rtl-llm/chisel-verilog-pairs · Datasets at Hugging Face

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Generate the Verilog code corresponding to the following Chisel files. File loop.scala: package boom.v3.ifu import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.{Field, Parameters} import freechips.rocketchip.diplomacy._ import freechips.rocketchip.tilelink._ import boom.v3.common._ import boom.v3.util.{BoomCoreStringPrefix} import scala.math.min case class BoomLoopPredictorParams( nWays: Int = 4, threshold: Int = 7 ) class LoopBranchPredictorBank(implicit p: Parameters) extends BranchPredictorBank()(p) { val tagSz = 10 override val nSets = 16 class LoopMeta extends Bundle { val s_cnt = UInt(10.W) } class LoopEntry extends Bundle { val tag = UInt(tagSz.W) val conf = UInt(3.W) val age = UInt(3.W) val p_cnt = UInt(10.W) val s_cnt = UInt(10.W) } class LoopBranchPredictorColumn extends Module { val io = IO(new Bundle { val f2_req_valid = Input(Bool()) val f2_req_idx = Input(UInt()) val f3_req_fire = Input(Bool()) val f3_pred_in = Input(Bool()) val f3_pred = Output(Bool()) val f3_meta = Output(new LoopMeta) val update_mispredict = Input(Bool()) val update_repair = Input(Bool()) val update_idx = Input(UInt()) val update_resolve_dir = Input(Bool()) val update_meta = Input(new LoopMeta) }) val doing_reset = RegInit(true.B) val reset_idx = RegInit(0.U(log2Ceil(nSets).W)) reset_idx := reset_idx + doing_reset when (reset_idx === (nSets-1).U) { doing_reset := false.B } val entries = Reg(Vec(nSets, new LoopEntry)) val f2_entry = WireInit(entries(io.f2_req_idx)) when (io.update_repair && io.update_idx === io.f2_req_idx) { f2_entry.s_cnt := io.update_meta.s_cnt } .elsewhen (io.update_mispredict && io.update_idx === io.f2_req_idx) { f2_entry.s_cnt := 0.U } val f3_entry = RegNext(f2_entry) val f3_scnt = Mux(io.update_repair && io.update_idx === RegNext(io.f2_req_idx), io.update_meta.s_cnt, f3_entry.s_cnt) val f3_tag = RegNext(io.f2_req_idx(tagSz+log2Ceil(nSets)-1,log2Ceil(nSets))) io.f3_pred := io.f3_pred_in io.f3_meta.s_cnt := f3_scnt when (f3_entry.tag === f3_tag) { when (f3_scnt === f3_entry.p_cnt && f3_entry.conf === 7.U) { io.f3_pred := !io.f3_pred_in } } val f4_fire = RegNext(io.f3_req_fire) val f4_entry = RegNext(f3_entry) val f4_tag = RegNext(f3_tag) val f4_scnt = RegNext(f3_scnt) val f4_idx = RegNext(RegNext(io.f2_req_idx)) when (f4_fire) { when (f4_entry.tag === f4_tag) { when (f4_scnt === f4_entry.p_cnt && f4_entry.conf === 7.U) { entries(f4_idx).age := 7.U entries(f4_idx).s_cnt := 0.U } .otherwise { entries(f4_idx).s_cnt := f4_scnt + 1.U entries(f4_idx).age := Mux(f4_entry.age === 7.U, 7.U, f4_entry.age + 1.U) } } } val entry = entries(io.update_idx) val tag = io.update_idx(tagSz+log2Ceil(nSets)-1,log2Ceil(nSets)) val tag_match = entry.tag === tag val ctr_match = entry.p_cnt === io.update_meta.s_cnt val wentry = WireInit(entry) when (io.update_mispredict && !doing_reset) { // Learned, tag match -> decrement confidence when (entry.conf === 7.U && tag_match) { wentry.s_cnt := 0.U wentry.conf := 0.U // Learned, no tag match -> do nothing? Don't evict super-confident entries? } .elsewhen (entry.conf === 7.U && !tag_match) { // Confident, tag match, ctr_match -> increment confidence, reset counter } .elsewhen (entry.conf =/= 0.U && tag_match && ctr_match) { wentry.conf := entry.conf + 1.U wentry.s_cnt := 0.U // Confident, tag match, no ctr match -> zero confidence, reset counter, set previous counter } .elsewhen (entry.conf =/= 0.U && tag_match && !ctr_match) { wentry.conf := 0.U wentry.s_cnt := 0.U wentry.p_cnt := io.update_meta.s_cnt // Confident, no tag match, age is 0 -> replace this entry with our own, set our age high to avoid ping-pong } .elsewhen (entry.conf =/= 0.U && !tag_match && entry.age === 0.U) { wentry.tag := tag wentry.conf := 1.U wentry.s_cnt := 0.U wentry.p_cnt := io.update_meta.s_cnt // Confident, no tag match, age > 0 -> decrement age } .elsewhen (entry.conf =/= 0.U && !tag_match && entry.age =/= 0.U) { wentry.age := entry.age - 1.U // Unconfident, tag match, ctr match -> increment confidence } .elsewhen (entry.conf === 0.U && tag_match && ctr_match) { wentry.conf := 1.U wentry.age := 7.U wentry.s_cnt := 0.U // Unconfident, tag match, no ctr match -> set previous counter } .elsewhen (entry.conf === 0.U && tag_match && !ctr_match) { wentry.p_cnt := io.update_meta.s_cnt wentry.age := 7.U wentry.s_cnt := 0.U // Unconfident, no tag match -> set previous counter and tag } .elsewhen (entry.conf === 0.U && !tag_match) { wentry.tag := tag wentry.conf := 1.U wentry.age := 7.U wentry.s_cnt := 0.U wentry.p_cnt := io.update_meta.s_cnt } entries(io.update_idx) := wentry } .elsewhen (io.update_repair && !doing_reset) { when (tag_match && !(f4_fire && io.update_idx === f4_idx)) { wentry.s_cnt := io.update_meta.s_cnt entries(io.update_idx) := wentry } } when (doing_reset) { entries(reset_idx) := (0.U).asTypeOf(new LoopEntry) } } val columns = Seq.fill(bankWidth) { Module(new LoopBranchPredictorColumn) } val mems = Nil // TODO fix val f3_meta = Wire(Vec(bankWidth, new LoopMeta)) override val metaSz = f3_meta.asUInt.getWidth val update_meta = s1_update.bits.meta.asTypeOf(Vec(bankWidth, new LoopMeta)) for (w <- 0 until bankWidth) { columns(w).io.f2_req_valid := s2_valid columns(w).io.f2_req_idx := s2_idx columns(w).io.f3_req_fire := (s3_valid && s3_mask(w) && io.f3_fire && RegNext(io.resp_in(0).f2(w).predicted_pc.valid && io.resp_in(0).f2(w).is_br)) columns(w).io.f3_pred_in := io.resp_in(0).f3(w).taken io.resp.f3(w).taken := columns(w).io.f3_pred columns(w).io.update_mispredict := (s1_update.valid && s1_update.bits.br_mask(w) && s1_update.bits.is_mispredict_update && s1_update.bits.cfi_mispredicted) columns(w).io.update_repair := (s1_update.valid && s1_update.bits.br_mask(w) && s1_update.bits.is_repair_update) columns(w).io.update_idx := s1_update_idx columns(w).io.update_resolve_dir := s1_update.bits.cfi_taken columns(w).io.update_meta := update_meta(w) f3_meta(w) := columns(w).io.f3_meta } io.f3_meta := f3_meta.asUInt } File predictor.scala: package boom.v3.ifu import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.{Field, Parameters} import freechips.rocketchip.diplomacy._ import freechips.rocketchip.tilelink._ import boom.v3.common._ import boom.v3.util.{BoomCoreStringPrefix} // A branch prediction for a single instruction class BranchPrediction(implicit p: Parameters) extends BoomBundle()(p) { // If this is a branch, do we take it? val taken = Bool() // Is this a branch? val is_br = Bool() // Is this a JAL? val is_jal = Bool() // What is the target of his branch/jump? Do we know the target? val predicted_pc = Valid(UInt(vaddrBitsExtended.W)) } // A branch prediction for a entire fetch-width worth of instructions // This is typically merged from individual predictions from the banked // predictor class BranchPredictionBundle(implicit p: Parameters) extends BoomBundle()(p) with HasBoomFrontendParameters { val pc = UInt(vaddrBitsExtended.W) val preds = Vec(fetchWidth, new BranchPrediction) val meta = Output(Vec(nBanks, UInt(bpdMaxMetaLength.W))) val lhist = Output(Vec(nBanks, UInt(localHistoryLength.W))) } // A branch update for a fetch-width worth of instructions class BranchPredictionUpdate(implicit p: Parameters) extends BoomBundle()(p) with HasBoomFrontendParameters { // Indicates that this update is due to a speculated misprediction // Local predictors typically update themselves with speculative info // Global predictors only care about non-speculative updates val is_mispredict_update = Bool() val is_repair_update = Bool() val btb_mispredicts = UInt(fetchWidth.W) def is_btb_mispredict_update = btb_mispredicts =/= 0.U def is_commit_update = !(is_mispredict_update \|\| is_repair_update \|\| is_btb_mispredict_update) val pc = UInt(vaddrBitsExtended.W) // Mask of instructions which are branches. // If these are not cfi_idx, then they were predicted not taken val br_mask = UInt(fetchWidth.W) // Which CFI was taken/mispredicted (if any) val cfi_idx = Valid(UInt(log2Ceil(fetchWidth).W)) // Was the cfi taken? val cfi_taken = Bool() // Was the cfi mispredicted from the original prediction? val cfi_mispredicted = Bool() // Was the cfi a br? val cfi_is_br = Bool() // Was the cfi a jal/jalr? val cfi_is_jal = Bool() // Was the cfi a jalr val cfi_is_jalr = Bool() //val cfi_is_ret = Bool() val ghist = new GlobalHistory val lhist = Vec(nBanks, UInt(localHistoryLength.W)) // What did this CFI jump to? val target = UInt(vaddrBitsExtended.W) val meta = Vec(nBanks, UInt(bpdMaxMetaLength.W)) } // A branch update to a single bank class BranchPredictionBankUpdate(implicit p: Parameters) extends BoomBundle()(p) with HasBoomFrontendParameters { val is_mispredict_update = Bool() val is_repair_update = Bool() val btb_mispredicts = UInt(bankWidth.W) def is_btb_mispredict_update = btb_mispredicts =/= 0.U def is_commit_update = !(is_mispredict_update \|\| is_repair_update \|\| is_btb_mispredict_update) val pc = UInt(vaddrBitsExtended.W) val br_mask = UInt(bankWidth.W) val cfi_idx = Valid(UInt(log2Ceil(bankWidth).W)) val cfi_taken = Bool() val cfi_mispredicted = Bool() val cfi_is_br = Bool() val cfi_is_jal = Bool() val cfi_is_jalr = Bool() val ghist = UInt(globalHistoryLength.W) val lhist = UInt(localHistoryLength.W) val target = UInt(vaddrBitsExtended.W) val meta = UInt(bpdMaxMetaLength.W) } class BranchPredictionRequest(implicit p: Parameters) extends BoomBundle()(p) { val pc = UInt(vaddrBitsExtended.W) val ghist = new GlobalHistory } class BranchPredictionBankResponse(implicit p: Parameters) extends BoomBundle()(p) with HasBoomFrontendParameters { val f1 = Vec(bankWidth, new BranchPrediction) val f2 = Vec(bankWidth, new BranchPrediction) val f3 = Vec(bankWidth, new BranchPrediction) } abstract class BranchPredictorBank(implicit p: Parameters) extends BoomModule()(p) with HasBoomFrontendParameters { val metaSz = 0 def nInputs = 1 val mems: Seq[Tuple3[String, Int, Int]] val io = IO(new Bundle { val f0_valid = Input(Bool()) val f0_pc = Input(UInt(vaddrBitsExtended.W)) val f0_mask = Input(UInt(bankWidth.W)) // Local history not available until end of f1 val f1_ghist = Input(UInt(globalHistoryLength.W)) val f1_lhist = Input(UInt(localHistoryLength.W)) val resp_in = Input(Vec(nInputs, new BranchPredictionBankResponse)) val resp = Output(new BranchPredictionBankResponse) // Store the meta as a UInt, use width inference to figure out the shape val f3_meta = Output(UInt(bpdMaxMetaLength.W)) val f3_fire = Input(Bool()) val update = Input(Valid(new BranchPredictionBankUpdate)) }) io.resp := io.resp_in(0) io.f3_meta := 0.U val s0_idx = fetchIdx(io.f0_pc) val s1_idx = RegNext(s0_idx) val s2_idx = RegNext(s1_idx) val s3_idx = RegNext(s2_idx) val s0_valid = io.f0_valid val s1_valid = RegNext(s0_valid) val s2_valid = RegNext(s1_valid) val s3_valid = RegNext(s2_valid) val s0_mask = io.f0_mask val s1_mask = RegNext(s0_mask) val s2_mask = RegNext(s1_mask) val s3_mask = RegNext(s2_mask) val s0_pc = io.f0_pc val s1_pc = RegNext(s0_pc) val s0_update = io.update val s0_update_idx = fetchIdx(io.update.bits.pc) val s0_update_valid = io.update.valid val s1_update = RegNext(s0_update) val s1_update_idx = RegNext(s0_update_idx) val s1_update_valid = RegNext(s0_update_valid) } class BranchPredictor(implicit p: Parameters) extends BoomModule()(p) with HasBoomFrontendParameters { val io = IO(new Bundle { // Requests and responses val f0_req = Input(Valid(new BranchPredictionRequest)) val resp = Output(new Bundle { val f1 = new BranchPredictionBundle val f2 = new BranchPredictionBundle val f3 = new BranchPredictionBundle }) val f3_fire = Input(Bool()) // Update val update = Input(Valid(new BranchPredictionUpdate)) }) var total_memsize = 0 val bpdStr = new StringBuilder bpdStr.append(BoomCoreStringPrefix("==Branch Predictor Memory Sizes==\n")) val banked_predictors = (0 until nBanks) map ( b => { val m = Module(if (useBPD) new ComposedBranchPredictorBank else new NullBranchPredictorBank) for ((n, d, w) <- m.mems) { bpdStr.append(BoomCoreStringPrefix(f"bank$b $n: $d x $w = ${d * w / 8}")) total_memsize = total_memsize + d * w / 8 } m }) bpdStr.append(BoomCoreStringPrefix(f"Total bpd size: ${total_memsize / 1024} KB\n")) override def toString: String = bpdStr.toString val banked_lhist_providers = Seq.fill(nBanks) { Module(if (localHistoryNSets > 0) new LocalBranchPredictorBank else new NullLocalBranchPredictorBank) } if (nBanks == 1) { banked_lhist_providers(0).io.f0_valid := io.f0_req.valid banked_lhist_providers(0).io.f0_pc := bankAlign(io.f0_req.bits.pc) banked_predictors(0).io.f0_valid := io.f0_req.valid banked_predictors(0).io.f0_pc := bankAlign(io.f0_req.bits.pc) banked_predictors(0).io.f0_mask := fetchMask(io.f0_req.bits.pc) banked_predictors(0).io.f1_ghist := RegNext(io.f0_req.bits.ghist.histories(0)) banked_predictors(0).io.f1_lhist := banked_lhist_providers(0).io.f1_lhist banked_predictors(0).io.resp_in(0) := (0.U).asTypeOf(new BranchPredictionBankResponse) } else { require(nBanks == 2) banked_predictors(0).io.resp_in(0) := (0.U).asTypeOf(new BranchPredictionBankResponse) banked_predictors(1).io.resp_in(0) := (0.U).asTypeOf(new BranchPredictionBankResponse) banked_predictors(0).io.f1_lhist := banked_lhist_providers(0).io.f1_lhist banked_predictors(1).io.f1_lhist := banked_lhist_providers(1).io.f1_lhist when (bank(io.f0_req.bits.pc) === 0.U) { banked_lhist_providers(0).io.f0_valid := io.f0_req.valid banked_lhist_providers(0).io.f0_pc := bankAlign(io.f0_req.bits.pc) banked_lhist_providers(1).io.f0_valid := io.f0_req.valid banked_lhist_providers(1).io.f0_pc := nextBank(io.f0_req.bits.pc) banked_predictors(0).io.f0_valid := io.f0_req.valid banked_predictors(0).io.f0_pc := bankAlign(io.f0_req.bits.pc) banked_predictors(0).io.f0_mask := fetchMask(io.f0_req.bits.pc) banked_predictors(1).io.f0_valid := io.f0_req.valid banked_predictors(1).io.f0_pc := nextBank(io.f0_req.bits.pc) banked_predictors(1).io.f0_mask := ~(0.U(bankWidth.W)) } .otherwise { banked_lhist_providers(0).io.f0_valid := io.f0_req.valid && !mayNotBeDualBanked(io.f0_req.bits.pc) banked_lhist_providers(0).io.f0_pc := nextBank(io.f0_req.bits.pc) banked_lhist_providers(1).io.f0_valid := io.f0_req.valid banked_lhist_providers(1).io.f0_pc := bankAlign(io.f0_req.bits.pc) banked_predictors(0).io.f0_valid := io.f0_req.valid && !mayNotBeDualBanked(io.f0_req.bits.pc) banked_predictors(0).io.f0_pc := nextBank(io.f0_req.bits.pc) banked_predictors(0).io.f0_mask := ~(0.U(bankWidth.W)) banked_predictors(1).io.f0_valid := io.f0_req.valid banked_predictors(1).io.f0_pc := bankAlign(io.f0_req.bits.pc) banked_predictors(1).io.f0_mask := fetchMask(io.f0_req.bits.pc) } when (RegNext(bank(io.f0_req.bits.pc) === 0.U)) { banked_predictors(0).io.f1_ghist := RegNext(io.f0_req.bits.ghist.histories(0)) banked_predictors(1).io.f1_ghist := RegNext(io.f0_req.bits.ghist.histories(1)) } .otherwise { banked_predictors(0).io.f1_ghist := RegNext(io.f0_req.bits.ghist.histories(1)) banked_predictors(1).io.f1_ghist := RegNext(io.f0_req.bits.ghist.histories(0)) } } for (i <- 0 until nBanks) { banked_lhist_providers(i).io.f3_taken_br := banked_predictors(i).io.resp.f3.map ( p => p.is_br && p.predicted_pc.valid && p.taken ).reduce(_\|\|_) } if (nBanks == 1) { io.resp.f1.preds := banked_predictors(0).io.resp.f1 io.resp.f2.preds := banked_predictors(0).io.resp.f2 io.resp.f3.preds := banked_predictors(0).io.resp.f3 io.resp.f3.meta(0) := banked_predictors(0).io.f3_meta io.resp.f3.lhist(0) := banked_lhist_providers(0).io.f3_lhist banked_predictors(0).io.f3_fire := io.f3_fire banked_lhist_providers(0).io.f3_fire := io.f3_fire } else { require(nBanks == 2) val b0_fire = io.f3_fire && RegNext(RegNext(RegNext(banked_predictors(0).io.f0_valid))) val b1_fire = io.f3_fire && RegNext(RegNext(RegNext(banked_predictors(1).io.f0_valid))) banked_predictors(0).io.f3_fire := b0_fire banked_predictors(1).io.f3_fire := b1_fire banked_lhist_providers(0).io.f3_fire := b0_fire banked_lhist_providers(1).io.f3_fire := b1_fire // The branch prediction metadata is stored un-shuffled io.resp.f3.meta(0) := banked_predictors(0).io.f3_meta io.resp.f3.meta(1) := banked_predictors(1).io.f3_meta io.resp.f3.lhist(0) := banked_lhist_providers(0).io.f3_lhist io.resp.f3.lhist(1) := banked_lhist_providers(1).io.f3_lhist when (bank(io.resp.f1.pc) === 0.U) { for (i <- 0 until bankWidth) { io.resp.f1.preds(i) := banked_predictors(0).io.resp.f1(i) io.resp.f1.preds(i+bankWidth) := banked_predictors(1).io.resp.f1(i) } } .otherwise { for (i <- 0 until bankWidth) { io.resp.f1.preds(i) := banked_predictors(1).io.resp.f1(i) io.resp.f1.preds(i+bankWidth) := banked_predictors(0).io.resp.f1(i) } } when (bank(io.resp.f2.pc) === 0.U) { for (i <- 0 until bankWidth) { io.resp.f2.preds(i) := banked_predictors(0).io.resp.f2(i) io.resp.f2.preds(i+bankWidth) := banked_predictors(1).io.resp.f2(i) } } .otherwise { for (i <- 0 until bankWidth) { io.resp.f2.preds(i) := banked_predictors(1).io.resp.f2(i) io.resp.f2.preds(i+bankWidth) := banked_predictors(0).io.resp.f2(i) } } when (bank(io.resp.f3.pc) === 0.U) { for (i <- 0 until bankWidth) { io.resp.f3.preds(i) := banked_predictors(0).io.resp.f3(i) io.resp.f3.preds(i+bankWidth) := banked_predictors(1).io.resp.f3(i) } } .otherwise { for (i <- 0 until bankWidth) { io.resp.f3.preds(i) := banked_predictors(1).io.resp.f3(i) io.resp.f3.preds(i+bankWidth) := banked_predictors(0).io.resp.f3(i) } } } io.resp.f1.pc := RegNext(io.f0_req.bits.pc) io.resp.f2.pc := RegNext(io.resp.f1.pc) io.resp.f3.pc := RegNext(io.resp.f2.pc) // We don't care about meta from the f1 and f2 resps // Use the meta from the latest resp io.resp.f1.meta := DontCare io.resp.f2.meta := DontCare io.resp.f1.lhist := DontCare io.resp.f2.lhist := DontCare for (i <- 0 until nBanks) { banked_predictors(i).io.update.bits.is_mispredict_update := io.update.bits.is_mispredict_update banked_predictors(i).io.update.bits.is_repair_update := io.update.bits.is_repair_update banked_predictors(i).io.update.bits.meta := io.update.bits.meta(i) banked_predictors(i).io.update.bits.lhist := io.update.bits.lhist(i) banked_predictors(i).io.update.bits.cfi_idx.bits := io.update.bits.cfi_idx.bits banked_predictors(i).io.update.bits.cfi_taken := io.update.bits.cfi_taken banked_predictors(i).io.update.bits.cfi_mispredicted := io.update.bits.cfi_mispredicted banked_predictors(i).io.update.bits.cfi_is_br := io.update.bits.cfi_is_br banked_predictors(i).io.update.bits.cfi_is_jal := io.update.bits.cfi_is_jal banked_predictors(i).io.update.bits.cfi_is_jalr := io.update.bits.cfi_is_jalr banked_predictors(i).io.update.bits.target := io.update.bits.target banked_lhist_providers(i).io.update.mispredict := io.update.bits.is_mispredict_update banked_lhist_providers(i).io.update.repair := io.update.bits.is_repair_update banked_lhist_providers(i).io.update.lhist := io.update.bits.lhist(i) } if (nBanks == 1) { banked_predictors(0).io.update.valid := io.update.valid banked_predictors(0).io.update.bits.pc := bankAlign(io.update.bits.pc) banked_predictors(0).io.update.bits.br_mask := io.update.bits.br_mask banked_predictors(0).io.update.bits.btb_mispredicts := io.update.bits.btb_mispredicts banked_predictors(0).io.update.bits.cfi_idx.valid := io.update.bits.cfi_idx.valid banked_predictors(0).io.update.bits.ghist := io.update.bits.ghist.histories(0) banked_lhist_providers(0).io.update.valid := io.update.valid && io.update.bits.br_mask =/= 0.U banked_lhist_providers(0).io.update.pc := bankAlign(io.update.bits.pc) } else { require(nBanks == 2) // Split the single update bundle for the fetchpacket into two updates // 1 for each bank. when (bank(io.update.bits.pc) === 0.U) { val b1_update_valid = io.update.valid && (!io.update.bits.cfi_idx.valid \|\| io.update.bits.cfi_idx.bits >= bankWidth.U) banked_lhist_providers(0).io.update.valid := io.update.valid && io.update.bits.br_mask(bankWidth-1,0) =/= 0.U banked_lhist_providers(1).io.update.valid := b1_update_valid && io.update.bits.br_mask(fetchWidth-1,bankWidth) =/= 0.U banked_lhist_providers(0).io.update.pc := bankAlign(io.update.bits.pc) banked_lhist_providers(1).io.update.pc := nextBank(io.update.bits.pc) banked_predictors(0).io.update.valid := io.update.valid banked_predictors(1).io.update.valid := b1_update_valid banked_predictors(0).io.update.bits.pc := bankAlign(io.update.bits.pc) banked_predictors(1).io.update.bits.pc := nextBank(io.update.bits.pc) banked_predictors(0).io.update.bits.br_mask := io.update.bits.br_mask banked_predictors(1).io.update.bits.br_mask := io.update.bits.br_mask >> bankWidth banked_predictors(0).io.update.bits.btb_mispredicts := io.update.bits.btb_mispredicts banked_predictors(1).io.update.bits.btb_mispredicts := io.update.bits.btb_mispredicts >> bankWidth banked_predictors(0).io.update.bits.cfi_idx.valid := io.update.bits.cfi_idx.valid && io.update.bits.cfi_idx.bits < bankWidth.U banked_predictors(1).io.update.bits.cfi_idx.valid := io.update.bits.cfi_idx.valid && io.update.bits.cfi_idx.bits >= bankWidth.U banked_predictors(0).io.update.bits.ghist := io.update.bits.ghist.histories(0) banked_predictors(1).io.update.bits.ghist := io.update.bits.ghist.histories(1) } .otherwise { val b0_update_valid = io.update.valid && !mayNotBeDualBanked(io.update.bits.pc) && (!io.update.bits.cfi_idx.valid \|\| io.update.bits.cfi_idx.bits >= bankWidth.U) banked_lhist_providers(1).io.update.valid := io.update.valid && io.update.bits.br_mask(bankWidth-1,0) =/= 0.U banked_lhist_providers(0).io.update.valid := b0_update_valid && io.update.bits.br_mask(fetchWidth-1,bankWidth) =/= 0.U banked_lhist_providers(1).io.update.pc := bankAlign(io.update.bits.pc) banked_lhist_providers(0).io.update.pc := nextBank(io.update.bits.pc) banked_predictors(1).io.update.valid := io.update.valid banked_predictors(0).io.update.valid := b0_update_valid banked_predictors(1).io.update.bits.pc := bankAlign(io.update.bits.pc) banked_predictors(0).io.update.bits.pc := nextBank(io.update.bits.pc) banked_predictors(1).io.update.bits.br_mask := io.update.bits.br_mask banked_predictors(0).io.update.bits.br_mask := io.update.bits.br_mask >> bankWidth banked_predictors(1).io.update.bits.btb_mispredicts := io.update.bits.btb_mispredicts banked_predictors(0).io.update.bits.btb_mispredicts := io.update.bits.btb_mispredicts >> bankWidth banked_predictors(1).io.update.bits.cfi_idx.valid := io.update.bits.cfi_idx.valid && io.update.bits.cfi_idx.bits < bankWidth.U banked_predictors(0).io.update.bits.cfi_idx.valid := io.update.bits.cfi_idx.valid && io.update.bits.cfi_idx.bits >= bankWidth.U banked_predictors(1).io.update.bits.ghist := io.update.bits.ghist.histories(0) banked_predictors(0).io.update.bits.ghist := io.update.bits.ghist.histories(1) } } when (io.update.valid) { when (io.update.bits.cfi_is_br && io.update.bits.cfi_idx.valid) { assert(io.update.bits.br_mask(io.update.bits.cfi_idx.bits)) } } } class NullBranchPredictorBank(implicit p: Parameters) extends BranchPredictorBank()(p) { val mems = Nil }	module LoopBranchPredictorBank( // @[loop.scala:20:7] input clock, // @[loop.scala:20:7] input reset, // @[loop.scala:20:7] input io_f0_valid, // @[predictor.scala:140:14] input [39:0] io_f0_pc, // @[predictor.scala:140:14] input [3:0] io_f0_mask, // @[predictor.scala:140:14] input [63:0] io_f1_ghist, // @[predictor.scala:140:14] input io_resp_in_0_f1_0_taken, // @[predictor.scala:140:14] input io_resp_in_0_f1_0_is_br, // @[predictor.scala:140:14] input io_resp_in_0_f1_0_is_jal, // @[predictor.scala:140:14] input io_resp_in_0_f1_0_predicted_pc_valid, // @[predictor.scala:140:14] input [39:0] io_resp_in_0_f1_0_predicted_pc_bits, // @[predictor.scala:140:14] input io_resp_in_0_f1_1_taken, // @[predictor.scala:140:14] input io_resp_in_0_f1_1_is_br, // @[predictor.scala:140:14] input io_resp_in_0_f1_1_is_jal, // @[predictor.scala:140:14] input io_resp_in_0_f1_1_predicted_pc_valid, // @[predictor.scala:140:14] input [39:0] io_resp_in_0_f1_1_predicted_pc_bits, // @[predictor.scala:140:14] input io_resp_in_0_f1_2_taken, // @[predictor.scala:140:14] input io_resp_in_0_f1_2_is_br, // @[predictor.scala:140:14] input io_resp_in_0_f1_2_is_jal, // @[predictor.scala:140:14] input io_resp_in_0_f1_2_predicted_pc_valid, // @[predictor.scala:140:14] input [39:0] io_resp_in_0_f1_2_predicted_pc_bits, // @[predictor.scala:140:14] input io_resp_in_0_f1_3_taken, // @[predictor.scala:140:14] input io_resp_in_0_f1_3_is_br, // @[predictor.scala:140:14] input io_resp_in_0_f1_3_is_jal, // @[predictor.scala:140:14] input io_resp_in_0_f1_3_predicted_pc_valid, // @[predictor.scala:140:14] input [39:0] io_resp_in_0_f1_3_predicted_pc_bits, // @[predictor.scala:140:14] input io_resp_in_0_f2_0_taken, // @[predictor.scala:140:14] input io_resp_in_0_f2_0_is_br, // @[predictor.scala:140:14] input io_resp_in_0_f2_0_is_jal, // @[predictor.scala:140:14] input io_resp_in_0_f2_0_predicted_pc_valid, // @[predictor.scala:140:14] input [39:0] io_resp_in_0_f2_0_predicted_pc_bits, // @[predictor.scala:140:14] input io_resp_in_0_f2_1_taken, // @[predictor.scala:140:14] input io_resp_in_0_f2_1_is_br, // @[predictor.scala:140:14] input io_resp_in_0_f2_1_is_jal, // @[predictor.scala:140:14] input io_resp_in_0_f2_1_predicted_pc_valid, // @[predictor.scala:140:14] input [39:0] io_resp_in_0_f2_1_predicted_pc_bits, // @[predictor.scala:140:14] input io_resp_in_0_f2_2_taken, // @[predictor.scala:140:14] input io_resp_in_0_f2_2_is_br, // @[predictor.scala:140:14] input io_resp_in_0_f2_2_is_jal, // @[predictor.scala:140:14] input io_resp_in_0_f2_2_predicted_pc_valid, // @[predictor.scala:140:14] input [39:0] io_resp_in_0_f2_2_predicted_pc_bits, // @[predictor.scala:140:14] input io_resp_in_0_f2_3_taken, // @[predictor.scala:140:14] input io_resp_in_0_f2_3_is_br, // @[predictor.scala:140:14] input io_resp_in_0_f2_3_is_jal, // @[predictor.scala:140:14] input io_resp_in_0_f2_3_predicted_pc_valid, // @[predictor.scala:140:14] input [39:0] io_resp_in_0_f2_3_predicted_pc_bits, // @[predictor.scala:140:14] input io_resp_in_0_f3_0_taken, // @[predictor.scala:140:14] input io_resp_in_0_f3_0_is_br, // @[predictor.scala:140:14] input io_resp_in_0_f3_0_is_jal, // @[predictor.scala:140:14] input io_resp_in_0_f3_0_predicted_pc_valid, // @[predictor.scala:140:14] input [39:0] io_resp_in_0_f3_0_predicted_pc_bits, // @[predictor.scala:140:14] input io_resp_in_0_f3_1_taken, // @[predictor.scala:140:14] input io_resp_in_0_f3_1_is_br, // @[predictor.scala:140:14] input io_resp_in_0_f3_1_is_jal, // @[predictor.scala:140:14] input io_resp_in_0_f3_1_predicted_pc_valid, // @[predictor.scala:140:14] input [39:0] io_resp_in_0_f3_1_predicted_pc_bits, // @[predictor.scala:140:14] input io_resp_in_0_f3_2_taken, // @[predictor.scala:140:14] input io_resp_in_0_f3_2_is_br, // @[predictor.scala:140:14] input io_resp_in_0_f3_2_is_jal, // @[predictor.scala:140:14] input io_resp_in_0_f3_2_predicted_pc_valid, // @[predictor.scala:140:14] input [39:0] io_resp_in_0_f3_2_predicted_pc_bits, // @[predictor.scala:140:14] input io_resp_in_0_f3_3_taken, // @[predictor.scala:140:14] input io_resp_in_0_f3_3_is_br, // @[predictor.scala:140:14] input io_resp_in_0_f3_3_is_jal, // @[predictor.scala:140:14] input io_resp_in_0_f3_3_predicted_pc_valid, // @[predictor.scala:140:14] input [39:0] io_resp_in_0_f3_3_predicted_pc_bits, // @[predictor.scala:140:14] output io_resp_f1_0_taken, // @[predictor.scala:140:14] output io_resp_f1_0_is_br, // @[predictor.scala:140:14] output io_resp_f1_0_is_jal, // @[predictor.scala:140:14] output io_resp_f1_0_predicted_pc_valid, // @[predictor.scala:140:14] output [39:0] io_resp_f1_0_predicted_pc_bits, // @[predictor.scala:140:14] output io_resp_f1_1_taken, // @[predictor.scala:140:14] output io_resp_f1_1_is_br, // @[predictor.scala:140:14] output io_resp_f1_1_is_jal, // @[predictor.scala:140:14] output io_resp_f1_1_predicted_pc_valid, // @[predictor.scala:140:14] output [39:0] io_resp_f1_1_predicted_pc_bits, // @[predictor.scala:140:14] output io_resp_f1_2_taken, // @[predictor.scala:140:14] output io_resp_f1_2_is_br, // @[predictor.scala:140:14] output io_resp_f1_2_is_jal, // @[predictor.scala:140:14] output io_resp_f1_2_predicted_pc_valid, // @[predictor.scala:140:14] output [39:0] io_resp_f1_2_predicted_pc_bits, // @[predictor.scala:140:14] output io_resp_f1_3_taken, // @[predictor.scala:140:14] output io_resp_f1_3_is_br, // @[predictor.scala:140:14] output io_resp_f1_3_is_jal, // @[predictor.scala:140:14] output io_resp_f1_3_predicted_pc_valid, // @[predictor.scala:140:14] output [39:0] io_resp_f1_3_predicted_pc_bits, // @[predictor.scala:140:14] output io_resp_f2_0_taken, // @[predictor.scala:140:14] output io_resp_f2_0_is_br, // @[predictor.scala:140:14] output io_resp_f2_0_is_jal, // @[predictor.scala:140:14] output io_resp_f2_0_predicted_pc_valid, // @[predictor.scala:140:14] output [39:0] io_resp_f2_0_predicted_pc_bits, // @[predictor.scala:140:14] output io_resp_f2_1_taken, // @[predictor.scala:140:14] output io_resp_f2_1_is_br, // @[predictor.scala:140:14] output io_resp_f2_1_is_jal, // @[predictor.scala:140:14] output io_resp_f2_1_predicted_pc_valid, // @[predictor.scala:140:14] output [39:0] io_resp_f2_1_predicted_pc_bits, // @[predictor.scala:140:14] output io_resp_f2_2_taken, // @[predictor.scala:140:14] output io_resp_f2_2_is_br, // @[predictor.scala:140:14] output io_resp_f2_2_is_jal, // @[predictor.scala:140:14] output io_resp_f2_2_predicted_pc_valid, // @[predictor.scala:140:14] output [39:0] io_resp_f2_2_predicted_pc_bits, // @[predictor.scala:140:14] output io_resp_f2_3_taken, // @[predictor.scala:140:14] output io_resp_f2_3_is_br, // @[predictor.scala:140:14] output io_resp_f2_3_is_jal, // @[predictor.scala:140:14] output io_resp_f2_3_predicted_pc_valid, // @[predictor.scala:140:14] output [39:0] io_resp_f2_3_predicted_pc_bits, // @[predictor.scala:140:14] output io_resp_f3_0_taken, // @[predictor.scala:140:14] output io_resp_f3_0_is_br, // @[predictor.scala:140:14] output io_resp_f3_0_is_jal, // @[predictor.scala:140:14] output io_resp_f3_0_predicted_pc_valid, // @[predictor.scala:140:14] output [39:0] io_resp_f3_0_predicted_pc_bits, // @[predictor.scala:140:14] output io_resp_f3_1_taken, // @[predictor.scala:140:14] output io_resp_f3_1_is_br, // @[predictor.scala:140:14] output io_resp_f3_1_is_jal, // @[predictor.scala:140:14] output io_resp_f3_1_predicted_pc_valid, // @[predictor.scala:140:14] output [39:0] io_resp_f3_1_predicted_pc_bits, // @[predictor.scala:140:14] output io_resp_f3_2_taken, // @[predictor.scala:140:14] output io_resp_f3_2_is_br, // @[predictor.scala:140:14] output io_resp_f3_2_is_jal, // @[predictor.scala:140:14] output io_resp_f3_2_predicted_pc_valid, // @[predictor.scala:140:14] output [39:0] io_resp_f3_2_predicted_pc_bits, // @[predictor.scala:140:14] output io_resp_f3_3_taken, // @[predictor.scala:140:14] output io_resp_f3_3_is_br, // @[predictor.scala:140:14] output io_resp_f3_3_is_jal, // @[predictor.scala:140:14] output io_resp_f3_3_predicted_pc_valid, // @[predictor.scala:140:14] output [39:0] io_resp_f3_3_predicted_pc_bits, // @[predictor.scala:140:14] output [119:0] io_f3_meta, // @[predictor.scala:140:14] input io_f3_fire, // @[predictor.scala:140:14] input io_update_valid, // @[predictor.scala:140:14] input io_update_bits_is_mispredict_update, // @[predictor.scala:140:14] input io_update_bits_is_repair_update, // @[predictor.scala:140:14] input [3:0] io_update_bits_btb_mispredicts, // @[predictor.scala:140:14] input [39:0] io_update_bits_pc, // @[predictor.scala:140:14] input [3:0] io_update_bits_br_mask, // @[predictor.scala:140:14] input io_update_bits_cfi_idx_valid, // @[predictor.scala:140:14] input [1:0] io_update_bits_cfi_idx_bits, // @[predictor.scala:140:14] input io_update_bits_cfi_taken, // @[predictor.scala:140:14] input io_update_bits_cfi_mispredicted, // @[predictor.scala:140:14] input io_update_bits_cfi_is_br, // @[predictor.scala:140:14] input io_update_bits_cfi_is_jal, // @[predictor.scala:140:14] input io_update_bits_cfi_is_jalr, // @[predictor.scala:140:14] input [63:0] io_update_bits_ghist, // @[predictor.scala:140:14] input io_update_bits_lhist, // @[predictor.scala:140:14] input [39:0] io_update_bits_target, // @[predictor.scala:140:14] input [119:0] io_update_bits_meta // @[predictor.scala:140:14] ); wire io_f0_valid_0 = io_f0_valid; // @[loop.scala:20:7] wire [39:0] io_f0_pc_0 = io_f0_pc; // @[loop.scala:20:7] wire [3:0] io_f0_mask_0 = io_f0_mask; // @[loop.scala:20:7] wire [63:0] io_f1_ghist_0 = io_f1_ghist; // @[loop.scala:20:7] wire io_resp_in_0_f1_0_taken_0 = io_resp_in_0_f1_0_taken; // @[loop.scala:20:7] wire io_resp_in_0_f1_0_is_br_0 = io_resp_in_0_f1_0_is_br; // @[loop.scala:20:7] wire io_resp_in_0_f1_0_is_jal_0 = io_resp_in_0_f1_0_is_jal; // @[loop.scala:20:7] wire io_resp_in_0_f1_0_predicted_pc_valid_0 = io_resp_in_0_f1_0_predicted_pc_valid; // @[loop.scala:20:7] wire [39:0] io_resp_in_0_f1_0_predicted_pc_bits_0 = io_resp_in_0_f1_0_predicted_pc_bits; // @[loop.scala:20:7] wire io_resp_in_0_f1_1_taken_0 = io_resp_in_0_f1_1_taken; // @[loop.scala:20:7] wire io_resp_in_0_f1_1_is_br_0 = io_resp_in_0_f1_1_is_br; // @[loop.scala:20:7] wire io_resp_in_0_f1_1_is_jal_0 = io_resp_in_0_f1_1_is_jal; // @[loop.scala:20:7] wire io_resp_in_0_f1_1_predicted_pc_valid_0 = io_resp_in_0_f1_1_predicted_pc_valid; // @[loop.scala:20:7] wire [39:0] io_resp_in_0_f1_1_predicted_pc_bits_0 = io_resp_in_0_f1_1_predicted_pc_bits; // @[loop.scala:20:7] wire io_resp_in_0_f1_2_taken_0 = io_resp_in_0_f1_2_taken; // @[loop.scala:20:7] wire io_resp_in_0_f1_2_is_br_0 = io_resp_in_0_f1_2_is_br; // @[loop.scala:20:7] wire io_resp_in_0_f1_2_is_jal_0 = io_resp_in_0_f1_2_is_jal; // @[loop.scala:20:7] wire io_resp_in_0_f1_2_predicted_pc_valid_0 = io_resp_in_0_f1_2_predicted_pc_valid; // @[loop.scala:20:7] wire [39:0] io_resp_in_0_f1_2_predicted_pc_bits_0 = io_resp_in_0_f1_2_predicted_pc_bits; // @[loop.scala:20:7] wire io_resp_in_0_f1_3_taken_0 = io_resp_in_0_f1_3_taken; // @[loop.scala:20:7] wire io_resp_in_0_f1_3_is_br_0 = io_resp_in_0_f1_3_is_br; // @[loop.scala:20:7] wire io_resp_in_0_f1_3_is_jal_0 = io_resp_in_0_f1_3_is_jal; // @[loop.scala:20:7] wire io_resp_in_0_f1_3_predicted_pc_valid_0 = io_resp_in_0_f1_3_predicted_pc_valid; // @[loop.scala:20:7] wire [39:0] io_resp_in_0_f1_3_predicted_pc_bits_0 = io_resp_in_0_f1_3_predicted_pc_bits; // @[loop.scala:20:7] wire io_resp_in_0_f2_0_taken_0 = io_resp_in_0_f2_0_taken; // @[loop.scala:20:7] wire io_resp_in_0_f2_0_is_br_0 = io_resp_in_0_f2_0_is_br; // @[loop.scala:20:7] wire io_resp_in_0_f2_0_is_jal_0 = io_resp_in_0_f2_0_is_jal; // @[loop.scala:20:7] wire io_resp_in_0_f2_0_predicted_pc_valid_0 = io_resp_in_0_f2_0_predicted_pc_valid; // @[loop.scala:20:7] wire [39:0] io_resp_in_0_f2_0_predicted_pc_bits_0 = io_resp_in_0_f2_0_predicted_pc_bits; // @[loop.scala:20:7] wire io_resp_in_0_f2_1_taken_0 = io_resp_in_0_f2_1_taken; // @[loop.scala:20:7] wire io_resp_in_0_f2_1_is_br_0 = io_resp_in_0_f2_1_is_br; // @[loop.scala:20:7] wire io_resp_in_0_f2_1_is_jal_0 = io_resp_in_0_f2_1_is_jal; // @[loop.scala:20:7] wire io_resp_in_0_f2_1_predicted_pc_valid_0 = io_resp_in_0_f2_1_predicted_pc_valid; // @[loop.scala:20:7] wire [39:0] io_resp_in_0_f2_1_predicted_pc_bits_0 = io_resp_in_0_f2_1_predicted_pc_bits; // @[loop.scala:20:7] wire io_resp_in_0_f2_2_taken_0 = io_resp_in_0_f2_2_taken; // @[loop.scala:20:7] wire io_resp_in_0_f2_2_is_br_0 = io_resp_in_0_f2_2_is_br; // @[loop.scala:20:7] wire io_resp_in_0_f2_2_is_jal_0 = io_resp_in_0_f2_2_is_jal; // @[loop.scala:20:7] wire io_resp_in_0_f2_2_predicted_pc_valid_0 = io_resp_in_0_f2_2_predicted_pc_valid; // @[loop.scala:20:7] wire [39:0] io_resp_in_0_f2_2_predicted_pc_bits_0 = io_resp_in_0_f2_2_predicted_pc_bits; // @[loop.scala:20:7] wire io_resp_in_0_f2_3_taken_0 = io_resp_in_0_f2_3_taken; // @[loop.scala:20:7] wire io_resp_in_0_f2_3_is_br_0 = io_resp_in_0_f2_3_is_br; // @[loop.scala:20:7] wire io_resp_in_0_f2_3_is_jal_0 = io_resp_in_0_f2_3_is_jal; // @[loop.scala:20:7] wire io_resp_in_0_f2_3_predicted_pc_valid_0 = io_resp_in_0_f2_3_predicted_pc_valid; // @[loop.scala:20:7] wire [39:0] io_resp_in_0_f2_3_predicted_pc_bits_0 = io_resp_in_0_f2_3_predicted_pc_bits; // @[loop.scala:20:7] wire io_resp_in_0_f3_0_taken_0 = io_resp_in_0_f3_0_taken; // @[loop.scala:20:7] wire io_resp_in_0_f3_0_is_br_0 = io_resp_in_0_f3_0_is_br; // @[loop.scala:20:7] wire io_resp_in_0_f3_0_is_jal_0 = io_resp_in_0_f3_0_is_jal; // @[loop.scala:20:7] wire io_resp_in_0_f3_0_predicted_pc_valid_0 = io_resp_in_0_f3_0_predicted_pc_valid; // @[loop.scala:20:7] wire [39:0] io_resp_in_0_f3_0_predicted_pc_bits_0 = io_resp_in_0_f3_0_predicted_pc_bits; // @[loop.scala:20:7] wire io_resp_in_0_f3_1_taken_0 = io_resp_in_0_f3_1_taken; // @[loop.scala:20:7] wire io_resp_in_0_f3_1_is_br_0 = io_resp_in_0_f3_1_is_br; // @[loop.scala:20:7] wire io_resp_in_0_f3_1_is_jal_0 = io_resp_in_0_f3_1_is_jal; // @[loop.scala:20:7] wire io_resp_in_0_f3_1_predicted_pc_valid_0 = io_resp_in_0_f3_1_predicted_pc_valid; // @[loop.scala:20:7] wire [39:0] io_resp_in_0_f3_1_predicted_pc_bits_0 = io_resp_in_0_f3_1_predicted_pc_bits; // @[loop.scala:20:7] wire io_resp_in_0_f3_2_taken_0 = io_resp_in_0_f3_2_taken; // @[loop.scala:20:7] wire io_resp_in_0_f3_2_is_br_0 = io_resp_in_0_f3_2_is_br; // @[loop.scala:20:7] wire io_resp_in_0_f3_2_is_jal_0 = io_resp_in_0_f3_2_is_jal; // @[loop.scala:20:7] wire io_resp_in_0_f3_2_predicted_pc_valid_0 = io_resp_in_0_f3_2_predicted_pc_valid; // @[loop.scala:20:7] wire [39:0] io_resp_in_0_f3_2_predicted_pc_bits_0 = io_resp_in_0_f3_2_predicted_pc_bits; // @[loop.scala:20:7] wire io_resp_in_0_f3_3_taken_0 = io_resp_in_0_f3_3_taken; // @[loop.scala:20:7] wire io_resp_in_0_f3_3_is_br_0 = io_resp_in_0_f3_3_is_br; // @[loop.scala:20:7] wire io_resp_in_0_f3_3_is_jal_0 = io_resp_in_0_f3_3_is_jal; // @[loop.scala:20:7] wire io_resp_in_0_f3_3_predicted_pc_valid_0 = io_resp_in_0_f3_3_predicted_pc_valid; // @[loop.scala:20:7] wire [39:0] io_resp_in_0_f3_3_predicted_pc_bits_0 = io_resp_in_0_f3_3_predicted_pc_bits; // @[loop.scala:20:7] wire io_f3_fire_0 = io_f3_fire; // @[loop.scala:20:7] wire io_update_valid_0 = io_update_valid; // @[loop.scala:20:7] wire io_update_bits_is_mispredict_update_0 = io_update_bits_is_mispredict_update; // @[loop.scala:20:7] wire io_update_bits_is_repair_update_0 = io_update_bits_is_repair_update; // @[loop.scala:20:7] wire [3:0] io_update_bits_btb_mispredicts_0 = io_update_bits_btb_mispredicts; // @[loop.scala:20:7] wire [39:0] io_update_bits_pc_0 = io_update_bits_pc; // @[loop.scala:20:7] wire [3:0] io_update_bits_br_mask_0 = io_update_bits_br_mask; // @[loop.scala:20:7] wire io_update_bits_cfi_idx_valid_0 = io_update_bits_cfi_idx_valid; // @[loop.scala:20:7] wire [1:0] io_update_bits_cfi_idx_bits_0 = io_update_bits_cfi_idx_bits; // @[loop.scala:20:7] wire io_update_bits_cfi_taken_0 = io_update_bits_cfi_taken; // @[loop.scala:20:7] wire io_update_bits_cfi_mispredicted_0 = io_update_bits_cfi_mispredicted; // @[loop.scala:20:7] wire io_update_bits_cfi_is_br_0 = io_update_bits_cfi_is_br; // @[loop.scala:20:7] wire io_update_bits_cfi_is_jal_0 = io_update_bits_cfi_is_jal; // @[loop.scala:20:7] wire io_update_bits_cfi_is_jalr_0 = io_update_bits_cfi_is_jalr; // @[loop.scala:20:7] wire [63:0] io_update_bits_ghist_0 = io_update_bits_ghist; // @[loop.scala:20:7] wire io_update_bits_lhist_0 = io_update_bits_lhist; // @[loop.scala:20:7] wire [39:0] io_update_bits_target_0 = io_update_bits_target; // @[loop.scala:20:7] wire [119:0] io_update_bits_meta_0 = io_update_bits_meta; // @[loop.scala:20:7] wire io_f1_lhist = 1'h0; // @[predictor.scala:140:14] wire io_resp_f1_0_taken_0 = io_resp_in_0_f1_0_taken_0; // @[loop.scala:20:7] wire io_resp_f1_0_is_br_0 = io_resp_in_0_f1_0_is_br_0; // @[loop.scala:20:7] wire io_resp_f1_0_is_jal_0 = io_resp_in_0_f1_0_is_jal_0; // @[loop.scala:20:7] wire io_resp_f1_0_predicted_pc_valid_0 = io_resp_in_0_f1_0_predicted_pc_valid_0; // @[loop.scala:20:7] wire [39:0] io_resp_f1_0_predicted_pc_bits_0 = io_resp_in_0_f1_0_predicted_pc_bits_0; // @[loop.scala:20:7] wire io_resp_f1_1_taken_0 = io_resp_in_0_f1_1_taken_0; // @[loop.scala:20:7] wire io_resp_f1_1_is_br_0 = io_resp_in_0_f1_1_is_br_0; // @[loop.scala:20:7] wire io_resp_f1_1_is_jal_0 = io_resp_in_0_f1_1_is_jal_0; // @[loop.scala:20:7] wire io_resp_f1_1_predicted_pc_valid_0 = io_resp_in_0_f1_1_predicted_pc_valid_0; // @[loop.scala:20:7] wire [39:0] io_resp_f1_1_predicted_pc_bits_0 = io_resp_in_0_f1_1_predicted_pc_bits_0; // @[loop.scala:20:7] wire io_resp_f1_2_taken_0 = io_resp_in_0_f1_2_taken_0; // @[loop.scala:20:7] wire io_resp_f1_2_is_br_0 = io_resp_in_0_f1_2_is_br_0; // @[loop.scala:20:7] wire io_resp_f1_2_is_jal_0 = io_resp_in_0_f1_2_is_jal_0; // @[loop.scala:20:7] wire io_resp_f1_2_predicted_pc_valid_0 = io_resp_in_0_f1_2_predicted_pc_valid_0; // @[loop.scala:20:7] wire [39:0] io_resp_f1_2_predicted_pc_bits_0 = io_resp_in_0_f1_2_predicted_pc_bits_0; // @[loop.scala:20:7] wire io_resp_f1_3_taken_0 = io_resp_in_0_f1_3_taken_0; // @[loop.scala:20:7] wire io_resp_f1_3_is_br_0 = io_resp_in_0_f1_3_is_br_0; // @[loop.scala:20:7] wire io_resp_f1_3_is_jal_0 = io_resp_in_0_f1_3_is_jal_0; // @[loop.scala:20:7] wire io_resp_f1_3_predicted_pc_valid_0 = io_resp_in_0_f1_3_predicted_pc_valid_0; // @[loop.scala:20:7] wire [39:0] io_resp_f1_3_predicted_pc_bits_0 = io_resp_in_0_f1_3_predicted_pc_bits_0; // @[loop.scala:20:7] wire io_resp_f2_0_taken_0 = io_resp_in_0_f2_0_taken_0; // @[loop.scala:20:7] wire io_resp_f2_0_is_br_0 = io_resp_in_0_f2_0_is_br_0; // @[loop.scala:20:7] wire io_resp_f2_0_is_jal_0 = io_resp_in_0_f2_0_is_jal_0; // @[loop.scala:20:7] wire io_resp_f2_0_predicted_pc_valid_0 = io_resp_in_0_f2_0_predicted_pc_valid_0; // @[loop.scala:20:7] wire [39:0] io_resp_f2_0_predicted_pc_bits_0 = io_resp_in_0_f2_0_predicted_pc_bits_0; // @[loop.scala:20:7] wire io_resp_f2_1_taken_0 = io_resp_in_0_f2_1_taken_0; // @[loop.scala:20:7] wire io_resp_f2_1_is_br_0 = io_resp_in_0_f2_1_is_br_0; // @[loop.scala:20:7] wire io_resp_f2_1_is_jal_0 = io_resp_in_0_f2_1_is_jal_0; // @[loop.scala:20:7] wire io_resp_f2_1_predicted_pc_valid_0 = io_resp_in_0_f2_1_predicted_pc_valid_0; // @[loop.scala:20:7] wire [39:0] io_resp_f2_1_predicted_pc_bits_0 = io_resp_in_0_f2_1_predicted_pc_bits_0; // @[loop.scala:20:7] wire io_resp_f2_2_taken_0 = io_resp_in_0_f2_2_taken_0; // @[loop.scala:20:7] wire io_resp_f2_2_is_br_0 = io_resp_in_0_f2_2_is_br_0; // @[loop.scala:20:7] wire io_resp_f2_2_is_jal_0 = io_resp_in_0_f2_2_is_jal_0; // @[loop.scala:20:7] wire io_resp_f2_2_predicted_pc_valid_0 = io_resp_in_0_f2_2_predicted_pc_valid_0; // @[loop.scala:20:7] wire [39:0] io_resp_f2_2_predicted_pc_bits_0 = io_resp_in_0_f2_2_predicted_pc_bits_0; // @[loop.scala:20:7] wire io_resp_f2_3_taken_0 = io_resp_in_0_f2_3_taken_0; // @[loop.scala:20:7] wire io_resp_f2_3_is_br_0 = io_resp_in_0_f2_3_is_br_0; // @[loop.scala:20:7] wire io_resp_f2_3_is_jal_0 = io_resp_in_0_f2_3_is_jal_0; // @[loop.scala:20:7] wire io_resp_f2_3_predicted_pc_valid_0 = io_resp_in_0_f2_3_predicted_pc_valid_0; // @[loop.scala:20:7] wire [39:0] io_resp_f2_3_predicted_pc_bits_0 = io_resp_in_0_f2_3_predicted_pc_bits_0; // @[loop.scala:20:7] wire io_resp_f3_0_is_br_0 = io_resp_in_0_f3_0_is_br_0; // @[loop.scala:20:7] wire io_resp_f3_0_is_jal_0 = io_resp_in_0_f3_0_is_jal_0; // @[loop.scala:20:7] wire io_resp_f3_0_predicted_pc_valid_0 = io_resp_in_0_f3_0_predicted_pc_valid_0; // @[loop.scala:20:7] wire [39:0] io_resp_f3_0_predicted_pc_bits_0 = io_resp_in_0_f3_0_predicted_pc_bits_0; // @[loop.scala:20:7] wire io_resp_f3_1_is_br_0 = io_resp_in_0_f3_1_is_br_0; // @[loop.scala:20:7] wire io_resp_f3_1_is_jal_0 = io_resp_in_0_f3_1_is_jal_0; // @[loop.scala:20:7] wire io_resp_f3_1_predicted_pc_valid_0 = io_resp_in_0_f3_1_predicted_pc_valid_0; // @[loop.scala:20:7] wire [39:0] io_resp_f3_1_predicted_pc_bits_0 = io_resp_in_0_f3_1_predicted_pc_bits_0; // @[loop.scala:20:7] wire io_resp_f3_2_is_br_0 = io_resp_in_0_f3_2_is_br_0; // @[loop.scala:20:7] wire io_resp_f3_2_is_jal_0 = io_resp_in_0_f3_2_is_jal_0; // @[loop.scala:20:7] wire io_resp_f3_2_predicted_pc_valid_0 = io_resp_in_0_f3_2_predicted_pc_valid_0; // @[loop.scala:20:7] wire [39:0] io_resp_f3_2_predicted_pc_bits_0 = io_resp_in_0_f3_2_predicted_pc_bits_0; // @[loop.scala:20:7] wire io_resp_f3_3_is_br_0 = io_resp_in_0_f3_3_is_br_0; // @[loop.scala:20:7] wire io_resp_f3_3_is_jal_0 = io_resp_in_0_f3_3_is_jal_0; // @[loop.scala:20:7] wire io_resp_f3_3_predicted_pc_valid_0 = io_resp_in_0_f3_3_predicted_pc_valid_0; // @[loop.scala:20:7] wire [39:0] io_resp_f3_3_predicted_pc_bits_0 = io_resp_in_0_f3_3_predicted_pc_bits_0; // @[loop.scala:20:7] wire io_resp_f3_0_taken_0; // @[loop.scala:20:7] wire io_resp_f3_1_taken_0; // @[loop.scala:20:7] wire io_resp_f3_2_taken_0; // @[loop.scala:20:7] wire io_resp_f3_3_taken_0; // @[loop.scala:20:7] wire [119:0] io_f3_meta_0; // @[loop.scala:20:7] wire [35:0] s0_idx = io_f0_pc_0[39:4]; // @[frontend.scala:162:35] reg [35:0] s1_idx; // @[predictor.scala:163:29] reg [35:0] s2_idx; // @[predictor.scala:164:29] reg [35:0] s3_idx; // @[predictor.scala:165:29] reg s1_valid; // @[predictor.scala:168:25] reg s2_valid; // @[predictor.scala:169:25] reg s3_valid; // @[predictor.scala:170:25] reg [3:0] s1_mask; // @[predictor.scala:173:24] reg [3:0] s2_mask; // @[predictor.scala:174:24] reg [3:0] s3_mask; // @[predictor.scala:175:24] reg [39:0] s1_pc; // @[predictor.scala:178:22] wire [35:0] s0_update_idx = io_update_bits_pc_0[39:4]; // @[frontend.scala:162:35] reg s1_update_valid; // @[predictor.scala:184:30] reg s1_update_bits_is_mispredict_update; // @[predictor.scala:184:30] reg s1_update_bits_is_repair_update; // @[predictor.scala:184:30] reg [3:0] s1_update_bits_btb_mispredicts; // @[predictor.scala:184:30] reg [39:0] s1_update_bits_pc; // @[predictor.scala:184:30] reg [3:0] s1_update_bits_br_mask; // @[predictor.scala:184:30] reg s1_update_bits_cfi_idx_valid; // @[predictor.scala:184:30] reg [1:0] s1_update_bits_cfi_idx_bits; // @[predictor.scala:184:30] reg s1_update_bits_cfi_taken; // @[predictor.scala:184:30] reg s1_update_bits_cfi_mispredicted; // @[predictor.scala:184:30] reg s1_update_bits_cfi_is_br; // @[predictor.scala:184:30] reg s1_update_bits_cfi_is_jal; // @[predictor.scala:184:30] reg s1_update_bits_cfi_is_jalr; // @[predictor.scala:184:30] reg [63:0] s1_update_bits_ghist; // @[predictor.scala:184:30] reg s1_update_bits_lhist; // @[predictor.scala:184:30] reg [39:0] s1_update_bits_target; // @[predictor.scala:184:30] reg [119:0] s1_update_bits_meta; // @[predictor.scala:184:30] reg [35:0] s1_update_idx; // @[predictor.scala:185:30] reg s1_update_valid_0; // @[predictor.scala:186:32] wire [9:0] f3_meta_0_s_cnt; // @[loop.scala:184:21] wire [9:0] f3_meta_1_s_cnt; // @[loop.scala:184:21] wire [9:0] f3_meta_2_s_cnt; // @[loop.scala:184:21] wire [9:0] f3_meta_3_s_cnt; // @[loop.scala:184:21] wire [19:0] _GEN = {f3_meta_1_s_cnt, f3_meta_0_s_cnt}; // @[loop.scala:184:21, :185:33] wire [19:0] lo; // @[loop.scala:185:33] assign lo = _GEN; // @[loop.scala:185:33] wire [19:0] io_f3_meta_lo; // @[loop.scala:212:25] assign io_f3_meta_lo = _GEN; // @[loop.scala:185:33, :212:25] wire [19:0] _GEN_0 = {f3_meta_3_s_cnt, f3_meta_2_s_cnt}; // @[loop.scala:184:21, :185:33] wire [19:0] hi; // @[loop.scala:185:33] assign hi = _GEN_0; // @[loop.scala:185:33] wire [19:0] io_f3_meta_hi; // @[loop.scala:212:25] assign io_f3_meta_hi = _GEN_0; // @[loop.scala:185:33, :212:25] wire [9:0] _update_meta_T; // @[loop.scala:187:49] wire [9:0] _update_meta_T_1; // @[loop.scala:187:49] wire [9:0] _update_meta_T_2; // @[loop.scala:187:49] wire [9:0] _update_meta_T_3; // @[loop.scala:187:49] wire [9:0] update_meta_0_s_cnt; // @[loop.scala:187:49] wire [9:0] update_meta_1_s_cnt; // @[loop.scala:187:49] wire [9:0] update_meta_2_s_cnt; // @[loop.scala:187:49] wire [9:0] update_meta_3_s_cnt; // @[loop.scala:187:49] wire [39:0] _update_meta_WIRE = s1_update_bits_meta[39:0]; // @[predictor.scala:184:30] assign _update_meta_T = _update_meta_WIRE[9:0]; // @[loop.scala:187:49] assign update_meta_0_s_cnt = _update_meta_T; // @[loop.scala:187:49] assign _update_meta_T_1 = _update_meta_WIRE[19:10]; // @[loop.scala:187:49] assign update_meta_1_s_cnt = _update_meta_T_1; // @[loop.scala:187:49] assign _update_meta_T_2 = _update_meta_WIRE[29:20]; // @[loop.scala:187:49] assign update_meta_2_s_cnt = _update_meta_T_2; // @[loop.scala:187:49] assign _update_meta_T_3 = _update_meta_WIRE[39:30]; // @[loop.scala:187:49] assign update_meta_3_s_cnt = _update_meta_T_3; // @[loop.scala:187:49] wire _columns_0_io_f3_req_fire_T = s3_mask[0]; // @[predictor.scala:175:24] wire _columns_0_io_f3_req_fire_T_1 = s3_valid & _columns_0_io_f3_req_fire_T; // @[predictor.scala:170:25] wire _columns_0_io_f3_req_fire_T_2 = _columns_0_io_f3_req_fire_T_1 & io_f3_fire_0; // @[loop.scala:20:7, :192:{44,58}] wire _columns_0_io_f3_req_fire_T_3 = io_resp_in_0_f2_0_predicted_pc_valid_0 & io_resp_in_0_f2_0_is_br_0; // @[loop.scala:20:7, :193:54] reg columns_0_io_f3_req_fire_REG; // @[loop.scala:193:14] wire _columns_0_io_f3_req_fire_T_4 = _columns_0_io_f3_req_fire_T_2 & columns_0_io_f3_req_fire_REG; // @[loop.scala:192:{58,72}, :193:14] wire _columns_0_io_update_mispredict_T = s1_update_bits_br_mask[0]; // @[predictor.scala:184:30] wire _columns_0_io_update_repair_T = s1_update_bits_br_mask[0]; // @[predictor.scala:184:30] wire _columns_0_io_update_mispredict_T_1 = s1_update_valid & _columns_0_io_update_mispredict_T; // @[predictor.scala:184:30] wire _columns_0_io_update_mispredict_T_2 = _columns_0_io_update_mispredict_T_1 & s1_update_bits_is_mispredict_update; // @[predictor.scala:184:30] wire _columns_0_io_update_mispredict_T_3 = _columns_0_io_update_mispredict_T_2 & s1_update_bits_cfi_mispredicted; // @[predictor.scala:184:30] wire _columns_0_io_update_repair_T_1 = s1_update_valid & _columns_0_io_update_repair_T; // @[predictor.scala:184:30] wire _columns_0_io_update_repair_T_2 = _columns_0_io_update_repair_T_1 & s1_update_bits_is_repair_update; // @[predictor.scala:184:30] wire _columns_1_io_f3_req_fire_T = s3_mask[1]; // @[predictor.scala:175:24] wire _columns_1_io_f3_req_fire_T_1 = s3_valid & _columns_1_io_f3_req_fire_T; // @[predictor.scala:170:25] wire _columns_1_io_f3_req_fire_T_2 = _columns_1_io_f3_req_fire_T_1 & io_f3_fire_0; // @[loop.scala:20:7, :192:{44,58}] wire _columns_1_io_f3_req_fire_T_3 = io_resp_in_0_f2_1_predicted_pc_valid_0 & io_resp_in_0_f2_1_is_br_0; // @[loop.scala:20:7, :193:54] reg columns_1_io_f3_req_fire_REG; // @[loop.scala:193:14] wire _columns_1_io_f3_req_fire_T_4 = _columns_1_io_f3_req_fire_T_2 & columns_1_io_f3_req_fire_REG; // @[loop.scala:192:{58,72}, :193:14] wire _columns_1_io_update_mispredict_T = s1_update_bits_br_mask[1]; // @[predictor.scala:184:30] wire _columns_1_io_update_repair_T = s1_update_bits_br_mask[1]; // @[predictor.scala:184:30] wire _columns_1_io_update_mispredict_T_1 = s1_update_valid & _columns_1_io_update_mispredict_T; // @[predictor.scala:184:30] wire _columns_1_io_update_mispredict_T_2 = _columns_1_io_update_mispredict_T_1 & s1_update_bits_is_mispredict_update; // @[predictor.scala:184:30] wire _columns_1_io_update_mispredict_T_3 = _columns_1_io_update_mispredict_T_2 & s1_update_bits_cfi_mispredicted; // @[predictor.scala:184:30] wire _columns_1_io_update_repair_T_1 = s1_update_valid & _columns_1_io_update_repair_T; // @[predictor.scala:184:30] wire _columns_1_io_update_repair_T_2 = _columns_1_io_update_repair_T_1 & s1_update_bits_is_repair_update; // @[predictor.scala:184:30] wire _columns_2_io_f3_req_fire_T = s3_mask[2]; // @[predictor.scala:175:24] wire _columns_2_io_f3_req_fire_T_1 = s3_valid & _columns_2_io_f3_req_fire_T; // @[predictor.scala:170:25] wire _columns_2_io_f3_req_fire_T_2 = _columns_2_io_f3_req_fire_T_1 & io_f3_fire_0; // @[loop.scala:20:7, :192:{44,58}] wire _columns_2_io_f3_req_fire_T_3 = io_resp_in_0_f2_2_predicted_pc_valid_0 & io_resp_in_0_f2_2_is_br_0; // @[loop.scala:20:7, :193:54] reg columns_2_io_f3_req_fire_REG; // @[loop.scala:193:14] wire _columns_2_io_f3_req_fire_T_4 = _columns_2_io_f3_req_fire_T_2 & columns_2_io_f3_req_fire_REG; // @[loop.scala:192:{58,72}, :193:14] wire _columns_2_io_update_mispredict_T = s1_update_bits_br_mask[2]; // @[predictor.scala:184:30] wire _columns_2_io_update_repair_T = s1_update_bits_br_mask[2]; // @[predictor.scala:184:30] wire _columns_2_io_update_mispredict_T_1 = s1_update_valid & _columns_2_io_update_mispredict_T; // @[predictor.scala:184:30] wire _columns_2_io_update_mispredict_T_2 = _columns_2_io_update_mispredict_T_1 & s1_update_bits_is_mispredict_update; // @[predictor.scala:184:30] wire _columns_2_io_update_mispredict_T_3 = _columns_2_io_update_mispredict_T_2 & s1_update_bits_cfi_mispredicted; // @[predictor.scala:184:30] wire _columns_2_io_update_repair_T_1 = s1_update_valid & _columns_2_io_update_repair_T; // @[predictor.scala:184:30] wire _columns_2_io_update_repair_T_2 = _columns_2_io_update_repair_T_1 & s1_update_bits_is_repair_update; // @[predictor.scala:184:30] wire _columns_3_io_f3_req_fire_T = s3_mask[3]; // @[predictor.scala:175:24] wire _columns_3_io_f3_req_fire_T_1 = s3_valid & _columns_3_io_f3_req_fire_T; // @[predictor.scala:170:25] wire _columns_3_io_f3_req_fire_T_2 = _columns_3_io_f3_req_fire_T_1 & io_f3_fire_0; // @[loop.scala:20:7, :192:{44,58}] wire _columns_3_io_f3_req_fire_T_3 = io_resp_in_0_f2_3_predicted_pc_valid_0 & io_resp_in_0_f2_3_is_br_0; // @[loop.scala:20:7, :193:54] reg columns_3_io_f3_req_fire_REG; // @[loop.scala:193:14] wire _columns_3_io_f3_req_fire_T_4 = _columns_3_io_f3_req_fire_T_2 & columns_3_io_f3_req_fire_REG; // @[loop.scala:192:{58,72}, :193:14] wire _columns_3_io_update_mispredict_T = s1_update_bits_br_mask[3]; // @[predictor.scala:184:30] wire _columns_3_io_update_repair_T = s1_update_bits_br_mask[3]; // @[predictor.scala:184:30] wire _columns_3_io_update_mispredict_T_1 = s1_update_valid & _columns_3_io_update_mispredict_T; // @[predictor.scala:184:30] wire _columns_3_io_update_mispredict_T_2 = _columns_3_io_update_mispredict_T_1 & s1_update_bits_is_mispredict_update; // @[predictor.scala:184:30] wire _columns_3_io_update_mispredict_T_3 = _columns_3_io_update_mispredict_T_2 & s1_update_bits_cfi_mispredicted; // @[predictor.scala:184:30] wire _columns_3_io_update_repair_T_1 = s1_update_valid & _columns_3_io_update_repair_T; // @[predictor.scala:184:30] wire _columns_3_io_update_repair_T_2 = _columns_3_io_update_repair_T_1 & s1_update_bits_is_repair_update; // @[predictor.scala:184:30] wire [39:0] _io_f3_meta_T = {io_f3_meta_hi, io_f3_meta_lo}; // @[loop.scala:212:25] assign io_f3_meta_0 = {80'h0, _io_f3_meta_T}; // @[loop.scala:20:7, :212:{14,25}] always @(posedge clock) begin // @[loop.scala:20:7] s1_idx <= s0_idx; // @[frontend.scala:162:35] s2_idx <= s1_idx; // @[predictor.scala:163:29, :164:29] s3_idx <= s2_idx; // @[predictor.scala:164:29, :165:29] s1_valid <= io_f0_valid_0; // @[predictor.scala:168:25] s2_valid <= s1_valid; // @[predictor.scala:168:25, :169:25] s3_valid <= s2_valid; // @[predictor.scala:169:25, :170:25] s1_mask <= io_f0_mask_0; // @[predictor.scala:173:24] s2_mask <= s1_mask; // @[predictor.scala:173:24, :174:24] s3_mask <= s2_mask; // @[predictor.scala:174:24, :175:24] s1_pc <= io_f0_pc_0; // @[predictor.scala:178:22] s1_update_valid <= io_update_valid_0; // @[predictor.scala:184:30] s1_update_bits_is_mispredict_update <= io_update_bits_is_mispredict_update_0; // @[predictor.scala:184:30] s1_update_bits_is_repair_update <= io_update_bits_is_repair_update_0; // @[predictor.scala:184:30] s1_update_bits_btb_mispredicts <= io_update_bits_btb_mispredicts_0; // @[predictor.scala:184:30] s1_update_bits_pc <= io_update_bits_pc_0; // @[predictor.scala:184:30] s1_update_bits_br_mask <= io_update_bits_br_mask_0; // @[predictor.scala:184:30] s1_update_bits_cfi_idx_valid <= io_update_bits_cfi_idx_valid_0; // @[predictor.scala:184:30] s1_update_bits_cfi_idx_bits <= io_update_bits_cfi_idx_bits_0; // @[predictor.scala:184:30] s1_update_bits_cfi_taken <= io_update_bits_cfi_taken_0; // @[predictor.scala:184:30] s1_update_bits_cfi_mispredicted <= io_update_bits_cfi_mispredicted_0; // @[predictor.scala:184:30] s1_update_bits_cfi_is_br <= io_update_bits_cfi_is_br_0; // @[predictor.scala:184:30] s1_update_bits_cfi_is_jal <= io_update_bits_cfi_is_jal_0; // @[predictor.scala:184:30] s1_update_bits_cfi_is_jalr <= io_update_bits_cfi_is_jalr_0; // @[predictor.scala:184:30] s1_update_bits_ghist <= io_update_bits_ghist_0; // @[predictor.scala:184:30] s1_update_bits_lhist <= io_update_bits_lhist_0; // @[predictor.scala:184:30] s1_update_bits_target <= io_update_bits_target_0; // @[predictor.scala:184:30] s1_update_bits_meta <= io_update_bits_meta_0; // @[predictor.scala:184:30] s1_update_idx <= s0_update_idx; // @[frontend.scala:162:35] s1_update_valid_0 <= io_update_valid_0; // @[predictor.scala:186:32] columns_0_io_f3_req_fire_REG <= _columns_0_io_f3_req_fire_T_3; // @[loop.scala:193:{14,54}] columns_1_io_f3_req_fire_REG <= _columns_1_io_f3_req_fire_T_3; // @[loop.scala:193:{14,54}] columns_2_io_f3_req_fire_REG <= _columns_2_io_f3_req_fire_T_3; // @[loop.scala:193:{14,54}] columns_3_io_f3_req_fire_REG <= _columns_3_io_f3_req_fire_T_3; // @[loop.scala:193:{14,54}] always @(posedge) LoopBranchPredictorColumn columns_0 ( // @[loop.scala:182:45] .clock (clock), .reset (reset), .io_f2_req_valid (s2_valid), // @[predictor.scala:169:25] .io_f2_req_idx (s2_idx), // @[predictor.scala:164:29] .io_f3_req_fire (_columns_0_io_f3_req_fire_T_4), // @[loop.scala:192:72] .io_f3_pred_in (io_resp_in_0_f3_0_taken_0), // @[loop.scala:20:7] .io_f3_pred (io_resp_f3_0_taken_0), .io_f3_meta_s_cnt (f3_meta_0_s_cnt), .io_update_mispredict (_columns_0_io_update_mispredict_T_3), // @[loop.scala:200:82] .io_update_repair (_columns_0_io_update_repair_T_2), // @[loop.scala:203:72] .io_update_idx (s1_update_idx), // @[predictor.scala:185:30] .io_update_resolve_dir (s1_update_bits_cfi_taken), // @[predictor.scala:184:30] .io_update_meta_s_cnt (update_meta_0_s_cnt) // @[loop.scala:187:49] ); // @[loop.scala:182:45] LoopBranchPredictorColumn_1 columns_1 ( // @[loop.scala:182:45] .clock (clock), .reset (reset), .io_f2_req_valid (s2_valid), // @[predictor.scala:169:25] .io_f2_req_idx (s2_idx), // @[predictor.scala:164:29] .io_f3_req_fire (_columns_1_io_f3_req_fire_T_4), // @[loop.scala:192:72] .io_f3_pred_in (io_resp_in_0_f3_1_taken_0), // @[loop.scala:20:7] .io_f3_pred (io_resp_f3_1_taken_0), .io_f3_meta_s_cnt (f3_meta_1_s_cnt), .io_update_mispredict (_columns_1_io_update_mispredict_T_3), // @[loop.scala:200:82] .io_update_repair (_columns_1_io_update_repair_T_2), // @[loop.scala:203:72] .io_update_idx (s1_update_idx), // @[predictor.scala:185:30] .io_update_resolve_dir (s1_update_bits_cfi_taken), // @[predictor.scala:184:30] .io_update_meta_s_cnt (update_meta_1_s_cnt) // @[loop.scala:187:49] ); // @[loop.scala:182:45] LoopBranchPredictorColumn_2 columns_2 ( // @[loop.scala:182:45] .clock (clock), .reset (reset), .io_f2_req_valid (s2_valid), // @[predictor.scala:169:25] .io_f2_req_idx (s2_idx), // @[predictor.scala:164:29] .io_f3_req_fire (_columns_2_io_f3_req_fire_T_4), // @[loop.scala:192:72] .io_f3_pred_in (io_resp_in_0_f3_2_taken_0), // @[loop.scala:20:7] .io_f3_pred (io_resp_f3_2_taken_0), .io_f3_meta_s_cnt (f3_meta_2_s_cnt), .io_update_mispredict (_columns_2_io_update_mispredict_T_3), // @[loop.scala:200:82] .io_update_repair (_columns_2_io_update_repair_T_2), // @[loop.scala:203:72] .io_update_idx (s1_update_idx), // @[predictor.scala:185:30] .io_update_resolve_dir (s1_update_bits_cfi_taken), // @[predictor.scala:184:30] .io_update_meta_s_cnt (update_meta_2_s_cnt) // @[loop.scala:187:49] ); // @[loop.scala:182:45] LoopBranchPredictorColumn_3 columns_3 ( // @[loop.scala:182:45] .clock (clock), .reset (reset), .io_f2_req_valid (s2_valid), // @[predictor.scala:169:25] .io_f2_req_idx (s2_idx), // @[predictor.scala:164:29] .io_f3_req_fire (_columns_3_io_f3_req_fire_T_4), // @[loop.scala:192:72] .io_f3_pred_in (io_resp_in_0_f3_3_taken_0), // @[loop.scala:20:7] .io_f3_pred (io_resp_f3_3_taken_0), .io_f3_meta_s_cnt (f3_meta_3_s_cnt), .io_update_mispredict (_columns_3_io_update_mispredict_T_3), // @[loop.scala:200:82] .io_update_repair (_columns_3_io_update_repair_T_2), // @[loop.scala:203:72] .io_update_idx (s1_update_idx), // @[predictor.scala:185:30] .io_update_resolve_dir (s1_update_bits_cfi_taken), // @[predictor.scala:184:30] .io_update_meta_s_cnt (update_meta_3_s_cnt) // @[loop.scala:187:49] ); // @[loop.scala:182:45] assign io_resp_f1_0_taken = io_resp_f1_0_taken_0; // @[loop.scala:20:7] assign io_resp_f1_0_is_br = io_resp_f1_0_is_br_0; // @[loop.scala:20:7] assign io_resp_f1_0_is_jal = io_resp_f1_0_is_jal_0; // @[loop.scala:20:7] assign io_resp_f1_0_predicted_pc_valid = io_resp_f1_0_predicted_pc_valid_0; // @[loop.scala:20:7] assign io_resp_f1_0_predicted_pc_bits = io_resp_f1_0_predicted_pc_bits_0; // @[loop.scala:20:7] assign io_resp_f1_1_taken = io_resp_f1_1_taken_0; // @[loop.scala:20:7] assign io_resp_f1_1_is_br = io_resp_f1_1_is_br_0; // @[loop.scala:20:7] assign io_resp_f1_1_is_jal = io_resp_f1_1_is_jal_0; // @[loop.scala:20:7] assign io_resp_f1_1_predicted_pc_valid = io_resp_f1_1_predicted_pc_valid_0; // @[loop.scala:20:7] assign io_resp_f1_1_predicted_pc_bits = io_resp_f1_1_predicted_pc_bits_0; // @[loop.scala:20:7] assign io_resp_f1_2_taken = io_resp_f1_2_taken_0; // @[loop.scala:20:7] assign io_resp_f1_2_is_br = io_resp_f1_2_is_br_0; // @[loop.scala:20:7] assign io_resp_f1_2_is_jal = io_resp_f1_2_is_jal_0; // @[loop.scala:20:7] assign io_resp_f1_2_predicted_pc_valid = io_resp_f1_2_predicted_pc_valid_0; // @[loop.scala:20:7] assign io_resp_f1_2_predicted_pc_bits = io_resp_f1_2_predicted_pc_bits_0; // @[loop.scala:20:7] assign io_resp_f1_3_taken = io_resp_f1_3_taken_0; // @[loop.scala:20:7] assign io_resp_f1_3_is_br = io_resp_f1_3_is_br_0; // @[loop.scala:20:7] assign io_resp_f1_3_is_jal = io_resp_f1_3_is_jal_0; // @[loop.scala:20:7] assign io_resp_f1_3_predicted_pc_valid = io_resp_f1_3_predicted_pc_valid_0; // @[loop.scala:20:7] assign io_resp_f1_3_predicted_pc_bits = io_resp_f1_3_predicted_pc_bits_0; // @[loop.scala:20:7] assign io_resp_f2_0_taken = io_resp_f2_0_taken_0; // @[loop.scala:20:7] assign io_resp_f2_0_is_br = io_resp_f2_0_is_br_0; // @[loop.scala:20:7] assign io_resp_f2_0_is_jal = io_resp_f2_0_is_jal_0; // @[loop.scala:20:7] assign io_resp_f2_0_predicted_pc_valid = io_resp_f2_0_predicted_pc_valid_0; // @[loop.scala:20:7] assign io_resp_f2_0_predicted_pc_bits = io_resp_f2_0_predicted_pc_bits_0; // @[loop.scala:20:7] assign io_resp_f2_1_taken = io_resp_f2_1_taken_0; // @[loop.scala:20:7] assign io_resp_f2_1_is_br = io_resp_f2_1_is_br_0; // @[loop.scala:20:7] assign io_resp_f2_1_is_jal = io_resp_f2_1_is_jal_0; // @[loop.scala:20:7] assign io_resp_f2_1_predicted_pc_valid = io_resp_f2_1_predicted_pc_valid_0; // @[loop.scala:20:7] assign io_resp_f2_1_predicted_pc_bits = io_resp_f2_1_predicted_pc_bits_0; // @[loop.scala:20:7] assign io_resp_f2_2_taken = io_resp_f2_2_taken_0; // @[loop.scala:20:7] assign io_resp_f2_2_is_br = io_resp_f2_2_is_br_0; // @[loop.scala:20:7] assign io_resp_f2_2_is_jal = io_resp_f2_2_is_jal_0; // @[loop.scala:20:7] assign io_resp_f2_2_predicted_pc_valid = io_resp_f2_2_predicted_pc_valid_0; // @[loop.scala:20:7] assign io_resp_f2_2_predicted_pc_bits = io_resp_f2_2_predicted_pc_bits_0; // @[loop.scala:20:7] assign io_resp_f2_3_taken = io_resp_f2_3_taken_0; // @[loop.scala:20:7] assign io_resp_f2_3_is_br = io_resp_f2_3_is_br_0; // @[loop.scala:20:7] assign io_resp_f2_3_is_jal = io_resp_f2_3_is_jal_0; // @[loop.scala:20:7] assign io_resp_f2_3_predicted_pc_valid = io_resp_f2_3_predicted_pc_valid_0; // @[loop.scala:20:7] assign io_resp_f2_3_predicted_pc_bits = io_resp_f2_3_predicted_pc_bits_0; // @[loop.scala:20:7] assign io_resp_f3_0_taken = io_resp_f3_0_taken_0; // @[loop.scala:20:7] assign io_resp_f3_0_is_br = io_resp_f3_0_is_br_0; // @[loop.scala:20:7] assign io_resp_f3_0_is_jal = io_resp_f3_0_is_jal_0; // @[loop.scala:20:7] assign io_resp_f3_0_predicted_pc_valid = io_resp_f3_0_predicted_pc_valid_0; // @[loop.scala:20:7] assign io_resp_f3_0_predicted_pc_bits = io_resp_f3_0_predicted_pc_bits_0; // @[loop.scala:20:7] assign io_resp_f3_1_taken = io_resp_f3_1_taken_0; // @[loop.scala:20:7] assign io_resp_f3_1_is_br = io_resp_f3_1_is_br_0; // @[loop.scala:20:7] assign io_resp_f3_1_is_jal = io_resp_f3_1_is_jal_0; // @[loop.scala:20:7] assign io_resp_f3_1_predicted_pc_valid = io_resp_f3_1_predicted_pc_valid_0; // @[loop.scala:20:7] assign io_resp_f3_1_predicted_pc_bits = io_resp_f3_1_predicted_pc_bits_0; // @[loop.scala:20:7] assign io_resp_f3_2_taken = io_resp_f3_2_taken_0; // @[loop.scala:20:7] assign io_resp_f3_2_is_br = io_resp_f3_2_is_br_0; // @[loop.scala:20:7] assign io_resp_f3_2_is_jal = io_resp_f3_2_is_jal_0; // @[loop.scala:20:7] assign io_resp_f3_2_predicted_pc_valid = io_resp_f3_2_predicted_pc_valid_0; // @[loop.scala:20:7] assign io_resp_f3_2_predicted_pc_bits = io_resp_f3_2_predicted_pc_bits_0; // @[loop.scala:20:7] assign io_resp_f3_3_taken = io_resp_f3_3_taken_0; // @[loop.scala:20:7] assign io_resp_f3_3_is_br = io_resp_f3_3_is_br_0; // @[loop.scala:20:7] assign io_resp_f3_3_is_jal = io_resp_f3_3_is_jal_0; // @[loop.scala:20:7] assign io_resp_f3_3_predicted_pc_valid = io_resp_f3_3_predicted_pc_valid_0; // @[loop.scala:20:7] assign io_resp_f3_3_predicted_pc_bits = io_resp_f3_3_predicted_pc_bits_0; // @[loop.scala:20:7] assign io_f3_meta = io_f3_meta_0; // @[loop.scala:20:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File TilelinkAdapters.scala: package constellation.protocol import chisel3._ import chisel3.util._ import constellation.channel._ import constellation.noc._ import constellation.soc.{CanAttachToGlobalNoC} import org.chipsalliance.cde.config._ import freechips.rocketchip.diplomacy._ import freechips.rocketchip.util._ import freechips.rocketchip.tilelink._ import scala.collection.immutable.{ListMap} abstract class TLChannelToNoC[T <: TLChannel](gen: => T, edge: TLEdge, idToEgress: Int => Int)(implicit val p: Parameters) extends Module with TLFieldHelper { val flitWidth = minTLPayloadWidth(gen) val io = IO(new Bundle { val protocol = Flipped(Decoupled(gen)) val flit = Decoupled(new IngressFlit(flitWidth)) }) def unique(x: Vector[Boolean]): Bool = (x.filter(x=>x).size <= 1).B // convert decoupled to irrevocable val q = Module(new Queue(gen, 1, pipe=true, flow=true)) val protocol = q.io.deq val has_body = Wire(Bool()) val body_fields = getBodyFields(protocol.bits) val const_fields = getConstFields(protocol.bits) val head = edge.first(protocol.bits, protocol.fire) val tail = edge.last(protocol.bits, protocol.fire) def requestOH: Seq[Bool] val body = Cat( body_fields.filter(_.getWidth > 0).map(_.asUInt)) val const = Cat(const_fields.filter(_.getWidth > 0).map(_.asUInt)) val is_body = RegInit(false.B) io.flit.valid := protocol.valid protocol.ready := io.flit.ready && (is_body \|\| !has_body) io.flit.bits.head := head && !is_body io.flit.bits.tail := tail && (is_body \|\| !has_body) io.flit.bits.egress_id := Mux1H(requestOH.zipWithIndex.map { case (r, i) => r -> idToEgress(i).U }) io.flit.bits.payload := Mux(is_body, body, const) when (io.flit.fire && io.flit.bits.head) { is_body := true.B } when (io.flit.fire && io.flit.bits.tail) { is_body := false.B } } abstract class TLChannelFromNoC[T <: TLChannel](gen: => T)(implicit val p: Parameters) extends Module with TLFieldHelper { val flitWidth = minTLPayloadWidth(gen) val io = IO(new Bundle { val protocol = Decoupled(gen) val flit = Flipped(Decoupled(new EgressFlit(flitWidth))) }) // Handle size = 1 gracefully (Chisel3 empty range is broken) def trim(id: UInt, size: Int): UInt = if (size <= 1) 0.U else id(log2Ceil(size)-1, 0) val protocol = Wire(Decoupled(gen)) val body_fields = getBodyFields(protocol.bits) val const_fields = getConstFields(protocol.bits) val is_const = RegInit(true.B) val const_reg = Reg(UInt(const_fields.map(_.getWidth).sum.W)) val const = Mux(io.flit.bits.head, io.flit.bits.payload, const_reg) io.flit.ready := (is_const && !io.flit.bits.tail) \|\| protocol.ready protocol.valid := (!is_const \|\| io.flit.bits.tail) && io.flit.valid def assign(i: UInt, sigs: Seq[Data]) = { var t = i for (s <- sigs.reverse) { s := t.asTypeOf(s.cloneType) t = t >> s.getWidth } } assign(const, const_fields) assign(io.flit.bits.payload, body_fields) when (io.flit.fire && io.flit.bits.head) { is_const := false.B; const_reg := io.flit.bits.payload } when (io.flit.fire && io.flit.bits.tail) { is_const := true.B } } trait HasAddressDecoder { // Filter a list to only those elements selected def filter[T](data: Seq[T], mask: Seq[Boolean]) = (data zip mask).filter(_._2).map(_._1) val edgeIn: TLEdge val edgesOut: Seq[TLEdge] lazy val reacheableIO = edgesOut.map { mp => edgeIn.client.clients.exists { c => mp.manager.managers.exists { m => c.visibility.exists { ca => m.address.exists { ma => ca.overlaps(ma) }} }} }.toVector lazy val releaseIO = (edgesOut zip reacheableIO).map { case (mp, reachable) => reachable && edgeIn.client.anySupportProbe && mp.manager.anySupportAcquireB }.toVector def outputPortFn(connectIO: Seq[Boolean]) = { val port_addrs = edgesOut.map(_.manager.managers.flatMap(_.address)) val routingMask = AddressDecoder(filter(port_addrs, connectIO)) val route_addrs = port_addrs.map(seq => AddressSet.unify(seq.map(_.widen(~routingMask)).distinct)) route_addrs.map(seq => (addr: UInt) => seq.map(_.contains(addr)).reduce(_\|\|_)) } } class TLAToNoC( val edgeIn: TLEdge, val edgesOut: Seq[TLEdge], bundle: TLBundleParameters, slaveToAEgress: Int => Int, sourceStart: Int )(implicit p: Parameters) extends TLChannelToNoC(new TLBundleA(bundle), edgeIn, slaveToAEgress)(p) with HasAddressDecoder { has_body := edgeIn.hasData(protocol.bits) \|\| (~protocol.bits.mask =/= 0.U) lazy val connectAIO = reacheableIO lazy val requestOH = outputPortFn(connectAIO).zipWithIndex.map { case (o, j) => connectAIO(j).B && (unique(connectAIO) \|\| o(protocol.bits.address)) } q.io.enq <> io.protocol q.io.enq.bits.source := io.protocol.bits.source \| sourceStart.U } class TLAFromNoC(edgeOut: TLEdge, bundle: TLBundleParameters)(implicit p: Parameters) extends TLChannelFromNoC(new TLBundleA(bundle))(p) { io.protocol <> protocol when (io.flit.bits.head) { io.protocol.bits.mask := ~(0.U(io.protocol.bits.mask.getWidth.W)) } } class TLBToNoC( edgeOut: TLEdge, edgesIn: Seq[TLEdge], bundle: TLBundleParameters, masterToBIngress: Int => Int )(implicit p: Parameters) extends TLChannelToNoC(new TLBundleB(bundle), edgeOut, masterToBIngress)(p) { has_body := edgeOut.hasData(protocol.bits) \|\| (~protocol.bits.mask =/= 0.U) lazy val inputIdRanges = TLXbar.mapInputIds(edgesIn.map(_.client)) lazy val requestOH = inputIdRanges.map { i => i.contains(protocol.bits.source) } q.io.enq <> io.protocol } class TLBFromNoC(edgeIn: TLEdge, bundle: TLBundleParameters, sourceSize: Int)(implicit p: Parameters) extends TLChannelFromNoC(new TLBundleB(bundle))(p) { io.protocol <> protocol io.protocol.bits.source := trim(protocol.bits.source, sourceSize) when (io.flit.bits.head) { io.protocol.bits.mask := ~(0.U(io.protocol.bits.mask.getWidth.W)) } } class TLCToNoC( val edgeIn: TLEdge, val edgesOut: Seq[TLEdge], bundle: TLBundleParameters, slaveToCEgress: Int => Int, sourceStart: Int )(implicit p: Parameters) extends TLChannelToNoC(new TLBundleC(bundle), edgeIn, slaveToCEgress)(p) with HasAddressDecoder { has_body := edgeIn.hasData(protocol.bits) lazy val connectCIO = releaseIO lazy val requestOH = outputPortFn(connectCIO).zipWithIndex.map { case (o, j) => connectCIO(j).B && (unique(connectCIO) \|\| o(protocol.bits.address)) } q.io.enq <> io.protocol q.io.enq.bits.source := io.protocol.bits.source \| sourceStart.U } class TLCFromNoC(edgeOut: TLEdge, bundle: TLBundleParameters)(implicit p: Parameters) extends TLChannelFromNoC(new TLBundleC(bundle))(p) { io.protocol <> protocol } class TLDToNoC( edgeOut: TLEdge, edgesIn: Seq[TLEdge], bundle: TLBundleParameters, masterToDIngress: Int => Int, sourceStart: Int )(implicit p: Parameters) extends TLChannelToNoC(new TLBundleD(bundle), edgeOut, masterToDIngress)(p) { has_body := edgeOut.hasData(protocol.bits) lazy val inputIdRanges = TLXbar.mapInputIds(edgesIn.map(_.client)) lazy val requestOH = inputIdRanges.map { i => i.contains(protocol.bits.source) } q.io.enq <> io.protocol q.io.enq.bits.sink := io.protocol.bits.sink \| sourceStart.U } class TLDFromNoC(edgeIn: TLEdge, bundle: TLBundleParameters, sourceSize: Int)(implicit p: Parameters) extends TLChannelFromNoC(new TLBundleD(bundle))(p) { io.protocol <> protocol io.protocol.bits.source := trim(protocol.bits.source, sourceSize) } class TLEToNoC( val edgeIn: TLEdge, val edgesOut: Seq[TLEdge], bundle: TLBundleParameters, slaveToEEgress: Int => Int )(implicit p: Parameters) extends TLChannelToNoC(new TLBundleE(bundle), edgeIn, slaveToEEgress)(p) { has_body := edgeIn.hasData(protocol.bits) lazy val outputIdRanges = TLXbar.mapOutputIds(edgesOut.map(_.manager)) lazy val requestOH = outputIdRanges.map { o => o.contains(protocol.bits.sink) } q.io.enq <> io.protocol } class TLEFromNoC(edgeOut: TLEdge, bundle: TLBundleParameters, sourceSize: Int)(implicit p: Parameters) extends TLChannelFromNoC(new TLBundleE(bundle))(p) { io.protocol <> protocol io.protocol.bits.sink := trim(protocol.bits.sink, sourceSize) } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportPutFull \|\| manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB \|\| manager.anySupportGet \|\| manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportPutFull \|\| client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe \|\| client.anySupportGet \|\| client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet \|\| client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull \|\| client.anySupportPutPartial \|\| client.anySupportHint \|\| client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet \|\| manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull \|\| manager.anySupportPutPartial \|\| manager.anySupportHint \|\| manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) \|\| !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.ProbeAckData \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode \| small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U \|\| beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }	module TLCToNoC_5( // @[TilelinkAdapters.scala:151:7] input clock, // @[TilelinkAdapters.scala:151:7] input reset, // @[TilelinkAdapters.scala:151:7] output io_protocol_ready, // @[TilelinkAdapters.scala:19:14] input io_protocol_valid, // @[TilelinkAdapters.scala:19:14] input [2:0] io_protocol_bits_opcode, // @[TilelinkAdapters.scala:19:14] input [2:0] io_protocol_bits_param, // @[TilelinkAdapters.scala:19:14] input [3:0] io_protocol_bits_size, // @[TilelinkAdapters.scala:19:14] input [6:0] io_protocol_bits_source, // @[TilelinkAdapters.scala:19:14] input [31:0] io_protocol_bits_address, // @[TilelinkAdapters.scala:19:14] input [127:0] io_protocol_bits_data, // @[TilelinkAdapters.scala:19:14] input io_protocol_bits_corrupt, // @[TilelinkAdapters.scala:19:14] input io_flit_ready, // @[TilelinkAdapters.scala:19:14] output io_flit_valid, // @[TilelinkAdapters.scala:19:14] output io_flit_bits_head, // @[TilelinkAdapters.scala:19:14] output io_flit_bits_tail, // @[TilelinkAdapters.scala:19:14] output [128:0] io_flit_bits_payload, // @[TilelinkAdapters.scala:19:14] output [4:0] io_flit_bits_egress_id // @[TilelinkAdapters.scala:19:14] ); wire _q_io_deq_valid; // @[TilelinkAdapters.scala:26:17] wire [2:0] _q_io_deq_bits_opcode; // @[TilelinkAdapters.scala:26:17] wire [2:0] _q_io_deq_bits_param; // @[TilelinkAdapters.scala:26:17] wire [3:0] _q_io_deq_bits_size; // @[TilelinkAdapters.scala:26:17] wire [6:0] _q_io_deq_bits_source; // @[TilelinkAdapters.scala:26:17] wire [31:0] _q_io_deq_bits_address; // @[TilelinkAdapters.scala:26:17] wire [127:0] _q_io_deq_bits_data; // @[TilelinkAdapters.scala:26:17] wire _q_io_deq_bits_corrupt; // @[TilelinkAdapters.scala:26:17] wire [26:0] _tail_beats1_decode_T = 27'hFFF << _q_io_deq_bits_size; // @[package.scala:243:71] reg [7:0] head_counter; // @[Edges.scala:229:27] wire head = head_counter == 8'h0; // @[Edges.scala:229:27, :231:25] wire [7:0] tail_beats1 = _q_io_deq_bits_opcode[0] ? ~(_tail_beats1_decode_T[11:4]) : 8'h0; // @[package.scala:243:{46,71,76}] reg [7:0] tail_counter; // @[Edges.scala:229:27] reg is_body; // @[TilelinkAdapters.scala:39:24] wire q_io_deq_ready = io_flit_ready & (is_body \| ~(_q_io_deq_bits_opcode[0])); // @[Edges.scala:102:36] wire io_flit_bits_head_0 = head & ~is_body; // @[Edges.scala:231:25] wire io_flit_bits_tail_0 = (tail_counter == 8'h1 \| tail_beats1 == 8'h0) & (is_body \| ~(_q_io_deq_bits_opcode[0])); // @[Edges.scala:102:36, :221:14, :229:27, :232:{25,33,43}] wire _GEN = io_flit_ready & _q_io_deq_valid; // @[Decoupled.scala:51:35] always @(posedge clock) begin // @[TilelinkAdapters.scala:151:7] if (reset) begin // @[TilelinkAdapters.scala:151:7] head_counter <= 8'h0; // @[Edges.scala:229:27] tail_counter <= 8'h0; // @[Edges.scala:229:27] is_body <= 1'h0; // @[TilelinkAdapters.scala:39:24, :151:7] end else begin // @[TilelinkAdapters.scala:151:7] if (q_io_deq_ready & _q_io_deq_valid) begin // @[Decoupled.scala:51:35] head_counter <= head ? (_q_io_deq_bits_opcode[0] ? ~(_tail_beats1_decode_T[11:4]) : 8'h0) : head_counter - 8'h1; // @[package.scala:243:{46,71,76}] tail_counter <= tail_counter == 8'h0 ? tail_beats1 : tail_counter - 8'h1; // @[Edges.scala:221:14, :229:27, :230:28, :231:25, :236:21] end is_body <= ~(_GEN & io_flit_bits_tail_0) & (_GEN & io_flit_bits_head_0 \| is_body); // @[Decoupled.scala:51:35] end always @(posedge)
Generate the Verilog code corresponding to the following Chisel files. File DescribedSRAM.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3.{Data, SyncReadMem, Vec} import chisel3.util.log2Ceil object DescribedSRAM { def apply[T <: Data]( name: String, desc: String, size: BigInt, // depth data: T ): SyncReadMem[T] = { val mem = SyncReadMem(size, data) mem.suggestName(name) val granWidth = data match { case v: Vec[_] => v.head.getWidth case d => d.getWidth } val uid = 0 Annotated.srams( component = mem, name = name, address_width = log2Ceil(size), data_width = data.getWidth, depth = size, description = desc, write_mask_granularity = granWidth ) mem } }	module dataArrayB1Way_5( // @[DescribedSRAM.scala:17:26] input [7:0] RW0_addr, input RW0_en, input RW0_clk, input RW0_wmode, input [63:0] RW0_wdata, output [63:0] RW0_rdata ); dataArrayB0Way_0_ext dataArrayB0Way_0_ext ( // @[DescribedSRAM.scala:17:26] .RW0_addr (RW0_addr), .RW0_en (RW0_en), .RW0_clk (RW0_clk), .RW0_wmode (RW0_wmode), .RW0_wdata (RW0_wdata), .RW0_rdata (RW0_rdata) ); // @[DescribedSRAM.scala:17:26] endmodule
Generate the Verilog code corresponding to the following Chisel files. File ShiftReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ // Similar to the Chisel ShiftRegister but allows the user to suggest a // name to the registers that get instantiated, and // to provide a reset value. object ShiftRegInit { def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T = (0 until n).foldRight(in) { case (i, next) => { val r = RegNext(next, init) name.foreach { na => r.suggestName(s"${na}_${i}") } r } } } /** These wrap behavioral * shift registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * The different types vary in their reset behavior: * AsyncResetShiftReg -- Asynchronously reset register array * A W(width) x D(depth) sized array is constructed from D instantiations of a * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg, * but only used for timing applications */ abstract class AbstractPipelineReg(w: Int = 1) extends Module { val io = IO(new Bundle { val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) } ) } object AbstractPipelineReg { def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = { val chain = Module(gen) name.foreach{ chain.suggestName(_) } chain.io.d := in.asUInt chain.io.q.asTypeOf(in) } } class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) { require(depth > 0, "Depth must be greater than 0.") override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}" val chain = List.tabulate(depth) { i => Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}") } chain.last.io.d := io.d chain.last.io.en := true.B (chain.init zip chain.tail).foreach { case (sink, source) => sink.io.d := source.io.q sink.io.en := true.B } io.q := chain.head.io.q } object AsyncResetShiftReg { def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name) def apply [T <: Data](in: T, depth: Int, name: Option[String]): T = apply(in, depth, 0, name) def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T = apply(in, depth, init.litValue.toInt, name) def apply [T <: Data](in: T, depth: Int, init: T): T = apply (in, depth, init.litValue.toInt, None) } File AsyncQueue.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ case class AsyncQueueParams( depth: Int = 8, sync: Int = 3, safe: Boolean = true, // If safe is true, then effort is made to resynchronize the crossing indices when either side is reset. // This makes it safe/possible to reset one side of the crossing (but not the other) when the queue is empty. narrow: Boolean = false) // If narrow is true then the read mux is moved to the source side of the crossing. // This reduces the number of level shifters in the case where the clock crossing is also a voltage crossing, // at the expense of a combinational path from the sink to the source and back to the sink. { require (depth > 0 && isPow2(depth)) require (sync >= 2) val bits = log2Ceil(depth) val wires = if (narrow) 1 else depth } object AsyncQueueParams { // When there is only one entry, we don't need narrow. def singleton(sync: Int = 3, safe: Boolean = true) = AsyncQueueParams(1, sync, safe, false) } class AsyncBundleSafety extends Bundle { val ridx_valid = Input (Bool()) val widx_valid = Output(Bool()) val source_reset_n = Output(Bool()) val sink_reset_n = Input (Bool()) } class AsyncBundle[T <: Data](private val gen: T, val params: AsyncQueueParams = AsyncQueueParams()) extends Bundle { // Data-path synchronization val mem = Output(Vec(params.wires, gen)) val ridx = Input (UInt((params.bits+1).W)) val widx = Output(UInt((params.bits+1).W)) val index = params.narrow.option(Input(UInt(params.bits.W))) // Signals used to self-stabilize a safe AsyncQueue val safe = params.safe.option(new AsyncBundleSafety) } object GrayCounter { def apply(bits: Int, increment: Bool = true.B, clear: Bool = false.B, name: String = "binary"): UInt = { val incremented = Wire(UInt(bits.W)) val binary = RegNext(next=incremented, init=0.U).suggestName(name) incremented := Mux(clear, 0.U, binary + increment.asUInt) incremented ^ (incremented >> 1) } } class AsyncValidSync(sync: Int, desc: String) extends RawModule { val io = IO(new Bundle { val in = Input(Bool()) val out = Output(Bool()) }) val clock = IO(Input(Clock())) val reset = IO(Input(AsyncReset())) withClockAndReset(clock, reset){ io.out := AsyncResetSynchronizerShiftReg(io.in, sync, Some(desc)) } } class AsyncQueueSource[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module { override def desiredName = s"AsyncQueueSource_${gen.typeName}" val io = IO(new Bundle { // These come from the source domain val enq = Flipped(Decoupled(gen)) // These cross to the sink clock domain val async = new AsyncBundle(gen, params) }) val bits = params.bits val sink_ready = WireInit(true.B) val mem = Reg(Vec(params.depth, gen)) // This does NOT need to be reset at all. val widx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.enq.fire, !sink_ready, "widx_bin")) val ridx = AsyncResetSynchronizerShiftReg(io.async.ridx, params.sync, Some("ridx_gray")) val ready = sink_ready && widx =/= (ridx ^ (params.depth \| params.depth >> 1).U) val index = if (bits == 0) 0.U else io.async.widx(bits-1, 0) ^ (io.async.widx(bits, bits) << (bits-1)) when (io.enq.fire) { mem(index) := io.enq.bits } val ready_reg = withReset(reset.asAsyncReset)(RegNext(next=ready, init=false.B).suggestName("ready_reg")) io.enq.ready := ready_reg && sink_ready val widx_reg = withReset(reset.asAsyncReset)(RegNext(next=widx, init=0.U).suggestName("widx_gray")) io.async.widx := widx_reg io.async.index match { case Some(index) => io.async.mem(0) := mem(index) case None => io.async.mem := mem } io.async.safe.foreach { sio => val source_valid_0 = Module(new AsyncValidSync(params.sync, "source_valid_0")) val source_valid_1 = Module(new AsyncValidSync(params.sync, "source_valid_1")) val sink_extend = Module(new AsyncValidSync(params.sync, "sink_extend")) val sink_valid = Module(new AsyncValidSync(params.sync, "sink_valid")) source_valid_0.reset := (reset.asBool \|\| !sio.sink_reset_n).asAsyncReset source_valid_1.reset := (reset.asBool \|\| !sio.sink_reset_n).asAsyncReset sink_extend .reset := (reset.asBool \|\| !sio.sink_reset_n).asAsyncReset sink_valid .reset := reset.asAsyncReset source_valid_0.clock := clock source_valid_1.clock := clock sink_extend .clock := clock sink_valid .clock := clock source_valid_0.io.in := true.B source_valid_1.io.in := source_valid_0.io.out sio.widx_valid := source_valid_1.io.out sink_extend.io.in := sio.ridx_valid sink_valid.io.in := sink_extend.io.out sink_ready := sink_valid.io.out sio.source_reset_n := !reset.asBool // Assert that if there is stuff in the queue, then reset cannot happen // Impossible to write because dequeue can occur on the receiving side, // then reset allowed to happen, but write side cannot know that dequeue // occurred. // TODO: write some sort of sanity check assertion for users // that denote don't reset when there is activity // assert (!(reset \|\| !sio.sink_reset_n) \|\| !io.enq.valid, "Enqueue while sink is reset and AsyncQueueSource is unprotected") // assert (!reset_rise \|\| prev_idx_match.asBool, "Sink reset while AsyncQueueSource not empty") } } class AsyncQueueSink[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module { override def desiredName = s"AsyncQueueSink_${gen.typeName}" val io = IO(new Bundle { // These come from the sink domain val deq = Decoupled(gen) // These cross to the source clock domain val async = Flipped(new AsyncBundle(gen, params)) }) val bits = params.bits val source_ready = WireInit(true.B) val ridx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.deq.fire, !source_ready, "ridx_bin")) val widx = AsyncResetSynchronizerShiftReg(io.async.widx, params.sync, Some("widx_gray")) val valid = source_ready && ridx =/= widx // The mux is safe because timing analysis ensures ridx has reached the register // On an ASIC, changes to the unread location cannot affect the selected value // On an FPGA, only one input changes at a time => mem updates don't cause glitches // The register only latches when the selected valued is not being written val index = if (bits == 0) 0.U else ridx(bits-1, 0) ^ (ridx(bits, bits) << (bits-1)) io.async.index.foreach { _ := index } // This register does not NEED to be reset, as its contents will not // be considered unless the asynchronously reset deq valid register is set. // It is possible that bits latches when the source domain is reset / has power cut // This is safe, because isolation gates brought mem low before the zeroed widx reached us val deq_bits_nxt = io.async.mem(if (params.narrow) 0.U else index) io.deq.bits := ClockCrossingReg(deq_bits_nxt, en = valid, doInit = false, name = Some("deq_bits_reg")) val valid_reg = withReset(reset.asAsyncReset)(RegNext(next=valid, init=false.B).suggestName("valid_reg")) io.deq.valid := valid_reg && source_ready val ridx_reg = withReset(reset.asAsyncReset)(RegNext(next=ridx, init=0.U).suggestName("ridx_gray")) io.async.ridx := ridx_reg io.async.safe.foreach { sio => val sink_valid_0 = Module(new AsyncValidSync(params.sync, "sink_valid_0")) val sink_valid_1 = Module(new AsyncValidSync(params.sync, "sink_valid_1")) val source_extend = Module(new AsyncValidSync(params.sync, "source_extend")) val source_valid = Module(new AsyncValidSync(params.sync, "source_valid")) sink_valid_0 .reset := (reset.asBool \|\| !sio.source_reset_n).asAsyncReset sink_valid_1 .reset := (reset.asBool \|\| !sio.source_reset_n).asAsyncReset source_extend.reset := (reset.asBool \|\| !sio.source_reset_n).asAsyncReset source_valid .reset := reset.asAsyncReset sink_valid_0 .clock := clock sink_valid_1 .clock := clock source_extend.clock := clock source_valid .clock := clock sink_valid_0.io.in := true.B sink_valid_1.io.in := sink_valid_0.io.out sio.ridx_valid := sink_valid_1.io.out source_extend.io.in := sio.widx_valid source_valid.io.in := source_extend.io.out source_ready := source_valid.io.out sio.sink_reset_n := !reset.asBool // TODO: write some sort of sanity check assertion for users // that denote don't reset when there is activity // // val reset_and_extend = !source_ready \|\| !sio.source_reset_n \|\| reset.asBool // val reset_and_extend_prev = RegNext(reset_and_extend, true.B) // val reset_rise = !reset_and_extend_prev && reset_and_extend // val prev_idx_match = AsyncResetReg(updateData=(io.async.widx===io.async.ridx), resetData=0) // assert (!reset_rise \|\| prev_idx_match.asBool, "Source reset while AsyncQueueSink not empty") } } object FromAsyncBundle { // Sometimes it makes sense for the sink to have different sync than the source def apply[T <: Data](x: AsyncBundle[T]): DecoupledIO[T] = apply(x, x.params.sync) def apply[T <: Data](x: AsyncBundle[T], sync: Int): DecoupledIO[T] = { val sink = Module(new AsyncQueueSink(chiselTypeOf(x.mem(0)), x.params.copy(sync = sync))) sink.io.async <> x sink.io.deq } } object ToAsyncBundle { def apply[T <: Data](x: ReadyValidIO[T], params: AsyncQueueParams = AsyncQueueParams()): AsyncBundle[T] = { val source = Module(new AsyncQueueSource(chiselTypeOf(x.bits), params)) source.io.enq <> x source.io.async } } class AsyncQueue[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Crossing[T] { val io = IO(new CrossingIO(gen)) val source = withClockAndReset(io.enq_clock, io.enq_reset) { Module(new AsyncQueueSource(gen, params)) } val sink = withClockAndReset(io.deq_clock, io.deq_reset) { Module(new AsyncQueueSink (gen, params)) } source.io.enq <> io.enq io.deq <> sink.io.deq sink.io.async <> source.io.async }	module AsyncValidSync_32( // @[AsyncQueue.scala:58:7] output io_out, // @[AsyncQueue.scala:59:14] input clock, // @[AsyncQueue.scala:63:17] input reset // @[AsyncQueue.scala:64:17] ); wire io_in = 1'h1; // @[ShiftReg.scala:45:23] wire _io_out_WIRE; // @[ShiftReg.scala:48:24] wire io_out_0; // @[AsyncQueue.scala:58:7] assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24] AsyncResetSynchronizerShiftReg_w1_d3_i0_42 io_out_source_valid_0 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (reset), .io_q (_io_out_WIRE) ); // @[ShiftReg.scala:45:23] assign io_out = io_out_0; // @[AsyncQueue.scala:58:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File WidthWidget.scala: package constellation.channel import chisel3._ import chisel3.util._ import freechips.rocketchip.diplomacy._ import org.chipsalliance.cde.config.{Parameters} import freechips.rocketchip.util._ object WidthWidget { def split[T <: BaseFlit](in: IrrevocableIO[T], out: IrrevocableIO[T]) = { val inBits = in.bits.payload.getWidth val outBits = out.bits.payload.getWidth require(inBits > outBits && inBits % outBits == 0) val ratio = inBits / outBits val count = RegInit(0.U(log2Ceil(ratio).W)) val first = count === 0.U val last = count === (ratio - 1).U val stored = Reg(UInt((inBits - outBits).W)) out.valid := in.valid out.bits := in.bits out.bits.head := in.bits.head && first out.bits.tail := in.bits.tail && last out.bits.payload := Mux(first, in.bits.payload, stored) in.ready := last && out.ready when (out.fire) { count := Mux(last, 0.U, count + 1.U) stored := Mux(first, in.bits.payload, stored) >> outBits } } def merge[T <: BaseFlit](in: IrrevocableIO[T], out: IrrevocableIO[T]) = { val inBits = in.bits.payload.getWidth val outBits = out.bits.payload.getWidth require(outBits > inBits && outBits % inBits == 0) val ratio = outBits / inBits val count = RegInit(0.U(log2Ceil(ratio).W)) val first = count === 0.U val last = count === (ratio - 1).U val flit = Reg(out.bits.cloneType) val payload = Reg(Vec(ratio-1, UInt(inBits.W))) out.valid := in.valid && last out.bits := flit out.bits.tail := last && in.bits.tail out.bits.payload := Cat(in.bits.payload, payload.asUInt) in.ready := !last \|\| out.ready when (in.fire) { count := Mux(last, 0.U, count + 1.U) payload(count) := in.bits.payload when (first) { flit := in.bits } } } def apply[T <: BaseFlit](in: IrrevocableIO[T], out: IrrevocableIO[T]) = { val inBits = in.bits.payload.getWidth val outBits = out.bits.payload.getWidth if (inBits == outBits) { out <> in } else if (inBits < outBits) { merge(in, out) } else { split(in, out) } } } class IngressWidthWidget(srcBits: Int)(implicit p: Parameters) extends LazyModule { val node = new IngressChannelAdapterNode( slaveFn = { s => s.copy(payloadBits=srcBits) } ) lazy val module = new LazyModuleImp(this) { (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => WidthWidget(in.flit, out.flit) } } } object IngressWidthWidget { def apply(destBits: Int, srcBits: Int)(implicit p: Parameters) = { if (destBits == srcBits) { val node = IngressChannelEphemeralNode() node } else { val ingress_width_widget = LazyModule(new IngressWidthWidget(srcBits)) ingress_width_widget.node } } } class EgressWidthWidget(srcBits: Int)(implicit p: Parameters) extends LazyModule { val node = new EgressChannelAdapterNode( slaveFn = { s => s.copy(payloadBits=srcBits) } ) lazy val module = new LazyModuleImp(this) { (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => WidthWidget(in.flit, out.flit) } } } object EgressWidthWidget { def apply(destBits: Int, srcBits: Int)(implicit p: Parameters) = { if (destBits == srcBits) { val node = EgressChannelEphemeralNode() node } else { val egress_width_widget = LazyModule(new EgressWidthWidget(srcBits)) egress_width_widget.node } } } class ChannelWidthWidget(srcBits: Int)(implicit p: Parameters) extends LazyModule { val node = new ChannelAdapterNode( slaveFn = { s => val destBits = s.payloadBits if (srcBits > destBits) { val ratio = srcBits / destBits val virtualChannelParams = s.virtualChannelParams.map { vP => require(vP.bufferSize >= ratio) vP.copy(bufferSize = vP.bufferSize / ratio) } s.copy(payloadBits=srcBits, virtualChannelParams=virtualChannelParams) } else { val ratio = destBits / srcBits val virtualChannelParams = s.virtualChannelParams.map { vP => vP.copy(bufferSize = vP.bufferSize * ratio) } s.copy(payloadBits=srcBits, virtualChannelParams=virtualChannelParams) } } ) lazy val module = new LazyModuleImp(this) { (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => val destBits = out.cParam.payloadBits in.vc_free := out.vc_free if (srcBits == destBits) { in.credit_return := out.credit_return out.flit <> in.flit } else if (srcBits > destBits) { require(srcBits % destBits == 0, s"$srcBits, $destBits") (in.flit zip out.flit) foreach { case (iF, oF) => val in_q = Module(new Queue(new Flit(in.cParam.payloadBits), in.cParam.virtualChannelParams.map(_.bufferSize).sum, pipe=true, flow=true)) in_q.io.enq.valid := iF.valid in_q.io.enq.bits := iF.bits assert(!(in_q.io.enq.valid && !in_q.io.enq.ready)) val in_flit = Wire(Irrevocable(new Flit(in.cParam.payloadBits))) in_flit.valid := in_q.io.deq.valid in_flit.bits := in_q.io.deq.bits in_q.io.deq.ready := in_flit.ready val out_flit = Wire(Irrevocable(new Flit(out.cParam.payloadBits))) oF.valid := out_flit.valid oF.bits := out_flit.bits out_flit.ready := true.B WidthWidget(in_flit, out_flit) } val ratio = srcBits / destBits val counts = RegInit(VecInit(Seq.fill(in.nVirtualChannels) { 0.U(log2Ceil(ratio).W) })) val in_credit_return = Wire(Vec(in.nVirtualChannels, Bool())) in.credit_return := in_credit_return.asUInt for (i <- 0 until in.nVirtualChannels) { in_credit_return(i) := false.B when (out.credit_return(i)) { val last = counts(i) === (ratio-1).U counts(i) := Mux(last, 0.U, counts(i) + 1.U) when (last) { in_credit_return(i) := true.B } } } } else { require(destBits % srcBits == 0) val in_flits = Wire(Vec(in.nVirtualChannels, Irrevocable(new Flit(in.cParam.payloadBits)))) val out_flits = Wire(Vec(in.nVirtualChannels, Irrevocable(new Flit(out.cParam.payloadBits)))) for (i <- 0 until in.nVirtualChannels) { val sel = in.flit.map(f => f.valid && f.bits.virt_channel_id === i.U) in_flits(i).valid := sel.orR in_flits(i).bits := Mux1H(sel, in.flit.map(_.bits)) out_flits(i).ready := sel.orR WidthWidget(in_flits(i), out_flits(i)) } for (i <- 0 until in.flit.size) { val sel = UIntToOH(in.flit(i).bits.virt_channel_id) out.flit(i).valid := Mux1H(sel, out_flits.map(_.valid)) out.flit(i).bits := Mux1H(sel, out_flits.map(_.bits)) } val ratio = destBits / srcBits val credits = RegInit(VecInit((0 until in.nVirtualChannels).map { i => 0.U(log2Ceil(ratioin.cParam.virtualChannelParams(i).bufferSize).W) })) val in_credit_return = Wire(Vec(in.nVirtualChannels, Bool())) in.credit_return := in_credit_return.asUInt for (i <- 0 until in.nVirtualChannels) { when (out.credit_return(i)) { in_credit_return(i) := true.B credits(i) := credits(i) + (ratio - 1).U } .otherwise { val empty = credits(i) === 0.U in_credit_return(i) := !empty credits(i) := Mux(empty, 0.U, credits(i) - 1.U) } } } } } } object ChannelWidthWidget { def apply(destBits: Int, srcBits: Int)(implicit p: Parameters) = { if (destBits == srcBits) { val node = ChannelEphemeralNode() node } else { val channel_width_widget = LazyModule(new ChannelWidthWidget(srcBits)) channel_width_widget.node } } } File LazyModuleImp.scala: package org.chipsalliance.diplomacy.lazymodule import chisel3.{withClockAndReset, Module, RawModule, Reset, _} import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo} import firrtl.passes.InlineAnnotation import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.nodes.Dangle import scala.collection.immutable.SortedMap /* Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]]. * * This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy. / sealed trait LazyModuleImpLike extends RawModule { /* [[LazyModule]] that contains this instance. / val wrapper: LazyModule /* IOs that will be automatically "punched" for this instance. / val auto: AutoBundle /* The metadata that describes the [[HalfEdge]]s which generated [[auto]]. / protected[diplomacy] val dangles: Seq[Dangle] // [[wrapper.module]] had better not be accessed while LazyModules are still being built! require( LazyModule.scope.isEmpty, s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}" ) /* Set module name. Defaults to the containing LazyModule's desiredName. / override def desiredName: String = wrapper.desiredName suggestName(wrapper.suggestedName) /* [[Parameters]] for chisel [[Module]]s. / implicit val p: Parameters = wrapper.p /* instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and * submodules. / protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = { // 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]], // 2. return [[Dangle]]s from each module. val childDangles = wrapper.children.reverse.flatMap { c => implicit val sourceInfo: SourceInfo = c.info c.cloneProto.map { cp => // If the child is a clone, then recursively set cloneProto of its children as well def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = { require(bases.size == clones.size) (bases.zip(clones)).map { case (l, r) => require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}") l.cloneProto = Some(r) assignCloneProtos(l.children, r.children) } } assignCloneProtos(c.children, cp.children) // Clone the child module as a record, and get its [[AutoBundle]] val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName) val clonedAuto = clone("auto").asInstanceOf[AutoBundle] // Get the empty [[Dangle]]'s of the cloned child val rawDangles = c.cloneDangles() require(rawDangles.size == clonedAuto.elements.size) // Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) } dangles }.getOrElse { // For non-clones, instantiate the child module val mod = try { Module(c.module) } catch { case e: ChiselException => { println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}") throw e } } mod.dangles } } // Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]]. // This will result in a sequence of [[Dangle]] from these [[BaseNode]]s. val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate()) // Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]] val allDangles = nodeDangles ++ childDangles // Group [[allDangles]] by their [[source]]. val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _) // For each [[source]] set of [[Dangle]]s of size 2, ensure that these // can be connected as a source-sink pair (have opposite flipped value). // Make the connection and mark them as [[done]]. val done = Set() ++ pairing.values.filter(_.size == 2).map { case Seq(a, b) => require(a.flipped != b.flipped) // @todo <> in chisel3 makes directionless connection. if (a.flipped) { a.data <> b.data } else { b.data <> a.data } a.source case _ => None } // Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module. val forward = allDangles.filter(d => !done(d.source)) // Generate [[AutoBundle]] IO from [[forward]]. val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _)) // Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]] val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) => if (d.flipped) { d.data <> io } else { io <> d.data } d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name) } // Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]]. wrapper.inModuleBody.reverse.foreach { _() } if (wrapper.shouldBeInlined) { chisel3.experimental.annotate(new ChiselAnnotation { def toFirrtl = InlineAnnotation(toNamed) }) } // Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]]. (auto, dangles) } } /* Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. / class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike { /* Instantiate hardware of this `Module`. / val (auto, dangles) = instantiate() } /* Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. / class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike { // These wires are the default clock+reset for all LazyModule children. // It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the // [[LazyRawModuleImp]] children. // Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly. /* drive clock explicitly. / val childClock: Clock = Wire(Clock()) /* drive reset explicitly. */ val childReset: Reset = Wire(Reset()) // the default is that these are disabled childClock := false.B.asClock childReset := chisel3.DontCare def provideImplicitClockToLazyChildren: Boolean = false val (auto, dangles) = if (provideImplicitClockToLazyChildren) { withClockAndReset(childClock, childReset) { instantiate() } } else { instantiate() } }	module EgressWidthWidget( // @[WidthWidget.scala:98:25] input clock, // @[WidthWidget.scala:98:25] input reset, // @[WidthWidget.scala:98:25] output auto_in_flit_ready, // @[LazyModuleImp.scala:107:25] input auto_in_flit_valid, // @[LazyModuleImp.scala:107:25] input auto_in_flit_bits_head, // @[LazyModuleImp.scala:107:25] input auto_in_flit_bits_tail, // @[LazyModuleImp.scala:107:25] input [36:0] auto_in_flit_bits_payload, // @[LazyModuleImp.scala:107:25] input auto_out_flit_ready, // @[LazyModuleImp.scala:107:25] output auto_out_flit_valid, // @[LazyModuleImp.scala:107:25] output auto_out_flit_bits_head, // @[LazyModuleImp.scala:107:25] output auto_out_flit_bits_tail, // @[LazyModuleImp.scala:107:25] output [73:0] auto_out_flit_bits_payload // @[LazyModuleImp.scala:107:25] ); reg last; // @[WidthWidget.scala:37:24] reg flit_head; // @[WidthWidget.scala:40:19] reg [36:0] payload_0; // @[WidthWidget.scala:41:22] wire nodeIn_flit_ready = ~last \| auto_out_flit_ready; // @[WidthWidget.scala:37:24, :47:{17,23}] wire _GEN = nodeIn_flit_ready & auto_in_flit_valid; // @[Decoupled.scala:51:35] always @(posedge clock) begin // @[WidthWidget.scala:98:25] if (reset) // @[WidthWidget.scala:98:25] last <= 1'h0; // @[WidthWidget.scala:37:24] else if (_GEN) // @[Decoupled.scala:51:35] last <= ~last & last - 1'h1; // @[WidthWidget.scala:37:24, :49:{19,37}] if (_GEN & ~last) // @[Decoupled.scala:51:35] flit_head <= auto_in_flit_bits_head; // @[WidthWidget.scala:40:19] if (_GEN) // @[Decoupled.scala:51:35] payload_0 <= auto_in_flit_bits_payload; // @[WidthWidget.scala:41:22] always @(posedge)
Generate the Verilog code corresponding to the following Chisel files. File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /* Like Vec.apply(idx), but tolerates indices of mismatched width / def extract(idx: UInt): T = x((idx \| 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx \| 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def \| (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a \|\| b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_\|\|_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /* Any Data subtype that has a Bool member named valid. / type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /* converts from camel case to to underscores, also removing all spaces / def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /* converts spaces or underscores to hyphens, also lowering case / def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y \| (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y \|\| y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 \| 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /* Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation / def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Nodes.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.nodes._ import freechips.rocketchip.util.{AsyncQueueParams,RationalDirection} case object TLMonitorBuilder extends Field[TLMonitorArgs => TLMonitorBase](args => new TLMonitor(args)) object TLImp extends NodeImp[TLMasterPortParameters, TLSlavePortParameters, TLEdgeOut, TLEdgeIn, TLBundle] { def edgeO(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeOut(pd, pu, p, sourceInfo) def edgeI(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeIn (pd, pu, p, sourceInfo) def bundleO(eo: TLEdgeOut) = TLBundle(eo.bundle) def bundleI(ei: TLEdgeIn) = TLBundle(ei.bundle) def render(ei: TLEdgeIn) = RenderedEdge(colour = "#000000" / black /, label = (ei.manager.beatBytes 8).toString) override def monitor(bundle: TLBundle, edge: TLEdgeIn): Unit = { val monitor = Module(edge.params(TLMonitorBuilder)(TLMonitorArgs(edge))) monitor.io.in := bundle } override def mixO(pd: TLMasterPortParameters, node: OutwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLMasterPortParameters = pd.v1copy(clients = pd.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }) override def mixI(pu: TLSlavePortParameters, node: InwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLSlavePortParameters = pu.v1copy(managers = pu.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }) } trait TLFormatNode extends FormatNode[TLEdgeIn, TLEdgeOut] case class TLClientNode(portParams: Seq[TLMasterPortParameters])(implicit valName: ValName) extends SourceNode(TLImp)(portParams) with TLFormatNode case class TLManagerNode(portParams: Seq[TLSlavePortParameters])(implicit valName: ValName) extends SinkNode(TLImp)(portParams) with TLFormatNode case class TLAdapterNode( clientFn: TLMasterPortParameters => TLMasterPortParameters = { s => s }, managerFn: TLSlavePortParameters => TLSlavePortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLImp)(clientFn, managerFn) with TLFormatNode case class TLJunctionNode( clientFn: Seq[TLMasterPortParameters] => Seq[TLMasterPortParameters], managerFn: Seq[TLSlavePortParameters] => Seq[TLSlavePortParameters])( implicit valName: ValName) extends JunctionNode(TLImp)(clientFn, managerFn) with TLFormatNode case class TLIdentityNode()(implicit valName: ValName) extends IdentityNode(TLImp)() with TLFormatNode object TLNameNode { def apply(name: ValName) = TLIdentityNode()(name) def apply(name: Option[String]): TLIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLIdentityNode = apply(Some(name)) } case class TLEphemeralNode()(implicit valName: ValName) extends EphemeralNode(TLImp)() object TLTempNode { def apply(): TLEphemeralNode = TLEphemeralNode()(ValName("temp")) } case class TLNexusNode( clientFn: Seq[TLMasterPortParameters] => TLMasterPortParameters, managerFn: Seq[TLSlavePortParameters] => TLSlavePortParameters)( implicit valName: ValName) extends NexusNode(TLImp)(clientFn, managerFn) with TLFormatNode abstract class TLCustomNode(implicit valName: ValName) extends CustomNode(TLImp) with TLFormatNode // Asynchronous crossings trait TLAsyncFormatNode extends FormatNode[TLAsyncEdgeParameters, TLAsyncEdgeParameters] object TLAsyncImp extends SimpleNodeImp[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncEdgeParameters, TLAsyncBundle] { def edge(pd: TLAsyncClientPortParameters, pu: TLAsyncManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLAsyncEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLAsyncEdgeParameters) = new TLAsyncBundle(e.bundle) def render(e: TLAsyncEdgeParameters) = RenderedEdge(colour = "#ff0000" /* red /, label = e.manager.async.depth.toString) override def mixO(pd: TLAsyncClientPortParameters, node: OutwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLAsyncManagerPortParameters, node: InwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLAsyncAdapterNode( clientFn: TLAsyncClientPortParameters => TLAsyncClientPortParameters = { s => s }, managerFn: TLAsyncManagerPortParameters => TLAsyncManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLAsyncImp)(clientFn, managerFn) with TLAsyncFormatNode case class TLAsyncIdentityNode()(implicit valName: ValName) extends IdentityNode(TLAsyncImp)() with TLAsyncFormatNode object TLAsyncNameNode { def apply(name: ValName) = TLAsyncIdentityNode()(name) def apply(name: Option[String]): TLAsyncIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLAsyncIdentityNode = apply(Some(name)) } case class TLAsyncSourceNode(sync: Option[Int])(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLAsyncImp)( dFn = { p => TLAsyncClientPortParameters(p) }, uFn = { p => p.base.v1copy(minLatency = p.base.minLatency + sync.getOrElse(p.async.sync)) }) with FormatNode[TLEdgeIn, TLAsyncEdgeParameters] // discard cycles in other clock domain case class TLAsyncSinkNode(async: AsyncQueueParams)(implicit valName: ValName) extends MixedAdapterNode(TLAsyncImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = p.base.minLatency + async.sync) }, uFn = { p => TLAsyncManagerPortParameters(async, p) }) with FormatNode[TLAsyncEdgeParameters, TLEdgeOut] // Rationally related crossings trait TLRationalFormatNode extends FormatNode[TLRationalEdgeParameters, TLRationalEdgeParameters] object TLRationalImp extends SimpleNodeImp[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalEdgeParameters, TLRationalBundle] { def edge(pd: TLRationalClientPortParameters, pu: TLRationalManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLRationalEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLRationalEdgeParameters) = new TLRationalBundle(e.bundle) def render(e: TLRationalEdgeParameters) = RenderedEdge(colour = "#00ff00" / green /) override def mixO(pd: TLRationalClientPortParameters, node: OutwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLRationalManagerPortParameters, node: InwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLRationalAdapterNode( clientFn: TLRationalClientPortParameters => TLRationalClientPortParameters = { s => s }, managerFn: TLRationalManagerPortParameters => TLRationalManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLRationalImp)(clientFn, managerFn) with TLRationalFormatNode case class TLRationalIdentityNode()(implicit valName: ValName) extends IdentityNode(TLRationalImp)() with TLRationalFormatNode object TLRationalNameNode { def apply(name: ValName) = TLRationalIdentityNode()(name) def apply(name: Option[String]): TLRationalIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLRationalIdentityNode = apply(Some(name)) } case class TLRationalSourceNode()(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLRationalImp)( dFn = { p => TLRationalClientPortParameters(p) }, uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLRationalEdgeParameters] // discard cycles from other clock domain case class TLRationalSinkNode(direction: RationalDirection)(implicit valName: ValName) extends MixedAdapterNode(TLRationalImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = 1) }, uFn = { p => TLRationalManagerPortParameters(direction, p) }) with FormatNode[TLRationalEdgeParameters, TLEdgeOut] // Credited version of TileLink channels trait TLCreditedFormatNode extends FormatNode[TLCreditedEdgeParameters, TLCreditedEdgeParameters] object TLCreditedImp extends SimpleNodeImp[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedEdgeParameters, TLCreditedBundle] { def edge(pd: TLCreditedClientPortParameters, pu: TLCreditedManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLCreditedEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLCreditedEdgeParameters) = new TLCreditedBundle(e.bundle) def render(e: TLCreditedEdgeParameters) = RenderedEdge(colour = "#ffff00" / yellow /, e.delay.toString) override def mixO(pd: TLCreditedClientPortParameters, node: OutwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLCreditedManagerPortParameters, node: InwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLCreditedAdapterNode( clientFn: TLCreditedClientPortParameters => TLCreditedClientPortParameters = { s => s }, managerFn: TLCreditedManagerPortParameters => TLCreditedManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLCreditedImp)(clientFn, managerFn) with TLCreditedFormatNode case class TLCreditedIdentityNode()(implicit valName: ValName) extends IdentityNode(TLCreditedImp)() with TLCreditedFormatNode object TLCreditedNameNode { def apply(name: ValName) = TLCreditedIdentityNode()(name) def apply(name: Option[String]): TLCreditedIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLCreditedIdentityNode = apply(Some(name)) } case class TLCreditedSourceNode(delay: TLCreditedDelay)(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLCreditedImp)( dFn = { p => TLCreditedClientPortParameters(delay, p) }, uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLCreditedEdgeParameters] // discard cycles from other clock domain case class TLCreditedSinkNode(delay: TLCreditedDelay)(implicit valName: ValName) extends MixedAdapterNode(TLCreditedImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = 1) }, uFn = { p => TLCreditedManagerPortParameters(delay, p) }) with FormatNode[TLCreditedEdgeParameters, TLEdgeOut] File Bundles.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import freechips.rocketchip.util._ import scala.collection.immutable.ListMap import chisel3.util.Decoupled import chisel3.util.DecoupledIO import chisel3.reflect.DataMirror abstract class TLBundleBase(val params: TLBundleParameters) extends Bundle // common combos in lazy policy: // Put + Acquire // Release + AccessAck object TLMessages { // A B C D E def PutFullData = 0.U // . . => AccessAck def PutPartialData = 1.U // . . => AccessAck def ArithmeticData = 2.U // . . => AccessAckData def LogicalData = 3.U // . . => AccessAckData def Get = 4.U // . . => AccessAckData def Hint = 5.U // . . => HintAck def AcquireBlock = 6.U // . => Grant[Data] def AcquirePerm = 7.U // . => Grant[Data] def Probe = 6.U // . => ProbeAck[Data] def AccessAck = 0.U // . . def AccessAckData = 1.U // . . def HintAck = 2.U // . . def ProbeAck = 4.U // . def ProbeAckData = 5.U // . def Release = 6.U // . => ReleaseAck def ReleaseData = 7.U // . => ReleaseAck def Grant = 4.U // . => GrantAck def GrantData = 5.U // . => GrantAck def ReleaseAck = 6.U // . def GrantAck = 0.U // . def isA(x: UInt) = x <= AcquirePerm def isB(x: UInt) = x <= Probe def isC(x: UInt) = x <= ReleaseData def isD(x: UInt) = x <= ReleaseAck def adResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, Grant, Grant) def bcResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, ProbeAck, ProbeAck) def a = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("AcquireBlock",TLPermissions.PermMsgGrow), ("AcquirePerm",TLPermissions.PermMsgGrow)) def b = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("Probe",TLPermissions.PermMsgCap)) def c = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("ProbeAck",TLPermissions.PermMsgReport), ("ProbeAckData",TLPermissions.PermMsgReport), ("Release",TLPermissions.PermMsgReport), ("ReleaseData",TLPermissions.PermMsgReport)) def d = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("Grant",TLPermissions.PermMsgCap), ("GrantData",TLPermissions.PermMsgCap), ("ReleaseAck",TLPermissions.PermMsgReserved)) } /* * The three primary TileLink permissions are: * (T)runk: the agent is (or is on inwards path to) the global point of serialization. * (B)ranch: the agent is on an outwards path to * (N)one: * These permissions are permuted by transfer operations in various ways. * Operations can cap permissions, request for them to be grown or shrunk, * or for a report on their current status. / object TLPermissions { val aWidth = 2 val bdWidth = 2 val cWidth = 3 // Cap types (Grant = new permissions, Probe = permisions <= target) def toT = 0.U(bdWidth.W) def toB = 1.U(bdWidth.W) def toN = 2.U(bdWidth.W) def isCap(x: UInt) = x <= toN // Grow types (Acquire = permissions >= target) def NtoB = 0.U(aWidth.W) def NtoT = 1.U(aWidth.W) def BtoT = 2.U(aWidth.W) def isGrow(x: UInt) = x <= BtoT // Shrink types (ProbeAck, Release) def TtoB = 0.U(cWidth.W) def TtoN = 1.U(cWidth.W) def BtoN = 2.U(cWidth.W) def isShrink(x: UInt) = x <= BtoN // Report types (ProbeAck, Release) def TtoT = 3.U(cWidth.W) def BtoB = 4.U(cWidth.W) def NtoN = 5.U(cWidth.W) def isReport(x: UInt) = x <= NtoN def PermMsgGrow:Seq[String] = Seq("Grow NtoB", "Grow NtoT", "Grow BtoT") def PermMsgCap:Seq[String] = Seq("Cap toT", "Cap toB", "Cap toN") def PermMsgReport:Seq[String] = Seq("Shrink TtoB", "Shrink TtoN", "Shrink BtoN", "Report TotT", "Report BtoB", "Report NtoN") def PermMsgReserved:Seq[String] = Seq("Reserved") } object TLAtomics { val width = 3 // Arithmetic types def MIN = 0.U(width.W) def MAX = 1.U(width.W) def MINU = 2.U(width.W) def MAXU = 3.U(width.W) def ADD = 4.U(width.W) def isArithmetic(x: UInt) = x <= ADD // Logical types def XOR = 0.U(width.W) def OR = 1.U(width.W) def AND = 2.U(width.W) def SWAP = 3.U(width.W) def isLogical(x: UInt) = x <= SWAP def ArithMsg:Seq[String] = Seq("MIN", "MAX", "MINU", "MAXU", "ADD") def LogicMsg:Seq[String] = Seq("XOR", "OR", "AND", "SWAP") } object TLHints { val width = 1 def PREFETCH_READ = 0.U(width.W) def PREFETCH_WRITE = 1.U(width.W) def isHints(x: UInt) = x <= PREFETCH_WRITE def HintsMsg:Seq[String] = Seq("PrefetchRead", "PrefetchWrite") } sealed trait TLChannel extends TLBundleBase { val channelName: String } sealed trait TLDataChannel extends TLChannel sealed trait TLAddrChannel extends TLDataChannel final class TLBundleA(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleA_${params.shortName}" val channelName = "'A' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(List(TLAtomics.width, TLPermissions.aWidth, TLHints.width).max.W) // amo_opcode \|\| grow perms \|\| hint val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleB(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleB_${params.shortName}" val channelName = "'B' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val address = UInt(params.addressBits.W) // from // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleC(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleC_${params.shortName}" val channelName = "'C' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.cWidth.W) // shrink or report perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleD(params: TLBundleParameters) extends TLBundleBase(params) with TLDataChannel { override def typeName = s"TLBundleD_${params.shortName}" val channelName = "'D' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val sink = UInt(params.sinkBits.W) // from val denied = Bool() // implies corrupt iff Data val user = BundleMap(params.responseFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleE(params: TLBundleParameters) extends TLBundleBase(params) with TLChannel { override def typeName = s"TLBundleE_${params.shortName}" val channelName = "'E' channel" val sink = UInt(params.sinkBits.W) // to } class TLBundle(val params: TLBundleParameters) extends Record { // Emulate a Bundle with elements abcde or ad depending on params.hasBCE private val optA = Some (Decoupled(new TLBundleA(params))) private val optB = params.hasBCE.option(Flipped(Decoupled(new TLBundleB(params)))) private val optC = params.hasBCE.option(Decoupled(new TLBundleC(params))) private val optD = Some (Flipped(Decoupled(new TLBundleD(params)))) private val optE = params.hasBCE.option(Decoupled(new TLBundleE(params))) def a: DecoupledIO[TLBundleA] = optA.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleA(params))))) def b: DecoupledIO[TLBundleB] = optB.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleB(params))))) def c: DecoupledIO[TLBundleC] = optC.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleC(params))))) def d: DecoupledIO[TLBundleD] = optD.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleD(params))))) def e: DecoupledIO[TLBundleE] = optE.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleE(params))))) val elements = if (params.hasBCE) ListMap("e" -> e, "d" -> d, "c" -> c, "b" -> b, "a" -> a) else ListMap("d" -> d, "a" -> a) def tieoff(): Unit = { DataMirror.specifiedDirectionOf(a.ready) match { case SpecifiedDirection.Input => a.ready := false.B c.ready := false.B e.ready := false.B b.valid := false.B d.valid := false.B case SpecifiedDirection.Output => a.valid := false.B c.valid := false.B e.valid := false.B b.ready := false.B d.ready := false.B case _ => } } } object TLBundle { def apply(params: TLBundleParameters) = new TLBundle(params) } class TLAsyncBundleBase(val params: TLAsyncBundleParameters) extends Bundle class TLAsyncBundle(params: TLAsyncBundleParameters) extends TLAsyncBundleBase(params) { val a = new AsyncBundle(new TLBundleA(params.base), params.async) val b = Flipped(new AsyncBundle(new TLBundleB(params.base), params.async)) val c = new AsyncBundle(new TLBundleC(params.base), params.async) val d = Flipped(new AsyncBundle(new TLBundleD(params.base), params.async)) val e = new AsyncBundle(new TLBundleE(params.base), params.async) } class TLRationalBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = RationalIO(new TLBundleA(params)) val b = Flipped(RationalIO(new TLBundleB(params))) val c = RationalIO(new TLBundleC(params)) val d = Flipped(RationalIO(new TLBundleD(params))) val e = RationalIO(new TLBundleE(params)) } class TLCreditedBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = CreditedIO(new TLBundleA(params)) val b = Flipped(CreditedIO(new TLBundleB(params))) val c = CreditedIO(new TLBundleC(params)) val d = Flipped(CreditedIO(new TLBundleD(params))) val e = CreditedIO(new TLBundleE(params)) } File LazyModuleImp.scala: package org.chipsalliance.diplomacy.lazymodule import chisel3.{withClockAndReset, Module, RawModule, Reset, _} import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo} import firrtl.passes.InlineAnnotation import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.nodes.Dangle import scala.collection.immutable.SortedMap /** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]]. * * This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy. / sealed trait LazyModuleImpLike extends RawModule { /* [[LazyModule]] that contains this instance. / val wrapper: LazyModule /* IOs that will be automatically "punched" for this instance. / val auto: AutoBundle /* The metadata that describes the [[HalfEdge]]s which generated [[auto]]. / protected[diplomacy] val dangles: Seq[Dangle] // [[wrapper.module]] had better not be accessed while LazyModules are still being built! require( LazyModule.scope.isEmpty, s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}" ) /* Set module name. Defaults to the containing LazyModule's desiredName. / override def desiredName: String = wrapper.desiredName suggestName(wrapper.suggestedName) /* [[Parameters]] for chisel [[Module]]s. / implicit val p: Parameters = wrapper.p /* instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and * submodules. / protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = { // 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]], // 2. return [[Dangle]]s from each module. val childDangles = wrapper.children.reverse.flatMap { c => implicit val sourceInfo: SourceInfo = c.info c.cloneProto.map { cp => // If the child is a clone, then recursively set cloneProto of its children as well def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = { require(bases.size == clones.size) (bases.zip(clones)).map { case (l, r) => require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}") l.cloneProto = Some(r) assignCloneProtos(l.children, r.children) } } assignCloneProtos(c.children, cp.children) // Clone the child module as a record, and get its [[AutoBundle]] val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName) val clonedAuto = clone("auto").asInstanceOf[AutoBundle] // Get the empty [[Dangle]]'s of the cloned child val rawDangles = c.cloneDangles() require(rawDangles.size == clonedAuto.elements.size) // Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) } dangles }.getOrElse { // For non-clones, instantiate the child module val mod = try { Module(c.module) } catch { case e: ChiselException => { println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}") throw e } } mod.dangles } } // Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]]. // This will result in a sequence of [[Dangle]] from these [[BaseNode]]s. val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate()) // Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]] val allDangles = nodeDangles ++ childDangles // Group [[allDangles]] by their [[source]]. val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _) // For each [[source]] set of [[Dangle]]s of size 2, ensure that these // can be connected as a source-sink pair (have opposite flipped value). // Make the connection and mark them as [[done]]. val done = Set() ++ pairing.values.filter(_.size == 2).map { case Seq(a, b) => require(a.flipped != b.flipped) // @todo <> in chisel3 makes directionless connection. if (a.flipped) { a.data <> b.data } else { b.data <> a.data } a.source case _ => None } // Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module. val forward = allDangles.filter(d => !done(d.source)) // Generate [[AutoBundle]] IO from [[forward]]. val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _)) // Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]] val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) => if (d.flipped) { d.data <> io } else { io <> d.data } d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name) } // Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]]. wrapper.inModuleBody.reverse.foreach { _() } if (wrapper.shouldBeInlined) { chisel3.experimental.annotate(new ChiselAnnotation { def toFirrtl = InlineAnnotation(toNamed) }) } // Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]]. (auto, dangles) } } /* Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. / class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike { /* Instantiate hardware of this `Module`. / val (auto, dangles) = instantiate() } /* Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. / class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike { // These wires are the default clock+reset for all LazyModule children. // It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the // [[LazyRawModuleImp]] children. // Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly. /* drive clock explicitly. / val childClock: Clock = Wire(Clock()) /* drive reset explicitly. / val childReset: Reset = Wire(Reset()) // the default is that these are disabled childClock := false.B.asClock childReset := chisel3.DontCare def provideImplicitClockToLazyChildren: Boolean = false val (auto, dangles) = if (provideImplicitClockToLazyChildren) { withClockAndReset(childClock, childReset) { instantiate() } } else { instantiate() } } File TLSerdes.scala: package testchipip.serdes import chisel3._ import chisel3.util._ import freechips.rocketchip.diplomacy._ import org.chipsalliance.cde.config._ import freechips.rocketchip.util._ import freechips.rocketchip.tilelink._ object TLSerdesser { // This should be the standard bundle type for TLSerdesser val STANDARD_TLBUNDLE_PARAMS = TLBundleParameters( addressBits=64, dataBits=64, sourceBits=8, sinkBits=8, sizeBits=8, echoFields=Nil, requestFields=Nil, responseFields=Nil, hasBCE=true) } class SerdesDebugIO extends Bundle { val ser_busy = Output(Bool()) val des_busy = Output(Bool()) } class TLSerdesser( val flitWidth: Int, clientPortParams: Option[TLMasterPortParameters], managerPortParams: Option[TLSlavePortParameters], val bundleParams: TLBundleParameters = TLSerdesser.STANDARD_TLBUNDLE_PARAMS, nameSuffix: Option[String] = None ) (implicit p: Parameters) extends LazyModule { require (clientPortParams.isDefined \|\| managerPortParams.isDefined) val clientNode = clientPortParams.map { c => TLClientNode(Seq(c)) } val managerNode = managerPortParams.map { m => TLManagerNode(Seq(m)) } override lazy val desiredName = (Seq("TLSerdesser") ++ nameSuffix).mkString("_") lazy val module = new Impl class Impl extends LazyModuleImp(this) { val io = IO(new Bundle { val ser = Vec(5, new DecoupledFlitIO(flitWidth)) val debug = new SerdesDebugIO }) val client_tl = clientNode.map(_.out(0)._1).getOrElse(0.U.asTypeOf(new TLBundle(bundleParams))) val client_edge = clientNode.map(_.out(0)._2) val manager_tl = managerNode.map(_.in(0)._1).getOrElse(0.U.asTypeOf(new TLBundle(bundleParams))) val manager_edge = managerNode.map(_.in(0)._2) val clientParams = client_edge.map(_.bundle).getOrElse(bundleParams) val managerParams = manager_edge.map(_.bundle).getOrElse(bundleParams) val mergedParams = clientParams.union(managerParams).union(bundleParams) require(mergedParams.echoFields.isEmpty, "TLSerdesser does not support TileLink with echo fields") require(mergedParams.requestFields.isEmpty, "TLSerdesser does not support TileLink with request fields") require(mergedParams.responseFields.isEmpty, "TLSerdesser does not support TileLink with response fields") require(mergedParams == bundleParams, s"TLSerdesser is misconfigured, the combined inwards/outwards parameters cannot be serialized using the provided bundle params\n$mergedParams > $bundleParams") val out_channels = Seq( (manager_tl.e, manager_edge.map(e => Module(new TLEToBeat(e, mergedParams, nameSuffix)))), (client_tl.d, client_edge.map (e => Module(new TLDToBeat(e, mergedParams, nameSuffix)))), (manager_tl.c, manager_edge.map(e => Module(new TLCToBeat(e, mergedParams, nameSuffix)))), (client_tl.b, client_edge.map (e => Module(new TLBToBeat(e, mergedParams, nameSuffix)))), (manager_tl.a, manager_edge.map(e => Module(new TLAToBeat(e, mergedParams, nameSuffix)))) ) io.ser.map(_.out.valid := false.B) io.ser.map(_.out.bits := DontCare) val out_sers = out_channels.zipWithIndex.map { case ((c,b),i) => b.map { b => b.io.protocol <> c val ser = Module(new GenericSerializer(b.io.beat.bits.cloneType, flitWidth)).suggestName(s"ser_$i") ser.io.in <> b.io.beat io.ser(i).out <> ser.io.out ser }}.flatten io.debug.ser_busy := out_sers.map(_.io.busy).orR val in_channels = Seq( (client_tl.e, Module(new TLEFromBeat(mergedParams, nameSuffix))), (manager_tl.d, Module(new TLDFromBeat(mergedParams, nameSuffix))), (client_tl.c, Module(new TLCFromBeat(mergedParams, nameSuffix))), (manager_tl.b, Module(new TLBFromBeat(mergedParams, nameSuffix))), (client_tl.a, Module(new TLAFromBeat(mergedParams, nameSuffix))) ) val in_desers = in_channels.zipWithIndex.map { case ((c,b),i) => c <> b.io.protocol val des = Module(new GenericDeserializer(b.io.beat.bits.cloneType, flitWidth)).suggestName(s"des_$i") des.io.in <> io.ser(i).in b.io.beat <> des.io.out des } io.debug.des_busy := in_desers.map(_.io.busy).orR } } File MixedNode.scala: package org.chipsalliance.diplomacy.nodes import chisel3.{Data, DontCare, Wire} import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.{Field, Parameters} import org.chipsalliance.diplomacy.ValName import org.chipsalliance.diplomacy.sourceLine /* One side metadata of a [[Dangle]]. * * Describes one side of an edge going into or out of a [[BaseNode]]. * * @param serial * the global [[BaseNode.serial]] number of the [[BaseNode]] that this [[HalfEdge]] connects to. * @param index * the `index` in the [[BaseNode]]'s input or output port list that this [[HalfEdge]] belongs to. / case class HalfEdge(serial: Int, index: Int) extends Ordered[HalfEdge] { import scala.math.Ordered.orderingToOrdered def compare(that: HalfEdge): Int = HalfEdge.unapply(this).compare(HalfEdge.unapply(that)) } /* [[Dangle]] captures the `IO` information of a [[LazyModule]] and which two [[BaseNode]]s the [[Edges]]/[[Bundle]] * connects. * * [[Dangle]]s are generated by [[BaseNode.instantiate]] using [[MixedNode.danglesOut]] and [[MixedNode.danglesIn]] , * [[LazyModuleImp.instantiate]] connects those that go to internal or explicit IO connections in a [[LazyModule]]. * * @param source * the source [[HalfEdge]] of this [[Dangle]], which captures the source [[BaseNode]] and the port `index` within * that [[BaseNode]]. * @param sink * sink [[HalfEdge]] of this [[Dangle]], which captures the sink [[BaseNode]] and the port `index` within that * [[BaseNode]]. * @param flipped * flip or not in [[AutoBundle.makeElements]]. If true this corresponds to `danglesOut`, if false it corresponds to * `danglesIn`. * @param dataOpt * actual [[Data]] for the hardware connection. Can be empty if this belongs to a cloned module / case class Dangle(source: HalfEdge, sink: HalfEdge, flipped: Boolean, name: String, dataOpt: Option[Data]) { def data = dataOpt.get } /* [[Edges]] is a collection of parameters describing the functionality and connection for an interface, which is often * derived from the interconnection protocol and can inform the parameterization of the hardware bundles that actually * implement the protocol. / case class Edges[EI, EO](in: Seq[EI], out: Seq[EO]) /* A field available in [[Parameters]] used to determine whether [[InwardNodeImp.monitor]] will be called. / case object MonitorsEnabled extends Field[Boolean](true) /* When rendering the edge in a graphical format, flip the order in which the edges' source and sink are presented. * * For example, when rendering graphML, yEd by default tries to put the source node vertically above the sink node, but * [[RenderFlipped]] inverts this relationship. When a particular [[LazyModule]] contains both source nodes and sink * nodes, flipping the rendering of one node's edge will usual produce a more concise visual layout for the * [[LazyModule]]. / case object RenderFlipped extends Field[Boolean](false) /* The sealed node class in the package, all node are derived from it. * * @param inner * Sink interface implementation. * @param outer * Source interface implementation. * @param valName * val name of this node. * @tparam DI * Downward-flowing parameters received on the inner side of the node. It is usually a brunch of parameters * describing the protocol parameters from a source. For an [[InwardNode]], it is determined by the connected * [[OutwardNode]]. Since it can be connected to multiple sources, this parameter is always a Seq of source port * parameters. * @tparam UI * Upward-flowing parameters generated by the inner side of the node. It is usually a brunch of parameters describing * the protocol parameters of a sink. For an [[InwardNode]], it is determined itself. * @tparam EI * Edge Parameters describing a connection on the inner side of the node. It is usually a brunch of transfers * specified for a sink according to protocol. * @tparam BI * Bundle type used when connecting to the inner side of the node. It is a hardware interface of this sink interface. * It should extends from [[chisel3.Data]], which represents the real hardware. * @tparam DO * Downward-flowing parameters generated on the outer side of the node. It is usually a brunch of parameters * describing the protocol parameters of a source. For an [[OutwardNode]], it is determined itself. * @tparam UO * Upward-flowing parameters received by the outer side of the node. It is usually a brunch of parameters describing * the protocol parameters from a sink. For an [[OutwardNode]], it is determined by the connected [[InwardNode]]. * Since it can be connected to multiple sinks, this parameter is always a Seq of sink port parameters. * @tparam EO * Edge Parameters describing a connection on the outer side of the node. It is usually a brunch of transfers * specified for a source according to protocol. * @tparam BO * Bundle type used when connecting to the outer side of the node. It is a hardware interface of this source * interface. It should extends from [[chisel3.Data]], which represents the real hardware. * * @note * Call Graph of [[MixedNode]] * - line `─`: source is process by a function and generate pass to others * - Arrow `→`: target of arrow is generated by source * * {{{ * (from the other node) * ┌─────────────────────────────────────────────────────────[[InwardNode.uiParams]]─────────────┐ * ↓ │ * (binding node when elaboration) [[OutwardNode.uoParams]]────────────────────────[[MixedNode.mapParamsU]]→──────────┐ │ * [[InwardNode.accPI]] │ │ │ * │ │ (based on protocol) │ * │ │ [[MixedNode.inner.edgeI]] │ * │ │ ↓ │ * ↓ │ │ │ * (immobilize after elaboration) (inward port from [[OutwardNode]]) │ ↓ │ * [[InwardNode.iBindings]]──┐ [[MixedNode.iDirectPorts]]────────────────────→[[MixedNode.iPorts]] [[InwardNode.uiParams]] │ * │ │ ↑ │ │ │ * │ │ │ [[OutwardNode.doParams]] │ │ * │ │ │ (from the other node) │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * │ │ │ └────────┬──────────────┤ │ * │ │ │ │ │ │ * │ │ │ │ (based on protocol) │ * │ │ │ │ [[MixedNode.inner.edgeI]] │ * │ │ │ │ │ │ * │ │ (from the other node) │ ↓ │ * │ └───[[OutwardNode.oPortMapping]] [[OutwardNode.oStar]] │ [[MixedNode.edgesIn]]───┐ │ * │ ↑ ↑ │ │ ↓ │ * │ │ │ │ │ [[MixedNode.in]] │ * │ │ │ │ ↓ ↑ │ * │ (solve star connection) │ │ │ [[MixedNode.bundleIn]]──┘ │ * ├───[[MixedNode.resolveStar]]→─┼─────────────────────────────┤ └────────────────────────────────────┐ │ * │ │ │ [[MixedNode.bundleOut]]─┐ │ │ * │ │ │ ↑ ↓ │ │ * │ │ │ │ [[MixedNode.out]] │ │ * │ ↓ ↓ │ ↑ │ │ * │ ┌─────[[InwardNode.iPortMapping]] [[InwardNode.iStar]] [[MixedNode.edgesOut]]──┘ │ │ * │ │ (from the other node) ↑ │ │ * │ │ │ │ │ │ * │ │ │ [[MixedNode.outer.edgeO]] │ │ * │ │ │ (based on protocol) │ │ * │ │ │ │ │ │ * │ │ │ ┌────────────────────────────────────────┤ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * (immobilize after elaboration)│ ↓ │ │ │ │ * [[OutwardNode.oBindings]]─┘ [[MixedNode.oDirectPorts]]───→[[MixedNode.oPorts]] [[OutwardNode.doParams]] │ │ * ↑ (inward port from [[OutwardNode]]) │ │ │ │ * │ ┌─────────────────────────────────────────┤ │ │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * [[OutwardNode.accPO]] │ ↓ │ │ │ * (binding node when elaboration) │ [[InwardNode.diParams]]─────→[[MixedNode.mapParamsD]]────────────────────────────┘ │ │ * │ ↑ │ │ * │ └──────────────────────────────────────────────────────────────────────────────────────────┘ │ * └──────────────────────────────────────────────────────────────────────────────────────────────────────────┘ * }}} / abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data]( val inner: InwardNodeImp[DI, UI, EI, BI], val outer: OutwardNodeImp[DO, UO, EO, BO] )( implicit valName: ValName) extends BaseNode with NodeHandle[DI, UI, EI, BI, DO, UO, EO, BO] with InwardNode[DI, UI, BI] with OutwardNode[DO, UO, BO] { // Generate a [[NodeHandle]] with inward and outward node are both this node. val inward = this val outward = this /* Debug info of nodes binding. / def bindingInfo: String = s"""$iBindingInfo \|$oBindingInfo \|""".stripMargin /* Debug info of ports connecting. / def connectedPortsInfo: String = s"""${oPorts.size} outward ports connected: [${oPorts.map(_._2.name).mkString(",")}] \|${iPorts.size} inward ports connected: [${iPorts.map(_._2.name).mkString(",")}] \|""".stripMargin /* Debug info of parameters propagations. / def parametersInfo: String = s"""${doParams.size} downstream outward parameters: [${doParams.mkString(",")}] \|${uoParams.size} upstream outward parameters: [${uoParams.mkString(",")}] \|${diParams.size} downstream inward parameters: [${diParams.mkString(",")}] \|${uiParams.size} upstream inward parameters: [${uiParams.mkString(",")}] \|""".stripMargin /* For a given node, converts [[OutwardNode.accPO]] and [[InwardNode.accPI]] to [[MixedNode.oPortMapping]] and * [[MixedNode.iPortMapping]]. * * Given counts of known inward and outward binding and inward and outward star bindings, return the resolved inward * stars and outward stars. * * This method will also validate the arguments and throw a runtime error if the values are unsuitable for this type * of node. * * @param iKnown * Number of known-size ([[BIND_ONCE]]) input bindings. * @param oKnown * Number of known-size ([[BIND_ONCE]]) output bindings. * @param iStar * Number of unknown size ([[BIND_STAR]]) input bindings. * @param oStar * Number of unknown size ([[BIND_STAR]]) output bindings. * @return * A Tuple of the resolved number of input and output connections. / protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStar: Int, oStar: Int): (Int, Int) /* Function to generate downward-flowing outward params from the downward-flowing input params and the current output * ports. * * @param n * The size of the output sequence to generate. * @param p * Sequence of downward-flowing input parameters of this node. * @return * A `n`-sized sequence of downward-flowing output edge parameters. / protected[diplomacy] def mapParamsD(n: Int, p: Seq[DI]): Seq[DO] /* Function to generate upward-flowing input parameters from the upward-flowing output parameters [[uiParams]]. * * @param n * Size of the output sequence. * @param p * Upward-flowing output edge parameters. * @return * A n-sized sequence of upward-flowing input edge parameters. / protected[diplomacy] def mapParamsU(n: Int, p: Seq[UO]): Seq[UI] /* @return * The sink cardinality of the node, the number of outputs bound with [[BIND_QUERY]] summed with inputs bound with * [[BIND_STAR]]. / protected[diplomacy] lazy val sinkCard: Int = oBindings.count(_._3 == BIND_QUERY) + iBindings.count(_._3 == BIND_STAR) /* @return * The source cardinality of this node, the number of inputs bound with [[BIND_QUERY]] summed with the number of * output bindings bound with [[BIND_STAR]]. / protected[diplomacy] lazy val sourceCard: Int = iBindings.count(_._3 == BIND_QUERY) + oBindings.count(_._3 == BIND_STAR) /* @return list of nodes involved in flex bindings with this node. / protected[diplomacy] lazy val flexes: Seq[BaseNode] = oBindings.filter(_._3 == BIND_FLEX).map(_._2) ++ iBindings.filter(_._3 == BIND_FLEX).map(_._2) /* Resolves the flex to be either source or sink and returns the offset where the [[BIND_STAR]] operators begin * greedily taking up the remaining connections. * * @return * A value >= 0 if it is sink cardinality, a negative value for source cardinality. The magnitude of the return * value is not relevant. / protected[diplomacy] lazy val flexOffset: Int = { /* Recursively performs a depth-first search of the [[flexes]], [[BaseNode]]s connected to this node with flex * operators. The algorithm bottoms out when we either get to a node we have already visited or when we get to a * connection that is not a flex and can set the direction for us. Otherwise, recurse by visiting the `flexes` of * each node in the current set and decide whether they should be added to the set or not. * * @return * the mapping of [[BaseNode]] indexed by their serial numbers. / def DFS(v: BaseNode, visited: Map[Int, BaseNode]): Map[Int, BaseNode] = { if (visited.contains(v.serial) \|\| !v.flexibleArityDirection) { visited } else { v.flexes.foldLeft(visited + (v.serial -> v))((sum, n) => DFS(n, sum)) } } /* Determine which [[BaseNode]] are involved in resolving the flex connections to/from this node. * * @example * {{{ * a := b := c * d := b * e := f * }}} * * `flexSet` for `a`, `b`, `c`, or `d` will be `Set(a, b, c, d)` `flexSet` for `e` or `f` will be `Set(e,f)` / val flexSet = DFS(this, Map()).values /* The total number of := operators where we're on the left. / val allSink = flexSet.map(_.sinkCard).sum /** The total number of :=* operators used when we're on the right. / val allSource = flexSet.map(_.sourceCard).sum require( allSink == 0 \|\| allSource == 0, s"The nodes ${flexSet.map(_.name)} which are inter-connected by :=* have ${allSink} := operators and ${allSource} := operators connected to them, making it impossible to determine cardinality inference direction." ) allSink - allSource } /** @return A value >= 0 if it is sink cardinality, a negative value for source cardinality. / protected[diplomacy] def edgeArityDirection(n: BaseNode): Int = { if (flexibleArityDirection) flexOffset else if (n.flexibleArityDirection) n.flexOffset else 0 } /* For a node which is connected between two nodes, select the one that will influence the direction of the flex * resolution. / protected[diplomacy] def edgeAritySelect(n: BaseNode, l: => Int, r: => Int): Int = { val dir = edgeArityDirection(n) if (dir < 0) l else if (dir > 0) r else 1 } /* Ensure that the same node is not visited twice in resolving `:=`, etc operators. / private var starCycleGuard = false /** Resolve all the star operators into concrete indicies. As connections are being made, some may be "star" * connections which need to be resolved. In some way to determine how many actual edges they correspond to. We also * need to build up the ranges of edges which correspond to each binding operator, so that We can apply the correct * edge parameters and later build up correct bundle connections. * * [[oPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that oPort (binding * operator). [[iPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that iPort * (binding operator). [[oStar]]: `Int` the value to return for this node `N` for any `N := foo` or `N :=* foo := bar` [[iStar]]: `Int` the value to return for this node `N` for any `foo :=* N` or `bar :=* foo := N` / protected[diplomacy] lazy val ( oPortMapping: Seq[(Int, Int)], iPortMapping: Seq[(Int, Int)], oStar: Int, iStar: Int ) = { try { if (starCycleGuard) throw StarCycleException() starCycleGuard = true // For a given node N... // Number of foo := N // + Number of bar :=* foo := N val oStars = oBindings.count { case (_, n, b, _, _) => b == BIND_STAR \|\| (b == BIND_FLEX && edgeArityDirection(n) < 0) } // Number of N := foo // + Number of N :=* foo := bar val iStars = iBindings.count { case (_, n, b, _, _) => b == BIND_STAR \|\| (b == BIND_FLEX && edgeArityDirection(n) > 0) } // 1 for foo := N // + bar.iStar for bar := foo := N // + foo.iStar for foo := N // + 0 for foo := N val oKnown = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, 0, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => 0 } }.sum // 1 for N := foo // + bar.oStar for N := foo :=* bar // + foo.oStar for N :=* foo // + 0 for N := foo val iKnown = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, 0) case BIND_QUERY => n.oStar case BIND_STAR => 0 } }.sum // Resolve star depends on the node subclass to implement the algorithm for this. val (iStar, oStar) = resolveStar(iKnown, oKnown, iStars, oStars) // Cumulative list of resolved outward binding range starting points val oSum = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, oStar, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => oStar } }.scanLeft(0)(_ + _) // Cumulative list of resolved inward binding range starting points val iSum = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, iStar) case BIND_QUERY => n.oStar case BIND_STAR => iStar } }.scanLeft(0)(_ + _) // Create ranges for each binding based on the running sums and return // those along with resolved values for the star operations. (oSum.init.zip(oSum.tail), iSum.init.zip(iSum.tail), oStar, iStar) } catch { case c: StarCycleException => throw c.copy(loop = context +: c.loop) } } /* Sequence of inward ports. * * This should be called after all star bindings are resolved. * * Each element is: `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. * `n` Instance of inward node. `p` View of [[Parameters]] where this connection was made. `s` Source info where this * connection was made in the source code. / protected[diplomacy] lazy val oDirectPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oBindings.flatMap { case (i, n, _, p, s) => // for each binding operator in this node, look at what it connects to val (start, end) = n.iPortMapping(i) (start until end).map { j => (j, n, p, s) } } /* Sequence of outward ports. * * This should be called after all star bindings are resolved. * * `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. `n` Instance of * outward node. `p` View of [[Parameters]] where this connection was made. `s` [[SourceInfo]] where this connection * was made in the source code. / protected[diplomacy] lazy val iDirectPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iBindings.flatMap { case (i, n, _, p, s) => // query this port index range of this node in the other side of node. val (start, end) = n.oPortMapping(i) (start until end).map { j => (j, n, p, s) } } // Ephemeral nodes ( which have non-None iForward/oForward) have in_degree = out_degree // Thus, there must exist an Eulerian path and the below algorithms terminate @scala.annotation.tailrec private def oTrace( tuple: (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) ): (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.iForward(i) match { case None => (i, n, p, s) case Some((j, m)) => oTrace((j, m, p, s)) } } @scala.annotation.tailrec private def iTrace( tuple: (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) ): (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.oForward(i) match { case None => (i, n, p, s) case Some((j, m)) => iTrace((j, m, p, s)) } } /* Final output ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - Numeric index of this binding in the [[InwardNode]] on the other end. * - [[InwardNode]] on the other end of this binding. * - A view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. / lazy val oPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oDirectPorts.map(oTrace) /* Final input ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - numeric index of this binding in [[OutwardNode]] on the other end. * - [[OutwardNode]] on the other end of this binding. * - a view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. / lazy val iPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iDirectPorts.map(iTrace) private var oParamsCycleGuard = false protected[diplomacy] lazy val diParams: Seq[DI] = iPorts.map { case (i, n, _, _) => n.doParams(i) } protected[diplomacy] lazy val doParams: Seq[DO] = { try { if (oParamsCycleGuard) throw DownwardCycleException() oParamsCycleGuard = true val o = mapParamsD(oPorts.size, diParams) require( o.size == oPorts.size, s"""Diplomacy has detected a problem with your graph: \|At the following node, the number of outward ports should equal the number of produced outward parameters. \|$context \|$connectedPortsInfo \|Downstreamed inward parameters: [${diParams.mkString(",")}] \|Produced outward parameters: [${o.mkString(",")}] \|""".stripMargin ) o.map(outer.mixO(_, this)) } catch { case c: DownwardCycleException => throw c.copy(loop = context +: c.loop) } } private var iParamsCycleGuard = false protected[diplomacy] lazy val uoParams: Seq[UO] = oPorts.map { case (o, n, _, _) => n.uiParams(o) } protected[diplomacy] lazy val uiParams: Seq[UI] = { try { if (iParamsCycleGuard) throw UpwardCycleException() iParamsCycleGuard = true val i = mapParamsU(iPorts.size, uoParams) require( i.size == iPorts.size, s"""Diplomacy has detected a problem with your graph: \|At the following node, the number of inward ports should equal the number of produced inward parameters. \|$context \|$connectedPortsInfo \|Upstreamed outward parameters: [${uoParams.mkString(",")}] \|Produced inward parameters: [${i.mkString(",")}] \|""".stripMargin ) i.map(inner.mixI(_, this)) } catch { case c: UpwardCycleException => throw c.copy(loop = context +: c.loop) } } /* Outward edge parameters. / protected[diplomacy] lazy val edgesOut: Seq[EO] = (oPorts.zip(doParams)).map { case ((i, n, p, s), o) => outer.edgeO(o, n.uiParams(i), p, s) } /* Inward edge parameters. / protected[diplomacy] lazy val edgesIn: Seq[EI] = (iPorts.zip(uiParams)).map { case ((o, n, p, s), i) => inner.edgeI(n.doParams(o), i, p, s) } /* A tuple of the input edge parameters and output edge parameters for the edges bound to this node. * * If you need to access to the edges of a foreign Node, use this method (in/out create bundles). / lazy val edges: Edges[EI, EO] = Edges(edgesIn, edgesOut) /* Create actual Wires corresponding to the Bundles parameterized by the outward edges of this node. / protected[diplomacy] lazy val bundleOut: Seq[BO] = edgesOut.map { e => val x = Wire(outer.bundleO(e)).suggestName(s"${valName.value}Out") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } /* Create actual Wires corresponding to the Bundles parameterized by the inward edges of this node. / protected[diplomacy] lazy val bundleIn: Seq[BI] = edgesIn.map { e => val x = Wire(inner.bundleI(e)).suggestName(s"${valName.value}In") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } private def emptyDanglesOut: Seq[Dangle] = oPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(serial, i), sink = HalfEdge(n.serial, j), flipped = false, name = wirePrefix + "out", dataOpt = None ) } private def emptyDanglesIn: Seq[Dangle] = iPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(n.serial, j), sink = HalfEdge(serial, i), flipped = true, name = wirePrefix + "in", dataOpt = None ) } /* Create the [[Dangle]]s which describe the connections from this node output to other nodes inputs. / protected[diplomacy] def danglesOut: Seq[Dangle] = emptyDanglesOut.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleOut(i))) } /* Create the [[Dangle]]s which describe the connections from this node input from other nodes outputs. / protected[diplomacy] def danglesIn: Seq[Dangle] = emptyDanglesIn.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleIn(i))) } private[diplomacy] var instantiated = false /* Gather Bundle and edge parameters of outward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. / def out: Seq[(BO, EO)] = { require( instantiated, s"$name.out should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleOut.zip(edgesOut) } /* Gather Bundle and edge parameters of inward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. / def in: Seq[(BI, EI)] = { require( instantiated, s"$name.in should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleIn.zip(edgesIn) } /* Actually instantiate this node during [[LazyModuleImp]] evaluation. Mark that it's safe to use the Bundle wires, * instantiate monitors on all input ports if appropriate, and return all the dangles of this node. / protected[diplomacy] def instantiate(): Seq[Dangle] = { instantiated = true if (!circuitIdentity) { (iPorts.zip(in)).foreach { case ((_, _, p, _), (b, e)) => if (p(MonitorsEnabled)) inner.monitor(b, e) } } danglesOut ++ danglesIn } protected[diplomacy] def cloneDangles(): Seq[Dangle] = emptyDanglesOut ++ emptyDanglesIn /* Connects the outward part of a node with the inward part of this node. / protected[diplomacy] def bind( h: OutwardNode[DI, UI, BI], binding: NodeBinding )( implicit p: Parameters, sourceInfo: SourceInfo ): Unit = { val x = this // x := y val y = h sourceLine(sourceInfo, " at ", "") val i = x.iPushed val o = y.oPushed y.oPush( i, x, binding match { case BIND_ONCE => BIND_ONCE case BIND_FLEX => BIND_FLEX case BIND_STAR => BIND_QUERY case BIND_QUERY => BIND_STAR } ) x.iPush(o, y, binding) } / Metadata for printing the node graph. / def inputs: Seq[(OutwardNode[DI, UI, BI], RenderedEdge)] = (iPorts.zip(edgesIn)).map { case ((_, n, p, _), e) => val re = inner.render(e) (n, re.copy(flipped = re.flipped != p(RenderFlipped))) } /* Metadata for printing the node graph */ def outputs: Seq[(InwardNode[DO, UO, BO], RenderedEdge)] = oPorts.map { case (i, n, _, _) => (n, n.inputs(i)._2) } }	module TLSerdesser_SerialRAM( // @[TLSerdes.scala:39:9] input clock, // @[TLSerdes.scala:39:9] input reset, // @[TLSerdes.scala:39:9] output auto_manager_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_manager_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_manager_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_manager_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_manager_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input auto_manager_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_manager_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_manager_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_manager_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_manager_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_manager_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_manager_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_manager_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_manager_in_d_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_manager_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output auto_manager_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output [3:0] auto_manager_in_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_manager_in_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [63:0] auto_manager_in_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_manager_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] output io_ser_0_in_ready, // @[TLSerdes.scala:40:16] input io_ser_0_in_valid, // @[TLSerdes.scala:40:16] input [31:0] io_ser_0_in_bits_flit, // @[TLSerdes.scala:40:16] input io_ser_0_out_ready, // @[TLSerdes.scala:40:16] output [31:0] io_ser_0_out_bits_flit, // @[TLSerdes.scala:40:16] output io_ser_1_in_ready, // @[TLSerdes.scala:40:16] input io_ser_1_in_valid, // @[TLSerdes.scala:40:16] input [31:0] io_ser_1_in_bits_flit, // @[TLSerdes.scala:40:16] output io_ser_2_in_ready, // @[TLSerdes.scala:40:16] input io_ser_2_in_valid, // @[TLSerdes.scala:40:16] input [31:0] io_ser_2_in_bits_flit, // @[TLSerdes.scala:40:16] input io_ser_2_out_ready, // @[TLSerdes.scala:40:16] output io_ser_2_out_valid, // @[TLSerdes.scala:40:16] output [31:0] io_ser_2_out_bits_flit, // @[TLSerdes.scala:40:16] output io_ser_3_in_ready, // @[TLSerdes.scala:40:16] input io_ser_3_in_valid, // @[TLSerdes.scala:40:16] input [31:0] io_ser_3_in_bits_flit, // @[TLSerdes.scala:40:16] output io_ser_4_in_ready, // @[TLSerdes.scala:40:16] input io_ser_4_in_valid, // @[TLSerdes.scala:40:16] input [31:0] io_ser_4_in_bits_flit, // @[TLSerdes.scala:40:16] input io_ser_4_out_ready, // @[TLSerdes.scala:40:16] output io_ser_4_out_valid, // @[TLSerdes.scala:40:16] output [31:0] io_ser_4_out_bits_flit // @[TLSerdes.scala:40:16] ); wire _des_4_io_out_valid; // @[TLSerdes.scala:86:23] wire [85:0] _des_4_io_out_bits_payload; // @[TLSerdes.scala:86:23] wire _des_4_io_out_bits_head; // @[TLSerdes.scala:86:23] wire _des_4_io_out_bits_tail; // @[TLSerdes.scala:86:23] wire _des_4_io_busy; // @[TLSerdes.scala:86:23] wire _des_3_io_out_valid; // @[TLSerdes.scala:86:23] wire [84:0] _des_3_io_out_bits_payload; // @[TLSerdes.scala:86:23] wire _des_3_io_out_bits_head; // @[TLSerdes.scala:86:23] wire _des_3_io_out_bits_tail; // @[TLSerdes.scala:86:23] wire _des_3_io_busy; // @[TLSerdes.scala:86:23] wire _des_2_io_out_valid; // @[TLSerdes.scala:86:23] wire [85:0] _des_2_io_out_bits_payload; // @[TLSerdes.scala:86:23] wire _des_2_io_out_bits_head; // @[TLSerdes.scala:86:23] wire _des_2_io_out_bits_tail; // @[TLSerdes.scala:86:23] wire _des_2_io_busy; // @[TLSerdes.scala:86:23] wire _des_1_io_out_valid; // @[TLSerdes.scala:86:23] wire [64:0] _des_1_io_out_bits_payload; // @[TLSerdes.scala:86:23] wire _des_1_io_out_bits_head; // @[TLSerdes.scala:86:23] wire _des_1_io_out_bits_tail; // @[TLSerdes.scala:86:23] wire _des_0_io_out_valid; // @[TLSerdes.scala:86:23] wire [7:0] _des_0_io_out_bits_payload; // @[TLSerdes.scala:86:23] wire _des_0_io_out_bits_head; // @[TLSerdes.scala:86:23] wire _des_0_io_out_bits_tail; // @[TLSerdes.scala:86:23] wire _in_channels_4_2_io_beat_ready; // @[TLSerdes.scala:82:28] wire [7:0] _in_channels_3_2_io_protocol_bits_size; // @[TLSerdes.scala:81:28] wire [7:0] _in_channels_3_2_io_protocol_bits_source; // @[TLSerdes.scala:81:28] wire [63:0] _in_channels_3_2_io_protocol_bits_address; // @[TLSerdes.scala:81:28] wire _in_channels_3_2_io_beat_ready; // @[TLSerdes.scala:81:28] wire _in_channels_2_2_io_beat_ready; // @[TLSerdes.scala:80:28] wire [7:0] _in_channels_1_2_io_protocol_bits_size; // @[TLSerdes.scala:79:28] wire [7:0] _in_channels_1_2_io_protocol_bits_source; // @[TLSerdes.scala:79:28] wire [7:0] _in_channels_1_2_io_protocol_bits_sink; // @[TLSerdes.scala:79:28] wire _in_channels_1_2_io_beat_ready; // @[TLSerdes.scala:79:28] wire _in_channels_0_2_io_beat_ready; // @[TLSerdes.scala:78:28] wire _ser_4_io_in_ready; // @[TLSerdes.scala:69:23] wire _ser_4_io_busy; // @[TLSerdes.scala:69:23] wire _ser_2_io_in_ready; // @[TLSerdes.scala:69:23] wire _ser_0_io_in_ready; // @[TLSerdes.scala:69:23] wire _out_channels_4_2_io_beat_valid; // @[TLSerdes.scala:63:50] wire [85:0] _out_channels_4_2_io_beat_bits_payload; // @[TLSerdes.scala:63:50] wire _out_channels_4_2_io_beat_bits_head; // @[TLSerdes.scala:63:50] wire _out_channels_4_2_io_beat_bits_tail; // @[TLSerdes.scala:63:50] wire _out_channels_2_2_io_beat_bits_head; // @[TLSerdes.scala:61:50] wire _out_channels_0_2_io_beat_bits_head; // @[TLSerdes.scala:59:50] wire auto_manager_in_a_valid_0 = auto_manager_in_a_valid; // @[TLSerdes.scala:39:9] wire [2:0] auto_manager_in_a_bits_opcode_0 = auto_manager_in_a_bits_opcode; // @[TLSerdes.scala:39:9] wire [2:0] auto_manager_in_a_bits_param_0 = auto_manager_in_a_bits_param; // @[TLSerdes.scala:39:9] wire [3:0] auto_manager_in_a_bits_size_0 = auto_manager_in_a_bits_size; // @[TLSerdes.scala:39:9] wire auto_manager_in_a_bits_source_0 = auto_manager_in_a_bits_source; // @[TLSerdes.scala:39:9] wire [31:0] auto_manager_in_a_bits_address_0 = auto_manager_in_a_bits_address; // @[TLSerdes.scala:39:9] wire [7:0] auto_manager_in_a_bits_mask_0 = auto_manager_in_a_bits_mask; // @[TLSerdes.scala:39:9] wire [63:0] auto_manager_in_a_bits_data_0 = auto_manager_in_a_bits_data; // @[TLSerdes.scala:39:9] wire auto_manager_in_a_bits_corrupt_0 = auto_manager_in_a_bits_corrupt; // @[TLSerdes.scala:39:9] wire auto_manager_in_d_ready_0 = auto_manager_in_d_ready; // @[TLSerdes.scala:39:9] wire io_ser_0_in_valid_0 = io_ser_0_in_valid; // @[TLSerdes.scala:39:9] wire [31:0] io_ser_0_in_bits_flit_0 = io_ser_0_in_bits_flit; // @[TLSerdes.scala:39:9] wire io_ser_0_out_ready_0 = io_ser_0_out_ready; // @[TLSerdes.scala:39:9] wire io_ser_1_in_valid_0 = io_ser_1_in_valid; // @[TLSerdes.scala:39:9] wire [31:0] io_ser_1_in_bits_flit_0 = io_ser_1_in_bits_flit; // @[TLSerdes.scala:39:9] wire io_ser_2_in_valid_0 = io_ser_2_in_valid; // @[TLSerdes.scala:39:9] wire [31:0] io_ser_2_in_bits_flit_0 = io_ser_2_in_bits_flit; // @[TLSerdes.scala:39:9] wire io_ser_2_out_ready_0 = io_ser_2_out_ready; // @[TLSerdes.scala:39:9] wire io_ser_3_in_valid_0 = io_ser_3_in_valid; // @[TLSerdes.scala:39:9] wire [31:0] io_ser_3_in_bits_flit_0 = io_ser_3_in_bits_flit; // @[TLSerdes.scala:39:9] wire io_ser_4_in_valid_0 = io_ser_4_in_valid; // @[TLSerdes.scala:39:9] wire [31:0] io_ser_4_in_bits_flit_0 = io_ser_4_in_bits_flit; // @[TLSerdes.scala:39:9] wire io_ser_4_out_ready_0 = io_ser_4_out_ready; // @[TLSerdes.scala:39:9] wire [2:0] client_tl_b_bits_opcode = 3'h0; // @[TLSerdes.scala:45:71] wire [2:0] client_tl_d_bits_opcode = 3'h0; // @[TLSerdes.scala:45:71] wire [2:0] _out_channels_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _out_channels_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] out_channels_2_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] out_channels_2_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _in_channels_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:264:74] wire [1:0] client_tl_b_bits_param = 2'h0; // @[TLSerdes.scala:45:71] wire [1:0] client_tl_d_bits_param = 2'h0; // @[TLSerdes.scala:45:71] wire [1:0] _in_channels_WIRE_bits_param = 2'h0; // @[Bundles.scala:264:74] wire [3:0] _out_channels_WIRE_bits_sink = 4'h0; // @[Bundles.scala:267:74] wire [3:0] out_channels_0_1_bits_sink = 4'h0; // @[Bundles.scala:267:61] wire [3:0] _out_channels_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] out_channels_2_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _in_channels_WIRE_bits_size = 4'h0; // @[Bundles.scala:264:74] wire [7:0] client_tl_b_bits_size = 8'h0; // @[TLSerdes.scala:45:71] wire [7:0] client_tl_b_bits_source = 8'h0; // @[TLSerdes.scala:45:71] wire [7:0] client_tl_b_bits_mask = 8'h0; // @[TLSerdes.scala:45:71] wire [7:0] client_tl_d_bits_size = 8'h0; // @[TLSerdes.scala:45:71] wire [7:0] client_tl_d_bits_source = 8'h0; // @[TLSerdes.scala:45:71] wire [7:0] client_tl_d_bits_sink = 8'h0; // @[TLSerdes.scala:45:71] wire [7:0] _in_channels_WIRE_bits_mask = 8'h0; // @[Bundles.scala:264:74] wire [63:0] client_tl_b_bits_address = 64'h0; // @[TLSerdes.scala:45:71] wire [63:0] client_tl_b_bits_data = 64'h0; // @[TLSerdes.scala:45:71] wire [63:0] client_tl_d_bits_data = 64'h0; // @[TLSerdes.scala:45:71] wire [63:0] _out_channels_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] out_channels_2_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _in_channels_WIRE_bits_data = 64'h0; // @[Bundles.scala:264:74] wire [31:0] io_ser_1_out_bits_flit = 32'h0; // @[TLSerdes.scala:39:9] wire [31:0] io_ser_3_out_bits_flit = 32'h0; // @[TLSerdes.scala:39:9] wire [31:0] _out_channels_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] out_channels_2_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _in_channels_WIRE_bits_address = 32'h0; // @[Bundles.scala:264:74] wire io_ser_1_out_ready = 1'h1; // @[TLSerdes.scala:39:9, :40:16, :59:50, :61:50] wire io_ser_3_out_ready = 1'h1; // @[TLSerdes.scala:39:9, :40:16, :59:50, :61:50] wire out_channels_0_1_ready = 1'h1; // @[TLSerdes.scala:39:9, :40:16, :59:50, :61:50] wire out_channels_2_1_ready = 1'h1; // @[TLSerdes.scala:39:9, :40:16, :59:50, :61:50] wire io_ser_0_out_valid = 1'h0; // @[TLSerdes.scala:39:9] wire io_ser_1_out_valid = 1'h0; // @[TLSerdes.scala:39:9] wire io_ser_3_out_valid = 1'h0; // @[TLSerdes.scala:39:9] wire managerNodeIn_a_ready; // @[MixedNode.scala:551:17] wire client_tl_a_ready = 1'h0; // @[TLSerdes.scala:45:71] wire client_tl_b_ready = 1'h0; // @[TLSerdes.scala:45:71] wire client_tl_b_valid = 1'h0; // @[TLSerdes.scala:45:71] wire client_tl_b_bits_corrupt = 1'h0; // @[TLSerdes.scala:45:71] wire client_tl_c_ready = 1'h0; // @[TLSerdes.scala:45:71] wire client_tl_d_ready = 1'h0; // @[TLSerdes.scala:45:71] wire client_tl_d_valid = 1'h0; // @[TLSerdes.scala:45:71] wire client_tl_d_bits_denied = 1'h0; // @[TLSerdes.scala:45:71] wire client_tl_d_bits_corrupt = 1'h0; // @[TLSerdes.scala:45:71] wire client_tl_e_ready = 1'h0; // @[TLSerdes.scala:45:71] wire _out_channels_WIRE_ready = 1'h0; // @[Bundles.scala:267:74] wire _out_channels_WIRE_valid = 1'h0; // @[Bundles.scala:267:74] wire out_channels_0_1_valid = 1'h0; // @[Bundles.scala:267:61] wire _out_channels_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:74] wire _out_channels_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:74] wire _out_channels_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _out_channels_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire out_channels_2_1_valid = 1'h0; // @[Bundles.scala:265:61] wire out_channels_2_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire out_channels_2_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _in_channels_WIRE_ready = 1'h0; // @[Bundles.scala:264:74] wire _in_channels_WIRE_valid = 1'h0; // @[Bundles.scala:264:74] wire _in_channels_WIRE_bits_source = 1'h0; // @[Bundles.scala:264:74] wire _in_channels_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:264:74] wire in_channels_3_1_ready = 1'h0; // @[Bundles.scala:264:61] wire managerNodeIn_a_valid = auto_manager_in_a_valid_0; // @[TLSerdes.scala:39:9] wire [2:0] managerNodeIn_a_bits_opcode = auto_manager_in_a_bits_opcode_0; // @[TLSerdes.scala:39:9] wire [2:0] managerNodeIn_a_bits_param = auto_manager_in_a_bits_param_0; // @[TLSerdes.scala:39:9] wire [3:0] managerNodeIn_a_bits_size = auto_manager_in_a_bits_size_0; // @[TLSerdes.scala:39:9] wire managerNodeIn_a_bits_source = auto_manager_in_a_bits_source_0; // @[TLSerdes.scala:39:9] wire [31:0] managerNodeIn_a_bits_address = auto_manager_in_a_bits_address_0; // @[TLSerdes.scala:39:9] wire [7:0] managerNodeIn_a_bits_mask = auto_manager_in_a_bits_mask_0; // @[TLSerdes.scala:39:9] wire [63:0] managerNodeIn_a_bits_data = auto_manager_in_a_bits_data_0; // @[TLSerdes.scala:39:9] wire managerNodeIn_a_bits_corrupt = auto_manager_in_a_bits_corrupt_0; // @[TLSerdes.scala:39:9] wire managerNodeIn_d_ready = auto_manager_in_d_ready_0; // @[TLSerdes.scala:39:9] wire managerNodeIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] managerNodeIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] managerNodeIn_d_bits_param; // @[MixedNode.scala:551:17] wire [3:0] managerNodeIn_d_bits_size; // @[MixedNode.scala:551:17] wire managerNodeIn_d_bits_source; // @[MixedNode.scala:551:17] wire [3:0] managerNodeIn_d_bits_sink; // @[MixedNode.scala:551:17] wire managerNodeIn_d_bits_denied; // @[MixedNode.scala:551:17] wire [63:0] managerNodeIn_d_bits_data; // @[MixedNode.scala:551:17] wire managerNodeIn_d_bits_corrupt; // @[MixedNode.scala:551:17] wire _io_debug_ser_busy_T_1; // @[package.scala:81:59] wire _io_debug_des_busy_T_3; // @[package.scala:81:59] wire auto_manager_in_a_ready_0; // @[TLSerdes.scala:39:9] wire [2:0] auto_manager_in_d_bits_opcode_0; // @[TLSerdes.scala:39:9] wire [1:0] auto_manager_in_d_bits_param_0; // @[TLSerdes.scala:39:9] wire [3:0] auto_manager_in_d_bits_size_0; // @[TLSerdes.scala:39:9] wire auto_manager_in_d_bits_source_0; // @[TLSerdes.scala:39:9] wire [3:0] auto_manager_in_d_bits_sink_0; // @[TLSerdes.scala:39:9] wire auto_manager_in_d_bits_denied_0; // @[TLSerdes.scala:39:9] wire [63:0] auto_manager_in_d_bits_data_0; // @[TLSerdes.scala:39:9] wire auto_manager_in_d_bits_corrupt_0; // @[TLSerdes.scala:39:9] wire auto_manager_in_d_valid_0; // @[TLSerdes.scala:39:9] wire io_ser_0_in_ready_0; // @[TLSerdes.scala:39:9] wire [31:0] io_ser_0_out_bits_flit_0; // @[TLSerdes.scala:39:9] wire io_ser_1_in_ready_0; // @[TLSerdes.scala:39:9] wire io_ser_2_in_ready_0; // @[TLSerdes.scala:39:9] wire [31:0] io_ser_2_out_bits_flit_0; // @[TLSerdes.scala:39:9] wire io_ser_2_out_valid_0; // @[TLSerdes.scala:39:9] wire io_ser_3_in_ready_0; // @[TLSerdes.scala:39:9] wire io_ser_4_in_ready_0; // @[TLSerdes.scala:39:9] wire [31:0] io_ser_4_out_bits_flit_0; // @[TLSerdes.scala:39:9] wire io_ser_4_out_valid_0; // @[TLSerdes.scala:39:9] wire io_debug_ser_busy; // @[TLSerdes.scala:39:9] wire io_debug_des_busy; // @[TLSerdes.scala:39:9] assign auto_manager_in_a_ready_0 = managerNodeIn_a_ready; // @[TLSerdes.scala:39:9] assign auto_manager_in_d_valid_0 = managerNodeIn_d_valid; // @[TLSerdes.scala:39:9] assign auto_manager_in_d_bits_opcode_0 = managerNodeIn_d_bits_opcode; // @[TLSerdes.scala:39:9] assign auto_manager_in_d_bits_param_0 = managerNodeIn_d_bits_param; // @[TLSerdes.scala:39:9] assign auto_manager_in_d_bits_size_0 = managerNodeIn_d_bits_size; // @[TLSerdes.scala:39:9] assign auto_manager_in_d_bits_source_0 = managerNodeIn_d_bits_source; // @[TLSerdes.scala:39:9] assign auto_manager_in_d_bits_sink_0 = managerNodeIn_d_bits_sink; // @[TLSerdes.scala:39:9] assign auto_manager_in_d_bits_denied_0 = managerNodeIn_d_bits_denied; // @[TLSerdes.scala:39:9] assign auto_manager_in_d_bits_data_0 = managerNodeIn_d_bits_data; // @[TLSerdes.scala:39:9] assign auto_manager_in_d_bits_corrupt_0 = managerNodeIn_d_bits_corrupt; // @[TLSerdes.scala:39:9] wire [2:0] client_tl_a_bits_opcode; // @[TLSerdes.scala:45:71] wire [2:0] client_tl_a_bits_param; // @[TLSerdes.scala:45:71] wire [7:0] client_tl_a_bits_size; // @[TLSerdes.scala:45:71] wire [7:0] client_tl_a_bits_source; // @[TLSerdes.scala:45:71] wire [63:0] client_tl_a_bits_address; // @[TLSerdes.scala:45:71] wire [7:0] client_tl_a_bits_mask; // @[TLSerdes.scala:45:71] wire [63:0] client_tl_a_bits_data; // @[TLSerdes.scala:45:71] wire client_tl_a_bits_corrupt; // @[TLSerdes.scala:45:71] wire client_tl_a_valid; // @[TLSerdes.scala:45:71] wire [2:0] client_tl_c_bits_opcode; // @[TLSerdes.scala:45:71] wire [2:0] client_tl_c_bits_param; // @[TLSerdes.scala:45:71] wire [7:0] client_tl_c_bits_size; // @[TLSerdes.scala:45:71] wire [7:0] client_tl_c_bits_source; // @[TLSerdes.scala:45:71] wire [63:0] client_tl_c_bits_address; // @[TLSerdes.scala:45:71] wire [63:0] client_tl_c_bits_data; // @[TLSerdes.scala:45:71] wire client_tl_c_bits_corrupt; // @[TLSerdes.scala:45:71] wire client_tl_c_valid; // @[TLSerdes.scala:45:71] wire [7:0] client_tl_e_bits_sink; // @[TLSerdes.scala:45:71] wire client_tl_e_valid; // @[TLSerdes.scala:45:71] wire _io_debug_ser_busy_T; // @[package.scala:81:59] assign _io_debug_ser_busy_T_1 = _io_debug_ser_busy_T \| _ser_4_io_busy; // @[TLSerdes.scala:69:23] assign io_debug_ser_busy = _io_debug_ser_busy_T_1; // @[TLSerdes.scala:39:9] wire [2:0] in_channels_3_1_bits_opcode; // @[Bundles.scala:264:61] wire [1:0] in_channels_3_1_bits_param; // @[Bundles.scala:264:61] wire [3:0] in_channels_3_1_bits_size; // @[Bundles.scala:264:61] wire in_channels_3_1_bits_source; // @[Bundles.scala:264:61] wire [31:0] in_channels_3_1_bits_address; // @[Bundles.scala:264:61] wire [7:0] in_channels_3_1_bits_mask; // @[Bundles.scala:264:61] wire [63:0] in_channels_3_1_bits_data; // @[Bundles.scala:264:61] wire in_channels_3_1_bits_corrupt; // @[Bundles.scala:264:61] wire in_channels_3_1_valid; // @[Bundles.scala:264:61] assign managerNodeIn_d_bits_size = _in_channels_1_2_io_protocol_bits_size[3:0]; // @[TLSerdes.scala:79:28, :85:9] assign managerNodeIn_d_bits_source = _in_channels_1_2_io_protocol_bits_source[0]; // @[TLSerdes.scala:79:28, :85:9] assign managerNodeIn_d_bits_sink = _in_channels_1_2_io_protocol_bits_sink[3:0]; // @[TLSerdes.scala:79:28, :85:9] assign in_channels_3_1_bits_size = _in_channels_3_2_io_protocol_bits_size[3:0]; // @[TLSerdes.scala:81:28, :85:9] assign in_channels_3_1_bits_source = _in_channels_3_2_io_protocol_bits_source[0]; // @[TLSerdes.scala:81:28, :85:9] assign in_channels_3_1_bits_address = _in_channels_3_2_io_protocol_bits_address[31:0]; // @[TLSerdes.scala:81:28, :85:9] wire _io_debug_des_busy_T; // @[package.scala:81:59] wire _io_debug_des_busy_T_1 = _io_debug_des_busy_T \| _des_2_io_busy; // @[TLSerdes.scala:86:23] wire _io_debug_des_busy_T_2 = _io_debug_des_busy_T_1 \| _des_3_io_busy; // @[TLSerdes.scala:86:23] assign _io_debug_des_busy_T_3 = _io_debug_des_busy_T_2 \| _des_4_io_busy; // @[TLSerdes.scala:86:23] assign io_debug_des_busy = _io_debug_des_busy_T_3; // @[TLSerdes.scala:39:9] TLMonitor_67 monitor ( // @[Nodes.scala:27:25] .clock (clock), .reset (reset), .io_in_a_ready (managerNodeIn_a_ready), // @[MixedNode.scala:551:17] .io_in_a_valid (managerNodeIn_a_valid), // @[MixedNode.scala:551:17] .io_in_a_bits_opcode (managerNodeIn_a_bits_opcode), // @[MixedNode.scala:551:17] .io_in_a_bits_param (managerNodeIn_a_bits_param), // @[MixedNode.scala:551:17] .io_in_a_bits_size (managerNodeIn_a_bits_size), // @[MixedNode.scala:551:17] .io_in_a_bits_source (managerNodeIn_a_bits_source), // @[MixedNode.scala:551:17] .io_in_a_bits_address (managerNodeIn_a_bits_address), // @[MixedNode.scala:551:17] .io_in_a_bits_mask (managerNodeIn_a_bits_mask), // @[MixedNode.scala:551:17] .io_in_a_bits_data (managerNodeIn_a_bits_data), // @[MixedNode.scala:551:17] .io_in_a_bits_corrupt (managerNodeIn_a_bits_corrupt), // @[MixedNode.scala:551:17] .io_in_d_ready (managerNodeIn_d_ready), // @[MixedNode.scala:551:17] .io_in_d_valid (managerNodeIn_d_valid), // @[MixedNode.scala:551:17] .io_in_d_bits_opcode (managerNodeIn_d_bits_opcode), // @[MixedNode.scala:551:17] .io_in_d_bits_param (managerNodeIn_d_bits_param), // @[MixedNode.scala:551:17] .io_in_d_bits_size (managerNodeIn_d_bits_size), // @[MixedNode.scala:551:17] .io_in_d_bits_source (managerNodeIn_d_bits_source), // @[MixedNode.scala:551:17] .io_in_d_bits_sink (managerNodeIn_d_bits_sink), // @[MixedNode.scala:551:17] .io_in_d_bits_denied (managerNodeIn_d_bits_denied), // @[MixedNode.scala:551:17] .io_in_d_bits_data (managerNodeIn_d_bits_data), // @[MixedNode.scala:551:17] .io_in_d_bits_corrupt (managerNodeIn_d_bits_corrupt) // @[MixedNode.scala:551:17] ); // @[Nodes.scala:27:25] TLEToBeat_SerialRAM_a64d64s8k8z8c out_channels_0_2 ( // @[TLSerdes.scala:59:50] .clock (clock), .reset (reset), .io_beat_ready (_ser_0_io_in_ready), // @[TLSerdes.scala:69:23] .io_beat_bits_head (_out_channels_0_2_io_beat_bits_head) ); // @[TLSerdes.scala:59:50] TLCToBeat_SerialRAM_a64d64s8k8z8c out_channels_2_2 ( // @[TLSerdes.scala:61:50] .clock (clock), .reset (reset), .io_beat_ready (_ser_2_io_in_ready), // @[TLSerdes.scala:69:23] .io_beat_bits_head (_out_channels_2_2_io_beat_bits_head) ); // @[TLSerdes.scala:61:50] TLAToBeat_SerialRAM_a64d64s8k8z8c out_channels_4_2 ( // @[TLSerdes.scala:63:50] .clock (clock), .reset (reset), .io_protocol_ready (managerNodeIn_a_ready), .io_protocol_valid (managerNodeIn_a_valid), // @[MixedNode.scala:551:17] .io_protocol_bits_opcode (managerNodeIn_a_bits_opcode), // @[MixedNode.scala:551:17] .io_protocol_bits_param (managerNodeIn_a_bits_param), // @[MixedNode.scala:551:17] .io_protocol_bits_size ({4'h0, managerNodeIn_a_bits_size}), // @[TLSerdes.scala:68:21] .io_protocol_bits_source ({7'h0, managerNodeIn_a_bits_source}), // @[TLSerdes.scala:68:21] .io_protocol_bits_address ({32'h0, managerNodeIn_a_bits_address}), // @[TLSerdes.scala:68:21] .io_protocol_bits_mask (managerNodeIn_a_bits_mask), // @[MixedNode.scala:551:17] .io_protocol_bits_data (managerNodeIn_a_bits_data), // @[MixedNode.scala:551:17] .io_protocol_bits_corrupt (managerNodeIn_a_bits_corrupt), // @[MixedNode.scala:551:17] .io_beat_ready (_ser_4_io_in_ready), // @[TLSerdes.scala:69:23] .io_beat_valid (_out_channels_4_2_io_beat_valid), .io_beat_bits_payload (_out_channels_4_2_io_beat_bits_payload), .io_beat_bits_head (_out_channels_4_2_io_beat_bits_head), .io_beat_bits_tail (_out_channels_4_2_io_beat_bits_tail) ); // @[TLSerdes.scala:63:50] GenericSerializer_TLBeatw10_f32 ser_0 ( // @[TLSerdes.scala:69:23] .clock (clock), .reset (reset), .io_in_ready (_ser_0_io_in_ready), .io_in_bits_head (_out_channels_0_2_io_beat_bits_head), // @[TLSerdes.scala:59:50] .io_out_ready (io_ser_0_out_ready_0), // @[TLSerdes.scala:39:9] .io_out_bits_flit (io_ser_0_out_bits_flit_0) ); // @[TLSerdes.scala:69:23] GenericSerializer_TLBeatw88_f32 ser_2 ( // @[TLSerdes.scala:69:23] .clock (clock), .reset (reset), .io_in_ready (_ser_2_io_in_ready), .io_in_bits_head (_out_channels_2_2_io_beat_bits_head), // @[TLSerdes.scala:61:50] .io_out_ready (io_ser_2_out_ready_0), // @[TLSerdes.scala:39:9] .io_out_valid (io_ser_2_out_valid_0), .io_out_bits_flit (io_ser_2_out_bits_flit_0), .io_busy (_io_debug_ser_busy_T) ); // @[TLSerdes.scala:69:23] GenericSerializer_TLBeatw88_f32_1 ser_4 ( // @[TLSerdes.scala:69:23] .clock (clock), .reset (reset), .io_in_ready (_ser_4_io_in_ready), .io_in_valid (_out_channels_4_2_io_beat_valid), // @[TLSerdes.scala:63:50] .io_in_bits_payload (_out_channels_4_2_io_beat_bits_payload), // @[TLSerdes.scala:63:50] .io_in_bits_head (_out_channels_4_2_io_beat_bits_head), // @[TLSerdes.scala:63:50] .io_in_bits_tail (_out_channels_4_2_io_beat_bits_tail), // @[TLSerdes.scala:63:50] .io_out_ready (io_ser_4_out_ready_0), // @[TLSerdes.scala:39:9] .io_out_valid (io_ser_4_out_valid_0), .io_out_bits_flit (io_ser_4_out_bits_flit_0), .io_busy (_ser_4_io_busy) ); // @[TLSerdes.scala:69:23] TLEFromBeat_SerialRAM_a64d64s8k8z8c in_channels_0_2 ( // @[TLSerdes.scala:78:28] .clock (clock), .reset (reset), .io_protocol_valid (client_tl_e_valid), .io_protocol_bits_sink (client_tl_e_bits_sink), .io_beat_ready (_in_channels_0_2_io_beat_ready), .io_beat_valid (_des_0_io_out_valid), // @[TLSerdes.scala:86:23] .io_beat_bits_payload (_des_0_io_out_bits_payload), // @[TLSerdes.scala:86:23] .io_beat_bits_head (_des_0_io_out_bits_head), // @[TLSerdes.scala:86:23] .io_beat_bits_tail (_des_0_io_out_bits_tail) // @[TLSerdes.scala:86:23] ); // @[TLSerdes.scala:78:28] TLDFromBeat_SerialRAM_a64d64s8k8z8c in_channels_1_2 ( // @[TLSerdes.scala:79:28] .clock (clock), .reset (reset), .io_protocol_ready (managerNodeIn_d_ready), // @[MixedNode.scala:551:17] .io_protocol_valid (managerNodeIn_d_valid), .io_protocol_bits_opcode (managerNodeIn_d_bits_opcode), .io_protocol_bits_param (managerNodeIn_d_bits_param), .io_protocol_bits_size (_in_channels_1_2_io_protocol_bits_size), .io_protocol_bits_source (_in_channels_1_2_io_protocol_bits_source), .io_protocol_bits_sink (_in_channels_1_2_io_protocol_bits_sink), .io_protocol_bits_denied (managerNodeIn_d_bits_denied), .io_protocol_bits_data (managerNodeIn_d_bits_data), .io_protocol_bits_corrupt (managerNodeIn_d_bits_corrupt), .io_beat_ready (_in_channels_1_2_io_beat_ready), .io_beat_valid (_des_1_io_out_valid), // @[TLSerdes.scala:86:23] .io_beat_bits_payload (_des_1_io_out_bits_payload), // @[TLSerdes.scala:86:23] .io_beat_bits_head (_des_1_io_out_bits_head), // @[TLSerdes.scala:86:23] .io_beat_bits_tail (_des_1_io_out_bits_tail) // @[TLSerdes.scala:86:23] ); // @[TLSerdes.scala:79:28] TLCFromBeat_SerialRAM_a64d64s8k8z8c in_channels_2_2 ( // @[TLSerdes.scala:80:28] .clock (clock), .reset (reset), .io_protocol_valid (client_tl_c_valid), .io_protocol_bits_opcode (client_tl_c_bits_opcode), .io_protocol_bits_param (client_tl_c_bits_param), .io_protocol_bits_size (client_tl_c_bits_size), .io_protocol_bits_source (client_tl_c_bits_source), .io_protocol_bits_address (client_tl_c_bits_address), .io_protocol_bits_data (client_tl_c_bits_data), .io_protocol_bits_corrupt (client_tl_c_bits_corrupt), .io_beat_ready (_in_channels_2_2_io_beat_ready), .io_beat_valid (_des_2_io_out_valid), // @[TLSerdes.scala:86:23] .io_beat_bits_payload (_des_2_io_out_bits_payload), // @[TLSerdes.scala:86:23] .io_beat_bits_head (_des_2_io_out_bits_head), // @[TLSerdes.scala:86:23] .io_beat_bits_tail (_des_2_io_out_bits_tail) // @[TLSerdes.scala:86:23] ); // @[TLSerdes.scala:80:28] TLBFromBeat_SerialRAM_a64d64s8k8z8c in_channels_3_2 ( // @[TLSerdes.scala:81:28] .clock (clock), .reset (reset), .io_protocol_valid (in_channels_3_1_valid), .io_protocol_bits_opcode (in_channels_3_1_bits_opcode), .io_protocol_bits_param (in_channels_3_1_bits_param), .io_protocol_bits_size (_in_channels_3_2_io_protocol_bits_size), .io_protocol_bits_source (_in_channels_3_2_io_protocol_bits_source), .io_protocol_bits_address (_in_channels_3_2_io_protocol_bits_address), .io_protocol_bits_mask (in_channels_3_1_bits_mask), .io_protocol_bits_data (in_channels_3_1_bits_data), .io_protocol_bits_corrupt (in_channels_3_1_bits_corrupt), .io_beat_ready (_in_channels_3_2_io_beat_ready), .io_beat_valid (_des_3_io_out_valid), // @[TLSerdes.scala:86:23] .io_beat_bits_payload (_des_3_io_out_bits_payload), // @[TLSerdes.scala:86:23] .io_beat_bits_head (_des_3_io_out_bits_head), // @[TLSerdes.scala:86:23] .io_beat_bits_tail (_des_3_io_out_bits_tail) // @[TLSerdes.scala:86:23] ); // @[TLSerdes.scala:81:28] TLAFromBeat_SerialRAM_a64d64s8k8z8c in_channels_4_2 ( // @[TLSerdes.scala:82:28] .clock (clock), .reset (reset), .io_protocol_valid (client_tl_a_valid), .io_protocol_bits_opcode (client_tl_a_bits_opcode), .io_protocol_bits_param (client_tl_a_bits_param), .io_protocol_bits_size (client_tl_a_bits_size), .io_protocol_bits_source (client_tl_a_bits_source), .io_protocol_bits_address (client_tl_a_bits_address), .io_protocol_bits_mask (client_tl_a_bits_mask), .io_protocol_bits_data (client_tl_a_bits_data), .io_protocol_bits_corrupt (client_tl_a_bits_corrupt), .io_beat_ready (_in_channels_4_2_io_beat_ready), .io_beat_valid (_des_4_io_out_valid), // @[TLSerdes.scala:86:23] .io_beat_bits_payload (_des_4_io_out_bits_payload), // @[TLSerdes.scala:86:23] .io_beat_bits_head (_des_4_io_out_bits_head), // @[TLSerdes.scala:86:23] .io_beat_bits_tail (_des_4_io_out_bits_tail) // @[TLSerdes.scala:86:23] ); // @[TLSerdes.scala:82:28] GenericDeserializer_TLBeatw10_f32_1 des_0 ( // @[TLSerdes.scala:86:23] .clock (clock), .reset (reset), .io_in_ready (io_ser_0_in_ready_0), .io_in_valid (io_ser_0_in_valid_0), // @[TLSerdes.scala:39:9] .io_in_bits_flit (io_ser_0_in_bits_flit_0), // @[TLSerdes.scala:39:9] .io_out_ready (_in_channels_0_2_io_beat_ready), // @[TLSerdes.scala:78:28] .io_out_valid (_des_0_io_out_valid), .io_out_bits_payload (_des_0_io_out_bits_payload), .io_out_bits_head (_des_0_io_out_bits_head), .io_out_bits_tail (_des_0_io_out_bits_tail) ); // @[TLSerdes.scala:86:23] GenericDeserializer_TLBeatw67_f32_1 des_1 ( // @[TLSerdes.scala:86:23] .clock (clock), .reset (reset), .io_in_ready (io_ser_1_in_ready_0), .io_in_valid (io_ser_1_in_valid_0), // @[TLSerdes.scala:39:9] .io_in_bits_flit (io_ser_1_in_bits_flit_0), // @[TLSerdes.scala:39:9] .io_out_ready (_in_channels_1_2_io_beat_ready), // @[TLSerdes.scala:79:28] .io_out_valid (_des_1_io_out_valid), .io_out_bits_payload (_des_1_io_out_bits_payload), .io_out_bits_head (_des_1_io_out_bits_head), .io_out_bits_tail (_des_1_io_out_bits_tail), .io_busy (_io_debug_des_busy_T) ); // @[TLSerdes.scala:86:23] GenericDeserializer_TLBeatw88_f32_2 des_2 ( // @[TLSerdes.scala:86:23] .clock (clock), .reset (reset), .io_in_ready (io_ser_2_in_ready_0), .io_in_valid (io_ser_2_in_valid_0), // @[TLSerdes.scala:39:9] .io_in_bits_flit (io_ser_2_in_bits_flit_0), // @[TLSerdes.scala:39:9] .io_out_ready (_in_channels_2_2_io_beat_ready), // @[TLSerdes.scala:80:28] .io_out_valid (_des_2_io_out_valid), .io_out_bits_payload (_des_2_io_out_bits_payload), .io_out_bits_head (_des_2_io_out_bits_head), .io_out_bits_tail (_des_2_io_out_bits_tail), .io_busy (_des_2_io_busy) ); // @[TLSerdes.scala:86:23] GenericDeserializer_TLBeatw87_f32_1 des_3 ( // @[TLSerdes.scala:86:23] .clock (clock), .reset (reset), .io_in_ready (io_ser_3_in_ready_0), .io_in_valid (io_ser_3_in_valid_0), // @[TLSerdes.scala:39:9] .io_in_bits_flit (io_ser_3_in_bits_flit_0), // @[TLSerdes.scala:39:9] .io_out_ready (_in_channels_3_2_io_beat_ready), // @[TLSerdes.scala:81:28] .io_out_valid (_des_3_io_out_valid), .io_out_bits_payload (_des_3_io_out_bits_payload), .io_out_bits_head (_des_3_io_out_bits_head), .io_out_bits_tail (_des_3_io_out_bits_tail), .io_busy (_des_3_io_busy) ); // @[TLSerdes.scala:86:23] GenericDeserializer_TLBeatw88_f32_3 des_4 ( // @[TLSerdes.scala:86:23] .clock (clock), .reset (reset), .io_in_ready (io_ser_4_in_ready_0), .io_in_valid (io_ser_4_in_valid_0), // @[TLSerdes.scala:39:9] .io_in_bits_flit (io_ser_4_in_bits_flit_0), // @[TLSerdes.scala:39:9] .io_out_ready (_in_channels_4_2_io_beat_ready), // @[TLSerdes.scala:82:28] .io_out_valid (_des_4_io_out_valid), .io_out_bits_payload (_des_4_io_out_bits_payload), .io_out_bits_head (_des_4_io_out_bits_head), .io_out_bits_tail (_des_4_io_out_bits_tail), .io_busy (_des_4_io_busy) ); // @[TLSerdes.scala:86:23] assign auto_manager_in_a_ready = auto_manager_in_a_ready_0; // @[TLSerdes.scala:39:9] assign auto_manager_in_d_valid = auto_manager_in_d_valid_0; // @[TLSerdes.scala:39:9] assign auto_manager_in_d_bits_opcode = auto_manager_in_d_bits_opcode_0; // @[TLSerdes.scala:39:9] assign auto_manager_in_d_bits_param = auto_manager_in_d_bits_param_0; // @[TLSerdes.scala:39:9] assign auto_manager_in_d_bits_size = auto_manager_in_d_bits_size_0; // @[TLSerdes.scala:39:9] assign auto_manager_in_d_bits_source = auto_manager_in_d_bits_source_0; // @[TLSerdes.scala:39:9] assign auto_manager_in_d_bits_sink = auto_manager_in_d_bits_sink_0; // @[TLSerdes.scala:39:9] assign auto_manager_in_d_bits_denied = auto_manager_in_d_bits_denied_0; // @[TLSerdes.scala:39:9] assign auto_manager_in_d_bits_data = auto_manager_in_d_bits_data_0; // @[TLSerdes.scala:39:9] assign auto_manager_in_d_bits_corrupt = auto_manager_in_d_bits_corrupt_0; // @[TLSerdes.scala:39:9] assign io_ser_0_in_ready = io_ser_0_in_ready_0; // @[TLSerdes.scala:39:9] assign io_ser_0_out_bits_flit = io_ser_0_out_bits_flit_0; // @[TLSerdes.scala:39:9] assign io_ser_1_in_ready = io_ser_1_in_ready_0; // @[TLSerdes.scala:39:9] assign io_ser_2_in_ready = io_ser_2_in_ready_0; // @[TLSerdes.scala:39:9] assign io_ser_2_out_valid = io_ser_2_out_valid_0; // @[TLSerdes.scala:39:9] assign io_ser_2_out_bits_flit = io_ser_2_out_bits_flit_0; // @[TLSerdes.scala:39:9] assign io_ser_3_in_ready = io_ser_3_in_ready_0; // @[TLSerdes.scala:39:9] assign io_ser_4_in_ready = io_ser_4_in_ready_0; // @[TLSerdes.scala:39:9] assign io_ser_4_out_valid = io_ser_4_out_valid_0; // @[TLSerdes.scala:39:9] assign io_ser_4_out_bits_flit = io_ser_4_out_bits_flit_0; // @[TLSerdes.scala:39:9] endmodule
Generate the Verilog code corresponding to the following Chisel files. File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /* Like Vec.apply(idx), but tolerates indices of mismatched width / def extract(idx: UInt): T = x((idx \| 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx \| 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def \| (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a \|\| b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_\|\|_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /* Any Data subtype that has a Bool member named valid. / type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /* converts from camel case to to underscores, also removing all spaces / def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /* converts spaces or underscores to hyphens, also lowering case / def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y \| (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y \|\| y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 \| 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /* Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation / def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File dcache.scala: //***************************************************************************** // Ported from Rocket-Chip // See LICENSE.Berkeley and LICENSE.SiFive in Rocket-Chip for license details. //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ package boom.v3.lsu import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.diplomacy._ import freechips.rocketchip.tilelink._ import freechips.rocketchip.tile._ import freechips.rocketchip.util._ import freechips.rocketchip.rocket._ import boom.v3.common._ import boom.v3.exu.BrUpdateInfo import boom.v3.util.{IsKilledByBranch, GetNewBrMask, BranchKillableQueue, IsOlder, UpdateBrMask, AgePriorityEncoder, WrapInc, Transpose} class BoomWritebackUnit(implicit edge: TLEdgeOut, p: Parameters) extends L1HellaCacheModule()(p) { val io = IO(new Bundle { val req = Flipped(Decoupled(new WritebackReq(edge.bundle))) val meta_read = Decoupled(new L1MetaReadReq) val resp = Output(Bool()) val idx = Output(Valid(UInt())) val data_req = Decoupled(new L1DataReadReq) val data_resp = Input(UInt(encRowBits.W)) val mem_grant = Input(Bool()) val release = Decoupled(new TLBundleC(edge.bundle)) val lsu_release = Decoupled(new TLBundleC(edge.bundle)) }) val req = Reg(new WritebackReq(edge.bundle)) val s_invalid :: s_fill_buffer :: s_lsu_release :: s_active :: s_grant :: Nil = Enum(5) val state = RegInit(s_invalid) val r1_data_req_fired = RegInit(false.B) val r2_data_req_fired = RegInit(false.B) val r1_data_req_cnt = Reg(UInt(log2Up(refillCycles+1).W)) val r2_data_req_cnt = Reg(UInt(log2Up(refillCycles+1).W)) val data_req_cnt = RegInit(0.U(log2Up(refillCycles+1).W)) val (_, last_beat, all_beats_done, beat_count) = edge.count(io.release) val wb_buffer = Reg(Vec(refillCycles, UInt(encRowBits.W))) val acked = RegInit(false.B) io.idx.valid := state =/= s_invalid io.idx.bits := req.idx io.release.valid := false.B io.release.bits := DontCare io.req.ready := false.B io.meta_read.valid := false.B io.meta_read.bits := DontCare io.data_req.valid := false.B io.data_req.bits := DontCare io.resp := false.B io.lsu_release.valid := false.B io.lsu_release.bits := DontCare val r_address = Cat(req.tag, req.idx) << blockOffBits val id = cfg.nMSHRs val probeResponse = edge.ProbeAck( fromSource = id.U, toAddress = r_address, lgSize = lgCacheBlockBytes.U, reportPermissions = req.param, data = wb_buffer(data_req_cnt)) val voluntaryRelease = edge.Release( fromSource = id.U, toAddress = r_address, lgSize = lgCacheBlockBytes.U, shrinkPermissions = req.param, data = wb_buffer(data_req_cnt))._2 when (state === s_invalid) { io.req.ready := true.B when (io.req.fire) { state := s_fill_buffer data_req_cnt := 0.U req := io.req.bits acked := false.B } } .elsewhen (state === s_fill_buffer) { io.meta_read.valid := data_req_cnt < refillCycles.U io.meta_read.bits.idx := req.idx io.meta_read.bits.tag := req.tag io.data_req.valid := data_req_cnt < refillCycles.U io.data_req.bits.way_en := req.way_en io.data_req.bits.addr := (if(refillCycles > 1) Cat(req.idx, data_req_cnt(log2Up(refillCycles)-1,0)) else req.idx) << rowOffBits r1_data_req_fired := false.B r1_data_req_cnt := 0.U r2_data_req_fired := r1_data_req_fired r2_data_req_cnt := r1_data_req_cnt when (io.data_req.fire && io.meta_read.fire) { r1_data_req_fired := true.B r1_data_req_cnt := data_req_cnt data_req_cnt := data_req_cnt + 1.U } when (r2_data_req_fired) { wb_buffer(r2_data_req_cnt) := io.data_resp when (r2_data_req_cnt === (refillCycles-1).U) { io.resp := true.B state := s_lsu_release data_req_cnt := 0.U } } } .elsewhen (state === s_lsu_release) { io.lsu_release.valid := true.B io.lsu_release.bits := probeResponse when (io.lsu_release.fire) { state := s_active } } .elsewhen (state === s_active) { io.release.valid := data_req_cnt < refillCycles.U io.release.bits := Mux(req.voluntary, voluntaryRelease, probeResponse) when (io.mem_grant) { acked := true.B } when (io.release.fire) { data_req_cnt := data_req_cnt + 1.U } when ((data_req_cnt === (refillCycles-1).U) && io.release.fire) { state := Mux(req.voluntary, s_grant, s_invalid) } } .elsewhen (state === s_grant) { when (io.mem_grant) { acked := true.B } when (acked) { state := s_invalid } } } class BoomProbeUnit(implicit edge: TLEdgeOut, p: Parameters) extends L1HellaCacheModule()(p) { val io = IO(new Bundle { val req = Flipped(Decoupled(new TLBundleB(edge.bundle))) val rep = Decoupled(new TLBundleC(edge.bundle)) val meta_read = Decoupled(new L1MetaReadReq) val meta_write = Decoupled(new L1MetaWriteReq) val wb_req = Decoupled(new WritebackReq(edge.bundle)) val way_en = Input(UInt(nWays.W)) val wb_rdy = Input(Bool()) // Is writeback unit currently busy? If so need to retry meta read when its done val mshr_rdy = Input(Bool()) // Is MSHR ready for this request to proceed? val mshr_wb_rdy = Output(Bool()) // Should we block MSHR writebacks while we finish our own? val block_state = Input(new ClientMetadata()) val lsu_release = Decoupled(new TLBundleC(edge.bundle)) val state = Output(Valid(UInt(coreMaxAddrBits.W))) }) val (s_invalid :: s_meta_read :: s_meta_resp :: s_mshr_req :: s_mshr_resp :: s_lsu_release :: s_release :: s_writeback_req :: s_writeback_resp :: s_meta_write :: s_meta_write_resp :: Nil) = Enum(11) val state = RegInit(s_invalid) val req = Reg(new TLBundleB(edge.bundle)) val req_idx = req.address(idxMSB, idxLSB) val req_tag = req.address >> untagBits val way_en = Reg(UInt()) val tag_matches = way_en.orR val old_coh = Reg(new ClientMetadata) val miss_coh = ClientMetadata.onReset val reply_coh = Mux(tag_matches, old_coh, miss_coh) val (is_dirty, report_param, new_coh) = reply_coh.onProbe(req.param) io.state.valid := state =/= s_invalid io.state.bits := req.address io.req.ready := state === s_invalid io.rep.valid := state === s_release io.rep.bits := edge.ProbeAck(req, report_param) assert(!io.rep.valid \|\| !edge.hasData(io.rep.bits), "ProbeUnit should not send ProbeAcks with data, WritebackUnit should handle it") io.meta_read.valid := state === s_meta_read io.meta_read.bits.idx := req_idx io.meta_read.bits.tag := req_tag io.meta_read.bits.way_en := ~(0.U(nWays.W)) io.meta_write.valid := state === s_meta_write io.meta_write.bits.way_en := way_en io.meta_write.bits.idx := req_idx io.meta_write.bits.tag := req_tag io.meta_write.bits.data.tag := req_tag io.meta_write.bits.data.coh := new_coh io.wb_req.valid := state === s_writeback_req io.wb_req.bits.source := req.source io.wb_req.bits.idx := req_idx io.wb_req.bits.tag := req_tag io.wb_req.bits.param := report_param io.wb_req.bits.way_en := way_en io.wb_req.bits.voluntary := false.B io.mshr_wb_rdy := !state.isOneOf(s_release, s_writeback_req, s_writeback_resp, s_meta_write, s_meta_write_resp) io.lsu_release.valid := state === s_lsu_release io.lsu_release.bits := edge.ProbeAck(req, report_param) // state === s_invalid when (state === s_invalid) { when (io.req.fire) { state := s_meta_read req := io.req.bits } } .elsewhen (state === s_meta_read) { when (io.meta_read.fire) { state := s_meta_resp } } .elsewhen (state === s_meta_resp) { // we need to wait one cycle for the metadata to be read from the array state := s_mshr_req } .elsewhen (state === s_mshr_req) { old_coh := io.block_state way_en := io.way_en // if the read didn't go through, we need to retry state := Mux(io.mshr_rdy && io.wb_rdy, s_mshr_resp, s_meta_read) } .elsewhen (state === s_mshr_resp) { state := Mux(tag_matches && is_dirty, s_writeback_req, s_lsu_release) } .elsewhen (state === s_lsu_release) { when (io.lsu_release.fire) { state := s_release } } .elsewhen (state === s_release) { when (io.rep.ready) { state := Mux(tag_matches, s_meta_write, s_invalid) } } .elsewhen (state === s_writeback_req) { when (io.wb_req.fire) { state := s_writeback_resp } } .elsewhen (state === s_writeback_resp) { // wait for the writeback request to finish before updating the metadata when (io.wb_req.ready) { state := s_meta_write } } .elsewhen (state === s_meta_write) { when (io.meta_write.fire) { state := s_meta_write_resp } } .elsewhen (state === s_meta_write_resp) { state := s_invalid } } class BoomL1MetaReadReq(implicit p: Parameters) extends BoomBundle()(p) { val req = Vec(memWidth, new L1MetaReadReq) } class BoomL1DataReadReq(implicit p: Parameters) extends BoomBundle()(p) { val req = Vec(memWidth, new L1DataReadReq) val valid = Vec(memWidth, Bool()) } abstract class AbstractBoomDataArray(implicit p: Parameters) extends BoomModule with HasL1HellaCacheParameters { val io = IO(new BoomBundle { val read = Input(Vec(memWidth, Valid(new L1DataReadReq))) val write = Input(Valid(new L1DataWriteReq)) val resp = Output(Vec(memWidth, Vec(nWays, Bits(encRowBits.W)))) val nacks = Output(Vec(memWidth, Bool())) }) def pipeMap[T <: Data](f: Int => T) = VecInit((0 until memWidth).map(f)) } class BoomDuplicatedDataArray(implicit p: Parameters) extends AbstractBoomDataArray { val waddr = io.write.bits.addr >> rowOffBits for (j <- 0 until memWidth) { val raddr = io.read(j).bits.addr >> rowOffBits for (w <- 0 until nWays) { val array = DescribedSRAM( name = s"array_${w}_${j}", desc = "Non-blocking DCache Data Array", size = nSets * refillCycles, data = Vec(rowWords, Bits(encDataBits.W)) ) when (io.write.bits.way_en(w) && io.write.valid) { val data = VecInit((0 until rowWords) map (i => io.write.bits.data(encDataBits(i+1)-1,encDataBitsi))) array.write(waddr, data, io.write.bits.wmask.asBools) } io.resp(j)(w) := RegNext(array.read(raddr, io.read(j).bits.way_en(w) && io.read(j).valid).asUInt) } io.nacks(j) := false.B } } class BoomBankedDataArray(implicit p: Parameters) extends AbstractBoomDataArray { val nBanks = boomParams.numDCacheBanks val bankSize = nSets * refillCycles / nBanks require (nBanks >= memWidth) require (bankSize > 0) val bankBits = log2Ceil(nBanks) val bankOffBits = log2Ceil(rowWords) + log2Ceil(wordBytes) val bidxBits = log2Ceil(bankSize) val bidxOffBits = bankOffBits + bankBits //---------------------------------------------------------------------------------------------------- val s0_rbanks = if (nBanks > 1) VecInit(io.read.map(r => (r.bits.addr >> bankOffBits)(bankBits-1,0))) else VecInit(0.U) val s0_wbank = if (nBanks > 1) (io.write.bits.addr >> bankOffBits)(bankBits-1,0) else 0.U val s0_ridxs = VecInit(io.read.map(r => (r.bits.addr >> bidxOffBits)(bidxBits-1,0))) val s0_widx = (io.write.bits.addr >> bidxOffBits)(bidxBits-1,0) val s0_read_valids = VecInit(io.read.map(_.valid)) val s0_bank_conflicts = pipeMap(w => (0 until w).foldLeft(false.B)((c,i) => c \|\| io.read(i).valid && s0_rbanks(i) === s0_rbanks(w))) val s0_do_bank_read = s0_read_valids zip s0_bank_conflicts map {case (v,c) => v && !c} val s0_bank_read_gnts = Transpose(VecInit(s0_rbanks zip s0_do_bank_read map {case (b,d) => VecInit((UIntToOH(b) & Fill(nBanks,d)).asBools)})) val s0_bank_write_gnt = (UIntToOH(s0_wbank) & Fill(nBanks, io.write.valid)).asBools //---------------------------------------------------------------------------------------------------- val s1_rbanks = RegNext(s0_rbanks) val s1_ridxs = RegNext(s0_ridxs) val s1_read_valids = RegNext(s0_read_valids) val s1_pipe_selection = pipeMap(i => VecInit(PriorityEncoderOH(pipeMap(j => if (j < i) s1_read_valids(j) && s1_rbanks(j) === s1_rbanks(i) else if (j == i) true.B else false.B)))) val s1_ridx_match = pipeMap(i => pipeMap(j => if (j < i) s1_ridxs(j) === s1_ridxs(i) else if (j == i) true.B else false.B)) val s1_nacks = pipeMap(w => s1_read_valids(w) && (s1_pipe_selection(w).asUInt & ~s1_ridx_match(w).asUInt).orR) val s1_bank_selection = pipeMap(w => Mux1H(s1_pipe_selection(w), s1_rbanks)) //---------------------------------------------------------------------------------------------------- val s2_bank_selection = RegNext(s1_bank_selection) val s2_nacks = RegNext(s1_nacks) for (w <- 0 until nWays) { val s2_bank_reads = Reg(Vec(nBanks, Bits(encRowBits.W))) for (b <- 0 until nBanks) { val array = DescribedSRAM( name = s"array_${w}_${b}", desc = "Non-blocking DCache Data Array", size = bankSize, data = Vec(rowWords, Bits(encDataBits.W)) ) val ridx = Mux1H(s0_bank_read_gnts(b), s0_ridxs) val way_en = Mux1H(s0_bank_read_gnts(b), io.read.map(_.bits.way_en)) s2_bank_reads(b) := array.read(ridx, way_en(w) && s0_bank_read_gnts(b).reduce(_\|\|_)).asUInt when (io.write.bits.way_en(w) && s0_bank_write_gnt(b)) { val data = VecInit((0 until rowWords) map (i => io.write.bits.data(encDataBits(i+1)-1,encDataBitsi))) array.write(s0_widx, data, io.write.bits.wmask.asBools) } } for (i <- 0 until memWidth) { io.resp(i)(w) := s2_bank_reads(s2_bank_selection(i)) } } io.nacks := s2_nacks } /** * Top level class wrapping a non-blocking dcache. * * @param hartid hardware thread for the cache / class BoomNonBlockingDCache(staticIdForMetadataUseOnly: Int)(implicit p: Parameters) extends LazyModule { private val tileParams = p(TileKey) protected val cfg = tileParams.dcache.get protected def cacheClientParameters = cfg.scratch.map(x => Seq()).getOrElse(Seq(TLMasterParameters.v1( name = s"Core ${staticIdForMetadataUseOnly} DCache", sourceId = IdRange(0, 1 max (cfg.nMSHRs + 1)), supportsProbe = TransferSizes(cfg.blockBytes, cfg.blockBytes)))) protected def mmioClientParameters = Seq(TLMasterParameters.v1( name = s"Core ${staticIdForMetadataUseOnly} DCache MMIO", sourceId = IdRange(cfg.nMSHRs + 1, cfg.nMSHRs + 1 + cfg.nMMIOs), requestFifo = true)) val node = TLClientNode(Seq(TLMasterPortParameters.v1( cacheClientParameters ++ mmioClientParameters, minLatency = 1))) lazy val module = new BoomNonBlockingDCacheModule(this) def flushOnFenceI = cfg.scratch.isEmpty && !node.edges.out(0).manager.managers.forall(m => !m.supportsAcquireT \|\| !m.executable \|\| m.regionType >= RegionType.TRACKED \|\| m.regionType <= RegionType.IDEMPOTENT) require(!tileParams.core.haveCFlush \|\| cfg.scratch.isEmpty, "CFLUSH_D_L1 instruction requires a D$") } class BoomDCacheBundle(implicit p: Parameters, edge: TLEdgeOut) extends BoomBundle()(p) { val lsu = Flipped(new LSUDMemIO) } class BoomNonBlockingDCacheModule(outer: BoomNonBlockingDCache) extends LazyModuleImp(outer) with HasL1HellaCacheParameters with HasBoomCoreParameters { implicit val edge = outer.node.edges.out(0) val (tl_out, _) = outer.node.out(0) val io = IO(new BoomDCacheBundle) private val fifoManagers = edge.manager.managers.filter(TLFIFOFixer.allVolatile) fifoManagers.foreach { m => require (m.fifoId == fifoManagers.head.fifoId, s"IOMSHRs must be FIFO for all regions with effects, but HellaCache sees ${m.nodePath.map(_.name)}") } def widthMap[T <: Data](f: Int => T) = VecInit((0 until memWidth).map(f)) val t_replay :: t_probe :: t_wb :: t_mshr_meta_read :: t_lsu :: t_prefetch :: Nil = Enum(6) val wb = Module(new BoomWritebackUnit) val prober = Module(new BoomProbeUnit) val mshrs = Module(new BoomMSHRFile) mshrs.io.clear_all := io.lsu.force_order mshrs.io.brupdate := io.lsu.brupdate mshrs.io.exception := io.lsu.exception mshrs.io.rob_pnr_idx := io.lsu.rob_pnr_idx mshrs.io.rob_head_idx := io.lsu.rob_head_idx // tags def onReset = L1Metadata(0.U, ClientMetadata.onReset) val meta = Seq.fill(memWidth) { Module(new L1MetadataArray(onReset _)) } val metaWriteArb = Module(new Arbiter(new L1MetaWriteReq, 2)) // 0 goes to MSHR refills, 1 goes to prober val metaReadArb = Module(new Arbiter(new BoomL1MetaReadReq, 6)) // 0 goes to MSHR replays, 1 goes to prober, 2 goes to wb, 3 goes to MSHR meta read, // 4 goes to pipeline, 5 goes to prefetcher metaReadArb.io.in := DontCare for (w <- 0 until memWidth) { meta(w).io.write.valid := metaWriteArb.io.out.fire meta(w).io.write.bits := metaWriteArb.io.out.bits meta(w).io.read.valid := metaReadArb.io.out.valid meta(w).io.read.bits := metaReadArb.io.out.bits.req(w) } metaReadArb.io.out.ready := meta.map(_.io.read.ready).reduce(_\|\|_) metaWriteArb.io.out.ready := meta.map(_.io.write.ready).reduce(_\|\|_) // data val data = Module(if (boomParams.numDCacheBanks == 1) new BoomDuplicatedDataArray else new BoomBankedDataArray) val dataWriteArb = Module(new Arbiter(new L1DataWriteReq, 2)) // 0 goes to pipeline, 1 goes to MSHR refills val dataReadArb = Module(new Arbiter(new BoomL1DataReadReq, 3)) // 0 goes to MSHR replays, 1 goes to wb, 2 goes to pipeline dataReadArb.io.in := DontCare for (w <- 0 until memWidth) { data.io.read(w).valid := dataReadArb.io.out.bits.valid(w) && dataReadArb.io.out.valid data.io.read(w).bits := dataReadArb.io.out.bits.req(w) } dataReadArb.io.out.ready := true.B data.io.write.valid := dataWriteArb.io.out.fire data.io.write.bits := dataWriteArb.io.out.bits dataWriteArb.io.out.ready := true.B // ------------ // New requests io.lsu.req.ready := metaReadArb.io.in(4).ready && dataReadArb.io.in(2).ready metaReadArb.io.in(4).valid := io.lsu.req.valid dataReadArb.io.in(2).valid := io.lsu.req.valid for (w <- 0 until memWidth) { // Tag read for new requests metaReadArb.io.in(4).bits.req(w).idx := io.lsu.req.bits(w).bits.addr >> blockOffBits metaReadArb.io.in(4).bits.req(w).way_en := DontCare metaReadArb.io.in(4).bits.req(w).tag := DontCare // Data read for new requests dataReadArb.io.in(2).bits.valid(w) := io.lsu.req.bits(w).valid dataReadArb.io.in(2).bits.req(w).addr := io.lsu.req.bits(w).bits.addr dataReadArb.io.in(2).bits.req(w).way_en := ~0.U(nWays.W) } // ------------ // MSHR Replays val replay_req = Wire(Vec(memWidth, new BoomDCacheReq)) replay_req := DontCare replay_req(0).uop := mshrs.io.replay.bits.uop replay_req(0).addr := mshrs.io.replay.bits.addr replay_req(0).data := mshrs.io.replay.bits.data replay_req(0).is_hella := mshrs.io.replay.bits.is_hella mshrs.io.replay.ready := metaReadArb.io.in(0).ready && dataReadArb.io.in(0).ready // Tag read for MSHR replays // We don't actually need to read the metadata, for replays we already know our way metaReadArb.io.in(0).valid := mshrs.io.replay.valid metaReadArb.io.in(0).bits.req(0).idx := mshrs.io.replay.bits.addr >> blockOffBits metaReadArb.io.in(0).bits.req(0).way_en := DontCare metaReadArb.io.in(0).bits.req(0).tag := DontCare // Data read for MSHR replays dataReadArb.io.in(0).valid := mshrs.io.replay.valid dataReadArb.io.in(0).bits.req(0).addr := mshrs.io.replay.bits.addr dataReadArb.io.in(0).bits.req(0).way_en := mshrs.io.replay.bits.way_en dataReadArb.io.in(0).bits.valid := widthMap(w => (w == 0).B) // ----------- // MSHR Meta read val mshr_read_req = Wire(Vec(memWidth, new BoomDCacheReq)) mshr_read_req := DontCare mshr_read_req(0).uop := NullMicroOp mshr_read_req(0).addr := Cat(mshrs.io.meta_read.bits.tag, mshrs.io.meta_read.bits.idx) << blockOffBits mshr_read_req(0).data := DontCare mshr_read_req(0).is_hella := false.B metaReadArb.io.in(3).valid := mshrs.io.meta_read.valid metaReadArb.io.in(3).bits.req(0) := mshrs.io.meta_read.bits mshrs.io.meta_read.ready := metaReadArb.io.in(3).ready // ----------- // Write-backs val wb_fire = wb.io.meta_read.fire && wb.io.data_req.fire val wb_req = Wire(Vec(memWidth, new BoomDCacheReq)) wb_req := DontCare wb_req(0).uop := NullMicroOp wb_req(0).addr := Cat(wb.io.meta_read.bits.tag, wb.io.data_req.bits.addr) wb_req(0).data := DontCare wb_req(0).is_hella := false.B // Couple the two decoupled interfaces of the WBUnit's meta_read and data_read // Tag read for write-back metaReadArb.io.in(2).valid := wb.io.meta_read.valid metaReadArb.io.in(2).bits.req(0) := wb.io.meta_read.bits wb.io.meta_read.ready := metaReadArb.io.in(2).ready && dataReadArb.io.in(1).ready // Data read for write-back dataReadArb.io.in(1).valid := wb.io.data_req.valid dataReadArb.io.in(1).bits.req(0) := wb.io.data_req.bits dataReadArb.io.in(1).bits.valid := widthMap(w => (w == 0).B) wb.io.data_req.ready := metaReadArb.io.in(2).ready && dataReadArb.io.in(1).ready assert(!(wb.io.meta_read.fire ^ wb.io.data_req.fire)) // ------- // Prober val prober_fire = prober.io.meta_read.fire val prober_req = Wire(Vec(memWidth, new BoomDCacheReq)) prober_req := DontCare prober_req(0).uop := NullMicroOp prober_req(0).addr := Cat(prober.io.meta_read.bits.tag, prober.io.meta_read.bits.idx) << blockOffBits prober_req(0).data := DontCare prober_req(0).is_hella := false.B // Tag read for prober metaReadArb.io.in(1).valid := prober.io.meta_read.valid metaReadArb.io.in(1).bits.req(0) := prober.io.meta_read.bits prober.io.meta_read.ready := metaReadArb.io.in(1).ready // Prober does not need to read data array // ------- // Prefetcher val prefetch_fire = mshrs.io.prefetch.fire val prefetch_req = Wire(Vec(memWidth, new BoomDCacheReq)) prefetch_req := DontCare prefetch_req(0) := mshrs.io.prefetch.bits // Tag read for prefetch metaReadArb.io.in(5).valid := mshrs.io.prefetch.valid metaReadArb.io.in(5).bits.req(0).idx := mshrs.io.prefetch.bits.addr >> blockOffBits metaReadArb.io.in(5).bits.req(0).way_en := DontCare metaReadArb.io.in(5).bits.req(0).tag := DontCare mshrs.io.prefetch.ready := metaReadArb.io.in(5).ready // Prefetch does not need to read data array val s0_valid = Mux(io.lsu.req.fire, VecInit(io.lsu.req.bits.map(_.valid)), Mux(mshrs.io.replay.fire \|\| wb_fire \|\| prober_fire \|\| prefetch_fire \|\| mshrs.io.meta_read.fire, VecInit(1.U(memWidth.W).asBools), VecInit(0.U(memWidth.W).asBools))) val s0_req = Mux(io.lsu.req.fire , VecInit(io.lsu.req.bits.map(_.bits)), Mux(wb_fire , wb_req, Mux(prober_fire , prober_req, Mux(prefetch_fire , prefetch_req, Mux(mshrs.io.meta_read.fire, mshr_read_req , replay_req))))) val s0_type = Mux(io.lsu.req.fire , t_lsu, Mux(wb_fire , t_wb, Mux(prober_fire , t_probe, Mux(prefetch_fire , t_prefetch, Mux(mshrs.io.meta_read.fire, t_mshr_meta_read , t_replay))))) // Does this request need to send a response or nack val s0_send_resp_or_nack = Mux(io.lsu.req.fire, s0_valid, VecInit(Mux(mshrs.io.replay.fire && isRead(mshrs.io.replay.bits.uop.mem_cmd), 1.U(memWidth.W), 0.U(memWidth.W)).asBools)) val s1_req = RegNext(s0_req) for (w <- 0 until memWidth) s1_req(w).uop.br_mask := GetNewBrMask(io.lsu.brupdate, s0_req(w).uop) val s2_store_failed = Wire(Bool()) val s1_valid = widthMap(w => RegNext(s0_valid(w) && !IsKilledByBranch(io.lsu.brupdate, s0_req(w).uop) && !(io.lsu.exception && s0_req(w).uop.uses_ldq) && !(s2_store_failed && io.lsu.req.fire && s0_req(w).uop.uses_stq), init=false.B)) for (w <- 0 until memWidth) assert(!(io.lsu.s1_kill(w) && !RegNext(io.lsu.req.fire) && !RegNext(io.lsu.req.bits(w).valid))) val s1_addr = s1_req.map(_.addr) val s1_nack = s1_addr.map(a => a(idxMSB,idxLSB) === prober.io.meta_write.bits.idx && !prober.io.req.ready) val s1_send_resp_or_nack = RegNext(s0_send_resp_or_nack) val s1_type = RegNext(s0_type) val s1_mshr_meta_read_way_en = RegNext(mshrs.io.meta_read.bits.way_en) val s1_replay_way_en = RegNext(mshrs.io.replay.bits.way_en) // For replays, the metadata isn't written yet val s1_wb_way_en = RegNext(wb.io.data_req.bits.way_en) // tag check def wayMap[T <: Data](f: Int => T) = VecInit((0 until nWays).map(f)) val s1_tag_eq_way = widthMap(i => wayMap((w: Int) => meta(i).io.resp(w).tag === (s1_addr(i) >> untagBits)).asUInt) val s1_tag_match_way = widthMap(i => Mux(s1_type === t_replay, s1_replay_way_en, Mux(s1_type === t_wb, s1_wb_way_en, Mux(s1_type === t_mshr_meta_read, s1_mshr_meta_read_way_en, wayMap((w: Int) => s1_tag_eq_way(i)(w) && meta(i).io.resp(w).coh.isValid()).asUInt)))) val s1_wb_idx_matches = widthMap(i => (s1_addr(i)(untagBits-1,blockOffBits) === wb.io.idx.bits) && wb.io.idx.valid) val s2_req = RegNext(s1_req) val s2_type = RegNext(s1_type) val s2_valid = widthMap(w => RegNext(s1_valid(w) && !io.lsu.s1_kill(w) && !IsKilledByBranch(io.lsu.brupdate, s1_req(w).uop) && !(io.lsu.exception && s1_req(w).uop.uses_ldq) && !(s2_store_failed && (s1_type === t_lsu) && s1_req(w).uop.uses_stq))) for (w <- 0 until memWidth) s2_req(w).uop.br_mask := GetNewBrMask(io.lsu.brupdate, s1_req(w).uop) val s2_tag_match_way = RegNext(s1_tag_match_way) val s2_tag_match = s2_tag_match_way.map(_.orR) val s2_hit_state = widthMap(i => Mux1H(s2_tag_match_way(i), wayMap((w: Int) => RegNext(meta(i).io.resp(w).coh)))) val s2_has_permission = widthMap(w => s2_hit_state(w).onAccess(s2_req(w).uop.mem_cmd)._1) val s2_new_hit_state = widthMap(w => s2_hit_state(w).onAccess(s2_req(w).uop.mem_cmd)._3) val s2_hit = widthMap(w => (s2_tag_match(w) && s2_has_permission(w) && s2_hit_state(w) === s2_new_hit_state(w) && !mshrs.io.block_hit(w)) \|\| s2_type.isOneOf(t_replay, t_wb)) val s2_nack = Wire(Vec(memWidth, Bool())) assert(!(s2_type === t_replay && !s2_hit(0)), "Replays should always hit") assert(!(s2_type === t_wb && !s2_hit(0)), "Writeback should always see data hit") val s2_wb_idx_matches = RegNext(s1_wb_idx_matches) // lr/sc val debug_sc_fail_addr = RegInit(0.U) val debug_sc_fail_cnt = RegInit(0.U(8.W)) val lrsc_count = RegInit(0.U(log2Ceil(lrscCycles).W)) val lrsc_valid = lrsc_count > lrscBackoff.U val lrsc_addr = Reg(UInt()) val s2_lr = s2_req(0).uop.mem_cmd === M_XLR && (!RegNext(s1_nack(0)) \|\| s2_type === t_replay) val s2_sc = s2_req(0).uop.mem_cmd === M_XSC && (!RegNext(s1_nack(0)) \|\| s2_type === t_replay) val s2_lrsc_addr_match = widthMap(w => lrsc_valid && lrsc_addr === (s2_req(w).addr >> blockOffBits)) val s2_sc_fail = s2_sc && !s2_lrsc_addr_match(0) when (lrsc_count > 0.U) { lrsc_count := lrsc_count - 1.U } when (s2_valid(0) && ((s2_type === t_lsu && s2_hit(0) && !s2_nack(0)) \|\| (s2_type === t_replay && s2_req(0).uop.mem_cmd =/= M_FLUSH_ALL))) { when (s2_lr) { lrsc_count := (lrscCycles - 1).U lrsc_addr := s2_req(0).addr >> blockOffBits } when (lrsc_count > 0.U) { lrsc_count := 0.U } } for (w <- 0 until memWidth) { when (s2_valid(w) && s2_type === t_lsu && !s2_hit(w) && !(s2_has_permission(w) && s2_tag_match(w)) && s2_lrsc_addr_match(w) && !s2_nack(w)) { lrsc_count := 0.U } } when (s2_valid(0)) { when (s2_req(0).addr === debug_sc_fail_addr) { when (s2_sc_fail) { debug_sc_fail_cnt := debug_sc_fail_cnt + 1.U } .elsewhen (s2_sc) { debug_sc_fail_cnt := 0.U } } .otherwise { when (s2_sc_fail) { debug_sc_fail_addr := s2_req(0).addr debug_sc_fail_cnt := 1.U } } } assert(debug_sc_fail_cnt < 100.U, "L1DCache failed too many SCs in a row") val s2_data = Wire(Vec(memWidth, Vec(nWays, UInt(encRowBits.W)))) for (i <- 0 until memWidth) { for (w <- 0 until nWays) { s2_data(i)(w) := data.io.resp(i)(w) } } val s2_data_muxed = widthMap(w => Mux1H(s2_tag_match_way(w), s2_data(w))) val s2_word_idx = widthMap(w => if (rowWords == 1) 0.U else s2_req(w).addr(log2Up(rowWordswordBytes)-1, log2Up(wordBytes))) // replacement policy val replacer = cacheParams.replacement val s1_replaced_way_en = UIntToOH(replacer.way) val s2_replaced_way_en = UIntToOH(RegNext(replacer.way)) val s2_repl_meta = widthMap(i => Mux1H(s2_replaced_way_en, wayMap((w: Int) => RegNext(meta(i).io.resp(w))).toSeq)) // nack because of incoming probe val s2_nack_hit = RegNext(VecInit(s1_nack)) // Nack when we hit something currently being evicted val s2_nack_victim = widthMap(w => s2_valid(w) && s2_hit(w) && mshrs.io.secondary_miss(w)) // MSHRs not ready for request val s2_nack_miss = widthMap(w => s2_valid(w) && !s2_hit(w) && !mshrs.io.req(w).ready) // Bank conflict on data arrays val s2_nack_data = widthMap(w => data.io.nacks(w)) // Can't allocate MSHR for same set currently being written back val s2_nack_wb = widthMap(w => s2_valid(w) && !s2_hit(w) && s2_wb_idx_matches(w)) s2_nack := widthMap(w => (s2_nack_miss(w) \|\| s2_nack_hit(w) \|\| s2_nack_victim(w) \|\| s2_nack_data(w) \|\| s2_nack_wb(w)) && s2_type =/= t_replay) val s2_send_resp = widthMap(w => (RegNext(s1_send_resp_or_nack(w)) && !s2_nack(w) && (s2_hit(w) \|\| (mshrs.io.req(w).fire && isWrite(s2_req(w).uop.mem_cmd) && !isRead(s2_req(w).uop.mem_cmd))))) val s2_send_nack = widthMap(w => (RegNext(s1_send_resp_or_nack(w)) && s2_nack(w))) for (w <- 0 until memWidth) assert(!(s2_send_resp(w) && s2_send_nack(w))) // hits always send a response // If MSHR is not available, LSU has to replay this request later // If MSHR is available and this is only a store(not a amo), we don't need to wait for resp later s2_store_failed := s2_valid(0) && s2_nack(0) && s2_send_nack(0) && s2_req(0).uop.uses_stq // Miss handling for (w <- 0 until memWidth) { mshrs.io.req(w).valid := s2_valid(w) && !s2_hit(w) && !s2_nack_hit(w) && !s2_nack_victim(w) && !s2_nack_data(w) && !s2_nack_wb(w) && s2_type.isOneOf(t_lsu, t_prefetch) && !IsKilledByBranch(io.lsu.brupdate, s2_req(w).uop) && !(io.lsu.exception && s2_req(w).uop.uses_ldq) && (isPrefetch(s2_req(w).uop.mem_cmd) \|\| isRead(s2_req(w).uop.mem_cmd) \|\| isWrite(s2_req(w).uop.mem_cmd)) assert(!(mshrs.io.req(w).valid && s2_type === t_replay), "Replays should not need to go back into MSHRs") mshrs.io.req(w).bits := DontCare mshrs.io.req(w).bits.uop := s2_req(w).uop mshrs.io.req(w).bits.uop.br_mask := GetNewBrMask(io.lsu.brupdate, s2_req(w).uop) mshrs.io.req(w).bits.addr := s2_req(w).addr mshrs.io.req(w).bits.tag_match := s2_tag_match(w) mshrs.io.req(w).bits.old_meta := Mux(s2_tag_match(w), L1Metadata(s2_repl_meta(w).tag, s2_hit_state(w)), s2_repl_meta(w)) mshrs.io.req(w).bits.way_en := Mux(s2_tag_match(w), s2_tag_match_way(w), s2_replaced_way_en) mshrs.io.req(w).bits.data := s2_req(w).data mshrs.io.req(w).bits.is_hella := s2_req(w).is_hella mshrs.io.req_is_probe(w) := s2_type === t_probe && s2_valid(w) } mshrs.io.meta_resp.valid := !s2_nack_hit(0) \|\| prober.io.mshr_wb_rdy mshrs.io.meta_resp.bits := Mux1H(s2_tag_match_way(0), RegNext(meta(0).io.resp)) when (mshrs.io.req.map(_.fire).reduce(_\|\|_)) { replacer.miss } tl_out.a <> mshrs.io.mem_acquire // probes and releases prober.io.req.valid := tl_out.b.valid && !lrsc_valid tl_out.b.ready := prober.io.req.ready && !lrsc_valid prober.io.req.bits := tl_out.b.bits prober.io.way_en := s2_tag_match_way(0) prober.io.block_state := s2_hit_state(0) metaWriteArb.io.in(1) <> prober.io.meta_write prober.io.mshr_rdy := mshrs.io.probe_rdy prober.io.wb_rdy := (prober.io.meta_write.bits.idx =/= wb.io.idx.bits) \|\| !wb.io.idx.valid mshrs.io.prober_state := prober.io.state // refills when (tl_out.d.bits.source === cfg.nMSHRs.U) { // This should be ReleaseAck tl_out.d.ready := true.B mshrs.io.mem_grant.valid := false.B mshrs.io.mem_grant.bits := DontCare } .otherwise { // This should be GrantData mshrs.io.mem_grant <> tl_out.d } dataWriteArb.io.in(1) <> mshrs.io.refill metaWriteArb.io.in(0) <> mshrs.io.meta_write tl_out.e <> mshrs.io.mem_finish // writebacks val wbArb = Module(new Arbiter(new WritebackReq(edge.bundle), 2)) // 0 goes to prober, 1 goes to MSHR evictions wbArb.io.in(0) <> prober.io.wb_req wbArb.io.in(1) <> mshrs.io.wb_req wb.io.req <> wbArb.io.out wb.io.data_resp := s2_data_muxed(0) mshrs.io.wb_resp := wb.io.resp wb.io.mem_grant := tl_out.d.fire && tl_out.d.bits.source === cfg.nMSHRs.U val lsu_release_arb = Module(new Arbiter(new TLBundleC(edge.bundle), 2)) io.lsu.release <> lsu_release_arb.io.out lsu_release_arb.io.in(0) <> wb.io.lsu_release lsu_release_arb.io.in(1) <> prober.io.lsu_release TLArbiter.lowest(edge, tl_out.c, wb.io.release, prober.io.rep) io.lsu.perf.release := edge.done(tl_out.c) io.lsu.perf.acquire := edge.done(tl_out.a) // load data gen val s2_data_word_prebypass = widthMap(w => s2_data_muxed(w) >> Cat(s2_word_idx(w), 0.U(log2Ceil(coreDataBits).W))) val s2_data_word = Wire(Vec(memWidth, UInt())) val loadgen = (0 until memWidth).map { w => new LoadGen(s2_req(w).uop.mem_size, s2_req(w).uop.mem_signed, s2_req(w).addr, s2_data_word(w), s2_sc && (w == 0).B, wordBytes) } // Mux between cache responses and uncache responses val cache_resp = Wire(Vec(memWidth, Valid(new BoomDCacheResp))) for (w <- 0 until memWidth) { cache_resp(w).valid := s2_valid(w) && s2_send_resp(w) cache_resp(w).bits.uop := s2_req(w).uop cache_resp(w).bits.data := loadgen(w).data \| s2_sc_fail cache_resp(w).bits.is_hella := s2_req(w).is_hella } val uncache_resp = Wire(Valid(new BoomDCacheResp)) uncache_resp.bits := mshrs.io.resp.bits uncache_resp.valid := mshrs.io.resp.valid mshrs.io.resp.ready := !(cache_resp.map(_.valid).reduce(_&&_)) // We can backpressure the MSHRs, but not cache hits val resp = WireInit(cache_resp) var uncache_responding = false.B for (w <- 0 until memWidth) { val uncache_respond = !cache_resp(w).valid && !uncache_responding when (uncache_respond) { resp(w) := uncache_resp } uncache_responding = uncache_responding \|\| uncache_respond } for (w <- 0 until memWidth) { io.lsu.resp(w).valid := resp(w).valid && !(io.lsu.exception && resp(w).bits.uop.uses_ldq) && !IsKilledByBranch(io.lsu.brupdate, resp(w).bits.uop) io.lsu.resp(w).bits := UpdateBrMask(io.lsu.brupdate, resp(w).bits) io.lsu.nack(w).valid := s2_valid(w) && s2_send_nack(w) && !(io.lsu.exception && s2_req(w).uop.uses_ldq) && !IsKilledByBranch(io.lsu.brupdate, s2_req(w).uop) io.lsu.nack(w).bits := UpdateBrMask(io.lsu.brupdate, s2_req(w)) assert(!(io.lsu.nack(w).valid && s2_type =/= t_lsu)) } // Store/amo hits val s3_req = RegNext(s2_req(0)) val s3_valid = RegNext(s2_valid(0) && s2_hit(0) && isWrite(s2_req(0).uop.mem_cmd) && !s2_sc_fail && !(s2_send_nack(0) && s2_nack(0))) for (w <- 1 until memWidth) { assert(!(s2_valid(w) && s2_hit(w) && isWrite(s2_req(w).uop.mem_cmd) && !s2_sc_fail && !(s2_send_nack(w) && s2_nack(w))), "Store must go through 0th pipe in L1D") } // For bypassing val s4_req = RegNext(s3_req) val s4_valid = RegNext(s3_valid) val s5_req = RegNext(s4_req) val s5_valid = RegNext(s4_valid) val s3_bypass = widthMap(w => s3_valid && ((s2_req(w).addr >> wordOffBits) === (s3_req.addr >> wordOffBits))) val s4_bypass = widthMap(w => s4_valid && ((s2_req(w).addr >> wordOffBits) === (s4_req.addr >> wordOffBits))) val s5_bypass = widthMap(w => s5_valid && ((s2_req(w).addr >> wordOffBits) === (s5_req.addr >> wordOffBits))) // Store -> Load bypassing for (w <- 0 until memWidth) { s2_data_word(w) := Mux(s3_bypass(w), s3_req.data, Mux(s4_bypass(w), s4_req.data, Mux(s5_bypass(w), s5_req.data, s2_data_word_prebypass(w)))) } val amoalu = Module(new AMOALU(xLen)) amoalu.io.mask := new StoreGen(s2_req(0).uop.mem_size, s2_req(0).addr, 0.U, xLen/8).mask amoalu.io.cmd := s2_req(0).uop.mem_cmd amoalu.io.lhs := s2_data_word(0) amoalu.io.rhs := s2_req(0).data s3_req.data := amoalu.io.out val s3_way = RegNext(s2_tag_match_way(0)) dataWriteArb.io.in(0).valid := s3_valid dataWriteArb.io.in(0).bits.addr := s3_req.addr dataWriteArb.io.in(0).bits.wmask := UIntToOH(s3_req.addr.extract(rowOffBits-1,offsetlsb)) dataWriteArb.io.in(0).bits.data := Fill(rowWords, s3_req.data) dataWriteArb.io.in(0).bits.way_en := s3_way io.lsu.ordered := mshrs.io.fence_rdy && !s1_valid.reduce(_\|\|_) && !s2_valid.reduce(_\|\|_) } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.nodes._ import freechips.rocketchip.diplomacy.{ AddressDecoder, AddressSet, BufferParams, DirectedBuffers, IdMap, IdMapEntry, IdRange, RegionType, TransferSizes } import freechips.rocketchip.resources.{Resource, ResourceAddress, ResourcePermissions} import freechips.rocketchip.util.{ AsyncQueueParams, BundleField, BundleFieldBase, BundleKeyBase, CreditedDelay, groupByIntoSeq, RationalDirection, SimpleProduct } import scala.math.max //These transfer sizes describe requests issued from masters on the A channel that will be responded by slaves on the D channel case class TLMasterToSlaveTransferSizes( // Supports both Acquire+Release of the following two sizes: acquireT: TransferSizes = TransferSizes.none, acquireB: TransferSizes = TransferSizes.none, arithmetic: TransferSizes = TransferSizes.none, logical: TransferSizes = TransferSizes.none, get: TransferSizes = TransferSizes.none, putFull: TransferSizes = TransferSizes.none, putPartial: TransferSizes = TransferSizes.none, hint: TransferSizes = TransferSizes.none) extends TLCommonTransferSizes { def intersect(rhs: TLMasterToSlaveTransferSizes) = TLMasterToSlaveTransferSizes( acquireT = acquireT .intersect(rhs.acquireT), acquireB = acquireB .intersect(rhs.acquireB), arithmetic = arithmetic.intersect(rhs.arithmetic), logical = logical .intersect(rhs.logical), get = get .intersect(rhs.get), putFull = putFull .intersect(rhs.putFull), putPartial = putPartial.intersect(rhs.putPartial), hint = hint .intersect(rhs.hint)) def mincover(rhs: TLMasterToSlaveTransferSizes) = TLMasterToSlaveTransferSizes( acquireT = acquireT .mincover(rhs.acquireT), acquireB = acquireB .mincover(rhs.acquireB), arithmetic = arithmetic.mincover(rhs.arithmetic), logical = logical .mincover(rhs.logical), get = get .mincover(rhs.get), putFull = putFull .mincover(rhs.putFull), putPartial = putPartial.mincover(rhs.putPartial), hint = hint .mincover(rhs.hint)) // Reduce rendering to a simple yes/no per field override def toString = { def str(x: TransferSizes, flag: String) = if (x.none) "" else flag def flags = Vector( str(acquireT, "T"), str(acquireB, "B"), str(arithmetic, "A"), str(logical, "L"), str(get, "G"), str(putFull, "F"), str(putPartial, "P"), str(hint, "H")) flags.mkString } // Prints out the actual information in a user readable way def infoString = { s"""acquireT = ${acquireT} \|acquireB = ${acquireB} \|arithmetic = ${arithmetic} \|logical = ${logical} \|get = ${get} \|putFull = ${putFull} \|putPartial = ${putPartial} \|hint = ${hint} \| \|""".stripMargin } } object TLMasterToSlaveTransferSizes { def unknownEmits = TLMasterToSlaveTransferSizes( acquireT = TransferSizes(1, 4096), acquireB = TransferSizes(1, 4096), arithmetic = TransferSizes(1, 4096), logical = TransferSizes(1, 4096), get = TransferSizes(1, 4096), putFull = TransferSizes(1, 4096), putPartial = TransferSizes(1, 4096), hint = TransferSizes(1, 4096)) def unknownSupports = TLMasterToSlaveTransferSizes() } //These transfer sizes describe requests issued from slaves on the B channel that will be responded by masters on the C channel case class TLSlaveToMasterTransferSizes( probe: TransferSizes = TransferSizes.none, arithmetic: TransferSizes = TransferSizes.none, logical: TransferSizes = TransferSizes.none, get: TransferSizes = TransferSizes.none, putFull: TransferSizes = TransferSizes.none, putPartial: TransferSizes = TransferSizes.none, hint: TransferSizes = TransferSizes.none ) extends TLCommonTransferSizes { def intersect(rhs: TLSlaveToMasterTransferSizes) = TLSlaveToMasterTransferSizes( probe = probe .intersect(rhs.probe), arithmetic = arithmetic.intersect(rhs.arithmetic), logical = logical .intersect(rhs.logical), get = get .intersect(rhs.get), putFull = putFull .intersect(rhs.putFull), putPartial = putPartial.intersect(rhs.putPartial), hint = hint .intersect(rhs.hint) ) def mincover(rhs: TLSlaveToMasterTransferSizes) = TLSlaveToMasterTransferSizes( probe = probe .mincover(rhs.probe), arithmetic = arithmetic.mincover(rhs.arithmetic), logical = logical .mincover(rhs.logical), get = get .mincover(rhs.get), putFull = putFull .mincover(rhs.putFull), putPartial = putPartial.mincover(rhs.putPartial), hint = hint .mincover(rhs.hint) ) // Reduce rendering to a simple yes/no per field override def toString = { def str(x: TransferSizes, flag: String) = if (x.none) "" else flag def flags = Vector( str(probe, "P"), str(arithmetic, "A"), str(logical, "L"), str(get, "G"), str(putFull, "F"), str(putPartial, "P"), str(hint, "H")) flags.mkString } // Prints out the actual information in a user readable way def infoString = { s"""probe = ${probe} \|arithmetic = ${arithmetic} \|logical = ${logical} \|get = ${get} \|putFull = ${putFull} \|putPartial = ${putPartial} \|hint = ${hint} \| \|""".stripMargin } } object TLSlaveToMasterTransferSizes { def unknownEmits = TLSlaveToMasterTransferSizes( arithmetic = TransferSizes(1, 4096), logical = TransferSizes(1, 4096), get = TransferSizes(1, 4096), putFull = TransferSizes(1, 4096), putPartial = TransferSizes(1, 4096), hint = TransferSizes(1, 4096), probe = TransferSizes(1, 4096)) def unknownSupports = TLSlaveToMasterTransferSizes() } trait TLCommonTransferSizes { def arithmetic: TransferSizes def logical: TransferSizes def get: TransferSizes def putFull: TransferSizes def putPartial: TransferSizes def hint: TransferSizes } class TLSlaveParameters private( val nodePath: Seq[BaseNode], val resources: Seq[Resource], setName: Option[String], val address: Seq[AddressSet], val regionType: RegionType.T, val executable: Boolean, val fifoId: Option[Int], val supports: TLMasterToSlaveTransferSizes, val emits: TLSlaveToMasterTransferSizes, // By default, slaves are forbidden from issuing 'denied' responses (it prevents Fragmentation) val alwaysGrantsT: Boolean, // typically only true for CacheCork'd read-write devices; dual: neverReleaseData // If fifoId=Some, all accesses sent to the same fifoId are executed and ACK'd in FIFO order // Note: you can only rely on this FIFO behaviour if your TLMasterParameters include requestFifo val mayDenyGet: Boolean, // applies to: AccessAckData, GrantData val mayDenyPut: Boolean) // applies to: AccessAck, Grant, HintAck // ReleaseAck may NEVER be denied extends SimpleProduct { def sortedAddress = address.sorted override def canEqual(that: Any): Boolean = that.isInstanceOf[TLSlaveParameters] override def productPrefix = "TLSlaveParameters" // We intentionally omit nodePath for equality testing / formatting def productArity: Int = 11 def productElement(n: Int): Any = n match { case 0 => name case 1 => address case 2 => resources case 3 => regionType case 4 => executable case 5 => fifoId case 6 => supports case 7 => emits case 8 => alwaysGrantsT case 9 => mayDenyGet case 10 => mayDenyPut case _ => throw new IndexOutOfBoundsException(n.toString) } def supportsAcquireT: TransferSizes = supports.acquireT def supportsAcquireB: TransferSizes = supports.acquireB def supportsArithmetic: TransferSizes = supports.arithmetic def supportsLogical: TransferSizes = supports.logical def supportsGet: TransferSizes = supports.get def supportsPutFull: TransferSizes = supports.putFull def supportsPutPartial: TransferSizes = supports.putPartial def supportsHint: TransferSizes = supports.hint require (!address.isEmpty, "Address cannot be empty") address.foreach { a => require (a.finite, "Address must be finite") } address.combinations(2).foreach { case Seq(x,y) => require (!x.overlaps(y), s"$x and $y overlap.") } require (supportsPutFull.contains(supportsPutPartial), s"PutFull($supportsPutFull) < PutPartial($supportsPutPartial)") require (supportsPutFull.contains(supportsArithmetic), s"PutFull($supportsPutFull) < Arithmetic($supportsArithmetic)") require (supportsPutFull.contains(supportsLogical), s"PutFull($supportsPutFull) < Logical($supportsLogical)") require (supportsGet.contains(supportsArithmetic), s"Get($supportsGet) < Arithmetic($supportsArithmetic)") require (supportsGet.contains(supportsLogical), s"Get($supportsGet) < Logical($supportsLogical)") require (supportsAcquireB.contains(supportsAcquireT), s"AcquireB($supportsAcquireB) < AcquireT($supportsAcquireT)") require (!alwaysGrantsT \|\| supportsAcquireT, s"Must supportAcquireT if promising to always grantT") // Make sure that the regionType agrees with the capabilities require (!supportsAcquireB \|\| regionType >= RegionType.UNCACHED) // acquire -> uncached, tracked, cached require (regionType <= RegionType.UNCACHED \|\| supportsAcquireB) // tracked, cached -> acquire require (regionType != RegionType.UNCACHED \|\| supportsGet) // uncached -> supportsGet val name = setName.orElse(nodePath.lastOption.map(_.lazyModule.name)).getOrElse("disconnected") val maxTransfer = List( // Largest supported transfer of all types supportsAcquireT.max, supportsAcquireB.max, supportsArithmetic.max, supportsLogical.max, supportsGet.max, supportsPutFull.max, supportsPutPartial.max).max val maxAddress = address.map(_.max).max val minAlignment = address.map(_.alignment).min // The device had better not support a transfer larger than its alignment require (minAlignment >= maxTransfer, s"Bad $address: minAlignment ($minAlignment) must be >= maxTransfer ($maxTransfer)") def toResource: ResourceAddress = { ResourceAddress(address, ResourcePermissions( r = supportsAcquireB \|\| supportsGet, w = supportsAcquireT \|\| supportsPutFull, x = executable, c = supportsAcquireB, a = supportsArithmetic && supportsLogical)) } def findTreeViolation() = nodePath.find { case _: MixedAdapterNode[_, _, _, _, _, _, _, _] => false case _: SinkNode[_, _, _, _, _] => false case node => node.inputs.size != 1 } def isTree = findTreeViolation() == None def infoString = { s"""Slave Name = ${name} \|Slave Address = ${address} \|supports = ${supports.infoString} \| \|""".stripMargin } def v1copy( address: Seq[AddressSet] = address, resources: Seq[Resource] = resources, regionType: RegionType.T = regionType, executable: Boolean = executable, nodePath: Seq[BaseNode] = nodePath, supportsAcquireT: TransferSizes = supports.acquireT, supportsAcquireB: TransferSizes = supports.acquireB, supportsArithmetic: TransferSizes = supports.arithmetic, supportsLogical: TransferSizes = supports.logical, supportsGet: TransferSizes = supports.get, supportsPutFull: TransferSizes = supports.putFull, supportsPutPartial: TransferSizes = supports.putPartial, supportsHint: TransferSizes = supports.hint, mayDenyGet: Boolean = mayDenyGet, mayDenyPut: Boolean = mayDenyPut, alwaysGrantsT: Boolean = alwaysGrantsT, fifoId: Option[Int] = fifoId) = { new TLSlaveParameters( setName = setName, address = address, resources = resources, regionType = regionType, executable = executable, nodePath = nodePath, supports = TLMasterToSlaveTransferSizes( acquireT = supportsAcquireT, acquireB = supportsAcquireB, arithmetic = supportsArithmetic, logical = supportsLogical, get = supportsGet, putFull = supportsPutFull, putPartial = supportsPutPartial, hint = supportsHint), emits = emits, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut, alwaysGrantsT = alwaysGrantsT, fifoId = fifoId) } def v2copy( nodePath: Seq[BaseNode] = nodePath, resources: Seq[Resource] = resources, name: Option[String] = setName, address: Seq[AddressSet] = address, regionType: RegionType.T = regionType, executable: Boolean = executable, fifoId: Option[Int] = fifoId, supports: TLMasterToSlaveTransferSizes = supports, emits: TLSlaveToMasterTransferSizes = emits, alwaysGrantsT: Boolean = alwaysGrantsT, mayDenyGet: Boolean = mayDenyGet, mayDenyPut: Boolean = mayDenyPut) = { new TLSlaveParameters( nodePath = nodePath, resources = resources, setName = name, address = address, regionType = regionType, executable = executable, fifoId = fifoId, supports = supports, emits = emits, alwaysGrantsT = alwaysGrantsT, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut) } @deprecated("Use v1copy instead of copy","") def copy( address: Seq[AddressSet] = address, resources: Seq[Resource] = resources, regionType: RegionType.T = regionType, executable: Boolean = executable, nodePath: Seq[BaseNode] = nodePath, supportsAcquireT: TransferSizes = supports.acquireT, supportsAcquireB: TransferSizes = supports.acquireB, supportsArithmetic: TransferSizes = supports.arithmetic, supportsLogical: TransferSizes = supports.logical, supportsGet: TransferSizes = supports.get, supportsPutFull: TransferSizes = supports.putFull, supportsPutPartial: TransferSizes = supports.putPartial, supportsHint: TransferSizes = supports.hint, mayDenyGet: Boolean = mayDenyGet, mayDenyPut: Boolean = mayDenyPut, alwaysGrantsT: Boolean = alwaysGrantsT, fifoId: Option[Int] = fifoId) = { v1copy( address = address, resources = resources, regionType = regionType, executable = executable, nodePath = nodePath, supportsAcquireT = supportsAcquireT, supportsAcquireB = supportsAcquireB, supportsArithmetic = supportsArithmetic, supportsLogical = supportsLogical, supportsGet = supportsGet, supportsPutFull = supportsPutFull, supportsPutPartial = supportsPutPartial, supportsHint = supportsHint, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut, alwaysGrantsT = alwaysGrantsT, fifoId = fifoId) } } object TLSlaveParameters { def v1( address: Seq[AddressSet], resources: Seq[Resource] = Seq(), regionType: RegionType.T = RegionType.GET_EFFECTS, executable: Boolean = false, nodePath: Seq[BaseNode] = Seq(), supportsAcquireT: TransferSizes = TransferSizes.none, supportsAcquireB: TransferSizes = TransferSizes.none, supportsArithmetic: TransferSizes = TransferSizes.none, supportsLogical: TransferSizes = TransferSizes.none, supportsGet: TransferSizes = TransferSizes.none, supportsPutFull: TransferSizes = TransferSizes.none, supportsPutPartial: TransferSizes = TransferSizes.none, supportsHint: TransferSizes = TransferSizes.none, mayDenyGet: Boolean = false, mayDenyPut: Boolean = false, alwaysGrantsT: Boolean = false, fifoId: Option[Int] = None) = { new TLSlaveParameters( setName = None, address = address, resources = resources, regionType = regionType, executable = executable, nodePath = nodePath, supports = TLMasterToSlaveTransferSizes( acquireT = supportsAcquireT, acquireB = supportsAcquireB, arithmetic = supportsArithmetic, logical = supportsLogical, get = supportsGet, putFull = supportsPutFull, putPartial = supportsPutPartial, hint = supportsHint), emits = TLSlaveToMasterTransferSizes.unknownEmits, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut, alwaysGrantsT = alwaysGrantsT, fifoId = fifoId) } def v2( address: Seq[AddressSet], nodePath: Seq[BaseNode] = Seq(), resources: Seq[Resource] = Seq(), name: Option[String] = None, regionType: RegionType.T = RegionType.GET_EFFECTS, executable: Boolean = false, fifoId: Option[Int] = None, supports: TLMasterToSlaveTransferSizes = TLMasterToSlaveTransferSizes.unknownSupports, emits: TLSlaveToMasterTransferSizes = TLSlaveToMasterTransferSizes.unknownEmits, alwaysGrantsT: Boolean = false, mayDenyGet: Boolean = false, mayDenyPut: Boolean = false) = { new TLSlaveParameters( nodePath = nodePath, resources = resources, setName = name, address = address, regionType = regionType, executable = executable, fifoId = fifoId, supports = supports, emits = emits, alwaysGrantsT = alwaysGrantsT, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut) } } object TLManagerParameters { @deprecated("Use TLSlaveParameters.v1 instead of TLManagerParameters","") def apply( address: Seq[AddressSet], resources: Seq[Resource] = Seq(), regionType: RegionType.T = RegionType.GET_EFFECTS, executable: Boolean = false, nodePath: Seq[BaseNode] = Seq(), supportsAcquireT: TransferSizes = TransferSizes.none, supportsAcquireB: TransferSizes = TransferSizes.none, supportsArithmetic: TransferSizes = TransferSizes.none, supportsLogical: TransferSizes = TransferSizes.none, supportsGet: TransferSizes = TransferSizes.none, supportsPutFull: TransferSizes = TransferSizes.none, supportsPutPartial: TransferSizes = TransferSizes.none, supportsHint: TransferSizes = TransferSizes.none, mayDenyGet: Boolean = false, mayDenyPut: Boolean = false, alwaysGrantsT: Boolean = false, fifoId: Option[Int] = None) = TLSlaveParameters.v1( address, resources, regionType, executable, nodePath, supportsAcquireT, supportsAcquireB, supportsArithmetic, supportsLogical, supportsGet, supportsPutFull, supportsPutPartial, supportsHint, mayDenyGet, mayDenyPut, alwaysGrantsT, fifoId, ) } case class TLChannelBeatBytes(a: Option[Int], b: Option[Int], c: Option[Int], d: Option[Int]) { def members = Seq(a, b, c, d) members.collect { case Some(beatBytes) => require (isPow2(beatBytes), "Data channel width must be a power of 2") } } object TLChannelBeatBytes{ def apply(beatBytes: Int): TLChannelBeatBytes = TLChannelBeatBytes( Some(beatBytes), Some(beatBytes), Some(beatBytes), Some(beatBytes)) def apply(): TLChannelBeatBytes = TLChannelBeatBytes( None, None, None, None) } class TLSlavePortParameters private( val slaves: Seq[TLSlaveParameters], val channelBytes: TLChannelBeatBytes, val endSinkId: Int, val minLatency: Int, val responseFields: Seq[BundleFieldBase], val requestKeys: Seq[BundleKeyBase]) extends SimpleProduct { def sortedSlaves = slaves.sortBy(_.sortedAddress.head) override def canEqual(that: Any): Boolean = that.isInstanceOf[TLSlavePortParameters] override def productPrefix = "TLSlavePortParameters" def productArity: Int = 6 def productElement(n: Int): Any = n match { case 0 => slaves case 1 => channelBytes case 2 => endSinkId case 3 => minLatency case 4 => responseFields case 5 => requestKeys case _ => throw new IndexOutOfBoundsException(n.toString) } require (!slaves.isEmpty, "Slave ports must have slaves") require (endSinkId >= 0, "Sink ids cannot be negative") require (minLatency >= 0, "Minimum required latency cannot be negative") // Using this API implies you cannot handle mixed-width busses def beatBytes = { channelBytes.members.foreach { width => require (width.isDefined && width == channelBytes.a) } channelBytes.a.get } // TODO this should be deprecated def managers = slaves def requireFifo(policy: TLFIFOFixer.Policy = TLFIFOFixer.allFIFO) = { val relevant = slaves.filter(m => policy(m)) relevant.foreach { m => require(m.fifoId == relevant.head.fifoId, s"${m.name} had fifoId ${m.fifoId}, which was not homogeneous (${slaves.map(s => (s.name, s.fifoId))}) ") } } // Bounds on required sizes def maxAddress = slaves.map(_.maxAddress).max def maxTransfer = slaves.map(_.maxTransfer).max def mayDenyGet = slaves.exists(_.mayDenyGet) def mayDenyPut = slaves.exists(_.mayDenyPut) // Diplomatically determined operation sizes emitted by all outward Slaves // as opposed to emits* which generate circuitry to check which specific addresses val allEmitClaims = slaves.map(_.emits).reduce( _ intersect _) // Operation Emitted by at least one outward Slaves // as opposed to emits* which generate circuitry to check which specific addresses val anyEmitClaims = slaves.map(_.emits).reduce(_ mincover _) // Diplomatically determined operation sizes supported by all outward Slaves // as opposed to supports* which generate circuitry to check which specific addresses val allSupportClaims = slaves.map(_.supports).reduce( _ intersect _) val allSupportAcquireT = allSupportClaims.acquireT val allSupportAcquireB = allSupportClaims.acquireB val allSupportArithmetic = allSupportClaims.arithmetic val allSupportLogical = allSupportClaims.logical val allSupportGet = allSupportClaims.get val allSupportPutFull = allSupportClaims.putFull val allSupportPutPartial = allSupportClaims.putPartial val allSupportHint = allSupportClaims.hint // Operation supported by at least one outward Slaves // as opposed to supports* which generate circuitry to check which specific addresses val anySupportClaims = slaves.map(_.supports).reduce(_ mincover _) val anySupportAcquireT = !anySupportClaims.acquireT.none val anySupportAcquireB = !anySupportClaims.acquireB.none val anySupportArithmetic = !anySupportClaims.arithmetic.none val anySupportLogical = !anySupportClaims.logical.none val anySupportGet = !anySupportClaims.get.none val anySupportPutFull = !anySupportClaims.putFull.none val anySupportPutPartial = !anySupportClaims.putPartial.none val anySupportHint = !anySupportClaims.hint.none // Supporting Acquire means being routable for GrantAck require ((endSinkId == 0) == !anySupportAcquireB) // These return Option[TLSlaveParameters] for your convenience def find(address: BigInt) = slaves.find(_.address.exists(_.contains(address))) // The safe version will check the entire address def findSafe(address: UInt) = VecInit(sortedSlaves.map(_.address.map(_.contains(address)).reduce(_ \|\| _))) // The fast version assumes the address is valid (you probably want fastProperty instead of this function) def findFast(address: UInt) = { val routingMask = AddressDecoder(slaves.map(_.address)) VecInit(sortedSlaves.map(_.address.map(_.widen(~routingMask)).distinct.map(_.contains(address)).reduce(_ \|\| _))) } // Compute the simplest AddressSets that decide a key def fastPropertyGroup[K](p: TLSlaveParameters => K): Seq[(K, Seq[AddressSet])] = { val groups = groupByIntoSeq(sortedSlaves.map(m => (p(m), m.address)))( _._1).map { case (k, vs) => k -> vs.flatMap(_._2) } val reductionMask = AddressDecoder(groups.map(_._2)) groups.map { case (k, seq) => k -> AddressSet.unify(seq.map(_.widen(~reductionMask)).distinct) } } // Select a property def fastProperty[K, D <: Data](address: UInt, p: TLSlaveParameters => K, d: K => D): D = Mux1H(fastPropertyGroup(p).map { case (v, a) => (a.map(_.contains(address)).reduce(_\|\|_), d(v)) }) // Note: returns the actual fifoId + 1 or 0 if None def findFifoIdFast(address: UInt) = fastProperty(address, _.fifoId.map(_+1).getOrElse(0), (i:Int) => i.U) def hasFifoIdFast(address: UInt) = fastProperty(address, _.fifoId.isDefined, (b:Boolean) => b.B) // Does this Port manage this ID/address? def containsSafe(address: UInt) = findSafe(address).reduce(_ \|\| _) private def addressHelper( // setting safe to false indicates that all addresses are expected to be legal, which might reduce circuit complexity safe: Boolean, // member filters out the sizes being checked based on the opcode being emitted or supported member: TLSlaveParameters => TransferSizes, address: UInt, lgSize: UInt, // range provides a limit on the sizes that are expected to be evaluated, which might reduce circuit complexity range: Option[TransferSizes]): Bool = { // trim reduces circuit complexity by intersecting checked sizes with the range argument def trim(x: TransferSizes) = range.map(_.intersect(x)).getOrElse(x) // groupBy returns an unordered map, convert back to Seq and sort the result for determinism // groupByIntoSeq is turning slaves into trimmed membership sizes // We are grouping all the slaves by their transfer size where // if they support the trimmed size then // member is the type of transfer that you are looking for (What you are trying to filter on) // When you consider membership, you are trimming the sizes to only the ones that you care about // you are filtering the slaves based on both whether they support a particular opcode and the size // Grouping the slaves based on the actual transfer size range they support // intersecting the range and checking their membership // FOR SUPPORTCASES instead of returning the list of slaves, // you are returning a map from transfer size to the set of // address sets that are supported for that transfer size // find all the slaves that support a certain type of operation and then group their addresses by the supported size // for every size there could be multiple address ranges // safety is a trade off between checking between all possible addresses vs only the addresses // that are known to have supported sizes // the trade off is 'checking all addresses is a more expensive circuit but will always give you // the right answer even if you give it an illegal address' // the not safe version is a cheaper circuit but if you give it an illegal address then it might produce the wrong answer // fast presumes address legality // This groupByIntoSeq deterministically groups all address sets for which a given `member` transfer size applies. // In the resulting Map of cases, the keys are transfer sizes and the values are all address sets which emit or support that size. val supportCases = groupByIntoSeq(slaves)(m => trim(member(m))).map { case (k: TransferSizes, vs: Seq[TLSlaveParameters]) => k -> vs.flatMap(_.address) } // safe produces a circuit that compares against all possible addresses, // whereas fast presumes that the address is legal but uses an efficient address decoder val mask = if (safe) ~BigInt(0) else AddressDecoder(supportCases.map(_._2)) // Simplified creates the most concise possible representation of each cases' address sets based on the mask. val simplified = supportCases.map { case (k, seq) => k -> AddressSet.unify(seq.map(_.widen(~mask)).distinct) } simplified.map { case (s, a) => // s is a size, you are checking for this size either the size of the operation is in s // We return an or-reduction of all the cases, checking whether any contains both the dynamic size and dynamic address on the wire. ((Some(s) == range).B \|\| s.containsLg(lgSize)) && a.map(_.contains(address)).reduce(_\|\|_) }.foldLeft(false.B)(_\|\|_) } def supportsAcquireTSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.acquireT, address, lgSize, range) def supportsAcquireBSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.acquireB, address, lgSize, range) def supportsArithmeticSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.arithmetic, address, lgSize, range) def supportsLogicalSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.logical, address, lgSize, range) def supportsGetSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.get, address, lgSize, range) def supportsPutFullSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.putFull, address, lgSize, range) def supportsPutPartialSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.putPartial, address, lgSize, range) def supportsHintSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.hint, address, lgSize, range) def supportsAcquireTFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.acquireT, address, lgSize, range) def supportsAcquireBFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.acquireB, address, lgSize, range) def supportsArithmeticFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.arithmetic, address, lgSize, range) def supportsLogicalFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.logical, address, lgSize, range) def supportsGetFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.get, address, lgSize, range) def supportsPutFullFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.putFull, address, lgSize, range) def supportsPutPartialFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.putPartial, address, lgSize, range) def supportsHintFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.hint, address, lgSize, range) def emitsProbeSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.probe, address, lgSize, range) def emitsArithmeticSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.arithmetic, address, lgSize, range) def emitsLogicalSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.logical, address, lgSize, range) def emitsGetSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.get, address, lgSize, range) def emitsPutFullSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.putFull, address, lgSize, range) def emitsPutPartialSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.putPartial, address, lgSize, range) def emitsHintSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.hint, address, lgSize, range) def findTreeViolation() = slaves.flatMap(_.findTreeViolation()).headOption def isTree = !slaves.exists(!_.isTree) def infoString = "Slave Port Beatbytes = " + beatBytes + "\n" + "Slave Port MinLatency = " + minLatency + "\n\n" + slaves.map(_.infoString).mkString def v1copy( managers: Seq[TLSlaveParameters] = slaves, beatBytes: Int = -1, endSinkId: Int = endSinkId, minLatency: Int = minLatency, responseFields: Seq[BundleFieldBase] = responseFields, requestKeys: Seq[BundleKeyBase] = requestKeys) = { new TLSlavePortParameters( slaves = managers, channelBytes = if (beatBytes != -1) TLChannelBeatBytes(beatBytes) else channelBytes, endSinkId = endSinkId, minLatency = minLatency, responseFields = responseFields, requestKeys = requestKeys) } def v2copy( slaves: Seq[TLSlaveParameters] = slaves, channelBytes: TLChannelBeatBytes = channelBytes, endSinkId: Int = endSinkId, minLatency: Int = minLatency, responseFields: Seq[BundleFieldBase] = responseFields, requestKeys: Seq[BundleKeyBase] = requestKeys) = { new TLSlavePortParameters( slaves = slaves, channelBytes = channelBytes, endSinkId = endSinkId, minLatency = minLatency, responseFields = responseFields, requestKeys = requestKeys) } @deprecated("Use v1copy instead of copy","") def copy( managers: Seq[TLSlaveParameters] = slaves, beatBytes: Int = -1, endSinkId: Int = endSinkId, minLatency: Int = minLatency, responseFields: Seq[BundleFieldBase] = responseFields, requestKeys: Seq[BundleKeyBase] = requestKeys) = { v1copy( managers, beatBytes, endSinkId, minLatency, responseFields, requestKeys) } } object TLSlavePortParameters { def v1( managers: Seq[TLSlaveParameters], beatBytes: Int, endSinkId: Int = 0, minLatency: Int = 0, responseFields: Seq[BundleFieldBase] = Nil, requestKeys: Seq[BundleKeyBase] = Nil) = { new TLSlavePortParameters( slaves = managers, channelBytes = TLChannelBeatBytes(beatBytes), endSinkId = endSinkId, minLatency = minLatency, responseFields = responseFields, requestKeys = requestKeys) } } object TLManagerPortParameters { @deprecated("Use TLSlavePortParameters.v1 instead of TLManagerPortParameters","") def apply( managers: Seq[TLSlaveParameters], beatBytes: Int, endSinkId: Int = 0, minLatency: Int = 0, responseFields: Seq[BundleFieldBase] = Nil, requestKeys: Seq[BundleKeyBase] = Nil) = { TLSlavePortParameters.v1( managers, beatBytes, endSinkId, minLatency, responseFields, requestKeys) } } class TLMasterParameters private( val nodePath: Seq[BaseNode], val resources: Seq[Resource], val name: String, val visibility: Seq[AddressSet], val unusedRegionTypes: Set[RegionType.T], val executesOnly: Boolean, val requestFifo: Boolean, // only a request, not a requirement. applies to A, not C. val supports: TLSlaveToMasterTransferSizes, val emits: TLMasterToSlaveTransferSizes, val neverReleasesData: Boolean, val sourceId: IdRange) extends SimpleProduct { override def canEqual(that: Any): Boolean = that.isInstanceOf[TLMasterParameters] override def productPrefix = "TLMasterParameters" // We intentionally omit nodePath for equality testing / formatting def productArity: Int = 10 def productElement(n: Int): Any = n match { case 0 => name case 1 => sourceId case 2 => resources case 3 => visibility case 4 => unusedRegionTypes case 5 => executesOnly case 6 => requestFifo case 7 => supports case 8 => emits case 9 => neverReleasesData case _ => throw new IndexOutOfBoundsException(n.toString) } require (!sourceId.isEmpty) require (!visibility.isEmpty) require (supports.putFull.contains(supports.putPartial)) // We only support these operations if we support Probe (ie: we're a cache) require (supports.probe.contains(supports.arithmetic)) require (supports.probe.contains(supports.logical)) require (supports.probe.contains(supports.get)) require (supports.probe.contains(supports.putFull)) require (supports.probe.contains(supports.putPartial)) require (supports.probe.contains(supports.hint)) visibility.combinations(2).foreach { case Seq(x,y) => require (!x.overlaps(y), s"$x and $y overlap.") } val maxTransfer = List( supports.probe.max, supports.arithmetic.max, supports.logical.max, supports.get.max, supports.putFull.max, supports.putPartial.max).max def infoString = { s"""Master Name = ${name} \|visibility = ${visibility} \|emits = ${emits.infoString} \|sourceId = ${sourceId} \| \|""".stripMargin } def v1copy( name: String = name, sourceId: IdRange = sourceId, nodePath: Seq[BaseNode] = nodePath, requestFifo: Boolean = requestFifo, visibility: Seq[AddressSet] = visibility, supportsProbe: TransferSizes = supports.probe, supportsArithmetic: TransferSizes = supports.arithmetic, supportsLogical: TransferSizes = supports.logical, supportsGet: TransferSizes = supports.get, supportsPutFull: TransferSizes = supports.putFull, supportsPutPartial: TransferSizes = supports.putPartial, supportsHint: TransferSizes = supports.hint) = { new TLMasterParameters( nodePath = nodePath, resources = this.resources, name = name, visibility = visibility, unusedRegionTypes = this.unusedRegionTypes, executesOnly = this.executesOnly, requestFifo = requestFifo, supports = TLSlaveToMasterTransferSizes( probe = supportsProbe, arithmetic = supportsArithmetic, logical = supportsLogical, get = supportsGet, putFull = supportsPutFull, putPartial = supportsPutPartial, hint = supportsHint), emits = this.emits, neverReleasesData = this.neverReleasesData, sourceId = sourceId) } def v2copy( nodePath: Seq[BaseNode] = nodePath, resources: Seq[Resource] = resources, name: String = name, visibility: Seq[AddressSet] = visibility, unusedRegionTypes: Set[RegionType.T] = unusedRegionTypes, executesOnly: Boolean = executesOnly, requestFifo: Boolean = requestFifo, supports: TLSlaveToMasterTransferSizes = supports, emits: TLMasterToSlaveTransferSizes = emits, neverReleasesData: Boolean = neverReleasesData, sourceId: IdRange = sourceId) = { new TLMasterParameters( nodePath = nodePath, resources = resources, name = name, visibility = visibility, unusedRegionTypes = unusedRegionTypes, executesOnly = executesOnly, requestFifo = requestFifo, supports = supports, emits = emits, neverReleasesData = neverReleasesData, sourceId = sourceId) } @deprecated("Use v1copy instead of copy","") def copy( name: String = name, sourceId: IdRange = sourceId, nodePath: Seq[BaseNode] = nodePath, requestFifo: Boolean = requestFifo, visibility: Seq[AddressSet] = visibility, supportsProbe: TransferSizes = supports.probe, supportsArithmetic: TransferSizes = supports.arithmetic, supportsLogical: TransferSizes = supports.logical, supportsGet: TransferSizes = supports.get, supportsPutFull: TransferSizes = supports.putFull, supportsPutPartial: TransferSizes = supports.putPartial, supportsHint: TransferSizes = supports.hint) = { v1copy( name = name, sourceId = sourceId, nodePath = nodePath, requestFifo = requestFifo, visibility = visibility, supportsProbe = supportsProbe, supportsArithmetic = supportsArithmetic, supportsLogical = supportsLogical, supportsGet = supportsGet, supportsPutFull = supportsPutFull, supportsPutPartial = supportsPutPartial, supportsHint = supportsHint) } } object TLMasterParameters { def v1( name: String, sourceId: IdRange = IdRange(0,1), nodePath: Seq[BaseNode] = Seq(), requestFifo: Boolean = false, visibility: Seq[AddressSet] = Seq(AddressSet(0, ~0)), supportsProbe: TransferSizes = TransferSizes.none, supportsArithmetic: TransferSizes = TransferSizes.none, supportsLogical: TransferSizes = TransferSizes.none, supportsGet: TransferSizes = TransferSizes.none, supportsPutFull: TransferSizes = TransferSizes.none, supportsPutPartial: TransferSizes = TransferSizes.none, supportsHint: TransferSizes = TransferSizes.none) = { new TLMasterParameters( nodePath = nodePath, resources = Nil, name = name, visibility = visibility, unusedRegionTypes = Set(), executesOnly = false, requestFifo = requestFifo, supports = TLSlaveToMasterTransferSizes( probe = supportsProbe, arithmetic = supportsArithmetic, logical = supportsLogical, get = supportsGet, putFull = supportsPutFull, putPartial = supportsPutPartial, hint = supportsHint), emits = TLMasterToSlaveTransferSizes.unknownEmits, neverReleasesData = false, sourceId = sourceId) } def v2( nodePath: Seq[BaseNode] = Seq(), resources: Seq[Resource] = Nil, name: String, visibility: Seq[AddressSet] = Seq(AddressSet(0, ~0)), unusedRegionTypes: Set[RegionType.T] = Set(), executesOnly: Boolean = false, requestFifo: Boolean = false, supports: TLSlaveToMasterTransferSizes = TLSlaveToMasterTransferSizes.unknownSupports, emits: TLMasterToSlaveTransferSizes = TLMasterToSlaveTransferSizes.unknownEmits, neverReleasesData: Boolean = false, sourceId: IdRange = IdRange(0,1)) = { new TLMasterParameters( nodePath = nodePath, resources = resources, name = name, visibility = visibility, unusedRegionTypes = unusedRegionTypes, executesOnly = executesOnly, requestFifo = requestFifo, supports = supports, emits = emits, neverReleasesData = neverReleasesData, sourceId = sourceId) } } object TLClientParameters { @deprecated("Use TLMasterParameters.v1 instead of TLClientParameters","") def apply( name: String, sourceId: IdRange = IdRange(0,1), nodePath: Seq[BaseNode] = Seq(), requestFifo: Boolean = false, visibility: Seq[AddressSet] = Seq(AddressSet.everything), supportsProbe: TransferSizes = TransferSizes.none, supportsArithmetic: TransferSizes = TransferSizes.none, supportsLogical: TransferSizes = TransferSizes.none, supportsGet: TransferSizes = TransferSizes.none, supportsPutFull: TransferSizes = TransferSizes.none, supportsPutPartial: TransferSizes = TransferSizes.none, supportsHint: TransferSizes = TransferSizes.none) = { TLMasterParameters.v1( name = name, sourceId = sourceId, nodePath = nodePath, requestFifo = requestFifo, visibility = visibility, supportsProbe = supportsProbe, supportsArithmetic = supportsArithmetic, supportsLogical = supportsLogical, supportsGet = supportsGet, supportsPutFull = supportsPutFull, supportsPutPartial = supportsPutPartial, supportsHint = supportsHint) } } class TLMasterPortParameters private( val masters: Seq[TLMasterParameters], val channelBytes: TLChannelBeatBytes, val minLatency: Int, val echoFields: Seq[BundleFieldBase], val requestFields: Seq[BundleFieldBase], val responseKeys: Seq[BundleKeyBase]) extends SimpleProduct { override def canEqual(that: Any): Boolean = that.isInstanceOf[TLMasterPortParameters] override def productPrefix = "TLMasterPortParameters" def productArity: Int = 6 def productElement(n: Int): Any = n match { case 0 => masters case 1 => channelBytes case 2 => minLatency case 3 => echoFields case 4 => requestFields case 5 => responseKeys case _ => throw new IndexOutOfBoundsException(n.toString) } require (!masters.isEmpty) require (minLatency >= 0) def clients = masters // Require disjoint ranges for Ids IdRange.overlaps(masters.map(_.sourceId)).foreach { case (x, y) => require (!x.overlaps(y), s"TLClientParameters.sourceId ${x} overlaps ${y}") } // Bounds on required sizes def endSourceId = masters.map(_.sourceId.end).max def maxTransfer = masters.map(_.maxTransfer).max // The unused sources < endSourceId def unusedSources: Seq[Int] = { val usedSources = masters.map(_.sourceId).sortBy(_.start) ((Seq(0) ++ usedSources.map(_.end)) zip usedSources.map(_.start)) flatMap { case (end, start) => end until start } } // Diplomatically determined operation sizes emitted by all inward Masters // as opposed to emits* which generate circuitry to check which specific addresses val allEmitClaims = masters.map(_.emits).reduce( _ intersect _) // Diplomatically determined operation sizes Emitted by at least one inward Masters // as opposed to emits* which generate circuitry to check which specific addresses val anyEmitClaims = masters.map(_.emits).reduce(_ mincover _) // Diplomatically determined operation sizes supported by all inward Masters // as opposed to supports* which generate circuitry to check which specific addresses val allSupportProbe = masters.map(_.supports.probe) .reduce(_ intersect _) val allSupportArithmetic = masters.map(_.supports.arithmetic).reduce(_ intersect _) val allSupportLogical = masters.map(_.supports.logical) .reduce(_ intersect _) val allSupportGet = masters.map(_.supports.get) .reduce(_ intersect _) val allSupportPutFull = masters.map(_.supports.putFull) .reduce(_ intersect _) val allSupportPutPartial = masters.map(_.supports.putPartial).reduce(_ intersect _) val allSupportHint = masters.map(_.supports.hint) .reduce(_ intersect _) // Diplomatically determined operation sizes supported by at least one master // as opposed to supports* which generate circuitry to check which specific addresses val anySupportProbe = masters.map(!_.supports.probe.none) .reduce(_ \|\| _) val anySupportArithmetic = masters.map(!_.supports.arithmetic.none).reduce(_ \|\| _) val anySupportLogical = masters.map(!_.supports.logical.none) .reduce(_ \|\| _) val anySupportGet = masters.map(!_.supports.get.none) .reduce(_ \|\| _) val anySupportPutFull = masters.map(!_.supports.putFull.none) .reduce(_ \|\| _) val anySupportPutPartial = masters.map(!_.supports.putPartial.none).reduce(_ \|\| _) val anySupportHint = masters.map(!_.supports.hint.none) .reduce(_ \|\| _) // These return Option[TLMasterParameters] for your convenience def find(id: Int) = masters.find(_.sourceId.contains(id)) // Synthesizable lookup methods def find(id: UInt) = VecInit(masters.map(_.sourceId.contains(id))) def contains(id: UInt) = find(id).reduce(_ \|\| _) def requestFifo(id: UInt) = Mux1H(find(id), masters.map(c => c.requestFifo.B)) // Available during RTL runtime, checks to see if (id, size) is supported by the master's (client's) diplomatic parameters private def sourceIdHelper(member: TLMasterParameters => TransferSizes)(id: UInt, lgSize: UInt) = { val allSame = masters.map(member(_) == member(masters(0))).reduce(_ && _) // this if statement is a coarse generalization of the groupBy in the sourceIdHelper2 version; // the case where there is only one group. if (allSame) member(masters(0)).containsLg(lgSize) else { // Find the master associated with ID and returns whether that particular master is able to receive transaction of lgSize Mux1H(find(id), masters.map(member(_).containsLg(lgSize))) } } // Check for support of a given operation at a specific id val supportsProbe = sourceIdHelper(_.supports.probe) _ val supportsArithmetic = sourceIdHelper(_.supports.arithmetic) _ val supportsLogical = sourceIdHelper(_.supports.logical) _ val supportsGet = sourceIdHelper(_.supports.get) _ val supportsPutFull = sourceIdHelper(_.supports.putFull) _ val supportsPutPartial = sourceIdHelper(_.supports.putPartial) _ val supportsHint = sourceIdHelper(_.supports.hint) _ // TODO: Merge sourceIdHelper2 with sourceIdHelper private def sourceIdHelper2( member: TLMasterParameters => TransferSizes, sourceId: UInt, lgSize: UInt): Bool = { // Because sourceIds are uniquely owned by each master, we use them to group the // cases that have to be checked. val emitCases = groupByIntoSeq(masters)(m => member(m)).map { case (k, vs) => k -> vs.map(_.sourceId) } emitCases.map { case (s, a) => (s.containsLg(lgSize)) && a.map(_.contains(sourceId)).reduce(_\|\|_) }.foldLeft(false.B)(_\|\|_) } // Check for emit of a given operation at a specific id def emitsAcquireT (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.acquireT, sourceId, lgSize) def emitsAcquireB (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.acquireB, sourceId, lgSize) def emitsArithmetic(sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.arithmetic, sourceId, lgSize) def emitsLogical (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.logical, sourceId, lgSize) def emitsGet (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.get, sourceId, lgSize) def emitsPutFull (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.putFull, sourceId, lgSize) def emitsPutPartial(sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.putPartial, sourceId, lgSize) def emitsHint (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.hint, sourceId, lgSize) def infoString = masters.map(_.infoString).mkString def v1copy( clients: Seq[TLMasterParameters] = masters, minLatency: Int = minLatency, echoFields: Seq[BundleFieldBase] = echoFields, requestFields: Seq[BundleFieldBase] = requestFields, responseKeys: Seq[BundleKeyBase] = responseKeys) = { new TLMasterPortParameters( masters = clients, channelBytes = channelBytes, minLatency = minLatency, echoFields = echoFields, requestFields = requestFields, responseKeys = responseKeys) } def v2copy( masters: Seq[TLMasterParameters] = masters, channelBytes: TLChannelBeatBytes = channelBytes, minLatency: Int = minLatency, echoFields: Seq[BundleFieldBase] = echoFields, requestFields: Seq[BundleFieldBase] = requestFields, responseKeys: Seq[BundleKeyBase] = responseKeys) = { new TLMasterPortParameters( masters = masters, channelBytes = channelBytes, minLatency = minLatency, echoFields = echoFields, requestFields = requestFields, responseKeys = responseKeys) } @deprecated("Use v1copy instead of copy","") def copy( clients: Seq[TLMasterParameters] = masters, minLatency: Int = minLatency, echoFields: Seq[BundleFieldBase] = echoFields, requestFields: Seq[BundleFieldBase] = requestFields, responseKeys: Seq[BundleKeyBase] = responseKeys) = { v1copy( clients, minLatency, echoFields, requestFields, responseKeys) } } object TLClientPortParameters { @deprecated("Use TLMasterPortParameters.v1 instead of TLClientPortParameters","") def apply( clients: Seq[TLMasterParameters], minLatency: Int = 0, echoFields: Seq[BundleFieldBase] = Nil, requestFields: Seq[BundleFieldBase] = Nil, responseKeys: Seq[BundleKeyBase] = Nil) = { TLMasterPortParameters.v1( clients, minLatency, echoFields, requestFields, responseKeys) } } object TLMasterPortParameters { def v1( clients: Seq[TLMasterParameters], minLatency: Int = 0, echoFields: Seq[BundleFieldBase] = Nil, requestFields: Seq[BundleFieldBase] = Nil, responseKeys: Seq[BundleKeyBase] = Nil) = { new TLMasterPortParameters( masters = clients, channelBytes = TLChannelBeatBytes(), minLatency = minLatency, echoFields = echoFields, requestFields = requestFields, responseKeys = responseKeys) } def v2( masters: Seq[TLMasterParameters], channelBytes: TLChannelBeatBytes = TLChannelBeatBytes(), minLatency: Int = 0, echoFields: Seq[BundleFieldBase] = Nil, requestFields: Seq[BundleFieldBase] = Nil, responseKeys: Seq[BundleKeyBase] = Nil) = { new TLMasterPortParameters( masters = masters, channelBytes = channelBytes, minLatency = minLatency, echoFields = echoFields, requestFields = requestFields, responseKeys = responseKeys) } } case class TLBundleParameters( addressBits: Int, dataBits: Int, sourceBits: Int, sinkBits: Int, sizeBits: Int, echoFields: Seq[BundleFieldBase], requestFields: Seq[BundleFieldBase], responseFields: Seq[BundleFieldBase], hasBCE: Boolean) { // Chisel has issues with 0-width wires require (addressBits >= 1) require (dataBits >= 8) require (sourceBits >= 1) require (sinkBits >= 1) require (sizeBits >= 1) require (isPow2(dataBits)) echoFields.foreach { f => require (f.key.isControl, s"${f} is not a legal echo field") } val addrLoBits = log2Up(dataBits/8) // Used to uniquify bus IP names def shortName = s"a${addressBits}d${dataBits}s${sourceBits}k${sinkBits}z${sizeBits}" + (if (hasBCE) "c" else "u") def union(x: TLBundleParameters) = TLBundleParameters( max(addressBits, x.addressBits), max(dataBits, x.dataBits), max(sourceBits, x.sourceBits), max(sinkBits, x.sinkBits), max(sizeBits, x.sizeBits), echoFields = BundleField.union(echoFields ++ x.echoFields), requestFields = BundleField.union(requestFields ++ x.requestFields), responseFields = BundleField.union(responseFields ++ x.responseFields), hasBCE \|\| x.hasBCE) } object TLBundleParameters { val emptyBundleParams = TLBundleParameters( addressBits = 1, dataBits = 8, sourceBits = 1, sinkBits = 1, sizeBits = 1, echoFields = Nil, requestFields = Nil, responseFields = Nil, hasBCE = false) def union(x: Seq[TLBundleParameters]) = x.foldLeft(emptyBundleParams)((x,y) => x.union(y)) def apply(master: TLMasterPortParameters, slave: TLSlavePortParameters) = new TLBundleParameters( addressBits = log2Up(slave.maxAddress + 1), dataBits = slave.beatBytes * 8, sourceBits = log2Up(master.endSourceId), sinkBits = log2Up(slave.endSinkId), sizeBits = log2Up(log2Ceil(max(master.maxTransfer, slave.maxTransfer))+1), echoFields = master.echoFields, requestFields = BundleField.accept(master.requestFields, slave.requestKeys), responseFields = BundleField.accept(slave.responseFields, master.responseKeys), hasBCE = master.anySupportProbe && slave.anySupportAcquireB) } case class TLEdgeParameters( master: TLMasterPortParameters, slave: TLSlavePortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge { // legacy names: def manager = slave def client = master val maxTransfer = max(master.maxTransfer, slave.maxTransfer) val maxLgSize = log2Ceil(maxTransfer) // Sanity check the link... require (maxTransfer >= slave.beatBytes, s"Link's max transfer (${maxTransfer}) < ${slave.slaves.map(_.name)}'s beatBytes (${slave.beatBytes})") def diplomaticClaimsMasterToSlave = master.anyEmitClaims.intersect(slave.anySupportClaims) val bundle = TLBundleParameters(master, slave) def formatEdge = master.infoString + "\n" + slave.infoString } case class TLCreditedDelay( a: CreditedDelay, b: CreditedDelay, c: CreditedDelay, d: CreditedDelay, e: CreditedDelay) { def + (that: TLCreditedDelay): TLCreditedDelay = TLCreditedDelay( a = a + that.a, b = b + that.b, c = c + that.c, d = d + that.d, e = e + that.e) override def toString = s"(${a}, ${b}, ${c}, ${d}, ${e})" } object TLCreditedDelay { def apply(delay: CreditedDelay): TLCreditedDelay = apply(delay, delay.flip, delay, delay.flip, delay) } case class TLCreditedManagerPortParameters(delay: TLCreditedDelay, base: TLSlavePortParameters) {def infoString = base.infoString} case class TLCreditedClientPortParameters(delay: TLCreditedDelay, base: TLMasterPortParameters) {def infoString = base.infoString} case class TLCreditedEdgeParameters(client: TLCreditedClientPortParameters, manager: TLCreditedManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge { val delay = client.delay + manager.delay val bundle = TLBundleParameters(client.base, manager.base) def formatEdge = client.infoString + "\n" + manager.infoString } case class TLAsyncManagerPortParameters(async: AsyncQueueParams, base: TLSlavePortParameters) {def infoString = base.infoString} case class TLAsyncClientPortParameters(base: TLMasterPortParameters) {def infoString = base.infoString} case class TLAsyncBundleParameters(async: AsyncQueueParams, base: TLBundleParameters) case class TLAsyncEdgeParameters(client: TLAsyncClientPortParameters, manager: TLAsyncManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge { val bundle = TLAsyncBundleParameters(manager.async, TLBundleParameters(client.base, manager.base)) def formatEdge = client.infoString + "\n" + manager.infoString } case class TLRationalManagerPortParameters(direction: RationalDirection, base: TLSlavePortParameters) {def infoString = base.infoString} case class TLRationalClientPortParameters(base: TLMasterPortParameters) {def infoString = base.infoString} case class TLRationalEdgeParameters(client: TLRationalClientPortParameters, manager: TLRationalManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge { val bundle = TLBundleParameters(client.base, manager.base) def formatEdge = client.infoString + "\n" + manager.infoString } // To be unified, devices must agree on all of these terms case class ManagerUnificationKey( resources: Seq[Resource], regionType: RegionType.T, executable: Boolean, supportsAcquireT: TransferSizes, supportsAcquireB: TransferSizes, supportsArithmetic: TransferSizes, supportsLogical: TransferSizes, supportsGet: TransferSizes, supportsPutFull: TransferSizes, supportsPutPartial: TransferSizes, supportsHint: TransferSizes) object ManagerUnificationKey { def apply(x: TLSlaveParameters): ManagerUnificationKey = ManagerUnificationKey( resources = x.resources, regionType = x.regionType, executable = x.executable, supportsAcquireT = x.supportsAcquireT, supportsAcquireB = x.supportsAcquireB, supportsArithmetic = x.supportsArithmetic, supportsLogical = x.supportsLogical, supportsGet = x.supportsGet, supportsPutFull = x.supportsPutFull, supportsPutPartial = x.supportsPutPartial, supportsHint = x.supportsHint) } object ManagerUnification { def apply(slaves: Seq[TLSlaveParameters]): List[TLSlaveParameters] = { slaves.groupBy(ManagerUnificationKey.apply).values.map { seq => val agree = seq.forall(_.fifoId == seq.head.fifoId) seq(0).v1copy( address = AddressSet.unify(seq.flatMap(_.address)), fifoId = if (agree) seq(0).fifoId else None) }.toList } } case class TLBufferParams( a: BufferParams = BufferParams.none, b: BufferParams = BufferParams.none, c: BufferParams = BufferParams.none, d: BufferParams = BufferParams.none, e: BufferParams = BufferParams.none ) extends DirectedBuffers[TLBufferParams] { def copyIn(x: BufferParams) = this.copy(b = x, d = x) def copyOut(x: BufferParams) = this.copy(a = x, c = x, e = x) def copyInOut(x: BufferParams) = this.copyIn(x).copyOut(x) } /** Pretty printing of TL source id maps / class TLSourceIdMap(tl: TLMasterPortParameters) extends IdMap[TLSourceIdMapEntry] { private val tlDigits = String.valueOf(tl.endSourceId-1).length() protected val fmt = s"\t[%${tlDigits}d, %${tlDigits}d) %s%s%s" private val sorted = tl.masters.sortBy(_.sourceId) val mapping: Seq[TLSourceIdMapEntry] = sorted.map { case c => TLSourceIdMapEntry(c.sourceId, c.name, c.supports.probe, c.requestFifo) } } case class TLSourceIdMapEntry(tlId: IdRange, name: String, isCache: Boolean, requestFifo: Boolean) extends IdMapEntry { val from = tlId val to = tlId val maxTransactionsInFlight = Some(tlId.size) } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportPutFull \|\| manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB \|\| manager.anySupportGet \|\| manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportPutFull \|\| client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe \|\| client.anySupportGet \|\| client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet \|\| client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull \|\| client.anySupportPutPartial \|\| client.anySupportHint \|\| client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet \|\| manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull \|\| manager.anySupportPutPartial \|\| manager.anySupportHint \|\| manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) \|\| !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.ProbeAckData \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode \| small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U \|\| beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }	module BoomWritebackUnit( // @[dcache.scala:24:7] input clock, // @[dcache.scala:24:7] input reset, // @[dcache.scala:24:7] output io_req_ready, // @[dcache.scala:25:14] input io_req_valid, // @[dcache.scala:25:14] input [21:0] io_req_bits_tag, // @[dcache.scala:25:14] input [3:0] io_req_bits_idx, // @[dcache.scala:25:14] input [3:0] io_req_bits_source, // @[dcache.scala:25:14] input [2:0] io_req_bits_param, // @[dcache.scala:25:14] input [1:0] io_req_bits_way_en, // @[dcache.scala:25:14] input io_req_bits_voluntary, // @[dcache.scala:25:14] input io_meta_read_ready, // @[dcache.scala:25:14] output io_meta_read_valid, // @[dcache.scala:25:14] output [3:0] io_meta_read_bits_idx, // @[dcache.scala:25:14] output [21:0] io_meta_read_bits_tag, // @[dcache.scala:25:14] output io_resp, // @[dcache.scala:25:14] output io_idx_valid, // @[dcache.scala:25:14] output [3:0] io_idx_bits, // @[dcache.scala:25:14] input io_data_req_ready, // @[dcache.scala:25:14] output io_data_req_valid, // @[dcache.scala:25:14] output [1:0] io_data_req_bits_way_en, // @[dcache.scala:25:14] output [9:0] io_data_req_bits_addr, // @[dcache.scala:25:14] input [63:0] io_data_resp, // @[dcache.scala:25:14] input io_mem_grant, // @[dcache.scala:25:14] input io_release_ready, // @[dcache.scala:25:14] output io_release_valid, // @[dcache.scala:25:14] output [2:0] io_release_bits_opcode, // @[dcache.scala:25:14] output [2:0] io_release_bits_param, // @[dcache.scala:25:14] output [31:0] io_release_bits_address, // @[dcache.scala:25:14] output [63:0] io_release_bits_data, // @[dcache.scala:25:14] input io_lsu_release_ready, // @[dcache.scala:25:14] output io_lsu_release_valid, // @[dcache.scala:25:14] output [2:0] io_lsu_release_bits_param, // @[dcache.scala:25:14] output [31:0] io_lsu_release_bits_address, // @[dcache.scala:25:14] output [63:0] io_lsu_release_bits_data // @[dcache.scala:25:14] ); reg [2:0] state; // @[dcache.scala:39:22] wire io_req_valid_0 = io_req_valid; // @[dcache.scala:24:7] wire [21:0] io_req_bits_tag_0 = io_req_bits_tag; // @[dcache.scala:24:7] wire [3:0] io_req_bits_idx_0 = io_req_bits_idx; // @[dcache.scala:24:7] wire [3:0] io_req_bits_source_0 = io_req_bits_source; // @[dcache.scala:24:7] wire [2:0] io_req_bits_param_0 = io_req_bits_param; // @[dcache.scala:24:7] wire [1:0] io_req_bits_way_en_0 = io_req_bits_way_en; // @[dcache.scala:24:7] wire io_req_bits_voluntary_0 = io_req_bits_voluntary; // @[dcache.scala:24:7] wire io_meta_read_ready_0 = io_meta_read_ready; // @[dcache.scala:24:7] wire io_data_req_ready_0 = io_data_req_ready; // @[dcache.scala:24:7] wire [63:0] io_data_resp_0 = io_data_resp; // @[dcache.scala:24:7] wire io_mem_grant_0 = io_mem_grant; // @[dcache.scala:24:7] wire io_release_ready_0 = io_release_ready; // @[dcache.scala:24:7] wire io_lsu_release_ready_0 = io_lsu_release_ready; // @[dcache.scala:24:7] wire [26:0] _r_beats1_decode_T = 27'h3FFC0; // @[package.scala:243:71] wire [11:0] _r_beats1_decode_T_1 = 12'hFC0; // @[package.scala:243:76] wire [11:0] _r_beats1_decode_T_2 = 12'h3F; // @[package.scala:243:46] wire [8:0] r_beats1_decode = 9'h7; // @[Edges.scala:220:59] wire _voluntaryRelease_legal_T_7 = 1'h1; // @[Parameters.scala:91:44] wire _voluntaryRelease_legal_T_8 = 1'h1; // @[Parameters.scala:684:29] wire [2:0] voluntaryRelease_opcode = 3'h7; // @[Edges.scala:396:17] wire [2:0] io_lsu_release_bits_opcode = 3'h5; // @[dcache.scala:24:7] wire [2:0] probeResponse_opcode = 3'h5; // @[Edges.scala:433:17] wire io_release_bits_corrupt = 1'h0; // @[dcache.scala:24:7] wire io_lsu_release_bits_corrupt = 1'h0; // @[dcache.scala:24:7] wire probeResponse_corrupt = 1'h0; // @[Edges.scala:433:17] wire _voluntaryRelease_legal_T = 1'h0; // @[Parameters.scala:684:29] wire _voluntaryRelease_legal_T_6 = 1'h0; // @[Parameters.scala:684:54] wire _voluntaryRelease_legal_T_15 = 1'h0; // @[Parameters.scala:686:26] wire voluntaryRelease_corrupt = 1'h0; // @[Edges.scala:396:17] wire _io_release_bits_T_corrupt = 1'h0; // @[dcache.scala:124:27] wire [3:0] io_release_bits_source = 4'h8; // @[dcache.scala:24:7] wire [3:0] io_lsu_release_bits_source = 4'h8; // @[dcache.scala:24:7] wire [3:0] probeResponse_source = 4'h8; // @[Edges.scala:433:17] wire [3:0] voluntaryRelease_source = 4'h8; // @[Edges.scala:396:17] wire [3:0] _io_release_bits_T_source = 4'h8; // @[dcache.scala:124:27] wire [3:0] io_release_bits_size = 4'h6; // @[dcache.scala:24:7] wire [3:0] io_lsu_release_bits_size = 4'h6; // @[dcache.scala:24:7] wire [3:0] probeResponse_size = 4'h6; // @[Edges.scala:433:17] wire [3:0] voluntaryRelease_size = 4'h6; // @[Edges.scala:396:17] wire [3:0] _io_release_bits_T_size = 4'h6; // @[dcache.scala:124:27] wire [1:0] io_meta_read_bits_way_en = 2'h0; // @[dcache.scala:24:7] wire io_req_ready_0 = ~(\|state); // @[dcache.scala:24:7, :39:22, :49:31, :80:15] wire _io_idx_valid_T; // @[dcache.scala:49:31] wire [9:0] _io_data_req_bits_addr_T_2; // @[dcache.scala:97:43] wire [2:0] _io_release_bits_T_opcode; // @[dcache.scala:124:27] wire [2:0] _io_release_bits_T_param; // @[dcache.scala:124:27] wire [31:0] _io_release_bits_T_address; // @[dcache.scala:124:27] wire [63:0] _io_release_bits_T_data; // @[dcache.scala:124:27] wire [2:0] probeResponse_param; // @[Edges.scala:433:17] wire [31:0] probeResponse_address; // @[Edges.scala:433:17] wire [63:0] probeResponse_data; // @[Edges.scala:433:17] wire [3:0] io_meta_read_bits_idx_0; // @[dcache.scala:24:7] wire [21:0] io_meta_read_bits_tag_0; // @[dcache.scala:24:7] wire io_meta_read_valid_0; // @[dcache.scala:24:7] wire io_idx_valid_0; // @[dcache.scala:24:7] wire [3:0] io_idx_bits_0; // @[dcache.scala:24:7] wire [1:0] io_data_req_bits_way_en_0; // @[dcache.scala:24:7] wire [9:0] io_data_req_bits_addr_0; // @[dcache.scala:24:7] wire io_data_req_valid_0; // @[dcache.scala:24:7] wire [2:0] io_release_bits_opcode_0; // @[dcache.scala:24:7] wire [2:0] io_release_bits_param_0; // @[dcache.scala:24:7] wire [31:0] io_release_bits_address_0; // @[dcache.scala:24:7] wire [63:0] io_release_bits_data_0; // @[dcache.scala:24:7] wire io_release_valid_0; // @[dcache.scala:24:7] wire [2:0] io_lsu_release_bits_param_0; // @[dcache.scala:24:7] wire [31:0] io_lsu_release_bits_address_0; // @[dcache.scala:24:7] wire [63:0] io_lsu_release_bits_data_0; // @[dcache.scala:24:7] wire io_lsu_release_valid_0; // @[dcache.scala:24:7] wire io_resp_0; // @[dcache.scala:24:7] reg [21:0] req_tag; // @[dcache.scala:37:16] assign io_meta_read_bits_tag_0 = req_tag; // @[dcache.scala:24:7, :37:16] reg [3:0] req_idx; // @[dcache.scala:37:16] assign io_meta_read_bits_idx_0 = req_idx; // @[dcache.scala:24:7, :37:16] assign io_idx_bits_0 = req_idx; // @[dcache.scala:24:7, :37:16] reg [3:0] req_source; // @[dcache.scala:37:16] reg [2:0] req_param; // @[dcache.scala:37:16] assign probeResponse_param = req_param; // @[Edges.scala:433:17] wire [2:0] voluntaryRelease_param = req_param; // @[Edges.scala:396:17] reg [1:0] req_way_en; // @[dcache.scala:37:16] assign io_data_req_bits_way_en_0 = req_way_en; // @[dcache.scala:24:7, :37:16] reg req_voluntary; // @[dcache.scala:37:16] reg r1_data_req_fired; // @[dcache.scala:40:34] reg r2_data_req_fired; // @[dcache.scala:41:34] reg [3:0] r1_data_req_cnt; // @[dcache.scala:42:28] reg [3:0] r2_data_req_cnt; // @[dcache.scala:43:28] reg [3:0] data_req_cnt; // @[dcache.scala:44:29] wire _T_14 = io_release_ready_0 & io_release_valid_0; // @[Decoupled.scala:51:35] wire r_beats1_opdata = io_release_bits_opcode_0[0]; // @[Edges.scala:102:36] wire [8:0] r_beats1 = r_beats1_opdata ? 9'h7 : 9'h0; // @[Edges.scala:102:36, :220:59, :221:14] reg [8:0] r_counter; // @[Edges.scala:229:27] wire [9:0] _r_counter1_T = {1'h0, r_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] r_counter1 = _r_counter1_T[8:0]; // @[Edges.scala:230:28] wire r_1 = r_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _r_last_T = r_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _r_last_T_1 = r_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire last_beat = _r_last_T \| _r_last_T_1; // @[Edges.scala:232:{25,33,43}] wire all_beats_done = last_beat & _T_14; // @[Decoupled.scala:51:35] wire [8:0] _r_count_T = ~r_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] beat_count = r_beats1 & _r_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _r_counter_T = r_1 ? r_beats1 : r_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [63:0] wb_buffer_0; // @[dcache.scala:46:22] reg [63:0] wb_buffer_1; // @[dcache.scala:46:22] reg [63:0] wb_buffer_2; // @[dcache.scala:46:22] reg [63:0] wb_buffer_3; // @[dcache.scala:46:22] reg [63:0] wb_buffer_4; // @[dcache.scala:46:22] reg [63:0] wb_buffer_5; // @[dcache.scala:46:22] reg [63:0] wb_buffer_6; // @[dcache.scala:46:22] reg [63:0] wb_buffer_7; // @[dcache.scala:46:22] reg acked; // @[dcache.scala:47:22] assign _io_idx_valid_T = \|state; // @[dcache.scala:39:22, :49:31] assign io_idx_valid_0 = _io_idx_valid_T; // @[dcache.scala:24:7, :49:31] wire [25:0] _r_address_T = {req_tag, req_idx}; // @[dcache.scala:37:16, :63:22] wire [31:0] r_address = {_r_address_T, 6'h0}; // @[dcache.scala:63:{22,41}] assign probeResponse_address = r_address; // @[Edges.scala:433:17] wire [31:0] _voluntaryRelease_legal_T_1 = r_address; // @[Parameters.scala:137:31] wire [31:0] voluntaryRelease_address = r_address; // @[Edges.scala:396:17] wire [2:0] _probeResponse_T = data_req_cnt[2:0]; // @[dcache.scala:44:29] wire [2:0] _voluntaryRelease_T = data_req_cnt[2:0]; // @[dcache.scala:44:29] wire [2:0] _io_data_req_bits_addr_T = data_req_cnt[2:0]; // @[dcache.scala:44:29, :96:56] assign io_lsu_release_bits_param_0 = probeResponse_param; // @[Edges.scala:433:17] assign io_lsu_release_bits_address_0 = probeResponse_address; // @[Edges.scala:433:17] assign io_lsu_release_bits_data_0 = probeResponse_data; // @[Edges.scala:433:17] wire [7:0][63:0] _GEN = {{wb_buffer_7}, {wb_buffer_6}, {wb_buffer_5}, {wb_buffer_4}, {wb_buffer_3}, {wb_buffer_2}, {wb_buffer_1}, {wb_buffer_0}}; // @[Edges.scala:441:15] assign probeResponse_data = _GEN[_probeResponse_T]; // @[Edges.scala:433:17, :441:15] wire [32:0] _voluntaryRelease_legal_T_2 = {1'h0, _voluntaryRelease_legal_T_1}; // @[Parameters.scala:137:{31,41}] wire [32:0] _voluntaryRelease_legal_T_3 = _voluntaryRelease_legal_T_2 & 33'h80000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _voluntaryRelease_legal_T_4 = _voluntaryRelease_legal_T_3; // @[Parameters.scala:137:46] wire _voluntaryRelease_legal_T_5 = _voluntaryRelease_legal_T_4 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] _voluntaryRelease_legal_T_9 = r_address ^ 32'h80000000; // @[Parameters.scala:137:31] wire [32:0] _voluntaryRelease_legal_T_10 = {1'h0, _voluntaryRelease_legal_T_9}; // @[Parameters.scala:137:{31,41}] wire [32:0] _voluntaryRelease_legal_T_11 = _voluntaryRelease_legal_T_10 & 33'h80000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _voluntaryRelease_legal_T_12 = _voluntaryRelease_legal_T_11; // @[Parameters.scala:137:46] wire _voluntaryRelease_legal_T_13 = _voluntaryRelease_legal_T_12 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _voluntaryRelease_legal_T_14 = _voluntaryRelease_legal_T_13; // @[Parameters.scala:684:54] wire voluntaryRelease_legal = _voluntaryRelease_legal_T_14; // @[Parameters.scala:684:54, :686:26] wire [63:0] voluntaryRelease_data; // @[Edges.scala:396:17] assign voluntaryRelease_data = _GEN[_voluntaryRelease_T]; // @[Edges.scala:396:17, :404:15, :441:15] wire _T_3 = state == 3'h1; // @[dcache.scala:39:22, :88:22] wire _io_meta_read_valid_T = ~(data_req_cnt[3]); // @[dcache.scala:44:29, :89:40] assign io_meta_read_valid_0 = (\|state) & _T_3 & _io_meta_read_valid_T; // @[dcache.scala:24:7, :39:22, :49:31, :54:22, :80:30, :88:{22,41}, :89:{24,40}] wire _io_data_req_valid_T = ~(data_req_cnt[3]); // @[dcache.scala:44:29, :89:40, :93:39] assign io_data_req_valid_0 = (\|state) & _T_3 & _io_data_req_valid_T; // @[dcache.scala:24:7, :39:22, :49:31, :56:22, :80:30, :88:{22,41}, :93:{23,39}] wire [6:0] _io_data_req_bits_addr_T_1 = {req_idx, _io_data_req_bits_addr_T}; // @[dcache.scala:37:16, :96:{34,56}] assign _io_data_req_bits_addr_T_2 = {_io_data_req_bits_addr_T_1, 3'h0}; // @[dcache.scala:96:34, :97:43] assign io_data_req_bits_addr_0 = _io_data_req_bits_addr_T_2; // @[dcache.scala:24:7, :97:43] wire [4:0] _GEN_0 = {1'h0, data_req_cnt} + 5'h1; // @[dcache.scala:44:29, :106:36] wire [4:0] _data_req_cnt_T; // @[dcache.scala:106:36] assign _data_req_cnt_T = _GEN_0; // @[dcache.scala:106:36] wire [4:0] _data_req_cnt_T_2; // @[dcache.scala:130:36] assign _data_req_cnt_T_2 = _GEN_0; // @[dcache.scala:106:36, :130:36] wire [3:0] _data_req_cnt_T_1 = _data_req_cnt_T[3:0]; // @[dcache.scala:106:36] wire _T_8 = r2_data_req_cnt == 4'h7; // @[dcache.scala:43:28, :110:29] assign io_resp_0 = (\|state) & _T_3 & r2_data_req_fired & _T_8; // @[dcache.scala:24:7, :39:22, :41:34, :49:31, :58:22, :80:30, :88:{22,41}, :108:30, :110:{29,53}] wire _T_9 = state == 3'h2; // @[dcache.scala:39:22, :116:22] assign io_lsu_release_valid_0 = ~(~(\|state) \| _T_3) & _T_9; // @[dcache.scala:24:7, :39:22, :49:31, :59:24, :80:{15,30}, :88:{22,41}, :116:{22,41}] wire _T_11 = state == 3'h3; // @[dcache.scala:39:22, :122:22] wire _io_release_valid_T = ~(data_req_cnt[3]); // @[dcache.scala:44:29, :89:40, :123:38] wire _GEN_1 = _T_3 \| _T_9; // @[dcache.scala:51:22, :88:{22,41}, :116:{22,41}, :122:36] assign io_release_valid_0 = ~(~(\|state) \| _GEN_1) & _T_11 & _io_release_valid_T; // @[dcache.scala:24:7, :39:22, :49:31, :51:22, :80:{15,30}, :88:41, :116:41, :122:{22,36}, :123:{22,38}] assign _io_release_bits_T_opcode = {1'h1, req_voluntary, 1'h1}; // @[dcache.scala:37:16, :124:27] assign _io_release_bits_T_param = req_voluntary ? voluntaryRelease_param : probeResponse_param; // @[Edges.scala:396:17, :433:17] assign _io_release_bits_T_address = req_voluntary ? voluntaryRelease_address : probeResponse_address; // @[Edges.scala:396:17, :433:17] assign _io_release_bits_T_data = req_voluntary ? voluntaryRelease_data : probeResponse_data; // @[Edges.scala:396:17, :433:17] assign io_release_bits_opcode_0 = _io_release_bits_T_opcode; // @[dcache.scala:24:7, :124:27] assign io_release_bits_param_0 = _io_release_bits_T_param; // @[dcache.scala:24:7, :124:27] assign io_release_bits_address_0 = _io_release_bits_T_address; // @[dcache.scala:24:7, :124:27] assign io_release_bits_data_0 = _io_release_bits_T_data; // @[dcache.scala:24:7, :124:27] wire [3:0] _data_req_cnt_T_3 = _data_req_cnt_T_2[3:0]; // @[dcache.scala:130:36] wire [2:0] _state_T = {req_voluntary, 2'h0}; // @[dcache.scala:37:16, :133:19] wire _T_16 = state == 3'h4; // @[dcache.scala:39:22, :135:22] wire _T_2 = io_req_ready_0 & io_req_valid_0; // @[Decoupled.scala:51:35] wire _GEN_2 = (\|state) & _T_3; // @[dcache.scala:39:22, :41:34, :49:31, :80:30, :88:{22,41}] wire _T_6 = io_data_req_ready_0 & io_data_req_valid_0 & io_meta_read_ready_0 & io_meta_read_valid_0; // @[Decoupled.scala:51:35] always @(posedge clock) begin // @[dcache.scala:24:7] if (~(\|state) & _T_2) begin // @[Decoupled.scala:51:35] req_tag <= io_req_bits_tag_0; // @[dcache.scala:24:7, :37:16] req_idx <= io_req_bits_idx_0; // @[dcache.scala:24:7, :37:16] req_source <= io_req_bits_source_0; // @[dcache.scala:24:7, :37:16] req_param <= io_req_bits_param_0; // @[dcache.scala:24:7, :37:16] req_way_en <= io_req_bits_way_en_0; // @[dcache.scala:24:7, :37:16] req_voluntary <= io_req_bits_voluntary_0; // @[dcache.scala:24:7, :37:16] end if (_GEN_2) begin // @[dcache.scala:41:34, :43:28, :80:30, :88:41] r1_data_req_cnt <= _T_6 ? data_req_cnt : 4'h0; // @[Decoupled.scala:51:35] r2_data_req_cnt <= r1_data_req_cnt; // @[dcache.scala:42:28, :43:28] end if ((\|state) & _T_3 & r2_data_req_fired & r2_data_req_cnt[2:0] == 3'h0) // @[dcache.scala:39:22, :41:34, :43:28, :46:22, :49:31, :80:30, :88:{22,41}, :108:30, :109:34] wb_buffer_0 <= io_data_resp_0; // @[dcache.scala:24:7, :46:22] if ((\|state) & _T_3 & r2_data_req_fired & r2_data_req_cnt[2:0] == 3'h1) // @[dcache.scala:39:22, :41:34, :43:28, :46:22, :49:31, :80:30, :88:{22,41}, :108:30, :109:34] wb_buffer_1 <= io_data_resp_0; // @[dcache.scala:24:7, :46:22] if ((\|state) & _T_3 & r2_data_req_fired & r2_data_req_cnt[2:0] == 3'h2) // @[dcache.scala:39:22, :41:34, :43:28, :46:22, :49:31, :80:30, :88:{22,41}, :108:30, :109:34] wb_buffer_2 <= io_data_resp_0; // @[dcache.scala:24:7, :46:22] if ((\|state) & _T_3 & r2_data_req_fired & r2_data_req_cnt[2:0] == 3'h3) // @[dcache.scala:39:22, :41:34, :43:28, :46:22, :49:31, :80:30, :88:{22,41}, :108:30, :109:34] wb_buffer_3 <= io_data_resp_0; // @[dcache.scala:24:7, :46:22] if ((\|state) & _T_3 & r2_data_req_fired & r2_data_req_cnt[2:0] == 3'h4) // @[dcache.scala:39:22, :41:34, :43:28, :46:22, :49:31, :80:30, :88:{22,41}, :108:30, :109:34] wb_buffer_4 <= io_data_resp_0; // @[dcache.scala:24:7, :46:22] if ((\|state) & _T_3 & r2_data_req_fired & r2_data_req_cnt[2:0] == 3'h5) // @[dcache.scala:39:22, :41:34, :43:28, :46:22, :49:31, :80:30, :88:{22,41}, :108:30, :109:34] wb_buffer_5 <= io_data_resp_0; // @[dcache.scala:24:7, :46:22] if ((\|state) & _T_3 & r2_data_req_fired & r2_data_req_cnt[2:0] == 3'h6) // @[dcache.scala:39:22, :41:34, :43:28, :46:22, :49:31, :80:30, :88:{22,41}, :108:30, :109:34] wb_buffer_6 <= io_data_resp_0; // @[dcache.scala:24:7, :46:22] if ((\|state) & _T_3 & r2_data_req_fired & (&(r2_data_req_cnt[2:0]))) // @[dcache.scala:39:22, :41:34, :43:28, :46:22, :49:31, :80:30, :88:{22,41}, :108:30, :109:34] wb_buffer_7 <= io_data_resp_0; // @[dcache.scala:24:7, :46:22] if (reset) begin // @[dcache.scala:24:7] state <= 3'h0; // @[dcache.scala:39:22] r1_data_req_fired <= 1'h0; // @[dcache.scala:40:34] r2_data_req_fired <= 1'h0; // @[dcache.scala:41:34] data_req_cnt <= 4'h0; // @[dcache.scala:44:29] r_counter <= 9'h0; // @[Edges.scala:229:27] acked <= 1'h0; // @[dcache.scala:47:22] end else begin // @[dcache.scala:24:7] if (\|state) begin // @[dcache.scala:39:22, :49:31] if (_T_3) begin // @[dcache.scala:88:22] if (r2_data_req_fired & _T_8) begin // @[dcache.scala:39:22, :41:34, :108:30, :110:{29,53}, :112:15] state <= 3'h2; // @[dcache.scala:39:22] data_req_cnt <= 4'h0; // @[dcache.scala:44:29] end else if (_T_6) // @[Decoupled.scala:51:35] data_req_cnt <= _data_req_cnt_T_1; // @[dcache.scala:44:29, :106:36] end else begin // @[dcache.scala:88:22] if (_T_9) begin // @[dcache.scala:116:22] if (io_lsu_release_ready_0 & io_lsu_release_valid_0) // @[Decoupled.scala:51:35] state <= 3'h3; // @[dcache.scala:39:22] end else if (_T_11) begin // @[dcache.scala:122:22] if (data_req_cnt == 4'h7 & _T_14) // @[Decoupled.scala:51:35] state <= _state_T; // @[dcache.scala:39:22, :133:19] end else if (_T_16 & acked) // @[dcache.scala:39:22, :47:22, :135:{22,35}, :139:18, :140:13] state <= 3'h0; // @[dcache.scala:39:22] if (_T_9 \| ~(_T_11 & _T_14)) begin // @[Decoupled.scala:51:35] end else // @[dcache.scala:44:29, :116:41, :122:36] data_req_cnt <= _data_req_cnt_T_3; // @[dcache.scala:44:29, :130:36] end if (~_GEN_1) // @[dcache.scala:51:22, :88:41, :116:41, :122:36] acked <= _T_11 ? io_mem_grant_0 \| acked : _T_16 & io_mem_grant_0 \| acked; // @[dcache.scala:24:7, :47:22, :122:{22,36}, :126:25, :127:13, :135:{22,35}, :136:25, :137:13] end else begin // @[dcache.scala:49:31] if (_T_2) begin // @[Decoupled.scala:51:35] state <= 3'h1; // @[dcache.scala:39:22] data_req_cnt <= 4'h0; // @[dcache.scala:44:29] end acked <= ~_T_2 & acked; // @[Decoupled.scala:51:35] end if (_GEN_2) begin // @[dcache.scala:41:34, :80:30, :88:41] r1_data_req_fired <= _T_6; // @[Decoupled.scala:51:35] r2_data_req_fired <= r1_data_req_fired; // @[dcache.scala:40:34, :41:34] end if (_T_14) // @[Decoupled.scala:51:35] r_counter <= _r_counter_T; // @[Edges.scala:229:27, :236:21] end always @(posedge) assign io_req_ready = io_req_ready_0; // @[dcache.scala:24:7] assign io_meta_read_valid = io_meta_read_valid_0; // @[dcache.scala:24:7] assign io_meta_read_bits_idx = io_meta_read_bits_idx_0; // @[dcache.scala:24:7] assign io_meta_read_bits_tag = io_meta_read_bits_tag_0; // @[dcache.scala:24:7] assign io_resp = io_resp_0; // @[dcache.scala:24:7] assign io_idx_valid = io_idx_valid_0; // @[dcache.scala:24:7] assign io_idx_bits = io_idx_bits_0; // @[dcache.scala:24:7] assign io_data_req_valid = io_data_req_valid_0; // @[dcache.scala:24:7] assign io_data_req_bits_way_en = io_data_req_bits_way_en_0; // @[dcache.scala:24:7] assign io_data_req_bits_addr = io_data_req_bits_addr_0; // @[dcache.scala:24:7] assign io_release_valid = io_release_valid_0; // @[dcache.scala:24:7] assign io_release_bits_opcode = io_release_bits_opcode_0; // @[dcache.scala:24:7] assign io_release_bits_param = io_release_bits_param_0; // @[dcache.scala:24:7] assign io_release_bits_address = io_release_bits_address_0; // @[dcache.scala:24:7] assign io_release_bits_data = io_release_bits_data_0; // @[dcache.scala:24:7] assign io_lsu_release_valid = io_lsu_release_valid_0; // @[dcache.scala:24:7] assign io_lsu_release_bits_param = io_lsu_release_bits_param_0; // @[dcache.scala:24:7] assign io_lsu_release_bits_address = io_lsu_release_bits_address_0; // @[dcache.scala:24:7] assign io_lsu_release_bits_data = io_lsu_release_bits_data_0; // @[dcache.scala:24:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File Monitor.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceLine import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import freechips.rocketchip.diplomacy.EnableMonitors import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode} import freechips.rocketchip.util.PlusArg case class TLMonitorArgs(edge: TLEdge) abstract class TLMonitorBase(args: TLMonitorArgs) extends Module { val io = IO(new Bundle { val in = Input(new TLBundle(args.edge.bundle)) }) def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit legalize(io.in, args.edge, reset) } object TLMonitor { def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = { if (enable) { EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) } } else { node } } } class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args) { require (args.edge.params(TLMonitorStrictMode) \|\| (! args.edge.params(TestplanTestType).formal)) val cover_prop_class = PropertyClass.Default //Like assert but can flip to being an assumption for formal verification def monAssert(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir, cond, message, PropertyClass.Default) } def assume(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir.flip, cond, message, PropertyClass.Default) } def extra = { args.edge.sourceInfo match { case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)" case _ => "" } } def visible(address: UInt, source: UInt, edge: TLEdge) = edge.client.clients.map { c => !c.sourceId.contains(source) \|\| c.visibility.map(_.contains(address)).reduce(_ \|\| _) }.reduce(_ && _) def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = { //switch this flag to turn on diplomacy in error messages def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n" monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra) // Reuse these subexpressions to save some firrtl lines val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility") //The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B //TODO: check for acquireT? when (bundle.opcode === TLMessages.AcquireBlock) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra) } when (bundle.opcode === TLMessages.AcquirePerm) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra) monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra) monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra) monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra) } } def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = { monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra) monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility") // Reuse these subexpressions to save some firrtl lines val address_ok = edge.manager.containsSafe(edge.address(bundle)) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source when (bundle.opcode === TLMessages.Probe) { assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra) assume (address_ok, "'B' channel Probe carries unmanaged address" + extra) assume (legal_source, "'B' channel Probe carries source that is not first source" + extra) assume (is_aligned, "'B' channel Probe address not aligned to size" + extra) assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra) assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra) assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra) monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra) monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra) monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra) monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra) } } def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = { monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val address_ok = edge.manager.containsSafe(edge.address(bundle)) monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility") when (bundle.opcode === TLMessages.ProbeAck) { monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra) } when (bundle.opcode === TLMessages.ProbeAckData) { monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.Release) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra) monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra) } when (bundle.opcode === TLMessages.ReleaseData) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.AccessAck) { monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra) } when (bundle.opcode === TLMessages.HintAck) { monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra) } } def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = { assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val sink_ok = bundle.sink < edge.manager.endSinkId.U val deny_put_ok = edge.manager.mayDenyPut.B val deny_get_ok = edge.manager.mayDenyGet.B when (bundle.opcode === TLMessages.ReleaseAck) { assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra) assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra) assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra) } when (bundle.opcode === TLMessages.Grant) { assume (source_ok, "'D' channel Grant carries invalid source ID" + extra) assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra) assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel Grant is denied" + extra) } when (bundle.opcode === TLMessages.GrantData) { assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra) assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra) assume (!bundle.denied \|\| bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra) assume (deny_get_ok \|\| !bundle.denied, "'D' channel GrantData is denied" + extra) } when (bundle.opcode === TLMessages.AccessAck) { assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel AccessAck is denied" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra) assume (!bundle.denied \|\| bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra) assume (deny_get_ok \|\| !bundle.denied, "'D' channel AccessAckData is denied" + extra) } when (bundle.opcode === TLMessages.HintAck) { assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel HintAck is denied" + extra) } } def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = { val sink_ok = bundle.sink < edge.manager.endSinkId.U monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra) } def legalizeFormat(bundle: TLBundle, edge: TLEdge) = { when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) } when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) } when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) } when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) } } else { monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra) monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra) monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra) } } def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = { val a_first = edge.first(a.bits, a.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (a.valid && !a_first) { monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra) monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra) monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra) monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra) monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra) } when (a.fire && a_first) { opcode := a.bits.opcode param := a.bits.param size := a.bits.size source := a.bits.source address := a.bits.address } } def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = { val b_first = edge.first(b.bits, b.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (b.valid && !b_first) { monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra) monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra) monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra) monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra) monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra) } when (b.fire && b_first) { opcode := b.bits.opcode param := b.bits.param size := b.bits.size source := b.bits.source address := b.bits.address } } def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = { // Symbolic variable val sym_source = Wire(UInt(edge.client.endSourceId.W)) // TODO: Connect sym_source to a fixed value for simulation and to a // free wire in formal sym_source := 0.U // Type casting Int to UInt val maxSourceId = Wire(UInt(edge.client.endSourceId.W)) maxSourceId := edge.client.endSourceId.U // Delayed verison of sym_source val sym_source_d = Reg(UInt(edge.client.endSourceId.W)) sym_source_d := sym_source // These will be constraints for FV setup Property( MonitorDirection.Monitor, (sym_source === sym_source_d), "sym_source should remain stable", PropertyClass.Default) Property( MonitorDirection.Monitor, (sym_source <= maxSourceId), "sym_source should take legal value", PropertyClass.Default) val my_resp_pend = RegInit(false.B) val my_opcode = Reg(UInt()) val my_size = Reg(UInt()) val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire) val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire) val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source) val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source) val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat) val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend) when (my_set_resp_pend) { my_resp_pend := true.B } .elsewhen (my_clr_resp_pend) { my_resp_pend := false.B } when (my_a_first_beat) { my_opcode := bundle.a.bits.opcode my_size := bundle.a.bits.size } val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size) val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode) val my_resp_opcode_legal = Wire(Bool()) when ((my_resp_opcode === TLMessages.Get) \|\| (my_resp_opcode === TLMessages.ArithmeticData) \|\| (my_resp_opcode === TLMessages.LogicalData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData) } .elsewhen ((my_resp_opcode === TLMessages.PutFullData) \|\| (my_resp_opcode === TLMessages.PutPartialData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck) } .otherwise { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck) } monAssert (IfThen(my_resp_pend, !my_a_first_beat), "Request message should not be sent with a source ID, for which a response message" + "is already pending (not received until current cycle) for a prior request message" + "with the same source ID" + extra) assume (IfThen(my_clr_resp_pend, (my_set_resp_pend \|\| my_resp_pend)), "Response message should be accepted with a source ID only if a request message with the" + "same source ID has been accepted or is being accepted in the current cycle" + extra) assume (IfThen(my_d_first_beat, (my_a_first_beat \|\| my_resp_pend)), "Response message should be sent with a source ID only if a request message with the" + "same source ID has been accepted or is being sent in the current cycle" + extra) assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)), "If d_valid is 1, then d_size should be same as a_size of the corresponding request" + "message" + extra) assume (IfThen(my_d_first_beat, my_resp_opcode_legal), "If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" + "request message" + extra) } def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = { val c_first = edge.first(c.bits, c.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (c.valid && !c_first) { monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra) monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra) monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra) monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra) monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra) } when (c.fire && c_first) { opcode := c.bits.opcode param := c.bits.param size := c.bits.size source := c.bits.source address := c.bits.address } } def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = { val d_first = edge.first(d.bits, d.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val sink = Reg(UInt()) val denied = Reg(Bool()) when (d.valid && !d_first) { assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra) assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra) assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra) assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra) assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra) assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra) } when (d.fire && d_first) { opcode := d.bits.opcode param := d.bits.param size := d.bits.size source := d.bits.source sink := d.bits.sink denied := d.bits.denied } } def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = { legalizeMultibeatA(bundle.a, edge) legalizeMultibeatD(bundle.d, edge) if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { legalizeMultibeatB(bundle.b, edge) legalizeMultibeatC(bundle.c, edge) } } //This is left in for almond which doesn't adhere to the tilelink protocol @deprecated("Use legalizeADSource instead if possible","") def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.client.endSourceId.W)) val a_first = edge.first(bundle.a.bits, bundle.a.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val a_set = WireInit(0.U(edge.client.endSourceId.W)) when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) assume((a_set \| inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra) } if (edge.manager.minLatency > 0) { assume(a_set =/= d_clr \|\| !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight \| a_set) & ~d_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") assert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = { val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size) val log_a_size_bus_size = log2Ceil(a_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error inflight.suggestName("inflight") val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) inflight_opcodes.suggestName("inflight_opcodes") val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) inflight_sizes.suggestName("inflight_sizes") val a_first = edge.first(bundle.a.bits, bundle.a.fire) a_first.suggestName("a_first") val d_first = edge.first(bundle.d.bits, bundle.d.fire) d_first.suggestName("d_first") val a_set = WireInit(0.U(edge.client.endSourceId.W)) val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) a_set.suggestName("a_set") a_set_wo_ready.suggestName("a_set_wo_ready") val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) a_opcodes_set.suggestName("a_opcodes_set") val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) a_sizes_set.suggestName("a_sizes_set") val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W)) a_opcode_lookup.suggestName("a_opcode_lookup") a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W)) a_size_lookup.suggestName("a_size_lookup") a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant)) val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant)) val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W)) a_opcodes_set_interm.suggestName("a_opcodes_set_interm") val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W)) a_sizes_set_interm.suggestName("a_sizes_set_interm") when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) { a_set_wo_ready := UIntToOH(bundle.a.bits.source) } when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) \| 1.U a_sizes_set_interm := (bundle.a.bits.size << 1.U) \| 1.U a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U) a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U) monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) d_opcodes_clr.suggestName("d_opcodes_clr") val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) \|\| same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) \|\| (bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra) assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) \|\| (bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra) assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) { assume((!bundle.d.ready) \|\| bundle.a.ready, "ready check") } if (edge.manager.minLatency > 0) { assume(a_set_wo_ready =/= d_clr_wo_ready \|\| !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight \| a_set) & ~d_clr inflight_opcodes := (inflight_opcodes \| a_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes \| a_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = { val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size) val log_c_size_bus_size = log2Ceil(c_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) inflight.suggestName("inflight") inflight_opcodes.suggestName("inflight_opcodes") inflight_sizes.suggestName("inflight_sizes") val c_first = edge.first(bundle.c.bits, bundle.c.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) c_first.suggestName("c_first") d_first.suggestName("d_first") val c_set = WireInit(0.U(edge.client.endSourceId.W)) val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) c_set.suggestName("c_set") c_set_wo_ready.suggestName("c_set_wo_ready") c_opcodes_set.suggestName("c_opcodes_set") c_sizes_set.suggestName("c_sizes_set") val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W)) val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W)) c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U c_opcode_lookup.suggestName("c_opcode_lookup") c_size_lookup.suggestName("c_size_lookup") val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W)) val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W)) c_opcodes_set_interm.suggestName("c_opcodes_set_interm") c_sizes_set_interm.suggestName("c_sizes_set_interm") when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) { c_set_wo_ready := UIntToOH(bundle.c.bits.source) } when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) { c_set := UIntToOH(bundle.c.bits.source) c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) \| 1.U c_sizes_set_interm := (bundle.c.bits.size << 1.U) \| 1.U c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U) c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U) monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra) } val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck \|\| bundle.c.bits.opcode === TLMessages.ProbeAckData val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") d_opcodes_clr.suggestName("d_opcodes_clr") d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) \|\| same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) { assume((!bundle.d.ready) \|\| bundle.c.ready, "ready check") } if (edge.manager.minLatency > 0) { when (c_set_wo_ready.orR) { assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra) } } inflight := (inflight \| c_set) & ~d_clr inflight_opcodes := (inflight_opcodes \| c_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes \| c_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.c.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.manager.endSinkId.W)) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val e_first = true.B val d_set = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) { d_set := UIntToOH(bundle.d.bits.sink) assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra) } val e_clr = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) { e_clr := UIntToOH(bundle.e.bits.sink) monAssert((d_set \| inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra) } // edge.client.minLatency applies to BC, not DE inflight := (inflight \| d_set) & ~e_clr } def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = { val sourceBits = log2Ceil(edge.client.endSourceId) val tooBig = 14 // >16kB worth of flight information gets to be too much if (sourceBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked") } else { if (args.edge.params(TestplanTestType).simulation) { if (args.edge.params(TLMonitorStrictMode)) { legalizeADSource(bundle, edge) legalizeCDSource(bundle, edge) } else { legalizeADSourceOld(bundle, edge) } } if (args.edge.params(TestplanTestType).formal) { legalizeADSourceFormal(bundle, edge) } } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { // legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize... val sinkBits = log2Ceil(edge.manager.endSinkId) if (sinkBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked") } else { legalizeDESink(bundle, edge) } } } def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = { legalizeFormat (bundle, edge) legalizeMultibeat (bundle, edge) legalizeUnique (bundle, edge) } } File Misc.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import scala.math._ class ParameterizedBundle(implicit p: Parameters) extends Bundle trait Clocked extends Bundle { val clock = Clock() val reset = Bool() } object DecoupledHelper { def apply(rvs: Bool) = new DecoupledHelper(rvs) } class DecoupledHelper(val rvs: Seq[Bool]) { def fire(exclude: Bool, includes: Bool) = { require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!") (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _) } def fire() = { rvs.reduce(_ && _) } } object MuxT { def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2)) def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3)) def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4)) } /** Creates a cascade of n MuxTs to search for a key value. / object MuxTLookup { def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } } object ValidMux { def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]): ValidIO[T] = { apply(v1 +: v2.toSeq) } def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = { val out = Wire(Valid(valids.head.bits.cloneType)) out.valid := valids.map(_.valid).reduce(_ \|\| _) out.bits := MuxCase(valids.head.bits, valids.map(v => (v.valid -> v.bits))) out } } object Str { def apply(s: String): UInt = { var i = BigInt(0) require(s.forall(validChar _)) for (c <- s) i = (i << 8) \| c i.U((s.length8).W) } def apply(x: Char): UInt = { require(validChar(x)) x.U(8.W) } def apply(x: UInt): UInt = apply(x, 10) def apply(x: UInt, radix: Int): UInt = { val rad = radix.U val w = x.getWidth require(w > 0) var q = x var s = digit(q % rad) for (i <- 1 until ceil(log(2)/log(radix)w).toInt) { q = q / rad s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s) } s } def apply(x: SInt): UInt = apply(x, 10) def apply(x: SInt, radix: Int): UInt = { val neg = x < 0.S val abs = x.abs.asUInt if (radix != 10) { Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix)) } else { val rad = radix.U val w = abs.getWidth require(w > 0) var q = abs var s = digit(q % rad) var needSign = neg for (i <- 1 until ceil(log(2)/log(radix)w).toInt) { q = q / rad val placeSpace = q === 0.U val space = Mux(needSign, Str('-'), Str(' ')) needSign = needSign && !placeSpace s = Cat(Mux(placeSpace, space, digit(q % rad)), s) } Cat(Mux(needSign, Str('-'), Str(' ')), s) } } private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0) private def validChar(x: Char) = x == (x & 0xFF) } object Split { def apply(x: UInt, n0: Int) = { val w = x.getWidth (x.extract(w-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n2: Int, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } } object Random { def apply(mod: Int, random: UInt): UInt = { if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0) else PriorityEncoder(partition(apply(1 << log2Up(mod8), random), mod)) } def apply(mod: Int): UInt = apply(mod, randomizer) def oneHot(mod: Int, random: UInt): UInt = { if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0)) else PriorityEncoderOH(partition(apply(1 << log2Up(mod8), random), mod)).asUInt } def oneHot(mod: Int): UInt = oneHot(mod, randomizer) private def randomizer = LFSR(16) private def partition(value: UInt, slices: Int) = Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U) } object Majority { def apply(in: Set[Bool]): Bool = { val n = (in.size >> 1) + 1 val clauses = in.subsets(n).map(_.reduce(_ && _)) clauses.reduce(_ \|\| _) } def apply(in: Seq[Bool]): Bool = apply(in.toSet) def apply(in: UInt): Bool = apply(in.asBools.toSet) } object PopCountAtLeast { private def two(x: UInt): (Bool, Bool) = x.getWidth match { case 1 => (x.asBool, false.B) case n => val half = x.getWidth / 2 val (leftOne, leftTwo) = two(x(half - 1, 0)) val (rightOne, rightTwo) = two(x(x.getWidth - 1, half)) (leftOne \|\| rightOne, leftTwo \|\| rightTwo \|\| (leftOne && rightOne)) } def apply(x: UInt, n: Int): Bool = n match { case 0 => true.B case 1 => x.orR case 2 => two(x)._2 case 3 => PopCount(x) >= n.U } } // This gets used everywhere, so make the smallest circuit possible ... // Given an address and size, create a mask of beatBytes size // eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111 // groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01 object MaskGen { def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = { require (groupBy >= 1 && beatBytes >= groupBy) require (isPow2(beatBytes) && isPow2(groupBy)) val lgBytes = log2Ceil(beatBytes) val sizeOH = UIntToOH(lgSize \| 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) \| (groupBy2 - 1).U def helper(i: Int): Seq[(Bool, Bool)] = { if (i == 0) { Seq((lgSize >= lgBytes.asUInt, true.B)) } else { val sub = helper(i-1) val size = sizeOH(lgBytes - i) val bit = addr_lo(lgBytes - i) val nbit = !bit Seq.tabulate (1 << i) { j => val (sub_acc, sub_eq) = sub(j/2) val eq = sub_eq && (if (j % 2 == 1) bit else nbit) val acc = sub_acc \|\| (size && eq) (acc, eq) } } } if (groupBy == beatBytes) 1.U else Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse) } } File PlusArg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.experimental._ import chisel3.util.HasBlackBoxResource @deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05") case class PlusArgInfo(default: BigInt, docstring: String) /** Case class for PlusArg information * * @tparam A scala type of the PlusArg value * @param default optional default value * @param docstring text to include in the help * @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT) / private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String) /* Typeclass for converting a type to a doctype string * @tparam A some type / trait Doctypeable[A] { /* Return the doctype string for some option / def toDoctype(a: Option[A]): String } /* Object containing implementations of the Doctypeable typeclass / object Doctypes { /* Converts an Int => "INT" / implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" } /* Converts a BigInt => "INT" / implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" } /* Converts a String => "STRING" / implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" } } class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map( "FORMAT" -> StringParam(format), "DEFAULT" -> IntParam(default), "WIDTH" -> IntParam(width) )) with HasBlackBoxResource { val io = IO(new Bundle { val out = Output(UInt(width.W)) }) addResource("/vsrc/plusarg_reader.v") } / This wrapper class has no outputs, making it clear it is a simulation-only construct / class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module { val io = IO(new Bundle { val count = Input(UInt(width.W)) }) val max = Module(new plusarg_reader(format, default, docstring, width)).io.out when (max > 0.U) { assert (io.count < max, s"Timeout exceeded: $docstring") } } import Doctypes._ object PlusArg { /* PlusArg("foo") will return 42.U if the simulation is run with +foo=42 * Do not use this as an initial register value. The value is set in an * initial block and thus accessing it from another initial is racey. * Add a docstring to document the arg, which can be dumped in an elaboration * pass. / def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out } /* PlusArg.timeout(name, default, docstring)(count) will use chisel.assert * to kill the simulation when count exceeds the specified integer argument. * Default 0 will never assert. / def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count } } object PlusArgArtefacts { private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty / Add a new PlusArg / @deprecated( "Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05" ) def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring) /* Add a new PlusArg * * @tparam A scala type of the PlusArg value * @param name name for the PlusArg * @param default optional default value * @param docstring text to include in the help / def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit = artefacts = artefacts ++ Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default))) / From plus args, generate help text / private def serializeHelp_cHeader(tab: String = ""): String = artefacts .map{ case(arg, info) => s"""\|$tab+$arg=${info.doctype}\\n\\ \|$tab${" "20}${info.docstring}\\n\\ \|""".stripMargin ++ info.default.map{ case default => s"$tab${" "22}(default=${default})\\n\\\n"}.getOrElse("") }.toSeq.mkString("\\n\\\n") ++ "\"" / From plus args, generate a char array of their names / private def serializeArray_cHeader(tab: String = ""): String = { val prettyTab = tab + " " 44 // Length of 'static const ...' s"${tab}static const char * verilog_plusargs [] = {\\\n" ++ artefacts .map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" } .mkString("")++ s"${prettyTab}0};" } /* Generate C code to be included in emulator.cc that helps with * argument parsing based on available Verilog PlusArgs / def serialize_cHeader(): String = s"""\|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\ \|${serializeHelp_cHeader(" "7)} \|${serializeArray_cHeader()} \|""".stripMargin } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /* Like Vec.apply(idx), but tolerates indices of mismatched width / def extract(idx: UInt): T = x((idx \| 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx \| 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def \| (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a \|\| b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_\|\|_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /* Any Data subtype that has a Bool member named valid. / type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /* converts from camel case to to underscores, also removing all spaces / def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /* converts spaces or underscores to hyphens, also lowering case / def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y \| (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y \|\| y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 \| 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /* Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation / def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Bundles.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import freechips.rocketchip.util._ import scala.collection.immutable.ListMap import chisel3.util.Decoupled import chisel3.util.DecoupledIO import chisel3.reflect.DataMirror abstract class TLBundleBase(val params: TLBundleParameters) extends Bundle // common combos in lazy policy: // Put + Acquire // Release + AccessAck object TLMessages { // A B C D E def PutFullData = 0.U // . . => AccessAck def PutPartialData = 1.U // . . => AccessAck def ArithmeticData = 2.U // . . => AccessAckData def LogicalData = 3.U // . . => AccessAckData def Get = 4.U // . . => AccessAckData def Hint = 5.U // . . => HintAck def AcquireBlock = 6.U // . => Grant[Data] def AcquirePerm = 7.U // . => Grant[Data] def Probe = 6.U // . => ProbeAck[Data] def AccessAck = 0.U // . . def AccessAckData = 1.U // . . def HintAck = 2.U // . . def ProbeAck = 4.U // . def ProbeAckData = 5.U // . def Release = 6.U // . => ReleaseAck def ReleaseData = 7.U // . => ReleaseAck def Grant = 4.U // . => GrantAck def GrantData = 5.U // . => GrantAck def ReleaseAck = 6.U // . def GrantAck = 0.U // . def isA(x: UInt) = x <= AcquirePerm def isB(x: UInt) = x <= Probe def isC(x: UInt) = x <= ReleaseData def isD(x: UInt) = x <= ReleaseAck def adResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, Grant, Grant) def bcResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, ProbeAck, ProbeAck) def a = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("AcquireBlock",TLPermissions.PermMsgGrow), ("AcquirePerm",TLPermissions.PermMsgGrow)) def b = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("Probe",TLPermissions.PermMsgCap)) def c = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("ProbeAck",TLPermissions.PermMsgReport), ("ProbeAckData",TLPermissions.PermMsgReport), ("Release",TLPermissions.PermMsgReport), ("ReleaseData",TLPermissions.PermMsgReport)) def d = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("Grant",TLPermissions.PermMsgCap), ("GrantData",TLPermissions.PermMsgCap), ("ReleaseAck",TLPermissions.PermMsgReserved)) } /* * The three primary TileLink permissions are: * (T)runk: the agent is (or is on inwards path to) the global point of serialization. * (B)ranch: the agent is on an outwards path to * (N)one: * These permissions are permuted by transfer operations in various ways. * Operations can cap permissions, request for them to be grown or shrunk, * or for a report on their current status. / object TLPermissions { val aWidth = 2 val bdWidth = 2 val cWidth = 3 // Cap types (Grant = new permissions, Probe = permisions <= target) def toT = 0.U(bdWidth.W) def toB = 1.U(bdWidth.W) def toN = 2.U(bdWidth.W) def isCap(x: UInt) = x <= toN // Grow types (Acquire = permissions >= target) def NtoB = 0.U(aWidth.W) def NtoT = 1.U(aWidth.W) def BtoT = 2.U(aWidth.W) def isGrow(x: UInt) = x <= BtoT // Shrink types (ProbeAck, Release) def TtoB = 0.U(cWidth.W) def TtoN = 1.U(cWidth.W) def BtoN = 2.U(cWidth.W) def isShrink(x: UInt) = x <= BtoN // Report types (ProbeAck, Release) def TtoT = 3.U(cWidth.W) def BtoB = 4.U(cWidth.W) def NtoN = 5.U(cWidth.W) def isReport(x: UInt) = x <= NtoN def PermMsgGrow:Seq[String] = Seq("Grow NtoB", "Grow NtoT", "Grow BtoT") def PermMsgCap:Seq[String] = Seq("Cap toT", "Cap toB", "Cap toN") def PermMsgReport:Seq[String] = Seq("Shrink TtoB", "Shrink TtoN", "Shrink BtoN", "Report TotT", "Report BtoB", "Report NtoN") def PermMsgReserved:Seq[String] = Seq("Reserved") } object TLAtomics { val width = 3 // Arithmetic types def MIN = 0.U(width.W) def MAX = 1.U(width.W) def MINU = 2.U(width.W) def MAXU = 3.U(width.W) def ADD = 4.U(width.W) def isArithmetic(x: UInt) = x <= ADD // Logical types def XOR = 0.U(width.W) def OR = 1.U(width.W) def AND = 2.U(width.W) def SWAP = 3.U(width.W) def isLogical(x: UInt) = x <= SWAP def ArithMsg:Seq[String] = Seq("MIN", "MAX", "MINU", "MAXU", "ADD") def LogicMsg:Seq[String] = Seq("XOR", "OR", "AND", "SWAP") } object TLHints { val width = 1 def PREFETCH_READ = 0.U(width.W) def PREFETCH_WRITE = 1.U(width.W) def isHints(x: UInt) = x <= PREFETCH_WRITE def HintsMsg:Seq[String] = Seq("PrefetchRead", "PrefetchWrite") } sealed trait TLChannel extends TLBundleBase { val channelName: String } sealed trait TLDataChannel extends TLChannel sealed trait TLAddrChannel extends TLDataChannel final class TLBundleA(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleA_${params.shortName}" val channelName = "'A' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(List(TLAtomics.width, TLPermissions.aWidth, TLHints.width).max.W) // amo_opcode \|\| grow perms \|\| hint val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleB(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleB_${params.shortName}" val channelName = "'B' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val address = UInt(params.addressBits.W) // from // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleC(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleC_${params.shortName}" val channelName = "'C' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.cWidth.W) // shrink or report perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleD(params: TLBundleParameters) extends TLBundleBase(params) with TLDataChannel { override def typeName = s"TLBundleD_${params.shortName}" val channelName = "'D' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val sink = UInt(params.sinkBits.W) // from val denied = Bool() // implies corrupt iff Data val user = BundleMap(params.responseFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleE(params: TLBundleParameters) extends TLBundleBase(params) with TLChannel { override def typeName = s"TLBundleE_${params.shortName}" val channelName = "'E' channel" val sink = UInt(params.sinkBits.W) // to } class TLBundle(val params: TLBundleParameters) extends Record { // Emulate a Bundle with elements abcde or ad depending on params.hasBCE private val optA = Some (Decoupled(new TLBundleA(params))) private val optB = params.hasBCE.option(Flipped(Decoupled(new TLBundleB(params)))) private val optC = params.hasBCE.option(Decoupled(new TLBundleC(params))) private val optD = Some (Flipped(Decoupled(new TLBundleD(params)))) private val optE = params.hasBCE.option(Decoupled(new TLBundleE(params))) def a: DecoupledIO[TLBundleA] = optA.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleA(params))))) def b: DecoupledIO[TLBundleB] = optB.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleB(params))))) def c: DecoupledIO[TLBundleC] = optC.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleC(params))))) def d: DecoupledIO[TLBundleD] = optD.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleD(params))))) def e: DecoupledIO[TLBundleE] = optE.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleE(params))))) val elements = if (params.hasBCE) ListMap("e" -> e, "d" -> d, "c" -> c, "b" -> b, "a" -> a) else ListMap("d" -> d, "a" -> a) def tieoff(): Unit = { DataMirror.specifiedDirectionOf(a.ready) match { case SpecifiedDirection.Input => a.ready := false.B c.ready := false.B e.ready := false.B b.valid := false.B d.valid := false.B case SpecifiedDirection.Output => a.valid := false.B c.valid := false.B e.valid := false.B b.ready := false.B d.ready := false.B case _ => } } } object TLBundle { def apply(params: TLBundleParameters) = new TLBundle(params) } class TLAsyncBundleBase(val params: TLAsyncBundleParameters) extends Bundle class TLAsyncBundle(params: TLAsyncBundleParameters) extends TLAsyncBundleBase(params) { val a = new AsyncBundle(new TLBundleA(params.base), params.async) val b = Flipped(new AsyncBundle(new TLBundleB(params.base), params.async)) val c = new AsyncBundle(new TLBundleC(params.base), params.async) val d = Flipped(new AsyncBundle(new TLBundleD(params.base), params.async)) val e = new AsyncBundle(new TLBundleE(params.base), params.async) } class TLRationalBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = RationalIO(new TLBundleA(params)) val b = Flipped(RationalIO(new TLBundleB(params))) val c = RationalIO(new TLBundleC(params)) val d = Flipped(RationalIO(new TLBundleD(params))) val e = RationalIO(new TLBundleE(params)) } class TLCreditedBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = CreditedIO(new TLBundleA(params)) val b = Flipped(CreditedIO(new TLBundleB(params))) val c = CreditedIO(new TLBundleC(params)) val d = Flipped(CreditedIO(new TLBundleD(params))) val e = CreditedIO(new TLBundleE(params)) } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.diplomacy import chisel3._ import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor} import freechips.rocketchip.util.ShiftQueue /** Options for describing the attributes of memory regions / object RegionType { // Define the 'more relaxed than' ordering val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS) sealed trait T extends Ordered[T] { def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this) } case object CACHED extends T // an intermediate agent may have cached a copy of the region for you case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively } // A non-empty half-open range; [start, end) case class IdRange(start: Int, end: Int) extends Ordered[IdRange] { require (start >= 0, s"Ids cannot be negative, but got: $start.") require (start <= end, "Id ranges cannot be negative.") def compare(x: IdRange) = { val primary = (this.start - x.start).signum val secondary = (x.end - this.end).signum if (primary != 0) primary else secondary } def overlaps(x: IdRange) = start < x.end && x.start < end def contains(x: IdRange) = start <= x.start && x.end <= end def contains(x: Int) = start <= x && x < end def contains(x: UInt) = if (size == 0) { false.B } else if (size == 1) { // simple comparison x === start.U } else { // find index of largest different bit val largestDeltaBit = log2Floor(start ^ (end-1)) val smallestCommonBit = largestDeltaBit + 1 // may not exist in x val uncommonMask = (1 << smallestCommonBit) - 1 val uncommonBits = (x \| 0.U(smallestCommonBit.W))(largestDeltaBit, 0) // the prefix must match exactly (note: may shift ALL bits away) (x >> smallestCommonBit) === (start >> smallestCommonBit).U && // firrtl constant prop range analysis can eliminate these two: (start & uncommonMask).U <= uncommonBits && uncommonBits <= ((end-1) & uncommonMask).U } def shift(x: Int) = IdRange(start+x, end+x) def size = end - start def isEmpty = end == start def range = start until end } object IdRange { def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else { val ranges = s.sorted (ranges.tail zip ranges.init) find { case (a, b) => a overlaps b } } } // An potentially empty inclusive range of 2-powers [min, max] (in bytes) case class TransferSizes(min: Int, max: Int) { def this(x: Int) = this(x, x) require (min <= max, s"Min transfer $min > max transfer $max") require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)") require (max == 0 \|\| isPow2(max), s"TransferSizes must be a power of 2, got: $max") require (min == 0 \|\| isPow2(min), s"TransferSizes must be a power of 2, got: $min") require (max == 0 \|\| min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)") def none = min == 0 def contains(x: Int) = isPow2(x) && min <= x && x <= max def containsLg(x: Int) = contains(1 << x) def containsLg(x: UInt) = if (none) false.B else if (min == max) { log2Ceil(min).U === x } else { log2Ceil(min).U <= x && x <= log2Ceil(max).U } def contains(x: TransferSizes) = x.none \|\| (min <= x.min && x.max <= max) def intersect(x: TransferSizes) = if (x.max < min \|\| max < x.min) TransferSizes.none else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max)) // Not a union, because the result may contain sizes contained by neither term // NOT TO BE CONFUSED WITH COVERPOINTS def mincover(x: TransferSizes) = { if (none) { x } else if (x.none) { this } else { TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max)) } } override def toString() = "TransferSizes[%d, %d]".format(min, max) } object TransferSizes { def apply(x: Int) = new TransferSizes(x) val none = new TransferSizes(0) def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _) def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _) implicit def asBool(x: TransferSizes) = !x.none } // AddressSets specify the address space managed by the manager // Base is the base address, and mask are the bits consumed by the manager // e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff // e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ... case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet] { // Forbid misaligned base address (and empty sets) require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}") require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous // We do allow negative mask (=> ignore all high bits) def contains(x: BigInt) = ((x ^ base) & ~mask) == 0 def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S // turn x into an address contained in this set def legalize(x: UInt): UInt = base.U \| (mask.U & x) // overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1) def overlaps(x: AddressSet) = (~(mask \| x.mask) & (base ^ x.base)) == 0 // contains iff bitwise: x.mask => mask && contains(x.base) def contains(x: AddressSet) = ((x.mask \| (base ^ x.base)) & ~mask) == 0 // The number of bytes to which the manager must be aligned def alignment = ((mask + 1) & ~mask) // Is this a contiguous memory range def contiguous = alignment == mask+1 def finite = mask >= 0 def max = { require (finite, "Max cannot be calculated on infinite mask"); base \| mask } // Widen the match function to ignore all bits in imask def widen(imask: BigInt) = AddressSet(base & ~imask, mask \| imask) // Return an AddressSet that only contains the addresses both sets contain def intersect(x: AddressSet): Option[AddressSet] = { if (!overlaps(x)) { None } else { val r_mask = mask & x.mask val r_base = base \| x.base Some(AddressSet(r_base, r_mask)) } } def subtract(x: AddressSet): Seq[AddressSet] = { intersect(x) match { case None => Seq(this) case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit => val nmask = (mask & (bit-1)) \| remove.mask val nbase = (remove.base ^ bit) & ~nmask AddressSet(nbase, nmask) } } } // AddressSets have one natural Ordering (the containment order, if contiguous) def compare(x: AddressSet) = { val primary = (this.base - x.base).signum // smallest address first val secondary = (x.mask - this.mask).signum // largest mask first if (primary != 0) primary else secondary } // We always want to see things in hex override def toString() = { if (mask >= 0) { "AddressSet(0x%x, 0x%x)".format(base, mask) } else { "AddressSet(0x%x, ~0x%x)".format(base, ~mask) } } def toRanges = { require (finite, "Ranges cannot be calculated on infinite mask") val size = alignment val fragments = mask & ~(size-1) val bits = bitIndexes(fragments) (BigInt(0) until (BigInt(1) << bits.size)).map { i => val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) } AddressRange(off, size) } } } object AddressSet { val everything = AddressSet(0, -1) def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = { if (size == 0) tail.reverse else { val maxBaseAlignment = base & (-base) // 0 for infinite (LSB) val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size val step = if (maxBaseAlignment == 0 \|\| maxBaseAlignment > maxSizeAlignment) maxSizeAlignment else maxBaseAlignment misaligned(base+step, size-step, AddressSet(base, step-1) +: tail) } } def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = { // Pair terms up by ignoring 'bit' seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) => if (seq.size == 1) { seq.head // singleton -> unaffected } else { key.copy(mask = key.mask \| bit) // pair - widen mask by bit } }.toList } def unify(seq: Seq[AddressSet]): Seq[AddressSet] = { val bits = seq.map(_.base).foldLeft(BigInt(0))(_ \| _) AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted } def enumerateMask(mask: BigInt): Seq[BigInt] = { def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] = if (id == mask) (id +: tail).reverse else helper(((~mask \| id) + 1) & mask, id +: tail) helper(0, Nil) } def enumerateBits(mask: BigInt): Seq[BigInt] = { def helper(x: BigInt): Seq[BigInt] = { if (x == 0) { Nil } else { val bit = x & (-x) bit +: helper(x & ~bit) } } helper(mask) } } case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean) { require (depth >= 0, "Buffer depth must be >= 0") def isDefined = depth > 0 def latency = if (isDefined && !flow) 1 else 0 def apply[T <: Data](x: DecoupledIO[T]) = if (isDefined) Queue(x, depth, flow=flow, pipe=pipe) else x def irrevocable[T <: Data](x: ReadyValidIO[T]) = if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe) else x def sq[T <: Data](x: DecoupledIO[T]) = if (!isDefined) x else { val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe)) sq.io.enq <> x sq.io.deq } override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "") } object BufferParams { implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false) val default = BufferParams(2) val none = BufferParams(0) val flow = BufferParams(1, true, false) val pipe = BufferParams(1, false, true) } case class TriStateValue(value: Boolean, set: Boolean) { def update(orig: Boolean) = if (set) value else orig } object TriStateValue { implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true) def unset = TriStateValue(false, false) } trait DirectedBuffers[T] { def copyIn(x: BufferParams): T def copyOut(x: BufferParams): T def copyInOut(x: BufferParams): T } trait IdMapEntry { def name: String def from: IdRange def to: IdRange def isCache: Boolean def requestFifo: Boolean def maxTransactionsInFlight: Option[Int] def pretty(fmt: String) = if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5 fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } else { fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } } abstract class IdMap[T <: IdMapEntry] { protected val fmt: String val mapping: Seq[T] def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n") } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportPutFull \|\| manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB \|\| manager.anySupportGet \|\| manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportPutFull \|\| client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe \|\| client.anySupportGet \|\| client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet \|\| client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull \|\| client.anySupportPutPartial \|\| client.anySupportHint \|\| client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet \|\| manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull \|\| manager.anySupportPutPartial \|\| manager.anySupportHint \|\| manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) \|\| !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.ProbeAckData \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode \| small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U \|\| beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }	module TLMonitor_59( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [1:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [8:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [27:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [8:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [1:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [8:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [27:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [8:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_sink = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_denied = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire _source_ok_T = 1'h0; // @[Parameters.scala:54:10] wire _source_ok_T_6 = 1'h0; // @[Parameters.scala:54:10] wire sink_ok = 1'h0; // @[Monitor.scala:309:31] wire a_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire a_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire a_first_count = 1'h0; // @[Edges.scala:234:25] wire d_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire d_first_count = 1'h0; // @[Edges.scala:234:25] wire a_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59] wire a_first_beats1_1 = 1'h0; // @[Edges.scala:221:14] wire a_first_count_1 = 1'h0; // @[Edges.scala:234:25] wire d_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1_1 = 1'h0; // @[Edges.scala:221:14] wire d_first_count_1 = 1'h0; // @[Edges.scala:234:25] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire c_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_first_count_T = 1'h0; // @[Edges.scala:234:27] wire c_first_count = 1'h0; // @[Edges.scala:234:25] wire _c_first_counter_T = 1'h0; // @[Edges.scala:236:21] wire d_first_beats1_decode_2 = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1_2 = 1'h0; // @[Edges.scala:221:14] wire d_first_count_2 = 1'h0; // @[Edges.scala:234:25] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire _source_ok_T_1 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:54:67] wire _source_ok_T_7 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_8 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:54:67] wire _a_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire a_first_last = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire d_first_last = 1'h1; // @[Edges.scala:232:33] wire _a_first_last_T_3 = 1'h1; // @[Edges.scala:232:43] wire a_first_last_1 = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_3 = 1'h1; // @[Edges.scala:232:43] wire d_first_last_1 = 1'h1; // @[Edges.scala:232:33] wire c_first_counter1 = 1'h1; // @[Edges.scala:230:28] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_5 = 1'h1; // @[Edges.scala:232:43] wire d_first_last_2 = 1'h1; // @[Edges.scala:232:33] wire [1:0] _c_first_counter1_T = 2'h3; // @[Edges.scala:230:28] wire [1:0] io_in_d_bits_param = 2'h0; // @[Monitor.scala:36:7] wire [1:0] _c_first_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_first_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_first_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_first_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_set_wo_ready_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_set_wo_ready_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_opcodes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_opcodes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_sizes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_sizes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_opcodes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_opcodes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_sizes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_sizes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_probe_ack_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_probe_ack_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_probe_ack_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_probe_ack_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_4_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_5_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [27:0] _c_first_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_first_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_first_WIRE_2_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_first_WIRE_3_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_set_wo_ready_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_set_wo_ready_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_set_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_set_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_opcodes_set_interm_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_opcodes_set_interm_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_sizes_set_interm_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_sizes_set_interm_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_opcodes_set_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_opcodes_set_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_sizes_set_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_sizes_set_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_probe_ack_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_probe_ack_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_probe_ack_WIRE_2_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_probe_ack_WIRE_3_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _same_cycle_resp_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _same_cycle_resp_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _same_cycle_resp_WIRE_2_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _same_cycle_resp_WIRE_3_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _same_cycle_resp_WIRE_4_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _same_cycle_resp_WIRE_5_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [8:0] _c_first_WIRE_bits_source = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _c_first_WIRE_1_bits_source = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _c_first_WIRE_2_bits_source = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _c_first_WIRE_3_bits_source = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _c_set_wo_ready_WIRE_bits_source = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _c_set_wo_ready_WIRE_1_bits_source = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _c_set_WIRE_bits_source = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _c_set_WIRE_1_bits_source = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _c_opcodes_set_interm_WIRE_bits_source = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _c_opcodes_set_interm_WIRE_1_bits_source = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _c_sizes_set_interm_WIRE_bits_source = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _c_sizes_set_interm_WIRE_1_bits_source = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _c_opcodes_set_WIRE_bits_source = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _c_opcodes_set_WIRE_1_bits_source = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _c_sizes_set_WIRE_bits_source = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _c_sizes_set_WIRE_1_bits_source = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _c_probe_ack_WIRE_bits_source = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _c_probe_ack_WIRE_1_bits_source = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _c_probe_ack_WIRE_2_bits_source = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _c_probe_ack_WIRE_3_bits_source = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _same_cycle_resp_WIRE_bits_source = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _same_cycle_resp_WIRE_1_bits_source = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _same_cycle_resp_WIRE_2_bits_source = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _same_cycle_resp_WIRE_3_bits_source = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _same_cycle_resp_WIRE_4_bits_source = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _same_cycle_resp_WIRE_5_bits_source = 9'h0; // @[Bundles.scala:265:61] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_beats1_decode_T_2 = 3'h0; // @[package.scala:243:46] wire [2:0] c_sizes_set_interm = 3'h0; // @[Monitor.scala:755:40] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_T = 3'h0; // @[Monitor.scala:766:51] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [4097:0] _c_sizes_set_T_1 = 4098'h0; // @[Monitor.scala:768:52] wire [11:0] _c_opcodes_set_T = 12'h0; // @[Monitor.scala:767:79] wire [11:0] _c_sizes_set_T = 12'h0; // @[Monitor.scala:768:77] wire [4098:0] _c_opcodes_set_T_1 = 4099'h0; // @[Monitor.scala:767:54] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] _c_sizes_set_interm_T_1 = 3'h1; // @[Monitor.scala:766:59] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [511:0] _c_set_wo_ready_T = 512'h1; // @[OneHot.scala:58:35] wire [511:0] _c_set_T = 512'h1; // @[OneHot.scala:58:35] wire [1279:0] c_opcodes_set = 1280'h0; // @[Monitor.scala:740:34] wire [1279:0] c_sizes_set = 1280'h0; // @[Monitor.scala:741:34] wire [319:0] c_set = 320'h0; // @[Monitor.scala:738:34] wire [319:0] c_set_wo_ready = 320'h0; // @[Monitor.scala:739:34] wire [2:0] _c_first_beats1_decode_T_1 = 3'h7; // @[package.scala:243:76] wire [5:0] _c_first_beats1_decode_T = 6'h7; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48] wire [8:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _source_ok_uncommonBits_T_1 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] source_ok_uncommonBits = _source_ok_uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_4 = source_ok_uncommonBits < 9'h140; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_5 = _source_ok_T_4; // @[Parameters.scala:56:48, :57:20] wire _source_ok_WIRE_0 = _source_ok_T_5; // @[Parameters.scala:1138:31] wire [5:0] _GEN = 6'h7 << io_in_a_bits_size_0; // @[package.scala:243:71] wire [5:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [5:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [5:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [2:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[2:0]; // @[package.scala:243:{71,76}] wire [2:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [27:0] _is_aligned_T = {25'h0, io_in_a_bits_address_0[2:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 28'h0; // @[Edges.scala:21:{16,24}] wire [2:0] _mask_sizeOH_T = {1'h0, io_in_a_bits_size_0}; // @[Misc.scala:202:34] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = &io_in_a_bits_size_0; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 \| _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 \| _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 \| _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 \| _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 \| _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 \| _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 \| _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 \| _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [8:0] uncommonBits = _uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire [8:0] uncommonBits_1 = _uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire [8:0] uncommonBits_2 = _uncommonBits_T_2; // @[Parameters.scala:52:{29,56}] wire [8:0] uncommonBits_3 = _uncommonBits_T_3; // @[Parameters.scala:52:{29,56}] wire [8:0] uncommonBits_4 = _uncommonBits_T_4; // @[Parameters.scala:52:{29,56}] wire [8:0] uncommonBits_5 = _uncommonBits_T_5; // @[Parameters.scala:52:{29,56}] wire [8:0] uncommonBits_6 = _uncommonBits_T_6; // @[Parameters.scala:52:{29,56}] wire [8:0] uncommonBits_7 = _uncommonBits_T_7; // @[Parameters.scala:52:{29,56}] wire [8:0] uncommonBits_8 = _uncommonBits_T_8; // @[Parameters.scala:52:{29,56}] wire [8:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_10 = source_ok_uncommonBits_1 < 9'h140; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_11 = _source_ok_T_10; // @[Parameters.scala:56:48, :57:20] wire _source_ok_WIRE_1_0 = _source_ok_T_11; // @[Parameters.scala:1138:31] wire _T_672 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_672; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_672; // @[Decoupled.scala:51:35] wire a_first_done = _a_first_T; // @[Decoupled.scala:51:35] wire [2:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] reg a_first_counter; // @[Edges.scala:229:27] wire _a_first_last_T = a_first_counter; // @[Edges.scala:229:27, :232:25] wire [1:0] _a_first_counter1_T = {1'h0, a_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28] wire a_first_counter1 = _a_first_counter1_T[0]; // @[Edges.scala:230:28] wire a_first = ~a_first_counter; // @[Edges.scala:229:27, :231:25] wire _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire _a_first_counter_T = ~a_first & a_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [1:0] size; // @[Monitor.scala:389:22] reg [8:0] source; // @[Monitor.scala:390:22] reg [27:0] address; // @[Monitor.scala:391:22] wire _T_745 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_745; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_745; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_745; // @[Decoupled.scala:51:35] wire d_first_done = _d_first_T; // @[Decoupled.scala:51:35] wire [5:0] _GEN_0 = 6'h7 << io_in_d_bits_size_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [2:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] reg d_first_counter; // @[Edges.scala:229:27] wire _d_first_last_T = d_first_counter; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T = {1'h0, d_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1 = _d_first_counter1_T[0]; // @[Edges.scala:230:28] wire d_first = ~d_first_counter; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T = ~d_first & d_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] size_1; // @[Monitor.scala:540:22] reg [8:0] source_1; // @[Monitor.scala:541:22] reg [319:0] inflight; // @[Monitor.scala:614:27] reg [1279:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [1279:0] inflight_sizes; // @[Monitor.scala:618:33] wire a_first_done_1 = _a_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] reg a_first_counter_1; // @[Edges.scala:229:27] wire _a_first_last_T_2 = a_first_counter_1; // @[Edges.scala:229:27, :232:25] wire [1:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28] wire a_first_counter1_1 = _a_first_counter1_T_1[0]; // @[Edges.scala:230:28] wire a_first_1 = ~a_first_counter_1; // @[Edges.scala:229:27, :231:25] wire _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire _a_first_counter_T_1 = ~a_first_1 & a_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21] wire d_first_done_1 = _d_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] reg d_first_counter_1; // @[Edges.scala:229:27] wire _d_first_last_T_2 = d_first_counter_1; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1_1 = _d_first_counter1_T_1[0]; // @[Edges.scala:230:28] wire d_first_1 = ~d_first_counter_1; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T_1 = ~d_first_1 & d_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21] wire [319:0] a_set; // @[Monitor.scala:626:34] wire [319:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [1279:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [1279:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [11:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [11:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [11:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :641:65] wire [11:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [11:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :681:99] wire [11:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [11:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :750:67] wire [11:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [11:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :791:99] wire [1279:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [1279:0] _a_opcode_lookup_T_6 = {1276'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [1279:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[1279:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [3:0] a_size_lookup; // @[Monitor.scala:639:33] wire [1279:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [1279:0] _a_size_lookup_T_6 = {1276'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}] wire [1279:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[1279:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [2:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [511:0] _GEN_2 = 512'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [511:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_2; // @[OneHot.scala:58:35] wire [511:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_2; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[319:0] : 320'h0; // @[OneHot.scala:58:35] wire _T_598 = _T_672 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_598 ? _a_set_T[319:0] : 320'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_598 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [2:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [2:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[2:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_598 ? _a_sizes_set_interm_T_1 : 3'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [11:0] _GEN_3 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [11:0] _a_opcodes_set_T; // @[Monitor.scala:659:79] assign _a_opcodes_set_T = _GEN_3; // @[Monitor.scala:659:79] wire [11:0] _a_sizes_set_T; // @[Monitor.scala:660:77] assign _a_sizes_set_T = _GEN_3; // @[Monitor.scala:659:79, :660:77] wire [4098:0] _a_opcodes_set_T_1 = {4095'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_598 ? _a_opcodes_set_T_1[1279:0] : 1280'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [4097:0] _a_sizes_set_T_1 = {4095'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_598 ? _a_sizes_set_T_1[1279:0] : 1280'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [319:0] d_clr; // @[Monitor.scala:664:34] wire [319:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [1279:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [1279:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46] wire _T_644 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [511:0] _GEN_5 = 512'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [511:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35] wire [511:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35] wire [511:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35] wire [511:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_644 & ~d_release_ack ? _d_clr_wo_ready_T[319:0] : 320'h0; // @[OneHot.scala:58:35] wire _T_613 = _T_745 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_613 ? _d_clr_T[319:0] : 320'h0; // @[OneHot.scala:58:35] wire [4110:0] _d_opcodes_clr_T_5 = 4111'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_613 ? _d_opcodes_clr_T_5[1279:0] : 1280'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [4110:0] _d_sizes_clr_T_5 = 4111'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_613 ? _d_sizes_clr_T_5[1279:0] : 1280'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [319:0] _inflight_T = inflight \| a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [319:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [319:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [1279:0] _inflight_opcodes_T = inflight_opcodes \| a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [1279:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [1279:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [1279:0] _inflight_sizes_T = inflight_sizes \| a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [1279:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [1279:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [319:0] inflight_1; // @[Monitor.scala:726:35] wire [319:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [1279:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [1279:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [1279:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [1279:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire d_first_done_2 = _d_first_T_2; // @[Decoupled.scala:51:35] wire [2:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] reg d_first_counter_2; // @[Edges.scala:229:27] wire _d_first_last_T_4 = d_first_counter_2; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1_2 = _d_first_counter1_T_2[0]; // @[Edges.scala:230:28] wire d_first_2 = ~d_first_counter_2; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T_2 = ~d_first_2 & d_first_counter1_2; // @[Edges.scala:230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [3:0] c_size_lookup; // @[Monitor.scala:748:35] wire [1279:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [1279:0] _c_opcode_lookup_T_6 = {1276'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [1279:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[1279:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [1279:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [1279:0] _c_size_lookup_T_6 = {1276'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}] wire [1279:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[1279:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [319:0] d_clr_1; // @[Monitor.scala:774:34] wire [319:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [1279:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [1279:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_716 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_716 & d_release_ack_1 ? _d_clr_wo_ready_T_1[319:0] : 320'h0; // @[OneHot.scala:58:35] wire _T_698 = _T_745 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_698 ? _d_clr_T_1[319:0] : 320'h0; // @[OneHot.scala:58:35] wire [4110:0] _d_opcodes_clr_T_11 = 4111'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_698 ? _d_opcodes_clr_T_11[1279:0] : 1280'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [4110:0] _d_sizes_clr_T_11 = 4111'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_698 ? _d_sizes_clr_T_11[1279:0] : 1280'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 9'h0; // @[Monitor.scala:36:7, :795:113] wire [319:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [319:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [1279:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [1279:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [1279:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [1279:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to the following Chisel files. File primitives.scala: /============================================================================ This Chisel source file is part of a pre-release version of the HardFloat IEEE Floating-Point Arithmetic Package, by John R. Hauser (with some contributions from Yunsup Lee and Andrew Waterman, mainly concerning testing). Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the University of California. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions, and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions, and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the University nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. =============================================================================/ package hardfloat import chisel3._ import chisel3.util._ //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- object lowMask { def apply(in: UInt, topBound: BigInt, bottomBound: BigInt): UInt = { require(topBound != bottomBound) val numInVals = BigInt(1)<<in.getWidth if (topBound < bottomBound) { lowMask(~in, numInVals - 1 - topBound, numInVals - 1 - bottomBound) } else if (numInVals > 64 /* Empirical /) { // For simulation performance, we should avoid generating // exteremely wide shifters, so we divide and conquer. // Empirically, this does not impact synthesis QoR. val mid = numInVals / 2 val msb = in(in.getWidth - 1) val lsbs = in(in.getWidth - 2, 0) if (mid < topBound) { if (mid <= bottomBound) { Mux(msb, lowMask(lsbs, topBound - mid, bottomBound - mid), 0.U ) } else { Mux(msb, lowMask(lsbs, topBound - mid, 0) ## ((BigInt(1)<<(mid - bottomBound).toInt) - 1).U, lowMask(lsbs, mid, bottomBound) ) } } else { ~Mux(msb, 0.U, ~lowMask(lsbs, topBound, bottomBound)) } } else { val shift = (BigInt(-1)<<numInVals.toInt).S>>in Reverse( shift( (numInVals - 1 - bottomBound).toInt, (numInVals - topBound).toInt ) ) } } } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- object countLeadingZeros { def apply(in: UInt): UInt = PriorityEncoder(in.asBools.reverse) } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- object orReduceBy2 { def apply(in: UInt): UInt = { val reducedWidth = (in.getWidth + 1)>>1 val reducedVec = Wire(Vec(reducedWidth, Bool())) for (ix <- 0 until reducedWidth - 1) { reducedVec(ix) := in(ix 2 + 1, ix * 2).orR } reducedVec(reducedWidth - 1) := in(in.getWidth - 1, (reducedWidth - 1) * 2).orR reducedVec.asUInt } } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- object orReduceBy4 { def apply(in: UInt): UInt = { val reducedWidth = (in.getWidth + 3)>>2 val reducedVec = Wire(Vec(reducedWidth, Bool())) for (ix <- 0 until reducedWidth - 1) { reducedVec(ix) := in(ix * 4 + 3, ix * 4).orR } reducedVec(reducedWidth - 1) := in(in.getWidth - 1, (reducedWidth - 1) * 4).orR reducedVec.asUInt } } File RoundAnyRawFNToRecFN.scala: /============================================================================ This Chisel source file is part of a pre-release version of the HardFloat IEEE Floating-Point Arithmetic Package, by John R. Hauser (with some contributions from Yunsup Lee and Andrew Waterman, mainly concerning testing). Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the University of California. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions, and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions, and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the University nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. =============================================================================/ package hardfloat import chisel3._ import chisel3.util.Fill import consts._ //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- class RoundAnyRawFNToRecFN( inExpWidth: Int, inSigWidth: Int, outExpWidth: Int, outSigWidth: Int, options: Int ) extends RawModule { override def desiredName = s"RoundAnyRawFNToRecFN_ie${inExpWidth}_is${inSigWidth}_oe${outExpWidth}_os${outSigWidth}" val io = IO(new Bundle { val invalidExc = Input(Bool()) // overrides 'infiniteExc' and 'in' val infiniteExc = Input(Bool()) // overrides 'in' except for 'in.sign' val in = Input(new RawFloat(inExpWidth, inSigWidth)) // (allowed exponent range has limits) val roundingMode = Input(UInt(3.W)) val detectTininess = Input(UInt(1.W)) val out = Output(Bits((outExpWidth + outSigWidth + 1).W)) val exceptionFlags = Output(Bits(5.W)) }) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val sigMSBitAlwaysZero = ((options & flRoundOpt_sigMSBitAlwaysZero) != 0) val effectiveInSigWidth = if (sigMSBitAlwaysZero) inSigWidth else inSigWidth + 1 val neverUnderflows = ((options & (flRoundOpt_neverUnderflows \| flRoundOpt_subnormsAlwaysExact) ) != 0) \|\| (inExpWidth < outExpWidth) val neverOverflows = ((options & flRoundOpt_neverOverflows) != 0) \|\| (inExpWidth < outExpWidth) val outNaNExp = BigInt(7)<<(outExpWidth - 2) val outInfExp = BigInt(6)<<(outExpWidth - 2) val outMaxFiniteExp = outInfExp - 1 val outMinNormExp = (BigInt(1)<<(outExpWidth - 1)) + 2 val outMinNonzeroExp = outMinNormExp - outSigWidth + 1 //------------------------------------------------------------------------ //------------------------------------------------------------------------ val roundingMode_near_even = (io.roundingMode === round_near_even) val roundingMode_minMag = (io.roundingMode === round_minMag) val roundingMode_min = (io.roundingMode === round_min) val roundingMode_max = (io.roundingMode === round_max) val roundingMode_near_maxMag = (io.roundingMode === round_near_maxMag) val roundingMode_odd = (io.roundingMode === round_odd) val roundMagUp = (roundingMode_min && io.in.sign) \|\| (roundingMode_max && ! io.in.sign) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val sAdjustedExp = if (inExpWidth < outExpWidth) (io.in.sExp +& ((BigInt(1)<<outExpWidth) - (BigInt(1)<<inExpWidth)).S )(outExpWidth, 0).zext else if (inExpWidth == outExpWidth) io.in.sExp else io.in.sExp +& ((BigInt(1)<<outExpWidth) - (BigInt(1)<<inExpWidth)).S val adjustedSig = if (inSigWidth <= outSigWidth + 2) io.in.sig<<(outSigWidth - inSigWidth + 2) else (io.in.sig(inSigWidth, inSigWidth - outSigWidth - 1) ## io.in.sig(inSigWidth - outSigWidth - 2, 0).orR ) val doShiftSigDown1 = if (sigMSBitAlwaysZero) false.B else adjustedSig(outSigWidth + 2) val common_expOut = Wire(UInt((outExpWidth + 1).W)) val common_fractOut = Wire(UInt((outSigWidth - 1).W)) val common_overflow = Wire(Bool()) val common_totalUnderflow = Wire(Bool()) val common_underflow = Wire(Bool()) val common_inexact = Wire(Bool()) if ( neverOverflows && neverUnderflows && (effectiveInSigWidth <= outSigWidth) ) { //-------------------------------------------------------------------- //-------------------------------------------------------------------- common_expOut := sAdjustedExp(outExpWidth, 0) + doShiftSigDown1 common_fractOut := Mux(doShiftSigDown1, adjustedSig(outSigWidth + 1, 3), adjustedSig(outSigWidth, 2) ) common_overflow := false.B common_totalUnderflow := false.B common_underflow := false.B common_inexact := false.B } else { //-------------------------------------------------------------------- //-------------------------------------------------------------------- val roundMask = if (neverUnderflows) 0.U(outSigWidth.W) ## doShiftSigDown1 ## 3.U(2.W) else (lowMask( sAdjustedExp(outExpWidth, 0), outMinNormExp - outSigWidth - 1, outMinNormExp ) \| doShiftSigDown1) ## 3.U(2.W) val shiftedRoundMask = 0.U(1.W) ## roundMask>>1 val roundPosMask = ~shiftedRoundMask & roundMask val roundPosBit = (adjustedSig & roundPosMask).orR val anyRoundExtra = (adjustedSig & shiftedRoundMask).orR val anyRound = roundPosBit \|\| anyRoundExtra val roundIncr = ((roundingMode_near_even \|\| roundingMode_near_maxMag) && roundPosBit) \|\| (roundMagUp && anyRound) val roundedSig: Bits = Mux(roundIncr, (((adjustedSig \| roundMask)>>2) +& 1.U) & ~Mux(roundingMode_near_even && roundPosBit && ! anyRoundExtra, roundMask>>1, 0.U((outSigWidth + 2).W) ), (adjustedSig & ~roundMask)>>2 \| Mux(roundingMode_odd && anyRound, roundPosMask>>1, 0.U) ) //* IF SIG WIDTH IS VERY NARROW, NEED TO ACCOUNT FOR ROUND-EVEN ZEROING //* M.S. BIT OF SUBNORMAL SIG? val sRoundedExp = sAdjustedExp +& (roundedSig>>outSigWidth).asUInt.zext common_expOut := sRoundedExp(outExpWidth, 0) common_fractOut := Mux(doShiftSigDown1, roundedSig(outSigWidth - 1, 1), roundedSig(outSigWidth - 2, 0) ) common_overflow := (if (neverOverflows) false.B else //* REWRITE BASED ON BEFORE-ROUNDING EXPONENT?: (sRoundedExp>>(outExpWidth - 1) >= 3.S)) common_totalUnderflow := (if (neverUnderflows) false.B else //* WOULD BE GOOD ENOUGH TO USE EXPONENT BEFORE ROUNDING?: (sRoundedExp < outMinNonzeroExp.S)) val unboundedRange_roundPosBit = Mux(doShiftSigDown1, adjustedSig(2), adjustedSig(1)) val unboundedRange_anyRound = (doShiftSigDown1 && adjustedSig(2)) \|\| adjustedSig(1, 0).orR val unboundedRange_roundIncr = ((roundingMode_near_even \|\| roundingMode_near_maxMag) && unboundedRange_roundPosBit) \|\| (roundMagUp && unboundedRange_anyRound) val roundCarry = Mux(doShiftSigDown1, roundedSig(outSigWidth + 1), roundedSig(outSigWidth) ) common_underflow := (if (neverUnderflows) false.B else common_totalUnderflow \|\| //* IF SIG WIDTH IS VERY NARROW, NEED TO ACCOUNT FOR ROUND-EVEN ZEROING //* M.S. BIT OF SUBNORMAL SIG? (anyRound && ((sAdjustedExp>>outExpWidth) <= 0.S) && Mux(doShiftSigDown1, roundMask(3), roundMask(2)) && ! ((io.detectTininess === tininess_afterRounding) && ! Mux(doShiftSigDown1, roundMask(4), roundMask(3) ) && roundCarry && roundPosBit && unboundedRange_roundIncr))) common_inexact := common_totalUnderflow \|\| anyRound } //------------------------------------------------------------------------ //------------------------------------------------------------------------ val isNaNOut = io.invalidExc \|\| io.in.isNaN val notNaN_isSpecialInfOut = io.infiniteExc \|\| io.in.isInf val commonCase = ! isNaNOut && ! notNaN_isSpecialInfOut && ! io.in.isZero val overflow = commonCase && common_overflow val underflow = commonCase && common_underflow val inexact = overflow \|\| (commonCase && common_inexact) val overflow_roundMagUp = roundingMode_near_even \|\| roundingMode_near_maxMag \|\| roundMagUp val pegMinNonzeroMagOut = commonCase && common_totalUnderflow && (roundMagUp \|\| roundingMode_odd) val pegMaxFiniteMagOut = overflow && ! overflow_roundMagUp val notNaN_isInfOut = notNaN_isSpecialInfOut \|\| (overflow && overflow_roundMagUp) val signOut = Mux(isNaNOut, false.B, io.in.sign) val expOut = (common_expOut & ~Mux(io.in.isZero \|\| common_totalUnderflow, (BigInt(7)<<(outExpWidth - 2)).U((outExpWidth + 1).W), 0.U ) & ~Mux(pegMinNonzeroMagOut, ~outMinNonzeroExp.U((outExpWidth + 1).W), 0.U ) & ~Mux(pegMaxFiniteMagOut, (BigInt(1)<<(outExpWidth - 1)).U((outExpWidth + 1).W), 0.U ) & ~Mux(notNaN_isInfOut, (BigInt(1)<<(outExpWidth - 2)).U((outExpWidth + 1).W), 0.U )) \| Mux(pegMinNonzeroMagOut, outMinNonzeroExp.U((outExpWidth + 1).W), 0.U ) \| Mux(pegMaxFiniteMagOut, outMaxFiniteExp.U((outExpWidth + 1).W), 0.U ) \| Mux(notNaN_isInfOut, outInfExp.U((outExpWidth + 1).W), 0.U) \| Mux(isNaNOut, outNaNExp.U((outExpWidth + 1).W), 0.U) val fractOut = Mux(isNaNOut \|\| io.in.isZero \|\| common_totalUnderflow, Mux(isNaNOut, (BigInt(1)<<(outSigWidth - 2)).U, 0.U), common_fractOut ) \| Fill(outSigWidth - 1, pegMaxFiniteMagOut) io.out := signOut ## expOut ## fractOut io.exceptionFlags := io.invalidExc ## io.infiniteExc ## overflow ## underflow ## inexact } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- class RoundRawFNToRecFN(expWidth: Int, sigWidth: Int, options: Int) extends RawModule { override def desiredName = s"RoundRawFNToRecFN_e${expWidth}_s${sigWidth}" val io = IO(new Bundle { val invalidExc = Input(Bool()) // overrides 'infiniteExc' and 'in' val infiniteExc = Input(Bool()) // overrides 'in' except for 'in.sign' val in = Input(new RawFloat(expWidth, sigWidth + 2)) val roundingMode = Input(UInt(3.W)) val detectTininess = Input(UInt(1.W)) val out = Output(Bits((expWidth + sigWidth + 1).W)) val exceptionFlags = Output(Bits(5.W)) }) val roundAnyRawFNToRecFN = Module( new RoundAnyRawFNToRecFN( expWidth, sigWidth + 2, expWidth, sigWidth, options)) roundAnyRawFNToRecFN.io.invalidExc := io.invalidExc roundAnyRawFNToRecFN.io.infiniteExc := io.infiniteExc roundAnyRawFNToRecFN.io.in := io.in roundAnyRawFNToRecFN.io.roundingMode := io.roundingMode roundAnyRawFNToRecFN.io.detectTininess := io.detectTininess io.out := roundAnyRawFNToRecFN.io.out io.exceptionFlags := roundAnyRawFNToRecFN.io.exceptionFlags }	module RoundAnyRawFNToRecFN_ie8_is26_oe8_os24_75( // @[RoundAnyRawFNToRecFN.scala:48:5] input io_invalidExc, // @[RoundAnyRawFNToRecFN.scala:58:16] input io_in_isNaN, // @[RoundAnyRawFNToRecFN.scala:58:16] input io_in_isInf, // @[RoundAnyRawFNToRecFN.scala:58:16] input io_in_isZero, // @[RoundAnyRawFNToRecFN.scala:58:16] input io_in_sign, // @[RoundAnyRawFNToRecFN.scala:58:16] input [9:0] io_in_sExp, // @[RoundAnyRawFNToRecFN.scala:58:16] input [26:0] io_in_sig, // @[RoundAnyRawFNToRecFN.scala:58:16] output [32:0] io_out, // @[RoundAnyRawFNToRecFN.scala:58:16] output [4:0] io_exceptionFlags // @[RoundAnyRawFNToRecFN.scala:58:16] ); wire io_invalidExc_0 = io_invalidExc; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_isNaN_0 = io_in_isNaN; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_isInf_0 = io_in_isInf; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_isZero_0 = io_in_isZero; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_sign_0 = io_in_sign; // @[RoundAnyRawFNToRecFN.scala:48:5] wire [9:0] io_in_sExp_0 = io_in_sExp; // @[RoundAnyRawFNToRecFN.scala:48:5] wire [26:0] io_in_sig_0 = io_in_sig; // @[RoundAnyRawFNToRecFN.scala:48:5] wire [8:0] _expOut_T_4 = 9'h194; // @[RoundAnyRawFNToRecFN.scala:258:19] wire [15:0] _roundMask_T_5 = 16'hFF; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_4 = 16'hFF00; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_10 = 16'hFF00; // @[primitives.scala:77:20] wire [11:0] _roundMask_T_13 = 12'hFF; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_14 = 16'hFF0; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_15 = 16'hF0F; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_20 = 16'hF0F0; // @[primitives.scala:77:20] wire [13:0] _roundMask_T_23 = 14'hF0F; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_24 = 16'h3C3C; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_25 = 16'h3333; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_30 = 16'hCCCC; // @[primitives.scala:77:20] wire [14:0] _roundMask_T_33 = 15'h3333; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_34 = 16'h6666; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_35 = 16'h5555; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_40 = 16'hAAAA; // @[primitives.scala:77:20] wire [25:0] _roundedSig_T_15 = 26'h0; // @[RoundAnyRawFNToRecFN.scala:181:24] wire [8:0] _expOut_T_6 = 9'h1FF; // @[RoundAnyRawFNToRecFN.scala:257:14, :261:14] wire [8:0] _expOut_T_9 = 9'h1FF; // @[RoundAnyRawFNToRecFN.scala:257:14, :261:14] wire [8:0] _expOut_T_5 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:257:18] wire [8:0] _expOut_T_8 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:261:18] wire [8:0] _expOut_T_14 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:269:16] wire [8:0] _expOut_T_16 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:273:16] wire [22:0] _fractOut_T_4 = 23'h0; // @[RoundAnyRawFNToRecFN.scala:284:13] wire io_detectTininess = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5] wire roundingMode_near_even = 1'h1; // @[RoundAnyRawFNToRecFN.scala:90:53] wire _roundIncr_T = 1'h1; // @[RoundAnyRawFNToRecFN.scala:169:38] wire _unboundedRange_roundIncr_T = 1'h1; // @[RoundAnyRawFNToRecFN.scala:207:38] wire _common_underflow_T_7 = 1'h1; // @[RoundAnyRawFNToRecFN.scala:222:49] wire _overflow_roundMagUp_T = 1'h1; // @[RoundAnyRawFNToRecFN.scala:243:32] wire overflow_roundMagUp = 1'h1; // @[RoundAnyRawFNToRecFN.scala:243:60] wire [2:0] io_roundingMode = 3'h0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_infiniteExc = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire roundingMode_minMag = 1'h0; // @[RoundAnyRawFNToRecFN.scala:91:53] wire roundingMode_min = 1'h0; // @[RoundAnyRawFNToRecFN.scala:92:53] wire roundingMode_max = 1'h0; // @[RoundAnyRawFNToRecFN.scala:93:53] wire roundingMode_near_maxMag = 1'h0; // @[RoundAnyRawFNToRecFN.scala:94:53] wire roundingMode_odd = 1'h0; // @[RoundAnyRawFNToRecFN.scala:95:53] wire _roundMagUp_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:98:27] wire _roundMagUp_T_2 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:98:63] wire roundMagUp = 1'h0; // @[RoundAnyRawFNToRecFN.scala:98:42] wire _roundIncr_T_2 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:171:29] wire _roundedSig_T_13 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:181:42] wire _unboundedRange_roundIncr_T_2 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:209:29] wire _pegMinNonzeroMagOut_T_1 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:245:60] wire pegMinNonzeroMagOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:245:45] wire _pegMaxFiniteMagOut_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:246:42] wire pegMaxFiniteMagOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:246:39] wire notNaN_isSpecialInfOut = io_in_isInf_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :236:49] wire [26:0] adjustedSig = io_in_sig_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :114:22] wire [32:0] _io_out_T_1; // @[RoundAnyRawFNToRecFN.scala:286:33] wire [4:0] _io_exceptionFlags_T_3; // @[RoundAnyRawFNToRecFN.scala:288:66] wire [32:0] io_out_0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire [4:0] io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire _roundMagUp_T_1 = ~io_in_sign_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :98:66] wire doShiftSigDown1 = adjustedSig[26]; // @[RoundAnyRawFNToRecFN.scala:114:22, :120:57] wire [8:0] _common_expOut_T; // @[RoundAnyRawFNToRecFN.scala:187:37] wire [8:0] common_expOut; // @[RoundAnyRawFNToRecFN.scala:122:31] wire [22:0] _common_fractOut_T_2; // @[RoundAnyRawFNToRecFN.scala:189:16] wire [22:0] common_fractOut; // @[RoundAnyRawFNToRecFN.scala:123:31] wire _common_overflow_T_1; // @[RoundAnyRawFNToRecFN.scala:196:50] wire common_overflow; // @[RoundAnyRawFNToRecFN.scala:124:37] wire _common_totalUnderflow_T; // @[RoundAnyRawFNToRecFN.scala:200:31] wire common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:125:37] wire _common_underflow_T_18; // @[RoundAnyRawFNToRecFN.scala:217:40] wire common_underflow; // @[RoundAnyRawFNToRecFN.scala:126:37] wire _common_inexact_T; // @[RoundAnyRawFNToRecFN.scala:230:49] wire common_inexact; // @[RoundAnyRawFNToRecFN.scala:127:37] wire [8:0] _roundMask_T = io_in_sExp_0[8:0]; // @[RoundAnyRawFNToRecFN.scala:48:5, :156:37] wire [8:0] _roundMask_T_1 = ~_roundMask_T; // @[primitives.scala:52:21] wire roundMask_msb = _roundMask_T_1[8]; // @[primitives.scala:52:21, :58:25] wire [7:0] roundMask_lsbs = _roundMask_T_1[7:0]; // @[primitives.scala:52:21, :59:26] wire roundMask_msb_1 = roundMask_lsbs[7]; // @[primitives.scala:58:25, :59:26] wire [6:0] roundMask_lsbs_1 = roundMask_lsbs[6:0]; // @[primitives.scala:59:26] wire roundMask_msb_2 = roundMask_lsbs_1[6]; // @[primitives.scala:58:25, :59:26] wire roundMask_msb_3 = roundMask_lsbs_1[6]; // @[primitives.scala:58:25, :59:26] wire [5:0] roundMask_lsbs_2 = roundMask_lsbs_1[5:0]; // @[primitives.scala:59:26] wire [5:0] roundMask_lsbs_3 = roundMask_lsbs_1[5:0]; // @[primitives.scala:59:26] wire [64:0] roundMask_shift = $signed(65'sh10000000000000000 >>> roundMask_lsbs_2); // @[primitives.scala:59:26, :76:56] wire [21:0] _roundMask_T_2 = roundMask_shift[63:42]; // @[primitives.scala:76:56, :78:22] wire [15:0] _roundMask_T_3 = _roundMask_T_2[15:0]; // @[primitives.scala:77:20, :78:22] wire [7:0] _roundMask_T_6 = _roundMask_T_3[15:8]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_7 = {8'h0, _roundMask_T_6}; // @[primitives.scala:77:20] wire [7:0] _roundMask_T_8 = _roundMask_T_3[7:0]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_9 = {_roundMask_T_8, 8'h0}; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_11 = _roundMask_T_9 & 16'hFF00; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_12 = _roundMask_T_7 \| _roundMask_T_11; // @[primitives.scala:77:20] wire [11:0] _roundMask_T_16 = _roundMask_T_12[15:4]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_17 = {4'h0, _roundMask_T_16 & 12'hF0F}; // @[primitives.scala:77:20] wire [11:0] _roundMask_T_18 = _roundMask_T_12[11:0]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_19 = {_roundMask_T_18, 4'h0}; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_21 = _roundMask_T_19 & 16'hF0F0; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_22 = _roundMask_T_17 \| _roundMask_T_21; // @[primitives.scala:77:20] wire [13:0] _roundMask_T_26 = _roundMask_T_22[15:2]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_27 = {2'h0, _roundMask_T_26 & 14'h3333}; // @[primitives.scala:77:20] wire [13:0] _roundMask_T_28 = _roundMask_T_22[13:0]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_29 = {_roundMask_T_28, 2'h0}; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_31 = _roundMask_T_29 & 16'hCCCC; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_32 = _roundMask_T_27 \| _roundMask_T_31; // @[primitives.scala:77:20] wire [14:0] _roundMask_T_36 = _roundMask_T_32[15:1]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_37 = {1'h0, _roundMask_T_36 & 15'h5555}; // @[primitives.scala:77:20] wire [14:0] _roundMask_T_38 = _roundMask_T_32[14:0]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_39 = {_roundMask_T_38, 1'h0}; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_41 = _roundMask_T_39 & 16'hAAAA; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_42 = _roundMask_T_37 \| _roundMask_T_41; // @[primitives.scala:77:20] wire [5:0] _roundMask_T_43 = _roundMask_T_2[21:16]; // @[primitives.scala:77:20, :78:22] wire [3:0] _roundMask_T_44 = _roundMask_T_43[3:0]; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_45 = _roundMask_T_44[1:0]; // @[primitives.scala:77:20] wire _roundMask_T_46 = _roundMask_T_45[0]; // @[primitives.scala:77:20] wire _roundMask_T_47 = _roundMask_T_45[1]; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_48 = {_roundMask_T_46, _roundMask_T_47}; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_49 = _roundMask_T_44[3:2]; // @[primitives.scala:77:20] wire _roundMask_T_50 = _roundMask_T_49[0]; // @[primitives.scala:77:20] wire _roundMask_T_51 = _roundMask_T_49[1]; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_52 = {_roundMask_T_50, _roundMask_T_51}; // @[primitives.scala:77:20] wire [3:0] _roundMask_T_53 = {_roundMask_T_48, _roundMask_T_52}; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_54 = _roundMask_T_43[5:4]; // @[primitives.scala:77:20] wire _roundMask_T_55 = _roundMask_T_54[0]; // @[primitives.scala:77:20] wire _roundMask_T_56 = _roundMask_T_54[1]; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_57 = {_roundMask_T_55, _roundMask_T_56}; // @[primitives.scala:77:20] wire [5:0] _roundMask_T_58 = {_roundMask_T_53, _roundMask_T_57}; // @[primitives.scala:77:20] wire [21:0] _roundMask_T_59 = {_roundMask_T_42, _roundMask_T_58}; // @[primitives.scala:77:20] wire [21:0] _roundMask_T_60 = ~_roundMask_T_59; // @[primitives.scala:73:32, :77:20] wire [21:0] _roundMask_T_61 = roundMask_msb_2 ? 22'h0 : _roundMask_T_60; // @[primitives.scala:58:25, :73:{21,32}] wire [21:0] _roundMask_T_62 = ~_roundMask_T_61; // @[primitives.scala:73:{17,21}] wire [24:0] _roundMask_T_63 = {_roundMask_T_62, 3'h7}; // @[primitives.scala:68:58, :73:17] wire [64:0] roundMask_shift_1 = $signed(65'sh10000000000000000 >>> roundMask_lsbs_3); // @[primitives.scala:59:26, :76:56] wire [2:0] _roundMask_T_64 = roundMask_shift_1[2:0]; // @[primitives.scala:76:56, :78:22] wire [1:0] _roundMask_T_65 = _roundMask_T_64[1:0]; // @[primitives.scala:77:20, :78:22] wire _roundMask_T_66 = _roundMask_T_65[0]; // @[primitives.scala:77:20] wire _roundMask_T_67 = _roundMask_T_65[1]; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_68 = {_roundMask_T_66, _roundMask_T_67}; // @[primitives.scala:77:20] wire _roundMask_T_69 = _roundMask_T_64[2]; // @[primitives.scala:77:20, :78:22] wire [2:0] _roundMask_T_70 = {_roundMask_T_68, _roundMask_T_69}; // @[primitives.scala:77:20] wire [2:0] _roundMask_T_71 = roundMask_msb_3 ? _roundMask_T_70 : 3'h0; // @[primitives.scala:58:25, :62:24, :77:20] wire [24:0] _roundMask_T_72 = roundMask_msb_1 ? _roundMask_T_63 : {22'h0, _roundMask_T_71}; // @[primitives.scala:58:25, :62:24, :67:24, :68:58] wire [24:0] _roundMask_T_73 = roundMask_msb ? _roundMask_T_72 : 25'h0; // @[primitives.scala:58:25, :62:24, :67:24] wire [24:0] _roundMask_T_74 = {_roundMask_T_73[24:1], _roundMask_T_73[0] \| doShiftSigDown1}; // @[primitives.scala:62:24] wire [26:0] roundMask = {_roundMask_T_74, 2'h3}; // @[RoundAnyRawFNToRecFN.scala:159:{23,42}] wire [27:0] _shiftedRoundMask_T = {1'h0, roundMask}; // @[RoundAnyRawFNToRecFN.scala:159:42, :162:41] wire [26:0] shiftedRoundMask = _shiftedRoundMask_T[27:1]; // @[RoundAnyRawFNToRecFN.scala:162:{41,53}] wire [26:0] _roundPosMask_T = ~shiftedRoundMask; // @[RoundAnyRawFNToRecFN.scala:162:53, :163:28] wire [26:0] roundPosMask = _roundPosMask_T & roundMask; // @[RoundAnyRawFNToRecFN.scala:159:42, :163:{28,46}] wire [26:0] _roundPosBit_T = adjustedSig & roundPosMask; // @[RoundAnyRawFNToRecFN.scala:114:22, :163:46, :164:40] wire roundPosBit = \|_roundPosBit_T; // @[RoundAnyRawFNToRecFN.scala:164:{40,56}] wire _roundIncr_T_1 = roundPosBit; // @[RoundAnyRawFNToRecFN.scala:164:56, :169:67] wire _roundedSig_T_3 = roundPosBit; // @[RoundAnyRawFNToRecFN.scala:164:56, :175:49] wire [26:0] _anyRoundExtra_T = adjustedSig & shiftedRoundMask; // @[RoundAnyRawFNToRecFN.scala:114:22, :162:53, :165:42] wire anyRoundExtra = \|_anyRoundExtra_T; // @[RoundAnyRawFNToRecFN.scala:165:{42,62}] wire anyRound = roundPosBit \| anyRoundExtra; // @[RoundAnyRawFNToRecFN.scala:164:56, :165:62, :166:36] wire roundIncr = _roundIncr_T_1; // @[RoundAnyRawFNToRecFN.scala:169:67, :170:31] wire [26:0] _roundedSig_T = adjustedSig \| roundMask; // @[RoundAnyRawFNToRecFN.scala:114:22, :159:42, :174:32] wire [24:0] _roundedSig_T_1 = _roundedSig_T[26:2]; // @[RoundAnyRawFNToRecFN.scala:174:{32,44}] wire [25:0] _roundedSig_T_2 = {1'h0, _roundedSig_T_1} + 26'h1; // @[RoundAnyRawFNToRecFN.scala:174:{44,49}] wire _roundedSig_T_4 = ~anyRoundExtra; // @[RoundAnyRawFNToRecFN.scala:165:62, :176:30] wire _roundedSig_T_5 = _roundedSig_T_3 & _roundedSig_T_4; // @[RoundAnyRawFNToRecFN.scala:175:{49,64}, :176:30] wire [25:0] _roundedSig_T_6 = roundMask[26:1]; // @[RoundAnyRawFNToRecFN.scala:159:42, :177:35] wire [25:0] _roundedSig_T_7 = _roundedSig_T_5 ? _roundedSig_T_6 : 26'h0; // @[RoundAnyRawFNToRecFN.scala:175:{25,64}, :177:35] wire [25:0] _roundedSig_T_8 = ~_roundedSig_T_7; // @[RoundAnyRawFNToRecFN.scala:175:{21,25}] wire [25:0] _roundedSig_T_9 = _roundedSig_T_2 & _roundedSig_T_8; // @[RoundAnyRawFNToRecFN.scala:174:{49,57}, :175:21] wire [26:0] _roundedSig_T_10 = ~roundMask; // @[RoundAnyRawFNToRecFN.scala:159:42, :180:32] wire [26:0] _roundedSig_T_11 = adjustedSig & _roundedSig_T_10; // @[RoundAnyRawFNToRecFN.scala:114:22, :180:{30,32}] wire [24:0] _roundedSig_T_12 = _roundedSig_T_11[26:2]; // @[RoundAnyRawFNToRecFN.scala:180:{30,43}] wire [25:0] _roundedSig_T_14 = roundPosMask[26:1]; // @[RoundAnyRawFNToRecFN.scala:163:46, :181:67] wire [25:0] _roundedSig_T_16 = {1'h0, _roundedSig_T_12}; // @[RoundAnyRawFNToRecFN.scala:180:{43,47}] wire [25:0] roundedSig = roundIncr ? _roundedSig_T_9 : _roundedSig_T_16; // @[RoundAnyRawFNToRecFN.scala:170:31, :173:16, :174:57, :180:47] wire [1:0] _sRoundedExp_T = roundedSig[25:24]; // @[RoundAnyRawFNToRecFN.scala:173:16, :185:54] wire [2:0] _sRoundedExp_T_1 = {1'h0, _sRoundedExp_T}; // @[RoundAnyRawFNToRecFN.scala:185:{54,76}] wire [10:0] sRoundedExp = {io_in_sExp_0[9], io_in_sExp_0} + {{8{_sRoundedExp_T_1[2]}}, _sRoundedExp_T_1}; // @[RoundAnyRawFNToRecFN.scala:48:5, :185:{40,76}] assign _common_expOut_T = sRoundedExp[8:0]; // @[RoundAnyRawFNToRecFN.scala:185:40, :187:37] assign common_expOut = _common_expOut_T; // @[RoundAnyRawFNToRecFN.scala:122:31, :187:37] wire [22:0] _common_fractOut_T = roundedSig[23:1]; // @[RoundAnyRawFNToRecFN.scala:173:16, :190:27] wire [22:0] _common_fractOut_T_1 = roundedSig[22:0]; // @[RoundAnyRawFNToRecFN.scala:173:16, :191:27] assign _common_fractOut_T_2 = doShiftSigDown1 ? _common_fractOut_T : _common_fractOut_T_1; // @[RoundAnyRawFNToRecFN.scala:120:57, :189:16, :190:27, :191:27] assign common_fractOut = _common_fractOut_T_2; // @[RoundAnyRawFNToRecFN.scala:123:31, :189:16] wire [3:0] _common_overflow_T = sRoundedExp[10:7]; // @[RoundAnyRawFNToRecFN.scala:185:40, :196:30] assign _common_overflow_T_1 = $signed(_common_overflow_T) > 4'sh2; // @[RoundAnyRawFNToRecFN.scala:196:{30,50}] assign common_overflow = _common_overflow_T_1; // @[RoundAnyRawFNToRecFN.scala:124:37, :196:50] assign _common_totalUnderflow_T = $signed(sRoundedExp) < 11'sh6B; // @[RoundAnyRawFNToRecFN.scala:185:40, :200:31] assign common_totalUnderflow = _common_totalUnderflow_T; // @[RoundAnyRawFNToRecFN.scala:125:37, :200:31] wire _unboundedRange_roundPosBit_T = adjustedSig[2]; // @[RoundAnyRawFNToRecFN.scala:114:22, :203:45] wire _unboundedRange_anyRound_T = adjustedSig[2]; // @[RoundAnyRawFNToRecFN.scala:114:22, :203:45, :205:44] wire _unboundedRange_roundPosBit_T_1 = adjustedSig[1]; // @[RoundAnyRawFNToRecFN.scala:114:22, :203:61] wire unboundedRange_roundPosBit = doShiftSigDown1 ? _unboundedRange_roundPosBit_T : _unboundedRange_roundPosBit_T_1; // @[RoundAnyRawFNToRecFN.scala:120:57, :203:{16,45,61}] wire _unboundedRange_roundIncr_T_1 = unboundedRange_roundPosBit; // @[RoundAnyRawFNToRecFN.scala:203:16, :207:67] wire _unboundedRange_anyRound_T_1 = doShiftSigDown1 & _unboundedRange_anyRound_T; // @[RoundAnyRawFNToRecFN.scala:120:57, :205:{30,44}] wire [1:0] _unboundedRange_anyRound_T_2 = adjustedSig[1:0]; // @[RoundAnyRawFNToRecFN.scala:114:22, :205:63] wire _unboundedRange_anyRound_T_3 = \|_unboundedRange_anyRound_T_2; // @[RoundAnyRawFNToRecFN.scala:205:{63,70}] wire unboundedRange_anyRound = _unboundedRange_anyRound_T_1 \| _unboundedRange_anyRound_T_3; // @[RoundAnyRawFNToRecFN.scala:205:{30,49,70}] wire unboundedRange_roundIncr = _unboundedRange_roundIncr_T_1; // @[RoundAnyRawFNToRecFN.scala:207:67, :208:46] wire _roundCarry_T = roundedSig[25]; // @[RoundAnyRawFNToRecFN.scala:173:16, :212:27] wire _roundCarry_T_1 = roundedSig[24]; // @[RoundAnyRawFNToRecFN.scala:173:16, :213:27] wire roundCarry = doShiftSigDown1 ? _roundCarry_T : _roundCarry_T_1; // @[RoundAnyRawFNToRecFN.scala:120:57, :211:16, :212:27, :213:27] wire [1:0] _common_underflow_T = io_in_sExp_0[9:8]; // @[RoundAnyRawFNToRecFN.scala:48:5, :220:49] wire _common_underflow_T_1 = _common_underflow_T != 2'h1; // @[RoundAnyRawFNToRecFN.scala:220:{49,64}] wire _common_underflow_T_2 = anyRound & _common_underflow_T_1; // @[RoundAnyRawFNToRecFN.scala:166:36, :220:{32,64}] wire _common_underflow_T_3 = roundMask[3]; // @[RoundAnyRawFNToRecFN.scala:159:42, :221:57] wire _common_underflow_T_9 = roundMask[3]; // @[RoundAnyRawFNToRecFN.scala:159:42, :221:57, :225:49] wire _common_underflow_T_4 = roundMask[2]; // @[RoundAnyRawFNToRecFN.scala:159:42, :221:71] wire _common_underflow_T_5 = doShiftSigDown1 ? _common_underflow_T_3 : _common_underflow_T_4; // @[RoundAnyRawFNToRecFN.scala:120:57, :221:{30,57,71}] wire _common_underflow_T_6 = _common_underflow_T_2 & _common_underflow_T_5; // @[RoundAnyRawFNToRecFN.scala:220:{32,72}, :221:30] wire _common_underflow_T_8 = roundMask[4]; // @[RoundAnyRawFNToRecFN.scala:159:42, :224:49] wire _common_underflow_T_10 = doShiftSigDown1 ? _common_underflow_T_8 : _common_underflow_T_9; // @[RoundAnyRawFNToRecFN.scala:120:57, :223:39, :224:49, :225:49] wire _common_underflow_T_11 = ~_common_underflow_T_10; // @[RoundAnyRawFNToRecFN.scala:223:{34,39}] wire _common_underflow_T_12 = _common_underflow_T_11; // @[RoundAnyRawFNToRecFN.scala:222:77, :223:34] wire _common_underflow_T_13 = _common_underflow_T_12 & roundCarry; // @[RoundAnyRawFNToRecFN.scala:211:16, :222:77, :226:38] wire _common_underflow_T_14 = _common_underflow_T_13 & roundPosBit; // @[RoundAnyRawFNToRecFN.scala:164:56, :226:38, :227:45] wire _common_underflow_T_15 = _common_underflow_T_14 & unboundedRange_roundIncr; // @[RoundAnyRawFNToRecFN.scala:208:46, :227:{45,60}] wire _common_underflow_T_16 = ~_common_underflow_T_15; // @[RoundAnyRawFNToRecFN.scala:222:27, :227:60] wire _common_underflow_T_17 = _common_underflow_T_6 & _common_underflow_T_16; // @[RoundAnyRawFNToRecFN.scala:220:72, :221:76, :222:27] assign _common_underflow_T_18 = common_totalUnderflow \| _common_underflow_T_17; // @[RoundAnyRawFNToRecFN.scala:125:37, :217:40, :221:76] assign common_underflow = _common_underflow_T_18; // @[RoundAnyRawFNToRecFN.scala:126:37, :217:40] assign _common_inexact_T = common_totalUnderflow \| anyRound; // @[RoundAnyRawFNToRecFN.scala:125:37, :166:36, :230:49] assign common_inexact = _common_inexact_T; // @[RoundAnyRawFNToRecFN.scala:127:37, :230:49] wire isNaNOut = io_invalidExc_0 \| io_in_isNaN_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :235:34] wire _commonCase_T = ~isNaNOut; // @[RoundAnyRawFNToRecFN.scala:235:34, :237:22] wire _commonCase_T_1 = ~notNaN_isSpecialInfOut; // @[RoundAnyRawFNToRecFN.scala:236:49, :237:36] wire _commonCase_T_2 = _commonCase_T & _commonCase_T_1; // @[RoundAnyRawFNToRecFN.scala:237:{22,33,36}] wire _commonCase_T_3 = ~io_in_isZero_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :237:64] wire commonCase = _commonCase_T_2 & _commonCase_T_3; // @[RoundAnyRawFNToRecFN.scala:237:{33,61,64}] wire overflow = commonCase & common_overflow; // @[RoundAnyRawFNToRecFN.scala:124:37, :237:61, :238:32] wire _notNaN_isInfOut_T = overflow; // @[RoundAnyRawFNToRecFN.scala:238:32, :248:45] wire underflow = commonCase & common_underflow; // @[RoundAnyRawFNToRecFN.scala:126:37, :237:61, :239:32] wire _inexact_T = commonCase & common_inexact; // @[RoundAnyRawFNToRecFN.scala:127:37, :237:61, :240:43] wire inexact = overflow \| _inexact_T; // @[RoundAnyRawFNToRecFN.scala:238:32, :240:{28,43}] wire _pegMinNonzeroMagOut_T = commonCase & common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:125:37, :237:61, :245:20] wire notNaN_isInfOut = notNaN_isSpecialInfOut \| _notNaN_isInfOut_T; // @[RoundAnyRawFNToRecFN.scala:236:49, :248:{32,45}] wire signOut = ~isNaNOut & io_in_sign_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :235:34, :250:22] wire _expOut_T = io_in_isZero_0 \| common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:48:5, :125:37, :253:32] wire [8:0] _expOut_T_1 = _expOut_T ? 9'h1C0 : 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:{18,32}] wire [8:0] _expOut_T_2 = ~_expOut_T_1; // @[RoundAnyRawFNToRecFN.scala:253:{14,18}] wire [8:0] _expOut_T_3 = common_expOut & _expOut_T_2; // @[RoundAnyRawFNToRecFN.scala:122:31, :252:24, :253:14] wire [8:0] _expOut_T_7 = _expOut_T_3; // @[RoundAnyRawFNToRecFN.scala:252:24, :256:17] wire [8:0] _expOut_T_10 = _expOut_T_7; // @[RoundAnyRawFNToRecFN.scala:256:17, :260:17] wire [8:0] _expOut_T_11 = {2'h0, notNaN_isInfOut, 6'h0}; // @[RoundAnyRawFNToRecFN.scala:248:32, :265:18] wire [8:0] _expOut_T_12 = ~_expOut_T_11; // @[RoundAnyRawFNToRecFN.scala:265:{14,18}] wire [8:0] _expOut_T_13 = _expOut_T_10 & _expOut_T_12; // @[RoundAnyRawFNToRecFN.scala:260:17, :264:17, :265:14] wire [8:0] _expOut_T_15 = _expOut_T_13; // @[RoundAnyRawFNToRecFN.scala:264:17, :268:18] wire [8:0] _expOut_T_17 = _expOut_T_15; // @[RoundAnyRawFNToRecFN.scala:268:18, :272:15] wire [8:0] _expOut_T_18 = notNaN_isInfOut ? 9'h180 : 9'h0; // @[RoundAnyRawFNToRecFN.scala:248:32, :277:16] wire [8:0] _expOut_T_19 = _expOut_T_17 \| _expOut_T_18; // @[RoundAnyRawFNToRecFN.scala:272:15, :276:15, :277:16] wire [8:0] _expOut_T_20 = isNaNOut ? 9'h1C0 : 9'h0; // @[RoundAnyRawFNToRecFN.scala:235:34, :278:16] wire [8:0] expOut = _expOut_T_19 \| _expOut_T_20; // @[RoundAnyRawFNToRecFN.scala:276:15, :277:73, :278:16] wire _fractOut_T = isNaNOut \| io_in_isZero_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :235:34, :280:22] wire _fractOut_T_1 = _fractOut_T \| common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:125:37, :280:{22,38}] wire [22:0] _fractOut_T_2 = {isNaNOut, 22'h0}; // @[RoundAnyRawFNToRecFN.scala:235:34, :281:16] wire [22:0] _fractOut_T_3 = _fractOut_T_1 ? _fractOut_T_2 : common_fractOut; // @[RoundAnyRawFNToRecFN.scala:123:31, :280:{12,38}, :281:16] wire [22:0] fractOut = _fractOut_T_3; // @[RoundAnyRawFNToRecFN.scala:280:12, :283:11] wire [9:0] _io_out_T = {signOut, expOut}; // @[RoundAnyRawFNToRecFN.scala:250:22, :277:73, :286:23] assign _io_out_T_1 = {_io_out_T, fractOut}; // @[RoundAnyRawFNToRecFN.scala:283:11, :286:{23,33}] assign io_out_0 = _io_out_T_1; // @[RoundAnyRawFNToRecFN.scala:48:5, :286:33] wire [1:0] _io_exceptionFlags_T = {io_invalidExc_0, 1'h0}; // @[RoundAnyRawFNToRecFN.scala:48:5, :288:23] wire [2:0] _io_exceptionFlags_T_1 = {_io_exceptionFlags_T, overflow}; // @[RoundAnyRawFNToRecFN.scala:238:32, :288:{23,41}] wire [3:0] _io_exceptionFlags_T_2 = {_io_exceptionFlags_T_1, underflow}; // @[RoundAnyRawFNToRecFN.scala:239:32, :288:{41,53}] assign _io_exceptionFlags_T_3 = {_io_exceptionFlags_T_2, inexact}; // @[RoundAnyRawFNToRecFN.scala:240:28, :288:{53,66}] assign io_exceptionFlags_0 = _io_exceptionFlags_T_3; // @[RoundAnyRawFNToRecFN.scala:48:5, :288:66] assign io_out = io_out_0; // @[RoundAnyRawFNToRecFN.scala:48:5] assign io_exceptionFlags = io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:48:5] endmodule
Generate the Verilog code corresponding to the following Chisel files. File Transposer.scala: package gemmini import chisel3._ import chisel3.util._ import Util._ trait Transposer[T <: Data] extends Module { def dim: Int def dataType: T val io = IO(new Bundle { val inRow = Flipped(Decoupled(Vec(dim, dataType))) val outCol = Decoupled(Vec(dim, dataType)) }) } class PipelinedTransposer[T <: Data](val dim: Int, val dataType: T) extends Transposer[T] { require(isPow2(dim)) val regArray = Seq.fill(dim, dim)(Reg(dataType)) val regArrayT = regArray.transpose val sMoveUp :: sMoveLeft :: Nil = Enum(2) val state = RegInit(sMoveUp) val leftCounter = RegInit(0.U(log2Ceil(dim+1).W)) //(io.inRow.fire && state === sMoveLeft, dim+1) val upCounter = RegInit(0.U(log2Ceil(dim+1).W)) //Counter(io.inRow.fire && state === sMoveUp, dim+1) io.outCol.valid := 0.U io.inRow.ready := 0.U switch(state) { is(sMoveUp) { io.inRow.ready := upCounter <= dim.U io.outCol.valid := leftCounter > 0.U when(io.inRow.fire) { upCounter := upCounter + 1.U } when(upCounter === (dim-1).U) { state := sMoveLeft leftCounter := 0.U } when(io.outCol.fire) { leftCounter := leftCounter - 1.U } } is(sMoveLeft) { io.inRow.ready := leftCounter <= dim.U // TODO: this is naive io.outCol.valid := upCounter > 0.U when(leftCounter === (dim-1).U) { state := sMoveUp } when(io.inRow.fire) { leftCounter := leftCounter + 1.U upCounter := 0.U } when(io.outCol.fire) { upCounter := upCounter - 1.U } } } // Propagate input from bottom row to top row systolically in the move up phase // TODO: need to iterate over columns to connect Chisel values of type T // Should be able to operate directly on the Vec, but Seq and Vec don't mix (try Array?) for (colIdx <- 0 until dim) { regArray.foldRight(io.inRow.bits(colIdx)) { case (regRow, prevReg) => when (state === sMoveUp) { regRow(colIdx) := prevReg } regRow(colIdx) } } // Propagate input from right side to left side systolically in the move left phase for (rowIdx <- 0 until dim) { regArrayT.foldRight(io.inRow.bits(rowIdx)) { case (regCol, prevReg) => when (state === sMoveLeft) { regCol(rowIdx) := prevReg } regCol(rowIdx) } } // Pull from the left side or the top side based on the state for (idx <- 0 until dim) { when (state === sMoveUp) { io.outCol.bits(idx) := regArray(0)(idx) }.elsewhen(state === sMoveLeft) { io.outCol.bits(idx) := regArrayT(0)(idx) }.otherwise { io.outCol.bits(idx) := DontCare } } } class AlwaysOutTransposer[T <: Data](val dim: Int, val dataType: T) extends Transposer[T] { require(isPow2(dim)) val LEFT_DIR = 0.U(1.W) val UP_DIR = 1.U(1.W) class PE extends Module { val io = IO(new Bundle { val inR = Input(dataType) val inD = Input(dataType) val outL = Output(dataType) val outU = Output(dataType) val dir = Input(UInt(1.W)) val en = Input(Bool()) }) val reg = RegEnable(Mux(io.dir === LEFT_DIR, io.inR, io.inD), io.en) io.outU := reg io.outL := reg } val pes = Seq.fill(dim,dim)(Module(new PE)) val counter = RegInit(0.U((log2Ceil(dim) max 1).W)) // TODO replace this with a standard Chisel counter val dir = RegInit(LEFT_DIR) // Wire up horizontal signals for (row <- 0 until dim; col <- 0 until dim) { val right_in = if (col == dim-1) io.inRow.bits(row) else pes(row)(col+1).io.outL pes(row)(col).io.inR := right_in } // Wire up vertical signals for (row <- 0 until dim; col <- 0 until dim) { val down_in = if (row == dim-1) io.inRow.bits(col) else pes(row+1)(col).io.outU pes(row)(col).io.inD := down_in } // Wire up global signals pes.flatten.foreach(_.io.dir := dir) pes.flatten.foreach(_.io.en := io.inRow.fire) io.outCol.valid := true.B io.inRow.ready := true.B val left_out = VecInit(pes.transpose.head.map(_.io.outL)) val up_out = VecInit(pes.head.map(_.io.outU)) io.outCol.bits := Mux(dir === LEFT_DIR, left_out, up_out) when (io.inRow.fire) { counter := wrappingAdd(counter, 1.U, dim) } when (counter === (dim-1).U && io.inRow.fire) { dir := ~dir } } class NaiveTransposer[T <: Data](val dim: Int, val dataType: T) extends Transposer[T] { val regArray = Seq.fill(dim, dim)(Reg(dataType)) val regArrayT = regArray.transpose // state = 0 => filling regArray row-wise, state = 1 => draining regArray column-wise val state = RegInit(0.U(1.W)) val countInc = io.inRow.fire \|\| io.outCol.fire val (countValue, countWrap) = Counter(countInc, dim) io.inRow.ready := state === 0.U io.outCol.valid := state === 1.U for (i <- 0 until dim) { for (j <- 0 until dim) { when(countValue === i.U && io.inRow.fire) { regArray(i)(j) := io.inRow.bits(j) } } } for (i <- 0 until dim) { io.outCol.bits(i) := 0.U for (j <- 0 until dim) { when(countValue === j.U) { io.outCol.bits(i) := regArrayT(j)(i) } } } when (io.inRow.fire && countWrap) { state := 1.U } when (io.outCol.fire && countWrap) { state := 0.U } assert(!(state === 0.U) \|\| !io.outCol.fire) assert(!(state === 1.U) \|\| !io.inRow.fire) }	module PE_233( // @[Transposer.scala:100:9] input clock, // @[Transposer.scala:100:9] input reset, // @[Transposer.scala:100:9] input [7:0] io_inR, // @[Transposer.scala:101:16] input [7:0] io_inD, // @[Transposer.scala:101:16] output [7:0] io_outL, // @[Transposer.scala:101:16] output [7:0] io_outU, // @[Transposer.scala:101:16] input io_dir, // @[Transposer.scala:101:16] input io_en // @[Transposer.scala:101:16] ); wire [7:0] io_inR_0 = io_inR; // @[Transposer.scala:100:9] wire [7:0] io_inD_0 = io_inD; // @[Transposer.scala:100:9] wire io_dir_0 = io_dir; // @[Transposer.scala:100:9] wire io_en_0 = io_en; // @[Transposer.scala:100:9] wire [7:0] io_outL_0; // @[Transposer.scala:100:9] wire [7:0] io_outU_0; // @[Transposer.scala:100:9] wire _reg_T = ~io_dir_0; // @[Transposer.scala:100:9, :110:36] wire [7:0] _reg_T_1 = _reg_T ? io_inR_0 : io_inD_0; // @[Transposer.scala:100:9, :110:{28,36}] reg [7:0] reg_0; // @[Transposer.scala:110:24] assign io_outL_0 = reg_0; // @[Transposer.scala:100:9, :110:24] assign io_outU_0 = reg_0; // @[Transposer.scala:100:9, :110:24] always @(posedge clock) begin // @[Transposer.scala:100:9] if (io_en_0) // @[Transposer.scala:100:9] reg_0 <= _reg_T_1; // @[Transposer.scala:110:{24,28}] always @(posedge) assign io_outL = io_outL_0; // @[Transposer.scala:100:9] assign io_outU = io_outU_0; // @[Transposer.scala:100:9] endmodule
Generate the Verilog code corresponding to the following Chisel files. File Buffer.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.diplomacy.BufferParams class TLBufferNode ( a: BufferParams, b: BufferParams, c: BufferParams, d: BufferParams, e: BufferParams)(implicit valName: ValName) extends TLAdapterNode( clientFn = { p => p.v1copy(minLatency = p.minLatency + b.latency + c.latency) }, managerFn = { p => p.v1copy(minLatency = p.minLatency + a.latency + d.latency) } ) { override lazy val nodedebugstring = s"a:${a.toString}, b:${b.toString}, c:${c.toString}, d:${d.toString}, e:${e.toString}" override def circuitIdentity = List(a,b,c,d,e).forall(_ == BufferParams.none) } class TLBuffer( a: BufferParams, b: BufferParams, c: BufferParams, d: BufferParams, e: BufferParams)(implicit p: Parameters) extends LazyModule { def this(ace: BufferParams, bd: BufferParams)(implicit p: Parameters) = this(ace, bd, ace, bd, ace) def this(abcde: BufferParams)(implicit p: Parameters) = this(abcde, abcde) def this()(implicit p: Parameters) = this(BufferParams.default) val node = new TLBufferNode(a, b, c, d, e) lazy val module = new Impl class Impl extends LazyModuleImp(this) { def headBundle = node.out.head._2.bundle override def desiredName = (Seq("TLBuffer") ++ node.out.headOption.map(_._2.bundle.shortName)).mkString("_") (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out.a <> a(in .a) in .d <> d(out.d) if (edgeOut.manager.anySupportAcquireB && edgeOut.client.anySupportProbe) { in .b <> b(out.b) out.c <> c(in .c) out.e <> e(in .e) } else { in.b.valid := false.B in.c.ready := true.B in.e.ready := true.B out.b.ready := true.B out.c.valid := false.B out.e.valid := false.B } } } } object TLBuffer { def apply() (implicit p: Parameters): TLNode = apply(BufferParams.default) def apply(abcde: BufferParams) (implicit p: Parameters): TLNode = apply(abcde, abcde) def apply(ace: BufferParams, bd: BufferParams)(implicit p: Parameters): TLNode = apply(ace, bd, ace, bd, ace) def apply( a: BufferParams, b: BufferParams, c: BufferParams, d: BufferParams, e: BufferParams)(implicit p: Parameters): TLNode = { val buffer = LazyModule(new TLBuffer(a, b, c, d, e)) buffer.node } def chain(depth: Int, name: Option[String] = None)(implicit p: Parameters): Seq[TLNode] = { val buffers = Seq.fill(depth) { LazyModule(new TLBuffer()) } name.foreach { n => buffers.zipWithIndex.foreach { case (b, i) => b.suggestName(s"${n}_${i}") } } buffers.map(_.node) } def chainNode(depth: Int, name: Option[String] = None)(implicit p: Parameters): TLNode = { chain(depth, name) .reduceLeftOption(_ := _) .getOrElse(TLNameNode("no_buffer")) } } File Nodes.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.nodes._ import freechips.rocketchip.util.{AsyncQueueParams,RationalDirection} case object TLMonitorBuilder extends Field[TLMonitorArgs => TLMonitorBase](args => new TLMonitor(args)) object TLImp extends NodeImp[TLMasterPortParameters, TLSlavePortParameters, TLEdgeOut, TLEdgeIn, TLBundle] { def edgeO(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeOut(pd, pu, p, sourceInfo) def edgeI(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeIn (pd, pu, p, sourceInfo) def bundleO(eo: TLEdgeOut) = TLBundle(eo.bundle) def bundleI(ei: TLEdgeIn) = TLBundle(ei.bundle) def render(ei: TLEdgeIn) = RenderedEdge(colour = "#000000" /* black /, label = (ei.manager.beatBytes 8).toString) override def monitor(bundle: TLBundle, edge: TLEdgeIn): Unit = { val monitor = Module(edge.params(TLMonitorBuilder)(TLMonitorArgs(edge))) monitor.io.in := bundle } override def mixO(pd: TLMasterPortParameters, node: OutwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLMasterPortParameters = pd.v1copy(clients = pd.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }) override def mixI(pu: TLSlavePortParameters, node: InwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLSlavePortParameters = pu.v1copy(managers = pu.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }) } trait TLFormatNode extends FormatNode[TLEdgeIn, TLEdgeOut] case class TLClientNode(portParams: Seq[TLMasterPortParameters])(implicit valName: ValName) extends SourceNode(TLImp)(portParams) with TLFormatNode case class TLManagerNode(portParams: Seq[TLSlavePortParameters])(implicit valName: ValName) extends SinkNode(TLImp)(portParams) with TLFormatNode case class TLAdapterNode( clientFn: TLMasterPortParameters => TLMasterPortParameters = { s => s }, managerFn: TLSlavePortParameters => TLSlavePortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLImp)(clientFn, managerFn) with TLFormatNode case class TLJunctionNode( clientFn: Seq[TLMasterPortParameters] => Seq[TLMasterPortParameters], managerFn: Seq[TLSlavePortParameters] => Seq[TLSlavePortParameters])( implicit valName: ValName) extends JunctionNode(TLImp)(clientFn, managerFn) with TLFormatNode case class TLIdentityNode()(implicit valName: ValName) extends IdentityNode(TLImp)() with TLFormatNode object TLNameNode { def apply(name: ValName) = TLIdentityNode()(name) def apply(name: Option[String]): TLIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLIdentityNode = apply(Some(name)) } case class TLEphemeralNode()(implicit valName: ValName) extends EphemeralNode(TLImp)() object TLTempNode { def apply(): TLEphemeralNode = TLEphemeralNode()(ValName("temp")) } case class TLNexusNode( clientFn: Seq[TLMasterPortParameters] => TLMasterPortParameters, managerFn: Seq[TLSlavePortParameters] => TLSlavePortParameters)( implicit valName: ValName) extends NexusNode(TLImp)(clientFn, managerFn) with TLFormatNode abstract class TLCustomNode(implicit valName: ValName) extends CustomNode(TLImp) with TLFormatNode // Asynchronous crossings trait TLAsyncFormatNode extends FormatNode[TLAsyncEdgeParameters, TLAsyncEdgeParameters] object TLAsyncImp extends SimpleNodeImp[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncEdgeParameters, TLAsyncBundle] { def edge(pd: TLAsyncClientPortParameters, pu: TLAsyncManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLAsyncEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLAsyncEdgeParameters) = new TLAsyncBundle(e.bundle) def render(e: TLAsyncEdgeParameters) = RenderedEdge(colour = "#ff0000" /* red /, label = e.manager.async.depth.toString) override def mixO(pd: TLAsyncClientPortParameters, node: OutwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLAsyncManagerPortParameters, node: InwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLAsyncAdapterNode( clientFn: TLAsyncClientPortParameters => TLAsyncClientPortParameters = { s => s }, managerFn: TLAsyncManagerPortParameters => TLAsyncManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLAsyncImp)(clientFn, managerFn) with TLAsyncFormatNode case class TLAsyncIdentityNode()(implicit valName: ValName) extends IdentityNode(TLAsyncImp)() with TLAsyncFormatNode object TLAsyncNameNode { def apply(name: ValName) = TLAsyncIdentityNode()(name) def apply(name: Option[String]): TLAsyncIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLAsyncIdentityNode = apply(Some(name)) } case class TLAsyncSourceNode(sync: Option[Int])(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLAsyncImp)( dFn = { p => TLAsyncClientPortParameters(p) }, uFn = { p => p.base.v1copy(minLatency = p.base.minLatency + sync.getOrElse(p.async.sync)) }) with FormatNode[TLEdgeIn, TLAsyncEdgeParameters] // discard cycles in other clock domain case class TLAsyncSinkNode(async: AsyncQueueParams)(implicit valName: ValName) extends MixedAdapterNode(TLAsyncImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = p.base.minLatency + async.sync) }, uFn = { p => TLAsyncManagerPortParameters(async, p) }) with FormatNode[TLAsyncEdgeParameters, TLEdgeOut] // Rationally related crossings trait TLRationalFormatNode extends FormatNode[TLRationalEdgeParameters, TLRationalEdgeParameters] object TLRationalImp extends SimpleNodeImp[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalEdgeParameters, TLRationalBundle] { def edge(pd: TLRationalClientPortParameters, pu: TLRationalManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLRationalEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLRationalEdgeParameters) = new TLRationalBundle(e.bundle) def render(e: TLRationalEdgeParameters) = RenderedEdge(colour = "#00ff00" / green /) override def mixO(pd: TLRationalClientPortParameters, node: OutwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLRationalManagerPortParameters, node: InwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLRationalAdapterNode( clientFn: TLRationalClientPortParameters => TLRationalClientPortParameters = { s => s }, managerFn: TLRationalManagerPortParameters => TLRationalManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLRationalImp)(clientFn, managerFn) with TLRationalFormatNode case class TLRationalIdentityNode()(implicit valName: ValName) extends IdentityNode(TLRationalImp)() with TLRationalFormatNode object TLRationalNameNode { def apply(name: ValName) = TLRationalIdentityNode()(name) def apply(name: Option[String]): TLRationalIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLRationalIdentityNode = apply(Some(name)) } case class TLRationalSourceNode()(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLRationalImp)( dFn = { p => TLRationalClientPortParameters(p) }, uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLRationalEdgeParameters] // discard cycles from other clock domain case class TLRationalSinkNode(direction: RationalDirection)(implicit valName: ValName) extends MixedAdapterNode(TLRationalImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = 1) }, uFn = { p => TLRationalManagerPortParameters(direction, p) }) with FormatNode[TLRationalEdgeParameters, TLEdgeOut] // Credited version of TileLink channels trait TLCreditedFormatNode extends FormatNode[TLCreditedEdgeParameters, TLCreditedEdgeParameters] object TLCreditedImp extends SimpleNodeImp[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedEdgeParameters, TLCreditedBundle] { def edge(pd: TLCreditedClientPortParameters, pu: TLCreditedManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLCreditedEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLCreditedEdgeParameters) = new TLCreditedBundle(e.bundle) def render(e: TLCreditedEdgeParameters) = RenderedEdge(colour = "#ffff00" / yellow /, e.delay.toString) override def mixO(pd: TLCreditedClientPortParameters, node: OutwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLCreditedManagerPortParameters, node: InwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLCreditedAdapterNode( clientFn: TLCreditedClientPortParameters => TLCreditedClientPortParameters = { s => s }, managerFn: TLCreditedManagerPortParameters => TLCreditedManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLCreditedImp)(clientFn, managerFn) with TLCreditedFormatNode case class TLCreditedIdentityNode()(implicit valName: ValName) extends IdentityNode(TLCreditedImp)() with TLCreditedFormatNode object TLCreditedNameNode { def apply(name: ValName) = TLCreditedIdentityNode()(name) def apply(name: Option[String]): TLCreditedIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLCreditedIdentityNode = apply(Some(name)) } case class TLCreditedSourceNode(delay: TLCreditedDelay)(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLCreditedImp)( dFn = { p => TLCreditedClientPortParameters(delay, p) }, uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLCreditedEdgeParameters] // discard cycles from other clock domain case class TLCreditedSinkNode(delay: TLCreditedDelay)(implicit valName: ValName) extends MixedAdapterNode(TLCreditedImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = 1) }, uFn = { p => TLCreditedManagerPortParameters(delay, p) }) with FormatNode[TLCreditedEdgeParameters, TLEdgeOut] File LazyModuleImp.scala: package org.chipsalliance.diplomacy.lazymodule import chisel3.{withClockAndReset, Module, RawModule, Reset, _} import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo} import firrtl.passes.InlineAnnotation import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.nodes.Dangle import scala.collection.immutable.SortedMap /* Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]]. * * This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy. / sealed trait LazyModuleImpLike extends RawModule { /* [[LazyModule]] that contains this instance. / val wrapper: LazyModule /* IOs that will be automatically "punched" for this instance. / val auto: AutoBundle /* The metadata that describes the [[HalfEdge]]s which generated [[auto]]. / protected[diplomacy] val dangles: Seq[Dangle] // [[wrapper.module]] had better not be accessed while LazyModules are still being built! require( LazyModule.scope.isEmpty, s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}" ) /* Set module name. Defaults to the containing LazyModule's desiredName. / override def desiredName: String = wrapper.desiredName suggestName(wrapper.suggestedName) /* [[Parameters]] for chisel [[Module]]s. / implicit val p: Parameters = wrapper.p /* instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and * submodules. / protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = { // 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]], // 2. return [[Dangle]]s from each module. val childDangles = wrapper.children.reverse.flatMap { c => implicit val sourceInfo: SourceInfo = c.info c.cloneProto.map { cp => // If the child is a clone, then recursively set cloneProto of its children as well def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = { require(bases.size == clones.size) (bases.zip(clones)).map { case (l, r) => require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}") l.cloneProto = Some(r) assignCloneProtos(l.children, r.children) } } assignCloneProtos(c.children, cp.children) // Clone the child module as a record, and get its [[AutoBundle]] val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName) val clonedAuto = clone("auto").asInstanceOf[AutoBundle] // Get the empty [[Dangle]]'s of the cloned child val rawDangles = c.cloneDangles() require(rawDangles.size == clonedAuto.elements.size) // Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) } dangles }.getOrElse { // For non-clones, instantiate the child module val mod = try { Module(c.module) } catch { case e: ChiselException => { println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}") throw e } } mod.dangles } } // Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]]. // This will result in a sequence of [[Dangle]] from these [[BaseNode]]s. val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate()) // Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]] val allDangles = nodeDangles ++ childDangles // Group [[allDangles]] by their [[source]]. val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _) // For each [[source]] set of [[Dangle]]s of size 2, ensure that these // can be connected as a source-sink pair (have opposite flipped value). // Make the connection and mark them as [[done]]. val done = Set() ++ pairing.values.filter(_.size == 2).map { case Seq(a, b) => require(a.flipped != b.flipped) // @todo <> in chisel3 makes directionless connection. if (a.flipped) { a.data <> b.data } else { b.data <> a.data } a.source case _ => None } // Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module. val forward = allDangles.filter(d => !done(d.source)) // Generate [[AutoBundle]] IO from [[forward]]. val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _)) // Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]] val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) => if (d.flipped) { d.data <> io } else { io <> d.data } d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name) } // Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]]. wrapper.inModuleBody.reverse.foreach { _() } if (wrapper.shouldBeInlined) { chisel3.experimental.annotate(new ChiselAnnotation { def toFirrtl = InlineAnnotation(toNamed) }) } // Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]]. (auto, dangles) } } /* Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. / class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike { /* Instantiate hardware of this `Module`. / val (auto, dangles) = instantiate() } /* Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. / class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike { // These wires are the default clock+reset for all LazyModule children. // It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the // [[LazyRawModuleImp]] children. // Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly. /* drive clock explicitly. / val childClock: Clock = Wire(Clock()) /* drive reset explicitly. / val childReset: Reset = Wire(Reset()) // the default is that these are disabled childClock := false.B.asClock childReset := chisel3.DontCare def provideImplicitClockToLazyChildren: Boolean = false val (auto, dangles) = if (provideImplicitClockToLazyChildren) { withClockAndReset(childClock, childReset) { instantiate() } } else { instantiate() } } File MixedNode.scala: package org.chipsalliance.diplomacy.nodes import chisel3.{Data, DontCare, Wire} import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.{Field, Parameters} import org.chipsalliance.diplomacy.ValName import org.chipsalliance.diplomacy.sourceLine /* One side metadata of a [[Dangle]]. * * Describes one side of an edge going into or out of a [[BaseNode]]. * * @param serial * the global [[BaseNode.serial]] number of the [[BaseNode]] that this [[HalfEdge]] connects to. * @param index * the `index` in the [[BaseNode]]'s input or output port list that this [[HalfEdge]] belongs to. / case class HalfEdge(serial: Int, index: Int) extends Ordered[HalfEdge] { import scala.math.Ordered.orderingToOrdered def compare(that: HalfEdge): Int = HalfEdge.unapply(this).compare(HalfEdge.unapply(that)) } /* [[Dangle]] captures the `IO` information of a [[LazyModule]] and which two [[BaseNode]]s the [[Edges]]/[[Bundle]] * connects. * * [[Dangle]]s are generated by [[BaseNode.instantiate]] using [[MixedNode.danglesOut]] and [[MixedNode.danglesIn]] , * [[LazyModuleImp.instantiate]] connects those that go to internal or explicit IO connections in a [[LazyModule]]. * * @param source * the source [[HalfEdge]] of this [[Dangle]], which captures the source [[BaseNode]] and the port `index` within * that [[BaseNode]]. * @param sink * sink [[HalfEdge]] of this [[Dangle]], which captures the sink [[BaseNode]] and the port `index` within that * [[BaseNode]]. * @param flipped * flip or not in [[AutoBundle.makeElements]]. If true this corresponds to `danglesOut`, if false it corresponds to * `danglesIn`. * @param dataOpt * actual [[Data]] for the hardware connection. Can be empty if this belongs to a cloned module / case class Dangle(source: HalfEdge, sink: HalfEdge, flipped: Boolean, name: String, dataOpt: Option[Data]) { def data = dataOpt.get } /* [[Edges]] is a collection of parameters describing the functionality and connection for an interface, which is often * derived from the interconnection protocol and can inform the parameterization of the hardware bundles that actually * implement the protocol. / case class Edges[EI, EO](in: Seq[EI], out: Seq[EO]) /* A field available in [[Parameters]] used to determine whether [[InwardNodeImp.monitor]] will be called. / case object MonitorsEnabled extends Field[Boolean](true) /* When rendering the edge in a graphical format, flip the order in which the edges' source and sink are presented. * * For example, when rendering graphML, yEd by default tries to put the source node vertically above the sink node, but * [[RenderFlipped]] inverts this relationship. When a particular [[LazyModule]] contains both source nodes and sink * nodes, flipping the rendering of one node's edge will usual produce a more concise visual layout for the * [[LazyModule]]. / case object RenderFlipped extends Field[Boolean](false) /* The sealed node class in the package, all node are derived from it. * * @param inner * Sink interface implementation. * @param outer * Source interface implementation. * @param valName * val name of this node. * @tparam DI * Downward-flowing parameters received on the inner side of the node. It is usually a brunch of parameters * describing the protocol parameters from a source. For an [[InwardNode]], it is determined by the connected * [[OutwardNode]]. Since it can be connected to multiple sources, this parameter is always a Seq of source port * parameters. * @tparam UI * Upward-flowing parameters generated by the inner side of the node. It is usually a brunch of parameters describing * the protocol parameters of a sink. For an [[InwardNode]], it is determined itself. * @tparam EI * Edge Parameters describing a connection on the inner side of the node. It is usually a brunch of transfers * specified for a sink according to protocol. * @tparam BI * Bundle type used when connecting to the inner side of the node. It is a hardware interface of this sink interface. * It should extends from [[chisel3.Data]], which represents the real hardware. * @tparam DO * Downward-flowing parameters generated on the outer side of the node. It is usually a brunch of parameters * describing the protocol parameters of a source. For an [[OutwardNode]], it is determined itself. * @tparam UO * Upward-flowing parameters received by the outer side of the node. It is usually a brunch of parameters describing * the protocol parameters from a sink. For an [[OutwardNode]], it is determined by the connected [[InwardNode]]. * Since it can be connected to multiple sinks, this parameter is always a Seq of sink port parameters. * @tparam EO * Edge Parameters describing a connection on the outer side of the node. It is usually a brunch of transfers * specified for a source according to protocol. * @tparam BO * Bundle type used when connecting to the outer side of the node. It is a hardware interface of this source * interface. It should extends from [[chisel3.Data]], which represents the real hardware. * * @note * Call Graph of [[MixedNode]] * - line `─`: source is process by a function and generate pass to others * - Arrow `→`: target of arrow is generated by source * * {{{ * (from the other node) * ┌─────────────────────────────────────────────────────────[[InwardNode.uiParams]]─────────────┐ * ↓ │ * (binding node when elaboration) [[OutwardNode.uoParams]]────────────────────────[[MixedNode.mapParamsU]]→──────────┐ │ * [[InwardNode.accPI]] │ │ │ * │ │ (based on protocol) │ * │ │ [[MixedNode.inner.edgeI]] │ * │ │ ↓ │ * ↓ │ │ │ * (immobilize after elaboration) (inward port from [[OutwardNode]]) │ ↓ │ * [[InwardNode.iBindings]]──┐ [[MixedNode.iDirectPorts]]────────────────────→[[MixedNode.iPorts]] [[InwardNode.uiParams]] │ * │ │ ↑ │ │ │ * │ │ │ [[OutwardNode.doParams]] │ │ * │ │ │ (from the other node) │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * │ │ │ └────────┬──────────────┤ │ * │ │ │ │ │ │ * │ │ │ │ (based on protocol) │ * │ │ │ │ [[MixedNode.inner.edgeI]] │ * │ │ │ │ │ │ * │ │ (from the other node) │ ↓ │ * │ └───[[OutwardNode.oPortMapping]] [[OutwardNode.oStar]] │ [[MixedNode.edgesIn]]───┐ │ * │ ↑ ↑ │ │ ↓ │ * │ │ │ │ │ [[MixedNode.in]] │ * │ │ │ │ ↓ ↑ │ * │ (solve star connection) │ │ │ [[MixedNode.bundleIn]]──┘ │ * ├───[[MixedNode.resolveStar]]→─┼─────────────────────────────┤ └────────────────────────────────────┐ │ * │ │ │ [[MixedNode.bundleOut]]─┐ │ │ * │ │ │ ↑ ↓ │ │ * │ │ │ │ [[MixedNode.out]] │ │ * │ ↓ ↓ │ ↑ │ │ * │ ┌─────[[InwardNode.iPortMapping]] [[InwardNode.iStar]] [[MixedNode.edgesOut]]──┘ │ │ * │ │ (from the other node) ↑ │ │ * │ │ │ │ │ │ * │ │ │ [[MixedNode.outer.edgeO]] │ │ * │ │ │ (based on protocol) │ │ * │ │ │ │ │ │ * │ │ │ ┌────────────────────────────────────────┤ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * (immobilize after elaboration)│ ↓ │ │ │ │ * [[OutwardNode.oBindings]]─┘ [[MixedNode.oDirectPorts]]───→[[MixedNode.oPorts]] [[OutwardNode.doParams]] │ │ * ↑ (inward port from [[OutwardNode]]) │ │ │ │ * │ ┌─────────────────────────────────────────┤ │ │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * [[OutwardNode.accPO]] │ ↓ │ │ │ * (binding node when elaboration) │ [[InwardNode.diParams]]─────→[[MixedNode.mapParamsD]]────────────────────────────┘ │ │ * │ ↑ │ │ * │ └──────────────────────────────────────────────────────────────────────────────────────────┘ │ * └──────────────────────────────────────────────────────────────────────────────────────────────────────────┘ * }}} / abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data]( val inner: InwardNodeImp[DI, UI, EI, BI], val outer: OutwardNodeImp[DO, UO, EO, BO] )( implicit valName: ValName) extends BaseNode with NodeHandle[DI, UI, EI, BI, DO, UO, EO, BO] with InwardNode[DI, UI, BI] with OutwardNode[DO, UO, BO] { // Generate a [[NodeHandle]] with inward and outward node are both this node. val inward = this val outward = this /* Debug info of nodes binding. / def bindingInfo: String = s"""$iBindingInfo \|$oBindingInfo \|""".stripMargin /* Debug info of ports connecting. / def connectedPortsInfo: String = s"""${oPorts.size} outward ports connected: [${oPorts.map(_._2.name).mkString(",")}] \|${iPorts.size} inward ports connected: [${iPorts.map(_._2.name).mkString(",")}] \|""".stripMargin /* Debug info of parameters propagations. / def parametersInfo: String = s"""${doParams.size} downstream outward parameters: [${doParams.mkString(",")}] \|${uoParams.size} upstream outward parameters: [${uoParams.mkString(",")}] \|${diParams.size} downstream inward parameters: [${diParams.mkString(",")}] \|${uiParams.size} upstream inward parameters: [${uiParams.mkString(",")}] \|""".stripMargin /* For a given node, converts [[OutwardNode.accPO]] and [[InwardNode.accPI]] to [[MixedNode.oPortMapping]] and * [[MixedNode.iPortMapping]]. * * Given counts of known inward and outward binding and inward and outward star bindings, return the resolved inward * stars and outward stars. * * This method will also validate the arguments and throw a runtime error if the values are unsuitable for this type * of node. * * @param iKnown * Number of known-size ([[BIND_ONCE]]) input bindings. * @param oKnown * Number of known-size ([[BIND_ONCE]]) output bindings. * @param iStar * Number of unknown size ([[BIND_STAR]]) input bindings. * @param oStar * Number of unknown size ([[BIND_STAR]]) output bindings. * @return * A Tuple of the resolved number of input and output connections. / protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStar: Int, oStar: Int): (Int, Int) /* Function to generate downward-flowing outward params from the downward-flowing input params and the current output * ports. * * @param n * The size of the output sequence to generate. * @param p * Sequence of downward-flowing input parameters of this node. * @return * A `n`-sized sequence of downward-flowing output edge parameters. / protected[diplomacy] def mapParamsD(n: Int, p: Seq[DI]): Seq[DO] /* Function to generate upward-flowing input parameters from the upward-flowing output parameters [[uiParams]]. * * @param n * Size of the output sequence. * @param p * Upward-flowing output edge parameters. * @return * A n-sized sequence of upward-flowing input edge parameters. / protected[diplomacy] def mapParamsU(n: Int, p: Seq[UO]): Seq[UI] /* @return * The sink cardinality of the node, the number of outputs bound with [[BIND_QUERY]] summed with inputs bound with * [[BIND_STAR]]. / protected[diplomacy] lazy val sinkCard: Int = oBindings.count(_._3 == BIND_QUERY) + iBindings.count(_._3 == BIND_STAR) /* @return * The source cardinality of this node, the number of inputs bound with [[BIND_QUERY]] summed with the number of * output bindings bound with [[BIND_STAR]]. / protected[diplomacy] lazy val sourceCard: Int = iBindings.count(_._3 == BIND_QUERY) + oBindings.count(_._3 == BIND_STAR) /* @return list of nodes involved in flex bindings with this node. / protected[diplomacy] lazy val flexes: Seq[BaseNode] = oBindings.filter(_._3 == BIND_FLEX).map(_._2) ++ iBindings.filter(_._3 == BIND_FLEX).map(_._2) /* Resolves the flex to be either source or sink and returns the offset where the [[BIND_STAR]] operators begin * greedily taking up the remaining connections. * * @return * A value >= 0 if it is sink cardinality, a negative value for source cardinality. The magnitude of the return * value is not relevant. / protected[diplomacy] lazy val flexOffset: Int = { /* Recursively performs a depth-first search of the [[flexes]], [[BaseNode]]s connected to this node with flex * operators. The algorithm bottoms out when we either get to a node we have already visited or when we get to a * connection that is not a flex and can set the direction for us. Otherwise, recurse by visiting the `flexes` of * each node in the current set and decide whether they should be added to the set or not. * * @return * the mapping of [[BaseNode]] indexed by their serial numbers. / def DFS(v: BaseNode, visited: Map[Int, BaseNode]): Map[Int, BaseNode] = { if (visited.contains(v.serial) \|\| !v.flexibleArityDirection) { visited } else { v.flexes.foldLeft(visited + (v.serial -> v))((sum, n) => DFS(n, sum)) } } /* Determine which [[BaseNode]] are involved in resolving the flex connections to/from this node. * * @example * {{{ * a := b := c * d := b * e := f * }}} * * `flexSet` for `a`, `b`, `c`, or `d` will be `Set(a, b, c, d)` `flexSet` for `e` or `f` will be `Set(e,f)` / val flexSet = DFS(this, Map()).values /* The total number of := operators where we're on the left. / val allSink = flexSet.map(_.sinkCard).sum /** The total number of :=* operators used when we're on the right. / val allSource = flexSet.map(_.sourceCard).sum require( allSink == 0 \|\| allSource == 0, s"The nodes ${flexSet.map(_.name)} which are inter-connected by :=* have ${allSink} := operators and ${allSource} := operators connected to them, making it impossible to determine cardinality inference direction." ) allSink - allSource } /** @return A value >= 0 if it is sink cardinality, a negative value for source cardinality. / protected[diplomacy] def edgeArityDirection(n: BaseNode): Int = { if (flexibleArityDirection) flexOffset else if (n.flexibleArityDirection) n.flexOffset else 0 } /* For a node which is connected between two nodes, select the one that will influence the direction of the flex * resolution. / protected[diplomacy] def edgeAritySelect(n: BaseNode, l: => Int, r: => Int): Int = { val dir = edgeArityDirection(n) if (dir < 0) l else if (dir > 0) r else 1 } /* Ensure that the same node is not visited twice in resolving `:=`, etc operators. / private var starCycleGuard = false /** Resolve all the star operators into concrete indicies. As connections are being made, some may be "star" * connections which need to be resolved. In some way to determine how many actual edges they correspond to. We also * need to build up the ranges of edges which correspond to each binding operator, so that We can apply the correct * edge parameters and later build up correct bundle connections. * * [[oPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that oPort (binding * operator). [[iPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that iPort * (binding operator). [[oStar]]: `Int` the value to return for this node `N` for any `N := foo` or `N :=* foo := bar` [[iStar]]: `Int` the value to return for this node `N` for any `foo :=* N` or `bar :=* foo := N` / protected[diplomacy] lazy val ( oPortMapping: Seq[(Int, Int)], iPortMapping: Seq[(Int, Int)], oStar: Int, iStar: Int ) = { try { if (starCycleGuard) throw StarCycleException() starCycleGuard = true // For a given node N... // Number of foo := N // + Number of bar :=* foo := N val oStars = oBindings.count { case (_, n, b, _, _) => b == BIND_STAR \|\| (b == BIND_FLEX && edgeArityDirection(n) < 0) } // Number of N := foo // + Number of N :=* foo := bar val iStars = iBindings.count { case (_, n, b, _, _) => b == BIND_STAR \|\| (b == BIND_FLEX && edgeArityDirection(n) > 0) } // 1 for foo := N // + bar.iStar for bar := foo := N // + foo.iStar for foo := N // + 0 for foo := N val oKnown = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, 0, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => 0 } }.sum // 1 for N := foo // + bar.oStar for N := foo :=* bar // + foo.oStar for N :=* foo // + 0 for N := foo val iKnown = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, 0) case BIND_QUERY => n.oStar case BIND_STAR => 0 } }.sum // Resolve star depends on the node subclass to implement the algorithm for this. val (iStar, oStar) = resolveStar(iKnown, oKnown, iStars, oStars) // Cumulative list of resolved outward binding range starting points val oSum = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, oStar, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => oStar } }.scanLeft(0)(_ + _) // Cumulative list of resolved inward binding range starting points val iSum = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, iStar) case BIND_QUERY => n.oStar case BIND_STAR => iStar } }.scanLeft(0)(_ + _) // Create ranges for each binding based on the running sums and return // those along with resolved values for the star operations. (oSum.init.zip(oSum.tail), iSum.init.zip(iSum.tail), oStar, iStar) } catch { case c: StarCycleException => throw c.copy(loop = context +: c.loop) } } /* Sequence of inward ports. * * This should be called after all star bindings are resolved. * * Each element is: `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. * `n` Instance of inward node. `p` View of [[Parameters]] where this connection was made. `s` Source info where this * connection was made in the source code. / protected[diplomacy] lazy val oDirectPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oBindings.flatMap { case (i, n, _, p, s) => // for each binding operator in this node, look at what it connects to val (start, end) = n.iPortMapping(i) (start until end).map { j => (j, n, p, s) } } /* Sequence of outward ports. * * This should be called after all star bindings are resolved. * * `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. `n` Instance of * outward node. `p` View of [[Parameters]] where this connection was made. `s` [[SourceInfo]] where this connection * was made in the source code. / protected[diplomacy] lazy val iDirectPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iBindings.flatMap { case (i, n, _, p, s) => // query this port index range of this node in the other side of node. val (start, end) = n.oPortMapping(i) (start until end).map { j => (j, n, p, s) } } // Ephemeral nodes ( which have non-None iForward/oForward) have in_degree = out_degree // Thus, there must exist an Eulerian path and the below algorithms terminate @scala.annotation.tailrec private def oTrace( tuple: (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) ): (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.iForward(i) match { case None => (i, n, p, s) case Some((j, m)) => oTrace((j, m, p, s)) } } @scala.annotation.tailrec private def iTrace( tuple: (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) ): (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.oForward(i) match { case None => (i, n, p, s) case Some((j, m)) => iTrace((j, m, p, s)) } } /* Final output ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - Numeric index of this binding in the [[InwardNode]] on the other end. * - [[InwardNode]] on the other end of this binding. * - A view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. / lazy val oPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oDirectPorts.map(oTrace) /* Final input ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - numeric index of this binding in [[OutwardNode]] on the other end. * - [[OutwardNode]] on the other end of this binding. * - a view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. / lazy val iPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iDirectPorts.map(iTrace) private var oParamsCycleGuard = false protected[diplomacy] lazy val diParams: Seq[DI] = iPorts.map { case (i, n, _, _) => n.doParams(i) } protected[diplomacy] lazy val doParams: Seq[DO] = { try { if (oParamsCycleGuard) throw DownwardCycleException() oParamsCycleGuard = true val o = mapParamsD(oPorts.size, diParams) require( o.size == oPorts.size, s"""Diplomacy has detected a problem with your graph: \|At the following node, the number of outward ports should equal the number of produced outward parameters. \|$context \|$connectedPortsInfo \|Downstreamed inward parameters: [${diParams.mkString(",")}] \|Produced outward parameters: [${o.mkString(",")}] \|""".stripMargin ) o.map(outer.mixO(_, this)) } catch { case c: DownwardCycleException => throw c.copy(loop = context +: c.loop) } } private var iParamsCycleGuard = false protected[diplomacy] lazy val uoParams: Seq[UO] = oPorts.map { case (o, n, _, _) => n.uiParams(o) } protected[diplomacy] lazy val uiParams: Seq[UI] = { try { if (iParamsCycleGuard) throw UpwardCycleException() iParamsCycleGuard = true val i = mapParamsU(iPorts.size, uoParams) require( i.size == iPorts.size, s"""Diplomacy has detected a problem with your graph: \|At the following node, the number of inward ports should equal the number of produced inward parameters. \|$context \|$connectedPortsInfo \|Upstreamed outward parameters: [${uoParams.mkString(",")}] \|Produced inward parameters: [${i.mkString(",")}] \|""".stripMargin ) i.map(inner.mixI(_, this)) } catch { case c: UpwardCycleException => throw c.copy(loop = context +: c.loop) } } /* Outward edge parameters. / protected[diplomacy] lazy val edgesOut: Seq[EO] = (oPorts.zip(doParams)).map { case ((i, n, p, s), o) => outer.edgeO(o, n.uiParams(i), p, s) } /* Inward edge parameters. / protected[diplomacy] lazy val edgesIn: Seq[EI] = (iPorts.zip(uiParams)).map { case ((o, n, p, s), i) => inner.edgeI(n.doParams(o), i, p, s) } /* A tuple of the input edge parameters and output edge parameters for the edges bound to this node. * * If you need to access to the edges of a foreign Node, use this method (in/out create bundles). / lazy val edges: Edges[EI, EO] = Edges(edgesIn, edgesOut) /* Create actual Wires corresponding to the Bundles parameterized by the outward edges of this node. / protected[diplomacy] lazy val bundleOut: Seq[BO] = edgesOut.map { e => val x = Wire(outer.bundleO(e)).suggestName(s"${valName.value}Out") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } /* Create actual Wires corresponding to the Bundles parameterized by the inward edges of this node. / protected[diplomacy] lazy val bundleIn: Seq[BI] = edgesIn.map { e => val x = Wire(inner.bundleI(e)).suggestName(s"${valName.value}In") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } private def emptyDanglesOut: Seq[Dangle] = oPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(serial, i), sink = HalfEdge(n.serial, j), flipped = false, name = wirePrefix + "out", dataOpt = None ) } private def emptyDanglesIn: Seq[Dangle] = iPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(n.serial, j), sink = HalfEdge(serial, i), flipped = true, name = wirePrefix + "in", dataOpt = None ) } /* Create the [[Dangle]]s which describe the connections from this node output to other nodes inputs. / protected[diplomacy] def danglesOut: Seq[Dangle] = emptyDanglesOut.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleOut(i))) } /* Create the [[Dangle]]s which describe the connections from this node input from other nodes outputs. / protected[diplomacy] def danglesIn: Seq[Dangle] = emptyDanglesIn.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleIn(i))) } private[diplomacy] var instantiated = false /* Gather Bundle and edge parameters of outward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. / def out: Seq[(BO, EO)] = { require( instantiated, s"$name.out should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleOut.zip(edgesOut) } /* Gather Bundle and edge parameters of inward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. / def in: Seq[(BI, EI)] = { require( instantiated, s"$name.in should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleIn.zip(edgesIn) } /* Actually instantiate this node during [[LazyModuleImp]] evaluation. Mark that it's safe to use the Bundle wires, * instantiate monitors on all input ports if appropriate, and return all the dangles of this node. / protected[diplomacy] def instantiate(): Seq[Dangle] = { instantiated = true if (!circuitIdentity) { (iPorts.zip(in)).foreach { case ((_, _, p, _), (b, e)) => if (p(MonitorsEnabled)) inner.monitor(b, e) } } danglesOut ++ danglesIn } protected[diplomacy] def cloneDangles(): Seq[Dangle] = emptyDanglesOut ++ emptyDanglesIn /* Connects the outward part of a node with the inward part of this node. / protected[diplomacy] def bind( h: OutwardNode[DI, UI, BI], binding: NodeBinding )( implicit p: Parameters, sourceInfo: SourceInfo ): Unit = { val x = this // x := y val y = h sourceLine(sourceInfo, " at ", "") val i = x.iPushed val o = y.oPushed y.oPush( i, x, binding match { case BIND_ONCE => BIND_ONCE case BIND_FLEX => BIND_FLEX case BIND_STAR => BIND_QUERY case BIND_QUERY => BIND_STAR } ) x.iPush(o, y, binding) } / Metadata for printing the node graph. / def inputs: Seq[(OutwardNode[DI, UI, BI], RenderedEdge)] = (iPorts.zip(edgesIn)).map { case ((_, n, p, _), e) => val re = inner.render(e) (n, re.copy(flipped = re.flipped != p(RenderFlipped))) } /* Metadata for printing the node graph */ def outputs: Seq[(InwardNode[DO, UO, BO], RenderedEdge)] = oPorts.map { case (i, n, _, _) => (n, n.inputs(i)._2) } }	module TLBuffer_a32d128s2k4z4c_1( // @[Buffer.scala:40:9] input clock, // @[Buffer.scala:40:9] input reset, // @[Buffer.scala:40:9] output auto_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [1:0] auto_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [15:0] auto_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [127:0] auto_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_in_b_ready, // @[LazyModuleImp.scala:107:25] output auto_in_b_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_b_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_b_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_in_b_bits_size, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_b_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_in_b_bits_address, // @[LazyModuleImp.scala:107:25] output [15:0] auto_in_b_bits_mask, // @[LazyModuleImp.scala:107:25] output [127:0] auto_in_b_bits_data, // @[LazyModuleImp.scala:107:25] output auto_in_b_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_in_c_ready, // @[LazyModuleImp.scala:107:25] input auto_in_c_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_c_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_c_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_in_c_bits_size, // @[LazyModuleImp.scala:107:25] input [1:0] auto_in_c_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_in_c_bits_address, // @[LazyModuleImp.scala:107:25] input [127:0] auto_in_c_bits_data, // @[LazyModuleImp.scala:107:25] input auto_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_d_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output [3:0] auto_in_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [127:0] auto_in_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_in_e_ready, // @[LazyModuleImp.scala:107:25] input auto_in_e_valid, // @[LazyModuleImp.scala:107:25] input [3:0] auto_in_e_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [1:0] auto_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [15:0] auto_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [127:0] auto_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_out_b_ready, // @[LazyModuleImp.scala:107:25] input auto_out_b_valid, // @[LazyModuleImp.scala:107:25] input [1:0] auto_out_b_bits_param, // @[LazyModuleImp.scala:107:25] input [1:0] auto_out_b_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_out_b_bits_address, // @[LazyModuleImp.scala:107:25] input auto_out_c_ready, // @[LazyModuleImp.scala:107:25] output auto_out_c_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_c_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_c_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_c_bits_size, // @[LazyModuleImp.scala:107:25] output [1:0] auto_out_c_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_out_c_bits_address, // @[LazyModuleImp.scala:107:25] output [127:0] auto_out_c_bits_data, // @[LazyModuleImp.scala:107:25] output auto_out_c_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_out_d_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [1:0] auto_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input [3:0] auto_out_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_out_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [127:0] auto_out_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_out_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_out_e_ready, // @[LazyModuleImp.scala:107:25] output auto_out_e_valid, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_e_bits_sink // @[LazyModuleImp.scala:107:25] ); wire auto_in_a_valid_0 = auto_in_a_valid; // @[Buffer.scala:40:9] wire [2:0] auto_in_a_bits_opcode_0 = auto_in_a_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] auto_in_a_bits_param_0 = auto_in_a_bits_param; // @[Buffer.scala:40:9] wire [3:0] auto_in_a_bits_size_0 = auto_in_a_bits_size; // @[Buffer.scala:40:9] wire [1:0] auto_in_a_bits_source_0 = auto_in_a_bits_source; // @[Buffer.scala:40:9] wire [31:0] auto_in_a_bits_address_0 = auto_in_a_bits_address; // @[Buffer.scala:40:9] wire [15:0] auto_in_a_bits_mask_0 = auto_in_a_bits_mask; // @[Buffer.scala:40:9] wire [127:0] auto_in_a_bits_data_0 = auto_in_a_bits_data; // @[Buffer.scala:40:9] wire auto_in_b_ready_0 = auto_in_b_ready; // @[Buffer.scala:40:9] wire auto_in_c_valid_0 = auto_in_c_valid; // @[Buffer.scala:40:9] wire [2:0] auto_in_c_bits_opcode_0 = auto_in_c_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] auto_in_c_bits_param_0 = auto_in_c_bits_param; // @[Buffer.scala:40:9] wire [3:0] auto_in_c_bits_size_0 = auto_in_c_bits_size; // @[Buffer.scala:40:9] wire [1:0] auto_in_c_bits_source_0 = auto_in_c_bits_source; // @[Buffer.scala:40:9] wire [31:0] auto_in_c_bits_address_0 = auto_in_c_bits_address; // @[Buffer.scala:40:9] wire [127:0] auto_in_c_bits_data_0 = auto_in_c_bits_data; // @[Buffer.scala:40:9] wire auto_in_d_ready_0 = auto_in_d_ready; // @[Buffer.scala:40:9] wire auto_in_e_valid_0 = auto_in_e_valid; // @[Buffer.scala:40:9] wire [3:0] auto_in_e_bits_sink_0 = auto_in_e_bits_sink; // @[Buffer.scala:40:9] wire auto_out_a_ready_0 = auto_out_a_ready; // @[Buffer.scala:40:9] wire auto_out_b_valid_0 = auto_out_b_valid; // @[Buffer.scala:40:9] wire [1:0] auto_out_b_bits_param_0 = auto_out_b_bits_param; // @[Buffer.scala:40:9] wire [1:0] auto_out_b_bits_source_0 = auto_out_b_bits_source; // @[Buffer.scala:40:9] wire [31:0] auto_out_b_bits_address_0 = auto_out_b_bits_address; // @[Buffer.scala:40:9] wire auto_out_c_ready_0 = auto_out_c_ready; // @[Buffer.scala:40:9] wire auto_out_d_valid_0 = auto_out_d_valid; // @[Buffer.scala:40:9] wire [2:0] auto_out_d_bits_opcode_0 = auto_out_d_bits_opcode; // @[Buffer.scala:40:9] wire [1:0] auto_out_d_bits_param_0 = auto_out_d_bits_param; // @[Buffer.scala:40:9] wire [3:0] auto_out_d_bits_size_0 = auto_out_d_bits_size; // @[Buffer.scala:40:9] wire [1:0] auto_out_d_bits_source_0 = auto_out_d_bits_source; // @[Buffer.scala:40:9] wire [3:0] auto_out_d_bits_sink_0 = auto_out_d_bits_sink; // @[Buffer.scala:40:9] wire auto_out_d_bits_denied_0 = auto_out_d_bits_denied; // @[Buffer.scala:40:9] wire [127:0] auto_out_d_bits_data_0 = auto_out_d_bits_data; // @[Buffer.scala:40:9] wire auto_out_d_bits_corrupt_0 = auto_out_d_bits_corrupt; // @[Buffer.scala:40:9] wire auto_out_e_ready_0 = auto_out_e_ready; // @[Buffer.scala:40:9] wire [127:0] auto_out_b_bits_data = 128'h0; // @[Decoupled.scala:362:21] wire [127:0] nodeOut_b_bits_data = 128'h0; // @[Decoupled.scala:362:21] wire [15:0] auto_out_b_bits_mask = 16'hFFFF; // @[Decoupled.scala:362:21] wire [15:0] nodeOut_b_bits_mask = 16'hFFFF; // @[Decoupled.scala:362:21] wire [3:0] auto_out_b_bits_size = 4'h6; // @[Decoupled.scala:362:21] wire [3:0] nodeOut_b_bits_size = 4'h6; // @[Decoupled.scala:362:21] wire [2:0] auto_out_b_bits_opcode = 3'h6; // @[Decoupled.scala:362:21] wire [2:0] nodeOut_b_bits_opcode = 3'h6; // @[Decoupled.scala:362:21] wire auto_in_a_bits_corrupt = 1'h0; // @[Decoupled.scala:362:21] wire auto_in_c_bits_corrupt = 1'h0; // @[Decoupled.scala:362:21] wire auto_out_b_bits_corrupt = 1'h0; // @[Decoupled.scala:362:21] wire nodeIn_a_ready; // @[MixedNode.scala:551:17] wire nodeIn_a_bits_corrupt = 1'h0; // @[Decoupled.scala:362:21] wire nodeIn_c_bits_corrupt = 1'h0; // @[Decoupled.scala:362:21] wire nodeOut_b_bits_corrupt = 1'h0; // @[Decoupled.scala:362:21] wire nodeIn_a_valid = auto_in_a_valid_0; // @[Buffer.scala:40:9] wire [2:0] nodeIn_a_bits_opcode = auto_in_a_bits_opcode_0; // @[Buffer.scala:40:9] wire [2:0] nodeIn_a_bits_param = auto_in_a_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] nodeIn_a_bits_size = auto_in_a_bits_size_0; // @[Buffer.scala:40:9] wire [1:0] nodeIn_a_bits_source = auto_in_a_bits_source_0; // @[Buffer.scala:40:9] wire [31:0] nodeIn_a_bits_address = auto_in_a_bits_address_0; // @[Buffer.scala:40:9] wire [15:0] nodeIn_a_bits_mask = auto_in_a_bits_mask_0; // @[Buffer.scala:40:9] wire [127:0] nodeIn_a_bits_data = auto_in_a_bits_data_0; // @[Buffer.scala:40:9] wire nodeIn_b_ready = auto_in_b_ready_0; // @[Buffer.scala:40:9] wire nodeIn_b_valid; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_b_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] nodeIn_b_bits_param; // @[MixedNode.scala:551:17] wire [3:0] nodeIn_b_bits_size; // @[MixedNode.scala:551:17] wire [1:0] nodeIn_b_bits_source; // @[MixedNode.scala:551:17] wire [31:0] nodeIn_b_bits_address; // @[MixedNode.scala:551:17] wire [15:0] nodeIn_b_bits_mask; // @[MixedNode.scala:551:17] wire [127:0] nodeIn_b_bits_data; // @[MixedNode.scala:551:17] wire nodeIn_b_bits_corrupt; // @[MixedNode.scala:551:17] wire nodeIn_c_ready; // @[MixedNode.scala:551:17] wire nodeIn_c_valid = auto_in_c_valid_0; // @[Buffer.scala:40:9] wire [2:0] nodeIn_c_bits_opcode = auto_in_c_bits_opcode_0; // @[Buffer.scala:40:9] wire [2:0] nodeIn_c_bits_param = auto_in_c_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] nodeIn_c_bits_size = auto_in_c_bits_size_0; // @[Buffer.scala:40:9] wire [1:0] nodeIn_c_bits_source = auto_in_c_bits_source_0; // @[Buffer.scala:40:9] wire [31:0] nodeIn_c_bits_address = auto_in_c_bits_address_0; // @[Buffer.scala:40:9] wire [127:0] nodeIn_c_bits_data = auto_in_c_bits_data_0; // @[Buffer.scala:40:9] wire nodeIn_d_ready = auto_in_d_ready_0; // @[Buffer.scala:40:9] wire nodeIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] nodeIn_d_bits_param; // @[MixedNode.scala:551:17] wire [3:0] nodeIn_d_bits_size; // @[MixedNode.scala:551:17] wire [1:0] nodeIn_d_bits_source; // @[MixedNode.scala:551:17] wire [3:0] nodeIn_d_bits_sink; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_denied; // @[MixedNode.scala:551:17] wire [127:0] nodeIn_d_bits_data; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_corrupt; // @[MixedNode.scala:551:17] wire nodeIn_e_ready; // @[MixedNode.scala:551:17] wire nodeIn_e_valid = auto_in_e_valid_0; // @[Buffer.scala:40:9] wire [3:0] nodeIn_e_bits_sink = auto_in_e_bits_sink_0; // @[Buffer.scala:40:9] wire nodeOut_a_ready = auto_out_a_ready_0; // @[Buffer.scala:40:9] wire nodeOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_a_bits_param; // @[MixedNode.scala:542:17] wire [3:0] nodeOut_a_bits_size; // @[MixedNode.scala:542:17] wire [1:0] nodeOut_a_bits_source; // @[MixedNode.scala:542:17] wire [31:0] nodeOut_a_bits_address; // @[MixedNode.scala:542:17] wire [15:0] nodeOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [127:0] nodeOut_a_bits_data; // @[MixedNode.scala:542:17] wire nodeOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire nodeOut_b_ready; // @[MixedNode.scala:542:17] wire nodeOut_b_valid = auto_out_b_valid_0; // @[Buffer.scala:40:9] wire [1:0] nodeOut_b_bits_param = auto_out_b_bits_param_0; // @[Buffer.scala:40:9] wire [1:0] nodeOut_b_bits_source = auto_out_b_bits_source_0; // @[Buffer.scala:40:9] wire [31:0] nodeOut_b_bits_address = auto_out_b_bits_address_0; // @[Buffer.scala:40:9] wire nodeOut_c_ready = auto_out_c_ready_0; // @[Buffer.scala:40:9] wire nodeOut_c_valid; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_c_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_c_bits_param; // @[MixedNode.scala:542:17] wire [3:0] nodeOut_c_bits_size; // @[MixedNode.scala:542:17] wire [1:0] nodeOut_c_bits_source; // @[MixedNode.scala:542:17] wire [31:0] nodeOut_c_bits_address; // @[MixedNode.scala:542:17] wire [127:0] nodeOut_c_bits_data; // @[MixedNode.scala:542:17] wire nodeOut_c_bits_corrupt; // @[MixedNode.scala:542:17] wire nodeOut_d_ready; // @[MixedNode.scala:542:17] wire nodeOut_d_valid = auto_out_d_valid_0; // @[Buffer.scala:40:9] wire [2:0] nodeOut_d_bits_opcode = auto_out_d_bits_opcode_0; // @[Buffer.scala:40:9] wire [1:0] nodeOut_d_bits_param = auto_out_d_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] nodeOut_d_bits_size = auto_out_d_bits_size_0; // @[Buffer.scala:40:9] wire [1:0] nodeOut_d_bits_source = auto_out_d_bits_source_0; // @[Buffer.scala:40:9] wire [3:0] nodeOut_d_bits_sink = auto_out_d_bits_sink_0; // @[Buffer.scala:40:9] wire nodeOut_d_bits_denied = auto_out_d_bits_denied_0; // @[Buffer.scala:40:9] wire [127:0] nodeOut_d_bits_data = auto_out_d_bits_data_0; // @[Buffer.scala:40:9] wire nodeOut_d_bits_corrupt = auto_out_d_bits_corrupt_0; // @[Buffer.scala:40:9] wire nodeOut_e_ready = auto_out_e_ready_0; // @[Buffer.scala:40:9] wire nodeOut_e_valid; // @[MixedNode.scala:542:17] wire [3:0] nodeOut_e_bits_sink; // @[MixedNode.scala:542:17] wire auto_in_a_ready_0; // @[Buffer.scala:40:9] wire [2:0] auto_in_b_bits_opcode_0; // @[Buffer.scala:40:9] wire [1:0] auto_in_b_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] auto_in_b_bits_size_0; // @[Buffer.scala:40:9] wire [1:0] auto_in_b_bits_source_0; // @[Buffer.scala:40:9] wire [31:0] auto_in_b_bits_address_0; // @[Buffer.scala:40:9] wire [15:0] auto_in_b_bits_mask_0; // @[Buffer.scala:40:9] wire [127:0] auto_in_b_bits_data_0; // @[Buffer.scala:40:9] wire auto_in_b_bits_corrupt_0; // @[Buffer.scala:40:9] wire auto_in_b_valid_0; // @[Buffer.scala:40:9] wire auto_in_c_ready_0; // @[Buffer.scala:40:9] wire [2:0] auto_in_d_bits_opcode_0; // @[Buffer.scala:40:9] wire [1:0] auto_in_d_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] auto_in_d_bits_size_0; // @[Buffer.scala:40:9] wire [1:0] auto_in_d_bits_source_0; // @[Buffer.scala:40:9] wire [3:0] auto_in_d_bits_sink_0; // @[Buffer.scala:40:9] wire auto_in_d_bits_denied_0; // @[Buffer.scala:40:9] wire [127:0] auto_in_d_bits_data_0; // @[Buffer.scala:40:9] wire auto_in_d_bits_corrupt_0; // @[Buffer.scala:40:9] wire auto_in_d_valid_0; // @[Buffer.scala:40:9] wire auto_in_e_ready_0; // @[Buffer.scala:40:9] wire [2:0] auto_out_a_bits_opcode_0; // @[Buffer.scala:40:9] wire [2:0] auto_out_a_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] auto_out_a_bits_size_0; // @[Buffer.scala:40:9] wire [1:0] auto_out_a_bits_source_0; // @[Buffer.scala:40:9] wire [31:0] auto_out_a_bits_address_0; // @[Buffer.scala:40:9] wire [15:0] auto_out_a_bits_mask_0; // @[Buffer.scala:40:9] wire [127:0] auto_out_a_bits_data_0; // @[Buffer.scala:40:9] wire auto_out_a_bits_corrupt_0; // @[Buffer.scala:40:9] wire auto_out_a_valid_0; // @[Buffer.scala:40:9] wire auto_out_b_ready_0; // @[Buffer.scala:40:9] wire [2:0] auto_out_c_bits_opcode_0; // @[Buffer.scala:40:9] wire [2:0] auto_out_c_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] auto_out_c_bits_size_0; // @[Buffer.scala:40:9] wire [1:0] auto_out_c_bits_source_0; // @[Buffer.scala:40:9] wire [31:0] auto_out_c_bits_address_0; // @[Buffer.scala:40:9] wire [127:0] auto_out_c_bits_data_0; // @[Buffer.scala:40:9] wire auto_out_c_bits_corrupt_0; // @[Buffer.scala:40:9] wire auto_out_c_valid_0; // @[Buffer.scala:40:9] wire auto_out_d_ready_0; // @[Buffer.scala:40:9] wire [3:0] auto_out_e_bits_sink_0; // @[Buffer.scala:40:9] wire auto_out_e_valid_0; // @[Buffer.scala:40:9] assign auto_in_a_ready_0 = nodeIn_a_ready; // @[Buffer.scala:40:9] assign auto_in_b_valid_0 = nodeIn_b_valid; // @[Buffer.scala:40:9] assign auto_in_b_bits_opcode_0 = nodeIn_b_bits_opcode; // @[Buffer.scala:40:9] assign auto_in_b_bits_param_0 = nodeIn_b_bits_param; // @[Buffer.scala:40:9] assign auto_in_b_bits_size_0 = nodeIn_b_bits_size; // @[Buffer.scala:40:9] assign auto_in_b_bits_source_0 = nodeIn_b_bits_source; // @[Buffer.scala:40:9] assign auto_in_b_bits_address_0 = nodeIn_b_bits_address; // @[Buffer.scala:40:9] assign auto_in_b_bits_mask_0 = nodeIn_b_bits_mask; // @[Buffer.scala:40:9] assign auto_in_b_bits_data_0 = nodeIn_b_bits_data; // @[Buffer.scala:40:9] assign auto_in_b_bits_corrupt_0 = nodeIn_b_bits_corrupt; // @[Buffer.scala:40:9] assign auto_in_c_ready_0 = nodeIn_c_ready; // @[Buffer.scala:40:9] assign auto_in_d_valid_0 = nodeIn_d_valid; // @[Buffer.scala:40:9] assign auto_in_d_bits_opcode_0 = nodeIn_d_bits_opcode; // @[Buffer.scala:40:9] assign auto_in_d_bits_param_0 = nodeIn_d_bits_param; // @[Buffer.scala:40:9] assign auto_in_d_bits_size_0 = nodeIn_d_bits_size; // @[Buffer.scala:40:9] assign auto_in_d_bits_source_0 = nodeIn_d_bits_source; // @[Buffer.scala:40:9] assign auto_in_d_bits_sink_0 = nodeIn_d_bits_sink; // @[Buffer.scala:40:9] assign auto_in_d_bits_denied_0 = nodeIn_d_bits_denied; // @[Buffer.scala:40:9] assign auto_in_d_bits_data_0 = nodeIn_d_bits_data; // @[Buffer.scala:40:9] assign auto_in_d_bits_corrupt_0 = nodeIn_d_bits_corrupt; // @[Buffer.scala:40:9] assign auto_in_e_ready_0 = nodeIn_e_ready; // @[Buffer.scala:40:9] assign auto_out_a_valid_0 = nodeOut_a_valid; // @[Buffer.scala:40:9] assign auto_out_a_bits_opcode_0 = nodeOut_a_bits_opcode; // @[Buffer.scala:40:9] assign auto_out_a_bits_param_0 = nodeOut_a_bits_param; // @[Buffer.scala:40:9] assign auto_out_a_bits_size_0 = nodeOut_a_bits_size; // @[Buffer.scala:40:9] assign auto_out_a_bits_source_0 = nodeOut_a_bits_source; // @[Buffer.scala:40:9] assign auto_out_a_bits_address_0 = nodeOut_a_bits_address; // @[Buffer.scala:40:9] assign auto_out_a_bits_mask_0 = nodeOut_a_bits_mask; // @[Buffer.scala:40:9] assign auto_out_a_bits_data_0 = nodeOut_a_bits_data; // @[Buffer.scala:40:9] assign auto_out_a_bits_corrupt_0 = nodeOut_a_bits_corrupt; // @[Buffer.scala:40:9] assign auto_out_b_ready_0 = nodeOut_b_ready; // @[Buffer.scala:40:9] assign auto_out_c_valid_0 = nodeOut_c_valid; // @[Buffer.scala:40:9] assign auto_out_c_bits_opcode_0 = nodeOut_c_bits_opcode; // @[Buffer.scala:40:9] assign auto_out_c_bits_param_0 = nodeOut_c_bits_param; // @[Buffer.scala:40:9] assign auto_out_c_bits_size_0 = nodeOut_c_bits_size; // @[Buffer.scala:40:9] assign auto_out_c_bits_source_0 = nodeOut_c_bits_source; // @[Buffer.scala:40:9] assign auto_out_c_bits_address_0 = nodeOut_c_bits_address; // @[Buffer.scala:40:9] assign auto_out_c_bits_data_0 = nodeOut_c_bits_data; // @[Buffer.scala:40:9] assign auto_out_c_bits_corrupt_0 = nodeOut_c_bits_corrupt; // @[Buffer.scala:40:9] assign auto_out_d_ready_0 = nodeOut_d_ready; // @[Buffer.scala:40:9] assign auto_out_e_valid_0 = nodeOut_e_valid; // @[Buffer.scala:40:9] assign auto_out_e_bits_sink_0 = nodeOut_e_bits_sink; // @[Buffer.scala:40:9] TLMonitor_45 monitor ( // @[Nodes.scala:27:25] .clock (clock), .reset (reset), .io_in_a_ready (nodeIn_a_ready), // @[MixedNode.scala:551:17] .io_in_a_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17] .io_in_a_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17] .io_in_a_bits_param (nodeIn_a_bits_param), // @[MixedNode.scala:551:17] .io_in_a_bits_size (nodeIn_a_bits_size), // @[MixedNode.scala:551:17] .io_in_a_bits_source (nodeIn_a_bits_source), // @[MixedNode.scala:551:17] .io_in_a_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17] .io_in_a_bits_mask (nodeIn_a_bits_mask), // @[MixedNode.scala:551:17] .io_in_a_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17] .io_in_b_ready (nodeIn_b_ready), // @[MixedNode.scala:551:17] .io_in_b_valid (nodeIn_b_valid), // @[MixedNode.scala:551:17] .io_in_b_bits_opcode (nodeIn_b_bits_opcode), // @[MixedNode.scala:551:17] .io_in_b_bits_param (nodeIn_b_bits_param), // @[MixedNode.scala:551:17] .io_in_b_bits_size (nodeIn_b_bits_size), // @[MixedNode.scala:551:17] .io_in_b_bits_source (nodeIn_b_bits_source), // @[MixedNode.scala:551:17] .io_in_b_bits_address (nodeIn_b_bits_address), // @[MixedNode.scala:551:17] .io_in_b_bits_mask (nodeIn_b_bits_mask), // @[MixedNode.scala:551:17] .io_in_b_bits_data (nodeIn_b_bits_data), // @[MixedNode.scala:551:17] .io_in_b_bits_corrupt (nodeIn_b_bits_corrupt), // @[MixedNode.scala:551:17] .io_in_c_ready (nodeIn_c_ready), // @[MixedNode.scala:551:17] .io_in_c_valid (nodeIn_c_valid), // @[MixedNode.scala:551:17] .io_in_c_bits_opcode (nodeIn_c_bits_opcode), // @[MixedNode.scala:551:17] .io_in_c_bits_param (nodeIn_c_bits_param), // @[MixedNode.scala:551:17] .io_in_c_bits_size (nodeIn_c_bits_size), // @[MixedNode.scala:551:17] .io_in_c_bits_source (nodeIn_c_bits_source), // @[MixedNode.scala:551:17] .io_in_c_bits_address (nodeIn_c_bits_address), // @[MixedNode.scala:551:17] .io_in_c_bits_data (nodeIn_c_bits_data), // @[MixedNode.scala:551:17] .io_in_d_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17] .io_in_d_valid (nodeIn_d_valid), // @[MixedNode.scala:551:17] .io_in_d_bits_opcode (nodeIn_d_bits_opcode), // @[MixedNode.scala:551:17] .io_in_d_bits_param (nodeIn_d_bits_param), // @[MixedNode.scala:551:17] .io_in_d_bits_size (nodeIn_d_bits_size), // @[MixedNode.scala:551:17] .io_in_d_bits_source (nodeIn_d_bits_source), // @[MixedNode.scala:551:17] .io_in_d_bits_sink (nodeIn_d_bits_sink), // @[MixedNode.scala:551:17] .io_in_d_bits_denied (nodeIn_d_bits_denied), // @[MixedNode.scala:551:17] .io_in_d_bits_data (nodeIn_d_bits_data), // @[MixedNode.scala:551:17] .io_in_d_bits_corrupt (nodeIn_d_bits_corrupt), // @[MixedNode.scala:551:17] .io_in_e_ready (nodeIn_e_ready), // @[MixedNode.scala:551:17] .io_in_e_valid (nodeIn_e_valid), // @[MixedNode.scala:551:17] .io_in_e_bits_sink (nodeIn_e_bits_sink) // @[MixedNode.scala:551:17] ); // @[Nodes.scala:27:25] Queue2_TLBundleA_a32d128s2k4z4c nodeOut_a_q ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (nodeIn_a_ready), .io_enq_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17] .io_enq_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17] .io_enq_bits_param (nodeIn_a_bits_param), // @[MixedNode.scala:551:17] .io_enq_bits_size (nodeIn_a_bits_size), // @[MixedNode.scala:551:17] .io_enq_bits_source (nodeIn_a_bits_source), // @[MixedNode.scala:551:17] .io_enq_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17] .io_enq_bits_mask (nodeIn_a_bits_mask), // @[MixedNode.scala:551:17] .io_enq_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17] .io_deq_ready (nodeOut_a_ready), // @[MixedNode.scala:542:17] .io_deq_valid (nodeOut_a_valid), .io_deq_bits_opcode (nodeOut_a_bits_opcode), .io_deq_bits_param (nodeOut_a_bits_param), .io_deq_bits_size (nodeOut_a_bits_size), .io_deq_bits_source (nodeOut_a_bits_source), .io_deq_bits_address (nodeOut_a_bits_address), .io_deq_bits_mask (nodeOut_a_bits_mask), .io_deq_bits_data (nodeOut_a_bits_data), .io_deq_bits_corrupt (nodeOut_a_bits_corrupt) ); // @[Decoupled.scala:362:21] Queue2_TLBundleD_a32d128s2k4z4c nodeIn_d_q ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (nodeOut_d_ready), .io_enq_valid (nodeOut_d_valid), // @[MixedNode.scala:542:17] .io_enq_bits_opcode (nodeOut_d_bits_opcode), // @[MixedNode.scala:542:17] .io_enq_bits_param (nodeOut_d_bits_param), // @[MixedNode.scala:542:17] .io_enq_bits_size (nodeOut_d_bits_size), // @[MixedNode.scala:542:17] .io_enq_bits_source (nodeOut_d_bits_source), // @[MixedNode.scala:542:17] .io_enq_bits_sink (nodeOut_d_bits_sink), // @[MixedNode.scala:542:17] .io_enq_bits_denied (nodeOut_d_bits_denied), // @[MixedNode.scala:542:17] .io_enq_bits_data (nodeOut_d_bits_data), // @[MixedNode.scala:542:17] .io_enq_bits_corrupt (nodeOut_d_bits_corrupt), // @[MixedNode.scala:542:17] .io_deq_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17] .io_deq_valid (nodeIn_d_valid), .io_deq_bits_opcode (nodeIn_d_bits_opcode), .io_deq_bits_param (nodeIn_d_bits_param), .io_deq_bits_size (nodeIn_d_bits_size), .io_deq_bits_source (nodeIn_d_bits_source), .io_deq_bits_sink (nodeIn_d_bits_sink), .io_deq_bits_denied (nodeIn_d_bits_denied), .io_deq_bits_data (nodeIn_d_bits_data), .io_deq_bits_corrupt (nodeIn_d_bits_corrupt) ); // @[Decoupled.scala:362:21] Queue2_TLBundleB_a32d128s2k4z4c nodeIn_b_q ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (nodeOut_b_ready), .io_enq_valid (nodeOut_b_valid), // @[MixedNode.scala:542:17] .io_enq_bits_param (nodeOut_b_bits_param), // @[MixedNode.scala:542:17] .io_enq_bits_source (nodeOut_b_bits_source), // @[MixedNode.scala:542:17] .io_enq_bits_address (nodeOut_b_bits_address), // @[MixedNode.scala:542:17] .io_deq_ready (nodeIn_b_ready), // @[MixedNode.scala:551:17] .io_deq_valid (nodeIn_b_valid), .io_deq_bits_opcode (nodeIn_b_bits_opcode), .io_deq_bits_param (nodeIn_b_bits_param), .io_deq_bits_size (nodeIn_b_bits_size), .io_deq_bits_source (nodeIn_b_bits_source), .io_deq_bits_address (nodeIn_b_bits_address), .io_deq_bits_mask (nodeIn_b_bits_mask), .io_deq_bits_data (nodeIn_b_bits_data), .io_deq_bits_corrupt (nodeIn_b_bits_corrupt) ); // @[Decoupled.scala:362:21] Queue2_TLBundleC_a32d128s2k4z4c nodeOut_c_q ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (nodeIn_c_ready), .io_enq_valid (nodeIn_c_valid), // @[MixedNode.scala:551:17] .io_enq_bits_opcode (nodeIn_c_bits_opcode), // @[MixedNode.scala:551:17] .io_enq_bits_param (nodeIn_c_bits_param), // @[MixedNode.scala:551:17] .io_enq_bits_size (nodeIn_c_bits_size), // @[MixedNode.scala:551:17] .io_enq_bits_source (nodeIn_c_bits_source), // @[MixedNode.scala:551:17] .io_enq_bits_address (nodeIn_c_bits_address), // @[MixedNode.scala:551:17] .io_enq_bits_data (nodeIn_c_bits_data), // @[MixedNode.scala:551:17] .io_deq_ready (nodeOut_c_ready), // @[MixedNode.scala:542:17] .io_deq_valid (nodeOut_c_valid), .io_deq_bits_opcode (nodeOut_c_bits_opcode), .io_deq_bits_param (nodeOut_c_bits_param), .io_deq_bits_size (nodeOut_c_bits_size), .io_deq_bits_source (nodeOut_c_bits_source), .io_deq_bits_address (nodeOut_c_bits_address), .io_deq_bits_data (nodeOut_c_bits_data), .io_deq_bits_corrupt (nodeOut_c_bits_corrupt) ); // @[Decoupled.scala:362:21] Queue2_TLBundleE_a32d128s2k4z4c nodeOut_e_q ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (nodeIn_e_ready), .io_enq_valid (nodeIn_e_valid), // @[MixedNode.scala:551:17] .io_enq_bits_sink (nodeIn_e_bits_sink), // @[MixedNode.scala:551:17] .io_deq_ready (nodeOut_e_ready), // @[MixedNode.scala:542:17] .io_deq_valid (nodeOut_e_valid), .io_deq_bits_sink (nodeOut_e_bits_sink) ); // @[Decoupled.scala:362:21] assign auto_in_a_ready = auto_in_a_ready_0; // @[Buffer.scala:40:9] assign auto_in_b_valid = auto_in_b_valid_0; // @[Buffer.scala:40:9] assign auto_in_b_bits_opcode = auto_in_b_bits_opcode_0; // @[Buffer.scala:40:9] assign auto_in_b_bits_param = auto_in_b_bits_param_0; // @[Buffer.scala:40:9] assign auto_in_b_bits_size = auto_in_b_bits_size_0; // @[Buffer.scala:40:9] assign auto_in_b_bits_source = auto_in_b_bits_source_0; // @[Buffer.scala:40:9] assign auto_in_b_bits_address = auto_in_b_bits_address_0; // @[Buffer.scala:40:9] assign auto_in_b_bits_mask = auto_in_b_bits_mask_0; // @[Buffer.scala:40:9] assign auto_in_b_bits_data = auto_in_b_bits_data_0; // @[Buffer.scala:40:9] assign auto_in_b_bits_corrupt = auto_in_b_bits_corrupt_0; // @[Buffer.scala:40:9] assign auto_in_c_ready = auto_in_c_ready_0; // @[Buffer.scala:40:9] assign auto_in_d_valid = auto_in_d_valid_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_opcode = auto_in_d_bits_opcode_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_param = auto_in_d_bits_param_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_size = auto_in_d_bits_size_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_source = auto_in_d_bits_source_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_sink = auto_in_d_bits_sink_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_denied = auto_in_d_bits_denied_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_data = auto_in_d_bits_data_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_corrupt = auto_in_d_bits_corrupt_0; // @[Buffer.scala:40:9] assign auto_in_e_ready = auto_in_e_ready_0; // @[Buffer.scala:40:9] assign auto_out_a_valid = auto_out_a_valid_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_opcode = auto_out_a_bits_opcode_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_param = auto_out_a_bits_param_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_size = auto_out_a_bits_size_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_source = auto_out_a_bits_source_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_address = auto_out_a_bits_address_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_mask = auto_out_a_bits_mask_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_data = auto_out_a_bits_data_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_corrupt = auto_out_a_bits_corrupt_0; // @[Buffer.scala:40:9] assign auto_out_b_ready = auto_out_b_ready_0; // @[Buffer.scala:40:9] assign auto_out_c_valid = auto_out_c_valid_0; // @[Buffer.scala:40:9] assign auto_out_c_bits_opcode = auto_out_c_bits_opcode_0; // @[Buffer.scala:40:9] assign auto_out_c_bits_param = auto_out_c_bits_param_0; // @[Buffer.scala:40:9] assign auto_out_c_bits_size = auto_out_c_bits_size_0; // @[Buffer.scala:40:9] assign auto_out_c_bits_source = auto_out_c_bits_source_0; // @[Buffer.scala:40:9] assign auto_out_c_bits_address = auto_out_c_bits_address_0; // @[Buffer.scala:40:9] assign auto_out_c_bits_data = auto_out_c_bits_data_0; // @[Buffer.scala:40:9] assign auto_out_c_bits_corrupt = auto_out_c_bits_corrupt_0; // @[Buffer.scala:40:9] assign auto_out_d_ready = auto_out_d_ready_0; // @[Buffer.scala:40:9] assign auto_out_e_valid = auto_out_e_valid_0; // @[Buffer.scala:40:9] assign auto_out_e_bits_sink = auto_out_e_bits_sink_0; // @[Buffer.scala:40:9] endmodule
Generate the Verilog code corresponding to the following Chisel files. File Decode.scala: // See LICENSE.Berkeley for license details. package freechips.rocketchip.rocket import chisel3._ import chisel3.util.BitPat import chisel3.util.experimental.decode._ object DecodeLogic { // TODO This should be a method on BitPat private def hasDontCare(bp: BitPat): Boolean = bp.mask.bitCount != bp.width // Pads BitPats that are safe to pad (no don't cares), errors otherwise private def padBP(bp: BitPat, width: Int): BitPat = { if (bp.width == width) bp else { require(!hasDontCare(bp), s"Cannot pad '$bp' to '$width' bits because it has don't cares") val diff = width - bp.width require(diff > 0, s"Cannot pad '$bp' to '$width' because it is already '${bp.width}' bits wide!") BitPat(0.U(diff.W)) ## bp } } def apply(addr: UInt, default: BitPat, mapping: Iterable[(BitPat, BitPat)]): UInt = chisel3.util.experimental.decode.decoder(QMCMinimizer, addr, TruthTable(mapping, default)) def apply(addr: UInt, default: Seq[BitPat], mappingIn: Iterable[(BitPat, Seq[BitPat])]): Seq[UInt] = { val nElts = default.size require(mappingIn.forall(_._2.size == nElts), s"All Seq[BitPat] must be of the same length, got $nElts vs. ${mappingIn.find(_._2.size != nElts).get}" ) val elementsGrouped = mappingIn.map(_._2).transpose val elementWidths = elementsGrouped.zip(default).map { case (elts, default) => (default :: elts.toList).map(_.getWidth).max } val resultWidth = elementWidths.sum val elementIndices = elementWidths.scan(resultWidth - 1) { case (l, r) => l - r } // All BitPats that correspond to a given element in the result must have the same width in the // chisel3 decoder. We will zero pad any BitPats that are too small so long as they dont have // any don't cares. If there are don't cares, it is an error and the user needs to pad the // BitPat themselves val defaultsPadded = default.zip(elementWidths).map { case (bp, w) => padBP(bp, w) } val mappingInPadded = mappingIn.map { case (in, elts) => in -> elts.zip(elementWidths).map { case (bp, w) => padBP(bp, w) } } val decoded = apply(addr, defaultsPadded.reduce(_ ## _), mappingInPadded.map { case (in, out) => (in, out.reduce(_ ## _)) }) elementIndices.zip(elementIndices.tail).map { case (msb, lsb) => decoded(msb, lsb + 1) }.toList } def apply(addr: UInt, default: Seq[BitPat], mappingIn: List[(UInt, Seq[BitPat])]): Seq[UInt] = apply(addr, default, mappingIn.map(m => (BitPat(m._1), m._2)).asInstanceOf[Iterable[(BitPat, Seq[BitPat])]]) def apply(addr: UInt, trues: Iterable[UInt], falses: Iterable[UInt]): Bool = apply(addr, BitPat.dontCare(1), trues.map(BitPat(_) -> BitPat("b1")) ++ falses.map(BitPat(_) -> BitPat("b0"))).asBool } File Counters.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ // Produces 0-width value when counting to 1 class ZCounter(val n: Int) { val value = RegInit(0.U(log2Ceil(n).W)) def inc(): Bool = { if (n == 1) true.B else { val wrap = value === (n-1).U value := Mux(!isPow2(n).B && wrap, 0.U, value + 1.U) wrap } } } object ZCounter { def apply(n: Int) = new ZCounter(n) def apply(cond: Bool, n: Int): (UInt, Bool) = { val c = new ZCounter(n) var wrap: Bool = null when (cond) { wrap = c.inc() } (c.value, cond && wrap) } } object TwoWayCounter { def apply(up: Bool, down: Bool, max: Int): UInt = { val cnt = RegInit(0.U(log2Up(max + 1).W)) when (up && !down) { cnt := cnt + 1.U } when (down && !up) { cnt := cnt - 1.U } cnt } } // a counter that clock gates most of its MSBs using the LSB carry-out case class WideCounter(width: Int, inc: UInt = 1.U, reset: Boolean = true, inhibit: Bool = false.B) { private val isWide = width > (2 * inc.getWidth) private val smallWidth = if (isWide) inc.getWidth max log2Up(width) else width private val small = if (reset) RegInit(0.U(smallWidth.W)) else Reg(UInt(smallWidth.W)) private val nextSmall = small +& inc when (!inhibit) { small := nextSmall } private val large = if (isWide) { val r = if (reset) RegInit(0.U((width - smallWidth).W)) else Reg(UInt((width - smallWidth).W)) when (nextSmall(smallWidth) && !inhibit) { r := r + 1.U } r } else null val value = if (isWide) Cat(large, small) else small lazy val carryOut = { val lo = (small ^ nextSmall) >> 1 if (!isWide) lo else { val hi = Mux(nextSmall(smallWidth), large ^ (large +& 1.U), 0.U) >> 1 Cat(hi, lo) } } def := (x: UInt) = { small := x if (isWide) large := x >> smallWidth } } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /* Like Vec.apply(idx), but tolerates indices of mismatched width / def extract(idx: UInt): T = x((idx \| 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx \| 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def \| (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a \|\| b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_\|\|_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /* Any Data subtype that has a Bool member named valid. / type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /* converts from camel case to to underscores, also removing all spaces / def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /* converts spaces or underscores to hyphens, also lowering case / def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y \| (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y \|\| y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 \| 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /* Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation / def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File PMP.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.rocket import chisel3._ import chisel3.util.{Cat, log2Ceil} import org.chipsalliance.cde.config._ import freechips.rocketchip.tile._ import freechips.rocketchip.util._ class PMPConfig extends Bundle { val l = Bool() val res = UInt(2.W) val a = UInt(2.W) val x = Bool() val w = Bool() val r = Bool() } object PMP { def lgAlign = 2 def apply(reg: PMPReg): PMP = { val pmp = Wire(new PMP()(reg.p)) pmp.cfg := reg.cfg pmp.addr := reg.addr pmp.mask := pmp.computeMask pmp } } class PMPReg(implicit p: Parameters) extends CoreBundle()(p) { val cfg = new PMPConfig val addr = UInt((paddrBits - PMP.lgAlign).W) def reset(): Unit = { cfg.a := 0.U cfg.l := 0.U } def readAddr = if (pmpGranularity.log2 == PMP.lgAlign) addr else { val mask = ((BigInt(1) << (pmpGranularity.log2 - PMP.lgAlign)) - 1).U Mux(napot, addr \| (mask >> 1), ~(~addr \| mask)) } def napot = cfg.a(1) def torNotNAPOT = cfg.a(0) def tor = !napot && torNotNAPOT def cfgLocked = cfg.l def addrLocked(next: PMPReg) = cfgLocked \|\| next.cfgLocked && next.tor } class PMP(implicit p: Parameters) extends PMPReg { val mask = UInt(paddrBits.W) import PMP._ def computeMask = { val base = Cat(addr, cfg.a(0)) \| ((pmpGranularity - 1).U >> lgAlign) Cat(base & ~(base + 1.U), ((1 << lgAlign) - 1).U) } private def comparand = ~(~(addr << lgAlign) \| (pmpGranularity - 1).U) private def pow2Match(x: UInt, lgSize: UInt, lgMaxSize: Int) = { def eval(a: UInt, b: UInt, m: UInt) = ((a ^ b) & ~m) === 0.U if (lgMaxSize <= pmpGranularity.log2) { eval(x, comparand, mask) } else { // break up the circuit; the MSB part will be CSE'd val lsbMask = mask \| UIntToOH1(lgSize, lgMaxSize) val msbMatch = eval(x >> lgMaxSize, comparand >> lgMaxSize, mask >> lgMaxSize) val lsbMatch = eval(x(lgMaxSize-1, 0), comparand(lgMaxSize-1, 0), lsbMask(lgMaxSize-1, 0)) msbMatch && lsbMatch } } private def boundMatch(x: UInt, lsbMask: UInt, lgMaxSize: Int) = { if (lgMaxSize <= pmpGranularity.log2) { x < comparand } else { // break up the circuit; the MSB part will be CSE'd val msbsLess = (x >> lgMaxSize) < (comparand >> lgMaxSize) val msbsEqual = ((x >> lgMaxSize) ^ (comparand >> lgMaxSize)) === 0.U val lsbsLess = (x(lgMaxSize-1, 0) \| lsbMask) < comparand(lgMaxSize-1, 0) msbsLess \|\| (msbsEqual && lsbsLess) } } private def lowerBoundMatch(x: UInt, lgSize: UInt, lgMaxSize: Int) = !boundMatch(x, UIntToOH1(lgSize, lgMaxSize), lgMaxSize) private def upperBoundMatch(x: UInt, lgMaxSize: Int) = boundMatch(x, 0.U, lgMaxSize) private def rangeMatch(x: UInt, lgSize: UInt, lgMaxSize: Int, prev: PMP) = prev.lowerBoundMatch(x, lgSize, lgMaxSize) && upperBoundMatch(x, lgMaxSize) private def pow2Homogeneous(x: UInt, pgLevel: UInt) = { val maskHomogeneous = pgLevelMap { idxBits => if (idxBits > paddrBits) false.B else mask(idxBits - 1) } (pgLevel) maskHomogeneous \|\| (pgLevelMap { idxBits => ((x ^ comparand) >> idxBits) =/= 0.U } (pgLevel)) } private def pgLevelMap[T](f: Int => T) = (0 until pgLevels).map { i => f(pgIdxBits + (pgLevels - 1 - i) pgLevelBits) } private def rangeHomogeneous(x: UInt, pgLevel: UInt, prev: PMP) = { val beginsAfterLower = !(x < prev.comparand) val beginsAfterUpper = !(x < comparand) val pgMask = pgLevelMap { idxBits => (((BigInt(1) << paddrBits) - (BigInt(1) << idxBits)) max 0).U } (pgLevel) val endsBeforeLower = (x & pgMask) < (prev.comparand & pgMask) val endsBeforeUpper = (x & pgMask) < (comparand & pgMask) endsBeforeLower \|\| beginsAfterUpper \|\| (beginsAfterLower && endsBeforeUpper) } // returns whether this PMP completely contains, or contains none of, a page def homogeneous(x: UInt, pgLevel: UInt, prev: PMP): Bool = Mux(napot, pow2Homogeneous(x, pgLevel), !torNotNAPOT \|\| rangeHomogeneous(x, pgLevel, prev)) // returns whether this matching PMP fully contains the access def aligned(x: UInt, lgSize: UInt, lgMaxSize: Int, prev: PMP): Bool = if (lgMaxSize <= pmpGranularity.log2) true.B else { val lsbMask = UIntToOH1(lgSize, lgMaxSize) val straddlesLowerBound = ((x >> lgMaxSize) ^ (prev.comparand >> lgMaxSize)) === 0.U && (prev.comparand(lgMaxSize-1, 0) & ~x(lgMaxSize-1, 0)) =/= 0.U val straddlesUpperBound = ((x >> lgMaxSize) ^ (comparand >> lgMaxSize)) === 0.U && (comparand(lgMaxSize-1, 0) & (x(lgMaxSize-1, 0) \| lsbMask)) =/= 0.U val rangeAligned = !(straddlesLowerBound \|\| straddlesUpperBound) val pow2Aligned = (lsbMask & ~mask(lgMaxSize-1, 0)) === 0.U Mux(napot, pow2Aligned, rangeAligned) } // returns whether this PMP matches at least one byte of the access def hit(x: UInt, lgSize: UInt, lgMaxSize: Int, prev: PMP): Bool = Mux(napot, pow2Match(x, lgSize, lgMaxSize), torNotNAPOT && rangeMatch(x, lgSize, lgMaxSize, prev)) } class PMPHomogeneityChecker(pmps: Seq[PMP])(implicit p: Parameters) { def apply(addr: UInt, pgLevel: UInt): Bool = { pmps.foldLeft((true.B, 0.U.asTypeOf(new PMP))) { case ((h, prev), pmp) => (h && pmp.homogeneous(addr, pgLevel, prev), pmp) }._1 } } class PMPChecker(lgMaxSize: Int)(implicit val p: Parameters) extends Module with HasCoreParameters { override def desiredName = s"PMPChecker_s${lgMaxSize}" val io = IO(new Bundle { val prv = Input(UInt(PRV.SZ.W)) val pmp = Input(Vec(nPMPs, new PMP)) val addr = Input(UInt(paddrBits.W)) val size = Input(UInt(log2Ceil(lgMaxSize + 1).W)) val r = Output(Bool()) val w = Output(Bool()) val x = Output(Bool()) }) val default = if (io.pmp.isEmpty) true.B else io.prv > PRV.S.U val pmp0 = WireInit(0.U.asTypeOf(new PMP)) pmp0.cfg.r := default pmp0.cfg.w := default pmp0.cfg.x := default val res = (io.pmp zip (pmp0 +: io.pmp)).reverse.foldLeft(pmp0) { case (prev, (pmp, prevPMP)) => val hit = pmp.hit(io.addr, io.size, lgMaxSize, prevPMP) val ignore = default && !pmp.cfg.l val aligned = pmp.aligned(io.addr, io.size, lgMaxSize, prevPMP) for ((name, idx) <- Seq("no", "TOR", if (pmpGranularity <= 4) "NA4" else "", "NAPOT").zipWithIndex; if name.nonEmpty) property.cover(pmp.cfg.a === idx.U, s"The cfg access is set to ${name} access ", "Cover PMP access mode setting") property.cover(pmp.cfg.l === 0x1.U, s"The cfg lock is set to high ", "Cover PMP lock mode setting") // Not including Write and no Read permission as the combination is reserved for ((name, idx) <- Seq("no", "RO", "", "RW", "X", "RX", "", "RWX").zipWithIndex; if name.nonEmpty) property.cover((Cat(pmp.cfg.x, pmp.cfg.w, pmp.cfg.r) === idx.U), s"The permission is set to ${name} access ", "Cover PMP access permission setting") for ((name, idx) <- Seq("", "TOR", if (pmpGranularity <= 4) "NA4" else "", "NAPOT").zipWithIndex; if name.nonEmpty) { property.cover(!ignore && hit && aligned && pmp.cfg.a === idx.U, s"The access matches ${name} mode ", "Cover PMP access") property.cover(pmp.cfg.l && hit && aligned && pmp.cfg.a === idx.U, s"The access matches ${name} mode with lock bit high", "Cover PMP access with lock bit") } val cur = WireInit(pmp) cur.cfg.r := aligned && (pmp.cfg.r \|\| ignore) cur.cfg.w := aligned && (pmp.cfg.w \|\| ignore) cur.cfg.x := aligned && (pmp.cfg.x \|\| ignore) Mux(hit, cur, prev) } io.r := res.cfg.r io.w := res.cfg.w io.x := res.cfg.x } File Events.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.rocket import chisel3._ import chisel3.util.log2Ceil import freechips.rocketchip.util._ import freechips.rocketchip.util.property class EventSet(val gate: (UInt, UInt) => Bool, val events: Seq[(String, () => Bool)]) { def size = events.size val hits = WireDefault(VecInit(Seq.fill(size)(false.B))) def check(mask: UInt) = { hits := events.map(_._2()) gate(mask, hits.asUInt) } def dump(): Unit = { for (((name, _), i) <- events.zipWithIndex) when (check(1.U << i)) { printf(s"Event $name\n") } } def withCovers: Unit = { events.zipWithIndex.foreach { case ((name, func), i) => property.cover(gate((1.U << i), (func() << i)), name) } } } class EventSets(val eventSets: Seq[EventSet]) { def maskEventSelector(eventSel: UInt): UInt = { // allow full associativity between counters and event sets (for now?) val setMask = (BigInt(1) << eventSetIdBits) - 1 val maskMask = ((BigInt(1) << eventSets.map(_.size).max) - 1) << maxEventSetIdBits eventSel & (setMask \| maskMask).U } private def decode(counter: UInt): (UInt, UInt) = { require(eventSets.size <= (1 << maxEventSetIdBits)) require(eventSetIdBits > 0) (counter(eventSetIdBits-1, 0), counter >> maxEventSetIdBits) } def evaluate(eventSel: UInt): Bool = { val (set, mask) = decode(eventSel) val sets = for (e <- eventSets) yield { require(e.hits.getWidth <= mask.getWidth, s"too many events ${e.hits.getWidth} wider than mask ${mask.getWidth}") e check mask } sets(set) } def cover() = eventSets.foreach { _.withCovers } private def eventSetIdBits = log2Ceil(eventSets.size) private def maxEventSetIdBits = 8 require(eventSetIdBits <= maxEventSetIdBits) } class SuperscalarEventSets(val eventSets: Seq[(Seq[EventSet], (UInt, UInt) => UInt)]) { def evaluate(eventSel: UInt): UInt = { val (set, mask) = decode(eventSel) val sets = for ((sets, reducer) <- eventSets) yield { sets.map { set => require(set.hits.getWidth <= mask.getWidth, s"too many events ${set.hits.getWidth} wider than mask ${mask.getWidth}") set.check(mask) }.reduce(reducer) } val zeroPadded = sets.padTo(1 << eventSetIdBits, 0.U) zeroPadded(set) } def toScalarEventSets: EventSets = new EventSets(eventSets.map(_._1.head)) def cover(): Unit = { eventSets.foreach(_._1.foreach(_.withCovers)) } private def decode(counter: UInt): (UInt, UInt) = { require(eventSets.size <= (1 << maxEventSetIdBits)) require(eventSetIdBits > 0) (counter(eventSetIdBits-1, 0), counter >> maxEventSetIdBits) } private def eventSetIdBits = log2Ceil(eventSets.size) private def maxEventSetIdBits = 8 require(eventSets.forall(s => s._1.forall(_.size == s._1.head.size))) require(eventSetIdBits <= maxEventSetIdBits) } File CSR.scala: // See LICENSE.SiFive for license details. // See LICENSE.Berkeley for license details. package freechips.rocketchip.rocket import chisel3._ import chisel3.util.{BitPat, Cat, Fill, Mux1H, PopCount, PriorityMux, RegEnable, UIntToOH, Valid, log2Ceil, log2Up} import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.devices.debug.DebugModuleKey import freechips.rocketchip.tile._ import freechips.rocketchip.util._ import freechips.rocketchip.util.property import scala.collection.mutable.LinkedHashMap import Instructions._ import CustomInstructions._ class MStatus extends Bundle { // not truly part of mstatus, but convenient val debug = Bool() val cease = Bool() val wfi = Bool() val isa = UInt(32.W) val dprv = UInt(PRV.SZ.W) // effective prv for data accesses val dv = Bool() // effective v for data accesses val prv = UInt(PRV.SZ.W) val v = Bool() val sd = Bool() val zero2 = UInt(23.W) val mpv = Bool() val gva = Bool() val mbe = Bool() val sbe = Bool() val sxl = UInt(2.W) val uxl = UInt(2.W) val sd_rv32 = Bool() val zero1 = UInt(8.W) val tsr = Bool() val tw = Bool() val tvm = Bool() val mxr = Bool() val sum = Bool() val mprv = Bool() val xs = UInt(2.W) val fs = UInt(2.W) val mpp = UInt(2.W) val vs = UInt(2.W) val spp = UInt(1.W) val mpie = Bool() val ube = Bool() val spie = Bool() val upie = Bool() val mie = Bool() val hie = Bool() val sie = Bool() val uie = Bool() } class MNStatus extends Bundle { val mpp = UInt(2.W) val zero3 = UInt(3.W) val mpv = Bool() val zero2 = UInt(3.W) val mie = Bool() val zero1 = UInt(3.W) } class HStatus extends Bundle { val zero6 = UInt(30.W) val vsxl = UInt(2.W) val zero5 = UInt(9.W) val vtsr = Bool() val vtw = Bool() val vtvm = Bool() val zero3 = UInt(2.W) val vgein = UInt(6.W) val zero2 = UInt(2.W) val hu = Bool() val spvp = Bool() val spv = Bool() val gva = Bool() val vsbe = Bool() val zero1 = UInt(5.W) } class DCSR extends Bundle { val xdebugver = UInt(2.W) val zero4 = UInt(2.W) val zero3 = UInt(12.W) val ebreakm = Bool() val ebreakh = Bool() val ebreaks = Bool() val ebreaku = Bool() val zero2 = Bool() val stopcycle = Bool() val stoptime = Bool() val cause = UInt(3.W) val v = Bool() val zero1 = UInt(2.W) val step = Bool() val prv = UInt(PRV.SZ.W) } class MIP(implicit p: Parameters) extends CoreBundle()(p) with HasCoreParameters { val lip = Vec(coreParams.nLocalInterrupts, Bool()) val zero1 = Bool() val debug = Bool() // keep in sync with CSR.debugIntCause val rocc = Bool() val sgeip = Bool() val meip = Bool() val vseip = Bool() val seip = Bool() val ueip = Bool() val mtip = Bool() val vstip = Bool() val stip = Bool() val utip = Bool() val msip = Bool() val vssip = Bool() val ssip = Bool() val usip = Bool() } class Envcfg extends Bundle { val stce = Bool() // only for menvcfg/henvcfg val pbmte = Bool() // only for menvcfg/henvcfg val zero54 = UInt(54.W) val cbze = Bool() val cbcfe = Bool() val cbie = UInt(2.W) val zero3 = UInt(3.W) val fiom = Bool() def write(wdata: UInt) { val new_envcfg = wdata.asTypeOf(new Envcfg) fiom := new_envcfg.fiom // only FIOM is writable currently } } class PTBR(implicit p: Parameters) extends CoreBundle()(p) { def additionalPgLevels = mode.extract(log2Ceil(pgLevels-minPgLevels+1)-1, 0) def pgLevelsToMode(i: Int) = (xLen, i) match { case (32, 2) => 1 case (64, x) if x >= 3 && x <= 6 => x + 5 } val (modeBits, maxASIdBits) = xLen match { case 32 => (1, 9) case 64 => (4, 16) } require(modeBits + maxASIdBits + maxPAddrBits - pgIdxBits == xLen) val mode = UInt(modeBits.W) val asid = UInt(maxASIdBits.W) val ppn = UInt((maxPAddrBits - pgIdxBits).W) } object PRV { val SZ = 2 val U = 0 val S = 1 val H = 2 val M = 3 } object CSR { // commands val SZ = 3 def X = BitPat.dontCare(SZ) def N = 0.U(SZ.W) def R = 2.U(SZ.W) def I = 4.U(SZ.W) def W = 5.U(SZ.W) def S = 6.U(SZ.W) def C = 7.U(SZ.W) // mask a CSR cmd with a valid bit def maskCmd(valid: Bool, cmd: UInt): UInt = { // all commands less than CSR.I are treated by CSRFile as NOPs cmd & ~Mux(valid, 0.U, CSR.I) } val ADDRSZ = 12 def modeLSB: Int = 8 def mode(addr: Int): Int = (addr >> modeLSB) % (1 << PRV.SZ) def mode(addr: UInt): UInt = addr(modeLSB + PRV.SZ - 1, modeLSB) def busErrorIntCause = 128 def debugIntCause = 14 // keep in sync with MIP.debug def debugTriggerCause = { val res = debugIntCause require(!(Causes.all contains res)) res } def rnmiIntCause = 13 // NMI: Higher numbers = higher priority, must not reuse debugIntCause def rnmiBEUCause = 12 val firstCtr = CSRs.cycle val firstCtrH = CSRs.cycleh val firstHPC = CSRs.hpmcounter3 val firstHPCH = CSRs.hpmcounter3h val firstHPE = CSRs.mhpmevent3 val firstMHPC = CSRs.mhpmcounter3 val firstMHPCH = CSRs.mhpmcounter3h val firstHPM = 3 val nCtr = 32 val nHPM = nCtr - firstHPM val hpmWidth = 40 val maxPMPs = 16 } class PerfCounterIO(implicit p: Parameters) extends CoreBundle with HasCoreParameters { val eventSel = Output(UInt(xLen.W)) val inc = Input(UInt(log2Ceil(1+retireWidth).W)) } class TracedInstruction(implicit p: Parameters) extends CoreBundle { val valid = Bool() val iaddr = UInt(coreMaxAddrBits.W) val insn = UInt(iLen.W) val priv = UInt(3.W) val exception = Bool() val interrupt = Bool() val cause = UInt(xLen.W) val tval = UInt((coreMaxAddrBits max iLen).W) val wdata = Option.when(traceHasWdata)(UInt((vLen max xLen).W)) } class TraceAux extends Bundle { val enable = Bool() val stall = Bool() } class CSRDecodeIO(implicit p: Parameters) extends CoreBundle { val inst = Input(UInt(iLen.W)) def csr_addr = (inst >> 20)(CSR.ADDRSZ-1, 0) val fp_illegal = Output(Bool()) val vector_illegal = Output(Bool()) val fp_csr = Output(Bool()) val vector_csr = Output(Bool()) val rocc_illegal = Output(Bool()) val read_illegal = Output(Bool()) val write_illegal = Output(Bool()) val write_flush = Output(Bool()) val system_illegal = Output(Bool()) val virtual_access_illegal = Output(Bool()) val virtual_system_illegal = Output(Bool()) } class CSRFileIO(hasBeu: Boolean)(implicit p: Parameters) extends CoreBundle with HasCoreParameters { val ungated_clock = Input(Clock()) val interrupts = Input(new CoreInterrupts(hasBeu)) val hartid = Input(UInt(hartIdLen.W)) val rw = new Bundle { val addr = Input(UInt(CSR.ADDRSZ.W)) val cmd = Input(Bits(CSR.SZ.W)) val rdata = Output(Bits(xLen.W)) val wdata = Input(Bits(xLen.W)) } val decode = Vec(decodeWidth, new CSRDecodeIO) val csr_stall = Output(Bool()) // stall retire for wfi val rw_stall = Output(Bool()) // stall rw, rw will have no effect while rw_stall val eret = Output(Bool()) val singleStep = Output(Bool()) val status = Output(new MStatus()) val hstatus = Output(new HStatus()) val gstatus = Output(new MStatus()) val ptbr = Output(new PTBR()) val hgatp = Output(new PTBR()) val vsatp = Output(new PTBR()) val evec = Output(UInt(vaddrBitsExtended.W)) val exception = Input(Bool()) val retire = Input(UInt(log2Up(1+retireWidth).W)) val cause = Input(UInt(xLen.W)) val pc = Input(UInt(vaddrBitsExtended.W)) val tval = Input(UInt(vaddrBitsExtended.W)) val htval = Input(UInt(((maxSVAddrBits + 1) min xLen).W)) val mhtinst_read_pseudo = Input(Bool()) val gva = Input(Bool()) val time = Output(UInt(xLen.W)) val fcsr_rm = Output(Bits(FPConstants.RM_SZ.W)) val fcsr_flags = Flipped(Valid(Bits(FPConstants.FLAGS_SZ.W))) val set_fs_dirty = coreParams.haveFSDirty.option(Input(Bool())) val rocc_interrupt = Input(Bool()) val interrupt = Output(Bool()) val interrupt_cause = Output(UInt(xLen.W)) val bp = Output(Vec(nBreakpoints, new BP)) val pmp = Output(Vec(nPMPs, new PMP)) val counters = Vec(nPerfCounters, new PerfCounterIO) val csrw_counter = Output(UInt(CSR.nCtr.W)) val inhibit_cycle = Output(Bool()) val inst = Input(Vec(retireWidth, UInt(iLen.W))) val trace = Output(Vec(retireWidth, new TracedInstruction)) val mcontext = Output(UInt(coreParams.mcontextWidth.W)) val scontext = Output(UInt(coreParams.scontextWidth.W)) val fiom = Output(Bool()) val vector = usingVector.option(new Bundle { val vconfig = Output(new VConfig()) val vstart = Output(UInt(maxVLMax.log2.W)) val vxrm = Output(UInt(2.W)) val set_vs_dirty = Input(Bool()) val set_vconfig = Flipped(Valid(new VConfig)) val set_vstart = Flipped(Valid(vstart)) val set_vxsat = Input(Bool()) }) } class VConfig(implicit p: Parameters) extends CoreBundle { val vl = UInt((maxVLMax.log2 + 1).W) val vtype = new VType } object VType { def fromUInt(that: UInt, ignore_vill: Boolean = false)(implicit p: Parameters): VType = { val res = 0.U.asTypeOf(new VType) val in = that.asTypeOf(res) val vill = (in.max_vsew.U < in.vsew) \|\| !in.lmul_ok \|\| in.reserved =/= 0.U \|\| in.vill when (!vill \|\| ignore_vill.B) { res := in res.vsew := in.vsew(log2Ceil(1 + in.max_vsew) - 1, 0) } res.reserved := 0.U res.vill := vill res } def computeVL(avl: UInt, vtype: UInt, currentVL: UInt, useCurrentVL: Bool, useMax: Bool, useZero: Bool)(implicit p: Parameters): UInt = VType.fromUInt(vtype, true).vl(avl, currentVL, useCurrentVL, useMax, useZero) } class VType(implicit p: Parameters) extends CoreBundle { val vill = Bool() val reserved = UInt((xLen - 9).W) val vma = Bool() val vta = Bool() val vsew = UInt(3.W) val vlmul_sign = Bool() val vlmul_mag = UInt(2.W) def vlmul_signed: SInt = Cat(vlmul_sign, vlmul_mag).asSInt @deprecated("use vlmul_sign, vlmul_mag, or vlmul_signed", "RVV 0.9") def vlmul: UInt = vlmul_mag def max_vsew = log2Ceil(eLen/8) def max_vlmul = (1 << vlmul_mag.getWidth) - 1 def lmul_ok: Bool = Mux(this.vlmul_sign, this.vlmul_mag =/= 0.U && ~this.vlmul_mag < max_vsew.U - this.vsew, true.B) def minVLMax: Int = ((maxVLMax / eLen) >> ((1 << vlmul_mag.getWidth) - 1)) max 1 def vlMax: UInt = (maxVLMax.U >> (this.vsew +& Cat(this.vlmul_sign, ~this.vlmul_mag))).andNot((minVLMax-1).U) def vl(avl: UInt, currentVL: UInt, useCurrentVL: Bool, useMax: Bool, useZero: Bool): UInt = { val atLeastMaxVLMax = useMax \|\| Mux(useCurrentVL, currentVL >= maxVLMax.U, avl >= maxVLMax.U) val avl_lsbs = Mux(useCurrentVL, currentVL, avl)(maxVLMax.log2 - 1, 0) val atLeastVLMax = atLeastMaxVLMax \|\| (avl_lsbs & (-maxVLMax.S >> (this.vsew +& Cat(this.vlmul_sign, ~this.vlmul_mag))).asUInt.andNot((minVLMax-1).U)).orR val isZero = vill \|\| useZero Mux(!isZero && atLeastVLMax, vlMax, 0.U) \| Mux(!isZero && !atLeastVLMax, avl_lsbs, 0.U) } } class CSRFile( perfEventSets: EventSets = new EventSets(Seq()), customCSRs: Seq[CustomCSR] = Nil, roccCSRs: Seq[CustomCSR] = Nil, hasBeu: Boolean = false)(implicit p: Parameters) extends CoreModule()(p) with HasCoreParameters { val io = IO(new CSRFileIO(hasBeu) { val customCSRs = Vec(CSRFile.this.customCSRs.size, new CustomCSRIO) val roccCSRs = Vec(CSRFile.this.roccCSRs.size, new CustomCSRIO) }) io.rw_stall := false.B val reset_mstatus = WireDefault(0.U.asTypeOf(new MStatus())) reset_mstatus.mpp := PRV.M.U reset_mstatus.prv := PRV.M.U reset_mstatus.xs := (if (usingRoCC) 3.U else 0.U) val reg_mstatus = RegInit(reset_mstatus) val new_prv = WireDefault(reg_mstatus.prv) reg_mstatus.prv := legalizePrivilege(new_prv) val reset_dcsr = WireDefault(0.U.asTypeOf(new DCSR())) reset_dcsr.xdebugver := 1.U reset_dcsr.prv := PRV.M.U val reg_dcsr = RegInit(reset_dcsr) val (supported_interrupts, delegable_interrupts) = { val sup = Wire(new MIP) sup.usip := false.B sup.ssip := usingSupervisor.B sup.vssip := usingHypervisor.B sup.msip := true.B sup.utip := false.B sup.stip := usingSupervisor.B sup.vstip := usingHypervisor.B sup.mtip := true.B sup.ueip := false.B sup.seip := usingSupervisor.B sup.vseip := usingHypervisor.B sup.meip := true.B sup.sgeip := false.B sup.rocc := usingRoCC.B sup.debug := false.B sup.zero1 := false.B sup.lip foreach { _ := true.B } val supported_high_interrupts = if (io.interrupts.buserror.nonEmpty && !usingNMI) (BigInt(1) << CSR.busErrorIntCause).U else 0.U val del = WireDefault(sup) del.msip := false.B del.mtip := false.B del.meip := false.B (sup.asUInt \| supported_high_interrupts, del.asUInt) } val delegable_base_exceptions = Seq( Causes.misaligned_fetch, Causes.fetch_page_fault, Causes.breakpoint, Causes.load_page_fault, Causes.store_page_fault, Causes.misaligned_load, Causes.misaligned_store, Causes.illegal_instruction, Causes.user_ecall, ) val delegable_hypervisor_exceptions = Seq( Causes.virtual_supervisor_ecall, Causes.fetch_guest_page_fault, Causes.load_guest_page_fault, Causes.virtual_instruction, Causes.store_guest_page_fault, ) val delegable_exceptions = ( delegable_base_exceptions ++ (if (usingHypervisor) delegable_hypervisor_exceptions else Seq()) ).map(1 << _).sum.U val hs_delegable_exceptions = Seq( Causes.misaligned_fetch, Causes.fetch_access, Causes.illegal_instruction, Causes.breakpoint, Causes.misaligned_load, Causes.load_access, Causes.misaligned_store, Causes.store_access, Causes.user_ecall, Causes.fetch_page_fault, Causes.load_page_fault, Causes.store_page_fault).map(1 << _).sum.U val (hs_delegable_interrupts, mideleg_always_hs) = { val always = WireDefault(0.U.asTypeOf(new MIP())) always.vssip := usingHypervisor.B always.vstip := usingHypervisor.B always.vseip := usingHypervisor.B val deleg = WireDefault(always) deleg.lip.foreach { _ := usingHypervisor.B } (deleg.asUInt, always.asUInt) } val reg_debug = RegInit(false.B) val reg_dpc = Reg(UInt(vaddrBitsExtended.W)) val reg_dscratch0 = Reg(UInt(xLen.W)) val reg_dscratch1 = (p(DebugModuleKey).map(_.nDscratch).getOrElse(1) > 1).option(Reg(UInt(xLen.W))) val reg_singleStepped = Reg(Bool()) val reg_mcontext = (coreParams.mcontextWidth > 0).option(RegInit(0.U(coreParams.mcontextWidth.W))) val reg_scontext = (coreParams.scontextWidth > 0).option(RegInit(0.U(coreParams.scontextWidth.W))) val reg_tselect = Reg(UInt(log2Up(nBreakpoints).W)) val reg_bp = Reg(Vec(1 << log2Up(nBreakpoints), new BP)) val reg_pmp = Reg(Vec(nPMPs, new PMPReg)) val reg_mie = Reg(UInt(xLen.W)) val (reg_mideleg, read_mideleg) = { val reg = Reg(UInt(xLen.W)) (reg, Mux(usingSupervisor.B, reg & delegable_interrupts \| mideleg_always_hs, 0.U)) } val (reg_medeleg, read_medeleg) = { val reg = Reg(UInt(xLen.W)) (reg, Mux(usingSupervisor.B, reg & delegable_exceptions, 0.U)) } val reg_mip = Reg(new MIP) val reg_mepc = Reg(UInt(vaddrBitsExtended.W)) val reg_mcause = RegInit(0.U(xLen.W)) val reg_mtval = Reg(UInt(vaddrBitsExtended.W)) val reg_mtval2 = Reg(UInt(((maxSVAddrBits + 1) min xLen).W)) val reg_mscratch = Reg(Bits(xLen.W)) val mtvecWidth = paddrBits min xLen val reg_mtvec = mtvecInit match { case Some(addr) => RegInit(addr.U(mtvecWidth.W)) case None => Reg(UInt(mtvecWidth.W)) } val reset_mnstatus = WireDefault(0.U.asTypeOf(new MNStatus())) reset_mnstatus.mpp := PRV.M.U val reg_mnscratch = Reg(Bits(xLen.W)) val reg_mnepc = Reg(UInt(vaddrBitsExtended.W)) val reg_mncause = RegInit(0.U(xLen.W)) val reg_mnstatus = RegInit(reset_mnstatus) val reg_rnmie = RegInit(true.B) val nmie = reg_rnmie val reg_menvcfg = RegInit(0.U.asTypeOf(new Envcfg)) val reg_senvcfg = RegInit(0.U.asTypeOf(new Envcfg)) val reg_henvcfg = RegInit(0.U.asTypeOf(new Envcfg)) val delegable_counters = ((BigInt(1) << (nPerfCounters + CSR.firstHPM)) - 1).U val (reg_mcounteren, read_mcounteren) = { val reg = Reg(UInt(32.W)) (reg, Mux(usingUser.B, reg & delegable_counters, 0.U)) } val (reg_scounteren, read_scounteren) = { val reg = Reg(UInt(32.W)) (reg, Mux(usingSupervisor.B, reg & delegable_counters, 0.U)) } val (reg_hideleg, read_hideleg) = { val reg = Reg(UInt(xLen.W)) (reg, Mux(usingHypervisor.B, reg & hs_delegable_interrupts, 0.U)) } val (reg_hedeleg, read_hedeleg) = { val reg = Reg(UInt(xLen.W)) (reg, Mux(usingHypervisor.B, reg & hs_delegable_exceptions, 0.U)) } val hs_delegable_counters = delegable_counters val (reg_hcounteren, read_hcounteren) = { val reg = Reg(UInt(32.W)) (reg, Mux(usingHypervisor.B, reg & hs_delegable_counters, 0.U)) } val reg_hstatus = RegInit(0.U.asTypeOf(new HStatus)) val reg_hgatp = Reg(new PTBR) val reg_htval = Reg(reg_mtval2.cloneType) val read_hvip = reg_mip.asUInt & hs_delegable_interrupts val read_hie = reg_mie & hs_delegable_interrupts val (reg_vstvec, read_vstvec) = { val reg = Reg(UInt(vaddrBitsExtended.W)) (reg, formTVec(reg).sextTo(xLen)) } val reg_vsstatus = Reg(new MStatus) val reg_vsscratch = Reg(Bits(xLen.W)) val reg_vsepc = Reg(UInt(vaddrBitsExtended.W)) val reg_vscause = Reg(Bits(xLen.W)) val reg_vstval = Reg(UInt(vaddrBitsExtended.W)) val reg_vsatp = Reg(new PTBR) val reg_sepc = Reg(UInt(vaddrBitsExtended.W)) val reg_scause = Reg(Bits(xLen.W)) val reg_stval = Reg(UInt(vaddrBitsExtended.W)) val reg_sscratch = Reg(Bits(xLen.W)) val reg_stvec = Reg(UInt((if (usingHypervisor) vaddrBitsExtended else vaddrBits).W)) val reg_satp = Reg(new PTBR) val reg_wfi = withClock(io.ungated_clock) { RegInit(false.B) } val reg_fflags = Reg(UInt(5.W)) val reg_frm = Reg(UInt(3.W)) val reg_vconfig = usingVector.option(Reg(new VConfig)) val reg_vstart = usingVector.option(Reg(UInt(maxVLMax.log2.W))) val reg_vxsat = usingVector.option(Reg(Bool())) val reg_vxrm = usingVector.option(Reg(UInt(io.vector.get.vxrm.getWidth.W))) val reg_mtinst_read_pseudo = Reg(Bool()) val reg_htinst_read_pseudo = Reg(Bool()) // XLEN=32: 0x00002000 // XLEN=64: 0x00003000 val Seq(read_mtinst, read_htinst) = Seq(reg_mtinst_read_pseudo, reg_htinst_read_pseudo).map(r => Cat(r, (xLen == 32).option(0.U).getOrElse(r), 0.U(12.W))) val reg_mcountinhibit = RegInit(0.U((CSR.firstHPM + nPerfCounters).W)) io.inhibit_cycle := reg_mcountinhibit(0) val reg_instret = WideCounter(64, io.retire, inhibit = reg_mcountinhibit(2)) val reg_cycle = if (enableCommitLog) WideCounter(64, io.retire, inhibit = reg_mcountinhibit(0)) else withClock(io.ungated_clock) { WideCounter(64, !io.csr_stall, inhibit = reg_mcountinhibit(0)) } val reg_hpmevent = io.counters.map(c => RegInit(0.U(xLen.W))) (io.counters zip reg_hpmevent) foreach { case (c, e) => c.eventSel := e } val reg_hpmcounter = io.counters.zipWithIndex.map { case (c, i) => WideCounter(CSR.hpmWidth, c.inc, reset = false, inhibit = reg_mcountinhibit(CSR.firstHPM+i)) } val mip = WireDefault(reg_mip) mip.lip := (io.interrupts.lip: Seq[Bool]) mip.mtip := io.interrupts.mtip mip.msip := io.interrupts.msip mip.meip := io.interrupts.meip // seip is the OR of reg_mip.seip and the actual line from the PLIC io.interrupts.seip.foreach { mip.seip := reg_mip.seip \|\| _ } // Simimlar sort of thing would apply if the PLIC had a VSEIP line: //io.interrupts.vseip.foreach { mip.vseip := reg_mip.vseip \|\| _ } mip.rocc := io.rocc_interrupt val read_mip = mip.asUInt & supported_interrupts val read_hip = read_mip & hs_delegable_interrupts val high_interrupts = (if (usingNMI) 0.U else io.interrupts.buserror.map(_ << CSR.busErrorIntCause).getOrElse(0.U)) val pending_interrupts = high_interrupts \| (read_mip & reg_mie) val d_interrupts = io.interrupts.debug << CSR.debugIntCause val (nmi_interrupts, nmiFlag) = io.interrupts.nmi.map(nmi => (((nmi.rnmi && reg_rnmie) << CSR.rnmiIntCause) \| io.interrupts.buserror.map(_ << CSR.rnmiBEUCause).getOrElse(0.U), !io.interrupts.debug && nmi.rnmi && reg_rnmie)).getOrElse(0.U, false.B) val m_interrupts = Mux(nmie && (reg_mstatus.prv <= PRV.S.U \|\| reg_mstatus.mie), ~(~pending_interrupts \| read_mideleg), 0.U) val s_interrupts = Mux(nmie && (reg_mstatus.v \|\| reg_mstatus.prv < PRV.S.U \|\| (reg_mstatus.prv === PRV.S.U && reg_mstatus.sie)), pending_interrupts & read_mideleg & ~read_hideleg, 0.U) val vs_interrupts = Mux(nmie && (reg_mstatus.v && (reg_mstatus.prv < PRV.S.U \|\| reg_mstatus.prv === PRV.S.U && reg_vsstatus.sie)), pending_interrupts & read_hideleg, 0.U) val (anyInterrupt, whichInterrupt) = chooseInterrupt(Seq(vs_interrupts, s_interrupts, m_interrupts, nmi_interrupts, d_interrupts)) val interruptMSB = BigInt(1) << (xLen-1) val interruptCause = interruptMSB.U + (nmiFlag << (xLen-2)) + whichInterrupt io.interrupt := (anyInterrupt && !io.singleStep \|\| reg_singleStepped) && !(reg_debug \|\| io.status.cease) io.interrupt_cause := interruptCause io.bp := reg_bp take nBreakpoints io.mcontext := reg_mcontext.getOrElse(0.U) io.scontext := reg_scontext.getOrElse(0.U) io.fiom := (reg_mstatus.prv < PRV.M.U && reg_menvcfg.fiom) \|\| (reg_mstatus.prv < PRV.S.U && reg_senvcfg.fiom) \|\| (reg_mstatus.v && reg_henvcfg.fiom) io.pmp := reg_pmp.map(PMP(_)) val isaMaskString = (if (usingMulDiv) "M" else "") + (if (usingAtomics) "A" else "") + (if (fLen >= 32) "F" else "") + (if (fLen >= 64) "D" else "") + (if (coreParams.hasV) "V" else "") + (if (usingCompressed) "C" else "") val isaString = (if (coreParams.useRVE) "E" else "I") + isaMaskString + (if (customIsaExt.isDefined \|\| usingRoCC) "X" else "") + (if (usingSupervisor) "S" else "") + (if (usingHypervisor) "H" else "") + (if (usingUser) "U" else "") val isaMax = (BigInt(log2Ceil(xLen) - 4) << (xLen-2)) \| isaStringToMask(isaString) val reg_misa = RegInit(isaMax.U) val read_mstatus = io.status.asUInt.extract(xLen-1,0) val read_mtvec = formTVec(reg_mtvec).padTo(xLen) val read_stvec = formTVec(reg_stvec).sextTo(xLen) val read_mapping = LinkedHashMap[Int,Bits]( CSRs.tselect -> reg_tselect, CSRs.tdata1 -> reg_bp(reg_tselect).control.asUInt, CSRs.tdata2 -> reg_bp(reg_tselect).address.sextTo(xLen), CSRs.tdata3 -> reg_bp(reg_tselect).textra.asUInt, CSRs.misa -> reg_misa, CSRs.mstatus -> read_mstatus, CSRs.mtvec -> read_mtvec, CSRs.mip -> read_mip, CSRs.mie -> reg_mie, CSRs.mscratch -> reg_mscratch, CSRs.mepc -> readEPC(reg_mepc).sextTo(xLen), CSRs.mtval -> reg_mtval.sextTo(xLen), CSRs.mcause -> reg_mcause, CSRs.mhartid -> io.hartid) val debug_csrs = if (!usingDebug) LinkedHashMap() else LinkedHashMap[Int,Bits]( CSRs.dcsr -> reg_dcsr.asUInt, CSRs.dpc -> readEPC(reg_dpc).sextTo(xLen), CSRs.dscratch0 -> reg_dscratch0.asUInt) ++ reg_dscratch1.map(r => CSRs.dscratch1 -> r) val read_mnstatus = WireInit(0.U.asTypeOf(new MNStatus())) read_mnstatus.mpp := reg_mnstatus.mpp read_mnstatus.mpv := reg_mnstatus.mpv read_mnstatus.mie := reg_rnmie val nmi_csrs = if (!usingNMI) LinkedHashMap() else LinkedHashMap[Int,Bits]( CustomCSRs.mnscratch -> reg_mnscratch, CustomCSRs.mnepc -> readEPC(reg_mnepc).sextTo(xLen), CustomCSRs.mncause -> reg_mncause, CustomCSRs.mnstatus -> read_mnstatus.asUInt) val context_csrs = LinkedHashMap[Int,Bits]() ++ reg_mcontext.map(r => CSRs.mcontext -> r) ++ reg_scontext.map(r => CSRs.scontext -> r) val read_fcsr = Cat(reg_frm, reg_fflags) val fp_csrs = LinkedHashMap[Int,Bits]() ++ usingFPU.option(CSRs.fflags -> reg_fflags) ++ usingFPU.option(CSRs.frm -> reg_frm) ++ (usingFPU \|\| usingVector).option(CSRs.fcsr -> read_fcsr) val read_vcsr = Cat(reg_vxrm.getOrElse(0.U), reg_vxsat.getOrElse(0.U)) val vector_csrs = if (!usingVector) LinkedHashMap() else LinkedHashMap[Int,Bits]( CSRs.vxsat -> reg_vxsat.get, CSRs.vxrm -> reg_vxrm.get, CSRs.vcsr -> read_vcsr, CSRs.vstart -> reg_vstart.get, CSRs.vtype -> reg_vconfig.get.vtype.asUInt, CSRs.vl -> reg_vconfig.get.vl, CSRs.vlenb -> (vLen / 8).U) read_mapping ++= debug_csrs read_mapping ++= nmi_csrs read_mapping ++= context_csrs read_mapping ++= fp_csrs read_mapping ++= vector_csrs if (coreParams.haveBasicCounters) { read_mapping += CSRs.mcountinhibit -> reg_mcountinhibit read_mapping += CSRs.mcycle -> reg_cycle read_mapping += CSRs.minstret -> reg_instret for (((e, c), i) <- (reg_hpmevent.padTo(CSR.nHPM, 0.U) zip reg_hpmcounter.map(x => x: UInt).padTo(CSR.nHPM, 0.U)).zipWithIndex) { read_mapping += (i + CSR.firstHPE) -> e // mhpmeventN read_mapping += (i + CSR.firstMHPC) -> c // mhpmcounterN read_mapping += (i + CSR.firstHPC) -> c // hpmcounterN if (xLen == 32) { read_mapping += (i + CSR.firstMHPCH) -> (c >> 32) // mhpmcounterNh read_mapping += (i + CSR.firstHPCH) -> (c >> 32) // hpmcounterNh } } if (usingUser) { read_mapping += CSRs.mcounteren -> read_mcounteren } read_mapping += CSRs.cycle -> reg_cycle read_mapping += CSRs.instret -> reg_instret if (xLen == 32) { read_mapping += CSRs.mcycleh -> (reg_cycle >> 32) read_mapping += CSRs.minstreth -> (reg_instret >> 32) read_mapping += CSRs.cycleh -> (reg_cycle >> 32) read_mapping += CSRs.instreth -> (reg_instret >> 32) } } if (usingUser) { read_mapping += CSRs.menvcfg -> reg_menvcfg.asUInt if (xLen == 32) read_mapping += CSRs.menvcfgh -> (reg_menvcfg.asUInt >> 32) } val sie_mask = { val sgeip_mask = WireInit(0.U.asTypeOf(new MIP)) sgeip_mask.sgeip := true.B read_mideleg & ~(hs_delegable_interrupts \| sgeip_mask.asUInt) } if (usingSupervisor) { val read_sie = reg_mie & sie_mask val read_sip = read_mip & sie_mask val read_sstatus = WireDefault(0.U.asTypeOf(new MStatus)) read_sstatus.sd := io.status.sd read_sstatus.uxl := io.status.uxl read_sstatus.sd_rv32 := io.status.sd_rv32 read_sstatus.mxr := io.status.mxr read_sstatus.sum := io.status.sum read_sstatus.xs := io.status.xs read_sstatus.fs := io.status.fs read_sstatus.vs := io.status.vs read_sstatus.spp := io.status.spp read_sstatus.spie := io.status.spie read_sstatus.sie := io.status.sie read_mapping += CSRs.sstatus -> (read_sstatus.asUInt)(xLen-1,0) read_mapping += CSRs.sip -> read_sip.asUInt read_mapping += CSRs.sie -> read_sie.asUInt read_mapping += CSRs.sscratch -> reg_sscratch read_mapping += CSRs.scause -> reg_scause read_mapping += CSRs.stval -> reg_stval.sextTo(xLen) read_mapping += CSRs.satp -> reg_satp.asUInt read_mapping += CSRs.sepc -> readEPC(reg_sepc).sextTo(xLen) read_mapping += CSRs.stvec -> read_stvec read_mapping += CSRs.scounteren -> read_scounteren read_mapping += CSRs.mideleg -> read_mideleg read_mapping += CSRs.medeleg -> read_medeleg read_mapping += CSRs.senvcfg -> reg_senvcfg.asUInt } val pmpCfgPerCSR = xLen / new PMPConfig().getWidth def pmpCfgIndex(i: Int) = (xLen / 32) * (i / pmpCfgPerCSR) if (reg_pmp.nonEmpty) { require(reg_pmp.size <= CSR.maxPMPs) val read_pmp = reg_pmp.padTo(CSR.maxPMPs, 0.U.asTypeOf(new PMP)) for (i <- 0 until read_pmp.size by pmpCfgPerCSR) read_mapping += (CSRs.pmpcfg0 + pmpCfgIndex(i)) -> read_pmp.map(_.cfg).slice(i, i + pmpCfgPerCSR).asUInt for ((pmp, i) <- read_pmp.zipWithIndex) read_mapping += (CSRs.pmpaddr0 + i) -> pmp.readAddr } // implementation-defined CSRs def generateCustomCSR(csr: CustomCSR, csr_io: CustomCSRIO) = { require(csr.mask >= 0 && csr.mask.bitLength <= xLen) require(!read_mapping.contains(csr.id)) val reg = csr.init.map(init => RegInit(init.U(xLen.W))).getOrElse(Reg(UInt(xLen.W))) val read = io.rw.cmd =/= CSR.N && io.rw.addr === csr.id.U csr_io.ren := read when (read && csr_io.stall) { io.rw_stall := true.B } read_mapping += csr.id -> reg reg } val reg_custom = customCSRs.zip(io.customCSRs).map(t => generateCustomCSR(t._1, t._2)) val reg_rocc = roccCSRs.zip(io.roccCSRs).map(t => generateCustomCSR(t._1, t._2)) if (usingHypervisor) { read_mapping += CSRs.mtinst -> read_mtinst read_mapping += CSRs.mtval2 -> reg_mtval2 val read_hstatus = io.hstatus.asUInt.extract(xLen-1,0) read_mapping += CSRs.hstatus -> read_hstatus read_mapping += CSRs.hedeleg -> read_hedeleg read_mapping += CSRs.hideleg -> read_hideleg read_mapping += CSRs.hcounteren-> read_hcounteren read_mapping += CSRs.hgatp -> reg_hgatp.asUInt read_mapping += CSRs.hip -> read_hip read_mapping += CSRs.hie -> read_hie read_mapping += CSRs.hvip -> read_hvip read_mapping += CSRs.hgeie -> 0.U read_mapping += CSRs.hgeip -> 0.U read_mapping += CSRs.htval -> reg_htval read_mapping += CSRs.htinst -> read_htinst read_mapping += CSRs.henvcfg -> reg_henvcfg.asUInt if (xLen == 32) read_mapping += CSRs.henvcfgh -> (reg_henvcfg.asUInt >> 32) val read_vsie = (read_hie & read_hideleg) >> 1 val read_vsip = (read_hip & read_hideleg) >> 1 val read_vsepc = readEPC(reg_vsepc).sextTo(xLen) val read_vstval = reg_vstval.sextTo(xLen) val read_vsstatus = io.gstatus.asUInt.extract(xLen-1,0) read_mapping += CSRs.vsstatus -> read_vsstatus read_mapping += CSRs.vsip -> read_vsip read_mapping += CSRs.vsie -> read_vsie read_mapping += CSRs.vsscratch -> reg_vsscratch read_mapping += CSRs.vscause -> reg_vscause read_mapping += CSRs.vstval -> read_vstval read_mapping += CSRs.vsatp -> reg_vsatp.asUInt read_mapping += CSRs.vsepc -> read_vsepc read_mapping += CSRs.vstvec -> read_vstvec } // mimpid, marchid, mvendorid, and mconfigptr are 0 unless overridden by customCSRs Seq(CSRs.mimpid, CSRs.marchid, CSRs.mvendorid, CSRs.mconfigptr).foreach(id => read_mapping.getOrElseUpdate(id, 0.U)) val decoded_addr = { val addr = Cat(io.status.v, io.rw.addr) val pats = for (((k, _), i) <- read_mapping.zipWithIndex) yield (BitPat(k.U), (0 until read_mapping.size).map(j => BitPat((i == j).B))) val decoded = DecodeLogic(addr, Seq.fill(read_mapping.size)(X), pats) val unvirtualized_mapping = (for (((k, _), v) <- read_mapping zip decoded) yield k -> v.asBool).toMap for ((k, v) <- unvirtualized_mapping) yield k -> { val alt: Option[Bool] = CSR.mode(k) match { // hcontext was assigned an unfortunate address; it lives where a // hypothetical vscontext will live. Exclude them from the S/VS remapping. // (on separate lines so scala-lint doesnt do something stupid) case _ if k == CSRs.scontext => None case _ if k == CSRs.hcontext => None // When V=1, if a corresponding VS CSR exists, access it instead... case PRV.H => unvirtualized_mapping.lift(k - (1 << CSR.modeLSB)) // ...and don't access the original S-mode version. case PRV.S => unvirtualized_mapping.contains(k + (1 << CSR.modeLSB)).option(false.B) case _ => None } alt.map(Mux(reg_mstatus.v, _, v)).getOrElse(v) } } val wdata = readModifyWriteCSR(io.rw.cmd, io.rw.rdata, io.rw.wdata) val system_insn = io.rw.cmd === CSR.I val hlsv = Seq(HLV_B, HLV_BU, HLV_H, HLV_HU, HLV_W, HLV_WU, HLV_D, HSV_B, HSV_H, HSV_W, HSV_D, HLVX_HU, HLVX_WU) val decode_table = Seq( ECALL-> List(Y,N,N,N,N,N,N,N,N), EBREAK-> List(N,Y,N,N,N,N,N,N,N), MRET-> List(N,N,Y,N,N,N,N,N,N), CEASE-> List(N,N,N,Y,N,N,N,N,N), WFI-> List(N,N,N,N,Y,N,N,N,N)) ++ usingDebug.option( DRET-> List(N,N,Y,N,N,N,N,N,N)) ++ usingNMI.option( MNRET-> List(N,N,Y,N,N,N,N,N,N)) ++ coreParams.haveCFlush.option(CFLUSH_D_L1-> List(N,N,N,N,N,N,N,N,N)) ++ usingSupervisor.option( SRET-> List(N,N,Y,N,N,N,N,N,N)) ++ usingVM.option( SFENCE_VMA-> List(N,N,N,N,N,Y,N,N,N)) ++ usingHypervisor.option( HFENCE_VVMA-> List(N,N,N,N,N,N,Y,N,N)) ++ usingHypervisor.option( HFENCE_GVMA-> List(N,N,N,N,N,N,N,Y,N)) ++ (if (usingHypervisor) hlsv.map(_-> List(N,N,N,N,N,N,N,N,Y)) else Seq()) val insn_call :: insn_break :: insn_ret :: insn_cease :: insn_wfi :: _ :: _ :: _ :: _ :: Nil = { val insn = ECALL.value.U \| (io.rw.addr << 20) DecodeLogic(insn, decode_table(0)._2.map(x=>X), decode_table).map(system_insn && _.asBool) } for (io_dec <- io.decode) { val addr = io_dec.inst(31, 20) def decodeAny(m: LinkedHashMap[Int,Bits]): Bool = m.map { case(k: Int, _: Bits) => addr === k.U }.reduce(_\|\|_) def decodeFast(s: Seq[Int]): Bool = DecodeLogic(addr, s.map(_.U), (read_mapping -- s).keys.toList.map(_.U)) val _ :: is_break :: is_ret :: _ :: is_wfi :: is_sfence :: is_hfence_vvma :: is_hfence_gvma :: is_hlsv :: Nil = DecodeLogic(io_dec.inst, decode_table(0)._2.map(x=>X), decode_table).map(_.asBool) val is_counter = (addr.inRange(CSR.firstCtr.U, (CSR.firstCtr + CSR.nCtr).U) \|\| addr.inRange(CSR.firstCtrH.U, (CSR.firstCtrH + CSR.nCtr).U)) val allow_wfi = (!usingSupervisor).B \|\| reg_mstatus.prv > PRV.S.U \|\| !reg_mstatus.tw && (!reg_mstatus.v \|\| !reg_hstatus.vtw) val allow_sfence_vma = (!usingVM).B \|\| reg_mstatus.prv > PRV.S.U \|\| !Mux(reg_mstatus.v, reg_hstatus.vtvm, reg_mstatus.tvm) val allow_hfence_vvma = (!usingHypervisor).B \|\| !reg_mstatus.v && (reg_mstatus.prv >= PRV.S.U) val allow_hlsv = (!usingHypervisor).B \|\| !reg_mstatus.v && (reg_mstatus.prv >= PRV.S.U \|\| reg_hstatus.hu) val allow_sret = (!usingSupervisor).B \|\| reg_mstatus.prv > PRV.S.U \|\| !Mux(reg_mstatus.v, reg_hstatus.vtsr, reg_mstatus.tsr) val counter_addr = addr(log2Ceil(read_mcounteren.getWidth)-1, 0) val allow_counter = (reg_mstatus.prv > PRV.S.U \|\| read_mcounteren(counter_addr)) && (!usingSupervisor.B \|\| reg_mstatus.prv >= PRV.S.U \|\| read_scounteren(counter_addr)) && (!usingHypervisor.B \|\| !reg_mstatus.v \|\| read_hcounteren(counter_addr)) io_dec.fp_illegal := io.status.fs === 0.U \|\| reg_mstatus.v && reg_vsstatus.fs === 0.U \|\| !reg_misa('f'-'a') io_dec.vector_illegal := io.status.vs === 0.U \|\| reg_mstatus.v && reg_vsstatus.vs === 0.U \|\| !reg_misa('v'-'a') io_dec.fp_csr := decodeFast(fp_csrs.keys.toList) io_dec.vector_csr := decodeFast(vector_csrs.keys.toList) io_dec.rocc_illegal := io.status.xs === 0.U \|\| reg_mstatus.v && reg_vsstatus.xs === 0.U \|\| !reg_misa('x'-'a') val csr_addr_legal = reg_mstatus.prv >= CSR.mode(addr) \|\| usingHypervisor.B && !reg_mstatus.v && reg_mstatus.prv === PRV.S.U && CSR.mode(addr) === PRV.H.U val csr_exists = decodeAny(read_mapping) io_dec.read_illegal := !csr_addr_legal \|\| !csr_exists \|\| ((addr === CSRs.satp.U \|\| addr === CSRs.hgatp.U) && !allow_sfence_vma) \|\| is_counter && !allow_counter \|\| decodeFast(debug_csrs.keys.toList) && !reg_debug \|\| decodeFast(vector_csrs.keys.toList) && io_dec.vector_illegal \|\| io_dec.fp_csr && io_dec.fp_illegal io_dec.write_illegal := addr(11,10).andR io_dec.write_flush := { val addr_m = addr \| (PRV.M.U << CSR.modeLSB) !(addr_m >= CSRs.mscratch.U && addr_m <= CSRs.mtval.U) } io_dec.system_illegal := !csr_addr_legal && !is_hlsv \|\| is_wfi && !allow_wfi \|\| is_ret && !allow_sret \|\| is_ret && addr(10) && addr(7) && !reg_debug \|\| (is_sfence \|\| is_hfence_gvma) && !allow_sfence_vma \|\| is_hfence_vvma && !allow_hfence_vvma \|\| is_hlsv && !allow_hlsv io_dec.virtual_access_illegal := reg_mstatus.v && csr_exists && ( CSR.mode(addr) === PRV.H.U \|\| is_counter && read_mcounteren(counter_addr) && (!read_hcounteren(counter_addr) \|\| !reg_mstatus.prv(0) && !read_scounteren(counter_addr)) \|\| CSR.mode(addr) === PRV.S.U && !reg_mstatus.prv(0) \|\| addr === CSRs.satp.U && reg_mstatus.prv(0) && reg_hstatus.vtvm) io_dec.virtual_system_illegal := reg_mstatus.v && ( is_hfence_vvma \|\| is_hfence_gvma \|\| is_hlsv \|\| is_wfi && (!reg_mstatus.prv(0) \|\| !reg_mstatus.tw && reg_hstatus.vtw) \|\| is_ret && CSR.mode(addr) === PRV.S.U && (!reg_mstatus.prv(0) \|\| reg_hstatus.vtsr) \|\| is_sfence && (!reg_mstatus.prv(0) \|\| reg_hstatus.vtvm)) } val cause = Mux(insn_call, Causes.user_ecall.U + Mux(reg_mstatus.prv(0) && reg_mstatus.v, PRV.H.U, reg_mstatus.prv), Mux[UInt](insn_break, Causes.breakpoint.U, io.cause)) val cause_lsbs = cause(log2Ceil(1 + CSR.busErrorIntCause)-1, 0) val cause_deleg_lsbs = cause(log2Ceil(xLen)-1,0) val causeIsDebugInt = cause(xLen-1) && cause_lsbs === CSR.debugIntCause.U val causeIsDebugTrigger = !cause(xLen-1) && cause_lsbs === CSR.debugTriggerCause.U val causeIsDebugBreak = !cause(xLen-1) && insn_break && Cat(reg_dcsr.ebreakm, reg_dcsr.ebreakh, reg_dcsr.ebreaks, reg_dcsr.ebreaku)(reg_mstatus.prv) val trapToDebug = usingDebug.B && (reg_singleStepped \|\| causeIsDebugInt \|\| causeIsDebugTrigger \|\| causeIsDebugBreak \|\| reg_debug) val debugEntry = p(DebugModuleKey).map(_.debugEntry).getOrElse(BigInt(0x800)) val debugException = p(DebugModuleKey).map(_.debugException).getOrElse(BigInt(0x808)) val debugTVec = Mux(reg_debug, Mux(insn_break, debugEntry.U, debugException.U), debugEntry.U) val delegate = usingSupervisor.B && reg_mstatus.prv <= PRV.S.U && Mux(cause(xLen-1), read_mideleg(cause_deleg_lsbs), read_medeleg(cause_deleg_lsbs)) val delegateVS = reg_mstatus.v && delegate && Mux(cause(xLen-1), read_hideleg(cause_deleg_lsbs), read_hedeleg(cause_deleg_lsbs)) def mtvecBaseAlign = 2 def mtvecInterruptAlign = { require(reg_mip.getWidth <= xLen) log2Ceil(xLen) } val notDebugTVec = { val base = Mux(delegate, Mux(delegateVS, read_vstvec, read_stvec), read_mtvec) val interruptOffset = cause(mtvecInterruptAlign-1, 0) << mtvecBaseAlign val interruptVec = Cat(base >> (mtvecInterruptAlign + mtvecBaseAlign), interruptOffset) val doVector = base(0) && cause(cause.getWidth-1) && (cause_lsbs >> mtvecInterruptAlign) === 0.U Mux(doVector, interruptVec, base >> mtvecBaseAlign << mtvecBaseAlign) } val causeIsRnmiInt = cause(xLen-1) && cause(xLen-2) && (cause_lsbs === CSR.rnmiIntCause.U \|\| cause_lsbs === CSR.rnmiBEUCause.U) val causeIsRnmiBEU = cause(xLen-1) && cause(xLen-2) && cause_lsbs === CSR.rnmiBEUCause.U val causeIsNmi = causeIsRnmiInt val nmiTVecInt = io.interrupts.nmi.map(nmi => nmi.rnmi_interrupt_vector).getOrElse(0.U) val nmiTVecXcpt = io.interrupts.nmi.map(nmi => nmi.rnmi_exception_vector).getOrElse(0.U) val trapToNmiInt = usingNMI.B && causeIsNmi val trapToNmiXcpt = usingNMI.B && !nmie val trapToNmi = trapToNmiInt \|\| trapToNmiXcpt val nmiTVec = (Mux(causeIsNmi, nmiTVecInt, nmiTVecXcpt)>>1)<<1 val tvec = Mux(trapToDebug, debugTVec, Mux(trapToNmi, nmiTVec, notDebugTVec)) io.evec := tvec io.ptbr := reg_satp io.hgatp := reg_hgatp io.vsatp := reg_vsatp io.eret := insn_call \|\| insn_break \|\| insn_ret io.singleStep := reg_dcsr.step && !reg_debug io.status := reg_mstatus io.status.sd := io.status.fs.andR \|\| io.status.xs.andR \|\| io.status.vs.andR io.status.debug := reg_debug io.status.isa := reg_misa io.status.uxl := (if (usingUser) log2Ceil(xLen) - 4 else 0).U io.status.sxl := (if (usingSupervisor) log2Ceil(xLen) - 4 else 0).U io.status.dprv := Mux(reg_mstatus.mprv && !reg_debug, reg_mstatus.mpp, reg_mstatus.prv) io.status.dv := reg_mstatus.v \|\| Mux(reg_mstatus.mprv && !reg_debug, reg_mstatus.mpv, false.B) io.status.sd_rv32 := (xLen == 32).B && io.status.sd io.status.mpv := reg_mstatus.mpv io.status.gva := reg_mstatus.gva io.hstatus := reg_hstatus io.hstatus.vsxl := (if (usingSupervisor) log2Ceil(xLen) - 4 else 0).U io.gstatus := reg_vsstatus io.gstatus.sd := io.gstatus.fs.andR \|\| io.gstatus.xs.andR \|\| io.gstatus.vs.andR io.gstatus.uxl := (if (usingUser) log2Ceil(xLen) - 4 else 0).U io.gstatus.sd_rv32 := (xLen == 32).B && io.gstatus.sd val exception = insn_call \|\| insn_break \|\| io.exception assert(PopCount(insn_ret :: insn_call :: insn_break :: io.exception :: Nil) <= 1.U, "these conditions must be mutually exclusive") when (insn_wfi && !io.singleStep && !reg_debug) { reg_wfi := true.B } when (pending_interrupts.orR \|\| io.interrupts.debug \|\| exception) { reg_wfi := false.B } io.interrupts.nmi.map(nmi => when (nmi.rnmi) { reg_wfi := false.B } ) when (io.retire(0) \|\| exception) { reg_singleStepped := true.B } when (!io.singleStep) { reg_singleStepped := false.B } assert(!io.singleStep \|\| io.retire <= 1.U) assert(!reg_singleStepped \|\| io.retire === 0.U) val epc = formEPC(io.pc) val tval = Mux(insn_break, epc, io.tval) when (exception) { when (trapToDebug) { when (!reg_debug) { reg_mstatus.v := false.B reg_debug := true.B reg_dpc := epc reg_dcsr.cause := Mux(reg_singleStepped, 4.U, Mux(causeIsDebugInt, 3.U, Mux[UInt](causeIsDebugTrigger, 2.U, 1.U))) reg_dcsr.prv := trimPrivilege(reg_mstatus.prv) reg_dcsr.v := reg_mstatus.v new_prv := PRV.M.U } }.elsewhen (trapToNmiInt) { when (reg_rnmie) { reg_mstatus.v := false.B reg_mnstatus.mpv := reg_mstatus.v reg_rnmie := false.B reg_mnepc := epc reg_mncause := (BigInt(1) << (xLen-1)).U \| Mux(causeIsRnmiBEU, 3.U, 2.U) reg_mnstatus.mpp := trimPrivilege(reg_mstatus.prv) new_prv := PRV.M.U } }.elsewhen (delegateVS && nmie) { reg_mstatus.v := true.B reg_vsstatus.spp := reg_mstatus.prv reg_vsepc := epc reg_vscause := Mux(cause(xLen-1), Cat(cause(xLen-1, 2), 1.U(2.W)), cause) reg_vstval := tval reg_vsstatus.spie := reg_vsstatus.sie reg_vsstatus.sie := false.B new_prv := PRV.S.U }.elsewhen (delegate && nmie) { reg_mstatus.v := false.B reg_hstatus.spvp := Mux(reg_mstatus.v, reg_mstatus.prv(0),reg_hstatus.spvp) reg_hstatus.gva := io.gva reg_hstatus.spv := reg_mstatus.v reg_sepc := epc reg_scause := cause reg_stval := tval reg_htval := io.htval reg_htinst_read_pseudo := io.mhtinst_read_pseudo reg_mstatus.spie := reg_mstatus.sie reg_mstatus.spp := reg_mstatus.prv reg_mstatus.sie := false.B new_prv := PRV.S.U }.otherwise { reg_mstatus.v := false.B reg_mstatus.mpv := reg_mstatus.v reg_mstatus.gva := io.gva reg_mepc := epc reg_mcause := cause reg_mtval := tval reg_mtval2 := io.htval reg_mtinst_read_pseudo := io.mhtinst_read_pseudo reg_mstatus.mpie := reg_mstatus.mie reg_mstatus.mpp := trimPrivilege(reg_mstatus.prv) reg_mstatus.mie := false.B new_prv := PRV.M.U } } for (i <- 0 until supported_interrupts.getWidth) { val en = exception && (supported_interrupts & (BigInt(1) << i).U) =/= 0.U && cause === (BigInt(1) << (xLen - 1)).U + i.U val delegable = (delegable_interrupts & (BigInt(1) << i).U) =/= 0.U property.cover(en && !delegate, s"INTERRUPT_M_$i") property.cover(en && delegable && delegate, s"INTERRUPT_S_$i") } for (i <- 0 until xLen) { val supported_exceptions: BigInt = 0x8fe \| (if (usingCompressed && !coreParams.misaWritable) 0 else 1) \| (if (usingUser) 0x100 else 0) \| (if (usingSupervisor) 0x200 else 0) \| (if (usingVM) 0xb000 else 0) if (((supported_exceptions >> i) & 1) != 0) { val en = exception && cause === i.U val delegable = (delegable_exceptions & (BigInt(1) << i).U) =/= 0.U property.cover(en && !delegate, s"EXCEPTION_M_$i") property.cover(en && delegable && delegate, s"EXCEPTION_S_$i") } } when (insn_ret) { val ret_prv = WireInit(UInt(), DontCare) when (usingSupervisor.B && !io.rw.addr(9)) { when (!reg_mstatus.v) { reg_mstatus.sie := reg_mstatus.spie reg_mstatus.spie := true.B reg_mstatus.spp := PRV.U.U ret_prv := reg_mstatus.spp reg_mstatus.v := usingHypervisor.B && reg_hstatus.spv io.evec := readEPC(reg_sepc) reg_hstatus.spv := false.B }.otherwise { reg_vsstatus.sie := reg_vsstatus.spie reg_vsstatus.spie := true.B reg_vsstatus.spp := PRV.U.U ret_prv := reg_vsstatus.spp reg_mstatus.v := usingHypervisor.B io.evec := readEPC(reg_vsepc) } }.elsewhen (usingDebug.B && io.rw.addr(10) && io.rw.addr(7)) { ret_prv := reg_dcsr.prv reg_mstatus.v := usingHypervisor.B && reg_dcsr.v && reg_dcsr.prv <= PRV.S.U reg_debug := false.B io.evec := readEPC(reg_dpc) }.elsewhen (usingNMI.B && io.rw.addr(10) && !io.rw.addr(7)) { ret_prv := reg_mnstatus.mpp reg_mstatus.v := usingHypervisor.B && reg_mnstatus.mpv && reg_mnstatus.mpp <= PRV.S.U reg_rnmie := true.B io.evec := readEPC(reg_mnepc) }.otherwise { reg_mstatus.mie := reg_mstatus.mpie reg_mstatus.mpie := true.B reg_mstatus.mpp := legalizePrivilege(PRV.U.U) reg_mstatus.mpv := false.B ret_prv := reg_mstatus.mpp reg_mstatus.v := usingHypervisor.B && reg_mstatus.mpv && reg_mstatus.mpp <= PRV.S.U io.evec := readEPC(reg_mepc) } new_prv := ret_prv when (usingUser.B && ret_prv <= PRV.S.U) { reg_mstatus.mprv := false.B } } io.time := reg_cycle io.csr_stall := reg_wfi \|\| io.status.cease io.status.cease := RegEnable(true.B, false.B, insn_cease) io.status.wfi := reg_wfi for ((io, reg) <- io.customCSRs zip reg_custom) { io.wen := false.B io.wdata := wdata io.value := reg } for ((io, reg) <- io.roccCSRs zip reg_rocc) { io.wen := false.B io.wdata := wdata io.value := reg } io.rw.rdata := Mux1H(for ((k, v) <- read_mapping) yield decoded_addr(k) -> v) // cover access to register val coverable_counters = read_mapping.filterNot { case (k, _) => k >= CSR.firstHPC + nPerfCounters && k < CSR.firstHPC + CSR.nHPM } coverable_counters.foreach( {case (k, v) => { when (!k.U(11,10).andR) { // Cover points for RW CSR registers property.cover(io.rw.cmd.isOneOf(CSR.W, CSR.S, CSR.C) && io.rw.addr===k.U, "CSR_access_"+k.toString, "Cover Accessing Core CSR field") } .otherwise { // Cover points for RO CSR registers property.cover(io.rw.cmd===CSR.R && io.rw.addr===k.U, "CSR_access_"+k.toString, "Cover Accessing Core CSR field") } }}) val set_vs_dirty = WireDefault(io.vector.map(_.set_vs_dirty).getOrElse(false.B)) io.vector.foreach { vio => when (set_vs_dirty) { assert(reg_mstatus.vs > 0.U) when (reg_mstatus.v) { reg_vsstatus.vs := 3.U } reg_mstatus.vs := 3.U } } val set_fs_dirty = WireDefault(io.set_fs_dirty.getOrElse(false.B)) if (coreParams.haveFSDirty) { when (set_fs_dirty) { assert(reg_mstatus.fs > 0.U) when (reg_mstatus.v) { reg_vsstatus.fs := 3.U } reg_mstatus.fs := 3.U } } io.fcsr_rm := reg_frm when (io.fcsr_flags.valid) { reg_fflags := reg_fflags \| io.fcsr_flags.bits set_fs_dirty := true.B } io.vector.foreach { vio => when (vio.set_vxsat) { reg_vxsat.get := true.B set_vs_dirty := true.B } } val csr_wen = io.rw.cmd.isOneOf(CSR.S, CSR.C, CSR.W) && !io.rw_stall io.csrw_counter := Mux(coreParams.haveBasicCounters.B && csr_wen && (io.rw.addr.inRange(CSRs.mcycle.U, (CSRs.mcycle + CSR.nCtr).U) \|\| io.rw.addr.inRange(CSRs.mcycleh.U, (CSRs.mcycleh + CSR.nCtr).U)), UIntToOH(io.rw.addr(log2Ceil(CSR.nCtr+nPerfCounters)-1, 0)), 0.U) when (csr_wen) { val scause_mask = ((BigInt(1) << (xLen-1)) + 31).U /* only implement 5 LSBs and MSB / val satp_valid_modes = 0 +: (minPgLevels to pgLevels).map(new PTBR().pgLevelsToMode(_)) when (decoded_addr(CSRs.mstatus)) { val new_mstatus = wdata.asTypeOf(new MStatus()) reg_mstatus.mie := new_mstatus.mie reg_mstatus.mpie := new_mstatus.mpie if (usingUser) { reg_mstatus.mprv := new_mstatus.mprv reg_mstatus.mpp := legalizePrivilege(new_mstatus.mpp) if (usingSupervisor) { reg_mstatus.spp := new_mstatus.spp reg_mstatus.spie := new_mstatus.spie reg_mstatus.sie := new_mstatus.sie reg_mstatus.tw := new_mstatus.tw reg_mstatus.tsr := new_mstatus.tsr } if (usingVM) { reg_mstatus.mxr := new_mstatus.mxr reg_mstatus.sum := new_mstatus.sum reg_mstatus.tvm := new_mstatus.tvm } if (usingHypervisor) { reg_mstatus.mpv := new_mstatus.mpv reg_mstatus.gva := new_mstatus.gva } } if (usingSupervisor \|\| usingFPU) reg_mstatus.fs := formFS(new_mstatus.fs) reg_mstatus.vs := formVS(new_mstatus.vs) } when (decoded_addr(CSRs.misa)) { val mask = isaStringToMask(isaMaskString).U(xLen.W) val f = wdata('f' - 'a') // suppress write if it would cause the next fetch to be misaligned when (!usingCompressed.B \|\| !io.pc(1) \|\| wdata('c' - 'a')) { if (coreParams.misaWritable) reg_misa := ~(~wdata \| (!f << ('d' - 'a'))) & mask \| reg_misa & ~mask } } when (decoded_addr(CSRs.mip)) { // MIP should be modified based on the value in reg_mip, not the value // in read_mip, since read_mip.seip is the OR of reg_mip.seip and // io.interrupts.seip. We don't want the value on the PLIC line to // inadvertently be OR'd into read_mip.seip. val new_mip = readModifyWriteCSR(io.rw.cmd, reg_mip.asUInt, io.rw.wdata).asTypeOf(new MIP) if (usingSupervisor) { reg_mip.ssip := new_mip.ssip reg_mip.stip := new_mip.stip reg_mip.seip := new_mip.seip } if (usingHypervisor) { reg_mip.vssip := new_mip.vssip } } when (decoded_addr(CSRs.mie)) { reg_mie := wdata & supported_interrupts } when (decoded_addr(CSRs.mepc)) { reg_mepc := formEPC(wdata) } when (decoded_addr(CSRs.mscratch)) { reg_mscratch := wdata } if (mtvecWritable) when (decoded_addr(CSRs.mtvec)) { reg_mtvec := wdata } when (decoded_addr(CSRs.mcause)) { reg_mcause := wdata & ((BigInt(1) << (xLen-1)) + (BigInt(1) << whichInterrupt.getWidth) - 1).U } when (decoded_addr(CSRs.mtval)) { reg_mtval := wdata } if (usingNMI) { val new_mnstatus = wdata.asTypeOf(new MNStatus()) when (decoded_addr(CustomCSRs.mnscratch)) { reg_mnscratch := wdata } when (decoded_addr(CustomCSRs.mnepc)) { reg_mnepc := formEPC(wdata) } when (decoded_addr(CustomCSRs.mncause)) { reg_mncause := wdata & ((BigInt(1) << (xLen-1)) + BigInt(3)).U } when (decoded_addr(CustomCSRs.mnstatus)) { reg_mnstatus.mpp := legalizePrivilege(new_mnstatus.mpp) reg_mnstatus.mpv := usingHypervisor.B && new_mnstatus.mpv reg_rnmie := reg_rnmie \| new_mnstatus.mie // mnie bit settable but not clearable from software } } for (((e, c), i) <- (reg_hpmevent zip reg_hpmcounter).zipWithIndex) { writeCounter(i + CSR.firstMHPC, c, wdata) when (decoded_addr(i + CSR.firstHPE)) { e := perfEventSets.maskEventSelector(wdata) } } if (coreParams.haveBasicCounters) { when (decoded_addr(CSRs.mcountinhibit)) { reg_mcountinhibit := wdata & ~2.U(xLen.W) } // mcountinhibit bit [1] is tied zero writeCounter(CSRs.mcycle, reg_cycle, wdata) writeCounter(CSRs.minstret, reg_instret, wdata) } if (usingFPU) { when (decoded_addr(CSRs.fflags)) { set_fs_dirty := true.B; reg_fflags := wdata } when (decoded_addr(CSRs.frm)) { set_fs_dirty := true.B; reg_frm := wdata } when (decoded_addr(CSRs.fcsr)) { set_fs_dirty := true.B reg_fflags := wdata reg_frm := wdata >> reg_fflags.getWidth } } if (usingDebug) { when (decoded_addr(CSRs.dcsr)) { val new_dcsr = wdata.asTypeOf(new DCSR()) reg_dcsr.step := new_dcsr.step reg_dcsr.ebreakm := new_dcsr.ebreakm if (usingSupervisor) reg_dcsr.ebreaks := new_dcsr.ebreaks if (usingUser) reg_dcsr.ebreaku := new_dcsr.ebreaku if (usingUser) reg_dcsr.prv := legalizePrivilege(new_dcsr.prv) if (usingHypervisor) reg_dcsr.v := new_dcsr.v } when (decoded_addr(CSRs.dpc)) { reg_dpc := formEPC(wdata) } when (decoded_addr(CSRs.dscratch0)) { reg_dscratch0 := wdata } reg_dscratch1.foreach { r => when (decoded_addr(CSRs.dscratch1)) { r := wdata } } } if (usingSupervisor) { when (decoded_addr(CSRs.sstatus)) { val new_sstatus = wdata.asTypeOf(new MStatus()) reg_mstatus.sie := new_sstatus.sie reg_mstatus.spie := new_sstatus.spie reg_mstatus.spp := new_sstatus.spp reg_mstatus.fs := formFS(new_sstatus.fs) reg_mstatus.vs := formVS(new_sstatus.vs) if (usingVM) { reg_mstatus.mxr := new_sstatus.mxr reg_mstatus.sum := new_sstatus.sum } } when (decoded_addr(CSRs.sip)) { val new_sip = ((read_mip & ~read_mideleg) \| (wdata & read_mideleg)).asTypeOf(new MIP()) reg_mip.ssip := new_sip.ssip } when (decoded_addr(CSRs.satp)) { if (usingVM) { val new_satp = wdata.asTypeOf(new PTBR()) when (new_satp.mode.isOneOf(satp_valid_modes.map(_.U))) { reg_satp.mode := new_satp.mode & satp_valid_modes.reduce(_\|_).U reg_satp.ppn := new_satp.ppn(ppnBits-1,0) if (asIdBits > 0) reg_satp.asid := new_satp.asid(asIdBits-1,0) } } } when (decoded_addr(CSRs.sie)) { reg_mie := (reg_mie & ~sie_mask) \| (wdata & sie_mask) } when (decoded_addr(CSRs.sscratch)) { reg_sscratch := wdata } when (decoded_addr(CSRs.sepc)) { reg_sepc := formEPC(wdata) } when (decoded_addr(CSRs.stvec)) { reg_stvec := wdata } when (decoded_addr(CSRs.scause)) { reg_scause := wdata & scause_mask } when (decoded_addr(CSRs.stval)) { reg_stval := wdata } when (decoded_addr(CSRs.mideleg)) { reg_mideleg := wdata } when (decoded_addr(CSRs.medeleg)) { reg_medeleg := wdata } when (decoded_addr(CSRs.scounteren)) { reg_scounteren := wdata } when (decoded_addr(CSRs.senvcfg)) { reg_senvcfg.write(wdata) } } if (usingHypervisor) { when (decoded_addr(CSRs.hstatus)) { val new_hstatus = wdata.asTypeOf(new HStatus()) reg_hstatus.gva := new_hstatus.gva reg_hstatus.spv := new_hstatus.spv reg_hstatus.spvp := new_hstatus.spvp reg_hstatus.hu := new_hstatus.hu reg_hstatus.vtvm := new_hstatus.vtvm reg_hstatus.vtw := new_hstatus.vtw reg_hstatus.vtsr := new_hstatus.vtsr reg_hstatus.vsxl := new_hstatus.vsxl } when (decoded_addr(CSRs.hideleg)) { reg_hideleg := wdata } when (decoded_addr(CSRs.hedeleg)) { reg_hedeleg := wdata } when (decoded_addr(CSRs.hgatp)) { val new_hgatp = wdata.asTypeOf(new PTBR()) val valid_modes = 0 +: (minPgLevels to pgLevels).map(new_hgatp.pgLevelsToMode(_)) when (new_hgatp.mode.isOneOf(valid_modes.map(_.U))) { reg_hgatp.mode := new_hgatp.mode & valid_modes.reduce(_\|_).U } reg_hgatp.ppn := Cat(new_hgatp.ppn(ppnBits-1,2), 0.U(2.W)) if (vmIdBits > 0) reg_hgatp.asid := new_hgatp.asid(vmIdBits-1,0) } when (decoded_addr(CSRs.hip)) { val new_hip = ((read_mip & ~hs_delegable_interrupts) \| (wdata & hs_delegable_interrupts)).asTypeOf(new MIP()) reg_mip.vssip := new_hip.vssip } when (decoded_addr(CSRs.hie)) { reg_mie := (reg_mie & ~hs_delegable_interrupts) \| (wdata & hs_delegable_interrupts) } when (decoded_addr(CSRs.hvip)) { val new_sip = ((read_mip & ~hs_delegable_interrupts) \| (wdata & hs_delegable_interrupts)).asTypeOf(new MIP()) reg_mip.vssip := new_sip.vssip reg_mip.vstip := new_sip.vstip reg_mip.vseip := new_sip.vseip } when (decoded_addr(CSRs.hcounteren)) { reg_hcounteren := wdata } when (decoded_addr(CSRs.htval)) { reg_htval := wdata } when (decoded_addr(CSRs.mtval2)) { reg_mtval2 := wdata } val write_mhtinst_read_pseudo = wdata(13) && (xLen == 32).option(true.B).getOrElse(wdata(12)) when(decoded_addr(CSRs.mtinst)) { reg_mtinst_read_pseudo := write_mhtinst_read_pseudo } when(decoded_addr(CSRs.htinst)) { reg_htinst_read_pseudo := write_mhtinst_read_pseudo } when (decoded_addr(CSRs.vsstatus)) { val new_vsstatus = wdata.asTypeOf(new MStatus()) reg_vsstatus.sie := new_vsstatus.sie reg_vsstatus.spie := new_vsstatus.spie reg_vsstatus.spp := new_vsstatus.spp reg_vsstatus.mxr := new_vsstatus.mxr reg_vsstatus.sum := new_vsstatus.sum reg_vsstatus.fs := formFS(new_vsstatus.fs) reg_vsstatus.vs := formVS(new_vsstatus.vs) } when (decoded_addr(CSRs.vsip)) { val new_vsip = ((read_hip & ~read_hideleg) \| ((wdata << 1) & read_hideleg)).asTypeOf(new MIP()) reg_mip.vssip := new_vsip.vssip } when (decoded_addr(CSRs.vsatp)) { val new_vsatp = wdata.asTypeOf(new PTBR()) val mode_ok = new_vsatp.mode.isOneOf(satp_valid_modes.map(_.U)) when (mode_ok) { reg_vsatp.mode := new_vsatp.mode & satp_valid_modes.reduce(_\|_).U } when (mode_ok \|\| !reg_mstatus.v) { reg_vsatp.ppn := new_vsatp.ppn(vpnBits.min(new_vsatp.ppn.getWidth)-1,0) if (asIdBits > 0) reg_vsatp.asid := new_vsatp.asid(asIdBits-1,0) } } when (decoded_addr(CSRs.vsie)) { reg_mie := (reg_mie & ~read_hideleg) \| ((wdata << 1) & read_hideleg) } when (decoded_addr(CSRs.vsscratch)) { reg_vsscratch := wdata } when (decoded_addr(CSRs.vsepc)) { reg_vsepc := formEPC(wdata) } when (decoded_addr(CSRs.vstvec)) { reg_vstvec := wdata } when (decoded_addr(CSRs.vscause)) { reg_vscause := wdata & scause_mask } when (decoded_addr(CSRs.vstval)) { reg_vstval := wdata } when (decoded_addr(CSRs.henvcfg)) { reg_henvcfg.write(wdata) } } if (usingUser) { when (decoded_addr(CSRs.mcounteren)) { reg_mcounteren := wdata } when (decoded_addr(CSRs.menvcfg)) { reg_menvcfg.write(wdata) } } if (nBreakpoints > 0) { when (decoded_addr(CSRs.tselect)) { reg_tselect := wdata } for ((bp, i) <- reg_bp.zipWithIndex) { when (i.U === reg_tselect && (!bp.control.dmode \|\| reg_debug)) { when (decoded_addr(CSRs.tdata2)) { bp.address := wdata } when (decoded_addr(CSRs.tdata3)) { if (coreParams.mcontextWidth > 0) { bp.textra.mselect := wdata(bp.textra.mselectPos) bp.textra.mvalue := wdata >> bp.textra.mvaluePos } if (coreParams.scontextWidth > 0) { bp.textra.sselect := wdata(bp.textra.sselectPos) bp.textra.svalue := wdata >> bp.textra.svaluePos } } when (decoded_addr(CSRs.tdata1)) { bp.control := wdata.asTypeOf(bp.control) val prevChain = if (i == 0) false.B else reg_bp(i-1).control.chain val prevDMode = if (i == 0) false.B else reg_bp(i-1).control.dmode val nextChain = if (i >= nBreakpoints-1) true.B else reg_bp(i+1).control.chain val nextDMode = if (i >= nBreakpoints-1) true.B else reg_bp(i+1).control.dmode val newBPC = readModifyWriteCSR(io.rw.cmd, bp.control.asUInt, io.rw.wdata).asTypeOf(bp.control) val dMode = newBPC.dmode && reg_debug && (prevDMode \|\| !prevChain) bp.control.dmode := dMode when (dMode \|\| (newBPC.action > 1.U)) { bp.control.action := newBPC.action }.otherwise { bp.control.action := 0.U } bp.control.chain := newBPC.chain && !(prevChain \|\| nextChain) && (dMode \|\| !nextDMode) } } } } reg_mcontext.foreach { r => when (decoded_addr(CSRs.mcontext)) { r := wdata }} reg_scontext.foreach { r => when (decoded_addr(CSRs.scontext)) { r := wdata }} if (reg_pmp.nonEmpty) for (((pmp, next), i) <- (reg_pmp zip (reg_pmp.tail :+ reg_pmp.last)).zipWithIndex) { require(xLen % pmp.cfg.getWidth == 0) when (decoded_addr(CSRs.pmpcfg0 + pmpCfgIndex(i)) && !pmp.cfgLocked) { val newCfg = (wdata >> ((i pmp.cfg.getWidth) % xLen)).asTypeOf(new PMPConfig()) pmp.cfg := newCfg // disallow unreadable but writable PMPs pmp.cfg.w := newCfg.w && newCfg.r // can't select a=NA4 with coarse-grained PMPs if (pmpGranularity.log2 > PMP.lgAlign) pmp.cfg.a := Cat(newCfg.a(1), newCfg.a.orR) } when (decoded_addr(CSRs.pmpaddr0 + i) && !pmp.addrLocked(next)) { pmp.addr := wdata } } def writeCustomCSR(io: CustomCSRIO, csr: CustomCSR, reg: UInt) = { val mask = csr.mask.U(xLen.W) when (decoded_addr(csr.id)) { reg := (wdata & mask) \| (reg & ~mask) io.wen := true.B } } for ((io, csr, reg) <- (io.customCSRs, customCSRs, reg_custom).zipped) { writeCustomCSR(io, csr, reg) } for ((io, csr, reg) <- (io.roccCSRs, roccCSRs, reg_rocc).zipped) { writeCustomCSR(io, csr, reg) } if (usingVector) { when (decoded_addr(CSRs.vstart)) { set_vs_dirty := true.B; reg_vstart.get := wdata } when (decoded_addr(CSRs.vxrm)) { set_vs_dirty := true.B; reg_vxrm.get := wdata } when (decoded_addr(CSRs.vxsat)) { set_vs_dirty := true.B; reg_vxsat.get := wdata } when (decoded_addr(CSRs.vcsr)) { set_vs_dirty := true.B reg_vxsat.get := wdata reg_vxrm.get := wdata >> 1 } } } def setCustomCSR(io: CustomCSRIO, csr: CustomCSR, reg: UInt) = { val mask = csr.mask.U(xLen.W) when (io.set) { reg := (io.sdata & mask) \| (reg & ~mask) } } for ((io, csr, reg) <- (io.customCSRs, customCSRs, reg_custom).zipped) { setCustomCSR(io, csr, reg) } for ((io, csr, reg) <- (io.roccCSRs, roccCSRs, reg_rocc).zipped) { setCustomCSR(io, csr, reg) } io.vector.map { vio => when (vio.set_vconfig.valid) { // user of CSRFile is responsible for set_vs_dirty in this case assert(vio.set_vconfig.bits.vl <= vio.set_vconfig.bits.vtype.vlMax) reg_vconfig.get := vio.set_vconfig.bits } when (vio.set_vstart.valid) { set_vs_dirty := true.B reg_vstart.get := vio.set_vstart.bits } vio.vstart := reg_vstart.get vio.vconfig := reg_vconfig.get vio.vxrm := reg_vxrm.get when (reset.asBool) { reg_vconfig.get.vl := 0.U reg_vconfig.get.vtype := 0.U.asTypeOf(new VType) reg_vconfig.get.vtype.vill := true.B } } when(reset.asBool) { reg_satp.mode := 0.U reg_vsatp.mode := 0.U reg_hgatp.mode := 0.U } if (!usingVM) { reg_satp.mode := 0.U reg_satp.ppn := 0.U reg_satp.asid := 0.U } if (!usingHypervisor) { reg_vsatp.mode := 0.U reg_vsatp.ppn := 0.U reg_vsatp.asid := 0.U reg_hgatp.mode := 0.U reg_hgatp.ppn := 0.U reg_hgatp.asid := 0.U } if (!(asIdBits > 0)) { reg_satp.asid := 0.U reg_vsatp.asid := 0.U } if (!(vmIdBits > 0)) { reg_hgatp.asid := 0.U } reg_vsstatus.xs := (if (usingRoCC) 3.U else 0.U) if (nBreakpoints <= 1) reg_tselect := 0.U for (bpc <- reg_bp map {_.control}) { bpc.ttype := bpc.tType.U bpc.maskmax := bpc.maskMax.U bpc.reserved := 0.U bpc.zero := 0.U bpc.h := false.B if (!usingSupervisor) bpc.s := false.B if (!usingUser) bpc.u := false.B if (!usingSupervisor && !usingUser) bpc.m := true.B when (reset.asBool) { bpc.action := 0.U bpc.dmode := false.B bpc.chain := false.B bpc.r := false.B bpc.w := false.B bpc.x := false.B } } for (bpx <- reg_bp map {_.textra}) { if (coreParams.mcontextWidth == 0) bpx.mselect := false.B if (coreParams.scontextWidth == 0) bpx.sselect := false.B } for (bp <- reg_bp drop nBreakpoints) bp := 0.U.asTypeOf(new BP()) for (pmp <- reg_pmp) { pmp.cfg.res := 0.U when (reset.asBool) { pmp.reset() } } for (((t, insn), i) <- (io.trace zip io.inst).zipWithIndex) { t.exception := io.retire >= i.U && exception t.valid := io.retire > i.U \|\| t.exception t.insn := insn t.iaddr := io.pc t.priv := Cat(reg_debug, reg_mstatus.prv) t.cause := cause t.interrupt := cause(xLen-1) t.tval := io.tval t.wdata.foreach(_ := DontCare) } def chooseInterrupt(masksIn: Seq[UInt]): (Bool, UInt) = { val nonstandard = supported_interrupts.getWidth-1 to 12 by -1 // MEI, MSI, MTI, SEI, SSI, STI, VSEI, VSSI, VSTI, UEI, USI, UTI val standard = Seq(11, 3, 7, 9, 1, 5, 10, 2, 6, 8, 0, 4) val priority = nonstandard ++ standard val masks = masksIn.reverse val any = masks.flatMap(m => priority.filter(_ < m.getWidth).map(i => m(i))).reduce(_\|\|_) val which = PriorityMux(masks.flatMap(m => priority.filter(_ < m.getWidth).map(i => (m(i), i.U)))) (any, which) } def readModifyWriteCSR(cmd: UInt, rdata: UInt, wdata: UInt) = { (Mux(cmd(1), rdata, 0.U) \| wdata) & ~Mux(cmd(1,0).andR, wdata, 0.U) } def legalizePrivilege(priv: UInt): UInt = if (usingSupervisor) Mux(priv === PRV.H.U, PRV.U.U, priv) else if (usingUser) Fill(2, priv(0)) else PRV.M.U def trimPrivilege(priv: UInt): UInt = if (usingSupervisor) priv else legalizePrivilege(priv) def writeCounter(lo: Int, ctr: WideCounter, wdata: UInt) = { if (xLen == 32) { val hi = lo + CSRs.mcycleh - CSRs.mcycle when (decoded_addr(lo)) { ctr := Cat(ctr(ctr.getWidth-1, 32), wdata) } when (decoded_addr(hi)) { ctr := Cat(wdata(ctr.getWidth-33, 0), ctr(31, 0)) } } else { when (decoded_addr(lo)) { ctr := wdata(ctr.getWidth-1, 0) } } } def formEPC(x: UInt) = ~(~x \| (if (usingCompressed) 1.U else 3.U)) def readEPC(x: UInt) = ~(~x \| Mux(reg_misa('c' - 'a'), 1.U, 3.U)) def formTVec(x: UInt) = x andNot Mux(x(0), ((((BigInt(1) << mtvecInterruptAlign) - 1) << mtvecBaseAlign) \| 2).U, 2.U) def isaStringToMask(s: String) = s.map(x => 1 << (x - 'A')).foldLeft(0)(_\|_) def formFS(fs: UInt) = if (coreParams.haveFSDirty) fs else Fill(2, fs.orR) def formVS(vs: UInt) = if (usingVector) vs else 0.U }	module CSRFile_1( // @[CSR.scala:377:7] input clock, // @[CSR.scala:377:7] input reset, // @[CSR.scala:377:7] input io_ungated_clock, // @[CSR.scala:384:14] input io_interrupts_debug, // @[CSR.scala:384:14] input io_interrupts_mtip, // @[CSR.scala:384:14] input io_interrupts_msip, // @[CSR.scala:384:14] input io_interrupts_meip, // @[CSR.scala:384:14] input io_interrupts_seip, // @[CSR.scala:384:14] input io_hartid, // @[CSR.scala:384:14] input [11:0] io_rw_addr, // @[CSR.scala:384:14] input [2:0] io_rw_cmd, // @[CSR.scala:384:14] output [63:0] io_rw_rdata, // @[CSR.scala:384:14] input [63:0] io_rw_wdata, // @[CSR.scala:384:14] input [31:0] io_decode_0_inst, // @[CSR.scala:384:14] output io_decode_0_fp_illegal, // @[CSR.scala:384:14] output io_decode_0_fp_csr, // @[CSR.scala:384:14] output io_decode_0_read_illegal, // @[CSR.scala:384:14] output io_decode_0_write_illegal, // @[CSR.scala:384:14] output io_decode_0_write_flush, // @[CSR.scala:384:14] output io_decode_0_system_illegal, // @[CSR.scala:384:14] output io_decode_0_virtual_access_illegal, // @[CSR.scala:384:14] output io_decode_0_virtual_system_illegal, // @[CSR.scala:384:14] output io_csr_stall, // @[CSR.scala:384:14] output io_singleStep, // @[CSR.scala:384:14] output io_status_debug, // @[CSR.scala:384:14] output io_status_cease, // @[CSR.scala:384:14] output io_status_wfi, // @[CSR.scala:384:14] output [1:0] io_status_dprv, // @[CSR.scala:384:14] output io_status_dv, // @[CSR.scala:384:14] output [1:0] io_status_prv, // @[CSR.scala:384:14] output io_status_v, // @[CSR.scala:384:14] output io_status_sd, // @[CSR.scala:384:14] output io_status_mpv, // @[CSR.scala:384:14] output io_status_gva, // @[CSR.scala:384:14] output io_status_tsr, // @[CSR.scala:384:14] output io_status_tw, // @[CSR.scala:384:14] output io_status_tvm, // @[CSR.scala:384:14] output io_status_mxr, // @[CSR.scala:384:14] output io_status_sum, // @[CSR.scala:384:14] output io_status_mprv, // @[CSR.scala:384:14] output [1:0] io_status_fs, // @[CSR.scala:384:14] output [1:0] io_status_mpp, // @[CSR.scala:384:14] output io_status_spp, // @[CSR.scala:384:14] output io_status_mpie, // @[CSR.scala:384:14] output io_status_spie, // @[CSR.scala:384:14] output io_status_mie, // @[CSR.scala:384:14] output io_status_sie, // @[CSR.scala:384:14] output [3:0] io_ptbr_mode, // @[CSR.scala:384:14] output [43:0] io_ptbr_ppn, // @[CSR.scala:384:14] output [39:0] io_evec, // @[CSR.scala:384:14] input io_exception, // @[CSR.scala:384:14] input io_retire, // @[CSR.scala:384:14] input [63:0] io_cause, // @[CSR.scala:384:14] input [39:0] io_pc, // @[CSR.scala:384:14] input [39:0] io_tval, // @[CSR.scala:384:14] output [63:0] io_time, // @[CSR.scala:384:14] output [2:0] io_fcsr_rm, // @[CSR.scala:384:14] input io_fcsr_flags_valid, // @[CSR.scala:384:14] input [4:0] io_fcsr_flags_bits, // @[CSR.scala:384:14] input io_set_fs_dirty, // @[CSR.scala:384:14] output io_interrupt, // @[CSR.scala:384:14] output [63:0] io_interrupt_cause, // @[CSR.scala:384:14] output io_pmp_0_cfg_l, // @[CSR.scala:384:14] output [1:0] io_pmp_0_cfg_a, // @[CSR.scala:384:14] output io_pmp_0_cfg_x, // @[CSR.scala:384:14] output io_pmp_0_cfg_w, // @[CSR.scala:384:14] output io_pmp_0_cfg_r, // @[CSR.scala:384:14] output [29:0] io_pmp_0_addr, // @[CSR.scala:384:14] output [31:0] io_pmp_0_mask, // @[CSR.scala:384:14] output io_pmp_1_cfg_l, // @[CSR.scala:384:14] output [1:0] io_pmp_1_cfg_a, // @[CSR.scala:384:14] output io_pmp_1_cfg_x, // @[CSR.scala:384:14] output io_pmp_1_cfg_w, // @[CSR.scala:384:14] output io_pmp_1_cfg_r, // @[CSR.scala:384:14] output [29:0] io_pmp_1_addr, // @[CSR.scala:384:14] output [31:0] io_pmp_1_mask, // @[CSR.scala:384:14] output io_pmp_2_cfg_l, // @[CSR.scala:384:14] output [1:0] io_pmp_2_cfg_a, // @[CSR.scala:384:14] output io_pmp_2_cfg_x, // @[CSR.scala:384:14] output io_pmp_2_cfg_w, // @[CSR.scala:384:14] output io_pmp_2_cfg_r, // @[CSR.scala:384:14] output [29:0] io_pmp_2_addr, // @[CSR.scala:384:14] output [31:0] io_pmp_2_mask, // @[CSR.scala:384:14] output io_pmp_3_cfg_l, // @[CSR.scala:384:14] output [1:0] io_pmp_3_cfg_a, // @[CSR.scala:384:14] output io_pmp_3_cfg_x, // @[CSR.scala:384:14] output io_pmp_3_cfg_w, // @[CSR.scala:384:14] output io_pmp_3_cfg_r, // @[CSR.scala:384:14] output [29:0] io_pmp_3_addr, // @[CSR.scala:384:14] output [31:0] io_pmp_3_mask, // @[CSR.scala:384:14] output io_pmp_4_cfg_l, // @[CSR.scala:384:14] output [1:0] io_pmp_4_cfg_a, // @[CSR.scala:384:14] output io_pmp_4_cfg_x, // @[CSR.scala:384:14] output io_pmp_4_cfg_w, // @[CSR.scala:384:14] output io_pmp_4_cfg_r, // @[CSR.scala:384:14] output [29:0] io_pmp_4_addr, // @[CSR.scala:384:14] output [31:0] io_pmp_4_mask, // @[CSR.scala:384:14] output io_pmp_5_cfg_l, // @[CSR.scala:384:14] output [1:0] io_pmp_5_cfg_a, // @[CSR.scala:384:14] output io_pmp_5_cfg_x, // @[CSR.scala:384:14] output io_pmp_5_cfg_w, // @[CSR.scala:384:14] output io_pmp_5_cfg_r, // @[CSR.scala:384:14] output [29:0] io_pmp_5_addr, // @[CSR.scala:384:14] output [31:0] io_pmp_5_mask, // @[CSR.scala:384:14] output io_pmp_6_cfg_l, // @[CSR.scala:384:14] output [1:0] io_pmp_6_cfg_a, // @[CSR.scala:384:14] output io_pmp_6_cfg_x, // @[CSR.scala:384:14] output io_pmp_6_cfg_w, // @[CSR.scala:384:14] output io_pmp_6_cfg_r, // @[CSR.scala:384:14] output [29:0] io_pmp_6_addr, // @[CSR.scala:384:14] output [31:0] io_pmp_6_mask, // @[CSR.scala:384:14] output io_pmp_7_cfg_l, // @[CSR.scala:384:14] output [1:0] io_pmp_7_cfg_a, // @[CSR.scala:384:14] output io_pmp_7_cfg_x, // @[CSR.scala:384:14] output io_pmp_7_cfg_w, // @[CSR.scala:384:14] output io_pmp_7_cfg_r, // @[CSR.scala:384:14] output [29:0] io_pmp_7_addr, // @[CSR.scala:384:14] output [31:0] io_pmp_7_mask, // @[CSR.scala:384:14] output [63:0] io_counters_0_eventSel, // @[CSR.scala:384:14] input io_counters_0_inc, // @[CSR.scala:384:14] output [63:0] io_counters_1_eventSel, // @[CSR.scala:384:14] input io_counters_1_inc, // @[CSR.scala:384:14] output io_customCSRs_0_ren, // @[CSR.scala:384:14] output io_customCSRs_0_wen, // @[CSR.scala:384:14] output [63:0] io_customCSRs_0_wdata, // @[CSR.scala:384:14] output [63:0] io_customCSRs_0_value, // @[CSR.scala:384:14] output io_customCSRs_1_ren, // @[CSR.scala:384:14] output io_customCSRs_1_wen, // @[CSR.scala:384:14] output [63:0] io_customCSRs_1_wdata, // @[CSR.scala:384:14] output [63:0] io_customCSRs_1_value // @[CSR.scala:384:14] ); wire io_status_sie_0; // @[CSR.scala:377:7] wire io_status_spie_0; // @[CSR.scala:377:7] wire io_status_spp_0; // @[CSR.scala:377:7] wire [1:0] io_status_fs_0; // @[CSR.scala:377:7] wire io_status_sum_0; // @[CSR.scala:377:7] wire io_status_mxr_0; // @[CSR.scala:377:7] wire io_status_sd_0; // @[CSR.scala:377:7] wire io_ungated_clock_0 = io_ungated_clock; // @[CSR.scala:377:7] wire io_interrupts_debug_0 = io_interrupts_debug; // @[CSR.scala:377:7] wire io_interrupts_mtip_0 = io_interrupts_mtip; // @[CSR.scala:377:7] wire io_interrupts_msip_0 = io_interrupts_msip; // @[CSR.scala:377:7] wire io_interrupts_meip_0 = io_interrupts_meip; // @[CSR.scala:377:7] wire io_interrupts_seip_0 = io_interrupts_seip; // @[CSR.scala:377:7] wire io_hartid_0 = io_hartid; // @[CSR.scala:377:7] wire [11:0] io_rw_addr_0 = io_rw_addr; // @[CSR.scala:377:7] wire [2:0] io_rw_cmd_0 = io_rw_cmd; // @[CSR.scala:377:7] wire [63:0] io_rw_wdata_0 = io_rw_wdata; // @[CSR.scala:377:7] wire [31:0] io_decode_0_inst_0 = io_decode_0_inst; // @[CSR.scala:377:7] wire io_exception_0 = io_exception; // @[CSR.scala:377:7] wire io_retire_0 = io_retire; // @[CSR.scala:377:7] wire [63:0] io_cause_0 = io_cause; // @[CSR.scala:377:7] wire [39:0] io_pc_0 = io_pc; // @[CSR.scala:377:7] wire [39:0] io_tval_0 = io_tval; // @[CSR.scala:377:7] wire io_fcsr_flags_valid_0 = io_fcsr_flags_valid; // @[CSR.scala:377:7] wire [4:0] io_fcsr_flags_bits_0 = io_fcsr_flags_bits; // @[CSR.scala:377:7] wire io_set_fs_dirty_0 = io_set_fs_dirty; // @[CSR.scala:377:7] wire io_counters_0_inc_0 = io_counters_0_inc; // @[CSR.scala:377:7] wire io_counters_1_inc_0 = io_counters_1_inc; // @[CSR.scala:377:7] wire io_decode_0_vector_illegal = 1'h1; // @[CSR.scala:377:7] wire io_decode_0_rocc_illegal = 1'h1; // @[CSR.scala:377:7] wire io_gstatus_sd = 1'h1; // @[CSR.scala:377:7] wire sup_meip = 1'h1; // @[CSR.scala:406:19] wire sup_seip = 1'h1; // @[CSR.scala:406:19] wire sup_mtip = 1'h1; // @[CSR.scala:406:19] wire sup_stip = 1'h1; // @[CSR.scala:406:19] wire sup_msip = 1'h1; // @[CSR.scala:406:19] wire sup_ssip = 1'h1; // @[CSR.scala:406:19] wire del_seip = 1'h1; // @[CSR.scala:426:26] wire del_stip = 1'h1; // @[CSR.scala:426:26] wire del_ssip = 1'h1; // @[CSR.scala:426:26] wire _read_mapping_T_3 = 1'h1; // @[CSR.scala:1665:45] wire _debug_csrs_T_1 = 1'h1; // @[CSR.scala:1665:45] wire read_mnstatus_mie = 1'h1; // @[CSR.scala:675:31] wire sie_mask_sgeip_mask_sgeip = 1'h1; // @[CSR.scala:748:30] wire _allow_wfi_T_4 = 1'h1; // @[CSR.scala:906:112] wire _allow_wfi_T_5 = 1'h1; // @[CSR.scala:906:109] wire allow_hfence_vvma = 1'h1; // @[CSR.scala:908:50] wire allow_hlsv = 1'h1; // @[CSR.scala:909:43] wire _allow_counter_T_11 = 1'h1; // @[CSR.scala:914:8] wire _allow_counter_T_13 = 1'h1; // @[CSR.scala:914:27] wire _allow_counter_T_16 = 1'h1; // @[CSR.scala:914:45] wire _io_decode_0_fp_illegal_T_4 = 1'h1; // @[CSR.scala:915:103] wire _io_decode_0_vector_illegal_T = 1'h1; // @[CSR.scala:916:43] wire _io_decode_0_vector_illegal_T_1 = 1'h1; // @[CSR.scala:916:87] wire _io_decode_0_vector_illegal_T_3 = 1'h1; // @[CSR.scala:916:51] wire _io_decode_0_vector_illegal_T_5 = 1'h1; // @[CSR.scala:916:98] wire _io_decode_0_vector_illegal_T_6 = 1'h1; // @[CSR.scala:916:95] wire _io_decode_0_rocc_illegal_T = 1'h1; // @[CSR.scala:919:41] wire _io_decode_0_rocc_illegal_T_1 = 1'h1; // @[CSR.scala:919:85] wire _io_decode_0_rocc_illegal_T_3 = 1'h1; // @[CSR.scala:919:49] wire _io_decode_0_rocc_illegal_T_5 = 1'h1; // @[CSR.scala:919:96] wire _io_decode_0_rocc_illegal_T_6 = 1'h1; // @[CSR.scala:919:93] wire _io_gstatus_sd_T = 1'h1; // @[CSR.scala:1016:34] wire _io_gstatus_sd_T_2 = 1'h1; // @[CSR.scala:1016:39] wire _io_gstatus_sd_T_4 = 1'h1; // @[CSR.scala:1016:61] wire _en_T_7 = 1'h1; // @[CSR.scala:1096:71] wire delegable_1 = 1'h1; // @[CSR.scala:1097:65] wire _en_T_19 = 1'h1; // @[CSR.scala:1096:71] wire _en_T_31 = 1'h1; // @[CSR.scala:1096:71] wire delegable_5 = 1'h1; // @[CSR.scala:1097:65] wire _en_T_43 = 1'h1; // @[CSR.scala:1096:71] wire _en_T_55 = 1'h1; // @[CSR.scala:1096:71] wire delegable_9 = 1'h1; // @[CSR.scala:1097:65] wire _en_T_67 = 1'h1; // @[CSR.scala:1096:71] wire delegable_17 = 1'h1; // @[CSR.scala:1109:67] wire delegable_18 = 1'h1; // @[CSR.scala:1109:67] wire delegable_19 = 1'h1; // @[CSR.scala:1109:67] wire delegable_21 = 1'h1; // @[CSR.scala:1109:67] wire delegable_23 = 1'h1; // @[CSR.scala:1109:67] wire delegable_26 = 1'h1; // @[CSR.scala:1109:67] wire delegable_27 = 1'h1; // @[CSR.scala:1109:67] wire delegable_28 = 1'h1; // @[CSR.scala:1109:67] wire _io_evec_T_1 = 1'h1; // @[CSR.scala:1665:45] wire _io_evec_T_6 = 1'h1; // @[CSR.scala:1665:45] wire _io_evec_T_11 = 1'h1; // @[CSR.scala:1665:45] wire _io_evec_T_16 = 1'h1; // @[CSR.scala:1665:45] wire _io_evec_T_21 = 1'h1; // @[CSR.scala:1665:45] wire _csr_wen_T_5 = 1'h1; // @[CSR.scala:1222:59] wire _io_trace_0_exception_T = 1'h1; // @[CSR.scala:1620:30] wire [31:0] io_status_isa = 32'h14112D; // @[CSR.scala:377:7] wire [22:0] io_status_zero2 = 23'h0; // @[CSR.scala:377:7] wire [22:0] io_gstatus_zero2 = 23'h0; // @[CSR.scala:377:7] wire [22:0] _reset_mstatus_WIRE_zero2 = 23'h0; // @[CSR.scala:391:47] wire [22:0] reset_mstatus_zero2 = 23'h0; // @[CSR.scala:391:34] wire [22:0] _read_sstatus_WIRE_zero2 = 23'h0; // @[CSR.scala:755:48] wire [22:0] read_sstatus_zero2 = 23'h0; // @[CSR.scala:755:35] wire io_decode_0_vector_csr = 1'h0; // @[CSR.scala:377:7] wire io_rw_stall = 1'h0; // @[CSR.scala:377:7] wire io_status_mbe = 1'h0; // @[CSR.scala:377:7] wire io_status_sbe = 1'h0; // @[CSR.scala:377:7] wire io_status_sd_rv32 = 1'h0; // @[CSR.scala:377:7] wire io_status_ube = 1'h0; // @[CSR.scala:377:7] wire io_status_upie = 1'h0; // @[CSR.scala:377:7] wire io_status_hie = 1'h0; // @[CSR.scala:377:7] wire io_status_uie = 1'h0; // @[CSR.scala:377:7] wire io_hstatus_vtsr = 1'h0; // @[CSR.scala:377:7] wire io_hstatus_vtw = 1'h0; // @[CSR.scala:377:7] wire io_hstatus_vtvm = 1'h0; // @[CSR.scala:377:7] wire io_hstatus_hu = 1'h0; // @[CSR.scala:377:7] wire io_hstatus_vsbe = 1'h0; // @[CSR.scala:377:7] wire io_gstatus_debug = 1'h0; // @[CSR.scala:377:7] wire io_gstatus_cease = 1'h0; // @[CSR.scala:377:7] wire io_gstatus_wfi = 1'h0; // @[CSR.scala:377:7] wire io_gstatus_dv = 1'h0; // @[CSR.scala:377:7] wire io_gstatus_v = 1'h0; // @[CSR.scala:377:7] wire io_gstatus_mpv = 1'h0; // @[CSR.scala:377:7] wire io_gstatus_gva = 1'h0; // @[CSR.scala:377:7] wire io_gstatus_mbe = 1'h0; // @[CSR.scala:377:7] wire io_gstatus_sbe = 1'h0; // @[CSR.scala:377:7] wire io_gstatus_sd_rv32 = 1'h0; // @[CSR.scala:377:7] wire io_gstatus_tsr = 1'h0; // @[CSR.scala:377:7] wire io_gstatus_tw = 1'h0; // @[CSR.scala:377:7] wire io_gstatus_tvm = 1'h0; // @[CSR.scala:377:7] wire io_gstatus_mxr = 1'h0; // @[CSR.scala:377:7] wire io_gstatus_sum = 1'h0; // @[CSR.scala:377:7] wire io_gstatus_mprv = 1'h0; // @[CSR.scala:377:7] wire io_gstatus_mpie = 1'h0; // @[CSR.scala:377:7] wire io_gstatus_ube = 1'h0; // @[CSR.scala:377:7] wire io_gstatus_upie = 1'h0; // @[CSR.scala:377:7] wire io_gstatus_mie = 1'h0; // @[CSR.scala:377:7] wire io_gstatus_hie = 1'h0; // @[CSR.scala:377:7] wire io_gstatus_uie = 1'h0; // @[CSR.scala:377:7] wire io_mhtinst_read_pseudo = 1'h0; // @[CSR.scala:377:7] wire io_gva = 1'h0; // @[CSR.scala:377:7] wire io_rocc_interrupt = 1'h0; // @[CSR.scala:377:7] wire io_customCSRs_0_stall = 1'h0; // @[CSR.scala:377:7] wire io_customCSRs_0_set = 1'h0; // @[CSR.scala:377:7] wire io_customCSRs_1_stall = 1'h0; // @[CSR.scala:377:7] wire io_customCSRs_1_set = 1'h0; // @[CSR.scala:377:7] wire _reset_mstatus_WIRE_debug = 1'h0; // @[CSR.scala:391:47] wire _reset_mstatus_WIRE_cease = 1'h0; // @[CSR.scala:391:47] wire _reset_mstatus_WIRE_wfi = 1'h0; // @[CSR.scala:391:47] wire _reset_mstatus_WIRE_dv = 1'h0; // @[CSR.scala:391:47] wire _reset_mstatus_WIRE_v = 1'h0; // @[CSR.scala:391:47] wire _reset_mstatus_WIRE_sd = 1'h0; // @[CSR.scala:391:47] wire _reset_mstatus_WIRE_mpv = 1'h0; // @[CSR.scala:391:47] wire _reset_mstatus_WIRE_gva = 1'h0; // @[CSR.scala:391:47] wire _reset_mstatus_WIRE_mbe = 1'h0; // @[CSR.scala:391:47] wire _reset_mstatus_WIRE_sbe = 1'h0; // @[CSR.scala:391:47] wire _reset_mstatus_WIRE_sd_rv32 = 1'h0; // @[CSR.scala:391:47] wire _reset_mstatus_WIRE_tsr = 1'h0; // @[CSR.scala:391:47] wire _reset_mstatus_WIRE_tw = 1'h0; // @[CSR.scala:391:47] wire _reset_mstatus_WIRE_tvm = 1'h0; // @[CSR.scala:391:47] wire _reset_mstatus_WIRE_mxr = 1'h0; // @[CSR.scala:391:47] wire _reset_mstatus_WIRE_sum = 1'h0; // @[CSR.scala:391:47] wire _reset_mstatus_WIRE_mprv = 1'h0; // @[CSR.scala:391:47] wire _reset_mstatus_WIRE_spp = 1'h0; // @[CSR.scala:391:47] wire _reset_mstatus_WIRE_mpie = 1'h0; // @[CSR.scala:391:47] wire _reset_mstatus_WIRE_ube = 1'h0; // @[CSR.scala:391:47] wire _reset_mstatus_WIRE_spie = 1'h0; // @[CSR.scala:391:47] wire _reset_mstatus_WIRE_upie = 1'h0; // @[CSR.scala:391:47] wire _reset_mstatus_WIRE_mie = 1'h0; // @[CSR.scala:391:47] wire _reset_mstatus_WIRE_hie = 1'h0; // @[CSR.scala:391:47] wire _reset_mstatus_WIRE_sie = 1'h0; // @[CSR.scala:391:47] wire _reset_mstatus_WIRE_uie = 1'h0; // @[CSR.scala:391:47] wire reset_mstatus_debug = 1'h0; // @[CSR.scala:391:34] wire reset_mstatus_cease = 1'h0; // @[CSR.scala:391:34] wire reset_mstatus_wfi = 1'h0; // @[CSR.scala:391:34] wire reset_mstatus_dv = 1'h0; // @[CSR.scala:391:34] wire reset_mstatus_v = 1'h0; // @[CSR.scala:391:34] wire reset_mstatus_sd = 1'h0; // @[CSR.scala:391:34] wire reset_mstatus_mpv = 1'h0; // @[CSR.scala:391:34] wire reset_mstatus_gva = 1'h0; // @[CSR.scala:391:34] wire reset_mstatus_mbe = 1'h0; // @[CSR.scala:391:34] wire reset_mstatus_sbe = 1'h0; // @[CSR.scala:391:34] wire reset_mstatus_sd_rv32 = 1'h0; // @[CSR.scala:391:34] wire reset_mstatus_tsr = 1'h0; // @[CSR.scala:391:34] wire reset_mstatus_tw = 1'h0; // @[CSR.scala:391:34] wire reset_mstatus_tvm = 1'h0; // @[CSR.scala:391:34] wire reset_mstatus_mxr = 1'h0; // @[CSR.scala:391:34] wire reset_mstatus_sum = 1'h0; // @[CSR.scala:391:34] wire reset_mstatus_mprv = 1'h0; // @[CSR.scala:391:34] wire reset_mstatus_spp = 1'h0; // @[CSR.scala:391:34] wire reset_mstatus_mpie = 1'h0; // @[CSR.scala:391:34] wire reset_mstatus_ube = 1'h0; // @[CSR.scala:391:34] wire reset_mstatus_spie = 1'h0; // @[CSR.scala:391:34] wire reset_mstatus_upie = 1'h0; // @[CSR.scala:391:34] wire reset_mstatus_mie = 1'h0; // @[CSR.scala:391:34] wire reset_mstatus_hie = 1'h0; // @[CSR.scala:391:34] wire reset_mstatus_sie = 1'h0; // @[CSR.scala:391:34] wire reset_mstatus_uie = 1'h0; // @[CSR.scala:391:34] wire _reset_dcsr_WIRE_ebreakm = 1'h0; // @[CSR.scala:400:44] wire _reset_dcsr_WIRE_ebreakh = 1'h0; // @[CSR.scala:400:44] wire _reset_dcsr_WIRE_ebreaks = 1'h0; // @[CSR.scala:400:44] wire _reset_dcsr_WIRE_ebreaku = 1'h0; // @[CSR.scala:400:44] wire _reset_dcsr_WIRE_zero2 = 1'h0; // @[CSR.scala:400:44] wire _reset_dcsr_WIRE_stopcycle = 1'h0; // @[CSR.scala:400:44] wire _reset_dcsr_WIRE_stoptime = 1'h0; // @[CSR.scala:400:44] wire _reset_dcsr_WIRE_v = 1'h0; // @[CSR.scala:400:44] wire _reset_dcsr_WIRE_step = 1'h0; // @[CSR.scala:400:44] wire reset_dcsr_ebreakm = 1'h0; // @[CSR.scala:400:31] wire reset_dcsr_ebreakh = 1'h0; // @[CSR.scala:400:31] wire reset_dcsr_ebreaks = 1'h0; // @[CSR.scala:400:31] wire reset_dcsr_ebreaku = 1'h0; // @[CSR.scala:400:31] wire reset_dcsr_zero2 = 1'h0; // @[CSR.scala:400:31] wire reset_dcsr_stopcycle = 1'h0; // @[CSR.scala:400:31] wire reset_dcsr_stoptime = 1'h0; // @[CSR.scala:400:31] wire reset_dcsr_v = 1'h0; // @[CSR.scala:400:31] wire reset_dcsr_step = 1'h0; // @[CSR.scala:400:31] wire sup_zero1 = 1'h0; // @[CSR.scala:406:19] wire sup_debug = 1'h0; // @[CSR.scala:406:19] wire sup_rocc = 1'h0; // @[CSR.scala:406:19] wire sup_sgeip = 1'h0; // @[CSR.scala:406:19] wire sup_vseip = 1'h0; // @[CSR.scala:406:19] wire sup_ueip = 1'h0; // @[CSR.scala:406:19] wire sup_vstip = 1'h0; // @[CSR.scala:406:19] wire sup_utip = 1'h0; // @[CSR.scala:406:19] wire sup_vssip = 1'h0; // @[CSR.scala:406:19] wire sup_usip = 1'h0; // @[CSR.scala:406:19] wire del_zero1 = 1'h0; // @[CSR.scala:426:26] wire del_debug = 1'h0; // @[CSR.scala:426:26] wire del_rocc = 1'h0; // @[CSR.scala:426:26] wire del_sgeip = 1'h0; // @[CSR.scala:426:26] wire del_meip = 1'h0; // @[CSR.scala:426:26] wire del_vseip = 1'h0; // @[CSR.scala:426:26] wire del_ueip = 1'h0; // @[CSR.scala:426:26] wire del_mtip = 1'h0; // @[CSR.scala:426:26] wire del_vstip = 1'h0; // @[CSR.scala:426:26] wire del_utip = 1'h0; // @[CSR.scala:426:26] wire del_msip = 1'h0; // @[CSR.scala:426:26] wire del_vssip = 1'h0; // @[CSR.scala:426:26] wire del_usip = 1'h0; // @[CSR.scala:426:26] wire hi_hi_hi_hi = 1'h0; // @[CSR.scala:431:10] wire hi_hi_hi_hi_1 = 1'h0; // @[CSR.scala:431:50] wire _always_WIRE_zero1 = 1'h0; // @[CSR.scala:471:42] wire _always_WIRE_debug = 1'h0; // @[CSR.scala:471:42] wire _always_WIRE_rocc = 1'h0; // @[CSR.scala:471:42] wire _always_WIRE_sgeip = 1'h0; // @[CSR.scala:471:42] wire _always_WIRE_meip = 1'h0; // @[CSR.scala:471:42] wire _always_WIRE_vseip = 1'h0; // @[CSR.scala:471:42] wire _always_WIRE_seip = 1'h0; // @[CSR.scala:471:42] wire _always_WIRE_ueip = 1'h0; // @[CSR.scala:471:42] wire _always_WIRE_mtip = 1'h0; // @[CSR.scala:471:42] wire _always_WIRE_vstip = 1'h0; // @[CSR.scala:471:42] wire _always_WIRE_stip = 1'h0; // @[CSR.scala:471:42] wire _always_WIRE_utip = 1'h0; // @[CSR.scala:471:42] wire _always_WIRE_msip = 1'h0; // @[CSR.scala:471:42] wire _always_WIRE_vssip = 1'h0; // @[CSR.scala:471:42] wire _always_WIRE_ssip = 1'h0; // @[CSR.scala:471:42] wire _always_WIRE_usip = 1'h0; // @[CSR.scala:471:42] wire always_zero1 = 1'h0; // @[CSR.scala:471:29] wire always_debug = 1'h0; // @[CSR.scala:471:29] wire always_rocc = 1'h0; // @[CSR.scala:471:29] wire always_sgeip = 1'h0; // @[CSR.scala:471:29] wire always_meip = 1'h0; // @[CSR.scala:471:29] wire always_vseip = 1'h0; // @[CSR.scala:471:29] wire always_seip = 1'h0; // @[CSR.scala:471:29] wire always_ueip = 1'h0; // @[CSR.scala:471:29] wire always_mtip = 1'h0; // @[CSR.scala:471:29] wire always_vstip = 1'h0; // @[CSR.scala:471:29] wire always_stip = 1'h0; // @[CSR.scala:471:29] wire always_utip = 1'h0; // @[CSR.scala:471:29] wire always_msip = 1'h0; // @[CSR.scala:471:29] wire always_vssip = 1'h0; // @[CSR.scala:471:29] wire always_ssip = 1'h0; // @[CSR.scala:471:29] wire always_usip = 1'h0; // @[CSR.scala:471:29] wire deleg_zero1 = 1'h0; // @[CSR.scala:476:28] wire deleg_debug = 1'h0; // @[CSR.scala:476:28] wire deleg_rocc = 1'h0; // @[CSR.scala:476:28] wire deleg_sgeip = 1'h0; // @[CSR.scala:476:28] wire deleg_meip = 1'h0; // @[CSR.scala:476:28] wire deleg_vseip = 1'h0; // @[CSR.scala:476:28] wire deleg_seip = 1'h0; // @[CSR.scala:476:28] wire deleg_ueip = 1'h0; // @[CSR.scala:476:28] wire deleg_mtip = 1'h0; // @[CSR.scala:476:28] wire deleg_vstip = 1'h0; // @[CSR.scala:476:28] wire deleg_stip = 1'h0; // @[CSR.scala:476:28] wire deleg_utip = 1'h0; // @[CSR.scala:476:28] wire deleg_msip = 1'h0; // @[CSR.scala:476:28] wire deleg_vssip = 1'h0; // @[CSR.scala:476:28] wire deleg_ssip = 1'h0; // @[CSR.scala:476:28] wire deleg_usip = 1'h0; // @[CSR.scala:476:28] wire hi_hi_hi_hi_2 = 1'h0; // @[CSR.scala:479:12] wire hi_hi_hi_hi_3 = 1'h0; // @[CSR.scala:479:27] wire _reset_mnstatus_WIRE_mpv = 1'h0; // @[CSR.scala:516:48] wire _reset_mnstatus_WIRE_mie = 1'h0; // @[CSR.scala:516:48] wire reset_mnstatus_mpv = 1'h0; // @[CSR.scala:516:35] wire reset_mnstatus_mie = 1'h0; // @[CSR.scala:516:35] wire _reg_menvcfg_WIRE_stce = 1'h0; // @[CSR.scala:525:41] wire _reg_menvcfg_WIRE_pbmte = 1'h0; // @[CSR.scala:525:41] wire _reg_menvcfg_WIRE_cbze = 1'h0; // @[CSR.scala:525:41] wire _reg_menvcfg_WIRE_cbcfe = 1'h0; // @[CSR.scala:525:41] wire _reg_menvcfg_WIRE_fiom = 1'h0; // @[CSR.scala:525:41] wire _reg_senvcfg_WIRE_stce = 1'h0; // @[CSR.scala:526:41] wire _reg_senvcfg_WIRE_pbmte = 1'h0; // @[CSR.scala:526:41] wire _reg_senvcfg_WIRE_cbze = 1'h0; // @[CSR.scala:526:41] wire _reg_senvcfg_WIRE_cbcfe = 1'h0; // @[CSR.scala:526:41] wire _reg_senvcfg_WIRE_fiom = 1'h0; // @[CSR.scala:526:41] wire _reg_henvcfg_WIRE_stce = 1'h0; // @[CSR.scala:527:41] wire _reg_henvcfg_WIRE_pbmte = 1'h0; // @[CSR.scala:527:41] wire _reg_henvcfg_WIRE_cbze = 1'h0; // @[CSR.scala:527:41] wire _reg_henvcfg_WIRE_cbcfe = 1'h0; // @[CSR.scala:527:41] wire _reg_henvcfg_WIRE_fiom = 1'h0; // @[CSR.scala:527:41] wire _reg_hstatus_WIRE_vtsr = 1'h0; // @[CSR.scala:552:41] wire _reg_hstatus_WIRE_vtw = 1'h0; // @[CSR.scala:552:41] wire _reg_hstatus_WIRE_vtvm = 1'h0; // @[CSR.scala:552:41] wire _reg_hstatus_WIRE_hu = 1'h0; // @[CSR.scala:552:41] wire _reg_hstatus_WIRE_spvp = 1'h0; // @[CSR.scala:552:41] wire _reg_hstatus_WIRE_spv = 1'h0; // @[CSR.scala:552:41] wire _reg_hstatus_WIRE_gva = 1'h0; // @[CSR.scala:552:41] wire _reg_hstatus_WIRE_vsbe = 1'h0; // @[CSR.scala:552:41] wire read_hvip_hi_hi_hi_hi = 1'h0; // @[CSR.scala:555:27] wire mip_zero1 = 1'h0; // @[CSR.scala:600:24] wire mip_debug = 1'h0; // @[CSR.scala:600:24] wire mip_rocc = 1'h0; // @[CSR.scala:600:24] wire mip_sgeip = 1'h0; // @[CSR.scala:600:24] wire mip_vseip = 1'h0; // @[CSR.scala:600:24] wire mip_ueip = 1'h0; // @[CSR.scala:600:24] wire mip_vstip = 1'h0; // @[CSR.scala:600:24] wire mip_utip = 1'h0; // @[CSR.scala:600:24] wire mip_vssip = 1'h0; // @[CSR.scala:600:24] wire mip_usip = 1'h0; // @[CSR.scala:600:24] wire _any_T_47 = 1'h0; // @[CSR.scala:1637:76] wire _any_T_48 = 1'h0; // @[CSR.scala:1637:76] wire _any_T_49 = 1'h0; // @[CSR.scala:1637:76] wire _any_T_50 = 1'h0; // @[CSR.scala:1637:76] wire _any_T_51 = 1'h0; // @[CSR.scala:1637:76] wire _any_T_52 = 1'h0; // @[CSR.scala:1637:76] wire _any_T_53 = 1'h0; // @[CSR.scala:1637:76] wire _any_T_54 = 1'h0; // @[CSR.scala:1637:76] wire _any_T_55 = 1'h0; // @[CSR.scala:1637:76] wire _any_T_56 = 1'h0; // @[CSR.scala:1637:76] wire _any_T_57 = 1'h0; // @[CSR.scala:1637:76] wire _any_T_58 = 1'h0; // @[CSR.scala:1637:76] wire _any_T_59 = 1'h0; // @[CSR.scala:1637:76] wire _any_T_60 = 1'h0; // @[CSR.scala:1637:76] wire _any_T_61 = 1'h0; // @[CSR.scala:1637:76] wire _any_T_62 = 1'h0; // @[CSR.scala:1637:76] wire _which_T_47 = 1'h0; // @[CSR.scala:1638:91] wire _which_T_48 = 1'h0; // @[CSR.scala:1638:91] wire _which_T_49 = 1'h0; // @[CSR.scala:1638:91] wire _which_T_50 = 1'h0; // @[CSR.scala:1638:91] wire _which_T_51 = 1'h0; // @[CSR.scala:1638:91] wire _which_T_52 = 1'h0; // @[CSR.scala:1638:91] wire _which_T_53 = 1'h0; // @[CSR.scala:1638:91] wire _which_T_54 = 1'h0; // @[CSR.scala:1638:91] wire _which_T_55 = 1'h0; // @[CSR.scala:1638:91] wire _which_T_56 = 1'h0; // @[CSR.scala:1638:91] wire _which_T_57 = 1'h0; // @[CSR.scala:1638:91] wire _which_T_58 = 1'h0; // @[CSR.scala:1638:91] wire _which_T_59 = 1'h0; // @[CSR.scala:1638:91] wire _which_T_60 = 1'h0; // @[CSR.scala:1638:91] wire _which_T_61 = 1'h0; // @[CSR.scala:1638:91] wire _which_T_62 = 1'h0; // @[CSR.scala:1638:91] wire _io_fiom_T_5 = 1'h0; // @[CSR.scala:631:131] wire _pmp_mask_base_T_2 = 1'h0; // @[PMP.scala:57:62] wire _pmp_mask_base_T_5 = 1'h0; // @[PMP.scala:57:62] wire _pmp_mask_base_T_8 = 1'h0; // @[PMP.scala:57:62] wire _pmp_mask_base_T_11 = 1'h0; // @[PMP.scala:57:62] wire _pmp_mask_base_T_14 = 1'h0; // @[PMP.scala:57:62] wire _pmp_mask_base_T_17 = 1'h0; // @[PMP.scala:57:62] wire _pmp_mask_base_T_20 = 1'h0; // @[PMP.scala:57:62] wire _pmp_mask_base_T_23 = 1'h0; // @[PMP.scala:57:62] wire _read_mapping_T = 1'h0; // @[package.scala:132:38] wire read_mapping_lo_hi_1 = 1'h0; // @[CSR.scala:657:47] wire read_mapping_hi_hi_1 = 1'h0; // @[CSR.scala:657:47] wire _read_mnstatus_WIRE_mpv = 1'h0; // @[CSR.scala:675:44] wire _read_mnstatus_WIRE_mie = 1'h0; // @[CSR.scala:675:44] wire read_mnstatus_mpv = 1'h0; // @[CSR.scala:675:31] wire _sie_mask_sgeip_mask_WIRE_zero1 = 1'h0; // @[CSR.scala:748:43] wire _sie_mask_sgeip_mask_WIRE_debug = 1'h0; // @[CSR.scala:748:43] wire _sie_mask_sgeip_mask_WIRE_rocc = 1'h0; // @[CSR.scala:748:43] wire _sie_mask_sgeip_mask_WIRE_sgeip = 1'h0; // @[CSR.scala:748:43] wire _sie_mask_sgeip_mask_WIRE_meip = 1'h0; // @[CSR.scala:748:43] wire _sie_mask_sgeip_mask_WIRE_vseip = 1'h0; // @[CSR.scala:748:43] wire _sie_mask_sgeip_mask_WIRE_seip = 1'h0; // @[CSR.scala:748:43] wire _sie_mask_sgeip_mask_WIRE_ueip = 1'h0; // @[CSR.scala:748:43] wire _sie_mask_sgeip_mask_WIRE_mtip = 1'h0; // @[CSR.scala:748:43] wire _sie_mask_sgeip_mask_WIRE_vstip = 1'h0; // @[CSR.scala:748:43] wire _sie_mask_sgeip_mask_WIRE_stip = 1'h0; // @[CSR.scala:748:43] wire _sie_mask_sgeip_mask_WIRE_utip = 1'h0; // @[CSR.scala:748:43] wire _sie_mask_sgeip_mask_WIRE_msip = 1'h0; // @[CSR.scala:748:43] wire _sie_mask_sgeip_mask_WIRE_vssip = 1'h0; // @[CSR.scala:748:43] wire _sie_mask_sgeip_mask_WIRE_ssip = 1'h0; // @[CSR.scala:748:43] wire _sie_mask_sgeip_mask_WIRE_usip = 1'h0; // @[CSR.scala:748:43] wire sie_mask_sgeip_mask_zero1 = 1'h0; // @[CSR.scala:748:30] wire sie_mask_sgeip_mask_debug = 1'h0; // @[CSR.scala:748:30] wire sie_mask_sgeip_mask_rocc = 1'h0; // @[CSR.scala:748:30] wire sie_mask_sgeip_mask_meip = 1'h0; // @[CSR.scala:748:30] wire sie_mask_sgeip_mask_vseip = 1'h0; // @[CSR.scala:748:30] wire sie_mask_sgeip_mask_seip = 1'h0; // @[CSR.scala:748:30] wire sie_mask_sgeip_mask_ueip = 1'h0; // @[CSR.scala:748:30] wire sie_mask_sgeip_mask_mtip = 1'h0; // @[CSR.scala:748:30] wire sie_mask_sgeip_mask_vstip = 1'h0; // @[CSR.scala:748:30] wire sie_mask_sgeip_mask_stip = 1'h0; // @[CSR.scala:748:30] wire sie_mask_sgeip_mask_utip = 1'h0; // @[CSR.scala:748:30] wire sie_mask_sgeip_mask_msip = 1'h0; // @[CSR.scala:748:30] wire sie_mask_sgeip_mask_vssip = 1'h0; // @[CSR.scala:748:30] wire sie_mask_sgeip_mask_ssip = 1'h0; // @[CSR.scala:748:30] wire sie_mask_sgeip_mask_usip = 1'h0; // @[CSR.scala:748:30] wire sie_mask_hi_hi_hi_hi = 1'h0; // @[CSR.scala:750:59] wire _read_sstatus_WIRE_debug = 1'h0; // @[CSR.scala:755:48] wire _read_sstatus_WIRE_cease = 1'h0; // @[CSR.scala:755:48] wire _read_sstatus_WIRE_wfi = 1'h0; // @[CSR.scala:755:48] wire _read_sstatus_WIRE_dv = 1'h0; // @[CSR.scala:755:48] wire _read_sstatus_WIRE_v = 1'h0; // @[CSR.scala:755:48] wire _read_sstatus_WIRE_sd = 1'h0; // @[CSR.scala:755:48] wire _read_sstatus_WIRE_mpv = 1'h0; // @[CSR.scala:755:48] wire _read_sstatus_WIRE_gva = 1'h0; // @[CSR.scala:755:48] wire _read_sstatus_WIRE_mbe = 1'h0; // @[CSR.scala:755:48] wire _read_sstatus_WIRE_sbe = 1'h0; // @[CSR.scala:755:48] wire _read_sstatus_WIRE_sd_rv32 = 1'h0; // @[CSR.scala:755:48] wire _read_sstatus_WIRE_tsr = 1'h0; // @[CSR.scala:755:48] wire _read_sstatus_WIRE_tw = 1'h0; // @[CSR.scala:755:48] wire _read_sstatus_WIRE_tvm = 1'h0; // @[CSR.scala:755:48] wire _read_sstatus_WIRE_mxr = 1'h0; // @[CSR.scala:755:48] wire _read_sstatus_WIRE_sum = 1'h0; // @[CSR.scala:755:48] wire _read_sstatus_WIRE_mprv = 1'h0; // @[CSR.scala:755:48] wire _read_sstatus_WIRE_spp = 1'h0; // @[CSR.scala:755:48] wire _read_sstatus_WIRE_mpie = 1'h0; // @[CSR.scala:755:48] wire _read_sstatus_WIRE_ube = 1'h0; // @[CSR.scala:755:48] wire _read_sstatus_WIRE_spie = 1'h0; // @[CSR.scala:755:48] wire _read_sstatus_WIRE_upie = 1'h0; // @[CSR.scala:755:48] wire _read_sstatus_WIRE_mie = 1'h0; // @[CSR.scala:755:48] wire _read_sstatus_WIRE_hie = 1'h0; // @[CSR.scala:755:48] wire _read_sstatus_WIRE_sie = 1'h0; // @[CSR.scala:755:48] wire _read_sstatus_WIRE_uie = 1'h0; // @[CSR.scala:755:48] wire read_sstatus_debug = 1'h0; // @[CSR.scala:755:35] wire read_sstatus_cease = 1'h0; // @[CSR.scala:755:35] wire read_sstatus_wfi = 1'h0; // @[CSR.scala:755:35] wire read_sstatus_dv = 1'h0; // @[CSR.scala:755:35] wire read_sstatus_v = 1'h0; // @[CSR.scala:755:35] wire read_sstatus_mpv = 1'h0; // @[CSR.scala:755:35] wire read_sstatus_gva = 1'h0; // @[CSR.scala:755:35] wire read_sstatus_mbe = 1'h0; // @[CSR.scala:755:35] wire read_sstatus_sbe = 1'h0; // @[CSR.scala:755:35] wire read_sstatus_sd_rv32 = 1'h0; // @[CSR.scala:755:35] wire read_sstatus_tsr = 1'h0; // @[CSR.scala:755:35] wire read_sstatus_tw = 1'h0; // @[CSR.scala:755:35] wire read_sstatus_tvm = 1'h0; // @[CSR.scala:755:35] wire read_sstatus_mprv = 1'h0; // @[CSR.scala:755:35] wire read_sstatus_mpie = 1'h0; // @[CSR.scala:755:35] wire read_sstatus_ube = 1'h0; // @[CSR.scala:755:35] wire read_sstatus_upie = 1'h0; // @[CSR.scala:755:35] wire read_sstatus_mie = 1'h0; // @[CSR.scala:755:35] wire read_sstatus_hie = 1'h0; // @[CSR.scala:755:35] wire read_sstatus_uie = 1'h0; // @[CSR.scala:755:35] wire read_pmp_15_cfg_l = 1'h0; // @[CSR.scala:787:59] wire read_pmp_15_cfg_x = 1'h0; // @[CSR.scala:787:59] wire read_pmp_15_cfg_w = 1'h0; // @[CSR.scala:787:59] wire read_pmp_15_cfg_r = 1'h0; // @[CSR.scala:787:59] wire _reg_custom_T = 1'h0; // @[CSR.scala:801:16] wire _reg_custom_T_1 = 1'h0; // @[CSR.scala:801:16] wire _allow_counter_T_4 = 1'h0; // @[CSR.scala:913:8] wire _io_decode_0_fp_illegal_T_1 = 1'h0; // @[CSR.scala:915:83] wire _io_decode_0_fp_illegal_T_2 = 1'h0; // @[CSR.scala:915:64] wire _io_decode_0_fp_illegal_T_5 = 1'h0; // @[CSR.scala:915:94] wire _io_decode_0_vector_illegal_T_4 = 1'h0; // @[CSR.scala:916:107] wire io_decode_0_vector_csr_plaOutput = 1'h0; // @[pla.scala:81:23] wire _io_decode_0_vector_csr_T = 1'h0; // @[Decode.scala:55:116] wire _io_decode_0_rocc_illegal_T_4 = 1'h0; // @[CSR.scala:919:105] wire _csr_addr_legal_T_3 = 1'h0; // @[CSR.scala:921:25] wire _csr_addr_legal_T_5 = 1'h0; // @[CSR.scala:921:43] wire _csr_addr_legal_T_8 = 1'h0; // @[CSR.scala:921:74] wire io_decode_0_read_illegal_plaOutput_1 = 1'h0; // @[pla.scala:81:23] wire _io_decode_0_read_illegal_T_16 = 1'h0; // @[Decode.scala:55:116] wire _io_decode_0_read_illegal_T_17 = 1'h0; // @[CSR.scala:928:43] wire _io_decode_0_system_illegal_T_20 = 1'h0; // @[CSR.scala:940:25] wire _io_decode_0_system_illegal_T_21 = 1'h0; // @[CSR.scala:940:22] wire _io_decode_0_system_illegal_T_23 = 1'h0; // @[CSR.scala:941:18] wire _io_decode_0_system_illegal_T_24 = 1'h0; // @[CSR.scala:941:15] wire _io_decode_0_virtual_access_illegal_T_27 = 1'h0; // @[CSR.scala:947:50] wire _io_decode_0_virtual_system_illegal_T_5 = 1'h0; // @[CSR.scala:953:57] wire trapToNmiInt = 1'h0; // @[CSR.scala:990:33] wire _trapToNmiXcpt_T = 1'h0; // @[CSR.scala:991:37] wire trapToNmiXcpt = 1'h0; // @[CSR.scala:991:34] wire trapToNmi = 1'h0; // @[CSR.scala:992:32] wire _nmiTVec_T = 1'h0; // @[CSR.scala:993:21] wire _nmiTVec_T_1 = 1'h0; // @[CSR.scala:993:58] wire _io_status_sd_T_1 = 1'h0; // @[CSR.scala:1003:53] wire _io_status_sd_T_3 = 1'h0; // @[CSR.scala:1003:74] wire _io_status_sd_rv32_T = 1'h0; // @[CSR.scala:1010:39] wire _io_gstatus_sd_T_1 = 1'h0; // @[CSR.scala:1016:56] wire _io_gstatus_sd_rv32_T = 1'h0; // @[CSR.scala:1018:40] wire _en_T_1 = 1'h0; // @[CSR.scala:1096:71] wire _en_T_2 = 1'h0; // @[CSR.scala:1096:24] wire en = 1'h0; // @[CSR.scala:1096:79] wire delegable = 1'h0; // @[CSR.scala:1097:65] wire _en_T_13 = 1'h0; // @[CSR.scala:1096:71] wire _en_T_14 = 1'h0; // @[CSR.scala:1096:24] wire en_2 = 1'h0; // @[CSR.scala:1096:79] wire delegable_2 = 1'h0; // @[CSR.scala:1097:65] wire delegable_3 = 1'h0; // @[CSR.scala:1097:65] wire _en_T_25 = 1'h0; // @[CSR.scala:1096:71] wire _en_T_26 = 1'h0; // @[CSR.scala:1096:24] wire en_4 = 1'h0; // @[CSR.scala:1096:79] wire delegable_4 = 1'h0; // @[CSR.scala:1097:65] wire _en_T_37 = 1'h0; // @[CSR.scala:1096:71] wire _en_T_38 = 1'h0; // @[CSR.scala:1096:24] wire en_6 = 1'h0; // @[CSR.scala:1096:79] wire delegable_6 = 1'h0; // @[CSR.scala:1097:65] wire delegable_7 = 1'h0; // @[CSR.scala:1097:65] wire _en_T_49 = 1'h0; // @[CSR.scala:1096:71] wire _en_T_50 = 1'h0; // @[CSR.scala:1096:24] wire en_8 = 1'h0; // @[CSR.scala:1096:79] wire delegable_8 = 1'h0; // @[CSR.scala:1097:65] wire _en_T_61 = 1'h0; // @[CSR.scala:1096:71] wire _en_T_62 = 1'h0; // @[CSR.scala:1096:24] wire en_10 = 1'h0; // @[CSR.scala:1096:79] wire delegable_10 = 1'h0; // @[CSR.scala:1097:65] wire delegable_11 = 1'h0; // @[CSR.scala:1097:65] wire _en_T_73 = 1'h0; // @[CSR.scala:1096:71] wire _en_T_74 = 1'h0; // @[CSR.scala:1096:24] wire en_12 = 1'h0; // @[CSR.scala:1096:79] wire delegable_12 = 1'h0; // @[CSR.scala:1097:65] wire _en_T_79 = 1'h0; // @[CSR.scala:1096:71] wire _en_T_80 = 1'h0; // @[CSR.scala:1096:24] wire en_13 = 1'h0; // @[CSR.scala:1096:79] wire delegable_13 = 1'h0; // @[CSR.scala:1097:65] wire _en_T_85 = 1'h0; // @[CSR.scala:1096:71] wire _en_T_86 = 1'h0; // @[CSR.scala:1096:24] wire en_14 = 1'h0; // @[CSR.scala:1096:79] wire delegable_14 = 1'h0; // @[CSR.scala:1097:65] wire _en_T_91 = 1'h0; // @[CSR.scala:1096:71] wire _en_T_92 = 1'h0; // @[CSR.scala:1096:24] wire en_15 = 1'h0; // @[CSR.scala:1096:79] wire delegable_15 = 1'h0; // @[CSR.scala:1097:65] wire delegable_16 = 1'h0; // @[CSR.scala:1109:67] wire delegable_20 = 1'h0; // @[CSR.scala:1109:67] wire delegable_22 = 1'h0; // @[CSR.scala:1109:67] wire delegable_24 = 1'h0; // @[CSR.scala:1109:67] wire delegable_25 = 1'h0; // @[CSR.scala:1109:67] wire _reg_mstatus_v_T = 1'h0; // @[CSR.scala:1123:44] wire _reg_mstatus_v_T_1 = 1'h0; // @[CSR.scala:1136:42] wire _reg_mstatus_v_T_3 = 1'h0; // @[CSR.scala:1136:56] wire _reg_mstatus_v_T_4 = 1'h0; // @[CSR.scala:1141:42] wire _reg_mstatus_v_T_5 = 1'h0; // @[CSR.scala:1141:82] wire _reg_mstatus_v_T_6 = 1'h0; // @[CSR.scala:1141:62] wire _reg_mstatus_mpp_T = 1'h0; // @[CSR.scala:1647:35] wire _reg_mstatus_mpp_T_1 = 1'h0; // @[CSR.scala:1647:29] wire _reg_mstatus_v_T_7 = 1'h0; // @[CSR.scala:1150:42] wire _reg_mstatus_v_T_9 = 1'h0; // @[CSR.scala:1150:61] wire _io_rw_rdata_T = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_29 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_30 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_31 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_32 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_33 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_34 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_35 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_36 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_37 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_38 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_39 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_40 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_41 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_42 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_43 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_44 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_45 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_46 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_47 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_48 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_49 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_50 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_51 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_52 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_53 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_54 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_55 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_56 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_57 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_58 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_59 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_60 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_61 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_62 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_63 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_64 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_65 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_66 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_67 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_68 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_69 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_70 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_71 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_72 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_73 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_74 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_75 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_76 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_77 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_78 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_79 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_80 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_81 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_82 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_83 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_84 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_85 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_86 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_87 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_88 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_89 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_90 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_91 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_92 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_93 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_94 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_95 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_96 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_97 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_98 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_99 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_100 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_101 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_102 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_103 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_104 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_105 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_106 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_107 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_108 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_109 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_147 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_148 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_149 = 1'h0; // @[Mux.scala:30:73] wire set_vs_dirty = 1'h0; // @[CSR.scala:1191:33] wire new_mip_hi_hi_hi_hi = 1'h0; // @[CSR.scala:1271:59] wire _reg_bp_0_WIRE_control_dmode = 1'h0; // @[CSR.scala:1613:23] wire _reg_bp_0_WIRE_control_action = 1'h0; // @[CSR.scala:1613:23] wire _reg_bp_0_WIRE_control_chain = 1'h0; // @[CSR.scala:1613:23] wire _reg_bp_0_WIRE_control_m = 1'h0; // @[CSR.scala:1613:23] wire _reg_bp_0_WIRE_control_h = 1'h0; // @[CSR.scala:1613:23] wire _reg_bp_0_WIRE_control_s = 1'h0; // @[CSR.scala:1613:23] wire _reg_bp_0_WIRE_control_u = 1'h0; // @[CSR.scala:1613:23] wire _reg_bp_0_WIRE_control_x = 1'h0; // @[CSR.scala:1613:23] wire _reg_bp_0_WIRE_control_w = 1'h0; // @[CSR.scala:1613:23] wire _reg_bp_0_WIRE_control_r = 1'h0; // @[CSR.scala:1613:23] wire _reg_bp_0_WIRE_textra_mselect = 1'h0; // @[CSR.scala:1613:23] wire _reg_bp_0_WIRE_textra_pad1 = 1'h0; // @[CSR.scala:1613:23] wire _reg_bp_0_WIRE_textra_sselect = 1'h0; // @[CSR.scala:1613:23] wire _reg_bp_1_WIRE_control_dmode = 1'h0; // @[CSR.scala:1613:23] wire _reg_bp_1_WIRE_control_action = 1'h0; // @[CSR.scala:1613:23] wire _reg_bp_1_WIRE_control_chain = 1'h0; // @[CSR.scala:1613:23] wire _reg_bp_1_WIRE_control_m = 1'h0; // @[CSR.scala:1613:23] wire _reg_bp_1_WIRE_control_h = 1'h0; // @[CSR.scala:1613:23] wire _reg_bp_1_WIRE_control_s = 1'h0; // @[CSR.scala:1613:23] wire _reg_bp_1_WIRE_control_u = 1'h0; // @[CSR.scala:1613:23] wire _reg_bp_1_WIRE_control_x = 1'h0; // @[CSR.scala:1613:23] wire _reg_bp_1_WIRE_control_w = 1'h0; // @[CSR.scala:1613:23] wire _reg_bp_1_WIRE_control_r = 1'h0; // @[CSR.scala:1613:23] wire _reg_bp_1_WIRE_textra_mselect = 1'h0; // @[CSR.scala:1613:23] wire _reg_bp_1_WIRE_textra_pad1 = 1'h0; // @[CSR.scala:1613:23] wire _reg_bp_1_WIRE_textra_sselect = 1'h0; // @[CSR.scala:1613:23] wire [7:0] io_status_zero1 = 8'h0; // @[CSR.scala:377:7] wire [7:0] io_gstatus_zero1 = 8'h0; // @[CSR.scala:377:7] wire [7:0] _reset_mstatus_WIRE_zero1 = 8'h0; // @[CSR.scala:391:47] wire [7:0] reset_mstatus_zero1 = 8'h0; // @[CSR.scala:391:34] wire [7:0] lo_2 = 8'h0; // @[CSR.scala:479:12] wire [7:0] hi_2 = 8'h0; // @[CSR.scala:479:12] wire [7:0] lo_3 = 8'h0; // @[CSR.scala:479:27] wire [7:0] hi_3 = 8'h0; // @[CSR.scala:479:27] wire [7:0] sie_mask_lo = 8'h0; // @[CSR.scala:750:59] wire [7:0] _read_sstatus_WIRE_zero1 = 8'h0; // @[CSR.scala:755:48] wire [7:0] read_sstatus_zero1 = 8'h0; // @[CSR.scala:755:35] wire [1:0] io_status_xs = 2'h0; // @[CSR.scala:377:7] wire [1:0] io_status_vs = 2'h0; // @[CSR.scala:377:7] wire [1:0] io_hstatus_zero3 = 2'h0; // @[CSR.scala:377:7] wire [1:0] io_hstatus_zero2 = 2'h0; // @[CSR.scala:377:7] wire [1:0] io_gstatus_dprv = 2'h0; // @[CSR.scala:377:7] wire [1:0] io_gstatus_prv = 2'h0; // @[CSR.scala:377:7] wire [1:0] io_gstatus_sxl = 2'h0; // @[CSR.scala:377:7] wire [1:0] io_gstatus_xs = 2'h0; // @[CSR.scala:377:7] wire [1:0] io_gstatus_mpp = 2'h0; // @[CSR.scala:377:7] wire [1:0] io_gstatus_vs = 2'h0; // @[CSR.scala:377:7] wire [1:0] io_pmp_0_cfg_res = 2'h0; // @[CSR.scala:377:7] wire [1:0] io_pmp_1_cfg_res = 2'h0; // @[CSR.scala:377:7] wire [1:0] io_pmp_2_cfg_res = 2'h0; // @[CSR.scala:377:7] wire [1:0] io_pmp_3_cfg_res = 2'h0; // @[CSR.scala:377:7] wire [1:0] io_pmp_4_cfg_res = 2'h0; // @[CSR.scala:377:7] wire [1:0] io_pmp_5_cfg_res = 2'h0; // @[CSR.scala:377:7] wire [1:0] io_pmp_6_cfg_res = 2'h0; // @[CSR.scala:377:7] wire [1:0] io_pmp_7_cfg_res = 2'h0; // @[CSR.scala:377:7] wire [1:0] _reset_mstatus_WIRE_dprv = 2'h0; // @[CSR.scala:391:47] wire [1:0] _reset_mstatus_WIRE_prv = 2'h0; // @[CSR.scala:391:47] wire [1:0] _reset_mstatus_WIRE_sxl = 2'h0; // @[CSR.scala:391:47] wire [1:0] _reset_mstatus_WIRE_uxl = 2'h0; // @[CSR.scala:391:47] wire [1:0] _reset_mstatus_WIRE_xs = 2'h0; // @[CSR.scala:391:47] wire [1:0] _reset_mstatus_WIRE_fs = 2'h0; // @[CSR.scala:391:47] wire [1:0] _reset_mstatus_WIRE_mpp = 2'h0; // @[CSR.scala:391:47] wire [1:0] _reset_mstatus_WIRE_vs = 2'h0; // @[CSR.scala:391:47] wire [1:0] reset_mstatus_dprv = 2'h0; // @[CSR.scala:391:34] wire [1:0] reset_mstatus_sxl = 2'h0; // @[CSR.scala:391:34] wire [1:0] reset_mstatus_uxl = 2'h0; // @[CSR.scala:391:34] wire [1:0] reset_mstatus_xs = 2'h0; // @[CSR.scala:391:34] wire [1:0] reset_mstatus_fs = 2'h0; // @[CSR.scala:391:34] wire [1:0] reset_mstatus_vs = 2'h0; // @[CSR.scala:391:34] wire [1:0] _reset_dcsr_WIRE_xdebugver = 2'h0; // @[CSR.scala:400:44] wire [1:0] _reset_dcsr_WIRE_zero4 = 2'h0; // @[CSR.scala:400:44] wire [1:0] _reset_dcsr_WIRE_zero1 = 2'h0; // @[CSR.scala:400:44] wire [1:0] _reset_dcsr_WIRE_prv = 2'h0; // @[CSR.scala:400:44] wire [1:0] reset_dcsr_zero4 = 2'h0; // @[CSR.scala:400:31] wire [1:0] reset_dcsr_zero1 = 2'h0; // @[CSR.scala:400:31] wire [1:0] hi_hi_lo = 2'h0; // @[CSR.scala:431:10] wire [1:0] hi_hi_hi = 2'h0; // @[CSR.scala:431:10] wire [1:0] lo_lo_hi_1 = 2'h0; // @[CSR.scala:431:50] wire [1:0] lo_hi_hi_1 = 2'h0; // @[CSR.scala:431:50] wire [1:0] hi_lo_hi_1 = 2'h0; // @[CSR.scala:431:50] wire [1:0] hi_hi_lo_1 = 2'h0; // @[CSR.scala:431:50] wire [1:0] hi_hi_hi_1 = 2'h0; // @[CSR.scala:431:50] wire [1:0] lo_lo_lo_2 = 2'h0; // @[CSR.scala:479:12] wire [1:0] lo_lo_hi_2 = 2'h0; // @[CSR.scala:479:12] wire [1:0] lo_hi_lo_2 = 2'h0; // @[CSR.scala:479:12] wire [1:0] lo_hi_hi_2 = 2'h0; // @[CSR.scala:479:12] wire [1:0] hi_lo_lo_2 = 2'h0; // @[CSR.scala:479:12] wire [1:0] hi_lo_hi_2 = 2'h0; // @[CSR.scala:479:12] wire [1:0] hi_hi_lo_2 = 2'h0; // @[CSR.scala:479:12] wire [1:0] hi_hi_hi_2 = 2'h0; // @[CSR.scala:479:12] wire [1:0] lo_lo_lo_3 = 2'h0; // @[CSR.scala:479:27] wire [1:0] lo_lo_hi_3 = 2'h0; // @[CSR.scala:479:27] wire [1:0] lo_hi_lo_3 = 2'h0; // @[CSR.scala:479:27] wire [1:0] lo_hi_hi_3 = 2'h0; // @[CSR.scala:479:27] wire [1:0] hi_lo_lo_3 = 2'h0; // @[CSR.scala:479:27] wire [1:0] hi_lo_hi_3 = 2'h0; // @[CSR.scala:479:27] wire [1:0] hi_hi_lo_3 = 2'h0; // @[CSR.scala:479:27] wire [1:0] hi_hi_hi_3 = 2'h0; // @[CSR.scala:479:27] wire [1:0] _reset_mnstatus_WIRE_mpp = 2'h0; // @[CSR.scala:516:48] wire [1:0] _reg_menvcfg_WIRE_cbie = 2'h0; // @[CSR.scala:525:41] wire [1:0] _reg_senvcfg_WIRE_cbie = 2'h0; // @[CSR.scala:526:41] wire [1:0] _reg_henvcfg_WIRE_cbie = 2'h0; // @[CSR.scala:527:41] wire [1:0] _reg_hstatus_WIRE_vsxl = 2'h0; // @[CSR.scala:552:41] wire [1:0] _reg_hstatus_WIRE_zero3 = 2'h0; // @[CSR.scala:552:41] wire [1:0] _reg_hstatus_WIRE_zero2 = 2'h0; // @[CSR.scala:552:41] wire [1:0] read_hvip_lo_lo_hi = 2'h0; // @[CSR.scala:555:27] wire [1:0] read_hvip_lo_hi_hi = 2'h0; // @[CSR.scala:555:27] wire [1:0] read_hvip_hi_lo_hi = 2'h0; // @[CSR.scala:555:27] wire [1:0] read_hvip_hi_hi_lo = 2'h0; // @[CSR.scala:555:27] wire [1:0] pmp_cfg_res = 2'h0; // @[PMP.scala:24:19] wire [1:0] pmp_1_cfg_res = 2'h0; // @[PMP.scala:24:19] wire [1:0] pmp_2_cfg_res = 2'h0; // @[PMP.scala:24:19] wire [1:0] pmp_3_cfg_res = 2'h0; // @[PMP.scala:24:19] wire [1:0] pmp_4_cfg_res = 2'h0; // @[PMP.scala:24:19] wire [1:0] pmp_5_cfg_res = 2'h0; // @[PMP.scala:24:19] wire [1:0] pmp_6_cfg_res = 2'h0; // @[PMP.scala:24:19] wire [1:0] pmp_7_cfg_res = 2'h0; // @[PMP.scala:24:19] wire [1:0] read_mapping_lo_lo_hi = 2'h0; // @[CSR.scala:655:48] wire [1:0] read_mapping_lo_hi_lo = 2'h0; // @[CSR.scala:655:48] wire [1:0] read_mapping_lo_hi_hi = 2'h0; // @[CSR.scala:655:48] wire [1:0] read_mapping_hi_lo_hi = 2'h0; // @[CSR.scala:655:48] wire [1:0] read_mapping_lo_1 = 2'h0; // @[CSR.scala:657:47] wire [1:0] debug_csrs_lo_hi_hi = 2'h0; // @[CSR.scala:670:27] wire [1:0] _read_mnstatus_WIRE_mpp = 2'h0; // @[CSR.scala:675:44] wire [1:0] read_vcsr = 2'h0; // @[CSR.scala:695:22] wire [1:0] hi_hi_4 = 2'h0; // @[CSR.scala:742:49] wire [1:0] sie_mask_lo_lo_lo = 2'h0; // @[CSR.scala:750:59] wire [1:0] sie_mask_lo_lo_hi = 2'h0; // @[CSR.scala:750:59] wire [1:0] sie_mask_lo_hi_lo = 2'h0; // @[CSR.scala:750:59] wire [1:0] sie_mask_lo_hi_hi = 2'h0; // @[CSR.scala:750:59] wire [1:0] sie_mask_hi_lo_lo = 2'h0; // @[CSR.scala:750:59] wire [1:0] sie_mask_hi_lo_hi = 2'h0; // @[CSR.scala:750:59] wire [1:0] sie_mask_hi_hi_hi = 2'h0; // @[CSR.scala:750:59] wire [1:0] _read_sstatus_WIRE_dprv = 2'h0; // @[CSR.scala:755:48] wire [1:0] _read_sstatus_WIRE_prv = 2'h0; // @[CSR.scala:755:48] wire [1:0] _read_sstatus_WIRE_sxl = 2'h0; // @[CSR.scala:755:48] wire [1:0] _read_sstatus_WIRE_uxl = 2'h0; // @[CSR.scala:755:48] wire [1:0] _read_sstatus_WIRE_xs = 2'h0; // @[CSR.scala:755:48] wire [1:0] _read_sstatus_WIRE_fs = 2'h0; // @[CSR.scala:755:48] wire [1:0] _read_sstatus_WIRE_mpp = 2'h0; // @[CSR.scala:755:48] wire [1:0] _read_sstatus_WIRE_vs = 2'h0; // @[CSR.scala:755:48] wire [1:0] read_sstatus_dprv = 2'h0; // @[CSR.scala:755:35] wire [1:0] read_sstatus_prv = 2'h0; // @[CSR.scala:755:35] wire [1:0] read_sstatus_sxl = 2'h0; // @[CSR.scala:755:35] wire [1:0] read_sstatus_xs = 2'h0; // @[CSR.scala:755:35] wire [1:0] read_sstatus_mpp = 2'h0; // @[CSR.scala:755:35] wire [1:0] read_sstatus_vs = 2'h0; // @[CSR.scala:755:35] wire [1:0] lo_lo_lo_hi = 2'h0; // @[CSR.scala:768:51] wire [1:0] lo_hi_hi_hi_hi = 2'h0; // @[CSR.scala:768:51] wire [1:0] hi_lo_hi_hi_hi = 2'h0; // @[CSR.scala:768:51] wire [1:0] hi_hi_hi_hi_hi = 2'h0; // @[CSR.scala:768:51] wire [1:0] hi_hi_6 = 2'h0; // @[CSR.scala:780:49] wire [1:0] read_pmp_15_cfg_res = 2'h0; // @[CSR.scala:787:59] wire [1:0] read_pmp_15_cfg_a = 2'h0; // @[CSR.scala:787:59] wire [1:0] lo_hi_16 = 2'h0; // @[package.scala:45:36] wire [1:0] lo_hi_17 = 2'h0; // @[package.scala:45:36] wire [1:0] lo_hi_18 = 2'h0; // @[package.scala:45:36] wire [1:0] lo_hi_19 = 2'h0; // @[package.scala:45:36] wire [1:0] lo_hi_20 = 2'h0; // @[package.scala:45:36] wire [1:0] lo_hi_21 = 2'h0; // @[package.scala:45:36] wire [1:0] lo_hi_22 = 2'h0; // @[package.scala:45:36] wire [1:0] lo_hi_23 = 2'h0; // @[package.scala:45:36] wire [1:0] decoded_orMatrixOutputs_lo_lo = 2'h0; // @[pla.scala:102:36] wire [1:0] decoded_orMatrixOutputs_lo_lo_1 = 2'h0; // @[pla.scala:102:36] wire [1:0] nmiTVec = 2'h0; // @[CSR.scala:993:62] wire [1:0] new_mip_lo_lo_hi = 2'h0; // @[CSR.scala:1271:59] wire [1:0] new_mip_lo_hi_hi = 2'h0; // @[CSR.scala:1271:59] wire [1:0] new_mip_hi_lo_hi = 2'h0; // @[CSR.scala:1271:59] wire [1:0] new_mip_hi_hi_lo = 2'h0; // @[CSR.scala:1271:59] wire [1:0] _reg_bp_0_WIRE_control_zero = 2'h0; // @[CSR.scala:1613:23] wire [1:0] _reg_bp_0_WIRE_control_tmatch = 2'h0; // @[CSR.scala:1613:23] wire [1:0] _reg_bp_1_WIRE_control_zero = 2'h0; // @[CSR.scala:1613:23] wire [1:0] _reg_bp_1_WIRE_control_tmatch = 2'h0; // @[CSR.scala:1613:23] wire [15:0] io_ptbr_asid = 16'h0; // @[CSR.scala:377:7] wire [15:0] io_hgatp_asid = 16'h0; // @[CSR.scala:377:7] wire [15:0] io_vsatp_asid = 16'h0; // @[CSR.scala:377:7] wire [15:0] hs_delegable_interrupts = 16'h0; // @[CSR.scala:479:12] wire [15:0] mideleg_always_hs = 16'h0; // @[CSR.scala:479:27] wire [15:0] read_hvip = 16'h0; // @[CSR.scala:555:34] wire [15:0] read_hip = 16'h0; // @[CSR.scala:611:27] wire [15:0] lo_lo_8 = 16'h0; // @[package.scala:45:27] wire [15:0] lo_hi_24 = 16'h0; // @[package.scala:45:27] wire [15:0] hi_lo_8 = 16'h0; // @[package.scala:45:27] wire [15:0] hi_hi_24 = 16'h0; // @[package.scala:45:27] wire [15:0] _en_T = 16'h0; // @[CSR.scala:1096:49] wire [15:0] _delegable_T = 16'h0; // @[CSR.scala:1097:43] wire [15:0] _en_T_12 = 16'h0; // @[CSR.scala:1096:49] wire [15:0] _delegable_T_2 = 16'h0; // @[CSR.scala:1097:43] wire [15:0] _delegable_T_3 = 16'h0; // @[CSR.scala:1097:43] wire [15:0] _en_T_24 = 16'h0; // @[CSR.scala:1096:49] wire [15:0] _delegable_T_4 = 16'h0; // @[CSR.scala:1097:43] wire [15:0] _en_T_36 = 16'h0; // @[CSR.scala:1096:49] wire [15:0] _delegable_T_6 = 16'h0; // @[CSR.scala:1097:43] wire [15:0] _delegable_T_7 = 16'h0; // @[CSR.scala:1097:43] wire [15:0] _en_T_48 = 16'h0; // @[CSR.scala:1096:49] wire [15:0] _delegable_T_8 = 16'h0; // @[CSR.scala:1097:43] wire [15:0] _en_T_60 = 16'h0; // @[CSR.scala:1096:49] wire [15:0] _delegable_T_10 = 16'h0; // @[CSR.scala:1097:43] wire [15:0] _delegable_T_11 = 16'h0; // @[CSR.scala:1097:43] wire [15:0] _en_T_72 = 16'h0; // @[CSR.scala:1096:49] wire [15:0] _delegable_T_12 = 16'h0; // @[CSR.scala:1097:43] wire [15:0] _en_T_78 = 16'h0; // @[CSR.scala:1096:49] wire [15:0] _delegable_T_13 = 16'h0; // @[CSR.scala:1097:43] wire [15:0] _en_T_84 = 16'h0; // @[CSR.scala:1096:49] wire [15:0] _delegable_T_14 = 16'h0; // @[CSR.scala:1097:43] wire [15:0] _en_T_90 = 16'h0; // @[CSR.scala:1096:49] wire [15:0] _delegable_T_15 = 16'h0; // @[CSR.scala:1097:43] wire [15:0] _delegable_T_16 = 16'h0; // @[CSR.scala:1109:45] wire [15:0] _delegable_T_20 = 16'h0; // @[CSR.scala:1109:45] wire [15:0] _delegable_T_22 = 16'h0; // @[CSR.scala:1109:45] wire [15:0] _delegable_T_24 = 16'h0; // @[CSR.scala:1109:45] wire [15:0] _delegable_T_25 = 16'h0; // @[CSR.scala:1109:45] wire [5:0] io_hstatus_vgein = 6'h0; // @[CSR.scala:377:7] wire [5:0] _reg_hstatus_WIRE_vgein = 6'h0; // @[CSR.scala:552:41] wire [5:0] read_mapping_hi_lo = 6'h0; // @[CSR.scala:655:48] wire [5:0] hi_lo_hi_4 = 6'h0; // @[CSR.scala:768:51] wire [5:0] _reg_bp_0_WIRE_control_maskmax = 6'h0; // @[CSR.scala:1613:23] wire [5:0] _reg_bp_1_WIRE_control_maskmax = 6'h0; // @[CSR.scala:1613:23] wire [3:0] io_hgatp_mode = 4'h0; // @[CSR.scala:377:7] wire [3:0] io_vsatp_mode = 4'h0; // @[CSR.scala:377:7] wire [3:0] hi_hi = 4'h0; // @[CSR.scala:431:10] wire [3:0] hi_hi_1 = 4'h0; // @[CSR.scala:431:50] wire [3:0] lo_lo_2 = 4'h0; // @[CSR.scala:479:12] wire [3:0] lo_hi_2 = 4'h0; // @[CSR.scala:479:12] wire [3:0] hi_lo_2 = 4'h0; // @[CSR.scala:479:12] wire [3:0] hi_hi_2 = 4'h0; // @[CSR.scala:479:12] wire [3:0] lo_lo_3 = 4'h0; // @[CSR.scala:479:27] wire [3:0] lo_hi_3 = 4'h0; // @[CSR.scala:479:27] wire [3:0] hi_lo_3 = 4'h0; // @[CSR.scala:479:27] wire [3:0] hi_hi_3 = 4'h0; // @[CSR.scala:479:27] wire [3:0] read_mapping_lo_hi = 4'h0; // @[CSR.scala:655:48] wire [3:0] read_mapping_hi_lo_lo = 4'h0; // @[CSR.scala:655:48] wire [3:0] sie_mask_lo_lo = 4'h0; // @[CSR.scala:750:59] wire [3:0] sie_mask_lo_hi = 4'h0; // @[CSR.scala:750:59] wire [3:0] sie_mask_hi_lo = 4'h0; // @[CSR.scala:750:59] wire [3:0] lo_hi_lo_lo = 4'h0; // @[CSR.scala:768:51] wire [3:0] hi_hi_lo_hi = 4'h0; // @[CSR.scala:768:51] wire [3:0] _reg_bp_0_WIRE_control_ttype = 4'h0; // @[CSR.scala:1613:23] wire [3:0] _reg_bp_1_WIRE_control_ttype = 4'h0; // @[CSR.scala:1613:23] wire [63:0] io_customCSRs_0_sdata = 64'h0; // @[CSR.scala:377:7] wire [63:0] io_customCSRs_1_sdata = 64'h0; // @[CSR.scala:377:7] wire [63:0] read_hideleg = 64'h0; // @[CSR.scala:541:14] wire [63:0] read_hedeleg = 64'h0; // @[CSR.scala:545:14] wire [63:0] read_hie = 64'h0; // @[CSR.scala:556:26] wire [63:0] read_vstvec = 64'h0; // @[package.scala:132:15] wire [63:0] _vs_interrupts_T_6 = 64'h0; // @[CSR.scala:622:153] wire [63:0] vs_interrupts = 64'h0; // @[CSR.scala:622:26] wire [63:0] read_mapping_1_2 = 64'h0; // @[CSR.scala:655:48] wire [63:0] read_mapping_2_2 = 64'h0; // @[package.scala:132:15] wire [63:0] _io_rw_rdata_T_1 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_2 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_128 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_150 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_151 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_152 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _reg_custom_1_T = 64'h0; // @[CSR.scala:1506:23] wire [63:0] _reg_custom_0_T_4 = 64'h0; // @[CSR.scala:1531:24] wire [63:0] _reg_custom_1_T_4 = 64'h0; // @[CSR.scala:1531:24] wire [29:0] io_hstatus_zero6 = 30'h0; // @[CSR.scala:377:7] wire [29:0] _reg_hstatus_WIRE_zero6 = 30'h0; // @[CSR.scala:552:41] wire [29:0] read_pmp_15_addr = 30'h0; // @[CSR.scala:787:59] wire [29:0] _io_rw_rdata_T_137 = 30'h0; // @[Mux.scala:30:73] wire [29:0] _io_rw_rdata_T_138 = 30'h0; // @[Mux.scala:30:73] wire [29:0] _io_rw_rdata_T_139 = 30'h0; // @[Mux.scala:30:73] wire [29:0] _io_rw_rdata_T_140 = 30'h0; // @[Mux.scala:30:73] wire [29:0] _io_rw_rdata_T_141 = 30'h0; // @[Mux.scala:30:73] wire [29:0] _io_rw_rdata_T_142 = 30'h0; // @[Mux.scala:30:73] wire [29:0] _io_rw_rdata_T_143 = 30'h0; // @[Mux.scala:30:73] wire [29:0] _io_rw_rdata_T_144 = 30'h0; // @[Mux.scala:30:73] wire [50:0] read_mapping_hi_hi = 51'h0; // @[CSR.scala:655:48] wire [50:0] read_mapping_3_2 = 51'h0; // @[CSR.scala:657:47] wire [50:0] _io_rw_rdata_T_3 = 51'h0; // @[Mux.scala:30:73] wire [1:0] reset_dcsr_xdebugver = 2'h1; // @[CSR.scala:400:31] wire [1:0] _read_mapping_T_4 = 2'h1; // @[CSR.scala:1665:36] wire [1:0] _debug_csrs_T_2 = 2'h1; // @[CSR.scala:1665:36] wire [1:0] sie_mask_hi_hi_lo = 2'h1; // @[CSR.scala:750:59] wire [1:0] _io_evec_T_2 = 2'h1; // @[CSR.scala:1665:36] wire [1:0] _io_evec_T_7 = 2'h1; // @[CSR.scala:1665:36] wire [1:0] _io_evec_T_12 = 2'h1; // @[CSR.scala:1665:36] wire [1:0] _io_evec_T_17 = 2'h1; // @[CSR.scala:1665:36] wire [1:0] _io_evec_T_22 = 2'h1; // @[CSR.scala:1665:36] wire [4:0] io_hstatus_zero1 = 5'h0; // @[CSR.scala:377:7] wire [4:0] _reg_hstatus_WIRE_zero1 = 5'h0; // @[CSR.scala:552:41] wire [4:0] read_mapping_hi_hi_hi = 5'h0; // @[CSR.scala:655:48] wire [4:0] hi_19 = 5'h0; // @[package.scala:45:36] wire [4:0] hi_20 = 5'h0; // @[package.scala:45:36] wire [4:0] hi_21 = 5'h0; // @[package.scala:45:36] wire [4:0] hi_22 = 5'h0; // @[package.scala:45:36] wire [4:0] hi_23 = 5'h0; // @[package.scala:45:36] wire [4:0] hi_24 = 5'h0; // @[package.scala:45:36] wire [4:0] hi_25 = 5'h0; // @[package.scala:45:36] wire [4:0] hi_26 = 5'h0; // @[package.scala:45:36] wire [2:0] _reset_dcsr_WIRE_cause = 3'h0; // @[CSR.scala:400:44] wire [2:0] reset_dcsr_cause = 3'h0; // @[CSR.scala:400:31] wire [2:0] _reset_mnstatus_WIRE_zero3 = 3'h0; // @[CSR.scala:516:48] wire [2:0] _reset_mnstatus_WIRE_zero2 = 3'h0; // @[CSR.scala:516:48] wire [2:0] _reset_mnstatus_WIRE_zero1 = 3'h0; // @[CSR.scala:516:48] wire [2:0] reset_mnstatus_zero3 = 3'h0; // @[CSR.scala:516:35] wire [2:0] reset_mnstatus_zero2 = 3'h0; // @[CSR.scala:516:35] wire [2:0] reset_mnstatus_zero1 = 3'h0; // @[CSR.scala:516:35] wire [2:0] _reg_menvcfg_WIRE_zero3 = 3'h0; // @[CSR.scala:525:41] wire [2:0] _reg_senvcfg_WIRE_zero3 = 3'h0; // @[CSR.scala:526:41] wire [2:0] _reg_henvcfg_WIRE_zero3 = 3'h0; // @[CSR.scala:527:41] wire [2:0] read_mapping_lo_lo = 3'h0; // @[CSR.scala:655:48] wire [2:0] _read_mnstatus_WIRE_zero3 = 3'h0; // @[CSR.scala:675:44] wire [2:0] _read_mnstatus_WIRE_zero2 = 3'h0; // @[CSR.scala:675:44] wire [2:0] _read_mnstatus_WIRE_zero1 = 3'h0; // @[CSR.scala:675:44] wire [2:0] read_mnstatus_zero3 = 3'h0; // @[CSR.scala:675:31] wire [2:0] read_mnstatus_zero2 = 3'h0; // @[CSR.scala:675:31] wire [2:0] read_mnstatus_zero1 = 3'h0; // @[CSR.scala:675:31] wire [2:0] lo_hi_4 = 3'h0; // @[CSR.scala:742:49] wire [2:0] hi_lo_hi_lo = 3'h0; // @[CSR.scala:768:51] wire [2:0] hi_lo_hi_hi = 3'h0; // @[CSR.scala:768:51] wire [2:0] hi_hi_lo_hi_hi = 3'h0; // @[CSR.scala:768:51] wire [2:0] hi_hi_hi_hi_4 = 3'h0; // @[CSR.scala:768:51] wire [2:0] lo_hi_6 = 3'h0; // @[CSR.scala:780:49] wire [2:0] lo_16 = 3'h0; // @[package.scala:45:36] wire [2:0] hi_hi_16 = 3'h0; // @[package.scala:45:36] wire [2:0] lo_17 = 3'h0; // @[package.scala:45:36] wire [2:0] hi_hi_17 = 3'h0; // @[package.scala:45:36] wire [2:0] lo_18 = 3'h0; // @[package.scala:45:36] wire [2:0] hi_hi_18 = 3'h0; // @[package.scala:45:36] wire [2:0] lo_19 = 3'h0; // @[package.scala:45:36] wire [2:0] hi_hi_19 = 3'h0; // @[package.scala:45:36] wire [2:0] lo_20 = 3'h0; // @[package.scala:45:36] wire [2:0] hi_hi_20 = 3'h0; // @[package.scala:45:36] wire [2:0] lo_21 = 3'h0; // @[package.scala:45:36] wire [2:0] hi_hi_21 = 3'h0; // @[package.scala:45:36] wire [2:0] lo_22 = 3'h0; // @[package.scala:45:36] wire [2:0] hi_hi_22 = 3'h0; // @[package.scala:45:36] wire [2:0] lo_23 = 3'h0; // @[package.scala:45:36] wire [2:0] hi_hi_23 = 3'h0; // @[package.scala:45:36] wire [56:0] read_mapping_hi = 57'h0; // @[CSR.scala:655:48] wire [56:0] hi_6 = 57'h0; // @[CSR.scala:742:49] wire [56:0] hi_9 = 57'h0; // @[CSR.scala:780:49] wire [54:0] hi_lo_4 = 55'h0; // @[CSR.scala:742:49] wire [54:0] hi_lo_6 = 55'h0; // @[CSR.scala:780:49] wire [8:0] io_hstatus_zero5 = 9'h0; // @[CSR.scala:377:7] wire [8:0] _reg_hstatus_WIRE_zero5 = 9'h0; // @[CSR.scala:552:41] wire [8:0] hi_lo_lo_lo = 9'h0; // @[CSR.scala:768:51] wire [1:0] io_gstatus_fs = 2'h3; // @[CSR.scala:377:7] wire [1:0] reset_mstatus_prv = 2'h3; // @[CSR.scala:391:34] wire [1:0] reset_mstatus_mpp = 2'h3; // @[CSR.scala:391:34] wire [1:0] reset_dcsr_prv = 2'h3; // @[CSR.scala:400:31] wire [1:0] reset_mnstatus_mpp = 2'h3; // @[CSR.scala:516:35] wire [1:0] read_mnstatus_mpp = 2'h3; // @[CSR.scala:675:31] wire [3:0] _which_T_64 = 4'h4; // @[Mux.scala:50:70] wire [3:0] _which_T_65 = 4'h4; // @[Mux.scala:50:70] wire [3:0] _which_T_66 = 4'h4; // @[Mux.scala:50:70] wire [3:0] _which_T_67 = 4'h4; // @[Mux.scala:50:70] wire [3:0] _which_T_68 = 4'h4; // @[Mux.scala:50:70] wire [3:0] _which_T_69 = 4'h4; // @[Mux.scala:50:70] wire [3:0] _which_T_70 = 4'h4; // @[Mux.scala:50:70] wire [3:0] _which_T_71 = 4'h4; // @[Mux.scala:50:70] wire [3:0] _which_T_72 = 4'h4; // @[Mux.scala:50:70] wire [3:0] _which_T_73 = 4'h4; // @[Mux.scala:50:70] wire [3:0] _which_T_74 = 4'h4; // @[Mux.scala:50:70] wire [3:0] _which_T_75 = 4'h4; // @[Mux.scala:50:70] wire [3:0] _which_T_76 = 4'h4; // @[Mux.scala:50:70] wire [3:0] _which_T_77 = 4'h4; // @[Mux.scala:50:70] wire [3:0] _which_T_78 = 4'h4; // @[Mux.scala:50:70] wire [3:0] debug_csrs_hi_hi_hi = 4'h4; // @[CSR.scala:670:27] wire [48:0] read_mapping_hi_1 = 49'h0; // @[CSR.scala:657:47] wire [24:0] _read_mapping_T_1 = 25'h0; // @[package.scala:132:20] wire [45:0] read_mapping_hi_hi_lo = 46'h0; // @[CSR.scala:655:48] wire [6:0] read_mapping_lo = 7'h0; // @[CSR.scala:655:48] wire [2:0] read_mstatus_hi_lo_hi_lo = 3'h2; // @[CSR.scala:649:32] wire [43:0] io_hgatp_ppn = 44'h0; // @[CSR.scala:377:7] wire [43:0] io_vsatp_ppn = 44'h0; // @[CSR.scala:377:7] wire [47:0] _reg_bp_0_WIRE_textra_pad2 = 48'h0; // @[CSR.scala:1613:23] wire [47:0] _reg_bp_1_WIRE_textra_pad2 = 48'h0; // @[CSR.scala:1613:23] wire [38:0] _read_stvec_T_2 = 39'h0; // @[package.scala:174:46] wire [38:0] _reg_bp_0_WIRE_address = 39'h0; // @[CSR.scala:1613:23] wire [38:0] _reg_bp_1_WIRE_address = 39'h0; // @[CSR.scala:1613:23] wire [39:0] io_htval = 40'h0; // @[CSR.scala:377:7] wire [39:0] _reg_bp_0_WIRE_control_reserved = 40'h0; // @[CSR.scala:1613:23] wire [39:0] _reg_bp_1_WIRE_control_reserved = 40'h0; // @[CSR.scala:1613:23] wire [1:0] io_status_sxl = 2'h2; // @[CSR.scala:377:7] wire [1:0] io_status_uxl = 2'h2; // @[CSR.scala:377:7] wire [1:0] io_hstatus_vsxl = 2'h2; // @[CSR.scala:377:7] wire [1:0] io_gstatus_uxl = 2'h2; // @[CSR.scala:377:7] wire [1:0] lo_lo_lo = 2'h2; // @[CSR.scala:431:10] wire [1:0] lo_lo_hi = 2'h2; // @[CSR.scala:431:10] wire [1:0] lo_hi_lo = 2'h2; // @[CSR.scala:431:10] wire [1:0] lo_hi_hi = 2'h2; // @[CSR.scala:431:10] wire [1:0] hi_lo_lo = 2'h2; // @[CSR.scala:431:10] wire [1:0] hi_lo_hi = 2'h2; // @[CSR.scala:431:10] wire [1:0] lo_lo_lo_1 = 2'h2; // @[CSR.scala:431:50] wire [1:0] lo_hi_lo_1 = 2'h2; // @[CSR.scala:431:50] wire [1:0] hi_lo_lo_1 = 2'h2; // @[CSR.scala:431:50] wire [1:0] read_sstatus_uxl = 2'h2; // @[CSR.scala:755:35] wire [31:0] io_gstatus_isa = 32'h0; // @[CSR.scala:377:7] wire [31:0] io_inst_0 = 32'h0; // @[CSR.scala:377:7] wire [31:0] io_trace_0_insn = 32'h0; // @[CSR.scala:377:7] wire [31:0] _reset_mstatus_WIRE_isa = 32'h0; // @[CSR.scala:391:47] wire [31:0] reset_mstatus_isa = 32'h0; // @[CSR.scala:391:34] wire [31:0] read_hcounteren = 32'h0; // @[CSR.scala:550:14] wire [31:0] _read_mtvec_T_2 = 32'h0; // @[package.scala:174:46] wire [31:0] _read_sstatus_WIRE_isa = 32'h0; // @[CSR.scala:755:48] wire [31:0] read_sstatus_isa = 32'h0; // @[CSR.scala:755:35] wire [31:0] read_pmp_15_mask = 32'h0; // @[CSR.scala:787:59] wire [31:0] lo_24 = 32'h0; // @[package.scala:45:27] wire [31:0] hi_27 = 32'h0; // @[package.scala:45:27] wire [63:0] _s_interrupts_T_7 = 64'hFFFFFFFFFFFFFFFF; // @[CSR.scala:621:168] wire [63:0] _reg_custom_1_T_1 = 64'hFFFFFFFFFFFFFFFF; // @[CSR.scala:1506:40] wire [63:0] _reg_custom_1_T_5 = 64'hFFFFFFFFFFFFFFFF; // @[CSR.scala:1531:41] wire [63:0] _reg_custom_0_T_1 = 64'hFFFFFFFFFFFFFFF7; // @[CSR.scala:1506:40] wire [63:0] _reg_custom_0_T_5 = 64'hFFFFFFFFFFFFFFF7; // @[CSR.scala:1531:41] wire [63:0] _reg_mcountinhibit_T = 64'hFFFFFFFFFFFFFFFD; // @[CSR.scala:1306:78] wire [15:0] _sie_mask_T = 16'h1000; // @[CSR.scala:750:59] wire [15:0] _sie_mask_T_1 = 16'h1000; // @[CSR.scala:750:46] wire [15:0] _delegable_T_26 = 16'h1000; // @[CSR.scala:1109:45] wire [15:0] _en_T_18 = 16'h8; // @[CSR.scala:1096:49] wire [15:0] _delegable_T_18 = 16'h8; // @[CSR.scala:1109:45] wire [63:0] _en_T_94 = 64'h800000000000000F; // @[CSR.scala:1096:120] wire [63:0] _en_T_88 = 64'h800000000000000E; // @[CSR.scala:1096:120] wire [63:0] _en_T_82 = 64'h800000000000000D; // @[CSR.scala:1096:120] wire [63:0] _en_T_76 = 64'h800000000000000C; // @[CSR.scala:1096:120] wire [63:0] _en_T_70 = 64'h800000000000000B; // @[CSR.scala:1096:120] wire [15:0] _en_T_66 = 16'h800; // @[CSR.scala:1096:49] wire [63:0] _en_T_64 = 64'h800000000000000A; // @[CSR.scala:1096:120] wire [15:0] _en_T_54 = 16'h200; // @[CSR.scala:1096:49] wire [15:0] _delegable_T_9 = 16'h200; // @[CSR.scala:1097:43] wire [63:0] _en_T_58 = 64'h8000000000000009; // @[CSR.scala:1096:120] wire [63:0] _en_T_52 = 64'h8000000000000008; // @[CSR.scala:1096:120] wire [63:0] _en_T_46 = 64'h8000000000000007; // @[CSR.scala:1096:120] wire [15:0] _en_T_42 = 16'h80; // @[CSR.scala:1096:49] wire [63:0] _en_T_40 = 64'h8000000000000006; // @[CSR.scala:1096:120] wire [15:0] _en_T_30 = 16'h20; // @[CSR.scala:1096:49] wire [15:0] _delegable_T_5 = 16'h20; // @[CSR.scala:1097:43] wire [63:0] _en_T_34 = 64'h8000000000000005; // @[CSR.scala:1096:120] wire [63:0] _en_T_28 = 64'h8000000000000004; // @[CSR.scala:1096:120] wire [63:0] _en_T_22 = 64'h8000000000000003; // @[CSR.scala:1096:120] wire [63:0] _en_T_16 = 64'h8000000000000002; // @[CSR.scala:1096:120] wire [15:0] _en_T_6 = 16'h2; // @[CSR.scala:1096:49] wire [15:0] _delegable_T_1 = 16'h2; // @[CSR.scala:1097:43] wire [63:0] _en_T_10 = 64'h8000000000000001; // @[CSR.scala:1096:120] wire [63:0] _interruptCause_T_2 = 64'h8000000000000000; // @[CSR.scala:625:39] wire [63:0] _en_T_4 = 64'h8000000000000000; // @[CSR.scala:1096:120] wire [64:0] _interruptCause_T_1 = 65'h8000000000000000; // @[CSR.scala:625:39] wire [64:0] _en_T_3 = 65'h8000000000000000; // @[CSR.scala:1096:120] wire [9:0] _io_decode_0_write_flush_addr_m_T = 10'h300; // @[CSR.scala:932:36] wire [36:0] hi_hi_hi_4 = 37'h0; // @[CSR.scala:768:51] wire [33:0] hi_hi_hi_lo = 34'h0; // @[CSR.scala:768:51] wire [17:0] hi_lo_5 = 18'h800; // @[CSR.scala:768:51] wire [11:0] hi_lo_lo_4 = 12'h800; // @[CSR.scala:768:51] wire [2:0] _which_T_63 = 3'h4; // @[Mux.scala:50:70] wire [2:0] read_mstatus_hi_lo_lo_hi = 3'h4; // @[CSR.scala:649:32] wire [2:0] hi_lo_lo_hi = 3'h4; // @[CSR.scala:768:51] wire [15:0] _sie_mask_T_2 = 16'hEFFF; // @[CSR.scala:750:20] wire [7:0] sie_mask_hi = 8'h10; // @[CSR.scala:750:59] wire [3:0] sie_mask_hi_hi = 4'h1; // @[CSR.scala:750:59] wire [53:0] _reg_menvcfg_WIRE_zero54 = 54'h0; // @[CSR.scala:525:41] wire [53:0] _reg_senvcfg_WIRE_zero54 = 54'h0; // @[CSR.scala:526:41] wire [53:0] _reg_henvcfg_WIRE_zero54 = 54'h0; // @[CSR.scala:527:41] wire [15:0] delegable_interrupts = 16'h222; // @[CSR.scala:431:50] wire [7:0] hi_1 = 8'h2; // @[CSR.scala:431:50] wire [3:0] lo_lo_1 = 4'h2; // @[CSR.scala:431:50] wire [3:0] lo_hi_1 = 4'h2; // @[CSR.scala:431:50] wire [3:0] hi_lo_1 = 4'h2; // @[CSR.scala:431:50] wire [7:0] lo_1 = 8'h22; // @[CSR.scala:431:50] wire [15:0] supported_interrupts = 16'hAAA; // @[CSR.scala:431:17] wire [7:0] hi = 8'hA; // @[CSR.scala:431:10] wire [3:0] lo_lo = 4'hA; // @[CSR.scala:431:10] wire [3:0] lo_hi = 4'hA; // @[CSR.scala:431:10] wire [3:0] hi_lo = 4'hA; // @[CSR.scala:431:10] wire [7:0] lo = 8'hAA; // @[CSR.scala:431:10] wire [11:0] _reset_dcsr_WIRE_zero3 = 12'h0; // @[CSR.scala:400:44] wire [11:0] reset_dcsr_zero3 = 12'h0; // @[CSR.scala:400:31] wire [15:0] _delegable_T_27 = 16'h2000; // @[CSR.scala:1109:45] wire [15:0] _delegable_T_23 = 16'h100; // @[CSR.scala:1109:45] wire [15:0] _delegable_T_21 = 16'h40; // @[CSR.scala:1109:45] wire [15:0] _delegable_T_19 = 16'h10; // @[CSR.scala:1109:45] wire [15:0] _delegable_T_17 = 16'h4; // @[CSR.scala:1109:45] wire [64:0] _en_T_93 = 65'h800000000000000F; // @[CSR.scala:1096:120] wire [64:0] _en_T_87 = 65'h800000000000000E; // @[CSR.scala:1096:120] wire [64:0] _en_T_81 = 65'h800000000000000D; // @[CSR.scala:1096:120] wire [64:0] _en_T_75 = 65'h800000000000000C; // @[CSR.scala:1096:120] wire [64:0] _en_T_69 = 65'h800000000000000B; // @[CSR.scala:1096:120] wire [64:0] _en_T_63 = 65'h800000000000000A; // @[CSR.scala:1096:120] wire [64:0] _en_T_57 = 65'h8000000000000009; // @[CSR.scala:1096:120] wire [64:0] _en_T_51 = 65'h8000000000000008; // @[CSR.scala:1096:120] wire [64:0] _en_T_45 = 65'h8000000000000007; // @[CSR.scala:1096:120] wire [64:0] _en_T_39 = 65'h8000000000000006; // @[CSR.scala:1096:120] wire [64:0] _en_T_33 = 65'h8000000000000005; // @[CSR.scala:1096:120] wire [64:0] _en_T_27 = 65'h8000000000000004; // @[CSR.scala:1096:120] wire [64:0] _en_T_21 = 65'h8000000000000003; // @[CSR.scala:1096:120] wire [64:0] _en_T_15 = 65'h8000000000000002; // @[CSR.scala:1096:120] wire [64:0] _en_T_9 = 65'h8000000000000001; // @[CSR.scala:1096:120] wire [62:0] _interruptCause_T = 63'h0; // @[CSR.scala:625:50] wire [15:0] _delegable_T_28 = 16'h8000; // @[CSR.scala:1109:45] wire [39:0] _io_evec_T_15 = 40'hFFFFFFFFFF; // @[CSR.scala:1665:28] wire mip_mtip = io_interrupts_mtip_0; // @[CSR.scala:377:7, :600:24] wire mip_msip = io_interrupts_msip_0; // @[CSR.scala:377:7, :600:24] wire mip_meip = io_interrupts_meip_0; // @[CSR.scala:377:7, :600:24] wire [63:0] _io_rw_rdata_WIRE; // @[Mux.scala:30:73] wire [31:0] decoded_plaInput_1 = io_decode_0_inst_0; // @[pla.scala:77:22] wire _io_decode_0_fp_illegal_T_6; // @[CSR.scala:915:91] wire _io_decode_0_fp_csr_T; // @[Decode.scala:55:116] wire _io_decode_0_read_illegal_T_20; // @[CSR.scala:928:68] wire _io_decode_0_write_illegal_T_1; // @[CSR.scala:930:41] wire _io_decode_0_write_flush_T_3; // @[CSR.scala:933:7] wire _io_decode_0_system_illegal_T_25; // @[CSR.scala:940:44] wire _io_decode_0_virtual_access_illegal_T_29; // @[CSR.scala:943:66] wire _io_decode_0_virtual_system_illegal_T_22; // @[CSR.scala:949:52] wire _io_csr_stall_T; // @[CSR.scala:1161:27] wire _io_eret_T_1; // @[CSR.scala:1000:38] wire _io_singleStep_T_1; // @[CSR.scala:1001:34] wire [1:0] _io_status_dprv_T_2; // @[CSR.scala:1008:24] wire _io_status_dv_T_3; // @[CSR.scala:1009:33] wire _io_status_sd_T_4; // @[CSR.scala:1003:58] wire read_sstatus_sd = io_status_sd_0; // @[CSR.scala:377:7, :755:35] wire read_sstatus_mxr = io_status_mxr_0; // @[CSR.scala:377:7, :755:35] wire read_sstatus_sum = io_status_sum_0; // @[CSR.scala:377:7, :755:35] wire [1:0] read_sstatus_fs = io_status_fs_0; // @[CSR.scala:377:7, :755:35] wire read_sstatus_spp = io_status_spp_0; // @[CSR.scala:377:7, :755:35] wire read_sstatus_spie = io_status_spie_0; // @[CSR.scala:377:7, :755:35] wire read_sstatus_sie = io_status_sie_0; // @[CSR.scala:377:7, :755:35] wire _io_trace_0_valid_T = io_retire_0; // @[CSR.scala:377:7, :1621:26] wire [39:0] io_trace_0_iaddr = io_pc_0; // @[CSR.scala:377:7] wire [39:0] io_trace_0_tval = io_tval_0; // @[CSR.scala:377:7] wire [63:0] value_1; // @[Counters.scala:55:30] wire _io_interrupt_T_5; // @[CSR.scala:626:73] wire [63:0] interruptCause; // @[CSR.scala:625:63] wire pmp_cfg_l; // @[PMP.scala:24:19] wire [1:0] pmp_cfg_a; // @[PMP.scala:24:19] wire pmp_cfg_x; // @[PMP.scala:24:19] wire pmp_cfg_w; // @[PMP.scala:24:19] wire pmp_cfg_r; // @[PMP.scala:24:19] wire [29:0] pmp_addr; // @[PMP.scala:24:19] wire [31:0] pmp_mask; // @[PMP.scala:24:19] wire pmp_1_cfg_l; // @[PMP.scala:24:19] wire [1:0] pmp_1_cfg_a; // @[PMP.scala:24:19] wire pmp_1_cfg_x; // @[PMP.scala:24:19] wire pmp_1_cfg_w; // @[PMP.scala:24:19] wire pmp_1_cfg_r; // @[PMP.scala:24:19] wire [29:0] pmp_1_addr; // @[PMP.scala:24:19] wire [31:0] pmp_1_mask; // @[PMP.scala:24:19] wire pmp_2_cfg_l; // @[PMP.scala:24:19] wire [1:0] pmp_2_cfg_a; // @[PMP.scala:24:19] wire pmp_2_cfg_x; // @[PMP.scala:24:19] wire pmp_2_cfg_w; // @[PMP.scala:24:19] wire pmp_2_cfg_r; // @[PMP.scala:24:19] wire [29:0] pmp_2_addr; // @[PMP.scala:24:19] wire [31:0] pmp_2_mask; // @[PMP.scala:24:19] wire pmp_3_cfg_l; // @[PMP.scala:24:19] wire [1:0] pmp_3_cfg_a; // @[PMP.scala:24:19] wire pmp_3_cfg_x; // @[PMP.scala:24:19] wire pmp_3_cfg_w; // @[PMP.scala:24:19] wire pmp_3_cfg_r; // @[PMP.scala:24:19] wire [29:0] pmp_3_addr; // @[PMP.scala:24:19] wire [31:0] pmp_3_mask; // @[PMP.scala:24:19] wire pmp_4_cfg_l; // @[PMP.scala:24:19] wire [1:0] pmp_4_cfg_a; // @[PMP.scala:24:19] wire pmp_4_cfg_x; // @[PMP.scala:24:19] wire pmp_4_cfg_w; // @[PMP.scala:24:19] wire pmp_4_cfg_r; // @[PMP.scala:24:19] wire [29:0] pmp_4_addr; // @[PMP.scala:24:19] wire [31:0] pmp_4_mask; // @[PMP.scala:24:19] wire pmp_5_cfg_l; // @[PMP.scala:24:19] wire [1:0] pmp_5_cfg_a; // @[PMP.scala:24:19] wire pmp_5_cfg_x; // @[PMP.scala:24:19] wire pmp_5_cfg_w; // @[PMP.scala:24:19] wire pmp_5_cfg_r; // @[PMP.scala:24:19] wire [29:0] pmp_5_addr; // @[PMP.scala:24:19] wire [31:0] pmp_5_mask; // @[PMP.scala:24:19] wire pmp_6_cfg_l; // @[PMP.scala:24:19] wire [1:0] pmp_6_cfg_a; // @[PMP.scala:24:19] wire pmp_6_cfg_x; // @[PMP.scala:24:19] wire pmp_6_cfg_w; // @[PMP.scala:24:19] wire pmp_6_cfg_r; // @[PMP.scala:24:19] wire [29:0] pmp_6_addr; // @[PMP.scala:24:19] wire [31:0] pmp_6_mask; // @[PMP.scala:24:19] wire pmp_7_cfg_l; // @[PMP.scala:24:19] wire [1:0] pmp_7_cfg_a; // @[PMP.scala:24:19] wire pmp_7_cfg_x; // @[PMP.scala:24:19] wire pmp_7_cfg_w; // @[PMP.scala:24:19] wire pmp_7_cfg_r; // @[PMP.scala:24:19] wire [29:0] pmp_7_addr; // @[PMP.scala:24:19] wire [31:0] pmp_7_mask; // @[PMP.scala:24:19] wire _io_inhibit_cycle_T; // @[CSR.scala:591:40] wire _io_trace_0_valid_T_1; // @[CSR.scala:1621:32] wire [2:0] _io_trace_0_priv_T; // @[CSR.scala:1624:18] wire _io_trace_0_exception_T_1; // @[CSR.scala:1620:37] wire _io_trace_0_interrupt_T; // @[CSR.scala:1626:25] wire [63:0] cause; // @[CSR.scala:959:8] wire _io_fiom_T_6; // @[CSR.scala:631:113] wire reg_custom_read; // @[CSR.scala:799:36] wire [63:0] wdata; // @[CSR.scala:1643:39] wire reg_custom_read_1; // @[CSR.scala:799:36] wire [63:0] io_rw_rdata_0; // @[CSR.scala:377:7] wire io_decode_0_fp_illegal_0; // @[CSR.scala:377:7] wire io_decode_0_fp_csr_0; // @[CSR.scala:377:7] wire io_decode_0_read_illegal_0; // @[CSR.scala:377:7] wire io_decode_0_write_illegal_0; // @[CSR.scala:377:7] wire io_decode_0_write_flush_0; // @[CSR.scala:377:7] wire io_decode_0_system_illegal_0; // @[CSR.scala:377:7] wire io_decode_0_virtual_access_illegal_0; // @[CSR.scala:377:7] wire io_decode_0_virtual_system_illegal_0; // @[CSR.scala:377:7] wire io_status_debug_0; // @[CSR.scala:377:7] wire io_status_cease_0; // @[CSR.scala:377:7] wire io_status_wfi_0; // @[CSR.scala:377:7] wire [1:0] io_status_dprv_0; // @[CSR.scala:377:7] wire io_status_dv_0; // @[CSR.scala:377:7] wire [1:0] io_status_prv_0; // @[CSR.scala:377:7] wire io_status_v_0; // @[CSR.scala:377:7] wire io_status_mpv_0; // @[CSR.scala:377:7] wire io_status_gva_0; // @[CSR.scala:377:7] wire io_status_tsr_0; // @[CSR.scala:377:7] wire io_status_tw_0; // @[CSR.scala:377:7] wire io_status_tvm_0; // @[CSR.scala:377:7] wire io_status_mprv_0; // @[CSR.scala:377:7] wire [1:0] io_status_mpp_0; // @[CSR.scala:377:7] wire io_status_mpie_0; // @[CSR.scala:377:7] wire io_status_mie_0; // @[CSR.scala:377:7] wire io_hstatus_spvp; // @[CSR.scala:377:7] wire io_hstatus_spv; // @[CSR.scala:377:7] wire io_hstatus_gva; // @[CSR.scala:377:7] wire io_gstatus_spp; // @[CSR.scala:377:7] wire io_gstatus_spie; // @[CSR.scala:377:7] wire io_gstatus_sie; // @[CSR.scala:377:7] wire [3:0] io_ptbr_mode_0; // @[CSR.scala:377:7] wire [43:0] io_ptbr_ppn_0; // @[CSR.scala:377:7] wire io_pmp_0_cfg_l_0; // @[CSR.scala:377:7] wire [1:0] io_pmp_0_cfg_a_0; // @[CSR.scala:377:7] wire io_pmp_0_cfg_x_0; // @[CSR.scala:377:7] wire io_pmp_0_cfg_w_0; // @[CSR.scala:377:7] wire io_pmp_0_cfg_r_0; // @[CSR.scala:377:7] wire [29:0] io_pmp_0_addr_0; // @[CSR.scala:377:7] wire [31:0] io_pmp_0_mask_0; // @[CSR.scala:377:7] wire io_pmp_1_cfg_l_0; // @[CSR.scala:377:7] wire [1:0] io_pmp_1_cfg_a_0; // @[CSR.scala:377:7] wire io_pmp_1_cfg_x_0; // @[CSR.scala:377:7] wire io_pmp_1_cfg_w_0; // @[CSR.scala:377:7] wire io_pmp_1_cfg_r_0; // @[CSR.scala:377:7] wire [29:0] io_pmp_1_addr_0; // @[CSR.scala:377:7] wire [31:0] io_pmp_1_mask_0; // @[CSR.scala:377:7] wire io_pmp_2_cfg_l_0; // @[CSR.scala:377:7] wire [1:0] io_pmp_2_cfg_a_0; // @[CSR.scala:377:7] wire io_pmp_2_cfg_x_0; // @[CSR.scala:377:7] wire io_pmp_2_cfg_w_0; // @[CSR.scala:377:7] wire io_pmp_2_cfg_r_0; // @[CSR.scala:377:7] wire [29:0] io_pmp_2_addr_0; // @[CSR.scala:377:7] wire [31:0] io_pmp_2_mask_0; // @[CSR.scala:377:7] wire io_pmp_3_cfg_l_0; // @[CSR.scala:377:7] wire [1:0] io_pmp_3_cfg_a_0; // @[CSR.scala:377:7] wire io_pmp_3_cfg_x_0; // @[CSR.scala:377:7] wire io_pmp_3_cfg_w_0; // @[CSR.scala:377:7] wire io_pmp_3_cfg_r_0; // @[CSR.scala:377:7] wire [29:0] io_pmp_3_addr_0; // @[CSR.scala:377:7] wire [31:0] io_pmp_3_mask_0; // @[CSR.scala:377:7] wire io_pmp_4_cfg_l_0; // @[CSR.scala:377:7] wire [1:0] io_pmp_4_cfg_a_0; // @[CSR.scala:377:7] wire io_pmp_4_cfg_x_0; // @[CSR.scala:377:7] wire io_pmp_4_cfg_w_0; // @[CSR.scala:377:7] wire io_pmp_4_cfg_r_0; // @[CSR.scala:377:7] wire [29:0] io_pmp_4_addr_0; // @[CSR.scala:377:7] wire [31:0] io_pmp_4_mask_0; // @[CSR.scala:377:7] wire io_pmp_5_cfg_l_0; // @[CSR.scala:377:7] wire [1:0] io_pmp_5_cfg_a_0; // @[CSR.scala:377:7] wire io_pmp_5_cfg_x_0; // @[CSR.scala:377:7] wire io_pmp_5_cfg_w_0; // @[CSR.scala:377:7] wire io_pmp_5_cfg_r_0; // @[CSR.scala:377:7] wire [29:0] io_pmp_5_addr_0; // @[CSR.scala:377:7] wire [31:0] io_pmp_5_mask_0; // @[CSR.scala:377:7] wire io_pmp_6_cfg_l_0; // @[CSR.scala:377:7] wire [1:0] io_pmp_6_cfg_a_0; // @[CSR.scala:377:7] wire io_pmp_6_cfg_x_0; // @[CSR.scala:377:7] wire io_pmp_6_cfg_w_0; // @[CSR.scala:377:7] wire io_pmp_6_cfg_r_0; // @[CSR.scala:377:7] wire [29:0] io_pmp_6_addr_0; // @[CSR.scala:377:7] wire [31:0] io_pmp_6_mask_0; // @[CSR.scala:377:7] wire io_pmp_7_cfg_l_0; // @[CSR.scala:377:7] wire [1:0] io_pmp_7_cfg_a_0; // @[CSR.scala:377:7] wire io_pmp_7_cfg_x_0; // @[CSR.scala:377:7] wire io_pmp_7_cfg_w_0; // @[CSR.scala:377:7] wire io_pmp_7_cfg_r_0; // @[CSR.scala:377:7] wire [29:0] io_pmp_7_addr_0; // @[CSR.scala:377:7] wire [31:0] io_pmp_7_mask_0; // @[CSR.scala:377:7] wire [63:0] io_counters_0_eventSel_0; // @[CSR.scala:377:7] wire [63:0] io_counters_1_eventSel_0; // @[CSR.scala:377:7] wire io_trace_0_valid; // @[CSR.scala:377:7] wire [2:0] io_trace_0_priv; // @[CSR.scala:377:7] wire io_trace_0_exception; // @[CSR.scala:377:7] wire io_trace_0_interrupt; // @[CSR.scala:377:7] wire [63:0] io_trace_0_cause; // @[CSR.scala:377:7] wire io_customCSRs_0_ren_0; // @[CSR.scala:377:7] wire io_customCSRs_0_wen_0; // @[CSR.scala:377:7] wire [63:0] io_customCSRs_0_wdata_0; // @[CSR.scala:377:7] wire [63:0] io_customCSRs_0_value_0; // @[CSR.scala:377:7] wire io_customCSRs_1_ren_0; // @[CSR.scala:377:7] wire io_customCSRs_1_wen_0; // @[CSR.scala:377:7] wire [63:0] io_customCSRs_1_wdata_0; // @[CSR.scala:377:7] wire [63:0] io_customCSRs_1_value_0; // @[CSR.scala:377:7] wire io_csr_stall_0; // @[CSR.scala:377:7] wire io_eret; // @[CSR.scala:377:7] wire io_singleStep_0; // @[CSR.scala:377:7] wire [39:0] io_evec_0; // @[CSR.scala:377:7] wire [63:0] io_time_0; // @[CSR.scala:377:7] wire [2:0] io_fcsr_rm_0; // @[CSR.scala:377:7] wire io_interrupt_0; // @[CSR.scala:377:7] wire [63:0] io_interrupt_cause_0; // @[CSR.scala:377:7] wire [31:0] io_csrw_counter; // @[CSR.scala:377:7] wire io_inhibit_cycle; // @[CSR.scala:377:7] wire io_fiom; // @[CSR.scala:377:7] reg [1:0] reg_mstatus_prv; // @[CSR.scala:395:28] assign io_status_prv_0 = reg_mstatus_prv; // @[CSR.scala:377:7, :395:28] reg reg_mstatus_v; // @[CSR.scala:395:28] assign io_status_v_0 = reg_mstatus_v; // @[CSR.scala:377:7, :395:28] wire _io_decode_0_rocc_illegal_T_2 = reg_mstatus_v; // @[CSR.scala:395:28, :919:66] reg reg_mstatus_mpv; // @[CSR.scala:395:28] assign io_status_mpv_0 = reg_mstatus_mpv; // @[CSR.scala:377:7, :395:28] reg reg_mstatus_gva; // @[CSR.scala:395:28] assign io_status_gva_0 = reg_mstatus_gva; // @[CSR.scala:377:7, :395:28] reg reg_mstatus_tsr; // @[CSR.scala:395:28] assign io_status_tsr_0 = reg_mstatus_tsr; // @[CSR.scala:377:7, :395:28] reg reg_mstatus_tw; // @[CSR.scala:395:28] assign io_status_tw_0 = reg_mstatus_tw; // @[CSR.scala:377:7, :395:28] reg reg_mstatus_tvm; // @[CSR.scala:395:28] assign io_status_tvm_0 = reg_mstatus_tvm; // @[CSR.scala:377:7, :395:28] reg reg_mstatus_mxr; // @[CSR.scala:395:28] assign io_status_mxr_0 = reg_mstatus_mxr; // @[CSR.scala:377:7, :395:28] reg reg_mstatus_sum; // @[CSR.scala:395:28] assign io_status_sum_0 = reg_mstatus_sum; // @[CSR.scala:377:7, :395:28] reg reg_mstatus_mprv; // @[CSR.scala:395:28] assign io_status_mprv_0 = reg_mstatus_mprv; // @[CSR.scala:377:7, :395:28] reg [1:0] reg_mstatus_fs; // @[CSR.scala:395:28] assign io_status_fs_0 = reg_mstatus_fs; // @[CSR.scala:377:7, :395:28] reg [1:0] reg_mstatus_mpp; // @[CSR.scala:395:28] assign io_status_mpp_0 = reg_mstatus_mpp; // @[CSR.scala:377:7, :395:28] reg reg_mstatus_spp; // @[CSR.scala:395:28] assign io_status_spp_0 = reg_mstatus_spp; // @[CSR.scala:377:7, :395:28] reg reg_mstatus_mpie; // @[CSR.scala:395:28] assign io_status_mpie_0 = reg_mstatus_mpie; // @[CSR.scala:377:7, :395:28] reg reg_mstatus_spie; // @[CSR.scala:395:28] assign io_status_spie_0 = reg_mstatus_spie; // @[CSR.scala:377:7, :395:28] reg reg_mstatus_mie; // @[CSR.scala:395:28] assign io_status_mie_0 = reg_mstatus_mie; // @[CSR.scala:377:7, :395:28] reg reg_mstatus_sie; // @[CSR.scala:395:28] assign io_status_sie_0 = reg_mstatus_sie; // @[CSR.scala:377:7, :395:28] wire [1:0] new_prv; // @[CSR.scala:397:28] wire _reg_mstatus_prv_T = new_prv == 2'h2; // @[CSR.scala:397:28, :1647:35] wire [1:0] _reg_mstatus_prv_T_1 = _reg_mstatus_prv_T ? 2'h0 : new_prv; // @[CSR.scala:397:28, :1647:{29,35}] reg reg_dcsr_ebreakm; // @[CSR.scala:403:25] reg reg_dcsr_ebreaks; // @[CSR.scala:403:25] reg reg_dcsr_ebreaku; // @[CSR.scala:403:25] reg [2:0] reg_dcsr_cause; // @[CSR.scala:403:25] reg reg_dcsr_v; // @[CSR.scala:403:25] reg reg_dcsr_step; // @[CSR.scala:403:25] reg [1:0] reg_dcsr_prv; // @[CSR.scala:403:25] reg reg_debug; // @[CSR.scala:482:26] assign io_status_debug_0 = reg_debug; // @[CSR.scala:377:7, :482:26] reg [39:0] reg_dpc; // @[CSR.scala:483:20] reg [63:0] reg_dscratch0; // @[CSR.scala:484:26] reg reg_singleStepped; // @[CSR.scala:486:30] reg reg_pmp_0_cfg_l; // @[CSR.scala:493:20] assign pmp_cfg_l = reg_pmp_0_cfg_l; // @[PMP.scala:24:19] reg [1:0] reg_pmp_0_cfg_a; // @[CSR.scala:493:20] assign pmp_cfg_a = reg_pmp_0_cfg_a; // @[PMP.scala:24:19] reg reg_pmp_0_cfg_x; // @[CSR.scala:493:20] assign pmp_cfg_x = reg_pmp_0_cfg_x; // @[PMP.scala:24:19] reg reg_pmp_0_cfg_w; // @[CSR.scala:493:20] assign pmp_cfg_w = reg_pmp_0_cfg_w; // @[PMP.scala:24:19] reg reg_pmp_0_cfg_r; // @[CSR.scala:493:20] assign pmp_cfg_r = reg_pmp_0_cfg_r; // @[PMP.scala:24:19] reg [29:0] reg_pmp_0_addr; // @[CSR.scala:493:20] assign pmp_addr = reg_pmp_0_addr; // @[PMP.scala:24:19] reg reg_pmp_1_cfg_l; // @[CSR.scala:493:20] assign pmp_1_cfg_l = reg_pmp_1_cfg_l; // @[PMP.scala:24:19] reg [1:0] reg_pmp_1_cfg_a; // @[CSR.scala:493:20] assign pmp_1_cfg_a = reg_pmp_1_cfg_a; // @[PMP.scala:24:19] reg reg_pmp_1_cfg_x; // @[CSR.scala:493:20] assign pmp_1_cfg_x = reg_pmp_1_cfg_x; // @[PMP.scala:24:19] reg reg_pmp_1_cfg_w; // @[CSR.scala:493:20] assign pmp_1_cfg_w = reg_pmp_1_cfg_w; // @[PMP.scala:24:19] reg reg_pmp_1_cfg_r; // @[CSR.scala:493:20] assign pmp_1_cfg_r = reg_pmp_1_cfg_r; // @[PMP.scala:24:19] reg [29:0] reg_pmp_1_addr; // @[CSR.scala:493:20] assign pmp_1_addr = reg_pmp_1_addr; // @[PMP.scala:24:19] reg reg_pmp_2_cfg_l; // @[CSR.scala:493:20] assign pmp_2_cfg_l = reg_pmp_2_cfg_l; // @[PMP.scala:24:19] reg [1:0] reg_pmp_2_cfg_a; // @[CSR.scala:493:20] assign pmp_2_cfg_a = reg_pmp_2_cfg_a; // @[PMP.scala:24:19] reg reg_pmp_2_cfg_x; // @[CSR.scala:493:20] assign pmp_2_cfg_x = reg_pmp_2_cfg_x; // @[PMP.scala:24:19] reg reg_pmp_2_cfg_w; // @[CSR.scala:493:20] assign pmp_2_cfg_w = reg_pmp_2_cfg_w; // @[PMP.scala:24:19] reg reg_pmp_2_cfg_r; // @[CSR.scala:493:20] assign pmp_2_cfg_r = reg_pmp_2_cfg_r; // @[PMP.scala:24:19] reg [29:0] reg_pmp_2_addr; // @[CSR.scala:493:20] assign pmp_2_addr = reg_pmp_2_addr; // @[PMP.scala:24:19] reg reg_pmp_3_cfg_l; // @[CSR.scala:493:20] assign pmp_3_cfg_l = reg_pmp_3_cfg_l; // @[PMP.scala:24:19] reg [1:0] reg_pmp_3_cfg_a; // @[CSR.scala:493:20] assign pmp_3_cfg_a = reg_pmp_3_cfg_a; // @[PMP.scala:24:19] reg reg_pmp_3_cfg_x; // @[CSR.scala:493:20] assign pmp_3_cfg_x = reg_pmp_3_cfg_x; // @[PMP.scala:24:19] reg reg_pmp_3_cfg_w; // @[CSR.scala:493:20] assign pmp_3_cfg_w = reg_pmp_3_cfg_w; // @[PMP.scala:24:19] reg reg_pmp_3_cfg_r; // @[CSR.scala:493:20] assign pmp_3_cfg_r = reg_pmp_3_cfg_r; // @[PMP.scala:24:19] reg [29:0] reg_pmp_3_addr; // @[CSR.scala:493:20] assign pmp_3_addr = reg_pmp_3_addr; // @[PMP.scala:24:19] reg reg_pmp_4_cfg_l; // @[CSR.scala:493:20] assign pmp_4_cfg_l = reg_pmp_4_cfg_l; // @[PMP.scala:24:19] reg [1:0] reg_pmp_4_cfg_a; // @[CSR.scala:493:20] assign pmp_4_cfg_a = reg_pmp_4_cfg_a; // @[PMP.scala:24:19] reg reg_pmp_4_cfg_x; // @[CSR.scala:493:20] assign pmp_4_cfg_x = reg_pmp_4_cfg_x; // @[PMP.scala:24:19] reg reg_pmp_4_cfg_w; // @[CSR.scala:493:20] assign pmp_4_cfg_w = reg_pmp_4_cfg_w; // @[PMP.scala:24:19] reg reg_pmp_4_cfg_r; // @[CSR.scala:493:20] assign pmp_4_cfg_r = reg_pmp_4_cfg_r; // @[PMP.scala:24:19] reg [29:0] reg_pmp_4_addr; // @[CSR.scala:493:20] assign pmp_4_addr = reg_pmp_4_addr; // @[PMP.scala:24:19] reg reg_pmp_5_cfg_l; // @[CSR.scala:493:20] assign pmp_5_cfg_l = reg_pmp_5_cfg_l; // @[PMP.scala:24:19] reg [1:0] reg_pmp_5_cfg_a; // @[CSR.scala:493:20] assign pmp_5_cfg_a = reg_pmp_5_cfg_a; // @[PMP.scala:24:19] reg reg_pmp_5_cfg_x; // @[CSR.scala:493:20] assign pmp_5_cfg_x = reg_pmp_5_cfg_x; // @[PMP.scala:24:19] reg reg_pmp_5_cfg_w; // @[CSR.scala:493:20] assign pmp_5_cfg_w = reg_pmp_5_cfg_w; // @[PMP.scala:24:19] reg reg_pmp_5_cfg_r; // @[CSR.scala:493:20] assign pmp_5_cfg_r = reg_pmp_5_cfg_r; // @[PMP.scala:24:19] reg [29:0] reg_pmp_5_addr; // @[CSR.scala:493:20] assign pmp_5_addr = reg_pmp_5_addr; // @[PMP.scala:24:19] reg reg_pmp_6_cfg_l; // @[CSR.scala:493:20] assign pmp_6_cfg_l = reg_pmp_6_cfg_l; // @[PMP.scala:24:19] reg [1:0] reg_pmp_6_cfg_a; // @[CSR.scala:493:20] assign pmp_6_cfg_a = reg_pmp_6_cfg_a; // @[PMP.scala:24:19] reg reg_pmp_6_cfg_x; // @[CSR.scala:493:20] assign pmp_6_cfg_x = reg_pmp_6_cfg_x; // @[PMP.scala:24:19] reg reg_pmp_6_cfg_w; // @[CSR.scala:493:20] assign pmp_6_cfg_w = reg_pmp_6_cfg_w; // @[PMP.scala:24:19] reg reg_pmp_6_cfg_r; // @[CSR.scala:493:20] assign pmp_6_cfg_r = reg_pmp_6_cfg_r; // @[PMP.scala:24:19] reg [29:0] reg_pmp_6_addr; // @[CSR.scala:493:20] assign pmp_6_addr = reg_pmp_6_addr; // @[PMP.scala:24:19] reg reg_pmp_7_cfg_l; // @[CSR.scala:493:20] assign pmp_7_cfg_l = reg_pmp_7_cfg_l; // @[PMP.scala:24:19] reg [1:0] reg_pmp_7_cfg_a; // @[CSR.scala:493:20] assign pmp_7_cfg_a = reg_pmp_7_cfg_a; // @[PMP.scala:24:19] reg reg_pmp_7_cfg_x; // @[CSR.scala:493:20] assign pmp_7_cfg_x = reg_pmp_7_cfg_x; // @[PMP.scala:24:19] reg reg_pmp_7_cfg_w; // @[CSR.scala:493:20] assign pmp_7_cfg_w = reg_pmp_7_cfg_w; // @[PMP.scala:24:19] reg reg_pmp_7_cfg_r; // @[CSR.scala:493:20] assign pmp_7_cfg_r = reg_pmp_7_cfg_r; // @[PMP.scala:24:19] reg [29:0] reg_pmp_7_addr; // @[CSR.scala:493:20] assign pmp_7_addr = reg_pmp_7_addr; // @[PMP.scala:24:19] reg [63:0] reg_mie; // @[CSR.scala:495:20] reg [63:0] reg_mideleg; // @[CSR.scala:497:18] wire [63:0] read_mideleg = {54'h0, reg_mideleg[9:1] & 9'h111, 1'h0}; // @[CSR.scala:497:18, :498:{14,38,61}] reg [63:0] reg_medeleg; // @[CSR.scala:501:18] wire [63:0] read_medeleg = {48'h0, reg_medeleg[15:0] & 16'hB15D}; // @[CSR.scala:501:18, :502:{14,38}] reg reg_mip_seip; // @[CSR.scala:504:20] reg reg_mip_stip; // @[CSR.scala:504:20] wire mip_stip = reg_mip_stip; // @[CSR.scala:504:20, :600:24] reg reg_mip_ssip; // @[CSR.scala:504:20] wire mip_ssip = reg_mip_ssip; // @[CSR.scala:504:20, :600:24] reg [39:0] reg_mepc; // @[CSR.scala:505:21] reg [63:0] reg_mcause; // @[CSR.scala:506:27] reg [39:0] reg_mtval; // @[CSR.scala:507:22] reg [39:0] reg_mtval2; // @[CSR.scala:508:23] reg [63:0] reg_mscratch; // @[CSR.scala:509:25] reg [31:0] reg_mtvec; // @[CSR.scala:512:31] reg reg_menvcfg_fiom; // @[CSR.scala:525:28] reg reg_senvcfg_fiom; // @[CSR.scala:526:28] reg [31:0] reg_mcounteren; // @[CSR.scala:531:18] wire [31:0] read_mcounteren = {27'h0, reg_mcounteren[4:0]}; // @[CSR.scala:531:18, :532:{14,32}] reg [31:0] reg_scounteren; // @[CSR.scala:535:18] wire [31:0] read_scounteren = {27'h0, reg_scounteren[4:0]}; // @[CSR.scala:535:18, :536:{14,38}] reg reg_hstatus_spvp; // @[CSR.scala:552:28] assign io_hstatus_spvp = reg_hstatus_spvp; // @[CSR.scala:377:7, :552:28] reg reg_hstatus_spv; // @[CSR.scala:552:28] assign io_hstatus_spv = reg_hstatus_spv; // @[CSR.scala:377:7, :552:28] reg reg_hstatus_gva; // @[CSR.scala:552:28] assign io_hstatus_gva = reg_hstatus_gva; // @[CSR.scala:377:7, :552:28] reg [39:0] reg_htval; // @[CSR.scala:554:22] wire [1:0] _GEN = {reg_mip_ssip, 1'h0}; // @[CSR.scala:504:20, :555:27] wire [1:0] read_hvip_lo_lo_lo; // @[CSR.scala:555:27] assign read_hvip_lo_lo_lo = _GEN; // @[CSR.scala:555:27] wire [1:0] new_mip_lo_lo_lo; // @[CSR.scala:1271:59] assign new_mip_lo_lo_lo = _GEN; // @[CSR.scala:555:27, :1271:59] wire [3:0] read_hvip_lo_lo = {read_hvip_lo_lo_hi, read_hvip_lo_lo_lo}; // @[CSR.scala:555:27] wire [1:0] _GEN_0 = {reg_mip_stip, 1'h0}; // @[CSR.scala:504:20, :555:27] wire [1:0] read_hvip_lo_hi_lo; // @[CSR.scala:555:27] assign read_hvip_lo_hi_lo = _GEN_0; // @[CSR.scala:555:27] wire [1:0] new_mip_lo_hi_lo; // @[CSR.scala:1271:59] assign new_mip_lo_hi_lo = _GEN_0; // @[CSR.scala:555:27, :1271:59] wire [3:0] read_hvip_lo_hi = {read_hvip_lo_hi_hi, read_hvip_lo_hi_lo}; // @[CSR.scala:555:27] wire [7:0] read_hvip_lo = {read_hvip_lo_hi, read_hvip_lo_lo}; // @[CSR.scala:555:27] wire [1:0] _GEN_1 = {reg_mip_seip, 1'h0}; // @[CSR.scala:504:20, :555:27] wire [1:0] read_hvip_hi_lo_lo; // @[CSR.scala:555:27] assign read_hvip_hi_lo_lo = _GEN_1; // @[CSR.scala:555:27] wire [1:0] new_mip_hi_lo_lo; // @[CSR.scala:1271:59] assign new_mip_hi_lo_lo = _GEN_1; // @[CSR.scala:555:27, :1271:59] wire [3:0] read_hvip_hi_lo = {read_hvip_hi_lo_hi, read_hvip_hi_lo_lo}; // @[CSR.scala:555:27] wire [1:0] read_hvip_hi_hi_hi = {read_hvip_hi_hi_hi_hi, 1'h0}; // @[CSR.scala:555:27] wire [3:0] read_hvip_hi_hi = {read_hvip_hi_hi_hi, read_hvip_hi_hi_lo}; // @[CSR.scala:555:27] wire [7:0] read_hvip_hi = {read_hvip_hi_hi, read_hvip_hi_lo}; // @[CSR.scala:555:27] wire [15:0] _read_hvip_T = {read_hvip_hi, read_hvip_lo}; // @[CSR.scala:555:27] reg reg_vsstatus_spp; // @[CSR.scala:562:25] assign io_gstatus_spp = reg_vsstatus_spp; // @[CSR.scala:377:7, :562:25] reg reg_vsstatus_spie; // @[CSR.scala:562:25] assign io_gstatus_spie = reg_vsstatus_spie; // @[CSR.scala:377:7, :562:25] reg reg_vsstatus_sie; // @[CSR.scala:562:25] assign io_gstatus_sie = reg_vsstatus_sie; // @[CSR.scala:377:7, :562:25] reg [39:0] reg_vsepc; // @[CSR.scala:564:22] reg [63:0] reg_vscause; // @[CSR.scala:565:24] reg [39:0] reg_vstval; // @[CSR.scala:566:23] reg [39:0] reg_sepc; // @[CSR.scala:569:21] reg [63:0] reg_scause; // @[CSR.scala:570:23] reg [39:0] reg_stval; // @[CSR.scala:571:22] reg [63:0] reg_sscratch; // @[CSR.scala:572:25] reg [38:0] reg_stvec; // @[CSR.scala:573:22] reg [3:0] reg_satp_mode; // @[CSR.scala:574:21] assign io_ptbr_mode_0 = reg_satp_mode; // @[CSR.scala:377:7, :574:21] reg [43:0] reg_satp_ppn; // @[CSR.scala:574:21] assign io_ptbr_ppn_0 = reg_satp_ppn; // @[CSR.scala:377:7, :574:21] reg reg_wfi; // @[CSR.scala:575:54] assign io_status_wfi_0 = reg_wfi; // @[CSR.scala:377:7, :575:54] reg [4:0] reg_fflags; // @[CSR.scala:577:23] reg [2:0] reg_frm; // @[CSR.scala:578:20] assign io_fcsr_rm_0 = reg_frm; // @[CSR.scala:377:7, :578:20] reg reg_mtinst_read_pseudo; // @[CSR.scala:584:35] reg reg_htinst_read_pseudo; // @[CSR.scala:585:35] wire [1:0] hi_4 = {2{reg_mtinst_read_pseudo}}; // @[CSR.scala:584:35, :588:103] wire [13:0] read_mtinst = {hi_4, 12'h0}; // @[CSR.scala:588:103] wire [1:0] hi_5 = {2{reg_htinst_read_pseudo}}; // @[CSR.scala:585:35, :588:103] wire [13:0] read_htinst = {hi_5, 12'h0}; // @[CSR.scala:588:103] reg [4:0] reg_mcountinhibit; // @[CSR.scala:590:34] assign _io_inhibit_cycle_T = reg_mcountinhibit[0]; // @[CSR.scala:590:34, :591:40] wire x11 = reg_mcountinhibit[0]; // @[CSR.scala:590:34, :591:40, :594:98] assign io_inhibit_cycle = _io_inhibit_cycle_T; // @[CSR.scala:377:7, :591:40] wire x3 = reg_mcountinhibit[2]; // @[CSR.scala:590:34, :592:75] reg [5:0] small_0; // @[Counters.scala:45:41] wire [6:0] nextSmall = {1'h0, small_0} + {6'h0, io_retire_0}; // @[Counters.scala:45:41, :46:33] wire _large_T_1 = ~x3; // @[Counters.scala:47:9, :51:36] reg [57:0] large_0; // @[Counters.scala:50:31] wire _large_T = nextSmall[6]; // @[Counters.scala:46:33, :51:20] wire _large_T_2 = _large_T & _large_T_1; // @[Counters.scala:51:{20,33,36}] wire [58:0] _large_r_T = {1'h0, large_0} + 59'h1; // @[Counters.scala:50:31, :51:55] wire [57:0] _large_r_T_1 = _large_r_T[57:0]; // @[Counters.scala:51:55] wire [63:0] value = {large_0, small_0}; // @[Counters.scala:45:41, :50:31, :55:30] wire x10 = ~io_csr_stall_0; // @[CSR.scala:377:7, :594:56] reg [5:0] small_1; // @[Counters.scala:45:41] wire [6:0] nextSmall_1 = {1'h0, small_1} + {6'h0, x10}; // @[Counters.scala:45:41, :46:33] wire _large_T_4 = ~x11; // @[Counters.scala:47:9, :51:36] reg [57:0] large_1; // @[Counters.scala:50:31] wire _large_T_3 = nextSmall_1[6]; // @[Counters.scala:46:33, :51:20] wire _large_T_5 = _large_T_3 & _large_T_4; // @[Counters.scala:51:{20,33,36}] wire [58:0] _large_r_T_2 = {1'h0, large_1} + 59'h1; // @[Counters.scala:50:31, :51:55] wire [57:0] _large_r_T_3 = _large_r_T_2[57:0]; // @[Counters.scala:51:55] assign value_1 = {large_1, small_1}; // @[Counters.scala:45:41, :50:31, :55:30] assign io_time_0 = value_1; // @[Counters.scala:55:30] reg [63:0] reg_hpmevent_0; // @[CSR.scala:595:50] assign io_counters_0_eventSel_0 = reg_hpmevent_0; // @[CSR.scala:377:7, :595:50] reg [63:0] reg_hpmevent_1; // @[CSR.scala:595:50] assign io_counters_1_eventSel_0 = reg_hpmevent_1; // @[CSR.scala:377:7, :595:50] reg [5:0] small_2; // @[Counters.scala:45:69] wire [6:0] nextSmall_2 = {1'h0, small_2} + {6'h0, io_counters_0_inc_0}; // @[Counters.scala:45:69, :46:33] wire _large_T_7 = ~(reg_mcountinhibit[3]); // @[Counters.scala:47:9, :51:36] reg [33:0] large_2; // @[Counters.scala:50:69] wire _large_T_6 = nextSmall_2[6]; // @[Counters.scala:46:33, :51:20] wire _large_T_8 = _large_T_6 & _large_T_7; // @[Counters.scala:51:{20,33,36}] wire [34:0] _large_r_T_4 = {1'h0, large_2} + 35'h1; // @[Counters.scala:50:69, :51:55] wire [33:0] _large_r_T_5 = _large_r_T_4[33:0]; // @[Counters.scala:51:55] wire [39:0] value_2 = {large_2, small_2}; // @[Counters.scala:45:69, :50:69, :55:30] reg [5:0] small_3; // @[Counters.scala:45:69] wire [6:0] nextSmall_3 = {1'h0, small_3} + {6'h0, io_counters_1_inc_0}; // @[Counters.scala:45:69, :46:33] wire _large_T_10 = ~(reg_mcountinhibit[4]); // @[Counters.scala:47:9, :51:36] reg [33:0] large_3; // @[Counters.scala:50:69] wire _large_T_9 = nextSmall_3[6]; // @[Counters.scala:46:33, :51:20] wire _large_T_11 = _large_T_9 & _large_T_10; // @[Counters.scala:51:{20,33,36}] wire [34:0] _large_r_T_6 = {1'h0, large_3} + 35'h1; // @[Counters.scala:50:69, :51:55] wire [33:0] _large_r_T_7 = _large_r_T_6[33:0]; // @[Counters.scala:51:55] wire [39:0] value_3 = {large_3, small_3}; // @[Counters.scala:45:69, :50:69, :55:30] wire read_mip_hi_hi_hi_hi = mip_zero1; // @[CSR.scala:600:24, :610:22] wire _mip_seip_T; // @[CSR.scala:606:57] wire mip_seip; // @[CSR.scala:600:24] assign _mip_seip_T = reg_mip_seip \| io_interrupts_seip_0; // @[CSR.scala:377:7, :504:20, :606:57] assign mip_seip = _mip_seip_T; // @[CSR.scala:600:24, :606:57] wire [1:0] read_mip_lo_lo_lo = {mip_ssip, mip_usip}; // @[CSR.scala:600:24, :610:22] wire [1:0] read_mip_lo_lo_hi = {mip_msip, mip_vssip}; // @[CSR.scala:600:24, :610:22] wire [3:0] read_mip_lo_lo = {read_mip_lo_lo_hi, read_mip_lo_lo_lo}; // @[CSR.scala:610:22] wire [1:0] read_mip_lo_hi_lo = {mip_stip, mip_utip}; // @[CSR.scala:600:24, :610:22] wire [1:0] read_mip_lo_hi_hi = {mip_mtip, mip_vstip}; // @[CSR.scala:600:24, :610:22] wire [3:0] read_mip_lo_hi = {read_mip_lo_hi_hi, read_mip_lo_hi_lo}; // @[CSR.scala:610:22] wire [7:0] read_mip_lo = {read_mip_lo_hi, read_mip_lo_lo}; // @[CSR.scala:610:22] wire [1:0] read_mip_hi_lo_lo = {mip_seip, mip_ueip}; // @[CSR.scala:600:24, :610:22] wire [1:0] read_mip_hi_lo_hi = {mip_meip, mip_vseip}; // @[CSR.scala:600:24, :610:22] wire [3:0] read_mip_hi_lo = {read_mip_hi_lo_hi, read_mip_hi_lo_lo}; // @[CSR.scala:610:22] wire [1:0] read_mip_hi_hi_lo = {1'h0, mip_sgeip}; // @[CSR.scala:600:24, :610:22] wire [1:0] read_mip_hi_hi_hi = {read_mip_hi_hi_hi_hi, mip_debug}; // @[CSR.scala:600:24, :610:22] wire [3:0] read_mip_hi_hi = {read_mip_hi_hi_hi, read_mip_hi_hi_lo}; // @[CSR.scala:610:22] wire [7:0] read_mip_hi = {read_mip_hi_hi, read_mip_hi_lo}; // @[CSR.scala:610:22] wire [15:0] _read_mip_T = {read_mip_hi, read_mip_lo}; // @[CSR.scala:610:22] wire [15:0] read_mip = _read_mip_T & 16'hAAA; // @[CSR.scala:610:{22,29}] wire [63:0] _pending_interrupts_T = {48'h0, reg_mie[15:0] & read_mip}; // @[CSR.scala:495:20, :610:29, :614:56] wire [63:0] pending_interrupts = _pending_interrupts_T; // @[CSR.scala:614:{44,56}] wire [14:0] d_interrupts = {io_interrupts_debug_0, 14'h0}; // @[CSR.scala:377:7, :615:42] wire _allow_wfi_T = reg_mstatus_prv[1]; // @[CSR.scala:395:28, :620:51, :906:61] wire _allow_sfence_vma_T = reg_mstatus_prv[1]; // @[CSR.scala:395:28, :620:51, :907:60] wire _allow_sret_T = reg_mstatus_prv[1]; // @[CSR.scala:395:28, :620:51, :910:62] wire _allow_counter_T = reg_mstatus_prv[1]; // @[CSR.scala:395:28, :620:51, :912:42] wire _m_interrupts_T = ~(reg_mstatus_prv[1]); // @[CSR.scala:395:28, :620:51] wire _m_interrupts_T_1 = _m_interrupts_T \| reg_mstatus_mie; // @[CSR.scala:395:28, :620:{51,62}] wire _m_interrupts_T_2 = _m_interrupts_T_1; // @[CSR.scala:620:{31,62}] wire [63:0] _m_interrupts_T_3 = ~pending_interrupts; // @[CSR.scala:614:44, :620:85] wire [63:0] _m_interrupts_T_4 = _m_interrupts_T_3 \| read_mideleg; // @[CSR.scala:498:14, :620:{85,105}] wire [63:0] _m_interrupts_T_5 = ~_m_interrupts_T_4; // @[CSR.scala:620:{83,105}] wire [63:0] m_interrupts = _m_interrupts_T_2 ? _m_interrupts_T_5 : 64'h0; // @[CSR.scala:620:{25,31,83}] wire _GEN_2 = reg_mstatus_prv == 2'h0; // @[CSR.scala:395:28, :621:68] wire _s_interrupts_T; // @[CSR.scala:621:68] assign _s_interrupts_T = _GEN_2; // @[CSR.scala:621:68] wire _vs_interrupts_T; // @[CSR.scala:622:70] assign _vs_interrupts_T = _GEN_2; // @[CSR.scala:621:68, :622:70] wire _io_fiom_T_2; // @[CSR.scala:631:82] assign _io_fiom_T_2 = _GEN_2; // @[CSR.scala:621:68, :631:82] wire _s_interrupts_T_1 = reg_mstatus_v \| _s_interrupts_T; // @[CSR.scala:395:28, :621:{49,68}] wire _GEN_3 = reg_mstatus_prv == 2'h1; // @[CSR.scala:395:28, :621:98] wire _s_interrupts_T_2; // @[CSR.scala:621:98] assign _s_interrupts_T_2 = _GEN_3; // @[CSR.scala:621:98] wire _vs_interrupts_T_1; // @[CSR.scala:622:99] assign _vs_interrupts_T_1 = _GEN_3; // @[CSR.scala:621:98, :622:99] wire _csr_addr_legal_T_4; // @[CSR.scala:921:62] assign _csr_addr_legal_T_4 = _GEN_3; // @[CSR.scala:621:98, :921:62] wire _s_interrupts_T_3 = _s_interrupts_T_2 & reg_mstatus_sie; // @[CSR.scala:395:28, :621:{98,110}] wire _s_interrupts_T_4 = _s_interrupts_T_1 \| _s_interrupts_T_3; // @[CSR.scala:621:{49,78,110}] wire _s_interrupts_T_5 = _s_interrupts_T_4; // @[CSR.scala:621:{31,78}] wire [63:0] _s_interrupts_T_6 = pending_interrupts & read_mideleg; // @[CSR.scala:498:14, :614:44, :621:151] wire [63:0] _s_interrupts_T_8 = _s_interrupts_T_6; // @[CSR.scala:621:{151,166}] wire [63:0] s_interrupts = _s_interrupts_T_5 ? _s_interrupts_T_8 : 64'h0; // @[CSR.scala:621:{25,31,166}] wire _vs_interrupts_T_2 = _vs_interrupts_T_1 & reg_vsstatus_sie; // @[CSR.scala:562:25, :622:{99,111}] wire _vs_interrupts_T_3 = _vs_interrupts_T \| _vs_interrupts_T_2; // @[CSR.scala:622:{70,80,111}] wire _vs_interrupts_T_4 = reg_mstatus_v & _vs_interrupts_T_3; // @[CSR.scala:395:28, :622:{50,80}] wire _vs_interrupts_T_5 = _vs_interrupts_T_4; // @[CSR.scala:622:{32,50}] wire _any_T = d_interrupts[14]; // @[CSR.scala:615:42, :1637:76] wire _which_T = d_interrupts[14]; // @[CSR.scala:615:42, :1637:76, :1638:91] wire _any_T_1 = d_interrupts[13]; // @[CSR.scala:615:42, :1637:76] wire _which_T_1 = d_interrupts[13]; // @[CSR.scala:615:42, :1637:76, :1638:91] wire _any_T_2 = d_interrupts[12]; // @[CSR.scala:615:42, :1637:76] wire _which_T_2 = d_interrupts[12]; // @[CSR.scala:615:42, :1637:76, :1638:91] wire _any_T_3 = d_interrupts[11]; // @[CSR.scala:615:42, :1637:76] wire _which_T_3 = d_interrupts[11]; // @[CSR.scala:615:42, :1637:76, :1638:91] wire _any_T_4 = d_interrupts[3]; // @[CSR.scala:615:42, :1637:76] wire _which_T_4 = d_interrupts[3]; // @[CSR.scala:615:42, :1637:76, :1638:91] wire _any_T_5 = d_interrupts[7]; // @[CSR.scala:615:42, :1637:76] wire _which_T_5 = d_interrupts[7]; // @[CSR.scala:615:42, :1637:76, :1638:91] wire _any_T_6 = d_interrupts[9]; // @[CSR.scala:615:42, :1637:76] wire _which_T_6 = d_interrupts[9]; // @[CSR.scala:615:42, :1637:76, :1638:91] wire _any_T_7 = d_interrupts[1]; // @[CSR.scala:615:42, :1637:76] wire _which_T_7 = d_interrupts[1]; // @[CSR.scala:615:42, :1637:76, :1638:91] wire _any_T_8 = d_interrupts[5]; // @[CSR.scala:615:42, :1637:76] wire _which_T_8 = d_interrupts[5]; // @[CSR.scala:615:42, :1637:76, :1638:91] wire _any_T_9 = d_interrupts[10]; // @[CSR.scala:615:42, :1637:76] wire _which_T_9 = d_interrupts[10]; // @[CSR.scala:615:42, :1637:76, :1638:91] wire _any_T_10 = d_interrupts[2]; // @[CSR.scala:615:42, :1637:76] wire _which_T_10 = d_interrupts[2]; // @[CSR.scala:615:42, :1637:76, :1638:91] wire _any_T_11 = d_interrupts[6]; // @[CSR.scala:615:42, :1637:76] wire _which_T_11 = d_interrupts[6]; // @[CSR.scala:615:42, :1637:76, :1638:91] wire _any_T_12 = d_interrupts[8]; // @[CSR.scala:615:42, :1637:76] wire _which_T_12 = d_interrupts[8]; // @[CSR.scala:615:42, :1637:76, :1638:91] wire _any_T_13 = d_interrupts[0]; // @[CSR.scala:615:42, :1637:76] wire _which_T_13 = d_interrupts[0]; // @[CSR.scala:615:42, :1637:76, :1638:91] wire _any_T_14 = d_interrupts[4]; // @[CSR.scala:615:42, :1637:76] wire _which_T_14 = d_interrupts[4]; // @[CSR.scala:615:42, :1637:76, :1638:91] wire _any_T_15 = m_interrupts[15]; // @[CSR.scala:620:25, :1637:76] wire _which_T_15 = m_interrupts[15]; // @[CSR.scala:620:25, :1637:76, :1638:91] wire _any_T_16 = m_interrupts[14]; // @[CSR.scala:620:25, :1637:76] wire _which_T_16 = m_interrupts[14]; // @[CSR.scala:620:25, :1637:76, :1638:91] wire _any_T_17 = m_interrupts[13]; // @[CSR.scala:620:25, :1637:76] wire _which_T_17 = m_interrupts[13]; // @[CSR.scala:620:25, :1637:76, :1638:91] wire _any_T_18 = m_interrupts[12]; // @[CSR.scala:620:25, :1637:76] wire _which_T_18 = m_interrupts[12]; // @[CSR.scala:620:25, :1637:76, :1638:91] wire _any_T_19 = m_interrupts[11]; // @[CSR.scala:620:25, :1637:76] wire _which_T_19 = m_interrupts[11]; // @[CSR.scala:620:25, :1637:76, :1638:91] wire _any_T_20 = m_interrupts[3]; // @[CSR.scala:620:25, :1637:76] wire _which_T_20 = m_interrupts[3]; // @[CSR.scala:620:25, :1637:76, :1638:91] wire _any_T_21 = m_interrupts[7]; // @[CSR.scala:620:25, :1637:76] wire _which_T_21 = m_interrupts[7]; // @[CSR.scala:620:25, :1637:76, :1638:91] wire _any_T_22 = m_interrupts[9]; // @[CSR.scala:620:25, :1637:76] wire _which_T_22 = m_interrupts[9]; // @[CSR.scala:620:25, :1637:76, :1638:91] wire _any_T_23 = m_interrupts[1]; // @[CSR.scala:620:25, :1637:76] wire _which_T_23 = m_interrupts[1]; // @[CSR.scala:620:25, :1637:76, :1638:91] wire _any_T_24 = m_interrupts[5]; // @[CSR.scala:620:25, :1637:76] wire _which_T_24 = m_interrupts[5]; // @[CSR.scala:620:25, :1637:76, :1638:91] wire _any_T_25 = m_interrupts[10]; // @[CSR.scala:620:25, :1637:76] wire _which_T_25 = m_interrupts[10]; // @[CSR.scala:620:25, :1637:76, :1638:91] wire _any_T_26 = m_interrupts[2]; // @[CSR.scala:620:25, :1637:76] wire _which_T_26 = m_interrupts[2]; // @[CSR.scala:620:25, :1637:76, :1638:91] wire _any_T_27 = m_interrupts[6]; // @[CSR.scala:620:25, :1637:76] wire _which_T_27 = m_interrupts[6]; // @[CSR.scala:620:25, :1637:76, :1638:91] wire _any_T_28 = m_interrupts[8]; // @[CSR.scala:620:25, :1637:76] wire _which_T_28 = m_interrupts[8]; // @[CSR.scala:620:25, :1637:76, :1638:91] wire _any_T_29 = m_interrupts[0]; // @[CSR.scala:620:25, :1637:76] wire _which_T_29 = m_interrupts[0]; // @[CSR.scala:620:25, :1637:76, :1638:91] wire _any_T_30 = m_interrupts[4]; // @[CSR.scala:620:25, :1637:76] wire _which_T_30 = m_interrupts[4]; // @[CSR.scala:620:25, :1637:76, :1638:91] wire _any_T_31 = s_interrupts[15]; // @[CSR.scala:621:25, :1637:76] wire _which_T_31 = s_interrupts[15]; // @[CSR.scala:621:25, :1637:76, :1638:91] wire _any_T_32 = s_interrupts[14]; // @[CSR.scala:621:25, :1637:76] wire _which_T_32 = s_interrupts[14]; // @[CSR.scala:621:25, :1637:76, :1638:91] wire _any_T_33 = s_interrupts[13]; // @[CSR.scala:621:25, :1637:76] wire _which_T_33 = s_interrupts[13]; // @[CSR.scala:621:25, :1637:76, :1638:91] wire _any_T_34 = s_interrupts[12]; // @[CSR.scala:621:25, :1637:76] wire _which_T_34 = s_interrupts[12]; // @[CSR.scala:621:25, :1637:76, :1638:91] wire _any_T_35 = s_interrupts[11]; // @[CSR.scala:621:25, :1637:76] wire _which_T_35 = s_interrupts[11]; // @[CSR.scala:621:25, :1637:76, :1638:91] wire _any_T_36 = s_interrupts[3]; // @[CSR.scala:621:25, :1637:76] wire _which_T_36 = s_interrupts[3]; // @[CSR.scala:621:25, :1637:76, :1638:91] wire _any_T_37 = s_interrupts[7]; // @[CSR.scala:621:25, :1637:76] wire _which_T_37 = s_interrupts[7]; // @[CSR.scala:621:25, :1637:76, :1638:91] wire _any_T_38 = s_interrupts[9]; // @[CSR.scala:621:25, :1637:76] wire _which_T_38 = s_interrupts[9]; // @[CSR.scala:621:25, :1637:76, :1638:91] wire _any_T_39 = s_interrupts[1]; // @[CSR.scala:621:25, :1637:76] wire _which_T_39 = s_interrupts[1]; // @[CSR.scala:621:25, :1637:76, :1638:91] wire _any_T_40 = s_interrupts[5]; // @[CSR.scala:621:25, :1637:76] wire _which_T_40 = s_interrupts[5]; // @[CSR.scala:621:25, :1637:76, :1638:91] wire _any_T_41 = s_interrupts[10]; // @[CSR.scala:621:25, :1637:76] wire _which_T_41 = s_interrupts[10]; // @[CSR.scala:621:25, :1637:76, :1638:91] wire _any_T_42 = s_interrupts[2]; // @[CSR.scala:621:25, :1637:76] wire _which_T_42 = s_interrupts[2]; // @[CSR.scala:621:25, :1637:76, :1638:91] wire _any_T_43 = s_interrupts[6]; // @[CSR.scala:621:25, :1637:76] wire _which_T_43 = s_interrupts[6]; // @[CSR.scala:621:25, :1637:76, :1638:91] wire _any_T_44 = s_interrupts[8]; // @[CSR.scala:621:25, :1637:76] wire _which_T_44 = s_interrupts[8]; // @[CSR.scala:621:25, :1637:76, :1638:91] wire _any_T_45 = s_interrupts[0]; // @[CSR.scala:621:25, :1637:76] wire _which_T_45 = s_interrupts[0]; // @[CSR.scala:621:25, :1637:76, :1638:91] wire _any_T_46 = s_interrupts[4]; // @[CSR.scala:621:25, :1637:76] wire _which_T_46 = s_interrupts[4]; // @[CSR.scala:621:25, :1637:76, :1638:91] wire _any_T_63 = _any_T \| _any_T_1; // @[CSR.scala:1637:{76,90}] wire _any_T_64 = _any_T_63 \| _any_T_2; // @[CSR.scala:1637:{76,90}] wire _any_T_65 = _any_T_64 \| _any_T_3; // @[CSR.scala:1637:{76,90}] wire _any_T_66 = _any_T_65 \| _any_T_4; // @[CSR.scala:1637:{76,90}] wire _any_T_67 = _any_T_66 \| _any_T_5; // @[CSR.scala:1637:{76,90}] wire _any_T_68 = _any_T_67 \| _any_T_6; // @[CSR.scala:1637:{76,90}] wire _any_T_69 = _any_T_68 \| _any_T_7; // @[CSR.scala:1637:{76,90}] wire _any_T_70 = _any_T_69 \| _any_T_8; // @[CSR.scala:1637:{76,90}] wire _any_T_71 = _any_T_70 \| _any_T_9; // @[CSR.scala:1637:{76,90}] wire _any_T_72 = _any_T_71 \| _any_T_10; // @[CSR.scala:1637:{76,90}] wire _any_T_73 = _any_T_72 \| _any_T_11; // @[CSR.scala:1637:{76,90}] wire _any_T_74 = _any_T_73 \| _any_T_12; // @[CSR.scala:1637:{76,90}] wire _any_T_75 = _any_T_74 \| _any_T_13; // @[CSR.scala:1637:{76,90}] wire _any_T_76 = _any_T_75 \| _any_T_14; // @[CSR.scala:1637:{76,90}] wire _any_T_77 = _any_T_76; // @[CSR.scala:1637:90] wire _any_T_78 = _any_T_77 \| _any_T_15; // @[CSR.scala:1637:{76,90}] wire _any_T_79 = _any_T_78 \| _any_T_16; // @[CSR.scala:1637:{76,90}] wire _any_T_80 = _any_T_79 \| _any_T_17; // @[CSR.scala:1637:{76,90}] wire _any_T_81 = _any_T_80 \| _any_T_18; // @[CSR.scala:1637:{76,90}] wire _any_T_82 = _any_T_81 \| _any_T_19; // @[CSR.scala:1637:{76,90}] wire _any_T_83 = _any_T_82 \| _any_T_20; // @[CSR.scala:1637:{76,90}] wire _any_T_84 = _any_T_83 \| _any_T_21; // @[CSR.scala:1637:{76,90}] wire _any_T_85 = _any_T_84 \| _any_T_22; // @[CSR.scala:1637:{76,90}] wire _any_T_86 = _any_T_85 \| _any_T_23; // @[CSR.scala:1637:{76,90}] wire _any_T_87 = _any_T_86 \| _any_T_24; // @[CSR.scala:1637:{76,90}] wire _any_T_88 = _any_T_87 \| _any_T_25; // @[CSR.scala:1637:{76,90}] wire _any_T_89 = _any_T_88 \| _any_T_26; // @[CSR.scala:1637:{76,90}] wire _any_T_90 = _any_T_89 \| _any_T_27; // @[CSR.scala:1637:{76,90}] wire _any_T_91 = _any_T_90 \| _any_T_28; // @[CSR.scala:1637:{76,90}] wire _any_T_92 = _any_T_91 \| _any_T_29; // @[CSR.scala:1637:{76,90}] wire _any_T_93 = _any_T_92 \| _any_T_30; // @[CSR.scala:1637:{76,90}] wire _any_T_94 = _any_T_93 \| _any_T_31; // @[CSR.scala:1637:{76,90}] wire _any_T_95 = _any_T_94 \| _any_T_32; // @[CSR.scala:1637:{76,90}] wire _any_T_96 = _any_T_95 \| _any_T_33; // @[CSR.scala:1637:{76,90}] wire _any_T_97 = _any_T_96 \| _any_T_34; // @[CSR.scala:1637:{76,90}] wire _any_T_98 = _any_T_97 \| _any_T_35; // @[CSR.scala:1637:{76,90}] wire _any_T_99 = _any_T_98 \| _any_T_36; // @[CSR.scala:1637:{76,90}] wire _any_T_100 = _any_T_99 \| _any_T_37; // @[CSR.scala:1637:{76,90}] wire _any_T_101 = _any_T_100 \| _any_T_38; // @[CSR.scala:1637:{76,90}] wire _any_T_102 = _any_T_101 \| _any_T_39; // @[CSR.scala:1637:{76,90}] wire _any_T_103 = _any_T_102 \| _any_T_40; // @[CSR.scala:1637:{76,90}] wire _any_T_104 = _any_T_103 \| _any_T_41; // @[CSR.scala:1637:{76,90}] wire _any_T_105 = _any_T_104 \| _any_T_42; // @[CSR.scala:1637:{76,90}] wire _any_T_106 = _any_T_105 \| _any_T_43; // @[CSR.scala:1637:{76,90}] wire _any_T_107 = _any_T_106 \| _any_T_44; // @[CSR.scala:1637:{76,90}] wire _any_T_108 = _any_T_107 \| _any_T_45; // @[CSR.scala:1637:{76,90}] wire _any_T_109 = _any_T_108 \| _any_T_46; // @[CSR.scala:1637:{76,90}] wire _any_T_110 = _any_T_109; // @[CSR.scala:1637:90] wire _any_T_111 = _any_T_110; // @[CSR.scala:1637:90] wire _any_T_112 = _any_T_111; // @[CSR.scala:1637:90] wire _any_T_113 = _any_T_112; // @[CSR.scala:1637:90] wire _any_T_114 = _any_T_113; // @[CSR.scala:1637:90] wire _any_T_115 = _any_T_114; // @[CSR.scala:1637:90] wire _any_T_116 = _any_T_115; // @[CSR.scala:1637:90] wire _any_T_117 = _any_T_116; // @[CSR.scala:1637:90] wire _any_T_118 = _any_T_117; // @[CSR.scala:1637:90] wire _any_T_119 = _any_T_118; // @[CSR.scala:1637:90] wire _any_T_120 = _any_T_119; // @[CSR.scala:1637:90] wire _any_T_121 = _any_T_120; // @[CSR.scala:1637:90] wire _any_T_122 = _any_T_121; // @[CSR.scala:1637:90] wire _any_T_123 = _any_T_122; // @[CSR.scala:1637:90] wire _any_T_124 = _any_T_123; // @[CSR.scala:1637:90] wire anyInterrupt = _any_T_124; // @[CSR.scala:1637:90] wire [3:0] _which_T_79 = {1'h0, ~_which_T_45, 2'h0}; // @[Mux.scala:50:70] wire [3:0] _which_T_80 = _which_T_44 ? 4'h8 : _which_T_79; // @[Mux.scala:50:70] wire [3:0] _which_T_81 = _which_T_43 ? 4'h6 : _which_T_80; // @[Mux.scala:50:70] wire [3:0] _which_T_82 = _which_T_42 ? 4'h2 : _which_T_81; // @[Mux.scala:50:70] wire [3:0] _which_T_83 = _which_T_41 ? 4'hA : _which_T_82; // @[Mux.scala:50:70] wire [3:0] _which_T_84 = _which_T_40 ? 4'h5 : _which_T_83; // @[Mux.scala:50:70] wire [3:0] _which_T_85 = _which_T_39 ? 4'h1 : _which_T_84; // @[Mux.scala:50:70] wire [3:0] _which_T_86 = _which_T_38 ? 4'h9 : _which_T_85; // @[Mux.scala:50:70] wire [3:0] _which_T_87 = _which_T_37 ? 4'h7 : _which_T_86; // @[Mux.scala:50:70] wire [3:0] _which_T_88 = _which_T_36 ? 4'h3 : _which_T_87; // @[Mux.scala:50:70] wire [3:0] _which_T_89 = _which_T_35 ? 4'hB : _which_T_88; // @[Mux.scala:50:70] wire [3:0] _which_T_90 = _which_T_34 ? 4'hC : _which_T_89; // @[Mux.scala:50:70] wire [3:0] _which_T_91 = _which_T_33 ? 4'hD : _which_T_90; // @[Mux.scala:50:70] wire [3:0] _which_T_92 = _which_T_32 ? 4'hE : _which_T_91; // @[Mux.scala:50:70] wire [3:0] _which_T_93 = _which_T_31 ? 4'hF : _which_T_92; // @[Mux.scala:50:70] wire [3:0] _which_T_94 = _which_T_30 ? 4'h4 : _which_T_93; // @[Mux.scala:50:70] wire [3:0] _which_T_95 = _which_T_29 ? 4'h0 : _which_T_94; // @[Mux.scala:50:70] wire [3:0] _which_T_96 = _which_T_28 ? 4'h8 : _which_T_95; // @[Mux.scala:50:70] wire [3:0] _which_T_97 = _which_T_27 ? 4'h6 : _which_T_96; // @[Mux.scala:50:70] wire [3:0] _which_T_98 = _which_T_26 ? 4'h2 : _which_T_97; // @[Mux.scala:50:70] wire [3:0] _which_T_99 = _which_T_25 ? 4'hA : _which_T_98; // @[Mux.scala:50:70] wire [3:0] _which_T_100 = _which_T_24 ? 4'h5 : _which_T_99; // @[Mux.scala:50:70] wire [3:0] _which_T_101 = _which_T_23 ? 4'h1 : _which_T_100; // @[Mux.scala:50:70] wire [3:0] _which_T_102 = _which_T_22 ? 4'h9 : _which_T_101; // @[Mux.scala:50:70] wire [3:0] _which_T_103 = _which_T_21 ? 4'h7 : _which_T_102; // @[Mux.scala:50:70] wire [3:0] _which_T_104 = _which_T_20 ? 4'h3 : _which_T_103; // @[Mux.scala:50:70] wire [3:0] _which_T_105 = _which_T_19 ? 4'hB : _which_T_104; // @[Mux.scala:50:70] wire [3:0] _which_T_106 = _which_T_18 ? 4'hC : _which_T_105; // @[Mux.scala:50:70] wire [3:0] _which_T_107 = _which_T_17 ? 4'hD : _which_T_106; // @[Mux.scala:50:70] wire [3:0] _which_T_108 = _which_T_16 ? 4'hE : _which_T_107; // @[Mux.scala:50:70] wire [3:0] _which_T_109 = _which_T_15 ? 4'hF : _which_T_108; // @[Mux.scala:50:70] wire [3:0] _which_T_110 = _which_T_109; // @[Mux.scala:50:70] wire [3:0] _which_T_111 = _which_T_14 ? 4'h4 : _which_T_110; // @[Mux.scala:50:70] wire [3:0] _which_T_112 = _which_T_13 ? 4'h0 : _which_T_111; // @[Mux.scala:50:70] wire [3:0] _which_T_113 = _which_T_12 ? 4'h8 : _which_T_112; // @[Mux.scala:50:70] wire [3:0] _which_T_114 = _which_T_11 ? 4'h6 : _which_T_113; // @[Mux.scala:50:70] wire [3:0] _which_T_115 = _which_T_10 ? 4'h2 : _which_T_114; // @[Mux.scala:50:70] wire [3:0] _which_T_116 = _which_T_9 ? 4'hA : _which_T_115; // @[Mux.scala:50:70] wire [3:0] _which_T_117 = _which_T_8 ? 4'h5 : _which_T_116; // @[Mux.scala:50:70] wire [3:0] _which_T_118 = _which_T_7 ? 4'h1 : _which_T_117; // @[Mux.scala:50:70] wire [3:0] _which_T_119 = _which_T_6 ? 4'h9 : _which_T_118; // @[Mux.scala:50:70] wire [3:0] _which_T_120 = _which_T_5 ? 4'h7 : _which_T_119; // @[Mux.scala:50:70] wire [3:0] _which_T_121 = _which_T_4 ? 4'h3 : _which_T_120; // @[Mux.scala:50:70] wire [3:0] _which_T_122 = _which_T_3 ? 4'hB : _which_T_121; // @[Mux.scala:50:70] wire [3:0] _which_T_123 = _which_T_2 ? 4'hC : _which_T_122; // @[Mux.scala:50:70] wire [3:0] _which_T_124 = _which_T_1 ? 4'hD : _which_T_123; // @[Mux.scala:50:70] wire [3:0] whichInterrupt = _which_T ? 4'hE : _which_T_124; // @[Mux.scala:50:70] wire [64:0] _interruptCause_T_3 = {61'h0, whichInterrupt} + 65'h8000000000000000; // @[Mux.scala:50:70] assign interruptCause = _interruptCause_T_3[63:0]; // @[CSR.scala:625:63] assign io_interrupt_cause_0 = interruptCause; // @[CSR.scala:377:7, :625:63] wire _io_interrupt_T = ~io_singleStep_0; // @[CSR.scala:377:7, :626:36] wire _io_interrupt_T_1 = anyInterrupt & _io_interrupt_T; // @[CSR.scala:626:{33,36}, :1637:90] wire _io_interrupt_T_2 = _io_interrupt_T_1 \| reg_singleStepped; // @[CSR.scala:486:30, :626:{33,51}] wire _io_interrupt_T_3 = reg_debug \| io_status_cease_0; // @[CSR.scala:377:7, :482:26, :626:88] wire _io_interrupt_T_4 = ~_io_interrupt_T_3; // @[CSR.scala:626:{76,88}] assign _io_interrupt_T_5 = _io_interrupt_T_2 & _io_interrupt_T_4; // @[CSR.scala:626:{51,73,76}] assign io_interrupt_0 = _io_interrupt_T_5; // @[CSR.scala:377:7, :626:73] wire _io_fiom_T = reg_mstatus_prv != 2'h3; // @[CSR.scala:395:28, :631:31] wire _io_fiom_T_1 = _io_fiom_T & reg_menvcfg_fiom; // @[CSR.scala:525:28, :631:{31,41}] wire _io_fiom_T_3 = _io_fiom_T_2 & reg_senvcfg_fiom; // @[CSR.scala:526:28, :631:{82,92}] wire _io_fiom_T_4 = _io_fiom_T_1 \| _io_fiom_T_3; // @[CSR.scala:631:{41,62,92}] assign _io_fiom_T_6 = _io_fiom_T_4; // @[CSR.scala:631:{62,113}] assign io_fiom = _io_fiom_T_6; // @[CSR.scala:377:7, :631:113] assign io_pmp_0_cfg_l_0 = pmp_cfg_l; // @[PMP.scala:24:19] assign io_pmp_0_cfg_a_0 = pmp_cfg_a; // @[PMP.scala:24:19] assign io_pmp_0_cfg_x_0 = pmp_cfg_x; // @[PMP.scala:24:19] assign io_pmp_0_cfg_w_0 = pmp_cfg_w; // @[PMP.scala:24:19] assign io_pmp_0_cfg_r_0 = pmp_cfg_r; // @[PMP.scala:24:19] assign io_pmp_0_addr_0 = pmp_addr; // @[PMP.scala:24:19] assign io_pmp_0_mask_0 = pmp_mask; // @[PMP.scala:24:19] wire _pmp_mask_base_T = pmp_cfg_a[0]; // @[PMP.scala:24:19, :57:31] wire [30:0] _pmp_mask_base_T_1 = {pmp_addr, _pmp_mask_base_T}; // @[PMP.scala:24:19, :57:{19,31}] wire [30:0] pmp_mask_base = _pmp_mask_base_T_1; // @[PMP.scala:57:{19,36}] wire [31:0] _pmp_mask_T = {1'h0, pmp_mask_base} + 32'h1; // @[PMP.scala:57:36, :58:23] wire [30:0] _pmp_mask_T_1 = _pmp_mask_T[30:0]; // @[PMP.scala:58:23] wire [30:0] _pmp_mask_T_2 = ~_pmp_mask_T_1; // @[PMP.scala:58:{16,23}] wire [30:0] _pmp_mask_T_3 = pmp_mask_base & _pmp_mask_T_2; // @[PMP.scala:57:36, :58:{14,16}] wire [32:0] _pmp_mask_T_4 = {_pmp_mask_T_3, 2'h3}; // @[PMP.scala:58:{8,14}] assign pmp_mask = _pmp_mask_T_4[31:0]; // @[PMP.scala:24:19, :27:14, :58:8] assign io_pmp_1_cfg_l_0 = pmp_1_cfg_l; // @[PMP.scala:24:19] assign io_pmp_1_cfg_a_0 = pmp_1_cfg_a; // @[PMP.scala:24:19] assign io_pmp_1_cfg_x_0 = pmp_1_cfg_x; // @[PMP.scala:24:19] assign io_pmp_1_cfg_w_0 = pmp_1_cfg_w; // @[PMP.scala:24:19] assign io_pmp_1_cfg_r_0 = pmp_1_cfg_r; // @[PMP.scala:24:19] assign io_pmp_1_addr_0 = pmp_1_addr; // @[PMP.scala:24:19] assign io_pmp_1_mask_0 = pmp_1_mask; // @[PMP.scala:24:19] wire _pmp_mask_base_T_3 = pmp_1_cfg_a[0]; // @[PMP.scala:24:19, :57:31] wire [30:0] _pmp_mask_base_T_4 = {pmp_1_addr, _pmp_mask_base_T_3}; // @[PMP.scala:24:19, :57:{19,31}] wire [30:0] pmp_mask_base_1 = _pmp_mask_base_T_4; // @[PMP.scala:57:{19,36}] wire [31:0] _pmp_mask_T_5 = {1'h0, pmp_mask_base_1} + 32'h1; // @[PMP.scala:57:36, :58:23] wire [30:0] _pmp_mask_T_6 = _pmp_mask_T_5[30:0]; // @[PMP.scala:58:23] wire [30:0] _pmp_mask_T_7 = ~_pmp_mask_T_6; // @[PMP.scala:58:{16,23}] wire [30:0] _pmp_mask_T_8 = pmp_mask_base_1 & _pmp_mask_T_7; // @[PMP.scala:57:36, :58:{14,16}] wire [32:0] _pmp_mask_T_9 = {_pmp_mask_T_8, 2'h3}; // @[PMP.scala:58:{8,14}] assign pmp_1_mask = _pmp_mask_T_9[31:0]; // @[PMP.scala:24:19, :27:14, :58:8] assign io_pmp_2_cfg_l_0 = pmp_2_cfg_l; // @[PMP.scala:24:19] assign io_pmp_2_cfg_a_0 = pmp_2_cfg_a; // @[PMP.scala:24:19] assign io_pmp_2_cfg_x_0 = pmp_2_cfg_x; // @[PMP.scala:24:19] assign io_pmp_2_cfg_w_0 = pmp_2_cfg_w; // @[PMP.scala:24:19] assign io_pmp_2_cfg_r_0 = pmp_2_cfg_r; // @[PMP.scala:24:19] assign io_pmp_2_addr_0 = pmp_2_addr; // @[PMP.scala:24:19] assign io_pmp_2_mask_0 = pmp_2_mask; // @[PMP.scala:24:19] wire _pmp_mask_base_T_6 = pmp_2_cfg_a[0]; // @[PMP.scala:24:19, :57:31] wire [30:0] _pmp_mask_base_T_7 = {pmp_2_addr, _pmp_mask_base_T_6}; // @[PMP.scala:24:19, :57:{19,31}] wire [30:0] pmp_mask_base_2 = _pmp_mask_base_T_7; // @[PMP.scala:57:{19,36}] wire [31:0] _pmp_mask_T_10 = {1'h0, pmp_mask_base_2} + 32'h1; // @[PMP.scala:57:36, :58:23] wire [30:0] _pmp_mask_T_11 = _pmp_mask_T_10[30:0]; // @[PMP.scala:58:23] wire [30:0] _pmp_mask_T_12 = ~_pmp_mask_T_11; // @[PMP.scala:58:{16,23}] wire [30:0] _pmp_mask_T_13 = pmp_mask_base_2 & _pmp_mask_T_12; // @[PMP.scala:57:36, :58:{14,16}] wire [32:0] _pmp_mask_T_14 = {_pmp_mask_T_13, 2'h3}; // @[PMP.scala:58:{8,14}] assign pmp_2_mask = _pmp_mask_T_14[31:0]; // @[PMP.scala:24:19, :27:14, :58:8] assign io_pmp_3_cfg_l_0 = pmp_3_cfg_l; // @[PMP.scala:24:19] assign io_pmp_3_cfg_a_0 = pmp_3_cfg_a; // @[PMP.scala:24:19] assign io_pmp_3_cfg_x_0 = pmp_3_cfg_x; // @[PMP.scala:24:19] assign io_pmp_3_cfg_w_0 = pmp_3_cfg_w; // @[PMP.scala:24:19] assign io_pmp_3_cfg_r_0 = pmp_3_cfg_r; // @[PMP.scala:24:19] assign io_pmp_3_addr_0 = pmp_3_addr; // @[PMP.scala:24:19] assign io_pmp_3_mask_0 = pmp_3_mask; // @[PMP.scala:24:19] wire _pmp_mask_base_T_9 = pmp_3_cfg_a[0]; // @[PMP.scala:24:19, :57:31] wire [30:0] _pmp_mask_base_T_10 = {pmp_3_addr, _pmp_mask_base_T_9}; // @[PMP.scala:24:19, :57:{19,31}] wire [30:0] pmp_mask_base_3 = _pmp_mask_base_T_10; // @[PMP.scala:57:{19,36}] wire [31:0] _pmp_mask_T_15 = {1'h0, pmp_mask_base_3} + 32'h1; // @[PMP.scala:57:36, :58:23] wire [30:0] _pmp_mask_T_16 = _pmp_mask_T_15[30:0]; // @[PMP.scala:58:23] wire [30:0] _pmp_mask_T_17 = ~_pmp_mask_T_16; // @[PMP.scala:58:{16,23}] wire [30:0] _pmp_mask_T_18 = pmp_mask_base_3 & _pmp_mask_T_17; // @[PMP.scala:57:36, :58:{14,16}] wire [32:0] _pmp_mask_T_19 = {_pmp_mask_T_18, 2'h3}; // @[PMP.scala:58:{8,14}] assign pmp_3_mask = _pmp_mask_T_19[31:0]; // @[PMP.scala:24:19, :27:14, :58:8] assign io_pmp_4_cfg_l_0 = pmp_4_cfg_l; // @[PMP.scala:24:19] assign io_pmp_4_cfg_a_0 = pmp_4_cfg_a; // @[PMP.scala:24:19] assign io_pmp_4_cfg_x_0 = pmp_4_cfg_x; // @[PMP.scala:24:19] assign io_pmp_4_cfg_w_0 = pmp_4_cfg_w; // @[PMP.scala:24:19] assign io_pmp_4_cfg_r_0 = pmp_4_cfg_r; // @[PMP.scala:24:19] assign io_pmp_4_addr_0 = pmp_4_addr; // @[PMP.scala:24:19] assign io_pmp_4_mask_0 = pmp_4_mask; // @[PMP.scala:24:19] wire _pmp_mask_base_T_12 = pmp_4_cfg_a[0]; // @[PMP.scala:24:19, :57:31] wire [30:0] _pmp_mask_base_T_13 = {pmp_4_addr, _pmp_mask_base_T_12}; // @[PMP.scala:24:19, :57:{19,31}] wire [30:0] pmp_mask_base_4 = _pmp_mask_base_T_13; // @[PMP.scala:57:{19,36}] wire [31:0] _pmp_mask_T_20 = {1'h0, pmp_mask_base_4} + 32'h1; // @[PMP.scala:57:36, :58:23] wire [30:0] _pmp_mask_T_21 = _pmp_mask_T_20[30:0]; // @[PMP.scala:58:23] wire [30:0] _pmp_mask_T_22 = ~_pmp_mask_T_21; // @[PMP.scala:58:{16,23}] wire [30:0] _pmp_mask_T_23 = pmp_mask_base_4 & _pmp_mask_T_22; // @[PMP.scala:57:36, :58:{14,16}] wire [32:0] _pmp_mask_T_24 = {_pmp_mask_T_23, 2'h3}; // @[PMP.scala:58:{8,14}] assign pmp_4_mask = _pmp_mask_T_24[31:0]; // @[PMP.scala:24:19, :27:14, :58:8] assign io_pmp_5_cfg_l_0 = pmp_5_cfg_l; // @[PMP.scala:24:19] assign io_pmp_5_cfg_a_0 = pmp_5_cfg_a; // @[PMP.scala:24:19] assign io_pmp_5_cfg_x_0 = pmp_5_cfg_x; // @[PMP.scala:24:19] assign io_pmp_5_cfg_w_0 = pmp_5_cfg_w; // @[PMP.scala:24:19] assign io_pmp_5_cfg_r_0 = pmp_5_cfg_r; // @[PMP.scala:24:19] assign io_pmp_5_addr_0 = pmp_5_addr; // @[PMP.scala:24:19] assign io_pmp_5_mask_0 = pmp_5_mask; // @[PMP.scala:24:19] wire _pmp_mask_base_T_15 = pmp_5_cfg_a[0]; // @[PMP.scala:24:19, :57:31] wire [30:0] _pmp_mask_base_T_16 = {pmp_5_addr, _pmp_mask_base_T_15}; // @[PMP.scala:24:19, :57:{19,31}] wire [30:0] pmp_mask_base_5 = _pmp_mask_base_T_16; // @[PMP.scala:57:{19,36}] wire [31:0] _pmp_mask_T_25 = {1'h0, pmp_mask_base_5} + 32'h1; // @[PMP.scala:57:36, :58:23] wire [30:0] _pmp_mask_T_26 = _pmp_mask_T_25[30:0]; // @[PMP.scala:58:23] wire [30:0] _pmp_mask_T_27 = ~_pmp_mask_T_26; // @[PMP.scala:58:{16,23}] wire [30:0] _pmp_mask_T_28 = pmp_mask_base_5 & _pmp_mask_T_27; // @[PMP.scala:57:36, :58:{14,16}] wire [32:0] _pmp_mask_T_29 = {_pmp_mask_T_28, 2'h3}; // @[PMP.scala:58:{8,14}] assign pmp_5_mask = _pmp_mask_T_29[31:0]; // @[PMP.scala:24:19, :27:14, :58:8] assign io_pmp_6_cfg_l_0 = pmp_6_cfg_l; // @[PMP.scala:24:19] assign io_pmp_6_cfg_a_0 = pmp_6_cfg_a; // @[PMP.scala:24:19] assign io_pmp_6_cfg_x_0 = pmp_6_cfg_x; // @[PMP.scala:24:19] assign io_pmp_6_cfg_w_0 = pmp_6_cfg_w; // @[PMP.scala:24:19] assign io_pmp_6_cfg_r_0 = pmp_6_cfg_r; // @[PMP.scala:24:19] assign io_pmp_6_addr_0 = pmp_6_addr; // @[PMP.scala:24:19] assign io_pmp_6_mask_0 = pmp_6_mask; // @[PMP.scala:24:19] wire _pmp_mask_base_T_18 = pmp_6_cfg_a[0]; // @[PMP.scala:24:19, :57:31] wire [30:0] _pmp_mask_base_T_19 = {pmp_6_addr, _pmp_mask_base_T_18}; // @[PMP.scala:24:19, :57:{19,31}] wire [30:0] pmp_mask_base_6 = _pmp_mask_base_T_19; // @[PMP.scala:57:{19,36}] wire [31:0] _pmp_mask_T_30 = {1'h0, pmp_mask_base_6} + 32'h1; // @[PMP.scala:57:36, :58:23] wire [30:0] _pmp_mask_T_31 = _pmp_mask_T_30[30:0]; // @[PMP.scala:58:23] wire [30:0] _pmp_mask_T_32 = ~_pmp_mask_T_31; // @[PMP.scala:58:{16,23}] wire [30:0] _pmp_mask_T_33 = pmp_mask_base_6 & _pmp_mask_T_32; // @[PMP.scala:57:36, :58:{14,16}] wire [32:0] _pmp_mask_T_34 = {_pmp_mask_T_33, 2'h3}; // @[PMP.scala:58:{8,14}] assign pmp_6_mask = _pmp_mask_T_34[31:0]; // @[PMP.scala:24:19, :27:14, :58:8] assign io_pmp_7_cfg_l_0 = pmp_7_cfg_l; // @[PMP.scala:24:19] assign io_pmp_7_cfg_a_0 = pmp_7_cfg_a; // @[PMP.scala:24:19] assign io_pmp_7_cfg_x_0 = pmp_7_cfg_x; // @[PMP.scala:24:19] assign io_pmp_7_cfg_w_0 = pmp_7_cfg_w; // @[PMP.scala:24:19] assign io_pmp_7_cfg_r_0 = pmp_7_cfg_r; // @[PMP.scala:24:19] assign io_pmp_7_addr_0 = pmp_7_addr; // @[PMP.scala:24:19] assign io_pmp_7_mask_0 = pmp_7_mask; // @[PMP.scala:24:19] wire _pmp_mask_base_T_21 = pmp_7_cfg_a[0]; // @[PMP.scala:24:19, :57:31] wire [30:0] _pmp_mask_base_T_22 = {pmp_7_addr, _pmp_mask_base_T_21}; // @[PMP.scala:24:19, :57:{19,31}] wire [30:0] pmp_mask_base_7 = _pmp_mask_base_T_22; // @[PMP.scala:57:{19,36}] wire [31:0] _pmp_mask_T_35 = {1'h0, pmp_mask_base_7} + 32'h1; // @[PMP.scala:57:36, :58:23] wire [30:0] _pmp_mask_T_36 = _pmp_mask_T_35[30:0]; // @[PMP.scala:58:23] wire [30:0] _pmp_mask_T_37 = ~_pmp_mask_T_36; // @[PMP.scala:58:{16,23}] wire [30:0] _pmp_mask_T_38 = pmp_mask_base_7 & _pmp_mask_T_37; // @[PMP.scala:57:36, :58:{14,16}] wire [32:0] _pmp_mask_T_39 = {_pmp_mask_T_38, 2'h3}; // @[PMP.scala:58:{8,14}] assign pmp_7_mask = _pmp_mask_T_39[31:0]; // @[PMP.scala:24:19, :27:14, :58:8] wire [1:0] read_mstatus_lo_lo_lo_lo = {io_status_sie_0, 1'h0}; // @[CSR.scala:377:7, :649:32] wire [1:0] read_mstatus_lo_lo_lo_hi = {io_status_mie_0, 1'h0}; // @[CSR.scala:377:7, :649:32] wire [3:0] read_mstatus_lo_lo_lo = {read_mstatus_lo_lo_lo_hi, read_mstatus_lo_lo_lo_lo}; // @[CSR.scala:649:32] wire [1:0] read_mstatus_lo_lo_hi_lo = {io_status_spie_0, 1'h0}; // @[CSR.scala:377:7, :649:32] wire [1:0] read_mstatus_lo_lo_hi_hi_hi = {io_status_spp_0, io_status_mpie_0}; // @[CSR.scala:377:7, :649:32] wire [2:0] read_mstatus_lo_lo_hi_hi = {read_mstatus_lo_lo_hi_hi_hi, 1'h0}; // @[CSR.scala:649:32] wire [4:0] read_mstatus_lo_lo_hi = {read_mstatus_lo_lo_hi_hi, read_mstatus_lo_lo_hi_lo}; // @[CSR.scala:649:32] wire [8:0] read_mstatus_lo_lo = {read_mstatus_lo_lo_hi, read_mstatus_lo_lo_lo}; // @[CSR.scala:649:32] wire [3:0] read_mstatus_lo_hi_lo_lo = {io_status_mpp_0, 2'h0}; // @[CSR.scala:377:7, :649:32] wire [3:0] read_mstatus_lo_hi_lo_hi = {2'h0, io_status_fs_0}; // @[CSR.scala:377:7, :649:32] wire [7:0] read_mstatus_lo_hi_lo = {read_mstatus_lo_hi_lo_hi, read_mstatus_lo_hi_lo_lo}; // @[CSR.scala:649:32] wire [1:0] read_mstatus_lo_hi_hi_lo = {io_status_sum_0, io_status_mprv_0}; // @[CSR.scala:377:7, :649:32] wire [1:0] read_mstatus_lo_hi_hi_hi_hi = {io_status_tw_0, io_status_tvm_0}; // @[CSR.scala:377:7, :649:32] wire [2:0] read_mstatus_lo_hi_hi_hi = {read_mstatus_lo_hi_hi_hi_hi, io_status_mxr_0}; // @[CSR.scala:377:7, :649:32] wire [4:0] read_mstatus_lo_hi_hi = {read_mstatus_lo_hi_hi_hi, read_mstatus_lo_hi_hi_lo}; // @[CSR.scala:649:32] wire [12:0] read_mstatus_lo_hi = {read_mstatus_lo_hi_hi, read_mstatus_lo_hi_lo}; // @[CSR.scala:649:32] wire [21:0] read_mstatus_lo = {read_mstatus_lo_hi, read_mstatus_lo_lo}; // @[CSR.scala:649:32] wire [8:0] read_mstatus_hi_lo_lo_lo = {8'h0, io_status_tsr_0}; // @[CSR.scala:377:7, :649:32] wire [11:0] read_mstatus_hi_lo_lo = {3'h4, read_mstatus_hi_lo_lo_lo}; // @[CSR.scala:649:32] wire [1:0] read_mstatus_hi_lo_hi_hi_hi = {io_status_mpv_0, io_status_gva_0}; // @[CSR.scala:377:7, :649:32] wire [2:0] read_mstatus_hi_lo_hi_hi = {read_mstatus_hi_lo_hi_hi_hi, 1'h0}; // @[CSR.scala:649:32] wire [5:0] read_mstatus_hi_lo_hi = {read_mstatus_hi_lo_hi_hi, 3'h2}; // @[CSR.scala:649:32] wire [17:0] read_mstatus_hi_lo = {read_mstatus_hi_lo_hi, read_mstatus_hi_lo_lo}; // @[CSR.scala:649:32] wire [23:0] read_mstatus_hi_hi_lo_lo = {io_status_sd_0, 23'h0}; // @[CSR.scala:377:7, :649:32] wire [2:0] read_mstatus_hi_hi_lo_hi_hi = {io_status_dv_0, io_status_prv_0}; // @[CSR.scala:377:7, :649:32] wire [3:0] read_mstatus_hi_hi_lo_hi = {read_mstatus_hi_hi_lo_hi_hi, io_status_v_0}; // @[CSR.scala:377:7, :649:32] wire [27:0] read_mstatus_hi_hi_lo = {read_mstatus_hi_hi_lo_hi, read_mstatus_hi_hi_lo_lo}; // @[CSR.scala:649:32] wire [33:0] read_mstatus_hi_hi_hi_lo = {32'h14112D, io_status_dprv_0}; // @[CSR.scala:377:7, :649:32] wire [1:0] read_mstatus_hi_hi_hi_hi_hi = {io_status_debug_0, io_status_cease_0}; // @[CSR.scala:377:7, :649:32] wire [2:0] read_mstatus_hi_hi_hi_hi = {read_mstatus_hi_hi_hi_hi_hi, io_status_wfi_0}; // @[CSR.scala:377:7, :649:32] wire [36:0] read_mstatus_hi_hi_hi = {read_mstatus_hi_hi_hi_hi, read_mstatus_hi_hi_hi_lo}; // @[CSR.scala:649:32] wire [64:0] read_mstatus_hi_hi = {read_mstatus_hi_hi_hi, read_mstatus_hi_hi_lo}; // @[CSR.scala:649:32] wire [82:0] read_mstatus_hi = {read_mstatus_hi_hi, read_mstatus_hi_lo}; // @[CSR.scala:649:32] wire [104:0] _read_mstatus_T = {read_mstatus_hi, read_mstatus_lo}; // @[CSR.scala:649:32] wire [63:0] read_mstatus = _read_mstatus_T[63:0]; // @[package.scala:163:13] wire _read_mtvec_T = reg_mtvec[0]; // @[CSR.scala:512:31, :1666:41] wire [7:0] _read_mtvec_T_1 = _read_mtvec_T ? 8'hFE : 8'h2; // @[CSR.scala:1666:{39,41}] wire [31:0] _read_mtvec_T_3 = {24'h0, _read_mtvec_T_1}; // @[package.scala:174:41] wire [31:0] _read_mtvec_T_4 = ~_read_mtvec_T_3; // @[package.scala:174:{37,41}] wire [31:0] _read_mtvec_T_5 = reg_mtvec & _read_mtvec_T_4; // @[package.scala:174:{35,37}] wire [63:0] read_mtvec = {32'h0, _read_mtvec_T_5}; // @[package.scala:138:15, :174:35] wire _read_stvec_T = reg_stvec[0]; // @[CSR.scala:573:22, :1666:41] wire [7:0] _read_stvec_T_1 = _read_stvec_T ? 8'hFE : 8'h2; // @[CSR.scala:1666:{39,41}] wire [38:0] _read_stvec_T_3 = {31'h0, _read_stvec_T_1}; // @[package.scala:174:41] wire [38:0] _read_stvec_T_4 = ~_read_stvec_T_3; // @[package.scala:174:{37,41}] wire [38:0] _read_stvec_T_5 = reg_stvec & _read_stvec_T_4; // @[package.scala:174:{35,37}] wire _read_stvec_T_6 = _read_stvec_T_5[38]; // @[package.scala:132:38, :174:35] wire [24:0] _read_stvec_T_7 = {25{_read_stvec_T_6}}; // @[package.scala:132:{20,38}] wire [63:0] read_stvec = {_read_stvec_T_7, _read_stvec_T_5}; // @[package.scala:132:{15,20}, :174:35] wire [39:0] _read_mapping_T_2 = ~reg_mepc; // @[CSR.scala:505:21, :1665:28] wire [39:0] _read_mapping_T_5 = {_read_mapping_T_2[39:2], _read_mapping_T_2[1:0] \| 2'h1}; // @[CSR.scala:1665:{28,31}] wire [39:0] _read_mapping_T_6 = ~_read_mapping_T_5; // @[CSR.scala:1665:{26,31}] wire _read_mapping_T_7 = _read_mapping_T_6[39]; // @[package.scala:132:38] wire [23:0] _read_mapping_T_8 = {24{_read_mapping_T_7}}; // @[package.scala:132:{20,38}] wire [63:0] read_mapping_10_2 = {_read_mapping_T_8, _read_mapping_T_6}; // @[package.scala:132:{15,20}] wire _read_mapping_T_9 = reg_mtval[39]; // @[package.scala:132:38] wire [23:0] _read_mapping_T_10 = {24{_read_mapping_T_9}}; // @[package.scala:132:{20,38}] wire [63:0] read_mapping_11_2 = {_read_mapping_T_10, reg_mtval}; // @[package.scala:132:{15,20}] wire [2:0] debug_csrs_lo_lo_hi = {2'h0, reg_dcsr_step}; // @[CSR.scala:403:25, :670:27] wire [4:0] debug_csrs_lo_lo = {debug_csrs_lo_lo_hi, reg_dcsr_prv}; // @[CSR.scala:403:25, :670:27] wire [3:0] debug_csrs_lo_hi_lo = {reg_dcsr_cause, reg_dcsr_v}; // @[CSR.scala:403:25, :670:27] wire [5:0] debug_csrs_lo_hi = {2'h0, debug_csrs_lo_hi_lo}; // @[CSR.scala:670:27] wire [10:0] debug_csrs_lo = {debug_csrs_lo_hi, debug_csrs_lo_lo}; // @[CSR.scala:670:27] wire [1:0] debug_csrs_hi_lo_lo = {reg_dcsr_ebreaku, 1'h0}; // @[CSR.scala:403:25, :670:27] wire [1:0] debug_csrs_hi_lo_hi = {1'h0, reg_dcsr_ebreaks}; // @[CSR.scala:403:25, :670:27] wire [3:0] debug_csrs_hi_lo = {debug_csrs_hi_lo_hi, debug_csrs_hi_lo_lo}; // @[CSR.scala:670:27] wire [12:0] debug_csrs_hi_hi_lo = {12'h0, reg_dcsr_ebreakm}; // @[CSR.scala:403:25, :670:27] wire [16:0] debug_csrs_hi_hi = {4'h4, debug_csrs_hi_hi_lo}; // @[CSR.scala:670:27] wire [20:0] debug_csrs_hi = {debug_csrs_hi_hi, debug_csrs_hi_lo}; // @[CSR.scala:670:27] wire [31:0] debug_csrs_0_2 = {debug_csrs_hi, debug_csrs_lo}; // @[CSR.scala:670:27] wire [39:0] _debug_csrs_T = ~reg_dpc; // @[CSR.scala:483:20, :1665:28] wire [39:0] _debug_csrs_T_3 = {_debug_csrs_T[39:2], _debug_csrs_T[1:0] \| 2'h1}; // @[CSR.scala:1665:{28,31}] wire [39:0] _debug_csrs_T_4 = ~_debug_csrs_T_3; // @[CSR.scala:1665:{26,31}] wire _debug_csrs_T_5 = _debug_csrs_T_4[39]; // @[package.scala:132:38] wire [23:0] _debug_csrs_T_6 = {24{_debug_csrs_T_5}}; // @[package.scala:132:{20,38}] wire [63:0] debug_csrs_1_2 = {_debug_csrs_T_6, _debug_csrs_T_4}; // @[package.scala:132:{15,20}] wire [7:0] read_fcsr = {reg_frm, reg_fflags}; // @[CSR.scala:577:23, :578:20, :689:22] wire [3:0] lo_lo_4 = {3'h0, reg_menvcfg_fiom}; // @[CSR.scala:525:28, :742:49] wire [6:0] lo_4 = {3'h0, lo_lo_4}; // @[CSR.scala:742:49] wire [63:0] sie_mask = {48'h0, read_mideleg[15:0] & 16'hEFFF}; // @[CSR.scala:498:14, :750:18] wire [63:0] read_sie = reg_mie & sie_mask; // @[CSR.scala:495:20, :750:18, :753:28] wire [63:0] read_sip = {48'h0, sie_mask[15:0] & read_mip}; // @[CSR.scala:610:29, :750:18, :754:29] wire [1:0] lo_lo_lo_lo = {read_sstatus_sie, 1'h0}; // @[CSR.scala:755:35, :768:51] wire [3:0] lo_lo_lo_4 = {2'h0, lo_lo_lo_lo}; // @[CSR.scala:768:51] wire [1:0] lo_lo_hi_lo = {read_sstatus_spie, 1'h0}; // @[CSR.scala:755:35, :768:51] wire [1:0] lo_lo_hi_hi_hi = {read_sstatus_spp, 1'h0}; // @[CSR.scala:755:35, :768:51] wire [2:0] lo_lo_hi_hi = {lo_lo_hi_hi_hi, 1'h0}; // @[CSR.scala:768:51] wire [4:0] lo_lo_hi_4 = {lo_lo_hi_hi, lo_lo_hi_lo}; // @[CSR.scala:768:51] wire [8:0] lo_lo_5 = {lo_lo_hi_4, lo_lo_lo_4}; // @[CSR.scala:768:51] wire [3:0] lo_hi_lo_hi = {2'h0, read_sstatus_fs}; // @[CSR.scala:755:35, :768:51] wire [7:0] lo_hi_lo_4 = {lo_hi_lo_hi, 4'h0}; // @[CSR.scala:768:51] wire [1:0] lo_hi_hi_lo = {read_sstatus_sum, 1'h0}; // @[CSR.scala:755:35, :768:51] wire [2:0] lo_hi_hi_hi = {2'h0, read_sstatus_mxr}; // @[CSR.scala:755:35, :768:51] wire [4:0] lo_hi_hi_4 = {lo_hi_hi_hi, lo_hi_hi_lo}; // @[CSR.scala:768:51] wire [12:0] lo_hi_5 = {lo_hi_hi_4, lo_hi_lo_4}; // @[CSR.scala:768:51] wire [21:0] lo_5 = {lo_hi_5, lo_lo_5}; // @[CSR.scala:768:51] wire [23:0] hi_hi_lo_lo = {read_sstatus_sd, 23'h0}; // @[CSR.scala:755:35, :768:51] wire [27:0] hi_hi_lo_4 = {4'h0, hi_hi_lo_lo}; // @[CSR.scala:768:51] wire [64:0] hi_hi_5 = {37'h0, hi_hi_lo_4}; // @[CSR.scala:768:51] wire [82:0] hi_7 = {hi_hi_5, 18'h800}; // @[CSR.scala:768:51] wire [19:0] hi_8 = {reg_satp_mode, 16'h0}; // @[CSR.scala:574:21, :774:43] wire [39:0] _io_evec_T = ~reg_sepc; // @[CSR.scala:569:21, :1665:28] wire [39:0] _T_34 = ~{_io_evec_T[39:2], _io_evec_T[1:0] \| 2'h1}; // @[CSR.scala:1665:{26,28,31}] wire [3:0] lo_lo_6 = {3'h0, reg_senvcfg_fiom}; // @[CSR.scala:526:28, :780:49] wire [6:0] lo_6 = {3'h0, lo_lo_6}; // @[CSR.scala:780:49] wire [1:0] lo_hi_7 = {reg_pmp_0_cfg_x, reg_pmp_0_cfg_w}; // @[package.scala:45:36] wire [2:0] lo_7 = {lo_hi_7, reg_pmp_0_cfg_r}; // @[package.scala:45:36] wire [2:0] hi_hi_7 = {reg_pmp_0_cfg_l, 2'h0}; // @[package.scala:45:36] wire [4:0] hi_10 = {hi_hi_7, reg_pmp_0_cfg_a}; // @[package.scala:45:36] wire [1:0] lo_hi_8 = {reg_pmp_1_cfg_x, reg_pmp_1_cfg_w}; // @[package.scala:45:36] wire [2:0] lo_8 = {lo_hi_8, reg_pmp_1_cfg_r}; // @[package.scala:45:36] wire [2:0] hi_hi_8 = {reg_pmp_1_cfg_l, 2'h0}; // @[package.scala:45:36] wire [4:0] hi_11 = {hi_hi_8, reg_pmp_1_cfg_a}; // @[package.scala:45:36] wire [1:0] lo_hi_9 = {reg_pmp_2_cfg_x, reg_pmp_2_cfg_w}; // @[package.scala:45:36] wire [2:0] lo_9 = {lo_hi_9, reg_pmp_2_cfg_r}; // @[package.scala:45:36] wire [2:0] hi_hi_9 = {reg_pmp_2_cfg_l, 2'h0}; // @[package.scala:45:36] wire [4:0] hi_12 = {hi_hi_9, reg_pmp_2_cfg_a}; // @[package.scala:45:36] wire [1:0] lo_hi_10 = {reg_pmp_3_cfg_x, reg_pmp_3_cfg_w}; // @[package.scala:45:36] wire [2:0] lo_10 = {lo_hi_10, reg_pmp_3_cfg_r}; // @[package.scala:45:36] wire [2:0] hi_hi_10 = {reg_pmp_3_cfg_l, 2'h0}; // @[package.scala:45:36] wire [4:0] hi_13 = {hi_hi_10, reg_pmp_3_cfg_a}; // @[package.scala:45:36] wire [1:0] lo_hi_11 = {reg_pmp_4_cfg_x, reg_pmp_4_cfg_w}; // @[package.scala:45:36] wire [2:0] lo_11 = {lo_hi_11, reg_pmp_4_cfg_r}; // @[package.scala:45:36] wire [2:0] hi_hi_11 = {reg_pmp_4_cfg_l, 2'h0}; // @[package.scala:45:36] wire [4:0] hi_14 = {hi_hi_11, reg_pmp_4_cfg_a}; // @[package.scala:45:36] wire [1:0] lo_hi_12 = {reg_pmp_5_cfg_x, reg_pmp_5_cfg_w}; // @[package.scala:45:36] wire [2:0] lo_12 = {lo_hi_12, reg_pmp_5_cfg_r}; // @[package.scala:45:36] wire [2:0] hi_hi_12 = {reg_pmp_5_cfg_l, 2'h0}; // @[package.scala:45:36] wire [4:0] hi_15 = {hi_hi_12, reg_pmp_5_cfg_a}; // @[package.scala:45:36] wire [1:0] lo_hi_13 = {reg_pmp_6_cfg_x, reg_pmp_6_cfg_w}; // @[package.scala:45:36] wire [2:0] lo_13 = {lo_hi_13, reg_pmp_6_cfg_r}; // @[package.scala:45:36] wire [2:0] hi_hi_13 = {reg_pmp_6_cfg_l, 2'h0}; // @[package.scala:45:36] wire [4:0] hi_16 = {hi_hi_13, reg_pmp_6_cfg_a}; // @[package.scala:45:36] wire [1:0] lo_hi_14 = {reg_pmp_7_cfg_x, reg_pmp_7_cfg_w}; // @[package.scala:45:36] wire [2:0] lo_14 = {lo_hi_14, reg_pmp_7_cfg_r}; // @[package.scala:45:36] wire [2:0] hi_hi_14 = {reg_pmp_7_cfg_l, 2'h0}; // @[package.scala:45:36] wire [4:0] hi_17 = {hi_hi_14, reg_pmp_7_cfg_a}; // @[package.scala:45:36] wire [15:0] lo_lo_7 = {hi_11, lo_8, hi_10, lo_7}; // @[package.scala:45:{27,36}] wire [15:0] lo_hi_15 = {hi_13, lo_10, hi_12, lo_9}; // @[package.scala:45:{27,36}] wire [31:0] lo_15 = {lo_hi_15, lo_lo_7}; // @[package.scala:45:27] wire [15:0] hi_lo_7 = {hi_15, lo_12, hi_14, lo_11}; // @[package.scala:45:{27,36}] wire [15:0] hi_hi_15 = {hi_17, lo_14, hi_16, lo_13}; // @[package.scala:45:{27,36}] wire [31:0] hi_18 = {hi_hi_15, hi_lo_7}; // @[package.scala:45:27] reg [63:0] reg_custom_0; // @[CSR.scala:798:43] assign io_customCSRs_0_value_0 = reg_custom_0; // @[CSR.scala:377:7, :798:43] wire _reg_custom_read_T = \|io_rw_cmd_0; // @[CSR.scala:377:7, :799:26] wire _reg_custom_read_T_1 = io_rw_addr_0 == 12'h7C1; // @[CSR.scala:377:7, :799:50] assign reg_custom_read = _reg_custom_read_T & _reg_custom_read_T_1; // @[CSR.scala:799:{26,36,50}] assign io_customCSRs_0_ren_0 = reg_custom_read; // @[CSR.scala:377:7, :799:36] reg [63:0] reg_custom_1; // @[CSR.scala:798:43] assign io_customCSRs_1_value_0 = reg_custom_1; // @[CSR.scala:377:7, :798:43] wire [63:0] _reg_custom_1_T_2 = reg_custom_1; // @[CSR.scala:798:43, :1506:38] wire [63:0] _reg_custom_1_T_6 = reg_custom_1; // @[CSR.scala:798:43, :1531:39] wire _reg_custom_read_T_2 = \|io_rw_cmd_0; // @[CSR.scala:377:7, :799:26] wire _reg_custom_read_T_3 = io_rw_addr_0 == 12'hF12; // @[CSR.scala:377:7, :799:50] assign reg_custom_read_1 = _reg_custom_read_T_2 & _reg_custom_read_T_3; // @[CSR.scala:799:{26,36,50}] assign io_customCSRs_1_ren_0 = reg_custom_read_1; // @[CSR.scala:377:7, :799:36] wire [12:0] decoded_addr_addr = {io_status_v_0, io_rw_addr_0}; // @[CSR.scala:377:7, :851:19] wire [11:0] decoded_addr_decoded_decoded_plaInput; // @[pla.scala:77:22] wire [11:0] decoded_addr_decoded_decoded_invInputs = ~decoded_addr_decoded_decoded_plaInput; // @[pla.scala:77:22, :78:21] wire [149:0] decoded_addr_decoded_decoded_invMatrixOutputs; // @[pla.scala:120:37] wire [149:0] decoded_addr_decoded_decoded; // @[pla.scala:81:23] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_4 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_5 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_8 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_9 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_14 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_15 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_18 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_19 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_22 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_24 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_25 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_28 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_29 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_32 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_33 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_36 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_37 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_40 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_41 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_44 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_45 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_48 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_49 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_52 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_53 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_57 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_59 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_60 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_63 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_64 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_67 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_68 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_71 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_72 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_75 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_76 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_79 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_80 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_83 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_86 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_87 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_90 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_91 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_94 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_95 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_98 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_99 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_102 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_103 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_106 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_107 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_110 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_111 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_114 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_117 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_118 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_121 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_122 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_125 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_126 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_129 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_130 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_133 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_134 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_137 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_138 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_141 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_142 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_145 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_148 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_149 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_1 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_2 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_3 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_8 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_9 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_10 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_11 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_14 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_15 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_16 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_17 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_22 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_23 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_28 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_29 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_30 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_31 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_36 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_37 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_38 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_39 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_44 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_45 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_46 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_47 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_52 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_53 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_54 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_55 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_57 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_58 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_59 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_60 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_61 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_62 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_67 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_68 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_69 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_70 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_75 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_76 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_77 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_78 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_79 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_80 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_81 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_83 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_84 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_85 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_90 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_91 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_92 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_93 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_98 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_99 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_100 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_101 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_106 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_107 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_108 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_109 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_114 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_115 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_116 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_121 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_122 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_123 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_124 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_129 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_130 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_131 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_132 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_137 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_138 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_139 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_140 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_145 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_146 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_147 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_1 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_2 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_3 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_4 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_5 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_6 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_8 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_9 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_10 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_11 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_12 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_14 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_15 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_16 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_17 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_18 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_19 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_20 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_22 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_23 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_24 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_25 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_26 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_27 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_36 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_37 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_38 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_39 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_40 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_41 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_42 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_43 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_52 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_53 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_54 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_55 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_56 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_57 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_58 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_59 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_60 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_61 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_62 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_63 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_64 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_65 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_66 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_75 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_76 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_77 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_78 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_79 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_80 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_81 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_83 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_84 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_85 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_86 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_87 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_88 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_89 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_98 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_99 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_100 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_101 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_102 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_103 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_104 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_105 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_114 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_115 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_116 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_117 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_118 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_119 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_120 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_129 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_130 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_131 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_132 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_133 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_134 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_135 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_136 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_145 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_146 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_147 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_148 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_149 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_1 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_2 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_3 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_4 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_5 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_6 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_7 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_8 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_9 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_10 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_11 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_12 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_14 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_15 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_16 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_17 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_18 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_19 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_20 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_21 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_22 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_23 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_24 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_25 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_26 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_27 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_28 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_29 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_30 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_31 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_32 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_33 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_34 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_35 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_52 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_53 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_54 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_55 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_56 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_57 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_58 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_75 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_76 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_77 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_78 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_83 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_84 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_85 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_86 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_87 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_88 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_89 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_90 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_91 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_92 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_93 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_94 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_95 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_96 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_97 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_114 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_115 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_116 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_117 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_118 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_119 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_120 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_121 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_122 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_123 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_124 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_125 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_126 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_127 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_128 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_1 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_2 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_3 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_4 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_5 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_6 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_7 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_8 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_9 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_10 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_11 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_12 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_13 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_14 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_15 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_16 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_17 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_18 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_20 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_21 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_51 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_52 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_53 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_54 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_56 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_83 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_83 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_84 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_85 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_86 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_87 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_88 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_89 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_90 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_91 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_92 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_93 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_94 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_95 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_96 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_97 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_98 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_99 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_100 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_101 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_102 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_103 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_104 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_105 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_106 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_107 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_108 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_109 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_110 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_111 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_112 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_114 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_114 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_115 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_116 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_117 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_118 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_119 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_120 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_121 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_122 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_123 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_124 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_125 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_126 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_127 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_128 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_129 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_130 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_131 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_132 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_133 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_134 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_135 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_136 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_137 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_138 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_139 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_140 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_141 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_142 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_143 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_145 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_145 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_146 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_147 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_148 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_1 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_2 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_3 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_4 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_5 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_6 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_7 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_13 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_14 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_15 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_16 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_17 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_18 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_19 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_21 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_21 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_22 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_23 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_24 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_25 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_26 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_27 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_28 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_29 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_30 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_31 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_32 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_33 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_34 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_35 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_36 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_37 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_38 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_39 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_40 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_41 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_42 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_43 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_44 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_45 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_46 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_47 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_48 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_49 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_50 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_56 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_57 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_58 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_59 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_60 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_61 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_62 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_63 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_64 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_65 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_66 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_67 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_68 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_69 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_70 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_71 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_72 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_73 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_74 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_75 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_76 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_77 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_78 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_79 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_80 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_82 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_82 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_83 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_84 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_85 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_86 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_87 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_88 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_89 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_90 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_91 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_92 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_93 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_94 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_95 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_96 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_97 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_98 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_99 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_100 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_101 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_102 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_103 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_104 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_105 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_106 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_107 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_108 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_109 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_110 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_111 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_113 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_113 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_114 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_115 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_116 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_117 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_118 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_119 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_120 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_121 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_122 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_123 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_124 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_125 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_126 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_127 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_128 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_129 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_130 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_131 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_132 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_133 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_134 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_135 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_136 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_137 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_138 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_139 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_140 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_141 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_142 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_144 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_144 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_145 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_146 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_147 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_1 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_2 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_3 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_4 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_5 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_6 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_7 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_8 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_9 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_10 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_11 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_12 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_13 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_14 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_15 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_16 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_17 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_18 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_19 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_21 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_21 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_22 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_23 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_24 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_25 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_26 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_27 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_28 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_29 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_30 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_31 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_32 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_33 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_34 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_35 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_36 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_37 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_38 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_39 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_40 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_41 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_42 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_43 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_44 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_45 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_46 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_47 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_48 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_49 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_50 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_51 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_52 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_53 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_54 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_55 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_81 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_82 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_83 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_84 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_85 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_86 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_87 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_88 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_89 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_90 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_91 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_92 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_93 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_94 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_95 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_96 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_97 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_98 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_99 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_100 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_101 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_102 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_103 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_104 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_105 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_106 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_107 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_108 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_109 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_110 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_111 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_112 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_113 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_114 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_115 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_116 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_117 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_118 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_119 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_120 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_121 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_122 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_123 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_124 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_125 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_126 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_127 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_128 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_129 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_130 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_131 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_132 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_133 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_134 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_135 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_136 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_137 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_138 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_139 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_140 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_141 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_142 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_143 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_144 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_145 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_146 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_147 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_1 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_2 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_112 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_113 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_114 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_115 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_116 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_117 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_118 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_119 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_120 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_121 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_122 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_123 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_124 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_125 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_126 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_127 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_128 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_129 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_130 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_131 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_132 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_133 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_134 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_135 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_136 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_137 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_138 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_139 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_140 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_141 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_142 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_1 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_2 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_3 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_4 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_5 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_6 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_7 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_7 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_8 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_9 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_10 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_12 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_13 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_112 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_111 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_112 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_113 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_114 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_115 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_116 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_117 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_118 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_119 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_120 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_121 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_122 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_123 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_124 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_125 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_126 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_127 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_128 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_129 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_130 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_131 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_132 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_133 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_134 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_135 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_136 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_137 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_138 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_139 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_140 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_1 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_2 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_3 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_3 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_4 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_6 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_7 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_6 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_7 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_8 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_9 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_12 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_13 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_10 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_11 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_12 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_13 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_14 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_15 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_18 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_20 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_19 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_20 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_19 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_20 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_21 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_22 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_23 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_24 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_25 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_26 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_27 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_28 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_29 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_30 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_31 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_32 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_33 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_34 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_35 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_36 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_37 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_38 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_39 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_40 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_41 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_42 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_43 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_44 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_45 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_46 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_47 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_48 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_49 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_50 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_55 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_54 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_55 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_53 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_54 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_55 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_56 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_57 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_58 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_59 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_60 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_61 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_62 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_63 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_64 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_65 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_66 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_67 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_68 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_79 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_77 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_78 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_79 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_80 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_81 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_82 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_83 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_84 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_85 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_86 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_87 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_88 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_89 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_90 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_91 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_92 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_93 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_94 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_95 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_96 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_97 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_98 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_99 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_100 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_101 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_102 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_103 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_104 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_105 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_106 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_1 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_3 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_2 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_3 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_5 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_7 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_4 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_5 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_6 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_7 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_11 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_13 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_8 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_9 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_10 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_11 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_12 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_13 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_16 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_20 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_17 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_18 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_14 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_15 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_16 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_17 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_18 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_19 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_20 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_21 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_22 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_23 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_24 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_25 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_26 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_27 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_28 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_29 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_30 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_31 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_32 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_33 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_34 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_35 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_36 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_37 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_38 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_39 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_40 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_41 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_42 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_43 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_44 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_45 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_53 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_51 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_52 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_46 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_47 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_48 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_49 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_50 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_51 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_52 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_53 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_54 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_55 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_56 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_57 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_58 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_59 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_60 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_61 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_62 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_63 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_64 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_65 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_66 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_67 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_75 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_81 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8}; // @[pla.scala:91:29, :98:53] wire [4:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo}; // @[pla.scala:98:53] wire [10:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T = {decoded_addr_decoded_decoded_andMatrixOutputs_hi, decoded_addr_decoded_decoded_andMatrixOutputs_lo}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_138_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_132 = decoded_addr_decoded_decoded_andMatrixOutputs_138_2; // @[pla.scala:98:70, :114:36] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_1 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_4 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_8 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_10 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_14 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_16 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_18 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_24 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_26 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_28 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_30 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_32 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_34 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_36 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_38 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_40 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_42 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_44 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_46 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_48 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_50 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_52 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_54 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_59 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_61 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_63 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_65 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_67 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_69 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_71 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_73 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_75 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_77 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_79 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_84 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_86 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_88 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_90 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_92 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_94 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_96 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_98 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_100 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_102 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_104 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_106 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_108 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_110 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_112 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_115 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_117 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_119 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_121 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_123 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_125 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_127 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_129 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_131 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_133 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_135 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_137 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_139 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_141 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_143 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_146 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_148 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_1 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_2 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_6 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_10 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_11 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_16 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_17 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_20 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_23 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_26 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_27 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_30 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_31 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_34 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_35 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_38 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_39 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_42 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_43 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_46 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_47 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_50 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_51 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_54 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_55 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_58 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_61 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_62 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_65 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_66 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_69 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_70 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_73 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_74 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_77 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_78 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_81 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_84 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_85 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_88 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_89 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_92 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_93 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_96 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_97 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_100 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_101 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_104 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_105 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_108 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_109 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_112 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_113 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_115 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_116 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_119 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_120 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_123 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_124 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_127 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_128 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_131 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_132 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_135 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_136 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_139 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_140 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_143 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_144 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_146 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_147 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_1, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_1}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_1 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_1 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_1, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_1}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_1 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_1, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_1}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_1 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_1, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_1}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_1 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_1, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_1}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_1 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_1, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_1}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_1 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_1, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_1}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_1 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_1, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_1}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_1 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_1, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_1}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_1 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_1, decoded_addr_decoded_decoded_andMatrixOutputs_lo_1}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_134_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_1; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_131 = decoded_addr_decoded_decoded_andMatrixOutputs_134_2; // @[pla.scala:98:70, :114:36] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_2 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_5 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_9 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_11 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_15 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_17 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_19 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_25 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_27 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_29 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_31 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_33 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_35 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_37 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_39 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_41 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_43 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_45 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_47 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_49 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_51 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_53 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_55 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_60 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_62 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_64 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_66 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_68 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_70 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_72 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_74 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_76 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_78 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_80 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_85 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_87 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_89 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_91 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_93 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_95 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_97 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_99 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_101 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_103 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_105 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_107 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_109 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_111 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_113 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_116 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_118 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_120 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_122 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_124 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_126 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_128 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_130 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_132 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_134 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_136 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_138 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_140 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_142 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_144 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_147 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_149 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_1 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_2, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_2}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_2 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_1, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_1}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_2 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_2, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_2}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_2 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_2, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_2}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_2 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_2, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_2}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_2 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_2, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_2}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_2 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_2, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_2}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_2 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_2, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_2}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_2 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_2, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_2}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_2 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_2, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_2}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_2 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_2, decoded_addr_decoded_decoded_andMatrixOutputs_lo_2}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_41_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_2; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_130 = decoded_addr_decoded_decoded_andMatrixOutputs_41_2; // @[pla.scala:98:70, :114:36] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_3 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_4 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_5 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_6 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_7 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_8 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_9 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_10 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_11 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_12 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_13 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_13 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_14 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_15 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_16 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_17 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_18 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_19 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_20 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_21 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_22 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_23 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_24 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_25 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_26 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_27 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_28 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_29 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_30 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_31 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_32 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_33 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_34 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_35 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_36 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_37 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_38 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_39 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_40 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_41 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_42 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_43 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_44 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_45 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_46 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_47 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_48 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_49 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_50 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_51 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_52 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_53 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_54 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_55 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_56 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_57 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_58 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_59 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_60 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_61 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_62 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_63 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_64 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_65 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_66 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_67 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_68 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_69 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_70 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_71 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_72 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_73 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_74 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_75 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_76 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_77 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_78 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_79 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_80 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_82 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_81 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_82 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_83 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_84 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_85 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_86 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_87 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_88 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_89 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_90 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_91 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_92 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_93 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_94 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_95 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_96 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_97 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_98 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_99 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_100 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_101 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_102 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_103 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_104 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_105 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_106 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_107 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_108 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_109 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_110 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_111 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_143 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_144 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_145 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_146 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_147 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_3 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_3, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_3}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_3 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_3, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_3}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_3 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_3, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_3}; // @[pla.scala:91:29, :98:53] wire [4:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_3 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_3, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_3}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_3 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_3, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_3}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_3 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_3, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_3}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_3 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_3, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_3}; // @[pla.scala:91:29, :98:53] wire [4:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_3 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_3, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_3}; // @[pla.scala:98:53] wire [9:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_3 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_3, decoded_addr_decoded_decoded_andMatrixOutputs_lo_3}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_1_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_3; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_35 = decoded_addr_decoded_decoded_andMatrixOutputs_1_2; // @[pla.scala:98:70, :114:36] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_4 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_5 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_6 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_12 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_18 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_19 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_20 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_24 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_25 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_26 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_27 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_32 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_33 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_34 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_35 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_40 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_41 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_42 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_43 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_48 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_49 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_50 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_51 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_56 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_63 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_64 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_65 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_66 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_71 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_72 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_73 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_74 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_86 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_87 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_88 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_89 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_94 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_95 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_96 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_97 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_102 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_103 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_104 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_105 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_110 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_111 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_112 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_113 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_117 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_118 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_119 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_120 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_125 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_126 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_127 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_128 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_133 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_134 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_135 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_136 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_141 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_142 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_143 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_144 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_148 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_149 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_2 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_4, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_3}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_4 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_2, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_2}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_4 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_4, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_4}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_4 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_4, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_4}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_4 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_4, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_4}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_3 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_4, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_4}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_4 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_3, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_4}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_4 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_4, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_4}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_4 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_4, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_4}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_4 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_4, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_4}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_4 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_4, decoded_addr_decoded_decoded_andMatrixOutputs_lo_4}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_89_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_4; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_33 = decoded_addr_decoded_decoded_andMatrixOutputs_89_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_3 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_5, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_4}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_5 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_3, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_3}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_5 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_5, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_5}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_5 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_5, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_5}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_5 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_5, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_5}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_4 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_5, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_5}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_5 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_4, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_5}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_5 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_5, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_5}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_5 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_5, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_5}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_5 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_5, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_5}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_5 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_5, decoded_addr_decoded_decoded_andMatrixOutputs_lo_5}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_123_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_5; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_27 = decoded_addr_decoded_decoded_andMatrixOutputs_123_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_6 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_6, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_5}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_6 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_6, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_6}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_6 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_6, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_6}; // @[pla.scala:91:29, :98:53] wire [4:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_6 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_6, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_6}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_5 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_6, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_6}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_6 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_5, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_6}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_6 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_6, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_6}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_6 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_6, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_6}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_6 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_6, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_6}; // @[pla.scala:98:53] wire [10:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_6 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_6, decoded_addr_decoded_decoded_andMatrixOutputs_lo_6}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_27_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_6; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_26 = decoded_addr_decoded_decoded_andMatrixOutputs_27_2; // @[pla.scala:98:70, :114:36] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_7 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_21 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_28 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_29 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_30 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_31 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_32 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_33 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_34 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_35 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_44 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_45 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_46 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_47 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_48 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_49 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_50 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_51 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_67 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_68 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_69 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_70 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_71 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_72 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_73 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_74 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_90 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_91 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_92 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_93 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_94 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_95 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_96 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_97 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_106 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_107 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_108 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_109 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_110 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_111 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_112 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_113 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_121 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_122 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_123 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_124 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_125 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_126 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_127 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_128 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_137 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_138 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_139 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_140 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_141 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_142 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_143 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_144 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_7 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_7, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_7}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_7 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_7, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_7}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_7 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_7, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_7}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_7 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_7, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_7}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_7 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_7, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_7}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_7 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_7, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_7}; // @[pla.scala:91:29, :98:53] wire [4:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_7 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_7, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_7}; // @[pla.scala:98:53] wire [8:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_7 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_7, decoded_addr_decoded_decoded_andMatrixOutputs_lo_7}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_0_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_7; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_23 = decoded_addr_decoded_decoded_andMatrixOutputs_0_2; // @[pla.scala:98:70, :114:36] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_8 = decoded_addr_decoded_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_9 = decoded_addr_decoded_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_10 = decoded_addr_decoded_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_11 = decoded_addr_decoded_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_12 = decoded_addr_decoded_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_51 = decoded_addr_decoded_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_52 = decoded_addr_decoded_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_53 = decoded_addr_decoded_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_54 = decoded_addr_decoded_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_56 = decoded_addr_decoded_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_82 = decoded_addr_decoded_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_4 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_7, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_6}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_8 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_4, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_4}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_7 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_8, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_8}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_8 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_7, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_8}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_8 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_8, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_8}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_6 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_8, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_8}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_8 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_6, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_8}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_8 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_8, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_8}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_8 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_8, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_8}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_8 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_8, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_8}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_8 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_8, decoded_addr_decoded_decoded_andMatrixOutputs_lo_8}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_92_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_8; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_32 = decoded_addr_decoded_decoded_andMatrixOutputs_92_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_5 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_8, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_7}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_9 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_5, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_5}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_8 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_9, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_9}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_9 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_8, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_9}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_9 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_9, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_9}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_7 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_9, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_9}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_9 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_7, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_9}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_9 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_9, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_9}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_9 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_9, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_9}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_9 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_9, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_9}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_9 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_9, decoded_addr_decoded_decoded_andMatrixOutputs_lo_9}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_59_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_9; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_28 = decoded_addr_decoded_decoded_andMatrixOutputs_59_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_6 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_9, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_8}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_10 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_6, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_6}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_9 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_10, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_10}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_10 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_9, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_10}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_10 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_10, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_10}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_8 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_10, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_10}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_10 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_8, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_10}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_10 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_10, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_10}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_10 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_10, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_10}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_10 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_10, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_10}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_10 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_10, decoded_addr_decoded_decoded_andMatrixOutputs_lo_10}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_24_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_10; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_31 = decoded_addr_decoded_decoded_andMatrixOutputs_24_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_7 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_10, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_9}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_11 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_7, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_7}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_10 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_11, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_11}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_11 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_10, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_11}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_11 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_11, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_11}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_9 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_11, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_11}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_11 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_9, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_11}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_11 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_11, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_11}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_11 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_11, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_11}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_11 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_11, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_11}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_11 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_11, decoded_addr_decoded_decoded_andMatrixOutputs_lo_11}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_116_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_11; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_30 = decoded_addr_decoded_decoded_andMatrixOutputs_116_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_12 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_12, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_11}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_11 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_12, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_12}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_12 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_11, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_12}; // @[pla.scala:91:29, :98:53] wire [4:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_12 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_12, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_12}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_12 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_12, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_12}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_12 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_12, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_12}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_12 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_12, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_12}; // @[pla.scala:91:29, :98:53] wire [4:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_12 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_12, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_12}; // @[pla.scala:98:53] wire [9:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_12 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_12, decoded_addr_decoded_decoded_andMatrixOutputs_lo_12}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_121_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_12; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_34 = decoded_addr_decoded_decoded_andMatrixOutputs_121_2; // @[pla.scala:98:70, :114:36] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_13 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_56 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_57 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_58 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_59 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_60 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_61 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_62 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_63 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_64 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_65 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_66 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_67 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_68 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_69 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_70 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_71 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_72 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_73 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_74 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_75 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_76 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_77 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_78 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_79 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_80 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_82 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_13 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_13, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_13}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_13 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_13, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_13}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_13 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_13, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_13}; // @[pla.scala:91:29, :98:53] wire [4:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_13 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_13, decoded_addr_decoded_decoded_andMatrixOutputs_lo_13}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_74_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_13; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_29 = decoded_addr_decoded_decoded_andMatrixOutputs_74_2; // @[pla.scala:98:70, :114:36] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_12 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_13 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_14 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_15 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_16 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_17 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_19 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_20 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_21 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_22 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_21 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_22 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_23 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_24 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_25 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_26 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_27 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_28 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_29 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_30 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_31 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_32 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_33 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_34 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_35 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_36 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_37 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_38 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_39 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_40 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_41 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_42 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_43 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_44 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_45 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_46 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_47 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_48 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_49 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_50 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_51 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_52 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_55 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_56 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_57 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_56 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_57 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_58 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_59 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_60 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_61 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_62 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_63 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_64 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_65 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_66 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_67 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_68 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_69 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_70 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_71 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_72 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_73 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_74 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_75 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_76 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_77 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_80 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_82 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_81 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_80 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_81 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_82 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_83 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_84 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_85 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_86 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_87 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_88 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_89 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_90 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_91 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_92 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_93 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_94 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_95 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_96 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_97 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_98 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_99 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_100 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_101 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_102 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_103 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_104 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_105 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_106 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_107 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_108 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_109 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_143 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_142 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_143 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_144 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_145 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_8 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_12, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_10}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_13 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_8, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_8}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_12 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_13, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_13}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_13 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_12, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_13}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_14 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_13, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_13}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_10 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_14, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_14}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_13 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_10, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_13}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_13 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_14, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_14}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_14 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_13, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_14}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_14 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_14, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_13}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_14 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_14, decoded_addr_decoded_decoded_andMatrixOutputs_lo_14}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_114_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_14; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_144 = decoded_addr_decoded_decoded_andMatrixOutputs_114_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_9 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_13, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_11}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_14 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_9, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_9}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_13 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_14, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_14}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_14 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_13, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_14}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_15 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_14, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_14}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_11 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_15, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_15}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_14 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_11, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_14}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_14 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_15, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_15}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_15 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_14, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_15}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_15 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_15, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_14}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_15 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_15, decoded_addr_decoded_decoded_andMatrixOutputs_lo_15}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_104_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_15; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_145 = decoded_addr_decoded_decoded_andMatrixOutputs_104_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_10 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_14, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_12}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_15 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_10, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_10}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_14 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_15, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_15}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_15 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_14, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_15}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_16 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_15, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_15}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_12 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_16, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_16}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_15 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_12, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_15}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_15 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_16, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_16}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_16 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_15, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_16}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_16 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_16, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_15}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_16 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_16, decoded_addr_decoded_decoded_andMatrixOutputs_lo_16}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_82_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_16; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_24 = decoded_addr_decoded_decoded_andMatrixOutputs_82_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_11 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_15, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_13}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_16 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_11, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_11}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_15 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_16, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_16}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_16 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_15, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_16}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_17 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_16, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_16}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_13 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_17, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_17}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_16 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_13, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_16}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_16 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_17, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_17}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_17 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_16, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_17}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_17 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_17, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_16}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_17 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_17, decoded_addr_decoded_decoded_andMatrixOutputs_lo_17}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_28_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_17; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_25 = decoded_addr_decoded_decoded_andMatrixOutputs_28_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_12 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_16, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_14}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_17 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_12, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_12}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_16 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_17, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_17}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_17 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_16, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_17}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_18 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_17, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_17}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_14 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_18, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_18}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_17 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_14, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_17}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_17 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_18, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_18}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_18 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_17, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_18}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_18 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_18, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_17}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_18 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_18, decoded_addr_decoded_decoded_andMatrixOutputs_lo_18}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_91_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_18; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_141 = decoded_addr_decoded_decoded_andMatrixOutputs_91_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_13 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_17, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_15}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_18 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_13, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_13}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_17 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_18, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_18}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_18 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_17, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_18}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_19 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_18, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_18}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_15 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_19, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_19}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_18 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_15, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_18}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_18 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_19, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_19}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_19 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_18, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_19}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_19 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_19, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_18}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_19 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_19, decoded_addr_decoded_decoded_andMatrixOutputs_lo_19}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_68_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_19; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_143 = decoded_addr_decoded_decoded_andMatrixOutputs_68_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_19 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_18, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_16}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_18 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_19, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_19}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_19 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_18, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_19}; // @[pla.scala:90:45, :98:53] wire [4:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_20 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_19, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_19}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_16 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_20, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_20}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_19 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_16, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_19}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_19 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_20, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_20}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_20 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_19, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_20}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_20 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_20, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_19}; // @[pla.scala:98:53] wire [10:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_20 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_20, decoded_addr_decoded_decoded_andMatrixOutputs_lo_20}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_84_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_20; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_39 = decoded_addr_decoded_decoded_andMatrixOutputs_84_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_20 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_20, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_20}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_20 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_20, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_20}; // @[pla.scala:90:45, :98:53] wire [3:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_21 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_20, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_20}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_20 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_21, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_21}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_20 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_21, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_21}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_21 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_20, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_21}; // @[pla.scala:91:29, :98:53] wire [4:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_21 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_21, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_20}; // @[pla.scala:98:53] wire [8:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_21 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_21, decoded_addr_decoded_decoded_andMatrixOutputs_lo_21}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_40_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_21; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_36 = decoded_addr_decoded_decoded_andMatrixOutputs_40_2; // @[pla.scala:98:70, :114:36] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_22 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_23 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_23 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_24 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_25 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_26 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_27 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_28 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_29 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_30 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_31 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_32 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_33 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_34 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_35 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_36 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_37 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_38 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_39 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_40 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_41 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_42 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_43 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_44 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_45 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_46 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_47 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_48 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_49 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_50 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_57 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_58 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_58 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_59 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_60 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_61 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_62 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_63 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_64 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_65 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_66 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_67 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_68 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_69 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_70 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_71 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_72 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_73 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_74 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_75 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_76 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_77 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_78 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_79 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_81 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_21 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_19, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_17}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_19 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_21, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_21}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_21 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_19, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_21}; // @[pla.scala:90:45, :98:53] wire [4:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_22 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_21, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_21}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_17 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_22, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_22}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_21 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_17, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_21}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_21 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_22, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_22}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_22 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_21, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_22}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_22 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_22, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_21}; // @[pla.scala:98:53] wire [10:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_22 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_22, decoded_addr_decoded_decoded_andMatrixOutputs_lo_22}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_34_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_22; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_129 = decoded_addr_decoded_decoded_andMatrixOutputs_34_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_22 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_20, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_18}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_20 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_22, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_22}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_22 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_20, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_22}; // @[pla.scala:90:45, :98:53] wire [4:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_23 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_22, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_22}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_18 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_23, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_23}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_22 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_18, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_22}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_22 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_23, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_23}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_23 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_22, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_23}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_23 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_23, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_22}; // @[pla.scala:98:53] wire [10:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_23 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_23, decoded_addr_decoded_decoded_andMatrixOutputs_lo_23}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_136_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_23; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_126 = decoded_addr_decoded_decoded_andMatrixOutputs_136_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_14 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_21, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_19}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_23 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_14, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_14}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_21 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_23, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_23}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_23 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_21, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_23}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_24 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_23, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_23}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_19 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_24, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_24}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_23 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_19, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_23}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_23 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_24, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_24}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_24 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_23, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_24}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_24 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_24, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_23}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_24 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_24, decoded_addr_decoded_decoded_andMatrixOutputs_lo_24}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_55_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_24; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_123 = decoded_addr_decoded_decoded_andMatrixOutputs_55_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_15 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_22, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_20}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_24 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_15, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_15}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_22 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_24, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_24}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_24 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_22, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_24}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_25 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_24, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_24}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_20 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_25, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_25}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_24 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_20, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_24}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_24 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_25, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_25}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_25 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_24, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_25}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_25 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_25, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_24}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_25 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_25, decoded_addr_decoded_decoded_andMatrixOutputs_lo_25}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_105_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_25; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_120 = decoded_addr_decoded_decoded_andMatrixOutputs_105_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_16 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_23, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_21}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_25 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_16, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_16}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_23 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_25, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_25}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_25 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_23, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_25}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_26 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_25, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_25}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_21 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_26, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_26}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_25 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_21, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_25}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_25 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_26, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_26}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_26 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_25, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_26}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_26 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_26, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_25}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_26 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_26, decoded_addr_decoded_decoded_andMatrixOutputs_lo_26}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_109_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_26; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_117 = decoded_addr_decoded_decoded_andMatrixOutputs_109_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_17 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_24, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_22}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_26 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_17, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_17}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_24 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_26, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_26}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_26 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_24, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_26}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_27 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_26, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_26}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_22 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_27, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_27}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_26 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_22, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_26}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_26 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_27, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_27}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_27 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_26, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_27}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_27 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_27, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_26}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_27 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_27, decoded_addr_decoded_decoded_andMatrixOutputs_lo_27}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_7_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_27; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_114 = decoded_addr_decoded_decoded_andMatrixOutputs_7_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_18 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_25, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_23}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_27 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_18, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_18}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_25 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_27, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_27}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_27 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_25, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_27}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_28 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_27, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_27}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_23 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_28, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_28}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_27 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_23, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_27}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_27 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_28, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_28}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_28 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_27, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_28}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_28 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_28, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_27}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_28 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_28, decoded_addr_decoded_decoded_andMatrixOutputs_lo_28}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_47_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_28; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_111 = decoded_addr_decoded_decoded_andMatrixOutputs_47_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_19 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_26, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_24}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_28 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_19, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_19}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_26 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_28, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_28}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_28 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_26, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_28}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_29 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_28, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_28}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_24 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_29, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_29}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_28 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_24, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_28}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_28 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_29, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_29}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_29 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_28, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_29}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_29 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_29, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_28}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_29 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_29, decoded_addr_decoded_decoded_andMatrixOutputs_lo_29}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_141_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_29; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_108 = decoded_addr_decoded_decoded_andMatrixOutputs_141_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_20 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_27, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_25}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_29 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_20, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_20}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_27 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_29, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_29}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_29 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_27, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_29}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_30 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_29, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_29}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_25 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_30, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_30}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_29 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_25, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_29}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_29 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_30, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_30}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_30 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_29, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_30}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_30 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_30, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_29}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_30 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_30, decoded_addr_decoded_decoded_andMatrixOutputs_lo_30}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_11_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_30; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_105 = decoded_addr_decoded_decoded_andMatrixOutputs_11_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_21 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_28, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_26}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_30 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_21, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_21}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_28 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_30, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_30}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_30 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_28, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_30}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_31 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_30, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_30}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_26 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_31, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_31}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_30 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_26, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_30}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_30 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_31, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_31}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_31 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_30, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_31}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_31 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_31, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_30}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_31 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_31, decoded_addr_decoded_decoded_andMatrixOutputs_lo_31}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_118_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_31; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_102 = decoded_addr_decoded_decoded_andMatrixOutputs_118_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_22 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_29, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_27}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_31 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_22, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_22}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_29 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_31, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_31}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_31 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_29, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_31}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_32 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_31, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_31}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_27 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_32, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_32}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_31 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_27, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_31}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_31 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_32, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_32}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_32 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_31, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_32}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_32 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_32, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_31}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_32 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_32, decoded_addr_decoded_decoded_andMatrixOutputs_lo_32}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_120_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_32; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_99 = decoded_addr_decoded_decoded_andMatrixOutputs_120_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_23 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_30, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_28}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_32 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_23, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_23}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_30 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_32, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_32}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_32 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_30, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_32}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_33 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_32, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_32}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_28 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_33, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_33}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_32 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_28, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_32}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_32 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_33, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_33}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_33 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_32, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_33}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_33 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_33, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_32}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_33 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_33, decoded_addr_decoded_decoded_andMatrixOutputs_lo_33}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_139_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_33; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_96 = decoded_addr_decoded_decoded_andMatrixOutputs_139_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_24 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_31, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_29}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_33 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_24, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_24}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_31 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_33, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_33}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_33 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_31, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_33}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_34 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_33, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_33}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_29 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_34, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_34}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_33 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_29, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_33}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_33 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_34, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_34}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_34 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_33, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_34}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_34 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_34, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_33}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_34 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_34, decoded_addr_decoded_decoded_andMatrixOutputs_lo_34}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_86_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_34; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_93 = decoded_addr_decoded_decoded_andMatrixOutputs_86_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_25 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_32, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_30}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_34 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_25, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_25}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_32 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_34, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_34}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_34 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_32, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_34}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_35 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_34, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_34}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_30 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_35, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_35}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_34 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_30, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_34}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_34 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_35, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_35}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_35 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_34, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_35}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_35 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_35, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_34}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_35 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_35, decoded_addr_decoded_decoded_andMatrixOutputs_lo_35}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_8_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_35; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_90 = decoded_addr_decoded_decoded_andMatrixOutputs_8_2; // @[pla.scala:98:70, :114:36] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_36 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_37 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_38 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_39 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_40 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_41 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_42 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_43 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_44 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_45 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_46 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_47 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_48 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_49 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_50 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_51 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_59 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_60 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_61 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_62 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_63 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_64 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_65 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_66 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_67 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_68 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_69 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_70 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_71 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_72 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_73 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_74 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_79 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_80 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_81 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_98 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_99 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_100 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_101 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_102 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_103 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_104 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_105 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_106 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_107 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_108 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_109 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_110 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_111 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_112 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_113 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_129 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_130 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_131 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_132 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_133 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_134 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_135 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_136 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_137 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_138 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_139 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_140 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_141 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_142 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_143 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_144 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_145 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_146 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_147 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_148 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_149 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_26 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_33, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_31}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_35 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_26, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_26}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_33 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_35, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_35}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_35 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_33, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_35}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_36 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_35, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_35}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_31 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_36, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_36}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_35 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_31, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_35}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_35 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_36, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_36}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_36 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_35, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_36}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_36 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_36, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_35}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_36 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_36, decoded_addr_decoded_decoded_andMatrixOutputs_lo_36}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_61_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_36; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_87 = decoded_addr_decoded_decoded_andMatrixOutputs_61_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_27 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_34, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_32}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_36 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_27, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_27}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_34 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_36, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_36}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_36 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_34, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_36}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_37 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_36, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_36}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_32 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_37, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_37}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_36 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_32, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_36}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_36 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_37, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_37}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_37 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_36, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_37}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_37 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_37, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_36}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_37 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_37, decoded_addr_decoded_decoded_andMatrixOutputs_lo_37}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_83_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_37; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_84 = decoded_addr_decoded_decoded_andMatrixOutputs_83_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_28 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_35, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_33}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_37 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_28, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_28}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_35 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_37, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_37}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_37 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_35, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_37}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_38 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_37, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_37}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_33 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_38, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_38}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_37 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_33, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_37}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_37 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_38, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_38}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_38 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_37, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_38}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_38 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_38, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_37}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_38 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_38, decoded_addr_decoded_decoded_andMatrixOutputs_lo_38}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_129_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_38; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_81 = decoded_addr_decoded_decoded_andMatrixOutputs_129_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_29 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_36, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_34}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_38 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_29, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_29}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_36 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_38, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_38}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_38 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_36, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_38}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_39 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_38, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_38}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_34 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_39, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_39}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_38 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_34, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_38}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_38 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_39, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_39}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_39 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_38, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_39}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_39 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_39, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_38}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_39 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_39, decoded_addr_decoded_decoded_andMatrixOutputs_lo_39}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_17_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_39; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_78 = decoded_addr_decoded_decoded_andMatrixOutputs_17_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_30 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_37, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_35}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_39 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_30, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_30}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_37 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_39, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_39}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_39 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_37, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_39}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_40 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_39, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_39}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_35 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_40, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_40}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_39 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_35, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_39}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_39 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_40, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_40}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_40 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_39, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_40}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_40 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_40, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_39}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_40 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_40, decoded_addr_decoded_decoded_andMatrixOutputs_lo_40}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_87_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_40; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_75 = decoded_addr_decoded_decoded_andMatrixOutputs_87_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_31 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_38, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_36}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_40 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_31, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_31}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_38 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_40, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_40}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_40 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_38, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_40}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_41 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_40, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_40}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_36 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_41, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_41}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_40 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_36, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_40}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_40 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_41, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_41}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_41 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_40, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_41}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_41 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_41, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_40}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_41 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_41, decoded_addr_decoded_decoded_andMatrixOutputs_lo_41}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_133_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_41; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_72 = decoded_addr_decoded_decoded_andMatrixOutputs_133_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_32 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_39, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_37}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_41 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_32, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_32}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_39 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_41, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_41}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_41 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_39, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_41}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_42 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_41, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_41}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_37 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_42, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_42}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_41 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_37, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_41}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_41 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_42, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_42}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_42 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_41, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_42}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_42 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_42, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_41}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_42 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_42, decoded_addr_decoded_decoded_andMatrixOutputs_lo_42}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_142_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_42; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_69 = decoded_addr_decoded_decoded_andMatrixOutputs_142_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_33 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_40, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_38}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_42 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_33, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_33}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_40 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_42, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_42}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_42 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_40, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_42}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_43 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_42, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_42}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_38 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_43, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_43}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_42 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_38, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_42}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_42 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_43, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_43}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_43 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_42, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_43}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_43 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_43, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_42}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_43 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_43, decoded_addr_decoded_decoded_andMatrixOutputs_lo_43}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_22_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_43; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_66 = decoded_addr_decoded_decoded_andMatrixOutputs_22_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_34 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_41, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_39}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_43 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_34, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_34}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_41 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_43, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_43}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_43 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_41, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_43}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_44 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_43, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_43}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_39 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_44, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_44}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_43 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_39, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_43}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_43 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_44, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_44}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_44 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_43, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_44}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_44 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_44, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_43}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_44 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_44, decoded_addr_decoded_decoded_andMatrixOutputs_lo_44}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_94_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_44; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_63 = decoded_addr_decoded_decoded_andMatrixOutputs_94_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_35 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_42, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_40}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_44 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_35, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_35}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_42 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_44, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_44}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_44 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_42, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_44}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_45 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_44, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_44}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_40 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_45, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_45}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_44 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_40, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_44}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_44 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_45, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_45}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_45 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_44, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_45}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_45 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_45, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_44}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_45 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_45, decoded_addr_decoded_decoded_andMatrixOutputs_lo_45}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_65_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_45; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_60 = decoded_addr_decoded_decoded_andMatrixOutputs_65_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_36 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_43, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_41}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_45 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_36, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_36}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_43 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_45, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_45}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_45 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_43, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_45}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_46 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_45, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_45}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_41 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_46, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_46}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_45 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_41, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_45}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_45 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_46, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_46}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_46 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_45, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_46}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_46 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_46, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_45}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_46 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_46, decoded_addr_decoded_decoded_andMatrixOutputs_lo_46}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_36_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_46; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_57 = decoded_addr_decoded_decoded_andMatrixOutputs_36_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_37 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_44, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_42}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_46 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_37, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_37}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_44 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_46, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_46}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_46 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_44, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_46}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_47 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_46, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_46}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_42 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_47, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_47}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_46 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_42, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_46}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_46 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_47, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_47}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_47 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_46, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_47}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_47 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_47, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_46}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_47 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_47, decoded_addr_decoded_decoded_andMatrixOutputs_lo_47}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_33_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_47; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_54 = decoded_addr_decoded_decoded_andMatrixOutputs_33_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_38 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_45, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_43}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_47 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_38, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_38}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_45 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_47, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_47}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_47 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_45, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_47}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_48 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_47, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_47}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_43 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_48, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_48}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_47 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_43, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_47}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_47 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_48, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_48}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_48 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_47, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_48}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_48 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_48, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_47}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_48 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_48, decoded_addr_decoded_decoded_andMatrixOutputs_lo_48}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_63_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_48; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_51 = decoded_addr_decoded_decoded_andMatrixOutputs_63_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_39 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_46, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_44}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_48 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_39, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_39}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_46 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_48, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_48}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_48 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_46, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_48}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_49 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_48, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_48}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_44 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_49, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_49}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_48 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_44, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_48}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_48 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_49, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_49}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_49 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_48, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_49}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_49 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_49, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_48}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_49 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_49, decoded_addr_decoded_decoded_andMatrixOutputs_lo_49}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_39_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_49; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_48 = decoded_addr_decoded_decoded_andMatrixOutputs_39_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_40 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_47, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_45}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_49 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_40, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_40}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_47 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_49, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_49}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_49 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_47, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_49}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_50 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_49, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_49}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_45 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_50, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_50}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_49 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_45, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_49}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_49 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_50, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_50}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_50 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_49, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_50}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_50 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_50, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_49}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_50 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_50, decoded_addr_decoded_decoded_andMatrixOutputs_lo_50}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_32_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_50; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_45 = decoded_addr_decoded_decoded_andMatrixOutputs_32_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_41 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_48, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_46}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_50 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_41, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_41}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_48 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_50, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_50}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_50 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_48, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_50}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_51 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_50, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_50}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_46 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_51, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_51}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_50 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_46, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_50}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_50 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_51, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_51}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_51 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_50, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_51}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_51 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_51, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_50}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_51 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_51, decoded_addr_decoded_decoded_andMatrixOutputs_lo_51}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_144_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_51; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_42 = decoded_addr_decoded_decoded_andMatrixOutputs_144_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_42 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_49, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_47}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_51 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_42, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_42}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_49 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_51, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_51}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_51 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_49, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_51}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_52 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_51, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_51}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_47 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_52, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_52}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_51 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_47, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_51}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_51 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_52, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_52}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_52 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_51, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_52}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_52 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_52, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_51}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_52 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_52, decoded_addr_decoded_decoded_andMatrixOutputs_lo_52}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_66_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_52; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_140 = decoded_addr_decoded_decoded_andMatrixOutputs_66_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_43 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_50, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_48}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_52 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_43, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_43}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_50 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_52, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_52}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_52 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_50, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_52}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_53 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_52, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_52}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_48 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_53, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_53}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_52 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_48, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_52}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_52 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_53, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_53}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_53 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_52, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_53}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_53 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_53, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_52}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_53 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_53, decoded_addr_decoded_decoded_andMatrixOutputs_lo_53}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_106_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_53; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_139 = decoded_addr_decoded_decoded_andMatrixOutputs_106_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_44 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_51, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_49}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_53 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_44, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_44}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_51 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_53, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_53}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_53 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_51, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_53}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_54 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_53, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_53}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_49 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_54, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_54}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_53 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_49, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_53}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_53 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_54, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_54}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_54 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_53, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_54}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_54 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_54, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_53}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_54 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_54, decoded_addr_decoded_decoded_andMatrixOutputs_lo_54}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_80_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_54; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_137 = decoded_addr_decoded_decoded_andMatrixOutputs_80_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_45 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_52, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_50}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_54 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_45, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_45}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_52 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_54, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_54}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_54 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_52, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_54}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_55 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_54, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_54}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_50 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_55, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_55}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_54 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_50, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_54}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_54 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_55, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_55}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_55 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_54, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_55}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_55 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_55, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_54}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_55 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_55, decoded_addr_decoded_decoded_andMatrixOutputs_lo_55}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_122_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_55; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_138 = decoded_addr_decoded_decoded_andMatrixOutputs_122_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_55 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_55, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_53}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_53 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_55, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_55}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_55 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_53, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_55}; // @[pla.scala:90:45, :98:53] wire [4:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_56 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_55, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_55}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_55 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_56, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_56}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_55 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_56, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_56}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_56 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_55, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_56}; // @[pla.scala:91:29, :98:53] wire [4:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_56 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_56, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_55}; // @[pla.scala:98:53] wire [9:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_56 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_56, decoded_addr_decoded_decoded_andMatrixOutputs_lo_56}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_119_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_56; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_142 = decoded_addr_decoded_decoded_andMatrixOutputs_119_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_56 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_54, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_51}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_54 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_56, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_56}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_56 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_54, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_56}; // @[pla.scala:90:45, :98:53] wire [4:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_57 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_56, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_56}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_51 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_57, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_57}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_56 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_51, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_56}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_56 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_57, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_57}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_57 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_56, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_57}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_57 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_57, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_56}; // @[pla.scala:98:53] wire [10:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_57 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_57, decoded_addr_decoded_decoded_andMatrixOutputs_lo_57}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_67_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_57; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_22 = decoded_addr_decoded_decoded_andMatrixOutputs_67_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_57 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_55, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_52}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_55 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_57, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_57}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_57 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_55, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_57}; // @[pla.scala:90:45, :98:53] wire [4:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_58 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_57, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_57}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_52 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_58, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_58}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_57 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_52, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_57}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_57 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_58, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_58}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_58 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_57, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_58}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_58 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_58, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_57}; // @[pla.scala:98:53] wire [10:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_58 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_58, decoded_addr_decoded_decoded_andMatrixOutputs_lo_58}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_48_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_58; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_21 = decoded_addr_decoded_decoded_andMatrixOutputs_48_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_46 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_56, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_53}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_58 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_46, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_46}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_56 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_58, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_58}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_58 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_56, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_58}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_59 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_58, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_58}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_53 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_59, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_59}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_58 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_53, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_58}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_58 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_59, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_59}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_59 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_58, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_59}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_59 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_59, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_58}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_59 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_59, decoded_addr_decoded_decoded_andMatrixOutputs_lo_59}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_10_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_59; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_20 = decoded_addr_decoded_decoded_andMatrixOutputs_10_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_47 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_57, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_54}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_59 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_47, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_47}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_57 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_59, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_59}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_59 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_57, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_59}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_60 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_59, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_59}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_54 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_60, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_60}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_59 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_54, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_59}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_59 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_60, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_60}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_60 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_59, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_60}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_60 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_60, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_59}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_60 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_60, decoded_addr_decoded_decoded_andMatrixOutputs_lo_60}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_45_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_60; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_19 = decoded_addr_decoded_decoded_andMatrixOutputs_45_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_48 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_58, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_55}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_60 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_48, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_48}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_58 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_60, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_60}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_60 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_58, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_60}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_61 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_60, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_60}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_55 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_61, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_61}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_60 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_55, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_60}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_60 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_61, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_61}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_61 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_60, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_61}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_61 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_61, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_60}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_61 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_61, decoded_addr_decoded_decoded_andMatrixOutputs_lo_61}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_18_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_61; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_18 = decoded_addr_decoded_decoded_andMatrixOutputs_18_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_49 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_59, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_56}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_61 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_49, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_49}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_59 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_61, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_61}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_61 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_59, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_61}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_62 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_61, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_61}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_56 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_62, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_62}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_61 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_56, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_61}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_61 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_62, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_62}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_62 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_61, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_62}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_62 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_62, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_61}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_62 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_62, decoded_addr_decoded_decoded_andMatrixOutputs_lo_62}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_88_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_62; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_17 = decoded_addr_decoded_decoded_andMatrixOutputs_88_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_50 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_60, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_57}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_62 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_50, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_50}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_60 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_62, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_62}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_62 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_60, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_62}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_63 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_62, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_62}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_57 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_63, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_63}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_62 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_57, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_62}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_62 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_63, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_63}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_63 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_62, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_63}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_63 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_63, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_62}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_63 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_63, decoded_addr_decoded_decoded_andMatrixOutputs_lo_63}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_57_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_63; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_16 = decoded_addr_decoded_decoded_andMatrixOutputs_57_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_51 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_61, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_58}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_63 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_51, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_51}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_61 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_63, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_63}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_63 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_61, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_63}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_64 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_63, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_63}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_58 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_64, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_64}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_63 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_58, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_63}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_63 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_64, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_64}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_64 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_63, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_64}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_64 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_64, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_63}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_64 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_64, decoded_addr_decoded_decoded_andMatrixOutputs_lo_64}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_85_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_64; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_15 = decoded_addr_decoded_decoded_andMatrixOutputs_85_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_52 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_62, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_59}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_64 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_52, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_52}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_62 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_64, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_64}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_64 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_62, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_64}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_65 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_64, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_64}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_59 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_65, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_65}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_64 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_59, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_64}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_64 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_65, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_65}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_65 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_64, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_65}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_65 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_65, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_64}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_65 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_65, decoded_addr_decoded_decoded_andMatrixOutputs_lo_65}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_100_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_65; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_14 = decoded_addr_decoded_decoded_andMatrixOutputs_100_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_53 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_63, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_60}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_65 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_53, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_53}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_63 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_65, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_65}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_65 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_63, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_65}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_66 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_65, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_65}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_60 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_66, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_66}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_65 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_60, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_65}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_65 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_66, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_66}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_66 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_65, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_66}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_66 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_66, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_65}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_66 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_66, decoded_addr_decoded_decoded_andMatrixOutputs_lo_66}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_111_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_66; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_13 = decoded_addr_decoded_decoded_andMatrixOutputs_111_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_54 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_64, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_61}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_66 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_54, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_54}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_64 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_66, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_66}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_66 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_64, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_66}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_67 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_66, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_66}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_61 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_67, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_67}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_66 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_61, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_66}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_66 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_67, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_67}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_67 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_66, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_67}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_67 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_67, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_66}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_67 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_67, decoded_addr_decoded_decoded_andMatrixOutputs_lo_67}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_93_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_67; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_12 = decoded_addr_decoded_decoded_andMatrixOutputs_93_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_55 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_65, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_62}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_67 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_55, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_55}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_65 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_67, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_67}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_67 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_65, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_67}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_68 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_67, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_67}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_62 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_68, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_68}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_67 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_62, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_67}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_67 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_68, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_68}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_68 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_67, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_68}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_68 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_68, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_67}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_68 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_68, decoded_addr_decoded_decoded_andMatrixOutputs_lo_68}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_137_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_68; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_11 = decoded_addr_decoded_decoded_andMatrixOutputs_137_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_56 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_66, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_63}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_68 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_56, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_56}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_66 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_68, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_68}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_68 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_66, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_68}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_69 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_68, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_68}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_63 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_69, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_69}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_68 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_63, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_68}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_68 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_69, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_69}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_69 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_68, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_69}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_69 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_69, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_68}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_69 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_69, decoded_addr_decoded_decoded_andMatrixOutputs_lo_69}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_72_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_69; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_10 = decoded_addr_decoded_decoded_andMatrixOutputs_72_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_57 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_67, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_64}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_69 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_57, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_57}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_67 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_69, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_69}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_69 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_67, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_69}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_70 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_69, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_69}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_64 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_70, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_70}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_69 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_64, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_69}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_69 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_70, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_70}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_70 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_69, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_70}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_70 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_70, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_69}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_70 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_70, decoded_addr_decoded_decoded_andMatrixOutputs_lo_70}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_42_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_70; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_9 = decoded_addr_decoded_decoded_andMatrixOutputs_42_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_58 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_68, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_65}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_70 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_58, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_58}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_68 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_70, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_70}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_70 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_68, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_70}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_71 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_70, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_70}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_65 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_71, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_71}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_70 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_65, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_70}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_70 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_71, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_71}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_71 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_70, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_71}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_71 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_71, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_70}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_71 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_71, decoded_addr_decoded_decoded_andMatrixOutputs_lo_71}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_145_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_71; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_8 = decoded_addr_decoded_decoded_andMatrixOutputs_145_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_59 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_69, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_66}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_71 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_59, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_59}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_69 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_71, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_71}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_71 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_69, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_71}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_72 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_71, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_71}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_66 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_72, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_72}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_71 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_66, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_71}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_71 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_72, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_72}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_72 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_71, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_72}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_72 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_72, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_71}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_72 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_72, decoded_addr_decoded_decoded_andMatrixOutputs_lo_72}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_98_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_72; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_7 = decoded_addr_decoded_decoded_andMatrixOutputs_98_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_60 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_70, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_67}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_72 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_60, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_60}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_70 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_72, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_72}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_72 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_70, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_72}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_73 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_72, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_72}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_67 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_73, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_73}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_72 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_67, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_72}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_72 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_73, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_73}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_73 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_72, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_73}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_73 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_73, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_72}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_73 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_73, decoded_addr_decoded_decoded_andMatrixOutputs_lo_73}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_113_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_73; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_6 = decoded_addr_decoded_decoded_andMatrixOutputs_113_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_61 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_71, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_68}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_73 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_61, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_61}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_71 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_73, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_73}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_73 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_71, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_73}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_74 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_73, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_73}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_68 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_74, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_74}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_73 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_68, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_73}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_73 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_74, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_74}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_74 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_73, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_74}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_74 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_74, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_73}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_74 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_74, decoded_addr_decoded_decoded_andMatrixOutputs_lo_74}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_149_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_74; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_5 = decoded_addr_decoded_decoded_andMatrixOutputs_149_2; // @[pla.scala:98:70, :114:36] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_69 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_70 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_71 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_72 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_73 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_74 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_78 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_82 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_110 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_108 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_109 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_110 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_111 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_112 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_113 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_114 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_115 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_116 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_117 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_118 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_119 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_120 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_121 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_122 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_123 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_124 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_125 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_126 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_127 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_128 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_129 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_130 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_131 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_132 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_133 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_134 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_135 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_136 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_137 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_141 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_139 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_140 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_141 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_142 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_62 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_72, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_69}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_74 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_62, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_62}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_72 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_74, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_74}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_74 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_72, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_74}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_75 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_74, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_74}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_69 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_75, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_75}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_74 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_69, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_74}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_74 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_75, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_75}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_75 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_74, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_75}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_75 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_75, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_74}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_75 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_75, decoded_addr_decoded_decoded_andMatrixOutputs_lo_75}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_2_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_75; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_149 = decoded_addr_decoded_decoded_andMatrixOutputs_2_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_63 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_73, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_70}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_75 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_63, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_63}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_73 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_75, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_75}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_75 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_73, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_75}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_76 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_75, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_75}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_70 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_76, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_76}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_75 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_70, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_75}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_75 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_76, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_76}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_76 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_75, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_76}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_76 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_76, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_75}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_76 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_76, decoded_addr_decoded_decoded_andMatrixOutputs_lo_76}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_146_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_76; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_148 = decoded_addr_decoded_decoded_andMatrixOutputs_146_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_64 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_74, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_71}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_76 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_64, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_64}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_74 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_76, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_76}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_76 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_74, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_76}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_77 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_76, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_76}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_71 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_77, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_77}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_76 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_71, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_76}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_76 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_77, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_77}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_77 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_76, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_77}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_77 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_77, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_76}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_77 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_77, decoded_addr_decoded_decoded_andMatrixOutputs_lo_77}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_128_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_77; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_147 = decoded_addr_decoded_decoded_andMatrixOutputs_128_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_65 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_75, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_72}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_77 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_65, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_65}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_75 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_77, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_77}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_77 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_75, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_77}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_78 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_77, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_77}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_72 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_78, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_78}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_77 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_72, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_77}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_77 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_78, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_78}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_78 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_77, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_78}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_78 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_78, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_77}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_78 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_78, decoded_addr_decoded_decoded_andMatrixOutputs_lo_78}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_56_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_78; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_146 = decoded_addr_decoded_decoded_andMatrixOutputs_56_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_66 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_76, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_73}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_78 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_66, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_66}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_76 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_78, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_78}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_78 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_76, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_78}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_79 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_78, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_78}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_73 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_79, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_79}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_78 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_73, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_78}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_78 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_79, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_79}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_79 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_78, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_79}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_79 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_79, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_78}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_79 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_79, decoded_addr_decoded_decoded_andMatrixOutputs_lo_79}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_3_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_79; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_135 = decoded_addr_decoded_decoded_andMatrixOutputs_3_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_67 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_77, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_74}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_79 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_67, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_67}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_77 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_79, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_79}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_79 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_77, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_79}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_80 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_79, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_79}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_74 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_80, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_80}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_79 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_74, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_79}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_79 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_80, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_80}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_80 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_79, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_80}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_80 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_80, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_79}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_80 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_80, decoded_addr_decoded_decoded_andMatrixOutputs_lo_80}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_50_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_80; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_134 = decoded_addr_decoded_decoded_andMatrixOutputs_50_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_80 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_78, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_75}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_78 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_80, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_80}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_80 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_78, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_80}; // @[pla.scala:90:45, :98:53] wire [4:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_81 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_80, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_80}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_75 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_81, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_81}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_80 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_75, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_80}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_80 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_81, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_81}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_81 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_80, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_81}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_81 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_81, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_80}; // @[pla.scala:98:53] wire [10:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_81 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_81, decoded_addr_decoded_decoded_andMatrixOutputs_lo_81}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_23_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_81; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_133 = decoded_addr_decoded_decoded_andMatrixOutputs_23_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_81 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_82, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_82}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_82 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_81, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_81}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_82 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_82, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_82}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_82 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_82, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_82}; // @[pla.scala:90:45, :98:53] wire [5:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_82 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_82, decoded_addr_decoded_decoded_andMatrixOutputs_lo_82}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_12_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_82; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_4 = decoded_addr_decoded_decoded_andMatrixOutputs_12_2; // @[pla.scala:98:70, :114:36] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_76 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_68 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_69 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_70 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_71 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_72 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_73 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_74 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_75 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_76 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_77 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_78 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_79 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_80 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_81 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_82 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_83 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_84 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_85 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_86 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_87 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_88 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_89 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_90 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_91 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_92 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_93 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_94 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_95 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_96 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_97 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_107 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_98 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_99 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_100 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_101 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_102 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_103 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_104 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_105 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_106 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_107 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_108 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_109 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_110 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_111 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_112 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_113 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_114 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_115 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_116 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_117 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_118 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_119 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_120 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_121 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_122 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_123 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_124 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_125 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_126 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_127 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_138 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_128 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_129 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_130 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_131 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_81 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_79, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_76}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_79 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_81, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_81}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_82 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_79, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_81}; // @[pla.scala:90:45, :98:53] wire [4:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_83 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_82, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_81}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_76 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_83, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_83}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_81 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_76, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_82}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_81 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_83, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_83}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_83 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_81, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_83}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_83 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_83, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_81}; // @[pla.scala:98:53] wire [10:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_83 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_83, decoded_addr_decoded_decoded_andMatrixOutputs_lo_83}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_76_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_83; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_128 = decoded_addr_decoded_decoded_andMatrixOutputs_76_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_68 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_80, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_77}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_82 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_68, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_68}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_80 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_82, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_82}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_83 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_80, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_82}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_84 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_83, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_82}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_77 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_84, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_84}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_82 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_77, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_83}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_82 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_84, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_84}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_84 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_82, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_84}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_84 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_84, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_82}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_84 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_84, decoded_addr_decoded_decoded_andMatrixOutputs_lo_84}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_79_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_84; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_127 = decoded_addr_decoded_decoded_andMatrixOutputs_79_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_69 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_81, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_78}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_83 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_69, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_69}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_81 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_83, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_83}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_84 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_81, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_83}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_85 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_84, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_83}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_78 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_85, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_85}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_83 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_78, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_84}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_83 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_85, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_85}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_85 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_83, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_85}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_85 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_85, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_83}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_85 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_85, decoded_addr_decoded_decoded_andMatrixOutputs_lo_85}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_95_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_85; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_125 = decoded_addr_decoded_decoded_andMatrixOutputs_95_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_70 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_82, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_79}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_84 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_70, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_70}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_82 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_84, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_84}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_85 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_82, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_84}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_86 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_85, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_84}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_79 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_86, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_86}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_84 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_79, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_85}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_84 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_86, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_86}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_86 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_84, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_86}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_86 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_86, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_84}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_86 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_86, decoded_addr_decoded_decoded_andMatrixOutputs_lo_86}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_26_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_86; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_122 = decoded_addr_decoded_decoded_andMatrixOutputs_26_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_71 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_83, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_80}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_85 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_71, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_71}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_83 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_85, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_85}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_86 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_83, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_85}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_87 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_86, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_85}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_80 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_87, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_87}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_85 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_80, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_86}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_85 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_87, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_87}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_87 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_85, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_87}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_87 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_87, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_85}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_87 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_87, decoded_addr_decoded_decoded_andMatrixOutputs_lo_87}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_124_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_87; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_119 = decoded_addr_decoded_decoded_andMatrixOutputs_124_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_72 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_84, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_81}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_86 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_72, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_72}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_84 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_86, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_86}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_87 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_84, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_86}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_88 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_87, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_86}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_81 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_88, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_88}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_86 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_81, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_87}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_86 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_88, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_88}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_88 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_86, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_88}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_88 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_88, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_86}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_88 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_88, decoded_addr_decoded_decoded_andMatrixOutputs_lo_88}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_147_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_88; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_116 = decoded_addr_decoded_decoded_andMatrixOutputs_147_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_73 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_85, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_82}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_87 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_73, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_73}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_85 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_87, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_87}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_88 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_85, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_87}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_89 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_88, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_87}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_82 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_89, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_89}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_87 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_82, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_88}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_87 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_89, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_89}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_89 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_87, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_89}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_89 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_89, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_87}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_89 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_89, decoded_addr_decoded_decoded_andMatrixOutputs_lo_89}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_77_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_89; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_113 = decoded_addr_decoded_decoded_andMatrixOutputs_77_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_74 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_86, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_83}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_88 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_74, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_74}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_86 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_88, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_88}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_89 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_86, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_88}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_90 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_89, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_88}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_83 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_90, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_90}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_88 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_83, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_89}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_88 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_90, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_90}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_90 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_88, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_90}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_90 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_90, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_88}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_90 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_90, decoded_addr_decoded_decoded_andMatrixOutputs_lo_90}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_140_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_90; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_110 = decoded_addr_decoded_decoded_andMatrixOutputs_140_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_75 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_87, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_84}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_89 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_75, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_75}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_87 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_89, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_89}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_90 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_87, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_89}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_91 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_90, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_89}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_84 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_91, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_91}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_89 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_84, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_90}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_89 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_91, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_91}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_91 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_89, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_91}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_91 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_91, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_89}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_91 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_91, decoded_addr_decoded_decoded_andMatrixOutputs_lo_91}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_44_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_91; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_107 = decoded_addr_decoded_decoded_andMatrixOutputs_44_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_76 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_88, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_85}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_90 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_76, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_76}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_88 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_90, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_90}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_91 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_88, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_90}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_92 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_91, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_90}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_85 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_92, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_92}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_90 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_85, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_91}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_90 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_92, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_92}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_92 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_90, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_92}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_92 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_92, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_90}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_92 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_92, decoded_addr_decoded_decoded_andMatrixOutputs_lo_92}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_31_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_92; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_104 = decoded_addr_decoded_decoded_andMatrixOutputs_31_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_77 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_89, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_86}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_91 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_77, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_77}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_89 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_91, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_91}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_92 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_89, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_91}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_93 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_92, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_91}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_86 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_93, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_93}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_91 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_86, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_92}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_91 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_93, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_93}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_93 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_91, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_93}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_93 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_93, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_91}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_93 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_93, decoded_addr_decoded_decoded_andMatrixOutputs_lo_93}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_62_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_93; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_101 = decoded_addr_decoded_decoded_andMatrixOutputs_62_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_78 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_90, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_87}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_92 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_78, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_78}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_90 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_92, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_92}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_93 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_90, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_92}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_94 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_93, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_92}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_87 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_94, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_94}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_92 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_87, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_93}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_92 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_94, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_94}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_94 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_92, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_94}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_94 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_94, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_92}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_94 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_94, decoded_addr_decoded_decoded_andMatrixOutputs_lo_94}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_58_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_94; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_98 = decoded_addr_decoded_decoded_andMatrixOutputs_58_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_79 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_91, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_88}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_93 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_79, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_79}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_91 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_93, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_93}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_94 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_91, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_93}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_95 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_94, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_93}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_88 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_95, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_95}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_93 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_88, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_94}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_93 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_95, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_95}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_95 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_93, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_95}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_95 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_95, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_93}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_95 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_95, decoded_addr_decoded_decoded_andMatrixOutputs_lo_95}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_132_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_95; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_95 = decoded_addr_decoded_decoded_andMatrixOutputs_132_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_80 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_92, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_89}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_94 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_80, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_80}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_92 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_94, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_94}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_95 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_92, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_94}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_96 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_95, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_94}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_89 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_96, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_96}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_94 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_89, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_95}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_94 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_96, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_96}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_96 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_94, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_96}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_96 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_96, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_94}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_96 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_96, decoded_addr_decoded_decoded_andMatrixOutputs_lo_96}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_9_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_96; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_92 = decoded_addr_decoded_decoded_andMatrixOutputs_9_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_81 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_93, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_90}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_95 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_81, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_81}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_93 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_95, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_95}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_96 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_93, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_95}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_97 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_96, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_95}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_90 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_97, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_97}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_95 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_90, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_96}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_95 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_97, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_97}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_97 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_95, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_97}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_97 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_97, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_95}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_97 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_97, decoded_addr_decoded_decoded_andMatrixOutputs_lo_97}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_115_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_97; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_89 = decoded_addr_decoded_decoded_andMatrixOutputs_115_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_82 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_94, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_91}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_96 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_82, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_82}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_94 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_96, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_96}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_97 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_94, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_96}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_98 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_97, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_96}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_91 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_98, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_98}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_96 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_91, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_97}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_96 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_98, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_98}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_98 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_96, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_98}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_98 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_98, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_96}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_98 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_98, decoded_addr_decoded_decoded_andMatrixOutputs_lo_98}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_5_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_98; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_86 = decoded_addr_decoded_decoded_andMatrixOutputs_5_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_83 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_95, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_92}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_97 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_83, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_83}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_95 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_97, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_97}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_98 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_95, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_97}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_99 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_98, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_97}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_92 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_99, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_99}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_97 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_92, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_98}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_97 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_99, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_99}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_99 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_97, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_99}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_99 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_99, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_97}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_99 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_99, decoded_addr_decoded_decoded_andMatrixOutputs_lo_99}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_71_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_99; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_83 = decoded_addr_decoded_decoded_andMatrixOutputs_71_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_84 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_96, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_93}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_98 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_84, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_84}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_96 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_98, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_98}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_99 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_96, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_98}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_100 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_99, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_98}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_93 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_100, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_100}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_98 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_93, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_99}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_98 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_100, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_100}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_100 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_98, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_100}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_100 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_100, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_98}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_100 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_100, decoded_addr_decoded_decoded_andMatrixOutputs_lo_100}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_130_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_100; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_80 = decoded_addr_decoded_decoded_andMatrixOutputs_130_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_85 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_97, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_94}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_99 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_85, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_85}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_97 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_99, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_99}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_100 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_97, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_99}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_101 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_100, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_99}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_94 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_101, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_101}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_99 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_94, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_100}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_99 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_101, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_101}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_101 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_99, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_101}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_101 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_101, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_99}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_101 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_101, decoded_addr_decoded_decoded_andMatrixOutputs_lo_101}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_102_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_101; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_77 = decoded_addr_decoded_decoded_andMatrixOutputs_102_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_86 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_98, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_95}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_100 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_86, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_86}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_98 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_100, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_100}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_101 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_98, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_100}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_102 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_101, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_100}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_95 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_102, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_102}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_100 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_95, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_101}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_100 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_102, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_102}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_102 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_100, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_102}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_102 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_102, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_100}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_102 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_102, decoded_addr_decoded_decoded_andMatrixOutputs_lo_102}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_4_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_102; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_74 = decoded_addr_decoded_decoded_andMatrixOutputs_4_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_87 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_99, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_96}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_101 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_87, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_87}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_99 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_101, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_101}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_102 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_99, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_101}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_103 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_102, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_101}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_96 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_103, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_103}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_101 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_96, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_102}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_101 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_103, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_103}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_103 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_101, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_103}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_103 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_103, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_101}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_103 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_103, decoded_addr_decoded_decoded_andMatrixOutputs_lo_103}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_29_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_103; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_71 = decoded_addr_decoded_decoded_andMatrixOutputs_29_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_88 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_100, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_97}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_102 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_88, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_88}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_100 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_102, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_102}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_103 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_100, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_102}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_104 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_103, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_102}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_97 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_104, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_104}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_102 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_97, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_103}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_102 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_104, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_104}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_104 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_102, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_104}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_104 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_104, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_102}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_104 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_104, decoded_addr_decoded_decoded_andMatrixOutputs_lo_104}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_16_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_104; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_68 = decoded_addr_decoded_decoded_andMatrixOutputs_16_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_89 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_101, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_98}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_103 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_89, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_89}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_101 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_103, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_103}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_104 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_101, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_103}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_105 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_104, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_103}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_98 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_105, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_105}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_103 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_98, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_104}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_103 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_105, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_105}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_105 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_103, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_105}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_105 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_105, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_103}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_105 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_105, decoded_addr_decoded_decoded_andMatrixOutputs_lo_105}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_143_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_105; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_65 = decoded_addr_decoded_decoded_andMatrixOutputs_143_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_90 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_102, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_99}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_104 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_90, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_90}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_102 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_104, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_104}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_105 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_102, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_104}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_106 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_105, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_104}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_99 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_106, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_106}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_104 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_99, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_105}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_104 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_106, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_106}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_106 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_104, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_106}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_106 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_106, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_104}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_106 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_106, decoded_addr_decoded_decoded_andMatrixOutputs_lo_106}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_131_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_106; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_62 = decoded_addr_decoded_decoded_andMatrixOutputs_131_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_91 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_103, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_100}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_105 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_91, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_91}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_103 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_105, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_105}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_106 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_103, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_105}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_107 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_106, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_105}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_100 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_107, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_107}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_105 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_100, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_106}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_105 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_107, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_107}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_107 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_105, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_107}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_107 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_107, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_105}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_107 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_107, decoded_addr_decoded_decoded_andMatrixOutputs_lo_107}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_14_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_107; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_59 = decoded_addr_decoded_decoded_andMatrixOutputs_14_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_92 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_104, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_101}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_106 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_92, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_92}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_104 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_106, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_106}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_107 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_104, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_106}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_108 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_107, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_106}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_101 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_108, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_108}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_106 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_101, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_107}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_106 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_108, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_108}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_108 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_106, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_108}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_108 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_108, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_106}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_108 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_108, decoded_addr_decoded_decoded_andMatrixOutputs_lo_108}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_90_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_108; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_56 = decoded_addr_decoded_decoded_andMatrixOutputs_90_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_93 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_105, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_102}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_107 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_93, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_93}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_105 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_107, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_107}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_108 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_105, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_107}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_109 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_108, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_107}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_102 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_109, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_109}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_107 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_102, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_108}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_107 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_109, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_109}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_109 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_107, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_109}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_109 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_109, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_107}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_109 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_109, decoded_addr_decoded_decoded_andMatrixOutputs_lo_109}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_97_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_109; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_53 = decoded_addr_decoded_decoded_andMatrixOutputs_97_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_94 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_106, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_103}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_108 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_94, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_94}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_106 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_108, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_108}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_109 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_106, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_108}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_110 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_109, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_108}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_103 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_110, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_110}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_108 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_103, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_109}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_108 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_110, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_110}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_110 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_108, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_110}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_110 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_110, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_108}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_110 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_110, decoded_addr_decoded_decoded_andMatrixOutputs_lo_110}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_60_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_110; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_50 = decoded_addr_decoded_decoded_andMatrixOutputs_60_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_95 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_107, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_104}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_109 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_95, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_95}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_107 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_109, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_109}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_110 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_107, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_109}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_111 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_110, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_109}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_104 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_111, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_111}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_109 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_104, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_110}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_109 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_111, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_111}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_111 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_109, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_111}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_111 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_111, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_109}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_111 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_111, decoded_addr_decoded_decoded_andMatrixOutputs_lo_111}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_96_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_111; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_47 = decoded_addr_decoded_decoded_andMatrixOutputs_96_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_96 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_108, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_105}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_110 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_96, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_96}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_108 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_110, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_110}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_111 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_108, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_110}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_112 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_111, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_110}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_105 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_112, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_112}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_110 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_105, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_111}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_110 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_112, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_112}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_112 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_110, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_112}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_112 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_112, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_110}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_112 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_112, decoded_addr_decoded_decoded_andMatrixOutputs_lo_112}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_54_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_112; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_44 = decoded_addr_decoded_decoded_andMatrixOutputs_54_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_97 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_109, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_106}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_111 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_97, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_97}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_109 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_111, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_111}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_112 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_109, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_111}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_113 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_112, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_111}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_106 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_113, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_113}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_111 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_106, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_112}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_111 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_113, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_113}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_113 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_111, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_113}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_113 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_113, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_111}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_113 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_113, decoded_addr_decoded_decoded_andMatrixOutputs_lo_113}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_126_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_113; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_41 = decoded_addr_decoded_decoded_andMatrixOutputs_126_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_112 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_110, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_107}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_110 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_112, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_112}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_113 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_110, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_112}; // @[pla.scala:91:29, :98:53] wire [4:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_114 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_113, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_112}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_107 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_114, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_114}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_112 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_107, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_113}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_112 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_114, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_114}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_114 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_112, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_114}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_114 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_114, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_112}; // @[pla.scala:98:53] wire [10:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_114 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_114, decoded_addr_decoded_decoded_andMatrixOutputs_lo_114}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_49_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_114; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_38 = decoded_addr_decoded_decoded_andMatrixOutputs_49_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_98 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_111, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_108}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_113 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_98, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_98}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_111 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_113, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_113}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_114 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_111, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_113}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_115 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_114, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_113}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_108 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_115, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_115}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_113 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_108, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_114}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_113 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_115, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_115}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_115 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_113, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_115}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_115 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_115, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_113}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_115 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_115, decoded_addr_decoded_decoded_andMatrixOutputs_lo_115}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_52_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_115; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_37 = decoded_addr_decoded_decoded_andMatrixOutputs_52_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_99 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_112, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_109}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_114 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_99, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_99}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_112 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_114, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_114}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_115 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_112, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_114}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_116 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_115, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_114}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_109 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_116, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_116}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_114 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_109, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_115}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_114 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_116, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_116}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_116 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_114, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_116}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_116 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_116, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_114}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_116 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_116, decoded_addr_decoded_decoded_andMatrixOutputs_lo_116}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_20_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_116; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_124 = decoded_addr_decoded_decoded_andMatrixOutputs_20_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_100 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_113, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_110}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_115 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_100, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_100}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_113 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_115, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_115}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_116 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_113, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_115}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_117 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_116, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_115}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_110 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_117, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_117}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_115 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_110, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_116}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_115 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_117, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_117}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_117 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_115, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_117}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_117 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_117, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_115}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_117 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_117, decoded_addr_decoded_decoded_andMatrixOutputs_lo_117}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_107_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_117; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_121 = decoded_addr_decoded_decoded_andMatrixOutputs_107_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_101 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_114, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_111}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_116 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_101, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_101}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_114 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_116, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_116}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_117 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_114, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_116}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_118 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_117, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_116}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_111 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_118, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_118}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_116 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_111, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_117}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_116 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_118, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_118}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_118 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_116, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_118}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_118 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_118, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_116}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_118 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_118, decoded_addr_decoded_decoded_andMatrixOutputs_lo_118}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_6_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_118; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_118 = decoded_addr_decoded_decoded_andMatrixOutputs_6_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_102 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_115, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_112}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_117 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_102, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_102}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_115 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_117, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_117}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_118 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_115, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_117}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_119 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_118, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_117}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_112 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_119, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_119}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_117 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_112, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_118}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_117 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_119, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_119}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_119 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_117, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_119}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_119 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_119, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_117}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_119 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_119, decoded_addr_decoded_decoded_andMatrixOutputs_lo_119}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_21_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_119; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_115 = decoded_addr_decoded_decoded_andMatrixOutputs_21_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_103 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_116, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_113}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_118 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_103, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_103}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_116 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_118, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_118}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_119 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_116, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_118}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_120 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_119, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_118}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_113 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_120, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_120}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_118 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_113, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_119}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_118 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_120, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_120}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_120 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_118, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_120}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_120 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_120, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_118}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_120 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_120, decoded_addr_decoded_decoded_andMatrixOutputs_lo_120}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_30_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_120; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_112 = decoded_addr_decoded_decoded_andMatrixOutputs_30_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_104 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_117, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_114}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_119 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_104, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_104}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_117 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_119, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_119}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_120 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_117, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_119}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_121 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_120, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_119}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_114 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_121, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_121}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_119 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_114, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_120}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_119 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_121, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_121}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_121 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_119, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_121}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_121 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_121, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_119}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_121 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_121, decoded_addr_decoded_decoded_andMatrixOutputs_lo_121}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_127_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_121; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_109 = decoded_addr_decoded_decoded_andMatrixOutputs_127_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_105 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_118, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_115}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_120 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_105, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_105}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_118 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_120, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_120}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_121 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_118, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_120}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_122 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_121, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_120}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_115 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_122, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_122}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_120 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_115, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_121}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_120 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_122, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_122}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_122 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_120, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_122}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_122 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_122, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_120}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_122 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_122, decoded_addr_decoded_decoded_andMatrixOutputs_lo_122}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_35_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_122; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_106 = decoded_addr_decoded_decoded_andMatrixOutputs_35_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_106 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_119, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_116}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_121 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_106, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_106}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_119 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_121, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_121}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_122 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_119, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_121}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_123 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_122, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_121}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_116 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_123, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_123}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_121 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_116, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_122}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_121 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_123, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_123}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_123 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_121, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_123}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_123 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_123, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_121}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_123 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_123, decoded_addr_decoded_decoded_andMatrixOutputs_lo_123}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_73_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_123; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_103 = decoded_addr_decoded_decoded_andMatrixOutputs_73_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_107 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_120, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_117}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_122 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_107, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_107}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_120 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_122, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_122}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_123 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_120, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_122}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_124 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_123, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_122}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_117 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_124, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_124}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_122 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_117, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_123}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_122 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_124, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_124}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_124 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_122, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_124}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_124 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_124, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_122}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_124 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_124, decoded_addr_decoded_decoded_andMatrixOutputs_lo_124}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_53_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_124; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_100 = decoded_addr_decoded_decoded_andMatrixOutputs_53_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_108 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_121, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_118}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_123 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_108, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_108}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_121 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_123, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_123}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_124 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_121, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_123}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_125 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_124, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_123}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_118 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_125, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_125}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_123 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_118, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_124}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_123 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_125, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_125}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_125 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_123, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_125}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_125 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_125, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_123}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_125 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_125, decoded_addr_decoded_decoded_andMatrixOutputs_lo_125}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_135_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_125; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_97 = decoded_addr_decoded_decoded_andMatrixOutputs_135_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_109 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_122, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_119}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_124 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_109, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_109}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_122 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_124, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_124}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_125 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_122, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_124}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_126 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_125, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_124}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_119 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_126, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_126}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_124 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_119, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_125}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_124 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_126, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_126}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_126 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_124, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_126}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_126 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_126, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_124}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_126 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_126, decoded_addr_decoded_decoded_andMatrixOutputs_lo_126}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_37_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_126; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_94 = decoded_addr_decoded_decoded_andMatrixOutputs_37_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_110 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_123, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_120}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_125 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_110, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_110}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_123 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_125, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_125}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_126 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_123, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_125}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_127 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_126, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_125}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_120 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_127, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_127}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_125 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_120, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_126}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_125 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_127, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_127}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_127 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_125, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_127}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_127 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_127, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_125}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_127 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_127, decoded_addr_decoded_decoded_andMatrixOutputs_lo_127}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_25_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_127; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_91 = decoded_addr_decoded_decoded_andMatrixOutputs_25_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_111 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_124, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_121}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_126 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_111, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_111}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_124 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_126, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_126}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_127 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_124, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_126}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_128 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_127, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_126}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_121 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_128, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_128}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_126 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_121, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_127}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_126 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_128, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_128}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_128 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_126, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_128}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_128 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_128, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_126}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_128 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_128, decoded_addr_decoded_decoded_andMatrixOutputs_lo_128}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_64_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_128; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_88 = decoded_addr_decoded_decoded_andMatrixOutputs_64_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_112 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_125, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_122}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_127 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_112, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_112}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_125 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_127, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_127}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_128 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_125, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_127}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_129 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_128, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_127}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_122 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_129, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_129}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_127 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_122, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_128}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_127 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_129, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_129}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_129 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_127, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_129}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_129 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_129, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_127}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_129 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_129, decoded_addr_decoded_decoded_andMatrixOutputs_lo_129}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_19_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_129; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_85 = decoded_addr_decoded_decoded_andMatrixOutputs_19_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_113 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_126, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_123}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_128 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_113, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_113}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_126 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_128, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_128}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_129 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_126, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_128}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_130 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_129, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_128}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_123 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_130, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_130}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_128 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_123, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_129}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_128 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_130, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_130}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_130 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_128, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_130}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_130 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_130, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_128}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_130 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_130, decoded_addr_decoded_decoded_andMatrixOutputs_lo_130}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_112_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_130; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_82 = decoded_addr_decoded_decoded_andMatrixOutputs_112_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_114 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_127, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_124}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_129 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_114, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_114}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_127 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_129, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_129}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_130 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_127, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_129}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_131 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_130, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_129}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_124 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_131, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_131}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_129 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_124, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_130}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_129 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_131, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_131}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_131 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_129, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_131}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_131 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_131, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_129}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_131 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_131, decoded_addr_decoded_decoded_andMatrixOutputs_lo_131}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_108_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_131; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_79 = decoded_addr_decoded_decoded_andMatrixOutputs_108_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_115 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_128, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_125}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_130 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_115, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_115}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_128 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_130, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_130}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_131 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_128, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_130}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_132 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_131, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_130}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_125 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_132, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_132}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_130 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_125, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_131}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_130 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_132, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_132}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_132 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_130, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_132}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_132 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_132, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_130}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_132 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_132, decoded_addr_decoded_decoded_andMatrixOutputs_lo_132}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_148_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_132; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_76 = decoded_addr_decoded_decoded_andMatrixOutputs_148_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_116 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_129, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_126}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_131 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_116, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_116}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_129 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_131, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_131}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_132 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_129, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_131}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_133 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_132, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_131}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_126 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_133, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_133}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_131 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_126, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_132}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_131 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_133, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_133}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_133 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_131, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_133}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_133 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_133, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_131}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_133 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_133, decoded_addr_decoded_decoded_andMatrixOutputs_lo_133}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_69_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_133; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_73 = decoded_addr_decoded_decoded_andMatrixOutputs_69_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_117 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_130, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_127}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_132 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_117, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_117}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_130 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_132, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_132}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_133 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_130, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_132}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_134 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_133, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_132}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_127 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_134, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_134}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_132 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_127, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_133}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_132 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_134, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_134}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_134 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_132, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_134}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_134 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_134, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_132}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_134 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_134, decoded_addr_decoded_decoded_andMatrixOutputs_lo_134}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_103_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_134; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_70 = decoded_addr_decoded_decoded_andMatrixOutputs_103_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_118 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_131, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_128}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_133 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_118, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_118}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_131 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_133, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_133}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_134 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_131, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_133}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_135 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_134, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_133}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_128 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_135, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_135}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_133 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_128, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_134}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_133 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_135, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_135}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_135 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_133, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_135}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_135 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_135, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_133}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_135 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_135, decoded_addr_decoded_decoded_andMatrixOutputs_lo_135}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_99_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_135; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_67 = decoded_addr_decoded_decoded_andMatrixOutputs_99_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_119 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_132, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_129}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_134 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_119, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_119}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_132 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_134, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_134}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_135 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_132, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_134}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_136 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_135, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_134}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_129 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_136, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_136}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_134 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_129, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_135}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_134 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_136, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_136}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_136 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_134, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_136}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_136 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_136, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_134}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_136 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_136, decoded_addr_decoded_decoded_andMatrixOutputs_lo_136}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_125_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_136; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_64 = decoded_addr_decoded_decoded_andMatrixOutputs_125_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_120 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_133, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_130}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_135 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_120, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_120}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_133 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_135, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_135}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_136 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_133, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_135}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_137 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_136, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_135}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_130 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_137, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_137}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_135 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_130, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_136}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_135 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_137, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_137}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_137 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_135, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_137}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_137 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_137, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_135}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_137 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_137, decoded_addr_decoded_decoded_andMatrixOutputs_lo_137}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_117_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_137; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_61 = decoded_addr_decoded_decoded_andMatrixOutputs_117_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_121 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_134, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_131}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_136 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_121, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_121}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_134 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_136, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_136}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_137 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_134, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_136}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_138 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_137, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_136}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_131 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_138, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_138}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_136 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_131, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_137}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_136 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_138, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_138}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_138 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_136, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_138}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_138 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_138, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_136}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_138 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_138, decoded_addr_decoded_decoded_andMatrixOutputs_lo_138}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_46_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_138; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_58 = decoded_addr_decoded_decoded_andMatrixOutputs_46_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_122 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_135, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_132}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_137 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_122, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_122}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_135 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_137, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_137}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_138 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_135, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_137}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_139 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_138, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_137}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_132 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_139, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_139}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_137 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_132, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_138}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_137 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_139, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_139}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_139 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_137, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_139}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_139 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_139, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_137}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_139 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_139, decoded_addr_decoded_decoded_andMatrixOutputs_lo_139}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_15_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_139; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_55 = decoded_addr_decoded_decoded_andMatrixOutputs_15_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_123 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_136, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_133}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_138 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_123, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_123}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_136 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_138, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_138}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_139 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_136, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_138}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_140 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_139, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_138}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_133 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_140, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_140}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_138 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_133, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_139}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_138 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_140, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_140}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_140 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_138, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_140}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_140 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_140, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_138}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_140 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_140, decoded_addr_decoded_decoded_andMatrixOutputs_lo_140}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_51_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_140; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_52 = decoded_addr_decoded_decoded_andMatrixOutputs_51_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_124 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_137, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_134}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_139 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_124, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_124}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_137 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_139, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_139}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_140 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_137, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_139}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_141 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_140, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_139}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_134 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_141, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_141}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_139 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_134, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_140}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_139 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_141, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_141}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_141 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_139, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_141}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_141 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_141, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_139}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_141 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_141, decoded_addr_decoded_decoded_andMatrixOutputs_lo_141}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_43_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_141; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_49 = decoded_addr_decoded_decoded_andMatrixOutputs_43_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_125 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_138, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_135}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_140 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_125, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_125}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_138 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_140, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_140}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_141 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_138, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_140}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_142 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_141, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_140}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_135 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_142, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_142}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_140 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_135, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_141}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_140 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_142, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_142}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_142 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_140, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_142}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_142 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_142, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_140}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_142 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_142, decoded_addr_decoded_decoded_andMatrixOutputs_lo_142}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_70_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_142; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_46 = decoded_addr_decoded_decoded_andMatrixOutputs_70_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_126 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_139, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_136}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_141 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_126, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_126}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_139 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_141, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_141}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_142 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_139, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_141}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_143 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_142, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_141}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_136 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_143, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_143}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_141 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_136, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_142}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_141 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_143, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_143}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_143 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_141, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_143}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_143 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_143, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_141}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_143 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_143, decoded_addr_decoded_decoded_andMatrixOutputs_lo_143}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_78_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_143; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_43 = decoded_addr_decoded_decoded_andMatrixOutputs_78_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_127 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_140, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_137}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_142 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_127, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_127}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_140 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_142, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_142}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_143 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_140, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_142}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_144 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_143, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_142}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_137 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_144, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_144}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_142 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_137, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_143}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_142 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_144, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_144}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_144 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_142, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_144}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_144 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_144, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_142}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_144 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_144, decoded_addr_decoded_decoded_andMatrixOutputs_lo_144}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_110_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_144; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_40 = decoded_addr_decoded_decoded_andMatrixOutputs_110_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_143 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_141, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_138}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_141 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_143, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_143}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_144 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_141, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_143}; // @[pla.scala:90:45, :98:53] wire [4:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_145 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_144, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_143}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_138 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_145, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_145}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_143 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_138, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_144}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_143 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_145, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_145}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_145 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_143, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_145}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_145 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_145, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_143}; // @[pla.scala:98:53] wire [10:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_145 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_145, decoded_addr_decoded_decoded_andMatrixOutputs_lo_145}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_101_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_145; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_1 = decoded_addr_decoded_decoded_andMatrixOutputs_101_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_128 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_142, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_139}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_144 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_128, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_128}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_142 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_144, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_144}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_145 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_142, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_144}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_146 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_145, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_144}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_139 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_146, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_146}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_144 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_139, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_145}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_144 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_146, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_146}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_146 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_144, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_146}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_146 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_146, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_144}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_146 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_146, decoded_addr_decoded_decoded_andMatrixOutputs_lo_146}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_38_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_146; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_3 = decoded_addr_decoded_decoded_andMatrixOutputs_38_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_129 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_143, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_140}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_145 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_129, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_129}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_143 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_145, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_145}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_146 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_143, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_145}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_147 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_146, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_145}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_140 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_147, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_147}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_145 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_140, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_146}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_145 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_147, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_147}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_147 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_145, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_147}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_147 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_147, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_145}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_147 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_147, decoded_addr_decoded_decoded_andMatrixOutputs_lo_147}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_13_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_147; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_2 = decoded_addr_decoded_decoded_andMatrixOutputs_13_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_130 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_144, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_141}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_146 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_130, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_130}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_144 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_146, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_146}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_147 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_144, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_146}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_148 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_147, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_146}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_141 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_148, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_148}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_146 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_141, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_147}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_146 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_148, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_148}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_148 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_146, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_148}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_148 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_148, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_146}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_148 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_148, decoded_addr_decoded_decoded_andMatrixOutputs_lo_148}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_81_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_148; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_136 = decoded_addr_decoded_decoded_andMatrixOutputs_81_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_131 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_145, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_142}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_147 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_131, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_131}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_145 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_147, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_147}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_148 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_145, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_147}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_149 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_148, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_147}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_142 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_149, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_149}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_147 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_142, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_148}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_147 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_149, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_149}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_149 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_147, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_149}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_149 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_149, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_147}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_149 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_149, decoded_addr_decoded_decoded_andMatrixOutputs_lo_149}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_75_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_149; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T = decoded_addr_decoded_decoded_andMatrixOutputs_75_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo_lo_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_1, _decoded_addr_decoded_decoded_orMatrixOutputs_T}; // @[pla.scala:102:36, :114:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo_lo_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_3, _decoded_addr_decoded_decoded_orMatrixOutputs_T_2}; // @[pla.scala:102:36, :114:36] wire [3:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo_lo_lo}; // @[pla.scala:102:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo_hi_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_5, _decoded_addr_decoded_decoded_orMatrixOutputs_T_4}; // @[pla.scala:102:36, :114:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo_hi_hi_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_8, _decoded_addr_decoded_decoded_orMatrixOutputs_T_7}; // @[pla.scala:102:36, :114:36] wire [2:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_6}; // @[pla.scala:102:36, :114:36] wire [4:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo_hi_lo}; // @[pla.scala:102:36] wire [8:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo_lo}; // @[pla.scala:102:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi_lo_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_10, _decoded_addr_decoded_decoded_orMatrixOutputs_T_9}; // @[pla.scala:102:36, :114:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi_lo_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_12, _decoded_addr_decoded_decoded_orMatrixOutputs_T_11}; // @[pla.scala:102:36, :114:36] wire [3:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi_lo_lo}; // @[pla.scala:102:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi_hi_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_14, _decoded_addr_decoded_decoded_orMatrixOutputs_T_13}; // @[pla.scala:102:36, :114:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi_hi_hi_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_17, _decoded_addr_decoded_decoded_orMatrixOutputs_T_16}; // @[pla.scala:102:36, :114:36] wire [2:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_15}; // @[pla.scala:102:36, :114:36] wire [4:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi_hi_lo}; // @[pla.scala:102:36] wire [8:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi_lo}; // @[pla.scala:102:36] wire [17:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo}; // @[pla.scala:102:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo_lo_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_19, _decoded_addr_decoded_decoded_orMatrixOutputs_T_18}; // @[pla.scala:102:36, :114:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo_lo_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_21, _decoded_addr_decoded_decoded_orMatrixOutputs_T_20}; // @[pla.scala:102:36, :114:36] wire [3:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo_lo_lo}; // @[pla.scala:102:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo_hi_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_23, _decoded_addr_decoded_decoded_orMatrixOutputs_T_22}; // @[pla.scala:102:36, :114:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo_hi_hi_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_26, _decoded_addr_decoded_decoded_orMatrixOutputs_T_25}; // @[pla.scala:102:36, :114:36] wire [2:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_24}; // @[pla.scala:102:36, :114:36] wire [4:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo_hi_lo}; // @[pla.scala:102:36] wire [8:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo_lo}; // @[pla.scala:102:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_lo_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_28, _decoded_addr_decoded_decoded_orMatrixOutputs_T_27}; // @[pla.scala:102:36, :114:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_lo_hi_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_31, _decoded_addr_decoded_decoded_orMatrixOutputs_T_30}; // @[pla.scala:102:36, :114:36] wire [2:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_lo_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_lo_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_29}; // @[pla.scala:102:36, :114:36] wire [4:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_lo_lo}; // @[pla.scala:102:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_33, _decoded_addr_decoded_decoded_orMatrixOutputs_T_32}; // @[pla.scala:102:36, :114:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_hi_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_36, _decoded_addr_decoded_decoded_orMatrixOutputs_T_35}; // @[pla.scala:102:36, :114:36] wire [2:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_34}; // @[pla.scala:102:36, :114:36] wire [4:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_lo}; // @[pla.scala:102:36] wire [9:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_lo}; // @[pla.scala:102:36] wire [18:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo}; // @[pla.scala:102:36] wire [36:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo}; // @[pla.scala:102:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo_lo_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_38, _decoded_addr_decoded_decoded_orMatrixOutputs_T_37}; // @[pla.scala:102:36, :114:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo_lo_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_40, _decoded_addr_decoded_decoded_orMatrixOutputs_T_39}; // @[pla.scala:102:36, :114:36] wire [3:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo_lo_lo}; // @[pla.scala:102:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo_hi_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_42, _decoded_addr_decoded_decoded_orMatrixOutputs_T_41}; // @[pla.scala:102:36, :114:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo_hi_hi_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_45, _decoded_addr_decoded_decoded_orMatrixOutputs_T_44}; // @[pla.scala:102:36, :114:36] wire [2:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_43}; // @[pla.scala:102:36, :114:36] wire [4:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo_hi_lo}; // @[pla.scala:102:36] wire [8:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo_lo}; // @[pla.scala:102:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_lo_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_47, _decoded_addr_decoded_decoded_orMatrixOutputs_T_46}; // @[pla.scala:102:36, :114:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_lo_hi_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_50, _decoded_addr_decoded_decoded_orMatrixOutputs_T_49}; // @[pla.scala:102:36, :114:36] wire [2:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_lo_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_lo_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_48}; // @[pla.scala:102:36, :114:36] wire [4:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_lo_lo}; // @[pla.scala:102:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_52, _decoded_addr_decoded_decoded_orMatrixOutputs_T_51}; // @[pla.scala:102:36, :114:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_hi_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_55, _decoded_addr_decoded_decoded_orMatrixOutputs_T_54}; // @[pla.scala:102:36, :114:36] wire [2:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_53}; // @[pla.scala:102:36, :114:36] wire [4:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_lo}; // @[pla.scala:102:36] wire [9:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_lo}; // @[pla.scala:102:36] wire [18:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo}; // @[pla.scala:102:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo_lo_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_57, _decoded_addr_decoded_decoded_orMatrixOutputs_T_56}; // @[pla.scala:102:36, :114:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo_lo_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_59, _decoded_addr_decoded_decoded_orMatrixOutputs_T_58}; // @[pla.scala:102:36, :114:36] wire [3:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo_lo_lo}; // @[pla.scala:102:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo_hi_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_61, _decoded_addr_decoded_decoded_orMatrixOutputs_T_60}; // @[pla.scala:102:36, :114:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo_hi_hi_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_64, _decoded_addr_decoded_decoded_orMatrixOutputs_T_63}; // @[pla.scala:102:36, :114:36] wire [2:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_62}; // @[pla.scala:102:36, :114:36] wire [4:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo_hi_lo}; // @[pla.scala:102:36] wire [8:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo_lo}; // @[pla.scala:102:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_lo_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_66, _decoded_addr_decoded_decoded_orMatrixOutputs_T_65}; // @[pla.scala:102:36, :114:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_lo_hi_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_69, _decoded_addr_decoded_decoded_orMatrixOutputs_T_68}; // @[pla.scala:102:36, :114:36] wire [2:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_lo_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_lo_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_67}; // @[pla.scala:102:36, :114:36] wire [4:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_lo_lo}; // @[pla.scala:102:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_71, _decoded_addr_decoded_decoded_orMatrixOutputs_T_70}; // @[pla.scala:102:36, :114:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_hi_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_74, _decoded_addr_decoded_decoded_orMatrixOutputs_T_73}; // @[pla.scala:102:36, :114:36] wire [2:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_72}; // @[pla.scala:102:36, :114:36] wire [4:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_lo}; // @[pla.scala:102:36] wire [9:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_lo}; // @[pla.scala:102:36] wire [18:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo}; // @[pla.scala:102:36] wire [37:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo}; // @[pla.scala:102:36] wire [74:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo}; // @[pla.scala:102:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo_lo_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_76, _decoded_addr_decoded_decoded_orMatrixOutputs_T_75}; // @[pla.scala:102:36, :114:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo_lo_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_78, _decoded_addr_decoded_decoded_orMatrixOutputs_T_77}; // @[pla.scala:102:36, :114:36] wire [3:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo_lo_lo}; // @[pla.scala:102:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo_hi_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_80, _decoded_addr_decoded_decoded_orMatrixOutputs_T_79}; // @[pla.scala:102:36, :114:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo_hi_hi_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_83, _decoded_addr_decoded_decoded_orMatrixOutputs_T_82}; // @[pla.scala:102:36, :114:36] wire [2:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_81}; // @[pla.scala:102:36, :114:36] wire [4:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo_hi_lo}; // @[pla.scala:102:36] wire [8:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo_lo}; // @[pla.scala:102:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi_lo_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_85, _decoded_addr_decoded_decoded_orMatrixOutputs_T_84}; // @[pla.scala:102:36, :114:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi_lo_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_87, _decoded_addr_decoded_decoded_orMatrixOutputs_T_86}; // @[pla.scala:102:36, :114:36] wire [3:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi_lo_lo}; // @[pla.scala:102:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_89, _decoded_addr_decoded_decoded_orMatrixOutputs_T_88}; // @[pla.scala:102:36, :114:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_hi_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_92, _decoded_addr_decoded_decoded_orMatrixOutputs_T_91}; // @[pla.scala:102:36, :114:36] wire [2:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_90}; // @[pla.scala:102:36, :114:36] wire [4:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_lo}; // @[pla.scala:102:36] wire [8:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi_lo}; // @[pla.scala:102:36] wire [17:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo}; // @[pla.scala:102:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo_lo_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_94, _decoded_addr_decoded_decoded_orMatrixOutputs_T_93}; // @[pla.scala:102:36, :114:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo_lo_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_96, _decoded_addr_decoded_decoded_orMatrixOutputs_T_95}; // @[pla.scala:102:36, :114:36] wire [3:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo_lo_lo}; // @[pla.scala:102:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo_hi_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_98, _decoded_addr_decoded_decoded_orMatrixOutputs_T_97}; // @[pla.scala:102:36, :114:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo_hi_hi_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_101, _decoded_addr_decoded_decoded_orMatrixOutputs_T_100}; // @[pla.scala:102:36, :114:36] wire [2:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_99}; // @[pla.scala:102:36, :114:36] wire [4:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo_hi_lo}; // @[pla.scala:102:36] wire [8:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo_lo}; // @[pla.scala:102:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_lo_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_103, _decoded_addr_decoded_decoded_orMatrixOutputs_T_102}; // @[pla.scala:102:36, :114:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_lo_hi_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_106, _decoded_addr_decoded_decoded_orMatrixOutputs_T_105}; // @[pla.scala:102:36, :114:36] wire [2:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_lo_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_lo_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_104}; // @[pla.scala:102:36, :114:36] wire [4:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_lo_lo}; // @[pla.scala:102:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_108, _decoded_addr_decoded_decoded_orMatrixOutputs_T_107}; // @[pla.scala:102:36, :114:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_hi_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_111, _decoded_addr_decoded_decoded_orMatrixOutputs_T_110}; // @[pla.scala:102:36, :114:36] wire [2:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_109}; // @[pla.scala:102:36, :114:36] wire [4:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_lo}; // @[pla.scala:102:36] wire [9:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_lo}; // @[pla.scala:102:36] wire [18:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo}; // @[pla.scala:102:36] wire [36:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo}; // @[pla.scala:102:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo_lo_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_113, _decoded_addr_decoded_decoded_orMatrixOutputs_T_112}; // @[pla.scala:102:36, :114:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo_lo_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_115, _decoded_addr_decoded_decoded_orMatrixOutputs_T_114}; // @[pla.scala:102:36, :114:36] wire [3:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo_lo_lo}; // @[pla.scala:102:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo_hi_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_117, _decoded_addr_decoded_decoded_orMatrixOutputs_T_116}; // @[pla.scala:102:36, :114:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo_hi_hi_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_120, _decoded_addr_decoded_decoded_orMatrixOutputs_T_119}; // @[pla.scala:102:36, :114:36] wire [2:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_118}; // @[pla.scala:102:36, :114:36] wire [4:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo_hi_lo}; // @[pla.scala:102:36] wire [8:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo_lo}; // @[pla.scala:102:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_lo_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_122, _decoded_addr_decoded_decoded_orMatrixOutputs_T_121}; // @[pla.scala:102:36, :114:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_lo_hi_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_125, _decoded_addr_decoded_decoded_orMatrixOutputs_T_124}; // @[pla.scala:102:36, :114:36] wire [2:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_lo_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_lo_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_123}; // @[pla.scala:102:36, :114:36] wire [4:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_lo_lo}; // @[pla.scala:102:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_127, _decoded_addr_decoded_decoded_orMatrixOutputs_T_126}; // @[pla.scala:102:36, :114:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_hi_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_130, _decoded_addr_decoded_decoded_orMatrixOutputs_T_129}; // @[pla.scala:102:36, :114:36] wire [2:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_128}; // @[pla.scala:102:36, :114:36] wire [4:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_lo}; // @[pla.scala:102:36] wire [9:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_lo}; // @[pla.scala:102:36] wire [18:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo}; // @[pla.scala:102:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo_lo_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_132, _decoded_addr_decoded_decoded_orMatrixOutputs_T_131}; // @[pla.scala:102:36, :114:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo_lo_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_134, _decoded_addr_decoded_decoded_orMatrixOutputs_T_133}; // @[pla.scala:102:36, :114:36] wire [3:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo_lo_lo}; // @[pla.scala:102:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo_hi_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_136, _decoded_addr_decoded_decoded_orMatrixOutputs_T_135}; // @[pla.scala:102:36, :114:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo_hi_hi_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_139, _decoded_addr_decoded_decoded_orMatrixOutputs_T_138}; // @[pla.scala:102:36, :114:36] wire [2:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_137}; // @[pla.scala:102:36, :114:36] wire [4:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo_hi_lo}; // @[pla.scala:102:36] wire [8:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo_lo}; // @[pla.scala:102:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_lo_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_141, _decoded_addr_decoded_decoded_orMatrixOutputs_T_140}; // @[pla.scala:102:36, :114:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_lo_hi_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_144, _decoded_addr_decoded_decoded_orMatrixOutputs_T_143}; // @[pla.scala:102:36, :114:36] wire [2:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_lo_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_lo_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_142}; // @[pla.scala:102:36, :114:36] wire [4:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_lo_lo}; // @[pla.scala:102:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_146, _decoded_addr_decoded_decoded_orMatrixOutputs_T_145}; // @[pla.scala:102:36, :114:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_hi_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_149, _decoded_addr_decoded_decoded_orMatrixOutputs_T_148}; // @[pla.scala:102:36, :114:36] wire [2:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_147}; // @[pla.scala:102:36, :114:36] wire [4:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_lo}; // @[pla.scala:102:36] wire [9:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_lo}; // @[pla.scala:102:36] wire [18:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo}; // @[pla.scala:102:36] wire [37:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo}; // @[pla.scala:102:36] wire [74:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo}; // @[pla.scala:102:36] wire [149:0] decoded_addr_decoded_decoded_orMatrixOutputs = {decoded_addr_decoded_decoded_orMatrixOutputs_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo}; // @[pla.scala:102:36] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T = decoded_addr_decoded_decoded_orMatrixOutputs[0]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_1 = decoded_addr_decoded_decoded_orMatrixOutputs[1]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_2 = decoded_addr_decoded_decoded_orMatrixOutputs[2]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_3 = decoded_addr_decoded_decoded_orMatrixOutputs[3]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_4 = decoded_addr_decoded_decoded_orMatrixOutputs[4]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_5 = decoded_addr_decoded_decoded_orMatrixOutputs[5]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_6 = decoded_addr_decoded_decoded_orMatrixOutputs[6]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_7 = decoded_addr_decoded_decoded_orMatrixOutputs[7]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_8 = decoded_addr_decoded_decoded_orMatrixOutputs[8]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_9 = decoded_addr_decoded_decoded_orMatrixOutputs[9]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_10 = decoded_addr_decoded_decoded_orMatrixOutputs[10]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_11 = decoded_addr_decoded_decoded_orMatrixOutputs[11]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_12 = decoded_addr_decoded_decoded_orMatrixOutputs[12]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_13 = decoded_addr_decoded_decoded_orMatrixOutputs[13]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_14 = decoded_addr_decoded_decoded_orMatrixOutputs[14]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_15 = decoded_addr_decoded_decoded_orMatrixOutputs[15]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_16 = decoded_addr_decoded_decoded_orMatrixOutputs[16]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_17 = decoded_addr_decoded_decoded_orMatrixOutputs[17]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_18 = decoded_addr_decoded_decoded_orMatrixOutputs[18]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_19 = decoded_addr_decoded_decoded_orMatrixOutputs[19]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_20 = decoded_addr_decoded_decoded_orMatrixOutputs[20]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_21 = decoded_addr_decoded_decoded_orMatrixOutputs[21]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_22 = decoded_addr_decoded_decoded_orMatrixOutputs[22]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_23 = decoded_addr_decoded_decoded_orMatrixOutputs[23]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_24 = decoded_addr_decoded_decoded_orMatrixOutputs[24]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_25 = decoded_addr_decoded_decoded_orMatrixOutputs[25]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_26 = decoded_addr_decoded_decoded_orMatrixOutputs[26]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_27 = decoded_addr_decoded_decoded_orMatrixOutputs[27]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_28 = decoded_addr_decoded_decoded_orMatrixOutputs[28]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_29 = decoded_addr_decoded_decoded_orMatrixOutputs[29]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_30 = decoded_addr_decoded_decoded_orMatrixOutputs[30]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_31 = decoded_addr_decoded_decoded_orMatrixOutputs[31]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_32 = decoded_addr_decoded_decoded_orMatrixOutputs[32]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_33 = decoded_addr_decoded_decoded_orMatrixOutputs[33]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_34 = decoded_addr_decoded_decoded_orMatrixOutputs[34]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_35 = decoded_addr_decoded_decoded_orMatrixOutputs[35]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_36 = decoded_addr_decoded_decoded_orMatrixOutputs[36]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_37 = decoded_addr_decoded_decoded_orMatrixOutputs[37]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_38 = decoded_addr_decoded_decoded_orMatrixOutputs[38]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_39 = decoded_addr_decoded_decoded_orMatrixOutputs[39]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_40 = decoded_addr_decoded_decoded_orMatrixOutputs[40]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_41 = decoded_addr_decoded_decoded_orMatrixOutputs[41]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_42 = decoded_addr_decoded_decoded_orMatrixOutputs[42]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_43 = decoded_addr_decoded_decoded_orMatrixOutputs[43]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_44 = decoded_addr_decoded_decoded_orMatrixOutputs[44]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_45 = decoded_addr_decoded_decoded_orMatrixOutputs[45]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_46 = decoded_addr_decoded_decoded_orMatrixOutputs[46]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_47 = decoded_addr_decoded_decoded_orMatrixOutputs[47]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_48 = decoded_addr_decoded_decoded_orMatrixOutputs[48]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_49 = decoded_addr_decoded_decoded_orMatrixOutputs[49]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_50 = decoded_addr_decoded_decoded_orMatrixOutputs[50]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_51 = decoded_addr_decoded_decoded_orMatrixOutputs[51]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_52 = decoded_addr_decoded_decoded_orMatrixOutputs[52]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_53 = decoded_addr_decoded_decoded_orMatrixOutputs[53]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_54 = decoded_addr_decoded_decoded_orMatrixOutputs[54]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_55 = decoded_addr_decoded_decoded_orMatrixOutputs[55]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_56 = decoded_addr_decoded_decoded_orMatrixOutputs[56]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_57 = decoded_addr_decoded_decoded_orMatrixOutputs[57]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_58 = decoded_addr_decoded_decoded_orMatrixOutputs[58]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_59 = decoded_addr_decoded_decoded_orMatrixOutputs[59]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_60 = decoded_addr_decoded_decoded_orMatrixOutputs[60]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_61 = decoded_addr_decoded_decoded_orMatrixOutputs[61]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_62 = decoded_addr_decoded_decoded_orMatrixOutputs[62]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_63 = decoded_addr_decoded_decoded_orMatrixOutputs[63]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_64 = decoded_addr_decoded_decoded_orMatrixOutputs[64]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_65 = decoded_addr_decoded_decoded_orMatrixOutputs[65]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_66 = decoded_addr_decoded_decoded_orMatrixOutputs[66]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_67 = decoded_addr_decoded_decoded_orMatrixOutputs[67]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_68 = decoded_addr_decoded_decoded_orMatrixOutputs[68]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_69 = decoded_addr_decoded_decoded_orMatrixOutputs[69]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_70 = decoded_addr_decoded_decoded_orMatrixOutputs[70]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_71 = decoded_addr_decoded_decoded_orMatrixOutputs[71]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_72 = decoded_addr_decoded_decoded_orMatrixOutputs[72]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_73 = decoded_addr_decoded_decoded_orMatrixOutputs[73]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_74 = decoded_addr_decoded_decoded_orMatrixOutputs[74]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_75 = decoded_addr_decoded_decoded_orMatrixOutputs[75]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_76 = decoded_addr_decoded_decoded_orMatrixOutputs[76]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_77 = decoded_addr_decoded_decoded_orMatrixOutputs[77]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_78 = decoded_addr_decoded_decoded_orMatrixOutputs[78]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_79 = decoded_addr_decoded_decoded_orMatrixOutputs[79]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_80 = decoded_addr_decoded_decoded_orMatrixOutputs[80]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_81 = decoded_addr_decoded_decoded_orMatrixOutputs[81]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_82 = decoded_addr_decoded_decoded_orMatrixOutputs[82]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_83 = decoded_addr_decoded_decoded_orMatrixOutputs[83]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_84 = decoded_addr_decoded_decoded_orMatrixOutputs[84]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_85 = decoded_addr_decoded_decoded_orMatrixOutputs[85]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_86 = decoded_addr_decoded_decoded_orMatrixOutputs[86]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_87 = decoded_addr_decoded_decoded_orMatrixOutputs[87]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_88 = decoded_addr_decoded_decoded_orMatrixOutputs[88]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_89 = decoded_addr_decoded_decoded_orMatrixOutputs[89]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_90 = decoded_addr_decoded_decoded_orMatrixOutputs[90]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_91 = decoded_addr_decoded_decoded_orMatrixOutputs[91]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_92 = decoded_addr_decoded_decoded_orMatrixOutputs[92]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_93 = decoded_addr_decoded_decoded_orMatrixOutputs[93]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_94 = decoded_addr_decoded_decoded_orMatrixOutputs[94]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_95 = decoded_addr_decoded_decoded_orMatrixOutputs[95]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_96 = decoded_addr_decoded_decoded_orMatrixOutputs[96]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_97 = decoded_addr_decoded_decoded_orMatrixOutputs[97]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_98 = decoded_addr_decoded_decoded_orMatrixOutputs[98]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_99 = decoded_addr_decoded_decoded_orMatrixOutputs[99]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_100 = decoded_addr_decoded_decoded_orMatrixOutputs[100]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_101 = decoded_addr_decoded_decoded_orMatrixOutputs[101]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_102 = decoded_addr_decoded_decoded_orMatrixOutputs[102]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_103 = decoded_addr_decoded_decoded_orMatrixOutputs[103]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_104 = decoded_addr_decoded_decoded_orMatrixOutputs[104]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_105 = decoded_addr_decoded_decoded_orMatrixOutputs[105]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_106 = decoded_addr_decoded_decoded_orMatrixOutputs[106]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_107 = decoded_addr_decoded_decoded_orMatrixOutputs[107]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_108 = decoded_addr_decoded_decoded_orMatrixOutputs[108]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_109 = decoded_addr_decoded_decoded_orMatrixOutputs[109]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_110 = decoded_addr_decoded_decoded_orMatrixOutputs[110]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_111 = decoded_addr_decoded_decoded_orMatrixOutputs[111]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_112 = decoded_addr_decoded_decoded_orMatrixOutputs[112]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_113 = decoded_addr_decoded_decoded_orMatrixOutputs[113]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_114 = decoded_addr_decoded_decoded_orMatrixOutputs[114]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_115 = decoded_addr_decoded_decoded_orMatrixOutputs[115]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_116 = decoded_addr_decoded_decoded_orMatrixOutputs[116]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_117 = decoded_addr_decoded_decoded_orMatrixOutputs[117]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_118 = decoded_addr_decoded_decoded_orMatrixOutputs[118]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_119 = decoded_addr_decoded_decoded_orMatrixOutputs[119]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_120 = decoded_addr_decoded_decoded_orMatrixOutputs[120]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_121 = decoded_addr_decoded_decoded_orMatrixOutputs[121]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_122 = decoded_addr_decoded_decoded_orMatrixOutputs[122]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_123 = decoded_addr_decoded_decoded_orMatrixOutputs[123]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_124 = decoded_addr_decoded_decoded_orMatrixOutputs[124]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_125 = decoded_addr_decoded_decoded_orMatrixOutputs[125]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_126 = decoded_addr_decoded_decoded_orMatrixOutputs[126]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_127 = decoded_addr_decoded_decoded_orMatrixOutputs[127]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_128 = decoded_addr_decoded_decoded_orMatrixOutputs[128]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_129 = decoded_addr_decoded_decoded_orMatrixOutputs[129]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_130 = decoded_addr_decoded_decoded_orMatrixOutputs[130]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_131 = decoded_addr_decoded_decoded_orMatrixOutputs[131]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_132 = decoded_addr_decoded_decoded_orMatrixOutputs[132]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_133 = decoded_addr_decoded_decoded_orMatrixOutputs[133]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_134 = decoded_addr_decoded_decoded_orMatrixOutputs[134]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_135 = decoded_addr_decoded_decoded_orMatrixOutputs[135]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_136 = decoded_addr_decoded_decoded_orMatrixOutputs[136]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_137 = decoded_addr_decoded_decoded_orMatrixOutputs[137]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_138 = decoded_addr_decoded_decoded_orMatrixOutputs[138]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_139 = decoded_addr_decoded_decoded_orMatrixOutputs[139]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_140 = decoded_addr_decoded_decoded_orMatrixOutputs[140]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_141 = decoded_addr_decoded_decoded_orMatrixOutputs[141]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_142 = decoded_addr_decoded_decoded_orMatrixOutputs[142]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_143 = decoded_addr_decoded_decoded_orMatrixOutputs[143]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_144 = decoded_addr_decoded_decoded_orMatrixOutputs[144]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_145 = decoded_addr_decoded_decoded_orMatrixOutputs[145]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_146 = decoded_addr_decoded_decoded_orMatrixOutputs[146]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_147 = decoded_addr_decoded_decoded_orMatrixOutputs[147]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_148 = decoded_addr_decoded_decoded_orMatrixOutputs[148]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_149 = decoded_addr_decoded_decoded_orMatrixOutputs[149]; // @[pla.scala:102:36, :124:31] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo_lo_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_1, _decoded_addr_decoded_decoded_invMatrixOutputs_T}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo_lo_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_3, _decoded_addr_decoded_decoded_invMatrixOutputs_T_2}; // @[pla.scala:120:37, :124:31] wire [3:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo_lo_lo}; // @[pla.scala:120:37] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo_hi_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_5, _decoded_addr_decoded_decoded_invMatrixOutputs_T_4}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo_hi_hi_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_8, _decoded_addr_decoded_decoded_invMatrixOutputs_T_7}; // @[pla.scala:120:37, :124:31] wire [2:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_6}; // @[pla.scala:120:37, :124:31] wire [4:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo_hi_lo}; // @[pla.scala:120:37] wire [8:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo_lo}; // @[pla.scala:120:37] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi_lo_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_10, _decoded_addr_decoded_decoded_invMatrixOutputs_T_9}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi_lo_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_12, _decoded_addr_decoded_decoded_invMatrixOutputs_T_11}; // @[pla.scala:120:37, :124:31] wire [3:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi_lo_lo}; // @[pla.scala:120:37] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi_hi_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_14, _decoded_addr_decoded_decoded_invMatrixOutputs_T_13}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi_hi_hi_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_17, _decoded_addr_decoded_decoded_invMatrixOutputs_T_16}; // @[pla.scala:120:37, :124:31] wire [2:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_15}; // @[pla.scala:120:37, :124:31] wire [4:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi_hi_lo}; // @[pla.scala:120:37] wire [8:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi_lo}; // @[pla.scala:120:37] wire [17:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo}; // @[pla.scala:120:37] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo_lo_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_19, _decoded_addr_decoded_decoded_invMatrixOutputs_T_18}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo_lo_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_21, _decoded_addr_decoded_decoded_invMatrixOutputs_T_20}; // @[pla.scala:120:37, :124:31] wire [3:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo_lo_lo}; // @[pla.scala:120:37] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo_hi_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_23, _decoded_addr_decoded_decoded_invMatrixOutputs_T_22}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo_hi_hi_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_26, _decoded_addr_decoded_decoded_invMatrixOutputs_T_25}; // @[pla.scala:120:37, :124:31] wire [2:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_24}; // @[pla.scala:120:37, :124:31] wire [4:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo_hi_lo}; // @[pla.scala:120:37] wire [8:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo_lo}; // @[pla.scala:120:37] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_lo_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_28, _decoded_addr_decoded_decoded_invMatrixOutputs_T_27}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_lo_hi_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_31, _decoded_addr_decoded_decoded_invMatrixOutputs_T_30}; // @[pla.scala:120:37, :124:31] wire [2:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_lo_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_lo_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_29}; // @[pla.scala:120:37, :124:31] wire [4:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_lo_lo}; // @[pla.scala:120:37] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_hi_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_33, _decoded_addr_decoded_decoded_invMatrixOutputs_T_32}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_hi_hi_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_36, _decoded_addr_decoded_decoded_invMatrixOutputs_T_35}; // @[pla.scala:120:37, :124:31] wire [2:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_34}; // @[pla.scala:120:37, :124:31] wire [4:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_hi_lo}; // @[pla.scala:120:37] wire [9:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_lo}; // @[pla.scala:120:37] wire [18:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo}; // @[pla.scala:120:37] wire [36:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo}; // @[pla.scala:120:37] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo_lo_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_38, _decoded_addr_decoded_decoded_invMatrixOutputs_T_37}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo_lo_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_40, _decoded_addr_decoded_decoded_invMatrixOutputs_T_39}; // @[pla.scala:120:37, :124:31] wire [3:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo_lo_lo}; // @[pla.scala:120:37] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo_hi_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_42, _decoded_addr_decoded_decoded_invMatrixOutputs_T_41}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo_hi_hi_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_45, _decoded_addr_decoded_decoded_invMatrixOutputs_T_44}; // @[pla.scala:120:37, :124:31] wire [2:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_43}; // @[pla.scala:120:37, :124:31] wire [4:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo_hi_lo}; // @[pla.scala:120:37] wire [8:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo_lo}; // @[pla.scala:120:37] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_lo_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_47, _decoded_addr_decoded_decoded_invMatrixOutputs_T_46}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_lo_hi_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_50, _decoded_addr_decoded_decoded_invMatrixOutputs_T_49}; // @[pla.scala:120:37, :124:31] wire [2:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_lo_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_lo_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_48}; // @[pla.scala:120:37, :124:31] wire [4:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_lo_lo}; // @[pla.scala:120:37] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_hi_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_52, _decoded_addr_decoded_decoded_invMatrixOutputs_T_51}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_hi_hi_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_55, _decoded_addr_decoded_decoded_invMatrixOutputs_T_54}; // @[pla.scala:120:37, :124:31] wire [2:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_53}; // @[pla.scala:120:37, :124:31] wire [4:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_hi_lo}; // @[pla.scala:120:37] wire [9:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_lo}; // @[pla.scala:120:37] wire [18:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo}; // @[pla.scala:120:37] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo_lo_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_57, _decoded_addr_decoded_decoded_invMatrixOutputs_T_56}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo_lo_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_59, _decoded_addr_decoded_decoded_invMatrixOutputs_T_58}; // @[pla.scala:120:37, :124:31] wire [3:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo_lo_lo}; // @[pla.scala:120:37] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo_hi_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_61, _decoded_addr_decoded_decoded_invMatrixOutputs_T_60}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo_hi_hi_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_64, _decoded_addr_decoded_decoded_invMatrixOutputs_T_63}; // @[pla.scala:120:37, :124:31] wire [2:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_62}; // @[pla.scala:120:37, :124:31] wire [4:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo_hi_lo}; // @[pla.scala:120:37] wire [8:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo_lo}; // @[pla.scala:120:37] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_lo_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_66, _decoded_addr_decoded_decoded_invMatrixOutputs_T_65}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_lo_hi_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_69, _decoded_addr_decoded_decoded_invMatrixOutputs_T_68}; // @[pla.scala:120:37, :124:31] wire [2:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_lo_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_lo_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_67}; // @[pla.scala:120:37, :124:31] wire [4:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_lo_lo}; // @[pla.scala:120:37] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_hi_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_71, _decoded_addr_decoded_decoded_invMatrixOutputs_T_70}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_hi_hi_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_74, _decoded_addr_decoded_decoded_invMatrixOutputs_T_73}; // @[pla.scala:120:37, :124:31] wire [2:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_72}; // @[pla.scala:120:37, :124:31] wire [4:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_hi_lo}; // @[pla.scala:120:37] wire [9:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_lo}; // @[pla.scala:120:37] wire [18:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo}; // @[pla.scala:120:37] wire [37:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo}; // @[pla.scala:120:37] wire [74:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo}; // @[pla.scala:120:37] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo_lo_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_76, _decoded_addr_decoded_decoded_invMatrixOutputs_T_75}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo_lo_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_78, _decoded_addr_decoded_decoded_invMatrixOutputs_T_77}; // @[pla.scala:120:37, :124:31] wire [3:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo_lo_lo}; // @[pla.scala:120:37] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo_hi_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_80, _decoded_addr_decoded_decoded_invMatrixOutputs_T_79}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo_hi_hi_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_83, _decoded_addr_decoded_decoded_invMatrixOutputs_T_82}; // @[pla.scala:120:37, :124:31] wire [2:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_81}; // @[pla.scala:120:37, :124:31] wire [4:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo_hi_lo}; // @[pla.scala:120:37] wire [8:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo_lo}; // @[pla.scala:120:37] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi_lo_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_85, _decoded_addr_decoded_decoded_invMatrixOutputs_T_84}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi_lo_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_87, _decoded_addr_decoded_decoded_invMatrixOutputs_T_86}; // @[pla.scala:120:37, :124:31] wire [3:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi_lo_lo}; // @[pla.scala:120:37] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi_hi_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_89, _decoded_addr_decoded_decoded_invMatrixOutputs_T_88}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi_hi_hi_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_92, _decoded_addr_decoded_decoded_invMatrixOutputs_T_91}; // @[pla.scala:120:37, :124:31] wire [2:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_90}; // @[pla.scala:120:37, :124:31] wire [4:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi_hi_lo}; // @[pla.scala:120:37] wire [8:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi_lo}; // @[pla.scala:120:37] wire [17:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo}; // @[pla.scala:120:37] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo_lo_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_94, _decoded_addr_decoded_decoded_invMatrixOutputs_T_93}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo_lo_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_96, _decoded_addr_decoded_decoded_invMatrixOutputs_T_95}; // @[pla.scala:120:37, :124:31] wire [3:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo_lo_lo}; // @[pla.scala:120:37] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo_hi_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_98, _decoded_addr_decoded_decoded_invMatrixOutputs_T_97}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo_hi_hi_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_101, _decoded_addr_decoded_decoded_invMatrixOutputs_T_100}; // @[pla.scala:120:37, :124:31] wire [2:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_99}; // @[pla.scala:120:37, :124:31] wire [4:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo_hi_lo}; // @[pla.scala:120:37] wire [8:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo_lo}; // @[pla.scala:120:37] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_lo_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_103, _decoded_addr_decoded_decoded_invMatrixOutputs_T_102}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_lo_hi_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_106, _decoded_addr_decoded_decoded_invMatrixOutputs_T_105}; // @[pla.scala:120:37, :124:31] wire [2:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_lo_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_lo_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_104}; // @[pla.scala:120:37, :124:31] wire [4:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_lo_lo}; // @[pla.scala:120:37] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_hi_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_108, _decoded_addr_decoded_decoded_invMatrixOutputs_T_107}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_hi_hi_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_111, _decoded_addr_decoded_decoded_invMatrixOutputs_T_110}; // @[pla.scala:120:37, :124:31] wire [2:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_109}; // @[pla.scala:120:37, :124:31] wire [4:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_hi_lo}; // @[pla.scala:120:37] wire [9:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_lo}; // @[pla.scala:120:37] wire [18:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo}; // @[pla.scala:120:37] wire [36:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo}; // @[pla.scala:120:37] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo_lo_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_113, _decoded_addr_decoded_decoded_invMatrixOutputs_T_112}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo_lo_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_115, _decoded_addr_decoded_decoded_invMatrixOutputs_T_114}; // @[pla.scala:120:37, :124:31] wire [3:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo_lo_lo}; // @[pla.scala:120:37] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo_hi_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_117, _decoded_addr_decoded_decoded_invMatrixOutputs_T_116}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo_hi_hi_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_120, _decoded_addr_decoded_decoded_invMatrixOutputs_T_119}; // @[pla.scala:120:37, :124:31] wire [2:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_118}; // @[pla.scala:120:37, :124:31] wire [4:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo_hi_lo}; // @[pla.scala:120:37] wire [8:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo_lo}; // @[pla.scala:120:37] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_lo_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_122, _decoded_addr_decoded_decoded_invMatrixOutputs_T_121}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_lo_hi_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_125, _decoded_addr_decoded_decoded_invMatrixOutputs_T_124}; // @[pla.scala:120:37, :124:31] wire [2:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_lo_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_lo_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_123}; // @[pla.scala:120:37, :124:31] wire [4:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_lo_lo}; // @[pla.scala:120:37] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_hi_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_127, _decoded_addr_decoded_decoded_invMatrixOutputs_T_126}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_hi_hi_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_130, _decoded_addr_decoded_decoded_invMatrixOutputs_T_129}; // @[pla.scala:120:37, :124:31] wire [2:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_128}; // @[pla.scala:120:37, :124:31] wire [4:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_hi_lo}; // @[pla.scala:120:37] wire [9:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_lo}; // @[pla.scala:120:37] wire [18:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo}; // @[pla.scala:120:37] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo_lo_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_132, _decoded_addr_decoded_decoded_invMatrixOutputs_T_131}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo_lo_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_134, _decoded_addr_decoded_decoded_invMatrixOutputs_T_133}; // @[pla.scala:120:37, :124:31] wire [3:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo_lo_lo}; // @[pla.scala:120:37] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo_hi_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_136, _decoded_addr_decoded_decoded_invMatrixOutputs_T_135}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo_hi_hi_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_139, _decoded_addr_decoded_decoded_invMatrixOutputs_T_138}; // @[pla.scala:120:37, :124:31] wire [2:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_137}; // @[pla.scala:120:37, :124:31] wire [4:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo_hi_lo}; // @[pla.scala:120:37] wire [8:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo_lo}; // @[pla.scala:120:37] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_lo_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_141, _decoded_addr_decoded_decoded_invMatrixOutputs_T_140}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_lo_hi_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_144, _decoded_addr_decoded_decoded_invMatrixOutputs_T_143}; // @[pla.scala:120:37, :124:31] wire [2:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_lo_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_lo_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_142}; // @[pla.scala:120:37, :124:31] wire [4:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_lo_lo}; // @[pla.scala:120:37] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_hi_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_146, _decoded_addr_decoded_decoded_invMatrixOutputs_T_145}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_hi_hi_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_149, _decoded_addr_decoded_decoded_invMatrixOutputs_T_148}; // @[pla.scala:120:37, :124:31] wire [2:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_147}; // @[pla.scala:120:37, :124:31] wire [4:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_hi_lo}; // @[pla.scala:120:37] wire [9:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_lo}; // @[pla.scala:120:37] wire [18:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo}; // @[pla.scala:120:37] wire [37:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo}; // @[pla.scala:120:37] wire [74:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo}; // @[pla.scala:120:37] assign decoded_addr_decoded_decoded_invMatrixOutputs = {decoded_addr_decoded_decoded_invMatrixOutputs_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo}; // @[pla.scala:120:37] assign decoded_addr_decoded_decoded = decoded_addr_decoded_decoded_invMatrixOutputs; // @[pla.scala:81:23, :120:37] assign decoded_addr_decoded_decoded_plaInput = decoded_addr_addr[11:0]; // @[pla.scala:77:22] wire decoded_addr_decoded_0 = decoded_addr_decoded_decoded[149]; // @[pla.scala:81:23] wire decoded_addr_97_2 = decoded_addr_decoded_0; // @[Decode.scala:50:77] wire decoded_addr_decoded_1 = decoded_addr_decoded_decoded[148]; // @[pla.scala:81:23] wire decoded_addr_55_2 = decoded_addr_decoded_1; // @[Decode.scala:50:77] wire decoded_addr_decoded_2 = decoded_addr_decoded_decoded[147]; // @[pla.scala:81:23] wire decoded_addr_10_2 = decoded_addr_decoded_2; // @[Decode.scala:50:77] wire decoded_addr_decoded_3 = decoded_addr_decoded_decoded[146]; // @[pla.scala:81:23] wire decoded_addr_118_2 = decoded_addr_decoded_3; // @[Decode.scala:50:77] wire decoded_addr_decoded_4 = decoded_addr_decoded_decoded[145]; // @[pla.scala:81:23] wire decoded_addr_94_2 = decoded_addr_decoded_4; // @[Decode.scala:50:77] wire decoded_addr_decoded_5 = decoded_addr_decoded_decoded[144]; // @[pla.scala:81:23] wire decoded_addr_100_2 = decoded_addr_decoded_5; // @[Decode.scala:50:77] wire decoded_addr_decoded_6 = decoded_addr_decoded_decoded[143]; // @[pla.scala:81:23] wire decoded_addr_72_2 = decoded_addr_decoded_6; // @[Decode.scala:50:77] wire decoded_addr_decoded_7 = decoded_addr_decoded_decoded[142]; // @[pla.scala:81:23] wire decoded_addr_108_2 = decoded_addr_decoded_7; // @[Decode.scala:50:77] wire decoded_addr_decoded_8 = decoded_addr_decoded_decoded[141]; // @[pla.scala:81:23] wire decoded_addr_76_2 = decoded_addr_decoded_8; // @[Decode.scala:50:77] wire decoded_addr_decoded_9 = decoded_addr_decoded_decoded[140]; // @[pla.scala:81:23] wire decoded_addr_129_2 = decoded_addr_decoded_9; // @[Decode.scala:50:77] wire decoded_addr_decoded_10 = decoded_addr_decoded_decoded[139]; // @[pla.scala:81:23] wire decoded_addr_132_2 = decoded_addr_decoded_10; // @[Decode.scala:50:77] wire decoded_addr_decoded_11 = decoded_addr_decoded_decoded[138]; // @[pla.scala:81:23] wire decoded_addr_136_2 = decoded_addr_decoded_11; // @[Decode.scala:50:77] wire decoded_addr_decoded_12 = decoded_addr_decoded_decoded[137]; // @[pla.scala:81:23] wire decoded_addr_29_2 = decoded_addr_decoded_12; // @[Decode.scala:50:77] wire decoded_addr_decoded_13 = decoded_addr_decoded_decoded[136]; // @[pla.scala:81:23] wire decoded_addr_131_2 = decoded_addr_decoded_13; // @[Decode.scala:50:77] wire decoded_addr_decoded_14 = decoded_addr_decoded_decoded[135]; // @[pla.scala:81:23] wire decoded_addr_49_2 = decoded_addr_decoded_14; // @[Decode.scala:50:77] wire decoded_addr_decoded_15 = decoded_addr_decoded_decoded[134]; // @[pla.scala:81:23] wire decoded_addr_89_2 = decoded_addr_decoded_15; // @[Decode.scala:50:77] wire decoded_addr_decoded_16 = decoded_addr_decoded_decoded[133]; // @[pla.scala:81:23] wire decoded_addr_57_2 = decoded_addr_decoded_16; // @[Decode.scala:50:77] wire decoded_addr_decoded_17 = decoded_addr_decoded_decoded[132]; // @[pla.scala:81:23] wire decoded_addr_36_2 = decoded_addr_decoded_17; // @[Decode.scala:50:77] wire decoded_addr_decoded_18 = decoded_addr_decoded_decoded[131]; // @[pla.scala:81:23] wire decoded_addr_68_2 = decoded_addr_decoded_18; // @[Decode.scala:50:77] wire decoded_addr_decoded_19 = decoded_addr_decoded_decoded[130]; // @[pla.scala:81:23] wire decoded_addr_99_2 = decoded_addr_decoded_19; // @[Decode.scala:50:77] wire decoded_addr_decoded_20 = decoded_addr_decoded_decoded[129]; // @[pla.scala:81:23] wire decoded_addr_130_2 = decoded_addr_decoded_20; // @[Decode.scala:50:77] wire decoded_addr_decoded_21 = decoded_addr_decoded_decoded[128]; // @[pla.scala:81:23] wire decoded_addr_103_2 = decoded_addr_decoded_21; // @[Decode.scala:50:77] wire decoded_addr_decoded_22 = decoded_addr_decoded_decoded[127]; // @[pla.scala:81:23] wire decoded_addr_121_2 = decoded_addr_decoded_22; // @[Decode.scala:50:77] wire decoded_addr_decoded_23 = decoded_addr_decoded_decoded[126]; // @[pla.scala:81:23] wire decoded_addr_146_2 = decoded_addr_decoded_23; // @[Decode.scala:50:77] wire decoded_addr_decoded_24 = decoded_addr_decoded_decoded[125]; // @[pla.scala:81:23] wire decoded_addr_17_2 = decoded_addr_decoded_24; // @[Decode.scala:50:77] wire decoded_addr_decoded_25 = decoded_addr_decoded_decoded[124]; // @[pla.scala:81:23] wire decoded_addr_27_2 = decoded_addr_decoded_25; // @[Decode.scala:50:77] wire decoded_addr_decoded_26 = decoded_addr_decoded_decoded[123]; // @[pla.scala:81:23] wire decoded_addr_83_2 = decoded_addr_decoded_26; // @[Decode.scala:50:77] wire decoded_addr_decoded_27 = decoded_addr_decoded_decoded[122]; // @[pla.scala:81:23] wire decoded_addr_52_2 = decoded_addr_decoded_27; // @[Decode.scala:50:77] wire decoded_addr_decoded_28 = decoded_addr_decoded_decoded[121]; // @[pla.scala:81:23] wire decoded_addr_144_2 = decoded_addr_decoded_28; // @[Decode.scala:50:77] wire decoded_addr_decoded_29 = decoded_addr_decoded_decoded[120]; // @[pla.scala:81:23] wire decoded_addr_70_2 = decoded_addr_decoded_29; // @[Decode.scala:50:77] wire decoded_addr_decoded_30 = decoded_addr_decoded_decoded[119]; // @[pla.scala:81:23] wire decoded_addr_111_2 = decoded_addr_decoded_30; // @[Decode.scala:50:77] wire decoded_addr_decoded_31 = decoded_addr_decoded_decoded[118]; // @[pla.scala:81:23] wire decoded_addr_82_2 = decoded_addr_decoded_31; // @[Decode.scala:50:77] wire decoded_addr_decoded_32 = decoded_addr_decoded_decoded[117]; // @[pla.scala:81:23] wire decoded_addr_31_2 = decoded_addr_decoded_32; // @[Decode.scala:50:77] wire decoded_addr_decoded_33 = decoded_addr_decoded_decoded[116]; // @[pla.scala:81:23] wire decoded_addr_0_2 = decoded_addr_decoded_33; // @[Decode.scala:50:77] wire decoded_addr_decoded_34 = decoded_addr_decoded_decoded[115]; // @[pla.scala:81:23] wire decoded_addr_59_2 = decoded_addr_decoded_34; // @[Decode.scala:50:77] wire decoded_addr_decoded_35 = decoded_addr_decoded_decoded[114]; // @[pla.scala:81:23] wire decoded_addr_138_2 = decoded_addr_decoded_35; // @[Decode.scala:50:77] wire decoded_addr_decoded_36 = decoded_addr_decoded_decoded[113]; // @[pla.scala:81:23] wire decoded_addr_126_2 = decoded_addr_decoded_36; // @[Decode.scala:50:77] wire decoded_addr_decoded_37 = decoded_addr_decoded_decoded[112]; // @[pla.scala:81:23] wire decoded_addr_74_2 = decoded_addr_decoded_37; // @[Decode.scala:50:77] wire decoded_addr_decoded_38 = decoded_addr_decoded_decoded[111]; // @[pla.scala:81:23] wire decoded_addr_116_2 = decoded_addr_decoded_38; // @[Decode.scala:50:77] wire decoded_addr_decoded_39 = decoded_addr_decoded_decoded[110]; // @[pla.scala:81:23] wire decoded_addr_90_2 = decoded_addr_decoded_39; // @[Decode.scala:50:77] wire decoded_addr_decoded_40 = decoded_addr_decoded_decoded[109]; // @[pla.scala:81:23] wire decoded_addr_113_2 = decoded_addr_decoded_40; // @[Decode.scala:50:77] wire decoded_addr_decoded_41 = decoded_addr_decoded_decoded[108]; // @[pla.scala:81:23] wire decoded_addr_1_2 = decoded_addr_decoded_41; // @[Decode.scala:50:77] wire decoded_addr_decoded_42 = decoded_addr_decoded_decoded[107]; // @[pla.scala:81:23] wire decoded_addr_16_2 = decoded_addr_decoded_42; // @[Decode.scala:50:77] wire decoded_addr_decoded_43 = decoded_addr_decoded_decoded[106]; // @[pla.scala:81:23] wire decoded_addr_78_2 = decoded_addr_decoded_43; // @[Decode.scala:50:77] wire decoded_addr_decoded_44 = decoded_addr_decoded_decoded[105]; // @[pla.scala:81:23] wire decoded_addr_39_2 = decoded_addr_decoded_44; // @[Decode.scala:50:77] wire decoded_addr_decoded_45 = decoded_addr_decoded_decoded[104]; // @[pla.scala:81:23] wire decoded_addr_51_2 = decoded_addr_decoded_45; // @[Decode.scala:50:77] wire decoded_addr_decoded_46 = decoded_addr_decoded_decoded[103]; // @[pla.scala:81:23] wire decoded_addr_109_2 = decoded_addr_decoded_46; // @[Decode.scala:50:77] wire decoded_addr_decoded_47 = decoded_addr_decoded_decoded[102]; // @[pla.scala:81:23] wire decoded_addr_91_2 = decoded_addr_decoded_47; // @[Decode.scala:50:77] wire decoded_addr_decoded_48 = decoded_addr_decoded_decoded[101]; // @[pla.scala:81:23] wire decoded_addr_81_2 = decoded_addr_decoded_48; // @[Decode.scala:50:77] wire decoded_addr_decoded_49 = decoded_addr_decoded_decoded[100]; // @[pla.scala:81:23] wire decoded_addr_67_2 = decoded_addr_decoded_49; // @[Decode.scala:50:77] wire decoded_addr_decoded_50 = decoded_addr_decoded_decoded[99]; // @[pla.scala:81:23] wire decoded_addr_105_2 = decoded_addr_decoded_50; // @[Decode.scala:50:77] wire decoded_addr_decoded_51 = decoded_addr_decoded_decoded[98]; // @[pla.scala:81:23] wire decoded_addr_122_2 = decoded_addr_decoded_51; // @[Decode.scala:50:77] wire decoded_addr_decoded_52 = decoded_addr_decoded_decoded[97]; // @[pla.scala:81:23] wire decoded_addr_24_2 = decoded_addr_decoded_52; // @[Decode.scala:50:77] wire decoded_addr_decoded_53 = decoded_addr_decoded_decoded[96]; // @[pla.scala:81:23] wire decoded_addr_124_2 = decoded_addr_decoded_53; // @[Decode.scala:50:77] wire decoded_addr_decoded_54 = decoded_addr_decoded_decoded[95]; // @[pla.scala:81:23] wire decoded_addr_26_2 = decoded_addr_decoded_54; // @[Decode.scala:50:77] wire decoded_addr_decoded_55 = decoded_addr_decoded_decoded[94]; // @[pla.scala:81:23] wire decoded_addr_128_2 = decoded_addr_decoded_55; // @[Decode.scala:50:77] wire decoded_addr_decoded_56 = decoded_addr_decoded_decoded[93]; // @[pla.scala:81:23] wire decoded_addr_7_2 = decoded_addr_decoded_56; // @[Decode.scala:50:77] wire decoded_addr_decoded_57 = decoded_addr_decoded_decoded[92]; // @[pla.scala:81:23] wire decoded_addr_62_2 = decoded_addr_decoded_57; // @[Decode.scala:50:77] wire decoded_addr_decoded_58 = decoded_addr_decoded_decoded[91]; // @[pla.scala:81:23] wire decoded_addr_77_2 = decoded_addr_decoded_58; // @[Decode.scala:50:77] wire decoded_addr_decoded_59 = decoded_addr_decoded_decoded[90]; // @[pla.scala:81:23] wire decoded_addr_46_2 = decoded_addr_decoded_59; // @[Decode.scala:50:77] wire decoded_addr_decoded_60 = decoded_addr_decoded_decoded[89]; // @[pla.scala:81:23] wire decoded_addr_112_2 = decoded_addr_decoded_60; // @[Decode.scala:50:77] wire decoded_addr_decoded_61 = decoded_addr_decoded_decoded[88]; // @[pla.scala:81:23] wire decoded_addr_60_2 = decoded_addr_decoded_61; // @[Decode.scala:50:77] wire decoded_addr_decoded_62 = decoded_addr_decoded_decoded[87]; // @[pla.scala:81:23] wire decoded_addr_92_2 = decoded_addr_decoded_62; // @[Decode.scala:50:77] wire decoded_addr_decoded_63 = decoded_addr_decoded_decoded[86]; // @[pla.scala:81:23] wire decoded_addr_148_2 = decoded_addr_decoded_63; // @[Decode.scala:50:77] wire decoded_addr_decoded_64 = decoded_addr_decoded_decoded[85]; // @[pla.scala:81:23] wire decoded_addr_14_2 = decoded_addr_decoded_64; // @[Decode.scala:50:77] wire decoded_addr_decoded_65 = decoded_addr_decoded_decoded[84]; // @[pla.scala:81:23] wire decoded_addr_21_2 = decoded_addr_decoded_65; // @[Decode.scala:50:77] wire decoded_addr_decoded_66 = decoded_addr_decoded_decoded[83]; // @[pla.scala:81:23] wire decoded_addr_33_2 = decoded_addr_decoded_66; // @[Decode.scala:50:77] wire decoded_addr_decoded_67 = decoded_addr_decoded_decoded[82]; // @[pla.scala:81:23] wire decoded_addr_19_2 = decoded_addr_decoded_67; // @[Decode.scala:50:77] wire decoded_addr_decoded_68 = decoded_addr_decoded_decoded[81]; // @[pla.scala:81:23] wire decoded_addr_133_2 = decoded_addr_decoded_68; // @[Decode.scala:50:77] wire decoded_addr_decoded_69 = decoded_addr_decoded_decoded[80]; // @[pla.scala:81:23] wire decoded_addr_149_2 = decoded_addr_decoded_69; // @[Decode.scala:50:77] wire decoded_addr_decoded_70 = decoded_addr_decoded_decoded[79]; // @[pla.scala:81:23] wire decoded_addr_50_2 = decoded_addr_decoded_70; // @[Decode.scala:50:77] wire decoded_addr_decoded_71 = decoded_addr_decoded_decoded[78]; // @[pla.scala:81:23] wire decoded_addr_75_2 = decoded_addr_decoded_71; // @[Decode.scala:50:77] wire decoded_addr_decoded_72 = decoded_addr_decoded_decoded[77]; // @[pla.scala:81:23] wire decoded_addr_102_2 = decoded_addr_decoded_72; // @[Decode.scala:50:77] wire decoded_addr_decoded_73 = decoded_addr_decoded_decoded[76]; // @[pla.scala:81:23] wire decoded_addr_84_2 = decoded_addr_decoded_73; // @[Decode.scala:50:77] wire decoded_addr_decoded_74 = decoded_addr_decoded_decoded[75]; // @[pla.scala:81:23] wire decoded_addr_45_2 = decoded_addr_decoded_74; // @[Decode.scala:50:77] wire decoded_addr_decoded_75 = decoded_addr_decoded_decoded[74]; // @[pla.scala:81:23] wire decoded_addr_64_2 = decoded_addr_decoded_75; // @[Decode.scala:50:77] wire decoded_addr_decoded_76 = decoded_addr_decoded_decoded[73]; // @[pla.scala:81:23] wire decoded_addr_120_2 = decoded_addr_decoded_76; // @[Decode.scala:50:77] wire decoded_addr_decoded_77 = decoded_addr_decoded_decoded[72]; // @[pla.scala:81:23] wire decoded_addr_30_2 = decoded_addr_decoded_77; // @[Decode.scala:50:77] wire decoded_addr_decoded_78 = decoded_addr_decoded_decoded[71]; // @[pla.scala:81:23] wire decoded_addr_5_2 = decoded_addr_decoded_78; // @[Decode.scala:50:77] wire decoded_addr_decoded_79 = decoded_addr_decoded_decoded[70]; // @[pla.scala:81:23] wire decoded_addr_32_2 = decoded_addr_decoded_79; // @[Decode.scala:50:77] wire decoded_addr_decoded_80 = decoded_addr_decoded_decoded[69]; // @[pla.scala:81:23] wire decoded_addr_143_2 = decoded_addr_decoded_80; // @[Decode.scala:50:77] wire decoded_addr_decoded_81 = decoded_addr_decoded_decoded[68]; // @[pla.scala:81:23] wire decoded_addr_117_2 = decoded_addr_decoded_81; // @[Decode.scala:50:77] wire decoded_addr_decoded_82 = decoded_addr_decoded_decoded[67]; // @[pla.scala:81:23] wire decoded_addr_63_2 = decoded_addr_decoded_82; // @[Decode.scala:50:77] wire decoded_addr_decoded_83 = decoded_addr_decoded_decoded[66]; // @[pla.scala:81:23] wire decoded_addr_107_2 = decoded_addr_decoded_83; // @[Decode.scala:50:77] wire decoded_addr_decoded_84 = decoded_addr_decoded_decoded[65]; // @[pla.scala:81:23] wire decoded_addr_88_2 = decoded_addr_decoded_84; // @[Decode.scala:50:77] wire decoded_addr_decoded_85 = decoded_addr_decoded_decoded[64]; // @[pla.scala:81:23] wire decoded_addr_114_2 = decoded_addr_decoded_85; // @[Decode.scala:50:77] wire decoded_addr_decoded_86 = decoded_addr_decoded_decoded[63]; // @[pla.scala:81:23] wire decoded_addr_73_2 = decoded_addr_decoded_86; // @[Decode.scala:50:77] wire decoded_addr_decoded_87 = decoded_addr_decoded_decoded[62]; // @[pla.scala:81:23] wire decoded_addr_53_2 = decoded_addr_decoded_87; // @[Decode.scala:50:77] wire decoded_addr_decoded_88 = decoded_addr_decoded_decoded[61]; // @[pla.scala:81:23] wire decoded_addr_147_2 = decoded_addr_decoded_88; // @[Decode.scala:50:77] wire decoded_addr_decoded_89 = decoded_addr_decoded_decoded[60]; // @[pla.scala:81:23] wire decoded_addr_41_2 = decoded_addr_decoded_89; // @[Decode.scala:50:77] wire decoded_addr_decoded_90 = decoded_addr_decoded_decoded[59]; // @[pla.scala:81:23] wire decoded_addr_56_2 = decoded_addr_decoded_90; // @[Decode.scala:50:77] wire decoded_addr_decoded_91 = decoded_addr_decoded_decoded[58]; // @[pla.scala:81:23] wire decoded_addr_37_2 = decoded_addr_decoded_91; // @[Decode.scala:50:77] wire decoded_addr_decoded_92 = decoded_addr_decoded_decoded[57]; // @[pla.scala:81:23] wire decoded_addr_79_2 = decoded_addr_decoded_92; // @[Decode.scala:50:77] wire decoded_addr_decoded_93 = decoded_addr_decoded_decoded[56]; // @[pla.scala:81:23] wire decoded_addr_96_2 = decoded_addr_decoded_93; // @[Decode.scala:50:77] wire decoded_addr_decoded_94 = decoded_addr_decoded_decoded[55]; // @[pla.scala:81:23] wire decoded_addr_4_2 = decoded_addr_decoded_94; // @[Decode.scala:50:77] wire decoded_addr_decoded_95 = decoded_addr_decoded_decoded[54]; // @[pla.scala:81:23] wire decoded_addr_101_2 = decoded_addr_decoded_95; // @[Decode.scala:50:77] wire decoded_addr_decoded_96 = decoded_addr_decoded_decoded[53]; // @[pla.scala:81:23] wire decoded_addr_119_2 = decoded_addr_decoded_96; // @[Decode.scala:50:77] wire decoded_addr_decoded_97 = decoded_addr_decoded_decoded[52]; // @[pla.scala:81:23] wire decoded_addr_22_2 = decoded_addr_decoded_97; // @[Decode.scala:50:77] wire decoded_addr_decoded_98 = decoded_addr_decoded_decoded[51]; // @[pla.scala:81:23] wire decoded_addr_139_2 = decoded_addr_decoded_98; // @[Decode.scala:50:77] wire decoded_addr_decoded_99 = decoded_addr_decoded_decoded[50]; // @[pla.scala:81:23] wire decoded_addr_11_2 = decoded_addr_decoded_99; // @[Decode.scala:50:77] wire decoded_addr_decoded_100 = decoded_addr_decoded_decoded[49]; // @[pla.scala:81:23] wire decoded_addr_134_2 = decoded_addr_decoded_100; // @[Decode.scala:50:77] wire decoded_addr_decoded_101 = decoded_addr_decoded_decoded[48]; // @[pla.scala:81:23] wire decoded_addr_12_2 = decoded_addr_decoded_101; // @[Decode.scala:50:77] wire decoded_addr_decoded_102 = decoded_addr_decoded_decoded[47]; // @[pla.scala:81:23] wire decoded_addr_65_2 = decoded_addr_decoded_102; // @[Decode.scala:50:77] wire decoded_addr_decoded_103 = decoded_addr_decoded_decoded[46]; // @[pla.scala:81:23] wire decoded_addr_86_2 = decoded_addr_decoded_103; // @[Decode.scala:50:77] wire decoded_addr_decoded_104 = decoded_addr_decoded_decoded[45]; // @[pla.scala:81:23] wire decoded_addr_47_2 = decoded_addr_decoded_104; // @[Decode.scala:50:77] wire decoded_addr_decoded_105 = decoded_addr_decoded_decoded[44]; // @[pla.scala:81:23] wire decoded_addr_106_2 = decoded_addr_decoded_105; // @[Decode.scala:50:77] wire decoded_addr_decoded_106 = decoded_addr_decoded_decoded[43]; // @[pla.scala:81:23] wire decoded_addr_58_2 = decoded_addr_decoded_106; // @[Decode.scala:50:77] wire decoded_addr_decoded_107 = decoded_addr_decoded_decoded[42]; // @[pla.scala:81:23] wire decoded_addr_87_2 = decoded_addr_decoded_107; // @[Decode.scala:50:77] wire decoded_addr_decoded_108 = decoded_addr_decoded_decoded[41]; // @[pla.scala:81:23] wire decoded_addr_142_2 = decoded_addr_decoded_108; // @[Decode.scala:50:77] wire decoded_addr_decoded_109 = decoded_addr_decoded_decoded[40]; // @[pla.scala:81:23] wire decoded_addr_13_2 = decoded_addr_decoded_109; // @[Decode.scala:50:77] wire decoded_addr_decoded_110 = decoded_addr_decoded_decoded[39]; // @[pla.scala:81:23] wire decoded_addr_35_2 = decoded_addr_decoded_110; // @[Decode.scala:50:77] wire decoded_addr_decoded_111 = decoded_addr_decoded_decoded[38]; // @[pla.scala:81:23] wire decoded_addr_2_2 = decoded_addr_decoded_111; // @[Decode.scala:50:77] wire decoded_addr_decoded_112 = decoded_addr_decoded_decoded[37]; // @[pla.scala:81:23] wire decoded_addr_66_2 = decoded_addr_decoded_112; // @[Decode.scala:50:77] wire decoded_addr_decoded_113 = decoded_addr_decoded_decoded[36]; // @[pla.scala:81:23] wire decoded_addr_42_2 = decoded_addr_decoded_113; // @[Decode.scala:50:77] wire decoded_addr_decoded_114 = decoded_addr_decoded_decoded[35]; // @[pla.scala:81:23] wire decoded_addr_61_2 = decoded_addr_decoded_114; // @[Decode.scala:50:77] wire decoded_addr_decoded_115 = decoded_addr_decoded_decoded[34]; // @[pla.scala:81:23] wire decoded_addr_48_2 = decoded_addr_decoded_115; // @[Decode.scala:50:77] wire decoded_addr_decoded_116 = decoded_addr_decoded_decoded[33]; // @[pla.scala:81:23] wire decoded_addr_44_2 = decoded_addr_decoded_116; // @[Decode.scala:50:77] wire decoded_addr_decoded_117 = decoded_addr_decoded_decoded[32]; // @[pla.scala:81:23] wire decoded_addr_15_2 = decoded_addr_decoded_117; // @[Decode.scala:50:77] wire decoded_addr_decoded_118 = decoded_addr_decoded_decoded[31]; // @[pla.scala:81:23] wire decoded_addr_145_2 = decoded_addr_decoded_118; // @[Decode.scala:50:77] wire decoded_addr_decoded_119 = decoded_addr_decoded_decoded[30]; // @[pla.scala:81:23] wire decoded_addr_93_2 = decoded_addr_decoded_119; // @[Decode.scala:50:77] wire decoded_addr_decoded_120 = decoded_addr_decoded_decoded[29]; // @[pla.scala:81:23] wire decoded_addr_6_2 = decoded_addr_decoded_120; // @[Decode.scala:50:77] wire decoded_addr_decoded_121 = decoded_addr_decoded_decoded[28]; // @[pla.scala:81:23] wire decoded_addr_28_2 = decoded_addr_decoded_121; // @[Decode.scala:50:77] wire decoded_addr_decoded_122 = decoded_addr_decoded_decoded[27]; // @[pla.scala:81:23] wire decoded_addr_25_2 = decoded_addr_decoded_122; // @[Decode.scala:50:77] wire decoded_addr_decoded_123 = decoded_addr_decoded_decoded[26]; // @[pla.scala:81:23] wire decoded_addr_137_2 = decoded_addr_decoded_123; // @[Decode.scala:50:77] wire decoded_addr_decoded_124 = decoded_addr_decoded_decoded[25]; // @[pla.scala:81:23] wire decoded_addr_123_2 = decoded_addr_decoded_124; // @[Decode.scala:50:77] wire decoded_addr_decoded_125 = decoded_addr_decoded_decoded[24]; // @[pla.scala:81:23] wire decoded_addr_23_2 = decoded_addr_decoded_125; // @[Decode.scala:50:77] wire decoded_addr_decoded_126 = decoded_addr_decoded_decoded[23]; // @[pla.scala:81:23] wire decoded_addr_69_2 = decoded_addr_decoded_126; // @[Decode.scala:50:77] wire decoded_addr_decoded_127 = decoded_addr_decoded_decoded[22]; // @[pla.scala:81:23] wire decoded_addr_141_2 = decoded_addr_decoded_127; // @[Decode.scala:50:77] wire decoded_addr_decoded_128 = decoded_addr_decoded_decoded[21]; // @[pla.scala:81:23] wire decoded_addr_9_2 = decoded_addr_decoded_128; // @[Decode.scala:50:77] wire decoded_addr_decoded_129 = decoded_addr_decoded_decoded[20]; // @[pla.scala:81:23] wire decoded_addr_104_2 = decoded_addr_decoded_129; // @[Decode.scala:50:77] wire decoded_addr_decoded_130 = decoded_addr_decoded_decoded[19]; // @[pla.scala:81:23] wire decoded_addr_8_2 = decoded_addr_decoded_130; // @[Decode.scala:50:77] wire decoded_addr_decoded_131 = decoded_addr_decoded_decoded[18]; // @[pla.scala:81:23] wire decoded_addr_125_2 = decoded_addr_decoded_131; // @[Decode.scala:50:77] wire decoded_addr_decoded_132 = decoded_addr_decoded_decoded[17]; // @[pla.scala:81:23] wire decoded_addr_85_2 = decoded_addr_decoded_132; // @[Decode.scala:50:77] wire decoded_addr_decoded_133 = decoded_addr_decoded_decoded[16]; // @[pla.scala:81:23] wire decoded_addr_54_2 = decoded_addr_decoded_133; // @[Decode.scala:50:77] wire decoded_addr_decoded_134 = decoded_addr_decoded_decoded[15]; // @[pla.scala:81:23] wire decoded_addr_20_2 = decoded_addr_decoded_134; // @[Decode.scala:50:77] wire decoded_addr_decoded_135 = decoded_addr_decoded_decoded[14]; // @[pla.scala:81:23] wire decoded_addr_135_2 = decoded_addr_decoded_135; // @[Decode.scala:50:77] wire decoded_addr_decoded_136 = decoded_addr_decoded_decoded[13]; // @[pla.scala:81:23] wire decoded_addr_115_2 = decoded_addr_decoded_136; // @[Decode.scala:50:77] wire decoded_addr_decoded_137 = decoded_addr_decoded_decoded[12]; // @[pla.scala:81:23] wire decoded_addr_43_2 = decoded_addr_decoded_137; // @[Decode.scala:50:77] wire decoded_addr_decoded_138 = decoded_addr_decoded_decoded[11]; // @[pla.scala:81:23] wire decoded_addr_71_2 = decoded_addr_decoded_138; // @[Decode.scala:50:77] wire decoded_addr_decoded_139 = decoded_addr_decoded_decoded[10]; // @[pla.scala:81:23] wire decoded_addr_110_2 = decoded_addr_decoded_139; // @[Decode.scala:50:77] wire decoded_addr_decoded_140 = decoded_addr_decoded_decoded[9]; // @[pla.scala:81:23] wire decoded_addr_140_2 = decoded_addr_decoded_140; // @[Decode.scala:50:77] wire decoded_addr_decoded_141 = decoded_addr_decoded_decoded[8]; // @[pla.scala:81:23] wire decoded_addr_34_2 = decoded_addr_decoded_141; // @[Decode.scala:50:77] wire decoded_addr_decoded_142 = decoded_addr_decoded_decoded[7]; // @[pla.scala:81:23] wire decoded_addr_40_2 = decoded_addr_decoded_142; // @[Decode.scala:50:77] wire decoded_addr_decoded_143 = decoded_addr_decoded_decoded[6]; // @[pla.scala:81:23] wire decoded_addr_80_2 = decoded_addr_decoded_143; // @[Decode.scala:50:77] wire decoded_addr_decoded_144 = decoded_addr_decoded_decoded[5]; // @[pla.scala:81:23] wire decoded_addr_98_2 = decoded_addr_decoded_144; // @[Decode.scala:50:77] wire decoded_addr_decoded_145 = decoded_addr_decoded_decoded[4]; // @[pla.scala:81:23] wire decoded_addr_18_2 = decoded_addr_decoded_145; // @[Decode.scala:50:77] wire decoded_addr_decoded_146 = decoded_addr_decoded_decoded[3]; // @[pla.scala:81:23] wire decoded_addr_3_2 = decoded_addr_decoded_146; // @[Decode.scala:50:77] wire decoded_addr_decoded_147 = decoded_addr_decoded_decoded[2]; // @[pla.scala:81:23] wire decoded_addr_127_2 = decoded_addr_decoded_147; // @[Decode.scala:50:77] wire decoded_addr_decoded_148 = decoded_addr_decoded_decoded[1]; // @[pla.scala:81:23] wire decoded_addr_38_2 = decoded_addr_decoded_148; // @[Decode.scala:50:77] wire decoded_addr_decoded_149 = decoded_addr_decoded_decoded[0]; // @[pla.scala:81:23] wire decoded_addr_95_2 = decoded_addr_decoded_149; // @[Decode.scala:50:77] wire _wdata_T = io_rw_cmd_0[1]; // @[CSR.scala:377:7, :1643:13] wire _new_mip_T_1 = io_rw_cmd_0[1]; // @[CSR.scala:377:7, :1643:13] wire [63:0] _wdata_T_1 = _wdata_T ? io_rw_rdata_0 : 64'h0; // @[CSR.scala:377:7, :1643:{9,13}] wire [63:0] _wdata_T_2 = _wdata_T_1 \| io_rw_wdata_0; // @[CSR.scala:377:7, :1643:{9,30}] wire [1:0] _wdata_T_3 = io_rw_cmd_0[1:0]; // @[CSR.scala:377:7, :1643:49] wire [1:0] _new_mip_T_4 = io_rw_cmd_0[1:0]; // @[CSR.scala:377:7, :1643:49] wire _wdata_T_4 = &_wdata_T_3; // @[CSR.scala:1643:{49,55}] wire [63:0] _wdata_T_5 = _wdata_T_4 ? io_rw_wdata_0 : 64'h0; // @[CSR.scala:377:7, :1643:{45,55}] wire [63:0] _wdata_T_6 = ~_wdata_T_5; // @[CSR.scala:1643:{41,45}] assign wdata = _wdata_T_2 & _wdata_T_6; // @[CSR.scala:1643:{30,39,41}] assign io_customCSRs_0_wdata_0 = wdata; // @[CSR.scala:377:7, :1643:39] assign io_customCSRs_1_wdata_0 = wdata; // @[CSR.scala:377:7, :1643:39] wire [63:0] _new_satp_WIRE = wdata; // @[CSR.scala:1355:40, :1643:39] wire [63:0] _new_envcfg_WIRE = wdata; // @[CSR.scala:137:36, :1643:39] wire [63:0] _new_envcfg_WIRE_1 = wdata; // @[CSR.scala:137:36, :1643:39] wire [63:0] _newCfg_T = wdata; // @[CSR.scala:1491:29, :1643:39] wire system_insn = io_rw_cmd_0 == 3'h4; // @[CSR.scala:377:7, :876:31] wire [31:0] _insn_T = {io_rw_addr_0, 20'h0}; // @[CSR.scala:377:7, :892:44] wire [31:0] insn = {_insn_T[31:7], _insn_T[6:0] \| 7'h73}; // @[CSR.scala:892:{30,44}] wire [31:0] decoded_plaInput = insn; // @[pla.scala:77:22] wire [31:0] decoded_invInputs = ~decoded_plaInput; // @[pla.scala:77:22, :78:21] wire [8:0] decoded_invMatrixOutputs; // @[pla.scala:120:37] wire [8:0] decoded; // @[pla.scala:81:23] wire decoded_andMatrixOutputs_andMatrixInput_0 = decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_1 = decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_1_1 = decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_2 = decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_2_1 = decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_1_2 = decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_3 = decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_3_1 = decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_2_2 = decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_1_3 = decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_1_5 = decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_4 = decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_4_1 = decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_3_2 = decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_2_3 = decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_2_5 = decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_5 = decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_5_1 = decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_4_2 = decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_3_3 = decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_3_5 = decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_6 = decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_6_1 = decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_5_2 = decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_4_3 = decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_11_2 = decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_4_5 = decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_7 = decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_7_1 = decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_6_2 = decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_5_3 = decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_12 = decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_5_5 = decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_8 = decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_8_1 = decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_9 = decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_9_1 = decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_7_3 = decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_14 = decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_10 = decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_10_1 = decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_8_2 = decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_8_3 = decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_15 = decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_8_5 = decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_11 = decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_11_1 = decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_9_2 = decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_9_3 = decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_16 = decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_9_5 = decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_1_6 = decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire [1:0] decoded_andMatrixOutputs_lo_lo_hi = {decoded_andMatrixOutputs_andMatrixInput_9, decoded_andMatrixOutputs_andMatrixInput_10}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_andMatrixOutputs_lo_lo = {decoded_andMatrixOutputs_lo_lo_hi, decoded_andMatrixOutputs_andMatrixInput_11}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_andMatrixOutputs_lo_hi_hi = {decoded_andMatrixOutputs_andMatrixInput_6, decoded_andMatrixOutputs_andMatrixInput_7}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_andMatrixOutputs_lo_hi = {decoded_andMatrixOutputs_lo_hi_hi, decoded_andMatrixOutputs_andMatrixInput_8}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_andMatrixOutputs_lo = {decoded_andMatrixOutputs_lo_hi, decoded_andMatrixOutputs_lo_lo}; // @[pla.scala:98:53] wire [1:0] decoded_andMatrixOutputs_hi_lo_hi = {decoded_andMatrixOutputs_andMatrixInput_3, decoded_andMatrixOutputs_andMatrixInput_4}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_andMatrixOutputs_hi_lo = {decoded_andMatrixOutputs_hi_lo_hi, decoded_andMatrixOutputs_andMatrixInput_5}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_andMatrixOutputs_hi_hi_hi = {decoded_andMatrixOutputs_andMatrixInput_0, decoded_andMatrixOutputs_andMatrixInput_1}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_andMatrixOutputs_hi_hi = {decoded_andMatrixOutputs_hi_hi_hi, decoded_andMatrixOutputs_andMatrixInput_2}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_andMatrixOutputs_hi = {decoded_andMatrixOutputs_hi_hi, decoded_andMatrixOutputs_hi_lo}; // @[pla.scala:98:53] wire [11:0] _decoded_andMatrixOutputs_T = {decoded_andMatrixOutputs_hi, decoded_andMatrixOutputs_lo}; // @[pla.scala:98:53] wire decoded_andMatrixOutputs_6_2 = &_decoded_andMatrixOutputs_T; // @[pla.scala:98:{53,70}] wire _decoded_orMatrixOutputs_T_6 = decoded_andMatrixOutputs_6_2; // @[pla.scala:98:70, :114:36] wire decoded_andMatrixOutputs_andMatrixInput_0_1 = decoded_plaInput[20]; // @[pla.scala:77:22, :90:45] wire [1:0] decoded_andMatrixOutputs_lo_lo_hi_1 = {decoded_andMatrixOutputs_andMatrixInput_9_1, decoded_andMatrixOutputs_andMatrixInput_10_1}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_andMatrixOutputs_lo_lo_1 = {decoded_andMatrixOutputs_lo_lo_hi_1, decoded_andMatrixOutputs_andMatrixInput_11_1}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_andMatrixOutputs_lo_hi_hi_1 = {decoded_andMatrixOutputs_andMatrixInput_6_1, decoded_andMatrixOutputs_andMatrixInput_7_1}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_andMatrixOutputs_lo_hi_1 = {decoded_andMatrixOutputs_lo_hi_hi_1, decoded_andMatrixOutputs_andMatrixInput_8_1}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_andMatrixOutputs_lo_1 = {decoded_andMatrixOutputs_lo_hi_1, decoded_andMatrixOutputs_lo_lo_1}; // @[pla.scala:98:53] wire [1:0] decoded_andMatrixOutputs_hi_lo_hi_1 = {decoded_andMatrixOutputs_andMatrixInput_3_1, decoded_andMatrixOutputs_andMatrixInput_4_1}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_andMatrixOutputs_hi_lo_1 = {decoded_andMatrixOutputs_hi_lo_hi_1, decoded_andMatrixOutputs_andMatrixInput_5_1}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_andMatrixOutputs_hi_hi_hi_1 = {decoded_andMatrixOutputs_andMatrixInput_0_1, decoded_andMatrixOutputs_andMatrixInput_1_1}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_andMatrixOutputs_hi_hi_1 = {decoded_andMatrixOutputs_hi_hi_hi_1, decoded_andMatrixOutputs_andMatrixInput_2_1}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_andMatrixOutputs_hi_1 = {decoded_andMatrixOutputs_hi_hi_1, decoded_andMatrixOutputs_hi_lo_1}; // @[pla.scala:98:53] wire [11:0] _decoded_andMatrixOutputs_T_1 = {decoded_andMatrixOutputs_hi_1, decoded_andMatrixOutputs_lo_1}; // @[pla.scala:98:53] wire decoded_andMatrixOutputs_4_2 = &_decoded_andMatrixOutputs_T_1; // @[pla.scala:98:{53,70}] wire _decoded_orMatrixOutputs_T_5 = decoded_andMatrixOutputs_4_2; // @[pla.scala:98:70, :114:36] wire decoded_andMatrixOutputs_andMatrixInput_0_2 = decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_andMatrixOutputs_andMatrixInput_0_4 = decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_andMatrixOutputs_andMatrixInput_7_2 = decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire decoded_andMatrixOutputs_andMatrixInput_6_3 = decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire decoded_andMatrixOutputs_andMatrixInput_13 = decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire decoded_andMatrixOutputs_andMatrixInput_6_5 = decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire [1:0] decoded_andMatrixOutputs_lo_lo_2 = {decoded_andMatrixOutputs_andMatrixInput_8_2, decoded_andMatrixOutputs_andMatrixInput_9_2}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_andMatrixOutputs_lo_hi_hi_2 = {decoded_andMatrixOutputs_andMatrixInput_5_2, decoded_andMatrixOutputs_andMatrixInput_6_2}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_andMatrixOutputs_lo_hi_2 = {decoded_andMatrixOutputs_lo_hi_hi_2, decoded_andMatrixOutputs_andMatrixInput_7_2}; // @[pla.scala:90:45, :98:53] wire [4:0] decoded_andMatrixOutputs_lo_2 = {decoded_andMatrixOutputs_lo_hi_2, decoded_andMatrixOutputs_lo_lo_2}; // @[pla.scala:98:53] wire [1:0] decoded_andMatrixOutputs_hi_lo_2 = {decoded_andMatrixOutputs_andMatrixInput_3_2, decoded_andMatrixOutputs_andMatrixInput_4_2}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_andMatrixOutputs_hi_hi_hi_2 = {decoded_andMatrixOutputs_andMatrixInput_0_2, decoded_andMatrixOutputs_andMatrixInput_1_2}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_andMatrixOutputs_hi_hi_2 = {decoded_andMatrixOutputs_hi_hi_hi_2, decoded_andMatrixOutputs_andMatrixInput_2_2}; // @[pla.scala:91:29, :98:53] wire [4:0] decoded_andMatrixOutputs_hi_2 = {decoded_andMatrixOutputs_hi_hi_2, decoded_andMatrixOutputs_hi_lo_2}; // @[pla.scala:98:53] wire [9:0] _decoded_andMatrixOutputs_T_2 = {decoded_andMatrixOutputs_hi_2, decoded_andMatrixOutputs_lo_2}; // @[pla.scala:98:53] wire decoded_andMatrixOutputs_3_2 = &_decoded_andMatrixOutputs_T_2; // @[pla.scala:98:{53,70}] wire decoded_andMatrixOutputs_andMatrixInput_0_3 = decoded_plaInput[22]; // @[pla.scala:77:22, :90:45] wire decoded_andMatrixOutputs_andMatrixInput_0_5 = decoded_plaInput[22]; // @[pla.scala:77:22, :90:45] wire [1:0] decoded_andMatrixOutputs_lo_lo_3 = {decoded_andMatrixOutputs_andMatrixInput_8_3, decoded_andMatrixOutputs_andMatrixInput_9_3}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_andMatrixOutputs_lo_hi_hi_3 = {decoded_andMatrixOutputs_andMatrixInput_5_3, decoded_andMatrixOutputs_andMatrixInput_6_3}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_andMatrixOutputs_lo_hi_3 = {decoded_andMatrixOutputs_lo_hi_hi_3, decoded_andMatrixOutputs_andMatrixInput_7_3}; // @[pla.scala:91:29, :98:53] wire [4:0] decoded_andMatrixOutputs_lo_3 = {decoded_andMatrixOutputs_lo_hi_3, decoded_andMatrixOutputs_lo_lo_3}; // @[pla.scala:98:53] wire [1:0] decoded_andMatrixOutputs_hi_lo_3 = {decoded_andMatrixOutputs_andMatrixInput_3_3, decoded_andMatrixOutputs_andMatrixInput_4_3}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_andMatrixOutputs_hi_hi_hi_3 = {decoded_andMatrixOutputs_andMatrixInput_0_3, decoded_andMatrixOutputs_andMatrixInput_1_3}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_andMatrixOutputs_hi_hi_3 = {decoded_andMatrixOutputs_hi_hi_hi_3, decoded_andMatrixOutputs_andMatrixInput_2_3}; // @[pla.scala:91:29, :98:53] wire [4:0] decoded_andMatrixOutputs_hi_3 = {decoded_andMatrixOutputs_hi_hi_3, decoded_andMatrixOutputs_hi_lo_3}; // @[pla.scala:98:53] wire [9:0] _decoded_andMatrixOutputs_T_3 = {decoded_andMatrixOutputs_hi_3, decoded_andMatrixOutputs_lo_3}; // @[pla.scala:98:53] wire decoded_andMatrixOutputs_1_2 = &_decoded_andMatrixOutputs_T_3; // @[pla.scala:98:{53,70}] wire _decoded_orMatrixOutputs_T_1 = decoded_andMatrixOutputs_1_2; // @[pla.scala:98:70, :114:36] wire decoded_andMatrixOutputs_andMatrixInput_1_4 = decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_andMatrixOutputs_andMatrixInput_2_4 = decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_3_4 = decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_4_4 = decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_andMatrixOutputs_andMatrixInput_5_4 = decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_andMatrixOutputs_andMatrixInput_6_4 = decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire decoded_andMatrixOutputs_andMatrixInput_7_4 = decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_8_4 = decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_9_4 = decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_10_2 = decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire [1:0] decoded_andMatrixOutputs_lo_lo_lo = {decoded_andMatrixOutputs_andMatrixInput_15, decoded_andMatrixOutputs_andMatrixInput_16}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_andMatrixOutputs_lo_lo_hi_2 = {decoded_andMatrixOutputs_andMatrixInput_13, decoded_andMatrixOutputs_andMatrixInput_14}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoded_andMatrixOutputs_lo_lo_4 = {decoded_andMatrixOutputs_lo_lo_hi_2, decoded_andMatrixOutputs_lo_lo_lo}; // @[pla.scala:98:53] wire [1:0] decoded_andMatrixOutputs_lo_hi_lo = {decoded_andMatrixOutputs_andMatrixInput_11_2, decoded_andMatrixOutputs_andMatrixInput_12}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_andMatrixOutputs_lo_hi_hi_4 = {decoded_andMatrixOutputs_andMatrixInput_9_4, decoded_andMatrixOutputs_andMatrixInput_10_2}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoded_andMatrixOutputs_lo_hi_4 = {decoded_andMatrixOutputs_lo_hi_hi_4, decoded_andMatrixOutputs_lo_hi_lo}; // @[pla.scala:98:53] wire [7:0] decoded_andMatrixOutputs_lo_4 = {decoded_andMatrixOutputs_lo_hi_4, decoded_andMatrixOutputs_lo_lo_4}; // @[pla.scala:98:53] wire [1:0] decoded_andMatrixOutputs_hi_lo_lo = {decoded_andMatrixOutputs_andMatrixInput_7_4, decoded_andMatrixOutputs_andMatrixInput_8_4}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_andMatrixOutputs_hi_lo_hi_2 = {decoded_andMatrixOutputs_andMatrixInput_5_4, decoded_andMatrixOutputs_andMatrixInput_6_4}; // @[pla.scala:90:45, :98:53] wire [3:0] decoded_andMatrixOutputs_hi_lo_4 = {decoded_andMatrixOutputs_hi_lo_hi_2, decoded_andMatrixOutputs_hi_lo_lo}; // @[pla.scala:98:53] wire [1:0] decoded_andMatrixOutputs_hi_hi_lo = {decoded_andMatrixOutputs_andMatrixInput_3_4, decoded_andMatrixOutputs_andMatrixInput_4_4}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoded_andMatrixOutputs_hi_hi_hi_hi = {decoded_andMatrixOutputs_andMatrixInput_0_4, decoded_andMatrixOutputs_andMatrixInput_1_4}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_andMatrixOutputs_hi_hi_hi_4 = {decoded_andMatrixOutputs_hi_hi_hi_hi, decoded_andMatrixOutputs_andMatrixInput_2_4}; // @[pla.scala:91:29, :98:53] wire [4:0] decoded_andMatrixOutputs_hi_hi_4 = {decoded_andMatrixOutputs_hi_hi_hi_4, decoded_andMatrixOutputs_hi_hi_lo}; // @[pla.scala:98:53] wire [8:0] decoded_andMatrixOutputs_hi_4 = {decoded_andMatrixOutputs_hi_hi_4, decoded_andMatrixOutputs_hi_lo_4}; // @[pla.scala:98:53] wire [16:0] _decoded_andMatrixOutputs_T_4 = {decoded_andMatrixOutputs_hi_4, decoded_andMatrixOutputs_lo_4}; // @[pla.scala:98:53] wire decoded_andMatrixOutputs_0_2 = &_decoded_andMatrixOutputs_T_4; // @[pla.scala:98:{53,70}] wire _decoded_orMatrixOutputs_T = decoded_andMatrixOutputs_0_2; // @[pla.scala:98:70, :114:36] wire decoded_andMatrixOutputs_andMatrixInput_7_5 = decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire [1:0] decoded_andMatrixOutputs_lo_lo_5 = {decoded_andMatrixOutputs_andMatrixInput_8_5, decoded_andMatrixOutputs_andMatrixInput_9_5}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_andMatrixOutputs_lo_hi_hi_5 = {decoded_andMatrixOutputs_andMatrixInput_5_5, decoded_andMatrixOutputs_andMatrixInput_6_5}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_andMatrixOutputs_lo_hi_5 = {decoded_andMatrixOutputs_lo_hi_hi_5, decoded_andMatrixOutputs_andMatrixInput_7_5}; // @[pla.scala:90:45, :98:53] wire [4:0] decoded_andMatrixOutputs_lo_5 = {decoded_andMatrixOutputs_lo_hi_5, decoded_andMatrixOutputs_lo_lo_5}; // @[pla.scala:98:53] wire [1:0] decoded_andMatrixOutputs_hi_lo_5 = {decoded_andMatrixOutputs_andMatrixInput_3_5, decoded_andMatrixOutputs_andMatrixInput_4_5}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_andMatrixOutputs_hi_hi_hi_5 = {decoded_andMatrixOutputs_andMatrixInput_0_5, decoded_andMatrixOutputs_andMatrixInput_1_5}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_andMatrixOutputs_hi_hi_5 = {decoded_andMatrixOutputs_hi_hi_hi_5, decoded_andMatrixOutputs_andMatrixInput_2_5}; // @[pla.scala:91:29, :98:53] wire [4:0] decoded_andMatrixOutputs_hi_5 = {decoded_andMatrixOutputs_hi_hi_5, decoded_andMatrixOutputs_hi_lo_5}; // @[pla.scala:98:53] wire [9:0] _decoded_andMatrixOutputs_T_5 = {decoded_andMatrixOutputs_hi_5, decoded_andMatrixOutputs_lo_5}; // @[pla.scala:98:53] wire decoded_andMatrixOutputs_5_2 = &_decoded_andMatrixOutputs_T_5; // @[pla.scala:98:{53,70}] wire _decoded_orMatrixOutputs_T_2 = decoded_andMatrixOutputs_5_2; // @[pla.scala:98:70, :114:36] wire decoded_andMatrixOutputs_andMatrixInput_0_6 = decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire [1:0] _decoded_andMatrixOutputs_T_6 = {decoded_andMatrixOutputs_andMatrixInput_0_6, decoded_andMatrixOutputs_andMatrixInput_1_6}; // @[pla.scala:90:45, :91:29, :98:53] wire decoded_andMatrixOutputs_2_2 = &_decoded_andMatrixOutputs_T_6; // @[pla.scala:98:{53,70}] wire [1:0] _decoded_orMatrixOutputs_T_3 = {decoded_andMatrixOutputs_3_2, decoded_andMatrixOutputs_2_2}; // @[pla.scala:98:70, :114:19] wire _decoded_orMatrixOutputs_T_4 = \|_decoded_orMatrixOutputs_T_3; // @[pla.scala:114:{19,36}] wire [1:0] decoded_orMatrixOutputs_lo_hi = {_decoded_orMatrixOutputs_T, 1'h0}; // @[pla.scala:102:36, :114:36] wire [3:0] decoded_orMatrixOutputs_lo = {decoded_orMatrixOutputs_lo_hi, 2'h0}; // @[pla.scala:102:36] wire [1:0] decoded_orMatrixOutputs_hi_lo = {_decoded_orMatrixOutputs_T_2, _decoded_orMatrixOutputs_T_1}; // @[pla.scala:102:36, :114:36] wire [1:0] decoded_orMatrixOutputs_hi_hi_hi = {_decoded_orMatrixOutputs_T_6, _decoded_orMatrixOutputs_T_5}; // @[pla.scala:102:36, :114:36] wire [2:0] decoded_orMatrixOutputs_hi_hi = {decoded_orMatrixOutputs_hi_hi_hi, _decoded_orMatrixOutputs_T_4}; // @[pla.scala:102:36, :114:36] wire [4:0] decoded_orMatrixOutputs_hi = {decoded_orMatrixOutputs_hi_hi, decoded_orMatrixOutputs_hi_lo}; // @[pla.scala:102:36] wire [8:0] decoded_orMatrixOutputs = {decoded_orMatrixOutputs_hi, decoded_orMatrixOutputs_lo}; // @[pla.scala:102:36] wire _decoded_invMatrixOutputs_T = decoded_orMatrixOutputs[0]; // @[pla.scala:102:36, :124:31] wire _decoded_invMatrixOutputs_T_1 = decoded_orMatrixOutputs[1]; // @[pla.scala:102:36, :124:31] wire _decoded_invMatrixOutputs_T_2 = decoded_orMatrixOutputs[2]; // @[pla.scala:102:36, :124:31] wire _decoded_invMatrixOutputs_T_3 = decoded_orMatrixOutputs[3]; // @[pla.scala:102:36, :124:31] wire _decoded_invMatrixOutputs_T_4 = decoded_orMatrixOutputs[4]; // @[pla.scala:102:36, :124:31] wire _decoded_invMatrixOutputs_T_5 = decoded_orMatrixOutputs[5]; // @[pla.scala:102:36, :124:31] wire _decoded_invMatrixOutputs_T_6 = decoded_orMatrixOutputs[6]; // @[pla.scala:102:36, :124:31] wire _decoded_invMatrixOutputs_T_7 = decoded_orMatrixOutputs[7]; // @[pla.scala:102:36, :124:31] wire _decoded_invMatrixOutputs_T_8 = decoded_orMatrixOutputs[8]; // @[pla.scala:102:36, :124:31] wire [1:0] decoded_invMatrixOutputs_lo_lo = {_decoded_invMatrixOutputs_T_1, _decoded_invMatrixOutputs_T}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_invMatrixOutputs_lo_hi = {_decoded_invMatrixOutputs_T_3, _decoded_invMatrixOutputs_T_2}; // @[pla.scala:120:37, :124:31] wire [3:0] decoded_invMatrixOutputs_lo = {decoded_invMatrixOutputs_lo_hi, decoded_invMatrixOutputs_lo_lo}; // @[pla.scala:120:37] wire [1:0] decoded_invMatrixOutputs_hi_lo = {_decoded_invMatrixOutputs_T_5, _decoded_invMatrixOutputs_T_4}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_invMatrixOutputs_hi_hi_hi = {_decoded_invMatrixOutputs_T_8, _decoded_invMatrixOutputs_T_7}; // @[pla.scala:120:37, :124:31] wire [2:0] decoded_invMatrixOutputs_hi_hi = {decoded_invMatrixOutputs_hi_hi_hi, _decoded_invMatrixOutputs_T_6}; // @[pla.scala:120:37, :124:31] wire [4:0] decoded_invMatrixOutputs_hi = {decoded_invMatrixOutputs_hi_hi, decoded_invMatrixOutputs_hi_lo}; // @[pla.scala:120:37] assign decoded_invMatrixOutputs = {decoded_invMatrixOutputs_hi, decoded_invMatrixOutputs_lo}; // @[pla.scala:120:37] assign decoded = decoded_invMatrixOutputs; // @[pla.scala:81:23, :120:37] wire insn_call = system_insn & decoded[8]; // @[pla.scala:81:23] wire insn_break = system_insn & decoded[7]; // @[pla.scala:81:23] wire insn_ret = system_insn & decoded[6]; // @[pla.scala:81:23] wire insn_cease = system_insn & decoded[5]; // @[pla.scala:81:23] wire insn_wfi = system_insn & decoded[4]; // @[pla.scala:81:23] wire [11:0] addr = io_decode_0_inst_0[31:20]; // @[CSR.scala:377:7, :897:27] wire [11:0] io_decode_0_fp_csr_plaInput = addr; // @[pla.scala:77:22] wire [11:0] io_decode_0_vector_csr_plaInput = addr; // @[pla.scala:77:22] wire [11:0] io_decode_0_read_illegal_plaInput = addr; // @[pla.scala:77:22] wire [11:0] io_decode_0_read_illegal_plaInput_1 = addr; // @[pla.scala:77:22] wire [31:0] decoded_invInputs_1 = ~decoded_plaInput_1; // @[pla.scala:77:22, :78:21] wire [8:0] decoded_invMatrixOutputs_1; // @[pla.scala:120:37] wire [8:0] decoded_1; // @[pla.scala:81:23] wire decoded_andMatrixOutputs_andMatrixInput_0_7 = decoded_invInputs_1[20]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_1_7 = decoded_invInputs_1[21]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_1_8 = decoded_invInputs_1[21]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_2_6 = decoded_invInputs_1[22]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_2_7 = decoded_invInputs_1[22]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_1_9 = decoded_invInputs_1[22]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_3_6 = decoded_invInputs_1[23]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_3_7 = decoded_invInputs_1[23]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_2_8 = decoded_invInputs_1[23]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_1_10 = decoded_invInputs_1[23]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_1_12 = decoded_invInputs_1[23]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_4_6 = decoded_invInputs_1[24]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_4_7 = decoded_invInputs_1[24]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_3_8 = decoded_invInputs_1[24]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_2_9 = decoded_invInputs_1[24]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_2_11 = decoded_invInputs_1[24]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_5_6 = decoded_invInputs_1[25]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_5_7 = decoded_invInputs_1[25]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_4_8 = decoded_invInputs_1[25]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_3_9 = decoded_invInputs_1[25]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_3_11 = decoded_invInputs_1[25]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_6_6 = decoded_invInputs_1[26]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_6_7 = decoded_invInputs_1[26]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_5_8 = decoded_invInputs_1[26]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_4_9 = decoded_invInputs_1[26]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_11_5 = decoded_invInputs_1[26]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_4_11 = decoded_invInputs_1[26]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_7_6 = decoded_invInputs_1[27]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_7_7 = decoded_invInputs_1[27]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_6_8 = decoded_invInputs_1[27]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_5_9 = decoded_invInputs_1[27]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_12_1 = decoded_invInputs_1[27]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_5_11 = decoded_invInputs_1[27]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_8_6 = decoded_invInputs_1[28]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_8_7 = decoded_invInputs_1[28]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_9_6 = decoded_invInputs_1[29]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_9_7 = decoded_invInputs_1[29]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_7_9 = decoded_invInputs_1[29]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_14_1 = decoded_invInputs_1[29]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_10_3 = decoded_invInputs_1[30]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_10_4 = decoded_invInputs_1[30]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_8_8 = decoded_invInputs_1[30]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_8_9 = decoded_invInputs_1[30]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_15_1 = decoded_invInputs_1[30]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_8_11 = decoded_invInputs_1[30]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_11_3 = decoded_invInputs_1[31]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_11_4 = decoded_invInputs_1[31]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_9_8 = decoded_invInputs_1[31]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_9_9 = decoded_invInputs_1[31]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_16_1 = decoded_invInputs_1[31]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_9_11 = decoded_invInputs_1[31]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_1_13 = decoded_invInputs_1[31]; // @[pla.scala:78:21, :91:29] wire [1:0] decoded_andMatrixOutputs_lo_lo_hi_3 = {decoded_andMatrixOutputs_andMatrixInput_9_6, decoded_andMatrixOutputs_andMatrixInput_10_3}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_andMatrixOutputs_lo_lo_6 = {decoded_andMatrixOutputs_lo_lo_hi_3, decoded_andMatrixOutputs_andMatrixInput_11_3}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_andMatrixOutputs_lo_hi_hi_6 = {decoded_andMatrixOutputs_andMatrixInput_6_6, decoded_andMatrixOutputs_andMatrixInput_7_6}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_andMatrixOutputs_lo_hi_6 = {decoded_andMatrixOutputs_lo_hi_hi_6, decoded_andMatrixOutputs_andMatrixInput_8_6}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_andMatrixOutputs_lo_6 = {decoded_andMatrixOutputs_lo_hi_6, decoded_andMatrixOutputs_lo_lo_6}; // @[pla.scala:98:53] wire [1:0] decoded_andMatrixOutputs_hi_lo_hi_3 = {decoded_andMatrixOutputs_andMatrixInput_3_6, decoded_andMatrixOutputs_andMatrixInput_4_6}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_andMatrixOutputs_hi_lo_6 = {decoded_andMatrixOutputs_hi_lo_hi_3, decoded_andMatrixOutputs_andMatrixInput_5_6}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_andMatrixOutputs_hi_hi_hi_6 = {decoded_andMatrixOutputs_andMatrixInput_0_7, decoded_andMatrixOutputs_andMatrixInput_1_7}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_andMatrixOutputs_hi_hi_6 = {decoded_andMatrixOutputs_hi_hi_hi_6, decoded_andMatrixOutputs_andMatrixInput_2_6}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_andMatrixOutputs_hi_6 = {decoded_andMatrixOutputs_hi_hi_6, decoded_andMatrixOutputs_hi_lo_6}; // @[pla.scala:98:53] wire [11:0] _decoded_andMatrixOutputs_T_7 = {decoded_andMatrixOutputs_hi_6, decoded_andMatrixOutputs_lo_6}; // @[pla.scala:98:53] wire decoded_andMatrixOutputs_6_2_1 = &_decoded_andMatrixOutputs_T_7; // @[pla.scala:98:{53,70}] wire _decoded_orMatrixOutputs_T_13 = decoded_andMatrixOutputs_6_2_1; // @[pla.scala:98:70, :114:36] wire decoded_andMatrixOutputs_andMatrixInput_0_8 = decoded_plaInput_1[20]; // @[pla.scala:77:22, :90:45] wire [1:0] decoded_andMatrixOutputs_lo_lo_hi_4 = {decoded_andMatrixOutputs_andMatrixInput_9_7, decoded_andMatrixOutputs_andMatrixInput_10_4}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_andMatrixOutputs_lo_lo_7 = {decoded_andMatrixOutputs_lo_lo_hi_4, decoded_andMatrixOutputs_andMatrixInput_11_4}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_andMatrixOutputs_lo_hi_hi_7 = {decoded_andMatrixOutputs_andMatrixInput_6_7, decoded_andMatrixOutputs_andMatrixInput_7_7}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_andMatrixOutputs_lo_hi_7 = {decoded_andMatrixOutputs_lo_hi_hi_7, decoded_andMatrixOutputs_andMatrixInput_8_7}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_andMatrixOutputs_lo_7 = {decoded_andMatrixOutputs_lo_hi_7, decoded_andMatrixOutputs_lo_lo_7}; // @[pla.scala:98:53] wire [1:0] decoded_andMatrixOutputs_hi_lo_hi_4 = {decoded_andMatrixOutputs_andMatrixInput_3_7, decoded_andMatrixOutputs_andMatrixInput_4_7}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_andMatrixOutputs_hi_lo_7 = {decoded_andMatrixOutputs_hi_lo_hi_4, decoded_andMatrixOutputs_andMatrixInput_5_7}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_andMatrixOutputs_hi_hi_hi_7 = {decoded_andMatrixOutputs_andMatrixInput_0_8, decoded_andMatrixOutputs_andMatrixInput_1_8}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_andMatrixOutputs_hi_hi_7 = {decoded_andMatrixOutputs_hi_hi_hi_7, decoded_andMatrixOutputs_andMatrixInput_2_7}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_andMatrixOutputs_hi_7 = {decoded_andMatrixOutputs_hi_hi_7, decoded_andMatrixOutputs_hi_lo_7}; // @[pla.scala:98:53] wire [11:0] _decoded_andMatrixOutputs_T_8 = {decoded_andMatrixOutputs_hi_7, decoded_andMatrixOutputs_lo_7}; // @[pla.scala:98:53] wire decoded_andMatrixOutputs_4_2_1 = &_decoded_andMatrixOutputs_T_8; // @[pla.scala:98:{53,70}] wire _decoded_orMatrixOutputs_T_12 = decoded_andMatrixOutputs_4_2_1; // @[pla.scala:98:70, :114:36] wire decoded_andMatrixOutputs_andMatrixInput_0_9 = decoded_plaInput_1[0]; // @[pla.scala:77:22, :90:45] wire decoded_andMatrixOutputs_andMatrixInput_0_11 = decoded_plaInput_1[0]; // @[pla.scala:77:22, :90:45] wire decoded_andMatrixOutputs_andMatrixInput_7_8 = decoded_plaInput_1[28]; // @[pla.scala:77:22, :90:45] wire decoded_andMatrixOutputs_andMatrixInput_6_9 = decoded_plaInput_1[28]; // @[pla.scala:77:22, :90:45] wire decoded_andMatrixOutputs_andMatrixInput_13_1 = decoded_plaInput_1[28]; // @[pla.scala:77:22, :90:45] wire decoded_andMatrixOutputs_andMatrixInput_6_11 = decoded_plaInput_1[28]; // @[pla.scala:77:22, :90:45] wire [1:0] decoded_andMatrixOutputs_lo_lo_8 = {decoded_andMatrixOutputs_andMatrixInput_8_8, decoded_andMatrixOutputs_andMatrixInput_9_8}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_andMatrixOutputs_lo_hi_hi_8 = {decoded_andMatrixOutputs_andMatrixInput_5_8, decoded_andMatrixOutputs_andMatrixInput_6_8}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_andMatrixOutputs_lo_hi_8 = {decoded_andMatrixOutputs_lo_hi_hi_8, decoded_andMatrixOutputs_andMatrixInput_7_8}; // @[pla.scala:90:45, :98:53] wire [4:0] decoded_andMatrixOutputs_lo_8 = {decoded_andMatrixOutputs_lo_hi_8, decoded_andMatrixOutputs_lo_lo_8}; // @[pla.scala:98:53] wire [1:0] decoded_andMatrixOutputs_hi_lo_8 = {decoded_andMatrixOutputs_andMatrixInput_3_8, decoded_andMatrixOutputs_andMatrixInput_4_8}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_andMatrixOutputs_hi_hi_hi_8 = {decoded_andMatrixOutputs_andMatrixInput_0_9, decoded_andMatrixOutputs_andMatrixInput_1_9}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_andMatrixOutputs_hi_hi_8 = {decoded_andMatrixOutputs_hi_hi_hi_8, decoded_andMatrixOutputs_andMatrixInput_2_8}; // @[pla.scala:91:29, :98:53] wire [4:0] decoded_andMatrixOutputs_hi_8 = {decoded_andMatrixOutputs_hi_hi_8, decoded_andMatrixOutputs_hi_lo_8}; // @[pla.scala:98:53] wire [9:0] _decoded_andMatrixOutputs_T_9 = {decoded_andMatrixOutputs_hi_8, decoded_andMatrixOutputs_lo_8}; // @[pla.scala:98:53] wire decoded_andMatrixOutputs_3_2_1 = &_decoded_andMatrixOutputs_T_9; // @[pla.scala:98:{53,70}] wire decoded_andMatrixOutputs_andMatrixInput_0_10 = decoded_plaInput_1[22]; // @[pla.scala:77:22, :90:45] wire decoded_andMatrixOutputs_andMatrixInput_0_12 = decoded_plaInput_1[22]; // @[pla.scala:77:22, :90:45] wire [1:0] decoded_andMatrixOutputs_lo_lo_9 = {decoded_andMatrixOutputs_andMatrixInput_8_9, decoded_andMatrixOutputs_andMatrixInput_9_9}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_andMatrixOutputs_lo_hi_hi_9 = {decoded_andMatrixOutputs_andMatrixInput_5_9, decoded_andMatrixOutputs_andMatrixInput_6_9}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_andMatrixOutputs_lo_hi_9 = {decoded_andMatrixOutputs_lo_hi_hi_9, decoded_andMatrixOutputs_andMatrixInput_7_9}; // @[pla.scala:91:29, :98:53] wire [4:0] decoded_andMatrixOutputs_lo_9 = {decoded_andMatrixOutputs_lo_hi_9, decoded_andMatrixOutputs_lo_lo_9}; // @[pla.scala:98:53] wire [1:0] decoded_andMatrixOutputs_hi_lo_9 = {decoded_andMatrixOutputs_andMatrixInput_3_9, decoded_andMatrixOutputs_andMatrixInput_4_9}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_andMatrixOutputs_hi_hi_hi_9 = {decoded_andMatrixOutputs_andMatrixInput_0_10, decoded_andMatrixOutputs_andMatrixInput_1_10}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_andMatrixOutputs_hi_hi_9 = {decoded_andMatrixOutputs_hi_hi_hi_9, decoded_andMatrixOutputs_andMatrixInput_2_9}; // @[pla.scala:91:29, :98:53] wire [4:0] decoded_andMatrixOutputs_hi_9 = {decoded_andMatrixOutputs_hi_hi_9, decoded_andMatrixOutputs_hi_lo_9}; // @[pla.scala:98:53] wire [9:0] _decoded_andMatrixOutputs_T_10 = {decoded_andMatrixOutputs_hi_9, decoded_andMatrixOutputs_lo_9}; // @[pla.scala:98:53] wire decoded_andMatrixOutputs_1_2_1 = &_decoded_andMatrixOutputs_T_10; // @[pla.scala:98:{53,70}] wire _decoded_orMatrixOutputs_T_8 = decoded_andMatrixOutputs_1_2_1; // @[pla.scala:98:70, :114:36] wire decoded_andMatrixOutputs_andMatrixInput_1_11 = decoded_plaInput_1[1]; // @[pla.scala:77:22, :90:45] wire decoded_andMatrixOutputs_andMatrixInput_2_10 = decoded_invInputs_1[2]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_3_10 = decoded_invInputs_1[3]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_4_10 = decoded_plaInput_1[4]; // @[pla.scala:77:22, :90:45] wire decoded_andMatrixOutputs_andMatrixInput_5_10 = decoded_plaInput_1[5]; // @[pla.scala:77:22, :90:45] wire decoded_andMatrixOutputs_andMatrixInput_6_10 = decoded_plaInput_1[6]; // @[pla.scala:77:22, :90:45] wire decoded_andMatrixOutputs_andMatrixInput_7_10 = decoded_invInputs_1[7]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_8_10 = decoded_invInputs_1[8]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_9_10 = decoded_invInputs_1[9]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_10_5 = decoded_plaInput_1[25]; // @[pla.scala:77:22, :90:45] wire [1:0] decoded_andMatrixOutputs_lo_lo_lo_1 = {decoded_andMatrixOutputs_andMatrixInput_15_1, decoded_andMatrixOutputs_andMatrixInput_16_1}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_andMatrixOutputs_lo_lo_hi_5 = {decoded_andMatrixOutputs_andMatrixInput_13_1, decoded_andMatrixOutputs_andMatrixInput_14_1}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoded_andMatrixOutputs_lo_lo_10 = {decoded_andMatrixOutputs_lo_lo_hi_5, decoded_andMatrixOutputs_lo_lo_lo_1}; // @[pla.scala:98:53] wire [1:0] decoded_andMatrixOutputs_lo_hi_lo_1 = {decoded_andMatrixOutputs_andMatrixInput_11_5, decoded_andMatrixOutputs_andMatrixInput_12_1}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_andMatrixOutputs_lo_hi_hi_10 = {decoded_andMatrixOutputs_andMatrixInput_9_10, decoded_andMatrixOutputs_andMatrixInput_10_5}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoded_andMatrixOutputs_lo_hi_10 = {decoded_andMatrixOutputs_lo_hi_hi_10, decoded_andMatrixOutputs_lo_hi_lo_1}; // @[pla.scala:98:53] wire [7:0] decoded_andMatrixOutputs_lo_10 = {decoded_andMatrixOutputs_lo_hi_10, decoded_andMatrixOutputs_lo_lo_10}; // @[pla.scala:98:53] wire [1:0] decoded_andMatrixOutputs_hi_lo_lo_1 = {decoded_andMatrixOutputs_andMatrixInput_7_10, decoded_andMatrixOutputs_andMatrixInput_8_10}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_andMatrixOutputs_hi_lo_hi_5 = {decoded_andMatrixOutputs_andMatrixInput_5_10, decoded_andMatrixOutputs_andMatrixInput_6_10}; // @[pla.scala:90:45, :98:53] wire [3:0] decoded_andMatrixOutputs_hi_lo_10 = {decoded_andMatrixOutputs_hi_lo_hi_5, decoded_andMatrixOutputs_hi_lo_lo_1}; // @[pla.scala:98:53] wire [1:0] decoded_andMatrixOutputs_hi_hi_lo_1 = {decoded_andMatrixOutputs_andMatrixInput_3_10, decoded_andMatrixOutputs_andMatrixInput_4_10}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoded_andMatrixOutputs_hi_hi_hi_hi_1 = {decoded_andMatrixOutputs_andMatrixInput_0_11, decoded_andMatrixOutputs_andMatrixInput_1_11}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_andMatrixOutputs_hi_hi_hi_10 = {decoded_andMatrixOutputs_hi_hi_hi_hi_1, decoded_andMatrixOutputs_andMatrixInput_2_10}; // @[pla.scala:91:29, :98:53] wire [4:0] decoded_andMatrixOutputs_hi_hi_10 = {decoded_andMatrixOutputs_hi_hi_hi_10, decoded_andMatrixOutputs_hi_hi_lo_1}; // @[pla.scala:98:53] wire [8:0] decoded_andMatrixOutputs_hi_10 = {decoded_andMatrixOutputs_hi_hi_10, decoded_andMatrixOutputs_hi_lo_10}; // @[pla.scala:98:53] wire [16:0] _decoded_andMatrixOutputs_T_11 = {decoded_andMatrixOutputs_hi_10, decoded_andMatrixOutputs_lo_10}; // @[pla.scala:98:53] wire decoded_andMatrixOutputs_0_2_1 = &_decoded_andMatrixOutputs_T_11; // @[pla.scala:98:{53,70}] wire _decoded_orMatrixOutputs_T_7 = decoded_andMatrixOutputs_0_2_1; // @[pla.scala:98:70, :114:36] wire decoded_andMatrixOutputs_andMatrixInput_7_11 = decoded_plaInput_1[29]; // @[pla.scala:77:22, :90:45] wire [1:0] decoded_andMatrixOutputs_lo_lo_11 = {decoded_andMatrixOutputs_andMatrixInput_8_11, decoded_andMatrixOutputs_andMatrixInput_9_11}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_andMatrixOutputs_lo_hi_hi_11 = {decoded_andMatrixOutputs_andMatrixInput_5_11, decoded_andMatrixOutputs_andMatrixInput_6_11}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_andMatrixOutputs_lo_hi_11 = {decoded_andMatrixOutputs_lo_hi_hi_11, decoded_andMatrixOutputs_andMatrixInput_7_11}; // @[pla.scala:90:45, :98:53] wire [4:0] decoded_andMatrixOutputs_lo_11 = {decoded_andMatrixOutputs_lo_hi_11, decoded_andMatrixOutputs_lo_lo_11}; // @[pla.scala:98:53] wire [1:0] decoded_andMatrixOutputs_hi_lo_11 = {decoded_andMatrixOutputs_andMatrixInput_3_11, decoded_andMatrixOutputs_andMatrixInput_4_11}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_andMatrixOutputs_hi_hi_hi_11 = {decoded_andMatrixOutputs_andMatrixInput_0_12, decoded_andMatrixOutputs_andMatrixInput_1_12}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_andMatrixOutputs_hi_hi_11 = {decoded_andMatrixOutputs_hi_hi_hi_11, decoded_andMatrixOutputs_andMatrixInput_2_11}; // @[pla.scala:91:29, :98:53] wire [4:0] decoded_andMatrixOutputs_hi_11 = {decoded_andMatrixOutputs_hi_hi_11, decoded_andMatrixOutputs_hi_lo_11}; // @[pla.scala:98:53] wire [9:0] _decoded_andMatrixOutputs_T_12 = {decoded_andMatrixOutputs_hi_11, decoded_andMatrixOutputs_lo_11}; // @[pla.scala:98:53] wire decoded_andMatrixOutputs_5_2_1 = &_decoded_andMatrixOutputs_T_12; // @[pla.scala:98:{53,70}] wire _decoded_orMatrixOutputs_T_9 = decoded_andMatrixOutputs_5_2_1; // @[pla.scala:98:70, :114:36] wire decoded_andMatrixOutputs_andMatrixInput_0_13 = decoded_plaInput_1[30]; // @[pla.scala:77:22, :90:45] wire [1:0] _decoded_andMatrixOutputs_T_13 = {decoded_andMatrixOutputs_andMatrixInput_0_13, decoded_andMatrixOutputs_andMatrixInput_1_13}; // @[pla.scala:90:45, :91:29, :98:53] wire decoded_andMatrixOutputs_2_2_1 = &_decoded_andMatrixOutputs_T_13; // @[pla.scala:98:{53,70}] wire [1:0] _decoded_orMatrixOutputs_T_10 = {decoded_andMatrixOutputs_3_2_1, decoded_andMatrixOutputs_2_2_1}; // @[pla.scala:98:70, :114:19] wire _decoded_orMatrixOutputs_T_11 = \|_decoded_orMatrixOutputs_T_10; // @[pla.scala:114:{19,36}] wire [1:0] decoded_orMatrixOutputs_lo_hi_1 = {_decoded_orMatrixOutputs_T_7, 1'h0}; // @[pla.scala:102:36, :114:36] wire [3:0] decoded_orMatrixOutputs_lo_1 = {decoded_orMatrixOutputs_lo_hi_1, 2'h0}; // @[pla.scala:102:36] wire [1:0] decoded_orMatrixOutputs_hi_lo_1 = {_decoded_orMatrixOutputs_T_9, _decoded_orMatrixOutputs_T_8}; // @[pla.scala:102:36, :114:36] wire [1:0] decoded_orMatrixOutputs_hi_hi_hi_1 = {_decoded_orMatrixOutputs_T_13, _decoded_orMatrixOutputs_T_12}; // @[pla.scala:102:36, :114:36] wire [2:0] decoded_orMatrixOutputs_hi_hi_1 = {decoded_orMatrixOutputs_hi_hi_hi_1, _decoded_orMatrixOutputs_T_11}; // @[pla.scala:102:36, :114:36] wire [4:0] decoded_orMatrixOutputs_hi_1 = {decoded_orMatrixOutputs_hi_hi_1, decoded_orMatrixOutputs_hi_lo_1}; // @[pla.scala:102:36] wire [8:0] decoded_orMatrixOutputs_1 = {decoded_orMatrixOutputs_hi_1, decoded_orMatrixOutputs_lo_1}; // @[pla.scala:102:36] wire _decoded_invMatrixOutputs_T_9 = decoded_orMatrixOutputs_1[0]; // @[pla.scala:102:36, :124:31] wire _decoded_invMatrixOutputs_T_10 = decoded_orMatrixOutputs_1[1]; // @[pla.scala:102:36, :124:31] wire _decoded_invMatrixOutputs_T_11 = decoded_orMatrixOutputs_1[2]; // @[pla.scala:102:36, :124:31] wire _decoded_invMatrixOutputs_T_12 = decoded_orMatrixOutputs_1[3]; // @[pla.scala:102:36, :124:31] wire _decoded_invMatrixOutputs_T_13 = decoded_orMatrixOutputs_1[4]; // @[pla.scala:102:36, :124:31] wire _decoded_invMatrixOutputs_T_14 = decoded_orMatrixOutputs_1[5]; // @[pla.scala:102:36, :124:31] wire _decoded_invMatrixOutputs_T_15 = decoded_orMatrixOutputs_1[6]; // @[pla.scala:102:36, :124:31] wire _decoded_invMatrixOutputs_T_16 = decoded_orMatrixOutputs_1[7]; // @[pla.scala:102:36, :124:31] wire _decoded_invMatrixOutputs_T_17 = decoded_orMatrixOutputs_1[8]; // @[pla.scala:102:36, :124:31] wire [1:0] decoded_invMatrixOutputs_lo_lo_1 = {_decoded_invMatrixOutputs_T_10, _decoded_invMatrixOutputs_T_9}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_invMatrixOutputs_lo_hi_1 = {_decoded_invMatrixOutputs_T_12, _decoded_invMatrixOutputs_T_11}; // @[pla.scala:120:37, :124:31] wire [3:0] decoded_invMatrixOutputs_lo_1 = {decoded_invMatrixOutputs_lo_hi_1, decoded_invMatrixOutputs_lo_lo_1}; // @[pla.scala:120:37] wire [1:0] decoded_invMatrixOutputs_hi_lo_1 = {_decoded_invMatrixOutputs_T_14, _decoded_invMatrixOutputs_T_13}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_invMatrixOutputs_hi_hi_hi_1 = {_decoded_invMatrixOutputs_T_17, _decoded_invMatrixOutputs_T_16}; // @[pla.scala:120:37, :124:31] wire [2:0] decoded_invMatrixOutputs_hi_hi_1 = {decoded_invMatrixOutputs_hi_hi_hi_1, _decoded_invMatrixOutputs_T_15}; // @[pla.scala:120:37, :124:31] wire [4:0] decoded_invMatrixOutputs_hi_1 = {decoded_invMatrixOutputs_hi_hi_1, decoded_invMatrixOutputs_hi_lo_1}; // @[pla.scala:120:37] assign decoded_invMatrixOutputs_1 = {decoded_invMatrixOutputs_hi_1, decoded_invMatrixOutputs_lo_1}; // @[pla.scala:120:37] assign decoded_1 = decoded_invMatrixOutputs_1; // @[pla.scala:81:23, :120:37] wire is_break = decoded_1[7]; // @[pla.scala:81:23] wire is_ret = decoded_1[6]; // @[pla.scala:81:23] wire is_wfi = decoded_1[4]; // @[pla.scala:81:23] wire is_sfence = decoded_1[3]; // @[pla.scala:81:23] wire is_hfence_vvma = decoded_1[2]; // @[pla.scala:81:23] wire is_hfence_gvma = decoded_1[1]; // @[pla.scala:81:23] wire is_hlsv = decoded_1[0]; // @[pla.scala:81:23] wire _is_counter_T = addr > 12'hBFF; // @[package.scala:213:47] wire _is_counter_T_1 = addr < 12'hC20; // @[package.scala:213:60] wire _is_counter_T_2 = _is_counter_T & _is_counter_T_1; // @[package.scala:213:{47,55,60}] wire _is_counter_T_3 = addr > 12'hC7F; // @[package.scala:213:47] wire _is_counter_T_4 = addr < 12'hCA0; // @[package.scala:213:60] wire _is_counter_T_5 = _is_counter_T_3 & _is_counter_T_4; // @[package.scala:213:{47,55,60}] wire is_counter = _is_counter_T_2 \| _is_counter_T_5; // @[package.scala:213:55] wire _allow_wfi_T_1 = _allow_wfi_T; // @[CSR.scala:906:{42,61}] wire _allow_wfi_T_2 = ~reg_mstatus_tw; // @[CSR.scala:395:28, :906:74] wire _allow_wfi_T_6 = _allow_wfi_T_2; // @[CSR.scala:906:{74,90}] wire _allow_wfi_T_3 = ~reg_mstatus_v; // @[CSR.scala:395:28, :906:94] wire allow_wfi = _allow_wfi_T_1 \| _allow_wfi_T_6; // @[CSR.scala:906:{42,71,90}] wire _allow_sfence_vma_T_1 = _allow_sfence_vma_T; // @[CSR.scala:907:{41,60}] wire _allow_sfence_vma_T_2 = ~reg_mstatus_v & reg_mstatus_tvm; // @[CSR.scala:395:28, :907:77] wire _allow_sfence_vma_T_3 = ~_allow_sfence_vma_T_2; // @[CSR.scala:907:{73,77}] wire allow_sfence_vma = _allow_sfence_vma_T_1 \| _allow_sfence_vma_T_3; // @[CSR.scala:907:{41,70,73}] wire _allow_hfence_vvma_T = ~reg_mstatus_v; // @[CSR.scala:395:28, :906:94, :908:53] wire _allow_hfence_vvma_T_1 = \|reg_mstatus_prv; // @[CSR.scala:395:28, :908:88] wire _allow_hfence_vvma_T_2 = _allow_hfence_vvma_T & _allow_hfence_vvma_T_1; // @[CSR.scala:908:{53,68,88}] wire _allow_hlsv_T = ~reg_mstatus_v; // @[CSR.scala:395:28, :906:94, :909:46] wire _allow_hlsv_T_1 = \|reg_mstatus_prv; // @[CSR.scala:395:28, :908:88, :909:81] wire _allow_hlsv_T_2 = _allow_hlsv_T_1; // @[CSR.scala:909:{81,92}] wire _allow_hlsv_T_3 = _allow_hlsv_T & _allow_hlsv_T_2; // @[CSR.scala:909:{46,61,92}] wire _allow_sret_T_1 = _allow_sret_T; // @[CSR.scala:910:{43,62}] wire _allow_sret_T_2 = ~reg_mstatus_v & reg_mstatus_tsr; // @[CSR.scala:395:28, :907:77, :910:79] wire _allow_sret_T_3 = ~_allow_sret_T_2; // @[CSR.scala:910:{75,79}] wire allow_sret = _allow_sret_T_1 \| _allow_sret_T_3; // @[CSR.scala:910:{43,72,75}] wire [4:0] counter_addr = addr[4:0]; // @[CSR.scala:897:27, :911:28] wire [31:0] _GEN_4 = {27'h0, counter_addr}; // @[CSR.scala:911:28, :912:70] wire [31:0] _GEN_5 = read_mcounteren >> _GEN_4; // @[CSR.scala:532:14, :912:70] wire [31:0] _allow_counter_T_1; // @[CSR.scala:912:70] assign _allow_counter_T_1 = _GEN_5; // @[CSR.scala:912:70] wire [31:0] _io_decode_0_virtual_access_illegal_T_3; // @[CSR.scala:945:36] assign _io_decode_0_virtual_access_illegal_T_3 = _GEN_5; // @[CSR.scala:912:70, :945:36] wire _allow_counter_T_2 = _allow_counter_T_1[0]; // @[CSR.scala:912:70] wire _allow_counter_T_3 = _allow_counter_T \| _allow_counter_T_2; // @[CSR.scala:912:{42,52,70}] wire _allow_counter_T_5 = \|reg_mstatus_prv; // @[CSR.scala:395:28, :908:88, :913:46] wire _allow_counter_T_6 = _allow_counter_T_5; // @[CSR.scala:913:{27,46}] wire [31:0] _GEN_6 = read_scounteren >> _GEN_4; // @[CSR.scala:536:14, :912:70, :913:75] wire [31:0] _allow_counter_T_7; // @[CSR.scala:913:75] assign _allow_counter_T_7 = _GEN_6; // @[CSR.scala:913:75] wire [31:0] _io_decode_0_virtual_access_illegal_T_11; // @[CSR.scala:945:128] assign _io_decode_0_virtual_access_illegal_T_11 = _GEN_6; // @[CSR.scala:913:75, :945:128] wire _allow_counter_T_8 = _allow_counter_T_7[0]; // @[CSR.scala:913:75] wire _allow_counter_T_9 = _allow_counter_T_6 \| _allow_counter_T_8; // @[CSR.scala:913:{27,57,75}] wire _allow_counter_T_10 = _allow_counter_T_3 & _allow_counter_T_9; // @[CSR.scala:912:{52,86}, :913:57] wire allow_counter = _allow_counter_T_10; // @[CSR.scala:912:86, :913:91] wire _allow_counter_T_12 = ~reg_mstatus_v; // @[CSR.scala:395:28, :906:94, :914:30] wire [31:0] _GEN_7 = 32'h0 >> _GEN_4; // @[CSR.scala:912:70, :914:63] wire [31:0] _allow_counter_T_14; // @[CSR.scala:914:63] assign _allow_counter_T_14 = _GEN_7; // @[CSR.scala:914:63] wire [31:0] _io_decode_0_virtual_access_illegal_T_6; // @[CSR.scala:945:71] assign _io_decode_0_virtual_access_illegal_T_6 = _GEN_7; // @[CSR.scala:914:63, :945:71] wire _allow_counter_T_15 = _allow_counter_T_14[0]; // @[CSR.scala:914:63] wire _io_decode_0_fp_illegal_T = io_status_fs_0 == 2'h0; // @[CSR.scala:377:7, :915:39] wire _io_decode_0_fp_illegal_T_3 = _io_decode_0_fp_illegal_T; // @[CSR.scala:915:{39,47}] assign _io_decode_0_fp_illegal_T_6 = _io_decode_0_fp_illegal_T_3; // @[CSR.scala:915:{47,91}] assign io_decode_0_fp_illegal_0 = _io_decode_0_fp_illegal_T_6; // @[CSR.scala:377:7, :915:91] wire _io_decode_0_vector_illegal_T_2 = reg_mstatus_v & _io_decode_0_vector_illegal_T_1; // @[CSR.scala:395:28, :916:{68,87}] wire [11:0] io_decode_0_fp_csr_invInputs = ~io_decode_0_fp_csr_plaInput; // @[pla.scala:77:22, :78:21] wire io_decode_0_fp_csr_invMatrixOutputs; // @[pla.scala:124:31] wire io_decode_0_fp_csr_plaOutput; // @[pla.scala:81:23] assign _io_decode_0_fp_csr_T = io_decode_0_fp_csr_plaOutput; // @[pla.scala:81:23] wire io_decode_0_fp_csr_andMatrixOutputs_andMatrixInput_0 = io_decode_0_fp_csr_invInputs[8]; // @[pla.scala:78:21, :91:29] wire io_decode_0_fp_csr_andMatrixOutputs_andMatrixInput_1 = io_decode_0_fp_csr_invInputs[9]; // @[pla.scala:78:21, :91:29] wire io_decode_0_fp_csr_andMatrixOutputs_andMatrixInput_2 = io_decode_0_fp_csr_invInputs[10]; // @[pla.scala:78:21, :91:29] wire io_decode_0_fp_csr_andMatrixOutputs_andMatrixInput_3 = io_decode_0_fp_csr_invInputs[11]; // @[pla.scala:78:21, :91:29] wire [1:0] io_decode_0_fp_csr_andMatrixOutputs_lo = {io_decode_0_fp_csr_andMatrixOutputs_andMatrixInput_2, io_decode_0_fp_csr_andMatrixOutputs_andMatrixInput_3}; // @[pla.scala:91:29, :98:53] wire [1:0] io_decode_0_fp_csr_andMatrixOutputs_hi = {io_decode_0_fp_csr_andMatrixOutputs_andMatrixInput_0, io_decode_0_fp_csr_andMatrixOutputs_andMatrixInput_1}; // @[pla.scala:91:29, :98:53] wire [3:0] _io_decode_0_fp_csr_andMatrixOutputs_T = {io_decode_0_fp_csr_andMatrixOutputs_hi, io_decode_0_fp_csr_andMatrixOutputs_lo}; // @[pla.scala:98:53] wire io_decode_0_fp_csr_andMatrixOutputs_0_2 = &_io_decode_0_fp_csr_andMatrixOutputs_T; // @[pla.scala:98:{53,70}] wire io_decode_0_fp_csr_orMatrixOutputs = io_decode_0_fp_csr_andMatrixOutputs_0_2; // @[pla.scala:98:70, :114:36] assign io_decode_0_fp_csr_invMatrixOutputs = io_decode_0_fp_csr_orMatrixOutputs; // @[pla.scala:114:36, :124:31] assign io_decode_0_fp_csr_plaOutput = io_decode_0_fp_csr_invMatrixOutputs; // @[pla.scala:81:23, :124:31] assign io_decode_0_fp_csr_0 = _io_decode_0_fp_csr_T; // @[Decode.scala:55:116] wire [11:0] io_decode_0_vector_csr_invInputs = ~io_decode_0_vector_csr_plaInput; // @[pla.scala:77:22, :78:21] wire [1:0] _csr_addr_legal_T = addr[9:8]; // @[CSR.scala:190:36, :897:27] wire [1:0] _csr_addr_legal_T_6 = addr[9:8]; // @[CSR.scala:190:36, :897:27] wire [1:0] _io_decode_0_virtual_access_illegal_T_1 = addr[9:8]; // @[CSR.scala:190:36, :897:27] wire [1:0] _io_decode_0_virtual_access_illegal_T_18 = addr[9:8]; // @[CSR.scala:190:36, :897:27] wire [1:0] _io_decode_0_virtual_system_illegal_T_9 = addr[9:8]; // @[CSR.scala:190:36, :897:27] wire _csr_addr_legal_T_1 = reg_mstatus_prv >= _csr_addr_legal_T; // @[CSR.scala:190:36, :395:28, :920:42] wire csr_addr_legal = _csr_addr_legal_T_1; // @[CSR.scala:920:{42,60}] wire _csr_addr_legal_T_2 = ~reg_mstatus_v; // @[CSR.scala:395:28, :906:94, :921:28] wire _csr_addr_legal_T_7 = _csr_addr_legal_T_6 == 2'h2; // @[CSR.scala:190:36, :921:92] wire _csr_exists_T = addr == 12'h7A0; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_1 = addr == 12'h7A1; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_2 = addr == 12'h7A2; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_3 = addr == 12'h7A3; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_4 = addr == 12'h301; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_5 = addr == 12'h300; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_6 = addr == 12'h305; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_7 = addr == 12'h344; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_8 = addr == 12'h304; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_9 = addr == 12'h340; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_10 = addr == 12'h341; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_11 = addr == 12'h343; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_12 = addr == 12'h342; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_13 = addr == 12'hF14; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_14 = addr == 12'h7B0; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_15 = addr == 12'h7B1; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_16 = addr == 12'h7B2; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_17 = addr == 12'h1; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_18 = addr == 12'h2; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_19 = addr == 12'h3; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_20 = addr == 12'h320; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_21 = addr == 12'hB00; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_22 = addr == 12'hB02; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_23 = addr == 12'h323; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_24 = addr == 12'hB03; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_25 = addr == 12'hC03; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_26 = addr == 12'h324; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_27 = addr == 12'hB04; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_28 = addr == 12'hC04; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_29 = addr == 12'h325; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_30 = addr == 12'hB05; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_31 = addr == 12'hC05; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_32 = addr == 12'h326; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_33 = addr == 12'hB06; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_34 = addr == 12'hC06; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_35 = addr == 12'h327; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_36 = addr == 12'hB07; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_37 = addr == 12'hC07; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_38 = addr == 12'h328; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_39 = addr == 12'hB08; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_40 = addr == 12'hC08; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_41 = addr == 12'h329; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_42 = addr == 12'hB09; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_43 = addr == 12'hC09; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_44 = addr == 12'h32A; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_45 = addr == 12'hB0A; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_46 = addr == 12'hC0A; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_47 = addr == 12'h32B; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_48 = addr == 12'hB0B; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_49 = addr == 12'hC0B; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_50 = addr == 12'h32C; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_51 = addr == 12'hB0C; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_52 = addr == 12'hC0C; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_53 = addr == 12'h32D; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_54 = addr == 12'hB0D; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_55 = addr == 12'hC0D; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_56 = addr == 12'h32E; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_57 = addr == 12'hB0E; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_58 = addr == 12'hC0E; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_59 = addr == 12'h32F; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_60 = addr == 12'hB0F; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_61 = addr == 12'hC0F; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_62 = addr == 12'h330; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_63 = addr == 12'hB10; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_64 = addr == 12'hC10; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_65 = addr == 12'h331; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_66 = addr == 12'hB11; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_67 = addr == 12'hC11; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_68 = addr == 12'h332; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_69 = addr == 12'hB12; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_70 = addr == 12'hC12; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_71 = addr == 12'h333; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_72 = addr == 12'hB13; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_73 = addr == 12'hC13; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_74 = addr == 12'h334; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_75 = addr == 12'hB14; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_76 = addr == 12'hC14; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_77 = addr == 12'h335; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_78 = addr == 12'hB15; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_79 = addr == 12'hC15; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_80 = addr == 12'h336; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_81 = addr == 12'hB16; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_82 = addr == 12'hC16; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_83 = addr == 12'h337; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_84 = addr == 12'hB17; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_85 = addr == 12'hC17; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_86 = addr == 12'h338; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_87 = addr == 12'hB18; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_88 = addr == 12'hC18; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_89 = addr == 12'h339; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_90 = addr == 12'hB19; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_91 = addr == 12'hC19; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_92 = addr == 12'h33A; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_93 = addr == 12'hB1A; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_94 = addr == 12'hC1A; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_95 = addr == 12'h33B; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_96 = addr == 12'hB1B; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_97 = addr == 12'hC1B; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_98 = addr == 12'h33C; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_99 = addr == 12'hB1C; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_100 = addr == 12'hC1C; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_101 = addr == 12'h33D; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_102 = addr == 12'hB1D; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_103 = addr == 12'hC1D; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_104 = addr == 12'h33E; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_105 = addr == 12'hB1E; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_106 = addr == 12'hC1E; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_107 = addr == 12'h33F; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_108 = addr == 12'hB1F; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_109 = addr == 12'hC1F; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_110 = addr == 12'h306; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_111 = addr == 12'hC00; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_112 = addr == 12'hC02; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_113 = addr == 12'h30A; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_114 = addr == 12'h100; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_115 = addr == 12'h144; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_116 = addr == 12'h104; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_117 = addr == 12'h140; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_118 = addr == 12'h142; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_119 = addr == 12'h143; // @[CSR.scala:897:27, :899:93] wire _GEN_8 = addr == 12'h180; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_120; // @[CSR.scala:899:93] assign _csr_exists_T_120 = _GEN_8; // @[CSR.scala:899:93] wire _io_decode_0_read_illegal_T_3; // @[CSR.scala:925:14] assign _io_decode_0_read_illegal_T_3 = _GEN_8; // @[CSR.scala:899:93, :925:14] wire _io_decode_0_virtual_access_illegal_T_24; // @[CSR.scala:947:12] assign _io_decode_0_virtual_access_illegal_T_24 = _GEN_8; // @[CSR.scala:899:93, :947:12] wire _csr_exists_T_121 = addr == 12'h141; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_122 = addr == 12'h105; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_123 = addr == 12'h106; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_124 = addr == 12'h303; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_125 = addr == 12'h302; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_126 = addr == 12'h10A; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_127 = addr == 12'h3A0; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_128 = addr == 12'h3A2; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_129 = addr == 12'h3B0; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_130 = addr == 12'h3B1; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_131 = addr == 12'h3B2; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_132 = addr == 12'h3B3; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_133 = addr == 12'h3B4; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_134 = addr == 12'h3B5; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_135 = addr == 12'h3B6; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_136 = addr == 12'h3B7; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_137 = addr == 12'h3B8; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_138 = addr == 12'h3B9; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_139 = addr == 12'h3BA; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_140 = addr == 12'h3BB; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_141 = addr == 12'h3BC; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_142 = addr == 12'h3BD; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_143 = addr == 12'h3BE; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_144 = addr == 12'h3BF; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_145 = addr == 12'h7C1; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_146 = addr == 12'hF12; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_147 = addr == 12'hF13; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_148 = addr == 12'hF11; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_149 = addr == 12'hF15; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_150 = _csr_exists_T \| _csr_exists_T_1; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_151 = _csr_exists_T_150 \| _csr_exists_T_2; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_152 = _csr_exists_T_151 \| _csr_exists_T_3; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_153 = _csr_exists_T_152 \| _csr_exists_T_4; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_154 = _csr_exists_T_153 \| _csr_exists_T_5; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_155 = _csr_exists_T_154 \| _csr_exists_T_6; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_156 = _csr_exists_T_155 \| _csr_exists_T_7; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_157 = _csr_exists_T_156 \| _csr_exists_T_8; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_158 = _csr_exists_T_157 \| _csr_exists_T_9; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_159 = _csr_exists_T_158 \| _csr_exists_T_10; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_160 = _csr_exists_T_159 \| _csr_exists_T_11; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_161 = _csr_exists_T_160 \| _csr_exists_T_12; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_162 = _csr_exists_T_161 \| _csr_exists_T_13; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_163 = _csr_exists_T_162 \| _csr_exists_T_14; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_164 = _csr_exists_T_163 \| _csr_exists_T_15; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_165 = _csr_exists_T_164 \| _csr_exists_T_16; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_166 = _csr_exists_T_165 \| _csr_exists_T_17; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_167 = _csr_exists_T_166 \| _csr_exists_T_18; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_168 = _csr_exists_T_167 \| _csr_exists_T_19; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_169 = _csr_exists_T_168 \| _csr_exists_T_20; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_170 = _csr_exists_T_169 \| _csr_exists_T_21; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_171 = _csr_exists_T_170 \| _csr_exists_T_22; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_172 = _csr_exists_T_171 \| _csr_exists_T_23; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_173 = _csr_exists_T_172 \| _csr_exists_T_24; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_174 = _csr_exists_T_173 \| _csr_exists_T_25; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_175 = _csr_exists_T_174 \| _csr_exists_T_26; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_176 = _csr_exists_T_175 \| _csr_exists_T_27; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_177 = _csr_exists_T_176 \| _csr_exists_T_28; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_178 = _csr_exists_T_177 \| _csr_exists_T_29; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_179 = _csr_exists_T_178 \| _csr_exists_T_30; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_180 = _csr_exists_T_179 \| _csr_exists_T_31; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_181 = _csr_exists_T_180 \| _csr_exists_T_32; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_182 = _csr_exists_T_181 \| _csr_exists_T_33; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_183 = _csr_exists_T_182 \| _csr_exists_T_34; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_184 = _csr_exists_T_183 \| _csr_exists_T_35; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_185 = _csr_exists_T_184 \| _csr_exists_T_36; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_186 = _csr_exists_T_185 \| _csr_exists_T_37; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_187 = _csr_exists_T_186 \| _csr_exists_T_38; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_188 = _csr_exists_T_187 \| _csr_exists_T_39; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_189 = _csr_exists_T_188 \| _csr_exists_T_40; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_190 = _csr_exists_T_189 \| _csr_exists_T_41; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_191 = _csr_exists_T_190 \| _csr_exists_T_42; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_192 = _csr_exists_T_191 \| _csr_exists_T_43; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_193 = _csr_exists_T_192 \| _csr_exists_T_44; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_194 = _csr_exists_T_193 \| _csr_exists_T_45; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_195 = _csr_exists_T_194 \| _csr_exists_T_46; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_196 = _csr_exists_T_195 \| _csr_exists_T_47; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_197 = _csr_exists_T_196 \| _csr_exists_T_48; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_198 = _csr_exists_T_197 \| _csr_exists_T_49; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_199 = _csr_exists_T_198 \| _csr_exists_T_50; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_200 = _csr_exists_T_199 \| _csr_exists_T_51; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_201 = _csr_exists_T_200 \| _csr_exists_T_52; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_202 = _csr_exists_T_201 \| _csr_exists_T_53; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_203 = _csr_exists_T_202 \| _csr_exists_T_54; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_204 = _csr_exists_T_203 \| _csr_exists_T_55; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_205 = _csr_exists_T_204 \| _csr_exists_T_56; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_206 = _csr_exists_T_205 \| _csr_exists_T_57; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_207 = _csr_exists_T_206 \| _csr_exists_T_58; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_208 = _csr_exists_T_207 \| _csr_exists_T_59; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_209 = _csr_exists_T_208 \| _csr_exists_T_60; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_210 = _csr_exists_T_209 \| _csr_exists_T_61; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_211 = _csr_exists_T_210 \| _csr_exists_T_62; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_212 = _csr_exists_T_211 \| _csr_exists_T_63; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_213 = _csr_exists_T_212 \| _csr_exists_T_64; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_214 = _csr_exists_T_213 \| _csr_exists_T_65; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_215 = _csr_exists_T_214 \| _csr_exists_T_66; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_216 = _csr_exists_T_215 \| _csr_exists_T_67; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_217 = _csr_exists_T_216 \| _csr_exists_T_68; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_218 = _csr_exists_T_217 \| _csr_exists_T_69; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_219 = _csr_exists_T_218 \| _csr_exists_T_70; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_220 = _csr_exists_T_219 \| _csr_exists_T_71; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_221 = _csr_exists_T_220 \| _csr_exists_T_72; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_222 = _csr_exists_T_221 \| _csr_exists_T_73; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_223 = _csr_exists_T_222 \| _csr_exists_T_74; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_224 = _csr_exists_T_223 \| _csr_exists_T_75; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_225 = _csr_exists_T_224 \| _csr_exists_T_76; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_226 = _csr_exists_T_225 \| _csr_exists_T_77; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_227 = _csr_exists_T_226 \| _csr_exists_T_78; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_228 = _csr_exists_T_227 \| _csr_exists_T_79; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_229 = _csr_exists_T_228 \| _csr_exists_T_80; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_230 = _csr_exists_T_229 \| _csr_exists_T_81; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_231 = _csr_exists_T_230 \| _csr_exists_T_82; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_232 = _csr_exists_T_231 \| _csr_exists_T_83; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_233 = _csr_exists_T_232 \| _csr_exists_T_84; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_234 = _csr_exists_T_233 \| _csr_exists_T_85; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_235 = _csr_exists_T_234 \| _csr_exists_T_86; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_236 = _csr_exists_T_235 \| _csr_exists_T_87; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_237 = _csr_exists_T_236 \| _csr_exists_T_88; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_238 = _csr_exists_T_237 \| _csr_exists_T_89; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_239 = _csr_exists_T_238 \| _csr_exists_T_90; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_240 = _csr_exists_T_239 \| _csr_exists_T_91; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_241 = _csr_exists_T_240 \| _csr_exists_T_92; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_242 = _csr_exists_T_241 \| _csr_exists_T_93; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_243 = _csr_exists_T_242 \| _csr_exists_T_94; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_244 = _csr_exists_T_243 \| _csr_exists_T_95; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_245 = _csr_exists_T_244 \| _csr_exists_T_96; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_246 = _csr_exists_T_245 \| _csr_exists_T_97; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_247 = _csr_exists_T_246 \| _csr_exists_T_98; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_248 = _csr_exists_T_247 \| _csr_exists_T_99; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_249 = _csr_exists_T_248 \| _csr_exists_T_100; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_250 = _csr_exists_T_249 \| _csr_exists_T_101; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_251 = _csr_exists_T_250 \| _csr_exists_T_102; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_252 = _csr_exists_T_251 \| _csr_exists_T_103; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_253 = _csr_exists_T_252 \| _csr_exists_T_104; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_254 = _csr_exists_T_253 \| _csr_exists_T_105; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_255 = _csr_exists_T_254 \| _csr_exists_T_106; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_256 = _csr_exists_T_255 \| _csr_exists_T_107; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_257 = _csr_exists_T_256 \| _csr_exists_T_108; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_258 = _csr_exists_T_257 \| _csr_exists_T_109; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_259 = _csr_exists_T_258 \| _csr_exists_T_110; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_260 = _csr_exists_T_259 \| _csr_exists_T_111; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_261 = _csr_exists_T_260 \| _csr_exists_T_112; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_262 = _csr_exists_T_261 \| _csr_exists_T_113; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_263 = _csr_exists_T_262 \| _csr_exists_T_114; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_264 = _csr_exists_T_263 \| _csr_exists_T_115; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_265 = _csr_exists_T_264 \| _csr_exists_T_116; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_266 = _csr_exists_T_265 \| _csr_exists_T_117; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_267 = _csr_exists_T_266 \| _csr_exists_T_118; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_268 = _csr_exists_T_267 \| _csr_exists_T_119; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_269 = _csr_exists_T_268 \| _csr_exists_T_120; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_270 = _csr_exists_T_269 \| _csr_exists_T_121; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_271 = _csr_exists_T_270 \| _csr_exists_T_122; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_272 = _csr_exists_T_271 \| _csr_exists_T_123; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_273 = _csr_exists_T_272 \| _csr_exists_T_124; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_274 = _csr_exists_T_273 \| _csr_exists_T_125; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_275 = _csr_exists_T_274 \| _csr_exists_T_126; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_276 = _csr_exists_T_275 \| _csr_exists_T_127; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_277 = _csr_exists_T_276 \| _csr_exists_T_128; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_278 = _csr_exists_T_277 \| _csr_exists_T_129; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_279 = _csr_exists_T_278 \| _csr_exists_T_130; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_280 = _csr_exists_T_279 \| _csr_exists_T_131; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_281 = _csr_exists_T_280 \| _csr_exists_T_132; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_282 = _csr_exists_T_281 \| _csr_exists_T_133; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_283 = _csr_exists_T_282 \| _csr_exists_T_134; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_284 = _csr_exists_T_283 \| _csr_exists_T_135; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_285 = _csr_exists_T_284 \| _csr_exists_T_136; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_286 = _csr_exists_T_285 \| _csr_exists_T_137; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_287 = _csr_exists_T_286 \| _csr_exists_T_138; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_288 = _csr_exists_T_287 \| _csr_exists_T_139; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_289 = _csr_exists_T_288 \| _csr_exists_T_140; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_290 = _csr_exists_T_289 \| _csr_exists_T_141; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_291 = _csr_exists_T_290 \| _csr_exists_T_142; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_292 = _csr_exists_T_291 \| _csr_exists_T_143; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_293 = _csr_exists_T_292 \| _csr_exists_T_144; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_294 = _csr_exists_T_293 \| _csr_exists_T_145; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_295 = _csr_exists_T_294 \| _csr_exists_T_146; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_296 = _csr_exists_T_295 \| _csr_exists_T_147; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_297 = _csr_exists_T_296 \| _csr_exists_T_148; // @[CSR.scala:899:{93,111}] wire csr_exists = _csr_exists_T_297 \| _csr_exists_T_149; // @[CSR.scala:899:{93,111}] wire _io_decode_0_read_illegal_T = ~csr_addr_legal; // @[CSR.scala:920:60, :923:28] wire _io_decode_0_read_illegal_T_1 = ~csr_exists; // @[CSR.scala:899:111, :924:7] wire _io_decode_0_read_illegal_T_2 = _io_decode_0_read_illegal_T \| _io_decode_0_read_illegal_T_1; // @[CSR.scala:923:{28,44}, :924:7] wire _io_decode_0_read_illegal_T_4 = addr == 12'h680; // @[CSR.scala:897:27, :925:38] wire _io_decode_0_read_illegal_T_5 = _io_decode_0_read_illegal_T_3 \| _io_decode_0_read_illegal_T_4; // @[CSR.scala:925:{14,30,38}] wire _io_decode_0_read_illegal_T_6 = ~allow_sfence_vma; // @[CSR.scala:907:70, :925:59] wire _io_decode_0_read_illegal_T_7 = _io_decode_0_read_illegal_T_5 & _io_decode_0_read_illegal_T_6; // @[CSR.scala:925:{30,56,59}] wire _io_decode_0_read_illegal_T_8 = _io_decode_0_read_illegal_T_2 \| _io_decode_0_read_illegal_T_7; // @[CSR.scala:923:44, :924:19, :925:56] wire _io_decode_0_read_illegal_T_9 = ~allow_counter; // @[CSR.scala:913:91, :926:21] wire _io_decode_0_read_illegal_T_10 = is_counter & _io_decode_0_read_illegal_T_9; // @[CSR.scala:904:81, :926:{18,21}] wire _io_decode_0_read_illegal_T_11 = _io_decode_0_read_illegal_T_8 \| _io_decode_0_read_illegal_T_10; // @[CSR.scala:924:19, :925:78, :926:18] wire [11:0] io_decode_0_read_illegal_invInputs = ~io_decode_0_read_illegal_plaInput; // @[pla.scala:77:22, :78:21] wire io_decode_0_read_illegal_invMatrixOutputs; // @[pla.scala:124:31] wire io_decode_0_read_illegal_plaOutput; // @[pla.scala:81:23] wire _io_decode_0_read_illegal_T_12 = io_decode_0_read_illegal_plaOutput; // @[pla.scala:81:23] wire io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_0 = io_decode_0_read_illegal_plaInput[4]; // @[pla.scala:77:22, :90:45] wire io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_1 = io_decode_0_read_illegal_plaInput[5]; // @[pla.scala:77:22, :90:45] wire io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_2 = io_decode_0_read_illegal_invInputs[6]; // @[pla.scala:78:21, :91:29] wire io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_3 = io_decode_0_read_illegal_plaInput[7]; // @[pla.scala:77:22, :90:45] wire io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_4 = io_decode_0_read_illegal_plaInput[8]; // @[pla.scala:77:22, :90:45] wire io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_5 = io_decode_0_read_illegal_plaInput[9]; // @[pla.scala:77:22, :90:45] wire io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_6 = io_decode_0_read_illegal_plaInput[10]; // @[pla.scala:77:22, :90:45] wire io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_7 = io_decode_0_read_illegal_invInputs[11]; // @[pla.scala:78:21, :91:29] wire [1:0] io_decode_0_read_illegal_andMatrixOutputs_lo_lo = {io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_6, io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_7}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] io_decode_0_read_illegal_andMatrixOutputs_lo_hi = {io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_4, io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_5}; // @[pla.scala:90:45, :98:53] wire [3:0] io_decode_0_read_illegal_andMatrixOutputs_lo = {io_decode_0_read_illegal_andMatrixOutputs_lo_hi, io_decode_0_read_illegal_andMatrixOutputs_lo_lo}; // @[pla.scala:98:53] wire [1:0] io_decode_0_read_illegal_andMatrixOutputs_hi_lo = {io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_2, io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_3}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] io_decode_0_read_illegal_andMatrixOutputs_hi_hi = {io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_0, io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_1}; // @[pla.scala:90:45, :98:53] wire [3:0] io_decode_0_read_illegal_andMatrixOutputs_hi = {io_decode_0_read_illegal_andMatrixOutputs_hi_hi, io_decode_0_read_illegal_andMatrixOutputs_hi_lo}; // @[pla.scala:98:53] wire [7:0] _io_decode_0_read_illegal_andMatrixOutputs_T = {io_decode_0_read_illegal_andMatrixOutputs_hi, io_decode_0_read_illegal_andMatrixOutputs_lo}; // @[pla.scala:98:53] wire io_decode_0_read_illegal_andMatrixOutputs_0_2 = &_io_decode_0_read_illegal_andMatrixOutputs_T; // @[pla.scala:98:{53,70}] wire io_decode_0_read_illegal_orMatrixOutputs = io_decode_0_read_illegal_andMatrixOutputs_0_2; // @[pla.scala:98:70, :114:36] assign io_decode_0_read_illegal_invMatrixOutputs = io_decode_0_read_illegal_orMatrixOutputs; // @[pla.scala:114:36, :124:31] assign io_decode_0_read_illegal_plaOutput = io_decode_0_read_illegal_invMatrixOutputs; // @[pla.scala:81:23, :124:31] wire _io_decode_0_read_illegal_T_13 = ~reg_debug; // @[CSR.scala:482:26, :927:45] wire _io_decode_0_read_illegal_T_14 = _io_decode_0_read_illegal_T_12 & _io_decode_0_read_illegal_T_13; // @[Decode.scala:55:116] wire _io_decode_0_read_illegal_T_15 = _io_decode_0_read_illegal_T_11 \| _io_decode_0_read_illegal_T_14; // @[CSR.scala:925:78, :926:36, :927:42] wire _io_decode_0_read_illegal_T_18 = _io_decode_0_read_illegal_T_15; // @[CSR.scala:926:36, :927:56] wire [11:0] io_decode_0_read_illegal_invInputs_1 = ~io_decode_0_read_illegal_plaInput_1; // @[pla.scala:77:22, :78:21] wire _io_decode_0_read_illegal_T_19 = io_decode_0_fp_csr_0 & io_decode_0_fp_illegal_0; // @[CSR.scala:377:7, :929:21] assign _io_decode_0_read_illegal_T_20 = _io_decode_0_read_illegal_T_18 \| _io_decode_0_read_illegal_T_19; // @[CSR.scala:927:56, :928:68, :929:21] assign io_decode_0_read_illegal_0 = _io_decode_0_read_illegal_T_20; // @[CSR.scala:377:7, :928:68] wire [1:0] _io_decode_0_write_illegal_T = addr[11:10]; // @[CSR.scala:897:27, :930:33] assign _io_decode_0_write_illegal_T_1 = &_io_decode_0_write_illegal_T; // @[CSR.scala:930:{33,41}] assign io_decode_0_write_illegal_0 = _io_decode_0_write_illegal_T_1; // @[CSR.scala:377:7, :930:41] wire [11:0] io_decode_0_write_flush_addr_m = {_io_decode_0_write_illegal_T, addr[9:0] \| 10'h300}; // @[CSR.scala:897:27, :930:33, :932:25] wire _io_decode_0_write_flush_T = io_decode_0_write_flush_addr_m > 12'h33F; // @[CSR.scala:932:25, :933:16] wire _io_decode_0_write_flush_T_1 = io_decode_0_write_flush_addr_m < 12'h344; // @[CSR.scala:932:25, :933:45] wire _io_decode_0_write_flush_T_2 = _io_decode_0_write_flush_T & _io_decode_0_write_flush_T_1; // @[CSR.scala:933:{16,35,45}] assign _io_decode_0_write_flush_T_3 = ~_io_decode_0_write_flush_T_2; // @[CSR.scala:933:{7,35}] assign io_decode_0_write_flush_0 = _io_decode_0_write_flush_T_3; // @[CSR.scala:377:7, :933:7] wire _io_decode_0_system_illegal_T = ~csr_addr_legal; // @[CSR.scala:920:60, :923:28, :935:30] wire _io_decode_0_system_illegal_T_1 = ~is_hlsv; // @[CSR.scala:903:82, :935:49] wire _io_decode_0_system_illegal_T_2 = _io_decode_0_system_illegal_T & _io_decode_0_system_illegal_T_1; // @[CSR.scala:935:{30,46,49}] wire _io_decode_0_system_illegal_T_3 = ~allow_wfi; // @[CSR.scala:906:71, :936:17] wire _io_decode_0_system_illegal_T_4 = is_wfi & _io_decode_0_system_illegal_T_3; // @[CSR.scala:903:82, :936:{14,17}] wire _io_decode_0_system_illegal_T_5 = _io_decode_0_system_illegal_T_2 \| _io_decode_0_system_illegal_T_4; // @[CSR.scala:935:{46,58}, :936:14] wire _io_decode_0_system_illegal_T_6 = ~allow_sret; // @[CSR.scala:910:72, :937:17] wire _io_decode_0_system_illegal_T_7 = is_ret & _io_decode_0_system_illegal_T_6; // @[CSR.scala:903:82, :937:{14,17}] wire _io_decode_0_system_illegal_T_8 = _io_decode_0_system_illegal_T_5 \| _io_decode_0_system_illegal_T_7; // @[CSR.scala:935:58, :936:28, :937:14] wire _io_decode_0_system_illegal_T_9 = addr[10]; // @[CSR.scala:897:27, :938:21] wire _io_decode_0_system_illegal_T_10 = is_ret & _io_decode_0_system_illegal_T_9; // @[CSR.scala:903:82, :938:{14,21}] wire _io_decode_0_system_illegal_T_11 = addr[7]; // @[CSR.scala:897:27, :938:33] wire _io_decode_0_system_illegal_T_12 = _io_decode_0_system_illegal_T_10 & _io_decode_0_system_illegal_T_11; // @[CSR.scala:938:{14,26,33}] wire _io_decode_0_system_illegal_T_13 = ~reg_debug; // @[CSR.scala:482:26, :927:45, :938:40] wire _io_decode_0_system_illegal_T_14 = _io_decode_0_system_illegal_T_12 & _io_decode_0_system_illegal_T_13; // @[CSR.scala:938:{26,37,40}] wire _io_decode_0_system_illegal_T_15 = _io_decode_0_system_illegal_T_8 \| _io_decode_0_system_illegal_T_14; // @[CSR.scala:936:28, :937:29, :938:37] wire _io_decode_0_system_illegal_T_16 = is_sfence \| is_hfence_gvma; // @[CSR.scala:903:82, :939:18] wire _io_decode_0_system_illegal_T_17 = ~allow_sfence_vma; // @[CSR.scala:907:70, :925:59, :939:40] wire _io_decode_0_system_illegal_T_18 = _io_decode_0_system_illegal_T_16 & _io_decode_0_system_illegal_T_17; // @[CSR.scala:939:{18,37,40}] wire _io_decode_0_system_illegal_T_19 = _io_decode_0_system_illegal_T_15 \| _io_decode_0_system_illegal_T_18; // @[CSR.scala:937:29, :938:51, :939:37] wire _io_decode_0_system_illegal_T_22 = _io_decode_0_system_illegal_T_19; // @[CSR.scala:938:51, :939:58] assign _io_decode_0_system_illegal_T_25 = _io_decode_0_system_illegal_T_22; // @[CSR.scala:939:58, :940:44] assign io_decode_0_system_illegal_0 = _io_decode_0_system_illegal_T_25; // @[CSR.scala:377:7, :940:44] wire _io_decode_0_virtual_access_illegal_T = reg_mstatus_v & csr_exists; // @[CSR.scala:395:28, :899:111, :943:52] wire _io_decode_0_virtual_access_illegal_T_2 = _io_decode_0_virtual_access_illegal_T_1 == 2'h2; // @[CSR.scala:190:36, :944:22] wire _io_decode_0_virtual_access_illegal_T_4 = _io_decode_0_virtual_access_illegal_T_3[0]; // @[CSR.scala:945:36] wire _io_decode_0_virtual_access_illegal_T_5 = is_counter & _io_decode_0_virtual_access_illegal_T_4; // @[CSR.scala:904:81, :945:{18,36}] wire _io_decode_0_virtual_access_illegal_T_7 = _io_decode_0_virtual_access_illegal_T_6[0]; // @[CSR.scala:945:71] wire _io_decode_0_virtual_access_illegal_T_8 = ~_io_decode_0_virtual_access_illegal_T_7; // @[CSR.scala:945:{55,71}] wire _io_decode_0_virtual_access_illegal_T_9 = reg_mstatus_prv[0]; // @[CSR.scala:395:28, :945:105] wire _io_decode_0_virtual_access_illegal_T_20 = reg_mstatus_prv[0]; // @[CSR.scala:395:28, :945:105, :946:53] wire _io_decode_0_virtual_access_illegal_T_25 = reg_mstatus_prv[0]; // @[CSR.scala:395:28, :945:105, :947:46] wire _io_decode_0_virtual_system_illegal_T_2 = reg_mstatus_prv[0]; // @[CSR.scala:395:28, :945:105, :953:34] wire _io_decode_0_virtual_system_illegal_T_12 = reg_mstatus_prv[0]; // @[CSR.scala:395:28, :945:105, :954:64] wire _io_decode_0_virtual_system_illegal_T_17 = reg_mstatus_prv[0]; // @[CSR.scala:395:28, :945:105, :955:37] wire _cause_T = reg_mstatus_prv[0]; // @[CSR.scala:395:28, :945:105, :959:61] wire _reg_hstatus_spvp_T = reg_mstatus_prv[0]; // @[CSR.scala:395:28, :945:105, :1067:61] wire _io_decode_0_virtual_access_illegal_T_10 = ~_io_decode_0_virtual_access_illegal_T_9; // @[CSR.scala:945:{89,105}] wire _io_decode_0_virtual_access_illegal_T_12 = _io_decode_0_virtual_access_illegal_T_11[0]; // @[CSR.scala:945:128] wire _io_decode_0_virtual_access_illegal_T_13 = ~_io_decode_0_virtual_access_illegal_T_12; // @[CSR.scala:945:{112,128}] wire _io_decode_0_virtual_access_illegal_T_14 = _io_decode_0_virtual_access_illegal_T_10 & _io_decode_0_virtual_access_illegal_T_13; // @[CSR.scala:945:{89,109,112}] wire _io_decode_0_virtual_access_illegal_T_15 = _io_decode_0_virtual_access_illegal_T_8 \| _io_decode_0_virtual_access_illegal_T_14; // @[CSR.scala:945:{55,86,109}] wire _io_decode_0_virtual_access_illegal_T_16 = _io_decode_0_virtual_access_illegal_T_5 & _io_decode_0_virtual_access_illegal_T_15; // @[CSR.scala:945:{18,51,86}] wire _io_decode_0_virtual_access_illegal_T_17 = _io_decode_0_virtual_access_illegal_T_2 \| _io_decode_0_virtual_access_illegal_T_16; // @[CSR.scala:944:{22,34}, :945:51] wire _io_decode_0_virtual_access_illegal_T_19 = _io_decode_0_virtual_access_illegal_T_18 == 2'h1; // @[CSR.scala:190:36, :946:22] wire _io_decode_0_virtual_access_illegal_T_21 = ~_io_decode_0_virtual_access_illegal_T_20; // @[CSR.scala:946:{37,53}] wire _io_decode_0_virtual_access_illegal_T_22 = _io_decode_0_virtual_access_illegal_T_19 & _io_decode_0_virtual_access_illegal_T_21; // @[CSR.scala:946:{22,34,37}] wire _io_decode_0_virtual_access_illegal_T_23 = _io_decode_0_virtual_access_illegal_T_17 \| _io_decode_0_virtual_access_illegal_T_22; // @[CSR.scala:944:34, :945:144, :946:34] wire _io_decode_0_virtual_access_illegal_T_28 = _io_decode_0_virtual_access_illegal_T_23; // @[CSR.scala:945:144, :946:57] wire _io_decode_0_virtual_access_illegal_T_26 = _io_decode_0_virtual_access_illegal_T_24 & _io_decode_0_virtual_access_illegal_T_25; // @[CSR.scala:947:{12,28,46}] assign _io_decode_0_virtual_access_illegal_T_29 = _io_decode_0_virtual_access_illegal_T & _io_decode_0_virtual_access_illegal_T_28; // @[CSR.scala:943:{52,66}, :946:57] assign io_decode_0_virtual_access_illegal_0 = _io_decode_0_virtual_access_illegal_T_29; // @[CSR.scala:377:7, :943:66] wire _io_decode_0_virtual_system_illegal_T = is_hfence_vvma \| is_hfence_gvma; // @[CSR.scala:903:82, :950:22] wire _io_decode_0_virtual_system_illegal_T_1 = _io_decode_0_virtual_system_illegal_T \| is_hlsv; // @[CSR.scala:903:82, :950:22, :951:22] wire _io_decode_0_virtual_system_illegal_T_3 = ~_io_decode_0_virtual_system_illegal_T_2; // @[CSR.scala:953:{18,34}] wire _io_decode_0_virtual_system_illegal_T_6 = _io_decode_0_virtual_system_illegal_T_3; // @[CSR.scala:953:{18,38}] wire _io_decode_0_virtual_system_illegal_T_4 = ~reg_mstatus_tw; // @[CSR.scala:395:28, :906:74, :953:41] wire _io_decode_0_virtual_system_illegal_T_7 = is_wfi & _io_decode_0_virtual_system_illegal_T_6; // @[CSR.scala:903:82, :953:{14,38}] wire _io_decode_0_virtual_system_illegal_T_8 = _io_decode_0_virtual_system_illegal_T_1 \| _io_decode_0_virtual_system_illegal_T_7; // @[CSR.scala:951:22, :952:15, :953:14] wire _io_decode_0_virtual_system_illegal_T_10 = _io_decode_0_virtual_system_illegal_T_9 == 2'h1; // @[CSR.scala:190:36, :954:32] wire _io_decode_0_virtual_system_illegal_T_11 = is_ret & _io_decode_0_virtual_system_illegal_T_10; // @[CSR.scala:903:82, :954:{14,32}] wire _io_decode_0_virtual_system_illegal_T_13 = ~_io_decode_0_virtual_system_illegal_T_12; // @[CSR.scala:954:{48,64}] wire _io_decode_0_virtual_system_illegal_T_14 = _io_decode_0_virtual_system_illegal_T_13; // @[CSR.scala:954:{48,68}] wire _io_decode_0_virtual_system_illegal_T_15 = _io_decode_0_virtual_system_illegal_T_11 & _io_decode_0_virtual_system_illegal_T_14; // @[CSR.scala:954:{14,44,68}] wire _io_decode_0_virtual_system_illegal_T_16 = _io_decode_0_virtual_system_illegal_T_8 \| _io_decode_0_virtual_system_illegal_T_15; // @[CSR.scala:952:15, :953:77, :954:44] wire _io_decode_0_virtual_system_illegal_T_18 = ~_io_decode_0_virtual_system_illegal_T_17; // @[CSR.scala:955:{21,37}] wire _io_decode_0_virtual_system_illegal_T_19 = _io_decode_0_virtual_system_illegal_T_18; // @[CSR.scala:955:{21,41}] wire _io_decode_0_virtual_system_illegal_T_20 = is_sfence & _io_decode_0_virtual_system_illegal_T_19; // @[CSR.scala:903:82, :955:{17,41}] wire _io_decode_0_virtual_system_illegal_T_21 = _io_decode_0_virtual_system_illegal_T_16 \| _io_decode_0_virtual_system_illegal_T_20; // @[CSR.scala:953:77, :954:89, :955:17] assign _io_decode_0_virtual_system_illegal_T_22 = reg_mstatus_v & _io_decode_0_virtual_system_illegal_T_21; // @[CSR.scala:395:28, :949:52, :954:89] assign io_decode_0_virtual_system_illegal_0 = _io_decode_0_virtual_system_illegal_T_22; // @[CSR.scala:377:7, :949:52] wire _cause_T_1 = _cause_T & reg_mstatus_v; // @[CSR.scala:395:28, :959:{61,65}] wire [1:0] _cause_T_2 = _cause_T_1 ? 2'h2 : reg_mstatus_prv; // @[CSR.scala:395:28, :959:{45,65}] wire [4:0] _cause_T_3 = {3'h0, _cause_T_2} + 5'h8; // @[CSR.scala:959:{40,45}] wire [3:0] _cause_T_4 = _cause_T_3[3:0]; // @[CSR.scala:959:40] wire [63:0] _cause_T_5 = insn_break ? 64'h3 : io_cause_0; // @[CSR.scala:377:7, :893:83, :960:14] assign cause = insn_call ? {60'h0, _cause_T_4} : _cause_T_5; // @[CSR.scala:893:83, :959:{8,40}, :960:14] assign io_trace_0_cause = cause; // @[CSR.scala:377:7, :959:8] wire [7:0] cause_lsbs = cause[7:0]; // @[CSR.scala:959:8, :961:25] wire [5:0] cause_deleg_lsbs = cause[5:0]; // @[CSR.scala:959:8, :962:31] wire [5:0] _notDebugTVec_interruptOffset_T = cause[5:0]; // @[CSR.scala:959:8, :962:31, :979:32] wire _causeIsDebugInt_T = cause[63]; // @[CSR.scala:959:8, :963:30] wire _causeIsDebugTrigger_T = cause[63]; // @[CSR.scala:959:8, :963:30, :964:35] wire _causeIsDebugBreak_T = cause[63]; // @[CSR.scala:959:8, :963:30, :965:33] wire _delegate_T_2 = cause[63]; // @[CSR.scala:959:8, :963:30, :970:78] wire _delegateVS_T_1 = cause[63]; // @[CSR.scala:959:8, :963:30, :971:58] wire _notDebugTVec_doVector_T_1 = cause[63]; // @[CSR.scala:959:8, :963:30, :981:36] wire _causeIsRnmiInt_T = cause[63]; // @[CSR.scala:959:8, :963:30, :985:29] wire _causeIsRnmiBEU_T = cause[63]; // @[CSR.scala:959:8, :963:30, :986:29] wire _reg_vscause_T = cause[63]; // @[CSR.scala:959:8, :963:30, :1060:31] assign _io_trace_0_interrupt_T = cause[63]; // @[CSR.scala:959:8, :963:30, :1626:25] wire _GEN_9 = cause_lsbs == 8'hE; // @[CSR.scala:961:25, :963:53] wire _causeIsDebugInt_T_1; // @[CSR.scala:963:53] assign _causeIsDebugInt_T_1 = _GEN_9; // @[CSR.scala:963:53] wire _causeIsDebugTrigger_T_2; // @[CSR.scala:964:58] assign _causeIsDebugTrigger_T_2 = _GEN_9; // @[CSR.scala:963:53, :964:58] wire causeIsDebugInt = _causeIsDebugInt_T & _causeIsDebugInt_T_1; // @[CSR.scala:963:{30,39,53}] wire _causeIsDebugTrigger_T_1 = ~_causeIsDebugTrigger_T; // @[CSR.scala:964:{29,35}] wire causeIsDebugTrigger = _causeIsDebugTrigger_T_1 & _causeIsDebugTrigger_T_2; // @[CSR.scala:964:{29,44,58}] wire _causeIsDebugBreak_T_1 = ~_causeIsDebugBreak_T; // @[CSR.scala:965:{27,33}] wire _causeIsDebugBreak_T_2 = _causeIsDebugBreak_T_1 & insn_break; // @[CSR.scala:893:83, :965:{27,42}] wire [1:0] causeIsDebugBreak_lo = {reg_dcsr_ebreaks, reg_dcsr_ebreaku}; // @[CSR.scala:403:25, :965:62] wire [1:0] causeIsDebugBreak_hi = {reg_dcsr_ebreakm, 1'h0}; // @[CSR.scala:403:25, :965:62] wire [3:0] _causeIsDebugBreak_T_3 = {causeIsDebugBreak_hi, causeIsDebugBreak_lo}; // @[CSR.scala:965:62] wire [3:0] _causeIsDebugBreak_T_4 = _causeIsDebugBreak_T_3 >> reg_mstatus_prv; // @[CSR.scala:395:28, :965:{62,134}] wire _causeIsDebugBreak_T_5 = _causeIsDebugBreak_T_4[0]; // @[CSR.scala:965:134] wire causeIsDebugBreak = _causeIsDebugBreak_T_2 & _causeIsDebugBreak_T_5; // @[CSR.scala:965:{42,56,134}] wire _trapToDebug_T = reg_singleStepped \| causeIsDebugInt; // @[CSR.scala:486:30, :963:39, :966:56] wire _trapToDebug_T_1 = _trapToDebug_T \| causeIsDebugTrigger; // @[CSR.scala:964:44, :966:{56,75}] wire _trapToDebug_T_2 = _trapToDebug_T_1 \| causeIsDebugBreak; // @[CSR.scala:965:56, :966:{75,98}] wire _trapToDebug_T_3 = _trapToDebug_T_2 \| reg_debug; // @[CSR.scala:482:26, :966:{98,119}] wire trapToDebug = _trapToDebug_T_3; // @[CSR.scala:966:{34,119}] wire [11:0] _debugTVec_T = {8'h80, ~insn_break, 3'h0}; // @[CSR.scala:893:83, :969:37] wire [11:0] debugTVec = reg_debug ? _debugTVec_T : 12'h800; // @[CSR.scala:482:26, :969:{22,37}] wire _delegate_T = ~(reg_mstatus_prv[1]); // @[CSR.scala:395:28, :620:51, :970:55] wire _delegate_T_1 = _delegate_T; // @[CSR.scala:970:{36,55}] wire [63:0] _GEN_10 = {58'h0, cause_deleg_lsbs}; // @[CSR.scala:962:31, :970:100] wire [63:0] _delegate_T_3 = read_mideleg >> _GEN_10; // @[CSR.scala:498:14, :970:100] wire _delegate_T_4 = _delegate_T_3[0]; // @[CSR.scala:970:100] wire [63:0] _delegate_T_5 = read_medeleg >> _GEN_10; // @[CSR.scala:502:14, :970:{100,132}] wire _delegate_T_6 = _delegate_T_5[0]; // @[CSR.scala:970:132] wire _delegate_T_7 = _delegate_T_2 ? _delegate_T_4 : _delegate_T_6; // @[CSR.scala:970:{72,78,100,132}] wire delegate = _delegate_T_1 & _delegate_T_7; // @[CSR.scala:970:{36,66,72}] wire _delegateVS_T = reg_mstatus_v & delegate; // @[CSR.scala:395:28, :970:66, :971:34] wire [63:0] _GEN_11 = 64'h0 >> _GEN_10; // @[CSR.scala:970:100, :971:80] wire [63:0] _delegateVS_T_2; // @[CSR.scala:971:80] assign _delegateVS_T_2 = _GEN_11; // @[CSR.scala:971:80] wire [63:0] _delegateVS_T_4; // @[CSR.scala:971:112] assign _delegateVS_T_4 = _GEN_11; // @[CSR.scala:971:{80,112}] wire _delegateVS_T_3 = _delegateVS_T_2[0]; // @[CSR.scala:971:80] wire _delegateVS_T_5 = _delegateVS_T_4[0]; // @[CSR.scala:971:112] wire _delegateVS_T_6 = _delegateVS_T_1 ? _delegateVS_T_3 : _delegateVS_T_5; // @[CSR.scala:971:{52,58,80,112}] wire delegateVS = _delegateVS_T & _delegateVS_T_6; // @[CSR.scala:971:{34,46,52}] wire [63:0] _notDebugTVec_base_T = delegateVS ? read_vstvec : read_stvec; // @[package.scala:132:15] wire [63:0] notDebugTVec_base = delegate ? _notDebugTVec_base_T : read_mtvec; // @[package.scala:138:15] wire [7:0] notDebugTVec_interruptOffset = {_notDebugTVec_interruptOffset_T, 2'h0}; // @[CSR.scala:979:{32,59}] wire [55:0] _notDebugTVec_interruptVec_T = notDebugTVec_base[63:8]; // @[CSR.scala:978:19, :980:33] wire [63:0] notDebugTVec_interruptVec = {_notDebugTVec_interruptVec_T, notDebugTVec_interruptOffset}; // @[CSR.scala:979:59, :980:{27,33}] wire _notDebugTVec_doVector_T = notDebugTVec_base[0]; // @[CSR.scala:978:19, :981:24] wire _notDebugTVec_doVector_T_2 = _notDebugTVec_doVector_T & _notDebugTVec_doVector_T_1; // @[CSR.scala:981:{24,28,36}] wire [1:0] _notDebugTVec_doVector_T_3 = cause_lsbs[7:6]; // @[CSR.scala:961:25, :981:70] wire _notDebugTVec_doVector_T_4 = _notDebugTVec_doVector_T_3 == 2'h0; // @[CSR.scala:981:{70,94}] wire notDebugTVec_doVector = _notDebugTVec_doVector_T_2 & _notDebugTVec_doVector_T_4; // @[CSR.scala:981:{28,55,94}] wire [61:0] _notDebugTVec_T = notDebugTVec_base[63:2]; // @[CSR.scala:978:19, :982:38] wire [63:0] _notDebugTVec_T_1 = {_notDebugTVec_T, 2'h0}; // @[CSR.scala:982:{38,56}] wire [63:0] notDebugTVec = notDebugTVec_doVector ? notDebugTVec_interruptVec : _notDebugTVec_T_1; // @[CSR.scala:980:27, :981:55, :982:{8,56}] wire [63:0] _tvec_T = notDebugTVec; // @[CSR.scala:982:8, :995:45] wire _causeIsRnmiInt_T_1 = cause[62]; // @[CSR.scala:959:8, :985:46] wire _causeIsRnmiBEU_T_1 = cause[62]; // @[CSR.scala:959:8, :985:46, :986:46] wire _causeIsRnmiInt_T_2 = _causeIsRnmiInt_T & _causeIsRnmiInt_T_1; // @[CSR.scala:985:{29,38,46}] wire _causeIsRnmiInt_T_3 = cause_lsbs == 8'hD; // @[CSR.scala:961:25, :985:70] wire _GEN_12 = cause_lsbs == 8'hC; // @[CSR.scala:961:25, :985:107] wire _causeIsRnmiInt_T_4; // @[CSR.scala:985:107] assign _causeIsRnmiInt_T_4 = _GEN_12; // @[CSR.scala:985:107] wire _causeIsRnmiBEU_T_3; // @[CSR.scala:986:69] assign _causeIsRnmiBEU_T_3 = _GEN_12; // @[CSR.scala:985:107, :986:69] wire _causeIsRnmiInt_T_5 = _causeIsRnmiInt_T_3 \| _causeIsRnmiInt_T_4; // @[CSR.scala:985:{70,93,107}] wire causeIsRnmiInt = _causeIsRnmiInt_T_2 & _causeIsRnmiInt_T_5; // @[CSR.scala:985:{38,55,93}] wire _causeIsRnmiBEU_T_2 = _causeIsRnmiBEU_T & _causeIsRnmiBEU_T_1; // @[CSR.scala:986:{29,38,46}] wire causeIsRnmiBEU = _causeIsRnmiBEU_T_2 & _causeIsRnmiBEU_T_3; // @[CSR.scala:986:{38,55,69}] wire [63:0] tvec = trapToDebug ? {52'h0, debugTVec} : _tvec_T; // @[CSR.scala:966:34, :969:22, :995:{17,45}] wire _GEN_13 = insn_call \| insn_break; // @[CSR.scala:893:83, :1000:24] wire _io_eret_T; // @[CSR.scala:1000:24] assign _io_eret_T = _GEN_13; // @[CSR.scala:1000:24] wire _exception_T; // @[CSR.scala:1020:29] assign _exception_T = _GEN_13; // @[CSR.scala:1000:24, :1020:29] assign _io_eret_T_1 = _io_eret_T \| insn_ret; // @[CSR.scala:893:83, :1000:{24,38}] assign io_eret = _io_eret_T_1; // @[CSR.scala:377:7, :1000:38] wire _io_singleStep_T = ~reg_debug; // @[CSR.scala:482:26, :927:45, :1001:37] assign _io_singleStep_T_1 = reg_dcsr_step & _io_singleStep_T; // @[CSR.scala:403:25, :1001:{34,37}] assign io_singleStep_0 = _io_singleStep_T_1; // @[CSR.scala:377:7, :1001:34] wire _io_status_sd_T = &io_status_fs_0; // @[CSR.scala:377:7, :1003:32] wire _io_status_sd_T_2 = _io_status_sd_T; // @[CSR.scala:1003:{32,37}] assign _io_status_sd_T_4 = _io_status_sd_T_2; // @[CSR.scala:1003:{37,58}] assign io_status_sd_0 = _io_status_sd_T_4; // @[CSR.scala:377:7, :1003:58] wire _io_status_dprv_T = ~reg_debug; // @[CSR.scala:482:26, :927:45, :1008:45] wire _io_status_dprv_T_1 = reg_mstatus_mprv & _io_status_dprv_T; // @[CSR.scala:395:28, :1008:{42,45}] assign _io_status_dprv_T_2 = _io_status_dprv_T_1 ? reg_mstatus_mpp : reg_mstatus_prv; // @[CSR.scala:395:28, :1008:{24,42}] assign io_status_dprv_0 = _io_status_dprv_T_2; // @[CSR.scala:377:7, :1008:24] wire _io_status_dv_T = ~reg_debug; // @[CSR.scala:482:26, :927:45, :1009:60] wire _io_status_dv_T_1 = reg_mstatus_mprv & _io_status_dv_T; // @[CSR.scala:395:28, :1009:{57,60}] wire _io_status_dv_T_2 = _io_status_dv_T_1 & reg_mstatus_mpv; // @[CSR.scala:395:28, :1009:{39,57}] assign _io_status_dv_T_3 = reg_mstatus_v \| _io_status_dv_T_2; // @[CSR.scala:395:28, :1009:{33,39}] assign io_status_dv_0 = _io_status_dv_T_3; // @[CSR.scala:377:7, :1009:33] wire _io_gstatus_sd_T_3 = &io_gstatus_vs; // @[CSR.scala:377:7, :1016:78] wire exception = _exception_T \| io_exception_0; // @[CSR.scala:377:7, :1020:{29,43}] wire _en_T_8 = exception; // @[CSR.scala:1020:43, :1096:24] wire _en_T_20 = exception; // @[CSR.scala:1020:43, :1096:24] wire _en_T_32 = exception; // @[CSR.scala:1020:43, :1096:24] wire _en_T_44 = exception; // @[CSR.scala:1020:43, :1096:24] wire _en_T_56 = exception; // @[CSR.scala:1020:43, :1096:24] wire _en_T_68 = exception; // @[CSR.scala:1020:43, :1096:24] assign _io_trace_0_exception_T_1 = exception; // @[CSR.scala:1020:43, :1620:37] wire [39:0] _epc_T = ~io_pc_0; // @[CSR.scala:377:7, :1664:28] wire [39:0] _epc_T_1 = {_epc_T[39:1], 1'h1}; // @[CSR.scala:1664:{28,31}] wire [39:0] epc = ~_epc_T_1; // @[CSR.scala:1664:{26,31}] wire [39:0] tval = insn_break ? epc : io_tval_0; // @[CSR.scala:377:7, :893:83, :1033:17, :1664:26] wire [1:0] _reg_dcsr_cause_T = causeIsDebugTrigger ? 2'h2 : 2'h1; // @[CSR.scala:964:44, :1041:90] wire [1:0] _reg_dcsr_cause_T_1 = causeIsDebugInt ? 2'h3 : _reg_dcsr_cause_T; // @[CSR.scala:963:39, :1041:{58,90}] wire [2:0] _reg_dcsr_cause_T_2 = reg_singleStepped ? 3'h4 : {1'h0, _reg_dcsr_cause_T_1}; // @[CSR.scala:486:30, :1041:{30,58}] wire [1:0] _reg_mncause_T = {1'h1, causeIsRnmiBEU}; // @[CSR.scala:986:55, :1052:55] wire [63:0] _reg_mncause_T_1 = {62'h2000000000000000, _reg_mncause_T}; // @[CSR.scala:1052:{50,55}] wire [61:0] _reg_vscause_T_1 = cause[63:2]; // @[CSR.scala:959:8, :1060:50] wire [63:0] _reg_vscause_T_2 = {_reg_vscause_T_1, 2'h1}; // @[CSR.scala:1060:{44,50}] wire [63:0] _reg_vscause_T_3 = _reg_vscause_T ? _reg_vscause_T_2 : cause; // @[CSR.scala:959:8, :1060:{25,31,44}] wire _reg_hstatus_spvp_T_1 = reg_mstatus_v ? _reg_hstatus_spvp_T : reg_hstatus_spvp; // @[CSR.scala:395:28, :552:28, :1067:{30,61}] wire _GEN_14 = delegateVS \| delegate; // @[CSR.scala:395:28, :970:66, :971:46, :1056:37, :1065:35, :1081:23] wire _en_T_5 = cause == 64'h8000000000000000; // @[CSR.scala:959:8, :1096:88] wire _en_T_11 = cause == 64'h8000000000000001; // @[CSR.scala:959:8, :1096:88] wire en_1 = _en_T_8 & _en_T_11; // @[CSR.scala:1096:{24,79,88}] wire _en_T_17 = cause == 64'h8000000000000002; // @[CSR.scala:959:8, :1096:88] wire _en_T_23 = cause == 64'h8000000000000003; // @[CSR.scala:959:8, :1096:88] wire en_3 = _en_T_20 & _en_T_23; // @[CSR.scala:1096:{24,79,88}] wire _en_T_29 = cause == 64'h8000000000000004; // @[CSR.scala:959:8, :1096:88] wire _en_T_35 = cause == 64'h8000000000000005; // @[CSR.scala:959:8, :1096:88] wire en_5 = _en_T_32 & _en_T_35; // @[CSR.scala:1096:{24,79,88}] wire _en_T_41 = cause == 64'h8000000000000006; // @[CSR.scala:959:8, :1096:88] wire _en_T_47 = cause == 64'h8000000000000007; // @[CSR.scala:959:8, :1096:88] wire en_7 = _en_T_44 & _en_T_47; // @[CSR.scala:1096:{24,79,88}] wire _en_T_53 = cause == 64'h8000000000000008; // @[CSR.scala:959:8, :1096:88] wire _en_T_59 = cause == 64'h8000000000000009; // @[CSR.scala:959:8, :1096:88] wire en_9 = _en_T_56 & _en_T_59; // @[CSR.scala:1096:{24,79,88}] wire _en_T_65 = cause == 64'h800000000000000A; // @[CSR.scala:959:8, :1096:88] wire _en_T_71 = cause == 64'h800000000000000B; // @[CSR.scala:959:8, :1096:88] wire en_11 = _en_T_68 & _en_T_71; // @[CSR.scala:1096:{24,79,88}] wire _en_T_77 = cause == 64'h800000000000000C; // @[CSR.scala:959:8, :1096:88] wire _en_T_83 = cause == 64'h800000000000000D; // @[CSR.scala:959:8, :1096:88] wire _en_T_89 = cause == 64'h800000000000000E; // @[CSR.scala:959:8, :1096:88] wire _en_T_95 = cause == 64'h800000000000000F; // @[CSR.scala:959:8, :1096:88] wire _en_T_96 = cause == 64'h1; // @[CSR.scala:959:8, :1108:35] wire en_16 = exception & _en_T_96; // @[CSR.scala:1020:43, :1108:{26,35}] wire _en_T_97 = cause == 64'h2; // @[CSR.scala:959:8, :1108:35] wire en_17 = exception & _en_T_97; // @[CSR.scala:1020:43, :1108:{26,35}] wire _en_T_98 = cause == 64'h3; // @[CSR.scala:959:8, :1108:35] wire en_18 = exception & _en_T_98; // @[CSR.scala:1020:43, :1108:{26,35}] wire _en_T_99 = cause == 64'h4; // @[CSR.scala:959:8, :1108:35] wire en_19 = exception & _en_T_99; // @[CSR.scala:1020:43, :1108:{26,35}] wire _en_T_100 = cause == 64'h5; // @[CSR.scala:959:8, :1108:35] wire en_20 = exception & _en_T_100; // @[CSR.scala:1020:43, :1108:{26,35}] wire _en_T_101 = cause == 64'h6; // @[CSR.scala:959:8, :1108:35] wire en_21 = exception & _en_T_101; // @[CSR.scala:1020:43, :1108:{26,35}] wire _en_T_102 = cause == 64'h7; // @[CSR.scala:959:8, :1108:35] wire en_22 = exception & _en_T_102; // @[CSR.scala:1020:43, :1108:{26,35}] wire _en_T_103 = cause == 64'h8; // @[CSR.scala:959:8, :1108:35] wire en_23 = exception & _en_T_103; // @[CSR.scala:1020:43, :1108:{26,35}] wire _en_T_104 = cause == 64'h9; // @[CSR.scala:959:8, :1108:35] wire en_24 = exception & _en_T_104; // @[CSR.scala:1020:43, :1108:{26,35}] wire _en_T_105 = cause == 64'hB; // @[CSR.scala:959:8, :1108:35] wire en_25 = exception & _en_T_105; // @[CSR.scala:1020:43, :1108:{26,35}] wire _en_T_106 = cause == 64'hC; // @[CSR.scala:959:8, :1108:35] wire en_26 = exception & _en_T_106; // @[CSR.scala:1020:43, :1108:{26,35}] wire _en_T_107 = cause == 64'hD; // @[CSR.scala:959:8, :1108:35] wire en_27 = exception & _en_T_107; // @[CSR.scala:1020:43, :1108:{26,35}] wire _en_T_108 = cause == 64'hF; // @[CSR.scala:959:8, :1108:35] wire en_28 = exception & _en_T_108; // @[CSR.scala:1020:43, :1108:{26,35}] wire [1:0] ret_prv; // @[CSR.scala:1116:27] wire [39:0] _io_evec_T_3 = {_io_evec_T[39:2], _io_evec_T[1:0] \| 2'h1}; // @[CSR.scala:1665:{28,31}] wire [39:0] _io_evec_T_4 = ~_io_evec_T_3; // @[CSR.scala:1665:{26,31}] wire [39:0] _io_evec_T_5 = ~reg_vsepc; // @[CSR.scala:564:22, :1665:28] wire [39:0] _io_evec_T_8 = {_io_evec_T_5[39:2], _io_evec_T_5[1:0] \| 2'h1}; // @[CSR.scala:1665:{28,31}] wire [39:0] _io_evec_T_9 = ~_io_evec_T_8; // @[CSR.scala:1665:{26,31}] wire _T_248 = io_rw_addr_0[10] & io_rw_addr_0[7]; // @[CSR.scala:377:7, :1134:{43,48,61}] wire _reg_mstatus_v_T_2 = ~(reg_dcsr_prv[1]); // @[CSR.scala:403:25, :1136:72] wire [39:0] _io_evec_T_10 = ~reg_dpc; // @[CSR.scala:483:20, :1665:28] wire [39:0] _io_evec_T_13 = {_io_evec_T_10[39:2], _io_evec_T_10[1:0] \| 2'h1}; // @[CSR.scala:1665:{28,31}] wire [39:0] _io_evec_T_14 = ~_io_evec_T_13; // @[CSR.scala:1665:{26,31}] wire [39:0] _io_evec_T_18 = {_io_evec_T_15[39:2], _io_evec_T_15[1:0] \| 2'h1}; // @[CSR.scala:1665:{28,31}] wire [39:0] _io_evec_T_19 = ~_io_evec_T_18; // @[CSR.scala:1665:{26,31}] assign ret_prv = io_rw_addr_0[9] ? (_T_248 ? reg_dcsr_prv : reg_mstatus_mpp) : {1'h0, reg_mstatus_v ? reg_vsstatus_spp : reg_mstatus_spp}; // @[CSR.scala:377:7, :395:28, :403:25, :562:25, :1116:27, :1117:{43,48}, :1118:29, :1122:17, :1130:17, :1134:{48,66}, :1135:15, :1139:65] wire _reg_mstatus_v_T_8 = ~(reg_mstatus_mpp[1]); // @[CSR.scala:395:28, :1150:80] wire [39:0] _io_evec_T_20 = ~reg_mepc; // @[CSR.scala:505:21, :1665:28] wire [39:0] _io_evec_T_23 = {_io_evec_T_20[39:2], _io_evec_T_20[1:0] \| 2'h1}; // @[CSR.scala:1665:{28,31}] wire [39:0] _io_evec_T_24 = ~_io_evec_T_23; // @[CSR.scala:1665:{26,31}] assign io_evec_0 = insn_ret ? (io_rw_addr_0[9] ? (_T_248 ? _io_evec_T_14 : _io_evec_T_24) : reg_mstatus_v ? _io_evec_T_9 : _io_evec_T_4) : tvec[39:0]; // @[CSR.scala:377:7, :395:28, :893:83, :995:17, :996:11, :1115:19, :1117:{43,48}, :1118:29, :1124:17, :1132:17, :1134:{48,66}, :1138:15, :1139:65, :1665:26] assign new_prv = insn_ret ? ret_prv : exception ? (trapToDebug ? (reg_debug ? reg_mstatus_prv : 2'h3) : {~_GEN_14, 1'h1}) : reg_mstatus_prv; // @[CSR.scala:395:28, :397:28, :482:26, :893:83, :966:34, :1020:43, :1035:20, :1036:24, :1037:25, :1044:17, :1046:31, :1056:37, :1064:15, :1065:35, :1078:15, :1081:23, :1091:15, :1115:19, :1116:27, :1154:13] assign _io_csr_stall_T = reg_wfi \| io_status_cease_0; // @[CSR.scala:377:7, :575:54, :1161:27] assign io_csr_stall_0 = _io_csr_stall_T; // @[CSR.scala:377:7, :1161:27] reg io_status_cease_r; // @[CSR.scala:1162:31] assign io_status_cease_0 = io_status_cease_r; // @[CSR.scala:377:7, :1162:31] wire [63:0] _io_rw_rdata_T_4 = decoded_addr_94_2 ? 64'h800000000014112D : 64'h0; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_153 = _io_rw_rdata_T_4; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_5 = decoded_addr_100_2 ? read_mstatus : 64'h0; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_6 = decoded_addr_72_2 ? read_mtvec : 64'h0; // @[Mux.scala:30:73] wire [15:0] _io_rw_rdata_T_7 = decoded_addr_108_2 ? read_mip : 16'h0; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_8 = decoded_addr_76_2 ? reg_mie : 64'h0; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_9 = decoded_addr_129_2 ? reg_mscratch : 64'h0; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_10 = decoded_addr_132_2 ? read_mapping_10_2 : 64'h0; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_11 = decoded_addr_136_2 ? read_mapping_11_2 : 64'h0; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_12 = decoded_addr_29_2 ? reg_mcause : 64'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_13 = decoded_addr_131_2 & io_hartid_0; // @[Mux.scala:30:73] wire [31:0] _io_rw_rdata_T_14 = decoded_addr_49_2 ? debug_csrs_0_2 : 32'h0; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_15 = decoded_addr_89_2 ? debug_csrs_1_2 : 64'h0; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_16 = decoded_addr_57_2 ? reg_dscratch0 : 64'h0; // @[Mux.scala:30:73] wire [4:0] _io_rw_rdata_T_17 = decoded_addr_36_2 ? reg_fflags : 5'h0; // @[Mux.scala:30:73] wire [2:0] _io_rw_rdata_T_18 = decoded_addr_68_2 ? reg_frm : 3'h0; // @[Mux.scala:30:73] wire [7:0] _io_rw_rdata_T_19 = decoded_addr_99_2 ? read_fcsr : 8'h0; // @[Mux.scala:30:73] wire [4:0] _io_rw_rdata_T_20 = decoded_addr_130_2 ? reg_mcountinhibit : 5'h0; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_21 = decoded_addr_103_2 ? value_1 : 64'h0; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_22 = decoded_addr_121_2 ? value : 64'h0; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_23 = decoded_addr_146_2 ? reg_hpmevent_0 : 64'h0; // @[Mux.scala:30:73] wire [39:0] _io_rw_rdata_T_24 = decoded_addr_17_2 ? value_2 : 40'h0; // @[Mux.scala:30:73] wire [39:0] _io_rw_rdata_T_25 = decoded_addr_27_2 ? value_2 : 40'h0; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_26 = decoded_addr_83_2 ? reg_hpmevent_1 : 64'h0; // @[Mux.scala:30:73] wire [39:0] _io_rw_rdata_T_27 = decoded_addr_52_2 ? value_3 : 40'h0; // @[Mux.scala:30:73] wire [39:0] _io_rw_rdata_T_28 = decoded_addr_144_2 ? value_3 : 40'h0; // @[Mux.scala:30:73] wire [31:0] _io_rw_rdata_T_110 = decoded_addr_35_2 ? read_mcounteren : 32'h0; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_111 = decoded_addr_2_2 ? value_1 : 64'h0; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_112 = decoded_addr_66_2 ? value : 64'h0; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_113 = decoded_addr_42_2 ? {57'h0, lo_4} : 64'h0; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_114 = decoded_addr_61_2 ? {hi_7[41:0], lo_5} : 64'h0; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_115 = decoded_addr_48_2 ? read_sip : 64'h0; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_116 = decoded_addr_44_2 ? read_sie : 64'h0; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_117 = decoded_addr_15_2 ? reg_sscratch : 64'h0; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_118 = decoded_addr_145_2 ? reg_scause : 64'h0; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_119 = decoded_addr_93_2 ? {{24{reg_stval[39]}}, reg_stval} : 64'h0; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_120 = decoded_addr_6_2 ? {hi_8, reg_satp_ppn} : 64'h0; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_121 = decoded_addr_28_2 ? {{24{_T_34[39]}}, _T_34} : 64'h0; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_122 = decoded_addr_25_2 ? read_stvec : 64'h0; // @[Mux.scala:30:73] wire [31:0] _io_rw_rdata_T_123 = decoded_addr_137_2 ? read_scounteren : 32'h0; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_124 = decoded_addr_123_2 ? read_mideleg : 64'h0; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_125 = decoded_addr_23_2 ? read_medeleg : 64'h0; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_126 = decoded_addr_69_2 ? {57'h0, lo_6} : 64'h0; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_127 = decoded_addr_141_2 ? {hi_18, lo_15} : 64'h0; // @[Mux.scala:30:73] wire [29:0] _io_rw_rdata_T_129 = decoded_addr_104_2 ? reg_pmp_0_addr : 30'h0; // @[Mux.scala:30:73] wire [29:0] _io_rw_rdata_T_130 = decoded_addr_8_2 ? reg_pmp_1_addr : 30'h0; // @[Mux.scala:30:73] wire [29:0] _io_rw_rdata_T_131 = decoded_addr_125_2 ? reg_pmp_2_addr : 30'h0; // @[Mux.scala:30:73] wire [29:0] _io_rw_rdata_T_132 = decoded_addr_85_2 ? reg_pmp_3_addr : 30'h0; // @[Mux.scala:30:73] wire [29:0] _io_rw_rdata_T_133 = decoded_addr_54_2 ? reg_pmp_4_addr : 30'h0; // @[Mux.scala:30:73] wire [29:0] _io_rw_rdata_T_134 = decoded_addr_20_2 ? reg_pmp_5_addr : 30'h0; // @[Mux.scala:30:73] wire [29:0] _io_rw_rdata_T_135 = decoded_addr_135_2 ? reg_pmp_6_addr : 30'h0; // @[Mux.scala:30:73] wire [29:0] _io_rw_rdata_T_136 = decoded_addr_115_2 ? reg_pmp_7_addr : 30'h0; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_145 = decoded_addr_18_2 ? reg_custom_0 : 64'h0; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_146 = decoded_addr_3_2 ? reg_custom_1 : 64'h0; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_154 = _io_rw_rdata_T_153 \| _io_rw_rdata_T_5; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_155 = _io_rw_rdata_T_154 \| _io_rw_rdata_T_6; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_156 = {_io_rw_rdata_T_155[63:16], _io_rw_rdata_T_155[15:0] \| _io_rw_rdata_T_7}; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_157 = _io_rw_rdata_T_156 \| _io_rw_rdata_T_8; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_158 = _io_rw_rdata_T_157 \| _io_rw_rdata_T_9; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_159 = _io_rw_rdata_T_158 \| _io_rw_rdata_T_10; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_160 = _io_rw_rdata_T_159 \| _io_rw_rdata_T_11; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_161 = _io_rw_rdata_T_160 \| _io_rw_rdata_T_12; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_162 = {_io_rw_rdata_T_161[63:1], _io_rw_rdata_T_161[0] \| _io_rw_rdata_T_13}; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_163 = {_io_rw_rdata_T_162[63:32], _io_rw_rdata_T_162[31:0] \| _io_rw_rdata_T_14}; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_164 = _io_rw_rdata_T_163 \| _io_rw_rdata_T_15; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_165 = _io_rw_rdata_T_164 \| _io_rw_rdata_T_16; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_166 = {_io_rw_rdata_T_165[63:5], _io_rw_rdata_T_165[4:0] \| _io_rw_rdata_T_17}; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_167 = {_io_rw_rdata_T_166[63:3], _io_rw_rdata_T_166[2:0] \| _io_rw_rdata_T_18}; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_168 = {_io_rw_rdata_T_167[63:8], _io_rw_rdata_T_167[7:0] \| _io_rw_rdata_T_19}; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_169 = {_io_rw_rdata_T_168[63:5], _io_rw_rdata_T_168[4:0] \| _io_rw_rdata_T_20}; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_170 = _io_rw_rdata_T_169 \| _io_rw_rdata_T_21; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_171 = _io_rw_rdata_T_170 \| _io_rw_rdata_T_22; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_172 = _io_rw_rdata_T_171 \| _io_rw_rdata_T_23; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_173 = {_io_rw_rdata_T_172[63:40], _io_rw_rdata_T_172[39:0] \| _io_rw_rdata_T_24}; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_174 = {_io_rw_rdata_T_173[63:40], _io_rw_rdata_T_173[39:0] \| _io_rw_rdata_T_25}; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_175 = _io_rw_rdata_T_174 \| _io_rw_rdata_T_26; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_176 = {_io_rw_rdata_T_175[63:40], _io_rw_rdata_T_175[39:0] \| _io_rw_rdata_T_27}; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_177 = {_io_rw_rdata_T_176[63:40], _io_rw_rdata_T_176[39:0] \| _io_rw_rdata_T_28}; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_178 = _io_rw_rdata_T_177; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_179 = _io_rw_rdata_T_178; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_180 = _io_rw_rdata_T_179; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_181 = _io_rw_rdata_T_180; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_182 = _io_rw_rdata_T_181; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_183 = _io_rw_rdata_T_182; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_184 = _io_rw_rdata_T_183; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_185 = _io_rw_rdata_T_184; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_186 = _io_rw_rdata_T_185; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_187 = _io_rw_rdata_T_186; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_188 = _io_rw_rdata_T_187; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_189 = _io_rw_rdata_T_188; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_190 = _io_rw_rdata_T_189; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_191 = _io_rw_rdata_T_190; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_192 = _io_rw_rdata_T_191; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_193 = _io_rw_rdata_T_192; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_194 = _io_rw_rdata_T_193; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_195 = _io_rw_rdata_T_194; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_196 = _io_rw_rdata_T_195; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_197 = _io_rw_rdata_T_196; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_198 = _io_rw_rdata_T_197; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_199 = _io_rw_rdata_T_198; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_200 = _io_rw_rdata_T_199; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_201 = _io_rw_rdata_T_200; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_202 = _io_rw_rdata_T_201; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_203 = _io_rw_rdata_T_202; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_204 = _io_rw_rdata_T_203; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_205 = _io_rw_rdata_T_204; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_206 = _io_rw_rdata_T_205; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_207 = _io_rw_rdata_T_206; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_208 = _io_rw_rdata_T_207; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_209 = _io_rw_rdata_T_208; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_210 = _io_rw_rdata_T_209; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_211 = _io_rw_rdata_T_210; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_212 = _io_rw_rdata_T_211; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_213 = _io_rw_rdata_T_212; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_214 = _io_rw_rdata_T_213; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_215 = _io_rw_rdata_T_214; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_216 = _io_rw_rdata_T_215; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_217 = _io_rw_rdata_T_216; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_218 = _io_rw_rdata_T_217; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_219 = _io_rw_rdata_T_218; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_220 = _io_rw_rdata_T_219; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_221 = _io_rw_rdata_T_220; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_222 = _io_rw_rdata_T_221; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_223 = _io_rw_rdata_T_222; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_224 = _io_rw_rdata_T_223; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_225 = _io_rw_rdata_T_224; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_226 = _io_rw_rdata_T_225; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_227 = _io_rw_rdata_T_226; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_228 = _io_rw_rdata_T_227; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_229 = _io_rw_rdata_T_228; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_230 = _io_rw_rdata_T_229; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_231 = _io_rw_rdata_T_230; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_232 = _io_rw_rdata_T_231; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_233 = _io_rw_rdata_T_232; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_234 = _io_rw_rdata_T_233; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_235 = _io_rw_rdata_T_234; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_236 = _io_rw_rdata_T_235; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_237 = _io_rw_rdata_T_236; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_238 = _io_rw_rdata_T_237; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_239 = _io_rw_rdata_T_238; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_240 = _io_rw_rdata_T_239; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_241 = _io_rw_rdata_T_240; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_242 = _io_rw_rdata_T_241; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_243 = _io_rw_rdata_T_242; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_244 = _io_rw_rdata_T_243; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_245 = _io_rw_rdata_T_244; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_246 = _io_rw_rdata_T_245; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_247 = _io_rw_rdata_T_246; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_248 = _io_rw_rdata_T_247; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_249 = _io_rw_rdata_T_248; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_250 = _io_rw_rdata_T_249; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_251 = _io_rw_rdata_T_250; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_252 = _io_rw_rdata_T_251; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_253 = _io_rw_rdata_T_252; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_254 = _io_rw_rdata_T_253; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_255 = _io_rw_rdata_T_254; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_256 = _io_rw_rdata_T_255; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_257 = _io_rw_rdata_T_256; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_258 = _io_rw_rdata_T_257; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_259 = {_io_rw_rdata_T_258[63:32], _io_rw_rdata_T_258[31:0] \| _io_rw_rdata_T_110}; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_260 = _io_rw_rdata_T_259 \| _io_rw_rdata_T_111; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_261 = _io_rw_rdata_T_260 \| _io_rw_rdata_T_112; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_262 = _io_rw_rdata_T_261 \| _io_rw_rdata_T_113; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_263 = _io_rw_rdata_T_262 \| _io_rw_rdata_T_114; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_264 = _io_rw_rdata_T_263 \| _io_rw_rdata_T_115; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_265 = _io_rw_rdata_T_264 \| _io_rw_rdata_T_116; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_266 = _io_rw_rdata_T_265 \| _io_rw_rdata_T_117; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_267 = _io_rw_rdata_T_266 \| _io_rw_rdata_T_118; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_268 = _io_rw_rdata_T_267 \| _io_rw_rdata_T_119; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_269 = _io_rw_rdata_T_268 \| _io_rw_rdata_T_120; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_270 = _io_rw_rdata_T_269 \| _io_rw_rdata_T_121; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_271 = _io_rw_rdata_T_270 \| _io_rw_rdata_T_122; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_272 = {_io_rw_rdata_T_271[63:32], _io_rw_rdata_T_271[31:0] \| _io_rw_rdata_T_123}; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_273 = _io_rw_rdata_T_272 \| _io_rw_rdata_T_124; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_274 = _io_rw_rdata_T_273 \| _io_rw_rdata_T_125; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_275 = _io_rw_rdata_T_274 \| _io_rw_rdata_T_126; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_276 = _io_rw_rdata_T_275 \| _io_rw_rdata_T_127; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_277 = _io_rw_rdata_T_276; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_278 = {_io_rw_rdata_T_277[63:30], _io_rw_rdata_T_277[29:0] \| _io_rw_rdata_T_129}; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_279 = {_io_rw_rdata_T_278[63:30], _io_rw_rdata_T_278[29:0] \| _io_rw_rdata_T_130}; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_280 = {_io_rw_rdata_T_279[63:30], _io_rw_rdata_T_279[29:0] \| _io_rw_rdata_T_131}; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_281 = {_io_rw_rdata_T_280[63:30], _io_rw_rdata_T_280[29:0] \| _io_rw_rdata_T_132}; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_282 = {_io_rw_rdata_T_281[63:30], _io_rw_rdata_T_281[29:0] \| _io_rw_rdata_T_133}; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_283 = {_io_rw_rdata_T_282[63:30], _io_rw_rdata_T_282[29:0] \| _io_rw_rdata_T_134}; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_284 = {_io_rw_rdata_T_283[63:30], _io_rw_rdata_T_283[29:0] \| _io_rw_rdata_T_135}; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_285 = {_io_rw_rdata_T_284[63:30], _io_rw_rdata_T_284[29:0] \| _io_rw_rdata_T_136}; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_286 = _io_rw_rdata_T_285; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_287 = _io_rw_rdata_T_286; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_288 = _io_rw_rdata_T_287; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_289 = _io_rw_rdata_T_288; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_290 = _io_rw_rdata_T_289; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_291 = _io_rw_rdata_T_290; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_292 = _io_rw_rdata_T_291; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_293 = _io_rw_rdata_T_292; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_294 = _io_rw_rdata_T_293 \| _io_rw_rdata_T_145; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_295 = _io_rw_rdata_T_294 \| _io_rw_rdata_T_146; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_296 = _io_rw_rdata_T_295; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_297 = _io_rw_rdata_T_296; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_298 = _io_rw_rdata_T_297; // @[Mux.scala:30:73] assign _io_rw_rdata_WIRE = _io_rw_rdata_T_298; // @[Mux.scala:30:73] assign io_rw_rdata_0 = _io_rw_rdata_WIRE; // @[Mux.scala:30:73] wire set_fs_dirty; // @[CSR.scala:1200:33]
Generate the Verilog code corresponding to the following Chisel files. File Transposer.scala: package gemmini import chisel3._ import chisel3.util._ import Util._ trait Transposer[T <: Data] extends Module { def dim: Int def dataType: T val io = IO(new Bundle { val inRow = Flipped(Decoupled(Vec(dim, dataType))) val outCol = Decoupled(Vec(dim, dataType)) }) } class PipelinedTransposer[T <: Data](val dim: Int, val dataType: T) extends Transposer[T] { require(isPow2(dim)) val regArray = Seq.fill(dim, dim)(Reg(dataType)) val regArrayT = regArray.transpose val sMoveUp :: sMoveLeft :: Nil = Enum(2) val state = RegInit(sMoveUp) val leftCounter = RegInit(0.U(log2Ceil(dim+1).W)) //(io.inRow.fire && state === sMoveLeft, dim+1) val upCounter = RegInit(0.U(log2Ceil(dim+1).W)) //Counter(io.inRow.fire && state === sMoveUp, dim+1) io.outCol.valid := 0.U io.inRow.ready := 0.U switch(state) { is(sMoveUp) { io.inRow.ready := upCounter <= dim.U io.outCol.valid := leftCounter > 0.U when(io.inRow.fire) { upCounter := upCounter + 1.U } when(upCounter === (dim-1).U) { state := sMoveLeft leftCounter := 0.U } when(io.outCol.fire) { leftCounter := leftCounter - 1.U } } is(sMoveLeft) { io.inRow.ready := leftCounter <= dim.U // TODO: this is naive io.outCol.valid := upCounter > 0.U when(leftCounter === (dim-1).U) { state := sMoveUp } when(io.inRow.fire) { leftCounter := leftCounter + 1.U upCounter := 0.U } when(io.outCol.fire) { upCounter := upCounter - 1.U } } } // Propagate input from bottom row to top row systolically in the move up phase // TODO: need to iterate over columns to connect Chisel values of type T // Should be able to operate directly on the Vec, but Seq and Vec don't mix (try Array?) for (colIdx <- 0 until dim) { regArray.foldRight(io.inRow.bits(colIdx)) { case (regRow, prevReg) => when (state === sMoveUp) { regRow(colIdx) := prevReg } regRow(colIdx) } } // Propagate input from right side to left side systolically in the move left phase for (rowIdx <- 0 until dim) { regArrayT.foldRight(io.inRow.bits(rowIdx)) { case (regCol, prevReg) => when (state === sMoveLeft) { regCol(rowIdx) := prevReg } regCol(rowIdx) } } // Pull from the left side or the top side based on the state for (idx <- 0 until dim) { when (state === sMoveUp) { io.outCol.bits(idx) := regArray(0)(idx) }.elsewhen(state === sMoveLeft) { io.outCol.bits(idx) := regArrayT(0)(idx) }.otherwise { io.outCol.bits(idx) := DontCare } } } class AlwaysOutTransposer[T <: Data](val dim: Int, val dataType: T) extends Transposer[T] { require(isPow2(dim)) val LEFT_DIR = 0.U(1.W) val UP_DIR = 1.U(1.W) class PE extends Module { val io = IO(new Bundle { val inR = Input(dataType) val inD = Input(dataType) val outL = Output(dataType) val outU = Output(dataType) val dir = Input(UInt(1.W)) val en = Input(Bool()) }) val reg = RegEnable(Mux(io.dir === LEFT_DIR, io.inR, io.inD), io.en) io.outU := reg io.outL := reg } val pes = Seq.fill(dim,dim)(Module(new PE)) val counter = RegInit(0.U((log2Ceil(dim) max 1).W)) // TODO replace this with a standard Chisel counter val dir = RegInit(LEFT_DIR) // Wire up horizontal signals for (row <- 0 until dim; col <- 0 until dim) { val right_in = if (col == dim-1) io.inRow.bits(row) else pes(row)(col+1).io.outL pes(row)(col).io.inR := right_in } // Wire up vertical signals for (row <- 0 until dim; col <- 0 until dim) { val down_in = if (row == dim-1) io.inRow.bits(col) else pes(row+1)(col).io.outU pes(row)(col).io.inD := down_in } // Wire up global signals pes.flatten.foreach(_.io.dir := dir) pes.flatten.foreach(_.io.en := io.inRow.fire) io.outCol.valid := true.B io.inRow.ready := true.B val left_out = VecInit(pes.transpose.head.map(_.io.outL)) val up_out = VecInit(pes.head.map(_.io.outU)) io.outCol.bits := Mux(dir === LEFT_DIR, left_out, up_out) when (io.inRow.fire) { counter := wrappingAdd(counter, 1.U, dim) } when (counter === (dim-1).U && io.inRow.fire) { dir := ~dir } } class NaiveTransposer[T <: Data](val dim: Int, val dataType: T) extends Transposer[T] { val regArray = Seq.fill(dim, dim)(Reg(dataType)) val regArrayT = regArray.transpose // state = 0 => filling regArray row-wise, state = 1 => draining regArray column-wise val state = RegInit(0.U(1.W)) val countInc = io.inRow.fire \|\| io.outCol.fire val (countValue, countWrap) = Counter(countInc, dim) io.inRow.ready := state === 0.U io.outCol.valid := state === 1.U for (i <- 0 until dim) { for (j <- 0 until dim) { when(countValue === i.U && io.inRow.fire) { regArray(i)(j) := io.inRow.bits(j) } } } for (i <- 0 until dim) { io.outCol.bits(i) := 0.U for (j <- 0 until dim) { when(countValue === j.U) { io.outCol.bits(i) := regArrayT(j)(i) } } } when (io.inRow.fire && countWrap) { state := 1.U } when (io.outCol.fire && countWrap) { state := 0.U } assert(!(state === 0.U) \|\| !io.outCol.fire) assert(!(state === 1.U) \|\| !io.inRow.fire) }	module PE_47( // @[Transposer.scala:100:9] input clock, // @[Transposer.scala:100:9] input reset, // @[Transposer.scala:100:9] input [7:0] io_inR, // @[Transposer.scala:101:16] input [7:0] io_inD, // @[Transposer.scala:101:16] output [7:0] io_outL, // @[Transposer.scala:101:16] output [7:0] io_outU, // @[Transposer.scala:101:16] input io_dir, // @[Transposer.scala:101:16] input io_en // @[Transposer.scala:101:16] ); wire [7:0] io_inR_0 = io_inR; // @[Transposer.scala:100:9] wire [7:0] io_inD_0 = io_inD; // @[Transposer.scala:100:9] wire io_dir_0 = io_dir; // @[Transposer.scala:100:9] wire io_en_0 = io_en; // @[Transposer.scala:100:9] wire [7:0] io_outL_0; // @[Transposer.scala:100:9] wire [7:0] io_outU_0; // @[Transposer.scala:100:9] wire _reg_T = ~io_dir_0; // @[Transposer.scala:100:9, :110:36] wire [7:0] _reg_T_1 = _reg_T ? io_inR_0 : io_inD_0; // @[Transposer.scala:100:9, :110:{28,36}] reg [7:0] reg_0; // @[Transposer.scala:110:24] assign io_outL_0 = reg_0; // @[Transposer.scala:100:9, :110:24] assign io_outU_0 = reg_0; // @[Transposer.scala:100:9, :110:24] always @(posedge clock) begin // @[Transposer.scala:100:9] if (io_en_0) // @[Transposer.scala:100:9] reg_0 <= _reg_T_1; // @[Transposer.scala:110:{24,28}] always @(posedge) assign io_outL = io_outL_0; // @[Transposer.scala:100:9] assign io_outU = io_outU_0; // @[Transposer.scala:100:9] endmodule
Generate the Verilog code corresponding to the following Chisel files. File Tilelink.scala: package constellation.protocol import chisel3._ import chisel3.util._ import constellation.channel._ import constellation.noc._ import constellation.soc.{CanAttachToGlobalNoC} import org.chipsalliance.cde.config._ import freechips.rocketchip.diplomacy._ import freechips.rocketchip.util._ import freechips.rocketchip.tilelink._ import scala.collection.immutable.{ListMap} trait TLFieldHelper { def getBodyFields(b: TLChannel): Seq[Data] = b match { case b: TLBundleA => Seq(b.mask, b.data, b.corrupt) case b: TLBundleB => Seq(b.mask, b.data, b.corrupt) case b: TLBundleC => Seq( b.data, b.corrupt) case b: TLBundleD => Seq( b.data, b.corrupt) case b: TLBundleE => Seq() } def getConstFields(b: TLChannel): Seq[Data] = b match { case b: TLBundleA => Seq(b.opcode, b.param, b.size, b.source, b.address, b.user, b.echo ) case b: TLBundleB => Seq(b.opcode, b.param, b.size, b.source, b.address ) case b: TLBundleC => Seq(b.opcode, b.param, b.size, b.source, b.address, b.user, b.echo ) case b: TLBundleD => Seq(b.opcode, b.param, b.size, b.source, b.user, b.echo, b.sink, b.denied) case b: TLBundleE => Seq( b.sink ) } def minTLPayloadWidth(b: TLChannel): Int = Seq(getBodyFields(b), getConstFields(b)).map(_.map(_.getWidth).sum).max def minTLPayloadWidth(bs: Seq[TLChannel]): Int = bs.map(b => minTLPayloadWidth(b)).max def minTLPayloadWidth(b: TLBundle): Int = minTLPayloadWidth(Seq(b.a, b.b, b.c, b.d, b.e).map(_.bits)) } class TLMasterToNoC( edgeIn: TLEdge, edgesOut: Seq[TLEdge], sourceStart: Int, sourceSize: Int, wideBundle: TLBundleParameters, slaveToEgressOffset: Int => Int, flitWidth: Int )(implicit p: Parameters) extends Module { val io = IO(new Bundle { val tilelink = Flipped(new TLBundle(wideBundle)) val flits = new Bundle { val a = Decoupled(new IngressFlit(flitWidth)) val b = Flipped(Decoupled(new EgressFlit(flitWidth))) val c = Decoupled(new IngressFlit(flitWidth)) val d = Flipped(Decoupled(new EgressFlit(flitWidth))) val e = Decoupled(new IngressFlit(flitWidth)) } }) val a = Module(new TLAToNoC(edgeIn, edgesOut, wideBundle, (i) => slaveToEgressOffset(i) + 0, sourceStart)) val b = Module(new TLBFromNoC(edgeIn, wideBundle, sourceSize)) val c = Module(new TLCToNoC(edgeIn, edgesOut, wideBundle, (i) => slaveToEgressOffset(i) + 1, sourceStart)) val d = Module(new TLDFromNoC(edgeIn, wideBundle, sourceSize)) val e = Module(new TLEToNoC(edgeIn, edgesOut, wideBundle, (i) => slaveToEgressOffset(i) + 2)) a.io.protocol <> io.tilelink.a io.tilelink.b <> b.io.protocol c.io.protocol <> io.tilelink.c io.tilelink.d <> d.io.protocol e.io.protocol <> io.tilelink.e io.flits.a <> a.io.flit b.io.flit <> io.flits.b io.flits.c <> c.io.flit d.io.flit <> io.flits.d io.flits.e <> e.io.flit } class TLMasterACDToNoC( edgeIn: TLEdge, edgesOut: Seq[TLEdge], sourceStart: Int, sourceSize: Int, wideBundle: TLBundleParameters, slaveToEgressOffset: Int => Int, flitWidth: Int )(implicit p: Parameters) extends Module { val io = IO(new Bundle { val tilelink = Flipped(new TLBundle(wideBundle)) val flits = new Bundle { val a = Decoupled(new IngressFlit(flitWidth)) val c = Decoupled(new IngressFlit(flitWidth)) val d = Flipped(Decoupled(new EgressFlit(flitWidth))) } }) io.tilelink := DontCare val a = Module(new TLAToNoC(edgeIn, edgesOut, wideBundle, (i) => slaveToEgressOffset(i) + 0, sourceStart)) val c = Module(new TLCToNoC(edgeIn, edgesOut, wideBundle, (i) => slaveToEgressOffset(i) + 1, sourceStart)) val d = Module(new TLDFromNoC(edgeIn, wideBundle, sourceSize)) a.io.protocol <> io.tilelink.a c.io.protocol <> io.tilelink.c io.tilelink.d <> d.io.protocol io.flits.a <> a.io.flit io.flits.c <> c.io.flit d.io.flit <> io.flits.d } class TLMasterBEToNoC( edgeIn: TLEdge, edgesOut: Seq[TLEdge], sourceStart: Int, sourceSize: Int, wideBundle: TLBundleParameters, slaveToEgressOffset: Int => Int, flitWidth: Int )(implicit p: Parameters) extends Module { val io = IO(new Bundle { val tilelink = Flipped(new TLBundle(wideBundle)) val flits = new Bundle { val b = Flipped(Decoupled(new EgressFlit(flitWidth))) val e = Decoupled(new IngressFlit(flitWidth)) } }) io.tilelink := DontCare val b = Module(new TLBFromNoC(edgeIn, wideBundle, sourceSize)) val e = Module(new TLEToNoC(edgeIn, edgesOut, wideBundle, (i) => slaveToEgressOffset(i) + 0)) io.tilelink.b <> b.io.protocol e.io.protocol <> io.tilelink.e b.io.flit <> io.flits.b io.flits.e <> e.io.flit } class TLSlaveToNoC( edgeOut: TLEdge, edgesIn: Seq[TLEdge], sourceStart: Int, sourceSize: Int, wideBundle: TLBundleParameters, masterToEgressOffset: Int => Int, flitWidth: Int )(implicit p: Parameters) extends Module { val io = IO(new Bundle { val tilelink = new TLBundle(wideBundle) val flits = new Bundle { val a = Flipped(Decoupled(new EgressFlit(flitWidth))) val b = Decoupled(new IngressFlit(flitWidth)) val c = Flipped(Decoupled(new EgressFlit(flitWidth))) val d = Decoupled(new IngressFlit(flitWidth)) val e = Flipped(Decoupled(new EgressFlit(flitWidth))) } }) val a = Module(new TLAFromNoC(edgeOut, wideBundle)) val b = Module(new TLBToNoC(edgeOut, edgesIn, wideBundle, (i) => masterToEgressOffset(i) + 0)) val c = Module(new TLCFromNoC(edgeOut, wideBundle)) val d = Module(new TLDToNoC(edgeOut, edgesIn, wideBundle, (i) => masterToEgressOffset(i) + 1, sourceStart)) val e = Module(new TLEFromNoC(edgeOut, wideBundle, sourceSize)) io.tilelink.a <> a.io.protocol b.io.protocol <> io.tilelink.b io.tilelink.c <> c.io.protocol d.io.protocol <> io.tilelink.d io.tilelink.e <> e.io.protocol a.io.flit <> io.flits.a io.flits.b <> b.io.flit c.io.flit <> io.flits.c io.flits.d <> d.io.flit e.io.flit <> io.flits.e } class TLSlaveACDToNoC( edgeOut: TLEdge, edgesIn: Seq[TLEdge], sourceStart: Int, sourceSize: Int, wideBundle: TLBundleParameters, masterToEgressOffset: Int => Int, flitWidth: Int )(implicit p: Parameters) extends Module { val io = IO(new Bundle { val tilelink = new TLBundle(wideBundle) val flits = new Bundle { val a = Flipped(Decoupled(new EgressFlit(flitWidth))) val c = Flipped(Decoupled(new EgressFlit(flitWidth))) val d = Decoupled(new IngressFlit(flitWidth)) } }) io.tilelink := DontCare val a = Module(new TLAFromNoC(edgeOut, wideBundle)) val c = Module(new TLCFromNoC(edgeOut, wideBundle)) val d = Module(new TLDToNoC(edgeOut, edgesIn, wideBundle, (i) => masterToEgressOffset(i) + 0, sourceStart)) io.tilelink.a <> a.io.protocol io.tilelink.c <> c.io.protocol d.io.protocol <> io.tilelink.d a.io.flit <> io.flits.a c.io.flit <> io.flits.c io.flits.d <> d.io.flit } class TLSlaveBEToNoC( edgeOut: TLEdge, edgesIn: Seq[TLEdge], sourceStart: Int, sourceSize: Int, wideBundle: TLBundleParameters, masterToEgressOffset: Int => Int, flitWidth: Int )(implicit p: Parameters) extends Module { val io = IO(new Bundle { val tilelink = new TLBundle(wideBundle) val flits = new Bundle { val b = Decoupled(new IngressFlit(flitWidth)) val e = Flipped(Decoupled(new EgressFlit(flitWidth))) } }) io.tilelink := DontCare val b = Module(new TLBToNoC(edgeOut, edgesIn, wideBundle, (i) => masterToEgressOffset(i) + 0)) val e = Module(new TLEFromNoC(edgeOut, wideBundle, sourceSize)) b.io.protocol <> io.tilelink.b io.tilelink.e <> e.io.protocol io.flits.b <> b.io.flit e.io.flit <> io.flits.e } class TileLinkInterconnectInterface(edgesIn: Seq[TLEdge], edgesOut: Seq[TLEdge])(implicit val p: Parameters) extends Bundle { val in = MixedVec(edgesIn.map { e => Flipped(new TLBundle(e.bundle)) }) val out = MixedVec(edgesOut.map { e => new TLBundle(e.bundle) }) } trait TileLinkProtocolParams extends ProtocolParams with TLFieldHelper { def edgesIn: Seq[TLEdge] def edgesOut: Seq[TLEdge] def edgeInNodes: Seq[Int] def edgeOutNodes: Seq[Int] require(edgesIn.size == edgeInNodes.size && edgesOut.size == edgeOutNodes.size) def wideBundle = TLBundleParameters.union(edgesIn.map(_.bundle) ++ edgesOut.map(_.bundle)) def genBundle = new TLBundle(wideBundle) def inputIdRanges = TLXbar.mapInputIds(edgesIn.map(_.client)) def outputIdRanges = TLXbar.mapOutputIds(edgesOut.map(_.manager)) val vNetBlocking = (blocker: Int, blockee: Int) => blocker < blockee def genIO()(implicit p: Parameters): Data = new TileLinkInterconnectInterface(edgesIn, edgesOut) } object TLConnect { def apply[T <: TLBundleBase](l: DecoupledIO[T], r: DecoupledIO[T]) = { l.valid := r.valid r.ready := l.ready l.bits.squeezeAll.waiveAll :<>= r.bits.squeezeAll.waiveAll } } // BEGIN: TileLinkProtocolParams case class TileLinkABCDEProtocolParams( edgesIn: Seq[TLEdge], edgesOut: Seq[TLEdge], edgeInNodes: Seq[Int], edgeOutNodes: Seq[Int] ) extends TileLinkProtocolParams { // END: TileLinkProtocolParams val minPayloadWidth = minTLPayloadWidth(new TLBundle(wideBundle)) val ingressNodes = (edgeInNodes.map(u => Seq.fill(3) (u)) ++ edgeOutNodes.map(u => Seq.fill (2) {u})).flatten val egressNodes = (edgeInNodes.map(u => Seq.fill(2) (u)) ++ edgeOutNodes.map(u => Seq.fill (3) {u})).flatten val nVirtualNetworks = 5 val flows = edgesIn.zipWithIndex.map { case (edgeIn, ii) => edgesOut.zipWithIndex.map { case (edgeOut, oi) => val reachable = edgeIn.client.clients.exists { c => edgeOut.manager.managers.exists { m => c.visibility.exists { ca => m.address.exists { ma => ca.overlaps(ma) }} }} val probe = edgeIn.client.anySupportProbe && edgeOut.manager.managers.exists(_.regionType >= RegionType.TRACKED) val release = edgeIn.client.anySupportProbe && edgeOut.manager.anySupportAcquireB ( (if (reachable) Some(FlowParams(ii * 3 + 0 , oi * 3 + 0 + edgesIn.size * 2, 4)) else None) ++ // A (if (probe ) Some(FlowParams(oi * 2 + 0 + edgesIn.size * 3, ii * 2 + 0 , 3)) else None) ++ // B (if (release ) Some(FlowParams(ii * 3 + 1 , oi * 3 + 1 + edgesIn.size * 2, 2)) else None) ++ // C (if (reachable) Some(FlowParams(oi * 2 + 1 + edgesIn.size * 3, ii * 2 + 1 , 1)) else None) ++ // D (if (release ) Some(FlowParams(ii * 3 + 2 , oi * 3 + 2 + edgesIn.size * 2, 0)) else None)) // E }}.flatten.flatten def interface(terminals: NoCTerminalIO, ingressOffset: Int, egressOffset: Int, protocol: Data)(implicit p: Parameters) = { val ingresses = terminals.ingress val egresses = terminals.egress protocol match { case protocol: TileLinkInterconnectInterface => { edgesIn.zipWithIndex.map { case (e,i) => val nif_master = Module(new TLMasterToNoC( e, edgesOut, inputIdRanges(i).start, inputIdRanges(i).size, wideBundle, (s) => s * 3 + edgesIn.size * 2 + egressOffset, minPayloadWidth )) nif_master.io.tilelink := DontCare nif_master.io.tilelink.a.valid := false.B nif_master.io.tilelink.c.valid := false.B nif_master.io.tilelink.e.valid := false.B TLConnect(nif_master.io.tilelink.a, protocol.in(i).a) TLConnect(protocol.in(i).d, nif_master.io.tilelink.d) if (protocol.in(i).params.hasBCE) { TLConnect(protocol.in(i).b, nif_master.io.tilelink.b) TLConnect(nif_master.io.tilelink.c, protocol.in(i).c) TLConnect(nif_master.io.tilelink.e, protocol.in(i).e) } ingresses(i * 3 + 0).flit <> nif_master.io.flits.a ingresses(i * 3 + 1).flit <> nif_master.io.flits.c ingresses(i * 3 + 2).flit <> nif_master.io.flits.e nif_master.io.flits.b <> egresses(i * 2 + 0).flit nif_master.io.flits.d <> egresses(i * 2 + 1).flit } edgesOut.zipWithIndex.map { case (e,i) => val nif_slave = Module(new TLSlaveToNoC( e, edgesIn, outputIdRanges(i).start, outputIdRanges(i).size, wideBundle, (s) => s * 2 + egressOffset, minPayloadWidth )) nif_slave.io.tilelink := DontCare nif_slave.io.tilelink.b.valid := false.B nif_slave.io.tilelink.d.valid := false.B TLConnect(protocol.out(i).a, nif_slave.io.tilelink.a) TLConnect(nif_slave.io.tilelink.d, protocol.out(i).d) if (protocol.out(i).params.hasBCE) { TLConnect(nif_slave.io.tilelink.b, protocol.out(i).b) TLConnect(protocol.out(i).c, nif_slave.io.tilelink.c) TLConnect(protocol.out(i).e, nif_slave.io.tilelink.e) } ingresses(i * 2 + 0 + edgesIn.size * 3).flit <> nif_slave.io.flits.b ingresses(i * 2 + 1 + edgesIn.size * 3).flit <> nif_slave.io.flits.d nif_slave.io.flits.a <> egresses(i * 3 + 0 + edgesIn.size * 2).flit nif_slave.io.flits.c <> egresses(i * 3 + 1 + edgesIn.size * 2).flit nif_slave.io.flits.e <> egresses(i * 3 + 2 + edgesIn.size * 2).flit } } } } } case class TileLinkACDProtocolParams( edgesIn: Seq[TLEdge], edgesOut: Seq[TLEdge], edgeInNodes: Seq[Int], edgeOutNodes: Seq[Int]) extends TileLinkProtocolParams { val minPayloadWidth = minTLPayloadWidth(Seq(genBundle.a, genBundle.c, genBundle.d).map(_.bits)) val ingressNodes = (edgeInNodes.map(u => Seq.fill(2) (u)) ++ edgeOutNodes.map(u => Seq.fill (1) {u})).flatten val egressNodes = (edgeInNodes.map(u => Seq.fill(1) (u)) ++ edgeOutNodes.map(u => Seq.fill (2) {u})).flatten val nVirtualNetworks = 3 val flows = edgesIn.zipWithIndex.map { case (edgeIn, ii) => edgesOut.zipWithIndex.map { case (edgeOut, oi) => val reachable = edgeIn.client.clients.exists { c => edgeOut.manager.managers.exists { m => c.visibility.exists { ca => m.address.exists { ma => ca.overlaps(ma) }} }} val release = edgeIn.client.anySupportProbe && edgeOut.manager.anySupportAcquireB ( (if (reachable) Some(FlowParams(ii * 2 + 0 , oi * 2 + 0 + edgesIn.size * 1, 2)) else None) ++ // A (if (release ) Some(FlowParams(ii * 2 + 1 , oi * 2 + 1 + edgesIn.size * 1, 1)) else None) ++ // C (if (reachable) Some(FlowParams(oi * 1 + 0 + edgesIn.size * 2, ii * 1 + 0 , 0)) else None)) // D }}.flatten.flatten def interface(terminals: NoCTerminalIO, ingressOffset: Int, egressOffset: Int, protocol: Data)(implicit p: Parameters) = { val ingresses = terminals.ingress val egresses = terminals.egress protocol match { case protocol: TileLinkInterconnectInterface => { protocol := DontCare edgesIn.zipWithIndex.map { case (e,i) => val nif_master_acd = Module(new TLMasterACDToNoC( e, edgesOut, inputIdRanges(i).start, inputIdRanges(i).size, wideBundle, (s) => s * 2 + edgesIn.size * 1 + egressOffset, minPayloadWidth )) nif_master_acd.io.tilelink := DontCare nif_master_acd.io.tilelink.a.valid := false.B nif_master_acd.io.tilelink.c.valid := false.B nif_master_acd.io.tilelink.e.valid := false.B TLConnect(nif_master_acd.io.tilelink.a, protocol.in(i).a) TLConnect(protocol.in(i).d, nif_master_acd.io.tilelink.d) if (protocol.in(i).params.hasBCE) { TLConnect(nif_master_acd.io.tilelink.c, protocol.in(i).c) } ingresses(i * 2 + 0).flit <> nif_master_acd.io.flits.a ingresses(i * 2 + 1).flit <> nif_master_acd.io.flits.c nif_master_acd.io.flits.d <> egresses(i * 1 + 0).flit } edgesOut.zipWithIndex.map { case (e,i) => val nif_slave_acd = Module(new TLSlaveACDToNoC( e, edgesIn, outputIdRanges(i).start, outputIdRanges(i).size, wideBundle, (s) => s * 1 + egressOffset, minPayloadWidth )) nif_slave_acd.io.tilelink := DontCare nif_slave_acd.io.tilelink.b.valid := false.B nif_slave_acd.io.tilelink.d.valid := false.B TLConnect(protocol.out(i).a, nif_slave_acd.io.tilelink.a) TLConnect(nif_slave_acd.io.tilelink.d, protocol.out(i).d) if (protocol.out(i).params.hasBCE) { TLConnect(protocol.out(i).c, nif_slave_acd.io.tilelink.c) } ingresses(i * 1 + 0 + edgesIn.size * 2).flit <> nif_slave_acd.io.flits.d nif_slave_acd.io.flits.a <> egresses(i * 2 + 0 + edgesIn.size * 1).flit nif_slave_acd.io.flits.c <> egresses(i * 2 + 1 + edgesIn.size * 1).flit } }} } } case class TileLinkBEProtocolParams( edgesIn: Seq[TLEdge], edgesOut: Seq[TLEdge], edgeInNodes: Seq[Int], edgeOutNodes: Seq[Int]) extends TileLinkProtocolParams { val minPayloadWidth = minTLPayloadWidth(Seq(genBundle.b, genBundle.e).map(_.bits)) val ingressNodes = (edgeInNodes.map(u => Seq.fill(1) (u)) ++ edgeOutNodes.map(u => Seq.fill (1) {u})).flatten val egressNodes = (edgeInNodes.map(u => Seq.fill(1) (u)) ++ edgeOutNodes.map(u => Seq.fill (1) {u})).flatten val nVirtualNetworks = 2 val flows = edgesIn.zipWithIndex.map { case (edgeIn, ii) => edgesOut.zipWithIndex.map { case (edgeOut, oi) => val probe = edgeIn.client.anySupportProbe && edgeOut.manager.managers.exists(_.regionType >= RegionType.TRACKED) val release = edgeIn.client.anySupportProbe && edgeOut.manager.anySupportAcquireB ( (if (probe ) Some(FlowParams(oi * 1 + 0 + edgesIn.size * 1, ii * 1 + 0 , 1)) else None) ++ // B (if (release ) Some(FlowParams(ii * 1 + 0 , oi * 1 + 0 + edgesIn.size * 1, 0)) else None)) // E }}.flatten.flatten def interface(terminals: NoCTerminalIO, ingressOffset: Int, egressOffset: Int, protocol: Data)(implicit p: Parameters) = { val ingresses = terminals.ingress val egresses = terminals.egress protocol match { case protocol: TileLinkInterconnectInterface => { protocol := DontCare edgesIn.zipWithIndex.map { case (e,i) => val nif_master_be = Module(new TLMasterBEToNoC( e, edgesOut, inputIdRanges(i).start, inputIdRanges(i).size, wideBundle, (s) => s * 1 + edgesIn.size * 1 + egressOffset, minPayloadWidth )) nif_master_be.io.tilelink := DontCare nif_master_be.io.tilelink.a.valid := false.B nif_master_be.io.tilelink.c.valid := false.B nif_master_be.io.tilelink.e.valid := false.B if (protocol.in(i).params.hasBCE) { TLConnect(protocol.in(i).b, nif_master_be.io.tilelink.b) TLConnect(nif_master_be.io.tilelink.e, protocol.in(i).e) } ingresses(i * 1 + 0).flit <> nif_master_be.io.flits.e nif_master_be.io.flits.b <> egresses(i * 1 + 0).flit } edgesOut.zipWithIndex.map { case (e,i) => val nif_slave_be = Module(new TLSlaveBEToNoC( e, edgesIn, outputIdRanges(i).start, outputIdRanges(i).size, wideBundle, (s) => s * 1 + egressOffset, minPayloadWidth )) nif_slave_be.io.tilelink := DontCare nif_slave_be.io.tilelink.b.valid := false.B nif_slave_be.io.tilelink.d.valid := false.B if (protocol.out(i).params.hasBCE) { TLConnect(protocol.out(i).e, nif_slave_be.io.tilelink.e) TLConnect(nif_slave_be.io.tilelink.b, protocol.out(i).b) } ingresses(i * 1 + 0 + edgesIn.size * 1).flit <> nif_slave_be.io.flits.b nif_slave_be.io.flits.e <> egresses(i * 1 + 0 + edgesIn.size * 1).flit } }} } } abstract class TLNoCLike(implicit p: Parameters) extends LazyModule { val node = new TLNexusNode( clientFn = { seq => seq(0).v1copy( echoFields = BundleField.union(seq.flatMap(_.echoFields)), requestFields = BundleField.union(seq.flatMap(_.requestFields)), responseKeys = seq.flatMap(_.responseKeys).distinct, minLatency = seq.map(_.minLatency).min, clients = (TLXbar.mapInputIds(seq) zip seq) flatMap { case (range, port) => port.clients map { client => client.v1copy( sourceId = client.sourceId.shift(range.start) )} } ) }, managerFn = { seq => val fifoIdFactory = TLXbar.relabeler() seq(0).v1copy( responseFields = BundleField.union(seq.flatMap(_.responseFields)), requestKeys = seq.flatMap(_.requestKeys).distinct, minLatency = seq.map(_.minLatency).min, endSinkId = TLXbar.mapOutputIds(seq).map(_.end).max, managers = seq.flatMap { port => require (port.beatBytes == seq(0).beatBytes, s"TLNoC (data widths don't match: ${port.managers.map(_.name)} has ${port.beatBytes}B vs ${seq(0).managers.map(_.name)} has ${seq(0).beatBytes}B") // TileLink NoC does not preserve FIFO-ness, masters to this NoC should instantiate FIFOFixers port.managers map { manager => manager.v1copy(fifoId = None) } } ) } ) } abstract class TLNoCModuleImp(outer: LazyModule) extends LazyModuleImp(outer) { val edgesIn: Seq[TLEdge] val edgesOut: Seq[TLEdge] val nodeMapping: DiplomaticNetworkNodeMapping val nocName: String lazy val inNames = nodeMapping.genUniqueName(edgesIn.map(_.master.masters.map(_.name))) lazy val outNames = nodeMapping.genUniqueName(edgesOut.map(_.slave.slaves.map(_.name))) lazy val edgeInNodes = nodeMapping.getNodesIn(inNames) lazy val edgeOutNodes = nodeMapping.getNodesOut(outNames) def printNodeMappings() { println(s"Constellation: TLNoC $nocName inwards mapping:") for ((n, i) <- inNames zip edgeInNodes) { val node = i.map(_.toString).getOrElse("X") println(s" $node <- $n") } println(s"Constellation: TLNoC $nocName outwards mapping:") for ((n, i) <- outNames zip edgeOutNodes) { val node = i.map(_.toString).getOrElse("X") println(s" $node <- $n") } } } trait TLNoCParams // Instantiates a private TLNoC. Replaces the TLXbar // BEGIN: TLNoCParams case class SimpleTLNoCParams( nodeMappings: DiplomaticNetworkNodeMapping, nocParams: NoCParams = NoCParams(), ) extends TLNoCParams class TLNoC(params: SimpleTLNoCParams, name: String = "test", inlineNoC: Boolean = false)(implicit p: Parameters) extends TLNoCLike { // END: TLNoCParams override def shouldBeInlined = inlineNoC lazy val module = new TLNoCModuleImp(this) { val (io_in, edgesIn) = node.in.unzip val (io_out, edgesOut) = node.out.unzip val nodeMapping = params.nodeMappings val nocName = name printNodeMappings() val protocolParams = TileLinkABCDEProtocolParams( edgesIn = edgesIn, edgesOut = edgesOut, edgeInNodes = edgeInNodes.flatten, edgeOutNodes = edgeOutNodes.flatten ) val noc = Module(new ProtocolNoC(ProtocolNoCParams( params.nocParams.copy(hasCtrl = false, nocName=name, inlineNoC = inlineNoC), Seq(protocolParams), inlineNoC = inlineNoC ))) noc.io.protocol(0) match { case protocol: TileLinkInterconnectInterface => { (protocol.in zip io_in).foreach { case (l,r) => l <> r } (io_out zip protocol.out).foreach { case (l,r) => l <> r } } } } } case class SplitACDxBETLNoCParams( nodeMappings: DiplomaticNetworkNodeMapping, acdNoCParams: NoCParams = NoCParams(), beNoCParams: NoCParams = NoCParams(), beDivision: Int = 2 ) extends TLNoCParams class TLSplitACDxBENoC(params: SplitACDxBETLNoCParams, name: String = "test", inlineNoC: Boolean = false)(implicit p: Parameters) extends TLNoCLike { override def shouldBeInlined = inlineNoC lazy val module = new TLNoCModuleImp(this) { val (io_in, edgesIn) = node.in.unzip val (io_out, edgesOut) = node.out.unzip val nodeMapping = params.nodeMappings val nocName = name printNodeMappings() val acdProtocolParams = TileLinkACDProtocolParams( edgesIn = edgesIn, edgesOut = edgesOut, edgeInNodes = edgeInNodes.flatten, edgeOutNodes = edgeOutNodes.flatten ) val beProtocolParams = TileLinkBEProtocolParams( edgesIn = edgesIn, edgesOut = edgesOut, edgeInNodes = edgeInNodes.flatten, edgeOutNodes = edgeOutNodes.flatten ) val acd_noc = Module(new ProtocolNoC(ProtocolNoCParams( params.acdNoCParams.copy(hasCtrl = false, nocName=s"${name}_acd", inlineNoC = inlineNoC), Seq(acdProtocolParams), inlineNoC = inlineNoC ))) val be_noc = Module(new ProtocolNoC(ProtocolNoCParams( params.beNoCParams.copy(hasCtrl = false, nocName=s"${name}_be", inlineNoC = inlineNoC), Seq(beProtocolParams), widthDivision = params.beDivision, inlineNoC = inlineNoC ))) acd_noc.io.protocol(0) match { case protocol: TileLinkInterconnectInterface => { (protocol.in zip io_in).foreach { case (l,r) => l := DontCare l.a <> r.a l.c <> r.c l.d <> r.d } (io_out zip protocol.out).foreach { case (l,r) => r := DontCare l.a <> r.a l.c <> r.c l.d <> r.d } }} be_noc.io.protocol(0) match { case protocol: TileLinkInterconnectInterface => { (protocol.in zip io_in).foreach { case (l,r) => l := DontCare l.b <> r.b l.e <> r.e } (io_out zip protocol.out).foreach { case (l,r) => r := DontCare l.b <> r.b l.e <> r.e } }} } } case class GlobalTLNoCParams( nodeMappings: DiplomaticNetworkNodeMapping ) extends TLNoCParams // Maps this interconnect onto a global NoC class TLGlobalNoC(params: GlobalTLNoCParams, name: String = "test")(implicit p: Parameters) extends TLNoCLike { lazy val module = new TLNoCModuleImp(this) with CanAttachToGlobalNoC { val (io_in, edgesIn) = node.in.unzip val (io_out, edgesOut) = node.out.unzip val nodeMapping = params.nodeMappings val nocName = name val protocolParams = TileLinkABCDEProtocolParams( edgesIn = edgesIn, edgesOut = edgesOut, edgeInNodes = edgeInNodes.flatten, edgeOutNodes = edgeOutNodes.flatten ) printNodeMappings() val io_global = IO(Flipped(protocolParams.genIO())) io_global match { case protocol: TileLinkInterconnectInterface => { (protocol.in zip io_in).foreach { case (l,r) => l <> r } (io_out zip protocol.out).foreach { case (l,r) => l <> r } } } } }	module TLMasterBEToNoC( // @[Tilelink.scala:100:7] input clock, // @[Tilelink.scala:100:7] input reset, // @[Tilelink.scala:100:7] output io_flits_b_ready, // @[Tilelink.scala:107:14] input io_flits_b_valid, // @[Tilelink.scala:107:14] input io_flits_b_bits_head, // @[Tilelink.scala:107:14] input io_flits_b_bits_tail, // @[Tilelink.scala:107:14] input io_flits_e_ready, // @[Tilelink.scala:107:14] output io_flits_e_valid, // @[Tilelink.scala:107:14] output io_flits_e_bits_head, // @[Tilelink.scala:107:14] output [144:0] io_flits_e_bits_payload, // @[Tilelink.scala:107:14] output [4:0] io_flits_e_bits_egress_id // @[Tilelink.scala:107:14] ); wire [5:0] _e_io_flit_bits_payload; // @[Tilelink.scala:116:17] TLBFromNoC b ( // @[Tilelink.scala:115:17] .clock (clock), .reset (reset), .io_flit_ready (io_flits_b_ready), .io_flit_valid (io_flits_b_valid), .io_flit_bits_head (io_flits_b_bits_head), .io_flit_bits_tail (io_flits_b_bits_tail) ); // @[Tilelink.scala:115:17] TLEToNoC e ( // @[Tilelink.scala:116:17] .clock (clock), .reset (reset), .io_protocol_ready (/* unused */), .io_protocol_valid (1'h0), // @[Tilelink.scala:107:14, :115:17, :116:17] .io_protocol_bits_sink (6'h0), // @[Tilelink.scala:107:14, :116:17] .io_flit_ready (io_flits_e_ready), .io_flit_valid (io_flits_e_valid), .io_flit_bits_head (io_flits_e_bits_head), .io_flit_bits_payload (_e_io_flit_bits_payload), .io_flit_bits_egress_id (io_flits_e_bits_egress_id) ); // @[Tilelink.scala:116:17] assign io_flits_e_bits_payload = {139'h0, _e_io_flit_bits_payload}; // @[Tilelink.scala:100:7, :116:17, :121:14] endmodule
Generate the Verilog code corresponding to the following Chisel files. File Tile.scala: // See README.md for license details. package gemmini import chisel3._ import chisel3.util._ import Util._ /** * A Tile is a purely combinational 2D array of passThrough PEs. * a, b, s, and in_propag are broadcast across the entire array and are passed through to the Tile's outputs * @param width The data width of each PE in bits * @param rows Number of PEs on each row * @param columns Number of PEs on each column */ class Tile[T <: Data](inputType: T, outputType: T, accType: T, df: Dataflow.Value, tree_reduction: Boolean, max_simultaneous_matmuls: Int, val rows: Int, val columns: Int)(implicit ev: Arithmetic[T]) extends Module { val io = IO(new Bundle { val in_a = Input(Vec(rows, inputType)) val in_b = Input(Vec(columns, outputType)) // This is the output of the tile next to it val in_d = Input(Vec(columns, outputType)) val in_control = Input(Vec(columns, new PEControl(accType))) val in_id = Input(Vec(columns, UInt(log2Up(max_simultaneous_matmuls).W))) val in_last = Input(Vec(columns, Bool())) val out_a = Output(Vec(rows, inputType)) val out_c = Output(Vec(columns, outputType)) val out_b = Output(Vec(columns, outputType)) val out_control = Output(Vec(columns, new PEControl(accType))) val out_id = Output(Vec(columns, UInt(log2Up(max_simultaneous_matmuls).W))) val out_last = Output(Vec(columns, Bool())) val in_valid = Input(Vec(columns, Bool())) val out_valid = Output(Vec(columns, Bool())) val bad_dataflow = Output(Bool()) }) import ev._ val tile = Seq.fill(rows, columns)(Module(new PE(inputType, outputType, accType, df, max_simultaneous_matmuls))) val tileT = tile.transpose // TODO: abstract hori/vert broadcast, all these connections look the same // Broadcast 'a' horizontally across the Tile for (r <- 0 until rows) { tile(r).foldLeft(io.in_a(r)) { case (in_a, pe) => pe.io.in_a := in_a pe.io.out_a } } // Broadcast 'b' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_b(c)) { case (in_b, pe) => pe.io.in_b := (if (tree_reduction) in_b.zero else in_b) pe.io.out_b } } // Broadcast 'd' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_d(c)) { case (in_d, pe) => pe.io.in_d := in_d pe.io.out_c } } // Broadcast 'control' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_control(c)) { case (in_ctrl, pe) => pe.io.in_control := in_ctrl pe.io.out_control } } // Broadcast 'garbage' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_valid(c)) { case (v, pe) => pe.io.in_valid := v pe.io.out_valid } } // Broadcast 'id' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_id(c)) { case (id, pe) => pe.io.in_id := id pe.io.out_id } } // Broadcast 'last' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_last(c)) { case (last, pe) => pe.io.in_last := last pe.io.out_last } } // Drive the Tile's bottom IO for (c <- 0 until columns) { io.out_c(c) := tile(rows-1)(c).io.out_c io.out_control(c) := tile(rows-1)(c).io.out_control io.out_id(c) := tile(rows-1)(c).io.out_id io.out_last(c) := tile(rows-1)(c).io.out_last io.out_valid(c) := tile(rows-1)(c).io.out_valid io.out_b(c) := { if (tree_reduction) { val prods = tileT(c).map(_.io.out_b) accumulateTree(prods :+ io.in_b(c)) } else { tile(rows - 1)(c).io.out_b } } } io.bad_dataflow := tile.map(_.map(_.io.bad_dataflow).reduce(_\|\|_)).reduce(_\|\|_) // Drive the Tile's right IO for (r <- 0 until rows) { io.out_a(r) := tile(r)(columns-1).io.out_a } }	module Tile_190( // @[Tile.scala:16:7] input clock, // @[Tile.scala:16:7] input reset, // @[Tile.scala:16:7] input [7:0] io_in_a_0, // @[Tile.scala:17:14] input [19:0] io_in_b_0, // @[Tile.scala:17:14] input [19:0] io_in_d_0, // @[Tile.scala:17:14] input io_in_control_0_dataflow, // @[Tile.scala:17:14] input io_in_control_0_propagate, // @[Tile.scala:17:14] input [4:0] io_in_control_0_shift, // @[Tile.scala:17:14] input [2:0] io_in_id_0, // @[Tile.scala:17:14] input io_in_last_0, // @[Tile.scala:17:14] output [7:0] io_out_a_0, // @[Tile.scala:17:14] output [19:0] io_out_c_0, // @[Tile.scala:17:14] output [19:0] io_out_b_0, // @[Tile.scala:17:14] output io_out_control_0_dataflow, // @[Tile.scala:17:14] output io_out_control_0_propagate, // @[Tile.scala:17:14] output [4:0] io_out_control_0_shift, // @[Tile.scala:17:14] output [2:0] io_out_id_0, // @[Tile.scala:17:14] output io_out_last_0, // @[Tile.scala:17:14] input io_in_valid_0, // @[Tile.scala:17:14] output io_out_valid_0, // @[Tile.scala:17:14] output io_bad_dataflow // @[Tile.scala:17:14] ); wire [7:0] io_in_a_0_0 = io_in_a_0; // @[Tile.scala:16:7] wire [19:0] io_in_b_0_0 = io_in_b_0; // @[Tile.scala:16:7] wire [19:0] io_in_d_0_0 = io_in_d_0; // @[Tile.scala:16:7] wire io_in_control_0_dataflow_0 = io_in_control_0_dataflow; // @[Tile.scala:16:7] wire io_in_control_0_propagate_0 = io_in_control_0_propagate; // @[Tile.scala:16:7] wire [4:0] io_in_control_0_shift_0 = io_in_control_0_shift; // @[Tile.scala:16:7] wire [2:0] io_in_id_0_0 = io_in_id_0; // @[Tile.scala:16:7] wire io_in_last_0_0 = io_in_last_0; // @[Tile.scala:16:7] wire io_in_valid_0_0 = io_in_valid_0; // @[Tile.scala:16:7] wire [7:0] io_out_a_0_0; // @[Tile.scala:16:7] wire [19:0] io_out_c_0_0; // @[Tile.scala:16:7] wire [19:0] io_out_b_0_0; // @[Tile.scala:16:7] wire io_out_control_0_dataflow_0; // @[Tile.scala:16:7] wire io_out_control_0_propagate_0; // @[Tile.scala:16:7] wire [4:0] io_out_control_0_shift_0; // @[Tile.scala:16:7] wire [2:0] io_out_id_0_0; // @[Tile.scala:16:7] wire io_out_last_0_0; // @[Tile.scala:16:7] wire io_out_valid_0_0; // @[Tile.scala:16:7] wire io_bad_dataflow_0; // @[Tile.scala:16:7] PE_446 tile_0_0 ( // @[Tile.scala:42:44] .clock (clock), .reset (reset), .io_in_a (io_in_a_0_0), // @[Tile.scala:16:7] .io_in_b (io_in_b_0_0), // @[Tile.scala:16:7] .io_in_d (io_in_d_0_0), // @[Tile.scala:16:7] .io_out_a (io_out_a_0_0), .io_out_b (io_out_b_0_0), .io_out_c (io_out_c_0_0), .io_in_control_dataflow (io_in_control_0_dataflow_0), // @[Tile.scala:16:7] .io_in_control_propagate (io_in_control_0_propagate_0), // @[Tile.scala:16:7] .io_in_control_shift (io_in_control_0_shift_0), // @[Tile.scala:16:7] .io_out_control_dataflow (io_out_control_0_dataflow_0), .io_out_control_propagate (io_out_control_0_propagate_0), .io_out_control_shift (io_out_control_0_shift_0), .io_in_id (io_in_id_0_0), // @[Tile.scala:16:7] .io_out_id (io_out_id_0_0), .io_in_last (io_in_last_0_0), // @[Tile.scala:16:7] .io_out_last (io_out_last_0_0), .io_in_valid (io_in_valid_0_0), // @[Tile.scala:16:7] .io_out_valid (io_out_valid_0_0), .io_bad_dataflow (io_bad_dataflow_0) ); // @[Tile.scala:42:44] assign io_out_a_0 = io_out_a_0_0; // @[Tile.scala:16:7] assign io_out_c_0 = io_out_c_0_0; // @[Tile.scala:16:7] assign io_out_b_0 = io_out_b_0_0; // @[Tile.scala:16:7] assign io_out_control_0_dataflow = io_out_control_0_dataflow_0; // @[Tile.scala:16:7] assign io_out_control_0_propagate = io_out_control_0_propagate_0; // @[Tile.scala:16:7] assign io_out_control_0_shift = io_out_control_0_shift_0; // @[Tile.scala:16:7] assign io_out_id_0 = io_out_id_0_0; // @[Tile.scala:16:7] assign io_out_last_0 = io_out_last_0_0; // @[Tile.scala:16:7] assign io_out_valid_0 = io_out_valid_0_0; // @[Tile.scala:16:7] assign io_bad_dataflow = io_bad_dataflow_0; // @[Tile.scala:16:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File ShiftReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ // Similar to the Chisel ShiftRegister but allows the user to suggest a // name to the registers that get instantiated, and // to provide a reset value. object ShiftRegInit { def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T = (0 until n).foldRight(in) { case (i, next) => { val r = RegNext(next, init) name.foreach { na => r.suggestName(s"${na}_${i}") } r } } } /** These wrap behavioral * shift registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * The different types vary in their reset behavior: * AsyncResetShiftReg -- Asynchronously reset register array * A W(width) x D(depth) sized array is constructed from D instantiations of a * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg, * but only used for timing applications / abstract class AbstractPipelineReg(w: Int = 1) extends Module { val io = IO(new Bundle { val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) } ) } object AbstractPipelineReg { def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = { val chain = Module(gen) name.foreach{ chain.suggestName(_) } chain.io.d := in.asUInt chain.io.q.asTypeOf(in) } } class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) { require(depth > 0, "Depth must be greater than 0.") override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}" val chain = List.tabulate(depth) { i => Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}") } chain.last.io.d := io.d chain.last.io.en := true.B (chain.init zip chain.tail).foreach { case (sink, source) => sink.io.d := source.io.q sink.io.en := true.B } io.q := chain.head.io.q } object AsyncResetShiftReg { def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name) def apply [T <: Data](in: T, depth: Int, name: Option[String]): T = apply(in, depth, 0, name) def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T = apply(in, depth, init.litValue.toInt, name) def apply [T <: Data](in: T, depth: Int, init: T): T = apply (in, depth, init.litValue.toInt, None) } File SynchronizerReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util.{RegEnable, Cat} /* These wrap behavioral * shift and next registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * * These are built up of ResetSynchronizerPrimitiveShiftReg, intended to be replaced by the integrator's metastable flops chains or replaced * at this level if they have a multi-bit wide synchronizer primitive. * The different types vary in their reset behavior: * NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin * AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep * 1-bit-wide shift registers. * SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg * * [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference. * * ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross * Clock Domains. */ object SynchronizerResetType extends Enumeration { val NonSync, Inferred, Sync, Async = Value } // Note: this should not be used directly. // Use the companion object to generate this with the correct reset type mixin. private class SynchronizerPrimitiveShiftReg( sync: Int, init: Boolean, resetType: SynchronizerResetType.Value) extends AbstractPipelineReg(1) { val initInt = if (init) 1 else 0 val initPostfix = resetType match { case SynchronizerResetType.NonSync => "" case _ => s"_i${initInt}" } override def desiredName = s"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}" val chain = List.tabulate(sync) { i => val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B) reg.suggestName(s"sync_$i") } chain.last := io.d.asBool (chain.init zip chain.tail).foreach { case (sink, source) => sink := source } io.q := chain.head.asUInt } private object SynchronizerPrimitiveShiftReg { def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = { val gen: () => SynchronizerPrimitiveShiftReg = resetType match { case SynchronizerResetType.NonSync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) case SynchronizerResetType.Async => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset case SynchronizerResetType.Sync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset case SynchronizerResetType.Inferred => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) } AbstractPipelineReg(gen(), in) } } // Note: This module may end up with a non-AsyncReset type reset. // But the Primitives within will always have AsyncReset type. class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asAsyncReset){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async) } } io.q := Cat(output.reverse) } object AsyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } // Note: This module may end up with a non-Bool type reset. // But the Primitives within will always have Bool reset type. @deprecated("SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.", "rocket-chip 1.2") class SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asBool){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync) } } io.q := Cat(output.reverse) } object SyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred) } io.q := Cat(output.reverse) } object ResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}" val output = Seq.tabulate(w) { i => SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync) } io.q := Cat(output.reverse) } object SynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, None) def apply [T <: Data](in: T): T = apply (in, 3, None) } class ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module { override def desiredName = s"ClockCrossingReg_w${w}" val io = IO(new Bundle{ val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) val en = Input(Bool()) }) val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en) io.q := cdc_reg } object ClockCrossingReg { def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = { val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit)) name.foreach{ cdc_reg.suggestName(_) } cdc_reg.io.d := in.asUInt cdc_reg.io.en := en cdc_reg.io.q.asTypeOf(in) } }	module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_82( // @[SynchronizerReg.scala:68:19] input clock, // @[SynchronizerReg.scala:68:19] input reset, // @[SynchronizerReg.scala:68:19] input io_d, // @[ShiftReg.scala:36:14] output io_q // @[ShiftReg.scala:36:14] ); wire io_d_0 = io_d; // @[SynchronizerReg.scala:68:19] wire _sync_2_T = io_d_0; // @[SynchronizerReg.scala:54:22, :68:19] wire io_q_0; // @[SynchronizerReg.scala:68:19] reg sync_0; // @[SynchronizerReg.scala:51:87] assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19] reg sync_1; // @[SynchronizerReg.scala:51:87] reg sync_2; // @[SynchronizerReg.scala:51:87] always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19] if (reset) begin // @[SynchronizerReg.scala:68:19] sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87] end else begin // @[SynchronizerReg.scala:68:19] sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87] sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87] sync_2 <= _sync_2_T; // @[SynchronizerReg.scala:51:87, :54:22] end always @(posedge, posedge)
Generate the Verilog code corresponding to the following Chisel files. File Tile.scala: // See README.md for license details. package gemmini import chisel3._ import chisel3.util._ import Util._ /** * A Tile is a purely combinational 2D array of passThrough PEs. * a, b, s, and in_propag are broadcast across the entire array and are passed through to the Tile's outputs * @param width The data width of each PE in bits * @param rows Number of PEs on each row * @param columns Number of PEs on each column */ class Tile[T <: Data](inputType: T, outputType: T, accType: T, df: Dataflow.Value, tree_reduction: Boolean, max_simultaneous_matmuls: Int, val rows: Int, val columns: Int)(implicit ev: Arithmetic[T]) extends Module { val io = IO(new Bundle { val in_a = Input(Vec(rows, inputType)) val in_b = Input(Vec(columns, outputType)) // This is the output of the tile next to it val in_d = Input(Vec(columns, outputType)) val in_control = Input(Vec(columns, new PEControl(accType))) val in_id = Input(Vec(columns, UInt(log2Up(max_simultaneous_matmuls).W))) val in_last = Input(Vec(columns, Bool())) val out_a = Output(Vec(rows, inputType)) val out_c = Output(Vec(columns, outputType)) val out_b = Output(Vec(columns, outputType)) val out_control = Output(Vec(columns, new PEControl(accType))) val out_id = Output(Vec(columns, UInt(log2Up(max_simultaneous_matmuls).W))) val out_last = Output(Vec(columns, Bool())) val in_valid = Input(Vec(columns, Bool())) val out_valid = Output(Vec(columns, Bool())) val bad_dataflow = Output(Bool()) }) import ev._ val tile = Seq.fill(rows, columns)(Module(new PE(inputType, outputType, accType, df, max_simultaneous_matmuls))) val tileT = tile.transpose // TODO: abstract hori/vert broadcast, all these connections look the same // Broadcast 'a' horizontally across the Tile for (r <- 0 until rows) { tile(r).foldLeft(io.in_a(r)) { case (in_a, pe) => pe.io.in_a := in_a pe.io.out_a } } // Broadcast 'b' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_b(c)) { case (in_b, pe) => pe.io.in_b := (if (tree_reduction) in_b.zero else in_b) pe.io.out_b } } // Broadcast 'd' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_d(c)) { case (in_d, pe) => pe.io.in_d := in_d pe.io.out_c } } // Broadcast 'control' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_control(c)) { case (in_ctrl, pe) => pe.io.in_control := in_ctrl pe.io.out_control } } // Broadcast 'garbage' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_valid(c)) { case (v, pe) => pe.io.in_valid := v pe.io.out_valid } } // Broadcast 'id' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_id(c)) { case (id, pe) => pe.io.in_id := id pe.io.out_id } } // Broadcast 'last' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_last(c)) { case (last, pe) => pe.io.in_last := last pe.io.out_last } } // Drive the Tile's bottom IO for (c <- 0 until columns) { io.out_c(c) := tile(rows-1)(c).io.out_c io.out_control(c) := tile(rows-1)(c).io.out_control io.out_id(c) := tile(rows-1)(c).io.out_id io.out_last(c) := tile(rows-1)(c).io.out_last io.out_valid(c) := tile(rows-1)(c).io.out_valid io.out_b(c) := { if (tree_reduction) { val prods = tileT(c).map(_.io.out_b) accumulateTree(prods :+ io.in_b(c)) } else { tile(rows - 1)(c).io.out_b } } } io.bad_dataflow := tile.map(_.map(_.io.bad_dataflow).reduce(_\|\|_)).reduce(_\|\|_) // Drive the Tile's right IO for (r <- 0 until rows) { io.out_a(r) := tile(r)(columns-1).io.out_a } }	module Tile_232( // @[Tile.scala:16:7] input clock, // @[Tile.scala:16:7] input reset, // @[Tile.scala:16:7] input [7:0] io_in_a_0, // @[Tile.scala:17:14] input [19:0] io_in_b_0, // @[Tile.scala:17:14] input [19:0] io_in_d_0, // @[Tile.scala:17:14] input io_in_control_0_dataflow, // @[Tile.scala:17:14] input io_in_control_0_propagate, // @[Tile.scala:17:14] input [4:0] io_in_control_0_shift, // @[Tile.scala:17:14] input [2:0] io_in_id_0, // @[Tile.scala:17:14] input io_in_last_0, // @[Tile.scala:17:14] output [7:0] io_out_a_0, // @[Tile.scala:17:14] output [19:0] io_out_c_0, // @[Tile.scala:17:14] output [19:0] io_out_b_0, // @[Tile.scala:17:14] output io_out_control_0_dataflow, // @[Tile.scala:17:14] output io_out_control_0_propagate, // @[Tile.scala:17:14] output [4:0] io_out_control_0_shift, // @[Tile.scala:17:14] output [2:0] io_out_id_0, // @[Tile.scala:17:14] output io_out_last_0, // @[Tile.scala:17:14] input io_in_valid_0, // @[Tile.scala:17:14] output io_out_valid_0 // @[Tile.scala:17:14] ); wire [7:0] io_in_a_0_0 = io_in_a_0; // @[Tile.scala:16:7] wire [19:0] io_in_b_0_0 = io_in_b_0; // @[Tile.scala:16:7] wire [19:0] io_in_d_0_0 = io_in_d_0; // @[Tile.scala:16:7] wire io_in_control_0_dataflow_0 = io_in_control_0_dataflow; // @[Tile.scala:16:7] wire io_in_control_0_propagate_0 = io_in_control_0_propagate; // @[Tile.scala:16:7] wire [4:0] io_in_control_0_shift_0 = io_in_control_0_shift; // @[Tile.scala:16:7] wire [2:0] io_in_id_0_0 = io_in_id_0; // @[Tile.scala:16:7] wire io_in_last_0_0 = io_in_last_0; // @[Tile.scala:16:7] wire io_in_valid_0_0 = io_in_valid_0; // @[Tile.scala:16:7] wire io_bad_dataflow = 1'h0; // @[Tile.scala:16:7, :17:14, :42:44] wire [7:0] io_out_a_0_0; // @[Tile.scala:16:7] wire [19:0] io_out_c_0_0; // @[Tile.scala:16:7] wire [19:0] io_out_b_0_0; // @[Tile.scala:16:7] wire io_out_control_0_dataflow_0; // @[Tile.scala:16:7] wire io_out_control_0_propagate_0; // @[Tile.scala:16:7] wire [4:0] io_out_control_0_shift_0; // @[Tile.scala:16:7] wire [2:0] io_out_id_0_0; // @[Tile.scala:16:7] wire io_out_last_0_0; // @[Tile.scala:16:7] wire io_out_valid_0_0; // @[Tile.scala:16:7] PE_488 tile_0_0 ( // @[Tile.scala:42:44] .clock (clock), .reset (reset), .io_in_a (io_in_a_0_0), // @[Tile.scala:16:7] .io_in_b (io_in_b_0_0), // @[Tile.scala:16:7] .io_in_d (io_in_d_0_0), // @[Tile.scala:16:7] .io_out_a (io_out_a_0_0), .io_out_b (io_out_b_0_0), .io_out_c (io_out_c_0_0), .io_in_control_dataflow (io_in_control_0_dataflow_0), // @[Tile.scala:16:7] .io_in_control_propagate (io_in_control_0_propagate_0), // @[Tile.scala:16:7] .io_in_control_shift (io_in_control_0_shift_0), // @[Tile.scala:16:7] .io_out_control_dataflow (io_out_control_0_dataflow_0), .io_out_control_propagate (io_out_control_0_propagate_0), .io_out_control_shift (io_out_control_0_shift_0), .io_in_id (io_in_id_0_0), // @[Tile.scala:16:7] .io_out_id (io_out_id_0_0), .io_in_last (io_in_last_0_0), // @[Tile.scala:16:7] .io_out_last (io_out_last_0_0), .io_in_valid (io_in_valid_0_0), // @[Tile.scala:16:7] .io_out_valid (io_out_valid_0_0) ); // @[Tile.scala:42:44] assign io_out_a_0 = io_out_a_0_0; // @[Tile.scala:16:7] assign io_out_c_0 = io_out_c_0_0; // @[Tile.scala:16:7] assign io_out_b_0 = io_out_b_0_0; // @[Tile.scala:16:7] assign io_out_control_0_dataflow = io_out_control_0_dataflow_0; // @[Tile.scala:16:7] assign io_out_control_0_propagate = io_out_control_0_propagate_0; // @[Tile.scala:16:7] assign io_out_control_0_shift = io_out_control_0_shift_0; // @[Tile.scala:16:7] assign io_out_id_0 = io_out_id_0_0; // @[Tile.scala:16:7] assign io_out_last_0 = io_out_last_0_0; // @[Tile.scala:16:7] assign io_out_valid_0 = io_out_valid_0_0; // @[Tile.scala:16:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File SynchronizerReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util.{RegEnable, Cat} /** These wrap behavioral * shift and next registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * * These are built up of ResetSynchronizerPrimitiveShiftReg, intended to be replaced by the integrator's metastable flops chains or replaced * at this level if they have a multi-bit wide synchronizer primitive. * The different types vary in their reset behavior: * NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin * AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep * 1-bit-wide shift registers. * SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg * * [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference. * * ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross * Clock Domains. */ object SynchronizerResetType extends Enumeration { val NonSync, Inferred, Sync, Async = Value } // Note: this should not be used directly. // Use the companion object to generate this with the correct reset type mixin. private class SynchronizerPrimitiveShiftReg( sync: Int, init: Boolean, resetType: SynchronizerResetType.Value) extends AbstractPipelineReg(1) { val initInt = if (init) 1 else 0 val initPostfix = resetType match { case SynchronizerResetType.NonSync => "" case _ => s"_i${initInt}" } override def desiredName = s"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}" val chain = List.tabulate(sync) { i => val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B) reg.suggestName(s"sync_$i") } chain.last := io.d.asBool (chain.init zip chain.tail).foreach { case (sink, source) => sink := source } io.q := chain.head.asUInt } private object SynchronizerPrimitiveShiftReg { def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = { val gen: () => SynchronizerPrimitiveShiftReg = resetType match { case SynchronizerResetType.NonSync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) case SynchronizerResetType.Async => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset case SynchronizerResetType.Sync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset case SynchronizerResetType.Inferred => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) } AbstractPipelineReg(gen(), in) } } // Note: This module may end up with a non-AsyncReset type reset. // But the Primitives within will always have AsyncReset type. class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asAsyncReset){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async) } } io.q := Cat(output.reverse) } object AsyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } // Note: This module may end up with a non-Bool type reset. // But the Primitives within will always have Bool reset type. @deprecated("SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.", "rocket-chip 1.2") class SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asBool){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync) } } io.q := Cat(output.reverse) } object SyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred) } io.q := Cat(output.reverse) } object ResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}" val output = Seq.tabulate(w) { i => SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync) } io.q := Cat(output.reverse) } object SynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, None) def apply [T <: Data](in: T): T = apply (in, 3, None) } class ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module { override def desiredName = s"ClockCrossingReg_w${w}" val io = IO(new Bundle{ val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) val en = Input(Bool()) }) val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en) io.q := cdc_reg } object ClockCrossingReg { def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = { val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit)) name.foreach{ cdc_reg.suggestName(_) } cdc_reg.io.d := in.asUInt cdc_reg.io.en := en cdc_reg.io.q.asTypeOf(in) } }	module ClockCrossingReg_w17( // @[SynchronizerReg.scala:191:7] input clock, // @[SynchronizerReg.scala:191:7] input reset, // @[SynchronizerReg.scala:191:7] input [16:0] io_d, // @[SynchronizerReg.scala:195:14] output [16:0] io_q, // @[SynchronizerReg.scala:195:14] input io_en // @[SynchronizerReg.scala:195:14] ); wire [16:0] io_d_0 = io_d; // @[SynchronizerReg.scala:191:7] wire io_en_0 = io_en; // @[SynchronizerReg.scala:191:7] wire [16:0] io_q_0; // @[SynchronizerReg.scala:191:7] reg [16:0] cdc_reg; // @[SynchronizerReg.scala:201:76] assign io_q_0 = cdc_reg; // @[SynchronizerReg.scala:191:7, :201:76] always @(posedge clock) begin // @[SynchronizerReg.scala:191:7] if (io_en_0) // @[SynchronizerReg.scala:191:7] cdc_reg <= io_d_0; // @[SynchronizerReg.scala:191:7, :201:76] always @(posedge) assign io_q = io_q_0; // @[SynchronizerReg.scala:191:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File EgressUnit.scala: package constellation.router import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.{Field, Parameters} import freechips.rocketchip.util._ import constellation.channel._ import constellation.routing.{FlowRoutingBundle} class EgressUnit(coupleSAVA: Boolean, combineSAST: Boolean, inParams: Seq[ChannelParams], ingressParams: Seq[IngressChannelParams], cParam: EgressChannelParams) (implicit p: Parameters) extends AbstractOutputUnit(inParams, ingressParams, cParam)(p) { class EgressUnitIO extends AbstractOutputUnitIO(inParams, ingressParams, cParam) { val out = Decoupled(new EgressFlit(cParam.payloadBits)) } val io = IO(new EgressUnitIO) val channel_empty = RegInit(true.B) val flow = Reg(new FlowRoutingBundle) val q = Module(new Queue(new EgressFlit(cParam.payloadBits), 3 - (if (combineSAST) 1 else 0), flow=true)) q.io.enq.valid := io.in(0).valid q.io.enq.bits.head := io.in(0).bits.head q.io.enq.bits.tail := io.in(0).bits.tail val flows = cParam.possibleFlows.toSeq if (flows.size == 0) { q.io.enq.bits.ingress_id := 0.U(1.W) } else { q.io.enq.bits.ingress_id := Mux1H( flows.map(f => (f.ingressNode.U === io.in(0).bits.flow.ingress_node && f.ingressNodeId.U === io.in(0).bits.flow.ingress_node_id)), flows.map(f => f.ingressId.U(ingressIdBits.W)) ) } q.io.enq.bits.payload := io.in(0).bits.payload io.out <> q.io.deq assert(!(q.io.enq.valid && !q.io.enq.ready)) io.credit_available(0) := q.io.count === 0.U io.channel_status(0).occupied := !channel_empty io.channel_status(0).flow := flow when (io.credit_alloc(0).alloc && io.credit_alloc(0).tail) { channel_empty := true.B if (coupleSAVA) io.channel_status(0).occupied := false.B } when (io.allocs(0).alloc) { channel_empty := false.B flow := io.allocs(0).flow } }	module EgressUnit_3( // @[EgressUnit.scala:12:7] input clock, // @[EgressUnit.scala:12:7] input reset, // @[EgressUnit.scala:12:7] input io_in_0_valid, // @[EgressUnit.scala:18:14] input io_in_0_bits_head, // @[EgressUnit.scala:18:14] input io_in_0_bits_tail, // @[EgressUnit.scala:18:14] input [72:0] io_in_0_bits_payload, // @[EgressUnit.scala:18:14] input [3:0] io_in_0_bits_flow_ingress_node, // @[EgressUnit.scala:18:14] input [1:0] io_in_0_bits_flow_ingress_node_id, // @[EgressUnit.scala:18:14] output io_credit_available_0, // @[EgressUnit.scala:18:14] output io_channel_status_0_occupied, // @[EgressUnit.scala:18:14] input io_allocs_0_alloc, // @[EgressUnit.scala:18:14] input io_credit_alloc_0_alloc, // @[EgressUnit.scala:18:14] input io_credit_alloc_0_tail, // @[EgressUnit.scala:18:14] input io_out_ready, // @[EgressUnit.scala:18:14] output io_out_valid, // @[EgressUnit.scala:18:14] output io_out_bits_head, // @[EgressUnit.scala:18:14] output io_out_bits_tail, // @[EgressUnit.scala:18:14] output [72:0] io_out_bits_payload // @[EgressUnit.scala:18:14] ); wire _q_io_enq_ready; // @[EgressUnit.scala:22:17] wire [1:0] _q_io_count; // @[EgressUnit.scala:22:17] reg channel_empty; // @[EgressUnit.scala:20:30] wire _q_io_enq_bits_ingress_id_T_10 = io_in_0_bits_flow_ingress_node_id == 2'h0; // @[EgressUnit.scala:32:27]
Generate the Verilog code corresponding to the following Chisel files. File Monitor.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceLine import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import freechips.rocketchip.diplomacy.EnableMonitors import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode} import freechips.rocketchip.util.PlusArg case class TLMonitorArgs(edge: TLEdge) abstract class TLMonitorBase(args: TLMonitorArgs) extends Module { val io = IO(new Bundle { val in = Input(new TLBundle(args.edge.bundle)) }) def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit legalize(io.in, args.edge, reset) } object TLMonitor { def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = { if (enable) { EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) } } else { node } } } class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args) { require (args.edge.params(TLMonitorStrictMode) \|\| (! args.edge.params(TestplanTestType).formal)) val cover_prop_class = PropertyClass.Default //Like assert but can flip to being an assumption for formal verification def monAssert(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir, cond, message, PropertyClass.Default) } def assume(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir.flip, cond, message, PropertyClass.Default) } def extra = { args.edge.sourceInfo match { case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)" case _ => "" } } def visible(address: UInt, source: UInt, edge: TLEdge) = edge.client.clients.map { c => !c.sourceId.contains(source) \|\| c.visibility.map(_.contains(address)).reduce(_ \|\| _) }.reduce(_ && _) def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = { //switch this flag to turn on diplomacy in error messages def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n" monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra) // Reuse these subexpressions to save some firrtl lines val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility") //The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B //TODO: check for acquireT? when (bundle.opcode === TLMessages.AcquireBlock) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra) } when (bundle.opcode === TLMessages.AcquirePerm) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra) monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra) monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra) monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra) } } def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = { monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra) monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility") // Reuse these subexpressions to save some firrtl lines val address_ok = edge.manager.containsSafe(edge.address(bundle)) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source when (bundle.opcode === TLMessages.Probe) { assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra) assume (address_ok, "'B' channel Probe carries unmanaged address" + extra) assume (legal_source, "'B' channel Probe carries source that is not first source" + extra) assume (is_aligned, "'B' channel Probe address not aligned to size" + extra) assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra) assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra) assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra) monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra) monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra) monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra) monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra) } } def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = { monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val address_ok = edge.manager.containsSafe(edge.address(bundle)) monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility") when (bundle.opcode === TLMessages.ProbeAck) { monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra) } when (bundle.opcode === TLMessages.ProbeAckData) { monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.Release) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra) monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra) } when (bundle.opcode === TLMessages.ReleaseData) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.AccessAck) { monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra) } when (bundle.opcode === TLMessages.HintAck) { monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra) } } def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = { assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val sink_ok = bundle.sink < edge.manager.endSinkId.U val deny_put_ok = edge.manager.mayDenyPut.B val deny_get_ok = edge.manager.mayDenyGet.B when (bundle.opcode === TLMessages.ReleaseAck) { assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra) assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra) assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra) } when (bundle.opcode === TLMessages.Grant) { assume (source_ok, "'D' channel Grant carries invalid source ID" + extra) assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra) assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel Grant is denied" + extra) } when (bundle.opcode === TLMessages.GrantData) { assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra) assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra) assume (!bundle.denied \|\| bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra) assume (deny_get_ok \|\| !bundle.denied, "'D' channel GrantData is denied" + extra) } when (bundle.opcode === TLMessages.AccessAck) { assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel AccessAck is denied" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra) assume (!bundle.denied \|\| bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra) assume (deny_get_ok \|\| !bundle.denied, "'D' channel AccessAckData is denied" + extra) } when (bundle.opcode === TLMessages.HintAck) { assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel HintAck is denied" + extra) } } def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = { val sink_ok = bundle.sink < edge.manager.endSinkId.U monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra) } def legalizeFormat(bundle: TLBundle, edge: TLEdge) = { when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) } when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) } when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) } when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) } } else { monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra) monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra) monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra) } } def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = { val a_first = edge.first(a.bits, a.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (a.valid && !a_first) { monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra) monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra) monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra) monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra) monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra) } when (a.fire && a_first) { opcode := a.bits.opcode param := a.bits.param size := a.bits.size source := a.bits.source address := a.bits.address } } def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = { val b_first = edge.first(b.bits, b.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (b.valid && !b_first) { monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra) monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra) monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra) monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra) monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra) } when (b.fire && b_first) { opcode := b.bits.opcode param := b.bits.param size := b.bits.size source := b.bits.source address := b.bits.address } } def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = { // Symbolic variable val sym_source = Wire(UInt(edge.client.endSourceId.W)) // TODO: Connect sym_source to a fixed value for simulation and to a // free wire in formal sym_source := 0.U // Type casting Int to UInt val maxSourceId = Wire(UInt(edge.client.endSourceId.W)) maxSourceId := edge.client.endSourceId.U // Delayed verison of sym_source val sym_source_d = Reg(UInt(edge.client.endSourceId.W)) sym_source_d := sym_source // These will be constraints for FV setup Property( MonitorDirection.Monitor, (sym_source === sym_source_d), "sym_source should remain stable", PropertyClass.Default) Property( MonitorDirection.Monitor, (sym_source <= maxSourceId), "sym_source should take legal value", PropertyClass.Default) val my_resp_pend = RegInit(false.B) val my_opcode = Reg(UInt()) val my_size = Reg(UInt()) val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire) val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire) val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source) val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source) val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat) val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend) when (my_set_resp_pend) { my_resp_pend := true.B } .elsewhen (my_clr_resp_pend) { my_resp_pend := false.B } when (my_a_first_beat) { my_opcode := bundle.a.bits.opcode my_size := bundle.a.bits.size } val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size) val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode) val my_resp_opcode_legal = Wire(Bool()) when ((my_resp_opcode === TLMessages.Get) \|\| (my_resp_opcode === TLMessages.ArithmeticData) \|\| (my_resp_opcode === TLMessages.LogicalData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData) } .elsewhen ((my_resp_opcode === TLMessages.PutFullData) \|\| (my_resp_opcode === TLMessages.PutPartialData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck) } .otherwise { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck) } monAssert (IfThen(my_resp_pend, !my_a_first_beat), "Request message should not be sent with a source ID, for which a response message" + "is already pending (not received until current cycle) for a prior request message" + "with the same source ID" + extra) assume (IfThen(my_clr_resp_pend, (my_set_resp_pend \|\| my_resp_pend)), "Response message should be accepted with a source ID only if a request message with the" + "same source ID has been accepted or is being accepted in the current cycle" + extra) assume (IfThen(my_d_first_beat, (my_a_first_beat \|\| my_resp_pend)), "Response message should be sent with a source ID only if a request message with the" + "same source ID has been accepted or is being sent in the current cycle" + extra) assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)), "If d_valid is 1, then d_size should be same as a_size of the corresponding request" + "message" + extra) assume (IfThen(my_d_first_beat, my_resp_opcode_legal), "If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" + "request message" + extra) } def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = { val c_first = edge.first(c.bits, c.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (c.valid && !c_first) { monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra) monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra) monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra) monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra) monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra) } when (c.fire && c_first) { opcode := c.bits.opcode param := c.bits.param size := c.bits.size source := c.bits.source address := c.bits.address } } def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = { val d_first = edge.first(d.bits, d.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val sink = Reg(UInt()) val denied = Reg(Bool()) when (d.valid && !d_first) { assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra) assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra) assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra) assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra) assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra) assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra) } when (d.fire && d_first) { opcode := d.bits.opcode param := d.bits.param size := d.bits.size source := d.bits.source sink := d.bits.sink denied := d.bits.denied } } def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = { legalizeMultibeatA(bundle.a, edge) legalizeMultibeatD(bundle.d, edge) if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { legalizeMultibeatB(bundle.b, edge) legalizeMultibeatC(bundle.c, edge) } } //This is left in for almond which doesn't adhere to the tilelink protocol @deprecated("Use legalizeADSource instead if possible","") def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.client.endSourceId.W)) val a_first = edge.first(bundle.a.bits, bundle.a.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val a_set = WireInit(0.U(edge.client.endSourceId.W)) when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) assume((a_set \| inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra) } if (edge.manager.minLatency > 0) { assume(a_set =/= d_clr \|\| !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight \| a_set) & ~d_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") assert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = { val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size) val log_a_size_bus_size = log2Ceil(a_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error inflight.suggestName("inflight") val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) inflight_opcodes.suggestName("inflight_opcodes") val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) inflight_sizes.suggestName("inflight_sizes") val a_first = edge.first(bundle.a.bits, bundle.a.fire) a_first.suggestName("a_first") val d_first = edge.first(bundle.d.bits, bundle.d.fire) d_first.suggestName("d_first") val a_set = WireInit(0.U(edge.client.endSourceId.W)) val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) a_set.suggestName("a_set") a_set_wo_ready.suggestName("a_set_wo_ready") val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) a_opcodes_set.suggestName("a_opcodes_set") val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) a_sizes_set.suggestName("a_sizes_set") val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W)) a_opcode_lookup.suggestName("a_opcode_lookup") a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W)) a_size_lookup.suggestName("a_size_lookup") a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant)) val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant)) val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W)) a_opcodes_set_interm.suggestName("a_opcodes_set_interm") val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W)) a_sizes_set_interm.suggestName("a_sizes_set_interm") when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) { a_set_wo_ready := UIntToOH(bundle.a.bits.source) } when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) \| 1.U a_sizes_set_interm := (bundle.a.bits.size << 1.U) \| 1.U a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U) a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U) monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) d_opcodes_clr.suggestName("d_opcodes_clr") val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) \|\| same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) \|\| (bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra) assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) \|\| (bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra) assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) { assume((!bundle.d.ready) \|\| bundle.a.ready, "ready check") } if (edge.manager.minLatency > 0) { assume(a_set_wo_ready =/= d_clr_wo_ready \|\| !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight \| a_set) & ~d_clr inflight_opcodes := (inflight_opcodes \| a_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes \| a_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = { val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size) val log_c_size_bus_size = log2Ceil(c_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) inflight.suggestName("inflight") inflight_opcodes.suggestName("inflight_opcodes") inflight_sizes.suggestName("inflight_sizes") val c_first = edge.first(bundle.c.bits, bundle.c.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) c_first.suggestName("c_first") d_first.suggestName("d_first") val c_set = WireInit(0.U(edge.client.endSourceId.W)) val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) c_set.suggestName("c_set") c_set_wo_ready.suggestName("c_set_wo_ready") c_opcodes_set.suggestName("c_opcodes_set") c_sizes_set.suggestName("c_sizes_set") val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W)) val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W)) c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U c_opcode_lookup.suggestName("c_opcode_lookup") c_size_lookup.suggestName("c_size_lookup") val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W)) val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W)) c_opcodes_set_interm.suggestName("c_opcodes_set_interm") c_sizes_set_interm.suggestName("c_sizes_set_interm") when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) { c_set_wo_ready := UIntToOH(bundle.c.bits.source) } when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) { c_set := UIntToOH(bundle.c.bits.source) c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) \| 1.U c_sizes_set_interm := (bundle.c.bits.size << 1.U) \| 1.U c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U) c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U) monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra) } val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck \|\| bundle.c.bits.opcode === TLMessages.ProbeAckData val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") d_opcodes_clr.suggestName("d_opcodes_clr") d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) \|\| same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) { assume((!bundle.d.ready) \|\| bundle.c.ready, "ready check") } if (edge.manager.minLatency > 0) { when (c_set_wo_ready.orR) { assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra) } } inflight := (inflight \| c_set) & ~d_clr inflight_opcodes := (inflight_opcodes \| c_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes \| c_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.c.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.manager.endSinkId.W)) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val e_first = true.B val d_set = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) { d_set := UIntToOH(bundle.d.bits.sink) assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra) } val e_clr = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) { e_clr := UIntToOH(bundle.e.bits.sink) monAssert((d_set \| inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra) } // edge.client.minLatency applies to BC, not DE inflight := (inflight \| d_set) & ~e_clr } def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = { val sourceBits = log2Ceil(edge.client.endSourceId) val tooBig = 14 // >16kB worth of flight information gets to be too much if (sourceBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked") } else { if (args.edge.params(TestplanTestType).simulation) { if (args.edge.params(TLMonitorStrictMode)) { legalizeADSource(bundle, edge) legalizeCDSource(bundle, edge) } else { legalizeADSourceOld(bundle, edge) } } if (args.edge.params(TestplanTestType).formal) { legalizeADSourceFormal(bundle, edge) } } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { // legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize... val sinkBits = log2Ceil(edge.manager.endSinkId) if (sinkBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked") } else { legalizeDESink(bundle, edge) } } } def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = { legalizeFormat (bundle, edge) legalizeMultibeat (bundle, edge) legalizeUnique (bundle, edge) } } File Misc.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import scala.math._ class ParameterizedBundle(implicit p: Parameters) extends Bundle trait Clocked extends Bundle { val clock = Clock() val reset = Bool() } object DecoupledHelper { def apply(rvs: Bool) = new DecoupledHelper(rvs) } class DecoupledHelper(val rvs: Seq[Bool]) { def fire(exclude: Bool, includes: Bool) = { require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!") (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _) } def fire() = { rvs.reduce(_ && _) } } object MuxT { def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2)) def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3)) def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4)) } /** Creates a cascade of n MuxTs to search for a key value. / object MuxTLookup { def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } } object ValidMux { def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]): ValidIO[T] = { apply(v1 +: v2.toSeq) } def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = { val out = Wire(Valid(valids.head.bits.cloneType)) out.valid := valids.map(_.valid).reduce(_ \|\| _) out.bits := MuxCase(valids.head.bits, valids.map(v => (v.valid -> v.bits))) out } } object Str { def apply(s: String): UInt = { var i = BigInt(0) require(s.forall(validChar _)) for (c <- s) i = (i << 8) \| c i.U((s.length8).W) } def apply(x: Char): UInt = { require(validChar(x)) x.U(8.W) } def apply(x: UInt): UInt = apply(x, 10) def apply(x: UInt, radix: Int): UInt = { val rad = radix.U val w = x.getWidth require(w > 0) var q = x var s = digit(q % rad) for (i <- 1 until ceil(log(2)/log(radix)w).toInt) { q = q / rad s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s) } s } def apply(x: SInt): UInt = apply(x, 10) def apply(x: SInt, radix: Int): UInt = { val neg = x < 0.S val abs = x.abs.asUInt if (radix != 10) { Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix)) } else { val rad = radix.U val w = abs.getWidth require(w > 0) var q = abs var s = digit(q % rad) var needSign = neg for (i <- 1 until ceil(log(2)/log(radix)w).toInt) { q = q / rad val placeSpace = q === 0.U val space = Mux(needSign, Str('-'), Str(' ')) needSign = needSign && !placeSpace s = Cat(Mux(placeSpace, space, digit(q % rad)), s) } Cat(Mux(needSign, Str('-'), Str(' ')), s) } } private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0) private def validChar(x: Char) = x == (x & 0xFF) } object Split { def apply(x: UInt, n0: Int) = { val w = x.getWidth (x.extract(w-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n2: Int, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } } object Random { def apply(mod: Int, random: UInt): UInt = { if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0) else PriorityEncoder(partition(apply(1 << log2Up(mod8), random), mod)) } def apply(mod: Int): UInt = apply(mod, randomizer) def oneHot(mod: Int, random: UInt): UInt = { if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0)) else PriorityEncoderOH(partition(apply(1 << log2Up(mod8), random), mod)).asUInt } def oneHot(mod: Int): UInt = oneHot(mod, randomizer) private def randomizer = LFSR(16) private def partition(value: UInt, slices: Int) = Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U) } object Majority { def apply(in: Set[Bool]): Bool = { val n = (in.size >> 1) + 1 val clauses = in.subsets(n).map(_.reduce(_ && _)) clauses.reduce(_ \|\| _) } def apply(in: Seq[Bool]): Bool = apply(in.toSet) def apply(in: UInt): Bool = apply(in.asBools.toSet) } object PopCountAtLeast { private def two(x: UInt): (Bool, Bool) = x.getWidth match { case 1 => (x.asBool, false.B) case n => val half = x.getWidth / 2 val (leftOne, leftTwo) = two(x(half - 1, 0)) val (rightOne, rightTwo) = two(x(x.getWidth - 1, half)) (leftOne \|\| rightOne, leftTwo \|\| rightTwo \|\| (leftOne && rightOne)) } def apply(x: UInt, n: Int): Bool = n match { case 0 => true.B case 1 => x.orR case 2 => two(x)._2 case 3 => PopCount(x) >= n.U } } // This gets used everywhere, so make the smallest circuit possible ... // Given an address and size, create a mask of beatBytes size // eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111 // groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01 object MaskGen { def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = { require (groupBy >= 1 && beatBytes >= groupBy) require (isPow2(beatBytes) && isPow2(groupBy)) val lgBytes = log2Ceil(beatBytes) val sizeOH = UIntToOH(lgSize \| 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) \| (groupBy2 - 1).U def helper(i: Int): Seq[(Bool, Bool)] = { if (i == 0) { Seq((lgSize >= lgBytes.asUInt, true.B)) } else { val sub = helper(i-1) val size = sizeOH(lgBytes - i) val bit = addr_lo(lgBytes - i) val nbit = !bit Seq.tabulate (1 << i) { j => val (sub_acc, sub_eq) = sub(j/2) val eq = sub_eq && (if (j % 2 == 1) bit else nbit) val acc = sub_acc \|\| (size && eq) (acc, eq) } } } if (groupBy == beatBytes) 1.U else Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse) } } File PlusArg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.experimental._ import chisel3.util.HasBlackBoxResource @deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05") case class PlusArgInfo(default: BigInt, docstring: String) /** Case class for PlusArg information * * @tparam A scala type of the PlusArg value * @param default optional default value * @param docstring text to include in the help * @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT) / private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String) /* Typeclass for converting a type to a doctype string * @tparam A some type / trait Doctypeable[A] { /* Return the doctype string for some option / def toDoctype(a: Option[A]): String } /* Object containing implementations of the Doctypeable typeclass / object Doctypes { /* Converts an Int => "INT" / implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" } /* Converts a BigInt => "INT" / implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" } /* Converts a String => "STRING" / implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" } } class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map( "FORMAT" -> StringParam(format), "DEFAULT" -> IntParam(default), "WIDTH" -> IntParam(width) )) with HasBlackBoxResource { val io = IO(new Bundle { val out = Output(UInt(width.W)) }) addResource("/vsrc/plusarg_reader.v") } / This wrapper class has no outputs, making it clear it is a simulation-only construct / class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module { val io = IO(new Bundle { val count = Input(UInt(width.W)) }) val max = Module(new plusarg_reader(format, default, docstring, width)).io.out when (max > 0.U) { assert (io.count < max, s"Timeout exceeded: $docstring") } } import Doctypes._ object PlusArg { /* PlusArg("foo") will return 42.U if the simulation is run with +foo=42 * Do not use this as an initial register value. The value is set in an * initial block and thus accessing it from another initial is racey. * Add a docstring to document the arg, which can be dumped in an elaboration * pass. / def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out } /* PlusArg.timeout(name, default, docstring)(count) will use chisel.assert * to kill the simulation when count exceeds the specified integer argument. * Default 0 will never assert. / def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count } } object PlusArgArtefacts { private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty / Add a new PlusArg / @deprecated( "Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05" ) def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring) /* Add a new PlusArg * * @tparam A scala type of the PlusArg value * @param name name for the PlusArg * @param default optional default value * @param docstring text to include in the help / def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit = artefacts = artefacts ++ Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default))) / From plus args, generate help text / private def serializeHelp_cHeader(tab: String = ""): String = artefacts .map{ case(arg, info) => s"""\|$tab+$arg=${info.doctype}\\n\\ \|$tab${" "20}${info.docstring}\\n\\ \|""".stripMargin ++ info.default.map{ case default => s"$tab${" "22}(default=${default})\\n\\\n"}.getOrElse("") }.toSeq.mkString("\\n\\\n") ++ "\"" / From plus args, generate a char array of their names / private def serializeArray_cHeader(tab: String = ""): String = { val prettyTab = tab + " " 44 // Length of 'static const ...' s"${tab}static const char * verilog_plusargs [] = {\\\n" ++ artefacts .map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" } .mkString("")++ s"${prettyTab}0};" } /* Generate C code to be included in emulator.cc that helps with * argument parsing based on available Verilog PlusArgs / def serialize_cHeader(): String = s"""\|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\ \|${serializeHelp_cHeader(" "7)} \|${serializeArray_cHeader()} \|""".stripMargin } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /* Like Vec.apply(idx), but tolerates indices of mismatched width / def extract(idx: UInt): T = x((idx \| 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx \| 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def \| (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a \|\| b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_\|\|_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /* Any Data subtype that has a Bool member named valid. / type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /* converts from camel case to to underscores, also removing all spaces / def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /* converts spaces or underscores to hyphens, also lowering case / def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y \| (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y \|\| y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 \| 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /* Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation / def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.diplomacy import chisel3._ import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor} import freechips.rocketchip.util.ShiftQueue /* Options for describing the attributes of memory regions / object RegionType { // Define the 'more relaxed than' ordering val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS) sealed trait T extends Ordered[T] { def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this) } case object CACHED extends T // an intermediate agent may have cached a copy of the region for you case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively } // A non-empty half-open range; [start, end) case class IdRange(start: Int, end: Int) extends Ordered[IdRange] { require (start >= 0, s"Ids cannot be negative, but got: $start.") require (start <= end, "Id ranges cannot be negative.") def compare(x: IdRange) = { val primary = (this.start - x.start).signum val secondary = (x.end - this.end).signum if (primary != 0) primary else secondary } def overlaps(x: IdRange) = start < x.end && x.start < end def contains(x: IdRange) = start <= x.start && x.end <= end def contains(x: Int) = start <= x && x < end def contains(x: UInt) = if (size == 0) { false.B } else if (size == 1) { // simple comparison x === start.U } else { // find index of largest different bit val largestDeltaBit = log2Floor(start ^ (end-1)) val smallestCommonBit = largestDeltaBit + 1 // may not exist in x val uncommonMask = (1 << smallestCommonBit) - 1 val uncommonBits = (x \| 0.U(smallestCommonBit.W))(largestDeltaBit, 0) // the prefix must match exactly (note: may shift ALL bits away) (x >> smallestCommonBit) === (start >> smallestCommonBit).U && // firrtl constant prop range analysis can eliminate these two: (start & uncommonMask).U <= uncommonBits && uncommonBits <= ((end-1) & uncommonMask).U } def shift(x: Int) = IdRange(start+x, end+x) def size = end - start def isEmpty = end == start def range = start until end } object IdRange { def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else { val ranges = s.sorted (ranges.tail zip ranges.init) find { case (a, b) => a overlaps b } } } // An potentially empty inclusive range of 2-powers [min, max] (in bytes) case class TransferSizes(min: Int, max: Int) { def this(x: Int) = this(x, x) require (min <= max, s"Min transfer $min > max transfer $max") require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)") require (max == 0 \|\| isPow2(max), s"TransferSizes must be a power of 2, got: $max") require (min == 0 \|\| isPow2(min), s"TransferSizes must be a power of 2, got: $min") require (max == 0 \|\| min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)") def none = min == 0 def contains(x: Int) = isPow2(x) && min <= x && x <= max def containsLg(x: Int) = contains(1 << x) def containsLg(x: UInt) = if (none) false.B else if (min == max) { log2Ceil(min).U === x } else { log2Ceil(min).U <= x && x <= log2Ceil(max).U } def contains(x: TransferSizes) = x.none \|\| (min <= x.min && x.max <= max) def intersect(x: TransferSizes) = if (x.max < min \|\| max < x.min) TransferSizes.none else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max)) // Not a union, because the result may contain sizes contained by neither term // NOT TO BE CONFUSED WITH COVERPOINTS def mincover(x: TransferSizes) = { if (none) { x } else if (x.none) { this } else { TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max)) } } override def toString() = "TransferSizes[%d, %d]".format(min, max) } object TransferSizes { def apply(x: Int) = new TransferSizes(x) val none = new TransferSizes(0) def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _) def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _) implicit def asBool(x: TransferSizes) = !x.none } // AddressSets specify the address space managed by the manager // Base is the base address, and mask are the bits consumed by the manager // e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff // e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ... case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet] { // Forbid misaligned base address (and empty sets) require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}") require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous // We do allow negative mask (=> ignore all high bits) def contains(x: BigInt) = ((x ^ base) & ~mask) == 0 def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S // turn x into an address contained in this set def legalize(x: UInt): UInt = base.U \| (mask.U & x) // overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1) def overlaps(x: AddressSet) = (~(mask \| x.mask) & (base ^ x.base)) == 0 // contains iff bitwise: x.mask => mask && contains(x.base) def contains(x: AddressSet) = ((x.mask \| (base ^ x.base)) & ~mask) == 0 // The number of bytes to which the manager must be aligned def alignment = ((mask + 1) & ~mask) // Is this a contiguous memory range def contiguous = alignment == mask+1 def finite = mask >= 0 def max = { require (finite, "Max cannot be calculated on infinite mask"); base \| mask } // Widen the match function to ignore all bits in imask def widen(imask: BigInt) = AddressSet(base & ~imask, mask \| imask) // Return an AddressSet that only contains the addresses both sets contain def intersect(x: AddressSet): Option[AddressSet] = { if (!overlaps(x)) { None } else { val r_mask = mask & x.mask val r_base = base \| x.base Some(AddressSet(r_base, r_mask)) } } def subtract(x: AddressSet): Seq[AddressSet] = { intersect(x) match { case None => Seq(this) case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit => val nmask = (mask & (bit-1)) \| remove.mask val nbase = (remove.base ^ bit) & ~nmask AddressSet(nbase, nmask) } } } // AddressSets have one natural Ordering (the containment order, if contiguous) def compare(x: AddressSet) = { val primary = (this.base - x.base).signum // smallest address first val secondary = (x.mask - this.mask).signum // largest mask first if (primary != 0) primary else secondary } // We always want to see things in hex override def toString() = { if (mask >= 0) { "AddressSet(0x%x, 0x%x)".format(base, mask) } else { "AddressSet(0x%x, ~0x%x)".format(base, ~mask) } } def toRanges = { require (finite, "Ranges cannot be calculated on infinite mask") val size = alignment val fragments = mask & ~(size-1) val bits = bitIndexes(fragments) (BigInt(0) until (BigInt(1) << bits.size)).map { i => val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) } AddressRange(off, size) } } } object AddressSet { val everything = AddressSet(0, -1) def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = { if (size == 0) tail.reverse else { val maxBaseAlignment = base & (-base) // 0 for infinite (LSB) val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size val step = if (maxBaseAlignment == 0 \|\| maxBaseAlignment > maxSizeAlignment) maxSizeAlignment else maxBaseAlignment misaligned(base+step, size-step, AddressSet(base, step-1) +: tail) } } def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = { // Pair terms up by ignoring 'bit' seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) => if (seq.size == 1) { seq.head // singleton -> unaffected } else { key.copy(mask = key.mask \| bit) // pair - widen mask by bit } }.toList } def unify(seq: Seq[AddressSet]): Seq[AddressSet] = { val bits = seq.map(_.base).foldLeft(BigInt(0))(_ \| _) AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted } def enumerateMask(mask: BigInt): Seq[BigInt] = { def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] = if (id == mask) (id +: tail).reverse else helper(((~mask \| id) + 1) & mask, id +: tail) helper(0, Nil) } def enumerateBits(mask: BigInt): Seq[BigInt] = { def helper(x: BigInt): Seq[BigInt] = { if (x == 0) { Nil } else { val bit = x & (-x) bit +: helper(x & ~bit) } } helper(mask) } } case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean) { require (depth >= 0, "Buffer depth must be >= 0") def isDefined = depth > 0 def latency = if (isDefined && !flow) 1 else 0 def apply[T <: Data](x: DecoupledIO[T]) = if (isDefined) Queue(x, depth, flow=flow, pipe=pipe) else x def irrevocable[T <: Data](x: ReadyValidIO[T]) = if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe) else x def sq[T <: Data](x: DecoupledIO[T]) = if (!isDefined) x else { val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe)) sq.io.enq <> x sq.io.deq } override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "") } object BufferParams { implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false) val default = BufferParams(2) val none = BufferParams(0) val flow = BufferParams(1, true, false) val pipe = BufferParams(1, false, true) } case class TriStateValue(value: Boolean, set: Boolean) { def update(orig: Boolean) = if (set) value else orig } object TriStateValue { implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true) def unset = TriStateValue(false, false) } trait DirectedBuffers[T] { def copyIn(x: BufferParams): T def copyOut(x: BufferParams): T def copyInOut(x: BufferParams): T } trait IdMapEntry { def name: String def from: IdRange def to: IdRange def isCache: Boolean def requestFifo: Boolean def maxTransactionsInFlight: Option[Int] def pretty(fmt: String) = if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5 fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } else { fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } } abstract class IdMap[T <: IdMapEntry] { protected val fmt: String val mapping: Seq[T] def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n") } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportPutFull \|\| manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB \|\| manager.anySupportGet \|\| manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportPutFull \|\| client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe \|\| client.anySupportGet \|\| client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet \|\| client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull \|\| client.anySupportPutPartial \|\| client.anySupportHint \|\| client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet \|\| manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull \|\| manager.anySupportPutPartial \|\| manager.anySupportHint \|\| manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) \|\| !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.ProbeAckData \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode \| small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U \|\| beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }	module TLMonitor_9( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [1:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [10:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [12:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [10:0] io_in_d_bits_source // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire a_first_done = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala:51:35] reg a_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [1:0] size; // @[Monitor.scala:389:22] reg [10:0] source; // @[Monitor.scala:390:22] reg [12:0] address; // @[Monitor.scala:391:22] reg d_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] size_1; // @[Monitor.scala:540:22] reg [10:0] source_1; // @[Monitor.scala:541:22] reg [1039:0] inflight; // @[Monitor.scala:614:27] reg [4159:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [4159:0] inflight_sizes; // @[Monitor.scala:618:33] reg a_first_counter_1; // @[Edges.scala:229:27] reg d_first_counter_1; // @[Edges.scala:229:27] wire _GEN = a_first_done & ~a_first_counter_1; // @[Decoupled.scala:51:35] wire d_release_ack = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala:673:46] wire _GEN_0 = io_in_d_bits_opcode != 3'h6; // @[Monitor.scala:673:46, :674:74] reg [31:0] watchdog; // @[Monitor.scala:709:27] reg [1039:0] inflight_1; // @[Monitor.scala:726:35] reg [4159:0] inflight_sizes_1; // @[Monitor.scala:728:35] reg d_first_counter_2; // @[Edges.scala:229:27] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to the following Chisel files. File InputUnit.scala: package constellation.router import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.{Field, Parameters} import freechips.rocketchip.util._ import constellation.channel._ import constellation.routing.{FlowRoutingBundle} import constellation.noc.{HasNoCParams} class AbstractInputUnitIO( val cParam: BaseChannelParams, val outParams: Seq[ChannelParams], val egressParams: Seq[EgressChannelParams], )(implicit val p: Parameters) extends Bundle with HasRouterOutputParams { val nodeId = cParam.destId val router_req = Decoupled(new RouteComputerReq) val router_resp = Input(new RouteComputerResp(outParams, egressParams)) val vcalloc_req = Decoupled(new VCAllocReq(cParam, outParams, egressParams)) val vcalloc_resp = Input(new VCAllocResp(outParams, egressParams)) val out_credit_available = Input(MixedVec(allOutParams.map { u => Vec(u.nVirtualChannels, Bool()) })) val salloc_req = Vec(cParam.destSpeedup, Decoupled(new SwitchAllocReq(outParams, egressParams))) val out = Vec(cParam.destSpeedup, Valid(new SwitchBundle(outParams, egressParams))) val debug = Output(new Bundle { val va_stall = UInt(log2Ceil(cParam.nVirtualChannels).W) val sa_stall = UInt(log2Ceil(cParam.nVirtualChannels).W) }) val block = Input(Bool()) } abstract class AbstractInputUnit( val cParam: BaseChannelParams, val outParams: Seq[ChannelParams], val egressParams: Seq[EgressChannelParams] )(implicit val p: Parameters) extends Module with HasRouterOutputParams with HasNoCParams { val nodeId = cParam.destId def io: AbstractInputUnitIO } class InputBuffer(cParam: ChannelParams)(implicit p: Parameters) extends Module { val nVirtualChannels = cParam.nVirtualChannels val io = IO(new Bundle { val enq = Flipped(Vec(cParam.srcSpeedup, Valid(new Flit(cParam.payloadBits)))) val deq = Vec(cParam.nVirtualChannels, Decoupled(new BaseFlit(cParam.payloadBits))) }) val useOutputQueues = cParam.useOutputQueues val delims = if (useOutputQueues) { cParam.virtualChannelParams.map(u => if (u.traversable) u.bufferSize else 0).scanLeft(0)(_+_) } else { // If no queuing, have to add an additional slot since head == tail implies empty // TODO this should be fixed, should use all slots available cParam.virtualChannelParams.map(u => if (u.traversable) u.bufferSize + 1 else 0).scanLeft(0)(_+_) } val starts = delims.dropRight(1).zipWithIndex.map { case (s,i) => if (cParam.virtualChannelParams(i).traversable) s else 0 } val ends = delims.tail.zipWithIndex.map { case (s,i) => if (cParam.virtualChannelParams(i).traversable) s else 0 } val fullSize = delims.last // Ugly case. Use multiple queues if ((cParam.srcSpeedup > 1 \|\| cParam.destSpeedup > 1 \|\| fullSize <= 1) \|\| !cParam.unifiedBuffer) { require(useOutputQueues) val qs = cParam.virtualChannelParams.map(v => Module(new Queue(new BaseFlit(cParam.payloadBits), v.bufferSize))) qs.zipWithIndex.foreach { case (q,i) => val sel = io.enq.map(f => f.valid && f.bits.virt_channel_id === i.U) q.io.enq.valid := sel.orR q.io.enq.bits.head := Mux1H(sel, io.enq.map(_.bits.head)) q.io.enq.bits.tail := Mux1H(sel, io.enq.map(_.bits.tail)) q.io.enq.bits.payload := Mux1H(sel, io.enq.map(_.bits.payload)) io.deq(i) <> q.io.deq } } else { val mem = Mem(fullSize, new BaseFlit(cParam.payloadBits)) val heads = RegInit(VecInit(starts.map(_.U(log2Ceil(fullSize).W)))) val tails = RegInit(VecInit(starts.map(_.U(log2Ceil(fullSize).W)))) val empty = (heads zip tails).map(t => t._1 === t._2) val qs = Seq.fill(nVirtualChannels) { Module(new Queue(new BaseFlit(cParam.payloadBits), 1, pipe=true)) } qs.foreach(_.io.enq.valid := false.B) qs.foreach(_.io.enq.bits := DontCare) val vc_sel = UIntToOH(io.enq(0).bits.virt_channel_id) val flit = Wire(new BaseFlit(cParam.payloadBits)) val direct_to_q = (Mux1H(vc_sel, qs.map(_.io.enq.ready)) && Mux1H(vc_sel, empty)) && useOutputQueues.B flit.head := io.enq(0).bits.head flit.tail := io.enq(0).bits.tail flit.payload := io.enq(0).bits.payload when (io.enq(0).valid && !direct_to_q) { val tail = tails(io.enq(0).bits.virt_channel_id) mem.write(tail, flit) tails(io.enq(0).bits.virt_channel_id) := Mux( tail === Mux1H(vc_sel, ends.map(_ - 1).map(_ max 0).map(_.U)), Mux1H(vc_sel, starts.map(_.U)), tail + 1.U) } .elsewhen (io.enq(0).valid && direct_to_q) { for (i <- 0 until nVirtualChannels) { when (io.enq(0).bits.virt_channel_id === i.U) { qs(i).io.enq.valid := true.B qs(i).io.enq.bits := flit } } } if (useOutputQueues) { val can_to_q = (0 until nVirtualChannels).map { i => !empty(i) && qs(i).io.enq.ready } val to_q_oh = PriorityEncoderOH(can_to_q) val to_q = OHToUInt(to_q_oh) when (can_to_q.orR) { val head = Mux1H(to_q_oh, heads) heads(to_q) := Mux( head === Mux1H(to_q_oh, ends.map(_ - 1).map(_ max 0).map(_.U)), Mux1H(to_q_oh, starts.map(_.U)), head + 1.U) for (i <- 0 until nVirtualChannels) { when (to_q_oh(i)) { qs(i).io.enq.valid := true.B qs(i).io.enq.bits := mem.read(head) } } } for (i <- 0 until nVirtualChannels) { io.deq(i) <> qs(i).io.deq } } else { qs.map(_.io.deq.ready := false.B) val ready_sel = io.deq.map(_.ready) val fire = io.deq.map(_.fire) assert(PopCount(fire) <= 1.U) val head = Mux1H(fire, heads) when (fire.orR) { val fire_idx = OHToUInt(fire) heads(fire_idx) := Mux( head === Mux1H(fire, ends.map(_ - 1).map(_ max 0).map(_.U)), Mux1H(fire, starts.map(_.U)), head + 1.U) } val read_flit = mem.read(head) for (i <- 0 until nVirtualChannels) { io.deq(i).valid := !empty(i) io.deq(i).bits := read_flit } } } } class InputUnit(cParam: ChannelParams, outParams: Seq[ChannelParams], egressParams: Seq[EgressChannelParams], combineRCVA: Boolean, combineSAST: Boolean ) (implicit p: Parameters) extends AbstractInputUnit(cParam, outParams, egressParams)(p) { val nVirtualChannels = cParam.nVirtualChannels val virtualChannelParams = cParam.virtualChannelParams class InputUnitIO extends AbstractInputUnitIO(cParam, outParams, egressParams) { val in = Flipped(new Channel(cParam.asInstanceOf[ChannelParams])) } val io = IO(new InputUnitIO) val g_i :: g_r :: g_v :: g_a :: g_c :: Nil = Enum(5) class InputState extends Bundle { val g = UInt(3.W) val vc_sel = MixedVec(allOutParams.map { u => Vec(u.nVirtualChannels, Bool()) }) val flow = new FlowRoutingBundle val fifo_deps = UInt(nVirtualChannels.W) } val input_buffer = Module(new InputBuffer(cParam)) for (i <- 0 until cParam.srcSpeedup) { input_buffer.io.enq(i) := io.in.flit(i) } input_buffer.io.deq.foreach(_.ready := false.B) val route_arbiter = Module(new Arbiter( new RouteComputerReq, nVirtualChannels )) io.router_req <> route_arbiter.io.out val states = Reg(Vec(nVirtualChannels, new InputState)) val anyFifo = cParam.possibleFlows.map(_.fifo).reduce(_\|\|_) val allFifo = cParam.possibleFlows.map(_.fifo).reduce(_&&_) if (anyFifo) { val idle_mask = VecInit(states.map(_.g === g_i)).asUInt for (s <- states) for (i <- 0 until nVirtualChannels) s.fifo_deps := s.fifo_deps & ~idle_mask } for (i <- 0 until cParam.srcSpeedup) { when (io.in.flit(i).fire && io.in.flit(i).bits.head) { val id = io.in.flit(i).bits.virt_channel_id assert(id < nVirtualChannels.U) assert(states(id).g === g_i) val at_dest = io.in.flit(i).bits.flow.egress_node === nodeId.U states(id).g := Mux(at_dest, g_v, g_r) states(id).vc_sel.foreach(_.foreach(_ := false.B)) for (o <- 0 until nEgress) { when (o.U === io.in.flit(i).bits.flow.egress_node_id) { states(id).vc_sel(o+nOutputs)(0) := true.B } } states(id).flow := io.in.flit(i).bits.flow if (anyFifo) { val fifo = cParam.possibleFlows.filter(_.fifo).map(_.isFlow(io.in.flit(i).bits.flow)).toSeq.orR states(id).fifo_deps := VecInit(states.zipWithIndex.map { case (s, j) => s.g =/= g_i && s.flow.asUInt === io.in.flit(i).bits.flow.asUInt && j.U =/= id }).asUInt } } } (route_arbiter.io.in zip states).zipWithIndex.map { case ((i,s),idx) => if (virtualChannelParams(idx).traversable) { i.valid := s.g === g_r i.bits.flow := s.flow i.bits.src_virt_id := idx.U when (i.fire) { s.g := g_v } } else { i.valid := false.B i.bits := DontCare } } when (io.router_req.fire) { val id = io.router_req.bits.src_virt_id assert(states(id).g === g_r) states(id).g := g_v for (i <- 0 until nVirtualChannels) { when (i.U === id) { states(i).vc_sel := io.router_resp.vc_sel } } } val mask = RegInit(0.U(nVirtualChannels.W)) val vcalloc_reqs = Wire(Vec(nVirtualChannels, new VCAllocReq(cParam, outParams, egressParams))) val vcalloc_vals = Wire(Vec(nVirtualChannels, Bool())) val vcalloc_filter = PriorityEncoderOH(Cat(vcalloc_vals.asUInt, vcalloc_vals.asUInt & ~mask)) val vcalloc_sel = vcalloc_filter(nVirtualChannels-1,0) \| (vcalloc_filter >> nVirtualChannels) // Prioritize incoming packetes when (io.router_req.fire) { mask := (1.U << io.router_req.bits.src_virt_id) - 1.U } .elsewhen (vcalloc_vals.orR) { mask := Mux1H(vcalloc_sel, (0 until nVirtualChannels).map { w => ~(0.U((w+1).W)) }) } io.vcalloc_req.valid := vcalloc_vals.orR io.vcalloc_req.bits := Mux1H(vcalloc_sel, vcalloc_reqs) states.zipWithIndex.map { case (s,idx) => if (virtualChannelParams(idx).traversable) { vcalloc_vals(idx) := s.g === g_v && s.fifo_deps === 0.U vcalloc_reqs(idx).in_vc := idx.U vcalloc_reqs(idx).vc_sel := s.vc_sel vcalloc_reqs(idx).flow := s.flow when (vcalloc_vals(idx) && vcalloc_sel(idx) && io.vcalloc_req.ready) { s.g := g_a } if (combineRCVA) { when (route_arbiter.io.in(idx).fire) { vcalloc_vals(idx) := true.B vcalloc_reqs(idx).vc_sel := io.router_resp.vc_sel } } } else { vcalloc_vals(idx) := false.B vcalloc_reqs(idx) := DontCare } } io.debug.va_stall := PopCount(vcalloc_vals) - io.vcalloc_req.ready when (io.vcalloc_req.fire) { for (i <- 0 until nVirtualChannels) { when (vcalloc_sel(i)) { states(i).vc_sel := io.vcalloc_resp.vc_sel states(i).g := g_a if (!combineRCVA) { assert(states(i).g === g_v) } } } } val salloc_arb = Module(new SwitchArbiter( nVirtualChannels, cParam.destSpeedup, outParams, egressParams )) (states zip salloc_arb.io.in).zipWithIndex.map { case ((s,r),i) => if (virtualChannelParams(i).traversable) { val credit_available = (s.vc_sel.asUInt & io.out_credit_available.asUInt) =/= 0.U r.valid := s.g === g_a && credit_available && input_buffer.io.deq(i).valid r.bits.vc_sel := s.vc_sel val deq_tail = input_buffer.io.deq(i).bits.tail r.bits.tail := deq_tail when (r.fire && deq_tail) { s.g := g_i } input_buffer.io.deq(i).ready := r.ready } else { r.valid := false.B r.bits := DontCare } } io.debug.sa_stall := PopCount(salloc_arb.io.in.map(r => r.valid && !r.ready)) io.salloc_req <> salloc_arb.io.out when (io.block) { salloc_arb.io.out.foreach(_.ready := false.B) io.salloc_req.foreach(_.valid := false.B) } class OutBundle extends Bundle { val valid = Bool() val vid = UInt(virtualChannelBits.W) val out_vid = UInt(log2Up(allOutParams.map(_.nVirtualChannels).max).W) val flit = new Flit(cParam.payloadBits) } val salloc_outs = if (combineSAST) { Wire(Vec(cParam.destSpeedup, new OutBundle)) } else { Reg(Vec(cParam.destSpeedup, new OutBundle)) } io.in.credit_return := salloc_arb.io.out.zipWithIndex.map { case (o, i) => Mux(o.fire, salloc_arb.io.chosen_oh(i), 0.U) }.reduce(_\|_) io.in.vc_free := salloc_arb.io.out.zipWithIndex.map { case (o, i) => Mux(o.fire && Mux1H(salloc_arb.io.chosen_oh(i), input_buffer.io.deq.map(_.bits.tail)), salloc_arb.io.chosen_oh(i), 0.U) }.reduce(_\|_) for (i <- 0 until cParam.destSpeedup) { val salloc_out = salloc_outs(i) salloc_out.valid := salloc_arb.io.out(i).fire salloc_out.vid := OHToUInt(salloc_arb.io.chosen_oh(i)) val vc_sel = Mux1H(salloc_arb.io.chosen_oh(i), states.map(_.vc_sel)) val channel_oh = vc_sel.map(_.reduce(_\|\|_)).toSeq val virt_channel = Mux1H(channel_oh, vc_sel.map(v => OHToUInt(v)).toSeq) when (salloc_arb.io.out(i).fire) { salloc_out.out_vid := virt_channel salloc_out.flit.payload := Mux1H(salloc_arb.io.chosen_oh(i), input_buffer.io.deq.map(_.bits.payload)) salloc_out.flit.head := Mux1H(salloc_arb.io.chosen_oh(i), input_buffer.io.deq.map(_.bits.head)) salloc_out.flit.tail := Mux1H(salloc_arb.io.chosen_oh(i), input_buffer.io.deq.map(_.bits.tail)) salloc_out.flit.flow := Mux1H(salloc_arb.io.chosen_oh(i), states.map(_.flow)) } .otherwise { salloc_out.out_vid := DontCare salloc_out.flit := DontCare } salloc_out.flit.virt_channel_id := DontCare // this gets set in the switch io.out(i).valid := salloc_out.valid io.out(i).bits.flit := salloc_out.flit io.out(i).bits.out_virt_channel := salloc_out.out_vid } def filterVCSel(sel: MixedVec[Vec[Bool]], srcV: Int) = { if (virtualChannelParams(srcV).traversable) { outParams.zipWithIndex.map { case (oP, oI) => (0 until oP.nVirtualChannels).map { oV => var allow = false virtualChannelParams(srcV).possibleFlows.foreach { pI => allow = allow \|\| routingRelation( cParam.channelRoutingInfos(srcV), oP.channelRoutingInfos(oV), pI ) } if (!allow) sel(oI)(oV) := false.B } } } } (0 until nVirtualChannels).map { i => if (!virtualChannelParams(i).traversable) states(i) := DontCare filterVCSel(states(i).vc_sel, i) } when (reset.asBool) { states.foreach(_.g := g_i) } }	module InputUnit_73( // @[InputUnit.scala:158:7] input clock, // @[InputUnit.scala:158:7] input reset, // @[InputUnit.scala:158:7] input io_vcalloc_req_ready, // @[InputUnit.scala:170:14] output io_vcalloc_req_valid, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_3_0, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_2_0, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_1_0, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_3_0, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_2_0, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_1_0, // @[InputUnit.scala:170:14] input io_out_credit_available_3_0, // @[InputUnit.scala:170:14] input io_out_credit_available_2_0, // @[InputUnit.scala:170:14] input io_out_credit_available_1_0, // @[InputUnit.scala:170:14] input io_out_credit_available_0_1, // @[InputUnit.scala:170:14] input io_salloc_req_0_ready, // @[InputUnit.scala:170:14] output io_salloc_req_0_valid, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_3_0, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_2_0, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_1_0, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_tail, // @[InputUnit.scala:170:14] output io_out_0_valid, // @[InputUnit.scala:170:14] output io_out_0_bits_flit_head, // @[InputUnit.scala:170:14] output io_out_0_bits_flit_tail, // @[InputUnit.scala:170:14] output [72:0] io_out_0_bits_flit_payload, // @[InputUnit.scala:170:14] output [2:0] io_out_0_bits_flit_flow_vnet_id, // @[InputUnit.scala:170:14] output [4:0] io_out_0_bits_flit_flow_ingress_node, // @[InputUnit.scala:170:14] output [1:0] io_out_0_bits_flit_flow_ingress_node_id, // @[InputUnit.scala:170:14] output [4:0] io_out_0_bits_flit_flow_egress_node, // @[InputUnit.scala:170:14] output [1:0] io_out_0_bits_flit_flow_egress_node_id, // @[InputUnit.scala:170:14] output [2:0] io_debug_va_stall, // @[InputUnit.scala:170:14] output [2:0] io_debug_sa_stall, // @[InputUnit.scala:170:14] input io_in_flit_0_valid, // @[InputUnit.scala:170:14] input io_in_flit_0_bits_head, // @[InputUnit.scala:170:14] input io_in_flit_0_bits_tail, // @[InputUnit.scala:170:14] input [72:0] io_in_flit_0_bits_payload, // @[InputUnit.scala:170:14] input [2:0] io_in_flit_0_bits_flow_vnet_id, // @[InputUnit.scala:170:14] input [4:0] io_in_flit_0_bits_flow_ingress_node, // @[InputUnit.scala:170:14] input [1:0] io_in_flit_0_bits_flow_ingress_node_id, // @[InputUnit.scala:170:14] input [4:0] io_in_flit_0_bits_flow_egress_node, // @[InputUnit.scala:170:14] input [1:0] io_in_flit_0_bits_flow_egress_node_id, // @[InputUnit.scala:170:14] input [2:0] io_in_flit_0_bits_virt_channel_id, // @[InputUnit.scala:170:14] output [4:0] io_in_credit_return, // @[InputUnit.scala:170:14] output [4:0] io_in_vc_free // @[InputUnit.scala:170:14] ); wire vcalloc_vals_4; // @[InputUnit.scala:266:32] wire _salloc_arb_io_in_4_ready; // @[InputUnit.scala:296:26] wire _salloc_arb_io_out_0_valid; // @[InputUnit.scala:296:26] wire [4:0] _salloc_arb_io_chosen_oh_0; // @[InputUnit.scala:296:26] wire _route_arbiter_io_in_4_ready; // @[InputUnit.scala:187:29] wire _route_arbiter_io_out_valid; // @[InputUnit.scala:187:29] wire [2:0] _route_arbiter_io_out_bits_src_virt_id; // @[InputUnit.scala:187:29] wire _input_buffer_io_deq_0_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_0_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_0_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_1_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_1_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_1_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_2_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_2_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_2_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_3_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_3_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_3_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_4_valid; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_4_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_4_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_4_bits_payload; // @[InputUnit.scala:181:28] reg [2:0] states_4_g; // @[InputUnit.scala:192:19] reg states_4_vc_sel_3_0; // @[InputUnit.scala:192:19] reg states_4_vc_sel_2_0; // @[InputUnit.scala:192:19] reg states_4_vc_sel_1_0; // @[InputUnit.scala:192:19] reg [2:0] states_4_flow_vnet_id; // @[InputUnit.scala:192:19] reg [4:0] states_4_flow_ingress_node; // @[InputUnit.scala:192:19] reg [1:0] states_4_flow_ingress_node_id; // @[InputUnit.scala:192:19] reg [4:0] states_4_flow_egress_node; // @[InputUnit.scala:192:19] reg [1:0] states_4_flow_egress_node_id; // @[InputUnit.scala:192:19] wire _GEN = io_in_flit_0_valid & io_in_flit_0_bits_head; // @[InputUnit.scala:205:30] wire route_arbiter_io_in_4_valid = states_4_g == 3'h1; // @[InputUnit.scala:192:19, :229:22] reg [4:0] mask; // @[InputUnit.scala:250:21] wire [4:0] _vcalloc_filter_T_3 = {vcalloc_vals_4, 4'h0} & ~mask; // @[InputUnit.scala:158:7, :250:21, :253:{80,87,89}, :266:32] wire [9:0] vcalloc_filter = _vcalloc_filter_T_3[0] ? 10'h1 : _vcalloc_filter_T_3[1] ? 10'h2 : _vcalloc_filter_T_3[2] ? 10'h4 : _vcalloc_filter_T_3[3] ? 10'h8 : _vcalloc_filter_T_3[4] ? 10'h10 : {vcalloc_vals_4, 9'h0}; // @[OneHot.scala:85:71] wire [4:0] vcalloc_sel = vcalloc_filter[4:0] \| vcalloc_filter[9:5]; // @[Mux.scala:50:70] assign vcalloc_vals_4 = states_4_g == 3'h2; // @[InputUnit.scala:192:19, :266:32] wire _GEN_0 = io_vcalloc_req_ready & vcalloc_vals_4; // @[Decoupled.scala:51:35] wire _GEN_1 = _GEN_0 & vcalloc_sel[4]; // @[Mux.scala:32:36]
Generate the Verilog code corresponding to the following Chisel files. File lsu.scala: //**************************************************************************** // Copyright (c) 2012 - 2018, The Regents of the University of California (Regents). // All Rights Reserved. See LICENSE and LICENSE.SiFive for license details. //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ // RISCV Out-of-Order Load/Store Unit //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ // // Load/Store Unit is made up of the Load Queue, the Store Queue (LDQ and STQ). // // Stores are sent to memory at (well, after) commit, loads are executed // optimstically ASAP. If a misspeculation was discovered, the pipeline is // cleared. Loads put to sleep are retried. If a LoadAddr and StoreAddr match, // the Load can receive its data by forwarding data out of the Store Queue. // // Currently, loads are sent to memory immediately, and in parallel do an // associative search of the STQ, on entering the LSU. If a hit on the STQ // search, the memory request is killed on the next cycle, and if the STQ entry // is valid, the store data is forwarded to the load (delayed to match the // load-use delay to delay with the write-port structural hazard). If the store // data is not present, or it's only a partial match (SB->LH), the load is put // to sleep in the LDQ. // // Memory ordering violations are detected by stores at their addr-gen time by // associatively searching the LDQ for newer loads that have been issued to // memory. // // The store queue contains both speculated and committed stores. // // Only one port to memory... loads and stores have to fight for it, West Side // Story style. // // TODO: // - Add predicting structure for ordering failures // - currently won't STD forward if DMEM is busy // - ability to turn off things if VM is disabled // - reconsider port count of the wakeup, retry stuff package boom.v3.lsu import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.rocket import freechips.rocketchip.tilelink._ import freechips.rocketchip.util.Str import boom.v3.common._ import boom.v3.exu.{BrUpdateInfo, Exception, FuncUnitResp, CommitSignals, ExeUnitResp} import boom.v3.util.{BoolToChar, AgePriorityEncoder, IsKilledByBranch, GetNewBrMask, WrapInc, IsOlder, UpdateBrMask} class LSUExeIO(implicit p: Parameters) extends BoomBundle()(p) { // The "resp" of the maddrcalc is really a "req" to the LSU val req = Flipped(new ValidIO(new FuncUnitResp(xLen))) // Send load data to regfiles val iresp = new DecoupledIO(new boom.v3.exu.ExeUnitResp(xLen)) val fresp = new DecoupledIO(new boom.v3.exu.ExeUnitResp(xLen+1)) // TODO: Should this be fLen? } class BoomDCacheReq(implicit p: Parameters) extends BoomBundle()(p) with HasBoomUOP { val addr = UInt(coreMaxAddrBits.W) val data = Bits(coreDataBits.W) val is_hella = Bool() // Is this the hellacache req? If so this is not tracked in LDQ or STQ } class BoomDCacheResp(implicit p: Parameters) extends BoomBundle()(p) with HasBoomUOP { val data = Bits(coreDataBits.W) val is_hella = Bool() } class LSUDMemIO(implicit p: Parameters, edge: TLEdgeOut) extends BoomBundle()(p) { // In LSU's dmem stage, send the request val req = new DecoupledIO(Vec(memWidth, Valid(new BoomDCacheReq))) // In LSU's LCAM search stage, kill if order fail (or forwarding possible) val s1_kill = Output(Vec(memWidth, Bool())) // Get a request any cycle val resp = Flipped(Vec(memWidth, new ValidIO(new BoomDCacheResp))) // In our response stage, if we get a nack, we need to reexecute val nack = Flipped(Vec(memWidth, new ValidIO(new BoomDCacheReq))) val brupdate = Output(new BrUpdateInfo) val exception = Output(Bool()) val rob_pnr_idx = Output(UInt(robAddrSz.W)) val rob_head_idx = Output(UInt(robAddrSz.W)) val release = Flipped(new DecoupledIO(new TLBundleC(edge.bundle))) // Clears prefetching MSHRs val force_order = Output(Bool()) val ordered = Input(Bool()) val perf = Input(new Bundle { val acquire = Bool() val release = Bool() }) } class LSUCoreIO(implicit p: Parameters) extends BoomBundle()(p) { val exe = Vec(memWidth, new LSUExeIO) val dis_uops = Flipped(Vec(coreWidth, Valid(new MicroOp))) val dis_ldq_idx = Output(Vec(coreWidth, UInt(ldqAddrSz.W))) val dis_stq_idx = Output(Vec(coreWidth, UInt(stqAddrSz.W))) val ldq_full = Output(Vec(coreWidth, Bool())) val stq_full = Output(Vec(coreWidth, Bool())) val fp_stdata = Flipped(Decoupled(new ExeUnitResp(fLen))) val commit = Input(new CommitSignals) val commit_load_at_rob_head = Input(Bool()) // Stores clear busy bit when stdata is received // memWidth for int, 1 for fp (to avoid back-pressure fpstdat) val clr_bsy = Output(Vec(memWidth + 1, Valid(UInt(robAddrSz.W)))) // Speculatively safe load (barring memory ordering failure) val clr_unsafe = Output(Vec(memWidth, Valid(UInt(robAddrSz.W)))) // Tell the DCache to clear prefetches/speculating misses val fence_dmem = Input(Bool()) // Speculatively tell the IQs that we'll get load data back next cycle val spec_ld_wakeup = Output(Vec(memWidth, Valid(UInt(maxPregSz.W)))) // Tell the IQs that the load we speculated last cycle was misspeculated val ld_miss = Output(Bool()) val brupdate = Input(new BrUpdateInfo) val rob_pnr_idx = Input(UInt(robAddrSz.W)) val rob_head_idx = Input(UInt(robAddrSz.W)) val exception = Input(Bool()) val fencei_rdy = Output(Bool()) val lxcpt = Output(Valid(new Exception)) val tsc_reg = Input(UInt()) val perf = Output(new Bundle { val acquire = Bool() val release = Bool() val tlbMiss = Bool() }) } class LSUIO(implicit p: Parameters, edge: TLEdgeOut) extends BoomBundle()(p) { val ptw = new rocket.TLBPTWIO val core = new LSUCoreIO val dmem = new LSUDMemIO val hellacache = Flipped(new freechips.rocketchip.rocket.HellaCacheIO) } class LDQEntry(implicit p: Parameters) extends BoomBundle()(p) with HasBoomUOP { val addr = Valid(UInt(coreMaxAddrBits.W)) val addr_is_virtual = Bool() // Virtual address, we got a TLB miss val addr_is_uncacheable = Bool() // Uncacheable, wait until head of ROB to execute val executed = Bool() // load sent to memory, reset by NACKs val succeeded = Bool() val order_fail = Bool() val observed = Bool() val st_dep_mask = UInt(numStqEntries.W) // list of stores older than us val youngest_stq_idx = UInt(stqAddrSz.W) // index of the oldest store younger than us val forward_std_val = Bool() val forward_stq_idx = UInt(stqAddrSz.W) // Which store did we get the store-load forward from? val debug_wb_data = UInt(xLen.W) } class STQEntry(implicit p: Parameters) extends BoomBundle()(p) with HasBoomUOP { val addr = Valid(UInt(coreMaxAddrBits.W)) val addr_is_virtual = Bool() // Virtual address, we got a TLB miss val data = Valid(UInt(xLen.W)) val committed = Bool() // committed by ROB val succeeded = Bool() // D$ has ack'd this, we don't need to maintain this anymore val debug_wb_data = UInt(xLen.W) } class LSU(implicit p: Parameters, edge: TLEdgeOut) extends BoomModule()(p) with rocket.HasL1HellaCacheParameters { val io = IO(new LSUIO) io.hellacache := DontCare val ldq = Reg(Vec(numLdqEntries, Valid(new LDQEntry))) val stq = Reg(Vec(numStqEntries, Valid(new STQEntry))) val ldq_head = Reg(UInt(ldqAddrSz.W)) val ldq_tail = Reg(UInt(ldqAddrSz.W)) val stq_head = Reg(UInt(stqAddrSz.W)) // point to next store to clear from STQ (i.e., send to memory) val stq_tail = Reg(UInt(stqAddrSz.W)) val stq_commit_head = Reg(UInt(stqAddrSz.W)) // point to next store to commit val stq_execute_head = Reg(UInt(stqAddrSz.W)) // point to next store to execute // If we got a mispredict, the tail will be misaligned for 1 extra cycle assert (io.core.brupdate.b2.mispredict \|\| stq(stq_execute_head).valid \|\| stq_head === stq_execute_head \|\| stq_tail === stq_execute_head, "stq_execute_head got off track.") val h_ready :: h_s1 :: h_s2 :: h_s2_nack :: h_wait :: h_replay :: h_dead :: Nil = Enum(7) // s1 : do TLB, if success and not killed, fire request go to h_s2 // store s1_data to register // if tlb miss, go to s2_nack // if don't get TLB, go to s2_nack // store tlb xcpt // s2 : If kill, go to dead // If tlb xcpt, send tlb xcpt, go to dead // s2_nack : send nack, go to dead // wait : wait for response, if nack, go to replay // replay : refire request, use already translated address // dead : wait for response, ignore it val hella_state = RegInit(h_ready) val hella_req = Reg(new rocket.HellaCacheReq) val hella_data = Reg(new rocket.HellaCacheWriteData) val hella_paddr = Reg(UInt(paddrBits.W)) val hella_xcpt = Reg(new rocket.HellaCacheExceptions) val dtlb = Module(new NBDTLB( instruction = false, lgMaxSize = log2Ceil(coreDataBytes), rocket.TLBConfig(dcacheParams.nTLBSets, dcacheParams.nTLBWays))) io.ptw <> dtlb.io.ptw io.core.perf.tlbMiss := io.ptw.req.fire io.core.perf.acquire := io.dmem.perf.acquire io.core.perf.release := io.dmem.perf.release val clear_store = WireInit(false.B) val live_store_mask = RegInit(0.U(numStqEntries.W)) var next_live_store_mask = Mux(clear_store, live_store_mask & ~(1.U << stq_head), live_store_mask) def widthMap[T <: Data](f: Int => T) = VecInit((0 until memWidth).map(f)) //------------------------------------------------------------- //------------------------------------------------------------- // Enqueue new entries //------------------------------------------------------------- //------------------------------------------------------------- // This is a newer store than existing loads, so clear the bit in all the store dependency masks for (i <- 0 until numLdqEntries) { when (clear_store) { ldq(i).bits.st_dep_mask := ldq(i).bits.st_dep_mask & ~(1.U << stq_head) } } // Decode stage var ld_enq_idx = ldq_tail var st_enq_idx = stq_tail val stq_nonempty = (0 until numStqEntries).map{ i => stq(i).valid }.reduce(_\|\|_) =/= 0.U var ldq_full = Bool() var stq_full = Bool() for (w <- 0 until coreWidth) { ldq_full = WrapInc(ld_enq_idx, numLdqEntries) === ldq_head io.core.ldq_full(w) := ldq_full io.core.dis_ldq_idx(w) := ld_enq_idx stq_full = WrapInc(st_enq_idx, numStqEntries) === stq_head io.core.stq_full(w) := stq_full io.core.dis_stq_idx(w) := st_enq_idx val dis_ld_val = io.core.dis_uops(w).valid && io.core.dis_uops(w).bits.uses_ldq && !io.core.dis_uops(w).bits.exception val dis_st_val = io.core.dis_uops(w).valid && io.core.dis_uops(w).bits.uses_stq && !io.core.dis_uops(w).bits.exception when (dis_ld_val) { ldq(ld_enq_idx).valid := true.B ldq(ld_enq_idx).bits.uop := io.core.dis_uops(w).bits ldq(ld_enq_idx).bits.youngest_stq_idx := st_enq_idx ldq(ld_enq_idx).bits.st_dep_mask := next_live_store_mask ldq(ld_enq_idx).bits.addr.valid := false.B ldq(ld_enq_idx).bits.executed := false.B ldq(ld_enq_idx).bits.succeeded := false.B ldq(ld_enq_idx).bits.order_fail := false.B ldq(ld_enq_idx).bits.observed := false.B ldq(ld_enq_idx).bits.forward_std_val := false.B assert (ld_enq_idx === io.core.dis_uops(w).bits.ldq_idx, "[lsu] mismatch enq load tag.") assert (!ldq(ld_enq_idx).valid, "[lsu] Enqueuing uop is overwriting ldq entries") } .elsewhen (dis_st_val) { stq(st_enq_idx).valid := true.B stq(st_enq_idx).bits.uop := io.core.dis_uops(w).bits stq(st_enq_idx).bits.addr.valid := false.B stq(st_enq_idx).bits.data.valid := false.B stq(st_enq_idx).bits.committed := false.B stq(st_enq_idx).bits.succeeded := false.B assert (st_enq_idx === io.core.dis_uops(w).bits.stq_idx, "[lsu] mismatch enq store tag.") assert (!stq(st_enq_idx).valid, "[lsu] Enqueuing uop is overwriting stq entries") } ld_enq_idx = Mux(dis_ld_val, WrapInc(ld_enq_idx, numLdqEntries), ld_enq_idx) next_live_store_mask = Mux(dis_st_val, next_live_store_mask \| (1.U << st_enq_idx), next_live_store_mask) st_enq_idx = Mux(dis_st_val, WrapInc(st_enq_idx, numStqEntries), st_enq_idx) assert(!(dis_ld_val && dis_st_val), "A UOP is trying to go into both the LDQ and the STQ") } ldq_tail := ld_enq_idx stq_tail := st_enq_idx io.dmem.force_order := io.core.fence_dmem io.core.fencei_rdy := !stq_nonempty && io.dmem.ordered //------------------------------------------------------------- //------------------------------------------------------------- // Execute stage (access TLB, send requests to Memory) //------------------------------------------------------------- //------------------------------------------------------------- // We can only report 1 exception per cycle. // Just be sure to report the youngest one val mem_xcpt_valid = Wire(Bool()) val mem_xcpt_cause = Wire(UInt()) val mem_xcpt_uop = Wire(new MicroOp) val mem_xcpt_vaddr = Wire(UInt()) //--------------------------------------- // Can-fire logic and wakeup/retry select // // First we determine what operations are waiting to execute. // These are the "can_fire"/"will_fire" signals val will_fire_load_incoming = Wire(Vec(memWidth, Bool())) val will_fire_stad_incoming = Wire(Vec(memWidth, Bool())) val will_fire_sta_incoming = Wire(Vec(memWidth, Bool())) val will_fire_std_incoming = Wire(Vec(memWidth, Bool())) val will_fire_sfence = Wire(Vec(memWidth, Bool())) val will_fire_hella_incoming = Wire(Vec(memWidth, Bool())) val will_fire_hella_wakeup = Wire(Vec(memWidth, Bool())) val will_fire_release = Wire(Vec(memWidth, Bool())) val will_fire_load_retry = Wire(Vec(memWidth, Bool())) val will_fire_sta_retry = Wire(Vec(memWidth, Bool())) val will_fire_store_commit = Wire(Vec(memWidth, Bool())) val will_fire_load_wakeup = Wire(Vec(memWidth, Bool())) val exe_req = WireInit(VecInit(io.core.exe.map(_.req))) // Sfence goes through all pipes for (i <- 0 until memWidth) { when (io.core.exe(i).req.bits.sfence.valid) { exe_req := VecInit(Seq.fill(memWidth) { io.core.exe(i).req }) } } // ------------------------------- // Assorted signals for scheduling // Don't wakeup a load if we just sent it last cycle or two cycles ago // The block_load_mask may be wrong, but the executing_load mask must be accurate val block_load_mask = WireInit(VecInit((0 until numLdqEntries).map(x=>false.B))) val p1_block_load_mask = RegNext(block_load_mask) val p2_block_load_mask = RegNext(p1_block_load_mask) // Prioritize emptying the store queue when it is almost full val stq_almost_full = RegNext(WrapInc(WrapInc(st_enq_idx, numStqEntries), numStqEntries) === stq_head \|\| WrapInc(st_enq_idx, numStqEntries) === stq_head) // The store at the commit head needs the DCache to appear ordered // Delay firing load wakeups and retries now val store_needs_order = WireInit(false.B) val ldq_incoming_idx = widthMap(i => exe_req(i).bits.uop.ldq_idx) val ldq_incoming_e = widthMap(i => ldq(ldq_incoming_idx(i))) val stq_incoming_idx = widthMap(i => exe_req(i).bits.uop.stq_idx) val stq_incoming_e = widthMap(i => stq(stq_incoming_idx(i))) val ldq_retry_idx = RegNext(AgePriorityEncoder((0 until numLdqEntries).map(i => { val e = ldq(i).bits val block = block_load_mask(i) \|\| p1_block_load_mask(i) e.addr.valid && e.addr_is_virtual && !block }), ldq_head)) val ldq_retry_e = ldq(ldq_retry_idx) val stq_retry_idx = RegNext(AgePriorityEncoder((0 until numStqEntries).map(i => { val e = stq(i).bits e.addr.valid && e.addr_is_virtual }), stq_commit_head)) val stq_retry_e = stq(stq_retry_idx) val stq_commit_e = stq(stq_execute_head) val ldq_wakeup_idx = RegNext(AgePriorityEncoder((0 until numLdqEntries).map(i=> { val e = ldq(i).bits val block = block_load_mask(i) \|\| p1_block_load_mask(i) e.addr.valid && !e.executed && !e.succeeded && !e.addr_is_virtual && !block }), ldq_head)) val ldq_wakeup_e = ldq(ldq_wakeup_idx) // ----------------------- // Determine what can fire // Can we fire a incoming load val can_fire_load_incoming = widthMap(w => exe_req(w).valid && exe_req(w).bits.uop.ctrl.is_load) // Can we fire an incoming store addrgen + store datagen val can_fire_stad_incoming = widthMap(w => exe_req(w).valid && exe_req(w).bits.uop.ctrl.is_sta && exe_req(w).bits.uop.ctrl.is_std) // Can we fire an incoming store addrgen val can_fire_sta_incoming = widthMap(w => exe_req(w).valid && exe_req(w).bits.uop.ctrl.is_sta && !exe_req(w).bits.uop.ctrl.is_std) // Can we fire an incoming store datagen val can_fire_std_incoming = widthMap(w => exe_req(w).valid && exe_req(w).bits.uop.ctrl.is_std && !exe_req(w).bits.uop.ctrl.is_sta) // Can we fire an incoming sfence val can_fire_sfence = widthMap(w => exe_req(w).valid && exe_req(w).bits.sfence.valid) // Can we fire a request from dcache to release a line // This needs to go through LDQ search to mark loads as dangerous val can_fire_release = widthMap(w => (w == memWidth-1).B && io.dmem.release.valid) io.dmem.release.ready := will_fire_release.reduce(_\|\|_) // Can we retry a load that missed in the TLB val can_fire_load_retry = widthMap(w => ( ldq_retry_e.valid && ldq_retry_e.bits.addr.valid && ldq_retry_e.bits.addr_is_virtual && !p1_block_load_mask(ldq_retry_idx) && !p2_block_load_mask(ldq_retry_idx) && RegNext(dtlb.io.miss_rdy) && !store_needs_order && (w == memWidth-1).B && // TODO: Is this best scheduling? !ldq_retry_e.bits.order_fail)) // Can we retry a store addrgen that missed in the TLB // - Weird edge case when sta_retry and std_incoming for same entry in same cycle. Delay this val can_fire_sta_retry = widthMap(w => ( stq_retry_e.valid && stq_retry_e.bits.addr.valid && stq_retry_e.bits.addr_is_virtual && (w == memWidth-1).B && RegNext(dtlb.io.miss_rdy) && !(widthMap(i => (i != w).B && can_fire_std_incoming(i) && stq_incoming_idx(i) === stq_retry_idx).reduce(_\|\|_)) )) // Can we commit a store val can_fire_store_commit = widthMap(w => ( stq_commit_e.valid && !stq_commit_e.bits.uop.is_fence && !mem_xcpt_valid && !stq_commit_e.bits.uop.exception && (w == 0).B && (stq_commit_e.bits.committed \|\| ( stq_commit_e.bits.uop.is_amo && stq_commit_e.bits.addr.valid && !stq_commit_e.bits.addr_is_virtual && stq_commit_e.bits.data.valid)))) // Can we wakeup a load that was nack'd val block_load_wakeup = WireInit(false.B) val can_fire_load_wakeup = widthMap(w => ( ldq_wakeup_e.valid && ldq_wakeup_e.bits.addr.valid && !ldq_wakeup_e.bits.succeeded && !ldq_wakeup_e.bits.addr_is_virtual && !ldq_wakeup_e.bits.executed && !ldq_wakeup_e.bits.order_fail && !p1_block_load_mask(ldq_wakeup_idx) && !p2_block_load_mask(ldq_wakeup_idx) && !store_needs_order && !block_load_wakeup && (w == memWidth-1).B && (!ldq_wakeup_e.bits.addr_is_uncacheable \|\| (io.core.commit_load_at_rob_head && ldq_head === ldq_wakeup_idx && ldq_wakeup_e.bits.st_dep_mask.asUInt === 0.U)))) // Can we fire an incoming hellacache request val can_fire_hella_incoming = WireInit(widthMap(w => false.B)) // This is assigned to in the hellashim ocntroller // Can we fire a hellacache request that the dcache nack'd val can_fire_hella_wakeup = WireInit(widthMap(w => false.B)) // This is assigned to in the hellashim controller //--------------------------------------------------------- // Controller logic. Arbitrate which request actually fires val exe_tlb_valid = Wire(Vec(memWidth, Bool())) for (w <- 0 until memWidth) { var tlb_avail = true.B var dc_avail = true.B var lcam_avail = true.B var rob_avail = true.B def lsu_sched(can_fire: Bool, uses_tlb:Boolean, uses_dc:Boolean, uses_lcam: Boolean, uses_rob:Boolean): Bool = { val will_fire = can_fire && !(uses_tlb.B && !tlb_avail) && !(uses_lcam.B && !lcam_avail) && !(uses_dc.B && !dc_avail) && !(uses_rob.B && !rob_avail) tlb_avail = tlb_avail && !(will_fire && uses_tlb.B) lcam_avail = lcam_avail && !(will_fire && uses_lcam.B) dc_avail = dc_avail && !(will_fire && uses_dc.B) rob_avail = rob_avail && !(will_fire && uses_rob.B) dontTouch(will_fire) // dontTouch these so we can inspect the will_fire signals will_fire } // The order of these statements is the priority // Some restrictions // - Incoming ops must get precedence, can't backpresure memaddrgen // - Incoming hellacache ops must get precedence over retrying ops (PTW must get precedence over retrying translation) // Notes on performance // - Prioritize releases, this speeds up cache line writebacks and refills // - Store commits are lowest priority, since they don't "block" younger instructions unless stq fills up will_fire_load_incoming (w) := lsu_sched(can_fire_load_incoming (w) , true , true , true , false) // TLB , DC , LCAM will_fire_stad_incoming (w) := lsu_sched(can_fire_stad_incoming (w) , true , false, true , true) // TLB , , LCAM , ROB will_fire_sta_incoming (w) := lsu_sched(can_fire_sta_incoming (w) , true , false, true , true) // TLB , , LCAM , ROB will_fire_std_incoming (w) := lsu_sched(can_fire_std_incoming (w) , false, false, false, true) // , ROB will_fire_sfence (w) := lsu_sched(can_fire_sfence (w) , true , false, false, true) // TLB , , , ROB will_fire_release (w) := lsu_sched(can_fire_release (w) , false, false, true , false) // LCAM will_fire_hella_incoming(w) := lsu_sched(can_fire_hella_incoming(w) , true , true , false, false) // TLB , DC will_fire_hella_wakeup (w) := lsu_sched(can_fire_hella_wakeup (w) , false, true , false, false) // , DC will_fire_load_retry (w) := lsu_sched(can_fire_load_retry (w) , true , true , true , false) // TLB , DC , LCAM will_fire_sta_retry (w) := lsu_sched(can_fire_sta_retry (w) , true , false, true , true) // TLB , , LCAM , ROB // TODO: This should be higher priority will_fire_load_wakeup (w) := lsu_sched(can_fire_load_wakeup (w) , false, true , true , false) // , DC , LCAM1 will_fire_store_commit (w) := lsu_sched(can_fire_store_commit (w) , false, true , false, false) // , DC assert(!(exe_req(w).valid && !(will_fire_load_incoming(w) \|\| will_fire_stad_incoming(w) \|\| will_fire_sta_incoming(w) \|\| will_fire_std_incoming(w) \|\| will_fire_sfence(w)))) when (will_fire_load_wakeup(w)) { block_load_mask(ldq_wakeup_idx) := true.B } .elsewhen (will_fire_load_incoming(w)) { block_load_mask(exe_req(w).bits.uop.ldq_idx) := true.B } .elsewhen (will_fire_load_retry(w)) { block_load_mask(ldq_retry_idx) := true.B } exe_tlb_valid(w) := !tlb_avail } assert((memWidth == 1).B \|\| (!(will_fire_sfence.reduce(_\|\|_) && !will_fire_sfence.reduce(_&&_)) && !will_fire_hella_incoming.reduce(_&&_) && !will_fire_hella_wakeup.reduce(_&&_) && !will_fire_load_retry.reduce(_&&_) && !will_fire_sta_retry.reduce(_&&_) && !will_fire_store_commit.reduce(_&&_) && !will_fire_load_wakeup.reduce(_&&_)), "Some operations is proceeding down multiple pipes") require(memWidth <= 2) //-------------------------------------------- // TLB Access assert(!(hella_state =/= h_ready && hella_req.cmd === rocket.M_SFENCE), "SFENCE through hella interface not supported") val exe_tlb_uop = widthMap(w => Mux(will_fire_load_incoming (w) \|\| will_fire_stad_incoming (w) \|\| will_fire_sta_incoming (w) \|\| will_fire_sfence (w) , exe_req(w).bits.uop, Mux(will_fire_load_retry (w) , ldq_retry_e.bits.uop, Mux(will_fire_sta_retry (w) , stq_retry_e.bits.uop, Mux(will_fire_hella_incoming(w) , NullMicroOp, NullMicroOp))))) val exe_tlb_vaddr = widthMap(w => Mux(will_fire_load_incoming (w) \|\| will_fire_stad_incoming (w) \|\| will_fire_sta_incoming (w) , exe_req(w).bits.addr, Mux(will_fire_sfence (w) , exe_req(w).bits.sfence.bits.addr, Mux(will_fire_load_retry (w) , ldq_retry_e.bits.addr.bits, Mux(will_fire_sta_retry (w) , stq_retry_e.bits.addr.bits, Mux(will_fire_hella_incoming(w) , hella_req.addr, 0.U)))))) val exe_sfence = WireInit((0.U).asTypeOf(Valid(new rocket.SFenceReq))) for (w <- 0 until memWidth) { when (will_fire_sfence(w)) { exe_sfence := exe_req(w).bits.sfence } } val exe_size = widthMap(w => Mux(will_fire_load_incoming (w) \|\| will_fire_stad_incoming (w) \|\| will_fire_sta_incoming (w) \|\| will_fire_sfence (w) \|\| will_fire_load_retry (w) \|\| will_fire_sta_retry (w) , exe_tlb_uop(w).mem_size, Mux(will_fire_hella_incoming(w) , hella_req.size, 0.U))) val exe_cmd = widthMap(w => Mux(will_fire_load_incoming (w) \|\| will_fire_stad_incoming (w) \|\| will_fire_sta_incoming (w) \|\| will_fire_sfence (w) \|\| will_fire_load_retry (w) \|\| will_fire_sta_retry (w) , exe_tlb_uop(w).mem_cmd, Mux(will_fire_hella_incoming(w) , hella_req.cmd, 0.U))) val exe_passthr= widthMap(w => Mux(will_fire_hella_incoming(w) , hella_req.phys, false.B)) val exe_kill = widthMap(w => Mux(will_fire_hella_incoming(w) , io.hellacache.s1_kill, false.B)) for (w <- 0 until memWidth) { dtlb.io.req(w).valid := exe_tlb_valid(w) dtlb.io.req(w).bits.vaddr := exe_tlb_vaddr(w) dtlb.io.req(w).bits.size := exe_size(w) dtlb.io.req(w).bits.cmd := exe_cmd(w) dtlb.io.req(w).bits.passthrough := exe_passthr(w) dtlb.io.req(w).bits.v := io.ptw.status.v dtlb.io.req(w).bits.prv := io.ptw.status.prv } dtlb.io.kill := exe_kill.reduce(_\|\|_) dtlb.io.sfence := exe_sfence // exceptions val ma_ld = widthMap(w => will_fire_load_incoming(w) && exe_req(w).bits.mxcpt.valid) // We get ma_ld in memaddrcalc val ma_st = widthMap(w => (will_fire_sta_incoming(w) \|\| will_fire_stad_incoming(w)) && exe_req(w).bits.mxcpt.valid) // We get ma_ld in memaddrcalc val pf_ld = widthMap(w => dtlb.io.req(w).valid && dtlb.io.resp(w).pf.ld && exe_tlb_uop(w).uses_ldq) val pf_st = widthMap(w => dtlb.io.req(w).valid && dtlb.io.resp(w).pf.st && exe_tlb_uop(w).uses_stq) val ae_ld = widthMap(w => dtlb.io.req(w).valid && dtlb.io.resp(w).ae.ld && exe_tlb_uop(w).uses_ldq) val ae_st = widthMap(w => dtlb.io.req(w).valid && dtlb.io.resp(w).ae.st && exe_tlb_uop(w).uses_stq) // TODO check for xcpt_if and verify that never happens on non-speculative instructions. val mem_xcpt_valids = RegNext(widthMap(w => (pf_ld(w) \|\| pf_st(w) \|\| ae_ld(w) \|\| ae_st(w) \|\| ma_ld(w) \|\| ma_st(w)) && !io.core.exception && !IsKilledByBranch(io.core.brupdate, exe_tlb_uop(w)))) val mem_xcpt_uops = RegNext(widthMap(w => UpdateBrMask(io.core.brupdate, exe_tlb_uop(w)))) val mem_xcpt_causes = RegNext(widthMap(w => Mux(ma_ld(w), rocket.Causes.misaligned_load.U, Mux(ma_st(w), rocket.Causes.misaligned_store.U, Mux(pf_ld(w), rocket.Causes.load_page_fault.U, Mux(pf_st(w), rocket.Causes.store_page_fault.U, Mux(ae_ld(w), rocket.Causes.load_access.U, rocket.Causes.store_access.U))))))) val mem_xcpt_vaddrs = RegNext(exe_tlb_vaddr) for (w <- 0 until memWidth) { assert (!(dtlb.io.req(w).valid && exe_tlb_uop(w).is_fence), "Fence is pretending to talk to the TLB") assert (!((will_fire_load_incoming(w) \|\| will_fire_sta_incoming(w) \|\| will_fire_stad_incoming(w)) && exe_req(w).bits.mxcpt.valid && dtlb.io.req(w).valid && !(exe_tlb_uop(w).ctrl.is_load \|\| exe_tlb_uop(w).ctrl.is_sta)), "A uop that's not a load or store-address is throwing a memory exception.") } mem_xcpt_valid := mem_xcpt_valids.reduce(_\|\|_) mem_xcpt_cause := mem_xcpt_causes(0) mem_xcpt_uop := mem_xcpt_uops(0) mem_xcpt_vaddr := mem_xcpt_vaddrs(0) var xcpt_found = mem_xcpt_valids(0) var oldest_xcpt_rob_idx = mem_xcpt_uops(0).rob_idx for (w <- 1 until memWidth) { val is_older = WireInit(false.B) when (mem_xcpt_valids(w) && (IsOlder(mem_xcpt_uops(w).rob_idx, oldest_xcpt_rob_idx, io.core.rob_head_idx) \|\| !xcpt_found)) { is_older := true.B mem_xcpt_cause := mem_xcpt_causes(w) mem_xcpt_uop := mem_xcpt_uops(w) mem_xcpt_vaddr := mem_xcpt_vaddrs(w) } xcpt_found = xcpt_found \|\| mem_xcpt_valids(w) oldest_xcpt_rob_idx = Mux(is_older, mem_xcpt_uops(w).rob_idx, oldest_xcpt_rob_idx) } val exe_tlb_miss = widthMap(w => dtlb.io.req(w).valid && (dtlb.io.resp(w).miss \|\| !dtlb.io.req(w).ready)) val exe_tlb_paddr = widthMap(w => Cat(dtlb.io.resp(w).paddr(paddrBits-1,corePgIdxBits), exe_tlb_vaddr(w)(corePgIdxBits-1,0))) val exe_tlb_uncacheable = widthMap(w => !(dtlb.io.resp(w).cacheable)) for (w <- 0 until memWidth) { assert (exe_tlb_paddr(w) === dtlb.io.resp(w).paddr \|\| exe_req(w).bits.sfence.valid, "[lsu] paddrs should match.") when (mem_xcpt_valids(w)) { assert(RegNext(will_fire_load_incoming(w) \|\| will_fire_stad_incoming(w) \|\| will_fire_sta_incoming(w) \|\| will_fire_load_retry(w) \|\| will_fire_sta_retry(w))) // Technically only faulting AMOs need this assert(mem_xcpt_uops(w).uses_ldq ^ mem_xcpt_uops(w).uses_stq) when (mem_xcpt_uops(w).uses_ldq) { ldq(mem_xcpt_uops(w).ldq_idx).bits.uop.exception := true.B } .otherwise { stq(mem_xcpt_uops(w).stq_idx).bits.uop.exception := true.B } } } //------------------------------ // Issue Someting to Memory // // A memory op can come from many different places // The address either was freshly translated, or we are // reading a physical address from the LDQ,STQ, or the HellaCache adapter // defaults io.dmem.brupdate := io.core.brupdate io.dmem.exception := io.core.exception io.dmem.rob_head_idx := io.core.rob_head_idx io.dmem.rob_pnr_idx := io.core.rob_pnr_idx val dmem_req = Wire(Vec(memWidth, Valid(new BoomDCacheReq))) io.dmem.req.valid := dmem_req.map(_.valid).reduce(_\|\|_) io.dmem.req.bits := dmem_req val dmem_req_fire = widthMap(w => dmem_req(w).valid && io.dmem.req.fire) val s0_executing_loads = WireInit(VecInit((0 until numLdqEntries).map(x=>false.B))) for (w <- 0 until memWidth) { dmem_req(w).valid := false.B dmem_req(w).bits.uop := NullMicroOp dmem_req(w).bits.addr := 0.U dmem_req(w).bits.data := 0.U dmem_req(w).bits.is_hella := false.B io.dmem.s1_kill(w) := false.B when (will_fire_load_incoming(w)) { dmem_req(w).valid := !exe_tlb_miss(w) && !exe_tlb_uncacheable(w) dmem_req(w).bits.addr := exe_tlb_paddr(w) dmem_req(w).bits.uop := exe_tlb_uop(w) s0_executing_loads(ldq_incoming_idx(w)) := dmem_req_fire(w) assert(!ldq_incoming_e(w).bits.executed) } .elsewhen (will_fire_load_retry(w)) { dmem_req(w).valid := !exe_tlb_miss(w) && !exe_tlb_uncacheable(w) dmem_req(w).bits.addr := exe_tlb_paddr(w) dmem_req(w).bits.uop := exe_tlb_uop(w) s0_executing_loads(ldq_retry_idx) := dmem_req_fire(w) assert(!ldq_retry_e.bits.executed) } .elsewhen (will_fire_store_commit(w)) { dmem_req(w).valid := true.B dmem_req(w).bits.addr := stq_commit_e.bits.addr.bits dmem_req(w).bits.data := (new freechips.rocketchip.rocket.StoreGen( stq_commit_e.bits.uop.mem_size, 0.U, stq_commit_e.bits.data.bits, coreDataBytes)).data dmem_req(w).bits.uop := stq_commit_e.bits.uop stq_execute_head := Mux(dmem_req_fire(w), WrapInc(stq_execute_head, numStqEntries), stq_execute_head) stq(stq_execute_head).bits.succeeded := false.B } .elsewhen (will_fire_load_wakeup(w)) { dmem_req(w).valid := true.B dmem_req(w).bits.addr := ldq_wakeup_e.bits.addr.bits dmem_req(w).bits.uop := ldq_wakeup_e.bits.uop s0_executing_loads(ldq_wakeup_idx) := dmem_req_fire(w) assert(!ldq_wakeup_e.bits.executed && !ldq_wakeup_e.bits.addr_is_virtual) } .elsewhen (will_fire_hella_incoming(w)) { assert(hella_state === h_s1) dmem_req(w).valid := !io.hellacache.s1_kill && (!exe_tlb_miss(w) \|\| hella_req.phys) dmem_req(w).bits.addr := exe_tlb_paddr(w) dmem_req(w).bits.data := (new freechips.rocketchip.rocket.StoreGen( hella_req.size, 0.U, io.hellacache.s1_data.data, coreDataBytes)).data dmem_req(w).bits.uop.mem_cmd := hella_req.cmd dmem_req(w).bits.uop.mem_size := hella_req.size dmem_req(w).bits.uop.mem_signed := hella_req.signed dmem_req(w).bits.is_hella := true.B hella_paddr := exe_tlb_paddr(w) } .elsewhen (will_fire_hella_wakeup(w)) { assert(hella_state === h_replay) dmem_req(w).valid := true.B dmem_req(w).bits.addr := hella_paddr dmem_req(w).bits.data := (new freechips.rocketchip.rocket.StoreGen( hella_req.size, 0.U, hella_data.data, coreDataBytes)).data dmem_req(w).bits.uop.mem_cmd := hella_req.cmd dmem_req(w).bits.uop.mem_size := hella_req.size dmem_req(w).bits.uop.mem_signed := hella_req.signed dmem_req(w).bits.is_hella := true.B } //------------------------------------------------------------- // Write Addr into the LAQ/SAQ when (will_fire_load_incoming(w) \|\| will_fire_load_retry(w)) { val ldq_idx = Mux(will_fire_load_incoming(w), ldq_incoming_idx(w), ldq_retry_idx) ldq(ldq_idx).bits.addr.valid := true.B ldq(ldq_idx).bits.addr.bits := Mux(exe_tlb_miss(w), exe_tlb_vaddr(w), exe_tlb_paddr(w)) ldq(ldq_idx).bits.uop.pdst := exe_tlb_uop(w).pdst ldq(ldq_idx).bits.addr_is_virtual := exe_tlb_miss(w) ldq(ldq_idx).bits.addr_is_uncacheable := exe_tlb_uncacheable(w) && !exe_tlb_miss(w) assert(!(will_fire_load_incoming(w) && ldq_incoming_e(w).bits.addr.valid), "[lsu] Incoming load is overwriting a valid address") } when (will_fire_sta_incoming(w) \|\| will_fire_stad_incoming(w) \|\| will_fire_sta_retry(w)) { val stq_idx = Mux(will_fire_sta_incoming(w) \|\| will_fire_stad_incoming(w), stq_incoming_idx(w), stq_retry_idx) stq(stq_idx).bits.addr.valid := !pf_st(w) // Prevent AMOs from executing! stq(stq_idx).bits.addr.bits := Mux(exe_tlb_miss(w), exe_tlb_vaddr(w), exe_tlb_paddr(w)) stq(stq_idx).bits.uop.pdst := exe_tlb_uop(w).pdst // Needed for AMOs stq(stq_idx).bits.addr_is_virtual := exe_tlb_miss(w) assert(!(will_fire_sta_incoming(w) && stq_incoming_e(w).bits.addr.valid), "[lsu] Incoming store is overwriting a valid address") } //------------------------------------------------------------- // Write data into the STQ if (w == 0) io.core.fp_stdata.ready := !will_fire_std_incoming(w) && !will_fire_stad_incoming(w) val fp_stdata_fire = io.core.fp_stdata.fire && (w == 0).B when (will_fire_std_incoming(w) \|\| will_fire_stad_incoming(w) \|\| fp_stdata_fire) { val sidx = Mux(will_fire_std_incoming(w) \|\| will_fire_stad_incoming(w), stq_incoming_idx(w), io.core.fp_stdata.bits.uop.stq_idx) stq(sidx).bits.data.valid := true.B stq(sidx).bits.data.bits := Mux(will_fire_std_incoming(w) \|\| will_fire_stad_incoming(w), exe_req(w).bits.data, io.core.fp_stdata.bits.data) assert(!(stq(sidx).bits.data.valid), "[lsu] Incoming store is overwriting a valid data entry") } } val will_fire_stdf_incoming = io.core.fp_stdata.fire require (xLen >= fLen) // for correct SDQ size //------------------------------------------------------------- //------------------------------------------------------------- // Cache Access Cycle (Mem) //------------------------------------------------------------- //------------------------------------------------------------- // Note the DCache may not have accepted our request val exe_req_killed = widthMap(w => IsKilledByBranch(io.core.brupdate, exe_req(w).bits.uop)) val stdf_killed = IsKilledByBranch(io.core.brupdate, io.core.fp_stdata.bits.uop) val fired_load_incoming = widthMap(w => RegNext(will_fire_load_incoming(w) && !exe_req_killed(w))) val fired_stad_incoming = widthMap(w => RegNext(will_fire_stad_incoming(w) && !exe_req_killed(w))) val fired_sta_incoming = widthMap(w => RegNext(will_fire_sta_incoming (w) && !exe_req_killed(w))) val fired_std_incoming = widthMap(w => RegNext(will_fire_std_incoming (w) && !exe_req_killed(w))) val fired_stdf_incoming = RegNext(will_fire_stdf_incoming && !stdf_killed) val fired_sfence = RegNext(will_fire_sfence) val fired_release = RegNext(will_fire_release) val fired_load_retry = widthMap(w => RegNext(will_fire_load_retry (w) && !IsKilledByBranch(io.core.brupdate, ldq_retry_e.bits.uop))) val fired_sta_retry = widthMap(w => RegNext(will_fire_sta_retry (w) && !IsKilledByBranch(io.core.brupdate, stq_retry_e.bits.uop))) val fired_store_commit = RegNext(will_fire_store_commit) val fired_load_wakeup = widthMap(w => RegNext(will_fire_load_wakeup (w) && !IsKilledByBranch(io.core.brupdate, ldq_wakeup_e.bits.uop))) val fired_hella_incoming = RegNext(will_fire_hella_incoming) val fired_hella_wakeup = RegNext(will_fire_hella_wakeup) val mem_incoming_uop = RegNext(widthMap(w => UpdateBrMask(io.core.brupdate, exe_req(w).bits.uop))) val mem_ldq_incoming_e = RegNext(widthMap(w => UpdateBrMask(io.core.brupdate, ldq_incoming_e(w)))) val mem_stq_incoming_e = RegNext(widthMap(w => UpdateBrMask(io.core.brupdate, stq_incoming_e(w)))) val mem_ldq_wakeup_e = RegNext(UpdateBrMask(io.core.brupdate, ldq_wakeup_e)) val mem_ldq_retry_e = RegNext(UpdateBrMask(io.core.brupdate, ldq_retry_e)) val mem_stq_retry_e = RegNext(UpdateBrMask(io.core.brupdate, stq_retry_e)) val mem_ldq_e = widthMap(w => Mux(fired_load_incoming(w), mem_ldq_incoming_e(w), Mux(fired_load_retry (w), mem_ldq_retry_e, Mux(fired_load_wakeup (w), mem_ldq_wakeup_e, (0.U).asTypeOf(Valid(new LDQEntry)))))) val mem_stq_e = widthMap(w => Mux(fired_stad_incoming(w) \|\| fired_sta_incoming (w), mem_stq_incoming_e(w), Mux(fired_sta_retry (w), mem_stq_retry_e, (0.U).asTypeOf(Valid(new STQEntry))))) val mem_stdf_uop = RegNext(UpdateBrMask(io.core.brupdate, io.core.fp_stdata.bits.uop)) val mem_tlb_miss = RegNext(exe_tlb_miss) val mem_tlb_uncacheable = RegNext(exe_tlb_uncacheable) val mem_paddr = RegNext(widthMap(w => dmem_req(w).bits.addr)) // Task 1: Clr ROB busy bit val clr_bsy_valid = RegInit(widthMap(w => false.B)) val clr_bsy_rob_idx = Reg(Vec(memWidth, UInt(robAddrSz.W))) val clr_bsy_brmask = Reg(Vec(memWidth, UInt(maxBrCount.W))) for (w <- 0 until memWidth) { clr_bsy_valid (w) := false.B clr_bsy_rob_idx (w) := 0.U clr_bsy_brmask (w) := 0.U when (fired_stad_incoming(w)) { clr_bsy_valid (w) := mem_stq_incoming_e(w).valid && !mem_tlb_miss(w) && !mem_stq_incoming_e(w).bits.uop.is_amo && !IsKilledByBranch(io.core.brupdate, mem_stq_incoming_e(w).bits.uop) clr_bsy_rob_idx (w) := mem_stq_incoming_e(w).bits.uop.rob_idx clr_bsy_brmask (w) := GetNewBrMask(io.core.brupdate, mem_stq_incoming_e(w).bits.uop) } .elsewhen (fired_sta_incoming(w)) { clr_bsy_valid (w) := mem_stq_incoming_e(w).valid && mem_stq_incoming_e(w).bits.data.valid && !mem_tlb_miss(w) && !mem_stq_incoming_e(w).bits.uop.is_amo && !IsKilledByBranch(io.core.brupdate, mem_stq_incoming_e(w).bits.uop) clr_bsy_rob_idx (w) := mem_stq_incoming_e(w).bits.uop.rob_idx clr_bsy_brmask (w) := GetNewBrMask(io.core.brupdate, mem_stq_incoming_e(w).bits.uop) } .elsewhen (fired_std_incoming(w)) { clr_bsy_valid (w) := mem_stq_incoming_e(w).valid && mem_stq_incoming_e(w).bits.addr.valid && !mem_stq_incoming_e(w).bits.addr_is_virtual && !mem_stq_incoming_e(w).bits.uop.is_amo && !IsKilledByBranch(io.core.brupdate, mem_stq_incoming_e(w).bits.uop) clr_bsy_rob_idx (w) := mem_stq_incoming_e(w).bits.uop.rob_idx clr_bsy_brmask (w) := GetNewBrMask(io.core.brupdate, mem_stq_incoming_e(w).bits.uop) } .elsewhen (fired_sfence(w)) { clr_bsy_valid (w) := (w == 0).B // SFence proceeds down all paths, only allow one to clr the rob clr_bsy_rob_idx (w) := mem_incoming_uop(w).rob_idx clr_bsy_brmask (w) := GetNewBrMask(io.core.brupdate, mem_incoming_uop(w)) } .elsewhen (fired_sta_retry(w)) { clr_bsy_valid (w) := mem_stq_retry_e.valid && mem_stq_retry_e.bits.data.valid && !mem_tlb_miss(w) && !mem_stq_retry_e.bits.uop.is_amo && !IsKilledByBranch(io.core.brupdate, mem_stq_retry_e.bits.uop) clr_bsy_rob_idx (w) := mem_stq_retry_e.bits.uop.rob_idx clr_bsy_brmask (w) := GetNewBrMask(io.core.brupdate, mem_stq_retry_e.bits.uop) } io.core.clr_bsy(w).valid := clr_bsy_valid(w) && !IsKilledByBranch(io.core.brupdate, clr_bsy_brmask(w)) && !io.core.exception && !RegNext(io.core.exception) && !RegNext(RegNext(io.core.exception)) io.core.clr_bsy(w).bits := clr_bsy_rob_idx(w) } val stdf_clr_bsy_valid = RegInit(false.B) val stdf_clr_bsy_rob_idx = Reg(UInt(robAddrSz.W)) val stdf_clr_bsy_brmask = Reg(UInt(maxBrCount.W)) stdf_clr_bsy_valid := false.B stdf_clr_bsy_rob_idx := 0.U stdf_clr_bsy_brmask := 0.U when (fired_stdf_incoming) { val s_idx = mem_stdf_uop.stq_idx stdf_clr_bsy_valid := stq(s_idx).valid && stq(s_idx).bits.addr.valid && !stq(s_idx).bits.addr_is_virtual && !stq(s_idx).bits.uop.is_amo && !IsKilledByBranch(io.core.brupdate, mem_stdf_uop) stdf_clr_bsy_rob_idx := mem_stdf_uop.rob_idx stdf_clr_bsy_brmask := GetNewBrMask(io.core.brupdate, mem_stdf_uop) } io.core.clr_bsy(memWidth).valid := stdf_clr_bsy_valid && !IsKilledByBranch(io.core.brupdate, stdf_clr_bsy_brmask) && !io.core.exception && !RegNext(io.core.exception) && !RegNext(RegNext(io.core.exception)) io.core.clr_bsy(memWidth).bits := stdf_clr_bsy_rob_idx // Task 2: Do LD-LD. ST-LD searches for ordering failures // Do LD-ST search for forwarding opportunities // We have the opportunity to kill a request we sent last cycle. Use it wisely! // We translated a store last cycle val do_st_search = widthMap(w => (fired_stad_incoming(w) \|\| fired_sta_incoming(w) \|\| fired_sta_retry(w)) && !mem_tlb_miss(w)) // We translated a load last cycle val do_ld_search = widthMap(w => ((fired_load_incoming(w) \|\| fired_load_retry(w)) && !mem_tlb_miss(w)) \|\| fired_load_wakeup(w)) // We are making a local line visible to other harts val do_release_search = widthMap(w => fired_release(w)) // Store addrs don't go to memory yet, get it from the TLB response // Load wakeups don't go through TLB, get it through memory // Load incoming and load retries go through both val lcam_addr = widthMap(w => Mux(fired_stad_incoming(w) \|\| fired_sta_incoming(w) \|\| fired_sta_retry(w), RegNext(exe_tlb_paddr(w)), Mux(fired_release(w), RegNext(io.dmem.release.bits.address), mem_paddr(w)))) val lcam_uop = widthMap(w => Mux(do_st_search(w), mem_stq_e(w).bits.uop, Mux(do_ld_search(w), mem_ldq_e(w).bits.uop, NullMicroOp))) val lcam_mask = widthMap(w => GenByteMask(lcam_addr(w), lcam_uop(w).mem_size)) val lcam_st_dep_mask = widthMap(w => mem_ldq_e(w).bits.st_dep_mask) val lcam_is_release = widthMap(w => fired_release(w)) val lcam_ldq_idx = widthMap(w => Mux(fired_load_incoming(w), mem_incoming_uop(w).ldq_idx, Mux(fired_load_wakeup (w), RegNext(ldq_wakeup_idx), Mux(fired_load_retry (w), RegNext(ldq_retry_idx), 0.U)))) val lcam_stq_idx = widthMap(w => Mux(fired_stad_incoming(w) \|\| fired_sta_incoming (w), mem_incoming_uop(w).stq_idx, Mux(fired_sta_retry (w), RegNext(stq_retry_idx), 0.U))) val can_forward = WireInit(widthMap(w => Mux(fired_load_incoming(w) \|\| fired_load_retry(w), !mem_tlb_uncacheable(w), !ldq(lcam_ldq_idx(w)).bits.addr_is_uncacheable))) // Mask of stores which we conflict on address with val ldst_addr_matches = WireInit(widthMap(w => VecInit((0 until numStqEntries).map(x=>false.B)))) // Mask of stores which we can forward from val ldst_forward_matches = WireInit(widthMap(w => VecInit((0 until numStqEntries).map(x=>false.B)))) val failed_loads = WireInit(VecInit((0 until numLdqEntries).map(x=>false.B))) // Loads which we will report as failures (throws a mini-exception) val nacking_loads = WireInit(VecInit((0 until numLdqEntries).map(x=>false.B))) // Loads which are being nacked by dcache in the next stage val s1_executing_loads = RegNext(s0_executing_loads) val s1_set_execute = WireInit(s1_executing_loads) val mem_forward_valid = Wire(Vec(memWidth, Bool())) val mem_forward_ldq_idx = lcam_ldq_idx val mem_forward_ld_addr = lcam_addr val mem_forward_stq_idx = Wire(Vec(memWidth, UInt(log2Ceil(numStqEntries).W))) val wb_forward_valid = RegNext(mem_forward_valid) val wb_forward_ldq_idx = RegNext(mem_forward_ldq_idx) val wb_forward_ld_addr = RegNext(mem_forward_ld_addr) val wb_forward_stq_idx = RegNext(mem_forward_stq_idx) for (i <- 0 until numLdqEntries) { val l_valid = ldq(i).valid val l_bits = ldq(i).bits val l_addr = ldq(i).bits.addr.bits val l_mask = GenByteMask(l_addr, l_bits.uop.mem_size) val l_forwarders = widthMap(w => wb_forward_valid(w) && wb_forward_ldq_idx(w) === i.U) val l_is_forwarding = l_forwarders.reduce(_\|\|_) val l_forward_stq_idx = Mux(l_is_forwarding, Mux1H(l_forwarders, wb_forward_stq_idx), l_bits.forward_stq_idx) val block_addr_matches = widthMap(w => lcam_addr(w) >> blockOffBits === l_addr >> blockOffBits) val dword_addr_matches = widthMap(w => block_addr_matches(w) && lcam_addr(w)(blockOffBits-1,3) === l_addr(blockOffBits-1,3)) val mask_match = widthMap(w => (l_mask & lcam_mask(w)) === l_mask) val mask_overlap = widthMap(w => (l_mask & lcam_mask(w)).orR) // Searcher is a store for (w <- 0 until memWidth) { when (do_release_search(w) && l_valid && l_bits.addr.valid && block_addr_matches(w)) { // This load has been observed, so if a younger load to the same address has not // executed yet, this load must be squashed ldq(i).bits.observed := true.B } .elsewhen (do_st_search(w) && l_valid && l_bits.addr.valid && (l_bits.executed \|\| l_bits.succeeded \|\| l_is_forwarding) && !l_bits.addr_is_virtual && l_bits.st_dep_mask(lcam_stq_idx(w)) && dword_addr_matches(w) && mask_overlap(w)) { val forwarded_is_older = IsOlder(l_forward_stq_idx, lcam_stq_idx(w), l_bits.youngest_stq_idx) // We are older than this load, which overlapped us. when (!l_bits.forward_std_val \|\| // If the load wasn't forwarded, it definitely failed ((l_forward_stq_idx =/= lcam_stq_idx(w)) && forwarded_is_older)) { // If the load forwarded from us, we might be ok ldq(i).bits.order_fail := true.B failed_loads(i) := true.B } } .elsewhen (do_ld_search(w) && l_valid && l_bits.addr.valid && !l_bits.addr_is_virtual && dword_addr_matches(w) && mask_overlap(w)) { val searcher_is_older = IsOlder(lcam_ldq_idx(w), i.U, ldq_head) when (searcher_is_older) { when ((l_bits.executed \|\| l_bits.succeeded \|\| l_is_forwarding) && !s1_executing_loads(i) && // If the load is proceeding in parallel we don't need to kill it l_bits.observed) { // Its only a ordering failure if the cache line was observed between the younger load and us ldq(i).bits.order_fail := true.B failed_loads(i) := true.B } } .elsewhen (lcam_ldq_idx(w) =/= i.U) { // The load is older, and either it hasn't executed, it was nacked, or it is ignoring its response // we need to kill ourselves, and prevent forwarding val older_nacked = nacking_loads(i) \|\| RegNext(nacking_loads(i)) when (!(l_bits.executed \|\| l_bits.succeeded) \|\| older_nacked) { s1_set_execute(lcam_ldq_idx(w)) := false.B io.dmem.s1_kill(w) := RegNext(dmem_req_fire(w)) can_forward(w) := false.B } } } } } for (i <- 0 until numStqEntries) { val s_addr = stq(i).bits.addr.bits val s_uop = stq(i).bits.uop val dword_addr_matches = widthMap(w => ( stq(i).bits.addr.valid && !stq(i).bits.addr_is_virtual && (s_addr(corePAddrBits-1,3) === lcam_addr(w)(corePAddrBits-1,3)))) val write_mask = GenByteMask(s_addr, s_uop.mem_size) for (w <- 0 until memWidth) { when (do_ld_search(w) && stq(i).valid && lcam_st_dep_mask(w)(i)) { when (((lcam_mask(w) & write_mask) === lcam_mask(w)) && !s_uop.is_fence && !s_uop.is_amo && dword_addr_matches(w) && can_forward(w)) { ldst_addr_matches(w)(i) := true.B ldst_forward_matches(w)(i) := true.B io.dmem.s1_kill(w) := RegNext(dmem_req_fire(w)) s1_set_execute(lcam_ldq_idx(w)) := false.B } .elsewhen (((lcam_mask(w) & write_mask) =/= 0.U) && dword_addr_matches(w)) { ldst_addr_matches(w)(i) := true.B io.dmem.s1_kill(w) := RegNext(dmem_req_fire(w)) s1_set_execute(lcam_ldq_idx(w)) := false.B } .elsewhen (s_uop.is_fence \|\| s_uop.is_amo) { ldst_addr_matches(w)(i) := true.B io.dmem.s1_kill(w) := RegNext(dmem_req_fire(w)) s1_set_execute(lcam_ldq_idx(w)) := false.B } } } } // Set execute bit in LDQ for (i <- 0 until numLdqEntries) { when (s1_set_execute(i)) { ldq(i).bits.executed := true.B } } // Find the youngest store which the load is dependent on val forwarding_age_logic = Seq.fill(memWidth) { Module(new ForwardingAgeLogic(numStqEntries)) } for (w <- 0 until memWidth) { forwarding_age_logic(w).io.addr_matches := ldst_addr_matches(w).asUInt forwarding_age_logic(w).io.youngest_st_idx := lcam_uop(w).stq_idx } val forwarding_idx = widthMap(w => forwarding_age_logic(w).io.forwarding_idx) // Forward if st-ld forwarding is possible from the writemask and loadmask mem_forward_valid := widthMap(w => (ldst_forward_matches(w)(forwarding_idx(w)) && !IsKilledByBranch(io.core.brupdate, lcam_uop(w)) && !io.core.exception && !RegNext(io.core.exception))) mem_forward_stq_idx := forwarding_idx // Avoid deadlock with a 1-w LSU prioritizing load wakeups > store commits // On a 2W machine, load wakeups and store commits occupy separate pipelines, // so only add this logic for 1-w LSU if (memWidth == 1) { // Wakeups may repeatedly find a st->ld addr conflict and fail to forward, // repeated wakeups may block the store from ever committing // Disallow load wakeups 1 cycle after this happens to allow the stores to drain when (RegNext(ldst_addr_matches(0).reduce(_\|\|_) && !mem_forward_valid(0))) { block_load_wakeup := true.B } // If stores remain blocked for 15 cycles, block load wakeups to get a store through val store_blocked_counter = Reg(UInt(4.W)) when (will_fire_store_commit(0) \|\| !can_fire_store_commit(0)) { store_blocked_counter := 0.U } .elsewhen (can_fire_store_commit(0) && !will_fire_store_commit(0)) { store_blocked_counter := Mux(store_blocked_counter === 15.U, 15.U, store_blocked_counter + 1.U) } when (store_blocked_counter === 15.U) { block_load_wakeup := true.B } } // Task 3: Clr unsafe bit in ROB for succesful translations // Delay this a cycle to avoid going ahead of the exception broadcast // The unsafe bit is cleared on the first translation, so no need to fire for load wakeups for (w <- 0 until memWidth) { io.core.clr_unsafe(w).valid := RegNext((do_st_search(w) \|\| do_ld_search(w)) && !fired_load_wakeup(w)) && false.B io.core.clr_unsafe(w).bits := RegNext(lcam_uop(w).rob_idx) } // detect which loads get marked as failures, but broadcast to the ROB the oldest failing load // TODO encapsulate this in an age-based priority-encoder // val l_idx = AgePriorityEncoder((Vec(Vec.tabulate(numLdqEntries)(i => failed_loads(i) && i.U >= laq_head) // ++ failed_loads)).asUInt) val temp_bits = (VecInit(VecInit.tabulate(numLdqEntries)(i => failed_loads(i) && i.U >= ldq_head) ++ failed_loads)).asUInt val l_idx = PriorityEncoder(temp_bits) // one exception port, but multiple causes! // - 1) the incoming store-address finds a faulting load (it is by definition younger) // - 2) the incoming load or store address is excepting. It must be older and thus takes precedent. val r_xcpt_valid = RegInit(false.B) val r_xcpt = Reg(new Exception) val ld_xcpt_valid = failed_loads.reduce(_\|_) val ld_xcpt_uop = ldq(Mux(l_idx >= numLdqEntries.U, l_idx - numLdqEntries.U, l_idx)).bits.uop val use_mem_xcpt = (mem_xcpt_valid && IsOlder(mem_xcpt_uop.rob_idx, ld_xcpt_uop.rob_idx, io.core.rob_head_idx)) \|\| !ld_xcpt_valid val xcpt_uop = Mux(use_mem_xcpt, mem_xcpt_uop, ld_xcpt_uop) r_xcpt_valid := (ld_xcpt_valid \|\| mem_xcpt_valid) && !io.core.exception && !IsKilledByBranch(io.core.brupdate, xcpt_uop) r_xcpt.uop := xcpt_uop r_xcpt.uop.br_mask := GetNewBrMask(io.core.brupdate, xcpt_uop) r_xcpt.cause := Mux(use_mem_xcpt, mem_xcpt_cause, MINI_EXCEPTION_MEM_ORDERING) r_xcpt.badvaddr := mem_xcpt_vaddr // TODO is there another register we can use instead? io.core.lxcpt.valid := r_xcpt_valid && !io.core.exception && !IsKilledByBranch(io.core.brupdate, r_xcpt.uop) io.core.lxcpt.bits := r_xcpt // Task 4: Speculatively wakeup loads 1 cycle before they come back for (w <- 0 until memWidth) { io.core.spec_ld_wakeup(w).valid := enableFastLoadUse.B && fired_load_incoming(w) && !mem_incoming_uop(w).fp_val && mem_incoming_uop(w).pdst =/= 0.U io.core.spec_ld_wakeup(w).bits := mem_incoming_uop(w).pdst } //------------------------------------------------------------- //------------------------------------------------------------- // Writeback Cycle (St->Ld Forwarding Path) //------------------------------------------------------------- //------------------------------------------------------------- // Handle Memory Responses and nacks //---------------------------------- for (w <- 0 until memWidth) { io.core.exe(w).iresp.valid := false.B io.core.exe(w).iresp.bits := DontCare io.core.exe(w).fresp.valid := false.B io.core.exe(w).fresp.bits := DontCare } val dmem_resp_fired = WireInit(widthMap(w => false.B)) for (w <- 0 until memWidth) { // Handle nacks when (io.dmem.nack(w).valid) { // We have to re-execute this! when (io.dmem.nack(w).bits.is_hella) { assert(hella_state === h_wait \|\| hella_state === h_dead) } .elsewhen (io.dmem.nack(w).bits.uop.uses_ldq) { assert(ldq(io.dmem.nack(w).bits.uop.ldq_idx).bits.executed) ldq(io.dmem.nack(w).bits.uop.ldq_idx).bits.executed := false.B nacking_loads(io.dmem.nack(w).bits.uop.ldq_idx) := true.B } .otherwise { assert(io.dmem.nack(w).bits.uop.uses_stq) when (IsOlder(io.dmem.nack(w).bits.uop.stq_idx, stq_execute_head, stq_head)) { stq_execute_head := io.dmem.nack(w).bits.uop.stq_idx } } } // Handle the response when (io.dmem.resp(w).valid) { when (io.dmem.resp(w).bits.uop.uses_ldq) { assert(!io.dmem.resp(w).bits.is_hella) val ldq_idx = io.dmem.resp(w).bits.uop.ldq_idx val send_iresp = ldq(ldq_idx).bits.uop.dst_rtype === RT_FIX val send_fresp = ldq(ldq_idx).bits.uop.dst_rtype === RT_FLT io.core.exe(w).iresp.bits.uop := ldq(ldq_idx).bits.uop io.core.exe(w).fresp.bits.uop := ldq(ldq_idx).bits.uop io.core.exe(w).iresp.valid := send_iresp io.core.exe(w).iresp.bits.data := io.dmem.resp(w).bits.data io.core.exe(w).fresp.valid := send_fresp io.core.exe(w).fresp.bits.data := io.dmem.resp(w).bits.data assert(send_iresp ^ send_fresp) dmem_resp_fired(w) := true.B ldq(ldq_idx).bits.succeeded := io.core.exe(w).iresp.valid \|\| io.core.exe(w).fresp.valid ldq(ldq_idx).bits.debug_wb_data := io.dmem.resp(w).bits.data } .elsewhen (io.dmem.resp(w).bits.uop.uses_stq) { assert(!io.dmem.resp(w).bits.is_hella) stq(io.dmem.resp(w).bits.uop.stq_idx).bits.succeeded := true.B when (io.dmem.resp(w).bits.uop.is_amo) { dmem_resp_fired(w) := true.B io.core.exe(w).iresp.valid := true.B io.core.exe(w).iresp.bits.uop := stq(io.dmem.resp(w).bits.uop.stq_idx).bits.uop io.core.exe(w).iresp.bits.data := io.dmem.resp(w).bits.data stq(io.dmem.resp(w).bits.uop.stq_idx).bits.debug_wb_data := io.dmem.resp(w).bits.data } } } when (dmem_resp_fired(w) && wb_forward_valid(w)) { // Twiddle thumbs. Can't forward because dcache response takes precedence } .elsewhen (!dmem_resp_fired(w) && wb_forward_valid(w)) { val f_idx = wb_forward_ldq_idx(w) val forward_uop = ldq(f_idx).bits.uop val stq_e = stq(wb_forward_stq_idx(w)) val data_ready = stq_e.bits.data.valid val live = !IsKilledByBranch(io.core.brupdate, forward_uop) val storegen = new freechips.rocketchip.rocket.StoreGen( stq_e.bits.uop.mem_size, stq_e.bits.addr.bits, stq_e.bits.data.bits, coreDataBytes) val loadgen = new freechips.rocketchip.rocket.LoadGen( forward_uop.mem_size, forward_uop.mem_signed, wb_forward_ld_addr(w), storegen.data, false.B, coreDataBytes) io.core.exe(w).iresp.valid := (forward_uop.dst_rtype === RT_FIX) && data_ready && live io.core.exe(w).fresp.valid := (forward_uop.dst_rtype === RT_FLT) && data_ready && live io.core.exe(w).iresp.bits.uop := forward_uop io.core.exe(w).fresp.bits.uop := forward_uop io.core.exe(w).iresp.bits.data := loadgen.data io.core.exe(w).fresp.bits.data := loadgen.data when (data_ready && live) { ldq(f_idx).bits.succeeded := data_ready ldq(f_idx).bits.forward_std_val := true.B ldq(f_idx).bits.forward_stq_idx := wb_forward_stq_idx(w) ldq(f_idx).bits.debug_wb_data := loadgen.data } } } // Initially assume the speculative load wakeup failed io.core.ld_miss := RegNext(io.core.spec_ld_wakeup.map(_.valid).reduce(_\|\|_)) val spec_ld_succeed = widthMap(w => !RegNext(io.core.spec_ld_wakeup(w).valid) \|\| (io.core.exe(w).iresp.valid && io.core.exe(w).iresp.bits.uop.ldq_idx === RegNext(mem_incoming_uop(w).ldq_idx) ) ).reduce(_&&_) when (spec_ld_succeed) { io.core.ld_miss := false.B } //------------------------------------------------------------- // Kill speculated entries on branch mispredict //------------------------------------------------------------- //------------------------------------------------------------- // Kill stores val st_brkilled_mask = Wire(Vec(numStqEntries, Bool())) for (i <- 0 until numStqEntries) { st_brkilled_mask(i) := false.B when (stq(i).valid) { stq(i).bits.uop.br_mask := GetNewBrMask(io.core.brupdate, stq(i).bits.uop.br_mask) when (IsKilledByBranch(io.core.brupdate, stq(i).bits.uop)) { stq(i).valid := false.B stq(i).bits.addr.valid := false.B stq(i).bits.data.valid := false.B st_brkilled_mask(i) := true.B } } assert (!(IsKilledByBranch(io.core.brupdate, stq(i).bits.uop) && stq(i).valid && stq(i).bits.committed), "Branch is trying to clear a committed store.") } // Kill loads for (i <- 0 until numLdqEntries) { when (ldq(i).valid) { ldq(i).bits.uop.br_mask := GetNewBrMask(io.core.brupdate, ldq(i).bits.uop.br_mask) when (IsKilledByBranch(io.core.brupdate, ldq(i).bits.uop)) { ldq(i).valid := false.B ldq(i).bits.addr.valid := false.B } } } //------------------------------------------------------------- when (io.core.brupdate.b2.mispredict && !io.core.exception) { stq_tail := io.core.brupdate.b2.uop.stq_idx ldq_tail := io.core.brupdate.b2.uop.ldq_idx } //------------------------------------------------------------- //------------------------------------------------------------- // dequeue old entries on commit //------------------------------------------------------------- //------------------------------------------------------------- var temp_stq_commit_head = stq_commit_head var temp_ldq_head = ldq_head for (w <- 0 until coreWidth) { val commit_store = io.core.commit.valids(w) && io.core.commit.uops(w).uses_stq val commit_load = io.core.commit.valids(w) && io.core.commit.uops(w).uses_ldq val idx = Mux(commit_store, temp_stq_commit_head, temp_ldq_head) when (commit_store) { stq(idx).bits.committed := true.B } .elsewhen (commit_load) { assert (ldq(idx).valid, "[lsu] trying to commit an un-allocated load entry.") assert ((ldq(idx).bits.executed \|\| ldq(idx).bits.forward_std_val) && ldq(idx).bits.succeeded , "[lsu] trying to commit an un-executed load entry.") ldq(idx).valid := false.B ldq(idx).bits.addr.valid := false.B ldq(idx).bits.executed := false.B ldq(idx).bits.succeeded := false.B ldq(idx).bits.order_fail := false.B ldq(idx).bits.forward_std_val := false.B } if (MEMTRACE_PRINTF) { when (commit_store \|\| commit_load) { val uop = Mux(commit_store, stq(idx).bits.uop, ldq(idx).bits.uop) val addr = Mux(commit_store, stq(idx).bits.addr.bits, ldq(idx).bits.addr.bits) val stdata = Mux(commit_store, stq(idx).bits.data.bits, 0.U) val wbdata = Mux(commit_store, stq(idx).bits.debug_wb_data, ldq(idx).bits.debug_wb_data) printf("MT %x %x %x %x %x %x %x\n", io.core.tsc_reg, uop.uopc, uop.mem_cmd, uop.mem_size, addr, stdata, wbdata) } } temp_stq_commit_head = Mux(commit_store, WrapInc(temp_stq_commit_head, numStqEntries), temp_stq_commit_head) temp_ldq_head = Mux(commit_load, WrapInc(temp_ldq_head, numLdqEntries), temp_ldq_head) } stq_commit_head := temp_stq_commit_head ldq_head := temp_ldq_head // store has been committed AND successfully sent data to memory when (stq(stq_head).valid && stq(stq_head).bits.committed) { when (stq(stq_head).bits.uop.is_fence && !io.dmem.ordered) { io.dmem.force_order := true.B store_needs_order := true.B } clear_store := Mux(stq(stq_head).bits.uop.is_fence, io.dmem.ordered, stq(stq_head).bits.succeeded) } when (clear_store) { stq(stq_head).valid := false.B stq(stq_head).bits.addr.valid := false.B stq(stq_head).bits.data.valid := false.B stq(stq_head).bits.succeeded := false.B stq(stq_head).bits.committed := false.B stq_head := WrapInc(stq_head, numStqEntries) when (stq(stq_head).bits.uop.is_fence) { stq_execute_head := WrapInc(stq_execute_head, numStqEntries) } } // ----------------------- // Hellacache interface // We need to time things like a HellaCache would io.hellacache.req.ready := false.B io.hellacache.s2_nack := false.B io.hellacache.s2_xcpt := (0.U).asTypeOf(new rocket.HellaCacheExceptions) io.hellacache.resp.valid := false.B io.hellacache.store_pending := stq.map(_.valid).reduce(_\|\|_) when (hella_state === h_ready) { io.hellacache.req.ready := true.B when (io.hellacache.req.fire) { hella_req := io.hellacache.req.bits hella_state := h_s1 } } .elsewhen (hella_state === h_s1) { can_fire_hella_incoming(memWidth-1) := true.B hella_data := io.hellacache.s1_data hella_xcpt := dtlb.io.resp(memWidth-1) when (io.hellacache.s1_kill) { when (will_fire_hella_incoming(memWidth-1) && dmem_req_fire(memWidth-1)) { hella_state := h_dead } .otherwise { hella_state := h_ready } } .elsewhen (will_fire_hella_incoming(memWidth-1) && dmem_req_fire(memWidth-1)) { hella_state := h_s2 } .otherwise { hella_state := h_s2_nack } } .elsewhen (hella_state === h_s2_nack) { io.hellacache.s2_nack := true.B hella_state := h_ready } .elsewhen (hella_state === h_s2) { io.hellacache.s2_xcpt := hella_xcpt when (io.hellacache.s2_kill \|\| hella_xcpt.asUInt =/= 0.U) { hella_state := h_dead } .otherwise { hella_state := h_wait } } .elsewhen (hella_state === h_wait) { for (w <- 0 until memWidth) { when (io.dmem.resp(w).valid && io.dmem.resp(w).bits.is_hella) { hella_state := h_ready io.hellacache.resp.valid := true.B io.hellacache.resp.bits.addr := hella_req.addr io.hellacache.resp.bits.tag := hella_req.tag io.hellacache.resp.bits.cmd := hella_req.cmd io.hellacache.resp.bits.signed := hella_req.signed io.hellacache.resp.bits.size := hella_req.size io.hellacache.resp.bits.data := io.dmem.resp(w).bits.data } .elsewhen (io.dmem.nack(w).valid && io.dmem.nack(w).bits.is_hella) { hella_state := h_replay } } } .elsewhen (hella_state === h_replay) { can_fire_hella_wakeup(memWidth-1) := true.B when (will_fire_hella_wakeup(memWidth-1) && dmem_req_fire(memWidth-1)) { hella_state := h_wait } } .elsewhen (hella_state === h_dead) { for (w <- 0 until memWidth) { when (io.dmem.resp(w).valid && io.dmem.resp(w).bits.is_hella) { hella_state := h_ready } } } //------------------------------------------------------------- // Exception / Reset // for the live_store_mask, need to kill stores that haven't been committed val st_exc_killed_mask = WireInit(VecInit((0 until numStqEntries).map(x=>false.B))) when (reset.asBool \|\| io.core.exception) { ldq_head := 0.U ldq_tail := 0.U when (reset.asBool) { stq_head := 0.U stq_tail := 0.U stq_commit_head := 0.U stq_execute_head := 0.U for (i <- 0 until numStqEntries) { stq(i).valid := false.B stq(i).bits.addr.valid := false.B stq(i).bits.data.valid := false.B stq(i).bits.uop := NullMicroOp } } .otherwise // exception { stq_tail := stq_commit_head for (i <- 0 until numStqEntries) { when (!stq(i).bits.committed && !stq(i).bits.succeeded) { stq(i).valid := false.B stq(i).bits.addr.valid := false.B stq(i).bits.data.valid := false.B st_exc_killed_mask(i) := true.B } } } for (i <- 0 until numLdqEntries) { ldq(i).valid := false.B ldq(i).bits.addr.valid := false.B ldq(i).bits.executed := false.B } } //------------------------------------------------------------- // Live Store Mask // track a bit-array of stores that are alive // (could maybe be re-produced from the stq_head/stq_tail, but need to know include spec_killed entries) // TODO is this the most efficient way to compute the live store mask? live_store_mask := next_live_store_mask & ~(st_brkilled_mask.asUInt) & ~(st_exc_killed_mask.asUInt) } / * Object to take an address and generate an 8-bit mask of which bytes within a * double-word. / object GenByteMask { def apply(addr: UInt, size: UInt): UInt = { val mask = Wire(UInt(8.W)) mask := MuxCase(255.U(8.W), Array( (size === 0.U) -> (1.U(8.W) << addr(2,0)), (size === 1.U) -> (3.U(8.W) << (addr(2,1) << 1.U)), (size === 2.U) -> Mux(addr(2), 240.U(8.W), 15.U(8.W)), (size === 3.U) -> 255.U(8.W))) mask } } /* * ... / class ForwardingAgeLogic(num_entries: Int)(implicit p: Parameters) extends BoomModule()(p) { val io = IO(new Bundle { val addr_matches = Input(UInt(num_entries.W)) // bit vector of addresses that match // between the load and the SAQ val youngest_st_idx = Input(UInt(stqAddrSz.W)) // needed to get "age" val forwarding_val = Output(Bool()) val forwarding_idx = Output(UInt(stqAddrSz.W)) }) // generating mask that zeroes out anything younger than tail val age_mask = Wire(Vec(num_entries, Bool())) for (i <- 0 until num_entries) { age_mask(i) := true.B when (i.U >= io.youngest_st_idx) // currently the tail points PAST last store, so use >= { age_mask(i) := false.B } } // Priority encoder with moving tail: double length val matches = Wire(UInt((2num_entries).W)) matches := Cat(io.addr_matches & age_mask.asUInt, io.addr_matches) val found_match = Wire(Bool()) found_match := false.B io.forwarding_idx := 0.U // look for youngest, approach from the oldest side, let the last one found stick for (i <- 0 until (2num_entries)) { when (matches(i)) { found_match := true.B io.forwarding_idx := (i % num_entries).U } } io.forwarding_val := found_match } File util.scala: //*************************************************************************** // Copyright (c) 2015 - 2019, The Regents of the University of California (Regents). // All Rights Reserved. See LICENSE and LICENSE.SiFive for license details. //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ // Utility Functions //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ package boom.v3.util import chisel3._ import chisel3.util._ import freechips.rocketchip.rocket.Instructions._ import freechips.rocketchip.rocket._ import freechips.rocketchip.util.{Str} import org.chipsalliance.cde.config.{Parameters} import freechips.rocketchip.tile.{TileKey} import boom.v3.common.{MicroOp} import boom.v3.exu.{BrUpdateInfo} / * Object to XOR fold a input register of fullLength into a compressedLength. / object Fold { def apply(input: UInt, compressedLength: Int, fullLength: Int): UInt = { val clen = compressedLength val hlen = fullLength if (hlen <= clen) { input } else { var res = 0.U(clen.W) var remaining = input.asUInt for (i <- 0 to hlen-1 by clen) { val len = if (i + clen > hlen ) (hlen - i) else clen require(len > 0) res = res(clen-1,0) ^ remaining(len-1,0) remaining = remaining >> len.U } res } } } /* * Object to check if MicroOp was killed due to a branch mispredict. * Uses "Fast" branch masks / object IsKilledByBranch { def apply(brupdate: BrUpdateInfo, uop: MicroOp): Bool = { return maskMatch(brupdate.b1.mispredict_mask, uop.br_mask) } def apply(brupdate: BrUpdateInfo, uop_mask: UInt): Bool = { return maskMatch(brupdate.b1.mispredict_mask, uop_mask) } } /* * Object to return new MicroOp with a new BR mask given a MicroOp mask * and old BR mask. / object GetNewUopAndBrMask { def apply(uop: MicroOp, brupdate: BrUpdateInfo) (implicit p: Parameters): MicroOp = { val newuop = WireInit(uop) newuop.br_mask := uop.br_mask & ~brupdate.b1.resolve_mask newuop } } /* * Object to return a BR mask given a MicroOp mask and old BR mask. / object GetNewBrMask { def apply(brupdate: BrUpdateInfo, uop: MicroOp): UInt = { return uop.br_mask & ~brupdate.b1.resolve_mask } def apply(brupdate: BrUpdateInfo, br_mask: UInt): UInt = { return br_mask & ~brupdate.b1.resolve_mask } } object UpdateBrMask { def apply(brupdate: BrUpdateInfo, uop: MicroOp): MicroOp = { val out = WireInit(uop) out.br_mask := GetNewBrMask(brupdate, uop) out } def apply[T <: boom.v3.common.HasBoomUOP](brupdate: BrUpdateInfo, bundle: T): T = { val out = WireInit(bundle) out.uop.br_mask := GetNewBrMask(brupdate, bundle.uop.br_mask) out } def apply[T <: boom.v3.common.HasBoomUOP](brupdate: BrUpdateInfo, bundle: Valid[T]): Valid[T] = { val out = WireInit(bundle) out.bits.uop.br_mask := GetNewBrMask(brupdate, bundle.bits.uop.br_mask) out.valid := bundle.valid && !IsKilledByBranch(brupdate, bundle.bits.uop.br_mask) out } } /* * Object to check if at least 1 bit matches in two masks / object maskMatch { def apply(msk1: UInt, msk2: UInt): Bool = (msk1 & msk2) =/= 0.U } /* * Object to clear one bit in a mask given an index / object clearMaskBit { def apply(msk: UInt, idx: UInt): UInt = (msk & ~(1.U << idx))(msk.getWidth-1, 0) } /* * Object to shift a register over by one bit and concat a new one / object PerformShiftRegister { def apply(reg_val: UInt, new_bit: Bool): UInt = { reg_val := Cat(reg_val(reg_val.getWidth-1, 0).asUInt, new_bit.asUInt).asUInt reg_val } } /* * Object to shift a register over by one bit, wrapping the top bit around to the bottom * (XOR'ed with a new-bit), and evicting a bit at index HLEN. * This is used to simulate a longer HLEN-width shift register that is folded * down to a compressed CLEN. / object PerformCircularShiftRegister { def apply(csr: UInt, new_bit: Bool, evict_bit: Bool, hlen: Int, clen: Int): UInt = { val carry = csr(clen-1) val newval = Cat(csr, new_bit ^ carry) ^ (evict_bit << (hlen % clen).U) newval } } /* * Object to increment an input value, wrapping it if * necessary. / object WrapAdd { // "n" is the number of increments, so we wrap at n-1. def apply(value: UInt, amt: UInt, n: Int): UInt = { if (isPow2(n)) { (value + amt)(log2Ceil(n)-1,0) } else { val sum = Cat(0.U(1.W), value) + Cat(0.U(1.W), amt) Mux(sum >= n.U, sum - n.U, sum) } } } /* * Object to decrement an input value, wrapping it if * necessary. / object WrapSub { // "n" is the number of increments, so we wrap to n-1. def apply(value: UInt, amt: Int, n: Int): UInt = { if (isPow2(n)) { (value - amt.U)(log2Ceil(n)-1,0) } else { val v = Cat(0.U(1.W), value) val b = Cat(0.U(1.W), amt.U) Mux(value >= amt.U, value - amt.U, n.U - amt.U + value) } } } /* * Object to increment an input value, wrapping it if * necessary. / object WrapInc { // "n" is the number of increments, so we wrap at n-1. def apply(value: UInt, n: Int): UInt = { if (isPow2(n)) { (value + 1.U)(log2Ceil(n)-1,0) } else { val wrap = (value === (n-1).U) Mux(wrap, 0.U, value + 1.U) } } } /* * Object to decrement an input value, wrapping it if * necessary. / object WrapDec { // "n" is the number of increments, so we wrap at n-1. def apply(value: UInt, n: Int): UInt = { if (isPow2(n)) { (value - 1.U)(log2Ceil(n)-1,0) } else { val wrap = (value === 0.U) Mux(wrap, (n-1).U, value - 1.U) } } } /* * Object to mask off lower bits of a PC to align to a "b" * Byte boundary. / object AlignPCToBoundary { def apply(pc: UInt, b: Int): UInt = { // Invert for scenario where pc longer than b // (which would clear all bits above size(b)). ~(~pc \| (b-1).U) } } /* * Object to rotate a signal left by one / object RotateL1 { def apply(signal: UInt): UInt = { val w = signal.getWidth val out = Cat(signal(w-2,0), signal(w-1)) return out } } /* * Object to sext a value to a particular length. / object Sext { def apply(x: UInt, length: Int): UInt = { if (x.getWidth == length) return x else return Cat(Fill(length-x.getWidth, x(x.getWidth-1)), x) } } /* * Object to translate from BOOM's special "packed immediate" to a 32b signed immediate * Asking for U-type gives it shifted up 12 bits. / object ImmGen { import boom.v3.common.{LONGEST_IMM_SZ, IS_B, IS_I, IS_J, IS_S, IS_U} def apply(ip: UInt, isel: UInt): SInt = { val sign = ip(LONGEST_IMM_SZ-1).asSInt val i30_20 = Mux(isel === IS_U, ip(18,8).asSInt, sign) val i19_12 = Mux(isel === IS_U \|\| isel === IS_J, ip(7,0).asSInt, sign) val i11 = Mux(isel === IS_U, 0.S, Mux(isel === IS_J \|\| isel === IS_B, ip(8).asSInt, sign)) val i10_5 = Mux(isel === IS_U, 0.S, ip(18,14).asSInt) val i4_1 = Mux(isel === IS_U, 0.S, ip(13,9).asSInt) val i0 = Mux(isel === IS_S \|\| isel === IS_I, ip(8).asSInt, 0.S) return Cat(sign, i30_20, i19_12, i11, i10_5, i4_1, i0).asSInt } } /* * Object to get the FP rounding mode out of a packed immediate. / object ImmGenRm { def apply(ip: UInt): UInt = { return ip(2,0) } } /* * Object to get the FP function fype from a packed immediate. * Note: only works if !(IS_B or IS_S) / object ImmGenTyp { def apply(ip: UInt): UInt = { return ip(9,8) } } /* * Object to see if an instruction is a JALR. / object DebugIsJALR { def apply(inst: UInt): Bool = { // TODO Chisel not sure why this won't compile // val is_jalr = rocket.DecodeLogic(inst, List(Bool(false)), // Array( // JALR -> Bool(true))) inst(6,0) === "b1100111".U } } /* * Object to take an instruction and output its branch or jal target. Only used * for a debug assert (no where else would we jump straight from instruction * bits to a target). / object DebugGetBJImm { def apply(inst: UInt): UInt = { // TODO Chisel not sure why this won't compile //val csignals = //rocket.DecodeLogic(inst, // List(Bool(false), Bool(false)), // Array( // BEQ -> List(Bool(true ), Bool(false)), // BNE -> List(Bool(true ), Bool(false)), // BGE -> List(Bool(true ), Bool(false)), // BGEU -> List(Bool(true ), Bool(false)), // BLT -> List(Bool(true ), Bool(false)), // BLTU -> List(Bool(true ), Bool(false)) // )) //val is_br :: nothing :: Nil = csignals val is_br = (inst(6,0) === "b1100011".U) val br_targ = Cat(Fill(12, inst(31)), Fill(8,inst(31)), inst(7), inst(30,25), inst(11,8), 0.U(1.W)) val jal_targ= Cat(Fill(12, inst(31)), inst(19,12), inst(20), inst(30,25), inst(24,21), 0.U(1.W)) Mux(is_br, br_targ, jal_targ) } } /* * Object to return the lowest bit position after the head. / object AgePriorityEncoder { def apply(in: Seq[Bool], head: UInt): UInt = { val n = in.size val width = log2Ceil(in.size) val n_padded = 1 << width val temp_vec = (0 until n_padded).map(i => if (i < n) in(i) && i.U >= head else false.B) ++ in val idx = PriorityEncoder(temp_vec) idx(width-1, 0) //discard msb } } /* * Object to determine whether queue * index i0 is older than index i1. / object IsOlder { def apply(i0: UInt, i1: UInt, head: UInt) = ((i0 < i1) ^ (i0 < head) ^ (i1 < head)) } /* * Set all bits at or below the highest order '1'. / object MaskLower { def apply(in: UInt) = { val n = in.getWidth (0 until n).map(i => in >> i.U).reduce(_\|_) } } /* * Set all bits at or above the lowest order '1'. / object MaskUpper { def apply(in: UInt) = { val n = in.getWidth (0 until n).map(i => (in << i.U)(n-1,0)).reduce(_\|_) } } /* * Transpose a matrix of Chisel Vecs. / object Transpose { def apply[T <: chisel3.Data](in: Vec[Vec[T]]) = { val n = in(0).size VecInit((0 until n).map(i => VecInit(in.map(row => row(i))))) } } /* * N-wide one-hot priority encoder. / object SelectFirstN { def apply(in: UInt, n: Int) = { val sels = Wire(Vec(n, UInt(in.getWidth.W))) var mask = in for (i <- 0 until n) { sels(i) := PriorityEncoderOH(mask) mask = mask & ~sels(i) } sels } } /* * Connect the first k of n valid input interfaces to k output interfaces. / class Compactor[T <: chisel3.Data](n: Int, k: Int, gen: T) extends Module { require(n >= k) val io = IO(new Bundle { val in = Vec(n, Flipped(DecoupledIO(gen))) val out = Vec(k, DecoupledIO(gen)) }) if (n == k) { io.out <> io.in } else { val counts = io.in.map(_.valid).scanLeft(1.U(k.W)) ((c,e) => Mux(e, (c<<1)(k-1,0), c)) val sels = Transpose(VecInit(counts map (c => VecInit(c.asBools)))) map (col => (col zip io.in.map(_.valid)) map {case (c,v) => c && v}) val in_readys = counts map (row => (row.asBools zip io.out.map(_.ready)) map {case (c,r) => c && r} reduce (_\|\|_)) val out_valids = sels map (col => col.reduce(_\|\|_)) val out_data = sels map (s => Mux1H(s, io.in.map(_.bits))) in_readys zip io.in foreach {case (r,i) => i.ready := r} out_valids zip out_data zip io.out foreach {case ((v,d),o) => o.valid := v; o.bits := d} } } /* * Create a queue that can be killed with a branch kill signal. * Assumption: enq.valid only high if not killed by branch (so don't check IsKilled on io.enq). / class BranchKillableQueue[T <: boom.v3.common.HasBoomUOP](gen: T, entries: Int, flush_fn: boom.v3.common.MicroOp => Bool = u => true.B, flow: Boolean = true) (implicit p: org.chipsalliance.cde.config.Parameters) extends boom.v3.common.BoomModule()(p) with boom.v3.common.HasBoomCoreParameters { val io = IO(new Bundle { val enq = Flipped(Decoupled(gen)) val deq = Decoupled(gen) val brupdate = Input(new BrUpdateInfo()) val flush = Input(Bool()) val empty = Output(Bool()) val count = Output(UInt(log2Ceil(entries).W)) }) val ram = Mem(entries, gen) val valids = RegInit(VecInit(Seq.fill(entries) {false.B})) val uops = Reg(Vec(entries, new MicroOp)) val enq_ptr = Counter(entries) val deq_ptr = Counter(entries) val maybe_full = RegInit(false.B) val ptr_match = enq_ptr.value === deq_ptr.value io.empty := ptr_match && !maybe_full val full = ptr_match && maybe_full val do_enq = WireInit(io.enq.fire) val do_deq = WireInit((io.deq.ready \|\| !valids(deq_ptr.value)) && !io.empty) for (i <- 0 until entries) { val mask = uops(i).br_mask val uop = uops(i) valids(i) := valids(i) && !IsKilledByBranch(io.brupdate, mask) && !(io.flush && flush_fn(uop)) when (valids(i)) { uops(i).br_mask := GetNewBrMask(io.brupdate, mask) } } when (do_enq) { ram(enq_ptr.value) := io.enq.bits valids(enq_ptr.value) := true.B //!IsKilledByBranch(io.brupdate, io.enq.bits.uop) uops(enq_ptr.value) := io.enq.bits.uop uops(enq_ptr.value).br_mask := GetNewBrMask(io.brupdate, io.enq.bits.uop) enq_ptr.inc() } when (do_deq) { valids(deq_ptr.value) := false.B deq_ptr.inc() } when (do_enq =/= do_deq) { maybe_full := do_enq } io.enq.ready := !full val out = Wire(gen) out := ram(deq_ptr.value) out.uop := uops(deq_ptr.value) io.deq.valid := !io.empty && valids(deq_ptr.value) && !IsKilledByBranch(io.brupdate, out.uop) && !(io.flush && flush_fn(out.uop)) io.deq.bits := out io.deq.bits.uop.br_mask := GetNewBrMask(io.brupdate, out.uop) // For flow queue behavior. if (flow) { when (io.empty) { io.deq.valid := io.enq.valid //&& !IsKilledByBranch(io.brupdate, io.enq.bits.uop) io.deq.bits := io.enq.bits io.deq.bits.uop.br_mask := GetNewBrMask(io.brupdate, io.enq.bits.uop) do_deq := false.B when (io.deq.ready) { do_enq := false.B } } } private val ptr_diff = enq_ptr.value - deq_ptr.value if (isPow2(entries)) { io.count := Cat(maybe_full && ptr_match, ptr_diff) } else { io.count := Mux(ptr_match, Mux(maybe_full, entries.asUInt, 0.U), Mux(deq_ptr.value > enq_ptr.value, entries.asUInt + ptr_diff, ptr_diff)) } } // ------------------------------------------ // Printf helper functions // ------------------------------------------ object BoolToChar { /* * Take in a Chisel Bool and convert it into a Str * based on the Chars given * * @param c_bool Chisel Bool * @param trueChar Scala Char if bool is true * @param falseChar Scala Char if bool is false * @return UInt ASCII Char for "trueChar" or "falseChar" / def apply(c_bool: Bool, trueChar: Char, falseChar: Char = '-'): UInt = { Mux(c_bool, Str(trueChar), Str(falseChar)) } } object CfiTypeToChars { /* * Get a Vec of Strs that can be used for printing * * @param cfi_type specific cfi type * @return Vec of Strs (must be indexed to get specific char) / def apply(cfi_type: UInt) = { val strings = Seq("----", "BR ", "JAL ", "JALR") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(cfi_type) } } object BpdTypeToChars { /* * Get a Vec of Strs that can be used for printing * * @param bpd_type specific bpd type * @return Vec of Strs (must be indexed to get specific char) / def apply(bpd_type: UInt) = { val strings = Seq("BR ", "JUMP", "----", "RET ", "----", "CALL", "----", "----") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(bpd_type) } } object RobTypeToChars { /* * Get a Vec of Strs that can be used for printing * * @param rob_type specific rob type * @return Vec of Strs (must be indexed to get specific char) / def apply(rob_type: UInt) = { val strings = Seq("RST", "NML", "RBK", " WT") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(rob_type) } } object XRegToChars { /* * Get a Vec of Strs that can be used for printing * * @param xreg specific register number * @return Vec of Strs (must be indexed to get specific char) / def apply(xreg: UInt) = { val strings = Seq(" x0", " ra", " sp", " gp", " tp", " t0", " t1", " t2", " s0", " s1", " a0", " a1", " a2", " a3", " a4", " a5", " a6", " a7", " s2", " s3", " s4", " s5", " s6", " s7", " s8", " s9", "s10", "s11", " t3", " t4", " t5", " t6") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(xreg) } } object FPRegToChars { /* * Get a Vec of Strs that can be used for printing * * @param fpreg specific register number * @return Vec of Strs (must be indexed to get specific char) / def apply(fpreg: UInt) = { val strings = Seq(" ft0", " ft1", " ft2", " ft3", " ft4", " ft5", " ft6", " ft7", " fs0", " fs1", " fa0", " fa1", " fa2", " fa3", " fa4", " fa5", " fa6", " fa7", " fs2", " fs3", " fs4", " fs5", " fs6", " fs7", " fs8", " fs9", "fs10", "fs11", " ft8", " ft9", "ft10", "ft11") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(fpreg) } } object BoomCoreStringPrefix { /* * Add prefix to BOOM strings (currently only adds the hartId) * * @param strs list of strings * @return String combining the list with the prefix per line / def apply(strs: String)(implicit p: Parameters) = { val prefix = "[C" + s"${p(TileKey).tileId}" + "] " strs.map(str => prefix + str + "\n").mkString("") } } File consts.scala: //**************************************************************************** // Copyright (c) 2011 - 2018, The Regents of the University of California (Regents). // All Rights Reserved. See LICENSE and LICENSE.SiFive for license details. //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ // RISCV Processor Constants //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ package boom.v3.common.constants import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util.Str import freechips.rocketchip.rocket.RVCExpander / * Mixin for issue queue types / trait IQType { val IQT_SZ = 3 val IQT_INT = 1.U(IQT_SZ.W) val IQT_MEM = 2.U(IQT_SZ.W) val IQT_FP = 4.U(IQT_SZ.W) val IQT_MFP = 6.U(IQT_SZ.W) } /* * Mixin for scalar operation constants / trait ScalarOpConstants { val X = BitPat("b?") val Y = BitPat("b1") val N = BitPat("b0") //********************************* // Extra Constants // Which branch predictor predicted us val BSRC_SZ = 2 val BSRC_1 = 0.U(BSRC_SZ.W) // 1-cycle branch pred val BSRC_2 = 1.U(BSRC_SZ.W) // 2-cycle branch pred val BSRC_3 = 2.U(BSRC_SZ.W) // 3-cycle branch pred val BSRC_C = 3.U(BSRC_SZ.W) // core branch resolution //******************************** // Control Signals // CFI types val CFI_SZ = 3 val CFI_X = 0.U(CFI_SZ.W) // Not a CFI instruction val CFI_BR = 1.U(CFI_SZ.W) // Branch val CFI_JAL = 2.U(CFI_SZ.W) // JAL val CFI_JALR = 3.U(CFI_SZ.W) // JALR // PC Select Signal val PC_PLUS4 = 0.U(2.W) // PC + 4 val PC_BRJMP = 1.U(2.W) // brjmp_target val PC_JALR = 2.U(2.W) // jump_reg_target // Branch Type val BR_N = 0.U(4.W) // Next val BR_NE = 1.U(4.W) // Branch on NotEqual val BR_EQ = 2.U(4.W) // Branch on Equal val BR_GE = 3.U(4.W) // Branch on Greater/Equal val BR_GEU = 4.U(4.W) // Branch on Greater/Equal Unsigned val BR_LT = 5.U(4.W) // Branch on Less Than val BR_LTU = 6.U(4.W) // Branch on Less Than Unsigned val BR_J = 7.U(4.W) // Jump val BR_JR = 8.U(4.W) // Jump Register // RS1 Operand Select Signal val OP1_RS1 = 0.U(2.W) // Register Source #1 val OP1_ZERO= 1.U(2.W) val OP1_PC = 2.U(2.W) val OP1_X = BitPat("b??") // RS2 Operand Select Signal val OP2_RS2 = 0.U(3.W) // Register Source #2 val OP2_IMM = 1.U(3.W) // immediate val OP2_ZERO= 2.U(3.W) // constant 0 val OP2_NEXT= 3.U(3.W) // constant 2/4 (for PC+2/4) val OP2_IMMC= 4.U(3.W) // for CSR imm found in RS1 val OP2_X = BitPat("b???") // Register File Write Enable Signal val REN_0 = false.B val REN_1 = true.B // Is 32b Word or 64b Doubldword? val SZ_DW = 1 val DW_X = true.B // Bool(xLen==64) val DW_32 = false.B val DW_64 = true.B val DW_XPR = true.B // Bool(xLen==64) // Memory Enable Signal val MEN_0 = false.B val MEN_1 = true.B val MEN_X = false.B // Immediate Extend Select val IS_I = 0.U(3.W) // I-Type (LD,ALU) val IS_S = 1.U(3.W) // S-Type (ST) val IS_B = 2.U(3.W) // SB-Type (BR) val IS_U = 3.U(3.W) // U-Type (LUI/AUIPC) val IS_J = 4.U(3.W) // UJ-Type (J/JAL) val IS_X = BitPat("b???") // Decode Stage Control Signals val RT_FIX = 0.U(2.W) val RT_FLT = 1.U(2.W) val RT_PAS = 3.U(2.W) // pass-through (prs1 := lrs1, etc) val RT_X = 2.U(2.W) // not-a-register (but shouldn't get a busy-bit, etc.) // TODO rename RT_NAR // Micro-op opcodes // TODO change micro-op opcodes into using enum val UOPC_SZ = 7 val uopX = BitPat.dontCare(UOPC_SZ) val uopNOP = 0.U(UOPC_SZ.W) val uopLD = 1.U(UOPC_SZ.W) val uopSTA = 2.U(UOPC_SZ.W) // store address generation val uopSTD = 3.U(UOPC_SZ.W) // store data generation val uopLUI = 4.U(UOPC_SZ.W) val uopADDI = 5.U(UOPC_SZ.W) val uopANDI = 6.U(UOPC_SZ.W) val uopORI = 7.U(UOPC_SZ.W) val uopXORI = 8.U(UOPC_SZ.W) val uopSLTI = 9.U(UOPC_SZ.W) val uopSLTIU= 10.U(UOPC_SZ.W) val uopSLLI = 11.U(UOPC_SZ.W) val uopSRAI = 12.U(UOPC_SZ.W) val uopSRLI = 13.U(UOPC_SZ.W) val uopSLL = 14.U(UOPC_SZ.W) val uopADD = 15.U(UOPC_SZ.W) val uopSUB = 16.U(UOPC_SZ.W) val uopSLT = 17.U(UOPC_SZ.W) val uopSLTU = 18.U(UOPC_SZ.W) val uopAND = 19.U(UOPC_SZ.W) val uopOR = 20.U(UOPC_SZ.W) val uopXOR = 21.U(UOPC_SZ.W) val uopSRA = 22.U(UOPC_SZ.W) val uopSRL = 23.U(UOPC_SZ.W) val uopBEQ = 24.U(UOPC_SZ.W) val uopBNE = 25.U(UOPC_SZ.W) val uopBGE = 26.U(UOPC_SZ.W) val uopBGEU = 27.U(UOPC_SZ.W) val uopBLT = 28.U(UOPC_SZ.W) val uopBLTU = 29.U(UOPC_SZ.W) val uopCSRRW= 30.U(UOPC_SZ.W) val uopCSRRS= 31.U(UOPC_SZ.W) val uopCSRRC= 32.U(UOPC_SZ.W) val uopCSRRWI=33.U(UOPC_SZ.W) val uopCSRRSI=34.U(UOPC_SZ.W) val uopCSRRCI=35.U(UOPC_SZ.W) val uopJ = 36.U(UOPC_SZ.W) val uopJAL = 37.U(UOPC_SZ.W) val uopJALR = 38.U(UOPC_SZ.W) val uopAUIPC= 39.U(UOPC_SZ.W) //val uopSRET = 40.U(UOPC_SZ.W) val uopCFLSH= 41.U(UOPC_SZ.W) val uopFENCE= 42.U(UOPC_SZ.W) val uopADDIW= 43.U(UOPC_SZ.W) val uopADDW = 44.U(UOPC_SZ.W) val uopSUBW = 45.U(UOPC_SZ.W) val uopSLLIW= 46.U(UOPC_SZ.W) val uopSLLW = 47.U(UOPC_SZ.W) val uopSRAIW= 48.U(UOPC_SZ.W) val uopSRAW = 49.U(UOPC_SZ.W) val uopSRLIW= 50.U(UOPC_SZ.W) val uopSRLW = 51.U(UOPC_SZ.W) val uopMUL = 52.U(UOPC_SZ.W) val uopMULH = 53.U(UOPC_SZ.W) val uopMULHU= 54.U(UOPC_SZ.W) val uopMULHSU=55.U(UOPC_SZ.W) val uopMULW = 56.U(UOPC_SZ.W) val uopDIV = 57.U(UOPC_SZ.W) val uopDIVU = 58.U(UOPC_SZ.W) val uopREM = 59.U(UOPC_SZ.W) val uopREMU = 60.U(UOPC_SZ.W) val uopDIVW = 61.U(UOPC_SZ.W) val uopDIVUW= 62.U(UOPC_SZ.W) val uopREMW = 63.U(UOPC_SZ.W) val uopREMUW= 64.U(UOPC_SZ.W) val uopFENCEI = 65.U(UOPC_SZ.W) // = 66.U(UOPC_SZ.W) val uopAMO_AG = 67.U(UOPC_SZ.W) // AMO-address gen (use normal STD for datagen) val uopFMV_W_X = 68.U(UOPC_SZ.W) val uopFMV_D_X = 69.U(UOPC_SZ.W) val uopFMV_X_W = 70.U(UOPC_SZ.W) val uopFMV_X_D = 71.U(UOPC_SZ.W) val uopFSGNJ_S = 72.U(UOPC_SZ.W) val uopFSGNJ_D = 73.U(UOPC_SZ.W) val uopFCVT_S_D = 74.U(UOPC_SZ.W) val uopFCVT_D_S = 75.U(UOPC_SZ.W) val uopFCVT_S_X = 76.U(UOPC_SZ.W) val uopFCVT_D_X = 77.U(UOPC_SZ.W) val uopFCVT_X_S = 78.U(UOPC_SZ.W) val uopFCVT_X_D = 79.U(UOPC_SZ.W) val uopCMPR_S = 80.U(UOPC_SZ.W) val uopCMPR_D = 81.U(UOPC_SZ.W) val uopFCLASS_S = 82.U(UOPC_SZ.W) val uopFCLASS_D = 83.U(UOPC_SZ.W) val uopFMINMAX_S = 84.U(UOPC_SZ.W) val uopFMINMAX_D = 85.U(UOPC_SZ.W) // = 86.U(UOPC_SZ.W) val uopFADD_S = 87.U(UOPC_SZ.W) val uopFSUB_S = 88.U(UOPC_SZ.W) val uopFMUL_S = 89.U(UOPC_SZ.W) val uopFADD_D = 90.U(UOPC_SZ.W) val uopFSUB_D = 91.U(UOPC_SZ.W) val uopFMUL_D = 92.U(UOPC_SZ.W) val uopFMADD_S = 93.U(UOPC_SZ.W) val uopFMSUB_S = 94.U(UOPC_SZ.W) val uopFNMADD_S = 95.U(UOPC_SZ.W) val uopFNMSUB_S = 96.U(UOPC_SZ.W) val uopFMADD_D = 97.U(UOPC_SZ.W) val uopFMSUB_D = 98.U(UOPC_SZ.W) val uopFNMADD_D = 99.U(UOPC_SZ.W) val uopFNMSUB_D = 100.U(UOPC_SZ.W) val uopFDIV_S = 101.U(UOPC_SZ.W) val uopFDIV_D = 102.U(UOPC_SZ.W) val uopFSQRT_S = 103.U(UOPC_SZ.W) val uopFSQRT_D = 104.U(UOPC_SZ.W) val uopWFI = 105.U(UOPC_SZ.W) // pass uop down the CSR pipeline val uopERET = 106.U(UOPC_SZ.W) // pass uop down the CSR pipeline, also is ERET val uopSFENCE = 107.U(UOPC_SZ.W) val uopROCC = 108.U(UOPC_SZ.W) val uopMOV = 109.U(UOPC_SZ.W) // conditional mov decoded from "add rd, x0, rs2" // The Bubble Instruction (Machine generated NOP) // Insert (XOR x0,x0,x0) which is different from software compiler // generated NOPs which are (ADDI x0, x0, 0). // Reasoning for this is to let visualizers and stat-trackers differentiate // between software NOPs and machine-generated Bubbles in the pipeline. val BUBBLE = (0x4033).U(32.W) def NullMicroOp()(implicit p: Parameters): boom.v3.common.MicroOp = { val uop = Wire(new boom.v3.common.MicroOp) uop := DontCare // Overridden in the following lines uop.uopc := uopNOP // maybe not required, but helps on asserts that try to catch spurious behavior uop.bypassable := false.B uop.fp_val := false.B uop.uses_stq := false.B uop.uses_ldq := false.B uop.pdst := 0.U uop.dst_rtype := RT_X val cs = Wire(new boom.v3.common.CtrlSignals()) cs := DontCare // Overridden in the following lines cs.br_type := BR_N cs.csr_cmd := freechips.rocketchip.rocket.CSR.N cs.is_load := false.B cs.is_sta := false.B cs.is_std := false.B uop.ctrl := cs uop } } / * Mixin for RISCV constants / trait RISCVConstants { // abstract out instruction decode magic numbers val RD_MSB = 11 val RD_LSB = 7 val RS1_MSB = 19 val RS1_LSB = 15 val RS2_MSB = 24 val RS2_LSB = 20 val RS3_MSB = 31 val RS3_LSB = 27 val CSR_ADDR_MSB = 31 val CSR_ADDR_LSB = 20 val CSR_ADDR_SZ = 12 // location of the fifth bit in the shamt (for checking for illegal ops for SRAIW,etc.) val SHAMT_5_BIT = 25 val LONGEST_IMM_SZ = 20 val X0 = 0.U val RA = 1.U // return address register // memory consistency model // The C/C++ atomics MCM requires that two loads to the same address maintain program order. // The Cortex A9 does NOT enforce load/load ordering (which leads to buggy behavior). val MCM_ORDER_DEPENDENT_LOADS = true val jal_opc = (0x6f).U val jalr_opc = (0x67).U def GetUop(inst: UInt): UInt = inst(6,0) def GetRd (inst: UInt): UInt = inst(RD_MSB,RD_LSB) def GetRs1(inst: UInt): UInt = inst(RS1_MSB,RS1_LSB) def ExpandRVC(inst: UInt)(implicit p: Parameters): UInt = { val rvc_exp = Module(new RVCExpander) rvc_exp.io.in := inst Mux(rvc_exp.io.rvc, rvc_exp.io.out.bits, inst) } // Note: Accepts only EXPANDED rvc instructions def ComputeBranchTarget(pc: UInt, inst: UInt, xlen: Int)(implicit p: Parameters): UInt = { val b_imm32 = Cat(Fill(20,inst(31)), inst(7), inst(30,25), inst(11,8), 0.U(1.W)) ((pc.asSInt + b_imm32.asSInt).asSInt & (-2).S).asUInt } // Note: Accepts only EXPANDED rvc instructions def ComputeJALTarget(pc: UInt, inst: UInt, xlen: Int)(implicit p: Parameters): UInt = { val j_imm32 = Cat(Fill(12,inst(31)), inst(19,12), inst(20), inst(30,25), inst(24,21), 0.U(1.W)) ((pc.asSInt + j_imm32.asSInt).asSInt & (-2).S).asUInt } // Note: Accepts only EXPANDED rvc instructions def GetCfiType(inst: UInt)(implicit p: Parameters): UInt = { val bdecode = Module(new boom.v3.exu.BranchDecode) bdecode.io.inst := inst bdecode.io.pc := 0.U bdecode.io.out.cfi_type } } /* * Mixin for exception cause constants / trait ExcCauseConstants { // a memory disambigious misspeculation occurred val MINI_EXCEPTION_MEM_ORDERING = 16.U val MINI_EXCEPTION_CSR_REPLAY = 17.U require (!freechips.rocketchip.rocket.Causes.all.contains(16)) require (!freechips.rocketchip.rocket.Causes.all.contains(17)) } File AMOALU.scala: // See LICENSE.SiFive for license details. // See LICENSE.Berkeley for license details. package freechips.rocketchip.rocket import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.Parameters class StoreGen(typ: UInt, addr: UInt, dat: UInt, maxSize: Int) { val size = Wire(UInt(log2Up(log2Up(maxSize)+1).W)) size := typ val dat_padded = dat.pad(maxSize8) def misaligned: Bool = (addr & ((1.U << size) - 1.U)(log2Up(maxSize)-1,0)).orR def mask = { var res = 1.U for (i <- 0 until log2Up(maxSize)) { val upper = Mux(addr(i), res, 0.U) \| Mux(size >= (i+1).U, ((BigInt(1) << (1 << i))-1).U, 0.U) val lower = Mux(addr(i), 0.U, res) res = Cat(upper, lower) } res } protected def genData(i: Int): UInt = if (i >= log2Up(maxSize)) dat_padded else Mux(size === i.U, Fill(1 << (log2Up(maxSize)-i), dat_padded((8 << i)-1,0)), genData(i+1)) def data = genData(0) def wordData = genData(2) } class LoadGen(typ: UInt, signed: Bool, addr: UInt, dat: UInt, zero: Bool, maxSize: Int) { private val size = new StoreGen(typ, addr, dat, maxSize).size private def genData(logMinSize: Int): UInt = { var res = dat for (i <- log2Up(maxSize)-1 to logMinSize by -1) { val pos = 8 << i val shifted = Mux(addr(i), res(2pos-1,pos), res(pos-1,0)) val doZero = (i == 0).B && zero val zeroed = Mux(doZero, 0.U, shifted) res = Cat(Mux(size === i.U \|\| doZero, Fill(8maxSize-pos, signed && zeroed(pos-1)), res(8*maxSize-1,pos)), zeroed) } res } def wordData = genData(2) def data = genData(0) } class AMOALU(operandBits: Int)(implicit p: Parameters) extends Module { val minXLen = 32 val widths = (0 to log2Ceil(operandBits / minXLen)).map(minXLen << _) val io = IO(new Bundle { val mask = Input(UInt((operandBits / 8).W)) val cmd = Input(UInt(M_SZ.W)) val lhs = Input(UInt(operandBits.W)) val rhs = Input(UInt(operandBits.W)) val out = Output(UInt(operandBits.W)) val out_unmasked = Output(UInt(operandBits.W)) }) val max = io.cmd === M_XA_MAX \|\| io.cmd === M_XA_MAXU val min = io.cmd === M_XA_MIN \|\| io.cmd === M_XA_MINU val add = io.cmd === M_XA_ADD val logic_and = io.cmd === M_XA_OR \|\| io.cmd === M_XA_AND val logic_xor = io.cmd === M_XA_XOR \|\| io.cmd === M_XA_OR val adder_out = { // partition the carry chain to support sub-xLen addition val mask = ~(0.U(operandBits.W) +: widths.init.map(w => !io.mask(w/8-1) << (w-1))).reduce(_\|_) (io.lhs & mask) + (io.rhs & mask) } val less = { // break up the comparator so the lower parts will be CSE'd def isLessUnsigned(x: UInt, y: UInt, n: Int): Bool = { if (n == minXLen) x(n-1, 0) < y(n-1, 0) else x(n-1, n/2) < y(n-1, n/2) \|\| x(n-1, n/2) === y(n-1, n/2) && isLessUnsigned(x, y, n/2) } def isLess(x: UInt, y: UInt, n: Int): Bool = { val signed = { val mask = M_XA_MIN ^ M_XA_MINU (io.cmd & mask) === (M_XA_MIN & mask) } Mux(x(n-1) === y(n-1), isLessUnsigned(x, y, n), Mux(signed, x(n-1), y(n-1))) } PriorityMux(widths.reverse.map(w => (io.mask(w/8/2), isLess(io.lhs, io.rhs, w)))) } val minmax = Mux(Mux(less, min, max), io.lhs, io.rhs) val logic = Mux(logic_and, io.lhs & io.rhs, 0.U) \| Mux(logic_xor, io.lhs ^ io.rhs, 0.U) val out = Mux(add, adder_out, Mux(logic_and \|\| logic_xor, logic, minmax)) val wmask = FillInterleaved(8, io.mask) io.out := wmask & out \| ~wmask & io.lhs io.out_unmasked := out }	module LSU_1( // @[lsu.scala:201:7] input clock, // @[lsu.scala:201:7] input reset, // @[lsu.scala:201:7] input io_ptw_req_ready, // @[lsu.scala:204:14] output io_ptw_req_valid, // @[lsu.scala:204:14] output io_ptw_req_bits_valid, // @[lsu.scala:204:14] output [26:0] io_ptw_req_bits_bits_addr, // @[lsu.scala:204:14] input io_ptw_resp_valid, // @[lsu.scala:204:14] input io_ptw_resp_bits_ae_ptw, // @[lsu.scala:204:14] input io_ptw_resp_bits_ae_final, // @[lsu.scala:204:14] input io_ptw_resp_bits_pf, // @[lsu.scala:204:14] input io_ptw_resp_bits_gf, // @[lsu.scala:204:14] input io_ptw_resp_bits_hr, // @[lsu.scala:204:14] input io_ptw_resp_bits_hw, // @[lsu.scala:204:14] input io_ptw_resp_bits_hx, // @[lsu.scala:204:14] input [9:0] io_ptw_resp_bits_pte_reserved_for_future, // @[lsu.scala:204:14] input [43:0] io_ptw_resp_bits_pte_ppn, // @[lsu.scala:204:14] input [1:0] io_ptw_resp_bits_pte_reserved_for_software, // @[lsu.scala:204:14] input io_ptw_resp_bits_pte_d, // @[lsu.scala:204:14] input io_ptw_resp_bits_pte_a, // @[lsu.scala:204:14] input io_ptw_resp_bits_pte_g, // @[lsu.scala:204:14] input io_ptw_resp_bits_pte_u, // @[lsu.scala:204:14] input io_ptw_resp_bits_pte_x, // @[lsu.scala:204:14] input io_ptw_resp_bits_pte_w, // @[lsu.scala:204:14] input io_ptw_resp_bits_pte_r, // @[lsu.scala:204:14] input io_ptw_resp_bits_pte_v, // @[lsu.scala:204:14] input [1:0] io_ptw_resp_bits_level, // @[lsu.scala:204:14] input io_ptw_resp_bits_homogeneous, // @[lsu.scala:204:14] input io_ptw_resp_bits_gpa_valid, // @[lsu.scala:204:14] input [38:0] io_ptw_resp_bits_gpa_bits, // @[lsu.scala:204:14] input io_ptw_resp_bits_gpa_is_pte, // @[lsu.scala:204:14] input [3:0] io_ptw_ptbr_mode, // @[lsu.scala:204:14] input [43:0] io_ptw_ptbr_ppn, // @[lsu.scala:204:14] input io_ptw_status_debug, // @[lsu.scala:204:14] input io_ptw_status_cease, // @[lsu.scala:204:14] input io_ptw_status_wfi, // @[lsu.scala:204:14] input [1:0] io_ptw_status_dprv, // @[lsu.scala:204:14] input io_ptw_status_dv, // @[lsu.scala:204:14] input [1:0] io_ptw_status_prv, // @[lsu.scala:204:14] input io_ptw_status_v, // @[lsu.scala:204:14] input io_ptw_status_sd, // @[lsu.scala:204:14] input io_ptw_status_mpv, // @[lsu.scala:204:14] input io_ptw_status_gva, // @[lsu.scala:204:14] input io_ptw_status_tsr, // @[lsu.scala:204:14] input io_ptw_status_tw, // @[lsu.scala:204:14] input io_ptw_status_tvm, // @[lsu.scala:204:14] input io_ptw_status_mxr, // @[lsu.scala:204:14] input io_ptw_status_sum, // @[lsu.scala:204:14] input io_ptw_status_mprv, // @[lsu.scala:204:14] input [1:0] io_ptw_status_fs, // @[lsu.scala:204:14] input [1:0] io_ptw_status_mpp, // @[lsu.scala:204:14] input io_ptw_status_spp, // @[lsu.scala:204:14] input io_ptw_status_mpie, // @[lsu.scala:204:14] input io_ptw_status_spie, // @[lsu.scala:204:14] input io_ptw_status_mie, // @[lsu.scala:204:14] input io_ptw_status_sie, // @[lsu.scala:204:14] input io_ptw_pmp_0_cfg_l, // @[lsu.scala:204:14] input [1:0] io_ptw_pmp_0_cfg_a, // @[lsu.scala:204:14] input io_ptw_pmp_0_cfg_x, // @[lsu.scala:204:14] input io_ptw_pmp_0_cfg_w, // @[lsu.scala:204:14] input io_ptw_pmp_0_cfg_r, // @[lsu.scala:204:14] input [29:0] io_ptw_pmp_0_addr, // @[lsu.scala:204:14] input [31:0] io_ptw_pmp_0_mask, // @[lsu.scala:204:14] input io_ptw_pmp_1_cfg_l, // @[lsu.scala:204:14] input [1:0] io_ptw_pmp_1_cfg_a, // @[lsu.scala:204:14] input io_ptw_pmp_1_cfg_x, // @[lsu.scala:204:14] input io_ptw_pmp_1_cfg_w, // @[lsu.scala:204:14] input io_ptw_pmp_1_cfg_r, // @[lsu.scala:204:14] input [29:0] io_ptw_pmp_1_addr, // @[lsu.scala:204:14] input [31:0] io_ptw_pmp_1_mask, // @[lsu.scala:204:14] input io_ptw_pmp_2_cfg_l, // @[lsu.scala:204:14] input [1:0] io_ptw_pmp_2_cfg_a, // @[lsu.scala:204:14] input io_ptw_pmp_2_cfg_x, // @[lsu.scala:204:14] input io_ptw_pmp_2_cfg_w, // @[lsu.scala:204:14] input io_ptw_pmp_2_cfg_r, // @[lsu.scala:204:14] input [29:0] io_ptw_pmp_2_addr, // @[lsu.scala:204:14] input [31:0] io_ptw_pmp_2_mask, // @[lsu.scala:204:14] input io_ptw_pmp_3_cfg_l, // @[lsu.scala:204:14] input [1:0] io_ptw_pmp_3_cfg_a, // @[lsu.scala:204:14] input io_ptw_pmp_3_cfg_x, // @[lsu.scala:204:14] input io_ptw_pmp_3_cfg_w, // @[lsu.scala:204:14] input io_ptw_pmp_3_cfg_r, // @[lsu.scala:204:14] input [29:0] io_ptw_pmp_3_addr, // @[lsu.scala:204:14] input [31:0] io_ptw_pmp_3_mask, // @[lsu.scala:204:14] input io_ptw_pmp_4_cfg_l, // @[lsu.scala:204:14] input [1:0] io_ptw_pmp_4_cfg_a, // @[lsu.scala:204:14] input io_ptw_pmp_4_cfg_x, // @[lsu.scala:204:14] input io_ptw_pmp_4_cfg_w, // @[lsu.scala:204:14] input io_ptw_pmp_4_cfg_r, // @[lsu.scala:204:14] input [29:0] io_ptw_pmp_4_addr, // @[lsu.scala:204:14] input [31:0] io_ptw_pmp_4_mask, // @[lsu.scala:204:14] input io_ptw_pmp_5_cfg_l, // @[lsu.scala:204:14] input [1:0] io_ptw_pmp_5_cfg_a, // @[lsu.scala:204:14] input io_ptw_pmp_5_cfg_x, // @[lsu.scala:204:14] input io_ptw_pmp_5_cfg_w, // @[lsu.scala:204:14] input io_ptw_pmp_5_cfg_r, // @[lsu.scala:204:14] input [29:0] io_ptw_pmp_5_addr, // @[lsu.scala:204:14] input [31:0] io_ptw_pmp_5_mask, // @[lsu.scala:204:14] input io_ptw_pmp_6_cfg_l, // @[lsu.scala:204:14] input [1:0] io_ptw_pmp_6_cfg_a, // @[lsu.scala:204:14] input io_ptw_pmp_6_cfg_x, // @[lsu.scala:204:14] input io_ptw_pmp_6_cfg_w, // @[lsu.scala:204:14] input io_ptw_pmp_6_cfg_r, // @[lsu.scala:204:14] input [29:0] io_ptw_pmp_6_addr, // @[lsu.scala:204:14] input [31:0] io_ptw_pmp_6_mask, // @[lsu.scala:204:14] input io_ptw_pmp_7_cfg_l, // @[lsu.scala:204:14] input [1:0] io_ptw_pmp_7_cfg_a, // @[lsu.scala:204:14] input io_ptw_pmp_7_cfg_x, // @[lsu.scala:204:14] input io_ptw_pmp_7_cfg_w, // @[lsu.scala:204:14] input io_ptw_pmp_7_cfg_r, // @[lsu.scala:204:14] input [29:0] io_ptw_pmp_7_addr, // @[lsu.scala:204:14] input [31:0] io_ptw_pmp_7_mask, // @[lsu.scala:204:14] input io_core_exe_0_req_valid, // @[lsu.scala:204:14] input [6:0] io_core_exe_0_req_bits_uop_uopc, // @[lsu.scala:204:14] input [31:0] io_core_exe_0_req_bits_uop_inst, // @[lsu.scala:204:14] input [31:0] io_core_exe_0_req_bits_uop_debug_inst, // @[lsu.scala:204:14] input io_core_exe_0_req_bits_uop_is_rvc, // @[lsu.scala:204:14] input [39:0] io_core_exe_0_req_bits_uop_debug_pc, // @[lsu.scala:204:14] input [2:0] io_core_exe_0_req_bits_uop_iq_type, // @[lsu.scala:204:14] input [9:0] io_core_exe_0_req_bits_uop_fu_code, // @[lsu.scala:204:14] input [3:0] io_core_exe_0_req_bits_uop_ctrl_br_type, // @[lsu.scala:204:14] input [1:0] io_core_exe_0_req_bits_uop_ctrl_op1_sel, // @[lsu.scala:204:14] input [2:0] io_core_exe_0_req_bits_uop_ctrl_op2_sel, // @[lsu.scala:204:14] input [2:0] io_core_exe_0_req_bits_uop_ctrl_imm_sel, // @[lsu.scala:204:14] input [4:0] io_core_exe_0_req_bits_uop_ctrl_op_fcn, // @[lsu.scala:204:14] input io_core_exe_0_req_bits_uop_ctrl_fcn_dw, // @[lsu.scala:204:14] input [2:0] io_core_exe_0_req_bits_uop_ctrl_csr_cmd, // @[lsu.scala:204:14] input io_core_exe_0_req_bits_uop_ctrl_is_load, // @[lsu.scala:204:14] input io_core_exe_0_req_bits_uop_ctrl_is_sta, // @[lsu.scala:204:14] input io_core_exe_0_req_bits_uop_ctrl_is_std, // @[lsu.scala:204:14] input [1:0] io_core_exe_0_req_bits_uop_iw_state, // @[lsu.scala:204:14] input io_core_exe_0_req_bits_uop_iw_p1_poisoned, // @[lsu.scala:204:14] input io_core_exe_0_req_bits_uop_iw_p2_poisoned, // @[lsu.scala:204:14] input io_core_exe_0_req_bits_uop_is_br, // @[lsu.scala:204:14] input io_core_exe_0_req_bits_uop_is_jalr, // @[lsu.scala:204:14] input io_core_exe_0_req_bits_uop_is_jal, // @[lsu.scala:204:14] input io_core_exe_0_req_bits_uop_is_sfb, // @[lsu.scala:204:14] input [7:0] io_core_exe_0_req_bits_uop_br_mask, // @[lsu.scala:204:14] input [2:0] io_core_exe_0_req_bits_uop_br_tag, // @[lsu.scala:204:14] input [3:0] io_core_exe_0_req_bits_uop_ftq_idx, // @[lsu.scala:204:14] input io_core_exe_0_req_bits_uop_edge_inst, // @[lsu.scala:204:14] input [5:0] io_core_exe_0_req_bits_uop_pc_lob, // @[lsu.scala:204:14] input io_core_exe_0_req_bits_uop_taken, // @[lsu.scala:204:14] input [19:0] io_core_exe_0_req_bits_uop_imm_packed, // @[lsu.scala:204:14] input [11:0] io_core_exe_0_req_bits_uop_csr_addr, // @[lsu.scala:204:14] input [4:0] io_core_exe_0_req_bits_uop_rob_idx, // @[lsu.scala:204:14] input [2:0] io_core_exe_0_req_bits_uop_ldq_idx, // @[lsu.scala:204:14] input [2:0] io_core_exe_0_req_bits_uop_stq_idx, // @[lsu.scala:204:14] input [1:0] io_core_exe_0_req_bits_uop_rxq_idx, // @[lsu.scala:204:14] input [5:0] io_core_exe_0_req_bits_uop_pdst, // @[lsu.scala:204:14] input [5:0] io_core_exe_0_req_bits_uop_prs1, // @[lsu.scala:204:14] input [5:0] io_core_exe_0_req_bits_uop_prs2, // @[lsu.scala:204:14] input [5:0] io_core_exe_0_req_bits_uop_prs3, // @[lsu.scala:204:14] input [3:0] io_core_exe_0_req_bits_uop_ppred, // @[lsu.scala:204:14] input io_core_exe_0_req_bits_uop_prs1_busy, // @[lsu.scala:204:14] input io_core_exe_0_req_bits_uop_prs2_busy, // @[lsu.scala:204:14] input io_core_exe_0_req_bits_uop_prs3_busy, // @[lsu.scala:204:14] input io_core_exe_0_req_bits_uop_ppred_busy, // @[lsu.scala:204:14] input [5:0] io_core_exe_0_req_bits_uop_stale_pdst, // @[lsu.scala:204:14] input io_core_exe_0_req_bits_uop_exception, // @[lsu.scala:204:14] input [63:0] io_core_exe_0_req_bits_uop_exc_cause, // @[lsu.scala:204:14] input io_core_exe_0_req_bits_uop_bypassable, // @[lsu.scala:204:14] input [4:0] io_core_exe_0_req_bits_uop_mem_cmd, // @[lsu.scala:204:14] input [1:0] io_core_exe_0_req_bits_uop_mem_size, // @[lsu.scala:204:14] input io_core_exe_0_req_bits_uop_mem_signed, // @[lsu.scala:204:14] input io_core_exe_0_req_bits_uop_is_fence, // @[lsu.scala:204:14] input io_core_exe_0_req_bits_uop_is_fencei, // @[lsu.scala:204:14] input io_core_exe_0_req_bits_uop_is_amo, // @[lsu.scala:204:14] input io_core_exe_0_req_bits_uop_uses_ldq, // @[lsu.scala:204:14] input io_core_exe_0_req_bits_uop_uses_stq, // @[lsu.scala:204:14] input io_core_exe_0_req_bits_uop_is_sys_pc2epc, // @[lsu.scala:204:14] input io_core_exe_0_req_bits_uop_is_unique, // @[lsu.scala:204:14] input io_core_exe_0_req_bits_uop_flush_on_commit, // @[lsu.scala:204:14] input io_core_exe_0_req_bits_uop_ldst_is_rs1, // @[lsu.scala:204:14] input [5:0] io_core_exe_0_req_bits_uop_ldst, // @[lsu.scala:204:14] input [5:0] io_core_exe_0_req_bits_uop_lrs1, // @[lsu.scala:204:14] input [5:0] io_core_exe_0_req_bits_uop_lrs2, // @[lsu.scala:204:14] input [5:0] io_core_exe_0_req_bits_uop_lrs3, // @[lsu.scala:204:14] input io_core_exe_0_req_bits_uop_ldst_val, // @[lsu.scala:204:14] input [1:0] io_core_exe_0_req_bits_uop_dst_rtype, // @[lsu.scala:204:14] input [1:0] io_core_exe_0_req_bits_uop_lrs1_rtype, // @[lsu.scala:204:14] input [1:0] io_core_exe_0_req_bits_uop_lrs2_rtype, // @[lsu.scala:204:14] input io_core_exe_0_req_bits_uop_frs3_en, // @[lsu.scala:204:14] input io_core_exe_0_req_bits_uop_fp_val, // @[lsu.scala:204:14] input io_core_exe_0_req_bits_uop_fp_single, // @[lsu.scala:204:14] input io_core_exe_0_req_bits_uop_xcpt_pf_if, // @[lsu.scala:204:14] input io_core_exe_0_req_bits_uop_xcpt_ae_if, // @[lsu.scala:204:14] input io_core_exe_0_req_bits_uop_xcpt_ma_if, // @[lsu.scala:204:14] input io_core_exe_0_req_bits_uop_bp_debug_if, // @[lsu.scala:204:14] input io_core_exe_0_req_bits_uop_bp_xcpt_if, // @[lsu.scala:204:14] input [1:0] io_core_exe_0_req_bits_uop_debug_fsrc, // @[lsu.scala:204:14] input [1:0] io_core_exe_0_req_bits_uop_debug_tsrc, // @[lsu.scala:204:14] input [63:0] io_core_exe_0_req_bits_data, // @[lsu.scala:204:14] input [39:0] io_core_exe_0_req_bits_addr, // @[lsu.scala:204:14] input io_core_exe_0_req_bits_mxcpt_valid, // @[lsu.scala:204:14] input [24:0] io_core_exe_0_req_bits_mxcpt_bits, // @[lsu.scala:204:14] input io_core_exe_0_req_bits_sfence_valid, // @[lsu.scala:204:14] input io_core_exe_0_req_bits_sfence_bits_rs1, // @[lsu.scala:204:14] input io_core_exe_0_req_bits_sfence_bits_rs2, // @[lsu.scala:204:14] input [38:0] io_core_exe_0_req_bits_sfence_bits_addr, // @[lsu.scala:204:14] input io_core_exe_0_req_bits_sfence_bits_asid, // @[lsu.scala:204:14] output io_core_exe_0_iresp_valid, // @[lsu.scala:204:14] output [6:0] io_core_exe_0_iresp_bits_uop_uopc, // @[lsu.scala:204:14] output [31:0] io_core_exe_0_iresp_bits_uop_inst, // @[lsu.scala:204:14] output [31:0] io_core_exe_0_iresp_bits_uop_debug_inst, // @[lsu.scala:204:14] output io_core_exe_0_iresp_bits_uop_is_rvc, // @[lsu.scala:204:14] output [39:0] io_core_exe_0_iresp_bits_uop_debug_pc, // @[lsu.scala:204:14] output [2:0] io_core_exe_0_iresp_bits_uop_iq_type, // @[lsu.scala:204:14] output [9:0] io_core_exe_0_iresp_bits_uop_fu_code, // @[lsu.scala:204:14] output [3:0] io_core_exe_0_iresp_bits_uop_ctrl_br_type, // @[lsu.scala:204:14] output [1:0] io_core_exe_0_iresp_bits_uop_ctrl_op1_sel, // @[lsu.scala:204:14] output [2:0] io_core_exe_0_iresp_bits_uop_ctrl_op2_sel, // @[lsu.scala:204:14] output [2:0] io_core_exe_0_iresp_bits_uop_ctrl_imm_sel, // @[lsu.scala:204:14] output [4:0] io_core_exe_0_iresp_bits_uop_ctrl_op_fcn, // @[lsu.scala:204:14] output io_core_exe_0_iresp_bits_uop_ctrl_fcn_dw, // @[lsu.scala:204:14] output [2:0] io_core_exe_0_iresp_bits_uop_ctrl_csr_cmd, // @[lsu.scala:204:14] output io_core_exe_0_iresp_bits_uop_ctrl_is_load, // @[lsu.scala:204:14] output io_core_exe_0_iresp_bits_uop_ctrl_is_sta, // @[lsu.scala:204:14] output io_core_exe_0_iresp_bits_uop_ctrl_is_std, // @[lsu.scala:204:14] output [1:0] io_core_exe_0_iresp_bits_uop_iw_state, // @[lsu.scala:204:14] output io_core_exe_0_iresp_bits_uop_iw_p1_poisoned, // @[lsu.scala:204:14] output io_core_exe_0_iresp_bits_uop_iw_p2_poisoned, // @[lsu.scala:204:14] output io_core_exe_0_iresp_bits_uop_is_br, // @[lsu.scala:204:14] output io_core_exe_0_iresp_bits_uop_is_jalr, // @[lsu.scala:204:14] output io_core_exe_0_iresp_bits_uop_is_jal, // @[lsu.scala:204:14] output io_core_exe_0_iresp_bits_uop_is_sfb, // @[lsu.scala:204:14] output [7:0] io_core_exe_0_iresp_bits_uop_br_mask, // @[lsu.scala:204:14] output [2:0] io_core_exe_0_iresp_bits_uop_br_tag, // @[lsu.scala:204:14] output [3:0] io_core_exe_0_iresp_bits_uop_ftq_idx, // @[lsu.scala:204:14] output io_core_exe_0_iresp_bits_uop_edge_inst, // @[lsu.scala:204:14] output [5:0] io_core_exe_0_iresp_bits_uop_pc_lob, // @[lsu.scala:204:14] output io_core_exe_0_iresp_bits_uop_taken, // @[lsu.scala:204:14] output [19:0] io_core_exe_0_iresp_bits_uop_imm_packed, // @[lsu.scala:204:14] output [11:0] io_core_exe_0_iresp_bits_uop_csr_addr, // @[lsu.scala:204:14] output [4:0] io_core_exe_0_iresp_bits_uop_rob_idx, // @[lsu.scala:204:14] output [2:0] io_core_exe_0_iresp_bits_uop_ldq_idx, // @[lsu.scala:204:14] output [2:0] io_core_exe_0_iresp_bits_uop_stq_idx, // @[lsu.scala:204:14] output [1:0] io_core_exe_0_iresp_bits_uop_rxq_idx, // @[lsu.scala:204:14] output [5:0] io_core_exe_0_iresp_bits_uop_pdst, // @[lsu.scala:204:14] output [5:0] io_core_exe_0_iresp_bits_uop_prs1, // @[lsu.scala:204:14] output [5:0] io_core_exe_0_iresp_bits_uop_prs2, // @[lsu.scala:204:14] output [5:0] io_core_exe_0_iresp_bits_uop_prs3, // @[lsu.scala:204:14] output [3:0] io_core_exe_0_iresp_bits_uop_ppred, // @[lsu.scala:204:14] output io_core_exe_0_iresp_bits_uop_prs1_busy, // @[lsu.scala:204:14] output io_core_exe_0_iresp_bits_uop_prs2_busy, // @[lsu.scala:204:14] output io_core_exe_0_iresp_bits_uop_prs3_busy, // @[lsu.scala:204:14] output io_core_exe_0_iresp_bits_uop_ppred_busy, // @[lsu.scala:204:14] output [5:0] io_core_exe_0_iresp_bits_uop_stale_pdst, // @[lsu.scala:204:14] output io_core_exe_0_iresp_bits_uop_exception, // @[lsu.scala:204:14] output [63:0] io_core_exe_0_iresp_bits_uop_exc_cause, // @[lsu.scala:204:14] output io_core_exe_0_iresp_bits_uop_bypassable, // @[lsu.scala:204:14] output [4:0] io_core_exe_0_iresp_bits_uop_mem_cmd, // @[lsu.scala:204:14] output [1:0] io_core_exe_0_iresp_bits_uop_mem_size, // @[lsu.scala:204:14] output io_core_exe_0_iresp_bits_uop_mem_signed, // @[lsu.scala:204:14] output io_core_exe_0_iresp_bits_uop_is_fence, // @[lsu.scala:204:14] output io_core_exe_0_iresp_bits_uop_is_fencei, // @[lsu.scala:204:14] output io_core_exe_0_iresp_bits_uop_is_amo, // @[lsu.scala:204:14] output io_core_exe_0_iresp_bits_uop_uses_ldq, // @[lsu.scala:204:14] output io_core_exe_0_iresp_bits_uop_uses_stq, // @[lsu.scala:204:14] output io_core_exe_0_iresp_bits_uop_is_sys_pc2epc, // @[lsu.scala:204:14] output io_core_exe_0_iresp_bits_uop_is_unique, // @[lsu.scala:204:14] output io_core_exe_0_iresp_bits_uop_flush_on_commit, // @[lsu.scala:204:14] output io_core_exe_0_iresp_bits_uop_ldst_is_rs1, // @[lsu.scala:204:14] output [5:0] io_core_exe_0_iresp_bits_uop_ldst, // @[lsu.scala:204:14] output [5:0] io_core_exe_0_iresp_bits_uop_lrs1, // @[lsu.scala:204:14] output [5:0] io_core_exe_0_iresp_bits_uop_lrs2, // @[lsu.scala:204:14] output [5:0] io_core_exe_0_iresp_bits_uop_lrs3, // @[lsu.scala:204:14] output io_core_exe_0_iresp_bits_uop_ldst_val, // @[lsu.scala:204:14] output [1:0] io_core_exe_0_iresp_bits_uop_dst_rtype, // @[lsu.scala:204:14] output [1:0] io_core_exe_0_iresp_bits_uop_lrs1_rtype, // @[lsu.scala:204:14] output [1:0] io_core_exe_0_iresp_bits_uop_lrs2_rtype, // @[lsu.scala:204:14] output io_core_exe_0_iresp_bits_uop_frs3_en, // @[lsu.scala:204:14] output io_core_exe_0_iresp_bits_uop_fp_val, // @[lsu.scala:204:14] output io_core_exe_0_iresp_bits_uop_fp_single, // @[lsu.scala:204:14] output io_core_exe_0_iresp_bits_uop_xcpt_pf_if, // @[lsu.scala:204:14] output io_core_exe_0_iresp_bits_uop_xcpt_ae_if, // @[lsu.scala:204:14] output io_core_exe_0_iresp_bits_uop_xcpt_ma_if, // @[lsu.scala:204:14] output io_core_exe_0_iresp_bits_uop_bp_debug_if, // @[lsu.scala:204:14] output io_core_exe_0_iresp_bits_uop_bp_xcpt_if, // @[lsu.scala:204:14] output [1:0] io_core_exe_0_iresp_bits_uop_debug_fsrc, // @[lsu.scala:204:14] output [1:0] io_core_exe_0_iresp_bits_uop_debug_tsrc, // @[lsu.scala:204:14] output [63:0] io_core_exe_0_iresp_bits_data, // @[lsu.scala:204:14] output io_core_exe_0_fresp_valid, // @[lsu.scala:204:14] output [6:0] io_core_exe_0_fresp_bits_uop_uopc, // @[lsu.scala:204:14] output [31:0] io_core_exe_0_fresp_bits_uop_inst, // @[lsu.scala:204:14] output [31:0] io_core_exe_0_fresp_bits_uop_debug_inst, // @[lsu.scala:204:14] output io_core_exe_0_fresp_bits_uop_is_rvc, // @[lsu.scala:204:14] output [39:0] io_core_exe_0_fresp_bits_uop_debug_pc, // @[lsu.scala:204:14] output [2:0] io_core_exe_0_fresp_bits_uop_iq_type, // @[lsu.scala:204:14] output [9:0] io_core_exe_0_fresp_bits_uop_fu_code, // @[lsu.scala:204:14] output [3:0] io_core_exe_0_fresp_bits_uop_ctrl_br_type, // @[lsu.scala:204:14] output [1:0] io_core_exe_0_fresp_bits_uop_ctrl_op1_sel, // @[lsu.scala:204:14] output [2:0] io_core_exe_0_fresp_bits_uop_ctrl_op2_sel, // @[lsu.scala:204:14] output [2:0] io_core_exe_0_fresp_bits_uop_ctrl_imm_sel, // @[lsu.scala:204:14] output [4:0] io_core_exe_0_fresp_bits_uop_ctrl_op_fcn, // @[lsu.scala:204:14] output io_core_exe_0_fresp_bits_uop_ctrl_fcn_dw, // @[lsu.scala:204:14] output [2:0] io_core_exe_0_fresp_bits_uop_ctrl_csr_cmd, // @[lsu.scala:204:14] output io_core_exe_0_fresp_bits_uop_ctrl_is_load, // @[lsu.scala:204:14] output io_core_exe_0_fresp_bits_uop_ctrl_is_sta, // @[lsu.scala:204:14] output io_core_exe_0_fresp_bits_uop_ctrl_is_std, // @[lsu.scala:204:14] output [1:0] io_core_exe_0_fresp_bits_uop_iw_state, // @[lsu.scala:204:14] output io_core_exe_0_fresp_bits_uop_iw_p1_poisoned, // @[lsu.scala:204:14] output io_core_exe_0_fresp_bits_uop_iw_p2_poisoned, // @[lsu.scala:204:14] output io_core_exe_0_fresp_bits_uop_is_br, // @[lsu.scala:204:14] output io_core_exe_0_fresp_bits_uop_is_jalr, // @[lsu.scala:204:14] output io_core_exe_0_fresp_bits_uop_is_jal, // @[lsu.scala:204:14] output io_core_exe_0_fresp_bits_uop_is_sfb, // @[lsu.scala:204:14] output [7:0] io_core_exe_0_fresp_bits_uop_br_mask, // @[lsu.scala:204:14] output [2:0] io_core_exe_0_fresp_bits_uop_br_tag, // @[lsu.scala:204:14] output [3:0] io_core_exe_0_fresp_bits_uop_ftq_idx, // @[lsu.scala:204:14] output io_core_exe_0_fresp_bits_uop_edge_inst, // @[lsu.scala:204:14] output [5:0] io_core_exe_0_fresp_bits_uop_pc_lob, // @[lsu.scala:204:14] output io_core_exe_0_fresp_bits_uop_taken, // @[lsu.scala:204:14] output [19:0] io_core_exe_0_fresp_bits_uop_imm_packed, // @[lsu.scala:204:14] output [11:0] io_core_exe_0_fresp_bits_uop_csr_addr, // @[lsu.scala:204:14] output [4:0] io_core_exe_0_fresp_bits_uop_rob_idx, // @[lsu.scala:204:14] output [2:0] io_core_exe_0_fresp_bits_uop_ldq_idx, // @[lsu.scala:204:14] output [2:0] io_core_exe_0_fresp_bits_uop_stq_idx, // @[lsu.scala:204:14] output [1:0] io_core_exe_0_fresp_bits_uop_rxq_idx, // @[lsu.scala:204:14] output [5:0] io_core_exe_0_fresp_bits_uop_pdst, // @[lsu.scala:204:14] output [5:0] io_core_exe_0_fresp_bits_uop_prs1, // @[lsu.scala:204:14] output [5:0] io_core_exe_0_fresp_bits_uop_prs2, // @[lsu.scala:204:14] output [5:0] io_core_exe_0_fresp_bits_uop_prs3, // @[lsu.scala:204:14] output [3:0] io_core_exe_0_fresp_bits_uop_ppred, // @[lsu.scala:204:14] output io_core_exe_0_fresp_bits_uop_prs1_busy, // @[lsu.scala:204:14] output io_core_exe_0_fresp_bits_uop_prs2_busy, // @[lsu.scala:204:14] output io_core_exe_0_fresp_bits_uop_prs3_busy, // @[lsu.scala:204:14] output io_core_exe_0_fresp_bits_uop_ppred_busy, // @[lsu.scala:204:14] output [5:0] io_core_exe_0_fresp_bits_uop_stale_pdst, // @[lsu.scala:204:14] output io_core_exe_0_fresp_bits_uop_exception, // @[lsu.scala:204:14] output [63:0] io_core_exe_0_fresp_bits_uop_exc_cause, // @[lsu.scala:204:14] output io_core_exe_0_fresp_bits_uop_bypassable, // @[lsu.scala:204:14] output [4:0] io_core_exe_0_fresp_bits_uop_mem_cmd, // @[lsu.scala:204:14] output [1:0] io_core_exe_0_fresp_bits_uop_mem_size, // @[lsu.scala:204:14] output io_core_exe_0_fresp_bits_uop_mem_signed, // @[lsu.scala:204:14] output io_core_exe_0_fresp_bits_uop_is_fence, // @[lsu.scala:204:14] output io_core_exe_0_fresp_bits_uop_is_fencei, // @[lsu.scala:204:14] output io_core_exe_0_fresp_bits_uop_is_amo, // @[lsu.scala:204:14] output io_core_exe_0_fresp_bits_uop_uses_ldq, // @[lsu.scala:204:14] output io_core_exe_0_fresp_bits_uop_uses_stq, // @[lsu.scala:204:14] output io_core_exe_0_fresp_bits_uop_is_sys_pc2epc, // @[lsu.scala:204:14] output io_core_exe_0_fresp_bits_uop_is_unique, // @[lsu.scala:204:14] output io_core_exe_0_fresp_bits_uop_flush_on_commit, // @[lsu.scala:204:14] output io_core_exe_0_fresp_bits_uop_ldst_is_rs1, // @[lsu.scala:204:14] output [5:0] io_core_exe_0_fresp_bits_uop_ldst, // @[lsu.scala:204:14] output [5:0] io_core_exe_0_fresp_bits_uop_lrs1, // @[lsu.scala:204:14] output [5:0] io_core_exe_0_fresp_bits_uop_lrs2, // @[lsu.scala:204:14] output [5:0] io_core_exe_0_fresp_bits_uop_lrs3, // @[lsu.scala:204:14] output io_core_exe_0_fresp_bits_uop_ldst_val, // @[lsu.scala:204:14] output [1:0] io_core_exe_0_fresp_bits_uop_dst_rtype, // @[lsu.scala:204:14] output [1:0] io_core_exe_0_fresp_bits_uop_lrs1_rtype, // @[lsu.scala:204:14] output [1:0] io_core_exe_0_fresp_bits_uop_lrs2_rtype, // @[lsu.scala:204:14] output io_core_exe_0_fresp_bits_uop_frs3_en, // @[lsu.scala:204:14] output io_core_exe_0_fresp_bits_uop_fp_val, // @[lsu.scala:204:14] output io_core_exe_0_fresp_bits_uop_fp_single, // @[lsu.scala:204:14] output io_core_exe_0_fresp_bits_uop_xcpt_pf_if, // @[lsu.scala:204:14] output io_core_exe_0_fresp_bits_uop_xcpt_ae_if, // @[lsu.scala:204:14] output io_core_exe_0_fresp_bits_uop_xcpt_ma_if, // @[lsu.scala:204:14] output io_core_exe_0_fresp_bits_uop_bp_debug_if, // @[lsu.scala:204:14] output io_core_exe_0_fresp_bits_uop_bp_xcpt_if, // @[lsu.scala:204:14] output [1:0] io_core_exe_0_fresp_bits_uop_debug_fsrc, // @[lsu.scala:204:14] output [1:0] io_core_exe_0_fresp_bits_uop_debug_tsrc, // @[lsu.scala:204:14] output [64:0] io_core_exe_0_fresp_bits_data, // @[lsu.scala:204:14] input io_core_dis_uops_0_valid, // @[lsu.scala:204:14] input [6:0] io_core_dis_uops_0_bits_uopc, // @[lsu.scala:204:14] input [31:0] io_core_dis_uops_0_bits_inst, // @[lsu.scala:204:14] input [31:0] io_core_dis_uops_0_bits_debug_inst, // @[lsu.scala:204:14] input io_core_dis_uops_0_bits_is_rvc, // @[lsu.scala:204:14] input [39:0] io_core_dis_uops_0_bits_debug_pc, // @[lsu.scala:204:14] input [2:0] io_core_dis_uops_0_bits_iq_type, // @[lsu.scala:204:14] input [9:0] io_core_dis_uops_0_bits_fu_code, // @[lsu.scala:204:14] input [3:0] io_core_dis_uops_0_bits_ctrl_br_type, // @[lsu.scala:204:14] input [1:0] io_core_dis_uops_0_bits_ctrl_op1_sel, // @[lsu.scala:204:14] input [2:0] io_core_dis_uops_0_bits_ctrl_op2_sel, // @[lsu.scala:204:14] input [2:0] io_core_dis_uops_0_bits_ctrl_imm_sel, // @[lsu.scala:204:14] input [4:0] io_core_dis_uops_0_bits_ctrl_op_fcn, // @[lsu.scala:204:14] input io_core_dis_uops_0_bits_ctrl_fcn_dw, // @[lsu.scala:204:14] input [2:0] io_core_dis_uops_0_bits_ctrl_csr_cmd, // @[lsu.scala:204:14] input io_core_dis_uops_0_bits_ctrl_is_load, // @[lsu.scala:204:14] input io_core_dis_uops_0_bits_ctrl_is_sta, // @[lsu.scala:204:14] input io_core_dis_uops_0_bits_ctrl_is_std, // @[lsu.scala:204:14] input [1:0] io_core_dis_uops_0_bits_iw_state, // @[lsu.scala:204:14] input io_core_dis_uops_0_bits_iw_p1_poisoned, // @[lsu.scala:204:14] input io_core_dis_uops_0_bits_iw_p2_poisoned, // @[lsu.scala:204:14] input io_core_dis_uops_0_bits_is_br, // @[lsu.scala:204:14] input io_core_dis_uops_0_bits_is_jalr, // @[lsu.scala:204:14] input io_core_dis_uops_0_bits_is_jal, // @[lsu.scala:204:14] input io_core_dis_uops_0_bits_is_sfb, // @[lsu.scala:204:14] input [7:0] io_core_dis_uops_0_bits_br_mask, // @[lsu.scala:204:14] input [2:0] io_core_dis_uops_0_bits_br_tag, // @[lsu.scala:204:14] input [3:0] io_core_dis_uops_0_bits_ftq_idx, // @[lsu.scala:204:14] input io_core_dis_uops_0_bits_edge_inst, // @[lsu.scala:204:14] input [5:0] io_core_dis_uops_0_bits_pc_lob, // @[lsu.scala:204:14] input io_core_dis_uops_0_bits_taken, // @[lsu.scala:204:14] input [19:0] io_core_dis_uops_0_bits_imm_packed, // @[lsu.scala:204:14] input [11:0] io_core_dis_uops_0_bits_csr_addr, // @[lsu.scala:204:14] input [4:0] io_core_dis_uops_0_bits_rob_idx, // @[lsu.scala:204:14] input [2:0] io_core_dis_uops_0_bits_ldq_idx, // @[lsu.scala:204:14] input [2:0] io_core_dis_uops_0_bits_stq_idx, // @[lsu.scala:204:14] input [1:0] io_core_dis_uops_0_bits_rxq_idx, // @[lsu.scala:204:14] input [5:0] io_core_dis_uops_0_bits_pdst, // @[lsu.scala:204:14] input [5:0] io_core_dis_uops_0_bits_prs1, // @[lsu.scala:204:14] input [5:0] io_core_dis_uops_0_bits_prs2, // @[lsu.scala:204:14] input [5:0] io_core_dis_uops_0_bits_prs3, // @[lsu.scala:204:14] input io_core_dis_uops_0_bits_prs1_busy, // @[lsu.scala:204:14] input io_core_dis_uops_0_bits_prs2_busy, // @[lsu.scala:204:14] input io_core_dis_uops_0_bits_prs3_busy, // @[lsu.scala:204:14] input [5:0] io_core_dis_uops_0_bits_stale_pdst, // @[lsu.scala:204:14] input io_core_dis_uops_0_bits_exception, // @[lsu.scala:204:14] input [63:0] io_core_dis_uops_0_bits_exc_cause, // @[lsu.scala:204:14] input io_core_dis_uops_0_bits_bypassable, // @[lsu.scala:204:14] input [4:0] io_core_dis_uops_0_bits_mem_cmd, // @[lsu.scala:204:14] input [1:0] io_core_dis_uops_0_bits_mem_size, // @[lsu.scala:204:14] input io_core_dis_uops_0_bits_mem_signed, // @[lsu.scala:204:14] input io_core_dis_uops_0_bits_is_fence, // @[lsu.scala:204:14] input io_core_dis_uops_0_bits_is_fencei, // @[lsu.scala:204:14] input io_core_dis_uops_0_bits_is_amo, // @[lsu.scala:204:14] input io_core_dis_uops_0_bits_uses_ldq, // @[lsu.scala:204:14] input io_core_dis_uops_0_bits_uses_stq, // @[lsu.scala:204:14] input io_core_dis_uops_0_bits_is_sys_pc2epc, // @[lsu.scala:204:14] input io_core_dis_uops_0_bits_is_unique, // @[lsu.scala:204:14] input io_core_dis_uops_0_bits_flush_on_commit, // @[lsu.scala:204:14] input io_core_dis_uops_0_bits_ldst_is_rs1, // @[lsu.scala:204:14] input [5:0] io_core_dis_uops_0_bits_ldst, // @[lsu.scala:204:14] input [5:0] io_core_dis_uops_0_bits_lrs1, // @[lsu.scala:204:14] input [5:0] io_core_dis_uops_0_bits_lrs2, // @[lsu.scala:204:14] input [5:0] io_core_dis_uops_0_bits_lrs3, // @[lsu.scala:204:14] input io_core_dis_uops_0_bits_ldst_val, // @[lsu.scala:204:14] input [1:0] io_core_dis_uops_0_bits_dst_rtype, // @[lsu.scala:204:14] input [1:0] io_core_dis_uops_0_bits_lrs1_rtype, // @[lsu.scala:204:14] input [1:0] io_core_dis_uops_0_bits_lrs2_rtype, // @[lsu.scala:204:14] input io_core_dis_uops_0_bits_frs3_en, // @[lsu.scala:204:14] input io_core_dis_uops_0_bits_fp_val, // @[lsu.scala:204:14] input io_core_dis_uops_0_bits_fp_single, // @[lsu.scala:204:14] input io_core_dis_uops_0_bits_xcpt_pf_if, // @[lsu.scala:204:14] input io_core_dis_uops_0_bits_xcpt_ae_if, // @[lsu.scala:204:14] input io_core_dis_uops_0_bits_xcpt_ma_if, // @[lsu.scala:204:14] input io_core_dis_uops_0_bits_bp_debug_if, // @[lsu.scala:204:14] input io_core_dis_uops_0_bits_bp_xcpt_if, // @[lsu.scala:204:14] input [1:0] io_core_dis_uops_0_bits_debug_fsrc, // @[lsu.scala:204:14] input [1:0] io_core_dis_uops_0_bits_debug_tsrc, // @[lsu.scala:204:14] output [2:0] io_core_dis_ldq_idx_0, // @[lsu.scala:204:14] output [2:0] io_core_dis_stq_idx_0, // @[lsu.scala:204:14] output io_core_ldq_full_0, // @[lsu.scala:204:14] output io_core_stq_full_0, // @[lsu.scala:204:14] output io_core_fp_stdata_ready, // @[lsu.scala:204:14] input io_core_fp_stdata_valid, // @[lsu.scala:204:14] input [6:0] io_core_fp_stdata_bits_uop_uopc, // @[lsu.scala:204:14] input [31:0] io_core_fp_stdata_bits_uop_inst, // @[lsu.scala:204:14] input [31:0] io_core_fp_stdata_bits_uop_debug_inst, // @[lsu.scala:204:14] input io_core_fp_stdata_bits_uop_is_rvc, // @[lsu.scala:204:14] input [39:0] io_core_fp_stdata_bits_uop_debug_pc, // @[lsu.scala:204:14] input [2:0] io_core_fp_stdata_bits_uop_iq_type, // @[lsu.scala:204:14] input [9:0] io_core_fp_stdata_bits_uop_fu_code, // @[lsu.scala:204:14] input [3:0] io_core_fp_stdata_bits_uop_ctrl_br_type, // @[lsu.scala:204:14] input [1:0] io_core_fp_stdata_bits_uop_ctrl_op1_sel, // @[lsu.scala:204:14] input [2:0] io_core_fp_stdata_bits_uop_ctrl_op2_sel, // @[lsu.scala:204:14] input [2:0] io_core_fp_stdata_bits_uop_ctrl_imm_sel, // @[lsu.scala:204:14] input [4:0] io_core_fp_stdata_bits_uop_ctrl_op_fcn, // @[lsu.scala:204:14] input io_core_fp_stdata_bits_uop_ctrl_fcn_dw, // @[lsu.scala:204:14] input [2:0] io_core_fp_stdata_bits_uop_ctrl_csr_cmd, // @[lsu.scala:204:14] input io_core_fp_stdata_bits_uop_ctrl_is_load, // @[lsu.scala:204:14] input io_core_fp_stdata_bits_uop_ctrl_is_sta, // @[lsu.scala:204:14] input io_core_fp_stdata_bits_uop_ctrl_is_std, // @[lsu.scala:204:14] input [1:0] io_core_fp_stdata_bits_uop_iw_state, // @[lsu.scala:204:14] input io_core_fp_stdata_bits_uop_iw_p1_poisoned, // @[lsu.scala:204:14] input io_core_fp_stdata_bits_uop_iw_p2_poisoned, // @[lsu.scala:204:14] input io_core_fp_stdata_bits_uop_is_br, // @[lsu.scala:204:14] input io_core_fp_stdata_bits_uop_is_jalr, // @[lsu.scala:204:14] input io_core_fp_stdata_bits_uop_is_jal, // @[lsu.scala:204:14] input io_core_fp_stdata_bits_uop_is_sfb, // @[lsu.scala:204:14] input [7:0] io_core_fp_stdata_bits_uop_br_mask, // @[lsu.scala:204:14] input [2:0] io_core_fp_stdata_bits_uop_br_tag, // @[lsu.scala:204:14] input [3:0] io_core_fp_stdata_bits_uop_ftq_idx, // @[lsu.scala:204:14] input io_core_fp_stdata_bits_uop_edge_inst, // @[lsu.scala:204:14] input [5:0] io_core_fp_stdata_bits_uop_pc_lob, // @[lsu.scala:204:14] input io_core_fp_stdata_bits_uop_taken, // @[lsu.scala:204:14] input [19:0] io_core_fp_stdata_bits_uop_imm_packed, // @[lsu.scala:204:14] input [11:0] io_core_fp_stdata_bits_uop_csr_addr, // @[lsu.scala:204:14] input [4:0] io_core_fp_stdata_bits_uop_rob_idx, // @[lsu.scala:204:14] input [2:0] io_core_fp_stdata_bits_uop_ldq_idx, // @[lsu.scala:204:14] input [2:0] io_core_fp_stdata_bits_uop_stq_idx, // @[lsu.scala:204:14] input [1:0] io_core_fp_stdata_bits_uop_rxq_idx, // @[lsu.scala:204:14] input [5:0] io_core_fp_stdata_bits_uop_pdst, // @[lsu.scala:204:14] input [5:0] io_core_fp_stdata_bits_uop_prs1, // @[lsu.scala:204:14] input [5:0] io_core_fp_stdata_bits_uop_prs2, // @[lsu.scala:204:14] input [5:0] io_core_fp_stdata_bits_uop_prs3, // @[lsu.scala:204:14] input [3:0] io_core_fp_stdata_bits_uop_ppred, // @[lsu.scala:204:14] input io_core_fp_stdata_bits_uop_prs1_busy, // @[lsu.scala:204:14] input io_core_fp_stdata_bits_uop_prs2_busy, // @[lsu.scala:204:14] input io_core_fp_stdata_bits_uop_prs3_busy, // @[lsu.scala:204:14] input io_core_fp_stdata_bits_uop_ppred_busy, // @[lsu.scala:204:14] input [5:0] io_core_fp_stdata_bits_uop_stale_pdst, // @[lsu.scala:204:14] input io_core_fp_stdata_bits_uop_exception, // @[lsu.scala:204:14] input [63:0] io_core_fp_stdata_bits_uop_exc_cause, // @[lsu.scala:204:14] input io_core_fp_stdata_bits_uop_bypassable, // @[lsu.scala:204:14] input [4:0] io_core_fp_stdata_bits_uop_mem_cmd, // @[lsu.scala:204:14] input [1:0] io_core_fp_stdata_bits_uop_mem_size, // @[lsu.scala:204:14] input io_core_fp_stdata_bits_uop_mem_signed, // @[lsu.scala:204:14] input io_core_fp_stdata_bits_uop_is_fence, // @[lsu.scala:204:14] input io_core_fp_stdata_bits_uop_is_fencei, // @[lsu.scala:204:14] input io_core_fp_stdata_bits_uop_is_amo, // @[lsu.scala:204:14] input io_core_fp_stdata_bits_uop_uses_ldq, // @[lsu.scala:204:14] input io_core_fp_stdata_bits_uop_uses_stq, // @[lsu.scala:204:14] input io_core_fp_stdata_bits_uop_is_sys_pc2epc, // @[lsu.scala:204:14] input io_core_fp_stdata_bits_uop_is_unique, // @[lsu.scala:204:14] input io_core_fp_stdata_bits_uop_flush_on_commit, // @[lsu.scala:204:14] input io_core_fp_stdata_bits_uop_ldst_is_rs1, // @[lsu.scala:204:14] input [5:0] io_core_fp_stdata_bits_uop_ldst, // @[lsu.scala:204:14] input [5:0] io_core_fp_stdata_bits_uop_lrs1, // @[lsu.scala:204:14] input [5:0] io_core_fp_stdata_bits_uop_lrs2, // @[lsu.scala:204:14] input [5:0] io_core_fp_stdata_bits_uop_lrs3, // @[lsu.scala:204:14] input io_core_fp_stdata_bits_uop_ldst_val, // @[lsu.scala:204:14] input [1:0] io_core_fp_stdata_bits_uop_dst_rtype, // @[lsu.scala:204:14] input [1:0] io_core_fp_stdata_bits_uop_lrs1_rtype, // @[lsu.scala:204:14] input [1:0] io_core_fp_stdata_bits_uop_lrs2_rtype, // @[lsu.scala:204:14] input io_core_fp_stdata_bits_uop_frs3_en, // @[lsu.scala:204:14] input io_core_fp_stdata_bits_uop_fp_val, // @[lsu.scala:204:14] input io_core_fp_stdata_bits_uop_fp_single, // @[lsu.scala:204:14] input io_core_fp_stdata_bits_uop_xcpt_pf_if, // @[lsu.scala:204:14] input io_core_fp_stdata_bits_uop_xcpt_ae_if, // @[lsu.scala:204:14] input io_core_fp_stdata_bits_uop_xcpt_ma_if, // @[lsu.scala:204:14] input io_core_fp_stdata_bits_uop_bp_debug_if, // @[lsu.scala:204:14] input io_core_fp_stdata_bits_uop_bp_xcpt_if, // @[lsu.scala:204:14] input [1:0] io_core_fp_stdata_bits_uop_debug_fsrc, // @[lsu.scala:204:14] input [1:0] io_core_fp_stdata_bits_uop_debug_tsrc, // @[lsu.scala:204:14] input [63:0] io_core_fp_stdata_bits_data, // @[lsu.scala:204:14] input io_core_fp_stdata_bits_predicated, // @[lsu.scala:204:14] input io_core_fp_stdata_bits_fflags_valid, // @[lsu.scala:204:14] input [6:0] io_core_fp_stdata_bits_fflags_bits_uop_uopc, // @[lsu.scala:204:14] input [31:0] io_core_fp_stdata_bits_fflags_bits_uop_inst, // @[lsu.scala:204:14] input [31:0] io_core_fp_stdata_bits_fflags_bits_uop_debug_inst, // @[lsu.scala:204:14] input io_core_fp_stdata_bits_fflags_bits_uop_is_rvc, // @[lsu.scala:204:14] input [39:0] io_core_fp_stdata_bits_fflags_bits_uop_debug_pc, // @[lsu.scala:204:14] input [2:0] io_core_fp_stdata_bits_fflags_bits_uop_iq_type, // @[lsu.scala:204:14] input [9:0] io_core_fp_stdata_bits_fflags_bits_uop_fu_code, // @[lsu.scala:204:14] input [3:0] io_core_fp_stdata_bits_fflags_bits_uop_ctrl_br_type, // @[lsu.scala:204:14] input [1:0] io_core_fp_stdata_bits_fflags_bits_uop_ctrl_op1_sel, // @[lsu.scala:204:14] input [2:0] io_core_fp_stdata_bits_fflags_bits_uop_ctrl_op2_sel, // @[lsu.scala:204:14] input [2:0] io_core_fp_stdata_bits_fflags_bits_uop_ctrl_imm_sel, // @[lsu.scala:204:14] input [4:0] io_core_fp_stdata_bits_fflags_bits_uop_ctrl_op_fcn, // @[lsu.scala:204:14] input io_core_fp_stdata_bits_fflags_bits_uop_ctrl_fcn_dw, // @[lsu.scala:204:14] input [2:0] io_core_fp_stdata_bits_fflags_bits_uop_ctrl_csr_cmd, // @[lsu.scala:204:14] input io_core_fp_stdata_bits_fflags_bits_uop_ctrl_is_load, // @[lsu.scala:204:14] input io_core_fp_stdata_bits_fflags_bits_uop_ctrl_is_sta, // @[lsu.scala:204:14] input io_core_fp_stdata_bits_fflags_bits_uop_ctrl_is_std, // @[lsu.scala:204:14] input [1:0] io_core_fp_stdata_bits_fflags_bits_uop_iw_state, // @[lsu.scala:204:14] input io_core_fp_stdata_bits_fflags_bits_uop_iw_p1_poisoned, // @[lsu.scala:204:14] input io_core_fp_stdata_bits_fflags_bits_uop_iw_p2_poisoned, // @[lsu.scala:204:14] input io_core_fp_stdata_bits_fflags_bits_uop_is_br, // @[lsu.scala:204:14] input io_core_fp_stdata_bits_fflags_bits_uop_is_jalr, // @[lsu.scala:204:14] input io_core_fp_stdata_bits_fflags_bits_uop_is_jal, // @[lsu.scala:204:14] input io_core_fp_stdata_bits_fflags_bits_uop_is_sfb, // @[lsu.scala:204:14] input [7:0] io_core_fp_stdata_bits_fflags_bits_uop_br_mask, // @[lsu.scala:204:14] input [2:0] io_core_fp_stdata_bits_fflags_bits_uop_br_tag, // @[lsu.scala:204:14] input [3:0] io_core_fp_stdata_bits_fflags_bits_uop_ftq_idx, // @[lsu.scala:204:14] input io_core_fp_stdata_bits_fflags_bits_uop_edge_inst, // @[lsu.scala:204:14] input [5:0] io_core_fp_stdata_bits_fflags_bits_uop_pc_lob, // @[lsu.scala:204:14] input io_core_fp_stdata_bits_fflags_bits_uop_taken, // @[lsu.scala:204:14] input [19:0] io_core_fp_stdata_bits_fflags_bits_uop_imm_packed, // @[lsu.scala:204:14] input [11:0] io_core_fp_stdata_bits_fflags_bits_uop_csr_addr, // @[lsu.scala:204:14] input [4:0] io_core_fp_stdata_bits_fflags_bits_uop_rob_idx, // @[lsu.scala:204:14] input [2:0] io_core_fp_stdata_bits_fflags_bits_uop_ldq_idx, // @[lsu.scala:204:14] input [2:0] io_core_fp_stdata_bits_fflags_bits_uop_stq_idx, // @[lsu.scala:204:14] input [1:0] io_core_fp_stdata_bits_fflags_bits_uop_rxq_idx, // @[lsu.scala:204:14] input [5:0] io_core_fp_stdata_bits_fflags_bits_uop_pdst, // @[lsu.scala:204:14] input [5:0] io_core_fp_stdata_bits_fflags_bits_uop_prs1, // @[lsu.scala:204:14] input [5:0] io_core_fp_stdata_bits_fflags_bits_uop_prs2, // @[lsu.scala:204:14] input [5:0] io_core_fp_stdata_bits_fflags_bits_uop_prs3, // @[lsu.scala:204:14] input [3:0] io_core_fp_stdata_bits_fflags_bits_uop_ppred, // @[lsu.scala:204:14] input io_core_fp_stdata_bits_fflags_bits_uop_prs1_busy, // @[lsu.scala:204:14] input io_core_fp_stdata_bits_fflags_bits_uop_prs2_busy, // @[lsu.scala:204:14] input io_core_fp_stdata_bits_fflags_bits_uop_prs3_busy, // @[lsu.scala:204:14] input io_core_fp_stdata_bits_fflags_bits_uop_ppred_busy, // @[lsu.scala:204:14] input [5:0] io_core_fp_stdata_bits_fflags_bits_uop_stale_pdst, // @[lsu.scala:204:14] input io_core_fp_stdata_bits_fflags_bits_uop_exception, // @[lsu.scala:204:14] input [63:0] io_core_fp_stdata_bits_fflags_bits_uop_exc_cause, // @[lsu.scala:204:14] input io_core_fp_stdata_bits_fflags_bits_uop_bypassable, // @[lsu.scala:204:14] input [4:0] io_core_fp_stdata_bits_fflags_bits_uop_mem_cmd, // @[lsu.scala:204:14] input [1:0] io_core_fp_stdata_bits_fflags_bits_uop_mem_size, // @[lsu.scala:204:14] input io_core_fp_stdata_bits_fflags_bits_uop_mem_signed, // @[lsu.scala:204:14] input io_core_fp_stdata_bits_fflags_bits_uop_is_fence, // @[lsu.scala:204:14] input io_core_fp_stdata_bits_fflags_bits_uop_is_fencei, // @[lsu.scala:204:14] input io_core_fp_stdata_bits_fflags_bits_uop_is_amo, // @[lsu.scala:204:14] input io_core_fp_stdata_bits_fflags_bits_uop_uses_ldq, // @[lsu.scala:204:14] input io_core_fp_stdata_bits_fflags_bits_uop_uses_stq, // @[lsu.scala:204:14] input io_core_fp_stdata_bits_fflags_bits_uop_is_sys_pc2epc, // @[lsu.scala:204:14] input io_core_fp_stdata_bits_fflags_bits_uop_is_unique, // @[lsu.scala:204:14] input io_core_fp_stdata_bits_fflags_bits_uop_flush_on_commit, // @[lsu.scala:204:14] input io_core_fp_stdata_bits_fflags_bits_uop_ldst_is_rs1, // @[lsu.scala:204:14] input [5:0] io_core_fp_stdata_bits_fflags_bits_uop_ldst, // @[lsu.scala:204:14] input [5:0] io_core_fp_stdata_bits_fflags_bits_uop_lrs1, // @[lsu.scala:204:14] input [5:0] io_core_fp_stdata_bits_fflags_bits_uop_lrs2, // @[lsu.scala:204:14] input [5:0] io_core_fp_stdata_bits_fflags_bits_uop_lrs3, // @[lsu.scala:204:14] input io_core_fp_stdata_bits_fflags_bits_uop_ldst_val, // @[lsu.scala:204:14] input [1:0] io_core_fp_stdata_bits_fflags_bits_uop_dst_rtype, // @[lsu.scala:204:14] input [1:0] io_core_fp_stdata_bits_fflags_bits_uop_lrs1_rtype, // @[lsu.scala:204:14] input [1:0] io_core_fp_stdata_bits_fflags_bits_uop_lrs2_rtype, // @[lsu.scala:204:14] input io_core_fp_stdata_bits_fflags_bits_uop_frs3_en, // @[lsu.scala:204:14] input io_core_fp_stdata_bits_fflags_bits_uop_fp_val, // @[lsu.scala:204:14] input io_core_fp_stdata_bits_fflags_bits_uop_fp_single, // @[lsu.scala:204:14] input io_core_fp_stdata_bits_fflags_bits_uop_xcpt_pf_if, // @[lsu.scala:204:14] input io_core_fp_stdata_bits_fflags_bits_uop_xcpt_ae_if, // @[lsu.scala:204:14] input io_core_fp_stdata_bits_fflags_bits_uop_xcpt_ma_if, // @[lsu.scala:204:14] input io_core_fp_stdata_bits_fflags_bits_uop_bp_debug_if, // @[lsu.scala:204:14] input io_core_fp_stdata_bits_fflags_bits_uop_bp_xcpt_if, // @[lsu.scala:204:14] input [1:0] io_core_fp_stdata_bits_fflags_bits_uop_debug_fsrc, // @[lsu.scala:204:14] input [1:0] io_core_fp_stdata_bits_fflags_bits_uop_debug_tsrc, // @[lsu.scala:204:14] input [4:0] io_core_fp_stdata_bits_fflags_bits_flags, // @[lsu.scala:204:14] input io_core_commit_valids_0, // @[lsu.scala:204:14] input io_core_commit_arch_valids_0, // @[lsu.scala:204:14] input [6:0] io_core_commit_uops_0_uopc, // @[lsu.scala:204:14] input [31:0] io_core_commit_uops_0_inst, // @[lsu.scala:204:14] input [31:0] io_core_commit_uops_0_debug_inst, // @[lsu.scala:204:14] input io_core_commit_uops_0_is_rvc, // @[lsu.scala:204:14] input [39:0] io_core_commit_uops_0_debug_pc, // @[lsu.scala:204:14] input [2:0] io_core_commit_uops_0_iq_type, // @[lsu.scala:204:14] input [9:0] io_core_commit_uops_0_fu_code, // @[lsu.scala:204:14] input [3:0] io_core_commit_uops_0_ctrl_br_type, // @[lsu.scala:204:14] input [1:0] io_core_commit_uops_0_ctrl_op1_sel, // @[lsu.scala:204:14] input [2:0] io_core_commit_uops_0_ctrl_op2_sel, // @[lsu.scala:204:14] input [2:0] io_core_commit_uops_0_ctrl_imm_sel, // @[lsu.scala:204:14] input [4:0] io_core_commit_uops_0_ctrl_op_fcn, // @[lsu.scala:204:14] input io_core_commit_uops_0_ctrl_fcn_dw, // @[lsu.scala:204:14] input [2:0] io_core_commit_uops_0_ctrl_csr_cmd, // @[lsu.scala:204:14] input io_core_commit_uops_0_ctrl_is_load, // @[lsu.scala:204:14] input io_core_commit_uops_0_ctrl_is_sta, // @[lsu.scala:204:14] input io_core_commit_uops_0_ctrl_is_std, // @[lsu.scala:204:14] input [1:0] io_core_commit_uops_0_iw_state, // @[lsu.scala:204:14] input io_core_commit_uops_0_iw_p1_poisoned, // @[lsu.scala:204:14] input io_core_commit_uops_0_iw_p2_poisoned, // @[lsu.scala:204:14] input io_core_commit_uops_0_is_br, // @[lsu.scala:204:14] input io_core_commit_uops_0_is_jalr, // @[lsu.scala:204:14] input io_core_commit_uops_0_is_jal, // @[lsu.scala:204:14] input io_core_commit_uops_0_is_sfb, // @[lsu.scala:204:14] input [7:0] io_core_commit_uops_0_br_mask, // @[lsu.scala:204:14] input [2:0] io_core_commit_uops_0_br_tag, // @[lsu.scala:204:14] input [3:0] io_core_commit_uops_0_ftq_idx, // @[lsu.scala:204:14] input io_core_commit_uops_0_edge_inst, // @[lsu.scala:204:14] input [5:0] io_core_commit_uops_0_pc_lob, // @[lsu.scala:204:14] input io_core_commit_uops_0_taken, // @[lsu.scala:204:14] input [19:0] io_core_commit_uops_0_imm_packed, // @[lsu.scala:204:14] input [11:0] io_core_commit_uops_0_csr_addr, // @[lsu.scala:204:14] input [4:0] io_core_commit_uops_0_rob_idx, // @[lsu.scala:204:14] input [2:0] io_core_commit_uops_0_ldq_idx, // @[lsu.scala:204:14] input [2:0] io_core_commit_uops_0_stq_idx, // @[lsu.scala:204:14] input [1:0] io_core_commit_uops_0_rxq_idx, // @[lsu.scala:204:14] input [5:0] io_core_commit_uops_0_pdst, // @[lsu.scala:204:14] input [5:0] io_core_commit_uops_0_prs1, // @[lsu.scala:204:14] input [5:0] io_core_commit_uops_0_prs2, // @[lsu.scala:204:14] input [5:0] io_core_commit_uops_0_prs3, // @[lsu.scala:204:14] input [3:0] io_core_commit_uops_0_ppred, // @[lsu.scala:204:14] input io_core_commit_uops_0_prs1_busy, // @[lsu.scala:204:14] input io_core_commit_uops_0_prs2_busy, // @[lsu.scala:204:14] input io_core_commit_uops_0_prs3_busy, // @[lsu.scala:204:14] input io_core_commit_uops_0_ppred_busy, // @[lsu.scala:204:14] input [5:0] io_core_commit_uops_0_stale_pdst, // @[lsu.scala:204:14] input io_core_commit_uops_0_exception, // @[lsu.scala:204:14] input [63:0] io_core_commit_uops_0_exc_cause, // @[lsu.scala:204:14] input io_core_commit_uops_0_bypassable, // @[lsu.scala:204:14] input [4:0] io_core_commit_uops_0_mem_cmd, // @[lsu.scala:204:14] input [1:0] io_core_commit_uops_0_mem_size, // @[lsu.scala:204:14] input io_core_commit_uops_0_mem_signed, // @[lsu.scala:204:14] input io_core_commit_uops_0_is_fence, // @[lsu.scala:204:14] input io_core_commit_uops_0_is_fencei, // @[lsu.scala:204:14] input io_core_commit_uops_0_is_amo, // @[lsu.scala:204:14] input io_core_commit_uops_0_uses_ldq, // @[lsu.scala:204:14] input io_core_commit_uops_0_uses_stq, // @[lsu.scala:204:14] input io_core_commit_uops_0_is_sys_pc2epc, // @[lsu.scala:204:14] input io_core_commit_uops_0_is_unique, // @[lsu.scala:204:14] input io_core_commit_uops_0_flush_on_commit, // @[lsu.scala:204:14] input io_core_commit_uops_0_ldst_is_rs1, // @[lsu.scala:204:14] input [5:0] io_core_commit_uops_0_ldst, // @[lsu.scala:204:14] input [5:0] io_core_commit_uops_0_lrs1, // @[lsu.scala:204:14] input [5:0] io_core_commit_uops_0_lrs2, // @[lsu.scala:204:14] input [5:0] io_core_commit_uops_0_lrs3, // @[lsu.scala:204:14] input io_core_commit_uops_0_ldst_val, // @[lsu.scala:204:14] input [1:0] io_core_commit_uops_0_dst_rtype, // @[lsu.scala:204:14] input [1:0] io_core_commit_uops_0_lrs1_rtype, // @[lsu.scala:204:14] input [1:0] io_core_commit_uops_0_lrs2_rtype, // @[lsu.scala:204:14] input io_core_commit_uops_0_frs3_en, // @[lsu.scala:204:14] input io_core_commit_uops_0_fp_val, // @[lsu.scala:204:14] input io_core_commit_uops_0_fp_single, // @[lsu.scala:204:14] input io_core_commit_uops_0_xcpt_pf_if, // @[lsu.scala:204:14] input io_core_commit_uops_0_xcpt_ae_if, // @[lsu.scala:204:14] input io_core_commit_uops_0_xcpt_ma_if, // @[lsu.scala:204:14] input io_core_commit_uops_0_bp_debug_if, // @[lsu.scala:204:14] input io_core_commit_uops_0_bp_xcpt_if, // @[lsu.scala:204:14] input [1:0] io_core_commit_uops_0_debug_fsrc, // @[lsu.scala:204:14] input [1:0] io_core_commit_uops_0_debug_tsrc, // @[lsu.scala:204:14] input io_core_commit_fflags_valid, // @[lsu.scala:204:14] input [4:0] io_core_commit_fflags_bits, // @[lsu.scala:204:14] input [31:0] io_core_commit_debug_insts_0, // @[lsu.scala:204:14] input io_core_commit_rbk_valids_0, // @[lsu.scala:204:14] input io_core_commit_rollback, // @[lsu.scala:204:14] input [63:0] io_core_commit_debug_wdata_0, // @[lsu.scala:204:14] input io_core_commit_load_at_rob_head, // @[lsu.scala:204:14] output io_core_clr_bsy_0_valid, // @[lsu.scala:204:14] output [4:0] io_core_clr_bsy_0_bits, // @[lsu.scala:204:14] output io_core_clr_bsy_1_valid, // @[lsu.scala:204:14] output [4:0] io_core_clr_bsy_1_bits, // @[lsu.scala:204:14] output [4:0] io_core_clr_unsafe_0_bits, // @[lsu.scala:204:14] input io_core_fence_dmem, // @[lsu.scala:204:14] output io_core_spec_ld_wakeup_0_valid, // @[lsu.scala:204:14] output [5:0] io_core_spec_ld_wakeup_0_bits, // @[lsu.scala:204:14] output io_core_ld_miss, // @[lsu.scala:204:14] input [7:0] io_core_brupdate_b1_resolve_mask, // @[lsu.scala:204:14] input [7:0] io_core_brupdate_b1_mispredict_mask, // @[lsu.scala:204:14] input [6:0] io_core_brupdate_b2_uop_uopc, // @[lsu.scala:204:14] input [31:0] io_core_brupdate_b2_uop_inst, // @[lsu.scala:204:14] input [31:0] io_core_brupdate_b2_uop_debug_inst, // @[lsu.scala:204:14] input io_core_brupdate_b2_uop_is_rvc, // @[lsu.scala:204:14] input [39:0] io_core_brupdate_b2_uop_debug_pc, // @[lsu.scala:204:14] input [2:0] io_core_brupdate_b2_uop_iq_type, // @[lsu.scala:204:14] input [9:0] io_core_brupdate_b2_uop_fu_code, // @[lsu.scala:204:14] input [3:0] io_core_brupdate_b2_uop_ctrl_br_type, // @[lsu.scala:204:14] input [1:0] io_core_brupdate_b2_uop_ctrl_op1_sel, // @[lsu.scala:204:14] input [2:0] io_core_brupdate_b2_uop_ctrl_op2_sel, // @[lsu.scala:204:14] input [2:0] io_core_brupdate_b2_uop_ctrl_imm_sel, // @[lsu.scala:204:14] input [4:0] io_core_brupdate_b2_uop_ctrl_op_fcn, // @[lsu.scala:204:14] input io_core_brupdate_b2_uop_ctrl_fcn_dw, // @[lsu.scala:204:14] input [2:0] io_core_brupdate_b2_uop_ctrl_csr_cmd, // @[lsu.scala:204:14] input io_core_brupdate_b2_uop_ctrl_is_load, // @[lsu.scala:204:14] input io_core_brupdate_b2_uop_ctrl_is_sta, // @[lsu.scala:204:14] input io_core_brupdate_b2_uop_ctrl_is_std, // @[lsu.scala:204:14] input [1:0] io_core_brupdate_b2_uop_iw_state, // @[lsu.scala:204:14] input io_core_brupdate_b2_uop_iw_p1_poisoned, // @[lsu.scala:204:14] input io_core_brupdate_b2_uop_iw_p2_poisoned, // @[lsu.scala:204:14] input io_core_brupdate_b2_uop_is_br, // @[lsu.scala:204:14] input io_core_brupdate_b2_uop_is_jalr, // @[lsu.scala:204:14] input io_core_brupdate_b2_uop_is_jal, // @[lsu.scala:204:14] input io_core_brupdate_b2_uop_is_sfb, // @[lsu.scala:204:14] input [7:0] io_core_brupdate_b2_uop_br_mask, // @[lsu.scala:204:14] input [2:0] io_core_brupdate_b2_uop_br_tag, // @[lsu.scala:204:14] input [3:0] io_core_brupdate_b2_uop_ftq_idx, // @[lsu.scala:204:14] input io_core_brupdate_b2_uop_edge_inst, // @[lsu.scala:204:14] input [5:0] io_core_brupdate_b2_uop_pc_lob, // @[lsu.scala:204:14] input io_core_brupdate_b2_uop_taken, // @[lsu.scala:204:14] input [19:0] io_core_brupdate_b2_uop_imm_packed, // @[lsu.scala:204:14] input [11:0] io_core_brupdate_b2_uop_csr_addr, // @[lsu.scala:204:14] input [4:0] io_core_brupdate_b2_uop_rob_idx, // @[lsu.scala:204:14] input [2:0] io_core_brupdate_b2_uop_ldq_idx, // @[lsu.scala:204:14] input [2:0] io_core_brupdate_b2_uop_stq_idx, // @[lsu.scala:204:14] input [1:0] io_core_brupdate_b2_uop_rxq_idx, // @[lsu.scala:204:14] input [5:0] io_core_brupdate_b2_uop_pdst, // @[lsu.scala:204:14] input [5:0] io_core_brupdate_b2_uop_prs1, // @[lsu.scala:204:14] input [5:0] io_core_brupdate_b2_uop_prs2, // @[lsu.scala:204:14] input [5:0] io_core_brupdate_b2_uop_prs3, // @[lsu.scala:204:14] input [3:0] io_core_brupdate_b2_uop_ppred, // @[lsu.scala:204:14] input io_core_brupdate_b2_uop_prs1_busy, // @[lsu.scala:204:14] input io_core_brupdate_b2_uop_prs2_busy, // @[lsu.scala:204:14] input io_core_brupdate_b2_uop_prs3_busy, // @[lsu.scala:204:14] input io_core_brupdate_b2_uop_ppred_busy, // @[lsu.scala:204:14] input [5:0] io_core_brupdate_b2_uop_stale_pdst, // @[lsu.scala:204:14] input io_core_brupdate_b2_uop_exception, // @[lsu.scala:204:14] input [63:0] io_core_brupdate_b2_uop_exc_cause, // @[lsu.scala:204:14] input io_core_brupdate_b2_uop_bypassable, // @[lsu.scala:204:14] input [4:0] io_core_brupdate_b2_uop_mem_cmd, // @[lsu.scala:204:14] input [1:0] io_core_brupdate_b2_uop_mem_size, // @[lsu.scala:204:14] input io_core_brupdate_b2_uop_mem_signed, // @[lsu.scala:204:14] input io_core_brupdate_b2_uop_is_fence, // @[lsu.scala:204:14] input io_core_brupdate_b2_uop_is_fencei, // @[lsu.scala:204:14] input io_core_brupdate_b2_uop_is_amo, // @[lsu.scala:204:14] input io_core_brupdate_b2_uop_uses_ldq, // @[lsu.scala:204:14] input io_core_brupdate_b2_uop_uses_stq, // @[lsu.scala:204:14] input io_core_brupdate_b2_uop_is_sys_pc2epc, // @[lsu.scala:204:14] input io_core_brupdate_b2_uop_is_unique, // @[lsu.scala:204:14] input io_core_brupdate_b2_uop_flush_on_commit, // @[lsu.scala:204:14] input io_core_brupdate_b2_uop_ldst_is_rs1, // @[lsu.scala:204:14] input [5:0] io_core_brupdate_b2_uop_ldst, // @[lsu.scala:204:14] input [5:0] io_core_brupdate_b2_uop_lrs1, // @[lsu.scala:204:14] input [5:0] io_core_brupdate_b2_uop_lrs2, // @[lsu.scala:204:14] input [5:0] io_core_brupdate_b2_uop_lrs3, // @[lsu.scala:204:14] input io_core_brupdate_b2_uop_ldst_val, // @[lsu.scala:204:14] input [1:0] io_core_brupdate_b2_uop_dst_rtype, // @[lsu.scala:204:14] input [1:0] io_core_brupdate_b2_uop_lrs1_rtype, // @[lsu.scala:204:14] input [1:0] io_core_brupdate_b2_uop_lrs2_rtype, // @[lsu.scala:204:14] input io_core_brupdate_b2_uop_frs3_en, // @[lsu.scala:204:14] input io_core_brupdate_b2_uop_fp_val, // @[lsu.scala:204:14] input io_core_brupdate_b2_uop_fp_single, // @[lsu.scala:204:14] input io_core_brupdate_b2_uop_xcpt_pf_if, // @[lsu.scala:204:14] input io_core_brupdate_b2_uop_xcpt_ae_if, // @[lsu.scala:204:14] input io_core_brupdate_b2_uop_xcpt_ma_if, // @[lsu.scala:204:14] input io_core_brupdate_b2_uop_bp_debug_if, // @[lsu.scala:204:14] input io_core_brupdate_b2_uop_bp_xcpt_if, // @[lsu.scala:204:14] input [1:0] io_core_brupdate_b2_uop_debug_fsrc, // @[lsu.scala:204:14] input [1:0] io_core_brupdate_b2_uop_debug_tsrc, // @[lsu.scala:204:14] input io_core_brupdate_b2_valid, // @[lsu.scala:204:14] input io_core_brupdate_b2_mispredict, // @[lsu.scala:204:14] input io_core_brupdate_b2_taken, // @[lsu.scala:204:14] input [2:0] io_core_brupdate_b2_cfi_type, // @[lsu.scala:204:14] input [1:0] io_core_brupdate_b2_pc_sel, // @[lsu.scala:204:14] input [39:0] io_core_brupdate_b2_jalr_target, // @[lsu.scala:204:14] input [20:0] io_core_brupdate_b2_target_offset, // @[lsu.scala:204:14] input [4:0] io_core_rob_pnr_idx, // @[lsu.scala:204:14] input [4:0] io_core_rob_head_idx, // @[lsu.scala:204:14] input io_core_exception, // @[lsu.scala:204:14] output io_core_fencei_rdy, // @[lsu.scala:204:14] output io_core_lxcpt_valid, // @[lsu.scala:204:14] output [6:0] io_core_lxcpt_bits_uop_uopc, // @[lsu.scala:204:14] output [31:0] io_core_lxcpt_bits_uop_inst, // @[lsu.scala:204:14] output [31:0] io_core_lxcpt_bits_uop_debug_inst, // @[lsu.scala:204:14] output io_core_lxcpt_bits_uop_is_rvc, // @[lsu.scala:204:14] output [39:0] io_core_lxcpt_bits_uop_debug_pc, // @[lsu.scala:204:14] output [2:0] io_core_lxcpt_bits_uop_iq_type, // @[lsu.scala:204:14] output [9:0] io_core_lxcpt_bits_uop_fu_code, // @[lsu.scala:204:14] output [3:0] io_core_lxcpt_bits_uop_ctrl_br_type, // @[lsu.scala:204:14] output [1:0] io_core_lxcpt_bits_uop_ctrl_op1_sel, // @[lsu.scala:204:14] output [2:0] io_core_lxcpt_bits_uop_ctrl_op2_sel, // @[lsu.scala:204:14] output [2:0] io_core_lxcpt_bits_uop_ctrl_imm_sel, // @[lsu.scala:204:14] output [4:0] io_core_lxcpt_bits_uop_ctrl_op_fcn, // @[lsu.scala:204:14] output io_core_lxcpt_bits_uop_ctrl_fcn_dw, // @[lsu.scala:204:14] output [2:0] io_core_lxcpt_bits_uop_ctrl_csr_cmd, // @[lsu.scala:204:14] output io_core_lxcpt_bits_uop_ctrl_is_load, // @[lsu.scala:204:14] output io_core_lxcpt_bits_uop_ctrl_is_sta, // @[lsu.scala:204:14] output io_core_lxcpt_bits_uop_ctrl_is_std, // @[lsu.scala:204:14] output [1:0] io_core_lxcpt_bits_uop_iw_state, // @[lsu.scala:204:14] output io_core_lxcpt_bits_uop_iw_p1_poisoned, // @[lsu.scala:204:14] output io_core_lxcpt_bits_uop_iw_p2_poisoned, // @[lsu.scala:204:14] output io_core_lxcpt_bits_uop_is_br, // @[lsu.scala:204:14] output io_core_lxcpt_bits_uop_is_jalr, // @[lsu.scala:204:14] output io_core_lxcpt_bits_uop_is_jal, // @[lsu.scala:204:14] output io_core_lxcpt_bits_uop_is_sfb, // @[lsu.scala:204:14] output [7:0] io_core_lxcpt_bits_uop_br_mask, // @[lsu.scala:204:14] output [2:0] io_core_lxcpt_bits_uop_br_tag, // @[lsu.scala:204:14] output [3:0] io_core_lxcpt_bits_uop_ftq_idx, // @[lsu.scala:204:14] output io_core_lxcpt_bits_uop_edge_inst, // @[lsu.scala:204:14] output [5:0] io_core_lxcpt_bits_uop_pc_lob, // @[lsu.scala:204:14] output io_core_lxcpt_bits_uop_taken, // @[lsu.scala:204:14] output [19:0] io_core_lxcpt_bits_uop_imm_packed, // @[lsu.scala:204:14] output [11:0] io_core_lxcpt_bits_uop_csr_addr, // @[lsu.scala:204:14] output [4:0] io_core_lxcpt_bits_uop_rob_idx, // @[lsu.scala:204:14] output [2:0] io_core_lxcpt_bits_uop_ldq_idx, // @[lsu.scala:204:14] output [2:0] io_core_lxcpt_bits_uop_stq_idx, // @[lsu.scala:204:14] output [1:0] io_core_lxcpt_bits_uop_rxq_idx, // @[lsu.scala:204:14] output [5:0] io_core_lxcpt_bits_uop_pdst, // @[lsu.scala:204:14] output [5:0] io_core_lxcpt_bits_uop_prs1, // @[lsu.scala:204:14] output [5:0] io_core_lxcpt_bits_uop_prs2, // @[lsu.scala:204:14] output [5:0] io_core_lxcpt_bits_uop_prs3, // @[lsu.scala:204:14] output [3:0] io_core_lxcpt_bits_uop_ppred, // @[lsu.scala:204:14] output io_core_lxcpt_bits_uop_prs1_busy, // @[lsu.scala:204:14] output io_core_lxcpt_bits_uop_prs2_busy, // @[lsu.scala:204:14] output io_core_lxcpt_bits_uop_prs3_busy, // @[lsu.scala:204:14] output io_core_lxcpt_bits_uop_ppred_busy, // @[lsu.scala:204:14] output [5:0] io_core_lxcpt_bits_uop_stale_pdst, // @[lsu.scala:204:14] output io_core_lxcpt_bits_uop_exception, // @[lsu.scala:204:14] output [63:0] io_core_lxcpt_bits_uop_exc_cause, // @[lsu.scala:204:14] output io_core_lxcpt_bits_uop_bypassable, // @[lsu.scala:204:14] output [4:0] io_core_lxcpt_bits_uop_mem_cmd, // @[lsu.scala:204:14] output [1:0] io_core_lxcpt_bits_uop_mem_size, // @[lsu.scala:204:14] output io_core_lxcpt_bits_uop_mem_signed, // @[lsu.scala:204:14] output io_core_lxcpt_bits_uop_is_fence, // @[lsu.scala:204:14] output io_core_lxcpt_bits_uop_is_fencei, // @[lsu.scala:204:14] output io_core_lxcpt_bits_uop_is_amo, // @[lsu.scala:204:14] output io_core_lxcpt_bits_uop_uses_ldq, // @[lsu.scala:204:14] output io_core_lxcpt_bits_uop_uses_stq, // @[lsu.scala:204:14] output io_core_lxcpt_bits_uop_is_sys_pc2epc, // @[lsu.scala:204:14] output io_core_lxcpt_bits_uop_is_unique, // @[lsu.scala:204:14] output io_core_lxcpt_bits_uop_flush_on_commit, // @[lsu.scala:204:14] output io_core_lxcpt_bits_uop_ldst_is_rs1, // @[lsu.scala:204:14] output [5:0] io_core_lxcpt_bits_uop_ldst, // @[lsu.scala:204:14] output [5:0] io_core_lxcpt_bits_uop_lrs1, // @[lsu.scala:204:14] output [5:0] io_core_lxcpt_bits_uop_lrs2, // @[lsu.scala:204:14] output [5:0] io_core_lxcpt_bits_uop_lrs3, // @[lsu.scala:204:14] output io_core_lxcpt_bits_uop_ldst_val, // @[lsu.scala:204:14] output [1:0] io_core_lxcpt_bits_uop_dst_rtype, // @[lsu.scala:204:14] output [1:0] io_core_lxcpt_bits_uop_lrs1_rtype, // @[lsu.scala:204:14] output [1:0] io_core_lxcpt_bits_uop_lrs2_rtype, // @[lsu.scala:204:14] output io_core_lxcpt_bits_uop_frs3_en, // @[lsu.scala:204:14] output io_core_lxcpt_bits_uop_fp_val, // @[lsu.scala:204:14] output io_core_lxcpt_bits_uop_fp_single, // @[lsu.scala:204:14] output io_core_lxcpt_bits_uop_xcpt_pf_if, // @[lsu.scala:204:14] output io_core_lxcpt_bits_uop_xcpt_ae_if, // @[lsu.scala:204:14] output io_core_lxcpt_bits_uop_xcpt_ma_if, // @[lsu.scala:204:14] output io_core_lxcpt_bits_uop_bp_debug_if, // @[lsu.scala:204:14] output io_core_lxcpt_bits_uop_bp_xcpt_if, // @[lsu.scala:204:14] output [1:0] io_core_lxcpt_bits_uop_debug_fsrc, // @[lsu.scala:204:14] output [1:0] io_core_lxcpt_bits_uop_debug_tsrc, // @[lsu.scala:204:14] output [4:0] io_core_lxcpt_bits_cause, // @[lsu.scala:204:14] output [39:0] io_core_lxcpt_bits_badvaddr, // @[lsu.scala:204:14] input [63:0] io_core_tsc_reg, // @[lsu.scala:204:14] output io_core_perf_acquire, // @[lsu.scala:204:14] output io_core_perf_release, // @[lsu.scala:204:14] output io_core_perf_tlbMiss, // @[lsu.scala:204:14] input io_dmem_req_ready, // @[lsu.scala:204:14] output io_dmem_req_valid, // @[lsu.scala:204:14] output io_dmem_req_bits_0_valid, // @[lsu.scala:204:14] output [6:0] io_dmem_req_bits_0_bits_uop_uopc, // @[lsu.scala:204:14] output [31:0] io_dmem_req_bits_0_bits_uop_inst, // @[lsu.scala:204:14] output [31:0] io_dmem_req_bits_0_bits_uop_debug_inst, // @[lsu.scala:204:14] output io_dmem_req_bits_0_bits_uop_is_rvc, // @[lsu.scala:204:14] output [39:0] io_dmem_req_bits_0_bits_uop_debug_pc, // @[lsu.scala:204:14] output [2:0] io_dmem_req_bits_0_bits_uop_iq_type, // @[lsu.scala:204:14] output [9:0] io_dmem_req_bits_0_bits_uop_fu_code, // @[lsu.scala:204:14] output [3:0] io_dmem_req_bits_0_bits_uop_ctrl_br_type, // @[lsu.scala:204:14] output [1:0] io_dmem_req_bits_0_bits_uop_ctrl_op1_sel, // @[lsu.scala:204:14] output [2:0] io_dmem_req_bits_0_bits_uop_ctrl_op2_sel, // @[lsu.scala:204:14] output [2:0] io_dmem_req_bits_0_bits_uop_ctrl_imm_sel, // @[lsu.scala:204:14] output [4:0] io_dmem_req_bits_0_bits_uop_ctrl_op_fcn, // @[lsu.scala:204:14] output io_dmem_req_bits_0_bits_uop_ctrl_fcn_dw, // @[lsu.scala:204:14] output [2:0] io_dmem_req_bits_0_bits_uop_ctrl_csr_cmd, // @[lsu.scala:204:14] output io_dmem_req_bits_0_bits_uop_ctrl_is_load, // @[lsu.scala:204:14] output io_dmem_req_bits_0_bits_uop_ctrl_is_sta, // @[lsu.scala:204:14] output io_dmem_req_bits_0_bits_uop_ctrl_is_std, // @[lsu.scala:204:14] output [1:0] io_dmem_req_bits_0_bits_uop_iw_state, // @[lsu.scala:204:14] output io_dmem_req_bits_0_bits_uop_iw_p1_poisoned, // @[lsu.scala:204:14] output io_dmem_req_bits_0_bits_uop_iw_p2_poisoned, // @[lsu.scala:204:14] output io_dmem_req_bits_0_bits_uop_is_br, // @[lsu.scala:204:14] output io_dmem_req_bits_0_bits_uop_is_jalr, // @[lsu.scala:204:14] output io_dmem_req_bits_0_bits_uop_is_jal, // @[lsu.scala:204:14] output io_dmem_req_bits_0_bits_uop_is_sfb, // @[lsu.scala:204:14] output [7:0] io_dmem_req_bits_0_bits_uop_br_mask, // @[lsu.scala:204:14] output [2:0] io_dmem_req_bits_0_bits_uop_br_tag, // @[lsu.scala:204:14] output [3:0] io_dmem_req_bits_0_bits_uop_ftq_idx, // @[lsu.scala:204:14] output io_dmem_req_bits_0_bits_uop_edge_inst, // @[lsu.scala:204:14] output [5:0] io_dmem_req_bits_0_bits_uop_pc_lob, // @[lsu.scala:204:14] output io_dmem_req_bits_0_bits_uop_taken, // @[lsu.scala:204:14] output [19:0] io_dmem_req_bits_0_bits_uop_imm_packed, // @[lsu.scala:204:14] output [11:0] io_dmem_req_bits_0_bits_uop_csr_addr, // @[lsu.scala:204:14] output [4:0] io_dmem_req_bits_0_bits_uop_rob_idx, // @[lsu.scala:204:14] output [2:0] io_dmem_req_bits_0_bits_uop_ldq_idx, // @[lsu.scala:204:14] output [2:0] io_dmem_req_bits_0_bits_uop_stq_idx, // @[lsu.scala:204:14] output [1:0] io_dmem_req_bits_0_bits_uop_rxq_idx, // @[lsu.scala:204:14] output [5:0] io_dmem_req_bits_0_bits_uop_pdst, // @[lsu.scala:204:14] output [5:0] io_dmem_req_bits_0_bits_uop_prs1, // @[lsu.scala:204:14] output [5:0] io_dmem_req_bits_0_bits_uop_prs2, // @[lsu.scala:204:14] output [5:0] io_dmem_req_bits_0_bits_uop_prs3, // @[lsu.scala:204:14] output [3:0] io_dmem_req_bits_0_bits_uop_ppred, // @[lsu.scala:204:14] output io_dmem_req_bits_0_bits_uop_prs1_busy, // @[lsu.scala:204:14] output io_dmem_req_bits_0_bits_uop_prs2_busy, // @[lsu.scala:204:14] output io_dmem_req_bits_0_bits_uop_prs3_busy, // @[lsu.scala:204:14] output io_dmem_req_bits_0_bits_uop_ppred_busy, // @[lsu.scala:204:14] output [5:0] io_dmem_req_bits_0_bits_uop_stale_pdst, // @[lsu.scala:204:14] output io_dmem_req_bits_0_bits_uop_exception, // @[lsu.scala:204:14] output [63:0] io_dmem_req_bits_0_bits_uop_exc_cause, // @[lsu.scala:204:14] output io_dmem_req_bits_0_bits_uop_bypassable, // @[lsu.scala:204:14] output [4:0] io_dmem_req_bits_0_bits_uop_mem_cmd, // @[lsu.scala:204:14] output [1:0] io_dmem_req_bits_0_bits_uop_mem_size, // @[lsu.scala:204:14] output io_dmem_req_bits_0_bits_uop_mem_signed, // @[lsu.scala:204:14] output io_dmem_req_bits_0_bits_uop_is_fence, // @[lsu.scala:204:14] output io_dmem_req_bits_0_bits_uop_is_fencei, // @[lsu.scala:204:14] output io_dmem_req_bits_0_bits_uop_is_amo, // @[lsu.scala:204:14] output io_dmem_req_bits_0_bits_uop_uses_ldq, // @[lsu.scala:204:14] output io_dmem_req_bits_0_bits_uop_uses_stq, // @[lsu.scala:204:14] output io_dmem_req_bits_0_bits_uop_is_sys_pc2epc, // @[lsu.scala:204:14] output io_dmem_req_bits_0_bits_uop_is_unique, // @[lsu.scala:204:14] output io_dmem_req_bits_0_bits_uop_flush_on_commit, // @[lsu.scala:204:14] output io_dmem_req_bits_0_bits_uop_ldst_is_rs1, // @[lsu.scala:204:14] output [5:0] io_dmem_req_bits_0_bits_uop_ldst, // @[lsu.scala:204:14] output [5:0] io_dmem_req_bits_0_bits_uop_lrs1, // @[lsu.scala:204:14] output [5:0] io_dmem_req_bits_0_bits_uop_lrs2, // @[lsu.scala:204:14] output [5:0] io_dmem_req_bits_0_bits_uop_lrs3, // @[lsu.scala:204:14] output io_dmem_req_bits_0_bits_uop_ldst_val, // @[lsu.scala:204:14] output [1:0] io_dmem_req_bits_0_bits_uop_dst_rtype, // @[lsu.scala:204:14] output [1:0] io_dmem_req_bits_0_bits_uop_lrs1_rtype, // @[lsu.scala:204:14] output [1:0] io_dmem_req_bits_0_bits_uop_lrs2_rtype, // @[lsu.scala:204:14] output io_dmem_req_bits_0_bits_uop_frs3_en, // @[lsu.scala:204:14] output io_dmem_req_bits_0_bits_uop_fp_val, // @[lsu.scala:204:14] output io_dmem_req_bits_0_bits_uop_fp_single, // @[lsu.scala:204:14] output io_dmem_req_bits_0_bits_uop_xcpt_pf_if, // @[lsu.scala:204:14] output io_dmem_req_bits_0_bits_uop_xcpt_ae_if, // @[lsu.scala:204:14] output io_dmem_req_bits_0_bits_uop_xcpt_ma_if, // @[lsu.scala:204:14] output io_dmem_req_bits_0_bits_uop_bp_debug_if, // @[lsu.scala:204:14] output io_dmem_req_bits_0_bits_uop_bp_xcpt_if, // @[lsu.scala:204:14] output [1:0] io_dmem_req_bits_0_bits_uop_debug_fsrc, // @[lsu.scala:204:14] output [1:0] io_dmem_req_bits_0_bits_uop_debug_tsrc, // @[lsu.scala:204:14] output [39:0] io_dmem_req_bits_0_bits_addr, // @[lsu.scala:204:14] output [63:0] io_dmem_req_bits_0_bits_data, // @[lsu.scala:204:14] output io_dmem_req_bits_0_bits_is_hella, // @[lsu.scala:204:14] output io_dmem_s1_kill_0, // @[lsu.scala:204:14] input io_dmem_resp_0_valid, // @[lsu.scala:204:14] input [6:0] io_dmem_resp_0_bits_uop_uopc, // @[lsu.scala:204:14] input [31:0] io_dmem_resp_0_bits_uop_inst, // @[lsu.scala:204:14] input [31:0] io_dmem_resp_0_bits_uop_debug_inst, // @[lsu.scala:204:14] input io_dmem_resp_0_bits_uop_is_rvc, // @[lsu.scala:204:14] input [39:0] io_dmem_resp_0_bits_uop_debug_pc, // @[lsu.scala:204:14] input [2:0] io_dmem_resp_0_bits_uop_iq_type, // @[lsu.scala:204:14] input [9:0] io_dmem_resp_0_bits_uop_fu_code, // @[lsu.scala:204:14] input [3:0] io_dmem_resp_0_bits_uop_ctrl_br_type, // @[lsu.scala:204:14] input [1:0] io_dmem_resp_0_bits_uop_ctrl_op1_sel, // @[lsu.scala:204:14] input [2:0] io_dmem_resp_0_bits_uop_ctrl_op2_sel, // @[lsu.scala:204:14] input [2:0] io_dmem_resp_0_bits_uop_ctrl_imm_sel, // @[lsu.scala:204:14] input [4:0] io_dmem_resp_0_bits_uop_ctrl_op_fcn, // @[lsu.scala:204:14] input io_dmem_resp_0_bits_uop_ctrl_fcn_dw, // @[lsu.scala:204:14] input [2:0] io_dmem_resp_0_bits_uop_ctrl_csr_cmd, // @[lsu.scala:204:14] input io_dmem_resp_0_bits_uop_ctrl_is_load, // @[lsu.scala:204:14] input io_dmem_resp_0_bits_uop_ctrl_is_sta, // @[lsu.scala:204:14] input io_dmem_resp_0_bits_uop_ctrl_is_std, // @[lsu.scala:204:14] input [1:0] io_dmem_resp_0_bits_uop_iw_state, // @[lsu.scala:204:14] input io_dmem_resp_0_bits_uop_iw_p1_poisoned, // @[lsu.scala:204:14] input io_dmem_resp_0_bits_uop_iw_p2_poisoned, // @[lsu.scala:204:14] input io_dmem_resp_0_bits_uop_is_br, // @[lsu.scala:204:14] input io_dmem_resp_0_bits_uop_is_jalr, // @[lsu.scala:204:14] input io_dmem_resp_0_bits_uop_is_jal, // @[lsu.scala:204:14] input io_dmem_resp_0_bits_uop_is_sfb, // @[lsu.scala:204:14] input [7:0] io_dmem_resp_0_bits_uop_br_mask, // @[lsu.scala:204:14] input [2:0] io_dmem_resp_0_bits_uop_br_tag, // @[lsu.scala:204:14] input [3:0] io_dmem_resp_0_bits_uop_ftq_idx, // @[lsu.scala:204:14] input io_dmem_resp_0_bits_uop_edge_inst, // @[lsu.scala:204:14] input [5:0] io_dmem_resp_0_bits_uop_pc_lob, // @[lsu.scala:204:14] input io_dmem_resp_0_bits_uop_taken, // @[lsu.scala:204:14] input [19:0] io_dmem_resp_0_bits_uop_imm_packed, // @[lsu.scala:204:14] input [11:0] io_dmem_resp_0_bits_uop_csr_addr, // @[lsu.scala:204:14] input [4:0] io_dmem_resp_0_bits_uop_rob_idx, // @[lsu.scala:204:14] input [2:0] io_dmem_resp_0_bits_uop_ldq_idx, // @[lsu.scala:204:14] input [2:0] io_dmem_resp_0_bits_uop_stq_idx, // @[lsu.scala:204:14] input [1:0] io_dmem_resp_0_bits_uop_rxq_idx, // @[lsu.scala:204:14] input [5:0] io_dmem_resp_0_bits_uop_pdst, // @[lsu.scala:204:14] input [5:0] io_dmem_resp_0_bits_uop_prs1, // @[lsu.scala:204:14] input [5:0] io_dmem_resp_0_bits_uop_prs2, // @[lsu.scala:204:14] input [5:0] io_dmem_resp_0_bits_uop_prs3, // @[lsu.scala:204:14] input [3:0] io_dmem_resp_0_bits_uop_ppred, // @[lsu.scala:204:14] input io_dmem_resp_0_bits_uop_prs1_busy, // @[lsu.scala:204:14] input io_dmem_resp_0_bits_uop_prs2_busy, // @[lsu.scala:204:14] input io_dmem_resp_0_bits_uop_prs3_busy, // @[lsu.scala:204:14] input io_dmem_resp_0_bits_uop_ppred_busy, // @[lsu.scala:204:14] input [5:0] io_dmem_resp_0_bits_uop_stale_pdst, // @[lsu.scala:204:14] input io_dmem_resp_0_bits_uop_exception, // @[lsu.scala:204:14] input [63:0] io_dmem_resp_0_bits_uop_exc_cause, // @[lsu.scala:204:14] input io_dmem_resp_0_bits_uop_bypassable, // @[lsu.scala:204:14] input [4:0] io_dmem_resp_0_bits_uop_mem_cmd, // @[lsu.scala:204:14] input [1:0] io_dmem_resp_0_bits_uop_mem_size, // @[lsu.scala:204:14] input io_dmem_resp_0_bits_uop_mem_signed, // @[lsu.scala:204:14] input io_dmem_resp_0_bits_uop_is_fence, // @[lsu.scala:204:14] input io_dmem_resp_0_bits_uop_is_fencei, // @[lsu.scala:204:14] input io_dmem_resp_0_bits_uop_is_amo, // @[lsu.scala:204:14] input io_dmem_resp_0_bits_uop_uses_ldq, // @[lsu.scala:204:14] input io_dmem_resp_0_bits_uop_uses_stq, // @[lsu.scala:204:14] input io_dmem_resp_0_bits_uop_is_sys_pc2epc, // @[lsu.scala:204:14] input io_dmem_resp_0_bits_uop_is_unique, // @[lsu.scala:204:14] input io_dmem_resp_0_bits_uop_flush_on_commit, // @[lsu.scala:204:14] input io_dmem_resp_0_bits_uop_ldst_is_rs1, // @[lsu.scala:204:14] input [5:0] io_dmem_resp_0_bits_uop_ldst, // @[lsu.scala:204:14] input [5:0] io_dmem_resp_0_bits_uop_lrs1, // @[lsu.scala:204:14] input [5:0] io_dmem_resp_0_bits_uop_lrs2, // @[lsu.scala:204:14] input [5:0] io_dmem_resp_0_bits_uop_lrs3, // @[lsu.scala:204:14] input io_dmem_resp_0_bits_uop_ldst_val, // @[lsu.scala:204:14] input [1:0] io_dmem_resp_0_bits_uop_dst_rtype, // @[lsu.scala:204:14] input [1:0] io_dmem_resp_0_bits_uop_lrs1_rtype, // @[lsu.scala:204:14] input [1:0] io_dmem_resp_0_bits_uop_lrs2_rtype, // @[lsu.scala:204:14] input io_dmem_resp_0_bits_uop_frs3_en, // @[lsu.scala:204:14] input io_dmem_resp_0_bits_uop_fp_val, // @[lsu.scala:204:14] input io_dmem_resp_0_bits_uop_fp_single, // @[lsu.scala:204:14] input io_dmem_resp_0_bits_uop_xcpt_pf_if, // @[lsu.scala:204:14] input io_dmem_resp_0_bits_uop_xcpt_ae_if, // @[lsu.scala:204:14] input io_dmem_resp_0_bits_uop_xcpt_ma_if, // @[lsu.scala:204:14] input io_dmem_resp_0_bits_uop_bp_debug_if, // @[lsu.scala:204:14] input io_dmem_resp_0_bits_uop_bp_xcpt_if, // @[lsu.scala:204:14] input [1:0] io_dmem_resp_0_bits_uop_debug_fsrc, // @[lsu.scala:204:14] input [1:0] io_dmem_resp_0_bits_uop_debug_tsrc, // @[lsu.scala:204:14] input [63:0] io_dmem_resp_0_bits_data, // @[lsu.scala:204:14] input io_dmem_resp_0_bits_is_hella, // @[lsu.scala:204:14] input io_dmem_nack_0_valid, // @[lsu.scala:204:14] input [6:0] io_dmem_nack_0_bits_uop_uopc, // @[lsu.scala:204:14] input [31:0] io_dmem_nack_0_bits_uop_inst, // @[lsu.scala:204:14] input [31:0] io_dmem_nack_0_bits_uop_debug_inst, // @[lsu.scala:204:14] input io_dmem_nack_0_bits_uop_is_rvc, // @[lsu.scala:204:14] input [39:0] io_dmem_nack_0_bits_uop_debug_pc, // @[lsu.scala:204:14] input [2:0] io_dmem_nack_0_bits_uop_iq_type, // @[lsu.scala:204:14] input [9:0] io_dmem_nack_0_bits_uop_fu_code, // @[lsu.scala:204:14] input [3:0] io_dmem_nack_0_bits_uop_ctrl_br_type, // @[lsu.scala:204:14] input [1:0] io_dmem_nack_0_bits_uop_ctrl_op1_sel, // @[lsu.scala:204:14] input [2:0] io_dmem_nack_0_bits_uop_ctrl_op2_sel, // @[lsu.scala:204:14] input [2:0] io_dmem_nack_0_bits_uop_ctrl_imm_sel, // @[lsu.scala:204:14] input [4:0] io_dmem_nack_0_bits_uop_ctrl_op_fcn, // @[lsu.scala:204:14] input io_dmem_nack_0_bits_uop_ctrl_fcn_dw, // @[lsu.scala:204:14] input [2:0] io_dmem_nack_0_bits_uop_ctrl_csr_cmd, // @[lsu.scala:204:14] input io_dmem_nack_0_bits_uop_ctrl_is_load, // @[lsu.scala:204:14] input io_dmem_nack_0_bits_uop_ctrl_is_sta, // @[lsu.scala:204:14] input io_dmem_nack_0_bits_uop_ctrl_is_std, // @[lsu.scala:204:14] input [1:0] io_dmem_nack_0_bits_uop_iw_state, // @[lsu.scala:204:14] input io_dmem_nack_0_bits_uop_iw_p1_poisoned, // @[lsu.scala:204:14] input io_dmem_nack_0_bits_uop_iw_p2_poisoned, // @[lsu.scala:204:14] input io_dmem_nack_0_bits_uop_is_br, // @[lsu.scala:204:14] input io_dmem_nack_0_bits_uop_is_jalr, // @[lsu.scala:204:14] input io_dmem_nack_0_bits_uop_is_jal, // @[lsu.scala:204:14] input io_dmem_nack_0_bits_uop_is_sfb, // @[lsu.scala:204:14] input [7:0] io_dmem_nack_0_bits_uop_br_mask, // @[lsu.scala:204:14] input [2:0] io_dmem_nack_0_bits_uop_br_tag, // @[lsu.scala:204:14] input [3:0] io_dmem_nack_0_bits_uop_ftq_idx, // @[lsu.scala:204:14] input io_dmem_nack_0_bits_uop_edge_inst, // @[lsu.scala:204:14] input [5:0] io_dmem_nack_0_bits_uop_pc_lob, // @[lsu.scala:204:14] input io_dmem_nack_0_bits_uop_taken, // @[lsu.scala:204:14] input [19:0] io_dmem_nack_0_bits_uop_imm_packed, // @[lsu.scala:204:14] input [11:0] io_dmem_nack_0_bits_uop_csr_addr, // @[lsu.scala:204:14] input [4:0] io_dmem_nack_0_bits_uop_rob_idx, // @[lsu.scala:204:14] input [2:0] io_dmem_nack_0_bits_uop_ldq_idx, // @[lsu.scala:204:14] input [2:0] io_dmem_nack_0_bits_uop_stq_idx, // @[lsu.scala:204:14] input [1:0] io_dmem_nack_0_bits_uop_rxq_idx, // @[lsu.scala:204:14] input [5:0] io_dmem_nack_0_bits_uop_pdst, // @[lsu.scala:204:14] input [5:0] io_dmem_nack_0_bits_uop_prs1, // @[lsu.scala:204:14] input [5:0] io_dmem_nack_0_bits_uop_prs2, // @[lsu.scala:204:14] input [5:0] io_dmem_nack_0_bits_uop_prs3, // @[lsu.scala:204:14] input [3:0] io_dmem_nack_0_bits_uop_ppred, // @[lsu.scala:204:14] input io_dmem_nack_0_bits_uop_prs1_busy, // @[lsu.scala:204:14] input io_dmem_nack_0_bits_uop_prs2_busy, // @[lsu.scala:204:14] input io_dmem_nack_0_bits_uop_prs3_busy, // @[lsu.scala:204:14] input io_dmem_nack_0_bits_uop_ppred_busy, // @[lsu.scala:204:14] input [5:0] io_dmem_nack_0_bits_uop_stale_pdst, // @[lsu.scala:204:14] input io_dmem_nack_0_bits_uop_exception, // @[lsu.scala:204:14] input [63:0] io_dmem_nack_0_bits_uop_exc_cause, // @[lsu.scala:204:14] input io_dmem_nack_0_bits_uop_bypassable, // @[lsu.scala:204:14] input [4:0] io_dmem_nack_0_bits_uop_mem_cmd, // @[lsu.scala:204:14] input [1:0] io_dmem_nack_0_bits_uop_mem_size, // @[lsu.scala:204:14] input io_dmem_nack_0_bits_uop_mem_signed, // @[lsu.scala:204:14] input io_dmem_nack_0_bits_uop_is_fence, // @[lsu.scala:204:14] input io_dmem_nack_0_bits_uop_is_fencei, // @[lsu.scala:204:14] input io_dmem_nack_0_bits_uop_is_amo, // @[lsu.scala:204:14] input io_dmem_nack_0_bits_uop_uses_ldq, // @[lsu.scala:204:14] input io_dmem_nack_0_bits_uop_uses_stq, // @[lsu.scala:204:14] input io_dmem_nack_0_bits_uop_is_sys_pc2epc, // @[lsu.scala:204:14] input io_dmem_nack_0_bits_uop_is_unique, // @[lsu.scala:204:14] input io_dmem_nack_0_bits_uop_flush_on_commit, // @[lsu.scala:204:14] input io_dmem_nack_0_bits_uop_ldst_is_rs1, // @[lsu.scala:204:14] input [5:0] io_dmem_nack_0_bits_uop_ldst, // @[lsu.scala:204:14] input [5:0] io_dmem_nack_0_bits_uop_lrs1, // @[lsu.scala:204:14] input [5:0] io_dmem_nack_0_bits_uop_lrs2, // @[lsu.scala:204:14] input [5:0] io_dmem_nack_0_bits_uop_lrs3, // @[lsu.scala:204:14] input io_dmem_nack_0_bits_uop_ldst_val, // @[lsu.scala:204:14] input [1:0] io_dmem_nack_0_bits_uop_dst_rtype, // @[lsu.scala:204:14] input [1:0] io_dmem_nack_0_bits_uop_lrs1_rtype, // @[lsu.scala:204:14] input [1:0] io_dmem_nack_0_bits_uop_lrs2_rtype, // @[lsu.scala:204:14] input io_dmem_nack_0_bits_uop_frs3_en, // @[lsu.scala:204:14] input io_dmem_nack_0_bits_uop_fp_val, // @[lsu.scala:204:14] input io_dmem_nack_0_bits_uop_fp_single, // @[lsu.scala:204:14] input io_dmem_nack_0_bits_uop_xcpt_pf_if, // @[lsu.scala:204:14] input io_dmem_nack_0_bits_uop_xcpt_ae_if, // @[lsu.scala:204:14] input io_dmem_nack_0_bits_uop_xcpt_ma_if, // @[lsu.scala:204:14] input io_dmem_nack_0_bits_uop_bp_debug_if, // @[lsu.scala:204:14] input io_dmem_nack_0_bits_uop_bp_xcpt_if, // @[lsu.scala:204:14] input [1:0] io_dmem_nack_0_bits_uop_debug_fsrc, // @[lsu.scala:204:14] input [1:0] io_dmem_nack_0_bits_uop_debug_tsrc, // @[lsu.scala:204:14] input [39:0] io_dmem_nack_0_bits_addr, // @[lsu.scala:204:14] input [63:0] io_dmem_nack_0_bits_data, // @[lsu.scala:204:14] input io_dmem_nack_0_bits_is_hella, // @[lsu.scala:204:14] output [7:0] io_dmem_brupdate_b1_resolve_mask, // @[lsu.scala:204:14] output [7:0] io_dmem_brupdate_b1_mispredict_mask, // @[lsu.scala:204:14] output [6:0] io_dmem_brupdate_b2_uop_uopc, // @[lsu.scala:204:14] output [31:0] io_dmem_brupdate_b2_uop_inst, // @[lsu.scala:204:14] output [31:0] io_dmem_brupdate_b2_uop_debug_inst, // @[lsu.scala:204:14] output io_dmem_brupdate_b2_uop_is_rvc, // @[lsu.scala:204:14] output [39:0] io_dmem_brupdate_b2_uop_debug_pc, // @[lsu.scala:204:14] output [2:0] io_dmem_brupdate_b2_uop_iq_type, // @[lsu.scala:204:14] output [9:0] io_dmem_brupdate_b2_uop_fu_code, // @[lsu.scala:204:14] output [3:0] io_dmem_brupdate_b2_uop_ctrl_br_type, // @[lsu.scala:204:14] output [1:0] io_dmem_brupdate_b2_uop_ctrl_op1_sel, // @[lsu.scala:204:14] output [2:0] io_dmem_brupdate_b2_uop_ctrl_op2_sel, // @[lsu.scala:204:14] output [2:0] io_dmem_brupdate_b2_uop_ctrl_imm_sel, // @[lsu.scala:204:14] output [4:0] io_dmem_brupdate_b2_uop_ctrl_op_fcn, // @[lsu.scala:204:14] output io_dmem_brupdate_b2_uop_ctrl_fcn_dw, // @[lsu.scala:204:14] output [2:0] io_dmem_brupdate_b2_uop_ctrl_csr_cmd, // @[lsu.scala:204:14] output io_dmem_brupdate_b2_uop_ctrl_is_load, // @[lsu.scala:204:14] output io_dmem_brupdate_b2_uop_ctrl_is_sta, // @[lsu.scala:204:14] output io_dmem_brupdate_b2_uop_ctrl_is_std, // @[lsu.scala:204:14] output [1:0] io_dmem_brupdate_b2_uop_iw_state, // @[lsu.scala:204:14] output io_dmem_brupdate_b2_uop_iw_p1_poisoned, // @[lsu.scala:204:14] output io_dmem_brupdate_b2_uop_iw_p2_poisoned, // @[lsu.scala:204:14] output io_dmem_brupdate_b2_uop_is_br, // @[lsu.scala:204:14] output io_dmem_brupdate_b2_uop_is_jalr, // @[lsu.scala:204:14] output io_dmem_brupdate_b2_uop_is_jal, // @[lsu.scala:204:14] output io_dmem_brupdate_b2_uop_is_sfb, // @[lsu.scala:204:14] output [7:0] io_dmem_brupdate_b2_uop_br_mask, // @[lsu.scala:204:14] output [2:0] io_dmem_brupdate_b2_uop_br_tag, // @[lsu.scala:204:14] output [3:0] io_dmem_brupdate_b2_uop_ftq_idx, // @[lsu.scala:204:14] output io_dmem_brupdate_b2_uop_edge_inst, // @[lsu.scala:204:14] output [5:0] io_dmem_brupdate_b2_uop_pc_lob, // @[lsu.scala:204:14] output io_dmem_brupdate_b2_uop_taken, // @[lsu.scala:204:14] output [19:0] io_dmem_brupdate_b2_uop_imm_packed, // @[lsu.scala:204:14] output [11:0] io_dmem_brupdate_b2_uop_csr_addr, // @[lsu.scala:204:14] output [4:0] io_dmem_brupdate_b2_uop_rob_idx, // @[lsu.scala:204:14] output [2:0] io_dmem_brupdate_b2_uop_ldq_idx, // @[lsu.scala:204:14] output [2:0] io_dmem_brupdate_b2_uop_stq_idx, // @[lsu.scala:204:14] output [1:0] io_dmem_brupdate_b2_uop_rxq_idx, // @[lsu.scala:204:14] output [5:0] io_dmem_brupdate_b2_uop_pdst, // @[lsu.scala:204:14] output [5:0] io_dmem_brupdate_b2_uop_prs1, // @[lsu.scala:204:14] output [5:0] io_dmem_brupdate_b2_uop_prs2, // @[lsu.scala:204:14] output [5:0] io_dmem_brupdate_b2_uop_prs3, // @[lsu.scala:204:14] output [3:0] io_dmem_brupdate_b2_uop_ppred, // @[lsu.scala:204:14] output io_dmem_brupdate_b2_uop_prs1_busy, // @[lsu.scala:204:14] output io_dmem_brupdate_b2_uop_prs2_busy, // @[lsu.scala:204:14] output io_dmem_brupdate_b2_uop_prs3_busy, // @[lsu.scala:204:14] output io_dmem_brupdate_b2_uop_ppred_busy, // @[lsu.scala:204:14] output [5:0] io_dmem_brupdate_b2_uop_stale_pdst, // @[lsu.scala:204:14] output io_dmem_brupdate_b2_uop_exception, // @[lsu.scala:204:14] output [63:0] io_dmem_brupdate_b2_uop_exc_cause, // @[lsu.scala:204:14] output io_dmem_brupdate_b2_uop_bypassable, // @[lsu.scala:204:14] output [4:0] io_dmem_brupdate_b2_uop_mem_cmd, // @[lsu.scala:204:14] output [1:0] io_dmem_brupdate_b2_uop_mem_size, // @[lsu.scala:204:14] output io_dmem_brupdate_b2_uop_mem_signed, // @[lsu.scala:204:14] output io_dmem_brupdate_b2_uop_is_fence, // @[lsu.scala:204:14] output io_dmem_brupdate_b2_uop_is_fencei, // @[lsu.scala:204:14] output io_dmem_brupdate_b2_uop_is_amo, // @[lsu.scala:204:14] output io_dmem_brupdate_b2_uop_uses_ldq, // @[lsu.scala:204:14] output io_dmem_brupdate_b2_uop_uses_stq, // @[lsu.scala:204:14] output io_dmem_brupdate_b2_uop_is_sys_pc2epc, // @[lsu.scala:204:14] output io_dmem_brupdate_b2_uop_is_unique, // @[lsu.scala:204:14] output io_dmem_brupdate_b2_uop_flush_on_commit, // @[lsu.scala:204:14] output io_dmem_brupdate_b2_uop_ldst_is_rs1, // @[lsu.scala:204:14] output [5:0] io_dmem_brupdate_b2_uop_ldst, // @[lsu.scala:204:14] output [5:0] io_dmem_brupdate_b2_uop_lrs1, // @[lsu.scala:204:14] output [5:0] io_dmem_brupdate_b2_uop_lrs2, // @[lsu.scala:204:14] output [5:0] io_dmem_brupdate_b2_uop_lrs3, // @[lsu.scala:204:14] output io_dmem_brupdate_b2_uop_ldst_val, // @[lsu.scala:204:14] output [1:0] io_dmem_brupdate_b2_uop_dst_rtype, // @[lsu.scala:204:14] output [1:0] io_dmem_brupdate_b2_uop_lrs1_rtype, // @[lsu.scala:204:14] output [1:0] io_dmem_brupdate_b2_uop_lrs2_rtype, // @[lsu.scala:204:14] output io_dmem_brupdate_b2_uop_frs3_en, // @[lsu.scala:204:14] output io_dmem_brupdate_b2_uop_fp_val, // @[lsu.scala:204:14] output io_dmem_brupdate_b2_uop_fp_single, // @[lsu.scala:204:14] output io_dmem_brupdate_b2_uop_xcpt_pf_if, // @[lsu.scala:204:14] output io_dmem_brupdate_b2_uop_xcpt_ae_if, // @[lsu.scala:204:14] output io_dmem_brupdate_b2_uop_xcpt_ma_if, // @[lsu.scala:204:14] output io_dmem_brupdate_b2_uop_bp_debug_if, // @[lsu.scala:204:14] output io_dmem_brupdate_b2_uop_bp_xcpt_if, // @[lsu.scala:204:14] output [1:0] io_dmem_brupdate_b2_uop_debug_fsrc, // @[lsu.scala:204:14] output [1:0] io_dmem_brupdate_b2_uop_debug_tsrc, // @[lsu.scala:204:14] output io_dmem_brupdate_b2_valid, // @[lsu.scala:204:14] output io_dmem_brupdate_b2_mispredict, // @[lsu.scala:204:14] output io_dmem_brupdate_b2_taken, // @[lsu.scala:204:14] output [2:0] io_dmem_brupdate_b2_cfi_type, // @[lsu.scala:204:14] output [1:0] io_dmem_brupdate_b2_pc_sel, // @[lsu.scala:204:14] output [39:0] io_dmem_brupdate_b2_jalr_target, // @[lsu.scala:204:14] output [20:0] io_dmem_brupdate_b2_target_offset, // @[lsu.scala:204:14] output io_dmem_exception, // @[lsu.scala:204:14] output [4:0] io_dmem_rob_pnr_idx, // @[lsu.scala:204:14] output [4:0] io_dmem_rob_head_idx, // @[lsu.scala:204:14] output io_dmem_release_ready, // @[lsu.scala:204:14] input io_dmem_release_valid, // @[lsu.scala:204:14] input [2:0] io_dmem_release_bits_opcode, // @[lsu.scala:204:14] input [2:0] io_dmem_release_bits_param, // @[lsu.scala:204:14] input [3:0] io_dmem_release_bits_size, // @[lsu.scala:204:14] input [1:0] io_dmem_release_bits_source, // @[lsu.scala:204:14] input [31:0] io_dmem_release_bits_address, // @[lsu.scala:204:14] input [63:0] io_dmem_release_bits_data, // @[lsu.scala:204:14] output io_dmem_force_order, // @[lsu.scala:204:14] input io_dmem_ordered, // @[lsu.scala:204:14] input io_dmem_perf_acquire, // @[lsu.scala:204:14] input io_dmem_perf_release, // @[lsu.scala:204:14] output io_hellacache_req_ready, // @[lsu.scala:204:14] input io_hellacache_req_valid, // @[lsu.scala:204:14] input [39:0] io_hellacache_req_bits_addr, // @[lsu.scala:204:14] input io_hellacache_req_bits_dv, // @[lsu.scala:204:14] input io_hellacache_s1_kill, // @[lsu.scala:204:14] output io_hellacache_s2_nack, // @[lsu.scala:204:14] output io_hellacache_resp_valid, // @[lsu.scala:204:14] output [39:0] io_hellacache_resp_bits_addr, // @[lsu.scala:204:14] output [63:0] io_hellacache_resp_bits_data, // @[lsu.scala:204:14] output io_hellacache_s2_xcpt_ma_ld, // @[lsu.scala:204:14] output io_hellacache_s2_xcpt_ma_st, // @[lsu.scala:204:14] output io_hellacache_s2_xcpt_pf_ld, // @[lsu.scala:204:14] output io_hellacache_s2_xcpt_pf_st, // @[lsu.scala:204:14] output io_hellacache_s2_xcpt_gf_ld, // @[lsu.scala:204:14] output io_hellacache_s2_xcpt_gf_st, // @[lsu.scala:204:14] output io_hellacache_s2_xcpt_ae_ld, // @[lsu.scala:204:14] output io_hellacache_s2_xcpt_ae_st, // @[lsu.scala:204:14] output io_hellacache_store_pending // @[lsu.scala:204:14] ); wire failed_loads_6; // @[lsu.scala:1054:34] wire failed_loads_5; // @[lsu.scala:1054:34] wire failed_loads_4; // @[lsu.scala:1054:34] wire failed_loads_3; // @[lsu.scala:1054:34] wire failed_loads_2; // @[lsu.scala:1054:34] wire failed_loads_1; // @[lsu.scala:1054:34] wire failed_loads_0; // @[lsu.scala:1054:34] wire mem_stq_incoming_e_out_valid; // @[util.scala:106:23] wire [7:0] mem_stq_incoming_e_out_bits_uop_br_mask; // @[util.scala:106:23] wire mem_ldq_incoming_e_out_valid; // @[util.scala:106:23] wire [7:0] mem_ldq_incoming_e_out_bits_uop_br_mask; // @[util.scala:106:23] wire [7:0] mem_incoming_uop_out_br_mask; // @[util.scala:96:23] wire [7:0] mem_xcpt_uops_out_br_mask; // @[util.scala:96:23] wire [63:0] stq_incoming_e_0_bits_debug_wb_data; // @[lsu.scala:263:49] wire stq_incoming_e_0_bits_succeeded; // @[lsu.scala:263:49] wire stq_incoming_e_0_bits_committed; // @[lsu.scala:263:49] wire stq_incoming_e_0_bits_addr_is_virtual; // @[lsu.scala:263:49] wire [63:0] stq_incoming_e_0_bits_data_bits; // @[lsu.scala:263:49] wire stq_incoming_e_0_bits_data_valid; // @[lsu.scala:263:49] wire [39:0] stq_incoming_e_0_bits_addr_bits; // @[lsu.scala:263:49] wire stq_incoming_e_0_bits_addr_valid; // @[lsu.scala:263:49] wire [1:0] stq_incoming_e_0_bits_uop_debug_tsrc; // @[lsu.scala:263:49] wire [1:0] stq_incoming_e_0_bits_uop_debug_fsrc; // @[lsu.scala:263:49] wire stq_incoming_e_0_bits_uop_bp_xcpt_if; // @[lsu.scala:263:49] wire stq_incoming_e_0_bits_uop_bp_debug_if; // @[lsu.scala:263:49] wire stq_incoming_e_0_bits_uop_xcpt_ma_if; // @[lsu.scala:263:49] wire stq_incoming_e_0_bits_uop_xcpt_ae_if; // @[lsu.scala:263:49] wire stq_incoming_e_0_bits_uop_xcpt_pf_if; // @[lsu.scala:263:49] wire stq_incoming_e_0_bits_uop_fp_single; // @[lsu.scala:263:49] wire stq_incoming_e_0_bits_uop_fp_val; // @[lsu.scala:263:49] wire stq_incoming_e_0_bits_uop_frs3_en; // @[lsu.scala:263:49] wire [1:0] stq_incoming_e_0_bits_uop_lrs2_rtype; // @[lsu.scala:263:49] wire [1:0] stq_incoming_e_0_bits_uop_lrs1_rtype; // @[lsu.scala:263:49] wire [1:0] stq_incoming_e_0_bits_uop_dst_rtype; // @[lsu.scala:263:49] wire stq_incoming_e_0_bits_uop_ldst_val; // @[lsu.scala:263:49] wire [5:0] stq_incoming_e_0_bits_uop_lrs3; // @[lsu.scala:263:49] wire [5:0] stq_incoming_e_0_bits_uop_lrs2; // @[lsu.scala:263:49] wire [5:0] stq_incoming_e_0_bits_uop_lrs1; // @[lsu.scala:263:49] wire [5:0] stq_incoming_e_0_bits_uop_ldst; // @[lsu.scala:263:49] wire stq_incoming_e_0_bits_uop_ldst_is_rs1; // @[lsu.scala:263:49] wire stq_incoming_e_0_bits_uop_flush_on_commit; // @[lsu.scala:263:49] wire stq_incoming_e_0_bits_uop_is_unique; // @[lsu.scala:263:49] wire stq_incoming_e_0_bits_uop_is_sys_pc2epc; // @[lsu.scala:263:49] wire stq_incoming_e_0_bits_uop_uses_stq; // @[lsu.scala:263:49] wire stq_incoming_e_0_bits_uop_uses_ldq; // @[lsu.scala:263:49] wire stq_incoming_e_0_bits_uop_is_amo; // @[lsu.scala:263:49] wire stq_incoming_e_0_bits_uop_is_fencei; // @[lsu.scala:263:49] wire stq_incoming_e_0_bits_uop_is_fence; // @[lsu.scala:263:49] wire stq_incoming_e_0_bits_uop_mem_signed; // @[lsu.scala:263:49] wire [1:0] stq_incoming_e_0_bits_uop_mem_size; // @[lsu.scala:263:49] wire [4:0] stq_incoming_e_0_bits_uop_mem_cmd; // @[lsu.scala:263:49] wire stq_incoming_e_0_bits_uop_bypassable; // @[lsu.scala:263:49] wire [63:0] stq_incoming_e_0_bits_uop_exc_cause; // @[lsu.scala:263:49] wire stq_incoming_e_0_bits_uop_exception; // @[lsu.scala:263:49] wire [5:0] stq_incoming_e_0_bits_uop_stale_pdst; // @[lsu.scala:263:49] wire stq_incoming_e_0_bits_uop_ppred_busy; // @[lsu.scala:263:49] wire stq_incoming_e_0_bits_uop_prs3_busy; // @[lsu.scala:263:49] wire stq_incoming_e_0_bits_uop_prs2_busy; // @[lsu.scala:263:49] wire stq_incoming_e_0_bits_uop_prs1_busy; // @[lsu.scala:263:49] wire [3:0] stq_incoming_e_0_bits_uop_ppred; // @[lsu.scala:263:49] wire [5:0] stq_incoming_e_0_bits_uop_prs3; // @[lsu.scala:263:49] wire [5:0] stq_incoming_e_0_bits_uop_prs2; // @[lsu.scala:263:49] wire [5:0] stq_incoming_e_0_bits_uop_prs1; // @[lsu.scala:263:49] wire [5:0] stq_incoming_e_0_bits_uop_pdst; // @[lsu.scala:263:49] wire [1:0] stq_incoming_e_0_bits_uop_rxq_idx; // @[lsu.scala:263:49] wire [2:0] stq_incoming_e_0_bits_uop_stq_idx; // @[lsu.scala:263:49] wire [2:0] stq_incoming_e_0_bits_uop_ldq_idx; // @[lsu.scala:263:49] wire [4:0] stq_incoming_e_0_bits_uop_rob_idx; // @[lsu.scala:263:49] wire [11:0] stq_incoming_e_0_bits_uop_csr_addr; // @[lsu.scala:263:49] wire [19:0] stq_incoming_e_0_bits_uop_imm_packed; // @[lsu.scala:263:49] wire stq_incoming_e_0_bits_uop_taken; // @[lsu.scala:263:49] wire [5:0] stq_incoming_e_0_bits_uop_pc_lob; // @[lsu.scala:263:49] wire stq_incoming_e_0_bits_uop_edge_inst; // @[lsu.scala:263:49] wire [3:0] stq_incoming_e_0_bits_uop_ftq_idx; // @[lsu.scala:263:49] wire [2:0] stq_incoming_e_0_bits_uop_br_tag; // @[lsu.scala:263:49] wire stq_incoming_e_0_bits_uop_is_sfb; // @[lsu.scala:263:49] wire stq_incoming_e_0_bits_uop_is_jal; // @[lsu.scala:263:49] wire stq_incoming_e_0_bits_uop_is_jalr; // @[lsu.scala:263:49] wire stq_incoming_e_0_bits_uop_is_br; // @[lsu.scala:263:49] wire stq_incoming_e_0_bits_uop_iw_p2_poisoned; // @[lsu.scala:263:49] wire stq_incoming_e_0_bits_uop_iw_p1_poisoned; // @[lsu.scala:263:49] wire [1:0] stq_incoming_e_0_bits_uop_iw_state; // @[lsu.scala:263:49] wire [9:0] stq_incoming_e_0_bits_uop_fu_code; // @[lsu.scala:263:49] wire [2:0] stq_incoming_e_0_bits_uop_iq_type; // @[lsu.scala:263:49] wire [39:0] stq_incoming_e_0_bits_uop_debug_pc; // @[lsu.scala:263:49] wire stq_incoming_e_0_bits_uop_is_rvc; // @[lsu.scala:263:49] wire [31:0] stq_incoming_e_0_bits_uop_debug_inst; // @[lsu.scala:263:49] wire [31:0] stq_incoming_e_0_bits_uop_inst; // @[lsu.scala:263:49] wire [6:0] stq_incoming_e_0_bits_uop_uopc; // @[lsu.scala:263:49] wire stq_incoming_e_0_bits_uop_ctrl_is_std; // @[lsu.scala:263:49] wire stq_incoming_e_0_bits_uop_ctrl_is_sta; // @[lsu.scala:263:49] wire stq_incoming_e_0_bits_uop_ctrl_is_load; // @[lsu.scala:263:49] wire [2:0] stq_incoming_e_0_bits_uop_ctrl_csr_cmd; // @[lsu.scala:263:49] wire stq_incoming_e_0_bits_uop_ctrl_fcn_dw; // @[lsu.scala:263:49] wire [4:0] stq_incoming_e_0_bits_uop_ctrl_op_fcn; // @[lsu.scala:263:49] wire [2:0] stq_incoming_e_0_bits_uop_ctrl_imm_sel; // @[lsu.scala:263:49] wire [2:0] stq_incoming_e_0_bits_uop_ctrl_op2_sel; // @[lsu.scala:263:49] wire [1:0] stq_incoming_e_0_bits_uop_ctrl_op1_sel; // @[lsu.scala:263:49] wire [3:0] stq_incoming_e_0_bits_uop_ctrl_br_type; // @[lsu.scala:263:49] wire [63:0] ldq_incoming_e_0_bits_debug_wb_data; // @[lsu.scala:263:49] wire [2:0] ldq_incoming_e_0_bits_forward_stq_idx; // @[lsu.scala:263:49] wire ldq_incoming_e_0_bits_forward_std_val; // @[lsu.scala:263:49] wire [2:0] ldq_incoming_e_0_bits_youngest_stq_idx; // @[lsu.scala:263:49] wire [7:0] ldq_incoming_e_0_bits_st_dep_mask; // @[lsu.scala:263:49] wire ldq_incoming_e_0_bits_observed; // @[lsu.scala:263:49] wire ldq_incoming_e_0_bits_order_fail; // @[lsu.scala:263:49] wire ldq_incoming_e_0_bits_succeeded; // @[lsu.scala:263:49] wire ldq_incoming_e_0_bits_executed; // @[lsu.scala:263:49] wire ldq_incoming_e_0_bits_addr_is_uncacheable; // @[lsu.scala:263:49] wire ldq_incoming_e_0_bits_addr_is_virtual; // @[lsu.scala:263:49] wire [39:0] ldq_incoming_e_0_bits_addr_bits; // @[lsu.scala:263:49] wire ldq_incoming_e_0_bits_addr_valid; // @[lsu.scala:263:49] wire [1:0] ldq_incoming_e_0_bits_uop_debug_tsrc; // @[lsu.scala:263:49] wire [1:0] ldq_incoming_e_0_bits_uop_debug_fsrc; // @[lsu.scala:263:49] wire ldq_incoming_e_0_bits_uop_bp_xcpt_if; // @[lsu.scala:263:49] wire ldq_incoming_e_0_bits_uop_bp_debug_if; // @[lsu.scala:263:49] wire ldq_incoming_e_0_bits_uop_xcpt_ma_if; // @[lsu.scala:263:49] wire ldq_incoming_e_0_bits_uop_xcpt_ae_if; // @[lsu.scala:263:49] wire ldq_incoming_e_0_bits_uop_xcpt_pf_if; // @[lsu.scala:263:49] wire ldq_incoming_e_0_bits_uop_fp_single; // @[lsu.scala:263:49] wire ldq_incoming_e_0_bits_uop_fp_val; // @[lsu.scala:263:49] wire ldq_incoming_e_0_bits_uop_frs3_en; // @[lsu.scala:263:49] wire [1:0] ldq_incoming_e_0_bits_uop_lrs2_rtype; // @[lsu.scala:263:49] wire [1:0] ldq_incoming_e_0_bits_uop_lrs1_rtype; // @[lsu.scala:263:49] wire [1:0] ldq_incoming_e_0_bits_uop_dst_rtype; // @[lsu.scala:263:49] wire ldq_incoming_e_0_bits_uop_ldst_val; // @[lsu.scala:263:49] wire [5:0] ldq_incoming_e_0_bits_uop_lrs3; // @[lsu.scala:263:49] wire [5:0] ldq_incoming_e_0_bits_uop_lrs2; // @[lsu.scala:263:49] wire [5:0] ldq_incoming_e_0_bits_uop_lrs1; // @[lsu.scala:263:49] wire [5:0] ldq_incoming_e_0_bits_uop_ldst; // @[lsu.scala:263:49] wire ldq_incoming_e_0_bits_uop_ldst_is_rs1; // @[lsu.scala:263:49] wire ldq_incoming_e_0_bits_uop_flush_on_commit; // @[lsu.scala:263:49] wire ldq_incoming_e_0_bits_uop_is_unique; // @[lsu.scala:263:49] wire ldq_incoming_e_0_bits_uop_is_sys_pc2epc; // @[lsu.scala:263:49] wire ldq_incoming_e_0_bits_uop_uses_stq; // @[lsu.scala:263:49] wire ldq_incoming_e_0_bits_uop_uses_ldq; // @[lsu.scala:263:49] wire ldq_incoming_e_0_bits_uop_is_amo; // @[lsu.scala:263:49] wire ldq_incoming_e_0_bits_uop_is_fencei; // @[lsu.scala:263:49] wire ldq_incoming_e_0_bits_uop_is_fence; // @[lsu.scala:263:49] wire ldq_incoming_e_0_bits_uop_mem_signed; // @[lsu.scala:263:49] wire [1:0] ldq_incoming_e_0_bits_uop_mem_size; // @[lsu.scala:263:49] wire [4:0] ldq_incoming_e_0_bits_uop_mem_cmd; // @[lsu.scala:263:49] wire ldq_incoming_e_0_bits_uop_bypassable; // @[lsu.scala:263:49] wire [63:0] ldq_incoming_e_0_bits_uop_exc_cause; // @[lsu.scala:263:49] wire ldq_incoming_e_0_bits_uop_exception; // @[lsu.scala:263:49] wire [5:0] ldq_incoming_e_0_bits_uop_stale_pdst; // @[lsu.scala:263:49] wire ldq_incoming_e_0_bits_uop_prs3_busy; // @[lsu.scala:263:49] wire ldq_incoming_e_0_bits_uop_prs2_busy; // @[lsu.scala:263:49] wire ldq_incoming_e_0_bits_uop_prs1_busy; // @[lsu.scala:263:49] wire [5:0] ldq_incoming_e_0_bits_uop_prs3; // @[lsu.scala:263:49] wire [5:0] ldq_incoming_e_0_bits_uop_prs2; // @[lsu.scala:263:49] wire [5:0] ldq_incoming_e_0_bits_uop_prs1; // @[lsu.scala:263:49] wire [5:0] ldq_incoming_e_0_bits_uop_pdst; // @[lsu.scala:263:49] wire [1:0] ldq_incoming_e_0_bits_uop_rxq_idx; // @[lsu.scala:263:49] wire [2:0] ldq_incoming_e_0_bits_uop_stq_idx; // @[lsu.scala:263:49] wire [2:0] ldq_incoming_e_0_bits_uop_ldq_idx; // @[lsu.scala:263:49] wire [4:0] ldq_incoming_e_0_bits_uop_rob_idx; // @[lsu.scala:263:49] wire [11:0] ldq_incoming_e_0_bits_uop_csr_addr; // @[lsu.scala:263:49] wire [19:0] ldq_incoming_e_0_bits_uop_imm_packed; // @[lsu.scala:263:49] wire ldq_incoming_e_0_bits_uop_taken; // @[lsu.scala:263:49] wire [5:0] ldq_incoming_e_0_bits_uop_pc_lob; // @[lsu.scala:263:49] wire ldq_incoming_e_0_bits_uop_edge_inst; // @[lsu.scala:263:49] wire [3:0] ldq_incoming_e_0_bits_uop_ftq_idx; // @[lsu.scala:263:49] wire [2:0] ldq_incoming_e_0_bits_uop_br_tag; // @[lsu.scala:263:49] wire ldq_incoming_e_0_bits_uop_is_sfb; // @[lsu.scala:263:49] wire ldq_incoming_e_0_bits_uop_is_jal; // @[lsu.scala:263:49] wire ldq_incoming_e_0_bits_uop_is_jalr; // @[lsu.scala:263:49] wire ldq_incoming_e_0_bits_uop_is_br; // @[lsu.scala:263:49] wire ldq_incoming_e_0_bits_uop_iw_p2_poisoned; // @[lsu.scala:263:49] wire ldq_incoming_e_0_bits_uop_iw_p1_poisoned; // @[lsu.scala:263:49] wire [1:0] ldq_incoming_e_0_bits_uop_iw_state; // @[lsu.scala:263:49] wire [9:0] ldq_incoming_e_0_bits_uop_fu_code; // @[lsu.scala:263:49] wire [2:0] ldq_incoming_e_0_bits_uop_iq_type; // @[lsu.scala:263:49] wire [39:0] ldq_incoming_e_0_bits_uop_debug_pc; // @[lsu.scala:263:49] wire ldq_incoming_e_0_bits_uop_is_rvc; // @[lsu.scala:263:49] wire [31:0] ldq_incoming_e_0_bits_uop_debug_inst; // @[lsu.scala:263:49] wire [31:0] ldq_incoming_e_0_bits_uop_inst; // @[lsu.scala:263:49] wire [6:0] ldq_incoming_e_0_bits_uop_uopc; // @[lsu.scala:263:49] wire ldq_incoming_e_0_bits_uop_ctrl_is_std; // @[lsu.scala:263:49] wire ldq_incoming_e_0_bits_uop_ctrl_is_sta; // @[lsu.scala:263:49] wire ldq_incoming_e_0_bits_uop_ctrl_is_load; // @[lsu.scala:263:49] wire [2:0] ldq_incoming_e_0_bits_uop_ctrl_csr_cmd; // @[lsu.scala:263:49] wire ldq_incoming_e_0_bits_uop_ctrl_fcn_dw; // @[lsu.scala:263:49] wire [4:0] ldq_incoming_e_0_bits_uop_ctrl_op_fcn; // @[lsu.scala:263:49] wire [2:0] ldq_incoming_e_0_bits_uop_ctrl_imm_sel; // @[lsu.scala:263:49] wire [2:0] ldq_incoming_e_0_bits_uop_ctrl_op2_sel; // @[lsu.scala:263:49] wire [1:0] ldq_incoming_e_0_bits_uop_ctrl_op1_sel; // @[lsu.scala:263:49] wire [3:0] ldq_incoming_e_0_bits_uop_ctrl_br_type; // @[lsu.scala:263:49] wire [1:0] exe_req_0_bits_uop_debug_tsrc; // @[lsu.scala:383:25] wire [1:0] exe_req_0_bits_uop_debug_fsrc; // @[lsu.scala:383:25] wire exe_req_0_bits_uop_bp_xcpt_if; // @[lsu.scala:383:25] wire exe_req_0_bits_uop_bp_debug_if; // @[lsu.scala:383:25] wire exe_req_0_bits_uop_xcpt_ma_if; // @[lsu.scala:383:25] wire exe_req_0_bits_uop_xcpt_ae_if; // @[lsu.scala:383:25] wire exe_req_0_bits_uop_xcpt_pf_if; // @[lsu.scala:383:25] wire exe_req_0_bits_uop_fp_single; // @[lsu.scala:383:25] wire exe_req_0_bits_uop_fp_val; // @[lsu.scala:383:25] wire exe_req_0_bits_uop_frs3_en; // @[lsu.scala:383:25] wire [1:0] exe_req_0_bits_uop_lrs2_rtype; // @[lsu.scala:383:25] wire [1:0] exe_req_0_bits_uop_lrs1_rtype; // @[lsu.scala:383:25] wire [1:0] exe_req_0_bits_uop_dst_rtype; // @[lsu.scala:383:25] wire exe_req_0_bits_uop_ldst_val; // @[lsu.scala:383:25] wire [5:0] exe_req_0_bits_uop_lrs3; // @[lsu.scala:383:25] wire [5:0] exe_req_0_bits_uop_lrs2; // @[lsu.scala:383:25] wire [5:0] exe_req_0_bits_uop_lrs1; // @[lsu.scala:383:25] wire [5:0] exe_req_0_bits_uop_ldst; // @[lsu.scala:383:25] wire exe_req_0_bits_uop_ldst_is_rs1; // @[lsu.scala:383:25] wire exe_req_0_bits_uop_flush_on_commit; // @[lsu.scala:383:25] wire exe_req_0_bits_uop_is_unique; // @[lsu.scala:383:25] wire exe_req_0_bits_uop_is_sys_pc2epc; // @[lsu.scala:383:25] wire exe_req_0_bits_uop_uses_stq; // @[lsu.scala:383:25] wire exe_req_0_bits_uop_uses_ldq; // @[lsu.scala:383:25] wire exe_req_0_bits_uop_is_amo; // @[lsu.scala:383:25] wire exe_req_0_bits_uop_is_fencei; // @[lsu.scala:383:25] wire exe_req_0_bits_uop_is_fence; // @[lsu.scala:383:25] wire exe_req_0_bits_uop_mem_signed; // @[lsu.scala:383:25] wire [1:0] exe_req_0_bits_uop_mem_size; // @[lsu.scala:383:25] wire [4:0] exe_req_0_bits_uop_mem_cmd; // @[lsu.scala:383:25] wire exe_req_0_bits_uop_bypassable; // @[lsu.scala:383:25] wire [63:0] exe_req_0_bits_uop_exc_cause; // @[lsu.scala:383:25] wire exe_req_0_bits_uop_exception; // @[lsu.scala:383:25] wire [5:0] exe_req_0_bits_uop_stale_pdst; // @[lsu.scala:383:25] wire exe_req_0_bits_uop_ppred_busy; // @[lsu.scala:383:25] wire exe_req_0_bits_uop_prs3_busy; // @[lsu.scala:383:25] wire exe_req_0_bits_uop_prs2_busy; // @[lsu.scala:383:25] wire exe_req_0_bits_uop_prs1_busy; // @[lsu.scala:383:25] wire [3:0] exe_req_0_bits_uop_ppred; // @[lsu.scala:383:25] wire [5:0] exe_req_0_bits_uop_prs3; // @[lsu.scala:383:25] wire [5:0] exe_req_0_bits_uop_prs2; // @[lsu.scala:383:25] wire [5:0] exe_req_0_bits_uop_prs1; // @[lsu.scala:383:25] wire [5:0] exe_req_0_bits_uop_pdst; // @[lsu.scala:383:25] wire [1:0] exe_req_0_bits_uop_rxq_idx; // @[lsu.scala:383:25] wire [2:0] exe_req_0_bits_uop_stq_idx; // @[lsu.scala:383:25] wire [2:0] exe_req_0_bits_uop_ldq_idx; // @[lsu.scala:383:25] wire [4:0] exe_req_0_bits_uop_rob_idx; // @[lsu.scala:383:25] wire [11:0] exe_req_0_bits_uop_csr_addr; // @[lsu.scala:383:25] wire [19:0] exe_req_0_bits_uop_imm_packed; // @[lsu.scala:383:25] wire exe_req_0_bits_uop_taken; // @[lsu.scala:383:25] wire [5:0] exe_req_0_bits_uop_pc_lob; // @[lsu.scala:383:25] wire exe_req_0_bits_uop_edge_inst; // @[lsu.scala:383:25] wire [3:0] exe_req_0_bits_uop_ftq_idx; // @[lsu.scala:383:25] wire [2:0] exe_req_0_bits_uop_br_tag; // @[lsu.scala:383:25] wire exe_req_0_bits_uop_is_sfb; // @[lsu.scala:383:25] wire exe_req_0_bits_uop_is_jal; // @[lsu.scala:383:25] wire exe_req_0_bits_uop_is_jalr; // @[lsu.scala:383:25] wire exe_req_0_bits_uop_is_br; // @[lsu.scala:383:25] wire exe_req_0_bits_uop_iw_p2_poisoned; // @[lsu.scala:383:25] wire exe_req_0_bits_uop_iw_p1_poisoned; // @[lsu.scala:383:25] wire [1:0] exe_req_0_bits_uop_iw_state; // @[lsu.scala:383:25] wire [9:0] exe_req_0_bits_uop_fu_code; // @[lsu.scala:383:25] wire [2:0] exe_req_0_bits_uop_iq_type; // @[lsu.scala:383:25] wire [39:0] exe_req_0_bits_uop_debug_pc; // @[lsu.scala:383:25] wire exe_req_0_bits_uop_is_rvc; // @[lsu.scala:383:25] wire [31:0] exe_req_0_bits_uop_debug_inst; // @[lsu.scala:383:25] wire [31:0] exe_req_0_bits_uop_inst; // @[lsu.scala:383:25] wire [6:0] exe_req_0_bits_uop_uopc; // @[lsu.scala:383:25] wire exe_req_0_bits_uop_ctrl_is_std; // @[lsu.scala:383:25] wire exe_req_0_bits_uop_ctrl_is_sta; // @[lsu.scala:383:25] wire exe_req_0_bits_uop_ctrl_is_load; // @[lsu.scala:383:25] wire [2:0] exe_req_0_bits_uop_ctrl_csr_cmd; // @[lsu.scala:383:25] wire exe_req_0_bits_uop_ctrl_fcn_dw; // @[lsu.scala:383:25] wire [4:0] exe_req_0_bits_uop_ctrl_op_fcn; // @[lsu.scala:383:25] wire [2:0] exe_req_0_bits_uop_ctrl_imm_sel; // @[lsu.scala:383:25] wire [2:0] exe_req_0_bits_uop_ctrl_op2_sel; // @[lsu.scala:383:25] wire [1:0] exe_req_0_bits_uop_ctrl_op1_sel; // @[lsu.scala:383:25] wire [3:0] exe_req_0_bits_uop_ctrl_br_type; // @[lsu.scala:383:25] wire _dtlb_io_miss_rdy; // @[lsu.scala:247:20] wire [31:0] _dtlb_io_resp_0_paddr; // @[lsu.scala:247:20] wire _dtlb_io_resp_0_pf_ld; // @[lsu.scala:247:20] wire _dtlb_io_resp_0_pf_st; // @[lsu.scala:247:20] wire _dtlb_io_resp_0_ae_ld; // @[lsu.scala:247:20] wire _dtlb_io_resp_0_ae_st; // @[lsu.scala:247:20] wire _dtlb_io_resp_0_ma_ld; // @[lsu.scala:247:20] wire _dtlb_io_resp_0_ma_st; // @[lsu.scala:247:20] wire _dtlb_io_resp_0_cacheable; // @[lsu.scala:247:20] wire io_ptw_req_ready_0 = io_ptw_req_ready; // @[lsu.scala:201:7] wire io_ptw_resp_valid_0 = io_ptw_resp_valid; // @[lsu.scala:201:7] wire io_ptw_resp_bits_ae_ptw_0 = io_ptw_resp_bits_ae_ptw; // @[lsu.scala:201:7] wire io_ptw_resp_bits_ae_final_0 = io_ptw_resp_bits_ae_final; // @[lsu.scala:201:7] wire io_ptw_resp_bits_pf_0 = io_ptw_resp_bits_pf; // @[lsu.scala:201:7] wire io_ptw_resp_bits_gf_0 = io_ptw_resp_bits_gf; // @[lsu.scala:201:7] wire io_ptw_resp_bits_hr_0 = io_ptw_resp_bits_hr; // @[lsu.scala:201:7] wire io_ptw_resp_bits_hw_0 = io_ptw_resp_bits_hw; // @[lsu.scala:201:7] wire io_ptw_resp_bits_hx_0 = io_ptw_resp_bits_hx; // @[lsu.scala:201:7] wire [9:0] io_ptw_resp_bits_pte_reserved_for_future_0 = io_ptw_resp_bits_pte_reserved_for_future; // @[lsu.scala:201:7] wire [43:0] io_ptw_resp_bits_pte_ppn_0 = io_ptw_resp_bits_pte_ppn; // @[lsu.scala:201:7] wire [1:0] io_ptw_resp_bits_pte_reserved_for_software_0 = io_ptw_resp_bits_pte_reserved_for_software; // @[lsu.scala:201:7] wire io_ptw_resp_bits_pte_d_0 = io_ptw_resp_bits_pte_d; // @[lsu.scala:201:7] wire io_ptw_resp_bits_pte_a_0 = io_ptw_resp_bits_pte_a; // @[lsu.scala:201:7] wire io_ptw_resp_bits_pte_g_0 = io_ptw_resp_bits_pte_g; // @[lsu.scala:201:7] wire io_ptw_resp_bits_pte_u_0 = io_ptw_resp_bits_pte_u; // @[lsu.scala:201:7] wire io_ptw_resp_bits_pte_x_0 = io_ptw_resp_bits_pte_x; // @[lsu.scala:201:7] wire io_ptw_resp_bits_pte_w_0 = io_ptw_resp_bits_pte_w; // @[lsu.scala:201:7] wire io_ptw_resp_bits_pte_r_0 = io_ptw_resp_bits_pte_r; // @[lsu.scala:201:7] wire io_ptw_resp_bits_pte_v_0 = io_ptw_resp_bits_pte_v; // @[lsu.scala:201:7] wire [1:0] io_ptw_resp_bits_level_0 = io_ptw_resp_bits_level; // @[lsu.scala:201:7] wire io_ptw_resp_bits_homogeneous_0 = io_ptw_resp_bits_homogeneous; // @[lsu.scala:201:7] wire io_ptw_resp_bits_gpa_valid_0 = io_ptw_resp_bits_gpa_valid; // @[lsu.scala:201:7] wire [38:0] io_ptw_resp_bits_gpa_bits_0 = io_ptw_resp_bits_gpa_bits; // @[lsu.scala:201:7] wire io_ptw_resp_bits_gpa_is_pte_0 = io_ptw_resp_bits_gpa_is_pte; // @[lsu.scala:201:7] wire [3:0] io_ptw_ptbr_mode_0 = io_ptw_ptbr_mode; // @[lsu.scala:201:7] wire [43:0] io_ptw_ptbr_ppn_0 = io_ptw_ptbr_ppn; // @[lsu.scala:201:7] wire io_ptw_status_debug_0 = io_ptw_status_debug; // @[lsu.scala:201:7] wire io_ptw_status_cease_0 = io_ptw_status_cease; // @[lsu.scala:201:7] wire io_ptw_status_wfi_0 = io_ptw_status_wfi; // @[lsu.scala:201:7] wire [1:0] io_ptw_status_dprv_0 = io_ptw_status_dprv; // @[lsu.scala:201:7] wire io_ptw_status_dv_0 = io_ptw_status_dv; // @[lsu.scala:201:7] wire [1:0] io_ptw_status_prv_0 = io_ptw_status_prv; // @[lsu.scala:201:7] wire io_ptw_status_v_0 = io_ptw_status_v; // @[lsu.scala:201:7] wire io_ptw_status_sd_0 = io_ptw_status_sd; // @[lsu.scala:201:7] wire io_ptw_status_mpv_0 = io_ptw_status_mpv; // @[lsu.scala:201:7] wire io_ptw_status_gva_0 = io_ptw_status_gva; // @[lsu.scala:201:7] wire io_ptw_status_tsr_0 = io_ptw_status_tsr; // @[lsu.scala:201:7] wire io_ptw_status_tw_0 = io_ptw_status_tw; // @[lsu.scala:201:7] wire io_ptw_status_tvm_0 = io_ptw_status_tvm; // @[lsu.scala:201:7] wire io_ptw_status_mxr_0 = io_ptw_status_mxr; // @[lsu.scala:201:7] wire io_ptw_status_sum_0 = io_ptw_status_sum; // @[lsu.scala:201:7] wire io_ptw_status_mprv_0 = io_ptw_status_mprv; // @[lsu.scala:201:7] wire [1:0] io_ptw_status_fs_0 = io_ptw_status_fs; // @[lsu.scala:201:7] wire [1:0] io_ptw_status_mpp_0 = io_ptw_status_mpp; // @[lsu.scala:201:7] wire io_ptw_status_spp_0 = io_ptw_status_spp; // @[lsu.scala:201:7] wire io_ptw_status_mpie_0 = io_ptw_status_mpie; // @[lsu.scala:201:7] wire io_ptw_status_spie_0 = io_ptw_status_spie; // @[lsu.scala:201:7] wire io_ptw_status_mie_0 = io_ptw_status_mie; // @[lsu.scala:201:7] wire io_ptw_status_sie_0 = io_ptw_status_sie; // @[lsu.scala:201:7] wire io_ptw_pmp_0_cfg_l_0 = io_ptw_pmp_0_cfg_l; // @[lsu.scala:201:7] wire [1:0] io_ptw_pmp_0_cfg_a_0 = io_ptw_pmp_0_cfg_a; // @[lsu.scala:201:7] wire io_ptw_pmp_0_cfg_x_0 = io_ptw_pmp_0_cfg_x; // @[lsu.scala:201:7] wire io_ptw_pmp_0_cfg_w_0 = io_ptw_pmp_0_cfg_w; // @[lsu.scala:201:7] wire io_ptw_pmp_0_cfg_r_0 = io_ptw_pmp_0_cfg_r; // @[lsu.scala:201:7] wire [29:0] io_ptw_pmp_0_addr_0 = io_ptw_pmp_0_addr; // @[lsu.scala:201:7] wire [31:0] io_ptw_pmp_0_mask_0 = io_ptw_pmp_0_mask; // @[lsu.scala:201:7] wire io_ptw_pmp_1_cfg_l_0 = io_ptw_pmp_1_cfg_l; // @[lsu.scala:201:7] wire [1:0] io_ptw_pmp_1_cfg_a_0 = io_ptw_pmp_1_cfg_a; // @[lsu.scala:201:7] wire io_ptw_pmp_1_cfg_x_0 = io_ptw_pmp_1_cfg_x; // @[lsu.scala:201:7] wire io_ptw_pmp_1_cfg_w_0 = io_ptw_pmp_1_cfg_w; // @[lsu.scala:201:7] wire io_ptw_pmp_1_cfg_r_0 = io_ptw_pmp_1_cfg_r; // @[lsu.scala:201:7] wire [29:0] io_ptw_pmp_1_addr_0 = io_ptw_pmp_1_addr; // @[lsu.scala:201:7] wire [31:0] io_ptw_pmp_1_mask_0 = io_ptw_pmp_1_mask; // @[lsu.scala:201:7] wire io_ptw_pmp_2_cfg_l_0 = io_ptw_pmp_2_cfg_l; // @[lsu.scala:201:7] wire [1:0] io_ptw_pmp_2_cfg_a_0 = io_ptw_pmp_2_cfg_a; // @[lsu.scala:201:7] wire io_ptw_pmp_2_cfg_x_0 = io_ptw_pmp_2_cfg_x; // @[lsu.scala:201:7] wire io_ptw_pmp_2_cfg_w_0 = io_ptw_pmp_2_cfg_w; // @[lsu.scala:201:7] wire io_ptw_pmp_2_cfg_r_0 = io_ptw_pmp_2_cfg_r; // @[lsu.scala:201:7] wire [29:0] io_ptw_pmp_2_addr_0 = io_ptw_pmp_2_addr; // @[lsu.scala:201:7] wire [31:0] io_ptw_pmp_2_mask_0 = io_ptw_pmp_2_mask; // @[lsu.scala:201:7] wire io_ptw_pmp_3_cfg_l_0 = io_ptw_pmp_3_cfg_l; // @[lsu.scala:201:7] wire [1:0] io_ptw_pmp_3_cfg_a_0 = io_ptw_pmp_3_cfg_a; // @[lsu.scala:201:7] wire io_ptw_pmp_3_cfg_x_0 = io_ptw_pmp_3_cfg_x; // @[lsu.scala:201:7] wire io_ptw_pmp_3_cfg_w_0 = io_ptw_pmp_3_cfg_w; // @[lsu.scala:201:7] wire io_ptw_pmp_3_cfg_r_0 = io_ptw_pmp_3_cfg_r; // @[lsu.scala:201:7] wire [29:0] io_ptw_pmp_3_addr_0 = io_ptw_pmp_3_addr; // @[lsu.scala:201:7] wire [31:0] io_ptw_pmp_3_mask_0 = io_ptw_pmp_3_mask; // @[lsu.scala:201:7] wire io_ptw_pmp_4_cfg_l_0 = io_ptw_pmp_4_cfg_l; // @[lsu.scala:201:7] wire [1:0] io_ptw_pmp_4_cfg_a_0 = io_ptw_pmp_4_cfg_a; // @[lsu.scala:201:7] wire io_ptw_pmp_4_cfg_x_0 = io_ptw_pmp_4_cfg_x; // @[lsu.scala:201:7] wire io_ptw_pmp_4_cfg_w_0 = io_ptw_pmp_4_cfg_w; // @[lsu.scala:201:7] wire io_ptw_pmp_4_cfg_r_0 = io_ptw_pmp_4_cfg_r; // @[lsu.scala:201:7] wire [29:0] io_ptw_pmp_4_addr_0 = io_ptw_pmp_4_addr; // @[lsu.scala:201:7] wire [31:0] io_ptw_pmp_4_mask_0 = io_ptw_pmp_4_mask; // @[lsu.scala:201:7] wire io_ptw_pmp_5_cfg_l_0 = io_ptw_pmp_5_cfg_l; // @[lsu.scala:201:7] wire [1:0] io_ptw_pmp_5_cfg_a_0 = io_ptw_pmp_5_cfg_a; // @[lsu.scala:201:7] wire io_ptw_pmp_5_cfg_x_0 = io_ptw_pmp_5_cfg_x; // @[lsu.scala:201:7] wire io_ptw_pmp_5_cfg_w_0 = io_ptw_pmp_5_cfg_w; // @[lsu.scala:201:7] wire io_ptw_pmp_5_cfg_r_0 = io_ptw_pmp_5_cfg_r; // @[lsu.scala:201:7] wire [29:0] io_ptw_pmp_5_addr_0 = io_ptw_pmp_5_addr; // @[lsu.scala:201:7] wire [31:0] io_ptw_pmp_5_mask_0 = io_ptw_pmp_5_mask; // @[lsu.scala:201:7] wire io_ptw_pmp_6_cfg_l_0 = io_ptw_pmp_6_cfg_l; // @[lsu.scala:201:7] wire [1:0] io_ptw_pmp_6_cfg_a_0 = io_ptw_pmp_6_cfg_a; // @[lsu.scala:201:7] wire io_ptw_pmp_6_cfg_x_0 = io_ptw_pmp_6_cfg_x; // @[lsu.scala:201:7] wire io_ptw_pmp_6_cfg_w_0 = io_ptw_pmp_6_cfg_w; // @[lsu.scala:201:7] wire io_ptw_pmp_6_cfg_r_0 = io_ptw_pmp_6_cfg_r; // @[lsu.scala:201:7] wire [29:0] io_ptw_pmp_6_addr_0 = io_ptw_pmp_6_addr; // @[lsu.scala:201:7] wire [31:0] io_ptw_pmp_6_mask_0 = io_ptw_pmp_6_mask; // @[lsu.scala:201:7] wire io_ptw_pmp_7_cfg_l_0 = io_ptw_pmp_7_cfg_l; // @[lsu.scala:201:7] wire [1:0] io_ptw_pmp_7_cfg_a_0 = io_ptw_pmp_7_cfg_a; // @[lsu.scala:201:7] wire io_ptw_pmp_7_cfg_x_0 = io_ptw_pmp_7_cfg_x; // @[lsu.scala:201:7] wire io_ptw_pmp_7_cfg_w_0 = io_ptw_pmp_7_cfg_w; // @[lsu.scala:201:7] wire io_ptw_pmp_7_cfg_r_0 = io_ptw_pmp_7_cfg_r; // @[lsu.scala:201:7] wire [29:0] io_ptw_pmp_7_addr_0 = io_ptw_pmp_7_addr; // @[lsu.scala:201:7] wire [31:0] io_ptw_pmp_7_mask_0 = io_ptw_pmp_7_mask; // @[lsu.scala:201:7] wire io_core_exe_0_req_valid_0 = io_core_exe_0_req_valid; // @[lsu.scala:201:7] wire [6:0] io_core_exe_0_req_bits_uop_uopc_0 = io_core_exe_0_req_bits_uop_uopc; // @[lsu.scala:201:7] wire [31:0] io_core_exe_0_req_bits_uop_inst_0 = io_core_exe_0_req_bits_uop_inst; // @[lsu.scala:201:7] wire [31:0] io_core_exe_0_req_bits_uop_debug_inst_0 = io_core_exe_0_req_bits_uop_debug_inst; // @[lsu.scala:201:7] wire io_core_exe_0_req_bits_uop_is_rvc_0 = io_core_exe_0_req_bits_uop_is_rvc; // @[lsu.scala:201:7] wire [39:0] io_core_exe_0_req_bits_uop_debug_pc_0 = io_core_exe_0_req_bits_uop_debug_pc; // @[lsu.scala:201:7] wire [2:0] io_core_exe_0_req_bits_uop_iq_type_0 = io_core_exe_0_req_bits_uop_iq_type; // @[lsu.scala:201:7] wire [9:0] io_core_exe_0_req_bits_uop_fu_code_0 = io_core_exe_0_req_bits_uop_fu_code; // @[lsu.scala:201:7] wire [3:0] io_core_exe_0_req_bits_uop_ctrl_br_type_0 = io_core_exe_0_req_bits_uop_ctrl_br_type; // @[lsu.scala:201:7] wire [1:0] io_core_exe_0_req_bits_uop_ctrl_op1_sel_0 = io_core_exe_0_req_bits_uop_ctrl_op1_sel; // @[lsu.scala:201:7] wire [2:0] io_core_exe_0_req_bits_uop_ctrl_op2_sel_0 = io_core_exe_0_req_bits_uop_ctrl_op2_sel; // @[lsu.scala:201:7] wire [2:0] io_core_exe_0_req_bits_uop_ctrl_imm_sel_0 = io_core_exe_0_req_bits_uop_ctrl_imm_sel; // @[lsu.scala:201:7] wire [4:0] io_core_exe_0_req_bits_uop_ctrl_op_fcn_0 = io_core_exe_0_req_bits_uop_ctrl_op_fcn; // @[lsu.scala:201:7] wire io_core_exe_0_req_bits_uop_ctrl_fcn_dw_0 = io_core_exe_0_req_bits_uop_ctrl_fcn_dw; // @[lsu.scala:201:7] wire [2:0] io_core_exe_0_req_bits_uop_ctrl_csr_cmd_0 = io_core_exe_0_req_bits_uop_ctrl_csr_cmd; // @[lsu.scala:201:7] wire io_core_exe_0_req_bits_uop_ctrl_is_load_0 = io_core_exe_0_req_bits_uop_ctrl_is_load; // @[lsu.scala:201:7] wire io_core_exe_0_req_bits_uop_ctrl_is_sta_0 = io_core_exe_0_req_bits_uop_ctrl_is_sta; // @[lsu.scala:201:7] wire io_core_exe_0_req_bits_uop_ctrl_is_std_0 = io_core_exe_0_req_bits_uop_ctrl_is_std; // @[lsu.scala:201:7] wire [1:0] io_core_exe_0_req_bits_uop_iw_state_0 = io_core_exe_0_req_bits_uop_iw_state; // @[lsu.scala:201:7] wire io_core_exe_0_req_bits_uop_iw_p1_poisoned_0 = io_core_exe_0_req_bits_uop_iw_p1_poisoned; // @[lsu.scala:201:7] wire io_core_exe_0_req_bits_uop_iw_p2_poisoned_0 = io_core_exe_0_req_bits_uop_iw_p2_poisoned; // @[lsu.scala:201:7] wire io_core_exe_0_req_bits_uop_is_br_0 = io_core_exe_0_req_bits_uop_is_br; // @[lsu.scala:201:7] wire io_core_exe_0_req_bits_uop_is_jalr_0 = io_core_exe_0_req_bits_uop_is_jalr; // @[lsu.scala:201:7] wire io_core_exe_0_req_bits_uop_is_jal_0 = io_core_exe_0_req_bits_uop_is_jal; // @[lsu.scala:201:7] wire io_core_exe_0_req_bits_uop_is_sfb_0 = io_core_exe_0_req_bits_uop_is_sfb; // @[lsu.scala:201:7] wire [7:0] io_core_exe_0_req_bits_uop_br_mask_0 = io_core_exe_0_req_bits_uop_br_mask; // @[lsu.scala:201:7] wire [2:0] io_core_exe_0_req_bits_uop_br_tag_0 = io_core_exe_0_req_bits_uop_br_tag; // @[lsu.scala:201:7] wire [3:0] io_core_exe_0_req_bits_uop_ftq_idx_0 = io_core_exe_0_req_bits_uop_ftq_idx; // @[lsu.scala:201:7] wire io_core_exe_0_req_bits_uop_edge_inst_0 = io_core_exe_0_req_bits_uop_edge_inst; // @[lsu.scala:201:7] wire [5:0] io_core_exe_0_req_bits_uop_pc_lob_0 = io_core_exe_0_req_bits_uop_pc_lob; // @[lsu.scala:201:7] wire io_core_exe_0_req_bits_uop_taken_0 = io_core_exe_0_req_bits_uop_taken; // @[lsu.scala:201:7] wire [19:0] io_core_exe_0_req_bits_uop_imm_packed_0 = io_core_exe_0_req_bits_uop_imm_packed; // @[lsu.scala:201:7] wire [11:0] io_core_exe_0_req_bits_uop_csr_addr_0 = io_core_exe_0_req_bits_uop_csr_addr; // @[lsu.scala:201:7] wire [4:0] io_core_exe_0_req_bits_uop_rob_idx_0 = io_core_exe_0_req_bits_uop_rob_idx; // @[lsu.scala:201:7] wire [2:0] io_core_exe_0_req_bits_uop_ldq_idx_0 = io_core_exe_0_req_bits_uop_ldq_idx; // @[lsu.scala:201:7] wire [2:0] io_core_exe_0_req_bits_uop_stq_idx_0 = io_core_exe_0_req_bits_uop_stq_idx; // @[lsu.scala:201:7] wire [1:0] io_core_exe_0_req_bits_uop_rxq_idx_0 = io_core_exe_0_req_bits_uop_rxq_idx; // @[lsu.scala:201:7] wire [5:0] io_core_exe_0_req_bits_uop_pdst_0 = io_core_exe_0_req_bits_uop_pdst; // @[lsu.scala:201:7] wire [5:0] io_core_exe_0_req_bits_uop_prs1_0 = io_core_exe_0_req_bits_uop_prs1; // @[lsu.scala:201:7] wire [5:0] io_core_exe_0_req_bits_uop_prs2_0 = io_core_exe_0_req_bits_uop_prs2; // @[lsu.scala:201:7] wire [5:0] io_core_exe_0_req_bits_uop_prs3_0 = io_core_exe_0_req_bits_uop_prs3; // @[lsu.scala:201:7] wire [3:0] io_core_exe_0_req_bits_uop_ppred_0 = io_core_exe_0_req_bits_uop_ppred; // @[lsu.scala:201:7] wire io_core_exe_0_req_bits_uop_prs1_busy_0 = io_core_exe_0_req_bits_uop_prs1_busy; // @[lsu.scala:201:7] wire io_core_exe_0_req_bits_uop_prs2_busy_0 = io_core_exe_0_req_bits_uop_prs2_busy; // @[lsu.scala:201:7] wire io_core_exe_0_req_bits_uop_prs3_busy_0 = io_core_exe_0_req_bits_uop_prs3_busy; // @[lsu.scala:201:7] wire io_core_exe_0_req_bits_uop_ppred_busy_0 = io_core_exe_0_req_bits_uop_ppred_busy; // @[lsu.scala:201:7] wire [5:0] io_core_exe_0_req_bits_uop_stale_pdst_0 = io_core_exe_0_req_bits_uop_stale_pdst; // @[lsu.scala:201:7] wire io_core_exe_0_req_bits_uop_exception_0 = io_core_exe_0_req_bits_uop_exception; // @[lsu.scala:201:7] wire [63:0] io_core_exe_0_req_bits_uop_exc_cause_0 = io_core_exe_0_req_bits_uop_exc_cause; // @[lsu.scala:201:7] wire io_core_exe_0_req_bits_uop_bypassable_0 = io_core_exe_0_req_bits_uop_bypassable; // @[lsu.scala:201:7] wire [4:0] io_core_exe_0_req_bits_uop_mem_cmd_0 = io_core_exe_0_req_bits_uop_mem_cmd; // @[lsu.scala:201:7] wire [1:0] io_core_exe_0_req_bits_uop_mem_size_0 = io_core_exe_0_req_bits_uop_mem_size; // @[lsu.scala:201:7] wire io_core_exe_0_req_bits_uop_mem_signed_0 = io_core_exe_0_req_bits_uop_mem_signed; // @[lsu.scala:201:7] wire io_core_exe_0_req_bits_uop_is_fence_0 = io_core_exe_0_req_bits_uop_is_fence; // @[lsu.scala:201:7] wire io_core_exe_0_req_bits_uop_is_fencei_0 = io_core_exe_0_req_bits_uop_is_fencei; // @[lsu.scala:201:7] wire io_core_exe_0_req_bits_uop_is_amo_0 = io_core_exe_0_req_bits_uop_is_amo; // @[lsu.scala:201:7] wire io_core_exe_0_req_bits_uop_uses_ldq_0 = io_core_exe_0_req_bits_uop_uses_ldq; // @[lsu.scala:201:7] wire io_core_exe_0_req_bits_uop_uses_stq_0 = io_core_exe_0_req_bits_uop_uses_stq; // @[lsu.scala:201:7] wire io_core_exe_0_req_bits_uop_is_sys_pc2epc_0 = io_core_exe_0_req_bits_uop_is_sys_pc2epc; // @[lsu.scala:201:7] wire io_core_exe_0_req_bits_uop_is_unique_0 = io_core_exe_0_req_bits_uop_is_unique; // @[lsu.scala:201:7] wire io_core_exe_0_req_bits_uop_flush_on_commit_0 = io_core_exe_0_req_bits_uop_flush_on_commit; // @[lsu.scala:201:7] wire io_core_exe_0_req_bits_uop_ldst_is_rs1_0 = io_core_exe_0_req_bits_uop_ldst_is_rs1; // @[lsu.scala:201:7] wire [5:0] io_core_exe_0_req_bits_uop_ldst_0 = io_core_exe_0_req_bits_uop_ldst; // @[lsu.scala:201:7] wire [5:0] io_core_exe_0_req_bits_uop_lrs1_0 = io_core_exe_0_req_bits_uop_lrs1; // @[lsu.scala:201:7] wire [5:0] io_core_exe_0_req_bits_uop_lrs2_0 = io_core_exe_0_req_bits_uop_lrs2; // @[lsu.scala:201:7] wire [5:0] io_core_exe_0_req_bits_uop_lrs3_0 = io_core_exe_0_req_bits_uop_lrs3; // @[lsu.scala:201:7] wire io_core_exe_0_req_bits_uop_ldst_val_0 = io_core_exe_0_req_bits_uop_ldst_val; // @[lsu.scala:201:7] wire [1:0] io_core_exe_0_req_bits_uop_dst_rtype_0 = io_core_exe_0_req_bits_uop_dst_rtype; // @[lsu.scala:201:7] wire [1:0] io_core_exe_0_req_bits_uop_lrs1_rtype_0 = io_core_exe_0_req_bits_uop_lrs1_rtype; // @[lsu.scala:201:7] wire [1:0] io_core_exe_0_req_bits_uop_lrs2_rtype_0 = io_core_exe_0_req_bits_uop_lrs2_rtype; // @[lsu.scala:201:7] wire io_core_exe_0_req_bits_uop_frs3_en_0 = io_core_exe_0_req_bits_uop_frs3_en; // @[lsu.scala:201:7] wire io_core_exe_0_req_bits_uop_fp_val_0 = io_core_exe_0_req_bits_uop_fp_val; // @[lsu.scala:201:7] wire io_core_exe_0_req_bits_uop_fp_single_0 = io_core_exe_0_req_bits_uop_fp_single; // @[lsu.scala:201:7] wire io_core_exe_0_req_bits_uop_xcpt_pf_if_0 = io_core_exe_0_req_bits_uop_xcpt_pf_if; // @[lsu.scala:201:7] wire io_core_exe_0_req_bits_uop_xcpt_ae_if_0 = io_core_exe_0_req_bits_uop_xcpt_ae_if; // @[lsu.scala:201:7] wire io_core_exe_0_req_bits_uop_xcpt_ma_if_0 = io_core_exe_0_req_bits_uop_xcpt_ma_if; // @[lsu.scala:201:7] wire io_core_exe_0_req_bits_uop_bp_debug_if_0 = io_core_exe_0_req_bits_uop_bp_debug_if; // @[lsu.scala:201:7] wire io_core_exe_0_req_bits_uop_bp_xcpt_if_0 = io_core_exe_0_req_bits_uop_bp_xcpt_if; // @[lsu.scala:201:7] wire [1:0] io_core_exe_0_req_bits_uop_debug_fsrc_0 = io_core_exe_0_req_bits_uop_debug_fsrc; // @[lsu.scala:201:7] wire [1:0] io_core_exe_0_req_bits_uop_debug_tsrc_0 = io_core_exe_0_req_bits_uop_debug_tsrc; // @[lsu.scala:201:7] wire [63:0] io_core_exe_0_req_bits_data_0 = io_core_exe_0_req_bits_data; // @[lsu.scala:201:7] wire [39:0] io_core_exe_0_req_bits_addr_0 = io_core_exe_0_req_bits_addr; // @[lsu.scala:201:7] wire io_core_exe_0_req_bits_mxcpt_valid_0 = io_core_exe_0_req_bits_mxcpt_valid; // @[lsu.scala:201:7] wire [24:0] io_core_exe_0_req_bits_mxcpt_bits_0 = io_core_exe_0_req_bits_mxcpt_bits; // @[lsu.scala:201:7] wire io_core_exe_0_req_bits_sfence_valid_0 = io_core_exe_0_req_bits_sfence_valid; // @[lsu.scala:201:7] wire io_core_exe_0_req_bits_sfence_bits_rs1_0 = io_core_exe_0_req_bits_sfence_bits_rs1; // @[lsu.scala:201:7] wire io_core_exe_0_req_bits_sfence_bits_rs2_0 = io_core_exe_0_req_bits_sfence_bits_rs2; // @[lsu.scala:201:7] wire [38:0] io_core_exe_0_req_bits_sfence_bits_addr_0 = io_core_exe_0_req_bits_sfence_bits_addr; // @[lsu.scala:201:7] wire io_core_exe_0_req_bits_sfence_bits_asid_0 = io_core_exe_0_req_bits_sfence_bits_asid; // @[lsu.scala:201:7] wire io_core_dis_uops_0_valid_0 = io_core_dis_uops_0_valid; // @[lsu.scala:201:7] wire [6:0] io_core_dis_uops_0_bits_uopc_0 = io_core_dis_uops_0_bits_uopc; // @[lsu.scala:201:7] wire [31:0] io_core_dis_uops_0_bits_inst_0 = io_core_dis_uops_0_bits_inst; // @[lsu.scala:201:7] wire [31:0] io_core_dis_uops_0_bits_debug_inst_0 = io_core_dis_uops_0_bits_debug_inst; // @[lsu.scala:201:7] wire io_core_dis_uops_0_bits_is_rvc_0 = io_core_dis_uops_0_bits_is_rvc; // @[lsu.scala:201:7] wire [39:0] io_core_dis_uops_0_bits_debug_pc_0 = io_core_dis_uops_0_bits_debug_pc; // @[lsu.scala:201:7] wire [2:0] io_core_dis_uops_0_bits_iq_type_0 = io_core_dis_uops_0_bits_iq_type; // @[lsu.scala:201:7] wire [9:0] io_core_dis_uops_0_bits_fu_code_0 = io_core_dis_uops_0_bits_fu_code; // @[lsu.scala:201:7] wire [3:0] io_core_dis_uops_0_bits_ctrl_br_type_0 = io_core_dis_uops_0_bits_ctrl_br_type; // @[lsu.scala:201:7] wire [1:0] io_core_dis_uops_0_bits_ctrl_op1_sel_0 = io_core_dis_uops_0_bits_ctrl_op1_sel; // @[lsu.scala:201:7] wire [2:0] io_core_dis_uops_0_bits_ctrl_op2_sel_0 = io_core_dis_uops_0_bits_ctrl_op2_sel; // @[lsu.scala:201:7] wire [2:0] io_core_dis_uops_0_bits_ctrl_imm_sel_0 = io_core_dis_uops_0_bits_ctrl_imm_sel; // @[lsu.scala:201:7] wire [4:0] io_core_dis_uops_0_bits_ctrl_op_fcn_0 = io_core_dis_uops_0_bits_ctrl_op_fcn; // @[lsu.scala:201:7] wire io_core_dis_uops_0_bits_ctrl_fcn_dw_0 = io_core_dis_uops_0_bits_ctrl_fcn_dw; // @[lsu.scala:201:7] wire [2:0] io_core_dis_uops_0_bits_ctrl_csr_cmd_0 = io_core_dis_uops_0_bits_ctrl_csr_cmd; // @[lsu.scala:201:7] wire io_core_dis_uops_0_bits_ctrl_is_load_0 = io_core_dis_uops_0_bits_ctrl_is_load; // @[lsu.scala:201:7] wire io_core_dis_uops_0_bits_ctrl_is_sta_0 = io_core_dis_uops_0_bits_ctrl_is_sta; // @[lsu.scala:201:7] wire io_core_dis_uops_0_bits_ctrl_is_std_0 = io_core_dis_uops_0_bits_ctrl_is_std; // @[lsu.scala:201:7] wire [1:0] io_core_dis_uops_0_bits_iw_state_0 = io_core_dis_uops_0_bits_iw_state; // @[lsu.scala:201:7] wire io_core_dis_uops_0_bits_iw_p1_poisoned_0 = io_core_dis_uops_0_bits_iw_p1_poisoned; // @[lsu.scala:201:7] wire io_core_dis_uops_0_bits_iw_p2_poisoned_0 = io_core_dis_uops_0_bits_iw_p2_poisoned; // @[lsu.scala:201:7] wire io_core_dis_uops_0_bits_is_br_0 = io_core_dis_uops_0_bits_is_br; // @[lsu.scala:201:7] wire io_core_dis_uops_0_bits_is_jalr_0 = io_core_dis_uops_0_bits_is_jalr; // @[lsu.scala:201:7] wire io_core_dis_uops_0_bits_is_jal_0 = io_core_dis_uops_0_bits_is_jal; // @[lsu.scala:201:7] wire io_core_dis_uops_0_bits_is_sfb_0 = io_core_dis_uops_0_bits_is_sfb; // @[lsu.scala:201:7] wire [7:0] io_core_dis_uops_0_bits_br_mask_0 = io_core_dis_uops_0_bits_br_mask; // @[lsu.scala:201:7] wire [2:0] io_core_dis_uops_0_bits_br_tag_0 = io_core_dis_uops_0_bits_br_tag; // @[lsu.scala:201:7] wire [3:0] io_core_dis_uops_0_bits_ftq_idx_0 = io_core_dis_uops_0_bits_ftq_idx; // @[lsu.scala:201:7] wire io_core_dis_uops_0_bits_edge_inst_0 = io_core_dis_uops_0_bits_edge_inst; // @[lsu.scala:201:7] wire [5:0] io_core_dis_uops_0_bits_pc_lob_0 = io_core_dis_uops_0_bits_pc_lob; // @[lsu.scala:201:7] wire io_core_dis_uops_0_bits_taken_0 = io_core_dis_uops_0_bits_taken; // @[lsu.scala:201:7] wire [19:0] io_core_dis_uops_0_bits_imm_packed_0 = io_core_dis_uops_0_bits_imm_packed; // @[lsu.scala:201:7] wire [11:0] io_core_dis_uops_0_bits_csr_addr_0 = io_core_dis_uops_0_bits_csr_addr; // @[lsu.scala:201:7] wire [4:0] io_core_dis_uops_0_bits_rob_idx_0 = io_core_dis_uops_0_bits_rob_idx; // @[lsu.scala:201:7] wire [2:0] io_core_dis_uops_0_bits_ldq_idx_0 = io_core_dis_uops_0_bits_ldq_idx; // @[lsu.scala:201:7] wire [2:0] io_core_dis_uops_0_bits_stq_idx_0 = io_core_dis_uops_0_bits_stq_idx; // @[lsu.scala:201:7] wire [1:0] io_core_dis_uops_0_bits_rxq_idx_0 = io_core_dis_uops_0_bits_rxq_idx; // @[lsu.scala:201:7] wire [5:0] io_core_dis_uops_0_bits_pdst_0 = io_core_dis_uops_0_bits_pdst; // @[lsu.scala:201:7] wire [5:0] io_core_dis_uops_0_bits_prs1_0 = io_core_dis_uops_0_bits_prs1; // @[lsu.scala:201:7] wire [5:0] io_core_dis_uops_0_bits_prs2_0 = io_core_dis_uops_0_bits_prs2; // @[lsu.scala:201:7] wire [5:0] io_core_dis_uops_0_bits_prs3_0 = io_core_dis_uops_0_bits_prs3; // @[lsu.scala:201:7] wire io_core_dis_uops_0_bits_prs1_busy_0 = io_core_dis_uops_0_bits_prs1_busy; // @[lsu.scala:201:7] wire io_core_dis_uops_0_bits_prs2_busy_0 = io_core_dis_uops_0_bits_prs2_busy; // @[lsu.scala:201:7] wire io_core_dis_uops_0_bits_prs3_busy_0 = io_core_dis_uops_0_bits_prs3_busy; // @[lsu.scala:201:7] wire [5:0] io_core_dis_uops_0_bits_stale_pdst_0 = io_core_dis_uops_0_bits_stale_pdst; // @[lsu.scala:201:7] wire io_core_dis_uops_0_bits_exception_0 = io_core_dis_uops_0_bits_exception; // @[lsu.scala:201:7] wire [63:0] io_core_dis_uops_0_bits_exc_cause_0 = io_core_dis_uops_0_bits_exc_cause; // @[lsu.scala:201:7] wire io_core_dis_uops_0_bits_bypassable_0 = io_core_dis_uops_0_bits_bypassable; // @[lsu.scala:201:7] wire [4:0] io_core_dis_uops_0_bits_mem_cmd_0 = io_core_dis_uops_0_bits_mem_cmd; // @[lsu.scala:201:7] wire [1:0] io_core_dis_uops_0_bits_mem_size_0 = io_core_dis_uops_0_bits_mem_size; // @[lsu.scala:201:7] wire io_core_dis_uops_0_bits_mem_signed_0 = io_core_dis_uops_0_bits_mem_signed; // @[lsu.scala:201:7] wire io_core_dis_uops_0_bits_is_fence_0 = io_core_dis_uops_0_bits_is_fence; // @[lsu.scala:201:7] wire io_core_dis_uops_0_bits_is_fencei_0 = io_core_dis_uops_0_bits_is_fencei; // @[lsu.scala:201:7] wire io_core_dis_uops_0_bits_is_amo_0 = io_core_dis_uops_0_bits_is_amo; // @[lsu.scala:201:7] wire io_core_dis_uops_0_bits_uses_ldq_0 = io_core_dis_uops_0_bits_uses_ldq; // @[lsu.scala:201:7] wire io_core_dis_uops_0_bits_uses_stq_0 = io_core_dis_uops_0_bits_uses_stq; // @[lsu.scala:201:7] wire io_core_dis_uops_0_bits_is_sys_pc2epc_0 = io_core_dis_uops_0_bits_is_sys_pc2epc; // @[lsu.scala:201:7] wire io_core_dis_uops_0_bits_is_unique_0 = io_core_dis_uops_0_bits_is_unique; // @[lsu.scala:201:7] wire io_core_dis_uops_0_bits_flush_on_commit_0 = io_core_dis_uops_0_bits_flush_on_commit; // @[lsu.scala:201:7] wire io_core_dis_uops_0_bits_ldst_is_rs1_0 = io_core_dis_uops_0_bits_ldst_is_rs1; // @[lsu.scala:201:7] wire [5:0] io_core_dis_uops_0_bits_ldst_0 = io_core_dis_uops_0_bits_ldst; // @[lsu.scala:201:7] wire [5:0] io_core_dis_uops_0_bits_lrs1_0 = io_core_dis_uops_0_bits_lrs1; // @[lsu.scala:201:7] wire [5:0] io_core_dis_uops_0_bits_lrs2_0 = io_core_dis_uops_0_bits_lrs2; // @[lsu.scala:201:7] wire [5:0] io_core_dis_uops_0_bits_lrs3_0 = io_core_dis_uops_0_bits_lrs3; // @[lsu.scala:201:7] wire io_core_dis_uops_0_bits_ldst_val_0 = io_core_dis_uops_0_bits_ldst_val; // @[lsu.scala:201:7] wire [1:0] io_core_dis_uops_0_bits_dst_rtype_0 = io_core_dis_uops_0_bits_dst_rtype; // @[lsu.scala:201:7] wire [1:0] io_core_dis_uops_0_bits_lrs1_rtype_0 = io_core_dis_uops_0_bits_lrs1_rtype; // @[lsu.scala:201:7] wire [1:0] io_core_dis_uops_0_bits_lrs2_rtype_0 = io_core_dis_uops_0_bits_lrs2_rtype; // @[lsu.scala:201:7] wire io_core_dis_uops_0_bits_frs3_en_0 = io_core_dis_uops_0_bits_frs3_en; // @[lsu.scala:201:7] wire io_core_dis_uops_0_bits_fp_val_0 = io_core_dis_uops_0_bits_fp_val; // @[lsu.scala:201:7] wire io_core_dis_uops_0_bits_fp_single_0 = io_core_dis_uops_0_bits_fp_single; // @[lsu.scala:201:7] wire io_core_dis_uops_0_bits_xcpt_pf_if_0 = io_core_dis_uops_0_bits_xcpt_pf_if; // @[lsu.scala:201:7] wire io_core_dis_uops_0_bits_xcpt_ae_if_0 = io_core_dis_uops_0_bits_xcpt_ae_if; // @[lsu.scala:201:7] wire io_core_dis_uops_0_bits_xcpt_ma_if_0 = io_core_dis_uops_0_bits_xcpt_ma_if; // @[lsu.scala:201:7] wire io_core_dis_uops_0_bits_bp_debug_if_0 = io_core_dis_uops_0_bits_bp_debug_if; // @[lsu.scala:201:7] wire io_core_dis_uops_0_bits_bp_xcpt_if_0 = io_core_dis_uops_0_bits_bp_xcpt_if; // @[lsu.scala:201:7] wire [1:0] io_core_dis_uops_0_bits_debug_fsrc_0 = io_core_dis_uops_0_bits_debug_fsrc; // @[lsu.scala:201:7] wire [1:0] io_core_dis_uops_0_bits_debug_tsrc_0 = io_core_dis_uops_0_bits_debug_tsrc; // @[lsu.scala:201:7] wire io_core_fp_stdata_valid_0 = io_core_fp_stdata_valid; // @[lsu.scala:201:7] wire [6:0] io_core_fp_stdata_bits_uop_uopc_0 = io_core_fp_stdata_bits_uop_uopc; // @[lsu.scala:201:7] wire [31:0] io_core_fp_stdata_bits_uop_inst_0 = io_core_fp_stdata_bits_uop_inst; // @[lsu.scala:201:7] wire [31:0] io_core_fp_stdata_bits_uop_debug_inst_0 = io_core_fp_stdata_bits_uop_debug_inst; // @[lsu.scala:201:7] wire io_core_fp_stdata_bits_uop_is_rvc_0 = io_core_fp_stdata_bits_uop_is_rvc; // @[lsu.scala:201:7] wire [39:0] io_core_fp_stdata_bits_uop_debug_pc_0 = io_core_fp_stdata_bits_uop_debug_pc; // @[lsu.scala:201:7] wire [2:0] io_core_fp_stdata_bits_uop_iq_type_0 = io_core_fp_stdata_bits_uop_iq_type; // @[lsu.scala:201:7] wire [9:0] io_core_fp_stdata_bits_uop_fu_code_0 = io_core_fp_stdata_bits_uop_fu_code; // @[lsu.scala:201:7] wire [3:0] io_core_fp_stdata_bits_uop_ctrl_br_type_0 = io_core_fp_stdata_bits_uop_ctrl_br_type; // @[lsu.scala:201:7] wire [1:0] io_core_fp_stdata_bits_uop_ctrl_op1_sel_0 = io_core_fp_stdata_bits_uop_ctrl_op1_sel; // @[lsu.scala:201:7] wire [2:0] io_core_fp_stdata_bits_uop_ctrl_op2_sel_0 = io_core_fp_stdata_bits_uop_ctrl_op2_sel; // @[lsu.scala:201:7] wire [2:0] io_core_fp_stdata_bits_uop_ctrl_imm_sel_0 = io_core_fp_stdata_bits_uop_ctrl_imm_sel; // @[lsu.scala:201:7] wire [4:0] io_core_fp_stdata_bits_uop_ctrl_op_fcn_0 = io_core_fp_stdata_bits_uop_ctrl_op_fcn; // @[lsu.scala:201:7] wire io_core_fp_stdata_bits_uop_ctrl_fcn_dw_0 = io_core_fp_stdata_bits_uop_ctrl_fcn_dw; // @[lsu.scala:201:7] wire [2:0] io_core_fp_stdata_bits_uop_ctrl_csr_cmd_0 = io_core_fp_stdata_bits_uop_ctrl_csr_cmd; // @[lsu.scala:201:7] wire io_core_fp_stdata_bits_uop_ctrl_is_load_0 = io_core_fp_stdata_bits_uop_ctrl_is_load; // @[lsu.scala:201:7] wire io_core_fp_stdata_bits_uop_ctrl_is_sta_0 = io_core_fp_stdata_bits_uop_ctrl_is_sta; // @[lsu.scala:201:7] wire io_core_fp_stdata_bits_uop_ctrl_is_std_0 = io_core_fp_stdata_bits_uop_ctrl_is_std; // @[lsu.scala:201:7] wire [1:0] io_core_fp_stdata_bits_uop_iw_state_0 = io_core_fp_stdata_bits_uop_iw_state; // @[lsu.scala:201:7] wire io_core_fp_stdata_bits_uop_iw_p1_poisoned_0 = io_core_fp_stdata_bits_uop_iw_p1_poisoned; // @[lsu.scala:201:7] wire io_core_fp_stdata_bits_uop_iw_p2_poisoned_0 = io_core_fp_stdata_bits_uop_iw_p2_poisoned; // @[lsu.scala:201:7] wire io_core_fp_stdata_bits_uop_is_br_0 = io_core_fp_stdata_bits_uop_is_br; // @[lsu.scala:201:7] wire io_core_fp_stdata_bits_uop_is_jalr_0 = io_core_fp_stdata_bits_uop_is_jalr; // @[lsu.scala:201:7] wire io_core_fp_stdata_bits_uop_is_jal_0 = io_core_fp_stdata_bits_uop_is_jal; // @[lsu.scala:201:7] wire io_core_fp_stdata_bits_uop_is_sfb_0 = io_core_fp_stdata_bits_uop_is_sfb; // @[lsu.scala:201:7] wire [7:0] io_core_fp_stdata_bits_uop_br_mask_0 = io_core_fp_stdata_bits_uop_br_mask; // @[lsu.scala:201:7] wire [2:0] io_core_fp_stdata_bits_uop_br_tag_0 = io_core_fp_stdata_bits_uop_br_tag; // @[lsu.scala:201:7] wire [3:0] io_core_fp_stdata_bits_uop_ftq_idx_0 = io_core_fp_stdata_bits_uop_ftq_idx; // @[lsu.scala:201:7] wire io_core_fp_stdata_bits_uop_edge_inst_0 = io_core_fp_stdata_bits_uop_edge_inst; // @[lsu.scala:201:7] wire [5:0] io_core_fp_stdata_bits_uop_pc_lob_0 = io_core_fp_stdata_bits_uop_pc_lob; // @[lsu.scala:201:7] wire io_core_fp_stdata_bits_uop_taken_0 = io_core_fp_stdata_bits_uop_taken; // @[lsu.scala:201:7] wire [19:0] io_core_fp_stdata_bits_uop_imm_packed_0 = io_core_fp_stdata_bits_uop_imm_packed; // @[lsu.scala:201:7] wire [11:0] io_core_fp_stdata_bits_uop_csr_addr_0 = io_core_fp_stdata_bits_uop_csr_addr; // @[lsu.scala:201:7] wire [4:0] io_core_fp_stdata_bits_uop_rob_idx_0 = io_core_fp_stdata_bits_uop_rob_idx; // @[lsu.scala:201:7] wire [2:0] io_core_fp_stdata_bits_uop_ldq_idx_0 = io_core_fp_stdata_bits_uop_ldq_idx; // @[lsu.scala:201:7] wire [2:0] io_core_fp_stdata_bits_uop_stq_idx_0 = io_core_fp_stdata_bits_uop_stq_idx; // @[lsu.scala:201:7] wire [1:0] io_core_fp_stdata_bits_uop_rxq_idx_0 = io_core_fp_stdata_bits_uop_rxq_idx; // @[lsu.scala:201:7] wire [5:0] io_core_fp_stdata_bits_uop_pdst_0 = io_core_fp_stdata_bits_uop_pdst; // @[lsu.scala:201:7] wire [5:0] io_core_fp_stdata_bits_uop_prs1_0 = io_core_fp_stdata_bits_uop_prs1; // @[lsu.scala:201:7] wire [5:0] io_core_fp_stdata_bits_uop_prs2_0 = io_core_fp_stdata_bits_uop_prs2; // @[lsu.scala:201:7] wire [5:0] io_core_fp_stdata_bits_uop_prs3_0 = io_core_fp_stdata_bits_uop_prs3; // @[lsu.scala:201:7] wire [3:0] io_core_fp_stdata_bits_uop_ppred_0 = io_core_fp_stdata_bits_uop_ppred; // @[lsu.scala:201:7] wire io_core_fp_stdata_bits_uop_prs1_busy_0 = io_core_fp_stdata_bits_uop_prs1_busy; // @[lsu.scala:201:7] wire io_core_fp_stdata_bits_uop_prs2_busy_0 = io_core_fp_stdata_bits_uop_prs2_busy; // @[lsu.scala:201:7] wire io_core_fp_stdata_bits_uop_prs3_busy_0 = io_core_fp_stdata_bits_uop_prs3_busy; // @[lsu.scala:201:7] wire io_core_fp_stdata_bits_uop_ppred_busy_0 = io_core_fp_stdata_bits_uop_ppred_busy; // @[lsu.scala:201:7] wire [5:0] io_core_fp_stdata_bits_uop_stale_pdst_0 = io_core_fp_stdata_bits_uop_stale_pdst; // @[lsu.scala:201:7] wire io_core_fp_stdata_bits_uop_exception_0 = io_core_fp_stdata_bits_uop_exception; // @[lsu.scala:201:7] wire [63:0] io_core_fp_stdata_bits_uop_exc_cause_0 = io_core_fp_stdata_bits_uop_exc_cause; // @[lsu.scala:201:7] wire io_core_fp_stdata_bits_uop_bypassable_0 = io_core_fp_stdata_bits_uop_bypassable; // @[lsu.scala:201:7] wire [4:0] io_core_fp_stdata_bits_uop_mem_cmd_0 = io_core_fp_stdata_bits_uop_mem_cmd; // @[lsu.scala:201:7] wire [1:0] io_core_fp_stdata_bits_uop_mem_size_0 = io_core_fp_stdata_bits_uop_mem_size; // @[lsu.scala:201:7] wire io_core_fp_stdata_bits_uop_mem_signed_0 = io_core_fp_stdata_bits_uop_mem_signed; // @[lsu.scala:201:7] wire io_core_fp_stdata_bits_uop_is_fence_0 = io_core_fp_stdata_bits_uop_is_fence; // @[lsu.scala:201:7] wire io_core_fp_stdata_bits_uop_is_fencei_0 = io_core_fp_stdata_bits_uop_is_fencei; // @[lsu.scala:201:7] wire io_core_fp_stdata_bits_uop_is_amo_0 = io_core_fp_stdata_bits_uop_is_amo; // @[lsu.scala:201:7] wire io_core_fp_stdata_bits_uop_uses_ldq_0 = io_core_fp_stdata_bits_uop_uses_ldq; // @[lsu.scala:201:7] wire io_core_fp_stdata_bits_uop_uses_stq_0 = io_core_fp_stdata_bits_uop_uses_stq; // @[lsu.scala:201:7] wire io_core_fp_stdata_bits_uop_is_sys_pc2epc_0 = io_core_fp_stdata_bits_uop_is_sys_pc2epc; // @[lsu.scala:201:7] wire io_core_fp_stdata_bits_uop_is_unique_0 = io_core_fp_stdata_bits_uop_is_unique; // @[lsu.scala:201:7] wire io_core_fp_stdata_bits_uop_flush_on_commit_0 = io_core_fp_stdata_bits_uop_flush_on_commit; // @[lsu.scala:201:7] wire io_core_fp_stdata_bits_uop_ldst_is_rs1_0 = io_core_fp_stdata_bits_uop_ldst_is_rs1; // @[lsu.scala:201:7] wire [5:0] io_core_fp_stdata_bits_uop_ldst_0 = io_core_fp_stdata_bits_uop_ldst; // @[lsu.scala:201:7] wire [5:0] io_core_fp_stdata_bits_uop_lrs1_0 = io_core_fp_stdata_bits_uop_lrs1; // @[lsu.scala:201:7] wire [5:0] io_core_fp_stdata_bits_uop_lrs2_0 = io_core_fp_stdata_bits_uop_lrs2; // @[lsu.scala:201:7] wire [5:0] io_core_fp_stdata_bits_uop_lrs3_0 = io_core_fp_stdata_bits_uop_lrs3; // @[lsu.scala:201:7] wire io_core_fp_stdata_bits_uop_ldst_val_0 = io_core_fp_stdata_bits_uop_ldst_val; // @[lsu.scala:201:7] wire [1:0] io_core_fp_stdata_bits_uop_dst_rtype_0 = io_core_fp_stdata_bits_uop_dst_rtype; // @[lsu.scala:201:7] wire [1:0] io_core_fp_stdata_bits_uop_lrs1_rtype_0 = io_core_fp_stdata_bits_uop_lrs1_rtype; // @[lsu.scala:201:7] wire [1:0] io_core_fp_stdata_bits_uop_lrs2_rtype_0 = io_core_fp_stdata_bits_uop_lrs2_rtype; // @[lsu.scala:201:7] wire io_core_fp_stdata_bits_uop_frs3_en_0 = io_core_fp_stdata_bits_uop_frs3_en; // @[lsu.scala:201:7] wire io_core_fp_stdata_bits_uop_fp_val_0 = io_core_fp_stdata_bits_uop_fp_val; // @[lsu.scala:201:7] wire io_core_fp_stdata_bits_uop_fp_single_0 = io_core_fp_stdata_bits_uop_fp_single; // @[lsu.scala:201:7] wire io_core_fp_stdata_bits_uop_xcpt_pf_if_0 = io_core_fp_stdata_bits_uop_xcpt_pf_if; // @[lsu.scala:201:7] wire io_core_fp_stdata_bits_uop_xcpt_ae_if_0 = io_core_fp_stdata_bits_uop_xcpt_ae_if; // @[lsu.scala:201:7] wire io_core_fp_stdata_bits_uop_xcpt_ma_if_0 = io_core_fp_stdata_bits_uop_xcpt_ma_if; // @[lsu.scala:201:7] wire io_core_fp_stdata_bits_uop_bp_debug_if_0 = io_core_fp_stdata_bits_uop_bp_debug_if; // @[lsu.scala:201:7] wire io_core_fp_stdata_bits_uop_bp_xcpt_if_0 = io_core_fp_stdata_bits_uop_bp_xcpt_if; // @[lsu.scala:201:7] wire [1:0] io_core_fp_stdata_bits_uop_debug_fsrc_0 = io_core_fp_stdata_bits_uop_debug_fsrc; // @[lsu.scala:201:7] wire [1:0] io_core_fp_stdata_bits_uop_debug_tsrc_0 = io_core_fp_stdata_bits_uop_debug_tsrc; // @[lsu.scala:201:7] wire [63:0] io_core_fp_stdata_bits_data_0 = io_core_fp_stdata_bits_data; // @[lsu.scala:201:7] wire io_core_fp_stdata_bits_predicated_0 = io_core_fp_stdata_bits_predicated; // @[lsu.scala:201:7] wire io_core_fp_stdata_bits_fflags_valid_0 = io_core_fp_stdata_bits_fflags_valid; // @[lsu.scala:201:7] wire [6:0] io_core_fp_stdata_bits_fflags_bits_uop_uopc_0 = io_core_fp_stdata_bits_fflags_bits_uop_uopc; // @[lsu.scala:201:7] wire [31:0] io_core_fp_stdata_bits_fflags_bits_uop_inst_0 = io_core_fp_stdata_bits_fflags_bits_uop_inst; // @[lsu.scala:201:7] wire [31:0] io_core_fp_stdata_bits_fflags_bits_uop_debug_inst_0 = io_core_fp_stdata_bits_fflags_bits_uop_debug_inst; // @[lsu.scala:201:7] wire io_core_fp_stdata_bits_fflags_bits_uop_is_rvc_0 = io_core_fp_stdata_bits_fflags_bits_uop_is_rvc; // @[lsu.scala:201:7] wire [39:0] io_core_fp_stdata_bits_fflags_bits_uop_debug_pc_0 = io_core_fp_stdata_bits_fflags_bits_uop_debug_pc; // @[lsu.scala:201:7] wire [2:0] io_core_fp_stdata_bits_fflags_bits_uop_iq_type_0 = io_core_fp_stdata_bits_fflags_bits_uop_iq_type; // @[lsu.scala:201:7] wire [9:0] io_core_fp_stdata_bits_fflags_bits_uop_fu_code_0 = io_core_fp_stdata_bits_fflags_bits_uop_fu_code; // @[lsu.scala:201:7] wire [3:0] io_core_fp_stdata_bits_fflags_bits_uop_ctrl_br_type_0 = io_core_fp_stdata_bits_fflags_bits_uop_ctrl_br_type; // @[lsu.scala:201:7] wire [1:0] io_core_fp_stdata_bits_fflags_bits_uop_ctrl_op1_sel_0 = io_core_fp_stdata_bits_fflags_bits_uop_ctrl_op1_sel; // @[lsu.scala:201:7] wire [2:0] io_core_fp_stdata_bits_fflags_bits_uop_ctrl_op2_sel_0 = io_core_fp_stdata_bits_fflags_bits_uop_ctrl_op2_sel; // @[lsu.scala:201:7] wire [2:0] io_core_fp_stdata_bits_fflags_bits_uop_ctrl_imm_sel_0 = io_core_fp_stdata_bits_fflags_bits_uop_ctrl_imm_sel; // @[lsu.scala:201:7] wire [4:0] io_core_fp_stdata_bits_fflags_bits_uop_ctrl_op_fcn_0 = io_core_fp_stdata_bits_fflags_bits_uop_ctrl_op_fcn; // @[lsu.scala:201:7] wire io_core_fp_stdata_bits_fflags_bits_uop_ctrl_fcn_dw_0 = io_core_fp_stdata_bits_fflags_bits_uop_ctrl_fcn_dw; // @[lsu.scala:201:7] wire [2:0] io_core_fp_stdata_bits_fflags_bits_uop_ctrl_csr_cmd_0 = io_core_fp_stdata_bits_fflags_bits_uop_ctrl_csr_cmd; // @[lsu.scala:201:7] wire io_core_fp_stdata_bits_fflags_bits_uop_ctrl_is_load_0 = io_core_fp_stdata_bits_fflags_bits_uop_ctrl_is_load; // @[lsu.scala:201:7] wire io_core_fp_stdata_bits_fflags_bits_uop_ctrl_is_sta_0 = io_core_fp_stdata_bits_fflags_bits_uop_ctrl_is_sta; // @[lsu.scala:201:7] wire io_core_fp_stdata_bits_fflags_bits_uop_ctrl_is_std_0 = io_core_fp_stdata_bits_fflags_bits_uop_ctrl_is_std; // @[lsu.scala:201:7] wire [1:0] io_core_fp_stdata_bits_fflags_bits_uop_iw_state_0 = io_core_fp_stdata_bits_fflags_bits_uop_iw_state; // @[lsu.scala:201:7] wire io_core_fp_stdata_bits_fflags_bits_uop_iw_p1_poisoned_0 = io_core_fp_stdata_bits_fflags_bits_uop_iw_p1_poisoned; // @[lsu.scala:201:7] wire io_core_fp_stdata_bits_fflags_bits_uop_iw_p2_poisoned_0 = io_core_fp_stdata_bits_fflags_bits_uop_iw_p2_poisoned; // @[lsu.scala:201:7] wire io_core_fp_stdata_bits_fflags_bits_uop_is_br_0 = io_core_fp_stdata_bits_fflags_bits_uop_is_br; // @[lsu.scala:201:7] wire io_core_fp_stdata_bits_fflags_bits_uop_is_jalr_0 = io_core_fp_stdata_bits_fflags_bits_uop_is_jalr; // @[lsu.scala:201:7] wire io_core_fp_stdata_bits_fflags_bits_uop_is_jal_0 = io_core_fp_stdata_bits_fflags_bits_uop_is_jal; // @[lsu.scala:201:7] wire io_core_fp_stdata_bits_fflags_bits_uop_is_sfb_0 = io_core_fp_stdata_bits_fflags_bits_uop_is_sfb; // @[lsu.scala:201:7] wire [7:0] io_core_fp_stdata_bits_fflags_bits_uop_br_mask_0 = io_core_fp_stdata_bits_fflags_bits_uop_br_mask; // @[lsu.scala:201:7] wire [2:0] io_core_fp_stdata_bits_fflags_bits_uop_br_tag_0 = io_core_fp_stdata_bits_fflags_bits_uop_br_tag; // @[lsu.scala:201:7] wire [3:0] io_core_fp_stdata_bits_fflags_bits_uop_ftq_idx_0 = io_core_fp_stdata_bits_fflags_bits_uop_ftq_idx; // @[lsu.scala:201:7] wire io_core_fp_stdata_bits_fflags_bits_uop_edge_inst_0 = io_core_fp_stdata_bits_fflags_bits_uop_edge_inst; // @[lsu.scala:201:7] wire [5:0] io_core_fp_stdata_bits_fflags_bits_uop_pc_lob_0 = io_core_fp_stdata_bits_fflags_bits_uop_pc_lob; // @[lsu.scala:201:7] wire io_core_fp_stdata_bits_fflags_bits_uop_taken_0 = io_core_fp_stdata_bits_fflags_bits_uop_taken; // @[lsu.scala:201:7] wire [19:0] io_core_fp_stdata_bits_fflags_bits_uop_imm_packed_0 = io_core_fp_stdata_bits_fflags_bits_uop_imm_packed; // @[lsu.scala:201:7] wire [11:0] io_core_fp_stdata_bits_fflags_bits_uop_csr_addr_0 = io_core_fp_stdata_bits_fflags_bits_uop_csr_addr; // @[lsu.scala:201:7] wire [4:0] io_core_fp_stdata_bits_fflags_bits_uop_rob_idx_0 = io_core_fp_stdata_bits_fflags_bits_uop_rob_idx; // @[lsu.scala:201:7] wire [2:0] io_core_fp_stdata_bits_fflags_bits_uop_ldq_idx_0 = io_core_fp_stdata_bits_fflags_bits_uop_ldq_idx; // @[lsu.scala:201:7] wire [2:0] io_core_fp_stdata_bits_fflags_bits_uop_stq_idx_0 = io_core_fp_stdata_bits_fflags_bits_uop_stq_idx; // @[lsu.scala:201:7] wire [1:0] io_core_fp_stdata_bits_fflags_bits_uop_rxq_idx_0 = io_core_fp_stdata_bits_fflags_bits_uop_rxq_idx; // @[lsu.scala:201:7] wire [5:0] io_core_fp_stdata_bits_fflags_bits_uop_pdst_0 = io_core_fp_stdata_bits_fflags_bits_uop_pdst; // @[lsu.scala:201:7] wire [5:0] io_core_fp_stdata_bits_fflags_bits_uop_prs1_0 = io_core_fp_stdata_bits_fflags_bits_uop_prs1; // @[lsu.scala:201:7] wire [5:0] io_core_fp_stdata_bits_fflags_bits_uop_prs2_0 = io_core_fp_stdata_bits_fflags_bits_uop_prs2; // @[lsu.scala:201:7] wire [5:0] io_core_fp_stdata_bits_fflags_bits_uop_prs3_0 = io_core_fp_stdata_bits_fflags_bits_uop_prs3; // @[lsu.scala:201:7] wire [3:0] io_core_fp_stdata_bits_fflags_bits_uop_ppred_0 = io_core_fp_stdata_bits_fflags_bits_uop_ppred; // @[lsu.scala:201:7] wire io_core_fp_stdata_bits_fflags_bits_uop_prs1_busy_0 = io_core_fp_stdata_bits_fflags_bits_uop_prs1_busy; // @[lsu.scala:201:7] wire io_core_fp_stdata_bits_fflags_bits_uop_prs2_busy_0 = io_core_fp_stdata_bits_fflags_bits_uop_prs2_busy; // @[lsu.scala:201:7] wire io_core_fp_stdata_bits_fflags_bits_uop_prs3_busy_0 = io_core_fp_stdata_bits_fflags_bits_uop_prs3_busy; // @[lsu.scala:201:7] wire io_core_fp_stdata_bits_fflags_bits_uop_ppred_busy_0 = io_core_fp_stdata_bits_fflags_bits_uop_ppred_busy; // @[lsu.scala:201:7] wire [5:0] io_core_fp_stdata_bits_fflags_bits_uop_stale_pdst_0 = io_core_fp_stdata_bits_fflags_bits_uop_stale_pdst; // @[lsu.scala:201:7] wire io_core_fp_stdata_bits_fflags_bits_uop_exception_0 = io_core_fp_stdata_bits_fflags_bits_uop_exception; // @[lsu.scala:201:7] wire [63:0] io_core_fp_stdata_bits_fflags_bits_uop_exc_cause_0 = io_core_fp_stdata_bits_fflags_bits_uop_exc_cause; // @[lsu.scala:201:7] wire io_core_fp_stdata_bits_fflags_bits_uop_bypassable_0 = io_core_fp_stdata_bits_fflags_bits_uop_bypassable; // @[lsu.scala:201:7] wire [4:0] io_core_fp_stdata_bits_fflags_bits_uop_mem_cmd_0 = io_core_fp_stdata_bits_fflags_bits_uop_mem_cmd; // @[lsu.scala:201:7] wire [1:0] io_core_fp_stdata_bits_fflags_bits_uop_mem_size_0 = io_core_fp_stdata_bits_fflags_bits_uop_mem_size; // @[lsu.scala:201:7] wire io_core_fp_stdata_bits_fflags_bits_uop_mem_signed_0 = io_core_fp_stdata_bits_fflags_bits_uop_mem_signed; // @[lsu.scala:201:7] wire io_core_fp_stdata_bits_fflags_bits_uop_is_fence_0 = io_core_fp_stdata_bits_fflags_bits_uop_is_fence; // @[lsu.scala:201:7] wire io_core_fp_stdata_bits_fflags_bits_uop_is_fencei_0 = io_core_fp_stdata_bits_fflags_bits_uop_is_fencei; // @[lsu.scala:201:7] wire io_core_fp_stdata_bits_fflags_bits_uop_is_amo_0 = io_core_fp_stdata_bits_fflags_bits_uop_is_amo; // @[lsu.scala:201:7] wire io_core_fp_stdata_bits_fflags_bits_uop_uses_ldq_0 = io_core_fp_stdata_bits_fflags_bits_uop_uses_ldq; // @[lsu.scala:201:7] wire io_core_fp_stdata_bits_fflags_bits_uop_uses_stq_0 = io_core_fp_stdata_bits_fflags_bits_uop_uses_stq; // @[lsu.scala:201:7] wire io_core_fp_stdata_bits_fflags_bits_uop_is_sys_pc2epc_0 = io_core_fp_stdata_bits_fflags_bits_uop_is_sys_pc2epc; // @[lsu.scala:201:7] wire io_core_fp_stdata_bits_fflags_bits_uop_is_unique_0 = io_core_fp_stdata_bits_fflags_bits_uop_is_unique; // @[lsu.scala:201:7] wire io_core_fp_stdata_bits_fflags_bits_uop_flush_on_commit_0 = io_core_fp_stdata_bits_fflags_bits_uop_flush_on_commit; // @[lsu.scala:201:7] wire io_core_fp_stdata_bits_fflags_bits_uop_ldst_is_rs1_0 = io_core_fp_stdata_bits_fflags_bits_uop_ldst_is_rs1; // @[lsu.scala:201:7] wire [5:0] io_core_fp_stdata_bits_fflags_bits_uop_ldst_0 = io_core_fp_stdata_bits_fflags_bits_uop_ldst; // @[lsu.scala:201:7] wire [5:0] io_core_fp_stdata_bits_fflags_bits_uop_lrs1_0 = io_core_fp_stdata_bits_fflags_bits_uop_lrs1; // @[lsu.scala:201:7] wire [5:0] io_core_fp_stdata_bits_fflags_bits_uop_lrs2_0 = io_core_fp_stdata_bits_fflags_bits_uop_lrs2; // @[lsu.scala:201:7] wire [5:0] io_core_fp_stdata_bits_fflags_bits_uop_lrs3_0 = io_core_fp_stdata_bits_fflags_bits_uop_lrs3; // @[lsu.scala:201:7] wire io_core_fp_stdata_bits_fflags_bits_uop_ldst_val_0 = io_core_fp_stdata_bits_fflags_bits_uop_ldst_val; // @[lsu.scala:201:7] wire [1:0] io_core_fp_stdata_bits_fflags_bits_uop_dst_rtype_0 = io_core_fp_stdata_bits_fflags_bits_uop_dst_rtype; // @[lsu.scala:201:7] wire [1:0] io_core_fp_stdata_bits_fflags_bits_uop_lrs1_rtype_0 = io_core_fp_stdata_bits_fflags_bits_uop_lrs1_rtype; // @[lsu.scala:201:7] wire [1:0] io_core_fp_stdata_bits_fflags_bits_uop_lrs2_rtype_0 = io_core_fp_stdata_bits_fflags_bits_uop_lrs2_rtype; // @[lsu.scala:201:7] wire io_core_fp_stdata_bits_fflags_bits_uop_frs3_en_0 = io_core_fp_stdata_bits_fflags_bits_uop_frs3_en; // @[lsu.scala:201:7] wire io_core_fp_stdata_bits_fflags_bits_uop_fp_val_0 = io_core_fp_stdata_bits_fflags_bits_uop_fp_val; // @[lsu.scala:201:7] wire io_core_fp_stdata_bits_fflags_bits_uop_fp_single_0 = io_core_fp_stdata_bits_fflags_bits_uop_fp_single; // @[lsu.scala:201:7] wire io_core_fp_stdata_bits_fflags_bits_uop_xcpt_pf_if_0 = io_core_fp_stdata_bits_fflags_bits_uop_xcpt_pf_if; // @[lsu.scala:201:7] wire io_core_fp_stdata_bits_fflags_bits_uop_xcpt_ae_if_0 = io_core_fp_stdata_bits_fflags_bits_uop_xcpt_ae_if; // @[lsu.scala:201:7] wire io_core_fp_stdata_bits_fflags_bits_uop_xcpt_ma_if_0 = io_core_fp_stdata_bits_fflags_bits_uop_xcpt_ma_if; // @[lsu.scala:201:7] wire io_core_fp_stdata_bits_fflags_bits_uop_bp_debug_if_0 = io_core_fp_stdata_bits_fflags_bits_uop_bp_debug_if; // @[lsu.scala:201:7] wire io_core_fp_stdata_bits_fflags_bits_uop_bp_xcpt_if_0 = io_core_fp_stdata_bits_fflags_bits_uop_bp_xcpt_if; // @[lsu.scala:201:7] wire [1:0] io_core_fp_stdata_bits_fflags_bits_uop_debug_fsrc_0 = io_core_fp_stdata_bits_fflags_bits_uop_debug_fsrc; // @[lsu.scala:201:7] wire [1:0] io_core_fp_stdata_bits_fflags_bits_uop_debug_tsrc_0 = io_core_fp_stdata_bits_fflags_bits_uop_debug_tsrc; // @[lsu.scala:201:7] wire [4:0] io_core_fp_stdata_bits_fflags_bits_flags_0 = io_core_fp_stdata_bits_fflags_bits_flags; // @[lsu.scala:201:7] wire io_core_commit_valids_0_0 = io_core_commit_valids_0; // @[lsu.scala:201:7] wire io_core_commit_arch_valids_0_0 = io_core_commit_arch_valids_0; // @[lsu.scala:201:7] wire [6:0] io_core_commit_uops_0_uopc_0 = io_core_commit_uops_0_uopc; // @[lsu.scala:201:7] wire [31:0] io_core_commit_uops_0_inst_0 = io_core_commit_uops_0_inst; // @[lsu.scala:201:7] wire [31:0] io_core_commit_uops_0_debug_inst_0 = io_core_commit_uops_0_debug_inst; // @[lsu.scala:201:7] wire io_core_commit_uops_0_is_rvc_0 = io_core_commit_uops_0_is_rvc; // @[lsu.scala:201:7] wire [39:0] io_core_commit_uops_0_debug_pc_0 = io_core_commit_uops_0_debug_pc; // @[lsu.scala:201:7] wire [2:0] io_core_commit_uops_0_iq_type_0 = io_core_commit_uops_0_iq_type; // @[lsu.scala:201:7] wire [9:0] io_core_commit_uops_0_fu_code_0 = io_core_commit_uops_0_fu_code; // @[lsu.scala:201:7] wire [3:0] io_core_commit_uops_0_ctrl_br_type_0 = io_core_commit_uops_0_ctrl_br_type; // @[lsu.scala:201:7] wire [1:0] io_core_commit_uops_0_ctrl_op1_sel_0 = io_core_commit_uops_0_ctrl_op1_sel; // @[lsu.scala:201:7] wire [2:0] io_core_commit_uops_0_ctrl_op2_sel_0 = io_core_commit_uops_0_ctrl_op2_sel; // @[lsu.scala:201:7] wire [2:0] io_core_commit_uops_0_ctrl_imm_sel_0 = io_core_commit_uops_0_ctrl_imm_sel; // @[lsu.scala:201:7] wire [4:0] io_core_commit_uops_0_ctrl_op_fcn_0 = io_core_commit_uops_0_ctrl_op_fcn; // @[lsu.scala:201:7] wire io_core_commit_uops_0_ctrl_fcn_dw_0 = io_core_commit_uops_0_ctrl_fcn_dw; // @[lsu.scala:201:7] wire [2:0] io_core_commit_uops_0_ctrl_csr_cmd_0 = io_core_commit_uops_0_ctrl_csr_cmd; // @[lsu.scala:201:7] wire io_core_commit_uops_0_ctrl_is_load_0 = io_core_commit_uops_0_ctrl_is_load; // @[lsu.scala:201:7] wire io_core_commit_uops_0_ctrl_is_sta_0 = io_core_commit_uops_0_ctrl_is_sta; // @[lsu.scala:201:7] wire io_core_commit_uops_0_ctrl_is_std_0 = io_core_commit_uops_0_ctrl_is_std; // @[lsu.scala:201:7] wire [1:0] io_core_commit_uops_0_iw_state_0 = io_core_commit_uops_0_iw_state; // @[lsu.scala:201:7] wire io_core_commit_uops_0_iw_p1_poisoned_0 = io_core_commit_uops_0_iw_p1_poisoned; // @[lsu.scala:201:7] wire io_core_commit_uops_0_iw_p2_poisoned_0 = io_core_commit_uops_0_iw_p2_poisoned; // @[lsu.scala:201:7] wire io_core_commit_uops_0_is_br_0 = io_core_commit_uops_0_is_br; // @[lsu.scala:201:7] wire io_core_commit_uops_0_is_jalr_0 = io_core_commit_uops_0_is_jalr; // @[lsu.scala:201:7] wire io_core_commit_uops_0_is_jal_0 = io_core_commit_uops_0_is_jal; // @[lsu.scala:201:7] wire io_core_commit_uops_0_is_sfb_0 = io_core_commit_uops_0_is_sfb; // @[lsu.scala:201:7] wire [7:0] io_core_commit_uops_0_br_mask_0 = io_core_commit_uops_0_br_mask; // @[lsu.scala:201:7] wire [2:0] io_core_commit_uops_0_br_tag_0 = io_core_commit_uops_0_br_tag; // @[lsu.scala:201:7] wire [3:0] io_core_commit_uops_0_ftq_idx_0 = io_core_commit_uops_0_ftq_idx; // @[lsu.scala:201:7] wire io_core_commit_uops_0_edge_inst_0 = io_core_commit_uops_0_edge_inst; // @[lsu.scala:201:7] wire [5:0] io_core_commit_uops_0_pc_lob_0 = io_core_commit_uops_0_pc_lob; // @[lsu.scala:201:7] wire io_core_commit_uops_0_taken_0 = io_core_commit_uops_0_taken; // @[lsu.scala:201:7] wire [19:0] io_core_commit_uops_0_imm_packed_0 = io_core_commit_uops_0_imm_packed; // @[lsu.scala:201:7] wire [11:0] io_core_commit_uops_0_csr_addr_0 = io_core_commit_uops_0_csr_addr; // @[lsu.scala:201:7] wire [4:0] io_core_commit_uops_0_rob_idx_0 = io_core_commit_uops_0_rob_idx; // @[lsu.scala:201:7] wire [2:0] io_core_commit_uops_0_ldq_idx_0 = io_core_commit_uops_0_ldq_idx; // @[lsu.scala:201:7] wire [2:0] io_core_commit_uops_0_stq_idx_0 = io_core_commit_uops_0_stq_idx; // @[lsu.scala:201:7] wire [1:0] io_core_commit_uops_0_rxq_idx_0 = io_core_commit_uops_0_rxq_idx; // @[lsu.scala:201:7] wire [5:0] io_core_commit_uops_0_pdst_0 = io_core_commit_uops_0_pdst; // @[lsu.scala:201:7] wire [5:0] io_core_commit_uops_0_prs1_0 = io_core_commit_uops_0_prs1; // @[lsu.scala:201:7] wire [5:0] io_core_commit_uops_0_prs2_0 = io_core_commit_uops_0_prs2; // @[lsu.scala:201:7] wire [5:0] io_core_commit_uops_0_prs3_0 = io_core_commit_uops_0_prs3; // @[lsu.scala:201:7] wire [3:0] io_core_commit_uops_0_ppred_0 = io_core_commit_uops_0_ppred; // @[lsu.scala:201:7] wire io_core_commit_uops_0_prs1_busy_0 = io_core_commit_uops_0_prs1_busy; // @[lsu.scala:201:7] wire io_core_commit_uops_0_prs2_busy_0 = io_core_commit_uops_0_prs2_busy; // @[lsu.scala:201:7] wire io_core_commit_uops_0_prs3_busy_0 = io_core_commit_uops_0_prs3_busy; // @[lsu.scala:201:7] wire io_core_commit_uops_0_ppred_busy_0 = io_core_commit_uops_0_ppred_busy; // @[lsu.scala:201:7] wire [5:0] io_core_commit_uops_0_stale_pdst_0 = io_core_commit_uops_0_stale_pdst; // @[lsu.scala:201:7] wire io_core_commit_uops_0_exception_0 = io_core_commit_uops_0_exception; // @[lsu.scala:201:7] wire [63:0] io_core_commit_uops_0_exc_cause_0 = io_core_commit_uops_0_exc_cause; // @[lsu.scala:201:7] wire io_core_commit_uops_0_bypassable_0 = io_core_commit_uops_0_bypassable; // @[lsu.scala:201:7] wire [4:0] io_core_commit_uops_0_mem_cmd_0 = io_core_commit_uops_0_mem_cmd; // @[lsu.scala:201:7] wire [1:0] io_core_commit_uops_0_mem_size_0 = io_core_commit_uops_0_mem_size; // @[lsu.scala:201:7] wire io_core_commit_uops_0_mem_signed_0 = io_core_commit_uops_0_mem_signed; // @[lsu.scala:201:7] wire io_core_commit_uops_0_is_fence_0 = io_core_commit_uops_0_is_fence; // @[lsu.scala:201:7] wire io_core_commit_uops_0_is_fencei_0 = io_core_commit_uops_0_is_fencei; // @[lsu.scala:201:7] wire io_core_commit_uops_0_is_amo_0 = io_core_commit_uops_0_is_amo; // @[lsu.scala:201:7] wire io_core_commit_uops_0_uses_ldq_0 = io_core_commit_uops_0_uses_ldq; // @[lsu.scala:201:7] wire io_core_commit_uops_0_uses_stq_0 = io_core_commit_uops_0_uses_stq; // @[lsu.scala:201:7] wire io_core_commit_uops_0_is_sys_pc2epc_0 = io_core_commit_uops_0_is_sys_pc2epc; // @[lsu.scala:201:7] wire io_core_commit_uops_0_is_unique_0 = io_core_commit_uops_0_is_unique; // @[lsu.scala:201:7] wire io_core_commit_uops_0_flush_on_commit_0 = io_core_commit_uops_0_flush_on_commit; // @[lsu.scala:201:7] wire io_core_commit_uops_0_ldst_is_rs1_0 = io_core_commit_uops_0_ldst_is_rs1; // @[lsu.scala:201:7] wire [5:0] io_core_commit_uops_0_ldst_0 = io_core_commit_uops_0_ldst; // @[lsu.scala:201:7] wire [5:0] io_core_commit_uops_0_lrs1_0 = io_core_commit_uops_0_lrs1; // @[lsu.scala:201:7] wire [5:0] io_core_commit_uops_0_lrs2_0 = io_core_commit_uops_0_lrs2; // @[lsu.scala:201:7] wire [5:0] io_core_commit_uops_0_lrs3_0 = io_core_commit_uops_0_lrs3; // @[lsu.scala:201:7] wire io_core_commit_uops_0_ldst_val_0 = io_core_commit_uops_0_ldst_val; // @[lsu.scala:201:7] wire [1:0] io_core_commit_uops_0_dst_rtype_0 = io_core_commit_uops_0_dst_rtype; // @[lsu.scala:201:7] wire [1:0] io_core_commit_uops_0_lrs1_rtype_0 = io_core_commit_uops_0_lrs1_rtype; // @[lsu.scala:201:7] wire [1:0] io_core_commit_uops_0_lrs2_rtype_0 = io_core_commit_uops_0_lrs2_rtype; // @[lsu.scala:201:7] wire io_core_commit_uops_0_frs3_en_0 = io_core_commit_uops_0_frs3_en; // @[lsu.scala:201:7] wire io_core_commit_uops_0_fp_val_0 = io_core_commit_uops_0_fp_val; // @[lsu.scala:201:7] wire io_core_commit_uops_0_fp_single_0 = io_core_commit_uops_0_fp_single; // @[lsu.scala:201:7] wire io_core_commit_uops_0_xcpt_pf_if_0 = io_core_commit_uops_0_xcpt_pf_if; // @[lsu.scala:201:7] wire io_core_commit_uops_0_xcpt_ae_if_0 = io_core_commit_uops_0_xcpt_ae_if; // @[lsu.scala:201:7] wire io_core_commit_uops_0_xcpt_ma_if_0 = io_core_commit_uops_0_xcpt_ma_if; // @[lsu.scala:201:7] wire io_core_commit_uops_0_bp_debug_if_0 = io_core_commit_uops_0_bp_debug_if; // @[lsu.scala:201:7] wire io_core_commit_uops_0_bp_xcpt_if_0 = io_core_commit_uops_0_bp_xcpt_if; // @[lsu.scala:201:7] wire [1:0] io_core_commit_uops_0_debug_fsrc_0 = io_core_commit_uops_0_debug_fsrc; // @[lsu.scala:201:7] wire [1:0] io_core_commit_uops_0_debug_tsrc_0 = io_core_commit_uops_0_debug_tsrc; // @[lsu.scala:201:7] wire io_core_commit_fflags_valid_0 = io_core_commit_fflags_valid; // @[lsu.scala:201:7] wire [4:0] io_core_commit_fflags_bits_0 = io_core_commit_fflags_bits; // @[lsu.scala:201:7] wire [31:0] io_core_commit_debug_insts_0_0 = io_core_commit_debug_insts_0; // @[lsu.scala:201:7] wire io_core_commit_rbk_valids_0_0 = io_core_commit_rbk_valids_0; // @[lsu.scala:201:7] wire io_core_commit_rollback_0 = io_core_commit_rollback; // @[lsu.scala:201:7] wire [63:0] io_core_commit_debug_wdata_0_0 = io_core_commit_debug_wdata_0; // @[lsu.scala:201:7] wire io_core_commit_load_at_rob_head_0 = io_core_commit_load_at_rob_head; // @[lsu.scala:201:7] wire io_core_fence_dmem_0 = io_core_fence_dmem; // @[lsu.scala:201:7] wire [7:0] io_core_brupdate_b1_resolve_mask_0 = io_core_brupdate_b1_resolve_mask; // @[lsu.scala:201:7] wire [7:0] io_core_brupdate_b1_mispredict_mask_0 = io_core_brupdate_b1_mispredict_mask; // @[lsu.scala:201:7] wire [6:0] io_core_brupdate_b2_uop_uopc_0 = io_core_brupdate_b2_uop_uopc; // @[lsu.scala:201:7] wire [31:0] io_core_brupdate_b2_uop_inst_0 = io_core_brupdate_b2_uop_inst; // @[lsu.scala:201:7] wire [31:0] io_core_brupdate_b2_uop_debug_inst_0 = io_core_brupdate_b2_uop_debug_inst; // @[lsu.scala:201:7] wire io_core_brupdate_b2_uop_is_rvc_0 = io_core_brupdate_b2_uop_is_rvc; // @[lsu.scala:201:7] wire [39:0] io_core_brupdate_b2_uop_debug_pc_0 = io_core_brupdate_b2_uop_debug_pc; // @[lsu.scala:201:7] wire [2:0] io_core_brupdate_b2_uop_iq_type_0 = io_core_brupdate_b2_uop_iq_type; // @[lsu.scala:201:7] wire [9:0] io_core_brupdate_b2_uop_fu_code_0 = io_core_brupdate_b2_uop_fu_code; // @[lsu.scala:201:7] wire [3:0] io_core_brupdate_b2_uop_ctrl_br_type_0 = io_core_brupdate_b2_uop_ctrl_br_type; // @[lsu.scala:201:7] wire [1:0] io_core_brupdate_b2_uop_ctrl_op1_sel_0 = io_core_brupdate_b2_uop_ctrl_op1_sel; // @[lsu.scala:201:7] wire [2:0] io_core_brupdate_b2_uop_ctrl_op2_sel_0 = io_core_brupdate_b2_uop_ctrl_op2_sel; // @[lsu.scala:201:7] wire [2:0] io_core_brupdate_b2_uop_ctrl_imm_sel_0 = io_core_brupdate_b2_uop_ctrl_imm_sel; // @[lsu.scala:201:7] wire [4:0] io_core_brupdate_b2_uop_ctrl_op_fcn_0 = io_core_brupdate_b2_uop_ctrl_op_fcn; // @[lsu.scala:201:7] wire io_core_brupdate_b2_uop_ctrl_fcn_dw_0 = io_core_brupdate_b2_uop_ctrl_fcn_dw; // @[lsu.scala:201:7] wire [2:0] io_core_brupdate_b2_uop_ctrl_csr_cmd_0 = io_core_brupdate_b2_uop_ctrl_csr_cmd; // @[lsu.scala:201:7] wire io_core_brupdate_b2_uop_ctrl_is_load_0 = io_core_brupdate_b2_uop_ctrl_is_load; // @[lsu.scala:201:7] wire io_core_brupdate_b2_uop_ctrl_is_sta_0 = io_core_brupdate_b2_uop_ctrl_is_sta; // @[lsu.scala:201:7] wire io_core_brupdate_b2_uop_ctrl_is_std_0 = io_core_brupdate_b2_uop_ctrl_is_std; // @[lsu.scala:201:7] wire [1:0] io_core_brupdate_b2_uop_iw_state_0 = io_core_brupdate_b2_uop_iw_state; // @[lsu.scala:201:7] wire io_core_brupdate_b2_uop_iw_p1_poisoned_0 = io_core_brupdate_b2_uop_iw_p1_poisoned; // @[lsu.scala:201:7] wire io_core_brupdate_b2_uop_iw_p2_poisoned_0 = io_core_brupdate_b2_uop_iw_p2_poisoned; // @[lsu.scala:201:7] wire io_core_brupdate_b2_uop_is_br_0 = io_core_brupdate_b2_uop_is_br; // @[lsu.scala:201:7] wire io_core_brupdate_b2_uop_is_jalr_0 = io_core_brupdate_b2_uop_is_jalr; // @[lsu.scala:201:7] wire io_core_brupdate_b2_uop_is_jal_0 = io_core_brupdate_b2_uop_is_jal; // @[lsu.scala:201:7] wire io_core_brupdate_b2_uop_is_sfb_0 = io_core_brupdate_b2_uop_is_sfb; // @[lsu.scala:201:7] wire [7:0] io_core_brupdate_b2_uop_br_mask_0 = io_core_brupdate_b2_uop_br_mask; // @[lsu.scala:201:7] wire [2:0] io_core_brupdate_b2_uop_br_tag_0 = io_core_brupdate_b2_uop_br_tag; // @[lsu.scala:201:7] wire [3:0] io_core_brupdate_b2_uop_ftq_idx_0 = io_core_brupdate_b2_uop_ftq_idx; // @[lsu.scala:201:7] wire io_core_brupdate_b2_uop_edge_inst_0 = io_core_brupdate_b2_uop_edge_inst; // @[lsu.scala:201:7] wire [5:0] io_core_brupdate_b2_uop_pc_lob_0 = io_core_brupdate_b2_uop_pc_lob; // @[lsu.scala:201:7] wire io_core_brupdate_b2_uop_taken_0 = io_core_brupdate_b2_uop_taken; // @[lsu.scala:201:7] wire [19:0] io_core_brupdate_b2_uop_imm_packed_0 = io_core_brupdate_b2_uop_imm_packed; // @[lsu.scala:201:7] wire [11:0] io_core_brupdate_b2_uop_csr_addr_0 = io_core_brupdate_b2_uop_csr_addr; // @[lsu.scala:201:7] wire [4:0] io_core_brupdate_b2_uop_rob_idx_0 = io_core_brupdate_b2_uop_rob_idx; // @[lsu.scala:201:7] wire [2:0] io_core_brupdate_b2_uop_ldq_idx_0 = io_core_brupdate_b2_uop_ldq_idx; // @[lsu.scala:201:7] wire [2:0] io_core_brupdate_b2_uop_stq_idx_0 = io_core_brupdate_b2_uop_stq_idx; // @[lsu.scala:201:7] wire [1:0] io_core_brupdate_b2_uop_rxq_idx_0 = io_core_brupdate_b2_uop_rxq_idx; // @[lsu.scala:201:7] wire [5:0] io_core_brupdate_b2_uop_pdst_0 = io_core_brupdate_b2_uop_pdst; // @[lsu.scala:201:7] wire [5:0] io_core_brupdate_b2_uop_prs1_0 = io_core_brupdate_b2_uop_prs1; // @[lsu.scala:201:7] wire [5:0] io_core_brupdate_b2_uop_prs2_0 = io_core_brupdate_b2_uop_prs2; // @[lsu.scala:201:7] wire [5:0] io_core_brupdate_b2_uop_prs3_0 = io_core_brupdate_b2_uop_prs3; // @[lsu.scala:201:7] wire [3:0] io_core_brupdate_b2_uop_ppred_0 = io_core_brupdate_b2_uop_ppred; // @[lsu.scala:201:7] wire io_core_brupdate_b2_uop_prs1_busy_0 = io_core_brupdate_b2_uop_prs1_busy; // @[lsu.scala:201:7] wire io_core_brupdate_b2_uop_prs2_busy_0 = io_core_brupdate_b2_uop_prs2_busy; // @[lsu.scala:201:7] wire io_core_brupdate_b2_uop_prs3_busy_0 = io_core_brupdate_b2_uop_prs3_busy; // @[lsu.scala:201:7] wire io_core_brupdate_b2_uop_ppred_busy_0 = io_core_brupdate_b2_uop_ppred_busy; // @[lsu.scala:201:7] wire [5:0] io_core_brupdate_b2_uop_stale_pdst_0 = io_core_brupdate_b2_uop_stale_pdst; // @[lsu.scala:201:7] wire io_core_brupdate_b2_uop_exception_0 = io_core_brupdate_b2_uop_exception; // @[lsu.scala:201:7] wire [63:0] io_core_brupdate_b2_uop_exc_cause_0 = io_core_brupdate_b2_uop_exc_cause; // @[lsu.scala:201:7] wire io_core_brupdate_b2_uop_bypassable_0 = io_core_brupdate_b2_uop_bypassable; // @[lsu.scala:201:7] wire [4:0] io_core_brupdate_b2_uop_mem_cmd_0 = io_core_brupdate_b2_uop_mem_cmd; // @[lsu.scala:201:7] wire [1:0] io_core_brupdate_b2_uop_mem_size_0 = io_core_brupdate_b2_uop_mem_size; // @[lsu.scala:201:7] wire io_core_brupdate_b2_uop_mem_signed_0 = io_core_brupdate_b2_uop_mem_signed; // @[lsu.scala:201:7] wire io_core_brupdate_b2_uop_is_fence_0 = io_core_brupdate_b2_uop_is_fence; // @[lsu.scala:201:7] wire io_core_brupdate_b2_uop_is_fencei_0 = io_core_brupdate_b2_uop_is_fencei; // @[lsu.scala:201:7] wire io_core_brupdate_b2_uop_is_amo_0 = io_core_brupdate_b2_uop_is_amo; // @[lsu.scala:201:7] wire io_core_brupdate_b2_uop_uses_ldq_0 = io_core_brupdate_b2_uop_uses_ldq; // @[lsu.scala:201:7] wire io_core_brupdate_b2_uop_uses_stq_0 = io_core_brupdate_b2_uop_uses_stq; // @[lsu.scala:201:7] wire io_core_brupdate_b2_uop_is_sys_pc2epc_0 = io_core_brupdate_b2_uop_is_sys_pc2epc; // @[lsu.scala:201:7] wire io_core_brupdate_b2_uop_is_unique_0 = io_core_brupdate_b2_uop_is_unique; // @[lsu.scala:201:7] wire io_core_brupdate_b2_uop_flush_on_commit_0 = io_core_brupdate_b2_uop_flush_on_commit; // @[lsu.scala:201:7] wire io_core_brupdate_b2_uop_ldst_is_rs1_0 = io_core_brupdate_b2_uop_ldst_is_rs1; // @[lsu.scala:201:7] wire [5:0] io_core_brupdate_b2_uop_ldst_0 = io_core_brupdate_b2_uop_ldst; // @[lsu.scala:201:7] wire [5:0] io_core_brupdate_b2_uop_lrs1_0 = io_core_brupdate_b2_uop_lrs1; // @[lsu.scala:201:7] wire [5:0] io_core_brupdate_b2_uop_lrs2_0 = io_core_brupdate_b2_uop_lrs2; // @[lsu.scala:201:7] wire [5:0] io_core_brupdate_b2_uop_lrs3_0 = io_core_brupdate_b2_uop_lrs3; // @[lsu.scala:201:7] wire io_core_brupdate_b2_uop_ldst_val_0 = io_core_brupdate_b2_uop_ldst_val; // @[lsu.scala:201:7] wire [1:0] io_core_brupdate_b2_uop_dst_rtype_0 = io_core_brupdate_b2_uop_dst_rtype; // @[lsu.scala:201:7] wire [1:0] io_core_brupdate_b2_uop_lrs1_rtype_0 = io_core_brupdate_b2_uop_lrs1_rtype; // @[lsu.scala:201:7] wire [1:0] io_core_brupdate_b2_uop_lrs2_rtype_0 = io_core_brupdate_b2_uop_lrs2_rtype; // @[lsu.scala:201:7] wire io_core_brupdate_b2_uop_frs3_en_0 = io_core_brupdate_b2_uop_frs3_en; // @[lsu.scala:201:7] wire io_core_brupdate_b2_uop_fp_val_0 = io_core_brupdate_b2_uop_fp_val; // @[lsu.scala:201:7] wire io_core_brupdate_b2_uop_fp_single_0 = io_core_brupdate_b2_uop_fp_single; // @[lsu.scala:201:7] wire io_core_brupdate_b2_uop_xcpt_pf_if_0 = io_core_brupdate_b2_uop_xcpt_pf_if; // @[lsu.scala:201:7] wire io_core_brupdate_b2_uop_xcpt_ae_if_0 = io_core_brupdate_b2_uop_xcpt_ae_if; // @[lsu.scala:201:7] wire io_core_brupdate_b2_uop_xcpt_ma_if_0 = io_core_brupdate_b2_uop_xcpt_ma_if; // @[lsu.scala:201:7] wire io_core_brupdate_b2_uop_bp_debug_if_0 = io_core_brupdate_b2_uop_bp_debug_if; // @[lsu.scala:201:7] wire io_core_brupdate_b2_uop_bp_xcpt_if_0 = io_core_brupdate_b2_uop_bp_xcpt_if; // @[lsu.scala:201:7] wire [1:0] io_core_brupdate_b2_uop_debug_fsrc_0 = io_core_brupdate_b2_uop_debug_fsrc; // @[lsu.scala:201:7] wire [1:0] io_core_brupdate_b2_uop_debug_tsrc_0 = io_core_brupdate_b2_uop_debug_tsrc; // @[lsu.scala:201:7] wire io_core_brupdate_b2_valid_0 = io_core_brupdate_b2_valid; // @[lsu.scala:201:7] wire io_core_brupdate_b2_mispredict_0 = io_core_brupdate_b2_mispredict; // @[lsu.scala:201:7] wire io_core_brupdate_b2_taken_0 = io_core_brupdate_b2_taken; // @[lsu.scala:201:7] wire [2:0] io_core_brupdate_b2_cfi_type_0 = io_core_brupdate_b2_cfi_type; // @[lsu.scala:201:7] wire [1:0] io_core_brupdate_b2_pc_sel_0 = io_core_brupdate_b2_pc_sel; // @[lsu.scala:201:7] wire [39:0] io_core_brupdate_b2_jalr_target_0 = io_core_brupdate_b2_jalr_target; // @[lsu.scala:201:7] wire [20:0] io_core_brupdate_b2_target_offset_0 = io_core_brupdate_b2_target_offset; // @[lsu.scala:201:7] wire [4:0] io_core_rob_pnr_idx_0 = io_core_rob_pnr_idx; // @[lsu.scala:201:7] wire [4:0] io_core_rob_head_idx_0 = io_core_rob_head_idx; // @[lsu.scala:201:7] wire io_core_exception_0 = io_core_exception; // @[lsu.scala:201:7] wire [63:0] io_core_tsc_reg_0 = io_core_tsc_reg; // @[lsu.scala:201:7] wire io_dmem_req_ready_0 = io_dmem_req_ready; // @[lsu.scala:201:7] wire io_dmem_resp_0_valid_0 = io_dmem_resp_0_valid; // @[lsu.scala:201:7] wire [6:0] io_dmem_resp_0_bits_uop_uopc_0 = io_dmem_resp_0_bits_uop_uopc; // @[lsu.scala:201:7] wire [31:0] io_dmem_resp_0_bits_uop_inst_0 = io_dmem_resp_0_bits_uop_inst; // @[lsu.scala:201:7] wire [31:0] io_dmem_resp_0_bits_uop_debug_inst_0 = io_dmem_resp_0_bits_uop_debug_inst; // @[lsu.scala:201:7] wire io_dmem_resp_0_bits_uop_is_rvc_0 = io_dmem_resp_0_bits_uop_is_rvc; // @[lsu.scala:201:7] wire [39:0] io_dmem_resp_0_bits_uop_debug_pc_0 = io_dmem_resp_0_bits_uop_debug_pc; // @[lsu.scala:201:7] wire [2:0] io_dmem_resp_0_bits_uop_iq_type_0 = io_dmem_resp_0_bits_uop_iq_type; // @[lsu.scala:201:7] wire [9:0] io_dmem_resp_0_bits_uop_fu_code_0 = io_dmem_resp_0_bits_uop_fu_code; // @[lsu.scala:201:7] wire [3:0] io_dmem_resp_0_bits_uop_ctrl_br_type_0 = io_dmem_resp_0_bits_uop_ctrl_br_type; // @[lsu.scala:201:7] wire [1:0] io_dmem_resp_0_bits_uop_ctrl_op1_sel_0 = io_dmem_resp_0_bits_uop_ctrl_op1_sel; // @[lsu.scala:201:7] wire [2:0] io_dmem_resp_0_bits_uop_ctrl_op2_sel_0 = io_dmem_resp_0_bits_uop_ctrl_op2_sel; // @[lsu.scala:201:7] wire [2:0] io_dmem_resp_0_bits_uop_ctrl_imm_sel_0 = io_dmem_resp_0_bits_uop_ctrl_imm_sel; // @[lsu.scala:201:7] wire [4:0] io_dmem_resp_0_bits_uop_ctrl_op_fcn_0 = io_dmem_resp_0_bits_uop_ctrl_op_fcn; // @[lsu.scala:201:7] wire io_dmem_resp_0_bits_uop_ctrl_fcn_dw_0 = io_dmem_resp_0_bits_uop_ctrl_fcn_dw; // @[lsu.scala:201:7] wire [2:0] io_dmem_resp_0_bits_uop_ctrl_csr_cmd_0 = io_dmem_resp_0_bits_uop_ctrl_csr_cmd; // @[lsu.scala:201:7] wire io_dmem_resp_0_bits_uop_ctrl_is_load_0 = io_dmem_resp_0_bits_uop_ctrl_is_load; // @[lsu.scala:201:7] wire io_dmem_resp_0_bits_uop_ctrl_is_sta_0 = io_dmem_resp_0_bits_uop_ctrl_is_sta; // @[lsu.scala:201:7] wire io_dmem_resp_0_bits_uop_ctrl_is_std_0 = io_dmem_resp_0_bits_uop_ctrl_is_std; // @[lsu.scala:201:7] wire [1:0] io_dmem_resp_0_bits_uop_iw_state_0 = io_dmem_resp_0_bits_uop_iw_state; // @[lsu.scala:201:7] wire io_dmem_resp_0_bits_uop_iw_p1_poisoned_0 = io_dmem_resp_0_bits_uop_iw_p1_poisoned; // @[lsu.scala:201:7] wire io_dmem_resp_0_bits_uop_iw_p2_poisoned_0 = io_dmem_resp_0_bits_uop_iw_p2_poisoned; // @[lsu.scala:201:7] wire io_dmem_resp_0_bits_uop_is_br_0 = io_dmem_resp_0_bits_uop_is_br; // @[lsu.scala:201:7] wire io_dmem_resp_0_bits_uop_is_jalr_0 = io_dmem_resp_0_bits_uop_is_jalr; // @[lsu.scala:201:7] wire io_dmem_resp_0_bits_uop_is_jal_0 = io_dmem_resp_0_bits_uop_is_jal; // @[lsu.scala:201:7] wire io_dmem_resp_0_bits_uop_is_sfb_0 = io_dmem_resp_0_bits_uop_is_sfb; // @[lsu.scala:201:7] wire [7:0] io_dmem_resp_0_bits_uop_br_mask_0 = io_dmem_resp_0_bits_uop_br_mask; // @[lsu.scala:201:7] wire [2:0] io_dmem_resp_0_bits_uop_br_tag_0 = io_dmem_resp_0_bits_uop_br_tag; // @[lsu.scala:201:7] wire [3:0] io_dmem_resp_0_bits_uop_ftq_idx_0 = io_dmem_resp_0_bits_uop_ftq_idx; // @[lsu.scala:201:7] wire io_dmem_resp_0_bits_uop_edge_inst_0 = io_dmem_resp_0_bits_uop_edge_inst; // @[lsu.scala:201:7] wire [5:0] io_dmem_resp_0_bits_uop_pc_lob_0 = io_dmem_resp_0_bits_uop_pc_lob; // @[lsu.scala:201:7] wire io_dmem_resp_0_bits_uop_taken_0 = io_dmem_resp_0_bits_uop_taken; // @[lsu.scala:201:7] wire [19:0] io_dmem_resp_0_bits_uop_imm_packed_0 = io_dmem_resp_0_bits_uop_imm_packed; // @[lsu.scala:201:7] wire [11:0] io_dmem_resp_0_bits_uop_csr_addr_0 = io_dmem_resp_0_bits_uop_csr_addr; // @[lsu.scala:201:7] wire [4:0] io_dmem_resp_0_bits_uop_rob_idx_0 = io_dmem_resp_0_bits_uop_rob_idx; // @[lsu.scala:201:7] wire [2:0] io_dmem_resp_0_bits_uop_ldq_idx_0 = io_dmem_resp_0_bits_uop_ldq_idx; // @[lsu.scala:201:7] wire [2:0] io_dmem_resp_0_bits_uop_stq_idx_0 = io_dmem_resp_0_bits_uop_stq_idx; // @[lsu.scala:201:7] wire [1:0] io_dmem_resp_0_bits_uop_rxq_idx_0 = io_dmem_resp_0_bits_uop_rxq_idx; // @[lsu.scala:201:7] wire [5:0] io_dmem_resp_0_bits_uop_pdst_0 = io_dmem_resp_0_bits_uop_pdst; // @[lsu.scala:201:7] wire [5:0] io_dmem_resp_0_bits_uop_prs1_0 = io_dmem_resp_0_bits_uop_prs1; // @[lsu.scala:201:7] wire [5:0] io_dmem_resp_0_bits_uop_prs2_0 = io_dmem_resp_0_bits_uop_prs2; // @[lsu.scala:201:7] wire [5:0] io_dmem_resp_0_bits_uop_prs3_0 = io_dmem_resp_0_bits_uop_prs3; // @[lsu.scala:201:7] wire [3:0] io_dmem_resp_0_bits_uop_ppred_0 = io_dmem_resp_0_bits_uop_ppred; // @[lsu.scala:201:7] wire io_dmem_resp_0_bits_uop_prs1_busy_0 = io_dmem_resp_0_bits_uop_prs1_busy; // @[lsu.scala:201:7] wire io_dmem_resp_0_bits_uop_prs2_busy_0 = io_dmem_resp_0_bits_uop_prs2_busy; // @[lsu.scala:201:7] wire io_dmem_resp_0_bits_uop_prs3_busy_0 = io_dmem_resp_0_bits_uop_prs3_busy; // @[lsu.scala:201:7] wire io_dmem_resp_0_bits_uop_ppred_busy_0 = io_dmem_resp_0_bits_uop_ppred_busy; // @[lsu.scala:201:7] wire [5:0] io_dmem_resp_0_bits_uop_stale_pdst_0 = io_dmem_resp_0_bits_uop_stale_pdst; // @[lsu.scala:201:7] wire io_dmem_resp_0_bits_uop_exception_0 = io_dmem_resp_0_bits_uop_exception; // @[lsu.scala:201:7] wire [63:0] io_dmem_resp_0_bits_uop_exc_cause_0 = io_dmem_resp_0_bits_uop_exc_cause; // @[lsu.scala:201:7] wire io_dmem_resp_0_bits_uop_bypassable_0 = io_dmem_resp_0_bits_uop_bypassable; // @[lsu.scala:201:7] wire [4:0] io_dmem_resp_0_bits_uop_mem_cmd_0 = io_dmem_resp_0_bits_uop_mem_cmd; // @[lsu.scala:201:7] wire [1:0] io_dmem_resp_0_bits_uop_mem_size_0 = io_dmem_resp_0_bits_uop_mem_size; // @[lsu.scala:201:7] wire io_dmem_resp_0_bits_uop_mem_signed_0 = io_dmem_resp_0_bits_uop_mem_signed; // @[lsu.scala:201:7] wire io_dmem_resp_0_bits_uop_is_fence_0 = io_dmem_resp_0_bits_uop_is_fence; // @[lsu.scala:201:7] wire io_dmem_resp_0_bits_uop_is_fencei_0 = io_dmem_resp_0_bits_uop_is_fencei; // @[lsu.scala:201:7] wire io_dmem_resp_0_bits_uop_is_amo_0 = io_dmem_resp_0_bits_uop_is_amo; // @[lsu.scala:201:7] wire io_dmem_resp_0_bits_uop_uses_ldq_0 = io_dmem_resp_0_bits_uop_uses_ldq; // @[lsu.scala:201:7] wire io_dmem_resp_0_bits_uop_uses_stq_0 = io_dmem_resp_0_bits_uop_uses_stq; // @[lsu.scala:201:7] wire io_dmem_resp_0_bits_uop_is_sys_pc2epc_0 = io_dmem_resp_0_bits_uop_is_sys_pc2epc; // @[lsu.scala:201:7] wire io_dmem_resp_0_bits_uop_is_unique_0 = io_dmem_resp_0_bits_uop_is_unique; // @[lsu.scala:201:7] wire io_dmem_resp_0_bits_uop_flush_on_commit_0 = io_dmem_resp_0_bits_uop_flush_on_commit; // @[lsu.scala:201:7] wire io_dmem_resp_0_bits_uop_ldst_is_rs1_0 = io_dmem_resp_0_bits_uop_ldst_is_rs1; // @[lsu.scala:201:7] wire [5:0] io_dmem_resp_0_bits_uop_ldst_0 = io_dmem_resp_0_bits_uop_ldst; // @[lsu.scala:201:7] wire [5:0] io_dmem_resp_0_bits_uop_lrs1_0 = io_dmem_resp_0_bits_uop_lrs1; // @[lsu.scala:201:7] wire [5:0] io_dmem_resp_0_bits_uop_lrs2_0 = io_dmem_resp_0_bits_uop_lrs2; // @[lsu.scala:201:7] wire [5:0] io_dmem_resp_0_bits_uop_lrs3_0 = io_dmem_resp_0_bits_uop_lrs3; // @[lsu.scala:201:7] wire io_dmem_resp_0_bits_uop_ldst_val_0 = io_dmem_resp_0_bits_uop_ldst_val; // @[lsu.scala:201:7] wire [1:0] io_dmem_resp_0_bits_uop_dst_rtype_0 = io_dmem_resp_0_bits_uop_dst_rtype; // @[lsu.scala:201:7] wire [1:0] io_dmem_resp_0_bits_uop_lrs1_rtype_0 = io_dmem_resp_0_bits_uop_lrs1_rtype; // @[lsu.scala:201:7] wire [1:0] io_dmem_resp_0_bits_uop_lrs2_rtype_0 = io_dmem_resp_0_bits_uop_lrs2_rtype; // @[lsu.scala:201:7] wire io_dmem_resp_0_bits_uop_frs3_en_0 = io_dmem_resp_0_bits_uop_frs3_en; // @[lsu.scala:201:7] wire io_dmem_resp_0_bits_uop_fp_val_0 = io_dmem_resp_0_bits_uop_fp_val; // @[lsu.scala:201:7] wire io_dmem_resp_0_bits_uop_fp_single_0 = io_dmem_resp_0_bits_uop_fp_single; // @[lsu.scala:201:7] wire io_dmem_resp_0_bits_uop_xcpt_pf_if_0 = io_dmem_resp_0_bits_uop_xcpt_pf_if; // @[lsu.scala:201:7] wire io_dmem_resp_0_bits_uop_xcpt_ae_if_0 = io_dmem_resp_0_bits_uop_xcpt_ae_if; // @[lsu.scala:201:7] wire io_dmem_resp_0_bits_uop_xcpt_ma_if_0 = io_dmem_resp_0_bits_uop_xcpt_ma_if; // @[lsu.scala:201:7] wire io_dmem_resp_0_bits_uop_bp_debug_if_0 = io_dmem_resp_0_bits_uop_bp_debug_if; // @[lsu.scala:201:7] wire io_dmem_resp_0_bits_uop_bp_xcpt_if_0 = io_dmem_resp_0_bits_uop_bp_xcpt_if; // @[lsu.scala:201:7] wire [1:0] io_dmem_resp_0_bits_uop_debug_fsrc_0 = io_dmem_resp_0_bits_uop_debug_fsrc; // @[lsu.scala:201:7] wire [1:0] io_dmem_resp_0_bits_uop_debug_tsrc_0 = io_dmem_resp_0_bits_uop_debug_tsrc; // @[lsu.scala:201:7] wire [63:0] io_dmem_resp_0_bits_data_0 = io_dmem_resp_0_bits_data; // @[lsu.scala:201:7] wire io_dmem_resp_0_bits_is_hella_0 = io_dmem_resp_0_bits_is_hella; // @[lsu.scala:201:7] wire io_dmem_nack_0_valid_0 = io_dmem_nack_0_valid; // @[lsu.scala:201:7] wire [6:0] io_dmem_nack_0_bits_uop_uopc_0 = io_dmem_nack_0_bits_uop_uopc; // @[lsu.scala:201:7] wire [31:0] io_dmem_nack_0_bits_uop_inst_0 = io_dmem_nack_0_bits_uop_inst; // @[lsu.scala:201:7] wire [31:0] io_dmem_nack_0_bits_uop_debug_inst_0 = io_dmem_nack_0_bits_uop_debug_inst; // @[lsu.scala:201:7] wire io_dmem_nack_0_bits_uop_is_rvc_0 = io_dmem_nack_0_bits_uop_is_rvc; // @[lsu.scala:201:7] wire [39:0] io_dmem_nack_0_bits_uop_debug_pc_0 = io_dmem_nack_0_bits_uop_debug_pc; // @[lsu.scala:201:7] wire [2:0] io_dmem_nack_0_bits_uop_iq_type_0 = io_dmem_nack_0_bits_uop_iq_type; // @[lsu.scala:201:7] wire [9:0] io_dmem_nack_0_bits_uop_fu_code_0 = io_dmem_nack_0_bits_uop_fu_code; // @[lsu.scala:201:7] wire [3:0] io_dmem_nack_0_bits_uop_ctrl_br_type_0 = io_dmem_nack_0_bits_uop_ctrl_br_type; // @[lsu.scala:201:7] wire [1:0] io_dmem_nack_0_bits_uop_ctrl_op1_sel_0 = io_dmem_nack_0_bits_uop_ctrl_op1_sel; // @[lsu.scala:201:7] wire [2:0] io_dmem_nack_0_bits_uop_ctrl_op2_sel_0 = io_dmem_nack_0_bits_uop_ctrl_op2_sel; // @[lsu.scala:201:7] wire [2:0] io_dmem_nack_0_bits_uop_ctrl_imm_sel_0 = io_dmem_nack_0_bits_uop_ctrl_imm_sel; // @[lsu.scala:201:7] wire [4:0] io_dmem_nack_0_bits_uop_ctrl_op_fcn_0 = io_dmem_nack_0_bits_uop_ctrl_op_fcn; // @[lsu.scala:201:7] wire io_dmem_nack_0_bits_uop_ctrl_fcn_dw_0 = io_dmem_nack_0_bits_uop_ctrl_fcn_dw; // @[lsu.scala:201:7] wire [2:0] io_dmem_nack_0_bits_uop_ctrl_csr_cmd_0 = io_dmem_nack_0_bits_uop_ctrl_csr_cmd; // @[lsu.scala:201:7] wire io_dmem_nack_0_bits_uop_ctrl_is_load_0 = io_dmem_nack_0_bits_uop_ctrl_is_load; // @[lsu.scala:201:7] wire io_dmem_nack_0_bits_uop_ctrl_is_sta_0 = io_dmem_nack_0_bits_uop_ctrl_is_sta; // @[lsu.scala:201:7] wire io_dmem_nack_0_bits_uop_ctrl_is_std_0 = io_dmem_nack_0_bits_uop_ctrl_is_std; // @[lsu.scala:201:7] wire [1:0] io_dmem_nack_0_bits_uop_iw_state_0 = io_dmem_nack_0_bits_uop_iw_state; // @[lsu.scala:201:7] wire io_dmem_nack_0_bits_uop_iw_p1_poisoned_0 = io_dmem_nack_0_bits_uop_iw_p1_poisoned; // @[lsu.scala:201:7] wire io_dmem_nack_0_bits_uop_iw_p2_poisoned_0 = io_dmem_nack_0_bits_uop_iw_p2_poisoned; // @[lsu.scala:201:7] wire io_dmem_nack_0_bits_uop_is_br_0 = io_dmem_nack_0_bits_uop_is_br; // @[lsu.scala:201:7] wire io_dmem_nack_0_bits_uop_is_jalr_0 = io_dmem_nack_0_bits_uop_is_jalr; // @[lsu.scala:201:7] wire io_dmem_nack_0_bits_uop_is_jal_0 = io_dmem_nack_0_bits_uop_is_jal; // @[lsu.scala:201:7] wire io_dmem_nack_0_bits_uop_is_sfb_0 = io_dmem_nack_0_bits_uop_is_sfb; // @[lsu.scala:201:7] wire [7:0] io_dmem_nack_0_bits_uop_br_mask_0 = io_dmem_nack_0_bits_uop_br_mask; // @[lsu.scala:201:7] wire [2:0] io_dmem_nack_0_bits_uop_br_tag_0 = io_dmem_nack_0_bits_uop_br_tag; // @[lsu.scala:201:7] wire [3:0] io_dmem_nack_0_bits_uop_ftq_idx_0 = io_dmem_nack_0_bits_uop_ftq_idx; // @[lsu.scala:201:7] wire io_dmem_nack_0_bits_uop_edge_inst_0 = io_dmem_nack_0_bits_uop_edge_inst; // @[lsu.scala:201:7] wire [5:0] io_dmem_nack_0_bits_uop_pc_lob_0 = io_dmem_nack_0_bits_uop_pc_lob; // @[lsu.scala:201:7] wire io_dmem_nack_0_bits_uop_taken_0 = io_dmem_nack_0_bits_uop_taken; // @[lsu.scala:201:7] wire [19:0] io_dmem_nack_0_bits_uop_imm_packed_0 = io_dmem_nack_0_bits_uop_imm_packed; // @[lsu.scala:201:7] wire [11:0] io_dmem_nack_0_bits_uop_csr_addr_0 = io_dmem_nack_0_bits_uop_csr_addr; // @[lsu.scala:201:7] wire [4:0] io_dmem_nack_0_bits_uop_rob_idx_0 = io_dmem_nack_0_bits_uop_rob_idx; // @[lsu.scala:201:7] wire [2:0] io_dmem_nack_0_bits_uop_ldq_idx_0 = io_dmem_nack_0_bits_uop_ldq_idx; // @[lsu.scala:201:7] wire [2:0] io_dmem_nack_0_bits_uop_stq_idx_0 = io_dmem_nack_0_bits_uop_stq_idx; // @[lsu.scala:201:7] wire [1:0] io_dmem_nack_0_bits_uop_rxq_idx_0 = io_dmem_nack_0_bits_uop_rxq_idx; // @[lsu.scala:201:7] wire [5:0] io_dmem_nack_0_bits_uop_pdst_0 = io_dmem_nack_0_bits_uop_pdst; // @[lsu.scala:201:7] wire [5:0] io_dmem_nack_0_bits_uop_prs1_0 = io_dmem_nack_0_bits_uop_prs1; // @[lsu.scala:201:7] wire [5:0] io_dmem_nack_0_bits_uop_prs2_0 = io_dmem_nack_0_bits_uop_prs2; // @[lsu.scala:201:7] wire [5:0] io_dmem_nack_0_bits_uop_prs3_0 = io_dmem_nack_0_bits_uop_prs3; // @[lsu.scala:201:7] wire [3:0] io_dmem_nack_0_bits_uop_ppred_0 = io_dmem_nack_0_bits_uop_ppred; // @[lsu.scala:201:7] wire io_dmem_nack_0_bits_uop_prs1_busy_0 = io_dmem_nack_0_bits_uop_prs1_busy; // @[lsu.scala:201:7] wire io_dmem_nack_0_bits_uop_prs2_busy_0 = io_dmem_nack_0_bits_uop_prs2_busy; // @[lsu.scala:201:7] wire io_dmem_nack_0_bits_uop_prs3_busy_0 = io_dmem_nack_0_bits_uop_prs3_busy; // @[lsu.scala:201:7] wire io_dmem_nack_0_bits_uop_ppred_busy_0 = io_dmem_nack_0_bits_uop_ppred_busy; // @[lsu.scala:201:7] wire [5:0] io_dmem_nack_0_bits_uop_stale_pdst_0 = io_dmem_nack_0_bits_uop_stale_pdst; // @[lsu.scala:201:7] wire io_dmem_nack_0_bits_uop_exception_0 = io_dmem_nack_0_bits_uop_exception; // @[lsu.scala:201:7] wire [63:0] io_dmem_nack_0_bits_uop_exc_cause_0 = io_dmem_nack_0_bits_uop_exc_cause; // @[lsu.scala:201:7] wire io_dmem_nack_0_bits_uop_bypassable_0 = io_dmem_nack_0_bits_uop_bypassable; // @[lsu.scala:201:7] wire [4:0] io_dmem_nack_0_bits_uop_mem_cmd_0 = io_dmem_nack_0_bits_uop_mem_cmd; // @[lsu.scala:201:7] wire [1:0] io_dmem_nack_0_bits_uop_mem_size_0 = io_dmem_nack_0_bits_uop_mem_size; // @[lsu.scala:201:7] wire io_dmem_nack_0_bits_uop_mem_signed_0 = io_dmem_nack_0_bits_uop_mem_signed; // @[lsu.scala:201:7] wire io_dmem_nack_0_bits_uop_is_fence_0 = io_dmem_nack_0_bits_uop_is_fence; // @[lsu.scala:201:7] wire io_dmem_nack_0_bits_uop_is_fencei_0 = io_dmem_nack_0_bits_uop_is_fencei; // @[lsu.scala:201:7] wire io_dmem_nack_0_bits_uop_is_amo_0 = io_dmem_nack_0_bits_uop_is_amo; // @[lsu.scala:201:7] wire io_dmem_nack_0_bits_uop_uses_ldq_0 = io_dmem_nack_0_bits_uop_uses_ldq; // @[lsu.scala:201:7] wire io_dmem_nack_0_bits_uop_uses_stq_0 = io_dmem_nack_0_bits_uop_uses_stq; // @[lsu.scala:201:7] wire io_dmem_nack_0_bits_uop_is_sys_pc2epc_0 = io_dmem_nack_0_bits_uop_is_sys_pc2epc; // @[lsu.scala:201:7] wire io_dmem_nack_0_bits_uop_is_unique_0 = io_dmem_nack_0_bits_uop_is_unique; // @[lsu.scala:201:7] wire io_dmem_nack_0_bits_uop_flush_on_commit_0 = io_dmem_nack_0_bits_uop_flush_on_commit; // @[lsu.scala:201:7] wire io_dmem_nack_0_bits_uop_ldst_is_rs1_0 = io_dmem_nack_0_bits_uop_ldst_is_rs1; // @[lsu.scala:201:7] wire [5:0] io_dmem_nack_0_bits_uop_ldst_0 = io_dmem_nack_0_bits_uop_ldst; // @[lsu.scala:201:7] wire [5:0] io_dmem_nack_0_bits_uop_lrs1_0 = io_dmem_nack_0_bits_uop_lrs1; // @[lsu.scala:201:7] wire [5:0] io_dmem_nack_0_bits_uop_lrs2_0 = io_dmem_nack_0_bits_uop_lrs2; // @[lsu.scala:201:7] wire [5:0] io_dmem_nack_0_bits_uop_lrs3_0 = io_dmem_nack_0_bits_uop_lrs3; // @[lsu.scala:201:7] wire io_dmem_nack_0_bits_uop_ldst_val_0 = io_dmem_nack_0_bits_uop_ldst_val; // @[lsu.scala:201:7] wire [1:0] io_dmem_nack_0_bits_uop_dst_rtype_0 = io_dmem_nack_0_bits_uop_dst_rtype; // @[lsu.scala:201:7] wire [1:0] io_dmem_nack_0_bits_uop_lrs1_rtype_0 = io_dmem_nack_0_bits_uop_lrs1_rtype; // @[lsu.scala:201:7] wire [1:0] io_dmem_nack_0_bits_uop_lrs2_rtype_0 = io_dmem_nack_0_bits_uop_lrs2_rtype; // @[lsu.scala:201:7] wire io_dmem_nack_0_bits_uop_frs3_en_0 = io_dmem_nack_0_bits_uop_frs3_en; // @[lsu.scala:201:7] wire io_dmem_nack_0_bits_uop_fp_val_0 = io_dmem_nack_0_bits_uop_fp_val; // @[lsu.scala:201:7] wire io_dmem_nack_0_bits_uop_fp_single_0 = io_dmem_nack_0_bits_uop_fp_single; // @[lsu.scala:201:7] wire io_dmem_nack_0_bits_uop_xcpt_pf_if_0 = io_dmem_nack_0_bits_uop_xcpt_pf_if; // @[lsu.scala:201:7] wire io_dmem_nack_0_bits_uop_xcpt_ae_if_0 = io_dmem_nack_0_bits_uop_xcpt_ae_if; // @[lsu.scala:201:7] wire io_dmem_nack_0_bits_uop_xcpt_ma_if_0 = io_dmem_nack_0_bits_uop_xcpt_ma_if; // @[lsu.scala:201:7] wire io_dmem_nack_0_bits_uop_bp_debug_if_0 = io_dmem_nack_0_bits_uop_bp_debug_if; // @[lsu.scala:201:7] wire io_dmem_nack_0_bits_uop_bp_xcpt_if_0 = io_dmem_nack_0_bits_uop_bp_xcpt_if; // @[lsu.scala:201:7] wire [1:0] io_dmem_nack_0_bits_uop_debug_fsrc_0 = io_dmem_nack_0_bits_uop_debug_fsrc; // @[lsu.scala:201:7] wire [1:0] io_dmem_nack_0_bits_uop_debug_tsrc_0 = io_dmem_nack_0_bits_uop_debug_tsrc; // @[lsu.scala:201:7] wire [39:0] io_dmem_nack_0_bits_addr_0 = io_dmem_nack_0_bits_addr; // @[lsu.scala:201:7] wire [63:0] io_dmem_nack_0_bits_data_0 = io_dmem_nack_0_bits_data; // @[lsu.scala:201:7] wire io_dmem_nack_0_bits_is_hella_0 = io_dmem_nack_0_bits_is_hella; // @[lsu.scala:201:7] wire io_dmem_release_valid_0 = io_dmem_release_valid; // @[lsu.scala:201:7] wire [2:0] io_dmem_release_bits_opcode_0 = io_dmem_release_bits_opcode; // @[lsu.scala:201:7] wire [2:0] io_dmem_release_bits_param_0 = io_dmem_release_bits_param; // @[lsu.scala:201:7] wire [3:0] io_dmem_release_bits_size_0 = io_dmem_release_bits_size; // @[lsu.scala:201:7] wire [1:0] io_dmem_release_bits_source_0 = io_dmem_release_bits_source; // @[lsu.scala:201:7] wire [31:0] io_dmem_release_bits_address_0 = io_dmem_release_bits_address; // @[lsu.scala:201:7] wire [63:0] io_dmem_release_bits_data_0 = io_dmem_release_bits_data; // @[lsu.scala:201:7] wire io_dmem_ordered_0 = io_dmem_ordered; // @[lsu.scala:201:7] wire io_dmem_perf_acquire_0 = io_dmem_perf_acquire; // @[lsu.scala:201:7] wire io_dmem_perf_release_0 = io_dmem_perf_release; // @[lsu.scala:201:7] wire io_hellacache_req_valid_0 = io_hellacache_req_valid; // @[lsu.scala:201:7] wire [39:0] io_hellacache_req_bits_addr_0 = io_hellacache_req_bits_addr; // @[lsu.scala:201:7] wire io_hellacache_req_bits_dv_0 = io_hellacache_req_bits_dv; // @[lsu.scala:201:7] wire io_hellacache_s1_kill_0 = io_hellacache_s1_kill; // @[lsu.scala:201:7] wire [15:0] io_ptw_ptbr_asid = 16'h0; // @[lsu.scala:201:7] wire [15:0] io_ptw_hgatp_asid = 16'h0; // @[lsu.scala:201:7] wire [15:0] io_ptw_vsatp_asid = 16'h0; // @[lsu.scala:201:7] wire [15:0] _dmem_req_0_bits_data_T_17 = 16'h0; // @[AMOALU.scala:29:32] wire [15:0] _dmem_req_0_bits_data_T_21 = 16'h0; // @[AMOALU.scala:29:69] wire [31:0] io_ptw_status_isa = 32'h14112D; // @[lsu.scala:201:7] wire [22:0] io_ptw_status_zero2 = 23'h0; // @[lsu.scala:201:7] wire [22:0] io_ptw_gstatus_zero2 = 23'h0; // @[lsu.scala:201:7] wire io_ptw_req_bits_bits_need_gpa = 1'h0; // @[lsu.scala:201:7] wire io_ptw_req_bits_bits_vstage1 = 1'h0; // @[lsu.scala:201:7] wire io_ptw_req_bits_bits_stage2 = 1'h0; // @[lsu.scala:201:7] wire io_ptw_resp_bits_fragmented_superpage = 1'h0; // @[lsu.scala:201:7] wire io_ptw_status_mbe = 1'h0; // @[lsu.scala:201:7] wire io_ptw_status_sbe = 1'h0; // @[lsu.scala:201:7] wire io_ptw_status_sd_rv32 = 1'h0; // @[lsu.scala:201:7] wire io_ptw_status_ube = 1'h0; // @[lsu.scala:201:7] wire io_ptw_status_upie = 1'h0; // @[lsu.scala:201:7] wire io_ptw_status_hie = 1'h0; // @[lsu.scala:201:7] wire io_ptw_status_uie = 1'h0; // @[lsu.scala:201:7] wire io_ptw_hstatus_vtsr = 1'h0; // @[lsu.scala:201:7] wire io_ptw_hstatus_vtw = 1'h0; // @[lsu.scala:201:7] wire io_ptw_hstatus_vtvm = 1'h0; // @[lsu.scala:201:7] wire io_ptw_hstatus_hu = 1'h0; // @[lsu.scala:201:7] wire io_ptw_hstatus_spvp = 1'h0; // @[lsu.scala:201:7] wire io_ptw_hstatus_spv = 1'h0; // @[lsu.scala:201:7] wire io_ptw_hstatus_gva = 1'h0; // @[lsu.scala:201:7] wire io_ptw_hstatus_vsbe = 1'h0; // @[lsu.scala:201:7] wire io_ptw_gstatus_debug = 1'h0; // @[lsu.scala:201:7] wire io_ptw_gstatus_cease = 1'h0; // @[lsu.scala:201:7] wire io_ptw_gstatus_wfi = 1'h0; // @[lsu.scala:201:7] wire io_ptw_gstatus_dv = 1'h0; // @[lsu.scala:201:7] wire io_ptw_gstatus_v = 1'h0; // @[lsu.scala:201:7] wire io_ptw_gstatus_sd = 1'h0; // @[lsu.scala:201:7] wire io_ptw_gstatus_mpv = 1'h0; // @[lsu.scala:201:7] wire io_ptw_gstatus_gva = 1'h0; // @[lsu.scala:201:7] wire io_ptw_gstatus_mbe = 1'h0; // @[lsu.scala:201:7] wire io_ptw_gstatus_sbe = 1'h0; // @[lsu.scala:201:7] wire io_ptw_gstatus_sd_rv32 = 1'h0; // @[lsu.scala:201:7] wire io_ptw_gstatus_tsr = 1'h0; // @[lsu.scala:201:7] wire io_ptw_gstatus_tw = 1'h0; // @[lsu.scala:201:7] wire io_ptw_gstatus_tvm = 1'h0; // @[lsu.scala:201:7] wire io_ptw_gstatus_mxr = 1'h0; // @[lsu.scala:201:7] wire io_ptw_gstatus_sum = 1'h0; // @[lsu.scala:201:7] wire io_ptw_gstatus_mprv = 1'h0; // @[lsu.scala:201:7] wire io_ptw_gstatus_spp = 1'h0; // @[lsu.scala:201:7] wire io_ptw_gstatus_mpie = 1'h0; // @[lsu.scala:201:7] wire io_ptw_gstatus_ube = 1'h0; // @[lsu.scala:201:7] wire io_ptw_gstatus_spie = 1'h0; // @[lsu.scala:201:7] wire io_ptw_gstatus_upie = 1'h0; // @[lsu.scala:201:7] wire io_ptw_gstatus_mie = 1'h0; // @[lsu.scala:201:7] wire io_ptw_gstatus_hie = 1'h0; // @[lsu.scala:201:7] wire io_ptw_gstatus_sie = 1'h0; // @[lsu.scala:201:7] wire io_ptw_gstatus_uie = 1'h0; // @[lsu.scala:201:7] wire io_ptw_customCSRs_csrs_0_ren = 1'h0; // @[lsu.scala:201:7] wire io_ptw_customCSRs_csrs_0_wen = 1'h0; // @[lsu.scala:201:7] wire io_ptw_customCSRs_csrs_0_stall = 1'h0; // @[lsu.scala:201:7] wire io_ptw_customCSRs_csrs_0_set = 1'h0; // @[lsu.scala:201:7] wire io_ptw_customCSRs_csrs_1_ren = 1'h0; // @[lsu.scala:201:7] wire io_ptw_customCSRs_csrs_1_wen = 1'h0; // @[lsu.scala:201:7] wire io_ptw_customCSRs_csrs_1_stall = 1'h0; // @[lsu.scala:201:7] wire io_ptw_customCSRs_csrs_1_set = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_req_bits_predicated = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_req_bits_fflags_valid = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_req_bits_fflags_bits_uop_is_rvc = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_req_bits_fflags_bits_uop_ctrl_fcn_dw = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_req_bits_fflags_bits_uop_ctrl_is_load = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_req_bits_fflags_bits_uop_ctrl_is_sta = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_req_bits_fflags_bits_uop_ctrl_is_std = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_req_bits_fflags_bits_uop_iw_p1_poisoned = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_req_bits_fflags_bits_uop_iw_p2_poisoned = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_req_bits_fflags_bits_uop_is_br = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_req_bits_fflags_bits_uop_is_jalr = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_req_bits_fflags_bits_uop_is_jal = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_req_bits_fflags_bits_uop_is_sfb = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_req_bits_fflags_bits_uop_edge_inst = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_req_bits_fflags_bits_uop_taken = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_req_bits_fflags_bits_uop_prs1_busy = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_req_bits_fflags_bits_uop_prs2_busy = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_req_bits_fflags_bits_uop_prs3_busy = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_req_bits_fflags_bits_uop_ppred_busy = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_req_bits_fflags_bits_uop_exception = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_req_bits_fflags_bits_uop_bypassable = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_req_bits_fflags_bits_uop_mem_signed = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_req_bits_fflags_bits_uop_is_fence = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_req_bits_fflags_bits_uop_is_fencei = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_req_bits_fflags_bits_uop_is_amo = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_req_bits_fflags_bits_uop_uses_ldq = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_req_bits_fflags_bits_uop_uses_stq = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_req_bits_fflags_bits_uop_is_sys_pc2epc = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_req_bits_fflags_bits_uop_is_unique = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_req_bits_fflags_bits_uop_flush_on_commit = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_req_bits_fflags_bits_uop_ldst_is_rs1 = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_req_bits_fflags_bits_uop_ldst_val = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_req_bits_fflags_bits_uop_frs3_en = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_req_bits_fflags_bits_uop_fp_val = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_req_bits_fflags_bits_uop_fp_single = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_req_bits_fflags_bits_uop_xcpt_pf_if = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_req_bits_fflags_bits_uop_xcpt_ae_if = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_req_bits_fflags_bits_uop_xcpt_ma_if = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_req_bits_fflags_bits_uop_bp_debug_if = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_req_bits_fflags_bits_uop_bp_xcpt_if = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_req_bits_sfence_bits_hv = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_req_bits_sfence_bits_hg = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_iresp_bits_predicated = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_iresp_bits_fflags_valid = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_iresp_bits_fflags_bits_uop_is_rvc = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_iresp_bits_fflags_bits_uop_ctrl_fcn_dw = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_iresp_bits_fflags_bits_uop_ctrl_is_load = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_iresp_bits_fflags_bits_uop_ctrl_is_sta = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_iresp_bits_fflags_bits_uop_ctrl_is_std = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_iresp_bits_fflags_bits_uop_iw_p1_poisoned = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_iresp_bits_fflags_bits_uop_iw_p2_poisoned = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_iresp_bits_fflags_bits_uop_is_br = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_iresp_bits_fflags_bits_uop_is_jalr = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_iresp_bits_fflags_bits_uop_is_jal = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_iresp_bits_fflags_bits_uop_is_sfb = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_iresp_bits_fflags_bits_uop_edge_inst = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_iresp_bits_fflags_bits_uop_taken = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_iresp_bits_fflags_bits_uop_prs1_busy = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_iresp_bits_fflags_bits_uop_prs2_busy = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_iresp_bits_fflags_bits_uop_prs3_busy = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_iresp_bits_fflags_bits_uop_ppred_busy = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_iresp_bits_fflags_bits_uop_exception = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_iresp_bits_fflags_bits_uop_bypassable = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_iresp_bits_fflags_bits_uop_mem_signed = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_iresp_bits_fflags_bits_uop_is_fence = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_iresp_bits_fflags_bits_uop_is_fencei = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_iresp_bits_fflags_bits_uop_is_amo = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_iresp_bits_fflags_bits_uop_uses_ldq = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_iresp_bits_fflags_bits_uop_uses_stq = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_iresp_bits_fflags_bits_uop_is_sys_pc2epc = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_iresp_bits_fflags_bits_uop_is_unique = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_iresp_bits_fflags_bits_uop_flush_on_commit = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_iresp_bits_fflags_bits_uop_ldst_is_rs1 = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_iresp_bits_fflags_bits_uop_ldst_val = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_iresp_bits_fflags_bits_uop_frs3_en = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_iresp_bits_fflags_bits_uop_fp_val = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_iresp_bits_fflags_bits_uop_fp_single = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_iresp_bits_fflags_bits_uop_xcpt_pf_if = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_iresp_bits_fflags_bits_uop_xcpt_ae_if = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_iresp_bits_fflags_bits_uop_xcpt_ma_if = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_iresp_bits_fflags_bits_uop_bp_debug_if = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_iresp_bits_fflags_bits_uop_bp_xcpt_if = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_fresp_bits_uop_ppred_busy_0 = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_fresp_bits_predicated = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_fresp_bits_fflags_valid = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_fresp_bits_fflags_bits_uop_is_rvc = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_fresp_bits_fflags_bits_uop_ctrl_fcn_dw = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_fresp_bits_fflags_bits_uop_ctrl_is_load = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_fresp_bits_fflags_bits_uop_ctrl_is_sta = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_fresp_bits_fflags_bits_uop_ctrl_is_std = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_fresp_bits_fflags_bits_uop_iw_p1_poisoned = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_fresp_bits_fflags_bits_uop_iw_p2_poisoned = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_fresp_bits_fflags_bits_uop_is_br = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_fresp_bits_fflags_bits_uop_is_jalr = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_fresp_bits_fflags_bits_uop_is_jal = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_fresp_bits_fflags_bits_uop_is_sfb = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_fresp_bits_fflags_bits_uop_edge_inst = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_fresp_bits_fflags_bits_uop_taken = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_fresp_bits_fflags_bits_uop_prs1_busy = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_fresp_bits_fflags_bits_uop_prs2_busy = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_fresp_bits_fflags_bits_uop_prs3_busy = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_fresp_bits_fflags_bits_uop_ppred_busy = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_fresp_bits_fflags_bits_uop_exception = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_fresp_bits_fflags_bits_uop_bypassable = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_fresp_bits_fflags_bits_uop_mem_signed = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_fresp_bits_fflags_bits_uop_is_fence = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_fresp_bits_fflags_bits_uop_is_fencei = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_fresp_bits_fflags_bits_uop_is_amo = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_fresp_bits_fflags_bits_uop_uses_ldq = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_fresp_bits_fflags_bits_uop_uses_stq = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_fresp_bits_fflags_bits_uop_is_sys_pc2epc = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_fresp_bits_fflags_bits_uop_is_unique = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_fresp_bits_fflags_bits_uop_flush_on_commit = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_fresp_bits_fflags_bits_uop_ldst_is_rs1 = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_fresp_bits_fflags_bits_uop_ldst_val = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_fresp_bits_fflags_bits_uop_frs3_en = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_fresp_bits_fflags_bits_uop_fp_val = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_fresp_bits_fflags_bits_uop_fp_single = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_fresp_bits_fflags_bits_uop_xcpt_pf_if = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_fresp_bits_fflags_bits_uop_xcpt_ae_if = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_fresp_bits_fflags_bits_uop_xcpt_ma_if = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_fresp_bits_fflags_bits_uop_bp_debug_if = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_fresp_bits_fflags_bits_uop_bp_xcpt_if = 1'h0; // @[lsu.scala:201:7] wire io_core_dis_uops_0_bits_ppred_busy = 1'h0; // @[lsu.scala:201:7] wire io_core_clr_unsafe_0_valid = 1'h0; // @[lsu.scala:201:7] wire io_dmem_release_bits_corrupt = 1'h0; // @[lsu.scala:201:7] wire io_hellacache_req_bits_signed = 1'h0; // @[lsu.scala:201:7] wire io_hellacache_req_bits_no_resp = 1'h0; // @[lsu.scala:201:7] wire io_hellacache_req_bits_no_alloc = 1'h0; // @[lsu.scala:201:7] wire io_hellacache_req_bits_no_xcpt = 1'h0; // @[lsu.scala:201:7] wire io_hellacache_s2_nack_cause_raw = 1'h0; // @[lsu.scala:201:7] wire io_hellacache_s2_kill = 1'h0; // @[lsu.scala:201:7] wire io_hellacache_s2_uncached = 1'h0; // @[lsu.scala:201:7] wire io_hellacache_resp_bits_signed = 1'h0; // @[lsu.scala:201:7] wire io_hellacache_resp_bits_dv = 1'h0; // @[lsu.scala:201:7] wire io_hellacache_resp_bits_replay = 1'h0; // @[lsu.scala:201:7] wire io_hellacache_resp_bits_has_data = 1'h0; // @[lsu.scala:201:7] wire io_hellacache_replay_next = 1'h0; // @[lsu.scala:201:7] wire io_hellacache_s2_gpa_is_pte = 1'h0; // @[lsu.scala:201:7] wire io_hellacache_ordered = 1'h0; // @[lsu.scala:201:7] wire io_hellacache_perf_acquire = 1'h0; // @[lsu.scala:201:7] wire io_hellacache_perf_release = 1'h0; // @[lsu.scala:201:7] wire io_hellacache_perf_grant = 1'h0; // @[lsu.scala:201:7] wire io_hellacache_perf_tlbMiss = 1'h0; // @[lsu.scala:201:7] wire io_hellacache_perf_blocked = 1'h0; // @[lsu.scala:201:7] wire io_hellacache_perf_canAcceptStoreThenLoad = 1'h0; // @[lsu.scala:201:7] wire io_hellacache_perf_canAcceptStoreThenRMW = 1'h0; // @[lsu.scala:201:7] wire io_hellacache_perf_canAcceptLoadThenLoad = 1'h0; // @[lsu.scala:201:7] wire io_hellacache_perf_storeBufferEmptyAfterLoad = 1'h0; // @[lsu.scala:201:7] wire io_hellacache_perf_storeBufferEmptyAfterStore = 1'h0; // @[lsu.scala:201:7] wire io_hellacache_keep_clock_enabled = 1'h0; // @[lsu.scala:201:7] wire io_hellacache_clock_enabled = 1'h0; // @[lsu.scala:201:7] wire _exe_req_WIRE_0_bits_predicated = 1'h0; // @[lsu.scala:383:33] wire _exe_req_WIRE_0_bits_fflags_valid = 1'h0; // @[lsu.scala:383:33] wire _exe_req_WIRE_0_bits_fflags_bits_uop_is_rvc = 1'h0; // @[lsu.scala:383:33] wire _exe_req_WIRE_0_bits_fflags_bits_uop_ctrl_fcn_dw = 1'h0; // @[lsu.scala:383:33] wire _exe_req_WIRE_0_bits_fflags_bits_uop_ctrl_is_load = 1'h0; // @[lsu.scala:383:33] wire _exe_req_WIRE_0_bits_fflags_bits_uop_ctrl_is_sta = 1'h0; // @[lsu.scala:383:33] wire _exe_req_WIRE_0_bits_fflags_bits_uop_ctrl_is_std = 1'h0; // @[lsu.scala:383:33] wire _exe_req_WIRE_0_bits_fflags_bits_uop_iw_p1_poisoned = 1'h0; // @[lsu.scala:383:33] wire _exe_req_WIRE_0_bits_fflags_bits_uop_iw_p2_poisoned = 1'h0; // @[lsu.scala:383:33] wire _exe_req_WIRE_0_bits_fflags_bits_uop_is_br = 1'h0; // @[lsu.scala:383:33] wire _exe_req_WIRE_0_bits_fflags_bits_uop_is_jalr = 1'h0; // @[lsu.scala:383:33] wire _exe_req_WIRE_0_bits_fflags_bits_uop_is_jal = 1'h0; // @[lsu.scala:383:33] wire _exe_req_WIRE_0_bits_fflags_bits_uop_is_sfb = 1'h0; // @[lsu.scala:383:33] wire _exe_req_WIRE_0_bits_fflags_bits_uop_edge_inst = 1'h0; // @[lsu.scala:383:33] wire _exe_req_WIRE_0_bits_fflags_bits_uop_taken = 1'h0; // @[lsu.scala:383:33] wire _exe_req_WIRE_0_bits_fflags_bits_uop_prs1_busy = 1'h0; // @[lsu.scala:383:33] wire _exe_req_WIRE_0_bits_fflags_bits_uop_prs2_busy = 1'h0; // @[lsu.scala:383:33] wire _exe_req_WIRE_0_bits_fflags_bits_uop_prs3_busy = 1'h0; // @[lsu.scala:383:33] wire _exe_req_WIRE_0_bits_fflags_bits_uop_ppred_busy = 1'h0; // @[lsu.scala:383:33] wire _exe_req_WIRE_0_bits_fflags_bits_uop_exception = 1'h0; // @[lsu.scala:383:33] wire _exe_req_WIRE_0_bits_fflags_bits_uop_bypassable = 1'h0; // @[lsu.scala:383:33] wire _exe_req_WIRE_0_bits_fflags_bits_uop_mem_signed = 1'h0; // @[lsu.scala:383:33] wire _exe_req_WIRE_0_bits_fflags_bits_uop_is_fence = 1'h0; // @[lsu.scala:383:33] wire _exe_req_WIRE_0_bits_fflags_bits_uop_is_fencei = 1'h0; // @[lsu.scala:383:33] wire _exe_req_WIRE_0_bits_fflags_bits_uop_is_amo = 1'h0; // @[lsu.scala:383:33] wire _exe_req_WIRE_0_bits_fflags_bits_uop_uses_ldq = 1'h0; // @[lsu.scala:383:33] wire _exe_req_WIRE_0_bits_fflags_bits_uop_uses_stq = 1'h0; // @[lsu.scala:383:33] wire _exe_req_WIRE_0_bits_fflags_bits_uop_is_sys_pc2epc = 1'h0; // @[lsu.scala:383:33] wire _exe_req_WIRE_0_bits_fflags_bits_uop_is_unique = 1'h0; // @[lsu.scala:383:33] wire _exe_req_WIRE_0_bits_fflags_bits_uop_flush_on_commit = 1'h0; // @[lsu.scala:383:33] wire _exe_req_WIRE_0_bits_fflags_bits_uop_ldst_is_rs1 = 1'h0; // @[lsu.scala:383:33] wire _exe_req_WIRE_0_bits_fflags_bits_uop_ldst_val = 1'h0; // @[lsu.scala:383:33] wire _exe_req_WIRE_0_bits_fflags_bits_uop_frs3_en = 1'h0; // @[lsu.scala:383:33] wire _exe_req_WIRE_0_bits_fflags_bits_uop_fp_val = 1'h0; // @[lsu.scala:383:33] wire _exe_req_WIRE_0_bits_fflags_bits_uop_fp_single = 1'h0; // @[lsu.scala:383:33] wire _exe_req_WIRE_0_bits_fflags_bits_uop_xcpt_pf_if = 1'h0; // @[lsu.scala:383:33] wire _exe_req_WIRE_0_bits_fflags_bits_uop_xcpt_ae_if = 1'h0; // @[lsu.scala:383:33] wire _exe_req_WIRE_0_bits_fflags_bits_uop_xcpt_ma_if = 1'h0; // @[lsu.scala:383:33] wire _exe_req_WIRE_0_bits_fflags_bits_uop_bp_debug_if = 1'h0; // @[lsu.scala:383:33] wire _exe_req_WIRE_0_bits_fflags_bits_uop_bp_xcpt_if = 1'h0; // @[lsu.scala:383:33] wire _exe_req_WIRE_0_bits_sfence_bits_hv = 1'h0; // @[lsu.scala:383:33] wire _exe_req_WIRE_0_bits_sfence_bits_hg = 1'h0; // @[lsu.scala:383:33] wire exe_req_0_bits_predicated = 1'h0; // @[lsu.scala:383:25] wire exe_req_0_bits_fflags_valid = 1'h0; // @[lsu.scala:383:25] wire exe_req_0_bits_fflags_bits_uop_is_rvc = 1'h0; // @[lsu.scala:383:25] wire exe_req_0_bits_fflags_bits_uop_ctrl_fcn_dw = 1'h0; // @[lsu.scala:383:25] wire exe_req_0_bits_fflags_bits_uop_ctrl_is_load = 1'h0; // @[lsu.scala:383:25] wire exe_req_0_bits_fflags_bits_uop_ctrl_is_sta = 1'h0; // @[lsu.scala:383:25] wire exe_req_0_bits_fflags_bits_uop_ctrl_is_std = 1'h0; // @[lsu.scala:383:25] wire exe_req_0_bits_fflags_bits_uop_iw_p1_poisoned = 1'h0; // @[lsu.scala:383:25] wire exe_req_0_bits_fflags_bits_uop_iw_p2_poisoned = 1'h0; // @[lsu.scala:383:25] wire exe_req_0_bits_fflags_bits_uop_is_br = 1'h0; // @[lsu.scala:383:25] wire exe_req_0_bits_fflags_bits_uop_is_jalr = 1'h0; // @[lsu.scala:383:25] wire exe_req_0_bits_fflags_bits_uop_is_jal = 1'h0; // @[lsu.scala:383:25] wire exe_req_0_bits_fflags_bits_uop_is_sfb = 1'h0; // @[lsu.scala:383:25] wire exe_req_0_bits_fflags_bits_uop_edge_inst = 1'h0; // @[lsu.scala:383:25] wire exe_req_0_bits_fflags_bits_uop_taken = 1'h0; // @[lsu.scala:383:25] wire exe_req_0_bits_fflags_bits_uop_prs1_busy = 1'h0; // @[lsu.scala:383:25] wire exe_req_0_bits_fflags_bits_uop_prs2_busy = 1'h0; // @[lsu.scala:383:25] wire exe_req_0_bits_fflags_bits_uop_prs3_busy = 1'h0; // @[lsu.scala:383:25] wire exe_req_0_bits_fflags_bits_uop_ppred_busy = 1'h0; // @[lsu.scala:383:25] wire exe_req_0_bits_fflags_bits_uop_exception = 1'h0; // @[lsu.scala:383:25] wire exe_req_0_bits_fflags_bits_uop_bypassable = 1'h0; // @[lsu.scala:383:25] wire exe_req_0_bits_fflags_bits_uop_mem_signed = 1'h0; // @[lsu.scala:383:25] wire exe_req_0_bits_fflags_bits_uop_is_fence = 1'h0; // @[lsu.scala:383:25] wire exe_req_0_bits_fflags_bits_uop_is_fencei = 1'h0; // @[lsu.scala:383:25] wire exe_req_0_bits_fflags_bits_uop_is_amo = 1'h0; // @[lsu.scala:383:25] wire exe_req_0_bits_fflags_bits_uop_uses_ldq = 1'h0; // @[lsu.scala:383:25] wire exe_req_0_bits_fflags_bits_uop_uses_stq = 1'h0; // @[lsu.scala:383:25] wire exe_req_0_bits_fflags_bits_uop_is_sys_pc2epc = 1'h0; // @[lsu.scala:383:25] wire exe_req_0_bits_fflags_bits_uop_is_unique = 1'h0; // @[lsu.scala:383:25] wire exe_req_0_bits_fflags_bits_uop_flush_on_commit = 1'h0; // @[lsu.scala:383:25] wire exe_req_0_bits_fflags_bits_uop_ldst_is_rs1 = 1'h0; // @[lsu.scala:383:25] wire exe_req_0_bits_fflags_bits_uop_ldst_val = 1'h0; // @[lsu.scala:383:25] wire exe_req_0_bits_fflags_bits_uop_frs3_en = 1'h0; // @[lsu.scala:383:25] wire exe_req_0_bits_fflags_bits_uop_fp_val = 1'h0; // @[lsu.scala:383:25] wire exe_req_0_bits_fflags_bits_uop_fp_single = 1'h0; // @[lsu.scala:383:25] wire exe_req_0_bits_fflags_bits_uop_xcpt_pf_if = 1'h0; // @[lsu.scala:383:25] wire exe_req_0_bits_fflags_bits_uop_xcpt_ae_if = 1'h0; // @[lsu.scala:383:25] wire exe_req_0_bits_fflags_bits_uop_xcpt_ma_if = 1'h0; // @[lsu.scala:383:25] wire exe_req_0_bits_fflags_bits_uop_bp_debug_if = 1'h0; // @[lsu.scala:383:25] wire exe_req_0_bits_fflags_bits_uop_bp_xcpt_if = 1'h0; // @[lsu.scala:383:25] wire exe_req_0_bits_sfence_bits_hv = 1'h0; // @[lsu.scala:383:25] wire exe_req_0_bits_sfence_bits_hg = 1'h0; // @[lsu.scala:383:25] wire _block_load_mask_WIRE_0 = 1'h0; // @[lsu.scala:396:44] wire _block_load_mask_WIRE_1 = 1'h0; // @[lsu.scala:396:44] wire _block_load_mask_WIRE_2 = 1'h0; // @[lsu.scala:396:44] wire _block_load_mask_WIRE_3 = 1'h0; // @[lsu.scala:396:44] wire _block_load_mask_WIRE_4 = 1'h0; // @[lsu.scala:396:44] wire _block_load_mask_WIRE_5 = 1'h0; // @[lsu.scala:396:44] wire _block_load_mask_WIRE_6 = 1'h0; // @[lsu.scala:396:44] wire _block_load_mask_WIRE_7 = 1'h0; // @[lsu.scala:396:44] wire ldq_incoming_e_0_bits_uop_ppred_busy = 1'h0; // @[lsu.scala:263:49] wire _can_fire_sta_retry_T_4 = 1'h0; // @[lsu.scala:482:75] wire _can_fire_sta_retry_T_6 = 1'h0; // @[lsu.scala:483:75] wire _can_fire_sta_retry_WIRE_0 = 1'h0; // @[lsu.scala:263:49] wire _can_fire_hella_incoming_WIRE_0 = 1'h0; // @[lsu.scala:263:49] wire _can_fire_hella_wakeup_WIRE_0 = 1'h0; // @[lsu.scala:263:49] wire _will_fire_load_incoming_0_will_fire_T = 1'h0; // @[lsu.scala:533:51] wire _will_fire_load_incoming_0_will_fire_T_1 = 1'h0; // @[lsu.scala:533:48] wire _will_fire_load_incoming_0_will_fire_T_4 = 1'h0; // @[lsu.scala:534:52] wire _will_fire_load_incoming_0_will_fire_T_5 = 1'h0; // @[lsu.scala:534:49] wire _will_fire_load_incoming_0_will_fire_T_8 = 1'h0; // @[lsu.scala:535:50] wire _will_fire_load_incoming_0_will_fire_T_9 = 1'h0; // @[lsu.scala:535:47] wire _will_fire_load_incoming_0_will_fire_T_12 = 1'h0; // @[lsu.scala:536:51] wire _will_fire_load_incoming_0_will_fire_T_13 = 1'h0; // @[lsu.scala:536:48] wire _will_fire_load_incoming_0_T_9 = 1'h0; // @[lsu.scala:540:46] wire _will_fire_stad_incoming_0_will_fire_T_9 = 1'h0; // @[lsu.scala:535:47] wire _will_fire_stad_incoming_0_will_fire_T_12 = 1'h0; // @[lsu.scala:536:51] wire _will_fire_stad_incoming_0_will_fire_T_13 = 1'h0; // @[lsu.scala:536:48] wire _will_fire_stad_incoming_0_T_6 = 1'h0; // @[lsu.scala:539:46] wire _will_fire_sta_incoming_0_will_fire_T_9 = 1'h0; // @[lsu.scala:535:47] wire _will_fire_sta_incoming_0_T_6 = 1'h0; // @[lsu.scala:539:46] wire _will_fire_std_incoming_0_will_fire_T_1 = 1'h0; // @[lsu.scala:533:48] wire _will_fire_std_incoming_0_will_fire_T_5 = 1'h0; // @[lsu.scala:534:49] wire _will_fire_std_incoming_0_will_fire_T_9 = 1'h0; // @[lsu.scala:535:47] wire _will_fire_std_incoming_0_T = 1'h0; // @[lsu.scala:537:46] wire _will_fire_std_incoming_0_T_3 = 1'h0; // @[lsu.scala:538:46] wire _will_fire_std_incoming_0_T_6 = 1'h0; // @[lsu.scala:539:46] wire _will_fire_sfence_0_will_fire_T_5 = 1'h0; // @[lsu.scala:534:49] wire _will_fire_sfence_0_will_fire_T_9 = 1'h0; // @[lsu.scala:535:47] wire _will_fire_sfence_0_T_3 = 1'h0; // @[lsu.scala:538:46] wire _will_fire_sfence_0_T_6 = 1'h0; // @[lsu.scala:539:46] wire _will_fire_release_0_will_fire_T_1 = 1'h0; // @[lsu.scala:533:48] wire _will_fire_release_0_will_fire_T_9 = 1'h0; // @[lsu.scala:535:47] wire _will_fire_release_0_will_fire_T_13 = 1'h0; // @[lsu.scala:536:48] wire _will_fire_release_0_T = 1'h0; // @[lsu.scala:537:46] wire _will_fire_release_0_T_6 = 1'h0; // @[lsu.scala:539:46] wire _will_fire_release_0_T_9 = 1'h0; // @[lsu.scala:540:46] wire _will_fire_hella_incoming_0_will_fire_T_5 = 1'h0; // @[lsu.scala:534:49] wire _will_fire_hella_incoming_0_will_fire_T_13 = 1'h0; // @[lsu.scala:536:48] wire _will_fire_hella_incoming_0_T_3 = 1'h0; // @[lsu.scala:538:46] wire _will_fire_hella_incoming_0_T_9 = 1'h0; // @[lsu.scala:540:46] wire _will_fire_hella_wakeup_0_will_fire_T_1 = 1'h0; // @[lsu.scala:533:48] wire _will_fire_hella_wakeup_0_will_fire_T_5 = 1'h0; // @[lsu.scala:534:49] wire _will_fire_hella_wakeup_0_will_fire_T_13 = 1'h0; // @[lsu.scala:536:48] wire _will_fire_hella_wakeup_0_T = 1'h0; // @[lsu.scala:537:46] wire _will_fire_hella_wakeup_0_T_3 = 1'h0; // @[lsu.scala:538:46] wire _will_fire_hella_wakeup_0_T_9 = 1'h0; // @[lsu.scala:540:46] wire _will_fire_load_retry_0_will_fire_T_13 = 1'h0; // @[lsu.scala:536:48] wire _will_fire_load_retry_0_T_9 = 1'h0; // @[lsu.scala:540:46] wire _will_fire_sta_retry_0_will_fire_T_9 = 1'h0; // @[lsu.scala:535:47] wire _will_fire_sta_retry_0_T_6 = 1'h0; // @[lsu.scala:539:46] wire _will_fire_load_wakeup_0_will_fire_T_1 = 1'h0; // @[lsu.scala:533:48] wire _will_fire_load_wakeup_0_will_fire_T_13 = 1'h0; // @[lsu.scala:536:48] wire _will_fire_load_wakeup_0_T = 1'h0; // @[lsu.scala:537:46] wire _will_fire_load_wakeup_0_T_9 = 1'h0; // @[lsu.scala:540:46] wire _will_fire_store_commit_0_will_fire_T_1 = 1'h0; // @[lsu.scala:533:48] wire _will_fire_store_commit_0_will_fire_T_5 = 1'h0; // @[lsu.scala:534:49] wire _will_fire_store_commit_0_will_fire_T_13 = 1'h0; // @[lsu.scala:536:48] wire _will_fire_store_commit_0_T = 1'h0; // @[lsu.scala:537:46] wire _will_fire_store_commit_0_T_3 = 1'h0; // @[lsu.scala:538:46] wire _will_fire_store_commit_0_T_9 = 1'h0; // @[lsu.scala:540:46] wire exe_tlb_uop_uop_is_rvc = 1'h0; // @[consts.scala:269:19] wire exe_tlb_uop_uop_ctrl_fcn_dw = 1'h0; // @[consts.scala:269:19] wire exe_tlb_uop_uop_ctrl_is_load = 1'h0; // @[consts.scala:269:19] wire exe_tlb_uop_uop_ctrl_is_sta = 1'h0; // @[consts.scala:269:19] wire exe_tlb_uop_uop_ctrl_is_std = 1'h0; // @[consts.scala:269:19] wire exe_tlb_uop_uop_iw_p1_poisoned = 1'h0; // @[consts.scala:269:19] wire exe_tlb_uop_uop_iw_p2_poisoned = 1'h0; // @[consts.scala:269:19] wire exe_tlb_uop_uop_is_br = 1'h0; // @[consts.scala:269:19] wire exe_tlb_uop_uop_is_jalr = 1'h0; // @[consts.scala:269:19] wire exe_tlb_uop_uop_is_jal = 1'h0; // @[consts.scala:269:19] wire exe_tlb_uop_uop_is_sfb = 1'h0; // @[consts.scala:269:19] wire exe_tlb_uop_uop_edge_inst = 1'h0; // @[consts.scala:269:19] wire exe_tlb_uop_uop_taken = 1'h0; // @[consts.scala:269:19] wire exe_tlb_uop_uop_prs1_busy = 1'h0; // @[consts.scala:269:19] wire exe_tlb_uop_uop_prs2_busy = 1'h0; // @[consts.scala:269:19] wire exe_tlb_uop_uop_prs3_busy = 1'h0; // @[consts.scala:269:19] wire exe_tlb_uop_uop_ppred_busy = 1'h0; // @[consts.scala:269:19] wire exe_tlb_uop_uop_exception = 1'h0; // @[consts.scala:269:19] wire exe_tlb_uop_uop_bypassable = 1'h0; // @[consts.scala:269:19] wire exe_tlb_uop_uop_mem_signed = 1'h0; // @[consts.scala:269:19] wire exe_tlb_uop_uop_is_fence = 1'h0; // @[consts.scala:269:19] wire exe_tlb_uop_uop_is_fencei = 1'h0; // @[consts.scala:269:19] wire exe_tlb_uop_uop_is_amo = 1'h0; // @[consts.scala:269:19] wire exe_tlb_uop_uop_uses_ldq = 1'h0; // @[consts.scala:269:19] wire exe_tlb_uop_uop_uses_stq = 1'h0; // @[consts.scala:269:19] wire exe_tlb_uop_uop_is_sys_pc2epc = 1'h0; // @[consts.scala:269:19] wire exe_tlb_uop_uop_is_unique = 1'h0; // @[consts.scala:269:19] wire exe_tlb_uop_uop_flush_on_commit = 1'h0; // @[consts.scala:269:19] wire exe_tlb_uop_uop_ldst_is_rs1 = 1'h0; // @[consts.scala:269:19] wire exe_tlb_uop_uop_ldst_val = 1'h0; // @[consts.scala:269:19] wire exe_tlb_uop_uop_frs3_en = 1'h0; // @[consts.scala:269:19] wire exe_tlb_uop_uop_fp_val = 1'h0; // @[consts.scala:269:19] wire exe_tlb_uop_uop_fp_single = 1'h0; // @[consts.scala:269:19] wire exe_tlb_uop_uop_xcpt_pf_if = 1'h0; // @[consts.scala:269:19] wire exe_tlb_uop_uop_xcpt_ae_if = 1'h0; // @[consts.scala:269:19] wire exe_tlb_uop_uop_xcpt_ma_if = 1'h0; // @[consts.scala:269:19] wire exe_tlb_uop_uop_bp_debug_if = 1'h0; // @[consts.scala:269:19] wire exe_tlb_uop_uop_bp_xcpt_if = 1'h0; // @[consts.scala:269:19] wire exe_tlb_uop_cs_fcn_dw = 1'h0; // @[consts.scala:279:18] wire exe_tlb_uop_cs_is_load = 1'h0; // @[consts.scala:279:18] wire exe_tlb_uop_cs_is_sta = 1'h0; // @[consts.scala:279:18] wire exe_tlb_uop_cs_is_std = 1'h0; // @[consts.scala:279:18] wire exe_tlb_uop_uop_1_is_rvc = 1'h0; // @[consts.scala:269:19] wire exe_tlb_uop_uop_1_ctrl_fcn_dw = 1'h0; // @[consts.scala:269:19] wire exe_tlb_uop_uop_1_ctrl_is_load = 1'h0; // @[consts.scala:269:19] wire exe_tlb_uop_uop_1_ctrl_is_sta = 1'h0; // @[consts.scala:269:19] wire exe_tlb_uop_uop_1_ctrl_is_std = 1'h0; // @[consts.scala:269:19] wire exe_tlb_uop_uop_1_iw_p1_poisoned = 1'h0; // @[consts.scala:269:19] wire exe_tlb_uop_uop_1_iw_p2_poisoned = 1'h0; // @[consts.scala:269:19] wire exe_tlb_uop_uop_1_is_br = 1'h0; // @[consts.scala:269:19] wire exe_tlb_uop_uop_1_is_jalr = 1'h0; // @[consts.scala:269:19] wire exe_tlb_uop_uop_1_is_jal = 1'h0; // @[consts.scala:269:19] wire exe_tlb_uop_uop_1_is_sfb = 1'h0; // @[consts.scala:269:19] wire exe_tlb_uop_uop_1_edge_inst = 1'h0; // @[consts.scala:269:19] wire exe_tlb_uop_uop_1_taken = 1'h0; // @[consts.scala:269:19] wire exe_tlb_uop_uop_1_prs1_busy = 1'h0; // @[consts.scala:269:19] wire exe_tlb_uop_uop_1_prs2_busy = 1'h0; // @[consts.scala:269:19] wire exe_tlb_uop_uop_1_prs3_busy = 1'h0; // @[consts.scala:269:19] wire exe_tlb_uop_uop_1_ppred_busy = 1'h0; // @[consts.scala:269:19] wire exe_tlb_uop_uop_1_exception = 1'h0; // @[consts.scala:269:19] wire exe_tlb_uop_uop_1_bypassable = 1'h0; // @[consts.scala:269:19] wire exe_tlb_uop_uop_1_mem_signed = 1'h0; // @[consts.scala:269:19] wire exe_tlb_uop_uop_1_is_fence = 1'h0; // @[consts.scala:269:19] wire exe_tlb_uop_uop_1_is_fencei = 1'h0; // @[consts.scala:269:19] wire exe_tlb_uop_uop_1_is_amo = 1'h0; // @[consts.scala:269:19] wire exe_tlb_uop_uop_1_uses_ldq = 1'h0; // @[consts.scala:269:19] wire exe_tlb_uop_uop_1_uses_stq = 1'h0; // @[consts.scala:269:19] wire exe_tlb_uop_uop_1_is_sys_pc2epc = 1'h0; // @[consts.scala:269:19] wire exe_tlb_uop_uop_1_is_unique = 1'h0; // @[consts.scala:269:19] wire exe_tlb_uop_uop_1_flush_on_commit = 1'h0; // @[consts.scala:269:19] wire exe_tlb_uop_uop_1_ldst_is_rs1 = 1'h0; // @[consts.scala:269:19] wire exe_tlb_uop_uop_1_ldst_val = 1'h0; // @[consts.scala:269:19] wire exe_tlb_uop_uop_1_frs3_en = 1'h0; // @[consts.scala:269:19] wire exe_tlb_uop_uop_1_fp_val = 1'h0; // @[consts.scala:269:19] wire exe_tlb_uop_uop_1_fp_single = 1'h0; // @[consts.scala:269:19] wire exe_tlb_uop_uop_1_xcpt_pf_if = 1'h0; // @[consts.scala:269:19] wire exe_tlb_uop_uop_1_xcpt_ae_if = 1'h0; // @[consts.scala:269:19] wire exe_tlb_uop_uop_1_xcpt_ma_if = 1'h0; // @[consts.scala:269:19] wire exe_tlb_uop_uop_1_bp_debug_if = 1'h0; // @[consts.scala:269:19] wire exe_tlb_uop_uop_1_bp_xcpt_if = 1'h0; // @[consts.scala:269:19] wire exe_tlb_uop_cs_1_fcn_dw = 1'h0; // @[consts.scala:279:18] wire exe_tlb_uop_cs_1_is_load = 1'h0; // @[consts.scala:279:18] wire exe_tlb_uop_cs_1_is_sta = 1'h0; // @[consts.scala:279:18] wire exe_tlb_uop_cs_1_is_std = 1'h0; // @[consts.scala:279:18] wire _exe_tlb_uop_T_3_is_rvc = 1'h0; // @[lsu.scala:602:24] wire _exe_tlb_uop_T_3_ctrl_fcn_dw = 1'h0; // @[lsu.scala:602:24] wire _exe_tlb_uop_T_3_ctrl_is_load = 1'h0; // @[lsu.scala:602:24] wire _exe_tlb_uop_T_3_ctrl_is_sta = 1'h0; // @[lsu.scala:602:24] wire _exe_tlb_uop_T_3_ctrl_is_std = 1'h0; // @[lsu.scala:602:24] wire _exe_tlb_uop_T_3_iw_p1_poisoned = 1'h0; // @[lsu.scala:602:24] wire _exe_tlb_uop_T_3_iw_p2_poisoned = 1'h0; // @[lsu.scala:602:24] wire _exe_tlb_uop_T_3_is_br = 1'h0; // @[lsu.scala:602:24] wire _exe_tlb_uop_T_3_is_jalr = 1'h0; // @[lsu.scala:602:24] wire _exe_tlb_uop_T_3_is_jal = 1'h0; // @[lsu.scala:602:24] wire _exe_tlb_uop_T_3_is_sfb = 1'h0; // @[lsu.scala:602:24] wire _exe_tlb_uop_T_3_edge_inst = 1'h0; // @[lsu.scala:602:24] wire _exe_tlb_uop_T_3_taken = 1'h0; // @[lsu.scala:602:24] wire _exe_tlb_uop_T_3_prs1_busy = 1'h0; // @[lsu.scala:602:24] wire _exe_tlb_uop_T_3_prs2_busy = 1'h0; // @[lsu.scala:602:24] wire _exe_tlb_uop_T_3_prs3_busy = 1'h0; // @[lsu.scala:602:24] wire _exe_tlb_uop_T_3_ppred_busy = 1'h0; // @[lsu.scala:602:24] wire _exe_tlb_uop_T_3_exception = 1'h0; // @[lsu.scala:602:24] wire _exe_tlb_uop_T_3_bypassable = 1'h0; // @[lsu.scala:602:24] wire _exe_tlb_uop_T_3_mem_signed = 1'h0; // @[lsu.scala:602:24] wire _exe_tlb_uop_T_3_is_fence = 1'h0; // @[lsu.scala:602:24] wire _exe_tlb_uop_T_3_is_fencei = 1'h0; // @[lsu.scala:602:24] wire _exe_tlb_uop_T_3_is_amo = 1'h0; // @[lsu.scala:602:24] wire _exe_tlb_uop_T_3_uses_ldq = 1'h0; // @[lsu.scala:602:24] wire _exe_tlb_uop_T_3_uses_stq = 1'h0; // @[lsu.scala:602:24] wire _exe_tlb_uop_T_3_is_sys_pc2epc = 1'h0; // @[lsu.scala:602:24] wire _exe_tlb_uop_T_3_is_unique = 1'h0; // @[lsu.scala:602:24] wire _exe_tlb_uop_T_3_flush_on_commit = 1'h0; // @[lsu.scala:602:24] wire _exe_tlb_uop_T_3_ldst_is_rs1 = 1'h0; // @[lsu.scala:602:24] wire _exe_tlb_uop_T_3_ldst_val = 1'h0; // @[lsu.scala:602:24] wire _exe_tlb_uop_T_3_frs3_en = 1'h0; // @[lsu.scala:602:24] wire _exe_tlb_uop_T_3_fp_val = 1'h0; // @[lsu.scala:602:24] wire _exe_tlb_uop_T_3_fp_single = 1'h0; // @[lsu.scala:602:24] wire _exe_tlb_uop_T_3_xcpt_pf_if = 1'h0; // @[lsu.scala:602:24] wire _exe_tlb_uop_T_3_xcpt_ae_if = 1'h0; // @[lsu.scala:602:24] wire _exe_tlb_uop_T_3_xcpt_ma_if = 1'h0; // @[lsu.scala:602:24] wire _exe_tlb_uop_T_3_bp_debug_if = 1'h0; // @[lsu.scala:602:24] wire _exe_tlb_uop_T_3_bp_xcpt_if = 1'h0; // @[lsu.scala:602:24] wire _exe_sfence_WIRE_valid = 1'h0; // @[lsu.scala:615:43] wire _exe_sfence_WIRE_bits_rs1 = 1'h0; // @[lsu.scala:615:43] wire _exe_sfence_WIRE_bits_rs2 = 1'h0; // @[lsu.scala:615:43] wire _exe_sfence_WIRE_bits_asid = 1'h0; // @[lsu.scala:615:43] wire _exe_sfence_WIRE_bits_hv = 1'h0; // @[lsu.scala:615:43] wire _exe_sfence_WIRE_bits_hg = 1'h0; // @[lsu.scala:615:43] wire exe_sfence_bits_hv = 1'h0; // @[lsu.scala:615:28] wire exe_sfence_bits_hg = 1'h0; // @[lsu.scala:615:28] wire _exe_tlb_miss_T = 1'h0; // @[lsu.scala:709:86] wire _s0_executing_loads_WIRE_0 = 1'h0; // @[lsu.scala:755:44] wire _s0_executing_loads_WIRE_1 = 1'h0; // @[lsu.scala:755:44] wire _s0_executing_loads_WIRE_2 = 1'h0; // @[lsu.scala:755:44] wire _s0_executing_loads_WIRE_3 = 1'h0; // @[lsu.scala:755:44] wire _s0_executing_loads_WIRE_4 = 1'h0; // @[lsu.scala:755:44] wire _s0_executing_loads_WIRE_5 = 1'h0; // @[lsu.scala:755:44] wire _s0_executing_loads_WIRE_6 = 1'h0; // @[lsu.scala:755:44] wire _s0_executing_loads_WIRE_7 = 1'h0; // @[lsu.scala:755:44] wire dmem_req_0_bits_uop_uop_is_rvc = 1'h0; // @[consts.scala:269:19] wire dmem_req_0_bits_uop_uop_ctrl_fcn_dw = 1'h0; // @[consts.scala:269:19] wire dmem_req_0_bits_uop_uop_ctrl_is_load = 1'h0; // @[consts.scala:269:19] wire dmem_req_0_bits_uop_uop_ctrl_is_sta = 1'h0; // @[consts.scala:269:19] wire dmem_req_0_bits_uop_uop_ctrl_is_std = 1'h0; // @[consts.scala:269:19] wire dmem_req_0_bits_uop_uop_iw_p1_poisoned = 1'h0; // @[consts.scala:269:19] wire dmem_req_0_bits_uop_uop_iw_p2_poisoned = 1'h0; // @[consts.scala:269:19] wire dmem_req_0_bits_uop_uop_is_br = 1'h0; // @[consts.scala:269:19] wire dmem_req_0_bits_uop_uop_is_jalr = 1'h0; // @[consts.scala:269:19] wire dmem_req_0_bits_uop_uop_is_jal = 1'h0; // @[consts.scala:269:19] wire dmem_req_0_bits_uop_uop_is_sfb = 1'h0; // @[consts.scala:269:19] wire dmem_req_0_bits_uop_uop_edge_inst = 1'h0; // @[consts.scala:269:19] wire dmem_req_0_bits_uop_uop_taken = 1'h0; // @[consts.scala:269:19] wire dmem_req_0_bits_uop_uop_prs1_busy = 1'h0; // @[consts.scala:269:19] wire dmem_req_0_bits_uop_uop_prs2_busy = 1'h0; // @[consts.scala:269:19] wire dmem_req_0_bits_uop_uop_prs3_busy = 1'h0; // @[consts.scala:269:19] wire dmem_req_0_bits_uop_uop_ppred_busy = 1'h0; // @[consts.scala:269:19] wire dmem_req_0_bits_uop_uop_exception = 1'h0; // @[consts.scala:269:19] wire dmem_req_0_bits_uop_uop_bypassable = 1'h0; // @[consts.scala:269:19] wire dmem_req_0_bits_uop_uop_mem_signed = 1'h0; // @[consts.scala:269:19] wire dmem_req_0_bits_uop_uop_is_fence = 1'h0; // @[consts.scala:269:19] wire dmem_req_0_bits_uop_uop_is_fencei = 1'h0; // @[consts.scala:269:19] wire dmem_req_0_bits_uop_uop_is_amo = 1'h0; // @[consts.scala:269:19] wire dmem_req_0_bits_uop_uop_uses_ldq = 1'h0; // @[consts.scala:269:19] wire dmem_req_0_bits_uop_uop_uses_stq = 1'h0; // @[consts.scala:269:19] wire dmem_req_0_bits_uop_uop_is_sys_pc2epc = 1'h0; // @[consts.scala:269:19] wire dmem_req_0_bits_uop_uop_is_unique = 1'h0; // @[consts.scala:269:19] wire dmem_req_0_bits_uop_uop_flush_on_commit = 1'h0; // @[consts.scala:269:19] wire dmem_req_0_bits_uop_uop_ldst_is_rs1 = 1'h0; // @[consts.scala:269:19] wire dmem_req_0_bits_uop_uop_ldst_val = 1'h0; // @[consts.scala:269:19] wire dmem_req_0_bits_uop_uop_frs3_en = 1'h0; // @[consts.scala:269:19] wire dmem_req_0_bits_uop_uop_fp_val = 1'h0; // @[consts.scala:269:19] wire dmem_req_0_bits_uop_uop_fp_single = 1'h0; // @[consts.scala:269:19] wire dmem_req_0_bits_uop_uop_xcpt_pf_if = 1'h0; // @[consts.scala:269:19] wire dmem_req_0_bits_uop_uop_xcpt_ae_if = 1'h0; // @[consts.scala:269:19] wire dmem_req_0_bits_uop_uop_xcpt_ma_if = 1'h0; // @[consts.scala:269:19] wire dmem_req_0_bits_uop_uop_bp_debug_if = 1'h0; // @[consts.scala:269:19] wire dmem_req_0_bits_uop_uop_bp_xcpt_if = 1'h0; // @[consts.scala:269:19] wire dmem_req_0_bits_uop_cs_fcn_dw = 1'h0; // @[consts.scala:279:18] wire dmem_req_0_bits_uop_cs_is_load = 1'h0; // @[consts.scala:279:18] wire dmem_req_0_bits_uop_cs_is_sta = 1'h0; // @[consts.scala:279:18] wire dmem_req_0_bits_uop_cs_is_std = 1'h0; // @[consts.scala:279:18] wire _dmem_req_0_bits_data_T_15 = 1'h0; // @[AMOALU.scala:29:19] wire _dmem_req_0_bits_data_T_20 = 1'h0; // @[AMOALU.scala:29:19] wire _dmem_req_0_bits_data_T_24 = 1'h0; // @[AMOALU.scala:29:19] wire _dmem_req_0_bits_data_T_30 = 1'h0; // @[AMOALU.scala:29:19] wire _dmem_req_0_bits_data_T_35 = 1'h0; // @[AMOALU.scala:29:19] wire _dmem_req_0_bits_data_T_39 = 1'h0; // @[AMOALU.scala:29:19] wire mem_ldq_wakeup_e_out_bits_uop_ppred_busy = 1'h0; // @[util.scala:106:23] wire mem_ldq_retry_e_out_bits_uop_ppred_busy = 1'h0; // @[util.scala:106:23] wire _mem_ldq_e_WIRE_valid = 1'h0; // @[lsu.scala:918:90] wire _mem_ldq_e_WIRE_bits_uop_is_rvc = 1'h0; // @[lsu.scala:918:90] wire _mem_ldq_e_WIRE_bits_uop_ctrl_fcn_dw = 1'h0; // @[lsu.scala:918:90] wire _mem_ldq_e_WIRE_bits_uop_ctrl_is_load = 1'h0; // @[lsu.scala:918:90] wire _mem_ldq_e_WIRE_bits_uop_ctrl_is_sta = 1'h0; // @[lsu.scala:918:90] wire _mem_ldq_e_WIRE_bits_uop_ctrl_is_std = 1'h0; // @[lsu.scala:918:90] wire _mem_ldq_e_WIRE_bits_uop_iw_p1_poisoned = 1'h0; // @[lsu.scala:918:90] wire _mem_ldq_e_WIRE_bits_uop_iw_p2_poisoned = 1'h0; // @[lsu.scala:918:90] wire _mem_ldq_e_WIRE_bits_uop_is_br = 1'h0; // @[lsu.scala:918:90] wire _mem_ldq_e_WIRE_bits_uop_is_jalr = 1'h0; // @[lsu.scala:918:90] wire _mem_ldq_e_WIRE_bits_uop_is_jal = 1'h0; // @[lsu.scala:918:90] wire _mem_ldq_e_WIRE_bits_uop_is_sfb = 1'h0; // @[lsu.scala:918:90] wire _mem_ldq_e_WIRE_bits_uop_edge_inst = 1'h0; // @[lsu.scala:918:90] wire _mem_ldq_e_WIRE_bits_uop_taken = 1'h0; // @[lsu.scala:918:90] wire _mem_ldq_e_WIRE_bits_uop_prs1_busy = 1'h0; // @[lsu.scala:918:90] wire _mem_ldq_e_WIRE_bits_uop_prs2_busy = 1'h0; // @[lsu.scala:918:90] wire _mem_ldq_e_WIRE_bits_uop_prs3_busy = 1'h0; // @[lsu.scala:918:90] wire _mem_ldq_e_WIRE_bits_uop_ppred_busy = 1'h0; // @[lsu.scala:918:90] wire _mem_ldq_e_WIRE_bits_uop_exception = 1'h0; // @[lsu.scala:918:90] wire _mem_ldq_e_WIRE_bits_uop_bypassable = 1'h0; // @[lsu.scala:918:90] wire _mem_ldq_e_WIRE_bits_uop_mem_signed = 1'h0; // @[lsu.scala:918:90] wire _mem_ldq_e_WIRE_bits_uop_is_fence = 1'h0; // @[lsu.scala:918:90] wire _mem_ldq_e_WIRE_bits_uop_is_fencei = 1'h0; // @[lsu.scala:918:90] wire _mem_ldq_e_WIRE_bits_uop_is_amo = 1'h0; // @[lsu.scala:918:90] wire _mem_ldq_e_WIRE_bits_uop_uses_ldq = 1'h0; // @[lsu.scala:918:90] wire _mem_ldq_e_WIRE_bits_uop_uses_stq = 1'h0; // @[lsu.scala:918:90] wire _mem_ldq_e_WIRE_bits_uop_is_sys_pc2epc = 1'h0; // @[lsu.scala:918:90] wire _mem_ldq_e_WIRE_bits_uop_is_unique = 1'h0; // @[lsu.scala:918:90] wire _mem_ldq_e_WIRE_bits_uop_flush_on_commit = 1'h0; // @[lsu.scala:918:90] wire _mem_ldq_e_WIRE_bits_uop_ldst_is_rs1 = 1'h0; // @[lsu.scala:918:90] wire _mem_ldq_e_WIRE_bits_uop_ldst_val = 1'h0; // @[lsu.scala:918:90] wire _mem_ldq_e_WIRE_bits_uop_frs3_en = 1'h0; // @[lsu.scala:918:90] wire _mem_ldq_e_WIRE_bits_uop_fp_val = 1'h0; // @[lsu.scala:918:90] wire _mem_ldq_e_WIRE_bits_uop_fp_single = 1'h0; // @[lsu.scala:918:90] wire _mem_ldq_e_WIRE_bits_uop_xcpt_pf_if = 1'h0; // @[lsu.scala:918:90] wire _mem_ldq_e_WIRE_bits_uop_xcpt_ae_if = 1'h0; // @[lsu.scala:918:90] wire _mem_ldq_e_WIRE_bits_uop_xcpt_ma_if = 1'h0; // @[lsu.scala:918:90] wire _mem_ldq_e_WIRE_bits_uop_bp_debug_if = 1'h0; // @[lsu.scala:918:90] wire _mem_ldq_e_WIRE_bits_uop_bp_xcpt_if = 1'h0; // @[lsu.scala:918:90] wire _mem_ldq_e_WIRE_bits_addr_valid = 1'h0; // @[lsu.scala:918:90] wire _mem_ldq_e_WIRE_bits_addr_is_virtual = 1'h0; // @[lsu.scala:918:90] wire _mem_ldq_e_WIRE_bits_addr_is_uncacheable = 1'h0; // @[lsu.scala:918:90] wire _mem_ldq_e_WIRE_bits_executed = 1'h0; // @[lsu.scala:918:90] wire _mem_ldq_e_WIRE_bits_succeeded = 1'h0; // @[lsu.scala:918:90] wire _mem_ldq_e_WIRE_bits_order_fail = 1'h0; // @[lsu.scala:918:90] wire _mem_ldq_e_WIRE_bits_observed = 1'h0; // @[lsu.scala:918:90] wire _mem_ldq_e_WIRE_bits_forward_std_val = 1'h0; // @[lsu.scala:918:90] wire _mem_stq_e_WIRE_valid = 1'h0; // @[lsu.scala:922:89] wire _mem_stq_e_WIRE_bits_uop_is_rvc = 1'h0; // @[lsu.scala:922:89] wire _mem_stq_e_WIRE_bits_uop_ctrl_fcn_dw = 1'h0; // @[lsu.scala:922:89] wire _mem_stq_e_WIRE_bits_uop_ctrl_is_load = 1'h0; // @[lsu.scala:922:89] wire _mem_stq_e_WIRE_bits_uop_ctrl_is_sta = 1'h0; // @[lsu.scala:922:89] wire _mem_stq_e_WIRE_bits_uop_ctrl_is_std = 1'h0; // @[lsu.scala:922:89] wire _mem_stq_e_WIRE_bits_uop_iw_p1_poisoned = 1'h0; // @[lsu.scala:922:89] wire _mem_stq_e_WIRE_bits_uop_iw_p2_poisoned = 1'h0; // @[lsu.scala:922:89] wire _mem_stq_e_WIRE_bits_uop_is_br = 1'h0; // @[lsu.scala:922:89] wire _mem_stq_e_WIRE_bits_uop_is_jalr = 1'h0; // @[lsu.scala:922:89] wire _mem_stq_e_WIRE_bits_uop_is_jal = 1'h0; // @[lsu.scala:922:89] wire _mem_stq_e_WIRE_bits_uop_is_sfb = 1'h0; // @[lsu.scala:922:89] wire _mem_stq_e_WIRE_bits_uop_edge_inst = 1'h0; // @[lsu.scala:922:89] wire _mem_stq_e_WIRE_bits_uop_taken = 1'h0; // @[lsu.scala:922:89] wire _mem_stq_e_WIRE_bits_uop_prs1_busy = 1'h0; // @[lsu.scala:922:89] wire _mem_stq_e_WIRE_bits_uop_prs2_busy = 1'h0; // @[lsu.scala:922:89] wire _mem_stq_e_WIRE_bits_uop_prs3_busy = 1'h0; // @[lsu.scala:922:89] wire _mem_stq_e_WIRE_bits_uop_ppred_busy = 1'h0; // @[lsu.scala:922:89] wire _mem_stq_e_WIRE_bits_uop_exception = 1'h0; // @[lsu.scala:922:89] wire _mem_stq_e_WIRE_bits_uop_bypassable = 1'h0; // @[lsu.scala:922:89] wire _mem_stq_e_WIRE_bits_uop_mem_signed = 1'h0; // @[lsu.scala:922:89] wire _mem_stq_e_WIRE_bits_uop_is_fence = 1'h0; // @[lsu.scala:922:89] wire _mem_stq_e_WIRE_bits_uop_is_fencei = 1'h0; // @[lsu.scala:922:89] wire _mem_stq_e_WIRE_bits_uop_is_amo = 1'h0; // @[lsu.scala:922:89] wire _mem_stq_e_WIRE_bits_uop_uses_ldq = 1'h0; // @[lsu.scala:922:89] wire _mem_stq_e_WIRE_bits_uop_uses_stq = 1'h0; // @[lsu.scala:922:89] wire _mem_stq_e_WIRE_bits_uop_is_sys_pc2epc = 1'h0; // @[lsu.scala:922:89] wire _mem_stq_e_WIRE_bits_uop_is_unique = 1'h0; // @[lsu.scala:922:89] wire _mem_stq_e_WIRE_bits_uop_flush_on_commit = 1'h0; // @[lsu.scala:922:89] wire _mem_stq_e_WIRE_bits_uop_ldst_is_rs1 = 1'h0; // @[lsu.scala:922:89] wire _mem_stq_e_WIRE_bits_uop_ldst_val = 1'h0; // @[lsu.scala:922:89] wire _mem_stq_e_WIRE_bits_uop_frs3_en = 1'h0; // @[lsu.scala:922:89] wire _mem_stq_e_WIRE_bits_uop_fp_val = 1'h0; // @[lsu.scala:922:89] wire _mem_stq_e_WIRE_bits_uop_fp_single = 1'h0; // @[lsu.scala:922:89] wire _mem_stq_e_WIRE_bits_uop_xcpt_pf_if = 1'h0; // @[lsu.scala:922:89] wire _mem_stq_e_WIRE_bits_uop_xcpt_ae_if = 1'h0; // @[lsu.scala:922:89] wire _mem_stq_e_WIRE_bits_uop_xcpt_ma_if = 1'h0; // @[lsu.scala:922:89] wire _mem_stq_e_WIRE_bits_uop_bp_debug_if = 1'h0; // @[lsu.scala:922:89] wire _mem_stq_e_WIRE_bits_uop_bp_xcpt_if = 1'h0; // @[lsu.scala:922:89] wire _mem_stq_e_WIRE_bits_addr_valid = 1'h0; // @[lsu.scala:922:89] wire _mem_stq_e_WIRE_bits_addr_is_virtual = 1'h0; // @[lsu.scala:922:89] wire _mem_stq_e_WIRE_bits_data_valid = 1'h0; // @[lsu.scala:922:89] wire _mem_stq_e_WIRE_bits_committed = 1'h0; // @[lsu.scala:922:89] wire _mem_stq_e_WIRE_bits_succeeded = 1'h0; // @[lsu.scala:922:89] wire _clr_bsy_valid_WIRE_0 = 1'h0; // @[lsu.scala:263:49] wire lcam_uop_uop_is_rvc = 1'h0; // @[consts.scala:269:19] wire lcam_uop_uop_ctrl_fcn_dw = 1'h0; // @[consts.scala:269:19] wire lcam_uop_uop_ctrl_is_load = 1'h0; // @[consts.scala:269:19] wire lcam_uop_uop_ctrl_is_sta = 1'h0; // @[consts.scala:269:19] wire lcam_uop_uop_ctrl_is_std = 1'h0; // @[consts.scala:269:19] wire lcam_uop_uop_iw_p1_poisoned = 1'h0; // @[consts.scala:269:19] wire lcam_uop_uop_iw_p2_poisoned = 1'h0; // @[consts.scala:269:19] wire lcam_uop_uop_is_br = 1'h0; // @[consts.scala:269:19] wire lcam_uop_uop_is_jalr = 1'h0; // @[consts.scala:269:19] wire lcam_uop_uop_is_jal = 1'h0; // @[consts.scala:269:19] wire lcam_uop_uop_is_sfb = 1'h0; // @[consts.scala:269:19] wire lcam_uop_uop_edge_inst = 1'h0; // @[consts.scala:269:19] wire lcam_uop_uop_taken = 1'h0; // @[consts.scala:269:19] wire lcam_uop_uop_prs1_busy = 1'h0; // @[consts.scala:269:19] wire lcam_uop_uop_prs2_busy = 1'h0; // @[consts.scala:269:19] wire lcam_uop_uop_prs3_busy = 1'h0; // @[consts.scala:269:19] wire lcam_uop_uop_ppred_busy = 1'h0; // @[consts.scala:269:19] wire lcam_uop_uop_exception = 1'h0; // @[consts.scala:269:19] wire lcam_uop_uop_bypassable = 1'h0; // @[consts.scala:269:19] wire lcam_uop_uop_mem_signed = 1'h0; // @[consts.scala:269:19] wire lcam_uop_uop_is_fence = 1'h0; // @[consts.scala:269:19] wire lcam_uop_uop_is_fencei = 1'h0; // @[consts.scala:269:19] wire lcam_uop_uop_is_amo = 1'h0; // @[consts.scala:269:19] wire lcam_uop_uop_uses_ldq = 1'h0; // @[consts.scala:269:19] wire lcam_uop_uop_uses_stq = 1'h0; // @[consts.scala:269:19] wire lcam_uop_uop_is_sys_pc2epc = 1'h0; // @[consts.scala:269:19] wire lcam_uop_uop_is_unique = 1'h0; // @[consts.scala:269:19] wire lcam_uop_uop_flush_on_commit = 1'h0; // @[consts.scala:269:19] wire lcam_uop_uop_ldst_is_rs1 = 1'h0; // @[consts.scala:269:19] wire lcam_uop_uop_ldst_val = 1'h0; // @[consts.scala:269:19] wire lcam_uop_uop_frs3_en = 1'h0; // @[consts.scala:269:19] wire lcam_uop_uop_fp_val = 1'h0; // @[consts.scala:269:19] wire lcam_uop_uop_fp_single = 1'h0; // @[consts.scala:269:19] wire lcam_uop_uop_xcpt_pf_if = 1'h0; // @[consts.scala:269:19] wire lcam_uop_uop_xcpt_ae_if = 1'h0; // @[consts.scala:269:19] wire lcam_uop_uop_xcpt_ma_if = 1'h0; // @[consts.scala:269:19] wire lcam_uop_uop_bp_debug_if = 1'h0; // @[consts.scala:269:19] wire lcam_uop_uop_bp_xcpt_if = 1'h0; // @[consts.scala:269:19] wire lcam_uop_cs_fcn_dw = 1'h0; // @[consts.scala:279:18] wire lcam_uop_cs_is_load = 1'h0; // @[consts.scala:279:18] wire lcam_uop_cs_is_sta = 1'h0; // @[consts.scala:279:18] wire lcam_uop_cs_is_std = 1'h0; // @[consts.scala:279:18] wire _ldst_addr_matches_WIRE_0 = 1'h0; // @[lsu.scala:1050:60] wire _ldst_addr_matches_WIRE_1 = 1'h0; // @[lsu.scala:1050:60] wire _ldst_addr_matches_WIRE_2 = 1'h0; // @[lsu.scala:1050:60] wire _ldst_addr_matches_WIRE_3 = 1'h0; // @[lsu.scala:1050:60] wire _ldst_addr_matches_WIRE_4 = 1'h0; // @[lsu.scala:1050:60] wire _ldst_addr_matches_WIRE_5 = 1'h0; // @[lsu.scala:1050:60] wire _ldst_addr_matches_WIRE_6 = 1'h0; // @[lsu.scala:1050:60] wire _ldst_addr_matches_WIRE_7 = 1'h0; // @[lsu.scala:1050:60] wire _ldst_addr_matches_WIRE_1_0_0 = 1'h0; // @[lsu.scala:263:49] wire _ldst_addr_matches_WIRE_1_0_1 = 1'h0; // @[lsu.scala:263:49] wire _ldst_addr_matches_WIRE_1_0_2 = 1'h0; // @[lsu.scala:263:49] wire _ldst_addr_matches_WIRE_1_0_3 = 1'h0; // @[lsu.scala:263:49] wire _ldst_addr_matches_WIRE_1_0_4 = 1'h0; // @[lsu.scala:263:49] wire _ldst_addr_matches_WIRE_1_0_5 = 1'h0; // @[lsu.scala:263:49] wire _ldst_addr_matches_WIRE_1_0_6 = 1'h0; // @[lsu.scala:263:49] wire _ldst_addr_matches_WIRE_1_0_7 = 1'h0; // @[lsu.scala:263:49] wire _ldst_forward_matches_WIRE_0 = 1'h0; // @[lsu.scala:1052:60] wire _ldst_forward_matches_WIRE_1 = 1'h0; // @[lsu.scala:1052:60] wire _ldst_forward_matches_WIRE_2 = 1'h0; // @[lsu.scala:1052:60] wire _ldst_forward_matches_WIRE_3 = 1'h0; // @[lsu.scala:1052:60] wire _ldst_forward_matches_WIRE_4 = 1'h0; // @[lsu.scala:1052:60] wire _ldst_forward_matches_WIRE_5 = 1'h0; // @[lsu.scala:1052:60] wire _ldst_forward_matches_WIRE_6 = 1'h0; // @[lsu.scala:1052:60] wire _ldst_forward_matches_WIRE_7 = 1'h0; // @[lsu.scala:1052:60] wire _ldst_forward_matches_WIRE_1_0_0 = 1'h0; // @[lsu.scala:263:49] wire _ldst_forward_matches_WIRE_1_0_1 = 1'h0; // @[lsu.scala:263:49] wire _ldst_forward_matches_WIRE_1_0_2 = 1'h0; // @[lsu.scala:263:49] wire _ldst_forward_matches_WIRE_1_0_3 = 1'h0; // @[lsu.scala:263:49] wire _ldst_forward_matches_WIRE_1_0_4 = 1'h0; // @[lsu.scala:263:49] wire _ldst_forward_matches_WIRE_1_0_5 = 1'h0; // @[lsu.scala:263:49] wire _ldst_forward_matches_WIRE_1_0_6 = 1'h0; // @[lsu.scala:263:49] wire _ldst_forward_matches_WIRE_1_0_7 = 1'h0; // @[lsu.scala:263:49] wire _failed_loads_WIRE_0 = 1'h0; // @[lsu.scala:1054:42] wire _failed_loads_WIRE_1 = 1'h0; // @[lsu.scala:1054:42] wire _failed_loads_WIRE_2 = 1'h0; // @[lsu.scala:1054:42] wire _failed_loads_WIRE_3 = 1'h0; // @[lsu.scala:1054:42] wire _failed_loads_WIRE_4 = 1'h0; // @[lsu.scala:1054:42] wire _failed_loads_WIRE_5 = 1'h0; // @[lsu.scala:1054:42] wire _failed_loads_WIRE_6 = 1'h0; // @[lsu.scala:1054:42] wire _failed_loads_WIRE_7 = 1'h0; // @[lsu.scala:1054:42] wire _nacking_loads_WIRE_0 = 1'h0; // @[lsu.scala:1055:42] wire _nacking_loads_WIRE_1 = 1'h0; // @[lsu.scala:1055:42] wire _nacking_loads_WIRE_2 = 1'h0; // @[lsu.scala:1055:42] wire _nacking_loads_WIRE_3 = 1'h0; // @[lsu.scala:1055:42] wire _nacking_loads_WIRE_4 = 1'h0; // @[lsu.scala:1055:42] wire _nacking_loads_WIRE_5 = 1'h0; // @[lsu.scala:1055:42] wire _nacking_loads_WIRE_6 = 1'h0; // @[lsu.scala:1055:42] wire _nacking_loads_WIRE_7 = 1'h0; // @[lsu.scala:1055:42] wire _searcher_is_older_T = 1'h0; // @[util.scala:363:52] wire _searcher_is_older_T_31 = 1'h0; // @[util.scala:363:78] wire _io_core_clr_unsafe_0_valid_T_3 = 1'h0; // @[lsu.scala:1221:107] wire _dmem_resp_fired_WIRE_0 = 1'h0; // @[lsu.scala:263:49] wire io_core_exe_0_iresp_bits_data_doZero = 1'h0; // @[AMOALU.scala:43:31] wire io_core_exe_0_iresp_bits_data_doZero_1 = 1'h0; // @[AMOALU.scala:43:31] wire io_core_exe_0_iresp_bits_data_doZero_2 = 1'h0; // @[AMOALU.scala:43:31] wire io_core_exe_0_fresp_bits_data_doZero = 1'h0; // @[AMOALU.scala:43:31] wire io_core_exe_0_fresp_bits_data_doZero_1 = 1'h0; // @[AMOALU.scala:43:31] wire io_core_exe_0_fresp_bits_data_doZero_2 = 1'h0; // @[AMOALU.scala:43:31] wire ldq_bits_debug_wb_data_doZero = 1'h0; // @[AMOALU.scala:43:31] wire ldq_bits_debug_wb_data_doZero_1 = 1'h0; // @[AMOALU.scala:43:31] wire ldq_bits_debug_wb_data_doZero_2 = 1'h0; // @[AMOALU.scala:43:31] wire _io_hellacache_s2_xcpt_WIRE_ma_ld = 1'h0; // @[lsu.scala:1528:44] wire _io_hellacache_s2_xcpt_WIRE_ma_st = 1'h0; // @[lsu.scala:1528:44] wire _io_hellacache_s2_xcpt_WIRE_pf_ld = 1'h0; // @[lsu.scala:1528:44] wire _io_hellacache_s2_xcpt_WIRE_pf_st = 1'h0; // @[lsu.scala:1528:44] wire _io_hellacache_s2_xcpt_WIRE_gf_ld = 1'h0; // @[lsu.scala:1528:44] wire _io_hellacache_s2_xcpt_WIRE_gf_st = 1'h0; // @[lsu.scala:1528:44] wire _io_hellacache_s2_xcpt_WIRE_ae_ld = 1'h0; // @[lsu.scala:1528:44] wire _io_hellacache_s2_xcpt_WIRE_ae_st = 1'h0; // @[lsu.scala:1528:44] wire _st_exc_killed_mask_WIRE_0 = 1'h0; // @[lsu.scala:1598:44] wire _st_exc_killed_mask_WIRE_1 = 1'h0; // @[lsu.scala:1598:44] wire _st_exc_killed_mask_WIRE_2 = 1'h0; // @[lsu.scala:1598:44] wire _st_exc_killed_mask_WIRE_3 = 1'h0; // @[lsu.scala:1598:44] wire _st_exc_killed_mask_WIRE_4 = 1'h0; // @[lsu.scala:1598:44] wire _st_exc_killed_mask_WIRE_5 = 1'h0; // @[lsu.scala:1598:44] wire _st_exc_killed_mask_WIRE_6 = 1'h0; // @[lsu.scala:1598:44] wire _st_exc_killed_mask_WIRE_7 = 1'h0; // @[lsu.scala:1598:44] wire stq_0_bits_uop_uop_is_rvc = 1'h0; // @[consts.scala:269:19] wire stq_0_bits_uop_uop_ctrl_fcn_dw = 1'h0; // @[consts.scala:269:19] wire stq_0_bits_uop_uop_ctrl_is_load = 1'h0; // @[consts.scala:269:19] wire stq_0_bits_uop_uop_ctrl_is_sta = 1'h0; // @[consts.scala:269:19] wire stq_0_bits_uop_uop_ctrl_is_std = 1'h0; // @[consts.scala:269:19] wire stq_0_bits_uop_uop_iw_p1_poisoned = 1'h0; // @[consts.scala:269:19] wire stq_0_bits_uop_uop_iw_p2_poisoned = 1'h0; // @[consts.scala:269:19] wire stq_0_bits_uop_uop_is_br = 1'h0; // @[consts.scala:269:19] wire stq_0_bits_uop_uop_is_jalr = 1'h0; // @[consts.scala:269:19] wire stq_0_bits_uop_uop_is_jal = 1'h0; // @[consts.scala:269:19] wire stq_0_bits_uop_uop_is_sfb = 1'h0; // @[consts.scala:269:19] wire stq_0_bits_uop_uop_edge_inst = 1'h0; // @[consts.scala:269:19] wire stq_0_bits_uop_uop_taken = 1'h0; // @[consts.scala:269:19] wire stq_0_bits_uop_uop_prs1_busy = 1'h0; // @[consts.scala:269:19] wire stq_0_bits_uop_uop_prs2_busy = 1'h0; // @[consts.scala:269:19] wire stq_0_bits_uop_uop_prs3_busy = 1'h0; // @[consts.scala:269:19] wire stq_0_bits_uop_uop_ppred_busy = 1'h0; // @[consts.scala:269:19] wire stq_0_bits_uop_uop_exception = 1'h0; // @[consts.scala:269:19] wire stq_0_bits_uop_uop_bypassable = 1'h0; // @[consts.scala:269:19] wire stq_0_bits_uop_uop_mem_signed = 1'h0; // @[consts.scala:269:19] wire stq_0_bits_uop_uop_is_fence = 1'h0; // @[consts.scala:269:19] wire stq_0_bits_uop_uop_is_fencei = 1'h0; // @[consts.scala:269:19] wire stq_0_bits_uop_uop_is_amo = 1'h0; // @[consts.scala:269:19] wire stq_0_bits_uop_uop_uses_ldq = 1'h0; // @[consts.scala:269:19] wire stq_0_bits_uop_uop_uses_stq = 1'h0; // @[consts.scala:269:19] wire stq_0_bits_uop_uop_is_sys_pc2epc = 1'h0; // @[consts.scala:269:19] wire stq_0_bits_uop_uop_is_unique = 1'h0; // @[consts.scala:269:19] wire stq_0_bits_uop_uop_flush_on_commit = 1'h0; // @[consts.scala:269:19] wire stq_0_bits_uop_uop_ldst_is_rs1 = 1'h0; // @[consts.scala:269:19] wire stq_0_bits_uop_uop_ldst_val = 1'h0; // @[consts.scala:269:19] wire stq_0_bits_uop_uop_frs3_en = 1'h0; // @[consts.scala:269:19] wire stq_0_bits_uop_uop_fp_val = 1'h0; // @[consts.scala:269:19] wire stq_0_bits_uop_uop_fp_single = 1'h0; // @[consts.scala:269:19] wire stq_0_bits_uop_uop_xcpt_pf_if = 1'h0; // @[consts.scala:269:19] wire stq_0_bits_uop_uop_xcpt_ae_if = 1'h0; // @[consts.scala:269:19] wire stq_0_bits_uop_uop_xcpt_ma_if = 1'h0; // @[consts.scala:269:19] wire stq_0_bits_uop_uop_bp_debug_if = 1'h0; // @[consts.scala:269:19] wire stq_0_bits_uop_uop_bp_xcpt_if = 1'h0; // @[consts.scala:269:19] wire stq_0_bits_uop_cs_fcn_dw = 1'h0; // @[consts.scala:279:18] wire stq_0_bits_uop_cs_is_load = 1'h0; // @[consts.scala:279:18] wire stq_0_bits_uop_cs_is_sta = 1'h0; // @[consts.scala:279:18] wire stq_0_bits_uop_cs_is_std = 1'h0; // @[consts.scala:279:18] wire stq_1_bits_uop_uop_is_rvc = 1'h0; // @[consts.scala:269:19] wire stq_1_bits_uop_uop_ctrl_fcn_dw = 1'h0; // @[consts.scala:269:19] wire stq_1_bits_uop_uop_ctrl_is_load = 1'h0; // @[consts.scala:269:19] wire stq_1_bits_uop_uop_ctrl_is_sta = 1'h0; // @[consts.scala:269:19] wire stq_1_bits_uop_uop_ctrl_is_std = 1'h0; // @[consts.scala:269:19] wire stq_1_bits_uop_uop_iw_p1_poisoned = 1'h0; // @[consts.scala:269:19] wire stq_1_bits_uop_uop_iw_p2_poisoned = 1'h0; // @[consts.scala:269:19] wire stq_1_bits_uop_uop_is_br = 1'h0; // @[consts.scala:269:19] wire stq_1_bits_uop_uop_is_jalr = 1'h0; // @[consts.scala:269:19] wire stq_1_bits_uop_uop_is_jal = 1'h0; // @[consts.scala:269:19] wire stq_1_bits_uop_uop_is_sfb = 1'h0; // @[consts.scala:269:19] wire stq_1_bits_uop_uop_edge_inst = 1'h0; // @[consts.scala:269:19] wire stq_1_bits_uop_uop_taken = 1'h0; // @[consts.scala:269:19] wire stq_1_bits_uop_uop_prs1_busy = 1'h0; // @[consts.scala:269:19] wire stq_1_bits_uop_uop_prs2_busy = 1'h0; // @[consts.scala:269:19] wire stq_1_bits_uop_uop_prs3_busy = 1'h0; // @[consts.scala:269:19] wire stq_1_bits_uop_uop_ppred_busy = 1'h0; // @[consts.scala:269:19] wire stq_1_bits_uop_uop_exception = 1'h0; // @[consts.scala:269:19] wire stq_1_bits_uop_uop_bypassable = 1'h0; // @[consts.scala:269:19] wire stq_1_bits_uop_uop_mem_signed = 1'h0; // @[consts.scala:269:19] wire stq_1_bits_uop_uop_is_fence = 1'h0; // @[consts.scala:269:19] wire stq_1_bits_uop_uop_is_fencei = 1'h0; // @[consts.scala:269:19] wire stq_1_bits_uop_uop_is_amo = 1'h0; // @[consts.scala:269:19] wire stq_1_bits_uop_uop_uses_ldq = 1'h0; // @[consts.scala:269:19] wire stq_1_bits_uop_uop_uses_stq = 1'h0; // @[consts.scala:269:19] wire stq_1_bits_uop_uop_is_sys_pc2epc = 1'h0; // @[consts.scala:269:19] wire stq_1_bits_uop_uop_is_unique = 1'h0; // @[consts.scala:269:19] wire stq_1_bits_uop_uop_flush_on_commit = 1'h0; // @[consts.scala:269:19] wire stq_1_bits_uop_uop_ldst_is_rs1 = 1'h0; // @[consts.scala:269:19] wire stq_1_bits_uop_uop_ldst_val = 1'h0; // @[consts.scala:269:19] wire stq_1_bits_uop_uop_frs3_en = 1'h0; // @[consts.scala:269:19] wire stq_1_bits_uop_uop_fp_val = 1'h0; // @[consts.scala:269:19] wire stq_1_bits_uop_uop_fp_single = 1'h0; // @[consts.scala:269:19] wire stq_1_bits_uop_uop_xcpt_pf_if = 1'h0; // @[consts.scala:269:19] wire stq_1_bits_uop_uop_xcpt_ae_if = 1'h0; // @[consts.scala:269:19] wire stq_1_bits_uop_uop_xcpt_ma_if = 1'h0; // @[consts.scala:269:19] wire stq_1_bits_uop_uop_bp_debug_if = 1'h0; // @[consts.scala:269:19] wire stq_1_bits_uop_uop_bp_xcpt_if = 1'h0; // @[consts.scala:269:19] wire stq_1_bits_uop_cs_fcn_dw = 1'h0; // @[consts.scala:279:18] wire stq_1_bits_uop_cs_is_load = 1'h0; // @[consts.scala:279:18] wire stq_1_bits_uop_cs_is_sta = 1'h0; // @[consts.scala:279:18] wire stq_1_bits_uop_cs_is_std = 1'h0; // @[consts.scala:279:18] wire stq_2_bits_uop_uop_is_rvc = 1'h0; // @[consts.scala:269:19] wire stq_2_bits_uop_uop_ctrl_fcn_dw = 1'h0; // @[consts.scala:269:19] wire stq_2_bits_uop_uop_ctrl_is_load = 1'h0; // @[consts.scala:269:19] wire stq_2_bits_uop_uop_ctrl_is_sta = 1'h0; // @[consts.scala:269:19] wire stq_2_bits_uop_uop_ctrl_is_std = 1'h0; // @[consts.scala:269:19] wire stq_2_bits_uop_uop_iw_p1_poisoned = 1'h0; // @[consts.scala:269:19] wire stq_2_bits_uop_uop_iw_p2_poisoned = 1'h0; // @[consts.scala:269:19] wire stq_2_bits_uop_uop_is_br = 1'h0; // @[consts.scala:269:19] wire stq_2_bits_uop_uop_is_jalr = 1'h0; // @[consts.scala:269:19] wire stq_2_bits_uop_uop_is_jal = 1'h0; // @[consts.scala:269:19] wire stq_2_bits_uop_uop_is_sfb = 1'h0; // @[consts.scala:269:19] wire stq_2_bits_uop_uop_edge_inst = 1'h0; // @[consts.scala:269:19] wire stq_2_bits_uop_uop_taken = 1'h0; // @[consts.scala:269:19] wire stq_2_bits_uop_uop_prs1_busy = 1'h0; // @[consts.scala:269:19] wire stq_2_bits_uop_uop_prs2_busy = 1'h0; // @[consts.scala:269:19] wire stq_2_bits_uop_uop_prs3_busy = 1'h0; // @[consts.scala:269:19] wire stq_2_bits_uop_uop_ppred_busy = 1'h0; // @[consts.scala:269:19] wire stq_2_bits_uop_uop_exception = 1'h0; // @[consts.scala:269:19] wire stq_2_bits_uop_uop_bypassable = 1'h0; // @[consts.scala:269:19] wire stq_2_bits_uop_uop_mem_signed = 1'h0; // @[consts.scala:269:19] wire stq_2_bits_uop_uop_is_fence = 1'h0; // @[consts.scala:269:19] wire stq_2_bits_uop_uop_is_fencei = 1'h0; // @[consts.scala:269:19] wire stq_2_bits_uop_uop_is_amo = 1'h0; // @[consts.scala:269:19] wire stq_2_bits_uop_uop_uses_ldq = 1'h0; // @[consts.scala:269:19] wire stq_2_bits_uop_uop_uses_stq = 1'h0; // @[consts.scala:269:19] wire stq_2_bits_uop_uop_is_sys_pc2epc = 1'h0; // @[consts.scala:269:19] wire stq_2_bits_uop_uop_is_unique = 1'h0; // @[consts.scala:269:19] wire stq_2_bits_uop_uop_flush_on_commit = 1'h0; // @[consts.scala:269:19] wire stq_2_bits_uop_uop_ldst_is_rs1 = 1'h0; // @[consts.scala:269:19] wire stq_2_bits_uop_uop_ldst_val = 1'h0; // @[consts.scala:269:19] wire stq_2_bits_uop_uop_frs3_en = 1'h0; // @[consts.scala:269:19] wire stq_2_bits_uop_uop_fp_val = 1'h0; // @[consts.scala:269:19] wire stq_2_bits_uop_uop_fp_single = 1'h0; // @[consts.scala:269:19] wire stq_2_bits_uop_uop_xcpt_pf_if = 1'h0; // @[consts.scala:269:19] wire stq_2_bits_uop_uop_xcpt_ae_if = 1'h0; // @[consts.scala:269:19] wire stq_2_bits_uop_uop_xcpt_ma_if = 1'h0; // @[consts.scala:269:19] wire stq_2_bits_uop_uop_bp_debug_if = 1'h0; // @[consts.scala:269:19] wire stq_2_bits_uop_uop_bp_xcpt_if = 1'h0; // @[consts.scala:269:19] wire stq_2_bits_uop_cs_fcn_dw = 1'h0; // @[consts.scala:279:18] wire stq_2_bits_uop_cs_is_load = 1'h0; // @[consts.scala:279:18] wire stq_2_bits_uop_cs_is_sta = 1'h0; // @[consts.scala:279:18] wire stq_2_bits_uop_cs_is_std = 1'h0; // @[consts.scala:279:18] wire stq_3_bits_uop_uop_is_rvc = 1'h0; // @[consts.scala:269:19] wire stq_3_bits_uop_uop_ctrl_fcn_dw = 1'h0; // @[consts.scala:269:19] wire stq_3_bits_uop_uop_ctrl_is_load = 1'h0; // @[consts.scala:269:19] wire stq_3_bits_uop_uop_ctrl_is_sta = 1'h0; // @[consts.scala:269:19] wire stq_3_bits_uop_uop_ctrl_is_std = 1'h0; // @[consts.scala:269:19] wire stq_3_bits_uop_uop_iw_p1_poisoned = 1'h0; // @[consts.scala:269:19] wire stq_3_bits_uop_uop_iw_p2_poisoned = 1'h0; // @[consts.scala:269:19] wire stq_3_bits_uop_uop_is_br = 1'h0; // @[consts.scala:269:19] wire stq_3_bits_uop_uop_is_jalr = 1'h0; // @[consts.scala:269:19] wire stq_3_bits_uop_uop_is_jal = 1'h0; // @[consts.scala:269:19] wire stq_3_bits_uop_uop_is_sfb = 1'h0; // @[consts.scala:269:19] wire stq_3_bits_uop_uop_edge_inst = 1'h0; // @[consts.scala:269:19] wire stq_3_bits_uop_uop_taken = 1'h0; // @[consts.scala:269:19] wire stq_3_bits_uop_uop_prs1_busy = 1'h0; // @[consts.scala:269:19] wire stq_3_bits_uop_uop_prs2_busy = 1'h0; // @[consts.scala:269:19] wire stq_3_bits_uop_uop_prs3_busy = 1'h0; // @[consts.scala:269:19] wire stq_3_bits_uop_uop_ppred_busy = 1'h0; // @[consts.scala:269:19] wire stq_3_bits_uop_uop_exception = 1'h0; // @[consts.scala:269:19] wire stq_3_bits_uop_uop_bypassable = 1'h0; // @[consts.scala:269:19] wire stq_3_bits_uop_uop_mem_signed = 1'h0; // @[consts.scala:269:19] wire stq_3_bits_uop_uop_is_fence = 1'h0; // @[consts.scala:269:19] wire stq_3_bits_uop_uop_is_fencei = 1'h0; // @[consts.scala:269:19] wire stq_3_bits_uop_uop_is_amo = 1'h0; // @[consts.scala:269:19] wire stq_3_bits_uop_uop_uses_ldq = 1'h0; // @[consts.scala:269:19] wire stq_3_bits_uop_uop_uses_stq = 1'h0; // @[consts.scala:269:19] wire stq_3_bits_uop_uop_is_sys_pc2epc = 1'h0; // @[consts.scala:269:19] wire stq_3_bits_uop_uop_is_unique = 1'h0; // @[consts.scala:269:19] wire stq_3_bits_uop_uop_flush_on_commit = 1'h0; // @[consts.scala:269:19] wire stq_3_bits_uop_uop_ldst_is_rs1 = 1'h0; // @[consts.scala:269:19] wire stq_3_bits_uop_uop_ldst_val = 1'h0; // @[consts.scala:269:19] wire stq_3_bits_uop_uop_frs3_en = 1'h0; // @[consts.scala:269:19] wire stq_3_bits_uop_uop_fp_val = 1'h0; // @[consts.scala:269:19] wire stq_3_bits_uop_uop_fp_single = 1'h0; // @[consts.scala:269:19] wire stq_3_bits_uop_uop_xcpt_pf_if = 1'h0; // @[consts.scala:269:19] wire stq_3_bits_uop_uop_xcpt_ae_if = 1'h0; // @[consts.scala:269:19] wire stq_3_bits_uop_uop_xcpt_ma_if = 1'h0; // @[consts.scala:269:19] wire stq_3_bits_uop_uop_bp_debug_if = 1'h0; // @[consts.scala:269:19] wire stq_3_bits_uop_uop_bp_xcpt_if = 1'h0; // @[consts.scala:269:19] wire stq_3_bits_uop_cs_fcn_dw = 1'h0; // @[consts.scala:279:18] wire stq_3_bits_uop_cs_is_load = 1'h0; // @[consts.scala:279:18] wire stq_3_bits_uop_cs_is_sta = 1'h0; // @[consts.scala:279:18] wire stq_3_bits_uop_cs_is_std = 1'h0; // @[consts.scala:279:18] wire stq_4_bits_uop_uop_is_rvc = 1'h0; // @[consts.scala:269:19] wire stq_4_bits_uop_uop_ctrl_fcn_dw = 1'h0; // @[consts.scala:269:19] wire stq_4_bits_uop_uop_ctrl_is_load = 1'h0; // @[consts.scala:269:19] wire stq_4_bits_uop_uop_ctrl_is_sta = 1'h0; // @[consts.scala:269:19] wire stq_4_bits_uop_uop_ctrl_is_std = 1'h0; // @[consts.scala:269:19] wire stq_4_bits_uop_uop_iw_p1_poisoned = 1'h0; // @[consts.scala:269:19] wire stq_4_bits_uop_uop_iw_p2_poisoned = 1'h0; // @[consts.scala:269:19] wire stq_4_bits_uop_uop_is_br = 1'h0; // @[consts.scala:269:19] wire stq_4_bits_uop_uop_is_jalr = 1'h0; // @[consts.scala:269:19] wire stq_4_bits_uop_uop_is_jal = 1'h0; // @[consts.scala:269:19] wire stq_4_bits_uop_uop_is_sfb = 1'h0; // @[consts.scala:269:19] wire stq_4_bits_uop_uop_edge_inst = 1'h0; // @[consts.scala:269:19] wire stq_4_bits_uop_uop_taken = 1'h0; // @[consts.scala:269:19] wire stq_4_bits_uop_uop_prs1_busy = 1'h0; // @[consts.scala:269:19] wire stq_4_bits_uop_uop_prs2_busy = 1'h0; // @[consts.scala:269:19] wire stq_4_bits_uop_uop_prs3_busy = 1'h0; // @[consts.scala:269:19] wire stq_4_bits_uop_uop_ppred_busy = 1'h0; // @[consts.scala:269:19] wire stq_4_bits_uop_uop_exception = 1'h0; // @[consts.scala:269:19] wire stq_4_bits_uop_uop_bypassable = 1'h0; // @[consts.scala:269:19] wire stq_4_bits_uop_uop_mem_signed = 1'h0; // @[consts.scala:269:19] wire stq_4_bits_uop_uop_is_fence = 1'h0; // @[consts.scala:269:19] wire stq_4_bits_uop_uop_is_fencei = 1'h0; // @[consts.scala:269:19] wire stq_4_bits_uop_uop_is_amo = 1'h0; // @[consts.scala:269:19] wire stq_4_bits_uop_uop_uses_ldq = 1'h0; // @[consts.scala:269:19] wire stq_4_bits_uop_uop_uses_stq = 1'h0; // @[consts.scala:269:19] wire stq_4_bits_uop_uop_is_sys_pc2epc = 1'h0; // @[consts.scala:269:19] wire stq_4_bits_uop_uop_is_unique = 1'h0; // @[consts.scala:269:19] wire stq_4_bits_uop_uop_flush_on_commit = 1'h0; // @[consts.scala:269:19] wire stq_4_bits_uop_uop_ldst_is_rs1 = 1'h0; // @[consts.scala:269:19] wire stq_4_bits_uop_uop_ldst_val = 1'h0; // @[consts.scala:269:19] wire stq_4_bits_uop_uop_frs3_en = 1'h0; // @[consts.scala:269:19] wire stq_4_bits_uop_uop_fp_val = 1'h0; // @[consts.scala:269:19] wire stq_4_bits_uop_uop_fp_single = 1'h0; // @[consts.scala:269:19] wire stq_4_bits_uop_uop_xcpt_pf_if = 1'h0; // @[consts.scala:269:19] wire stq_4_bits_uop_uop_xcpt_ae_if = 1'h0; // @[consts.scala:269:19] wire stq_4_bits_uop_uop_xcpt_ma_if = 1'h0; // @[consts.scala:269:19] wire stq_4_bits_uop_uop_bp_debug_if = 1'h0; // @[consts.scala:269:19] wire stq_4_bits_uop_uop_bp_xcpt_if = 1'h0; // @[consts.scala:269:19] wire stq_4_bits_uop_cs_fcn_dw = 1'h0; // @[consts.scala:279:18] wire stq_4_bits_uop_cs_is_load = 1'h0; // @[consts.scala:279:18] wire stq_4_bits_uop_cs_is_sta = 1'h0; // @[consts.scala:279:18] wire stq_4_bits_uop_cs_is_std = 1'h0; // @[consts.scala:279:18] wire stq_5_bits_uop_uop_is_rvc = 1'h0; // @[consts.scala:269:19] wire stq_5_bits_uop_uop_ctrl_fcn_dw = 1'h0; // @[consts.scala:269:19] wire stq_5_bits_uop_uop_ctrl_is_load = 1'h0; // @[consts.scala:269:19] wire stq_5_bits_uop_uop_ctrl_is_sta = 1'h0; // @[consts.scala:269:19] wire stq_5_bits_uop_uop_ctrl_is_std = 1'h0; // @[consts.scala:269:19] wire stq_5_bits_uop_uop_iw_p1_poisoned = 1'h0; // @[consts.scala:269:19] wire stq_5_bits_uop_uop_iw_p2_poisoned = 1'h0; // @[consts.scala:269:19] wire stq_5_bits_uop_uop_is_br = 1'h0; // @[consts.scala:269:19] wire stq_5_bits_uop_uop_is_jalr = 1'h0; // @[consts.scala:269:19] wire stq_5_bits_uop_uop_is_jal = 1'h0; // @[consts.scala:269:19] wire stq_5_bits_uop_uop_is_sfb = 1'h0; // @[consts.scala:269:19] wire stq_5_bits_uop_uop_edge_inst = 1'h0; // @[consts.scala:269:19] wire stq_5_bits_uop_uop_taken = 1'h0; // @[consts.scala:269:19] wire stq_5_bits_uop_uop_prs1_busy = 1'h0; // @[consts.scala:269:19] wire stq_5_bits_uop_uop_prs2_busy = 1'h0; // @[consts.scala:269:19] wire stq_5_bits_uop_uop_prs3_busy = 1'h0; // @[consts.scala:269:19] wire stq_5_bits_uop_uop_ppred_busy = 1'h0; // @[consts.scala:269:19] wire stq_5_bits_uop_uop_exception = 1'h0; // @[consts.scala:269:19] wire stq_5_bits_uop_uop_bypassable = 1'h0; // @[consts.scala:269:19] wire stq_5_bits_uop_uop_mem_signed = 1'h0; // @[consts.scala:269:19] wire stq_5_bits_uop_uop_is_fence = 1'h0; // @[consts.scala:269:19] wire stq_5_bits_uop_uop_is_fencei = 1'h0; // @[consts.scala:269:19] wire stq_5_bits_uop_uop_is_amo = 1'h0; // @[consts.scala:269:19] wire stq_5_bits_uop_uop_uses_ldq = 1'h0; // @[consts.scala:269:19] wire stq_5_bits_uop_uop_uses_stq = 1'h0; // @[consts.scala:269:19] wire stq_5_bits_uop_uop_is_sys_pc2epc = 1'h0; // @[consts.scala:269:19] wire stq_5_bits_uop_uop_is_unique = 1'h0; // @[consts.scala:269:19] wire stq_5_bits_uop_uop_flush_on_commit = 1'h0; // @[consts.scala:269:19] wire stq_5_bits_uop_uop_ldst_is_rs1 = 1'h0; // @[consts.scala:269:19] wire stq_5_bits_uop_uop_ldst_val = 1'h0; // @[consts.scala:269:19] wire stq_5_bits_uop_uop_frs3_en = 1'h0; // @[consts.scala:269:19] wire stq_5_bits_uop_uop_fp_val = 1'h0; // @[consts.scala:269:19] wire stq_5_bits_uop_uop_fp_single = 1'h0; // @[consts.scala:269:19] wire stq_5_bits_uop_uop_xcpt_pf_if = 1'h0; // @[consts.scala:269:19] wire stq_5_bits_uop_uop_xcpt_ae_if = 1'h0; // @[consts.scala:269:19] wire stq_5_bits_uop_uop_xcpt_ma_if = 1'h0; // @[consts.scala:269:19] wire stq_5_bits_uop_uop_bp_debug_if = 1'h0; // @[consts.scala:269:19] wire stq_5_bits_uop_uop_bp_xcpt_if = 1'h0; // @[consts.scala:269:19] wire stq_5_bits_uop_cs_fcn_dw = 1'h0; // @[consts.scala:279:18] wire stq_5_bits_uop_cs_is_load = 1'h0; // @[consts.scala:279:18] wire stq_5_bits_uop_cs_is_sta = 1'h0; // @[consts.scala:279:18] wire stq_5_bits_uop_cs_is_std = 1'h0; // @[consts.scala:279:18] wire stq_6_bits_uop_uop_is_rvc = 1'h0; // @[consts.scala:269:19] wire stq_6_bits_uop_uop_ctrl_fcn_dw = 1'h0; // @[consts.scala:269:19] wire stq_6_bits_uop_uop_ctrl_is_load = 1'h0; // @[consts.scala:269:19] wire stq_6_bits_uop_uop_ctrl_is_sta = 1'h0; // @[consts.scala:269:19] wire stq_6_bits_uop_uop_ctrl_is_std = 1'h0; // @[consts.scala:269:19] wire stq_6_bits_uop_uop_iw_p1_poisoned = 1'h0; // @[consts.scala:269:19] wire stq_6_bits_uop_uop_iw_p2_poisoned = 1'h0; // @[consts.scala:269:19] wire stq_6_bits_uop_uop_is_br = 1'h0; // @[consts.scala:269:19] wire stq_6_bits_uop_uop_is_jalr = 1'h0; // @[consts.scala:269:19] wire stq_6_bits_uop_uop_is_jal = 1'h0; // @[consts.scala:269:19] wire stq_6_bits_uop_uop_is_sfb = 1'h0; // @[consts.scala:269:19] wire stq_6_bits_uop_uop_edge_inst = 1'h0; // @[consts.scala:269:19] wire stq_6_bits_uop_uop_taken = 1'h0; // @[consts.scala:269:19] wire stq_6_bits_uop_uop_prs1_busy = 1'h0; // @[consts.scala:269:19] wire stq_6_bits_uop_uop_prs2_busy = 1'h0; // @[consts.scala:269:19] wire stq_6_bits_uop_uop_prs3_busy = 1'h0; // @[consts.scala:269:19] wire stq_6_bits_uop_uop_ppred_busy = 1'h0; // @[consts.scala:269:19] wire stq_6_bits_uop_uop_exception = 1'h0; // @[consts.scala:269:19] wire stq_6_bits_uop_uop_bypassable = 1'h0; // @[consts.scala:269:19] wire stq_6_bits_uop_uop_mem_signed = 1'h0; // @[consts.scala:269:19] wire stq_6_bits_uop_uop_is_fence = 1'h0; // @[consts.scala:269:19] wire stq_6_bits_uop_uop_is_fencei = 1'h0; // @[consts.scala:269:19] wire stq_6_bits_uop_uop_is_amo = 1'h0; // @[consts.scala:269:19] wire stq_6_bits_uop_uop_uses_ldq = 1'h0; // @[consts.scala:269:19] wire stq_6_bits_uop_uop_uses_stq = 1'h0; // @[consts.scala:269:19] wire stq_6_bits_uop_uop_is_sys_pc2epc = 1'h0; // @[consts.scala:269:19] wire stq_6_bits_uop_uop_is_unique = 1'h0; // @[consts.scala:269:19] wire stq_6_bits_uop_uop_flush_on_commit = 1'h0; // @[consts.scala:269:19] wire stq_6_bits_uop_uop_ldst_is_rs1 = 1'h0; // @[consts.scala:269:19] wire stq_6_bits_uop_uop_ldst_val = 1'h0; // @[consts.scala:269:19] wire stq_6_bits_uop_uop_frs3_en = 1'h0; // @[consts.scala:269:19] wire stq_6_bits_uop_uop_fp_val = 1'h0; // @[consts.scala:269:19] wire stq_6_bits_uop_uop_fp_single = 1'h0; // @[consts.scala:269:19] wire stq_6_bits_uop_uop_xcpt_pf_if = 1'h0; // @[consts.scala:269:19] wire stq_6_bits_uop_uop_xcpt_ae_if = 1'h0; // @[consts.scala:269:19] wire stq_6_bits_uop_uop_xcpt_ma_if = 1'h0; // @[consts.scala:269:19] wire stq_6_bits_uop_uop_bp_debug_if = 1'h0; // @[consts.scala:269:19] wire stq_6_bits_uop_uop_bp_xcpt_if = 1'h0; // @[consts.scala:269:19] wire stq_6_bits_uop_cs_fcn_dw = 1'h0; // @[consts.scala:279:18] wire stq_6_bits_uop_cs_is_load = 1'h0; // @[consts.scala:279:18] wire stq_6_bits_uop_cs_is_sta = 1'h0; // @[consts.scala:279:18] wire stq_6_bits_uop_cs_is_std = 1'h0; // @[consts.scala:279:18] wire stq_7_bits_uop_uop_is_rvc = 1'h0; // @[consts.scala:269:19] wire stq_7_bits_uop_uop_ctrl_fcn_dw = 1'h0; // @[consts.scala:269:19] wire stq_7_bits_uop_uop_ctrl_is_load = 1'h0; // @[consts.scala:269:19] wire stq_7_bits_uop_uop_ctrl_is_sta = 1'h0; // @[consts.scala:269:19] wire stq_7_bits_uop_uop_ctrl_is_std = 1'h0; // @[consts.scala:269:19] wire stq_7_bits_uop_uop_iw_p1_poisoned = 1'h0; // @[consts.scala:269:19] wire stq_7_bits_uop_uop_iw_p2_poisoned = 1'h0; // @[consts.scala:269:19] wire stq_7_bits_uop_uop_is_br = 1'h0; // @[consts.scala:269:19] wire stq_7_bits_uop_uop_is_jalr = 1'h0; // @[consts.scala:269:19] wire stq_7_bits_uop_uop_is_jal = 1'h0; // @[consts.scala:269:19] wire stq_7_bits_uop_uop_is_sfb = 1'h0; // @[consts.scala:269:19] wire stq_7_bits_uop_uop_edge_inst = 1'h0; // @[consts.scala:269:19] wire stq_7_bits_uop_uop_taken = 1'h0; // @[consts.scala:269:19] wire stq_7_bits_uop_uop_prs1_busy = 1'h0; // @[consts.scala:269:19] wire stq_7_bits_uop_uop_prs2_busy = 1'h0; // @[consts.scala:269:19] wire stq_7_bits_uop_uop_prs3_busy = 1'h0; // @[consts.scala:269:19] wire stq_7_bits_uop_uop_ppred_busy = 1'h0; // @[consts.scala:269:19] wire stq_7_bits_uop_uop_exception = 1'h0; // @[consts.scala:269:19] wire stq_7_bits_uop_uop_bypassable = 1'h0; // @[consts.scala:269:19] wire stq_7_bits_uop_uop_mem_signed = 1'h0; // @[consts.scala:269:19] wire stq_7_bits_uop_uop_is_fence = 1'h0; // @[consts.scala:269:19] wire stq_7_bits_uop_uop_is_fencei = 1'h0; // @[consts.scala:269:19] wire stq_7_bits_uop_uop_is_amo = 1'h0; // @[consts.scala:269:19] wire stq_7_bits_uop_uop_uses_ldq = 1'h0; // @[consts.scala:269:19] wire stq_7_bits_uop_uop_uses_stq = 1'h0; // @[consts.scala:269:19] wire stq_7_bits_uop_uop_is_sys_pc2epc = 1'h0; // @[consts.scala:269:19] wire stq_7_bits_uop_uop_is_unique = 1'h0; // @[consts.scala:269:19] wire stq_7_bits_uop_uop_flush_on_commit = 1'h0; // @[consts.scala:269:19] wire stq_7_bits_uop_uop_ldst_is_rs1 = 1'h0; // @[consts.scala:269:19] wire stq_7_bits_uop_uop_ldst_val = 1'h0; // @[consts.scala:269:19] wire stq_7_bits_uop_uop_frs3_en = 1'h0; // @[consts.scala:269:19] wire stq_7_bits_uop_uop_fp_val = 1'h0; // @[consts.scala:269:19] wire stq_7_bits_uop_uop_fp_single = 1'h0; // @[consts.scala:269:19] wire stq_7_bits_uop_uop_xcpt_pf_if = 1'h0; // @[consts.scala:269:19] wire stq_7_bits_uop_uop_xcpt_ae_if = 1'h0; // @[consts.scala:269:19] wire stq_7_bits_uop_uop_xcpt_ma_if = 1'h0; // @[consts.scala:269:19] wire stq_7_bits_uop_uop_bp_debug_if = 1'h0; // @[consts.scala:269:19] wire stq_7_bits_uop_uop_bp_xcpt_if = 1'h0; // @[consts.scala:269:19] wire stq_7_bits_uop_cs_fcn_dw = 1'h0; // @[consts.scala:279:18] wire stq_7_bits_uop_cs_is_load = 1'h0; // @[consts.scala:279:18] wire stq_7_bits_uop_cs_is_sta = 1'h0; // @[consts.scala:279:18] wire stq_7_bits_uop_cs_is_std = 1'h0; // @[consts.scala:279:18] wire [7:0] io_ptw_status_zero1 = 8'h0; // @[lsu.scala:201:7] wire [7:0] io_ptw_gstatus_zero1 = 8'h0; // @[lsu.scala:201:7] wire [7:0] io_core_exe_0_req_bits_fflags_bits_uop_br_mask = 8'h0; // @[lsu.scala:201:7] wire [7:0] io_core_exe_0_iresp_bits_fflags_bits_uop_br_mask = 8'h0; // @[lsu.scala:201:7] wire [7:0] io_core_exe_0_fresp_bits_fflags_bits_uop_br_mask = 8'h0; // @[lsu.scala:201:7] wire [7:0] io_hellacache_req_bits_mask = 8'h0; // @[lsu.scala:201:7] wire [7:0] io_hellacache_s1_data_mask = 8'h0; // @[lsu.scala:201:7] wire [7:0] io_hellacache_resp_bits_mask = 8'h0; // @[lsu.scala:201:7] wire [7:0] _exe_req_WIRE_0_bits_fflags_bits_uop_br_mask = 8'h0; // @[lsu.scala:383:33] wire [7:0] exe_req_0_bits_fflags_bits_uop_br_mask = 8'h0; // @[lsu.scala:383:25] wire [7:0] exe_tlb_uop_uop_br_mask = 8'h0; // @[consts.scala:269:19] wire [7:0] exe_tlb_uop_uop_1_br_mask = 8'h0; // @[consts.scala:269:19] wire [7:0] _exe_tlb_uop_T_3_br_mask = 8'h0; // @[lsu.scala:602:24] wire [7:0] dmem_req_0_bits_uop_uop_br_mask = 8'h0; // @[consts.scala:269:19] wire [7:0] _dmem_req_0_bits_data_T_16 = 8'h0; // @[AMOALU.scala:29:69] wire [7:0] _mem_ldq_e_WIRE_bits_uop_br_mask = 8'h0; // @[lsu.scala:918:90] wire [7:0] _mem_ldq_e_WIRE_bits_st_dep_mask = 8'h0; // @[lsu.scala:918:90] wire [7:0] _mem_stq_e_WIRE_bits_uop_br_mask = 8'h0; // @[lsu.scala:922:89] wire [7:0] lcam_uop_uop_br_mask = 8'h0; // @[consts.scala:269:19] wire [7:0] stq_0_bits_uop_uop_br_mask = 8'h0; // @[consts.scala:269:19] wire [7:0] stq_1_bits_uop_uop_br_mask = 8'h0; // @[consts.scala:269:19] wire [7:0] stq_2_bits_uop_uop_br_mask = 8'h0; // @[consts.scala:269:19] wire [7:0] stq_3_bits_uop_uop_br_mask = 8'h0; // @[consts.scala:269:19] wire [7:0] stq_4_bits_uop_uop_br_mask = 8'h0; // @[consts.scala:269:19] wire [7:0] stq_5_bits_uop_uop_br_mask = 8'h0; // @[consts.scala:269:19] wire [7:0] stq_6_bits_uop_uop_br_mask = 8'h0; // @[consts.scala:269:19] wire [7:0] stq_7_bits_uop_uop_br_mask = 8'h0; // @[consts.scala:269:19] wire [1:0] io_ptw_status_xs = 2'h0; // @[lsu.scala:201:7] wire [1:0] io_ptw_status_vs = 2'h0; // @[lsu.scala:201:7] wire [1:0] io_ptw_hstatus_vsxl = 2'h0; // @[lsu.scala:201:7] wire [1:0] io_ptw_hstatus_zero3 = 2'h0; // @[lsu.scala:201:7] wire [1:0] io_ptw_hstatus_zero2 = 2'h0; // @[lsu.scala:201:7] wire [1:0] io_ptw_gstatus_dprv = 2'h0; // @[lsu.scala:201:7] wire [1:0] io_ptw_gstatus_prv = 2'h0; // @[lsu.scala:201:7] wire [1:0] io_ptw_gstatus_sxl = 2'h0; // @[lsu.scala:201:7] wire [1:0] io_ptw_gstatus_uxl = 2'h0; // @[lsu.scala:201:7] wire [1:0] io_ptw_gstatus_xs = 2'h0; // @[lsu.scala:201:7] wire [1:0] io_ptw_gstatus_fs = 2'h0; // @[lsu.scala:201:7] wire [1:0] io_ptw_gstatus_mpp = 2'h0; // @[lsu.scala:201:7] wire [1:0] io_ptw_gstatus_vs = 2'h0; // @[lsu.scala:201:7] wire [1:0] io_ptw_pmp_0_cfg_res = 2'h0; // @[lsu.scala:201:7] wire [1:0] io_ptw_pmp_1_cfg_res = 2'h0; // @[lsu.scala:201:7] wire [1:0] io_ptw_pmp_2_cfg_res = 2'h0; // @[lsu.scala:201:7] wire [1:0] io_ptw_pmp_3_cfg_res = 2'h0; // @[lsu.scala:201:7] wire [1:0] io_ptw_pmp_4_cfg_res = 2'h0; // @[lsu.scala:201:7] wire [1:0] io_ptw_pmp_5_cfg_res = 2'h0; // @[lsu.scala:201:7] wire [1:0] io_ptw_pmp_6_cfg_res = 2'h0; // @[lsu.scala:201:7] wire [1:0] io_ptw_pmp_7_cfg_res = 2'h0; // @[lsu.scala:201:7] wire [1:0] io_core_exe_0_req_bits_fflags_bits_uop_ctrl_op1_sel = 2'h0; // @[lsu.scala:201:7] wire [1:0] io_core_exe_0_req_bits_fflags_bits_uop_iw_state = 2'h0; // @[lsu.scala:201:7] wire [1:0] io_core_exe_0_req_bits_fflags_bits_uop_rxq_idx = 2'h0; // @[lsu.scala:201:7] wire [1:0] io_core_exe_0_req_bits_fflags_bits_uop_mem_size = 2'h0; // @[lsu.scala:201:7] wire [1:0] io_core_exe_0_req_bits_fflags_bits_uop_dst_rtype = 2'h0; // @[lsu.scala:201:7] wire [1:0] io_core_exe_0_req_bits_fflags_bits_uop_lrs1_rtype = 2'h0; // @[lsu.scala:201:7] wire [1:0] io_core_exe_0_req_bits_fflags_bits_uop_lrs2_rtype = 2'h0; // @[lsu.scala:201:7] wire [1:0] io_core_exe_0_req_bits_fflags_bits_uop_debug_fsrc = 2'h0; // @[lsu.scala:201:7] wire [1:0] io_core_exe_0_req_bits_fflags_bits_uop_debug_tsrc = 2'h0; // @[lsu.scala:201:7] wire [1:0] io_core_exe_0_iresp_bits_fflags_bits_uop_ctrl_op1_sel = 2'h0; // @[lsu.scala:201:7] wire [1:0] io_core_exe_0_iresp_bits_fflags_bits_uop_iw_state = 2'h0; // @[lsu.scala:201:7] wire [1:0] io_core_exe_0_iresp_bits_fflags_bits_uop_rxq_idx = 2'h0; // @[lsu.scala:201:7] wire [1:0] io_core_exe_0_iresp_bits_fflags_bits_uop_mem_size = 2'h0; // @[lsu.scala:201:7] wire [1:0] io_core_exe_0_iresp_bits_fflags_bits_uop_dst_rtype = 2'h0; // @[lsu.scala:201:7] wire [1:0] io_core_exe_0_iresp_bits_fflags_bits_uop_lrs1_rtype = 2'h0; // @[lsu.scala:201:7] wire [1:0] io_core_exe_0_iresp_bits_fflags_bits_uop_lrs2_rtype = 2'h0; // @[lsu.scala:201:7] wire [1:0] io_core_exe_0_iresp_bits_fflags_bits_uop_debug_fsrc = 2'h0; // @[lsu.scala:201:7] wire [1:0] io_core_exe_0_iresp_bits_fflags_bits_uop_debug_tsrc = 2'h0; // @[lsu.scala:201:7] wire [1:0] io_core_exe_0_fresp_bits_fflags_bits_uop_ctrl_op1_sel = 2'h0; // @[lsu.scala:201:7] wire [1:0] io_core_exe_0_fresp_bits_fflags_bits_uop_iw_state = 2'h0; // @[lsu.scala:201:7] wire [1:0] io_core_exe_0_fresp_bits_fflags_bits_uop_rxq_idx = 2'h0; // @[lsu.scala:201:7] wire [1:0] io_core_exe_0_fresp_bits_fflags_bits_uop_mem_size = 2'h0; // @[lsu.scala:201:7] wire [1:0] io_core_exe_0_fresp_bits_fflags_bits_uop_dst_rtype = 2'h0; // @[lsu.scala:201:7] wire [1:0] io_core_exe_0_fresp_bits_fflags_bits_uop_lrs1_rtype = 2'h0; // @[lsu.scala:201:7] wire [1:0] io_core_exe_0_fresp_bits_fflags_bits_uop_lrs2_rtype = 2'h0; // @[lsu.scala:201:7] wire [1:0] io_core_exe_0_fresp_bits_fflags_bits_uop_debug_fsrc = 2'h0; // @[lsu.scala:201:7] wire [1:0] io_core_exe_0_fresp_bits_fflags_bits_uop_debug_tsrc = 2'h0; // @[lsu.scala:201:7] wire [1:0] io_hellacache_resp_bits_dprv = 2'h0; // @[lsu.scala:201:7] wire [1:0] _exe_req_WIRE_0_bits_fflags_bits_uop_ctrl_op1_sel = 2'h0; // @[lsu.scala:383:33] wire [1:0] _exe_req_WIRE_0_bits_fflags_bits_uop_iw_state = 2'h0; // @[lsu.scala:383:33] wire [1:0] _exe_req_WIRE_0_bits_fflags_bits_uop_rxq_idx = 2'h0; // @[lsu.scala:383:33] wire [1:0] _exe_req_WIRE_0_bits_fflags_bits_uop_mem_size = 2'h0; // @[lsu.scala:383:33] wire [1:0] _exe_req_WIRE_0_bits_fflags_bits_uop_dst_rtype = 2'h0; // @[lsu.scala:383:33] wire [1:0] _exe_req_WIRE_0_bits_fflags_bits_uop_lrs1_rtype = 2'h0; // @[lsu.scala:383:33] wire [1:0] _exe_req_WIRE_0_bits_fflags_bits_uop_lrs2_rtype = 2'h0; // @[lsu.scala:383:33] wire [1:0] _exe_req_WIRE_0_bits_fflags_bits_uop_debug_fsrc = 2'h0; // @[lsu.scala:383:33] wire [1:0] _exe_req_WIRE_0_bits_fflags_bits_uop_debug_tsrc = 2'h0; // @[lsu.scala:383:33] wire [1:0] exe_req_0_bits_fflags_bits_uop_ctrl_op1_sel = 2'h0; // @[lsu.scala:383:25] wire [1:0] exe_req_0_bits_fflags_bits_uop_iw_state = 2'h0; // @[lsu.scala:383:25] wire [1:0] exe_req_0_bits_fflags_bits_uop_rxq_idx = 2'h0; // @[lsu.scala:383:25] wire [1:0] exe_req_0_bits_fflags_bits_uop_mem_size = 2'h0; // @[lsu.scala:383:25] wire [1:0] exe_req_0_bits_fflags_bits_uop_dst_rtype = 2'h0; // @[lsu.scala:383:25] wire [1:0] exe_req_0_bits_fflags_bits_uop_lrs1_rtype = 2'h0; // @[lsu.scala:383:25] wire [1:0] exe_req_0_bits_fflags_bits_uop_lrs2_rtype = 2'h0; // @[lsu.scala:383:25] wire [1:0] exe_req_0_bits_fflags_bits_uop_debug_fsrc = 2'h0; // @[lsu.scala:383:25] wire [1:0] exe_req_0_bits_fflags_bits_uop_debug_tsrc = 2'h0; // @[lsu.scala:383:25] wire [1:0] exe_tlb_uop_uop_ctrl_op1_sel = 2'h0; // @[consts.scala:269:19] wire [1:0] exe_tlb_uop_uop_iw_state = 2'h0; // @[consts.scala:269:19] wire [1:0] exe_tlb_uop_uop_rxq_idx = 2'h0; // @[consts.scala:269:19] wire [1:0] exe_tlb_uop_uop_mem_size = 2'h0; // @[consts.scala:269:19] wire [1:0] exe_tlb_uop_uop_lrs1_rtype = 2'h0; // @[consts.scala:269:19] wire [1:0] exe_tlb_uop_uop_lrs2_rtype = 2'h0; // @[consts.scala:269:19] wire [1:0] exe_tlb_uop_uop_debug_fsrc = 2'h0; // @[consts.scala:269:19] wire [1:0] exe_tlb_uop_uop_debug_tsrc = 2'h0; // @[consts.scala:269:19] wire [1:0] exe_tlb_uop_cs_op1_sel = 2'h0; // @[consts.scala:279:18] wire [1:0] exe_tlb_uop_uop_1_ctrl_op1_sel = 2'h0; // @[consts.scala:269:19] wire [1:0] exe_tlb_uop_uop_1_iw_state = 2'h0; // @[consts.scala:269:19] wire [1:0] exe_tlb_uop_uop_1_rxq_idx = 2'h0; // @[consts.scala:269:19] wire [1:0] exe_tlb_uop_uop_1_mem_size = 2'h0; // @[consts.scala:269:19] wire [1:0] exe_tlb_uop_uop_1_lrs1_rtype = 2'h0; // @[consts.scala:269:19] wire [1:0] exe_tlb_uop_uop_1_lrs2_rtype = 2'h0; // @[consts.scala:269:19] wire [1:0] exe_tlb_uop_uop_1_debug_fsrc = 2'h0; // @[consts.scala:269:19] wire [1:0] exe_tlb_uop_uop_1_debug_tsrc = 2'h0; // @[consts.scala:269:19] wire [1:0] exe_tlb_uop_cs_1_op1_sel = 2'h0; // @[consts.scala:279:18] wire [1:0] _exe_tlb_uop_T_3_ctrl_op1_sel = 2'h0; // @[lsu.scala:602:24] wire [1:0] _exe_tlb_uop_T_3_iw_state = 2'h0; // @[lsu.scala:602:24] wire [1:0] _exe_tlb_uop_T_3_rxq_idx = 2'h0; // @[lsu.scala:602:24] wire [1:0] _exe_tlb_uop_T_3_mem_size = 2'h0; // @[lsu.scala:602:24] wire [1:0] _exe_tlb_uop_T_3_lrs1_rtype = 2'h0; // @[lsu.scala:602:24] wire [1:0] _exe_tlb_uop_T_3_lrs2_rtype = 2'h0; // @[lsu.scala:602:24] wire [1:0] _exe_tlb_uop_T_3_debug_fsrc = 2'h0; // @[lsu.scala:602:24] wire [1:0] _exe_tlb_uop_T_3_debug_tsrc = 2'h0; // @[lsu.scala:602:24] wire [1:0] dmem_req_0_bits_uop_uop_ctrl_op1_sel = 2'h0; // @[consts.scala:269:19] wire [1:0] dmem_req_0_bits_uop_uop_iw_state = 2'h0; // @[consts.scala:269:19] wire [1:0] dmem_req_0_bits_uop_uop_rxq_idx = 2'h0; // @[consts.scala:269:19] wire [1:0] dmem_req_0_bits_uop_uop_mem_size = 2'h0; // @[consts.scala:269:19] wire [1:0] dmem_req_0_bits_uop_uop_lrs1_rtype = 2'h0; // @[consts.scala:269:19] wire [1:0] dmem_req_0_bits_uop_uop_lrs2_rtype = 2'h0; // @[consts.scala:269:19] wire [1:0] dmem_req_0_bits_uop_uop_debug_fsrc = 2'h0; // @[consts.scala:269:19] wire [1:0] dmem_req_0_bits_uop_uop_debug_tsrc = 2'h0; // @[consts.scala:269:19] wire [1:0] dmem_req_0_bits_uop_cs_op1_sel = 2'h0; // @[consts.scala:279:18] wire [1:0] _mem_ldq_e_WIRE_bits_uop_ctrl_op1_sel = 2'h0; // @[lsu.scala:918:90] wire [1:0] _mem_ldq_e_WIRE_bits_uop_iw_state = 2'h0; // @[lsu.scala:918:90] wire [1:0] _mem_ldq_e_WIRE_bits_uop_rxq_idx = 2'h0; // @[lsu.scala:918:90] wire [1:0] _mem_ldq_e_WIRE_bits_uop_mem_size = 2'h0; // @[lsu.scala:918:90] wire [1:0] _mem_ldq_e_WIRE_bits_uop_dst_rtype = 2'h0; // @[lsu.scala:918:90] wire [1:0] _mem_ldq_e_WIRE_bits_uop_lrs1_rtype = 2'h0; // @[lsu.scala:918:90] wire [1:0] _mem_ldq_e_WIRE_bits_uop_lrs2_rtype = 2'h0; // @[lsu.scala:918:90] wire [1:0] _mem_ldq_e_WIRE_bits_uop_debug_fsrc = 2'h0; // @[lsu.scala:918:90] wire [1:0] _mem_ldq_e_WIRE_bits_uop_debug_tsrc = 2'h0; // @[lsu.scala:918:90] wire [1:0] _mem_stq_e_WIRE_bits_uop_ctrl_op1_sel = 2'h0; // @[lsu.scala:922:89] wire [1:0] _mem_stq_e_WIRE_bits_uop_iw_state = 2'h0; // @[lsu.scala:922:89] wire [1:0] _mem_stq_e_WIRE_bits_uop_rxq_idx = 2'h0; // @[lsu.scala:922:89] wire [1:0] _mem_stq_e_WIRE_bits_uop_mem_size = 2'h0; // @[lsu.scala:922:89] wire [1:0] _mem_stq_e_WIRE_bits_uop_dst_rtype = 2'h0; // @[lsu.scala:922:89] wire [1:0] _mem_stq_e_WIRE_bits_uop_lrs1_rtype = 2'h0; // @[lsu.scala:922:89] wire [1:0] _mem_stq_e_WIRE_bits_uop_lrs2_rtype = 2'h0; // @[lsu.scala:922:89] wire [1:0] _mem_stq_e_WIRE_bits_uop_debug_fsrc = 2'h0; // @[lsu.scala:922:89] wire [1:0] _mem_stq_e_WIRE_bits_uop_debug_tsrc = 2'h0; // @[lsu.scala:922:89] wire [1:0] lcam_uop_uop_ctrl_op1_sel = 2'h0; // @[consts.scala:269:19] wire [1:0] lcam_uop_uop_iw_state = 2'h0; // @[consts.scala:269:19] wire [1:0] lcam_uop_uop_rxq_idx = 2'h0; // @[consts.scala:269:19] wire [1:0] lcam_uop_uop_mem_size = 2'h0; // @[consts.scala:269:19] wire [1:0] lcam_uop_uop_lrs1_rtype = 2'h0; // @[consts.scala:269:19] wire [1:0] lcam_uop_uop_lrs2_rtype = 2'h0; // @[consts.scala:269:19] wire [1:0] lcam_uop_uop_debug_fsrc = 2'h0; // @[consts.scala:269:19] wire [1:0] lcam_uop_uop_debug_tsrc = 2'h0; // @[consts.scala:269:19] wire [1:0] lcam_uop_cs_op1_sel = 2'h0; // @[consts.scala:279:18] wire [1:0] stq_0_bits_uop_uop_ctrl_op1_sel = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_0_bits_uop_uop_iw_state = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_0_bits_uop_uop_rxq_idx = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_0_bits_uop_uop_mem_size = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_0_bits_uop_uop_lrs1_rtype = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_0_bits_uop_uop_lrs2_rtype = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_0_bits_uop_uop_debug_fsrc = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_0_bits_uop_uop_debug_tsrc = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_0_bits_uop_cs_op1_sel = 2'h0; // @[consts.scala:279:18] wire [1:0] stq_1_bits_uop_uop_ctrl_op1_sel = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_1_bits_uop_uop_iw_state = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_1_bits_uop_uop_rxq_idx = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_1_bits_uop_uop_mem_size = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_1_bits_uop_uop_lrs1_rtype = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_1_bits_uop_uop_lrs2_rtype = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_1_bits_uop_uop_debug_fsrc = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_1_bits_uop_uop_debug_tsrc = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_1_bits_uop_cs_op1_sel = 2'h0; // @[consts.scala:279:18] wire [1:0] stq_2_bits_uop_uop_ctrl_op1_sel = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_2_bits_uop_uop_iw_state = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_2_bits_uop_uop_rxq_idx = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_2_bits_uop_uop_mem_size = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_2_bits_uop_uop_lrs1_rtype = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_2_bits_uop_uop_lrs2_rtype = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_2_bits_uop_uop_debug_fsrc = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_2_bits_uop_uop_debug_tsrc = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_2_bits_uop_cs_op1_sel = 2'h0; // @[consts.scala:279:18] wire [1:0] stq_3_bits_uop_uop_ctrl_op1_sel = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_3_bits_uop_uop_iw_state = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_3_bits_uop_uop_rxq_idx = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_3_bits_uop_uop_mem_size = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_3_bits_uop_uop_lrs1_rtype = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_3_bits_uop_uop_lrs2_rtype = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_3_bits_uop_uop_debug_fsrc = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_3_bits_uop_uop_debug_tsrc = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_3_bits_uop_cs_op1_sel = 2'h0; // @[consts.scala:279:18] wire [1:0] stq_4_bits_uop_uop_ctrl_op1_sel = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_4_bits_uop_uop_iw_state = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_4_bits_uop_uop_rxq_idx = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_4_bits_uop_uop_mem_size = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_4_bits_uop_uop_lrs1_rtype = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_4_bits_uop_uop_lrs2_rtype = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_4_bits_uop_uop_debug_fsrc = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_4_bits_uop_uop_debug_tsrc = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_4_bits_uop_cs_op1_sel = 2'h0; // @[consts.scala:279:18] wire [1:0] stq_5_bits_uop_uop_ctrl_op1_sel = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_5_bits_uop_uop_iw_state = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_5_bits_uop_uop_rxq_idx = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_5_bits_uop_uop_mem_size = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_5_bits_uop_uop_lrs1_rtype = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_5_bits_uop_uop_lrs2_rtype = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_5_bits_uop_uop_debug_fsrc = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_5_bits_uop_uop_debug_tsrc = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_5_bits_uop_cs_op1_sel = 2'h0; // @[consts.scala:279:18] wire [1:0] stq_6_bits_uop_uop_ctrl_op1_sel = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_6_bits_uop_uop_iw_state = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_6_bits_uop_uop_rxq_idx = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_6_bits_uop_uop_mem_size = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_6_bits_uop_uop_lrs1_rtype = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_6_bits_uop_uop_lrs2_rtype = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_6_bits_uop_uop_debug_fsrc = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_6_bits_uop_uop_debug_tsrc = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_6_bits_uop_cs_op1_sel = 2'h0; // @[consts.scala:279:18] wire [1:0] stq_7_bits_uop_uop_ctrl_op1_sel = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_7_bits_uop_uop_iw_state = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_7_bits_uop_uop_rxq_idx = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_7_bits_uop_uop_mem_size = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_7_bits_uop_uop_lrs1_rtype = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_7_bits_uop_uop_lrs2_rtype = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_7_bits_uop_uop_debug_fsrc = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_7_bits_uop_uop_debug_tsrc = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_7_bits_uop_cs_op1_sel = 2'h0; // @[consts.scala:279:18] wire [6:0] io_core_exe_0_req_bits_fflags_bits_uop_uopc = 7'h0; // @[lsu.scala:201:7] wire [6:0] io_core_exe_0_iresp_bits_fflags_bits_uop_uopc = 7'h0; // @[lsu.scala:201:7] wire [6:0] io_core_exe_0_fresp_bits_fflags_bits_uop_uopc = 7'h0; // @[lsu.scala:201:7] wire [6:0] io_hellacache_req_bits_tag = 7'h0; // @[lsu.scala:201:7] wire [6:0] io_hellacache_resp_bits_tag = 7'h0; // @[lsu.scala:201:7] wire [6:0] _exe_req_WIRE_0_bits_fflags_bits_uop_uopc = 7'h0; // @[lsu.scala:383:33] wire [6:0] exe_req_0_bits_fflags_bits_uop_uopc = 7'h0; // @[lsu.scala:383:25] wire [6:0] exe_tlb_uop_uop_uopc = 7'h0; // @[consts.scala:269:19] wire [6:0] exe_tlb_uop_uop_1_uopc = 7'h0; // @[consts.scala:269:19] wire [6:0] _exe_tlb_uop_T_3_uopc = 7'h0; // @[lsu.scala:602:24] wire [6:0] dmem_req_0_bits_uop_uop_uopc = 7'h0; // @[consts.scala:269:19] wire [6:0] _mem_ldq_e_WIRE_bits_uop_uopc = 7'h0; // @[lsu.scala:918:90] wire [6:0] _mem_stq_e_WIRE_bits_uop_uopc = 7'h0; // @[lsu.scala:922:89] wire [6:0] lcam_uop_uop_uopc = 7'h0; // @[consts.scala:269:19] wire [6:0] stq_0_bits_uop_uop_uopc = 7'h0; // @[consts.scala:269:19] wire [6:0] stq_1_bits_uop_uop_uopc = 7'h0; // @[consts.scala:269:19] wire [6:0] stq_2_bits_uop_uop_uopc = 7'h0; // @[consts.scala:269:19] wire [6:0] stq_3_bits_uop_uop_uopc = 7'h0; // @[consts.scala:269:19] wire [6:0] stq_4_bits_uop_uop_uopc = 7'h0; // @[consts.scala:269:19] wire [6:0] stq_5_bits_uop_uop_uopc = 7'h0; // @[consts.scala:269:19] wire [6:0] stq_6_bits_uop_uop_uopc = 7'h0; // @[consts.scala:269:19] wire [6:0] stq_7_bits_uop_uop_uopc = 7'h0; // @[consts.scala:269:19] wire [4:0] io_ptw_hstatus_zero1 = 5'h0; // @[lsu.scala:201:7] wire [4:0] io_core_exe_0_req_bits_fflags_bits_uop_ctrl_op_fcn = 5'h0; // @[lsu.scala:201:7] wire [4:0] io_core_exe_0_req_bits_fflags_bits_uop_rob_idx = 5'h0; // @[lsu.scala:201:7] wire [4:0] io_core_exe_0_req_bits_fflags_bits_uop_mem_cmd = 5'h0; // @[lsu.scala:201:7] wire [4:0] io_core_exe_0_req_bits_fflags_bits_flags = 5'h0; // @[lsu.scala:201:7] wire [4:0] io_core_exe_0_iresp_bits_fflags_bits_uop_ctrl_op_fcn = 5'h0; // @[lsu.scala:201:7] wire [4:0] io_core_exe_0_iresp_bits_fflags_bits_uop_rob_idx = 5'h0; // @[lsu.scala:201:7] wire [4:0] io_core_exe_0_iresp_bits_fflags_bits_uop_mem_cmd = 5'h0; // @[lsu.scala:201:7] wire [4:0] io_core_exe_0_iresp_bits_fflags_bits_flags = 5'h0; // @[lsu.scala:201:7] wire [4:0] io_core_exe_0_fresp_bits_fflags_bits_uop_ctrl_op_fcn = 5'h0; // @[lsu.scala:201:7] wire [4:0] io_core_exe_0_fresp_bits_fflags_bits_uop_rob_idx = 5'h0; // @[lsu.scala:201:7] wire [4:0] io_core_exe_0_fresp_bits_fflags_bits_uop_mem_cmd = 5'h0; // @[lsu.scala:201:7] wire [4:0] io_core_exe_0_fresp_bits_fflags_bits_flags = 5'h0; // @[lsu.scala:201:7] wire [4:0] io_hellacache_req_bits_cmd = 5'h0; // @[lsu.scala:201:7] wire [4:0] io_hellacache_resp_bits_cmd = 5'h0; // @[lsu.scala:201:7] wire [4:0] _exe_req_WIRE_0_bits_fflags_bits_uop_ctrl_op_fcn = 5'h0; // @[lsu.scala:383:33] wire [4:0] _exe_req_WIRE_0_bits_fflags_bits_uop_rob_idx = 5'h0; // @[lsu.scala:383:33] wire [4:0] _exe_req_WIRE_0_bits_fflags_bits_uop_mem_cmd = 5'h0; // @[lsu.scala:383:33] wire [4:0] _exe_req_WIRE_0_bits_fflags_bits_flags = 5'h0; // @[lsu.scala:383:33] wire [4:0] exe_req_0_bits_fflags_bits_uop_ctrl_op_fcn = 5'h0; // @[lsu.scala:383:25] wire [4:0] exe_req_0_bits_fflags_bits_uop_rob_idx = 5'h0; // @[lsu.scala:383:25] wire [4:0] exe_req_0_bits_fflags_bits_uop_mem_cmd = 5'h0; // @[lsu.scala:383:25] wire [4:0] exe_req_0_bits_fflags_bits_flags = 5'h0; // @[lsu.scala:383:25] wire [4:0] exe_tlb_uop_uop_ctrl_op_fcn = 5'h0; // @[consts.scala:269:19] wire [4:0] exe_tlb_uop_uop_rob_idx = 5'h0; // @[consts.scala:269:19] wire [4:0] exe_tlb_uop_uop_mem_cmd = 5'h0; // @[consts.scala:269:19] wire [4:0] exe_tlb_uop_cs_op_fcn = 5'h0; // @[consts.scala:279:18] wire [4:0] exe_tlb_uop_uop_1_ctrl_op_fcn = 5'h0; // @[consts.scala:269:19] wire [4:0] exe_tlb_uop_uop_1_rob_idx = 5'h0; // @[consts.scala:269:19] wire [4:0] exe_tlb_uop_uop_1_mem_cmd = 5'h0; // @[consts.scala:269:19] wire [4:0] exe_tlb_uop_cs_1_op_fcn = 5'h0; // @[consts.scala:279:18] wire [4:0] _exe_tlb_uop_T_3_ctrl_op_fcn = 5'h0; // @[lsu.scala:602:24] wire [4:0] _exe_tlb_uop_T_3_rob_idx = 5'h0; // @[lsu.scala:602:24] wire [4:0] _exe_tlb_uop_T_3_mem_cmd = 5'h0; // @[lsu.scala:602:24] wire [4:0] _exe_cmd_T_5 = 5'h0; // @[lsu.scala:638:23] wire [4:0] dmem_req_0_bits_uop_uop_ctrl_op_fcn = 5'h0; // @[consts.scala:269:19] wire [4:0] dmem_req_0_bits_uop_uop_rob_idx = 5'h0; // @[consts.scala:269:19] wire [4:0] dmem_req_0_bits_uop_uop_mem_cmd = 5'h0; // @[consts.scala:269:19] wire [4:0] dmem_req_0_bits_uop_cs_op_fcn = 5'h0; // @[consts.scala:279:18] wire [4:0] _mem_ldq_e_WIRE_bits_uop_ctrl_op_fcn = 5'h0; // @[lsu.scala:918:90] wire [4:0] _mem_ldq_e_WIRE_bits_uop_rob_idx = 5'h0; // @[lsu.scala:918:90] wire [4:0] _mem_ldq_e_WIRE_bits_uop_mem_cmd = 5'h0; // @[lsu.scala:918:90] wire [4:0] _mem_stq_e_WIRE_bits_uop_ctrl_op_fcn = 5'h0; // @[lsu.scala:922:89] wire [4:0] _mem_stq_e_WIRE_bits_uop_rob_idx = 5'h0; // @[lsu.scala:922:89] wire [4:0] _mem_stq_e_WIRE_bits_uop_mem_cmd = 5'h0; // @[lsu.scala:922:89] wire [4:0] lcam_uop_uop_ctrl_op_fcn = 5'h0; // @[consts.scala:269:19] wire [4:0] lcam_uop_uop_rob_idx = 5'h0; // @[consts.scala:269:19] wire [4:0] lcam_uop_uop_mem_cmd = 5'h0; // @[consts.scala:269:19] wire [4:0] lcam_uop_cs_op_fcn = 5'h0; // @[consts.scala:279:18] wire [4:0] stq_0_bits_uop_uop_ctrl_op_fcn = 5'h0; // @[consts.scala:269:19] wire [4:0] stq_0_bits_uop_uop_rob_idx = 5'h0; // @[consts.scala:269:19] wire [4:0] stq_0_bits_uop_uop_mem_cmd = 5'h0; // @[consts.scala:269:19] wire [4:0] stq_0_bits_uop_cs_op_fcn = 5'h0; // @[consts.scala:279:18] wire [4:0] stq_1_bits_uop_uop_ctrl_op_fcn = 5'h0; // @[consts.scala:269:19] wire [4:0] stq_1_bits_uop_uop_rob_idx = 5'h0; // @[consts.scala:269:19] wire [4:0] stq_1_bits_uop_uop_mem_cmd = 5'h0; // @[consts.scala:269:19] wire [4:0] stq_1_bits_uop_cs_op_fcn = 5'h0; // @[consts.scala:279:18] wire [4:0] stq_2_bits_uop_uop_ctrl_op_fcn = 5'h0; // @[consts.scala:269:19] wire [4:0] stq_2_bits_uop_uop_rob_idx = 5'h0; // @[consts.scala:269:19] wire [4:0] stq_2_bits_uop_uop_mem_cmd = 5'h0; // @[consts.scala:269:19] wire [4:0] stq_2_bits_uop_cs_op_fcn = 5'h0; // @[consts.scala:279:18] wire [4:0] stq_3_bits_uop_uop_ctrl_op_fcn = 5'h0; // @[consts.scala:269:19] wire [4:0] stq_3_bits_uop_uop_rob_idx = 5'h0; // @[consts.scala:269:19] wire [4:0] stq_3_bits_uop_uop_mem_cmd = 5'h0; // @[consts.scala:269:19] wire [4:0] stq_3_bits_uop_cs_op_fcn = 5'h0; // @[consts.scala:279:18] wire [4:0] stq_4_bits_uop_uop_ctrl_op_fcn = 5'h0; // @[consts.scala:269:19] wire [4:0] stq_4_bits_uop_uop_rob_idx = 5'h0; // @[consts.scala:269:19] wire [4:0] stq_4_bits_uop_uop_mem_cmd = 5'h0; // @[consts.scala:269:19] wire [4:0] stq_4_bits_uop_cs_op_fcn = 5'h0; // @[consts.scala:279:18] wire [4:0] stq_5_bits_uop_uop_ctrl_op_fcn = 5'h0; // @[consts.scala:269:19] wire [4:0] stq_5_bits_uop_uop_rob_idx = 5'h0; // @[consts.scala:269:19] wire [4:0] stq_5_bits_uop_uop_mem_cmd = 5'h0; // @[consts.scala:269:19] wire [4:0] stq_5_bits_uop_cs_op_fcn = 5'h0; // @[consts.scala:279:18] wire [4:0] stq_6_bits_uop_uop_ctrl_op_fcn = 5'h0; // @[consts.scala:269:19] wire [4:0] stq_6_bits_uop_uop_rob_idx = 5'h0; // @[consts.scala:269:19] wire [4:0] stq_6_bits_uop_uop_mem_cmd = 5'h0; // @[consts.scala:269:19] wire [4:0] stq_6_bits_uop_cs_op_fcn = 5'h0; // @[consts.scala:279:18] wire [4:0] stq_7_bits_uop_uop_ctrl_op_fcn = 5'h0; // @[consts.scala:269:19] wire [4:0] stq_7_bits_uop_uop_rob_idx = 5'h0; // @[consts.scala:269:19] wire [4:0] stq_7_bits_uop_uop_mem_cmd = 5'h0; // @[consts.scala:269:19] wire [4:0] stq_7_bits_uop_cs_op_fcn = 5'h0; // @[consts.scala:279:18] wire [1:0] io_hellacache_req_bits_size = 2'h3; // @[lsu.scala:201:7] wire [1:0] io_hellacache_resp_bits_size = 2'h3; // @[lsu.scala:201:7] wire [1:0] dmem_req_0_bits_data_size_1 = 2'h3; // @[AMOALU.scala:11:18] wire [1:0] dmem_req_0_bits_data_size_2 = 2'h3; // @[AMOALU.scala:11:18] wire io_core_exe_0_iresp_ready = 1'h1; // @[lsu.scala:201:7] wire io_core_exe_0_fresp_ready = 1'h1; // @[lsu.scala:201:7] wire io_hellacache_req_bits_phys = 1'h1; // @[lsu.scala:201:7] wire _ldq_retry_idx_temp_vec_T_7 = 1'h1; // @[util.scala:351:72] wire _stq_retry_idx_temp_vec_T_7 = 1'h1; // @[util.scala:351:72] wire _ldq_wakeup_idx_temp_vec_T_7 = 1'h1; // @[util.scala:351:72] wire _can_fire_sta_retry_T_7 = 1'h1; // @[lsu.scala:482:34] wire _will_fire_load_incoming_0_will_fire_T_2 = 1'h1; // @[lsu.scala:533:35] wire _will_fire_load_incoming_0_will_fire_T_6 = 1'h1; // @[lsu.scala:534:35] wire _will_fire_load_incoming_0_will_fire_T_10 = 1'h1; // @[lsu.scala:535:35] wire _will_fire_load_incoming_0_will_fire_T_14 = 1'h1; // @[lsu.scala:536:35] wire _will_fire_load_incoming_0_T_10 = 1'h1; // @[lsu.scala:540:34] wire _will_fire_load_incoming_0_T_11 = 1'h1; // @[lsu.scala:540:31] wire _will_fire_stad_incoming_0_will_fire_T_10 = 1'h1; // @[lsu.scala:535:35] wire _will_fire_stad_incoming_0_will_fire_T_14 = 1'h1; // @[lsu.scala:536:35] wire _will_fire_stad_incoming_0_T_7 = 1'h1; // @[lsu.scala:539:34] wire _will_fire_sta_incoming_0_will_fire_T_10 = 1'h1; // @[lsu.scala:535:35] wire _will_fire_sta_incoming_0_T_7 = 1'h1; // @[lsu.scala:539:34] wire _will_fire_std_incoming_0_will_fire_T_2 = 1'h1; // @[lsu.scala:533:35] wire _will_fire_std_incoming_0_will_fire_T_6 = 1'h1; // @[lsu.scala:534:35] wire _will_fire_std_incoming_0_will_fire_T_10 = 1'h1; // @[lsu.scala:535:35] wire _will_fire_std_incoming_0_T_1 = 1'h1; // @[lsu.scala:537:34] wire _will_fire_std_incoming_0_T_4 = 1'h1; // @[lsu.scala:538:34] wire _will_fire_std_incoming_0_T_7 = 1'h1; // @[lsu.scala:539:34] wire _will_fire_sfence_0_will_fire_T_6 = 1'h1; // @[lsu.scala:534:35] wire _will_fire_sfence_0_will_fire_T_10 = 1'h1; // @[lsu.scala:535:35] wire _will_fire_sfence_0_T_4 = 1'h1; // @[lsu.scala:538:34] wire _will_fire_sfence_0_T_7 = 1'h1; // @[lsu.scala:539:34] wire _will_fire_release_0_will_fire_T_2 = 1'h1; // @[lsu.scala:533:35] wire _will_fire_release_0_will_fire_T_10 = 1'h1; // @[lsu.scala:535:35] wire _will_fire_release_0_will_fire_T_14 = 1'h1; // @[lsu.scala:536:35] wire _will_fire_release_0_T_1 = 1'h1; // @[lsu.scala:537:34] wire _will_fire_release_0_T_7 = 1'h1; // @[lsu.scala:539:34] wire _will_fire_release_0_T_10 = 1'h1; // @[lsu.scala:540:34] wire _will_fire_hella_incoming_0_will_fire_T_6 = 1'h1; // @[lsu.scala:534:35] wire _will_fire_hella_incoming_0_will_fire_T_14 = 1'h1; // @[lsu.scala:536:35] wire _will_fire_hella_incoming_0_T_4 = 1'h1; // @[lsu.scala:538:34] wire _will_fire_hella_incoming_0_T_10 = 1'h1; // @[lsu.scala:540:34] wire _will_fire_hella_wakeup_0_will_fire_T_2 = 1'h1; // @[lsu.scala:533:35] wire _will_fire_hella_wakeup_0_will_fire_T_6 = 1'h1; // @[lsu.scala:534:35] wire _will_fire_hella_wakeup_0_will_fire_T_14 = 1'h1; // @[lsu.scala:536:35] wire _will_fire_hella_wakeup_0_T_1 = 1'h1; // @[lsu.scala:537:34] wire _will_fire_hella_wakeup_0_T_4 = 1'h1; // @[lsu.scala:538:34] wire _will_fire_hella_wakeup_0_T_10 = 1'h1; // @[lsu.scala:540:34] wire _will_fire_load_retry_0_will_fire_T_14 = 1'h1; // @[lsu.scala:536:35] wire _will_fire_load_retry_0_T_10 = 1'h1; // @[lsu.scala:540:34] wire _will_fire_sta_retry_0_will_fire_T_10 = 1'h1; // @[lsu.scala:535:35] wire _will_fire_sta_retry_0_T_7 = 1'h1; // @[lsu.scala:539:34] wire _will_fire_load_wakeup_0_will_fire_T_2 = 1'h1; // @[lsu.scala:533:35] wire _will_fire_load_wakeup_0_will_fire_T_14 = 1'h1; // @[lsu.scala:536:35] wire _will_fire_load_wakeup_0_T_1 = 1'h1; // @[lsu.scala:537:34] wire _will_fire_load_wakeup_0_T_10 = 1'h1; // @[lsu.scala:540:34] wire _will_fire_store_commit_0_will_fire_T_2 = 1'h1; // @[lsu.scala:533:35] wire _will_fire_store_commit_0_will_fire_T_6 = 1'h1; // @[lsu.scala:534:35] wire _will_fire_store_commit_0_will_fire_T_14 = 1'h1; // @[lsu.scala:536:35] wire _will_fire_store_commit_0_T_1 = 1'h1; // @[lsu.scala:537:34] wire _will_fire_store_commit_0_T_4 = 1'h1; // @[lsu.scala:538:34] wire _will_fire_store_commit_0_T_10 = 1'h1; // @[lsu.scala:540:34] wire _dmem_req_0_valid_T_8 = 1'h1; // @[lsu.scala:806:86] wire _temp_bits_T_14 = 1'h1; // @[lsu.scala:1230:28] wire [63:0] io_ptw_customCSRs_csrs_0_wdata = 64'h0; // @[lsu.scala:201:7] wire [63:0] io_ptw_customCSRs_csrs_0_value = 64'h0; // @[lsu.scala:201:7] wire [63:0] io_ptw_customCSRs_csrs_0_sdata = 64'h0; // @[lsu.scala:201:7] wire [63:0] io_ptw_customCSRs_csrs_1_wdata = 64'h0; // @[lsu.scala:201:7] wire [63:0] io_ptw_customCSRs_csrs_1_value = 64'h0; // @[lsu.scala:201:7] wire [63:0] io_ptw_customCSRs_csrs_1_sdata = 64'h0; // @[lsu.scala:201:7] wire [63:0] io_core_exe_0_req_bits_fflags_bits_uop_exc_cause = 64'h0; // @[lsu.scala:201:7] wire [63:0] io_core_exe_0_iresp_bits_fflags_bits_uop_exc_cause = 64'h0; // @[lsu.scala:201:7] wire [63:0] io_core_exe_0_fresp_bits_fflags_bits_uop_exc_cause = 64'h0; // @[lsu.scala:201:7] wire [63:0] io_hellacache_req_bits_data = 64'h0; // @[lsu.scala:201:7] wire [63:0] io_hellacache_s1_data_data = 64'h0; // @[lsu.scala:201:7] wire [63:0] io_hellacache_resp_bits_data_word_bypass = 64'h0; // @[lsu.scala:201:7] wire [63:0] io_hellacache_resp_bits_data_raw = 64'h0; // @[lsu.scala:201:7] wire [63:0] io_hellacache_resp_bits_store_data = 64'h0; // @[lsu.scala:201:7] wire [63:0] _exe_req_WIRE_0_bits_fflags_bits_uop_exc_cause = 64'h0; // @[lsu.scala:383:33] wire [63:0] exe_req_0_bits_fflags_bits_uop_exc_cause = 64'h0; // @[lsu.scala:383:25] wire [63:0] exe_tlb_uop_uop_exc_cause = 64'h0; // @[consts.scala:269:19] wire [63:0] exe_tlb_uop_uop_1_exc_cause = 64'h0; // @[consts.scala:269:19] wire [63:0] _exe_tlb_uop_T_3_exc_cause = 64'h0; // @[lsu.scala:602:24] wire [63:0] dmem_req_0_bits_uop_uop_exc_cause = 64'h0; // @[consts.scala:269:19] wire [63:0] _dmem_req_0_bits_data_T_19 = 64'h0; // @[AMOALU.scala:29:32] wire [63:0] _dmem_req_0_bits_data_T_23 = 64'h0; // @[AMOALU.scala:29:32] wire [63:0] _dmem_req_0_bits_data_T_26 = 64'h0; // @[AMOALU.scala:29:32] wire [63:0] _dmem_req_0_bits_data_T_27 = 64'h0; // @[AMOALU.scala:29:13] wire [63:0] _dmem_req_0_bits_data_T_28 = 64'h0; // @[AMOALU.scala:29:13] wire [63:0] _dmem_req_0_bits_data_T_29 = 64'h0; // @[AMOALU.scala:29:13] wire [63:0] _mem_ldq_e_WIRE_bits_uop_exc_cause = 64'h0; // @[lsu.scala:918:90] wire [63:0] _mem_ldq_e_WIRE_bits_debug_wb_data = 64'h0; // @[lsu.scala:918:90] wire [63:0] _mem_stq_e_WIRE_bits_uop_exc_cause = 64'h0; // @[lsu.scala:922:89] wire [63:0] _mem_stq_e_WIRE_bits_data_bits = 64'h0; // @[lsu.scala:922:89] wire [63:0] _mem_stq_e_WIRE_bits_debug_wb_data = 64'h0; // @[lsu.scala:922:89] wire [63:0] lcam_uop_uop_exc_cause = 64'h0; // @[consts.scala:269:19] wire [63:0] stq_0_bits_uop_uop_exc_cause = 64'h0; // @[consts.scala:269:19] wire [63:0] stq_1_bits_uop_uop_exc_cause = 64'h0; // @[consts.scala:269:19] wire [63:0] stq_2_bits_uop_uop_exc_cause = 64'h0; // @[consts.scala:269:19] wire [63:0] stq_3_bits_uop_uop_exc_cause = 64'h0; // @[consts.scala:269:19] wire [63:0] stq_4_bits_uop_uop_exc_cause = 64'h0; // @[consts.scala:269:19] wire [63:0] stq_5_bits_uop_uop_exc_cause = 64'h0; // @[consts.scala:269:19] wire [63:0] stq_6_bits_uop_uop_exc_cause = 64'h0; // @[consts.scala:269:19] wire [63:0] stq_7_bits_uop_uop_exc_cause = 64'h0; // @[consts.scala:269:19] wire [1:0] io_hellacache_req_bits_dprv = 2'h1; // @[lsu.scala:201:7] wire [3:0] io_ptw_hgatp_mode = 4'h0; // @[lsu.scala:201:7] wire [3:0] io_ptw_vsatp_mode = 4'h0; // @[lsu.scala:201:7] wire [3:0] io_core_exe_0_req_bits_fflags_bits_uop_ctrl_br_type = 4'h0; // @[lsu.scala:201:7] wire [3:0] io_core_exe_0_req_bits_fflags_bits_uop_ftq_idx = 4'h0; // @[lsu.scala:201:7] wire [3:0] io_core_exe_0_req_bits_fflags_bits_uop_ppred = 4'h0; // @[lsu.scala:201:7] wire [3:0] io_core_exe_0_iresp_bits_fflags_bits_uop_ctrl_br_type = 4'h0; // @[lsu.scala:201:7] wire [3:0] io_core_exe_0_iresp_bits_fflags_bits_uop_ftq_idx = 4'h0; // @[lsu.scala:201:7] wire [3:0] io_core_exe_0_iresp_bits_fflags_bits_uop_ppred = 4'h0; // @[lsu.scala:201:7] wire [3:0] io_core_exe_0_fresp_bits_uop_ppred_0 = 4'h0; // @[lsu.scala:201:7] wire [3:0] io_core_exe_0_fresp_bits_fflags_bits_uop_ctrl_br_type = 4'h0; // @[lsu.scala:201:7] wire [3:0] io_core_exe_0_fresp_bits_fflags_bits_uop_ftq_idx = 4'h0; // @[lsu.scala:201:7] wire [3:0] io_core_exe_0_fresp_bits_fflags_bits_uop_ppred = 4'h0; // @[lsu.scala:201:7] wire [3:0] io_core_dis_uops_0_bits_ppred = 4'h0; // @[lsu.scala:201:7] wire [3:0] _exe_req_WIRE_0_bits_fflags_bits_uop_ctrl_br_type = 4'h0; // @[lsu.scala:383:33] wire [3:0] _exe_req_WIRE_0_bits_fflags_bits_uop_ftq_idx = 4'h0; // @[lsu.scala:383:33] wire [3:0] _exe_req_WIRE_0_bits_fflags_bits_uop_ppred = 4'h0; // @[lsu.scala:383:33] wire [3:0] exe_req_0_bits_fflags_bits_uop_ctrl_br_type = 4'h0; // @[lsu.scala:383:25] wire [3:0] exe_req_0_bits_fflags_bits_uop_ftq_idx = 4'h0; // @[lsu.scala:383:25] wire [3:0] exe_req_0_bits_fflags_bits_uop_ppred = 4'h0; // @[lsu.scala:383:25] wire [3:0] ldq_incoming_e_0_bits_uop_ppred = 4'h0; // @[lsu.scala:263:49] wire [3:0] exe_tlb_uop_uop_ctrl_br_type = 4'h0; // @[consts.scala:269:19] wire [3:0] exe_tlb_uop_uop_ftq_idx = 4'h0; // @[consts.scala:269:19] wire [3:0] exe_tlb_uop_uop_ppred = 4'h0; // @[consts.scala:269:19] wire [3:0] exe_tlb_uop_cs_br_type = 4'h0; // @[consts.scala:279:18] wire [3:0] exe_tlb_uop_uop_1_ctrl_br_type = 4'h0; // @[consts.scala:269:19] wire [3:0] exe_tlb_uop_uop_1_ftq_idx = 4'h0; // @[consts.scala:269:19] wire [3:0] exe_tlb_uop_uop_1_ppred = 4'h0; // @[consts.scala:269:19] wire [3:0] exe_tlb_uop_cs_1_br_type = 4'h0; // @[consts.scala:279:18] wire [3:0] _exe_tlb_uop_T_3_ctrl_br_type = 4'h0; // @[lsu.scala:602:24] wire [3:0] _exe_tlb_uop_T_3_ftq_idx = 4'h0; // @[lsu.scala:602:24] wire [3:0] _exe_tlb_uop_T_3_ppred = 4'h0; // @[lsu.scala:602:24] wire [3:0] dmem_req_0_bits_uop_uop_ctrl_br_type = 4'h0; // @[consts.scala:269:19] wire [3:0] dmem_req_0_bits_uop_uop_ftq_idx = 4'h0; // @[consts.scala:269:19] wire [3:0] dmem_req_0_bits_uop_uop_ppred = 4'h0; // @[consts.scala:269:19] wire [3:0] dmem_req_0_bits_uop_cs_br_type = 4'h0; // @[consts.scala:279:18] wire [3:0] mem_ldq_wakeup_e_out_bits_uop_ppred = 4'h0; // @[util.scala:106:23] wire [3:0] mem_ldq_retry_e_out_bits_uop_ppred = 4'h0; // @[util.scala:106:23] wire [3:0] _mem_ldq_e_WIRE_bits_uop_ctrl_br_type = 4'h0; // @[lsu.scala:918:90] wire [3:0] _mem_ldq_e_WIRE_bits_uop_ftq_idx = 4'h0; // @[lsu.scala:918:90] wire [3:0] _mem_ldq_e_WIRE_bits_uop_ppred = 4'h0; // @[lsu.scala:918:90] wire [3:0] _mem_stq_e_WIRE_bits_uop_ctrl_br_type = 4'h0; // @[lsu.scala:922:89] wire [3:0] _mem_stq_e_WIRE_bits_uop_ftq_idx = 4'h0; // @[lsu.scala:922:89] wire [3:0] _mem_stq_e_WIRE_bits_uop_ppred = 4'h0; // @[lsu.scala:922:89] wire [3:0] lcam_uop_uop_ctrl_br_type = 4'h0; // @[consts.scala:269:19] wire [3:0] lcam_uop_uop_ftq_idx = 4'h0; // @[consts.scala:269:19] wire [3:0] lcam_uop_uop_ppred = 4'h0; // @[consts.scala:269:19] wire [3:0] lcam_uop_cs_br_type = 4'h0; // @[consts.scala:279:18] wire [3:0] stq_0_bits_uop_uop_ctrl_br_type = 4'h0; // @[consts.scala:269:19] wire [3:0] stq_0_bits_uop_uop_ftq_idx = 4'h0; // @[consts.scala:269:19] wire [3:0] stq_0_bits_uop_uop_ppred = 4'h0; // @[consts.scala:269:19] wire [3:0] stq_0_bits_uop_cs_br_type = 4'h0; // @[consts.scala:279:18] wire [3:0] stq_1_bits_uop_uop_ctrl_br_type = 4'h0; // @[consts.scala:269:19] wire [3:0] stq_1_bits_uop_uop_ftq_idx = 4'h0; // @[consts.scala:269:19] wire [3:0] stq_1_bits_uop_uop_ppred = 4'h0; // @[consts.scala:269:19] wire [3:0] stq_1_bits_uop_cs_br_type = 4'h0; // @[consts.scala:279:18] wire [3:0] stq_2_bits_uop_uop_ctrl_br_type = 4'h0; // @[consts.scala:269:19] wire [3:0] stq_2_bits_uop_uop_ftq_idx = 4'h0; // @[consts.scala:269:19] wire [3:0] stq_2_bits_uop_uop_ppred = 4'h0; // @[consts.scala:269:19] wire [3:0] stq_2_bits_uop_cs_br_type = 4'h0; // @[consts.scala:279:18] wire [3:0] stq_3_bits_uop_uop_ctrl_br_type = 4'h0; // @[consts.scala:269:19] wire [3:0] stq_3_bits_uop_uop_ftq_idx = 4'h0; // @[consts.scala:269:19] wire [3:0] stq_3_bits_uop_uop_ppred = 4'h0; // @[consts.scala:269:19] wire [3:0] stq_3_bits_uop_cs_br_type = 4'h0; // @[consts.scala:279:18] wire [3:0] stq_4_bits_uop_uop_ctrl_br_type = 4'h0; // @[consts.scala:269:19] wire [3:0] stq_4_bits_uop_uop_ftq_idx = 4'h0; // @[consts.scala:269:19] wire [3:0] stq_4_bits_uop_uop_ppred = 4'h0; // @[consts.scala:269:19] wire [3:0] stq_4_bits_uop_cs_br_type = 4'h0; // @[consts.scala:279:18] wire [3:0] stq_5_bits_uop_uop_ctrl_br_type = 4'h0; // @[consts.scala:269:19] wire [3:0] stq_5_bits_uop_uop_ftq_idx = 4'h0; // @[consts.scala:269:19] wire [3:0] stq_5_bits_uop_uop_ppred = 4'h0; // @[consts.scala:269:19] wire [3:0] stq_5_bits_uop_cs_br_type = 4'h0; // @[consts.scala:279:18] wire [3:0] stq_6_bits_uop_uop_ctrl_br_type = 4'h0; // @[consts.scala:269:19] wire [3:0] stq_6_bits_uop_uop_ftq_idx = 4'h0; // @[consts.scala:269:19] wire [3:0] stq_6_bits_uop_uop_ppred = 4'h0; // @[consts.scala:269:19] wire [3:0] stq_6_bits_uop_cs_br_type = 4'h0; // @[consts.scala:279:18] wire [3:0] stq_7_bits_uop_uop_ctrl_br_type = 4'h0; // @[consts.scala:269:19] wire [3:0] stq_7_bits_uop_uop_ftq_idx = 4'h0; // @[consts.scala:269:19] wire [3:0] stq_7_bits_uop_uop_ppred = 4'h0; // @[consts.scala:269:19] wire [3:0] stq_7_bits_uop_cs_br_type = 4'h0; // @[consts.scala:279:18] wire [43:0] io_ptw_hgatp_ppn = 44'h0; // @[lsu.scala:201:7] wire [43:0] io_ptw_vsatp_ppn = 44'h0; // @[lsu.scala:201:7] wire [1:0] io_ptw_status_sxl = 2'h2; // @[lsu.scala:201:7] wire [1:0] io_ptw_status_uxl = 2'h2; // @[lsu.scala:201:7] wire [1:0] exe_tlb_uop_uop_dst_rtype = 2'h2; // @[consts.scala:269:19] wire [1:0] exe_tlb_uop_uop_1_dst_rtype = 2'h2; // @[consts.scala:269:19] wire [1:0] _exe_tlb_uop_T_3_dst_rtype = 2'h2; // @[lsu.scala:602:24] wire [1:0] dmem_req_0_bits_uop_uop_dst_rtype = 2'h2; // @[consts.scala:269:19] wire [1:0] lcam_uop_uop_dst_rtype = 2'h2; // @[consts.scala:269:19] wire [1:0] stq_0_bits_uop_uop_dst_rtype = 2'h2; // @[consts.scala:269:19] wire [1:0] stq_1_bits_uop_uop_dst_rtype = 2'h2; // @[consts.scala:269:19] wire [1:0] stq_2_bits_uop_uop_dst_rtype = 2'h2; // @[consts.scala:269:19] wire [1:0] stq_3_bits_uop_uop_dst_rtype = 2'h2; // @[consts.scala:269:19] wire [1:0] stq_4_bits_uop_uop_dst_rtype = 2'h2; // @[consts.scala:269:19] wire [1:0] stq_5_bits_uop_uop_dst_rtype = 2'h2; // @[consts.scala:269:19] wire [1:0] stq_6_bits_uop_uop_dst_rtype = 2'h2; // @[consts.scala:269:19] wire [1:0] stq_7_bits_uop_uop_dst_rtype = 2'h2; // @[consts.scala:269:19] wire [29:0] io_ptw_hstatus_zero6 = 30'h0; // @[lsu.scala:201:7] wire [8:0] io_ptw_hstatus_zero5 = 9'h0; // @[lsu.scala:201:7] wire [5:0] io_ptw_hstatus_vgein = 6'h0; // @[lsu.scala:201:7] wire [5:0] io_core_exe_0_req_bits_fflags_bits_uop_pc_lob = 6'h0; // @[lsu.scala:201:7] wire [5:0] io_core_exe_0_req_bits_fflags_bits_uop_pdst = 6'h0; // @[lsu.scala:201:7] wire [5:0] io_core_exe_0_req_bits_fflags_bits_uop_prs1 = 6'h0; // @[lsu.scala:201:7] wire [5:0] io_core_exe_0_req_bits_fflags_bits_uop_prs2 = 6'h0; // @[lsu.scala:201:7] wire [5:0] io_core_exe_0_req_bits_fflags_bits_uop_prs3 = 6'h0; // @[lsu.scala:201:7] wire [5:0] io_core_exe_0_req_bits_fflags_bits_uop_stale_pdst = 6'h0; // @[lsu.scala:201:7] wire [5:0] io_core_exe_0_req_bits_fflags_bits_uop_ldst = 6'h0; // @[lsu.scala:201:7] wire [5:0] io_core_exe_0_req_bits_fflags_bits_uop_lrs1 = 6'h0; // @[lsu.scala:201:7] wire [5:0] io_core_exe_0_req_bits_fflags_bits_uop_lrs2 = 6'h0; // @[lsu.scala:201:7] wire [5:0] io_core_exe_0_req_bits_fflags_bits_uop_lrs3 = 6'h0; // @[lsu.scala:201:7] wire [5:0] io_core_exe_0_iresp_bits_fflags_bits_uop_pc_lob = 6'h0; // @[lsu.scala:201:7] wire [5:0] io_core_exe_0_iresp_bits_fflags_bits_uop_pdst = 6'h0; // @[lsu.scala:201:7] wire [5:0] io_core_exe_0_iresp_bits_fflags_bits_uop_prs1 = 6'h0; // @[lsu.scala:201:7] wire [5:0] io_core_exe_0_iresp_bits_fflags_bits_uop_prs2 = 6'h0; // @[lsu.scala:201:7] wire [5:0] io_core_exe_0_iresp_bits_fflags_bits_uop_prs3 = 6'h0; // @[lsu.scala:201:7] wire [5:0] io_core_exe_0_iresp_bits_fflags_bits_uop_stale_pdst = 6'h0; // @[lsu.scala:201:7] wire [5:0] io_core_exe_0_iresp_bits_fflags_bits_uop_ldst = 6'h0; // @[lsu.scala:201:7] wire [5:0] io_core_exe_0_iresp_bits_fflags_bits_uop_lrs1 = 6'h0; // @[lsu.scala:201:7] wire [5:0] io_core_exe_0_iresp_bits_fflags_bits_uop_lrs2 = 6'h0; // @[lsu.scala:201:7] wire [5:0] io_core_exe_0_iresp_bits_fflags_bits_uop_lrs3 = 6'h0; // @[lsu.scala:201:7] wire [5:0] io_core_exe_0_fresp_bits_fflags_bits_uop_pc_lob = 6'h0; // @[lsu.scala:201:7] wire [5:0] io_core_exe_0_fresp_bits_fflags_bits_uop_pdst = 6'h0; // @[lsu.scala:201:7] wire [5:0] io_core_exe_0_fresp_bits_fflags_bits_uop_prs1 = 6'h0; // @[lsu.scala:201:7] wire [5:0] io_core_exe_0_fresp_bits_fflags_bits_uop_prs2 = 6'h0; // @[lsu.scala:201:7] wire [5:0] io_core_exe_0_fresp_bits_fflags_bits_uop_prs3 = 6'h0; // @[lsu.scala:201:7] wire [5:0] io_core_exe_0_fresp_bits_fflags_bits_uop_stale_pdst = 6'h0; // @[lsu.scala:201:7] wire [5:0] io_core_exe_0_fresp_bits_fflags_bits_uop_ldst = 6'h0; // @[lsu.scala:201:7] wire [5:0] io_core_exe_0_fresp_bits_fflags_bits_uop_lrs1 = 6'h0; // @[lsu.scala:201:7] wire [5:0] io_core_exe_0_fresp_bits_fflags_bits_uop_lrs2 = 6'h0; // @[lsu.scala:201:7] wire [5:0] io_core_exe_0_fresp_bits_fflags_bits_uop_lrs3 = 6'h0; // @[lsu.scala:201:7] wire [5:0] _exe_req_WIRE_0_bits_fflags_bits_uop_pc_lob = 6'h0; // @[lsu.scala:383:33] wire [5:0] _exe_req_WIRE_0_bits_fflags_bits_uop_pdst = 6'h0; // @[lsu.scala:383:33] wire [5:0] _exe_req_WIRE_0_bits_fflags_bits_uop_prs1 = 6'h0; // @[lsu.scala:383:33] wire [5:0] _exe_req_WIRE_0_bits_fflags_bits_uop_prs2 = 6'h0; // @[lsu.scala:383:33] wire [5:0] _exe_req_WIRE_0_bits_fflags_bits_uop_prs3 = 6'h0; // @[lsu.scala:383:33] wire [5:0] _exe_req_WIRE_0_bits_fflags_bits_uop_stale_pdst = 6'h0; // @[lsu.scala:383:33] wire [5:0] _exe_req_WIRE_0_bits_fflags_bits_uop_ldst = 6'h0; // @[lsu.scala:383:33] wire [5:0] _exe_req_WIRE_0_bits_fflags_bits_uop_lrs1 = 6'h0; // @[lsu.scala:383:33] wire [5:0] _exe_req_WIRE_0_bits_fflags_bits_uop_lrs2 = 6'h0; // @[lsu.scala:383:33] wire [5:0] _exe_req_WIRE_0_bits_fflags_bits_uop_lrs3 = 6'h0; // @[lsu.scala:383:33] wire [5:0] exe_req_0_bits_fflags_bits_uop_pc_lob = 6'h0; // @[lsu.scala:383:25] wire [5:0] exe_req_0_bits_fflags_bits_uop_pdst = 6'h0; // @[lsu.scala:383:25] wire [5:0] exe_req_0_bits_fflags_bits_uop_prs1 = 6'h0; // @[lsu.scala:383:25] wire [5:0] exe_req_0_bits_fflags_bits_uop_prs2 = 6'h0; // @[lsu.scala:383:25] wire [5:0] exe_req_0_bits_fflags_bits_uop_prs3 = 6'h0; // @[lsu.scala:383:25] wire [5:0] exe_req_0_bits_fflags_bits_uop_stale_pdst = 6'h0; // @[lsu.scala:383:25] wire [5:0] exe_req_0_bits_fflags_bits_uop_ldst = 6'h0; // @[lsu.scala:383:25] wire [5:0] exe_req_0_bits_fflags_bits_uop_lrs1 = 6'h0; // @[lsu.scala:383:25] wire [5:0] exe_req_0_bits_fflags_bits_uop_lrs2 = 6'h0; // @[lsu.scala:383:25] wire [5:0] exe_req_0_bits_fflags_bits_uop_lrs3 = 6'h0; // @[lsu.scala:383:25] wire [5:0] exe_tlb_uop_uop_pc_lob = 6'h0; // @[consts.scala:269:19] wire [5:0] exe_tlb_uop_uop_pdst = 6'h0; // @[consts.scala:269:19] wire [5:0] exe_tlb_uop_uop_prs1 = 6'h0; // @[consts.scala:269:19] wire [5:0] exe_tlb_uop_uop_prs2 = 6'h0; // @[consts.scala:269:19] wire [5:0] exe_tlb_uop_uop_prs3 = 6'h0; // @[consts.scala:269:19] wire [5:0] exe_tlb_uop_uop_stale_pdst = 6'h0; // @[consts.scala:269:19] wire [5:0] exe_tlb_uop_uop_ldst = 6'h0; // @[consts.scala:269:19] wire [5:0] exe_tlb_uop_uop_lrs1 = 6'h0; // @[consts.scala:269:19] wire [5:0] exe_tlb_uop_uop_lrs2 = 6'h0; // @[consts.scala:269:19] wire [5:0] exe_tlb_uop_uop_lrs3 = 6'h0; // @[consts.scala:269:19] wire [5:0] exe_tlb_uop_uop_1_pc_lob = 6'h0; // @[consts.scala:269:19] wire [5:0] exe_tlb_uop_uop_1_pdst = 6'h0; // @[consts.scala:269:19] wire [5:0] exe_tlb_uop_uop_1_prs1 = 6'h0; // @[consts.scala:269:19] wire [5:0] exe_tlb_uop_uop_1_prs2 = 6'h0; // @[consts.scala:269:19] wire [5:0] exe_tlb_uop_uop_1_prs3 = 6'h0; // @[consts.scala:269:19] wire [5:0] exe_tlb_uop_uop_1_stale_pdst = 6'h0; // @[consts.scala:269:19] wire [5:0] exe_tlb_uop_uop_1_ldst = 6'h0; // @[consts.scala:269:19] wire [5:0] exe_tlb_uop_uop_1_lrs1 = 6'h0; // @[consts.scala:269:19] wire [5:0] exe_tlb_uop_uop_1_lrs2 = 6'h0; // @[consts.scala:269:19] wire [5:0] exe_tlb_uop_uop_1_lrs3 = 6'h0; // @[consts.scala:269:19] wire [5:0] _exe_tlb_uop_T_3_pc_lob = 6'h0; // @[lsu.scala:602:24] wire [5:0] _exe_tlb_uop_T_3_pdst = 6'h0; // @[lsu.scala:602:24] wire [5:0] _exe_tlb_uop_T_3_prs1 = 6'h0; // @[lsu.scala:602:24] wire [5:0] _exe_tlb_uop_T_3_prs2 = 6'h0; // @[lsu.scala:602:24] wire [5:0] _exe_tlb_uop_T_3_prs3 = 6'h0; // @[lsu.scala:602:24] wire [5:0] _exe_tlb_uop_T_3_stale_pdst = 6'h0; // @[lsu.scala:602:24] wire [5:0] _exe_tlb_uop_T_3_ldst = 6'h0; // @[lsu.scala:602:24] wire [5:0] _exe_tlb_uop_T_3_lrs1 = 6'h0; // @[lsu.scala:602:24] wire [5:0] _exe_tlb_uop_T_3_lrs2 = 6'h0; // @[lsu.scala:602:24] wire [5:0] _exe_tlb_uop_T_3_lrs3 = 6'h0; // @[lsu.scala:602:24] wire [5:0] dmem_req_0_bits_uop_uop_pc_lob = 6'h0; // @[consts.scala:269:19] wire [5:0] dmem_req_0_bits_uop_uop_pdst = 6'h0; // @[consts.scala:269:19] wire [5:0] dmem_req_0_bits_uop_uop_prs1 = 6'h0; // @[consts.scala:269:19] wire [5:0] dmem_req_0_bits_uop_uop_prs2 = 6'h0; // @[consts.scala:269:19] wire [5:0] dmem_req_0_bits_uop_uop_prs3 = 6'h0; // @[consts.scala:269:19] wire [5:0] dmem_req_0_bits_uop_uop_stale_pdst = 6'h0; // @[consts.scala:269:19] wire [5:0] dmem_req_0_bits_uop_uop_ldst = 6'h0; // @[consts.scala:269:19] wire [5:0] dmem_req_0_bits_uop_uop_lrs1 = 6'h0; // @[consts.scala:269:19] wire [5:0] dmem_req_0_bits_uop_uop_lrs2 = 6'h0; // @[consts.scala:269:19] wire [5:0] dmem_req_0_bits_uop_uop_lrs3 = 6'h0; // @[consts.scala:269:19] wire [5:0] _mem_ldq_e_WIRE_bits_uop_pc_lob = 6'h0; // @[lsu.scala:918:90] wire [5:0] _mem_ldq_e_WIRE_bits_uop_pdst = 6'h0; // @[lsu.scala:918:90] wire [5:0] _mem_ldq_e_WIRE_bits_uop_prs1 = 6'h0; // @[lsu.scala:918:90] wire [5:0] _mem_ldq_e_WIRE_bits_uop_prs2 = 6'h0; // @[lsu.scala:918:90] wire [5:0] _mem_ldq_e_WIRE_bits_uop_prs3 = 6'h0; // @[lsu.scala:918:90] wire [5:0] _mem_ldq_e_WIRE_bits_uop_stale_pdst = 6'h0; // @[lsu.scala:918:90] wire [5:0] _mem_ldq_e_WIRE_bits_uop_ldst = 6'h0; // @[lsu.scala:918:90] wire [5:0] _mem_ldq_e_WIRE_bits_uop_lrs1 = 6'h0; // @[lsu.scala:918:90] wire [5:0] _mem_ldq_e_WIRE_bits_uop_lrs2 = 6'h0; // @[lsu.scala:918:90] wire [5:0] _mem_ldq_e_WIRE_bits_uop_lrs3 = 6'h0; // @[lsu.scala:918:90] wire [5:0] _mem_stq_e_WIRE_bits_uop_pc_lob = 6'h0; // @[lsu.scala:922:89] wire [5:0] _mem_stq_e_WIRE_bits_uop_pdst = 6'h0; // @[lsu.scala:922:89] wire [5:0] _mem_stq_e_WIRE_bits_uop_prs1 = 6'h0; // @[lsu.scala:922:89] wire [5:0] _mem_stq_e_WIRE_bits_uop_prs2 = 6'h0; // @[lsu.scala:922:89] wire [5:0] _mem_stq_e_WIRE_bits_uop_prs3 = 6'h0; // @[lsu.scala:922:89] wire [5:0] _mem_stq_e_WIRE_bits_uop_stale_pdst = 6'h0; // @[lsu.scala:922:89] wire [5:0] _mem_stq_e_WIRE_bits_uop_ldst = 6'h0; // @[lsu.scala:922:89] wire [5:0] _mem_stq_e_WIRE_bits_uop_lrs1 = 6'h0; // @[lsu.scala:922:89] wire [5:0] _mem_stq_e_WIRE_bits_uop_lrs2 = 6'h0; // @[lsu.scala:922:89] wire [5:0] _mem_stq_e_WIRE_bits_uop_lrs3 = 6'h0; // @[lsu.scala:922:89] wire [5:0] lcam_uop_uop_pc_lob = 6'h0; // @[consts.scala:269:19] wire [5:0] lcam_uop_uop_pdst = 6'h0; // @[consts.scala:269:19] wire [5:0] lcam_uop_uop_prs1 = 6'h0; // @[consts.scala:269:19] wire [5:0] lcam_uop_uop_prs2 = 6'h0; // @[consts.scala:269:19] wire [5:0] lcam_uop_uop_prs3 = 6'h0; // @[consts.scala:269:19] wire [5:0] lcam_uop_uop_stale_pdst = 6'h0; // @[consts.scala:269:19] wire [5:0] lcam_uop_uop_ldst = 6'h0; // @[consts.scala:269:19] wire [5:0] lcam_uop_uop_lrs1 = 6'h0; // @[consts.scala:269:19] wire [5:0] lcam_uop_uop_lrs2 = 6'h0; // @[consts.scala:269:19] wire [5:0] lcam_uop_uop_lrs3 = 6'h0; // @[consts.scala:269:19] wire [5:0] stq_0_bits_uop_uop_pc_lob = 6'h0; // @[consts.scala:269:19] wire [5:0] stq_0_bits_uop_uop_pdst = 6'h0; // @[consts.scala:269:19] wire [5:0] stq_0_bits_uop_uop_prs1 = 6'h0; // @[consts.scala:269:19] wire [5:0] stq_0_bits_uop_uop_prs2 = 6'h0; // @[consts.scala:269:19] wire [5:0] stq_0_bits_uop_uop_prs3 = 6'h0; // @[consts.scala:269:19] wire [5:0] stq_0_bits_uop_uop_stale_pdst = 6'h0; // @[consts.scala:269:19] wire [5:0] stq_0_bits_uop_uop_ldst = 6'h0; // @[consts.scala:269:19] wire [5:0] stq_0_bits_uop_uop_lrs1 = 6'h0; // @[consts.scala:269:19] wire [5:0] stq_0_bits_uop_uop_lrs2 = 6'h0; // @[consts.scala:269:19] wire [5:0] stq_0_bits_uop_uop_lrs3 = 6'h0; // @[consts.scala:269:19] wire [5:0] stq_1_bits_uop_uop_pc_lob = 6'h0; // @[consts.scala:269:19] wire [5:0] stq_1_bits_uop_uop_pdst = 6'h0; // @[consts.scala:269:19] wire [5:0] stq_1_bits_uop_uop_prs1 = 6'h0; // @[consts.scala:269:19] wire [5:0] stq_1_bits_uop_uop_prs2 = 6'h0; // @[consts.scala:269:19] wire [5:0] stq_1_bits_uop_uop_prs3 = 6'h0; // @[consts.scala:269:19] wire [5:0] stq_1_bits_uop_uop_stale_pdst = 6'h0; // @[consts.scala:269:19] wire [5:0] stq_1_bits_uop_uop_ldst = 6'h0; // @[consts.scala:269:19] wire [5:0] stq_1_bits_uop_uop_lrs1 = 6'h0; // @[consts.scala:269:19] wire [5:0] stq_1_bits_uop_uop_lrs2 = 6'h0; // @[consts.scala:269:19] wire [5:0] stq_1_bits_uop_uop_lrs3 = 6'h0; // @[consts.scala:269:19] wire [5:0] stq_2_bits_uop_uop_pc_lob = 6'h0; // @[consts.scala:269:19] wire [5:0] stq_2_bits_uop_uop_pdst = 6'h0; // @[consts.scala:269:19] wire [5:0] stq_2_bits_uop_uop_prs1 = 6'h0; // @[consts.scala:269:19] wire [5:0] stq_2_bits_uop_uop_prs2 = 6'h0; // @[consts.scala:269:19] wire [5:0] stq_2_bits_uop_uop_prs3 = 6'h0; // @[consts.scala:269:19] wire [5:0] stq_2_bits_uop_uop_stale_pdst = 6'h0; // @[consts.scala:269:19] wire [5:0] stq_2_bits_uop_uop_ldst = 6'h0; // @[consts.scala:269:19] wire [5:0] stq_2_bits_uop_uop_lrs1 = 6'h0; // @[consts.scala:269:19] wire [5:0] stq_2_bits_uop_uop_lrs2 = 6'h0; // @[consts.scala:269:19] wire [5:0] stq_2_bits_uop_uop_lrs3 = 6'h0; // @[consts.scala:269:19] wire [5:0] stq_3_bits_uop_uop_pc_lob = 6'h0; // @[consts.scala:269:19] wire [5:0] stq_3_bits_uop_uop_pdst = 6'h0; // @[consts.scala:269:19] wire [5:0] stq_3_bits_uop_uop_prs1 = 6'h0; // @[consts.scala:269:19] wire [5:0] stq_3_bits_uop_uop_prs2 = 6'h0; // @[consts.scala:269:19] wire [5:0] stq_3_bits_uop_uop_prs3 = 6'h0; // @[consts.scala:269:19] wire [5:0] stq_3_bits_uop_uop_stale_pdst = 6'h0; // @[consts.scala:269:19] wire [5:0] stq_3_bits_uop_uop_ldst = 6'h0; // @[consts.scala:269:19] wire [5:0] stq_3_bits_uop_uop_lrs1 = 6'h0; // @[consts.scala:269:19] wire [5:0] stq_3_bits_uop_uop_lrs2 = 6'h0; // @[consts.scala:269:19] wire [5:0] stq_3_bits_uop_uop_lrs3 = 6'h0; // @[consts.scala:269:19] wire [5:0] stq_4_bits_uop_uop_pc_lob = 6'h0; // @[consts.scala:269:19] wire [5:0] stq_4_bits_uop_uop_pdst = 6'h0; // @[consts.scala:269:19] wire [5:0] stq_4_bits_uop_uop_prs1 = 6'h0; // @[consts.scala:269:19] wire [5:0] stq_4_bits_uop_uop_prs2 = 6'h0; // @[consts.scala:269:19] wire [5:0] stq_4_bits_uop_uop_prs3 = 6'h0; // @[consts.scala:269:19] wire [5:0] stq_4_bits_uop_uop_stale_pdst = 6'h0; // @[consts.scala:269:19] wire [5:0] stq_4_bits_uop_uop_ldst = 6'h0; // @[consts.scala:269:19] wire [5:0] stq_4_bits_uop_uop_lrs1 = 6'h0; // @[consts.scala:269:19] wire [5:0] stq_4_bits_uop_uop_lrs2 = 6'h0; // @[consts.scala:269:19] wire [5:0] stq_4_bits_uop_uop_lrs3 = 6'h0; // @[consts.scala:269:19] wire [5:0] stq_5_bits_uop_uop_pc_lob = 6'h0; // @[consts.scala:269:19] wire [5:0] stq_5_bits_uop_uop_pdst = 6'h0; // @[consts.scala:269:19] wire [5:0] stq_5_bits_uop_uop_prs1 = 6'h0; // @[consts.scala:269:19] wire [5:0] stq_5_bits_uop_uop_prs2 = 6'h0; // @[consts.scala:269:19] wire [5:0] stq_5_bits_uop_uop_prs3 = 6'h0; // @[consts.scala:269:19] wire [5:0] stq_5_bits_uop_uop_stale_pdst = 6'h0; // @[consts.scala:269:19] wire [5:0] stq_5_bits_uop_uop_ldst = 6'h0; // @[consts.scala:269:19] wire [5:0] stq_5_bits_uop_uop_lrs1 = 6'h0; // @[consts.scala:269:19] wire [5:0] stq_5_bits_uop_uop_lrs2 = 6'h0; // @[consts.scala:269:19] wire [5:0] stq_5_bits_uop_uop_lrs3 = 6'h0; // @[consts.scala:269:19] wire [5:0] stq_6_bits_uop_uop_pc_lob = 6'h0; // @[consts.scala:269:19] wire [5:0] stq_6_bits_uop_uop_pdst = 6'h0; // @[consts.scala:269:19] wire [5:0] stq_6_bits_uop_uop_prs1 = 6'h0; // @[consts.scala:269:19] wire [5:0] stq_6_bits_uop_uop_prs2 = 6'h0; // @[consts.scala:269:19] wire [5:0] stq_6_bits_uop_uop_prs3 = 6'h0; // @[consts.scala:269:19] wire [5:0] stq_6_bits_uop_uop_stale_pdst = 6'h0; // @[consts.scala:269:19] wire [5:0] stq_6_bits_uop_uop_ldst = 6'h0; // @[consts.scala:269:19] wire [5:0] stq_6_bits_uop_uop_lrs1 = 6'h0; // @[consts.scala:269:19] wire [5:0] stq_6_bits_uop_uop_lrs2 = 6'h0; // @[consts.scala:269:19] wire [5:0] stq_6_bits_uop_uop_lrs3 = 6'h0; // @[consts.scala:269:19] wire [5:0] stq_7_bits_uop_uop_pc_lob = 6'h0; // @[consts.scala:269:19] wire [5:0] stq_7_bits_uop_uop_pdst = 6'h0; // @[consts.scala:269:19] wire [5:0] stq_7_bits_uop_uop_prs1 = 6'h0; // @[consts.scala:269:19] wire [5:0] stq_7_bits_uop_uop_prs2 = 6'h0; // @[consts.scala:269:19] wire [5:0] stq_7_bits_uop_uop_prs3 = 6'h0; // @[consts.scala:269:19] wire [5:0] stq_7_bits_uop_uop_stale_pdst = 6'h0; // @[consts.scala:269:19] wire [5:0] stq_7_bits_uop_uop_ldst = 6'h0; // @[consts.scala:269:19] wire [5:0] stq_7_bits_uop_uop_lrs1 = 6'h0; // @[consts.scala:269:19] wire [5:0] stq_7_bits_uop_uop_lrs2 = 6'h0; // @[consts.scala:269:19] wire [5:0] stq_7_bits_uop_uop_lrs3 = 6'h0; // @[consts.scala:269:19] wire [31:0] io_ptw_gstatus_isa = 32'h0; // @[lsu.scala:201:7] wire [31:0] io_core_exe_0_req_bits_fflags_bits_uop_inst = 32'h0; // @[lsu.scala:201:7] wire [31:0] io_core_exe_0_req_bits_fflags_bits_uop_debug_inst = 32'h0; // @[lsu.scala:201:7] wire [31:0] io_core_exe_0_iresp_bits_fflags_bits_uop_inst = 32'h0; // @[lsu.scala:201:7] wire [31:0] io_core_exe_0_iresp_bits_fflags_bits_uop_debug_inst = 32'h0; // @[lsu.scala:201:7] wire [31:0] io_core_exe_0_fresp_bits_fflags_bits_uop_inst = 32'h0; // @[lsu.scala:201:7] wire [31:0] io_core_exe_0_fresp_bits_fflags_bits_uop_debug_inst = 32'h0; // @[lsu.scala:201:7] wire [31:0] io_hellacache_s2_paddr = 32'h0; // @[lsu.scala:201:7] wire [31:0] _exe_req_WIRE_0_bits_fflags_bits_uop_inst = 32'h0; // @[lsu.scala:383:33] wire [31:0] _exe_req_WIRE_0_bits_fflags_bits_uop_debug_inst = 32'h0; // @[lsu.scala:383:33] wire [31:0] exe_req_0_bits_fflags_bits_uop_inst = 32'h0; // @[lsu.scala:383:25] wire [31:0] exe_req_0_bits_fflags_bits_uop_debug_inst = 32'h0; // @[lsu.scala:383:25] wire [31:0] exe_tlb_uop_uop_inst = 32'h0; // @[consts.scala:269:19] wire [31:0] exe_tlb_uop_uop_debug_inst = 32'h0; // @[consts.scala:269:19] wire [31:0] exe_tlb_uop_uop_1_inst = 32'h0; // @[consts.scala:269:19] wire [31:0] exe_tlb_uop_uop_1_debug_inst = 32'h0; // @[consts.scala:269:19] wire [31:0] _exe_tlb_uop_T_3_inst = 32'h0; // @[lsu.scala:602:24] wire [31:0] _exe_tlb_uop_T_3_debug_inst = 32'h0; // @[lsu.scala:602:24] wire [31:0] dmem_req_0_bits_uop_uop_inst = 32'h0; // @[consts.scala:269:19] wire [31:0] dmem_req_0_bits_uop_uop_debug_inst = 32'h0; // @[consts.scala:269:19] wire [31:0] _dmem_req_0_bits_data_T_18 = 32'h0; // @[AMOALU.scala:29:32] wire [31:0] _dmem_req_0_bits_data_T_22 = 32'h0; // @[AMOALU.scala:29:32] wire [31:0] _dmem_req_0_bits_data_T_25 = 32'h0; // @[AMOALU.scala:29:69] wire [31:0] _mem_ldq_e_WIRE_bits_uop_inst = 32'h0; // @[lsu.scala:918:90] wire [31:0] _mem_ldq_e_WIRE_bits_uop_debug_inst = 32'h0; // @[lsu.scala:918:90] wire [31:0] _mem_stq_e_WIRE_bits_uop_inst = 32'h0; // @[lsu.scala:922:89] wire [31:0] _mem_stq_e_WIRE_bits_uop_debug_inst = 32'h0; // @[lsu.scala:922:89] wire [31:0] lcam_uop_uop_inst = 32'h0; // @[consts.scala:269:19] wire [31:0] lcam_uop_uop_debug_inst = 32'h0; // @[consts.scala:269:19] wire [31:0] stq_0_bits_uop_uop_inst = 32'h0; // @[consts.scala:269:19] wire [31:0] stq_0_bits_uop_uop_debug_inst = 32'h0; // @[consts.scala:269:19] wire [31:0] stq_1_bits_uop_uop_inst = 32'h0; // @[consts.scala:269:19] wire [31:0] stq_1_bits_uop_uop_debug_inst = 32'h0; // @[consts.scala:269:19] wire [31:0] stq_2_bits_uop_uop_inst = 32'h0; // @[consts.scala:269:19] wire [31:0] stq_2_bits_uop_uop_debug_inst = 32'h0; // @[consts.scala:269:19] wire [31:0] stq_3_bits_uop_uop_inst = 32'h0; // @[consts.scala:269:19] wire [31:0] stq_3_bits_uop_uop_debug_inst = 32'h0; // @[consts.scala:269:19] wire [31:0] stq_4_bits_uop_uop_inst = 32'h0; // @[consts.scala:269:19] wire [31:0] stq_4_bits_uop_uop_debug_inst = 32'h0; // @[consts.scala:269:19] wire [31:0] stq_5_bits_uop_uop_inst = 32'h0; // @[consts.scala:269:19] wire [31:0] stq_5_bits_uop_uop_debug_inst = 32'h0; // @[consts.scala:269:19] wire [31:0] stq_6_bits_uop_uop_inst = 32'h0; // @[consts.scala:269:19] wire [31:0] stq_6_bits_uop_uop_debug_inst = 32'h0; // @[consts.scala:269:19] wire [31:0] stq_7_bits_uop_uop_inst = 32'h0; // @[consts.scala:269:19] wire [31:0] stq_7_bits_uop_uop_debug_inst = 32'h0; // @[consts.scala:269:19] wire [39:0] io_core_exe_0_req_bits_fflags_bits_uop_debug_pc = 40'h0; // @[lsu.scala:201:7] wire [39:0] io_core_exe_0_iresp_bits_fflags_bits_uop_debug_pc = 40'h0; // @[lsu.scala:201:7] wire [39:0] io_core_exe_0_fresp_bits_fflags_bits_uop_debug_pc = 40'h0; // @[lsu.scala:201:7] wire [39:0] io_hellacache_s2_gpa = 40'h0; // @[lsu.scala:201:7] wire [39:0] _exe_req_WIRE_0_bits_fflags_bits_uop_debug_pc = 40'h0; // @[lsu.scala:383:33] wire [39:0] exe_req_0_bits_fflags_bits_uop_debug_pc = 40'h0; // @[lsu.scala:383:25] wire [39:0] exe_tlb_uop_uop_debug_pc = 40'h0; // @[consts.scala:269:19] wire [39:0] exe_tlb_uop_uop_1_debug_pc = 40'h0; // @[consts.scala:269:19] wire [39:0] _exe_tlb_uop_T_3_debug_pc = 40'h0; // @[lsu.scala:602:24] wire [39:0] dmem_req_0_bits_uop_uop_debug_pc = 40'h0; // @[consts.scala:269:19] wire [39:0] _mem_ldq_e_WIRE_bits_uop_debug_pc = 40'h0; // @[lsu.scala:918:90] wire [39:0] _mem_ldq_e_WIRE_bits_addr_bits = 40'h0; // @[lsu.scala:918:90] wire [39:0] _mem_stq_e_WIRE_bits_uop_debug_pc = 40'h0; // @[lsu.scala:922:89] wire [39:0] _mem_stq_e_WIRE_bits_addr_bits = 40'h0; // @[lsu.scala:922:89] wire [39:0] lcam_uop_uop_debug_pc = 40'h0; // @[consts.scala:269:19] wire [39:0] stq_0_bits_uop_uop_debug_pc = 40'h0; // @[consts.scala:269:19] wire [39:0] stq_1_bits_uop_uop_debug_pc = 40'h0; // @[consts.scala:269:19] wire [39:0] stq_2_bits_uop_uop_debug_pc = 40'h0; // @[consts.scala:269:19] wire [39:0] stq_3_bits_uop_uop_debug_pc = 40'h0; // @[consts.scala:269:19] wire [39:0] stq_4_bits_uop_uop_debug_pc = 40'h0; // @[consts.scala:269:19] wire [39:0] stq_5_bits_uop_uop_debug_pc = 40'h0; // @[consts.scala:269:19] wire [39:0] stq_6_bits_uop_uop_debug_pc = 40'h0; // @[consts.scala:269:19] wire [39:0] stq_7_bits_uop_uop_debug_pc = 40'h0; // @[consts.scala:269:19] wire [2:0] io_core_exe_0_req_bits_fflags_bits_uop_iq_type = 3'h0; // @[lsu.scala:201:7] wire [2:0] io_core_exe_0_req_bits_fflags_bits_uop_ctrl_op2_sel = 3'h0; // @[lsu.scala:201:7] wire [2:0] io_core_exe_0_req_bits_fflags_bits_uop_ctrl_imm_sel = 3'h0; // @[lsu.scala:201:7] wire [2:0] io_core_exe_0_req_bits_fflags_bits_uop_ctrl_csr_cmd = 3'h0; // @[lsu.scala:201:7] wire [2:0] io_core_exe_0_req_bits_fflags_bits_uop_br_tag = 3'h0; // @[lsu.scala:201:7] wire [2:0] io_core_exe_0_req_bits_fflags_bits_uop_ldq_idx = 3'h0; // @[lsu.scala:201:7] wire [2:0] io_core_exe_0_req_bits_fflags_bits_uop_stq_idx = 3'h0; // @[lsu.scala:201:7] wire [2:0] io_core_exe_0_iresp_bits_fflags_bits_uop_iq_type = 3'h0; // @[lsu.scala:201:7] wire [2:0] io_core_exe_0_iresp_bits_fflags_bits_uop_ctrl_op2_sel = 3'h0; // @[lsu.scala:201:7] wire [2:0] io_core_exe_0_iresp_bits_fflags_bits_uop_ctrl_imm_sel = 3'h0; // @[lsu.scala:201:7] wire [2:0] io_core_exe_0_iresp_bits_fflags_bits_uop_ctrl_csr_cmd = 3'h0; // @[lsu.scala:201:7] wire [2:0] io_core_exe_0_iresp_bits_fflags_bits_uop_br_tag = 3'h0; // @[lsu.scala:201:7] wire [2:0] io_core_exe_0_iresp_bits_fflags_bits_uop_ldq_idx = 3'h0; // @[lsu.scala:201:7] wire [2:0] io_core_exe_0_iresp_bits_fflags_bits_uop_stq_idx = 3'h0; // @[lsu.scala:201:7] wire [2:0] io_core_exe_0_fresp_bits_fflags_bits_uop_iq_type = 3'h0; // @[lsu.scala:201:7] wire [2:0] io_core_exe_0_fresp_bits_fflags_bits_uop_ctrl_op2_sel = 3'h0; // @[lsu.scala:201:7] wire [2:0] io_core_exe_0_fresp_bits_fflags_bits_uop_ctrl_imm_sel = 3'h0; // @[lsu.scala:201:7] wire [2:0] io_core_exe_0_fresp_bits_fflags_bits_uop_ctrl_csr_cmd = 3'h0; // @[lsu.scala:201:7] wire [2:0] io_core_exe_0_fresp_bits_fflags_bits_uop_br_tag = 3'h0; // @[lsu.scala:201:7] wire [2:0] io_core_exe_0_fresp_bits_fflags_bits_uop_ldq_idx = 3'h0; // @[lsu.scala:201:7] wire [2:0] io_core_exe_0_fresp_bits_fflags_bits_uop_stq_idx = 3'h0; // @[lsu.scala:201:7] wire [2:0] _exe_req_WIRE_0_bits_fflags_bits_uop_iq_type = 3'h0; // @[lsu.scala:383:33] wire [2:0] _exe_req_WIRE_0_bits_fflags_bits_uop_ctrl_op2_sel = 3'h0; // @[lsu.scala:383:33] wire [2:0] _exe_req_WIRE_0_bits_fflags_bits_uop_ctrl_imm_sel = 3'h0; // @[lsu.scala:383:33] wire [2:0] _exe_req_WIRE_0_bits_fflags_bits_uop_ctrl_csr_cmd = 3'h0; // @[lsu.scala:383:33] wire [2:0] _exe_req_WIRE_0_bits_fflags_bits_uop_br_tag = 3'h0; // @[lsu.scala:383:33] wire [2:0] _exe_req_WIRE_0_bits_fflags_bits_uop_ldq_idx = 3'h0; // @[lsu.scala:383:33] wire [2:0] _exe_req_WIRE_0_bits_fflags_bits_uop_stq_idx = 3'h0; // @[lsu.scala:383:33] wire [2:0] exe_req_0_bits_fflags_bits_uop_iq_type = 3'h0; // @[lsu.scala:383:25] wire [2:0] exe_req_0_bits_fflags_bits_uop_ctrl_op2_sel = 3'h0; // @[lsu.scala:383:25] wire [2:0] exe_req_0_bits_fflags_bits_uop_ctrl_imm_sel = 3'h0; // @[lsu.scala:383:25] wire [2:0] exe_req_0_bits_fflags_bits_uop_ctrl_csr_cmd = 3'h0; // @[lsu.scala:383:25] wire [2:0] exe_req_0_bits_fflags_bits_uop_br_tag = 3'h0; // @[lsu.scala:383:25] wire [2:0] exe_req_0_bits_fflags_bits_uop_ldq_idx = 3'h0; // @[lsu.scala:383:25] wire [2:0] exe_req_0_bits_fflags_bits_uop_stq_idx = 3'h0; // @[lsu.scala:383:25] wire [2:0] exe_tlb_uop_uop_iq_type = 3'h0; // @[consts.scala:269:19] wire [2:0] exe_tlb_uop_uop_ctrl_op2_sel = 3'h0; // @[consts.scala:269:19] wire [2:0] exe_tlb_uop_uop_ctrl_imm_sel = 3'h0; // @[consts.scala:269:19] wire [2:0] exe_tlb_uop_uop_ctrl_csr_cmd = 3'h0; // @[consts.scala:269:19] wire [2:0] exe_tlb_uop_uop_br_tag = 3'h0; // @[consts.scala:269:19] wire [2:0] exe_tlb_uop_uop_ldq_idx = 3'h0; // @[consts.scala:269:19] wire [2:0] exe_tlb_uop_uop_stq_idx = 3'h0; // @[consts.scala:269:19] wire [2:0] exe_tlb_uop_cs_op2_sel = 3'h0; // @[consts.scala:279:18] wire [2:0] exe_tlb_uop_cs_imm_sel = 3'h0; // @[consts.scala:279:18] wire [2:0] exe_tlb_uop_cs_csr_cmd = 3'h0; // @[consts.scala:279:18] wire [2:0] exe_tlb_uop_uop_1_iq_type = 3'h0; // @[consts.scala:269:19] wire [2:0] exe_tlb_uop_uop_1_ctrl_op2_sel = 3'h0; // @[consts.scala:269:19] wire [2:0] exe_tlb_uop_uop_1_ctrl_imm_sel = 3'h0; // @[consts.scala:269:19] wire [2:0] exe_tlb_uop_uop_1_ctrl_csr_cmd = 3'h0; // @[consts.scala:269:19] wire [2:0] exe_tlb_uop_uop_1_br_tag = 3'h0; // @[consts.scala:269:19] wire [2:0] exe_tlb_uop_uop_1_ldq_idx = 3'h0; // @[consts.scala:269:19] wire [2:0] exe_tlb_uop_uop_1_stq_idx = 3'h0; // @[consts.scala:269:19] wire [2:0] exe_tlb_uop_cs_1_op2_sel = 3'h0; // @[consts.scala:279:18] wire [2:0] exe_tlb_uop_cs_1_imm_sel = 3'h0; // @[consts.scala:279:18] wire [2:0] exe_tlb_uop_cs_1_csr_cmd = 3'h0; // @[consts.scala:279:18] wire [2:0] _exe_tlb_uop_T_3_iq_type = 3'h0; // @[lsu.scala:602:24] wire [2:0] _exe_tlb_uop_T_3_ctrl_op2_sel = 3'h0; // @[lsu.scala:602:24] wire [2:0] _exe_tlb_uop_T_3_ctrl_imm_sel = 3'h0; // @[lsu.scala:602:24] wire [2:0] _exe_tlb_uop_T_3_ctrl_csr_cmd = 3'h0; // @[lsu.scala:602:24] wire [2:0] _exe_tlb_uop_T_3_br_tag = 3'h0; // @[lsu.scala:602:24] wire [2:0] _exe_tlb_uop_T_3_ldq_idx = 3'h0; // @[lsu.scala:602:24] wire [2:0] _exe_tlb_uop_T_3_stq_idx = 3'h0; // @[lsu.scala:602:24] wire [2:0] dmem_req_0_bits_uop_uop_iq_type = 3'h0; // @[consts.scala:269:19] wire [2:0] dmem_req_0_bits_uop_uop_ctrl_op2_sel = 3'h0; // @[consts.scala:269:19] wire [2:0] dmem_req_0_bits_uop_uop_ctrl_imm_sel = 3'h0; // @[consts.scala:269:19] wire [2:0] dmem_req_0_bits_uop_uop_ctrl_csr_cmd = 3'h0; // @[consts.scala:269:19] wire [2:0] dmem_req_0_bits_uop_uop_br_tag = 3'h0; // @[consts.scala:269:19] wire [2:0] dmem_req_0_bits_uop_uop_ldq_idx = 3'h0; // @[consts.scala:269:19] wire [2:0] dmem_req_0_bits_uop_uop_stq_idx = 3'h0; // @[consts.scala:269:19] wire [2:0] dmem_req_0_bits_uop_cs_op2_sel = 3'h0; // @[consts.scala:279:18] wire [2:0] dmem_req_0_bits_uop_cs_imm_sel = 3'h0; // @[consts.scala:279:18] wire [2:0] dmem_req_0_bits_uop_cs_csr_cmd = 3'h0; // @[consts.scala:279:18] wire [2:0] _mem_ldq_e_WIRE_bits_uop_iq_type = 3'h0; // @[lsu.scala:918:90] wire [2:0] _mem_ldq_e_WIRE_bits_uop_ctrl_op2_sel = 3'h0; // @[lsu.scala:918:90] wire [2:0] _mem_ldq_e_WIRE_bits_uop_ctrl_imm_sel = 3'h0; // @[lsu.scala:918:90] wire [2:0] _mem_ldq_e_WIRE_bits_uop_ctrl_csr_cmd = 3'h0; // @[lsu.scala:918:90] wire [2:0] _mem_ldq_e_WIRE_bits_uop_br_tag = 3'h0; // @[lsu.scala:918:90] wire [2:0] _mem_ldq_e_WIRE_bits_uop_ldq_idx = 3'h0; // @[lsu.scala:918:90] wire [2:0] _mem_ldq_e_WIRE_bits_uop_stq_idx = 3'h0; // @[lsu.scala:918:90] wire [2:0] _mem_ldq_e_WIRE_bits_youngest_stq_idx = 3'h0; // @[lsu.scala:918:90] wire [2:0] _mem_ldq_e_WIRE_bits_forward_stq_idx = 3'h0; // @[lsu.scala:918:90] wire [2:0] _mem_stq_e_WIRE_bits_uop_iq_type = 3'h0; // @[lsu.scala:922:89] wire [2:0] _mem_stq_e_WIRE_bits_uop_ctrl_op2_sel = 3'h0; // @[lsu.scala:922:89] wire [2:0] _mem_stq_e_WIRE_bits_uop_ctrl_imm_sel = 3'h0; // @[lsu.scala:922:89] wire [2:0] _mem_stq_e_WIRE_bits_uop_ctrl_csr_cmd = 3'h0; // @[lsu.scala:922:89] wire [2:0] _mem_stq_e_WIRE_bits_uop_br_tag = 3'h0; // @[lsu.scala:922:89] wire [2:0] _mem_stq_e_WIRE_bits_uop_ldq_idx = 3'h0; // @[lsu.scala:922:89] wire [2:0] _mem_stq_e_WIRE_bits_uop_stq_idx = 3'h0; // @[lsu.scala:922:89] wire [2:0] lcam_uop_uop_iq_type = 3'h0; // @[consts.scala:269:19] wire [2:0] lcam_uop_uop_ctrl_op2_sel = 3'h0; // @[consts.scala:269:19] wire [2:0] lcam_uop_uop_ctrl_imm_sel = 3'h0; // @[consts.scala:269:19] wire [2:0] lcam_uop_uop_ctrl_csr_cmd = 3'h0; // @[consts.scala:269:19] wire [2:0] lcam_uop_uop_br_tag = 3'h0; // @[consts.scala:269:19] wire [2:0] lcam_uop_uop_ldq_idx = 3'h0; // @[consts.scala:269:19] wire [2:0] lcam_uop_uop_stq_idx = 3'h0; // @[consts.scala:269:19] wire [2:0] lcam_uop_cs_op2_sel = 3'h0; // @[consts.scala:279:18] wire [2:0] lcam_uop_cs_imm_sel = 3'h0; // @[consts.scala:279:18] wire [2:0] lcam_uop_cs_csr_cmd = 3'h0; // @[consts.scala:279:18] wire [2:0] stq_0_bits_uop_uop_iq_type = 3'h0; // @[consts.scala:269:19] wire [2:0] stq_0_bits_uop_uop_ctrl_op2_sel = 3'h0; // @[consts.scala:269:19] wire [2:0] stq_0_bits_uop_uop_ctrl_imm_sel = 3'h0; // @[consts.scala:269:19] wire [2:0] stq_0_bits_uop_uop_ctrl_csr_cmd = 3'h0; // @[consts.scala:269:19] wire [2:0] stq_0_bits_uop_uop_br_tag = 3'h0; // @[consts.scala:269:19] wire [2:0] stq_0_bits_uop_uop_ldq_idx = 3'h0; // @[consts.scala:269:19] wire [2:0] stq_0_bits_uop_uop_stq_idx = 3'h0; // @[consts.scala:269:19] wire [2:0] stq_0_bits_uop_cs_op2_sel = 3'h0; // @[consts.scala:279:18] wire [2:0] stq_0_bits_uop_cs_imm_sel = 3'h0; // @[consts.scala:279:18] wire [2:0] stq_0_bits_uop_cs_csr_cmd = 3'h0; // @[consts.scala:279:18] wire [2:0] stq_1_bits_uop_uop_iq_type = 3'h0; // @[consts.scala:269:19] wire [2:0] stq_1_bits_uop_uop_ctrl_op2_sel = 3'h0; // @[consts.scala:269:19] wire [2:0] stq_1_bits_uop_uop_ctrl_imm_sel = 3'h0; // @[consts.scala:269:19] wire [2:0] stq_1_bits_uop_uop_ctrl_csr_cmd = 3'h0; // @[consts.scala:269:19] wire [2:0] stq_1_bits_uop_uop_br_tag = 3'h0; // @[consts.scala:269:19] wire [2:0] stq_1_bits_uop_uop_ldq_idx = 3'h0; // @[consts.scala:269:19] wire [2:0] stq_1_bits_uop_uop_stq_idx = 3'h0; // @[consts.scala:269:19] wire [2:0] stq_1_bits_uop_cs_op2_sel = 3'h0; // @[consts.scala:279:18] wire [2:0] stq_1_bits_uop_cs_imm_sel = 3'h0; // @[consts.scala:279:18] wire [2:0] stq_1_bits_uop_cs_csr_cmd = 3'h0; // @[consts.scala:279:18] wire [2:0] stq_2_bits_uop_uop_iq_type = 3'h0; // @[consts.scala:269:19] wire [2:0] stq_2_bits_uop_uop_ctrl_op2_sel = 3'h0; // @[consts.scala:269:19] wire [2:0] stq_2_bits_uop_uop_ctrl_imm_sel = 3'h0; // @[consts.scala:269:19] wire [2:0] stq_2_bits_uop_uop_ctrl_csr_cmd = 3'h0; // @[consts.scala:269:19] wire [2:0] stq_2_bits_uop_uop_br_tag = 3'h0; // @[consts.scala:269:19] wire [2:0] stq_2_bits_uop_uop_ldq_idx = 3'h0; // @[consts.scala:269:19] wire [2:0] stq_2_bits_uop_uop_stq_idx = 3'h0; // @[consts.scala:269:19] wire [2:0] stq_2_bits_uop_cs_op2_sel = 3'h0; // @[consts.scala:279:18] wire [2:0] stq_2_bits_uop_cs_imm_sel = 3'h0; // @[consts.scala:279:18] wire [2:0] stq_2_bits_uop_cs_csr_cmd = 3'h0; // @[consts.scala:279:18] wire [2:0] stq_3_bits_uop_uop_iq_type = 3'h0; // @[consts.scala:269:19] wire [2:0] stq_3_bits_uop_uop_ctrl_op2_sel = 3'h0; // @[consts.scala:269:19] wire [2:0] stq_3_bits_uop_uop_ctrl_imm_sel = 3'h0; // @[consts.scala:269:19] wire [2:0] stq_3_bits_uop_uop_ctrl_csr_cmd = 3'h0; // @[consts.scala:269:19] wire [2:0] stq_3_bits_uop_uop_br_tag = 3'h0; // @[consts.scala:269:19] wire [2:0] stq_3_bits_uop_uop_ldq_idx = 3'h0; // @[consts.scala:269:19] wire [2:0] stq_3_bits_uop_uop_stq_idx = 3'h0; // @[consts.scala:269:19] wire [2:0] stq_3_bits_uop_cs_op2_sel = 3'h0; // @[consts.scala:279:18] wire [2:0] stq_3_bits_uop_cs_imm_sel = 3'h0; // @[consts.scala:279:18] wire [2:0] stq_3_bits_uop_cs_csr_cmd = 3'h0; // @[consts.scala:279:18] wire [2:0] stq_4_bits_uop_uop_iq_type = 3'h0; // @[consts.scala:269:19] wire [2:0] stq_4_bits_uop_uop_ctrl_op2_sel = 3'h0; // @[consts.scala:269:19] wire [2:0] stq_4_bits_uop_uop_ctrl_imm_sel = 3'h0; // @[consts.scala:269:19] wire [2:0] stq_4_bits_uop_uop_ctrl_csr_cmd = 3'h0; // @[consts.scala:269:19] wire [2:0] stq_4_bits_uop_uop_br_tag = 3'h0; // @[consts.scala:269:19] wire [2:0] stq_4_bits_uop_uop_ldq_idx = 3'h0; // @[consts.scala:269:19] wire [2:0] stq_4_bits_uop_uop_stq_idx = 3'h0; // @[consts.scala:269:19] wire [2:0] stq_4_bits_uop_cs_op2_sel = 3'h0; // @[consts.scala:279:18] wire [2:0] stq_4_bits_uop_cs_imm_sel = 3'h0; // @[consts.scala:279:18] wire [2:0] stq_4_bits_uop_cs_csr_cmd = 3'h0; // @[consts.scala:279:18] wire [2:0] stq_5_bits_uop_uop_iq_type = 3'h0; // @[consts.scala:269:19] wire [2:0] stq_5_bits_uop_uop_ctrl_op2_sel = 3'h0; // @[consts.scala:269:19] wire [2:0] stq_5_bits_uop_uop_ctrl_imm_sel = 3'h0; // @[consts.scala:269:19] wire [2:0] stq_5_bits_uop_uop_ctrl_csr_cmd = 3'h0; // @[consts.scala:269:19] wire [2:0] stq_5_bits_uop_uop_br_tag = 3'h0; // @[consts.scala:269:19] wire [2:0] stq_5_bits_uop_uop_ldq_idx = 3'h0; // @[consts.scala:269:19] wire [2:0] stq_5_bits_uop_uop_stq_idx = 3'h0; // @[consts.scala:269:19] wire [2:0] stq_5_bits_uop_cs_op2_sel = 3'h0; // @[consts.scala:279:18] wire [2:0] stq_5_bits_uop_cs_imm_sel = 3'h0; // @[consts.scala:279:18] wire [2:0] stq_5_bits_uop_cs_csr_cmd = 3'h0; // @[consts.scala:279:18] wire [2:0] stq_6_bits_uop_uop_iq_type = 3'h0; // @[consts.scala:269:19] wire [2:0] stq_6_bits_uop_uop_ctrl_op2_sel = 3'h0; // @[consts.scala:269:19] wire [2:0] stq_6_bits_uop_uop_ctrl_imm_sel = 3'h0; // @[consts.scala:269:19] wire [2:0] stq_6_bits_uop_uop_ctrl_csr_cmd = 3'h0; // @[consts.scala:269:19] wire [2:0] stq_6_bits_uop_uop_br_tag = 3'h0; // @[consts.scala:269:19] wire [2:0] stq_6_bits_uop_uop_ldq_idx = 3'h0; // @[consts.scala:269:19] wire [2:0] stq_6_bits_uop_uop_stq_idx = 3'h0; // @[consts.scala:269:19] wire [2:0] stq_6_bits_uop_cs_op2_sel = 3'h0; // @[consts.scala:279:18] wire [2:0] stq_6_bits_uop_cs_imm_sel = 3'h0; // @[consts.scala:279:18] wire [2:0] stq_6_bits_uop_cs_csr_cmd = 3'h0; // @[consts.scala:279:18] wire [2:0] stq_7_bits_uop_uop_iq_type = 3'h0; // @[consts.scala:269:19] wire [2:0] stq_7_bits_uop_uop_ctrl_op2_sel = 3'h0; // @[consts.scala:269:19] wire [2:0] stq_7_bits_uop_uop_ctrl_imm_sel = 3'h0; // @[consts.scala:269:19] wire [2:0] stq_7_bits_uop_uop_ctrl_csr_cmd = 3'h0; // @[consts.scala:269:19] wire [2:0] stq_7_bits_uop_uop_br_tag = 3'h0; // @[consts.scala:269:19] wire [2:0] stq_7_bits_uop_uop_ldq_idx = 3'h0; // @[consts.scala:269:19] wire [2:0] stq_7_bits_uop_uop_stq_idx = 3'h0; // @[consts.scala:269:19] wire [2:0] stq_7_bits_uop_cs_op2_sel = 3'h0; // @[consts.scala:279:18] wire [2:0] stq_7_bits_uop_cs_imm_sel = 3'h0; // @[consts.scala:279:18] wire [2:0] stq_7_bits_uop_cs_csr_cmd = 3'h0; // @[consts.scala:279:18] wire [9:0] io_core_exe_0_req_bits_fflags_bits_uop_fu_code = 10'h0; // @[lsu.scala:201:7] wire [9:0] io_core_exe_0_iresp_bits_fflags_bits_uop_fu_code = 10'h0; // @[lsu.scala:201:7] wire [9:0] io_core_exe_0_fresp_bits_fflags_bits_uop_fu_code = 10'h0; // @[lsu.scala:201:7] wire [9:0] _exe_req_WIRE_0_bits_fflags_bits_uop_fu_code = 10'h0; // @[lsu.scala:383:33] wire [9:0] exe_req_0_bits_fflags_bits_uop_fu_code = 10'h0; // @[lsu.scala:383:25] wire [9:0] exe_tlb_uop_uop_fu_code = 10'h0; // @[consts.scala:269:19] wire [9:0] exe_tlb_uop_uop_1_fu_code = 10'h0; // @[consts.scala:269:19] wire [9:0] _exe_tlb_uop_T_3_fu_code = 10'h0; // @[lsu.scala:602:24] wire [9:0] dmem_req_0_bits_uop_uop_fu_code = 10'h0; // @[consts.scala:269:19] wire [9:0] _mem_ldq_e_WIRE_bits_uop_fu_code = 10'h0; // @[lsu.scala:918:90] wire [9:0] _mem_stq_e_WIRE_bits_uop_fu_code = 10'h0; // @[lsu.scala:922:89] wire [9:0] lcam_uop_uop_fu_code = 10'h0; // @[consts.scala:269:19] wire [9:0] stq_0_bits_uop_uop_fu_code = 10'h0; // @[consts.scala:269:19] wire [9:0] stq_1_bits_uop_uop_fu_code = 10'h0; // @[consts.scala:269:19] wire [9:0] stq_2_bits_uop_uop_fu_code = 10'h0; // @[consts.scala:269:19] wire [9:0] stq_3_bits_uop_uop_fu_code = 10'h0; // @[consts.scala:269:19] wire [9:0] stq_4_bits_uop_uop_fu_code = 10'h0; // @[consts.scala:269:19] wire [9:0] stq_5_bits_uop_uop_fu_code = 10'h0; // @[consts.scala:269:19] wire [9:0] stq_6_bits_uop_uop_fu_code = 10'h0; // @[consts.scala:269:19] wire [9:0] stq_7_bits_uop_uop_fu_code = 10'h0; // @[consts.scala:269:19] wire [19:0] io_core_exe_0_req_bits_fflags_bits_uop_imm_packed = 20'h0; // @[lsu.scala:201:7] wire [19:0] io_core_exe_0_iresp_bits_fflags_bits_uop_imm_packed = 20'h0; // @[lsu.scala:201:7] wire [19:0] io_core_exe_0_fresp_bits_fflags_bits_uop_imm_packed = 20'h0; // @[lsu.scala:201:7] wire [19:0] _exe_req_WIRE_0_bits_fflags_bits_uop_imm_packed = 20'h0; // @[lsu.scala:383:33] wire [19:0] exe_req_0_bits_fflags_bits_uop_imm_packed = 20'h0; // @[lsu.scala:383:25] wire [19:0] exe_tlb_uop_uop_imm_packed = 20'h0; // @[consts.scala:269:19] wire [19:0] exe_tlb_uop_uop_1_imm_packed = 20'h0; // @[consts.scala:269:19] wire [19:0] _exe_tlb_uop_T_3_imm_packed = 20'h0; // @[lsu.scala:602:24] wire [19:0] dmem_req_0_bits_uop_uop_imm_packed = 20'h0; // @[consts.scala:269:19] wire [19:0] _mem_ldq_e_WIRE_bits_uop_imm_packed = 20'h0; // @[lsu.scala:918:90] wire [19:0] _mem_stq_e_WIRE_bits_uop_imm_packed = 20'h0; // @[lsu.scala:922:89] wire [19:0] lcam_uop_uop_imm_packed = 20'h0; // @[consts.scala:269:19] wire [19:0] stq_0_bits_uop_uop_imm_packed = 20'h0; // @[consts.scala:269:19] wire [19:0] stq_1_bits_uop_uop_imm_packed = 20'h0; // @[consts.scala:269:19] wire [19:0] stq_2_bits_uop_uop_imm_packed = 20'h0; // @[consts.scala:269:19] wire [19:0] stq_3_bits_uop_uop_imm_packed = 20'h0; // @[consts.scala:269:19] wire [19:0] stq_4_bits_uop_uop_imm_packed = 20'h0; // @[consts.scala:269:19] wire [19:0] stq_5_bits_uop_uop_imm_packed = 20'h0; // @[consts.scala:269:19] wire [19:0] stq_6_bits_uop_uop_imm_packed = 20'h0; // @[consts.scala:269:19] wire [19:0] stq_7_bits_uop_uop_imm_packed = 20'h0; // @[consts.scala:269:19] wire [11:0] io_core_exe_0_req_bits_fflags_bits_uop_csr_addr = 12'h0; // @[lsu.scala:201:7] wire [11:0] io_core_exe_0_iresp_bits_fflags_bits_uop_csr_addr = 12'h0; // @[lsu.scala:201:7] wire [11:0] io_core_exe_0_fresp_bits_fflags_bits_uop_csr_addr = 12'h0; // @[lsu.scala:201:7] wire [11:0] _exe_req_WIRE_0_bits_fflags_bits_uop_csr_addr = 12'h0; // @[lsu.scala:383:33] wire [11:0] exe_req_0_bits_fflags_bits_uop_csr_addr = 12'h0; // @[lsu.scala:383:25] wire [11:0] exe_tlb_uop_uop_csr_addr = 12'h0; // @[consts.scala:269:19] wire [11:0] exe_tlb_uop_uop_1_csr_addr = 12'h0; // @[consts.scala:269:19] wire [11:0] _exe_tlb_uop_T_3_csr_addr = 12'h0; // @[lsu.scala:602:24] wire [11:0] dmem_req_0_bits_uop_uop_csr_addr = 12'h0; // @[consts.scala:269:19] wire [11:0] _mem_ldq_e_WIRE_bits_uop_csr_addr = 12'h0; // @[lsu.scala:918:90] wire [11:0] _mem_stq_e_WIRE_bits_uop_csr_addr = 12'h0; // @[lsu.scala:922:89] wire [11:0] lcam_uop_uop_csr_addr = 12'h0; // @[consts.scala:269:19] wire [11:0] stq_0_bits_uop_uop_csr_addr = 12'h0; // @[consts.scala:269:19] wire [11:0] stq_1_bits_uop_uop_csr_addr = 12'h0; // @[consts.scala:269:19] wire [11:0] stq_2_bits_uop_uop_csr_addr = 12'h0; // @[consts.scala:269:19] wire [11:0] stq_3_bits_uop_uop_csr_addr = 12'h0; // @[consts.scala:269:19] wire [11:0] stq_4_bits_uop_uop_csr_addr = 12'h0; // @[consts.scala:269:19] wire [11:0] stq_5_bits_uop_uop_csr_addr = 12'h0; // @[consts.scala:269:19] wire [11:0] stq_6_bits_uop_uop_csr_addr = 12'h0; // @[consts.scala:269:19] wire [11:0] stq_7_bits_uop_uop_csr_addr = 12'h0; // @[consts.scala:269:19] wire [7:0] _lcam_mask_mask_T_11 = 8'hFF; // @[Mux.scala:126:16] wire [7:0] _l_mask_mask_T_11 = 8'hFF; // @[Mux.scala:126:16] wire [7:0] _l_mask_mask_T_26 = 8'hFF; // @[Mux.scala:126:16] wire [7:0] _l_mask_mask_T_41 = 8'hFF; // @[Mux.scala:126:16] wire [7:0] _l_mask_mask_T_56 = 8'hFF; // @[Mux.scala:126:16] wire [7:0] _l_mask_mask_T_71 = 8'hFF; // @[Mux.scala:126:16] wire [7:0] _l_mask_mask_T_86 = 8'hFF; // @[Mux.scala:126:16] wire [7:0] _l_mask_mask_T_101 = 8'hFF; // @[Mux.scala:126:16] wire [7:0] _l_mask_mask_T_116 = 8'hFF; // @[Mux.scala:126:16] wire [7:0] _write_mask_mask_T_11 = 8'hFF; // @[Mux.scala:126:16] wire [7:0] _write_mask_mask_T_26 = 8'hFF; // @[Mux.scala:126:16] wire [7:0] _write_mask_mask_T_41 = 8'hFF; // @[Mux.scala:126:16] wire [7:0] _write_mask_mask_T_56 = 8'hFF; // @[Mux.scala:126:16] wire [7:0] _write_mask_mask_T_71 = 8'hFF; // @[Mux.scala:126:16] wire [7:0] _write_mask_mask_T_86 = 8'hFF; // @[Mux.scala:126:16] wire [7:0] _write_mask_mask_T_101 = 8'hFF; // @[Mux.scala:126:16] wire [7:0] _write_mask_mask_T_116 = 8'hFF; // @[Mux.scala:126:16] wire [38:0] _exe_sfence_WIRE_bits_addr = 39'h0; // @[lsu.scala:615:43] wire _exe_req_WIRE_0_valid = io_core_exe_0_req_valid_0; // @[lsu.scala:201:7, :383:33] wire [6:0] _exe_req_WIRE_0_bits_uop_uopc = io_core_exe_0_req_bits_uop_uopc_0; // @[lsu.scala:201:7, :383:33] wire [31:0] _exe_req_WIRE_0_bits_uop_inst = io_core_exe_0_req_bits_uop_inst_0; // @[lsu.scala:201:7, :383:33] wire [31:0] _exe_req_WIRE_0_bits_uop_debug_inst = io_core_exe_0_req_bits_uop_debug_inst_0; // @[lsu.scala:201:7, :383:33] wire _exe_req_WIRE_0_bits_uop_is_rvc = io_core_exe_0_req_bits_uop_is_rvc_0; // @[lsu.scala:201:7, :383:33] wire [39:0] _exe_req_WIRE_0_bits_uop_debug_pc = io_core_exe_0_req_bits_uop_debug_pc_0; // @[lsu.scala:201:7, :383:33] wire [2:0] _exe_req_WIRE_0_bits_uop_iq_type = io_core_exe_0_req_bits_uop_iq_type_0; // @[lsu.scala:201:7, :383:33] wire [9:0] _exe_req_WIRE_0_bits_uop_fu_code = io_core_exe_0_req_bits_uop_fu_code_0; // @[lsu.scala:201:7, :383:33] wire [3:0] _exe_req_WIRE_0_bits_uop_ctrl_br_type = io_core_exe_0_req_bits_uop_ctrl_br_type_0; // @[lsu.scala:201:7, :383:33] wire [1:0] _exe_req_WIRE_0_bits_uop_ctrl_op1_sel = io_core_exe_0_req_bits_uop_ctrl_op1_sel_0; // @[lsu.scala:201:7, :383:33] wire [2:0] _exe_req_WIRE_0_bits_uop_ctrl_op2_sel = io_core_exe_0_req_bits_uop_ctrl_op2_sel_0; // @[lsu.scala:201:7, :383:33] wire [2:0] _exe_req_WIRE_0_bits_uop_ctrl_imm_sel = io_core_exe_0_req_bits_uop_ctrl_imm_sel_0; // @[lsu.scala:201:7, :383:33] wire [4:0] _exe_req_WIRE_0_bits_uop_ctrl_op_fcn = io_core_exe_0_req_bits_uop_ctrl_op_fcn_0; // @[lsu.scala:201:7, :383:33] wire _exe_req_WIRE_0_bits_uop_ctrl_fcn_dw = io_core_exe_0_req_bits_uop_ctrl_fcn_dw_0; // @[lsu.scala:201:7, :383:33] wire [2:0] _exe_req_WIRE_0_bits_uop_ctrl_csr_cmd = io_core_exe_0_req_bits_uop_ctrl_csr_cmd_0; // @[lsu.scala:201:7, :383:33] wire _exe_req_WIRE_0_bits_uop_ctrl_is_load = io_core_exe_0_req_bits_uop_ctrl_is_load_0; // @[lsu.scala:201:7, :383:33] wire _exe_req_WIRE_0_bits_uop_ctrl_is_sta = io_core_exe_0_req_bits_uop_ctrl_is_sta_0; // @[lsu.scala:201:7, :383:33] wire _exe_req_WIRE_0_bits_uop_ctrl_is_std = io_core_exe_0_req_bits_uop_ctrl_is_std_0; // @[lsu.scala:201:7, :383:33] wire [1:0] _exe_req_WIRE_0_bits_uop_iw_state = io_core_exe_0_req_bits_uop_iw_state_0; // @[lsu.scala:201:7, :383:33] wire _exe_req_WIRE_0_bits_uop_iw_p1_poisoned = io_core_exe_0_req_bits_uop_iw_p1_poisoned_0; // @[lsu.scala:201:7, :383:33] wire _exe_req_WIRE_0_bits_uop_iw_p2_poisoned = io_core_exe_0_req_bits_uop_iw_p2_poisoned_0; // @[lsu.scala:201:7, :383:33] wire _exe_req_WIRE_0_bits_uop_is_br = io_core_exe_0_req_bits_uop_is_br_0; // @[lsu.scala:201:7, :383:33] wire _exe_req_WIRE_0_bits_uop_is_jalr = io_core_exe_0_req_bits_uop_is_jalr_0; // @[lsu.scala:201:7, :383:33] wire _exe_req_WIRE_0_bits_uop_is_jal = io_core_exe_0_req_bits_uop_is_jal_0; // @[lsu.scala:201:7, :383:33] wire _exe_req_WIRE_0_bits_uop_is_sfb = io_core_exe_0_req_bits_uop_is_sfb_0; // @[lsu.scala:201:7, :383:33] wire [7:0] _exe_req_WIRE_0_bits_uop_br_mask = io_core_exe_0_req_bits_uop_br_mask_0; // @[lsu.scala:201:7, :383:33] wire [2:0] _exe_req_WIRE_0_bits_uop_br_tag = io_core_exe_0_req_bits_uop_br_tag_0; // @[lsu.scala:201:7, :383:33] wire [3:0] _exe_req_WIRE_0_bits_uop_ftq_idx = io_core_exe_0_req_bits_uop_ftq_idx_0; // @[lsu.scala:201:7, :383:33] wire _exe_req_WIRE_0_bits_uop_edge_inst = io_core_exe_0_req_bits_uop_edge_inst_0; // @[lsu.scala:201:7, :383:33] wire [5:0] _exe_req_WIRE_0_bits_uop_pc_lob = io_core_exe_0_req_bits_uop_pc_lob_0; // @[lsu.scala:201:7, :383:33] wire _exe_req_WIRE_0_bits_uop_taken = io_core_exe_0_req_bits_uop_taken_0; // @[lsu.scala:201:7, :383:33] wire [19:0] _exe_req_WIRE_0_bits_uop_imm_packed = io_core_exe_0_req_bits_uop_imm_packed_0; // @[lsu.scala:201:7, :383:33] wire [11:0] _exe_req_WIRE_0_bits_uop_csr_addr = io_core_exe_0_req_bits_uop_csr_addr_0; // @[lsu.scala:201:7, :383:33] wire [4:0] _exe_req_WIRE_0_bits_uop_rob_idx = io_core_exe_0_req_bits_uop_rob_idx_0; // @[lsu.scala:201:7, :383:33] wire [2:0] _exe_req_WIRE_0_bits_uop_ldq_idx = io_core_exe_0_req_bits_uop_ldq_idx_0; // @[lsu.scala:201:7, :383:33] wire [2:0] _exe_req_WIRE_0_bits_uop_stq_idx = io_core_exe_0_req_bits_uop_stq_idx_0; // @[lsu.scala:201:7, :383:33] wire [1:0] _exe_req_WIRE_0_bits_uop_rxq_idx = io_core_exe_0_req_bits_uop_rxq_idx_0; // @[lsu.scala:201:7, :383:33] wire [5:0] _exe_req_WIRE_0_bits_uop_pdst = io_core_exe_0_req_bits_uop_pdst_0; // @[lsu.scala:201:7, :383:33] wire [5:0] _exe_req_WIRE_0_bits_uop_prs1 = io_core_exe_0_req_bits_uop_prs1_0; // @[lsu.scala:201:7, :383:33] wire [5:0] _exe_req_WIRE_0_bits_uop_prs2 = io_core_exe_0_req_bits_uop_prs2_0; // @[lsu.scala:201:7, :383:33] wire [5:0] _exe_req_WIRE_0_bits_uop_prs3 = io_core_exe_0_req_bits_uop_prs3_0; // @[lsu.scala:201:7, :383:33] wire [3:0] _exe_req_WIRE_0_bits_uop_ppred = io_core_exe_0_req_bits_uop_ppred_0; // @[lsu.scala:201:7, :383:33] wire _exe_req_WIRE_0_bits_uop_prs1_busy = io_core_exe_0_req_bits_uop_prs1_busy_0; // @[lsu.scala:201:7, :383:33] wire _exe_req_WIRE_0_bits_uop_prs2_busy = io_core_exe_0_req_bits_uop_prs2_busy_0; // @[lsu.scala:201:7, :383:33] wire _exe_req_WIRE_0_bits_uop_prs3_busy = io_core_exe_0_req_bits_uop_prs3_busy_0; // @[lsu.scala:201:7, :383:33] wire _exe_req_WIRE_0_bits_uop_ppred_busy = io_core_exe_0_req_bits_uop_ppred_busy_0; // @[lsu.scala:201:7, :383:33] wire [5:0] _exe_req_WIRE_0_bits_uop_stale_pdst = io_core_exe_0_req_bits_uop_stale_pdst_0; // @[lsu.scala:201:7, :383:33] wire _exe_req_WIRE_0_bits_uop_exception = io_core_exe_0_req_bits_uop_exception_0; // @[lsu.scala:201:7, :383:33] wire [63:0] _exe_req_WIRE_0_bits_uop_exc_cause = io_core_exe_0_req_bits_uop_exc_cause_0; // @[lsu.scala:201:7, :383:33] wire _exe_req_WIRE_0_bits_uop_bypassable = io_core_exe_0_req_bits_uop_bypassable_0; // @[lsu.scala:201:7, :383:33] wire [4:0] _exe_req_WIRE_0_bits_uop_mem_cmd = io_core_exe_0_req_bits_uop_mem_cmd_0; // @[lsu.scala:201:7, :383:33] wire [1:0] _exe_req_WIRE_0_bits_uop_mem_size = io_core_exe_0_req_bits_uop_mem_size_0; // @[lsu.scala:201:7, :383:33] wire _exe_req_WIRE_0_bits_uop_mem_signed = io_core_exe_0_req_bits_uop_mem_signed_0; // @[lsu.scala:201:7, :383:33] wire _exe_req_WIRE_0_bits_uop_is_fence = io_core_exe_0_req_bits_uop_is_fence_0; // @[lsu.scala:201:7, :383:33] wire _exe_req_WIRE_0_bits_uop_is_fencei = io_core_exe_0_req_bits_uop_is_fencei_0; // @[lsu.scala:201:7, :383:33] wire _exe_req_WIRE_0_bits_uop_is_amo = io_core_exe_0_req_bits_uop_is_amo_0; // @[lsu.scala:201:7, :383:33] wire _exe_req_WIRE_0_bits_uop_uses_ldq = io_core_exe_0_req_bits_uop_uses_ldq_0; // @[lsu.scala:201:7, :383:33] wire _exe_req_WIRE_0_bits_uop_uses_stq = io_core_exe_0_req_bits_uop_uses_stq_0; // @[lsu.scala:201:7, :383:33] wire _exe_req_WIRE_0_bits_uop_is_sys_pc2epc = io_core_exe_0_req_bits_uop_is_sys_pc2epc_0; // @[lsu.scala:201:7, :383:33] wire _exe_req_WIRE_0_bits_uop_is_unique = io_core_exe_0_req_bits_uop_is_unique_0; // @[lsu.scala:201:7, :383:33] wire _exe_req_WIRE_0_bits_uop_flush_on_commit = io_core_exe_0_req_bits_uop_flush_on_commit_0; // @[lsu.scala:201:7, :383:33] wire _exe_req_WIRE_0_bits_uop_ldst_is_rs1 = io_core_exe_0_req_bits_uop_ldst_is_rs1_0; // @[lsu.scala:201:7, :383:33] wire [5:0] _exe_req_WIRE_0_bits_uop_ldst = io_core_exe_0_req_bits_uop_ldst_0; // @[lsu.scala:201:7, :383:33] wire [5:0] _exe_req_WIRE_0_bits_uop_lrs1 = io_core_exe_0_req_bits_uop_lrs1_0; // @[lsu.scala:201:7, :383:33] wire [5:0] _exe_req_WIRE_0_bits_uop_lrs2 = io_core_exe_0_req_bits_uop_lrs2_0; // @[lsu.scala:201:7, :383:33] wire [5:0] _exe_req_WIRE_0_bits_uop_lrs3 = io_core_exe_0_req_bits_uop_lrs3_0; // @[lsu.scala:201:7, :383:33] wire _exe_req_WIRE_0_bits_uop_ldst_val = io_core_exe_0_req_bits_uop_ldst_val_0; // @[lsu.scala:201:7, :383:33] wire [1:0] _exe_req_WIRE_0_bits_uop_dst_rtype = io_core_exe_0_req_bits_uop_dst_rtype_0; // @[lsu.scala:201:7, :383:33] wire [1:0] _exe_req_WIRE_0_bits_uop_lrs1_rtype = io_core_exe_0_req_bits_uop_lrs1_rtype_0; // @[lsu.scala:201:7, :383:33] wire [1:0] _exe_req_WIRE_0_bits_uop_lrs2_rtype = io_core_exe_0_req_bits_uop_lrs2_rtype_0; // @[lsu.scala:201:7, :383:33] wire _exe_req_WIRE_0_bits_uop_frs3_en = io_core_exe_0_req_bits_uop_frs3_en_0; // @[lsu.scala:201:7, :383:33] wire _exe_req_WIRE_0_bits_uop_fp_val = io_core_exe_0_req_bits_uop_fp_val_0; // @[lsu.scala:201:7, :383:33] wire _exe_req_WIRE_0_bits_uop_fp_single = io_core_exe_0_req_bits_uop_fp_single_0; // @[lsu.scala:201:7, :383:33] wire _exe_req_WIRE_0_bits_uop_xcpt_pf_if = io_core_exe_0_req_bits_uop_xcpt_pf_if_0; // @[lsu.scala:201:7, :383:33] wire _exe_req_WIRE_0_bits_uop_xcpt_ae_if = io_core_exe_0_req_bits_uop_xcpt_ae_if_0; // @[lsu.scala:201:7, :383:33] wire _exe_req_WIRE_0_bits_uop_xcpt_ma_if = io_core_exe_0_req_bits_uop_xcpt_ma_if_0; // @[lsu.scala:201:7, :383:33] wire _exe_req_WIRE_0_bits_uop_bp_debug_if = io_core_exe_0_req_bits_uop_bp_debug_if_0; // @[lsu.scala:201:7, :383:33] wire _exe_req_WIRE_0_bits_uop_bp_xcpt_if = io_core_exe_0_req_bits_uop_bp_xcpt_if_0; // @[lsu.scala:201:7, :383:33] wire [1:0] _exe_req_WIRE_0_bits_uop_debug_fsrc = io_core_exe_0_req_bits_uop_debug_fsrc_0; // @[lsu.scala:201:7, :383:33] wire [1:0] _exe_req_WIRE_0_bits_uop_debug_tsrc = io_core_exe_0_req_bits_uop_debug_tsrc_0; // @[lsu.scala:201:7, :383:33] wire [63:0] _exe_req_WIRE_0_bits_data = io_core_exe_0_req_bits_data_0; // @[lsu.scala:201:7, :383:33] wire [39:0] _exe_req_WIRE_0_bits_addr = io_core_exe_0_req_bits_addr_0; // @[lsu.scala:201:7, :383:33] wire _exe_req_WIRE_0_bits_mxcpt_valid = io_core_exe_0_req_bits_mxcpt_valid_0; // @[lsu.scala:201:7, :383:33] wire [24:0] _exe_req_WIRE_0_bits_mxcpt_bits = io_core_exe_0_req_bits_mxcpt_bits_0; // @[lsu.scala:201:7, :383:33] wire _exe_req_WIRE_0_bits_sfence_valid = io_core_exe_0_req_bits_sfence_valid_0; // @[lsu.scala:201:7, :383:33] wire _exe_req_WIRE_0_bits_sfence_bits_rs1 = io_core_exe_0_req_bits_sfence_bits_rs1_0; // @[lsu.scala:201:7, :383:33] wire _exe_req_WIRE_0_bits_sfence_bits_rs2 = io_core_exe_0_req_bits_sfence_bits_rs2_0; // @[lsu.scala:201:7, :383:33] wire [38:0] _exe_req_WIRE_0_bits_sfence_bits_addr = io_core_exe_0_req_bits_sfence_bits_addr_0; // @[lsu.scala:201:7, :383:33] wire _exe_req_WIRE_0_bits_sfence_bits_asid = io_core_exe_0_req_bits_sfence_bits_asid_0; // @[lsu.scala:201:7, :383:33] wire _io_core_fp_stdata_ready_T_2; // @[lsu.scala:867:61] wire [6:0] mem_stdf_uop_out_uopc = io_core_fp_stdata_bits_uop_uopc_0; // @[util.scala:96:23] wire [31:0] mem_stdf_uop_out_inst = io_core_fp_stdata_bits_uop_inst_0; // @[util.scala:96:23] wire [31:0] mem_stdf_uop_out_debug_inst = io_core_fp_stdata_bits_uop_debug_inst_0; // @[util.scala:96:23] wire mem_stdf_uop_out_is_rvc = io_core_fp_stdata_bits_uop_is_rvc_0; // @[util.scala:96:23] wire [39:0] mem_stdf_uop_out_debug_pc = io_core_fp_stdata_bits_uop_debug_pc_0; // @[util.scala:96:23] wire [2:0] mem_stdf_uop_out_iq_type = io_core_fp_stdata_bits_uop_iq_type_0; // @[util.scala:96:23] wire [9:0] mem_stdf_uop_out_fu_code = io_core_fp_stdata_bits_uop_fu_code_0; // @[util.scala:96:23] wire [3:0] mem_stdf_uop_out_ctrl_br_type = io_core_fp_stdata_bits_uop_ctrl_br_type_0; // @[util.scala:96:23] wire [1:0] mem_stdf_uop_out_ctrl_op1_sel = io_core_fp_stdata_bits_uop_ctrl_op1_sel_0; // @[util.scala:96:23] wire [2:0] mem_stdf_uop_out_ctrl_op2_sel = io_core_fp_stdata_bits_uop_ctrl_op2_sel_0; // @[util.scala:96:23] wire [2:0] mem_stdf_uop_out_ctrl_imm_sel = io_core_fp_stdata_bits_uop_ctrl_imm_sel_0; // @[util.scala:96:23] wire [4:0] mem_stdf_uop_out_ctrl_op_fcn = io_core_fp_stdata_bits_uop_ctrl_op_fcn_0; // @[util.scala:96:23] wire mem_stdf_uop_out_ctrl_fcn_dw = io_core_fp_stdata_bits_uop_ctrl_fcn_dw_0; // @[util.scala:96:23] wire [2:0] mem_stdf_uop_out_ctrl_csr_cmd = io_core_fp_stdata_bits_uop_ctrl_csr_cmd_0; // @[util.scala:96:23] wire mem_stdf_uop_out_ctrl_is_load = io_core_fp_stdata_bits_uop_ctrl_is_load_0; // @[util.scala:96:23] wire mem_stdf_uop_out_ctrl_is_sta = io_core_fp_stdata_bits_uop_ctrl_is_sta_0; // @[util.scala:96:23] wire mem_stdf_uop_out_ctrl_is_std = io_core_fp_stdata_bits_uop_ctrl_is_std_0; // @[util.scala:96:23] wire [1:0] mem_stdf_uop_out_iw_state = io_core_fp_stdata_bits_uop_iw_state_0; // @[util.scala:96:23] wire mem_stdf_uop_out_iw_p1_poisoned = io_core_fp_stdata_bits_uop_iw_p1_poisoned_0; // @[util.scala:96:23] wire mem_stdf_uop_out_iw_p2_poisoned = io_core_fp_stdata_bits_uop_iw_p2_poisoned_0; // @[util.scala:96:23] wire mem_stdf_uop_out_is_br = io_core_fp_stdata_bits_uop_is_br_0; // @[util.scala:96:23] wire mem_stdf_uop_out_is_jalr = io_core_fp_stdata_bits_uop_is_jalr_0; // @[util.scala:96:23] wire mem_stdf_uop_out_is_jal = io_core_fp_stdata_bits_uop_is_jal_0; // @[util.scala:96:23] wire mem_stdf_uop_out_is_sfb = io_core_fp_stdata_bits_uop_is_sfb_0; // @[util.scala:96:23] wire [2:0] mem_stdf_uop_out_br_tag = io_core_fp_stdata_bits_uop_br_tag_0; // @[util.scala:96:23] wire [3:0] mem_stdf_uop_out_ftq_idx = io_core_fp_stdata_bits_uop_ftq_idx_0; // @[util.scala:96:23] wire mem_stdf_uop_out_edge_inst = io_core_fp_stdata_bits_uop_edge_inst_0; // @[util.scala:96:23] wire [5:0] mem_stdf_uop_out_pc_lob = io_core_fp_stdata_bits_uop_pc_lob_0; // @[util.scala:96:23] wire mem_stdf_uop_out_taken = io_core_fp_stdata_bits_uop_taken_0; // @[util.scala:96:23] wire [19:0] mem_stdf_uop_out_imm_packed = io_core_fp_stdata_bits_uop_imm_packed_0; // @[util.scala:96:23] wire [11:0] mem_stdf_uop_out_csr_addr = io_core_fp_stdata_bits_uop_csr_addr_0; // @[util.scala:96:23] wire [4:0] mem_stdf_uop_out_rob_idx = io_core_fp_stdata_bits_uop_rob_idx_0; // @[util.scala:96:23] wire [2:0] mem_stdf_uop_out_ldq_idx = io_core_fp_stdata_bits_uop_ldq_idx_0; // @[util.scala:96:23] wire [2:0] mem_stdf_uop_out_stq_idx = io_core_fp_stdata_bits_uop_stq_idx_0; // @[util.scala:96:23] wire [1:0] mem_stdf_uop_out_rxq_idx = io_core_fp_stdata_bits_uop_rxq_idx_0; // @[util.scala:96:23] wire [5:0] mem_stdf_uop_out_pdst = io_core_fp_stdata_bits_uop_pdst_0; // @[util.scala:96:23] wire [5:0] mem_stdf_uop_out_prs1 = io_core_fp_stdata_bits_uop_prs1_0; // @[util.scala:96:23] wire [5:0] mem_stdf_uop_out_prs2 = io_core_fp_stdata_bits_uop_prs2_0; // @[util.scala:96:23] wire [5:0] mem_stdf_uop_out_prs3 = io_core_fp_stdata_bits_uop_prs3_0; // @[util.scala:96:23] wire [3:0] mem_stdf_uop_out_ppred = io_core_fp_stdata_bits_uop_ppred_0; // @[util.scala:96:23] wire mem_stdf_uop_out_prs1_busy = io_core_fp_stdata_bits_uop_prs1_busy_0; // @[util.scala:96:23] wire mem_stdf_uop_out_prs2_busy = io_core_fp_stdata_bits_uop_prs2_busy_0; // @[util.scala:96:23] wire mem_stdf_uop_out_prs3_busy = io_core_fp_stdata_bits_uop_prs3_busy_0; // @[util.scala:96:23] wire mem_stdf_uop_out_ppred_busy = io_core_fp_stdata_bits_uop_ppred_busy_0; // @[util.scala:96:23] wire [5:0] mem_stdf_uop_out_stale_pdst = io_core_fp_stdata_bits_uop_stale_pdst_0; // @[util.scala:96:23] wire mem_stdf_uop_out_exception = io_core_fp_stdata_bits_uop_exception_0; // @[util.scala:96:23] wire [63:0] mem_stdf_uop_out_exc_cause = io_core_fp_stdata_bits_uop_exc_cause_0; // @[util.scala:96:23] wire mem_stdf_uop_out_bypassable = io_core_fp_stdata_bits_uop_bypassable_0; // @[util.scala:96:23] wire [4:0] mem_stdf_uop_out_mem_cmd = io_core_fp_stdata_bits_uop_mem_cmd_0; // @[util.scala:96:23] wire [1:0] mem_stdf_uop_out_mem_size = io_core_fp_stdata_bits_uop_mem_size_0; // @[util.scala:96:23] wire mem_stdf_uop_out_mem_signed = io_core_fp_stdata_bits_uop_mem_signed_0; // @[util.scala:96:23] wire mem_stdf_uop_out_is_fence = io_core_fp_stdata_bits_uop_is_fence_0; // @[util.scala:96:23] wire mem_stdf_uop_out_is_fencei = io_core_fp_stdata_bits_uop_is_fencei_0; // @[util.scala:96:23] wire mem_stdf_uop_out_is_amo = io_core_fp_stdata_bits_uop_is_amo_0; // @[util.scala:96:23] wire mem_stdf_uop_out_uses_ldq = io_core_fp_stdata_bits_uop_uses_ldq_0; // @[util.scala:96:23] wire mem_stdf_uop_out_uses_stq = io_core_fp_stdata_bits_uop_uses_stq_0; // @[util.scala:96:23] wire mem_stdf_uop_out_is_sys_pc2epc = io_core_fp_stdata_bits_uop_is_sys_pc2epc_0; // @[util.scala:96:23] wire mem_stdf_uop_out_is_unique = io_core_fp_stdata_bits_uop_is_unique_0; // @[util.scala:96:23] wire mem_stdf_uop_out_flush_on_commit = io_core_fp_stdata_bits_uop_flush_on_commit_0; // @[util.scala:96:23] wire mem_stdf_uop_out_ldst_is_rs1 = io_core_fp_stdata_bits_uop_ldst_is_rs1_0; // @[util.scala:96:23] wire [5:0] mem_stdf_uop_out_ldst = io_core_fp_stdata_bits_uop_ldst_0; // @[util.scala:96:23] wire [5:0] mem_stdf_uop_out_lrs1 = io_core_fp_stdata_bits_uop_lrs1_0; // @[util.scala:96:23] wire [5:0] mem_stdf_uop_out_lrs2 = io_core_fp_stdata_bits_uop_lrs2_0; // @[util.scala:96:23] wire [5:0] mem_stdf_uop_out_lrs3 = io_core_fp_stdata_bits_uop_lrs3_0; // @[util.scala:96:23] wire mem_stdf_uop_out_ldst_val = io_core_fp_stdata_bits_uop_ldst_val_0; // @[util.scala:96:23] wire [1:0] mem_stdf_uop_out_dst_rtype = io_core_fp_stdata_bits_uop_dst_rtype_0; // @[util.scala:96:23] wire [1:0] mem_stdf_uop_out_lrs1_rtype = io_core_fp_stdata_bits_uop_lrs1_rtype_0; // @[util.scala:96:23] wire [1:0] mem_stdf_uop_out_lrs2_rtype = io_core_fp_stdata_bits_uop_lrs2_rtype_0; // @[util.scala:96:23] wire mem_stdf_uop_out_frs3_en = io_core_fp_stdata_bits_uop_frs3_en_0; // @[util.scala:96:23] wire mem_stdf_uop_out_fp_val = io_core_fp_stdata_bits_uop_fp_val_0; // @[util.scala:96:23] wire mem_stdf_uop_out_fp_single = io_core_fp_stdata_bits_uop_fp_single_0; // @[util.scala:96:23] wire mem_stdf_uop_out_xcpt_pf_if = io_core_fp_stdata_bits_uop_xcpt_pf_if_0; // @[util.scala:96:23] wire mem_stdf_uop_out_xcpt_ae_if = io_core_fp_stdata_bits_uop_xcpt_ae_if_0; // @[util.scala:96:23] wire mem_stdf_uop_out_xcpt_ma_if = io_core_fp_stdata_bits_uop_xcpt_ma_if_0; // @[util.scala:96:23] wire mem_stdf_uop_out_bp_debug_if = io_core_fp_stdata_bits_uop_bp_debug_if_0; // @[util.scala:96:23] wire mem_stdf_uop_out_bp_xcpt_if = io_core_fp_stdata_bits_uop_bp_xcpt_if_0; // @[util.scala:96:23] wire [1:0] mem_stdf_uop_out_debug_fsrc = io_core_fp_stdata_bits_uop_debug_fsrc_0; // @[util.scala:96:23] wire [1:0] mem_stdf_uop_out_debug_tsrc = io_core_fp_stdata_bits_uop_debug_tsrc_0; // @[util.scala:96:23] wire _io_core_clr_bsy_0_valid_T_9; // @[lsu.scala:980:82] wire _io_core_clr_bsy_1_valid_T_9; // @[lsu.scala:1005:87] wire _io_core_spec_ld_wakeup_0_valid_T_4; // @[lsu.scala:1261:69] wire [7:0] io_dmem_brupdate_b1_resolve_mask_0 = io_core_brupdate_b1_resolve_mask_0; // @[lsu.scala:201:7] wire [7:0] io_dmem_brupdate_b1_mispredict_mask_0 = io_core_brupdate_b1_mispredict_mask_0; // @[lsu.scala:201:7] wire [6:0] io_dmem_brupdate_b2_uop_uopc_0 = io_core_brupdate_b2_uop_uopc_0; // @[lsu.scala:201:7] wire [31:0] io_dmem_brupdate_b2_uop_inst_0 = io_core_brupdate_b2_uop_inst_0; // @[lsu.scala:201:7] wire [31:0] io_dmem_brupdate_b2_uop_debug_inst_0 = io_core_brupdate_b2_uop_debug_inst_0; // @[lsu.scala:201:7] wire io_dmem_brupdate_b2_uop_is_rvc_0 = io_core_brupdate_b2_uop_is_rvc_0; // @[lsu.scala:201:7] wire [39:0] io_dmem_brupdate_b2_uop_debug_pc_0 = io_core_brupdate_b2_uop_debug_pc_0; // @[lsu.scala:201:7] wire [2:0] io_dmem_brupdate_b2_uop_iq_type_0 = io_core_brupdate_b2_uop_iq_type_0; // @[lsu.scala:201:7] wire [9:0] io_dmem_brupdate_b2_uop_fu_code_0 = io_core_brupdate_b2_uop_fu_code_0; // @[lsu.scala:201:7] wire [3:0] io_dmem_brupdate_b2_uop_ctrl_br_type_0 = io_core_brupdate_b2_uop_ctrl_br_type_0; // @[lsu.scala:201:7] wire [1:0] io_dmem_brupdate_b2_uop_ctrl_op1_sel_0 = io_core_brupdate_b2_uop_ctrl_op1_sel_0; // @[lsu.scala:201:7] wire [2:0] io_dmem_brupdate_b2_uop_ctrl_op2_sel_0 = io_core_brupdate_b2_uop_ctrl_op2_sel_0; // @[lsu.scala:201:7] wire [2:0] io_dmem_brupdate_b2_uop_ctrl_imm_sel_0 = io_core_brupdate_b2_uop_ctrl_imm_sel_0; // @[lsu.scala:201:7] wire [4:0] io_dmem_brupdate_b2_uop_ctrl_op_fcn_0 = io_core_brupdate_b2_uop_ctrl_op_fcn_0; // @[lsu.scala:201:7] wire io_dmem_brupdate_b2_uop_ctrl_fcn_dw_0 = io_core_brupdate_b2_uop_ctrl_fcn_dw_0; // @[lsu.scala:201:7] wire [2:0] io_dmem_brupdate_b2_uop_ctrl_csr_cmd_0 = io_core_brupdate_b2_uop_ctrl_csr_cmd_0; // @[lsu.scala:201:7] wire io_dmem_brupdate_b2_uop_ctrl_is_load_0 = io_core_brupdate_b2_uop_ctrl_is_load_0; // @[lsu.scala:201:7] wire io_dmem_brupdate_b2_uop_ctrl_is_sta_0 = io_core_brupdate_b2_uop_ctrl_is_sta_0; // @[lsu.scala:201:7] wire io_dmem_brupdate_b2_uop_ctrl_is_std_0 = io_core_brupdate_b2_uop_ctrl_is_std_0; // @[lsu.scala:201:7] wire [1:0] io_dmem_brupdate_b2_uop_iw_state_0 = io_core_brupdate_b2_uop_iw_state_0; // @[lsu.scala:201:7] wire io_dmem_brupdate_b2_uop_iw_p1_poisoned_0 = io_core_brupdate_b2_uop_iw_p1_poisoned_0; // @[lsu.scala:201:7] wire io_dmem_brupdate_b2_uop_iw_p2_poisoned_0 = io_core_brupdate_b2_uop_iw_p2_poisoned_0; // @[lsu.scala:201:7] wire io_dmem_brupdate_b2_uop_is_br_0 = io_core_brupdate_b2_uop_is_br_0; // @[lsu.scala:201:7] wire io_dmem_brupdate_b2_uop_is_jalr_0 = io_core_brupdate_b2_uop_is_jalr_0; // @[lsu.scala:201:7] wire io_dmem_brupdate_b2_uop_is_jal_0 = io_core_brupdate_b2_uop_is_jal_0; // @[lsu.scala:201:7] wire io_dmem_brupdate_b2_uop_is_sfb_0 = io_core_brupdate_b2_uop_is_sfb_0; // @[lsu.scala:201:7] wire [7:0] io_dmem_brupdate_b2_uop_br_mask_0 = io_core_brupdate_b2_uop_br_mask_0; // @[lsu.scala:201:7] wire [2:0] io_dmem_brupdate_b2_uop_br_tag_0 = io_core_brupdate_b2_uop_br_tag_0; // @[lsu.scala:201:7] wire [3:0] io_dmem_brupdate_b2_uop_ftq_idx_0 = io_core_brupdate_b2_uop_ftq_idx_0; // @[lsu.scala:201:7] wire io_dmem_brupdate_b2_uop_edge_inst_0 = io_core_brupdate_b2_uop_edge_inst_0; // @[lsu.scala:201:7] wire [5:0] io_dmem_brupdate_b2_uop_pc_lob_0 = io_core_brupdate_b2_uop_pc_lob_0; // @[lsu.scala:201:7] wire io_dmem_brupdate_b2_uop_taken_0 = io_core_brupdate_b2_uop_taken_0; // @[lsu.scala:201:7] wire [19:0] io_dmem_brupdate_b2_uop_imm_packed_0 = io_core_brupdate_b2_uop_imm_packed_0; // @[lsu.scala:201:7] wire [11:0] io_dmem_brupdate_b2_uop_csr_addr_0 = io_core_brupdate_b2_uop_csr_addr_0; // @[lsu.scala:201:7] wire [4:0] io_dmem_brupdate_b2_uop_rob_idx_0 = io_core_brupdate_b2_uop_rob_idx_0; // @[lsu.scala:201:7] wire [2:0] io_dmem_brupdate_b2_uop_ldq_idx_0 = io_core_brupdate_b2_uop_ldq_idx_0; // @[lsu.scala:201:7] wire [2:0] io_dmem_brupdate_b2_uop_stq_idx_0 = io_core_brupdate_b2_uop_stq_idx_0; // @[lsu.scala:201:7] wire [1:0] io_dmem_brupdate_b2_uop_rxq_idx_0 = io_core_brupdate_b2_uop_rxq_idx_0; // @[lsu.scala:201:7] wire [5:0] io_dmem_brupdate_b2_uop_pdst_0 = io_core_brupdate_b2_uop_pdst_0; // @[lsu.scala:201:7] wire [5:0] io_dmem_brupdate_b2_uop_prs1_0 = io_core_brupdate_b2_uop_prs1_0; // @[lsu.scala:201:7] wire [5:0] io_dmem_brupdate_b2_uop_prs2_0 = io_core_brupdate_b2_uop_prs2_0; // @[lsu.scala:201:7] wire [5:0] io_dmem_brupdate_b2_uop_prs3_0 = io_core_brupdate_b2_uop_prs3_0; // @[lsu.scala:201:7] wire [3:0] io_dmem_brupdate_b2_uop_ppred_0 = io_core_brupdate_b2_uop_ppred_0; // @[lsu.scala:201:7] wire io_dmem_brupdate_b2_uop_prs1_busy_0 = io_core_brupdate_b2_uop_prs1_busy_0; // @[lsu.scala:201:7] wire io_dmem_brupdate_b2_uop_prs2_busy_0 = io_core_brupdate_b2_uop_prs2_busy_0; // @[lsu.scala:201:7] wire io_dmem_brupdate_b2_uop_prs3_busy_0 = io_core_brupdate_b2_uop_prs3_busy_0; // @[lsu.scala:201:7] wire io_dmem_brupdate_b2_uop_ppred_busy_0 = io_core_brupdate_b2_uop_ppred_busy_0; // @[lsu.scala:201:7] wire [5:0] io_dmem_brupdate_b2_uop_stale_pdst_0 = io_core_brupdate_b2_uop_stale_pdst_0; // @[lsu.scala:201:7] wire io_dmem_brupdate_b2_uop_exception_0 = io_core_brupdate_b2_uop_exception_0; // @[lsu.scala:201:7] wire [63:0] io_dmem_brupdate_b2_uop_exc_cause_0 = io_core_brupdate_b2_uop_exc_cause_0; // @[lsu.scala:201:7] wire io_dmem_brupdate_b2_uop_bypassable_0 = io_core_brupdate_b2_uop_bypassable_0; // @[lsu.scala:201:7] wire [4:0] io_dmem_brupdate_b2_uop_mem_cmd_0 = io_core_brupdate_b2_uop_mem_cmd_0; // @[lsu.scala:201:7] wire [1:0] io_dmem_brupdate_b2_uop_mem_size_0 = io_core_brupdate_b2_uop_mem_size_0; // @[lsu.scala:201:7] wire io_dmem_brupdate_b2_uop_mem_signed_0 = io_core_brupdate_b2_uop_mem_signed_0; // @[lsu.scala:201:7] wire io_dmem_brupdate_b2_uop_is_fence_0 = io_core_brupdate_b2_uop_is_fence_0; // @[lsu.scala:201:7] wire io_dmem_brupdate_b2_uop_is_fencei_0 = io_core_brupdate_b2_uop_is_fencei_0; // @[lsu.scala:201:7] wire io_dmem_brupdate_b2_uop_is_amo_0 = io_core_brupdate_b2_uop_is_amo_0; // @[lsu.scala:201:7] wire io_dmem_brupdate_b2_uop_uses_ldq_0 = io_core_brupdate_b2_uop_uses_ldq_0; // @[lsu.scala:201:7] wire io_dmem_brupdate_b2_uop_uses_stq_0 = io_core_brupdate_b2_uop_uses_stq_0; // @[lsu.scala:201:7] wire io_dmem_brupdate_b2_uop_is_sys_pc2epc_0 = io_core_brupdate_b2_uop_is_sys_pc2epc_0; // @[lsu.scala:201:7] wire io_dmem_brupdate_b2_uop_is_unique_0 = io_core_brupdate_b2_uop_is_unique_0; // @[lsu.scala:201:7] wire io_dmem_brupdate_b2_uop_flush_on_commit_0 = io_core_brupdate_b2_uop_flush_on_commit_0; // @[lsu.scala:201:7] wire io_dmem_brupdate_b2_uop_ldst_is_rs1_0 = io_core_brupdate_b2_uop_ldst_is_rs1_0; // @[lsu.scala:201:7] wire [5:0] io_dmem_brupdate_b2_uop_ldst_0 = io_core_brupdate_b2_uop_ldst_0; // @[lsu.scala:201:7] wire [5:0] io_dmem_brupdate_b2_uop_lrs1_0 = io_core_brupdate_b2_uop_lrs1_0; // @[lsu.scala:201:7] wire [5:0] io_dmem_brupdate_b2_uop_lrs2_0 = io_core_brupdate_b2_uop_lrs2_0; // @[lsu.scala:201:7] wire [5:0] io_dmem_brupdate_b2_uop_lrs3_0 = io_core_brupdate_b2_uop_lrs3_0; // @[lsu.scala:201:7] wire io_dmem_brupdate_b2_uop_ldst_val_0 = io_core_brupdate_b2_uop_ldst_val_0; // @[lsu.scala:201:7] wire [1:0] io_dmem_brupdate_b2_uop_dst_rtype_0 = io_core_brupdate_b2_uop_dst_rtype_0; // @[lsu.scala:201:7] wire [1:0] io_dmem_brupdate_b2_uop_lrs1_rtype_0 = io_core_brupdate_b2_uop_lrs1_rtype_0; // @[lsu.scala:201:7] wire [1:0] io_dmem_brupdate_b2_uop_lrs2_rtype_0 = io_core_brupdate_b2_uop_lrs2_rtype_0; // @[lsu.scala:201:7] wire io_dmem_brupdate_b2_uop_frs3_en_0 = io_core_brupdate_b2_uop_frs3_en_0; // @[lsu.scala:201:7] wire io_dmem_brupdate_b2_uop_fp_val_0 = io_core_brupdate_b2_uop_fp_val_0; // @[lsu.scala:201:7] wire io_dmem_brupdate_b2_uop_fp_single_0 = io_core_brupdate_b2_uop_fp_single_0; // @[lsu.scala:201:7] wire io_dmem_brupdate_b2_uop_xcpt_pf_if_0 = io_core_brupdate_b2_uop_xcpt_pf_if_0; // @[lsu.scala:201:7] wire io_dmem_brupdate_b2_uop_xcpt_ae_if_0 = io_core_brupdate_b2_uop_xcpt_ae_if_0; // @[lsu.scala:201:7] wire io_dmem_brupdate_b2_uop_xcpt_ma_if_0 = io_core_brupdate_b2_uop_xcpt_ma_if_0; // @[lsu.scala:201:7] wire io_dmem_brupdate_b2_uop_bp_debug_if_0 = io_core_brupdate_b2_uop_bp_debug_if_0; // @[lsu.scala:201:7] wire io_dmem_brupdate_b2_uop_bp_xcpt_if_0 = io_core_brupdate_b2_uop_bp_xcpt_if_0; // @[lsu.scala:201:7] wire [1:0] io_dmem_brupdate_b2_uop_debug_fsrc_0 = io_core_brupdate_b2_uop_debug_fsrc_0; // @[lsu.scala:201:7] wire [1:0] io_dmem_brupdate_b2_uop_debug_tsrc_0 = io_core_brupdate_b2_uop_debug_tsrc_0; // @[lsu.scala:201:7] wire io_dmem_brupdate_b2_valid_0 = io_core_brupdate_b2_valid_0; // @[lsu.scala:201:7] wire io_dmem_brupdate_b2_mispredict_0 = io_core_brupdate_b2_mispredict_0; // @[lsu.scala:201:7] wire io_dmem_brupdate_b2_taken_0 = io_core_brupdate_b2_taken_0; // @[lsu.scala:201:7] wire [2:0] io_dmem_brupdate_b2_cfi_type_0 = io_core_brupdate_b2_cfi_type_0; // @[lsu.scala:201:7] wire [1:0] io_dmem_brupdate_b2_pc_sel_0 = io_core_brupdate_b2_pc_sel_0; // @[lsu.scala:201:7] wire [39:0] io_dmem_brupdate_b2_jalr_target_0 = io_core_brupdate_b2_jalr_target_0; // @[lsu.scala:201:7] wire [20:0] io_dmem_brupdate_b2_target_offset_0 = io_core_brupdate_b2_target_offset_0; // @[lsu.scala:201:7] wire [4:0] io_dmem_rob_pnr_idx_0 = io_core_rob_pnr_idx_0; // @[lsu.scala:201:7] wire [4:0] io_dmem_rob_head_idx_0 = io_core_rob_head_idx_0; // @[lsu.scala:201:7] wire io_dmem_exception_0 = io_core_exception_0; // @[lsu.scala:201:7] wire _io_core_fencei_rdy_T_1; // @[lsu.scala:347:42] wire _io_core_lxcpt_valid_T_5; // @[lsu.scala:1254:61] wire _io_core_perf_tlbMiss_T; // @[Decoupled.scala:51:35] wire dmem_req_0_valid; // @[lsu.scala:750:22] wire [6:0] dmem_req_0_bits_uop_uopc; // @[lsu.scala:750:22] wire [31:0] dmem_req_0_bits_uop_inst; // @[lsu.scala:750:22] wire [31:0] dmem_req_0_bits_uop_debug_inst; // @[lsu.scala:750:22] wire dmem_req_0_bits_uop_is_rvc; // @[lsu.scala:750:22] wire [39:0] dmem_req_0_bits_uop_debug_pc; // @[lsu.scala:750:22] wire [2:0] dmem_req_0_bits_uop_iq_type; // @[lsu.scala:750:22] wire [9:0] dmem_req_0_bits_uop_fu_code; // @[lsu.scala:750:22] wire [3:0] dmem_req_0_bits_uop_ctrl_br_type; // @[lsu.scala:750:22] wire [1:0] dmem_req_0_bits_uop_ctrl_op1_sel; // @[lsu.scala:750:22] wire [2:0] dmem_req_0_bits_uop_ctrl_op2_sel; // @[lsu.scala:750:22] wire [2:0] dmem_req_0_bits_uop_ctrl_imm_sel; // @[lsu.scala:750:22] wire [4:0] dmem_req_0_bits_uop_ctrl_op_fcn; // @[lsu.scala:750:22] wire dmem_req_0_bits_uop_ctrl_fcn_dw; // @[lsu.scala:750:22] wire [2:0] dmem_req_0_bits_uop_ctrl_csr_cmd; // @[lsu.scala:750:22] wire dmem_req_0_bits_uop_ctrl_is_load; // @[lsu.scala:750:22] wire dmem_req_0_bits_uop_ctrl_is_sta; // @[lsu.scala:750:22] wire dmem_req_0_bits_uop_ctrl_is_std; // @[lsu.scala:750:22] wire [1:0] dmem_req_0_bits_uop_iw_state; // @[lsu.scala:750:22] wire dmem_req_0_bits_uop_iw_p1_poisoned; // @[lsu.scala:750:22] wire dmem_req_0_bits_uop_iw_p2_poisoned; // @[lsu.scala:750:22] wire dmem_req_0_bits_uop_is_br; // @[lsu.scala:750:22] wire dmem_req_0_bits_uop_is_jalr; // @[lsu.scala:750:22] wire dmem_req_0_bits_uop_is_jal; // @[lsu.scala:750:22] wire dmem_req_0_bits_uop_is_sfb; // @[lsu.scala:750:22] wire [7:0] dmem_req_0_bits_uop_br_mask; // @[lsu.scala:750:22] wire [2:0] dmem_req_0_bits_uop_br_tag; // @[lsu.scala:750:22] wire [3:0] dmem_req_0_bits_uop_ftq_idx; // @[lsu.scala:750:22] wire dmem_req_0_bits_uop_edge_inst; // @[lsu.scala:750:22] wire [5:0] dmem_req_0_bits_uop_pc_lob; // @[lsu.scala:750:22] wire dmem_req_0_bits_uop_taken; // @[lsu.scala:750:22] wire [19:0] dmem_req_0_bits_uop_imm_packed; // @[lsu.scala:750:22] wire [11:0] dmem_req_0_bits_uop_csr_addr; // @[lsu.scala:750:22] wire [4:0] dmem_req_0_bits_uop_rob_idx; // @[lsu.scala:750:22] wire [2:0] dmem_req_0_bits_uop_ldq_idx; // @[lsu.scala:750:22] wire [2:0] dmem_req_0_bits_uop_stq_idx; // @[lsu.scala:750:22] wire [1:0] dmem_req_0_bits_uop_rxq_idx; // @[lsu.scala:750:22] wire [5:0] dmem_req_0_bits_uop_pdst; // @[lsu.scala:750:22] wire [5:0] dmem_req_0_bits_uop_prs1; // @[lsu.scala:750:22] wire [5:0] dmem_req_0_bits_uop_prs2; // @[lsu.scala:750:22] wire [5:0] dmem_req_0_bits_uop_prs3; // @[lsu.scala:750:22] wire [3:0] dmem_req_0_bits_uop_ppred; // @[lsu.scala:750:22] wire dmem_req_0_bits_uop_prs1_busy; // @[lsu.scala:750:22] wire dmem_req_0_bits_uop_prs2_busy; // @[lsu.scala:750:22] wire dmem_req_0_bits_uop_prs3_busy; // @[lsu.scala:750:22] wire dmem_req_0_bits_uop_ppred_busy; // @[lsu.scala:750:22] wire [5:0] dmem_req_0_bits_uop_stale_pdst; // @[lsu.scala:750:22] wire dmem_req_0_bits_uop_exception; // @[lsu.scala:750:22] wire [63:0] dmem_req_0_bits_uop_exc_cause; // @[lsu.scala:750:22] wire dmem_req_0_bits_uop_bypassable; // @[lsu.scala:750:22] wire [4:0] dmem_req_0_bits_uop_mem_cmd; // @[lsu.scala:750:22] wire [1:0] dmem_req_0_bits_uop_mem_size; // @[lsu.scala:750:22] wire dmem_req_0_bits_uop_mem_signed; // @[lsu.scala:750:22] wire dmem_req_0_bits_uop_is_fence; // @[lsu.scala:750:22] wire dmem_req_0_bits_uop_is_fencei; // @[lsu.scala:750:22] wire dmem_req_0_bits_uop_is_amo; // @[lsu.scala:750:22] wire dmem_req_0_bits_uop_uses_ldq; // @[lsu.scala:750:22] wire dmem_req_0_bits_uop_uses_stq; // @[lsu.scala:750:22] wire dmem_req_0_bits_uop_is_sys_pc2epc; // @[lsu.scala:750:22] wire dmem_req_0_bits_uop_is_unique; // @[lsu.scala:750:22] wire dmem_req_0_bits_uop_flush_on_commit; // @[lsu.scala:750:22] wire dmem_req_0_bits_uop_ldst_is_rs1; // @[lsu.scala:750:22] wire [5:0] dmem_req_0_bits_uop_ldst; // @[lsu.scala:750:22] wire [5:0] dmem_req_0_bits_uop_lrs1; // @[lsu.scala:750:22] wire [5:0] dmem_req_0_bits_uop_lrs2; // @[lsu.scala:750:22] wire [5:0] dmem_req_0_bits_uop_lrs3; // @[lsu.scala:750:22] wire dmem_req_0_bits_uop_ldst_val; // @[lsu.scala:750:22] wire [1:0] dmem_req_0_bits_uop_dst_rtype; // @[lsu.scala:750:22] wire [1:0] dmem_req_0_bits_uop_lrs1_rtype; // @[lsu.scala:750:22] wire [1:0] dmem_req_0_bits_uop_lrs2_rtype; // @[lsu.scala:750:22] wire dmem_req_0_bits_uop_frs3_en; // @[lsu.scala:750:22] wire dmem_req_0_bits_uop_fp_val; // @[lsu.scala:750:22] wire dmem_req_0_bits_uop_fp_single; // @[lsu.scala:750:22] wire dmem_req_0_bits_uop_xcpt_pf_if; // @[lsu.scala:750:22] wire dmem_req_0_bits_uop_xcpt_ae_if; // @[lsu.scala:750:22] wire dmem_req_0_bits_uop_xcpt_ma_if; // @[lsu.scala:750:22] wire dmem_req_0_bits_uop_bp_debug_if; // @[lsu.scala:750:22] wire dmem_req_0_bits_uop_bp_xcpt_if; // @[lsu.scala:750:22] wire [1:0] dmem_req_0_bits_uop_debug_fsrc; // @[lsu.scala:750:22] wire [1:0] dmem_req_0_bits_uop_debug_tsrc; // @[lsu.scala:750:22] wire [39:0] dmem_req_0_bits_addr; // @[lsu.scala:750:22] wire [63:0] dmem_req_0_bits_data; // @[lsu.scala:750:22] wire dmem_req_0_bits_is_hella; // @[lsu.scala:750:22] wire [63:0] io_hellacache_resp_bits_data_0 = io_dmem_resp_0_bits_data_0; // @[lsu.scala:201:7] wire will_fire_release_0; // @[lsu.scala:377:38] wire _can_fire_release_T = io_dmem_release_valid_0; // @[lsu.scala:201:7, :459:66] wire io_core_perf_acquire_0 = io_dmem_perf_acquire_0; // @[lsu.scala:201:7] wire io_core_perf_release_0 = io_dmem_perf_release_0; // @[lsu.scala:201:7] wire _io_hellacache_store_pending_T_6; // @[lsu.scala:1530:59] wire [26:0] io_ptw_req_bits_bits_addr_0; // @[lsu.scala:201:7] wire io_ptw_req_bits_valid_0; // @[lsu.scala:201:7] wire io_ptw_req_valid_0; // @[lsu.scala:201:7] wire [3:0] io_core_exe_0_iresp_bits_uop_ctrl_br_type_0; // @[lsu.scala:201:7] wire [1:0] io_core_exe_0_iresp_bits_uop_ctrl_op1_sel_0; // @[lsu.scala:201:7] wire [2:0] io_core_exe_0_iresp_bits_uop_ctrl_op2_sel_0; // @[lsu.scala:201:7] wire [2:0] io_core_exe_0_iresp_bits_uop_ctrl_imm_sel_0; // @[lsu.scala:201:7] wire [4:0] io_core_exe_0_iresp_bits_uop_ctrl_op_fcn_0; // @[lsu.scala:201:7] wire io_core_exe_0_iresp_bits_uop_ctrl_fcn_dw_0; // @[lsu.scala:201:7] wire [2:0] io_core_exe_0_iresp_bits_uop_ctrl_csr_cmd_0; // @[lsu.scala:201:7] wire io_core_exe_0_iresp_bits_uop_ctrl_is_load_0; // @[lsu.scala:201:7] wire io_core_exe_0_iresp_bits_uop_ctrl_is_sta_0; // @[lsu.scala:201:7] wire io_core_exe_0_iresp_bits_uop_ctrl_is_std_0; // @[lsu.scala:201:7] wire [6:0] io_core_exe_0_iresp_bits_uop_uopc_0; // @[lsu.scala:201:7] wire [31:0] io_core_exe_0_iresp_bits_uop_inst_0; // @[lsu.scala:201:7] wire [31:0] io_core_exe_0_iresp_bits_uop_debug_inst_0; // @[lsu.scala:201:7] wire io_core_exe_0_iresp_bits_uop_is_rvc_0; // @[lsu.scala:201:7] wire [39:0] io_core_exe_0_iresp_bits_uop_debug_pc_0; // @[lsu.scala:201:7] wire [2:0] io_core_exe_0_iresp_bits_uop_iq_type_0; // @[lsu.scala:201:7] wire [9:0] io_core_exe_0_iresp_bits_uop_fu_code_0; // @[lsu.scala:201:7] wire [1:0] io_core_exe_0_iresp_bits_uop_iw_state_0; // @[lsu.scala:201:7] wire io_core_exe_0_iresp_bits_uop_iw_p1_poisoned_0; // @[lsu.scala:201:7] wire io_core_exe_0_iresp_bits_uop_iw_p2_poisoned_0; // @[lsu.scala:201:7] wire io_core_exe_0_iresp_bits_uop_is_br_0; // @[lsu.scala:201:7] wire io_core_exe_0_iresp_bits_uop_is_jalr_0; // @[lsu.scala:201:7] wire io_core_exe_0_iresp_bits_uop_is_jal_0; // @[lsu.scala:201:7] wire io_core_exe_0_iresp_bits_uop_is_sfb_0; // @[lsu.scala:201:7] wire [7:0] io_core_exe_0_iresp_bits_uop_br_mask_0; // @[lsu.scala:201:7] wire [2:0] io_core_exe_0_iresp_bits_uop_br_tag_0; // @[lsu.scala:201:7] wire [3:0] io_core_exe_0_iresp_bits_uop_ftq_idx_0; // @[lsu.scala:201:7] wire io_core_exe_0_iresp_bits_uop_edge_inst_0; // @[lsu.scala:201:7] wire [5:0] io_core_exe_0_iresp_bits_uop_pc_lob_0; // @[lsu.scala:201:7] wire io_core_exe_0_iresp_bits_uop_taken_0; // @[lsu.scala:201:7] wire [19:0] io_core_exe_0_iresp_bits_uop_imm_packed_0; // @[lsu.scala:201:7] wire [11:0] io_core_exe_0_iresp_bits_uop_csr_addr_0; // @[lsu.scala:201:7] wire [4:0] io_core_exe_0_iresp_bits_uop_rob_idx_0; // @[lsu.scala:201:7] wire [2:0] io_core_exe_0_iresp_bits_uop_ldq_idx_0; // @[lsu.scala:201:7] wire [2:0] io_core_exe_0_iresp_bits_uop_stq_idx_0; // @[lsu.scala:201:7] wire [1:0] io_core_exe_0_iresp_bits_uop_rxq_idx_0; // @[lsu.scala:201:7] wire [5:0] io_core_exe_0_iresp_bits_uop_pdst_0; // @[lsu.scala:201:7] wire [5:0] io_core_exe_0_iresp_bits_uop_prs1_0; // @[lsu.scala:201:7] wire [5:0] io_core_exe_0_iresp_bits_uop_prs2_0; // @[lsu.scala:201:7] wire [5:0] io_core_exe_0_iresp_bits_uop_prs3_0; // @[lsu.scala:201:7] wire [3:0] io_core_exe_0_iresp_bits_uop_ppred_0; // @[lsu.scala:201:7] wire io_core_exe_0_iresp_bits_uop_prs1_busy_0; // @[lsu.scala:201:7] wire io_core_exe_0_iresp_bits_uop_prs2_busy_0; // @[lsu.scala:201:7] wire io_core_exe_0_iresp_bits_uop_prs3_busy_0; // @[lsu.scala:201:7] wire io_core_exe_0_iresp_bits_uop_ppred_busy_0; // @[lsu.scala:201:7] wire [5:0] io_core_exe_0_iresp_bits_uop_stale_pdst_0; // @[lsu.scala:201:7] wire io_core_exe_0_iresp_bits_uop_exception_0; // @[lsu.scala:201:7] wire [63:0] io_core_exe_0_iresp_bits_uop_exc_cause_0; // @[lsu.scala:201:7] wire io_core_exe_0_iresp_bits_uop_bypassable_0; // @[lsu.scala:201:7] wire [4:0] io_core_exe_0_iresp_bits_uop_mem_cmd_0; // @[lsu.scala:201:7] wire [1:0] io_core_exe_0_iresp_bits_uop_mem_size_0; // @[lsu.scala:201:7] wire io_core_exe_0_iresp_bits_uop_mem_signed_0; // @[lsu.scala:201:7] wire io_core_exe_0_iresp_bits_uop_is_fence_0; // @[lsu.scala:201:7] wire io_core_exe_0_iresp_bits_uop_is_fencei_0; // @[lsu.scala:201:7] wire io_core_exe_0_iresp_bits_uop_is_amo_0; // @[lsu.scala:201:7] wire io_core_exe_0_iresp_bits_uop_uses_ldq_0; // @[lsu.scala:201:7] wire io_core_exe_0_iresp_bits_uop_uses_stq_0; // @[lsu.scala:201:7] wire io_core_exe_0_iresp_bits_uop_is_sys_pc2epc_0; // @[lsu.scala:201:7] wire io_core_exe_0_iresp_bits_uop_is_unique_0; // @[lsu.scala:201:7] wire io_core_exe_0_iresp_bits_uop_flush_on_commit_0; // @[lsu.scala:201:7] wire io_core_exe_0_iresp_bits_uop_ldst_is_rs1_0; // @[lsu.scala:201:7] wire [5:0] io_core_exe_0_iresp_bits_uop_ldst_0; // @[lsu.scala:201:7] wire [5:0] io_core_exe_0_iresp_bits_uop_lrs1_0; // @[lsu.scala:201:7] wire [5:0] io_core_exe_0_iresp_bits_uop_lrs2_0; // @[lsu.scala:201:7] wire [5:0] io_core_exe_0_iresp_bits_uop_lrs3_0; // @[lsu.scala:201:7] wire io_core_exe_0_iresp_bits_uop_ldst_val_0; // @[lsu.scala:201:7] wire [1:0] io_core_exe_0_iresp_bits_uop_dst_rtype_0; // @[lsu.scala:201:7] wire [1:0] io_core_exe_0_iresp_bits_uop_lrs1_rtype_0; // @[lsu.scala:201:7] wire [1:0] io_core_exe_0_iresp_bits_uop_lrs2_rtype_0; // @[lsu.scala:201:7] wire io_core_exe_0_iresp_bits_uop_frs3_en_0; // @[lsu.scala:201:7] wire io_core_exe_0_iresp_bits_uop_fp_val_0; // @[lsu.scala:201:7] wire io_core_exe_0_iresp_bits_uop_fp_single_0; // @[lsu.scala:201:7] wire io_core_exe_0_iresp_bits_uop_xcpt_pf_if_0; // @[lsu.scala:201:7] wire io_core_exe_0_iresp_bits_uop_xcpt_ae_if_0; // @[lsu.scala:201:7] wire io_core_exe_0_iresp_bits_uop_xcpt_ma_if_0; // @[lsu.scala:201:7] wire io_core_exe_0_iresp_bits_uop_bp_debug_if_0; // @[lsu.scala:201:7] wire io_core_exe_0_iresp_bits_uop_bp_xcpt_if_0; // @[lsu.scala:201:7] wire [1:0] io_core_exe_0_iresp_bits_uop_debug_fsrc_0; // @[lsu.scala:201:7] wire [1:0] io_core_exe_0_iresp_bits_uop_debug_tsrc_0; // @[lsu.scala:201:7] wire [63:0] io_core_exe_0_iresp_bits_data_0; // @[lsu.scala:201:7] wire io_core_exe_0_iresp_valid_0; // @[lsu.scala:201:7] wire [3:0] io_core_exe_0_fresp_bits_uop_ctrl_br_type_0; // @[lsu.scala:201:7] wire [1:0] io_core_exe_0_fresp_bits_uop_ctrl_op1_sel_0; // @[lsu.scala:201:7] wire [2:0] io_core_exe_0_fresp_bits_uop_ctrl_op2_sel_0; // @[lsu.scala:201:7] wire [2:0] io_core_exe_0_fresp_bits_uop_ctrl_imm_sel_0; // @[lsu.scala:201:7] wire [4:0] io_core_exe_0_fresp_bits_uop_ctrl_op_fcn_0; // @[lsu.scala:201:7] wire io_core_exe_0_fresp_bits_uop_ctrl_fcn_dw_0; // @[lsu.scala:201:7] wire [2:0] io_core_exe_0_fresp_bits_uop_ctrl_csr_cmd_0; // @[lsu.scala:201:7] wire io_core_exe_0_fresp_bits_uop_ctrl_is_load_0; // @[lsu.scala:201:7] wire io_core_exe_0_fresp_bits_uop_ctrl_is_sta_0; // @[lsu.scala:201:7] wire io_core_exe_0_fresp_bits_uop_ctrl_is_std_0; // @[lsu.scala:201:7] wire [6:0] io_core_exe_0_fresp_bits_uop_uopc_0; // @[lsu.scala:201:7] wire [31:0] io_core_exe_0_fresp_bits_uop_inst_0; // @[lsu.scala:201:7] wire [31:0] io_core_exe_0_fresp_bits_uop_debug_inst_0; // @[lsu.scala:201:7] wire io_core_exe_0_fresp_bits_uop_is_rvc_0; // @[lsu.scala:201:7] wire [39:0] io_core_exe_0_fresp_bits_uop_debug_pc_0; // @[lsu.scala:201:7] wire [2:0] io_core_exe_0_fresp_bits_uop_iq_type_0; // @[lsu.scala:201:7] wire [9:0] io_core_exe_0_fresp_bits_uop_fu_code_0; // @[lsu.scala:201:7] wire [1:0] io_core_exe_0_fresp_bits_uop_iw_state_0; // @[lsu.scala:201:7] wire io_core_exe_0_fresp_bits_uop_iw_p1_poisoned_0; // @[lsu.scala:201:7] wire io_core_exe_0_fresp_bits_uop_iw_p2_poisoned_0; // @[lsu.scala:201:7] wire io_core_exe_0_fresp_bits_uop_is_br_0; // @[lsu.scala:201:7] wire io_core_exe_0_fresp_bits_uop_is_jalr_0; // @[lsu.scala:201:7] wire io_core_exe_0_fresp_bits_uop_is_jal_0; // @[lsu.scala:201:7] wire io_core_exe_0_fresp_bits_uop_is_sfb_0; // @[lsu.scala:201:7] wire [7:0] io_core_exe_0_fresp_bits_uop_br_mask_0; // @[lsu.scala:201:7] wire [2:0] io_core_exe_0_fresp_bits_uop_br_tag_0; // @[lsu.scala:201:7] wire [3:0] io_core_exe_0_fresp_bits_uop_ftq_idx_0; // @[lsu.scala:201:7] wire io_core_exe_0_fresp_bits_uop_edge_inst_0; // @[lsu.scala:201:7] wire [5:0] io_core_exe_0_fresp_bits_uop_pc_lob_0; // @[lsu.scala:201:7] wire io_core_exe_0_fresp_bits_uop_taken_0; // @[lsu.scala:201:7] wire [19:0] io_core_exe_0_fresp_bits_uop_imm_packed_0; // @[lsu.scala:201:7] wire [11:0] io_core_exe_0_fresp_bits_uop_csr_addr_0; // @[lsu.scala:201:7] wire [4:0] io_core_exe_0_fresp_bits_uop_rob_idx_0; // @[lsu.scala:201:7] wire [2:0] io_core_exe_0_fresp_bits_uop_ldq_idx_0; // @[lsu.scala:201:7] wire [2:0] io_core_exe_0_fresp_bits_uop_stq_idx_0; // @[lsu.scala:201:7] wire [1:0] io_core_exe_0_fresp_bits_uop_rxq_idx_0; // @[lsu.scala:201:7] wire [5:0] io_core_exe_0_fresp_bits_uop_pdst_0; // @[lsu.scala:201:7] wire [5:0] io_core_exe_0_fresp_bits_uop_prs1_0; // @[lsu.scala:201:7] wire [5:0] io_core_exe_0_fresp_bits_uop_prs2_0; // @[lsu.scala:201:7] wire [5:0] io_core_exe_0_fresp_bits_uop_prs3_0; // @[lsu.scala:201:7] wire io_core_exe_0_fresp_bits_uop_prs1_busy_0; // @[lsu.scala:201:7] wire io_core_exe_0_fresp_bits_uop_prs2_busy_0; // @[lsu.scala:201:7] wire io_core_exe_0_fresp_bits_uop_prs3_busy_0; // @[lsu.scala:201:7] wire [5:0] io_core_exe_0_fresp_bits_uop_stale_pdst_0; // @[lsu.scala:201:7] wire io_core_exe_0_fresp_bits_uop_exception_0; // @[lsu.scala:201:7] wire [63:0] io_core_exe_0_fresp_bits_uop_exc_cause_0; // @[lsu.scala:201:7] wire io_core_exe_0_fresp_bits_uop_bypassable_0; // @[lsu.scala:201:7] wire [4:0] io_core_exe_0_fresp_bits_uop_mem_cmd_0; // @[lsu.scala:201:7] wire [1:0] io_core_exe_0_fresp_bits_uop_mem_size_0; // @[lsu.scala:201:7] wire io_core_exe_0_fresp_bits_uop_mem_signed_0; // @[lsu.scala:201:7] wire io_core_exe_0_fresp_bits_uop_is_fence_0; // @[lsu.scala:201:7] wire io_core_exe_0_fresp_bits_uop_is_fencei_0; // @[lsu.scala:201:7] wire io_core_exe_0_fresp_bits_uop_is_amo_0; // @[lsu.scala:201:7] wire io_core_exe_0_fresp_bits_uop_uses_ldq_0; // @[lsu.scala:201:7] wire io_core_exe_0_fresp_bits_uop_uses_stq_0; // @[lsu.scala:201:7] wire io_core_exe_0_fresp_bits_uop_is_sys_pc2epc_0; // @[lsu.scala:201:7] wire io_core_exe_0_fresp_bits_uop_is_unique_0; // @[lsu.scala:201:7] wire io_core_exe_0_fresp_bits_uop_flush_on_commit_0; // @[lsu.scala:201:7] wire io_core_exe_0_fresp_bits_uop_ldst_is_rs1_0; // @[lsu.scala:201:7] wire [5:0] io_core_exe_0_fresp_bits_uop_ldst_0; // @[lsu.scala:201:7] wire [5:0] io_core_exe_0_fresp_bits_uop_lrs1_0; // @[lsu.scala:201:7] wire [5:0] io_core_exe_0_fresp_bits_uop_lrs2_0; // @[lsu.scala:201:7] wire [5:0] io_core_exe_0_fresp_bits_uop_lrs3_0; // @[lsu.scala:201:7] wire io_core_exe_0_fresp_bits_uop_ldst_val_0; // @[lsu.scala:201:7] wire [1:0] io_core_exe_0_fresp_bits_uop_dst_rtype_0; // @[lsu.scala:201:7] wire [1:0] io_core_exe_0_fresp_bits_uop_lrs1_rtype_0; // @[lsu.scala:201:7] wire [1:0] io_core_exe_0_fresp_bits_uop_lrs2_rtype_0; // @[lsu.scala:201:7] wire io_core_exe_0_fresp_bits_uop_frs3_en_0; // @[lsu.scala:201:7] wire io_core_exe_0_fresp_bits_uop_fp_val_0; // @[lsu.scala:201:7] wire io_core_exe_0_fresp_bits_uop_fp_single_0; // @[lsu.scala:201:7] wire io_core_exe_0_fresp_bits_uop_xcpt_pf_if_0; // @[lsu.scala:201:7] wire io_core_exe_0_fresp_bits_uop_xcpt_ae_if_0; // @[lsu.scala:201:7] wire io_core_exe_0_fresp_bits_uop_xcpt_ma_if_0; // @[lsu.scala:201:7] wire io_core_exe_0_fresp_bits_uop_bp_debug_if_0; // @[lsu.scala:201:7] wire io_core_exe_0_fresp_bits_uop_bp_xcpt_if_0; // @[lsu.scala:201:7] wire [1:0] io_core_exe_0_fresp_bits_uop_debug_fsrc_0; // @[lsu.scala:201:7] wire [1:0] io_core_exe_0_fresp_bits_uop_debug_tsrc_0; // @[lsu.scala:201:7] wire [64:0] io_core_exe_0_fresp_bits_data_0; // @[lsu.scala:201:7] wire io_core_exe_0_fresp_valid_0; // @[lsu.scala:201:7] wire [2:0] io_core_dis_ldq_idx_0_0; // @[lsu.scala:201:7] wire [2:0] io_core_dis_stq_idx_0_0; // @[lsu.scala:201:7] wire io_core_ldq_full_0_0; // @[lsu.scala:201:7] wire io_core_stq_full_0_0; // @[lsu.scala:201:7] wire io_core_fp_stdata_ready_0; // @[lsu.scala:201:7] wire io_core_clr_bsy_0_valid_0; // @[lsu.scala:201:7] wire [4:0] io_core_clr_bsy_0_bits_0; // @[lsu.scala:201:7] wire io_core_clr_bsy_1_valid_0; // @[lsu.scala:201:7] wire [4:0] io_core_clr_bsy_1_bits_0; // @[lsu.scala:201:7] wire [4:0] io_core_clr_unsafe_0_bits_0; // @[lsu.scala:201:7] wire io_core_spec_ld_wakeup_0_valid_0; // @[lsu.scala:201:7] wire [5:0] io_core_spec_ld_wakeup_0_bits_0; // @[lsu.scala:201:7] wire [3:0] io_core_lxcpt_bits_uop_ctrl_br_type_0; // @[lsu.scala:201:7] wire [1:0] io_core_lxcpt_bits_uop_ctrl_op1_sel_0; // @[lsu.scala:201:7] wire [2:0] io_core_lxcpt_bits_uop_ctrl_op2_sel_0; // @[lsu.scala:201:7] wire [2:0] io_core_lxcpt_bits_uop_ctrl_imm_sel_0; // @[lsu.scala:201:7] wire [4:0] io_core_lxcpt_bits_uop_ctrl_op_fcn_0; // @[lsu.scala:201:7] wire io_core_lxcpt_bits_uop_ctrl_fcn_dw_0; // @[lsu.scala:201:7] wire [2:0] io_core_lxcpt_bits_uop_ctrl_csr_cmd_0; // @[lsu.scala:201:7] wire io_core_lxcpt_bits_uop_ctrl_is_load_0; // @[lsu.scala:201:7] wire io_core_lxcpt_bits_uop_ctrl_is_sta_0; // @[lsu.scala:201:7] wire io_core_lxcpt_bits_uop_ctrl_is_std_0; // @[lsu.scala:201:7] wire [6:0] io_core_lxcpt_bits_uop_uopc_0; // @[lsu.scala:201:7] wire [31:0] io_core_lxcpt_bits_uop_inst_0; // @[lsu.scala:201:7] wire [31:0] io_core_lxcpt_bits_uop_debug_inst_0; // @[lsu.scala:201:7] wire io_core_lxcpt_bits_uop_is_rvc_0; // @[lsu.scala:201:7] wire [39:0] io_core_lxcpt_bits_uop_debug_pc_0; // @[lsu.scala:201:7] wire [2:0] io_core_lxcpt_bits_uop_iq_type_0; // @[lsu.scala:201:7] wire [9:0] io_core_lxcpt_bits_uop_fu_code_0; // @[lsu.scala:201:7] wire [1:0] io_core_lxcpt_bits_uop_iw_state_0; // @[lsu.scala:201:7] wire io_core_lxcpt_bits_uop_iw_p1_poisoned_0; // @[lsu.scala:201:7] wire io_core_lxcpt_bits_uop_iw_p2_poisoned_0; // @[lsu.scala:201:7] wire io_core_lxcpt_bits_uop_is_br_0; // @[lsu.scala:201:7] wire io_core_lxcpt_bits_uop_is_jalr_0; // @[lsu.scala:201:7] wire io_core_lxcpt_bits_uop_is_jal_0; // @[lsu.scala:201:7] wire io_core_lxcpt_bits_uop_is_sfb_0; // @[lsu.scala:201:7] wire [7:0] io_core_lxcpt_bits_uop_br_mask_0; // @[lsu.scala:201:7] wire [2:0] io_core_lxcpt_bits_uop_br_tag_0; // @[lsu.scala:201:7] wire [3:0] io_core_lxcpt_bits_uop_ftq_idx_0; // @[lsu.scala:201:7] wire io_core_lxcpt_bits_uop_edge_inst_0; // @[lsu.scala:201:7] wire [5:0] io_core_lxcpt_bits_uop_pc_lob_0; // @[lsu.scala:201:7] wire io_core_lxcpt_bits_uop_taken_0; // @[lsu.scala:201:7] wire [19:0] io_core_lxcpt_bits_uop_imm_packed_0; // @[lsu.scala:201:7] wire [11:0] io_core_lxcpt_bits_uop_csr_addr_0; // @[lsu.scala:201:7] wire [4:0] io_core_lxcpt_bits_uop_rob_idx_0; // @[lsu.scala:201:7] wire [2:0] io_core_lxcpt_bits_uop_ldq_idx_0; // @[lsu.scala:201:7] wire [2:0] io_core_lxcpt_bits_uop_stq_idx_0; // @[lsu.scala:201:7] wire [1:0] io_core_lxcpt_bits_uop_rxq_idx_0; // @[lsu.scala:201:7] wire [5:0] io_core_lxcpt_bits_uop_pdst_0; // @[lsu.scala:201:7] wire [5:0] io_core_lxcpt_bits_uop_prs1_0; // @[lsu.scala:201:7] wire [5:0] io_core_lxcpt_bits_uop_prs2_0; // @[lsu.scala:201:7] wire [5:0] io_core_lxcpt_bits_uop_prs3_0; // @[lsu.scala:201:7] wire [3:0] io_core_lxcpt_bits_uop_ppred_0; // @[lsu.scala:201:7] wire io_core_lxcpt_bits_uop_prs1_busy_0; // @[lsu.scala:201:7] wire io_core_lxcpt_bits_uop_prs2_busy_0; // @[lsu.scala:201:7] wire io_core_lxcpt_bits_uop_prs3_busy_0; // @[lsu.scala:201:7] wire io_core_lxcpt_bits_uop_ppred_busy_0; // @[lsu.scala:201:7] wire [5:0] io_core_lxcpt_bits_uop_stale_pdst_0; // @[lsu.scala:201:7] wire io_core_lxcpt_bits_uop_exception_0; // @[lsu.scala:201:7] wire [63:0] io_core_lxcpt_bits_uop_exc_cause_0; // @[lsu.scala:201:7] wire io_core_lxcpt_bits_uop_bypassable_0; // @[lsu.scala:201:7] wire [4:0] io_core_lxcpt_bits_uop_mem_cmd_0; // @[lsu.scala:201:7] wire [1:0] io_core_lxcpt_bits_uop_mem_size_0; // @[lsu.scala:201:7] wire io_core_lxcpt_bits_uop_mem_signed_0; // @[lsu.scala:201:7] wire io_core_lxcpt_bits_uop_is_fence_0; // @[lsu.scala:201:7] wire io_core_lxcpt_bits_uop_is_fencei_0; // @[lsu.scala:201:7] wire io_core_lxcpt_bits_uop_is_amo_0; // @[lsu.scala:201:7] wire io_core_lxcpt_bits_uop_uses_ldq_0; // @[lsu.scala:201:7] wire io_core_lxcpt_bits_uop_uses_stq_0; // @[lsu.scala:201:7] wire io_core_lxcpt_bits_uop_is_sys_pc2epc_0; // @[lsu.scala:201:7] wire io_core_lxcpt_bits_uop_is_unique_0; // @[lsu.scala:201:7] wire io_core_lxcpt_bits_uop_flush_on_commit_0; // @[lsu.scala:201:7] wire io_core_lxcpt_bits_uop_ldst_is_rs1_0; // @[lsu.scala:201:7] wire [5:0] io_core_lxcpt_bits_uop_ldst_0; // @[lsu.scala:201:7] wire [5:0] io_core_lxcpt_bits_uop_lrs1_0; // @[lsu.scala:201:7] wire [5:0] io_core_lxcpt_bits_uop_lrs2_0; // @[lsu.scala:201:7] wire [5:0] io_core_lxcpt_bits_uop_lrs3_0; // @[lsu.scala:201:7] wire io_core_lxcpt_bits_uop_ldst_val_0; // @[lsu.scala:201:7] wire [1:0] io_core_lxcpt_bits_uop_dst_rtype_0; // @[lsu.scala:201:7] wire [1:0] io_core_lxcpt_bits_uop_lrs1_rtype_0; // @[lsu.scala:201:7] wire [1:0] io_core_lxcpt_bits_uop_lrs2_rtype_0; // @[lsu.scala:201:7] wire io_core_lxcpt_bits_uop_frs3_en_0; // @[lsu.scala:201:7] wire io_core_lxcpt_bits_uop_fp_val_0; // @[lsu.scala:201:7] wire io_core_lxcpt_bits_uop_fp_single_0; // @[lsu.scala:201:7] wire io_core_lxcpt_bits_uop_xcpt_pf_if_0; // @[lsu.scala:201:7] wire io_core_lxcpt_bits_uop_xcpt_ae_if_0; // @[lsu.scala:201:7] wire io_core_lxcpt_bits_uop_xcpt_ma_if_0; // @[lsu.scala:201:7] wire io_core_lxcpt_bits_uop_bp_debug_if_0; // @[lsu.scala:201:7] wire io_core_lxcpt_bits_uop_bp_xcpt_if_0; // @[lsu.scala:201:7] wire [1:0] io_core_lxcpt_bits_uop_debug_fsrc_0; // @[lsu.scala:201:7] wire [1:0] io_core_lxcpt_bits_uop_debug_tsrc_0; // @[lsu.scala:201:7] wire [4:0] io_core_lxcpt_bits_cause_0; // @[lsu.scala:201:7] wire [39:0] io_core_lxcpt_bits_badvaddr_0; // @[lsu.scala:201:7] wire io_core_lxcpt_valid_0; // @[lsu.scala:201:7] wire io_core_perf_tlbMiss_0; // @[lsu.scala:201:7] wire io_core_ld_miss_0; // @[lsu.scala:201:7] wire io_core_fencei_rdy_0; // @[lsu.scala:201:7] wire [3:0] io_dmem_req_bits_0_bits_uop_ctrl_br_type_0; // @[lsu.scala:201:7] wire [1:0] io_dmem_req_bits_0_bits_uop_ctrl_op1_sel_0; // @[lsu.scala:201:7] wire [2:0] io_dmem_req_bits_0_bits_uop_ctrl_op2_sel_0; // @[lsu.scala:201:7] wire [2:0] io_dmem_req_bits_0_bits_uop_ctrl_imm_sel_0; // @[lsu.scala:201:7] wire [4:0] io_dmem_req_bits_0_bits_uop_ctrl_op_fcn_0; // @[lsu.scala:201:7] wire io_dmem_req_bits_0_bits_uop_ctrl_fcn_dw_0; // @[lsu.scala:201:7] wire [2:0] io_dmem_req_bits_0_bits_uop_ctrl_csr_cmd_0; // @[lsu.scala:201:7] wire io_dmem_req_bits_0_bits_uop_ctrl_is_load_0; // @[lsu.scala:201:7] wire io_dmem_req_bits_0_bits_uop_ctrl_is_sta_0; // @[lsu.scala:201:7] wire io_dmem_req_bits_0_bits_uop_ctrl_is_std_0; // @[lsu.scala:201:7] wire [6:0] io_dmem_req_bits_0_bits_uop_uopc_0; // @[lsu.scala:201:7] wire [31:0] io_dmem_req_bits_0_bits_uop_inst_0; // @[lsu.scala:201:7] wire [31:0] io_dmem_req_bits_0_bits_uop_debug_inst_0; // @[lsu.scala:201:7] wire io_dmem_req_bits_0_bits_uop_is_rvc_0; // @[lsu.scala:201:7] wire [39:0] io_dmem_req_bits_0_bits_uop_debug_pc_0; // @[lsu.scala:201:7] wire [2:0] io_dmem_req_bits_0_bits_uop_iq_type_0; // @[lsu.scala:201:7] wire [9:0] io_dmem_req_bits_0_bits_uop_fu_code_0; // @[lsu.scala:201:7] wire [1:0] io_dmem_req_bits_0_bits_uop_iw_state_0; // @[lsu.scala:201:7] wire io_dmem_req_bits_0_bits_uop_iw_p1_poisoned_0; // @[lsu.scala:201:7] wire io_dmem_req_bits_0_bits_uop_iw_p2_poisoned_0; // @[lsu.scala:201:7] wire io_dmem_req_bits_0_bits_uop_is_br_0; // @[lsu.scala:201:7] wire io_dmem_req_bits_0_bits_uop_is_jalr_0; // @[lsu.scala:201:7] wire io_dmem_req_bits_0_bits_uop_is_jal_0; // @[lsu.scala:201:7] wire io_dmem_req_bits_0_bits_uop_is_sfb_0; // @[lsu.scala:201:7] wire [7:0] io_dmem_req_bits_0_bits_uop_br_mask_0; // @[lsu.scala:201:7] wire [2:0] io_dmem_req_bits_0_bits_uop_br_tag_0; // @[lsu.scala:201:7] wire [3:0] io_dmem_req_bits_0_bits_uop_ftq_idx_0; // @[lsu.scala:201:7] wire io_dmem_req_bits_0_bits_uop_edge_inst_0; // @[lsu.scala:201:7] wire [5:0] io_dmem_req_bits_0_bits_uop_pc_lob_0; // @[lsu.scala:201:7] wire io_dmem_req_bits_0_bits_uop_taken_0; // @[lsu.scala:201:7] wire [19:0] io_dmem_req_bits_0_bits_uop_imm_packed_0; // @[lsu.scala:201:7] wire [11:0] io_dmem_req_bits_0_bits_uop_csr_addr_0; // @[lsu.scala:201:7] wire [4:0] io_dmem_req_bits_0_bits_uop_rob_idx_0; // @[lsu.scala:201:7] wire [2:0] io_dmem_req_bits_0_bits_uop_ldq_idx_0; // @[lsu.scala:201:7] wire [2:0] io_dmem_req_bits_0_bits_uop_stq_idx_0; // @[lsu.scala:201:7] wire [1:0] io_dmem_req_bits_0_bits_uop_rxq_idx_0; // @[lsu.scala:201:7] wire [5:0] io_dmem_req_bits_0_bits_uop_pdst_0; // @[lsu.scala:201:7] wire [5:0] io_dmem_req_bits_0_bits_uop_prs1_0; // @[lsu.scala:201:7] wire [5:0] io_dmem_req_bits_0_bits_uop_prs2_0; // @[lsu.scala:201:7] wire [5:0] io_dmem_req_bits_0_bits_uop_prs3_0; // @[lsu.scala:201:7] wire [3:0] io_dmem_req_bits_0_bits_uop_ppred_0; // @[lsu.scala:201:7] wire io_dmem_req_bits_0_bits_uop_prs1_busy_0; // @[lsu.scala:201:7] wire io_dmem_req_bits_0_bits_uop_prs2_busy_0; // @[lsu.scala:201:7] wire io_dmem_req_bits_0_bits_uop_prs3_busy_0; // @[lsu.scala:201:7] wire io_dmem_req_bits_0_bits_uop_ppred_busy_0; // @[lsu.scala:201:7] wire [5:0] io_dmem_req_bits_0_bits_uop_stale_pdst_0; // @[lsu.scala:201:7] wire io_dmem_req_bits_0_bits_uop_exception_0; // @[lsu.scala:201:7] wire [63:0] io_dmem_req_bits_0_bits_uop_exc_cause_0; // @[lsu.scala:201:7] wire io_dmem_req_bits_0_bits_uop_bypassable_0; // @[lsu.scala:201:7] wire [4:0] io_dmem_req_bits_0_bits_uop_mem_cmd_0; // @[lsu.scala:201:7] wire [1:0] io_dmem_req_bits_0_bits_uop_mem_size_0; // @[lsu.scala:201:7] wire io_dmem_req_bits_0_bits_uop_mem_signed_0; // @[lsu.scala:201:7] wire io_dmem_req_bits_0_bits_uop_is_fence_0; // @[lsu.scala:201:7] wire io_dmem_req_bits_0_bits_uop_is_fencei_0; // @[lsu.scala:201:7] wire io_dmem_req_bits_0_bits_uop_is_amo_0; // @[lsu.scala:201:7] wire io_dmem_req_bits_0_bits_uop_uses_ldq_0; // @[lsu.scala:201:7] wire io_dmem_req_bits_0_bits_uop_uses_stq_0; // @[lsu.scala:201:7] wire io_dmem_req_bits_0_bits_uop_is_sys_pc2epc_0; // @[lsu.scala:201:7] wire io_dmem_req_bits_0_bits_uop_is_unique_0; // @[lsu.scala:201:7] wire io_dmem_req_bits_0_bits_uop_flush_on_commit_0; // @[lsu.scala:201:7] wire io_dmem_req_bits_0_bits_uop_ldst_is_rs1_0; // @[lsu.scala:201:7] wire [5:0] io_dmem_req_bits_0_bits_uop_ldst_0; // @[lsu.scala:201:7] wire [5:0] io_dmem_req_bits_0_bits_uop_lrs1_0; // @[lsu.scala:201:7] wire [5:0] io_dmem_req_bits_0_bits_uop_lrs2_0; // @[lsu.scala:201:7] wire [5:0] io_dmem_req_bits_0_bits_uop_lrs3_0; // @[lsu.scala:201:7] wire io_dmem_req_bits_0_bits_uop_ldst_val_0; // @[lsu.scala:201:7] wire [1:0] io_dmem_req_bits_0_bits_uop_dst_rtype_0; // @[lsu.scala:201:7] wire [1:0] io_dmem_req_bits_0_bits_uop_lrs1_rtype_0; // @[lsu.scala:201:7] wire [1:0] io_dmem_req_bits_0_bits_uop_lrs2_rtype_0; // @[lsu.scala:201:7] wire io_dmem_req_bits_0_bits_uop_frs3_en_0; // @[lsu.scala:201:7] wire io_dmem_req_bits_0_bits_uop_fp_val_0; // @[lsu.scala:201:7] wire io_dmem_req_bits_0_bits_uop_fp_single_0; // @[lsu.scala:201:7] wire io_dmem_req_bits_0_bits_uop_xcpt_pf_if_0; // @[lsu.scala:201:7] wire io_dmem_req_bits_0_bits_uop_xcpt_ae_if_0; // @[lsu.scala:201:7] wire io_dmem_req_bits_0_bits_uop_xcpt_ma_if_0; // @[lsu.scala:201:7] wire io_dmem_req_bits_0_bits_uop_bp_debug_if_0; // @[lsu.scala:201:7] wire io_dmem_req_bits_0_bits_uop_bp_xcpt_if_0; // @[lsu.scala:201:7] wire [1:0] io_dmem_req_bits_0_bits_uop_debug_fsrc_0; // @[lsu.scala:201:7] wire [1:0] io_dmem_req_bits_0_bits_uop_debug_tsrc_0; // @[lsu.scala:201:7] wire [39:0] io_dmem_req_bits_0_bits_addr_0; // @[lsu.scala:201:7] wire [63:0] io_dmem_req_bits_0_bits_data_0; // @[lsu.scala:201:7] wire io_dmem_req_bits_0_bits_is_hella_0; // @[lsu.scala:201:7] wire io_dmem_req_bits_0_valid_0; // @[lsu.scala:201:7] wire io_dmem_req_valid_0; // @[lsu.scala:201:7] wire io_dmem_s1_kill_0_0; // @[lsu.scala:201:7] wire io_dmem_release_ready_0; // @[lsu.scala:201:7] wire io_dmem_force_order_0; // @[lsu.scala:201:7] wire io_hellacache_req_ready_0; // @[lsu.scala:201:7] wire [39:0] io_hellacache_resp_bits_addr_0; // @[lsu.scala:201:7] wire io_hellacache_resp_valid_0; // @[lsu.scala:201:7] wire io_hellacache_s2_xcpt_ma_ld_0; // @[lsu.scala:201:7] wire io_hellacache_s2_xcpt_ma_st_0; // @[lsu.scala:201:7] wire io_hellacache_s2_xcpt_pf_ld_0; // @[lsu.scala:201:7] wire io_hellacache_s2_xcpt_pf_st_0; // @[lsu.scala:201:7] wire io_hellacache_s2_xcpt_gf_ld_0; // @[lsu.scala:201:7] wire io_hellacache_s2_xcpt_gf_st_0; // @[lsu.scala:201:7] wire io_hellacache_s2_xcpt_ae_ld_0; // @[lsu.scala:201:7] wire io_hellacache_s2_xcpt_ae_st_0; // @[lsu.scala:201:7] wire io_hellacache_s2_nack_0; // @[lsu.scala:201:7] wire io_hellacache_store_pending_0; // @[lsu.scala:201:7] reg ldq_0_valid; // @[lsu.scala:208:16] reg [6:0] ldq_0_bits_uop_uopc; // @[lsu.scala:208:16] reg [31:0] ldq_0_bits_uop_inst; // @[lsu.scala:208:16] reg [31:0] ldq_0_bits_uop_debug_inst; // @[lsu.scala:208:16] reg ldq_0_bits_uop_is_rvc; // @[lsu.scala:208:16] reg [39:0] ldq_0_bits_uop_debug_pc; // @[lsu.scala:208:16] reg [2:0] ldq_0_bits_uop_iq_type; // @[lsu.scala:208:16] reg [9:0] ldq_0_bits_uop_fu_code; // @[lsu.scala:208:16] reg [3:0] ldq_0_bits_uop_ctrl_br_type; // @[lsu.scala:208:16] reg [1:0] ldq_0_bits_uop_ctrl_op1_sel; // @[lsu.scala:208:16] reg [2:0] ldq_0_bits_uop_ctrl_op2_sel; // @[lsu.scala:208:16] reg [2:0] ldq_0_bits_uop_ctrl_imm_sel; // @[lsu.scala:208:16] reg [4:0] ldq_0_bits_uop_ctrl_op_fcn; // @[lsu.scala:208:16] reg ldq_0_bits_uop_ctrl_fcn_dw; // @[lsu.scala:208:16] reg [2:0] ldq_0_bits_uop_ctrl_csr_cmd; // @[lsu.scala:208:16] reg ldq_0_bits_uop_ctrl_is_load; // @[lsu.scala:208:16] reg ldq_0_bits_uop_ctrl_is_sta; // @[lsu.scala:208:16] reg ldq_0_bits_uop_ctrl_is_std; // @[lsu.scala:208:16] reg [1:0] ldq_0_bits_uop_iw_state; // @[lsu.scala:208:16] reg ldq_0_bits_uop_iw_p1_poisoned; // @[lsu.scala:208:16] reg ldq_0_bits_uop_iw_p2_poisoned; // @[lsu.scala:208:16] reg ldq_0_bits_uop_is_br; // @[lsu.scala:208:16] reg ldq_0_bits_uop_is_jalr; // @[lsu.scala:208:16] reg ldq_0_bits_uop_is_jal; // @[lsu.scala:208:16] reg ldq_0_bits_uop_is_sfb; // @[lsu.scala:208:16] reg [7:0] ldq_0_bits_uop_br_mask; // @[lsu.scala:208:16] reg [2:0] ldq_0_bits_uop_br_tag; // @[lsu.scala:208:16] reg [3:0] ldq_0_bits_uop_ftq_idx; // @[lsu.scala:208:16] reg ldq_0_bits_uop_edge_inst; // @[lsu.scala:208:16] reg [5:0] ldq_0_bits_uop_pc_lob; // @[lsu.scala:208:16] reg ldq_0_bits_uop_taken; // @[lsu.scala:208:16] reg [19:0] ldq_0_bits_uop_imm_packed; // @[lsu.scala:208:16] reg [11:0] ldq_0_bits_uop_csr_addr; // @[lsu.scala:208:16] reg [4:0] ldq_0_bits_uop_rob_idx; // @[lsu.scala:208:16] reg [2:0] ldq_0_bits_uop_ldq_idx; // @[lsu.scala:208:16] reg [2:0] ldq_0_bits_uop_stq_idx; // @[lsu.scala:208:16] reg [1:0] ldq_0_bits_uop_rxq_idx; // @[lsu.scala:208:16] reg [5:0] ldq_0_bits_uop_pdst; // @[lsu.scala:208:16] reg [5:0] ldq_0_bits_uop_prs1; // @[lsu.scala:208:16] reg [5:0] ldq_0_bits_uop_prs2; // @[lsu.scala:208:16] reg [5:0] ldq_0_bits_uop_prs3; // @[lsu.scala:208:16] reg ldq_0_bits_uop_prs1_busy; // @[lsu.scala:208:16] reg ldq_0_bits_uop_prs2_busy; // @[lsu.scala:208:16] reg ldq_0_bits_uop_prs3_busy; // @[lsu.scala:208:16] reg [5:0] ldq_0_bits_uop_stale_pdst; // @[lsu.scala:208:16] reg ldq_0_bits_uop_exception; // @[lsu.scala:208:16] reg [63:0] ldq_0_bits_uop_exc_cause; // @[lsu.scala:208:16] reg ldq_0_bits_uop_bypassable; // @[lsu.scala:208:16] reg [4:0] ldq_0_bits_uop_mem_cmd; // @[lsu.scala:208:16] reg [1:0] ldq_0_bits_uop_mem_size; // @[lsu.scala:208:16] reg ldq_0_bits_uop_mem_signed; // @[lsu.scala:208:16] reg ldq_0_bits_uop_is_fence; // @[lsu.scala:208:16] reg ldq_0_bits_uop_is_fencei; // @[lsu.scala:208:16] reg ldq_0_bits_uop_is_amo; // @[lsu.scala:208:16] reg ldq_0_bits_uop_uses_ldq; // @[lsu.scala:208:16] reg ldq_0_bits_uop_uses_stq; // @[lsu.scala:208:16] reg ldq_0_bits_uop_is_sys_pc2epc; // @[lsu.scala:208:16] reg ldq_0_bits_uop_is_unique; // @[lsu.scala:208:16] reg ldq_0_bits_uop_flush_on_commit; // @[lsu.scala:208:16] reg ldq_0_bits_uop_ldst_is_rs1; // @[lsu.scala:208:16] reg [5:0] ldq_0_bits_uop_ldst; // @[lsu.scala:208:16] reg [5:0] ldq_0_bits_uop_lrs1; // @[lsu.scala:208:16] reg [5:0] ldq_0_bits_uop_lrs2; // @[lsu.scala:208:16] reg [5:0] ldq_0_bits_uop_lrs3; // @[lsu.scala:208:16] reg ldq_0_bits_uop_ldst_val; // @[lsu.scala:208:16] reg [1:0] ldq_0_bits_uop_dst_rtype; // @[lsu.scala:208:16] reg [1:0] ldq_0_bits_uop_lrs1_rtype; // @[lsu.scala:208:16] reg [1:0] ldq_0_bits_uop_lrs2_rtype; // @[lsu.scala:208:16] reg ldq_0_bits_uop_frs3_en; // @[lsu.scala:208:16] reg ldq_0_bits_uop_fp_val; // @[lsu.scala:208:16] reg ldq_0_bits_uop_fp_single; // @[lsu.scala:208:16] reg ldq_0_bits_uop_xcpt_pf_if; // @[lsu.scala:208:16] reg ldq_0_bits_uop_xcpt_ae_if; // @[lsu.scala:208:16] reg ldq_0_bits_uop_xcpt_ma_if; // @[lsu.scala:208:16] reg ldq_0_bits_uop_bp_debug_if; // @[lsu.scala:208:16] reg ldq_0_bits_uop_bp_xcpt_if; // @[lsu.scala:208:16] reg [1:0] ldq_0_bits_uop_debug_fsrc; // @[lsu.scala:208:16] reg [1:0] ldq_0_bits_uop_debug_tsrc; // @[lsu.scala:208:16] reg ldq_0_bits_addr_valid; // @[lsu.scala:208:16] reg [39:0] ldq_0_bits_addr_bits; // @[lsu.scala:208:16] reg ldq_0_bits_addr_is_virtual; // @[lsu.scala:208:16] reg ldq_0_bits_addr_is_uncacheable; // @[lsu.scala:208:16] reg ldq_0_bits_executed; // @[lsu.scala:208:16] reg ldq_0_bits_succeeded; // @[lsu.scala:208:16] reg ldq_0_bits_order_fail; // @[lsu.scala:208:16] reg ldq_0_bits_observed; // @[lsu.scala:208:16] reg [7:0] ldq_0_bits_st_dep_mask; // @[lsu.scala:208:16] reg [2:0] ldq_0_bits_youngest_stq_idx; // @[lsu.scala:208:16] reg ldq_0_bits_forward_std_val; // @[lsu.scala:208:16] reg [2:0] ldq_0_bits_forward_stq_idx; // @[lsu.scala:208:16] reg [63:0] ldq_0_bits_debug_wb_data; // @[lsu.scala:208:16] reg ldq_1_valid; // @[lsu.scala:208:16] reg [6:0] ldq_1_bits_uop_uopc; // @[lsu.scala:208:16] reg [31:0] ldq_1_bits_uop_inst; // @[lsu.scala:208:16] reg [31:0] ldq_1_bits_uop_debug_inst; // @[lsu.scala:208:16] reg ldq_1_bits_uop_is_rvc; // @[lsu.scala:208:16] reg [39:0] ldq_1_bits_uop_debug_pc; // @[lsu.scala:208:16] reg [2:0] ldq_1_bits_uop_iq_type; // @[lsu.scala:208:16] reg [9:0] ldq_1_bits_uop_fu_code; // @[lsu.scala:208:16] reg [3:0] ldq_1_bits_uop_ctrl_br_type; // @[lsu.scala:208:16] reg [1:0] ldq_1_bits_uop_ctrl_op1_sel; // @[lsu.scala:208:16] reg [2:0] ldq_1_bits_uop_ctrl_op2_sel; // @[lsu.scala:208:16] reg [2:0] ldq_1_bits_uop_ctrl_imm_sel; // @[lsu.scala:208:16] reg [4:0] ldq_1_bits_uop_ctrl_op_fcn; // @[lsu.scala:208:16] reg ldq_1_bits_uop_ctrl_fcn_dw; // @[lsu.scala:208:16] reg [2:0] ldq_1_bits_uop_ctrl_csr_cmd; // @[lsu.scala:208:16] reg ldq_1_bits_uop_ctrl_is_load; // @[lsu.scala:208:16] reg ldq_1_bits_uop_ctrl_is_sta; // @[lsu.scala:208:16] reg ldq_1_bits_uop_ctrl_is_std; // @[lsu.scala:208:16] reg [1:0] ldq_1_bits_uop_iw_state; // @[lsu.scala:208:16] reg ldq_1_bits_uop_iw_p1_poisoned; // @[lsu.scala:208:16] reg ldq_1_bits_uop_iw_p2_poisoned; // @[lsu.scala:208:16] reg ldq_1_bits_uop_is_br; // @[lsu.scala:208:16] reg ldq_1_bits_uop_is_jalr; // @[lsu.scala:208:16] reg ldq_1_bits_uop_is_jal; // @[lsu.scala:208:16] reg ldq_1_bits_uop_is_sfb; // @[lsu.scala:208:16] reg [7:0] ldq_1_bits_uop_br_mask; // @[lsu.scala:208:16] reg [2:0] ldq_1_bits_uop_br_tag; // @[lsu.scala:208:16] reg [3:0] ldq_1_bits_uop_ftq_idx; // @[lsu.scala:208:16] reg ldq_1_bits_uop_edge_inst; // @[lsu.scala:208:16] reg [5:0] ldq_1_bits_uop_pc_lob; // @[lsu.scala:208:16] reg ldq_1_bits_uop_taken; // @[lsu.scala:208:16] reg [19:0] ldq_1_bits_uop_imm_packed; // @[lsu.scala:208:16] reg [11:0] ldq_1_bits_uop_csr_addr; // @[lsu.scala:208:16] reg [4:0] ldq_1_bits_uop_rob_idx; // @[lsu.scala:208:16] reg [2:0] ldq_1_bits_uop_ldq_idx; // @[lsu.scala:208:16] reg [2:0] ldq_1_bits_uop_stq_idx; // @[lsu.scala:208:16] reg [1:0] ldq_1_bits_uop_rxq_idx; // @[lsu.scala:208:16] reg [5:0] ldq_1_bits_uop_pdst; // @[lsu.scala:208:16] reg [5:0] ldq_1_bits_uop_prs1; // @[lsu.scala:208:16] reg [5:0] ldq_1_bits_uop_prs2; // @[lsu.scala:208:16] reg [5:0] ldq_1_bits_uop_prs3; // @[lsu.scala:208:16] reg ldq_1_bits_uop_prs1_busy; // @[lsu.scala:208:16] reg ldq_1_bits_uop_prs2_busy; // @[lsu.scala:208:16] reg ldq_1_bits_uop_prs3_busy; // @[lsu.scala:208:16] reg [5:0] ldq_1_bits_uop_stale_pdst; // @[lsu.scala:208:16] reg ldq_1_bits_uop_exception; // @[lsu.scala:208:16] reg [63:0] ldq_1_bits_uop_exc_cause; // @[lsu.scala:208:16] reg ldq_1_bits_uop_bypassable; // @[lsu.scala:208:16] reg [4:0] ldq_1_bits_uop_mem_cmd; // @[lsu.scala:208:16] reg [1:0] ldq_1_bits_uop_mem_size; // @[lsu.scala:208:16] reg ldq_1_bits_uop_mem_signed; // @[lsu.scala:208:16] reg ldq_1_bits_uop_is_fence; // @[lsu.scala:208:16] reg ldq_1_bits_uop_is_fencei; // @[lsu.scala:208:16] reg ldq_1_bits_uop_is_amo; // @[lsu.scala:208:16] reg ldq_1_bits_uop_uses_ldq; // @[lsu.scala:208:16] reg ldq_1_bits_uop_uses_stq; // @[lsu.scala:208:16] reg ldq_1_bits_uop_is_sys_pc2epc; // @[lsu.scala:208:16] reg ldq_1_bits_uop_is_unique; // @[lsu.scala:208:16] reg ldq_1_bits_uop_flush_on_commit; // @[lsu.scala:208:16] reg ldq_1_bits_uop_ldst_is_rs1; // @[lsu.scala:208:16] reg [5:0] ldq_1_bits_uop_ldst; // @[lsu.scala:208:16] reg [5:0] ldq_1_bits_uop_lrs1; // @[lsu.scala:208:16] reg [5:0] ldq_1_bits_uop_lrs2; // @[lsu.scala:208:16] reg [5:0] ldq_1_bits_uop_lrs3; // @[lsu.scala:208:16] reg ldq_1_bits_uop_ldst_val; // @[lsu.scala:208:16] reg [1:0] ldq_1_bits_uop_dst_rtype; // @[lsu.scala:208:16] reg [1:0] ldq_1_bits_uop_lrs1_rtype; // @[lsu.scala:208:16] reg [1:0] ldq_1_bits_uop_lrs2_rtype; // @[lsu.scala:208:16] reg ldq_1_bits_uop_frs3_en; // @[lsu.scala:208:16] reg ldq_1_bits_uop_fp_val; // @[lsu.scala:208:16] reg ldq_1_bits_uop_fp_single; // @[lsu.scala:208:16] reg ldq_1_bits_uop_xcpt_pf_if; // @[lsu.scala:208:16] reg ldq_1_bits_uop_xcpt_ae_if; // @[lsu.scala:208:16] reg ldq_1_bits_uop_xcpt_ma_if; // @[lsu.scala:208:16] reg ldq_1_bits_uop_bp_debug_if; // @[lsu.scala:208:16] reg ldq_1_bits_uop_bp_xcpt_if; // @[lsu.scala:208:16] reg [1:0] ldq_1_bits_uop_debug_fsrc; // @[lsu.scala:208:16] reg [1:0] ldq_1_bits_uop_debug_tsrc; // @[lsu.scala:208:16] reg ldq_1_bits_addr_valid; // @[lsu.scala:208:16] reg [39:0] ldq_1_bits_addr_bits; // @[lsu.scala:208:16] reg ldq_1_bits_addr_is_virtual; // @[lsu.scala:208:16] reg ldq_1_bits_addr_is_uncacheable; // @[lsu.scala:208:16] reg ldq_1_bits_executed; // @[lsu.scala:208:16] reg ldq_1_bits_succeeded; // @[lsu.scala:208:16] reg ldq_1_bits_order_fail; // @[lsu.scala:208:16] reg ldq_1_bits_observed; // @[lsu.scala:208:16] reg [7:0] ldq_1_bits_st_dep_mask; // @[lsu.scala:208:16] reg [2:0] ldq_1_bits_youngest_stq_idx; // @[lsu.scala:208:16] reg ldq_1_bits_forward_std_val; // @[lsu.scala:208:16] reg [2:0] ldq_1_bits_forward_stq_idx; // @[lsu.scala:208:16] reg [63:0] ldq_1_bits_debug_wb_data; // @[lsu.scala:208:16] reg ldq_2_valid; // @[lsu.scala:208:16] reg [6:0] ldq_2_bits_uop_uopc; // @[lsu.scala:208:16] reg [31:0] ldq_2_bits_uop_inst; // @[lsu.scala:208:16] reg [31:0] ldq_2_bits_uop_debug_inst; // @[lsu.scala:208:16] reg ldq_2_bits_uop_is_rvc; // @[lsu.scala:208:16] reg [39:0] ldq_2_bits_uop_debug_pc; // @[lsu.scala:208:16] reg [2:0] ldq_2_bits_uop_iq_type; // @[lsu.scala:208:16] reg [9:0] ldq_2_bits_uop_fu_code; // @[lsu.scala:208:16] reg [3:0] ldq_2_bits_uop_ctrl_br_type; // @[lsu.scala:208:16] reg [1:0] ldq_2_bits_uop_ctrl_op1_sel; // @[lsu.scala:208:16] reg [2:0] ldq_2_bits_uop_ctrl_op2_sel; // @[lsu.scala:208:16] reg [2:0] ldq_2_bits_uop_ctrl_imm_sel; // @[lsu.scala:208:16] reg [4:0] ldq_2_bits_uop_ctrl_op_fcn; // @[lsu.scala:208:16] reg ldq_2_bits_uop_ctrl_fcn_dw; // @[lsu.scala:208:16] reg [2:0] ldq_2_bits_uop_ctrl_csr_cmd; // @[lsu.scala:208:16] reg ldq_2_bits_uop_ctrl_is_load; // @[lsu.scala:208:16] reg ldq_2_bits_uop_ctrl_is_sta; // @[lsu.scala:208:16] reg ldq_2_bits_uop_ctrl_is_std; // @[lsu.scala:208:16] reg [1:0] ldq_2_bits_uop_iw_state; // @[lsu.scala:208:16] reg ldq_2_bits_uop_iw_p1_poisoned; // @[lsu.scala:208:16] reg ldq_2_bits_uop_iw_p2_poisoned; // @[lsu.scala:208:16] reg ldq_2_bits_uop_is_br; // @[lsu.scala:208:16] reg ldq_2_bits_uop_is_jalr; // @[lsu.scala:208:16] reg ldq_2_bits_uop_is_jal; // @[lsu.scala:208:16] reg ldq_2_bits_uop_is_sfb; // @[lsu.scala:208:16] reg [7:0] ldq_2_bits_uop_br_mask; // @[lsu.scala:208:16] reg [2:0] ldq_2_bits_uop_br_tag; // @[lsu.scala:208:16] reg [3:0] ldq_2_bits_uop_ftq_idx; // @[lsu.scala:208:16] reg ldq_2_bits_uop_edge_inst; // @[lsu.scala:208:16] reg [5:0] ldq_2_bits_uop_pc_lob; // @[lsu.scala:208:16] reg ldq_2_bits_uop_taken; // @[lsu.scala:208:16] reg [19:0] ldq_2_bits_uop_imm_packed; // @[lsu.scala:208:16] reg [11:0] ldq_2_bits_uop_csr_addr; // @[lsu.scala:208:16] reg [4:0] ldq_2_bits_uop_rob_idx; // @[lsu.scala:208:16] reg [2:0] ldq_2_bits_uop_ldq_idx; // @[lsu.scala:208:16] reg [2:0] ldq_2_bits_uop_stq_idx; // @[lsu.scala:208:16] reg [1:0] ldq_2_bits_uop_rxq_idx; // @[lsu.scala:208:16] reg [5:0] ldq_2_bits_uop_pdst; // @[lsu.scala:208:16] reg [5:0] ldq_2_bits_uop_prs1; // @[lsu.scala:208:16] reg [5:0] ldq_2_bits_uop_prs2; // @[lsu.scala:208:16] reg [5:0] ldq_2_bits_uop_prs3; // @[lsu.scala:208:16] reg ldq_2_bits_uop_prs1_busy; // @[lsu.scala:208:16] reg ldq_2_bits_uop_prs2_busy; // @[lsu.scala:208:16] reg ldq_2_bits_uop_prs3_busy; // @[lsu.scala:208:16] reg [5:0] ldq_2_bits_uop_stale_pdst; // @[lsu.scala:208:16] reg ldq_2_bits_uop_exception; // @[lsu.scala:208:16] reg [63:0] ldq_2_bits_uop_exc_cause; // @[lsu.scala:208:16] reg ldq_2_bits_uop_bypassable; // @[lsu.scala:208:16] reg [4:0] ldq_2_bits_uop_mem_cmd; // @[lsu.scala:208:16] reg [1:0] ldq_2_bits_uop_mem_size; // @[lsu.scala:208:16] reg ldq_2_bits_uop_mem_signed; // @[lsu.scala:208:16] reg ldq_2_bits_uop_is_fence; // @[lsu.scala:208:16] reg ldq_2_bits_uop_is_fencei; // @[lsu.scala:208:16] reg ldq_2_bits_uop_is_amo; // @[lsu.scala:208:16] reg ldq_2_bits_uop_uses_ldq; // @[lsu.scala:208:16] reg ldq_2_bits_uop_uses_stq; // @[lsu.scala:208:16] reg ldq_2_bits_uop_is_sys_pc2epc; // @[lsu.scala:208:16] reg ldq_2_bits_uop_is_unique; // @[lsu.scala:208:16] reg ldq_2_bits_uop_flush_on_commit; // @[lsu.scala:208:16] reg ldq_2_bits_uop_ldst_is_rs1; // @[lsu.scala:208:16] reg [5:0] ldq_2_bits_uop_ldst; // @[lsu.scala:208:16] reg [5:0] ldq_2_bits_uop_lrs1; // @[lsu.scala:208:16] reg [5:0] ldq_2_bits_uop_lrs2; // @[lsu.scala:208:16] reg [5:0] ldq_2_bits_uop_lrs3; // @[lsu.scala:208:16] reg ldq_2_bits_uop_ldst_val; // @[lsu.scala:208:16] reg [1:0] ldq_2_bits_uop_dst_rtype; // @[lsu.scala:208:16] reg [1:0] ldq_2_bits_uop_lrs1_rtype; // @[lsu.scala:208:16] reg [1:0] ldq_2_bits_uop_lrs2_rtype; // @[lsu.scala:208:16] reg ldq_2_bits_uop_frs3_en; // @[lsu.scala:208:16] reg ldq_2_bits_uop_fp_val; // @[lsu.scala:208:16] reg ldq_2_bits_uop_fp_single; // @[lsu.scala:208:16] reg ldq_2_bits_uop_xcpt_pf_if; // @[lsu.scala:208:16] reg ldq_2_bits_uop_xcpt_ae_if; // @[lsu.scala:208:16] reg ldq_2_bits_uop_xcpt_ma_if; // @[lsu.scala:208:16] reg ldq_2_bits_uop_bp_debug_if; // @[lsu.scala:208:16] reg ldq_2_bits_uop_bp_xcpt_if; // @[lsu.scala:208:16] reg [1:0] ldq_2_bits_uop_debug_fsrc; // @[lsu.scala:208:16] reg [1:0] ldq_2_bits_uop_debug_tsrc; // @[lsu.scala:208:16] reg ldq_2_bits_addr_valid; // @[lsu.scala:208:16] reg [39:0] ldq_2_bits_addr_bits; // @[lsu.scala:208:16] reg ldq_2_bits_addr_is_virtual; // @[lsu.scala:208:16] reg ldq_2_bits_addr_is_uncacheable; // @[lsu.scala:208:16] reg ldq_2_bits_executed; // @[lsu.scala:208:16] reg ldq_2_bits_succeeded; // @[lsu.scala:208:16] reg ldq_2_bits_order_fail; // @[lsu.scala:208:16] reg ldq_2_bits_observed; // @[lsu.scala:208:16] reg [7:0] ldq_2_bits_st_dep_mask; // @[lsu.scala:208:16] reg [2:0] ldq_2_bits_youngest_stq_idx; // @[lsu.scala:208:16] reg ldq_2_bits_forward_std_val; // @[lsu.scala:208:16] reg [2:0] ldq_2_bits_forward_stq_idx; // @[lsu.scala:208:16] reg [63:0] ldq_2_bits_debug_wb_data; // @[lsu.scala:208:16] reg ldq_3_valid; // @[lsu.scala:208:16] reg [6:0] ldq_3_bits_uop_uopc; // @[lsu.scala:208:16] reg [31:0] ldq_3_bits_uop_inst; // @[lsu.scala:208:16] reg [31:0] ldq_3_bits_uop_debug_inst; // @[lsu.scala:208:16] reg ldq_3_bits_uop_is_rvc; // @[lsu.scala:208:16] reg [39:0] ldq_3_bits_uop_debug_pc; // @[lsu.scala:208:16] reg [2:0] ldq_3_bits_uop_iq_type; // @[lsu.scala:208:16] reg [9:0] ldq_3_bits_uop_fu_code; // @[lsu.scala:208:16] reg [3:0] ldq_3_bits_uop_ctrl_br_type; // @[lsu.scala:208:16] reg [1:0] ldq_3_bits_uop_ctrl_op1_sel; // @[lsu.scala:208:16] reg [2:0] ldq_3_bits_uop_ctrl_op2_sel; // @[lsu.scala:208:16] reg [2:0] ldq_3_bits_uop_ctrl_imm_sel; // @[lsu.scala:208:16] reg [4:0] ldq_3_bits_uop_ctrl_op_fcn; // @[lsu.scala:208:16] reg ldq_3_bits_uop_ctrl_fcn_dw; // @[lsu.scala:208:16] reg [2:0] ldq_3_bits_uop_ctrl_csr_cmd; // @[lsu.scala:208:16] reg ldq_3_bits_uop_ctrl_is_load; // @[lsu.scala:208:16] reg ldq_3_bits_uop_ctrl_is_sta; // @[lsu.scala:208:16] reg ldq_3_bits_uop_ctrl_is_std; // @[lsu.scala:208:16] reg [1:0] ldq_3_bits_uop_iw_state; // @[lsu.scala:208:16] reg ldq_3_bits_uop_iw_p1_poisoned; // @[lsu.scala:208:16] reg ldq_3_bits_uop_iw_p2_poisoned; // @[lsu.scala:208:16] reg ldq_3_bits_uop_is_br; // @[lsu.scala:208:16] reg ldq_3_bits_uop_is_jalr; // @[lsu.scala:208:16] reg ldq_3_bits_uop_is_jal; // @[lsu.scala:208:16] reg ldq_3_bits_uop_is_sfb; // @[lsu.scala:208:16] reg [7:0] ldq_3_bits_uop_br_mask; // @[lsu.scala:208:16] reg [2:0] ldq_3_bits_uop_br_tag; // @[lsu.scala:208:16] reg [3:0] ldq_3_bits_uop_ftq_idx; // @[lsu.scala:208:16] reg ldq_3_bits_uop_edge_inst; // @[lsu.scala:208:16] reg [5:0] ldq_3_bits_uop_pc_lob; // @[lsu.scala:208:16] reg ldq_3_bits_uop_taken; // @[lsu.scala:208:16] reg [19:0] ldq_3_bits_uop_imm_packed; // @[lsu.scala:208:16] reg [11:0] ldq_3_bits_uop_csr_addr; // @[lsu.scala:208:16] reg [4:0] ldq_3_bits_uop_rob_idx; // @[lsu.scala:208:16] reg [2:0] ldq_3_bits_uop_ldq_idx; // @[lsu.scala:208:16] reg [2:0] ldq_3_bits_uop_stq_idx; // @[lsu.scala:208:16] reg [1:0] ldq_3_bits_uop_rxq_idx; // @[lsu.scala:208:16] reg [5:0] ldq_3_bits_uop_pdst; // @[lsu.scala:208:16] reg [5:0] ldq_3_bits_uop_prs1; // @[lsu.scala:208:16] reg [5:0] ldq_3_bits_uop_prs2; // @[lsu.scala:208:16] reg [5:0] ldq_3_bits_uop_prs3; // @[lsu.scala:208:16] reg ldq_3_bits_uop_prs1_busy; // @[lsu.scala:208:16] reg ldq_3_bits_uop_prs2_busy; // @[lsu.scala:208:16] reg ldq_3_bits_uop_prs3_busy; // @[lsu.scala:208:16] reg [5:0] ldq_3_bits_uop_stale_pdst; // @[lsu.scala:208:16] reg ldq_3_bits_uop_exception; // @[lsu.scala:208:16] reg [63:0] ldq_3_bits_uop_exc_cause; // @[lsu.scala:208:16] reg ldq_3_bits_uop_bypassable; // @[lsu.scala:208:16] reg [4:0] ldq_3_bits_uop_mem_cmd; // @[lsu.scala:208:16] reg [1:0] ldq_3_bits_uop_mem_size; // @[lsu.scala:208:16] reg ldq_3_bits_uop_mem_signed; // @[lsu.scala:208:16] reg ldq_3_bits_uop_is_fence; // @[lsu.scala:208:16] reg ldq_3_bits_uop_is_fencei; // @[lsu.scala:208:16] reg ldq_3_bits_uop_is_amo; // @[lsu.scala:208:16] reg ldq_3_bits_uop_uses_ldq; // @[lsu.scala:208:16] reg ldq_3_bits_uop_uses_stq; // @[lsu.scala:208:16] reg ldq_3_bits_uop_is_sys_pc2epc; // @[lsu.scala:208:16] reg ldq_3_bits_uop_is_unique; // @[lsu.scala:208:16] reg ldq_3_bits_uop_flush_on_commit; // @[lsu.scala:208:16] reg ldq_3_bits_uop_ldst_is_rs1; // @[lsu.scala:208:16] reg [5:0] ldq_3_bits_uop_ldst; // @[lsu.scala:208:16] reg [5:0] ldq_3_bits_uop_lrs1; // @[lsu.scala:208:16] reg [5:0] ldq_3_bits_uop_lrs2; // @[lsu.scala:208:16] reg [5:0] ldq_3_bits_uop_lrs3; // @[lsu.scala:208:16] reg ldq_3_bits_uop_ldst_val; // @[lsu.scala:208:16] reg [1:0] ldq_3_bits_uop_dst_rtype; // @[lsu.scala:208:16] reg [1:0] ldq_3_bits_uop_lrs1_rtype; // @[lsu.scala:208:16] reg [1:0] ldq_3_bits_uop_lrs2_rtype; // @[lsu.scala:208:16] reg ldq_3_bits_uop_frs3_en; // @[lsu.scala:208:16] reg ldq_3_bits_uop_fp_val; // @[lsu.scala:208:16] reg ldq_3_bits_uop_fp_single; // @[lsu.scala:208:16] reg ldq_3_bits_uop_xcpt_pf_if; // @[lsu.scala:208:16] reg ldq_3_bits_uop_xcpt_ae_if; // @[lsu.scala:208:16] reg ldq_3_bits_uop_xcpt_ma_if; // @[lsu.scala:208:16] reg ldq_3_bits_uop_bp_debug_if; // @[lsu.scala:208:16] reg ldq_3_bits_uop_bp_xcpt_if; // @[lsu.scala:208:16] reg [1:0] ldq_3_bits_uop_debug_fsrc; // @[lsu.scala:208:16] reg [1:0] ldq_3_bits_uop_debug_tsrc; // @[lsu.scala:208:16] reg ldq_3_bits_addr_valid; // @[lsu.scala:208:16] reg [39:0] ldq_3_bits_addr_bits; // @[lsu.scala:208:16] reg ldq_3_bits_addr_is_virtual; // @[lsu.scala:208:16] reg ldq_3_bits_addr_is_uncacheable; // @[lsu.scala:208:16] reg ldq_3_bits_executed; // @[lsu.scala:208:16] reg ldq_3_bits_succeeded; // @[lsu.scala:208:16] reg ldq_3_bits_order_fail; // @[lsu.scala:208:16] reg ldq_3_bits_observed; // @[lsu.scala:208:16] reg [7:0] ldq_3_bits_st_dep_mask; // @[lsu.scala:208:16] reg [2:0] ldq_3_bits_youngest_stq_idx; // @[lsu.scala:208:16] reg ldq_3_bits_forward_std_val; // @[lsu.scala:208:16] reg [2:0] ldq_3_bits_forward_stq_idx; // @[lsu.scala:208:16] reg [63:0] ldq_3_bits_debug_wb_data; // @[lsu.scala:208:16] reg ldq_4_valid; // @[lsu.scala:208:16] reg [6:0] ldq_4_bits_uop_uopc; // @[lsu.scala:208:16] reg [31:0] ldq_4_bits_uop_inst; // @[lsu.scala:208:16] reg [31:0] ldq_4_bits_uop_debug_inst; // @[lsu.scala:208:16] reg ldq_4_bits_uop_is_rvc; // @[lsu.scala:208:16] reg [39:0] ldq_4_bits_uop_debug_pc; // @[lsu.scala:208:16] reg [2:0] ldq_4_bits_uop_iq_type; // @[lsu.scala:208:16] reg [9:0] ldq_4_bits_uop_fu_code; // @[lsu.scala:208:16] reg [3:0] ldq_4_bits_uop_ctrl_br_type; // @[lsu.scala:208:16] reg [1:0] ldq_4_bits_uop_ctrl_op1_sel; // @[lsu.scala:208:16] reg [2:0] ldq_4_bits_uop_ctrl_op2_sel; // @[lsu.scala:208:16] reg [2:0] ldq_4_bits_uop_ctrl_imm_sel; // @[lsu.scala:208:16] reg [4:0] ldq_4_bits_uop_ctrl_op_fcn; // @[lsu.scala:208:16] reg ldq_4_bits_uop_ctrl_fcn_dw; // @[lsu.scala:208:16] reg [2:0] ldq_4_bits_uop_ctrl_csr_cmd; // @[lsu.scala:208:16] reg ldq_4_bits_uop_ctrl_is_load; // @[lsu.scala:208:16] reg ldq_4_bits_uop_ctrl_is_sta; // @[lsu.scala:208:16] reg ldq_4_bits_uop_ctrl_is_std; // @[lsu.scala:208:16] reg [1:0] ldq_4_bits_uop_iw_state; // @[lsu.scala:208:16] reg ldq_4_bits_uop_iw_p1_poisoned; // @[lsu.scala:208:16] reg ldq_4_bits_uop_iw_p2_poisoned; // @[lsu.scala:208:16] reg ldq_4_bits_uop_is_br; // @[lsu.scala:208:16] reg ldq_4_bits_uop_is_jalr; // @[lsu.scala:208:16] reg ldq_4_bits_uop_is_jal; // @[lsu.scala:208:16] reg ldq_4_bits_uop_is_sfb; // @[lsu.scala:208:16] reg [7:0] ldq_4_bits_uop_br_mask; // @[lsu.scala:208:16] reg [2:0] ldq_4_bits_uop_br_tag; // @[lsu.scala:208:16] reg [3:0] ldq_4_bits_uop_ftq_idx; // @[lsu.scala:208:16] reg ldq_4_bits_uop_edge_inst; // @[lsu.scala:208:16] reg [5:0] ldq_4_bits_uop_pc_lob; // @[lsu.scala:208:16] reg ldq_4_bits_uop_taken; // @[lsu.scala:208:16] reg [19:0] ldq_4_bits_uop_imm_packed; // @[lsu.scala:208:16] reg [11:0] ldq_4_bits_uop_csr_addr; // @[lsu.scala:208:16] reg [4:0] ldq_4_bits_uop_rob_idx; // @[lsu.scala:208:16] reg [2:0] ldq_4_bits_uop_ldq_idx; // @[lsu.scala:208:16] reg [2:0] ldq_4_bits_uop_stq_idx; // @[lsu.scala:208:16] reg [1:0] ldq_4_bits_uop_rxq_idx; // @[lsu.scala:208:16] reg [5:0] ldq_4_bits_uop_pdst; // @[lsu.scala:208:16] reg [5:0] ldq_4_bits_uop_prs1; // @[lsu.scala:208:16] reg [5:0] ldq_4_bits_uop_prs2; // @[lsu.scala:208:16] reg [5:0] ldq_4_bits_uop_prs3; // @[lsu.scala:208:16] reg ldq_4_bits_uop_prs1_busy; // @[lsu.scala:208:16] reg ldq_4_bits_uop_prs2_busy; // @[lsu.scala:208:16] reg ldq_4_bits_uop_prs3_busy; // @[lsu.scala:208:16] reg [5:0] ldq_4_bits_uop_stale_pdst; // @[lsu.scala:208:16] reg ldq_4_bits_uop_exception; // @[lsu.scala:208:16] reg [63:0] ldq_4_bits_uop_exc_cause; // @[lsu.scala:208:16] reg ldq_4_bits_uop_bypassable; // @[lsu.scala:208:16] reg [4:0] ldq_4_bits_uop_mem_cmd; // @[lsu.scala:208:16] reg [1:0] ldq_4_bits_uop_mem_size; // @[lsu.scala:208:16] reg ldq_4_bits_uop_mem_signed; // @[lsu.scala:208:16] reg ldq_4_bits_uop_is_fence; // @[lsu.scala:208:16] reg ldq_4_bits_uop_is_fencei; // @[lsu.scala:208:16] reg ldq_4_bits_uop_is_amo; // @[lsu.scala:208:16] reg ldq_4_bits_uop_uses_ldq; // @[lsu.scala:208:16] reg ldq_4_bits_uop_uses_stq; // @[lsu.scala:208:16] reg ldq_4_bits_uop_is_sys_pc2epc; // @[lsu.scala:208:16] reg ldq_4_bits_uop_is_unique; // @[lsu.scala:208:16] reg ldq_4_bits_uop_flush_on_commit; // @[lsu.scala:208:16] reg ldq_4_bits_uop_ldst_is_rs1; // @[lsu.scala:208:16] reg [5:0] ldq_4_bits_uop_ldst; // @[lsu.scala:208:16] reg [5:0] ldq_4_bits_uop_lrs1; // @[lsu.scala:208:16] reg [5:0] ldq_4_bits_uop_lrs2; // @[lsu.scala:208:16] reg [5:0] ldq_4_bits_uop_lrs3; // @[lsu.scala:208:16] reg ldq_4_bits_uop_ldst_val; // @[lsu.scala:208:16] reg [1:0] ldq_4_bits_uop_dst_rtype; // @[lsu.scala:208:16] reg [1:0] ldq_4_bits_uop_lrs1_rtype; // @[lsu.scala:208:16] reg [1:0] ldq_4_bits_uop_lrs2_rtype; // @[lsu.scala:208:16] reg ldq_4_bits_uop_frs3_en; // @[lsu.scala:208:16] reg ldq_4_bits_uop_fp_val; // @[lsu.scala:208:16] reg ldq_4_bits_uop_fp_single; // @[lsu.scala:208:16] reg ldq_4_bits_uop_xcpt_pf_if; // @[lsu.scala:208:16] reg ldq_4_bits_uop_xcpt_ae_if; // @[lsu.scala:208:16] reg ldq_4_bits_uop_xcpt_ma_if; // @[lsu.scala:208:16] reg ldq_4_bits_uop_bp_debug_if; // @[lsu.scala:208:16] reg ldq_4_bits_uop_bp_xcpt_if; // @[lsu.scala:208:16] reg [1:0] ldq_4_bits_uop_debug_fsrc; // @[lsu.scala:208:16] reg [1:0] ldq_4_bits_uop_debug_tsrc; // @[lsu.scala:208:16] reg ldq_4_bits_addr_valid; // @[lsu.scala:208:16] reg [39:0] ldq_4_bits_addr_bits; // @[lsu.scala:208:16] reg ldq_4_bits_addr_is_virtual; // @[lsu.scala:208:16] reg ldq_4_bits_addr_is_uncacheable; // @[lsu.scala:208:16] reg ldq_4_bits_executed; // @[lsu.scala:208:16] reg ldq_4_bits_succeeded; // @[lsu.scala:208:16] reg ldq_4_bits_order_fail; // @[lsu.scala:208:16] reg ldq_4_bits_observed; // @[lsu.scala:208:16] reg [7:0] ldq_4_bits_st_dep_mask; // @[lsu.scala:208:16] reg [2:0] ldq_4_bits_youngest_stq_idx; // @[lsu.scala:208:16] reg ldq_4_bits_forward_std_val; // @[lsu.scala:208:16] reg [2:0] ldq_4_bits_forward_stq_idx; // @[lsu.scala:208:16] reg [63:0] ldq_4_bits_debug_wb_data; // @[lsu.scala:208:16] reg ldq_5_valid; // @[lsu.scala:208:16] reg [6:0] ldq_5_bits_uop_uopc; // @[lsu.scala:208:16] reg [31:0] ldq_5_bits_uop_inst; // @[lsu.scala:208:16] reg [31:0] ldq_5_bits_uop_debug_inst; // @[lsu.scala:208:16] reg ldq_5_bits_uop_is_rvc; // @[lsu.scala:208:16] reg [39:0] ldq_5_bits_uop_debug_pc; // @[lsu.scala:208:16] reg [2:0] ldq_5_bits_uop_iq_type; // @[lsu.scala:208:16] reg [9:0] ldq_5_bits_uop_fu_code; // @[lsu.scala:208:16] reg [3:0] ldq_5_bits_uop_ctrl_br_type; // @[lsu.scala:208:16] reg [1:0] ldq_5_bits_uop_ctrl_op1_sel; // @[lsu.scala:208:16] reg [2:0] ldq_5_bits_uop_ctrl_op2_sel; // @[lsu.scala:208:16] reg [2:0] ldq_5_bits_uop_ctrl_imm_sel; // @[lsu.scala:208:16] reg [4:0] ldq_5_bits_uop_ctrl_op_fcn; // @[lsu.scala:208:16] reg ldq_5_bits_uop_ctrl_fcn_dw; // @[lsu.scala:208:16] reg [2:0] ldq_5_bits_uop_ctrl_csr_cmd; // @[lsu.scala:208:16] reg ldq_5_bits_uop_ctrl_is_load; // @[lsu.scala:208:16] reg ldq_5_bits_uop_ctrl_is_sta; // @[lsu.scala:208:16] reg ldq_5_bits_uop_ctrl_is_std; // @[lsu.scala:208:16] reg [1:0] ldq_5_bits_uop_iw_state; // @[lsu.scala:208:16] reg ldq_5_bits_uop_iw_p1_poisoned; // @[lsu.scala:208:16] reg ldq_5_bits_uop_iw_p2_poisoned; // @[lsu.scala:208:16] reg ldq_5_bits_uop_is_br; // @[lsu.scala:208:16] reg ldq_5_bits_uop_is_jalr; // @[lsu.scala:208:16] reg ldq_5_bits_uop_is_jal; // @[lsu.scala:208:16] reg ldq_5_bits_uop_is_sfb; // @[lsu.scala:208:16] reg [7:0] ldq_5_bits_uop_br_mask; // @[lsu.scala:208:16] reg [2:0] ldq_5_bits_uop_br_tag; // @[lsu.scala:208:16] reg [3:0] ldq_5_bits_uop_ftq_idx; // @[lsu.scala:208:16] reg ldq_5_bits_uop_edge_inst; // @[lsu.scala:208:16] reg [5:0] ldq_5_bits_uop_pc_lob; // @[lsu.scala:208:16] reg ldq_5_bits_uop_taken; // @[lsu.scala:208:16] reg [19:0] ldq_5_bits_uop_imm_packed; // @[lsu.scala:208:16] reg [11:0] ldq_5_bits_uop_csr_addr; // @[lsu.scala:208:16] reg [4:0] ldq_5_bits_uop_rob_idx; // @[lsu.scala:208:16] reg [2:0] ldq_5_bits_uop_ldq_idx; // @[lsu.scala:208:16] reg [2:0] ldq_5_bits_uop_stq_idx; // @[lsu.scala:208:16] reg [1:0] ldq_5_bits_uop_rxq_idx; // @[lsu.scala:208:16] reg [5:0] ldq_5_bits_uop_pdst; // @[lsu.scala:208:16] reg [5:0] ldq_5_bits_uop_prs1; // @[lsu.scala:208:16] reg [5:0] ldq_5_bits_uop_prs2; // @[lsu.scala:208:16] reg [5:0] ldq_5_bits_uop_prs3; // @[lsu.scala:208:16] reg ldq_5_bits_uop_prs1_busy; // @[lsu.scala:208:16] reg ldq_5_bits_uop_prs2_busy; // @[lsu.scala:208:16] reg ldq_5_bits_uop_prs3_busy; // @[lsu.scala:208:16] reg [5:0] ldq_5_bits_uop_stale_pdst; // @[lsu.scala:208:16] reg ldq_5_bits_uop_exception; // @[lsu.scala:208:16] reg [63:0] ldq_5_bits_uop_exc_cause; // @[lsu.scala:208:16] reg ldq_5_bits_uop_bypassable; // @[lsu.scala:208:16] reg [4:0] ldq_5_bits_uop_mem_cmd; // @[lsu.scala:208:16] reg [1:0] ldq_5_bits_uop_mem_size; // @[lsu.scala:208:16] reg ldq_5_bits_uop_mem_signed; // @[lsu.scala:208:16] reg ldq_5_bits_uop_is_fence; // @[lsu.scala:208:16] reg ldq_5_bits_uop_is_fencei; // @[lsu.scala:208:16] reg ldq_5_bits_uop_is_amo; // @[lsu.scala:208:16] reg ldq_5_bits_uop_uses_ldq; // @[lsu.scala:208:16] reg ldq_5_bits_uop_uses_stq; // @[lsu.scala:208:16] reg ldq_5_bits_uop_is_sys_pc2epc; // @[lsu.scala:208:16] reg ldq_5_bits_uop_is_unique; // @[lsu.scala:208:16] reg ldq_5_bits_uop_flush_on_commit; // @[lsu.scala:208:16] reg ldq_5_bits_uop_ldst_is_rs1; // @[lsu.scala:208:16] reg [5:0] ldq_5_bits_uop_ldst; // @[lsu.scala:208:16] reg [5:0] ldq_5_bits_uop_lrs1; // @[lsu.scala:208:16] reg [5:0] ldq_5_bits_uop_lrs2; // @[lsu.scala:208:16] reg [5:0] ldq_5_bits_uop_lrs3; // @[lsu.scala:208:16] reg ldq_5_bits_uop_ldst_val; // @[lsu.scala:208:16] reg [1:0] ldq_5_bits_uop_dst_rtype; // @[lsu.scala:208:16] reg [1:0] ldq_5_bits_uop_lrs1_rtype; // @[lsu.scala:208:16] reg [1:0] ldq_5_bits_uop_lrs2_rtype; // @[lsu.scala:208:16] reg ldq_5_bits_uop_frs3_en; // @[lsu.scala:208:16] reg ldq_5_bits_uop_fp_val; // @[lsu.scala:208:16] reg ldq_5_bits_uop_fp_single; // @[lsu.scala:208:16] reg ldq_5_bits_uop_xcpt_pf_if; // @[lsu.scala:208:16] reg ldq_5_bits_uop_xcpt_ae_if; // @[lsu.scala:208:16] reg ldq_5_bits_uop_xcpt_ma_if; // @[lsu.scala:208:16] reg ldq_5_bits_uop_bp_debug_if; // @[lsu.scala:208:16] reg ldq_5_bits_uop_bp_xcpt_if; // @[lsu.scala:208:16] reg [1:0] ldq_5_bits_uop_debug_fsrc; // @[lsu.scala:208:16] reg [1:0] ldq_5_bits_uop_debug_tsrc; // @[lsu.scala:208:16] reg ldq_5_bits_addr_valid; // @[lsu.scala:208:16] reg [39:0] ldq_5_bits_addr_bits; // @[lsu.scala:208:16] reg ldq_5_bits_addr_is_virtual; // @[lsu.scala:208:16] reg ldq_5_bits_addr_is_uncacheable; // @[lsu.scala:208:16] reg ldq_5_bits_executed; // @[lsu.scala:208:16] reg ldq_5_bits_succeeded; // @[lsu.scala:208:16] reg ldq_5_bits_order_fail; // @[lsu.scala:208:16] reg ldq_5_bits_observed; // @[lsu.scala:208:16] reg [7:0] ldq_5_bits_st_dep_mask; // @[lsu.scala:208:16] reg [2:0] ldq_5_bits_youngest_stq_idx; // @[lsu.scala:208:16] reg ldq_5_bits_forward_std_val; // @[lsu.scala:208:16] reg [2:0] ldq_5_bits_forward_stq_idx; // @[lsu.scala:208:16] reg [63:0] ldq_5_bits_debug_wb_data; // @[lsu.scala:208:16] reg ldq_6_valid; // @[lsu.scala:208:16] reg [6:0] ldq_6_bits_uop_uopc; // @[lsu.scala:208:16] reg [31:0] ldq_6_bits_uop_inst; // @[lsu.scala:208:16] reg [31:0] ldq_6_bits_uop_debug_inst; // @[lsu.scala:208:16] reg ldq_6_bits_uop_is_rvc; // @[lsu.scala:208:16] reg [39:0] ldq_6_bits_uop_debug_pc; // @[lsu.scala:208:16] reg [2:0] ldq_6_bits_uop_iq_type; // @[lsu.scala:208:16] reg [9:0] ldq_6_bits_uop_fu_code; // @[lsu.scala:208:16] reg [3:0] ldq_6_bits_uop_ctrl_br_type; // @[lsu.scala:208:16] reg [1:0] ldq_6_bits_uop_ctrl_op1_sel; // @[lsu.scala:208:16] reg [2:0] ldq_6_bits_uop_ctrl_op2_sel; // @[lsu.scala:208:16] reg [2:0] ldq_6_bits_uop_ctrl_imm_sel; // @[lsu.scala:208:16] reg [4:0] ldq_6_bits_uop_ctrl_op_fcn; // @[lsu.scala:208:16] reg ldq_6_bits_uop_ctrl_fcn_dw; // @[lsu.scala:208:16] reg [2:0] ldq_6_bits_uop_ctrl_csr_cmd; // @[lsu.scala:208:16] reg ldq_6_bits_uop_ctrl_is_load; // @[lsu.scala:208:16] reg ldq_6_bits_uop_ctrl_is_sta; // @[lsu.scala:208:16] reg ldq_6_bits_uop_ctrl_is_std; // @[lsu.scala:208:16] reg [1:0] ldq_6_bits_uop_iw_state; // @[lsu.scala:208:16] reg ldq_6_bits_uop_iw_p1_poisoned; // @[lsu.scala:208:16] reg ldq_6_bits_uop_iw_p2_poisoned; // @[lsu.scala:208:16] reg ldq_6_bits_uop_is_br; // @[lsu.scala:208:16] reg ldq_6_bits_uop_is_jalr; // @[lsu.scala:208:16] reg ldq_6_bits_uop_is_jal; // @[lsu.scala:208:16] reg ldq_6_bits_uop_is_sfb; // @[lsu.scala:208:16] reg [7:0] ldq_6_bits_uop_br_mask; // @[lsu.scala:208:16] reg [2:0] ldq_6_bits_uop_br_tag; // @[lsu.scala:208:16] reg [3:0] ldq_6_bits_uop_ftq_idx; // @[lsu.scala:208:16] reg ldq_6_bits_uop_edge_inst; // @[lsu.scala:208:16] reg [5:0] ldq_6_bits_uop_pc_lob; // @[lsu.scala:208:16] reg ldq_6_bits_uop_taken; // @[lsu.scala:208:16] reg [19:0] ldq_6_bits_uop_imm_packed; // @[lsu.scala:208:16] reg [11:0] ldq_6_bits_uop_csr_addr; // @[lsu.scala:208:16] reg [4:0] ldq_6_bits_uop_rob_idx; // @[lsu.scala:208:16] reg [2:0] ldq_6_bits_uop_ldq_idx; // @[lsu.scala:208:16] reg [2:0] ldq_6_bits_uop_stq_idx; // @[lsu.scala:208:16] reg [1:0] ldq_6_bits_uop_rxq_idx; // @[lsu.scala:208:16] reg [5:0] ldq_6_bits_uop_pdst; // @[lsu.scala:208:16] reg [5:0] ldq_6_bits_uop_prs1; // @[lsu.scala:208:16] reg [5:0] ldq_6_bits_uop_prs2; // @[lsu.scala:208:16] reg [5:0] ldq_6_bits_uop_prs3; // @[lsu.scala:208:16] reg ldq_6_bits_uop_prs1_busy; // @[lsu.scala:208:16] reg ldq_6_bits_uop_prs2_busy; // @[lsu.scala:208:16] reg ldq_6_bits_uop_prs3_busy; // @[lsu.scala:208:16] reg [5:0] ldq_6_bits_uop_stale_pdst; // @[lsu.scala:208:16] reg ldq_6_bits_uop_exception; // @[lsu.scala:208:16] reg [63:0] ldq_6_bits_uop_exc_cause; // @[lsu.scala:208:16] reg ldq_6_bits_uop_bypassable; // @[lsu.scala:208:16] reg [4:0] ldq_6_bits_uop_mem_cmd; // @[lsu.scala:208:16] reg [1:0] ldq_6_bits_uop_mem_size; // @[lsu.scala:208:16] reg ldq_6_bits_uop_mem_signed; // @[lsu.scala:208:16] reg ldq_6_bits_uop_is_fence; // @[lsu.scala:208:16] reg ldq_6_bits_uop_is_fencei; // @[lsu.scala:208:16] reg ldq_6_bits_uop_is_amo; // @[lsu.scala:208:16] reg ldq_6_bits_uop_uses_ldq; // @[lsu.scala:208:16] reg ldq_6_bits_uop_uses_stq; // @[lsu.scala:208:16] reg ldq_6_bits_uop_is_sys_pc2epc; // @[lsu.scala:208:16] reg ldq_6_bits_uop_is_unique; // @[lsu.scala:208:16] reg ldq_6_bits_uop_flush_on_commit; // @[lsu.scala:208:16] reg ldq_6_bits_uop_ldst_is_rs1; // @[lsu.scala:208:16] reg [5:0] ldq_6_bits_uop_ldst; // @[lsu.scala:208:16] reg [5:0] ldq_6_bits_uop_lrs1; // @[lsu.scala:208:16] reg [5:0] ldq_6_bits_uop_lrs2; // @[lsu.scala:208:16] reg [5:0] ldq_6_bits_uop_lrs3; // @[lsu.scala:208:16] reg ldq_6_bits_uop_ldst_val; // @[lsu.scala:208:16] reg [1:0] ldq_6_bits_uop_dst_rtype; // @[lsu.scala:208:16] reg [1:0] ldq_6_bits_uop_lrs1_rtype; // @[lsu.scala:208:16] reg [1:0] ldq_6_bits_uop_lrs2_rtype; // @[lsu.scala:208:16] reg ldq_6_bits_uop_frs3_en; // @[lsu.scala:208:16] reg ldq_6_bits_uop_fp_val; // @[lsu.scala:208:16] reg ldq_6_bits_uop_fp_single; // @[lsu.scala:208:16] reg ldq_6_bits_uop_xcpt_pf_if; // @[lsu.scala:208:16] reg ldq_6_bits_uop_xcpt_ae_if; // @[lsu.scala:208:16] reg ldq_6_bits_uop_xcpt_ma_if; // @[lsu.scala:208:16] reg ldq_6_bits_uop_bp_debug_if; // @[lsu.scala:208:16] reg ldq_6_bits_uop_bp_xcpt_if; // @[lsu.scala:208:16] reg [1:0] ldq_6_bits_uop_debug_fsrc; // @[lsu.scala:208:16] reg [1:0] ldq_6_bits_uop_debug_tsrc; // @[lsu.scala:208:16] reg ldq_6_bits_addr_valid; // @[lsu.scala:208:16] reg [39:0] ldq_6_bits_addr_bits; // @[lsu.scala:208:16] reg ldq_6_bits_addr_is_virtual; // @[lsu.scala:208:16] reg ldq_6_bits_addr_is_uncacheable; // @[lsu.scala:208:16] reg ldq_6_bits_executed; // @[lsu.scala:208:16] reg ldq_6_bits_succeeded; // @[lsu.scala:208:16] reg ldq_6_bits_order_fail; // @[lsu.scala:208:16] reg ldq_6_bits_observed; // @[lsu.scala:208:16] reg [7:0] ldq_6_bits_st_dep_mask; // @[lsu.scala:208:16] reg [2:0] ldq_6_bits_youngest_stq_idx; // @[lsu.scala:208:16] reg ldq_6_bits_forward_std_val; // @[lsu.scala:208:16] reg [2:0] ldq_6_bits_forward_stq_idx; // @[lsu.scala:208:16] reg [63:0] ldq_6_bits_debug_wb_data; // @[lsu.scala:208:16] reg ldq_7_valid; // @[lsu.scala:208:16] reg [6:0] ldq_7_bits_uop_uopc; // @[lsu.scala:208:16] reg [31:0] ldq_7_bits_uop_inst; // @[lsu.scala:208:16] reg [31:0] ldq_7_bits_uop_debug_inst; // @[lsu.scala:208:16] reg ldq_7_bits_uop_is_rvc; // @[lsu.scala:208:16] reg [39:0] ldq_7_bits_uop_debug_pc; // @[lsu.scala:208:16] reg [2:0] ldq_7_bits_uop_iq_type; // @[lsu.scala:208:16] reg [9:0] ldq_7_bits_uop_fu_code; // @[lsu.scala:208:16] reg [3:0] ldq_7_bits_uop_ctrl_br_type; // @[lsu.scala:208:16] reg [1:0] ldq_7_bits_uop_ctrl_op1_sel; // @[lsu.scala:208:16] reg [2:0] ldq_7_bits_uop_ctrl_op2_sel; // @[lsu.scala:208:16] reg [2:0] ldq_7_bits_uop_ctrl_imm_sel; // @[lsu.scala:208:16] reg [4:0] ldq_7_bits_uop_ctrl_op_fcn; // @[lsu.scala:208:16] reg ldq_7_bits_uop_ctrl_fcn_dw; // @[lsu.scala:208:16] reg [2:0] ldq_7_bits_uop_ctrl_csr_cmd; // @[lsu.scala:208:16] reg ldq_7_bits_uop_ctrl_is_load; // @[lsu.scala:208:16] reg ldq_7_bits_uop_ctrl_is_sta; // @[lsu.scala:208:16] reg ldq_7_bits_uop_ctrl_is_std; // @[lsu.scala:208:16] reg [1:0] ldq_7_bits_uop_iw_state; // @[lsu.scala:208:16] reg ldq_7_bits_uop_iw_p1_poisoned; // @[lsu.scala:208:16] reg ldq_7_bits_uop_iw_p2_poisoned; // @[lsu.scala:208:16] reg ldq_7_bits_uop_is_br; // @[lsu.scala:208:16] reg ldq_7_bits_uop_is_jalr; // @[lsu.scala:208:16] reg ldq_7_bits_uop_is_jal; // @[lsu.scala:208:16] reg ldq_7_bits_uop_is_sfb; // @[lsu.scala:208:16] reg [7:0] ldq_7_bits_uop_br_mask; // @[lsu.scala:208:16] reg [2:0] ldq_7_bits_uop_br_tag; // @[lsu.scala:208:16] reg [3:0] ldq_7_bits_uop_ftq_idx; // @[lsu.scala:208:16] reg ldq_7_bits_uop_edge_inst; // @[lsu.scala:208:16] reg [5:0] ldq_7_bits_uop_pc_lob; // @[lsu.scala:208:16] reg ldq_7_bits_uop_taken; // @[lsu.scala:208:16] reg [19:0] ldq_7_bits_uop_imm_packed; // @[lsu.scala:208:16] reg [11:0] ldq_7_bits_uop_csr_addr; // @[lsu.scala:208:16] reg [4:0] ldq_7_bits_uop_rob_idx; // @[lsu.scala:208:16] reg [2:0] ldq_7_bits_uop_ldq_idx; // @[lsu.scala:208:16] reg [2:0] ldq_7_bits_uop_stq_idx; // @[lsu.scala:208:16] reg [1:0] ldq_7_bits_uop_rxq_idx; // @[lsu.scala:208:16] reg [5:0] ldq_7_bits_uop_pdst; // @[lsu.scala:208:16] reg [5:0] ldq_7_bits_uop_prs1; // @[lsu.scala:208:16] reg [5:0] ldq_7_bits_uop_prs2; // @[lsu.scala:208:16] reg [5:0] ldq_7_bits_uop_prs3; // @[lsu.scala:208:16] reg ldq_7_bits_uop_prs1_busy; // @[lsu.scala:208:16] reg ldq_7_bits_uop_prs2_busy; // @[lsu.scala:208:16] reg ldq_7_bits_uop_prs3_busy; // @[lsu.scala:208:16] reg [5:0] ldq_7_bits_uop_stale_pdst; // @[lsu.scala:208:16] reg ldq_7_bits_uop_exception; // @[lsu.scala:208:16] reg [63:0] ldq_7_bits_uop_exc_cause; // @[lsu.scala:208:16] reg ldq_7_bits_uop_bypassable; // @[lsu.scala:208:16] reg [4:0] ldq_7_bits_uop_mem_cmd; // @[lsu.scala:208:16] reg [1:0] ldq_7_bits_uop_mem_size; // @[lsu.scala:208:16] reg ldq_7_bits_uop_mem_signed; // @[lsu.scala:208:16] reg ldq_7_bits_uop_is_fence; // @[lsu.scala:208:16] reg ldq_7_bits_uop_is_fencei; // @[lsu.scala:208:16] reg ldq_7_bits_uop_is_amo; // @[lsu.scala:208:16] reg ldq_7_bits_uop_uses_ldq; // @[lsu.scala:208:16] reg ldq_7_bits_uop_uses_stq; // @[lsu.scala:208:16] reg ldq_7_bits_uop_is_sys_pc2epc; // @[lsu.scala:208:16] reg ldq_7_bits_uop_is_unique; // @[lsu.scala:208:16] reg ldq_7_bits_uop_flush_on_commit; // @[lsu.scala:208:16] reg ldq_7_bits_uop_ldst_is_rs1; // @[lsu.scala:208:16] reg [5:0] ldq_7_bits_uop_ldst; // @[lsu.scala:208:16] reg [5:0] ldq_7_bits_uop_lrs1; // @[lsu.scala:208:16] reg [5:0] ldq_7_bits_uop_lrs2; // @[lsu.scala:208:16] reg [5:0] ldq_7_bits_uop_lrs3; // @[lsu.scala:208:16] reg ldq_7_bits_uop_ldst_val; // @[lsu.scala:208:16] reg [1:0] ldq_7_bits_uop_dst_rtype; // @[lsu.scala:208:16] reg [1:0] ldq_7_bits_uop_lrs1_rtype; // @[lsu.scala:208:16] reg [1:0] ldq_7_bits_uop_lrs2_rtype; // @[lsu.scala:208:16] reg ldq_7_bits_uop_frs3_en; // @[lsu.scala:208:16] reg ldq_7_bits_uop_fp_val; // @[lsu.scala:208:16] reg ldq_7_bits_uop_fp_single; // @[lsu.scala:208:16] reg ldq_7_bits_uop_xcpt_pf_if; // @[lsu.scala:208:16] reg ldq_7_bits_uop_xcpt_ae_if; // @[lsu.scala:208:16] reg ldq_7_bits_uop_xcpt_ma_if; // @[lsu.scala:208:16] reg ldq_7_bits_uop_bp_debug_if; // @[lsu.scala:208:16] reg ldq_7_bits_uop_bp_xcpt_if; // @[lsu.scala:208:16] reg [1:0] ldq_7_bits_uop_debug_fsrc; // @[lsu.scala:208:16] reg [1:0] ldq_7_bits_uop_debug_tsrc; // @[lsu.scala:208:16] reg ldq_7_bits_addr_valid; // @[lsu.scala:208:16] reg [39:0] ldq_7_bits_addr_bits; // @[lsu.scala:208:16] reg ldq_7_bits_addr_is_virtual; // @[lsu.scala:208:16] reg ldq_7_bits_addr_is_uncacheable; // @[lsu.scala:208:16] reg ldq_7_bits_executed; // @[lsu.scala:208:16] reg ldq_7_bits_succeeded; // @[lsu.scala:208:16] reg ldq_7_bits_order_fail; // @[lsu.scala:208:16] reg ldq_7_bits_observed; // @[lsu.scala:208:16] reg [7:0] ldq_7_bits_st_dep_mask; // @[lsu.scala:208:16] reg [2:0] ldq_7_bits_youngest_stq_idx; // @[lsu.scala:208:16] reg ldq_7_bits_forward_std_val; // @[lsu.scala:208:16] reg [2:0] ldq_7_bits_forward_stq_idx; // @[lsu.scala:208:16] reg [63:0] ldq_7_bits_debug_wb_data; // @[lsu.scala:208:16] reg stq_0_valid; // @[lsu.scala:209:16] reg [6:0] stq_0_bits_uop_uopc; // @[lsu.scala:209:16] reg [31:0] stq_0_bits_uop_inst; // @[lsu.scala:209:16] reg [31:0] stq_0_bits_uop_debug_inst; // @[lsu.scala:209:16] reg stq_0_bits_uop_is_rvc; // @[lsu.scala:209:16] reg [39:0] stq_0_bits_uop_debug_pc; // @[lsu.scala:209:16] reg [2:0] stq_0_bits_uop_iq_type; // @[lsu.scala:209:16] reg [9:0] stq_0_bits_uop_fu_code; // @[lsu.scala:209:16] reg [3:0] stq_0_bits_uop_ctrl_br_type; // @[lsu.scala:209:16] reg [1:0] stq_0_bits_uop_ctrl_op1_sel; // @[lsu.scala:209:16] reg [2:0] stq_0_bits_uop_ctrl_op2_sel; // @[lsu.scala:209:16] reg [2:0] stq_0_bits_uop_ctrl_imm_sel; // @[lsu.scala:209:16] reg [4:0] stq_0_bits_uop_ctrl_op_fcn; // @[lsu.scala:209:16] reg stq_0_bits_uop_ctrl_fcn_dw; // @[lsu.scala:209:16] reg [2:0] stq_0_bits_uop_ctrl_csr_cmd; // @[lsu.scala:209:16] reg stq_0_bits_uop_ctrl_is_load; // @[lsu.scala:209:16] reg stq_0_bits_uop_ctrl_is_sta; // @[lsu.scala:209:16] reg stq_0_bits_uop_ctrl_is_std; // @[lsu.scala:209:16] reg [1:0] stq_0_bits_uop_iw_state; // @[lsu.scala:209:16] reg stq_0_bits_uop_iw_p1_poisoned; // @[lsu.scala:209:16] reg stq_0_bits_uop_iw_p2_poisoned; // @[lsu.scala:209:16] reg stq_0_bits_uop_is_br; // @[lsu.scala:209:16] reg stq_0_bits_uop_is_jalr; // @[lsu.scala:209:16] reg stq_0_bits_uop_is_jal; // @[lsu.scala:209:16] reg stq_0_bits_uop_is_sfb; // @[lsu.scala:209:16] reg [7:0] stq_0_bits_uop_br_mask; // @[lsu.scala:209:16] reg [2:0] stq_0_bits_uop_br_tag; // @[lsu.scala:209:16] reg [3:0] stq_0_bits_uop_ftq_idx; // @[lsu.scala:209:16] reg stq_0_bits_uop_edge_inst; // @[lsu.scala:209:16] reg [5:0] stq_0_bits_uop_pc_lob; // @[lsu.scala:209:16] reg stq_0_bits_uop_taken; // @[lsu.scala:209:16] reg [19:0] stq_0_bits_uop_imm_packed; // @[lsu.scala:209:16] reg [11:0] stq_0_bits_uop_csr_addr; // @[lsu.scala:209:16] reg [4:0] stq_0_bits_uop_rob_idx; // @[lsu.scala:209:16] reg [2:0] stq_0_bits_uop_ldq_idx; // @[lsu.scala:209:16] reg [2:0] stq_0_bits_uop_stq_idx; // @[lsu.scala:209:16] reg [1:0] stq_0_bits_uop_rxq_idx; // @[lsu.scala:209:16] reg [5:0] stq_0_bits_uop_pdst; // @[lsu.scala:209:16] reg [5:0] stq_0_bits_uop_prs1; // @[lsu.scala:209:16] reg [5:0] stq_0_bits_uop_prs2; // @[lsu.scala:209:16] reg [5:0] stq_0_bits_uop_prs3; // @[lsu.scala:209:16] reg [3:0] stq_0_bits_uop_ppred; // @[lsu.scala:209:16] reg stq_0_bits_uop_prs1_busy; // @[lsu.scala:209:16] reg stq_0_bits_uop_prs2_busy; // @[lsu.scala:209:16] reg stq_0_bits_uop_prs3_busy; // @[lsu.scala:209:16] reg stq_0_bits_uop_ppred_busy; // @[lsu.scala:209:16] reg [5:0] stq_0_bits_uop_stale_pdst; // @[lsu.scala:209:16] reg stq_0_bits_uop_exception; // @[lsu.scala:209:16] reg [63:0] stq_0_bits_uop_exc_cause; // @[lsu.scala:209:16] reg stq_0_bits_uop_bypassable; // @[lsu.scala:209:16] reg [4:0] stq_0_bits_uop_mem_cmd; // @[lsu.scala:209:16] reg [1:0] stq_0_bits_uop_mem_size; // @[lsu.scala:209:16] reg stq_0_bits_uop_mem_signed; // @[lsu.scala:209:16] reg stq_0_bits_uop_is_fence; // @[lsu.scala:209:16] reg stq_0_bits_uop_is_fencei; // @[lsu.scala:209:16] reg stq_0_bits_uop_is_amo; // @[lsu.scala:209:16] reg stq_0_bits_uop_uses_ldq; // @[lsu.scala:209:16] reg stq_0_bits_uop_uses_stq; // @[lsu.scala:209:16] reg stq_0_bits_uop_is_sys_pc2epc; // @[lsu.scala:209:16] reg stq_0_bits_uop_is_unique; // @[lsu.scala:209:16] reg stq_0_bits_uop_flush_on_commit; // @[lsu.scala:209:16] reg stq_0_bits_uop_ldst_is_rs1; // @[lsu.scala:209:16] reg [5:0] stq_0_bits_uop_ldst; // @[lsu.scala:209:16] reg [5:0] stq_0_bits_uop_lrs1; // @[lsu.scala:209:16] reg [5:0] stq_0_bits_uop_lrs2; // @[lsu.scala:209:16] reg [5:0] stq_0_bits_uop_lrs3; // @[lsu.scala:209:16] reg stq_0_bits_uop_ldst_val; // @[lsu.scala:209:16] reg [1:0] stq_0_bits_uop_dst_rtype; // @[lsu.scala:209:16] reg [1:0] stq_0_bits_uop_lrs1_rtype; // @[lsu.scala:209:16] reg [1:0] stq_0_bits_uop_lrs2_rtype; // @[lsu.scala:209:16] reg stq_0_bits_uop_frs3_en; // @[lsu.scala:209:16] reg stq_0_bits_uop_fp_val; // @[lsu.scala:209:16] reg stq_0_bits_uop_fp_single; // @[lsu.scala:209:16] reg stq_0_bits_uop_xcpt_pf_if; // @[lsu.scala:209:16] reg stq_0_bits_uop_xcpt_ae_if; // @[lsu.scala:209:16] reg stq_0_bits_uop_xcpt_ma_if; // @[lsu.scala:209:16] reg stq_0_bits_uop_bp_debug_if; // @[lsu.scala:209:16] reg stq_0_bits_uop_bp_xcpt_if; // @[lsu.scala:209:16] reg [1:0] stq_0_bits_uop_debug_fsrc; // @[lsu.scala:209:16] reg [1:0] stq_0_bits_uop_debug_tsrc; // @[lsu.scala:209:16] reg stq_0_bits_addr_valid; // @[lsu.scala:209:16] reg [39:0] stq_0_bits_addr_bits; // @[lsu.scala:209:16] reg stq_0_bits_addr_is_virtual; // @[lsu.scala:209:16] reg stq_0_bits_data_valid; // @[lsu.scala:209:16] reg [63:0] stq_0_bits_data_bits; // @[lsu.scala:209:16] reg stq_0_bits_committed; // @[lsu.scala:209:16] reg stq_0_bits_succeeded; // @[lsu.scala:209:16] reg [63:0] stq_0_bits_debug_wb_data; // @[lsu.scala:209:16] reg stq_1_valid; // @[lsu.scala:209:16] reg [6:0] stq_1_bits_uop_uopc; // @[lsu.scala:209:16] reg [31:0] stq_1_bits_uop_inst; // @[lsu.scala:209:16] reg [31:0] stq_1_bits_uop_debug_inst; // @[lsu.scala:209:16] reg stq_1_bits_uop_is_rvc; // @[lsu.scala:209:16] reg [39:0] stq_1_bits_uop_debug_pc; // @[lsu.scala:209:16] reg [2:0] stq_1_bits_uop_iq_type; // @[lsu.scala:209:16] reg [9:0] stq_1_bits_uop_fu_code; // @[lsu.scala:209:16] reg [3:0] stq_1_bits_uop_ctrl_br_type; // @[lsu.scala:209:16] reg [1:0] stq_1_bits_uop_ctrl_op1_sel; // @[lsu.scala:209:16] reg [2:0] stq_1_bits_uop_ctrl_op2_sel; // @[lsu.scala:209:16] reg [2:0] stq_1_bits_uop_ctrl_imm_sel; // @[lsu.scala:209:16] reg [4:0] stq_1_bits_uop_ctrl_op_fcn; // @[lsu.scala:209:16] reg stq_1_bits_uop_ctrl_fcn_dw; // @[lsu.scala:209:16] reg [2:0] stq_1_bits_uop_ctrl_csr_cmd; // @[lsu.scala:209:16] reg stq_1_bits_uop_ctrl_is_load; // @[lsu.scala:209:16] reg stq_1_bits_uop_ctrl_is_sta; // @[lsu.scala:209:16] reg stq_1_bits_uop_ctrl_is_std; // @[lsu.scala:209:16] reg [1:0] stq_1_bits_uop_iw_state; // @[lsu.scala:209:16] reg stq_1_bits_uop_iw_p1_poisoned; // @[lsu.scala:209:16] reg stq_1_bits_uop_iw_p2_poisoned; // @[lsu.scala:209:16] reg stq_1_bits_uop_is_br; // @[lsu.scala:209:16] reg stq_1_bits_uop_is_jalr; // @[lsu.scala:209:16] reg stq_1_bits_uop_is_jal; // @[lsu.scala:209:16] reg stq_1_bits_uop_is_sfb; // @[lsu.scala:209:16] reg [7:0] stq_1_bits_uop_br_mask; // @[lsu.scala:209:16] reg [2:0] stq_1_bits_uop_br_tag; // @[lsu.scala:209:16] reg [3:0] stq_1_bits_uop_ftq_idx; // @[lsu.scala:209:16] reg stq_1_bits_uop_edge_inst; // @[lsu.scala:209:16] reg [5:0] stq_1_bits_uop_pc_lob; // @[lsu.scala:209:16] reg stq_1_bits_uop_taken; // @[lsu.scala:209:16] reg [19:0] stq_1_bits_uop_imm_packed; // @[lsu.scala:209:16] reg [11:0] stq_1_bits_uop_csr_addr; // @[lsu.scala:209:16] reg [4:0] stq_1_bits_uop_rob_idx; // @[lsu.scala:209:16] reg [2:0] stq_1_bits_uop_ldq_idx; // @[lsu.scala:209:16] reg [2:0] stq_1_bits_uop_stq_idx; // @[lsu.scala:209:16] reg [1:0] stq_1_bits_uop_rxq_idx; // @[lsu.scala:209:16] reg [5:0] stq_1_bits_uop_pdst; // @[lsu.scala:209:16] reg [5:0] stq_1_bits_uop_prs1; // @[lsu.scala:209:16] reg [5:0] stq_1_bits_uop_prs2; // @[lsu.scala:209:16] reg [5:0] stq_1_bits_uop_prs3; // @[lsu.scala:209:16] reg [3:0] stq_1_bits_uop_ppred; // @[lsu.scala:209:16] reg stq_1_bits_uop_prs1_busy; // @[lsu.scala:209:16] reg stq_1_bits_uop_prs2_busy; // @[lsu.scala:209:16] reg stq_1_bits_uop_prs3_busy; // @[lsu.scala:209:16] reg stq_1_bits_uop_ppred_busy; // @[lsu.scala:209:16] reg [5:0] stq_1_bits_uop_stale_pdst; // @[lsu.scala:209:16] reg stq_1_bits_uop_exception; // @[lsu.scala:209:16] reg [63:0] stq_1_bits_uop_exc_cause; // @[lsu.scala:209:16] reg stq_1_bits_uop_bypassable; // @[lsu.scala:209:16] reg [4:0] stq_1_bits_uop_mem_cmd; // @[lsu.scala:209:16] reg [1:0] stq_1_bits_uop_mem_size; // @[lsu.scala:209:16] reg stq_1_bits_uop_mem_signed; // @[lsu.scala:209:16] reg stq_1_bits_uop_is_fence; // @[lsu.scala:209:16] reg stq_1_bits_uop_is_fencei; // @[lsu.scala:209:16] reg stq_1_bits_uop_is_amo; // @[lsu.scala:209:16] reg stq_1_bits_uop_uses_ldq; // @[lsu.scala:209:16] reg stq_1_bits_uop_uses_stq; // @[lsu.scala:209:16] reg stq_1_bits_uop_is_sys_pc2epc; // @[lsu.scala:209:16] reg stq_1_bits_uop_is_unique; // @[lsu.scala:209:16] reg stq_1_bits_uop_flush_on_commit; // @[lsu.scala:209:16] reg stq_1_bits_uop_ldst_is_rs1; // @[lsu.scala:209:16] reg [5:0] stq_1_bits_uop_ldst; // @[lsu.scala:209:16] reg [5:0] stq_1_bits_uop_lrs1; // @[lsu.scala:209:16] reg [5:0] stq_1_bits_uop_lrs2; // @[lsu.scala:209:16] reg [5:0] stq_1_bits_uop_lrs3; // @[lsu.scala:209:16] reg stq_1_bits_uop_ldst_val; // @[lsu.scala:209:16] reg [1:0] stq_1_bits_uop_dst_rtype; // @[lsu.scala:209:16] reg [1:0] stq_1_bits_uop_lrs1_rtype; // @[lsu.scala:209:16] reg [1:0] stq_1_bits_uop_lrs2_rtype; // @[lsu.scala:209:16] reg stq_1_bits_uop_frs3_en; // @[lsu.scala:209:16] reg stq_1_bits_uop_fp_val; // @[lsu.scala:209:16] reg stq_1_bits_uop_fp_single; // @[lsu.scala:209:16] reg stq_1_bits_uop_xcpt_pf_if; // @[lsu.scala:209:16] reg stq_1_bits_uop_xcpt_ae_if; // @[lsu.scala:209:16] reg stq_1_bits_uop_xcpt_ma_if; // @[lsu.scala:209:16] reg stq_1_bits_uop_bp_debug_if; // @[lsu.scala:209:16] reg stq_1_bits_uop_bp_xcpt_if; // @[lsu.scala:209:16] reg [1:0] stq_1_bits_uop_debug_fsrc; // @[lsu.scala:209:16] reg [1:0] stq_1_bits_uop_debug_tsrc; // @[lsu.scala:209:16] reg stq_1_bits_addr_valid; // @[lsu.scala:209:16] reg [39:0] stq_1_bits_addr_bits; // @[lsu.scala:209:16] reg stq_1_bits_addr_is_virtual; // @[lsu.scala:209:16] reg stq_1_bits_data_valid; // @[lsu.scala:209:16] reg [63:0] stq_1_bits_data_bits; // @[lsu.scala:209:16] reg stq_1_bits_committed; // @[lsu.scala:209:16] reg stq_1_bits_succeeded; // @[lsu.scala:209:16] reg [63:0] stq_1_bits_debug_wb_data; // @[lsu.scala:209:16] reg stq_2_valid; // @[lsu.scala:209:16] reg [6:0] stq_2_bits_uop_uopc; // @[lsu.scala:209:16] reg [31:0] stq_2_bits_uop_inst; // @[lsu.scala:209:16] reg [31:0] stq_2_bits_uop_debug_inst; // @[lsu.scala:209:16] reg stq_2_bits_uop_is_rvc; // @[lsu.scala:209:16] reg [39:0] stq_2_bits_uop_debug_pc; // @[lsu.scala:209:16] reg [2:0] stq_2_bits_uop_iq_type; // @[lsu.scala:209:16] reg [9:0] stq_2_bits_uop_fu_code; // @[lsu.scala:209:16] reg [3:0] stq_2_bits_uop_ctrl_br_type; // @[lsu.scala:209:16] reg [1:0] stq_2_bits_uop_ctrl_op1_sel; // @[lsu.scala:209:16] reg [2:0] stq_2_bits_uop_ctrl_op2_sel; // @[lsu.scala:209:16] reg [2:0] stq_2_bits_uop_ctrl_imm_sel; // @[lsu.scala:209:16] reg [4:0] stq_2_bits_uop_ctrl_op_fcn; // @[lsu.scala:209:16] reg stq_2_bits_uop_ctrl_fcn_dw; // @[lsu.scala:209:16] reg [2:0] stq_2_bits_uop_ctrl_csr_cmd; // @[lsu.scala:209:16] reg stq_2_bits_uop_ctrl_is_load; // @[lsu.scala:209:16] reg stq_2_bits_uop_ctrl_is_sta; // @[lsu.scala:209:16] reg stq_2_bits_uop_ctrl_is_std; // @[lsu.scala:209:16] reg [1:0] stq_2_bits_uop_iw_state; // @[lsu.scala:209:16] reg stq_2_bits_uop_iw_p1_poisoned; // @[lsu.scala:209:16] reg stq_2_bits_uop_iw_p2_poisoned; // @[lsu.scala:209:16] reg stq_2_bits_uop_is_br; // @[lsu.scala:209:16] reg stq_2_bits_uop_is_jalr; // @[lsu.scala:209:16] reg stq_2_bits_uop_is_jal; // @[lsu.scala:209:16] reg stq_2_bits_uop_is_sfb; // @[lsu.scala:209:16] reg [7:0] stq_2_bits_uop_br_mask; // @[lsu.scala:209:16] reg [2:0] stq_2_bits_uop_br_tag; // @[lsu.scala:209:16] reg [3:0] stq_2_bits_uop_ftq_idx; // @[lsu.scala:209:16] reg stq_2_bits_uop_edge_inst; // @[lsu.scala:209:16] reg [5:0] stq_2_bits_uop_pc_lob; // @[lsu.scala:209:16] reg stq_2_bits_uop_taken; // @[lsu.scala:209:16] reg [19:0] stq_2_bits_uop_imm_packed; // @[lsu.scala:209:16] reg [11:0] stq_2_bits_uop_csr_addr; // @[lsu.scala:209:16] reg [4:0] stq_2_bits_uop_rob_idx; // @[lsu.scala:209:16] reg [2:0] stq_2_bits_uop_ldq_idx; // @[lsu.scala:209:16] reg [2:0] stq_2_bits_uop_stq_idx; // @[lsu.scala:209:16] reg [1:0] stq_2_bits_uop_rxq_idx; // @[lsu.scala:209:16] reg [5:0] stq_2_bits_uop_pdst; // @[lsu.scala:209:16] reg [5:0] stq_2_bits_uop_prs1; // @[lsu.scala:209:16] reg [5:0] stq_2_bits_uop_prs2; // @[lsu.scala:209:16] reg [5:0] stq_2_bits_uop_prs3; // @[lsu.scala:209:16] reg [3:0] stq_2_bits_uop_ppred; // @[lsu.scala:209:16] reg stq_2_bits_uop_prs1_busy; // @[lsu.scala:209:16] reg stq_2_bits_uop_prs2_busy; // @[lsu.scala:209:16] reg stq_2_bits_uop_prs3_busy; // @[lsu.scala:209:16] reg stq_2_bits_uop_ppred_busy; // @[lsu.scala:209:16] reg [5:0] stq_2_bits_uop_stale_pdst; // @[lsu.scala:209:16] reg stq_2_bits_uop_exception; // @[lsu.scala:209:16] reg [63:0] stq_2_bits_uop_exc_cause; // @[lsu.scala:209:16] reg stq_2_bits_uop_bypassable; // @[lsu.scala:209:16] reg [4:0] stq_2_bits_uop_mem_cmd; // @[lsu.scala:209:16] reg [1:0] stq_2_bits_uop_mem_size; // @[lsu.scala:209:16] reg stq_2_bits_uop_mem_signed; // @[lsu.scala:209:16] reg stq_2_bits_uop_is_fence; // @[lsu.scala:209:16] reg stq_2_bits_uop_is_fencei; // @[lsu.scala:209:16] reg stq_2_bits_uop_is_amo; // @[lsu.scala:209:16] reg stq_2_bits_uop_uses_ldq; // @[lsu.scala:209:16] reg stq_2_bits_uop_uses_stq; // @[lsu.scala:209:16] reg stq_2_bits_uop_is_sys_pc2epc; // @[lsu.scala:209:16] reg stq_2_bits_uop_is_unique; // @[lsu.scala:209:16] reg stq_2_bits_uop_flush_on_commit; // @[lsu.scala:209:16] reg stq_2_bits_uop_ldst_is_rs1; // @[lsu.scala:209:16] reg [5:0] stq_2_bits_uop_ldst; // @[lsu.scala:209:16] reg [5:0] stq_2_bits_uop_lrs1; // @[lsu.scala:209:16] reg [5:0] stq_2_bits_uop_lrs2; // @[lsu.scala:209:16] reg [5:0] stq_2_bits_uop_lrs3; // @[lsu.scala:209:16] reg stq_2_bits_uop_ldst_val; // @[lsu.scala:209:16] reg [1:0] stq_2_bits_uop_dst_rtype; // @[lsu.scala:209:16] reg [1:0] stq_2_bits_uop_lrs1_rtype; // @[lsu.scala:209:16] reg [1:0] stq_2_bits_uop_lrs2_rtype; // @[lsu.scala:209:16] reg stq_2_bits_uop_frs3_en; // @[lsu.scala:209:16] reg stq_2_bits_uop_fp_val; // @[lsu.scala:209:16] reg stq_2_bits_uop_fp_single; // @[lsu.scala:209:16] reg stq_2_bits_uop_xcpt_pf_if; // @[lsu.scala:209:16] reg stq_2_bits_uop_xcpt_ae_if; // @[lsu.scala:209:16] reg stq_2_bits_uop_xcpt_ma_if; // @[lsu.scala:209:16] reg stq_2_bits_uop_bp_debug_if; // @[lsu.scala:209:16] reg stq_2_bits_uop_bp_xcpt_if; // @[lsu.scala:209:16] reg [1:0] stq_2_bits_uop_debug_fsrc; // @[lsu.scala:209:16] reg [1:0] stq_2_bits_uop_debug_tsrc; // @[lsu.scala:209:16] reg stq_2_bits_addr_valid; // @[lsu.scala:209:16] reg [39:0] stq_2_bits_addr_bits; // @[lsu.scala:209:16] reg stq_2_bits_addr_is_virtual; // @[lsu.scala:209:16] reg stq_2_bits_data_valid; // @[lsu.scala:209:16] reg [63:0] stq_2_bits_data_bits; // @[lsu.scala:209:16] reg stq_2_bits_committed; // @[lsu.scala:209:16] reg stq_2_bits_succeeded; // @[lsu.scala:209:16] reg [63:0] stq_2_bits_debug_wb_data; // @[lsu.scala:209:16] reg stq_3_valid; // @[lsu.scala:209:16] reg [6:0] stq_3_bits_uop_uopc; // @[lsu.scala:209:16] reg [31:0] stq_3_bits_uop_inst; // @[lsu.scala:209:16] reg [31:0] stq_3_bits_uop_debug_inst; // @[lsu.scala:209:16] reg stq_3_bits_uop_is_rvc; // @[lsu.scala:209:16] reg [39:0] stq_3_bits_uop_debug_pc; // @[lsu.scala:209:16] reg [2:0] stq_3_bits_uop_iq_type; // @[lsu.scala:209:16] reg [9:0] stq_3_bits_uop_fu_code; // @[lsu.scala:209:16] reg [3:0] stq_3_bits_uop_ctrl_br_type; // @[lsu.scala:209:16] reg [1:0] stq_3_bits_uop_ctrl_op1_sel; // @[lsu.scala:209:16] reg [2:0] stq_3_bits_uop_ctrl_op2_sel; // @[lsu.scala:209:16] reg [2:0] stq_3_bits_uop_ctrl_imm_sel; // @[lsu.scala:209:16] reg [4:0] stq_3_bits_uop_ctrl_op_fcn; // @[lsu.scala:209:16] reg stq_3_bits_uop_ctrl_fcn_dw; // @[lsu.scala:209:16] reg [2:0] stq_3_bits_uop_ctrl_csr_cmd; // @[lsu.scala:209:16] reg stq_3_bits_uop_ctrl_is_load; // @[lsu.scala:209:16] reg stq_3_bits_uop_ctrl_is_sta; // @[lsu.scala:209:16] reg stq_3_bits_uop_ctrl_is_std; // @[lsu.scala:209:16] reg [1:0] stq_3_bits_uop_iw_state; // @[lsu.scala:209:16] reg stq_3_bits_uop_iw_p1_poisoned; // @[lsu.scala:209:16] reg stq_3_bits_uop_iw_p2_poisoned; // @[lsu.scala:209:16] reg stq_3_bits_uop_is_br; // @[lsu.scala:209:16] reg stq_3_bits_uop_is_jalr; // @[lsu.scala:209:16] reg stq_3_bits_uop_is_jal; // @[lsu.scala:209:16] reg stq_3_bits_uop_is_sfb; // @[lsu.scala:209:16] reg [7:0] stq_3_bits_uop_br_mask; // @[lsu.scala:209:16] reg [2:0] stq_3_bits_uop_br_tag; // @[lsu.scala:209:16] reg [3:0] stq_3_bits_uop_ftq_idx; // @[lsu.scala:209:16] reg stq_3_bits_uop_edge_inst; // @[lsu.scala:209:16] reg [5:0] stq_3_bits_uop_pc_lob; // @[lsu.scala:209:16] reg stq_3_bits_uop_taken; // @[lsu.scala:209:16] reg [19:0] stq_3_bits_uop_imm_packed; // @[lsu.scala:209:16] reg [11:0] stq_3_bits_uop_csr_addr; // @[lsu.scala:209:16] reg [4:0] stq_3_bits_uop_rob_idx; // @[lsu.scala:209:16] reg [2:0] stq_3_bits_uop_ldq_idx; // @[lsu.scala:209:16] reg [2:0] stq_3_bits_uop_stq_idx; // @[lsu.scala:209:16] reg [1:0] stq_3_bits_uop_rxq_idx; // @[lsu.scala:209:16] reg [5:0] stq_3_bits_uop_pdst; // @[lsu.scala:209:16] reg [5:0] stq_3_bits_uop_prs1; // @[lsu.scala:209:16] reg [5:0] stq_3_bits_uop_prs2; // @[lsu.scala:209:16] reg [5:0] stq_3_bits_uop_prs3; // @[lsu.scala:209:16] reg [3:0] stq_3_bits_uop_ppred; // @[lsu.scala:209:16] reg stq_3_bits_uop_prs1_busy; // @[lsu.scala:209:16] reg stq_3_bits_uop_prs2_busy; // @[lsu.scala:209:16] reg stq_3_bits_uop_prs3_busy; // @[lsu.scala:209:16] reg stq_3_bits_uop_ppred_busy; // @[lsu.scala:209:16] reg [5:0] stq_3_bits_uop_stale_pdst; // @[lsu.scala:209:16] reg stq_3_bits_uop_exception; // @[lsu.scala:209:16] reg [63:0] stq_3_bits_uop_exc_cause; // @[lsu.scala:209:16] reg stq_3_bits_uop_bypassable; // @[lsu.scala:209:16] reg [4:0] stq_3_bits_uop_mem_cmd; // @[lsu.scala:209:16] reg [1:0] stq_3_bits_uop_mem_size; // @[lsu.scala:209:16] reg stq_3_bits_uop_mem_signed; // @[lsu.scala:209:16] reg stq_3_bits_uop_is_fence; // @[lsu.scala:209:16] reg stq_3_bits_uop_is_fencei; // @[lsu.scala:209:16] reg stq_3_bits_uop_is_amo; // @[lsu.scala:209:16] reg stq_3_bits_uop_uses_ldq; // @[lsu.scala:209:16] reg stq_3_bits_uop_uses_stq; // @[lsu.scala:209:16] reg stq_3_bits_uop_is_sys_pc2epc; // @[lsu.scala:209:16] reg stq_3_bits_uop_is_unique; // @[lsu.scala:209:16] reg stq_3_bits_uop_flush_on_commit; // @[lsu.scala:209:16] reg stq_3_bits_uop_ldst_is_rs1; // @[lsu.scala:209:16] reg [5:0] stq_3_bits_uop_ldst; // @[lsu.scala:209:16] reg [5:0] stq_3_bits_uop_lrs1; // @[lsu.scala:209:16] reg [5:0] stq_3_bits_uop_lrs2; // @[lsu.scala:209:16] reg [5:0] stq_3_bits_uop_lrs3; // @[lsu.scala:209:16] reg stq_3_bits_uop_ldst_val; // @[lsu.scala:209:16] reg [1:0] stq_3_bits_uop_dst_rtype; // @[lsu.scala:209:16] reg [1:0] stq_3_bits_uop_lrs1_rtype; // @[lsu.scala:209:16] reg [1:0] stq_3_bits_uop_lrs2_rtype; // @[lsu.scala:209:16] reg stq_3_bits_uop_frs3_en; // @[lsu.scala:209:16] reg stq_3_bits_uop_fp_val; // @[lsu.scala:209:16] reg stq_3_bits_uop_fp_single; // @[lsu.scala:209:16] reg stq_3_bits_uop_xcpt_pf_if; // @[lsu.scala:209:16] reg stq_3_bits_uop_xcpt_ae_if; // @[lsu.scala:209:16] reg stq_3_bits_uop_xcpt_ma_if; // @[lsu.scala:209:16] reg stq_3_bits_uop_bp_debug_if; // @[lsu.scala:209:16] reg stq_3_bits_uop_bp_xcpt_if; // @[lsu.scala:209:16] reg [1:0] stq_3_bits_uop_debug_fsrc; // @[lsu.scala:209:16] reg [1:0] stq_3_bits_uop_debug_tsrc; // @[lsu.scala:209:16] reg stq_3_bits_addr_valid; // @[lsu.scala:209:16] reg [39:0] stq_3_bits_addr_bits; // @[lsu.scala:209:16] reg stq_3_bits_addr_is_virtual; // @[lsu.scala:209:16] reg stq_3_bits_data_valid; // @[lsu.scala:209:16] reg [63:0] stq_3_bits_data_bits; // @[lsu.scala:209:16] reg stq_3_bits_committed; // @[lsu.scala:209:16] reg stq_3_bits_succeeded; // @[lsu.scala:209:16] reg [63:0] stq_3_bits_debug_wb_data; // @[lsu.scala:209:16] reg stq_4_valid; // @[lsu.scala:209:16] reg [6:0] stq_4_bits_uop_uopc; // @[lsu.scala:209:16] reg [31:0] stq_4_bits_uop_inst; // @[lsu.scala:209:16] reg [31:0] stq_4_bits_uop_debug_inst; // @[lsu.scala:209:16] reg stq_4_bits_uop_is_rvc; // @[lsu.scala:209:16] reg [39:0] stq_4_bits_uop_debug_pc; // @[lsu.scala:209:16] reg [2:0] stq_4_bits_uop_iq_type; // @[lsu.scala:209:16] reg [9:0] stq_4_bits_uop_fu_code; // @[lsu.scala:209:16] reg [3:0] stq_4_bits_uop_ctrl_br_type; // @[lsu.scala:209:16] reg [1:0] stq_4_bits_uop_ctrl_op1_sel; // @[lsu.scala:209:16] reg [2:0] stq_4_bits_uop_ctrl_op2_sel; // @[lsu.scala:209:16] reg [2:0] stq_4_bits_uop_ctrl_imm_sel; // @[lsu.scala:209:16] reg [4:0] stq_4_bits_uop_ctrl_op_fcn; // @[lsu.scala:209:16] reg stq_4_bits_uop_ctrl_fcn_dw; // @[lsu.scala:209:16] reg [2:0] stq_4_bits_uop_ctrl_csr_cmd; // @[lsu.scala:209:16] reg stq_4_bits_uop_ctrl_is_load; // @[lsu.scala:209:16] reg stq_4_bits_uop_ctrl_is_sta; // @[lsu.scala:209:16] reg stq_4_bits_uop_ctrl_is_std; // @[lsu.scala:209:16] reg [1:0] stq_4_bits_uop_iw_state; // @[lsu.scala:209:16] reg stq_4_bits_uop_iw_p1_poisoned; // @[lsu.scala:209:16] reg stq_4_bits_uop_iw_p2_poisoned; // @[lsu.scala:209:16] reg stq_4_bits_uop_is_br; // @[lsu.scala:209:16] reg stq_4_bits_uop_is_jalr; // @[lsu.scala:209:16] reg stq_4_bits_uop_is_jal; // @[lsu.scala:209:16] reg stq_4_bits_uop_is_sfb; // @[lsu.scala:209:16] reg [7:0] stq_4_bits_uop_br_mask; // @[lsu.scala:209:16] reg [2:0] stq_4_bits_uop_br_tag; // @[lsu.scala:209:16] reg [3:0] stq_4_bits_uop_ftq_idx; // @[lsu.scala:209:16] reg stq_4_bits_uop_edge_inst; // @[lsu.scala:209:16] reg [5:0] stq_4_bits_uop_pc_lob; // @[lsu.scala:209:16] reg stq_4_bits_uop_taken; // @[lsu.scala:209:16] reg [19:0] stq_4_bits_uop_imm_packed; // @[lsu.scala:209:16] reg [11:0] stq_4_bits_uop_csr_addr; // @[lsu.scala:209:16] reg [4:0] stq_4_bits_uop_rob_idx; // @[lsu.scala:209:16] reg [2:0] stq_4_bits_uop_ldq_idx; // @[lsu.scala:209:16] reg [2:0] stq_4_bits_uop_stq_idx; // @[lsu.scala:209:16] reg [1:0] stq_4_bits_uop_rxq_idx; // @[lsu.scala:209:16] reg [5:0] stq_4_bits_uop_pdst; // @[lsu.scala:209:16] reg [5:0] stq_4_bits_uop_prs1; // @[lsu.scala:209:16] reg [5:0] stq_4_bits_uop_prs2; // @[lsu.scala:209:16] reg [5:0] stq_4_bits_uop_prs3; // @[lsu.scala:209:16] reg [3:0] stq_4_bits_uop_ppred; // @[lsu.scala:209:16] reg stq_4_bits_uop_prs1_busy; // @[lsu.scala:209:16] reg stq_4_bits_uop_prs2_busy; // @[lsu.scala:209:16] reg stq_4_bits_uop_prs3_busy; // @[lsu.scala:209:16] reg stq_4_bits_uop_ppred_busy; // @[lsu.scala:209:16] reg [5:0] stq_4_bits_uop_stale_pdst; // @[lsu.scala:209:16] reg stq_4_bits_uop_exception; // @[lsu.scala:209:16] reg [63:0] stq_4_bits_uop_exc_cause; // @[lsu.scala:209:16] reg stq_4_bits_uop_bypassable; // @[lsu.scala:209:16] reg [4:0] stq_4_bits_uop_mem_cmd; // @[lsu.scala:209:16] reg [1:0] stq_4_bits_uop_mem_size; // @[lsu.scala:209:16] reg stq_4_bits_uop_mem_signed; // @[lsu.scala:209:16] reg stq_4_bits_uop_is_fence; // @[lsu.scala:209:16] reg stq_4_bits_uop_is_fencei; // @[lsu.scala:209:16] reg stq_4_bits_uop_is_amo; // @[lsu.scala:209:16] reg stq_4_bits_uop_uses_ldq; // @[lsu.scala:209:16] reg stq_4_bits_uop_uses_stq; // @[lsu.scala:209:16] reg stq_4_bits_uop_is_sys_pc2epc; // @[lsu.scala:209:16] reg stq_4_bits_uop_is_unique; // @[lsu.scala:209:16] reg stq_4_bits_uop_flush_on_commit; // @[lsu.scala:209:16] reg stq_4_bits_uop_ldst_is_rs1; // @[lsu.scala:209:16] reg [5:0] stq_4_bits_uop_ldst; // @[lsu.scala:209:16] reg [5:0] stq_4_bits_uop_lrs1; // @[lsu.scala:209:16] reg [5:0] stq_4_bits_uop_lrs2; // @[lsu.scala:209:16] reg [5:0] stq_4_bits_uop_lrs3; // @[lsu.scala:209:16] reg stq_4_bits_uop_ldst_val; // @[lsu.scala:209:16] reg [1:0] stq_4_bits_uop_dst_rtype; // @[lsu.scala:209:16] reg [1:0] stq_4_bits_uop_lrs1_rtype; // @[lsu.scala:209:16] reg [1:0] stq_4_bits_uop_lrs2_rtype; // @[lsu.scala:209:16] reg stq_4_bits_uop_frs3_en; // @[lsu.scala:209:16] reg stq_4_bits_uop_fp_val; // @[lsu.scala:209:16] reg stq_4_bits_uop_fp_single; // @[lsu.scala:209:16] reg stq_4_bits_uop_xcpt_pf_if; // @[lsu.scala:209:16] reg stq_4_bits_uop_xcpt_ae_if; // @[lsu.scala:209:16] reg stq_4_bits_uop_xcpt_ma_if; // @[lsu.scala:209:16] reg stq_4_bits_uop_bp_debug_if; // @[lsu.scala:209:16] reg stq_4_bits_uop_bp_xcpt_if; // @[lsu.scala:209:16] reg [1:0] stq_4_bits_uop_debug_fsrc; // @[lsu.scala:209:16] reg [1:0] stq_4_bits_uop_debug_tsrc; // @[lsu.scala:209:16] reg stq_4_bits_addr_valid; // @[lsu.scala:209:16] reg [39:0] stq_4_bits_addr_bits; // @[lsu.scala:209:16] reg stq_4_bits_addr_is_virtual; // @[lsu.scala:209:16] reg stq_4_bits_data_valid; // @[lsu.scala:209:16] reg [63:0] stq_4_bits_data_bits; // @[lsu.scala:209:16] reg stq_4_bits_committed; // @[lsu.scala:209:16] reg stq_4_bits_succeeded; // @[lsu.scala:209:16] reg [63:0] stq_4_bits_debug_wb_data; // @[lsu.scala:209:16] reg stq_5_valid; // @[lsu.scala:209:16] reg [6:0] stq_5_bits_uop_uopc; // @[lsu.scala:209:16] reg [31:0] stq_5_bits_uop_inst; // @[lsu.scala:209:16] reg [31:0] stq_5_bits_uop_debug_inst; // @[lsu.scala:209:16] reg stq_5_bits_uop_is_rvc; // @[lsu.scala:209:16] reg [39:0] stq_5_bits_uop_debug_pc; // @[lsu.scala:209:16] reg [2:0] stq_5_bits_uop_iq_type; // @[lsu.scala:209:16] reg [9:0] stq_5_bits_uop_fu_code; // @[lsu.scala:209:16] reg [3:0] stq_5_bits_uop_ctrl_br_type; // @[lsu.scala:209:16] reg [1:0] stq_5_bits_uop_ctrl_op1_sel; // @[lsu.scala:209:16] reg [2:0] stq_5_bits_uop_ctrl_op2_sel; // @[lsu.scala:209:16] reg [2:0] stq_5_bits_uop_ctrl_imm_sel; // @[lsu.scala:209:16] reg [4:0] stq_5_bits_uop_ctrl_op_fcn; // @[lsu.scala:209:16] reg stq_5_bits_uop_ctrl_fcn_dw; // @[lsu.scala:209:16] reg [2:0] stq_5_bits_uop_ctrl_csr_cmd; // @[lsu.scala:209:16] reg stq_5_bits_uop_ctrl_is_load; // @[lsu.scala:209:16] reg stq_5_bits_uop_ctrl_is_sta; // @[lsu.scala:209:16] reg stq_5_bits_uop_ctrl_is_std; // @[lsu.scala:209:16] reg [1:0] stq_5_bits_uop_iw_state; // @[lsu.scala:209:16] reg stq_5_bits_uop_iw_p1_poisoned; // @[lsu.scala:209:16] reg stq_5_bits_uop_iw_p2_poisoned; // @[lsu.scala:209:16] reg stq_5_bits_uop_is_br; // @[lsu.scala:209:16] reg stq_5_bits_uop_is_jalr; // @[lsu.scala:209:16] reg stq_5_bits_uop_is_jal; // @[lsu.scala:209:16] reg stq_5_bits_uop_is_sfb; // @[lsu.scala:209:16] reg [7:0] stq_5_bits_uop_br_mask; // @[lsu.scala:209:16] reg [2:0] stq_5_bits_uop_br_tag; // @[lsu.scala:209:16] reg [3:0] stq_5_bits_uop_ftq_idx; // @[lsu.scala:209:16] reg stq_5_bits_uop_edge_inst; // @[lsu.scala:209:16] reg [5:0] stq_5_bits_uop_pc_lob; // @[lsu.scala:209:16] reg stq_5_bits_uop_taken; // @[lsu.scala:209:16] reg [19:0] stq_5_bits_uop_imm_packed; // @[lsu.scala:209:16] reg [11:0] stq_5_bits_uop_csr_addr; // @[lsu.scala:209:16] reg [4:0] stq_5_bits_uop_rob_idx; // @[lsu.scala:209:16] reg [2:0] stq_5_bits_uop_ldq_idx; // @[lsu.scala:209:16] reg [2:0] stq_5_bits_uop_stq_idx; // @[lsu.scala:209:16] reg [1:0] stq_5_bits_uop_rxq_idx; // @[lsu.scala:209:16] reg [5:0] stq_5_bits_uop_pdst; // @[lsu.scala:209:16] reg [5:0] stq_5_bits_uop_prs1; // @[lsu.scala:209:16] reg [5:0] stq_5_bits_uop_prs2; // @[lsu.scala:209:16] reg [5:0] stq_5_bits_uop_prs3; // @[lsu.scala:209:16] reg [3:0] stq_5_bits_uop_ppred; // @[lsu.scala:209:16] reg stq_5_bits_uop_prs1_busy; // @[lsu.scala:209:16] reg stq_5_bits_uop_prs2_busy; // @[lsu.scala:209:16] reg stq_5_bits_uop_prs3_busy; // @[lsu.scala:209:16] reg stq_5_bits_uop_ppred_busy; // @[lsu.scala:209:16] reg [5:0] stq_5_bits_uop_stale_pdst; // @[lsu.scala:209:16] reg stq_5_bits_uop_exception; // @[lsu.scala:209:16] reg [63:0] stq_5_bits_uop_exc_cause; // @[lsu.scala:209:16] reg stq_5_bits_uop_bypassable; // @[lsu.scala:209:16] reg [4:0] stq_5_bits_uop_mem_cmd; // @[lsu.scala:209:16] reg [1:0] stq_5_bits_uop_mem_size; // @[lsu.scala:209:16] reg stq_5_bits_uop_mem_signed; // @[lsu.scala:209:16] reg stq_5_bits_uop_is_fence; // @[lsu.scala:209:16] reg stq_5_bits_uop_is_fencei; // @[lsu.scala:209:16] reg stq_5_bits_uop_is_amo; // @[lsu.scala:209:16] reg stq_5_bits_uop_uses_ldq; // @[lsu.scala:209:16] reg stq_5_bits_uop_uses_stq; // @[lsu.scala:209:16] reg stq_5_bits_uop_is_sys_pc2epc; // @[lsu.scala:209:16] reg stq_5_bits_uop_is_unique; // @[lsu.scala:209:16] reg stq_5_bits_uop_flush_on_commit; // @[lsu.scala:209:16] reg stq_5_bits_uop_ldst_is_rs1; // @[lsu.scala:209:16] reg [5:0] stq_5_bits_uop_ldst; // @[lsu.scala:209:16] reg [5:0] stq_5_bits_uop_lrs1; // @[lsu.scala:209:16] reg [5:0] stq_5_bits_uop_lrs2; // @[lsu.scala:209:16] reg [5:0] stq_5_bits_uop_lrs3; // @[lsu.scala:209:16] reg stq_5_bits_uop_ldst_val; // @[lsu.scala:209:16] reg [1:0] stq_5_bits_uop_dst_rtype; // @[lsu.scala:209:16] reg [1:0] stq_5_bits_uop_lrs1_rtype; // @[lsu.scala:209:16] reg [1:0] stq_5_bits_uop_lrs2_rtype; // @[lsu.scala:209:16] reg stq_5_bits_uop_frs3_en; // @[lsu.scala:209:16] reg stq_5_bits_uop_fp_val; // @[lsu.scala:209:16] reg stq_5_bits_uop_fp_single; // @[lsu.scala:209:16] reg stq_5_bits_uop_xcpt_pf_if; // @[lsu.scala:209:16] reg stq_5_bits_uop_xcpt_ae_if; // @[lsu.scala:209:16] reg stq_5_bits_uop_xcpt_ma_if; // @[lsu.scala:209:16] reg stq_5_bits_uop_bp_debug_if; // @[lsu.scala:209:16] reg stq_5_bits_uop_bp_xcpt_if; // @[lsu.scala:209:16] reg [1:0] stq_5_bits_uop_debug_fsrc; // @[lsu.scala:209:16] reg [1:0] stq_5_bits_uop_debug_tsrc; // @[lsu.scala:209:16] reg stq_5_bits_addr_valid; // @[lsu.scala:209:16] reg [39:0] stq_5_bits_addr_bits; // @[lsu.scala:209:16] reg stq_5_bits_addr_is_virtual; // @[lsu.scala:209:16] reg stq_5_bits_data_valid; // @[lsu.scala:209:16] reg [63:0] stq_5_bits_data_bits; // @[lsu.scala:209:16] reg stq_5_bits_committed; // @[lsu.scala:209:16] reg stq_5_bits_succeeded; // @[lsu.scala:209:16] reg [63:0] stq_5_bits_debug_wb_data; // @[lsu.scala:209:16] reg stq_6_valid; // @[lsu.scala:209:16] reg [6:0] stq_6_bits_uop_uopc; // @[lsu.scala:209:16] reg [31:0] stq_6_bits_uop_inst; // @[lsu.scala:209:16] reg [31:0] stq_6_bits_uop_debug_inst; // @[lsu.scala:209:16] reg stq_6_bits_uop_is_rvc; // @[lsu.scala:209:16] reg [39:0] stq_6_bits_uop_debug_pc; // @[lsu.scala:209:16] reg [2:0] stq_6_bits_uop_iq_type; // @[lsu.scala:209:16] reg [9:0] stq_6_bits_uop_fu_code; // @[lsu.scala:209:16] reg [3:0] stq_6_bits_uop_ctrl_br_type; // @[lsu.scala:209:16] reg [1:0] stq_6_bits_uop_ctrl_op1_sel; // @[lsu.scala:209:16] reg [2:0] stq_6_bits_uop_ctrl_op2_sel; // @[lsu.scala:209:16] reg [2:0] stq_6_bits_uop_ctrl_imm_sel; // @[lsu.scala:209:16] reg [4:0] stq_6_bits_uop_ctrl_op_fcn; // @[lsu.scala:209:16] reg stq_6_bits_uop_ctrl_fcn_dw; // @[lsu.scala:209:16] reg [2:0] stq_6_bits_uop_ctrl_csr_cmd; // @[lsu.scala:209:16] reg stq_6_bits_uop_ctrl_is_load; // @[lsu.scala:209:16] reg stq_6_bits_uop_ctrl_is_sta; // @[lsu.scala:209:16] reg stq_6_bits_uop_ctrl_is_std; // @[lsu.scala:209:16] reg [1:0] stq_6_bits_uop_iw_state; // @[lsu.scala:209:16] reg stq_6_bits_uop_iw_p1_poisoned; // @[lsu.scala:209:16] reg stq_6_bits_uop_iw_p2_poisoned; // @[lsu.scala:209:16] reg stq_6_bits_uop_is_br; // @[lsu.scala:209:16] reg stq_6_bits_uop_is_jalr; // @[lsu.scala:209:16] reg stq_6_bits_uop_is_jal; // @[lsu.scala:209:16] reg stq_6_bits_uop_is_sfb; // @[lsu.scala:209:16] reg [7:0] stq_6_bits_uop_br_mask; // @[lsu.scala:209:16] reg [2:0] stq_6_bits_uop_br_tag; // @[lsu.scala:209:16] reg [3:0] stq_6_bits_uop_ftq_idx; // @[lsu.scala:209:16] reg stq_6_bits_uop_edge_inst; // @[lsu.scala:209:16] reg [5:0] stq_6_bits_uop_pc_lob; // @[lsu.scala:209:16] reg stq_6_bits_uop_taken; // @[lsu.scala:209:16] reg [19:0] stq_6_bits_uop_imm_packed; // @[lsu.scala:209:16] reg [11:0] stq_6_bits_uop_csr_addr; // @[lsu.scala:209:16] reg [4:0] stq_6_bits_uop_rob_idx; // @[lsu.scala:209:16] reg [2:0] stq_6_bits_uop_ldq_idx; // @[lsu.scala:209:16] reg [2:0] stq_6_bits_uop_stq_idx; // @[lsu.scala:209:16] reg [1:0] stq_6_bits_uop_rxq_idx; // @[lsu.scala:209:16] reg [5:0] stq_6_bits_uop_pdst; // @[lsu.scala:209:16] reg [5:0] stq_6_bits_uop_prs1; // @[lsu.scala:209:16] reg [5:0] stq_6_bits_uop_prs2; // @[lsu.scala:209:16] reg [5:0] stq_6_bits_uop_prs3; // @[lsu.scala:209:16] reg [3:0] stq_6_bits_uop_ppred; // @[lsu.scala:209:16] reg stq_6_bits_uop_prs1_busy; // @[lsu.scala:209:16] reg stq_6_bits_uop_prs2_busy; // @[lsu.scala:209:16] reg stq_6_bits_uop_prs3_busy; // @[lsu.scala:209:16] reg stq_6_bits_uop_ppred_busy; // @[lsu.scala:209:16] reg [5:0] stq_6_bits_uop_stale_pdst; // @[lsu.scala:209:16] reg stq_6_bits_uop_exception; // @[lsu.scala:209:16] reg [63:0] stq_6_bits_uop_exc_cause; // @[lsu.scala:209:16] reg stq_6_bits_uop_bypassable; // @[lsu.scala:209:16] reg [4:0] stq_6_bits_uop_mem_cmd; // @[lsu.scala:209:16] reg [1:0] stq_6_bits_uop_mem_size; // @[lsu.scala:209:16] reg stq_6_bits_uop_mem_signed; // @[lsu.scala:209:16] reg stq_6_bits_uop_is_fence; // @[lsu.scala:209:16] reg stq_6_bits_uop_is_fencei; // @[lsu.scala:209:16] reg stq_6_bits_uop_is_amo; // @[lsu.scala:209:16] reg stq_6_bits_uop_uses_ldq; // @[lsu.scala:209:16] reg stq_6_bits_uop_uses_stq; // @[lsu.scala:209:16] reg stq_6_bits_uop_is_sys_pc2epc; // @[lsu.scala:209:16] reg stq_6_bits_uop_is_unique; // @[lsu.scala:209:16] reg stq_6_bits_uop_flush_on_commit; // @[lsu.scala:209:16] reg stq_6_bits_uop_ldst_is_rs1; // @[lsu.scala:209:16] reg [5:0] stq_6_bits_uop_ldst; // @[lsu.scala:209:16] reg [5:0] stq_6_bits_uop_lrs1; // @[lsu.scala:209:16] reg [5:0] stq_6_bits_uop_lrs2; // @[lsu.scala:209:16] reg [5:0] stq_6_bits_uop_lrs3; // @[lsu.scala:209:16] reg stq_6_bits_uop_ldst_val; // @[lsu.scala:209:16] reg [1:0] stq_6_bits_uop_dst_rtype; // @[lsu.scala:209:16] reg [1:0] stq_6_bits_uop_lrs1_rtype; // @[lsu.scala:209:16] reg [1:0] stq_6_bits_uop_lrs2_rtype; // @[lsu.scala:209:16] reg stq_6_bits_uop_frs3_en; // @[lsu.scala:209:16] reg stq_6_bits_uop_fp_val; // @[lsu.scala:209:16] reg stq_6_bits_uop_fp_single; // @[lsu.scala:209:16] reg stq_6_bits_uop_xcpt_pf_if; // @[lsu.scala:209:16] reg stq_6_bits_uop_xcpt_ae_if; // @[lsu.scala:209:16] reg stq_6_bits_uop_xcpt_ma_if; // @[lsu.scala:209:16] reg stq_6_bits_uop_bp_debug_if; // @[lsu.scala:209:16] reg stq_6_bits_uop_bp_xcpt_if; // @[lsu.scala:209:16] reg [1:0] stq_6_bits_uop_debug_fsrc; // @[lsu.scala:209:16] reg [1:0] stq_6_bits_uop_debug_tsrc; // @[lsu.scala:209:16] reg stq_6_bits_addr_valid; // @[lsu.scala:209:16] reg [39:0] stq_6_bits_addr_bits; // @[lsu.scala:209:16] reg stq_6_bits_addr_is_virtual; // @[lsu.scala:209:16] reg stq_6_bits_data_valid; // @[lsu.scala:209:16] reg [63:0] stq_6_bits_data_bits; // @[lsu.scala:209:16] reg stq_6_bits_committed; // @[lsu.scala:209:16] reg stq_6_bits_succeeded; // @[lsu.scala:209:16] reg [63:0] stq_6_bits_debug_wb_data; // @[lsu.scala:209:16] reg stq_7_valid; // @[lsu.scala:209:16] reg [6:0] stq_7_bits_uop_uopc; // @[lsu.scala:209:16] reg [31:0] stq_7_bits_uop_inst; // @[lsu.scala:209:16] reg [31:0] stq_7_bits_uop_debug_inst; // @[lsu.scala:209:16] reg stq_7_bits_uop_is_rvc; // @[lsu.scala:209:16] reg [39:0] stq_7_bits_uop_debug_pc; // @[lsu.scala:209:16] reg [2:0] stq_7_bits_uop_iq_type; // @[lsu.scala:209:16] reg [9:0] stq_7_bits_uop_fu_code; // @[lsu.scala:209:16] reg [3:0] stq_7_bits_uop_ctrl_br_type; // @[lsu.scala:209:16] reg [1:0] stq_7_bits_uop_ctrl_op1_sel; // @[lsu.scala:209:16] reg [2:0] stq_7_bits_uop_ctrl_op2_sel; // @[lsu.scala:209:16] reg [2:0] stq_7_bits_uop_ctrl_imm_sel; // @[lsu.scala:209:16] reg [4:0] stq_7_bits_uop_ctrl_op_fcn; // @[lsu.scala:209:16] reg stq_7_bits_uop_ctrl_fcn_dw; // @[lsu.scala:209:16] reg [2:0] stq_7_bits_uop_ctrl_csr_cmd; // @[lsu.scala:209:16] reg stq_7_bits_uop_ctrl_is_load; // @[lsu.scala:209:16] reg stq_7_bits_uop_ctrl_is_sta; // @[lsu.scala:209:16] reg stq_7_bits_uop_ctrl_is_std; // @[lsu.scala:209:16] reg [1:0] stq_7_bits_uop_iw_state; // @[lsu.scala:209:16] reg stq_7_bits_uop_iw_p1_poisoned; // @[lsu.scala:209:16] reg stq_7_bits_uop_iw_p2_poisoned; // @[lsu.scala:209:16] reg stq_7_bits_uop_is_br; // @[lsu.scala:209:16] reg stq_7_bits_uop_is_jalr; // @[lsu.scala:209:16] reg stq_7_bits_uop_is_jal; // @[lsu.scala:209:16] reg stq_7_bits_uop_is_sfb; // @[lsu.scala:209:16] reg [7:0] stq_7_bits_uop_br_mask; // @[lsu.scala:209:16] reg [2:0] stq_7_bits_uop_br_tag; // @[lsu.scala:209:16] reg [3:0] stq_7_bits_uop_ftq_idx; // @[lsu.scala:209:16] reg stq_7_bits_uop_edge_inst; // @[lsu.scala:209:16] reg [5:0] stq_7_bits_uop_pc_lob; // @[lsu.scala:209:16] reg stq_7_bits_uop_taken; // @[lsu.scala:209:16] reg [19:0] stq_7_bits_uop_imm_packed; // @[lsu.scala:209:16] reg [11:0] stq_7_bits_uop_csr_addr; // @[lsu.scala:209:16] reg [4:0] stq_7_bits_uop_rob_idx; // @[lsu.scala:209:16] reg [2:0] stq_7_bits_uop_ldq_idx; // @[lsu.scala:209:16] reg [2:0] stq_7_bits_uop_stq_idx; // @[lsu.scala:209:16] reg [1:0] stq_7_bits_uop_rxq_idx; // @[lsu.scala:209:16] reg [5:0] stq_7_bits_uop_pdst; // @[lsu.scala:209:16] reg [5:0] stq_7_bits_uop_prs1; // @[lsu.scala:209:16] reg [5:0] stq_7_bits_uop_prs2; // @[lsu.scala:209:16] reg [5:0] stq_7_bits_uop_prs3; // @[lsu.scala:209:16] reg [3:0] stq_7_bits_uop_ppred; // @[lsu.scala:209:16] reg stq_7_bits_uop_prs1_busy; // @[lsu.scala:209:16] reg stq_7_bits_uop_prs2_busy; // @[lsu.scala:209:16] reg stq_7_bits_uop_prs3_busy; // @[lsu.scala:209:16] reg stq_7_bits_uop_ppred_busy; // @[lsu.scala:209:16] reg [5:0] stq_7_bits_uop_stale_pdst; // @[lsu.scala:209:16] reg stq_7_bits_uop_exception; // @[lsu.scala:209:16] reg [63:0] stq_7_bits_uop_exc_cause; // @[lsu.scala:209:16] reg stq_7_bits_uop_bypassable; // @[lsu.scala:209:16] reg [4:0] stq_7_bits_uop_mem_cmd; // @[lsu.scala:209:16] reg [1:0] stq_7_bits_uop_mem_size; // @[lsu.scala:209:16] reg stq_7_bits_uop_mem_signed; // @[lsu.scala:209:16] reg stq_7_bits_uop_is_fence; // @[lsu.scala:209:16] reg stq_7_bits_uop_is_fencei; // @[lsu.scala:209:16] reg stq_7_bits_uop_is_amo; // @[lsu.scala:209:16] reg stq_7_bits_uop_uses_ldq; // @[lsu.scala:209:16] reg stq_7_bits_uop_uses_stq; // @[lsu.scala:209:16] reg stq_7_bits_uop_is_sys_pc2epc; // @[lsu.scala:209:16] reg stq_7_bits_uop_is_unique; // @[lsu.scala:209:16] reg stq_7_bits_uop_flush_on_commit; // @[lsu.scala:209:16] reg stq_7_bits_uop_ldst_is_rs1; // @[lsu.scala:209:16] reg [5:0] stq_7_bits_uop_ldst; // @[lsu.scala:209:16] reg [5:0] stq_7_bits_uop_lrs1; // @[lsu.scala:209:16] reg [5:0] stq_7_bits_uop_lrs2; // @[lsu.scala:209:16] reg [5:0] stq_7_bits_uop_lrs3; // @[lsu.scala:209:16] reg stq_7_bits_uop_ldst_val; // @[lsu.scala:209:16] reg [1:0] stq_7_bits_uop_dst_rtype; // @[lsu.scala:209:16] reg [1:0] stq_7_bits_uop_lrs1_rtype; // @[lsu.scala:209:16] reg [1:0] stq_7_bits_uop_lrs2_rtype; // @[lsu.scala:209:16] reg stq_7_bits_uop_frs3_en; // @[lsu.scala:209:16] reg stq_7_bits_uop_fp_val; // @[lsu.scala:209:16] reg stq_7_bits_uop_fp_single; // @[lsu.scala:209:16] reg stq_7_bits_uop_xcpt_pf_if; // @[lsu.scala:209:16] reg stq_7_bits_uop_xcpt_ae_if; // @[lsu.scala:209:16] reg stq_7_bits_uop_xcpt_ma_if; // @[lsu.scala:209:16] reg stq_7_bits_uop_bp_debug_if; // @[lsu.scala:209:16] reg stq_7_bits_uop_bp_xcpt_if; // @[lsu.scala:209:16] reg [1:0] stq_7_bits_uop_debug_fsrc; // @[lsu.scala:209:16] reg [1:0] stq_7_bits_uop_debug_tsrc; // @[lsu.scala:209:16] reg stq_7_bits_addr_valid; // @[lsu.scala:209:16] reg [39:0] stq_7_bits_addr_bits; // @[lsu.scala:209:16] reg stq_7_bits_addr_is_virtual; // @[lsu.scala:209:16] reg stq_7_bits_data_valid; // @[lsu.scala:209:16] reg [63:0] stq_7_bits_data_bits; // @[lsu.scala:209:16] reg stq_7_bits_committed; // @[lsu.scala:209:16] reg stq_7_bits_succeeded; // @[lsu.scala:209:16] reg [63:0] stq_7_bits_debug_wb_data; // @[lsu.scala:209:16] reg [2:0] ldq_head; // @[lsu.scala:213:29] reg [2:0] ldq_tail; // @[lsu.scala:214:29] assign io_core_dis_ldq_idx_0_0 = ldq_tail; // @[lsu.scala:201:7, :214:29] reg [2:0] stq_head; // @[lsu.scala:215:29] reg [2:0] stq_tail; // @[lsu.scala:216:29] assign io_core_dis_stq_idx_0_0 = stq_tail; // @[lsu.scala:201:7, :216:29] reg [2:0] stq_commit_head; // @[lsu.scala:217:29] reg [2:0] stq_execute_head; // @[lsu.scala:218:29] wire [7:0] _GEN = {{stq_7_valid}, {stq_6_valid}, {stq_5_valid}, {stq_4_valid}, {stq_3_valid}, {stq_2_valid}, {stq_1_valid}, {stq_0_valid}}; // @[lsu.scala:209:16, :222:42] wire _GEN_0 = _GEN[stq_execute_head]; // @[lsu.scala:218:29, :222:42] wire [7:0][6:0] _GEN_1 = {{stq_7_bits_uop_uopc}, {stq_6_bits_uop_uopc}, {stq_5_bits_uop_uopc}, {stq_4_bits_uop_uopc}, {stq_3_bits_uop_uopc}, {stq_2_bits_uop_uopc}, {stq_1_bits_uop_uopc}, {stq_0_bits_uop_uopc}}; // @[lsu.scala:209:16, :222:42] wire [7:0][31:0] _GEN_2 = {{stq_7_bits_uop_inst}, {stq_6_bits_uop_inst}, {stq_5_bits_uop_inst}, {stq_4_bits_uop_inst}, {stq_3_bits_uop_inst}, {stq_2_bits_uop_inst}, {stq_1_bits_uop_inst}, {stq_0_bits_uop_inst}}; // @[lsu.scala:209:16, :222:42] wire [7:0][31:0] _GEN_3 = {{stq_7_bits_uop_debug_inst}, {stq_6_bits_uop_debug_inst}, {stq_5_bits_uop_debug_inst}, {stq_4_bits_uop_debug_inst}, {stq_3_bits_uop_debug_inst}, {stq_2_bits_uop_debug_inst}, {stq_1_bits_uop_debug_inst}, {stq_0_bits_uop_debug_inst}}; // @[lsu.scala:209:16, :222:42] wire [7:0] _GEN_4 = {{stq_7_bits_uop_is_rvc}, {stq_6_bits_uop_is_rvc}, {stq_5_bits_uop_is_rvc}, {stq_4_bits_uop_is_rvc}, {stq_3_bits_uop_is_rvc}, {stq_2_bits_uop_is_rvc}, {stq_1_bits_uop_is_rvc}, {stq_0_bits_uop_is_rvc}}; // @[lsu.scala:209:16, :222:42] wire [7:0][39:0] _GEN_5 = {{stq_7_bits_uop_debug_pc}, {stq_6_bits_uop_debug_pc}, {stq_5_bits_uop_debug_pc}, {stq_4_bits_uop_debug_pc}, {stq_3_bits_uop_debug_pc}, {stq_2_bits_uop_debug_pc}, {stq_1_bits_uop_debug_pc}, {stq_0_bits_uop_debug_pc}}; // @[lsu.scala:209:16, :222:42] wire [7:0][2:0] _GEN_6 = {{stq_7_bits_uop_iq_type}, {stq_6_bits_uop_iq_type}, {stq_5_bits_uop_iq_type}, {stq_4_bits_uop_iq_type}, {stq_3_bits_uop_iq_type}, {stq_2_bits_uop_iq_type}, {stq_1_bits_uop_iq_type}, {stq_0_bits_uop_iq_type}}; // @[lsu.scala:209:16, :222:42] wire [7:0][9:0] _GEN_7 = {{stq_7_bits_uop_fu_code}, {stq_6_bits_uop_fu_code}, {stq_5_bits_uop_fu_code}, {stq_4_bits_uop_fu_code}, {stq_3_bits_uop_fu_code}, {stq_2_bits_uop_fu_code}, {stq_1_bits_uop_fu_code}, {stq_0_bits_uop_fu_code}}; // @[lsu.scala:209:16, :222:42] wire [7:0][3:0] _GEN_8 = {{stq_7_bits_uop_ctrl_br_type}, {stq_6_bits_uop_ctrl_br_type}, {stq_5_bits_uop_ctrl_br_type}, {stq_4_bits_uop_ctrl_br_type}, {stq_3_bits_uop_ctrl_br_type}, {stq_2_bits_uop_ctrl_br_type}, {stq_1_bits_uop_ctrl_br_type}, {stq_0_bits_uop_ctrl_br_type}}; // @[lsu.scala:209:16, :222:42] wire [7:0][1:0] _GEN_9 = {{stq_7_bits_uop_ctrl_op1_sel}, {stq_6_bits_uop_ctrl_op1_sel}, {stq_5_bits_uop_ctrl_op1_sel}, {stq_4_bits_uop_ctrl_op1_sel}, {stq_3_bits_uop_ctrl_op1_sel}, {stq_2_bits_uop_ctrl_op1_sel}, {stq_1_bits_uop_ctrl_op1_sel}, {stq_0_bits_uop_ctrl_op1_sel}}; // @[lsu.scala:209:16, :222:42] wire [7:0][2:0] _GEN_10 = {{stq_7_bits_uop_ctrl_op2_sel}, {stq_6_bits_uop_ctrl_op2_sel}, {stq_5_bits_uop_ctrl_op2_sel}, {stq_4_bits_uop_ctrl_op2_sel}, {stq_3_bits_uop_ctrl_op2_sel}, {stq_2_bits_uop_ctrl_op2_sel}, {stq_1_bits_uop_ctrl_op2_sel}, {stq_0_bits_uop_ctrl_op2_sel}}; // @[lsu.scala:209:16, :222:42] wire [7:0][2:0] _GEN_11 = {{stq_7_bits_uop_ctrl_imm_sel}, {stq_6_bits_uop_ctrl_imm_sel}, {stq_5_bits_uop_ctrl_imm_sel}, {stq_4_bits_uop_ctrl_imm_sel}, {stq_3_bits_uop_ctrl_imm_sel}, {stq_2_bits_uop_ctrl_imm_sel}, {stq_1_bits_uop_ctrl_imm_sel}, {stq_0_bits_uop_ctrl_imm_sel}}; // @[lsu.scala:209:16, :222:42] wire [7:0][4:0] _GEN_12 = {{stq_7_bits_uop_ctrl_op_fcn}, {stq_6_bits_uop_ctrl_op_fcn}, {stq_5_bits_uop_ctrl_op_fcn}, {stq_4_bits_uop_ctrl_op_fcn}, {stq_3_bits_uop_ctrl_op_fcn}, {stq_2_bits_uop_ctrl_op_fcn}, {stq_1_bits_uop_ctrl_op_fcn}, {stq_0_bits_uop_ctrl_op_fcn}}; // @[lsu.scala:209:16, :222:42] wire [7:0] _GEN_13 = {{stq_7_bits_uop_ctrl_fcn_dw}, {stq_6_bits_uop_ctrl_fcn_dw}, {stq_5_bits_uop_ctrl_fcn_dw}, {stq_4_bits_uop_ctrl_fcn_dw}, {stq_3_bits_uop_ctrl_fcn_dw}, {stq_2_bits_uop_ctrl_fcn_dw}, {stq_1_bits_uop_ctrl_fcn_dw}, {stq_0_bits_uop_ctrl_fcn_dw}}; // @[lsu.scala:209:16, :222:42] wire [7:0][2:0] _GEN_14 = {{stq_7_bits_uop_ctrl_csr_cmd}, {stq_6_bits_uop_ctrl_csr_cmd}, {stq_5_bits_uop_ctrl_csr_cmd}, {stq_4_bits_uop_ctrl_csr_cmd}, {stq_3_bits_uop_ctrl_csr_cmd}, {stq_2_bits_uop_ctrl_csr_cmd}, {stq_1_bits_uop_ctrl_csr_cmd}, {stq_0_bits_uop_ctrl_csr_cmd}}; // @[lsu.scala:209:16, :222:42] wire [7:0] _GEN_15 = {{stq_7_bits_uop_ctrl_is_load}, {stq_6_bits_uop_ctrl_is_load}, {stq_5_bits_uop_ctrl_is_load}, {stq_4_bits_uop_ctrl_is_load}, {stq_3_bits_uop_ctrl_is_load}, {stq_2_bits_uop_ctrl_is_load}, {stq_1_bits_uop_ctrl_is_load}, {stq_0_bits_uop_ctrl_is_load}}; // @[lsu.scala:209:16, :222:42] wire [7:0] _GEN_16 = {{stq_7_bits_uop_ctrl_is_sta}, {stq_6_bits_uop_ctrl_is_sta}, {stq_5_bits_uop_ctrl_is_sta}, {stq_4_bits_uop_ctrl_is_sta}, {stq_3_bits_uop_ctrl_is_sta}, {stq_2_bits_uop_ctrl_is_sta}, {stq_1_bits_uop_ctrl_is_sta}, {stq_0_bits_uop_ctrl_is_sta}}; // @[lsu.scala:209:16, :222:42] wire [7:0] _GEN_17 = {{stq_7_bits_uop_ctrl_is_std}, {stq_6_bits_uop_ctrl_is_std}, {stq_5_bits_uop_ctrl_is_std}, {stq_4_bits_uop_ctrl_is_std}, {stq_3_bits_uop_ctrl_is_std}, {stq_2_bits_uop_ctrl_is_std}, {stq_1_bits_uop_ctrl_is_std}, {stq_0_bits_uop_ctrl_is_std}}; // @[lsu.scala:209:16, :222:42] wire [7:0][1:0] _GEN_18 = {{stq_7_bits_uop_iw_state}, {stq_6_bits_uop_iw_state}, {stq_5_bits_uop_iw_state}, {stq_4_bits_uop_iw_state}, {stq_3_bits_uop_iw_state}, {stq_2_bits_uop_iw_state}, {stq_1_bits_uop_iw_state}, {stq_0_bits_uop_iw_state}}; // @[lsu.scala:209:16, :222:42] wire [7:0] _GEN_19 = {{stq_7_bits_uop_iw_p1_poisoned}, {stq_6_bits_uop_iw_p1_poisoned}, {stq_5_bits_uop_iw_p1_poisoned}, {stq_4_bits_uop_iw_p1_poisoned}, {stq_3_bits_uop_iw_p1_poisoned}, {stq_2_bits_uop_iw_p1_poisoned}, {stq_1_bits_uop_iw_p1_poisoned}, {stq_0_bits_uop_iw_p1_poisoned}}; // @[lsu.scala:209:16, :222:42] wire [7:0] _GEN_20 = {{stq_7_bits_uop_iw_p2_poisoned}, {stq_6_bits_uop_iw_p2_poisoned}, {stq_5_bits_uop_iw_p2_poisoned}, {stq_4_bits_uop_iw_p2_poisoned}, {stq_3_bits_uop_iw_p2_poisoned}, {stq_2_bits_uop_iw_p2_poisoned}, {stq_1_bits_uop_iw_p2_poisoned}, {stq_0_bits_uop_iw_p2_poisoned}}; // @[lsu.scala:209:16, :222:42] wire [7:0] _GEN_21 = {{stq_7_bits_uop_is_br}, {stq_6_bits_uop_is_br}, {stq_5_bits_uop_is_br}, {stq_4_bits_uop_is_br}, {stq_3_bits_uop_is_br}, {stq_2_bits_uop_is_br}, {stq_1_bits_uop_is_br}, {stq_0_bits_uop_is_br}}; // @[lsu.scala:209:16, :222:42] wire [7:0] _GEN_22 = {{stq_7_bits_uop_is_jalr}, {stq_6_bits_uop_is_jalr}, {stq_5_bits_uop_is_jalr}, {stq_4_bits_uop_is_jalr}, {stq_3_bits_uop_is_jalr}, {stq_2_bits_uop_is_jalr}, {stq_1_bits_uop_is_jalr}, {stq_0_bits_uop_is_jalr}}; // @[lsu.scala:209:16, :222:42] wire [7:0] _GEN_23 = {{stq_7_bits_uop_is_jal}, {stq_6_bits_uop_is_jal}, {stq_5_bits_uop_is_jal}, {stq_4_bits_uop_is_jal}, {stq_3_bits_uop_is_jal}, {stq_2_bits_uop_is_jal}, {stq_1_bits_uop_is_jal}, {stq_0_bits_uop_is_jal}}; // @[lsu.scala:209:16, :222:42] wire [7:0] _GEN_24 = {{stq_7_bits_uop_is_sfb}, {stq_6_bits_uop_is_sfb}, {stq_5_bits_uop_is_sfb}, {stq_4_bits_uop_is_sfb}, {stq_3_bits_uop_is_sfb}, {stq_2_bits_uop_is_sfb}, {stq_1_bits_uop_is_sfb}, {stq_0_bits_uop_is_sfb}}; // @[lsu.scala:209:16, :222:42] wire [7:0][7:0] _GEN_25 = {{stq_7_bits_uop_br_mask}, {stq_6_bits_uop_br_mask}, {stq_5_bits_uop_br_mask}, {stq_4_bits_uop_br_mask}, {stq_3_bits_uop_br_mask}, {stq_2_bits_uop_br_mask}, {stq_1_bits_uop_br_mask}, {stq_0_bits_uop_br_mask}}; // @[lsu.scala:209:16, :222:42] wire [7:0][2:0] _GEN_26 = {{stq_7_bits_uop_br_tag}, {stq_6_bits_uop_br_tag}, {stq_5_bits_uop_br_tag}, {stq_4_bits_uop_br_tag}, {stq_3_bits_uop_br_tag}, {stq_2_bits_uop_br_tag}, {stq_1_bits_uop_br_tag}, {stq_0_bits_uop_br_tag}}; // @[lsu.scala:209:16, :222:42] wire [7:0][3:0] _GEN_27 = {{stq_7_bits_uop_ftq_idx}, {stq_6_bits_uop_ftq_idx}, {stq_5_bits_uop_ftq_idx}, {stq_4_bits_uop_ftq_idx}, {stq_3_bits_uop_ftq_idx}, {stq_2_bits_uop_ftq_idx}, {stq_1_bits_uop_ftq_idx}, {stq_0_bits_uop_ftq_idx}}; // @[lsu.scala:209:16, :222:42] wire [7:0] _GEN_28 = {{stq_7_bits_uop_edge_inst}, {stq_6_bits_uop_edge_inst}, {stq_5_bits_uop_edge_inst}, {stq_4_bits_uop_edge_inst}, {stq_3_bits_uop_edge_inst}, {stq_2_bits_uop_edge_inst}, {stq_1_bits_uop_edge_inst}, {stq_0_bits_uop_edge_inst}}; // @[lsu.scala:209:16, :222:42] wire [7:0][5:0] _GEN_29 = {{stq_7_bits_uop_pc_lob}, {stq_6_bits_uop_pc_lob}, {stq_5_bits_uop_pc_lob}, {stq_4_bits_uop_pc_lob}, {stq_3_bits_uop_pc_lob}, {stq_2_bits_uop_pc_lob}, {stq_1_bits_uop_pc_lob}, {stq_0_bits_uop_pc_lob}}; // @[lsu.scala:209:16, :222:42] wire [7:0] _GEN_30 = {{stq_7_bits_uop_taken}, {stq_6_bits_uop_taken}, {stq_5_bits_uop_taken}, {stq_4_bits_uop_taken}, {stq_3_bits_uop_taken}, {stq_2_bits_uop_taken}, {stq_1_bits_uop_taken}, {stq_0_bits_uop_taken}}; // @[lsu.scala:209:16, :222:42] wire [7:0][19:0] _GEN_31 = {{stq_7_bits_uop_imm_packed}, {stq_6_bits_uop_imm_packed}, {stq_5_bits_uop_imm_packed}, {stq_4_bits_uop_imm_packed}, {stq_3_bits_uop_imm_packed}, {stq_2_bits_uop_imm_packed}, {stq_1_bits_uop_imm_packed}, {stq_0_bits_uop_imm_packed}}; // @[lsu.scala:209:16, :222:42] wire [7:0][11:0] _GEN_32 = {{stq_7_bits_uop_csr_addr}, {stq_6_bits_uop_csr_addr}, {stq_5_bits_uop_csr_addr}, {stq_4_bits_uop_csr_addr}, {stq_3_bits_uop_csr_addr}, {stq_2_bits_uop_csr_addr}, {stq_1_bits_uop_csr_addr}, {stq_0_bits_uop_csr_addr}}; // @[lsu.scala:209:16, :222:42] wire [7:0][4:0] _GEN_33 = {{stq_7_bits_uop_rob_idx}, {stq_6_bits_uop_rob_idx}, {stq_5_bits_uop_rob_idx}, {stq_4_bits_uop_rob_idx}, {stq_3_bits_uop_rob_idx}, {stq_2_bits_uop_rob_idx}, {stq_1_bits_uop_rob_idx}, {stq_0_bits_uop_rob_idx}}; // @[lsu.scala:209:16, :222:42] wire [7:0][2:0] _GEN_34 = {{stq_7_bits_uop_ldq_idx}, {stq_6_bits_uop_ldq_idx}, {stq_5_bits_uop_ldq_idx}, {stq_4_bits_uop_ldq_idx}, {stq_3_bits_uop_ldq_idx}, {stq_2_bits_uop_ldq_idx}, {stq_1_bits_uop_ldq_idx}, {stq_0_bits_uop_ldq_idx}}; // @[lsu.scala:209:16, :222:42] wire [7:0][2:0] _GEN_35 = {{stq_7_bits_uop_stq_idx}, {stq_6_bits_uop_stq_idx}, {stq_5_bits_uop_stq_idx}, {stq_4_bits_uop_stq_idx}, {stq_3_bits_uop_stq_idx}, {stq_2_bits_uop_stq_idx}, {stq_1_bits_uop_stq_idx}, {stq_0_bits_uop_stq_idx}}; // @[lsu.scala:209:16, :222:42] wire [7:0][1:0] _GEN_36 = {{stq_7_bits_uop_rxq_idx}, {stq_6_bits_uop_rxq_idx}, {stq_5_bits_uop_rxq_idx}, {stq_4_bits_uop_rxq_idx}, {stq_3_bits_uop_rxq_idx}, {stq_2_bits_uop_rxq_idx}, {stq_1_bits_uop_rxq_idx}, {stq_0_bits_uop_rxq_idx}}; // @[lsu.scala:209:16, :222:42] wire [7:0][5:0] _GEN_37 = {{stq_7_bits_uop_pdst}, {stq_6_bits_uop_pdst}, {stq_5_bits_uop_pdst}, {stq_4_bits_uop_pdst}, {stq_3_bits_uop_pdst}, {stq_2_bits_uop_pdst}, {stq_1_bits_uop_pdst}, {stq_0_bits_uop_pdst}}; // @[lsu.scala:209:16, :222:42] wire [7:0][5:0] _GEN_38 = {{stq_7_bits_uop_prs1}, {stq_6_bits_uop_prs1}, {stq_5_bits_uop_prs1}, {stq_4_bits_uop_prs1}, {stq_3_bits_uop_prs1}, {stq_2_bits_uop_prs1}, {stq_1_bits_uop_prs1}, {stq_0_bits_uop_prs1}}; // @[lsu.scala:209:16, :222:42] wire [7:0][5:0] _GEN_39 = {{stq_7_bits_uop_prs2}, {stq_6_bits_uop_prs2}, {stq_5_bits_uop_prs2}, {stq_4_bits_uop_prs2}, {stq_3_bits_uop_prs2}, {stq_2_bits_uop_prs2}, {stq_1_bits_uop_prs2}, {stq_0_bits_uop_prs2}}; // @[lsu.scala:209:16, :222:42] wire [7:0][5:0] _GEN_40 = {{stq_7_bits_uop_prs3}, {stq_6_bits_uop_prs3}, {stq_5_bits_uop_prs3}, {stq_4_bits_uop_prs3}, {stq_3_bits_uop_prs3}, {stq_2_bits_uop_prs3}, {stq_1_bits_uop_prs3}, {stq_0_bits_uop_prs3}}; // @[lsu.scala:209:16, :222:42] wire [7:0][3:0] _GEN_41 = {{stq_7_bits_uop_ppred}, {stq_6_bits_uop_ppred}, {stq_5_bits_uop_ppred}, {stq_4_bits_uop_ppred}, {stq_3_bits_uop_ppred}, {stq_2_bits_uop_ppred}, {stq_1_bits_uop_ppred}, {stq_0_bits_uop_ppred}}; // @[lsu.scala:209:16, :222:42] wire [7:0] _GEN_42 = {{stq_7_bits_uop_prs1_busy}, {stq_6_bits_uop_prs1_busy}, {stq_5_bits_uop_prs1_busy}, {stq_4_bits_uop_prs1_busy}, {stq_3_bits_uop_prs1_busy}, {stq_2_bits_uop_prs1_busy}, {stq_1_bits_uop_prs1_busy}, {stq_0_bits_uop_prs1_busy}}; // @[lsu.scala:209:16, :222:42] wire [7:0] _GEN_43 = {{stq_7_bits_uop_prs2_busy}, {stq_6_bits_uop_prs2_busy}, {stq_5_bits_uop_prs2_busy}, {stq_4_bits_uop_prs2_busy}, {stq_3_bits_uop_prs2_busy}, {stq_2_bits_uop_prs2_busy}, {stq_1_bits_uop_prs2_busy}, {stq_0_bits_uop_prs2_busy}}; // @[lsu.scala:209:16, :222:42] wire [7:0] _GEN_44 = {{stq_7_bits_uop_prs3_busy}, {stq_6_bits_uop_prs3_busy}, {stq_5_bits_uop_prs3_busy}, {stq_4_bits_uop_prs3_busy}, {stq_3_bits_uop_prs3_busy}, {stq_2_bits_uop_prs3_busy}, {stq_1_bits_uop_prs3_busy}, {stq_0_bits_uop_prs3_busy}}; // @[lsu.scala:209:16, :222:42] wire [7:0] _GEN_45 = {{stq_7_bits_uop_ppred_busy}, {stq_6_bits_uop_ppred_busy}, {stq_5_bits_uop_ppred_busy}, {stq_4_bits_uop_ppred_busy}, {stq_3_bits_uop_ppred_busy}, {stq_2_bits_uop_ppred_busy}, {stq_1_bits_uop_ppred_busy}, {stq_0_bits_uop_ppred_busy}}; // @[lsu.scala:209:16, :222:42] wire [7:0][5:0] _GEN_46 = {{stq_7_bits_uop_stale_pdst}, {stq_6_bits_uop_stale_pdst}, {stq_5_bits_uop_stale_pdst}, {stq_4_bits_uop_stale_pdst}, {stq_3_bits_uop_stale_pdst}, {stq_2_bits_uop_stale_pdst}, {stq_1_bits_uop_stale_pdst}, {stq_0_bits_uop_stale_pdst}}; // @[lsu.scala:209:16, :222:42] wire [7:0] _GEN_47 = {{stq_7_bits_uop_exception}, {stq_6_bits_uop_exception}, {stq_5_bits_uop_exception}, {stq_4_bits_uop_exception}, {stq_3_bits_uop_exception}, {stq_2_bits_uop_exception}, {stq_1_bits_uop_exception}, {stq_0_bits_uop_exception}}; // @[lsu.scala:209:16, :222:42] wire _GEN_48 = _GEN_47[stq_execute_head]; // @[lsu.scala:218:29, :222:42] wire [7:0][63:0] _GEN_49 = {{stq_7_bits_uop_exc_cause}, {stq_6_bits_uop_exc_cause}, {stq_5_bits_uop_exc_cause}, {stq_4_bits_uop_exc_cause}, {stq_3_bits_uop_exc_cause}, {stq_2_bits_uop_exc_cause}, {stq_1_bits_uop_exc_cause}, {stq_0_bits_uop_exc_cause}}; // @[lsu.scala:209:16, :222:42] wire [7:0] _GEN_50 = {{stq_7_bits_uop_bypassable}, {stq_6_bits_uop_bypassable}, {stq_5_bits_uop_bypassable}, {stq_4_bits_uop_bypassable}, {stq_3_bits_uop_bypassable}, {stq_2_bits_uop_bypassable}, {stq_1_bits_uop_bypassable}, {stq_0_bits_uop_bypassable}}; // @[lsu.scala:209:16, :222:42] wire [7:0][4:0] _GEN_51 = {{stq_7_bits_uop_mem_cmd}, {stq_6_bits_uop_mem_cmd}, {stq_5_bits_uop_mem_cmd}, {stq_4_bits_uop_mem_cmd}, {stq_3_bits_uop_mem_cmd}, {stq_2_bits_uop_mem_cmd}, {stq_1_bits_uop_mem_cmd}, {stq_0_bits_uop_mem_cmd}}; // @[lsu.scala:209:16, :222:42] wire [7:0][1:0] _GEN_52 = {{stq_7_bits_uop_mem_size}, {stq_6_bits_uop_mem_size}, {stq_5_bits_uop_mem_size}, {stq_4_bits_uop_mem_size}, {stq_3_bits_uop_mem_size}, {stq_2_bits_uop_mem_size}, {stq_1_bits_uop_mem_size}, {stq_0_bits_uop_mem_size}}; // @[lsu.scala:209:16, :222:42] wire [1:0] dmem_req_0_bits_data_size = _GEN_52[stq_execute_head]; // @[AMOALU.scala:11:18] wire [7:0] _GEN_53 = {{stq_7_bits_uop_mem_signed}, {stq_6_bits_uop_mem_signed}, {stq_5_bits_uop_mem_signed}, {stq_4_bits_uop_mem_signed}, {stq_3_bits_uop_mem_signed}, {stq_2_bits_uop_mem_signed}, {stq_1_bits_uop_mem_signed}, {stq_0_bits_uop_mem_signed}}; // @[lsu.scala:209:16, :222:42] wire [7:0] _GEN_54 = {{stq_7_bits_uop_is_fence}, {stq_6_bits_uop_is_fence}, {stq_5_bits_uop_is_fence}, {stq_4_bits_uop_is_fence}, {stq_3_bits_uop_is_fence}, {stq_2_bits_uop_is_fence}, {stq_1_bits_uop_is_fence}, {stq_0_bits_uop_is_fence}}; // @[lsu.scala:209:16, :222:42] wire _GEN_55 = _GEN_54[stq_execute_head]; // @[lsu.scala:218:29, :222:42] wire [7:0] _GEN_56 = {{stq_7_bits_uop_is_fencei}, {stq_6_bits_uop_is_fencei}, {stq_5_bits_uop_is_fencei}, {stq_4_bits_uop_is_fencei}, {stq_3_bits_uop_is_fencei}, {stq_2_bits_uop_is_fencei}, {stq_1_bits_uop_is_fencei}, {stq_0_bits_uop_is_fencei}}; // @[lsu.scala:209:16, :222:42] wire [7:0] _GEN_57 = {{stq_7_bits_uop_is_amo}, {stq_6_bits_uop_is_amo}, {stq_5_bits_uop_is_amo}, {stq_4_bits_uop_is_amo}, {stq_3_bits_uop_is_amo}, {stq_2_bits_uop_is_amo}, {stq_1_bits_uop_is_amo}, {stq_0_bits_uop_is_amo}}; // @[lsu.scala:209:16, :222:42] wire _GEN_58 = _GEN_57[stq_execute_head]; // @[lsu.scala:218:29, :222:42] wire [7:0] _GEN_59 = {{stq_7_bits_uop_uses_ldq}, {stq_6_bits_uop_uses_ldq}, {stq_5_bits_uop_uses_ldq}, {stq_4_bits_uop_uses_ldq}, {stq_3_bits_uop_uses_ldq}, {stq_2_bits_uop_uses_ldq}, {stq_1_bits_uop_uses_ldq}, {stq_0_bits_uop_uses_ldq}}; // @[lsu.scala:209:16, :222:42] wire [7:0] _GEN_60 = {{stq_7_bits_uop_uses_stq}, {stq_6_bits_uop_uses_stq}, {stq_5_bits_uop_uses_stq}, {stq_4_bits_uop_uses_stq}, {stq_3_bits_uop_uses_stq}, {stq_2_bits_uop_uses_stq}, {stq_1_bits_uop_uses_stq}, {stq_0_bits_uop_uses_stq}}; // @[lsu.scala:209:16, :222:42] wire [7:0] _GEN_61 = {{stq_7_bits_uop_is_sys_pc2epc}, {stq_6_bits_uop_is_sys_pc2epc}, {stq_5_bits_uop_is_sys_pc2epc}, {stq_4_bits_uop_is_sys_pc2epc}, {stq_3_bits_uop_is_sys_pc2epc}, {stq_2_bits_uop_is_sys_pc2epc}, {stq_1_bits_uop_is_sys_pc2epc}, {stq_0_bits_uop_is_sys_pc2epc}}; // @[lsu.scala:209:16, :222:42] wire [7:0] _GEN_62 = {{stq_7_bits_uop_is_unique}, {stq_6_bits_uop_is_unique}, {stq_5_bits_uop_is_unique}, {stq_4_bits_uop_is_unique}, {stq_3_bits_uop_is_unique}, {stq_2_bits_uop_is_unique}, {stq_1_bits_uop_is_unique}, {stq_0_bits_uop_is_unique}}; // @[lsu.scala:209:16, :222:42] wire [7:0] _GEN_63 = {{stq_7_bits_uop_flush_on_commit}, {stq_6_bits_uop_flush_on_commit}, {stq_5_bits_uop_flush_on_commit}, {stq_4_bits_uop_flush_on_commit}, {stq_3_bits_uop_flush_on_commit}, {stq_2_bits_uop_flush_on_commit}, {stq_1_bits_uop_flush_on_commit}, {stq_0_bits_uop_flush_on_commit}}; // @[lsu.scala:209:16, :222:42] wire [7:0] _GEN_64 = {{stq_7_bits_uop_ldst_is_rs1}, {stq_6_bits_uop_ldst_is_rs1}, {stq_5_bits_uop_ldst_is_rs1}, {stq_4_bits_uop_ldst_is_rs1}, {stq_3_bits_uop_ldst_is_rs1}, {stq_2_bits_uop_ldst_is_rs1}, {stq_1_bits_uop_ldst_is_rs1}, {stq_0_bits_uop_ldst_is_rs1}}; // @[lsu.scala:209:16, :222:42] wire [7:0][5:0] _GEN_65 = {{stq_7_bits_uop_ldst}, {stq_6_bits_uop_ldst}, {stq_5_bits_uop_ldst}, {stq_4_bits_uop_ldst}, {stq_3_bits_uop_ldst}, {stq_2_bits_uop_ldst}, {stq_1_bits_uop_ldst}, {stq_0_bits_uop_ldst}}; // @[lsu.scala:209:16, :222:42] wire [7:0][5:0] _GEN_66 = {{stq_7_bits_uop_lrs1}, {stq_6_bits_uop_lrs1}, {stq_5_bits_uop_lrs1}, {stq_4_bits_uop_lrs1}, {stq_3_bits_uop_lrs1}, {stq_2_bits_uop_lrs1}, {stq_1_bits_uop_lrs1}, {stq_0_bits_uop_lrs1}}; // @[lsu.scala:209:16, :222:42] wire [7:0][5:0] _GEN_67 = {{stq_7_bits_uop_lrs2}, {stq_6_bits_uop_lrs2}, {stq_5_bits_uop_lrs2}, {stq_4_bits_uop_lrs2}, {stq_3_bits_uop_lrs2}, {stq_2_bits_uop_lrs2}, {stq_1_bits_uop_lrs2}, {stq_0_bits_uop_lrs2}}; // @[lsu.scala:209:16, :222:42] wire [7:0][5:0] _GEN_68 = {{stq_7_bits_uop_lrs3}, {stq_6_bits_uop_lrs3}, {stq_5_bits_uop_lrs3}, {stq_4_bits_uop_lrs3}, {stq_3_bits_uop_lrs3}, {stq_2_bits_uop_lrs3}, {stq_1_bits_uop_lrs3}, {stq_0_bits_uop_lrs3}}; // @[lsu.scala:209:16, :222:42] wire [7:0] _GEN_69 = {{stq_7_bits_uop_ldst_val}, {stq_6_bits_uop_ldst_val}, {stq_5_bits_uop_ldst_val}, {stq_4_bits_uop_ldst_val}, {stq_3_bits_uop_ldst_val}, {stq_2_bits_uop_ldst_val}, {stq_1_bits_uop_ldst_val}, {stq_0_bits_uop_ldst_val}}; // @[lsu.scala:209:16, :222:42] wire [7:0][1:0] _GEN_70 = {{stq_7_bits_uop_dst_rtype}, {stq_6_bits_uop_dst_rtype}, {stq_5_bits_uop_dst_rtype}, {stq_4_bits_uop_dst_rtype}, {stq_3_bits_uop_dst_rtype}, {stq_2_bits_uop_dst_rtype}, {stq_1_bits_uop_dst_rtype}, {stq_0_bits_uop_dst_rtype}}; // @[lsu.scala:209:16, :222:42] wire [7:0][1:0] _GEN_71 = {{stq_7_bits_uop_lrs1_rtype}, {stq_6_bits_uop_lrs1_rtype}, {stq_5_bits_uop_lrs1_rtype}, {stq_4_bits_uop_lrs1_rtype}, {stq_3_bits_uop_lrs1_rtype}, {stq_2_bits_uop_lrs1_rtype}, {stq_1_bits_uop_lrs1_rtype}, {stq_0_bits_uop_lrs1_rtype}}; // @[lsu.scala:209:16, :222:42] wire [7:0][1:0] _GEN_72 = {{stq_7_bits_uop_lrs2_rtype}, {stq_6_bits_uop_lrs2_rtype}, {stq_5_bits_uop_lrs2_rtype}, {stq_4_bits_uop_lrs2_rtype}, {stq_3_bits_uop_lrs2_rtype}, {stq_2_bits_uop_lrs2_rtype}, {stq_1_bits_uop_lrs2_rtype}, {stq_0_bits_uop_lrs2_rtype}}; // @[lsu.scala:209:16, :222:42] wire [7:0] _GEN_73 = {{stq_7_bits_uop_frs3_en}, {stq_6_bits_uop_frs3_en}, {stq_5_bits_uop_frs3_en}, {stq_4_bits_uop_frs3_en}, {stq_3_bits_uop_frs3_en}, {stq_2_bits_uop_frs3_en}, {stq_1_bits_uop_frs3_en}, {stq_0_bits_uop_frs3_en}}; // @[lsu.scala:209:16, :222:42] wire [7:0] _GEN_74 = {{stq_7_bits_uop_fp_val}, {stq_6_bits_uop_fp_val}, {stq_5_bits_uop_fp_val}, {stq_4_bits_uop_fp_val}, {stq_3_bits_uop_fp_val}, {stq_2_bits_uop_fp_val}, {stq_1_bits_uop_fp_val}, {stq_0_bits_uop_fp_val}}; // @[lsu.scala:209:16, :222:42] wire [7:0] _GEN_75 = {{stq_7_bits_uop_fp_single}, {stq_6_bits_uop_fp_single}, {stq_5_bits_uop_fp_single}, {stq_4_bits_uop_fp_single}, {stq_3_bits_uop_fp_single}, {stq_2_bits_uop_fp_single}, {stq_1_bits_uop_fp_single}, {stq_0_bits_uop_fp_single}}; // @[lsu.scala:209:16, :222:42] wire [7:0] _GEN_76 = {{stq_7_bits_uop_xcpt_pf_if}, {stq_6_bits_uop_xcpt_pf_if}, {stq_5_bits_uop_xcpt_pf_if}, {stq_4_bits_uop_xcpt_pf_if}, {stq_3_bits_uop_xcpt_pf_if}, {stq_2_bits_uop_xcpt_pf_if}, {stq_1_bits_uop_xcpt_pf_if}, {stq_0_bits_uop_xcpt_pf_if}}; // @[lsu.scala:209:16, :222:42] wire [7:0] _GEN_77 = {{stq_7_bits_uop_xcpt_ae_if}, {stq_6_bits_uop_xcpt_ae_if}, {stq_5_bits_uop_xcpt_ae_if}, {stq_4_bits_uop_xcpt_ae_if}, {stq_3_bits_uop_xcpt_ae_if}, {stq_2_bits_uop_xcpt_ae_if}, {stq_1_bits_uop_xcpt_ae_if}, {stq_0_bits_uop_xcpt_ae_if}}; // @[lsu.scala:209:16, :222:42] wire [7:0] _GEN_78 = {{stq_7_bits_uop_xcpt_ma_if}, {stq_6_bits_uop_xcpt_ma_if}, {stq_5_bits_uop_xcpt_ma_if}, {stq_4_bits_uop_xcpt_ma_if}, {stq_3_bits_uop_xcpt_ma_if}, {stq_2_bits_uop_xcpt_ma_if}, {stq_1_bits_uop_xcpt_ma_if}, {stq_0_bits_uop_xcpt_ma_if}}; // @[lsu.scala:209:16, :222:42] wire [7:0] _GEN_79 = {{stq_7_bits_uop_bp_debug_if}, {stq_6_bits_uop_bp_debug_if}, {stq_5_bits_uop_bp_debug_if}, {stq_4_bits_uop_bp_debug_if}, {stq_3_bits_uop_bp_debug_if}, {stq_2_bits_uop_bp_debug_if}, {stq_1_bits_uop_bp_debug_if}, {stq_0_bits_uop_bp_debug_if}}; // @[lsu.scala:209:16, :222:42] wire [7:0] _GEN_80 = {{stq_7_bits_uop_bp_xcpt_if}, {stq_6_bits_uop_bp_xcpt_if}, {stq_5_bits_uop_bp_xcpt_if}, {stq_4_bits_uop_bp_xcpt_if}, {stq_3_bits_uop_bp_xcpt_if}, {stq_2_bits_uop_bp_xcpt_if}, {stq_1_bits_uop_bp_xcpt_if}, {stq_0_bits_uop_bp_xcpt_if}}; // @[lsu.scala:209:16, :222:42] wire [7:0][1:0] _GEN_81 = {{stq_7_bits_uop_debug_fsrc}, {stq_6_bits_uop_debug_fsrc}, {stq_5_bits_uop_debug_fsrc}, {stq_4_bits_uop_debug_fsrc}, {stq_3_bits_uop_debug_fsrc}, {stq_2_bits_uop_debug_fsrc}, {stq_1_bits_uop_debug_fsrc}, {stq_0_bits_uop_debug_fsrc}}; // @[lsu.scala:209:16, :222:42] wire [7:0][1:0] _GEN_82 = {{stq_7_bits_uop_debug_tsrc}, {stq_6_bits_uop_debug_tsrc}, {stq_5_bits_uop_debug_tsrc}, {stq_4_bits_uop_debug_tsrc}, {stq_3_bits_uop_debug_tsrc}, {stq_2_bits_uop_debug_tsrc}, {stq_1_bits_uop_debug_tsrc}, {stq_0_bits_uop_debug_tsrc}}; // @[lsu.scala:209:16, :222:42] wire [7:0] _GEN_83 = {{stq_7_bits_addr_valid}, {stq_6_bits_addr_valid}, {stq_5_bits_addr_valid}, {stq_4_bits_addr_valid}, {stq_3_bits_addr_valid}, {stq_2_bits_addr_valid}, {stq_1_bits_addr_valid}, {stq_0_bits_addr_valid}}; // @[lsu.scala:209:16, :222:42] wire [7:0][39:0] _GEN_84 = {{stq_7_bits_addr_bits}, {stq_6_bits_addr_bits}, {stq_5_bits_addr_bits}, {stq_4_bits_addr_bits}, {stq_3_bits_addr_bits}, {stq_2_bits_addr_bits}, {stq_1_bits_addr_bits}, {stq_0_bits_addr_bits}}; // @[lsu.scala:209:16, :222:42] wire [7:0] _GEN_85 = {{stq_7_bits_addr_is_virtual}, {stq_6_bits_addr_is_virtual}, {stq_5_bits_addr_is_virtual}, {stq_4_bits_addr_is_virtual}, {stq_3_bits_addr_is_virtual}, {stq_2_bits_addr_is_virtual}, {stq_1_bits_addr_is_virtual}, {stq_0_bits_addr_is_virtual}}; // @[lsu.scala:209:16, :222:42] wire [7:0] _GEN_86 = {{stq_7_bits_data_valid}, {stq_6_bits_data_valid}, {stq_5_bits_data_valid}, {stq_4_bits_data_valid}, {stq_3_bits_data_valid}, {stq_2_bits_data_valid}, {stq_1_bits_data_valid}, {stq_0_bits_data_valid}}; // @[lsu.scala:209:16, :222:42] wire [7:0][63:0] _GEN_87 = {{stq_7_bits_data_bits}, {stq_6_bits_data_bits}, {stq_5_bits_data_bits}, {stq_4_bits_data_bits}, {stq_3_bits_data_bits}, {stq_2_bits_data_bits}, {stq_1_bits_data_bits}, {stq_0_bits_data_bits}}; // @[lsu.scala:209:16, :222:42] wire [63:0] _GEN_88 = _GEN_87[stq_execute_head]; // @[lsu.scala:218:29, :222:42] wire [7:0] _GEN_89 = {{stq_7_bits_committed}, {stq_6_bits_committed}, {stq_5_bits_committed}, {stq_4_bits_committed}, {stq_3_bits_committed}, {stq_2_bits_committed}, {stq_1_bits_committed}, {stq_0_bits_committed}}; // @[lsu.scala:209:16, :222:42] reg [2:0] hella_state; // @[lsu.scala:240:38] reg [39:0] hella_req_addr; // @[lsu.scala:241:34] assign io_hellacache_resp_bits_addr_0 = hella_req_addr; // @[lsu.scala:201:7, :241:34] reg hella_req_dv; // @[lsu.scala:241:34] reg [63:0] hella_data_data; // @[lsu.scala:242:34] wire [63:0] _dmem_req_0_bits_data_T_42 = hella_data_data; // @[AMOALU.scala:29:13] reg [7:0] hella_data_mask; // @[lsu.scala:242:34] reg [31:0] hella_paddr; // @[lsu.scala:243:34] reg hella_xcpt_ma_ld; // @[lsu.scala:244:34] reg hella_xcpt_ma_st; // @[lsu.scala:244:34] reg hella_xcpt_pf_ld; // @[lsu.scala:244:34] reg hella_xcpt_pf_st; // @[lsu.scala:244:34] reg hella_xcpt_gf_ld; // @[lsu.scala:244:34] reg hella_xcpt_gf_st; // @[lsu.scala:244:34] reg hella_xcpt_ae_ld; // @[lsu.scala:244:34] reg hella_xcpt_ae_st; // @[lsu.scala:244:34] assign _io_core_perf_tlbMiss_T = io_ptw_req_ready_0 & io_ptw_req_valid_0; // @[Decoupled.scala:51:35] assign io_core_perf_tlbMiss_0 = _io_core_perf_tlbMiss_T; // @[Decoupled.scala:51:35] wire clear_store; // @[lsu.scala:257:33] reg [7:0] live_store_mask; // @[lsu.scala:258:32] wire [7:0] _GEN_90 = 8'h1 << stq_head; // @[lsu.scala:215:29, :259:71] wire [7:0] _next_live_store_mask_T; // @[lsu.scala:259:71] assign _next_live_store_mask_T = _GEN_90; // @[lsu.scala:259:71] wire [7:0] _ldq_0_bits_st_dep_mask_T; // @[lsu.scala:277:66] assign _ldq_0_bits_st_dep_mask_T = _GEN_90; // @[lsu.scala:259:71, :277:66] wire [7:0] _ldq_1_bits_st_dep_mask_T; // @[lsu.scala:277:66] assign _ldq_1_bits_st_dep_mask_T = _GEN_90; // @[lsu.scala:259:71, :277:66] wire [7:0] _ldq_2_bits_st_dep_mask_T; // @[lsu.scala:277:66] assign _ldq_2_bits_st_dep_mask_T = _GEN_90; // @[lsu.scala:259:71, :277:66] wire [7:0] _ldq_3_bits_st_dep_mask_T; // @[lsu.scala:277:66] assign _ldq_3_bits_st_dep_mask_T = _GEN_90; // @[lsu.scala:259:71, :277:66] wire [7:0] _ldq_4_bits_st_dep_mask_T; // @[lsu.scala:277:66] assign _ldq_4_bits_st_dep_mask_T = _GEN_90; // @[lsu.scala:259:71, :277:66] wire [7:0] _ldq_5_bits_st_dep_mask_T; // @[lsu.scala:277:66] assign _ldq_5_bits_st_dep_mask_T = _GEN_90; // @[lsu.scala:259:71, :277:66] wire [7:0] _ldq_6_bits_st_dep_mask_T; // @[lsu.scala:277:66] assign _ldq_6_bits_st_dep_mask_T = _GEN_90; // @[lsu.scala:259:71, :277:66] wire [7:0] _ldq_7_bits_st_dep_mask_T; // @[lsu.scala:277:66] assign _ldq_7_bits_st_dep_mask_T = _GEN_90; // @[lsu.scala:259:71, :277:66] wire [7:0] _next_live_store_mask_T_1 = ~_next_live_store_mask_T; // @[lsu.scala:259:{65,71}] wire [7:0] _next_live_store_mask_T_2 = live_store_mask & _next_live_store_mask_T_1; // @[lsu.scala:258:32, :259:{63,65}] wire [7:0] next_live_store_mask = clear_store ? _next_live_store_mask_T_2 : live_store_mask; // @[lsu.scala:257:33, :258:32, :259:{33,63}] wire [7:0] _ldq_0_bits_st_dep_mask_T_1 = ~_ldq_0_bits_st_dep_mask_T; // @[lsu.scala:277:{60,66}] wire [7:0] _ldq_0_bits_st_dep_mask_T_2 = ldq_0_bits_st_dep_mask & _ldq_0_bits_st_dep_mask_T_1; // @[lsu.scala:208:16, :277:{58,60}] wire [7:0] _ldq_1_bits_st_dep_mask_T_1 = ~_ldq_1_bits_st_dep_mask_T; // @[lsu.scala:277:{60,66}] wire [7:0] _ldq_1_bits_st_dep_mask_T_2 = ldq_1_bits_st_dep_mask & _ldq_1_bits_st_dep_mask_T_1; // @[lsu.scala:208:16, :277:{58,60}] wire [7:0] _ldq_2_bits_st_dep_mask_T_1 = ~_ldq_2_bits_st_dep_mask_T; // @[lsu.scala:277:{60,66}] wire [7:0] _ldq_2_bits_st_dep_mask_T_2 = ldq_2_bits_st_dep_mask & _ldq_2_bits_st_dep_mask_T_1; // @[lsu.scala:208:16, :277:{58,60}] wire [7:0] _ldq_3_bits_st_dep_mask_T_1 = ~_ldq_3_bits_st_dep_mask_T; // @[lsu.scala:277:{60,66}] wire [7:0] _ldq_3_bits_st_dep_mask_T_2 = ldq_3_bits_st_dep_mask & _ldq_3_bits_st_dep_mask_T_1; // @[lsu.scala:208:16, :277:{58,60}] wire [7:0] _ldq_4_bits_st_dep_mask_T_1 = ~_ldq_4_bits_st_dep_mask_T; // @[lsu.scala:277:{60,66}] wire [7:0] _ldq_4_bits_st_dep_mask_T_2 = ldq_4_bits_st_dep_mask & _ldq_4_bits_st_dep_mask_T_1; // @[lsu.scala:208:16, :277:{58,60}] wire [7:0] _ldq_5_bits_st_dep_mask_T_1 = ~_ldq_5_bits_st_dep_mask_T; // @[lsu.scala:277:{60,66}] wire [7:0] _ldq_5_bits_st_dep_mask_T_2 = ldq_5_bits_st_dep_mask & _ldq_5_bits_st_dep_mask_T_1; // @[lsu.scala:208:16, :277:{58,60}] wire [7:0] _ldq_6_bits_st_dep_mask_T_1 = ~_ldq_6_bits_st_dep_mask_T; // @[lsu.scala:277:{60,66}] wire [7:0] _ldq_6_bits_st_dep_mask_T_2 = ldq_6_bits_st_dep_mask & _ldq_6_bits_st_dep_mask_T_1; // @[lsu.scala:208:16, :277:{58,60}] wire [7:0] _ldq_7_bits_st_dep_mask_T_1 = ~_ldq_7_bits_st_dep_mask_T; // @[lsu.scala:277:{60,66}] wire [7:0] _ldq_7_bits_st_dep_mask_T_2 = ldq_7_bits_st_dep_mask & _ldq_7_bits_st_dep_mask_T_1; // @[lsu.scala:208:16, :277:{58,60}] wire _GEN_91 = stq_0_valid \| stq_1_valid; // @[lsu.scala:209:16, :285:79] wire _stq_nonempty_T; // @[lsu.scala:285:79] assign _stq_nonempty_T = _GEN_91; // @[lsu.scala:285:79] wire _io_hellacache_store_pending_T; // @[lsu.scala:1530:59] assign _io_hellacache_store_pending_T = _GEN_91; // @[lsu.scala:285:79, :1530:59] wire _stq_nonempty_T_1 = _stq_nonempty_T \| stq_2_valid; // @[lsu.scala:209:16, :285:79] wire _stq_nonempty_T_2 = _stq_nonempty_T_1 \| stq_3_valid; // @[lsu.scala:209:16, :285:79] wire _stq_nonempty_T_3 = _stq_nonempty_T_2 \| stq_4_valid; // @[lsu.scala:209:16, :285:79] wire _stq_nonempty_T_4 = _stq_nonempty_T_3 \| stq_5_valid; // @[lsu.scala:209:16, :285:79] wire _stq_nonempty_T_5 = _stq_nonempty_T_4 \| stq_6_valid; // @[lsu.scala:209:16, :285:79] wire _stq_nonempty_T_6 = _stq_nonempty_T_5 \| stq_7_valid; // @[lsu.scala:209:16, :285:79] wire stq_nonempty = _stq_nonempty_T_6; // @[lsu.scala:285:{79,84}] wire [2:0] _T_32 = ldq_tail + 3'h1; // @[util.scala:203:14] assign io_core_ldq_full_0_0 = _T_32 == ldq_head; // @[util.scala:203:14] wire [2:0] _T_39 = stq_tail + 3'h1; // @[util.scala:203:14] assign io_core_stq_full_0_0 = _T_39 == stq_head; // @[util.scala:203:14] wire _dis_ld_val_T = io_core_dis_uops_0_valid_0 & io_core_dis_uops_0_bits_uses_ldq_0; // @[lsu.scala:201:7, :300:48] wire _dis_ld_val_T_1 = ~io_core_dis_uops_0_bits_exception_0; // @[lsu.scala:201:7, :300:88] wire dis_ld_val = _dis_ld_val_T & _dis_ld_val_T_1; // @[lsu.scala:300:{48,85,88}] wire _dis_st_val_T = io_core_dis_uops_0_valid_0 & io_core_dis_uops_0_bits_uses_stq_0; // @[lsu.scala:201:7, :301:48] wire _dis_st_val_T_1 = ~io_core_dis_uops_0_bits_exception_0; // @[lsu.scala:201:7, :300:88, :301:88] wire dis_st_val = _dis_st_val_T & _dis_st_val_T_1; // @[lsu.scala:301:{48,85,88}] wire [7:0] _GEN_92 = {{ldq_7_valid}, {ldq_6_valid}, {ldq_5_valid}, {ldq_4_valid}, {ldq_3_valid}, {ldq_2_valid}, {ldq_1_valid}, {ldq_0_valid}}; // @[lsu.scala:208:16, :304:44] wire _io_core_fencei_rdy_T = ~stq_nonempty; // @[lsu.scala:285:84, :347:28] assign _io_core_fencei_rdy_T_1 = _io_core_fencei_rdy_T & io_dmem_ordered_0; // @[lsu.scala:201:7, :347:{28,42}] assign io_core_fencei_rdy_0 = _io_core_fencei_rdy_T_1; // @[lsu.scala:201:7, :347:42] wire mem_xcpt_valid; // @[lsu.scala:358:29] wire [3:0] mem_xcpt_cause; // @[lsu.scala:359:29] wire [3:0] mem_xcpt_uop_ctrl_br_type; // @[lsu.scala:360:29] wire [1:0] mem_xcpt_uop_ctrl_op1_sel; // @[lsu.scala:360:29] wire [2:0] mem_xcpt_uop_ctrl_op2_sel; // @[lsu.scala:360:29] wire [2:0] mem_xcpt_uop_ctrl_imm_sel; // @[lsu.scala:360:29] wire [4:0] mem_xcpt_uop_ctrl_op_fcn; // @[lsu.scala:360:29] wire mem_xcpt_uop_ctrl_fcn_dw; // @[lsu.scala:360:29] wire [2:0] mem_xcpt_uop_ctrl_csr_cmd; // @[lsu.scala:360:29] wire mem_xcpt_uop_ctrl_is_load; // @[lsu.scala:360:29] wire mem_xcpt_uop_ctrl_is_sta; // @[lsu.scala:360:29] wire mem_xcpt_uop_ctrl_is_std; // @[lsu.scala:360:29] wire [6:0] mem_xcpt_uop_uopc; // @[lsu.scala:360:29] wire [31:0] mem_xcpt_uop_inst; // @[lsu.scala:360:29] wire [31:0] mem_xcpt_uop_debug_inst; // @[lsu.scala:360:29] wire mem_xcpt_uop_is_rvc; // @[lsu.scala:360:29] wire [39:0] mem_xcpt_uop_debug_pc; // @[lsu.scala:360:29] wire [2:0] mem_xcpt_uop_iq_type; // @[lsu.scala:360:29] wire [9:0] mem_xcpt_uop_fu_code; // @[lsu.scala:360:29] wire [1:0] mem_xcpt_uop_iw_state; // @[lsu.scala:360:29] wire mem_xcpt_uop_iw_p1_poisoned; // @[lsu.scala:360:29] wire mem_xcpt_uop_iw_p2_poisoned; // @[lsu.scala:360:29] wire mem_xcpt_uop_is_br; // @[lsu.scala:360:29] wire mem_xcpt_uop_is_jalr; // @[lsu.scala:360:29] wire mem_xcpt_uop_is_jal; // @[lsu.scala:360:29] wire mem_xcpt_uop_is_sfb; // @[lsu.scala:360:29] wire [7:0] mem_xcpt_uop_br_mask; // @[lsu.scala:360:29] wire [2:0] mem_xcpt_uop_br_tag; // @[lsu.scala:360:29] wire [3:0] mem_xcpt_uop_ftq_idx; // @[lsu.scala:360:29] wire mem_xcpt_uop_edge_inst; // @[lsu.scala:360:29] wire [5:0] mem_xcpt_uop_pc_lob; // @[lsu.scala:360:29] wire mem_xcpt_uop_taken; // @[lsu.scala:360:29] wire [19:0] mem_xcpt_uop_imm_packed; // @[lsu.scala:360:29] wire [11:0] mem_xcpt_uop_csr_addr; // @[lsu.scala:360:29] wire [4:0] mem_xcpt_uop_rob_idx; // @[lsu.scala:360:29] wire [2:0] mem_xcpt_uop_ldq_idx; // @[lsu.scala:360:29] wire [2:0] mem_xcpt_uop_stq_idx; // @[lsu.scala:360:29] wire [1:0] mem_xcpt_uop_rxq_idx; // @[lsu.scala:360:29] wire [5:0] mem_xcpt_uop_pdst; // @[lsu.scala:360:29] wire [5:0] mem_xcpt_uop_prs1; // @[lsu.scala:360:29] wire [5:0] mem_xcpt_uop_prs2; // @[lsu.scala:360:29] wire [5:0] mem_xcpt_uop_prs3; // @[lsu.scala:360:29] wire [3:0] mem_xcpt_uop_ppred; // @[lsu.scala:360:29] wire mem_xcpt_uop_prs1_busy; // @[lsu.scala:360:29] wire mem_xcpt_uop_prs2_busy; // @[lsu.scala:360:29] wire mem_xcpt_uop_prs3_busy; // @[lsu.scala:360:29] wire mem_xcpt_uop_ppred_busy; // @[lsu.scala:360:29] wire [5:0] mem_xcpt_uop_stale_pdst; // @[lsu.scala:360:29] wire mem_xcpt_uop_exception; // @[lsu.scala:360:29] wire [63:0] mem_xcpt_uop_exc_cause; // @[lsu.scala:360:29] wire mem_xcpt_uop_bypassable; // @[lsu.scala:360:29] wire [4:0] mem_xcpt_uop_mem_cmd; // @[lsu.scala:360:29] wire [1:0] mem_xcpt_uop_mem_size; // @[lsu.scala:360:29] wire mem_xcpt_uop_mem_signed; // @[lsu.scala:360:29] wire mem_xcpt_uop_is_fence; // @[lsu.scala:360:29] wire mem_xcpt_uop_is_fencei; // @[lsu.scala:360:29] wire mem_xcpt_uop_is_amo; // @[lsu.scala:360:29] wire mem_xcpt_uop_uses_ldq; // @[lsu.scala:360:29] wire mem_xcpt_uop_uses_stq; // @[lsu.scala:360:29] wire mem_xcpt_uop_is_sys_pc2epc; // @[lsu.scala:360:29] wire mem_xcpt_uop_is_unique; // @[lsu.scala:360:29] wire mem_xcpt_uop_flush_on_commit; // @[lsu.scala:360:29] wire mem_xcpt_uop_ldst_is_rs1; // @[lsu.scala:360:29] wire [5:0] mem_xcpt_uop_ldst; // @[lsu.scala:360:29] wire [5:0] mem_xcpt_uop_lrs1; // @[lsu.scala:360:29] wire [5:0] mem_xcpt_uop_lrs2; // @[lsu.scala:360:29] wire [5:0] mem_xcpt_uop_lrs3; // @[lsu.scala:360:29] wire mem_xcpt_uop_ldst_val; // @[lsu.scala:360:29] wire [1:0] mem_xcpt_uop_dst_rtype; // @[lsu.scala:360:29] wire [1:0] mem_xcpt_uop_lrs1_rtype; // @[lsu.scala:360:29] wire [1:0] mem_xcpt_uop_lrs2_rtype; // @[lsu.scala:360:29] wire mem_xcpt_uop_frs3_en; // @[lsu.scala:360:29] wire mem_xcpt_uop_fp_val; // @[lsu.scala:360:29] wire mem_xcpt_uop_fp_single; // @[lsu.scala:360:29] wire mem_xcpt_uop_xcpt_pf_if; // @[lsu.scala:360:29] wire mem_xcpt_uop_xcpt_ae_if; // @[lsu.scala:360:29] wire mem_xcpt_uop_xcpt_ma_if; // @[lsu.scala:360:29] wire mem_xcpt_uop_bp_debug_if; // @[lsu.scala:360:29] wire mem_xcpt_uop_bp_xcpt_if; // @[lsu.scala:360:29] wire [1:0] mem_xcpt_uop_debug_fsrc; // @[lsu.scala:360:29] wire [1:0] mem_xcpt_uop_debug_tsrc; // @[lsu.scala:360:29] wire [39:0] mem_xcpt_vaddr; // @[lsu.scala:361:29] wire will_fire_load_incoming_0_will_fire; // @[lsu.scala:535:61] wire will_fire_load_incoming_0; // @[lsu.scala:370:38] wire will_fire_stad_incoming_0_will_fire; // @[lsu.scala:535:61] wire will_fire_stad_incoming_0; // @[lsu.scala:371:38] wire will_fire_sta_incoming_0_will_fire; // @[lsu.scala:535:61] wire will_fire_sta_incoming_0; // @[lsu.scala:372:38] wire will_fire_std_incoming_0_will_fire; // @[lsu.scala:535:61] wire will_fire_std_incoming_0; // @[lsu.scala:373:38] wire will_fire_sfence_0_will_fire; // @[lsu.scala:535:61] wire will_fire_sfence_0; // @[lsu.scala:374:38] wire will_fire_hella_incoming_0_will_fire; // @[lsu.scala:535:61] wire will_fire_hella_incoming_0; // @[lsu.scala:375:38] wire _exe_passthr_T = will_fire_hella_incoming_0; // @[lsu.scala:375:38, :642:23] wire will_fire_hella_wakeup_0_will_fire; // @[lsu.scala:535:61] wire will_fire_hella_wakeup_0; // @[lsu.scala:376:38] wire will_fire_release_0_will_fire; // @[lsu.scala:535:61] assign io_dmem_release_ready_0 = will_fire_release_0; // @[lsu.scala:201:7, :377:38] wire will_fire_load_retry_0_will_fire; // @[lsu.scala:535:61] wire will_fire_load_retry_0; // @[lsu.scala:378:38] wire will_fire_sta_retry_0_will_fire; // @[lsu.scala:535:61] wire will_fire_sta_retry_0; // @[lsu.scala:379:38] wire will_fire_store_commit_0_will_fire; // @[lsu.scala:535:61] wire will_fire_store_commit_0; // @[lsu.scala:380:38] wire will_fire_load_wakeup_0_will_fire; // @[lsu.scala:535:61] wire will_fire_load_wakeup_0; // @[lsu.scala:381:38] wire [6:0] mem_incoming_uop_out_uopc = exe_req_0_bits_uop_uopc; // @[util.scala:96:23] wire [31:0] mem_incoming_uop_out_inst = exe_req_0_bits_uop_inst; // @[util.scala:96:23] wire [31:0] mem_incoming_uop_out_debug_inst = exe_req_0_bits_uop_debug_inst; // @[util.scala:96:23] wire mem_incoming_uop_out_is_rvc = exe_req_0_bits_uop_is_rvc; // @[util.scala:96:23] wire [39:0] mem_incoming_uop_out_debug_pc = exe_req_0_bits_uop_debug_pc; // @[util.scala:96:23] wire [2:0] mem_incoming_uop_out_iq_type = exe_req_0_bits_uop_iq_type; // @[util.scala:96:23] wire [9:0] mem_incoming_uop_out_fu_code = exe_req_0_bits_uop_fu_code; // @[util.scala:96:23] wire [3:0] mem_incoming_uop_out_ctrl_br_type = exe_req_0_bits_uop_ctrl_br_type; // @[util.scala:96:23] wire [1:0] mem_incoming_uop_out_ctrl_op1_sel = exe_req_0_bits_uop_ctrl_op1_sel; // @[util.scala:96:23] wire [2:0] mem_incoming_uop_out_ctrl_op2_sel = exe_req_0_bits_uop_ctrl_op2_sel; // @[util.scala:96:23] wire [2:0] mem_incoming_uop_out_ctrl_imm_sel = exe_req_0_bits_uop_ctrl_imm_sel; // @[util.scala:96:23] wire [4:0] mem_incoming_uop_out_ctrl_op_fcn = exe_req_0_bits_uop_ctrl_op_fcn; // @[util.scala:96:23] wire mem_incoming_uop_out_ctrl_fcn_dw = exe_req_0_bits_uop_ctrl_fcn_dw; // @[util.scala:96:23] wire [2:0] mem_incoming_uop_out_ctrl_csr_cmd = exe_req_0_bits_uop_ctrl_csr_cmd; // @[util.scala:96:23] wire mem_incoming_uop_out_ctrl_is_load = exe_req_0_bits_uop_ctrl_is_load; // @[util.scala:96:23] wire mem_incoming_uop_out_ctrl_is_sta = exe_req_0_bits_uop_ctrl_is_sta; // @[util.scala:96:23] wire mem_incoming_uop_out_ctrl_is_std = exe_req_0_bits_uop_ctrl_is_std; // @[util.scala:96:23] wire [1:0] mem_incoming_uop_out_iw_state = exe_req_0_bits_uop_iw_state; // @[util.scala:96:23] wire mem_incoming_uop_out_iw_p1_poisoned = exe_req_0_bits_uop_iw_p1_poisoned; // @[util.scala:96:23] wire mem_incoming_uop_out_iw_p2_poisoned = exe_req_0_bits_uop_iw_p2_poisoned; // @[util.scala:96:23] wire mem_incoming_uop_out_is_br = exe_req_0_bits_uop_is_br; // @[util.scala:96:23] wire mem_incoming_uop_out_is_jalr = exe_req_0_bits_uop_is_jalr; // @[util.scala:96:23] wire mem_incoming_uop_out_is_jal = exe_req_0_bits_uop_is_jal; // @[util.scala:96:23] wire mem_incoming_uop_out_is_sfb = exe_req_0_bits_uop_is_sfb; // @[util.scala:96:23] wire [2:0] mem_incoming_uop_out_br_tag = exe_req_0_bits_uop_br_tag; // @[util.scala:96:23] wire [3:0] mem_incoming_uop_out_ftq_idx = exe_req_0_bits_uop_ftq_idx; // @[util.scala:96:23] wire mem_incoming_uop_out_edge_inst = exe_req_0_bits_uop_edge_inst; // @[util.scala:96:23] wire [5:0] mem_incoming_uop_out_pc_lob = exe_req_0_bits_uop_pc_lob; // @[util.scala:96:23] wire mem_incoming_uop_out_taken = exe_req_0_bits_uop_taken; // @[util.scala:96:23] wire [19:0] mem_incoming_uop_out_imm_packed = exe_req_0_bits_uop_imm_packed; // @[util.scala:96:23] wire [11:0] mem_incoming_uop_out_csr_addr = exe_req_0_bits_uop_csr_addr; // @[util.scala:96:23] wire [4:0] mem_incoming_uop_out_rob_idx = exe_req_0_bits_uop_rob_idx; // @[util.scala:96:23] wire [2:0] ldq_incoming_idx_0 = exe_req_0_bits_uop_ldq_idx; // @[lsu.scala:263:49, :383:25] wire [2:0] mem_incoming_uop_out_ldq_idx = exe_req_0_bits_uop_ldq_idx; // @[util.scala:96:23] wire [2:0] stq_incoming_idx_0 = exe_req_0_bits_uop_stq_idx; // @[lsu.scala:263:49, :383:25] wire [2:0] mem_incoming_uop_out_stq_idx = exe_req_0_bits_uop_stq_idx; // @[util.scala:96:23] wire [1:0] mem_incoming_uop_out_rxq_idx = exe_req_0_bits_uop_rxq_idx; // @[util.scala:96:23] wire [5:0] mem_incoming_uop_out_pdst = exe_req_0_bits_uop_pdst; // @[util.scala:96:23] wire [5:0] mem_incoming_uop_out_prs1 = exe_req_0_bits_uop_prs1; // @[util.scala:96:23] wire [5:0] mem_incoming_uop_out_prs2 = exe_req_0_bits_uop_prs2; // @[util.scala:96:23] wire [5:0] mem_incoming_uop_out_prs3 = exe_req_0_bits_uop_prs3; // @[util.scala:96:23] wire [3:0] mem_incoming_uop_out_ppred = exe_req_0_bits_uop_ppred; // @[util.scala:96:23] wire mem_incoming_uop_out_prs1_busy = exe_req_0_bits_uop_prs1_busy; // @[util.scala:96:23] wire mem_incoming_uop_out_prs2_busy = exe_req_0_bits_uop_prs2_busy; // @[util.scala:96:23] wire mem_incoming_uop_out_prs3_busy = exe_req_0_bits_uop_prs3_busy; // @[util.scala:96:23] wire mem_incoming_uop_out_ppred_busy = exe_req_0_bits_uop_ppred_busy; // @[util.scala:96:23] wire [5:0] mem_incoming_uop_out_stale_pdst = exe_req_0_bits_uop_stale_pdst; // @[util.scala:96:23] wire mem_incoming_uop_out_exception = exe_req_0_bits_uop_exception; // @[util.scala:96:23] wire [63:0] mem_incoming_uop_out_exc_cause = exe_req_0_bits_uop_exc_cause; // @[util.scala:96:23] wire mem_incoming_uop_out_bypassable = exe_req_0_bits_uop_bypassable; // @[util.scala:96:23] wire [4:0] mem_incoming_uop_out_mem_cmd = exe_req_0_bits_uop_mem_cmd; // @[util.scala:96:23] wire [1:0] mem_incoming_uop_out_mem_size = exe_req_0_bits_uop_mem_size; // @[util.scala:96:23] wire mem_incoming_uop_out_mem_signed = exe_req_0_bits_uop_mem_signed; // @[util.scala:96:23] wire mem_incoming_uop_out_is_fence = exe_req_0_bits_uop_is_fence; // @[util.scala:96:23] wire mem_incoming_uop_out_is_fencei = exe_req_0_bits_uop_is_fencei; // @[util.scala:96:23] wire mem_incoming_uop_out_is_amo = exe_req_0_bits_uop_is_amo; // @[util.scala:96:23] wire mem_incoming_uop_out_uses_ldq = exe_req_0_bits_uop_uses_ldq; // @[util.scala:96:23] wire mem_incoming_uop_out_uses_stq = exe_req_0_bits_uop_uses_stq; // @[util.scala:96:23] wire mem_incoming_uop_out_is_sys_pc2epc = exe_req_0_bits_uop_is_sys_pc2epc; // @[util.scala:96:23] wire mem_incoming_uop_out_is_unique = exe_req_0_bits_uop_is_unique; // @[util.scala:96:23] wire mem_incoming_uop_out_flush_on_commit = exe_req_0_bits_uop_flush_on_commit; // @[util.scala:96:23] wire mem_incoming_uop_out_ldst_is_rs1 = exe_req_0_bits_uop_ldst_is_rs1; // @[util.scala:96:23] wire [5:0] mem_incoming_uop_out_ldst = exe_req_0_bits_uop_ldst; // @[util.scala:96:23] wire [5:0] mem_incoming_uop_out_lrs1 = exe_req_0_bits_uop_lrs1; // @[util.scala:96:23] wire [5:0] mem_incoming_uop_out_lrs2 = exe_req_0_bits_uop_lrs2; // @[util.scala:96:23] wire [5:0] mem_incoming_uop_out_lrs3 = exe_req_0_bits_uop_lrs3; // @[util.scala:96:23] wire mem_incoming_uop_out_ldst_val = exe_req_0_bits_uop_ldst_val; // @[util.scala:96:23] wire [1:0] mem_incoming_uop_out_dst_rtype = exe_req_0_bits_uop_dst_rtype; // @[util.scala:96:23] wire [1:0] mem_incoming_uop_out_lrs1_rtype = exe_req_0_bits_uop_lrs1_rtype; // @[util.scala:96:23] wire [1:0] mem_incoming_uop_out_lrs2_rtype = exe_req_0_bits_uop_lrs2_rtype; // @[util.scala:96:23] wire mem_incoming_uop_out_frs3_en = exe_req_0_bits_uop_frs3_en; // @[util.scala:96:23] wire mem_incoming_uop_out_fp_val = exe_req_0_bits_uop_fp_val; // @[util.scala:96:23] wire mem_incoming_uop_out_fp_single = exe_req_0_bits_uop_fp_single; // @[util.scala:96:23] wire mem_incoming_uop_out_xcpt_pf_if = exe_req_0_bits_uop_xcpt_pf_if; // @[util.scala:96:23] wire mem_incoming_uop_out_xcpt_ae_if = exe_req_0_bits_uop_xcpt_ae_if; // @[util.scala:96:23] wire mem_incoming_uop_out_xcpt_ma_if = exe_req_0_bits_uop_xcpt_ma_if; // @[util.scala:96:23] wire mem_incoming_uop_out_bp_debug_if = exe_req_0_bits_uop_bp_debug_if; // @[util.scala:96:23] wire mem_incoming_uop_out_bp_xcpt_if = exe_req_0_bits_uop_bp_xcpt_if; // @[util.scala:96:23] wire [1:0] mem_incoming_uop_out_debug_fsrc = exe_req_0_bits_uop_debug_fsrc; // @[util.scala:96:23] wire [1:0] mem_incoming_uop_out_debug_tsrc = exe_req_0_bits_uop_debug_tsrc; // @[util.scala:96:23] wire [7:0] exe_req_0_bits_uop_br_mask; // @[lsu.scala:383:25] wire exe_req_0_bits_mxcpt_valid; // @[lsu.scala:383:25] wire [24:0] exe_req_0_bits_mxcpt_bits; // @[lsu.scala:383:25] wire exe_req_0_bits_sfence_bits_rs1; // @[lsu.scala:383:25] wire exe_req_0_bits_sfence_bits_rs2; // @[lsu.scala:383:25] wire [38:0] exe_req_0_bits_sfence_bits_addr; // @[lsu.scala:383:25] wire exe_req_0_bits_sfence_bits_asid; // @[lsu.scala:383:25] wire exe_req_0_bits_sfence_valid; // @[lsu.scala:383:25] wire [63:0] exe_req_0_bits_data; // @[lsu.scala:383:25] wire [39:0] exe_req_0_bits_addr; // @[lsu.scala:383:25] wire exe_req_0_valid; // @[lsu.scala:383:25] assign exe_req_0_bits_sfence_bits_asid = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_sfence_bits_asid_0 : _exe_req_WIRE_0_bits_sfence_bits_asid; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15] assign exe_req_0_bits_sfence_bits_addr = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_sfence_bits_addr_0 : _exe_req_WIRE_0_bits_sfence_bits_addr; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15] assign exe_req_0_bits_sfence_bits_rs2 = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_sfence_bits_rs2_0 : _exe_req_WIRE_0_bits_sfence_bits_rs2; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15] assign exe_req_0_bits_sfence_bits_rs1 = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_sfence_bits_rs1_0 : _exe_req_WIRE_0_bits_sfence_bits_rs1; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15] assign exe_req_0_bits_sfence_valid = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_sfence_valid_0 : _exe_req_WIRE_0_bits_sfence_valid; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15] assign exe_req_0_bits_mxcpt_bits = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_mxcpt_bits_0 : _exe_req_WIRE_0_bits_mxcpt_bits; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15] assign exe_req_0_bits_mxcpt_valid = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_mxcpt_valid_0 : _exe_req_WIRE_0_bits_mxcpt_valid; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15] assign exe_req_0_bits_addr = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_addr_0 : _exe_req_WIRE_0_bits_addr; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15] assign exe_req_0_bits_data = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_data_0 : _exe_req_WIRE_0_bits_data; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15] assign exe_req_0_bits_uop_debug_tsrc = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_uop_debug_tsrc_0 : _exe_req_WIRE_0_bits_uop_debug_tsrc; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15] assign exe_req_0_bits_uop_debug_fsrc = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_uop_debug_fsrc_0 : _exe_req_WIRE_0_bits_uop_debug_fsrc; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15] assign exe_req_0_bits_uop_bp_xcpt_if = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_uop_bp_xcpt_if_0 : _exe_req_WIRE_0_bits_uop_bp_xcpt_if; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15] assign exe_req_0_bits_uop_bp_debug_if = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_uop_bp_debug_if_0 : _exe_req_WIRE_0_bits_uop_bp_debug_if; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15] assign exe_req_0_bits_uop_xcpt_ma_if = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_uop_xcpt_ma_if_0 : _exe_req_WIRE_0_bits_uop_xcpt_ma_if; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15] assign exe_req_0_bits_uop_xcpt_ae_if = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_uop_xcpt_ae_if_0 : _exe_req_WIRE_0_bits_uop_xcpt_ae_if; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15] assign exe_req_0_bits_uop_xcpt_pf_if = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_uop_xcpt_pf_if_0 : _exe_req_WIRE_0_bits_uop_xcpt_pf_if; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15] assign exe_req_0_bits_uop_fp_single = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_uop_fp_single_0 : _exe_req_WIRE_0_bits_uop_fp_single; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15] assign exe_req_0_bits_uop_fp_val = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_uop_fp_val_0 : _exe_req_WIRE_0_bits_uop_fp_val; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15] assign exe_req_0_bits_uop_frs3_en = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_uop_frs3_en_0 : _exe_req_WIRE_0_bits_uop_frs3_en; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15] assign exe_req_0_bits_uop_lrs2_rtype = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_uop_lrs2_rtype_0 : _exe_req_WIRE_0_bits_uop_lrs2_rtype; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15] assign exe_req_0_bits_uop_lrs1_rtype = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_uop_lrs1_rtype_0 : _exe_req_WIRE_0_bits_uop_lrs1_rtype; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15] assign exe_req_0_bits_uop_dst_rtype = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_uop_dst_rtype_0 : _exe_req_WIRE_0_bits_uop_dst_rtype; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15] assign exe_req_0_bits_uop_ldst_val = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_uop_ldst_val_0 : _exe_req_WIRE_0_bits_uop_ldst_val; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15] assign exe_req_0_bits_uop_lrs3 = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_uop_lrs3_0 : _exe_req_WIRE_0_bits_uop_lrs3; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15] assign exe_req_0_bits_uop_lrs2 = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_uop_lrs2_0 : _exe_req_WIRE_0_bits_uop_lrs2; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15] assign exe_req_0_bits_uop_lrs1 = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_uop_lrs1_0 : _exe_req_WIRE_0_bits_uop_lrs1; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15] assign exe_req_0_bits_uop_ldst = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_uop_ldst_0 : _exe_req_WIRE_0_bits_uop_ldst; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15] assign exe_req_0_bits_uop_ldst_is_rs1 = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_uop_ldst_is_rs1_0 : _exe_req_WIRE_0_bits_uop_ldst_is_rs1; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15] assign exe_req_0_bits_uop_flush_on_commit = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_uop_flush_on_commit_0 : _exe_req_WIRE_0_bits_uop_flush_on_commit; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15] assign exe_req_0_bits_uop_is_unique = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_uop_is_unique_0 : _exe_req_WIRE_0_bits_uop_is_unique; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15] assign exe_req_0_bits_uop_is_sys_pc2epc = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_uop_is_sys_pc2epc_0 : _exe_req_WIRE_0_bits_uop_is_sys_pc2epc; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15] assign exe_req_0_bits_uop_uses_stq = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_uop_uses_stq_0 : _exe_req_WIRE_0_bits_uop_uses_stq; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15] assign exe_req_0_bits_uop_uses_ldq = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_uop_uses_ldq_0 : _exe_req_WIRE_0_bits_uop_uses_ldq; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15] assign exe_req_0_bits_uop_is_amo = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_uop_is_amo_0 : _exe_req_WIRE_0_bits_uop_is_amo; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15] assign exe_req_0_bits_uop_is_fencei = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_uop_is_fencei_0 : _exe_req_WIRE_0_bits_uop_is_fencei; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15] assign exe_req_0_bits_uop_is_fence = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_uop_is_fence_0 : _exe_req_WIRE_0_bits_uop_is_fence; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15] assign exe_req_0_bits_uop_mem_signed = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_uop_mem_signed_0 : _exe_req_WIRE_0_bits_uop_mem_signed; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15] assign exe_req_0_bits_uop_mem_size = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_uop_mem_size_0 : _exe_req_WIRE_0_bits_uop_mem_size; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15] assign exe_req_0_bits_uop_mem_cmd = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_uop_mem_cmd_0 : _exe_req_WIRE_0_bits_uop_mem_cmd; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15] assign exe_req_0_bits_uop_bypassable = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_uop_bypassable_0 : _exe_req_WIRE_0_bits_uop_bypassable; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15] assign exe_req_0_bits_uop_exc_cause = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_uop_exc_cause_0 : _exe_req_WIRE_0_bits_uop_exc_cause; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15] assign exe_req_0_bits_uop_exception = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_uop_exception_0 : _exe_req_WIRE_0_bits_uop_exception; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15] assign exe_req_0_bits_uop_stale_pdst = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_uop_stale_pdst_0 : _exe_req_WIRE_0_bits_uop_stale_pdst; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15] assign exe_req_0_bits_uop_ppred_busy = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_uop_ppred_busy_0 : _exe_req_WIRE_0_bits_uop_ppred_busy; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15] assign exe_req_0_bits_uop_prs3_busy = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_uop_prs3_busy_0 : _exe_req_WIRE_0_bits_uop_prs3_busy; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15] assign exe_req_0_bits_uop_prs2_busy = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_uop_prs2_busy_0 : _exe_req_WIRE_0_bits_uop_prs2_busy; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15] assign exe_req_0_bits_uop_prs1_busy = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_uop_prs1_busy_0 : _exe_req_WIRE_0_bits_uop_prs1_busy; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15] assign exe_req_0_bits_uop_ppred = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_uop_ppred_0 : _exe_req_WIRE_0_bits_uop_ppred; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15] assign exe_req_0_bits_uop_prs3 = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_uop_prs3_0 : _exe_req_WIRE_0_bits_uop_prs3; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15] assign exe_req_0_bits_uop_prs2 = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_uop_prs2_0 : _exe_req_WIRE_0_bits_uop_prs2; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15] assign exe_req_0_bits_uop_prs1 = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_uop_prs1_0 : _exe_req_WIRE_0_bits_uop_prs1; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15] assign exe_req_0_bits_uop_pdst = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_uop_pdst_0 : _exe_req_WIRE_0_bits_uop_pdst; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15] assign exe_req_0_bits_uop_rxq_idx = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_uop_rxq_idx_0 : _exe_req_WIRE_0_bits_uop_rxq_idx; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15] assign exe_req_0_bits_uop_stq_idx = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_uop_stq_idx_0 : _exe_req_WIRE_0_bits_uop_stq_idx; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15] assign exe_req_0_bits_uop_ldq_idx = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_uop_ldq_idx_0 : _exe_req_WIRE_0_bits_uop_ldq_idx; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15] assign exe_req_0_bits_uop_rob_idx = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_uop_rob_idx_0 : _exe_req_WIRE_0_bits_uop_rob_idx; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15] assign exe_req_0_bits_uop_csr_addr = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_uop_csr_addr_0 : _exe_req_WIRE_0_bits_uop_csr_addr; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15] assign exe_req_0_bits_uop_imm_packed = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_uop_imm_packed_0 : _exe_req_WIRE_0_bits_uop_imm_packed; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15] assign exe_req_0_bits_uop_taken = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_uop_taken_0 : _exe_req_WIRE_0_bits_uop_taken; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15] assign exe_req_0_bits_uop_pc_lob = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_uop_pc_lob_0 : _exe_req_WIRE_0_bits_uop_pc_lob; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15] assign exe_req_0_bits_uop_edge_inst = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_uop_edge_inst_0 : _exe_req_WIRE_0_bits_uop_edge_inst; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15] assign exe_req_0_bits_uop_ftq_idx = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_uop_ftq_idx_0 : _exe_req_WIRE_0_bits_uop_ftq_idx; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15] assign exe_req_0_bits_uop_br_tag = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_uop_br_tag_0 : _exe_req_WIRE_0_bits_uop_br_tag; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15] assign exe_req_0_bits_uop_br_mask = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_uop_br_mask_0 : _exe_req_WIRE_0_bits_uop_br_mask; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15] assign exe_req_0_bits_uop_is_sfb = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_uop_is_sfb_0 : _exe_req_WIRE_0_bits_uop_is_sfb; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15] assign exe_req_0_bits_uop_is_jal = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_uop_is_jal_0 : _exe_req_WIRE_0_bits_uop_is_jal; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15] assign exe_req_0_bits_uop_is_jalr = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_uop_is_jalr_0 : _exe_req_WIRE_0_bits_uop_is_jalr; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15] assign exe_req_0_bits_uop_is_br = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_uop_is_br_0 : _exe_req_WIRE_0_bits_uop_is_br; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15] assign exe_req_0_bits_uop_iw_p2_poisoned = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_uop_iw_p2_poisoned_0 : _exe_req_WIRE_0_bits_uop_iw_p2_poisoned; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15] assign exe_req_0_bits_uop_iw_p1_poisoned = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_uop_iw_p1_poisoned_0 : _exe_req_WIRE_0_bits_uop_iw_p1_poisoned; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15] assign exe_req_0_bits_uop_iw_state = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_uop_iw_state_0 : _exe_req_WIRE_0_bits_uop_iw_state; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15] assign exe_req_0_bits_uop_ctrl_is_std = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_uop_ctrl_is_std_0 : _exe_req_WIRE_0_bits_uop_ctrl_is_std; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15] assign exe_req_0_bits_uop_ctrl_is_sta = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_uop_ctrl_is_sta_0 : _exe_req_WIRE_0_bits_uop_ctrl_is_sta; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15] assign exe_req_0_bits_uop_ctrl_is_load = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_uop_ctrl_is_load_0 : _exe_req_WIRE_0_bits_uop_ctrl_is_load; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15] assign exe_req_0_bits_uop_ctrl_csr_cmd = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_uop_ctrl_csr_cmd_0 : _exe_req_WIRE_0_bits_uop_ctrl_csr_cmd; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15] assign exe_req_0_bits_uop_ctrl_fcn_dw = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_uop_ctrl_fcn_dw_0 : _exe_req_WIRE_0_bits_uop_ctrl_fcn_dw; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15] assign exe_req_0_bits_uop_ctrl_op_fcn = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_uop_ctrl_op_fcn_0 : _exe_req_WIRE_0_bits_uop_ctrl_op_fcn; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15] assign exe_req_0_bits_uop_ctrl_imm_sel = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_uop_ctrl_imm_sel_0 : _exe_req_WIRE_0_bits_uop_ctrl_imm_sel; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15] assign exe_req_0_bits_uop_ctrl_op2_sel = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_uop_ctrl_op2_sel_0 : _exe_req_WIRE_0_bits_uop_ctrl_op2_sel; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15] assign exe_req_0_bits_uop_ctrl_op1_sel = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_uop_ctrl_op1_sel_0 : _exe_req_WIRE_0_bits_uop_ctrl_op1_sel; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15] assign exe_req_0_bits_uop_ctrl_br_type = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_uop_ctrl_br_type_0 : _exe_req_WIRE_0_bits_uop_ctrl_br_type; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15] assign exe_req_0_bits_uop_fu_code = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_uop_fu_code_0 : _exe_req_WIRE_0_bits_uop_fu_code; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15] assign exe_req_0_bits_uop_iq_type = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_uop_iq_type_0 : _exe_req_WIRE_0_bits_uop_iq_type; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15] assign exe_req_0_bits_uop_debug_pc = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_uop_debug_pc_0 : _exe_req_WIRE_0_bits_uop_debug_pc; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15] assign exe_req_0_bits_uop_is_rvc = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_uop_is_rvc_0 : _exe_req_WIRE_0_bits_uop_is_rvc; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15] assign exe_req_0_bits_uop_debug_inst = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_uop_debug_inst_0 : _exe_req_WIRE_0_bits_uop_debug_inst; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15] assign exe_req_0_bits_uop_inst = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_uop_inst_0 : _exe_req_WIRE_0_bits_uop_inst; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15] assign exe_req_0_bits_uop_uopc = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_uop_uopc_0 : _exe_req_WIRE_0_bits_uop_uopc; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15] assign exe_req_0_valid = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_valid_0 : _exe_req_WIRE_0_valid; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15] wire block_load_mask_0; // @[lsu.scala:396:36] wire block_load_mask_1; // @[lsu.scala:396:36] wire block_load_mask_2; // @[lsu.scala:396:36] wire block_load_mask_3; // @[lsu.scala:396:36] wire block_load_mask_4; // @[lsu.scala:396:36] wire block_load_mask_5; // @[lsu.scala:396:36] wire block_load_mask_6; // @[lsu.scala:396:36] wire block_load_mask_7; // @[lsu.scala:396:36] reg p1_block_load_mask_0; // @[lsu.scala:397:35] reg p1_block_load_mask_1; // @[lsu.scala:397:35] reg p1_block_load_mask_2; // @[lsu.scala:397:35] reg p1_block_load_mask_3; // @[lsu.scala:397:35] reg p1_block_load_mask_4; // @[lsu.scala:397:35] reg p1_block_load_mask_5; // @[lsu.scala:397:35] reg p1_block_load_mask_6; // @[lsu.scala:397:35] reg p1_block_load_mask_7; // @[lsu.scala:397:35] reg p2_block_load_mask_0; // @[lsu.scala:398:35] reg p2_block_load_mask_1; // @[lsu.scala:398:35] reg p2_block_load_mask_2; // @[lsu.scala:398:35] reg p2_block_load_mask_3; // @[lsu.scala:398:35] reg p2_block_load_mask_4; // @[lsu.scala:398:35] reg p2_block_load_mask_5; // @[lsu.scala:398:35] reg p2_block_load_mask_6; // @[lsu.scala:398:35] reg p2_block_load_mask_7; // @[lsu.scala:398:35] wire [3:0] _GEN_93 = {1'h0, dis_st_val ? _T_39 : stq_tail} + 4'h1; // @[util.scala:203:14] wire [3:0] _stq_almost_full_T; // @[util.scala:203:14] assign _stq_almost_full_T = _GEN_93; // @[util.scala:203:14] wire [3:0] _stq_almost_full_T_7; // @[util.scala:203:14] assign _stq_almost_full_T_7 = _GEN_93; // @[util.scala:203:14] wire [2:0] _stq_almost_full_T_1 = _stq_almost_full_T[2:0]; // @[util.scala:203:14] wire [2:0] _stq_almost_full_T_2 = _stq_almost_full_T_1; // @[util.scala:203:{14,20}] wire [3:0] _stq_almost_full_T_3 = {1'h0, _stq_almost_full_T_2} + 4'h1; // @[util.scala:203:{14,20}] wire [2:0] _stq_almost_full_T_4 = _stq_almost_full_T_3[2:0]; // @[util.scala:203:14] wire [2:0] _stq_almost_full_T_5 = _stq_almost_full_T_4; // @[util.scala:203:{14,20}] wire _stq_almost_full_T_6 = _stq_almost_full_T_5 == stq_head; // @[util.scala:203:20] wire [2:0] _stq_almost_full_T_8 = _stq_almost_full_T_7[2:0]; // @[util.scala:203:14] wire [2:0] _stq_almost_full_T_9 = _stq_almost_full_T_8; // @[util.scala:203:{14,20}] wire _stq_almost_full_T_10 = _stq_almost_full_T_9 == stq_head; // @[util.scala:203:20] wire _stq_almost_full_T_11 = _stq_almost_full_T_6 \| _stq_almost_full_T_10; // @[lsu.scala:401:{92,105}, :402:68] reg stq_almost_full; // @[lsu.scala:401:32] wire store_needs_order; // @[lsu.scala:406:35] wire [6:0] mem_ldq_incoming_e_out_bits_uop_uopc = ldq_incoming_e_0_bits_uop_uopc; // @[util.scala:106:23] wire [31:0] mem_ldq_incoming_e_out_bits_uop_inst = ldq_incoming_e_0_bits_uop_inst; // @[util.scala:106:23] wire [31:0] mem_ldq_incoming_e_out_bits_uop_debug_inst = ldq_incoming_e_0_bits_uop_debug_inst; // @[util.scala:106:23] wire mem_ldq_incoming_e_out_bits_uop_is_rvc = ldq_incoming_e_0_bits_uop_is_rvc; // @[util.scala:106:23] wire [39:0] mem_ldq_incoming_e_out_bits_uop_debug_pc = ldq_incoming_e_0_bits_uop_debug_pc; // @[util.scala:106:23] wire [2:0] mem_ldq_incoming_e_out_bits_uop_iq_type = ldq_incoming_e_0_bits_uop_iq_type; // @[util.scala:106:23] wire [9:0] mem_ldq_incoming_e_out_bits_uop_fu_code = ldq_incoming_e_0_bits_uop_fu_code; // @[util.scala:106:23] wire [3:0] mem_ldq_incoming_e_out_bits_uop_ctrl_br_type = ldq_incoming_e_0_bits_uop_ctrl_br_type; // @[util.scala:106:23] wire [1:0] mem_ldq_incoming_e_out_bits_uop_ctrl_op1_sel = ldq_incoming_e_0_bits_uop_ctrl_op1_sel; // @[util.scala:106:23] wire [2:0] mem_ldq_incoming_e_out_bits_uop_ctrl_op2_sel = ldq_incoming_e_0_bits_uop_ctrl_op2_sel; // @[util.scala:106:23] wire [2:0] mem_ldq_incoming_e_out_bits_uop_ctrl_imm_sel = ldq_incoming_e_0_bits_uop_ctrl_imm_sel; // @[util.scala:106:23] wire [4:0] mem_ldq_incoming_e_out_bits_uop_ctrl_op_fcn = ldq_incoming_e_0_bits_uop_ctrl_op_fcn; // @[util.scala:106:23] wire mem_ldq_incoming_e_out_bits_uop_ctrl_fcn_dw = ldq_incoming_e_0_bits_uop_ctrl_fcn_dw; // @[util.scala:106:23] wire [2:0] mem_ldq_incoming_e_out_bits_uop_ctrl_csr_cmd = ldq_incoming_e_0_bits_uop_ctrl_csr_cmd; // @[util.scala:106:23] wire mem_ldq_incoming_e_out_bits_uop_ctrl_is_load = ldq_incoming_e_0_bits_uop_ctrl_is_load; // @[util.scala:106:23] wire mem_ldq_incoming_e_out_bits_uop_ctrl_is_sta = ldq_incoming_e_0_bits_uop_ctrl_is_sta; // @[util.scala:106:23] wire mem_ldq_incoming_e_out_bits_uop_ctrl_is_std = ldq_incoming_e_0_bits_uop_ctrl_is_std; // @[util.scala:106:23] wire [1:0] mem_ldq_incoming_e_out_bits_uop_iw_state = ldq_incoming_e_0_bits_uop_iw_state; // @[util.scala:106:23] wire mem_ldq_incoming_e_out_bits_uop_iw_p1_poisoned = ldq_incoming_e_0_bits_uop_iw_p1_poisoned; // @[util.scala:106:23] wire mem_ldq_incoming_e_out_bits_uop_iw_p2_poisoned = ldq_incoming_e_0_bits_uop_iw_p2_poisoned; // @[util.scala:106:23] wire mem_ldq_incoming_e_out_bits_uop_is_br = ldq_incoming_e_0_bits_uop_is_br; // @[util.scala:106:23] wire mem_ldq_incoming_e_out_bits_uop_is_jalr = ldq_incoming_e_0_bits_uop_is_jalr; // @[util.scala:106:23] wire mem_ldq_incoming_e_out_bits_uop_is_jal = ldq_incoming_e_0_bits_uop_is_jal; // @[util.scala:106:23] wire mem_ldq_incoming_e_out_bits_uop_is_sfb = ldq_incoming_e_0_bits_uop_is_sfb; // @[util.scala:106:23] wire [2:0] mem_ldq_incoming_e_out_bits_uop_br_tag = ldq_incoming_e_0_bits_uop_br_tag; // @[util.scala:106:23] wire [3:0] mem_ldq_incoming_e_out_bits_uop_ftq_idx = ldq_incoming_e_0_bits_uop_ftq_idx; // @[util.scala:106:23] wire mem_ldq_incoming_e_out_bits_uop_edge_inst = ldq_incoming_e_0_bits_uop_edge_inst; // @[util.scala:106:23] wire [5:0] mem_ldq_incoming_e_out_bits_uop_pc_lob = ldq_incoming_e_0_bits_uop_pc_lob; // @[util.scala:106:23] wire mem_ldq_incoming_e_out_bits_uop_taken = ldq_incoming_e_0_bits_uop_taken; // @[util.scala:106:23] wire [19:0] mem_ldq_incoming_e_out_bits_uop_imm_packed = ldq_incoming_e_0_bits_uop_imm_packed; // @[util.scala:106:23] wire [11:0] mem_ldq_incoming_e_out_bits_uop_csr_addr = ldq_incoming_e_0_bits_uop_csr_addr; // @[util.scala:106:23] wire [4:0] mem_ldq_incoming_e_out_bits_uop_rob_idx = ldq_incoming_e_0_bits_uop_rob_idx; // @[util.scala:106:23] wire [2:0] mem_ldq_incoming_e_out_bits_uop_ldq_idx = ldq_incoming_e_0_bits_uop_ldq_idx; // @[util.scala:106:23] wire [2:0] mem_ldq_incoming_e_out_bits_uop_stq_idx = ldq_incoming_e_0_bits_uop_stq_idx; // @[util.scala:106:23] wire [1:0] mem_ldq_incoming_e_out_bits_uop_rxq_idx = ldq_incoming_e_0_bits_uop_rxq_idx; // @[util.scala:106:23] wire [5:0] mem_ldq_incoming_e_out_bits_uop_pdst = ldq_incoming_e_0_bits_uop_pdst; // @[util.scala:106:23] wire [5:0] mem_ldq_incoming_e_out_bits_uop_prs1 = ldq_incoming_e_0_bits_uop_prs1; // @[util.scala:106:23] wire [5:0] mem_ldq_incoming_e_out_bits_uop_prs2 = ldq_incoming_e_0_bits_uop_prs2; // @[util.scala:106:23] wire [5:0] mem_ldq_incoming_e_out_bits_uop_prs3 = ldq_incoming_e_0_bits_uop_prs3; // @[util.scala:106:23] wire [3:0] mem_ldq_incoming_e_out_bits_uop_ppred = ldq_incoming_e_0_bits_uop_ppred; // @[util.scala:106:23] wire mem_ldq_incoming_e_out_bits_uop_prs1_busy = ldq_incoming_e_0_bits_uop_prs1_busy; // @[util.scala:106:23] wire mem_ldq_incoming_e_out_bits_uop_prs2_busy = ldq_incoming_e_0_bits_uop_prs2_busy; // @[util.scala:106:23] wire mem_ldq_incoming_e_out_bits_uop_prs3_busy = ldq_incoming_e_0_bits_uop_prs3_busy; // @[util.scala:106:23] wire mem_ldq_incoming_e_out_bits_uop_ppred_busy = ldq_incoming_e_0_bits_uop_ppred_busy; // @[util.scala:106:23] wire [5:0] mem_ldq_incoming_e_out_bits_uop_stale_pdst = ldq_incoming_e_0_bits_uop_stale_pdst; // @[util.scala:106:23] wire mem_ldq_incoming_e_out_bits_uop_exception = ldq_incoming_e_0_bits_uop_exception; // @[util.scala:106:23] wire [63:0] mem_ldq_incoming_e_out_bits_uop_exc_cause = ldq_incoming_e_0_bits_uop_exc_cause; // @[util.scala:106:23] wire mem_ldq_incoming_e_out_bits_uop_bypassable = ldq_incoming_e_0_bits_uop_bypassable; // @[util.scala:106:23] wire [4:0] mem_ldq_incoming_e_out_bits_uop_mem_cmd = ldq_incoming_e_0_bits_uop_mem_cmd; // @[util.scala:106:23] wire [1:0] mem_ldq_incoming_e_out_bits_uop_mem_size = ldq_incoming_e_0_bits_uop_mem_size; // @[util.scala:106:23] wire mem_ldq_incoming_e_out_bits_uop_mem_signed = ldq_incoming_e_0_bits_uop_mem_signed; // @[util.scala:106:23] wire mem_ldq_incoming_e_out_bits_uop_is_fence = ldq_incoming_e_0_bits_uop_is_fence; // @[util.scala:106:23] wire mem_ldq_incoming_e_out_bits_uop_is_fencei = ldq_incoming_e_0_bits_uop_is_fencei; // @[util.scala:106:23] wire mem_ldq_incoming_e_out_bits_uop_is_amo = ldq_incoming_e_0_bits_uop_is_amo; // @[util.scala:106:23] wire mem_ldq_incoming_e_out_bits_uop_uses_ldq = ldq_incoming_e_0_bits_uop_uses_ldq; // @[util.scala:106:23] wire mem_ldq_incoming_e_out_bits_uop_uses_stq = ldq_incoming_e_0_bits_uop_uses_stq; // @[util.scala:106:23] wire mem_ldq_incoming_e_out_bits_uop_is_sys_pc2epc = ldq_incoming_e_0_bits_uop_is_sys_pc2epc; // @[util.scala:106:23] wire mem_ldq_incoming_e_out_bits_uop_is_unique = ldq_incoming_e_0_bits_uop_is_unique; // @[util.scala:106:23] wire mem_ldq_incoming_e_out_bits_uop_flush_on_commit = ldq_incoming_e_0_bits_uop_flush_on_commit; // @[util.scala:106:23] wire mem_ldq_incoming_e_out_bits_uop_ldst_is_rs1 = ldq_incoming_e_0_bits_uop_ldst_is_rs1; // @[util.scala:106:23] wire [5:0] mem_ldq_incoming_e_out_bits_uop_ldst = ldq_incoming_e_0_bits_uop_ldst; // @[util.scala:106:23] wire [5:0] mem_ldq_incoming_e_out_bits_uop_lrs1 = ldq_incoming_e_0_bits_uop_lrs1; // @[util.scala:106:23] wire [5:0] mem_ldq_incoming_e_out_bits_uop_lrs2 = ldq_incoming_e_0_bits_uop_lrs2; // @[util.scala:106:23] wire [5:0] mem_ldq_incoming_e_out_bits_uop_lrs3 = ldq_incoming_e_0_bits_uop_lrs3; // @[util.scala:106:23] wire mem_ldq_incoming_e_out_bits_uop_ldst_val = ldq_incoming_e_0_bits_uop_ldst_val; // @[util.scala:106:23] wire [1:0] mem_ldq_incoming_e_out_bits_uop_dst_rtype = ldq_incoming_e_0_bits_uop_dst_rtype; // @[util.scala:106:23] wire [1:0] mem_ldq_incoming_e_out_bits_uop_lrs1_rtype = ldq_incoming_e_0_bits_uop_lrs1_rtype; // @[util.scala:106:23] wire [1:0] mem_ldq_incoming_e_out_bits_uop_lrs2_rtype = ldq_incoming_e_0_bits_uop_lrs2_rtype; // @[util.scala:106:23] wire mem_ldq_incoming_e_out_bits_uop_frs3_en = ldq_incoming_e_0_bits_uop_frs3_en; // @[util.scala:106:23] wire mem_ldq_incoming_e_out_bits_uop_fp_val = ldq_incoming_e_0_bits_uop_fp_val; // @[util.scala:106:23] wire mem_ldq_incoming_e_out_bits_uop_fp_single = ldq_incoming_e_0_bits_uop_fp_single; // @[util.scala:106:23] wire mem_ldq_incoming_e_out_bits_uop_xcpt_pf_if = ldq_incoming_e_0_bits_uop_xcpt_pf_if; // @[util.scala:106:23] wire mem_ldq_incoming_e_out_bits_uop_xcpt_ae_if = ldq_incoming_e_0_bits_uop_xcpt_ae_if; // @[util.scala:106:23] wire mem_ldq_incoming_e_out_bits_uop_xcpt_ma_if = ldq_incoming_e_0_bits_uop_xcpt_ma_if; // @[util.scala:106:23] wire mem_ldq_incoming_e_out_bits_uop_bp_debug_if = ldq_incoming_e_0_bits_uop_bp_debug_if; // @[util.scala:106:23] wire mem_ldq_incoming_e_out_bits_uop_bp_xcpt_if = ldq_incoming_e_0_bits_uop_bp_xcpt_if; // @[util.scala:106:23] wire [1:0] mem_ldq_incoming_e_out_bits_uop_debug_fsrc = ldq_incoming_e_0_bits_uop_debug_fsrc; // @[util.scala:106:23] wire [1:0] mem_ldq_incoming_e_out_bits_uop_debug_tsrc = ldq_incoming_e_0_bits_uop_debug_tsrc; // @[util.scala:106:23] wire mem_ldq_incoming_e_out_bits_addr_valid = ldq_incoming_e_0_bits_addr_valid; // @[util.scala:106:23] wire [39:0] mem_ldq_incoming_e_out_bits_addr_bits = ldq_incoming_e_0_bits_addr_bits; // @[util.scala:106:23] wire mem_ldq_incoming_e_out_bits_addr_is_virtual = ldq_incoming_e_0_bits_addr_is_virtual; // @[util.scala:106:23] wire mem_ldq_incoming_e_out_bits_addr_is_uncacheable = ldq_incoming_e_0_bits_addr_is_uncacheable; // @[util.scala:106:23] wire mem_ldq_incoming_e_out_bits_executed = ldq_incoming_e_0_bits_executed; // @[util.scala:106:23] wire mem_ldq_incoming_e_out_bits_succeeded = ldq_incoming_e_0_bits_succeeded; // @[util.scala:106:23] wire mem_ldq_incoming_e_out_bits_order_fail = ldq_incoming_e_0_bits_order_fail; // @[util.scala:106:23] wire mem_ldq_incoming_e_out_bits_observed = ldq_incoming_e_0_bits_observed; // @[util.scala:106:23] wire [7:0] mem_ldq_incoming_e_out_bits_st_dep_mask = ldq_incoming_e_0_bits_st_dep_mask; // @[util.scala:106:23] wire [2:0] mem_ldq_incoming_e_out_bits_youngest_stq_idx = ldq_incoming_e_0_bits_youngest_stq_idx; // @[util.scala:106:23] wire mem_ldq_incoming_e_out_bits_forward_std_val = ldq_incoming_e_0_bits_forward_std_val; // @[util.scala:106:23] wire [2:0] mem_ldq_incoming_e_out_bits_forward_stq_idx = ldq_incoming_e_0_bits_forward_stq_idx; // @[util.scala:106:23] wire [63:0] mem_ldq_incoming_e_out_bits_debug_wb_data = ldq_incoming_e_0_bits_debug_wb_data; // @[util.scala:106:23] wire [7:0] ldq_incoming_e_0_bits_uop_br_mask; // @[lsu.scala:263:49] wire ldq_incoming_e_0_valid; // @[lsu.scala:263:49] assign ldq_incoming_e_0_valid = _GEN_92[ldq_incoming_idx_0]; // @[lsu.scala:263:49, :304:44] wire [7:0][6:0] _GEN_94 = {{ldq_7_bits_uop_uopc}, {ldq_6_bits_uop_uopc}, {ldq_5_bits_uop_uopc}, {ldq_4_bits_uop_uopc}, {ldq_3_bits_uop_uopc}, {ldq_2_bits_uop_uopc}, {ldq_1_bits_uop_uopc}, {ldq_0_bits_uop_uopc}}; // @[lsu.scala:208:16, :263:49] assign ldq_incoming_e_0_bits_uop_uopc = _GEN_94[ldq_incoming_idx_0]; // @[lsu.scala:263:49] wire [7:0][31:0] _GEN_95 = {{ldq_7_bits_uop_inst}, {ldq_6_bits_uop_inst}, {ldq_5_bits_uop_inst}, {ldq_4_bits_uop_inst}, {ldq_3_bits_uop_inst}, {ldq_2_bits_uop_inst}, {ldq_1_bits_uop_inst}, {ldq_0_bits_uop_inst}}; // @[lsu.scala:208:16, :263:49] assign ldq_incoming_e_0_bits_uop_inst = _GEN_95[ldq_incoming_idx_0]; // @[lsu.scala:263:49] wire [7:0][31:0] _GEN_96 = {{ldq_7_bits_uop_debug_inst}, {ldq_6_bits_uop_debug_inst}, {ldq_5_bits_uop_debug_inst}, {ldq_4_bits_uop_debug_inst}, {ldq_3_bits_uop_debug_inst}, {ldq_2_bits_uop_debug_inst}, {ldq_1_bits_uop_debug_inst}, {ldq_0_bits_uop_debug_inst}}; // @[lsu.scala:208:16, :263:49] assign ldq_incoming_e_0_bits_uop_debug_inst = _GEN_96[ldq_incoming_idx_0]; // @[lsu.scala:263:49] wire [7:0] _GEN_97 = {{ldq_7_bits_uop_is_rvc}, {ldq_6_bits_uop_is_rvc}, {ldq_5_bits_uop_is_rvc}, {ldq_4_bits_uop_is_rvc}, {ldq_3_bits_uop_is_rvc}, {ldq_2_bits_uop_is_rvc}, {ldq_1_bits_uop_is_rvc}, {ldq_0_bits_uop_is_rvc}}; // @[lsu.scala:208:16, :263:49] assign ldq_incoming_e_0_bits_uop_is_rvc = _GEN_97[ldq_incoming_idx_0]; // @[lsu.scala:263:49] wire [7:0][39:0] _GEN_98 = {{ldq_7_bits_uop_debug_pc}, {ldq_6_bits_uop_debug_pc}, {ldq_5_bits_uop_debug_pc}, {ldq_4_bits_uop_debug_pc}, {ldq_3_bits_uop_debug_pc}, {ldq_2_bits_uop_debug_pc}, {ldq_1_bits_uop_debug_pc}, {ldq_0_bits_uop_debug_pc}}; // @[lsu.scala:208:16, :263:49] assign ldq_incoming_e_0_bits_uop_debug_pc = _GEN_98[ldq_incoming_idx_0]; // @[lsu.scala:263:49] wire [7:0][2:0] _GEN_99 = {{ldq_7_bits_uop_iq_type}, {ldq_6_bits_uop_iq_type}, {ldq_5_bits_uop_iq_type}, {ldq_4_bits_uop_iq_type}, {ldq_3_bits_uop_iq_type}, {ldq_2_bits_uop_iq_type}, {ldq_1_bits_uop_iq_type}, {ldq_0_bits_uop_iq_type}}; // @[lsu.scala:208:16, :263:49] assign ldq_incoming_e_0_bits_uop_iq_type = _GEN_99[ldq_incoming_idx_0]; // @[lsu.scala:263:49] wire [7:0][9:0] _GEN_100 = {{ldq_7_bits_uop_fu_code}, {ldq_6_bits_uop_fu_code}, {ldq_5_bits_uop_fu_code}, {ldq_4_bits_uop_fu_code}, {ldq_3_bits_uop_fu_code}, {ldq_2_bits_uop_fu_code}, {ldq_1_bits_uop_fu_code}, {ldq_0_bits_uop_fu_code}}; // @[lsu.scala:208:16, :263:49] assign ldq_incoming_e_0_bits_uop_fu_code = _GEN_100[ldq_incoming_idx_0]; // @[lsu.scala:263:49] wire [7:0][3:0] _GEN_101 = {{ldq_7_bits_uop_ctrl_br_type}, {ldq_6_bits_uop_ctrl_br_type}, {ldq_5_bits_uop_ctrl_br_type}, {ldq_4_bits_uop_ctrl_br_type}, {ldq_3_bits_uop_ctrl_br_type}, {ldq_2_bits_uop_ctrl_br_type}, {ldq_1_bits_uop_ctrl_br_type}, {ldq_0_bits_uop_ctrl_br_type}}; // @[lsu.scala:208:16, :263:49] assign ldq_incoming_e_0_bits_uop_ctrl_br_type = _GEN_101[ldq_incoming_idx_0]; // @[lsu.scala:263:49] wire [7:0][1:0] _GEN_102 = {{ldq_7_bits_uop_ctrl_op1_sel}, {ldq_6_bits_uop_ctrl_op1_sel}, {ldq_5_bits_uop_ctrl_op1_sel}, {ldq_4_bits_uop_ctrl_op1_sel}, {ldq_3_bits_uop_ctrl_op1_sel}, {ldq_2_bits_uop_ctrl_op1_sel}, {ldq_1_bits_uop_ctrl_op1_sel}, {ldq_0_bits_uop_ctrl_op1_sel}}; // @[lsu.scala:208:16, :263:49] assign ldq_incoming_e_0_bits_uop_ctrl_op1_sel = _GEN_102[ldq_incoming_idx_0]; // @[lsu.scala:263:49] wire [7:0][2:0] _GEN_103 = {{ldq_7_bits_uop_ctrl_op2_sel}, {ldq_6_bits_uop_ctrl_op2_sel}, {ldq_5_bits_uop_ctrl_op2_sel}, {ldq_4_bits_uop_ctrl_op2_sel}, {ldq_3_bits_uop_ctrl_op2_sel}, {ldq_2_bits_uop_ctrl_op2_sel}, {ldq_1_bits_uop_ctrl_op2_sel}, {ldq_0_bits_uop_ctrl_op2_sel}}; // @[lsu.scala:208:16, :263:49] assign ldq_incoming_e_0_bits_uop_ctrl_op2_sel = _GEN_103[ldq_incoming_idx_0]; // @[lsu.scala:263:49] wire [7:0][2:0] _GEN_104 = {{ldq_7_bits_uop_ctrl_imm_sel}, {ldq_6_bits_uop_ctrl_imm_sel}, {ldq_5_bits_uop_ctrl_imm_sel}, {ldq_4_bits_uop_ctrl_imm_sel}, {ldq_3_bits_uop_ctrl_imm_sel}, {ldq_2_bits_uop_ctrl_imm_sel}, {ldq_1_bits_uop_ctrl_imm_sel}, {ldq_0_bits_uop_ctrl_imm_sel}}; // @[lsu.scala:208:16, :263:49] assign ldq_incoming_e_0_bits_uop_ctrl_imm_sel = _GEN_104[ldq_incoming_idx_0]; // @[lsu.scala:263:49] wire [7:0][4:0] _GEN_105 = {{ldq_7_bits_uop_ctrl_op_fcn}, {ldq_6_bits_uop_ctrl_op_fcn}, {ldq_5_bits_uop_ctrl_op_fcn}, {ldq_4_bits_uop_ctrl_op_fcn}, {ldq_3_bits_uop_ctrl_op_fcn}, {ldq_2_bits_uop_ctrl_op_fcn}, {ldq_1_bits_uop_ctrl_op_fcn}, {ldq_0_bits_uop_ctrl_op_fcn}}; // @[lsu.scala:208:16, :263:49] assign ldq_incoming_e_0_bits_uop_ctrl_op_fcn = _GEN_105[ldq_incoming_idx_0]; // @[lsu.scala:263:49] wire [7:0] _GEN_106 = {{ldq_7_bits_uop_ctrl_fcn_dw}, {ldq_6_bits_uop_ctrl_fcn_dw}, {ldq_5_bits_uop_ctrl_fcn_dw}, {ldq_4_bits_uop_ctrl_fcn_dw}, {ldq_3_bits_uop_ctrl_fcn_dw}, {ldq_2_bits_uop_ctrl_fcn_dw}, {ldq_1_bits_uop_ctrl_fcn_dw}, {ldq_0_bits_uop_ctrl_fcn_dw}}; // @[lsu.scala:208:16, :263:49] assign ldq_incoming_e_0_bits_uop_ctrl_fcn_dw = _GEN_106[ldq_incoming_idx_0]; // @[lsu.scala:263:49] wire [7:0][2:0] _GEN_107 = {{ldq_7_bits_uop_ctrl_csr_cmd}, {ldq_6_bits_uop_ctrl_csr_cmd}, {ldq_5_bits_uop_ctrl_csr_cmd}, {ldq_4_bits_uop_ctrl_csr_cmd}, {ldq_3_bits_uop_ctrl_csr_cmd}, {ldq_2_bits_uop_ctrl_csr_cmd}, {ldq_1_bits_uop_ctrl_csr_cmd}, {ldq_0_bits_uop_ctrl_csr_cmd}}; // @[lsu.scala:208:16, :263:49] assign ldq_incoming_e_0_bits_uop_ctrl_csr_cmd = _GEN_107[ldq_incoming_idx_0]; // @[lsu.scala:263:49] wire [7:0] _GEN_108 = {{ldq_7_bits_uop_ctrl_is_load}, {ldq_6_bits_uop_ctrl_is_load}, {ldq_5_bits_uop_ctrl_is_load}, {ldq_4_bits_uop_ctrl_is_load}, {ldq_3_bits_uop_ctrl_is_load}, {ldq_2_bits_uop_ctrl_is_load}, {ldq_1_bits_uop_ctrl_is_load}, {ldq_0_bits_uop_ctrl_is_load}}; // @[lsu.scala:208:16, :263:49] assign ldq_incoming_e_0_bits_uop_ctrl_is_load = _GEN_108[ldq_incoming_idx_0]; // @[lsu.scala:263:49] wire [7:0] _GEN_109 = {{ldq_7_bits_uop_ctrl_is_sta}, {ldq_6_bits_uop_ctrl_is_sta}, {ldq_5_bits_uop_ctrl_is_sta}, {ldq_4_bits_uop_ctrl_is_sta}, {ldq_3_bits_uop_ctrl_is_sta}, {ldq_2_bits_uop_ctrl_is_sta}, {ldq_1_bits_uop_ctrl_is_sta}, {ldq_0_bits_uop_ctrl_is_sta}}; // @[lsu.scala:208:16, :263:49] assign ldq_incoming_e_0_bits_uop_ctrl_is_sta = _GEN_109[ldq_incoming_idx_0]; // @[lsu.scala:263:49] wire [7:0] _GEN_110 = {{ldq_7_bits_uop_ctrl_is_std}, {ldq_6_bits_uop_ctrl_is_std}, {ldq_5_bits_uop_ctrl_is_std}, {ldq_4_bits_uop_ctrl_is_std}, {ldq_3_bits_uop_ctrl_is_std}, {ldq_2_bits_uop_ctrl_is_std}, {ldq_1_bits_uop_ctrl_is_std}, {ldq_0_bits_uop_ctrl_is_std}}; // @[lsu.scala:208:16, :263:49] assign ldq_incoming_e_0_bits_uop_ctrl_is_std = _GEN_110[ldq_incoming_idx_0]; // @[lsu.scala:263:49] wire [7:0][1:0] _GEN_111 = {{ldq_7_bits_uop_iw_state}, {ldq_6_bits_uop_iw_state}, {ldq_5_bits_uop_iw_state}, {ldq_4_bits_uop_iw_state}, {ldq_3_bits_uop_iw_state}, {ldq_2_bits_uop_iw_state}, {ldq_1_bits_uop_iw_state}, {ldq_0_bits_uop_iw_state}}; // @[lsu.scala:208:16, :263:49] assign ldq_incoming_e_0_bits_uop_iw_state = _GEN_111[ldq_incoming_idx_0]; // @[lsu.scala:263:49] wire [7:0] _GEN_112 = {{ldq_7_bits_uop_iw_p1_poisoned}, {ldq_6_bits_uop_iw_p1_poisoned}, {ldq_5_bits_uop_iw_p1_poisoned}, {ldq_4_bits_uop_iw_p1_poisoned}, {ldq_3_bits_uop_iw_p1_poisoned}, {ldq_2_bits_uop_iw_p1_poisoned}, {ldq_1_bits_uop_iw_p1_poisoned}, {ldq_0_bits_uop_iw_p1_poisoned}}; // @[lsu.scala:208:16, :263:49] assign ldq_incoming_e_0_bits_uop_iw_p1_poisoned = _GEN_112[ldq_incoming_idx_0]; // @[lsu.scala:263:49] wire [7:0] _GEN_113 = {{ldq_7_bits_uop_iw_p2_poisoned}, {ldq_6_bits_uop_iw_p2_poisoned}, {ldq_5_bits_uop_iw_p2_poisoned}, {ldq_4_bits_uop_iw_p2_poisoned}, {ldq_3_bits_uop_iw_p2_poisoned}, {ldq_2_bits_uop_iw_p2_poisoned}, {ldq_1_bits_uop_iw_p2_poisoned}, {ldq_0_bits_uop_iw_p2_poisoned}}; // @[lsu.scala:208:16, :263:49] assign ldq_incoming_e_0_bits_uop_iw_p2_poisoned = _GEN_113[ldq_incoming_idx_0]; // @[lsu.scala:263:49] wire [7:0] _GEN_114 = {{ldq_7_bits_uop_is_br}, {ldq_6_bits_uop_is_br}, {ldq_5_bits_uop_is_br}, {ldq_4_bits_uop_is_br}, {ldq_3_bits_uop_is_br}, {ldq_2_bits_uop_is_br}, {ldq_1_bits_uop_is_br}, {ldq_0_bits_uop_is_br}}; // @[lsu.scala:208:16, :263:49] assign ldq_incoming_e_0_bits_uop_is_br = _GEN_114[ldq_incoming_idx_0]; // @[lsu.scala:263:49] wire [7:0] _GEN_115 = {{ldq_7_bits_uop_is_jalr}, {ldq_6_bits_uop_is_jalr}, {ldq_5_bits_uop_is_jalr}, {ldq_4_bits_uop_is_jalr}, {ldq_3_bits_uop_is_jalr}, {ldq_2_bits_uop_is_jalr}, {ldq_1_bits_uop_is_jalr}, {ldq_0_bits_uop_is_jalr}}; // @[lsu.scala:208:16, :263:49] assign ldq_incoming_e_0_bits_uop_is_jalr = _GEN_115[ldq_incoming_idx_0]; // @[lsu.scala:263:49] wire [7:0] _GEN_116 = {{ldq_7_bits_uop_is_jal}, {ldq_6_bits_uop_is_jal}, {ldq_5_bits_uop_is_jal}, {ldq_4_bits_uop_is_jal}, {ldq_3_bits_uop_is_jal}, {ldq_2_bits_uop_is_jal}, {ldq_1_bits_uop_is_jal}, {ldq_0_bits_uop_is_jal}}; // @[lsu.scala:208:16, :263:49] assign ldq_incoming_e_0_bits_uop_is_jal = _GEN_116[ldq_incoming_idx_0]; // @[lsu.scala:263:49] wire [7:0] _GEN_117 = {{ldq_7_bits_uop_is_sfb}, {ldq_6_bits_uop_is_sfb}, {ldq_5_bits_uop_is_sfb}, {ldq_4_bits_uop_is_sfb}, {ldq_3_bits_uop_is_sfb}, {ldq_2_bits_uop_is_sfb}, {ldq_1_bits_uop_is_sfb}, {ldq_0_bits_uop_is_sfb}}; // @[lsu.scala:208:16, :263:49] assign ldq_incoming_e_0_bits_uop_is_sfb = _GEN_117[ldq_incoming_idx_0]; // @[lsu.scala:263:49] wire [7:0][7:0] _GEN_118 = {{ldq_7_bits_uop_br_mask}, {ldq_6_bits_uop_br_mask}, {ldq_5_bits_uop_br_mask}, {ldq_4_bits_uop_br_mask}, {ldq_3_bits_uop_br_mask}, {ldq_2_bits_uop_br_mask}, {ldq_1_bits_uop_br_mask}, {ldq_0_bits_uop_br_mask}}; // @[lsu.scala:208:16, :263:49] assign ldq_incoming_e_0_bits_uop_br_mask = _GEN_118[ldq_incoming_idx_0]; // @[lsu.scala:263:49] wire [7:0][2:0] _GEN_119 = {{ldq_7_bits_uop_br_tag}, {ldq_6_bits_uop_br_tag}, {ldq_5_bits_uop_br_tag}, {ldq_4_bits_uop_br_tag}, {ldq_3_bits_uop_br_tag}, {ldq_2_bits_uop_br_tag}, {ldq_1_bits_uop_br_tag}, {ldq_0_bits_uop_br_tag}}; // @[lsu.scala:208:16, :263:49] assign ldq_incoming_e_0_bits_uop_br_tag = _GEN_119[ldq_incoming_idx_0]; // @[lsu.scala:263:49] wire [7:0][3:0] _GEN_120 = {{ldq_7_bits_uop_ftq_idx}, {ldq_6_bits_uop_ftq_idx}, {ldq_5_bits_uop_ftq_idx}, {ldq_4_bits_uop_ftq_idx}, {ldq_3_bits_uop_ftq_idx}, {ldq_2_bits_uop_ftq_idx}, {ldq_1_bits_uop_ftq_idx}, {ldq_0_bits_uop_ftq_idx}}; // @[lsu.scala:208:16, :263:49] assign ldq_incoming_e_0_bits_uop_ftq_idx = _GEN_120[ldq_incoming_idx_0]; // @[lsu.scala:263:49] wire [7:0] _GEN_121 = {{ldq_7_bits_uop_edge_inst}, {ldq_6_bits_uop_edge_inst}, {ldq_5_bits_uop_edge_inst}, {ldq_4_bits_uop_edge_inst}, {ldq_3_bits_uop_edge_inst}, {ldq_2_bits_uop_edge_inst}, {ldq_1_bits_uop_edge_inst}, {ldq_0_bits_uop_edge_inst}}; // @[lsu.scala:208:16, :263:49] assign ldq_incoming_e_0_bits_uop_edge_inst = _GEN_121[ldq_incoming_idx_0]; // @[lsu.scala:263:49] wire [7:0][5:0] _GEN_122 = {{ldq_7_bits_uop_pc_lob}, {ldq_6_bits_uop_pc_lob}, {ldq_5_bits_uop_pc_lob}, {ldq_4_bits_uop_pc_lob}, {ldq_3_bits_uop_pc_lob}, {ldq_2_bits_uop_pc_lob}, {ldq_1_bits_uop_pc_lob}, {ldq_0_bits_uop_pc_lob}}; // @[lsu.scala:208:16, :263:49] assign ldq_incoming_e_0_bits_uop_pc_lob = _GEN_122[ldq_incoming_idx_0]; // @[lsu.scala:263:49] wire [7:0] _GEN_123 = {{ldq_7_bits_uop_taken}, {ldq_6_bits_uop_taken}, {ldq_5_bits_uop_taken}, {ldq_4_bits_uop_taken}, {ldq_3_bits_uop_taken}, {ldq_2_bits_uop_taken}, {ldq_1_bits_uop_taken}, {ldq_0_bits_uop_taken}}; // @[lsu.scala:208:16, :263:49] assign ldq_incoming_e_0_bits_uop_taken = _GEN_123[ldq_incoming_idx_0]; // @[lsu.scala:263:49] wire [7:0][19:0] _GEN_124 = {{ldq_7_bits_uop_imm_packed}, {ldq_6_bits_uop_imm_packed}, {ldq_5_bits_uop_imm_packed}, {ldq_4_bits_uop_imm_packed}, {ldq_3_bits_uop_imm_packed}, {ldq_2_bits_uop_imm_packed}, {ldq_1_bits_uop_imm_packed}, {ldq_0_bits_uop_imm_packed}}; // @[lsu.scala:208:16, :263:49] assign ldq_incoming_e_0_bits_uop_imm_packed = _GEN_124[ldq_incoming_idx_0]; // @[lsu.scala:263:49] wire [7:0][11:0] _GEN_125 = {{ldq_7_bits_uop_csr_addr}, {ldq_6_bits_uop_csr_addr}, {ldq_5_bits_uop_csr_addr}, {ldq_4_bits_uop_csr_addr}, {ldq_3_bits_uop_csr_addr}, {ldq_2_bits_uop_csr_addr}, {ldq_1_bits_uop_csr_addr}, {ldq_0_bits_uop_csr_addr}}; // @[lsu.scala:208:16, :263:49] assign ldq_incoming_e_0_bits_uop_csr_addr = _GEN_125[ldq_incoming_idx_0]; // @[lsu.scala:263:49] wire [7:0][4:0] _GEN_126 = {{ldq_7_bits_uop_rob_idx}, {ldq_6_bits_uop_rob_idx}, {ldq_5_bits_uop_rob_idx}, {ldq_4_bits_uop_rob_idx}, {ldq_3_bits_uop_rob_idx}, {ldq_2_bits_uop_rob_idx}, {ldq_1_bits_uop_rob_idx}, {ldq_0_bits_uop_rob_idx}}; // @[lsu.scala:208:16, :263:49] assign ldq_incoming_e_0_bits_uop_rob_idx = _GEN_126[ldq_incoming_idx_0]; // @[lsu.scala:263:49] wire [7:0][2:0] _GEN_127 = {{ldq_7_bits_uop_ldq_idx}, {ldq_6_bits_uop_ldq_idx}, {ldq_5_bits_uop_ldq_idx}, {ldq_4_bits_uop_ldq_idx}, {ldq_3_bits_uop_ldq_idx}, {ldq_2_bits_uop_ldq_idx}, {ldq_1_bits_uop_ldq_idx}, {ldq_0_bits_uop_ldq_idx}}; // @[lsu.scala:208:16, :263:49] assign ldq_incoming_e_0_bits_uop_ldq_idx = _GEN_127[ldq_incoming_idx_0]; // @[lsu.scala:263:49] wire [7:0][2:0] _GEN_128 = {{ldq_7_bits_uop_stq_idx}, {ldq_6_bits_uop_stq_idx}, {ldq_5_bits_uop_stq_idx}, {ldq_4_bits_uop_stq_idx}, {ldq_3_bits_uop_stq_idx}, {ldq_2_bits_uop_stq_idx}, {ldq_1_bits_uop_stq_idx}, {ldq_0_bits_uop_stq_idx}}; // @[lsu.scala:208:16, :263:49] assign ldq_incoming_e_0_bits_uop_stq_idx = _GEN_128[ldq_incoming_idx_0]; // @[lsu.scala:263:49] wire [7:0][1:0] _GEN_129 = {{ldq_7_bits_uop_rxq_idx}, {ldq_6_bits_uop_rxq_idx}, {ldq_5_bits_uop_rxq_idx}, {ldq_4_bits_uop_rxq_idx}, {ldq_3_bits_uop_rxq_idx}, {ldq_2_bits_uop_rxq_idx}, {ldq_1_bits_uop_rxq_idx}, {ldq_0_bits_uop_rxq_idx}}; // @[lsu.scala:208:16, :263:49] assign ldq_incoming_e_0_bits_uop_rxq_idx = _GEN_129[ldq_incoming_idx_0]; // @[lsu.scala:263:49] wire [7:0][5:0] _GEN_130 = {{ldq_7_bits_uop_pdst}, {ldq_6_bits_uop_pdst}, {ldq_5_bits_uop_pdst}, {ldq_4_bits_uop_pdst}, {ldq_3_bits_uop_pdst}, {ldq_2_bits_uop_pdst}, {ldq_1_bits_uop_pdst}, {ldq_0_bits_uop_pdst}}; // @[lsu.scala:208:16, :263:49] assign ldq_incoming_e_0_bits_uop_pdst = _GEN_130[ldq_incoming_idx_0]; // @[lsu.scala:263:49] wire [7:0][5:0] _GEN_131 = {{ldq_7_bits_uop_prs1}, {ldq_6_bits_uop_prs1}, {ldq_5_bits_uop_prs1}, {ldq_4_bits_uop_prs1}, {ldq_3_bits_uop_prs1}, {ldq_2_bits_uop_prs1}, {ldq_1_bits_uop_prs1}, {ldq_0_bits_uop_prs1}}; // @[lsu.scala:208:16, :263:49] assign ldq_incoming_e_0_bits_uop_prs1 = _GEN_131[ldq_incoming_idx_0]; // @[lsu.scala:263:49] wire [7:0][5:0] _GEN_132 = {{ldq_7_bits_uop_prs2}, {ldq_6_bits_uop_prs2}, {ldq_5_bits_uop_prs2}, {ldq_4_bits_uop_prs2}, {ldq_3_bits_uop_prs2}, {ldq_2_bits_uop_prs2}, {ldq_1_bits_uop_prs2}, {ldq_0_bits_uop_prs2}}; // @[lsu.scala:208:16, :263:49] assign ldq_incoming_e_0_bits_uop_prs2 = _GEN_132[ldq_incoming_idx_0]; // @[lsu.scala:263:49] wire [7:0][5:0] _GEN_133 = {{ldq_7_bits_uop_prs3}, {ldq_6_bits_uop_prs3}, {ldq_5_bits_uop_prs3}, {ldq_4_bits_uop_prs3}, {ldq_3_bits_uop_prs3}, {ldq_2_bits_uop_prs3}, {ldq_1_bits_uop_prs3}, {ldq_0_bits_uop_prs3}}; // @[lsu.scala:208:16, :263:49] assign ldq_incoming_e_0_bits_uop_prs3 = _GEN_133[ldq_incoming_idx_0]; // @[lsu.scala:263:49] wire [7:0] _GEN_134 = {{ldq_7_bits_uop_prs1_busy}, {ldq_6_bits_uop_prs1_busy}, {ldq_5_bits_uop_prs1_busy}, {ldq_4_bits_uop_prs1_busy}, {ldq_3_bits_uop_prs1_busy}, {ldq_2_bits_uop_prs1_busy}, {ldq_1_bits_uop_prs1_busy}, {ldq_0_bits_uop_prs1_busy}}; // @[lsu.scala:208:16, :263:49] assign ldq_incoming_e_0_bits_uop_prs1_busy = _GEN_134[ldq_incoming_idx_0]; // @[lsu.scala:263:49] wire [7:0] _GEN_135 = {{ldq_7_bits_uop_prs2_busy}, {ldq_6_bits_uop_prs2_busy}, {ldq_5_bits_uop_prs2_busy}, {ldq_4_bits_uop_prs2_busy}, {ldq_3_bits_uop_prs2_busy}, {ldq_2_bits_uop_prs2_busy}, {ldq_1_bits_uop_prs2_busy}, {ldq_0_bits_uop_prs2_busy}}; // @[lsu.scala:208:16, :263:49] assign ldq_incoming_e_0_bits_uop_prs2_busy = _GEN_135[ldq_incoming_idx_0]; // @[lsu.scala:263:49] wire [7:0] _GEN_136 = {{ldq_7_bits_uop_prs3_busy}, {ldq_6_bits_uop_prs3_busy}, {ldq_5_bits_uop_prs3_busy}, {ldq_4_bits_uop_prs3_busy}, {ldq_3_bits_uop_prs3_busy}, {ldq_2_bits_uop_prs3_busy}, {ldq_1_bits_uop_prs3_busy}, {ldq_0_bits_uop_prs3_busy}}; // @[lsu.scala:208:16, :263:49] assign ldq_incoming_e_0_bits_uop_prs3_busy = _GEN_136[ldq_incoming_idx_0]; // @[lsu.scala:263:49] wire [7:0][5:0] _GEN_137 = {{ldq_7_bits_uop_stale_pdst}, {ldq_6_bits_uop_stale_pdst}, {ldq_5_bits_uop_stale_pdst}, {ldq_4_bits_uop_stale_pdst}, {ldq_3_bits_uop_stale_pdst}, {ldq_2_bits_uop_stale_pdst}, {ldq_1_bits_uop_stale_pdst}, {ldq_0_bits_uop_stale_pdst}}; // @[lsu.scala:208:16, :263:49] assign ldq_incoming_e_0_bits_uop_stale_pdst = _GEN_137[ldq_incoming_idx_0]; // @[lsu.scala:263:49] wire [7:0] _GEN_138 = {{ldq_7_bits_uop_exception}, {ldq_6_bits_uop_exception}, {ldq_5_bits_uop_exception}, {ldq_4_bits_uop_exception}, {ldq_3_bits_uop_exception}, {ldq_2_bits_uop_exception}, {ldq_1_bits_uop_exception}, {ldq_0_bits_uop_exception}}; // @[lsu.scala:208:16, :263:49] assign ldq_incoming_e_0_bits_uop_exception = _GEN_138[ldq_incoming_idx_0]; // @[lsu.scala:263:49] wire [7:0][63:0] _GEN_139 = {{ldq_7_bits_uop_exc_cause}, {ldq_6_bits_uop_exc_cause}, {ldq_5_bits_uop_exc_cause}, {ldq_4_bits_uop_exc_cause}, {ldq_3_bits_uop_exc_cause}, {ldq_2_bits_uop_exc_cause}, {ldq_1_bits_uop_exc_cause}, {ldq_0_bits_uop_exc_cause}}; // @[lsu.scala:208:16, :263:49] assign ldq_incoming_e_0_bits_uop_exc_cause = _GEN_139[ldq_incoming_idx_0]; // @[lsu.scala:263:49] wire [7:0] _GEN_140 = {{ldq_7_bits_uop_bypassable}, {ldq_6_bits_uop_bypassable}, {ldq_5_bits_uop_bypassable}, {ldq_4_bits_uop_bypassable}, {ldq_3_bits_uop_bypassable}, {ldq_2_bits_uop_bypassable}, {ldq_1_bits_uop_bypassable}, {ldq_0_bits_uop_bypassable}}; // @[lsu.scala:208:16, :263:49] assign ldq_incoming_e_0_bits_uop_bypassable = _GEN_140[ldq_incoming_idx_0]; // @[lsu.scala:263:49] wire [7:0][4:0] _GEN_141 = {{ldq_7_bits_uop_mem_cmd}, {ldq_6_bits_uop_mem_cmd}, {ldq_5_bits_uop_mem_cmd}, {ldq_4_bits_uop_mem_cmd}, {ldq_3_bits_uop_mem_cmd}, {ldq_2_bits_uop_mem_cmd}, {ldq_1_bits_uop_mem_cmd}, {ldq_0_bits_uop_mem_cmd}}; // @[lsu.scala:208:16, :263:49] assign ldq_incoming_e_0_bits_uop_mem_cmd = _GEN_141[ldq_incoming_idx_0]; // @[lsu.scala:263:49] wire [7:0][1:0] _GEN_142 = {{ldq_7_bits_uop_mem_size}, {ldq_6_bits_uop_mem_size}, {ldq_5_bits_uop_mem_size}, {ldq_4_bits_uop_mem_size}, {ldq_3_bits_uop_mem_size}, {ldq_2_bits_uop_mem_size}, {ldq_1_bits_uop_mem_size}, {ldq_0_bits_uop_mem_size}}; // @[lsu.scala:208:16, :263:49] assign ldq_incoming_e_0_bits_uop_mem_size = _GEN_142[ldq_incoming_idx_0]; // @[lsu.scala:263:49] wire [7:0] _GEN_143 = {{ldq_7_bits_uop_mem_signed}, {ldq_6_bits_uop_mem_signed}, {ldq_5_bits_uop_mem_signed}, {ldq_4_bits_uop_mem_signed}, {ldq_3_bits_uop_mem_signed}, {ldq_2_bits_uop_mem_signed}, {ldq_1_bits_uop_mem_signed}, {ldq_0_bits_uop_mem_signed}}; // @[lsu.scala:208:16, :263:49] assign ldq_incoming_e_0_bits_uop_mem_signed = _GEN_143[ldq_incoming_idx_0]; // @[lsu.scala:263:49] wire [7:0] _GEN_144 = {{ldq_7_bits_uop_is_fence}, {ldq_6_bits_uop_is_fence}, {ldq_5_bits_uop_is_fence}, {ldq_4_bits_uop_is_fence}, {ldq_3_bits_uop_is_fence}, {ldq_2_bits_uop_is_fence}, {ldq_1_bits_uop_is_fence}, {ldq_0_bits_uop_is_fence}}; // @[lsu.scala:208:16, :263:49] assign ldq_incoming_e_0_bits_uop_is_fence = _GEN_144[ldq_incoming_idx_0]; // @[lsu.scala:263:49] wire [7:0] _GEN_145 = {{ldq_7_bits_uop_is_fencei}, {ldq_6_bits_uop_is_fencei}, {ldq_5_bits_uop_is_fencei}, {ldq_4_bits_uop_is_fencei}, {ldq_3_bits_uop_is_fencei}, {ldq_2_bits_uop_is_fencei}, {ldq_1_bits_uop_is_fencei}, {ldq_0_bits_uop_is_fencei}}; // @[lsu.scala:208:16, :263:49] assign ldq_incoming_e_0_bits_uop_is_fencei = _GEN_145[ldq_incoming_idx_0]; // @[lsu.scala:263:49] wire [7:0] _GEN_146 = {{ldq_7_bits_uop_is_amo}, {ldq_6_bits_uop_is_amo}, {ldq_5_bits_uop_is_amo}, {ldq_4_bits_uop_is_amo}, {ldq_3_bits_uop_is_amo}, {ldq_2_bits_uop_is_amo}, {ldq_1_bits_uop_is_amo}, {ldq_0_bits_uop_is_amo}}; // @[lsu.scala:208:16, :263:49] assign ldq_incoming_e_0_bits_uop_is_amo = _GEN_146[ldq_incoming_idx_0]; // @[lsu.scala:263:49] wire [7:0] _GEN_147 = {{ldq_7_bits_uop_uses_ldq}, {ldq_6_bits_uop_uses_ldq}, {ldq_5_bits_uop_uses_ldq}, {ldq_4_bits_uop_uses_ldq}, {ldq_3_bits_uop_uses_ldq}, {ldq_2_bits_uop_uses_ldq}, {ldq_1_bits_uop_uses_ldq}, {ldq_0_bits_uop_uses_ldq}}; // @[lsu.scala:208:16, :263:49] assign ldq_incoming_e_0_bits_uop_uses_ldq = _GEN_147[ldq_incoming_idx_0]; // @[lsu.scala:263:49] wire [7:0] _GEN_148 = {{ldq_7_bits_uop_uses_stq}, {ldq_6_bits_uop_uses_stq}, {ldq_5_bits_uop_uses_stq}, {ldq_4_bits_uop_uses_stq}, {ldq_3_bits_uop_uses_stq}, {ldq_2_bits_uop_uses_stq}, {ldq_1_bits_uop_uses_stq}, {ldq_0_bits_uop_uses_stq}}; // @[lsu.scala:208:16, :263:49] assign ldq_incoming_e_0_bits_uop_uses_stq = _GEN_148[ldq_incoming_idx_0]; // @[lsu.scala:263:49] wire [7:0] _GEN_149 = {{ldq_7_bits_uop_is_sys_pc2epc}, {ldq_6_bits_uop_is_sys_pc2epc}, {ldq_5_bits_uop_is_sys_pc2epc}, {ldq_4_bits_uop_is_sys_pc2epc}, {ldq_3_bits_uop_is_sys_pc2epc}, {ldq_2_bits_uop_is_sys_pc2epc}, {ldq_1_bits_uop_is_sys_pc2epc}, {ldq_0_bits_uop_is_sys_pc2epc}}; // @[lsu.scala:208:16, :263:49] assign ldq_incoming_e_0_bits_uop_is_sys_pc2epc = _GEN_149[ldq_incoming_idx_0]; // @[lsu.scala:263:49] wire [7:0] _GEN_150 = {{ldq_7_bits_uop_is_unique}, {ldq_6_bits_uop_is_unique}, {ldq_5_bits_uop_is_unique}, {ldq_4_bits_uop_is_unique}, {ldq_3_bits_uop_is_unique}, {ldq_2_bits_uop_is_unique}, {ldq_1_bits_uop_is_unique}, {ldq_0_bits_uop_is_unique}}; // @[lsu.scala:208:16, :263:49] assign ldq_incoming_e_0_bits_uop_is_unique = _GEN_150[ldq_incoming_idx_0]; // @[lsu.scala:263:49] wire [7:0] _GEN_151 = {{ldq_7_bits_uop_flush_on_commit}, {ldq_6_bits_uop_flush_on_commit}, {ldq_5_bits_uop_flush_on_commit}, {ldq_4_bits_uop_flush_on_commit}, {ldq_3_bits_uop_flush_on_commit}, {ldq_2_bits_uop_flush_on_commit}, {ldq_1_bits_uop_flush_on_commit}, {ldq_0_bits_uop_flush_on_commit}}; // @[lsu.scala:208:16, :263:49] assign ldq_incoming_e_0_bits_uop_flush_on_commit = _GEN_151[ldq_incoming_idx_0]; // @[lsu.scala:263:49] wire [7:0] _GEN_152 = {{ldq_7_bits_uop_ldst_is_rs1}, {ldq_6_bits_uop_ldst_is_rs1}, {ldq_5_bits_uop_ldst_is_rs1}, {ldq_4_bits_uop_ldst_is_rs1}, {ldq_3_bits_uop_ldst_is_rs1}, {ldq_2_bits_uop_ldst_is_rs1}, {ldq_1_bits_uop_ldst_is_rs1}, {ldq_0_bits_uop_ldst_is_rs1}}; // @[lsu.scala:208:16, :263:49] assign ldq_incoming_e_0_bits_uop_ldst_is_rs1 = _GEN_152[ldq_incoming_idx_0]; // @[lsu.scala:263:49] wire [7:0][5:0] _GEN_153 = {{ldq_7_bits_uop_ldst}, {ldq_6_bits_uop_ldst}, {ldq_5_bits_uop_ldst}, {ldq_4_bits_uop_ldst}, {ldq_3_bits_uop_ldst}, {ldq_2_bits_uop_ldst}, {ldq_1_bits_uop_ldst}, {ldq_0_bits_uop_ldst}}; // @[lsu.scala:208:16, :263:49] assign ldq_incoming_e_0_bits_uop_ldst = _GEN_153[ldq_incoming_idx_0]; // @[lsu.scala:263:49] wire [7:0][5:0] _GEN_154 = {{ldq_7_bits_uop_lrs1}, {ldq_6_bits_uop_lrs1}, {ldq_5_bits_uop_lrs1}, {ldq_4_bits_uop_lrs1}, {ldq_3_bits_uop_lrs1}, {ldq_2_bits_uop_lrs1}, {ldq_1_bits_uop_lrs1}, {ldq_0_bits_uop_lrs1}}; // @[lsu.scala:208:16, :263:49] assign ldq_incoming_e_0_bits_uop_lrs1 = _GEN_154[ldq_incoming_idx_0]; // @[lsu.scala:263:49] wire [7:0][5:0] _GEN_155 = {{ldq_7_bits_uop_lrs2}, {ldq_6_bits_uop_lrs2}, {ldq_5_bits_uop_lrs2}, {ldq_4_bits_uop_lrs2}, {ldq_3_bits_uop_lrs2}, {ldq_2_bits_uop_lrs2}, {ldq_1_bits_uop_lrs2}, {ldq_0_bits_uop_lrs2}}; // @[lsu.scala:208:16, :263:49] assign ldq_incoming_e_0_bits_uop_lrs2 = _GEN_155[ldq_incoming_idx_0]; // @[lsu.scala:263:49] wire [7:0][5:0] _GEN_156 = {{ldq_7_bits_uop_lrs3}, {ldq_6_bits_uop_lrs3}, {ldq_5_bits_uop_lrs3}, {ldq_4_bits_uop_lrs3}, {ldq_3_bits_uop_lrs3}, {ldq_2_bits_uop_lrs3}, {ldq_1_bits_uop_lrs3}, {ldq_0_bits_uop_lrs3}}; // @[lsu.scala:208:16, :263:49] assign ldq_incoming_e_0_bits_uop_lrs3 = _GEN_156[ldq_incoming_idx_0]; // @[lsu.scala:263:49] wire [7:0] _GEN_157 = {{ldq_7_bits_uop_ldst_val}, {ldq_6_bits_uop_ldst_val}, {ldq_5_bits_uop_ldst_val}, {ldq_4_bits_uop_ldst_val}, {ldq_3_bits_uop_ldst_val}, {ldq_2_bits_uop_ldst_val}, {ldq_1_bits_uop_ldst_val}, {ldq_0_bits_uop_ldst_val}}; // @[lsu.scala:208:16, :263:49] assign ldq_incoming_e_0_bits_uop_ldst_val = _GEN_157[ldq_incoming_idx_0]; // @[lsu.scala:263:49] wire [7:0][1:0] _GEN_158 = {{ldq_7_bits_uop_dst_rtype}, {ldq_6_bits_uop_dst_rtype}, {ldq_5_bits_uop_dst_rtype}, {ldq_4_bits_uop_dst_rtype}, {ldq_3_bits_uop_dst_rtype}, {ldq_2_bits_uop_dst_rtype}, {ldq_1_bits_uop_dst_rtype}, {ldq_0_bits_uop_dst_rtype}}; // @[lsu.scala:208:16, :263:49] assign ldq_incoming_e_0_bits_uop_dst_rtype = _GEN_158[ldq_incoming_idx_0]; // @[lsu.scala:263:49] wire [7:0][1:0] _GEN_159 = {{ldq_7_bits_uop_lrs1_rtype}, {ldq_6_bits_uop_lrs1_rtype}, {ldq_5_bits_uop_lrs1_rtype}, {ldq_4_bits_uop_lrs1_rtype}, {ldq_3_bits_uop_lrs1_rtype}, {ldq_2_bits_uop_lrs1_rtype}, {ldq_1_bits_uop_lrs1_rtype}, {ldq_0_bits_uop_lrs1_rtype}}; // @[lsu.scala:208:16, :263:49] assign ldq_incoming_e_0_bits_uop_lrs1_rtype = _GEN_159[ldq_incoming_idx_0]; // @[lsu.scala:263:49] wire [7:0][1:0] _GEN_160 = {{ldq_7_bits_uop_lrs2_rtype}, {ldq_6_bits_uop_lrs2_rtype}, {ldq_5_bits_uop_lrs2_rtype}, {ldq_4_bits_uop_lrs2_rtype}, {ldq_3_bits_uop_lrs2_rtype}, {ldq_2_bits_uop_lrs2_rtype}, {ldq_1_bits_uop_lrs2_rtype}, {ldq_0_bits_uop_lrs2_rtype}}; // @[lsu.scala:208:16, :263:49] assign ldq_incoming_e_0_bits_uop_lrs2_rtype = _GEN_160[ldq_incoming_idx_0]; // @[lsu.scala:263:49] wire [7:0] _GEN_161 = {{ldq_7_bits_uop_frs3_en}, {ldq_6_bits_uop_frs3_en}, {ldq_5_bits_uop_frs3_en}, {ldq_4_bits_uop_frs3_en}, {ldq_3_bits_uop_frs3_en}, {ldq_2_bits_uop_frs3_en}, {ldq_1_bits_uop_frs3_en}, {ldq_0_bits_uop_frs3_en}}; // @[lsu.scala:208:16, :263:49] assign ldq_incoming_e_0_bits_uop_frs3_en = _GEN_161[ldq_incoming_idx_0]; // @[lsu.scala:263:49] wire [7:0] _GEN_162 = {{ldq_7_bits_uop_fp_val}, {ldq_6_bits_uop_fp_val}, {ldq_5_bits_uop_fp_val}, {ldq_4_bits_uop_fp_val}, {ldq_3_bits_uop_fp_val}, {ldq_2_bits_uop_fp_val}, {ldq_1_bits_uop_fp_val}, {ldq_0_bits_uop_fp_val}}; // @[lsu.scala:208:16, :263:49] assign ldq_incoming_e_0_bits_uop_fp_val = _GEN_162[ldq_incoming_idx_0]; // @[lsu.scala:263:49] wire [7:0] _GEN_163 = {{ldq_7_bits_uop_fp_single}, {ldq_6_bits_uop_fp_single}, {ldq_5_bits_uop_fp_single}, {ldq_4_bits_uop_fp_single}, {ldq_3_bits_uop_fp_single}, {ldq_2_bits_uop_fp_single}, {ldq_1_bits_uop_fp_single}, {ldq_0_bits_uop_fp_single}}; // @[lsu.scala:208:16, :263:49] assign ldq_incoming_e_0_bits_uop_fp_single = _GEN_163[ldq_incoming_idx_0]; // @[lsu.scala:263:49] wire [7:0] _GEN_164 = {{ldq_7_bits_uop_xcpt_pf_if}, {ldq_6_bits_uop_xcpt_pf_if}, {ldq_5_bits_uop_xcpt_pf_if}, {ldq_4_bits_uop_xcpt_pf_if}, {ldq_3_bits_uop_xcpt_pf_if}, {ldq_2_bits_uop_xcpt_pf_if}, {ldq_1_bits_uop_xcpt_pf_if}, {ldq_0_bits_uop_xcpt_pf_if}}; // @[lsu.scala:208:16, :263:49] assign ldq_incoming_e_0_bits_uop_xcpt_pf_if = _GEN_164[ldq_incoming_idx_0]; // @[lsu.scala:263:49] wire [7:0] _GEN_165 = {{ldq_7_bits_uop_xcpt_ae_if}, {ldq_6_bits_uop_xcpt_ae_if}, {ldq_5_bits_uop_xcpt_ae_if}, {ldq_4_bits_uop_xcpt_ae_if}, {ldq_3_bits_uop_xcpt_ae_if}, {ldq_2_bits_uop_xcpt_ae_if}, {ldq_1_bits_uop_xcpt_ae_if}, {ldq_0_bits_uop_xcpt_ae_if}}; // @[lsu.scala:208:16, :263:49] assign ldq_incoming_e_0_bits_uop_xcpt_ae_if = _GEN_165[ldq_incoming_idx_0]; // @[lsu.scala:263:49] wire [7:0] _GEN_166 = {{ldq_7_bits_uop_xcpt_ma_if}, {ldq_6_bits_uop_xcpt_ma_if}, {ldq_5_bits_uop_xcpt_ma_if}, {ldq_4_bits_uop_xcpt_ma_if}, {ldq_3_bits_uop_xcpt_ma_if}, {ldq_2_bits_uop_xcpt_ma_if}, {ldq_1_bits_uop_xcpt_ma_if}, {ldq_0_bits_uop_xcpt_ma_if}}; // @[lsu.scala:208:16, :263:49] assign ldq_incoming_e_0_bits_uop_xcpt_ma_if = _GEN_166[ldq_incoming_idx_0]; // @[lsu.scala:263:49] wire [7:0] _GEN_167 = {{ldq_7_bits_uop_bp_debug_if}, {ldq_6_bits_uop_bp_debug_if}, {ldq_5_bits_uop_bp_debug_if}, {ldq_4_bits_uop_bp_debug_if}, {ldq_3_bits_uop_bp_debug_if}, {ldq_2_bits_uop_bp_debug_if}, {ldq_1_bits_uop_bp_debug_if}, {ldq_0_bits_uop_bp_debug_if}}; // @[lsu.scala:208:16, :263:49] assign ldq_incoming_e_0_bits_uop_bp_debug_if = _GEN_167[ldq_incoming_idx_0]; // @[lsu.scala:263:49] wire [7:0] _GEN_168 = {{ldq_7_bits_uop_bp_xcpt_if}, {ldq_6_bits_uop_bp_xcpt_if}, {ldq_5_bits_uop_bp_xcpt_if}, {ldq_4_bits_uop_bp_xcpt_if}, {ldq_3_bits_uop_bp_xcpt_if}, {ldq_2_bits_uop_bp_xcpt_if}, {ldq_1_bits_uop_bp_xcpt_if}, {ldq_0_bits_uop_bp_xcpt_if}}; // @[lsu.scala:208:16, :263:49] assign ldq_incoming_e_0_bits_uop_bp_xcpt_if = _GEN_168[ldq_incoming_idx_0]; // @[lsu.scala:263:49] wire [7:0][1:0] _GEN_169 = {{ldq_7_bits_uop_debug_fsrc}, {ldq_6_bits_uop_debug_fsrc}, {ldq_5_bits_uop_debug_fsrc}, {ldq_4_bits_uop_debug_fsrc}, {ldq_3_bits_uop_debug_fsrc}, {ldq_2_bits_uop_debug_fsrc}, {ldq_1_bits_uop_debug_fsrc}, {ldq_0_bits_uop_debug_fsrc}}; // @[lsu.scala:208:16, :263:49] assign ldq_incoming_e_0_bits_uop_debug_fsrc = _GEN_169[ldq_incoming_idx_0]; // @[lsu.scala:263:49] wire [7:0][1:0] _GEN_170 = {{ldq_7_bits_uop_debug_tsrc}, {ldq_6_bits_uop_debug_tsrc}, {ldq_5_bits_uop_debug_tsrc}, {ldq_4_bits_uop_debug_tsrc}, {ldq_3_bits_uop_debug_tsrc}, {ldq_2_bits_uop_debug_tsrc}, {ldq_1_bits_uop_debug_tsrc}, {ldq_0_bits_uop_debug_tsrc}}; // @[lsu.scala:208:16, :263:49] assign ldq_incoming_e_0_bits_uop_debug_tsrc = _GEN_170[ldq_incoming_idx_0]; // @[lsu.scala:263:49] wire [7:0] _GEN_171 = {{ldq_7_bits_addr_valid}, {ldq_6_bits_addr_valid}, {ldq_5_bits_addr_valid}, {ldq_4_bits_addr_valid}, {ldq_3_bits_addr_valid}, {ldq_2_bits_addr_valid}, {ldq_1_bits_addr_valid}, {ldq_0_bits_addr_valid}}; // @[lsu.scala:208:16, :263:49] assign ldq_incoming_e_0_bits_addr_valid = _GEN_171[ldq_incoming_idx_0]; // @[lsu.scala:263:49] wire [7:0][39:0] _GEN_172 = {{ldq_7_bits_addr_bits}, {ldq_6_bits_addr_bits}, {ldq_5_bits_addr_bits}, {ldq_4_bits_addr_bits}, {ldq_3_bits_addr_bits}, {ldq_2_bits_addr_bits}, {ldq_1_bits_addr_bits}, {ldq_0_bits_addr_bits}}; // @[lsu.scala:208:16, :263:49] assign ldq_incoming_e_0_bits_addr_bits = _GEN_172[ldq_incoming_idx_0]; // @[lsu.scala:263:49] wire [7:0] _GEN_173 = {{ldq_7_bits_addr_is_virtual}, {ldq_6_bits_addr_is_virtual}, {ldq_5_bits_addr_is_virtual}, {ldq_4_bits_addr_is_virtual}, {ldq_3_bits_addr_is_virtual}, {ldq_2_bits_addr_is_virtual}, {ldq_1_bits_addr_is_virtual}, {ldq_0_bits_addr_is_virtual}}; // @[lsu.scala:208:16, :263:49] assign ldq_incoming_e_0_bits_addr_is_virtual = _GEN_173[ldq_incoming_idx_0]; // @[lsu.scala:263:49] wire [7:0] _GEN_174 = {{ldq_7_bits_addr_is_uncacheable}, {ldq_6_bits_addr_is_uncacheable}, {ldq_5_bits_addr_is_uncacheable}, {ldq_4_bits_addr_is_uncacheable}, {ldq_3_bits_addr_is_uncacheable}, {ldq_2_bits_addr_is_uncacheable}, {ldq_1_bits_addr_is_uncacheable}, {ldq_0_bits_addr_is_uncacheable}}; // @[lsu.scala:208:16, :263:49] assign ldq_incoming_e_0_bits_addr_is_uncacheable = _GEN_174[ldq_incoming_idx_0]; // @[lsu.scala:263:49] wire [7:0] _GEN_175 = {{ldq_7_bits_executed}, {ldq_6_bits_executed}, {ldq_5_bits_executed}, {ldq_4_bits_executed}, {ldq_3_bits_executed}, {ldq_2_bits_executed}, {ldq_1_bits_executed}, {ldq_0_bits_executed}}; // @[lsu.scala:208:16, :263:49] assign ldq_incoming_e_0_bits_executed = _GEN_175[ldq_incoming_idx_0]; // @[lsu.scala:263:49] wire [7:0] _GEN_176 = {{ldq_7_bits_succeeded}, {ldq_6_bits_succeeded}, {ldq_5_bits_succeeded}, {ldq_4_bits_succeeded}, {ldq_3_bits_succeeded}, {ldq_2_bits_succeeded}, {ldq_1_bits_succeeded}, {ldq_0_bits_succeeded}}; // @[lsu.scala:208:16, :263:49] assign ldq_incoming_e_0_bits_succeeded = _GEN_176[ldq_incoming_idx_0]; // @[lsu.scala:263:49] wire [7:0] _GEN_177 = {{ldq_7_bits_order_fail}, {ldq_6_bits_order_fail}, {ldq_5_bits_order_fail}, {ldq_4_bits_order_fail}, {ldq_3_bits_order_fail}, {ldq_2_bits_order_fail}, {ldq_1_bits_order_fail}, {ldq_0_bits_order_fail}}; // @[lsu.scala:208:16, :263:49] assign ldq_incoming_e_0_bits_order_fail = _GEN_177[ldq_incoming_idx_0]; // @[lsu.scala:263:49] wire [7:0] _GEN_178 = {{ldq_7_bits_observed}, {ldq_6_bits_observed}, {ldq_5_bits_observed}, {ldq_4_bits_observed}, {ldq_3_bits_observed}, {ldq_2_bits_observed}, {ldq_1_bits_observed}, {ldq_0_bits_observed}}; // @[lsu.scala:208:16, :263:49] assign ldq_incoming_e_0_bits_observed = _GEN_178[ldq_incoming_idx_0]; // @[lsu.scala:263:49] wire [7:0][7:0] _GEN_179 = {{ldq_7_bits_st_dep_mask}, {ldq_6_bits_st_dep_mask}, {ldq_5_bits_st_dep_mask}, {ldq_4_bits_st_dep_mask}, {ldq_3_bits_st_dep_mask}, {ldq_2_bits_st_dep_mask}, {ldq_1_bits_st_dep_mask}, {ldq_0_bits_st_dep_mask}}; // @[lsu.scala:208:16, :263:49] assign ldq_incoming_e_0_bits_st_dep_mask = _GEN_179[ldq_incoming_idx_0]; // @[lsu.scala:263:49] wire [7:0][2:0] _GEN_180 = {{ldq_7_bits_youngest_stq_idx}, {ldq_6_bits_youngest_stq_idx}, {ldq_5_bits_youngest_stq_idx}, {ldq_4_bits_youngest_stq_idx}, {ldq_3_bits_youngest_stq_idx}, {ldq_2_bits_youngest_stq_idx}, {ldq_1_bits_youngest_stq_idx}, {ldq_0_bits_youngest_stq_idx}}; // @[lsu.scala:208:16, :263:49] assign ldq_incoming_e_0_bits_youngest_stq_idx = _GEN_180[ldq_incoming_idx_0]; // @[lsu.scala:263:49] wire [7:0] _GEN_181 = {{ldq_7_bits_forward_std_val}, {ldq_6_bits_forward_std_val}, {ldq_5_bits_forward_std_val}, {ldq_4_bits_forward_std_val}, {ldq_3_bits_forward_std_val}, {ldq_2_bits_forward_std_val}, {ldq_1_bits_forward_std_val}, {ldq_0_bits_forward_std_val}}; // @[lsu.scala:208:16, :263:49] assign ldq_incoming_e_0_bits_forward_std_val = _GEN_181[ldq_incoming_idx_0]; // @[lsu.scala:263:49] wire [7:0][2:0] _GEN_182 = {{ldq_7_bits_forward_stq_idx}, {ldq_6_bits_forward_stq_idx}, {ldq_5_bits_forward_stq_idx}, {ldq_4_bits_forward_stq_idx}, {ldq_3_bits_forward_stq_idx}, {ldq_2_bits_forward_stq_idx}, {ldq_1_bits_forward_stq_idx}, {ldq_0_bits_forward_stq_idx}}; // @[lsu.scala:208:16, :263:49] assign ldq_incoming_e_0_bits_forward_stq_idx = _GEN_182[ldq_incoming_idx_0]; // @[lsu.scala:263:49] wire [7:0][63:0] _GEN_183 = {{ldq_7_bits_debug_wb_data}, {ldq_6_bits_debug_wb_data}, {ldq_5_bits_debug_wb_data}, {ldq_4_bits_debug_wb_data}, {ldq_3_bits_debug_wb_data}, {ldq_2_bits_debug_wb_data}, {ldq_1_bits_debug_wb_data}, {ldq_0_bits_debug_wb_data}}; // @[lsu.scala:208:16, :263:49] assign ldq_incoming_e_0_bits_debug_wb_data = _GEN_183[ldq_incoming_idx_0]; // @[lsu.scala:263:49] wire [6:0] mem_stq_incoming_e_out_bits_uop_uopc = stq_incoming_e_0_bits_uop_uopc; // @[util.scala:106:23] wire [31:0] mem_stq_incoming_e_out_bits_uop_inst = stq_incoming_e_0_bits_uop_inst; // @[util.scala:106:23] wire [31:0] mem_stq_incoming_e_out_bits_uop_debug_inst = stq_incoming_e_0_bits_uop_debug_inst; // @[util.scala:106:23] wire mem_stq_incoming_e_out_bits_uop_is_rvc = stq_incoming_e_0_bits_uop_is_rvc; // @[util.scala:106:23] wire [39:0] mem_stq_incoming_e_out_bits_uop_debug_pc = stq_incoming_e_0_bits_uop_debug_pc; // @[util.scala:106:23] wire [2:0] mem_stq_incoming_e_out_bits_uop_iq_type = stq_incoming_e_0_bits_uop_iq_type; // @[util.scala:106:23] wire [9:0] mem_stq_incoming_e_out_bits_uop_fu_code = stq_incoming_e_0_bits_uop_fu_code; // @[util.scala:106:23] wire [3:0] mem_stq_incoming_e_out_bits_uop_ctrl_br_type = stq_incoming_e_0_bits_uop_ctrl_br_type; // @[util.scala:106:23] wire [1:0] mem_stq_incoming_e_out_bits_uop_ctrl_op1_sel = stq_incoming_e_0_bits_uop_ctrl_op1_sel; // @[util.scala:106:23] wire [2:0] mem_stq_incoming_e_out_bits_uop_ctrl_op2_sel = stq_incoming_e_0_bits_uop_ctrl_op2_sel; // @[util.scala:106:23] wire [2:0] mem_stq_incoming_e_out_bits_uop_ctrl_imm_sel = stq_incoming_e_0_bits_uop_ctrl_imm_sel; // @[util.scala:106:23] wire [4:0] mem_stq_incoming_e_out_bits_uop_ctrl_op_fcn = stq_incoming_e_0_bits_uop_ctrl_op_fcn; // @[util.scala:106:23] wire mem_stq_incoming_e_out_bits_uop_ctrl_fcn_dw = stq_incoming_e_0_bits_uop_ctrl_fcn_dw; // @[util.scala:106:23] wire [2:0] mem_stq_incoming_e_out_bits_uop_ctrl_csr_cmd = stq_incoming_e_0_bits_uop_ctrl_csr_cmd; // @[util.scala:106:23] wire mem_stq_incoming_e_out_bits_uop_ctrl_is_load = stq_incoming_e_0_bits_uop_ctrl_is_load; // @[util.scala:106:23] wire mem_stq_incoming_e_out_bits_uop_ctrl_is_sta = stq_incoming_e_0_bits_uop_ctrl_is_sta; // @[util.scala:106:23] wire mem_stq_incoming_e_out_bits_uop_ctrl_is_std = stq_incoming_e_0_bits_uop_ctrl_is_std; // @[util.scala:106:23] wire [1:0] mem_stq_incoming_e_out_bits_uop_iw_state = stq_incoming_e_0_bits_uop_iw_state; // @[util.scala:106:23] wire mem_stq_incoming_e_out_bits_uop_iw_p1_poisoned = stq_incoming_e_0_bits_uop_iw_p1_poisoned; // @[util.scala:106:23] wire mem_stq_incoming_e_out_bits_uop_iw_p2_poisoned = stq_incoming_e_0_bits_uop_iw_p2_poisoned; // @[util.scala:106:23] wire mem_stq_incoming_e_out_bits_uop_is_br = stq_incoming_e_0_bits_uop_is_br; // @[util.scala:106:23] wire mem_stq_incoming_e_out_bits_uop_is_jalr = stq_incoming_e_0_bits_uop_is_jalr; // @[util.scala:106:23] wire mem_stq_incoming_e_out_bits_uop_is_jal = stq_incoming_e_0_bits_uop_is_jal; // @[util.scala:106:23] wire mem_stq_incoming_e_out_bits_uop_is_sfb = stq_incoming_e_0_bits_uop_is_sfb; // @[util.scala:106:23] wire [2:0] mem_stq_incoming_e_out_bits_uop_br_tag = stq_incoming_e_0_bits_uop_br_tag; // @[util.scala:106:23] wire [3:0] mem_stq_incoming_e_out_bits_uop_ftq_idx = stq_incoming_e_0_bits_uop_ftq_idx; // @[util.scala:106:23] wire mem_stq_incoming_e_out_bits_uop_edge_inst = stq_incoming_e_0_bits_uop_edge_inst; // @[util.scala:106:23] wire [5:0] mem_stq_incoming_e_out_bits_uop_pc_lob = stq_incoming_e_0_bits_uop_pc_lob; // @[util.scala:106:23] wire mem_stq_incoming_e_out_bits_uop_taken = stq_incoming_e_0_bits_uop_taken; // @[util.scala:106:23] wire [19:0] mem_stq_incoming_e_out_bits_uop_imm_packed = stq_incoming_e_0_bits_uop_imm_packed; // @[util.scala:106:23] wire [11:0] mem_stq_incoming_e_out_bits_uop_csr_addr = stq_incoming_e_0_bits_uop_csr_addr; // @[util.scala:106:23] wire [4:0] mem_stq_incoming_e_out_bits_uop_rob_idx = stq_incoming_e_0_bits_uop_rob_idx; // @[util.scala:106:23] wire [2:0] mem_stq_incoming_e_out_bits_uop_ldq_idx = stq_incoming_e_0_bits_uop_ldq_idx; // @[util.scala:106:23] wire [2:0] mem_stq_incoming_e_out_bits_uop_stq_idx = stq_incoming_e_0_bits_uop_stq_idx; // @[util.scala:106:23] wire [1:0] mem_stq_incoming_e_out_bits_uop_rxq_idx = stq_incoming_e_0_bits_uop_rxq_idx; // @[util.scala:106:23] wire [5:0] mem_stq_incoming_e_out_bits_uop_pdst = stq_incoming_e_0_bits_uop_pdst; // @[util.scala:106:23] wire [5:0] mem_stq_incoming_e_out_bits_uop_prs1 = stq_incoming_e_0_bits_uop_prs1; // @[util.scala:106:23] wire [5:0] mem_stq_incoming_e_out_bits_uop_prs2 = stq_incoming_e_0_bits_uop_prs2; // @[util.scala:106:23] wire [5:0] mem_stq_incoming_e_out_bits_uop_prs3 = stq_incoming_e_0_bits_uop_prs3; // @[util.scala:106:23] wire [3:0] mem_stq_incoming_e_out_bits_uop_ppred = stq_incoming_e_0_bits_uop_ppred; // @[util.scala:106:23] wire mem_stq_incoming_e_out_bits_uop_prs1_busy = stq_incoming_e_0_bits_uop_prs1_busy; // @[util.scala:106:23] wire mem_stq_incoming_e_out_bits_uop_prs2_busy = stq_incoming_e_0_bits_uop_prs2_busy; // @[util.scala:106:23] wire mem_stq_incoming_e_out_bits_uop_prs3_busy = stq_incoming_e_0_bits_uop_prs3_busy; // @[util.scala:106:23] wire mem_stq_incoming_e_out_bits_uop_ppred_busy = stq_incoming_e_0_bits_uop_ppred_busy; // @[util.scala:106:23] wire [5:0] mem_stq_incoming_e_out_bits_uop_stale_pdst = stq_incoming_e_0_bits_uop_stale_pdst; // @[util.scala:106:23] wire mem_stq_incoming_e_out_bits_uop_exception = stq_incoming_e_0_bits_uop_exception; // @[util.scala:106:23] wire [63:0] mem_stq_incoming_e_out_bits_uop_exc_cause = stq_incoming_e_0_bits_uop_exc_cause; // @[util.scala:106:23] wire mem_stq_incoming_e_out_bits_uop_bypassable = stq_incoming_e_0_bits_uop_bypassable; // @[util.scala:106:23] wire [4:0] mem_stq_incoming_e_out_bits_uop_mem_cmd = stq_incoming_e_0_bits_uop_mem_cmd; // @[util.scala:106:23] wire [1:0] mem_stq_incoming_e_out_bits_uop_mem_size = stq_incoming_e_0_bits_uop_mem_size; // @[util.scala:106:23] wire mem_stq_incoming_e_out_bits_uop_mem_signed = stq_incoming_e_0_bits_uop_mem_signed; // @[util.scala:106:23] wire mem_stq_incoming_e_out_bits_uop_is_fence = stq_incoming_e_0_bits_uop_is_fence; // @[util.scala:106:23] wire mem_stq_incoming_e_out_bits_uop_is_fencei = stq_incoming_e_0_bits_uop_is_fencei; // @[util.scala:106:23] wire mem_stq_incoming_e_out_bits_uop_is_amo = stq_incoming_e_0_bits_uop_is_amo; // @[util.scala:106:23] wire mem_stq_incoming_e_out_bits_uop_uses_ldq = stq_incoming_e_0_bits_uop_uses_ldq; // @[util.scala:106:23] wire mem_stq_incoming_e_out_bits_uop_uses_stq = stq_incoming_e_0_bits_uop_uses_stq; // @[util.scala:106:23] wire mem_stq_incoming_e_out_bits_uop_is_sys_pc2epc = stq_incoming_e_0_bits_uop_is_sys_pc2epc; // @[util.scala:106:23] wire mem_stq_incoming_e_out_bits_uop_is_unique = stq_incoming_e_0_bits_uop_is_unique; // @[util.scala:106:23] wire mem_stq_incoming_e_out_bits_uop_flush_on_commit = stq_incoming_e_0_bits_uop_flush_on_commit; // @[util.scala:106:23] wire mem_stq_incoming_e_out_bits_uop_ldst_is_rs1 = stq_incoming_e_0_bits_uop_ldst_is_rs1; // @[util.scala:106:23] wire [5:0] mem_stq_incoming_e_out_bits_uop_ldst = stq_incoming_e_0_bits_uop_ldst; // @[util.scala:106:23] wire [5:0] mem_stq_incoming_e_out_bits_uop_lrs1 = stq_incoming_e_0_bits_uop_lrs1; // @[util.scala:106:23] wire [5:0] mem_stq_incoming_e_out_bits_uop_lrs2 = stq_incoming_e_0_bits_uop_lrs2; // @[util.scala:106:23] wire [5:0] mem_stq_incoming_e_out_bits_uop_lrs3 = stq_incoming_e_0_bits_uop_lrs3; // @[util.scala:106:23] wire mem_stq_incoming_e_out_bits_uop_ldst_val = stq_incoming_e_0_bits_uop_ldst_val; // @[util.scala:106:23] wire [1:0] mem_stq_incoming_e_out_bits_uop_dst_rtype = stq_incoming_e_0_bits_uop_dst_rtype; // @[util.scala:106:23] wire [1:0] mem_stq_incoming_e_out_bits_uop_lrs1_rtype = stq_incoming_e_0_bits_uop_lrs1_rtype; // @[util.scala:106:23] wire [1:0] mem_stq_incoming_e_out_bits_uop_lrs2_rtype = stq_incoming_e_0_bits_uop_lrs2_rtype; // @[util.scala:106:23] wire mem_stq_incoming_e_out_bits_uop_frs3_en = stq_incoming_e_0_bits_uop_frs3_en; // @[util.scala:106:23] wire mem_stq_incoming_e_out_bits_uop_fp_val = stq_incoming_e_0_bits_uop_fp_val; // @[util.scala:106:23] wire mem_stq_incoming_e_out_bits_uop_fp_single = stq_incoming_e_0_bits_uop_fp_single; // @[util.scala:106:23] wire mem_stq_incoming_e_out_bits_uop_xcpt_pf_if = stq_incoming_e_0_bits_uop_xcpt_pf_if; // @[util.scala:106:23] wire mem_stq_incoming_e_out_bits_uop_xcpt_ae_if = stq_incoming_e_0_bits_uop_xcpt_ae_if; // @[util.scala:106:23] wire mem_stq_incoming_e_out_bits_uop_xcpt_ma_if = stq_incoming_e_0_bits_uop_xcpt_ma_if; // @[util.scala:106:23] wire mem_stq_incoming_e_out_bits_uop_bp_debug_if = stq_incoming_e_0_bits_uop_bp_debug_if; // @[util.scala:106:23] wire mem_stq_incoming_e_out_bits_uop_bp_xcpt_if = stq_incoming_e_0_bits_uop_bp_xcpt_if; // @[util.scala:106:23] wire [1:0] mem_stq_incoming_e_out_bits_uop_debug_fsrc = stq_incoming_e_0_bits_uop_debug_fsrc; // @[util.scala:106:23] wire [1:0] mem_stq_incoming_e_out_bits_uop_debug_tsrc = stq_incoming_e_0_bits_uop_debug_tsrc; // @[util.scala:106:23] wire mem_stq_incoming_e_out_bits_addr_valid = stq_incoming_e_0_bits_addr_valid; // @[util.scala:106:23] wire [39:0] mem_stq_incoming_e_out_bits_addr_bits = stq_incoming_e_0_bits_addr_bits; // @[util.scala:106:23] wire mem_stq_incoming_e_out_bits_addr_is_virtual = stq_incoming_e_0_bits_addr_is_virtual; // @[util.scala:106:23] wire mem_stq_incoming_e_out_bits_data_valid = stq_incoming_e_0_bits_data_valid; // @[util.scala:106:23] wire [63:0] mem_stq_incoming_e_out_bits_data_bits = stq_incoming_e_0_bits_data_bits; // @[util.scala:106:23] wire mem_stq_incoming_e_out_bits_committed = stq_incoming_e_0_bits_committed; // @[util.scala:106:23] wire mem_stq_incoming_e_out_bits_succeeded = stq_incoming_e_0_bits_succeeded; // @[util.scala:106:23] wire [63:0] mem_stq_incoming_e_out_bits_debug_wb_data = stq_incoming_e_0_bits_debug_wb_data; // @[util.scala:106:23] wire [7:0] stq_incoming_e_0_bits_uop_br_mask; // @[lsu.scala:263:49] wire stq_incoming_e_0_valid; // @[lsu.scala:263:49] assign stq_incoming_e_0_valid = _GEN[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49] assign stq_incoming_e_0_bits_uop_uopc = _GEN_1[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49] assign stq_incoming_e_0_bits_uop_inst = _GEN_2[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49] assign stq_incoming_e_0_bits_uop_debug_inst = _GEN_3[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49] assign stq_incoming_e_0_bits_uop_is_rvc = _GEN_4[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49] assign stq_incoming_e_0_bits_uop_debug_pc = _GEN_5[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49] assign stq_incoming_e_0_bits_uop_iq_type = _GEN_6[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49] assign stq_incoming_e_0_bits_uop_fu_code = _GEN_7[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49] assign stq_incoming_e_0_bits_uop_ctrl_br_type = _GEN_8[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49] assign stq_incoming_e_0_bits_uop_ctrl_op1_sel = _GEN_9[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49] assign stq_incoming_e_0_bits_uop_ctrl_op2_sel = _GEN_10[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49] assign stq_incoming_e_0_bits_uop_ctrl_imm_sel = _GEN_11[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49] assign stq_incoming_e_0_bits_uop_ctrl_op_fcn = _GEN_12[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49] assign stq_incoming_e_0_bits_uop_ctrl_fcn_dw = _GEN_13[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49] assign stq_incoming_e_0_bits_uop_ctrl_csr_cmd = _GEN_14[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49] assign stq_incoming_e_0_bits_uop_ctrl_is_load = _GEN_15[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49] assign stq_incoming_e_0_bits_uop_ctrl_is_sta = _GEN_16[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49] assign stq_incoming_e_0_bits_uop_ctrl_is_std = _GEN_17[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49] assign stq_incoming_e_0_bits_uop_iw_state = _GEN_18[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49] assign stq_incoming_e_0_bits_uop_iw_p1_poisoned = _GEN_19[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49] assign stq_incoming_e_0_bits_uop_iw_p2_poisoned = _GEN_20[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49] assign stq_incoming_e_0_bits_uop_is_br = _GEN_21[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49] assign stq_incoming_e_0_bits_uop_is_jalr = _GEN_22[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49] assign stq_incoming_e_0_bits_uop_is_jal = _GEN_23[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49] assign stq_incoming_e_0_bits_uop_is_sfb = _GEN_24[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49] assign stq_incoming_e_0_bits_uop_br_mask = _GEN_25[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49] assign stq_incoming_e_0_bits_uop_br_tag = _GEN_26[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49] assign stq_incoming_e_0_bits_uop_ftq_idx = _GEN_27[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49] assign stq_incoming_e_0_bits_uop_edge_inst = _GEN_28[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49] assign stq_incoming_e_0_bits_uop_pc_lob = _GEN_29[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49] assign stq_incoming_e_0_bits_uop_taken = _GEN_30[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49] assign stq_incoming_e_0_bits_uop_imm_packed = _GEN_31[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49] assign stq_incoming_e_0_bits_uop_csr_addr = _GEN_32[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49] assign stq_incoming_e_0_bits_uop_rob_idx = _GEN_33[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49] assign stq_incoming_e_0_bits_uop_ldq_idx = _GEN_34[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49] assign stq_incoming_e_0_bits_uop_stq_idx = _GEN_35[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49] assign stq_incoming_e_0_bits_uop_rxq_idx = _GEN_36[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49] assign stq_incoming_e_0_bits_uop_pdst = _GEN_37[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49] assign stq_incoming_e_0_bits_uop_prs1 = _GEN_38[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49] assign stq_incoming_e_0_bits_uop_prs2 = _GEN_39[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49] assign stq_incoming_e_0_bits_uop_prs3 = _GEN_40[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49] assign stq_incoming_e_0_bits_uop_ppred = _GEN_41[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49] assign stq_incoming_e_0_bits_uop_prs1_busy = _GEN_42[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49] assign stq_incoming_e_0_bits_uop_prs2_busy = _GEN_43[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49] assign stq_incoming_e_0_bits_uop_prs3_busy = _GEN_44[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49] assign stq_incoming_e_0_bits_uop_ppred_busy = _GEN_45[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49] assign stq_incoming_e_0_bits_uop_stale_pdst = _GEN_46[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49] assign stq_incoming_e_0_bits_uop_exception = _GEN_47[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49] assign stq_incoming_e_0_bits_uop_exc_cause = _GEN_49[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49] assign stq_incoming_e_0_bits_uop_bypassable = _GEN_50[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49] assign stq_incoming_e_0_bits_uop_mem_cmd = _GEN_51[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49] assign stq_incoming_e_0_bits_uop_mem_size = _GEN_52[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49] assign stq_incoming_e_0_bits_uop_mem_signed = _GEN_53[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49] assign stq_incoming_e_0_bits_uop_is_fence = _GEN_54[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49] assign stq_incoming_e_0_bits_uop_is_fencei = _GEN_56[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49] assign stq_incoming_e_0_bits_uop_is_amo = _GEN_57[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49] assign stq_incoming_e_0_bits_uop_uses_ldq = _GEN_59[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49] assign stq_incoming_e_0_bits_uop_uses_stq = _GEN_60[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49] assign stq_incoming_e_0_bits_uop_is_sys_pc2epc = _GEN_61[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49] assign stq_incoming_e_0_bits_uop_is_unique = _GEN_62[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49] assign stq_incoming_e_0_bits_uop_flush_on_commit = _GEN_63[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49] assign stq_incoming_e_0_bits_uop_ldst_is_rs1 = _GEN_64[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49] assign stq_incoming_e_0_bits_uop_ldst = _GEN_65[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49] assign stq_incoming_e_0_bits_uop_lrs1 = _GEN_66[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49] assign stq_incoming_e_0_bits_uop_lrs2 = _GEN_67[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49] assign stq_incoming_e_0_bits_uop_lrs3 = _GEN_68[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49] assign stq_incoming_e_0_bits_uop_ldst_val = _GEN_69[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49] assign stq_incoming_e_0_bits_uop_dst_rtype = _GEN_70[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49] assign stq_incoming_e_0_bits_uop_lrs1_rtype = _GEN_71[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49] assign stq_incoming_e_0_bits_uop_lrs2_rtype = _GEN_72[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49] assign stq_incoming_e_0_bits_uop_frs3_en = _GEN_73[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49] assign stq_incoming_e_0_bits_uop_fp_val = _GEN_74[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49] assign stq_incoming_e_0_bits_uop_fp_single = _GEN_75[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49] assign stq_incoming_e_0_bits_uop_xcpt_pf_if = _GEN_76[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49] assign stq_incoming_e_0_bits_uop_xcpt_ae_if = _GEN_77[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49] assign stq_incoming_e_0_bits_uop_xcpt_ma_if = _GEN_78[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49] assign stq_incoming_e_0_bits_uop_bp_debug_if = _GEN_79[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49] assign stq_incoming_e_0_bits_uop_bp_xcpt_if = _GEN_80[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49] assign stq_incoming_e_0_bits_uop_debug_fsrc = _GEN_81[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49] assign stq_incoming_e_0_bits_uop_debug_tsrc = _GEN_82[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49] assign stq_incoming_e_0_bits_addr_valid = _GEN_83[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49] assign stq_incoming_e_0_bits_addr_bits = _GEN_84[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49] assign stq_incoming_e_0_bits_addr_is_virtual = _GEN_85[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49] assign stq_incoming_e_0_bits_data_valid = _GEN_86[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49] assign stq_incoming_e_0_bits_data_bits = _GEN_87[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49] assign stq_incoming_e_0_bits_committed = _GEN_89[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49] wire [7:0] _GEN_184 = {{stq_7_bits_succeeded}, {stq_6_bits_succeeded}, {stq_5_bits_succeeded}, {stq_4_bits_succeeded}, {stq_3_bits_succeeded}, {stq_2_bits_succeeded}, {stq_1_bits_succeeded}, {stq_0_bits_succeeded}}; // @[lsu.scala:209:16, :263:49] assign stq_incoming_e_0_bits_succeeded = _GEN_184[stq_incoming_idx_0]; // @[lsu.scala:263:49] wire [7:0][63:0] _GEN_185 = {{stq_7_bits_debug_wb_data}, {stq_6_bits_debug_wb_data}, {stq_5_bits_debug_wb_data}, {stq_4_bits_debug_wb_data}, {stq_3_bits_debug_wb_data}, {stq_2_bits_debug_wb_data}, {stq_1_bits_debug_wb_data}, {stq_0_bits_debug_wb_data}}; // @[lsu.scala:209:16, :263:49] assign stq_incoming_e_0_bits_debug_wb_data = _GEN_185[stq_incoming_idx_0]; // @[lsu.scala:263:49] wire _GEN_186 = block_load_mask_0 \| p1_block_load_mask_0; // @[lsu.scala:396:36, :397:35, :416:36] wire ldq_retry_idx_block; // @[lsu.scala:416:36] assign ldq_retry_idx_block = _GEN_186; // @[lsu.scala:416:36] wire ldq_wakeup_idx_block; // @[lsu.scala:431:36] assign ldq_wakeup_idx_block = _GEN_186; // @[lsu.scala:416:36, :431:36] wire _ldq_retry_idx_T = ldq_0_bits_addr_valid & ldq_0_bits_addr_is_virtual; // @[lsu.scala:208:16, :417:18] wire _ldq_retry_idx_T_1 = ~ldq_retry_idx_block; // @[lsu.scala:416:36, :417:42] wire _ldq_retry_idx_T_2 = _ldq_retry_idx_T & _ldq_retry_idx_T_1; // @[lsu.scala:417:{18,39,42}] wire _GEN_187 = block_load_mask_1 \| p1_block_load_mask_1; // @[lsu.scala:396:36, :397:35, :416:36] wire ldq_retry_idx_block_1; // @[lsu.scala:416:36] assign ldq_retry_idx_block_1 = _GEN_187; // @[lsu.scala:416:36] wire ldq_wakeup_idx_block_1; // @[lsu.scala:431:36] assign ldq_wakeup_idx_block_1 = _GEN_187; // @[lsu.scala:416:36, :431:36] wire _ldq_retry_idx_T_3 = ldq_1_bits_addr_valid & ldq_1_bits_addr_is_virtual; // @[lsu.scala:208:16, :417:18] wire _ldq_retry_idx_T_4 = ~ldq_retry_idx_block_1; // @[lsu.scala:416:36, :417:42] wire _ldq_retry_idx_T_5 = _ldq_retry_idx_T_3 & _ldq_retry_idx_T_4; // @[lsu.scala:417:{18,39,42}] wire _GEN_188 = block_load_mask_2 \| p1_block_load_mask_2; // @[lsu.scala:396:36, :397:35, :416:36] wire ldq_retry_idx_block_2; // @[lsu.scala:416:36] assign ldq_retry_idx_block_2 = _GEN_188; // @[lsu.scala:416:36] wire ldq_wakeup_idx_block_2; // @[lsu.scala:431:36] assign ldq_wakeup_idx_block_2 = _GEN_188; // @[lsu.scala:416:36, :431:36] wire _ldq_retry_idx_T_6 = ldq_2_bits_addr_valid & ldq_2_bits_addr_is_virtual; // @[lsu.scala:208:16, :417:18] wire _ldq_retry_idx_T_7 = ~ldq_retry_idx_block_2; // @[lsu.scala:416:36, :417:42] wire _ldq_retry_idx_T_8 = _ldq_retry_idx_T_6 & _ldq_retry_idx_T_7; // @[lsu.scala:417:{18,39,42}] wire _GEN_189 = block_load_mask_3 \| p1_block_load_mask_3; // @[lsu.scala:396:36, :397:35, :416:36] wire ldq_retry_idx_block_3; // @[lsu.scala:416:36] assign ldq_retry_idx_block_3 = _GEN_189; // @[lsu.scala:416:36] wire ldq_wakeup_idx_block_3; // @[lsu.scala:431:36] assign ldq_wakeup_idx_block_3 = _GEN_189; // @[lsu.scala:416:36, :431:36] wire _ldq_retry_idx_T_9 = ldq_3_bits_addr_valid & ldq_3_bits_addr_is_virtual; // @[lsu.scala:208:16, :417:18] wire _ldq_retry_idx_T_10 = ~ldq_retry_idx_block_3; // @[lsu.scala:416:36, :417:42] wire _ldq_retry_idx_T_11 = _ldq_retry_idx_T_9 & _ldq_retry_idx_T_10; // @[lsu.scala:417:{18,39,42}] wire _GEN_190 = block_load_mask_4 \| p1_block_load_mask_4; // @[lsu.scala:396:36, :397:35, :416:36] wire ldq_retry_idx_block_4; // @[lsu.scala:416:36] assign ldq_retry_idx_block_4 = _GEN_190; // @[lsu.scala:416:36] wire ldq_wakeup_idx_block_4; // @[lsu.scala:431:36] assign ldq_wakeup_idx_block_4 = _GEN_190; // @[lsu.scala:416:36, :431:36] wire _ldq_retry_idx_T_12 = ldq_4_bits_addr_valid & ldq_4_bits_addr_is_virtual; // @[lsu.scala:208:16, :417:18] wire _ldq_retry_idx_T_13 = ~ldq_retry_idx_block_4; // @[lsu.scala:416:36, :417:42] wire _ldq_retry_idx_T_14 = _ldq_retry_idx_T_12 & _ldq_retry_idx_T_13; // @[lsu.scala:417:{18,39,42}] wire _GEN_191 = block_load_mask_5 \| p1_block_load_mask_5; // @[lsu.scala:396:36, :397:35, :416:36] wire ldq_retry_idx_block_5; // @[lsu.scala:416:36] assign ldq_retry_idx_block_5 = _GEN_191; // @[lsu.scala:416:36] wire ldq_wakeup_idx_block_5; // @[lsu.scala:431:36] assign ldq_wakeup_idx_block_5 = _GEN_191; // @[lsu.scala:416:36, :431:36] wire _ldq_retry_idx_T_15 = ldq_5_bits_addr_valid & ldq_5_bits_addr_is_virtual; // @[lsu.scala:208:16, :417:18] wire _ldq_retry_idx_T_16 = ~ldq_retry_idx_block_5; // @[lsu.scala:416:36, :417:42] wire _ldq_retry_idx_T_17 = _ldq_retry_idx_T_15 & _ldq_retry_idx_T_16; // @[lsu.scala:417:{18,39,42}] wire _GEN_192 = block_load_mask_6 \| p1_block_load_mask_6; // @[lsu.scala:396:36, :397:35, :416:36] wire ldq_retry_idx_block_6; // @[lsu.scala:416:36] assign ldq_retry_idx_block_6 = _GEN_192; // @[lsu.scala:416:36] wire ldq_wakeup_idx_block_6; // @[lsu.scala:431:36] assign ldq_wakeup_idx_block_6 = _GEN_192; // @[lsu.scala:416:36, :431:36] wire _ldq_retry_idx_T_18 = ldq_6_bits_addr_valid & ldq_6_bits_addr_is_virtual; // @[lsu.scala:208:16, :417:18] wire _ldq_retry_idx_T_19 = ~ldq_retry_idx_block_6; // @[lsu.scala:416:36, :417:42] wire _ldq_retry_idx_T_20 = _ldq_retry_idx_T_18 & _ldq_retry_idx_T_19; // @[lsu.scala:417:{18,39,42}] wire _GEN_193 = block_load_mask_7 \| p1_block_load_mask_7; // @[lsu.scala:396:36, :397:35, :416:36] wire ldq_retry_idx_block_7; // @[lsu.scala:416:36] assign ldq_retry_idx_block_7 = _GEN_193; // @[lsu.scala:416:36] wire ldq_wakeup_idx_block_7; // @[lsu.scala:431:36] assign ldq_wakeup_idx_block_7 = _GEN_193; // @[lsu.scala:416:36, :431:36] wire _ldq_retry_idx_T_21 = ldq_7_bits_addr_valid & ldq_7_bits_addr_is_virtual; // @[lsu.scala:208:16, :417:18] wire _ldq_retry_idx_T_22 = ~ldq_retry_idx_block_7; // @[lsu.scala:416:36, :417:42] wire _ldq_retry_idx_T_23 = _ldq_retry_idx_T_21 & _ldq_retry_idx_T_22; // @[lsu.scala:417:{18,39,42}] wire ldq_retry_idx_temp_vec_7 = _ldq_retry_idx_T_23; // @[util.scala:351:65] wire _GEN_194 = ldq_head == 3'h0; // @[util.scala:351:72] wire _ldq_retry_idx_temp_vec_T; // @[util.scala:351:72] assign _ldq_retry_idx_temp_vec_T = _GEN_194; // @[util.scala:351:72] wire _ldq_wakeup_idx_temp_vec_T; // @[util.scala:351:72] assign _ldq_wakeup_idx_temp_vec_T = _GEN_194; // @[util.scala:351:72] wire _temp_bits_T; // @[lsu.scala:1230:28] assign _temp_bits_T = _GEN_194; // @[util.scala:351:72] wire ldq_retry_idx_temp_vec_0 = _ldq_retry_idx_T_2 & _ldq_retry_idx_temp_vec_T; // @[util.scala:351:{65,72}] wire _GEN_195 = ldq_head < 3'h2; // @[util.scala:351:72] wire _ldq_retry_idx_temp_vec_T_1; // @[util.scala:351:72] assign _ldq_retry_idx_temp_vec_T_1 = _GEN_195; // @[util.scala:351:72] wire _ldq_wakeup_idx_temp_vec_T_1; // @[util.scala:351:72] assign _ldq_wakeup_idx_temp_vec_T_1 = _GEN_195; // @[util.scala:351:72] wire _temp_bits_T_2; // @[lsu.scala:1230:28] assign _temp_bits_T_2 = _GEN_195; // @[util.scala:351:72] wire ldq_retry_idx_temp_vec_1 = _ldq_retry_idx_T_5 & _ldq_retry_idx_temp_vec_T_1; // @[util.scala:351:{65,72}] wire _GEN_196 = ldq_head < 3'h3; // @[util.scala:351:72] wire _ldq_retry_idx_temp_vec_T_2; // @[util.scala:351:72] assign _ldq_retry_idx_temp_vec_T_2 = _GEN_196; // @[util.scala:351:72] wire _ldq_wakeup_idx_temp_vec_T_2; // @[util.scala:351:72] assign _ldq_wakeup_idx_temp_vec_T_2 = _GEN_196; // @[util.scala:351:72] wire _temp_bits_T_4; // @[lsu.scala:1230:28] assign _temp_bits_T_4 = _GEN_196; // @[util.scala:351:72] wire ldq_retry_idx_temp_vec_2 = _ldq_retry_idx_T_8 & _ldq_retry_idx_temp_vec_T_2; // @[util.scala:351:{65,72}] wire _searcher_is_older_T_15 = ldq_head[2]; // @[util.scala:351:72, :363:78] wire _ldq_retry_idx_temp_vec_T_3 = ~_searcher_is_older_T_15; // @[util.scala:351:72, :363:78] wire ldq_retry_idx_temp_vec_3 = _ldq_retry_idx_T_11 & _ldq_retry_idx_temp_vec_T_3; // @[util.scala:351:{65,72}] wire _GEN_197 = ldq_head < 3'h5; // @[util.scala:351:72] wire _ldq_retry_idx_temp_vec_T_4; // @[util.scala:351:72] assign _ldq_retry_idx_temp_vec_T_4 = _GEN_197; // @[util.scala:351:72] wire _ldq_wakeup_idx_temp_vec_T_4; // @[util.scala:351:72] assign _ldq_wakeup_idx_temp_vec_T_4 = _GEN_197; // @[util.scala:351:72] wire _temp_bits_T_8; // @[lsu.scala:1230:28] assign _temp_bits_T_8 = _GEN_197; // @[util.scala:351:72] wire ldq_retry_idx_temp_vec_4 = _ldq_retry_idx_T_14 & _ldq_retry_idx_temp_vec_T_4; // @[util.scala:351:{65,72}] wire _GEN_198 = ldq_head[2:1] != 2'h3; // @[util.scala:351:72] wire _ldq_retry_idx_temp_vec_T_5; // @[util.scala:351:72] assign _ldq_retry_idx_temp_vec_T_5 = _GEN_198; // @[util.scala:351:72] wire _ldq_wakeup_idx_temp_vec_T_5; // @[util.scala:351:72] assign _ldq_wakeup_idx_temp_vec_T_5 = _GEN_198; // @[util.scala:351:72] wire _temp_bits_T_10; // @[lsu.scala:1230:28] assign _temp_bits_T_10 = _GEN_198; // @[util.scala:351:72] wire ldq_retry_idx_temp_vec_5 = _ldq_retry_idx_T_17 & _ldq_retry_idx_temp_vec_T_5; // @[util.scala:351:{65,72}] wire _GEN_199 = ldq_head != 3'h7; // @[util.scala:351:72] wire _ldq_retry_idx_temp_vec_T_6; // @[util.scala:351:72] assign _ldq_retry_idx_temp_vec_T_6 = _GEN_199; // @[util.scala:351:72] wire _ldq_wakeup_idx_temp_vec_T_6; // @[util.scala:351:72] assign _ldq_wakeup_idx_temp_vec_T_6 = _GEN_199; // @[util.scala:351:72] wire _temp_bits_T_12; // @[lsu.scala:1230:28] assign _temp_bits_T_12 = _GEN_199; // @[util.scala:351:72] wire ldq_retry_idx_temp_vec_6 = _ldq_retry_idx_T_20 & _ldq_retry_idx_temp_vec_T_6; // @[util.scala:351:{65,72}] wire [3:0] _ldq_retry_idx_idx_T = {3'h7, ~_ldq_retry_idx_T_20}; // @[Mux.scala:50:70] wire [3:0] _ldq_retry_idx_idx_T_1 = _ldq_retry_idx_T_17 ? 4'hD : _ldq_retry_idx_idx_T; // @[Mux.scala:50:70] wire [3:0] _ldq_retry_idx_idx_T_2 = _ldq_retry_idx_T_14 ? 4'hC : _ldq_retry_idx_idx_T_1; // @[Mux.scala:50:70] wire [3:0] _ldq_retry_idx_idx_T_3 = _ldq_retry_idx_T_11 ? 4'hB : _ldq_retry_idx_idx_T_2; // @[Mux.scala:50:70] wire [3:0] _ldq_retry_idx_idx_T_4 = _ldq_retry_idx_T_8 ? 4'hA : _ldq_retry_idx_idx_T_3; // @[Mux.scala:50:70] wire [3:0] _ldq_retry_idx_idx_T_5 = _ldq_retry_idx_T_5 ? 4'h9 : _ldq_retry_idx_idx_T_4; // @[Mux.scala:50:70] wire [3:0] _ldq_retry_idx_idx_T_6 = _ldq_retry_idx_T_2 ? 4'h8 : _ldq_retry_idx_idx_T_5; // @[Mux.scala:50:70] wire [3:0] _ldq_retry_idx_idx_T_7 = ldq_retry_idx_temp_vec_7 ? 4'h7 : _ldq_retry_idx_idx_T_6; // @[Mux.scala:50:70] wire [3:0] _ldq_retry_idx_idx_T_8 = ldq_retry_idx_temp_vec_6 ? 4'h6 : _ldq_retry_idx_idx_T_7; // @[Mux.scala:50:70] wire [3:0] _ldq_retry_idx_idx_T_9 = ldq_retry_idx_temp_vec_5 ? 4'h5 : _ldq_retry_idx_idx_T_8; // @[Mux.scala:50:70] wire [3:0] _ldq_retry_idx_idx_T_10 = ldq_retry_idx_temp_vec_4 ? 4'h4 : _ldq_retry_idx_idx_T_9; // @[Mux.scala:50:70] wire [3:0] _ldq_retry_idx_idx_T_11 = ldq_retry_idx_temp_vec_3 ? 4'h3 : _ldq_retry_idx_idx_T_10; // @[Mux.scala:50:70] wire [3:0] _ldq_retry_idx_idx_T_12 = ldq_retry_idx_temp_vec_2 ? 4'h2 : _ldq_retry_idx_idx_T_11; // @[Mux.scala:50:70] wire [3:0] _ldq_retry_idx_idx_T_13 = ldq_retry_idx_temp_vec_1 ? 4'h1 : _ldq_retry_idx_idx_T_12; // @[Mux.scala:50:70] wire [3:0] ldq_retry_idx_idx = ldq_retry_idx_temp_vec_0 ? 4'h0 : _ldq_retry_idx_idx_T_13; // @[Mux.scala:50:70] wire [2:0] _ldq_retry_idx_T_24 = ldq_retry_idx_idx[2:0]; // @[Mux.scala:50:70] reg [2:0] ldq_retry_idx; // @[lsu.scala:414:30] wire [2:0] _ldq_retry_e_T = ldq_retry_idx; // @[lsu.scala:414:30] wire [2:0] _can_fire_load_retry_T_2 = ldq_retry_idx; // @[lsu.scala:414:30] wire [2:0] _can_fire_load_retry_T_6 = ldq_retry_idx; // @[lsu.scala:414:30] wire [2:0] _ldq_retry_e_T_1 = _ldq_retry_e_T; wire _stq_retry_idx_T = stq_0_bits_addr_valid & stq_0_bits_addr_is_virtual; // @[lsu.scala:209:16, :423:18] wire _stq_retry_idx_T_1 = stq_1_bits_addr_valid & stq_1_bits_addr_is_virtual; // @[lsu.scala:209:16, :423:18] wire _stq_retry_idx_T_2 = stq_2_bits_addr_valid & stq_2_bits_addr_is_virtual; // @[lsu.scala:209:16, :423:18] wire _stq_retry_idx_T_3 = stq_3_bits_addr_valid & stq_3_bits_addr_is_virtual; // @[lsu.scala:209:16, :423:18] wire _stq_retry_idx_T_4 = stq_4_bits_addr_valid & stq_4_bits_addr_is_virtual; // @[lsu.scala:209:16, :423:18] wire _stq_retry_idx_T_5 = stq_5_bits_addr_valid & stq_5_bits_addr_is_virtual; // @[lsu.scala:209:16, :423:18] wire _stq_retry_idx_T_6 = stq_6_bits_addr_valid & stq_6_bits_addr_is_virtual; // @[lsu.scala:209:16, :423:18] wire _stq_retry_idx_T_7 = stq_7_bits_addr_valid & stq_7_bits_addr_is_virtual; // @[lsu.scala:209:16, :423:18] wire stq_retry_idx_temp_vec_7 = _stq_retry_idx_T_7; // @[util.scala:351:65] wire _stq_retry_idx_temp_vec_T = stq_commit_head == 3'h0; // @[util.scala:351:72] wire stq_retry_idx_temp_vec_0 = _stq_retry_idx_T & _stq_retry_idx_temp_vec_T; // @[util.scala:351:{65,72}] wire _stq_retry_idx_temp_vec_T_1 = stq_commit_head < 3'h2; // @[util.scala:351:72] wire stq_retry_idx_temp_vec_1 = _stq_retry_idx_T_1 & _stq_retry_idx_temp_vec_T_1; // @[util.scala:351:{65,72}] wire _stq_retry_idx_temp_vec_T_2 = stq_commit_head < 3'h3; // @[util.scala:351:72] wire stq_retry_idx_temp_vec_2 = _stq_retry_idx_T_2 & _stq_retry_idx_temp_vec_T_2; // @[util.scala:351:{65,72}] wire _stq_retry_idx_temp_vec_T_3 = ~(stq_commit_head[2]); // @[util.scala:351:72] wire stq_retry_idx_temp_vec_3 = _stq_retry_idx_T_3 & _stq_retry_idx_temp_vec_T_3; // @[util.scala:351:{65,72}] wire _stq_retry_idx_temp_vec_T_4 = stq_commit_head < 3'h5; // @[util.scala:351:72] wire stq_retry_idx_temp_vec_4 = _stq_retry_idx_T_4 & _stq_retry_idx_temp_vec_T_4; // @[util.scala:351:{65,72}] wire _stq_retry_idx_temp_vec_T_5 = stq_commit_head[2:1] != 2'h3; // @[util.scala:351:72] wire stq_retry_idx_temp_vec_5 = _stq_retry_idx_T_5 & _stq_retry_idx_temp_vec_T_5; // @[util.scala:351:{65,72}] wire _stq_retry_idx_temp_vec_T_6 = stq_commit_head != 3'h7; // @[util.scala:351:72] wire stq_retry_idx_temp_vec_6 = _stq_retry_idx_T_6 & _stq_retry_idx_temp_vec_T_6; // @[util.scala:351:{65,72}] wire [3:0] _stq_retry_idx_idx_T = {3'h7, ~_stq_retry_idx_T_6}; // @[Mux.scala:50:70] wire [3:0] _stq_retry_idx_idx_T_1 = _stq_retry_idx_T_5 ? 4'hD : _stq_retry_idx_idx_T; // @[Mux.scala:50:70] wire [3:0] _stq_retry_idx_idx_T_2 = _stq_retry_idx_T_4 ? 4'hC : _stq_retry_idx_idx_T_1; // @[Mux.scala:50:70] wire [3:0] _stq_retry_idx_idx_T_3 = _stq_retry_idx_T_3 ? 4'hB : _stq_retry_idx_idx_T_2; // @[Mux.scala:50:70] wire [3:0] _stq_retry_idx_idx_T_4 = _stq_retry_idx_T_2 ? 4'hA : _stq_retry_idx_idx_T_3; // @[Mux.scala:50:70] wire [3:0] _stq_retry_idx_idx_T_5 = _stq_retry_idx_T_1 ? 4'h9 : _stq_retry_idx_idx_T_4; // @[Mux.scala:50:70] wire [3:0] _stq_retry_idx_idx_T_6 = _stq_retry_idx_T ? 4'h8 : _stq_retry_idx_idx_T_5; // @[Mux.scala:50:70] wire [3:0] _stq_retry_idx_idx_T_7 = stq_retry_idx_temp_vec_7 ? 4'h7 : _stq_retry_idx_idx_T_6; // @[Mux.scala:50:70] wire [3:0] _stq_retry_idx_idx_T_8 = stq_retry_idx_temp_vec_6 ? 4'h6 : _stq_retry_idx_idx_T_7; // @[Mux.scala:50:70] wire [3:0] _stq_retry_idx_idx_T_9 = stq_retry_idx_temp_vec_5 ? 4'h5 : _stq_retry_idx_idx_T_8; // @[Mux.scala:50:70] wire [3:0] _stq_retry_idx_idx_T_10 = stq_retry_idx_temp_vec_4 ? 4'h4 : _stq_retry_idx_idx_T_9; // @[Mux.scala:50:70] wire [3:0] _stq_retry_idx_idx_T_11 = stq_retry_idx_temp_vec_3 ? 4'h3 : _stq_retry_idx_idx_T_10; // @[Mux.scala:50:70] wire [3:0] _stq_retry_idx_idx_T_12 = stq_retry_idx_temp_vec_2 ? 4'h2 : _stq_retry_idx_idx_T_11; // @[Mux.scala:50:70] wire [3:0] _stq_retry_idx_idx_T_13 = stq_retry_idx_temp_vec_1 ? 4'h1 : _stq_retry_idx_idx_T_12; // @[Mux.scala:50:70] wire [3:0] stq_retry_idx_idx = stq_retry_idx_temp_vec_0 ? 4'h0 : _stq_retry_idx_idx_T_13; // @[Mux.scala:50:70] wire [2:0] _stq_retry_idx_T_8 = stq_retry_idx_idx[2:0]; // @[Mux.scala:50:70] reg [2:0] stq_retry_idx; // @[lsu.scala:421:30] wire [2:0] _stq_retry_e_T = stq_retry_idx; // @[lsu.scala:421:30] wire [2:0] _stq_retry_e_T_1 = _stq_retry_e_T; wire _ldq_wakeup_idx_T = ~ldq_0_bits_executed; // @[lsu.scala:208:16, :432:21] wire _ldq_wakeup_idx_T_1 = ldq_0_bits_addr_valid & _ldq_wakeup_idx_T; // @[lsu.scala:208:16, :432:{18,21}] wire _ldq_wakeup_idx_T_2 = ~ldq_0_bits_succeeded; // @[lsu.scala:208:16, :432:36] wire _ldq_wakeup_idx_T_3 = _ldq_wakeup_idx_T_1 & _ldq_wakeup_idx_T_2; // @[lsu.scala:432:{18,33,36}] wire _ldq_wakeup_idx_T_4 = ~ldq_0_bits_addr_is_virtual; // @[lsu.scala:208:16, :432:52] wire _ldq_wakeup_idx_T_5 = _ldq_wakeup_idx_T_3 & _ldq_wakeup_idx_T_4; // @[lsu.scala:432:{33,49,52}] wire _ldq_wakeup_idx_T_6 = ~ldq_wakeup_idx_block; // @[lsu.scala:431:36, :432:74] wire _ldq_wakeup_idx_T_7 = _ldq_wakeup_idx_T_5 & _ldq_wakeup_idx_T_6; // @[lsu.scala:432:{49,71,74}] wire _ldq_wakeup_idx_T_8 = ~ldq_1_bits_executed; // @[lsu.scala:208:16, :432:21] wire _ldq_wakeup_idx_T_9 = ldq_1_bits_addr_valid & _ldq_wakeup_idx_T_8; // @[lsu.scala:208:16, :432:{18,21}] wire _ldq_wakeup_idx_T_10 = ~ldq_1_bits_succeeded; // @[lsu.scala:208:16, :432:36] wire _ldq_wakeup_idx_T_11 = _ldq_wakeup_idx_T_9 & _ldq_wakeup_idx_T_10; // @[lsu.scala:432:{18,33,36}] wire _ldq_wakeup_idx_T_12 = ~ldq_1_bits_addr_is_virtual; // @[lsu.scala:208:16, :432:52] wire _ldq_wakeup_idx_T_13 = _ldq_wakeup_idx_T_11 & _ldq_wakeup_idx_T_12; // @[lsu.scala:432:{33,49,52}] wire _ldq_wakeup_idx_T_14 = ~ldq_wakeup_idx_block_1; // @[lsu.scala:431:36, :432:74] wire _ldq_wakeup_idx_T_15 = _ldq_wakeup_idx_T_13 & _ldq_wakeup_idx_T_14; // @[lsu.scala:432:{49,71,74}] wire _ldq_wakeup_idx_T_16 = ~ldq_2_bits_executed; // @[lsu.scala:208:16, :432:21] wire _ldq_wakeup_idx_T_17 = ldq_2_bits_addr_valid & _ldq_wakeup_idx_T_16; // @[lsu.scala:208:16, :432:{18,21}] wire _ldq_wakeup_idx_T_18 = ~ldq_2_bits_succeeded; // @[lsu.scala:208:16, :432:36] wire _ldq_wakeup_idx_T_19 = _ldq_wakeup_idx_T_17 & _ldq_wakeup_idx_T_18; // @[lsu.scala:432:{18,33,36}] wire _ldq_wakeup_idx_T_20 = ~ldq_2_bits_addr_is_virtual; // @[lsu.scala:208:16, :432:52] wire _ldq_wakeup_idx_T_21 = _ldq_wakeup_idx_T_19 & _ldq_wakeup_idx_T_20; // @[lsu.scala:432:{33,49,52}] wire _ldq_wakeup_idx_T_22 = ~ldq_wakeup_idx_block_2; // @[lsu.scala:431:36, :432:74] wire _ldq_wakeup_idx_T_23 = _ldq_wakeup_idx_T_21 & _ldq_wakeup_idx_T_22; // @[lsu.scala:432:{49,71,74}] wire _ldq_wakeup_idx_T_24 = ~ldq_3_bits_executed; // @[lsu.scala:208:16, :432:21] wire _ldq_wakeup_idx_T_25 = ldq_3_bits_addr_valid & _ldq_wakeup_idx_T_24; // @[lsu.scala:208:16, :432:{18,21}] wire _ldq_wakeup_idx_T_26 = ~ldq_3_bits_succeeded; // @[lsu.scala:208:16, :432:36] wire _ldq_wakeup_idx_T_27 = _ldq_wakeup_idx_T_25 & _ldq_wakeup_idx_T_26; // @[lsu.scala:432:{18,33,36}] wire _ldq_wakeup_idx_T_28 = ~ldq_3_bits_addr_is_virtual; // @[lsu.scala:208:16, :432:52] wire _ldq_wakeup_idx_T_29 = _ldq_wakeup_idx_T_27 & _ldq_wakeup_idx_T_28; // @[lsu.scala:432:{33,49,52}] wire _ldq_wakeup_idx_T_30 = ~ldq_wakeup_idx_block_3; // @[lsu.scala:431:36, :432:74] wire _ldq_wakeup_idx_T_31 = _ldq_wakeup_idx_T_29 & _ldq_wakeup_idx_T_30; // @[lsu.scala:432:{49,71,74}] wire _ldq_wakeup_idx_T_32 = ~ldq_4_bits_executed; // @[lsu.scala:208:16, :432:21] wire _ldq_wakeup_idx_T_33 = ldq_4_bits_addr_valid & _ldq_wakeup_idx_T_32; // @[lsu.scala:208:16, :432:{18,21}] wire _ldq_wakeup_idx_T_34 = ~ldq_4_bits_succeeded; // @[lsu.scala:208:16, :432:36] wire _ldq_wakeup_idx_T_35 = _ldq_wakeup_idx_T_33 & _ldq_wakeup_idx_T_34; // @[lsu.scala:432:{18,33,36}] wire _ldq_wakeup_idx_T_36 = ~ldq_4_bits_addr_is_virtual; // @[lsu.scala:208:16, :432:52] wire _ldq_wakeup_idx_T_37 = _ldq_wakeup_idx_T_35 & _ldq_wakeup_idx_T_36; // @[lsu.scala:432:{33,49,52}] wire _ldq_wakeup_idx_T_38 = ~ldq_wakeup_idx_block_4; // @[lsu.scala:431:36, :432:74] wire _ldq_wakeup_idx_T_39 = _ldq_wakeup_idx_T_37 & _ldq_wakeup_idx_T_38; // @[lsu.scala:432:{49,71,74}] wire _ldq_wakeup_idx_T_40 = ~ldq_5_bits_executed; // @[lsu.scala:208:16, :432:21] wire _ldq_wakeup_idx_T_41 = ldq_5_bits_addr_valid & _ldq_wakeup_idx_T_40; // @[lsu.scala:208:16, :432:{18,21}] wire _ldq_wakeup_idx_T_42 = ~ldq_5_bits_succeeded; // @[lsu.scala:208:16, :432:36] wire _ldq_wakeup_idx_T_43 = _ldq_wakeup_idx_T_41 & _ldq_wakeup_idx_T_42; // @[lsu.scala:432:{18,33,36}] wire _ldq_wakeup_idx_T_44 = ~ldq_5_bits_addr_is_virtual; // @[lsu.scala:208:16, :432:52] wire _ldq_wakeup_idx_T_45 = _ldq_wakeup_idx_T_43 & _ldq_wakeup_idx_T_44; // @[lsu.scala:432:{33,49,52}] wire _ldq_wakeup_idx_T_46 = ~ldq_wakeup_idx_block_5; // @[lsu.scala:431:36, :432:74] wire _ldq_wakeup_idx_T_47 = _ldq_wakeup_idx_T_45 & _ldq_wakeup_idx_T_46; // @[lsu.scala:432:{49,71,74}] wire _ldq_wakeup_idx_T_48 = ~ldq_6_bits_executed; // @[lsu.scala:208:16, :432:21] wire _ldq_wakeup_idx_T_49 = ldq_6_bits_addr_valid & _ldq_wakeup_idx_T_48; // @[lsu.scala:208:16, :432:{18,21}] wire _ldq_wakeup_idx_T_50 = ~ldq_6_bits_succeeded; // @[lsu.scala:208:16, :432:36] wire _ldq_wakeup_idx_T_51 = _ldq_wakeup_idx_T_49 & _ldq_wakeup_idx_T_50; // @[lsu.scala:432:{18,33,36}] wire _ldq_wakeup_idx_T_52 = ~ldq_6_bits_addr_is_virtual; // @[lsu.scala:208:16, :432:52] wire _ldq_wakeup_idx_T_53 = _ldq_wakeup_idx_T_51 & _ldq_wakeup_idx_T_52; // @[lsu.scala:432:{33,49,52}] wire _ldq_wakeup_idx_T_54 = ~ldq_wakeup_idx_block_6; // @[lsu.scala:431:36, :432:74] wire _ldq_wakeup_idx_T_55 = _ldq_wakeup_idx_T_53 & _ldq_wakeup_idx_T_54; // @[lsu.scala:432:{49,71,74}] wire _ldq_wakeup_idx_T_56 = ~ldq_7_bits_executed; // @[lsu.scala:208:16, :432:21] wire _ldq_wakeup_idx_T_57 = ldq_7_bits_addr_valid & _ldq_wakeup_idx_T_56; // @[lsu.scala:208:16, :432:{18,21}] wire _ldq_wakeup_idx_T_58 = ~ldq_7_bits_succeeded; // @[lsu.scala:208:16, :432:36] wire _ldq_wakeup_idx_T_59 = _ldq_wakeup_idx_T_57 & _ldq_wakeup_idx_T_58; // @[lsu.scala:432:{18,33,36}] wire _ldq_wakeup_idx_T_60 = ~ldq_7_bits_addr_is_virtual; // @[lsu.scala:208:16, :432:52] wire _ldq_wakeup_idx_T_61 = _ldq_wakeup_idx_T_59 & _ldq_wakeup_idx_T_60; // @[lsu.scala:432:{33,49,52}] wire _ldq_wakeup_idx_T_62 = ~ldq_wakeup_idx_block_7; // @[lsu.scala:431:36, :432:74] wire _ldq_wakeup_idx_T_63 = _ldq_wakeup_idx_T_61 & _ldq_wakeup_idx_T_62; // @[lsu.scala:432:{49,71,74}] wire ldq_wakeup_idx_temp_vec_7 = _ldq_wakeup_idx_T_63; // @[util.scala:351:65] wire ldq_wakeup_idx_temp_vec_0 = _ldq_wakeup_idx_T_7 & _ldq_wakeup_idx_temp_vec_T; // @[util.scala:351:{65,72}] wire ldq_wakeup_idx_temp_vec_1 = _ldq_wakeup_idx_T_15 & _ldq_wakeup_idx_temp_vec_T_1; // @[util.scala:351:{65,72}] wire ldq_wakeup_idx_temp_vec_2 = _ldq_wakeup_idx_T_23 & _ldq_wakeup_idx_temp_vec_T_2; // @[util.scala:351:{65,72}] wire _ldq_wakeup_idx_temp_vec_T_3 = ~_searcher_is_older_T_15; // @[util.scala:351:72, :363:78] wire ldq_wakeup_idx_temp_vec_3 = _ldq_wakeup_idx_T_31 & _ldq_wakeup_idx_temp_vec_T_3; // @[util.scala:351:{65,72}] wire ldq_wakeup_idx_temp_vec_4 = _ldq_wakeup_idx_T_39 & _ldq_wakeup_idx_temp_vec_T_4; // @[util.scala:351:{65,72}] wire ldq_wakeup_idx_temp_vec_5 = _ldq_wakeup_idx_T_47 & _ldq_wakeup_idx_temp_vec_T_5; // @[util.scala:351:{65,72}] wire ldq_wakeup_idx_temp_vec_6 = _ldq_wakeup_idx_T_55 & _ldq_wakeup_idx_temp_vec_T_6; // @[util.scala:351:{65,72}] wire [3:0] _ldq_wakeup_idx_idx_T = {3'h7, ~_ldq_wakeup_idx_T_55}; // @[Mux.scala:50:70] wire [3:0] _ldq_wakeup_idx_idx_T_1 = _ldq_wakeup_idx_T_47 ? 4'hD : _ldq_wakeup_idx_idx_T; // @[Mux.scala:50:70] wire [3:0] _ldq_wakeup_idx_idx_T_2 = _ldq_wakeup_idx_T_39 ? 4'hC : _ldq_wakeup_idx_idx_T_1; // @[Mux.scala:50:70] wire [3:0] _ldq_wakeup_idx_idx_T_3 = _ldq_wakeup_idx_T_31 ? 4'hB : _ldq_wakeup_idx_idx_T_2; // @[Mux.scala:50:70] wire [3:0] _ldq_wakeup_idx_idx_T_4 = _ldq_wakeup_idx_T_23 ? 4'hA : _ldq_wakeup_idx_idx_T_3; // @[Mux.scala:50:70] wire [3:0] _ldq_wakeup_idx_idx_T_5 = _ldq_wakeup_idx_T_15 ? 4'h9 : _ldq_wakeup_idx_idx_T_4; // @[Mux.scala:50:70] wire [3:0] _ldq_wakeup_idx_idx_T_6 = _ldq_wakeup_idx_T_7 ? 4'h8 : _ldq_wakeup_idx_idx_T_5; // @[Mux.scala:50:70] wire [3:0] _ldq_wakeup_idx_idx_T_7 = ldq_wakeup_idx_temp_vec_7 ? 4'h7 : _ldq_wakeup_idx_idx_T_6; // @[Mux.scala:50:70] wire [3:0] _ldq_wakeup_idx_idx_T_8 = ldq_wakeup_idx_temp_vec_6 ? 4'h6 : _ldq_wakeup_idx_idx_T_7; // @[Mux.scala:50:70] wire [3:0] _ldq_wakeup_idx_idx_T_9 = ldq_wakeup_idx_temp_vec_5 ? 4'h5 : _ldq_wakeup_idx_idx_T_8; // @[Mux.scala:50:70] wire [3:0] _ldq_wakeup_idx_idx_T_10 = ldq_wakeup_idx_temp_vec_4 ? 4'h4 : _ldq_wakeup_idx_idx_T_9; // @[Mux.scala:50:70] wire [3:0] _ldq_wakeup_idx_idx_T_11 = ldq_wakeup_idx_temp_vec_3 ? 4'h3 : _ldq_wakeup_idx_idx_T_10; // @[Mux.scala:50:70] wire [3:0] _ldq_wakeup_idx_idx_T_12 = ldq_wakeup_idx_temp_vec_2 ? 4'h2 : _ldq_wakeup_idx_idx_T_11; // @[Mux.scala:50:70] wire [3:0] _ldq_wakeup_idx_idx_T_13 = ldq_wakeup_idx_temp_vec_1 ? 4'h1 : _ldq_wakeup_idx_idx_T_12; // @[Mux.scala:50:70] wire [3:0] ldq_wakeup_idx_idx = ldq_wakeup_idx_temp_vec_0 ? 4'h0 : _ldq_wakeup_idx_idx_T_13; // @[Mux.scala:50:70] wire [2:0] _ldq_wakeup_idx_T_64 = ldq_wakeup_idx_idx[2:0]; // @[Mux.scala:50:70] reg [2:0] ldq_wakeup_idx; // @[lsu.scala:429:31] wire [2:0] _ldq_wakeup_e_T = ldq_wakeup_idx; // @[lsu.scala:429:31] wire [2:0] _can_fire_load_wakeup_T_9 = ldq_wakeup_idx; // @[lsu.scala:429:31] wire [2:0] _can_fire_load_wakeup_T_13 = ldq_wakeup_idx; // @[lsu.scala:429:31] wire [2:0] _ldq_wakeup_e_T_1 = _ldq_wakeup_e_T; wire _can_fire_load_incoming_T = exe_req_0_valid & exe_req_0_bits_uop_ctrl_is_load; // @[lsu.scala:383:25, :440:63] wire can_fire_load_incoming_0 = _can_fire_load_incoming_T; // @[lsu.scala:263:49, :440:63] wire _will_fire_load_incoming_0_will_fire_T_3 = can_fire_load_incoming_0; // @[lsu.scala:263:49, :533:32] wire _GEN_200 = exe_req_0_valid & exe_req_0_bits_uop_ctrl_is_sta; // @[lsu.scala:383:25, :443:63] wire _can_fire_stad_incoming_T; // @[lsu.scala:443:63] assign _can_fire_stad_incoming_T = _GEN_200; // @[lsu.scala:443:63] wire _can_fire_sta_incoming_T; // @[lsu.scala:447:63] assign _can_fire_sta_incoming_T = _GEN_200; // @[lsu.scala:443:63, :447:63] wire _can_fire_stad_incoming_T_1 = _can_fire_stad_incoming_T & exe_req_0_bits_uop_ctrl_is_std; // @[lsu.scala:383:25, :443:63, :444:63] wire can_fire_stad_incoming_0 = _can_fire_stad_incoming_T_1; // @[lsu.scala:263:49, :444:63] wire _can_fire_sta_incoming_T_1 = ~exe_req_0_bits_uop_ctrl_is_std; // @[lsu.scala:383:25, :448:66] wire _can_fire_sta_incoming_T_2 = _can_fire_sta_incoming_T & _can_fire_sta_incoming_T_1; // @[lsu.scala:447:63, :448:{63,66}] wire can_fire_sta_incoming_0 = _can_fire_sta_incoming_T_2; // @[lsu.scala:263:49, :448:63] wire _can_fire_std_incoming_T = exe_req_0_valid & exe_req_0_bits_uop_ctrl_is_std; // @[lsu.scala:383:25, :451:63] wire _can_fire_std_incoming_T_1 = ~exe_req_0_bits_uop_ctrl_is_sta; // @[lsu.scala:383:25, :452:66] wire _can_fire_std_incoming_T_2 = _can_fire_std_incoming_T & _can_fire_std_incoming_T_1; // @[lsu.scala:451:63, :452:{63,66}] wire can_fire_std_incoming_0 = _can_fire_std_incoming_T_2; // @[lsu.scala:263:49, :452:63] wire _will_fire_std_incoming_0_will_fire_T_3 = can_fire_std_incoming_0; // @[lsu.scala:263:49, :533:32] wire _can_fire_sfence_T = exe_req_0_valid & exe_req_0_bits_sfence_valid; // @[lsu.scala:383:25, :455:63] wire can_fire_sfence_0 = _can_fire_sfence_T; // @[lsu.scala:263:49, :455:63] wire can_fire_release_0 = _can_fire_release_T; // @[lsu.scala:263:49, :459:66] wire _will_fire_release_0_will_fire_T_3 = can_fire_release_0; // @[lsu.scala:263:49, :533:32] wire [6:0] mem_ldq_retry_e_out_bits_uop_uopc = _GEN_94[_ldq_retry_e_T_1]; // @[util.scala:106:23] wire [31:0] mem_ldq_retry_e_out_bits_uop_inst = _GEN_95[_ldq_retry_e_T_1]; // @[util.scala:106:23] wire [31:0] mem_ldq_retry_e_out_bits_uop_debug_inst = _GEN_96[_ldq_retry_e_T_1]; // @[util.scala:106:23] wire mem_ldq_retry_e_out_bits_uop_is_rvc = _GEN_97[_ldq_retry_e_T_1]; // @[util.scala:106:23] wire [39:0] mem_ldq_retry_e_out_bits_uop_debug_pc = _GEN_98[_ldq_retry_e_T_1]; // @[util.scala:106:23] wire [2:0] mem_ldq_retry_e_out_bits_uop_iq_type = _GEN_99[_ldq_retry_e_T_1]; // @[util.scala:106:23] wire [9:0] mem_ldq_retry_e_out_bits_uop_fu_code = _GEN_100[_ldq_retry_e_T_1]; // @[util.scala:106:23] wire [3:0] mem_ldq_retry_e_out_bits_uop_ctrl_br_type = _GEN_101[_ldq_retry_e_T_1]; // @[util.scala:106:23] wire [1:0] mem_ldq_retry_e_out_bits_uop_ctrl_op1_sel = _GEN_102[_ldq_retry_e_T_1]; // @[util.scala:106:23] wire [2:0] mem_ldq_retry_e_out_bits_uop_ctrl_op2_sel = _GEN_103[_ldq_retry_e_T_1]; // @[util.scala:106:23] wire [2:0] mem_ldq_retry_e_out_bits_uop_ctrl_imm_sel = _GEN_104[_ldq_retry_e_T_1]; // @[util.scala:106:23] wire [4:0] mem_ldq_retry_e_out_bits_uop_ctrl_op_fcn = _GEN_105[_ldq_retry_e_T_1]; // @[util.scala:106:23] wire mem_ldq_retry_e_out_bits_uop_ctrl_fcn_dw = _GEN_106[_ldq_retry_e_T_1]; // @[util.scala:106:23] wire [2:0] mem_ldq_retry_e_out_bits_uop_ctrl_csr_cmd = _GEN_107[_ldq_retry_e_T_1]; // @[util.scala:106:23] wire mem_ldq_retry_e_out_bits_uop_ctrl_is_load = _GEN_108[_ldq_retry_e_T_1]; // @[util.scala:106:23] wire mem_ldq_retry_e_out_bits_uop_ctrl_is_sta = _GEN_109[_ldq_retry_e_T_1]; // @[util.scala:106:23] wire mem_ldq_retry_e_out_bits_uop_ctrl_is_std = _GEN_110[_ldq_retry_e_T_1]; // @[util.scala:106:23] wire [1:0] mem_ldq_retry_e_out_bits_uop_iw_state = _GEN_111[_ldq_retry_e_T_1]; // @[util.scala:106:23] wire mem_ldq_retry_e_out_bits_uop_iw_p1_poisoned = _GEN_112[_ldq_retry_e_T_1]; // @[util.scala:106:23] wire mem_ldq_retry_e_out_bits_uop_iw_p2_poisoned = _GEN_113[_ldq_retry_e_T_1]; // @[util.scala:106:23] wire mem_ldq_retry_e_out_bits_uop_is_br = _GEN_114[_ldq_retry_e_T_1]; // @[util.scala:106:23] wire mem_ldq_retry_e_out_bits_uop_is_jalr = _GEN_115[_ldq_retry_e_T_1]; // @[util.scala:106:23] wire mem_ldq_retry_e_out_bits_uop_is_jal = _GEN_116[_ldq_retry_e_T_1]; // @[util.scala:106:23] wire mem_ldq_retry_e_out_bits_uop_is_sfb = _GEN_117[_ldq_retry_e_T_1]; // @[util.scala:106:23] wire [2:0] mem_ldq_retry_e_out_bits_uop_br_tag = _GEN_119[_ldq_retry_e_T_1]; // @[util.scala:106:23] wire [3:0] mem_ldq_retry_e_out_bits_uop_ftq_idx = _GEN_120[_ldq_retry_e_T_1]; // @[util.scala:106:23] wire mem_ldq_retry_e_out_bits_uop_edge_inst = _GEN_121[_ldq_retry_e_T_1]; // @[util.scala:106:23] wire [5:0] mem_ldq_retry_e_out_bits_uop_pc_lob = _GEN_122[_ldq_retry_e_T_1]; // @[util.scala:106:23] wire mem_ldq_retry_e_out_bits_uop_taken = _GEN_123[_ldq_retry_e_T_1]; // @[util.scala:106:23] wire [19:0] mem_ldq_retry_e_out_bits_uop_imm_packed = _GEN_124[_ldq_retry_e_T_1]; // @[util.scala:106:23] wire [11:0] mem_ldq_retry_e_out_bits_uop_csr_addr = _GEN_125[_ldq_retry_e_T_1]; // @[util.scala:106:23] wire [4:0] mem_ldq_retry_e_out_bits_uop_rob_idx = _GEN_126[_ldq_retry_e_T_1]; // @[util.scala:106:23] wire [2:0] mem_ldq_retry_e_out_bits_uop_ldq_idx = _GEN_127[_ldq_retry_e_T_1]; // @[util.scala:106:23] wire [2:0] mem_ldq_retry_e_out_bits_uop_stq_idx = _GEN_128[_ldq_retry_e_T_1]; // @[util.scala:106:23] wire [1:0] mem_ldq_retry_e_out_bits_uop_rxq_idx = _GEN_129[_ldq_retry_e_T_1]; // @[util.scala:106:23] wire [5:0] mem_ldq_retry_e_out_bits_uop_pdst = _GEN_130[_ldq_retry_e_T_1]; // @[util.scala:106:23] wire [5:0] mem_ldq_retry_e_out_bits_uop_prs1 = _GEN_131[_ldq_retry_e_T_1]; // @[util.scala:106:23] wire [5:0] mem_ldq_retry_e_out_bits_uop_prs2 = _GEN_132[_ldq_retry_e_T_1]; // @[util.scala:106:23] wire [5:0] mem_ldq_retry_e_out_bits_uop_prs3 = _GEN_133[_ldq_retry_e_T_1]; // @[util.scala:106:23] wire mem_ldq_retry_e_out_bits_uop_prs1_busy = _GEN_134[_ldq_retry_e_T_1]; // @[util.scala:106:23] wire mem_ldq_retry_e_out_bits_uop_prs2_busy = _GEN_135[_ldq_retry_e_T_1]; // @[util.scala:106:23] wire mem_ldq_retry_e_out_bits_uop_prs3_busy = _GEN_136[_ldq_retry_e_T_1]; // @[util.scala:106:23] wire [5:0] mem_ldq_retry_e_out_bits_uop_stale_pdst = _GEN_137[_ldq_retry_e_T_1]; // @[util.scala:106:23] wire mem_ldq_retry_e_out_bits_uop_exception = _GEN_138[_ldq_retry_e_T_1]; // @[util.scala:106:23] wire [63:0] mem_ldq_retry_e_out_bits_uop_exc_cause = _GEN_139[_ldq_retry_e_T_1]; // @[util.scala:106:23] wire mem_ldq_retry_e_out_bits_uop_bypassable = _GEN_140[_ldq_retry_e_T_1]; // @[util.scala:106:23] wire [4:0] mem_ldq_retry_e_out_bits_uop_mem_cmd = _GEN_141[_ldq_retry_e_T_1]; // @[util.scala:106:23] wire [1:0] mem_ldq_retry_e_out_bits_uop_mem_size = _GEN_142[_ldq_retry_e_T_1]; // @[util.scala:106:23] wire mem_ldq_retry_e_out_bits_uop_mem_signed = _GEN_143[_ldq_retry_e_T_1]; // @[util.scala:106:23] wire mem_ldq_retry_e_out_bits_uop_is_fence = _GEN_144[_ldq_retry_e_T_1]; // @[util.scala:106:23] wire mem_ldq_retry_e_out_bits_uop_is_fencei = _GEN_145[_ldq_retry_e_T_1]; // @[util.scala:106:23] wire mem_ldq_retry_e_out_bits_uop_is_amo = _GEN_146[_ldq_retry_e_T_1]; // @[util.scala:106:23] wire mem_ldq_retry_e_out_bits_uop_uses_ldq = _GEN_147[_ldq_retry_e_T_1]; // @[util.scala:106:23] wire mem_ldq_retry_e_out_bits_uop_uses_stq = _GEN_148[_ldq_retry_e_T_1]; // @[util.scala:106:23] wire mem_ldq_retry_e_out_bits_uop_is_sys_pc2epc = _GEN_149[_ldq_retry_e_T_1]; // @[util.scala:106:23] wire mem_ldq_retry_e_out_bits_uop_is_unique = _GEN_150[_ldq_retry_e_T_1]; // @[util.scala:106:23] wire mem_ldq_retry_e_out_bits_uop_flush_on_commit = _GEN_151[_ldq_retry_e_T_1]; // @[util.scala:106:23] wire mem_ldq_retry_e_out_bits_uop_ldst_is_rs1 = _GEN_152[_ldq_retry_e_T_1]; // @[util.scala:106:23] wire [5:0] mem_ldq_retry_e_out_bits_uop_ldst = _GEN_153[_ldq_retry_e_T_1]; // @[util.scala:106:23] wire [5:0] mem_ldq_retry_e_out_bits_uop_lrs1 = _GEN_154[_ldq_retry_e_T_1]; // @[util.scala:106:23] wire [5:0] mem_ldq_retry_e_out_bits_uop_lrs2 = _GEN_155[_ldq_retry_e_T_1]; // @[util.scala:106:23] wire [5:0] mem_ldq_retry_e_out_bits_uop_lrs3 = _GEN_156[_ldq_retry_e_T_1]; // @[util.scala:106:23] wire mem_ldq_retry_e_out_bits_uop_ldst_val = _GEN_157[_ldq_retry_e_T_1]; // @[util.scala:106:23] wire [1:0] mem_ldq_retry_e_out_bits_uop_dst_rtype = _GEN_158[_ldq_retry_e_T_1]; // @[util.scala:106:23] wire [1:0] mem_ldq_retry_e_out_bits_uop_lrs1_rtype = _GEN_159[_ldq_retry_e_T_1]; // @[util.scala:106:23] wire [1:0] mem_ldq_retry_e_out_bits_uop_lrs2_rtype = _GEN_160[_ldq_retry_e_T_1]; // @[util.scala:106:23] wire mem_ldq_retry_e_out_bits_uop_frs3_en = _GEN_161[_ldq_retry_e_T_1]; // @[util.scala:106:23] wire mem_ldq_retry_e_out_bits_uop_fp_val = _GEN_162[_ldq_retry_e_T_1]; // @[util.scala:106:23] wire mem_ldq_retry_e_out_bits_uop_fp_single = _GEN_163[_ldq_retry_e_T_1]; // @[util.scala:106:23] wire mem_ldq_retry_e_out_bits_uop_xcpt_pf_if = _GEN_164[_ldq_retry_e_T_1]; // @[util.scala:106:23] wire mem_ldq_retry_e_out_bits_uop_xcpt_ae_if = _GEN_165[_ldq_retry_e_T_1]; // @[util.scala:106:23] wire mem_ldq_retry_e_out_bits_uop_xcpt_ma_if = _GEN_166[_ldq_retry_e_T_1]; // @[util.scala:106:23] wire mem_ldq_retry_e_out_bits_uop_bp_debug_if = _GEN_167[_ldq_retry_e_T_1]; // @[util.scala:106:23] wire mem_ldq_retry_e_out_bits_uop_bp_xcpt_if = _GEN_168[_ldq_retry_e_T_1]; // @[util.scala:106:23] wire [1:0] mem_ldq_retry_e_out_bits_uop_debug_fsrc = _GEN_169[_ldq_retry_e_T_1]; // @[util.scala:106:23] wire [1:0] mem_ldq_retry_e_out_bits_uop_debug_tsrc = _GEN_170[_ldq_retry_e_T_1]; // @[util.scala:106:23] wire mem_ldq_retry_e_out_bits_addr_valid = _GEN_171[_ldq_retry_e_T_1]; // @[util.scala:106:23] wire [39:0] mem_ldq_retry_e_out_bits_addr_bits = _GEN_172[_ldq_retry_e_T_1]; // @[util.scala:106:23] wire mem_ldq_retry_e_out_bits_addr_is_virtual = _GEN_173[_ldq_retry_e_T_1]; // @[util.scala:106:23] wire mem_ldq_retry_e_out_bits_addr_is_uncacheable = _GEN_174[_ldq_retry_e_T_1]; // @[util.scala:106:23] wire mem_ldq_retry_e_out_bits_executed = _GEN_175[_ldq_retry_e_T_1]; // @[util.scala:106:23] wire mem_ldq_retry_e_out_bits_succeeded = _GEN_176[_ldq_retry_e_T_1]; // @[util.scala:106:23] wire mem_ldq_retry_e_out_bits_order_fail = _GEN_177[_ldq_retry_e_T_1]; // @[util.scala:106:23] wire mem_ldq_retry_e_out_bits_observed = _GEN_178[_ldq_retry_e_T_1]; // @[util.scala:106:23] wire [7:0] mem_ldq_retry_e_out_bits_st_dep_mask = _GEN_179[_ldq_retry_e_T_1]; // @[util.scala:106:23] wire [2:0] mem_ldq_retry_e_out_bits_youngest_stq_idx = _GEN_180[_ldq_retry_e_T_1]; // @[util.scala:106:23] wire mem_ldq_retry_e_out_bits_forward_std_val = _GEN_181[_ldq_retry_e_T_1]; // @[util.scala:106:23] wire [2:0] mem_ldq_retry_e_out_bits_forward_stq_idx = _GEN_182[_ldq_retry_e_T_1]; // @[util.scala:106:23] wire [63:0] mem_ldq_retry_e_out_bits_debug_wb_data = _GEN_183[_ldq_retry_e_T_1]; // @[util.scala:106:23] wire _can_fire_load_retry_T = _GEN_92[_ldq_retry_e_T_1] & mem_ldq_retry_e_out_bits_addr_valid; // @[util.scala:106:23] wire _can_fire_load_retry_T_1 = _can_fire_load_retry_T & mem_ldq_retry_e_out_bits_addr_is_virtual; // @[util.scala:106:23] wire [2:0] _can_fire_load_retry_T_3 = _can_fire_load_retry_T_2; wire [7:0] _GEN_201 = {{p1_block_load_mask_7}, {p1_block_load_mask_6}, {p1_block_load_mask_5}, {p1_block_load_mask_4}, {p1_block_load_mask_3}, {p1_block_load_mask_2}, {p1_block_load_mask_1}, {p1_block_load_mask_0}}; // @[lsu.scala:397:35, :467:33] wire _can_fire_load_retry_T_4 = ~_GEN_201[_can_fire_load_retry_T_3]; // @[lsu.scala:467:33] wire _can_fire_load_retry_T_5 = _can_fire_load_retry_T_1 & _can_fire_load_retry_T_4; // @[lsu.scala:465:79, :466:79, :467:33] wire [2:0] _can_fire_load_retry_T_7 = _can_fire_load_retry_T_6; wire [7:0] _GEN_202 = {{p2_block_load_mask_7}, {p2_block_load_mask_6}, {p2_block_load_mask_5}, {p2_block_load_mask_4}, {p2_block_load_mask_3}, {p2_block_load_mask_2}, {p2_block_load_mask_1}, {p2_block_load_mask_0}}; // @[lsu.scala:398:35, :468:33] wire _can_fire_load_retry_T_8 = ~_GEN_202[_can_fire_load_retry_T_7]; // @[lsu.scala:468:33] wire _can_fire_load_retry_T_9 = _can_fire_load_retry_T_5 & _can_fire_load_retry_T_8; // @[lsu.scala:466:79, :467:79, :468:33] reg can_fire_load_retry_REG; // @[lsu.scala:469:40] wire _can_fire_load_retry_T_10 = _can_fire_load_retry_T_9 & can_fire_load_retry_REG; // @[lsu.scala:467:79, :468:79, :469:40] wire _can_fire_load_retry_T_11 = ~store_needs_order; // @[lsu.scala:406:35, :470:33] wire _can_fire_load_retry_T_12 = _can_fire_load_retry_T_10 & _can_fire_load_retry_T_11; // @[lsu.scala:468:79, :469:79, :470:33] wire _can_fire_load_retry_T_13 = _can_fire_load_retry_T_12; // @[lsu.scala:469:79, :470:79] wire _can_fire_load_retry_T_14 = ~mem_ldq_retry_e_out_bits_order_fail; // @[util.scala:106:23] wire _can_fire_load_retry_T_15 = _can_fire_load_retry_T_13 & _can_fire_load_retry_T_14; // @[lsu.scala:470:79, :471:79, :472:33] wire can_fire_load_retry_0 = _can_fire_load_retry_T_15; // @[lsu.scala:263:49, :471:79] wire [6:0] mem_stq_retry_e_out_bits_uop_uopc = _GEN_1[_stq_retry_e_T_1]; // @[util.scala:106:23] wire [31:0] mem_stq_retry_e_out_bits_uop_inst = _GEN_2[_stq_retry_e_T_1]; // @[util.scala:106:23] wire [31:0] mem_stq_retry_e_out_bits_uop_debug_inst = _GEN_3[_stq_retry_e_T_1]; // @[util.scala:106:23] wire mem_stq_retry_e_out_bits_uop_is_rvc = _GEN_4[_stq_retry_e_T_1]; // @[util.scala:106:23] wire [39:0] mem_stq_retry_e_out_bits_uop_debug_pc = _GEN_5[_stq_retry_e_T_1]; // @[util.scala:106:23] wire [2:0] mem_stq_retry_e_out_bits_uop_iq_type = _GEN_6[_stq_retry_e_T_1]; // @[util.scala:106:23] wire [9:0] mem_stq_retry_e_out_bits_uop_fu_code = _GEN_7[_stq_retry_e_T_1]; // @[util.scala:106:23] wire [3:0] mem_stq_retry_e_out_bits_uop_ctrl_br_type = _GEN_8[_stq_retry_e_T_1]; // @[util.scala:106:23] wire [1:0] mem_stq_retry_e_out_bits_uop_ctrl_op1_sel = _GEN_9[_stq_retry_e_T_1]; // @[util.scala:106:23] wire [2:0] mem_stq_retry_e_out_bits_uop_ctrl_op2_sel = _GEN_10[_stq_retry_e_T_1]; // @[util.scala:106:23] wire [2:0] mem_stq_retry_e_out_bits_uop_ctrl_imm_sel = _GEN_11[_stq_retry_e_T_1]; // @[util.scala:106:23] wire [4:0] mem_stq_retry_e_out_bits_uop_ctrl_op_fcn = _GEN_12[_stq_retry_e_T_1]; // @[util.scala:106:23] wire mem_stq_retry_e_out_bits_uop_ctrl_fcn_dw = _GEN_13[_stq_retry_e_T_1]; // @[util.scala:106:23] wire [2:0] mem_stq_retry_e_out_bits_uop_ctrl_csr_cmd = _GEN_14[_stq_retry_e_T_1]; // @[util.scala:106:23] wire mem_stq_retry_e_out_bits_uop_ctrl_is_load = _GEN_15[_stq_retry_e_T_1]; // @[util.scala:106:23] wire mem_stq_retry_e_out_bits_uop_ctrl_is_sta = _GEN_16[_stq_retry_e_T_1]; // @[util.scala:106:23] wire mem_stq_retry_e_out_bits_uop_ctrl_is_std = _GEN_17[_stq_retry_e_T_1]; // @[util.scala:106:23] wire [1:0] mem_stq_retry_e_out_bits_uop_iw_state = _GEN_18[_stq_retry_e_T_1]; // @[util.scala:106:23] wire mem_stq_retry_e_out_bits_uop_iw_p1_poisoned = _GEN_19[_stq_retry_e_T_1]; // @[util.scala:106:23] wire mem_stq_retry_e_out_bits_uop_iw_p2_poisoned = _GEN_20[_stq_retry_e_T_1]; // @[util.scala:106:23] wire mem_stq_retry_e_out_bits_uop_is_br = _GEN_21[_stq_retry_e_T_1]; // @[util.scala:106:23] wire mem_stq_retry_e_out_bits_uop_is_jalr = _GEN_22[_stq_retry_e_T_1]; // @[util.scala:106:23] wire mem_stq_retry_e_out_bits_uop_is_jal = _GEN_23[_stq_retry_e_T_1]; // @[util.scala:106:23] wire mem_stq_retry_e_out_bits_uop_is_sfb = _GEN_24[_stq_retry_e_T_1]; // @[util.scala:106:23] wire [2:0] mem_stq_retry_e_out_bits_uop_br_tag = _GEN_26[_stq_retry_e_T_1]; // @[util.scala:106:23] wire [3:0] mem_stq_retry_e_out_bits_uop_ftq_idx = _GEN_27[_stq_retry_e_T_1]; // @[util.scala:106:23] wire mem_stq_retry_e_out_bits_uop_edge_inst = _GEN_28[_stq_retry_e_T_1]; // @[util.scala:106:23] wire [5:0] mem_stq_retry_e_out_bits_uop_pc_lob = _GEN_29[_stq_retry_e_T_1]; // @[util.scala:106:23] wire mem_stq_retry_e_out_bits_uop_taken = _GEN_30[_stq_retry_e_T_1]; // @[util.scala:106:23] wire [19:0] mem_stq_retry_e_out_bits_uop_imm_packed = _GEN_31[_stq_retry_e_T_1]; // @[util.scala:106:23] wire [11:0] mem_stq_retry_e_out_bits_uop_csr_addr = _GEN_32[_stq_retry_e_T_1]; // @[util.scala:106:23] wire [4:0] mem_stq_retry_e_out_bits_uop_rob_idx = _GEN_33[_stq_retry_e_T_1]; // @[util.scala:106:23] wire [2:0] mem_stq_retry_e_out_bits_uop_ldq_idx = _GEN_34[_stq_retry_e_T_1]; // @[util.scala:106:23] wire [2:0] mem_stq_retry_e_out_bits_uop_stq_idx = _GEN_35[_stq_retry_e_T_1]; // @[util.scala:106:23] wire [1:0] mem_stq_retry_e_out_bits_uop_rxq_idx = _GEN_36[_stq_retry_e_T_1]; // @[util.scala:106:23] wire [5:0] mem_stq_retry_e_out_bits_uop_pdst = _GEN_37[_stq_retry_e_T_1]; // @[util.scala:106:23] wire [5:0] mem_stq_retry_e_out_bits_uop_prs1 = _GEN_38[_stq_retry_e_T_1]; // @[util.scala:106:23] wire [5:0] mem_stq_retry_e_out_bits_uop_prs2 = _GEN_39[_stq_retry_e_T_1]; // @[util.scala:106:23] wire [5:0] mem_stq_retry_e_out_bits_uop_prs3 = _GEN_40[_stq_retry_e_T_1]; // @[util.scala:106:23] wire [3:0] mem_stq_retry_e_out_bits_uop_ppred = _GEN_41[_stq_retry_e_T_1]; // @[util.scala:106:23] wire mem_stq_retry_e_out_bits_uop_prs1_busy = _GEN_42[_stq_retry_e_T_1]; // @[util.scala:106:23] wire mem_stq_retry_e_out_bits_uop_prs2_busy = _GEN_43[_stq_retry_e_T_1]; // @[util.scala:106:23] wire mem_stq_retry_e_out_bits_uop_prs3_busy = _GEN_44[_stq_retry_e_T_1]; // @[util.scala:106:23] wire mem_stq_retry_e_out_bits_uop_ppred_busy = _GEN_45[_stq_retry_e_T_1]; // @[util.scala:106:23] wire [5:0] mem_stq_retry_e_out_bits_uop_stale_pdst = _GEN_46[_stq_retry_e_T_1]; // @[util.scala:106:23] wire mem_stq_retry_e_out_bits_uop_exception = _GEN_47[_stq_retry_e_T_1]; // @[util.scala:106:23] wire [63:0] mem_stq_retry_e_out_bits_uop_exc_cause = _GEN_49[_stq_retry_e_T_1]; // @[util.scala:106:23] wire mem_stq_retry_e_out_bits_uop_bypassable = _GEN_50[_stq_retry_e_T_1]; // @[util.scala:106:23] wire [4:0] mem_stq_retry_e_out_bits_uop_mem_cmd = _GEN_51[_stq_retry_e_T_1]; // @[util.scala:106:23] wire [1:0] mem_stq_retry_e_out_bits_uop_mem_size = _GEN_52[_stq_retry_e_T_1]; // @[util.scala:106:23] wire mem_stq_retry_e_out_bits_uop_mem_signed = _GEN_53[_stq_retry_e_T_1]; // @[util.scala:106:23] wire mem_stq_retry_e_out_bits_uop_is_fence = _GEN_54[_stq_retry_e_T_1]; // @[util.scala:106:23] wire mem_stq_retry_e_out_bits_uop_is_fencei = _GEN_56[_stq_retry_e_T_1]; // @[util.scala:106:23] wire mem_stq_retry_e_out_bits_uop_is_amo = _GEN_57[_stq_retry_e_T_1]; // @[util.scala:106:23] wire mem_stq_retry_e_out_bits_uop_uses_ldq = _GEN_59[_stq_retry_e_T_1]; // @[util.scala:106:23] wire mem_stq_retry_e_out_bits_uop_uses_stq = _GEN_60[_stq_retry_e_T_1]; // @[util.scala:106:23] wire mem_stq_retry_e_out_bits_uop_is_sys_pc2epc = _GEN_61[_stq_retry_e_T_1]; // @[util.scala:106:23] wire mem_stq_retry_e_out_bits_uop_is_unique = _GEN_62[_stq_retry_e_T_1]; // @[util.scala:106:23] wire mem_stq_retry_e_out_bits_uop_flush_on_commit = _GEN_63[_stq_retry_e_T_1]; // @[util.scala:106:23] wire mem_stq_retry_e_out_bits_uop_ldst_is_rs1 = _GEN_64[_stq_retry_e_T_1]; // @[util.scala:106:23] wire [5:0] mem_stq_retry_e_out_bits_uop_ldst = _GEN_65[_stq_retry_e_T_1]; // @[util.scala:106:23] wire [5:0] mem_stq_retry_e_out_bits_uop_lrs1 = _GEN_66[_stq_retry_e_T_1]; // @[util.scala:106:23] wire [5:0] mem_stq_retry_e_out_bits_uop_lrs2 = _GEN_67[_stq_retry_e_T_1]; // @[util.scala:106:23] wire [5:0] mem_stq_retry_e_out_bits_uop_lrs3 = _GEN_68[_stq_retry_e_T_1]; // @[util.scala:106:23] wire mem_stq_retry_e_out_bits_uop_ldst_val = _GEN_69[_stq_retry_e_T_1]; // @[util.scala:106:23] wire [1:0] mem_stq_retry_e_out_bits_uop_dst_rtype = _GEN_70[_stq_retry_e_T_1]; // @[util.scala:106:23] wire [1:0] mem_stq_retry_e_out_bits_uop_lrs1_rtype = _GEN_71[_stq_retry_e_T_1]; // @[util.scala:106:23] wire [1:0] mem_stq_retry_e_out_bits_uop_lrs2_rtype = _GEN_72[_stq_retry_e_T_1]; // @[util.scala:106:23] wire mem_stq_retry_e_out_bits_uop_frs3_en = _GEN_73[_stq_retry_e_T_1]; // @[util.scala:106:23] wire mem_stq_retry_e_out_bits_uop_fp_val = _GEN_74[_stq_retry_e_T_1]; // @[util.scala:106:23] wire mem_stq_retry_e_out_bits_uop_fp_single = _GEN_75[_stq_retry_e_T_1]; // @[util.scala:106:23] wire mem_stq_retry_e_out_bits_uop_xcpt_pf_if = _GEN_76[_stq_retry_e_T_1]; // @[util.scala:106:23] wire mem_stq_retry_e_out_bits_uop_xcpt_ae_if = _GEN_77[_stq_retry_e_T_1]; // @[util.scala:106:23] wire mem_stq_retry_e_out_bits_uop_xcpt_ma_if = _GEN_78[_stq_retry_e_T_1]; // @[util.scala:106:23] wire mem_stq_retry_e_out_bits_uop_bp_debug_if = _GEN_79[_stq_retry_e_T_1]; // @[util.scala:106:23] wire mem_stq_retry_e_out_bits_uop_bp_xcpt_if = _GEN_80[_stq_retry_e_T_1]; // @[util.scala:106:23] wire [1:0] mem_stq_retry_e_out_bits_uop_debug_fsrc = _GEN_81[_stq_retry_e_T_1]; // @[util.scala:106:23] wire [1:0] mem_stq_retry_e_out_bits_uop_debug_tsrc = _GEN_82[_stq_retry_e_T_1]; // @[util.scala:106:23] wire mem_stq_retry_e_out_bits_addr_valid = _GEN_83[_stq_retry_e_T_1]; // @[util.scala:106:23] wire [39:0] mem_stq_retry_e_out_bits_addr_bits = _GEN_84[_stq_retry_e_T_1]; // @[util.scala:106:23] wire mem_stq_retry_e_out_bits_addr_is_virtual = _GEN_85[_stq_retry_e_T_1]; // @[util.scala:106:23] wire mem_stq_retry_e_out_bits_data_valid = _GEN_86[_stq_retry_e_T_1]; // @[util.scala:106:23] wire [63:0] mem_stq_retry_e_out_bits_data_bits = _GEN_87[_stq_retry_e_T_1]; // @[util.scala:106:23] wire mem_stq_retry_e_out_bits_committed = _GEN_89[_stq_retry_e_T_1]; // @[util.scala:106:23] wire mem_stq_retry_e_out_bits_succeeded = _GEN_184[_stq_retry_e_T_1]; // @[util.scala:106:23] wire [63:0] mem_stq_retry_e_out_bits_debug_wb_data = _GEN_185[_stq_retry_e_T_1]; // @[util.scala:106:23] wire _can_fire_sta_retry_T = _GEN[_stq_retry_e_T_1] & mem_stq_retry_e_out_bits_addr_valid; // @[util.scala:106:23] wire _can_fire_sta_retry_T_1 = _can_fire_sta_retry_T & mem_stq_retry_e_out_bits_addr_is_virtual; // @[util.scala:106:23] wire _can_fire_sta_retry_T_2 = _can_fire_sta_retry_T_1; // @[lsu.scala:478:79, :479:79] reg can_fire_sta_retry_REG; // @[lsu.scala:481:41] wire _can_fire_sta_retry_T_3 = _can_fire_sta_retry_T_2 & can_fire_sta_retry_REG; // @[lsu.scala:479:79, :480:79, :481:41] wire _can_fire_sta_retry_T_8 = _can_fire_sta_retry_T_3; // @[lsu.scala:480:79, :481:79] wire _can_fire_sta_retry_T_5 = stq_incoming_idx_0 == stq_retry_idx; // @[lsu.scala:263:49, :421:30, :484:70] wire can_fire_sta_retry_0 = _can_fire_sta_retry_T_8; // @[lsu.scala:263:49, :481:79] wire _can_fire_store_commit_T = ~_GEN_55; // @[lsu.scala:222:42, :489:33] wire _can_fire_store_commit_T_1 = _GEN_0 & _can_fire_store_commit_T; // @[lsu.scala:222:42, :488:79, :489:33] wire _can_fire_store_commit_T_2 = ~mem_xcpt_valid; // @[lsu.scala:358:29, :490:33] wire _can_fire_store_commit_T_3 = _can_fire_store_commit_T_1 & _can_fire_store_commit_T_2; // @[lsu.scala:488:79, :489:79, :490:33] wire _can_fire_store_commit_T_4 = ~_GEN_48; // @[lsu.scala:222:42, :491:33] wire _can_fire_store_commit_T_5 = _can_fire_store_commit_T_3 & _can_fire_store_commit_T_4; // @[lsu.scala:489:79, :490:79, :491:33] wire _can_fire_store_commit_T_6 = _can_fire_store_commit_T_5; // @[lsu.scala:490:79, :491:79] wire _can_fire_store_commit_T_7 = _GEN_58 & _GEN_83[stq_execute_head]; // @[lsu.scala:218:29, :222:42, :493:101] wire _can_fire_store_commit_T_8 = ~_GEN_85[stq_execute_head]; // @[lsu.scala:218:29, :222:42, :495:66] wire _can_fire_store_commit_T_9 = _can_fire_store_commit_T_7 & _can_fire_store_commit_T_8; // @[lsu.scala:493:101, :494:101, :495:66] wire _can_fire_store_commit_T_10 = _can_fire_store_commit_T_9 & _GEN_86[stq_execute_head]; // @[lsu.scala:218:29, :222:42, :494:101, :495:101] wire _can_fire_store_commit_T_11 = _GEN_89[stq_execute_head] \| _can_fire_store_commit_T_10; // @[lsu.scala:218:29, :222:42, :493:62, :495:101] wire _can_fire_store_commit_T_12 = _can_fire_store_commit_T_6 & _can_fire_store_commit_T_11; // @[lsu.scala:491:79, :492:79, :493:62] wire can_fire_store_commit_0 = _can_fire_store_commit_T_12; // @[lsu.scala:263:49, :492:79] wire _will_fire_store_commit_0_will_fire_T_3 = can_fire_store_commit_0; // @[lsu.scala:263:49, :533:32] wire block_load_wakeup; // @[lsu.scala:499:35] wire [6:0] mem_ldq_wakeup_e_out_bits_uop_uopc = _GEN_94[_ldq_wakeup_e_T_1]; // @[util.scala:106:23] wire [31:0] mem_ldq_wakeup_e_out_bits_uop_inst = _GEN_95[_ldq_wakeup_e_T_1]; // @[util.scala:106:23] wire [31:0] mem_ldq_wakeup_e_out_bits_uop_debug_inst = _GEN_96[_ldq_wakeup_e_T_1]; // @[util.scala:106:23] wire mem_ldq_wakeup_e_out_bits_uop_is_rvc = _GEN_97[_ldq_wakeup_e_T_1]; // @[util.scala:106:23] wire [39:0] mem_ldq_wakeup_e_out_bits_uop_debug_pc = _GEN_98[_ldq_wakeup_e_T_1]; // @[util.scala:106:23] wire [2:0] mem_ldq_wakeup_e_out_bits_uop_iq_type = _GEN_99[_ldq_wakeup_e_T_1]; // @[util.scala:106:23] wire [9:0] mem_ldq_wakeup_e_out_bits_uop_fu_code = _GEN_100[_ldq_wakeup_e_T_1]; // @[util.scala:106:23] wire [3:0] mem_ldq_wakeup_e_out_bits_uop_ctrl_br_type = _GEN_101[_ldq_wakeup_e_T_1]; // @[util.scala:106:23] wire [1:0] mem_ldq_wakeup_e_out_bits_uop_ctrl_op1_sel = _GEN_102[_ldq_wakeup_e_T_1]; // @[util.scala:106:23] wire [2:0] mem_ldq_wakeup_e_out_bits_uop_ctrl_op2_sel = _GEN_103[_ldq_wakeup_e_T_1]; // @[util.scala:106:23] wire [2:0] mem_ldq_wakeup_e_out_bits_uop_ctrl_imm_sel = _GEN_104[_ldq_wakeup_e_T_1]; // @[util.scala:106:23] wire [4:0] mem_ldq_wakeup_e_out_bits_uop_ctrl_op_fcn = _GEN_105[_ldq_wakeup_e_T_1]; // @[util.scala:106:23] wire mem_ldq_wakeup_e_out_bits_uop_ctrl_fcn_dw = _GEN_106[_ldq_wakeup_e_T_1]; // @[util.scala:106:23] wire [2:0] mem_ldq_wakeup_e_out_bits_uop_ctrl_csr_cmd = _GEN_107[_ldq_wakeup_e_T_1]; // @[util.scala:106:23] wire mem_ldq_wakeup_e_out_bits_uop_ctrl_is_load = _GEN_108[_ldq_wakeup_e_T_1]; // @[util.scala:106:23] wire mem_ldq_wakeup_e_out_bits_uop_ctrl_is_sta = _GEN_109[_ldq_wakeup_e_T_1]; // @[util.scala:106:23] wire mem_ldq_wakeup_e_out_bits_uop_ctrl_is_std = _GEN_110[_ldq_wakeup_e_T_1]; // @[util.scala:106:23] wire [1:0] mem_ldq_wakeup_e_out_bits_uop_iw_state = _GEN_111[_ldq_wakeup_e_T_1]; // @[util.scala:106:23] wire mem_ldq_wakeup_e_out_bits_uop_iw_p1_poisoned = _GEN_112[_ldq_wakeup_e_T_1]; // @[util.scala:106:23] wire mem_ldq_wakeup_e_out_bits_uop_iw_p2_poisoned = _GEN_113[_ldq_wakeup_e_T_1]; // @[util.scala:106:23] wire mem_ldq_wakeup_e_out_bits_uop_is_br = _GEN_114[_ldq_wakeup_e_T_1]; // @[util.scala:106:23] wire mem_ldq_wakeup_e_out_bits_uop_is_jalr = _GEN_115[_ldq_wakeup_e_T_1]; // @[util.scala:106:23] wire mem_ldq_wakeup_e_out_bits_uop_is_jal = _GEN_116[_ldq_wakeup_e_T_1]; // @[util.scala:106:23] wire mem_ldq_wakeup_e_out_bits_uop_is_sfb = _GEN_117[_ldq_wakeup_e_T_1]; // @[util.scala:106:23] wire [2:0] mem_ldq_wakeup_e_out_bits_uop_br_tag = _GEN_119[_ldq_wakeup_e_T_1]; // @[util.scala:106:23] wire [3:0] mem_ldq_wakeup_e_out_bits_uop_ftq_idx = _GEN_120[_ldq_wakeup_e_T_1]; // @[util.scala:106:23] wire mem_ldq_wakeup_e_out_bits_uop_edge_inst = _GEN_121[_ldq_wakeup_e_T_1]; // @[util.scala:106:23] wire [5:0] mem_ldq_wakeup_e_out_bits_uop_pc_lob = _GEN_122[_ldq_wakeup_e_T_1]; // @[util.scala:106:23] wire mem_ldq_wakeup_e_out_bits_uop_taken = _GEN_123[_ldq_wakeup_e_T_1]; // @[util.scala:106:23] wire [19:0] mem_ldq_wakeup_e_out_bits_uop_imm_packed = _GEN_124[_ldq_wakeup_e_T_1]; // @[util.scala:106:23] wire [11:0] mem_ldq_wakeup_e_out_bits_uop_csr_addr = _GEN_125[_ldq_wakeup_e_T_1]; // @[util.scala:106:23] wire [4:0] mem_ldq_wakeup_e_out_bits_uop_rob_idx = _GEN_126[_ldq_wakeup_e_T_1]; // @[util.scala:106:23] wire [2:0] mem_ldq_wakeup_e_out_bits_uop_ldq_idx = _GEN_127[_ldq_wakeup_e_T_1]; // @[util.scala:106:23] wire [2:0] mem_ldq_wakeup_e_out_bits_uop_stq_idx = _GEN_128[_ldq_wakeup_e_T_1]; // @[util.scala:106:23] wire [1:0] mem_ldq_wakeup_e_out_bits_uop_rxq_idx = _GEN_129[_ldq_wakeup_e_T_1]; // @[util.scala:106:23] wire [5:0] mem_ldq_wakeup_e_out_bits_uop_pdst = _GEN_130[_ldq_wakeup_e_T_1]; // @[util.scala:106:23] wire [5:0] mem_ldq_wakeup_e_out_bits_uop_prs1 = _GEN_131[_ldq_wakeup_e_T_1]; // @[util.scala:106:23] wire [5:0] mem_ldq_wakeup_e_out_bits_uop_prs2 = _GEN_132[_ldq_wakeup_e_T_1]; // @[util.scala:106:23] wire [5:0] mem_ldq_wakeup_e_out_bits_uop_prs3 = _GEN_133[_ldq_wakeup_e_T_1]; // @[util.scala:106:23] wire mem_ldq_wakeup_e_out_bits_uop_prs1_busy = _GEN_134[_ldq_wakeup_e_T_1]; // @[util.scala:106:23] wire mem_ldq_wakeup_e_out_bits_uop_prs2_busy = _GEN_135[_ldq_wakeup_e_T_1]; // @[util.scala:106:23] wire mem_ldq_wakeup_e_out_bits_uop_prs3_busy = _GEN_136[_ldq_wakeup_e_T_1]; // @[util.scala:106:23] wire [5:0] mem_ldq_wakeup_e_out_bits_uop_stale_pdst = _GEN_137[_ldq_wakeup_e_T_1]; // @[util.scala:106:23] wire mem_ldq_wakeup_e_out_bits_uop_exception = _GEN_138[_ldq_wakeup_e_T_1]; // @[util.scala:106:23] wire [63:0] mem_ldq_wakeup_e_out_bits_uop_exc_cause = _GEN_139[_ldq_wakeup_e_T_1]; // @[util.scala:106:23] wire mem_ldq_wakeup_e_out_bits_uop_bypassable = _GEN_140[_ldq_wakeup_e_T_1]; // @[util.scala:106:23] wire [4:0] mem_ldq_wakeup_e_out_bits_uop_mem_cmd = _GEN_141[_ldq_wakeup_e_T_1]; // @[util.scala:106:23] wire [1:0] mem_ldq_wakeup_e_out_bits_uop_mem_size = _GEN_142[_ldq_wakeup_e_T_1]; // @[util.scala:106:23] wire mem_ldq_wakeup_e_out_bits_uop_mem_signed = _GEN_143[_ldq_wakeup_e_T_1]; // @[util.scala:106:23] wire mem_ldq_wakeup_e_out_bits_uop_is_fence = _GEN_144[_ldq_wakeup_e_T_1]; // @[util.scala:106:23] wire mem_ldq_wakeup_e_out_bits_uop_is_fencei = _GEN_145[_ldq_wakeup_e_T_1]; // @[util.scala:106:23] wire mem_ldq_wakeup_e_out_bits_uop_is_amo = _GEN_146[_ldq_wakeup_e_T_1]; // @[util.scala:106:23] wire mem_ldq_wakeup_e_out_bits_uop_uses_ldq = _GEN_147[_ldq_wakeup_e_T_1]; // @[util.scala:106:23] wire mem_ldq_wakeup_e_out_bits_uop_uses_stq = _GEN_148[_ldq_wakeup_e_T_1]; // @[util.scala:106:23] wire mem_ldq_wakeup_e_out_bits_uop_is_sys_pc2epc = _GEN_149[_ldq_wakeup_e_T_1]; // @[util.scala:106:23] wire mem_ldq_wakeup_e_out_bits_uop_is_unique = _GEN_150[_ldq_wakeup_e_T_1]; // @[util.scala:106:23] wire mem_ldq_wakeup_e_out_bits_uop_flush_on_commit = _GEN_151[_ldq_wakeup_e_T_1]; // @[util.scala:106:23] wire mem_ldq_wakeup_e_out_bits_uop_ldst_is_rs1 = _GEN_152[_ldq_wakeup_e_T_1]; // @[util.scala:106:23] wire [5:0] mem_ldq_wakeup_e_out_bits_uop_ldst = _GEN_153[_ldq_wakeup_e_T_1]; // @[util.scala:106:23] wire [5:0] mem_ldq_wakeup_e_out_bits_uop_lrs1 = _GEN_154[_ldq_wakeup_e_T_1]; // @[util.scala:106:23] wire [5:0] mem_ldq_wakeup_e_out_bits_uop_lrs2 = _GEN_155[_ldq_wakeup_e_T_1]; // @[util.scala:106:23] wire [5:0] mem_ldq_wakeup_e_out_bits_uop_lrs3 = _GEN_156[_ldq_wakeup_e_T_1]; // @[util.scala:106:23] wire mem_ldq_wakeup_e_out_bits_uop_ldst_val = _GEN_157[_ldq_wakeup_e_T_1]; // @[util.scala:106:23] wire [1:0] mem_ldq_wakeup_e_out_bits_uop_dst_rtype = _GEN_158[_ldq_wakeup_e_T_1]; // @[util.scala:106:23] wire [1:0] mem_ldq_wakeup_e_out_bits_uop_lrs1_rtype = _GEN_159[_ldq_wakeup_e_T_1]; // @[util.scala:106:23] wire [1:0] mem_ldq_wakeup_e_out_bits_uop_lrs2_rtype = _GEN_160[_ldq_wakeup_e_T_1]; // @[util.scala:106:23] wire mem_ldq_wakeup_e_out_bits_uop_frs3_en = _GEN_161[_ldq_wakeup_e_T_1]; // @[util.scala:106:23] wire mem_ldq_wakeup_e_out_bits_uop_fp_val = _GEN_162[_ldq_wakeup_e_T_1]; // @[util.scala:106:23] wire mem_ldq_wakeup_e_out_bits_uop_fp_single = _GEN_163[_ldq_wakeup_e_T_1]; // @[util.scala:106:23] wire mem_ldq_wakeup_e_out_bits_uop_xcpt_pf_if = _GEN_164[_ldq_wakeup_e_T_1]; // @[util.scala:106:23] wire mem_ldq_wakeup_e_out_bits_uop_xcpt_ae_if = _GEN_165[_ldq_wakeup_e_T_1]; // @[util.scala:106:23] wire mem_ldq_wakeup_e_out_bits_uop_xcpt_ma_if = _GEN_166[_ldq_wakeup_e_T_1]; // @[util.scala:106:23] wire mem_ldq_wakeup_e_out_bits_uop_bp_debug_if = _GEN_167[_ldq_wakeup_e_T_1]; // @[util.scala:106:23] wire mem_ldq_wakeup_e_out_bits_uop_bp_xcpt_if = _GEN_168[_ldq_wakeup_e_T_1]; // @[util.scala:106:23] wire [1:0] mem_ldq_wakeup_e_out_bits_uop_debug_fsrc = _GEN_169[_ldq_wakeup_e_T_1]; // @[util.scala:106:23] wire [1:0] mem_ldq_wakeup_e_out_bits_uop_debug_tsrc = _GEN_170[_ldq_wakeup_e_T_1]; // @[util.scala:106:23] wire mem_ldq_wakeup_e_out_bits_addr_valid = _GEN_171[_ldq_wakeup_e_T_1]; // @[util.scala:106:23] wire [39:0] mem_ldq_wakeup_e_out_bits_addr_bits = _GEN_172[_ldq_wakeup_e_T_1]; // @[util.scala:106:23] wire mem_ldq_wakeup_e_out_bits_addr_is_virtual = _GEN_173[_ldq_wakeup_e_T_1]; // @[util.scala:106:23] wire mem_ldq_wakeup_e_out_bits_addr_is_uncacheable = _GEN_174[_ldq_wakeup_e_T_1]; // @[util.scala:106:23] wire mem_ldq_wakeup_e_out_bits_executed = _GEN_175[_ldq_wakeup_e_T_1]; // @[util.scala:106:23] wire mem_ldq_wakeup_e_out_bits_succeeded = _GEN_176[_ldq_wakeup_e_T_1]; // @[util.scala:106:23] wire mem_ldq_wakeup_e_out_bits_order_fail = _GEN_177[_ldq_wakeup_e_T_1]; // @[util.scala:106:23] wire mem_ldq_wakeup_e_out_bits_observed = _GEN_178[_ldq_wakeup_e_T_1]; // @[util.scala:106:23] wire [7:0] mem_ldq_wakeup_e_out_bits_st_dep_mask = _GEN_179[_ldq_wakeup_e_T_1]; // @[util.scala:106:23] wire [2:0] mem_ldq_wakeup_e_out_bits_youngest_stq_idx = _GEN_180[_ldq_wakeup_e_T_1]; // @[util.scala:106:23] wire mem_ldq_wakeup_e_out_bits_forward_std_val = _GEN_181[_ldq_wakeup_e_T_1]; // @[util.scala:106:23] wire [2:0] mem_ldq_wakeup_e_out_bits_forward_stq_idx = _GEN_182[_ldq_wakeup_e_T_1]; // @[util.scala:106:23] wire [63:0] mem_ldq_wakeup_e_out_bits_debug_wb_data = _GEN_183[_ldq_wakeup_e_T_1]; // @[util.scala:106:23] wire _can_fire_load_wakeup_T = _GEN_92[_ldq_wakeup_e_T_1] & mem_ldq_wakeup_e_out_bits_addr_valid; // @[util.scala:106:23] wire _can_fire_load_wakeup_T_1 = ~mem_ldq_wakeup_e_out_bits_succeeded; // @[util.scala:106:23] wire _can_fire_load_wakeup_T_2 = _can_fire_load_wakeup_T & _can_fire_load_wakeup_T_1; // @[lsu.scala:501:88, :502:88, :503:31] wire _can_fire_load_wakeup_T_3 = ~mem_ldq_wakeup_e_out_bits_addr_is_virtual; // @[util.scala:106:23] wire _can_fire_load_wakeup_T_4 = _can_fire_load_wakeup_T_2 & _can_fire_load_wakeup_T_3; // @[lsu.scala:502:88, :503:88, :504:31] wire _can_fire_load_wakeup_T_5 = ~mem_ldq_wakeup_e_out_bits_executed; // @[util.scala:106:23] wire _can_fire_load_wakeup_T_6 = _can_fire_load_wakeup_T_4 & _can_fire_load_wakeup_T_5; // @[lsu.scala:503:88, :504:88, :505:31] wire _can_fire_load_wakeup_T_7 = ~mem_ldq_wakeup_e_out_bits_order_fail; // @[util.scala:106:23] wire _can_fire_load_wakeup_T_8 = _can_fire_load_wakeup_T_6 & _can_fire_load_wakeup_T_7; // @[lsu.scala:504:88, :505:88, :506:31] wire [2:0] _can_fire_load_wakeup_T_10 = _can_fire_load_wakeup_T_9; wire _can_fire_load_wakeup_T_11 = ~_GEN_201[_can_fire_load_wakeup_T_10]; // @[lsu.scala:467:33, :507:31] wire _can_fire_load_wakeup_T_12 = _can_fire_load_wakeup_T_8 & _can_fire_load_wakeup_T_11; // @[lsu.scala:505:88, :506:88, :507:31] wire [2:0] _can_fire_load_wakeup_T_14 = _can_fire_load_wakeup_T_13; wire _can_fire_load_wakeup_T_15 = ~_GEN_202[_can_fire_load_wakeup_T_14]; // @[lsu.scala:468:33, :508:31] wire _can_fire_load_wakeup_T_16 = _can_fire_load_wakeup_T_12 & _can_fire_load_wakeup_T_15; // @[lsu.scala:506:88, :507:88, :508:31] wire _can_fire_load_wakeup_T_17 = ~store_needs_order; // @[lsu.scala:406:35, :470:33, :509:31] wire _can_fire_load_wakeup_T_18 = _can_fire_load_wakeup_T_16 & _can_fire_load_wakeup_T_17; // @[lsu.scala:507:88, :508:88, :509:31] wire _can_fire_load_wakeup_T_19 = ~block_load_wakeup; // @[lsu.scala:499:35, :510:31] wire _can_fire_load_wakeup_T_20 = _can_fire_load_wakeup_T_18 & _can_fire_load_wakeup_T_19; // @[lsu.scala:508:88, :509:88, :510:31] wire _can_fire_load_wakeup_T_21 = _can_fire_load_wakeup_T_20; // @[lsu.scala:509:88, :510:88] wire _can_fire_load_wakeup_T_22 = ~mem_ldq_wakeup_e_out_bits_addr_is_uncacheable; // @[util.scala:106:23] wire _can_fire_load_wakeup_T_23 = ldq_head == ldq_wakeup_idx; // @[lsu.scala:213:29, :429:31, :513:84] wire _can_fire_load_wakeup_T_24 = io_core_commit_load_at_rob_head_0 & _can_fire_load_wakeup_T_23; // @[lsu.scala:201:7, :512:107, :513:84] wire _can_fire_load_wakeup_T_25 = mem_ldq_wakeup_e_out_bits_st_dep_mask == 8'h0; // @[util.scala:106:23] wire _can_fire_load_wakeup_T_26 = _can_fire_load_wakeup_T_24 & _can_fire_load_wakeup_T_25; // @[lsu.scala:512:107, :513:103, :514:112] wire _can_fire_load_wakeup_T_27 = _can_fire_load_wakeup_T_22 \| _can_fire_load_wakeup_T_26; // @[lsu.scala:512:{32,71}, :513:103] wire _can_fire_load_wakeup_T_28 = _can_fire_load_wakeup_T_21 & _can_fire_load_wakeup_T_27; // @[lsu.scala:510:88, :511:88, :512:71] wire can_fire_load_wakeup_0 = _can_fire_load_wakeup_T_28; // @[lsu.scala:263:49, :511:88] wire _will_fire_load_wakeup_0_will_fire_T_3 = can_fire_load_wakeup_0; // @[lsu.scala:263:49, :533:32] wire can_fire_hella_incoming_0; // @[lsu.scala:517:42] wire can_fire_hella_wakeup_0; // @[lsu.scala:520:42] wire _will_fire_hella_wakeup_0_will_fire_T_3 = can_fire_hella_wakeup_0; // @[lsu.scala:520:42, :533:32] wire _exe_tlb_valid_0_T; // @[lsu.scala:575:25] wire exe_tlb_valid_0; // @[lsu.scala:525:27] wire _will_fire_load_incoming_0_will_fire_T_7 = _will_fire_load_incoming_0_will_fire_T_3; // @[lsu.scala:533:{32,63}] wire _will_fire_load_incoming_0_will_fire_T_11 = _will_fire_load_incoming_0_will_fire_T_7; // @[lsu.scala:533:63, :534:65] assign will_fire_load_incoming_0_will_fire = _will_fire_load_incoming_0_will_fire_T_11; // @[lsu.scala:534:65, :535:61] assign will_fire_load_incoming_0 = will_fire_load_incoming_0_will_fire; // @[lsu.scala:370:38, :535:61] wire _will_fire_load_incoming_0_T = will_fire_load_incoming_0_will_fire; // @[lsu.scala:535:61, :537:46] wire _will_fire_load_incoming_0_T_3 = will_fire_load_incoming_0_will_fire; // @[lsu.scala:535:61, :538:46] wire _will_fire_load_incoming_0_T_6 = will_fire_load_incoming_0_will_fire; // @[lsu.scala:535:61, :539:46] wire _will_fire_load_incoming_0_T_1 = ~_will_fire_load_incoming_0_T; // @[lsu.scala:537:{34,46}] wire _will_fire_load_incoming_0_T_2 = _will_fire_load_incoming_0_T_1; // @[lsu.scala:537:{31,34}] wire _will_fire_load_incoming_0_T_4 = ~_will_fire_load_incoming_0_T_3; // @[lsu.scala:538:{34,46}] wire _will_fire_load_incoming_0_T_5 = _will_fire_load_incoming_0_T_4; // @[lsu.scala:538:{31,34}] wire _will_fire_load_incoming_0_T_7 = ~_will_fire_load_incoming_0_T_6; // @[lsu.scala:539:{34,46}] wire _will_fire_load_incoming_0_T_8 = _will_fire_load_incoming_0_T_7; // @[lsu.scala:539:{31,34}] wire _will_fire_stad_incoming_0_T_8 = _will_fire_load_incoming_0_T_8; // @[lsu.scala:539:31] wire _will_fire_stad_incoming_0_will_fire_T = ~_will_fire_load_incoming_0_T_2; // @[lsu.scala:533:51, :537:31] wire _will_fire_stad_incoming_0_will_fire_T_1 = _will_fire_stad_incoming_0_will_fire_T; // @[lsu.scala:533:{48,51}] wire _will_fire_stad_incoming_0_will_fire_T_2 = ~_will_fire_stad_incoming_0_will_fire_T_1; // @[lsu.scala:533:{35,48}] wire _will_fire_stad_incoming_0_will_fire_T_3 = can_fire_stad_incoming_0 & _will_fire_stad_incoming_0_will_fire_T_2; // @[lsu.scala:263:49, :533:{32,35}] wire _will_fire_stad_incoming_0_will_fire_T_4 = ~_will_fire_load_incoming_0_T_5; // @[lsu.scala:534:52, :538:31] wire _will_fire_stad_incoming_0_will_fire_T_5 = _will_fire_stad_incoming_0_will_fire_T_4; // @[lsu.scala:534:{49,52}] wire _will_fire_stad_incoming_0_will_fire_T_6 = ~_will_fire_stad_incoming_0_will_fire_T_5; // @[lsu.scala:534:{35,49}] wire _will_fire_stad_incoming_0_will_fire_T_7 = _will_fire_stad_incoming_0_will_fire_T_3 & _will_fire_stad_incoming_0_will_fire_T_6; // @[lsu.scala:533:{32,63}, :534:35] wire _will_fire_stad_incoming_0_will_fire_T_11 = _will_fire_stad_incoming_0_will_fire_T_7; // @[lsu.scala:533:63, :534:65] wire _will_fire_stad_incoming_0_will_fire_T_8 = ~_will_fire_load_incoming_0_T_8; // @[lsu.scala:535:50, :539:31] assign will_fire_stad_incoming_0_will_fire = _will_fire_stad_incoming_0_will_fire_T_11; // @[lsu.scala:534:65, :535:61] assign will_fire_stad_incoming_0 = will_fire_stad_incoming_0_will_fire; // @[lsu.scala:371:38, :535:61] wire _will_fire_stad_incoming_0_T = will_fire_stad_incoming_0_will_fire; // @[lsu.scala:535:61, :537:46] wire _will_fire_stad_incoming_0_T_3 = will_fire_stad_incoming_0_will_fire; // @[lsu.scala:535:61, :538:46] wire _will_fire_stad_incoming_0_T_9 = will_fire_stad_incoming_0_will_fire; // @[lsu.scala:535:61, :540:46] wire _will_fire_stad_incoming_0_T_1 = ~_will_fire_stad_incoming_0_T; // @[lsu.scala:537:{34,46}] wire _will_fire_stad_incoming_0_T_2 = _will_fire_load_incoming_0_T_2 & _will_fire_stad_incoming_0_T_1; // @[lsu.scala:537:{31,34}] wire _will_fire_stad_incoming_0_T_4 = ~_will_fire_stad_incoming_0_T_3; // @[lsu.scala:538:{34,46}] wire _will_fire_stad_incoming_0_T_5 = _will_fire_load_incoming_0_T_5 & _will_fire_stad_incoming_0_T_4; // @[lsu.scala:538:{31,34}] wire _will_fire_sta_incoming_0_T_8 = _will_fire_stad_incoming_0_T_8; // @[lsu.scala:539:31] wire _will_fire_stad_incoming_0_T_10 = ~_will_fire_stad_incoming_0_T_9; // @[lsu.scala:540:{34,46}] wire _will_fire_stad_incoming_0_T_11 = _will_fire_stad_incoming_0_T_10; // @[lsu.scala:540:{31,34}] wire _will_fire_sta_incoming_0_will_fire_T = ~_will_fire_stad_incoming_0_T_2; // @[lsu.scala:533:51, :537:31] wire _will_fire_sta_incoming_0_will_fire_T_1 = _will_fire_sta_incoming_0_will_fire_T; // @[lsu.scala:533:{48,51}] wire _will_fire_sta_incoming_0_will_fire_T_2 = ~_will_fire_sta_incoming_0_will_fire_T_1; // @[lsu.scala:533:{35,48}] wire _will_fire_sta_incoming_0_will_fire_T_3 = can_fire_sta_incoming_0 & _will_fire_sta_incoming_0_will_fire_T_2; // @[lsu.scala:263:49, :533:{32,35}] wire _will_fire_sta_incoming_0_will_fire_T_4 = ~_will_fire_stad_incoming_0_T_5; // @[lsu.scala:534:52, :538:31] wire _will_fire_sta_incoming_0_will_fire_T_5 = _will_fire_sta_incoming_0_will_fire_T_4; // @[lsu.scala:534:{49,52}] wire _will_fire_sta_incoming_0_will_fire_T_6 = ~_will_fire_sta_incoming_0_will_fire_T_5; // @[lsu.scala:534:{35,49}] wire _will_fire_sta_incoming_0_will_fire_T_7 = _will_fire_sta_incoming_0_will_fire_T_3 & _will_fire_sta_incoming_0_will_fire_T_6; // @[lsu.scala:533:{32,63}, :534:35] wire _will_fire_sta_incoming_0_will_fire_T_11 = _will_fire_sta_incoming_0_will_fire_T_7; // @[lsu.scala:533:63, :534:65] wire _will_fire_sta_incoming_0_will_fire_T_8 = ~_will_fire_stad_incoming_0_T_8; // @[lsu.scala:535:50, :539:31] wire _will_fire_sta_incoming_0_will_fire_T_12 = ~_will_fire_stad_incoming_0_T_11; // @[lsu.scala:536:51, :540:31] wire _will_fire_sta_incoming_0_will_fire_T_13 = _will_fire_sta_incoming_0_will_fire_T_12; // @[lsu.scala:536:{48,51}] wire _will_fire_sta_incoming_0_will_fire_T_14 = ~_will_fire_sta_incoming_0_will_fire_T_13; // @[lsu.scala:536:{35,48}] assign will_fire_sta_incoming_0_will_fire = _will_fire_sta_incoming_0_will_fire_T_11 & _will_fire_sta_incoming_0_will_fire_T_14; // @[lsu.scala:534:65, :535:61, :536:35] assign will_fire_sta_incoming_0 = will_fire_sta_incoming_0_will_fire; // @[lsu.scala:372:38, :535:61] wire _will_fire_sta_incoming_0_T = will_fire_sta_incoming_0_will_fire; // @[lsu.scala:535:61, :537:46] wire _will_fire_sta_incoming_0_T_3 = will_fire_sta_incoming_0_will_fire; // @[lsu.scala:535:61, :538:46] wire _will_fire_sta_incoming_0_T_9 = will_fire_sta_incoming_0_will_fire; // @[lsu.scala:535:61, :540:46] wire _will_fire_sta_incoming_0_T_1 = ~_will_fire_sta_incoming_0_T; // @[lsu.scala:537:{34,46}] wire _will_fire_sta_incoming_0_T_2 = _will_fire_stad_incoming_0_T_2 & _will_fire_sta_incoming_0_T_1; // @[lsu.scala:537:{31,34}] wire _will_fire_std_incoming_0_T_2 = _will_fire_sta_incoming_0_T_2; // @[lsu.scala:537:31] wire _will_fire_sta_incoming_0_T_4 = ~_will_fire_sta_incoming_0_T_3; // @[lsu.scala:538:{34,46}] wire _will_fire_sta_incoming_0_T_5 = _will_fire_stad_incoming_0_T_5 & _will_fire_sta_incoming_0_T_4; // @[lsu.scala:538:{31,34}] wire _will_fire_std_incoming_0_T_5 = _will_fire_sta_incoming_0_T_5; // @[lsu.scala:538:31] wire _will_fire_std_incoming_0_T_8 = _will_fire_sta_incoming_0_T_8; // @[lsu.scala:539:31] wire _will_fire_sta_incoming_0_T_10 = ~_will_fire_sta_incoming_0_T_9; // @[lsu.scala:540:{34,46}] wire _will_fire_sta_incoming_0_T_11 = _will_fire_stad_incoming_0_T_11 & _will_fire_sta_incoming_0_T_10; // @[lsu.scala:540:{31,34}] wire _will_fire_std_incoming_0_will_fire_T = ~_will_fire_sta_incoming_0_T_2; // @[lsu.scala:533:51, :537:31] wire _will_fire_std_incoming_0_will_fire_T_7 = _will_fire_std_incoming_0_will_fire_T_3; // @[lsu.scala:533:{32,63}] wire _will_fire_std_incoming_0_will_fire_T_4 = ~_will_fire_sta_incoming_0_T_5; // @[lsu.scala:534:52, :538:31] wire _will_fire_std_incoming_0_will_fire_T_11 = _will_fire_std_incoming_0_will_fire_T_7; // @[lsu.scala:533:63, :534:65] wire _will_fire_std_incoming_0_will_fire_T_8 = ~_will_fire_sta_incoming_0_T_8; // @[lsu.scala:535:50, :539:31] wire _will_fire_std_incoming_0_will_fire_T_12 = ~_will_fire_sta_incoming_0_T_11; // @[lsu.scala:536:51, :540:31] wire _will_fire_std_incoming_0_will_fire_T_13 = _will_fire_std_incoming_0_will_fire_T_12; // @[lsu.scala:536:{48,51}] wire _will_fire_std_incoming_0_will_fire_T_14 = ~_will_fire_std_incoming_0_will_fire_T_13; // @[lsu.scala:536:{35,48}] assign will_fire_std_incoming_0_will_fire = _will_fire_std_incoming_0_will_fire_T_11 & _will_fire_std_incoming_0_will_fire_T_14; // @[lsu.scala:534:65, :535:61, :536:35] assign will_fire_std_incoming_0 = will_fire_std_incoming_0_will_fire; // @[lsu.scala:373:38, :535:61] wire _will_fire_std_incoming_0_T_9 = will_fire_std_incoming_0_will_fire; // @[lsu.scala:535:61, :540:46] wire _will_fire_sfence_0_T_5 = _will_fire_std_incoming_0_T_5; // @[lsu.scala:538:31] wire _will_fire_sfence_0_T_8 = _will_fire_std_incoming_0_T_8; // @[lsu.scala:539:31] wire _will_fire_std_incoming_0_T_10 = ~_will_fire_std_incoming_0_T_9; // @[lsu.scala:540:{34,46}] wire _will_fire_std_incoming_0_T_11 = _will_fire_sta_incoming_0_T_11 & _will_fire_std_incoming_0_T_10; // @[lsu.scala:540:{31,34}] wire _will_fire_sfence_0_will_fire_T = ~_will_fire_std_incoming_0_T_2; // @[lsu.scala:533:51, :537:31] wire _will_fire_sfence_0_will_fire_T_1 = _will_fire_sfence_0_will_fire_T; // @[lsu.scala:533:{48,51}] wire _will_fire_sfence_0_will_fire_T_2 = ~_will_fire_sfence_0_will_fire_T_1; // @[lsu.scala:533:{35,48}] wire _will_fire_sfence_0_will_fire_T_3 = can_fire_sfence_0 & _will_fire_sfence_0_will_fire_T_2; // @[lsu.scala:263:49, :533:{32,35}] wire _will_fire_sfence_0_will_fire_T_7 = _will_fire_sfence_0_will_fire_T_3; // @[lsu.scala:533:{32,63}] wire _will_fire_sfence_0_will_fire_T_4 = ~_will_fire_std_incoming_0_T_5; // @[lsu.scala:534:52, :538:31] wire _will_fire_sfence_0_will_fire_T_11 = _will_fire_sfence_0_will_fire_T_7; // @[lsu.scala:533:63, :534:65] wire _will_fire_sfence_0_will_fire_T_8 = ~_will_fire_std_incoming_0_T_8; // @[lsu.scala:535:50, :539:31] wire _will_fire_sfence_0_will_fire_T_12 = ~_will_fire_std_incoming_0_T_11; // @[lsu.scala:536:51, :540:31] wire _will_fire_sfence_0_will_fire_T_13 = _will_fire_sfence_0_will_fire_T_12; // @[lsu.scala:536:{48,51}] wire _will_fire_sfence_0_will_fire_T_14 = ~_will_fire_sfence_0_will_fire_T_13; // @[lsu.scala:536:{35,48}] assign will_fire_sfence_0_will_fire = _will_fire_sfence_0_will_fire_T_11 & _will_fire_sfence_0_will_fire_T_14; // @[lsu.scala:534:65, :535:61, :536:35] assign will_fire_sfence_0 = will_fire_sfence_0_will_fire; // @[lsu.scala:374:38, :535:61] wire _will_fire_sfence_0_T = will_fire_sfence_0_will_fire; // @[lsu.scala:535:61, :537:46] wire _will_fire_sfence_0_T_9 = will_fire_sfence_0_will_fire; // @[lsu.scala:535:61, :540:46] wire _will_fire_sfence_0_T_1 = ~_will_fire_sfence_0_T; // @[lsu.scala:537:{34,46}] wire _will_fire_sfence_0_T_2 = _will_fire_std_incoming_0_T_2 & _will_fire_sfence_0_T_1; // @[lsu.scala:537:{31,34}] wire _will_fire_release_0_T_2 = _will_fire_sfence_0_T_2; // @[lsu.scala:537:31] wire _will_fire_release_0_T_8 = _will_fire_sfence_0_T_8; // @[lsu.scala:539:31] wire _will_fire_sfence_0_T_10 = ~_will_fire_sfence_0_T_9; // @[lsu.scala:540:{34,46}] wire _will_fire_sfence_0_T_11 = _will_fire_std_incoming_0_T_11 & _will_fire_sfence_0_T_10; // @[lsu.scala:540:{31,34}] wire _will_fire_release_0_T_11 = _will_fire_sfence_0_T_11; // @[lsu.scala:540:31] wire _will_fire_release_0_will_fire_T = ~_will_fire_sfence_0_T_2; // @[lsu.scala:533:51, :537:31] wire _will_fire_release_0_will_fire_T_4 = ~_will_fire_sfence_0_T_5; // @[lsu.scala:534:52, :538:31] wire _will_fire_release_0_will_fire_T_5 = _will_fire_release_0_will_fire_T_4; // @[lsu.scala:534:{49,52}] wire _will_fire_release_0_will_fire_T_6 = ~_will_fire_release_0_will_fire_T_5; // @[lsu.scala:534:{35,49}] wire _will_fire_release_0_will_fire_T_7 = _will_fire_release_0_will_fire_T_3 & _will_fire_release_0_will_fire_T_6; // @[lsu.scala:533:{32,63}, :534:35] wire _will_fire_release_0_will_fire_T_11 = _will_fire_release_0_will_fire_T_7; // @[lsu.scala:533:63, :534:65] wire _will_fire_release_0_will_fire_T_8 = ~_will_fire_sfence_0_T_8; // @[lsu.scala:535:50, :539:31] assign will_fire_release_0_will_fire = _will_fire_release_0_will_fire_T_11; // @[lsu.scala:534:65, :535:61] wire _will_fire_release_0_will_fire_T_12 = ~_will_fire_sfence_0_T_11; // @[lsu.scala:536:51, :540:31] assign will_fire_release_0 = will_fire_release_0_will_fire; // @[lsu.scala:377:38, :535:61] wire _will_fire_release_0_T_3 = will_fire_release_0_will_fire; // @[lsu.scala:535:61, :538:46] wire _will_fire_release_0_T_4 = ~_will_fire_release_0_T_3; // @[lsu.scala:538:{34,46}] wire _will_fire_release_0_T_5 = _will_fire_sfence_0_T_5 & _will_fire_release_0_T_4; // @[lsu.scala:538:{31,34}] wire _will_fire_hella_incoming_0_T_5 = _will_fire_release_0_T_5; // @[lsu.scala:538:31] wire _will_fire_hella_incoming_0_T_11 = _will_fire_release_0_T_11; // @[lsu.scala:540:31] wire _will_fire_hella_incoming_0_will_fire_T = ~_will_fire_release_0_T_2; // @[lsu.scala:533:51, :537:31] wire _will_fire_hella_incoming_0_will_fire_T_1 = _will_fire_hella_incoming_0_will_fire_T; // @[lsu.scala:533:{48,51}] wire _will_fire_hella_incoming_0_will_fire_T_2 = ~_will_fire_hella_incoming_0_will_fire_T_1; // @[lsu.scala:533:{35,48}] wire _will_fire_hella_incoming_0_will_fire_T_3 = can_fire_hella_incoming_0 & _will_fire_hella_incoming_0_will_fire_T_2; // @[lsu.scala:517:42, :533:{32,35}] wire _will_fire_hella_incoming_0_will_fire_T_7 = _will_fire_hella_incoming_0_will_fire_T_3; // @[lsu.scala:533:{32,63}] wire _will_fire_hella_incoming_0_will_fire_T_4 = ~_will_fire_release_0_T_5; // @[lsu.scala:534:52, :538:31] wire _will_fire_hella_incoming_0_will_fire_T_8 = ~_will_fire_release_0_T_8; // @[lsu.scala:535:50, :539:31] wire _will_fire_hella_incoming_0_will_fire_T_9 = _will_fire_hella_incoming_0_will_fire_T_8; // @[lsu.scala:535:{47,50}] wire _will_fire_hella_incoming_0_will_fire_T_10 = ~_will_fire_hella_incoming_0_will_fire_T_9; // @[lsu.scala:535:{35,47}] wire _will_fire_hella_incoming_0_will_fire_T_11 = _will_fire_hella_incoming_0_will_fire_T_7 & _will_fire_hella_incoming_0_will_fire_T_10; // @[lsu.scala:533:63, :534:65, :535:35] assign will_fire_hella_incoming_0_will_fire = _will_fire_hella_incoming_0_will_fire_T_11; // @[lsu.scala:534:65, :535:61] wire _will_fire_hella_incoming_0_will_fire_T_12 = ~_will_fire_release_0_T_11; // @[lsu.scala:536:51, :540:31] assign will_fire_hella_incoming_0 = will_fire_hella_incoming_0_will_fire; // @[lsu.scala:375:38, :535:61] wire _will_fire_hella_incoming_0_T = will_fire_hella_incoming_0_will_fire; // @[lsu.scala:535:61, :537:46] wire _will_fire_hella_incoming_0_T_6 = will_fire_hella_incoming_0_will_fire; // @[lsu.scala:535:61, :539:46] wire _will_fire_hella_incoming_0_T_1 = ~_will_fire_hella_incoming_0_T; // @[lsu.scala:537:{34,46}] wire _will_fire_hella_incoming_0_T_2 = _will_fire_release_0_T_2 & _will_fire_hella_incoming_0_T_1; // @[lsu.scala:537:{31,34}] wire _will_fire_hella_wakeup_0_T_2 = _will_fire_hella_incoming_0_T_2; // @[lsu.scala:537:31] wire _will_fire_hella_wakeup_0_T_5 = _will_fire_hella_incoming_0_T_5; // @[lsu.scala:538:31] wire _will_fire_hella_incoming_0_T_7 = ~_will_fire_hella_incoming_0_T_6; // @[lsu.scala:539:{34,46}] wire _will_fire_hella_incoming_0_T_8 = _will_fire_release_0_T_8 & _will_fire_hella_incoming_0_T_7; // @[lsu.scala:539:{31,34}] wire _will_fire_hella_wakeup_0_T_11 = _will_fire_hella_incoming_0_T_11; // @[lsu.scala:540:31] wire _will_fire_hella_wakeup_0_will_fire_T = ~_will_fire_hella_incoming_0_T_2; // @[lsu.scala:533:51, :537:31] wire _will_fire_hella_wakeup_0_will_fire_T_7 = _will_fire_hella_wakeup_0_will_fire_T_3; // @[lsu.scala:533:{32,63}] wire _will_fire_hella_wakeup_0_will_fire_T_4 = ~_will_fire_hella_incoming_0_T_5; // @[lsu.scala:534:52, :538:31] wire _will_fire_hella_wakeup_0_will_fire_T_8 = ~_will_fire_hella_incoming_0_T_8; // @[lsu.scala:535:50, :539:31] wire _will_fire_hella_wakeup_0_will_fire_T_9 = _will_fire_hella_wakeup_0_will_fire_T_8; // @[lsu.scala:535:{47,50}] wire _will_fire_hella_wakeup_0_will_fire_T_10 = ~_will_fire_hella_wakeup_0_will_fire_T_9; // @[lsu.scala:535:{35,47}] wire _will_fire_hella_wakeup_0_will_fire_T_11 = _will_fire_hella_wakeup_0_will_fire_T_7 & _will_fire_hella_wakeup_0_will_fire_T_10; // @[lsu.scala:533:63, :534:65, :535:35] assign will_fire_hella_wakeup_0_will_fire = _will_fire_hella_wakeup_0_will_fire_T_11; // @[lsu.scala:534:65, :535:61] wire _will_fire_hella_wakeup_0_will_fire_T_12 = ~_will_fire_hella_incoming_0_T_11; // @[lsu.scala:536:51, :540:31] assign will_fire_hella_wakeup_0 = will_fire_hella_wakeup_0_will_fire; // @[lsu.scala:376:38, :535:61] wire _will_fire_hella_wakeup_0_T_6 = will_fire_hella_wakeup_0_will_fire; // @[lsu.scala:535:61, :539:46] wire _will_fire_hella_wakeup_0_T_7 = ~_will_fire_hella_wakeup_0_T_6; // @[lsu.scala:539:{34,46}] wire _will_fire_hella_wakeup_0_T_8 = _will_fire_hella_incoming_0_T_8 & _will_fire_hella_wakeup_0_T_7; // @[lsu.scala:539:{31,34}] wire _will_fire_load_retry_0_T_11 = _will_fire_hella_wakeup_0_T_11; // @[lsu.scala:540:31] wire _will_fire_load_retry_0_will_fire_T = ~_will_fire_hella_wakeup_0_T_2; // @[lsu.scala:533:51, :537:31] wire _will_fire_load_retry_0_will_fire_T_1 = _will_fire_load_retry_0_will_fire_T; // @[lsu.scala:533:{48,51}] wire _will_fire_load_retry_0_will_fire_T_2 = ~_will_fire_load_retry_0_will_fire_T_1; // @[lsu.scala:533:{35,48}] wire _will_fire_load_retry_0_will_fire_T_3 = can_fire_load_retry_0 & _will_fire_load_retry_0_will_fire_T_2; // @[lsu.scala:263:49, :533:{32,35}] wire _will_fire_load_retry_0_will_fire_T_4 = ~_will_fire_hella_wakeup_0_T_5; // @[lsu.scala:534:52, :538:31] wire _will_fire_load_retry_0_will_fire_T_5 = _will_fire_load_retry_0_will_fire_T_4; // @[lsu.scala:534:{49,52}] wire _will_fire_load_retry_0_will_fire_T_6 = ~_will_fire_load_retry_0_will_fire_T_5; // @[lsu.scala:534:{35,49}] wire _will_fire_load_retry_0_will_fire_T_7 = _will_fire_load_retry_0_will_fire_T_3 & _will_fire_load_retry_0_will_fire_T_6; // @[lsu.scala:533:{32,63}, :534:35] wire _will_fire_load_retry_0_will_fire_T_8 = ~_will_fire_hella_wakeup_0_T_8; // @[lsu.scala:535:50, :539:31] wire _will_fire_load_retry_0_will_fire_T_9 = _will_fire_load_retry_0_will_fire_T_8; // @[lsu.scala:535:{47,50}] wire _will_fire_load_retry_0_will_fire_T_10 = ~_will_fire_load_retry_0_will_fire_T_9; // @[lsu.scala:535:{35,47}] wire _will_fire_load_retry_0_will_fire_T_11 = _will_fire_load_retry_0_will_fire_T_7 & _will_fire_load_retry_0_will_fire_T_10; // @[lsu.scala:533:63, :534:65, :535:35] assign will_fire_load_retry_0_will_fire = _will_fire_load_retry_0_will_fire_T_11; // @[lsu.scala:534:65, :535:61] wire _will_fire_load_retry_0_will_fire_T_12 = ~_will_fire_hella_wakeup_0_T_11; // @[lsu.scala:536:51, :540:31] assign will_fire_load_retry_0 = will_fire_load_retry_0_will_fire; // @[lsu.scala:378:38, :535:61] wire _will_fire_load_retry_0_T = will_fire_load_retry_0_will_fire; // @[lsu.scala:535:61, :537:46] wire _will_fire_load_retry_0_T_3 = will_fire_load_retry_0_will_fire; // @[lsu.scala:535:61, :538:46] wire _will_fire_load_retry_0_T_6 = will_fire_load_retry_0_will_fire; // @[lsu.scala:535:61, :539:46] wire _will_fire_load_retry_0_T_1 = ~_will_fire_load_retry_0_T; // @[lsu.scala:537:{34,46}] wire _will_fire_load_retry_0_T_2 = _will_fire_hella_wakeup_0_T_2 & _will_fire_load_retry_0_T_1; // @[lsu.scala:537:{31,34}] wire _will_fire_load_retry_0_T_4 = ~_will_fire_load_retry_0_T_3; // @[lsu.scala:538:{34,46}] wire _will_fire_load_retry_0_T_5 = _will_fire_hella_wakeup_0_T_5 & _will_fire_load_retry_0_T_4; // @[lsu.scala:538:{31,34}] wire _will_fire_load_retry_0_T_7 = ~_will_fire_load_retry_0_T_6; // @[lsu.scala:539:{34,46}] wire _will_fire_load_retry_0_T_8 = _will_fire_hella_wakeup_0_T_8 & _will_fire_load_retry_0_T_7; // @[lsu.scala:539:{31,34}] wire _will_fire_sta_retry_0_T_8 = _will_fire_load_retry_0_T_8; // @[lsu.scala:539:31] wire _will_fire_sta_retry_0_will_fire_T = ~_will_fire_load_retry_0_T_2; // @[lsu.scala:533:51, :537:31] wire _will_fire_sta_retry_0_will_fire_T_1 = _will_fire_sta_retry_0_will_fire_T; // @[lsu.scala:533:{48,51}] wire _will_fire_sta_retry_0_will_fire_T_2 = ~_will_fire_sta_retry_0_will_fire_T_1; // @[lsu.scala:533:{35,48}] wire _will_fire_sta_retry_0_will_fire_T_3 = can_fire_sta_retry_0 & _will_fire_sta_retry_0_will_fire_T_2; // @[lsu.scala:263:49, :533:{32,35}] wire _will_fire_sta_retry_0_will_fire_T_4 = ~_will_fire_load_retry_0_T_5; // @[lsu.scala:534:52, :538:31] wire _will_fire_sta_retry_0_will_fire_T_5 = _will_fire_sta_retry_0_will_fire_T_4; // @[lsu.scala:534:{49,52}] wire _will_fire_sta_retry_0_will_fire_T_6 = ~_will_fire_sta_retry_0_will_fire_T_5; // @[lsu.scala:534:{35,49}] wire _will_fire_sta_retry_0_will_fire_T_7 = _will_fire_sta_retry_0_will_fire_T_3 & _will_fire_sta_retry_0_will_fire_T_6; // @[lsu.scala:533:{32,63}, :534:35] wire _will_fire_sta_retry_0_will_fire_T_11 = _will_fire_sta_retry_0_will_fire_T_7; // @[lsu.scala:533:63, :534:65] wire _will_fire_sta_retry_0_will_fire_T_8 = ~_will_fire_load_retry_0_T_8; // @[lsu.scala:535:50, :539:31] wire _will_fire_sta_retry_0_will_fire_T_12 = ~_will_fire_load_retry_0_T_11; // @[lsu.scala:536:51, :540:31] wire _will_fire_sta_retry_0_will_fire_T_13 = _will_fire_sta_retry_0_will_fire_T_12; // @[lsu.scala:536:{48,51}] wire _will_fire_sta_retry_0_will_fire_T_14 = ~_will_fire_sta_retry_0_will_fire_T_13; // @[lsu.scala:536:{35,48}] assign will_fire_sta_retry_0_will_fire = _will_fire_sta_retry_0_will_fire_T_11 & _will_fire_sta_retry_0_will_fire_T_14; // @[lsu.scala:534:65, :535:61, :536:35] assign will_fire_sta_retry_0 = will_fire_sta_retry_0_will_fire; // @[lsu.scala:379:38, :535:61] wire _will_fire_sta_retry_0_T = will_fire_sta_retry_0_will_fire; // @[lsu.scala:535:61, :537:46] wire _will_fire_sta_retry_0_T_3 = will_fire_sta_retry_0_will_fire; // @[lsu.scala:535:61, :538:46] wire _will_fire_sta_retry_0_T_9 = will_fire_sta_retry_0_will_fire; // @[lsu.scala:535:61, :540:46] wire _will_fire_sta_retry_0_T_1 = ~_will_fire_sta_retry_0_T; // @[lsu.scala:537:{34,46}] wire _will_fire_sta_retry_0_T_2 = _will_fire_load_retry_0_T_2 & _will_fire_sta_retry_0_T_1; // @[lsu.scala:537:{31,34}] wire _will_fire_load_wakeup_0_T_2 = _will_fire_sta_retry_0_T_2; // @[lsu.scala:537:31] wire _will_fire_sta_retry_0_T_4 = ~_will_fire_sta_retry_0_T_3; // @[lsu.scala:538:{34,46}] wire _will_fire_sta_retry_0_T_5 = _will_fire_load_retry_0_T_5 & _will_fire_sta_retry_0_T_4; // @[lsu.scala:538:{31,34}] wire _will_fire_sta_retry_0_T_10 = ~_will_fire_sta_retry_0_T_9; // @[lsu.scala:540:{34,46}] wire _will_fire_sta_retry_0_T_11 = _will_fire_load_retry_0_T_11 & _will_fire_sta_retry_0_T_10; // @[lsu.scala:540:{31,34}] wire _will_fire_load_wakeup_0_T_11 = _will_fire_sta_retry_0_T_11; // @[lsu.scala:540:31] wire _will_fire_load_wakeup_0_will_fire_T = ~_will_fire_sta_retry_0_T_2; // @[lsu.scala:533:51, :537:31] wire _will_fire_load_wakeup_0_will_fire_T_4 = ~_will_fire_sta_retry_0_T_5; // @[lsu.scala:534:52, :538:31] wire _will_fire_load_wakeup_0_will_fire_T_5 = _will_fire_load_wakeup_0_will_fire_T_4; // @[lsu.scala:534:{49,52}] wire _will_fire_load_wakeup_0_will_fire_T_6 = ~_will_fire_load_wakeup_0_will_fire_T_5; // @[lsu.scala:534:{35,49}] wire _will_fire_load_wakeup_0_will_fire_T_7 = _will_fire_load_wakeup_0_will_fire_T_3 & _will_fire_load_wakeup_0_will_fire_T_6; // @[lsu.scala:533:{32,63}, :534:35] wire _will_fire_load_wakeup_0_will_fire_T_8 = ~_will_fire_sta_retry_0_T_8; // @[lsu.scala:535:50, :539:31] wire _will_fire_load_wakeup_0_will_fire_T_9 = _will_fire_load_wakeup_0_will_fire_T_8; // @[lsu.scala:535:{47,50}] wire _will_fire_load_wakeup_0_will_fire_T_10 = ~_will_fire_load_wakeup_0_will_fire_T_9; // @[lsu.scala:535:{35,47}] wire _will_fire_load_wakeup_0_will_fire_T_11 = _will_fire_load_wakeup_0_will_fire_T_7 & _will_fire_load_wakeup_0_will_fire_T_10; // @[lsu.scala:533:63, :534:65, :535:35] assign will_fire_load_wakeup_0_will_fire = _will_fire_load_wakeup_0_will_fire_T_11; // @[lsu.scala:534:65, :535:61] wire _will_fire_load_wakeup_0_will_fire_T_12 = ~_will_fire_sta_retry_0_T_11; // @[lsu.scala:536:51, :540:31] assign will_fire_load_wakeup_0 = will_fire_load_wakeup_0_will_fire; // @[lsu.scala:381:38, :535:61] wire _will_fire_load_wakeup_0_T_3 = will_fire_load_wakeup_0_will_fire; // @[lsu.scala:535:61, :538:46] wire _will_fire_load_wakeup_0_T_6 = will_fire_load_wakeup_0_will_fire; // @[lsu.scala:535:61, :539:46] wire _will_fire_store_commit_0_T_2 = _will_fire_load_wakeup_0_T_2; // @[lsu.scala:537:31] wire _will_fire_load_wakeup_0_T_4 = ~_will_fire_load_wakeup_0_T_3; // @[lsu.scala:538:{34,46}] wire _will_fire_load_wakeup_0_T_5 = _will_fire_sta_retry_0_T_5 & _will_fire_load_wakeup_0_T_4; // @[lsu.scala:538:{31,34}] wire _will_fire_store_commit_0_T_5 = _will_fire_load_wakeup_0_T_5; // @[lsu.scala:538:31] wire _will_fire_load_wakeup_0_T_7 = ~_will_fire_load_wakeup_0_T_6; // @[lsu.scala:539:{34,46}] wire _will_fire_load_wakeup_0_T_8 = _will_fire_sta_retry_0_T_8 & _will_fire_load_wakeup_0_T_7; // @[lsu.scala:539:{31,34}] wire _will_fire_store_commit_0_T_11 = _will_fire_load_wakeup_0_T_11; // @[lsu.scala:540:31] wire _will_fire_store_commit_0_will_fire_T = ~_will_fire_load_wakeup_0_T_2; // @[lsu.scala:533:51, :537:31] wire _will_fire_store_commit_0_will_fire_T_7 = _will_fire_store_commit_0_will_fire_T_3; // @[lsu.scala:533:{32,63}] wire _will_fire_store_commit_0_will_fire_T_4 = ~_will_fire_load_wakeup_0_T_5; // @[lsu.scala:534:52, :538:31] wire _will_fire_store_commit_0_will_fire_T_8 = ~_will_fire_load_wakeup_0_T_8; // @[lsu.scala:535:50, :539:31] wire _will_fire_store_commit_0_will_fire_T_9 = _will_fire_store_commit_0_will_fire_T_8; // @[lsu.scala:535:{47,50}] wire _will_fire_store_commit_0_will_fire_T_10 = ~_will_fire_store_commit_0_will_fire_T_9; // @[lsu.scala:535:{35,47}] wire _will_fire_store_commit_0_will_fire_T_11 = _will_fire_store_commit_0_will_fire_T_7 & _will_fire_store_commit_0_will_fire_T_10; // @[lsu.scala:533:63, :534:65, :535:35] assign will_fire_store_commit_0_will_fire = _will_fire_store_commit_0_will_fire_T_11; // @[lsu.scala:534:65, :535:61] wire _will_fire_store_commit_0_will_fire_T_12 = ~_will_fire_load_wakeup_0_T_11; // @[lsu.scala:536:51, :540:31] assign will_fire_store_commit_0 = will_fire_store_commit_0_will_fire; // @[lsu.scala:380:38, :535:61] wire _will_fire_store_commit_0_T_6 = will_fire_store_commit_0_will_fire; // @[lsu.scala:535:61, :539:46] wire _will_fire_store_commit_0_T_7 = ~_will_fire_store_commit_0_T_6; // @[lsu.scala:539:{34,46}] wire _will_fire_store_commit_0_T_8 = _will_fire_load_wakeup_0_T_8 & _will_fire_store_commit_0_T_7; // @[lsu.scala:539:{31,34}] wire _T_109 = will_fire_load_incoming_0 \| will_fire_stad_incoming_0; // @[lsu.scala:370:38, :371:38, :566:63] wire _exe_tlb_uop_T; // @[lsu.scala:596:53] assign _exe_tlb_uop_T = _T_109; // @[lsu.scala:566:63, :596:53] wire _exe_tlb_vaddr_T; // @[lsu.scala:606:53] assign _exe_tlb_vaddr_T = _T_109; // @[lsu.scala:566:63, :606:53] wire _exe_size_T; // @[lsu.scala:623:52] assign _exe_size_T = _T_109; // @[lsu.scala:566:63, :623:52] wire _exe_cmd_T; // @[lsu.scala:632:52] assign _exe_cmd_T = _T_109; // @[lsu.scala:566:63, :632:52] wire _GEN_203 = ldq_wakeup_idx == 3'h0; // @[lsu.scala:429:31, :569:49] wire _GEN_204 = ldq_wakeup_idx == 3'h1; // @[lsu.scala:429:31, :569:49] wire _GEN_205 = ldq_wakeup_idx == 3'h2; // @[lsu.scala:429:31, :569:49] wire _GEN_206 = ldq_wakeup_idx == 3'h3; // @[lsu.scala:429:31, :569:49] wire _GEN_207 = ldq_wakeup_idx == 3'h4; // @[lsu.scala:429:31, :569:49] wire _GEN_208 = ldq_wakeup_idx == 3'h5; // @[lsu.scala:429:31, :569:49] wire _GEN_209 = ldq_wakeup_idx == 3'h6; // @[lsu.scala:429:31, :569:49] wire _GEN_210 = ldq_retry_idx == 3'h0; // @[lsu.scala:414:30, :573:49] assign block_load_mask_0 = will_fire_load_wakeup_0 ? _GEN_203 : will_fire_load_incoming_0 ? exe_req_0_bits_uop_ldq_idx == 3'h0 : will_fire_load_retry_0 & _GEN_210; // @[lsu.scala:370:38, :378:38, :381:38, :383:25, :396:36, :568:37, :569:49, :570:46, :571:52, :572:43, :573:49] wire _GEN_211 = ldq_retry_idx == 3'h1; // @[lsu.scala:414:30, :573:49] assign block_load_mask_1 = will_fire_load_wakeup_0 ? _GEN_204 : will_fire_load_incoming_0 ? exe_req_0_bits_uop_ldq_idx == 3'h1 : will_fire_load_retry_0 & _GEN_211; // @[lsu.scala:370:38, :378:38, :381:38, :383:25, :396:36, :568:37, :569:49, :570:46, :571:52, :572:43, :573:49] wire _GEN_212 = ldq_retry_idx == 3'h2; // @[lsu.scala:414:30, :573:49] assign block_load_mask_2 = will_fire_load_wakeup_0 ? _GEN_205 : will_fire_load_incoming_0 ? exe_req_0_bits_uop_ldq_idx == 3'h2 : will_fire_load_retry_0 & _GEN_212; // @[lsu.scala:370:38, :378:38, :381:38, :383:25, :396:36, :568:37, :569:49, :570:46, :571:52, :572:43, :573:49] wire _GEN_213 = ldq_retry_idx == 3'h3; // @[lsu.scala:414:30, :573:49] assign block_load_mask_3 = will_fire_load_wakeup_0 ? _GEN_206 : will_fire_load_incoming_0 ? exe_req_0_bits_uop_ldq_idx == 3'h3 : will_fire_load_retry_0 & _GEN_213; // @[lsu.scala:370:38, :378:38, :381:38, :383:25, :396:36, :568:37, :569:49, :570:46, :571:52, :572:43, :573:49] wire _GEN_214 = ldq_retry_idx == 3'h4; // @[lsu.scala:414:30, :573:49] assign block_load_mask_4 = will_fire_load_wakeup_0 ? _GEN_207 : will_fire_load_incoming_0 ? exe_req_0_bits_uop_ldq_idx == 3'h4 : will_fire_load_retry_0 & _GEN_214; // @[lsu.scala:370:38, :378:38, :381:38, :383:25, :396:36, :568:37, :569:49, :570:46, :571:52, :572:43, :573:49] wire _GEN_215 = ldq_retry_idx == 3'h5; // @[lsu.scala:414:30, :573:49] assign block_load_mask_5 = will_fire_load_wakeup_0 ? _GEN_208 : will_fire_load_incoming_0 ? exe_req_0_bits_uop_ldq_idx == 3'h5 : will_fire_load_retry_0 & _GEN_215; // @[lsu.scala:370:38, :378:38, :381:38, :383:25, :396:36, :568:37, :569:49, :570:46, :571:52, :572:43, :573:49] wire _GEN_216 = ldq_retry_idx == 3'h6; // @[lsu.scala:414:30, :573:49] assign block_load_mask_6 = will_fire_load_wakeup_0 ? _GEN_209 : will_fire_load_incoming_0 ? exe_req_0_bits_uop_ldq_idx == 3'h6 : will_fire_load_retry_0 & _GEN_216; // @[lsu.scala:370:38, :378:38, :381:38, :383:25, :396:36, :568:37, :569:49, :570:46, :571:52, :572:43, :573:49] assign block_load_mask_7 = will_fire_load_wakeup_0 ? (&ldq_wakeup_idx) : will_fire_load_incoming_0 ? (&exe_req_0_bits_uop_ldq_idx) : will_fire_load_retry_0 & (&ldq_retry_idx); // @[lsu.scala:370:38, :378:38, :381:38, :383:25, :396:36, :414:30, :429:31, :568:37, :569:49, :570:46, :571:52, :572:43, :573:49] assign _exe_tlb_valid_0_T = ~_will_fire_store_commit_0_T_2; // @[lsu.scala:537:31, :575:25] assign exe_tlb_valid_0 = _exe_tlb_valid_0_T; // @[lsu.scala:525:27, :575:25] wire _exe_tlb_uop_T_1 = _exe_tlb_uop_T \| will_fire_sta_incoming_0; // @[lsu.scala:372:38, :596:53, :597:53] wire _exe_tlb_uop_T_2 = _exe_tlb_uop_T_1 \| will_fire_sfence_0; // @[lsu.scala:374:38, :597:53, :598:53] wire [6:0] _exe_tlb_uop_T_4_uopc = will_fire_sta_retry_0 ? mem_stq_retry_e_out_bits_uop_uopc : 7'h0; // @[util.scala:106:23] wire [31:0] _exe_tlb_uop_T_4_inst = will_fire_sta_retry_0 ? mem_stq_retry_e_out_bits_uop_inst : 32'h0; // @[util.scala:106:23] wire [31:0] _exe_tlb_uop_T_4_debug_inst = will_fire_sta_retry_0 ? mem_stq_retry_e_out_bits_uop_debug_inst : 32'h0; // @[util.scala:106:23] wire _exe_tlb_uop_T_4_is_rvc = will_fire_sta_retry_0 & mem_stq_retry_e_out_bits_uop_is_rvc; // @[util.scala:106:23] wire [39:0] _exe_tlb_uop_T_4_debug_pc = will_fire_sta_retry_0 ? mem_stq_retry_e_out_bits_uop_debug_pc : 40'h0; // @[util.scala:106:23] wire [2:0] _exe_tlb_uop_T_4_iq_type = will_fire_sta_retry_0 ? mem_stq_retry_e_out_bits_uop_iq_type : 3'h0; // @[util.scala:106:23] wire [9:0] _exe_tlb_uop_T_4_fu_code = will_fire_sta_retry_0 ? mem_stq_retry_e_out_bits_uop_fu_code : 10'h0; // @[util.scala:106:23] wire [3:0] _exe_tlb_uop_T_4_ctrl_br_type = will_fire_sta_retry_0 ? mem_stq_retry_e_out_bits_uop_ctrl_br_type : 4'h0; // @[util.scala:106:23] wire [1:0] _exe_tlb_uop_T_4_ctrl_op1_sel = will_fire_sta_retry_0 ? mem_stq_retry_e_out_bits_uop_ctrl_op1_sel : 2'h0; // @[util.scala:106:23] wire [2:0] _exe_tlb_uop_T_4_ctrl_op2_sel = will_fire_sta_retry_0 ? mem_stq_retry_e_out_bits_uop_ctrl_op2_sel : 3'h0; // @[util.scala:106:23] wire [2:0] _exe_tlb_uop_T_4_ctrl_imm_sel = will_fire_sta_retry_0 ? mem_stq_retry_e_out_bits_uop_ctrl_imm_sel : 3'h0; // @[util.scala:106:23] wire [4:0] _exe_tlb_uop_T_4_ctrl_op_fcn = will_fire_sta_retry_0 ? mem_stq_retry_e_out_bits_uop_ctrl_op_fcn : 5'h0; // @[util.scala:106:23] wire _exe_tlb_uop_T_4_ctrl_fcn_dw = will_fire_sta_retry_0 & mem_stq_retry_e_out_bits_uop_ctrl_fcn_dw; // @[util.scala:106:23] wire [2:0] _exe_tlb_uop_T_4_ctrl_csr_cmd = will_fire_sta_retry_0 ? mem_stq_retry_e_out_bits_uop_ctrl_csr_cmd : 3'h0; // @[util.scala:106:23] wire _exe_tlb_uop_T_4_ctrl_is_load = will_fire_sta_retry_0 & mem_stq_retry_e_out_bits_uop_ctrl_is_load; // @[util.scala:106:23] wire _exe_tlb_uop_T_4_ctrl_is_sta = will_fire_sta_retry_0 & mem_stq_retry_e_out_bits_uop_ctrl_is_sta; // @[util.scala:106:23] wire _exe_tlb_uop_T_4_ctrl_is_std = will_fire_sta_retry_0 & mem_stq_retry_e_out_bits_uop_ctrl_is_std; // @[util.scala:106:23] wire [1:0] _exe_tlb_uop_T_4_iw_state = will_fire_sta_retry_0 ? mem_stq_retry_e_out_bits_uop_iw_state : 2'h0; // @[util.scala:106:23] wire _exe_tlb_uop_T_4_iw_p1_poisoned = will_fire_sta_retry_0 & mem_stq_retry_e_out_bits_uop_iw_p1_poisoned; // @[util.scala:106:23] wire _exe_tlb_uop_T_4_iw_p2_poisoned = will_fire_sta_retry_0 & mem_stq_retry_e_out_bits_uop_iw_p2_poisoned; // @[util.scala:106:23] wire _exe_tlb_uop_T_4_is_br = will_fire_sta_retry_0 & mem_stq_retry_e_out_bits_uop_is_br; // @[util.scala:106:23] wire _exe_tlb_uop_T_4_is_jalr = will_fire_sta_retry_0 & mem_stq_retry_e_out_bits_uop_is_jalr; // @[util.scala:106:23] wire _exe_tlb_uop_T_4_is_jal = will_fire_sta_retry_0 & mem_stq_retry_e_out_bits_uop_is_jal; // @[util.scala:106:23] wire _exe_tlb_uop_T_4_is_sfb = will_fire_sta_retry_0 & mem_stq_retry_e_out_bits_uop_is_sfb; // @[util.scala:106:23] wire [7:0] _exe_tlb_uop_T_4_br_mask = will_fire_sta_retry_0 ? _GEN_25[_stq_retry_e_T_1] : 8'h0; // @[lsu.scala:222:42, :379:38, :477:79, :601:24] wire [2:0] _exe_tlb_uop_T_4_br_tag = will_fire_sta_retry_0 ? mem_stq_retry_e_out_bits_uop_br_tag : 3'h0; // @[util.scala:106:23] wire [3:0] _exe_tlb_uop_T_4_ftq_idx = will_fire_sta_retry_0 ? mem_stq_retry_e_out_bits_uop_ftq_idx : 4'h0; // @[util.scala:106:23] wire _exe_tlb_uop_T_4_edge_inst = will_fire_sta_retry_0 & mem_stq_retry_e_out_bits_uop_edge_inst; // @[util.scala:106:23] wire [5:0] _exe_tlb_uop_T_4_pc_lob = will_fire_sta_retry_0 ? mem_stq_retry_e_out_bits_uop_pc_lob : 6'h0; // @[util.scala:106:23] wire _exe_tlb_uop_T_4_taken = will_fire_sta_retry_0 & mem_stq_retry_e_out_bits_uop_taken; // @[util.scala:106:23] wire [19:0] _exe_tlb_uop_T_4_imm_packed = will_fire_sta_retry_0 ? mem_stq_retry_e_out_bits_uop_imm_packed : 20'h0; // @[util.scala:106:23] wire [11:0] _exe_tlb_uop_T_4_csr_addr = will_fire_sta_retry_0 ? mem_stq_retry_e_out_bits_uop_csr_addr : 12'h0; // @[util.scala:106:23] wire [4:0] _exe_tlb_uop_T_4_rob_idx = will_fire_sta_retry_0 ? mem_stq_retry_e_out_bits_uop_rob_idx : 5'h0; // @[util.scala:106:23] wire [2:0] _exe_tlb_uop_T_4_ldq_idx = will_fire_sta_retry_0 ? mem_stq_retry_e_out_bits_uop_ldq_idx : 3'h0; // @[util.scala:106:23] wire [2:0] _exe_tlb_uop_T_4_stq_idx = will_fire_sta_retry_0 ? mem_stq_retry_e_out_bits_uop_stq_idx : 3'h0; // @[util.scala:106:23] wire [1:0] _exe_tlb_uop_T_4_rxq_idx = will_fire_sta_retry_0 ? mem_stq_retry_e_out_bits_uop_rxq_idx : 2'h0; // @[util.scala:106:23] wire [5:0] _exe_tlb_uop_T_4_pdst = will_fire_sta_retry_0 ? mem_stq_retry_e_out_bits_uop_pdst : 6'h0; // @[util.scala:106:23] wire [5:0] _exe_tlb_uop_T_4_prs1 = will_fire_sta_retry_0 ? mem_stq_retry_e_out_bits_uop_prs1 : 6'h0; // @[util.scala:106:23] wire [5:0] _exe_tlb_uop_T_4_prs2 = will_fire_sta_retry_0 ? mem_stq_retry_e_out_bits_uop_prs2 : 6'h0; // @[util.scala:106:23] wire [5:0] _exe_tlb_uop_T_4_prs3 = will_fire_sta_retry_0 ? mem_stq_retry_e_out_bits_uop_prs3 : 6'h0; // @[util.scala:106:23] wire [3:0] _exe_tlb_uop_T_4_ppred = will_fire_sta_retry_0 ? mem_stq_retry_e_out_bits_uop_ppred : 4'h0; // @[util.scala:106:23] wire _exe_tlb_uop_T_4_prs1_busy = will_fire_sta_retry_0 & mem_stq_retry_e_out_bits_uop_prs1_busy; // @[util.scala:106:23] wire _exe_tlb_uop_T_4_prs2_busy = will_fire_sta_retry_0 & mem_stq_retry_e_out_bits_uop_prs2_busy; // @[util.scala:106:23] wire _exe_tlb_uop_T_4_prs3_busy = will_fire_sta_retry_0 & mem_stq_retry_e_out_bits_uop_prs3_busy; // @[util.scala:106:23] wire _exe_tlb_uop_T_4_ppred_busy = will_fire_sta_retry_0 & mem_stq_retry_e_out_bits_uop_ppred_busy; // @[util.scala:106:23] wire [5:0] _exe_tlb_uop_T_4_stale_pdst = will_fire_sta_retry_0 ? mem_stq_retry_e_out_bits_uop_stale_pdst : 6'h0; // @[util.scala:106:23] wire _exe_tlb_uop_T_4_exception = will_fire_sta_retry_0 & mem_stq_retry_e_out_bits_uop_exception; // @[util.scala:106:23] wire [63:0] _exe_tlb_uop_T_4_exc_cause = will_fire_sta_retry_0 ? mem_stq_retry_e_out_bits_uop_exc_cause : 64'h0; // @[util.scala:106:23] wire _exe_tlb_uop_T_4_bypassable = will_fire_sta_retry_0 & mem_stq_retry_e_out_bits_uop_bypassable; // @[util.scala:106:23] wire [4:0] _exe_tlb_uop_T_4_mem_cmd = will_fire_sta_retry_0 ? mem_stq_retry_e_out_bits_uop_mem_cmd : 5'h0; // @[util.scala:106:23] wire [1:0] _exe_tlb_uop_T_4_mem_size = will_fire_sta_retry_0 ? mem_stq_retry_e_out_bits_uop_mem_size : 2'h0; // @[util.scala:106:23] wire _exe_tlb_uop_T_4_mem_signed = will_fire_sta_retry_0 & mem_stq_retry_e_out_bits_uop_mem_signed; // @[util.scala:106:23] wire _exe_tlb_uop_T_4_is_fence = will_fire_sta_retry_0 & mem_stq_retry_e_out_bits_uop_is_fence; // @[util.scala:106:23] wire _exe_tlb_uop_T_4_is_fencei = will_fire_sta_retry_0 & mem_stq_retry_e_out_bits_uop_is_fencei; // @[util.scala:106:23] wire _exe_tlb_uop_T_4_is_amo = will_fire_sta_retry_0 & mem_stq_retry_e_out_bits_uop_is_amo; // @[util.scala:106:23] wire _exe_tlb_uop_T_4_uses_ldq = will_fire_sta_retry_0 & mem_stq_retry_e_out_bits_uop_uses_ldq; // @[util.scala:106:23] wire _exe_tlb_uop_T_4_uses_stq = will_fire_sta_retry_0 & mem_stq_retry_e_out_bits_uop_uses_stq; // @[util.scala:106:23] wire _exe_tlb_uop_T_4_is_sys_pc2epc = will_fire_sta_retry_0 & mem_stq_retry_e_out_bits_uop_is_sys_pc2epc; // @[util.scala:106:23] wire _exe_tlb_uop_T_4_is_unique = will_fire_sta_retry_0 & mem_stq_retry_e_out_bits_uop_is_unique; // @[util.scala:106:23] wire _exe_tlb_uop_T_4_flush_on_commit = will_fire_sta_retry_0 & mem_stq_retry_e_out_bits_uop_flush_on_commit; // @[util.scala:106:23] wire _exe_tlb_uop_T_4_ldst_is_rs1 = will_fire_sta_retry_0 & mem_stq_retry_e_out_bits_uop_ldst_is_rs1; // @[util.scala:106:23] wire [5:0] _exe_tlb_uop_T_4_ldst = will_fire_sta_retry_0 ? mem_stq_retry_e_out_bits_uop_ldst : 6'h0; // @[util.scala:106:23] wire [5:0] _exe_tlb_uop_T_4_lrs1 = will_fire_sta_retry_0 ? mem_stq_retry_e_out_bits_uop_lrs1 : 6'h0; // @[util.scala:106:23] wire [5:0] _exe_tlb_uop_T_4_lrs2 = will_fire_sta_retry_0 ? mem_stq_retry_e_out_bits_uop_lrs2 : 6'h0; // @[util.scala:106:23] wire [5:0] _exe_tlb_uop_T_4_lrs3 = will_fire_sta_retry_0 ? mem_stq_retry_e_out_bits_uop_lrs3 : 6'h0; // @[util.scala:106:23] wire _exe_tlb_uop_T_4_ldst_val = will_fire_sta_retry_0 & mem_stq_retry_e_out_bits_uop_ldst_val; // @[util.scala:106:23] wire [1:0] _exe_tlb_uop_T_4_dst_rtype = will_fire_sta_retry_0 ? mem_stq_retry_e_out_bits_uop_dst_rtype : 2'h2; // @[util.scala:106:23] wire [1:0] _exe_tlb_uop_T_4_lrs1_rtype = will_fire_sta_retry_0 ? mem_stq_retry_e_out_bits_uop_lrs1_rtype : 2'h0; // @[util.scala:106:23] wire [1:0] _exe_tlb_uop_T_4_lrs2_rtype = will_fire_sta_retry_0 ? mem_stq_retry_e_out_bits_uop_lrs2_rtype : 2'h0; // @[util.scala:106:23] wire _exe_tlb_uop_T_4_frs3_en = will_fire_sta_retry_0 & mem_stq_retry_e_out_bits_uop_frs3_en; // @[util.scala:106:23] wire _exe_tlb_uop_T_4_fp_val = will_fire_sta_retry_0 & mem_stq_retry_e_out_bits_uop_fp_val; // @[util.scala:106:23] wire _exe_tlb_uop_T_4_fp_single = will_fire_sta_retry_0 & mem_stq_retry_e_out_bits_uop_fp_single; // @[util.scala:106:23] wire _exe_tlb_uop_T_4_xcpt_pf_if = will_fire_sta_retry_0 & mem_stq_retry_e_out_bits_uop_xcpt_pf_if; // @[util.scala:106:23] wire _exe_tlb_uop_T_4_xcpt_ae_if = will_fire_sta_retry_0 & mem_stq_retry_e_out_bits_uop_xcpt_ae_if; // @[util.scala:106:23] wire _exe_tlb_uop_T_4_xcpt_ma_if = will_fire_sta_retry_0 & mem_stq_retry_e_out_bits_uop_xcpt_ma_if; // @[util.scala:106:23] wire _exe_tlb_uop_T_4_bp_debug_if = will_fire_sta_retry_0 & mem_stq_retry_e_out_bits_uop_bp_debug_if; // @[util.scala:106:23] wire _exe_tlb_uop_T_4_bp_xcpt_if = will_fire_sta_retry_0 & mem_stq_retry_e_out_bits_uop_bp_xcpt_if; // @[util.scala:106:23] wire [1:0] _exe_tlb_uop_T_4_debug_fsrc = will_fire_sta_retry_0 ? mem_stq_retry_e_out_bits_uop_debug_fsrc : 2'h0; // @[util.scala:106:23] wire [1:0] _exe_tlb_uop_T_4_debug_tsrc = will_fire_sta_retry_0 ? mem_stq_retry_e_out_bits_uop_debug_tsrc : 2'h0; // @[util.scala:106:23] wire [6:0] _exe_tlb_uop_T_5_uopc = will_fire_load_retry_0 ? mem_ldq_retry_e_out_bits_uop_uopc : _exe_tlb_uop_T_4_uopc; // @[util.scala:106:23] wire [31:0] _exe_tlb_uop_T_5_inst = will_fire_load_retry_0 ? mem_ldq_retry_e_out_bits_uop_inst : _exe_tlb_uop_T_4_inst; // @[util.scala:106:23] wire [31:0] _exe_tlb_uop_T_5_debug_inst = will_fire_load_retry_0 ? mem_ldq_retry_e_out_bits_uop_debug_inst : _exe_tlb_uop_T_4_debug_inst; // @[util.scala:106:23] wire _exe_tlb_uop_T_5_is_rvc = will_fire_load_retry_0 ? mem_ldq_retry_e_out_bits_uop_is_rvc : _exe_tlb_uop_T_4_is_rvc; // @[util.scala:106:23] wire [39:0] _exe_tlb_uop_T_5_debug_pc = will_fire_load_retry_0 ? mem_ldq_retry_e_out_bits_uop_debug_pc : _exe_tlb_uop_T_4_debug_pc; // @[util.scala:106:23] wire [2:0] _exe_tlb_uop_T_5_iq_type = will_fire_load_retry_0 ? mem_ldq_retry_e_out_bits_uop_iq_type : _exe_tlb_uop_T_4_iq_type; // @[util.scala:106:23] wire [9:0] _exe_tlb_uop_T_5_fu_code = will_fire_load_retry_0 ? mem_ldq_retry_e_out_bits_uop_fu_code : _exe_tlb_uop_T_4_fu_code; // @[util.scala:106:23] wire [3:0] _exe_tlb_uop_T_5_ctrl_br_type = will_fire_load_retry_0 ? mem_ldq_retry_e_out_bits_uop_ctrl_br_type : _exe_tlb_uop_T_4_ctrl_br_type; // @[util.scala:106:23] wire [1:0] _exe_tlb_uop_T_5_ctrl_op1_sel = will_fire_load_retry_0 ? mem_ldq_retry_e_out_bits_uop_ctrl_op1_sel : _exe_tlb_uop_T_4_ctrl_op1_sel; // @[util.scala:106:23] wire [2:0] _exe_tlb_uop_T_5_ctrl_op2_sel = will_fire_load_retry_0 ? mem_ldq_retry_e_out_bits_uop_ctrl_op2_sel : _exe_tlb_uop_T_4_ctrl_op2_sel; // @[util.scala:106:23] wire [2:0] _exe_tlb_uop_T_5_ctrl_imm_sel = will_fire_load_retry_0 ? mem_ldq_retry_e_out_bits_uop_ctrl_imm_sel : _exe_tlb_uop_T_4_ctrl_imm_sel; // @[util.scala:106:23] wire [4:0] _exe_tlb_uop_T_5_ctrl_op_fcn = will_fire_load_retry_0 ? mem_ldq_retry_e_out_bits_uop_ctrl_op_fcn : _exe_tlb_uop_T_4_ctrl_op_fcn; // @[util.scala:106:23] wire _exe_tlb_uop_T_5_ctrl_fcn_dw = will_fire_load_retry_0 ? mem_ldq_retry_e_out_bits_uop_ctrl_fcn_dw : _exe_tlb_uop_T_4_ctrl_fcn_dw; // @[util.scala:106:23] wire [2:0] _exe_tlb_uop_T_5_ctrl_csr_cmd = will_fire_load_retry_0 ? mem_ldq_retry_e_out_bits_uop_ctrl_csr_cmd : _exe_tlb_uop_T_4_ctrl_csr_cmd; // @[util.scala:106:23] wire _exe_tlb_uop_T_5_ctrl_is_load = will_fire_load_retry_0 ? mem_ldq_retry_e_out_bits_uop_ctrl_is_load : _exe_tlb_uop_T_4_ctrl_is_load; // @[util.scala:106:23] wire _exe_tlb_uop_T_5_ctrl_is_sta = will_fire_load_retry_0 ? mem_ldq_retry_e_out_bits_uop_ctrl_is_sta : _exe_tlb_uop_T_4_ctrl_is_sta; // @[util.scala:106:23] wire _exe_tlb_uop_T_5_ctrl_is_std = will_fire_load_retry_0 ? mem_ldq_retry_e_out_bits_uop_ctrl_is_std : _exe_tlb_uop_T_4_ctrl_is_std; // @[util.scala:106:23] wire [1:0] _exe_tlb_uop_T_5_iw_state = will_fire_load_retry_0 ? mem_ldq_retry_e_out_bits_uop_iw_state : _exe_tlb_uop_T_4_iw_state; // @[util.scala:106:23] wire _exe_tlb_uop_T_5_iw_p1_poisoned = will_fire_load_retry_0 ? mem_ldq_retry_e_out_bits_uop_iw_p1_poisoned : _exe_tlb_uop_T_4_iw_p1_poisoned; // @[util.scala:106:23] wire _exe_tlb_uop_T_5_iw_p2_poisoned = will_fire_load_retry_0 ? mem_ldq_retry_e_out_bits_uop_iw_p2_poisoned : _exe_tlb_uop_T_4_iw_p2_poisoned; // @[util.scala:106:23] wire _exe_tlb_uop_T_5_is_br = will_fire_load_retry_0 ? mem_ldq_retry_e_out_bits_uop_is_br : _exe_tlb_uop_T_4_is_br; // @[util.scala:106:23] wire _exe_tlb_uop_T_5_is_jalr = will_fire_load_retry_0 ? mem_ldq_retry_e_out_bits_uop_is_jalr : _exe_tlb_uop_T_4_is_jalr; // @[util.scala:106:23] wire _exe_tlb_uop_T_5_is_jal = will_fire_load_retry_0 ? mem_ldq_retry_e_out_bits_uop_is_jal : _exe_tlb_uop_T_4_is_jal; // @[util.scala:106:23] wire _exe_tlb_uop_T_5_is_sfb = will_fire_load_retry_0 ? mem_ldq_retry_e_out_bits_uop_is_sfb : _exe_tlb_uop_T_4_is_sfb; // @[util.scala:106:23] wire [7:0] _exe_tlb_uop_T_5_br_mask = will_fire_load_retry_0 ? _GEN_118[_ldq_retry_e_T_1] : _exe_tlb_uop_T_4_br_mask; // @[lsu.scala:263:49, :378:38, :464:79, :600:24, :601:24] wire [2:0] _exe_tlb_uop_T_5_br_tag = will_fire_load_retry_0 ? mem_ldq_retry_e_out_bits_uop_br_tag : _exe_tlb_uop_T_4_br_tag; // @[util.scala:106:23] wire [3:0] _exe_tlb_uop_T_5_ftq_idx = will_fire_load_retry_0 ? mem_ldq_retry_e_out_bits_uop_ftq_idx : _exe_tlb_uop_T_4_ftq_idx; // @[util.scala:106:23] wire _exe_tlb_uop_T_5_edge_inst = will_fire_load_retry_0 ? mem_ldq_retry_e_out_bits_uop_edge_inst : _exe_tlb_uop_T_4_edge_inst; // @[util.scala:106:23] wire [5:0] _exe_tlb_uop_T_5_pc_lob = will_fire_load_retry_0 ? mem_ldq_retry_e_out_bits_uop_pc_lob : _exe_tlb_uop_T_4_pc_lob; // @[util.scala:106:23] wire _exe_tlb_uop_T_5_taken = will_fire_load_retry_0 ? mem_ldq_retry_e_out_bits_uop_taken : _exe_tlb_uop_T_4_taken; // @[util.scala:106:23] wire [19:0] _exe_tlb_uop_T_5_imm_packed = will_fire_load_retry_0 ? mem_ldq_retry_e_out_bits_uop_imm_packed : _exe_tlb_uop_T_4_imm_packed; // @[util.scala:106:23] wire [11:0] _exe_tlb_uop_T_5_csr_addr = will_fire_load_retry_0 ? mem_ldq_retry_e_out_bits_uop_csr_addr : _exe_tlb_uop_T_4_csr_addr; // @[util.scala:106:23] wire [4:0] _exe_tlb_uop_T_5_rob_idx = will_fire_load_retry_0 ? mem_ldq_retry_e_out_bits_uop_rob_idx : _exe_tlb_uop_T_4_rob_idx; // @[util.scala:106:23] wire [2:0] _exe_tlb_uop_T_5_ldq_idx = will_fire_load_retry_0 ? mem_ldq_retry_e_out_bits_uop_ldq_idx : _exe_tlb_uop_T_4_ldq_idx; // @[util.scala:106:23] wire [2:0] _exe_tlb_uop_T_5_stq_idx = will_fire_load_retry_0 ? mem_ldq_retry_e_out_bits_uop_stq_idx : _exe_tlb_uop_T_4_stq_idx; // @[util.scala:106:23] wire [1:0] _exe_tlb_uop_T_5_rxq_idx = will_fire_load_retry_0 ? mem_ldq_retry_e_out_bits_uop_rxq_idx : _exe_tlb_uop_T_4_rxq_idx; // @[util.scala:106:23] wire [5:0] _exe_tlb_uop_T_5_pdst = will_fire_load_retry_0 ? mem_ldq_retry_e_out_bits_uop_pdst : _exe_tlb_uop_T_4_pdst; // @[util.scala:106:23] wire [5:0] _exe_tlb_uop_T_5_prs1 = will_fire_load_retry_0 ? mem_ldq_retry_e_out_bits_uop_prs1 : _exe_tlb_uop_T_4_prs1; // @[util.scala:106:23] wire [5:0] _exe_tlb_uop_T_5_prs2 = will_fire_load_retry_0 ? mem_ldq_retry_e_out_bits_uop_prs2 : _exe_tlb_uop_T_4_prs2; // @[util.scala:106:23] wire [5:0] _exe_tlb_uop_T_5_prs3 = will_fire_load_retry_0 ? mem_ldq_retry_e_out_bits_uop_prs3 : _exe_tlb_uop_T_4_prs3; // @[util.scala:106:23] wire [3:0] _exe_tlb_uop_T_5_ppred = will_fire_load_retry_0 ? 4'h0 : _exe_tlb_uop_T_4_ppred; // @[lsu.scala:378:38, :600:24, :601:24] wire _exe_tlb_uop_T_5_prs1_busy = will_fire_load_retry_0 ? mem_ldq_retry_e_out_bits_uop_prs1_busy : _exe_tlb_uop_T_4_prs1_busy; // @[util.scala:106:23] wire _exe_tlb_uop_T_5_prs2_busy = will_fire_load_retry_0 ? mem_ldq_retry_e_out_bits_uop_prs2_busy : _exe_tlb_uop_T_4_prs2_busy; // @[util.scala:106:23] wire _exe_tlb_uop_T_5_prs3_busy = will_fire_load_retry_0 ? mem_ldq_retry_e_out_bits_uop_prs3_busy : _exe_tlb_uop_T_4_prs3_busy; // @[util.scala:106:23] wire _exe_tlb_uop_T_5_ppred_busy = ~will_fire_load_retry_0 & _exe_tlb_uop_T_4_ppred_busy; // @[lsu.scala:378:38, :600:24, :601:24] wire [5:0] _exe_tlb_uop_T_5_stale_pdst = will_fire_load_retry_0 ? mem_ldq_retry_e_out_bits_uop_stale_pdst : _exe_tlb_uop_T_4_stale_pdst; // @[util.scala:106:23] wire _exe_tlb_uop_T_5_exception = will_fire_load_retry_0 ? mem_ldq_retry_e_out_bits_uop_exception : _exe_tlb_uop_T_4_exception; // @[util.scala:106:23] wire [63:0] _exe_tlb_uop_T_5_exc_cause = will_fire_load_retry_0 ? mem_ldq_retry_e_out_bits_uop_exc_cause : _exe_tlb_uop_T_4_exc_cause; // @[util.scala:106:23] wire _exe_tlb_uop_T_5_bypassable = will_fire_load_retry_0 ? mem_ldq_retry_e_out_bits_uop_bypassable : _exe_tlb_uop_T_4_bypassable; // @[util.scala:106:23] wire [4:0] _exe_tlb_uop_T_5_mem_cmd = will_fire_load_retry_0 ? mem_ldq_retry_e_out_bits_uop_mem_cmd : _exe_tlb_uop_T_4_mem_cmd; // @[util.scala:106:23] wire [1:0] _exe_tlb_uop_T_5_mem_size = will_fire_load_retry_0 ? mem_ldq_retry_e_out_bits_uop_mem_size : _exe_tlb_uop_T_4_mem_size; // @[util.scala:106:23] wire _exe_tlb_uop_T_5_mem_signed = will_fire_load_retry_0 ? mem_ldq_retry_e_out_bits_uop_mem_signed : _exe_tlb_uop_T_4_mem_signed; // @[util.scala:106:23] wire _exe_tlb_uop_T_5_is_fence = will_fire_load_retry_0 ? mem_ldq_retry_e_out_bits_uop_is_fence : _exe_tlb_uop_T_4_is_fence; // @[util.scala:106:23] wire _exe_tlb_uop_T_5_is_fencei = will_fire_load_retry_0 ? mem_ldq_retry_e_out_bits_uop_is_fencei : _exe_tlb_uop_T_4_is_fencei; // @[util.scala:106:23] wire _exe_tlb_uop_T_5_is_amo = will_fire_load_retry_0 ? mem_ldq_retry_e_out_bits_uop_is_amo : _exe_tlb_uop_T_4_is_amo; // @[util.scala:106:23] wire _exe_tlb_uop_T_5_uses_ldq = will_fire_load_retry_0 ? mem_ldq_retry_e_out_bits_uop_uses_ldq : _exe_tlb_uop_T_4_uses_ldq; // @[util.scala:106:23] wire _exe_tlb_uop_T_5_uses_stq = will_fire_load_retry_0 ? mem_ldq_retry_e_out_bits_uop_uses_stq : _exe_tlb_uop_T_4_uses_stq; // @[util.scala:106:23] wire _exe_tlb_uop_T_5_is_sys_pc2epc = will_fire_load_retry_0 ? mem_ldq_retry_e_out_bits_uop_is_sys_pc2epc : _exe_tlb_uop_T_4_is_sys_pc2epc; // @[util.scala:106:23] wire _exe_tlb_uop_T_5_is_unique = will_fire_load_retry_0 ? mem_ldq_retry_e_out_bits_uop_is_unique : _exe_tlb_uop_T_4_is_unique; // @[util.scala:106:23] wire _exe_tlb_uop_T_5_flush_on_commit = will_fire_load_retry_0 ? mem_ldq_retry_e_out_bits_uop_flush_on_commit : _exe_tlb_uop_T_4_flush_on_commit; // @[util.scala:106:23] wire _exe_tlb_uop_T_5_ldst_is_rs1 = will_fire_load_retry_0 ? mem_ldq_retry_e_out_bits_uop_ldst_is_rs1 : _exe_tlb_uop_T_4_ldst_is_rs1; // @[util.scala:106:23] wire [5:0] _exe_tlb_uop_T_5_ldst = will_fire_load_retry_0 ? mem_ldq_retry_e_out_bits_uop_ldst : _exe_tlb_uop_T_4_ldst; // @[util.scala:106:23] wire [5:0] _exe_tlb_uop_T_5_lrs1 = will_fire_load_retry_0 ? mem_ldq_retry_e_out_bits_uop_lrs1 : _exe_tlb_uop_T_4_lrs1; // @[util.scala:106:23] wire [5:0] _exe_tlb_uop_T_5_lrs2 = will_fire_load_retry_0 ? mem_ldq_retry_e_out_bits_uop_lrs2 : _exe_tlb_uop_T_4_lrs2; // @[util.scala:106:23] wire [5:0] _exe_tlb_uop_T_5_lrs3 = will_fire_load_retry_0 ? mem_ldq_retry_e_out_bits_uop_lrs3 : _exe_tlb_uop_T_4_lrs3; // @[util.scala:106:23] wire _exe_tlb_uop_T_5_ldst_val = will_fire_load_retry_0 ? mem_ldq_retry_e_out_bits_uop_ldst_val : _exe_tlb_uop_T_4_ldst_val; // @[util.scala:106:23] wire [1:0] _exe_tlb_uop_T_5_dst_rtype = will_fire_load_retry_0 ? mem_ldq_retry_e_out_bits_uop_dst_rtype : _exe_tlb_uop_T_4_dst_rtype; // @[util.scala:106:23] wire [1:0] _exe_tlb_uop_T_5_lrs1_rtype = will_fire_load_retry_0 ? mem_ldq_retry_e_out_bits_uop_lrs1_rtype : _exe_tlb_uop_T_4_lrs1_rtype; // @[util.scala:106:23] wire [1:0] _exe_tlb_uop_T_5_lrs2_rtype = will_fire_load_retry_0 ? mem_ldq_retry_e_out_bits_uop_lrs2_rtype : _exe_tlb_uop_T_4_lrs2_rtype; // @[util.scala:106:23] wire _exe_tlb_uop_T_5_frs3_en = will_fire_load_retry_0 ? mem_ldq_retry_e_out_bits_uop_frs3_en : _exe_tlb_uop_T_4_frs3_en; // @[util.scala:106:23] wire _exe_tlb_uop_T_5_fp_val = will_fire_load_retry_0 ? mem_ldq_retry_e_out_bits_uop_fp_val : _exe_tlb_uop_T_4_fp_val; // @[util.scala:106:23] wire _exe_tlb_uop_T_5_fp_single = will_fire_load_retry_0 ? mem_ldq_retry_e_out_bits_uop_fp_single : _exe_tlb_uop_T_4_fp_single; // @[util.scala:106:23] wire _exe_tlb_uop_T_5_xcpt_pf_if = will_fire_load_retry_0 ? mem_ldq_retry_e_out_bits_uop_xcpt_pf_if : _exe_tlb_uop_T_4_xcpt_pf_if; // @[util.scala:106:23] wire _exe_tlb_uop_T_5_xcpt_ae_if = will_fire_load_retry_0 ? mem_ldq_retry_e_out_bits_uop_xcpt_ae_if : _exe_tlb_uop_T_4_xcpt_ae_if; // @[util.scala:106:23] wire _exe_tlb_uop_T_5_xcpt_ma_if = will_fire_load_retry_0 ? mem_ldq_retry_e_out_bits_uop_xcpt_ma_if : _exe_tlb_uop_T_4_xcpt_ma_if; // @[util.scala:106:23] wire _exe_tlb_uop_T_5_bp_debug_if = will_fire_load_retry_0 ? mem_ldq_retry_e_out_bits_uop_bp_debug_if : _exe_tlb_uop_T_4_bp_debug_if; // @[util.scala:106:23] wire _exe_tlb_uop_T_5_bp_xcpt_if = will_fire_load_retry_0 ? mem_ldq_retry_e_out_bits_uop_bp_xcpt_if : _exe_tlb_uop_T_4_bp_xcpt_if; // @[util.scala:106:23] wire [1:0] _exe_tlb_uop_T_5_debug_fsrc = will_fire_load_retry_0 ? mem_ldq_retry_e_out_bits_uop_debug_fsrc : _exe_tlb_uop_T_4_debug_fsrc; // @[util.scala:106:23] wire [1:0] _exe_tlb_uop_T_5_debug_tsrc = will_fire_load_retry_0 ? mem_ldq_retry_e_out_bits_uop_debug_tsrc : _exe_tlb_uop_T_4_debug_tsrc; // @[util.scala:106:23] wire [6:0] _exe_tlb_uop_T_6_uopc = _exe_tlb_uop_T_2 ? exe_req_0_bits_uop_uopc : _exe_tlb_uop_T_5_uopc; // @[lsu.scala:383:25, :596:24, :598:53, :600:24] wire [31:0] _exe_tlb_uop_T_6_inst = _exe_tlb_uop_T_2 ? exe_req_0_bits_uop_inst : _exe_tlb_uop_T_5_inst; // @[lsu.scala:383:25, :596:24, :598:53, :600:24] wire [31:0] _exe_tlb_uop_T_6_debug_inst = _exe_tlb_uop_T_2 ? exe_req_0_bits_uop_debug_inst : _exe_tlb_uop_T_5_debug_inst; // @[lsu.scala:383:25, :596:24, :598:53, :600:24] wire _exe_tlb_uop_T_6_is_rvc = _exe_tlb_uop_T_2 ? exe_req_0_bits_uop_is_rvc : _exe_tlb_uop_T_5_is_rvc; // @[lsu.scala:383:25, :596:24, :598:53, :600:24] wire [39:0] _exe_tlb_uop_T_6_debug_pc = _exe_tlb_uop_T_2 ? exe_req_0_bits_uop_debug_pc : _exe_tlb_uop_T_5_debug_pc; // @[lsu.scala:383:25, :596:24, :598:53, :600:24] wire [2:0] _exe_tlb_uop_T_6_iq_type = _exe_tlb_uop_T_2 ? exe_req_0_bits_uop_iq_type : _exe_tlb_uop_T_5_iq_type; // @[lsu.scala:383:25, :596:24, :598:53, :600:24] wire [9:0] _exe_tlb_uop_T_6_fu_code = _exe_tlb_uop_T_2 ? exe_req_0_bits_uop_fu_code : _exe_tlb_uop_T_5_fu_code; // @[lsu.scala:383:25, :596:24, :598:53, :600:24] wire [3:0] _exe_tlb_uop_T_6_ctrl_br_type = _exe_tlb_uop_T_2 ? exe_req_0_bits_uop_ctrl_br_type : _exe_tlb_uop_T_5_ctrl_br_type; // @[lsu.scala:383:25, :596:24, :598:53, :600:24] wire [1:0] _exe_tlb_uop_T_6_ctrl_op1_sel = _exe_tlb_uop_T_2 ? exe_req_0_bits_uop_ctrl_op1_sel : _exe_tlb_uop_T_5_ctrl_op1_sel; // @[lsu.scala:383:25, :596:24, :598:53, :600:24] wire [2:0] _exe_tlb_uop_T_6_ctrl_op2_sel = _exe_tlb_uop_T_2 ? exe_req_0_bits_uop_ctrl_op2_sel : _exe_tlb_uop_T_5_ctrl_op2_sel; // @[lsu.scala:383:25, :596:24, :598:53, :600:24] wire [2:0] _exe_tlb_uop_T_6_ctrl_imm_sel = _exe_tlb_uop_T_2 ? exe_req_0_bits_uop_ctrl_imm_sel : _exe_tlb_uop_T_5_ctrl_imm_sel; // @[lsu.scala:383:25, :596:24, :598:53, :600:24] wire [4:0] _exe_tlb_uop_T_6_ctrl_op_fcn = _exe_tlb_uop_T_2 ? exe_req_0_bits_uop_ctrl_op_fcn : _exe_tlb_uop_T_5_ctrl_op_fcn; // @[lsu.scala:383:25, :596:24, :598:53, :600:24] wire _exe_tlb_uop_T_6_ctrl_fcn_dw = _exe_tlb_uop_T_2 ? exe_req_0_bits_uop_ctrl_fcn_dw : _exe_tlb_uop_T_5_ctrl_fcn_dw; // @[lsu.scala:383:25, :596:24, :598:53, :600:24] wire [2:0] _exe_tlb_uop_T_6_ctrl_csr_cmd = _exe_tlb_uop_T_2 ? exe_req_0_bits_uop_ctrl_csr_cmd : _exe_tlb_uop_T_5_ctrl_csr_cmd; // @[lsu.scala:383:25, :596:24, :598:53, :600:24] wire _exe_tlb_uop_T_6_ctrl_is_load = _exe_tlb_uop_T_2 ? exe_req_0_bits_uop_ctrl_is_load : _exe_tlb_uop_T_5_ctrl_is_load; // @[lsu.scala:383:25, :596:24, :598:53, :600:24] wire _exe_tlb_uop_T_6_ctrl_is_sta = _exe_tlb_uop_T_2 ? exe_req_0_bits_uop_ctrl_is_sta : _exe_tlb_uop_T_5_ctrl_is_sta; // @[lsu.scala:383:25, :596:24, :598:53, :600:24] wire _exe_tlb_uop_T_6_ctrl_is_std = _exe_tlb_uop_T_2 ? exe_req_0_bits_uop_ctrl_is_std : _exe_tlb_uop_T_5_ctrl_is_std; // @[lsu.scala:383:25, :596:24, :598:53, :600:24] wire [1:0] _exe_tlb_uop_T_6_iw_state = _exe_tlb_uop_T_2 ? exe_req_0_bits_uop_iw_state : _exe_tlb_uop_T_5_iw_state; // @[lsu.scala:383:25, :596:24, :598:53, :600:24] wire _exe_tlb_uop_T_6_iw_p1_poisoned = _exe_tlb_uop_T_2 ? exe_req_0_bits_uop_iw_p1_poisoned : _exe_tlb_uop_T_5_iw_p1_poisoned; // @[lsu.scala:383:25, :596:24, :598:53, :600:24] wire _exe_tlb_uop_T_6_iw_p2_poisoned = _exe_tlb_uop_T_2 ? exe_req_0_bits_uop_iw_p2_poisoned : _exe_tlb_uop_T_5_iw_p2_poisoned; // @[lsu.scala:383:25, :596:24, :598:53, :600:24] wire _exe_tlb_uop_T_6_is_br = _exe_tlb_uop_T_2 ? exe_req_0_bits_uop_is_br : _exe_tlb_uop_T_5_is_br; // @[lsu.scala:383:25, :596:24, :598:53, :600:24] wire _exe_tlb_uop_T_6_is_jalr = _exe_tlb_uop_T_2 ? exe_req_0_bits_uop_is_jalr : _exe_tlb_uop_T_5_is_jalr; // @[lsu.scala:383:25, :596:24, :598:53, :600:24] wire _exe_tlb_uop_T_6_is_jal = _exe_tlb_uop_T_2 ? exe_req_0_bits_uop_is_jal : _exe_tlb_uop_T_5_is_jal; // @[lsu.scala:383:25, :596:24, :598:53, :600:24] wire _exe_tlb_uop_T_6_is_sfb = _exe_tlb_uop_T_2 ? exe_req_0_bits_uop_is_sfb : _exe_tlb_uop_T_5_is_sfb; // @[lsu.scala:383:25, :596:24, :598:53, :600:24] wire [7:0] _exe_tlb_uop_T_6_br_mask = _exe_tlb_uop_T_2 ? exe_req_0_bits_uop_br_mask : _exe_tlb_uop_T_5_br_mask; // @[lsu.scala:383:25, :596:24, :598:53, :600:24] wire [2:0] _exe_tlb_uop_T_6_br_tag = _exe_tlb_uop_T_2 ? exe_req_0_bits_uop_br_tag : _exe_tlb_uop_T_5_br_tag; // @[lsu.scala:383:25, :596:24, :598:53, :600:24] wire [3:0] _exe_tlb_uop_T_6_ftq_idx = _exe_tlb_uop_T_2 ? exe_req_0_bits_uop_ftq_idx : _exe_tlb_uop_T_5_ftq_idx; // @[lsu.scala:383:25, :596:24, :598:53, :600:24] wire _exe_tlb_uop_T_6_edge_inst = _exe_tlb_uop_T_2 ? exe_req_0_bits_uop_edge_inst : _exe_tlb_uop_T_5_edge_inst; // @[lsu.scala:383:25, :596:24, :598:53, :600:24] wire [5:0] _exe_tlb_uop_T_6_pc_lob = _exe_tlb_uop_T_2 ? exe_req_0_bits_uop_pc_lob : _exe_tlb_uop_T_5_pc_lob; // @[lsu.scala:383:25, :596:24, :598:53, :600:24] wire _exe_tlb_uop_T_6_taken = _exe_tlb_uop_T_2 ? exe_req_0_bits_uop_taken : _exe_tlb_uop_T_5_taken; // @[lsu.scala:383:25, :596:24, :598:53, :600:24] wire [19:0] _exe_tlb_uop_T_6_imm_packed = _exe_tlb_uop_T_2 ? exe_req_0_bits_uop_imm_packed : _exe_tlb_uop_T_5_imm_packed; // @[lsu.scala:383:25, :596:24, :598:53, :600:24] wire [11:0] _exe_tlb_uop_T_6_csr_addr = _exe_tlb_uop_T_2 ? exe_req_0_bits_uop_csr_addr : _exe_tlb_uop_T_5_csr_addr; // @[lsu.scala:383:25, :596:24, :598:53, :600:24] wire [4:0] _exe_tlb_uop_T_6_rob_idx = _exe_tlb_uop_T_2 ? exe_req_0_bits_uop_rob_idx : _exe_tlb_uop_T_5_rob_idx; // @[lsu.scala:383:25, :596:24, :598:53, :600:24] wire [2:0] _exe_tlb_uop_T_6_ldq_idx = _exe_tlb_uop_T_2 ? exe_req_0_bits_uop_ldq_idx : _exe_tlb_uop_T_5_ldq_idx; // @[lsu.scala:383:25, :596:24, :598:53, :600:24] wire [2:0] _exe_tlb_uop_T_6_stq_idx = _exe_tlb_uop_T_2 ? exe_req_0_bits_uop_stq_idx : _exe_tlb_uop_T_5_stq_idx; // @[lsu.scala:383:25, :596:24, :598:53, :600:24] wire [1:0] _exe_tlb_uop_T_6_rxq_idx = _exe_tlb_uop_T_2 ? exe_req_0_bits_uop_rxq_idx : _exe_tlb_uop_T_5_rxq_idx; // @[lsu.scala:383:25, :596:24, :598:53, :600:24] wire [5:0] _exe_tlb_uop_T_6_pdst = _exe_tlb_uop_T_2 ? exe_req_0_bits_uop_pdst : _exe_tlb_uop_T_5_pdst; // @[lsu.scala:383:25, :596:24, :598:53, :600:24] wire [5:0] _exe_tlb_uop_T_6_prs1 = _exe_tlb_uop_T_2 ? exe_req_0_bits_uop_prs1 : _exe_tlb_uop_T_5_prs1; // @[lsu.scala:383:25, :596:24, :598:53, :600:24] wire [5:0] _exe_tlb_uop_T_6_prs2 = _exe_tlb_uop_T_2 ? exe_req_0_bits_uop_prs2 : _exe_tlb_uop_T_5_prs2; // @[lsu.scala:383:25, :596:24, :598:53, :600:24] wire [5:0] _exe_tlb_uop_T_6_prs3 = _exe_tlb_uop_T_2 ? exe_req_0_bits_uop_prs3 : _exe_tlb_uop_T_5_prs3; // @[lsu.scala:383:25, :596:24, :598:53, :600:24] wire [3:0] _exe_tlb_uop_T_6_ppred = _exe_tlb_uop_T_2 ? exe_req_0_bits_uop_ppred : _exe_tlb_uop_T_5_ppred; // @[lsu.scala:383:25, :596:24, :598:53, :600:24] wire _exe_tlb_uop_T_6_prs1_busy = _exe_tlb_uop_T_2 ? exe_req_0_bits_uop_prs1_busy : _exe_tlb_uop_T_5_prs1_busy; // @[lsu.scala:383:25, :596:24, :598:53, :600:24] wire _exe_tlb_uop_T_6_prs2_busy = _exe_tlb_uop_T_2 ? exe_req_0_bits_uop_prs2_busy : _exe_tlb_uop_T_5_prs2_busy; // @[lsu.scala:383:25, :596:24, :598:53, :600:24] wire _exe_tlb_uop_T_6_prs3_busy = _exe_tlb_uop_T_2 ? exe_req_0_bits_uop_prs3_busy : _exe_tlb_uop_T_5_prs3_busy; // @[lsu.scala:383:25, :596:24, :598:53, :600:24] wire _exe_tlb_uop_T_6_ppred_busy = _exe_tlb_uop_T_2 ? exe_req_0_bits_uop_ppred_busy : _exe_tlb_uop_T_5_ppred_busy; // @[lsu.scala:383:25, :596:24, :598:53, :600:24] wire [5:0] _exe_tlb_uop_T_6_stale_pdst = _exe_tlb_uop_T_2 ? exe_req_0_bits_uop_stale_pdst : _exe_tlb_uop_T_5_stale_pdst; // @[lsu.scala:383:25, :596:24, :598:53, :600:24] wire _exe_tlb_uop_T_6_exception = _exe_tlb_uop_T_2 ? exe_req_0_bits_uop_exception : _exe_tlb_uop_T_5_exception; // @[lsu.scala:383:25, :596:24, :598:53, :600:24] wire [63:0] _exe_tlb_uop_T_6_exc_cause = _exe_tlb_uop_T_2 ? exe_req_0_bits_uop_exc_cause : _exe_tlb_uop_T_5_exc_cause; // @[lsu.scala:383:25, :596:24, :598:53, :600:24] wire _exe_tlb_uop_T_6_bypassable = _exe_tlb_uop_T_2 ? exe_req_0_bits_uop_bypassable : _exe_tlb_uop_T_5_bypassable; // @[lsu.scala:383:25, :596:24, :598:53, :600:24] wire [4:0] _exe_tlb_uop_T_6_mem_cmd = _exe_tlb_uop_T_2 ? exe_req_0_bits_uop_mem_cmd : _exe_tlb_uop_T_5_mem_cmd; // @[lsu.scala:383:25, :596:24, :598:53, :600:24] wire [1:0] _exe_tlb_uop_T_6_mem_size = _exe_tlb_uop_T_2 ? exe_req_0_bits_uop_mem_size : _exe_tlb_uop_T_5_mem_size; // @[lsu.scala:383:25, :596:24, :598:53, :600:24] wire _exe_tlb_uop_T_6_mem_signed = _exe_tlb_uop_T_2 ? exe_req_0_bits_uop_mem_signed : _exe_tlb_uop_T_5_mem_signed; // @[lsu.scala:383:25, :596:24, :598:53, :600:24] wire _exe_tlb_uop_T_6_is_fence = _exe_tlb_uop_T_2 ? exe_req_0_bits_uop_is_fence : _exe_tlb_uop_T_5_is_fence; // @[lsu.scala:383:25, :596:24, :598:53, :600:24] wire _exe_tlb_uop_T_6_is_fencei = _exe_tlb_uop_T_2 ? exe_req_0_bits_uop_is_fencei : _exe_tlb_uop_T_5_is_fencei; // @[lsu.scala:383:25, :596:24, :598:53, :600:24] wire _exe_tlb_uop_T_6_is_amo = _exe_tlb_uop_T_2 ? exe_req_0_bits_uop_is_amo : _exe_tlb_uop_T_5_is_amo; // @[lsu.scala:383:25, :596:24, :598:53, :600:24] wire _exe_tlb_uop_T_6_uses_ldq = _exe_tlb_uop_T_2 ? exe_req_0_bits_uop_uses_ldq : _exe_tlb_uop_T_5_uses_ldq; // @[lsu.scala:383:25, :596:24, :598:53, :600:24] wire _exe_tlb_uop_T_6_uses_stq = _exe_tlb_uop_T_2 ? exe_req_0_bits_uop_uses_stq : _exe_tlb_uop_T_5_uses_stq; // @[lsu.scala:383:25, :596:24, :598:53, :600:24] wire _exe_tlb_uop_T_6_is_sys_pc2epc = _exe_tlb_uop_T_2 ? exe_req_0_bits_uop_is_sys_pc2epc : _exe_tlb_uop_T_5_is_sys_pc2epc; // @[lsu.scala:383:25, :596:24, :598:53, :600:24] wire _exe_tlb_uop_T_6_is_unique = _exe_tlb_uop_T_2 ? exe_req_0_bits_uop_is_unique : _exe_tlb_uop_T_5_is_unique; // @[lsu.scala:383:25, :596:24, :598:53, :600:24] wire _exe_tlb_uop_T_6_flush_on_commit = _exe_tlb_uop_T_2 ? exe_req_0_bits_uop_flush_on_commit : _exe_tlb_uop_T_5_flush_on_commit; // @[lsu.scala:383:25, :596:24, :598:53, :600:24] wire _exe_tlb_uop_T_6_ldst_is_rs1 = _exe_tlb_uop_T_2 ? exe_req_0_bits_uop_ldst_is_rs1 : _exe_tlb_uop_T_5_ldst_is_rs1; // @[lsu.scala:383:25, :596:24, :598:53, :600:24] wire [5:0] _exe_tlb_uop_T_6_ldst = _exe_tlb_uop_T_2 ? exe_req_0_bits_uop_ldst : _exe_tlb_uop_T_5_ldst; // @[lsu.scala:383:25, :596:24, :598:53, :600:24] wire [5:0] _exe_tlb_uop_T_6_lrs1 = _exe_tlb_uop_T_2 ? exe_req_0_bits_uop_lrs1 : _exe_tlb_uop_T_5_lrs1; // @[lsu.scala:383:25, :596:24, :598:53, :600:24] wire [5:0] _exe_tlb_uop_T_6_lrs2 = _exe_tlb_uop_T_2 ? exe_req_0_bits_uop_lrs2 : _exe_tlb_uop_T_5_lrs2; // @[lsu.scala:383:25, :596:24, :598:53, :600:24] wire [5:0] _exe_tlb_uop_T_6_lrs3 = _exe_tlb_uop_T_2 ? exe_req_0_bits_uop_lrs3 : _exe_tlb_uop_T_5_lrs3; // @[lsu.scala:383:25, :596:24, :598:53, :600:24] wire _exe_tlb_uop_T_6_ldst_val = _exe_tlb_uop_T_2 ? exe_req_0_bits_uop_ldst_val : _exe_tlb_uop_T_5_ldst_val; // @[lsu.scala:383:25, :596:24, :598:53, :600:24] wire [1:0] _exe_tlb_uop_T_6_dst_rtype = _exe_tlb_uop_T_2 ? exe_req_0_bits_uop_dst_rtype : _exe_tlb_uop_T_5_dst_rtype; // @[lsu.scala:383:25, :596:24, :598:53, :600:24] wire [1:0] _exe_tlb_uop_T_6_lrs1_rtype = _exe_tlb_uop_T_2 ? exe_req_0_bits_uop_lrs1_rtype : _exe_tlb_uop_T_5_lrs1_rtype; // @[lsu.scala:383:25, :596:24, :598:53, :600:24] wire [1:0] _exe_tlb_uop_T_6_lrs2_rtype = _exe_tlb_uop_T_2 ? exe_req_0_bits_uop_lrs2_rtype : _exe_tlb_uop_T_5_lrs2_rtype; // @[lsu.scala:383:25, :596:24, :598:53, :600:24] wire _exe_tlb_uop_T_6_frs3_en = _exe_tlb_uop_T_2 ? exe_req_0_bits_uop_frs3_en : _exe_tlb_uop_T_5_frs3_en; // @[lsu.scala:383:25, :596:24, :598:53, :600:24] wire _exe_tlb_uop_T_6_fp_val = _exe_tlb_uop_T_2 ? exe_req_0_bits_uop_fp_val : _exe_tlb_uop_T_5_fp_val; // @[lsu.scala:383:25, :596:24, :598:53, :600:24] wire _exe_tlb_uop_T_6_fp_single = _exe_tlb_uop_T_2 ? exe_req_0_bits_uop_fp_single : _exe_tlb_uop_T_5_fp_single; // @[lsu.scala:383:25, :596:24, :598:53, :600:24] wire _exe_tlb_uop_T_6_xcpt_pf_if = _exe_tlb_uop_T_2 ? exe_req_0_bits_uop_xcpt_pf_if : _exe_tlb_uop_T_5_xcpt_pf_if; // @[lsu.scala:383:25, :596:24, :598:53, :600:24] wire _exe_tlb_uop_T_6_xcpt_ae_if = _exe_tlb_uop_T_2 ? exe_req_0_bits_uop_xcpt_ae_if : _exe_tlb_uop_T_5_xcpt_ae_if; // @[lsu.scala:383:25, :596:24, :598:53, :600:24] wire _exe_tlb_uop_T_6_xcpt_ma_if = _exe_tlb_uop_T_2 ? exe_req_0_bits_uop_xcpt_ma_if : _exe_tlb_uop_T_5_xcpt_ma_if; // @[lsu.scala:383:25, :596:24, :598:53, :600:24] wire _exe_tlb_uop_T_6_bp_debug_if = _exe_tlb_uop_T_2 ? exe_req_0_bits_uop_bp_debug_if : _exe_tlb_uop_T_5_bp_debug_if; // @[lsu.scala:383:25, :596:24, :598:53, :600:24] wire _exe_tlb_uop_T_6_bp_xcpt_if = _exe_tlb_uop_T_2 ? exe_req_0_bits_uop_bp_xcpt_if : _exe_tlb_uop_T_5_bp_xcpt_if; // @[lsu.scala:383:25, :596:24, :598:53, :600:24] wire [1:0] _exe_tlb_uop_T_6_debug_fsrc = _exe_tlb_uop_T_2 ? exe_req_0_bits_uop_debug_fsrc : _exe_tlb_uop_T_5_debug_fsrc; // @[lsu.scala:383:25, :596:24, :598:53, :600:24] wire [1:0] _exe_tlb_uop_T_6_debug_tsrc = _exe_tlb_uop_T_2 ? exe_req_0_bits_uop_debug_tsrc : _exe_tlb_uop_T_5_debug_tsrc; // @[lsu.scala:383:25, :596:24, :598:53, :600:24] wire [6:0] exe_tlb_uop_0_uopc = _exe_tlb_uop_T_6_uopc; // @[lsu.scala:263:49, :596:24] wire [31:0] exe_tlb_uop_0_inst = _exe_tlb_uop_T_6_inst; // @[lsu.scala:263:49, :596:24] wire [31:0] exe_tlb_uop_0_debug_inst = _exe_tlb_uop_T_6_debug_inst; // @[lsu.scala:263:49, :596:24] wire exe_tlb_uop_0_is_rvc = _exe_tlb_uop_T_6_is_rvc; // @[lsu.scala:263:49, :596:24] wire [39:0] exe_tlb_uop_0_debug_pc = _exe_tlb_uop_T_6_debug_pc; // @[lsu.scala:263:49, :596:24] wire [2:0] exe_tlb_uop_0_iq_type = _exe_tlb_uop_T_6_iq_type; // @[lsu.scala:263:49, :596:24] wire [9:0] exe_tlb_uop_0_fu_code = _exe_tlb_uop_T_6_fu_code; // @[lsu.scala:263:49, :596:24] wire [3:0] exe_tlb_uop_0_ctrl_br_type = _exe_tlb_uop_T_6_ctrl_br_type; // @[lsu.scala:263:49, :596:24] wire [1:0] exe_tlb_uop_0_ctrl_op1_sel = _exe_tlb_uop_T_6_ctrl_op1_sel; // @[lsu.scala:263:49, :596:24] wire [2:0] exe_tlb_uop_0_ctrl_op2_sel = _exe_tlb_uop_T_6_ctrl_op2_sel; // @[lsu.scala:263:49, :596:24] wire [2:0] exe_tlb_uop_0_ctrl_imm_sel = _exe_tlb_uop_T_6_ctrl_imm_sel; // @[lsu.scala:263:49, :596:24] wire [4:0] exe_tlb_uop_0_ctrl_op_fcn = _exe_tlb_uop_T_6_ctrl_op_fcn; // @[lsu.scala:263:49, :596:24] wire exe_tlb_uop_0_ctrl_fcn_dw = _exe_tlb_uop_T_6_ctrl_fcn_dw; // @[lsu.scala:263:49, :596:24] wire [2:0] exe_tlb_uop_0_ctrl_csr_cmd = _exe_tlb_uop_T_6_ctrl_csr_cmd; // @[lsu.scala:263:49, :596:24] wire exe_tlb_uop_0_ctrl_is_load = _exe_tlb_uop_T_6_ctrl_is_load; // @[lsu.scala:263:49, :596:24] wire exe_tlb_uop_0_ctrl_is_sta = _exe_tlb_uop_T_6_ctrl_is_sta; // @[lsu.scala:263:49, :596:24] wire exe_tlb_uop_0_ctrl_is_std = _exe_tlb_uop_T_6_ctrl_is_std; // @[lsu.scala:263:49, :596:24] wire [1:0] exe_tlb_uop_0_iw_state = _exe_tlb_uop_T_6_iw_state; // @[lsu.scala:263:49, :596:24] wire exe_tlb_uop_0_iw_p1_poisoned = _exe_tlb_uop_T_6_iw_p1_poisoned; // @[lsu.scala:263:49, :596:24] wire exe_tlb_uop_0_iw_p2_poisoned = _exe_tlb_uop_T_6_iw_p2_poisoned; // @[lsu.scala:263:49, :596:24] wire exe_tlb_uop_0_is_br = _exe_tlb_uop_T_6_is_br; // @[lsu.scala:263:49, :596:24] wire exe_tlb_uop_0_is_jalr = _exe_tlb_uop_T_6_is_jalr; // @[lsu.scala:263:49, :596:24] wire exe_tlb_uop_0_is_jal = _exe_tlb_uop_T_6_is_jal; // @[lsu.scala:263:49, :596:24] wire exe_tlb_uop_0_is_sfb = _exe_tlb_uop_T_6_is_sfb; // @[lsu.scala:263:49, :596:24] wire [7:0] exe_tlb_uop_0_br_mask = _exe_tlb_uop_T_6_br_mask; // @[lsu.scala:263:49, :596:24] wire [2:0] exe_tlb_uop_0_br_tag = _exe_tlb_uop_T_6_br_tag; // @[lsu.scala:263:49, :596:24] wire [3:0] exe_tlb_uop_0_ftq_idx = _exe_tlb_uop_T_6_ftq_idx; // @[lsu.scala:263:49, :596:24] wire exe_tlb_uop_0_edge_inst = _exe_tlb_uop_T_6_edge_inst; // @[lsu.scala:263:49, :596:24] wire [5:0] exe_tlb_uop_0_pc_lob = _exe_tlb_uop_T_6_pc_lob; // @[lsu.scala:263:49, :596:24] wire exe_tlb_uop_0_taken = _exe_tlb_uop_T_6_taken; // @[lsu.scala:263:49, :596:24] wire [19:0] exe_tlb_uop_0_imm_packed = _exe_tlb_uop_T_6_imm_packed; // @[lsu.scala:263:49, :596:24] wire [11:0] exe_tlb_uop_0_csr_addr = _exe_tlb_uop_T_6_csr_addr; // @[lsu.scala:263:49, :596:24] wire [4:0] exe_tlb_uop_0_rob_idx = _exe_tlb_uop_T_6_rob_idx; // @[lsu.scala:263:49, :596:24] wire [2:0] exe_tlb_uop_0_ldq_idx = _exe_tlb_uop_T_6_ldq_idx; // @[lsu.scala:263:49, :596:24] wire [2:0] exe_tlb_uop_0_stq_idx = _exe_tlb_uop_T_6_stq_idx; // @[lsu.scala:263:49, :596:24] wire [1:0] exe_tlb_uop_0_rxq_idx = _exe_tlb_uop_T_6_rxq_idx; // @[lsu.scala:263:49, :596:24] wire [5:0] exe_tlb_uop_0_pdst = _exe_tlb_uop_T_6_pdst; // @[lsu.scala:263:49, :596:24] wire [5:0] exe_tlb_uop_0_prs1 = _exe_tlb_uop_T_6_prs1; // @[lsu.scala:263:49, :596:24] wire [5:0] exe_tlb_uop_0_prs2 = _exe_tlb_uop_T_6_prs2; // @[lsu.scala:263:49, :596:24] wire [5:0] exe_tlb_uop_0_prs3 = _exe_tlb_uop_T_6_prs3; // @[lsu.scala:263:49, :596:24] wire [3:0] exe_tlb_uop_0_ppred = _exe_tlb_uop_T_6_ppred; // @[lsu.scala:263:49, :596:24] wire exe_tlb_uop_0_prs1_busy = _exe_tlb_uop_T_6_prs1_busy; // @[lsu.scala:263:49, :596:24] wire exe_tlb_uop_0_prs2_busy = _exe_tlb_uop_T_6_prs2_busy; // @[lsu.scala:263:49, :596:24] wire exe_tlb_uop_0_prs3_busy = _exe_tlb_uop_T_6_prs3_busy; // @[lsu.scala:263:49, :596:24] wire exe_tlb_uop_0_ppred_busy = _exe_tlb_uop_T_6_ppred_busy; // @[lsu.scala:263:49, :596:24] wire [5:0] exe_tlb_uop_0_stale_pdst = _exe_tlb_uop_T_6_stale_pdst; // @[lsu.scala:263:49, :596:24] wire exe_tlb_uop_0_exception = _exe_tlb_uop_T_6_exception; // @[lsu.scala:263:49, :596:24] wire [63:0] exe_tlb_uop_0_exc_cause = _exe_tlb_uop_T_6_exc_cause; // @[lsu.scala:263:49, :596:24] wire exe_tlb_uop_0_bypassable = _exe_tlb_uop_T_6_bypassable; // @[lsu.scala:263:49, :596:24] wire [4:0] exe_tlb_uop_0_mem_cmd = _exe_tlb_uop_T_6_mem_cmd; // @[lsu.scala:263:49, :596:24] wire [1:0] exe_tlb_uop_0_mem_size = _exe_tlb_uop_T_6_mem_size; // @[lsu.scala:263:49, :596:24] wire exe_tlb_uop_0_mem_signed = _exe_tlb_uop_T_6_mem_signed; // @[lsu.scala:263:49, :596:24] wire exe_tlb_uop_0_is_fence = _exe_tlb_uop_T_6_is_fence; // @[lsu.scala:263:49, :596:24] wire exe_tlb_uop_0_is_fencei = _exe_tlb_uop_T_6_is_fencei; // @[lsu.scala:263:49, :596:24] wire exe_tlb_uop_0_is_amo = _exe_tlb_uop_T_6_is_amo; // @[lsu.scala:263:49, :596:24] wire exe_tlb_uop_0_uses_ldq = _exe_tlb_uop_T_6_uses_ldq; // @[lsu.scala:263:49, :596:24] wire exe_tlb_uop_0_uses_stq = _exe_tlb_uop_T_6_uses_stq; // @[lsu.scala:263:49, :596:24] wire exe_tlb_uop_0_is_sys_pc2epc = _exe_tlb_uop_T_6_is_sys_pc2epc; // @[lsu.scala:263:49, :596:24] wire exe_tlb_uop_0_is_unique = _exe_tlb_uop_T_6_is_unique; // @[lsu.scala:263:49, :596:24] wire exe_tlb_uop_0_flush_on_commit = _exe_tlb_uop_T_6_flush_on_commit; // @[lsu.scala:263:49, :596:24] wire exe_tlb_uop_0_ldst_is_rs1 = _exe_tlb_uop_T_6_ldst_is_rs1; // @[lsu.scala:263:49, :596:24] wire [5:0] exe_tlb_uop_0_ldst = _exe_tlb_uop_T_6_ldst; // @[lsu.scala:263:49, :596:24] wire [5:0] exe_tlb_uop_0_lrs1 = _exe_tlb_uop_T_6_lrs1; // @[lsu.scala:263:49, :596:24] wire [5:0] exe_tlb_uop_0_lrs2 = _exe_tlb_uop_T_6_lrs2; // @[lsu.scala:263:49, :596:24] wire [5:0] exe_tlb_uop_0_lrs3 = _exe_tlb_uop_T_6_lrs3; // @[lsu.scala:263:49, :596:24] wire exe_tlb_uop_0_ldst_val = _exe_tlb_uop_T_6_ldst_val; // @[lsu.scala:263:49, :596:24] wire [1:0] exe_tlb_uop_0_dst_rtype = _exe_tlb_uop_T_6_dst_rtype; // @[lsu.scala:263:49, :596:24] wire [1:0] exe_tlb_uop_0_lrs1_rtype = _exe_tlb_uop_T_6_lrs1_rtype; // @[lsu.scala:263:49, :596:24] wire [1:0] exe_tlb_uop_0_lrs2_rtype = _exe_tlb_uop_T_6_lrs2_rtype; // @[lsu.scala:263:49, :596:24] wire exe_tlb_uop_0_frs3_en = _exe_tlb_uop_T_6_frs3_en; // @[lsu.scala:263:49, :596:24] wire exe_tlb_uop_0_fp_val = _exe_tlb_uop_T_6_fp_val; // @[lsu.scala:263:49, :596:24] wire exe_tlb_uop_0_fp_single = _exe_tlb_uop_T_6_fp_single; // @[lsu.scala:263:49, :596:24] wire exe_tlb_uop_0_xcpt_pf_if = _exe_tlb_uop_T_6_xcpt_pf_if; // @[lsu.scala:263:49, :596:24] wire exe_tlb_uop_0_xcpt_ae_if = _exe_tlb_uop_T_6_xcpt_ae_if; // @[lsu.scala:263:49, :596:24] wire exe_tlb_uop_0_xcpt_ma_if = _exe_tlb_uop_T_6_xcpt_ma_if; // @[lsu.scala:263:49, :596:24] wire exe_tlb_uop_0_bp_debug_if = _exe_tlb_uop_T_6_bp_debug_if; // @[lsu.scala:263:49, :596:24] wire exe_tlb_uop_0_bp_xcpt_if = _exe_tlb_uop_T_6_bp_xcpt_if; // @[lsu.scala:263:49, :596:24] wire [1:0] exe_tlb_uop_0_debug_fsrc = _exe_tlb_uop_T_6_debug_fsrc; // @[lsu.scala:263:49, :596:24] wire [1:0] exe_tlb_uop_0_debug_tsrc = _exe_tlb_uop_T_6_debug_tsrc; // @[lsu.scala:263:49, :596:24] wire [6:0] mem_xcpt_uops_out_uopc = exe_tlb_uop_0_uopc; // @[util.scala:96:23] wire [31:0] mem_xcpt_uops_out_inst = exe_tlb_uop_0_inst; // @[util.scala:96:23] wire [31:0] mem_xcpt_uops_out_debug_inst = exe_tlb_uop_0_debug_inst; // @[util.scala:96:23] wire mem_xcpt_uops_out_is_rvc = exe_tlb_uop_0_is_rvc; // @[util.scala:96:23] wire [39:0] mem_xcpt_uops_out_debug_pc = exe_tlb_uop_0_debug_pc; // @[util.scala:96:23] wire [2:0] mem_xcpt_uops_out_iq_type = exe_tlb_uop_0_iq_type; // @[util.scala:96:23] wire [9:0] mem_xcpt_uops_out_fu_code = exe_tlb_uop_0_fu_code; // @[util.scala:96:23] wire [3:0] mem_xcpt_uops_out_ctrl_br_type = exe_tlb_uop_0_ctrl_br_type; // @[util.scala:96:23] wire [1:0] mem_xcpt_uops_out_ctrl_op1_sel = exe_tlb_uop_0_ctrl_op1_sel; // @[util.scala:96:23] wire [2:0] mem_xcpt_uops_out_ctrl_op2_sel = exe_tlb_uop_0_ctrl_op2_sel; // @[util.scala:96:23] wire [2:0] mem_xcpt_uops_out_ctrl_imm_sel = exe_tlb_uop_0_ctrl_imm_sel; // @[util.scala:96:23] wire [4:0] mem_xcpt_uops_out_ctrl_op_fcn = exe_tlb_uop_0_ctrl_op_fcn; // @[util.scala:96:23] wire mem_xcpt_uops_out_ctrl_fcn_dw = exe_tlb_uop_0_ctrl_fcn_dw; // @[util.scala:96:23] wire [2:0] mem_xcpt_uops_out_ctrl_csr_cmd = exe_tlb_uop_0_ctrl_csr_cmd; // @[util.scala:96:23] wire mem_xcpt_uops_out_ctrl_is_load = exe_tlb_uop_0_ctrl_is_load; // @[util.scala:96:23] wire mem_xcpt_uops_out_ctrl_is_sta = exe_tlb_uop_0_ctrl_is_sta; // @[util.scala:96:23] wire mem_xcpt_uops_out_ctrl_is_std = exe_tlb_uop_0_ctrl_is_std; // @[util.scala:96:23] wire [1:0] mem_xcpt_uops_out_iw_state = exe_tlb_uop_0_iw_state; // @[util.scala:96:23] wire mem_xcpt_uops_out_iw_p1_poisoned = exe_tlb_uop_0_iw_p1_poisoned; // @[util.scala:96:23] wire mem_xcpt_uops_out_iw_p2_poisoned = exe_tlb_uop_0_iw_p2_poisoned; // @[util.scala:96:23] wire mem_xcpt_uops_out_is_br = exe_tlb_uop_0_is_br; // @[util.scala:96:23] wire mem_xcpt_uops_out_is_jalr = exe_tlb_uop_0_is_jalr; // @[util.scala:96:23] wire mem_xcpt_uops_out_is_jal = exe_tlb_uop_0_is_jal; // @[util.scala:96:23] wire mem_xcpt_uops_out_is_sfb = exe_tlb_uop_0_is_sfb; // @[util.scala:96:23] wire [2:0] mem_xcpt_uops_out_br_tag = exe_tlb_uop_0_br_tag; // @[util.scala:96:23] wire [3:0] mem_xcpt_uops_out_ftq_idx = exe_tlb_uop_0_ftq_idx; // @[util.scala:96:23] wire mem_xcpt_uops_out_edge_inst = exe_tlb_uop_0_edge_inst; // @[util.scala:96:23] wire [5:0] mem_xcpt_uops_out_pc_lob = exe_tlb_uop_0_pc_lob; // @[util.scala:96:23] wire mem_xcpt_uops_out_taken = exe_tlb_uop_0_taken; // @[util.scala:96:23] wire [19:0] mem_xcpt_uops_out_imm_packed = exe_tlb_uop_0_imm_packed; // @[util.scala:96:23] wire [11:0] mem_xcpt_uops_out_csr_addr = exe_tlb_uop_0_csr_addr; // @[util.scala:96:23] wire [4:0] mem_xcpt_uops_out_rob_idx = exe_tlb_uop_0_rob_idx; // @[util.scala:96:23] wire [2:0] mem_xcpt_uops_out_ldq_idx = exe_tlb_uop_0_ldq_idx; // @[util.scala:96:23] wire [2:0] mem_xcpt_uops_out_stq_idx = exe_tlb_uop_0_stq_idx; // @[util.scala:96:23] wire [1:0] mem_xcpt_uops_out_rxq_idx = exe_tlb_uop_0_rxq_idx; // @[util.scala:96:23] wire [5:0] mem_xcpt_uops_out_pdst = exe_tlb_uop_0_pdst; // @[util.scala:96:23] wire [5:0] mem_xcpt_uops_out_prs1 = exe_tlb_uop_0_prs1; // @[util.scala:96:23] wire [5:0] mem_xcpt_uops_out_prs2 = exe_tlb_uop_0_prs2; // @[util.scala:96:23] wire [5:0] mem_xcpt_uops_out_prs3 = exe_tlb_uop_0_prs3; // @[util.scala:96:23] wire [3:0] mem_xcpt_uops_out_ppred = exe_tlb_uop_0_ppred; // @[util.scala:96:23] wire mem_xcpt_uops_out_prs1_busy = exe_tlb_uop_0_prs1_busy; // @[util.scala:96:23] wire mem_xcpt_uops_out_prs2_busy = exe_tlb_uop_0_prs2_busy; // @[util.scala:96:23] wire mem_xcpt_uops_out_prs3_busy = exe_tlb_uop_0_prs3_busy; // @[util.scala:96:23] wire mem_xcpt_uops_out_ppred_busy = exe_tlb_uop_0_ppred_busy; // @[util.scala:96:23] wire [5:0] mem_xcpt_uops_out_stale_pdst = exe_tlb_uop_0_stale_pdst; // @[util.scala:96:23] wire mem_xcpt_uops_out_exception = exe_tlb_uop_0_exception; // @[util.scala:96:23] wire [63:0] mem_xcpt_uops_out_exc_cause = exe_tlb_uop_0_exc_cause; // @[util.scala:96:23] wire mem_xcpt_uops_out_bypassable = exe_tlb_uop_0_bypassable; // @[util.scala:96:23] wire [4:0] mem_xcpt_uops_out_mem_cmd = exe_tlb_uop_0_mem_cmd; // @[util.scala:96:23] wire [1:0] mem_xcpt_uops_out_mem_size = exe_tlb_uop_0_mem_size; // @[util.scala:96:23] wire mem_xcpt_uops_out_mem_signed = exe_tlb_uop_0_mem_signed; // @[util.scala:96:23] wire mem_xcpt_uops_out_is_fence = exe_tlb_uop_0_is_fence; // @[util.scala:96:23] wire mem_xcpt_uops_out_is_fencei = exe_tlb_uop_0_is_fencei; // @[util.scala:96:23] wire mem_xcpt_uops_out_is_amo = exe_tlb_uop_0_is_amo; // @[util.scala:96:23] wire mem_xcpt_uops_out_uses_ldq = exe_tlb_uop_0_uses_ldq; // @[util.scala:96:23] wire mem_xcpt_uops_out_uses_stq = exe_tlb_uop_0_uses_stq; // @[util.scala:96:23] wire mem_xcpt_uops_out_is_sys_pc2epc = exe_tlb_uop_0_is_sys_pc2epc; // @[util.scala:96:23] wire mem_xcpt_uops_out_is_unique = exe_tlb_uop_0_is_unique; // @[util.scala:96:23] wire mem_xcpt_uops_out_flush_on_commit = exe_tlb_uop_0_flush_on_commit; // @[util.scala:96:23] wire mem_xcpt_uops_out_ldst_is_rs1 = exe_tlb_uop_0_ldst_is_rs1; // @[util.scala:96:23] wire [5:0] mem_xcpt_uops_out_ldst = exe_tlb_uop_0_ldst; // @[util.scala:96:23] wire [5:0] mem_xcpt_uops_out_lrs1 = exe_tlb_uop_0_lrs1; // @[util.scala:96:23] wire [5:0] mem_xcpt_uops_out_lrs2 = exe_tlb_uop_0_lrs2; // @[util.scala:96:23] wire [5:0] mem_xcpt_uops_out_lrs3 = exe_tlb_uop_0_lrs3; // @[util.scala:96:23] wire mem_xcpt_uops_out_ldst_val = exe_tlb_uop_0_ldst_val; // @[util.scala:96:23] wire [1:0] mem_xcpt_uops_out_dst_rtype = exe_tlb_uop_0_dst_rtype; // @[util.scala:96:23] wire [1:0] mem_xcpt_uops_out_lrs1_rtype = exe_tlb_uop_0_lrs1_rtype; // @[util.scala:96:23] wire [1:0] mem_xcpt_uops_out_lrs2_rtype = exe_tlb_uop_0_lrs2_rtype; // @[util.scala:96:23] wire mem_xcpt_uops_out_frs3_en = exe_tlb_uop_0_frs3_en; // @[util.scala:96:23] wire mem_xcpt_uops_out_fp_val = exe_tlb_uop_0_fp_val; // @[util.scala:96:23] wire mem_xcpt_uops_out_fp_single = exe_tlb_uop_0_fp_single; // @[util.scala:96:23] wire mem_xcpt_uops_out_xcpt_pf_if = exe_tlb_uop_0_xcpt_pf_if; // @[util.scala:96:23] wire mem_xcpt_uops_out_xcpt_ae_if = exe_tlb_uop_0_xcpt_ae_if; // @[util.scala:96:23] wire mem_xcpt_uops_out_xcpt_ma_if = exe_tlb_uop_0_xcpt_ma_if; // @[util.scala:96:23] wire mem_xcpt_uops_out_bp_debug_if = exe_tlb_uop_0_bp_debug_if; // @[util.scala:96:23] wire mem_xcpt_uops_out_bp_xcpt_if = exe_tlb_uop_0_bp_xcpt_if; // @[util.scala:96:23] wire [1:0] mem_xcpt_uops_out_debug_fsrc = exe_tlb_uop_0_debug_fsrc; // @[util.scala:96:23] wire [1:0] mem_xcpt_uops_out_debug_tsrc = exe_tlb_uop_0_debug_tsrc; // @[util.scala:96:23] wire _exe_tlb_vaddr_T_1 = _exe_tlb_vaddr_T \| will_fire_sta_incoming_0; // @[lsu.scala:372:38, :606:53, :607:53] wire [39:0] _exe_tlb_vaddr_T_2 = will_fire_hella_incoming_0 ? hella_req_addr : 40'h0; // @[lsu.scala:241:34, :375:38, :612:24] wire [39:0] _exe_tlb_vaddr_T_3 = will_fire_sta_retry_0 ? mem_stq_retry_e_out_bits_addr_bits : _exe_tlb_vaddr_T_2; // @[util.scala:106:23] wire [39:0] _exe_tlb_vaddr_T_4 = will_fire_load_retry_0 ? mem_ldq_retry_e_out_bits_addr_bits : _exe_tlb_vaddr_T_3; // @[util.scala:106:23] wire [39:0] _exe_tlb_vaddr_T_5 = will_fire_sfence_0 ? {1'h0, exe_req_0_bits_sfence_bits_addr} : _exe_tlb_vaddr_T_4; // @[lsu.scala:374:38, :383:25, :609:24, :610:24] wire [39:0] _exe_tlb_vaddr_T_6 = _exe_tlb_vaddr_T_1 ? exe_req_0_bits_addr : _exe_tlb_vaddr_T_5; // @[lsu.scala:383:25, :606:24, :607:53, :609:24] wire [39:0] exe_tlb_vaddr_0 = _exe_tlb_vaddr_T_6; // @[lsu.scala:263:49, :606:24] wire exe_sfence_bits_rs1; // @[lsu.scala:615:28] wire exe_sfence_bits_rs2; // @[lsu.scala:615:28] wire [38:0] exe_sfence_bits_addr; // @[lsu.scala:615:28] wire exe_sfence_bits_asid; // @[lsu.scala:615:28] wire exe_sfence_valid; // @[lsu.scala:615:28] assign exe_sfence_valid = will_fire_sfence_0 & exe_req_0_bits_sfence_valid; // @[lsu.scala:374:38, :383:25, :615:28, :617:32, :618:18] assign exe_sfence_bits_rs1 = will_fire_sfence_0 & exe_req_0_bits_sfence_bits_rs1; // @[lsu.scala:374:38, :383:25, :615:28, :617:32, :618:18] assign exe_sfence_bits_rs2 = will_fire_sfence_0 & exe_req_0_bits_sfence_bits_rs2; // @[lsu.scala:374:38, :383:25, :615:28, :617:32, :618:18] assign exe_sfence_bits_addr = will_fire_sfence_0 ? exe_req_0_bits_sfence_bits_addr : 39'h0; // @[lsu.scala:374:38, :383:25, :615:28, :617:32, :618:18] assign exe_sfence_bits_asid = will_fire_sfence_0 & exe_req_0_bits_sfence_bits_asid; // @[lsu.scala:374:38, :383:25, :615:28, :617:32, :618:18] wire _exe_size_T_1 = _exe_size_T \| will_fire_sta_incoming_0; // @[lsu.scala:372:38, :623:52, :624:52] wire _exe_size_T_2 = _exe_size_T_1 \| will_fire_sfence_0; // @[lsu.scala:374:38, :624:52, :625:52] wire _exe_size_T_3 = _exe_size_T_2 \| will_fire_load_retry_0; // @[lsu.scala:378:38, :625:52, :626:52] wire _exe_size_T_4 = _exe_size_T_3 \| will_fire_sta_retry_0; // @[lsu.scala:379:38, :626:52, :627:52] wire [1:0] _exe_size_T_5 = {2{will_fire_hella_incoming_0}}; // @[lsu.scala:375:38, :629:23] wire [1:0] _exe_size_T_6 = _exe_size_T_4 ? exe_tlb_uop_0_mem_size : _exe_size_T_5; // @[lsu.scala:263:49, :623:23, :627:52, :629:23] wire [1:0] exe_size_0 = _exe_size_T_6; // @[lsu.scala:263:49, :623:23] wire _exe_cmd_T_1 = _exe_cmd_T \| will_fire_sta_incoming_0; // @[lsu.scala:372:38, :632:52, :633:52] wire _exe_cmd_T_2 = _exe_cmd_T_1 \| will_fire_sfence_0; // @[lsu.scala:374:38, :633:52, :634:52] wire _exe_cmd_T_3 = _exe_cmd_T_2 \| will_fire_load_retry_0; // @[lsu.scala:378:38, :634:52, :635:52] wire _exe_cmd_T_4 = _exe_cmd_T_3 \| will_fire_sta_retry_0; // @[lsu.scala:379:38, :635:52, :636:52] wire [4:0] _exe_cmd_T_6 = _exe_cmd_T_4 ? exe_tlb_uop_0_mem_cmd : 5'h0; // @[lsu.scala:263:49, :632:23, :636:52] wire [4:0] exe_cmd_0 = _exe_cmd_T_6; // @[lsu.scala:263:49, :632:23] wire exe_passthr_0 = _exe_passthr_T; // @[lsu.scala:263:49, :642:23] wire _exe_kill_T = will_fire_hella_incoming_0 & io_hellacache_s1_kill_0; // @[lsu.scala:201:7, :375:38, :645:23] wire exe_kill_0 = _exe_kill_T; // @[lsu.scala:263:49, :645:23] wire _ma_ld_T = will_fire_load_incoming_0 & exe_req_0_bits_mxcpt_valid; // @[lsu.scala:370:38, :383:25, :660:56] wire ma_ld_0 = _ma_ld_T; // @[lsu.scala:263:49, :660:56] wire _T_162 = will_fire_sta_incoming_0 \| will_fire_stad_incoming_0; // @[lsu.scala:371:38, :372:38, :661:56] wire _ma_st_T; // @[lsu.scala:661:56] assign _ma_st_T = _T_162; // @[lsu.scala:661:56] wire _stq_idx_T; // @[lsu.scala:851:51] assign _stq_idx_T = _T_162; // @[lsu.scala:661:56, :851:51] wire _ma_st_T_1 = _ma_st_T & exe_req_0_bits_mxcpt_valid; // @[lsu.scala:383:25, :661:{56,87}] wire ma_st_0 = _ma_st_T_1; // @[lsu.scala:263:49, :661:87] wire _pf_ld_T = exe_tlb_valid_0 & _dtlb_io_resp_0_pf_ld; // @[lsu.scala:247:20, :525:27, :662:50] wire _pf_ld_T_1 = _pf_ld_T & exe_tlb_uop_0_uses_ldq; // @[lsu.scala:263:49, :662:{50,75}] wire pf_ld_0 = _pf_ld_T_1; // @[lsu.scala:263:49, :662:75] wire _pf_st_T = exe_tlb_valid_0 & _dtlb_io_resp_0_pf_st; // @[lsu.scala:247:20, :525:27, :663:50] wire _pf_st_T_1 = _pf_st_T & exe_tlb_uop_0_uses_stq; // @[lsu.scala:263:49, :663:{50,75}] wire pf_st_0 = _pf_st_T_1; // @[lsu.scala:263:49, :663:75] wire _ae_ld_T = exe_tlb_valid_0 & _dtlb_io_resp_0_ae_ld; // @[lsu.scala:247:20, :525:27, :664:50] wire _ae_ld_T_1 = _ae_ld_T & exe_tlb_uop_0_uses_ldq; // @[lsu.scala:263:49, :664:{50,75}] wire ae_ld_0 = _ae_ld_T_1; // @[lsu.scala:263:49, :664:75] wire _ae_st_T = exe_tlb_valid_0 & _dtlb_io_resp_0_ae_st; // @[lsu.scala:247:20, :525:27, :665:50] wire _ae_st_T_1 = _ae_st_T & exe_tlb_uop_0_uses_stq; // @[lsu.scala:263:49, :665:{50,75}] wire ae_st_0 = _ae_st_T_1; // @[lsu.scala:263:49, :665:75] wire _mem_xcpt_valids_T = pf_ld_0 \| pf_st_0; // @[lsu.scala:263:49, :669:32] wire _mem_xcpt_valids_T_1 = _mem_xcpt_valids_T \| ae_ld_0; // @[lsu.scala:263:49, :669:{32,44}] wire _mem_xcpt_valids_T_2 = _mem_xcpt_valids_T_1 \| ae_st_0; // @[lsu.scala:263:49, :669:{44,56}] wire _mem_xcpt_valids_T_3 = _mem_xcpt_valids_T_2 \| ma_ld_0; // @[lsu.scala:263:49, :669:{56,68}] wire _mem_xcpt_valids_T_4 = _mem_xcpt_valids_T_3 \| ma_st_0; // @[lsu.scala:263:49, :669:{68,80}] wire _mem_xcpt_valids_T_5 = ~io_core_exception_0; // @[lsu.scala:201:7, :670:22] wire _mem_xcpt_valids_T_6 = _mem_xcpt_valids_T_4 & _mem_xcpt_valids_T_5; // @[lsu.scala:669:{80,93}, :670:22] wire [7:0] _mem_xcpt_valids_T_7 = io_core_brupdate_b1_mispredict_mask_0 & exe_tlb_uop_0_br_mask; // @[util.scala:118:51] wire _mem_xcpt_valids_T_8 = \|_mem_xcpt_valids_T_7; // @[util.scala:118:{51,59}] wire _mem_xcpt_valids_T_9 = ~_mem_xcpt_valids_T_8; // @[util.scala:118:59] wire _mem_xcpt_valids_T_10 = _mem_xcpt_valids_T_6 & _mem_xcpt_valids_T_9; // @[lsu.scala:669:93, :670:41, :671:22] wire _mem_xcpt_valids_WIRE_0 = _mem_xcpt_valids_T_10; // @[lsu.scala:263:49, :670:41] reg mem_xcpt_valids_0; // @[lsu.scala:668:32] assign mem_xcpt_valid = mem_xcpt_valids_0; // @[lsu.scala:358:29, :668:32] wire [6:0] _mem_xcpt_uops_WIRE_0_uopc = mem_xcpt_uops_out_uopc; // @[util.scala:96:23] wire [31:0] _mem_xcpt_uops_WIRE_0_inst = mem_xcpt_uops_out_inst; // @[util.scala:96:23] wire [31:0] _mem_xcpt_uops_WIRE_0_debug_inst = mem_xcpt_uops_out_debug_inst; // @[util.scala:96:23] wire _mem_xcpt_uops_WIRE_0_is_rvc = mem_xcpt_uops_out_is_rvc; // @[util.scala:96:23] wire [39:0] _mem_xcpt_uops_WIRE_0_debug_pc = mem_xcpt_uops_out_debug_pc; // @[util.scala:96:23] wire [2:0] _mem_xcpt_uops_WIRE_0_iq_type = mem_xcpt_uops_out_iq_type; // @[util.scala:96:23] wire [9:0] _mem_xcpt_uops_WIRE_0_fu_code = mem_xcpt_uops_out_fu_code; // @[util.scala:96:23] wire [3:0] _mem_xcpt_uops_WIRE_0_ctrl_br_type = mem_xcpt_uops_out_ctrl_br_type; // @[util.scala:96:23] wire [1:0] _mem_xcpt_uops_WIRE_0_ctrl_op1_sel = mem_xcpt_uops_out_ctrl_op1_sel; // @[util.scala:96:23] wire [2:0] _mem_xcpt_uops_WIRE_0_ctrl_op2_sel = mem_xcpt_uops_out_ctrl_op2_sel; // @[util.scala:96:23] wire [2:0] _mem_xcpt_uops_WIRE_0_ctrl_imm_sel = mem_xcpt_uops_out_ctrl_imm_sel; // @[util.scala:96:23] wire [4:0] _mem_xcpt_uops_WIRE_0_ctrl_op_fcn = mem_xcpt_uops_out_ctrl_op_fcn; // @[util.scala:96:23] wire _mem_xcpt_uops_WIRE_0_ctrl_fcn_dw = mem_xcpt_uops_out_ctrl_fcn_dw; // @[util.scala:96:23] wire [2:0] _mem_xcpt_uops_WIRE_0_ctrl_csr_cmd = mem_xcpt_uops_out_ctrl_csr_cmd; // @[util.scala:96:23] wire _mem_xcpt_uops_WIRE_0_ctrl_is_load = mem_xcpt_uops_out_ctrl_is_load; // @[util.scala:96:23] wire _mem_xcpt_uops_WIRE_0_ctrl_is_sta = mem_xcpt_uops_out_ctrl_is_sta; // @[util.scala:96:23] wire _mem_xcpt_uops_WIRE_0_ctrl_is_std = mem_xcpt_uops_out_ctrl_is_std; // @[util.scala:96:23] wire [1:0] _mem_xcpt_uops_WIRE_0_iw_state = mem_xcpt_uops_out_iw_state; // @[util.scala:96:23] wire _mem_xcpt_uops_WIRE_0_iw_p1_poisoned = mem_xcpt_uops_out_iw_p1_poisoned; // @[util.scala:96:23] wire _mem_xcpt_uops_WIRE_0_iw_p2_poisoned = mem_xcpt_uops_out_iw_p2_poisoned; // @[util.scala:96:23] wire _mem_xcpt_uops_WIRE_0_is_br = mem_xcpt_uops_out_is_br; // @[util.scala:96:23] wire _mem_xcpt_uops_WIRE_0_is_jalr = mem_xcpt_uops_out_is_jalr; // @[util.scala:96:23] wire _mem_xcpt_uops_WIRE_0_is_jal = mem_xcpt_uops_out_is_jal; // @[util.scala:96:23] wire [7:0] _mem_xcpt_uops_out_br_mask_T_1; // @[util.scala:85:25] wire _mem_xcpt_uops_WIRE_0_is_sfb = mem_xcpt_uops_out_is_sfb; // @[util.scala:96:23] wire [7:0] _mem_xcpt_uops_WIRE_0_br_mask = mem_xcpt_uops_out_br_mask; // @[util.scala:96:23] wire [2:0] _mem_xcpt_uops_WIRE_0_br_tag = mem_xcpt_uops_out_br_tag; // @[util.scala:96:23] wire [3:0] _mem_xcpt_uops_WIRE_0_ftq_idx = mem_xcpt_uops_out_ftq_idx; // @[util.scala:96:23] wire _mem_xcpt_uops_WIRE_0_edge_inst = mem_xcpt_uops_out_edge_inst; // @[util.scala:96:23] wire [5:0] _mem_xcpt_uops_WIRE_0_pc_lob = mem_xcpt_uops_out_pc_lob; // @[util.scala:96:23] wire _mem_xcpt_uops_WIRE_0_taken = mem_xcpt_uops_out_taken; // @[util.scala:96:23] wire [19:0] _mem_xcpt_uops_WIRE_0_imm_packed = mem_xcpt_uops_out_imm_packed; // @[util.scala:96:23] wire [11:0] _mem_xcpt_uops_WIRE_0_csr_addr = mem_xcpt_uops_out_csr_addr; // @[util.scala:96:23] wire [4:0] _mem_xcpt_uops_WIRE_0_rob_idx = mem_xcpt_uops_out_rob_idx; // @[util.scala:96:23] wire [2:0] _mem_xcpt_uops_WIRE_0_ldq_idx = mem_xcpt_uops_out_ldq_idx; // @[util.scala:96:23] wire [2:0] _mem_xcpt_uops_WIRE_0_stq_idx = mem_xcpt_uops_out_stq_idx; // @[util.scala:96:23] wire [1:0] _mem_xcpt_uops_WIRE_0_rxq_idx = mem_xcpt_uops_out_rxq_idx; // @[util.scala:96:23] wire [5:0] _mem_xcpt_uops_WIRE_0_pdst = mem_xcpt_uops_out_pdst; // @[util.scala:96:23] wire [5:0] _mem_xcpt_uops_WIRE_0_prs1 = mem_xcpt_uops_out_prs1; // @[util.scala:96:23] wire [5:0] _mem_xcpt_uops_WIRE_0_prs2 = mem_xcpt_uops_out_prs2; // @[util.scala:96:23] wire [5:0] _mem_xcpt_uops_WIRE_0_prs3 = mem_xcpt_uops_out_prs3; // @[util.scala:96:23] wire [3:0] _mem_xcpt_uops_WIRE_0_ppred = mem_xcpt_uops_out_ppred; // @[util.scala:96:23] wire _mem_xcpt_uops_WIRE_0_prs1_busy = mem_xcpt_uops_out_prs1_busy; // @[util.scala:96:23] wire _mem_xcpt_uops_WIRE_0_prs2_busy = mem_xcpt_uops_out_prs2_busy; // @[util.scala:96:23] wire _mem_xcpt_uops_WIRE_0_prs3_busy = mem_xcpt_uops_out_prs3_busy; // @[util.scala:96:23] wire _mem_xcpt_uops_WIRE_0_ppred_busy = mem_xcpt_uops_out_ppred_busy; // @[util.scala:96:23] wire [5:0] _mem_xcpt_uops_WIRE_0_stale_pdst = mem_xcpt_uops_out_stale_pdst; // @[util.scala:96:23] wire _mem_xcpt_uops_WIRE_0_exception = mem_xcpt_uops_out_exception; // @[util.scala:96:23] wire [63:0] _mem_xcpt_uops_WIRE_0_exc_cause = mem_xcpt_uops_out_exc_cause; // @[util.scala:96:23] wire _mem_xcpt_uops_WIRE_0_bypassable = mem_xcpt_uops_out_bypassable; // @[util.scala:96:23] wire [4:0] _mem_xcpt_uops_WIRE_0_mem_cmd = mem_xcpt_uops_out_mem_cmd; // @[util.scala:96:23] wire [1:0] _mem_xcpt_uops_WIRE_0_mem_size = mem_xcpt_uops_out_mem_size; // @[util.scala:96:23] wire _mem_xcpt_uops_WIRE_0_mem_signed = mem_xcpt_uops_out_mem_signed; // @[util.scala:96:23] wire _mem_xcpt_uops_WIRE_0_is_fence = mem_xcpt_uops_out_is_fence; // @[util.scala:96:23] wire _mem_xcpt_uops_WIRE_0_is_fencei = mem_xcpt_uops_out_is_fencei; // @[util.scala:96:23] wire _mem_xcpt_uops_WIRE_0_is_amo = mem_xcpt_uops_out_is_amo; // @[util.scala:96:23] wire _mem_xcpt_uops_WIRE_0_uses_ldq = mem_xcpt_uops_out_uses_ldq; // @[util.scala:96:23] wire _mem_xcpt_uops_WIRE_0_uses_stq = mem_xcpt_uops_out_uses_stq; // @[util.scala:96:23] wire _mem_xcpt_uops_WIRE_0_is_sys_pc2epc = mem_xcpt_uops_out_is_sys_pc2epc; // @[util.scala:96:23] wire _mem_xcpt_uops_WIRE_0_is_unique = mem_xcpt_uops_out_is_unique; // @[util.scala:96:23] wire _mem_xcpt_uops_WIRE_0_flush_on_commit = mem_xcpt_uops_out_flush_on_commit; // @[util.scala:96:23] wire _mem_xcpt_uops_WIRE_0_ldst_is_rs1 = mem_xcpt_uops_out_ldst_is_rs1; // @[util.scala:96:23] wire [5:0] _mem_xcpt_uops_WIRE_0_ldst = mem_xcpt_uops_out_ldst; // @[util.scala:96:23] wire [5:0] _mem_xcpt_uops_WIRE_0_lrs1 = mem_xcpt_uops_out_lrs1; // @[util.scala:96:23] wire [5:0] _mem_xcpt_uops_WIRE_0_lrs2 = mem_xcpt_uops_out_lrs2; // @[util.scala:96:23] wire [5:0] _mem_xcpt_uops_WIRE_0_lrs3 = mem_xcpt_uops_out_lrs3; // @[util.scala:96:23] wire _mem_xcpt_uops_WIRE_0_ldst_val = mem_xcpt_uops_out_ldst_val; // @[util.scala:96:23] wire [1:0] _mem_xcpt_uops_WIRE_0_dst_rtype = mem_xcpt_uops_out_dst_rtype; // @[util.scala:96:23] wire [1:0] _mem_xcpt_uops_WIRE_0_lrs1_rtype = mem_xcpt_uops_out_lrs1_rtype; // @[util.scala:96:23] wire [1:0] _mem_xcpt_uops_WIRE_0_lrs2_rtype = mem_xcpt_uops_out_lrs2_rtype; // @[util.scala:96:23] wire _mem_xcpt_uops_WIRE_0_frs3_en = mem_xcpt_uops_out_frs3_en; // @[util.scala:96:23] wire _mem_xcpt_uops_WIRE_0_fp_val = mem_xcpt_uops_out_fp_val; // @[util.scala:96:23] wire _mem_xcpt_uops_WIRE_0_fp_single = mem_xcpt_uops_out_fp_single; // @[util.scala:96:23] wire _mem_xcpt_uops_WIRE_0_xcpt_pf_if = mem_xcpt_uops_out_xcpt_pf_if; // @[util.scala:96:23] wire _mem_xcpt_uops_WIRE_0_xcpt_ae_if = mem_xcpt_uops_out_xcpt_ae_if; // @[util.scala:96:23] wire _mem_xcpt_uops_WIRE_0_xcpt_ma_if = mem_xcpt_uops_out_xcpt_ma_if; // @[util.scala:96:23] wire _mem_xcpt_uops_WIRE_0_bp_debug_if = mem_xcpt_uops_out_bp_debug_if; // @[util.scala:96:23] wire _mem_xcpt_uops_WIRE_0_bp_xcpt_if = mem_xcpt_uops_out_bp_xcpt_if; // @[util.scala:96:23] wire [1:0] _mem_xcpt_uops_WIRE_0_debug_fsrc = mem_xcpt_uops_out_debug_fsrc; // @[util.scala:96:23] wire [1:0] _mem_xcpt_uops_WIRE_0_debug_tsrc = mem_xcpt_uops_out_debug_tsrc; // @[util.scala:96:23] wire [7:0] _mem_xcpt_uops_out_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:85:27] assign _mem_xcpt_uops_out_br_mask_T_1 = exe_tlb_uop_0_br_mask & _mem_xcpt_uops_out_br_mask_T; // @[util.scala:85:{25,27}] assign mem_xcpt_uops_out_br_mask = _mem_xcpt_uops_out_br_mask_T_1; // @[util.scala:85:25, :96:23] reg [6:0] mem_xcpt_uops_0_uopc; // @[lsu.scala:672:32] assign mem_xcpt_uop_uopc = mem_xcpt_uops_0_uopc; // @[lsu.scala:360:29, :672:32] reg [31:0] mem_xcpt_uops_0_inst; // @[lsu.scala:672:32] assign mem_xcpt_uop_inst = mem_xcpt_uops_0_inst; // @[lsu.scala:360:29, :672:32] reg [31:0] mem_xcpt_uops_0_debug_inst; // @[lsu.scala:672:32] assign mem_xcpt_uop_debug_inst = mem_xcpt_uops_0_debug_inst; // @[lsu.scala:360:29, :672:32] reg mem_xcpt_uops_0_is_rvc; // @[lsu.scala:672:32] assign mem_xcpt_uop_is_rvc = mem_xcpt_uops_0_is_rvc; // @[lsu.scala:360:29, :672:32] reg [39:0] mem_xcpt_uops_0_debug_pc; // @[lsu.scala:672:32] assign mem_xcpt_uop_debug_pc = mem_xcpt_uops_0_debug_pc; // @[lsu.scala:360:29, :672:32] reg [2:0] mem_xcpt_uops_0_iq_type; // @[lsu.scala:672:32] assign mem_xcpt_uop_iq_type = mem_xcpt_uops_0_iq_type; // @[lsu.scala:360:29, :672:32] reg [9:0] mem_xcpt_uops_0_fu_code; // @[lsu.scala:672:32] assign mem_xcpt_uop_fu_code = mem_xcpt_uops_0_fu_code; // @[lsu.scala:360:29, :672:32] reg [3:0] mem_xcpt_uops_0_ctrl_br_type; // @[lsu.scala:672:32] assign mem_xcpt_uop_ctrl_br_type = mem_xcpt_uops_0_ctrl_br_type; // @[lsu.scala:360:29, :672:32] reg [1:0] mem_xcpt_uops_0_ctrl_op1_sel; // @[lsu.scala:672:32] assign mem_xcpt_uop_ctrl_op1_sel = mem_xcpt_uops_0_ctrl_op1_sel; // @[lsu.scala:360:29, :672:32] reg [2:0] mem_xcpt_uops_0_ctrl_op2_sel; // @[lsu.scala:672:32] assign mem_xcpt_uop_ctrl_op2_sel = mem_xcpt_uops_0_ctrl_op2_sel; // @[lsu.scala:360:29, :672:32] reg [2:0] mem_xcpt_uops_0_ctrl_imm_sel; // @[lsu.scala:672:32] assign mem_xcpt_uop_ctrl_imm_sel = mem_xcpt_uops_0_ctrl_imm_sel; // @[lsu.scala:360:29, :672:32] reg [4:0] mem_xcpt_uops_0_ctrl_op_fcn; // @[lsu.scala:672:32] assign mem_xcpt_uop_ctrl_op_fcn = mem_xcpt_uops_0_ctrl_op_fcn; // @[lsu.scala:360:29, :672:32] reg mem_xcpt_uops_0_ctrl_fcn_dw; // @[lsu.scala:672:32] assign mem_xcpt_uop_ctrl_fcn_dw = mem_xcpt_uops_0_ctrl_fcn_dw; // @[lsu.scala:360:29, :672:32] reg [2:0] mem_xcpt_uops_0_ctrl_csr_cmd; // @[lsu.scala:672:32] assign mem_xcpt_uop_ctrl_csr_cmd = mem_xcpt_uops_0_ctrl_csr_cmd; // @[lsu.scala:360:29, :672:32] reg mem_xcpt_uops_0_ctrl_is_load; // @[lsu.scala:672:32] assign mem_xcpt_uop_ctrl_is_load = mem_xcpt_uops_0_ctrl_is_load; // @[lsu.scala:360:29, :672:32] reg mem_xcpt_uops_0_ctrl_is_sta; // @[lsu.scala:672:32] assign mem_xcpt_uop_ctrl_is_sta = mem_xcpt_uops_0_ctrl_is_sta; // @[lsu.scala:360:29, :672:32] reg mem_xcpt_uops_0_ctrl_is_std; // @[lsu.scala:672:32] assign mem_xcpt_uop_ctrl_is_std = mem_xcpt_uops_0_ctrl_is_std; // @[lsu.scala:360:29, :672:32] reg [1:0] mem_xcpt_uops_0_iw_state; // @[lsu.scala:672:32] assign mem_xcpt_uop_iw_state = mem_xcpt_uops_0_iw_state; // @[lsu.scala:360:29, :672:32] reg mem_xcpt_uops_0_iw_p1_poisoned; // @[lsu.scala:672:32] assign mem_xcpt_uop_iw_p1_poisoned = mem_xcpt_uops_0_iw_p1_poisoned; // @[lsu.scala:360:29, :672:32] reg mem_xcpt_uops_0_iw_p2_poisoned; // @[lsu.scala:672:32] assign mem_xcpt_uop_iw_p2_poisoned = mem_xcpt_uops_0_iw_p2_poisoned; // @[lsu.scala:360:29, :672:32] reg mem_xcpt_uops_0_is_br; // @[lsu.scala:672:32] assign mem_xcpt_uop_is_br = mem_xcpt_uops_0_is_br; // @[lsu.scala:360:29, :672:32] reg mem_xcpt_uops_0_is_jalr; // @[lsu.scala:672:32] assign mem_xcpt_uop_is_jalr = mem_xcpt_uops_0_is_jalr; // @[lsu.scala:360:29, :672:32] reg mem_xcpt_uops_0_is_jal; // @[lsu.scala:672:32] assign mem_xcpt_uop_is_jal = mem_xcpt_uops_0_is_jal; // @[lsu.scala:360:29, :672:32] reg mem_xcpt_uops_0_is_sfb; // @[lsu.scala:672:32] assign mem_xcpt_uop_is_sfb = mem_xcpt_uops_0_is_sfb; // @[lsu.scala:360:29, :672:32] reg [7:0] mem_xcpt_uops_0_br_mask; // @[lsu.scala:672:32] assign mem_xcpt_uop_br_mask = mem_xcpt_uops_0_br_mask; // @[lsu.scala:360:29, :672:32] reg [2:0] mem_xcpt_uops_0_br_tag; // @[lsu.scala:672:32] assign mem_xcpt_uop_br_tag = mem_xcpt_uops_0_br_tag; // @[lsu.scala:360:29, :672:32] reg [3:0] mem_xcpt_uops_0_ftq_idx; // @[lsu.scala:672:32] assign mem_xcpt_uop_ftq_idx = mem_xcpt_uops_0_ftq_idx; // @[lsu.scala:360:29, :672:32] reg mem_xcpt_uops_0_edge_inst; // @[lsu.scala:672:32] assign mem_xcpt_uop_edge_inst = mem_xcpt_uops_0_edge_inst; // @[lsu.scala:360:29, :672:32] reg [5:0] mem_xcpt_uops_0_pc_lob; // @[lsu.scala:672:32] assign mem_xcpt_uop_pc_lob = mem_xcpt_uops_0_pc_lob; // @[lsu.scala:360:29, :672:32] reg mem_xcpt_uops_0_taken; // @[lsu.scala:672:32] assign mem_xcpt_uop_taken = mem_xcpt_uops_0_taken; // @[lsu.scala:360:29, :672:32] reg [19:0] mem_xcpt_uops_0_imm_packed; // @[lsu.scala:672:32] assign mem_xcpt_uop_imm_packed = mem_xcpt_uops_0_imm_packed; // @[lsu.scala:360:29, :672:32] reg [11:0] mem_xcpt_uops_0_csr_addr; // @[lsu.scala:672:32] assign mem_xcpt_uop_csr_addr = mem_xcpt_uops_0_csr_addr; // @[lsu.scala:360:29, :672:32] reg [4:0] mem_xcpt_uops_0_rob_idx; // @[lsu.scala:672:32] assign mem_xcpt_uop_rob_idx = mem_xcpt_uops_0_rob_idx; // @[lsu.scala:360:29, :672:32] reg [2:0] mem_xcpt_uops_0_ldq_idx; // @[lsu.scala:672:32] assign mem_xcpt_uop_ldq_idx = mem_xcpt_uops_0_ldq_idx; // @[lsu.scala:360:29, :672:32] reg [2:0] mem_xcpt_uops_0_stq_idx; // @[lsu.scala:672:32] assign mem_xcpt_uop_stq_idx = mem_xcpt_uops_0_stq_idx; // @[lsu.scala:360:29, :672:32] reg [1:0] mem_xcpt_uops_0_rxq_idx; // @[lsu.scala:672:32] assign mem_xcpt_uop_rxq_idx = mem_xcpt_uops_0_rxq_idx; // @[lsu.scala:360:29, :672:32] reg [5:0] mem_xcpt_uops_0_pdst; // @[lsu.scala:672:32] assign mem_xcpt_uop_pdst = mem_xcpt_uops_0_pdst; // @[lsu.scala:360:29, :672:32] reg [5:0] mem_xcpt_uops_0_prs1; // @[lsu.scala:672:32] assign mem_xcpt_uop_prs1 = mem_xcpt_uops_0_prs1; // @[lsu.scala:360:29, :672:32] reg [5:0] mem_xcpt_uops_0_prs2; // @[lsu.scala:672:32] assign mem_xcpt_uop_prs2 = mem_xcpt_uops_0_prs2; // @[lsu.scala:360:29, :672:32] reg [5:0] mem_xcpt_uops_0_prs3; // @[lsu.scala:672:32] assign mem_xcpt_uop_prs3 = mem_xcpt_uops_0_prs3; // @[lsu.scala:360:29, :672:32] reg [3:0] mem_xcpt_uops_0_ppred; // @[lsu.scala:672:32] assign mem_xcpt_uop_ppred = mem_xcpt_uops_0_ppred; // @[lsu.scala:360:29, :672:32] reg mem_xcpt_uops_0_prs1_busy; // @[lsu.scala:672:32] assign mem_xcpt_uop_prs1_busy = mem_xcpt_uops_0_prs1_busy; // @[lsu.scala:360:29, :672:32] reg mem_xcpt_uops_0_prs2_busy; // @[lsu.scala:672:32] assign mem_xcpt_uop_prs2_busy = mem_xcpt_uops_0_prs2_busy; // @[lsu.scala:360:29, :672:32] reg mem_xcpt_uops_0_prs3_busy; // @[lsu.scala:672:32] assign mem_xcpt_uop_prs3_busy = mem_xcpt_uops_0_prs3_busy; // @[lsu.scala:360:29, :672:32] reg mem_xcpt_uops_0_ppred_busy; // @[lsu.scala:672:32] assign mem_xcpt_uop_ppred_busy = mem_xcpt_uops_0_ppred_busy; // @[lsu.scala:360:29, :672:32] reg [5:0] mem_xcpt_uops_0_stale_pdst; // @[lsu.scala:672:32] assign mem_xcpt_uop_stale_pdst = mem_xcpt_uops_0_stale_pdst; // @[lsu.scala:360:29, :672:32] reg mem_xcpt_uops_0_exception; // @[lsu.scala:672:32] assign mem_xcpt_uop_exception = mem_xcpt_uops_0_exception; // @[lsu.scala:360:29, :672:32] reg [63:0] mem_xcpt_uops_0_exc_cause; // @[lsu.scala:672:32] assign mem_xcpt_uop_exc_cause = mem_xcpt_uops_0_exc_cause; // @[lsu.scala:360:29, :672:32] reg mem_xcpt_uops_0_bypassable; // @[lsu.scala:672:32] assign mem_xcpt_uop_bypassable = mem_xcpt_uops_0_bypassable; // @[lsu.scala:360:29, :672:32] reg [4:0] mem_xcpt_uops_0_mem_cmd; // @[lsu.scala:672:32] assign mem_xcpt_uop_mem_cmd = mem_xcpt_uops_0_mem_cmd; // @[lsu.scala:360:29, :672:32] reg [1:0] mem_xcpt_uops_0_mem_size; // @[lsu.scala:672:32] assign mem_xcpt_uop_mem_size = mem_xcpt_uops_0_mem_size; // @[lsu.scala:360:29, :672:32] reg mem_xcpt_uops_0_mem_signed; // @[lsu.scala:672:32] assign mem_xcpt_uop_mem_signed = mem_xcpt_uops_0_mem_signed; // @[lsu.scala:360:29, :672:32] reg mem_xcpt_uops_0_is_fence; // @[lsu.scala:672:32] assign mem_xcpt_uop_is_fence = mem_xcpt_uops_0_is_fence; // @[lsu.scala:360:29, :672:32] reg mem_xcpt_uops_0_is_fencei; // @[lsu.scala:672:32] assign mem_xcpt_uop_is_fencei = mem_xcpt_uops_0_is_fencei; // @[lsu.scala:360:29, :672:32] reg mem_xcpt_uops_0_is_amo; // @[lsu.scala:672:32] assign mem_xcpt_uop_is_amo = mem_xcpt_uops_0_is_amo; // @[lsu.scala:360:29, :672:32] reg mem_xcpt_uops_0_uses_ldq; // @[lsu.scala:672:32] assign mem_xcpt_uop_uses_ldq = mem_xcpt_uops_0_uses_ldq; // @[lsu.scala:360:29, :672:32] reg mem_xcpt_uops_0_uses_stq; // @[lsu.scala:672:32] assign mem_xcpt_uop_uses_stq = mem_xcpt_uops_0_uses_stq; // @[lsu.scala:360:29, :672:32] reg mem_xcpt_uops_0_is_sys_pc2epc; // @[lsu.scala:672:32] assign mem_xcpt_uop_is_sys_pc2epc = mem_xcpt_uops_0_is_sys_pc2epc; // @[lsu.scala:360:29, :672:32] reg mem_xcpt_uops_0_is_unique; // @[lsu.scala:672:32] assign mem_xcpt_uop_is_unique = mem_xcpt_uops_0_is_unique; // @[lsu.scala:360:29, :672:32] reg mem_xcpt_uops_0_flush_on_commit; // @[lsu.scala:672:32] assign mem_xcpt_uop_flush_on_commit = mem_xcpt_uops_0_flush_on_commit; // @[lsu.scala:360:29, :672:32] reg mem_xcpt_uops_0_ldst_is_rs1; // @[lsu.scala:672:32] assign mem_xcpt_uop_ldst_is_rs1 = mem_xcpt_uops_0_ldst_is_rs1; // @[lsu.scala:360:29, :672:32] reg [5:0] mem_xcpt_uops_0_ldst; // @[lsu.scala:672:32] assign mem_xcpt_uop_ldst = mem_xcpt_uops_0_ldst; // @[lsu.scala:360:29, :672:32] reg [5:0] mem_xcpt_uops_0_lrs1; // @[lsu.scala:672:32] assign mem_xcpt_uop_lrs1 = mem_xcpt_uops_0_lrs1; // @[lsu.scala:360:29, :672:32] reg [5:0] mem_xcpt_uops_0_lrs2; // @[lsu.scala:672:32] assign mem_xcpt_uop_lrs2 = mem_xcpt_uops_0_lrs2; // @[lsu.scala:360:29, :672:32] reg [5:0] mem_xcpt_uops_0_lrs3; // @[lsu.scala:672:32] assign mem_xcpt_uop_lrs3 = mem_xcpt_uops_0_lrs3; // @[lsu.scala:360:29, :672:32] reg mem_xcpt_uops_0_ldst_val; // @[lsu.scala:672:32] assign mem_xcpt_uop_ldst_val = mem_xcpt_uops_0_ldst_val; // @[lsu.scala:360:29, :672:32] reg [1:0] mem_xcpt_uops_0_dst_rtype; // @[lsu.scala:672:32] assign mem_xcpt_uop_dst_rtype = mem_xcpt_uops_0_dst_rtype; // @[lsu.scala:360:29, :672:32] reg [1:0] mem_xcpt_uops_0_lrs1_rtype; // @[lsu.scala:672:32] assign mem_xcpt_uop_lrs1_rtype = mem_xcpt_uops_0_lrs1_rtype; // @[lsu.scala:360:29, :672:32] reg [1:0] mem_xcpt_uops_0_lrs2_rtype; // @[lsu.scala:672:32] assign mem_xcpt_uop_lrs2_rtype = mem_xcpt_uops_0_lrs2_rtype; // @[lsu.scala:360:29, :672:32] reg mem_xcpt_uops_0_frs3_en; // @[lsu.scala:672:32] assign mem_xcpt_uop_frs3_en = mem_xcpt_uops_0_frs3_en; // @[lsu.scala:360:29, :672:32] reg mem_xcpt_uops_0_fp_val; // @[lsu.scala:672:32] assign mem_xcpt_uop_fp_val = mem_xcpt_uops_0_fp_val; // @[lsu.scala:360:29, :672:32] reg mem_xcpt_uops_0_fp_single; // @[lsu.scala:672:32] assign mem_xcpt_uop_fp_single = mem_xcpt_uops_0_fp_single; // @[lsu.scala:360:29, :672:32] reg mem_xcpt_uops_0_xcpt_pf_if; // @[lsu.scala:672:32] assign mem_xcpt_uop_xcpt_pf_if = mem_xcpt_uops_0_xcpt_pf_if; // @[lsu.scala:360:29, :672:32] reg mem_xcpt_uops_0_xcpt_ae_if; // @[lsu.scala:672:32] assign mem_xcpt_uop_xcpt_ae_if = mem_xcpt_uops_0_xcpt_ae_if; // @[lsu.scala:360:29, :672:32] reg mem_xcpt_uops_0_xcpt_ma_if; // @[lsu.scala:672:32] assign mem_xcpt_uop_xcpt_ma_if = mem_xcpt_uops_0_xcpt_ma_if; // @[lsu.scala:360:29, :672:32] reg mem_xcpt_uops_0_bp_debug_if; // @[lsu.scala:672:32] assign mem_xcpt_uop_bp_debug_if = mem_xcpt_uops_0_bp_debug_if; // @[lsu.scala:360:29, :672:32] reg mem_xcpt_uops_0_bp_xcpt_if; // @[lsu.scala:672:32] assign mem_xcpt_uop_bp_xcpt_if = mem_xcpt_uops_0_bp_xcpt_if; // @[lsu.scala:360:29, :672:32] reg [1:0] mem_xcpt_uops_0_debug_fsrc; // @[lsu.scala:672:32] assign mem_xcpt_uop_debug_fsrc = mem_xcpt_uops_0_debug_fsrc; // @[lsu.scala:360:29, :672:32] reg [1:0] mem_xcpt_uops_0_debug_tsrc; // @[lsu.scala:672:32] assign mem_xcpt_uop_debug_tsrc = mem_xcpt_uops_0_debug_tsrc; // @[lsu.scala:360:29, :672:32] wire [2:0] _mem_xcpt_causes_T = {1'h1, ~ae_ld_0, 1'h1}; // @[lsu.scala:263:49, :678:8] wire [3:0] _mem_xcpt_causes_T_1 = pf_st_0 ? 4'hF : {1'h0, _mem_xcpt_causes_T}; // @[lsu.scala:263:49, :677:8, :678:8] wire [3:0] _mem_xcpt_causes_T_2 = pf_ld_0 ? 4'hD : _mem_xcpt_causes_T_1; // @[lsu.scala:263:49, :676:8, :677:8] wire [3:0] _mem_xcpt_causes_T_3 = ma_st_0 ? 4'h6 : _mem_xcpt_causes_T_2; // @[lsu.scala:263:49, :675:8, :676:8] wire [3:0] _mem_xcpt_causes_T_4 = ma_ld_0 ? 4'h4 : _mem_xcpt_causes_T_3; // @[lsu.scala:263:49, :674:8, :675:8] wire [3:0] _mem_xcpt_causes_WIRE_0 = _mem_xcpt_causes_T_4; // @[lsu.scala:263:49, :674:8] reg [3:0] mem_xcpt_causes_0; // @[lsu.scala:673:32] assign mem_xcpt_cause = mem_xcpt_causes_0; // @[lsu.scala:359:29, :673:32] reg [39:0] mem_xcpt_vaddrs_0; // @[lsu.scala:680:32] assign mem_xcpt_vaddr = mem_xcpt_vaddrs_0; // @[lsu.scala:361:29, :680:32] wire _exe_tlb_miss_T_1; // @[lsu.scala:709:83] wire _exe_tlb_miss_T_2 = exe_tlb_valid_0 & _exe_tlb_miss_T_1; // @[lsu.scala:525:27, :709:{58,83}] wire exe_tlb_miss_0 = _exe_tlb_miss_T_2; // @[lsu.scala:263:49, :709:58] wire [19:0] _exe_tlb_paddr_T = _dtlb_io_resp_0_paddr[31:12]; // @[lsu.scala:247:20, :710:62] wire [11:0] _exe_tlb_paddr_T_1 = exe_tlb_vaddr_0[11:0]; // @[lsu.scala:263:49, :711:57] wire [31:0] _exe_tlb_paddr_T_2 = {_exe_tlb_paddr_T, _exe_tlb_paddr_T_1}; // @[lsu.scala:710:{40,62}, :711:57] wire [31:0] exe_tlb_paddr_0 = _exe_tlb_paddr_T_2; // @[lsu.scala:263:49, :710:40] wire _exe_tlb_uncacheable_T = ~_dtlb_io_resp_0_cacheable; // @[lsu.scala:247:20, :712:43] wire exe_tlb_uncacheable_0 = _exe_tlb_uncacheable_T; // @[lsu.scala:263:49, :712:43] reg REG; // @[lsu.scala:719:21] assign io_dmem_req_valid_0 = dmem_req_0_valid; // @[lsu.scala:201:7, :750:22] assign io_dmem_req_bits_0_valid_0 = dmem_req_0_valid; // @[lsu.scala:201:7, :750:22] assign io_dmem_req_bits_0_bits_uop_uopc_0 = dmem_req_0_bits_uop_uopc; // @[lsu.scala:201:7, :750:22] assign io_dmem_req_bits_0_bits_uop_inst_0 = dmem_req_0_bits_uop_inst; // @[lsu.scala:201:7, :750:22] assign io_dmem_req_bits_0_bits_uop_debug_inst_0 = dmem_req_0_bits_uop_debug_inst; // @[lsu.scala:201:7, :750:22] assign io_dmem_req_bits_0_bits_uop_is_rvc_0 = dmem_req_0_bits_uop_is_rvc; // @[lsu.scala:201:7, :750:22] assign io_dmem_req_bits_0_bits_uop_debug_pc_0 = dmem_req_0_bits_uop_debug_pc; // @[lsu.scala:201:7, :750:22] assign io_dmem_req_bits_0_bits_uop_iq_type_0 = dmem_req_0_bits_uop_iq_type; // @[lsu.scala:201:7, :750:22] assign io_dmem_req_bits_0_bits_uop_fu_code_0 = dmem_req_0_bits_uop_fu_code; // @[lsu.scala:201:7, :750:22] assign io_dmem_req_bits_0_bits_uop_ctrl_br_type_0 = dmem_req_0_bits_uop_ctrl_br_type; // @[lsu.scala:201:7, :750:22] assign io_dmem_req_bits_0_bits_uop_ctrl_op1_sel_0 = dmem_req_0_bits_uop_ctrl_op1_sel; // @[lsu.scala:201:7, :750:22] assign io_dmem_req_bits_0_bits_uop_ctrl_op2_sel_0 = dmem_req_0_bits_uop_ctrl_op2_sel; // @[lsu.scala:201:7, :750:22] assign io_dmem_req_bits_0_bits_uop_ctrl_imm_sel_0 = dmem_req_0_bits_uop_ctrl_imm_sel; // @[lsu.scala:201:7, :750:22] assign io_dmem_req_bits_0_bits_uop_ctrl_op_fcn_0 = dmem_req_0_bits_uop_ctrl_op_fcn; // @[lsu.scala:201:7, :750:22] assign io_dmem_req_bits_0_bits_uop_ctrl_fcn_dw_0 = dmem_req_0_bits_uop_ctrl_fcn_dw; // @[lsu.scala:201:7, :750:22] assign io_dmem_req_bits_0_bits_uop_ctrl_csr_cmd_0 = dmem_req_0_bits_uop_ctrl_csr_cmd; // @[lsu.scala:201:7, :750:22] assign io_dmem_req_bits_0_bits_uop_ctrl_is_load_0 = dmem_req_0_bits_uop_ctrl_is_load; // @[lsu.scala:201:7, :750:22] assign io_dmem_req_bits_0_bits_uop_ctrl_is_sta_0 = dmem_req_0_bits_uop_ctrl_is_sta; // @[lsu.scala:201:7, :750:22] assign io_dmem_req_bits_0_bits_uop_ctrl_is_std_0 = dmem_req_0_bits_uop_ctrl_is_std; // @[lsu.scala:201:7, :750:22] assign io_dmem_req_bits_0_bits_uop_iw_state_0 = dmem_req_0_bits_uop_iw_state; // @[lsu.scala:201:7, :750:22] assign io_dmem_req_bits_0_bits_uop_iw_p1_poisoned_0 = dmem_req_0_bits_uop_iw_p1_poisoned; // @[lsu.scala:201:7, :750:22] assign io_dmem_req_bits_0_bits_uop_iw_p2_poisoned_0 = dmem_req_0_bits_uop_iw_p2_poisoned; // @[lsu.scala:201:7, :750:22] assign io_dmem_req_bits_0_bits_uop_is_br_0 = dmem_req_0_bits_uop_is_br; // @[lsu.scala:201:7, :750:22] assign io_dmem_req_bits_0_bits_uop_is_jalr_0 = dmem_req_0_bits_uop_is_jalr; // @[lsu.scala:201:7, :750:22] assign io_dmem_req_bits_0_bits_uop_is_jal_0 = dmem_req_0_bits_uop_is_jal; // @[lsu.scala:201:7, :750:22] assign io_dmem_req_bits_0_bits_uop_is_sfb_0 = dmem_req_0_bits_uop_is_sfb; // @[lsu.scala:201:7, :750:22] assign io_dmem_req_bits_0_bits_uop_br_mask_0 = dmem_req_0_bits_uop_br_mask; // @[lsu.scala:201:7, :750:22] assign io_dmem_req_bits_0_bits_uop_br_tag_0 = dmem_req_0_bits_uop_br_tag; // @[lsu.scala:201:7, :750:22] assign io_dmem_req_bits_0_bits_uop_ftq_idx_0 = dmem_req_0_bits_uop_ftq_idx; // @[lsu.scala:201:7, :750:22] assign io_dmem_req_bits_0_bits_uop_edge_inst_0 = dmem_req_0_bits_uop_edge_inst; // @[lsu.scala:201:7, :750:22] assign io_dmem_req_bits_0_bits_uop_pc_lob_0 = dmem_req_0_bits_uop_pc_lob; // @[lsu.scala:201:7, :750:22] assign io_dmem_req_bits_0_bits_uop_taken_0 = dmem_req_0_bits_uop_taken; // @[lsu.scala:201:7, :750:22] assign io_dmem_req_bits_0_bits_uop_imm_packed_0 = dmem_req_0_bits_uop_imm_packed; // @[lsu.scala:201:7, :750:22] assign io_dmem_req_bits_0_bits_uop_csr_addr_0 = dmem_req_0_bits_uop_csr_addr; // @[lsu.scala:201:7, :750:22] assign io_dmem_req_bits_0_bits_uop_rob_idx_0 = dmem_req_0_bits_uop_rob_idx; // @[lsu.scala:201:7, :750:22] assign io_dmem_req_bits_0_bits_uop_ldq_idx_0 = dmem_req_0_bits_uop_ldq_idx; // @[lsu.scala:201:7, :750:22] assign io_dmem_req_bits_0_bits_uop_stq_idx_0 = dmem_req_0_bits_uop_stq_idx; // @[lsu.scala:201:7, :750:22] assign io_dmem_req_bits_0_bits_uop_rxq_idx_0 = dmem_req_0_bits_uop_rxq_idx; // @[lsu.scala:201:7, :750:22] assign io_dmem_req_bits_0_bits_uop_pdst_0 = dmem_req_0_bits_uop_pdst; // @[lsu.scala:201:7, :750:22] assign io_dmem_req_bits_0_bits_uop_prs1_0 = dmem_req_0_bits_uop_prs1; // @[lsu.scala:201:7, :750:22] assign io_dmem_req_bits_0_bits_uop_prs2_0 = dmem_req_0_bits_uop_prs2; // @[lsu.scala:201:7, :750:22] assign io_dmem_req_bits_0_bits_uop_prs3_0 = dmem_req_0_bits_uop_prs3; // @[lsu.scala:201:7, :750:22] assign io_dmem_req_bits_0_bits_uop_ppred_0 = dmem_req_0_bits_uop_ppred; // @[lsu.scala:201:7, :750:22] assign io_dmem_req_bits_0_bits_uop_prs1_busy_0 = dmem_req_0_bits_uop_prs1_busy; // @[lsu.scala:201:7, :750:22] assign io_dmem_req_bits_0_bits_uop_prs2_busy_0 = dmem_req_0_bits_uop_prs2_busy; // @[lsu.scala:201:7, :750:22] assign io_dmem_req_bits_0_bits_uop_prs3_busy_0 = dmem_req_0_bits_uop_prs3_busy; // @[lsu.scala:201:7, :750:22] assign io_dmem_req_bits_0_bits_uop_ppred_busy_0 = dmem_req_0_bits_uop_ppred_busy; // @[lsu.scala:201:7, :750:22] assign io_dmem_req_bits_0_bits_uop_stale_pdst_0 = dmem_req_0_bits_uop_stale_pdst; // @[lsu.scala:201:7, :750:22] assign io_dmem_req_bits_0_bits_uop_exception_0 = dmem_req_0_bits_uop_exception; // @[lsu.scala:201:7, :750:22] assign io_dmem_req_bits_0_bits_uop_exc_cause_0 = dmem_req_0_bits_uop_exc_cause; // @[lsu.scala:201:7, :750:22] assign io_dmem_req_bits_0_bits_uop_bypassable_0 = dmem_req_0_bits_uop_bypassable; // @[lsu.scala:201:7, :750:22] assign io_dmem_req_bits_0_bits_uop_mem_cmd_0 = dmem_req_0_bits_uop_mem_cmd; // @[lsu.scala:201:7, :750:22] assign io_dmem_req_bits_0_bits_uop_mem_size_0 = dmem_req_0_bits_uop_mem_size; // @[lsu.scala:201:7, :750:22] assign io_dmem_req_bits_0_bits_uop_mem_signed_0 = dmem_req_0_bits_uop_mem_signed; // @[lsu.scala:201:7, :750:22] assign io_dmem_req_bits_0_bits_uop_is_fence_0 = dmem_req_0_bits_uop_is_fence; // @[lsu.scala:201:7, :750:22] assign io_dmem_req_bits_0_bits_uop_is_fencei_0 = dmem_req_0_bits_uop_is_fencei; // @[lsu.scala:201:7, :750:22] assign io_dmem_req_bits_0_bits_uop_is_amo_0 = dmem_req_0_bits_uop_is_amo; // @[lsu.scala:201:7, :750:22] assign io_dmem_req_bits_0_bits_uop_uses_ldq_0 = dmem_req_0_bits_uop_uses_ldq; // @[lsu.scala:201:7, :750:22] assign io_dmem_req_bits_0_bits_uop_uses_stq_0 = dmem_req_0_bits_uop_uses_stq; // @[lsu.scala:201:7, :750:22] assign io_dmem_req_bits_0_bits_uop_is_sys_pc2epc_0 = dmem_req_0_bits_uop_is_sys_pc2epc; // @[lsu.scala:201:7, :750:22] assign io_dmem_req_bits_0_bits_uop_is_unique_0 = dmem_req_0_bits_uop_is_unique; // @[lsu.scala:201:7, :750:22] assign io_dmem_req_bits_0_bits_uop_flush_on_commit_0 = dmem_req_0_bits_uop_flush_on_commit; // @[lsu.scala:201:7, :750:22] assign io_dmem_req_bits_0_bits_uop_ldst_is_rs1_0 = dmem_req_0_bits_uop_ldst_is_rs1; // @[lsu.scala:201:7, :750:22] assign io_dmem_req_bits_0_bits_uop_ldst_0 = dmem_req_0_bits_uop_ldst; // @[lsu.scala:201:7, :750:22] assign io_dmem_req_bits_0_bits_uop_lrs1_0 = dmem_req_0_bits_uop_lrs1; // @[lsu.scala:201:7, :750:22] assign io_dmem_req_bits_0_bits_uop_lrs2_0 = dmem_req_0_bits_uop_lrs2; // @[lsu.scala:201:7, :750:22] assign io_dmem_req_bits_0_bits_uop_lrs3_0 = dmem_req_0_bits_uop_lrs3; // @[lsu.scala:201:7, :750:22] assign io_dmem_req_bits_0_bits_uop_ldst_val_0 = dmem_req_0_bits_uop_ldst_val; // @[lsu.scala:201:7, :750:22] assign io_dmem_req_bits_0_bits_uop_dst_rtype_0 = dmem_req_0_bits_uop_dst_rtype; // @[lsu.scala:201:7, :750:22] assign io_dmem_req_bits_0_bits_uop_lrs1_rtype_0 = dmem_req_0_bits_uop_lrs1_rtype; // @[lsu.scala:201:7, :750:22] assign io_dmem_req_bits_0_bits_uop_lrs2_rtype_0 = dmem_req_0_bits_uop_lrs2_rtype; // @[lsu.scala:201:7, :750:22] assign io_dmem_req_bits_0_bits_uop_frs3_en_0 = dmem_req_0_bits_uop_frs3_en; // @[lsu.scala:201:7, :750:22] assign io_dmem_req_bits_0_bits_uop_fp_val_0 = dmem_req_0_bits_uop_fp_val; // @[lsu.scala:201:7, :750:22] assign io_dmem_req_bits_0_bits_uop_fp_single_0 = dmem_req_0_bits_uop_fp_single; // @[lsu.scala:201:7, :750:22] assign io_dmem_req_bits_0_bits_uop_xcpt_pf_if_0 = dmem_req_0_bits_uop_xcpt_pf_if; // @[lsu.scala:201:7, :750:22] assign io_dmem_req_bits_0_bits_uop_xcpt_ae_if_0 = dmem_req_0_bits_uop_xcpt_ae_if; // @[lsu.scala:201:7, :750:22] assign io_dmem_req_bits_0_bits_uop_xcpt_ma_if_0 = dmem_req_0_bits_uop_xcpt_ma_if; // @[lsu.scala:201:7, :750:22] assign io_dmem_req_bits_0_bits_uop_bp_debug_if_0 = dmem_req_0_bits_uop_bp_debug_if; // @[lsu.scala:201:7, :750:22] assign io_dmem_req_bits_0_bits_uop_bp_xcpt_if_0 = dmem_req_0_bits_uop_bp_xcpt_if; // @[lsu.scala:201:7, :750:22] assign io_dmem_req_bits_0_bits_uop_debug_fsrc_0 = dmem_req_0_bits_uop_debug_fsrc; // @[lsu.scala:201:7, :750:22] assign io_dmem_req_bits_0_bits_uop_debug_tsrc_0 = dmem_req_0_bits_uop_debug_tsrc; // @[lsu.scala:201:7, :750:22] assign io_dmem_req_bits_0_bits_addr_0 = dmem_req_0_bits_addr; // @[lsu.scala:201:7, :750:22] wire [39:0] _mem_paddr_WIRE_0 = dmem_req_0_bits_addr; // @[lsu.scala:263:49, :750:22] assign io_dmem_req_bits_0_bits_data_0 = dmem_req_0_bits_data; // @[lsu.scala:201:7, :750:22] assign io_dmem_req_bits_0_bits_is_hella_0 = dmem_req_0_bits_is_hella; // @[lsu.scala:201:7, :750:22] wire _dmem_req_fire_T = io_dmem_req_ready_0 & io_dmem_req_valid_0; // @[Decoupled.scala:51:35] wire _dmem_req_fire_T_1 = dmem_req_0_valid & _dmem_req_fire_T; // @[Decoupled.scala:51:35] wire dmem_req_fire_0 = _dmem_req_fire_T_1; // @[lsu.scala:263:49, :753:55] wire s0_executing_loads_0; // @[lsu.scala:755:36] wire s0_executing_loads_1; // @[lsu.scala:755:36] wire s0_executing_loads_2; // @[lsu.scala:755:36] wire s0_executing_loads_3; // @[lsu.scala:755:36] wire s0_executing_loads_4; // @[lsu.scala:755:36] wire s0_executing_loads_5; // @[lsu.scala:755:36] wire s0_executing_loads_6; // @[lsu.scala:755:36] wire s0_executing_loads_7; // @[lsu.scala:755:36] wire _dmem_req_0_valid_T = ~exe_tlb_miss_0; // @[lsu.scala:263:49, :768:33] wire _dmem_req_0_valid_T_1 = ~exe_tlb_uncacheable_0; // @[lsu.scala:263:49, :768:53] wire _dmem_req_0_valid_T_2 = _dmem_req_0_valid_T & _dmem_req_0_valid_T_1; // @[lsu.scala:768:{33,50,53}] wire [39:0] _GEN_217 = {8'h0, exe_tlb_paddr_0}; // @[lsu.scala:263:49, :769:30] wire _dmem_req_0_valid_T_3 = ~exe_tlb_miss_0; // @[lsu.scala:263:49, :768:33, :775:33] wire _dmem_req_0_valid_T_4 = ~exe_tlb_uncacheable_0; // @[lsu.scala:263:49, :768:53, :775:53] wire _dmem_req_0_valid_T_5 = _dmem_req_0_valid_T_3 & _dmem_req_0_valid_T_4; // @[lsu.scala:775:{33,50,53}] wire _dmem_req_0_bits_data_T = dmem_req_0_bits_data_size == 2'h0; // @[AMOALU.scala:11:18, :29:19] wire [7:0] _dmem_req_0_bits_data_T_1 = _GEN_88[7:0]; // @[AMOALU.scala:29:69] wire [15:0] _dmem_req_0_bits_data_T_2 = {2{_dmem_req_0_bits_data_T_1}}; // @[AMOALU.scala:29:{32,69}] wire [31:0] _dmem_req_0_bits_data_T_3 = {2{_dmem_req_0_bits_data_T_2}}; // @[AMOALU.scala:29:32] wire [63:0] _dmem_req_0_bits_data_T_4 = {2{_dmem_req_0_bits_data_T_3}}; // @[AMOALU.scala:29:32] wire _dmem_req_0_bits_data_T_5 = dmem_req_0_bits_data_size == 2'h1; // @[AMOALU.scala:11:18, :29:19] wire [15:0] _dmem_req_0_bits_data_T_6 = _GEN_88[15:0]; // @[AMOALU.scala:29:69] wire [31:0] _dmem_req_0_bits_data_T_7 = {2{_dmem_req_0_bits_data_T_6}}; // @[AMOALU.scala:29:{32,69}] wire [63:0] _dmem_req_0_bits_data_T_8 = {2{_dmem_req_0_bits_data_T_7}}; // @[AMOALU.scala:29:32] wire _dmem_req_0_bits_data_T_9 = dmem_req_0_bits_data_size == 2'h2; // @[AMOALU.scala:11:18, :29:19] wire [31:0] _dmem_req_0_bits_data_T_10 = _GEN_88[31:0]; // @[AMOALU.scala:29:69] wire [63:0] _dmem_req_0_bits_data_T_11 = {2{_dmem_req_0_bits_data_T_10}}; // @[AMOALU.scala:29:{32,69}] wire [63:0] _dmem_req_0_bits_data_T_12 = _dmem_req_0_bits_data_T_9 ? _dmem_req_0_bits_data_T_11 : _GEN_88; // @[AMOALU.scala:29:{13,19,32}] wire [63:0] _dmem_req_0_bits_data_T_13 = _dmem_req_0_bits_data_T_5 ? _dmem_req_0_bits_data_T_8 : _dmem_req_0_bits_data_T_12; // @[AMOALU.scala:29:{13,19,32}] wire [63:0] _dmem_req_0_bits_data_T_14 = _dmem_req_0_bits_data_T ? _dmem_req_0_bits_data_T_4 : _dmem_req_0_bits_data_T_13; // @[AMOALU.scala:29:{13,19,32}] wire [3:0] _GEN_218 = {1'h0, stq_execute_head} + 4'h1; // @[util.scala:203:14] wire [3:0] _stq_execute_head_T; // @[util.scala:203:14] assign _stq_execute_head_T = _GEN_218; // @[util.scala:203:14] wire [3:0] _stq_execute_head_T_4; // @[util.scala:203:14] assign _stq_execute_head_T_4 = _GEN_218; // @[util.scala:203:14] wire [2:0] _stq_execute_head_T_1 = _stq_execute_head_T[2:0]; // @[util.scala:203:14] wire [2:0] _stq_execute_head_T_2 = _stq_execute_head_T_1; // @[util.scala:203:{14,20}] wire [2:0] _stq_execute_head_T_3 = dmem_req_fire_0 ? _stq_execute_head_T_2 : stq_execute_head; // @[util.scala:203:20] wire _GEN_219 = will_fire_load_incoming_0 \| will_fire_load_retry_0; // @[lsu.scala:218:29, :370:38, :378:38, :767:39, :774:43, :781:45] assign dmem_req_0_bits_uop_uopc = _GEN_219 ? exe_tlb_uop_0_uopc : will_fire_store_commit_0 ? _GEN_1[stq_execute_head] : will_fire_load_wakeup_0 ? mem_ldq_wakeup_e_out_bits_uop_uopc : 7'h0; // @[util.scala:106:23] assign dmem_req_0_bits_uop_inst = _GEN_219 ? exe_tlb_uop_0_inst : will_fire_store_commit_0 ? _GEN_2[stq_execute_head] : will_fire_load_wakeup_0 ? mem_ldq_wakeup_e_out_bits_uop_inst : 32'h0; // @[util.scala:106:23] assign dmem_req_0_bits_uop_debug_inst = _GEN_219 ? exe_tlb_uop_0_debug_inst : will_fire_store_commit_0 ? _GEN_3[stq_execute_head] : will_fire_load_wakeup_0 ? mem_ldq_wakeup_e_out_bits_uop_debug_inst : 32'h0; // @[util.scala:106:23] assign dmem_req_0_bits_uop_is_rvc = _GEN_219 ? exe_tlb_uop_0_is_rvc : will_fire_store_commit_0 ? _GEN_4[stq_execute_head] : will_fire_load_wakeup_0 & mem_ldq_wakeup_e_out_bits_uop_is_rvc; // @[util.scala:106:23] assign dmem_req_0_bits_uop_debug_pc = _GEN_219 ? exe_tlb_uop_0_debug_pc : will_fire_store_commit_0 ? _GEN_5[stq_execute_head] : will_fire_load_wakeup_0 ? mem_ldq_wakeup_e_out_bits_uop_debug_pc : 40'h0; // @[util.scala:106:23] assign dmem_req_0_bits_uop_iq_type = _GEN_219 ? exe_tlb_uop_0_iq_type : will_fire_store_commit_0 ? _GEN_6[stq_execute_head] : will_fire_load_wakeup_0 ? mem_ldq_wakeup_e_out_bits_uop_iq_type : 3'h0; // @[util.scala:106:23] assign dmem_req_0_bits_uop_fu_code = _GEN_219 ? exe_tlb_uop_0_fu_code : will_fire_store_commit_0 ? _GEN_7[stq_execute_head] : will_fire_load_wakeup_0 ? mem_ldq_wakeup_e_out_bits_uop_fu_code : 10'h0; // @[util.scala:106:23] assign dmem_req_0_bits_uop_ctrl_br_type = _GEN_219 ? exe_tlb_uop_0_ctrl_br_type : will_fire_store_commit_0 ? _GEN_8[stq_execute_head] : will_fire_load_wakeup_0 ? mem_ldq_wakeup_e_out_bits_uop_ctrl_br_type : 4'h0; // @[util.scala:106:23] assign dmem_req_0_bits_uop_ctrl_op1_sel = _GEN_219 ? exe_tlb_uop_0_ctrl_op1_sel : will_fire_store_commit_0 ? _GEN_9[stq_execute_head] : will_fire_load_wakeup_0 ? mem_ldq_wakeup_e_out_bits_uop_ctrl_op1_sel : 2'h0; // @[util.scala:106:23] assign dmem_req_0_bits_uop_ctrl_op2_sel = _GEN_219 ? exe_tlb_uop_0_ctrl_op2_sel : will_fire_store_commit_0 ? _GEN_10[stq_execute_head] : will_fire_load_wakeup_0 ? mem_ldq_wakeup_e_out_bits_uop_ctrl_op2_sel : 3'h0; // @[util.scala:106:23] assign dmem_req_0_bits_uop_ctrl_imm_sel = _GEN_219 ? exe_tlb_uop_0_ctrl_imm_sel : will_fire_store_commit_0 ? _GEN_11[stq_execute_head] : will_fire_load_wakeup_0 ? mem_ldq_wakeup_e_out_bits_uop_ctrl_imm_sel : 3'h0; // @[util.scala:106:23] assign dmem_req_0_bits_uop_ctrl_op_fcn = _GEN_219 ? exe_tlb_uop_0_ctrl_op_fcn : will_fire_store_commit_0 ? _GEN_12[stq_execute_head] : will_fire_load_wakeup_0 ? mem_ldq_wakeup_e_out_bits_uop_ctrl_op_fcn : 5'h0; // @[util.scala:106:23] assign dmem_req_0_bits_uop_ctrl_fcn_dw = _GEN_219 ? exe_tlb_uop_0_ctrl_fcn_dw : will_fire_store_commit_0 ? _GEN_13[stq_execute_head] : will_fire_load_wakeup_0 & mem_ldq_wakeup_e_out_bits_uop_ctrl_fcn_dw; // @[util.scala:106:23] assign dmem_req_0_bits_uop_ctrl_csr_cmd = _GEN_219 ? exe_tlb_uop_0_ctrl_csr_cmd : will_fire_store_commit_0 ? _GEN_14[stq_execute_head] : will_fire_load_wakeup_0 ? mem_ldq_wakeup_e_out_bits_uop_ctrl_csr_cmd : 3'h0; // @[util.scala:106:23] assign dmem_req_0_bits_uop_ctrl_is_load = _GEN_219 ? exe_tlb_uop_0_ctrl_is_load : will_fire_store_commit_0 ? _GEN_15[stq_execute_head] : will_fire_load_wakeup_0 & mem_ldq_wakeup_e_out_bits_uop_ctrl_is_load; // @[util.scala:106:23] assign dmem_req_0_bits_uop_ctrl_is_sta = _GEN_219 ? exe_tlb_uop_0_ctrl_is_sta : will_fire_store_commit_0 ? _GEN_16[stq_execute_head] : will_fire_load_wakeup_0 & mem_ldq_wakeup_e_out_bits_uop_ctrl_is_sta; // @[util.scala:106:23] assign dmem_req_0_bits_uop_ctrl_is_std = _GEN_219 ? exe_tlb_uop_0_ctrl_is_std : will_fire_store_commit_0 ? _GEN_17[stq_execute_head] : will_fire_load_wakeup_0 & mem_ldq_wakeup_e_out_bits_uop_ctrl_is_std; // @[util.scala:106:23] assign dmem_req_0_bits_uop_iw_state = _GEN_219 ? exe_tlb_uop_0_iw_state : will_fire_store_commit_0 ? _GEN_18[stq_execute_head] : will_fire_load_wakeup_0 ? mem_ldq_wakeup_e_out_bits_uop_iw_state : 2'h0; // @[util.scala:106:23] assign dmem_req_0_bits_uop_iw_p1_poisoned = _GEN_219 ? exe_tlb_uop_0_iw_p1_poisoned : will_fire_store_commit_0 ? _GEN_19[stq_execute_head] : will_fire_load_wakeup_0 & mem_ldq_wakeup_e_out_bits_uop_iw_p1_poisoned; // @[util.scala:106:23] assign dmem_req_0_bits_uop_iw_p2_poisoned = _GEN_219 ? exe_tlb_uop_0_iw_p2_poisoned : will_fire_store_commit_0 ? _GEN_20[stq_execute_head] : will_fire_load_wakeup_0 & mem_ldq_wakeup_e_out_bits_uop_iw_p2_poisoned; // @[util.scala:106:23] assign dmem_req_0_bits_uop_is_br = _GEN_219 ? exe_tlb_uop_0_is_br : will_fire_store_commit_0 ? _GEN_21[stq_execute_head] : will_fire_load_wakeup_0 & mem_ldq_wakeup_e_out_bits_uop_is_br; // @[util.scala:106:23] assign dmem_req_0_bits_uop_is_jalr = _GEN_219 ? exe_tlb_uop_0_is_jalr : will_fire_store_commit_0 ? _GEN_22[stq_execute_head] : will_fire_load_wakeup_0 & mem_ldq_wakeup_e_out_bits_uop_is_jalr; // @[util.scala:106:23] assign dmem_req_0_bits_uop_is_jal = _GEN_219 ? exe_tlb_uop_0_is_jal : will_fire_store_commit_0 ? _GEN_23[stq_execute_head] : will_fire_load_wakeup_0 & mem_ldq_wakeup_e_out_bits_uop_is_jal; // @[util.scala:106:23] assign dmem_req_0_bits_uop_is_sfb = _GEN_219 ? exe_tlb_uop_0_is_sfb : will_fire_store_commit_0 ? _GEN_24[stq_execute_head] : will_fire_load_wakeup_0 & mem_ldq_wakeup_e_out_bits_uop_is_sfb; // @[util.scala:106:23] assign dmem_req_0_bits_uop_br_mask = _GEN_219 ? exe_tlb_uop_0_br_mask : will_fire_store_commit_0 ? _GEN_25[stq_execute_head] : will_fire_load_wakeup_0 ? _GEN_118[_ldq_wakeup_e_T_1] : 8'h0; // @[lsu.scala:218:29, :222:42, :263:49, :380:38, :381:38, :501:88, :750:22, :760:28, :767:39, :770:30, :774:43, :777:30, :781:45, :788:33, :795:44, :798:30] assign dmem_req_0_bits_uop_br_tag = _GEN_219 ? exe_tlb_uop_0_br_tag : will_fire_store_commit_0 ? _GEN_26[stq_execute_head] : will_fire_load_wakeup_0 ? mem_ldq_wakeup_e_out_bits_uop_br_tag : 3'h0; // @[util.scala:106:23] assign dmem_req_0_bits_uop_ftq_idx = _GEN_219 ? exe_tlb_uop_0_ftq_idx : will_fire_store_commit_0 ? _GEN_27[stq_execute_head] : will_fire_load_wakeup_0 ? mem_ldq_wakeup_e_out_bits_uop_ftq_idx : 4'h0; // @[util.scala:106:23] assign dmem_req_0_bits_uop_edge_inst = _GEN_219 ? exe_tlb_uop_0_edge_inst : will_fire_store_commit_0 ? _GEN_28[stq_execute_head] : will_fire_load_wakeup_0 & mem_ldq_wakeup_e_out_bits_uop_edge_inst; // @[util.scala:106:23] assign dmem_req_0_bits_uop_pc_lob = _GEN_219 ? exe_tlb_uop_0_pc_lob : will_fire_store_commit_0 ? _GEN_29[stq_execute_head] : will_fire_load_wakeup_0 ? mem_ldq_wakeup_e_out_bits_uop_pc_lob : 6'h0; // @[util.scala:106:23] assign dmem_req_0_bits_uop_taken = _GEN_219 ? exe_tlb_uop_0_taken : will_fire_store_commit_0 ? _GEN_30[stq_execute_head] : will_fire_load_wakeup_0 & mem_ldq_wakeup_e_out_bits_uop_taken; // @[util.scala:106:23] assign dmem_req_0_bits_uop_imm_packed = _GEN_219 ? exe_tlb_uop_0_imm_packed : will_fire_store_commit_0 ? _GEN_31[stq_execute_head] : will_fire_load_wakeup_0 ? mem_ldq_wakeup_e_out_bits_uop_imm_packed : 20'h0; // @[util.scala:106:23] assign dmem_req_0_bits_uop_csr_addr = _GEN_219 ? exe_tlb_uop_0_csr_addr : will_fire_store_commit_0 ? _GEN_32[stq_execute_head] : will_fire_load_wakeup_0 ? mem_ldq_wakeup_e_out_bits_uop_csr_addr : 12'h0; // @[util.scala:106:23] assign dmem_req_0_bits_uop_rob_idx = _GEN_219 ? exe_tlb_uop_0_rob_idx : will_fire_store_commit_0 ? _GEN_33[stq_execute_head] : will_fire_load_wakeup_0 ? mem_ldq_wakeup_e_out_bits_uop_rob_idx : 5'h0; // @[util.scala:106:23] assign dmem_req_0_bits_uop_ldq_idx = _GEN_219 ? exe_tlb_uop_0_ldq_idx : will_fire_store_commit_0 ? _GEN_34[stq_execute_head] : will_fire_load_wakeup_0 ? mem_ldq_wakeup_e_out_bits_uop_ldq_idx : 3'h0; // @[util.scala:106:23] assign dmem_req_0_bits_uop_stq_idx = _GEN_219 ? exe_tlb_uop_0_stq_idx : will_fire_store_commit_0 ? _GEN_35[stq_execute_head] : will_fire_load_wakeup_0 ? mem_ldq_wakeup_e_out_bits_uop_stq_idx : 3'h0; // @[util.scala:106:23] assign dmem_req_0_bits_uop_rxq_idx = _GEN_219 ? exe_tlb_uop_0_rxq_idx : will_fire_store_commit_0 ? _GEN_36[stq_execute_head] : will_fire_load_wakeup_0 ? mem_ldq_wakeup_e_out_bits_uop_rxq_idx : 2'h0; // @[util.scala:106:23] assign dmem_req_0_bits_uop_pdst = _GEN_219 ? exe_tlb_uop_0_pdst : will_fire_store_commit_0 ? _GEN_37[stq_execute_head] : will_fire_load_wakeup_0 ? mem_ldq_wakeup_e_out_bits_uop_pdst : 6'h0; // @[util.scala:106:23] assign dmem_req_0_bits_uop_prs1 = _GEN_219 ? exe_tlb_uop_0_prs1 : will_fire_store_commit_0 ? _GEN_38[stq_execute_head] : will_fire_load_wakeup_0 ? mem_ldq_wakeup_e_out_bits_uop_prs1 : 6'h0; // @[util.scala:106:23] assign dmem_req_0_bits_uop_prs2 = _GEN_219 ? exe_tlb_uop_0_prs2 : will_fire_store_commit_0 ? _GEN_39[stq_execute_head] : will_fire_load_wakeup_0 ? mem_ldq_wakeup_e_out_bits_uop_prs2 : 6'h0; // @[util.scala:106:23] assign dmem_req_0_bits_uop_prs3 = _GEN_219 ? exe_tlb_uop_0_prs3 : will_fire_store_commit_0 ? _GEN_40[stq_execute_head] : will_fire_load_wakeup_0 ? mem_ldq_wakeup_e_out_bits_uop_prs3 : 6'h0; // @[util.scala:106:23] assign dmem_req_0_bits_uop_ppred = _GEN_219 ? exe_tlb_uop_0_ppred : will_fire_store_commit_0 ? _GEN_41[stq_execute_head] : 4'h0; // @[lsu.scala:218:29, :222:42, :263:49, :380:38, :750:22, :767:39, :770:30, :774:43, :777:30, :781:45, :788:33, :795:44] assign dmem_req_0_bits_uop_prs1_busy = _GEN_219 ? exe_tlb_uop_0_prs1_busy : will_fire_store_commit_0 ? _GEN_42[stq_execute_head] : will_fire_load_wakeup_0 & mem_ldq_wakeup_e_out_bits_uop_prs1_busy; // @[util.scala:106:23] assign dmem_req_0_bits_uop_prs2_busy = _GEN_219 ? exe_tlb_uop_0_prs2_busy : will_fire_store_commit_0 ? _GEN_43[stq_execute_head] : will_fire_load_wakeup_0 & mem_ldq_wakeup_e_out_bits_uop_prs2_busy; // @[util.scala:106:23] assign dmem_req_0_bits_uop_prs3_busy = _GEN_219 ? exe_tlb_uop_0_prs3_busy : will_fire_store_commit_0 ? _GEN_44[stq_execute_head] : will_fire_load_wakeup_0 & mem_ldq_wakeup_e_out_bits_uop_prs3_busy; // @[util.scala:106:23] assign dmem_req_0_bits_uop_ppred_busy = _GEN_219 ? exe_tlb_uop_0_ppred_busy : will_fire_store_commit_0 & _GEN_45[stq_execute_head]; // @[lsu.scala:218:29, :222:42, :263:49, :380:38, :750:22, :767:39, :770:30, :774:43, :777:30, :781:45, :788:33, :795:44] assign dmem_req_0_bits_uop_stale_pdst = _GEN_219 ? exe_tlb_uop_0_stale_pdst : will_fire_store_commit_0 ? _GEN_46[stq_execute_head] : will_fire_load_wakeup_0 ? mem_ldq_wakeup_e_out_bits_uop_stale_pdst : 6'h0; // @[util.scala:106:23] assign dmem_req_0_bits_uop_exception = _GEN_219 ? exe_tlb_uop_0_exception : will_fire_store_commit_0 ? _GEN_48 : will_fire_load_wakeup_0 & mem_ldq_wakeup_e_out_bits_uop_exception; // @[util.scala:106:23] assign dmem_req_0_bits_uop_exc_cause = _GEN_219 ? exe_tlb_uop_0_exc_cause : will_fire_store_commit_0 ? _GEN_49[stq_execute_head] : will_fire_load_wakeup_0 ? mem_ldq_wakeup_e_out_bits_uop_exc_cause : 64'h0; // @[util.scala:106:23] assign dmem_req_0_bits_uop_bypassable = _GEN_219 ? exe_tlb_uop_0_bypassable : will_fire_store_commit_0 ? _GEN_50[stq_execute_head] : will_fire_load_wakeup_0 & mem_ldq_wakeup_e_out_bits_uop_bypassable; // @[util.scala:106:23] assign dmem_req_0_bits_uop_is_fence = _GEN_219 ? exe_tlb_uop_0_is_fence : will_fire_store_commit_0 ? _GEN_55 : will_fire_load_wakeup_0 & mem_ldq_wakeup_e_out_bits_uop_is_fence; // @[util.scala:106:23] assign dmem_req_0_bits_uop_is_fencei = _GEN_219 ? exe_tlb_uop_0_is_fencei : will_fire_store_commit_0 ? _GEN_56[stq_execute_head] : will_fire_load_wakeup_0 & mem_ldq_wakeup_e_out_bits_uop_is_fencei; // @[util.scala:106:23] assign dmem_req_0_bits_uop_is_amo = _GEN_219 ? exe_tlb_uop_0_is_amo : will_fire_store_commit_0 ? _GEN_58 : will_fire_load_wakeup_0 & mem_ldq_wakeup_e_out_bits_uop_is_amo; // @[util.scala:106:23] assign dmem_req_0_bits_uop_uses_ldq = _GEN_219 ? exe_tlb_uop_0_uses_ldq : will_fire_store_commit_0 ? _GEN_59[stq_execute_head] : will_fire_load_wakeup_0 & mem_ldq_wakeup_e_out_bits_uop_uses_ldq; // @[util.scala:106:23] assign dmem_req_0_bits_uop_uses_stq = _GEN_219 ? exe_tlb_uop_0_uses_stq : will_fire_store_commit_0 ? _GEN_60[stq_execute_head] : will_fire_load_wakeup_0 & mem_ldq_wakeup_e_out_bits_uop_uses_stq; // @[util.scala:106:23] assign dmem_req_0_bits_uop_is_sys_pc2epc = _GEN_219 ? exe_tlb_uop_0_is_sys_pc2epc : will_fire_store_commit_0 ? _GEN_61[stq_execute_head] : will_fire_load_wakeup_0 & mem_ldq_wakeup_e_out_bits_uop_is_sys_pc2epc; // @[util.scala:106:23] assign dmem_req_0_bits_uop_is_unique = _GEN_219 ? exe_tlb_uop_0_is_unique : will_fire_store_commit_0 ? _GEN_62[stq_execute_head] : will_fire_load_wakeup_0 & mem_ldq_wakeup_e_out_bits_uop_is_unique; // @[util.scala:106:23] assign dmem_req_0_bits_uop_flush_on_commit = _GEN_219 ? exe_tlb_uop_0_flush_on_commit : will_fire_store_commit_0 ? _GEN_63[stq_execute_head] : will_fire_load_wakeup_0 & mem_ldq_wakeup_e_out_bits_uop_flush_on_commit; // @[util.scala:106:23] assign dmem_req_0_bits_uop_ldst_is_rs1 = _GEN_219 ? exe_tlb_uop_0_ldst_is_rs1 : will_fire_store_commit_0 ? _GEN_64[stq_execute_head] : will_fire_load_wakeup_0 & mem_ldq_wakeup_e_out_bits_uop_ldst_is_rs1; // @[util.scala:106:23] assign dmem_req_0_bits_uop_ldst = _GEN_219 ? exe_tlb_uop_0_ldst : will_fire_store_commit_0 ? _GEN_65[stq_execute_head] : will_fire_load_wakeup_0 ? mem_ldq_wakeup_e_out_bits_uop_ldst : 6'h0; // @[util.scala:106:23] assign dmem_req_0_bits_uop_lrs1 = _GEN_219 ? exe_tlb_uop_0_lrs1 : will_fire_store_commit_0 ? _GEN_66[stq_execute_head] : will_fire_load_wakeup_0 ? mem_ldq_wakeup_e_out_bits_uop_lrs1 : 6'h0; // @[util.scala:106:23] assign dmem_req_0_bits_uop_lrs2 = _GEN_219 ? exe_tlb_uop_0_lrs2 : will_fire_store_commit_0 ? _GEN_67[stq_execute_head] : will_fire_load_wakeup_0 ? mem_ldq_wakeup_e_out_bits_uop_lrs2 : 6'h0; // @[util.scala:106:23] assign dmem_req_0_bits_uop_lrs3 = _GEN_219 ? exe_tlb_uop_0_lrs3 : will_fire_store_commit_0 ? _GEN_68[stq_execute_head] : will_fire_load_wakeup_0 ? mem_ldq_wakeup_e_out_bits_uop_lrs3 : 6'h0; // @[util.scala:106:23] assign dmem_req_0_bits_uop_ldst_val = _GEN_219 ? exe_tlb_uop_0_ldst_val : will_fire_store_commit_0 ? _GEN_69[stq_execute_head] : will_fire_load_wakeup_0 & mem_ldq_wakeup_e_out_bits_uop_ldst_val; // @[util.scala:106:23] assign dmem_req_0_bits_uop_dst_rtype = _GEN_219 ? exe_tlb_uop_0_dst_rtype : will_fire_store_commit_0 ? _GEN_70[stq_execute_head] : will_fire_load_wakeup_0 ? mem_ldq_wakeup_e_out_bits_uop_dst_rtype : 2'h2; // @[util.scala:106:23] assign dmem_req_0_bits_uop_lrs1_rtype = _GEN_219 ? exe_tlb_uop_0_lrs1_rtype : will_fire_store_commit_0 ? _GEN_71[stq_execute_head] : will_fire_load_wakeup_0 ? mem_ldq_wakeup_e_out_bits_uop_lrs1_rtype : 2'h0; // @[util.scala:106:23] assign dmem_req_0_bits_uop_lrs2_rtype = _GEN_219 ? exe_tlb_uop_0_lrs2_rtype : will_fire_store_commit_0 ? _GEN_72[stq_execute_head] : will_fire_load_wakeup_0 ? mem_ldq_wakeup_e_out_bits_uop_lrs2_rtype : 2'h0; // @[util.scala:106:23] assign dmem_req_0_bits_uop_frs3_en = _GEN_219 ? exe_tlb_uop_0_frs3_en : will_fire_store_commit_0 ? _GEN_73[stq_execute_head] : will_fire_load_wakeup_0 & mem_ldq_wakeup_e_out_bits_uop_frs3_en; // @[util.scala:106:23] assign dmem_req_0_bits_uop_fp_val = _GEN_219 ? exe_tlb_uop_0_fp_val : will_fire_store_commit_0 ? _GEN_74[stq_execute_head] : will_fire_load_wakeup_0 & mem_ldq_wakeup_e_out_bits_uop_fp_val; // @[util.scala:106:23] assign dmem_req_0_bits_uop_fp_single = _GEN_219 ? exe_tlb_uop_0_fp_single : will_fire_store_commit_0 ? _GEN_75[stq_execute_head] : will_fire_load_wakeup_0 & mem_ldq_wakeup_e_out_bits_uop_fp_single; // @[util.scala:106:23] assign dmem_req_0_bits_uop_xcpt_pf_if = _GEN_219 ? exe_tlb_uop_0_xcpt_pf_if : will_fire_store_commit_0 ? _GEN_76[stq_execute_head] : will_fire_load_wakeup_0 & mem_ldq_wakeup_e_out_bits_uop_xcpt_pf_if; // @[util.scala:106:23] assign dmem_req_0_bits_uop_xcpt_ae_if = _GEN_219 ? exe_tlb_uop_0_xcpt_ae_if : will_fire_store_commit_0 ? _GEN_77[stq_execute_head] : will_fire_load_wakeup_0 & mem_ldq_wakeup_e_out_bits_uop_xcpt_ae_if; // @[util.scala:106:23] assign dmem_req_0_bits_uop_xcpt_ma_if = _GEN_219 ? exe_tlb_uop_0_xcpt_ma_if : will_fire_store_commit_0 ? _GEN_78[stq_execute_head] : will_fire_load_wakeup_0 & mem_ldq_wakeup_e_out_bits_uop_xcpt_ma_if; // @[util.scala:106:23] assign dmem_req_0_bits_uop_bp_debug_if = _GEN_219 ? exe_tlb_uop_0_bp_debug_if : will_fire_store_commit_0 ? _GEN_79[stq_execute_head] : will_fire_load_wakeup_0 & mem_ldq_wakeup_e_out_bits_uop_bp_debug_if; // @[util.scala:106:23] assign dmem_req_0_bits_uop_bp_xcpt_if = _GEN_219 ? exe_tlb_uop_0_bp_xcpt_if : will_fire_store_commit_0 ? _GEN_80[stq_execute_head] : will_fire_load_wakeup_0 & mem_ldq_wakeup_e_out_bits_uop_bp_xcpt_if; // @[util.scala:106:23] assign dmem_req_0_bits_uop_debug_fsrc = _GEN_219 ? exe_tlb_uop_0_debug_fsrc : will_fire_store_commit_0 ? _GEN_81[stq_execute_head] : will_fire_load_wakeup_0 ? mem_ldq_wakeup_e_out_bits_uop_debug_fsrc : 2'h0; // @[util.scala:106:23] assign dmem_req_0_bits_uop_debug_tsrc = _GEN_219 ? exe_tlb_uop_0_debug_tsrc : will_fire_store_commit_0 ? _GEN_82[stq_execute_head] : will_fire_load_wakeup_0 ? mem_ldq_wakeup_e_out_bits_uop_debug_tsrc : 2'h0; // @[util.scala:106:23] assign s0_executing_loads_0 = will_fire_load_incoming_0 ? ldq_incoming_idx_0 == 3'h0 & dmem_req_fire_0 : will_fire_load_retry_0 ? _GEN_210 & dmem_req_fire_0 : ~will_fire_store_commit_0 & will_fire_load_wakeup_0 & _GEN_203 & dmem_req_fire_0; // @[lsu.scala:218:29, :263:49, :370:38, :378:38, :380:38, :381:38, :569:49, :573:49, :755:36, :767:39, :772:47, :774:43, :779:41, :781:45, :795:44, :800:42] assign s0_executing_loads_1 = will_fire_load_incoming_0 ? ldq_incoming_idx_0 == 3'h1 & dmem_req_fire_0 : will_fire_load_retry_0 ? _GEN_211 & dmem_req_fire_0 : ~will_fire_store_commit_0 & will_fire_load_wakeup_0 & _GEN_204 & dmem_req_fire_0; // @[lsu.scala:218:29, :263:49, :370:38, :378:38, :380:38, :381:38, :569:49, :573:49, :755:36, :767:39, :772:47, :774:43, :779:41, :781:45, :795:44, :800:42] assign s0_executing_loads_2 = will_fire_load_incoming_0 ? ldq_incoming_idx_0 == 3'h2 & dmem_req_fire_0 : will_fire_load_retry_0 ? _GEN_212 & dmem_req_fire_0 : ~will_fire_store_commit_0 & will_fire_load_wakeup_0 & _GEN_205 & dmem_req_fire_0; // @[lsu.scala:218:29, :263:49, :370:38, :378:38, :380:38, :381:38, :569:49, :573:49, :755:36, :767:39, :772:47, :774:43, :779:41, :781:45, :795:44, :800:42] assign s0_executing_loads_3 = will_fire_load_incoming_0 ? ldq_incoming_idx_0 == 3'h3 & dmem_req_fire_0 : will_fire_load_retry_0 ? _GEN_213 & dmem_req_fire_0 : ~will_fire_store_commit_0 & will_fire_load_wakeup_0 & _GEN_206 & dmem_req_fire_0; // @[lsu.scala:218:29, :263:49, :370:38, :378:38, :380:38, :381:38, :569:49, :573:49, :755:36, :767:39, :772:47, :774:43, :779:41, :781:45, :795:44, :800:42] assign s0_executing_loads_4 = will_fire_load_incoming_0 ? ldq_incoming_idx_0 == 3'h4 & dmem_req_fire_0 : will_fire_load_retry_0 ? _GEN_214 & dmem_req_fire_0 : ~will_fire_store_commit_0 & will_fire_load_wakeup_0 & _GEN_207 & dmem_req_fire_0; // @[lsu.scala:218:29, :263:49, :370:38, :378:38, :380:38, :381:38, :569:49, :573:49, :755:36, :767:39, :772:47, :774:43, :779:41, :781:45, :795:44, :800:42] assign s0_executing_loads_5 = will_fire_load_incoming_0 ? ldq_incoming_idx_0 == 3'h5 & dmem_req_fire_0 : will_fire_load_retry_0 ? _GEN_215 & dmem_req_fire_0 : ~will_fire_store_commit_0 & will_fire_load_wakeup_0 & _GEN_208 & dmem_req_fire_0; // @[lsu.scala:218:29, :263:49, :370:38, :378:38, :380:38, :381:38, :569:49, :573:49, :755:36, :767:39, :772:47, :774:43, :779:41, :781:45, :795:44, :800:42] assign s0_executing_loads_6 = will_fire_load_incoming_0 ? ldq_incoming_idx_0 == 3'h6 & dmem_req_fire_0 : will_fire_load_retry_0 ? _GEN_216 & dmem_req_fire_0 : ~will_fire_store_commit_0 & will_fire_load_wakeup_0 & _GEN_209 & dmem_req_fire_0; // @[lsu.scala:218:29, :263:49, :370:38, :378:38, :380:38, :381:38, :569:49, :573:49, :755:36, :767:39, :772:47, :774:43, :779:41, :781:45, :795:44, :800:42] assign s0_executing_loads_7 = will_fire_load_incoming_0 ? (&ldq_incoming_idx_0) & dmem_req_fire_0 : will_fire_load_retry_0 ? (&ldq_retry_idx) & dmem_req_fire_0 : ~will_fire_store_commit_0 & will_fire_load_wakeup_0 & (&ldq_wakeup_idx) & dmem_req_fire_0; // @[lsu.scala:218:29, :263:49, :370:38, :378:38, :380:38, :381:38, :414:30, :429:31, :569:49, :573:49, :755:36, :767:39, :772:47, :774:43, :779:41, :781:45, :795:44, :800:42] wire _dmem_req_0_valid_T_6 = ~io_hellacache_s1_kill_0; // @[lsu.scala:201:7, :806:42] wire _dmem_req_0_valid_T_9 = _dmem_req_0_valid_T_6; // @[lsu.scala:806:{42,65}] wire _dmem_req_0_valid_T_7 = ~exe_tlb_miss_0; // @[lsu.scala:263:49, :768:33, :806:69] wire _GEN_220 = will_fire_store_commit_0 \| will_fire_load_wakeup_0; // @[lsu.scala:243:34, :380:38, :381:38, :781:45, :795:44, :803:47] assign dmem_req_0_valid = will_fire_load_incoming_0 ? _dmem_req_0_valid_T_2 : will_fire_load_retry_0 ? _dmem_req_0_valid_T_5 : _GEN_220 \| (will_fire_hella_incoming_0 ? _dmem_req_0_valid_T_9 : will_fire_hella_wakeup_0); // @[lsu.scala:243:34, :370:38, :375:38, :376:38, :378:38, :750:22, :767:39, :768:{30,50}, :774:43, :775:{30,50}, :781:45, :782:33, :795:44, :796:30, :803:47, :806:{39,65}, :820:5] assign dmem_req_0_bits_addr = will_fire_load_incoming_0 \| will_fire_load_retry_0 ? _GEN_217 : will_fire_store_commit_0 ? _GEN_84[stq_execute_head] : will_fire_load_wakeup_0 ? mem_ldq_wakeup_e_out_bits_addr_bits : will_fire_hella_incoming_0 ? _GEN_217 : will_fire_hella_wakeup_0 ? {8'h0, hella_paddr} : 40'h0; // @[util.scala:106:23] wire [7:0] _dmem_req_0_bits_data_T_31 = hella_data_data[7:0]; // @[AMOALU.scala:29:69] wire [15:0] _dmem_req_0_bits_data_T_32 = {2{_dmem_req_0_bits_data_T_31}}; // @[AMOALU.scala:29:{32,69}] wire [31:0] _dmem_req_0_bits_data_T_33 = {2{_dmem_req_0_bits_data_T_32}}; // @[AMOALU.scala:29:32] wire [63:0] _dmem_req_0_bits_data_T_34 = {2{_dmem_req_0_bits_data_T_33}}; // @[AMOALU.scala:29:32] wire [15:0] _dmem_req_0_bits_data_T_36 = hella_data_data[15:0]; // @[AMOALU.scala:29:69] wire [31:0] _dmem_req_0_bits_data_T_37 = {2{_dmem_req_0_bits_data_T_36}}; // @[AMOALU.scala:29:{32,69}] wire [63:0] _dmem_req_0_bits_data_T_38 = {2{_dmem_req_0_bits_data_T_37}}; // @[AMOALU.scala:29:32] wire [31:0] _dmem_req_0_bits_data_T_40 = hella_data_data[31:0]; // @[AMOALU.scala:29:69] wire [63:0] _dmem_req_0_bits_data_T_41 = {2{_dmem_req_0_bits_data_T_40}}; // @[AMOALU.scala:29:{32,69}] wire [63:0] _dmem_req_0_bits_data_T_43 = _dmem_req_0_bits_data_T_42; // @[AMOALU.scala:29:13] wire [63:0] _dmem_req_0_bits_data_T_44 = _dmem_req_0_bits_data_T_43; // @[AMOALU.scala:29:13] assign dmem_req_0_bits_data = _GEN_219 ? 64'h0 : will_fire_store_commit_0 ? _dmem_req_0_bits_data_T_14 : will_fire_load_wakeup_0 \| will_fire_hella_incoming_0 \| ~will_fire_hella_wakeup_0 ? 64'h0 : _dmem_req_0_bits_data_T_44; // @[AMOALU.scala:29:13] assign dmem_req_0_bits_uop_mem_cmd = _GEN_219 ? exe_tlb_uop_0_mem_cmd : will_fire_store_commit_0 ? _GEN_51[stq_execute_head] : will_fire_load_wakeup_0 ? mem_ldq_wakeup_e_out_bits_uop_mem_cmd : 5'h0; // @[util.scala:106:23] assign dmem_req_0_bits_uop_mem_size = _GEN_219 ? exe_tlb_uop_0_mem_size : will_fire_store_commit_0 ? dmem_req_0_bits_data_size : will_fire_load_wakeup_0 ? mem_ldq_wakeup_e_out_bits_uop_mem_size : {2{will_fire_hella_incoming_0 \| will_fire_hella_wakeup_0}}; // @[AMOALU.scala:11:18] assign dmem_req_0_bits_uop_mem_signed = _GEN_219 ? exe_tlb_uop_0_mem_signed : will_fire_store_commit_0 ? _GEN_53[stq_execute_head] : will_fire_load_wakeup_0 & mem_ldq_wakeup_e_out_bits_uop_mem_signed; // @[util.scala:106:23] assign dmem_req_0_bits_is_hella = ~(_GEN_219 \| will_fire_store_commit_0 \| will_fire_load_wakeup_0) & (will_fire_hella_incoming_0 \| will_fire_hella_wakeup_0); // @[lsu.scala:218:29, :375:38, :376:38, :380:38, :381:38, :750:22, :763:31, :767:39, :774:43, :781:45, :795:44, :803:47, :815:39, :820:5] wire _T_146 = will_fire_load_incoming_0 \| will_fire_load_retry_0; // @[lsu.scala:370:38, :378:38, :836:38] wire [2:0] ldq_idx = will_fire_load_incoming_0 ? ldq_incoming_idx_0 : ldq_retry_idx; // @[lsu.scala:263:49, :370:38, :414:30, :838:24] wire [39:0] _GEN_221 = exe_tlb_miss_0 ? exe_tlb_vaddr_0 : _GEN_217; // @[lsu.scala:263:49, :769:30, :840:51] wire [39:0] _ldq_bits_addr_bits_T; // @[lsu.scala:840:51] assign _ldq_bits_addr_bits_T = _GEN_221; // @[lsu.scala:840:51] wire [39:0] _stq_bits_addr_bits_T; // @[lsu.scala:855:42] assign _stq_bits_addr_bits_T = _GEN_221; // @[lsu.scala:840:51, :855:42] wire _ldq_bits_addr_is_uncacheable_T = ~exe_tlb_miss_0; // @[lsu.scala:263:49, :768:33, :843:74] wire _ldq_bits_addr_is_uncacheable_T_1 = exe_tlb_uncacheable_0 & _ldq_bits_addr_is_uncacheable_T; // @[lsu.scala:263:49, :843:{71,74}] wire _T_163 = _T_162 \| will_fire_sta_retry_0; // @[lsu.scala:379:38, :661:56, :849:67] wire [2:0] stq_idx = _stq_idx_T ? stq_incoming_idx_0 : stq_retry_idx; // @[lsu.scala:263:49, :421:30, :851:{24,51}] wire _stq_bits_addr_valid_T = ~pf_st_0; // @[lsu.scala:263:49, :854:39] wire _io_core_fp_stdata_ready_T = ~will_fire_std_incoming_0; // @[lsu.scala:373:38, :867:34] wire _io_core_fp_stdata_ready_T_1 = ~will_fire_stad_incoming_0; // @[lsu.scala:371:38, :867:64] assign _io_core_fp_stdata_ready_T_2 = _io_core_fp_stdata_ready_T & _io_core_fp_stdata_ready_T_1; // @[lsu.scala:867:{34,61,64}] assign io_core_fp_stdata_ready_0 = _io_core_fp_stdata_ready_T_2; // @[lsu.scala:201:7, :867:61] wire _GEN_222 = io_core_fp_stdata_ready_0 & io_core_fp_stdata_valid_0; // @[Decoupled.scala:51:35] wire _fp_stdata_fire_T; // @[Decoupled.scala:51:35] assign _fp_stdata_fire_T = _GEN_222; // @[Decoupled.scala:51:35] wire will_fire_stdf_incoming; // @[Decoupled.scala:51:35] assign will_fire_stdf_incoming = _GEN_222; // @[Decoupled.scala:51:35] wire fp_stdata_fire = _fp_stdata_fire_T; // @[Decoupled.scala:51:35] wire _T_177 = will_fire_std_incoming_0 \| will_fire_stad_incoming_0; // @[lsu.scala:371:38, :373:38, :869:37] wire _sidx_T; // @[lsu.scala:871:48] assign _sidx_T = _T_177; // @[lsu.scala:869:37, :871:48] wire _stq_bits_data_bits_T; // @[lsu.scala:875:66] assign _stq_bits_data_bits_T = _T_177; // @[lsu.scala:869:37, :875:66] wire _T_178 = _T_177 \| fp_stdata_fire; // @[lsu.scala:868:49, :869:{37,67}] wire [2:0] sidx = _sidx_T ? stq_incoming_idx_0 : io_core_fp_stdata_bits_uop_stq_idx_0; // @[lsu.scala:201:7, :263:49, :871:{21,48}] wire [63:0] _stq_bits_data_bits_T_1 = _stq_bits_data_bits_T ? exe_req_0_bits_data : io_core_fp_stdata_bits_data_0; // @[lsu.scala:201:7, :383:25, :875:{39,66}] wire [7:0] _exe_req_killed_T = io_core_brupdate_b1_mispredict_mask_0 & exe_req_0_bits_uop_br_mask; // @[util.scala:118:51] wire _exe_req_killed_T_1 = \|_exe_req_killed_T; // @[util.scala:118:{51,59}] wire exe_req_killed_0 = _exe_req_killed_T_1; // @[util.scala:118:59] wire [7:0] _stdf_killed_T = io_core_brupdate_b1_mispredict_mask_0 & io_core_fp_stdata_bits_uop_br_mask_0; // @[util.scala:118:51] wire stdf_killed = \|_stdf_killed_T; // @[util.scala:118:{51,59}] wire _fired_load_incoming_T = ~exe_req_killed_0; // @[lsu.scala:263:49, :895:82] wire _fired_load_incoming_T_1 = will_fire_load_incoming_0 & _fired_load_incoming_T; // @[lsu.scala:370:38, :895:{79,82}] reg fired_load_incoming_REG; // @[lsu.scala:895:51] wire fired_load_incoming_0 = fired_load_incoming_REG; // @[lsu.scala:263:49, :895:51] wire _io_core_spec_ld_wakeup_0_valid_T = fired_load_incoming_0; // @[lsu.scala:263:49, :1259:69] wire _fired_stad_incoming_T = ~exe_req_killed_0; // @[lsu.scala:263:49, :895:82, :896:82] wire _fired_stad_incoming_T_1 = will_fire_stad_incoming_0 & _fired_stad_incoming_T; // @[lsu.scala:371:38, :896:{79,82}] reg fired_stad_incoming_REG; // @[lsu.scala:896:51] wire fired_stad_incoming_0 = fired_stad_incoming_REG; // @[lsu.scala:263:49, :896:51] wire _fired_sta_incoming_T = ~exe_req_killed_0; // @[lsu.scala:263:49, :895:82, :897:82] wire _fired_sta_incoming_T_1 = will_fire_sta_incoming_0 & _fired_sta_incoming_T; // @[lsu.scala:372:38, :897:{79,82}] reg fired_sta_incoming_REG; // @[lsu.scala:897:51] wire fired_sta_incoming_0 = fired_sta_incoming_REG; // @[lsu.scala:263:49, :897:51] wire _fired_std_incoming_T = ~exe_req_killed_0; // @[lsu.scala:263:49, :895:82, :898:82] wire _fired_std_incoming_T_1 = will_fire_std_incoming_0 & _fired_std_incoming_T; // @[lsu.scala:373:38, :898:{79,82}] reg fired_std_incoming_REG; // @[lsu.scala:898:51] wire fired_std_incoming_0 = fired_std_incoming_REG; // @[lsu.scala:263:49, :898:51] wire _fired_stdf_incoming_T = ~stdf_killed; // @[util.scala:118:59] wire _fired_stdf_incoming_T_1 = will_fire_stdf_incoming & _fired_stdf_incoming_T; // @[Decoupled.scala:51:35] reg fired_stdf_incoming; // @[lsu.scala:899:37] reg fired_sfence_0; // @[lsu.scala:900:37] reg fired_release_0; // @[lsu.scala:901:37] wire do_release_search_0 = fired_release_0; // @[lsu.scala:263:49, :901:37] wire lcam_is_release_0 = fired_release_0; // @[lsu.scala:263:49, :901:37] wire [7:0] _GEN_223 = io_core_brupdate_b1_mispredict_mask_0 & _GEN_118[_ldq_retry_e_T_1]; // @[util.scala:118:51] wire [7:0] _fired_load_retry_T; // @[util.scala:118:51] assign _fired_load_retry_T = _GEN_223; // @[util.scala:118:51] wire [7:0] _mem_ldq_retry_e_out_valid_T; // @[util.scala:118:51] assign _mem_ldq_retry_e_out_valid_T = _GEN_223; // @[util.scala:118:51] wire _fired_load_retry_T_1 = \|_fired_load_retry_T; // @[util.scala:118:{51,59}] wire _fired_load_retry_T_2 = ~_fired_load_retry_T_1; // @[util.scala:118:59] wire _fired_load_retry_T_3 = will_fire_load_retry_0 & _fired_load_retry_T_2; // @[lsu.scala:378:38, :902:{79,82}] reg fired_load_retry_REG; // @[lsu.scala:902:51] wire fired_load_retry_0 = fired_load_retry_REG; // @[lsu.scala:263:49, :902:51] wire [7:0] _GEN_224 = io_core_brupdate_b1_mispredict_mask_0 & _GEN_25[_stq_retry_e_T_1]; // @[util.scala:118:51] wire [7:0] _fired_sta_retry_T; // @[util.scala:118:51] assign _fired_sta_retry_T = _GEN_224; // @[util.scala:118:51] wire [7:0] _mem_stq_retry_e_out_valid_T; // @[util.scala:118:51] assign _mem_stq_retry_e_out_valid_T = _GEN_224; // @[util.scala:118:51] wire _fired_sta_retry_T_1 = \|_fired_sta_retry_T; // @[util.scala:118:{51,59}] wire _fired_sta_retry_T_2 = ~_fired_sta_retry_T_1; // @[util.scala:118:59] wire _fired_sta_retry_T_3 = will_fire_sta_retry_0 & _fired_sta_retry_T_2; // @[lsu.scala:379:38, :903:{79,82}] reg fired_sta_retry_REG; // @[lsu.scala:903:51] wire fired_sta_retry_0 = fired_sta_retry_REG; // @[lsu.scala:263:49, :903:51] reg fired_store_commit_0; // @[lsu.scala:904:37] wire [7:0] _GEN_225 = io_core_brupdate_b1_mispredict_mask_0 & _GEN_118[_ldq_wakeup_e_T_1]; // @[util.scala:118:51] wire [7:0] _fired_load_wakeup_T; // @[util.scala:118:51] assign _fired_load_wakeup_T = _GEN_225; // @[util.scala:118:51] wire [7:0] _mem_ldq_wakeup_e_out_valid_T; // @[util.scala:118:51] assign _mem_ldq_wakeup_e_out_valid_T = _GEN_225; // @[util.scala:118:51] wire _fired_load_wakeup_T_1 = \|_fired_load_wakeup_T; // @[util.scala:118:{51,59}] wire _fired_load_wakeup_T_2 = ~_fired_load_wakeup_T_1; // @[util.scala:118:59] wire _fired_load_wakeup_T_3 = will_fire_load_wakeup_0 & _fired_load_wakeup_T_2; // @[lsu.scala:381:38, :905:{79,82}] reg fired_load_wakeup_REG; // @[lsu.scala:905:51] wire fired_load_wakeup_0 = fired_load_wakeup_REG; // @[lsu.scala:263:49, :905:51] reg fired_hella_incoming_0; // @[lsu.scala:906:37] reg fired_hella_wakeup_0; // @[lsu.scala:907:37] wire [6:0] _mem_incoming_uop_WIRE_0_uopc = mem_incoming_uop_out_uopc; // @[util.scala:96:23] wire [31:0] _mem_incoming_uop_WIRE_0_inst = mem_incoming_uop_out_inst; // @[util.scala:96:23] wire [31:0] _mem_incoming_uop_WIRE_0_debug_inst = mem_incoming_uop_out_debug_inst; // @[util.scala:96:23] wire _mem_incoming_uop_WIRE_0_is_rvc = mem_incoming_uop_out_is_rvc; // @[util.scala:96:23] wire [39:0] _mem_incoming_uop_WIRE_0_debug_pc = mem_incoming_uop_out_debug_pc; // @[util.scala:96:23] wire [2:0] _mem_incoming_uop_WIRE_0_iq_type = mem_incoming_uop_out_iq_type; // @[util.scala:96:23] wire [9:0] _mem_incoming_uop_WIRE_0_fu_code = mem_incoming_uop_out_fu_code; // @[util.scala:96:23] wire [3:0] _mem_incoming_uop_WIRE_0_ctrl_br_type = mem_incoming_uop_out_ctrl_br_type; // @[util.scala:96:23] wire [1:0] _mem_incoming_uop_WIRE_0_ctrl_op1_sel = mem_incoming_uop_out_ctrl_op1_sel; // @[util.scala:96:23] wire [2:0] _mem_incoming_uop_WIRE_0_ctrl_op2_sel = mem_incoming_uop_out_ctrl_op2_sel; // @[util.scala:96:23] wire [2:0] _mem_incoming_uop_WIRE_0_ctrl_imm_sel = mem_incoming_uop_out_ctrl_imm_sel; // @[util.scala:96:23] wire [4:0] _mem_incoming_uop_WIRE_0_ctrl_op_fcn = mem_incoming_uop_out_ctrl_op_fcn; // @[util.scala:96:23] wire _mem_incoming_uop_WIRE_0_ctrl_fcn_dw = mem_incoming_uop_out_ctrl_fcn_dw; // @[util.scala:96:23] wire [2:0] _mem_incoming_uop_WIRE_0_ctrl_csr_cmd = mem_incoming_uop_out_ctrl_csr_cmd; // @[util.scala:96:23] wire _mem_incoming_uop_WIRE_0_ctrl_is_load = mem_incoming_uop_out_ctrl_is_load; // @[util.scala:96:23] wire _mem_incoming_uop_WIRE_0_ctrl_is_sta = mem_incoming_uop_out_ctrl_is_sta; // @[util.scala:96:23] wire _mem_incoming_uop_WIRE_0_ctrl_is_std = mem_incoming_uop_out_ctrl_is_std; // @[util.scala:96:23] wire [1:0] _mem_incoming_uop_WIRE_0_iw_state = mem_incoming_uop_out_iw_state; // @[util.scala:96:23] wire _mem_incoming_uop_WIRE_0_iw_p1_poisoned = mem_incoming_uop_out_iw_p1_poisoned; // @[util.scala:96:23] wire _mem_incoming_uop_WIRE_0_iw_p2_poisoned = mem_incoming_uop_out_iw_p2_poisoned; // @[util.scala:96:23] wire _mem_incoming_uop_WIRE_0_is_br = mem_incoming_uop_out_is_br; // @[util.scala:96:23] wire _mem_incoming_uop_WIRE_0_is_jalr = mem_incoming_uop_out_is_jalr; // @[util.scala:96:23] wire _mem_incoming_uop_WIRE_0_is_jal = mem_incoming_uop_out_is_jal; // @[util.scala:96:23] wire [7:0] _mem_incoming_uop_out_br_mask_T_1; // @[util.scala:85:25] wire _mem_incoming_uop_WIRE_0_is_sfb = mem_incoming_uop_out_is_sfb; // @[util.scala:96:23] wire [7:0] _mem_incoming_uop_WIRE_0_br_mask = mem_incoming_uop_out_br_mask; // @[util.scala:96:23] wire [2:0] _mem_incoming_uop_WIRE_0_br_tag = mem_incoming_uop_out_br_tag; // @[util.scala:96:23] wire [3:0] _mem_incoming_uop_WIRE_0_ftq_idx = mem_incoming_uop_out_ftq_idx; // @[util.scala:96:23] wire _mem_incoming_uop_WIRE_0_edge_inst = mem_incoming_uop_out_edge_inst; // @[util.scala:96:23] wire [5:0] _mem_incoming_uop_WIRE_0_pc_lob = mem_incoming_uop_out_pc_lob; // @[util.scala:96:23] wire _mem_incoming_uop_WIRE_0_taken = mem_incoming_uop_out_taken; // @[util.scala:96:23] wire [19:0] _mem_incoming_uop_WIRE_0_imm_packed = mem_incoming_uop_out_imm_packed; // @[util.scala:96:23] wire [11:0] _mem_incoming_uop_WIRE_0_csr_addr = mem_incoming_uop_out_csr_addr; // @[util.scala:96:23] wire [4:0] _mem_incoming_uop_WIRE_0_rob_idx = mem_incoming_uop_out_rob_idx; // @[util.scala:96:23] wire [2:0] _mem_incoming_uop_WIRE_0_ldq_idx = mem_incoming_uop_out_ldq_idx; // @[util.scala:96:23] wire [2:0] _mem_incoming_uop_WIRE_0_stq_idx = mem_incoming_uop_out_stq_idx; // @[util.scala:96:23] wire [1:0] _mem_incoming_uop_WIRE_0_rxq_idx = mem_incoming_uop_out_rxq_idx; // @[util.scala:96:23] wire [5:0] _mem_incoming_uop_WIRE_0_pdst = mem_incoming_uop_out_pdst; // @[util.scala:96:23] wire [5:0] _mem_incoming_uop_WIRE_0_prs1 = mem_incoming_uop_out_prs1; // @[util.scala:96:23] wire [5:0] _mem_incoming_uop_WIRE_0_prs2 = mem_incoming_uop_out_prs2; // @[util.scala:96:23] wire [5:0] _mem_incoming_uop_WIRE_0_prs3 = mem_incoming_uop_out_prs3; // @[util.scala:96:23] wire [3:0] _mem_incoming_uop_WIRE_0_ppred = mem_incoming_uop_out_ppred; // @[util.scala:96:23] wire _mem_incoming_uop_WIRE_0_prs1_busy = mem_incoming_uop_out_prs1_busy; // @[util.scala:96:23] wire _mem_incoming_uop_WIRE_0_prs2_busy = mem_incoming_uop_out_prs2_busy; // @[util.scala:96:23] wire _mem_incoming_uop_WIRE_0_prs3_busy = mem_incoming_uop_out_prs3_busy; // @[util.scala:96:23] wire _mem_incoming_uop_WIRE_0_ppred_busy = mem_incoming_uop_out_ppred_busy; // @[util.scala:96:23] wire [5:0] _mem_incoming_uop_WIRE_0_stale_pdst = mem_incoming_uop_out_stale_pdst; // @[util.scala:96:23] wire _mem_incoming_uop_WIRE_0_exception = mem_incoming_uop_out_exception; // @[util.scala:96:23] wire [63:0] _mem_incoming_uop_WIRE_0_exc_cause = mem_incoming_uop_out_exc_cause; // @[util.scala:96:23] wire _mem_incoming_uop_WIRE_0_bypassable = mem_incoming_uop_out_bypassable; // @[util.scala:96:23] wire [4:0] _mem_incoming_uop_WIRE_0_mem_cmd = mem_incoming_uop_out_mem_cmd; // @[util.scala:96:23] wire [1:0] _mem_incoming_uop_WIRE_0_mem_size = mem_incoming_uop_out_mem_size; // @[util.scala:96:23] wire _mem_incoming_uop_WIRE_0_mem_signed = mem_incoming_uop_out_mem_signed; // @[util.scala:96:23] wire _mem_incoming_uop_WIRE_0_is_fence = mem_incoming_uop_out_is_fence; // @[util.scala:96:23] wire _mem_incoming_uop_WIRE_0_is_fencei = mem_incoming_uop_out_is_fencei; // @[util.scala:96:23] wire _mem_incoming_uop_WIRE_0_is_amo = mem_incoming_uop_out_is_amo; // @[util.scala:96:23] wire _mem_incoming_uop_WIRE_0_uses_ldq = mem_incoming_uop_out_uses_ldq; // @[util.scala:96:23] wire _mem_incoming_uop_WIRE_0_uses_stq = mem_incoming_uop_out_uses_stq; // @[util.scala:96:23] wire _mem_incoming_uop_WIRE_0_is_sys_pc2epc = mem_incoming_uop_out_is_sys_pc2epc; // @[util.scala:96:23] wire _mem_incoming_uop_WIRE_0_is_unique = mem_incoming_uop_out_is_unique; // @[util.scala:96:23] wire _mem_incoming_uop_WIRE_0_flush_on_commit = mem_incoming_uop_out_flush_on_commit; // @[util.scala:96:23] wire _mem_incoming_uop_WIRE_0_ldst_is_rs1 = mem_incoming_uop_out_ldst_is_rs1; // @[util.scala:96:23] wire [5:0] _mem_incoming_uop_WIRE_0_ldst = mem_incoming_uop_out_ldst; // @[util.scala:96:23] wire [5:0] _mem_incoming_uop_WIRE_0_lrs1 = mem_incoming_uop_out_lrs1; // @[util.scala:96:23] wire [5:0] _mem_incoming_uop_WIRE_0_lrs2 = mem_incoming_uop_out_lrs2; // @[util.scala:96:23] wire [5:0] _mem_incoming_uop_WIRE_0_lrs3 = mem_incoming_uop_out_lrs3; // @[util.scala:96:23] wire _mem_incoming_uop_WIRE_0_ldst_val = mem_incoming_uop_out_ldst_val; // @[util.scala:96:23] wire [1:0] _mem_incoming_uop_WIRE_0_dst_rtype = mem_incoming_uop_out_dst_rtype; // @[util.scala:96:23] wire [1:0] _mem_incoming_uop_WIRE_0_lrs1_rtype = mem_incoming_uop_out_lrs1_rtype; // @[util.scala:96:23] wire [1:0] _mem_incoming_uop_WIRE_0_lrs2_rtype = mem_incoming_uop_out_lrs2_rtype; // @[util.scala:96:23] wire _mem_incoming_uop_WIRE_0_frs3_en = mem_incoming_uop_out_frs3_en; // @[util.scala:96:23] wire _mem_incoming_uop_WIRE_0_fp_val = mem_incoming_uop_out_fp_val; // @[util.scala:96:23] wire _mem_incoming_uop_WIRE_0_fp_single = mem_incoming_uop_out_fp_single; // @[util.scala:96:23] wire _mem_incoming_uop_WIRE_0_xcpt_pf_if = mem_incoming_uop_out_xcpt_pf_if; // @[util.scala:96:23] wire _mem_incoming_uop_WIRE_0_xcpt_ae_if = mem_incoming_uop_out_xcpt_ae_if; // @[util.scala:96:23] wire _mem_incoming_uop_WIRE_0_xcpt_ma_if = mem_incoming_uop_out_xcpt_ma_if; // @[util.scala:96:23] wire _mem_incoming_uop_WIRE_0_bp_debug_if = mem_incoming_uop_out_bp_debug_if; // @[util.scala:96:23] wire _mem_incoming_uop_WIRE_0_bp_xcpt_if = mem_incoming_uop_out_bp_xcpt_if; // @[util.scala:96:23] wire [1:0] _mem_incoming_uop_WIRE_0_debug_fsrc = mem_incoming_uop_out_debug_fsrc; // @[util.scala:96:23] wire [1:0] _mem_incoming_uop_WIRE_0_debug_tsrc = mem_incoming_uop_out_debug_tsrc; // @[util.scala:96:23] wire [7:0] _mem_incoming_uop_out_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:85:27] assign _mem_incoming_uop_out_br_mask_T_1 = exe_req_0_bits_uop_br_mask & _mem_incoming_uop_out_br_mask_T; // @[util.scala:85:{25,27}] assign mem_incoming_uop_out_br_mask = _mem_incoming_uop_out_br_mask_T_1; // @[util.scala:85:25, :96:23] reg [6:0] mem_incoming_uop_0_uopc; // @[lsu.scala:909:37] reg [31:0] mem_incoming_uop_0_inst; // @[lsu.scala:909:37] reg [31:0] mem_incoming_uop_0_debug_inst; // @[lsu.scala:909:37] reg mem_incoming_uop_0_is_rvc; // @[lsu.scala:909:37] reg [39:0] mem_incoming_uop_0_debug_pc; // @[lsu.scala:909:37] reg [2:0] mem_incoming_uop_0_iq_type; // @[lsu.scala:909:37] reg [9:0] mem_incoming_uop_0_fu_code; // @[lsu.scala:909:37] reg [3:0] mem_incoming_uop_0_ctrl_br_type; // @[lsu.scala:909:37] reg [1:0] mem_incoming_uop_0_ctrl_op1_sel; // @[lsu.scala:909:37] reg [2:0] mem_incoming_uop_0_ctrl_op2_sel; // @[lsu.scala:909:37] reg [2:0] mem_incoming_uop_0_ctrl_imm_sel; // @[lsu.scala:909:37] reg [4:0] mem_incoming_uop_0_ctrl_op_fcn; // @[lsu.scala:909:37] reg mem_incoming_uop_0_ctrl_fcn_dw; // @[lsu.scala:909:37] reg [2:0] mem_incoming_uop_0_ctrl_csr_cmd; // @[lsu.scala:909:37] reg mem_incoming_uop_0_ctrl_is_load; // @[lsu.scala:909:37] reg mem_incoming_uop_0_ctrl_is_sta; // @[lsu.scala:909:37] reg mem_incoming_uop_0_ctrl_is_std; // @[lsu.scala:909:37] reg [1:0] mem_incoming_uop_0_iw_state; // @[lsu.scala:909:37] reg mem_incoming_uop_0_iw_p1_poisoned; // @[lsu.scala:909:37] reg mem_incoming_uop_0_iw_p2_poisoned; // @[lsu.scala:909:37] reg mem_incoming_uop_0_is_br; // @[lsu.scala:909:37] reg mem_incoming_uop_0_is_jalr; // @[lsu.scala:909:37] reg mem_incoming_uop_0_is_jal; // @[lsu.scala:909:37] reg mem_incoming_uop_0_is_sfb; // @[lsu.scala:909:37] reg [7:0] mem_incoming_uop_0_br_mask; // @[lsu.scala:909:37] reg [2:0] mem_incoming_uop_0_br_tag; // @[lsu.scala:909:37] reg [3:0] mem_incoming_uop_0_ftq_idx; // @[lsu.scala:909:37] reg mem_incoming_uop_0_edge_inst; // @[lsu.scala:909:37] reg [5:0] mem_incoming_uop_0_pc_lob; // @[lsu.scala:909:37] reg mem_incoming_uop_0_taken; // @[lsu.scala:909:37] reg [19:0] mem_incoming_uop_0_imm_packed; // @[lsu.scala:909:37] reg [11:0] mem_incoming_uop_0_csr_addr; // @[lsu.scala:909:37] reg [4:0] mem_incoming_uop_0_rob_idx; // @[lsu.scala:909:37] reg [2:0] mem_incoming_uop_0_ldq_idx; // @[lsu.scala:909:37] reg [2:0] mem_incoming_uop_0_stq_idx; // @[lsu.scala:909:37] reg [1:0] mem_incoming_uop_0_rxq_idx; // @[lsu.scala:909:37] reg [5:0] mem_incoming_uop_0_pdst; // @[lsu.scala:909:37] assign io_core_spec_ld_wakeup_0_bits_0 = mem_incoming_uop_0_pdst; // @[lsu.scala:201:7, :909:37] reg [5:0] mem_incoming_uop_0_prs1; // @[lsu.scala:909:37] reg [5:0] mem_incoming_uop_0_prs2; // @[lsu.scala:909:37] reg [5:0] mem_incoming_uop_0_prs3; // @[lsu.scala:909:37] reg [3:0] mem_incoming_uop_0_ppred; // @[lsu.scala:909:37] reg mem_incoming_uop_0_prs1_busy; // @[lsu.scala:909:37] reg mem_incoming_uop_0_prs2_busy; // @[lsu.scala:909:37] reg mem_incoming_uop_0_prs3_busy; // @[lsu.scala:909:37] reg mem_incoming_uop_0_ppred_busy; // @[lsu.scala:909:37] reg [5:0] mem_incoming_uop_0_stale_pdst; // @[lsu.scala:909:37] reg mem_incoming_uop_0_exception; // @[lsu.scala:909:37] reg [63:0] mem_incoming_uop_0_exc_cause; // @[lsu.scala:909:37] reg mem_incoming_uop_0_bypassable; // @[lsu.scala:909:37] reg [4:0] mem_incoming_uop_0_mem_cmd; // @[lsu.scala:909:37] reg [1:0] mem_incoming_uop_0_mem_size; // @[lsu.scala:909:37] reg mem_incoming_uop_0_mem_signed; // @[lsu.scala:909:37] reg mem_incoming_uop_0_is_fence; // @[lsu.scala:909:37] reg mem_incoming_uop_0_is_fencei; // @[lsu.scala:909:37] reg mem_incoming_uop_0_is_amo; // @[lsu.scala:909:37] reg mem_incoming_uop_0_uses_ldq; // @[lsu.scala:909:37] reg mem_incoming_uop_0_uses_stq; // @[lsu.scala:909:37] reg mem_incoming_uop_0_is_sys_pc2epc; // @[lsu.scala:909:37] reg mem_incoming_uop_0_is_unique; // @[lsu.scala:909:37] reg mem_incoming_uop_0_flush_on_commit; // @[lsu.scala:909:37] reg mem_incoming_uop_0_ldst_is_rs1; // @[lsu.scala:909:37] reg [5:0] mem_incoming_uop_0_ldst; // @[lsu.scala:909:37] reg [5:0] mem_incoming_uop_0_lrs1; // @[lsu.scala:909:37] reg [5:0] mem_incoming_uop_0_lrs2; // @[lsu.scala:909:37] reg [5:0] mem_incoming_uop_0_lrs3; // @[lsu.scala:909:37] reg mem_incoming_uop_0_ldst_val; // @[lsu.scala:909:37] reg [1:0] mem_incoming_uop_0_dst_rtype; // @[lsu.scala:909:37] reg [1:0] mem_incoming_uop_0_lrs1_rtype; // @[lsu.scala:909:37] reg [1:0] mem_incoming_uop_0_lrs2_rtype; // @[lsu.scala:909:37] reg mem_incoming_uop_0_frs3_en; // @[lsu.scala:909:37] reg mem_incoming_uop_0_fp_val; // @[lsu.scala:909:37] reg mem_incoming_uop_0_fp_single; // @[lsu.scala:909:37] reg mem_incoming_uop_0_xcpt_pf_if; // @[lsu.scala:909:37] reg mem_incoming_uop_0_xcpt_ae_if; // @[lsu.scala:909:37] reg mem_incoming_uop_0_xcpt_ma_if; // @[lsu.scala:909:37] reg mem_incoming_uop_0_bp_debug_if; // @[lsu.scala:909:37] reg mem_incoming_uop_0_bp_xcpt_if; // @[lsu.scala:909:37] reg [1:0] mem_incoming_uop_0_debug_fsrc; // @[lsu.scala:909:37] reg [1:0] mem_incoming_uop_0_debug_tsrc; // @[lsu.scala:909:37] wire _mem_ldq_incoming_e_out_valid_T_3; // @[util.scala:108:31] wire _mem_ldq_incoming_e_WIRE_0_valid = mem_ldq_incoming_e_out_valid; // @[util.scala:106:23] wire [6:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_uopc = mem_ldq_incoming_e_out_bits_uop_uopc; // @[util.scala:106:23] wire [31:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_inst = mem_ldq_incoming_e_out_bits_uop_inst; // @[util.scala:106:23] wire [31:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_debug_inst = mem_ldq_incoming_e_out_bits_uop_debug_inst; // @[util.scala:106:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_is_rvc = mem_ldq_incoming_e_out_bits_uop_is_rvc; // @[util.scala:106:23] wire [39:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_debug_pc = mem_ldq_incoming_e_out_bits_uop_debug_pc; // @[util.scala:106:23] wire [2:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_iq_type = mem_ldq_incoming_e_out_bits_uop_iq_type; // @[util.scala:106:23] wire [9:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_fu_code = mem_ldq_incoming_e_out_bits_uop_fu_code; // @[util.scala:106:23] wire [3:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_ctrl_br_type = mem_ldq_incoming_e_out_bits_uop_ctrl_br_type; // @[util.scala:106:23] wire [1:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_ctrl_op1_sel = mem_ldq_incoming_e_out_bits_uop_ctrl_op1_sel; // @[util.scala:106:23] wire [2:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_ctrl_op2_sel = mem_ldq_incoming_e_out_bits_uop_ctrl_op2_sel; // @[util.scala:106:23] wire [2:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_ctrl_imm_sel = mem_ldq_incoming_e_out_bits_uop_ctrl_imm_sel; // @[util.scala:106:23] wire [4:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_ctrl_op_fcn = mem_ldq_incoming_e_out_bits_uop_ctrl_op_fcn; // @[util.scala:106:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_ctrl_fcn_dw = mem_ldq_incoming_e_out_bits_uop_ctrl_fcn_dw; // @[util.scala:106:23] wire [2:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_ctrl_csr_cmd = mem_ldq_incoming_e_out_bits_uop_ctrl_csr_cmd; // @[util.scala:106:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_ctrl_is_load = mem_ldq_incoming_e_out_bits_uop_ctrl_is_load; // @[util.scala:106:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_ctrl_is_sta = mem_ldq_incoming_e_out_bits_uop_ctrl_is_sta; // @[util.scala:106:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_ctrl_is_std = mem_ldq_incoming_e_out_bits_uop_ctrl_is_std; // @[util.scala:106:23] wire [1:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_iw_state = mem_ldq_incoming_e_out_bits_uop_iw_state; // @[util.scala:106:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_iw_p1_poisoned = mem_ldq_incoming_e_out_bits_uop_iw_p1_poisoned; // @[util.scala:106:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_iw_p2_poisoned = mem_ldq_incoming_e_out_bits_uop_iw_p2_poisoned; // @[util.scala:106:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_is_br = mem_ldq_incoming_e_out_bits_uop_is_br; // @[util.scala:106:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_is_jalr = mem_ldq_incoming_e_out_bits_uop_is_jalr; // @[util.scala:106:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_is_jal = mem_ldq_incoming_e_out_bits_uop_is_jal; // @[util.scala:106:23] wire [7:0] _mem_ldq_incoming_e_out_bits_uop_br_mask_T_1; // @[util.scala:89:21] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_is_sfb = mem_ldq_incoming_e_out_bits_uop_is_sfb; // @[util.scala:106:23] wire [7:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_br_mask = mem_ldq_incoming_e_out_bits_uop_br_mask; // @[util.scala:106:23] wire [2:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_br_tag = mem_ldq_incoming_e_out_bits_uop_br_tag; // @[util.scala:106:23] wire [3:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_ftq_idx = mem_ldq_incoming_e_out_bits_uop_ftq_idx; // @[util.scala:106:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_edge_inst = mem_ldq_incoming_e_out_bits_uop_edge_inst; // @[util.scala:106:23] wire [5:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_pc_lob = mem_ldq_incoming_e_out_bits_uop_pc_lob; // @[util.scala:106:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_taken = mem_ldq_incoming_e_out_bits_uop_taken; // @[util.scala:106:23] wire [19:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_imm_packed = mem_ldq_incoming_e_out_bits_uop_imm_packed; // @[util.scala:106:23] wire [11:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_csr_addr = mem_ldq_incoming_e_out_bits_uop_csr_addr; // @[util.scala:106:23] wire [4:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_rob_idx = mem_ldq_incoming_e_out_bits_uop_rob_idx; // @[util.scala:106:23] wire [2:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_ldq_idx = mem_ldq_incoming_e_out_bits_uop_ldq_idx; // @[util.scala:106:23] wire [2:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_stq_idx = mem_ldq_incoming_e_out_bits_uop_stq_idx; // @[util.scala:106:23] wire [1:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_rxq_idx = mem_ldq_incoming_e_out_bits_uop_rxq_idx; // @[util.scala:106:23] wire [5:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_pdst = mem_ldq_incoming_e_out_bits_uop_pdst; // @[util.scala:106:23] wire [5:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_prs1 = mem_ldq_incoming_e_out_bits_uop_prs1; // @[util.scala:106:23] wire [5:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_prs2 = mem_ldq_incoming_e_out_bits_uop_prs2; // @[util.scala:106:23] wire [5:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_prs3 = mem_ldq_incoming_e_out_bits_uop_prs3; // @[util.scala:106:23] wire [3:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_ppred = mem_ldq_incoming_e_out_bits_uop_ppred; // @[util.scala:106:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_prs1_busy = mem_ldq_incoming_e_out_bits_uop_prs1_busy; // @[util.scala:106:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_prs2_busy = mem_ldq_incoming_e_out_bits_uop_prs2_busy; // @[util.scala:106:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_prs3_busy = mem_ldq_incoming_e_out_bits_uop_prs3_busy; // @[util.scala:106:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_ppred_busy = mem_ldq_incoming_e_out_bits_uop_ppred_busy; // @[util.scala:106:23] wire [5:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_stale_pdst = mem_ldq_incoming_e_out_bits_uop_stale_pdst; // @[util.scala:106:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_exception = mem_ldq_incoming_e_out_bits_uop_exception; // @[util.scala:106:23] wire [63:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_exc_cause = mem_ldq_incoming_e_out_bits_uop_exc_cause; // @[util.scala:106:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_bypassable = mem_ldq_incoming_e_out_bits_uop_bypassable; // @[util.scala:106:23] wire [4:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_mem_cmd = mem_ldq_incoming_e_out_bits_uop_mem_cmd; // @[util.scala:106:23] wire [1:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_mem_size = mem_ldq_incoming_e_out_bits_uop_mem_size; // @[util.scala:106:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_mem_signed = mem_ldq_incoming_e_out_bits_uop_mem_signed; // @[util.scala:106:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_is_fence = mem_ldq_incoming_e_out_bits_uop_is_fence; // @[util.scala:106:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_is_fencei = mem_ldq_incoming_e_out_bits_uop_is_fencei; // @[util.scala:106:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_is_amo = mem_ldq_incoming_e_out_bits_uop_is_amo; // @[util.scala:106:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_uses_ldq = mem_ldq_incoming_e_out_bits_uop_uses_ldq; // @[util.scala:106:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_uses_stq = mem_ldq_incoming_e_out_bits_uop_uses_stq; // @[util.scala:106:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_is_sys_pc2epc = mem_ldq_incoming_e_out_bits_uop_is_sys_pc2epc; // @[util.scala:106:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_is_unique = mem_ldq_incoming_e_out_bits_uop_is_unique; // @[util.scala:106:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_flush_on_commit = mem_ldq_incoming_e_out_bits_uop_flush_on_commit; // @[util.scala:106:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_ldst_is_rs1 = mem_ldq_incoming_e_out_bits_uop_ldst_is_rs1; // @[util.scala:106:23] wire [5:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_ldst = mem_ldq_incoming_e_out_bits_uop_ldst; // @[util.scala:106:23] wire [5:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_lrs1 = mem_ldq_incoming_e_out_bits_uop_lrs1; // @[util.scala:106:23] wire [5:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_lrs2 = mem_ldq_incoming_e_out_bits_uop_lrs2; // @[util.scala:106:23] wire [5:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_lrs3 = mem_ldq_incoming_e_out_bits_uop_lrs3; // @[util.scala:106:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_ldst_val = mem_ldq_incoming_e_out_bits_uop_ldst_val; // @[util.scala:106:23] wire [1:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_dst_rtype = mem_ldq_incoming_e_out_bits_uop_dst_rtype; // @[util.scala:106:23] wire [1:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_lrs1_rtype = mem_ldq_incoming_e_out_bits_uop_lrs1_rtype; // @[util.scala:106:23] wire [1:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_lrs2_rtype = mem_ldq_incoming_e_out_bits_uop_lrs2_rtype; // @[util.scala:106:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_frs3_en = mem_ldq_incoming_e_out_bits_uop_frs3_en; // @[util.scala:106:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_fp_val = mem_ldq_incoming_e_out_bits_uop_fp_val; // @[util.scala:106:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_fp_single = mem_ldq_incoming_e_out_bits_uop_fp_single; // @[util.scala:106:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_xcpt_pf_if = mem_ldq_incoming_e_out_bits_uop_xcpt_pf_if; // @[util.scala:106:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_xcpt_ae_if = mem_ldq_incoming_e_out_bits_uop_xcpt_ae_if; // @[util.scala:106:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_xcpt_ma_if = mem_ldq_incoming_e_out_bits_uop_xcpt_ma_if; // @[util.scala:106:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_bp_debug_if = mem_ldq_incoming_e_out_bits_uop_bp_debug_if; // @[util.scala:106:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_bp_xcpt_if = mem_ldq_incoming_e_out_bits_uop_bp_xcpt_if; // @[util.scala:106:23] wire [1:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_debug_fsrc = mem_ldq_incoming_e_out_bits_uop_debug_fsrc; // @[util.scala:106:23] wire [1:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_debug_tsrc = mem_ldq_incoming_e_out_bits_uop_debug_tsrc; // @[util.scala:106:23] wire _mem_ldq_incoming_e_WIRE_0_bits_addr_valid = mem_ldq_incoming_e_out_bits_addr_valid; // @[util.scala:106:23] wire [39:0] _mem_ldq_incoming_e_WIRE_0_bits_addr_bits = mem_ldq_incoming_e_out_bits_addr_bits; // @[util.scala:106:23] wire _mem_ldq_incoming_e_WIRE_0_bits_addr_is_virtual = mem_ldq_incoming_e_out_bits_addr_is_virtual; // @[util.scala:106:23] wire _mem_ldq_incoming_e_WIRE_0_bits_addr_is_uncacheable = mem_ldq_incoming_e_out_bits_addr_is_uncacheable; // @[util.scala:106:23] wire _mem_ldq_incoming_e_WIRE_0_bits_executed = mem_ldq_incoming_e_out_bits_executed; // @[util.scala:106:23] wire _mem_ldq_incoming_e_WIRE_0_bits_succeeded = mem_ldq_incoming_e_out_bits_succeeded; // @[util.scala:106:23] wire _mem_ldq_incoming_e_WIRE_0_bits_order_fail = mem_ldq_incoming_e_out_bits_order_fail; // @[util.scala:106:23] wire _mem_ldq_incoming_e_WIRE_0_bits_observed = mem_ldq_incoming_e_out_bits_observed; // @[util.scala:106:23] wire [7:0] _mem_ldq_incoming_e_WIRE_0_bits_st_dep_mask = mem_ldq_incoming_e_out_bits_st_dep_mask; // @[util.scala:106:23] wire [2:0] _mem_ldq_incoming_e_WIRE_0_bits_youngest_stq_idx = mem_ldq_incoming_e_out_bits_youngest_stq_idx; // @[util.scala:106:23] wire _mem_ldq_incoming_e_WIRE_0_bits_forward_std_val = mem_ldq_incoming_e_out_bits_forward_std_val; // @[util.scala:106:23] wire [2:0] _mem_ldq_incoming_e_WIRE_0_bits_forward_stq_idx = mem_ldq_incoming_e_out_bits_forward_stq_idx; // @[util.scala:106:23] wire [63:0] _mem_ldq_incoming_e_WIRE_0_bits_debug_wb_data = mem_ldq_incoming_e_out_bits_debug_wb_data; // @[util.scala:106:23] wire [7:0] _mem_ldq_incoming_e_out_bits_uop_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:85:27, :89:23] assign _mem_ldq_incoming_e_out_bits_uop_br_mask_T_1 = ldq_incoming_e_0_bits_uop_br_mask & _mem_ldq_incoming_e_out_bits_uop_br_mask_T; // @[util.scala:89:{21,23}] assign mem_ldq_incoming_e_out_bits_uop_br_mask = _mem_ldq_incoming_e_out_bits_uop_br_mask_T_1; // @[util.scala:89:21, :106:23] wire [7:0] _mem_ldq_incoming_e_out_valid_T = io_core_brupdate_b1_mispredict_mask_0 & ldq_incoming_e_0_bits_uop_br_mask; // @[util.scala:118:51] wire _mem_ldq_incoming_e_out_valid_T_1 = \|_mem_ldq_incoming_e_out_valid_T; // @[util.scala:118:{51,59}] wire _mem_ldq_incoming_e_out_valid_T_2 = ~_mem_ldq_incoming_e_out_valid_T_1; // @[util.scala:108:34, :118:59] assign _mem_ldq_incoming_e_out_valid_T_3 = ldq_incoming_e_0_valid & _mem_ldq_incoming_e_out_valid_T_2; // @[util.scala:108:{31,34}] assign mem_ldq_incoming_e_out_valid = _mem_ldq_incoming_e_out_valid_T_3; // @[util.scala:106:23, :108:31] reg mem_ldq_incoming_e_0_valid; // @[lsu.scala:910:37] reg [6:0] mem_ldq_incoming_e_0_bits_uop_uopc; // @[lsu.scala:910:37] reg [31:0] mem_ldq_incoming_e_0_bits_uop_inst; // @[lsu.scala:910:37] reg [31:0] mem_ldq_incoming_e_0_bits_uop_debug_inst; // @[lsu.scala:910:37] reg mem_ldq_incoming_e_0_bits_uop_is_rvc; // @[lsu.scala:910:37] reg [39:0] mem_ldq_incoming_e_0_bits_uop_debug_pc; // @[lsu.scala:910:37] reg [2:0] mem_ldq_incoming_e_0_bits_uop_iq_type; // @[lsu.scala:910:37] reg [9:0] mem_ldq_incoming_e_0_bits_uop_fu_code; // @[lsu.scala:910:37] reg [3:0] mem_ldq_incoming_e_0_bits_uop_ctrl_br_type; // @[lsu.scala:910:37] reg [1:0] mem_ldq_incoming_e_0_bits_uop_ctrl_op1_sel; // @[lsu.scala:910:37] reg [2:0] mem_ldq_incoming_e_0_bits_uop_ctrl_op2_sel; // @[lsu.scala:910:37] reg [2:0] mem_ldq_incoming_e_0_bits_uop_ctrl_imm_sel; // @[lsu.scala:910:37] reg [4:0] mem_ldq_incoming_e_0_bits_uop_ctrl_op_fcn; // @[lsu.scala:910:37] reg mem_ldq_incoming_e_0_bits_uop_ctrl_fcn_dw; // @[lsu.scala:910:37] reg [2:0] mem_ldq_incoming_e_0_bits_uop_ctrl_csr_cmd; // @[lsu.scala:910:37] reg mem_ldq_incoming_e_0_bits_uop_ctrl_is_load; // @[lsu.scala:910:37] reg mem_ldq_incoming_e_0_bits_uop_ctrl_is_sta; // @[lsu.scala:910:37] reg mem_ldq_incoming_e_0_bits_uop_ctrl_is_std; // @[lsu.scala:910:37] reg [1:0] mem_ldq_incoming_e_0_bits_uop_iw_state; // @[lsu.scala:910:37] reg mem_ldq_incoming_e_0_bits_uop_iw_p1_poisoned; // @[lsu.scala:910:37] reg mem_ldq_incoming_e_0_bits_uop_iw_p2_poisoned; // @[lsu.scala:910:37] reg mem_ldq_incoming_e_0_bits_uop_is_br; // @[lsu.scala:910:37] reg mem_ldq_incoming_e_0_bits_uop_is_jalr; // @[lsu.scala:910:37] reg mem_ldq_incoming_e_0_bits_uop_is_jal; // @[lsu.scala:910:37] reg mem_ldq_incoming_e_0_bits_uop_is_sfb; // @[lsu.scala:910:37] reg [7:0] mem_ldq_incoming_e_0_bits_uop_br_mask; // @[lsu.scala:910:37] reg [2:0] mem_ldq_incoming_e_0_bits_uop_br_tag; // @[lsu.scala:910:37] reg [3:0] mem_ldq_incoming_e_0_bits_uop_ftq_idx; // @[lsu.scala:910:37] reg mem_ldq_incoming_e_0_bits_uop_edge_inst; // @[lsu.scala:910:37] reg [5:0] mem_ldq_incoming_e_0_bits_uop_pc_lob; // @[lsu.scala:910:37] reg mem_ldq_incoming_e_0_bits_uop_taken; // @[lsu.scala:910:37] reg [19:0] mem_ldq_incoming_e_0_bits_uop_imm_packed; // @[lsu.scala:910:37] reg [11:0] mem_ldq_incoming_e_0_bits_uop_csr_addr; // @[lsu.scala:910:37] reg [4:0] mem_ldq_incoming_e_0_bits_uop_rob_idx; // @[lsu.scala:910:37] reg [2:0] mem_ldq_incoming_e_0_bits_uop_ldq_idx; // @[lsu.scala:910:37] reg [2:0] mem_ldq_incoming_e_0_bits_uop_stq_idx; // @[lsu.scala:910:37] reg [1:0] mem_ldq_incoming_e_0_bits_uop_rxq_idx; // @[lsu.scala:910:37] reg [5:0] mem_ldq_incoming_e_0_bits_uop_pdst; // @[lsu.scala:910:37] reg [5:0] mem_ldq_incoming_e_0_bits_uop_prs1; // @[lsu.scala:910:37] reg [5:0] mem_ldq_incoming_e_0_bits_uop_prs2; // @[lsu.scala:910:37] reg [5:0] mem_ldq_incoming_e_0_bits_uop_prs3; // @[lsu.scala:910:37] reg [3:0] mem_ldq_incoming_e_0_bits_uop_ppred; // @[lsu.scala:910:37] reg mem_ldq_incoming_e_0_bits_uop_prs1_busy; // @[lsu.scala:910:37] reg mem_ldq_incoming_e_0_bits_uop_prs2_busy; // @[lsu.scala:910:37] reg mem_ldq_incoming_e_0_bits_uop_prs3_busy; // @[lsu.scala:910:37] reg mem_ldq_incoming_e_0_bits_uop_ppred_busy; // @[lsu.scala:910:37] reg [5:0] mem_ldq_incoming_e_0_bits_uop_stale_pdst; // @[lsu.scala:910:37] reg mem_ldq_incoming_e_0_bits_uop_exception; // @[lsu.scala:910:37] reg [63:0] mem_ldq_incoming_e_0_bits_uop_exc_cause; // @[lsu.scala:910:37] reg mem_ldq_incoming_e_0_bits_uop_bypassable; // @[lsu.scala:910:37] reg [4:0] mem_ldq_incoming_e_0_bits_uop_mem_cmd; // @[lsu.scala:910:37] reg [1:0] mem_ldq_incoming_e_0_bits_uop_mem_size; // @[lsu.scala:910:37] reg mem_ldq_incoming_e_0_bits_uop_mem_signed; // @[lsu.scala:910:37] reg mem_ldq_incoming_e_0_bits_uop_is_fence; // @[lsu.scala:910:37] reg mem_ldq_incoming_e_0_bits_uop_is_fencei; // @[lsu.scala:910:37] reg mem_ldq_incoming_e_0_bits_uop_is_amo; // @[lsu.scala:910:37] reg mem_ldq_incoming_e_0_bits_uop_uses_ldq; // @[lsu.scala:910:37] reg mem_ldq_incoming_e_0_bits_uop_uses_stq; // @[lsu.scala:910:37] reg mem_ldq_incoming_e_0_bits_uop_is_sys_pc2epc; // @[lsu.scala:910:37] reg mem_ldq_incoming_e_0_bits_uop_is_unique; // @[lsu.scala:910:37] reg mem_ldq_incoming_e_0_bits_uop_flush_on_commit; // @[lsu.scala:910:37] reg mem_ldq_incoming_e_0_bits_uop_ldst_is_rs1; // @[lsu.scala:910:37] reg [5:0] mem_ldq_incoming_e_0_bits_uop_ldst; // @[lsu.scala:910:37] reg [5:0] mem_ldq_incoming_e_0_bits_uop_lrs1; // @[lsu.scala:910:37] reg [5:0] mem_ldq_incoming_e_0_bits_uop_lrs2; // @[lsu.scala:910:37] reg [5:0] mem_ldq_incoming_e_0_bits_uop_lrs3; // @[lsu.scala:910:37] reg mem_ldq_incoming_e_0_bits_uop_ldst_val; // @[lsu.scala:910:37] reg [1:0] mem_ldq_incoming_e_0_bits_uop_dst_rtype; // @[lsu.scala:910:37] reg [1:0] mem_ldq_incoming_e_0_bits_uop_lrs1_rtype; // @[lsu.scala:910:37] reg [1:0] mem_ldq_incoming_e_0_bits_uop_lrs2_rtype; // @[lsu.scala:910:37] reg mem_ldq_incoming_e_0_bits_uop_frs3_en; // @[lsu.scala:910:37] reg mem_ldq_incoming_e_0_bits_uop_fp_val; // @[lsu.scala:910:37] reg mem_ldq_incoming_e_0_bits_uop_fp_single; // @[lsu.scala:910:37] reg mem_ldq_incoming_e_0_bits_uop_xcpt_pf_if; // @[lsu.scala:910:37] reg mem_ldq_incoming_e_0_bits_uop_xcpt_ae_if; // @[lsu.scala:910:37] reg mem_ldq_incoming_e_0_bits_uop_xcpt_ma_if; // @[lsu.scala:910:37] reg mem_ldq_incoming_e_0_bits_uop_bp_debug_if; // @[lsu.scala:910:37] reg mem_ldq_incoming_e_0_bits_uop_bp_xcpt_if; // @[lsu.scala:910:37] reg [1:0] mem_ldq_incoming_e_0_bits_uop_debug_fsrc; // @[lsu.scala:910:37] reg [1:0] mem_ldq_incoming_e_0_bits_uop_debug_tsrc; // @[lsu.scala:910:37] reg mem_ldq_incoming_e_0_bits_addr_valid; // @[lsu.scala:910:37] reg [39:0] mem_ldq_incoming_e_0_bits_addr_bits; // @[lsu.scala:910:37] reg mem_ldq_incoming_e_0_bits_addr_is_virtual; // @[lsu.scala:910:37] reg mem_ldq_incoming_e_0_bits_addr_is_uncacheable; // @[lsu.scala:910:37] reg mem_ldq_incoming_e_0_bits_executed; // @[lsu.scala:910:37] reg mem_ldq_incoming_e_0_bits_succeeded; // @[lsu.scala:910:37] reg mem_ldq_incoming_e_0_bits_order_fail; // @[lsu.scala:910:37] reg mem_ldq_incoming_e_0_bits_observed; // @[lsu.scala:910:37] reg [7:0] mem_ldq_incoming_e_0_bits_st_dep_mask; // @[lsu.scala:910:37] reg [2:0] mem_ldq_incoming_e_0_bits_youngest_stq_idx; // @[lsu.scala:910:37] reg mem_ldq_incoming_e_0_bits_forward_std_val; // @[lsu.scala:910:37] reg [2:0] mem_ldq_incoming_e_0_bits_forward_stq_idx; // @[lsu.scala:910:37] reg [63:0] mem_ldq_incoming_e_0_bits_debug_wb_data; // @[lsu.scala:910:37] wire _mem_stq_incoming_e_out_valid_T_3; // @[util.scala:108:31] wire _mem_stq_incoming_e_WIRE_0_valid = mem_stq_incoming_e_out_valid; // @[util.scala:106:23] wire [6:0] _mem_stq_incoming_e_WIRE_0_bits_uop_uopc = mem_stq_incoming_e_out_bits_uop_uopc; // @[util.scala:106:23] wire [31:0] _mem_stq_incoming_e_WIRE_0_bits_uop_inst = mem_stq_incoming_e_out_bits_uop_inst; // @[util.scala:106:23] wire [31:0] _mem_stq_incoming_e_WIRE_0_bits_uop_debug_inst = mem_stq_incoming_e_out_bits_uop_debug_inst; // @[util.scala:106:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_is_rvc = mem_stq_incoming_e_out_bits_uop_is_rvc; // @[util.scala:106:23] wire [39:0] _mem_stq_incoming_e_WIRE_0_bits_uop_debug_pc = mem_stq_incoming_e_out_bits_uop_debug_pc; // @[util.scala:106:23] wire [2:0] _mem_stq_incoming_e_WIRE_0_bits_uop_iq_type = mem_stq_incoming_e_out_bits_uop_iq_type; // @[util.scala:106:23] wire [9:0] _mem_stq_incoming_e_WIRE_0_bits_uop_fu_code = mem_stq_incoming_e_out_bits_uop_fu_code; // @[util.scala:106:23] wire [3:0] _mem_stq_incoming_e_WIRE_0_bits_uop_ctrl_br_type = mem_stq_incoming_e_out_bits_uop_ctrl_br_type; // @[util.scala:106:23] wire [1:0] _mem_stq_incoming_e_WIRE_0_bits_uop_ctrl_op1_sel = mem_stq_incoming_e_out_bits_uop_ctrl_op1_sel; // @[util.scala:106:23] wire [2:0] _mem_stq_incoming_e_WIRE_0_bits_uop_ctrl_op2_sel = mem_stq_incoming_e_out_bits_uop_ctrl_op2_sel; // @[util.scala:106:23] wire [2:0] _mem_stq_incoming_e_WIRE_0_bits_uop_ctrl_imm_sel = mem_stq_incoming_e_out_bits_uop_ctrl_imm_sel; // @[util.scala:106:23] wire [4:0] _mem_stq_incoming_e_WIRE_0_bits_uop_ctrl_op_fcn = mem_stq_incoming_e_out_bits_uop_ctrl_op_fcn; // @[util.scala:106:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_ctrl_fcn_dw = mem_stq_incoming_e_out_bits_uop_ctrl_fcn_dw; // @[util.scala:106:23] wire [2:0] _mem_stq_incoming_e_WIRE_0_bits_uop_ctrl_csr_cmd = mem_stq_incoming_e_out_bits_uop_ctrl_csr_cmd; // @[util.scala:106:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_ctrl_is_load = mem_stq_incoming_e_out_bits_uop_ctrl_is_load; // @[util.scala:106:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_ctrl_is_sta = mem_stq_incoming_e_out_bits_uop_ctrl_is_sta; // @[util.scala:106:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_ctrl_is_std = mem_stq_incoming_e_out_bits_uop_ctrl_is_std; // @[util.scala:106:23] wire [1:0] _mem_stq_incoming_e_WIRE_0_bits_uop_iw_state = mem_stq_incoming_e_out_bits_uop_iw_state; // @[util.scala:106:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_iw_p1_poisoned = mem_stq_incoming_e_out_bits_uop_iw_p1_poisoned; // @[util.scala:106:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_iw_p2_poisoned = mem_stq_incoming_e_out_bits_uop_iw_p2_poisoned; // @[util.scala:106:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_is_br = mem_stq_incoming_e_out_bits_uop_is_br; // @[util.scala:106:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_is_jalr = mem_stq_incoming_e_out_bits_uop_is_jalr; // @[util.scala:106:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_is_jal = mem_stq_incoming_e_out_bits_uop_is_jal; // @[util.scala:106:23] wire [7:0] _mem_stq_incoming_e_out_bits_uop_br_mask_T_1; // @[util.scala:89:21] wire _mem_stq_incoming_e_WIRE_0_bits_uop_is_sfb = mem_stq_incoming_e_out_bits_uop_is_sfb; // @[util.scala:106:23] wire [7:0] _mem_stq_incoming_e_WIRE_0_bits_uop_br_mask = mem_stq_incoming_e_out_bits_uop_br_mask; // @[util.scala:106:23] wire [2:0] _mem_stq_incoming_e_WIRE_0_bits_uop_br_tag = mem_stq_incoming_e_out_bits_uop_br_tag; // @[util.scala:106:23] wire [3:0] _mem_stq_incoming_e_WIRE_0_bits_uop_ftq_idx = mem_stq_incoming_e_out_bits_uop_ftq_idx; // @[util.scala:106:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_edge_inst = mem_stq_incoming_e_out_bits_uop_edge_inst; // @[util.scala:106:23] wire [5:0] _mem_stq_incoming_e_WIRE_0_bits_uop_pc_lob = mem_stq_incoming_e_out_bits_uop_pc_lob; // @[util.scala:106:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_taken = mem_stq_incoming_e_out_bits_uop_taken; // @[util.scala:106:23] wire [19:0] _mem_stq_incoming_e_WIRE_0_bits_uop_imm_packed = mem_stq_incoming_e_out_bits_uop_imm_packed; // @[util.scala:106:23] wire [11:0] _mem_stq_incoming_e_WIRE_0_bits_uop_csr_addr = mem_stq_incoming_e_out_bits_uop_csr_addr; // @[util.scala:106:23] wire [4:0] _mem_stq_incoming_e_WIRE_0_bits_uop_rob_idx = mem_stq_incoming_e_out_bits_uop_rob_idx; // @[util.scala:106:23] wire [2:0] _mem_stq_incoming_e_WIRE_0_bits_uop_ldq_idx = mem_stq_incoming_e_out_bits_uop_ldq_idx; // @[util.scala:106:23] wire [2:0] _mem_stq_incoming_e_WIRE_0_bits_uop_stq_idx = mem_stq_incoming_e_out_bits_uop_stq_idx; // @[util.scala:106:23] wire [1:0] _mem_stq_incoming_e_WIRE_0_bits_uop_rxq_idx = mem_stq_incoming_e_out_bits_uop_rxq_idx; // @[util.scala:106:23] wire [5:0] _mem_stq_incoming_e_WIRE_0_bits_uop_pdst = mem_stq_incoming_e_out_bits_uop_pdst; // @[util.scala:106:23] wire [5:0] _mem_stq_incoming_e_WIRE_0_bits_uop_prs1 = mem_stq_incoming_e_out_bits_uop_prs1; // @[util.scala:106:23] wire [5:0] _mem_stq_incoming_e_WIRE_0_bits_uop_prs2 = mem_stq_incoming_e_out_bits_uop_prs2; // @[util.scala:106:23] wire [5:0] _mem_stq_incoming_e_WIRE_0_bits_uop_prs3 = mem_stq_incoming_e_out_bits_uop_prs3; // @[util.scala:106:23] wire [3:0] _mem_stq_incoming_e_WIRE_0_bits_uop_ppred = mem_stq_incoming_e_out_bits_uop_ppred; // @[util.scala:106:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_prs1_busy = mem_stq_incoming_e_out_bits_uop_prs1_busy; // @[util.scala:106:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_prs2_busy = mem_stq_incoming_e_out_bits_uop_prs2_busy; // @[util.scala:106:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_prs3_busy = mem_stq_incoming_e_out_bits_uop_prs3_busy; // @[util.scala:106:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_ppred_busy = mem_stq_incoming_e_out_bits_uop_ppred_busy; // @[util.scala:106:23] wire [5:0] _mem_stq_incoming_e_WIRE_0_bits_uop_stale_pdst = mem_stq_incoming_e_out_bits_uop_stale_pdst; // @[util.scala:106:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_exception = mem_stq_incoming_e_out_bits_uop_exception; // @[util.scala:106:23] wire [63:0] _mem_stq_incoming_e_WIRE_0_bits_uop_exc_cause = mem_stq_incoming_e_out_bits_uop_exc_cause; // @[util.scala:106:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_bypassable = mem_stq_incoming_e_out_bits_uop_bypassable; // @[util.scala:106:23] wire [4:0] _mem_stq_incoming_e_WIRE_0_bits_uop_mem_cmd = mem_stq_incoming_e_out_bits_uop_mem_cmd; // @[util.scala:106:23] wire [1:0] _mem_stq_incoming_e_WIRE_0_bits_uop_mem_size = mem_stq_incoming_e_out_bits_uop_mem_size; // @[util.scala:106:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_mem_signed = mem_stq_incoming_e_out_bits_uop_mem_signed; // @[util.scala:106:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_is_fence = mem_stq_incoming_e_out_bits_uop_is_fence; // @[util.scala:106:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_is_fencei = mem_stq_incoming_e_out_bits_uop_is_fencei; // @[util.scala:106:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_is_amo = mem_stq_incoming_e_out_bits_uop_is_amo; // @[util.scala:106:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_uses_ldq = mem_stq_incoming_e_out_bits_uop_uses_ldq; // @[util.scala:106:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_uses_stq = mem_stq_incoming_e_out_bits_uop_uses_stq; // @[util.scala:106:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_is_sys_pc2epc = mem_stq_incoming_e_out_bits_uop_is_sys_pc2epc; // @[util.scala:106:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_is_unique = mem_stq_incoming_e_out_bits_uop_is_unique; // @[util.scala:106:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_flush_on_commit = mem_stq_incoming_e_out_bits_uop_flush_on_commit; // @[util.scala:106:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_ldst_is_rs1 = mem_stq_incoming_e_out_bits_uop_ldst_is_rs1; // @[util.scala:106:23] wire [5:0] _mem_stq_incoming_e_WIRE_0_bits_uop_ldst = mem_stq_incoming_e_out_bits_uop_ldst; // @[util.scala:106:23] wire [5:0] _mem_stq_incoming_e_WIRE_0_bits_uop_lrs1 = mem_stq_incoming_e_out_bits_uop_lrs1; // @[util.scala:106:23] wire [5:0] _mem_stq_incoming_e_WIRE_0_bits_uop_lrs2 = mem_stq_incoming_e_out_bits_uop_lrs2; // @[util.scala:106:23] wire [5:0] _mem_stq_incoming_e_WIRE_0_bits_uop_lrs3 = mem_stq_incoming_e_out_bits_uop_lrs3; // @[util.scala:106:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_ldst_val = mem_stq_incoming_e_out_bits_uop_ldst_val; // @[util.scala:106:23] wire [1:0] _mem_stq_incoming_e_WIRE_0_bits_uop_dst_rtype = mem_stq_incoming_e_out_bits_uop_dst_rtype; // @[util.scala:106:23] wire [1:0] _mem_stq_incoming_e_WIRE_0_bits_uop_lrs1_rtype = mem_stq_incoming_e_out_bits_uop_lrs1_rtype; // @[util.scala:106:23] wire [1:0] _mem_stq_incoming_e_WIRE_0_bits_uop_lrs2_rtype = mem_stq_incoming_e_out_bits_uop_lrs2_rtype; // @[util.scala:106:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_frs3_en = mem_stq_incoming_e_out_bits_uop_frs3_en; // @[util.scala:106:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_fp_val = mem_stq_incoming_e_out_bits_uop_fp_val; // @[util.scala:106:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_fp_single = mem_stq_incoming_e_out_bits_uop_fp_single; // @[util.scala:106:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_xcpt_pf_if = mem_stq_incoming_e_out_bits_uop_xcpt_pf_if; // @[util.scala:106:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_xcpt_ae_if = mem_stq_incoming_e_out_bits_uop_xcpt_ae_if; // @[util.scala:106:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_xcpt_ma_if = mem_stq_incoming_e_out_bits_uop_xcpt_ma_if; // @[util.scala:106:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_bp_debug_if = mem_stq_incoming_e_out_bits_uop_bp_debug_if; // @[util.scala:106:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_bp_xcpt_if = mem_stq_incoming_e_out_bits_uop_bp_xcpt_if; // @[util.scala:106:23] wire [1:0] _mem_stq_incoming_e_WIRE_0_bits_uop_debug_fsrc = mem_stq_incoming_e_out_bits_uop_debug_fsrc; // @[util.scala:106:23] wire [1:0] _mem_stq_incoming_e_WIRE_0_bits_uop_debug_tsrc = mem_stq_incoming_e_out_bits_uop_debug_tsrc; // @[util.scala:106:23] wire _mem_stq_incoming_e_WIRE_0_bits_addr_valid = mem_stq_incoming_e_out_bits_addr_valid; // @[util.scala:106:23] wire [39:0] _mem_stq_incoming_e_WIRE_0_bits_addr_bits = mem_stq_incoming_e_out_bits_addr_bits; // @[util.scala:106:23] wire _mem_stq_incoming_e_WIRE_0_bits_addr_is_virtual = mem_stq_incoming_e_out_bits_addr_is_virtual; // @[util.scala:106:23] wire _mem_stq_incoming_e_WIRE_0_bits_data_valid = mem_stq_incoming_e_out_bits_data_valid; // @[util.scala:106:23] wire [63:0] _mem_stq_incoming_e_WIRE_0_bits_data_bits = mem_stq_incoming_e_out_bits_data_bits; // @[util.scala:106:23] wire _mem_stq_incoming_e_WIRE_0_bits_committed = mem_stq_incoming_e_out_bits_committed; // @[util.scala:106:23] wire _mem_stq_incoming_e_WIRE_0_bits_succeeded = mem_stq_incoming_e_out_bits_succeeded; // @[util.scala:106:23] wire [63:0] _mem_stq_incoming_e_WIRE_0_bits_debug_wb_data = mem_stq_incoming_e_out_bits_debug_wb_data; // @[util.scala:106:23] wire [7:0] _mem_stq_incoming_e_out_bits_uop_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:85:27, :89:23] assign _mem_stq_incoming_e_out_bits_uop_br_mask_T_1 = stq_incoming_e_0_bits_uop_br_mask & _mem_stq_incoming_e_out_bits_uop_br_mask_T; // @[util.scala:89:{21,23}] assign mem_stq_incoming_e_out_bits_uop_br_mask = _mem_stq_incoming_e_out_bits_uop_br_mask_T_1; // @[util.scala:89:21, :106:23] wire [7:0] _mem_stq_incoming_e_out_valid_T = io_core_brupdate_b1_mispredict_mask_0 & stq_incoming_e_0_bits_uop_br_mask; // @[util.scala:118:51] wire _mem_stq_incoming_e_out_valid_T_1 = \|_mem_stq_incoming_e_out_valid_T; // @[util.scala:118:{51,59}] wire _mem_stq_incoming_e_out_valid_T_2 = ~_mem_stq_incoming_e_out_valid_T_1; // @[util.scala:108:34, :118:59] assign _mem_stq_incoming_e_out_valid_T_3 = stq_incoming_e_0_valid & _mem_stq_incoming_e_out_valid_T_2; // @[util.scala:108:{31,34}] assign mem_stq_incoming_e_out_valid = _mem_stq_incoming_e_out_valid_T_3; // @[util.scala:106:23, :108:31] reg mem_stq_incoming_e_0_valid; // @[lsu.scala:911:37] reg [6:0] mem_stq_incoming_e_0_bits_uop_uopc; // @[lsu.scala:911:37] reg [31:0] mem_stq_incoming_e_0_bits_uop_inst; // @[lsu.scala:911:37] reg [31:0] mem_stq_incoming_e_0_bits_uop_debug_inst; // @[lsu.scala:911:37] reg mem_stq_incoming_e_0_bits_uop_is_rvc; // @[lsu.scala:911:37] reg [39:0] mem_stq_incoming_e_0_bits_uop_debug_pc; // @[lsu.scala:911:37] reg [2:0] mem_stq_incoming_e_0_bits_uop_iq_type; // @[lsu.scala:911:37] reg [9:0] mem_stq_incoming_e_0_bits_uop_fu_code; // @[lsu.scala:911:37] reg [3:0] mem_stq_incoming_e_0_bits_uop_ctrl_br_type; // @[lsu.scala:911:37] reg [1:0] mem_stq_incoming_e_0_bits_uop_ctrl_op1_sel; // @[lsu.scala:911:37] reg [2:0] mem_stq_incoming_e_0_bits_uop_ctrl_op2_sel; // @[lsu.scala:911:37] reg [2:0] mem_stq_incoming_e_0_bits_uop_ctrl_imm_sel; // @[lsu.scala:911:37] reg [4:0] mem_stq_incoming_e_0_bits_uop_ctrl_op_fcn; // @[lsu.scala:911:37] reg mem_stq_incoming_e_0_bits_uop_ctrl_fcn_dw; // @[lsu.scala:911:37] reg [2:0] mem_stq_incoming_e_0_bits_uop_ctrl_csr_cmd; // @[lsu.scala:911:37] reg mem_stq_incoming_e_0_bits_uop_ctrl_is_load; // @[lsu.scala:911:37] reg mem_stq_incoming_e_0_bits_uop_ctrl_is_sta; // @[lsu.scala:911:37] reg mem_stq_incoming_e_0_bits_uop_ctrl_is_std; // @[lsu.scala:911:37] reg [1:0] mem_stq_incoming_e_0_bits_uop_iw_state; // @[lsu.scala:911:37] reg mem_stq_incoming_e_0_bits_uop_iw_p1_poisoned; // @[lsu.scala:911:37] reg mem_stq_incoming_e_0_bits_uop_iw_p2_poisoned; // @[lsu.scala:911:37] reg mem_stq_incoming_e_0_bits_uop_is_br; // @[lsu.scala:911:37] reg mem_stq_incoming_e_0_bits_uop_is_jalr; // @[lsu.scala:911:37] reg mem_stq_incoming_e_0_bits_uop_is_jal; // @[lsu.scala:911:37] reg mem_stq_incoming_e_0_bits_uop_is_sfb; // @[lsu.scala:911:37] reg [7:0] mem_stq_incoming_e_0_bits_uop_br_mask; // @[lsu.scala:911:37] reg [2:0] mem_stq_incoming_e_0_bits_uop_br_tag; // @[lsu.scala:911:37] reg [3:0] mem_stq_incoming_e_0_bits_uop_ftq_idx; // @[lsu.scala:911:37] reg mem_stq_incoming_e_0_bits_uop_edge_inst; // @[lsu.scala:911:37] reg [5:0] mem_stq_incoming_e_0_bits_uop_pc_lob; // @[lsu.scala:911:37] reg mem_stq_incoming_e_0_bits_uop_taken; // @[lsu.scala:911:37] reg [19:0] mem_stq_incoming_e_0_bits_uop_imm_packed; // @[lsu.scala:911:37] reg [11:0] mem_stq_incoming_e_0_bits_uop_csr_addr; // @[lsu.scala:911:37] reg [4:0] mem_stq_incoming_e_0_bits_uop_rob_idx; // @[lsu.scala:911:37] reg [2:0] mem_stq_incoming_e_0_bits_uop_ldq_idx; // @[lsu.scala:911:37] reg [2:0] mem_stq_incoming_e_0_bits_uop_stq_idx; // @[lsu.scala:911:37] reg [1:0] mem_stq_incoming_e_0_bits_uop_rxq_idx; // @[lsu.scala:911:37] reg [5:0] mem_stq_incoming_e_0_bits_uop_pdst; // @[lsu.scala:911:37] reg [5:0] mem_stq_incoming_e_0_bits_uop_prs1; // @[lsu.scala:911:37] reg [5:0] mem_stq_incoming_e_0_bits_uop_prs2; // @[lsu.scala:911:37] reg [5:0] mem_stq_incoming_e_0_bits_uop_prs3; // @[lsu.scala:911:37] reg [3:0] mem_stq_incoming_e_0_bits_uop_ppred; // @[lsu.scala:911:37] reg mem_stq_incoming_e_0_bits_uop_prs1_busy; // @[lsu.scala:911:37] reg mem_stq_incoming_e_0_bits_uop_prs2_busy; // @[lsu.scala:911:37] reg mem_stq_incoming_e_0_bits_uop_prs3_busy; // @[lsu.scala:911:37] reg mem_stq_incoming_e_0_bits_uop_ppred_busy; // @[lsu.scala:911:37] reg [5:0] mem_stq_incoming_e_0_bits_uop_stale_pdst; // @[lsu.scala:911:37] reg mem_stq_incoming_e_0_bits_uop_exception; // @[lsu.scala:911:37] reg [63:0] mem_stq_incoming_e_0_bits_uop_exc_cause; // @[lsu.scala:911:37] reg mem_stq_incoming_e_0_bits_uop_bypassable; // @[lsu.scala:911:37] reg [4:0] mem_stq_incoming_e_0_bits_uop_mem_cmd; // @[lsu.scala:911:37] reg [1:0] mem_stq_incoming_e_0_bits_uop_mem_size; // @[lsu.scala:911:37] reg mem_stq_incoming_e_0_bits_uop_mem_signed; // @[lsu.scala:911:37] reg mem_stq_incoming_e_0_bits_uop_is_fence; // @[lsu.scala:911:37] reg mem_stq_incoming_e_0_bits_uop_is_fencei; // @[lsu.scala:911:37] reg mem_stq_incoming_e_0_bits_uop_is_amo; // @[lsu.scala:911:37] reg mem_stq_incoming_e_0_bits_uop_uses_ldq; // @[lsu.scala:911:37] reg mem_stq_incoming_e_0_bits_uop_uses_stq; // @[lsu.scala:911:37] reg mem_stq_incoming_e_0_bits_uop_is_sys_pc2epc; // @[lsu.scala:911:37] reg mem_stq_incoming_e_0_bits_uop_is_unique; // @[lsu.scala:911:37] reg mem_stq_incoming_e_0_bits_uop_flush_on_commit; // @[lsu.scala:911:37] reg mem_stq_incoming_e_0_bits_uop_ldst_is_rs1; // @[lsu.scala:911:37] reg [5:0] mem_stq_incoming_e_0_bits_uop_ldst; // @[lsu.scala:911:37] reg [5:0] mem_stq_incoming_e_0_bits_uop_lrs1; // @[lsu.scala:911:37] reg [5:0] mem_stq_incoming_e_0_bits_uop_lrs2; // @[lsu.scala:911:37] reg [5:0] mem_stq_incoming_e_0_bits_uop_lrs3; // @[lsu.scala:911:37] reg mem_stq_incoming_e_0_bits_uop_ldst_val; // @[lsu.scala:911:37] reg [1:0] mem_stq_incoming_e_0_bits_uop_dst_rtype; // @[lsu.scala:911:37] reg [1:0] mem_stq_incoming_e_0_bits_uop_lrs1_rtype; // @[lsu.scala:911:37] reg [1:0] mem_stq_incoming_e_0_bits_uop_lrs2_rtype; // @[lsu.scala:911:37] reg mem_stq_incoming_e_0_bits_uop_frs3_en; // @[lsu.scala:911:37] reg mem_stq_incoming_e_0_bits_uop_fp_val; // @[lsu.scala:911:37] reg mem_stq_incoming_e_0_bits_uop_fp_single; // @[lsu.scala:911:37] reg mem_stq_incoming_e_0_bits_uop_xcpt_pf_if; // @[lsu.scala:911:37] reg mem_stq_incoming_e_0_bits_uop_xcpt_ae_if; // @[lsu.scala:911:37] reg mem_stq_incoming_e_0_bits_uop_xcpt_ma_if; // @[lsu.scala:911:37] reg mem_stq_incoming_e_0_bits_uop_bp_debug_if; // @[lsu.scala:911:37] reg mem_stq_incoming_e_0_bits_uop_bp_xcpt_if; // @[lsu.scala:911:37] reg [1:0] mem_stq_incoming_e_0_bits_uop_debug_fsrc; // @[lsu.scala:911:37] reg [1:0] mem_stq_incoming_e_0_bits_uop_debug_tsrc; // @[lsu.scala:911:37] reg mem_stq_incoming_e_0_bits_addr_valid; // @[lsu.scala:911:37] reg [39:0] mem_stq_incoming_e_0_bits_addr_bits; // @[lsu.scala:911:37] reg mem_stq_incoming_e_0_bits_addr_is_virtual; // @[lsu.scala:911:37] reg mem_stq_incoming_e_0_bits_data_valid; // @[lsu.scala:911:37] reg [63:0] mem_stq_incoming_e_0_bits_data_bits; // @[lsu.scala:911:37] reg mem_stq_incoming_e_0_bits_committed; // @[lsu.scala:911:37] reg mem_stq_incoming_e_0_bits_succeeded; // @[lsu.scala:911:37] reg [63:0] mem_stq_incoming_e_0_bits_debug_wb_data; // @[lsu.scala:911:37] wire _mem_ldq_wakeup_e_out_valid_T_3; // @[util.scala:108:31] wire [7:0] _mem_ldq_wakeup_e_out_bits_uop_br_mask_T_1; // @[util.scala:89:21] wire [7:0] mem_ldq_wakeup_e_out_bits_uop_br_mask; // @[util.scala:106:23] wire mem_ldq_wakeup_e_out_valid; // @[util.scala:106:23] wire [7:0] _mem_ldq_wakeup_e_out_bits_uop_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:85:27, :89:23] assign _mem_ldq_wakeup_e_out_bits_uop_br_mask_T_1 = _GEN_118[_ldq_wakeup_e_T_1] & _mem_ldq_wakeup_e_out_bits_uop_br_mask_T; // @[util.scala:89:{21,23}] assign mem_ldq_wakeup_e_out_bits_uop_br_mask = _mem_ldq_wakeup_e_out_bits_uop_br_mask_T_1; // @[util.scala:89:21, :106:23] wire _mem_ldq_wakeup_e_out_valid_T_1 = \|_mem_ldq_wakeup_e_out_valid_T; // @[util.scala:118:{51,59}] wire _mem_ldq_wakeup_e_out_valid_T_2 = ~_mem_ldq_wakeup_e_out_valid_T_1; // @[util.scala:108:34, :118:59] assign _mem_ldq_wakeup_e_out_valid_T_3 = _GEN_92[_ldq_wakeup_e_T_1] & _mem_ldq_wakeup_e_out_valid_T_2; // @[util.scala:108:{31,34}] assign mem_ldq_wakeup_e_out_valid = _mem_ldq_wakeup_e_out_valid_T_3; // @[util.scala:106:23, :108:31] reg mem_ldq_wakeup_e_valid; // @[lsu.scala:912:37] reg [6:0] mem_ldq_wakeup_e_bits_uop_uopc; // @[lsu.scala:912:37] reg [31:0] mem_ldq_wakeup_e_bits_uop_inst; // @[lsu.scala:912:37] reg [31:0] mem_ldq_wakeup_e_bits_uop_debug_inst; // @[lsu.scala:912:37] reg mem_ldq_wakeup_e_bits_uop_is_rvc; // @[lsu.scala:912:37] reg [39:0] mem_ldq_wakeup_e_bits_uop_debug_pc; // @[lsu.scala:912:37] reg [2:0] mem_ldq_wakeup_e_bits_uop_iq_type; // @[lsu.scala:912:37] reg [9:0] mem_ldq_wakeup_e_bits_uop_fu_code; // @[lsu.scala:912:37] reg [3:0] mem_ldq_wakeup_e_bits_uop_ctrl_br_type; // @[lsu.scala:912:37] reg [1:0] mem_ldq_wakeup_e_bits_uop_ctrl_op1_sel; // @[lsu.scala:912:37] reg [2:0] mem_ldq_wakeup_e_bits_uop_ctrl_op2_sel; // @[lsu.scala:912:37] reg [2:0] mem_ldq_wakeup_e_bits_uop_ctrl_imm_sel; // @[lsu.scala:912:37] reg [4:0] mem_ldq_wakeup_e_bits_uop_ctrl_op_fcn; // @[lsu.scala:912:37] reg mem_ldq_wakeup_e_bits_uop_ctrl_fcn_dw; // @[lsu.scala:912:37] reg [2:0] mem_ldq_wakeup_e_bits_uop_ctrl_csr_cmd; // @[lsu.scala:912:37] reg mem_ldq_wakeup_e_bits_uop_ctrl_is_load; // @[lsu.scala:912:37] reg mem_ldq_wakeup_e_bits_uop_ctrl_is_sta; // @[lsu.scala:912:37] reg mem_ldq_wakeup_e_bits_uop_ctrl_is_std; // @[lsu.scala:912:37] reg [1:0] mem_ldq_wakeup_e_bits_uop_iw_state; // @[lsu.scala:912:37] reg mem_ldq_wakeup_e_bits_uop_iw_p1_poisoned; // @[lsu.scala:912:37] reg mem_ldq_wakeup_e_bits_uop_iw_p2_poisoned; // @[lsu.scala:912:37] reg mem_ldq_wakeup_e_bits_uop_is_br; // @[lsu.scala:912:37] reg mem_ldq_wakeup_e_bits_uop_is_jalr; // @[lsu.scala:912:37] reg mem_ldq_wakeup_e_bits_uop_is_jal; // @[lsu.scala:912:37] reg mem_ldq_wakeup_e_bits_uop_is_sfb; // @[lsu.scala:912:37] reg [7:0] mem_ldq_wakeup_e_bits_uop_br_mask; // @[lsu.scala:912:37] reg [2:0] mem_ldq_wakeup_e_bits_uop_br_tag; // @[lsu.scala:912:37] reg [3:0] mem_ldq_wakeup_e_bits_uop_ftq_idx; // @[lsu.scala:912:37] reg mem_ldq_wakeup_e_bits_uop_edge_inst; // @[lsu.scala:912:37] reg [5:0] mem_ldq_wakeup_e_bits_uop_pc_lob; // @[lsu.scala:912:37] reg mem_ldq_wakeup_e_bits_uop_taken; // @[lsu.scala:912:37] reg [19:0] mem_ldq_wakeup_e_bits_uop_imm_packed; // @[lsu.scala:912:37] reg [11:0] mem_ldq_wakeup_e_bits_uop_csr_addr; // @[lsu.scala:912:37] reg [4:0] mem_ldq_wakeup_e_bits_uop_rob_idx; // @[lsu.scala:912:37] reg [2:0] mem_ldq_wakeup_e_bits_uop_ldq_idx; // @[lsu.scala:912:37] reg [2:0] mem_ldq_wakeup_e_bits_uop_stq_idx; // @[lsu.scala:912:37] reg [1:0] mem_ldq_wakeup_e_bits_uop_rxq_idx; // @[lsu.scala:912:37] reg [5:0] mem_ldq_wakeup_e_bits_uop_pdst; // @[lsu.scala:912:37] reg [5:0] mem_ldq_wakeup_e_bits_uop_prs1; // @[lsu.scala:912:37] reg [5:0] mem_ldq_wakeup_e_bits_uop_prs2; // @[lsu.scala:912:37] reg [5:0] mem_ldq_wakeup_e_bits_uop_prs3; // @[lsu.scala:912:37] reg [3:0] mem_ldq_wakeup_e_bits_uop_ppred; // @[lsu.scala:912:37] reg mem_ldq_wakeup_e_bits_uop_prs1_busy; // @[lsu.scala:912:37] reg mem_ldq_wakeup_e_bits_uop_prs2_busy; // @[lsu.scala:912:37] reg mem_ldq_wakeup_e_bits_uop_prs3_busy; // @[lsu.scala:912:37] reg mem_ldq_wakeup_e_bits_uop_ppred_busy; // @[lsu.scala:912:37] reg [5:0] mem_ldq_wakeup_e_bits_uop_stale_pdst; // @[lsu.scala:912:37] reg mem_ldq_wakeup_e_bits_uop_exception; // @[lsu.scala:912:37] reg [63:0] mem_ldq_wakeup_e_bits_uop_exc_cause; // @[lsu.scala:912:37] reg mem_ldq_wakeup_e_bits_uop_bypassable; // @[lsu.scala:912:37] reg [4:0] mem_ldq_wakeup_e_bits_uop_mem_cmd; // @[lsu.scala:912:37] reg [1:0] mem_ldq_wakeup_e_bits_uop_mem_size; // @[lsu.scala:912:37] reg mem_ldq_wakeup_e_bits_uop_mem_signed; // @[lsu.scala:912:37] reg mem_ldq_wakeup_e_bits_uop_is_fence; // @[lsu.scala:912:37] reg mem_ldq_wakeup_e_bits_uop_is_fencei; // @[lsu.scala:912:37] reg mem_ldq_wakeup_e_bits_uop_is_amo; // @[lsu.scala:912:37] reg mem_ldq_wakeup_e_bits_uop_uses_ldq; // @[lsu.scala:912:37] reg mem_ldq_wakeup_e_bits_uop_uses_stq; // @[lsu.scala:912:37] reg mem_ldq_wakeup_e_bits_uop_is_sys_pc2epc; // @[lsu.scala:912:37] reg mem_ldq_wakeup_e_bits_uop_is_unique; // @[lsu.scala:912:37] reg mem_ldq_wakeup_e_bits_uop_flush_on_commit; // @[lsu.scala:912:37] reg mem_ldq_wakeup_e_bits_uop_ldst_is_rs1; // @[lsu.scala:912:37] reg [5:0] mem_ldq_wakeup_e_bits_uop_ldst; // @[lsu.scala:912:37] reg [5:0] mem_ldq_wakeup_e_bits_uop_lrs1; // @[lsu.scala:912:37] reg [5:0] mem_ldq_wakeup_e_bits_uop_lrs2; // @[lsu.scala:912:37] reg [5:0] mem_ldq_wakeup_e_bits_uop_lrs3; // @[lsu.scala:912:37] reg mem_ldq_wakeup_e_bits_uop_ldst_val; // @[lsu.scala:912:37] reg [1:0] mem_ldq_wakeup_e_bits_uop_dst_rtype; // @[lsu.scala:912:37] reg [1:0] mem_ldq_wakeup_e_bits_uop_lrs1_rtype; // @[lsu.scala:912:37] reg [1:0] mem_ldq_wakeup_e_bits_uop_lrs2_rtype; // @[lsu.scala:912:37] reg mem_ldq_wakeup_e_bits_uop_frs3_en; // @[lsu.scala:912:37] reg mem_ldq_wakeup_e_bits_uop_fp_val; // @[lsu.scala:912:37] reg mem_ldq_wakeup_e_bits_uop_fp_single; // @[lsu.scala:912:37] reg mem_ldq_wakeup_e_bits_uop_xcpt_pf_if; // @[lsu.scala:912:37] reg mem_ldq_wakeup_e_bits_uop_xcpt_ae_if; // @[lsu.scala:912:37] reg mem_ldq_wakeup_e_bits_uop_xcpt_ma_if; // @[lsu.scala:912:37] reg mem_ldq_wakeup_e_bits_uop_bp_debug_if; // @[lsu.scala:912:37] reg mem_ldq_wakeup_e_bits_uop_bp_xcpt_if; // @[lsu.scala:912:37] reg [1:0] mem_ldq_wakeup_e_bits_uop_debug_fsrc; // @[lsu.scala:912:37] reg [1:0] mem_ldq_wakeup_e_bits_uop_debug_tsrc; // @[lsu.scala:912:37] reg mem_ldq_wakeup_e_bits_addr_valid; // @[lsu.scala:912:37] reg [39:0] mem_ldq_wakeup_e_bits_addr_bits; // @[lsu.scala:912:37] reg mem_ldq_wakeup_e_bits_addr_is_virtual; // @[lsu.scala:912:37] reg mem_ldq_wakeup_e_bits_addr_is_uncacheable; // @[lsu.scala:912:37] reg mem_ldq_wakeup_e_bits_executed; // @[lsu.scala:912:37] reg mem_ldq_wakeup_e_bits_succeeded; // @[lsu.scala:912:37] reg mem_ldq_wakeup_e_bits_order_fail; // @[lsu.scala:912:37] reg mem_ldq_wakeup_e_bits_observed; // @[lsu.scala:912:37] reg [7:0] mem_ldq_wakeup_e_bits_st_dep_mask; // @[lsu.scala:912:37] reg [2:0] mem_ldq_wakeup_e_bits_youngest_stq_idx; // @[lsu.scala:912:37] reg mem_ldq_wakeup_e_bits_forward_std_val; // @[lsu.scala:912:37] reg [2:0] mem_ldq_wakeup_e_bits_forward_stq_idx; // @[lsu.scala:912:37] reg [63:0] mem_ldq_wakeup_e_bits_debug_wb_data; // @[lsu.scala:912:37] wire _mem_ldq_retry_e_out_valid_T_3; // @[util.scala:108:31] wire [7:0] _mem_ldq_retry_e_out_bits_uop_br_mask_T_1; // @[util.scala:89:21] wire [7:0] mem_ldq_retry_e_out_bits_uop_br_mask; // @[util.scala:106:23] wire mem_ldq_retry_e_out_valid; // @[util.scala:106:23] wire [7:0] _mem_ldq_retry_e_out_bits_uop_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:85:27, :89:23] assign _mem_ldq_retry_e_out_bits_uop_br_mask_T_1 = _GEN_118[_ldq_retry_e_T_1] & _mem_ldq_retry_e_out_bits_uop_br_mask_T; // @[util.scala:89:{21,23}] assign mem_ldq_retry_e_out_bits_uop_br_mask = _mem_ldq_retry_e_out_bits_uop_br_mask_T_1; // @[util.scala:89:21, :106:23] wire _mem_ldq_retry_e_out_valid_T_1 = \|_mem_ldq_retry_e_out_valid_T; // @[util.scala:118:{51,59}] wire _mem_ldq_retry_e_out_valid_T_2 = ~_mem_ldq_retry_e_out_valid_T_1; // @[util.scala:108:34, :118:59] assign _mem_ldq_retry_e_out_valid_T_3 = _GEN_92[_ldq_retry_e_T_1] & _mem_ldq_retry_e_out_valid_T_2; // @[util.scala:108:{31,34}] assign mem_ldq_retry_e_out_valid = _mem_ldq_retry_e_out_valid_T_3; // @[util.scala:106:23, :108:31] reg mem_ldq_retry_e_valid; // @[lsu.scala:913:37] reg [6:0] mem_ldq_retry_e_bits_uop_uopc; // @[lsu.scala:913:37] reg [31:0] mem_ldq_retry_e_bits_uop_inst; // @[lsu.scala:913:37] reg [31:0] mem_ldq_retry_e_bits_uop_debug_inst; // @[lsu.scala:913:37] reg mem_ldq_retry_e_bits_uop_is_rvc; // @[lsu.scala:913:37] reg [39:0] mem_ldq_retry_e_bits_uop_debug_pc; // @[lsu.scala:913:37] reg [2:0] mem_ldq_retry_e_bits_uop_iq_type; // @[lsu.scala:913:37] reg [9:0] mem_ldq_retry_e_bits_uop_fu_code; // @[lsu.scala:913:37] reg [3:0] mem_ldq_retry_e_bits_uop_ctrl_br_type; // @[lsu.scala:913:37] reg [1:0] mem_ldq_retry_e_bits_uop_ctrl_op1_sel; // @[lsu.scala:913:37] reg [2:0] mem_ldq_retry_e_bits_uop_ctrl_op2_sel; // @[lsu.scala:913:37] reg [2:0] mem_ldq_retry_e_bits_uop_ctrl_imm_sel; // @[lsu.scala:913:37] reg [4:0] mem_ldq_retry_e_bits_uop_ctrl_op_fcn; // @[lsu.scala:913:37] reg mem_ldq_retry_e_bits_uop_ctrl_fcn_dw; // @[lsu.scala:913:37] reg [2:0] mem_ldq_retry_e_bits_uop_ctrl_csr_cmd; // @[lsu.scala:913:37] reg mem_ldq_retry_e_bits_uop_ctrl_is_load; // @[lsu.scala:913:37] reg mem_ldq_retry_e_bits_uop_ctrl_is_sta; // @[lsu.scala:913:37] reg mem_ldq_retry_e_bits_uop_ctrl_is_std; // @[lsu.scala:913:37] reg [1:0] mem_ldq_retry_e_bits_uop_iw_state; // @[lsu.scala:913:37] reg mem_ldq_retry_e_bits_uop_iw_p1_poisoned; // @[lsu.scala:913:37] reg mem_ldq_retry_e_bits_uop_iw_p2_poisoned; // @[lsu.scala:913:37] reg mem_ldq_retry_e_bits_uop_is_br; // @[lsu.scala:913:37] reg mem_ldq_retry_e_bits_uop_is_jalr; // @[lsu.scala:913:37] reg mem_ldq_retry_e_bits_uop_is_jal; // @[lsu.scala:913:37] reg mem_ldq_retry_e_bits_uop_is_sfb; // @[lsu.scala:913:37] reg [7:0] mem_ldq_retry_e_bits_uop_br_mask; // @[lsu.scala:913:37] reg [2:0] mem_ldq_retry_e_bits_uop_br_tag; // @[lsu.scala:913:37] reg [3:0] mem_ldq_retry_e_bits_uop_ftq_idx; // @[lsu.scala:913:37] reg mem_ldq_retry_e_bits_uop_edge_inst; // @[lsu.scala:913:37] reg [5:0] mem_ldq_retry_e_bits_uop_pc_lob; // @[lsu.scala:913:37] reg mem_ldq_retry_e_bits_uop_taken; // @[lsu.scala:913:37] reg [19:0] mem_ldq_retry_e_bits_uop_imm_packed; // @[lsu.scala:913:37] reg [11:0] mem_ldq_retry_e_bits_uop_csr_addr; // @[lsu.scala:913:37] reg [4:0] mem_ldq_retry_e_bits_uop_rob_idx; // @[lsu.scala:913:37] reg [2:0] mem_ldq_retry_e_bits_uop_ldq_idx; // @[lsu.scala:913:37] reg [2:0] mem_ldq_retry_e_bits_uop_stq_idx; // @[lsu.scala:913:37] reg [1:0] mem_ldq_retry_e_bits_uop_rxq_idx; // @[lsu.scala:913:37] reg [5:0] mem_ldq_retry_e_bits_uop_pdst; // @[lsu.scala:913:37] reg [5:0] mem_ldq_retry_e_bits_uop_prs1; // @[lsu.scala:913:37] reg [5:0] mem_ldq_retry_e_bits_uop_prs2; // @[lsu.scala:913:37] reg [5:0] mem_ldq_retry_e_bits_uop_prs3; // @[lsu.scala:913:37] reg [3:0] mem_ldq_retry_e_bits_uop_ppred; // @[lsu.scala:913:37] reg mem_ldq_retry_e_bits_uop_prs1_busy; // @[lsu.scala:913:37] reg mem_ldq_retry_e_bits_uop_prs2_busy; // @[lsu.scala:913:37] reg mem_ldq_retry_e_bits_uop_prs3_busy; // @[lsu.scala:913:37] reg mem_ldq_retry_e_bits_uop_ppred_busy; // @[lsu.scala:913:37] reg [5:0] mem_ldq_retry_e_bits_uop_stale_pdst; // @[lsu.scala:913:37] reg mem_ldq_retry_e_bits_uop_exception; // @[lsu.scala:913:37] reg [63:0] mem_ldq_retry_e_bits_uop_exc_cause; // @[lsu.scala:913:37] reg mem_ldq_retry_e_bits_uop_bypassable; // @[lsu.scala:913:37] reg [4:0] mem_ldq_retry_e_bits_uop_mem_cmd; // @[lsu.scala:913:37] reg [1:0] mem_ldq_retry_e_bits_uop_mem_size; // @[lsu.scala:913:37] reg mem_ldq_retry_e_bits_uop_mem_signed; // @[lsu.scala:913:37] reg mem_ldq_retry_e_bits_uop_is_fence; // @[lsu.scala:913:37] reg mem_ldq_retry_e_bits_uop_is_fencei; // @[lsu.scala:913:37] reg mem_ldq_retry_e_bits_uop_is_amo; // @[lsu.scala:913:37] reg mem_ldq_retry_e_bits_uop_uses_ldq; // @[lsu.scala:913:37] reg mem_ldq_retry_e_bits_uop_uses_stq; // @[lsu.scala:913:37] reg mem_ldq_retry_e_bits_uop_is_sys_pc2epc; // @[lsu.scala:913:37] reg mem_ldq_retry_e_bits_uop_is_unique; // @[lsu.scala:913:37] reg mem_ldq_retry_e_bits_uop_flush_on_commit; // @[lsu.scala:913:37] reg mem_ldq_retry_e_bits_uop_ldst_is_rs1; // @[lsu.scala:913:37] reg [5:0] mem_ldq_retry_e_bits_uop_ldst; // @[lsu.scala:913:37] reg [5:0] mem_ldq_retry_e_bits_uop_lrs1; // @[lsu.scala:913:37] reg [5:0] mem_ldq_retry_e_bits_uop_lrs2; // @[lsu.scala:913:37] reg [5:0] mem_ldq_retry_e_bits_uop_lrs3; // @[lsu.scala:913:37] reg mem_ldq_retry_e_bits_uop_ldst_val; // @[lsu.scala:913:37] reg [1:0] mem_ldq_retry_e_bits_uop_dst_rtype; // @[lsu.scala:913:37] reg [1:0] mem_ldq_retry_e_bits_uop_lrs1_rtype; // @[lsu.scala:913:37] reg [1:0] mem_ldq_retry_e_bits_uop_lrs2_rtype; // @[lsu.scala:913:37] reg mem_ldq_retry_e_bits_uop_frs3_en; // @[lsu.scala:913:37] reg mem_ldq_retry_e_bits_uop_fp_val; // @[lsu.scala:913:37] reg mem_ldq_retry_e_bits_uop_fp_single; // @[lsu.scala:913:37] reg mem_ldq_retry_e_bits_uop_xcpt_pf_if; // @[lsu.scala:913:37] reg mem_ldq_retry_e_bits_uop_xcpt_ae_if; // @[lsu.scala:913:37] reg mem_ldq_retry_e_bits_uop_xcpt_ma_if; // @[lsu.scala:913:37] reg mem_ldq_retry_e_bits_uop_bp_debug_if; // @[lsu.scala:913:37] reg mem_ldq_retry_e_bits_uop_bp_xcpt_if; // @[lsu.scala:913:37] reg [1:0] mem_ldq_retry_e_bits_uop_debug_fsrc; // @[lsu.scala:913:37] reg [1:0] mem_ldq_retry_e_bits_uop_debug_tsrc; // @[lsu.scala:913:37] reg mem_ldq_retry_e_bits_addr_valid; // @[lsu.scala:913:37] reg [39:0] mem_ldq_retry_e_bits_addr_bits; // @[lsu.scala:913:37] reg mem_ldq_retry_e_bits_addr_is_virtual; // @[lsu.scala:913:37] reg mem_ldq_retry_e_bits_addr_is_uncacheable; // @[lsu.scala:913:37] reg mem_ldq_retry_e_bits_executed; // @[lsu.scala:913:37] reg mem_ldq_retry_e_bits_succeeded; // @[lsu.scala:913:37] reg mem_ldq_retry_e_bits_order_fail; // @[lsu.scala:913:37] reg mem_ldq_retry_e_bits_observed; // @[lsu.scala:913:37] reg [7:0] mem_ldq_retry_e_bits_st_dep_mask; // @[lsu.scala:913:37] reg [2:0] mem_ldq_retry_e_bits_youngest_stq_idx; // @[lsu.scala:913:37] reg mem_ldq_retry_e_bits_forward_std_val; // @[lsu.scala:913:37] reg [2:0] mem_ldq_retry_e_bits_forward_stq_idx; // @[lsu.scala:913:37] reg [63:0] mem_ldq_retry_e_bits_debug_wb_data; // @[lsu.scala:913:37] wire _mem_stq_retry_e_out_valid_T_3; // @[util.scala:108:31] wire [7:0] _mem_stq_retry_e_out_bits_uop_br_mask_T_1; // @[util.scala:89:21] wire [7:0] mem_stq_retry_e_out_bits_uop_br_mask; // @[util.scala:106:23] wire mem_stq_retry_e_out_valid; // @[util.scala:106:23] wire [7:0] _mem_stq_retry_e_out_bits_uop_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:85:27, :89:23] assign _mem_stq_retry_e_out_bits_uop_br_mask_T_1 = _GEN_25[_stq_retry_e_T_1] & _mem_stq_retry_e_out_bits_uop_br_mask_T; // @[util.scala:89:{21,23}] assign mem_stq_retry_e_out_bits_uop_br_mask = _mem_stq_retry_e_out_bits_uop_br_mask_T_1; // @[util.scala:89:21, :106:23] wire _mem_stq_retry_e_out_valid_T_1 = \|_mem_stq_retry_e_out_valid_T; // @[util.scala:118:{51,59}] wire _mem_stq_retry_e_out_valid_T_2 = ~_mem_stq_retry_e_out_valid_T_1; // @[util.scala:108:34, :118:59] assign _mem_stq_retry_e_out_valid_T_3 = _GEN[_stq_retry_e_T_1] & _mem_stq_retry_e_out_valid_T_2; // @[util.scala:108:{31,34}] assign mem_stq_retry_e_out_valid = _mem_stq_retry_e_out_valid_T_3; // @[util.scala:106:23, :108:31] reg mem_stq_retry_e_valid; // @[lsu.scala:914:37] reg [6:0] mem_stq_retry_e_bits_uop_uopc; // @[lsu.scala:914:37] reg [31:0] mem_stq_retry_e_bits_uop_inst; // @[lsu.scala:914:37] reg [31:0] mem_stq_retry_e_bits_uop_debug_inst; // @[lsu.scala:914:37] reg mem_stq_retry_e_bits_uop_is_rvc; // @[lsu.scala:914:37] reg [39:0] mem_stq_retry_e_bits_uop_debug_pc; // @[lsu.scala:914:37] reg [2:0] mem_stq_retry_e_bits_uop_iq_type; // @[lsu.scala:914:37] reg [9:0] mem_stq_retry_e_bits_uop_fu_code; // @[lsu.scala:914:37] reg [3:0] mem_stq_retry_e_bits_uop_ctrl_br_type; // @[lsu.scala:914:37] reg [1:0] mem_stq_retry_e_bits_uop_ctrl_op1_sel; // @[lsu.scala:914:37] reg [2:0] mem_stq_retry_e_bits_uop_ctrl_op2_sel; // @[lsu.scala:914:37] reg [2:0] mem_stq_retry_e_bits_uop_ctrl_imm_sel; // @[lsu.scala:914:37] reg [4:0] mem_stq_retry_e_bits_uop_ctrl_op_fcn; // @[lsu.scala:914:37] reg mem_stq_retry_e_bits_uop_ctrl_fcn_dw; // @[lsu.scala:914:37] reg [2:0] mem_stq_retry_e_bits_uop_ctrl_csr_cmd; // @[lsu.scala:914:37] reg mem_stq_retry_e_bits_uop_ctrl_is_load; // @[lsu.scala:914:37] reg mem_stq_retry_e_bits_uop_ctrl_is_sta; // @[lsu.scala:914:37] reg mem_stq_retry_e_bits_uop_ctrl_is_std; // @[lsu.scala:914:37] reg [1:0] mem_stq_retry_e_bits_uop_iw_state; // @[lsu.scala:914:37] reg mem_stq_retry_e_bits_uop_iw_p1_poisoned; // @[lsu.scala:914:37] reg mem_stq_retry_e_bits_uop_iw_p2_poisoned; // @[lsu.scala:914:37] reg mem_stq_retry_e_bits_uop_is_br; // @[lsu.scala:914:37] reg mem_stq_retry_e_bits_uop_is_jalr; // @[lsu.scala:914:37] reg mem_stq_retry_e_bits_uop_is_jal; // @[lsu.scala:914:37] reg mem_stq_retry_e_bits_uop_is_sfb; // @[lsu.scala:914:37] reg [7:0] mem_stq_retry_e_bits_uop_br_mask; // @[lsu.scala:914:37] reg [2:0] mem_stq_retry_e_bits_uop_br_tag; // @[lsu.scala:914:37] reg [3:0] mem_stq_retry_e_bits_uop_ftq_idx; // @[lsu.scala:914:37] reg mem_stq_retry_e_bits_uop_edge_inst; // @[lsu.scala:914:37] reg [5:0] mem_stq_retry_e_bits_uop_pc_lob; // @[lsu.scala:914:37] reg mem_stq_retry_e_bits_uop_taken; // @[lsu.scala:914:37] reg [19:0] mem_stq_retry_e_bits_uop_imm_packed; // @[lsu.scala:914:37] reg [11:0] mem_stq_retry_e_bits_uop_csr_addr; // @[lsu.scala:914:37] reg [4:0] mem_stq_retry_e_bits_uop_rob_idx; // @[lsu.scala:914:37] reg [2:0] mem_stq_retry_e_bits_uop_ldq_idx; // @[lsu.scala:914:37] reg [2:0] mem_stq_retry_e_bits_uop_stq_idx; // @[lsu.scala:914:37] reg [1:0] mem_stq_retry_e_bits_uop_rxq_idx; // @[lsu.scala:914:37] reg [5:0] mem_stq_retry_e_bits_uop_pdst; // @[lsu.scala:914:37] reg [5:0] mem_stq_retry_e_bits_uop_prs1; // @[lsu.scala:914:37] reg [5:0] mem_stq_retry_e_bits_uop_prs2; // @[lsu.scala:914:37] reg [5:0] mem_stq_retry_e_bits_uop_prs3; // @[lsu.scala:914:37] reg [3:0] mem_stq_retry_e_bits_uop_ppred; // @[lsu.scala:914:37] reg mem_stq_retry_e_bits_uop_prs1_busy; // @[lsu.scala:914:37] reg mem_stq_retry_e_bits_uop_prs2_busy; // @[lsu.scala:914:37] reg mem_stq_retry_e_bits_uop_prs3_busy; // @[lsu.scala:914:37] reg mem_stq_retry_e_bits_uop_ppred_busy; // @[lsu.scala:914:37] reg [5:0] mem_stq_retry_e_bits_uop_stale_pdst; // @[lsu.scala:914:37] reg mem_stq_retry_e_bits_uop_exception; // @[lsu.scala:914:37] reg [63:0] mem_stq_retry_e_bits_uop_exc_cause; // @[lsu.scala:914:37] reg mem_stq_retry_e_bits_uop_bypassable; // @[lsu.scala:914:37] reg [4:0] mem_stq_retry_e_bits_uop_mem_cmd; // @[lsu.scala:914:37] reg [1:0] mem_stq_retry_e_bits_uop_mem_size; // @[lsu.scala:914:37] reg mem_stq_retry_e_bits_uop_mem_signed; // @[lsu.scala:914:37] reg mem_stq_retry_e_bits_uop_is_fence; // @[lsu.scala:914:37] reg mem_stq_retry_e_bits_uop_is_fencei; // @[lsu.scala:914:37] reg mem_stq_retry_e_bits_uop_is_amo; // @[lsu.scala:914:37] reg mem_stq_retry_e_bits_uop_uses_ldq; // @[lsu.scala:914:37] reg mem_stq_retry_e_bits_uop_uses_stq; // @[lsu.scala:914:37] reg mem_stq_retry_e_bits_uop_is_sys_pc2epc; // @[lsu.scala:914:37] reg mem_stq_retry_e_bits_uop_is_unique; // @[lsu.scala:914:37] reg mem_stq_retry_e_bits_uop_flush_on_commit; // @[lsu.scala:914:37] reg mem_stq_retry_e_bits_uop_ldst_is_rs1; // @[lsu.scala:914:37] reg [5:0] mem_stq_retry_e_bits_uop_ldst; // @[lsu.scala:914:37] reg [5:0] mem_stq_retry_e_bits_uop_lrs1; // @[lsu.scala:914:37] reg [5:0] mem_stq_retry_e_bits_uop_lrs2; // @[lsu.scala:914:37] reg [5:0] mem_stq_retry_e_bits_uop_lrs3; // @[lsu.scala:914:37] reg mem_stq_retry_e_bits_uop_ldst_val; // @[lsu.scala:914:37] reg [1:0] mem_stq_retry_e_bits_uop_dst_rtype; // @[lsu.scala:914:37] reg [1:0] mem_stq_retry_e_bits_uop_lrs1_rtype; // @[lsu.scala:914:37] reg [1:0] mem_stq_retry_e_bits_uop_lrs2_rtype; // @[lsu.scala:914:37] reg mem_stq_retry_e_bits_uop_frs3_en; // @[lsu.scala:914:37] reg mem_stq_retry_e_bits_uop_fp_val; // @[lsu.scala:914:37] reg mem_stq_retry_e_bits_uop_fp_single; // @[lsu.scala:914:37] reg mem_stq_retry_e_bits_uop_xcpt_pf_if; // @[lsu.scala:914:37] reg mem_stq_retry_e_bits_uop_xcpt_ae_if; // @[lsu.scala:914:37] reg mem_stq_retry_e_bits_uop_xcpt_ma_if; // @[lsu.scala:914:37] reg mem_stq_retry_e_bits_uop_bp_debug_if; // @[lsu.scala:914:37] reg mem_stq_retry_e_bits_uop_bp_xcpt_if; // @[lsu.scala:914:37] reg [1:0] mem_stq_retry_e_bits_uop_debug_fsrc; // @[lsu.scala:914:37] reg [1:0] mem_stq_retry_e_bits_uop_debug_tsrc; // @[lsu.scala:914:37] reg mem_stq_retry_e_bits_addr_valid; // @[lsu.scala:914:37] reg [39:0] mem_stq_retry_e_bits_addr_bits; // @[lsu.scala:914:37] reg mem_stq_retry_e_bits_addr_is_virtual; // @[lsu.scala:914:37] reg mem_stq_retry_e_bits_data_valid; // @[lsu.scala:914:37] reg [63:0] mem_stq_retry_e_bits_data_bits; // @[lsu.scala:914:37] reg mem_stq_retry_e_bits_committed; // @[lsu.scala:914:37] reg mem_stq_retry_e_bits_succeeded; // @[lsu.scala:914:37] reg [63:0] mem_stq_retry_e_bits_debug_wb_data; // @[lsu.scala:914:37] wire _mem_ldq_e_T_valid = fired_load_wakeup_0 & mem_ldq_wakeup_e_valid; // @[lsu.scala:263:49, :912:37, :918:33] wire [6:0] _mem_ldq_e_T_bits_uop_uopc = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_uopc : 7'h0; // @[lsu.scala:263:49, :912:37, :918:33] wire [31:0] _mem_ldq_e_T_bits_uop_inst = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_inst : 32'h0; // @[lsu.scala:263:49, :912:37, :918:33] wire [31:0] _mem_ldq_e_T_bits_uop_debug_inst = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_debug_inst : 32'h0; // @[lsu.scala:263:49, :912:37, :918:33] wire _mem_ldq_e_T_bits_uop_is_rvc = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_is_rvc; // @[lsu.scala:263:49, :912:37, :918:33] wire [39:0] _mem_ldq_e_T_bits_uop_debug_pc = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_debug_pc : 40'h0; // @[lsu.scala:263:49, :912:37, :918:33] wire [2:0] _mem_ldq_e_T_bits_uop_iq_type = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_iq_type : 3'h0; // @[lsu.scala:263:49, :912:37, :918:33] wire [9:0] _mem_ldq_e_T_bits_uop_fu_code = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_fu_code : 10'h0; // @[lsu.scala:263:49, :912:37, :918:33] wire [3:0] _mem_ldq_e_T_bits_uop_ctrl_br_type = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_ctrl_br_type : 4'h0; // @[lsu.scala:263:49, :912:37, :918:33] wire [1:0] _mem_ldq_e_T_bits_uop_ctrl_op1_sel = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_ctrl_op1_sel : 2'h0; // @[lsu.scala:263:49, :912:37, :918:33] wire [2:0] _mem_ldq_e_T_bits_uop_ctrl_op2_sel = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_ctrl_op2_sel : 3'h0; // @[lsu.scala:263:49, :912:37, :918:33] wire [2:0] _mem_ldq_e_T_bits_uop_ctrl_imm_sel = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_ctrl_imm_sel : 3'h0; // @[lsu.scala:263:49, :912:37, :918:33] wire [4:0] _mem_ldq_e_T_bits_uop_ctrl_op_fcn = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_ctrl_op_fcn : 5'h0; // @[lsu.scala:263:49, :912:37, :918:33] wire _mem_ldq_e_T_bits_uop_ctrl_fcn_dw = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_ctrl_fcn_dw; // @[lsu.scala:263:49, :912:37, :918:33] wire [2:0] _mem_ldq_e_T_bits_uop_ctrl_csr_cmd = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_ctrl_csr_cmd : 3'h0; // @[lsu.scala:263:49, :912:37, :918:33] wire _mem_ldq_e_T_bits_uop_ctrl_is_load = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_ctrl_is_load; // @[lsu.scala:263:49, :912:37, :918:33] wire _mem_ldq_e_T_bits_uop_ctrl_is_sta = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_ctrl_is_sta; // @[lsu.scala:263:49, :912:37, :918:33] wire _mem_ldq_e_T_bits_uop_ctrl_is_std = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_ctrl_is_std; // @[lsu.scala:263:49, :912:37, :918:33] wire [1:0] _mem_ldq_e_T_bits_uop_iw_state = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_iw_state : 2'h0; // @[lsu.scala:263:49, :912:37, :918:33] wire _mem_ldq_e_T_bits_uop_iw_p1_poisoned = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_iw_p1_poisoned; // @[lsu.scala:263:49, :912:37, :918:33] wire _mem_ldq_e_T_bits_uop_iw_p2_poisoned = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_iw_p2_poisoned; // @[lsu.scala:263:49, :912:37, :918:33] wire _mem_ldq_e_T_bits_uop_is_br = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_is_br; // @[lsu.scala:263:49, :912:37, :918:33] wire _mem_ldq_e_T_bits_uop_is_jalr = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_is_jalr; // @[lsu.scala:263:49, :912:37, :918:33] wire _mem_ldq_e_T_bits_uop_is_jal = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_is_jal; // @[lsu.scala:263:49, :912:37, :918:33] wire _mem_ldq_e_T_bits_uop_is_sfb = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_is_sfb; // @[lsu.scala:263:49, :912:37, :918:33] wire [7:0] _mem_ldq_e_T_bits_uop_br_mask = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_br_mask : 8'h0; // @[lsu.scala:263:49, :912:37, :918:33] wire [2:0] _mem_ldq_e_T_bits_uop_br_tag = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_br_tag : 3'h0; // @[lsu.scala:263:49, :912:37, :918:33] wire [3:0] _mem_ldq_e_T_bits_uop_ftq_idx = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_ftq_idx : 4'h0; // @[lsu.scala:263:49, :912:37, :918:33] wire _mem_ldq_e_T_bits_uop_edge_inst = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_edge_inst; // @[lsu.scala:263:49, :912:37, :918:33] wire [5:0] _mem_ldq_e_T_bits_uop_pc_lob = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_pc_lob : 6'h0; // @[lsu.scala:263:49, :912:37, :918:33] wire _mem_ldq_e_T_bits_uop_taken = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_taken; // @[lsu.scala:263:49, :912:37, :918:33] wire [19:0] _mem_ldq_e_T_bits_uop_imm_packed = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_imm_packed : 20'h0; // @[lsu.scala:263:49, :912:37, :918:33] wire [11:0] _mem_ldq_e_T_bits_uop_csr_addr = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_csr_addr : 12'h0; // @[lsu.scala:263:49, :912:37, :918:33] wire [4:0] _mem_ldq_e_T_bits_uop_rob_idx = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_rob_idx : 5'h0; // @[lsu.scala:263:49, :912:37, :918:33] wire [2:0] _mem_ldq_e_T_bits_uop_ldq_idx = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_ldq_idx : 3'h0; // @[lsu.scala:263:49, :912:37, :918:33] wire [2:0] _mem_ldq_e_T_bits_uop_stq_idx = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_stq_idx : 3'h0; // @[lsu.scala:263:49, :912:37, :918:33] wire [1:0] _mem_ldq_e_T_bits_uop_rxq_idx = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_rxq_idx : 2'h0; // @[lsu.scala:263:49, :912:37, :918:33] wire [5:0] _mem_ldq_e_T_bits_uop_pdst = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_pdst : 6'h0; // @[lsu.scala:263:49, :912:37, :918:33] wire [5:0] _mem_ldq_e_T_bits_uop_prs1 = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_prs1 : 6'h0; // @[lsu.scala:263:49, :912:37, :918:33] wire [5:0] _mem_ldq_e_T_bits_uop_prs2 = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_prs2 : 6'h0; // @[lsu.scala:263:49, :912:37, :918:33] wire [5:0] _mem_ldq_e_T_bits_uop_prs3 = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_prs3 : 6'h0; // @[lsu.scala:263:49, :912:37, :918:33] wire [3:0] _mem_ldq_e_T_bits_uop_ppred = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_ppred : 4'h0; // @[lsu.scala:263:49, :912:37, :918:33] wire _mem_ldq_e_T_bits_uop_prs1_busy = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_prs1_busy; // @[lsu.scala:263:49, :912:37, :918:33] wire _mem_ldq_e_T_bits_uop_prs2_busy = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_prs2_busy; // @[lsu.scala:263:49, :912:37, :918:33] wire _mem_ldq_e_T_bits_uop_prs3_busy = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_prs3_busy; // @[lsu.scala:263:49, :912:37, :918:33] wire _mem_ldq_e_T_bits_uop_ppred_busy = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_ppred_busy; // @[lsu.scala:263:49, :912:37, :918:33] wire [5:0] _mem_ldq_e_T_bits_uop_stale_pdst = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_stale_pdst : 6'h0; // @[lsu.scala:263:49, :912:37, :918:33] wire _mem_ldq_e_T_bits_uop_exception = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_exception; // @[lsu.scala:263:49, :912:37, :918:33] wire [63:0] _mem_ldq_e_T_bits_uop_exc_cause = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_exc_cause : 64'h0; // @[lsu.scala:263:49, :912:37, :918:33] wire _mem_ldq_e_T_bits_uop_bypassable = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_bypassable; // @[lsu.scala:263:49, :912:37, :918:33] wire [4:0] _mem_ldq_e_T_bits_uop_mem_cmd = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_mem_cmd : 5'h0; // @[lsu.scala:263:49, :912:37, :918:33] wire [1:0] _mem_ldq_e_T_bits_uop_mem_size = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_mem_size : 2'h0; // @[lsu.scala:263:49, :912:37, :918:33] wire _mem_ldq_e_T_bits_uop_mem_signed = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_mem_signed; // @[lsu.scala:263:49, :912:37, :918:33] wire _mem_ldq_e_T_bits_uop_is_fence = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_is_fence; // @[lsu.scala:263:49, :912:37, :918:33] wire _mem_ldq_e_T_bits_uop_is_fencei = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_is_fencei; // @[lsu.scala:263:49, :912:37, :918:33] wire _mem_ldq_e_T_bits_uop_is_amo = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_is_amo; // @[lsu.scala:263:49, :912:37, :918:33] wire _mem_ldq_e_T_bits_uop_uses_ldq = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_uses_ldq; // @[lsu.scala:263:49, :912:37, :918:33] wire _mem_ldq_e_T_bits_uop_uses_stq = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_uses_stq; // @[lsu.scala:263:49, :912:37, :918:33] wire _mem_ldq_e_T_bits_uop_is_sys_pc2epc = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_is_sys_pc2epc; // @[lsu.scala:263:49, :912:37, :918:33] wire _mem_ldq_e_T_bits_uop_is_unique = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_is_unique; // @[lsu.scala:263:49, :912:37, :918:33] wire _mem_ldq_e_T_bits_uop_flush_on_commit = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_flush_on_commit; // @[lsu.scala:263:49, :912:37, :918:33] wire _mem_ldq_e_T_bits_uop_ldst_is_rs1 = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_ldst_is_rs1; // @[lsu.scala:263:49, :912:37, :918:33] wire [5:0] _mem_ldq_e_T_bits_uop_ldst = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_ldst : 6'h0; // @[lsu.scala:263:49, :912:37, :918:33] wire [5:0] _mem_ldq_e_T_bits_uop_lrs1 = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_lrs1 : 6'h0; // @[lsu.scala:263:49, :912:37, :918:33] wire [5:0] _mem_ldq_e_T_bits_uop_lrs2 = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_lrs2 : 6'h0; // @[lsu.scala:263:49, :912:37, :918:33] wire [5:0] _mem_ldq_e_T_bits_uop_lrs3 = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_lrs3 : 6'h0; // @[lsu.scala:263:49, :912:37, :918:33] wire _mem_ldq_e_T_bits_uop_ldst_val = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_ldst_val; // @[lsu.scala:263:49, :912:37, :918:33] wire [1:0] _mem_ldq_e_T_bits_uop_dst_rtype = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_dst_rtype : 2'h0; // @[lsu.scala:263:49, :912:37, :918:33] wire [1:0] _mem_ldq_e_T_bits_uop_lrs1_rtype = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_lrs1_rtype : 2'h0; // @[lsu.scala:263:49, :912:37, :918:33] wire [1:0] _mem_ldq_e_T_bits_uop_lrs2_rtype = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_lrs2_rtype : 2'h0; // @[lsu.scala:263:49, :912:37, :918:33] wire _mem_ldq_e_T_bits_uop_frs3_en = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_frs3_en; // @[lsu.scala:263:49, :912:37, :918:33] wire _mem_ldq_e_T_bits_uop_fp_val = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_fp_val; // @[lsu.scala:263:49, :912:37, :918:33] wire _mem_ldq_e_T_bits_uop_fp_single = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_fp_single; // @[lsu.scala:263:49, :912:37, :918:33] wire _mem_ldq_e_T_bits_uop_xcpt_pf_if = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_xcpt_pf_if; // @[lsu.scala:263:49, :912:37, :918:33] wire _mem_ldq_e_T_bits_uop_xcpt_ae_if = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_xcpt_ae_if; // @[lsu.scala:263:49, :912:37, :918:33] wire _mem_ldq_e_T_bits_uop_xcpt_ma_if = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_xcpt_ma_if; // @[lsu.scala:263:49, :912:37, :918:33] wire _mem_ldq_e_T_bits_uop_bp_debug_if = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_bp_debug_if; // @[lsu.scala:263:49, :912:37, :918:33] wire _mem_ldq_e_T_bits_uop_bp_xcpt_if = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_bp_xcpt_if; // @[lsu.scala:263:49, :912:37, :918:33] wire [1:0] _mem_ldq_e_T_bits_uop_debug_fsrc = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_debug_fsrc : 2'h0; // @[lsu.scala:263:49, :912:37, :918:33] wire [1:0] _mem_ldq_e_T_bits_uop_debug_tsrc = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_debug_tsrc : 2'h0; // @[lsu.scala:263:49, :912:37, :918:33] wire _mem_ldq_e_T_bits_addr_valid = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_addr_valid; // @[lsu.scala:263:49, :912:37, :918:33] wire [39:0] _mem_ldq_e_T_bits_addr_bits = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_addr_bits : 40'h0; // @[lsu.scala:263:49, :912:37, :918:33] wire _mem_ldq_e_T_bits_addr_is_virtual = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_addr_is_virtual; // @[lsu.scala:263:49, :912:37, :918:33] wire _mem_ldq_e_T_bits_addr_is_uncacheable = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_addr_is_uncacheable; // @[lsu.scala:263:49, :912:37, :918:33] wire _mem_ldq_e_T_bits_executed = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_executed; // @[lsu.scala:263:49, :912:37, :918:33] wire _mem_ldq_e_T_bits_succeeded = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_succeeded; // @[lsu.scala:263:49, :912:37, :918:33] wire _mem_ldq_e_T_bits_order_fail = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_order_fail; // @[lsu.scala:263:49, :912:37, :918:33] wire _mem_ldq_e_T_bits_observed = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_observed; // @[lsu.scala:263:49, :912:37, :918:33] wire [7:0] _mem_ldq_e_T_bits_st_dep_mask = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_st_dep_mask : 8'h0; // @[lsu.scala:263:49, :912:37, :918:33] wire [2:0] _mem_ldq_e_T_bits_youngest_stq_idx = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_youngest_stq_idx : 3'h0; // @[lsu.scala:263:49, :912:37, :918:33] wire _mem_ldq_e_T_bits_forward_std_val = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_forward_std_val; // @[lsu.scala:263:49, :912:37, :918:33] wire [2:0] _mem_ldq_e_T_bits_forward_stq_idx = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_forward_stq_idx : 3'h0; // @[lsu.scala:263:49, :912:37, :918:33] wire [63:0] _mem_ldq_e_T_bits_debug_wb_data = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_debug_wb_data : 64'h0; // @[lsu.scala:263:49, :912:37, :918:33] wire _mem_ldq_e_T_1_valid = fired_load_retry_0 ? mem_ldq_retry_e_valid : _mem_ldq_e_T_valid; // @[lsu.scala:263:49, :913:37, :917:33, :918:33] wire [6:0] _mem_ldq_e_T_1_bits_uop_uopc = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_uopc : _mem_ldq_e_T_bits_uop_uopc; // @[lsu.scala:263:49, :913:37, :917:33, :918:33] wire [31:0] _mem_ldq_e_T_1_bits_uop_inst = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_inst : _mem_ldq_e_T_bits_uop_inst; // @[lsu.scala:263:49, :913:37, :917:33, :918:33] wire [31:0] _mem_ldq_e_T_1_bits_uop_debug_inst = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_debug_inst : _mem_ldq_e_T_bits_uop_debug_inst; // @[lsu.scala:263:49, :913:37, :917:33, :918:33] wire _mem_ldq_e_T_1_bits_uop_is_rvc = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_is_rvc : _mem_ldq_e_T_bits_uop_is_rvc; // @[lsu.scala:263:49, :913:37, :917:33, :918:33] wire [39:0] _mem_ldq_e_T_1_bits_uop_debug_pc = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_debug_pc : _mem_ldq_e_T_bits_uop_debug_pc; // @[lsu.scala:263:49, :913:37, :917:33, :918:33] wire [2:0] _mem_ldq_e_T_1_bits_uop_iq_type = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_iq_type : _mem_ldq_e_T_bits_uop_iq_type; // @[lsu.scala:263:49, :913:37, :917:33, :918:33] wire [9:0] _mem_ldq_e_T_1_bits_uop_fu_code = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_fu_code : _mem_ldq_e_T_bits_uop_fu_code; // @[lsu.scala:263:49, :913:37, :917:33, :918:33] wire [3:0] _mem_ldq_e_T_1_bits_uop_ctrl_br_type = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_ctrl_br_type : _mem_ldq_e_T_bits_uop_ctrl_br_type; // @[lsu.scala:263:49, :913:37, :917:33, :918:33] wire [1:0] _mem_ldq_e_T_1_bits_uop_ctrl_op1_sel = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_ctrl_op1_sel : _mem_ldq_e_T_bits_uop_ctrl_op1_sel; // @[lsu.scala:263:49, :913:37, :917:33, :918:33] wire [2:0] _mem_ldq_e_T_1_bits_uop_ctrl_op2_sel = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_ctrl_op2_sel : _mem_ldq_e_T_bits_uop_ctrl_op2_sel; // @[lsu.scala:263:49, :913:37, :917:33, :918:33] wire [2:0] _mem_ldq_e_T_1_bits_uop_ctrl_imm_sel = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_ctrl_imm_sel : _mem_ldq_e_T_bits_uop_ctrl_imm_sel; // @[lsu.scala:263:49, :913:37, :917:33, :918:33] wire [4:0] _mem_ldq_e_T_1_bits_uop_ctrl_op_fcn = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_ctrl_op_fcn : _mem_ldq_e_T_bits_uop_ctrl_op_fcn; // @[lsu.scala:263:49, :913:37, :917:33, :918:33] wire _mem_ldq_e_T_1_bits_uop_ctrl_fcn_dw = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_ctrl_fcn_dw : _mem_ldq_e_T_bits_uop_ctrl_fcn_dw; // @[lsu.scala:263:49, :913:37, :917:33, :918:33] wire [2:0] _mem_ldq_e_T_1_bits_uop_ctrl_csr_cmd = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_ctrl_csr_cmd : _mem_ldq_e_T_bits_uop_ctrl_csr_cmd; // @[lsu.scala:263:49, :913:37, :917:33, :918:33] wire _mem_ldq_e_T_1_bits_uop_ctrl_is_load = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_ctrl_is_load : _mem_ldq_e_T_bits_uop_ctrl_is_load; // @[lsu.scala:263:49, :913:37, :917:33, :918:33] wire _mem_ldq_e_T_1_bits_uop_ctrl_is_sta = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_ctrl_is_sta : _mem_ldq_e_T_bits_uop_ctrl_is_sta; // @[lsu.scala:263:49, :913:37, :917:33, :918:33] wire _mem_ldq_e_T_1_bits_uop_ctrl_is_std = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_ctrl_is_std : _mem_ldq_e_T_bits_uop_ctrl_is_std; // @[lsu.scala:263:49, :913:37, :917:33, :918:33] wire [1:0] _mem_ldq_e_T_1_bits_uop_iw_state = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_iw_state : _mem_ldq_e_T_bits_uop_iw_state; // @[lsu.scala:263:49, :913:37, :917:33, :918:33] wire _mem_ldq_e_T_1_bits_uop_iw_p1_poisoned = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_iw_p1_poisoned : _mem_ldq_e_T_bits_uop_iw_p1_poisoned; // @[lsu.scala:263:49, :913:37, :917:33, :918:33] wire _mem_ldq_e_T_1_bits_uop_iw_p2_poisoned = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_iw_p2_poisoned : _mem_ldq_e_T_bits_uop_iw_p2_poisoned; // @[lsu.scala:263:49, :913:37, :917:33, :918:33] wire _mem_ldq_e_T_1_bits_uop_is_br = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_is_br : _mem_ldq_e_T_bits_uop_is_br; // @[lsu.scala:263:49, :913:37, :917:33, :918:33] wire _mem_ldq_e_T_1_bits_uop_is_jalr = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_is_jalr : _mem_ldq_e_T_bits_uop_is_jalr; // @[lsu.scala:263:49, :913:37, :917:33, :918:33] wire _mem_ldq_e_T_1_bits_uop_is_jal = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_is_jal : _mem_ldq_e_T_bits_uop_is_jal; // @[lsu.scala:263:49, :913:37, :917:33, :918:33] wire _mem_ldq_e_T_1_bits_uop_is_sfb = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_is_sfb : _mem_ldq_e_T_bits_uop_is_sfb; // @[lsu.scala:263:49, :913:37, :917:33, :918:33] wire [7:0] _mem_ldq_e_T_1_bits_uop_br_mask = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_br_mask : _mem_ldq_e_T_bits_uop_br_mask; // @[lsu.scala:263:49, :913:37, :917:33, :918:33] wire [2:0] _mem_ldq_e_T_1_bits_uop_br_tag = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_br_tag : _mem_ldq_e_T_bits_uop_br_tag; // @[lsu.scala:263:49, :913:37, :917:33, :918:33] wire [3:0] _mem_ldq_e_T_1_bits_uop_ftq_idx = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_ftq_idx : _mem_ldq_e_T_bits_uop_ftq_idx; // @[lsu.scala:263:49, :913:37, :917:33, :918:33] wire _mem_ldq_e_T_1_bits_uop_edge_inst = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_edge_inst : _mem_ldq_e_T_bits_uop_edge_inst; // @[lsu.scala:263:49, :913:37, :917:33, :918:33] wire [5:0] _mem_ldq_e_T_1_bits_uop_pc_lob = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_pc_lob : _mem_ldq_e_T_bits_uop_pc_lob; // @[lsu.scala:263:49, :913:37, :917:33, :918:33] wire _mem_ldq_e_T_1_bits_uop_taken = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_taken : _mem_ldq_e_T_bits_uop_taken; // @[lsu.scala:263:49, :913:37, :917:33, :918:33] wire [19:0] _mem_ldq_e_T_1_bits_uop_imm_packed = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_imm_packed : _mem_ldq_e_T_bits_uop_imm_packed; // @[lsu.scala:263:49, :913:37, :917:33, :918:33] wire [11:0] _mem_ldq_e_T_1_bits_uop_csr_addr = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_csr_addr : _mem_ldq_e_T_bits_uop_csr_addr; // @[lsu.scala:263:49, :913:37, :917:33, :918:33] wire [4:0] _mem_ldq_e_T_1_bits_uop_rob_idx = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_rob_idx : _mem_ldq_e_T_bits_uop_rob_idx; // @[lsu.scala:263:49, :913:37, :917:33, :918:33] wire [2:0] _mem_ldq_e_T_1_bits_uop_ldq_idx = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_ldq_idx : _mem_ldq_e_T_bits_uop_ldq_idx; // @[lsu.scala:263:49, :913:37, :917:33, :918:33] wire [2:0] _mem_ldq_e_T_1_bits_uop_stq_idx = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_stq_idx : _mem_ldq_e_T_bits_uop_stq_idx; // @[lsu.scala:263:49, :913:37, :917:33, :918:33] wire [1:0] _mem_ldq_e_T_1_bits_uop_rxq_idx = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_rxq_idx : _mem_ldq_e_T_bits_uop_rxq_idx; // @[lsu.scala:263:49, :913:37, :917:33, :918:33] wire [5:0] _mem_ldq_e_T_1_bits_uop_pdst = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_pdst : _mem_ldq_e_T_bits_uop_pdst; // @[lsu.scala:263:49, :913:37, :917:33, :918:33] wire [5:0] _mem_ldq_e_T_1_bits_uop_prs1 = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_prs1 : _mem_ldq_e_T_bits_uop_prs1; // @[lsu.scala:263:49, :913:37, :917:33, :918:33] wire [5:0] _mem_ldq_e_T_1_bits_uop_prs2 = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_prs2 : _mem_ldq_e_T_bits_uop_prs2; // @[lsu.scala:263:49, :913:37, :917:33, :918:33] wire [5:0] _mem_ldq_e_T_1_bits_uop_prs3 = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_prs3 : _mem_ldq_e_T_bits_uop_prs3; // @[lsu.scala:263:49, :913:37, :917:33, :918:33] wire [3:0] _mem_ldq_e_T_1_bits_uop_ppred = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_ppred : _mem_ldq_e_T_bits_uop_ppred; // @[lsu.scala:263:49, :913:37, :917:33, :918:33] wire _mem_ldq_e_T_1_bits_uop_prs1_busy = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_prs1_busy : _mem_ldq_e_T_bits_uop_prs1_busy; // @[lsu.scala:263:49, :913:37, :917:33, :918:33] wire _mem_ldq_e_T_1_bits_uop_prs2_busy = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_prs2_busy : _mem_ldq_e_T_bits_uop_prs2_busy; // @[lsu.scala:263:49, :913:37, :917:33, :918:33] wire _mem_ldq_e_T_1_bits_uop_prs3_busy = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_prs3_busy : _mem_ldq_e_T_bits_uop_prs3_busy; // @[lsu.scala:263:49, :913:37, :917:33, :918:33] wire _mem_ldq_e_T_1_bits_uop_ppred_busy = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_ppred_busy : _mem_ldq_e_T_bits_uop_ppred_busy; // @[lsu.scala:263:49, :913:37, :917:33, :918:33] wire [5:0] _mem_ldq_e_T_1_bits_uop_stale_pdst = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_stale_pdst : _mem_ldq_e_T_bits_uop_stale_pdst; // @[lsu.scala:263:49, :913:37, :917:33, :918:33] wire _mem_ldq_e_T_1_bits_uop_exception = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_exception : _mem_ldq_e_T_bits_uop_exception; // @[lsu.scala:263:49, :913:37, :917:33, :918:33] wire [63:0] _mem_ldq_e_T_1_bits_uop_exc_cause = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_exc_cause : _mem_ldq_e_T_bits_uop_exc_cause; // @[lsu.scala:263:49, :913:37, :917:33, :918:33] wire _mem_ldq_e_T_1_bits_uop_bypassable = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_bypassable : _mem_ldq_e_T_bits_uop_bypassable; // @[lsu.scala:263:49, :913:37, :917:33, :918:33] wire [4:0] _mem_ldq_e_T_1_bits_uop_mem_cmd = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_mem_cmd : _mem_ldq_e_T_bits_uop_mem_cmd; // @[lsu.scala:263:49, :913:37, :917:33, :918:33] wire [1:0] _mem_ldq_e_T_1_bits_uop_mem_size = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_mem_size : _mem_ldq_e_T_bits_uop_mem_size; // @[lsu.scala:263:49, :913:37, :917:33, :918:33] wire _mem_ldq_e_T_1_bits_uop_mem_signed = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_mem_signed : _mem_ldq_e_T_bits_uop_mem_signed; // @[lsu.scala:263:49, :913:37, :917:33, :918:33] wire _mem_ldq_e_T_1_bits_uop_is_fence = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_is_fence : _mem_ldq_e_T_bits_uop_is_fence; // @[lsu.scala:263:49, :913:37, :917:33, :918:33] wire _mem_ldq_e_T_1_bits_uop_is_fencei = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_is_fencei : _mem_ldq_e_T_bits_uop_is_fencei; // @[lsu.scala:263:49, :913:37, :917:33, :918:33] wire _mem_ldq_e_T_1_bits_uop_is_amo = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_is_amo : _mem_ldq_e_T_bits_uop_is_amo; // @[lsu.scala:263:49, :913:37, :917:33, :918:33] wire _mem_ldq_e_T_1_bits_uop_uses_ldq = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_uses_ldq : _mem_ldq_e_T_bits_uop_uses_ldq; // @[lsu.scala:263:49, :913:37, :917:33, :918:33] wire _mem_ldq_e_T_1_bits_uop_uses_stq = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_uses_stq : _mem_ldq_e_T_bits_uop_uses_stq; // @[lsu.scala:263:49, :913:37, :917:33, :918:33] wire _mem_ldq_e_T_1_bits_uop_is_sys_pc2epc = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_is_sys_pc2epc : _mem_ldq_e_T_bits_uop_is_sys_pc2epc; // @[lsu.scala:263:49, :913:37, :917:33, :918:33] wire _mem_ldq_e_T_1_bits_uop_is_unique = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_is_unique : _mem_ldq_e_T_bits_uop_is_unique; // @[lsu.scala:263:49, :913:37, :917:33, :918:33] wire _mem_ldq_e_T_1_bits_uop_flush_on_commit = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_flush_on_commit : _mem_ldq_e_T_bits_uop_flush_on_commit; // @[lsu.scala:263:49, :913:37, :917:33, :918:33] wire _mem_ldq_e_T_1_bits_uop_ldst_is_rs1 = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_ldst_is_rs1 : _mem_ldq_e_T_bits_uop_ldst_is_rs1; // @[lsu.scala:263:49, :913:37, :917:33, :918:33] wire [5:0] _mem_ldq_e_T_1_bits_uop_ldst = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_ldst : _mem_ldq_e_T_bits_uop_ldst; // @[lsu.scala:263:49, :913:37, :917:33, :918:33] wire [5:0] _mem_ldq_e_T_1_bits_uop_lrs1 = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_lrs1 : _mem_ldq_e_T_bits_uop_lrs1; // @[lsu.scala:263:49, :913:37, :917:33, :918:33] wire [5:0] _mem_ldq_e_T_1_bits_uop_lrs2 = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_lrs2 : _mem_ldq_e_T_bits_uop_lrs2; // @[lsu.scala:263:49, :913:37, :917:33, :918:33] wire [5:0] _mem_ldq_e_T_1_bits_uop_lrs3 = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_lrs3 : _mem_ldq_e_T_bits_uop_lrs3; // @[lsu.scala:263:49, :913:37, :917:33, :918:33] wire _mem_ldq_e_T_1_bits_uop_ldst_val = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_ldst_val : _mem_ldq_e_T_bits_uop_ldst_val; // @[lsu.scala:263:49, :913:37, :917:33, :918:33] wire [1:0] _mem_ldq_e_T_1_bits_uop_dst_rtype = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_dst_rtype : _mem_ldq_e_T_bits_uop_dst_rtype; // @[lsu.scala:263:49, :913:37, :917:33, :918:33] wire [1:0] _mem_ldq_e_T_1_bits_uop_lrs1_rtype = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_lrs1_rtype : _mem_ldq_e_T_bits_uop_lrs1_rtype; // @[lsu.scala:263:49, :913:37, :917:33, :918:33] wire [1:0] _mem_ldq_e_T_1_bits_uop_lrs2_rtype = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_lrs2_rtype : _mem_ldq_e_T_bits_uop_lrs2_rtype; // @[lsu.scala:263:49, :913:37, :917:33, :918:33] wire _mem_ldq_e_T_1_bits_uop_frs3_en = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_frs3_en : _mem_ldq_e_T_bits_uop_frs3_en; // @[lsu.scala:263:49, :913:37, :917:33, :918:33] wire _mem_ldq_e_T_1_bits_uop_fp_val = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_fp_val : _mem_ldq_e_T_bits_uop_fp_val; // @[lsu.scala:263:49, :913:37, :917:33, :918:33] wire _mem_ldq_e_T_1_bits_uop_fp_single = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_fp_single : _mem_ldq_e_T_bits_uop_fp_single; // @[lsu.scala:263:49, :913:37, :917:33, :918:33] wire _mem_ldq_e_T_1_bits_uop_xcpt_pf_if = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_xcpt_pf_if : _mem_ldq_e_T_bits_uop_xcpt_pf_if; // @[lsu.scala:263:49, :913:37, :917:33, :918:33] wire _mem_ldq_e_T_1_bits_uop_xcpt_ae_if = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_xcpt_ae_if : _mem_ldq_e_T_bits_uop_xcpt_ae_if; // @[lsu.scala:263:49, :913:37, :917:33, :918:33] wire _mem_ldq_e_T_1_bits_uop_xcpt_ma_if = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_xcpt_ma_if : _mem_ldq_e_T_bits_uop_xcpt_ma_if; // @[lsu.scala:263:49, :913:37, :917:33, :918:33] wire _mem_ldq_e_T_1_bits_uop_bp_debug_if = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_bp_debug_if : _mem_ldq_e_T_bits_uop_bp_debug_if; // @[lsu.scala:263:49, :913:37, :917:33, :918:33] wire _mem_ldq_e_T_1_bits_uop_bp_xcpt_if = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_bp_xcpt_if : _mem_ldq_e_T_bits_uop_bp_xcpt_if; // @[lsu.scala:263:49, :913:37, :917:33, :918:33] wire [1:0] _mem_ldq_e_T_1_bits_uop_debug_fsrc = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_debug_fsrc : _mem_ldq_e_T_bits_uop_debug_fsrc; // @[lsu.scala:263:49, :913:37, :917:33, :918:33] wire [1:0] _mem_ldq_e_T_1_bits_uop_debug_tsrc = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_debug_tsrc : _mem_ldq_e_T_bits_uop_debug_tsrc; // @[lsu.scala:263:49, :913:37, :917:33, :918:33] wire _mem_ldq_e_T_1_bits_addr_valid = fired_load_retry_0 ? mem_ldq_retry_e_bits_addr_valid : _mem_ldq_e_T_bits_addr_valid; // @[lsu.scala:263:49, :913:37, :917:33, :918:33] wire [39:0] _mem_ldq_e_T_1_bits_addr_bits = fired_load_retry_0 ? mem_ldq_retry_e_bits_addr_bits : _mem_ldq_e_T_bits_addr_bits; // @[lsu.scala:263:49, :913:37, :917:33, :918:33] wire _mem_ldq_e_T_1_bits_addr_is_virtual = fired_load_retry_0 ? mem_ldq_retry_e_bits_addr_is_virtual : _mem_ldq_e_T_bits_addr_is_virtual; // @[lsu.scala:263:49, :913:37, :917:33, :918:33] wire _mem_ldq_e_T_1_bits_addr_is_uncacheable = fired_load_retry_0 ? mem_ldq_retry_e_bits_addr_is_uncacheable : _mem_ldq_e_T_bits_addr_is_uncacheable; // @[lsu.scala:263:49, :913:37, :917:33, :918:33] wire _mem_ldq_e_T_1_bits_executed = fired_load_retry_0 ? mem_ldq_retry_e_bits_executed : _mem_ldq_e_T_bits_executed; // @[lsu.scala:263:49, :913:37, :917:33, :918:33] wire _mem_ldq_e_T_1_bits_succeeded = fired_load_retry_0 ? mem_ldq_retry_e_bits_succeeded : _mem_ldq_e_T_bits_succeeded; // @[lsu.scala:263:49, :913:37, :917:33, :918:33] wire _mem_ldq_e_T_1_bits_order_fail = fired_load_retry_0 ? mem_ldq_retry_e_bits_order_fail : _mem_ldq_e_T_bits_order_fail; // @[lsu.scala:263:49, :913:37, :917:33, :918:33] wire _mem_ldq_e_T_1_bits_observed = fired_load_retry_0 ? mem_ldq_retry_e_bits_observed : _mem_ldq_e_T_bits_observed; // @[lsu.scala:263:49, :913:37, :917:33, :918:33] wire [7:0] _mem_ldq_e_T_1_bits_st_dep_mask = fired_load_retry_0 ? mem_ldq_retry_e_bits_st_dep_mask : _mem_ldq_e_T_bits_st_dep_mask; // @[lsu.scala:263:49, :913:37, :917:33, :918:33] wire [2:0] _mem_ldq_e_T_1_bits_youngest_stq_idx = fired_load_retry_0 ? mem_ldq_retry_e_bits_youngest_stq_idx : _mem_ldq_e_T_bits_youngest_stq_idx; // @[lsu.scala:263:49, :913:37, :917:33, :918:33] wire _mem_ldq_e_T_1_bits_forward_std_val = fired_load_retry_0 ? mem_ldq_retry_e_bits_forward_std_val : _mem_ldq_e_T_bits_forward_std_val; // @[lsu.scala:263:49, :913:37, :917:33, :918:33] wire [2:0] _mem_ldq_e_T_1_bits_forward_stq_idx = fired_load_retry_0 ? mem_ldq_retry_e_bits_forward_stq_idx : _mem_ldq_e_T_bits_forward_stq_idx; // @[lsu.scala:263:49, :913:37, :917:33, :918:33] wire [63:0] _mem_ldq_e_T_1_bits_debug_wb_data = fired_load_retry_0 ? mem_ldq_retry_e_bits_debug_wb_data : _mem_ldq_e_T_bits_debug_wb_data; // @[lsu.scala:263:49, :913:37, :917:33, :918:33] wire _mem_ldq_e_T_2_valid = fired_load_incoming_0 ? mem_ldq_incoming_e_0_valid : _mem_ldq_e_T_1_valid; // @[lsu.scala:263:49, :910:37, :916:33, :917:33] wire [6:0] _mem_ldq_e_T_2_bits_uop_uopc = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_uop_uopc : _mem_ldq_e_T_1_bits_uop_uopc; // @[lsu.scala:263:49, :910:37, :916:33, :917:33] wire [31:0] _mem_ldq_e_T_2_bits_uop_inst = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_uop_inst : _mem_ldq_e_T_1_bits_uop_inst; // @[lsu.scala:263:49, :910:37, :916:33, :917:33] wire [31:0] _mem_ldq_e_T_2_bits_uop_debug_inst = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_uop_debug_inst : _mem_ldq_e_T_1_bits_uop_debug_inst; // @[lsu.scala:263:49, :910:37, :916:33, :917:33] wire _mem_ldq_e_T_2_bits_uop_is_rvc = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_uop_is_rvc : _mem_ldq_e_T_1_bits_uop_is_rvc; // @[lsu.scala:263:49, :910:37, :916:33, :917:33] wire [39:0] _mem_ldq_e_T_2_bits_uop_debug_pc = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_uop_debug_pc : _mem_ldq_e_T_1_bits_uop_debug_pc; // @[lsu.scala:263:49, :910:37, :916:33, :917:33] wire [2:0] _mem_ldq_e_T_2_bits_uop_iq_type = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_uop_iq_type : _mem_ldq_e_T_1_bits_uop_iq_type; // @[lsu.scala:263:49, :910:37, :916:33, :917:33] wire [9:0] _mem_ldq_e_T_2_bits_uop_fu_code = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_uop_fu_code : _mem_ldq_e_T_1_bits_uop_fu_code; // @[lsu.scala:263:49, :910:37, :916:33, :917:33] wire [3:0] _mem_ldq_e_T_2_bits_uop_ctrl_br_type = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_uop_ctrl_br_type : _mem_ldq_e_T_1_bits_uop_ctrl_br_type; // @[lsu.scala:263:49, :910:37, :916:33, :917:33] wire [1:0] _mem_ldq_e_T_2_bits_uop_ctrl_op1_sel = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_uop_ctrl_op1_sel : _mem_ldq_e_T_1_bits_uop_ctrl_op1_sel; // @[lsu.scala:263:49, :910:37, :916:33, :917:33] wire [2:0] _mem_ldq_e_T_2_bits_uop_ctrl_op2_sel = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_uop_ctrl_op2_sel : _mem_ldq_e_T_1_bits_uop_ctrl_op2_sel; // @[lsu.scala:263:49, :910:37, :916:33, :917:33] wire [2:0] _mem_ldq_e_T_2_bits_uop_ctrl_imm_sel = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_uop_ctrl_imm_sel : _mem_ldq_e_T_1_bits_uop_ctrl_imm_sel; // @[lsu.scala:263:49, :910:37, :916:33, :917:33] wire [4:0] _mem_ldq_e_T_2_bits_uop_ctrl_op_fcn = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_uop_ctrl_op_fcn : _mem_ldq_e_T_1_bits_uop_ctrl_op_fcn; // @[lsu.scala:263:49, :910:37, :916:33, :917:33] wire _mem_ldq_e_T_2_bits_uop_ctrl_fcn_dw = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_uop_ctrl_fcn_dw : _mem_ldq_e_T_1_bits_uop_ctrl_fcn_dw; // @[lsu.scala:263:49, :910:37, :916:33, :917:33] wire [2:0] _mem_ldq_e_T_2_bits_uop_ctrl_csr_cmd = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_uop_ctrl_csr_cmd : _mem_ldq_e_T_1_bits_uop_ctrl_csr_cmd; // @[lsu.scala:263:49, :910:37, :916:33, :917:33] wire _mem_ldq_e_T_2_bits_uop_ctrl_is_load = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_uop_ctrl_is_load : _mem_ldq_e_T_1_bits_uop_ctrl_is_load; // @[lsu.scala:263:49, :910:37, :916:33, :917:33] wire _mem_ldq_e_T_2_bits_uop_ctrl_is_sta = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_uop_ctrl_is_sta : _mem_ldq_e_T_1_bits_uop_ctrl_is_sta; // @[lsu.scala:263:49, :910:37, :916:33, :917:33] wire _mem_ldq_e_T_2_bits_uop_ctrl_is_std = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_uop_ctrl_is_std : _mem_ldq_e_T_1_bits_uop_ctrl_is_std; // @[lsu.scala:263:49, :910:37, :916:33, :917:33] wire [1:0] _mem_ldq_e_T_2_bits_uop_iw_state = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_uop_iw_state : _mem_ldq_e_T_1_bits_uop_iw_state; // @[lsu.scala:263:49, :910:37, :916:33, :917:33] wire _mem_ldq_e_T_2_bits_uop_iw_p1_poisoned = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_uop_iw_p1_poisoned : _mem_ldq_e_T_1_bits_uop_iw_p1_poisoned; // @[lsu.scala:263:49, :910:37, :916:33, :917:33] wire _mem_ldq_e_T_2_bits_uop_iw_p2_poisoned = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_uop_iw_p2_poisoned : _mem_ldq_e_T_1_bits_uop_iw_p2_poisoned; // @[lsu.scala:263:49, :910:37, :916:33, :917:33] wire _mem_ldq_e_T_2_bits_uop_is_br = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_uop_is_br : _mem_ldq_e_T_1_bits_uop_is_br; // @[lsu.scala:263:49, :910:37, :916:33, :917:33] wire _mem_ldq_e_T_2_bits_uop_is_jalr = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_uop_is_jalr : _mem_ldq_e_T_1_bits_uop_is_jalr; // @[lsu.scala:263:49, :910:37, :916:33, :917:33] wire _mem_ldq_e_T_2_bits_uop_is_jal = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_uop_is_jal : _mem_ldq_e_T_1_bits_uop_is_jal; // @[lsu.scala:263:49, :910:37, :916:33, :917:33] wire _mem_ldq_e_T_2_bits_uop_is_sfb = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_uop_is_sfb : _mem_ldq_e_T_1_bits_uop_is_sfb; // @[lsu.scala:263:49, :910:37, :916:33, :917:33] wire [7:0] _mem_ldq_e_T_2_bits_uop_br_mask = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_uop_br_mask : _mem_ldq_e_T_1_bits_uop_br_mask; // @[lsu.scala:263:49, :910:37, :916:33, :917:33] wire [2:0] _mem_ldq_e_T_2_bits_uop_br_tag = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_uop_br_tag : _mem_ldq_e_T_1_bits_uop_br_tag; // @[lsu.scala:263:49, :910:37, :916:33, :917:33] wire [3:0] _mem_ldq_e_T_2_bits_uop_ftq_idx = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_uop_ftq_idx : _mem_ldq_e_T_1_bits_uop_ftq_idx; // @[lsu.scala:263:49, :910:37, :916:33, :917:33] wire _mem_ldq_e_T_2_bits_uop_edge_inst = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_uop_edge_inst : _mem_ldq_e_T_1_bits_uop_edge_inst; // @[lsu.scala:263:49, :910:37, :916:33, :917:33] wire [5:0] _mem_ldq_e_T_2_bits_uop_pc_lob = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_uop_pc_lob : _mem_ldq_e_T_1_bits_uop_pc_lob; // @[lsu.scala:263:49, :910:37, :916:33, :917:33] wire _mem_ldq_e_T_2_bits_uop_taken = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_uop_taken : _mem_ldq_e_T_1_bits_uop_taken; // @[lsu.scala:263:49, :910:37, :916:33, :917:33] wire [19:0] _mem_ldq_e_T_2_bits_uop_imm_packed = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_uop_imm_packed : _mem_ldq_e_T_1_bits_uop_imm_packed; // @[lsu.scala:263:49, :910:37, :916:33, :917:33] wire [11:0] _mem_ldq_e_T_2_bits_uop_csr_addr = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_uop_csr_addr : _mem_ldq_e_T_1_bits_uop_csr_addr; // @[lsu.scala:263:49, :910:37, :916:33, :917:33] wire [4:0] _mem_ldq_e_T_2_bits_uop_rob_idx = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_uop_rob_idx : _mem_ldq_e_T_1_bits_uop_rob_idx; // @[lsu.scala:263:49, :910:37, :916:33, :917:33] wire [2:0] _mem_ldq_e_T_2_bits_uop_ldq_idx = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_uop_ldq_idx : _mem_ldq_e_T_1_bits_uop_ldq_idx; // @[lsu.scala:263:49, :910:37, :916:33, :917:33] wire [2:0] _mem_ldq_e_T_2_bits_uop_stq_idx = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_uop_stq_idx : _mem_ldq_e_T_1_bits_uop_stq_idx; // @[lsu.scala:263:49, :910:37, :916:33, :917:33] wire [1:0] _mem_ldq_e_T_2_bits_uop_rxq_idx = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_uop_rxq_idx : _mem_ldq_e_T_1_bits_uop_rxq_idx; // @[lsu.scala:263:49, :910:37, :916:33, :917:33] wire [5:0] _mem_ldq_e_T_2_bits_uop_pdst = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_uop_pdst : _mem_ldq_e_T_1_bits_uop_pdst; // @[lsu.scala:263:49, :910:37, :916:33, :917:33] wire [5:0] _mem_ldq_e_T_2_bits_uop_prs1 = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_uop_prs1 : _mem_ldq_e_T_1_bits_uop_prs1; // @[lsu.scala:263:49, :910:37, :916:33, :917:33] wire [5:0] _mem_ldq_e_T_2_bits_uop_prs2 = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_uop_prs2 : _mem_ldq_e_T_1_bits_uop_prs2; // @[lsu.scala:263:49, :910:37, :916:33, :917:33] wire [5:0] _mem_ldq_e_T_2_bits_uop_prs3 = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_uop_prs3 : _mem_ldq_e_T_1_bits_uop_prs3; // @[lsu.scala:263:49, :910:37, :916:33, :917:33] wire [3:0] _mem_ldq_e_T_2_bits_uop_ppred = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_uop_ppred : _mem_ldq_e_T_1_bits_uop_ppred; // @[lsu.scala:263:49, :910:37, :916:33, :917:33] wire _mem_ldq_e_T_2_bits_uop_prs1_busy = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_uop_prs1_busy : _mem_ldq_e_T_1_bits_uop_prs1_busy; // @[lsu.scala:263:49, :910:37, :916:33, :917:33] wire _mem_ldq_e_T_2_bits_uop_prs2_busy = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_uop_prs2_busy : _mem_ldq_e_T_1_bits_uop_prs2_busy; // @[lsu.scala:263:49, :910:37, :916:33, :917:33] wire _mem_ldq_e_T_2_bits_uop_prs3_busy = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_uop_prs3_busy : _mem_ldq_e_T_1_bits_uop_prs3_busy; // @[lsu.scala:263:49, :910:37, :916:33, :917:33] wire _mem_ldq_e_T_2_bits_uop_ppred_busy = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_uop_ppred_busy : _mem_ldq_e_T_1_bits_uop_ppred_busy; // @[lsu.scala:263:49, :910:37, :916:33, :917:33] wire [5:0] _mem_ldq_e_T_2_bits_uop_stale_pdst = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_uop_stale_pdst : _mem_ldq_e_T_1_bits_uop_stale_pdst; // @[lsu.scala:263:49, :910:37, :916:33, :917:33] wire _mem_ldq_e_T_2_bits_uop_exception = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_uop_exception : _mem_ldq_e_T_1_bits_uop_exception; // @[lsu.scala:263:49, :910:37, :916:33, :917:33] wire [63:0] _mem_ldq_e_T_2_bits_uop_exc_cause = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_uop_exc_cause : _mem_ldq_e_T_1_bits_uop_exc_cause; // @[lsu.scala:263:49, :910:37, :916:33, :917:33] wire _mem_ldq_e_T_2_bits_uop_bypassable = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_uop_bypassable : _mem_ldq_e_T_1_bits_uop_bypassable; // @[lsu.scala:263:49, :910:37, :916:33, :917:33] wire [4:0] _mem_ldq_e_T_2_bits_uop_mem_cmd = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_uop_mem_cmd : _mem_ldq_e_T_1_bits_uop_mem_cmd; // @[lsu.scala:263:49, :910:37, :916:33, :917:33] wire [1:0] _mem_ldq_e_T_2_bits_uop_mem_size = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_uop_mem_size : _mem_ldq_e_T_1_bits_uop_mem_size; // @[lsu.scala:263:49, :910:37, :916:33, :917:33] wire _mem_ldq_e_T_2_bits_uop_mem_signed = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_uop_mem_signed : _mem_ldq_e_T_1_bits_uop_mem_signed; // @[lsu.scala:263:49, :910:37, :916:33, :917:33] wire _mem_ldq_e_T_2_bits_uop_is_fence = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_uop_is_fence : _mem_ldq_e_T_1_bits_uop_is_fence; // @[lsu.scala:263:49, :910:37, :916:33, :917:33] wire _mem_ldq_e_T_2_bits_uop_is_fencei = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_uop_is_fencei : _mem_ldq_e_T_1_bits_uop_is_fencei; // @[lsu.scala:263:49, :910:37, :916:33, :917:33] wire _mem_ldq_e_T_2_bits_uop_is_amo = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_uop_is_amo : _mem_ldq_e_T_1_bits_uop_is_amo; // @[lsu.scala:263:49, :910:37, :916:33, :917:33] wire _mem_ldq_e_T_2_bits_uop_uses_ldq = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_uop_uses_ldq : _mem_ldq_e_T_1_bits_uop_uses_ldq; // @[lsu.scala:263:49, :910:37, :916:33, :917:33] wire _mem_ldq_e_T_2_bits_uop_uses_stq = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_uop_uses_stq : _mem_ldq_e_T_1_bits_uop_uses_stq; // @[lsu.scala:263:49, :910:37, :916:33, :917:33] wire _mem_ldq_e_T_2_bits_uop_is_sys_pc2epc = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_uop_is_sys_pc2epc : _mem_ldq_e_T_1_bits_uop_is_sys_pc2epc; // @[lsu.scala:263:49, :910:37, :916:33, :917:33] wire _mem_ldq_e_T_2_bits_uop_is_unique = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_uop_is_unique : _mem_ldq_e_T_1_bits_uop_is_unique; // @[lsu.scala:263:49, :910:37, :916:33, :917:33] wire _mem_ldq_e_T_2_bits_uop_flush_on_commit = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_uop_flush_on_commit : _mem_ldq_e_T_1_bits_uop_flush_on_commit; // @[lsu.scala:263:49, :910:37, :916:33, :917:33] wire _mem_ldq_e_T_2_bits_uop_ldst_is_rs1 = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_uop_ldst_is_rs1 : _mem_ldq_e_T_1_bits_uop_ldst_is_rs1; // @[lsu.scala:263:49, :910:37, :916:33, :917:33] wire [5:0] _mem_ldq_e_T_2_bits_uop_ldst = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_uop_ldst : _mem_ldq_e_T_1_bits_uop_ldst; // @[lsu.scala:263:49, :910:37, :916:33, :917:33] wire [5:0] _mem_ldq_e_T_2_bits_uop_lrs1 = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_uop_lrs1 : _mem_ldq_e_T_1_bits_uop_lrs1; // @[lsu.scala:263:49, :910:37, :916:33, :917:33] wire [5:0] _mem_ldq_e_T_2_bits_uop_lrs2 = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_uop_lrs2 : _mem_ldq_e_T_1_bits_uop_lrs2; // @[lsu.scala:263:49, :910:37, :916:33, :917:33] wire [5:0] _mem_ldq_e_T_2_bits_uop_lrs3 = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_uop_lrs3 : _mem_ldq_e_T_1_bits_uop_lrs3; // @[lsu.scala:263:49, :910:37, :916:33, :917:33] wire _mem_ldq_e_T_2_bits_uop_ldst_val = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_uop_ldst_val : _mem_ldq_e_T_1_bits_uop_ldst_val; // @[lsu.scala:263:49, :910:37, :916:33, :917:33] wire [1:0] _mem_ldq_e_T_2_bits_uop_dst_rtype = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_uop_dst_rtype : _mem_ldq_e_T_1_bits_uop_dst_rtype; // @[lsu.scala:263:49, :910:37, :916:33, :917:33] wire [1:0] _mem_ldq_e_T_2_bits_uop_lrs1_rtype = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_uop_lrs1_rtype : _mem_ldq_e_T_1_bits_uop_lrs1_rtype; // @[lsu.scala:263:49, :910:37, :916:33, :917:33] wire [1:0] _mem_ldq_e_T_2_bits_uop_lrs2_rtype = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_uop_lrs2_rtype : _mem_ldq_e_T_1_bits_uop_lrs2_rtype; // @[lsu.scala:263:49, :910:37, :916:33, :917:33] wire _mem_ldq_e_T_2_bits_uop_frs3_en = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_uop_frs3_en : _mem_ldq_e_T_1_bits_uop_frs3_en; // @[lsu.scala:263:49, :910:37, :916:33, :917:33] wire _mem_ldq_e_T_2_bits_uop_fp_val = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_uop_fp_val : _mem_ldq_e_T_1_bits_uop_fp_val; // @[lsu.scala:263:49, :910:37, :916:33, :917:33] wire _mem_ldq_e_T_2_bits_uop_fp_single = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_uop_fp_single : _mem_ldq_e_T_1_bits_uop_fp_single; // @[lsu.scala:263:49, :910:37, :916:33, :917:33] wire _mem_ldq_e_T_2_bits_uop_xcpt_pf_if = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_uop_xcpt_pf_if : _mem_ldq_e_T_1_bits_uop_xcpt_pf_if; // @[lsu.scala:263:49, :910:37, :916:33, :917:33] wire _mem_ldq_e_T_2_bits_uop_xcpt_ae_if = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_uop_xcpt_ae_if : _mem_ldq_e_T_1_bits_uop_xcpt_ae_if; // @[lsu.scala:263:49, :910:37, :916:33, :917:33] wire _mem_ldq_e_T_2_bits_uop_xcpt_ma_if = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_uop_xcpt_ma_if : _mem_ldq_e_T_1_bits_uop_xcpt_ma_if; // @[lsu.scala:263:49, :910:37, :916:33, :917:33] wire _mem_ldq_e_T_2_bits_uop_bp_debug_if = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_uop_bp_debug_if : _mem_ldq_e_T_1_bits_uop_bp_debug_if; // @[lsu.scala:263:49, :910:37, :916:33, :917:33] wire _mem_ldq_e_T_2_bits_uop_bp_xcpt_if = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_uop_bp_xcpt_if : _mem_ldq_e_T_1_bits_uop_bp_xcpt_if; // @[lsu.scala:263:49, :910:37, :916:33, :917:33] wire [1:0] _mem_ldq_e_T_2_bits_uop_debug_fsrc = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_uop_debug_fsrc : _mem_ldq_e_T_1_bits_uop_debug_fsrc; // @[lsu.scala:263:49, :910:37, :916:33, :917:33] wire [1:0] _mem_ldq_e_T_2_bits_uop_debug_tsrc = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_uop_debug_tsrc : _mem_ldq_e_T_1_bits_uop_debug_tsrc; // @[lsu.scala:263:49, :910:37, :916:33, :917:33] wire _mem_ldq_e_T_2_bits_addr_valid = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_addr_valid : _mem_ldq_e_T_1_bits_addr_valid; // @[lsu.scala:263:49, :910:37, :916:33, :917:33] wire [39:0] _mem_ldq_e_T_2_bits_addr_bits = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_addr_bits : _mem_ldq_e_T_1_bits_addr_bits; // @[lsu.scala:263:49, :910:37, :916:33, :917:33] wire _mem_ldq_e_T_2_bits_addr_is_virtual = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_addr_is_virtual : _mem_ldq_e_T_1_bits_addr_is_virtual; // @[lsu.scala:263:49, :910:37, :916:33, :917:33] wire _mem_ldq_e_T_2_bits_addr_is_uncacheable = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_addr_is_uncacheable : _mem_ldq_e_T_1_bits_addr_is_uncacheable; // @[lsu.scala:263:49, :910:37, :916:33, :917:33] wire _mem_ldq_e_T_2_bits_executed = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_executed : _mem_ldq_e_T_1_bits_executed; // @[lsu.scala:263:49, :910:37, :916:33, :917:33] wire _mem_ldq_e_T_2_bits_succeeded = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_succeeded : _mem_ldq_e_T_1_bits_succeeded; // @[lsu.scala:263:49, :910:37, :916:33, :917:33] wire _mem_ldq_e_T_2_bits_order_fail = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_order_fail : _mem_ldq_e_T_1_bits_order_fail; // @[lsu.scala:263:49, :910:37, :916:33, :917:33] wire _mem_ldq_e_T_2_bits_observed = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_observed : _mem_ldq_e_T_1_bits_observed; // @[lsu.scala:263:49, :910:37, :916:33, :917:33] wire [7:0] _mem_ldq_e_T_2_bits_st_dep_mask = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_st_dep_mask : _mem_ldq_e_T_1_bits_st_dep_mask; // @[lsu.scala:263:49, :910:37, :916:33, :917:33] wire [2:0] _mem_ldq_e_T_2_bits_youngest_stq_idx = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_youngest_stq_idx : _mem_ldq_e_T_1_bits_youngest_stq_idx; // @[lsu.scala:263:49, :910:37, :916:33, :917:33] wire _mem_ldq_e_T_2_bits_forward_std_val = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_forward_std_val : _mem_ldq_e_T_1_bits_forward_std_val; // @[lsu.scala:263:49, :910:37, :916:33, :917:33] wire [2:0] _mem_ldq_e_T_2_bits_forward_stq_idx = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_forward_stq_idx : _mem_ldq_e_T_1_bits_forward_stq_idx; // @[lsu.scala:263:49, :910:37, :916:33, :917:33] wire [63:0] _mem_ldq_e_T_2_bits_debug_wb_data = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_debug_wb_data : _mem_ldq_e_T_1_bits_debug_wb_data; // @[lsu.scala:263:49, :910:37, :916:33, :917:33] wire mem_ldq_e_0_valid = _mem_ldq_e_T_2_valid; // @[lsu.scala:263:49, :916:33] wire [6:0] mem_ldq_e_0_bits_uop_uopc = _mem_ldq_e_T_2_bits_uop_uopc; // @[lsu.scala:263:49, :916:33] wire [31:0] mem_ldq_e_0_bits_uop_inst = _mem_ldq_e_T_2_bits_uop_inst; // @[lsu.scala:263:49, :916:33] wire [31:0] mem_ldq_e_0_bits_uop_debug_inst = _mem_ldq_e_T_2_bits_uop_debug_inst; // @[lsu.scala:263:49, :916:33] wire mem_ldq_e_0_bits_uop_is_rvc = _mem_ldq_e_T_2_bits_uop_is_rvc; // @[lsu.scala:263:49, :916:33] wire [39:0] mem_ldq_e_0_bits_uop_debug_pc = _mem_ldq_e_T_2_bits_uop_debug_pc; // @[lsu.scala:263:49, :916:33] wire [2:0] mem_ldq_e_0_bits_uop_iq_type = _mem_ldq_e_T_2_bits_uop_iq_type; // @[lsu.scala:263:49, :916:33] wire [9:0] mem_ldq_e_0_bits_uop_fu_code = _mem_ldq_e_T_2_bits_uop_fu_code; // @[lsu.scala:263:49, :916:33] wire [3:0] mem_ldq_e_0_bits_uop_ctrl_br_type = _mem_ldq_e_T_2_bits_uop_ctrl_br_type; // @[lsu.scala:263:49, :916:33] wire [1:0] mem_ldq_e_0_bits_uop_ctrl_op1_sel = _mem_ldq_e_T_2_bits_uop_ctrl_op1_sel; // @[lsu.scala:263:49, :916:33] wire [2:0] mem_ldq_e_0_bits_uop_ctrl_op2_sel = _mem_ldq_e_T_2_bits_uop_ctrl_op2_sel; // @[lsu.scala:263:49, :916:33] wire [2:0] mem_ldq_e_0_bits_uop_ctrl_imm_sel = _mem_ldq_e_T_2_bits_uop_ctrl_imm_sel; // @[lsu.scala:263:49, :916:33] wire [4:0] mem_ldq_e_0_bits_uop_ctrl_op_fcn = _mem_ldq_e_T_2_bits_uop_ctrl_op_fcn; // @[lsu.scala:263:49, :916:33] wire mem_ldq_e_0_bits_uop_ctrl_fcn_dw = _mem_ldq_e_T_2_bits_uop_ctrl_fcn_dw; // @[lsu.scala:263:49, :916:33] wire [2:0] mem_ldq_e_0_bits_uop_ctrl_csr_cmd = _mem_ldq_e_T_2_bits_uop_ctrl_csr_cmd; // @[lsu.scala:263:49, :916:33] wire mem_ldq_e_0_bits_uop_ctrl_is_load = _mem_ldq_e_T_2_bits_uop_ctrl_is_load; // @[lsu.scala:263:49, :916:33] wire mem_ldq_e_0_bits_uop_ctrl_is_sta = _mem_ldq_e_T_2_bits_uop_ctrl_is_sta; // @[lsu.scala:263:49, :916:33] wire mem_ldq_e_0_bits_uop_ctrl_is_std = _mem_ldq_e_T_2_bits_uop_ctrl_is_std; // @[lsu.scala:263:49, :916:33] wire [1:0] mem_ldq_e_0_bits_uop_iw_state = _mem_ldq_e_T_2_bits_uop_iw_state; // @[lsu.scala:263:49, :916:33] wire mem_ldq_e_0_bits_uop_iw_p1_poisoned = _mem_ldq_e_T_2_bits_uop_iw_p1_poisoned; // @[lsu.scala:263:49, :916:33] wire mem_ldq_e_0_bits_uop_iw_p2_poisoned = _mem_ldq_e_T_2_bits_uop_iw_p2_poisoned; // @[lsu.scala:263:49, :916:33] wire mem_ldq_e_0_bits_uop_is_br = _mem_ldq_e_T_2_bits_uop_is_br; // @[lsu.scala:263:49, :916:33] wire mem_ldq_e_0_bits_uop_is_jalr = _mem_ldq_e_T_2_bits_uop_is_jalr; // @[lsu.scala:263:49, :916:33] wire mem_ldq_e_0_bits_uop_is_jal = _mem_ldq_e_T_2_bits_uop_is_jal; // @[lsu.scala:263:49, :916:33] wire mem_ldq_e_0_bits_uop_is_sfb = _mem_ldq_e_T_2_bits_uop_is_sfb; // @[lsu.scala:263:49, :916:33] wire [7:0] mem_ldq_e_0_bits_uop_br_mask = _mem_ldq_e_T_2_bits_uop_br_mask; // @[lsu.scala:263:49, :916:33] wire [2:0] mem_ldq_e_0_bits_uop_br_tag = _mem_ldq_e_T_2_bits_uop_br_tag; // @[lsu.scala:263:49, :916:33] wire [3:0] mem_ldq_e_0_bits_uop_ftq_idx = _mem_ldq_e_T_2_bits_uop_ftq_idx; // @[lsu.scala:263:49, :916:33] wire mem_ldq_e_0_bits_uop_edge_inst = _mem_ldq_e_T_2_bits_uop_edge_inst; // @[lsu.scala:263:49, :916:33] wire [5:0] mem_ldq_e_0_bits_uop_pc_lob = _mem_ldq_e_T_2_bits_uop_pc_lob; // @[lsu.scala:263:49, :916:33] wire mem_ldq_e_0_bits_uop_taken = _mem_ldq_e_T_2_bits_uop_taken; // @[lsu.scala:263:49, :916:33] wire [19:0] mem_ldq_e_0_bits_uop_imm_packed = _mem_ldq_e_T_2_bits_uop_imm_packed; // @[lsu.scala:263:49, :916:33] wire [11:0] mem_ldq_e_0_bits_uop_csr_addr = _mem_ldq_e_T_2_bits_uop_csr_addr; // @[lsu.scala:263:49, :916:33] wire [4:0] mem_ldq_e_0_bits_uop_rob_idx = _mem_ldq_e_T_2_bits_uop_rob_idx; // @[lsu.scala:263:49, :916:33] wire [2:0] mem_ldq_e_0_bits_uop_ldq_idx = _mem_ldq_e_T_2_bits_uop_ldq_idx; // @[lsu.scala:263:49, :916:33] wire [2:0] mem_ldq_e_0_bits_uop_stq_idx = _mem_ldq_e_T_2_bits_uop_stq_idx; // @[lsu.scala:263:49, :916:33] wire [1:0] mem_ldq_e_0_bits_uop_rxq_idx = _mem_ldq_e_T_2_bits_uop_rxq_idx; // @[lsu.scala:263:49, :916:33] wire [5:0] mem_ldq_e_0_bits_uop_pdst = _mem_ldq_e_T_2_bits_uop_pdst; // @[lsu.scala:263:49, :916:33] wire [5:0] mem_ldq_e_0_bits_uop_prs1 = _mem_ldq_e_T_2_bits_uop_prs1; // @[lsu.scala:263:49, :916:33] wire [5:0] mem_ldq_e_0_bits_uop_prs2 = _mem_ldq_e_T_2_bits_uop_prs2; // @[lsu.scala:263:49, :916:33] wire [5:0] mem_ldq_e_0_bits_uop_prs3 = _mem_ldq_e_T_2_bits_uop_prs3; // @[lsu.scala:263:49, :916:33] wire [3:0] mem_ldq_e_0_bits_uop_ppred = _mem_ldq_e_T_2_bits_uop_ppred; // @[lsu.scala:263:49, :916:33] wire mem_ldq_e_0_bits_uop_prs1_busy = _mem_ldq_e_T_2_bits_uop_prs1_busy; // @[lsu.scala:263:49, :916:33] wire mem_ldq_e_0_bits_uop_prs2_busy = _mem_ldq_e_T_2_bits_uop_prs2_busy; // @[lsu.scala:263:49, :916:33] wire mem_ldq_e_0_bits_uop_prs3_busy = _mem_ldq_e_T_2_bits_uop_prs3_busy; // @[lsu.scala:263:49, :916:33] wire mem_ldq_e_0_bits_uop_ppred_busy = _mem_ldq_e_T_2_bits_uop_ppred_busy; // @[lsu.scala:263:49, :916:33] wire [5:0] mem_ldq_e_0_bits_uop_stale_pdst = _mem_ldq_e_T_2_bits_uop_stale_pdst; // @[lsu.scala:263:49, :916:33] wire mem_ldq_e_0_bits_uop_exception = _mem_ldq_e_T_2_bits_uop_exception; // @[lsu.scala:263:49, :916:33] wire [63:0] mem_ldq_e_0_bits_uop_exc_cause = _mem_ldq_e_T_2_bits_uop_exc_cause; // @[lsu.scala:263:49, :916:33] wire mem_ldq_e_0_bits_uop_bypassable = _mem_ldq_e_T_2_bits_uop_bypassable; // @[lsu.scala:263:49, :916:33] wire [4:0] mem_ldq_e_0_bits_uop_mem_cmd = _mem_ldq_e_T_2_bits_uop_mem_cmd; // @[lsu.scala:263:49, :916:33] wire [1:0] mem_ldq_e_0_bits_uop_mem_size = _mem_ldq_e_T_2_bits_uop_mem_size; // @[lsu.scala:263:49, :916:33] wire mem_ldq_e_0_bits_uop_mem_signed = _mem_ldq_e_T_2_bits_uop_mem_signed; // @[lsu.scala:263:49, :916:33] wire mem_ldq_e_0_bits_uop_is_fence = _mem_ldq_e_T_2_bits_uop_is_fence; // @[lsu.scala:263:49, :916:33] wire mem_ldq_e_0_bits_uop_is_fencei = _mem_ldq_e_T_2_bits_uop_is_fencei; // @[lsu.scala:263:49, :916:33] wire mem_ldq_e_0_bits_uop_is_amo = _mem_ldq_e_T_2_bits_uop_is_amo; // @[lsu.scala:263:49, :916:33] wire mem_ldq_e_0_bits_uop_uses_ldq = _mem_ldq_e_T_2_bits_uop_uses_ldq; // @[lsu.scala:263:49, :916:33] wire mem_ldq_e_0_bits_uop_uses_stq = _mem_ldq_e_T_2_bits_uop_uses_stq; // @[lsu.scala:263:49, :916:33] wire mem_ldq_e_0_bits_uop_is_sys_pc2epc = _mem_ldq_e_T_2_bits_uop_is_sys_pc2epc; // @[lsu.scala:263:49, :916:33] wire mem_ldq_e_0_bits_uop_is_unique = _mem_ldq_e_T_2_bits_uop_is_unique; // @[lsu.scala:263:49, :916:33] wire mem_ldq_e_0_bits_uop_flush_on_commit = _mem_ldq_e_T_2_bits_uop_flush_on_commit; // @[lsu.scala:263:49, :916:33] wire mem_ldq_e_0_bits_uop_ldst_is_rs1 = _mem_ldq_e_T_2_bits_uop_ldst_is_rs1; // @[lsu.scala:263:49, :916:33] wire [5:0] mem_ldq_e_0_bits_uop_ldst = _mem_ldq_e_T_2_bits_uop_ldst; // @[lsu.scala:263:49, :916:33] wire [5:0] mem_ldq_e_0_bits_uop_lrs1 = _mem_ldq_e_T_2_bits_uop_lrs1; // @[lsu.scala:263:49, :916:33] wire [5:0] mem_ldq_e_0_bits_uop_lrs2 = _mem_ldq_e_T_2_bits_uop_lrs2; // @[lsu.scala:263:49, :916:33] wire [5:0] mem_ldq_e_0_bits_uop_lrs3 = _mem_ldq_e_T_2_bits_uop_lrs3; // @[lsu.scala:263:49, :916:33] wire mem_ldq_e_0_bits_uop_ldst_val = _mem_ldq_e_T_2_bits_uop_ldst_val; // @[lsu.scala:263:49, :916:33] wire [1:0] mem_ldq_e_0_bits_uop_dst_rtype = _mem_ldq_e_T_2_bits_uop_dst_rtype; // @[lsu.scala:263:49, :916:33] wire [1:0] mem_ldq_e_0_bits_uop_lrs1_rtype = _mem_ldq_e_T_2_bits_uop_lrs1_rtype; // @[lsu.scala:263:49, :916:33] wire [1:0] mem_ldq_e_0_bits_uop_lrs2_rtype = _mem_ldq_e_T_2_bits_uop_lrs2_rtype; // @[lsu.scala:263:49, :916:33] wire mem_ldq_e_0_bits_uop_frs3_en = _mem_ldq_e_T_2_bits_uop_frs3_en; // @[lsu.scala:263:49, :916:33] wire mem_ldq_e_0_bits_uop_fp_val = _mem_ldq_e_T_2_bits_uop_fp_val; // @[lsu.scala:263:49, :916:33] wire mem_ldq_e_0_bits_uop_fp_single = _mem_ldq_e_T_2_bits_uop_fp_single; // @[lsu.scala:263:49, :916:33] wire mem_ldq_e_0_bits_uop_xcpt_pf_if = _mem_ldq_e_T_2_bits_uop_xcpt_pf_if; // @[lsu.scala:263:49, :916:33] wire mem_ldq_e_0_bits_uop_xcpt_ae_if = _mem_ldq_e_T_2_bits_uop_xcpt_ae_if; // @[lsu.scala:263:49, :916:33] wire mem_ldq_e_0_bits_uop_xcpt_ma_if = _mem_ldq_e_T_2_bits_uop_xcpt_ma_if; // @[lsu.scala:263:49, :916:33] wire mem_ldq_e_0_bits_uop_bp_debug_if = _mem_ldq_e_T_2_bits_uop_bp_debug_if; // @[lsu.scala:263:49, :916:33] wire mem_ldq_e_0_bits_uop_bp_xcpt_if = _mem_ldq_e_T_2_bits_uop_bp_xcpt_if; // @[lsu.scala:263:49, :916:33] wire [1:0] mem_ldq_e_0_bits_uop_debug_fsrc = _mem_ldq_e_T_2_bits_uop_debug_fsrc; // @[lsu.scala:263:49, :916:33] wire [1:0] mem_ldq_e_0_bits_uop_debug_tsrc = _mem_ldq_e_T_2_bits_uop_debug_tsrc; // @[lsu.scala:263:49, :916:33] wire mem_ldq_e_0_bits_addr_valid = _mem_ldq_e_T_2_bits_addr_valid; // @[lsu.scala:263:49, :916:33] wire [39:0] mem_ldq_e_0_bits_addr_bits = _mem_ldq_e_T_2_bits_addr_bits; // @[lsu.scala:263:49, :916:33] wire mem_ldq_e_0_bits_addr_is_virtual = _mem_ldq_e_T_2_bits_addr_is_virtual; // @[lsu.scala:263:49, :916:33] wire mem_ldq_e_0_bits_addr_is_uncacheable = _mem_ldq_e_T_2_bits_addr_is_uncacheable; // @[lsu.scala:263:49, :916:33] wire mem_ldq_e_0_bits_executed = _mem_ldq_e_T_2_bits_executed; // @[lsu.scala:263:49, :916:33] wire mem_ldq_e_0_bits_succeeded = _mem_ldq_e_T_2_bits_succeeded; // @[lsu.scala:263:49, :916:33] wire mem_ldq_e_0_bits_order_fail = _mem_ldq_e_T_2_bits_order_fail; // @[lsu.scala:263:49, :916:33] wire mem_ldq_e_0_bits_observed = _mem_ldq_e_T_2_bits_observed; // @[lsu.scala:263:49, :916:33] wire [7:0] mem_ldq_e_0_bits_st_dep_mask = _mem_ldq_e_T_2_bits_st_dep_mask; // @[lsu.scala:263:49, :916:33] wire [2:0] mem_ldq_e_0_bits_youngest_stq_idx = _mem_ldq_e_T_2_bits_youngest_stq_idx; // @[lsu.scala:263:49, :916:33] wire mem_ldq_e_0_bits_forward_std_val = _mem_ldq_e_T_2_bits_forward_std_val; // @[lsu.scala:263:49, :916:33] wire [2:0] mem_ldq_e_0_bits_forward_stq_idx = _mem_ldq_e_T_2_bits_forward_stq_idx; // @[lsu.scala:263:49, :916:33] wire [63:0] mem_ldq_e_0_bits_debug_wb_data = _mem_ldq_e_T_2_bits_debug_wb_data; // @[lsu.scala:263:49, :916:33] wire [7:0] lcam_st_dep_mask_0 = mem_ldq_e_0_bits_st_dep_mask; // @[lsu.scala:263:49] wire _GEN_226 = fired_stad_incoming_0 \| fired_sta_incoming_0; // @[lsu.scala:263:49, :920:57] wire _mem_stq_e_T; // @[lsu.scala:920:57] assign _mem_stq_e_T = _GEN_226; // @[lsu.scala:920:57] wire _do_st_search_T; // @[lsu.scala:1015:60] assign _do_st_search_T = _GEN_226; // @[lsu.scala:920:57, :1015:60] wire _lcam_addr_T; // @[lsu.scala:1026:61] assign _lcam_addr_T = _GEN_226; // @[lsu.scala:920:57, :1026:61] wire _lcam_stq_idx_T; // @[lsu.scala:1041:50] assign _lcam_stq_idx_T = _GEN_226; // @[lsu.scala:920:57, :1041:50] wire _mem_stq_e_T_1_valid = fired_sta_retry_0 & mem_stq_retry_e_valid; // @[lsu.scala:263:49, :914:37, :922:33] wire [6:0] _mem_stq_e_T_1_bits_uop_uopc = fired_sta_retry_0 ? mem_stq_retry_e_bits_uop_uopc : 7'h0; // @[lsu.scala:263:49, :914:37, :922:33] wire [31:0] _mem_stq_e_T_1_bits_uop_inst = fired_sta_retry_0 ? mem_stq_retry_e_bits_uop_inst : 32'h0; // @[lsu.scala:263:49, :914:37, :922:33] wire [31:0] _mem_stq_e_T_1_bits_uop_debug_inst = fired_sta_retry_0 ? mem_stq_retry_e_bits_uop_debug_inst : 32'h0; // @[lsu.scala:263:49, :914:37, :922:33] wire _mem_stq_e_T_1_bits_uop_is_rvc = fired_sta_retry_0 & mem_stq_retry_e_bits_uop_is_rvc; // @[lsu.scala:263:49, :914:37, :922:33] wire [39:0] _mem_stq_e_T_1_bits_uop_debug_pc = fired_sta_retry_0 ? mem_stq_retry_e_bits_uop_debug_pc : 40'h0; // @[lsu.scala:263:49, :914:37, :922:33] wire [2:0] _mem_stq_e_T_1_bits_uop_iq_type = fired_sta_retry_0 ? mem_stq_retry_e_bits_uop_iq_type : 3'h0; // @[lsu.scala:263:49, :914:37, :922:33] wire [9:0] _mem_stq_e_T_1_bits_uop_fu_code = fired_sta_retry_0 ? mem_stq_retry_e_bits_uop_fu_code : 10'h0; // @[lsu.scala:263:49, :914:37, :922:33] wire [3:0] _mem_stq_e_T_1_bits_uop_ctrl_br_type = fired_sta_retry_0 ? mem_stq_retry_e_bits_uop_ctrl_br_type : 4'h0; // @[lsu.scala:263:49, :914:37, :922:33] wire [1:0] _mem_stq_e_T_1_bits_uop_ctrl_op1_sel = fired_sta_retry_0 ? mem_stq_retry_e_bits_uop_ctrl_op1_sel : 2'h0; // @[lsu.scala:263:49, :914:37, :922:33] wire [2:0] _mem_stq_e_T_1_bits_uop_ctrl_op2_sel = fired_sta_retry_0 ? mem_stq_retry_e_bits_uop_ctrl_op2_sel : 3'h0; // @[lsu.scala:263:49, :914:37, :922:33] wire [2:0] _mem_stq_e_T_1_bits_uop_ctrl_imm_sel = fired_sta_retry_0 ? mem_stq_retry_e_bits_uop_ctrl_imm_sel : 3'h0; // @[lsu.scala:263:49, :914:37, :922:33] wire [4:0] _mem_stq_e_T_1_bits_uop_ctrl_op_fcn = fired_sta_retry_0 ? mem_stq_retry_e_bits_uop_ctrl_op_fcn : 5'h0; // @[lsu.scala:263:49, :914:37, :922:33] wire _mem_stq_e_T_1_bits_uop_ctrl_fcn_dw = fired_sta_retry_0 & mem_stq_retry_e_bits_uop_ctrl_fcn_dw; // @[lsu.scala:263:49, :914:37, :922:33] wire [2:0] _mem_stq_e_T_1_bits_uop_ctrl_csr_cmd = fired_sta_retry_0 ? mem_stq_retry_e_bits_uop_ctrl_csr_cmd : 3'h0; // @[lsu.scala:263:49, :914:37, :922:33] wire _mem_stq_e_T_1_bits_uop_ctrl_is_load = fired_sta_retry_0 & mem_stq_retry_e_bits_uop_ctrl_is_load; // @[lsu.scala:263:49, :914:37, :922:33] wire _mem_stq_e_T_1_bits_uop_ctrl_is_sta = fired_sta_retry_0 & mem_stq_retry_e_bits_uop_ctrl_is_sta; // @[lsu.scala:263:49, :914:37, :922:33] wire _mem_stq_e_T_1_bits_uop_ctrl_is_std = fired_sta_retry_0 & mem_stq_retry_e_bits_uop_ctrl_is_std; // @[lsu.scala:263:49, :914:37, :922:33] wire [1:0] _mem_stq_e_T_1_bits_uop_iw_state = fired_sta_retry_0 ? mem_stq_retry_e_bits_uop_iw_state : 2'h0; // @[lsu.scala:263:49, :914:37, :922:33] wire _mem_stq_e_T_1_bits_uop_iw_p1_poisoned = fired_sta_retry_0 & mem_stq_retry_e_bits_uop_iw_p1_poisoned; // @[lsu.scala:263:49, :914:37, :922:33] wire _mem_stq_e_T_1_bits_uop_iw_p2_poisoned = fired_sta_retry_0 & mem_stq_retry_e_bits_uop_iw_p2_poisoned; // @[lsu.scala:263:49, :914:37, :922:33] wire _mem_stq_e_T_1_bits_uop_is_br = fired_sta_retry_0 & mem_stq_retry_e_bits_uop_is_br; // @[lsu.scala:263:49, :914:37, :922:33] wire _mem_stq_e_T_1_bits_uop_is_jalr = fired_sta_retry_0 & mem_stq_retry_e_bits_uop_is_jalr; // @[lsu.scala:263:49, :914:37, :922:33] wire _mem_stq_e_T_1_bits_uop_is_jal = fired_sta_retry_0 & mem_stq_retry_e_bits_uop_is_jal; // @[lsu.scala:263:49, :914:37, :922:33] wire _mem_stq_e_T_1_bits_uop_is_sfb = fired_sta_retry_0 & mem_stq_retry_e_bits_uop_is_sfb; // @[lsu.scala:263:49, :914:37, :922:33] wire [7:0] _mem_stq_e_T_1_bits_uop_br_mask = fired_sta_retry_0 ? mem_stq_retry_e_bits_uop_br_mask : 8'h0; // @[lsu.scala:263:49, :914:37, :922:33] wire [2:0] _mem_stq_e_T_1_bits_uop_br_tag = fired_sta_retry_0 ? mem_stq_retry_e_bits_uop_br_tag : 3'h0; // @[lsu.scala:263:49, :914:37, :922:33] wire [3:0] _mem_stq_e_T_1_bits_uop_ftq_idx = fired_sta_retry_0 ? mem_stq_retry_e_bits_uop_ftq_idx : 4'h0; // @[lsu.scala:263:49, :914:37, :922:33] wire _mem_stq_e_T_1_bits_uop_edge_inst = fired_sta_retry_0 & mem_stq_retry_e_bits_uop_edge_inst; // @[lsu.scala:263:49, :914:37, :922:33] wire [5:0] _mem_stq_e_T_1_bits_uop_pc_lob = fired_sta_retry_0 ? mem_stq_retry_e_bits_uop_pc_lob : 6'h0; // @[lsu.scala:263:49, :914:37, :922:33] wire _mem_stq_e_T_1_bits_uop_taken = fired_sta_retry_0 & mem_stq_retry_e_bits_uop_taken; // @[lsu.scala:263:49, :914:37, :922:33] wire [19:0] _mem_stq_e_T_1_bits_uop_imm_packed = fired_sta_retry_0 ? mem_stq_retry_e_bits_uop_imm_packed : 20'h0; // @[lsu.scala:263:49, :914:37, :922:33] wire [11:0] _mem_stq_e_T_1_bits_uop_csr_addr = fired_sta_retry_0 ? mem_stq_retry_e_bits_uop_csr_addr : 12'h0; // @[lsu.scala:263:49, :914:37, :922:33] wire [4:0] _mem_stq_e_T_1_bits_uop_rob_idx = fired_sta_retry_0 ? mem_stq_retry_e_bits_uop_rob_idx : 5'h0; // @[lsu.scala:263:49, :914:37, :922:33] wire [2:0] _mem_stq_e_T_1_bits_uop_ldq_idx = fired_sta_retry_0 ? mem_stq_retry_e_bits_uop_ldq_idx : 3'h0; // @[lsu.scala:263:49, :914:37, :922:33] wire [2:0] _mem_stq_e_T_1_bits_uop_stq_idx = fired_sta_retry_0 ? mem_stq_retry_e_bits_uop_stq_idx : 3'h0; // @[lsu.scala:263:49, :914:37, :922:33] wire [1:0] _mem_stq_e_T_1_bits_uop_rxq_idx = fired_sta_retry_0 ? mem_stq_retry_e_bits_uop_rxq_idx : 2'h0; // @[lsu.scala:263:49, :914:37, :922:33] wire [5:0] _mem_stq_e_T_1_bits_uop_pdst = fired_sta_retry_0 ? mem_stq_retry_e_bits_uop_pdst : 6'h0; // @[lsu.scala:263:49, :914:37, :922:33] wire [5:0] _mem_stq_e_T_1_bits_uop_prs1 = fired_sta_retry_0 ? mem_stq_retry_e_bits_uop_prs1 : 6'h0; // @[lsu.scala:263:49, :914:37, :922:33] wire [5:0] _mem_stq_e_T_1_bits_uop_prs2 = fired_sta_retry_0 ? mem_stq_retry_e_bits_uop_prs2 : 6'h0; // @[lsu.scala:263:49, :914:37, :922:33] wire [5:0] _mem_stq_e_T_1_bits_uop_prs3 = fired_sta_retry_0 ? mem_stq_retry_e_bits_uop_prs3 : 6'h0; // @[lsu.scala:263:49, :914:37, :922:33] wire [3:0] _mem_stq_e_T_1_bits_uop_ppred = fired_sta_retry_0 ? mem_stq_retry_e_bits_uop_ppred : 4'h0; // @[lsu.scala:263:49, :914:37, :922:33] wire _mem_stq_e_T_1_bits_uop_prs1_busy = fired_sta_retry_0 & mem_stq_retry_e_bits_uop_prs1_busy; // @[lsu.scala:263:49, :914:37, :922:33] wire _mem_stq_e_T_1_bits_uop_prs2_busy = fired_sta_retry_0 & mem_stq_retry_e_bits_uop_prs2_busy; // @[lsu.scala:263:49, :914:37, :922:33] wire _mem_stq_e_T_1_bits_uop_prs3_busy = fired_sta_retry_0 & mem_stq_retry_e_bits_uop_prs3_busy; // @[lsu.scala:263:49, :914:37, :922:33] wire _mem_stq_e_T_1_bits_uop_ppred_busy = fired_sta_retry_0 & mem_stq_retry_e_bits_uop_ppred_busy; // @[lsu.scala:263:49, :914:37, :922:33] wire [5:0] _mem_stq_e_T_1_bits_uop_stale_pdst = fired_sta_retry_0 ? mem_stq_retry_e_bits_uop_stale_pdst : 6'h0; // @[lsu.scala:263:49, :914:37, :922:33] wire _mem_stq_e_T_1_bits_uop_exception = fired_sta_retry_0 & mem_stq_retry_e_bits_uop_exception; // @[lsu.scala:263:49, :914:37, :922:33] wire [63:0] _mem_stq_e_T_1_bits_uop_exc_cause = fired_sta_retry_0 ? mem_stq_retry_e_bits_uop_exc_cause : 64'h0; // @[lsu.scala:263:49, :914:37, :922:33] wire _mem_stq_e_T_1_bits_uop_bypassable = fired_sta_retry_0 & mem_stq_retry_e_bits_uop_bypassable; // @[lsu.scala:263:49, :914:37, :922:33] wire [4:0] _mem_stq_e_T_1_bits_uop_mem_cmd = fired_sta_retry_0 ? mem_stq_retry_e_bits_uop_mem_cmd : 5'h0; // @[lsu.scala:263:49, :914:37, :922:33] wire [1:0] _mem_stq_e_T_1_bits_uop_mem_size = fired_sta_retry_0 ? mem_stq_retry_e_bits_uop_mem_size : 2'h0; // @[lsu.scala:263:49, :914:37, :922:33] wire _mem_stq_e_T_1_bits_uop_mem_signed = fired_sta_retry_0 & mem_stq_retry_e_bits_uop_mem_signed; // @[lsu.scala:263:49, :914:37, :922:33] wire _mem_stq_e_T_1_bits_uop_is_fence = fired_sta_retry_0 & mem_stq_retry_e_bits_uop_is_fence; // @[lsu.scala:263:49, :914:37, :922:33] wire _mem_stq_e_T_1_bits_uop_is_fencei = fired_sta_retry_0 & mem_stq_retry_e_bits_uop_is_fencei; // @[lsu.scala:263:49, :914:37, :922:33] wire _mem_stq_e_T_1_bits_uop_is_amo = fired_sta_retry_0 & mem_stq_retry_e_bits_uop_is_amo; // @[lsu.scala:263:49, :914:37, :922:33] wire _mem_stq_e_T_1_bits_uop_uses_ldq = fired_sta_retry_0 & mem_stq_retry_e_bits_uop_uses_ldq; // @[lsu.scala:263:49, :914:37, :922:33] wire _mem_stq_e_T_1_bits_uop_uses_stq = fired_sta_retry_0 & mem_stq_retry_e_bits_uop_uses_stq; // @[lsu.scala:263:49, :914:37, :922:33] wire _mem_stq_e_T_1_bits_uop_is_sys_pc2epc = fired_sta_retry_0 & mem_stq_retry_e_bits_uop_is_sys_pc2epc; // @[lsu.scala:263:49, :914:37, :922:33] wire _mem_stq_e_T_1_bits_uop_is_unique = fired_sta_retry_0 & mem_stq_retry_e_bits_uop_is_unique; // @[lsu.scala:263:49, :914:37, :922:33] wire _mem_stq_e_T_1_bits_uop_flush_on_commit = fired_sta_retry_0 & mem_stq_retry_e_bits_uop_flush_on_commit; // @[lsu.scala:263:49, :914:37, :922:33] wire _mem_stq_e_T_1_bits_uop_ldst_is_rs1 = fired_sta_retry_0 & mem_stq_retry_e_bits_uop_ldst_is_rs1; // @[lsu.scala:263:49, :914:37, :922:33] wire [5:0] _mem_stq_e_T_1_bits_uop_ldst = fired_sta_retry_0 ? mem_stq_retry_e_bits_uop_ldst : 6'h0; // @[lsu.scala:263:49, :914:37, :922:33] wire [5:0] _mem_stq_e_T_1_bits_uop_lrs1 = fired_sta_retry_0 ? mem_stq_retry_e_bits_uop_lrs1 : 6'h0; // @[lsu.scala:263:49, :914:37, :922:33] wire [5:0] _mem_stq_e_T_1_bits_uop_lrs2 = fired_sta_retry_0 ? mem_stq_retry_e_bits_uop_lrs2 : 6'h0; // @[lsu.scala:263:49, :914:37, :922:33] wire [5:0] _mem_stq_e_T_1_bits_uop_lrs3 = fired_sta_retry_0 ? mem_stq_retry_e_bits_uop_lrs3 : 6'h0; // @[lsu.scala:263:49, :914:37, :922:33] wire _mem_stq_e_T_1_bits_uop_ldst_val = fired_sta_retry_0 & mem_stq_retry_e_bits_uop_ldst_val; // @[lsu.scala:263:49, :914:37, :922:33] wire [1:0] _mem_stq_e_T_1_bits_uop_dst_rtype = fired_sta_retry_0 ? mem_stq_retry_e_bits_uop_dst_rtype : 2'h0; // @[lsu.scala:263:49, :914:37, :922:33] wire [1:0] _mem_stq_e_T_1_bits_uop_lrs1_rtype = fired_sta_retry_0 ? mem_stq_retry_e_bits_uop_lrs1_rtype : 2'h0; // @[lsu.scala:263:49, :914:37, :922:33] wire [1:0] _mem_stq_e_T_1_bits_uop_lrs2_rtype = fired_sta_retry_0 ? mem_stq_retry_e_bits_uop_lrs2_rtype : 2'h0; // @[lsu.scala:263:49, :914:37, :922:33] wire _mem_stq_e_T_1_bits_uop_frs3_en = fired_sta_retry_0 & mem_stq_retry_e_bits_uop_frs3_en; // @[lsu.scala:263:49, :914:37, :922:33] wire _mem_stq_e_T_1_bits_uop_fp_val = fired_sta_retry_0 & mem_stq_retry_e_bits_uop_fp_val; // @[lsu.scala:263:49, :914:37, :922:33] wire _mem_stq_e_T_1_bits_uop_fp_single = fired_sta_retry_0 & mem_stq_retry_e_bits_uop_fp_single; // @[lsu.scala:263:49, :914:37, :922:33] wire _mem_stq_e_T_1_bits_uop_xcpt_pf_if = fired_sta_retry_0 & mem_stq_retry_e_bits_uop_xcpt_pf_if; // @[lsu.scala:263:49, :914:37, :922:33] wire _mem_stq_e_T_1_bits_uop_xcpt_ae_if = fired_sta_retry_0 & mem_stq_retry_e_bits_uop_xcpt_ae_if; // @[lsu.scala:263:49, :914:37, :922:33] wire _mem_stq_e_T_1_bits_uop_xcpt_ma_if = fired_sta_retry_0 & mem_stq_retry_e_bits_uop_xcpt_ma_if; // @[lsu.scala:263:49, :914:37, :922:33] wire _mem_stq_e_T_1_bits_uop_bp_debug_if = fired_sta_retry_0 & mem_stq_retry_e_bits_uop_bp_debug_if; // @[lsu.scala:263:49, :914:37, :922:33] wire _mem_stq_e_T_1_bits_uop_bp_xcpt_if = fired_sta_retry_0 & mem_stq_retry_e_bits_uop_bp_xcpt_if; // @[lsu.scala:263:49, :914:37, :922:33] wire [1:0] _mem_stq_e_T_1_bits_uop_debug_fsrc = fired_sta_retry_0 ? mem_stq_retry_e_bits_uop_debug_fsrc : 2'h0; // @[lsu.scala:263:49, :914:37, :922:33] wire [1:0] _mem_stq_e_T_1_bits_uop_debug_tsrc = fired_sta_retry_0 ? mem_stq_retry_e_bits_uop_debug_tsrc : 2'h0; // @[lsu.scala:263:49, :914:37, :922:33] wire _mem_stq_e_T_1_bits_addr_valid = fired_sta_retry_0 & mem_stq_retry_e_bits_addr_valid; // @[lsu.scala:263:49, :914:37, :922:33] wire [39:0] _mem_stq_e_T_1_bits_addr_bits = fired_sta_retry_0 ? mem_stq_retry_e_bits_addr_bits : 40'h0; // @[lsu.scala:263:49, :914:37, :922:33] wire _mem_stq_e_T_1_bits_addr_is_virtual = fired_sta_retry_0 & mem_stq_retry_e_bits_addr_is_virtual; // @[lsu.scala:263:49, :914:37, :922:33] wire _mem_stq_e_T_1_bits_data_valid = fired_sta_retry_0 & mem_stq_retry_e_bits_data_valid; // @[lsu.scala:263:49, :914:37, :922:33] wire [63:0] _mem_stq_e_T_1_bits_data_bits = fired_sta_retry_0 ? mem_stq_retry_e_bits_data_bits : 64'h0; // @[lsu.scala:263:49, :914:37, :922:33] wire _mem_stq_e_T_1_bits_committed = fired_sta_retry_0 & mem_stq_retry_e_bits_committed; // @[lsu.scala:263:49, :914:37, :922:33] wire _mem_stq_e_T_1_bits_succeeded = fired_sta_retry_0 & mem_stq_retry_e_bits_succeeded; // @[lsu.scala:263:49, :914:37, :922:33] wire [63:0] _mem_stq_e_T_1_bits_debug_wb_data = fired_sta_retry_0 ? mem_stq_retry_e_bits_debug_wb_data : 64'h0; // @[lsu.scala:263:49, :914:37, :922:33] wire _mem_stq_e_T_2_valid = _mem_stq_e_T ? mem_stq_incoming_e_0_valid : _mem_stq_e_T_1_valid; // @[lsu.scala:911:37, :920:{33,57}, :922:33] wire [6:0] _mem_stq_e_T_2_bits_uop_uopc = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_uop_uopc : _mem_stq_e_T_1_bits_uop_uopc; // @[lsu.scala:911:37, :920:{33,57}, :922:33] wire [31:0] _mem_stq_e_T_2_bits_uop_inst = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_uop_inst : _mem_stq_e_T_1_bits_uop_inst; // @[lsu.scala:911:37, :920:{33,57}, :922:33] wire [31:0] _mem_stq_e_T_2_bits_uop_debug_inst = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_uop_debug_inst : _mem_stq_e_T_1_bits_uop_debug_inst; // @[lsu.scala:911:37, :920:{33,57}, :922:33] wire _mem_stq_e_T_2_bits_uop_is_rvc = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_uop_is_rvc : _mem_stq_e_T_1_bits_uop_is_rvc; // @[lsu.scala:911:37, :920:{33,57}, :922:33] wire [39:0] _mem_stq_e_T_2_bits_uop_debug_pc = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_uop_debug_pc : _mem_stq_e_T_1_bits_uop_debug_pc; // @[lsu.scala:911:37, :920:{33,57}, :922:33] wire [2:0] _mem_stq_e_T_2_bits_uop_iq_type = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_uop_iq_type : _mem_stq_e_T_1_bits_uop_iq_type; // @[lsu.scala:911:37, :920:{33,57}, :922:33] wire [9:0] _mem_stq_e_T_2_bits_uop_fu_code = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_uop_fu_code : _mem_stq_e_T_1_bits_uop_fu_code; // @[lsu.scala:911:37, :920:{33,57}, :922:33] wire [3:0] _mem_stq_e_T_2_bits_uop_ctrl_br_type = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_uop_ctrl_br_type : _mem_stq_e_T_1_bits_uop_ctrl_br_type; // @[lsu.scala:911:37, :920:{33,57}, :922:33] wire [1:0] _mem_stq_e_T_2_bits_uop_ctrl_op1_sel = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_uop_ctrl_op1_sel : _mem_stq_e_T_1_bits_uop_ctrl_op1_sel; // @[lsu.scala:911:37, :920:{33,57}, :922:33] wire [2:0] _mem_stq_e_T_2_bits_uop_ctrl_op2_sel = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_uop_ctrl_op2_sel : _mem_stq_e_T_1_bits_uop_ctrl_op2_sel; // @[lsu.scala:911:37, :920:{33,57}, :922:33] wire [2:0] _mem_stq_e_T_2_bits_uop_ctrl_imm_sel = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_uop_ctrl_imm_sel : _mem_stq_e_T_1_bits_uop_ctrl_imm_sel; // @[lsu.scala:911:37, :920:{33,57}, :922:33] wire [4:0] _mem_stq_e_T_2_bits_uop_ctrl_op_fcn = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_uop_ctrl_op_fcn : _mem_stq_e_T_1_bits_uop_ctrl_op_fcn; // @[lsu.scala:911:37, :920:{33,57}, :922:33] wire _mem_stq_e_T_2_bits_uop_ctrl_fcn_dw = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_uop_ctrl_fcn_dw : _mem_stq_e_T_1_bits_uop_ctrl_fcn_dw; // @[lsu.scala:911:37, :920:{33,57}, :922:33] wire [2:0] _mem_stq_e_T_2_bits_uop_ctrl_csr_cmd = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_uop_ctrl_csr_cmd : _mem_stq_e_T_1_bits_uop_ctrl_csr_cmd; // @[lsu.scala:911:37, :920:{33,57}, :922:33] wire _mem_stq_e_T_2_bits_uop_ctrl_is_load = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_uop_ctrl_is_load : _mem_stq_e_T_1_bits_uop_ctrl_is_load; // @[lsu.scala:911:37, :920:{33,57}, :922:33] wire _mem_stq_e_T_2_bits_uop_ctrl_is_sta = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_uop_ctrl_is_sta : _mem_stq_e_T_1_bits_uop_ctrl_is_sta; // @[lsu.scala:911:37, :920:{33,57}, :922:33] wire _mem_stq_e_T_2_bits_uop_ctrl_is_std = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_uop_ctrl_is_std : _mem_stq_e_T_1_bits_uop_ctrl_is_std; // @[lsu.scala:911:37, :920:{33,57}, :922:33] wire [1:0] _mem_stq_e_T_2_bits_uop_iw_state = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_uop_iw_state : _mem_stq_e_T_1_bits_uop_iw_state; // @[lsu.scala:911:37, :920:{33,57}, :922:33] wire _mem_stq_e_T_2_bits_uop_iw_p1_poisoned = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_uop_iw_p1_poisoned : _mem_stq_e_T_1_bits_uop_iw_p1_poisoned; // @[lsu.scala:911:37, :920:{33,57}, :922:33] wire _mem_stq_e_T_2_bits_uop_iw_p2_poisoned = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_uop_iw_p2_poisoned : _mem_stq_e_T_1_bits_uop_iw_p2_poisoned; // @[lsu.scala:911:37, :920:{33,57}, :922:33] wire _mem_stq_e_T_2_bits_uop_is_br = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_uop_is_br : _mem_stq_e_T_1_bits_uop_is_br; // @[lsu.scala:911:37, :920:{33,57}, :922:33] wire _mem_stq_e_T_2_bits_uop_is_jalr = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_uop_is_jalr : _mem_stq_e_T_1_bits_uop_is_jalr; // @[lsu.scala:911:37, :920:{33,57}, :922:33] wire _mem_stq_e_T_2_bits_uop_is_jal = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_uop_is_jal : _mem_stq_e_T_1_bits_uop_is_jal; // @[lsu.scala:911:37, :920:{33,57}, :922:33] wire _mem_stq_e_T_2_bits_uop_is_sfb = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_uop_is_sfb : _mem_stq_e_T_1_bits_uop_is_sfb; // @[lsu.scala:911:37, :920:{33,57}, :922:33] wire [7:0] _mem_stq_e_T_2_bits_uop_br_mask = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_uop_br_mask : _mem_stq_e_T_1_bits_uop_br_mask; // @[lsu.scala:911:37, :920:{33,57}, :922:33] wire [2:0] _mem_stq_e_T_2_bits_uop_br_tag = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_uop_br_tag : _mem_stq_e_T_1_bits_uop_br_tag; // @[lsu.scala:911:37, :920:{33,57}, :922:33] wire [3:0] _mem_stq_e_T_2_bits_uop_ftq_idx = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_uop_ftq_idx : _mem_stq_e_T_1_bits_uop_ftq_idx; // @[lsu.scala:911:37, :920:{33,57}, :922:33] wire _mem_stq_e_T_2_bits_uop_edge_inst = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_uop_edge_inst : _mem_stq_e_T_1_bits_uop_edge_inst; // @[lsu.scala:911:37, :920:{33,57}, :922:33] wire [5:0] _mem_stq_e_T_2_bits_uop_pc_lob = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_uop_pc_lob : _mem_stq_e_T_1_bits_uop_pc_lob; // @[lsu.scala:911:37, :920:{33,57}, :922:33] wire _mem_stq_e_T_2_bits_uop_taken = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_uop_taken : _mem_stq_e_T_1_bits_uop_taken; // @[lsu.scala:911:37, :920:{33,57}, :922:33] wire [19:0] _mem_stq_e_T_2_bits_uop_imm_packed = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_uop_imm_packed : _mem_stq_e_T_1_bits_uop_imm_packed; // @[lsu.scala:911:37, :920:{33,57}, :922:33] wire [11:0] _mem_stq_e_T_2_bits_uop_csr_addr = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_uop_csr_addr : _mem_stq_e_T_1_bits_uop_csr_addr; // @[lsu.scala:911:37, :920:{33,57}, :922:33] wire [4:0] _mem_stq_e_T_2_bits_uop_rob_idx = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_uop_rob_idx : _mem_stq_e_T_1_bits_uop_rob_idx; // @[lsu.scala:911:37, :920:{33,57}, :922:33] wire [2:0] _mem_stq_e_T_2_bits_uop_ldq_idx = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_uop_ldq_idx : _mem_stq_e_T_1_bits_uop_ldq_idx; // @[lsu.scala:911:37, :920:{33,57}, :922:33] wire [2:0] _mem_stq_e_T_2_bits_uop_stq_idx = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_uop_stq_idx : _mem_stq_e_T_1_bits_uop_stq_idx; // @[lsu.scala:911:37, :920:{33,57}, :922:33] wire [1:0] _mem_stq_e_T_2_bits_uop_rxq_idx = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_uop_rxq_idx : _mem_stq_e_T_1_bits_uop_rxq_idx; // @[lsu.scala:911:37, :920:{33,57}, :922:33] wire [5:0] _mem_stq_e_T_2_bits_uop_pdst = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_uop_pdst : _mem_stq_e_T_1_bits_uop_pdst; // @[lsu.scala:911:37, :920:{33,57}, :922:33] wire [5:0] _mem_stq_e_T_2_bits_uop_prs1 = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_uop_prs1 : _mem_stq_e_T_1_bits_uop_prs1; // @[lsu.scala:911:37, :920:{33,57}, :922:33] wire [5:0] _mem_stq_e_T_2_bits_uop_prs2 = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_uop_prs2 : _mem_stq_e_T_1_bits_uop_prs2; // @[lsu.scala:911:37, :920:{33,57}, :922:33] wire [5:0] _mem_stq_e_T_2_bits_uop_prs3 = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_uop_prs3 : _mem_stq_e_T_1_bits_uop_prs3; // @[lsu.scala:911:37, :920:{33,57}, :922:33] wire [3:0] _mem_stq_e_T_2_bits_uop_ppred = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_uop_ppred : _mem_stq_e_T_1_bits_uop_ppred; // @[lsu.scala:911:37, :920:{33,57}, :922:33] wire _mem_stq_e_T_2_bits_uop_prs1_busy = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_uop_prs1_busy : _mem_stq_e_T_1_bits_uop_prs1_busy; // @[lsu.scala:911:37, :920:{33,57}, :922:33] wire _mem_stq_e_T_2_bits_uop_prs2_busy = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_uop_prs2_busy : _mem_stq_e_T_1_bits_uop_prs2_busy; // @[lsu.scala:911:37, :920:{33,57}, :922:33] wire _mem_stq_e_T_2_bits_uop_prs3_busy = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_uop_prs3_busy : _mem_stq_e_T_1_bits_uop_prs3_busy; // @[lsu.scala:911:37, :920:{33,57}, :922:33] wire _mem_stq_e_T_2_bits_uop_ppred_busy = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_uop_ppred_busy : _mem_stq_e_T_1_bits_uop_ppred_busy; // @[lsu.scala:911:37, :920:{33,57}, :922:33] wire [5:0] _mem_stq_e_T_2_bits_uop_stale_pdst = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_uop_stale_pdst : _mem_stq_e_T_1_bits_uop_stale_pdst; // @[lsu.scala:911:37, :920:{33,57}, :922:33] wire _mem_stq_e_T_2_bits_uop_exception = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_uop_exception : _mem_stq_e_T_1_bits_uop_exception; // @[lsu.scala:911:37, :920:{33,57}, :922:33] wire [63:0] _mem_stq_e_T_2_bits_uop_exc_cause = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_uop_exc_cause : _mem_stq_e_T_1_bits_uop_exc_cause; // @[lsu.scala:911:37, :920:{33,57}, :922:33] wire _mem_stq_e_T_2_bits_uop_bypassable = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_uop_bypassable : _mem_stq_e_T_1_bits_uop_bypassable; // @[lsu.scala:911:37, :920:{33,57}, :922:33] wire [4:0] _mem_stq_e_T_2_bits_uop_mem_cmd = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_uop_mem_cmd : _mem_stq_e_T_1_bits_uop_mem_cmd; // @[lsu.scala:911:37, :920:{33,57}, :922:33] wire [1:0] _mem_stq_e_T_2_bits_uop_mem_size = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_uop_mem_size : _mem_stq_e_T_1_bits_uop_mem_size; // @[lsu.scala:911:37, :920:{33,57}, :922:33] wire _mem_stq_e_T_2_bits_uop_mem_signed = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_uop_mem_signed : _mem_stq_e_T_1_bits_uop_mem_signed; // @[lsu.scala:911:37, :920:{33,57}, :922:33] wire _mem_stq_e_T_2_bits_uop_is_fence = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_uop_is_fence : _mem_stq_e_T_1_bits_uop_is_fence; // @[lsu.scala:911:37, :920:{33,57}, :922:33] wire _mem_stq_e_T_2_bits_uop_is_fencei = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_uop_is_fencei : _mem_stq_e_T_1_bits_uop_is_fencei; // @[lsu.scala:911:37, :920:{33,57}, :922:33] wire _mem_stq_e_T_2_bits_uop_is_amo = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_uop_is_amo : _mem_stq_e_T_1_bits_uop_is_amo; // @[lsu.scala:911:37, :920:{33,57}, :922:33] wire _mem_stq_e_T_2_bits_uop_uses_ldq = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_uop_uses_ldq : _mem_stq_e_T_1_bits_uop_uses_ldq; // @[lsu.scala:911:37, :920:{33,57}, :922:33] wire _mem_stq_e_T_2_bits_uop_uses_stq = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_uop_uses_stq : _mem_stq_e_T_1_bits_uop_uses_stq; // @[lsu.scala:911:37, :920:{33,57}, :922:33] wire _mem_stq_e_T_2_bits_uop_is_sys_pc2epc = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_uop_is_sys_pc2epc : _mem_stq_e_T_1_bits_uop_is_sys_pc2epc; // @[lsu.scala:911:37, :920:{33,57}, :922:33] wire _mem_stq_e_T_2_bits_uop_is_unique = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_uop_is_unique : _mem_stq_e_T_1_bits_uop_is_unique; // @[lsu.scala:911:37, :920:{33,57}, :922:33] wire _mem_stq_e_T_2_bits_uop_flush_on_commit = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_uop_flush_on_commit : _mem_stq_e_T_1_bits_uop_flush_on_commit; // @[lsu.scala:911:37, :920:{33,57}, :922:33] wire _mem_stq_e_T_2_bits_uop_ldst_is_rs1 = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_uop_ldst_is_rs1 : _mem_stq_e_T_1_bits_uop_ldst_is_rs1; // @[lsu.scala:911:37, :920:{33,57}, :922:33] wire [5:0] _mem_stq_e_T_2_bits_uop_ldst = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_uop_ldst : _mem_stq_e_T_1_bits_uop_ldst; // @[lsu.scala:911:37, :920:{33,57}, :922:33] wire [5:0] _mem_stq_e_T_2_bits_uop_lrs1 = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_uop_lrs1 : _mem_stq_e_T_1_bits_uop_lrs1; // @[lsu.scala:911:37, :920:{33,57}, :922:33] wire [5:0] _mem_stq_e_T_2_bits_uop_lrs2 = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_uop_lrs2 : _mem_stq_e_T_1_bits_uop_lrs2; // @[lsu.scala:911:37, :920:{33,57}, :922:33] wire [5:0] _mem_stq_e_T_2_bits_uop_lrs3 = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_uop_lrs3 : _mem_stq_e_T_1_bits_uop_lrs3; // @[lsu.scala:911:37, :920:{33,57}, :922:33] wire _mem_stq_e_T_2_bits_uop_ldst_val = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_uop_ldst_val : _mem_stq_e_T_1_bits_uop_ldst_val; // @[lsu.scala:911:37, :920:{33,57}, :922:33] wire [1:0] _mem_stq_e_T_2_bits_uop_dst_rtype = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_uop_dst_rtype : _mem_stq_e_T_1_bits_uop_dst_rtype; // @[lsu.scala:911:37, :920:{33,57}, :922:33] wire [1:0] _mem_stq_e_T_2_bits_uop_lrs1_rtype = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_uop_lrs1_rtype : _mem_stq_e_T_1_bits_uop_lrs1_rtype; // @[lsu.scala:911:37, :920:{33,57}, :922:33] wire [1:0] _mem_stq_e_T_2_bits_uop_lrs2_rtype = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_uop_lrs2_rtype : _mem_stq_e_T_1_bits_uop_lrs2_rtype; // @[lsu.scala:911:37, :920:{33,57}, :922:33] wire _mem_stq_e_T_2_bits_uop_frs3_en = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_uop_frs3_en : _mem_stq_e_T_1_bits_uop_frs3_en; // @[lsu.scala:911:37, :920:{33,57}, :922:33] wire _mem_stq_e_T_2_bits_uop_fp_val = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_uop_fp_val : _mem_stq_e_T_1_bits_uop_fp_val; // @[lsu.scala:911:37, :920:{33,57}, :922:33] wire _mem_stq_e_T_2_bits_uop_fp_single = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_uop_fp_single : _mem_stq_e_T_1_bits_uop_fp_single; // @[lsu.scala:911:37, :920:{33,57}, :922:33] wire _mem_stq_e_T_2_bits_uop_xcpt_pf_if = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_uop_xcpt_pf_if : _mem_stq_e_T_1_bits_uop_xcpt_pf_if; // @[lsu.scala:911:37, :920:{33,57}, :922:33] wire _mem_stq_e_T_2_bits_uop_xcpt_ae_if = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_uop_xcpt_ae_if : _mem_stq_e_T_1_bits_uop_xcpt_ae_if; // @[lsu.scala:911:37, :920:{33,57}, :922:33] wire _mem_stq_e_T_2_bits_uop_xcpt_ma_if = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_uop_xcpt_ma_if : _mem_stq_e_T_1_bits_uop_xcpt_ma_if; // @[lsu.scala:911:37, :920:{33,57}, :922:33] wire _mem_stq_e_T_2_bits_uop_bp_debug_if = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_uop_bp_debug_if : _mem_stq_e_T_1_bits_uop_bp_debug_if; // @[lsu.scala:911:37, :920:{33,57}, :922:33] wire _mem_stq_e_T_2_bits_uop_bp_xcpt_if = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_uop_bp_xcpt_if : _mem_stq_e_T_1_bits_uop_bp_xcpt_if; // @[lsu.scala:911:37, :920:{33,57}, :922:33] wire [1:0] _mem_stq_e_T_2_bits_uop_debug_fsrc = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_uop_debug_fsrc : _mem_stq_e_T_1_bits_uop_debug_fsrc; // @[lsu.scala:911:37, :920:{33,57}, :922:33] wire [1:0] _mem_stq_e_T_2_bits_uop_debug_tsrc = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_uop_debug_tsrc : _mem_stq_e_T_1_bits_uop_debug_tsrc; // @[lsu.scala:911:37, :920:{33,57}, :922:33] wire _mem_stq_e_T_2_bits_addr_valid = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_addr_valid : _mem_stq_e_T_1_bits_addr_valid; // @[lsu.scala:911:37, :920:{33,57}, :922:33] wire [39:0] _mem_stq_e_T_2_bits_addr_bits = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_addr_bits : _mem_stq_e_T_1_bits_addr_bits; // @[lsu.scala:911:37, :920:{33,57}, :922:33] wire _mem_stq_e_T_2_bits_addr_is_virtual = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_addr_is_virtual : _mem_stq_e_T_1_bits_addr_is_virtual; // @[lsu.scala:911:37, :920:{33,57}, :922:33] wire _mem_stq_e_T_2_bits_data_valid = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_data_valid : _mem_stq_e_T_1_bits_data_valid; // @[lsu.scala:911:37, :920:{33,57}, :922:33] wire [63:0] _mem_stq_e_T_2_bits_data_bits = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_data_bits : _mem_stq_e_T_1_bits_data_bits; // @[lsu.scala:911:37, :920:{33,57}, :922:33] wire _mem_stq_e_T_2_bits_committed = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_committed : _mem_stq_e_T_1_bits_committed; // @[lsu.scala:911:37, :920:{33,57}, :922:33] wire _mem_stq_e_T_2_bits_succeeded = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_succeeded : _mem_stq_e_T_1_bits_succeeded; // @[lsu.scala:911:37, :920:{33,57}, :922:33] wire [63:0] _mem_stq_e_T_2_bits_debug_wb_data = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_debug_wb_data : _mem_stq_e_T_1_bits_debug_wb_data; // @[lsu.scala:911:37, :920:{33,57}, :922:33] wire mem_stq_e_0_valid = _mem_stq_e_T_2_valid; // @[lsu.scala:263:49, :920:33] wire [6:0] mem_stq_e_0_bits_uop_uopc = _mem_stq_e_T_2_bits_uop_uopc; // @[lsu.scala:263:49, :920:33] wire [31:0] mem_stq_e_0_bits_uop_inst = _mem_stq_e_T_2_bits_uop_inst; // @[lsu.scala:263:49, :920:33] wire [31:0] mem_stq_e_0_bits_uop_debug_inst = _mem_stq_e_T_2_bits_uop_debug_inst; // @[lsu.scala:263:49, :920:33] wire mem_stq_e_0_bits_uop_is_rvc = _mem_stq_e_T_2_bits_uop_is_rvc; // @[lsu.scala:263:49, :920:33] wire [39:0] mem_stq_e_0_bits_uop_debug_pc = _mem_stq_e_T_2_bits_uop_debug_pc; // @[lsu.scala:263:49, :920:33] wire [2:0] mem_stq_e_0_bits_uop_iq_type = _mem_stq_e_T_2_bits_uop_iq_type; // @[lsu.scala:263:49, :920:33] wire [9:0] mem_stq_e_0_bits_uop_fu_code = _mem_stq_e_T_2_bits_uop_fu_code; // @[lsu.scala:263:49, :920:33] wire [3:0] mem_stq_e_0_bits_uop_ctrl_br_type = _mem_stq_e_T_2_bits_uop_ctrl_br_type; // @[lsu.scala:263:49, :920:33] wire [1:0] mem_stq_e_0_bits_uop_ctrl_op1_sel = _mem_stq_e_T_2_bits_uop_ctrl_op1_sel; // @[lsu.scala:263:49, :920:33] wire [2:0] mem_stq_e_0_bits_uop_ctrl_op2_sel = _mem_stq_e_T_2_bits_uop_ctrl_op2_sel; // @[lsu.scala:263:49, :920:33] wire [2:0] mem_stq_e_0_bits_uop_ctrl_imm_sel = _mem_stq_e_T_2_bits_uop_ctrl_imm_sel; // @[lsu.scala:263:49, :920:33] wire [4:0] mem_stq_e_0_bits_uop_ctrl_op_fcn = _mem_stq_e_T_2_bits_uop_ctrl_op_fcn; // @[lsu.scala:263:49, :920:33] wire mem_stq_e_0_bits_uop_ctrl_fcn_dw = _mem_stq_e_T_2_bits_uop_ctrl_fcn_dw; // @[lsu.scala:263:49, :920:33] wire [2:0] mem_stq_e_0_bits_uop_ctrl_csr_cmd = _mem_stq_e_T_2_bits_uop_ctrl_csr_cmd; // @[lsu.scala:263:49, :920:33] wire mem_stq_e_0_bits_uop_ctrl_is_load = _mem_stq_e_T_2_bits_uop_ctrl_is_load; // @[lsu.scala:263:49, :920:33] wire mem_stq_e_0_bits_uop_ctrl_is_sta = _mem_stq_e_T_2_bits_uop_ctrl_is_sta; // @[lsu.scala:263:49, :920:33] wire mem_stq_e_0_bits_uop_ctrl_is_std = _mem_stq_e_T_2_bits_uop_ctrl_is_std; // @[lsu.scala:263:49, :920:33] wire [1:0] mem_stq_e_0_bits_uop_iw_state = _mem_stq_e_T_2_bits_uop_iw_state; // @[lsu.scala:263:49, :920:33] wire mem_stq_e_0_bits_uop_iw_p1_poisoned = _mem_stq_e_T_2_bits_uop_iw_p1_poisoned; // @[lsu.scala:263:49, :920:33] wire mem_stq_e_0_bits_uop_iw_p2_poisoned = _mem_stq_e_T_2_bits_uop_iw_p2_poisoned; // @[lsu.scala:263:49, :920:33] wire mem_stq_e_0_bits_uop_is_br = _mem_stq_e_T_2_bits_uop_is_br; // @[lsu.scala:263:49, :920:33] wire mem_stq_e_0_bits_uop_is_jalr = _mem_stq_e_T_2_bits_uop_is_jalr; // @[lsu.scala:263:49, :920:33] wire mem_stq_e_0_bits_uop_is_jal = _mem_stq_e_T_2_bits_uop_is_jal; // @[lsu.scala:263:49, :920:33] wire mem_stq_e_0_bits_uop_is_sfb = _mem_stq_e_T_2_bits_uop_is_sfb; // @[lsu.scala:263:49, :920:33] wire [7:0] mem_stq_e_0_bits_uop_br_mask = _mem_stq_e_T_2_bits_uop_br_mask; // @[lsu.scala:263:49, :920:33] wire [2:0] mem_stq_e_0_bits_uop_br_tag = _mem_stq_e_T_2_bits_uop_br_tag; // @[lsu.scala:263:49, :920:33] wire [3:0] mem_stq_e_0_bits_uop_ftq_idx = _mem_stq_e_T_2_bits_uop_ftq_idx; // @[lsu.scala:263:49, :920:33] wire mem_stq_e_0_bits_uop_edge_inst = _mem_stq_e_T_2_bits_uop_edge_inst; // @[lsu.scala:263:49, :920:33] wire [5:0] mem_stq_e_0_bits_uop_pc_lob = _mem_stq_e_T_2_bits_uop_pc_lob; // @[lsu.scala:263:49, :920:33] wire mem_stq_e_0_bits_uop_taken = _mem_stq_e_T_2_bits_uop_taken; // @[lsu.scala:263:49, :920:33] wire [19:0] mem_stq_e_0_bits_uop_imm_packed = _mem_stq_e_T_2_bits_uop_imm_packed; // @[lsu.scala:263:49, :920:33] wire [11:0] mem_stq_e_0_bits_uop_csr_addr = _mem_stq_e_T_2_bits_uop_csr_addr; // @[lsu.scala:263:49, :920:33] wire [4:0] mem_stq_e_0_bits_uop_rob_idx = _mem_stq_e_T_2_bits_uop_rob_idx; // @[lsu.scala:263:49, :920:33] wire [2:0] mem_stq_e_0_bits_uop_ldq_idx = _mem_stq_e_T_2_bits_uop_ldq_idx; // @[lsu.scala:263:49, :920:33] wire [2:0] mem_stq_e_0_bits_uop_stq_idx = _mem_stq_e_T_2_bits_uop_stq_idx; // @[lsu.scala:263:49, :920:33] wire [1:0] mem_stq_e_0_bits_uop_rxq_idx = _mem_stq_e_T_2_bits_uop_rxq_idx; // @[lsu.scala:263:49, :920:33] wire [5:0] mem_stq_e_0_bits_uop_pdst = _mem_stq_e_T_2_bits_uop_pdst; // @[lsu.scala:263:49, :920:33] wire [5:0] mem_stq_e_0_bits_uop_prs1 = _mem_stq_e_T_2_bits_uop_prs1; // @[lsu.scala:263:49, :920:33] wire [5:0] mem_stq_e_0_bits_uop_prs2 = _mem_stq_e_T_2_bits_uop_prs2; // @[lsu.scala:263:49, :920:33] wire [5:0] mem_stq_e_0_bits_uop_prs3 = _mem_stq_e_T_2_bits_uop_prs3; // @[lsu.scala:263:49, :920:33] wire [3:0] mem_stq_e_0_bits_uop_ppred = _mem_stq_e_T_2_bits_uop_ppred; // @[lsu.scala:263:49, :920:33] wire mem_stq_e_0_bits_uop_prs1_busy = _mem_stq_e_T_2_bits_uop_prs1_busy; // @[lsu.scala:263:49, :920:33] wire mem_stq_e_0_bits_uop_prs2_busy = _mem_stq_e_T_2_bits_uop_prs2_busy; // @[lsu.scala:263:49, :920:33] wire mem_stq_e_0_bits_uop_prs3_busy = _mem_stq_e_T_2_bits_uop_prs3_busy; // @[lsu.scala:263:49, :920:33] wire mem_stq_e_0_bits_uop_ppred_busy = _mem_stq_e_T_2_bits_uop_ppred_busy; // @[lsu.scala:263:49, :920:33] wire [5:0] mem_stq_e_0_bits_uop_stale_pdst = _mem_stq_e_T_2_bits_uop_stale_pdst; // @[lsu.scala:263:49, :920:33] wire mem_stq_e_0_bits_uop_exception = _mem_stq_e_T_2_bits_uop_exception; // @[lsu.scala:263:49, :920:33] wire [63:0] mem_stq_e_0_bits_uop_exc_cause = _mem_stq_e_T_2_bits_uop_exc_cause; // @[lsu.scala:263:49, :920:33] wire mem_stq_e_0_bits_uop_bypassable = _mem_stq_e_T_2_bits_uop_bypassable; // @[lsu.scala:263:49, :920:33] wire [4:0] mem_stq_e_0_bits_uop_mem_cmd = _mem_stq_e_T_2_bits_uop_mem_cmd; // @[lsu.scala:263:49, :920:33] wire [1:0] mem_stq_e_0_bits_uop_mem_size = _mem_stq_e_T_2_bits_uop_mem_size; // @[lsu.scala:263:49, :920:33] wire mem_stq_e_0_bits_uop_mem_signed = _mem_stq_e_T_2_bits_uop_mem_signed; // @[lsu.scala:263:49, :920:33] wire mem_stq_e_0_bits_uop_is_fence = _mem_stq_e_T_2_bits_uop_is_fence; // @[lsu.scala:263:49, :920:33] wire mem_stq_e_0_bits_uop_is_fencei = _mem_stq_e_T_2_bits_uop_is_fencei; // @[lsu.scala:263:49, :920:33] wire mem_stq_e_0_bits_uop_is_amo = _mem_stq_e_T_2_bits_uop_is_amo; // @[lsu.scala:263:49, :920:33] wire mem_stq_e_0_bits_uop_uses_ldq = _mem_stq_e_T_2_bits_uop_uses_ldq; // @[lsu.scala:263:49, :920:33] wire mem_stq_e_0_bits_uop_uses_stq = _mem_stq_e_T_2_bits_uop_uses_stq; // @[lsu.scala:263:49, :920:33] wire mem_stq_e_0_bits_uop_is_sys_pc2epc = _mem_stq_e_T_2_bits_uop_is_sys_pc2epc; // @[lsu.scala:263:49, :920:33] wire mem_stq_e_0_bits_uop_is_unique = _mem_stq_e_T_2_bits_uop_is_unique; // @[lsu.scala:263:49, :920:33] wire mem_stq_e_0_bits_uop_flush_on_commit = _mem_stq_e_T_2_bits_uop_flush_on_commit; // @[lsu.scala:263:49, :920:33] wire mem_stq_e_0_bits_uop_ldst_is_rs1 = _mem_stq_e_T_2_bits_uop_ldst_is_rs1; // @[lsu.scala:263:49, :920:33] wire [5:0] mem_stq_e_0_bits_uop_ldst = _mem_stq_e_T_2_bits_uop_ldst; // @[lsu.scala:263:49, :920:33] wire [5:0] mem_stq_e_0_bits_uop_lrs1 = _mem_stq_e_T_2_bits_uop_lrs1; // @[lsu.scala:263:49, :920:33] wire [5:0] mem_stq_e_0_bits_uop_lrs2 = _mem_stq_e_T_2_bits_uop_lrs2; // @[lsu.scala:263:49, :920:33] wire [5:0] mem_stq_e_0_bits_uop_lrs3 = _mem_stq_e_T_2_bits_uop_lrs3; // @[lsu.scala:263:49, :920:33] wire mem_stq_e_0_bits_uop_ldst_val = _mem_stq_e_T_2_bits_uop_ldst_val; // @[lsu.scala:263:49, :920:33] wire [1:0] mem_stq_e_0_bits_uop_dst_rtype = _mem_stq_e_T_2_bits_uop_dst_rtype; // @[lsu.scala:263:49, :920:33] wire [1:0] mem_stq_e_0_bits_uop_lrs1_rtype = _mem_stq_e_T_2_bits_uop_lrs1_rtype; // @[lsu.scala:263:49, :920:33] wire [1:0] mem_stq_e_0_bits_uop_lrs2_rtype = _mem_stq_e_T_2_bits_uop_lrs2_rtype; // @[lsu.scala:263:49, :920:33] wire mem_stq_e_0_bits_uop_frs3_en = _mem_stq_e_T_2_bits_uop_frs3_en; // @[lsu.scala:263:49, :920:33] wire mem_stq_e_0_bits_uop_fp_val = _mem_stq_e_T_2_bits_uop_fp_val; // @[lsu.scala:263:49, :920:33] wire mem_stq_e_0_bits_uop_fp_single = _mem_stq_e_T_2_bits_uop_fp_single; // @[lsu.scala:263:49, :920:33] wire mem_stq_e_0_bits_uop_xcpt_pf_if = _mem_stq_e_T_2_bits_uop_xcpt_pf_if; // @[lsu.scala:263:49, :920:33] wire mem_stq_e_0_bits_uop_xcpt_ae_if = _mem_stq_e_T_2_bits_uop_xcpt_ae_if; // @[lsu.scala:263:49, :920:33] wire mem_stq_e_0_bits_uop_xcpt_ma_if = _mem_stq_e_T_2_bits_uop_xcpt_ma_if; // @[lsu.scala:263:49, :920:33] wire mem_stq_e_0_bits_uop_bp_debug_if = _mem_stq_e_T_2_bits_uop_bp_debug_if; // @[lsu.scala:263:49, :920:33] wire mem_stq_e_0_bits_uop_bp_xcpt_if = _mem_stq_e_T_2_bits_uop_bp_xcpt_if; // @[lsu.scala:263:49, :920:33] wire [1:0] mem_stq_e_0_bits_uop_debug_fsrc = _mem_stq_e_T_2_bits_uop_debug_fsrc; // @[lsu.scala:263:49, :920:33] wire [1:0] mem_stq_e_0_bits_uop_debug_tsrc = _mem_stq_e_T_2_bits_uop_debug_tsrc; // @[lsu.scala:263:49, :920:33] wire mem_stq_e_0_bits_addr_valid = _mem_stq_e_T_2_bits_addr_valid; // @[lsu.scala:263:49, :920:33] wire [39:0] mem_stq_e_0_bits_addr_bits = _mem_stq_e_T_2_bits_addr_bits; // @[lsu.scala:263:49, :920:33] wire mem_stq_e_0_bits_addr_is_virtual = _mem_stq_e_T_2_bits_addr_is_virtual; // @[lsu.scala:263:49, :920:33] wire mem_stq_e_0_bits_data_valid = _mem_stq_e_T_2_bits_data_valid; // @[lsu.scala:263:49, :920:33] wire [63:0] mem_stq_e_0_bits_data_bits = _mem_stq_e_T_2_bits_data_bits; // @[lsu.scala:263:49, :920:33] wire mem_stq_e_0_bits_committed = _mem_stq_e_T_2_bits_committed; // @[lsu.scala:263:49, :920:33] wire mem_stq_e_0_bits_succeeded = _mem_stq_e_T_2_bits_succeeded; // @[lsu.scala:263:49, :920:33] wire [63:0] mem_stq_e_0_bits_debug_wb_data = _mem_stq_e_T_2_bits_debug_wb_data; // @[lsu.scala:263:49, :920:33] wire [7:0] _mem_stdf_uop_out_br_mask_T_1; // @[util.scala:85:25] wire [7:0] mem_stdf_uop_out_br_mask; // @[util.scala:96:23] wire [7:0] _mem_stdf_uop_out_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:85:27] assign _mem_stdf_uop_out_br_mask_T_1 = io_core_fp_stdata_bits_uop_br_mask_0 & _mem_stdf_uop_out_br_mask_T; // @[util.scala:85:{25,27}] assign mem_stdf_uop_out_br_mask = _mem_stdf_uop_out_br_mask_T_1; // @[util.scala:85:25, :96:23] reg [6:0] mem_stdf_uop_uopc; // @[lsu.scala:923:37] reg [31:0] mem_stdf_uop_inst; // @[lsu.scala:923:37] reg [31:0] mem_stdf_uop_debug_inst; // @[lsu.scala:923:37] reg mem_stdf_uop_is_rvc; // @[lsu.scala:923:37] reg [39:0] mem_stdf_uop_debug_pc; // @[lsu.scala:923:37] reg [2:0] mem_stdf_uop_iq_type; // @[lsu.scala:923:37] reg [9:0] mem_stdf_uop_fu_code; // @[lsu.scala:923:37] reg [3:0] mem_stdf_uop_ctrl_br_type; // @[lsu.scala:923:37] reg [1:0] mem_stdf_uop_ctrl_op1_sel; // @[lsu.scala:923:37] reg [2:0] mem_stdf_uop_ctrl_op2_sel; // @[lsu.scala:923:37] reg [2:0] mem_stdf_uop_ctrl_imm_sel; // @[lsu.scala:923:37] reg [4:0] mem_stdf_uop_ctrl_op_fcn; // @[lsu.scala:923:37] reg mem_stdf_uop_ctrl_fcn_dw; // @[lsu.scala:923:37] reg [2:0] mem_stdf_uop_ctrl_csr_cmd; // @[lsu.scala:923:37] reg mem_stdf_uop_ctrl_is_load; // @[lsu.scala:923:37] reg mem_stdf_uop_ctrl_is_sta; // @[lsu.scala:923:37] reg mem_stdf_uop_ctrl_is_std; // @[lsu.scala:923:37] reg [1:0] mem_stdf_uop_iw_state; // @[lsu.scala:923:37] reg mem_stdf_uop_iw_p1_poisoned; // @[lsu.scala:923:37] reg mem_stdf_uop_iw_p2_poisoned; // @[lsu.scala:923:37] reg mem_stdf_uop_is_br; // @[lsu.scala:923:37] reg mem_stdf_uop_is_jalr; // @[lsu.scala:923:37] reg mem_stdf_uop_is_jal; // @[lsu.scala:923:37] reg mem_stdf_uop_is_sfb; // @[lsu.scala:923:37] reg [7:0] mem_stdf_uop_br_mask; // @[lsu.scala:923:37] reg [2:0] mem_stdf_uop_br_tag; // @[lsu.scala:923:37] reg [3:0] mem_stdf_uop_ftq_idx; // @[lsu.scala:923:37] reg mem_stdf_uop_edge_inst; // @[lsu.scala:923:37] reg [5:0] mem_stdf_uop_pc_lob; // @[lsu.scala:923:37] reg mem_stdf_uop_taken; // @[lsu.scala:923:37] reg [19:0] mem_stdf_uop_imm_packed; // @[lsu.scala:923:37] reg [11:0] mem_stdf_uop_csr_addr; // @[lsu.scala:923:37] reg [4:0] mem_stdf_uop_rob_idx; // @[lsu.scala:923:37] reg [2:0] mem_stdf_uop_ldq_idx; // @[lsu.scala:923:37] reg [2:0] mem_stdf_uop_stq_idx; // @[lsu.scala:923:37] reg [1:0] mem_stdf_uop_rxq_idx; // @[lsu.scala:923:37] reg [5:0] mem_stdf_uop_pdst; // @[lsu.scala:923:37] reg [5:0] mem_stdf_uop_prs1; // @[lsu.scala:923:37] reg [5:0] mem_stdf_uop_prs2; // @[lsu.scala:923:37] reg [5:0] mem_stdf_uop_prs3; // @[lsu.scala:923:37] reg [3:0] mem_stdf_uop_ppred; // @[lsu.scala:923:37] reg mem_stdf_uop_prs1_busy; // @[lsu.scala:923:37] reg mem_stdf_uop_prs2_busy; // @[lsu.scala:923:37] reg mem_stdf_uop_prs3_busy; // @[lsu.scala:923:37] reg mem_stdf_uop_ppred_busy; // @[lsu.scala:923:37] reg [5:0] mem_stdf_uop_stale_pdst; // @[lsu.scala:923:37] reg mem_stdf_uop_exception; // @[lsu.scala:923:37] reg [63:0] mem_stdf_uop_exc_cause; // @[lsu.scala:923:37] reg mem_stdf_uop_bypassable; // @[lsu.scala:923:37] reg [4:0] mem_stdf_uop_mem_cmd; // @[lsu.scala:923:37] reg [1:0] mem_stdf_uop_mem_size; // @[lsu.scala:923:37] reg mem_stdf_uop_mem_signed; // @[lsu.scala:923:37] reg mem_stdf_uop_is_fence; // @[lsu.scala:923:37] reg mem_stdf_uop_is_fencei; // @[lsu.scala:923:37] reg mem_stdf_uop_is_amo; // @[lsu.scala:923:37] reg mem_stdf_uop_uses_ldq; // @[lsu.scala:923:37] reg mem_stdf_uop_uses_stq; // @[lsu.scala:923:37] reg mem_stdf_uop_is_sys_pc2epc; // @[lsu.scala:923:37] reg mem_stdf_uop_is_unique; // @[lsu.scala:923:37] reg mem_stdf_uop_flush_on_commit; // @[lsu.scala:923:37] reg mem_stdf_uop_ldst_is_rs1; // @[lsu.scala:923:37] reg [5:0] mem_stdf_uop_ldst; // @[lsu.scala:923:37] reg [5:0] mem_stdf_uop_lrs1; // @[lsu.scala:923:37] reg [5:0] mem_stdf_uop_lrs2; // @[lsu.scala:923:37] reg [5:0] mem_stdf_uop_lrs3; // @[lsu.scala:923:37] reg mem_stdf_uop_ldst_val; // @[lsu.scala:923:37] reg [1:0] mem_stdf_uop_dst_rtype; // @[lsu.scala:923:37] reg [1:0] mem_stdf_uop_lrs1_rtype; // @[lsu.scala:923:37] reg [1:0] mem_stdf_uop_lrs2_rtype; // @[lsu.scala:923:37] reg mem_stdf_uop_frs3_en; // @[lsu.scala:923:37] reg mem_stdf_uop_fp_val; // @[lsu.scala:923:37] reg mem_stdf_uop_fp_single; // @[lsu.scala:923:37] reg mem_stdf_uop_xcpt_pf_if; // @[lsu.scala:923:37] reg mem_stdf_uop_xcpt_ae_if; // @[lsu.scala:923:37] reg mem_stdf_uop_xcpt_ma_if; // @[lsu.scala:923:37] reg mem_stdf_uop_bp_debug_if; // @[lsu.scala:923:37] reg mem_stdf_uop_bp_xcpt_if; // @[lsu.scala:923:37] reg [1:0] mem_stdf_uop_debug_fsrc; // @[lsu.scala:923:37] reg [1:0] mem_stdf_uop_debug_tsrc; // @[lsu.scala:923:37] reg mem_tlb_miss_0; // @[lsu.scala:926:41] reg mem_tlb_uncacheable_0; // @[lsu.scala:927:41] reg [39:0] mem_paddr_0; // @[lsu.scala:928:41] reg clr_bsy_valid_0; // @[lsu.scala:931:32] reg [4:0] clr_bsy_rob_idx_0; // @[lsu.scala:932:28] assign io_core_clr_bsy_0_bits_0 = clr_bsy_rob_idx_0; // @[lsu.scala:201:7, :932:28] reg [7:0] clr_bsy_brmask_0; // @[lsu.scala:933:28] wire _clr_bsy_valid_0_T = ~mem_tlb_miss_0; // @[lsu.scala:926:41, :943:29] wire _clr_bsy_valid_0_T_1 = mem_stq_incoming_e_0_valid & _clr_bsy_valid_0_T; // @[lsu.scala:911:37, :942:68, :943:29] wire _clr_bsy_valid_0_T_2 = ~mem_stq_incoming_e_0_bits_uop_is_amo; // @[lsu.scala:911:37, :944:29] wire _clr_bsy_valid_0_T_3 = _clr_bsy_valid_0_T_1 & _clr_bsy_valid_0_T_2; // @[lsu.scala:942:68, :943:68, :944:29] wire [7:0] _GEN_227 = io_core_brupdate_b1_mispredict_mask_0 & mem_stq_incoming_e_0_bits_uop_br_mask; // @[util.scala:118:51] wire [7:0] _clr_bsy_valid_0_T_4; // @[util.scala:118:51] assign _clr_bsy_valid_0_T_4 = _GEN_227; // @[util.scala:118:51] wire [7:0] _clr_bsy_valid_0_T_13; // @[util.scala:118:51] assign _clr_bsy_valid_0_T_13 = _GEN_227; // @[util.scala:118:51] wire [7:0] _clr_bsy_valid_0_T_22; // @[util.scala:118:51] assign _clr_bsy_valid_0_T_22 = _GEN_227; // @[util.scala:118:51] wire _clr_bsy_valid_0_T_5 = \|_clr_bsy_valid_0_T_4; // @[util.scala:118:{51,59}] wire _clr_bsy_valid_0_T_6 = ~_clr_bsy_valid_0_T_5; // @[util.scala:118:59] wire _clr_bsy_valid_0_T_7 = _clr_bsy_valid_0_T_3 & _clr_bsy_valid_0_T_6; // @[lsu.scala:943:68, :944:68, :945:29] wire [7:0] _clr_bsy_brmask_0_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:85:27] wire [7:0] _clr_bsy_brmask_0_T_1 = mem_stq_incoming_e_0_bits_uop_br_mask & _clr_bsy_brmask_0_T; // @[util.scala:85:{25,27}] wire _clr_bsy_valid_0_T_8 = mem_stq_incoming_e_0_valid & mem_stq_incoming_e_0_bits_data_valid; // @[lsu.scala:911:37, :949:69] wire _clr_bsy_valid_0_T_9 = ~mem_tlb_miss_0; // @[lsu.scala:926:41, :943:29, :951:29] wire _clr_bsy_valid_0_T_10 = _clr_bsy_valid_0_T_8 & _clr_bsy_valid_0_T_9; // @[lsu.scala:949:69, :950:69, :951:29] wire _clr_bsy_valid_0_T_11 = ~mem_stq_incoming_e_0_bits_uop_is_amo; // @[lsu.scala:911:37, :944:29, :952:29] wire _clr_bsy_valid_0_T_12 = _clr_bsy_valid_0_T_10 & _clr_bsy_valid_0_T_11; // @[lsu.scala:950:69, :951:69, :952:29] wire _clr_bsy_valid_0_T_14 = \|_clr_bsy_valid_0_T_13; // @[util.scala:118:{51,59}] wire _clr_bsy_valid_0_T_15 = ~_clr_bsy_valid_0_T_14; // @[util.scala:118:59] wire _clr_bsy_valid_0_T_16 = _clr_bsy_valid_0_T_12 & _clr_bsy_valid_0_T_15; // @[lsu.scala:951:69, :952:69, :953:29] wire [7:0] _clr_bsy_brmask_0_T_2 = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:85:27] wire [7:0] _clr_bsy_brmask_0_T_3 = mem_stq_incoming_e_0_bits_uop_br_mask & _clr_bsy_brmask_0_T_2; // @[util.scala:85:{25,27}] wire _clr_bsy_valid_0_T_17 = mem_stq_incoming_e_0_valid & mem_stq_incoming_e_0_bits_addr_valid; // @[lsu.scala:911:37, :957:74] wire _clr_bsy_valid_0_T_18 = ~mem_stq_incoming_e_0_bits_addr_is_virtual; // @[lsu.scala:911:37, :959:29] wire _clr_bsy_valid_0_T_19 = _clr_bsy_valid_0_T_17 & _clr_bsy_valid_0_T_18; // @[lsu.scala:957:74, :958:74, :959:29] wire _clr_bsy_valid_0_T_20 = ~mem_stq_incoming_e_0_bits_uop_is_amo; // @[lsu.scala:911:37, :944:29, :960:29] wire _clr_bsy_valid_0_T_21 = _clr_bsy_valid_0_T_19 & _clr_bsy_valid_0_T_20; // @[lsu.scala:958:74, :959:74, :960:29] wire _clr_bsy_valid_0_T_23 = \|_clr_bsy_valid_0_T_22; // @[util.scala:118:{51,59}] wire _clr_bsy_valid_0_T_24 = ~_clr_bsy_valid_0_T_23; // @[util.scala:118:59] wire _clr_bsy_valid_0_T_25 = _clr_bsy_valid_0_T_21 & _clr_bsy_valid_0_T_24; // @[lsu.scala:959:74, :960:74, :961:29] wire [7:0] _clr_bsy_brmask_0_T_4 = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:85:27] wire [7:0] _clr_bsy_brmask_0_T_5 = mem_stq_incoming_e_0_bits_uop_br_mask & _clr_bsy_brmask_0_T_4; // @[util.scala:85:{25,27}] wire [7:0] _clr_bsy_brmask_0_T_6 = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:85:27] wire [7:0] _clr_bsy_brmask_0_T_7 = mem_incoming_uop_0_br_mask & _clr_bsy_brmask_0_T_6; // @[util.scala:85:{25,27}] wire _clr_bsy_valid_0_T_26 = mem_stq_retry_e_valid & mem_stq_retry_e_bits_data_valid; // @[lsu.scala:914:37, :969:63] wire _clr_bsy_valid_0_T_27 = ~mem_tlb_miss_0; // @[lsu.scala:926:41, :943:29, :971:29] wire _clr_bsy_valid_0_T_28 = _clr_bsy_valid_0_T_26 & _clr_bsy_valid_0_T_27; // @[lsu.scala:969:63, :970:63, :971:29] wire _clr_bsy_valid_0_T_29 = ~mem_stq_retry_e_bits_uop_is_amo; // @[lsu.scala:914:37, :972:29] wire _clr_bsy_valid_0_T_30 = _clr_bsy_valid_0_T_28 & _clr_bsy_valid_0_T_29; // @[lsu.scala:970:63, :971:63, :972:29] wire [7:0] _clr_bsy_valid_0_T_31 = io_core_brupdate_b1_mispredict_mask_0 & mem_stq_retry_e_bits_uop_br_mask; // @[util.scala:118:51] wire _clr_bsy_valid_0_T_32 = \|_clr_bsy_valid_0_T_31; // @[util.scala:118:{51,59}] wire _clr_bsy_valid_0_T_33 = ~_clr_bsy_valid_0_T_32; // @[util.scala:118:59] wire _clr_bsy_valid_0_T_34 = _clr_bsy_valid_0_T_30 & _clr_bsy_valid_0_T_33; // @[lsu.scala:971:63, :972:63, :973:29] wire [7:0] _clr_bsy_brmask_0_T_8 = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:85:27] wire [7:0] _clr_bsy_brmask_0_T_9 = mem_stq_retry_e_bits_uop_br_mask & _clr_bsy_brmask_0_T_8; // @[util.scala:85:{25,27}] wire [7:0] _io_core_clr_bsy_0_valid_T = io_core_brupdate_b1_mispredict_mask_0 & clr_bsy_brmask_0; // @[util.scala:118:51] wire _io_core_clr_bsy_0_valid_T_1 = \|_io_core_clr_bsy_0_valid_T; // @[util.scala:118:{51,59}] wire _io_core_clr_bsy_0_valid_T_2 = ~_io_core_clr_bsy_0_valid_T_1; // @[util.scala:118:59] wire _io_core_clr_bsy_0_valid_T_3 = clr_bsy_valid_0 & _io_core_clr_bsy_0_valid_T_2; // @[lsu.scala:931:32, :978:50, :979:32] wire _io_core_clr_bsy_0_valid_T_4 = ~io_core_exception_0; // @[lsu.scala:201:7, :670:22, :980:32] wire _io_core_clr_bsy_0_valid_T_5 = _io_core_clr_bsy_0_valid_T_3 & _io_core_clr_bsy_0_valid_T_4; // @[lsu.scala:978:50, :979:87, :980:32] reg io_core_clr_bsy_0_valid_REG; // @[lsu.scala:980:62] wire _io_core_clr_bsy_0_valid_T_6 = ~io_core_clr_bsy_0_valid_REG; // @[lsu.scala:980:{54,62}] wire _io_core_clr_bsy_0_valid_T_7 = _io_core_clr_bsy_0_valid_T_5 & _io_core_clr_bsy_0_valid_T_6; // @[lsu.scala:979:87, :980:{51,54}] reg io_core_clr_bsy_0_valid_REG_1; // @[lsu.scala:980:101] reg io_core_clr_bsy_0_valid_REG_2; // @[lsu.scala:980:93] wire _io_core_clr_bsy_0_valid_T_8 = ~io_core_clr_bsy_0_valid_REG_2; // @[lsu.scala:980:{85,93}] assign _io_core_clr_bsy_0_valid_T_9 = _io_core_clr_bsy_0_valid_T_7 & _io_core_clr_bsy_0_valid_T_8; // @[lsu.scala:980:{51,82,85}] assign io_core_clr_bsy_0_valid_0 = _io_core_clr_bsy_0_valid_T_9; // @[lsu.scala:201:7, :980:82] reg stdf_clr_bsy_valid; // @[lsu.scala:984:37] reg [4:0] stdf_clr_bsy_rob_idx; // @[lsu.scala:985:33] assign io_core_clr_bsy_1_bits_0 = stdf_clr_bsy_rob_idx; // @[lsu.scala:201:7, :985:33] reg [7:0] stdf_clr_bsy_brmask; // @[lsu.scala:986:33] wire _stdf_clr_bsy_valid_T = _GEN[mem_stdf_uop_stq_idx] & _GEN_83[mem_stdf_uop_stq_idx]; // @[lsu.scala:222:42, :923:37, :992:62] wire _stdf_clr_bsy_valid_T_1 = ~_GEN_85[mem_stdf_uop_stq_idx]; // @[lsu.scala:222:42, :923:37, :992:62, :994:29] wire _stdf_clr_bsy_valid_T_2 = _stdf_clr_bsy_valid_T & _stdf_clr_bsy_valid_T_1; // @[lsu.scala:992:62, :993:62, :994:29] wire _stdf_clr_bsy_valid_T_3 = ~_GEN_57[mem_stdf_uop_stq_idx]; // @[lsu.scala:222:42, :923:37, :992:62, :995:29] wire _stdf_clr_bsy_valid_T_4 = _stdf_clr_bsy_valid_T_2 & _stdf_clr_bsy_valid_T_3; // @[lsu.scala:993:62, :994:62, :995:29] wire [7:0] _stdf_clr_bsy_valid_T_5 = io_core_brupdate_b1_mispredict_mask_0 & mem_stdf_uop_br_mask; // @[util.scala:118:51] wire _stdf_clr_bsy_valid_T_6 = \|_stdf_clr_bsy_valid_T_5; // @[util.scala:118:{51,59}] wire _stdf_clr_bsy_valid_T_7 = ~_stdf_clr_bsy_valid_T_6; // @[util.scala:118:59] wire _stdf_clr_bsy_valid_T_8 = _stdf_clr_bsy_valid_T_4 & _stdf_clr_bsy_valid_T_7; // @[lsu.scala:994:62, :995:62, :996:29] wire [7:0] _stdf_clr_bsy_brmask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:85:27] wire [7:0] _stdf_clr_bsy_brmask_T_1 = mem_stdf_uop_br_mask & _stdf_clr_bsy_brmask_T; // @[util.scala:85:{25,27}] wire [7:0] _io_core_clr_bsy_1_valid_T = io_core_brupdate_b1_mispredict_mask_0 & stdf_clr_bsy_brmask; // @[util.scala:118:51] wire _io_core_clr_bsy_1_valid_T_1 = \|_io_core_clr_bsy_1_valid_T; // @[util.scala:118:{51,59}] wire _io_core_clr_bsy_1_valid_T_2 = ~_io_core_clr_bsy_1_valid_T_1; // @[util.scala:118:59] wire _io_core_clr_bsy_1_valid_T_3 = stdf_clr_bsy_valid & _io_core_clr_bsy_1_valid_T_2; // @[lsu.scala:984:37, :1003:57, :1004:37] wire _io_core_clr_bsy_1_valid_T_4 = ~io_core_exception_0; // @[lsu.scala:201:7, :670:22, :1005:37] wire _io_core_clr_bsy_1_valid_T_5 = _io_core_clr_bsy_1_valid_T_3 & _io_core_clr_bsy_1_valid_T_4; // @[lsu.scala:1003:57, :1004:94, :1005:37] reg io_core_clr_bsy_1_valid_REG; // @[lsu.scala:1005:67] wire _io_core_clr_bsy_1_valid_T_6 = ~io_core_clr_bsy_1_valid_REG; // @[lsu.scala:1005:{59,67}] wire _io_core_clr_bsy_1_valid_T_7 = _io_core_clr_bsy_1_valid_T_5 & _io_core_clr_bsy_1_valid_T_6; // @[lsu.scala:1004:94, :1005:{56,59}] reg io_core_clr_bsy_1_valid_REG_1; // @[lsu.scala:1005:106] reg io_core_clr_bsy_1_valid_REG_2; // @[lsu.scala:1005:98] wire _io_core_clr_bsy_1_valid_T_8 = ~io_core_clr_bsy_1_valid_REG_2; // @[lsu.scala:1005:{90,98}] assign _io_core_clr_bsy_1_valid_T_9 = _io_core_clr_bsy_1_valid_T_7 & _io_core_clr_bsy_1_valid_T_8; // @[lsu.scala:1005:{56,87,90}] assign io_core_clr_bsy_1_valid_0 = _io_core_clr_bsy_1_valid_T_9; // @[lsu.scala:201:7, :1005:87] wire _do_st_search_T_1 = _do_st_search_T \| fired_sta_retry_0; // @[lsu.scala:263:49, :1015:{60,85}] wire _do_st_search_T_2 = ~mem_tlb_miss_0; // @[lsu.scala:926:41, :943:29, :1015:111] wire _do_st_search_T_3 = _do_st_search_T_1 & _do_st_search_T_2; // @[lsu.scala:1015:{85,108,111}] wire do_st_search_0 = _do_st_search_T_3; // @[lsu.scala:263:49, :1015:108] wire _GEN_228 = fired_load_incoming_0 \| fired_load_retry_0; // @[lsu.scala:263:49, :1017:61] wire _do_ld_search_T; // @[lsu.scala:1017:61] assign _do_ld_search_T = _GEN_228; // @[lsu.scala:1017:61] wire _can_forward_T; // @[lsu.scala:1046:32] assign _can_forward_T = _GEN_228; // @[lsu.scala:1017:61, :1046:32] wire _do_ld_search_T_1 = ~mem_tlb_miss_0; // @[lsu.scala:926:41, :943:29, :1017:88] wire _do_ld_search_T_2 = _do_ld_search_T & _do_ld_search_T_1; // @[lsu.scala:1017:{61,85,88}] wire _do_ld_search_T_3 = _do_ld_search_T_2 \| fired_load_wakeup_0; // @[lsu.scala:263:49, :1017:{85,106}] wire do_ld_search_0 = _do_ld_search_T_3; // @[lsu.scala:263:49, :1017:106] wire _lcam_addr_T_1 = _lcam_addr_T \| fired_sta_retry_0; // @[lsu.scala:263:49, :1026:{61,86}] reg [31:0] lcam_addr_REG; // @[lsu.scala:1027:45] reg [31:0] lcam_addr_REG_1; // @[lsu.scala:1028:67] wire [39:0] _lcam_addr_T_2 = fired_release_0 ? {8'h0, lcam_addr_REG_1} : mem_paddr_0; // @[lsu.scala:901:37, :928:41, :1028:{41,67}] wire [39:0] _lcam_addr_T_3 = _lcam_addr_T_1 ? {8'h0, lcam_addr_REG} : _lcam_addr_T_2; // @[lsu.scala:1026:{37,86}, :1027:45, :1028:41] wire [39:0] lcam_addr_0 = _lcam_addr_T_3; // @[lsu.scala:263:49, :1026:37] wire [6:0] _lcam_uop_T_uopc = do_ld_search_0 ? mem_ldq_e_0_bits_uop_uopc : 7'h0; // @[lsu.scala:263:49, :1031:37] wire [31:0] _lcam_uop_T_inst = do_ld_search_0 ? mem_ldq_e_0_bits_uop_inst : 32'h0; // @[lsu.scala:263:49, :1031:37] wire [31:0] _lcam_uop_T_debug_inst = do_ld_search_0 ? mem_ldq_e_0_bits_uop_debug_inst : 32'h0; // @[lsu.scala:263:49, :1031:37] wire _lcam_uop_T_is_rvc = do_ld_search_0 & mem_ldq_e_0_bits_uop_is_rvc; // @[lsu.scala:263:49, :1031:37] wire [39:0] _lcam_uop_T_debug_pc = do_ld_search_0 ? mem_ldq_e_0_bits_uop_debug_pc : 40'h0; // @[lsu.scala:263:49, :1031:37] wire [2:0] _lcam_uop_T_iq_type = do_ld_search_0 ? mem_ldq_e_0_bits_uop_iq_type : 3'h0; // @[lsu.scala:263:49, :1031:37] wire [9:0] _lcam_uop_T_fu_code = do_ld_search_0 ? mem_ldq_e_0_bits_uop_fu_code : 10'h0; // @[lsu.scala:263:49, :1031:37] wire [3:0] _lcam_uop_T_ctrl_br_type = do_ld_search_0 ? mem_ldq_e_0_bits_uop_ctrl_br_type : 4'h0; // @[lsu.scala:263:49, :1031:37] wire [1:0] _lcam_uop_T_ctrl_op1_sel = do_ld_search_0 ? mem_ldq_e_0_bits_uop_ctrl_op1_sel : 2'h0; // @[lsu.scala:263:49, :1031:37] wire [2:0] _lcam_uop_T_ctrl_op2_sel = do_ld_search_0 ? mem_ldq_e_0_bits_uop_ctrl_op2_sel : 3'h0; // @[lsu.scala:263:49, :1031:37] wire [2:0] _lcam_uop_T_ctrl_imm_sel = do_ld_search_0 ? mem_ldq_e_0_bits_uop_ctrl_imm_sel : 3'h0; // @[lsu.scala:263:49, :1031:37] wire [4:0] _lcam_uop_T_ctrl_op_fcn = do_ld_search_0 ? mem_ldq_e_0_bits_uop_ctrl_op_fcn : 5'h0; // @[lsu.scala:263:49, :1031:37] wire _lcam_uop_T_ctrl_fcn_dw = do_ld_search_0 & mem_ldq_e_0_bits_uop_ctrl_fcn_dw; // @[lsu.scala:263:49, :1031:37] wire [2:0] _lcam_uop_T_ctrl_csr_cmd = do_ld_search_0 ? mem_ldq_e_0_bits_uop_ctrl_csr_cmd : 3'h0; // @[lsu.scala:263:49, :1031:37] wire _lcam_uop_T_ctrl_is_load = do_ld_search_0 & mem_ldq_e_0_bits_uop_ctrl_is_load; // @[lsu.scala:263:49, :1031:37] wire _lcam_uop_T_ctrl_is_sta = do_ld_search_0 & mem_ldq_e_0_bits_uop_ctrl_is_sta; // @[lsu.scala:263:49, :1031:37] wire _lcam_uop_T_ctrl_is_std = do_ld_search_0 & mem_ldq_e_0_bits_uop_ctrl_is_std; // @[lsu.scala:263:49, :1031:37] wire [1:0] _lcam_uop_T_iw_state = do_ld_search_0 ? mem_ldq_e_0_bits_uop_iw_state : 2'h0; // @[lsu.scala:263:49, :1031:37] wire _lcam_uop_T_iw_p1_poisoned = do_ld_search_0 & mem_ldq_e_0_bits_uop_iw_p1_poisoned; // @[lsu.scala:263:49, :1031:37] wire _lcam_uop_T_iw_p2_poisoned = do_ld_search_0 & mem_ldq_e_0_bits_uop_iw_p2_poisoned; // @[lsu.scala:263:49, :1031:37] wire _lcam_uop_T_is_br = do_ld_search_0 & mem_ldq_e_0_bits_uop_is_br; // @[lsu.scala:263:49, :1031:37] wire _lcam_uop_T_is_jalr = do_ld_search_0 & mem_ldq_e_0_bits_uop_is_jalr; // @[lsu.scala:263:49, :1031:37] wire _lcam_uop_T_is_jal = do_ld_search_0 & mem_ldq_e_0_bits_uop_is_jal; // @[lsu.scala:263:49, :1031:37] wire _lcam_uop_T_is_sfb = do_ld_search_0 & mem_ldq_e_0_bits_uop_is_sfb; // @[lsu.scala:263:49, :1031:37] wire [7:0] _lcam_uop_T_br_mask = do_ld_search_0 ? mem_ldq_e_0_bits_uop_br_mask : 8'h0; // @[lsu.scala:263:49, :1031:37] wire [2:0] _lcam_uop_T_br_tag = do_ld_search_0 ? mem_ldq_e_0_bits_uop_br_tag : 3'h0; // @[lsu.scala:263:49, :1031:37] wire [3:0] _lcam_uop_T_ftq_idx = do_ld_search_0 ? mem_ldq_e_0_bits_uop_ftq_idx : 4'h0; // @[lsu.scala:263:49, :1031:37] wire _lcam_uop_T_edge_inst = do_ld_search_0 & mem_ldq_e_0_bits_uop_edge_inst; // @[lsu.scala:263:49, :1031:37] wire [5:0] _lcam_uop_T_pc_lob = do_ld_search_0 ? mem_ldq_e_0_bits_uop_pc_lob : 6'h0; // @[lsu.scala:263:49, :1031:37] wire _lcam_uop_T_taken = do_ld_search_0 & mem_ldq_e_0_bits_uop_taken; // @[lsu.scala:263:49, :1031:37] wire [19:0] _lcam_uop_T_imm_packed = do_ld_search_0 ? mem_ldq_e_0_bits_uop_imm_packed : 20'h0; // @[lsu.scala:263:49, :1031:37] wire [11:0] _lcam_uop_T_csr_addr = do_ld_search_0 ? mem_ldq_e_0_bits_uop_csr_addr : 12'h0; // @[lsu.scala:263:49, :1031:37] wire [4:0] _lcam_uop_T_rob_idx = do_ld_search_0 ? mem_ldq_e_0_bits_uop_rob_idx : 5'h0; // @[lsu.scala:263:49, :1031:37] wire [2:0] _lcam_uop_T_ldq_idx = do_ld_search_0 ? mem_ldq_e_0_bits_uop_ldq_idx : 3'h0; // @[lsu.scala:263:49, :1031:37] wire [2:0] _lcam_uop_T_stq_idx = do_ld_search_0 ? mem_ldq_e_0_bits_uop_stq_idx : 3'h0; // @[lsu.scala:263:49, :1031:37] wire [1:0] _lcam_uop_T_rxq_idx = do_ld_search_0 ? mem_ldq_e_0_bits_uop_rxq_idx : 2'h0; // @[lsu.scala:263:49, :1031:37] wire [5:0] _lcam_uop_T_pdst = do_ld_search_0 ? mem_ldq_e_0_bits_uop_pdst : 6'h0; // @[lsu.scala:263:49, :1031:37] wire [5:0] _lcam_uop_T_prs1 = do_ld_search_0 ? mem_ldq_e_0_bits_uop_prs1 : 6'h0; // @[lsu.scala:263:49, :1031:37] wire [5:0] _lcam_uop_T_prs2 = do_ld_search_0 ? mem_ldq_e_0_bits_uop_prs2 : 6'h0; // @[lsu.scala:263:49, :1031:37] wire [5:0] _lcam_uop_T_prs3 = do_ld_search_0 ? mem_ldq_e_0_bits_uop_prs3 : 6'h0; // @[lsu.scala:263:49, :1031:37] wire [3:0] _lcam_uop_T_ppred = do_ld_search_0 ? mem_ldq_e_0_bits_uop_ppred : 4'h0; // @[lsu.scala:263:49, :1031:37] wire _lcam_uop_T_prs1_busy = do_ld_search_0 & mem_ldq_e_0_bits_uop_prs1_busy; // @[lsu.scala:263:49, :1031:37] wire _lcam_uop_T_prs2_busy = do_ld_search_0 & mem_ldq_e_0_bits_uop_prs2_busy; // @[lsu.scala:263:49, :1031:37] wire _lcam_uop_T_prs3_busy = do_ld_search_0 & mem_ldq_e_0_bits_uop_prs3_busy; // @[lsu.scala:263:49, :1031:37] wire _lcam_uop_T_ppred_busy = do_ld_search_0 & mem_ldq_e_0_bits_uop_ppred_busy; // @[lsu.scala:263:49, :1031:37] wire [5:0] _lcam_uop_T_stale_pdst = do_ld_search_0 ? mem_ldq_e_0_bits_uop_stale_pdst : 6'h0; // @[lsu.scala:263:49, :1031:37] wire _lcam_uop_T_exception = do_ld_search_0 & mem_ldq_e_0_bits_uop_exception; // @[lsu.scala:263:49, :1031:37] wire [63:0] _lcam_uop_T_exc_cause = do_ld_search_0 ? mem_ldq_e_0_bits_uop_exc_cause : 64'h0; // @[lsu.scala:263:49, :1031:37] wire _lcam_uop_T_bypassable = do_ld_search_0 & mem_ldq_e_0_bits_uop_bypassable; // @[lsu.scala:263:49, :1031:37] wire [4:0] _lcam_uop_T_mem_cmd = do_ld_search_0 ? mem_ldq_e_0_bits_uop_mem_cmd : 5'h0; // @[lsu.scala:263:49, :1031:37] wire [1:0] _lcam_uop_T_mem_size = do_ld_search_0 ? mem_ldq_e_0_bits_uop_mem_size : 2'h0; // @[lsu.scala:263:49, :1031:37] wire _lcam_uop_T_mem_signed = do_ld_search_0 & mem_ldq_e_0_bits_uop_mem_signed; // @[lsu.scala:263:49, :1031:37] wire _lcam_uop_T_is_fence = do_ld_search_0 & mem_ldq_e_0_bits_uop_is_fence; // @[lsu.scala:263:49, :1031:37] wire _lcam_uop_T_is_fencei = do_ld_search_0 & mem_ldq_e_0_bits_uop_is_fencei; // @[lsu.scala:263:49, :1031:37] wire _lcam_uop_T_is_amo = do_ld_search_0 & mem_ldq_e_0_bits_uop_is_amo; // @[lsu.scala:263:49, :1031:37] wire _lcam_uop_T_uses_ldq = do_ld_search_0 & mem_ldq_e_0_bits_uop_uses_ldq; // @[lsu.scala:263:49, :1031:37] wire _lcam_uop_T_uses_stq = do_ld_search_0 & mem_ldq_e_0_bits_uop_uses_stq; // @[lsu.scala:263:49, :1031:37] wire _lcam_uop_T_is_sys_pc2epc = do_ld_search_0 & mem_ldq_e_0_bits_uop_is_sys_pc2epc; // @[lsu.scala:263:49, :1031:37] wire _lcam_uop_T_is_unique = do_ld_search_0 & mem_ldq_e_0_bits_uop_is_unique; // @[lsu.scala:263:49, :1031:37] wire _lcam_uop_T_flush_on_commit = do_ld_search_0 & mem_ldq_e_0_bits_uop_flush_on_commit; // @[lsu.scala:263:49, :1031:37] wire _lcam_uop_T_ldst_is_rs1 = do_ld_search_0 & mem_ldq_e_0_bits_uop_ldst_is_rs1; // @[lsu.scala:263:49, :1031:37] wire [5:0] _lcam_uop_T_ldst = do_ld_search_0 ? mem_ldq_e_0_bits_uop_ldst : 6'h0; // @[lsu.scala:263:49, :1031:37] wire [5:0] _lcam_uop_T_lrs1 = do_ld_search_0 ? mem_ldq_e_0_bits_uop_lrs1 : 6'h0; // @[lsu.scala:263:49, :1031:37] wire [5:0] _lcam_uop_T_lrs2 = do_ld_search_0 ? mem_ldq_e_0_bits_uop_lrs2 : 6'h0; // @[lsu.scala:263:49, :1031:37] wire [5:0] _lcam_uop_T_lrs3 = do_ld_search_0 ? mem_ldq_e_0_bits_uop_lrs3 : 6'h0; // @[lsu.scala:263:49, :1031:37] wire _lcam_uop_T_ldst_val = do_ld_search_0 & mem_ldq_e_0_bits_uop_ldst_val; // @[lsu.scala:263:49, :1031:37] wire [1:0] _lcam_uop_T_dst_rtype = do_ld_search_0 ? mem_ldq_e_0_bits_uop_dst_rtype : 2'h2; // @[lsu.scala:263:49, :1031:37] wire [1:0] _lcam_uop_T_lrs1_rtype = do_ld_search_0 ? mem_ldq_e_0_bits_uop_lrs1_rtype : 2'h0; // @[lsu.scala:263:49, :1031:37] wire [1:0] _lcam_uop_T_lrs2_rtype = do_ld_search_0 ? mem_ldq_e_0_bits_uop_lrs2_rtype : 2'h0; // @[lsu.scala:263:49, :1031:37] wire _lcam_uop_T_frs3_en = do_ld_search_0 & mem_ldq_e_0_bits_uop_frs3_en; // @[lsu.scala:263:49, :1031:37] wire _lcam_uop_T_fp_val = do_ld_search_0 & mem_ldq_e_0_bits_uop_fp_val; // @[lsu.scala:263:49, :1031:37] wire _lcam_uop_T_fp_single = do_ld_search_0 & mem_ldq_e_0_bits_uop_fp_single; // @[lsu.scala:263:49, :1031:37] wire _lcam_uop_T_xcpt_pf_if = do_ld_search_0 & mem_ldq_e_0_bits_uop_xcpt_pf_if; // @[lsu.scala:263:49, :1031:37] wire _lcam_uop_T_xcpt_ae_if = do_ld_search_0 & mem_ldq_e_0_bits_uop_xcpt_ae_if; // @[lsu.scala:263:49, :1031:37] wire _lcam_uop_T_xcpt_ma_if = do_ld_search_0 & mem_ldq_e_0_bits_uop_xcpt_ma_if; // @[lsu.scala:263:49, :1031:37] wire _lcam_uop_T_bp_debug_if = do_ld_search_0 & mem_ldq_e_0_bits_uop_bp_debug_if; // @[lsu.scala:263:49, :1031:37] wire _lcam_uop_T_bp_xcpt_if = do_ld_search_0 & mem_ldq_e_0_bits_uop_bp_xcpt_if; // @[lsu.scala:263:49, :1031:37] wire [1:0] _lcam_uop_T_debug_fsrc = do_ld_search_0 ? mem_ldq_e_0_bits_uop_debug_fsrc : 2'h0; // @[lsu.scala:263:49, :1031:37] wire [1:0] _lcam_uop_T_debug_tsrc = do_ld_search_0 ? mem_ldq_e_0_bits_uop_debug_tsrc : 2'h0; // @[lsu.scala:263:49, :1031:37] wire [6:0] _lcam_uop_T_1_uopc = do_st_search_0 ? mem_stq_e_0_bits_uop_uopc : _lcam_uop_T_uopc; // @[lsu.scala:263:49, :1030:37, :1031:37] wire [31:0] _lcam_uop_T_1_inst = do_st_search_0 ? mem_stq_e_0_bits_uop_inst : _lcam_uop_T_inst; // @[lsu.scala:263:49, :1030:37, :1031:37] wire [31:0] _lcam_uop_T_1_debug_inst = do_st_search_0 ? mem_stq_e_0_bits_uop_debug_inst : _lcam_uop_T_debug_inst; // @[lsu.scala:263:49, :1030:37, :1031:37] wire _lcam_uop_T_1_is_rvc = do_st_search_0 ? mem_stq_e_0_bits_uop_is_rvc : _lcam_uop_T_is_rvc; // @[lsu.scala:263:49, :1030:37, :1031:37] wire [39:0] _lcam_uop_T_1_debug_pc = do_st_search_0 ? mem_stq_e_0_bits_uop_debug_pc : _lcam_uop_T_debug_pc; // @[lsu.scala:263:49, :1030:37, :1031:37] wire [2:0] _lcam_uop_T_1_iq_type = do_st_search_0 ? mem_stq_e_0_bits_uop_iq_type : _lcam_uop_T_iq_type; // @[lsu.scala:263:49, :1030:37, :1031:37] wire [9:0] _lcam_uop_T_1_fu_code = do_st_search_0 ? mem_stq_e_0_bits_uop_fu_code : _lcam_uop_T_fu_code; // @[lsu.scala:263:49, :1030:37, :1031:37] wire [3:0] _lcam_uop_T_1_ctrl_br_type = do_st_search_0 ? mem_stq_e_0_bits_uop_ctrl_br_type : _lcam_uop_T_ctrl_br_type; // @[lsu.scala:263:49, :1030:37, :1031:37] wire [1:0] _lcam_uop_T_1_ctrl_op1_sel = do_st_search_0 ? mem_stq_e_0_bits_uop_ctrl_op1_sel : _lcam_uop_T_ctrl_op1_sel; // @[lsu.scala:263:49, :1030:37, :1031:37] wire [2:0] _lcam_uop_T_1_ctrl_op2_sel = do_st_search_0 ? mem_stq_e_0_bits_uop_ctrl_op2_sel : _lcam_uop_T_ctrl_op2_sel; // @[lsu.scala:263:49, :1030:37, :1031:37] wire [2:0] _lcam_uop_T_1_ctrl_imm_sel = do_st_search_0 ? mem_stq_e_0_bits_uop_ctrl_imm_sel : _lcam_uop_T_ctrl_imm_sel; // @[lsu.scala:263:49, :1030:37, :1031:37] wire [4:0] _lcam_uop_T_1_ctrl_op_fcn = do_st_search_0 ? mem_stq_e_0_bits_uop_ctrl_op_fcn : _lcam_uop_T_ctrl_op_fcn; // @[lsu.scala:263:49, :1030:37, :1031:37] wire _lcam_uop_T_1_ctrl_fcn_dw = do_st_search_0 ? mem_stq_e_0_bits_uop_ctrl_fcn_dw : _lcam_uop_T_ctrl_fcn_dw; // @[lsu.scala:263:49, :1030:37, :1031:37] wire [2:0] _lcam_uop_T_1_ctrl_csr_cmd = do_st_search_0 ? mem_stq_e_0_bits_uop_ctrl_csr_cmd : _lcam_uop_T_ctrl_csr_cmd; // @[lsu.scala:263:49, :1030:37, :1031:37] wire _lcam_uop_T_1_ctrl_is_load = do_st_search_0 ? mem_stq_e_0_bits_uop_ctrl_is_load : _lcam_uop_T_ctrl_is_load; // @[lsu.scala:263:49, :1030:37, :1031:37] wire _lcam_uop_T_1_ctrl_is_sta = do_st_search_0 ? mem_stq_e_0_bits_uop_ctrl_is_sta : _lcam_uop_T_ctrl_is_sta; // @[lsu.scala:263:49, :1030:37, :1031:37] wire _lcam_uop_T_1_ctrl_is_std = do_st_search_0 ? mem_stq_e_0_bits_uop_ctrl_is_std : _lcam_uop_T_ctrl_is_std; // @[lsu.scala:263:49, :1030:37, :1031:37] wire [1:0] _lcam_uop_T_1_iw_state = do_st_search_0 ? mem_stq_e_0_bits_uop_iw_state : _lcam_uop_T_iw_state; // @[lsu.scala:263:49, :1030:37, :1031:37] wire _lcam_uop_T_1_iw_p1_poisoned = do_st_search_0 ? mem_stq_e_0_bits_uop_iw_p1_poisoned : _lcam_uop_T_iw_p1_poisoned; // @[lsu.scala:263:49, :1030:37, :1031:37] wire _lcam_uop_T_1_iw_p2_poisoned = do_st_search_0 ? mem_stq_e_0_bits_uop_iw_p2_poisoned : _lcam_uop_T_iw_p2_poisoned; // @[lsu.scala:263:49, :1030:37, :1031:37] wire _lcam_uop_T_1_is_br = do_st_search_0 ? mem_stq_e_0_bits_uop_is_br : _lcam_uop_T_is_br; // @[lsu.scala:263:49, :1030:37, :1031:37] wire _lcam_uop_T_1_is_jalr = do_st_search_0 ? mem_stq_e_0_bits_uop_is_jalr : _lcam_uop_T_is_jalr; // @[lsu.scala:263:49, :1030:37, :1031:37] wire _lcam_uop_T_1_is_jal = do_st_search_0 ? mem_stq_e_0_bits_uop_is_jal : _lcam_uop_T_is_jal; // @[lsu.scala:263:49, :1030:37, :1031:37] wire _lcam_uop_T_1_is_sfb = do_st_search_0 ? mem_stq_e_0_bits_uop_is_sfb : _lcam_uop_T_is_sfb; // @[lsu.scala:263:49, :1030:37, :1031:37] wire [7:0] _lcam_uop_T_1_br_mask = do_st_search_0 ? mem_stq_e_0_bits_uop_br_mask : _lcam_uop_T_br_mask; // @[lsu.scala:263:49, :1030:37, :1031:37] wire [2:0] _lcam_uop_T_1_br_tag = do_st_search_0 ? mem_stq_e_0_bits_uop_br_tag : _lcam_uop_T_br_tag; // @[lsu.scala:263:49, :1030:37, :1031:37] wire [3:0] _lcam_uop_T_1_ftq_idx = do_st_search_0 ? mem_stq_e_0_bits_uop_ftq_idx : _lcam_uop_T_ftq_idx; // @[lsu.scala:263:49, :1030:37, :1031:37] wire _lcam_uop_T_1_edge_inst = do_st_search_0 ? mem_stq_e_0_bits_uop_edge_inst : _lcam_uop_T_edge_inst; // @[lsu.scala:263:49, :1030:37, :1031:37] wire [5:0] _lcam_uop_T_1_pc_lob = do_st_search_0 ? mem_stq_e_0_bits_uop_pc_lob : _lcam_uop_T_pc_lob; // @[lsu.scala:263:49, :1030:37, :1031:37] wire _lcam_uop_T_1_taken = do_st_search_0 ? mem_stq_e_0_bits_uop_taken : _lcam_uop_T_taken; // @[lsu.scala:263:49, :1030:37, :1031:37] wire [19:0] _lcam_uop_T_1_imm_packed = do_st_search_0 ? mem_stq_e_0_bits_uop_imm_packed : _lcam_uop_T_imm_packed; // @[lsu.scala:263:49, :1030:37, :1031:37] wire [11:0] _lcam_uop_T_1_csr_addr = do_st_search_0 ? mem_stq_e_0_bits_uop_csr_addr : _lcam_uop_T_csr_addr; // @[lsu.scala:263:49, :1030:37, :1031:37] wire [4:0] _lcam_uop_T_1_rob_idx = do_st_search_0 ? mem_stq_e_0_bits_uop_rob_idx : _lcam_uop_T_rob_idx; // @[lsu.scala:263:49, :1030:37, :1031:37] wire [2:0] _lcam_uop_T_1_ldq_idx = do_st_search_0 ? mem_stq_e_0_bits_uop_ldq_idx : _lcam_uop_T_ldq_idx; // @[lsu.scala:263:49, :1030:37, :1031:37] wire [2:0] _lcam_uop_T_1_stq_idx = do_st_search_0 ? mem_stq_e_0_bits_uop_stq_idx : _lcam_uop_T_stq_idx; // @[lsu.scala:263:49, :1030:37, :1031:37] wire [1:0] _lcam_uop_T_1_rxq_idx = do_st_search_0 ? mem_stq_e_0_bits_uop_rxq_idx : _lcam_uop_T_rxq_idx; // @[lsu.scala:263:49, :1030:37, :1031:37] wire [5:0] _lcam_uop_T_1_pdst = do_st_search_0 ? mem_stq_e_0_bits_uop_pdst : _lcam_uop_T_pdst; // @[lsu.scala:263:49, :1030:37, :1031:37] wire [5:0] _lcam_uop_T_1_prs1 = do_st_search_0 ? mem_stq_e_0_bits_uop_prs1 : _lcam_uop_T_prs1; // @[lsu.scala:263:49, :1030:37, :1031:37] wire [5:0] _lcam_uop_T_1_prs2 = do_st_search_0 ? mem_stq_e_0_bits_uop_prs2 : _lcam_uop_T_prs2; // @[lsu.scala:263:49, :1030:37, :1031:37] wire [5:0] _lcam_uop_T_1_prs3 = do_st_search_0 ? mem_stq_e_0_bits_uop_prs3 : _lcam_uop_T_prs3; // @[lsu.scala:263:49, :1030:37, :1031:37] wire [3:0] _lcam_uop_T_1_ppred = do_st_search_0 ? mem_stq_e_0_bits_uop_ppred : _lcam_uop_T_ppred; // @[lsu.scala:263:49, :1030:37, :1031:37] wire _lcam_uop_T_1_prs1_busy = do_st_search_0 ? mem_stq_e_0_bits_uop_prs1_busy : _lcam_uop_T_prs1_busy; // @[lsu.scala:263:49, :1030:37, :1031:37] wire _lcam_uop_T_1_prs2_busy = do_st_search_0 ? mem_stq_e_0_bits_uop_prs2_busy : _lcam_uop_T_prs2_busy; // @[lsu.scala:263:49, :1030:37, :1031:37] wire _lcam_uop_T_1_prs3_busy = do_st_search_0 ? mem_stq_e_0_bits_uop_prs3_busy : _lcam_uop_T_prs3_busy; // @[lsu.scala:263:49, :1030:37, :1031:37] wire _lcam_uop_T_1_ppred_busy = do_st_search_0 ? mem_stq_e_0_bits_uop_ppred_busy : _lcam_uop_T_ppred_busy; // @[lsu.scala:263:49, :1030:37, :1031:37] wire [5:0] _lcam_uop_T_1_stale_pdst = do_st_search_0 ? mem_stq_e_0_bits_uop_stale_pdst : _lcam_uop_T_stale_pdst; // @[lsu.scala:263:49, :1030:37, :1031:37] wire _lcam_uop_T_1_exception = do_st_search_0 ? mem_stq_e_0_bits_uop_exception : _lcam_uop_T_exception; // @[lsu.scala:263:49, :1030:37, :1031:37] wire [63:0] _lcam_uop_T_1_exc_cause = do_st_search_0 ? mem_stq_e_0_bits_uop_exc_cause : _lcam_uop_T_exc_cause; // @[lsu.scala:263:49, :1030:37, :1031:37] wire _lcam_uop_T_1_bypassable = do_st_search_0 ? mem_stq_e_0_bits_uop_bypassable : _lcam_uop_T_bypassable; // @[lsu.scala:263:49, :1030:37, :1031:37] wire [4:0] _lcam_uop_T_1_mem_cmd = do_st_search_0 ? mem_stq_e_0_bits_uop_mem_cmd : _lcam_uop_T_mem_cmd; // @[lsu.scala:263:49, :1030:37, :1031:37] wire [1:0] _lcam_uop_T_1_mem_size = do_st_search_0 ? mem_stq_e_0_bits_uop_mem_size : _lcam_uop_T_mem_size; // @[lsu.scala:263:49, :1030:37, :1031:37] wire _lcam_uop_T_1_mem_signed = do_st_search_0 ? mem_stq_e_0_bits_uop_mem_signed : _lcam_uop_T_mem_signed; // @[lsu.scala:263:49, :1030:37, :1031:37] wire _lcam_uop_T_1_is_fence = do_st_search_0 ? mem_stq_e_0_bits_uop_is_fence : _lcam_uop_T_is_fence; // @[lsu.scala:263:49, :1030:37, :1031:37] wire _lcam_uop_T_1_is_fencei = do_st_search_0 ? mem_stq_e_0_bits_uop_is_fencei : _lcam_uop_T_is_fencei; // @[lsu.scala:263:49, :1030:37, :1031:37] wire _lcam_uop_T_1_is_amo = do_st_search_0 ? mem_stq_e_0_bits_uop_is_amo : _lcam_uop_T_is_amo; // @[lsu.scala:263:49, :1030:37, :1031:37] wire _lcam_uop_T_1_uses_ldq = do_st_search_0 ? mem_stq_e_0_bits_uop_uses_ldq : _lcam_uop_T_uses_ldq; // @[lsu.scala:263:49, :1030:37, :1031:37] wire _lcam_uop_T_1_uses_stq = do_st_search_0 ? mem_stq_e_0_bits_uop_uses_stq : _lcam_uop_T_uses_stq; // @[lsu.scala:263:49, :1030:37, :1031:37] wire _lcam_uop_T_1_is_sys_pc2epc = do_st_search_0 ? mem_stq_e_0_bits_uop_is_sys_pc2epc : _lcam_uop_T_is_sys_pc2epc; // @[lsu.scala:263:49, :1030:37, :1031:37] wire _lcam_uop_T_1_is_unique = do_st_search_0 ? mem_stq_e_0_bits_uop_is_unique : _lcam_uop_T_is_unique; // @[lsu.scala:263:49, :1030:37, :1031:37] wire _lcam_uop_T_1_flush_on_commit = do_st_search_0 ? mem_stq_e_0_bits_uop_flush_on_commit : _lcam_uop_T_flush_on_commit; // @[lsu.scala:263:49, :1030:37, :1031:37] wire _lcam_uop_T_1_ldst_is_rs1 = do_st_search_0 ? mem_stq_e_0_bits_uop_ldst_is_rs1 : _lcam_uop_T_ldst_is_rs1; // @[lsu.scala:263:49, :1030:37, :1031:37] wire [5:0] _lcam_uop_T_1_ldst = do_st_search_0 ? mem_stq_e_0_bits_uop_ldst : _lcam_uop_T_ldst; // @[lsu.scala:263:49, :1030:37, :1031:37] wire [5:0] _lcam_uop_T_1_lrs1 = do_st_search_0 ? mem_stq_e_0_bits_uop_lrs1 : _lcam_uop_T_lrs1; // @[lsu.scala:263:49, :1030:37, :1031:37] wire [5:0] _lcam_uop_T_1_lrs2 = do_st_search_0 ? mem_stq_e_0_bits_uop_lrs2 : _lcam_uop_T_lrs2; // @[lsu.scala:263:49, :1030:37, :1031:37] wire [5:0] _lcam_uop_T_1_lrs3 = do_st_search_0 ? mem_stq_e_0_bits_uop_lrs3 : _lcam_uop_T_lrs3; // @[lsu.scala:263:49, :1030:37, :1031:37] wire _lcam_uop_T_1_ldst_val = do_st_search_0 ? mem_stq_e_0_bits_uop_ldst_val : _lcam_uop_T_ldst_val; // @[lsu.scala:263:49, :1030:37, :1031:37] wire [1:0] _lcam_uop_T_1_dst_rtype = do_st_search_0 ? mem_stq_e_0_bits_uop_dst_rtype : _lcam_uop_T_dst_rtype; // @[lsu.scala:263:49, :1030:37, :1031:37] wire [1:0] _lcam_uop_T_1_lrs1_rtype = do_st_search_0 ? mem_stq_e_0_bits_uop_lrs1_rtype : _lcam_uop_T_lrs1_rtype; // @[lsu.scala:263:49, :1030:37, :1031:37] wire [1:0] _lcam_uop_T_1_lrs2_rtype = do_st_search_0 ? mem_stq_e_0_bits_uop_lrs2_rtype : _lcam_uop_T_lrs2_rtype; // @[lsu.scala:263:49, :1030:37, :1031:37] wire _lcam_uop_T_1_frs3_en = do_st_search_0 ? mem_stq_e_0_bits_uop_frs3_en : _lcam_uop_T_frs3_en; // @[lsu.scala:263:49, :1030:37, :1031:37] wire _lcam_uop_T_1_fp_val = do_st_search_0 ? mem_stq_e_0_bits_uop_fp_val : _lcam_uop_T_fp_val; // @[lsu.scala:263:49, :1030:37, :1031:37] wire _lcam_uop_T_1_fp_single = do_st_search_0 ? mem_stq_e_0_bits_uop_fp_single : _lcam_uop_T_fp_single; // @[lsu.scala:263:49, :1030:37, :1031:37] wire _lcam_uop_T_1_xcpt_pf_if = do_st_search_0 ? mem_stq_e_0_bits_uop_xcpt_pf_if : _lcam_uop_T_xcpt_pf_if; // @[lsu.scala:263:49, :1030:37, :1031:37] wire _lcam_uop_T_1_xcpt_ae_if = do_st_search_0 ? mem_stq_e_0_bits_uop_xcpt_ae_if : _lcam_uop_T_xcpt_ae_if; // @[lsu.scala:263:49, :1030:37, :1031:37] wire _lcam_uop_T_1_xcpt_ma_if = do_st_search_0 ? mem_stq_e_0_bits_uop_xcpt_ma_if : _lcam_uop_T_xcpt_ma_if; // @[lsu.scala:263:49, :1030:37, :1031:37] wire _lcam_uop_T_1_bp_debug_if = do_st_search_0 ? mem_stq_e_0_bits_uop_bp_debug_if : _lcam_uop_T_bp_debug_if; // @[lsu.scala:263:49, :1030:37, :1031:37] wire _lcam_uop_T_1_bp_xcpt_if = do_st_search_0 ? mem_stq_e_0_bits_uop_bp_xcpt_if : _lcam_uop_T_bp_xcpt_if; // @[lsu.scala:263:49, :1030:37, :1031:37] wire [1:0] _lcam_uop_T_1_debug_fsrc = do_st_search_0 ? mem_stq_e_0_bits_uop_debug_fsrc : _lcam_uop_T_debug_fsrc; // @[lsu.scala:263:49, :1030:37, :1031:37] wire [1:0] _lcam_uop_T_1_debug_tsrc = do_st_search_0 ? mem_stq_e_0_bits_uop_debug_tsrc : _lcam_uop_T_debug_tsrc; // @[lsu.scala:263:49, :1030:37, :1031:37] wire [6:0] lcam_uop_0_uopc = _lcam_uop_T_1_uopc; // @[lsu.scala:263:49, :1030:37] wire [31:0] lcam_uop_0_inst = _lcam_uop_T_1_inst; // @[lsu.scala:263:49, :1030:37] wire [31:0] lcam_uop_0_debug_inst = _lcam_uop_T_1_debug_inst; // @[lsu.scala:263:49, :1030:37] wire lcam_uop_0_is_rvc = _lcam_uop_T_1_is_rvc; // @[lsu.scala:263:49, :1030:37] wire [39:0] lcam_uop_0_debug_pc = _lcam_uop_T_1_debug_pc; // @[lsu.scala:263:49, :1030:37] wire [2:0] lcam_uop_0_iq_type = _lcam_uop_T_1_iq_type; // @[lsu.scala:263:49, :1030:37] wire [9:0] lcam_uop_0_fu_code = _lcam_uop_T_1_fu_code; // @[lsu.scala:263:49, :1030:37] wire [3:0] lcam_uop_0_ctrl_br_type = _lcam_uop_T_1_ctrl_br_type; // @[lsu.scala:263:49, :1030:37] wire [1:0] lcam_uop_0_ctrl_op1_sel = _lcam_uop_T_1_ctrl_op1_sel; // @[lsu.scala:263:49, :1030:37] wire [2:0] lcam_uop_0_ctrl_op2_sel = _lcam_uop_T_1_ctrl_op2_sel; // @[lsu.scala:263:49, :1030:37] wire [2:0] lcam_uop_0_ctrl_imm_sel = _lcam_uop_T_1_ctrl_imm_sel; // @[lsu.scala:263:49, :1030:37] wire [4:0] lcam_uop_0_ctrl_op_fcn = _lcam_uop_T_1_ctrl_op_fcn; // @[lsu.scala:263:49, :1030:37] wire lcam_uop_0_ctrl_fcn_dw = _lcam_uop_T_1_ctrl_fcn_dw; // @[lsu.scala:263:49, :1030:37] wire [2:0] lcam_uop_0_ctrl_csr_cmd = _lcam_uop_T_1_ctrl_csr_cmd; // @[lsu.scala:263:49, :1030:37] wire lcam_uop_0_ctrl_is_load = _lcam_uop_T_1_ctrl_is_load; // @[lsu.scala:263:49, :1030:37] wire lcam_uop_0_ctrl_is_sta = _lcam_uop_T_1_ctrl_is_sta; // @[lsu.scala:263:49, :1030:37] wire lcam_uop_0_ctrl_is_std = _lcam_uop_T_1_ctrl_is_std; // @[lsu.scala:263:49, :1030:37] wire [1:0] lcam_uop_0_iw_state = _lcam_uop_T_1_iw_state; // @[lsu.scala:263:49, :1030:37] wire lcam_uop_0_iw_p1_poisoned = _lcam_uop_T_1_iw_p1_poisoned; // @[lsu.scala:263:49, :1030:37] wire lcam_uop_0_iw_p2_poisoned = _lcam_uop_T_1_iw_p2_poisoned; // @[lsu.scala:263:49, :1030:37] wire lcam_uop_0_is_br = _lcam_uop_T_1_is_br; // @[lsu.scala:263:49, :1030:37] wire lcam_uop_0_is_jalr = _lcam_uop_T_1_is_jalr; // @[lsu.scala:263:49, :1030:37] wire lcam_uop_0_is_jal = _lcam_uop_T_1_is_jal; // @[lsu.scala:263:49, :1030:37] wire lcam_uop_0_is_sfb = _lcam_uop_T_1_is_sfb; // @[lsu.scala:263:49, :1030:37] wire [7:0] lcam_uop_0_br_mask = _lcam_uop_T_1_br_mask; // @[lsu.scala:263:49, :1030:37] wire [2:0] lcam_uop_0_br_tag = _lcam_uop_T_1_br_tag; // @[lsu.scala:263:49, :1030:37] wire [3:0] lcam_uop_0_ftq_idx = _lcam_uop_T_1_ftq_idx; // @[lsu.scala:263:49, :1030:37] wire lcam_uop_0_edge_inst = _lcam_uop_T_1_edge_inst; // @[lsu.scala:263:49, :1030:37] wire [5:0] lcam_uop_0_pc_lob = _lcam_uop_T_1_pc_lob; // @[lsu.scala:263:49, :1030:37] wire lcam_uop_0_taken = _lcam_uop_T_1_taken; // @[lsu.scala:263:49, :1030:37] wire [19:0] lcam_uop_0_imm_packed = _lcam_uop_T_1_imm_packed; // @[lsu.scala:263:49, :1030:37] wire [11:0] lcam_uop_0_csr_addr = _lcam_uop_T_1_csr_addr; // @[lsu.scala:263:49, :1030:37] wire [4:0] lcam_uop_0_rob_idx = _lcam_uop_T_1_rob_idx; // @[lsu.scala:263:49, :1030:37] wire [2:0] lcam_uop_0_ldq_idx = _lcam_uop_T_1_ldq_idx; // @[lsu.scala:263:49, :1030:37] wire [2:0] lcam_uop_0_stq_idx = _lcam_uop_T_1_stq_idx; // @[lsu.scala:263:49, :1030:37] wire [1:0] lcam_uop_0_rxq_idx = _lcam_uop_T_1_rxq_idx; // @[lsu.scala:263:49, :1030:37] wire [5:0] lcam_uop_0_pdst = _lcam_uop_T_1_pdst; // @[lsu.scala:263:49, :1030:37] wire [5:0] lcam_uop_0_prs1 = _lcam_uop_T_1_prs1; // @[lsu.scala:263:49, :1030:37] wire [5:0] lcam_uop_0_prs2 = _lcam_uop_T_1_prs2; // @[lsu.scala:263:49, :1030:37] wire [5:0] lcam_uop_0_prs3 = _lcam_uop_T_1_prs3; // @[lsu.scala:263:49, :1030:37] wire [3:0] lcam_uop_0_ppred = _lcam_uop_T_1_ppred; // @[lsu.scala:263:49, :1030:37] wire lcam_uop_0_prs1_busy = _lcam_uop_T_1_prs1_busy; // @[lsu.scala:263:49, :1030:37] wire lcam_uop_0_prs2_busy = _lcam_uop_T_1_prs2_busy; // @[lsu.scala:263:49, :1030:37] wire lcam_uop_0_prs3_busy = _lcam_uop_T_1_prs3_busy; // @[lsu.scala:263:49, :1030:37] wire lcam_uop_0_ppred_busy = _lcam_uop_T_1_ppred_busy; // @[lsu.scala:263:49, :1030:37] wire [5:0] lcam_uop_0_stale_pdst = _lcam_uop_T_1_stale_pdst; // @[lsu.scala:263:49, :1030:37] wire lcam_uop_0_exception = _lcam_uop_T_1_exception; // @[lsu.scala:263:49, :1030:37] wire [63:0] lcam_uop_0_exc_cause = _lcam_uop_T_1_exc_cause; // @[lsu.scala:263:49, :1030:37] wire lcam_uop_0_bypassable = _lcam_uop_T_1_bypassable; // @[lsu.scala:263:49, :1030:37] wire [4:0] lcam_uop_0_mem_cmd = _lcam_uop_T_1_mem_cmd; // @[lsu.scala:263:49, :1030:37] wire [1:0] lcam_uop_0_mem_size = _lcam_uop_T_1_mem_size; // @[lsu.scala:263:49, :1030:37] wire lcam_uop_0_mem_signed = _lcam_uop_T_1_mem_signed; // @[lsu.scala:263:49, :1030:37] wire lcam_uop_0_is_fence = _lcam_uop_T_1_is_fence; // @[lsu.scala:263:49, :1030:37] wire lcam_uop_0_is_fencei = _lcam_uop_T_1_is_fencei; // @[lsu.scala:263:49, :1030:37] wire lcam_uop_0_is_amo = _lcam_uop_T_1_is_amo; // @[lsu.scala:263:49, :1030:37] wire lcam_uop_0_uses_ldq = _lcam_uop_T_1_uses_ldq; // @[lsu.scala:263:49, :1030:37] wire lcam_uop_0_uses_stq = _lcam_uop_T_1_uses_stq; // @[lsu.scala:263:49, :1030:37] wire lcam_uop_0_is_sys_pc2epc = _lcam_uop_T_1_is_sys_pc2epc; // @[lsu.scala:263:49, :1030:37] wire lcam_uop_0_is_unique = _lcam_uop_T_1_is_unique; // @[lsu.scala:263:49, :1030:37] wire lcam_uop_0_flush_on_commit = _lcam_uop_T_1_flush_on_commit; // @[lsu.scala:263:49, :1030:37] wire lcam_uop_0_ldst_is_rs1 = _lcam_uop_T_1_ldst_is_rs1; // @[lsu.scala:263:49, :1030:37] wire [5:0] lcam_uop_0_ldst = _lcam_uop_T_1_ldst; // @[lsu.scala:263:49, :1030:37] wire [5:0] lcam_uop_0_lrs1 = _lcam_uop_T_1_lrs1; // @[lsu.scala:263:49, :1030:37] wire [5:0] lcam_uop_0_lrs2 = _lcam_uop_T_1_lrs2; // @[lsu.scala:263:49, :1030:37] wire [5:0] lcam_uop_0_lrs3 = _lcam_uop_T_1_lrs3; // @[lsu.scala:263:49, :1030:37] wire lcam_uop_0_ldst_val = _lcam_uop_T_1_ldst_val; // @[lsu.scala:263:49, :1030:37] wire [1:0] lcam_uop_0_dst_rtype = _lcam_uop_T_1_dst_rtype; // @[lsu.scala:263:49, :1030:37] wire [1:0] lcam_uop_0_lrs1_rtype = _lcam_uop_T_1_lrs1_rtype; // @[lsu.scala:263:49, :1030:37] wire [1:0] lcam_uop_0_lrs2_rtype = _lcam_uop_T_1_lrs2_rtype; // @[lsu.scala:263:49, :1030:37] wire lcam_uop_0_frs3_en = _lcam_uop_T_1_frs3_en; // @[lsu.scala:263:49, :1030:37] wire lcam_uop_0_fp_val = _lcam_uop_T_1_fp_val; // @[lsu.scala:263:49, :1030:37] wire lcam_uop_0_fp_single = _lcam_uop_T_1_fp_single; // @[lsu.scala:263:49, :1030:37] wire lcam_uop_0_xcpt_pf_if = _lcam_uop_T_1_xcpt_pf_if; // @[lsu.scala:263:49, :1030:37] wire lcam_uop_0_xcpt_ae_if = _lcam_uop_T_1_xcpt_ae_if; // @[lsu.scala:263:49, :1030:37] wire lcam_uop_0_xcpt_ma_if = _lcam_uop_T_1_xcpt_ma_if; // @[lsu.scala:263:49, :1030:37] wire lcam_uop_0_bp_debug_if = _lcam_uop_T_1_bp_debug_if; // @[lsu.scala:263:49, :1030:37] wire lcam_uop_0_bp_xcpt_if = _lcam_uop_T_1_bp_xcpt_if; // @[lsu.scala:263:49, :1030:37] wire [1:0] lcam_uop_0_debug_fsrc = _lcam_uop_T_1_debug_fsrc; // @[lsu.scala:263:49, :1030:37] wire [1:0] lcam_uop_0_debug_tsrc = _lcam_uop_T_1_debug_tsrc; // @[lsu.scala:263:49, :1030:37] wire [7:0] lcam_mask_mask; // @[lsu.scala:1665:22] wire [7:0] lcam_mask_0 = lcam_mask_mask; // @[lsu.scala:263:49, :1665:22] wire _lcam_mask_mask_T = lcam_uop_0_mem_size == 2'h0; // @[lsu.scala:263:49, :1667:26] wire [2:0] _lcam_mask_mask_T_1 = lcam_addr_0[2:0]; // @[lsu.scala:263:49, :1667:55] wire [14:0] _lcam_mask_mask_T_2 = 15'h1 << _lcam_mask_mask_T_1; // @[lsu.scala:1667:{48,55}] wire _lcam_mask_mask_T_3 = lcam_uop_0_mem_size == 2'h1; // @[lsu.scala:263:49, :1668:26] wire [1:0] _lcam_mask_mask_T_4 = lcam_addr_0[2:1]; // @[lsu.scala:263:49, :1668:56] wire [2:0] _lcam_mask_mask_T_5 = {_lcam_mask_mask_T_4, 1'h0}; // @[lsu.scala:1668:{56,62}] wire [14:0] _lcam_mask_mask_T_6 = 15'h3 << _lcam_mask_mask_T_5; // @[lsu.scala:1668:{48,62}] wire _lcam_mask_mask_T_7 = lcam_uop_0_mem_size == 2'h2; // @[lsu.scala:263:49, :1669:26] wire _lcam_mask_mask_T_8 = lcam_addr_0[2]; // @[lsu.scala:263:49, :1669:46] wire [7:0] _lcam_mask_mask_T_9 = _lcam_mask_mask_T_8 ? 8'hF0 : 8'hF; // @[lsu.scala:1669:{41,46}] wire _lcam_mask_mask_T_10 = &lcam_uop_0_mem_size; // @[lsu.scala:263:49, :1670:26] wire [7:0] _lcam_mask_mask_T_12 = _lcam_mask_mask_T_7 ? _lcam_mask_mask_T_9 : 8'hFF; // @[Mux.scala:126:16] wire [14:0] _lcam_mask_mask_T_13 = _lcam_mask_mask_T_3 ? _lcam_mask_mask_T_6 : {7'h0, _lcam_mask_mask_T_12}; // @[Mux.scala:126:16] wire [14:0] _lcam_mask_mask_T_14 = _lcam_mask_mask_T ? _lcam_mask_mask_T_2 : _lcam_mask_mask_T_13; // @[Mux.scala:126:16] assign lcam_mask_mask = _lcam_mask_mask_T_14[7:0]; // @[Mux.scala:126:16] reg [2:0] lcam_ldq_idx_REG; // @[lsu.scala:1038:58] reg [2:0] lcam_ldq_idx_REG_1; // @[lsu.scala:1039:58] wire [2:0] _lcam_ldq_idx_T = fired_load_retry_0 ? lcam_ldq_idx_REG_1 : 3'h0; // @[lsu.scala:263:49, :1039:{26,58}] wire [2:0] _lcam_ldq_idx_T_1 = fired_load_wakeup_0 ? lcam_ldq_idx_REG : _lcam_ldq_idx_T; // @[lsu.scala:263:49, :1038:{26,58}, :1039:26] wire [2:0] _lcam_ldq_idx_T_2 = fired_load_incoming_0 ? mem_incoming_uop_0_ldq_idx : _lcam_ldq_idx_T_1; // @[lsu.scala:263:49, :909:37, :1037:26, :1038:26] wire [2:0] lcam_ldq_idx_0 = _lcam_ldq_idx_T_2; // @[lsu.scala:263:49, :1037:26] wire [2:0] _can_forward_T_2 = lcam_ldq_idx_0; // @[lsu.scala:263:49] reg [2:0] lcam_stq_idx_REG; // @[lsu.scala:1043:58] wire [2:0] _lcam_stq_idx_T_1 = fired_sta_retry_0 ? lcam_stq_idx_REG : 3'h0; // @[lsu.scala:263:49, :1043:{26,58}] wire [2:0] _lcam_stq_idx_T_2 = _lcam_stq_idx_T ? mem_incoming_uop_0_stq_idx : _lcam_stq_idx_T_1; // @[lsu.scala:909:37, :1041:{26,50}, :1043:26] wire [2:0] lcam_stq_idx_0 = _lcam_stq_idx_T_2; // @[lsu.scala:263:49, :1041:26] wire _can_forward_T_1 = ~mem_tlb_uncacheable_0; // @[lsu.scala:927:41, :1046:56] wire [2:0] _can_forward_T_3 = _can_forward_T_2; wire _can_forward_T_4 = ~_GEN_174[_can_forward_T_3]; // @[lsu.scala:263:49, :1047:7] wire _can_forward_T_5 = _can_forward_T ? _can_forward_T_1 : _can_forward_T_4; // @[lsu.scala:1046:{8,32,56}, :1047:7] wire _can_forward_WIRE_0 = _can_forward_T_5; // @[lsu.scala:263:49, :1046:8] wire can_forward_0; // @[lsu.scala:1045:29] wire ldst_addr_matches_0_0; // @[lsu.scala:1050:38] wire ldst_addr_matches_0_1; // @[lsu.scala:1050:38] wire ldst_addr_matches_0_2; // @[lsu.scala:1050:38] wire ldst_addr_matches_0_3; // @[lsu.scala:1050:38] wire ldst_addr_matches_0_4; // @[lsu.scala:1050:38] wire ldst_addr_matches_0_5; // @[lsu.scala:1050:38] wire ldst_addr_matches_0_6; // @[lsu.scala:1050:38] wire ldst_addr_matches_0_7; // @[lsu.scala:1050:38] wire ldst_forward_matches_0_0; // @[lsu.scala:1052:38] wire ldst_forward_matches_0_1; // @[lsu.scala:1052:38] wire ldst_forward_matches_0_2; // @[lsu.scala:1052:38] wire ldst_forward_matches_0_3; // @[lsu.scala:1052:38] wire ldst_forward_matches_0_4; // @[lsu.scala:1052:38] wire ldst_forward_matches_0_5; // @[lsu.scala:1052:38] wire ldst_forward_matches_0_6; // @[lsu.scala:1052:38] wire ldst_forward_matches_0_7; // @[lsu.scala:1052:38] wire _temp_bits_WIRE_1_8 = failed_loads_0; // @[lsu.scala:1054:34, :1229:27] wire _temp_bits_WIRE_1_9 = failed_loads_1; // @[lsu.scala:1054:34, :1229:27] wire _temp_bits_WIRE_1_10 = failed_loads_2; // @[lsu.scala:1054:34, :1229:27] wire _temp_bits_WIRE_1_11 = failed_loads_3; // @[lsu.scala:1054:34, :1229:27] wire _temp_bits_WIRE_1_12 = failed_loads_4; // @[lsu.scala:1054:34, :1229:27] wire _temp_bits_WIRE_1_13 = failed_loads_5; // @[lsu.scala:1054:34, :1229:27] wire _temp_bits_WIRE_1_14 = failed_loads_6; // @[lsu.scala:1054:34, :1229:27] wire failed_loads_7; // @[lsu.scala:1054:34] wire _temp_bits_T_15 = failed_loads_7; // @[lsu.scala:1054:34, :1230:21] wire _temp_bits_WIRE_1_15 = failed_loads_7; // @[lsu.scala:1054:34, :1229:27] wire nacking_loads_0; // @[lsu.scala:1055:34] wire nacking_loads_1; // @[lsu.scala:1055:34] wire nacking_loads_2; // @[lsu.scala:1055:34] wire nacking_loads_3; // @[lsu.scala:1055:34] wire nacking_loads_4; // @[lsu.scala:1055:34] wire nacking_loads_5; // @[lsu.scala:1055:34] wire nacking_loads_6; // @[lsu.scala:1055:34] wire nacking_loads_7; // @[lsu.scala:1055:34] reg s1_executing_loads_0; // @[lsu.scala:1057:35] reg s1_executing_loads_1; // @[lsu.scala:1057:35] reg s1_executing_loads_2; // @[lsu.scala:1057:35] reg s1_executing_loads_3; // @[lsu.scala:1057:35] reg s1_executing_loads_4; // @[lsu.scala:1057:35] reg s1_executing_loads_5; // @[lsu.scala:1057:35] reg s1_executing_loads_6; // @[lsu.scala:1057:35] reg s1_executing_loads_7; // @[lsu.scala:1057:35] wire s1_set_execute_0; // @[lsu.scala:1058:36] wire s1_set_execute_1; // @[lsu.scala:1058:36] wire s1_set_execute_2; // @[lsu.scala:1058:36] wire s1_set_execute_3; // @[lsu.scala:1058:36] wire s1_set_execute_4; // @[lsu.scala:1058:36] wire s1_set_execute_5; // @[lsu.scala:1058:36] wire s1_set_execute_6; // @[lsu.scala:1058:36] wire s1_set_execute_7; // @[lsu.scala:1058:36] wire mem_forward_valid_0; // @[lsu.scala:1060:33] wire [2:0] forwarding_idx_0; // @[lsu.scala:263:49] wire [2:0] mem_forward_stq_idx_0; // @[lsu.scala:1063:33] reg wb_forward_valid_0; // @[lsu.scala:1065:36] reg [2:0] wb_forward_ldq_idx_0; // @[lsu.scala:1066:36] wire [2:0] _forward_uop_T = wb_forward_ldq_idx_0; // @[lsu.scala:1066:36] reg [39:0] wb_forward_ld_addr_0; // @[lsu.scala:1067:36] reg [2:0] wb_forward_stq_idx_0; // @[lsu.scala:1068:36] wire [7:0] l_mask; // @[lsu.scala:1665:22] wire _l_mask_mask_T = ldq_0_bits_uop_mem_size == 2'h0; // @[lsu.scala:208:16, :1667:26] wire [2:0] _l_mask_mask_T_1 = ldq_0_bits_addr_bits[2:0]; // @[lsu.scala:208:16, :1667:55] wire [14:0] _l_mask_mask_T_2 = 15'h1 << _l_mask_mask_T_1; // @[lsu.scala:1667:{48,55}] wire _l_mask_mask_T_3 = ldq_0_bits_uop_mem_size == 2'h1; // @[lsu.scala:208:16, :1668:26] wire [1:0] _l_mask_mask_T_4 = ldq_0_bits_addr_bits[2:1]; // @[lsu.scala:208:16, :1668:56] wire [2:0] _l_mask_mask_T_5 = {_l_mask_mask_T_4, 1'h0}; // @[lsu.scala:1668:{56,62}] wire [14:0] _l_mask_mask_T_6 = 15'h3 << _l_mask_mask_T_5; // @[lsu.scala:1668:{48,62}] wire _l_mask_mask_T_7 = ldq_0_bits_uop_mem_size == 2'h2; // @[lsu.scala:208:16, :1669:26] wire _l_mask_mask_T_8 = ldq_0_bits_addr_bits[2]; // @[lsu.scala:208:16, :1669:46] wire [7:0] _l_mask_mask_T_9 = _l_mask_mask_T_8 ? 8'hF0 : 8'hF; // @[lsu.scala:1669:{41,46}] wire _l_mask_mask_T_10 = &ldq_0_bits_uop_mem_size; // @[lsu.scala:208:16, :1670:26] wire [7:0] _l_mask_mask_T_12 = _l_mask_mask_T_7 ? _l_mask_mask_T_9 : 8'hFF; // @[Mux.scala:126:16] wire [14:0] _l_mask_mask_T_13 = _l_mask_mask_T_3 ? _l_mask_mask_T_6 : {7'h0, _l_mask_mask_T_12}; // @[Mux.scala:126:16] wire [14:0] _l_mask_mask_T_14 = _l_mask_mask_T ? _l_mask_mask_T_2 : _l_mask_mask_T_13; // @[Mux.scala:126:16] assign l_mask = _l_mask_mask_T_14[7:0]; // @[Mux.scala:126:16] wire _l_forwarders_T = wb_forward_ldq_idx_0 == 3'h0; // @[lsu.scala:1066:36, :1076:88] wire _l_forwarders_T_1 = wb_forward_valid_0 & _l_forwarders_T; // @[lsu.scala:1065:36, :1076:{63,88}] wire l_forwarders_0 = _l_forwarders_T_1; // @[lsu.scala:263:49, :1076:63] wire [2:0] l_forward_stq_idx = l_forwarders_0 ? wb_forward_stq_idx_0 : ldq_0_bits_forward_stq_idx; // @[lsu.scala:208:16, :263:49, :1068:36, :1078:32] wire [33:0] _block_addr_matches_T = lcam_addr_0[39:6]; // @[lsu.scala:263:49, :1081:57] wire [33:0] _block_addr_matches_T_3 = lcam_addr_0[39:6]; // @[lsu.scala:263:49, :1081:57] wire [33:0] _block_addr_matches_T_6 = lcam_addr_0[39:6]; // @[lsu.scala:263:49, :1081:57] wire [33:0] _block_addr_matches_T_9 = lcam_addr_0[39:6]; // @[lsu.scala:263:49, :1081:57] wire [33:0] _block_addr_matches_T_12 = lcam_addr_0[39:6]; // @[lsu.scala:263:49, :1081:57] wire [33:0] _block_addr_matches_T_15 = lcam_addr_0[39:6]; // @[lsu.scala:263:49, :1081:57] wire [33:0] _block_addr_matches_T_18 = lcam_addr_0[39:6]; // @[lsu.scala:263:49, :1081:57] wire [33:0] _block_addr_matches_T_21 = lcam_addr_0[39:6]; // @[lsu.scala:263:49, :1081:57] wire [33:0] _block_addr_matches_T_1 = ldq_0_bits_addr_bits[39:6]; // @[lsu.scala:208:16, :1081:84] wire _block_addr_matches_T_2 = _block_addr_matches_T == _block_addr_matches_T_1; // @[lsu.scala:1081:{57,73,84}] wire block_addr_matches_0 = _block_addr_matches_T_2; // @[lsu.scala:263:49, :1081:73] wire [2:0] _dword_addr_matches_T = lcam_addr_0[5:3]; // @[lsu.scala:263:49, :1082:81] wire [2:0] _dword_addr_matches_T_4 = lcam_addr_0[5:3]; // @[lsu.scala:263:49, :1082:81] wire [2:0] _dword_addr_matches_T_8 = lcam_addr_0[5:3]; // @[lsu.scala:263:49, :1082:81] wire [2:0] _dword_addr_matches_T_12 = lcam_addr_0[5:3]; // @[lsu.scala:263:49, :1082:81] wire [2:0] _dword_addr_matches_T_16 = lcam_addr_0[5:3]; // @[lsu.scala:263:49, :1082:81] wire [2:0] _dword_addr_matches_T_20 = lcam_addr_0[5:3]; // @[lsu.scala:263:49, :1082:81] wire [2:0] _dword_addr_matches_T_24 = lcam_addr_0[5:3]; // @[lsu.scala:263:49, :1082:81] wire [2:0] _dword_addr_matches_T_28 = lcam_addr_0[5:3]; // @[lsu.scala:263:49, :1082:81] wire [2:0] _dword_addr_matches_T_1 = ldq_0_bits_addr_bits[5:3]; // @[lsu.scala:208:16, :1082:110] wire _dword_addr_matches_T_2 = _dword_addr_matches_T == _dword_addr_matches_T_1; // @[lsu.scala:1082:{81,100,110}] wire _dword_addr_matches_T_3 = block_addr_matches_0 & _dword_addr_matches_T_2; // @[lsu.scala:263:49, :1082:{66,100}] wire dword_addr_matches_0 = _dword_addr_matches_T_3; // @[lsu.scala:263:49, :1082:66] wire [7:0] _GEN_229 = l_mask & lcam_mask_0; // @[lsu.scala:263:49, :1083:46, :1665:22] wire [7:0] _mask_match_T; // @[lsu.scala:1083:46] assign _mask_match_T = _GEN_229; // @[lsu.scala:1083:46] wire [7:0] _mask_overlap_T; // @[lsu.scala:1084:46] assign _mask_overlap_T = _GEN_229; // @[lsu.scala:1083:46, :1084:46] wire _mask_match_T_1 = _mask_match_T == l_mask; // @[lsu.scala:1083:{46,62}, :1665:22] wire mask_match_0 = _mask_match_T_1; // @[lsu.scala:263:49, :1083:62] wire _mask_overlap_T_1 = \|_mask_overlap_T; // @[lsu.scala:1084:{46,62}] wire mask_overlap_0 = _mask_overlap_T_1; // @[lsu.scala:263:49, :1084:62] wire _T_185 = do_release_search_0 & ldq_0_valid & ldq_0_bits_addr_valid & block_addr_matches_0; // @[lsu.scala:208:16, :263:49, :1089:34, :1090:34, :1091:34] wire _T_214 = ldq_0_bits_executed \| ldq_0_bits_succeeded; // @[lsu.scala:208:16, :1099:37] wire [7:0] _GEN_230 = {5'h0, lcam_stq_idx_0}; // @[lsu.scala:263:49, :1101:38] wire [7:0] _T_193 = ldq_0_bits_st_dep_mask >> _GEN_230; // @[lsu.scala:208:16, :1101:38] wire _T_197 = do_st_search_0 & ldq_0_valid & ldq_0_bits_addr_valid & (_T_214 \| l_forwarders_0) & ~ldq_0_bits_addr_is_virtual & _T_193[0] & dword_addr_matches_0 & mask_overlap_0; // @[lsu.scala:208:16, :263:49, :432:52, :1096:131, :1097:131, :1098:131, :1099:{37,57,131}, :1100:131, :1101:{38,131}, :1102:131] wire _forwarded_is_older_T = l_forward_stq_idx < lcam_stq_idx_0; // @[util.scala:363:52] wire _forwarded_is_older_T_1 = l_forward_stq_idx < ldq_0_bits_youngest_stq_idx; // @[util.scala:363:64] wire _forwarded_is_older_T_2 = _forwarded_is_older_T ^ _forwarded_is_older_T_1; // @[util.scala:363:{52,58,64}] wire _forwarded_is_older_T_3 = lcam_stq_idx_0 < ldq_0_bits_youngest_stq_idx; // @[util.scala:363:78] wire forwarded_is_older = _forwarded_is_older_T_2 ^ _forwarded_is_older_T_3; // @[util.scala:363:{58,72,78}] wire _T_201 = ~ldq_0_bits_forward_std_val \| l_forward_stq_idx != lcam_stq_idx_0 & forwarded_is_older; // @[util.scala:363:72] wire _T_207 = do_ld_search_0 & ldq_0_valid & ldq_0_bits_addr_valid & ~ldq_0_bits_addr_is_virtual & dword_addr_matches_0 & mask_overlap_0; // @[lsu.scala:208:16, :263:49, :432:52, :1112:47, :1113:47, :1114:47, :1115:47, :1116:47] wire _GEN_231 = lcam_ldq_idx_0 < ldq_head; // @[util.scala:363:64] wire _searcher_is_older_T_1; // @[util.scala:363:64] assign _searcher_is_older_T_1 = _GEN_231; // @[util.scala:363:64] wire _searcher_is_older_T_5; // @[util.scala:363:64] assign _searcher_is_older_T_5 = _GEN_231; // @[util.scala:363:64] wire _searcher_is_older_T_9; // @[util.scala:363:64] assign _searcher_is_older_T_9 = _GEN_231; // @[util.scala:363:64] wire _searcher_is_older_T_13; // @[util.scala:363:64] assign _searcher_is_older_T_13 = _GEN_231; // @[util.scala:363:64] wire _searcher_is_older_T_17; // @[util.scala:363:64] assign _searcher_is_older_T_17 = _GEN_231; // @[util.scala:363:64] wire _searcher_is_older_T_21; // @[util.scala:363:64] assign _searcher_is_older_T_21 = _GEN_231; // @[util.scala:363:64] wire _searcher_is_older_T_25; // @[util.scala:363:64] assign _searcher_is_older_T_25 = _GEN_231; // @[util.scala:363:64] wire _searcher_is_older_T_29; // @[util.scala:363:64] assign _searcher_is_older_T_29 = _GEN_231; // @[util.scala:363:64] wire _searcher_is_older_T_2 = _searcher_is_older_T_1; // @[util.scala:363:{58,64}] wire _searcher_is_older_T_3 = \|ldq_head; // @[util.scala:363:78] wire searcher_is_older = _searcher_is_older_T_2 ^ _searcher_is_older_T_3; // @[util.scala:363:{58,72,78}] wire _GEN_232 = _T_207 & searcher_is_older & (_T_214 \| l_forwarders_0) & ~s1_executing_loads_0 & ldq_0_bits_observed; // @[util.scala:363:72] assign failed_loads_0 = ~_T_185 & (_T_197 ? _T_201 : _GEN_232); // @[lsu.scala:303:5, :1054:34, :1089:34, :1090:34, :1091:34, :1092:36, :1096:131, :1097:131, :1098:131, :1099:131, :1100:131, :1101:131, :1102:131, :1103:37, :1107:39, :1108:76, :1117:37, :1119:34, :1120:74, :1121:40, :1122:34, :1123:36] reg older_nacked_REG; // @[lsu.scala:1129:57] wire older_nacked = nacking_loads_0 \| older_nacked_REG; // @[lsu.scala:1055:34, :1129:{47,57}] wire _T_216 = ~_T_214 \| older_nacked; // @[lsu.scala:1099:37, :1129:47, :1130:{17,56}] wire _searcher_is_older_T_4 = lcam_ldq_idx_0 == 3'h0; // @[util.scala:363:52] wire _GEN_233 = _T_185 \| _T_197; // @[lsu.scala:1058:36, :1089:34, :1090:34, :1091:34, :1092:36, :1096:131, :1097:131, :1098:131, :1099:131, :1100:131, :1101:131, :1102:131, :1103:37, :1117:37] wire _GEN_234 = lcam_ldq_idx_0 == 3'h1; // @[lsu.scala:263:49, :1131:48] wire _GEN_235 = lcam_ldq_idx_0 == 3'h2; // @[lsu.scala:263:49, :1131:48] wire _GEN_236 = lcam_ldq_idx_0 == 3'h3; // @[lsu.scala:263:49, :1131:48] wire _GEN_237 = lcam_ldq_idx_0 == 3'h4; // @[lsu.scala:263:49, :1131:48] wire _GEN_238 = lcam_ldq_idx_0 == 3'h5; // @[lsu.scala:263:49, :1131:48] wire _GEN_239 = lcam_ldq_idx_0 == 3'h6; // @[lsu.scala:263:49, :1131:48] reg io_dmem_s1_kill_0_REG; // @[lsu.scala:1132:58] wire _GEN_240 = (\|lcam_ldq_idx_0) & _T_216; // @[lsu.scala:263:49, :765:24, :1126:{38,47}, :1130:{56,73}, :1132:48] wire [7:0] l_mask_1; // @[lsu.scala:1665:22] wire _l_mask_mask_T_15 = ldq_1_bits_uop_mem_size == 2'h0; // @[lsu.scala:208:16, :1667:26] wire [2:0] _l_mask_mask_T_16 = ldq_1_bits_addr_bits[2:0]; // @[lsu.scala:208:16, :1667:55] wire [14:0] _l_mask_mask_T_17 = 15'h1 << _l_mask_mask_T_16; // @[lsu.scala:1667:{48,55}] wire _l_mask_mask_T_18 = ldq_1_bits_uop_mem_size == 2'h1; // @[lsu.scala:208:16, :1668:26] wire [1:0] _l_mask_mask_T_19 = ldq_1_bits_addr_bits[2:1]; // @[lsu.scala:208:16, :1668:56] wire [2:0] _l_mask_mask_T_20 = {_l_mask_mask_T_19, 1'h0}; // @[lsu.scala:1668:{56,62}] wire [14:0] _l_mask_mask_T_21 = 15'h3 << _l_mask_mask_T_20; // @[lsu.scala:1668:{48,62}] wire _l_mask_mask_T_22 = ldq_1_bits_uop_mem_size == 2'h2; // @[lsu.scala:208:16, :1669:26] wire _l_mask_mask_T_23 = ldq_1_bits_addr_bits[2]; // @[lsu.scala:208:16, :1669:46] wire [7:0] _l_mask_mask_T_24 = _l_mask_mask_T_23 ? 8'hF0 : 8'hF; // @[lsu.scala:1669:{41,46}] wire _l_mask_mask_T_25 = &ldq_1_bits_uop_mem_size; // @[lsu.scala:208:16, :1670:26] wire [7:0] _l_mask_mask_T_27 = _l_mask_mask_T_22 ? _l_mask_mask_T_24 : 8'hFF; // @[Mux.scala:126:16] wire [14:0] _l_mask_mask_T_28 = _l_mask_mask_T_18 ? _l_mask_mask_T_21 : {7'h0, _l_mask_mask_T_27}; // @[Mux.scala:126:16] wire [14:0] _l_mask_mask_T_29 = _l_mask_mask_T_15 ? _l_mask_mask_T_17 : _l_mask_mask_T_28; // @[Mux.scala:126:16] assign l_mask_1 = _l_mask_mask_T_29[7:0]; // @[Mux.scala:126:16] wire _l_forwarders_T_2 = wb_forward_ldq_idx_0 == 3'h1; // @[lsu.scala:1066:36, :1076:88] wire _l_forwarders_T_3 = wb_forward_valid_0 & _l_forwarders_T_2; // @[lsu.scala:1065:36, :1076:{63,88}] wire l_forwarders_1_0 = _l_forwarders_T_3; // @[lsu.scala:263:49, :1076:63] wire [2:0] l_forward_stq_idx_1 = l_forwarders_1_0 ? wb_forward_stq_idx_0 : ldq_1_bits_forward_stq_idx; // @[lsu.scala:208:16, :263:49, :1068:36, :1078:32] wire [33:0] _block_addr_matches_T_4 = ldq_1_bits_addr_bits[39:6]; // @[lsu.scala:208:16, :1081:84] wire _block_addr_matches_T_5 = _block_addr_matches_T_3 == _block_addr_matches_T_4; // @[lsu.scala:1081:{57,73,84}] wire block_addr_matches_1_0 = _block_addr_matches_T_5; // @[lsu.scala:263:49, :1081:73] wire [2:0] _dword_addr_matches_T_5 = ldq_1_bits_addr_bits[5:3]; // @[lsu.scala:208:16, :1082:110] wire _dword_addr_matches_T_6 = _dword_addr_matches_T_4 == _dword_addr_matches_T_5; // @[lsu.scala:1082:{81,100,110}] wire _dword_addr_matches_T_7 = block_addr_matches_1_0 & _dword_addr_matches_T_6; // @[lsu.scala:263:49, :1082:{66,100}] wire dword_addr_matches_1_0 = _dword_addr_matches_T_7; // @[lsu.scala:263:49, :1082:66] wire [7:0] _GEN_241 = l_mask_1 & lcam_mask_0; // @[lsu.scala:263:49, :1083:46, :1665:22] wire [7:0] _mask_match_T_2; // @[lsu.scala:1083:46] assign _mask_match_T_2 = _GEN_241; // @[lsu.scala:1083:46] wire [7:0] _mask_overlap_T_2; // @[lsu.scala:1084:46] assign _mask_overlap_T_2 = _GEN_241; // @[lsu.scala:1083:46, :1084:46] wire _mask_match_T_3 = _mask_match_T_2 == l_mask_1; // @[lsu.scala:1083:{46,62}, :1665:22] wire mask_match_1_0 = _mask_match_T_3; // @[lsu.scala:263:49, :1083:62] wire _mask_overlap_T_3 = \|_mask_overlap_T_2; // @[lsu.scala:1084:{46,62}] wire mask_overlap_1_0 = _mask_overlap_T_3; // @[lsu.scala:263:49, :1084:62] wire _T_221 = do_release_search_0 & ldq_1_valid & ldq_1_bits_addr_valid & block_addr_matches_1_0; // @[lsu.scala:208:16, :263:49, :1089:34, :1090:34, :1091:34] wire _T_250 = ldq_1_bits_executed \| ldq_1_bits_succeeded; // @[lsu.scala:208:16, :1099:37] wire [7:0] _T_229 = ldq_1_bits_st_dep_mask >> _GEN_230; // @[lsu.scala:208:16, :1101:38] wire _T_233 = do_st_search_0 & ldq_1_valid & ldq_1_bits_addr_valid & (_T_250 \| l_forwarders_1_0) & ~ldq_1_bits_addr_is_virtual & _T_229[0] & dword_addr_matches_1_0 & mask_overlap_1_0; // @[lsu.scala:208:16, :263:49, :432:52, :1096:131, :1097:131, :1098:131, :1099:{37,57,131}, :1100:131, :1101:{38,131}, :1102:131] wire _forwarded_is_older_T_4 = l_forward_stq_idx_1 < lcam_stq_idx_0; // @[util.scala:363:52] wire _forwarded_is_older_T_5 = l_forward_stq_idx_1 < ldq_1_bits_youngest_stq_idx; // @[util.scala:363:64] wire _forwarded_is_older_T_6 = _forwarded_is_older_T_4 ^ _forwarded_is_older_T_5; // @[util.scala:363:{52,58,64}] wire _forwarded_is_older_T_7 = lcam_stq_idx_0 < ldq_1_bits_youngest_stq_idx; // @[util.scala:363:78] wire forwarded_is_older_1 = _forwarded_is_older_T_6 ^ _forwarded_is_older_T_7; // @[util.scala:363:{58,72,78}] wire _T_237 = ~ldq_1_bits_forward_std_val \| l_forward_stq_idx_1 != lcam_stq_idx_0 & forwarded_is_older_1; // @[util.scala:363:72] wire _T_243 = do_ld_search_0 & ldq_1_valid & ldq_1_bits_addr_valid & ~ldq_1_bits_addr_is_virtual & dword_addr_matches_1_0 & mask_overlap_1_0; // @[lsu.scala:208:16, :263:49, :432:52, :1112:47, :1113:47, :1114:47, :1115:47, :1116:47] wire _searcher_is_older_T_6 = _searcher_is_older_T_4 ^ _searcher_is_older_T_5; // @[util.scala:363:{52,58,64}] wire _searcher_is_older_T_7 = \|(ldq_head[2:1]); // @[util.scala:351:72, :363:78] wire searcher_is_older_1 = _searcher_is_older_T_6 ^ _searcher_is_older_T_7; // @[util.scala:363:{58,72,78}] wire _GEN_242 = _T_243 & searcher_is_older_1 & (_T_250 \| l_forwarders_1_0) & ~s1_executing_loads_1 & ldq_1_bits_observed; // @[util.scala:363:72] assign failed_loads_1 = ~_T_221 & (_T_233 ? _T_237 : _GEN_242); // @[lsu.scala:303:5, :1054:34, :1089:34, :1090:34, :1091:34, :1092:36, :1096:131, :1097:131, :1098:131, :1099:131, :1100:131, :1101:131, :1102:131, :1103:37, :1107:39, :1108:76, :1117:37, :1119:34, :1120:74, :1121:40, :1122:34, :1123:36] reg older_nacked_REG_1; // @[lsu.scala:1129:57] wire older_nacked_1 = nacking_loads_1 \| older_nacked_REG_1; // @[lsu.scala:1055:34, :1129:{47,57}] wire _T_252 = ~_T_250 \| older_nacked_1; // @[lsu.scala:1099:37, :1129:47, :1130:{17,56}] wire _GEN_243 = searcher_is_older_1 \| _GEN_234; // @[util.scala:363:72] wire _GEN_244 = _T_221 \| _T_233; // @[lsu.scala:1089:34, :1090:34, :1091:34, :1092:36, :1096:131, :1097:131, :1098:131, :1099:131, :1100:131, :1101:131, :1102:131, :1103:37, :1117:37] reg io_dmem_s1_kill_0_REG_1; // @[lsu.scala:1132:58] wire _GEN_245 = _GEN_244 \| ~_T_243 \| _GEN_243 \| ~_T_252; // @[lsu.scala:1092:36, :1103:37, :1112:47, :1113:47, :1114:47, :1115:47, :1116:47, :1117:37, :1119:34, :1126:{38,47}, :1130:{56,73}] wire [7:0] l_mask_2; // @[lsu.scala:1665:22] wire _l_mask_mask_T_30 = ldq_2_bits_uop_mem_size == 2'h0; // @[lsu.scala:208:16, :1667:26] wire [2:0] _l_mask_mask_T_31 = ldq_2_bits_addr_bits[2:0]; // @[lsu.scala:208:16, :1667:55] wire [14:0] _l_mask_mask_T_32 = 15'h1 << _l_mask_mask_T_31; // @[lsu.scala:1667:{48,55}] wire _l_mask_mask_T_33 = ldq_2_bits_uop_mem_size == 2'h1; // @[lsu.scala:208:16, :1668:26] wire [1:0] _l_mask_mask_T_34 = ldq_2_bits_addr_bits[2:1]; // @[lsu.scala:208:16, :1668:56] wire [2:0] _l_mask_mask_T_35 = {_l_mask_mask_T_34, 1'h0}; // @[lsu.scala:1668:{56,62}] wire [14:0] _l_mask_mask_T_36 = 15'h3 << _l_mask_mask_T_35; // @[lsu.scala:1668:{48,62}] wire _l_mask_mask_T_37 = ldq_2_bits_uop_mem_size == 2'h2; // @[lsu.scala:208:16, :1669:26] wire _l_mask_mask_T_38 = ldq_2_bits_addr_bits[2]; // @[lsu.scala:208:16, :1669:46] wire [7:0] _l_mask_mask_T_39 = _l_mask_mask_T_38 ? 8'hF0 : 8'hF; // @[lsu.scala:1669:{41,46}] wire _l_mask_mask_T_40 = &ldq_2_bits_uop_mem_size; // @[lsu.scala:208:16, :1670:26] wire [7:0] _l_mask_mask_T_42 = _l_mask_mask_T_37 ? _l_mask_mask_T_39 : 8'hFF; // @[Mux.scala:126:16] wire [14:0] _l_mask_mask_T_43 = _l_mask_mask_T_33 ? _l_mask_mask_T_36 : {7'h0, _l_mask_mask_T_42}; // @[Mux.scala:126:16] wire [14:0] _l_mask_mask_T_44 = _l_mask_mask_T_30 ? _l_mask_mask_T_32 : _l_mask_mask_T_43; // @[Mux.scala:126:16] assign l_mask_2 = _l_mask_mask_T_44[7:0]; // @[Mux.scala:126:16] wire _l_forwarders_T_4 = wb_forward_ldq_idx_0 == 3'h2; // @[lsu.scala:1066:36, :1076:88] wire _l_forwarders_T_5 = wb_forward_valid_0 & _l_forwarders_T_4; // @[lsu.scala:1065:36, :1076:{63,88}] wire l_forwarders_2_0 = _l_forwarders_T_5; // @[lsu.scala:263:49, :1076:63] wire [2:0] l_forward_stq_idx_2 = l_forwarders_2_0 ? wb_forward_stq_idx_0 : ldq_2_bits_forward_stq_idx; // @[lsu.scala:208:16, :263:49, :1068:36, :1078:32] wire [33:0] _block_addr_matches_T_7 = ldq_2_bits_addr_bits[39:6]; // @[lsu.scala:208:16, :1081:84] wire _block_addr_matches_T_8 = _block_addr_matches_T_6 == _block_addr_matches_T_7; // @[lsu.scala:1081:{57,73,84}] wire block_addr_matches_2_0 = _block_addr_matches_T_8; // @[lsu.scala:263:49, :1081:73] wire [2:0] _dword_addr_matches_T_9 = ldq_2_bits_addr_bits[5:3]; // @[lsu.scala:208:16, :1082:110] wire _dword_addr_matches_T_10 = _dword_addr_matches_T_8 == _dword_addr_matches_T_9; // @[lsu.scala:1082:{81,100,110}] wire _dword_addr_matches_T_11 = block_addr_matches_2_0 & _dword_addr_matches_T_10; // @[lsu.scala:263:49, :1082:{66,100}] wire dword_addr_matches_2_0 = _dword_addr_matches_T_11; // @[lsu.scala:263:49, :1082:66] wire [7:0] _GEN_246 = l_mask_2 & lcam_mask_0; // @[lsu.scala:263:49, :1083:46, :1665:22] wire [7:0] _mask_match_T_4; // @[lsu.scala:1083:46] assign _mask_match_T_4 = _GEN_246; // @[lsu.scala:1083:46] wire [7:0] _mask_overlap_T_4; // @[lsu.scala:1084:46] assign _mask_overlap_T_4 = _GEN_246; // @[lsu.scala:1083:46, :1084:46] wire _mask_match_T_5 = _mask_match_T_4 == l_mask_2; // @[lsu.scala:1083:{46,62}, :1665:22] wire mask_match_2_0 = _mask_match_T_5; // @[lsu.scala:263:49, :1083:62] wire _mask_overlap_T_5 = \|_mask_overlap_T_4; // @[lsu.scala:1084:{46,62}] wire mask_overlap_2_0 = _mask_overlap_T_5; // @[lsu.scala:263:49, :1084:62] wire _T_257 = do_release_search_0 & ldq_2_valid & ldq_2_bits_addr_valid & block_addr_matches_2_0; // @[lsu.scala:208:16, :263:49, :1089:34, :1090:34, :1091:34] wire _T_286 = ldq_2_bits_executed \| ldq_2_bits_succeeded; // @[lsu.scala:208:16, :1099:37] wire [7:0] _T_265 = ldq_2_bits_st_dep_mask >> _GEN_230; // @[lsu.scala:208:16, :1101:38] wire _T_269 = do_st_search_0 & ldq_2_valid & ldq_2_bits_addr_valid & (_T_286 \| l_forwarders_2_0) & ~ldq_2_bits_addr_is_virtual & _T_265[0] & dword_addr_matches_2_0 & mask_overlap_2_0; // @[lsu.scala:208:16, :263:49, :432:52, :1096:131, :1097:131, :1098:131, :1099:{37,57,131}, :1100:131, :1101:{38,131}, :1102:131] wire _forwarded_is_older_T_8 = l_forward_stq_idx_2 < lcam_stq_idx_0; // @[util.scala:363:52] wire _forwarded_is_older_T_9 = l_forward_stq_idx_2 < ldq_2_bits_youngest_stq_idx; // @[util.scala:363:64] wire _forwarded_is_older_T_10 = _forwarded_is_older_T_8 ^ _forwarded_is_older_T_9; // @[util.scala:363:{52,58,64}] wire _forwarded_is_older_T_11 = lcam_stq_idx_0 < ldq_2_bits_youngest_stq_idx; // @[util.scala:363:78] wire forwarded_is_older_2 = _forwarded_is_older_T_10 ^ _forwarded_is_older_T_11; // @[util.scala:363:{58,72,78}] wire _T_273 = ~ldq_2_bits_forward_std_val \| l_forward_stq_idx_2 != lcam_stq_idx_0 & forwarded_is_older_2; // @[util.scala:363:72] wire _T_279 = do_ld_search_0 & ldq_2_valid & ldq_2_bits_addr_valid & ~ldq_2_bits_addr_is_virtual & dword_addr_matches_2_0 & mask_overlap_2_0; // @[lsu.scala:208:16, :263:49, :432:52, :1112:47, :1113:47, :1114:47, :1115:47, :1116:47] wire _searcher_is_older_T_8 = lcam_ldq_idx_0 < 3'h2; // @[util.scala:363:52] wire _searcher_is_older_T_10 = _searcher_is_older_T_8 ^ _searcher_is_older_T_9; // @[util.scala:363:{52,58,64}] wire _searcher_is_older_T_11 = ldq_head > 3'h2; // @[util.scala:363:78] wire searcher_is_older_2 = _searcher_is_older_T_10 ^ _searcher_is_older_T_11; // @[util.scala:363:{58,72,78}] wire _GEN_247 = _T_279 & searcher_is_older_2 & (_T_286 \| l_forwarders_2_0) & ~s1_executing_loads_2 & ldq_2_bits_observed; // @[util.scala:363:72] assign failed_loads_2 = ~_T_257 & (_T_269 ? _T_273 : _GEN_247); // @[lsu.scala:303:5, :1054:34, :1089:34, :1090:34, :1091:34, :1092:36, :1096:131, :1097:131, :1098:131, :1099:131, :1100:131, :1101:131, :1102:131, :1103:37, :1107:39, :1108:76, :1117:37, :1119:34, :1120:74, :1121:40, :1122:34, :1123:36] reg older_nacked_REG_2; // @[lsu.scala:1129:57] wire older_nacked_2 = nacking_loads_2 \| older_nacked_REG_2; // @[lsu.scala:1055:34, :1129:{47,57}] wire _T_288 = ~_T_286 \| older_nacked_2; // @[lsu.scala:1099:37, :1129:47, :1130:{17,56}] wire _GEN_248 = searcher_is_older_2 \| _GEN_235; // @[util.scala:363:72] wire _GEN_249 = _T_257 \| _T_269; // @[lsu.scala:1089:34, :1090:34, :1091:34, :1092:36, :1096:131, :1097:131, :1098:131, :1099:131, :1100:131, :1101:131, :1102:131, :1103:37, :1117:37] reg io_dmem_s1_kill_0_REG_2; // @[lsu.scala:1132:58] wire _GEN_250 = _GEN_249 \| ~_T_279 \| _GEN_248 \| ~_T_288; // @[lsu.scala:1092:36, :1103:37, :1112:47, :1113:47, :1114:47, :1115:47, :1116:47, :1117:37, :1119:34, :1126:{38,47}, :1130:{56,73}] wire [7:0] l_mask_3; // @[lsu.scala:1665:22] wire _l_mask_mask_T_45 = ldq_3_bits_uop_mem_size == 2'h0; // @[lsu.scala:208:16, :1667:26] wire [2:0] _l_mask_mask_T_46 = ldq_3_bits_addr_bits[2:0]; // @[lsu.scala:208:16, :1667:55] wire [14:0] _l_mask_mask_T_47 = 15'h1 << _l_mask_mask_T_46; // @[lsu.scala:1667:{48,55}] wire _l_mask_mask_T_48 = ldq_3_bits_uop_mem_size == 2'h1; // @[lsu.scala:208:16, :1668:26] wire [1:0] _l_mask_mask_T_49 = ldq_3_bits_addr_bits[2:1]; // @[lsu.scala:208:16, :1668:56] wire [2:0] _l_mask_mask_T_50 = {_l_mask_mask_T_49, 1'h0}; // @[lsu.scala:1668:{56,62}] wire [14:0] _l_mask_mask_T_51 = 15'h3 << _l_mask_mask_T_50; // @[lsu.scala:1668:{48,62}] wire _l_mask_mask_T_52 = ldq_3_bits_uop_mem_size == 2'h2; // @[lsu.scala:208:16, :1669:26] wire _l_mask_mask_T_53 = ldq_3_bits_addr_bits[2]; // @[lsu.scala:208:16, :1669:46] wire [7:0] _l_mask_mask_T_54 = _l_mask_mask_T_53 ? 8'hF0 : 8'hF; // @[lsu.scala:1669:{41,46}] wire _l_mask_mask_T_55 = &ldq_3_bits_uop_mem_size; // @[lsu.scala:208:16, :1670:26] wire [7:0] _l_mask_mask_T_57 = _l_mask_mask_T_52 ? _l_mask_mask_T_54 : 8'hFF; // @[Mux.scala:126:16] wire [14:0] _l_mask_mask_T_58 = _l_mask_mask_T_48 ? _l_mask_mask_T_51 : {7'h0, _l_mask_mask_T_57}; // @[Mux.scala:126:16] wire [14:0] _l_mask_mask_T_59 = _l_mask_mask_T_45 ? _l_mask_mask_T_47 : _l_mask_mask_T_58; // @[Mux.scala:126:16] assign l_mask_3 = _l_mask_mask_T_59[7:0]; // @[Mux.scala:126:16] wire _l_forwarders_T_6 = wb_forward_ldq_idx_0 == 3'h3; // @[lsu.scala:1066:36, :1076:88] wire _l_forwarders_T_7 = wb_forward_valid_0 & _l_forwarders_T_6; // @[lsu.scala:1065:36, :1076:{63,88}] wire l_forwarders_3_0 = _l_forwarders_T_7; // @[lsu.scala:263:49, :1076:63] wire [2:0] l_forward_stq_idx_3 = l_forwarders_3_0 ? wb_forward_stq_idx_0 : ldq_3_bits_forward_stq_idx; // @[lsu.scala:208:16, :263:49, :1068:36, :1078:32] wire [33:0] _block_addr_matches_T_10 = ldq_3_bits_addr_bits[39:6]; // @[lsu.scala:208:16, :1081:84] wire _block_addr_matches_T_11 = _block_addr_matches_T_9 == _block_addr_matches_T_10; // @[lsu.scala:1081:{57,73,84}] wire block_addr_matches_3_0 = _block_addr_matches_T_11; // @[lsu.scala:263:49, :1081:73] wire [2:0] _dword_addr_matches_T_13 = ldq_3_bits_addr_bits[5:3]; // @[lsu.scala:208:16, :1082:110] wire _dword_addr_matches_T_14 = _dword_addr_matches_T_12 == _dword_addr_matches_T_13; // @[lsu.scala:1082:{81,100,110}] wire _dword_addr_matches_T_15 = block_addr_matches_3_0 & _dword_addr_matches_T_14; // @[lsu.scala:263:49, :1082:{66,100}] wire dword_addr_matches_3_0 = _dword_addr_matches_T_15; // @[lsu.scala:263:49, :1082:66] wire [7:0] _GEN_251 = l_mask_3 & lcam_mask_0; // @[lsu.scala:263:49, :1083:46, :1665:22] wire [7:0] _mask_match_T_6; // @[lsu.scala:1083:46] assign _mask_match_T_6 = _GEN_251; // @[lsu.scala:1083:46] wire [7:0] _mask_overlap_T_6; // @[lsu.scala:1084:46] assign _mask_overlap_T_6 = _GEN_251; // @[lsu.scala:1083:46, :1084:46] wire _mask_match_T_7 = _mask_match_T_6 == l_mask_3; // @[lsu.scala:1083:{46,62}, :1665:22] wire mask_match_3_0 = _mask_match_T_7; // @[lsu.scala:263:49, :1083:62] wire _mask_overlap_T_7 = \|_mask_overlap_T_6; // @[lsu.scala:1084:{46,62}] wire mask_overlap_3_0 = _mask_overlap_T_7; // @[lsu.scala:263:49, :1084:62] wire _T_293 = do_release_search_0 & ldq_3_valid & ldq_3_bits_addr_valid & block_addr_matches_3_0; // @[lsu.scala:208:16, :263:49, :1089:34, :1090:34, :1091:34] wire _T_322 = ldq_3_bits_executed \| ldq_3_bits_succeeded; // @[lsu.scala:208:16, :1099:37] wire [7:0] _T_301 = ldq_3_bits_st_dep_mask >> _GEN_230; // @[lsu.scala:208:16, :1101:38] wire _T_305 = do_st_search_0 & ldq_3_valid & ldq_3_bits_addr_valid & (_T_322 \| l_forwarders_3_0) & ~ldq_3_bits_addr_is_virtual & _T_301[0] & dword_addr_matches_3_0 & mask_overlap_3_0; // @[lsu.scala:208:16, :263:49, :432:52, :1096:131, :1097:131, :1098:131, :1099:{37,57,131}, :1100:131, :1101:{38,131}, :1102:131] wire _forwarded_is_older_T_12 = l_forward_stq_idx_3 < lcam_stq_idx_0; // @[util.scala:363:52] wire _forwarded_is_older_T_13 = l_forward_stq_idx_3 < ldq_3_bits_youngest_stq_idx; // @[util.scala:363:64] wire _forwarded_is_older_T_14 = _forwarded_is_older_T_12 ^ _forwarded_is_older_T_13; // @[util.scala:363:{52,58,64}] wire _forwarded_is_older_T_15 = lcam_stq_idx_0 < ldq_3_bits_youngest_stq_idx; // @[util.scala:363:78] wire forwarded_is_older_3 = _forwarded_is_older_T_14 ^ _forwarded_is_older_T_15; // @[util.scala:363:{58,72,78}] wire _T_309 = ~ldq_3_bits_forward_std_val \| l_forward_stq_idx_3 != lcam_stq_idx_0 & forwarded_is_older_3; // @[util.scala:363:72] wire _T_315 = do_ld_search_0 & ldq_3_valid & ldq_3_bits_addr_valid & ~ldq_3_bits_addr_is_virtual & dword_addr_matches_3_0 & mask_overlap_3_0; // @[lsu.scala:208:16, :263:49, :432:52, :1112:47, :1113:47, :1114:47, :1115:47, :1116:47] wire _searcher_is_older_T_12 = lcam_ldq_idx_0 < 3'h3; // @[util.scala:363:52] wire _searcher_is_older_T_14 = _searcher_is_older_T_12 ^ _searcher_is_older_T_13; // @[util.scala:363:{52,58,64}] wire searcher_is_older_3 = _searcher_is_older_T_14 ^ _searcher_is_older_T_15; // @[util.scala:363:{58,72,78}] wire _GEN_252 = _T_315 & searcher_is_older_3 & (_T_322 \| l_forwarders_3_0) & ~s1_executing_loads_3 & ldq_3_bits_observed; // @[util.scala:363:72] assign failed_loads_3 = ~_T_293 & (_T_305 ? _T_309 : _GEN_252); // @[lsu.scala:303:5, :1054:34, :1089:34, :1090:34, :1091:34, :1092:36, :1096:131, :1097:131, :1098:131, :1099:131, :1100:131, :1101:131, :1102:131, :1103:37, :1107:39, :1108:76, :1117:37, :1119:34, :1120:74, :1121:40, :1122:34, :1123:36] reg older_nacked_REG_3; // @[lsu.scala:1129:57] wire older_nacked_3 = nacking_loads_3 \| older_nacked_REG_3; // @[lsu.scala:1055:34, :1129:{47,57}] wire _T_324 = ~_T_322 \| older_nacked_3; // @[lsu.scala:1099:37, :1129:47, :1130:{17,56}] wire _GEN_253 = searcher_is_older_3 \| _GEN_236; // @[util.scala:363:72] wire _GEN_254 = _T_293 \| _T_305; // @[lsu.scala:1089:34, :1090:34, :1091:34, :1092:36, :1096:131, :1097:131, :1098:131, :1099:131, :1100:131, :1101:131, :1102:131, :1103:37, :1117:37] reg io_dmem_s1_kill_0_REG_3; // @[lsu.scala:1132:58] wire _GEN_255 = _GEN_254 \| ~_T_315 \| _GEN_253 \| ~_T_324; // @[lsu.scala:1092:36, :1103:37, :1112:47, :1113:47, :1114:47, :1115:47, :1116:47, :1117:37, :1119:34, :1126:{38,47}, :1130:{56,73}] wire [7:0] l_mask_4; // @[lsu.scala:1665:22] wire _l_mask_mask_T_60 = ldq_4_bits_uop_mem_size == 2'h0; // @[lsu.scala:208:16, :1667:26] wire [2:0] _l_mask_mask_T_61 = ldq_4_bits_addr_bits[2:0]; // @[lsu.scala:208:16, :1667:55] wire [14:0] _l_mask_mask_T_62 = 15'h1 << _l_mask_mask_T_61; // @[lsu.scala:1667:{48,55}] wire _l_mask_mask_T_63 = ldq_4_bits_uop_mem_size == 2'h1; // @[lsu.scala:208:16, :1668:26] wire [1:0] _l_mask_mask_T_64 = ldq_4_bits_addr_bits[2:1]; // @[lsu.scala:208:16, :1668:56] wire [2:0] _l_mask_mask_T_65 = {_l_mask_mask_T_64, 1'h0}; // @[lsu.scala:1668:{56,62}] wire [14:0] _l_mask_mask_T_66 = 15'h3 << _l_mask_mask_T_65; // @[lsu.scala:1668:{48,62}] wire _l_mask_mask_T_67 = ldq_4_bits_uop_mem_size == 2'h2; // @[lsu.scala:208:16, :1669:26] wire _l_mask_mask_T_68 = ldq_4_bits_addr_bits[2]; // @[lsu.scala:208:16, :1669:46] wire [7:0] _l_mask_mask_T_69 = _l_mask_mask_T_68 ? 8'hF0 : 8'hF; // @[lsu.scala:1669:{41,46}] wire _l_mask_mask_T_70 = &ldq_4_bits_uop_mem_size; // @[lsu.scala:208:16, :1670:26] wire [7:0] _l_mask_mask_T_72 = _l_mask_mask_T_67 ? _l_mask_mask_T_69 : 8'hFF; // @[Mux.scala:126:16] wire [14:0] _l_mask_mask_T_73 = _l_mask_mask_T_63 ? _l_mask_mask_T_66 : {7'h0, _l_mask_mask_T_72}; // @[Mux.scala:126:16] wire [14:0] _l_mask_mask_T_74 = _l_mask_mask_T_60 ? _l_mask_mask_T_62 : _l_mask_mask_T_73; // @[Mux.scala:126:16] assign l_mask_4 = _l_mask_mask_T_74[7:0]; // @[Mux.scala:126:16] wire _l_forwarders_T_8 = wb_forward_ldq_idx_0 == 3'h4; // @[lsu.scala:1066:36, :1076:88] wire _l_forwarders_T_9 = wb_forward_valid_0 & _l_forwarders_T_8; // @[lsu.scala:1065:36, :1076:{63,88}] wire l_forwarders_4_0 = _l_forwarders_T_9; // @[lsu.scala:263:49, :1076:63] wire [2:0] l_forward_stq_idx_4 = l_forwarders_4_0 ? wb_forward_stq_idx_0 : ldq_4_bits_forward_stq_idx; // @[lsu.scala:208:16, :263:49, :1068:36, :1078:32] wire [33:0] _block_addr_matches_T_13 = ldq_4_bits_addr_bits[39:6]; // @[lsu.scala:208:16, :1081:84] wire _block_addr_matches_T_14 = _block_addr_matches_T_12 == _block_addr_matches_T_13; // @[lsu.scala:1081:{57,73,84}] wire block_addr_matches_4_0 = _block_addr_matches_T_14; // @[lsu.scala:263:49, :1081:73] wire [2:0] _dword_addr_matches_T_17 = ldq_4_bits_addr_bits[5:3]; // @[lsu.scala:208:16, :1082:110] wire _dword_addr_matches_T_18 = _dword_addr_matches_T_16 == _dword_addr_matches_T_17; // @[lsu.scala:1082:{81,100,110}] wire _dword_addr_matches_T_19 = block_addr_matches_4_0 & _dword_addr_matches_T_18; // @[lsu.scala:263:49, :1082:{66,100}] wire dword_addr_matches_4_0 = _dword_addr_matches_T_19; // @[lsu.scala:263:49, :1082:66] wire [7:0] _GEN_256 = l_mask_4 & lcam_mask_0; // @[lsu.scala:263:49, :1083:46, :1665:22] wire [7:0] _mask_match_T_8; // @[lsu.scala:1083:46] assign _mask_match_T_8 = _GEN_256; // @[lsu.scala:1083:46] wire [7:0] _mask_overlap_T_8; // @[lsu.scala:1084:46] assign _mask_overlap_T_8 = _GEN_256; // @[lsu.scala:1083:46, :1084:46] wire _mask_match_T_9 = _mask_match_T_8 == l_mask_4; // @[lsu.scala:1083:{46,62}, :1665:22] wire mask_match_4_0 = _mask_match_T_9; // @[lsu.scala:263:49, :1083:62] wire _mask_overlap_T_9 = \|_mask_overlap_T_8; // @[lsu.scala:1084:{46,62}] wire mask_overlap_4_0 = _mask_overlap_T_9; // @[lsu.scala:263:49, :1084:62] wire _T_329 = do_release_search_0 & ldq_4_valid & ldq_4_bits_addr_valid & block_addr_matches_4_0; // @[lsu.scala:208:16, :263:49, :1089:34, :1090:34, :1091:34] wire _T_358 = ldq_4_bits_executed \| ldq_4_bits_succeeded; // @[lsu.scala:208:16, :1099:37] wire [7:0] _T_337 = ldq_4_bits_st_dep_mask >> _GEN_230; // @[lsu.scala:208:16, :1101:38] wire _T_341 = do_st_search_0 & ldq_4_valid & ldq_4_bits_addr_valid & (_T_358 \| l_forwarders_4_0) & ~ldq_4_bits_addr_is_virtual & _T_337[0] & dword_addr_matches_4_0 & mask_overlap_4_0; // @[lsu.scala:208:16, :263:49, :432:52, :1096:131, :1097:131, :1098:131, :1099:{37,57,131}, :1100:131, :1101:{38,131}, :1102:131] wire _forwarded_is_older_T_16 = l_forward_stq_idx_4 < lcam_stq_idx_0; // @[util.scala:363:52] wire _forwarded_is_older_T_17 = l_forward_stq_idx_4 < ldq_4_bits_youngest_stq_idx; // @[util.scala:363:64] wire _forwarded_is_older_T_18 = _forwarded_is_older_T_16 ^ _forwarded_is_older_T_17; // @[util.scala:363:{52,58,64}] wire _forwarded_is_older_T_19 = lcam_stq_idx_0 < ldq_4_bits_youngest_stq_idx; // @[util.scala:363:78] wire forwarded_is_older_4 = _forwarded_is_older_T_18 ^ _forwarded_is_older_T_19; // @[util.scala:363:{58,72,78}] wire _T_345 = ~ldq_4_bits_forward_std_val \| l_forward_stq_idx_4 != lcam_stq_idx_0 & forwarded_is_older_4; // @[util.scala:363:72] wire _T_351 = do_ld_search_0 & ldq_4_valid & ldq_4_bits_addr_valid & ~ldq_4_bits_addr_is_virtual & dword_addr_matches_4_0 & mask_overlap_4_0; // @[lsu.scala:208:16, :263:49, :432:52, :1112:47, :1113:47, :1114:47, :1115:47, :1116:47] wire _searcher_is_older_T_16 = ~(lcam_ldq_idx_0[2]); // @[util.scala:363:52] wire _searcher_is_older_T_18 = _searcher_is_older_T_16 ^ _searcher_is_older_T_17; // @[util.scala:363:{52,58,64}] wire _searcher_is_older_T_19 = ldq_head > 3'h4; // @[util.scala:363:78] wire searcher_is_older_4 = _searcher_is_older_T_18 ^ _searcher_is_older_T_19; // @[util.scala:363:{58,72,78}] wire _GEN_257 = _T_351 & searcher_is_older_4 & (_T_358 \| l_forwarders_4_0) & ~s1_executing_loads_4 & ldq_4_bits_observed; // @[util.scala:363:72] assign failed_loads_4 = ~_T_329 & (_T_341 ? _T_345 : _GEN_257); // @[lsu.scala:303:5, :1054:34, :1089:34, :1090:34, :1091:34, :1092:36, :1096:131, :1097:131, :1098:131, :1099:131, :1100:131, :1101:131, :1102:131, :1103:37, :1107:39, :1108:76, :1117:37, :1119:34, :1120:74, :1121:40, :1122:34, :1123:36] reg older_nacked_REG_4; // @[lsu.scala:1129:57] wire older_nacked_4 = nacking_loads_4 \| older_nacked_REG_4; // @[lsu.scala:1055:34, :1129:{47,57}] wire _T_360 = ~_T_358 \| older_nacked_4; // @[lsu.scala:1099:37, :1129:47, :1130:{17,56}] wire _GEN_258 = searcher_is_older_4 \| _GEN_237; // @[util.scala:363:72] wire _GEN_259 = _T_329 \| _T_341; // @[lsu.scala:1089:34, :1090:34, :1091:34, :1092:36, :1096:131, :1097:131, :1098:131, :1099:131, :1100:131, :1101:131, :1102:131, :1103:37, :1117:37] reg io_dmem_s1_kill_0_REG_4; // @[lsu.scala:1132:58] wire _GEN_260 = _GEN_259 \| ~_T_351 \| _GEN_258 \| ~_T_360; // @[lsu.scala:1092:36, :1103:37, :1112:47, :1113:47, :1114:47, :1115:47, :1116:47, :1117:37, :1119:34, :1126:{38,47}, :1130:{56,73}] wire [7:0] l_mask_5; // @[lsu.scala:1665:22] wire _l_mask_mask_T_75 = ldq_5_bits_uop_mem_size == 2'h0; // @[lsu.scala:208:16, :1667:26] wire [2:0] _l_mask_mask_T_76 = ldq_5_bits_addr_bits[2:0]; // @[lsu.scala:208:16, :1667:55] wire [14:0] _l_mask_mask_T_77 = 15'h1 << _l_mask_mask_T_76; // @[lsu.scala:1667:{48,55}] wire _l_mask_mask_T_78 = ldq_5_bits_uop_mem_size == 2'h1; // @[lsu.scala:208:16, :1668:26] wire [1:0] _l_mask_mask_T_79 = ldq_5_bits_addr_bits[2:1]; // @[lsu.scala:208:16, :1668:56] wire [2:0] _l_mask_mask_T_80 = {_l_mask_mask_T_79, 1'h0}; // @[lsu.scala:1668:{56,62}] wire [14:0] _l_mask_mask_T_81 = 15'h3 << _l_mask_mask_T_80; // @[lsu.scala:1668:{48,62}] wire _l_mask_mask_T_82 = ldq_5_bits_uop_mem_size == 2'h2; // @[lsu.scala:208:16, :1669:26] wire _l_mask_mask_T_83 = ldq_5_bits_addr_bits[2]; // @[lsu.scala:208:16, :1669:46] wire [7:0] _l_mask_mask_T_84 = _l_mask_mask_T_83 ? 8'hF0 : 8'hF; // @[lsu.scala:1669:{41,46}] wire _l_mask_mask_T_85 = &ldq_5_bits_uop_mem_size; // @[lsu.scala:208:16, :1670:26] wire [7:0] _l_mask_mask_T_87 = _l_mask_mask_T_82 ? _l_mask_mask_T_84 : 8'hFF; // @[Mux.scala:126:16] wire [14:0] _l_mask_mask_T_88 = _l_mask_mask_T_78 ? _l_mask_mask_T_81 : {7'h0, _l_mask_mask_T_87}; // @[Mux.scala:126:16] wire [14:0] _l_mask_mask_T_89 = _l_mask_mask_T_75 ? _l_mask_mask_T_77 : _l_mask_mask_T_88; // @[Mux.scala:126:16] assign l_mask_5 = _l_mask_mask_T_89[7:0]; // @[Mux.scala:126:16] wire _l_forwarders_T_10 = wb_forward_ldq_idx_0 == 3'h5; // @[lsu.scala:1066:36, :1076:88] wire _l_forwarders_T_11 = wb_forward_valid_0 & _l_forwarders_T_10; // @[lsu.scala:1065:36, :1076:{63,88}] wire l_forwarders_5_0 = _l_forwarders_T_11; // @[lsu.scala:263:49, :1076:63] wire [2:0] l_forward_stq_idx_5 = l_forwarders_5_0 ? wb_forward_stq_idx_0 : ldq_5_bits_forward_stq_idx; // @[lsu.scala:208:16, :263:49, :1068:36, :1078:32] wire [33:0] _block_addr_matches_T_16 = ldq_5_bits_addr_bits[39:6]; // @[lsu.scala:208:16, :1081:84] wire _block_addr_matches_T_17 = _block_addr_matches_T_15 == _block_addr_matches_T_16; // @[lsu.scala:1081:{57,73,84}] wire block_addr_matches_5_0 = _block_addr_matches_T_17; // @[lsu.scala:263:49, :1081:73] wire [2:0] _dword_addr_matches_T_21 = ldq_5_bits_addr_bits[5:3]; // @[lsu.scala:208:16, :1082:110] wire _dword_addr_matches_T_22 = _dword_addr_matches_T_20 == _dword_addr_matches_T_21; // @[lsu.scala:1082:{81,100,110}] wire _dword_addr_matches_T_23 = block_addr_matches_5_0 & _dword_addr_matches_T_22; // @[lsu.scala:263:49, :1082:{66,100}] wire dword_addr_matches_5_0 = _dword_addr_matches_T_23; // @[lsu.scala:263:49, :1082:66] wire [7:0] _GEN_261 = l_mask_5 & lcam_mask_0; // @[lsu.scala:263:49, :1083:46, :1665:22] wire [7:0] _mask_match_T_10; // @[lsu.scala:1083:46] assign _mask_match_T_10 = _GEN_261; // @[lsu.scala:1083:46] wire [7:0] _mask_overlap_T_10; // @[lsu.scala:1084:46] assign _mask_overlap_T_10 = _GEN_261; // @[lsu.scala:1083:46, :1084:46] wire _mask_match_T_11 = _mask_match_T_10 == l_mask_5; // @[lsu.scala:1083:{46,62}, :1665:22] wire mask_match_5_0 = _mask_match_T_11; // @[lsu.scala:263:49, :1083:62] wire _mask_overlap_T_11 = \|_mask_overlap_T_10; // @[lsu.scala:1084:{46,62}] wire mask_overlap_5_0 = _mask_overlap_T_11; // @[lsu.scala:263:49, :1084:62] wire _T_365 = do_release_search_0 & ldq_5_valid & ldq_5_bits_addr_valid & block_addr_matches_5_0; // @[lsu.scala:208:16, :263:49, :1089:34, :1090:34, :1091:34] wire _T_394 = ldq_5_bits_executed \| ldq_5_bits_succeeded; // @[lsu.scala:208:16, :1099:37] wire [7:0] _T_373 = ldq_5_bits_st_dep_mask >> _GEN_230; // @[lsu.scala:208:16, :1101:38] wire _T_377 = do_st_search_0 & ldq_5_valid & ldq_5_bits_addr_valid & (_T_394 \| l_forwarders_5_0) & ~ldq_5_bits_addr_is_virtual & _T_373[0] & dword_addr_matches_5_0 & mask_overlap_5_0; // @[lsu.scala:208:16, :263:49, :432:52, :1096:131, :1097:131, :1098:131, :1099:{37,57,131}, :1100:131, :1101:{38,131}, :1102:131] wire _forwarded_is_older_T_20 = l_forward_stq_idx_5 < lcam_stq_idx_0; // @[util.scala:363:52] wire _forwarded_is_older_T_21 = l_forward_stq_idx_5 < ldq_5_bits_youngest_stq_idx; // @[util.scala:363:64] wire _forwarded_is_older_T_22 = _forwarded_is_older_T_20 ^ _forwarded_is_older_T_21; // @[util.scala:363:{52,58,64}] wire _forwarded_is_older_T_23 = lcam_stq_idx_0 < ldq_5_bits_youngest_stq_idx; // @[util.scala:363:78] wire forwarded_is_older_5 = _forwarded_is_older_T_22 ^ _forwarded_is_older_T_23; // @[util.scala:363:{58,72,78}] wire _T_381 = ~ldq_5_bits_forward_std_val \| l_forward_stq_idx_5 != lcam_stq_idx_0 & forwarded_is_older_5; // @[util.scala:363:72] wire _T_387 = do_ld_search_0 & ldq_5_valid & ldq_5_bits_addr_valid & ~ldq_5_bits_addr_is_virtual & dword_addr_matches_5_0 & mask_overlap_5_0; // @[lsu.scala:208:16, :263:49, :432:52, :1112:47, :1113:47, :1114:47, :1115:47, :1116:47] wire _searcher_is_older_T_20 = lcam_ldq_idx_0 < 3'h5; // @[util.scala:363:52] wire _searcher_is_older_T_22 = _searcher_is_older_T_20 ^ _searcher_is_older_T_21; // @[util.scala:363:{52,58,64}] wire _searcher_is_older_T_23 = ldq_head > 3'h5; // @[util.scala:363:78] wire searcher_is_older_5 = _searcher_is_older_T_22 ^ _searcher_is_older_T_23; // @[util.scala:363:{58,72,78}] wire _GEN_262 = _T_387 & searcher_is_older_5 & (_T_394 \| l_forwarders_5_0) & ~s1_executing_loads_5 & ldq_5_bits_observed; // @[util.scala:363:72] assign failed_loads_5 = ~_T_365 & (_T_377 ? _T_381 : _GEN_262); // @[lsu.scala:303:5, :1054:34, :1089:34, :1090:34, :1091:34, :1092:36, :1096:131, :1097:131, :1098:131, :1099:131, :1100:131, :1101:131, :1102:131, :1103:37, :1107:39, :1108:76, :1117:37, :1119:34, :1120:74, :1121:40, :1122:34, :1123:36] reg older_nacked_REG_5; // @[lsu.scala:1129:57] wire older_nacked_5 = nacking_loads_5 \| older_nacked_REG_5; // @[lsu.scala:1055:34, :1129:{47,57}] wire _T_396 = ~_T_394 \| older_nacked_5; // @[lsu.scala:1099:37, :1129:47, :1130:{17,56}] wire _GEN_263 = searcher_is_older_5 \| _GEN_238; // @[util.scala:363:72] wire _GEN_264 = _T_365 \| _T_377; // @[lsu.scala:1089:34, :1090:34, :1091:34, :1092:36, :1096:131, :1097:131, :1098:131, :1099:131, :1100:131, :1101:131, :1102:131, :1103:37, :1117:37] reg io_dmem_s1_kill_0_REG_5; // @[lsu.scala:1132:58] wire _GEN_265 = _GEN_264 \| ~_T_387 \| _GEN_263 \| ~_T_396; // @[lsu.scala:1092:36, :1103:37, :1112:47, :1113:47, :1114:47, :1115:47, :1116:47, :1117:37, :1119:34, :1126:{38,47}, :1130:{56,73}] wire [7:0] l_mask_6; // @[lsu.scala:1665:22] wire _l_mask_mask_T_90 = ldq_6_bits_uop_mem_size == 2'h0; // @[lsu.scala:208:16, :1667:26] wire [2:0] _l_mask_mask_T_91 = ldq_6_bits_addr_bits[2:0]; // @[lsu.scala:208:16, :1667:55] wire [14:0] _l_mask_mask_T_92 = 15'h1 << _l_mask_mask_T_91; // @[lsu.scala:1667:{48,55}] wire _l_mask_mask_T_93 = ldq_6_bits_uop_mem_size == 2'h1; // @[lsu.scala:208:16, :1668:26] wire [1:0] _l_mask_mask_T_94 = ldq_6_bits_addr_bits[2:1]; // @[lsu.scala:208:16, :1668:56] wire [2:0] _l_mask_mask_T_95 = {_l_mask_mask_T_94, 1'h0}; // @[lsu.scala:1668:{56,62}] wire [14:0] _l_mask_mask_T_96 = 15'h3 << _l_mask_mask_T_95; // @[lsu.scala:1668:{48,62}] wire _l_mask_mask_T_97 = ldq_6_bits_uop_mem_size == 2'h2; // @[lsu.scala:208:16, :1669:26] wire _l_mask_mask_T_98 = ldq_6_bits_addr_bits[2]; // @[lsu.scala:208:16, :1669:46] wire [7:0] _l_mask_mask_T_99 = _l_mask_mask_T_98 ? 8'hF0 : 8'hF; // @[lsu.scala:1669:{41,46}] wire _l_mask_mask_T_100 = &ldq_6_bits_uop_mem_size; // @[lsu.scala:208:16, :1670:26] wire [7:0] _l_mask_mask_T_102 = _l_mask_mask_T_97 ? _l_mask_mask_T_99 : 8'hFF; // @[Mux.scala:126:16] wire [14:0] _l_mask_mask_T_103 = _l_mask_mask_T_93 ? _l_mask_mask_T_96 : {7'h0, _l_mask_mask_T_102}; // @[Mux.scala:126:16] wire [14:0] _l_mask_mask_T_104 = _l_mask_mask_T_90 ? _l_mask_mask_T_92 : _l_mask_mask_T_103; // @[Mux.scala:126:16] assign l_mask_6 = _l_mask_mask_T_104[7:0]; // @[Mux.scala:126:16] wire _l_forwarders_T_12 = wb_forward_ldq_idx_0 == 3'h6; // @[lsu.scala:1066:36, :1076:88] wire _l_forwarders_T_13 = wb_forward_valid_0 & _l_forwarders_T_12; // @[lsu.scala:1065:36, :1076:{63,88}] wire l_forwarders_6_0 = _l_forwarders_T_13; // @[lsu.scala:263:49, :1076:63] wire [2:0] l_forward_stq_idx_6 = l_forwarders_6_0 ? wb_forward_stq_idx_0 : ldq_6_bits_forward_stq_idx; // @[lsu.scala:208:16, :263:49, :1068:36, :1078:32] wire [33:0] _block_addr_matches_T_19 = ldq_6_bits_addr_bits[39:6]; // @[lsu.scala:208:16, :1081:84] wire _block_addr_matches_T_20 = _block_addr_matches_T_18 == _block_addr_matches_T_19; // @[lsu.scala:1081:{57,73,84}] wire block_addr_matches_6_0 = _block_addr_matches_T_20; // @[lsu.scala:263:49, :1081:73] wire [2:0] _dword_addr_matches_T_25 = ldq_6_bits_addr_bits[5:3]; // @[lsu.scala:208:16, :1082:110] wire _dword_addr_matches_T_26 = _dword_addr_matches_T_24 == _dword_addr_matches_T_25; // @[lsu.scala:1082:{81,100,110}] wire _dword_addr_matches_T_27 = block_addr_matches_6_0 & _dword_addr_matches_T_26; // @[lsu.scala:263:49, :1082:{66,100}] wire dword_addr_matches_6_0 = _dword_addr_matches_T_27; // @[lsu.scala:263:49, :1082:66] wire [7:0] _GEN_266 = l_mask_6 & lcam_mask_0; // @[lsu.scala:263:49, :1083:46, :1665:22] wire [7:0] _mask_match_T_12; // @[lsu.scala:1083:46] assign _mask_match_T_12 = _GEN_266; // @[lsu.scala:1083:46] wire [7:0] _mask_overlap_T_12; // @[lsu.scala:1084:46] assign _mask_overlap_T_12 = _GEN_266; // @[lsu.scala:1083:46, :1084:46] wire _mask_match_T_13 = _mask_match_T_12 == l_mask_6; // @[lsu.scala:1083:{46,62}, :1665:22] wire mask_match_6_0 = _mask_match_T_13; // @[lsu.scala:263:49, :1083:62] wire _mask_overlap_T_13 = \|_mask_overlap_T_12; // @[lsu.scala:1084:{46,62}] wire mask_overlap_6_0 = _mask_overlap_T_13; // @[lsu.scala:263:49, :1084:62] wire _T_401 = do_release_search_0 & ldq_6_valid & ldq_6_bits_addr_valid & block_addr_matches_6_0; // @[lsu.scala:208:16, :263:49, :1089:34, :1090:34, :1091:34] wire _T_430 = ldq_6_bits_executed \| ldq_6_bits_succeeded; // @[lsu.scala:208:16, :1099:37] wire [7:0] _T_409 = ldq_6_bits_st_dep_mask >> _GEN_230; // @[lsu.scala:208:16, :1101:38] wire _T_413 = do_st_search_0 & ldq_6_valid & ldq_6_bits_addr_valid & (_T_430 \| l_forwarders_6_0) & ~ldq_6_bits_addr_is_virtual & _T_409[0] & dword_addr_matches_6_0 & mask_overlap_6_0; // @[lsu.scala:208:16, :263:49, :432:52, :1096:131, :1097:131, :1098:131, :1099:{37,57,131}, :1100:131, :1101:{38,131}, :1102:131] wire _forwarded_is_older_T_24 = l_forward_stq_idx_6 < lcam_stq_idx_0; // @[util.scala:363:52] wire _forwarded_is_older_T_25 = l_forward_stq_idx_6 < ldq_6_bits_youngest_stq_idx; // @[util.scala:363:64] wire _forwarded_is_older_T_26 = _forwarded_is_older_T_24 ^ _forwarded_is_older_T_25; // @[util.scala:363:{52,58,64}] wire _forwarded_is_older_T_27 = lcam_stq_idx_0 < ldq_6_bits_youngest_stq_idx; // @[util.scala:363:78] wire forwarded_is_older_6 = _forwarded_is_older_T_26 ^ _forwarded_is_older_T_27; // @[util.scala:363:{58,72,78}] wire _T_417 = ~ldq_6_bits_forward_std_val \| l_forward_stq_idx_6 != lcam_stq_idx_0 & forwarded_is_older_6; // @[util.scala:363:72] wire _T_423 = do_ld_search_0 & ldq_6_valid & ldq_6_bits_addr_valid & ~ldq_6_bits_addr_is_virtual & dword_addr_matches_6_0 & mask_overlap_6_0; // @[lsu.scala:208:16, :263:49, :432:52, :1112:47, :1113:47, :1114:47, :1115:47, :1116:47] wire _searcher_is_older_T_24 = lcam_ldq_idx_0[2:1] != 2'h3; // @[util.scala:363:52] wire _searcher_is_older_T_26 = _searcher_is_older_T_24 ^ _searcher_is_older_T_25; // @[util.scala:363:{52,58,64}] wire _searcher_is_older_T_27 = &ldq_head; // @[util.scala:363:78] wire searcher_is_older_6 = _searcher_is_older_T_26 ^ _searcher_is_older_T_27; // @[util.scala:363:{58,72,78}] wire _GEN_267 = _T_423 & searcher_is_older_6 & (_T_430 \| l_forwarders_6_0) & ~s1_executing_loads_6 & ldq_6_bits_observed; // @[util.scala:363:72] assign failed_loads_6 = ~_T_401 & (_T_413 ? _T_417 : _GEN_267); // @[lsu.scala:303:5, :1054:34, :1089:34, :1090:34, :1091:34, :1092:36, :1096:131, :1097:131, :1098:131, :1099:131, :1100:131, :1101:131, :1102:131, :1103:37, :1107:39, :1108:76, :1117:37, :1119:34, :1120:74, :1121:40, :1122:34, :1123:36] reg older_nacked_REG_6; // @[lsu.scala:1129:57] wire older_nacked_6 = nacking_loads_6 \| older_nacked_REG_6; // @[lsu.scala:1055:34, :1129:{47,57}] wire _T_432 = ~_T_430 \| older_nacked_6; // @[lsu.scala:1099:37, :1129:47, :1130:{17,56}] wire _GEN_268 = searcher_is_older_6 \| _GEN_239; // @[util.scala:363:72] wire _GEN_269 = _T_401 \| _T_413; // @[lsu.scala:1089:34, :1090:34, :1091:34, :1092:36, :1096:131, :1097:131, :1098:131, :1099:131, :1100:131, :1101:131, :1102:131, :1103:37, :1117:37] wire _GEN_270 = (_GEN_269 \| ~_T_423 \| _GEN_268 \| ~(_T_432 & (&lcam_ldq_idx_0))) & (_GEN_264 \| ~_T_387 \| _GEN_263 \| ~(_T_396 & (&lcam_ldq_idx_0))) & (_GEN_259 \| ~_T_351 \| _GEN_258 \| ~(_T_360 & (&lcam_ldq_idx_0))) & (_GEN_254 \| ~_T_315 \| _GEN_253 \| ~(_T_324 & (&lcam_ldq_idx_0))) & (_GEN_249 \| ~_T_279 \| _GEN_248 \| ~(_T_288 & (&lcam_ldq_idx_0))) & (_GEN_244 \| ~_T_243 \| _GEN_243 \| ~(_T_252 & (&lcam_ldq_idx_0))) & (_GEN_233 \| ~_T_207 \| searcher_is_older \| ~((\|lcam_ldq_idx_0) & _T_216 & (&lcam_ldq_idx_0))) & s1_executing_loads_7; // @[util.scala:363:72] reg io_dmem_s1_kill_0_REG_6; // @[lsu.scala:1132:58] wire _GEN_271 = _GEN_269 \| ~_T_423 \| _GEN_268 \| ~_T_432; // @[lsu.scala:1092:36, :1103:37, :1112:47, :1113:47, :1114:47, :1115:47, :1116:47, :1117:37, :1119:34, :1126:{38,47}, :1130:{56,73}] wire [7:0] l_mask_7; // @[lsu.scala:1665:22] wire _l_mask_mask_T_105 = ldq_7_bits_uop_mem_size == 2'h0; // @[lsu.scala:208:16, :1667:26] wire [2:0] _l_mask_mask_T_106 = ldq_7_bits_addr_bits[2:0]; // @[lsu.scala:208:16, :1667:55] wire [14:0] _l_mask_mask_T_107 = 15'h1 << _l_mask_mask_T_106; // @[lsu.scala:1667:{48,55}] wire _l_mask_mask_T_108 = ldq_7_bits_uop_mem_size == 2'h1; // @[lsu.scala:208:16, :1668:26] wire [1:0] _l_mask_mask_T_109 = ldq_7_bits_addr_bits[2:1]; // @[lsu.scala:208:16, :1668:56] wire [2:0] _l_mask_mask_T_110 = {_l_mask_mask_T_109, 1'h0}; // @[lsu.scala:1668:{56,62}] wire [14:0] _l_mask_mask_T_111 = 15'h3 << _l_mask_mask_T_110; // @[lsu.scala:1668:{48,62}] wire _l_mask_mask_T_112 = ldq_7_bits_uop_mem_size == 2'h2; // @[lsu.scala:208:16, :1669:26] wire _l_mask_mask_T_113 = ldq_7_bits_addr_bits[2]; // @[lsu.scala:208:16, :1669:46] wire [7:0] _l_mask_mask_T_114 = _l_mask_mask_T_113 ? 8'hF0 : 8'hF; // @[lsu.scala:1669:{41,46}] wire _l_mask_mask_T_115 = &ldq_7_bits_uop_mem_size; // @[lsu.scala:208:16, :1670:26] wire [7:0] _l_mask_mask_T_117 = _l_mask_mask_T_112 ? _l_mask_mask_T_114 : 8'hFF; // @[Mux.scala:126:16] wire [14:0] _l_mask_mask_T_118 = _l_mask_mask_T_108 ? _l_mask_mask_T_111 : {7'h0, _l_mask_mask_T_117}; // @[Mux.scala:126:16] wire [14:0] _l_mask_mask_T_119 = _l_mask_mask_T_105 ? _l_mask_mask_T_107 : _l_mask_mask_T_118; // @[Mux.scala:126:16] assign l_mask_7 = _l_mask_mask_T_119[7:0]; // @[Mux.scala:126:16] wire _l_forwarders_T_14 = &wb_forward_ldq_idx_0; // @[lsu.scala:1066:36, :1076:88] wire _l_forwarders_T_15 = wb_forward_valid_0 & _l_forwarders_T_14; // @[lsu.scala:1065:36, :1076:{63,88}] wire l_forwarders_7_0 = _l_forwarders_T_15; // @[lsu.scala:263:49, :1076:63] wire [2:0] l_forward_stq_idx_7 = l_forwarders_7_0 ? wb_forward_stq_idx_0 : ldq_7_bits_forward_stq_idx; // @[lsu.scala:208:16, :263:49, :1068:36, :1078:32] wire [33:0] _block_addr_matches_T_22 = ldq_7_bits_addr_bits[39:6]; // @[lsu.scala:208:16, :1081:84] wire _block_addr_matches_T_23 = _block_addr_matches_T_21 == _block_addr_matches_T_22; // @[lsu.scala:1081:{57,73,84}] wire block_addr_matches_7_0 = _block_addr_matches_T_23; // @[lsu.scala:263:49, :1081:73] wire [2:0] _dword_addr_matches_T_29 = ldq_7_bits_addr_bits[5:3]; // @[lsu.scala:208:16, :1082:110] wire _dword_addr_matches_T_30 = _dword_addr_matches_T_28 == _dword_addr_matches_T_29; // @[lsu.scala:1082:{81,100,110}] wire _dword_addr_matches_T_31 = block_addr_matches_7_0 & _dword_addr_matches_T_30; // @[lsu.scala:263:49, :1082:{66,100}] wire dword_addr_matches_7_0 = _dword_addr_matches_T_31; // @[lsu.scala:263:49, :1082:66] wire [7:0] _GEN_272 = l_mask_7 & lcam_mask_0; // @[lsu.scala:263:49, :1083:46, :1665:22] wire [7:0] _mask_match_T_14; // @[lsu.scala:1083:46] assign _mask_match_T_14 = _GEN_272; // @[lsu.scala:1083:46] wire [7:0] _mask_overlap_T_14; // @[lsu.scala:1084:46] assign _mask_overlap_T_14 = _GEN_272; // @[lsu.scala:1083:46, :1084:46] wire _mask_match_T_15 = _mask_match_T_14 == l_mask_7; // @[lsu.scala:1083:{46,62}, :1665:22] wire mask_match_7_0 = _mask_match_T_15; // @[lsu.scala:263:49, :1083:62] wire _mask_overlap_T_15 = \|_mask_overlap_T_14; // @[lsu.scala:1084:{46,62}] wire mask_overlap_7_0 = _mask_overlap_T_15; // @[lsu.scala:263:49, :1084:62] wire _T_437 = do_release_search_0 & ldq_7_valid & ldq_7_bits_addr_valid & block_addr_matches_7_0; // @[lsu.scala:208:16, :263:49, :1089:34, :1090:34, :1091:34] wire _T_466 = ldq_7_bits_executed \| ldq_7_bits_succeeded; // @[lsu.scala:208:16, :1099:37] wire [7:0] _T_445 = ldq_7_bits_st_dep_mask >> _GEN_230; // @[lsu.scala:208:16, :1101:38] wire _T_449 = do_st_search_0 & ldq_7_valid & ldq_7_bits_addr_valid & (_T_466 \| l_forwarders_7_0) & ~ldq_7_bits_addr_is_virtual & _T_445[0] & dword_addr_matches_7_0 & mask_overlap_7_0; // @[lsu.scala:208:16, :263:49, :432:52, :1096:131, :1097:131, :1098:131, :1099:{37,57,131}, :1100:131, :1101:{38,131}, :1102:131] wire _forwarded_is_older_T_28 = l_forward_stq_idx_7 < lcam_stq_idx_0; // @[util.scala:363:52] wire _forwarded_is_older_T_29 = l_forward_stq_idx_7 < ldq_7_bits_youngest_stq_idx; // @[util.scala:363:64] wire _forwarded_is_older_T_30 = _forwarded_is_older_T_28 ^ _forwarded_is_older_T_29; // @[util.scala:363:{52,58,64}] wire _forwarded_is_older_T_31 = lcam_stq_idx_0 < ldq_7_bits_youngest_stq_idx; // @[util.scala:363:78] wire forwarded_is_older_7 = _forwarded_is_older_T_30 ^ _forwarded_is_older_T_31; // @[util.scala:363:{58,72,78}] wire _T_453 = ~ldq_7_bits_forward_std_val \| l_forward_stq_idx_7 != lcam_stq_idx_0 & forwarded_is_older_7; // @[util.scala:363:72] wire _T_459 = do_ld_search_0 & ldq_7_valid & ldq_7_bits_addr_valid & ~ldq_7_bits_addr_is_virtual & dword_addr_matches_7_0 & mask_overlap_7_0; // @[lsu.scala:208:16, :263:49, :432:52, :1112:47, :1113:47, :1114:47, :1115:47, :1116:47] wire _searcher_is_older_T_28 = lcam_ldq_idx_0 != 3'h7; // @[util.scala:363:52] wire _searcher_is_older_T_30 = _searcher_is_older_T_28 ^ _searcher_is_older_T_29; // @[util.scala:363:{52,58,64}] wire searcher_is_older_7 = _searcher_is_older_T_30; // @[util.scala:363:{58,72}] wire _GEN_273 = _T_459 & searcher_is_older_7 & (_T_466 \| l_forwarders_7_0) & ~s1_executing_loads_7 & ldq_7_bits_observed; // @[util.scala:363:72] assign failed_loads_7 = ~_T_437 & (_T_449 ? _T_453 : _GEN_273); // @[lsu.scala:303:5, :1054:34, :1089:34, :1090:34, :1091:34, :1092:36, :1096:131, :1097:131, :1098:131, :1099:131, :1100:131, :1101:131, :1102:131, :1103:37, :1107:39, :1108:76, :1117:37, :1119:34, :1120:74, :1121:40, :1122:34, :1123:36] reg older_nacked_REG_7; // @[lsu.scala:1129:57] wire older_nacked_7 = nacking_loads_7 \| older_nacked_REG_7; // @[lsu.scala:1055:34, :1129:{47,57}] wire _T_468 = ~_T_466 \| older_nacked_7; // @[lsu.scala:1099:37, :1129:47, :1130:{17,56}] wire _GEN_274 = _T_437 \| _T_449; // @[lsu.scala:1089:34, :1090:34, :1091:34, :1092:36, :1096:131, :1097:131, :1098:131, :1099:131, :1100:131, :1101:131, :1102:131, :1103:37, :1117:37] wire _GEN_275 = (_GEN_274 \| ~_T_459 \| searcher_is_older_7 \| ~(~(&lcam_ldq_idx_0) & _T_468 & _searcher_is_older_T_4)) & (_GEN_269 \| ~_T_423 \| _GEN_268 \| ~(_T_432 & _searcher_is_older_T_4)) & (_GEN_264 \| ~_T_387 \| _GEN_263 \| ~(_T_396 & _searcher_is_older_T_4)) & (_GEN_259 \| ~_T_351 \| _GEN_258 \| ~(_T_360 & _searcher_is_older_T_4)) & (_GEN_254 \| ~_T_315 \| _GEN_253 \| ~(_T_324 & _searcher_is_older_T_4)) & (_GEN_249 \| ~_T_279 \| _GEN_248 \| ~(_T_288 & _searcher_is_older_T_4)) & (_GEN_244 \| ~_T_243 \| _GEN_243 \| ~(_T_252 & _searcher_is_older_T_4)) & s1_executing_loads_0; // @[util.scala:363:{52,72}] wire _GEN_276 = (_GEN_274 \| ~_T_459 \| searcher_is_older_7 \| ~(~(&lcam_ldq_idx_0) & _T_468 & _GEN_234)) & (_GEN_269 \| ~_T_423 \| _GEN_268 \| ~(_T_432 & _GEN_234)) & (_GEN_264 \| ~_T_387 \| _GEN_263 \| ~(_T_396 & _GEN_234)) & (_GEN_259 \| ~_T_351 \| _GEN_258 \| ~(_T_360 & _GEN_234)) & (_GEN_254 \| ~_T_315 \| _GEN_253 \| ~(_T_324 & _GEN_234)) & (_GEN_249 \| ~_T_279 \| _GEN_248 \| ~(_T_288 & _GEN_234)) & (_GEN_244 \| ~_T_243 \| _GEN_243 \| ~(_T_252 & _GEN_234)) & (_GEN_233 \| ~_T_207 \| searcher_is_older \| ~((\|lcam_ldq_idx_0) & _T_216 & _GEN_234)) & s1_executing_loads_1; // @[util.scala:363:72] wire _GEN_277 = (_GEN_274 \| ~_T_459 \| searcher_is_older_7 \| ~(~(&lcam_ldq_idx_0) & _T_468 & _GEN_235)) & (_GEN_269 \| ~_T_423 \| _GEN_268 \| ~(_T_432 & _GEN_235)) & (_GEN_264 \| ~_T_387 \| _GEN_263 \| ~(_T_396 & _GEN_235)) & (_GEN_259 \| ~_T_351 \| _GEN_258 \| ~(_T_360 & _GEN_235)) & (_GEN_254 \| ~_T_315 \| _GEN_253 \| ~(_T_324 & _GEN_235)) & (_GEN_249 \| ~_T_279 \| _GEN_248 \| ~(_T_288 & _GEN_235)) & (_GEN_244 \| ~_T_243 \| _GEN_243 \| ~(_T_252 & _GEN_235)) & (_GEN_233 \| ~_T_207 \| searcher_is_older \| ~((\|lcam_ldq_idx_0) & _T_216 & _GEN_235)) & s1_executing_loads_2; // @[util.scala:363:72] wire _GEN_278 = (_GEN_274 \| ~_T_459 \| searcher_is_older_7 \| ~(~(&lcam_ldq_idx_0) & _T_468 & _GEN_236)) & (_GEN_269 \| ~_T_423 \| _GEN_268 \| ~(_T_432 & _GEN_236)) & (_GEN_264 \| ~_T_387 \| _GEN_263 \| ~(_T_396 & _GEN_236)) & (_GEN_259 \| ~_T_351 \| _GEN_258 \| ~(_T_360 & _GEN_236)) & (_GEN_254 \| ~_T_315 \| _GEN_253 \| ~(_T_324 & _GEN_236)) & (_GEN_249 \| ~_T_279 \| _GEN_248 \| ~(_T_288 & _GEN_236)) & (_GEN_244 \| ~_T_243 \| _GEN_243 \| ~(_T_252 & _GEN_236)) & (_GEN_233 \| ~_T_207 \| searcher_is_older \| ~((\|lcam_ldq_idx_0) & _T_216 & _GEN_236)) & s1_executing_loads_3; // @[util.scala:363:72] wire _GEN_279 = (_GEN_274 \| ~_T_459 \| searcher_is_older_7 \| ~(~(&lcam_ldq_idx_0) & _T_468 & _GEN_237)) & (_GEN_269 \| ~_T_423 \| _GEN_268 \| ~(_T_432 & _GEN_237)) & (_GEN_264 \| ~_T_387 \| _GEN_263 \| ~(_T_396 & _GEN_237)) & (_GEN_259 \| ~_T_351 \| _GEN_258 \| ~(_T_360 & _GEN_237)) & (_GEN_254 \| ~_T_315 \| _GEN_253 \| ~(_T_324 & _GEN_237)) & (_GEN_249 \| ~_T_279 \| _GEN_248 \| ~(_T_288 & _GEN_237)) & (_GEN_244 \| ~_T_243 \| _GEN_243 \| ~(_T_252 & _GEN_237)) & (_GEN_233 \| ~_T_207 \| searcher_is_older \| ~((\|lcam_ldq_idx_0) & _T_216 & _GEN_237)) & s1_executing_loads_4; // @[util.scala:363:72] wire _GEN_280 = (_GEN_274 \| ~_T_459 \| searcher_is_older_7 \| ~(~(&lcam_ldq_idx_0) & _T_468 & _GEN_238)) & (_GEN_269 \| ~_T_423 \| _GEN_268 \| ~(_T_432 & _GEN_238)) & (_GEN_264 \| ~_T_387 \| _GEN_263 \| ~(_T_396 & _GEN_238)) & (_GEN_259 \| ~_T_351 \| _GEN_258 \| ~(_T_360 & _GEN_238)) & (_GEN_254 \| ~_T_315 \| _GEN_253 \| ~(_T_324 & _GEN_238)) & (_GEN_249 \| ~_T_279 \| _GEN_248 \| ~(_T_288 & _GEN_238)) & (_GEN_244 \| ~_T_243 \| _GEN_243 \| ~(_T_252 & _GEN_238)) & (_GEN_233 \| ~_T_207 \| searcher_is_older \| ~((\|lcam_ldq_idx_0) & _T_216 & _GEN_238)) & s1_executing_loads_5; // @[util.scala:363:72] wire _GEN_281 = (_GEN_274 \| ~_T_459 \| searcher_is_older_7 \| ~(~(&lcam_ldq_idx_0) & _T_468 & _GEN_239)) & (_GEN_269 \| ~_T_423 \| _GEN_268 \| ~(_T_432 & _GEN_239)) & (_GEN_264 \| ~_T_387 \| _GEN_263 \| ~(_T_396 & _GEN_239)) & (_GEN_259 \| ~_T_351 \| _GEN_258 \| ~(_T_360 & _GEN_239)) & (_GEN_254 \| ~_T_315 \| _GEN_253 \| ~(_T_324 & _GEN_239)) & (_GEN_249 \| ~_T_279 \| _GEN_248 \| ~(_T_288 & _GEN_239)) & (_GEN_244 \| ~_T_243 \| _GEN_243 \| ~(_T_252 & _GEN_239)) & (_GEN_233 \| ~_T_207 \| searcher_is_older \| ~((\|lcam_ldq_idx_0) & _T_216 & _GEN_239)) & s1_executing_loads_6; // @[util.scala:363:72] reg io_dmem_s1_kill_0_REG_7; // @[lsu.scala:1132:58] wire _GEN_282 = _GEN_274 \| ~_T_459 \| searcher_is_older_7 \| ~(~(&lcam_ldq_idx_0) & _T_468); // @[util.scala:363:72] wire _GEN_283 = _GEN_282 ? (_GEN_271 ? (_GEN_265 ? (_GEN_260 ? (_GEN_255 ? (_GEN_250 ? (_GEN_245 ? ~_GEN_233 & _T_207 & ~searcher_is_older & _GEN_240 & io_dmem_s1_kill_0_REG : io_dmem_s1_kill_0_REG_1) : io_dmem_s1_kill_0_REG_2) : io_dmem_s1_kill_0_REG_3) : io_dmem_s1_kill_0_REG_4) : io_dmem_s1_kill_0_REG_5) : io_dmem_s1_kill_0_REG_6) : io_dmem_s1_kill_0_REG_7; // @[util.scala:363:72] assign can_forward_0 = _GEN_282 & _GEN_271 & _GEN_265 & _GEN_260 & _GEN_255 & _GEN_250 & _GEN_245 & (_GEN_233 \| ~_T_207 \| searcher_is_older \| ~_GEN_240) & _can_forward_WIRE_0; // @[util.scala:363:72] wire _dword_addr_matches_T_32 = ~stq_0_bits_addr_is_virtual; // @[lsu.scala:209:16, :1145:31] wire _dword_addr_matches_T_33 = stq_0_bits_addr_valid & _dword_addr_matches_T_32; // @[lsu.scala:209:16, :1144:60, :1145:31] wire [28:0] _dword_addr_matches_T_34 = stq_0_bits_addr_bits[31:3]; // @[lsu.scala:209:16, :1146:38] wire [28:0] _dword_addr_matches_T_35 = lcam_addr_0[31:3]; // @[lsu.scala:263:49, :1146:74] wire [28:0] _dword_addr_matches_T_41 = lcam_addr_0[31:3]; // @[lsu.scala:263:49, :1146:74] wire [28:0] _dword_addr_matches_T_47 = lcam_addr_0[31:3]; // @[lsu.scala:263:49, :1146:74] wire [28:0] _dword_addr_matches_T_53 = lcam_addr_0[31:3]; // @[lsu.scala:263:49, :1146:74] wire [28:0] _dword_addr_matches_T_59 = lcam_addr_0[31:3]; // @[lsu.scala:263:49, :1146:74] wire [28:0] _dword_addr_matches_T_65 = lcam_addr_0[31:3]; // @[lsu.scala:263:49, :1146:74] wire [28:0] _dword_addr_matches_T_71 = lcam_addr_0[31:3]; // @[lsu.scala:263:49, :1146:74] wire [28:0] _dword_addr_matches_T_77 = lcam_addr_0[31:3]; // @[lsu.scala:263:49, :1146:74] wire _dword_addr_matches_T_36 = _dword_addr_matches_T_34 == _dword_addr_matches_T_35; // @[lsu.scala:1146:{38,58,74}] wire _dword_addr_matches_T_37 = _dword_addr_matches_T_33 & _dword_addr_matches_T_36; // @[lsu.scala:1144:60, :1145:60, :1146:58] wire dword_addr_matches_8_0 = _dword_addr_matches_T_37; // @[lsu.scala:263:49, :1145:60] wire [7:0] write_mask; // @[lsu.scala:1665:22] wire _write_mask_mask_T = stq_0_bits_uop_mem_size == 2'h0; // @[lsu.scala:209:16, :1667:26] wire [2:0] _write_mask_mask_T_1 = stq_0_bits_addr_bits[2:0]; // @[lsu.scala:209:16, :1667:55] wire [14:0] _write_mask_mask_T_2 = 15'h1 << _write_mask_mask_T_1; // @[lsu.scala:1667:{48,55}] wire _write_mask_mask_T_3 = stq_0_bits_uop_mem_size == 2'h1; // @[lsu.scala:209:16, :1668:26] wire [1:0] _write_mask_mask_T_4 = stq_0_bits_addr_bits[2:1]; // @[lsu.scala:209:16, :1668:56] wire [2:0] _write_mask_mask_T_5 = {_write_mask_mask_T_4, 1'h0}; // @[lsu.scala:1668:{56,62}] wire [14:0] _write_mask_mask_T_6 = 15'h3 << _write_mask_mask_T_5; // @[lsu.scala:1668:{48,62}] wire _write_mask_mask_T_7 = stq_0_bits_uop_mem_size == 2'h2; // @[lsu.scala:209:16, :1669:26] wire _write_mask_mask_T_8 = stq_0_bits_addr_bits[2]; // @[lsu.scala:209:16, :1669:46] wire [7:0] _write_mask_mask_T_9 = _write_mask_mask_T_8 ? 8'hF0 : 8'hF; // @[lsu.scala:1669:{41,46}] wire _write_mask_mask_T_10 = &stq_0_bits_uop_mem_size; // @[lsu.scala:209:16, :1670:26] wire [7:0] _write_mask_mask_T_12 = _write_mask_mask_T_7 ? _write_mask_mask_T_9 : 8'hFF; // @[Mux.scala:126:16] wire [14:0] _write_mask_mask_T_13 = _write_mask_mask_T_3 ? _write_mask_mask_T_6 : {7'h0, _write_mask_mask_T_12}; // @[Mux.scala:126:16] wire [14:0] _write_mask_mask_T_14 = _write_mask_mask_T ? _write_mask_mask_T_2 : _write_mask_mask_T_13; // @[Mux.scala:126:16] assign write_mask = _write_mask_mask_T_14[7:0]; // @[Mux.scala:126:16] wire _T_473 = do_ld_search_0 & stq_0_valid & lcam_st_dep_mask_0[0]; // @[lsu.scala:209:16, :263:49, :1149:{29,45,67}] wire [7:0] _T_484 = lcam_mask_0 & write_mask; // @[lsu.scala:263:49, :1150:30, :1665:22] wire _T_481 = _T_484 == lcam_mask_0 & ~stq_0_bits_uop_is_fence & ~stq_0_bits_uop_is_amo & dword_addr_matches_8_0 & can_forward_0; // @[lsu.scala:209:16, :263:49, :1045:29, :1150:{30,44,62,65,81,84,98,123}] assign ldst_forward_matches_0_0 = _T_473 & _T_481; // @[lsu.scala:1052:38, :1149:{29,45,72}, :1150:{62,81,98,123}, :1151:9, :1153:46] reg io_dmem_s1_kill_0_REG_8; // @[lsu.scala:1154:56] wire _T_486 = (\|_T_484) & dword_addr_matches_8_0; // @[lsu.scala:263:49, :1150:30, :1157:{51,60}] reg io_dmem_s1_kill_0_REG_9; // @[lsu.scala:1160:56] wire _T_489 = stq_0_bits_uop_is_fence \| stq_0_bits_uop_is_amo; // @[lsu.scala:209:16, :1163:37] assign ldst_addr_matches_0_0 = _T_473 & (_T_481 \| _T_486 \| _T_489); // @[lsu.scala:1050:38, :1149:{29,45,72}, :1150:{62,81,98,123}, :1151:9, :1152:46, :1157:60, :1158:9, :1159:46, :1163:37, :1164:9, :1165:46] reg io_dmem_s1_kill_0_REG_10; // @[lsu.scala:1166:56] wire _GEN_284 = _T_473 ? (_T_481 ? io_dmem_s1_kill_0_REG_8 : _T_486 ? io_dmem_s1_kill_0_REG_9 : _T_489 ? io_dmem_s1_kill_0_REG_10 : _GEN_283) : _GEN_283; // @[lsu.scala:1092:36, :1103:37, :1117:37, :1149:{29,45,72}, :1150:{62,81,98,123}, :1151:9, :1154:{46,56}, :1157:60, :1158:9, :1160:{46,56}, :1163:37, :1164:9, :1166:{46,56}] wire _GEN_285 = _T_481 \| _T_486; // @[lsu.scala:1150:{62,81,98,123}, :1151:9, :1155:46, :1157:60, :1158:9] wire _GEN_286 = _T_473 ? (_GEN_285 ? ~_searcher_is_older_T_4 & _GEN_275 : ~(_T_489 & _searcher_is_older_T_4) & _GEN_275) : _GEN_275; // @[util.scala:363:52] wire _GEN_287 = _T_473 ? (_GEN_285 ? ~_GEN_234 & _GEN_276 : ~(_T_489 & _GEN_234) & _GEN_276) : _GEN_276; // @[lsu.scala:1058:36, :1092:36, :1103:37, :1117:37, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_288 = _T_473 ? (_GEN_285 ? ~_GEN_235 & _GEN_277 : ~(_T_489 & _GEN_235) & _GEN_277) : _GEN_277; // @[lsu.scala:1058:36, :1092:36, :1103:37, :1117:37, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_289 = _T_473 ? (_GEN_285 ? ~_GEN_236 & _GEN_278 : ~(_T_489 & _GEN_236) & _GEN_278) : _GEN_278; // @[lsu.scala:1058:36, :1092:36, :1103:37, :1117:37, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_290 = _T_473 ? (_GEN_285 ? ~_GEN_237 & _GEN_279 : ~(_T_489 & _GEN_237) & _GEN_279) : _GEN_279; // @[lsu.scala:1058:36, :1092:36, :1103:37, :1117:37, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_291 = _T_473 ? (_GEN_285 ? ~_GEN_238 & _GEN_280 : ~(_T_489 & _GEN_238) & _GEN_280) : _GEN_280; // @[lsu.scala:1058:36, :1092:36, :1103:37, :1117:37, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_292 = _T_473 ? (_GEN_285 ? ~_GEN_239 & _GEN_281 : ~(_T_489 & _GEN_239) & _GEN_281) : _GEN_281; // @[lsu.scala:1058:36, :1092:36, :1103:37, :1117:37, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_293 = _T_473 ? (_GEN_285 ? ~(&lcam_ldq_idx_0) & _GEN_270 : ~(_T_489 & (&lcam_ldq_idx_0)) & _GEN_270) : _GEN_270; // @[lsu.scala:263:49, :1058:36, :1092:36, :1103:37, :1117:37, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _dword_addr_matches_T_38 = ~stq_1_bits_addr_is_virtual; // @[lsu.scala:209:16, :1145:31] wire _dword_addr_matches_T_39 = stq_1_bits_addr_valid & _dword_addr_matches_T_38; // @[lsu.scala:209:16, :1144:60, :1145:31] wire [28:0] _dword_addr_matches_T_40 = stq_1_bits_addr_bits[31:3]; // @[lsu.scala:209:16, :1146:38] wire _dword_addr_matches_T_42 = _dword_addr_matches_T_40 == _dword_addr_matches_T_41; // @[lsu.scala:1146:{38,58,74}] wire _dword_addr_matches_T_43 = _dword_addr_matches_T_39 & _dword_addr_matches_T_42; // @[lsu.scala:1144:60, :1145:60, :1146:58] wire dword_addr_matches_9_0 = _dword_addr_matches_T_43; // @[lsu.scala:263:49, :1145:60] wire [7:0] write_mask_1; // @[lsu.scala:1665:22] wire _write_mask_mask_T_15 = stq_1_bits_uop_mem_size == 2'h0; // @[lsu.scala:209:16, :1667:26] wire [2:0] _write_mask_mask_T_16 = stq_1_bits_addr_bits[2:0]; // @[lsu.scala:209:16, :1667:55] wire [14:0] _write_mask_mask_T_17 = 15'h1 << _write_mask_mask_T_16; // @[lsu.scala:1667:{48,55}] wire _write_mask_mask_T_18 = stq_1_bits_uop_mem_size == 2'h1; // @[lsu.scala:209:16, :1668:26] wire [1:0] _write_mask_mask_T_19 = stq_1_bits_addr_bits[2:1]; // @[lsu.scala:209:16, :1668:56] wire [2:0] _write_mask_mask_T_20 = {_write_mask_mask_T_19, 1'h0}; // @[lsu.scala:1668:{56,62}] wire [14:0] _write_mask_mask_T_21 = 15'h3 << _write_mask_mask_T_20; // @[lsu.scala:1668:{48,62}] wire _write_mask_mask_T_22 = stq_1_bits_uop_mem_size == 2'h2; // @[lsu.scala:209:16, :1669:26] wire _write_mask_mask_T_23 = stq_1_bits_addr_bits[2]; // @[lsu.scala:209:16, :1669:46] wire [7:0] _write_mask_mask_T_24 = _write_mask_mask_T_23 ? 8'hF0 : 8'hF; // @[lsu.scala:1669:{41,46}] wire _write_mask_mask_T_25 = &stq_1_bits_uop_mem_size; // @[lsu.scala:209:16, :1670:26] wire [7:0] _write_mask_mask_T_27 = _write_mask_mask_T_22 ? _write_mask_mask_T_24 : 8'hFF; // @[Mux.scala:126:16] wire [14:0] _write_mask_mask_T_28 = _write_mask_mask_T_18 ? _write_mask_mask_T_21 : {7'h0, _write_mask_mask_T_27}; // @[Mux.scala:126:16] wire [14:0] _write_mask_mask_T_29 = _write_mask_mask_T_15 ? _write_mask_mask_T_17 : _write_mask_mask_T_28; // @[Mux.scala:126:16] assign write_mask_1 = _write_mask_mask_T_29[7:0]; // @[Mux.scala:126:16] wire _T_494 = do_ld_search_0 & stq_1_valid & lcam_st_dep_mask_0[1]; // @[lsu.scala:209:16, :263:49, :1149:{29,45,67}] wire [7:0] _T_505 = lcam_mask_0 & write_mask_1; // @[lsu.scala:263:49, :1150:30, :1665:22] wire _T_502 = _T_505 == lcam_mask_0 & ~stq_1_bits_uop_is_fence & ~stq_1_bits_uop_is_amo & dword_addr_matches_9_0 & can_forward_0; // @[lsu.scala:209:16, :263:49, :1045:29, :1150:{30,44,62,65,81,84,98,123}] assign ldst_forward_matches_0_1 = _T_494 & _T_502; // @[lsu.scala:1052:38, :1149:{29,45,72}, :1150:{62,81,98,123}, :1151:9, :1153:46] reg io_dmem_s1_kill_0_REG_11; // @[lsu.scala:1154:56] wire _T_507 = (\|_T_505) & dword_addr_matches_9_0; // @[lsu.scala:263:49, :1150:30, :1157:{51,60}] reg io_dmem_s1_kill_0_REG_12; // @[lsu.scala:1160:56] wire _T_510 = stq_1_bits_uop_is_fence \| stq_1_bits_uop_is_amo; // @[lsu.scala:209:16, :1163:37] assign ldst_addr_matches_0_1 = _T_494 & (_T_502 \| _T_507 \| _T_510); // @[lsu.scala:1050:38, :1149:{29,45,72}, :1150:{62,81,98,123}, :1151:9, :1152:46, :1157:60, :1158:9, :1159:46, :1163:37, :1164:9, :1165:46] reg io_dmem_s1_kill_0_REG_13; // @[lsu.scala:1166:56] wire _GEN_294 = _T_494 ? (_T_502 ? io_dmem_s1_kill_0_REG_11 : _T_507 ? io_dmem_s1_kill_0_REG_12 : _T_510 ? io_dmem_s1_kill_0_REG_13 : _GEN_284) : _GEN_284; // @[lsu.scala:1092:36, :1149:{29,45,72}, :1150:{62,81,98,123}, :1151:9, :1154:{46,56}, :1157:60, :1158:9, :1160:{46,56}, :1163:37, :1164:9, :1166:{46,56}] wire _GEN_295 = _T_502 \| _T_507; // @[lsu.scala:1150:{62,81,98,123}, :1151:9, :1155:46, :1157:60, :1158:9] wire _GEN_296 = _T_494 ? (_GEN_295 ? ~_searcher_is_older_T_4 & _GEN_286 : ~(_T_510 & _searcher_is_older_T_4) & _GEN_286) : _GEN_286; // @[util.scala:363:52] wire _GEN_297 = _T_494 ? (_GEN_295 ? ~_GEN_234 & _GEN_287 : ~(_T_510 & _GEN_234) & _GEN_287) : _GEN_287; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_298 = _T_494 ? (_GEN_295 ? ~_GEN_235 & _GEN_288 : ~(_T_510 & _GEN_235) & _GEN_288) : _GEN_288; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_299 = _T_494 ? (_GEN_295 ? ~_GEN_236 & _GEN_289 : ~(_T_510 & _GEN_236) & _GEN_289) : _GEN_289; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_300 = _T_494 ? (_GEN_295 ? ~_GEN_237 & _GEN_290 : ~(_T_510 & _GEN_237) & _GEN_290) : _GEN_290; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_301 = _T_494 ? (_GEN_295 ? ~_GEN_238 & _GEN_291 : ~(_T_510 & _GEN_238) & _GEN_291) : _GEN_291; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_302 = _T_494 ? (_GEN_295 ? ~_GEN_239 & _GEN_292 : ~(_T_510 & _GEN_239) & _GEN_292) : _GEN_292; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_303 = _T_494 ? (_GEN_295 ? ~(&lcam_ldq_idx_0) & _GEN_293 : ~(_T_510 & (&lcam_ldq_idx_0)) & _GEN_293) : _GEN_293; // @[lsu.scala:263:49, :1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _dword_addr_matches_T_44 = ~stq_2_bits_addr_is_virtual; // @[lsu.scala:209:16, :1145:31] wire _dword_addr_matches_T_45 = stq_2_bits_addr_valid & _dword_addr_matches_T_44; // @[lsu.scala:209:16, :1144:60, :1145:31] wire [28:0] _dword_addr_matches_T_46 = stq_2_bits_addr_bits[31:3]; // @[lsu.scala:209:16, :1146:38] wire _dword_addr_matches_T_48 = _dword_addr_matches_T_46 == _dword_addr_matches_T_47; // @[lsu.scala:1146:{38,58,74}] wire _dword_addr_matches_T_49 = _dword_addr_matches_T_45 & _dword_addr_matches_T_48; // @[lsu.scala:1144:60, :1145:60, :1146:58] wire dword_addr_matches_10_0 = _dword_addr_matches_T_49; // @[lsu.scala:263:49, :1145:60] wire [7:0] write_mask_2; // @[lsu.scala:1665:22] wire _write_mask_mask_T_30 = stq_2_bits_uop_mem_size == 2'h0; // @[lsu.scala:209:16, :1667:26] wire [2:0] _write_mask_mask_T_31 = stq_2_bits_addr_bits[2:0]; // @[lsu.scala:209:16, :1667:55] wire [14:0] _write_mask_mask_T_32 = 15'h1 << _write_mask_mask_T_31; // @[lsu.scala:1667:{48,55}] wire _write_mask_mask_T_33 = stq_2_bits_uop_mem_size == 2'h1; // @[lsu.scala:209:16, :1668:26] wire [1:0] _write_mask_mask_T_34 = stq_2_bits_addr_bits[2:1]; // @[lsu.scala:209:16, :1668:56] wire [2:0] _write_mask_mask_T_35 = {_write_mask_mask_T_34, 1'h0}; // @[lsu.scala:1668:{56,62}] wire [14:0] _write_mask_mask_T_36 = 15'h3 << _write_mask_mask_T_35; // @[lsu.scala:1668:{48,62}] wire _write_mask_mask_T_37 = stq_2_bits_uop_mem_size == 2'h2; // @[lsu.scala:209:16, :1669:26] wire _write_mask_mask_T_38 = stq_2_bits_addr_bits[2]; // @[lsu.scala:209:16, :1669:46] wire [7:0] _write_mask_mask_T_39 = _write_mask_mask_T_38 ? 8'hF0 : 8'hF; // @[lsu.scala:1669:{41,46}] wire _write_mask_mask_T_40 = &stq_2_bits_uop_mem_size; // @[lsu.scala:209:16, :1670:26] wire [7:0] _write_mask_mask_T_42 = _write_mask_mask_T_37 ? _write_mask_mask_T_39 : 8'hFF; // @[Mux.scala:126:16] wire [14:0] _write_mask_mask_T_43 = _write_mask_mask_T_33 ? _write_mask_mask_T_36 : {7'h0, _write_mask_mask_T_42}; // @[Mux.scala:126:16] wire [14:0] _write_mask_mask_T_44 = _write_mask_mask_T_30 ? _write_mask_mask_T_32 : _write_mask_mask_T_43; // @[Mux.scala:126:16] assign write_mask_2 = _write_mask_mask_T_44[7:0]; // @[Mux.scala:126:16] wire _T_515 = do_ld_search_0 & stq_2_valid & lcam_st_dep_mask_0[2]; // @[lsu.scala:209:16, :263:49, :1149:{29,45,67}] wire [7:0] _T_526 = lcam_mask_0 & write_mask_2; // @[lsu.scala:263:49, :1150:30, :1665:22] wire _T_523 = _T_526 == lcam_mask_0 & ~stq_2_bits_uop_is_fence & ~stq_2_bits_uop_is_amo & dword_addr_matches_10_0 & can_forward_0; // @[lsu.scala:209:16, :263:49, :1045:29, :1150:{30,44,62,65,81,84,98,123}] assign ldst_forward_matches_0_2 = _T_515 & _T_523; // @[lsu.scala:1052:38, :1149:{29,45,72}, :1150:{62,81,98,123}, :1151:9, :1153:46] reg io_dmem_s1_kill_0_REG_14; // @[lsu.scala:1154:56] wire _T_528 = (\|_T_526) & dword_addr_matches_10_0; // @[lsu.scala:263:49, :1150:30, :1157:{51,60}] reg io_dmem_s1_kill_0_REG_15; // @[lsu.scala:1160:56] wire _T_531 = stq_2_bits_uop_is_fence \| stq_2_bits_uop_is_amo; // @[lsu.scala:209:16, :1163:37] assign ldst_addr_matches_0_2 = _T_515 & (_T_523 \| _T_528 \| _T_531); // @[lsu.scala:1050:38, :1149:{29,45,72}, :1150:{62,81,98,123}, :1151:9, :1152:46, :1157:60, :1158:9, :1159:46, :1163:37, :1164:9, :1165:46] reg io_dmem_s1_kill_0_REG_16; // @[lsu.scala:1166:56] wire _GEN_304 = _T_515 ? (_T_523 ? io_dmem_s1_kill_0_REG_14 : _T_528 ? io_dmem_s1_kill_0_REG_15 : _T_531 ? io_dmem_s1_kill_0_REG_16 : _GEN_294) : _GEN_294; // @[lsu.scala:1149:{29,45,72}, :1150:{62,81,98,123}, :1151:9, :1154:{46,56}, :1157:60, :1158:9, :1160:{46,56}, :1163:37, :1164:9, :1166:{46,56}] wire _GEN_305 = _T_523 \| _T_528; // @[lsu.scala:1150:{62,81,98,123}, :1151:9, :1155:46, :1157:60, :1158:9] wire _GEN_306 = _T_515 ? (_GEN_305 ? ~_searcher_is_older_T_4 & _GEN_296 : ~(_T_531 & _searcher_is_older_T_4) & _GEN_296) : _GEN_296; // @[util.scala:363:52] wire _GEN_307 = _T_515 ? (_GEN_305 ? ~_GEN_234 & _GEN_297 : ~(_T_531 & _GEN_234) & _GEN_297) : _GEN_297; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_308 = _T_515 ? (_GEN_305 ? ~_GEN_235 & _GEN_298 : ~(_T_531 & _GEN_235) & _GEN_298) : _GEN_298; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_309 = _T_515 ? (_GEN_305 ? ~_GEN_236 & _GEN_299 : ~(_T_531 & _GEN_236) & _GEN_299) : _GEN_299; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_310 = _T_515 ? (_GEN_305 ? ~_GEN_237 & _GEN_300 : ~(_T_531 & _GEN_237) & _GEN_300) : _GEN_300; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_311 = _T_515 ? (_GEN_305 ? ~_GEN_238 & _GEN_301 : ~(_T_531 & _GEN_238) & _GEN_301) : _GEN_301; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_312 = _T_515 ? (_GEN_305 ? ~_GEN_239 & _GEN_302 : ~(_T_531 & _GEN_239) & _GEN_302) : _GEN_302; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_313 = _T_515 ? (_GEN_305 ? ~(&lcam_ldq_idx_0) & _GEN_303 : ~(_T_531 & (&lcam_ldq_idx_0)) & _GEN_303) : _GEN_303; // @[lsu.scala:263:49, :1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _dword_addr_matches_T_50 = ~stq_3_bits_addr_is_virtual; // @[lsu.scala:209:16, :1145:31] wire _dword_addr_matches_T_51 = stq_3_bits_addr_valid & _dword_addr_matches_T_50; // @[lsu.scala:209:16, :1144:60, :1145:31] wire [28:0] _dword_addr_matches_T_52 = stq_3_bits_addr_bits[31:3]; // @[lsu.scala:209:16, :1146:38] wire _dword_addr_matches_T_54 = _dword_addr_matches_T_52 == _dword_addr_matches_T_53; // @[lsu.scala:1146:{38,58,74}] wire _dword_addr_matches_T_55 = _dword_addr_matches_T_51 & _dword_addr_matches_T_54; // @[lsu.scala:1144:60, :1145:60, :1146:58] wire dword_addr_matches_11_0 = _dword_addr_matches_T_55; // @[lsu.scala:263:49, :1145:60] wire [7:0] write_mask_3; // @[lsu.scala:1665:22] wire _write_mask_mask_T_45 = stq_3_bits_uop_mem_size == 2'h0; // @[lsu.scala:209:16, :1667:26] wire [2:0] _write_mask_mask_T_46 = stq_3_bits_addr_bits[2:0]; // @[lsu.scala:209:16, :1667:55] wire [14:0] _write_mask_mask_T_47 = 15'h1 << _write_mask_mask_T_46; // @[lsu.scala:1667:{48,55}] wire _write_mask_mask_T_48 = stq_3_bits_uop_mem_size == 2'h1; // @[lsu.scala:209:16, :1668:26] wire [1:0] _write_mask_mask_T_49 = stq_3_bits_addr_bits[2:1]; // @[lsu.scala:209:16, :1668:56] wire [2:0] _write_mask_mask_T_50 = {_write_mask_mask_T_49, 1'h0}; // @[lsu.scala:1668:{56,62}] wire [14:0] _write_mask_mask_T_51 = 15'h3 << _write_mask_mask_T_50; // @[lsu.scala:1668:{48,62}] wire _write_mask_mask_T_52 = stq_3_bits_uop_mem_size == 2'h2; // @[lsu.scala:209:16, :1669:26] wire _write_mask_mask_T_53 = stq_3_bits_addr_bits[2]; // @[lsu.scala:209:16, :1669:46] wire [7:0] _write_mask_mask_T_54 = _write_mask_mask_T_53 ? 8'hF0 : 8'hF; // @[lsu.scala:1669:{41,46}] wire _write_mask_mask_T_55 = &stq_3_bits_uop_mem_size; // @[lsu.scala:209:16, :1670:26] wire [7:0] _write_mask_mask_T_57 = _write_mask_mask_T_52 ? _write_mask_mask_T_54 : 8'hFF; // @[Mux.scala:126:16] wire [14:0] _write_mask_mask_T_58 = _write_mask_mask_T_48 ? _write_mask_mask_T_51 : {7'h0, _write_mask_mask_T_57}; // @[Mux.scala:126:16] wire [14:0] _write_mask_mask_T_59 = _write_mask_mask_T_45 ? _write_mask_mask_T_47 : _write_mask_mask_T_58; // @[Mux.scala:126:16] assign write_mask_3 = _write_mask_mask_T_59[7:0]; // @[Mux.scala:126:16] wire _T_536 = do_ld_search_0 & stq_3_valid & lcam_st_dep_mask_0[3]; // @[lsu.scala:209:16, :263:49, :1149:{29,45,67}] wire [7:0] _T_547 = lcam_mask_0 & write_mask_3; // @[lsu.scala:263:49, :1150:30, :1665:22] wire _T_544 = _T_547 == lcam_mask_0 & ~stq_3_bits_uop_is_fence & ~stq_3_bits_uop_is_amo & dword_addr_matches_11_0 & can_forward_0; // @[lsu.scala:209:16, :263:49, :1045:29, :1150:{30,44,62,65,81,84,98,123}] assign ldst_forward_matches_0_3 = _T_536 & _T_544; // @[lsu.scala:1052:38, :1149:{29,45,72}, :1150:{62,81,98,123}, :1151:9, :1153:46] reg io_dmem_s1_kill_0_REG_17; // @[lsu.scala:1154:56] wire _T_549 = (\|_T_547) & dword_addr_matches_11_0; // @[lsu.scala:263:49, :1150:30, :1157:{51,60}] reg io_dmem_s1_kill_0_REG_18; // @[lsu.scala:1160:56] wire _T_552 = stq_3_bits_uop_is_fence \| stq_3_bits_uop_is_amo; // @[lsu.scala:209:16, :1163:37] assign ldst_addr_matches_0_3 = _T_536 & (_T_544 \| _T_549 \| _T_552); // @[lsu.scala:1050:38, :1149:{29,45,72}, :1150:{62,81,98,123}, :1151:9, :1152:46, :1157:60, :1158:9, :1159:46, :1163:37, :1164:9, :1165:46] reg io_dmem_s1_kill_0_REG_19; // @[lsu.scala:1166:56] wire _GEN_314 = _T_536 ? (_T_544 ? io_dmem_s1_kill_0_REG_17 : _T_549 ? io_dmem_s1_kill_0_REG_18 : _T_552 ? io_dmem_s1_kill_0_REG_19 : _GEN_304) : _GEN_304; // @[lsu.scala:1149:{29,45,72}, :1150:{62,81,98,123}, :1151:9, :1154:{46,56}, :1157:60, :1158:9, :1160:{46,56}, :1163:37, :1164:9, :1166:{46,56}] wire _GEN_315 = _T_544 \| _T_549; // @[lsu.scala:1150:{62,81,98,123}, :1151:9, :1155:46, :1157:60, :1158:9] wire _GEN_316 = _T_536 ? (_GEN_315 ? ~_searcher_is_older_T_4 & _GEN_306 : ~(_T_552 & _searcher_is_older_T_4) & _GEN_306) : _GEN_306; // @[util.scala:363:52] wire _GEN_317 = _T_536 ? (_GEN_315 ? ~_GEN_234 & _GEN_307 : ~(_T_552 & _GEN_234) & _GEN_307) : _GEN_307; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_318 = _T_536 ? (_GEN_315 ? ~_GEN_235 & _GEN_308 : ~(_T_552 & _GEN_235) & _GEN_308) : _GEN_308; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_319 = _T_536 ? (_GEN_315 ? ~_GEN_236 & _GEN_309 : ~(_T_552 & _GEN_236) & _GEN_309) : _GEN_309; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_320 = _T_536 ? (_GEN_315 ? ~_GEN_237 & _GEN_310 : ~(_T_552 & _GEN_237) & _GEN_310) : _GEN_310; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_321 = _T_536 ? (_GEN_315 ? ~_GEN_238 & _GEN_311 : ~(_T_552 & _GEN_238) & _GEN_311) : _GEN_311; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_322 = _T_536 ? (_GEN_315 ? ~_GEN_239 & _GEN_312 : ~(_T_552 & _GEN_239) & _GEN_312) : _GEN_312; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_323 = _T_536 ? (_GEN_315 ? ~(&lcam_ldq_idx_0) & _GEN_313 : ~(_T_552 & (&lcam_ldq_idx_0)) & _GEN_313) : _GEN_313; // @[lsu.scala:263:49, :1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _dword_addr_matches_T_56 = ~stq_4_bits_addr_is_virtual; // @[lsu.scala:209:16, :1145:31] wire _dword_addr_matches_T_57 = stq_4_bits_addr_valid & _dword_addr_matches_T_56; // @[lsu.scala:209:16, :1144:60, :1145:31] wire [28:0] _dword_addr_matches_T_58 = stq_4_bits_addr_bits[31:3]; // @[lsu.scala:209:16, :1146:38] wire _dword_addr_matches_T_60 = _dword_addr_matches_T_58 == _dword_addr_matches_T_59; // @[lsu.scala:1146:{38,58,74}] wire _dword_addr_matches_T_61 = _dword_addr_matches_T_57 & _dword_addr_matches_T_60; // @[lsu.scala:1144:60, :1145:60, :1146:58] wire dword_addr_matches_12_0 = _dword_addr_matches_T_61; // @[lsu.scala:263:49, :1145:60] wire [7:0] write_mask_4; // @[lsu.scala:1665:22] wire _write_mask_mask_T_60 = stq_4_bits_uop_mem_size == 2'h0; // @[lsu.scala:209:16, :1667:26] wire [2:0] _write_mask_mask_T_61 = stq_4_bits_addr_bits[2:0]; // @[lsu.scala:209:16, :1667:55] wire [14:0] _write_mask_mask_T_62 = 15'h1 << _write_mask_mask_T_61; // @[lsu.scala:1667:{48,55}] wire _write_mask_mask_T_63 = stq_4_bits_uop_mem_size == 2'h1; // @[lsu.scala:209:16, :1668:26] wire [1:0] _write_mask_mask_T_64 = stq_4_bits_addr_bits[2:1]; // @[lsu.scala:209:16, :1668:56] wire [2:0] _write_mask_mask_T_65 = {_write_mask_mask_T_64, 1'h0}; // @[lsu.scala:1668:{56,62}] wire [14:0] _write_mask_mask_T_66 = 15'h3 << _write_mask_mask_T_65; // @[lsu.scala:1668:{48,62}] wire _write_mask_mask_T_67 = stq_4_bits_uop_mem_size == 2'h2; // @[lsu.scala:209:16, :1669:26] wire _write_mask_mask_T_68 = stq_4_bits_addr_bits[2]; // @[lsu.scala:209:16, :1669:46] wire [7:0] _write_mask_mask_T_69 = _write_mask_mask_T_68 ? 8'hF0 : 8'hF; // @[lsu.scala:1669:{41,46}] wire _write_mask_mask_T_70 = &stq_4_bits_uop_mem_size; // @[lsu.scala:209:16, :1670:26] wire [7:0] _write_mask_mask_T_72 = _write_mask_mask_T_67 ? _write_mask_mask_T_69 : 8'hFF; // @[Mux.scala:126:16] wire [14:0] _write_mask_mask_T_73 = _write_mask_mask_T_63 ? _write_mask_mask_T_66 : {7'h0, _write_mask_mask_T_72}; // @[Mux.scala:126:16] wire [14:0] _write_mask_mask_T_74 = _write_mask_mask_T_60 ? _write_mask_mask_T_62 : _write_mask_mask_T_73; // @[Mux.scala:126:16] assign write_mask_4 = _write_mask_mask_T_74[7:0]; // @[Mux.scala:126:16] wire _T_557 = do_ld_search_0 & stq_4_valid & lcam_st_dep_mask_0[4]; // @[lsu.scala:209:16, :263:49, :1149:{29,45,67}] wire [7:0] _T_568 = lcam_mask_0 & write_mask_4; // @[lsu.scala:263:49, :1150:30, :1665:22] wire _T_565 = _T_568 == lcam_mask_0 & ~stq_4_bits_uop_is_fence & ~stq_4_bits_uop_is_amo & dword_addr_matches_12_0 & can_forward_0; // @[lsu.scala:209:16, :263:49, :1045:29, :1150:{30,44,62,65,81,84,98,123}] assign ldst_forward_matches_0_4 = _T_557 & _T_565; // @[lsu.scala:1052:38, :1149:{29,45,72}, :1150:{62,81,98,123}, :1151:9, :1153:46] reg io_dmem_s1_kill_0_REG_20; // @[lsu.scala:1154:56] wire _T_570 = (\|_T_568) & dword_addr_matches_12_0; // @[lsu.scala:263:49, :1150:30, :1157:{51,60}] reg io_dmem_s1_kill_0_REG_21; // @[lsu.scala:1160:56] wire _T_573 = stq_4_bits_uop_is_fence \| stq_4_bits_uop_is_amo; // @[lsu.scala:209:16, :1163:37] assign ldst_addr_matches_0_4 = _T_557 & (_T_565 \| _T_570 \| _T_573); // @[lsu.scala:1050:38, :1149:{29,45,72}, :1150:{62,81,98,123}, :1151:9, :1152:46, :1157:60, :1158:9, :1159:46, :1163:37, :1164:9, :1165:46] reg io_dmem_s1_kill_0_REG_22; // @[lsu.scala:1166:56] wire _GEN_324 = _T_557 ? (_T_565 ? io_dmem_s1_kill_0_REG_20 : _T_570 ? io_dmem_s1_kill_0_REG_21 : _T_573 ? io_dmem_s1_kill_0_REG_22 : _GEN_314) : _GEN_314; // @[lsu.scala:1149:{29,45,72}, :1150:{62,81,98,123}, :1151:9, :1154:{46,56}, :1157:60, :1158:9, :1160:{46,56}, :1163:37, :1164:9, :1166:{46,56}] wire _GEN_325 = _T_565 \| _T_570; // @[lsu.scala:1150:{62,81,98,123}, :1151:9, :1155:46, :1157:60, :1158:9] wire _GEN_326 = _T_557 ? (_GEN_325 ? ~_searcher_is_older_T_4 & _GEN_316 : ~(_T_573 & _searcher_is_older_T_4) & _GEN_316) : _GEN_316; // @[util.scala:363:52] wire _GEN_327 = _T_557 ? (_GEN_325 ? ~_GEN_234 & _GEN_317 : ~(_T_573 & _GEN_234) & _GEN_317) : _GEN_317; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_328 = _T_557 ? (_GEN_325 ? ~_GEN_235 & _GEN_318 : ~(_T_573 & _GEN_235) & _GEN_318) : _GEN_318; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_329 = _T_557 ? (_GEN_325 ? ~_GEN_236 & _GEN_319 : ~(_T_573 & _GEN_236) & _GEN_319) : _GEN_319; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_330 = _T_557 ? (_GEN_325 ? ~_GEN_237 & _GEN_320 : ~(_T_573 & _GEN_237) & _GEN_320) : _GEN_320; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_331 = _T_557 ? (_GEN_325 ? ~_GEN_238 & _GEN_321 : ~(_T_573 & _GEN_238) & _GEN_321) : _GEN_321; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_332 = _T_557 ? (_GEN_325 ? ~_GEN_239 & _GEN_322 : ~(_T_573 & _GEN_239) & _GEN_322) : _GEN_322; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_333 = _T_557 ? (_GEN_325 ? ~(&lcam_ldq_idx_0) & _GEN_323 : ~(_T_573 & (&lcam_ldq_idx_0)) & _GEN_323) : _GEN_323; // @[lsu.scala:263:49, :1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _dword_addr_matches_T_62 = ~stq_5_bits_addr_is_virtual; // @[lsu.scala:209:16, :1145:31] wire _dword_addr_matches_T_63 = stq_5_bits_addr_valid & _dword_addr_matches_T_62; // @[lsu.scala:209:16, :1144:60, :1145:31] wire [28:0] _dword_addr_matches_T_64 = stq_5_bits_addr_bits[31:3]; // @[lsu.scala:209:16, :1146:38] wire _dword_addr_matches_T_66 = _dword_addr_matches_T_64 == _dword_addr_matches_T_65; // @[lsu.scala:1146:{38,58,74}] wire _dword_addr_matches_T_67 = _dword_addr_matches_T_63 & _dword_addr_matches_T_66; // @[lsu.scala:1144:60, :1145:60, :1146:58] wire dword_addr_matches_13_0 = _dword_addr_matches_T_67; // @[lsu.scala:263:49, :1145:60] wire [7:0] write_mask_5; // @[lsu.scala:1665:22] wire _write_mask_mask_T_75 = stq_5_bits_uop_mem_size == 2'h0; // @[lsu.scala:209:16, :1667:26] wire [2:0] _write_mask_mask_T_76 = stq_5_bits_addr_bits[2:0]; // @[lsu.scala:209:16, :1667:55] wire [14:0] _write_mask_mask_T_77 = 15'h1 << _write_mask_mask_T_76; // @[lsu.scala:1667:{48,55}] wire _write_mask_mask_T_78 = stq_5_bits_uop_mem_size == 2'h1; // @[lsu.scala:209:16, :1668:26] wire [1:0] _write_mask_mask_T_79 = stq_5_bits_addr_bits[2:1]; // @[lsu.scala:209:16, :1668:56] wire [2:0] _write_mask_mask_T_80 = {_write_mask_mask_T_79, 1'h0}; // @[lsu.scala:1668:{56,62}] wire [14:0] _write_mask_mask_T_81 = 15'h3 << _write_mask_mask_T_80; // @[lsu.scala:1668:{48,62}] wire _write_mask_mask_T_82 = stq_5_bits_uop_mem_size == 2'h2; // @[lsu.scala:209:16, :1669:26] wire _write_mask_mask_T_83 = stq_5_bits_addr_bits[2]; // @[lsu.scala:209:16, :1669:46] wire [7:0] _write_mask_mask_T_84 = _write_mask_mask_T_83 ? 8'hF0 : 8'hF; // @[lsu.scala:1669:{41,46}] wire _write_mask_mask_T_85 = &stq_5_bits_uop_mem_size; // @[lsu.scala:209:16, :1670:26] wire [7:0] _write_mask_mask_T_87 = _write_mask_mask_T_82 ? _write_mask_mask_T_84 : 8'hFF; // @[Mux.scala:126:16] wire [14:0] _write_mask_mask_T_88 = _write_mask_mask_T_78 ? _write_mask_mask_T_81 : {7'h0, _write_mask_mask_T_87}; // @[Mux.scala:126:16] wire [14:0] _write_mask_mask_T_89 = _write_mask_mask_T_75 ? _write_mask_mask_T_77 : _write_mask_mask_T_88; // @[Mux.scala:126:16] assign write_mask_5 = _write_mask_mask_T_89[7:0]; // @[Mux.scala:126:16] wire _T_578 = do_ld_search_0 & stq_5_valid & lcam_st_dep_mask_0[5]; // @[lsu.scala:209:16, :263:49, :1149:{29,45,67}] wire [7:0] _T_589 = lcam_mask_0 & write_mask_5; // @[lsu.scala:263:49, :1150:30, :1665:22] wire _T_586 = _T_589 == lcam_mask_0 & ~stq_5_bits_uop_is_fence & ~stq_5_bits_uop_is_amo & dword_addr_matches_13_0 & can_forward_0; // @[lsu.scala:209:16, :263:49, :1045:29, :1150:{30,44,62,65,81,84,98,123}] assign ldst_forward_matches_0_5 = _T_578 & _T_586; // @[lsu.scala:1052:38, :1149:{29,45,72}, :1150:{62,81,98,123}, :1151:9, :1153:46] reg io_dmem_s1_kill_0_REG_23; // @[lsu.scala:1154:56] wire _T_591 = (\|_T_589) & dword_addr_matches_13_0; // @[lsu.scala:263:49, :1150:30, :1157:{51,60}] reg io_dmem_s1_kill_0_REG_24; // @[lsu.scala:1160:56] wire _T_594 = stq_5_bits_uop_is_fence \| stq_5_bits_uop_is_amo; // @[lsu.scala:209:16, :1163:37] assign ldst_addr_matches_0_5 = _T_578 & (_T_586 \| _T_591 \| _T_594); // @[lsu.scala:1050:38, :1149:{29,45,72}, :1150:{62,81,98,123}, :1151:9, :1152:46, :1157:60, :1158:9, :1159:46, :1163:37, :1164:9, :1165:46] reg io_dmem_s1_kill_0_REG_25; // @[lsu.scala:1166:56] wire _GEN_334 = _T_578 ? (_T_586 ? io_dmem_s1_kill_0_REG_23 : _T_591 ? io_dmem_s1_kill_0_REG_24 : _T_594 ? io_dmem_s1_kill_0_REG_25 : _GEN_324) : _GEN_324; // @[lsu.scala:1149:{29,45,72}, :1150:{62,81,98,123}, :1151:9, :1154:{46,56}, :1157:60, :1158:9, :1160:{46,56}, :1163:37, :1164:9, :1166:{46,56}] wire _GEN_335 = _T_586 \| _T_591; // @[lsu.scala:1150:{62,81,98,123}, :1151:9, :1155:46, :1157:60, :1158:9] wire _GEN_336 = _T_578 ? (_GEN_335 ? ~_searcher_is_older_T_4 & _GEN_326 : ~(_T_594 & _searcher_is_older_T_4) & _GEN_326) : _GEN_326; // @[util.scala:363:52] wire _GEN_337 = _T_578 ? (_GEN_335 ? ~_GEN_234 & _GEN_327 : ~(_T_594 & _GEN_234) & _GEN_327) : _GEN_327; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_338 = _T_578 ? (_GEN_335 ? ~_GEN_235 & _GEN_328 : ~(_T_594 & _GEN_235) & _GEN_328) : _GEN_328; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_339 = _T_578 ? (_GEN_335 ? ~_GEN_236 & _GEN_329 : ~(_T_594 & _GEN_236) & _GEN_329) : _GEN_329; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_340 = _T_578 ? (_GEN_335 ? ~_GEN_237 & _GEN_330 : ~(_T_594 & _GEN_237) & _GEN_330) : _GEN_330; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_341 = _T_578 ? (_GEN_335 ? ~_GEN_238 & _GEN_331 : ~(_T_594 & _GEN_238) & _GEN_331) : _GEN_331; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_342 = _T_578 ? (_GEN_335 ? ~_GEN_239 & _GEN_332 : ~(_T_594 & _GEN_239) & _GEN_332) : _GEN_332; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_343 = _T_578 ? (_GEN_335 ? ~(&lcam_ldq_idx_0) & _GEN_333 : ~(_T_594 & (&lcam_ldq_idx_0)) & _GEN_333) : _GEN_333; // @[lsu.scala:263:49, :1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _dword_addr_matches_T_68 = ~stq_6_bits_addr_is_virtual; // @[lsu.scala:209:16, :1145:31] wire _dword_addr_matches_T_69 = stq_6_bits_addr_valid & _dword_addr_matches_T_68; // @[lsu.scala:209:16, :1144:60, :1145:31] wire [28:0] _dword_addr_matches_T_70 = stq_6_bits_addr_bits[31:3]; // @[lsu.scala:209:16, :1146:38] wire _dword_addr_matches_T_72 = _dword_addr_matches_T_70 == _dword_addr_matches_T_71; // @[lsu.scala:1146:{38,58,74}] wire _dword_addr_matches_T_73 = _dword_addr_matches_T_69 & _dword_addr_matches_T_72; // @[lsu.scala:1144:60, :1145:60, :1146:58] wire dword_addr_matches_14_0 = _dword_addr_matches_T_73; // @[lsu.scala:263:49, :1145:60] wire [7:0] write_mask_6; // @[lsu.scala:1665:22] wire _write_mask_mask_T_90 = stq_6_bits_uop_mem_size == 2'h0; // @[lsu.scala:209:16, :1667:26] wire [2:0] _write_mask_mask_T_91 = stq_6_bits_addr_bits[2:0]; // @[lsu.scala:209:16, :1667:55] wire [14:0] _write_mask_mask_T_92 = 15'h1 << _write_mask_mask_T_91; // @[lsu.scala:1667:{48,55}] wire _write_mask_mask_T_93 = stq_6_bits_uop_mem_size == 2'h1; // @[lsu.scala:209:16, :1668:26] wire [1:0] _write_mask_mask_T_94 = stq_6_bits_addr_bits[2:1]; // @[lsu.scala:209:16, :1668:56] wire [2:0] _write_mask_mask_T_95 = {_write_mask_mask_T_94, 1'h0}; // @[lsu.scala:1668:{56,62}] wire [14:0] _write_mask_mask_T_96 = 15'h3 << _write_mask_mask_T_95; // @[lsu.scala:1668:{48,62}] wire _write_mask_mask_T_97 = stq_6_bits_uop_mem_size == 2'h2; // @[lsu.scala:209:16, :1669:26] wire _write_mask_mask_T_98 = stq_6_bits_addr_bits[2]; // @[lsu.scala:209:16, :1669:46] wire [7:0] _write_mask_mask_T_99 = _write_mask_mask_T_98 ? 8'hF0 : 8'hF; // @[lsu.scala:1669:{41,46}] wire _write_mask_mask_T_100 = &stq_6_bits_uop_mem_size; // @[lsu.scala:209:16, :1670:26] wire [7:0] _write_mask_mask_T_102 = _write_mask_mask_T_97 ? _write_mask_mask_T_99 : 8'hFF; // @[Mux.scala:126:16] wire [14:0] _write_mask_mask_T_103 = _write_mask_mask_T_93 ? _write_mask_mask_T_96 : {7'h0, _write_mask_mask_T_102}; // @[Mux.scala:126:16] wire [14:0] _write_mask_mask_T_104 = _write_mask_mask_T_90 ? _write_mask_mask_T_92 : _write_mask_mask_T_103; // @[Mux.scala:126:16] assign write_mask_6 = _write_mask_mask_T_104[7:0]; // @[Mux.scala:126:16] wire _T_599 = do_ld_search_0 & stq_6_valid & lcam_st_dep_mask_0[6]; // @[lsu.scala:209:16, :263:49, :1149:{29,45,67}] wire [7:0] _T_610 = lcam_mask_0 & write_mask_6; // @[lsu.scala:263:49, :1150:30, :1665:22] wire _T_607 = _T_610 == lcam_mask_0 & ~stq_6_bits_uop_is_fence & ~stq_6_bits_uop_is_amo & dword_addr_matches_14_0 & can_forward_0; // @[lsu.scala:209:16, :263:49, :1045:29, :1150:{30,44,62,65,81,84,98,123}] assign ldst_forward_matches_0_6 = _T_599 & _T_607; // @[lsu.scala:1052:38, :1149:{29,45,72}, :1150:{62,81,98,123}, :1151:9, :1153:46] reg io_dmem_s1_kill_0_REG_26; // @[lsu.scala:1154:56] wire _T_612 = (\|_T_610) & dword_addr_matches_14_0; // @[lsu.scala:263:49, :1150:30, :1157:{51,60}] reg io_dmem_s1_kill_0_REG_27; // @[lsu.scala:1160:56] wire _T_615 = stq_6_bits_uop_is_fence \| stq_6_bits_uop_is_amo; // @[lsu.scala:209:16, :1163:37] assign ldst_addr_matches_0_6 = _T_599 & (_T_607 \| _T_612 \| _T_615); // @[lsu.scala:1050:38, :1149:{29,45,72}, :1150:{62,81,98,123}, :1151:9, :1152:46, :1157:60, :1158:9, :1159:46, :1163:37, :1164:9, :1165:46] reg io_dmem_s1_kill_0_REG_28; // @[lsu.scala:1166:56] wire _GEN_344 = _T_599 ? (_T_607 ? io_dmem_s1_kill_0_REG_26 : _T_612 ? io_dmem_s1_kill_0_REG_27 : _T_615 ? io_dmem_s1_kill_0_REG_28 : _GEN_334) : _GEN_334; // @[lsu.scala:1149:{29,45,72}, :1150:{62,81,98,123}, :1151:9, :1154:{46,56}, :1157:60, :1158:9, :1160:{46,56}, :1163:37, :1164:9, :1166:{46,56}] wire _GEN_345 = _T_607 \| _T_612; // @[lsu.scala:1150:{62,81,98,123}, :1151:9, :1155:46, :1157:60, :1158:9] wire _GEN_346 = _T_599 ? (_GEN_345 ? ~_searcher_is_older_T_4 & _GEN_336 : ~(_T_615 & _searcher_is_older_T_4) & _GEN_336) : _GEN_336; // @[util.scala:363:52] wire _GEN_347 = _T_599 ? (_GEN_345 ? ~_GEN_234 & _GEN_337 : ~(_T_615 & _GEN_234) & _GEN_337) : _GEN_337; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_348 = _T_599 ? (_GEN_345 ? ~_GEN_235 & _GEN_338 : ~(_T_615 & _GEN_235) & _GEN_338) : _GEN_338; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_349 = _T_599 ? (_GEN_345 ? ~_GEN_236 & _GEN_339 : ~(_T_615 & _GEN_236) & _GEN_339) : _GEN_339; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_350 = _T_599 ? (_GEN_345 ? ~_GEN_237 & _GEN_340 : ~(_T_615 & _GEN_237) & _GEN_340) : _GEN_340; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_351 = _T_599 ? (_GEN_345 ? ~_GEN_238 & _GEN_341 : ~(_T_615 & _GEN_238) & _GEN_341) : _GEN_341; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_352 = _T_599 ? (_GEN_345 ? ~_GEN_239 & _GEN_342 : ~(_T_615 & _GEN_239) & _GEN_342) : _GEN_342; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_353 = _T_599 ? (_GEN_345 ? ~(&lcam_ldq_idx_0) & _GEN_343 : ~(_T_615 & (&lcam_ldq_idx_0)) & _GEN_343) : _GEN_343; // @[lsu.scala:263:49, :1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _dword_addr_matches_T_74 = ~stq_7_bits_addr_is_virtual; // @[lsu.scala:209:16, :1145:31] wire _dword_addr_matches_T_75 = stq_7_bits_addr_valid & _dword_addr_matches_T_74; // @[lsu.scala:209:16, :1144:60, :1145:31] wire [28:0] _dword_addr_matches_T_76 = stq_7_bits_addr_bits[31:3]; // @[lsu.scala:209:16, :1146:38] wire _dword_addr_matches_T_78 = _dword_addr_matches_T_76 == _dword_addr_matches_T_77; // @[lsu.scala:1146:{38,58,74}] wire _dword_addr_matches_T_79 = _dword_addr_matches_T_75 & _dword_addr_matches_T_78; // @[lsu.scala:1144:60, :1145:60, :1146:58] wire dword_addr_matches_15_0 = _dword_addr_matches_T_79; // @[lsu.scala:263:49, :1145:60] wire [7:0] write_mask_7; // @[lsu.scala:1665:22] wire _write_mask_mask_T_105 = stq_7_bits_uop_mem_size == 2'h0; // @[lsu.scala:209:16, :1667:26] wire [2:0] _write_mask_mask_T_106 = stq_7_bits_addr_bits[2:0]; // @[lsu.scala:209:16, :1667:55] wire [14:0] _write_mask_mask_T_107 = 15'h1 << _write_mask_mask_T_106; // @[lsu.scala:1667:{48,55}] wire _write_mask_mask_T_108 = stq_7_bits_uop_mem_size == 2'h1; // @[lsu.scala:209:16, :1668:26] wire [1:0] _write_mask_mask_T_109 = stq_7_bits_addr_bits[2:1]; // @[lsu.scala:209:16, :1668:56] wire [2:0] _write_mask_mask_T_110 = {_write_mask_mask_T_109, 1'h0}; // @[lsu.scala:1668:{56,62}] wire [14:0] _write_mask_mask_T_111 = 15'h3 << _write_mask_mask_T_110; // @[lsu.scala:1668:{48,62}] wire _write_mask_mask_T_112 = stq_7_bits_uop_mem_size == 2'h2; // @[lsu.scala:209:16, :1669:26] wire _write_mask_mask_T_113 = stq_7_bits_addr_bits[2]; // @[lsu.scala:209:16, :1669:46] wire [7:0] _write_mask_mask_T_114 = _write_mask_mask_T_113 ? 8'hF0 : 8'hF; // @[lsu.scala:1669:{41,46}] wire _write_mask_mask_T_115 = &stq_7_bits_uop_mem_size; // @[lsu.scala:209:16, :1670:26] wire [7:0] _write_mask_mask_T_117 = _write_mask_mask_T_112 ? _write_mask_mask_T_114 : 8'hFF; // @[Mux.scala:126:16] wire [14:0] _write_mask_mask_T_118 = _write_mask_mask_T_108 ? _write_mask_mask_T_111 : {7'h0, _write_mask_mask_T_117}; // @[Mux.scala:126:16] wire [14:0] _write_mask_mask_T_119 = _write_mask_mask_T_105 ? _write_mask_mask_T_107 : _write_mask_mask_T_118; // @[Mux.scala:126:16] assign write_mask_7 = _write_mask_mask_T_119[7:0]; // @[Mux.scala:126:16] wire _T_620 = do_ld_search_0 & stq_7_valid & lcam_st_dep_mask_0[7]; // @[lsu.scala:209:16, :263:49, :1149:{29,45,67}] wire [7:0] _T_631 = lcam_mask_0 & write_mask_7; // @[lsu.scala:263:49, :1150:30, :1665:22] wire _T_628 = _T_631 == lcam_mask_0 & ~stq_7_bits_uop_is_fence & ~stq_7_bits_uop_is_amo & dword_addr_matches_15_0 & can_forward_0; // @[lsu.scala:209:16, :263:49, :1045:29, :1150:{30,44,62,65,81,84,98,123}] assign ldst_forward_matches_0_7 = _T_620 & _T_628; // @[lsu.scala:1052:38, :1149:{29,45,72}, :1150:{62,81,98,123}, :1151:9, :1153:46] reg io_dmem_s1_kill_0_REG_29; // @[lsu.scala:1154:56] wire _T_633 = (\|_T_631) & dword_addr_matches_15_0; // @[lsu.scala:263:49, :1150:30, :1157:{51,60}] reg io_dmem_s1_kill_0_REG_30; // @[lsu.scala:1160:56] wire _T_636 = stq_7_bits_uop_is_fence \| stq_7_bits_uop_is_amo; // @[lsu.scala:209:16, :1163:37] assign ldst_addr_matches_0_7 = _T_620 & (_T_628 \| _T_633 \| _T_636); // @[lsu.scala:1050:38, :1149:{29,45,72}, :1150:{62,81,98,123}, :1151:9, :1152:46, :1157:60, :1158:9, :1159:46, :1163:37, :1164:9, :1165:46] reg io_dmem_s1_kill_0_REG_31; // @[lsu.scala:1166:56] assign io_dmem_s1_kill_0_0 = _T_620 ? (_T_628 ? io_dmem_s1_kill_0_REG_29 : _T_633 ? io_dmem_s1_kill_0_REG_30 : _T_636 ? io_dmem_s1_kill_0_REG_31 : _GEN_344) : _GEN_344; // @[lsu.scala:201:7, :1149:{29,45,72}, :1150:{62,81,98,123}, :1151:9, :1154:{46,56}, :1157:60, :1158:9, :1160:{46,56}, :1163:37, :1164:9, :1166:{46,56}] wire _GEN_354 = _T_628 \| _T_633; // @[lsu.scala:1150:{62,81,98,123}, :1151:9, :1155:46, :1157:60, :1158:9] assign s1_set_execute_0 = _T_620 ? (_GEN_354 ? ~_searcher_is_older_T_4 & _GEN_346 : ~(_T_636 & _searcher_is_older_T_4) & _GEN_346) : _GEN_346; // @[util.scala:363:52] assign s1_set_execute_1 = _T_620 ? (_GEN_354 ? ~_GEN_234 & _GEN_347 : ~(_T_636 & _GEN_234) & _GEN_347) : _GEN_347; // @[lsu.scala:1058:36, :1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] assign s1_set_execute_2 = _T_620 ? (_GEN_354 ? ~_GEN_235 & _GEN_348 : ~(_T_636 & _GEN_235) & _GEN_348) : _GEN_348; // @[lsu.scala:1058:36, :1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] assign s1_set_execute_3 = _T_620 ? (_GEN_354 ? ~_GEN_236 & _GEN_349 : ~(_T_636 & _GEN_236) & _GEN_349) : _GEN_349; // @[lsu.scala:1058:36, :1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] assign s1_set_execute_4 = _T_620 ? (_GEN_354 ? ~_GEN_237 & _GEN_350 : ~(_T_636 & _GEN_237) & _GEN_350) : _GEN_350; // @[lsu.scala:1058:36, :1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] assign s1_set_execute_5 = _T_620 ? (_GEN_354 ? ~_GEN_238 & _GEN_351 : ~(_T_636 & _GEN_238) & _GEN_351) : _GEN_351; // @[lsu.scala:1058:36, :1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] assign s1_set_execute_6 = _T_620 ? (_GEN_354 ? ~_GEN_239 & _GEN_352 : ~(_T_636 & _GEN_239) & _GEN_352) : _GEN_352; // @[lsu.scala:1058:36, :1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] assign s1_set_execute_7 = _T_620 ? (_GEN_354 ? ~(&lcam_ldq_idx_0) & _GEN_353 : ~(_T_636 & (&lcam_ldq_idx_0)) & _GEN_353) : _GEN_353; // @[lsu.scala:263:49, :1058:36, :1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire [1:0] forwarding_age_logic_0_io_addr_matches_lo_lo = {ldst_addr_matches_0_1, ldst_addr_matches_0_0}; // @[lsu.scala:1050:38, :1181:72] wire [1:0] forwarding_age_logic_0_io_addr_matches_lo_hi = {ldst_addr_matches_0_3, ldst_addr_matches_0_2}; // @[lsu.scala:1050:38, :1181:72] wire [3:0] forwarding_age_logic_0_io_addr_matches_lo = {forwarding_age_logic_0_io_addr_matches_lo_hi, forwarding_age_logic_0_io_addr_matches_lo_lo}; // @[lsu.scala:1181:72] wire [1:0] forwarding_age_logic_0_io_addr_matches_hi_lo = {ldst_addr_matches_0_5, ldst_addr_matches_0_4}; // @[lsu.scala:1050:38, :1181:72] wire [1:0] forwarding_age_logic_0_io_addr_matches_hi_hi = {ldst_addr_matches_0_7, ldst_addr_matches_0_6}; // @[lsu.scala:1050:38, :1181:72] wire [3:0] forwarding_age_logic_0_io_addr_matches_hi = {forwarding_age_logic_0_io_addr_matches_hi_hi, forwarding_age_logic_0_io_addr_matches_hi_lo}; // @[lsu.scala:1181:72] wire [7:0] _forwarding_age_logic_0_io_addr_matches_T = {forwarding_age_logic_0_io_addr_matches_hi, forwarding_age_logic_0_io_addr_matches_lo}; // @[lsu.scala:1181:72] assign mem_forward_stq_idx_0 = forwarding_idx_0; // @[lsu.scala:263:49, :1063:33] wire [7:0] _GEN_355 = {{ldst_forward_matches_0_7}, {ldst_forward_matches_0_6}, {ldst_forward_matches_0_5}, {ldst_forward_matches_0_4}, {ldst_forward_matches_0_3}, {ldst_forward_matches_0_2}, {ldst_forward_matches_0_1}, {ldst_forward_matches_0_0}}; // @[lsu.scala:1052:38, :1188:86] reg REG_1; // @[lsu.scala:1190:64] assign mem_forward_valid_0 = _GEN_355[forwarding_idx_0] & (io_core_brupdate_b1_mispredict_mask_0 & lcam_uop_0_br_mask) == 8'h0 & ~io_core_exception_0 & ~REG_1; // @[util.scala:118:{51,59}] reg REG_2; // @[lsu.scala:1200:18] reg [3:0] store_blocked_counter; // @[lsu.scala:1205:36] wire _store_blocked_counter_T = &store_blocked_counter; // @[lsu.scala:1205:36, :1209:58] wire [4:0] _store_blocked_counter_T_1 = {1'h0, store_blocked_counter} + 5'h1; // @[lsu.scala:1205:36, :1209:96] wire [3:0] _store_blocked_counter_T_2 = _store_blocked_counter_T_1[3:0]; // @[lsu.scala:1209:96] wire [3:0] _store_blocked_counter_T_3 = _store_blocked_counter_T ? 4'hF : _store_blocked_counter_T_2; // @[lsu.scala:1209:{35,58,96}] assign block_load_wakeup = (&store_blocked_counter) \| REG_2; // @[lsu.scala:499:35, :1200:{18,80}, :1205:36, :1211:{33,43}, :1212:25] wire _io_core_clr_unsafe_0_valid_T = do_st_search_0 \| do_ld_search_0; // @[lsu.scala:263:49, :1221:61] wire _io_core_clr_unsafe_0_valid_T_1 = ~fired_load_wakeup_0; // @[lsu.scala:263:49, :1221:84] wire _io_core_clr_unsafe_0_valid_T_2 = _io_core_clr_unsafe_0_valid_T & _io_core_clr_unsafe_0_valid_T_1; // @[lsu.scala:1221:{61,81,84}] reg io_core_clr_unsafe_0_valid_REG; // @[lsu.scala:1221:43] reg [4:0] io_core_clr_unsafe_0_bits_REG; // @[lsu.scala:1222:43] assign io_core_clr_unsafe_0_bits_0 = io_core_clr_unsafe_0_bits_REG; // @[lsu.scala:201:7, :1222:43] wire _temp_bits_T_1 = failed_loads_0 & _temp_bits_T; // @[lsu.scala:1054:34, :1230:{21,28}] wire _temp_bits_WIRE_0 = _temp_bits_T_1; // @[lsu.scala:1229:59, :1230:21] wire _temp_bits_T_3 = failed_loads_1 & _temp_bits_T_2; // @[lsu.scala:1054:34, :1230:{21,28}] wire _temp_bits_WIRE_1 = _temp_bits_T_3; // @[lsu.scala:1229:59, :1230:21] wire _temp_bits_T_5 = failed_loads_2 & _temp_bits_T_4; // @[lsu.scala:1054:34, :1230:{21,28}] wire _temp_bits_WIRE_2 = _temp_bits_T_5; // @[lsu.scala:1229:59, :1230:21] wire _temp_bits_T_6 = ~_searcher_is_older_T_15; // @[util.scala:351:72, :363:78] wire _temp_bits_T_7 = failed_loads_3 & _temp_bits_T_6; // @[lsu.scala:1054:34, :1230:{21,28}] wire _temp_bits_WIRE_3 = _temp_bits_T_7; // @[lsu.scala:1229:59, :1230:21] wire _temp_bits_T_9 = failed_loads_4 & _temp_bits_T_8; // @[lsu.scala:1054:34, :1230:{21,28}] wire _temp_bits_WIRE_4 = _temp_bits_T_9; // @[lsu.scala:1229:59, :1230:21] wire _temp_bits_T_11 = failed_loads_5 & _temp_bits_T_10; // @[lsu.scala:1054:34, :1230:{21,28}] wire _temp_bits_WIRE_5 = _temp_bits_T_11; // @[lsu.scala:1229:59, :1230:21] wire _temp_bits_T_13 = failed_loads_6 & _temp_bits_T_12; // @[lsu.scala:1054:34, :1230:{21,28}] wire _temp_bits_WIRE_6 = _temp_bits_T_13; // @[lsu.scala:1229:59, :1230:21] wire _temp_bits_WIRE_7 = _temp_bits_T_15; // @[lsu.scala:1229:59, :1230:21] wire _temp_bits_WIRE_1_0 = _temp_bits_WIRE_0; // @[lsu.scala:1229:{27,59}] wire _temp_bits_WIRE_1_1 = _temp_bits_WIRE_1; // @[lsu.scala:1229:{27,59}] wire _temp_bits_WIRE_1_2 = _temp_bits_WIRE_2; // @[lsu.scala:1229:{27,59}] wire _temp_bits_WIRE_1_3 = _temp_bits_WIRE_3; // @[lsu.scala:1229:{27,59}] wire _temp_bits_WIRE_1_4 = _temp_bits_WIRE_4; // @[lsu.scala:1229:{27,59}] wire _temp_bits_WIRE_1_5 = _temp_bits_WIRE_5; // @[lsu.scala:1229:{27,59}] wire _temp_bits_WIRE_1_6 = _temp_bits_WIRE_6; // @[lsu.scala:1229:{27,59}] wire _temp_bits_WIRE_1_7 = _temp_bits_WIRE_7; // @[lsu.scala:1229:{27,59}] wire [1:0] temp_bits_lo_lo_lo = {_temp_bits_WIRE_1_1, _temp_bits_WIRE_1_0}; // @[lsu.scala:1229:27, :1230:59] wire [1:0] temp_bits_lo_lo_hi = {_temp_bits_WIRE_1_3, _temp_bits_WIRE_1_2}; // @[lsu.scala:1229:27, :1230:59] wire [3:0] temp_bits_lo_lo = {temp_bits_lo_lo_hi, temp_bits_lo_lo_lo}; // @[lsu.scala:1230:59] wire [1:0] temp_bits_lo_hi_lo = {_temp_bits_WIRE_1_5, _temp_bits_WIRE_1_4}; // @[lsu.scala:1229:27, :1230:59] wire [1:0] temp_bits_lo_hi_hi = {_temp_bits_WIRE_1_7, _temp_bits_WIRE_1_6}; // @[lsu.scala:1229:27, :1230:59] wire [3:0] temp_bits_lo_hi = {temp_bits_lo_hi_hi, temp_bits_lo_hi_lo}; // @[lsu.scala:1230:59] wire [7:0] temp_bits_lo = {temp_bits_lo_hi, temp_bits_lo_lo}; // @[lsu.scala:1230:59] wire [1:0] temp_bits_hi_lo_lo = {_temp_bits_WIRE_1_9, _temp_bits_WIRE_1_8}; // @[lsu.scala:1229:27, :1230:59] wire [1:0] temp_bits_hi_lo_hi = {_temp_bits_WIRE_1_11, _temp_bits_WIRE_1_10}; // @[lsu.scala:1229:27, :1230:59] wire [3:0] temp_bits_hi_lo = {temp_bits_hi_lo_hi, temp_bits_hi_lo_lo}; // @[lsu.scala:1230:59] wire [1:0] temp_bits_hi_hi_lo = {_temp_bits_WIRE_1_13, _temp_bits_WIRE_1_12}; // @[lsu.scala:1229:27, :1230:59] wire [1:0] temp_bits_hi_hi_hi = {_temp_bits_WIRE_1_15, _temp_bits_WIRE_1_14}; // @[lsu.scala:1229:27, :1230:59] wire [3:0] temp_bits_hi_hi = {temp_bits_hi_hi_hi, temp_bits_hi_hi_lo}; // @[lsu.scala:1230:59] wire [7:0] temp_bits_hi = {temp_bits_hi_hi, temp_bits_hi_lo}; // @[lsu.scala:1230:59] wire [15:0] temp_bits = {temp_bits_hi, temp_bits_lo}; // @[lsu.scala:1230:59] wire _l_idx_T = temp_bits[0]; // @[OneHot.scala:48:45] wire _l_idx_T_1 = temp_bits[1]; // @[OneHot.scala:48:45] wire _l_idx_T_2 = temp_bits[2]; // @[OneHot.scala:48:45] wire _l_idx_T_3 = temp_bits[3]; // @[OneHot.scala:48:45] wire _l_idx_T_4 = temp_bits[4]; // @[OneHot.scala:48:45] wire _l_idx_T_5 = temp_bits[5]; // @[OneHot.scala:48:45] wire _l_idx_T_6 = temp_bits[6]; // @[OneHot.scala:48:45] wire _l_idx_T_7 = temp_bits[7]; // @[OneHot.scala:48:45] wire _l_idx_T_8 = temp_bits[8]; // @[OneHot.scala:48:45] wire _l_idx_T_9 = temp_bits[9]; // @[OneHot.scala:48:45] wire _l_idx_T_10 = temp_bits[10]; // @[OneHot.scala:48:45] wire _l_idx_T_11 = temp_bits[11]; // @[OneHot.scala:48:45] wire _l_idx_T_12 = temp_bits[12]; // @[OneHot.scala:48:45] wire _l_idx_T_13 = temp_bits[13]; // @[OneHot.scala:48:45] wire _l_idx_T_14 = temp_bits[14]; // @[OneHot.scala:48:45] wire _l_idx_T_15 = temp_bits[15]; // @[OneHot.scala:48:45] wire [3:0] _l_idx_T_16 = {3'h7, ~_l_idx_T_14}; // @[OneHot.scala:48:45] wire [3:0] _l_idx_T_17 = _l_idx_T_13 ? 4'hD : _l_idx_T_16; // @[OneHot.scala:48:45] wire [3:0] _l_idx_T_18 = _l_idx_T_12 ? 4'hC : _l_idx_T_17; // @[OneHot.scala:48:45] wire [3:0] _l_idx_T_19 = _l_idx_T_11 ? 4'hB : _l_idx_T_18; // @[OneHot.scala:48:45] wire [3:0] _l_idx_T_20 = _l_idx_T_10 ? 4'hA : _l_idx_T_19; // @[OneHot.scala:48:45] wire [3:0] _l_idx_T_21 = _l_idx_T_9 ? 4'h9 : _l_idx_T_20; // @[OneHot.scala:48:45] wire [3:0] _l_idx_T_22 = _l_idx_T_8 ? 4'h8 : _l_idx_T_21; // @[OneHot.scala:48:45] wire [3:0] _l_idx_T_23 = _l_idx_T_7 ? 4'h7 : _l_idx_T_22; // @[OneHot.scala:48:45] wire [3:0] _l_idx_T_24 = _l_idx_T_6 ? 4'h6 : _l_idx_T_23; // @[OneHot.scala:48:45] wire [3:0] _l_idx_T_25 = _l_idx_T_5 ? 4'h5 : _l_idx_T_24; // @[OneHot.scala:48:45] wire [3:0] _l_idx_T_26 = _l_idx_T_4 ? 4'h4 : _l_idx_T_25; // @[OneHot.scala:48:45] wire [3:0] _l_idx_T_27 = _l_idx_T_3 ? 4'h3 : _l_idx_T_26; // @[OneHot.scala:48:45] wire [3:0] _l_idx_T_28 = _l_idx_T_2 ? 4'h2 : _l_idx_T_27; // @[OneHot.scala:48:45] wire [3:0] _l_idx_T_29 = _l_idx_T_1 ? 4'h1 : _l_idx_T_28; // @[OneHot.scala:48:45] wire [3:0] l_idx = _l_idx_T ? 4'h0 : _l_idx_T_29; // @[OneHot.scala:48:45] reg r_xcpt_valid; // @[lsu.scala:1236:29] reg [6:0] r_xcpt_uop_uopc; // @[lsu.scala:1237:25] assign io_core_lxcpt_bits_uop_uopc_0 = r_xcpt_uop_uopc; // @[lsu.scala:201:7, :1237:25] reg [31:0] r_xcpt_uop_inst; // @[lsu.scala:1237:25] assign io_core_lxcpt_bits_uop_inst_0 = r_xcpt_uop_inst; // @[lsu.scala:201:7, :1237:25] reg [31:0] r_xcpt_uop_debug_inst; // @[lsu.scala:1237:25] assign io_core_lxcpt_bits_uop_debug_inst_0 = r_xcpt_uop_debug_inst; // @[lsu.scala:201:7, :1237:25] reg r_xcpt_uop_is_rvc; // @[lsu.scala:1237:25] assign io_core_lxcpt_bits_uop_is_rvc_0 = r_xcpt_uop_is_rvc; // @[lsu.scala:201:7, :1237:25] reg [39:0] r_xcpt_uop_debug_pc; // @[lsu.scala:1237:25] assign io_core_lxcpt_bits_uop_debug_pc_0 = r_xcpt_uop_debug_pc; // @[lsu.scala:201:7, :1237:25] reg [2:0] r_xcpt_uop_iq_type; // @[lsu.scala:1237:25] assign io_core_lxcpt_bits_uop_iq_type_0 = r_xcpt_uop_iq_type; // @[lsu.scala:201:7, :1237:25] reg [9:0] r_xcpt_uop_fu_code; // @[lsu.scala:1237:25] assign io_core_lxcpt_bits_uop_fu_code_0 = r_xcpt_uop_fu_code; // @[lsu.scala:201:7, :1237:25] reg [3:0] r_xcpt_uop_ctrl_br_type; // @[lsu.scala:1237:25] assign io_core_lxcpt_bits_uop_ctrl_br_type_0 = r_xcpt_uop_ctrl_br_type; // @[lsu.scala:201:7, :1237:25] reg [1:0] r_xcpt_uop_ctrl_op1_sel; // @[lsu.scala:1237:25] assign io_core_lxcpt_bits_uop_ctrl_op1_sel_0 = r_xcpt_uop_ctrl_op1_sel; // @[lsu.scala:201:7, :1237:25] reg [2:0] r_xcpt_uop_ctrl_op2_sel; // @[lsu.scala:1237:25] assign io_core_lxcpt_bits_uop_ctrl_op2_sel_0 = r_xcpt_uop_ctrl_op2_sel; // @[lsu.scala:201:7, :1237:25] reg [2:0] r_xcpt_uop_ctrl_imm_sel; // @[lsu.scala:1237:25] assign io_core_lxcpt_bits_uop_ctrl_imm_sel_0 = r_xcpt_uop_ctrl_imm_sel; // @[lsu.scala:201:7, :1237:25] reg [4:0] r_xcpt_uop_ctrl_op_fcn; // @[lsu.scala:1237:25] assign io_core_lxcpt_bits_uop_ctrl_op_fcn_0 = r_xcpt_uop_ctrl_op_fcn; // @[lsu.scala:201:7, :1237:25] reg r_xcpt_uop_ctrl_fcn_dw; // @[lsu.scala:1237:25] assign io_core_lxcpt_bits_uop_ctrl_fcn_dw_0 = r_xcpt_uop_ctrl_fcn_dw; // @[lsu.scala:201:7, :1237:25] reg [2:0] r_xcpt_uop_ctrl_csr_cmd; // @[lsu.scala:1237:25] assign io_core_lxcpt_bits_uop_ctrl_csr_cmd_0 = r_xcpt_uop_ctrl_csr_cmd; // @[lsu.scala:201:7, :1237:25] reg r_xcpt_uop_ctrl_is_load; // @[lsu.scala:1237:25] assign io_core_lxcpt_bits_uop_ctrl_is_load_0 = r_xcpt_uop_ctrl_is_load; // @[lsu.scala:201:7, :1237:25] reg r_xcpt_uop_ctrl_is_sta; // @[lsu.scala:1237:25] assign io_core_lxcpt_bits_uop_ctrl_is_sta_0 = r_xcpt_uop_ctrl_is_sta; // @[lsu.scala:201:7, :1237:25] reg r_xcpt_uop_ctrl_is_std; // @[lsu.scala:1237:25] assign io_core_lxcpt_bits_uop_ctrl_is_std_0 = r_xcpt_uop_ctrl_is_std; // @[lsu.scala:201:7, :1237:25] reg [1:0] r_xcpt_uop_iw_state; // @[lsu.scala:1237:25] assign io_core_lxcpt_bits_uop_iw_state_0 = r_xcpt_uop_iw_state; // @[lsu.scala:201:7, :1237:25] reg r_xcpt_uop_iw_p1_poisoned; // @[lsu.scala:1237:25] assign io_core_lxcpt_bits_uop_iw_p1_poisoned_0 = r_xcpt_uop_iw_p1_poisoned; // @[lsu.scala:201:7, :1237:25] reg r_xcpt_uop_iw_p2_poisoned; // @[lsu.scala:1237:25] assign io_core_lxcpt_bits_uop_iw_p2_poisoned_0 = r_xcpt_uop_iw_p2_poisoned; // @[lsu.scala:201:7, :1237:25] reg r_xcpt_uop_is_br; // @[lsu.scala:1237:25] assign io_core_lxcpt_bits_uop_is_br_0 = r_xcpt_uop_is_br; // @[lsu.scala:201:7, :1237:25] reg r_xcpt_uop_is_jalr; // @[lsu.scala:1237:25] assign io_core_lxcpt_bits_uop_is_jalr_0 = r_xcpt_uop_is_jalr; // @[lsu.scala:201:7, :1237:25] reg r_xcpt_uop_is_jal; // @[lsu.scala:1237:25] assign io_core_lxcpt_bits_uop_is_jal_0 = r_xcpt_uop_is_jal; // @[lsu.scala:201:7, :1237:25] reg r_xcpt_uop_is_sfb; // @[lsu.scala:1237:25] assign io_core_lxcpt_bits_uop_is_sfb_0 = r_xcpt_uop_is_sfb; // @[lsu.scala:201:7, :1237:25] reg [7:0] r_xcpt_uop_br_mask; // @[lsu.scala:1237:25] assign io_core_lxcpt_bits_uop_br_mask_0 = r_xcpt_uop_br_mask; // @[lsu.scala:201:7, :1237:25] reg [2:0] r_xcpt_uop_br_tag; // @[lsu.scala:1237:25] assign io_core_lxcpt_bits_uop_br_tag_0 = r_xcpt_uop_br_tag; // @[lsu.scala:201:7, :1237:25] reg [3:0] r_xcpt_uop_ftq_idx; // @[lsu.scala:1237:25] assign io_core_lxcpt_bits_uop_ftq_idx_0 = r_xcpt_uop_ftq_idx; // @[lsu.scala:201:7, :1237:25] reg r_xcpt_uop_edge_inst; // @[lsu.scala:1237:25] assign io_core_lxcpt_bits_uop_edge_inst_0 = r_xcpt_uop_edge_inst; // @[lsu.scala:201:7, :1237:25] reg [5:0] r_xcpt_uop_pc_lob; // @[lsu.scala:1237:25] assign io_core_lxcpt_bits_uop_pc_lob_0 = r_xcpt_uop_pc_lob; // @[lsu.scala:201:7, :1237:25] reg r_xcpt_uop_taken; // @[lsu.scala:1237:25] assign io_core_lxcpt_bits_uop_taken_0 = r_xcpt_uop_taken; // @[lsu.scala:201:7, :1237:25] reg [19:0] r_xcpt_uop_imm_packed; // @[lsu.scala:1237:25] assign io_core_lxcpt_bits_uop_imm_packed_0 = r_xcpt_uop_imm_packed; // @[lsu.scala:201:7, :1237:25] reg [11:0] r_xcpt_uop_csr_addr; // @[lsu.scala:1237:25] assign io_core_lxcpt_bits_uop_csr_addr_0 = r_xcpt_uop_csr_addr; // @[lsu.scala:201:7, :1237:25] reg [4:0] r_xcpt_uop_rob_idx; // @[lsu.scala:1237:25] assign io_core_lxcpt_bits_uop_rob_idx_0 = r_xcpt_uop_rob_idx; // @[lsu.scala:201:7, :1237:25] reg [2:0] r_xcpt_uop_ldq_idx; // @[lsu.scala:1237:25] assign io_core_lxcpt_bits_uop_ldq_idx_0 = r_xcpt_uop_ldq_idx; // @[lsu.scala:201:7, :1237:25] reg [2:0] r_xcpt_uop_stq_idx; // @[lsu.scala:1237:25] assign io_core_lxcpt_bits_uop_stq_idx_0 = r_xcpt_uop_stq_idx; // @[lsu.scala:201:7, :1237:25] reg [1:0] r_xcpt_uop_rxq_idx; // @[lsu.scala:1237:25] assign io_core_lxcpt_bits_uop_rxq_idx_0 = r_xcpt_uop_rxq_idx; // @[lsu.scala:201:7, :1237:25] reg [5:0] r_xcpt_uop_pdst; // @[lsu.scala:1237:25] assign io_core_lxcpt_bits_uop_pdst_0 = r_xcpt_uop_pdst; // @[lsu.scala:201:7, :1237:25] reg [5:0] r_xcpt_uop_prs1; // @[lsu.scala:1237:25] assign io_core_lxcpt_bits_uop_prs1_0 = r_xcpt_uop_prs1; // @[lsu.scala:201:7, :1237:25] reg [5:0] r_xcpt_uop_prs2; // @[lsu.scala:1237:25] assign io_core_lxcpt_bits_uop_prs2_0 = r_xcpt_uop_prs2; // @[lsu.scala:201:7, :1237:25] reg [5:0] r_xcpt_uop_prs3; // @[lsu.scala:1237:25] assign io_core_lxcpt_bits_uop_prs3_0 = r_xcpt_uop_prs3; // @[lsu.scala:201:7, :1237:25] reg [3:0] r_xcpt_uop_ppred; // @[lsu.scala:1237:25] assign io_core_lxcpt_bits_uop_ppred_0 = r_xcpt_uop_ppred; // @[lsu.scala:201:7, :1237:25] reg r_xcpt_uop_prs1_busy; // @[lsu.scala:1237:25] assign io_core_lxcpt_bits_uop_prs1_busy_0 = r_xcpt_uop_prs1_busy; // @[lsu.scala:201:7, :1237:25] reg r_xcpt_uop_prs2_busy; // @[lsu.scala:1237:25] assign io_core_lxcpt_bits_uop_prs2_busy_0 = r_xcpt_uop_prs2_busy; // @[lsu.scala:201:7, :1237:25] reg r_xcpt_uop_prs3_busy; // @[lsu.scala:1237:25] assign io_core_lxcpt_bits_uop_prs3_busy_0 = r_xcpt_uop_prs3_busy; // @[lsu.scala:201:7, :1237:25] reg r_xcpt_uop_ppred_busy; // @[lsu.scala:1237:25] assign io_core_lxcpt_bits_uop_ppred_busy_0 = r_xcpt_uop_ppred_busy; // @[lsu.scala:201:7, :1237:25] reg [5:0] r_xcpt_uop_stale_pdst; // @[lsu.scala:1237:25] assign io_core_lxcpt_bits_uop_stale_pdst_0 = r_xcpt_uop_stale_pdst; // @[lsu.scala:201:7, :1237:25] reg r_xcpt_uop_exception; // @[lsu.scala:1237:25] assign io_core_lxcpt_bits_uop_exception_0 = r_xcpt_uop_exception; // @[lsu.scala:201:7, :1237:25] reg [63:0] r_xcpt_uop_exc_cause; // @[lsu.scala:1237:25] assign io_core_lxcpt_bits_uop_exc_cause_0 = r_xcpt_uop_exc_cause; // @[lsu.scala:201:7, :1237:25] reg r_xcpt_uop_bypassable; // @[lsu.scala:1237:25] assign io_core_lxcpt_bits_uop_bypassable_0 = r_xcpt_uop_bypassable; // @[lsu.scala:201:7, :1237:25] reg [4:0] r_xcpt_uop_mem_cmd; // @[lsu.scala:1237:25] assign io_core_lxcpt_bits_uop_mem_cmd_0 = r_xcpt_uop_mem_cmd; // @[lsu.scala:201:7, :1237:25] reg [1:0] r_xcpt_uop_mem_size; // @[lsu.scala:1237:25] assign io_core_lxcpt_bits_uop_mem_size_0 = r_xcpt_uop_mem_size; // @[lsu.scala:201:7, :1237:25] reg r_xcpt_uop_mem_signed; // @[lsu.scala:1237:25] assign io_core_lxcpt_bits_uop_mem_signed_0 = r_xcpt_uop_mem_signed; // @[lsu.scala:201:7, :1237:25] reg r_xcpt_uop_is_fence; // @[lsu.scala:1237:25] assign io_core_lxcpt_bits_uop_is_fence_0 = r_xcpt_uop_is_fence; // @[lsu.scala:201:7, :1237:25] reg r_xcpt_uop_is_fencei; // @[lsu.scala:1237:25] assign io_core_lxcpt_bits_uop_is_fencei_0 = r_xcpt_uop_is_fencei; // @[lsu.scala:201:7, :1237:25] reg r_xcpt_uop_is_amo; // @[lsu.scala:1237:25] assign io_core_lxcpt_bits_uop_is_amo_0 = r_xcpt_uop_is_amo; // @[lsu.scala:201:7, :1237:25] reg r_xcpt_uop_uses_ldq; // @[lsu.scala:1237:25] assign io_core_lxcpt_bits_uop_uses_ldq_0 = r_xcpt_uop_uses_ldq; // @[lsu.scala:201:7, :1237:25] reg r_xcpt_uop_uses_stq; // @[lsu.scala:1237:25] assign io_core_lxcpt_bits_uop_uses_stq_0 = r_xcpt_uop_uses_stq; // @[lsu.scala:201:7, :1237:25] reg r_xcpt_uop_is_sys_pc2epc; // @[lsu.scala:1237:25] assign io_core_lxcpt_bits_uop_is_sys_pc2epc_0 = r_xcpt_uop_is_sys_pc2epc; // @[lsu.scala:201:7, :1237:25] reg r_xcpt_uop_is_unique; // @[lsu.scala:1237:25] assign io_core_lxcpt_bits_uop_is_unique_0 = r_xcpt_uop_is_unique; // @[lsu.scala:201:7, :1237:25] reg r_xcpt_uop_flush_on_commit; // @[lsu.scala:1237:25] assign io_core_lxcpt_bits_uop_flush_on_commit_0 = r_xcpt_uop_flush_on_commit; // @[lsu.scala:201:7, :1237:25] reg r_xcpt_uop_ldst_is_rs1; // @[lsu.scala:1237:25] assign io_core_lxcpt_bits_uop_ldst_is_rs1_0 = r_xcpt_uop_ldst_is_rs1; // @[lsu.scala:201:7, :1237:25] reg [5:0] r_xcpt_uop_ldst; // @[lsu.scala:1237:25] assign io_core_lxcpt_bits_uop_ldst_0 = r_xcpt_uop_ldst; // @[lsu.scala:201:7, :1237:25] reg [5:0] r_xcpt_uop_lrs1; // @[lsu.scala:1237:25] assign io_core_lxcpt_bits_uop_lrs1_0 = r_xcpt_uop_lrs1; // @[lsu.scala:201:7, :1237:25] reg [5:0] r_xcpt_uop_lrs2; // @[lsu.scala:1237:25] assign io_core_lxcpt_bits_uop_lrs2_0 = r_xcpt_uop_lrs2; // @[lsu.scala:201:7, :1237:25] reg [5:0] r_xcpt_uop_lrs3; // @[lsu.scala:1237:25] assign io_core_lxcpt_bits_uop_lrs3_0 = r_xcpt_uop_lrs3; // @[lsu.scala:201:7, :1237:25] reg r_xcpt_uop_ldst_val; // @[lsu.scala:1237:25] assign io_core_lxcpt_bits_uop_ldst_val_0 = r_xcpt_uop_ldst_val; // @[lsu.scala:201:7, :1237:25] reg [1:0] r_xcpt_uop_dst_rtype; // @[lsu.scala:1237:25] assign io_core_lxcpt_bits_uop_dst_rtype_0 = r_xcpt_uop_dst_rtype; // @[lsu.scala:201:7, :1237:25] reg [1:0] r_xcpt_uop_lrs1_rtype; // @[lsu.scala:1237:25] assign io_core_lxcpt_bits_uop_lrs1_rtype_0 = r_xcpt_uop_lrs1_rtype; // @[lsu.scala:201:7, :1237:25] reg [1:0] r_xcpt_uop_lrs2_rtype; // @[lsu.scala:1237:25] assign io_core_lxcpt_bits_uop_lrs2_rtype_0 = r_xcpt_uop_lrs2_rtype; // @[lsu.scala:201:7, :1237:25] reg r_xcpt_uop_frs3_en; // @[lsu.scala:1237:25] assign io_core_lxcpt_bits_uop_frs3_en_0 = r_xcpt_uop_frs3_en; // @[lsu.scala:201:7, :1237:25] reg r_xcpt_uop_fp_val; // @[lsu.scala:1237:25] assign io_core_lxcpt_bits_uop_fp_val_0 = r_xcpt_uop_fp_val; // @[lsu.scala:201:7, :1237:25] reg r_xcpt_uop_fp_single; // @[lsu.scala:1237:25] assign io_core_lxcpt_bits_uop_fp_single_0 = r_xcpt_uop_fp_single; // @[lsu.scala:201:7, :1237:25] reg r_xcpt_uop_xcpt_pf_if; // @[lsu.scala:1237:25] assign io_core_lxcpt_bits_uop_xcpt_pf_if_0 = r_xcpt_uop_xcpt_pf_if; // @[lsu.scala:201:7, :1237:25] reg r_xcpt_uop_xcpt_ae_if; // @[lsu.scala:1237:25] assign io_core_lxcpt_bits_uop_xcpt_ae_if_0 = r_xcpt_uop_xcpt_ae_if; // @[lsu.scala:201:7, :1237:25] reg r_xcpt_uop_xcpt_ma_if; // @[lsu.scala:1237:25] assign io_core_lxcpt_bits_uop_xcpt_ma_if_0 = r_xcpt_uop_xcpt_ma_if; // @[lsu.scala:201:7, :1237:25] reg r_xcpt_uop_bp_debug_if; // @[lsu.scala:1237:25] assign io_core_lxcpt_bits_uop_bp_debug_if_0 = r_xcpt_uop_bp_debug_if; // @[lsu.scala:201:7, :1237:25] reg r_xcpt_uop_bp_xcpt_if; // @[lsu.scala:1237:25] assign io_core_lxcpt_bits_uop_bp_xcpt_if_0 = r_xcpt_uop_bp_xcpt_if; // @[lsu.scala:201:7, :1237:25] reg [1:0] r_xcpt_uop_debug_fsrc; // @[lsu.scala:1237:25] assign io_core_lxcpt_bits_uop_debug_fsrc_0 = r_xcpt_uop_debug_fsrc; // @[lsu.scala:201:7, :1237:25] reg [1:0] r_xcpt_uop_debug_tsrc; // @[lsu.scala:1237:25] assign io_core_lxcpt_bits_uop_debug_tsrc_0 = r_xcpt_uop_debug_tsrc; // @[lsu.scala:201:7, :1237:25] reg [4:0] r_xcpt_cause; // @[lsu.scala:1237:25] assign io_core_lxcpt_bits_cause_0 = r_xcpt_cause; // @[lsu.scala:201:7, :1237:25] reg [39:0] r_xcpt_badvaddr; // @[lsu.scala:1237:25] assign io_core_lxcpt_bits_badvaddr_0 = r_xcpt_badvaddr; // @[lsu.scala:201:7, :1237:25] wire _ld_xcpt_valid_T = failed_loads_0 \| failed_loads_1; // @[lsu.scala:1054:34, :1239:44] wire _ld_xcpt_valid_T_1 = _ld_xcpt_valid_T \| failed_loads_2; // @[lsu.scala:1054:34, :1239:44] wire _ld_xcpt_valid_T_2 = _ld_xcpt_valid_T_1 \| failed_loads_3; // @[lsu.scala:1054:34, :1239:44] wire _ld_xcpt_valid_T_3 = _ld_xcpt_valid_T_2 \| failed_loads_4; // @[lsu.scala:1054:34, :1239:44] wire _ld_xcpt_valid_T_4 = _ld_xcpt_valid_T_3 \| failed_loads_5; // @[lsu.scala:1054:34, :1239:44] wire _ld_xcpt_valid_T_5 = _ld_xcpt_valid_T_4 \| failed_loads_6; // @[lsu.scala:1054:34, :1239:44] wire ld_xcpt_valid = _ld_xcpt_valid_T_5 \| failed_loads_7; // @[lsu.scala:1054:34, :1239:44] wire _ld_xcpt_uop_T = l_idx[3]; // @[Mux.scala:50:70] wire [4:0] _ld_xcpt_uop_T_1 = {1'h0, l_idx} - 5'h8; // @[Mux.scala:50:70] wire [3:0] _ld_xcpt_uop_T_2 = _ld_xcpt_uop_T_1[3:0]; // @[lsu.scala:1240:63] wire [3:0] _ld_xcpt_uop_T_3 = _ld_xcpt_uop_T ? _ld_xcpt_uop_T_2 : l_idx; // @[Mux.scala:50:70] wire [2:0] _ld_xcpt_uop_T_4 = _ld_xcpt_uop_T_3[2:0]; // @[lsu.scala:1240:30] wire _use_mem_xcpt_T = mem_xcpt_uop_rob_idx < _GEN_126[_ld_xcpt_uop_T_4]; // @[util.scala:363:52] wire _use_mem_xcpt_T_1 = mem_xcpt_uop_rob_idx < io_core_rob_head_idx_0; // @[util.scala:363:64] wire _use_mem_xcpt_T_2 = _use_mem_xcpt_T ^ _use_mem_xcpt_T_1; // @[util.scala:363:{52,58,64}] wire _use_mem_xcpt_T_3 = _GEN_126[_ld_xcpt_uop_T_4] < io_core_rob_head_idx_0; // @[util.scala:363:{52,78}] wire _use_mem_xcpt_T_4 = _use_mem_xcpt_T_2 ^ _use_mem_xcpt_T_3; // @[util.scala:363:{58,72,78}] wire _use_mem_xcpt_T_5 = mem_xcpt_valid & _use_mem_xcpt_T_4; // @[util.scala:363:72] wire _use_mem_xcpt_T_6 = ~ld_xcpt_valid; // @[lsu.scala:1239:44, :1242:118] wire use_mem_xcpt = _use_mem_xcpt_T_5 \| _use_mem_xcpt_T_6; // @[lsu.scala:1242:{38,115,118}] wire [6:0] xcpt_uop_uopc = use_mem_xcpt ? mem_xcpt_uop_uopc : _GEN_94[_ld_xcpt_uop_T_4]; // @[util.scala:363:52] wire [31:0] xcpt_uop_inst = use_mem_xcpt ? mem_xcpt_uop_inst : _GEN_95[_ld_xcpt_uop_T_4]; // @[util.scala:363:52] wire [31:0] xcpt_uop_debug_inst = use_mem_xcpt ? mem_xcpt_uop_debug_inst : _GEN_96[_ld_xcpt_uop_T_4]; // @[util.scala:363:52] wire xcpt_uop_is_rvc = use_mem_xcpt ? mem_xcpt_uop_is_rvc : _GEN_97[_ld_xcpt_uop_T_4]; // @[util.scala:363:52] wire [39:0] xcpt_uop_debug_pc = use_mem_xcpt ? mem_xcpt_uop_debug_pc : _GEN_98[_ld_xcpt_uop_T_4]; // @[util.scala:363:52] wire [2:0] xcpt_uop_iq_type = use_mem_xcpt ? mem_xcpt_uop_iq_type : _GEN_99[_ld_xcpt_uop_T_4]; // @[util.scala:363:52] wire [9:0] xcpt_uop_fu_code = use_mem_xcpt ? mem_xcpt_uop_fu_code : _GEN_100[_ld_xcpt_uop_T_4]; // @[util.scala:363:52] wire [3:0] xcpt_uop_ctrl_br_type = use_mem_xcpt ? mem_xcpt_uop_ctrl_br_type : _GEN_101[_ld_xcpt_uop_T_4]; // @[util.scala:363:52] wire [1:0] xcpt_uop_ctrl_op1_sel = use_mem_xcpt ? mem_xcpt_uop_ctrl_op1_sel : _GEN_102[_ld_xcpt_uop_T_4]; // @[util.scala:363:52] wire [2:0] xcpt_uop_ctrl_op2_sel = use_mem_xcpt ? mem_xcpt_uop_ctrl_op2_sel : _GEN_103[_ld_xcpt_uop_T_4]; // @[util.scala:363:52] wire [2:0] xcpt_uop_ctrl_imm_sel = use_mem_xcpt ? mem_xcpt_uop_ctrl_imm_sel : _GEN_104[_ld_xcpt_uop_T_4]; // @[util.scala:363:52] wire [4:0] xcpt_uop_ctrl_op_fcn = use_mem_xcpt ? mem_xcpt_uop_ctrl_op_fcn : _GEN_105[_ld_xcpt_uop_T_4]; // @[util.scala:363:52] wire xcpt_uop_ctrl_fcn_dw = use_mem_xcpt ? mem_xcpt_uop_ctrl_fcn_dw : _GEN_106[_ld_xcpt_uop_T_4]; // @[util.scala:363:52] wire [2:0] xcpt_uop_ctrl_csr_cmd = use_mem_xcpt ? mem_xcpt_uop_ctrl_csr_cmd : _GEN_107[_ld_xcpt_uop_T_4]; // @[util.scala:363:52] wire xcpt_uop_ctrl_is_load = use_mem_xcpt ? mem_xcpt_uop_ctrl_is_load : _GEN_108[_ld_xcpt_uop_T_4]; // @[util.scala:363:52] wire xcpt_uop_ctrl_is_sta = use_mem_xcpt ? mem_xcpt_uop_ctrl_is_sta : _GEN_109[_ld_xcpt_uop_T_4]; // @[util.scala:363:52] wire xcpt_uop_ctrl_is_std = use_mem_xcpt ? mem_xcpt_uop_ctrl_is_std : _GEN_110[_ld_xcpt_uop_T_4]; // @[util.scala:363:52] wire [1:0] xcpt_uop_iw_state = use_mem_xcpt ? mem_xcpt_uop_iw_state : _GEN_111[_ld_xcpt_uop_T_4]; // @[util.scala:363:52] wire xcpt_uop_iw_p1_poisoned = use_mem_xcpt ? mem_xcpt_uop_iw_p1_poisoned : _GEN_112[_ld_xcpt_uop_T_4]; // @[util.scala:363:52] wire xcpt_uop_iw_p2_poisoned = use_mem_xcpt ? mem_xcpt_uop_iw_p2_poisoned : _GEN_113[_ld_xcpt_uop_T_4]; // @[util.scala:363:52] wire xcpt_uop_is_br = use_mem_xcpt ? mem_xcpt_uop_is_br : _GEN_114[_ld_xcpt_uop_T_4]; // @[util.scala:363:52] wire xcpt_uop_is_jalr = use_mem_xcpt ? mem_xcpt_uop_is_jalr : _GEN_115[_ld_xcpt_uop_T_4]; // @[util.scala:363:52] wire xcpt_uop_is_jal = use_mem_xcpt ? mem_xcpt_uop_is_jal : _GEN_116[_ld_xcpt_uop_T_4]; // @[util.scala:363:52] wire xcpt_uop_is_sfb = use_mem_xcpt ? mem_xcpt_uop_is_sfb : _GEN_117[_ld_xcpt_uop_T_4]; // @[util.scala:363:52] wire [7:0] xcpt_uop_br_mask = use_mem_xcpt ? mem_xcpt_uop_br_mask : _GEN_118[_ld_xcpt_uop_T_4]; // @[util.scala:363:52] wire [2:0] xcpt_uop_br_tag = use_mem_xcpt ? mem_xcpt_uop_br_tag : _GEN_119[_ld_xcpt_uop_T_4]; // @[util.scala:363:52] wire [3:0] xcpt_uop_ftq_idx = use_mem_xcpt ? mem_xcpt_uop_ftq_idx : _GEN_120[_ld_xcpt_uop_T_4]; // @[util.scala:363:52] wire xcpt_uop_edge_inst = use_mem_xcpt ? mem_xcpt_uop_edge_inst : _GEN_121[_ld_xcpt_uop_T_4]; // @[util.scala:363:52] wire [5:0] xcpt_uop_pc_lob = use_mem_xcpt ? mem_xcpt_uop_pc_lob : _GEN_122[_ld_xcpt_uop_T_4]; // @[util.scala:363:52] wire xcpt_uop_taken = use_mem_xcpt ? mem_xcpt_uop_taken : _GEN_123[_ld_xcpt_uop_T_4]; // @[util.scala:363:52] wire [19:0] xcpt_uop_imm_packed = use_mem_xcpt ? mem_xcpt_uop_imm_packed : _GEN_124[_ld_xcpt_uop_T_4]; // @[util.scala:363:52] wire [11:0] xcpt_uop_csr_addr = use_mem_xcpt ? mem_xcpt_uop_csr_addr : _GEN_125[_ld_xcpt_uop_T_4]; // @[util.scala:363:52] wire [4:0] xcpt_uop_rob_idx = use_mem_xcpt ? mem_xcpt_uop_rob_idx : _GEN_126[_ld_xcpt_uop_T_4]; // @[util.scala:363:52] wire [2:0] xcpt_uop_ldq_idx = use_mem_xcpt ? mem_xcpt_uop_ldq_idx : _GEN_127[_ld_xcpt_uop_T_4]; // @[util.scala:363:52] wire [2:0] xcpt_uop_stq_idx = use_mem_xcpt ? mem_xcpt_uop_stq_idx : _GEN_128[_ld_xcpt_uop_T_4]; // @[util.scala:363:52] wire [1:0] xcpt_uop_rxq_idx = use_mem_xcpt ? mem_xcpt_uop_rxq_idx : _GEN_129[_ld_xcpt_uop_T_4]; // @[util.scala:363:52] wire [5:0] xcpt_uop_pdst = use_mem_xcpt ? mem_xcpt_uop_pdst : _GEN_130[_ld_xcpt_uop_T_4]; // @[util.scala:363:52] wire [5:0] xcpt_uop_prs1 = use_mem_xcpt ? mem_xcpt_uop_prs1 : _GEN_131[_ld_xcpt_uop_T_4]; // @[util.scala:363:52] wire [5:0] xcpt_uop_prs2 = use_mem_xcpt ? mem_xcpt_uop_prs2 : _GEN_132[_ld_xcpt_uop_T_4]; // @[util.scala:363:52] wire [5:0] xcpt_uop_prs3 = use_mem_xcpt ? mem_xcpt_uop_prs3 : _GEN_133[_ld_xcpt_uop_T_4]; // @[util.scala:363:52] wire [3:0] xcpt_uop_ppred = use_mem_xcpt ? mem_xcpt_uop_ppred : 4'h0; // @[lsu.scala:360:29, :1242:115, :1244:21] wire xcpt_uop_prs1_busy = use_mem_xcpt ? mem_xcpt_uop_prs1_busy : _GEN_134[_ld_xcpt_uop_T_4]; // @[util.scala:363:52] wire xcpt_uop_prs2_busy = use_mem_xcpt ? mem_xcpt_uop_prs2_busy : _GEN_135[_ld_xcpt_uop_T_4]; // @[util.scala:363:52] wire xcpt_uop_prs3_busy = use_mem_xcpt ? mem_xcpt_uop_prs3_busy : _GEN_136[_ld_xcpt_uop_T_4]; // @[util.scala:363:52] wire xcpt_uop_ppred_busy = use_mem_xcpt & mem_xcpt_uop_ppred_busy; // @[lsu.scala:360:29, :1242:115, :1244:21] wire [5:0] xcpt_uop_stale_pdst = use_mem_xcpt ? mem_xcpt_uop_stale_pdst : _GEN_137[_ld_xcpt_uop_T_4]; // @[util.scala:363:52] wire xcpt_uop_exception = use_mem_xcpt ? mem_xcpt_uop_exception : _GEN_138[_ld_xcpt_uop_T_4]; // @[util.scala:363:52] wire [63:0] xcpt_uop_exc_cause = use_mem_xcpt ? mem_xcpt_uop_exc_cause : _GEN_139[_ld_xcpt_uop_T_4]; // @[util.scala:363:52] wire xcpt_uop_bypassable = use_mem_xcpt ? mem_xcpt_uop_bypassable : _GEN_140[_ld_xcpt_uop_T_4]; // @[util.scala:363:52] wire [4:0] xcpt_uop_mem_cmd = use_mem_xcpt ? mem_xcpt_uop_mem_cmd : _GEN_141[_ld_xcpt_uop_T_4]; // @[util.scala:363:52] wire [1:0] xcpt_uop_mem_size = use_mem_xcpt ? mem_xcpt_uop_mem_size : _GEN_142[_ld_xcpt_uop_T_4]; // @[util.scala:363:52] wire xcpt_uop_mem_signed = use_mem_xcpt ? mem_xcpt_uop_mem_signed : _GEN_143[_ld_xcpt_uop_T_4]; // @[util.scala:363:52] wire xcpt_uop_is_fence = use_mem_xcpt ? mem_xcpt_uop_is_fence : _GEN_144[_ld_xcpt_uop_T_4]; // @[util.scala:363:52] wire xcpt_uop_is_fencei = use_mem_xcpt ? mem_xcpt_uop_is_fencei : _GEN_145[_ld_xcpt_uop_T_4]; // @[util.scala:363:52] wire xcpt_uop_is_amo = use_mem_xcpt ? mem_xcpt_uop_is_amo : _GEN_146[_ld_xcpt_uop_T_4]; // @[util.scala:363:52] wire xcpt_uop_uses_ldq = use_mem_xcpt ? mem_xcpt_uop_uses_ldq : _GEN_147[_ld_xcpt_uop_T_4]; // @[util.scala:363:52] wire xcpt_uop_uses_stq = use_mem_xcpt ? mem_xcpt_uop_uses_stq : _GEN_148[_ld_xcpt_uop_T_4]; // @[util.scala:363:52] wire xcpt_uop_is_sys_pc2epc = use_mem_xcpt ? mem_xcpt_uop_is_sys_pc2epc : _GEN_149[_ld_xcpt_uop_T_4]; // @[util.scala:363:52] wire xcpt_uop_is_unique = use_mem_xcpt ? mem_xcpt_uop_is_unique : _GEN_150[_ld_xcpt_uop_T_4]; // @[util.scala:363:52] wire xcpt_uop_flush_on_commit = use_mem_xcpt ? mem_xcpt_uop_flush_on_commit : _GEN_151[_ld_xcpt_uop_T_4]; // @[util.scala:363:52] wire xcpt_uop_ldst_is_rs1 = use_mem_xcpt ? mem_xcpt_uop_ldst_is_rs1 : _GEN_152[_ld_xcpt_uop_T_4]; // @[util.scala:363:52] wire [5:0] xcpt_uop_ldst = use_mem_xcpt ? mem_xcpt_uop_ldst : _GEN_153[_ld_xcpt_uop_T_4]; // @[util.scala:363:52] wire [5:0] xcpt_uop_lrs1 = use_mem_xcpt ? mem_xcpt_uop_lrs1 : _GEN_154[_ld_xcpt_uop_T_4]; // @[util.scala:363:52] wire [5:0] xcpt_uop_lrs2 = use_mem_xcpt ? mem_xcpt_uop_lrs2 : _GEN_155[_ld_xcpt_uop_T_4]; // @[util.scala:363:52] wire [5:0] xcpt_uop_lrs3 = use_mem_xcpt ? mem_xcpt_uop_lrs3 : _GEN_156[_ld_xcpt_uop_T_4]; // @[util.scala:363:52] wire xcpt_uop_ldst_val = use_mem_xcpt ? mem_xcpt_uop_ldst_val : _GEN_157[_ld_xcpt_uop_T_4]; // @[util.scala:363:52] wire [1:0] xcpt_uop_dst_rtype = use_mem_xcpt ? mem_xcpt_uop_dst_rtype : _GEN_158[_ld_xcpt_uop_T_4]; // @[util.scala:363:52] wire [1:0] xcpt_uop_lrs1_rtype = use_mem_xcpt ? mem_xcpt_uop_lrs1_rtype : _GEN_159[_ld_xcpt_uop_T_4]; // @[util.scala:363:52] wire [1:0] xcpt_uop_lrs2_rtype = use_mem_xcpt ? mem_xcpt_uop_lrs2_rtype : _GEN_160[_ld_xcpt_uop_T_4]; // @[util.scala:363:52] wire xcpt_uop_frs3_en = use_mem_xcpt ? mem_xcpt_uop_frs3_en : _GEN_161[_ld_xcpt_uop_T_4]; // @[util.scala:363:52] wire xcpt_uop_fp_val = use_mem_xcpt ? mem_xcpt_uop_fp_val : _GEN_162[_ld_xcpt_uop_T_4]; // @[util.scala:363:52] wire xcpt_uop_fp_single = use_mem_xcpt ? mem_xcpt_uop_fp_single : _GEN_163[_ld_xcpt_uop_T_4]; // @[util.scala:363:52] wire xcpt_uop_xcpt_pf_if = use_mem_xcpt ? mem_xcpt_uop_xcpt_pf_if : _GEN_164[_ld_xcpt_uop_T_4]; // @[util.scala:363:52] wire xcpt_uop_xcpt_ae_if = use_mem_xcpt ? mem_xcpt_uop_xcpt_ae_if : _GEN_165[_ld_xcpt_uop_T_4]; // @[util.scala:363:52] wire xcpt_uop_xcpt_ma_if = use_mem_xcpt ? mem_xcpt_uop_xcpt_ma_if : _GEN_166[_ld_xcpt_uop_T_4]; // @[util.scala:363:52] wire xcpt_uop_bp_debug_if = use_mem_xcpt ? mem_xcpt_uop_bp_debug_if : _GEN_167[_ld_xcpt_uop_T_4]; // @[util.scala:363:52] wire xcpt_uop_bp_xcpt_if = use_mem_xcpt ? mem_xcpt_uop_bp_xcpt_if : _GEN_168[_ld_xcpt_uop_T_4]; // @[util.scala:363:52] wire [1:0] xcpt_uop_debug_fsrc = use_mem_xcpt ? mem_xcpt_uop_debug_fsrc : _GEN_169[_ld_xcpt_uop_T_4]; // @[util.scala:363:52] wire [1:0] xcpt_uop_debug_tsrc = use_mem_xcpt ? mem_xcpt_uop_debug_tsrc : _GEN_170[_ld_xcpt_uop_T_4]; // @[util.scala:363:52] wire _r_xcpt_valid_T = ld_xcpt_valid \| mem_xcpt_valid; // @[lsu.scala:358:29, :1239:44, :1246:34] wire _r_xcpt_valid_T_1 = ~io_core_exception_0; // @[lsu.scala:201:7, :670:22, :1247:20] wire _r_xcpt_valid_T_2 = _r_xcpt_valid_T & _r_xcpt_valid_T_1; // @[lsu.scala:1246:{34,53}, :1247:20] wire [7:0] _r_xcpt_valid_T_3 = io_core_brupdate_b1_mispredict_mask_0 & xcpt_uop_br_mask; // @[util.scala:118:51] wire _r_xcpt_valid_T_4 = \|_r_xcpt_valid_T_3; // @[util.scala:118:{51,59}] wire _r_xcpt_valid_T_5 = ~_r_xcpt_valid_T_4; // @[util.scala:118:59] wire _r_xcpt_valid_T_6 = _r_xcpt_valid_T_2 & _r_xcpt_valid_T_5; // @[lsu.scala:1246:53, :1247:39, :1248:20] wire [7:0] _r_xcpt_uop_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:85:27] wire [7:0] _r_xcpt_uop_br_mask_T_1 = xcpt_uop_br_mask & _r_xcpt_uop_br_mask_T; // @[util.scala:85:{25,27}] wire [4:0] _r_xcpt_cause_T = use_mem_xcpt ? {1'h0, mem_xcpt_cause} : 5'h10; // @[lsu.scala:359:29, :1242:115, :1251:28] wire _io_core_lxcpt_valid_T = ~io_core_exception_0; // @[lsu.scala:201:7, :670:22, :1254:42] wire _io_core_lxcpt_valid_T_1 = r_xcpt_valid & _io_core_lxcpt_valid_T; // @[lsu.scala:1236:29, :1254:{39,42}] wire [7:0] _io_core_lxcpt_valid_T_2 = io_core_brupdate_b1_mispredict_mask_0 & r_xcpt_uop_br_mask; // @[util.scala:118:51] wire _io_core_lxcpt_valid_T_3 = \|_io_core_lxcpt_valid_T_2; // @[util.scala:118:{51,59}] wire _io_core_lxcpt_valid_T_4 = ~_io_core_lxcpt_valid_T_3; // @[util.scala:118:59] assign _io_core_lxcpt_valid_T_5 = _io_core_lxcpt_valid_T_1 & _io_core_lxcpt_valid_T_4; // @[lsu.scala:1254:{39,61,64}] assign io_core_lxcpt_valid_0 = _io_core_lxcpt_valid_T_5; // @[lsu.scala:201:7, :1254:61] wire _io_core_spec_ld_wakeup_0_valid_T_1 = ~mem_incoming_uop_0_fp_val; // @[lsu.scala:909:37, :1261:40] wire _io_core_spec_ld_wakeup_0_valid_T_2 = _io_core_spec_ld_wakeup_0_valid_T & _io_core_spec_ld_wakeup_0_valid_T_1; // @[lsu.scala:1259:69, :1260:69, :1261:40] wire _io_core_spec_ld_wakeup_0_valid_T_3 = \|mem_incoming_uop_0_pdst; // @[lsu.scala:909:37, :1262:65] assign _io_core_spec_ld_wakeup_0_valid_T_4 = _io_core_spec_ld_wakeup_0_valid_T_2 & _io_core_spec_ld_wakeup_0_valid_T_3; // @[lsu.scala:1260:69, :1261:69, :1262:65] assign io_core_spec_ld_wakeup_0_valid_0 = _io_core_spec_ld_wakeup_0_valid_T_4; // @[lsu.scala:201:7, :1261:69] wire dmem_resp_fired_0; // @[lsu.scala:1282:33] wire _GEN_356 = io_dmem_nack_0_valid_0 & ~io_dmem_nack_0_bits_is_hella_0; // @[lsu.scala:201:7, :1290:7] wire _GEN_357 = _GEN_356 & io_dmem_nack_0_bits_uop_uses_ldq_0 & ~reset; // @[lsu.scala:201:7, :1290:7, :1294:7, :1295:15] wire _GEN_358 = io_dmem_nack_0_bits_uop_uses_ldq_0 & io_dmem_nack_0_bits_uop_ldq_idx_0 == 3'h0; // @[lsu.scala:201:7, :1175:30, :1294:7, :1296:62] wire _GEN_359 = io_dmem_nack_0_bits_uop_uses_ldq_0 & io_dmem_nack_0_bits_uop_ldq_idx_0 == 3'h1; // @[lsu.scala:201:7, :1175:30, :1294:7, :1296:62] wire _GEN_360 = io_dmem_nack_0_bits_uop_uses_ldq_0 & io_dmem_nack_0_bits_uop_ldq_idx_0 == 3'h2; // @[lsu.scala:201:7, :1175:30, :1294:7, :1296:62] wire _GEN_361 = io_dmem_nack_0_bits_uop_uses_ldq_0 & io_dmem_nack_0_bits_uop_ldq_idx_0 == 3'h3; // @[lsu.scala:201:7, :1175:30, :1294:7, :1296:62] wire _GEN_362 = io_dmem_nack_0_bits_uop_uses_ldq_0 & io_dmem_nack_0_bits_uop_ldq_idx_0 == 3'h4; // @[lsu.scala:201:7, :1175:30, :1294:7, :1296:62] wire _GEN_363 = io_dmem_nack_0_bits_uop_uses_ldq_0 & io_dmem_nack_0_bits_uop_ldq_idx_0 == 3'h5; // @[lsu.scala:201:7, :1175:30, :1294:7, :1296:62] wire _GEN_364 = io_dmem_nack_0_bits_uop_uses_ldq_0 & io_dmem_nack_0_bits_uop_ldq_idx_0 == 3'h6; // @[lsu.scala:201:7, :1175:30, :1294:7, :1296:62] wire _GEN_365 = io_dmem_nack_0_bits_uop_uses_ldq_0 & (&io_dmem_nack_0_bits_uop_ldq_idx_0); // @[lsu.scala:201:7, :1175:30, :1294:7, :1296:62] assign nacking_loads_0 = io_dmem_nack_0_valid_0 & ~io_dmem_nack_0_bits_is_hella_0 & _GEN_358; // @[lsu.scala:201:7, :1055:34, :1175:30, :1287:5, :1290:7, :1294:7, :1296:62] assign nacking_loads_1 = io_dmem_nack_0_valid_0 & ~io_dmem_nack_0_bits_is_hella_0 & _GEN_359; // @[lsu.scala:201:7, :1055:34, :1175:30, :1287:5, :1290:7, :1294:7, :1296:62] assign nacking_loads_2 = io_dmem_nack_0_valid_0 & ~io_dmem_nack_0_bits_is_hella_0 & _GEN_360; // @[lsu.scala:201:7, :1055:34, :1175:30, :1287:5, :1290:7, :1294:7, :1296:62] assign nacking_loads_3 = io_dmem_nack_0_valid_0 & ~io_dmem_nack_0_bits_is_hella_0 & _GEN_361; // @[lsu.scala:201:7, :1055:34, :1175:30, :1287:5, :1290:7, :1294:7, :1296:62] assign nacking_loads_4 = io_dmem_nack_0_valid_0 & ~io_dmem_nack_0_bits_is_hella_0 & _GEN_362; // @[lsu.scala:201:7, :1055:34, :1175:30, :1287:5, :1290:7, :1294:7, :1296:62] assign nacking_loads_5 = io_dmem_nack_0_valid_0 & ~io_dmem_nack_0_bits_is_hella_0 & _GEN_363; // @[lsu.scala:201:7, :1055:34, :1175:30, :1287:5, :1290:7, :1294:7, :1296:62] assign nacking_loads_6 = io_dmem_nack_0_valid_0 & ~io_dmem_nack_0_bits_is_hella_0 & _GEN_364; // @[lsu.scala:201:7, :1055:34, :1175:30, :1287:5, :1290:7, :1294:7, :1296:62] assign nacking_loads_7 = io_dmem_nack_0_valid_0 & ~io_dmem_nack_0_bits_is_hella_0 & _GEN_365; // @[lsu.scala:201:7, :1055:34, :1175:30, :1287:5, :1290:7, :1294:7, :1296:62] wire _GEN_366 = io_dmem_resp_0_valid_0 & io_dmem_resp_0_bits_uop_uses_ldq_0; // @[lsu.scala:201:7, :1311:7] wire send_iresp = _GEN_158[io_dmem_resp_0_bits_uop_ldq_idx_0] == 2'h0; // @[lsu.scala:201:7, :263:49, :1314:58] wire send_fresp = _GEN_158[io_dmem_resp_0_bits_uop_ldq_idx_0] == 2'h1; // @[lsu.scala:201:7, :263:49, :1314:58, :1315:58] wire _ldq_bits_succeeded_T = io_core_exe_0_iresp_valid_0 \| io_core_exe_0_fresp_valid_0; // @[lsu.scala:201:7, :1327:72] assign dmem_resp_fired_0 = io_dmem_resp_0_valid_0 & (io_dmem_resp_0_bits_uop_uses_ldq_0 \| io_dmem_resp_0_bits_uop_uses_stq_0 & io_dmem_resp_0_bits_uop_is_amo_0); // @[lsu.scala:201:7, :1282:33, :1309:5, :1311:7, :1325:28, :1331:7, :1334:48, :1335:30] wire _T_690 = dmem_resp_fired_0 & wb_forward_valid_0; // @[lsu.scala:1065:36, :1282:33, :1346:30] wire _T_692 = ~dmem_resp_fired_0 & wb_forward_valid_0; // @[lsu.scala:1065:36, :1282:33, :1350:{18,38}] wire [2:0] _forward_uop_T_1 = _forward_uop_T; wire [1:0] size_1 = _GEN_142[_forward_uop_T_1]; // @[AMOALU.scala:11:18] wire [7:0] _live_T = io_core_brupdate_b1_mispredict_mask_0 & _GEN_118[_forward_uop_T_1]; // @[util.scala:118:51] wire _live_T_1 = \|_live_T; // @[util.scala:118:{51,59}] wire live = ~_live_T_1; // @[util.scala:118:59] wire [1:0] size; // @[AMOALU.scala:11:18] assign size = _GEN_52[wb_forward_stq_idx_0]; // @[AMOALU.scala:11:18, :12:8] wire _GEN_367 = _GEN_86[wb_forward_stq_idx_0]; // @[AMOALU.scala:12:8] wire [63:0] _GEN_368 = _GEN_87[wb_forward_stq_idx_0]; // @[AMOALU.scala:12:8] wire [3:0][63:0] _GEN_369 = {{_GEN_368}, {{2{_GEN_368[31:0]}}}, {{2{{2{_GEN_368[15:0]}}}}}, {{2{{2{{2{_GEN_368[7:0]}}}}}}}}; // @[AMOALU.scala:12:8, :29:{13,19,32,69}] wire _io_core_exe_0_iresp_valid_T = _GEN_158[_forward_uop_T_1] == 2'h0; // @[util.scala:118:51] wire _io_core_exe_0_iresp_valid_T_1 = _io_core_exe_0_iresp_valid_T & _GEN_367; // @[AMOALU.scala:12:8] wire _io_core_exe_0_iresp_valid_T_2 = _io_core_exe_0_iresp_valid_T_1 & live; // @[lsu.scala:1356:25, :1365:{72,86}] wire _GEN_370 = _T_690 \| ~_T_692; // @[lsu.scala:1309:5, :1346:30, :1347:5, :1350:38, :1351:5] assign io_core_exe_0_iresp_valid_0 = _GEN_370 ? io_dmem_resp_0_valid_0 & (io_dmem_resp_0_bits_uop_uses_ldq_0 ? send_iresp : io_dmem_resp_0_bits_uop_uses_stq_0 & io_dmem_resp_0_bits_uop_is_amo_0) : _io_core_exe_0_iresp_valid_T_2; // @[lsu.scala:201:7, :1276:32, :1309:5, :1311:7, :1314:58, :1319:40, :1331:7, :1334:48, :1347:5, :1351:5, :1365:86] wire _io_core_exe_0_fresp_valid_T = _GEN_158[_forward_uop_T_1] == 2'h1; // @[util.scala:118:51] wire _io_core_exe_0_fresp_valid_T_1 = _io_core_exe_0_fresp_valid_T & _GEN_367; // @[AMOALU.scala:12:8] wire _io_core_exe_0_fresp_valid_T_2 = _io_core_exe_0_fresp_valid_T_1 & live; // @[lsu.scala:1356:25, :1366:{72,86}] assign io_core_exe_0_fresp_valid_0 = _GEN_370 ? _GEN_366 & send_fresp : _io_core_exe_0_fresp_valid_T_2; // @[lsu.scala:201:7, :1278:32, :1309:5, :1311:7, :1315:58, :1321:40, :1347:5, :1351:5, :1366:86] assign io_core_exe_0_iresp_bits_uop_uopc_0 = _GEN_370 ? (io_dmem_resp_0_bits_uop_uses_ldq_0 ? _GEN_94[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_1[io_dmem_resp_0_bits_uop_stq_idx_0]) : _GEN_94[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_iresp_bits_uop_inst_0 = _GEN_370 ? (io_dmem_resp_0_bits_uop_uses_ldq_0 ? _GEN_95[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_2[io_dmem_resp_0_bits_uop_stq_idx_0]) : _GEN_95[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_iresp_bits_uop_debug_inst_0 = _GEN_370 ? (io_dmem_resp_0_bits_uop_uses_ldq_0 ? _GEN_96[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_3[io_dmem_resp_0_bits_uop_stq_idx_0]) : _GEN_96[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_iresp_bits_uop_is_rvc_0 = _GEN_370 ? (io_dmem_resp_0_bits_uop_uses_ldq_0 ? _GEN_97[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_4[io_dmem_resp_0_bits_uop_stq_idx_0]) : _GEN_97[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_iresp_bits_uop_debug_pc_0 = _GEN_370 ? (io_dmem_resp_0_bits_uop_uses_ldq_0 ? _GEN_98[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_5[io_dmem_resp_0_bits_uop_stq_idx_0]) : _GEN_98[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_iresp_bits_uop_iq_type_0 = _GEN_370 ? (io_dmem_resp_0_bits_uop_uses_ldq_0 ? _GEN_99[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_6[io_dmem_resp_0_bits_uop_stq_idx_0]) : _GEN_99[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_iresp_bits_uop_fu_code_0 = _GEN_370 ? (io_dmem_resp_0_bits_uop_uses_ldq_0 ? _GEN_100[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_7[io_dmem_resp_0_bits_uop_stq_idx_0]) : _GEN_100[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_iresp_bits_uop_ctrl_br_type_0 = _GEN_370 ? (io_dmem_resp_0_bits_uop_uses_ldq_0 ? _GEN_101[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_8[io_dmem_resp_0_bits_uop_stq_idx_0]) : _GEN_101[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_iresp_bits_uop_ctrl_op1_sel_0 = _GEN_370 ? (io_dmem_resp_0_bits_uop_uses_ldq_0 ? _GEN_102[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_9[io_dmem_resp_0_bits_uop_stq_idx_0]) : _GEN_102[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_iresp_bits_uop_ctrl_op2_sel_0 = _GEN_370 ? (io_dmem_resp_0_bits_uop_uses_ldq_0 ? _GEN_103[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_10[io_dmem_resp_0_bits_uop_stq_idx_0]) : _GEN_103[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_iresp_bits_uop_ctrl_imm_sel_0 = _GEN_370 ? (io_dmem_resp_0_bits_uop_uses_ldq_0 ? _GEN_104[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_11[io_dmem_resp_0_bits_uop_stq_idx_0]) : _GEN_104[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_iresp_bits_uop_ctrl_op_fcn_0 = _GEN_370 ? (io_dmem_resp_0_bits_uop_uses_ldq_0 ? _GEN_105[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_12[io_dmem_resp_0_bits_uop_stq_idx_0]) : _GEN_105[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_iresp_bits_uop_ctrl_fcn_dw_0 = _GEN_370 ? (io_dmem_resp_0_bits_uop_uses_ldq_0 ? _GEN_106[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_13[io_dmem_resp_0_bits_uop_stq_idx_0]) : _GEN_106[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_iresp_bits_uop_ctrl_csr_cmd_0 = _GEN_370 ? (io_dmem_resp_0_bits_uop_uses_ldq_0 ? _GEN_107[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_14[io_dmem_resp_0_bits_uop_stq_idx_0]) : _GEN_107[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_iresp_bits_uop_ctrl_is_load_0 = _GEN_370 ? (io_dmem_resp_0_bits_uop_uses_ldq_0 ? _GEN_108[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_15[io_dmem_resp_0_bits_uop_stq_idx_0]) : _GEN_108[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_iresp_bits_uop_ctrl_is_sta_0 = _GEN_370 ? (io_dmem_resp_0_bits_uop_uses_ldq_0 ? _GEN_109[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_16[io_dmem_resp_0_bits_uop_stq_idx_0]) : _GEN_109[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_iresp_bits_uop_ctrl_is_std_0 = _GEN_370 ? (io_dmem_resp_0_bits_uop_uses_ldq_0 ? _GEN_110[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_17[io_dmem_resp_0_bits_uop_stq_idx_0]) : _GEN_110[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_iresp_bits_uop_iw_state_0 = _GEN_370 ? (io_dmem_resp_0_bits_uop_uses_ldq_0 ? _GEN_111[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_18[io_dmem_resp_0_bits_uop_stq_idx_0]) : _GEN_111[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_iresp_bits_uop_iw_p1_poisoned_0 = _GEN_370 ? (io_dmem_resp_0_bits_uop_uses_ldq_0 ? _GEN_112[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_19[io_dmem_resp_0_bits_uop_stq_idx_0]) : _GEN_112[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_iresp_bits_uop_iw_p2_poisoned_0 = _GEN_370 ? (io_dmem_resp_0_bits_uop_uses_ldq_0 ? _GEN_113[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_20[io_dmem_resp_0_bits_uop_stq_idx_0]) : _GEN_113[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_iresp_bits_uop_is_br_0 = _GEN_370 ? (io_dmem_resp_0_bits_uop_uses_ldq_0 ? _GEN_114[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_21[io_dmem_resp_0_bits_uop_stq_idx_0]) : _GEN_114[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_iresp_bits_uop_is_jalr_0 = _GEN_370 ? (io_dmem_resp_0_bits_uop_uses_ldq_0 ? _GEN_115[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_22[io_dmem_resp_0_bits_uop_stq_idx_0]) : _GEN_115[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_iresp_bits_uop_is_jal_0 = _GEN_370 ? (io_dmem_resp_0_bits_uop_uses_ldq_0 ? _GEN_116[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_23[io_dmem_resp_0_bits_uop_stq_idx_0]) : _GEN_116[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_iresp_bits_uop_is_sfb_0 = _GEN_370 ? (io_dmem_resp_0_bits_uop_uses_ldq_0 ? _GEN_117[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_24[io_dmem_resp_0_bits_uop_stq_idx_0]) : _GEN_117[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_iresp_bits_uop_br_mask_0 = _GEN_370 ? (io_dmem_resp_0_bits_uop_uses_ldq_0 ? _GEN_118[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_25[io_dmem_resp_0_bits_uop_stq_idx_0]) : _GEN_118[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_iresp_bits_uop_br_tag_0 = _GEN_370 ? (io_dmem_resp_0_bits_uop_uses_ldq_0 ? _GEN_119[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_26[io_dmem_resp_0_bits_uop_stq_idx_0]) : _GEN_119[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_iresp_bits_uop_ftq_idx_0 = _GEN_370 ? (io_dmem_resp_0_bits_uop_uses_ldq_0 ? _GEN_120[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_27[io_dmem_resp_0_bits_uop_stq_idx_0]) : _GEN_120[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_iresp_bits_uop_edge_inst_0 = _GEN_370 ? (io_dmem_resp_0_bits_uop_uses_ldq_0 ? _GEN_121[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_28[io_dmem_resp_0_bits_uop_stq_idx_0]) : _GEN_121[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_iresp_bits_uop_pc_lob_0 = _GEN_370 ? (io_dmem_resp_0_bits_uop_uses_ldq_0 ? _GEN_122[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_29[io_dmem_resp_0_bits_uop_stq_idx_0]) : _GEN_122[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_iresp_bits_uop_taken_0 = _GEN_370 ? (io_dmem_resp_0_bits_uop_uses_ldq_0 ? _GEN_123[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_30[io_dmem_resp_0_bits_uop_stq_idx_0]) : _GEN_123[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_iresp_bits_uop_imm_packed_0 = _GEN_370 ? (io_dmem_resp_0_bits_uop_uses_ldq_0 ? _GEN_124[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_31[io_dmem_resp_0_bits_uop_stq_idx_0]) : _GEN_124[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_iresp_bits_uop_csr_addr_0 = _GEN_370 ? (io_dmem_resp_0_bits_uop_uses_ldq_0 ? _GEN_125[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_32[io_dmem_resp_0_bits_uop_stq_idx_0]) : _GEN_125[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_iresp_bits_uop_rob_idx_0 = _GEN_370 ? (io_dmem_resp_0_bits_uop_uses_ldq_0 ? _GEN_126[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_33[io_dmem_resp_0_bits_uop_stq_idx_0]) : _GEN_126[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_iresp_bits_uop_ldq_idx_0 = _GEN_370 ? (io_dmem_resp_0_bits_uop_uses_ldq_0 ? _GEN_127[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_34[io_dmem_resp_0_bits_uop_stq_idx_0]) : _GEN_127[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_iresp_bits_uop_stq_idx_0 = _GEN_370 ? (io_dmem_resp_0_bits_uop_uses_ldq_0 ? _GEN_128[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_35[io_dmem_resp_0_bits_uop_stq_idx_0]) : _GEN_128[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_iresp_bits_uop_rxq_idx_0 = _GEN_370 ? (io_dmem_resp_0_bits_uop_uses_ldq_0 ? _GEN_129[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_36[io_dmem_resp_0_bits_uop_stq_idx_0]) : _GEN_129[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_iresp_bits_uop_pdst_0 = _GEN_370 ? (io_dmem_resp_0_bits_uop_uses_ldq_0 ? _GEN_130[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_37[io_dmem_resp_0_bits_uop_stq_idx_0]) : _GEN_130[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_iresp_bits_uop_prs1_0 = _GEN_370 ? (io_dmem_resp_0_bits_uop_uses_ldq_0 ? _GEN_131[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_38[io_dmem_resp_0_bits_uop_stq_idx_0]) : _GEN_131[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_iresp_bits_uop_prs2_0 = _GEN_370 ? (io_dmem_resp_0_bits_uop_uses_ldq_0 ? _GEN_132[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_39[io_dmem_resp_0_bits_uop_stq_idx_0]) : _GEN_132[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_iresp_bits_uop_prs3_0 = _GEN_370 ? (io_dmem_resp_0_bits_uop_uses_ldq_0 ? _GEN_133[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_40[io_dmem_resp_0_bits_uop_stq_idx_0]) : _GEN_133[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_iresp_bits_uop_ppred_0 = ~_GEN_370 \| io_dmem_resp_0_bits_uop_uses_ldq_0 ? 4'h0 : _GEN_41[io_dmem_resp_0_bits_uop_stq_idx_0]; // @[lsu.scala:201:7, :222:42, :1309:5, :1333:62, :1347:5, :1351:5] assign io_core_exe_0_iresp_bits_uop_prs1_busy_0 = _GEN_370 ? (io_dmem_resp_0_bits_uop_uses_ldq_0 ? _GEN_134[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_42[io_dmem_resp_0_bits_uop_stq_idx_0]) : _GEN_134[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_iresp_bits_uop_prs2_busy_0 = _GEN_370 ? (io_dmem_resp_0_bits_uop_uses_ldq_0 ? _GEN_135[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_43[io_dmem_resp_0_bits_uop_stq_idx_0]) : _GEN_135[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_iresp_bits_uop_prs3_busy_0 = _GEN_370 ? (io_dmem_resp_0_bits_uop_uses_ldq_0 ? _GEN_136[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_44[io_dmem_resp_0_bits_uop_stq_idx_0]) : _GEN_136[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_iresp_bits_uop_ppred_busy_0 = _GEN_370 & ~io_dmem_resp_0_bits_uop_uses_ldq_0 & _GEN_45[io_dmem_resp_0_bits_uop_stq_idx_0]; // @[lsu.scala:201:7, :222:42, :767:39, :1309:5, :1311:7, :1317:40, :1331:7, :1333:62, :1347:5, :1351:5] assign io_core_exe_0_iresp_bits_uop_stale_pdst_0 = _GEN_370 ? (io_dmem_resp_0_bits_uop_uses_ldq_0 ? _GEN_137[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_46[io_dmem_resp_0_bits_uop_stq_idx_0]) : _GEN_137[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_iresp_bits_uop_exception_0 = _GEN_370 ? (io_dmem_resp_0_bits_uop_uses_ldq_0 ? _GEN_138[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_47[io_dmem_resp_0_bits_uop_stq_idx_0]) : _GEN_138[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_iresp_bits_uop_exc_cause_0 = _GEN_370 ? (io_dmem_resp_0_bits_uop_uses_ldq_0 ? _GEN_139[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_49[io_dmem_resp_0_bits_uop_stq_idx_0]) : _GEN_139[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_iresp_bits_uop_bypassable_0 = _GEN_370 ? (io_dmem_resp_0_bits_uop_uses_ldq_0 ? _GEN_140[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_50[io_dmem_resp_0_bits_uop_stq_idx_0]) : _GEN_140[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_iresp_bits_uop_mem_cmd_0 = _GEN_370 ? (io_dmem_resp_0_bits_uop_uses_ldq_0 ? _GEN_141[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_51[io_dmem_resp_0_bits_uop_stq_idx_0]) : _GEN_141[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_iresp_bits_uop_mem_size_0 = _GEN_370 ? (io_dmem_resp_0_bits_uop_uses_ldq_0 ? _GEN_142[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_52[io_dmem_resp_0_bits_uop_stq_idx_0]) : size_1; // @[AMOALU.scala:11:18] assign io_core_exe_0_iresp_bits_uop_mem_signed_0 = _GEN_370 ? (io_dmem_resp_0_bits_uop_uses_ldq_0 ? _GEN_143[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_53[io_dmem_resp_0_bits_uop_stq_idx_0]) : _GEN_143[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_iresp_bits_uop_is_fence_0 = _GEN_370 ? (io_dmem_resp_0_bits_uop_uses_ldq_0 ? _GEN_144[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_54[io_dmem_resp_0_bits_uop_stq_idx_0]) : _GEN_144[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_iresp_bits_uop_is_fencei_0 = _GEN_370 ? (io_dmem_resp_0_bits_uop_uses_ldq_0 ? _GEN_145[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_56[io_dmem_resp_0_bits_uop_stq_idx_0]) : _GEN_145[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_iresp_bits_uop_is_amo_0 = _GEN_370 ? (io_dmem_resp_0_bits_uop_uses_ldq_0 ? _GEN_146[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_57[io_dmem_resp_0_bits_uop_stq_idx_0]) : _GEN_146[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_iresp_bits_uop_uses_ldq_0 = _GEN_370 ? (io_dmem_resp_0_bits_uop_uses_ldq_0 ? _GEN_147[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_59[io_dmem_resp_0_bits_uop_stq_idx_0]) : _GEN_147[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_iresp_bits_uop_uses_stq_0 = _GEN_370 ? (io_dmem_resp_0_bits_uop_uses_ldq_0 ? _GEN_148[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_60[io_dmem_resp_0_bits_uop_stq_idx_0]) : _GEN_148[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_iresp_bits_uop_is_sys_pc2epc_0 = _GEN_370 ? (io_dmem_resp_0_bits_uop_uses_ldq_0 ? _GEN_149[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_61[io_dmem_resp_0_bits_uop_stq_idx_0]) : _GEN_149[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_iresp_bits_uop_is_unique_0 = _GEN_370 ? (io_dmem_resp_0_bits_uop_uses_ldq_0 ? _GEN_150[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_62[io_dmem_resp_0_bits_uop_stq_idx_0]) : _GEN_150[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_iresp_bits_uop_flush_on_commit_0 = _GEN_370 ? (io_dmem_resp_0_bits_uop_uses_ldq_0 ? _GEN_151[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_63[io_dmem_resp_0_bits_uop_stq_idx_0]) : _GEN_151[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_iresp_bits_uop_ldst_is_rs1_0 = _GEN_370 ? (io_dmem_resp_0_bits_uop_uses_ldq_0 ? _GEN_152[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_64[io_dmem_resp_0_bits_uop_stq_idx_0]) : _GEN_152[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_iresp_bits_uop_ldst_0 = _GEN_370 ? (io_dmem_resp_0_bits_uop_uses_ldq_0 ? _GEN_153[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_65[io_dmem_resp_0_bits_uop_stq_idx_0]) : _GEN_153[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_iresp_bits_uop_lrs1_0 = _GEN_370 ? (io_dmem_resp_0_bits_uop_uses_ldq_0 ? _GEN_154[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_66[io_dmem_resp_0_bits_uop_stq_idx_0]) : _GEN_154[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_iresp_bits_uop_lrs2_0 = _GEN_370 ? (io_dmem_resp_0_bits_uop_uses_ldq_0 ? _GEN_155[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_67[io_dmem_resp_0_bits_uop_stq_idx_0]) : _GEN_155[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_iresp_bits_uop_lrs3_0 = _GEN_370 ? (io_dmem_resp_0_bits_uop_uses_ldq_0 ? _GEN_156[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_68[io_dmem_resp_0_bits_uop_stq_idx_0]) : _GEN_156[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_iresp_bits_uop_ldst_val_0 = _GEN_370 ? (io_dmem_resp_0_bits_uop_uses_ldq_0 ? _GEN_157[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_69[io_dmem_resp_0_bits_uop_stq_idx_0]) : _GEN_157[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_iresp_bits_uop_dst_rtype_0 = _GEN_370 ? (io_dmem_resp_0_bits_uop_uses_ldq_0 ? _GEN_158[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_70[io_dmem_resp_0_bits_uop_stq_idx_0]) : _GEN_158[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_iresp_bits_uop_lrs1_rtype_0 = _GEN_370 ? (io_dmem_resp_0_bits_uop_uses_ldq_0 ? _GEN_159[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_71[io_dmem_resp_0_bits_uop_stq_idx_0]) : _GEN_159[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_iresp_bits_uop_lrs2_rtype_0 = _GEN_370 ? (io_dmem_resp_0_bits_uop_uses_ldq_0 ? _GEN_160[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_72[io_dmem_resp_0_bits_uop_stq_idx_0]) : _GEN_160[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_iresp_bits_uop_frs3_en_0 = _GEN_370 ? (io_dmem_resp_0_bits_uop_uses_ldq_0 ? _GEN_161[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_73[io_dmem_resp_0_bits_uop_stq_idx_0]) : _GEN_161[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_iresp_bits_uop_fp_val_0 = _GEN_370 ? (io_dmem_resp_0_bits_uop_uses_ldq_0 ? _GEN_162[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_74[io_dmem_resp_0_bits_uop_stq_idx_0]) : _GEN_162[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_iresp_bits_uop_fp_single_0 = _GEN_370 ? (io_dmem_resp_0_bits_uop_uses_ldq_0 ? _GEN_163[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_75[io_dmem_resp_0_bits_uop_stq_idx_0]) : _GEN_163[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_iresp_bits_uop_xcpt_pf_if_0 = _GEN_370 ? (io_dmem_resp_0_bits_uop_uses_ldq_0 ? _GEN_164[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_76[io_dmem_resp_0_bits_uop_stq_idx_0]) : _GEN_164[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_iresp_bits_uop_xcpt_ae_if_0 = _GEN_370 ? (io_dmem_resp_0_bits_uop_uses_ldq_0 ? _GEN_165[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_77[io_dmem_resp_0_bits_uop_stq_idx_0]) : _GEN_165[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_iresp_bits_uop_xcpt_ma_if_0 = _GEN_370 ? (io_dmem_resp_0_bits_uop_uses_ldq_0 ? _GEN_166[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_78[io_dmem_resp_0_bits_uop_stq_idx_0]) : _GEN_166[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_iresp_bits_uop_bp_debug_if_0 = _GEN_370 ? (io_dmem_resp_0_bits_uop_uses_ldq_0 ? _GEN_167[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_79[io_dmem_resp_0_bits_uop_stq_idx_0]) : _GEN_167[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_iresp_bits_uop_bp_xcpt_if_0 = _GEN_370 ? (io_dmem_resp_0_bits_uop_uses_ldq_0 ? _GEN_168[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_80[io_dmem_resp_0_bits_uop_stq_idx_0]) : _GEN_168[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_iresp_bits_uop_debug_fsrc_0 = _GEN_370 ? (io_dmem_resp_0_bits_uop_uses_ldq_0 ? _GEN_169[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_81[io_dmem_resp_0_bits_uop_stq_idx_0]) : _GEN_169[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_iresp_bits_uop_debug_tsrc_0 = _GEN_370 ? (io_dmem_resp_0_bits_uop_uses_ldq_0 ? _GEN_170[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_82[io_dmem_resp_0_bits_uop_stq_idx_0]) : _GEN_170[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_fresp_bits_uop_uopc_0 = _GEN_370 ? _GEN_94[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_94[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_fresp_bits_uop_inst_0 = _GEN_370 ? _GEN_95[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_95[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_fresp_bits_uop_debug_inst_0 = _GEN_370 ? _GEN_96[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_96[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_fresp_bits_uop_is_rvc_0 = _GEN_370 ? _GEN_97[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_97[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_fresp_bits_uop_debug_pc_0 = _GEN_370 ? _GEN_98[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_98[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_fresp_bits_uop_iq_type_0 = _GEN_370 ? _GEN_99[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_99[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_fresp_bits_uop_fu_code_0 = _GEN_370 ? _GEN_100[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_100[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_fresp_bits_uop_ctrl_br_type_0 = _GEN_370 ? _GEN_101[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_101[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_fresp_bits_uop_ctrl_op1_sel_0 = _GEN_370 ? _GEN_102[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_102[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_fresp_bits_uop_ctrl_op2_sel_0 = _GEN_370 ? _GEN_103[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_103[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_fresp_bits_uop_ctrl_imm_sel_0 = _GEN_370 ? _GEN_104[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_104[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_fresp_bits_uop_ctrl_op_fcn_0 = _GEN_370 ? _GEN_105[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_105[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_fresp_bits_uop_ctrl_fcn_dw_0 = _GEN_370 ? _GEN_106[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_106[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_fresp_bits_uop_ctrl_csr_cmd_0 = _GEN_370 ? _GEN_107[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_107[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_fresp_bits_uop_ctrl_is_load_0 = _GEN_370 ? _GEN_108[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_108[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_fresp_bits_uop_ctrl_is_sta_0 = _GEN_370 ? _GEN_109[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_109[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_fresp_bits_uop_ctrl_is_std_0 = _GEN_370 ? _GEN_110[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_110[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_fresp_bits_uop_iw_state_0 = _GEN_370 ? _GEN_111[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_111[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_fresp_bits_uop_iw_p1_poisoned_0 = _GEN_370 ? _GEN_112[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_112[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_fresp_bits_uop_iw_p2_poisoned_0 = _GEN_370 ? _GEN_113[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_113[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_fresp_bits_uop_is_br_0 = _GEN_370 ? _GEN_114[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_114[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_fresp_bits_uop_is_jalr_0 = _GEN_370 ? _GEN_115[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_115[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_fresp_bits_uop_is_jal_0 = _GEN_370 ? _GEN_116[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_116[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_fresp_bits_uop_is_sfb_0 = _GEN_370 ? _GEN_117[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_117[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_fresp_bits_uop_br_mask_0 = _GEN_370 ? _GEN_118[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_118[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_fresp_bits_uop_br_tag_0 = _GEN_370 ? _GEN_119[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_119[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_fresp_bits_uop_ftq_idx_0 = _GEN_370 ? _GEN_120[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_120[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_fresp_bits_uop_edge_inst_0 = _GEN_370 ? _GEN_121[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_121[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_fresp_bits_uop_pc_lob_0 = _GEN_370 ? _GEN_122[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_122[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_fresp_bits_uop_taken_0 = _GEN_370 ? _GEN_123[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_123[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_fresp_bits_uop_imm_packed_0 = _GEN_370 ? _GEN_124[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_124[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_fresp_bits_uop_csr_addr_0 = _GEN_370 ? _GEN_125[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_125[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_fresp_bits_uop_rob_idx_0 = _GEN_370 ? _GEN_126[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_126[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_fresp_bits_uop_ldq_idx_0 = _GEN_370 ? _GEN_127[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_127[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_fresp_bits_uop_stq_idx_0 = _GEN_370 ? _GEN_128[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_128[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_fresp_bits_uop_rxq_idx_0 = _GEN_370 ? _GEN_129[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_129[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_fresp_bits_uop_pdst_0 = _GEN_370 ? _GEN_130[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_130[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_fresp_bits_uop_prs1_0 = _GEN_370 ? _GEN_131[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_131[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_fresp_bits_uop_prs2_0 = _GEN_370 ? _GEN_132[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_132[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_fresp_bits_uop_prs3_0 = _GEN_370 ? _GEN_133[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_133[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_fresp_bits_uop_prs1_busy_0 = _GEN_370 ? _GEN_134[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_134[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_fresp_bits_uop_prs2_busy_0 = _GEN_370 ? _GEN_135[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_135[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_fresp_bits_uop_prs3_busy_0 = _GEN_370 ? _GEN_136[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_136[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_fresp_bits_uop_stale_pdst_0 = _GEN_370 ? _GEN_137[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_137[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_fresp_bits_uop_exception_0 = _GEN_370 ? _GEN_138[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_138[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_fresp_bits_uop_exc_cause_0 = _GEN_370 ? _GEN_139[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_139[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_fresp_bits_uop_bypassable_0 = _GEN_370 ? _GEN_140[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_140[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_fresp_bits_uop_mem_cmd_0 = _GEN_370 ? _GEN_141[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_141[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_fresp_bits_uop_mem_size_0 = _GEN_370 ? _GEN_142[io_dmem_resp_0_bits_uop_ldq_idx_0] : size_1; // @[AMOALU.scala:11:18] assign io_core_exe_0_fresp_bits_uop_mem_signed_0 = _GEN_370 ? _GEN_143[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_143[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_fresp_bits_uop_is_fence_0 = _GEN_370 ? _GEN_144[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_144[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_fresp_bits_uop_is_fencei_0 = _GEN_370 ? _GEN_145[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_145[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_fresp_bits_uop_is_amo_0 = _GEN_370 ? _GEN_146[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_146[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_fresp_bits_uop_uses_ldq_0 = _GEN_370 ? _GEN_147[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_147[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_fresp_bits_uop_uses_stq_0 = _GEN_370 ? _GEN_148[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_148[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_fresp_bits_uop_is_sys_pc2epc_0 = _GEN_370 ? _GEN_149[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_149[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_fresp_bits_uop_is_unique_0 = _GEN_370 ? _GEN_150[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_150[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_fresp_bits_uop_flush_on_commit_0 = _GEN_370 ? _GEN_151[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_151[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_fresp_bits_uop_ldst_is_rs1_0 = _GEN_370 ? _GEN_152[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_152[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_fresp_bits_uop_ldst_0 = _GEN_370 ? _GEN_153[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_153[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_fresp_bits_uop_lrs1_0 = _GEN_370 ? _GEN_154[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_154[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_fresp_bits_uop_lrs2_0 = _GEN_370 ? _GEN_155[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_155[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_fresp_bits_uop_lrs3_0 = _GEN_370 ? _GEN_156[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_156[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_fresp_bits_uop_ldst_val_0 = _GEN_370 ? _GEN_157[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_157[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_fresp_bits_uop_dst_rtype_0 = _GEN_370 ? _GEN_158[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_158[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_fresp_bits_uop_lrs1_rtype_0 = _GEN_370 ? _GEN_159[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_159[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_fresp_bits_uop_lrs2_rtype_0 = _GEN_370 ? _GEN_160[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_160[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_fresp_bits_uop_frs3_en_0 = _GEN_370 ? _GEN_161[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_161[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_fresp_bits_uop_fp_val_0 = _GEN_370 ? _GEN_162[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_162[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_fresp_bits_uop_fp_single_0 = _GEN_370 ? _GEN_163[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_163[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_fresp_bits_uop_xcpt_pf_if_0 = _GEN_370 ? _GEN_164[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_164[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_fresp_bits_uop_xcpt_ae_if_0 = _GEN_370 ? _GEN_165[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_165[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_fresp_bits_uop_xcpt_ma_if_0 = _GEN_370 ? _GEN_166[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_166[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_fresp_bits_uop_bp_debug_if_0 = _GEN_370 ? _GEN_167[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_167[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_fresp_bits_uop_bp_xcpt_if_0 = _GEN_370 ? _GEN_168[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_168[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_fresp_bits_uop_debug_fsrc_0 = _GEN_370 ? _GEN_169[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_169[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_fresp_bits_uop_debug_tsrc_0 = _GEN_370 ? _GEN_170[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_170[_forward_uop_T_1]; // @[util.scala:118:51] wire _io_core_exe_0_iresp_bits_data_shifted_T = wb_forward_ld_addr_0[2]; // @[AMOALU.scala:42:29] wire _io_core_exe_0_fresp_bits_data_shifted_T = wb_forward_ld_addr_0[2]; // @[AMOALU.scala:42:29] wire _ldq_bits_debug_wb_data_shifted_T = wb_forward_ld_addr_0[2]; // @[AMOALU.scala:42:29] wire [31:0] _io_core_exe_0_iresp_bits_data_shifted_T_1 = _GEN_369[size][63:32]; // @[AMOALU.scala:11:18, :29:{13,19}, :42:37] wire [31:0] _io_core_exe_0_iresp_bits_data_T_5 = _GEN_369[size][63:32]; // @[AMOALU.scala:11:18, :29:{13,19}, :42:37, :45:94] wire [31:0] _io_core_exe_0_fresp_bits_data_shifted_T_1 = _GEN_369[size][63:32]; // @[AMOALU.scala:11:18, :29:{13,19}, :42:37] wire [31:0] _io_core_exe_0_fresp_bits_data_T_5 = _GEN_369[size][63:32]; // @[AMOALU.scala:11:18, :29:{13,19}, :42:37, :45:94] wire [31:0] _ldq_bits_debug_wb_data_shifted_T_1 = _GEN_369[size][63:32]; // @[AMOALU.scala:11:18, :29:{13,19}, :42:37] wire [31:0] _ldq_bits_debug_wb_data_T_5 = _GEN_369[size][63:32]; // @[AMOALU.scala:11:18, :29:{13,19}, :42:37, :45:94] wire [31:0] _io_core_exe_0_iresp_bits_data_shifted_T_2 = _GEN_369[size][31:0]; // @[AMOALU.scala:11:18, :29:{13,19}, :42:55] wire [31:0] _io_core_exe_0_fresp_bits_data_shifted_T_2 = _GEN_369[size][31:0]; // @[AMOALU.scala:11:18, :29:{13,19}, :42:55] wire [31:0] _ldq_bits_debug_wb_data_shifted_T_2 = _GEN_369[size][31:0]; // @[AMOALU.scala:11:18, :29:{13,19}, :42:55] wire [31:0] io_core_exe_0_iresp_bits_data_shifted = _io_core_exe_0_iresp_bits_data_shifted_T ? _io_core_exe_0_iresp_bits_data_shifted_T_1 : _io_core_exe_0_iresp_bits_data_shifted_T_2; // @[AMOALU.scala:42:{24,29,37,55}] wire [31:0] io_core_exe_0_iresp_bits_data_zeroed = io_core_exe_0_iresp_bits_data_shifted; // @[AMOALU.scala:42:24, :44:23] wire _GEN_371 = size_1 == 2'h2; // @[AMOALU.scala:11:18, :45:26] wire _io_core_exe_0_iresp_bits_data_T; // @[AMOALU.scala:45:26] assign _io_core_exe_0_iresp_bits_data_T = _GEN_371; // @[AMOALU.scala:45:26] wire _io_core_exe_0_fresp_bits_data_T; // @[AMOALU.scala:45:26] assign _io_core_exe_0_fresp_bits_data_T = _GEN_371; // @[AMOALU.scala:45:26] wire _ldq_bits_debug_wb_data_T; // @[AMOALU.scala:45:26] assign _ldq_bits_debug_wb_data_T = _GEN_371; // @[AMOALU.scala:45:26] wire _io_core_exe_0_iresp_bits_data_T_1 = _io_core_exe_0_iresp_bits_data_T; // @[AMOALU.scala:45:{26,34}] wire _io_core_exe_0_iresp_bits_data_T_2 = io_core_exe_0_iresp_bits_data_zeroed[31]; // @[AMOALU.scala:44:23, :45:81] wire _io_core_exe_0_iresp_bits_data_T_3 = _GEN_143[_forward_uop_T_1] & _io_core_exe_0_iresp_bits_data_T_2; // @[AMOALU.scala:45:{72,81}] wire [31:0] _io_core_exe_0_iresp_bits_data_T_4 = {32{_io_core_exe_0_iresp_bits_data_T_3}}; // @[AMOALU.scala:45:{49,72}] wire [31:0] _io_core_exe_0_iresp_bits_data_T_6 = _io_core_exe_0_iresp_bits_data_T_1 ? _io_core_exe_0_iresp_bits_data_T_4 : _io_core_exe_0_iresp_bits_data_T_5; // @[AMOALU.scala:45:{20,34,49,94}] wire [63:0] _io_core_exe_0_iresp_bits_data_T_7 = {_io_core_exe_0_iresp_bits_data_T_6, io_core_exe_0_iresp_bits_data_zeroed}; // @[AMOALU.scala:44:23, :45:{16,20}] wire _io_core_exe_0_iresp_bits_data_shifted_T_3 = wb_forward_ld_addr_0[1]; // @[AMOALU.scala:42:29] wire _io_core_exe_0_fresp_bits_data_shifted_T_3 = wb_forward_ld_addr_0[1]; // @[AMOALU.scala:42:29] wire _ldq_bits_debug_wb_data_shifted_T_3 = wb_forward_ld_addr_0[1]; // @[AMOALU.scala:42:29] wire [15:0] _io_core_exe_0_iresp_bits_data_shifted_T_4 = _io_core_exe_0_iresp_bits_data_T_7[31:16]; // @[AMOALU.scala:42:37, :45:16] wire [15:0] _io_core_exe_0_iresp_bits_data_shifted_T_5 = _io_core_exe_0_iresp_bits_data_T_7[15:0]; // @[AMOALU.scala:42:55, :45:16] wire [15:0] io_core_exe_0_iresp_bits_data_shifted_1 = _io_core_exe_0_iresp_bits_data_shifted_T_3 ? _io_core_exe_0_iresp_bits_data_shifted_T_4 : _io_core_exe_0_iresp_bits_data_shifted_T_5; // @[AMOALU.scala:42:{24,29,37,55}] wire [15:0] io_core_exe_0_iresp_bits_data_zeroed_1 = io_core_exe_0_iresp_bits_data_shifted_1; // @[AMOALU.scala:42:24, :44:23] wire _GEN_372 = size_1 == 2'h1; // @[AMOALU.scala:11:18, :45:26] wire _io_core_exe_0_iresp_bits_data_T_8; // @[AMOALU.scala:45:26] assign _io_core_exe_0_iresp_bits_data_T_8 = _GEN_372; // @[AMOALU.scala:45:26] wire _io_core_exe_0_fresp_bits_data_T_8; // @[AMOALU.scala:45:26] assign _io_core_exe_0_fresp_bits_data_T_8 = _GEN_372; // @[AMOALU.scala:45:26] wire _ldq_bits_debug_wb_data_T_8; // @[AMOALU.scala:45:26] assign _ldq_bits_debug_wb_data_T_8 = _GEN_372; // @[AMOALU.scala:45:26] wire _io_core_exe_0_iresp_bits_data_T_9 = _io_core_exe_0_iresp_bits_data_T_8; // @[AMOALU.scala:45:{26,34}] wire _io_core_exe_0_iresp_bits_data_T_10 = io_core_exe_0_iresp_bits_data_zeroed_1[15]; // @[AMOALU.scala:44:23, :45:81] wire _io_core_exe_0_iresp_bits_data_T_11 = _GEN_143[_forward_uop_T_1] & _io_core_exe_0_iresp_bits_data_T_10; // @[AMOALU.scala:45:{72,81}] wire [47:0] _io_core_exe_0_iresp_bits_data_T_12 = {48{_io_core_exe_0_iresp_bits_data_T_11}}; // @[AMOALU.scala:45:{49,72}] wire [47:0] _io_core_exe_0_iresp_bits_data_T_13 = _io_core_exe_0_iresp_bits_data_T_7[63:16]; // @[AMOALU.scala:45:{16,94}] wire [47:0] _io_core_exe_0_iresp_bits_data_T_14 = _io_core_exe_0_iresp_bits_data_T_9 ? _io_core_exe_0_iresp_bits_data_T_12 : _io_core_exe_0_iresp_bits_data_T_13; // @[AMOALU.scala:45:{20,34,49,94}] wire [63:0] _io_core_exe_0_iresp_bits_data_T_15 = {_io_core_exe_0_iresp_bits_data_T_14, io_core_exe_0_iresp_bits_data_zeroed_1}; // @[AMOALU.scala:44:23, :45:{16,20}] wire _io_core_exe_0_iresp_bits_data_shifted_T_6 = wb_forward_ld_addr_0[0]; // @[AMOALU.scala:42:29] wire _io_core_exe_0_fresp_bits_data_shifted_T_6 = wb_forward_ld_addr_0[0]; // @[AMOALU.scala:42:29] wire _ldq_bits_debug_wb_data_shifted_T_6 = wb_forward_ld_addr_0[0]; // @[AMOALU.scala:42:29] wire [7:0] _io_core_exe_0_iresp_bits_data_shifted_T_7 = _io_core_exe_0_iresp_bits_data_T_15[15:8]; // @[AMOALU.scala:42:37, :45:16] wire [7:0] _io_core_exe_0_iresp_bits_data_shifted_T_8 = _io_core_exe_0_iresp_bits_data_T_15[7:0]; // @[AMOALU.scala:42:55, :45:16] wire [7:0] io_core_exe_0_iresp_bits_data_shifted_2 = _io_core_exe_0_iresp_bits_data_shifted_T_6 ? _io_core_exe_0_iresp_bits_data_shifted_T_7 : _io_core_exe_0_iresp_bits_data_shifted_T_8; // @[AMOALU.scala:42:{24,29,37,55}] wire [7:0] io_core_exe_0_iresp_bits_data_zeroed_2 = io_core_exe_0_iresp_bits_data_shifted_2; // @[AMOALU.scala:42:24, :44:23] wire _GEN_373 = size_1 == 2'h0; // @[AMOALU.scala:11:18, :45:26] wire _io_core_exe_0_iresp_bits_data_T_16; // @[AMOALU.scala:45:26] assign _io_core_exe_0_iresp_bits_data_T_16 = _GEN_373; // @[AMOALU.scala:45:26] wire _io_core_exe_0_fresp_bits_data_T_16; // @[AMOALU.scala:45:26] assign _io_core_exe_0_fresp_bits_data_T_16 = _GEN_373; // @[AMOALU.scala:45:26] wire _ldq_bits_debug_wb_data_T_16; // @[AMOALU.scala:45:26] assign _ldq_bits_debug_wb_data_T_16 = _GEN_373; // @[AMOALU.scala:45:26] wire _io_core_exe_0_iresp_bits_data_T_17 = _io_core_exe_0_iresp_bits_data_T_16; // @[AMOALU.scala:45:{26,34}] wire _io_core_exe_0_iresp_bits_data_T_18 = io_core_exe_0_iresp_bits_data_zeroed_2[7]; // @[AMOALU.scala:44:23, :45:81] wire _io_core_exe_0_iresp_bits_data_T_19 = _GEN_143[_forward_uop_T_1] & _io_core_exe_0_iresp_bits_data_T_18; // @[AMOALU.scala:45:{72,81}] wire [55:0] _io_core_exe_0_iresp_bits_data_T_20 = {56{_io_core_exe_0_iresp_bits_data_T_19}}; // @[AMOALU.scala:45:{49,72}] wire [55:0] _io_core_exe_0_iresp_bits_data_T_21 = _io_core_exe_0_iresp_bits_data_T_15[63:8]; // @[AMOALU.scala:45:{16,94}] wire [55:0] _io_core_exe_0_iresp_bits_data_T_22 = _io_core_exe_0_iresp_bits_data_T_17 ? _io_core_exe_0_iresp_bits_data_T_20 : _io_core_exe_0_iresp_bits_data_T_21; // @[AMOALU.scala:45:{20,34,49,94}] wire [63:0] _io_core_exe_0_iresp_bits_data_T_23 = {_io_core_exe_0_iresp_bits_data_T_22, io_core_exe_0_iresp_bits_data_zeroed_2}; // @[AMOALU.scala:44:23, :45:{16,20}] assign io_core_exe_0_iresp_bits_data_0 = _GEN_370 ? io_dmem_resp_0_bits_data_0 : _io_core_exe_0_iresp_bits_data_T_23; // @[AMOALU.scala:45:16] wire [31:0] io_core_exe_0_fresp_bits_data_shifted = _io_core_exe_0_fresp_bits_data_shifted_T ? _io_core_exe_0_fresp_bits_data_shifted_T_1 : _io_core_exe_0_fresp_bits_data_shifted_T_2; // @[AMOALU.scala:42:{24,29,37,55}] wire [31:0] io_core_exe_0_fresp_bits_data_zeroed = io_core_exe_0_fresp_bits_data_shifted; // @[AMOALU.scala:42:24, :44:23] wire _io_core_exe_0_fresp_bits_data_T_1 = _io_core_exe_0_fresp_bits_data_T; // @[AMOALU.scala:45:{26,34}] wire _io_core_exe_0_fresp_bits_data_T_2 = io_core_exe_0_fresp_bits_data_zeroed[31]; // @[AMOALU.scala:44:23, :45:81] wire _io_core_exe_0_fresp_bits_data_T_3 = _GEN_143[_forward_uop_T_1] & _io_core_exe_0_fresp_bits_data_T_2; // @[AMOALU.scala:45:{72,81}] wire [31:0] _io_core_exe_0_fresp_bits_data_T_4 = {32{_io_core_exe_0_fresp_bits_data_T_3}}; // @[AMOALU.scala:45:{49,72}] wire [31:0] _io_core_exe_0_fresp_bits_data_T_6 = _io_core_exe_0_fresp_bits_data_T_1 ? _io_core_exe_0_fresp_bits_data_T_4 : _io_core_exe_0_fresp_bits_data_T_5; // @[AMOALU.scala:45:{20,34,49,94}] wire [63:0] _io_core_exe_0_fresp_bits_data_T_7 = {_io_core_exe_0_fresp_bits_data_T_6, io_core_exe_0_fresp_bits_data_zeroed}; // @[AMOALU.scala:44:23, :45:{16,20}] wire [15:0] _io_core_exe_0_fresp_bits_data_shifted_T_4 = _io_core_exe_0_fresp_bits_data_T_7[31:16]; // @[AMOALU.scala:42:37, :45:16] wire [15:0] _io_core_exe_0_fresp_bits_data_shifted_T_5 = _io_core_exe_0_fresp_bits_data_T_7[15:0]; // @[AMOALU.scala:42:55, :45:16] wire [15:0] io_core_exe_0_fresp_bits_data_shifted_1 = _io_core_exe_0_fresp_bits_data_shifted_T_3 ? _io_core_exe_0_fresp_bits_data_shifted_T_4 : _io_core_exe_0_fresp_bits_data_shifted_T_5; // @[AMOALU.scala:42:{24,29,37,55}] wire [15:0] io_core_exe_0_fresp_bits_data_zeroed_1 = io_core_exe_0_fresp_bits_data_shifted_1; // @[AMOALU.scala:42:24, :44:23] wire _io_core_exe_0_fresp_bits_data_T_9 = _io_core_exe_0_fresp_bits_data_T_8; // @[AMOALU.scala:45:{26,34}] wire _io_core_exe_0_fresp_bits_data_T_10 = io_core_exe_0_fresp_bits_data_zeroed_1[15]; // @[AMOALU.scala:44:23, :45:81] wire _io_core_exe_0_fresp_bits_data_T_11 = _GEN_143[_forward_uop_T_1] & _io_core_exe_0_fresp_bits_data_T_10; // @[AMOALU.scala:45:{72,81}] wire [47:0] _io_core_exe_0_fresp_bits_data_T_12 = {48{_io_core_exe_0_fresp_bits_data_T_11}}; // @[AMOALU.scala:45:{49,72}] wire [47:0] _io_core_exe_0_fresp_bits_data_T_13 = _io_core_exe_0_fresp_bits_data_T_7[63:16]; // @[AMOALU.scala:45:{16,94}] wire [47:0] _io_core_exe_0_fresp_bits_data_T_14 = _io_core_exe_0_fresp_bits_data_T_9 ? _io_core_exe_0_fresp_bits_data_T_12 : _io_core_exe_0_fresp_bits_data_T_13; // @[AMOALU.scala:45:{20,34,49,94}] wire [63:0] _io_core_exe_0_fresp_bits_data_T_15 = {_io_core_exe_0_fresp_bits_data_T_14, io_core_exe_0_fresp_bits_data_zeroed_1}; // @[AMOALU.scala:44:23, :45:{16,20}] wire [7:0] _io_core_exe_0_fresp_bits_data_shifted_T_7 = _io_core_exe_0_fresp_bits_data_T_15[15:8]; // @[AMOALU.scala:42:37, :45:16] wire [7:0] _io_core_exe_0_fresp_bits_data_shifted_T_8 = _io_core_exe_0_fresp_bits_data_T_15[7:0]; // @[AMOALU.scala:42:55, :45:16] wire [7:0] io_core_exe_0_fresp_bits_data_shifted_2 = _io_core_exe_0_fresp_bits_data_shifted_T_6 ? _io_core_exe_0_fresp_bits_data_shifted_T_7 : _io_core_exe_0_fresp_bits_data_shifted_T_8; // @[AMOALU.scala:42:{24,29,37,55}] wire [7:0] io_core_exe_0_fresp_bits_data_zeroed_2 = io_core_exe_0_fresp_bits_data_shifted_2; // @[AMOALU.scala:42:24, :44:23] wire _io_core_exe_0_fresp_bits_data_T_17 = _io_core_exe_0_fresp_bits_data_T_16; // @[AMOALU.scala:45:{26,34}] wire _io_core_exe_0_fresp_bits_data_T_18 = io_core_exe_0_fresp_bits_data_zeroed_2[7]; // @[AMOALU.scala:44:23, :45:81] wire _io_core_exe_0_fresp_bits_data_T_19 = _GEN_143[_forward_uop_T_1] & _io_core_exe_0_fresp_bits_data_T_18; // @[AMOALU.scala:45:{72,81}] wire [55:0] _io_core_exe_0_fresp_bits_data_T_20 = {56{_io_core_exe_0_fresp_bits_data_T_19}}; // @[AMOALU.scala:45:{49,72}] wire [55:0] _io_core_exe_0_fresp_bits_data_T_21 = _io_core_exe_0_fresp_bits_data_T_15[63:8]; // @[AMOALU.scala:45:{16,94}] wire [55:0] _io_core_exe_0_fresp_bits_data_T_22 = _io_core_exe_0_fresp_bits_data_T_17 ? _io_core_exe_0_fresp_bits_data_T_20 : _io_core_exe_0_fresp_bits_data_T_21; // @[AMOALU.scala:45:{20,34,49,94}] wire [63:0] _io_core_exe_0_fresp_bits_data_T_23 = {_io_core_exe_0_fresp_bits_data_T_22, io_core_exe_0_fresp_bits_data_zeroed_2}; // @[AMOALU.scala:44:23, :45:{16,20}] assign io_core_exe_0_fresp_bits_data_0 = {1'h0, _GEN_370 ? io_dmem_resp_0_bits_data_0 : _io_core_exe_0_fresp_bits_data_T_23}; // @[AMOALU.scala:45:16] wire [31:0] ldq_bits_debug_wb_data_shifted = _ldq_bits_debug_wb_data_shifted_T ? _ldq_bits_debug_wb_data_shifted_T_1 : _ldq_bits_debug_wb_data_shifted_T_2; // @[AMOALU.scala:42:{24,29,37,55}] wire [31:0] ldq_bits_debug_wb_data_zeroed = ldq_bits_debug_wb_data_shifted; // @[AMOALU.scala:42:24, :44:23] wire _ldq_bits_debug_wb_data_T_1 = _ldq_bits_debug_wb_data_T; // @[AMOALU.scala:45:{26,34}] wire _ldq_bits_debug_wb_data_T_2 = ldq_bits_debug_wb_data_zeroed[31]; // @[AMOALU.scala:44:23, :45:81] wire _ldq_bits_debug_wb_data_T_3 = _GEN_143[_forward_uop_T_1] & _ldq_bits_debug_wb_data_T_2; // @[AMOALU.scala:45:{72,81}] wire [31:0] _ldq_bits_debug_wb_data_T_4 = {32{_ldq_bits_debug_wb_data_T_3}}; // @[AMOALU.scala:45:{49,72}] wire [31:0] _ldq_bits_debug_wb_data_T_6 = _ldq_bits_debug_wb_data_T_1 ? _ldq_bits_debug_wb_data_T_4 : _ldq_bits_debug_wb_data_T_5; // @[AMOALU.scala:45:{20,34,49,94}] wire [63:0] _ldq_bits_debug_wb_data_T_7 = {_ldq_bits_debug_wb_data_T_6, ldq_bits_debug_wb_data_zeroed}; // @[AMOALU.scala:44:23, :45:{16,20}] wire [15:0] _ldq_bits_debug_wb_data_shifted_T_4 = _ldq_bits_debug_wb_data_T_7[31:16]; // @[AMOALU.scala:42:37, :45:16] wire [15:0] _ldq_bits_debug_wb_data_shifted_T_5 = _ldq_bits_debug_wb_data_T_7[15:0]; // @[AMOALU.scala:42:55, :45:16] wire [15:0] ldq_bits_debug_wb_data_shifted_1 = _ldq_bits_debug_wb_data_shifted_T_3 ? _ldq_bits_debug_wb_data_shifted_T_4 : _ldq_bits_debug_wb_data_shifted_T_5; // @[AMOALU.scala:42:{24,29,37,55}] wire [15:0] ldq_bits_debug_wb_data_zeroed_1 = ldq_bits_debug_wb_data_shifted_1; // @[AMOALU.scala:42:24, :44:23] wire _ldq_bits_debug_wb_data_T_9 = _ldq_bits_debug_wb_data_T_8; // @[AMOALU.scala:45:{26,34}] wire _ldq_bits_debug_wb_data_T_10 = ldq_bits_debug_wb_data_zeroed_1[15]; // @[AMOALU.scala:44:23, :45:81] wire _ldq_bits_debug_wb_data_T_11 = _GEN_143[_forward_uop_T_1] & _ldq_bits_debug_wb_data_T_10; // @[AMOALU.scala:45:{72,81}] wire [47:0] _ldq_bits_debug_wb_data_T_12 = {48{_ldq_bits_debug_wb_data_T_11}}; // @[AMOALU.scala:45:{49,72}] wire [47:0] _ldq_bits_debug_wb_data_T_13 = _ldq_bits_debug_wb_data_T_7[63:16]; // @[AMOALU.scala:45:{16,94}] wire [47:0] _ldq_bits_debug_wb_data_T_14 = _ldq_bits_debug_wb_data_T_9 ? _ldq_bits_debug_wb_data_T_12 : _ldq_bits_debug_wb_data_T_13; // @[AMOALU.scala:45:{20,34,49,94}] wire [63:0] _ldq_bits_debug_wb_data_T_15 = {_ldq_bits_debug_wb_data_T_14, ldq_bits_debug_wb_data_zeroed_1}; // @[AMOALU.scala:44:23, :45:{16,20}] wire [7:0] _ldq_bits_debug_wb_data_shifted_T_7 = _ldq_bits_debug_wb_data_T_15[15:8]; // @[AMOALU.scala:42:37, :45:16] wire [7:0] _ldq_bits_debug_wb_data_shifted_T_8 = _ldq_bits_debug_wb_data_T_15[7:0]; // @[AMOALU.scala:42:55, :45:16] wire [7:0] ldq_bits_debug_wb_data_shifted_2 = _ldq_bits_debug_wb_data_shifted_T_6 ? _ldq_bits_debug_wb_data_shifted_T_7 : _ldq_bits_debug_wb_data_shifted_T_8; // @[AMOALU.scala:42:{24,29,37,55}] wire [7:0] ldq_bits_debug_wb_data_zeroed_2 = ldq_bits_debug_wb_data_shifted_2; // @[AMOALU.scala:42:24, :44:23] wire _ldq_bits_debug_wb_data_T_17 = _ldq_bits_debug_wb_data_T_16; // @[AMOALU.scala:45:{26,34}] wire _ldq_bits_debug_wb_data_T_18 = ldq_bits_debug_wb_data_zeroed_2[7]; // @[AMOALU.scala:44:23, :45:81] wire _ldq_bits_debug_wb_data_T_19 = _GEN_143[_forward_uop_T_1] & _ldq_bits_debug_wb_data_T_18; // @[AMOALU.scala:45:{72,81}] wire [55:0] _ldq_bits_debug_wb_data_T_20 = {56{_ldq_bits_debug_wb_data_T_19}}; // @[AMOALU.scala:45:{49,72}] wire [55:0] _ldq_bits_debug_wb_data_T_21 = _ldq_bits_debug_wb_data_T_15[63:8]; // @[AMOALU.scala:45:{16,94}] wire [55:0] _ldq_bits_debug_wb_data_T_22 = _ldq_bits_debug_wb_data_T_17 ? _ldq_bits_debug_wb_data_T_20 : _ldq_bits_debug_wb_data_T_21; // @[AMOALU.scala:45:{20,34,49,94}] wire [63:0] _ldq_bits_debug_wb_data_T_23 = {_ldq_bits_debug_wb_data_T_22, ldq_bits_debug_wb_data_zeroed_2}; // @[AMOALU.scala:44:23, :45:{16,20}] reg io_core_ld_miss_REG; // @[lsu.scala:1383:37] reg spec_ld_succeed_REG; // @[lsu.scala:1385:13] wire _spec_ld_succeed_T = ~spec_ld_succeed_REG; // @[lsu.scala:1385:{5,13}] reg [2:0] spec_ld_succeed_REG_1; // @[lsu.scala:1387:56] wire _spec_ld_succeed_T_1 = io_core_exe_0_iresp_bits_uop_ldq_idx_0 == spec_ld_succeed_REG_1; // @[lsu.scala:201:7, :1387:{45,56}] wire _spec_ld_succeed_T_2 = io_core_exe_0_iresp_valid_0 & _spec_ld_succeed_T_1; // @[lsu.scala:201:7, :1386:33, :1387:45] wire _spec_ld_succeed_T_3 = _spec_ld_succeed_T \| _spec_ld_succeed_T_2; // @[lsu.scala:1385:{5,47}, :1386:33] wire _spec_ld_succeed_WIRE_0 = _spec_ld_succeed_T_3; // @[lsu.scala:263:49, :1385:47] assign io_core_ld_miss_0 = ~_spec_ld_succeed_WIRE_0 & io_core_ld_miss_REG; // @[lsu.scala:201:7, :263:49, :1383:{27,37}, :1390:26, :1391:21] wire st_brkilled_mask_0; // @[lsu.scala:1401:30] wire st_brkilled_mask_1; // @[lsu.scala:1401:30] wire st_brkilled_mask_2; // @[lsu.scala:1401:30] wire st_brkilled_mask_3; // @[lsu.scala:1401:30] wire st_brkilled_mask_4; // @[lsu.scala:1401:30] wire st_brkilled_mask_5; // @[lsu.scala:1401:30] wire st_brkilled_mask_6; // @[lsu.scala:1401:30] wire st_brkilled_mask_7; // @[lsu.scala:1401:30] wire [7:0] _stq_0_bits_uop_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:85:27, :89:23] wire [7:0] _stq_0_bits_uop_br_mask_T_1 = stq_0_bits_uop_br_mask & _stq_0_bits_uop_br_mask_T; // @[util.scala:89:{21,23}] wire [7:0] _T_717 = io_core_brupdate_b1_mispredict_mask_0 & stq_0_bits_uop_br_mask; // @[util.scala:118:51] assign st_brkilled_mask_0 = stq_0_valid & (\|_T_717); // @[util.scala:118:{51,59}] wire [7:0] _stq_1_bits_uop_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:85:27, :89:23] wire [7:0] _stq_1_bits_uop_br_mask_T_1 = stq_1_bits_uop_br_mask & _stq_1_bits_uop_br_mask_T; // @[util.scala:89:{21,23}] wire [7:0] _T_727 = io_core_brupdate_b1_mispredict_mask_0 & stq_1_bits_uop_br_mask; // @[util.scala:118:51] assign st_brkilled_mask_1 = stq_1_valid & (\|_T_727); // @[util.scala:118:{51,59}] wire [7:0] _stq_2_bits_uop_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:85:27, :89:23] wire [7:0] _stq_2_bits_uop_br_mask_T_1 = stq_2_bits_uop_br_mask & _stq_2_bits_uop_br_mask_T; // @[util.scala:89:{21,23}] wire [7:0] _T_737 = io_core_brupdate_b1_mispredict_mask_0 & stq_2_bits_uop_br_mask; // @[util.scala:118:51] assign st_brkilled_mask_2 = stq_2_valid & (\|_T_737); // @[util.scala:118:{51,59}] wire [7:0] _stq_3_bits_uop_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:85:27, :89:23] wire [7:0] _stq_3_bits_uop_br_mask_T_1 = stq_3_bits_uop_br_mask & _stq_3_bits_uop_br_mask_T; // @[util.scala:89:{21,23}] wire [7:0] _T_747 = io_core_brupdate_b1_mispredict_mask_0 & stq_3_bits_uop_br_mask; // @[util.scala:118:51] assign st_brkilled_mask_3 = stq_3_valid & (\|_T_747); // @[util.scala:118:{51,59}] wire [7:0] _stq_4_bits_uop_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:85:27, :89:23] wire [7:0] _stq_4_bits_uop_br_mask_T_1 = stq_4_bits_uop_br_mask & _stq_4_bits_uop_br_mask_T; // @[util.scala:89:{21,23}] wire [7:0] _T_757 = io_core_brupdate_b1_mispredict_mask_0 & stq_4_bits_uop_br_mask; // @[util.scala:118:51] assign st_brkilled_mask_4 = stq_4_valid & (\|_T_757); // @[util.scala:118:{51,59}] wire [7:0] _stq_5_bits_uop_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:85:27, :89:23] wire [7:0] _stq_5_bits_uop_br_mask_T_1 = stq_5_bits_uop_br_mask & _stq_5_bits_uop_br_mask_T; // @[util.scala:89:{21,23}] wire [7:0] _T_767 = io_core_brupdate_b1_mispredict_mask_0 & stq_5_bits_uop_br_mask; // @[util.scala:118:51] assign st_brkilled_mask_5 = stq_5_valid & (\|_T_767); // @[util.scala:118:{51,59}] wire [7:0] _stq_6_bits_uop_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:85:27, :89:23] wire [7:0] _stq_6_bits_uop_br_mask_T_1 = stq_6_bits_uop_br_mask & _stq_6_bits_uop_br_mask_T; // @[util.scala:89:{21,23}] wire [7:0] _T_777 = io_core_brupdate_b1_mispredict_mask_0 & stq_6_bits_uop_br_mask; // @[util.scala:118:51] assign st_brkilled_mask_6 = stq_6_valid & (\|_T_777); // @[util.scala:118:{51,59}] wire [7:0] _stq_7_bits_uop_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:85:27, :89:23] wire [7:0] _stq_7_bits_uop_br_mask_T_1 = stq_7_bits_uop_br_mask & _stq_7_bits_uop_br_mask_T; // @[util.scala:89:{21,23}] wire [7:0] _T_787 = io_core_brupdate_b1_mispredict_mask_0 & stq_7_bits_uop_br_mask; // @[util.scala:118:51] assign st_brkilled_mask_7 = stq_7_valid & (\|_T_787); // @[util.scala:118:{51,59}] wire [7:0] _ldq_0_bits_uop_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:85:27, :89:23] wire [7:0] _ldq_0_bits_uop_br_mask_T_1 = ldq_0_bits_uop_br_mask & _ldq_0_bits_uop_br_mask_T; // @[util.scala:89:{21,23}] wire [7:0] _ldq_1_bits_uop_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:85:27, :89:23] wire [7:0] _ldq_1_bits_uop_br_mask_T_1 = ldq_1_bits_uop_br_mask & _ldq_1_bits_uop_br_mask_T; // @[util.scala:89:{21,23}] wire [7:0] _ldq_2_bits_uop_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:85:27, :89:23] wire [7:0] _ldq_2_bits_uop_br_mask_T_1 = ldq_2_bits_uop_br_mask & _ldq_2_bits_uop_br_mask_T; // @[util.scala:89:{21,23}] wire [7:0] _ldq_3_bits_uop_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:85:27, :89:23] wire [7:0] _ldq_3_bits_uop_br_mask_T_1 = ldq_3_bits_uop_br_mask & _ldq_3_bits_uop_br_mask_T; // @[util.scala:89:{21,23}] wire [7:0] _ldq_4_bits_uop_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:85:27, :89:23] wire [7:0] _ldq_4_bits_uop_br_mask_T_1 = ldq_4_bits_uop_br_mask & _ldq_4_bits_uop_br_mask_T; // @[util.scala:89:{21,23}] wire [7:0] _ldq_5_bits_uop_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:85:27, :89:23] wire [7:0] _ldq_5_bits_uop_br_mask_T_1 = ldq_5_bits_uop_br_mask & _ldq_5_bits_uop_br_mask_T; // @[util.scala:89:{21,23}] wire [7:0] _ldq_6_bits_uop_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:85:27, :89:23] wire [7:0] _ldq_6_bits_uop_br_mask_T_1 = ldq_6_bits_uop_br_mask & _ldq_6_bits_uop_br_mask_T; // @[util.scala:89:{21,23}] wire [7:0] _ldq_7_bits_uop_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:85:27, :89:23] wire [7:0] _ldq_7_bits_uop_br_mask_T_1 = ldq_7_bits_uop_br_mask & _ldq_7_bits_uop_br_mask_T; // @[util.scala:89:{21,23}] wire commit_store = io_core_commit_valids_0_0 & io_core_commit_uops_0_uses_stq_0; // @[lsu.scala:201:7, :1454:49] wire commit_load = io_core_commit_valids_0_0 & io_core_commit_uops_0_uses_ldq_0; // @[lsu.scala:201:7, :1455:49] wire [2:0] idx = commit_store ? stq_commit_head : ldq_head; // @[lsu.scala:213:29, :217:29, :1454:49, :1456:18] wire _GEN_374 = ~commit_store & commit_load; // @[lsu.scala:1454:49, :1455:49, :1458:5, :1460:31] wire _GEN_375 = _GEN_374 & ~reset; // @[lsu.scala:1460:31, :1461:14]
Generate the Verilog code corresponding to the following Chisel files. File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /* Like Vec.apply(idx), but tolerates indices of mismatched width / def extract(idx: UInt): T = x((idx \| 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx \| 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def \| (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a \|\| b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_\|\|_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /* Any Data subtype that has a Bool member named valid. / type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /* converts from camel case to to underscores, also removing all spaces / def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /* converts spaces or underscores to hyphens, also lowering case / def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y \| (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y \|\| y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 \| 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /* Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation / def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File PMP.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.rocket import chisel3._ import chisel3.util.{Cat, log2Ceil} import org.chipsalliance.cde.config._ import freechips.rocketchip.tile._ import freechips.rocketchip.util._ class PMPConfig extends Bundle { val l = Bool() val res = UInt(2.W) val a = UInt(2.W) val x = Bool() val w = Bool() val r = Bool() } object PMP { def lgAlign = 2 def apply(reg: PMPReg): PMP = { val pmp = Wire(new PMP()(reg.p)) pmp.cfg := reg.cfg pmp.addr := reg.addr pmp.mask := pmp.computeMask pmp } } class PMPReg(implicit p: Parameters) extends CoreBundle()(p) { val cfg = new PMPConfig val addr = UInt((paddrBits - PMP.lgAlign).W) def reset(): Unit = { cfg.a := 0.U cfg.l := 0.U } def readAddr = if (pmpGranularity.log2 == PMP.lgAlign) addr else { val mask = ((BigInt(1) << (pmpGranularity.log2 - PMP.lgAlign)) - 1).U Mux(napot, addr \| (mask >> 1), ~(~addr \| mask)) } def napot = cfg.a(1) def torNotNAPOT = cfg.a(0) def tor = !napot && torNotNAPOT def cfgLocked = cfg.l def addrLocked(next: PMPReg) = cfgLocked \|\| next.cfgLocked && next.tor } class PMP(implicit p: Parameters) extends PMPReg { val mask = UInt(paddrBits.W) import PMP._ def computeMask = { val base = Cat(addr, cfg.a(0)) \| ((pmpGranularity - 1).U >> lgAlign) Cat(base & ~(base + 1.U), ((1 << lgAlign) - 1).U) } private def comparand = ~(~(addr << lgAlign) \| (pmpGranularity - 1).U) private def pow2Match(x: UInt, lgSize: UInt, lgMaxSize: Int) = { def eval(a: UInt, b: UInt, m: UInt) = ((a ^ b) & ~m) === 0.U if (lgMaxSize <= pmpGranularity.log2) { eval(x, comparand, mask) } else { // break up the circuit; the MSB part will be CSE'd val lsbMask = mask \| UIntToOH1(lgSize, lgMaxSize) val msbMatch = eval(x >> lgMaxSize, comparand >> lgMaxSize, mask >> lgMaxSize) val lsbMatch = eval(x(lgMaxSize-1, 0), comparand(lgMaxSize-1, 0), lsbMask(lgMaxSize-1, 0)) msbMatch && lsbMatch } } private def boundMatch(x: UInt, lsbMask: UInt, lgMaxSize: Int) = { if (lgMaxSize <= pmpGranularity.log2) { x < comparand } else { // break up the circuit; the MSB part will be CSE'd val msbsLess = (x >> lgMaxSize) < (comparand >> lgMaxSize) val msbsEqual = ((x >> lgMaxSize) ^ (comparand >> lgMaxSize)) === 0.U val lsbsLess = (x(lgMaxSize-1, 0) \| lsbMask) < comparand(lgMaxSize-1, 0) msbsLess \|\| (msbsEqual && lsbsLess) } } private def lowerBoundMatch(x: UInt, lgSize: UInt, lgMaxSize: Int) = !boundMatch(x, UIntToOH1(lgSize, lgMaxSize), lgMaxSize) private def upperBoundMatch(x: UInt, lgMaxSize: Int) = boundMatch(x, 0.U, lgMaxSize) private def rangeMatch(x: UInt, lgSize: UInt, lgMaxSize: Int, prev: PMP) = prev.lowerBoundMatch(x, lgSize, lgMaxSize) && upperBoundMatch(x, lgMaxSize) private def pow2Homogeneous(x: UInt, pgLevel: UInt) = { val maskHomogeneous = pgLevelMap { idxBits => if (idxBits > paddrBits) false.B else mask(idxBits - 1) } (pgLevel) maskHomogeneous \|\| (pgLevelMap { idxBits => ((x ^ comparand) >> idxBits) =/= 0.U } (pgLevel)) } private def pgLevelMap[T](f: Int => T) = (0 until pgLevels).map { i => f(pgIdxBits + (pgLevels - 1 - i) pgLevelBits) } private def rangeHomogeneous(x: UInt, pgLevel: UInt, prev: PMP) = { val beginsAfterLower = !(x < prev.comparand) val beginsAfterUpper = !(x < comparand) val pgMask = pgLevelMap { idxBits => (((BigInt(1) << paddrBits) - (BigInt(1) << idxBits)) max 0).U } (pgLevel) val endsBeforeLower = (x & pgMask) < (prev.comparand & pgMask) val endsBeforeUpper = (x & pgMask) < (comparand & pgMask) endsBeforeLower \|\| beginsAfterUpper \|\| (beginsAfterLower && endsBeforeUpper) } // returns whether this PMP completely contains, or contains none of, a page def homogeneous(x: UInt, pgLevel: UInt, prev: PMP): Bool = Mux(napot, pow2Homogeneous(x, pgLevel), !torNotNAPOT \|\| rangeHomogeneous(x, pgLevel, prev)) // returns whether this matching PMP fully contains the access def aligned(x: UInt, lgSize: UInt, lgMaxSize: Int, prev: PMP): Bool = if (lgMaxSize <= pmpGranularity.log2) true.B else { val lsbMask = UIntToOH1(lgSize, lgMaxSize) val straddlesLowerBound = ((x >> lgMaxSize) ^ (prev.comparand >> lgMaxSize)) === 0.U && (prev.comparand(lgMaxSize-1, 0) & ~x(lgMaxSize-1, 0)) =/= 0.U val straddlesUpperBound = ((x >> lgMaxSize) ^ (comparand >> lgMaxSize)) === 0.U && (comparand(lgMaxSize-1, 0) & (x(lgMaxSize-1, 0) \| lsbMask)) =/= 0.U val rangeAligned = !(straddlesLowerBound \|\| straddlesUpperBound) val pow2Aligned = (lsbMask & ~mask(lgMaxSize-1, 0)) === 0.U Mux(napot, pow2Aligned, rangeAligned) } // returns whether this PMP matches at least one byte of the access def hit(x: UInt, lgSize: UInt, lgMaxSize: Int, prev: PMP): Bool = Mux(napot, pow2Match(x, lgSize, lgMaxSize), torNotNAPOT && rangeMatch(x, lgSize, lgMaxSize, prev)) } class PMPHomogeneityChecker(pmps: Seq[PMP])(implicit p: Parameters) { def apply(addr: UInt, pgLevel: UInt): Bool = { pmps.foldLeft((true.B, 0.U.asTypeOf(new PMP))) { case ((h, prev), pmp) => (h && pmp.homogeneous(addr, pgLevel, prev), pmp) }._1 } } class PMPChecker(lgMaxSize: Int)(implicit val p: Parameters) extends Module with HasCoreParameters { override def desiredName = s"PMPChecker_s${lgMaxSize}" val io = IO(new Bundle { val prv = Input(UInt(PRV.SZ.W)) val pmp = Input(Vec(nPMPs, new PMP)) val addr = Input(UInt(paddrBits.W)) val size = Input(UInt(log2Ceil(lgMaxSize + 1).W)) val r = Output(Bool()) val w = Output(Bool()) val x = Output(Bool()) }) val default = if (io.pmp.isEmpty) true.B else io.prv > PRV.S.U val pmp0 = WireInit(0.U.asTypeOf(new PMP)) pmp0.cfg.r := default pmp0.cfg.w := default pmp0.cfg.x := default val res = (io.pmp zip (pmp0 +: io.pmp)).reverse.foldLeft(pmp0) { case (prev, (pmp, prevPMP)) => val hit = pmp.hit(io.addr, io.size, lgMaxSize, prevPMP) val ignore = default && !pmp.cfg.l val aligned = pmp.aligned(io.addr, io.size, lgMaxSize, prevPMP) for ((name, idx) <- Seq("no", "TOR", if (pmpGranularity <= 4) "NA4" else "", "NAPOT").zipWithIndex; if name.nonEmpty) property.cover(pmp.cfg.a === idx.U, s"The cfg access is set to ${name} access ", "Cover PMP access mode setting") property.cover(pmp.cfg.l === 0x1.U, s"The cfg lock is set to high ", "Cover PMP lock mode setting") // Not including Write and no Read permission as the combination is reserved for ((name, idx) <- Seq("no", "RO", "", "RW", "X", "RX", "", "RWX").zipWithIndex; if name.nonEmpty) property.cover((Cat(pmp.cfg.x, pmp.cfg.w, pmp.cfg.r) === idx.U), s"The permission is set to ${name} access ", "Cover PMP access permission setting") for ((name, idx) <- Seq("", "TOR", if (pmpGranularity <= 4) "NA4" else "", "NAPOT").zipWithIndex; if name.nonEmpty) { property.cover(!ignore && hit && aligned && pmp.cfg.a === idx.U, s"The access matches ${name} mode ", "Cover PMP access") property.cover(pmp.cfg.l && hit && aligned && pmp.cfg.a === idx.U, s"The access matches ${name} mode with lock bit high", "Cover PMP access with lock bit") } val cur = WireInit(pmp) cur.cfg.r := aligned && (pmp.cfg.r \|\| ignore) cur.cfg.w := aligned && (pmp.cfg.w \|\| ignore) cur.cfg.x := aligned && (pmp.cfg.x \|\| ignore) Mux(hit, cur, prev) } io.r := res.cfg.r io.w := res.cfg.w io.x := res.cfg.x }	module PMPChecker_s6( // @[PMP.scala:143:7] input clock, // @[PMP.scala:143:7] input reset, // @[PMP.scala:143:7] input [1:0] io_prv, // @[PMP.scala:146:14] input io_pmp_0_cfg_l, // @[PMP.scala:146:14] input [1:0] io_pmp_0_cfg_a, // @[PMP.scala:146:14] input io_pmp_0_cfg_x, // @[PMP.scala:146:14] input io_pmp_0_cfg_w, // @[PMP.scala:146:14] input io_pmp_0_cfg_r, // @[PMP.scala:146:14] input [29:0] io_pmp_0_addr, // @[PMP.scala:146:14] input [31:0] io_pmp_0_mask, // @[PMP.scala:146:14] input io_pmp_1_cfg_l, // @[PMP.scala:146:14] input [1:0] io_pmp_1_cfg_a, // @[PMP.scala:146:14] input io_pmp_1_cfg_x, // @[PMP.scala:146:14] input io_pmp_1_cfg_w, // @[PMP.scala:146:14] input io_pmp_1_cfg_r, // @[PMP.scala:146:14] input [29:0] io_pmp_1_addr, // @[PMP.scala:146:14] input [31:0] io_pmp_1_mask, // @[PMP.scala:146:14] input io_pmp_2_cfg_l, // @[PMP.scala:146:14] input [1:0] io_pmp_2_cfg_a, // @[PMP.scala:146:14] input io_pmp_2_cfg_x, // @[PMP.scala:146:14] input io_pmp_2_cfg_w, // @[PMP.scala:146:14] input io_pmp_2_cfg_r, // @[PMP.scala:146:14] input [29:0] io_pmp_2_addr, // @[PMP.scala:146:14] input [31:0] io_pmp_2_mask, // @[PMP.scala:146:14] input io_pmp_3_cfg_l, // @[PMP.scala:146:14] input [1:0] io_pmp_3_cfg_a, // @[PMP.scala:146:14] input io_pmp_3_cfg_x, // @[PMP.scala:146:14] input io_pmp_3_cfg_w, // @[PMP.scala:146:14] input io_pmp_3_cfg_r, // @[PMP.scala:146:14] input [29:0] io_pmp_3_addr, // @[PMP.scala:146:14] input [31:0] io_pmp_3_mask, // @[PMP.scala:146:14] input io_pmp_4_cfg_l, // @[PMP.scala:146:14] input [1:0] io_pmp_4_cfg_a, // @[PMP.scala:146:14] input io_pmp_4_cfg_x, // @[PMP.scala:146:14] input io_pmp_4_cfg_w, // @[PMP.scala:146:14] input io_pmp_4_cfg_r, // @[PMP.scala:146:14] input [29:0] io_pmp_4_addr, // @[PMP.scala:146:14] input [31:0] io_pmp_4_mask, // @[PMP.scala:146:14] input io_pmp_5_cfg_l, // @[PMP.scala:146:14] input [1:0] io_pmp_5_cfg_a, // @[PMP.scala:146:14] input io_pmp_5_cfg_x, // @[PMP.scala:146:14] input io_pmp_5_cfg_w, // @[PMP.scala:146:14] input io_pmp_5_cfg_r, // @[PMP.scala:146:14] input [29:0] io_pmp_5_addr, // @[PMP.scala:146:14] input [31:0] io_pmp_5_mask, // @[PMP.scala:146:14] input io_pmp_6_cfg_l, // @[PMP.scala:146:14] input [1:0] io_pmp_6_cfg_a, // @[PMP.scala:146:14] input io_pmp_6_cfg_x, // @[PMP.scala:146:14] input io_pmp_6_cfg_w, // @[PMP.scala:146:14] input io_pmp_6_cfg_r, // @[PMP.scala:146:14] input [29:0] io_pmp_6_addr, // @[PMP.scala:146:14] input [31:0] io_pmp_6_mask, // @[PMP.scala:146:14] input io_pmp_7_cfg_l, // @[PMP.scala:146:14] input [1:0] io_pmp_7_cfg_a, // @[PMP.scala:146:14] input io_pmp_7_cfg_x, // @[PMP.scala:146:14] input io_pmp_7_cfg_w, // @[PMP.scala:146:14] input io_pmp_7_cfg_r, // @[PMP.scala:146:14] input [29:0] io_pmp_7_addr, // @[PMP.scala:146:14] input [31:0] io_pmp_7_mask, // @[PMP.scala:146:14] input [31:0] io_addr, // @[PMP.scala:146:14] output io_r, // @[PMP.scala:146:14] output io_w, // @[PMP.scala:146:14] output io_x // @[PMP.scala:146:14] ); wire [1:0] io_prv_0 = io_prv; // @[PMP.scala:143:7] wire io_pmp_0_cfg_l_0 = io_pmp_0_cfg_l; // @[PMP.scala:143:7] wire [1:0] io_pmp_0_cfg_a_0 = io_pmp_0_cfg_a; // @[PMP.scala:143:7] wire io_pmp_0_cfg_x_0 = io_pmp_0_cfg_x; // @[PMP.scala:143:7] wire io_pmp_0_cfg_w_0 = io_pmp_0_cfg_w; // @[PMP.scala:143:7] wire io_pmp_0_cfg_r_0 = io_pmp_0_cfg_r; // @[PMP.scala:143:7] wire [29:0] io_pmp_0_addr_0 = io_pmp_0_addr; // @[PMP.scala:143:7] wire [31:0] io_pmp_0_mask_0 = io_pmp_0_mask; // @[PMP.scala:143:7] wire io_pmp_1_cfg_l_0 = io_pmp_1_cfg_l; // @[PMP.scala:143:7] wire [1:0] io_pmp_1_cfg_a_0 = io_pmp_1_cfg_a; // @[PMP.scala:143:7] wire io_pmp_1_cfg_x_0 = io_pmp_1_cfg_x; // @[PMP.scala:143:7] wire io_pmp_1_cfg_w_0 = io_pmp_1_cfg_w; // @[PMP.scala:143:7] wire io_pmp_1_cfg_r_0 = io_pmp_1_cfg_r; // @[PMP.scala:143:7] wire [29:0] io_pmp_1_addr_0 = io_pmp_1_addr; // @[PMP.scala:143:7] wire [31:0] io_pmp_1_mask_0 = io_pmp_1_mask; // @[PMP.scala:143:7] wire io_pmp_2_cfg_l_0 = io_pmp_2_cfg_l; // @[PMP.scala:143:7] wire [1:0] io_pmp_2_cfg_a_0 = io_pmp_2_cfg_a; // @[PMP.scala:143:7] wire io_pmp_2_cfg_x_0 = io_pmp_2_cfg_x; // @[PMP.scala:143:7] wire io_pmp_2_cfg_w_0 = io_pmp_2_cfg_w; // @[PMP.scala:143:7] wire io_pmp_2_cfg_r_0 = io_pmp_2_cfg_r; // @[PMP.scala:143:7] wire [29:0] io_pmp_2_addr_0 = io_pmp_2_addr; // @[PMP.scala:143:7] wire [31:0] io_pmp_2_mask_0 = io_pmp_2_mask; // @[PMP.scala:143:7] wire io_pmp_3_cfg_l_0 = io_pmp_3_cfg_l; // @[PMP.scala:143:7] wire [1:0] io_pmp_3_cfg_a_0 = io_pmp_3_cfg_a; // @[PMP.scala:143:7] wire io_pmp_3_cfg_x_0 = io_pmp_3_cfg_x; // @[PMP.scala:143:7] wire io_pmp_3_cfg_w_0 = io_pmp_3_cfg_w; // @[PMP.scala:143:7] wire io_pmp_3_cfg_r_0 = io_pmp_3_cfg_r; // @[PMP.scala:143:7] wire [29:0] io_pmp_3_addr_0 = io_pmp_3_addr; // @[PMP.scala:143:7] wire [31:0] io_pmp_3_mask_0 = io_pmp_3_mask; // @[PMP.scala:143:7] wire io_pmp_4_cfg_l_0 = io_pmp_4_cfg_l; // @[PMP.scala:143:7] wire [1:0] io_pmp_4_cfg_a_0 = io_pmp_4_cfg_a; // @[PMP.scala:143:7] wire io_pmp_4_cfg_x_0 = io_pmp_4_cfg_x; // @[PMP.scala:143:7] wire io_pmp_4_cfg_w_0 = io_pmp_4_cfg_w; // @[PMP.scala:143:7] wire io_pmp_4_cfg_r_0 = io_pmp_4_cfg_r; // @[PMP.scala:143:7] wire [29:0] io_pmp_4_addr_0 = io_pmp_4_addr; // @[PMP.scala:143:7] wire [31:0] io_pmp_4_mask_0 = io_pmp_4_mask; // @[PMP.scala:143:7] wire io_pmp_5_cfg_l_0 = io_pmp_5_cfg_l; // @[PMP.scala:143:7] wire [1:0] io_pmp_5_cfg_a_0 = io_pmp_5_cfg_a; // @[PMP.scala:143:7] wire io_pmp_5_cfg_x_0 = io_pmp_5_cfg_x; // @[PMP.scala:143:7] wire io_pmp_5_cfg_w_0 = io_pmp_5_cfg_w; // @[PMP.scala:143:7] wire io_pmp_5_cfg_r_0 = io_pmp_5_cfg_r; // @[PMP.scala:143:7] wire [29:0] io_pmp_5_addr_0 = io_pmp_5_addr; // @[PMP.scala:143:7] wire [31:0] io_pmp_5_mask_0 = io_pmp_5_mask; // @[PMP.scala:143:7] wire io_pmp_6_cfg_l_0 = io_pmp_6_cfg_l; // @[PMP.scala:143:7] wire [1:0] io_pmp_6_cfg_a_0 = io_pmp_6_cfg_a; // @[PMP.scala:143:7] wire io_pmp_6_cfg_x_0 = io_pmp_6_cfg_x; // @[PMP.scala:143:7] wire io_pmp_6_cfg_w_0 = io_pmp_6_cfg_w; // @[PMP.scala:143:7] wire io_pmp_6_cfg_r_0 = io_pmp_6_cfg_r; // @[PMP.scala:143:7] wire [29:0] io_pmp_6_addr_0 = io_pmp_6_addr; // @[PMP.scala:143:7] wire [31:0] io_pmp_6_mask_0 = io_pmp_6_mask; // @[PMP.scala:143:7] wire io_pmp_7_cfg_l_0 = io_pmp_7_cfg_l; // @[PMP.scala:143:7] wire [1:0] io_pmp_7_cfg_a_0 = io_pmp_7_cfg_a; // @[PMP.scala:143:7] wire io_pmp_7_cfg_x_0 = io_pmp_7_cfg_x; // @[PMP.scala:143:7] wire io_pmp_7_cfg_w_0 = io_pmp_7_cfg_w; // @[PMP.scala:143:7] wire io_pmp_7_cfg_r_0 = io_pmp_7_cfg_r; // @[PMP.scala:143:7] wire [29:0] io_pmp_7_addr_0 = io_pmp_7_addr; // @[PMP.scala:143:7] wire [31:0] io_pmp_7_mask_0 = io_pmp_7_mask; // @[PMP.scala:143:7] wire [31:0] io_addr_0 = io_addr; // @[PMP.scala:143:7] wire [29:0] _pmp0_WIRE_addr = 30'h0; // @[PMP.scala:157:35] wire [29:0] pmp0_addr = 30'h0; // @[PMP.scala:157:22] wire [25:0] _res_hit_msbsLess_T_89 = 26'h0; // @[PMP.scala:80:52, :81:54, :123:67] wire [25:0] _res_hit_msbsEqual_T_103 = 26'h0; // @[PMP.scala:80:52, :81:54, :123:67] wire [25:0] _res_aligned_straddlesLowerBound_T_124 = 26'h0; // @[PMP.scala:80:52, :81:54, :123:67] wire [31:0] _res_hit_msbsLess_T_86 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsLess_T_87 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsEqual_T_100 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsEqual_T_101 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbsLess_T_101 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbsLess_T_102 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesLowerBound_T_121 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesLowerBound_T_122 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesLowerBound_T_128 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesLowerBound_T_129 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}] wire [31:0] _pmp0_WIRE_mask = 32'h0; // @[PMP.scala:157:35] wire [31:0] pmp0_mask = 32'h0; // @[PMP.scala:157:22] wire [31:0] _res_hit_msbsLess_T_85 = 32'h0; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsLess_T_88 = 32'h0; // @[PMP.scala:60:27] wire [31:0] _res_hit_msbsEqual_T_99 = 32'h0; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsEqual_T_102 = 32'h0; // @[PMP.scala:60:27] wire [31:0] _res_hit_lsbsLess_T_100 = 32'h0; // @[PMP.scala:60:36] wire [31:0] _res_hit_lsbsLess_T_103 = 32'h0; // @[PMP.scala:60:27] wire [31:0] _res_aligned_straddlesLowerBound_T_120 = 32'h0; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesLowerBound_T_123 = 32'h0; // @[PMP.scala:60:27] wire [31:0] _res_aligned_straddlesLowerBound_T_127 = 32'h0; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesLowerBound_T_130 = 32'h0; // @[PMP.scala:60:27] wire _pmp0_WIRE_cfg_l = 1'h0; // @[PMP.scala:157:35] wire _pmp0_WIRE_cfg_x = 1'h0; // @[PMP.scala:157:35] wire _pmp0_WIRE_cfg_w = 1'h0; // @[PMP.scala:157:35] wire _pmp0_WIRE_cfg_r = 1'h0; // @[PMP.scala:157:35] wire pmp0_cfg_l = 1'h0; // @[PMP.scala:157:22] wire res_hit_msbsLess_14 = 1'h0; // @[PMP.scala:80:39] wire res_hit_lsbsLess_14 = 1'h0; // @[PMP.scala:82:53] wire _res_hit_T_97 = 1'h0; // @[PMP.scala:83:30] wire _res_hit_T_98 = 1'h0; // @[PMP.scala:83:16] wire _res_aligned_straddlesLowerBound_T_135 = 1'h0; // @[PMP.scala:123:147] wire res_aligned_straddlesLowerBound_7 = 1'h0; // @[PMP.scala:123:90] wire [12:0] _res_hit_lsbMask_T = 13'h3F; // @[package.scala:243:71] wire [12:0] _res_hit_T_3 = 13'h3F; // @[package.scala:243:71] wire [12:0] _res_aligned_lsbMask_T = 13'h3F; // @[package.scala:243:71] wire [12:0] _res_hit_lsbMask_T_3 = 13'h3F; // @[package.scala:243:71] wire [12:0] _res_hit_T_16 = 13'h3F; // @[package.scala:243:71] wire [12:0] _res_aligned_lsbMask_T_2 = 13'h3F; // @[package.scala:243:71] wire [12:0] _res_hit_lsbMask_T_6 = 13'h3F; // @[package.scala:243:71] wire [12:0] _res_hit_T_29 = 13'h3F; // @[package.scala:243:71] wire [12:0] _res_aligned_lsbMask_T_4 = 13'h3F; // @[package.scala:243:71] wire [12:0] _res_hit_lsbMask_T_9 = 13'h3F; // @[package.scala:243:71] wire [12:0] _res_hit_T_42 = 13'h3F; // @[package.scala:243:71] wire [12:0] _res_aligned_lsbMask_T_6 = 13'h3F; // @[package.scala:243:71] wire [12:0] _res_hit_lsbMask_T_12 = 13'h3F; // @[package.scala:243:71] wire [12:0] _res_hit_T_55 = 13'h3F; // @[package.scala:243:71] wire [12:0] _res_aligned_lsbMask_T_8 = 13'h3F; // @[package.scala:243:71] wire [12:0] _res_hit_lsbMask_T_15 = 13'h3F; // @[package.scala:243:71] wire [12:0] _res_hit_T_68 = 13'h3F; // @[package.scala:243:71] wire [12:0] _res_aligned_lsbMask_T_10 = 13'h3F; // @[package.scala:243:71] wire [12:0] _res_hit_lsbMask_T_18 = 13'h3F; // @[package.scala:243:71] wire [12:0] _res_hit_T_81 = 13'h3F; // @[package.scala:243:71] wire [12:0] _res_aligned_lsbMask_T_12 = 13'h3F; // @[package.scala:243:71] wire [12:0] _res_hit_lsbMask_T_21 = 13'h3F; // @[package.scala:243:71] wire [12:0] _res_hit_T_94 = 13'h3F; // @[package.scala:243:71] wire [12:0] _res_aligned_lsbMask_T_14 = 13'h3F; // @[package.scala:243:71] wire [5:0] _res_hit_lsbMask_T_1 = 6'h3F; // @[package.scala:243:76] wire [5:0] _res_hit_T_4 = 6'h3F; // @[package.scala:243:76] wire [5:0] _res_aligned_lsbMask_T_1 = 6'h3F; // @[package.scala:243:76] wire [5:0] _res_hit_lsbMask_T_4 = 6'h3F; // @[package.scala:243:76] wire [5:0] _res_hit_T_17 = 6'h3F; // @[package.scala:243:76] wire [5:0] _res_aligned_lsbMask_T_3 = 6'h3F; // @[package.scala:243:76] wire [5:0] _res_hit_lsbMask_T_7 = 6'h3F; // @[package.scala:243:76] wire [5:0] _res_hit_T_30 = 6'h3F; // @[package.scala:243:76] wire [5:0] _res_aligned_lsbMask_T_5 = 6'h3F; // @[package.scala:243:76] wire [5:0] _res_hit_lsbMask_T_10 = 6'h3F; // @[package.scala:243:76] wire [5:0] _res_hit_T_43 = 6'h3F; // @[package.scala:243:76] wire [5:0] _res_aligned_lsbMask_T_7 = 6'h3F; // @[package.scala:243:76] wire [5:0] _res_hit_lsbMask_T_13 = 6'h3F; // @[package.scala:243:76] wire [5:0] _res_hit_T_56 = 6'h3F; // @[package.scala:243:76] wire [5:0] _res_aligned_lsbMask_T_9 = 6'h3F; // @[package.scala:243:76] wire [5:0] _res_hit_lsbMask_T_16 = 6'h3F; // @[package.scala:243:76] wire [5:0] _res_hit_T_69 = 6'h3F; // @[package.scala:243:76] wire [5:0] _res_aligned_lsbMask_T_11 = 6'h3F; // @[package.scala:243:76] wire [5:0] _res_hit_lsbMask_T_19 = 6'h3F; // @[package.scala:243:76] wire [5:0] _res_hit_T_82 = 6'h3F; // @[package.scala:243:76] wire [5:0] _res_aligned_lsbMask_T_13 = 6'h3F; // @[package.scala:243:76] wire [5:0] _res_hit_lsbMask_T_22 = 6'h3F; // @[package.scala:243:76] wire [5:0] _res_hit_T_95 = 6'h3F; // @[package.scala:243:76] wire [5:0] _res_aligned_lsbMask_T_15 = 6'h3F; // @[package.scala:243:76] wire [5:0] _res_hit_lsbMask_T_2 = 6'h0; // @[package.scala:243:46] wire [5:0] _res_hit_T_5 = 6'h0; // @[package.scala:243:46] wire [5:0] res_aligned_lsbMask = 6'h0; // @[package.scala:243:46] wire [5:0] _res_aligned_pow2Aligned_T_2 = 6'h0; // @[PMP.scala:126:32] wire [5:0] _res_hit_lsbMask_T_5 = 6'h0; // @[package.scala:243:46] wire [5:0] _res_hit_T_18 = 6'h0; // @[package.scala:243:46] wire [5:0] res_aligned_lsbMask_1 = 6'h0; // @[package.scala:243:46] wire [5:0] _res_aligned_pow2Aligned_T_5 = 6'h0; // @[PMP.scala:126:32] wire [5:0] _res_hit_lsbMask_T_8 = 6'h0; // @[package.scala:243:46] wire [5:0] _res_hit_T_31 = 6'h0; // @[package.scala:243:46] wire [5:0] res_aligned_lsbMask_2 = 6'h0; // @[package.scala:243:46] wire [5:0] _res_aligned_pow2Aligned_T_8 = 6'h0; // @[PMP.scala:126:32] wire [5:0] _res_hit_lsbMask_T_11 = 6'h0; // @[package.scala:243:46] wire [5:0] _res_hit_T_44 = 6'h0; // @[package.scala:243:46] wire [5:0] res_aligned_lsbMask_3 = 6'h0; // @[package.scala:243:46] wire [5:0] _res_aligned_pow2Aligned_T_11 = 6'h0; // @[PMP.scala:126:32] wire [5:0] _res_hit_lsbMask_T_14 = 6'h0; // @[package.scala:243:46] wire [5:0] _res_hit_T_57 = 6'h0; // @[package.scala:243:46] wire [5:0] res_aligned_lsbMask_4 = 6'h0; // @[package.scala:243:46] wire [5:0] _res_aligned_pow2Aligned_T_14 = 6'h0; // @[PMP.scala:126:32] wire [5:0] _res_hit_lsbMask_T_17 = 6'h0; // @[package.scala:243:46] wire [5:0] _res_hit_T_70 = 6'h0; // @[package.scala:243:46] wire [5:0] res_aligned_lsbMask_5 = 6'h0; // @[package.scala:243:46] wire [5:0] _res_aligned_pow2Aligned_T_17 = 6'h0; // @[PMP.scala:126:32] wire [5:0] _res_hit_lsbMask_T_20 = 6'h0; // @[package.scala:243:46] wire [5:0] _res_hit_T_83 = 6'h0; // @[package.scala:243:46] wire [5:0] res_aligned_lsbMask_6 = 6'h0; // @[package.scala:243:46] wire [5:0] _res_aligned_pow2Aligned_T_20 = 6'h0; // @[PMP.scala:126:32] wire [5:0] _res_hit_lsbMask_T_23 = 6'h0; // @[package.scala:243:46] wire [5:0] _res_hit_T_96 = 6'h0; // @[package.scala:243:46] wire [5:0] _res_hit_lsbsLess_T_104 = 6'h0; // @[PMP.scala:82:64] wire [5:0] res_aligned_lsbMask_7 = 6'h0; // @[package.scala:243:46] wire [5:0] _res_aligned_straddlesLowerBound_T_131 = 6'h0; // @[PMP.scala:123:108] wire [5:0] _res_aligned_straddlesLowerBound_T_134 = 6'h0; // @[PMP.scala:123:125] wire [5:0] _res_aligned_pow2Aligned_T_23 = 6'h0; // @[PMP.scala:126:32] wire res_aligned_pow2Aligned = 1'h1; // @[PMP.scala:126:57] wire res_aligned_pow2Aligned_1 = 1'h1; // @[PMP.scala:126:57] wire res_aligned_pow2Aligned_2 = 1'h1; // @[PMP.scala:126:57] wire res_aligned_pow2Aligned_3 = 1'h1; // @[PMP.scala:126:57] wire res_aligned_pow2Aligned_4 = 1'h1; // @[PMP.scala:126:57] wire res_aligned_pow2Aligned_5 = 1'h1; // @[PMP.scala:126:57] wire res_aligned_pow2Aligned_6 = 1'h1; // @[PMP.scala:126:57] wire _res_hit_T_99 = 1'h1; // @[PMP.scala:88:5] wire res_aligned_pow2Aligned_7 = 1'h1; // @[PMP.scala:126:57] wire [2:0] io_size = 3'h0; // @[PMP.scala:143:7, :146:14] wire [1:0] io_pmp_0_cfg_res = 2'h0; // @[PMP.scala:143:7] wire [1:0] io_pmp_1_cfg_res = 2'h0; // @[PMP.scala:143:7] wire [1:0] io_pmp_2_cfg_res = 2'h0; // @[PMP.scala:143:7] wire [1:0] io_pmp_3_cfg_res = 2'h0; // @[PMP.scala:143:7] wire [1:0] io_pmp_4_cfg_res = 2'h0; // @[PMP.scala:143:7] wire [1:0] io_pmp_5_cfg_res = 2'h0; // @[PMP.scala:143:7] wire [1:0] io_pmp_6_cfg_res = 2'h0; // @[PMP.scala:143:7] wire [1:0] io_pmp_7_cfg_res = 2'h0; // @[PMP.scala:143:7] wire [1:0] _pmp0_WIRE_cfg_res = 2'h0; // @[PMP.scala:157:35] wire [1:0] _pmp0_WIRE_cfg_a = 2'h0; // @[PMP.scala:157:35] wire [1:0] pmp0_cfg_res = 2'h0; // @[PMP.scala:157:22] wire [1:0] pmp0_cfg_a = 2'h0; // @[PMP.scala:157:22] wire [1:0] res_cur_cfg_res = 2'h0; // @[PMP.scala:181:23] wire [1:0] _res_T_44_cfg_res = 2'h0; // @[PMP.scala:185:8] wire [1:0] res_cur_1_cfg_res = 2'h0; // @[PMP.scala:181:23] wire [1:0] _res_T_89_cfg_res = 2'h0; // @[PMP.scala:185:8] wire [1:0] res_cur_2_cfg_res = 2'h0; // @[PMP.scala:181:23] wire [1:0] _res_T_134_cfg_res = 2'h0; // @[PMP.scala:185:8] wire [1:0] res_cur_3_cfg_res = 2'h0; // @[PMP.scala:181:23] wire [1:0] _res_T_179_cfg_res = 2'h0; // @[PMP.scala:185:8] wire [1:0] res_cur_4_cfg_res = 2'h0; // @[PMP.scala:181:23] wire [1:0] _res_T_224_cfg_res = 2'h0; // @[PMP.scala:185:8] wire [1:0] res_cur_5_cfg_res = 2'h0; // @[PMP.scala:181:23] wire [1:0] _res_T_269_cfg_res = 2'h0; // @[PMP.scala:185:8] wire [1:0] res_cur_6_cfg_res = 2'h0; // @[PMP.scala:181:23] wire [1:0] _res_T_314_cfg_res = 2'h0; // @[PMP.scala:185:8] wire [1:0] res_cur_7_cfg_res = 2'h0; // @[PMP.scala:181:23] wire [1:0] res_cfg_res = 2'h0; // @[PMP.scala:185:8] wire _res_T_319 = io_pmp_0_cfg_l_0; // @[PMP.scala:143:7, :170:30] wire res_cur_7_cfg_l = io_pmp_0_cfg_l_0; // @[PMP.scala:143:7, :181:23] wire [1:0] res_cur_7_cfg_a = io_pmp_0_cfg_a_0; // @[PMP.scala:143:7, :181:23] wire [29:0] res_cur_7_addr = io_pmp_0_addr_0; // @[PMP.scala:143:7, :181:23] wire [31:0] res_hit_lsbMask_7 = io_pmp_0_mask_0; // @[PMP.scala:68:26, :143:7] wire [31:0] res_cur_7_mask = io_pmp_0_mask_0; // @[PMP.scala:143:7, :181:23] wire _res_T_274 = io_pmp_1_cfg_l_0; // @[PMP.scala:143:7, :170:30] wire res_cur_6_cfg_l = io_pmp_1_cfg_l_0; // @[PMP.scala:143:7, :181:23] wire [1:0] res_cur_6_cfg_a = io_pmp_1_cfg_a_0; // @[PMP.scala:143:7, :181:23] wire [29:0] res_cur_6_addr = io_pmp_1_addr_0; // @[PMP.scala:143:7, :181:23] wire [31:0] res_hit_lsbMask_6 = io_pmp_1_mask_0; // @[PMP.scala:68:26, :143:7] wire [31:0] res_cur_6_mask = io_pmp_1_mask_0; // @[PMP.scala:143:7, :181:23] wire _res_T_229 = io_pmp_2_cfg_l_0; // @[PMP.scala:143:7, :170:30] wire res_cur_5_cfg_l = io_pmp_2_cfg_l_0; // @[PMP.scala:143:7, :181:23] wire [1:0] res_cur_5_cfg_a = io_pmp_2_cfg_a_0; // @[PMP.scala:143:7, :181:23] wire [29:0] res_cur_5_addr = io_pmp_2_addr_0; // @[PMP.scala:143:7, :181:23] wire [31:0] res_hit_lsbMask_5 = io_pmp_2_mask_0; // @[PMP.scala:68:26, :143:7] wire [31:0] res_cur_5_mask = io_pmp_2_mask_0; // @[PMP.scala:143:7, :181:23] wire _res_T_184 = io_pmp_3_cfg_l_0; // @[PMP.scala:143:7, :170:30] wire res_cur_4_cfg_l = io_pmp_3_cfg_l_0; // @[PMP.scala:143:7, :181:23] wire [1:0] res_cur_4_cfg_a = io_pmp_3_cfg_a_0; // @[PMP.scala:143:7, :181:23] wire [29:0] res_cur_4_addr = io_pmp_3_addr_0; // @[PMP.scala:143:7, :181:23] wire [31:0] res_hit_lsbMask_4 = io_pmp_3_mask_0; // @[PMP.scala:68:26, :143:7] wire [31:0] res_cur_4_mask = io_pmp_3_mask_0; // @[PMP.scala:143:7, :181:23] wire _res_T_139 = io_pmp_4_cfg_l_0; // @[PMP.scala:143:7, :170:30] wire res_cur_3_cfg_l = io_pmp_4_cfg_l_0; // @[PMP.scala:143:7, :181:23] wire [1:0] res_cur_3_cfg_a = io_pmp_4_cfg_a_0; // @[PMP.scala:143:7, :181:23] wire [29:0] res_cur_3_addr = io_pmp_4_addr_0; // @[PMP.scala:143:7, :181:23] wire [31:0] res_hit_lsbMask_3 = io_pmp_4_mask_0; // @[PMP.scala:68:26, :143:7] wire [31:0] res_cur_3_mask = io_pmp_4_mask_0; // @[PMP.scala:143:7, :181:23] wire _res_T_94 = io_pmp_5_cfg_l_0; // @[PMP.scala:143:7, :170:30] wire res_cur_2_cfg_l = io_pmp_5_cfg_l_0; // @[PMP.scala:143:7, :181:23] wire [1:0] res_cur_2_cfg_a = io_pmp_5_cfg_a_0; // @[PMP.scala:143:7, :181:23] wire [29:0] res_cur_2_addr = io_pmp_5_addr_0; // @[PMP.scala:143:7, :181:23] wire [31:0] res_hit_lsbMask_2 = io_pmp_5_mask_0; // @[PMP.scala:68:26, :143:7] wire [31:0] res_cur_2_mask = io_pmp_5_mask_0; // @[PMP.scala:143:7, :181:23] wire _res_T_49 = io_pmp_6_cfg_l_0; // @[PMP.scala:143:7, :170:30] wire res_cur_1_cfg_l = io_pmp_6_cfg_l_0; // @[PMP.scala:143:7, :181:23] wire [1:0] res_cur_1_cfg_a = io_pmp_6_cfg_a_0; // @[PMP.scala:143:7, :181:23] wire [29:0] res_cur_1_addr = io_pmp_6_addr_0; // @[PMP.scala:143:7, :181:23] wire [31:0] res_hit_lsbMask_1 = io_pmp_6_mask_0; // @[PMP.scala:68:26, :143:7] wire [31:0] res_cur_1_mask = io_pmp_6_mask_0; // @[PMP.scala:143:7, :181:23] wire _res_T_4 = io_pmp_7_cfg_l_0; // @[PMP.scala:143:7, :170:30] wire res_cur_cfg_l = io_pmp_7_cfg_l_0; // @[PMP.scala:143:7, :181:23] wire [1:0] res_cur_cfg_a = io_pmp_7_cfg_a_0; // @[PMP.scala:143:7, :181:23] wire [29:0] res_cur_addr = io_pmp_7_addr_0; // @[PMP.scala:143:7, :181:23] wire [31:0] res_hit_lsbMask = io_pmp_7_mask_0; // @[PMP.scala:68:26, :143:7] wire [31:0] res_cur_mask = io_pmp_7_mask_0; // @[PMP.scala:143:7, :181:23] wire res_cfg_r; // @[PMP.scala:185:8] wire res_cfg_w; // @[PMP.scala:185:8] wire res_cfg_x; // @[PMP.scala:185:8] wire io_r_0; // @[PMP.scala:143:7] wire io_w_0; // @[PMP.scala:143:7] wire io_x_0; // @[PMP.scala:143:7] wire default_0 = io_prv_0[1]; // @[PMP.scala:143:7, :156:56] wire pmp0_cfg_x = default_0; // @[PMP.scala:156:56, :157:22] wire pmp0_cfg_w = default_0; // @[PMP.scala:156:56, :157:22] wire pmp0_cfg_r = default_0; // @[PMP.scala:156:56, :157:22] wire _res_hit_T = io_pmp_7_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7] wire _res_aligned_T = io_pmp_7_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7] wire [25:0] _res_hit_msbMatch_T_6 = io_pmp_7_mask_0[31:6]; // @[PMP.scala:68:26, :69:72, :143:7] wire [5:0] _res_aligned_pow2Aligned_T = io_pmp_7_mask_0[5:0]; // @[PMP.scala:68:26, :126:39, :143:7] wire [25:0] _res_hit_msbMatch_T = io_addr_0[31:6]; // @[PMP.scala:69:29, :143:7] wire [25:0] _res_hit_msbsLess_T = io_addr_0[31:6]; // @[PMP.scala:69:29, :80:25, :143:7] wire [25:0] _res_hit_msbsEqual_T = io_addr_0[31:6]; // @[PMP.scala:69:29, :81:27, :143:7] wire [25:0] _res_hit_msbsLess_T_6 = io_addr_0[31:6]; // @[PMP.scala:69:29, :80:25, :143:7] wire [25:0] _res_hit_msbsEqual_T_7 = io_addr_0[31:6]; // @[PMP.scala:69:29, :81:27, :143:7] wire [25:0] _res_aligned_straddlesLowerBound_T = io_addr_0[31:6]; // @[PMP.scala:69:29, :123:35, :143:7] wire [25:0] _res_aligned_straddlesUpperBound_T = io_addr_0[31:6]; // @[PMP.scala:69:29, :124:35, :143:7] wire [25:0] _res_hit_msbMatch_T_10 = io_addr_0[31:6]; // @[PMP.scala:69:29, :143:7] wire [25:0] _res_hit_msbsLess_T_12 = io_addr_0[31:6]; // @[PMP.scala:69:29, :80:25, :143:7] wire [25:0] _res_hit_msbsEqual_T_14 = io_addr_0[31:6]; // @[PMP.scala:69:29, :81:27, :143:7] wire [25:0] _res_hit_msbsLess_T_18 = io_addr_0[31:6]; // @[PMP.scala:69:29, :80:25, :143:7] wire [25:0] _res_hit_msbsEqual_T_21 = io_addr_0[31:6]; // @[PMP.scala:69:29, :81:27, :143:7] wire [25:0] _res_aligned_straddlesLowerBound_T_17 = io_addr_0[31:6]; // @[PMP.scala:69:29, :123:35, :143:7] wire [25:0] _res_aligned_straddlesUpperBound_T_17 = io_addr_0[31:6]; // @[PMP.scala:69:29, :124:35, :143:7] wire [25:0] _res_hit_msbMatch_T_20 = io_addr_0[31:6]; // @[PMP.scala:69:29, :143:7] wire [25:0] _res_hit_msbsLess_T_24 = io_addr_0[31:6]; // @[PMP.scala:69:29, :80:25, :143:7] wire [25:0] _res_hit_msbsEqual_T_28 = io_addr_0[31:6]; // @[PMP.scala:69:29, :81:27, :143:7] wire [25:0] _res_hit_msbsLess_T_30 = io_addr_0[31:6]; // @[PMP.scala:69:29, :80:25, :143:7] wire [25:0] _res_hit_msbsEqual_T_35 = io_addr_0[31:6]; // @[PMP.scala:69:29, :81:27, :143:7] wire [25:0] _res_aligned_straddlesLowerBound_T_34 = io_addr_0[31:6]; // @[PMP.scala:69:29, :123:35, :143:7] wire [25:0] _res_aligned_straddlesUpperBound_T_34 = io_addr_0[31:6]; // @[PMP.scala:69:29, :124:35, :143:7] wire [25:0] _res_hit_msbMatch_T_30 = io_addr_0[31:6]; // @[PMP.scala:69:29, :143:7] wire [25:0] _res_hit_msbsLess_T_36 = io_addr_0[31:6]; // @[PMP.scala:69:29, :80:25, :143:7] wire [25:0] _res_hit_msbsEqual_T_42 = io_addr_0[31:6]; // @[PMP.scala:69:29, :81:27, :143:7] wire [25:0] _res_hit_msbsLess_T_42 = io_addr_0[31:6]; // @[PMP.scala:69:29, :80:25, :143:7] wire [25:0] _res_hit_msbsEqual_T_49 = io_addr_0[31:6]; // @[PMP.scala:69:29, :81:27, :143:7] wire [25:0] _res_aligned_straddlesLowerBound_T_51 = io_addr_0[31:6]; // @[PMP.scala:69:29, :123:35, :143:7] wire [25:0] _res_aligned_straddlesUpperBound_T_51 = io_addr_0[31:6]; // @[PMP.scala:69:29, :124:35, :143:7] wire [25:0] _res_hit_msbMatch_T_40 = io_addr_0[31:6]; // @[PMP.scala:69:29, :143:7] wire [25:0] _res_hit_msbsLess_T_48 = io_addr_0[31:6]; // @[PMP.scala:69:29, :80:25, :143:7] wire [25:0] _res_hit_msbsEqual_T_56 = io_addr_0[31:6]; // @[PMP.scala:69:29, :81:27, :143:7] wire [25:0] _res_hit_msbsLess_T_54 = io_addr_0[31:6]; // @[PMP.scala:69:29, :80:25, :143:7] wire [25:0] _res_hit_msbsEqual_T_63 = io_addr_0[31:6]; // @[PMP.scala:69:29, :81:27, :143:7] wire [25:0] _res_aligned_straddlesLowerBound_T_68 = io_addr_0[31:6]; // @[PMP.scala:69:29, :123:35, :143:7] wire [25:0] _res_aligned_straddlesUpperBound_T_68 = io_addr_0[31:6]; // @[PMP.scala:69:29, :124:35, :143:7] wire [25:0] _res_hit_msbMatch_T_50 = io_addr_0[31:6]; // @[PMP.scala:69:29, :143:7] wire [25:0] _res_hit_msbsLess_T_60 = io_addr_0[31:6]; // @[PMP.scala:69:29, :80:25, :143:7] wire [25:0] _res_hit_msbsEqual_T_70 = io_addr_0[31:6]; // @[PMP.scala:69:29, :81:27, :143:7] wire [25:0] _res_hit_msbsLess_T_66 = io_addr_0[31:6]; // @[PMP.scala:69:29, :80:25, :143:7] wire [25:0] _res_hit_msbsEqual_T_77 = io_addr_0[31:6]; // @[PMP.scala:69:29, :81:27, :143:7] wire [25:0] _res_aligned_straddlesLowerBound_T_85 = io_addr_0[31:6]; // @[PMP.scala:69:29, :123:35, :143:7] wire [25:0] _res_aligned_straddlesUpperBound_T_85 = io_addr_0[31:6]; // @[PMP.scala:69:29, :124:35, :143:7] wire [25:0] _res_hit_msbMatch_T_60 = io_addr_0[31:6]; // @[PMP.scala:69:29, :143:7] wire [25:0] _res_hit_msbsLess_T_72 = io_addr_0[31:6]; // @[PMP.scala:69:29, :80:25, :143:7] wire [25:0] _res_hit_msbsEqual_T_84 = io_addr_0[31:6]; // @[PMP.scala:69:29, :81:27, :143:7] wire [25:0] _res_hit_msbsLess_T_78 = io_addr_0[31:6]; // @[PMP.scala:69:29, :80:25, :143:7] wire [25:0] _res_hit_msbsEqual_T_91 = io_addr_0[31:6]; // @[PMP.scala:69:29, :81:27, :143:7] wire [25:0] _res_aligned_straddlesLowerBound_T_102 = io_addr_0[31:6]; // @[PMP.scala:69:29, :123:35, :143:7] wire [25:0] _res_aligned_straddlesUpperBound_T_102 = io_addr_0[31:6]; // @[PMP.scala:69:29, :124:35, :143:7] wire [25:0] _res_hit_msbMatch_T_70 = io_addr_0[31:6]; // @[PMP.scala:69:29, :143:7] wire [25:0] _res_hit_msbsLess_T_84 = io_addr_0[31:6]; // @[PMP.scala:69:29, :80:25, :143:7] wire [25:0] _res_hit_msbsEqual_T_98 = io_addr_0[31:6]; // @[PMP.scala:69:29, :81:27, :143:7] wire [25:0] _res_hit_msbsLess_T_90 = io_addr_0[31:6]; // @[PMP.scala:69:29, :80:25, :143:7] wire [25:0] _res_hit_msbsEqual_T_105 = io_addr_0[31:6]; // @[PMP.scala:69:29, :81:27, :143:7] wire [25:0] _res_aligned_straddlesLowerBound_T_119 = io_addr_0[31:6]; // @[PMP.scala:69:29, :123:35, :143:7] wire [25:0] _res_aligned_straddlesUpperBound_T_119 = io_addr_0[31:6]; // @[PMP.scala:69:29, :124:35, :143:7] wire [31:0] _GEN = {io_pmp_7_addr_0, 2'h0}; // @[PMP.scala:60:36, :143:7] wire [31:0] _res_hit_msbMatch_T_1; // @[PMP.scala:60:36] assign _res_hit_msbMatch_T_1 = _GEN; // @[PMP.scala:60:36] wire [31:0] _res_hit_lsbMatch_T_1; // @[PMP.scala:60:36] assign _res_hit_lsbMatch_T_1 = _GEN; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsLess_T_7; // @[PMP.scala:60:36] assign _res_hit_msbsLess_T_7 = _GEN; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsEqual_T_8; // @[PMP.scala:60:36] assign _res_hit_msbsEqual_T_8 = _GEN; // @[PMP.scala:60:36] wire [31:0] _res_hit_lsbsLess_T_9; // @[PMP.scala:60:36] assign _res_hit_lsbsLess_T_9 = _GEN; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesUpperBound_T_1; // @[PMP.scala:60:36] assign _res_aligned_straddlesUpperBound_T_1 = _GEN; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesUpperBound_T_8; // @[PMP.scala:60:36] assign _res_aligned_straddlesUpperBound_T_8 = _GEN; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbMatch_T_2 = ~_res_hit_msbMatch_T_1; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbMatch_T_3 = {_res_hit_msbMatch_T_2[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbMatch_T_4 = ~_res_hit_msbMatch_T_3; // @[PMP.scala:60:{27,48}] wire [25:0] _res_hit_msbMatch_T_5 = _res_hit_msbMatch_T_4[31:6]; // @[PMP.scala:60:27, :69:53] wire [25:0] _res_hit_msbMatch_T_7 = _res_hit_msbMatch_T ^ _res_hit_msbMatch_T_5; // @[PMP.scala:63:47, :69:{29,53}] wire [25:0] _res_hit_msbMatch_T_8 = ~_res_hit_msbMatch_T_6; // @[PMP.scala:63:54, :69:72] wire [25:0] _res_hit_msbMatch_T_9 = _res_hit_msbMatch_T_7 & _res_hit_msbMatch_T_8; // @[PMP.scala:63:{47,52,54}] wire res_hit_msbMatch = _res_hit_msbMatch_T_9 == 26'h0; // @[PMP.scala:63:{52,58}, :80:52, :81:54, :123:67] wire [5:0] _res_hit_lsbMatch_T = io_addr_0[5:0]; // @[PMP.scala:70:28, :143:7] wire [5:0] _res_hit_lsbsLess_T = io_addr_0[5:0]; // @[PMP.scala:70:28, :82:25, :143:7] wire [5:0] _res_hit_lsbsLess_T_7 = io_addr_0[5:0]; // @[PMP.scala:70:28, :82:25, :143:7] wire [5:0] _res_aligned_straddlesLowerBound_T_13 = io_addr_0[5:0]; // @[PMP.scala:70:28, :123:129, :143:7] wire [5:0] _res_aligned_straddlesUpperBound_T_13 = io_addr_0[5:0]; // @[PMP.scala:70:28, :124:119, :143:7] wire [5:0] _res_hit_lsbMatch_T_10 = io_addr_0[5:0]; // @[PMP.scala:70:28, :143:7] wire [5:0] _res_hit_lsbsLess_T_14 = io_addr_0[5:0]; // @[PMP.scala:70:28, :82:25, :143:7] wire [5:0] _res_hit_lsbsLess_T_21 = io_addr_0[5:0]; // @[PMP.scala:70:28, :82:25, :143:7] wire [5:0] _res_aligned_straddlesLowerBound_T_30 = io_addr_0[5:0]; // @[PMP.scala:70:28, :123:129, :143:7] wire [5:0] _res_aligned_straddlesUpperBound_T_30 = io_addr_0[5:0]; // @[PMP.scala:70:28, :124:119, :143:7] wire [5:0] _res_hit_lsbMatch_T_20 = io_addr_0[5:0]; // @[PMP.scala:70:28, :143:7] wire [5:0] _res_hit_lsbsLess_T_28 = io_addr_0[5:0]; // @[PMP.scala:70:28, :82:25, :143:7] wire [5:0] _res_hit_lsbsLess_T_35 = io_addr_0[5:0]; // @[PMP.scala:70:28, :82:25, :143:7] wire [5:0] _res_aligned_straddlesLowerBound_T_47 = io_addr_0[5:0]; // @[PMP.scala:70:28, :123:129, :143:7] wire [5:0] _res_aligned_straddlesUpperBound_T_47 = io_addr_0[5:0]; // @[PMP.scala:70:28, :124:119, :143:7] wire [5:0] _res_hit_lsbMatch_T_30 = io_addr_0[5:0]; // @[PMP.scala:70:28, :143:7] wire [5:0] _res_hit_lsbsLess_T_42 = io_addr_0[5:0]; // @[PMP.scala:70:28, :82:25, :143:7] wire [5:0] _res_hit_lsbsLess_T_49 = io_addr_0[5:0]; // @[PMP.scala:70:28, :82:25, :143:7] wire [5:0] _res_aligned_straddlesLowerBound_T_64 = io_addr_0[5:0]; // @[PMP.scala:70:28, :123:129, :143:7] wire [5:0] _res_aligned_straddlesUpperBound_T_64 = io_addr_0[5:0]; // @[PMP.scala:70:28, :124:119, :143:7] wire [5:0] _res_hit_lsbMatch_T_40 = io_addr_0[5:0]; // @[PMP.scala:70:28, :143:7] wire [5:0] _res_hit_lsbsLess_T_56 = io_addr_0[5:0]; // @[PMP.scala:70:28, :82:25, :143:7] wire [5:0] _res_hit_lsbsLess_T_63 = io_addr_0[5:0]; // @[PMP.scala:70:28, :82:25, :143:7] wire [5:0] _res_aligned_straddlesLowerBound_T_81 = io_addr_0[5:0]; // @[PMP.scala:70:28, :123:129, :143:7] wire [5:0] _res_aligned_straddlesUpperBound_T_81 = io_addr_0[5:0]; // @[PMP.scala:70:28, :124:119, :143:7] wire [5:0] _res_hit_lsbMatch_T_50 = io_addr_0[5:0]; // @[PMP.scala:70:28, :143:7] wire [5:0] _res_hit_lsbsLess_T_70 = io_addr_0[5:0]; // @[PMP.scala:70:28, :82:25, :143:7] wire [5:0] _res_hit_lsbsLess_T_77 = io_addr_0[5:0]; // @[PMP.scala:70:28, :82:25, :143:7] wire [5:0] _res_aligned_straddlesLowerBound_T_98 = io_addr_0[5:0]; // @[PMP.scala:70:28, :123:129, :143:7] wire [5:0] _res_aligned_straddlesUpperBound_T_98 = io_addr_0[5:0]; // @[PMP.scala:70:28, :124:119, :143:7] wire [5:0] _res_hit_lsbMatch_T_60 = io_addr_0[5:0]; // @[PMP.scala:70:28, :143:7] wire [5:0] _res_hit_lsbsLess_T_84 = io_addr_0[5:0]; // @[PMP.scala:70:28, :82:25, :143:7] wire [5:0] _res_hit_lsbsLess_T_91 = io_addr_0[5:0]; // @[PMP.scala:70:28, :82:25, :143:7] wire [5:0] _res_aligned_straddlesLowerBound_T_115 = io_addr_0[5:0]; // @[PMP.scala:70:28, :123:129, :143:7] wire [5:0] _res_aligned_straddlesUpperBound_T_115 = io_addr_0[5:0]; // @[PMP.scala:70:28, :124:119, :143:7] wire [5:0] _res_hit_lsbMatch_T_70 = io_addr_0[5:0]; // @[PMP.scala:70:28, :143:7] wire [5:0] _res_hit_lsbsLess_T_98 = io_addr_0[5:0]; // @[PMP.scala:70:28, :82:25, :143:7] wire [5:0] _res_hit_lsbsLess_T_105 = io_addr_0[5:0]; // @[PMP.scala:70:28, :82:25, :143:7] wire [5:0] _res_aligned_straddlesLowerBound_T_132 = io_addr_0[5:0]; // @[PMP.scala:70:28, :123:129, :143:7] wire [5:0] _res_aligned_straddlesUpperBound_T_132 = io_addr_0[5:0]; // @[PMP.scala:70:28, :124:119, :143:7] wire [31:0] _res_hit_lsbMatch_T_2 = ~_res_hit_lsbMatch_T_1; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_lsbMatch_T_3 = {_res_hit_lsbMatch_T_2[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbMatch_T_4 = ~_res_hit_lsbMatch_T_3; // @[PMP.scala:60:{27,48}] wire [5:0] _res_hit_lsbMatch_T_5 = _res_hit_lsbMatch_T_4[5:0]; // @[PMP.scala:60:27, :70:55] wire [5:0] _res_hit_lsbMatch_T_6 = res_hit_lsbMask[5:0]; // @[PMP.scala:68:26, :70:80] wire [5:0] _res_hit_lsbMatch_T_7 = _res_hit_lsbMatch_T ^ _res_hit_lsbMatch_T_5; // @[PMP.scala:63:47, :70:{28,55}] wire [5:0] _res_hit_lsbMatch_T_8 = ~_res_hit_lsbMatch_T_6; // @[PMP.scala:63:54, :70:80] wire [5:0] _res_hit_lsbMatch_T_9 = _res_hit_lsbMatch_T_7 & _res_hit_lsbMatch_T_8; // @[PMP.scala:63:{47,52,54}] wire res_hit_lsbMatch = _res_hit_lsbMatch_T_9 == 6'h0; // @[PMP.scala:63:{52,58}] wire _res_hit_T_1 = res_hit_msbMatch & res_hit_lsbMatch; // @[PMP.scala:63:58, :71:16] wire _res_hit_T_2 = io_pmp_7_cfg_a_0[0]; // @[PMP.scala:46:26, :143:7] wire [31:0] _GEN_0 = {io_pmp_6_addr_0, 2'h0}; // @[PMP.scala:60:36, :143:7] wire [31:0] _res_hit_msbsLess_T_1; // @[PMP.scala:60:36] assign _res_hit_msbsLess_T_1 = _GEN_0; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsEqual_T_1; // @[PMP.scala:60:36] assign _res_hit_msbsEqual_T_1 = _GEN_0; // @[PMP.scala:60:36] wire [31:0] _res_hit_lsbsLess_T_2; // @[PMP.scala:60:36] assign _res_hit_lsbsLess_T_2 = _GEN_0; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesLowerBound_T_1; // @[PMP.scala:60:36] assign _res_aligned_straddlesLowerBound_T_1 = _GEN_0; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesLowerBound_T_8; // @[PMP.scala:60:36] assign _res_aligned_straddlesLowerBound_T_8 = _GEN_0; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbMatch_T_11; // @[PMP.scala:60:36] assign _res_hit_msbMatch_T_11 = _GEN_0; // @[PMP.scala:60:36] wire [31:0] _res_hit_lsbMatch_T_11; // @[PMP.scala:60:36] assign _res_hit_lsbMatch_T_11 = _GEN_0; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsLess_T_19; // @[PMP.scala:60:36] assign _res_hit_msbsLess_T_19 = _GEN_0; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsEqual_T_22; // @[PMP.scala:60:36] assign _res_hit_msbsEqual_T_22 = _GEN_0; // @[PMP.scala:60:36] wire [31:0] _res_hit_lsbsLess_T_23; // @[PMP.scala:60:36] assign _res_hit_lsbsLess_T_23 = _GEN_0; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesUpperBound_T_18; // @[PMP.scala:60:36] assign _res_aligned_straddlesUpperBound_T_18 = _GEN_0; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesUpperBound_T_25; // @[PMP.scala:60:36] assign _res_aligned_straddlesUpperBound_T_25 = _GEN_0; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsLess_T_2 = ~_res_hit_msbsLess_T_1; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsLess_T_3 = {_res_hit_msbsLess_T_2[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsLess_T_4 = ~_res_hit_msbsLess_T_3; // @[PMP.scala:60:{27,48}] wire [25:0] _res_hit_msbsLess_T_5 = _res_hit_msbsLess_T_4[31:6]; // @[PMP.scala:60:27, :80:52] wire res_hit_msbsLess = _res_hit_msbsLess_T < _res_hit_msbsLess_T_5; // @[PMP.scala:80:{25,39,52}] wire [31:0] _res_hit_msbsEqual_T_2 = ~_res_hit_msbsEqual_T_1; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsEqual_T_3 = {_res_hit_msbsEqual_T_2[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsEqual_T_4 = ~_res_hit_msbsEqual_T_3; // @[PMP.scala:60:{27,48}] wire [25:0] _res_hit_msbsEqual_T_5 = _res_hit_msbsEqual_T_4[31:6]; // @[PMP.scala:60:27, :81:54] wire [25:0] _res_hit_msbsEqual_T_6 = _res_hit_msbsEqual_T ^ _res_hit_msbsEqual_T_5; // @[PMP.scala:81:{27,41,54}] wire res_hit_msbsEqual = _res_hit_msbsEqual_T_6 == 26'h0; // @[PMP.scala:80:52, :81:{41,54,69}, :123:67] wire [5:0] _res_hit_lsbsLess_T_1 = _res_hit_lsbsLess_T; // @[PMP.scala:82:{25,42}] wire [31:0] _res_hit_lsbsLess_T_3 = ~_res_hit_lsbsLess_T_2; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_lsbsLess_T_4 = {_res_hit_lsbsLess_T_3[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbsLess_T_5 = ~_res_hit_lsbsLess_T_4; // @[PMP.scala:60:{27,48}] wire [5:0] _res_hit_lsbsLess_T_6 = _res_hit_lsbsLess_T_5[5:0]; // @[PMP.scala:60:27, :82:64] wire res_hit_lsbsLess = _res_hit_lsbsLess_T_1 < _res_hit_lsbsLess_T_6; // @[PMP.scala:82:{42,53,64}] wire _res_hit_T_6 = res_hit_msbsEqual & res_hit_lsbsLess; // @[PMP.scala:81:69, :82:53, :83:30] wire _res_hit_T_7 = res_hit_msbsLess \| _res_hit_T_6; // @[PMP.scala:80:39, :83:{16,30}] wire _res_hit_T_8 = ~_res_hit_T_7; // @[PMP.scala:83:16, :88:5] wire [31:0] _res_hit_msbsLess_T_8 = ~_res_hit_msbsLess_T_7; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsLess_T_9 = {_res_hit_msbsLess_T_8[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsLess_T_10 = ~_res_hit_msbsLess_T_9; // @[PMP.scala:60:{27,48}] wire [25:0] _res_hit_msbsLess_T_11 = _res_hit_msbsLess_T_10[31:6]; // @[PMP.scala:60:27, :80:52] wire res_hit_msbsLess_1 = _res_hit_msbsLess_T_6 < _res_hit_msbsLess_T_11; // @[PMP.scala:80:{25,39,52}] wire [31:0] _res_hit_msbsEqual_T_9 = ~_res_hit_msbsEqual_T_8; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsEqual_T_10 = {_res_hit_msbsEqual_T_9[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsEqual_T_11 = ~_res_hit_msbsEqual_T_10; // @[PMP.scala:60:{27,48}] wire [25:0] _res_hit_msbsEqual_T_12 = _res_hit_msbsEqual_T_11[31:6]; // @[PMP.scala:60:27, :81:54] wire [25:0] _res_hit_msbsEqual_T_13 = _res_hit_msbsEqual_T_7 ^ _res_hit_msbsEqual_T_12; // @[PMP.scala:81:{27,41,54}] wire res_hit_msbsEqual_1 = _res_hit_msbsEqual_T_13 == 26'h0; // @[PMP.scala:80:52, :81:{41,54,69}, :123:67] wire [5:0] _res_hit_lsbsLess_T_8 = _res_hit_lsbsLess_T_7; // @[PMP.scala:82:{25,42}] wire [31:0] _res_hit_lsbsLess_T_10 = ~_res_hit_lsbsLess_T_9; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_lsbsLess_T_11 = {_res_hit_lsbsLess_T_10[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbsLess_T_12 = ~_res_hit_lsbsLess_T_11; // @[PMP.scala:60:{27,48}] wire [5:0] _res_hit_lsbsLess_T_13 = _res_hit_lsbsLess_T_12[5:0]; // @[PMP.scala:60:27, :82:64] wire res_hit_lsbsLess_1 = _res_hit_lsbsLess_T_8 < _res_hit_lsbsLess_T_13; // @[PMP.scala:82:{42,53,64}] wire _res_hit_T_9 = res_hit_msbsEqual_1 & res_hit_lsbsLess_1; // @[PMP.scala:81:69, :82:53, :83:30] wire _res_hit_T_10 = res_hit_msbsLess_1 \| _res_hit_T_9; // @[PMP.scala:80:39, :83:{16,30}] wire _res_hit_T_11 = _res_hit_T_8 & _res_hit_T_10; // @[PMP.scala:83:16, :88:5, :94:48] wire _res_hit_T_12 = _res_hit_T_2 & _res_hit_T_11; // @[PMP.scala:46:26, :94:48, :132:61] wire res_hit = _res_hit_T ? _res_hit_T_1 : _res_hit_T_12; // @[PMP.scala:45:20, :71:16, :132:{8,61}] wire _res_ignore_T = ~io_pmp_7_cfg_l_0; // @[PMP.scala:143:7, :164:29] wire res_ignore = default_0 & _res_ignore_T; // @[PMP.scala:156:56, :164:{26,29}] wire [31:0] _res_aligned_straddlesLowerBound_T_2 = ~_res_aligned_straddlesLowerBound_T_1; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesLowerBound_T_3 = {_res_aligned_straddlesLowerBound_T_2[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesLowerBound_T_4 = ~_res_aligned_straddlesLowerBound_T_3; // @[PMP.scala:60:{27,48}] wire [25:0] _res_aligned_straddlesLowerBound_T_5 = _res_aligned_straddlesLowerBound_T_4[31:6]; // @[PMP.scala:60:27, :123:67] wire [25:0] _res_aligned_straddlesLowerBound_T_6 = _res_aligned_straddlesLowerBound_T ^ _res_aligned_straddlesLowerBound_T_5; // @[PMP.scala:123:{35,49,67}] wire _res_aligned_straddlesLowerBound_T_7 = _res_aligned_straddlesLowerBound_T_6 == 26'h0; // @[PMP.scala:80:52, :81:54, :123:{49,67,82}] wire [31:0] _res_aligned_straddlesLowerBound_T_9 = ~_res_aligned_straddlesLowerBound_T_8; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesLowerBound_T_10 = {_res_aligned_straddlesLowerBound_T_9[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesLowerBound_T_11 = ~_res_aligned_straddlesLowerBound_T_10; // @[PMP.scala:60:{27,48}] wire [5:0] _res_aligned_straddlesLowerBound_T_12 = _res_aligned_straddlesLowerBound_T_11[5:0]; // @[PMP.scala:60:27, :123:108] wire [5:0] _res_aligned_straddlesLowerBound_T_14 = ~_res_aligned_straddlesLowerBound_T_13; // @[PMP.scala:123:{127,129}] wire [5:0] _res_aligned_straddlesLowerBound_T_15 = _res_aligned_straddlesLowerBound_T_12 & _res_aligned_straddlesLowerBound_T_14; // @[PMP.scala:123:{108,125,127}] wire _res_aligned_straddlesLowerBound_T_16 = \|_res_aligned_straddlesLowerBound_T_15; // @[PMP.scala:123:{125,147}] wire res_aligned_straddlesLowerBound = _res_aligned_straddlesLowerBound_T_7 & _res_aligned_straddlesLowerBound_T_16; // @[PMP.scala:123:{82,90,147}] wire [31:0] _res_aligned_straddlesUpperBound_T_2 = ~_res_aligned_straddlesUpperBound_T_1; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesUpperBound_T_3 = {_res_aligned_straddlesUpperBound_T_2[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesUpperBound_T_4 = ~_res_aligned_straddlesUpperBound_T_3; // @[PMP.scala:60:{27,48}] wire [25:0] _res_aligned_straddlesUpperBound_T_5 = _res_aligned_straddlesUpperBound_T_4[31:6]; // @[PMP.scala:60:27, :124:62] wire [25:0] _res_aligned_straddlesUpperBound_T_6 = _res_aligned_straddlesUpperBound_T ^ _res_aligned_straddlesUpperBound_T_5; // @[PMP.scala:124:{35,49,62}] wire _res_aligned_straddlesUpperBound_T_7 = _res_aligned_straddlesUpperBound_T_6 == 26'h0; // @[PMP.scala:80:52, :81:54, :123:67, :124:{49,77}] wire [31:0] _res_aligned_straddlesUpperBound_T_9 = ~_res_aligned_straddlesUpperBound_T_8; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesUpperBound_T_10 = {_res_aligned_straddlesUpperBound_T_9[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesUpperBound_T_11 = ~_res_aligned_straddlesUpperBound_T_10; // @[PMP.scala:60:{27,48}] wire [5:0] _res_aligned_straddlesUpperBound_T_12 = _res_aligned_straddlesUpperBound_T_11[5:0]; // @[PMP.scala:60:27, :124:98] wire [5:0] _res_aligned_straddlesUpperBound_T_14 = _res_aligned_straddlesUpperBound_T_13; // @[PMP.scala:124:{119,136}] wire [5:0] _res_aligned_straddlesUpperBound_T_15 = _res_aligned_straddlesUpperBound_T_12 & _res_aligned_straddlesUpperBound_T_14; // @[PMP.scala:124:{98,115,136}] wire _res_aligned_straddlesUpperBound_T_16 = \|_res_aligned_straddlesUpperBound_T_15; // @[PMP.scala:124:{115,148}] wire res_aligned_straddlesUpperBound = _res_aligned_straddlesUpperBound_T_7 & _res_aligned_straddlesUpperBound_T_16; // @[PMP.scala:124:{77,85,148}] wire _res_aligned_rangeAligned_T = res_aligned_straddlesLowerBound \| res_aligned_straddlesUpperBound; // @[PMP.scala:123:90, :124:85, :125:46] wire res_aligned_rangeAligned = ~_res_aligned_rangeAligned_T; // @[PMP.scala:125:{24,46}] wire [5:0] _res_aligned_pow2Aligned_T_1 = ~_res_aligned_pow2Aligned_T; // @[PMP.scala:126:{34,39}] wire res_aligned = _res_aligned_T \| res_aligned_rangeAligned; // @[PMP.scala:45:20, :125:24, :127:8] wire _res_T = io_pmp_7_cfg_a_0 == 2'h0; // @[PMP.scala:143:7, :168:32] wire _GEN_1 = io_pmp_7_cfg_a_0 == 2'h1; // @[PMP.scala:143:7, :168:32] wire _res_T_1; // @[PMP.scala:168:32] assign _res_T_1 = _GEN_1; // @[PMP.scala:168:32] wire _res_T_20; // @[PMP.scala:177:61] assign _res_T_20 = _GEN_1; // @[PMP.scala:168:32, :177:61] wire _res_T_24; // @[PMP.scala:178:63] assign _res_T_24 = _GEN_1; // @[PMP.scala:168:32, :178:63] wire _GEN_2 = io_pmp_7_cfg_a_0 == 2'h2; // @[PMP.scala:143:7, :168:32] wire _res_T_2; // @[PMP.scala:168:32] assign _res_T_2 = _GEN_2; // @[PMP.scala:168:32] wire _res_T_29; // @[PMP.scala:177:61] assign _res_T_29 = _GEN_2; // @[PMP.scala:168:32, :177:61] wire _res_T_33; // @[PMP.scala:178:63] assign _res_T_33 = _GEN_2; // @[PMP.scala:168:32, :178:63] wire _res_T_3 = &io_pmp_7_cfg_a_0; // @[PMP.scala:143:7, :168:32] wire [1:0] _GEN_3 = {io_pmp_7_cfg_x_0, io_pmp_7_cfg_w_0}; // @[PMP.scala:143:7, :174:26] wire [1:0] res_hi; // @[PMP.scala:174:26] assign res_hi = _GEN_3; // @[PMP.scala:174:26] wire [1:0] res_hi_1; // @[PMP.scala:174:26] assign res_hi_1 = _GEN_3; // @[PMP.scala:174:26] wire [1:0] res_hi_2; // @[PMP.scala:174:26] assign res_hi_2 = _GEN_3; // @[PMP.scala:174:26] wire [1:0] res_hi_3; // @[PMP.scala:174:26] assign res_hi_3 = _GEN_3; // @[PMP.scala:174:26] wire [1:0] res_hi_4; // @[PMP.scala:174:26] assign res_hi_4 = _GEN_3; // @[PMP.scala:174:26] wire [1:0] res_hi_5; // @[PMP.scala:174:26] assign res_hi_5 = _GEN_3; // @[PMP.scala:174:26] wire [2:0] _res_T_5 = {res_hi, io_pmp_7_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_6 = _res_T_5 == 3'h0; // @[PMP.scala:143:7, :146:14, :174:{26,60}] wire [2:0] _res_T_7 = {res_hi_1, io_pmp_7_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_8 = _res_T_7 == 3'h1; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_9 = {res_hi_2, io_pmp_7_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_10 = _res_T_9 == 3'h3; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_11 = {res_hi_3, io_pmp_7_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_12 = _res_T_11 == 3'h4; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_13 = {res_hi_4, io_pmp_7_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_14 = _res_T_13 == 3'h5; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_15 = {res_hi_5, io_pmp_7_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_16 = &_res_T_15; // @[PMP.scala:174:{26,60}] wire _res_T_17 = ~res_ignore; // @[PMP.scala:164:26, :177:22] wire _res_T_18 = _res_T_17 & res_hit; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_19 = _res_T_18 & res_aligned; // @[PMP.scala:127:8, :177:{30,37}] wire _res_T_21 = _res_T_19 & _res_T_20; // @[PMP.scala:177:{37,48,61}] wire _GEN_4 = io_pmp_7_cfg_l_0 & res_hit; // @[PMP.scala:132:8, :143:7, :178:32] wire _res_T_22; // @[PMP.scala:178:32] assign _res_T_22 = _GEN_4; // @[PMP.scala:178:32] wire _res_T_31; // @[PMP.scala:178:32] assign _res_T_31 = _GEN_4; // @[PMP.scala:178:32] wire _res_T_40; // @[PMP.scala:178:32] assign _res_T_40 = _GEN_4; // @[PMP.scala:178:32] wire _res_T_23 = _res_T_22 & res_aligned; // @[PMP.scala:127:8, :178:{32,39}] wire _res_T_25 = _res_T_23 & _res_T_24; // @[PMP.scala:178:{39,50,63}] wire _res_T_26 = ~res_ignore; // @[PMP.scala:164:26, :177:22] wire _res_T_27 = _res_T_26 & res_hit; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_28 = _res_T_27 & res_aligned; // @[PMP.scala:127:8, :177:{30,37}] wire _res_T_30 = _res_T_28 & _res_T_29; // @[PMP.scala:177:{37,48,61}] wire _res_T_32 = _res_T_31 & res_aligned; // @[PMP.scala:127:8, :178:{32,39}] wire _res_T_34 = _res_T_32 & _res_T_33; // @[PMP.scala:178:{39,50,63}] wire _res_T_35 = ~res_ignore; // @[PMP.scala:164:26, :177:22] wire _res_T_36 = _res_T_35 & res_hit; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_37 = _res_T_36 & res_aligned; // @[PMP.scala:127:8, :177:{30,37}] wire _res_T_38 = &io_pmp_7_cfg_a_0; // @[PMP.scala:143:7, :168:32, :177:61] wire _res_T_39 = _res_T_37 & _res_T_38; // @[PMP.scala:177:{37,48,61}] wire _res_T_41 = _res_T_40 & res_aligned; // @[PMP.scala:127:8, :178:{32,39}] wire _res_T_42 = &io_pmp_7_cfg_a_0; // @[PMP.scala:143:7, :168:32, :178:63] wire _res_T_43 = _res_T_41 & _res_T_42; // @[PMP.scala:178:{39,50,63}] wire _res_cur_cfg_x_T_1; // @[PMP.scala:184:26] wire _res_cur_cfg_w_T_1; // @[PMP.scala:183:26] wire _res_cur_cfg_r_T_1; // @[PMP.scala:182:26] wire res_cur_cfg_x; // @[PMP.scala:181:23] wire res_cur_cfg_w; // @[PMP.scala:181:23] wire res_cur_cfg_r; // @[PMP.scala:181:23] wire _res_cur_cfg_r_T = io_pmp_7_cfg_r_0 \| res_ignore; // @[PMP.scala:143:7, :164:26, :182:40] assign _res_cur_cfg_r_T_1 = res_aligned & _res_cur_cfg_r_T; // @[PMP.scala:127:8, :182:{26,40}] assign res_cur_cfg_r = _res_cur_cfg_r_T_1; // @[PMP.scala:181:23, :182:26] wire _res_cur_cfg_w_T = io_pmp_7_cfg_w_0 \| res_ignore; // @[PMP.scala:143:7, :164:26, :183:40] assign _res_cur_cfg_w_T_1 = res_aligned & _res_cur_cfg_w_T; // @[PMP.scala:127:8, :183:{26,40}] assign res_cur_cfg_w = _res_cur_cfg_w_T_1; // @[PMP.scala:181:23, :183:26] wire _res_cur_cfg_x_T = io_pmp_7_cfg_x_0 \| res_ignore; // @[PMP.scala:143:7, :164:26, :184:40] assign _res_cur_cfg_x_T_1 = res_aligned & _res_cur_cfg_x_T; // @[PMP.scala:127:8, :184:{26,40}] assign res_cur_cfg_x = _res_cur_cfg_x_T_1; // @[PMP.scala:181:23, :184:26] wire _res_T_44_cfg_l = res_hit & res_cur_cfg_l; // @[PMP.scala:132:8, :181:23, :185:8] wire [1:0] _res_T_44_cfg_a = res_hit ? res_cur_cfg_a : 2'h0; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_T_44_cfg_x = res_hit ? res_cur_cfg_x : pmp0_cfg_x; // @[PMP.scala:132:8, :157:22, :181:23, :185:8] wire _res_T_44_cfg_w = res_hit ? res_cur_cfg_w : pmp0_cfg_w; // @[PMP.scala:132:8, :157:22, :181:23, :185:8] wire _res_T_44_cfg_r = res_hit ? res_cur_cfg_r : pmp0_cfg_r; // @[PMP.scala:132:8, :157:22, :181:23, :185:8] wire [29:0] _res_T_44_addr = res_hit ? res_cur_addr : 30'h0; // @[PMP.scala:132:8, :181:23, :185:8] wire [31:0] _res_T_44_mask = res_hit ? res_cur_mask : 32'h0; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_hit_T_13 = io_pmp_6_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7] wire _res_aligned_T_1 = io_pmp_6_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7] wire [25:0] _res_hit_msbMatch_T_16 = io_pmp_6_mask_0[31:6]; // @[PMP.scala:68:26, :69:72, :143:7] wire [5:0] _res_aligned_pow2Aligned_T_3 = io_pmp_6_mask_0[5:0]; // @[PMP.scala:68:26, :126:39, :143:7] wire [31:0] _res_hit_msbMatch_T_12 = ~_res_hit_msbMatch_T_11; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbMatch_T_13 = {_res_hit_msbMatch_T_12[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbMatch_T_14 = ~_res_hit_msbMatch_T_13; // @[PMP.scala:60:{27,48}] wire [25:0] _res_hit_msbMatch_T_15 = _res_hit_msbMatch_T_14[31:6]; // @[PMP.scala:60:27, :69:53] wire [25:0] _res_hit_msbMatch_T_17 = _res_hit_msbMatch_T_10 ^ _res_hit_msbMatch_T_15; // @[PMP.scala:63:47, :69:{29,53}] wire [25:0] _res_hit_msbMatch_T_18 = ~_res_hit_msbMatch_T_16; // @[PMP.scala:63:54, :69:72] wire [25:0] _res_hit_msbMatch_T_19 = _res_hit_msbMatch_T_17 & _res_hit_msbMatch_T_18; // @[PMP.scala:63:{47,52,54}] wire res_hit_msbMatch_1 = _res_hit_msbMatch_T_19 == 26'h0; // @[PMP.scala:63:{52,58}, :80:52, :81:54, :123:67] wire [31:0] _res_hit_lsbMatch_T_12 = ~_res_hit_lsbMatch_T_11; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_lsbMatch_T_13 = {_res_hit_lsbMatch_T_12[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbMatch_T_14 = ~_res_hit_lsbMatch_T_13; // @[PMP.scala:60:{27,48}] wire [5:0] _res_hit_lsbMatch_T_15 = _res_hit_lsbMatch_T_14[5:0]; // @[PMP.scala:60:27, :70:55] wire [5:0] _res_hit_lsbMatch_T_16 = res_hit_lsbMask_1[5:0]; // @[PMP.scala:68:26, :70:80] wire [5:0] _res_hit_lsbMatch_T_17 = _res_hit_lsbMatch_T_10 ^ _res_hit_lsbMatch_T_15; // @[PMP.scala:63:47, :70:{28,55}] wire [5:0] _res_hit_lsbMatch_T_18 = ~_res_hit_lsbMatch_T_16; // @[PMP.scala:63:54, :70:80] wire [5:0] _res_hit_lsbMatch_T_19 = _res_hit_lsbMatch_T_17 & _res_hit_lsbMatch_T_18; // @[PMP.scala:63:{47,52,54}] wire res_hit_lsbMatch_1 = _res_hit_lsbMatch_T_19 == 6'h0; // @[PMP.scala:63:{52,58}] wire _res_hit_T_14 = res_hit_msbMatch_1 & res_hit_lsbMatch_1; // @[PMP.scala:63:58, :71:16] wire _res_hit_T_15 = io_pmp_6_cfg_a_0[0]; // @[PMP.scala:46:26, :143:7] wire [31:0] _GEN_5 = {io_pmp_5_addr_0, 2'h0}; // @[PMP.scala:60:36, :143:7] wire [31:0] _res_hit_msbsLess_T_13; // @[PMP.scala:60:36] assign _res_hit_msbsLess_T_13 = _GEN_5; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsEqual_T_15; // @[PMP.scala:60:36] assign _res_hit_msbsEqual_T_15 = _GEN_5; // @[PMP.scala:60:36] wire [31:0] _res_hit_lsbsLess_T_16; // @[PMP.scala:60:36] assign _res_hit_lsbsLess_T_16 = _GEN_5; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesLowerBound_T_18; // @[PMP.scala:60:36] assign _res_aligned_straddlesLowerBound_T_18 = _GEN_5; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesLowerBound_T_25; // @[PMP.scala:60:36] assign _res_aligned_straddlesLowerBound_T_25 = _GEN_5; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbMatch_T_21; // @[PMP.scala:60:36] assign _res_hit_msbMatch_T_21 = _GEN_5; // @[PMP.scala:60:36] wire [31:0] _res_hit_lsbMatch_T_21; // @[PMP.scala:60:36] assign _res_hit_lsbMatch_T_21 = _GEN_5; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsLess_T_31; // @[PMP.scala:60:36] assign _res_hit_msbsLess_T_31 = _GEN_5; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsEqual_T_36; // @[PMP.scala:60:36] assign _res_hit_msbsEqual_T_36 = _GEN_5; // @[PMP.scala:60:36] wire [31:0] _res_hit_lsbsLess_T_37; // @[PMP.scala:60:36] assign _res_hit_lsbsLess_T_37 = _GEN_5; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesUpperBound_T_35; // @[PMP.scala:60:36] assign _res_aligned_straddlesUpperBound_T_35 = _GEN_5; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesUpperBound_T_42; // @[PMP.scala:60:36] assign _res_aligned_straddlesUpperBound_T_42 = _GEN_5; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsLess_T_14 = ~_res_hit_msbsLess_T_13; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsLess_T_15 = {_res_hit_msbsLess_T_14[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsLess_T_16 = ~_res_hit_msbsLess_T_15; // @[PMP.scala:60:{27,48}] wire [25:0] _res_hit_msbsLess_T_17 = _res_hit_msbsLess_T_16[31:6]; // @[PMP.scala:60:27, :80:52] wire res_hit_msbsLess_2 = _res_hit_msbsLess_T_12 < _res_hit_msbsLess_T_17; // @[PMP.scala:80:{25,39,52}] wire [31:0] _res_hit_msbsEqual_T_16 = ~_res_hit_msbsEqual_T_15; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsEqual_T_17 = {_res_hit_msbsEqual_T_16[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsEqual_T_18 = ~_res_hit_msbsEqual_T_17; // @[PMP.scala:60:{27,48}] wire [25:0] _res_hit_msbsEqual_T_19 = _res_hit_msbsEqual_T_18[31:6]; // @[PMP.scala:60:27, :81:54] wire [25:0] _res_hit_msbsEqual_T_20 = _res_hit_msbsEqual_T_14 ^ _res_hit_msbsEqual_T_19; // @[PMP.scala:81:{27,41,54}] wire res_hit_msbsEqual_2 = _res_hit_msbsEqual_T_20 == 26'h0; // @[PMP.scala:80:52, :81:{41,54,69}, :123:67] wire [5:0] _res_hit_lsbsLess_T_15 = _res_hit_lsbsLess_T_14; // @[PMP.scala:82:{25,42}] wire [31:0] _res_hit_lsbsLess_T_17 = ~_res_hit_lsbsLess_T_16; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_lsbsLess_T_18 = {_res_hit_lsbsLess_T_17[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbsLess_T_19 = ~_res_hit_lsbsLess_T_18; // @[PMP.scala:60:{27,48}] wire [5:0] _res_hit_lsbsLess_T_20 = _res_hit_lsbsLess_T_19[5:0]; // @[PMP.scala:60:27, :82:64] wire res_hit_lsbsLess_2 = _res_hit_lsbsLess_T_15 < _res_hit_lsbsLess_T_20; // @[PMP.scala:82:{42,53,64}] wire _res_hit_T_19 = res_hit_msbsEqual_2 & res_hit_lsbsLess_2; // @[PMP.scala:81:69, :82:53, :83:30] wire _res_hit_T_20 = res_hit_msbsLess_2 \| _res_hit_T_19; // @[PMP.scala:80:39, :83:{16,30}] wire _res_hit_T_21 = ~_res_hit_T_20; // @[PMP.scala:83:16, :88:5] wire [31:0] _res_hit_msbsLess_T_20 = ~_res_hit_msbsLess_T_19; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsLess_T_21 = {_res_hit_msbsLess_T_20[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsLess_T_22 = ~_res_hit_msbsLess_T_21; // @[PMP.scala:60:{27,48}] wire [25:0] _res_hit_msbsLess_T_23 = _res_hit_msbsLess_T_22[31:6]; // @[PMP.scala:60:27, :80:52] wire res_hit_msbsLess_3 = _res_hit_msbsLess_T_18 < _res_hit_msbsLess_T_23; // @[PMP.scala:80:{25,39,52}] wire [31:0] _res_hit_msbsEqual_T_23 = ~_res_hit_msbsEqual_T_22; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsEqual_T_24 = {_res_hit_msbsEqual_T_23[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsEqual_T_25 = ~_res_hit_msbsEqual_T_24; // @[PMP.scala:60:{27,48}] wire [25:0] _res_hit_msbsEqual_T_26 = _res_hit_msbsEqual_T_25[31:6]; // @[PMP.scala:60:27, :81:54] wire [25:0] _res_hit_msbsEqual_T_27 = _res_hit_msbsEqual_T_21 ^ _res_hit_msbsEqual_T_26; // @[PMP.scala:81:{27,41,54}] wire res_hit_msbsEqual_3 = _res_hit_msbsEqual_T_27 == 26'h0; // @[PMP.scala:80:52, :81:{41,54,69}, :123:67] wire [5:0] _res_hit_lsbsLess_T_22 = _res_hit_lsbsLess_T_21; // @[PMP.scala:82:{25,42}] wire [31:0] _res_hit_lsbsLess_T_24 = ~_res_hit_lsbsLess_T_23; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_lsbsLess_T_25 = {_res_hit_lsbsLess_T_24[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbsLess_T_26 = ~_res_hit_lsbsLess_T_25; // @[PMP.scala:60:{27,48}] wire [5:0] _res_hit_lsbsLess_T_27 = _res_hit_lsbsLess_T_26[5:0]; // @[PMP.scala:60:27, :82:64] wire res_hit_lsbsLess_3 = _res_hit_lsbsLess_T_22 < _res_hit_lsbsLess_T_27; // @[PMP.scala:82:{42,53,64}] wire _res_hit_T_22 = res_hit_msbsEqual_3 & res_hit_lsbsLess_3; // @[PMP.scala:81:69, :82:53, :83:30] wire _res_hit_T_23 = res_hit_msbsLess_3 \| _res_hit_T_22; // @[PMP.scala:80:39, :83:{16,30}] wire _res_hit_T_24 = _res_hit_T_21 & _res_hit_T_23; // @[PMP.scala:83:16, :88:5, :94:48] wire _res_hit_T_25 = _res_hit_T_15 & _res_hit_T_24; // @[PMP.scala:46:26, :94:48, :132:61] wire res_hit_1 = _res_hit_T_13 ? _res_hit_T_14 : _res_hit_T_25; // @[PMP.scala:45:20, :71:16, :132:{8,61}] wire _res_ignore_T_1 = ~io_pmp_6_cfg_l_0; // @[PMP.scala:143:7, :164:29] wire res_ignore_1 = default_0 & _res_ignore_T_1; // @[PMP.scala:156:56, :164:{26,29}] wire [31:0] _res_aligned_straddlesLowerBound_T_19 = ~_res_aligned_straddlesLowerBound_T_18; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesLowerBound_T_20 = {_res_aligned_straddlesLowerBound_T_19[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesLowerBound_T_21 = ~_res_aligned_straddlesLowerBound_T_20; // @[PMP.scala:60:{27,48}] wire [25:0] _res_aligned_straddlesLowerBound_T_22 = _res_aligned_straddlesLowerBound_T_21[31:6]; // @[PMP.scala:60:27, :123:67] wire [25:0] _res_aligned_straddlesLowerBound_T_23 = _res_aligned_straddlesLowerBound_T_17 ^ _res_aligned_straddlesLowerBound_T_22; // @[PMP.scala:123:{35,49,67}] wire _res_aligned_straddlesLowerBound_T_24 = _res_aligned_straddlesLowerBound_T_23 == 26'h0; // @[PMP.scala:80:52, :81:54, :123:{49,67,82}] wire [31:0] _res_aligned_straddlesLowerBound_T_26 = ~_res_aligned_straddlesLowerBound_T_25; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesLowerBound_T_27 = {_res_aligned_straddlesLowerBound_T_26[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesLowerBound_T_28 = ~_res_aligned_straddlesLowerBound_T_27; // @[PMP.scala:60:{27,48}] wire [5:0] _res_aligned_straddlesLowerBound_T_29 = _res_aligned_straddlesLowerBound_T_28[5:0]; // @[PMP.scala:60:27, :123:108] wire [5:0] _res_aligned_straddlesLowerBound_T_31 = ~_res_aligned_straddlesLowerBound_T_30; // @[PMP.scala:123:{127,129}] wire [5:0] _res_aligned_straddlesLowerBound_T_32 = _res_aligned_straddlesLowerBound_T_29 & _res_aligned_straddlesLowerBound_T_31; // @[PMP.scala:123:{108,125,127}] wire _res_aligned_straddlesLowerBound_T_33 = \|_res_aligned_straddlesLowerBound_T_32; // @[PMP.scala:123:{125,147}] wire res_aligned_straddlesLowerBound_1 = _res_aligned_straddlesLowerBound_T_24 & _res_aligned_straddlesLowerBound_T_33; // @[PMP.scala:123:{82,90,147}] wire [31:0] _res_aligned_straddlesUpperBound_T_19 = ~_res_aligned_straddlesUpperBound_T_18; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesUpperBound_T_20 = {_res_aligned_straddlesUpperBound_T_19[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesUpperBound_T_21 = ~_res_aligned_straddlesUpperBound_T_20; // @[PMP.scala:60:{27,48}] wire [25:0] _res_aligned_straddlesUpperBound_T_22 = _res_aligned_straddlesUpperBound_T_21[31:6]; // @[PMP.scala:60:27, :124:62] wire [25:0] _res_aligned_straddlesUpperBound_T_23 = _res_aligned_straddlesUpperBound_T_17 ^ _res_aligned_straddlesUpperBound_T_22; // @[PMP.scala:124:{35,49,62}] wire _res_aligned_straddlesUpperBound_T_24 = _res_aligned_straddlesUpperBound_T_23 == 26'h0; // @[PMP.scala:80:52, :81:54, :123:67, :124:{49,77}] wire [31:0] _res_aligned_straddlesUpperBound_T_26 = ~_res_aligned_straddlesUpperBound_T_25; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesUpperBound_T_27 = {_res_aligned_straddlesUpperBound_T_26[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesUpperBound_T_28 = ~_res_aligned_straddlesUpperBound_T_27; // @[PMP.scala:60:{27,48}] wire [5:0] _res_aligned_straddlesUpperBound_T_29 = _res_aligned_straddlesUpperBound_T_28[5:0]; // @[PMP.scala:60:27, :124:98] wire [5:0] _res_aligned_straddlesUpperBound_T_31 = _res_aligned_straddlesUpperBound_T_30; // @[PMP.scala:124:{119,136}] wire [5:0] _res_aligned_straddlesUpperBound_T_32 = _res_aligned_straddlesUpperBound_T_29 & _res_aligned_straddlesUpperBound_T_31; // @[PMP.scala:124:{98,115,136}] wire _res_aligned_straddlesUpperBound_T_33 = \|_res_aligned_straddlesUpperBound_T_32; // @[PMP.scala:124:{115,148}] wire res_aligned_straddlesUpperBound_1 = _res_aligned_straddlesUpperBound_T_24 & _res_aligned_straddlesUpperBound_T_33; // @[PMP.scala:124:{77,85,148}] wire _res_aligned_rangeAligned_T_1 = res_aligned_straddlesLowerBound_1 \| res_aligned_straddlesUpperBound_1; // @[PMP.scala:123:90, :124:85, :125:46] wire res_aligned_rangeAligned_1 = ~_res_aligned_rangeAligned_T_1; // @[PMP.scala:125:{24,46}] wire [5:0] _res_aligned_pow2Aligned_T_4 = ~_res_aligned_pow2Aligned_T_3; // @[PMP.scala:126:{34,39}] wire res_aligned_1 = _res_aligned_T_1 \| res_aligned_rangeAligned_1; // @[PMP.scala:45:20, :125:24, :127:8] wire _res_T_45 = io_pmp_6_cfg_a_0 == 2'h0; // @[PMP.scala:143:7, :168:32] wire _GEN_6 = io_pmp_6_cfg_a_0 == 2'h1; // @[PMP.scala:143:7, :168:32] wire _res_T_46; // @[PMP.scala:168:32] assign _res_T_46 = _GEN_6; // @[PMP.scala:168:32] wire _res_T_65; // @[PMP.scala:177:61] assign _res_T_65 = _GEN_6; // @[PMP.scala:168:32, :177:61] wire _res_T_69; // @[PMP.scala:178:63] assign _res_T_69 = _GEN_6; // @[PMP.scala:168:32, :178:63] wire _GEN_7 = io_pmp_6_cfg_a_0 == 2'h2; // @[PMP.scala:143:7, :168:32] wire _res_T_47; // @[PMP.scala:168:32] assign _res_T_47 = _GEN_7; // @[PMP.scala:168:32] wire _res_T_74; // @[PMP.scala:177:61] assign _res_T_74 = _GEN_7; // @[PMP.scala:168:32, :177:61] wire _res_T_78; // @[PMP.scala:178:63] assign _res_T_78 = _GEN_7; // @[PMP.scala:168:32, :178:63] wire _res_T_48 = &io_pmp_6_cfg_a_0; // @[PMP.scala:143:7, :168:32] wire [1:0] _GEN_8 = {io_pmp_6_cfg_x_0, io_pmp_6_cfg_w_0}; // @[PMP.scala:143:7, :174:26] wire [1:0] res_hi_6; // @[PMP.scala:174:26] assign res_hi_6 = _GEN_8; // @[PMP.scala:174:26] wire [1:0] res_hi_7; // @[PMP.scala:174:26] assign res_hi_7 = _GEN_8; // @[PMP.scala:174:26] wire [1:0] res_hi_8; // @[PMP.scala:174:26] assign res_hi_8 = _GEN_8; // @[PMP.scala:174:26] wire [1:0] res_hi_9; // @[PMP.scala:174:26] assign res_hi_9 = _GEN_8; // @[PMP.scala:174:26] wire [1:0] res_hi_10; // @[PMP.scala:174:26] assign res_hi_10 = _GEN_8; // @[PMP.scala:174:26] wire [1:0] res_hi_11; // @[PMP.scala:174:26] assign res_hi_11 = _GEN_8; // @[PMP.scala:174:26] wire [2:0] _res_T_50 = {res_hi_6, io_pmp_6_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_51 = _res_T_50 == 3'h0; // @[PMP.scala:143:7, :146:14, :174:{26,60}] wire [2:0] _res_T_52 = {res_hi_7, io_pmp_6_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_53 = _res_T_52 == 3'h1; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_54 = {res_hi_8, io_pmp_6_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_55 = _res_T_54 == 3'h3; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_56 = {res_hi_9, io_pmp_6_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_57 = _res_T_56 == 3'h4; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_58 = {res_hi_10, io_pmp_6_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_59 = _res_T_58 == 3'h5; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_60 = {res_hi_11, io_pmp_6_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_61 = &_res_T_60; // @[PMP.scala:174:{26,60}] wire _res_T_62 = ~res_ignore_1; // @[PMP.scala:164:26, :177:22] wire _res_T_63 = _res_T_62 & res_hit_1; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_64 = _res_T_63 & res_aligned_1; // @[PMP.scala:127:8, :177:{30,37}] wire _res_T_66 = _res_T_64 & _res_T_65; // @[PMP.scala:177:{37,48,61}] wire _GEN_9 = io_pmp_6_cfg_l_0 & res_hit_1; // @[PMP.scala:132:8, :143:7, :178:32] wire _res_T_67; // @[PMP.scala:178:32] assign _res_T_67 = _GEN_9; // @[PMP.scala:178:32] wire _res_T_76; // @[PMP.scala:178:32] assign _res_T_76 = _GEN_9; // @[PMP.scala:178:32] wire _res_T_85; // @[PMP.scala:178:32] assign _res_T_85 = _GEN_9; // @[PMP.scala:178:32] wire _res_T_68 = _res_T_67 & res_aligned_1; // @[PMP.scala:127:8, :178:{32,39}] wire _res_T_70 = _res_T_68 & _res_T_69; // @[PMP.scala:178:{39,50,63}] wire _res_T_71 = ~res_ignore_1; // @[PMP.scala:164:26, :177:22] wire _res_T_72 = _res_T_71 & res_hit_1; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_73 = _res_T_72 & res_aligned_1; // @[PMP.scala:127:8, :177:{30,37}] wire _res_T_75 = _res_T_73 & _res_T_74; // @[PMP.scala:177:{37,48,61}] wire _res_T_77 = _res_T_76 & res_aligned_1; // @[PMP.scala:127:8, :178:{32,39}] wire _res_T_79 = _res_T_77 & _res_T_78; // @[PMP.scala:178:{39,50,63}] wire _res_T_80 = ~res_ignore_1; // @[PMP.scala:164:26, :177:22] wire _res_T_81 = _res_T_80 & res_hit_1; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_82 = _res_T_81 & res_aligned_1; // @[PMP.scala:127:8, :177:{30,37}] wire _res_T_83 = &io_pmp_6_cfg_a_0; // @[PMP.scala:143:7, :168:32, :177:61] wire _res_T_84 = _res_T_82 & _res_T_83; // @[PMP.scala:177:{37,48,61}] wire _res_T_86 = _res_T_85 & res_aligned_1; // @[PMP.scala:127:8, :178:{32,39}] wire _res_T_87 = &io_pmp_6_cfg_a_0; // @[PMP.scala:143:7, :168:32, :178:63] wire _res_T_88 = _res_T_86 & _res_T_87; // @[PMP.scala:178:{39,50,63}] wire _res_cur_cfg_x_T_3; // @[PMP.scala:184:26] wire _res_cur_cfg_w_T_3; // @[PMP.scala:183:26] wire _res_cur_cfg_r_T_3; // @[PMP.scala:182:26] wire res_cur_1_cfg_x; // @[PMP.scala:181:23] wire res_cur_1_cfg_w; // @[PMP.scala:181:23] wire res_cur_1_cfg_r; // @[PMP.scala:181:23] wire _res_cur_cfg_r_T_2 = io_pmp_6_cfg_r_0 \| res_ignore_1; // @[PMP.scala:143:7, :164:26, :182:40] assign _res_cur_cfg_r_T_3 = res_aligned_1 & _res_cur_cfg_r_T_2; // @[PMP.scala:127:8, :182:{26,40}] assign res_cur_1_cfg_r = _res_cur_cfg_r_T_3; // @[PMP.scala:181:23, :182:26] wire _res_cur_cfg_w_T_2 = io_pmp_6_cfg_w_0 \| res_ignore_1; // @[PMP.scala:143:7, :164:26, :183:40] assign _res_cur_cfg_w_T_3 = res_aligned_1 & _res_cur_cfg_w_T_2; // @[PMP.scala:127:8, :183:{26,40}] assign res_cur_1_cfg_w = _res_cur_cfg_w_T_3; // @[PMP.scala:181:23, :183:26] wire _res_cur_cfg_x_T_2 = io_pmp_6_cfg_x_0 \| res_ignore_1; // @[PMP.scala:143:7, :164:26, :184:40] assign _res_cur_cfg_x_T_3 = res_aligned_1 & _res_cur_cfg_x_T_2; // @[PMP.scala:127:8, :184:{26,40}] assign res_cur_1_cfg_x = _res_cur_cfg_x_T_3; // @[PMP.scala:181:23, :184:26] wire _res_T_89_cfg_l = res_hit_1 ? res_cur_1_cfg_l : _res_T_44_cfg_l; // @[PMP.scala:132:8, :181:23, :185:8] wire [1:0] _res_T_89_cfg_a = res_hit_1 ? res_cur_1_cfg_a : _res_T_44_cfg_a; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_T_89_cfg_x = res_hit_1 ? res_cur_1_cfg_x : _res_T_44_cfg_x; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_T_89_cfg_w = res_hit_1 ? res_cur_1_cfg_w : _res_T_44_cfg_w; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_T_89_cfg_r = res_hit_1 ? res_cur_1_cfg_r : _res_T_44_cfg_r; // @[PMP.scala:132:8, :181:23, :185:8] wire [29:0] _res_T_89_addr = res_hit_1 ? res_cur_1_addr : _res_T_44_addr; // @[PMP.scala:132:8, :181:23, :185:8] wire [31:0] _res_T_89_mask = res_hit_1 ? res_cur_1_mask : _res_T_44_mask; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_hit_T_26 = io_pmp_5_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7] wire _res_aligned_T_2 = io_pmp_5_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7] wire [25:0] _res_hit_msbMatch_T_26 = io_pmp_5_mask_0[31:6]; // @[PMP.scala:68:26, :69:72, :143:7] wire [5:0] _res_aligned_pow2Aligned_T_6 = io_pmp_5_mask_0[5:0]; // @[PMP.scala:68:26, :126:39, :143:7] wire [31:0] _res_hit_msbMatch_T_22 = ~_res_hit_msbMatch_T_21; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbMatch_T_23 = {_res_hit_msbMatch_T_22[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbMatch_T_24 = ~_res_hit_msbMatch_T_23; // @[PMP.scala:60:{27,48}] wire [25:0] _res_hit_msbMatch_T_25 = _res_hit_msbMatch_T_24[31:6]; // @[PMP.scala:60:27, :69:53] wire [25:0] _res_hit_msbMatch_T_27 = _res_hit_msbMatch_T_20 ^ _res_hit_msbMatch_T_25; // @[PMP.scala:63:47, :69:{29,53}] wire [25:0] _res_hit_msbMatch_T_28 = ~_res_hit_msbMatch_T_26; // @[PMP.scala:63:54, :69:72] wire [25:0] _res_hit_msbMatch_T_29 = _res_hit_msbMatch_T_27 & _res_hit_msbMatch_T_28; // @[PMP.scala:63:{47,52,54}] wire res_hit_msbMatch_2 = _res_hit_msbMatch_T_29 == 26'h0; // @[PMP.scala:63:{52,58}, :80:52, :81:54, :123:67] wire [31:0] _res_hit_lsbMatch_T_22 = ~_res_hit_lsbMatch_T_21; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_lsbMatch_T_23 = {_res_hit_lsbMatch_T_22[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbMatch_T_24 = ~_res_hit_lsbMatch_T_23; // @[PMP.scala:60:{27,48}] wire [5:0] _res_hit_lsbMatch_T_25 = _res_hit_lsbMatch_T_24[5:0]; // @[PMP.scala:60:27, :70:55] wire [5:0] _res_hit_lsbMatch_T_26 = res_hit_lsbMask_2[5:0]; // @[PMP.scala:68:26, :70:80] wire [5:0] _res_hit_lsbMatch_T_27 = _res_hit_lsbMatch_T_20 ^ _res_hit_lsbMatch_T_25; // @[PMP.scala:63:47, :70:{28,55}] wire [5:0] _res_hit_lsbMatch_T_28 = ~_res_hit_lsbMatch_T_26; // @[PMP.scala:63:54, :70:80] wire [5:0] _res_hit_lsbMatch_T_29 = _res_hit_lsbMatch_T_27 & _res_hit_lsbMatch_T_28; // @[PMP.scala:63:{47,52,54}] wire res_hit_lsbMatch_2 = _res_hit_lsbMatch_T_29 == 6'h0; // @[PMP.scala:63:{52,58}] wire _res_hit_T_27 = res_hit_msbMatch_2 & res_hit_lsbMatch_2; // @[PMP.scala:63:58, :71:16] wire _res_hit_T_28 = io_pmp_5_cfg_a_0[0]; // @[PMP.scala:46:26, :143:7] wire [31:0] _GEN_10 = {io_pmp_4_addr_0, 2'h0}; // @[PMP.scala:60:36, :143:7] wire [31:0] _res_hit_msbsLess_T_25; // @[PMP.scala:60:36] assign _res_hit_msbsLess_T_25 = _GEN_10; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsEqual_T_29; // @[PMP.scala:60:36] assign _res_hit_msbsEqual_T_29 = _GEN_10; // @[PMP.scala:60:36] wire [31:0] _res_hit_lsbsLess_T_30; // @[PMP.scala:60:36] assign _res_hit_lsbsLess_T_30 = _GEN_10; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesLowerBound_T_35; // @[PMP.scala:60:36] assign _res_aligned_straddlesLowerBound_T_35 = _GEN_10; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesLowerBound_T_42; // @[PMP.scala:60:36] assign _res_aligned_straddlesLowerBound_T_42 = _GEN_10; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbMatch_T_31; // @[PMP.scala:60:36] assign _res_hit_msbMatch_T_31 = _GEN_10; // @[PMP.scala:60:36] wire [31:0] _res_hit_lsbMatch_T_31; // @[PMP.scala:60:36] assign _res_hit_lsbMatch_T_31 = _GEN_10; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsLess_T_43; // @[PMP.scala:60:36] assign _res_hit_msbsLess_T_43 = _GEN_10; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsEqual_T_50; // @[PMP.scala:60:36] assign _res_hit_msbsEqual_T_50 = _GEN_10; // @[PMP.scala:60:36] wire [31:0] _res_hit_lsbsLess_T_51; // @[PMP.scala:60:36] assign _res_hit_lsbsLess_T_51 = _GEN_10; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesUpperBound_T_52; // @[PMP.scala:60:36] assign _res_aligned_straddlesUpperBound_T_52 = _GEN_10; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesUpperBound_T_59; // @[PMP.scala:60:36] assign _res_aligned_straddlesUpperBound_T_59 = _GEN_10; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsLess_T_26 = ~_res_hit_msbsLess_T_25; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsLess_T_27 = {_res_hit_msbsLess_T_26[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsLess_T_28 = ~_res_hit_msbsLess_T_27; // @[PMP.scala:60:{27,48}] wire [25:0] _res_hit_msbsLess_T_29 = _res_hit_msbsLess_T_28[31:6]; // @[PMP.scala:60:27, :80:52] wire res_hit_msbsLess_4 = _res_hit_msbsLess_T_24 < _res_hit_msbsLess_T_29; // @[PMP.scala:80:{25,39,52}] wire [31:0] _res_hit_msbsEqual_T_30 = ~_res_hit_msbsEqual_T_29; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsEqual_T_31 = {_res_hit_msbsEqual_T_30[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsEqual_T_32 = ~_res_hit_msbsEqual_T_31; // @[PMP.scala:60:{27,48}] wire [25:0] _res_hit_msbsEqual_T_33 = _res_hit_msbsEqual_T_32[31:6]; // @[PMP.scala:60:27, :81:54] wire [25:0] _res_hit_msbsEqual_T_34 = _res_hit_msbsEqual_T_28 ^ _res_hit_msbsEqual_T_33; // @[PMP.scala:81:{27,41,54}] wire res_hit_msbsEqual_4 = _res_hit_msbsEqual_T_34 == 26'h0; // @[PMP.scala:80:52, :81:{41,54,69}, :123:67] wire [5:0] _res_hit_lsbsLess_T_29 = _res_hit_lsbsLess_T_28; // @[PMP.scala:82:{25,42}] wire [31:0] _res_hit_lsbsLess_T_31 = ~_res_hit_lsbsLess_T_30; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_lsbsLess_T_32 = {_res_hit_lsbsLess_T_31[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbsLess_T_33 = ~_res_hit_lsbsLess_T_32; // @[PMP.scala:60:{27,48}] wire [5:0] _res_hit_lsbsLess_T_34 = _res_hit_lsbsLess_T_33[5:0]; // @[PMP.scala:60:27, :82:64] wire res_hit_lsbsLess_4 = _res_hit_lsbsLess_T_29 < _res_hit_lsbsLess_T_34; // @[PMP.scala:82:{42,53,64}] wire _res_hit_T_32 = res_hit_msbsEqual_4 & res_hit_lsbsLess_4; // @[PMP.scala:81:69, :82:53, :83:30] wire _res_hit_T_33 = res_hit_msbsLess_4 \| _res_hit_T_32; // @[PMP.scala:80:39, :83:{16,30}] wire _res_hit_T_34 = ~_res_hit_T_33; // @[PMP.scala:83:16, :88:5] wire [31:0] _res_hit_msbsLess_T_32 = ~_res_hit_msbsLess_T_31; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsLess_T_33 = {_res_hit_msbsLess_T_32[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsLess_T_34 = ~_res_hit_msbsLess_T_33; // @[PMP.scala:60:{27,48}] wire [25:0] _res_hit_msbsLess_T_35 = _res_hit_msbsLess_T_34[31:6]; // @[PMP.scala:60:27, :80:52] wire res_hit_msbsLess_5 = _res_hit_msbsLess_T_30 < _res_hit_msbsLess_T_35; // @[PMP.scala:80:{25,39,52}] wire [31:0] _res_hit_msbsEqual_T_37 = ~_res_hit_msbsEqual_T_36; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsEqual_T_38 = {_res_hit_msbsEqual_T_37[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsEqual_T_39 = ~_res_hit_msbsEqual_T_38; // @[PMP.scala:60:{27,48}] wire [25:0] _res_hit_msbsEqual_T_40 = _res_hit_msbsEqual_T_39[31:6]; // @[PMP.scala:60:27, :81:54] wire [25:0] _res_hit_msbsEqual_T_41 = _res_hit_msbsEqual_T_35 ^ _res_hit_msbsEqual_T_40; // @[PMP.scala:81:{27,41,54}] wire res_hit_msbsEqual_5 = _res_hit_msbsEqual_T_41 == 26'h0; // @[PMP.scala:80:52, :81:{41,54,69}, :123:67] wire [5:0] _res_hit_lsbsLess_T_36 = _res_hit_lsbsLess_T_35; // @[PMP.scala:82:{25,42}] wire [31:0] _res_hit_lsbsLess_T_38 = ~_res_hit_lsbsLess_T_37; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_lsbsLess_T_39 = {_res_hit_lsbsLess_T_38[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbsLess_T_40 = ~_res_hit_lsbsLess_T_39; // @[PMP.scala:60:{27,48}] wire [5:0] _res_hit_lsbsLess_T_41 = _res_hit_lsbsLess_T_40[5:0]; // @[PMP.scala:60:27, :82:64] wire res_hit_lsbsLess_5 = _res_hit_lsbsLess_T_36 < _res_hit_lsbsLess_T_41; // @[PMP.scala:82:{42,53,64}] wire _res_hit_T_35 = res_hit_msbsEqual_5 & res_hit_lsbsLess_5; // @[PMP.scala:81:69, :82:53, :83:30] wire _res_hit_T_36 = res_hit_msbsLess_5 \| _res_hit_T_35; // @[PMP.scala:80:39, :83:{16,30}] wire _res_hit_T_37 = _res_hit_T_34 & _res_hit_T_36; // @[PMP.scala:83:16, :88:5, :94:48] wire _res_hit_T_38 = _res_hit_T_28 & _res_hit_T_37; // @[PMP.scala:46:26, :94:48, :132:61] wire res_hit_2 = _res_hit_T_26 ? _res_hit_T_27 : _res_hit_T_38; // @[PMP.scala:45:20, :71:16, :132:{8,61}] wire _res_ignore_T_2 = ~io_pmp_5_cfg_l_0; // @[PMP.scala:143:7, :164:29] wire res_ignore_2 = default_0 & _res_ignore_T_2; // @[PMP.scala:156:56, :164:{26,29}] wire [31:0] _res_aligned_straddlesLowerBound_T_36 = ~_res_aligned_straddlesLowerBound_T_35; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesLowerBound_T_37 = {_res_aligned_straddlesLowerBound_T_36[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesLowerBound_T_38 = ~_res_aligned_straddlesLowerBound_T_37; // @[PMP.scala:60:{27,48}] wire [25:0] _res_aligned_straddlesLowerBound_T_39 = _res_aligned_straddlesLowerBound_T_38[31:6]; // @[PMP.scala:60:27, :123:67] wire [25:0] _res_aligned_straddlesLowerBound_T_40 = _res_aligned_straddlesLowerBound_T_34 ^ _res_aligned_straddlesLowerBound_T_39; // @[PMP.scala:123:{35,49,67}] wire _res_aligned_straddlesLowerBound_T_41 = _res_aligned_straddlesLowerBound_T_40 == 26'h0; // @[PMP.scala:80:52, :81:54, :123:{49,67,82}] wire [31:0] _res_aligned_straddlesLowerBound_T_43 = ~_res_aligned_straddlesLowerBound_T_42; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesLowerBound_T_44 = {_res_aligned_straddlesLowerBound_T_43[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesLowerBound_T_45 = ~_res_aligned_straddlesLowerBound_T_44; // @[PMP.scala:60:{27,48}] wire [5:0] _res_aligned_straddlesLowerBound_T_46 = _res_aligned_straddlesLowerBound_T_45[5:0]; // @[PMP.scala:60:27, :123:108] wire [5:0] _res_aligned_straddlesLowerBound_T_48 = ~_res_aligned_straddlesLowerBound_T_47; // @[PMP.scala:123:{127,129}] wire [5:0] _res_aligned_straddlesLowerBound_T_49 = _res_aligned_straddlesLowerBound_T_46 & _res_aligned_straddlesLowerBound_T_48; // @[PMP.scala:123:{108,125,127}] wire _res_aligned_straddlesLowerBound_T_50 = \|_res_aligned_straddlesLowerBound_T_49; // @[PMP.scala:123:{125,147}] wire res_aligned_straddlesLowerBound_2 = _res_aligned_straddlesLowerBound_T_41 & _res_aligned_straddlesLowerBound_T_50; // @[PMP.scala:123:{82,90,147}] wire [31:0] _res_aligned_straddlesUpperBound_T_36 = ~_res_aligned_straddlesUpperBound_T_35; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesUpperBound_T_37 = {_res_aligned_straddlesUpperBound_T_36[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesUpperBound_T_38 = ~_res_aligned_straddlesUpperBound_T_37; // @[PMP.scala:60:{27,48}] wire [25:0] _res_aligned_straddlesUpperBound_T_39 = _res_aligned_straddlesUpperBound_T_38[31:6]; // @[PMP.scala:60:27, :124:62] wire [25:0] _res_aligned_straddlesUpperBound_T_40 = _res_aligned_straddlesUpperBound_T_34 ^ _res_aligned_straddlesUpperBound_T_39; // @[PMP.scala:124:{35,49,62}] wire _res_aligned_straddlesUpperBound_T_41 = _res_aligned_straddlesUpperBound_T_40 == 26'h0; // @[PMP.scala:80:52, :81:54, :123:67, :124:{49,77}] wire [31:0] _res_aligned_straddlesUpperBound_T_43 = ~_res_aligned_straddlesUpperBound_T_42; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesUpperBound_T_44 = {_res_aligned_straddlesUpperBound_T_43[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesUpperBound_T_45 = ~_res_aligned_straddlesUpperBound_T_44; // @[PMP.scala:60:{27,48}] wire [5:0] _res_aligned_straddlesUpperBound_T_46 = _res_aligned_straddlesUpperBound_T_45[5:0]; // @[PMP.scala:60:27, :124:98] wire [5:0] _res_aligned_straddlesUpperBound_T_48 = _res_aligned_straddlesUpperBound_T_47; // @[PMP.scala:124:{119,136}] wire [5:0] _res_aligned_straddlesUpperBound_T_49 = _res_aligned_straddlesUpperBound_T_46 & _res_aligned_straddlesUpperBound_T_48; // @[PMP.scala:124:{98,115,136}] wire _res_aligned_straddlesUpperBound_T_50 = \|_res_aligned_straddlesUpperBound_T_49; // @[PMP.scala:124:{115,148}] wire res_aligned_straddlesUpperBound_2 = _res_aligned_straddlesUpperBound_T_41 & _res_aligned_straddlesUpperBound_T_50; // @[PMP.scala:124:{77,85,148}] wire _res_aligned_rangeAligned_T_2 = res_aligned_straddlesLowerBound_2 \| res_aligned_straddlesUpperBound_2; // @[PMP.scala:123:90, :124:85, :125:46] wire res_aligned_rangeAligned_2 = ~_res_aligned_rangeAligned_T_2; // @[PMP.scala:125:{24,46}] wire [5:0] _res_aligned_pow2Aligned_T_7 = ~_res_aligned_pow2Aligned_T_6; // @[PMP.scala:126:{34,39}] wire res_aligned_2 = _res_aligned_T_2 \| res_aligned_rangeAligned_2; // @[PMP.scala:45:20, :125:24, :127:8] wire _res_T_90 = io_pmp_5_cfg_a_0 == 2'h0; // @[PMP.scala:143:7, :168:32] wire _GEN_11 = io_pmp_5_cfg_a_0 == 2'h1; // @[PMP.scala:143:7, :168:32] wire _res_T_91; // @[PMP.scala:168:32] assign _res_T_91 = _GEN_11; // @[PMP.scala:168:32] wire _res_T_110; // @[PMP.scala:177:61] assign _res_T_110 = _GEN_11; // @[PMP.scala:168:32, :177:61] wire _res_T_114; // @[PMP.scala:178:63] assign _res_T_114 = _GEN_11; // @[PMP.scala:168:32, :178:63] wire _GEN_12 = io_pmp_5_cfg_a_0 == 2'h2; // @[PMP.scala:143:7, :168:32] wire _res_T_92; // @[PMP.scala:168:32] assign _res_T_92 = _GEN_12; // @[PMP.scala:168:32] wire _res_T_119; // @[PMP.scala:177:61] assign _res_T_119 = _GEN_12; // @[PMP.scala:168:32, :177:61] wire _res_T_123; // @[PMP.scala:178:63] assign _res_T_123 = _GEN_12; // @[PMP.scala:168:32, :178:63] wire _res_T_93 = &io_pmp_5_cfg_a_0; // @[PMP.scala:143:7, :168:32] wire [1:0] _GEN_13 = {io_pmp_5_cfg_x_0, io_pmp_5_cfg_w_0}; // @[PMP.scala:143:7, :174:26] wire [1:0] res_hi_12; // @[PMP.scala:174:26] assign res_hi_12 = _GEN_13; // @[PMP.scala:174:26] wire [1:0] res_hi_13; // @[PMP.scala:174:26] assign res_hi_13 = _GEN_13; // @[PMP.scala:174:26] wire [1:0] res_hi_14; // @[PMP.scala:174:26] assign res_hi_14 = _GEN_13; // @[PMP.scala:174:26] wire [1:0] res_hi_15; // @[PMP.scala:174:26] assign res_hi_15 = _GEN_13; // @[PMP.scala:174:26] wire [1:0] res_hi_16; // @[PMP.scala:174:26] assign res_hi_16 = _GEN_13; // @[PMP.scala:174:26] wire [1:0] res_hi_17; // @[PMP.scala:174:26] assign res_hi_17 = _GEN_13; // @[PMP.scala:174:26] wire [2:0] _res_T_95 = {res_hi_12, io_pmp_5_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_96 = _res_T_95 == 3'h0; // @[PMP.scala:143:7, :146:14, :174:{26,60}] wire [2:0] _res_T_97 = {res_hi_13, io_pmp_5_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_98 = _res_T_97 == 3'h1; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_99 = {res_hi_14, io_pmp_5_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_100 = _res_T_99 == 3'h3; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_101 = {res_hi_15, io_pmp_5_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_102 = _res_T_101 == 3'h4; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_103 = {res_hi_16, io_pmp_5_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_104 = _res_T_103 == 3'h5; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_105 = {res_hi_17, io_pmp_5_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_106 = &_res_T_105; // @[PMP.scala:174:{26,60}] wire _res_T_107 = ~res_ignore_2; // @[PMP.scala:164:26, :177:22] wire _res_T_108 = _res_T_107 & res_hit_2; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_109 = _res_T_108 & res_aligned_2; // @[PMP.scala:127:8, :177:{30,37}] wire _res_T_111 = _res_T_109 & _res_T_110; // @[PMP.scala:177:{37,48,61}] wire _GEN_14 = io_pmp_5_cfg_l_0 & res_hit_2; // @[PMP.scala:132:8, :143:7, :178:32] wire _res_T_112; // @[PMP.scala:178:32] assign _res_T_112 = _GEN_14; // @[PMP.scala:178:32] wire _res_T_121; // @[PMP.scala:178:32] assign _res_T_121 = _GEN_14; // @[PMP.scala:178:32] wire _res_T_130; // @[PMP.scala:178:32] assign _res_T_130 = _GEN_14; // @[PMP.scala:178:32] wire _res_T_113 = _res_T_112 & res_aligned_2; // @[PMP.scala:127:8, :178:{32,39}] wire _res_T_115 = _res_T_113 & _res_T_114; // @[PMP.scala:178:{39,50,63}] wire _res_T_116 = ~res_ignore_2; // @[PMP.scala:164:26, :177:22] wire _res_T_117 = _res_T_116 & res_hit_2; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_118 = _res_T_117 & res_aligned_2; // @[PMP.scala:127:8, :177:{30,37}] wire _res_T_120 = _res_T_118 & _res_T_119; // @[PMP.scala:177:{37,48,61}] wire _res_T_122 = _res_T_121 & res_aligned_2; // @[PMP.scala:127:8, :178:{32,39}] wire _res_T_124 = _res_T_122 & _res_T_123; // @[PMP.scala:178:{39,50,63}] wire _res_T_125 = ~res_ignore_2; // @[PMP.scala:164:26, :177:22] wire _res_T_126 = _res_T_125 & res_hit_2; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_127 = _res_T_126 & res_aligned_2; // @[PMP.scala:127:8, :177:{30,37}] wire _res_T_128 = &io_pmp_5_cfg_a_0; // @[PMP.scala:143:7, :168:32, :177:61] wire _res_T_129 = _res_T_127 & _res_T_128; // @[PMP.scala:177:{37,48,61}] wire _res_T_131 = _res_T_130 & res_aligned_2; // @[PMP.scala:127:8, :178:{32,39}] wire _res_T_132 = &io_pmp_5_cfg_a_0; // @[PMP.scala:143:7, :168:32, :178:63] wire _res_T_133 = _res_T_131 & _res_T_132; // @[PMP.scala:178:{39,50,63}] wire _res_cur_cfg_x_T_5; // @[PMP.scala:184:26] wire _res_cur_cfg_w_T_5; // @[PMP.scala:183:26] wire _res_cur_cfg_r_T_5; // @[PMP.scala:182:26] wire res_cur_2_cfg_x; // @[PMP.scala:181:23] wire res_cur_2_cfg_w; // @[PMP.scala:181:23] wire res_cur_2_cfg_r; // @[PMP.scala:181:23] wire _res_cur_cfg_r_T_4 = io_pmp_5_cfg_r_0 \| res_ignore_2; // @[PMP.scala:143:7, :164:26, :182:40] assign _res_cur_cfg_r_T_5 = res_aligned_2 & _res_cur_cfg_r_T_4; // @[PMP.scala:127:8, :182:{26,40}] assign res_cur_2_cfg_r = _res_cur_cfg_r_T_5; // @[PMP.scala:181:23, :182:26] wire _res_cur_cfg_w_T_4 = io_pmp_5_cfg_w_0 \| res_ignore_2; // @[PMP.scala:143:7, :164:26, :183:40] assign _res_cur_cfg_w_T_5 = res_aligned_2 & _res_cur_cfg_w_T_4; // @[PMP.scala:127:8, :183:{26,40}] assign res_cur_2_cfg_w = _res_cur_cfg_w_T_5; // @[PMP.scala:181:23, :183:26] wire _res_cur_cfg_x_T_4 = io_pmp_5_cfg_x_0 \| res_ignore_2; // @[PMP.scala:143:7, :164:26, :184:40] assign _res_cur_cfg_x_T_5 = res_aligned_2 & _res_cur_cfg_x_T_4; // @[PMP.scala:127:8, :184:{26,40}] assign res_cur_2_cfg_x = _res_cur_cfg_x_T_5; // @[PMP.scala:181:23, :184:26] wire _res_T_134_cfg_l = res_hit_2 ? res_cur_2_cfg_l : _res_T_89_cfg_l; // @[PMP.scala:132:8, :181:23, :185:8] wire [1:0] _res_T_134_cfg_a = res_hit_2 ? res_cur_2_cfg_a : _res_T_89_cfg_a; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_T_134_cfg_x = res_hit_2 ? res_cur_2_cfg_x : _res_T_89_cfg_x; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_T_134_cfg_w = res_hit_2 ? res_cur_2_cfg_w : _res_T_89_cfg_w; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_T_134_cfg_r = res_hit_2 ? res_cur_2_cfg_r : _res_T_89_cfg_r; // @[PMP.scala:132:8, :181:23, :185:8] wire [29:0] _res_T_134_addr = res_hit_2 ? res_cur_2_addr : _res_T_89_addr; // @[PMP.scala:132:8, :181:23, :185:8] wire [31:0] _res_T_134_mask = res_hit_2 ? res_cur_2_mask : _res_T_89_mask; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_hit_T_39 = io_pmp_4_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7] wire _res_aligned_T_3 = io_pmp_4_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7] wire [25:0] _res_hit_msbMatch_T_36 = io_pmp_4_mask_0[31:6]; // @[PMP.scala:68:26, :69:72, :143:7] wire [5:0] _res_aligned_pow2Aligned_T_9 = io_pmp_4_mask_0[5:0]; // @[PMP.scala:68:26, :126:39, :143:7] wire [31:0] _res_hit_msbMatch_T_32 = ~_res_hit_msbMatch_T_31; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbMatch_T_33 = {_res_hit_msbMatch_T_32[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbMatch_T_34 = ~_res_hit_msbMatch_T_33; // @[PMP.scala:60:{27,48}] wire [25:0] _res_hit_msbMatch_T_35 = _res_hit_msbMatch_T_34[31:6]; // @[PMP.scala:60:27, :69:53] wire [25:0] _res_hit_msbMatch_T_37 = _res_hit_msbMatch_T_30 ^ _res_hit_msbMatch_T_35; // @[PMP.scala:63:47, :69:{29,53}] wire [25:0] _res_hit_msbMatch_T_38 = ~_res_hit_msbMatch_T_36; // @[PMP.scala:63:54, :69:72] wire [25:0] _res_hit_msbMatch_T_39 = _res_hit_msbMatch_T_37 & _res_hit_msbMatch_T_38; // @[PMP.scala:63:{47,52,54}] wire res_hit_msbMatch_3 = _res_hit_msbMatch_T_39 == 26'h0; // @[PMP.scala:63:{52,58}, :80:52, :81:54, :123:67] wire [31:0] _res_hit_lsbMatch_T_32 = ~_res_hit_lsbMatch_T_31; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_lsbMatch_T_33 = {_res_hit_lsbMatch_T_32[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbMatch_T_34 = ~_res_hit_lsbMatch_T_33; // @[PMP.scala:60:{27,48}] wire [5:0] _res_hit_lsbMatch_T_35 = _res_hit_lsbMatch_T_34[5:0]; // @[PMP.scala:60:27, :70:55] wire [5:0] _res_hit_lsbMatch_T_36 = res_hit_lsbMask_3[5:0]; // @[PMP.scala:68:26, :70:80] wire [5:0] _res_hit_lsbMatch_T_37 = _res_hit_lsbMatch_T_30 ^ _res_hit_lsbMatch_T_35; // @[PMP.scala:63:47, :70:{28,55}] wire [5:0] _res_hit_lsbMatch_T_38 = ~_res_hit_lsbMatch_T_36; // @[PMP.scala:63:54, :70:80] wire [5:0] _res_hit_lsbMatch_T_39 = _res_hit_lsbMatch_T_37 & _res_hit_lsbMatch_T_38; // @[PMP.scala:63:{47,52,54}] wire res_hit_lsbMatch_3 = _res_hit_lsbMatch_T_39 == 6'h0; // @[PMP.scala:63:{52,58}] wire _res_hit_T_40 = res_hit_msbMatch_3 & res_hit_lsbMatch_3; // @[PMP.scala:63:58, :71:16] wire _res_hit_T_41 = io_pmp_4_cfg_a_0[0]; // @[PMP.scala:46:26, :143:7] wire [31:0] _GEN_15 = {io_pmp_3_addr_0, 2'h0}; // @[PMP.scala:60:36, :143:7] wire [31:0] _res_hit_msbsLess_T_37; // @[PMP.scala:60:36] assign _res_hit_msbsLess_T_37 = _GEN_15; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsEqual_T_43; // @[PMP.scala:60:36] assign _res_hit_msbsEqual_T_43 = _GEN_15; // @[PMP.scala:60:36] wire [31:0] _res_hit_lsbsLess_T_44; // @[PMP.scala:60:36] assign _res_hit_lsbsLess_T_44 = _GEN_15; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesLowerBound_T_52; // @[PMP.scala:60:36] assign _res_aligned_straddlesLowerBound_T_52 = _GEN_15; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesLowerBound_T_59; // @[PMP.scala:60:36] assign _res_aligned_straddlesLowerBound_T_59 = _GEN_15; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbMatch_T_41; // @[PMP.scala:60:36] assign _res_hit_msbMatch_T_41 = _GEN_15; // @[PMP.scala:60:36] wire [31:0] _res_hit_lsbMatch_T_41; // @[PMP.scala:60:36] assign _res_hit_lsbMatch_T_41 = _GEN_15; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsLess_T_55; // @[PMP.scala:60:36] assign _res_hit_msbsLess_T_55 = _GEN_15; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsEqual_T_64; // @[PMP.scala:60:36] assign _res_hit_msbsEqual_T_64 = _GEN_15; // @[PMP.scala:60:36] wire [31:0] _res_hit_lsbsLess_T_65; // @[PMP.scala:60:36] assign _res_hit_lsbsLess_T_65 = _GEN_15; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesUpperBound_T_69; // @[PMP.scala:60:36] assign _res_aligned_straddlesUpperBound_T_69 = _GEN_15; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesUpperBound_T_76; // @[PMP.scala:60:36] assign _res_aligned_straddlesUpperBound_T_76 = _GEN_15; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsLess_T_38 = ~_res_hit_msbsLess_T_37; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsLess_T_39 = {_res_hit_msbsLess_T_38[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsLess_T_40 = ~_res_hit_msbsLess_T_39; // @[PMP.scala:60:{27,48}] wire [25:0] _res_hit_msbsLess_T_41 = _res_hit_msbsLess_T_40[31:6]; // @[PMP.scala:60:27, :80:52] wire res_hit_msbsLess_6 = _res_hit_msbsLess_T_36 < _res_hit_msbsLess_T_41; // @[PMP.scala:80:{25,39,52}] wire [31:0] _res_hit_msbsEqual_T_44 = ~_res_hit_msbsEqual_T_43; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsEqual_T_45 = {_res_hit_msbsEqual_T_44[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsEqual_T_46 = ~_res_hit_msbsEqual_T_45; // @[PMP.scala:60:{27,48}] wire [25:0] _res_hit_msbsEqual_T_47 = _res_hit_msbsEqual_T_46[31:6]; // @[PMP.scala:60:27, :81:54] wire [25:0] _res_hit_msbsEqual_T_48 = _res_hit_msbsEqual_T_42 ^ _res_hit_msbsEqual_T_47; // @[PMP.scala:81:{27,41,54}] wire res_hit_msbsEqual_6 = _res_hit_msbsEqual_T_48 == 26'h0; // @[PMP.scala:80:52, :81:{41,54,69}, :123:67] wire [5:0] _res_hit_lsbsLess_T_43 = _res_hit_lsbsLess_T_42; // @[PMP.scala:82:{25,42}] wire [31:0] _res_hit_lsbsLess_T_45 = ~_res_hit_lsbsLess_T_44; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_lsbsLess_T_46 = {_res_hit_lsbsLess_T_45[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbsLess_T_47 = ~_res_hit_lsbsLess_T_46; // @[PMP.scala:60:{27,48}] wire [5:0] _res_hit_lsbsLess_T_48 = _res_hit_lsbsLess_T_47[5:0]; // @[PMP.scala:60:27, :82:64] wire res_hit_lsbsLess_6 = _res_hit_lsbsLess_T_43 < _res_hit_lsbsLess_T_48; // @[PMP.scala:82:{42,53,64}] wire _res_hit_T_45 = res_hit_msbsEqual_6 & res_hit_lsbsLess_6; // @[PMP.scala:81:69, :82:53, :83:30] wire _res_hit_T_46 = res_hit_msbsLess_6 \| _res_hit_T_45; // @[PMP.scala:80:39, :83:{16,30}] wire _res_hit_T_47 = ~_res_hit_T_46; // @[PMP.scala:83:16, :88:5] wire [31:0] _res_hit_msbsLess_T_44 = ~_res_hit_msbsLess_T_43; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsLess_T_45 = {_res_hit_msbsLess_T_44[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsLess_T_46 = ~_res_hit_msbsLess_T_45; // @[PMP.scala:60:{27,48}] wire [25:0] _res_hit_msbsLess_T_47 = _res_hit_msbsLess_T_46[31:6]; // @[PMP.scala:60:27, :80:52] wire res_hit_msbsLess_7 = _res_hit_msbsLess_T_42 < _res_hit_msbsLess_T_47; // @[PMP.scala:80:{25,39,52}] wire [31:0] _res_hit_msbsEqual_T_51 = ~_res_hit_msbsEqual_T_50; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsEqual_T_52 = {_res_hit_msbsEqual_T_51[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsEqual_T_53 = ~_res_hit_msbsEqual_T_52; // @[PMP.scala:60:{27,48}] wire [25:0] _res_hit_msbsEqual_T_54 = _res_hit_msbsEqual_T_53[31:6]; // @[PMP.scala:60:27, :81:54] wire [25:0] _res_hit_msbsEqual_T_55 = _res_hit_msbsEqual_T_49 ^ _res_hit_msbsEqual_T_54; // @[PMP.scala:81:{27,41,54}] wire res_hit_msbsEqual_7 = _res_hit_msbsEqual_T_55 == 26'h0; // @[PMP.scala:80:52, :81:{41,54,69}, :123:67] wire [5:0] _res_hit_lsbsLess_T_50 = _res_hit_lsbsLess_T_49; // @[PMP.scala:82:{25,42}] wire [31:0] _res_hit_lsbsLess_T_52 = ~_res_hit_lsbsLess_T_51; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_lsbsLess_T_53 = {_res_hit_lsbsLess_T_52[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbsLess_T_54 = ~_res_hit_lsbsLess_T_53; // @[PMP.scala:60:{27,48}] wire [5:0] _res_hit_lsbsLess_T_55 = _res_hit_lsbsLess_T_54[5:0]; // @[PMP.scala:60:27, :82:64] wire res_hit_lsbsLess_7 = _res_hit_lsbsLess_T_50 < _res_hit_lsbsLess_T_55; // @[PMP.scala:82:{42,53,64}] wire _res_hit_T_48 = res_hit_msbsEqual_7 & res_hit_lsbsLess_7; // @[PMP.scala:81:69, :82:53, :83:30] wire _res_hit_T_49 = res_hit_msbsLess_7 \| _res_hit_T_48; // @[PMP.scala:80:39, :83:{16,30}] wire _res_hit_T_50 = _res_hit_T_47 & _res_hit_T_49; // @[PMP.scala:83:16, :88:5, :94:48] wire _res_hit_T_51 = _res_hit_T_41 & _res_hit_T_50; // @[PMP.scala:46:26, :94:48, :132:61] wire res_hit_3 = _res_hit_T_39 ? _res_hit_T_40 : _res_hit_T_51; // @[PMP.scala:45:20, :71:16, :132:{8,61}] wire _res_ignore_T_3 = ~io_pmp_4_cfg_l_0; // @[PMP.scala:143:7, :164:29] wire res_ignore_3 = default_0 & _res_ignore_T_3; // @[PMP.scala:156:56, :164:{26,29}] wire [31:0] _res_aligned_straddlesLowerBound_T_53 = ~_res_aligned_straddlesLowerBound_T_52; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesLowerBound_T_54 = {_res_aligned_straddlesLowerBound_T_53[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesLowerBound_T_55 = ~_res_aligned_straddlesLowerBound_T_54; // @[PMP.scala:60:{27,48}] wire [25:0] _res_aligned_straddlesLowerBound_T_56 = _res_aligned_straddlesLowerBound_T_55[31:6]; // @[PMP.scala:60:27, :123:67] wire [25:0] _res_aligned_straddlesLowerBound_T_57 = _res_aligned_straddlesLowerBound_T_51 ^ _res_aligned_straddlesLowerBound_T_56; // @[PMP.scala:123:{35,49,67}] wire _res_aligned_straddlesLowerBound_T_58 = _res_aligned_straddlesLowerBound_T_57 == 26'h0; // @[PMP.scala:80:52, :81:54, :123:{49,67,82}] wire [31:0] _res_aligned_straddlesLowerBound_T_60 = ~_res_aligned_straddlesLowerBound_T_59; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesLowerBound_T_61 = {_res_aligned_straddlesLowerBound_T_60[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesLowerBound_T_62 = ~_res_aligned_straddlesLowerBound_T_61; // @[PMP.scala:60:{27,48}] wire [5:0] _res_aligned_straddlesLowerBound_T_63 = _res_aligned_straddlesLowerBound_T_62[5:0]; // @[PMP.scala:60:27, :123:108] wire [5:0] _res_aligned_straddlesLowerBound_T_65 = ~_res_aligned_straddlesLowerBound_T_64; // @[PMP.scala:123:{127,129}] wire [5:0] _res_aligned_straddlesLowerBound_T_66 = _res_aligned_straddlesLowerBound_T_63 & _res_aligned_straddlesLowerBound_T_65; // @[PMP.scala:123:{108,125,127}] wire _res_aligned_straddlesLowerBound_T_67 = \|_res_aligned_straddlesLowerBound_T_66; // @[PMP.scala:123:{125,147}] wire res_aligned_straddlesLowerBound_3 = _res_aligned_straddlesLowerBound_T_58 & _res_aligned_straddlesLowerBound_T_67; // @[PMP.scala:123:{82,90,147}] wire [31:0] _res_aligned_straddlesUpperBound_T_53 = ~_res_aligned_straddlesUpperBound_T_52; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesUpperBound_T_54 = {_res_aligned_straddlesUpperBound_T_53[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesUpperBound_T_55 = ~_res_aligned_straddlesUpperBound_T_54; // @[PMP.scala:60:{27,48}] wire [25:0] _res_aligned_straddlesUpperBound_T_56 = _res_aligned_straddlesUpperBound_T_55[31:6]; // @[PMP.scala:60:27, :124:62] wire [25:0] _res_aligned_straddlesUpperBound_T_57 = _res_aligned_straddlesUpperBound_T_51 ^ _res_aligned_straddlesUpperBound_T_56; // @[PMP.scala:124:{35,49,62}] wire _res_aligned_straddlesUpperBound_T_58 = _res_aligned_straddlesUpperBound_T_57 == 26'h0; // @[PMP.scala:80:52, :81:54, :123:67, :124:{49,77}] wire [31:0] _res_aligned_straddlesUpperBound_T_60 = ~_res_aligned_straddlesUpperBound_T_59; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesUpperBound_T_61 = {_res_aligned_straddlesUpperBound_T_60[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesUpperBound_T_62 = ~_res_aligned_straddlesUpperBound_T_61; // @[PMP.scala:60:{27,48}] wire [5:0] _res_aligned_straddlesUpperBound_T_63 = _res_aligned_straddlesUpperBound_T_62[5:0]; // @[PMP.scala:60:27, :124:98] wire [5:0] _res_aligned_straddlesUpperBound_T_65 = _res_aligned_straddlesUpperBound_T_64; // @[PMP.scala:124:{119,136}] wire [5:0] _res_aligned_straddlesUpperBound_T_66 = _res_aligned_straddlesUpperBound_T_63 & _res_aligned_straddlesUpperBound_T_65; // @[PMP.scala:124:{98,115,136}] wire _res_aligned_straddlesUpperBound_T_67 = \|_res_aligned_straddlesUpperBound_T_66; // @[PMP.scala:124:{115,148}] wire res_aligned_straddlesUpperBound_3 = _res_aligned_straddlesUpperBound_T_58 & _res_aligned_straddlesUpperBound_T_67; // @[PMP.scala:124:{77,85,148}] wire _res_aligned_rangeAligned_T_3 = res_aligned_straddlesLowerBound_3 \| res_aligned_straddlesUpperBound_3; // @[PMP.scala:123:90, :124:85, :125:46] wire res_aligned_rangeAligned_3 = ~_res_aligned_rangeAligned_T_3; // @[PMP.scala:125:{24,46}] wire [5:0] _res_aligned_pow2Aligned_T_10 = ~_res_aligned_pow2Aligned_T_9; // @[PMP.scala:126:{34,39}] wire res_aligned_3 = _res_aligned_T_3 \| res_aligned_rangeAligned_3; // @[PMP.scala:45:20, :125:24, :127:8] wire _res_T_135 = io_pmp_4_cfg_a_0 == 2'h0; // @[PMP.scala:143:7, :168:32] wire _GEN_16 = io_pmp_4_cfg_a_0 == 2'h1; // @[PMP.scala:143:7, :168:32] wire _res_T_136; // @[PMP.scala:168:32] assign _res_T_136 = _GEN_16; // @[PMP.scala:168:32] wire _res_T_155; // @[PMP.scala:177:61] assign _res_T_155 = _GEN_16; // @[PMP.scala:168:32, :177:61] wire _res_T_159; // @[PMP.scala:178:63] assign _res_T_159 = _GEN_16; // @[PMP.scala:168:32, :178:63] wire _GEN_17 = io_pmp_4_cfg_a_0 == 2'h2; // @[PMP.scala:143:7, :168:32] wire _res_T_137; // @[PMP.scala:168:32] assign _res_T_137 = _GEN_17; // @[PMP.scala:168:32] wire _res_T_164; // @[PMP.scala:177:61] assign _res_T_164 = _GEN_17; // @[PMP.scala:168:32, :177:61] wire _res_T_168; // @[PMP.scala:178:63] assign _res_T_168 = _GEN_17; // @[PMP.scala:168:32, :178:63] wire _res_T_138 = &io_pmp_4_cfg_a_0; // @[PMP.scala:143:7, :168:32] wire [1:0] _GEN_18 = {io_pmp_4_cfg_x_0, io_pmp_4_cfg_w_0}; // @[PMP.scala:143:7, :174:26] wire [1:0] res_hi_18; // @[PMP.scala:174:26] assign res_hi_18 = _GEN_18; // @[PMP.scala:174:26] wire [1:0] res_hi_19; // @[PMP.scala:174:26] assign res_hi_19 = _GEN_18; // @[PMP.scala:174:26] wire [1:0] res_hi_20; // @[PMP.scala:174:26] assign res_hi_20 = _GEN_18; // @[PMP.scala:174:26] wire [1:0] res_hi_21; // @[PMP.scala:174:26] assign res_hi_21 = _GEN_18; // @[PMP.scala:174:26] wire [1:0] res_hi_22; // @[PMP.scala:174:26] assign res_hi_22 = _GEN_18; // @[PMP.scala:174:26] wire [1:0] res_hi_23; // @[PMP.scala:174:26] assign res_hi_23 = _GEN_18; // @[PMP.scala:174:26] wire [2:0] _res_T_140 = {res_hi_18, io_pmp_4_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_141 = _res_T_140 == 3'h0; // @[PMP.scala:143:7, :146:14, :174:{26,60}] wire [2:0] _res_T_142 = {res_hi_19, io_pmp_4_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_143 = _res_T_142 == 3'h1; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_144 = {res_hi_20, io_pmp_4_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_145 = _res_T_144 == 3'h3; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_146 = {res_hi_21, io_pmp_4_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_147 = _res_T_146 == 3'h4; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_148 = {res_hi_22, io_pmp_4_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_149 = _res_T_148 == 3'h5; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_150 = {res_hi_23, io_pmp_4_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_151 = &_res_T_150; // @[PMP.scala:174:{26,60}] wire _res_T_152 = ~res_ignore_3; // @[PMP.scala:164:26, :177:22] wire _res_T_153 = _res_T_152 & res_hit_3; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_154 = _res_T_153 & res_aligned_3; // @[PMP.scala:127:8, :177:{30,37}] wire _res_T_156 = _res_T_154 & _res_T_155; // @[PMP.scala:177:{37,48,61}] wire _GEN_19 = io_pmp_4_cfg_l_0 & res_hit_3; // @[PMP.scala:132:8, :143:7, :178:32] wire _res_T_157; // @[PMP.scala:178:32] assign _res_T_157 = _GEN_19; // @[PMP.scala:178:32] wire _res_T_166; // @[PMP.scala:178:32] assign _res_T_166 = _GEN_19; // @[PMP.scala:178:32] wire _res_T_175; // @[PMP.scala:178:32] assign _res_T_175 = _GEN_19; // @[PMP.scala:178:32] wire _res_T_158 = _res_T_157 & res_aligned_3; // @[PMP.scala:127:8, :178:{32,39}] wire _res_T_160 = _res_T_158 & _res_T_159; // @[PMP.scala:178:{39,50,63}] wire _res_T_161 = ~res_ignore_3; // @[PMP.scala:164:26, :177:22] wire _res_T_162 = _res_T_161 & res_hit_3; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_163 = _res_T_162 & res_aligned_3; // @[PMP.scala:127:8, :177:{30,37}] wire _res_T_165 = _res_T_163 & _res_T_164; // @[PMP.scala:177:{37,48,61}] wire _res_T_167 = _res_T_166 & res_aligned_3; // @[PMP.scala:127:8, :178:{32,39}] wire _res_T_169 = _res_T_167 & _res_T_168; // @[PMP.scala:178:{39,50,63}] wire _res_T_170 = ~res_ignore_3; // @[PMP.scala:164:26, :177:22] wire _res_T_171 = _res_T_170 & res_hit_3; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_172 = _res_T_171 & res_aligned_3; // @[PMP.scala:127:8, :177:{30,37}] wire _res_T_173 = &io_pmp_4_cfg_a_0; // @[PMP.scala:143:7, :168:32, :177:61] wire _res_T_174 = _res_T_172 & _res_T_173; // @[PMP.scala:177:{37,48,61}] wire _res_T_176 = _res_T_175 & res_aligned_3; // @[PMP.scala:127:8, :178:{32,39}] wire _res_T_177 = &io_pmp_4_cfg_a_0; // @[PMP.scala:143:7, :168:32, :178:63] wire _res_T_178 = _res_T_176 & _res_T_177; // @[PMP.scala:178:{39,50,63}] wire _res_cur_cfg_x_T_7; // @[PMP.scala:184:26] wire _res_cur_cfg_w_T_7; // @[PMP.scala:183:26] wire _res_cur_cfg_r_T_7; // @[PMP.scala:182:26] wire res_cur_3_cfg_x; // @[PMP.scala:181:23] wire res_cur_3_cfg_w; // @[PMP.scala:181:23] wire res_cur_3_cfg_r; // @[PMP.scala:181:23] wire _res_cur_cfg_r_T_6 = io_pmp_4_cfg_r_0 \| res_ignore_3; // @[PMP.scala:143:7, :164:26, :182:40] assign _res_cur_cfg_r_T_7 = res_aligned_3 & _res_cur_cfg_r_T_6; // @[PMP.scala:127:8, :182:{26,40}] assign res_cur_3_cfg_r = _res_cur_cfg_r_T_7; // @[PMP.scala:181:23, :182:26] wire _res_cur_cfg_w_T_6 = io_pmp_4_cfg_w_0 \| res_ignore_3; // @[PMP.scala:143:7, :164:26, :183:40] assign _res_cur_cfg_w_T_7 = res_aligned_3 & _res_cur_cfg_w_T_6; // @[PMP.scala:127:8, :183:{26,40}] assign res_cur_3_cfg_w = _res_cur_cfg_w_T_7; // @[PMP.scala:181:23, :183:26] wire _res_cur_cfg_x_T_6 = io_pmp_4_cfg_x_0 \| res_ignore_3; // @[PMP.scala:143:7, :164:26, :184:40] assign _res_cur_cfg_x_T_7 = res_aligned_3 & _res_cur_cfg_x_T_6; // @[PMP.scala:127:8, :184:{26,40}] assign res_cur_3_cfg_x = _res_cur_cfg_x_T_7; // @[PMP.scala:181:23, :184:26] wire _res_T_179_cfg_l = res_hit_3 ? res_cur_3_cfg_l : _res_T_134_cfg_l; // @[PMP.scala:132:8, :181:23, :185:8] wire [1:0] _res_T_179_cfg_a = res_hit_3 ? res_cur_3_cfg_a : _res_T_134_cfg_a; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_T_179_cfg_x = res_hit_3 ? res_cur_3_cfg_x : _res_T_134_cfg_x; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_T_179_cfg_w = res_hit_3 ? res_cur_3_cfg_w : _res_T_134_cfg_w; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_T_179_cfg_r = res_hit_3 ? res_cur_3_cfg_r : _res_T_134_cfg_r; // @[PMP.scala:132:8, :181:23, :185:8] wire [29:0] _res_T_179_addr = res_hit_3 ? res_cur_3_addr : _res_T_134_addr; // @[PMP.scala:132:8, :181:23, :185:8] wire [31:0] _res_T_179_mask = res_hit_3 ? res_cur_3_mask : _res_T_134_mask; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_hit_T_52 = io_pmp_3_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7] wire _res_aligned_T_4 = io_pmp_3_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7] wire [25:0] _res_hit_msbMatch_T_46 = io_pmp_3_mask_0[31:6]; // @[PMP.scala:68:26, :69:72, :143:7] wire [5:0] _res_aligned_pow2Aligned_T_12 = io_pmp_3_mask_0[5:0]; // @[PMP.scala:68:26, :126:39, :143:7] wire [31:0] _res_hit_msbMatch_T_42 = ~_res_hit_msbMatch_T_41; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbMatch_T_43 = {_res_hit_msbMatch_T_42[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbMatch_T_44 = ~_res_hit_msbMatch_T_43; // @[PMP.scala:60:{27,48}] wire [25:0] _res_hit_msbMatch_T_45 = _res_hit_msbMatch_T_44[31:6]; // @[PMP.scala:60:27, :69:53] wire [25:0] _res_hit_msbMatch_T_47 = _res_hit_msbMatch_T_40 ^ _res_hit_msbMatch_T_45; // @[PMP.scala:63:47, :69:{29,53}] wire [25:0] _res_hit_msbMatch_T_48 = ~_res_hit_msbMatch_T_46; // @[PMP.scala:63:54, :69:72] wire [25:0] _res_hit_msbMatch_T_49 = _res_hit_msbMatch_T_47 & _res_hit_msbMatch_T_48; // @[PMP.scala:63:{47,52,54}] wire res_hit_msbMatch_4 = _res_hit_msbMatch_T_49 == 26'h0; // @[PMP.scala:63:{52,58}, :80:52, :81:54, :123:67] wire [31:0] _res_hit_lsbMatch_T_42 = ~_res_hit_lsbMatch_T_41; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_lsbMatch_T_43 = {_res_hit_lsbMatch_T_42[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbMatch_T_44 = ~_res_hit_lsbMatch_T_43; // @[PMP.scala:60:{27,48}] wire [5:0] _res_hit_lsbMatch_T_45 = _res_hit_lsbMatch_T_44[5:0]; // @[PMP.scala:60:27, :70:55] wire [5:0] _res_hit_lsbMatch_T_46 = res_hit_lsbMask_4[5:0]; // @[PMP.scala:68:26, :70:80] wire [5:0] _res_hit_lsbMatch_T_47 = _res_hit_lsbMatch_T_40 ^ _res_hit_lsbMatch_T_45; // @[PMP.scala:63:47, :70:{28,55}] wire [5:0] _res_hit_lsbMatch_T_48 = ~_res_hit_lsbMatch_T_46; // @[PMP.scala:63:54, :70:80] wire [5:0] _res_hit_lsbMatch_T_49 = _res_hit_lsbMatch_T_47 & _res_hit_lsbMatch_T_48; // @[PMP.scala:63:{47,52,54}] wire res_hit_lsbMatch_4 = _res_hit_lsbMatch_T_49 == 6'h0; // @[PMP.scala:63:{52,58}] wire _res_hit_T_53 = res_hit_msbMatch_4 & res_hit_lsbMatch_4; // @[PMP.scala:63:58, :71:16] wire _res_hit_T_54 = io_pmp_3_cfg_a_0[0]; // @[PMP.scala:46:26, :143:7] wire [31:0] _GEN_20 = {io_pmp_2_addr_0, 2'h0}; // @[PMP.scala:60:36, :143:7] wire [31:0] _res_hit_msbsLess_T_49; // @[PMP.scala:60:36] assign _res_hit_msbsLess_T_49 = _GEN_20; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsEqual_T_57; // @[PMP.scala:60:36] assign _res_hit_msbsEqual_T_57 = _GEN_20; // @[PMP.scala:60:36] wire [31:0] _res_hit_lsbsLess_T_58; // @[PMP.scala:60:36] assign _res_hit_lsbsLess_T_58 = _GEN_20; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesLowerBound_T_69; // @[PMP.scala:60:36] assign _res_aligned_straddlesLowerBound_T_69 = _GEN_20; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesLowerBound_T_76; // @[PMP.scala:60:36] assign _res_aligned_straddlesLowerBound_T_76 = _GEN_20; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbMatch_T_51; // @[PMP.scala:60:36] assign _res_hit_msbMatch_T_51 = _GEN_20; // @[PMP.scala:60:36] wire [31:0] _res_hit_lsbMatch_T_51; // @[PMP.scala:60:36] assign _res_hit_lsbMatch_T_51 = _GEN_20; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsLess_T_67; // @[PMP.scala:60:36] assign _res_hit_msbsLess_T_67 = _GEN_20; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsEqual_T_78; // @[PMP.scala:60:36] assign _res_hit_msbsEqual_T_78 = _GEN_20; // @[PMP.scala:60:36] wire [31:0] _res_hit_lsbsLess_T_79; // @[PMP.scala:60:36] assign _res_hit_lsbsLess_T_79 = _GEN_20; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesUpperBound_T_86; // @[PMP.scala:60:36] assign _res_aligned_straddlesUpperBound_T_86 = _GEN_20; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesUpperBound_T_93; // @[PMP.scala:60:36] assign _res_aligned_straddlesUpperBound_T_93 = _GEN_20; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsLess_T_50 = ~_res_hit_msbsLess_T_49; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsLess_T_51 = {_res_hit_msbsLess_T_50[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsLess_T_52 = ~_res_hit_msbsLess_T_51; // @[PMP.scala:60:{27,48}] wire [25:0] _res_hit_msbsLess_T_53 = _res_hit_msbsLess_T_52[31:6]; // @[PMP.scala:60:27, :80:52] wire res_hit_msbsLess_8 = _res_hit_msbsLess_T_48 < _res_hit_msbsLess_T_53; // @[PMP.scala:80:{25,39,52}] wire [31:0] _res_hit_msbsEqual_T_58 = ~_res_hit_msbsEqual_T_57; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsEqual_T_59 = {_res_hit_msbsEqual_T_58[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsEqual_T_60 = ~_res_hit_msbsEqual_T_59; // @[PMP.scala:60:{27,48}] wire [25:0] _res_hit_msbsEqual_T_61 = _res_hit_msbsEqual_T_60[31:6]; // @[PMP.scala:60:27, :81:54] wire [25:0] _res_hit_msbsEqual_T_62 = _res_hit_msbsEqual_T_56 ^ _res_hit_msbsEqual_T_61; // @[PMP.scala:81:{27,41,54}] wire res_hit_msbsEqual_8 = _res_hit_msbsEqual_T_62 == 26'h0; // @[PMP.scala:80:52, :81:{41,54,69}, :123:67] wire [5:0] _res_hit_lsbsLess_T_57 = _res_hit_lsbsLess_T_56; // @[PMP.scala:82:{25,42}] wire [31:0] _res_hit_lsbsLess_T_59 = ~_res_hit_lsbsLess_T_58; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_lsbsLess_T_60 = {_res_hit_lsbsLess_T_59[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbsLess_T_61 = ~_res_hit_lsbsLess_T_60; // @[PMP.scala:60:{27,48}] wire [5:0] _res_hit_lsbsLess_T_62 = _res_hit_lsbsLess_T_61[5:0]; // @[PMP.scala:60:27, :82:64] wire res_hit_lsbsLess_8 = _res_hit_lsbsLess_T_57 < _res_hit_lsbsLess_T_62; // @[PMP.scala:82:{42,53,64}] wire _res_hit_T_58 = res_hit_msbsEqual_8 & res_hit_lsbsLess_8; // @[PMP.scala:81:69, :82:53, :83:30] wire _res_hit_T_59 = res_hit_msbsLess_8 \| _res_hit_T_58; // @[PMP.scala:80:39, :83:{16,30}] wire _res_hit_T_60 = ~_res_hit_T_59; // @[PMP.scala:83:16, :88:5] wire [31:0] _res_hit_msbsLess_T_56 = ~_res_hit_msbsLess_T_55; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsLess_T_57 = {_res_hit_msbsLess_T_56[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsLess_T_58 = ~_res_hit_msbsLess_T_57; // @[PMP.scala:60:{27,48}] wire [25:0] _res_hit_msbsLess_T_59 = _res_hit_msbsLess_T_58[31:6]; // @[PMP.scala:60:27, :80:52] wire res_hit_msbsLess_9 = _res_hit_msbsLess_T_54 < _res_hit_msbsLess_T_59; // @[PMP.scala:80:{25,39,52}] wire [31:0] _res_hit_msbsEqual_T_65 = ~_res_hit_msbsEqual_T_64; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsEqual_T_66 = {_res_hit_msbsEqual_T_65[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsEqual_T_67 = ~_res_hit_msbsEqual_T_66; // @[PMP.scala:60:{27,48}] wire [25:0] _res_hit_msbsEqual_T_68 = _res_hit_msbsEqual_T_67[31:6]; // @[PMP.scala:60:27, :81:54] wire [25:0] _res_hit_msbsEqual_T_69 = _res_hit_msbsEqual_T_63 ^ _res_hit_msbsEqual_T_68; // @[PMP.scala:81:{27,41,54}] wire res_hit_msbsEqual_9 = _res_hit_msbsEqual_T_69 == 26'h0; // @[PMP.scala:80:52, :81:{41,54,69}, :123:67] wire [5:0] _res_hit_lsbsLess_T_64 = _res_hit_lsbsLess_T_63; // @[PMP.scala:82:{25,42}] wire [31:0] _res_hit_lsbsLess_T_66 = ~_res_hit_lsbsLess_T_65; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_lsbsLess_T_67 = {_res_hit_lsbsLess_T_66[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbsLess_T_68 = ~_res_hit_lsbsLess_T_67; // @[PMP.scala:60:{27,48}] wire [5:0] _res_hit_lsbsLess_T_69 = _res_hit_lsbsLess_T_68[5:0]; // @[PMP.scala:60:27, :82:64] wire res_hit_lsbsLess_9 = _res_hit_lsbsLess_T_64 < _res_hit_lsbsLess_T_69; // @[PMP.scala:82:{42,53,64}] wire _res_hit_T_61 = res_hit_msbsEqual_9 & res_hit_lsbsLess_9; // @[PMP.scala:81:69, :82:53, :83:30] wire _res_hit_T_62 = res_hit_msbsLess_9 \| _res_hit_T_61; // @[PMP.scala:80:39, :83:{16,30}] wire _res_hit_T_63 = _res_hit_T_60 & _res_hit_T_62; // @[PMP.scala:83:16, :88:5, :94:48] wire _res_hit_T_64 = _res_hit_T_54 & _res_hit_T_63; // @[PMP.scala:46:26, :94:48, :132:61] wire res_hit_4 = _res_hit_T_52 ? _res_hit_T_53 : _res_hit_T_64; // @[PMP.scala:45:20, :71:16, :132:{8,61}] wire _res_ignore_T_4 = ~io_pmp_3_cfg_l_0; // @[PMP.scala:143:7, :164:29] wire res_ignore_4 = default_0 & _res_ignore_T_4; // @[PMP.scala:156:56, :164:{26,29}] wire [31:0] _res_aligned_straddlesLowerBound_T_70 = ~_res_aligned_straddlesLowerBound_T_69; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesLowerBound_T_71 = {_res_aligned_straddlesLowerBound_T_70[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesLowerBound_T_72 = ~_res_aligned_straddlesLowerBound_T_71; // @[PMP.scala:60:{27,48}] wire [25:0] _res_aligned_straddlesLowerBound_T_73 = _res_aligned_straddlesLowerBound_T_72[31:6]; // @[PMP.scala:60:27, :123:67] wire [25:0] _res_aligned_straddlesLowerBound_T_74 = _res_aligned_straddlesLowerBound_T_68 ^ _res_aligned_straddlesLowerBound_T_73; // @[PMP.scala:123:{35,49,67}] wire _res_aligned_straddlesLowerBound_T_75 = _res_aligned_straddlesLowerBound_T_74 == 26'h0; // @[PMP.scala:80:52, :81:54, :123:{49,67,82}] wire [31:0] _res_aligned_straddlesLowerBound_T_77 = ~_res_aligned_straddlesLowerBound_T_76; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesLowerBound_T_78 = {_res_aligned_straddlesLowerBound_T_77[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesLowerBound_T_79 = ~_res_aligned_straddlesLowerBound_T_78; // @[PMP.scala:60:{27,48}] wire [5:0] _res_aligned_straddlesLowerBound_T_80 = _res_aligned_straddlesLowerBound_T_79[5:0]; // @[PMP.scala:60:27, :123:108] wire [5:0] _res_aligned_straddlesLowerBound_T_82 = ~_res_aligned_straddlesLowerBound_T_81; // @[PMP.scala:123:{127,129}] wire [5:0] _res_aligned_straddlesLowerBound_T_83 = _res_aligned_straddlesLowerBound_T_80 & _res_aligned_straddlesLowerBound_T_82; // @[PMP.scala:123:{108,125,127}] wire _res_aligned_straddlesLowerBound_T_84 = \|_res_aligned_straddlesLowerBound_T_83; // @[PMP.scala:123:{125,147}] wire res_aligned_straddlesLowerBound_4 = _res_aligned_straddlesLowerBound_T_75 & _res_aligned_straddlesLowerBound_T_84; // @[PMP.scala:123:{82,90,147}] wire [31:0] _res_aligned_straddlesUpperBound_T_70 = ~_res_aligned_straddlesUpperBound_T_69; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesUpperBound_T_71 = {_res_aligned_straddlesUpperBound_T_70[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesUpperBound_T_72 = ~_res_aligned_straddlesUpperBound_T_71; // @[PMP.scala:60:{27,48}] wire [25:0] _res_aligned_straddlesUpperBound_T_73 = _res_aligned_straddlesUpperBound_T_72[31:6]; // @[PMP.scala:60:27, :124:62] wire [25:0] _res_aligned_straddlesUpperBound_T_74 = _res_aligned_straddlesUpperBound_T_68 ^ _res_aligned_straddlesUpperBound_T_73; // @[PMP.scala:124:{35,49,62}] wire _res_aligned_straddlesUpperBound_T_75 = _res_aligned_straddlesUpperBound_T_74 == 26'h0; // @[PMP.scala:80:52, :81:54, :123:67, :124:{49,77}] wire [31:0] _res_aligned_straddlesUpperBound_T_77 = ~_res_aligned_straddlesUpperBound_T_76; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesUpperBound_T_78 = {_res_aligned_straddlesUpperBound_T_77[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesUpperBound_T_79 = ~_res_aligned_straddlesUpperBound_T_78; // @[PMP.scala:60:{27,48}] wire [5:0] _res_aligned_straddlesUpperBound_T_80 = _res_aligned_straddlesUpperBound_T_79[5:0]; // @[PMP.scala:60:27, :124:98] wire [5:0] _res_aligned_straddlesUpperBound_T_82 = _res_aligned_straddlesUpperBound_T_81; // @[PMP.scala:124:{119,136}] wire [5:0] _res_aligned_straddlesUpperBound_T_83 = _res_aligned_straddlesUpperBound_T_80 & _res_aligned_straddlesUpperBound_T_82; // @[PMP.scala:124:{98,115,136}] wire _res_aligned_straddlesUpperBound_T_84 = \|_res_aligned_straddlesUpperBound_T_83; // @[PMP.scala:124:{115,148}] wire res_aligned_straddlesUpperBound_4 = _res_aligned_straddlesUpperBound_T_75 & _res_aligned_straddlesUpperBound_T_84; // @[PMP.scala:124:{77,85,148}] wire _res_aligned_rangeAligned_T_4 = res_aligned_straddlesLowerBound_4 \| res_aligned_straddlesUpperBound_4; // @[PMP.scala:123:90, :124:85, :125:46] wire res_aligned_rangeAligned_4 = ~_res_aligned_rangeAligned_T_4; // @[PMP.scala:125:{24,46}] wire [5:0] _res_aligned_pow2Aligned_T_13 = ~_res_aligned_pow2Aligned_T_12; // @[PMP.scala:126:{34,39}] wire res_aligned_4 = _res_aligned_T_4 \| res_aligned_rangeAligned_4; // @[PMP.scala:45:20, :125:24, :127:8] wire _res_T_180 = io_pmp_3_cfg_a_0 == 2'h0; // @[PMP.scala:143:7, :168:32] wire _GEN_21 = io_pmp_3_cfg_a_0 == 2'h1; // @[PMP.scala:143:7, :168:32] wire _res_T_181; // @[PMP.scala:168:32] assign _res_T_181 = _GEN_21; // @[PMP.scala:168:32] wire _res_T_200; // @[PMP.scala:177:61] assign _res_T_200 = _GEN_21; // @[PMP.scala:168:32, :177:61] wire _res_T_204; // @[PMP.scala:178:63] assign _res_T_204 = _GEN_21; // @[PMP.scala:168:32, :178:63] wire _GEN_22 = io_pmp_3_cfg_a_0 == 2'h2; // @[PMP.scala:143:7, :168:32] wire _res_T_182; // @[PMP.scala:168:32] assign _res_T_182 = _GEN_22; // @[PMP.scala:168:32] wire _res_T_209; // @[PMP.scala:177:61] assign _res_T_209 = _GEN_22; // @[PMP.scala:168:32, :177:61] wire _res_T_213; // @[PMP.scala:178:63] assign _res_T_213 = _GEN_22; // @[PMP.scala:168:32, :178:63] wire _res_T_183 = &io_pmp_3_cfg_a_0; // @[PMP.scala:143:7, :168:32] wire [1:0] _GEN_23 = {io_pmp_3_cfg_x_0, io_pmp_3_cfg_w_0}; // @[PMP.scala:143:7, :174:26] wire [1:0] res_hi_24; // @[PMP.scala:174:26] assign res_hi_24 = _GEN_23; // @[PMP.scala:174:26] wire [1:0] res_hi_25; // @[PMP.scala:174:26] assign res_hi_25 = _GEN_23; // @[PMP.scala:174:26] wire [1:0] res_hi_26; // @[PMP.scala:174:26] assign res_hi_26 = _GEN_23; // @[PMP.scala:174:26] wire [1:0] res_hi_27; // @[PMP.scala:174:26] assign res_hi_27 = _GEN_23; // @[PMP.scala:174:26] wire [1:0] res_hi_28; // @[PMP.scala:174:26] assign res_hi_28 = _GEN_23; // @[PMP.scala:174:26] wire [1:0] res_hi_29; // @[PMP.scala:174:26] assign res_hi_29 = _GEN_23; // @[PMP.scala:174:26] wire [2:0] _res_T_185 = {res_hi_24, io_pmp_3_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_186 = _res_T_185 == 3'h0; // @[PMP.scala:143:7, :146:14, :174:{26,60}] wire [2:0] _res_T_187 = {res_hi_25, io_pmp_3_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_188 = _res_T_187 == 3'h1; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_189 = {res_hi_26, io_pmp_3_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_190 = _res_T_189 == 3'h3; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_191 = {res_hi_27, io_pmp_3_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_192 = _res_T_191 == 3'h4; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_193 = {res_hi_28, io_pmp_3_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_194 = _res_T_193 == 3'h5; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_195 = {res_hi_29, io_pmp_3_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_196 = &_res_T_195; // @[PMP.scala:174:{26,60}] wire _res_T_197 = ~res_ignore_4; // @[PMP.scala:164:26, :177:22] wire _res_T_198 = _res_T_197 & res_hit_4; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_199 = _res_T_198 & res_aligned_4; // @[PMP.scala:127:8, :177:{30,37}] wire _res_T_201 = _res_T_199 & _res_T_200; // @[PMP.scala:177:{37,48,61}] wire _GEN_24 = io_pmp_3_cfg_l_0 & res_hit_4; // @[PMP.scala:132:8, :143:7, :178:32] wire _res_T_202; // @[PMP.scala:178:32] assign _res_T_202 = _GEN_24; // @[PMP.scala:178:32] wire _res_T_211; // @[PMP.scala:178:32] assign _res_T_211 = _GEN_24; // @[PMP.scala:178:32] wire _res_T_220; // @[PMP.scala:178:32] assign _res_T_220 = _GEN_24; // @[PMP.scala:178:32] wire _res_T_203 = _res_T_202 & res_aligned_4; // @[PMP.scala:127:8, :178:{32,39}] wire _res_T_205 = _res_T_203 & _res_T_204; // @[PMP.scala:178:{39,50,63}] wire _res_T_206 = ~res_ignore_4; // @[PMP.scala:164:26, :177:22] wire _res_T_207 = _res_T_206 & res_hit_4; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_208 = _res_T_207 & res_aligned_4; // @[PMP.scala:127:8, :177:{30,37}] wire _res_T_210 = _res_T_208 & _res_T_209; // @[PMP.scala:177:{37,48,61}] wire _res_T_212 = _res_T_211 & res_aligned_4; // @[PMP.scala:127:8, :178:{32,39}] wire _res_T_214 = _res_T_212 & _res_T_213; // @[PMP.scala:178:{39,50,63}] wire _res_T_215 = ~res_ignore_4; // @[PMP.scala:164:26, :177:22] wire _res_T_216 = _res_T_215 & res_hit_4; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_217 = _res_T_216 & res_aligned_4; // @[PMP.scala:127:8, :177:{30,37}] wire _res_T_218 = &io_pmp_3_cfg_a_0; // @[PMP.scala:143:7, :168:32, :177:61] wire _res_T_219 = _res_T_217 & _res_T_218; // @[PMP.scala:177:{37,48,61}] wire _res_T_221 = _res_T_220 & res_aligned_4; // @[PMP.scala:127:8, :178:{32,39}] wire _res_T_222 = &io_pmp_3_cfg_a_0; // @[PMP.scala:143:7, :168:32, :178:63] wire _res_T_223 = _res_T_221 & _res_T_222; // @[PMP.scala:178:{39,50,63}] wire _res_cur_cfg_x_T_9; // @[PMP.scala:184:26] wire _res_cur_cfg_w_T_9; // @[PMP.scala:183:26] wire _res_cur_cfg_r_T_9; // @[PMP.scala:182:26] wire res_cur_4_cfg_x; // @[PMP.scala:181:23] wire res_cur_4_cfg_w; // @[PMP.scala:181:23] wire res_cur_4_cfg_r; // @[PMP.scala:181:23] wire _res_cur_cfg_r_T_8 = io_pmp_3_cfg_r_0 \| res_ignore_4; // @[PMP.scala:143:7, :164:26, :182:40] assign _res_cur_cfg_r_T_9 = res_aligned_4 & _res_cur_cfg_r_T_8; // @[PMP.scala:127:8, :182:{26,40}] assign res_cur_4_cfg_r = _res_cur_cfg_r_T_9; // @[PMP.scala:181:23, :182:26] wire _res_cur_cfg_w_T_8 = io_pmp_3_cfg_w_0 \| res_ignore_4; // @[PMP.scala:143:7, :164:26, :183:40] assign _res_cur_cfg_w_T_9 = res_aligned_4 & _res_cur_cfg_w_T_8; // @[PMP.scala:127:8, :183:{26,40}] assign res_cur_4_cfg_w = _res_cur_cfg_w_T_9; // @[PMP.scala:181:23, :183:26] wire _res_cur_cfg_x_T_8 = io_pmp_3_cfg_x_0 \| res_ignore_4; // @[PMP.scala:143:7, :164:26, :184:40] assign _res_cur_cfg_x_T_9 = res_aligned_4 & _res_cur_cfg_x_T_8; // @[PMP.scala:127:8, :184:{26,40}] assign res_cur_4_cfg_x = _res_cur_cfg_x_T_9; // @[PMP.scala:181:23, :184:26] wire _res_T_224_cfg_l = res_hit_4 ? res_cur_4_cfg_l : _res_T_179_cfg_l; // @[PMP.scala:132:8, :181:23, :185:8] wire [1:0] _res_T_224_cfg_a = res_hit_4 ? res_cur_4_cfg_a : _res_T_179_cfg_a; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_T_224_cfg_x = res_hit_4 ? res_cur_4_cfg_x : _res_T_179_cfg_x; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_T_224_cfg_w = res_hit_4 ? res_cur_4_cfg_w : _res_T_179_cfg_w; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_T_224_cfg_r = res_hit_4 ? res_cur_4_cfg_r : _res_T_179_cfg_r; // @[PMP.scala:132:8, :181:23, :185:8] wire [29:0] _res_T_224_addr = res_hit_4 ? res_cur_4_addr : _res_T_179_addr; // @[PMP.scala:132:8, :181:23, :185:8] wire [31:0] _res_T_224_mask = res_hit_4 ? res_cur_4_mask : _res_T_179_mask; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_hit_T_65 = io_pmp_2_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7] wire _res_aligned_T_5 = io_pmp_2_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7] wire [25:0] _res_hit_msbMatch_T_56 = io_pmp_2_mask_0[31:6]; // @[PMP.scala:68:26, :69:72, :143:7] wire [5:0] _res_aligned_pow2Aligned_T_15 = io_pmp_2_mask_0[5:0]; // @[PMP.scala:68:26, :126:39, :143:7] wire [31:0] _res_hit_msbMatch_T_52 = ~_res_hit_msbMatch_T_51; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbMatch_T_53 = {_res_hit_msbMatch_T_52[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbMatch_T_54 = ~_res_hit_msbMatch_T_53; // @[PMP.scala:60:{27,48}] wire [25:0] _res_hit_msbMatch_T_55 = _res_hit_msbMatch_T_54[31:6]; // @[PMP.scala:60:27, :69:53] wire [25:0] _res_hit_msbMatch_T_57 = _res_hit_msbMatch_T_50 ^ _res_hit_msbMatch_T_55; // @[PMP.scala:63:47, :69:{29,53}] wire [25:0] _res_hit_msbMatch_T_58 = ~_res_hit_msbMatch_T_56; // @[PMP.scala:63:54, :69:72] wire [25:0] _res_hit_msbMatch_T_59 = _res_hit_msbMatch_T_57 & _res_hit_msbMatch_T_58; // @[PMP.scala:63:{47,52,54}] wire res_hit_msbMatch_5 = _res_hit_msbMatch_T_59 == 26'h0; // @[PMP.scala:63:{52,58}, :80:52, :81:54, :123:67] wire [31:0] _res_hit_lsbMatch_T_52 = ~_res_hit_lsbMatch_T_51; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_lsbMatch_T_53 = {_res_hit_lsbMatch_T_52[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbMatch_T_54 = ~_res_hit_lsbMatch_T_53; // @[PMP.scala:60:{27,48}] wire [5:0] _res_hit_lsbMatch_T_55 = _res_hit_lsbMatch_T_54[5:0]; // @[PMP.scala:60:27, :70:55] wire [5:0] _res_hit_lsbMatch_T_56 = res_hit_lsbMask_5[5:0]; // @[PMP.scala:68:26, :70:80] wire [5:0] _res_hit_lsbMatch_T_57 = _res_hit_lsbMatch_T_50 ^ _res_hit_lsbMatch_T_55; // @[PMP.scala:63:47, :70:{28,55}] wire [5:0] _res_hit_lsbMatch_T_58 = ~_res_hit_lsbMatch_T_56; // @[PMP.scala:63:54, :70:80] wire [5:0] _res_hit_lsbMatch_T_59 = _res_hit_lsbMatch_T_57 & _res_hit_lsbMatch_T_58; // @[PMP.scala:63:{47,52,54}] wire res_hit_lsbMatch_5 = _res_hit_lsbMatch_T_59 == 6'h0; // @[PMP.scala:63:{52,58}] wire _res_hit_T_66 = res_hit_msbMatch_5 & res_hit_lsbMatch_5; // @[PMP.scala:63:58, :71:16] wire _res_hit_T_67 = io_pmp_2_cfg_a_0[0]; // @[PMP.scala:46:26, :143:7] wire [31:0] _GEN_25 = {io_pmp_1_addr_0, 2'h0}; // @[PMP.scala:60:36, :143:7] wire [31:0] _res_hit_msbsLess_T_61; // @[PMP.scala:60:36] assign _res_hit_msbsLess_T_61 = _GEN_25; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsEqual_T_71; // @[PMP.scala:60:36] assign _res_hit_msbsEqual_T_71 = _GEN_25; // @[PMP.scala:60:36] wire [31:0] _res_hit_lsbsLess_T_72; // @[PMP.scala:60:36] assign _res_hit_lsbsLess_T_72 = _GEN_25; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesLowerBound_T_86; // @[PMP.scala:60:36] assign _res_aligned_straddlesLowerBound_T_86 = _GEN_25; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesLowerBound_T_93; // @[PMP.scala:60:36] assign _res_aligned_straddlesLowerBound_T_93 = _GEN_25; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbMatch_T_61; // @[PMP.scala:60:36] assign _res_hit_msbMatch_T_61 = _GEN_25; // @[PMP.scala:60:36] wire [31:0] _res_hit_lsbMatch_T_61; // @[PMP.scala:60:36] assign _res_hit_lsbMatch_T_61 = _GEN_25; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsLess_T_79; // @[PMP.scala:60:36] assign _res_hit_msbsLess_T_79 = _GEN_25; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsEqual_T_92; // @[PMP.scala:60:36] assign _res_hit_msbsEqual_T_92 = _GEN_25; // @[PMP.scala:60:36] wire [31:0] _res_hit_lsbsLess_T_93; // @[PMP.scala:60:36] assign _res_hit_lsbsLess_T_93 = _GEN_25; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesUpperBound_T_103; // @[PMP.scala:60:36] assign _res_aligned_straddlesUpperBound_T_103 = _GEN_25; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesUpperBound_T_110; // @[PMP.scala:60:36] assign _res_aligned_straddlesUpperBound_T_110 = _GEN_25; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsLess_T_62 = ~_res_hit_msbsLess_T_61; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsLess_T_63 = {_res_hit_msbsLess_T_62[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsLess_T_64 = ~_res_hit_msbsLess_T_63; // @[PMP.scala:60:{27,48}] wire [25:0] _res_hit_msbsLess_T_65 = _res_hit_msbsLess_T_64[31:6]; // @[PMP.scala:60:27, :80:52] wire res_hit_msbsLess_10 = _res_hit_msbsLess_T_60 < _res_hit_msbsLess_T_65; // @[PMP.scala:80:{25,39,52}] wire [31:0] _res_hit_msbsEqual_T_72 = ~_res_hit_msbsEqual_T_71; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsEqual_T_73 = {_res_hit_msbsEqual_T_72[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsEqual_T_74 = ~_res_hit_msbsEqual_T_73; // @[PMP.scala:60:{27,48}] wire [25:0] _res_hit_msbsEqual_T_75 = _res_hit_msbsEqual_T_74[31:6]; // @[PMP.scala:60:27, :81:54] wire [25:0] _res_hit_msbsEqual_T_76 = _res_hit_msbsEqual_T_70 ^ _res_hit_msbsEqual_T_75; // @[PMP.scala:81:{27,41,54}] wire res_hit_msbsEqual_10 = _res_hit_msbsEqual_T_76 == 26'h0; // @[PMP.scala:80:52, :81:{41,54,69}, :123:67] wire [5:0] _res_hit_lsbsLess_T_71 = _res_hit_lsbsLess_T_70; // @[PMP.scala:82:{25,42}] wire [31:0] _res_hit_lsbsLess_T_73 = ~_res_hit_lsbsLess_T_72; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_lsbsLess_T_74 = {_res_hit_lsbsLess_T_73[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbsLess_T_75 = ~_res_hit_lsbsLess_T_74; // @[PMP.scala:60:{27,48}] wire [5:0] _res_hit_lsbsLess_T_76 = _res_hit_lsbsLess_T_75[5:0]; // @[PMP.scala:60:27, :82:64] wire res_hit_lsbsLess_10 = _res_hit_lsbsLess_T_71 < _res_hit_lsbsLess_T_76; // @[PMP.scala:82:{42,53,64}] wire _res_hit_T_71 = res_hit_msbsEqual_10 & res_hit_lsbsLess_10; // @[PMP.scala:81:69, :82:53, :83:30] wire _res_hit_T_72 = res_hit_msbsLess_10 \| _res_hit_T_71; // @[PMP.scala:80:39, :83:{16,30}] wire _res_hit_T_73 = ~_res_hit_T_72; // @[PMP.scala:83:16, :88:5] wire [31:0] _res_hit_msbsLess_T_68 = ~_res_hit_msbsLess_T_67; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsLess_T_69 = {_res_hit_msbsLess_T_68[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsLess_T_70 = ~_res_hit_msbsLess_T_69; // @[PMP.scala:60:{27,48}] wire [25:0] _res_hit_msbsLess_T_71 = _res_hit_msbsLess_T_70[31:6]; // @[PMP.scala:60:27, :80:52] wire res_hit_msbsLess_11 = _res_hit_msbsLess_T_66 < _res_hit_msbsLess_T_71; // @[PMP.scala:80:{25,39,52}] wire [31:0] _res_hit_msbsEqual_T_79 = ~_res_hit_msbsEqual_T_78; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsEqual_T_80 = {_res_hit_msbsEqual_T_79[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsEqual_T_81 = ~_res_hit_msbsEqual_T_80; // @[PMP.scala:60:{27,48}] wire [25:0] _res_hit_msbsEqual_T_82 = _res_hit_msbsEqual_T_81[31:6]; // @[PMP.scala:60:27, :81:54] wire [25:0] _res_hit_msbsEqual_T_83 = _res_hit_msbsEqual_T_77 ^ _res_hit_msbsEqual_T_82; // @[PMP.scala:81:{27,41,54}] wire res_hit_msbsEqual_11 = _res_hit_msbsEqual_T_83 == 26'h0; // @[PMP.scala:80:52, :81:{41,54,69}, :123:67] wire [5:0] _res_hit_lsbsLess_T_78 = _res_hit_lsbsLess_T_77; // @[PMP.scala:82:{25,42}] wire [31:0] _res_hit_lsbsLess_T_80 = ~_res_hit_lsbsLess_T_79; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_lsbsLess_T_81 = {_res_hit_lsbsLess_T_80[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbsLess_T_82 = ~_res_hit_lsbsLess_T_81; // @[PMP.scala:60:{27,48}] wire [5:0] _res_hit_lsbsLess_T_83 = _res_hit_lsbsLess_T_82[5:0]; // @[PMP.scala:60:27, :82:64] wire res_hit_lsbsLess_11 = _res_hit_lsbsLess_T_78 < _res_hit_lsbsLess_T_83; // @[PMP.scala:82:{42,53,64}] wire _res_hit_T_74 = res_hit_msbsEqual_11 & res_hit_lsbsLess_11; // @[PMP.scala:81:69, :82:53, :83:30] wire _res_hit_T_75 = res_hit_msbsLess_11 \| _res_hit_T_74; // @[PMP.scala:80:39, :83:{16,30}] wire _res_hit_T_76 = _res_hit_T_73 & _res_hit_T_75; // @[PMP.scala:83:16, :88:5, :94:48] wire _res_hit_T_77 = _res_hit_T_67 & _res_hit_T_76; // @[PMP.scala:46:26, :94:48, :132:61] wire res_hit_5 = _res_hit_T_65 ? _res_hit_T_66 : _res_hit_T_77; // @[PMP.scala:45:20, :71:16, :132:{8,61}] wire _res_ignore_T_5 = ~io_pmp_2_cfg_l_0; // @[PMP.scala:143:7, :164:29] wire res_ignore_5 = default_0 & _res_ignore_T_5; // @[PMP.scala:156:56, :164:{26,29}] wire [31:0] _res_aligned_straddlesLowerBound_T_87 = ~_res_aligned_straddlesLowerBound_T_86; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesLowerBound_T_88 = {_res_aligned_straddlesLowerBound_T_87[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesLowerBound_T_89 = ~_res_aligned_straddlesLowerBound_T_88; // @[PMP.scala:60:{27,48}] wire [25:0] _res_aligned_straddlesLowerBound_T_90 = _res_aligned_straddlesLowerBound_T_89[31:6]; // @[PMP.scala:60:27, :123:67] wire [25:0] _res_aligned_straddlesLowerBound_T_91 = _res_aligned_straddlesLowerBound_T_85 ^ _res_aligned_straddlesLowerBound_T_90; // @[PMP.scala:123:{35,49,67}] wire _res_aligned_straddlesLowerBound_T_92 = _res_aligned_straddlesLowerBound_T_91 == 26'h0; // @[PMP.scala:80:52, :81:54, :123:{49,67,82}] wire [31:0] _res_aligned_straddlesLowerBound_T_94 = ~_res_aligned_straddlesLowerBound_T_93; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesLowerBound_T_95 = {_res_aligned_straddlesLowerBound_T_94[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesLowerBound_T_96 = ~_res_aligned_straddlesLowerBound_T_95; // @[PMP.scala:60:{27,48}] wire [5:0] _res_aligned_straddlesLowerBound_T_97 = _res_aligned_straddlesLowerBound_T_96[5:0]; // @[PMP.scala:60:27, :123:108] wire [5:0] _res_aligned_straddlesLowerBound_T_99 = ~_res_aligned_straddlesLowerBound_T_98; // @[PMP.scala:123:{127,129}] wire [5:0] _res_aligned_straddlesLowerBound_T_100 = _res_aligned_straddlesLowerBound_T_97 & _res_aligned_straddlesLowerBound_T_99; // @[PMP.scala:123:{108,125,127}] wire _res_aligned_straddlesLowerBound_T_101 = \|_res_aligned_straddlesLowerBound_T_100; // @[PMP.scala:123:{125,147}] wire res_aligned_straddlesLowerBound_5 = _res_aligned_straddlesLowerBound_T_92 & _res_aligned_straddlesLowerBound_T_101; // @[PMP.scala:123:{82,90,147}] wire [31:0] _res_aligned_straddlesUpperBound_T_87 = ~_res_aligned_straddlesUpperBound_T_86; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesUpperBound_T_88 = {_res_aligned_straddlesUpperBound_T_87[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesUpperBound_T_89 = ~_res_aligned_straddlesUpperBound_T_88; // @[PMP.scala:60:{27,48}] wire [25:0] _res_aligned_straddlesUpperBound_T_90 = _res_aligned_straddlesUpperBound_T_89[31:6]; // @[PMP.scala:60:27, :124:62] wire [25:0] _res_aligned_straddlesUpperBound_T_91 = _res_aligned_straddlesUpperBound_T_85 ^ _res_aligned_straddlesUpperBound_T_90; // @[PMP.scala:124:{35,49,62}] wire _res_aligned_straddlesUpperBound_T_92 = _res_aligned_straddlesUpperBound_T_91 == 26'h0; // @[PMP.scala:80:52, :81:54, :123:67, :124:{49,77}] wire [31:0] _res_aligned_straddlesUpperBound_T_94 = ~_res_aligned_straddlesUpperBound_T_93; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesUpperBound_T_95 = {_res_aligned_straddlesUpperBound_T_94[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesUpperBound_T_96 = ~_res_aligned_straddlesUpperBound_T_95; // @[PMP.scala:60:{27,48}] wire [5:0] _res_aligned_straddlesUpperBound_T_97 = _res_aligned_straddlesUpperBound_T_96[5:0]; // @[PMP.scala:60:27, :124:98] wire [5:0] _res_aligned_straddlesUpperBound_T_99 = _res_aligned_straddlesUpperBound_T_98; // @[PMP.scala:124:{119,136}] wire [5:0] _res_aligned_straddlesUpperBound_T_100 = _res_aligned_straddlesUpperBound_T_97 & _res_aligned_straddlesUpperBound_T_99; // @[PMP.scala:124:{98,115,136}] wire _res_aligned_straddlesUpperBound_T_101 = \|_res_aligned_straddlesUpperBound_T_100; // @[PMP.scala:124:{115,148}] wire res_aligned_straddlesUpperBound_5 = _res_aligned_straddlesUpperBound_T_92 & _res_aligned_straddlesUpperBound_T_101; // @[PMP.scala:124:{77,85,148}] wire _res_aligned_rangeAligned_T_5 = res_aligned_straddlesLowerBound_5 \| res_aligned_straddlesUpperBound_5; // @[PMP.scala:123:90, :124:85, :125:46] wire res_aligned_rangeAligned_5 = ~_res_aligned_rangeAligned_T_5; // @[PMP.scala:125:{24,46}] wire [5:0] _res_aligned_pow2Aligned_T_16 = ~_res_aligned_pow2Aligned_T_15; // @[PMP.scala:126:{34,39}] wire res_aligned_5 = _res_aligned_T_5 \| res_aligned_rangeAligned_5; // @[PMP.scala:45:20, :125:24, :127:8] wire _res_T_225 = io_pmp_2_cfg_a_0 == 2'h0; // @[PMP.scala:143:7, :168:32] wire _GEN_26 = io_pmp_2_cfg_a_0 == 2'h1; // @[PMP.scala:143:7, :168:32] wire _res_T_226; // @[PMP.scala:168:32] assign _res_T_226 = _GEN_26; // @[PMP.scala:168:32] wire _res_T_245; // @[PMP.scala:177:61] assign _res_T_245 = _GEN_26; // @[PMP.scala:168:32, :177:61] wire _res_T_249; // @[PMP.scala:178:63] assign _res_T_249 = _GEN_26; // @[PMP.scala:168:32, :178:63] wire _GEN_27 = io_pmp_2_cfg_a_0 == 2'h2; // @[PMP.scala:143:7, :168:32] wire _res_T_227; // @[PMP.scala:168:32] assign _res_T_227 = _GEN_27; // @[PMP.scala:168:32] wire _res_T_254; // @[PMP.scala:177:61] assign _res_T_254 = _GEN_27; // @[PMP.scala:168:32, :177:61] wire _res_T_258; // @[PMP.scala:178:63] assign _res_T_258 = _GEN_27; // @[PMP.scala:168:32, :178:63] wire _res_T_228 = &io_pmp_2_cfg_a_0; // @[PMP.scala:143:7, :168:32] wire [1:0] _GEN_28 = {io_pmp_2_cfg_x_0, io_pmp_2_cfg_w_0}; // @[PMP.scala:143:7, :174:26] wire [1:0] res_hi_30; // @[PMP.scala:174:26] assign res_hi_30 = _GEN_28; // @[PMP.scala:174:26] wire [1:0] res_hi_31; // @[PMP.scala:174:26] assign res_hi_31 = _GEN_28; // @[PMP.scala:174:26] wire [1:0] res_hi_32; // @[PMP.scala:174:26] assign res_hi_32 = _GEN_28; // @[PMP.scala:174:26] wire [1:0] res_hi_33; // @[PMP.scala:174:26] assign res_hi_33 = _GEN_28; // @[PMP.scala:174:26] wire [1:0] res_hi_34; // @[PMP.scala:174:26] assign res_hi_34 = _GEN_28; // @[PMP.scala:174:26] wire [1:0] res_hi_35; // @[PMP.scala:174:26] assign res_hi_35 = _GEN_28; // @[PMP.scala:174:26] wire [2:0] _res_T_230 = {res_hi_30, io_pmp_2_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_231 = _res_T_230 == 3'h0; // @[PMP.scala:143:7, :146:14, :174:{26,60}] wire [2:0] _res_T_232 = {res_hi_31, io_pmp_2_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_233 = _res_T_232 == 3'h1; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_234 = {res_hi_32, io_pmp_2_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_235 = _res_T_234 == 3'h3; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_236 = {res_hi_33, io_pmp_2_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_237 = _res_T_236 == 3'h4; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_238 = {res_hi_34, io_pmp_2_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_239 = _res_T_238 == 3'h5; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_240 = {res_hi_35, io_pmp_2_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_241 = &_res_T_240; // @[PMP.scala:174:{26,60}] wire _res_T_242 = ~res_ignore_5; // @[PMP.scala:164:26, :177:22] wire _res_T_243 = _res_T_242 & res_hit_5; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_244 = _res_T_243 & res_aligned_5; // @[PMP.scala:127:8, :177:{30,37}] wire _res_T_246 = _res_T_244 & _res_T_245; // @[PMP.scala:177:{37,48,61}] wire _GEN_29 = io_pmp_2_cfg_l_0 & res_hit_5; // @[PMP.scala:132:8, :143:7, :178:32] wire _res_T_247; // @[PMP.scala:178:32] assign _res_T_247 = _GEN_29; // @[PMP.scala:178:32] wire _res_T_256; // @[PMP.scala:178:32] assign _res_T_256 = _GEN_29; // @[PMP.scala:178:32] wire _res_T_265; // @[PMP.scala:178:32] assign _res_T_265 = _GEN_29; // @[PMP.scala:178:32] wire _res_T_248 = _res_T_247 & res_aligned_5; // @[PMP.scala:127:8, :178:{32,39}] wire _res_T_250 = _res_T_248 & _res_T_249; // @[PMP.scala:178:{39,50,63}] wire _res_T_251 = ~res_ignore_5; // @[PMP.scala:164:26, :177:22] wire _res_T_252 = _res_T_251 & res_hit_5; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_253 = _res_T_252 & res_aligned_5; // @[PMP.scala:127:8, :177:{30,37}] wire _res_T_255 = _res_T_253 & _res_T_254; // @[PMP.scala:177:{37,48,61}] wire _res_T_257 = _res_T_256 & res_aligned_5; // @[PMP.scala:127:8, :178:{32,39}] wire _res_T_259 = _res_T_257 & _res_T_258; // @[PMP.scala:178:{39,50,63}] wire _res_T_260 = ~res_ignore_5; // @[PMP.scala:164:26, :177:22] wire _res_T_261 = _res_T_260 & res_hit_5; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_262 = _res_T_261 & res_aligned_5; // @[PMP.scala:127:8, :177:{30,37}] wire _res_T_263 = &io_pmp_2_cfg_a_0; // @[PMP.scala:143:7, :168:32, :177:61] wire _res_T_264 = _res_T_262 & _res_T_263; // @[PMP.scala:177:{37,48,61}] wire _res_T_266 = _res_T_265 & res_aligned_5; // @[PMP.scala:127:8, :178:{32,39}] wire _res_T_267 = &io_pmp_2_cfg_a_0; // @[PMP.scala:143:7, :168:32, :178:63] wire _res_T_268 = _res_T_266 & _res_T_267; // @[PMP.scala:178:{39,50,63}] wire _res_cur_cfg_x_T_11; // @[PMP.scala:184:26] wire _res_cur_cfg_w_T_11; // @[PMP.scala:183:26] wire _res_cur_cfg_r_T_11; // @[PMP.scala:182:26] wire res_cur_5_cfg_x; // @[PMP.scala:181:23] wire res_cur_5_cfg_w; // @[PMP.scala:181:23] wire res_cur_5_cfg_r; // @[PMP.scala:181:23] wire _res_cur_cfg_r_T_10 = io_pmp_2_cfg_r_0 \| res_ignore_5; // @[PMP.scala:143:7, :164:26, :182:40] assign _res_cur_cfg_r_T_11 = res_aligned_5 & _res_cur_cfg_r_T_10; // @[PMP.scala:127:8, :182:{26,40}] assign res_cur_5_cfg_r = _res_cur_cfg_r_T_11; // @[PMP.scala:181:23, :182:26] wire _res_cur_cfg_w_T_10 = io_pmp_2_cfg_w_0 \| res_ignore_5; // @[PMP.scala:143:7, :164:26, :183:40] assign _res_cur_cfg_w_T_11 = res_aligned_5 & _res_cur_cfg_w_T_10; // @[PMP.scala:127:8, :183:{26,40}] assign res_cur_5_cfg_w = _res_cur_cfg_w_T_11; // @[PMP.scala:181:23, :183:26] wire _res_cur_cfg_x_T_10 = io_pmp_2_cfg_x_0 \| res_ignore_5; // @[PMP.scala:143:7, :164:26, :184:40] assign _res_cur_cfg_x_T_11 = res_aligned_5 & _res_cur_cfg_x_T_10; // @[PMP.scala:127:8, :184:{26,40}] assign res_cur_5_cfg_x = _res_cur_cfg_x_T_11; // @[PMP.scala:181:23, :184:26] wire _res_T_269_cfg_l = res_hit_5 ? res_cur_5_cfg_l : _res_T_224_cfg_l; // @[PMP.scala:132:8, :181:23, :185:8] wire [1:0] _res_T_269_cfg_a = res_hit_5 ? res_cur_5_cfg_a : _res_T_224_cfg_a; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_T_269_cfg_x = res_hit_5 ? res_cur_5_cfg_x : _res_T_224_cfg_x; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_T_269_cfg_w = res_hit_5 ? res_cur_5_cfg_w : _res_T_224_cfg_w; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_T_269_cfg_r = res_hit_5 ? res_cur_5_cfg_r : _res_T_224_cfg_r; // @[PMP.scala:132:8, :181:23, :185:8] wire [29:0] _res_T_269_addr = res_hit_5 ? res_cur_5_addr : _res_T_224_addr; // @[PMP.scala:132:8, :181:23, :185:8] wire [31:0] _res_T_269_mask = res_hit_5 ? res_cur_5_mask : _res_T_224_mask; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_hit_T_78 = io_pmp_1_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7] wire _res_aligned_T_6 = io_pmp_1_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7] wire [25:0] _res_hit_msbMatch_T_66 = io_pmp_1_mask_0[31:6]; // @[PMP.scala:68:26, :69:72, :143:7] wire [5:0] _res_aligned_pow2Aligned_T_18 = io_pmp_1_mask_0[5:0]; // @[PMP.scala:68:26, :126:39, :143:7] wire [31:0] _res_hit_msbMatch_T_62 = ~_res_hit_msbMatch_T_61; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbMatch_T_63 = {_res_hit_msbMatch_T_62[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbMatch_T_64 = ~_res_hit_msbMatch_T_63; // @[PMP.scala:60:{27,48}] wire [25:0] _res_hit_msbMatch_T_65 = _res_hit_msbMatch_T_64[31:6]; // @[PMP.scala:60:27, :69:53] wire [25:0] _res_hit_msbMatch_T_67 = _res_hit_msbMatch_T_60 ^ _res_hit_msbMatch_T_65; // @[PMP.scala:63:47, :69:{29,53}] wire [25:0] _res_hit_msbMatch_T_68 = ~_res_hit_msbMatch_T_66; // @[PMP.scala:63:54, :69:72] wire [25:0] _res_hit_msbMatch_T_69 = _res_hit_msbMatch_T_67 & _res_hit_msbMatch_T_68; // @[PMP.scala:63:{47,52,54}] wire res_hit_msbMatch_6 = _res_hit_msbMatch_T_69 == 26'h0; // @[PMP.scala:63:{52,58}, :80:52, :81:54, :123:67] wire [31:0] _res_hit_lsbMatch_T_62 = ~_res_hit_lsbMatch_T_61; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_lsbMatch_T_63 = {_res_hit_lsbMatch_T_62[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbMatch_T_64 = ~_res_hit_lsbMatch_T_63; // @[PMP.scala:60:{27,48}] wire [5:0] _res_hit_lsbMatch_T_65 = _res_hit_lsbMatch_T_64[5:0]; // @[PMP.scala:60:27, :70:55] wire [5:0] _res_hit_lsbMatch_T_66 = res_hit_lsbMask_6[5:0]; // @[PMP.scala:68:26, :70:80] wire [5:0] _res_hit_lsbMatch_T_67 = _res_hit_lsbMatch_T_60 ^ _res_hit_lsbMatch_T_65; // @[PMP.scala:63:47, :70:{28,55}] wire [5:0] _res_hit_lsbMatch_T_68 = ~_res_hit_lsbMatch_T_66; // @[PMP.scala:63:54, :70:80] wire [5:0] _res_hit_lsbMatch_T_69 = _res_hit_lsbMatch_T_67 & _res_hit_lsbMatch_T_68; // @[PMP.scala:63:{47,52,54}] wire res_hit_lsbMatch_6 = _res_hit_lsbMatch_T_69 == 6'h0; // @[PMP.scala:63:{52,58}] wire _res_hit_T_79 = res_hit_msbMatch_6 & res_hit_lsbMatch_6; // @[PMP.scala:63:58, :71:16] wire _res_hit_T_80 = io_pmp_1_cfg_a_0[0]; // @[PMP.scala:46:26, :143:7] wire [31:0] _GEN_30 = {io_pmp_0_addr_0, 2'h0}; // @[PMP.scala:60:36, :143:7] wire [31:0] _res_hit_msbsLess_T_73; // @[PMP.scala:60:36] assign _res_hit_msbsLess_T_73 = _GEN_30; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsEqual_T_85; // @[PMP.scala:60:36] assign _res_hit_msbsEqual_T_85 = _GEN_30; // @[PMP.scala:60:36] wire [31:0] _res_hit_lsbsLess_T_86; // @[PMP.scala:60:36] assign _res_hit_lsbsLess_T_86 = _GEN_30; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesLowerBound_T_103; // @[PMP.scala:60:36] assign _res_aligned_straddlesLowerBound_T_103 = _GEN_30; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesLowerBound_T_110; // @[PMP.scala:60:36] assign _res_aligned_straddlesLowerBound_T_110 = _GEN_30; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbMatch_T_71; // @[PMP.scala:60:36] assign _res_hit_msbMatch_T_71 = _GEN_30; // @[PMP.scala:60:36] wire [31:0] _res_hit_lsbMatch_T_71; // @[PMP.scala:60:36] assign _res_hit_lsbMatch_T_71 = _GEN_30; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsLess_T_91; // @[PMP.scala:60:36] assign _res_hit_msbsLess_T_91 = _GEN_30; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsEqual_T_106; // @[PMP.scala:60:36] assign _res_hit_msbsEqual_T_106 = _GEN_30; // @[PMP.scala:60:36] wire [31:0] _res_hit_lsbsLess_T_107; // @[PMP.scala:60:36] assign _res_hit_lsbsLess_T_107 = _GEN_30; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesUpperBound_T_120; // @[PMP.scala:60:36] assign _res_aligned_straddlesUpperBound_T_120 = _GEN_30; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesUpperBound_T_127; // @[PMP.scala:60:36] assign _res_aligned_straddlesUpperBound_T_127 = _GEN_30; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsLess_T_74 = ~_res_hit_msbsLess_T_73; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsLess_T_75 = {_res_hit_msbsLess_T_74[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsLess_T_76 = ~_res_hit_msbsLess_T_75; // @[PMP.scala:60:{27,48}] wire [25:0] _res_hit_msbsLess_T_77 = _res_hit_msbsLess_T_76[31:6]; // @[PMP.scala:60:27, :80:52] wire res_hit_msbsLess_12 = _res_hit_msbsLess_T_72 < _res_hit_msbsLess_T_77; // @[PMP.scala:80:{25,39,52}] wire [31:0] _res_hit_msbsEqual_T_86 = ~_res_hit_msbsEqual_T_85; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsEqual_T_87 = {_res_hit_msbsEqual_T_86[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsEqual_T_88 = ~_res_hit_msbsEqual_T_87; // @[PMP.scala:60:{27,48}] wire [25:0] _res_hit_msbsEqual_T_89 = _res_hit_msbsEqual_T_88[31:6]; // @[PMP.scala:60:27, :81:54] wire [25:0] _res_hit_msbsEqual_T_90 = _res_hit_msbsEqual_T_84 ^ _res_hit_msbsEqual_T_89; // @[PMP.scala:81:{27,41,54}] wire res_hit_msbsEqual_12 = _res_hit_msbsEqual_T_90 == 26'h0; // @[PMP.scala:80:52, :81:{41,54,69}, :123:67] wire [5:0] _res_hit_lsbsLess_T_85 = _res_hit_lsbsLess_T_84; // @[PMP.scala:82:{25,42}] wire [31:0] _res_hit_lsbsLess_T_87 = ~_res_hit_lsbsLess_T_86; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_lsbsLess_T_88 = {_res_hit_lsbsLess_T_87[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbsLess_T_89 = ~_res_hit_lsbsLess_T_88; // @[PMP.scala:60:{27,48}] wire [5:0] _res_hit_lsbsLess_T_90 = _res_hit_lsbsLess_T_89[5:0]; // @[PMP.scala:60:27, :82:64] wire res_hit_lsbsLess_12 = _res_hit_lsbsLess_T_85 < _res_hit_lsbsLess_T_90; // @[PMP.scala:82:{42,53,64}] wire _res_hit_T_84 = res_hit_msbsEqual_12 & res_hit_lsbsLess_12; // @[PMP.scala:81:69, :82:53, :83:30] wire _res_hit_T_85 = res_hit_msbsLess_12 \| _res_hit_T_84; // @[PMP.scala:80:39, :83:{16,30}] wire _res_hit_T_86 = ~_res_hit_T_85; // @[PMP.scala:83:16, :88:5] wire [31:0] _res_hit_msbsLess_T_80 = ~_res_hit_msbsLess_T_79; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsLess_T_81 = {_res_hit_msbsLess_T_80[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsLess_T_82 = ~_res_hit_msbsLess_T_81; // @[PMP.scala:60:{27,48}] wire [25:0] _res_hit_msbsLess_T_83 = _res_hit_msbsLess_T_82[31:6]; // @[PMP.scala:60:27, :80:52] wire res_hit_msbsLess_13 = _res_hit_msbsLess_T_78 < _res_hit_msbsLess_T_83; // @[PMP.scala:80:{25,39,52}] wire [31:0] _res_hit_msbsEqual_T_93 = ~_res_hit_msbsEqual_T_92; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsEqual_T_94 = {_res_hit_msbsEqual_T_93[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsEqual_T_95 = ~_res_hit_msbsEqual_T_94; // @[PMP.scala:60:{27,48}] wire [25:0] _res_hit_msbsEqual_T_96 = _res_hit_msbsEqual_T_95[31:6]; // @[PMP.scala:60:27, :81:54] wire [25:0] _res_hit_msbsEqual_T_97 = _res_hit_msbsEqual_T_91 ^ _res_hit_msbsEqual_T_96; // @[PMP.scala:81:{27,41,54}] wire res_hit_msbsEqual_13 = _res_hit_msbsEqual_T_97 == 26'h0; // @[PMP.scala:80:52, :81:{41,54,69}, :123:67] wire [5:0] _res_hit_lsbsLess_T_92 = _res_hit_lsbsLess_T_91; // @[PMP.scala:82:{25,42}] wire [31:0] _res_hit_lsbsLess_T_94 = ~_res_hit_lsbsLess_T_93; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_lsbsLess_T_95 = {_res_hit_lsbsLess_T_94[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbsLess_T_96 = ~_res_hit_lsbsLess_T_95; // @[PMP.scala:60:{27,48}] wire [5:0] _res_hit_lsbsLess_T_97 = _res_hit_lsbsLess_T_96[5:0]; // @[PMP.scala:60:27, :82:64] wire res_hit_lsbsLess_13 = _res_hit_lsbsLess_T_92 < _res_hit_lsbsLess_T_97; // @[PMP.scala:82:{42,53,64}] wire _res_hit_T_87 = res_hit_msbsEqual_13 & res_hit_lsbsLess_13; // @[PMP.scala:81:69, :82:53, :83:30] wire _res_hit_T_88 = res_hit_msbsLess_13 \| _res_hit_T_87; // @[PMP.scala:80:39, :83:{16,30}] wire _res_hit_T_89 = _res_hit_T_86 & _res_hit_T_88; // @[PMP.scala:83:16, :88:5, :94:48] wire _res_hit_T_90 = _res_hit_T_80 & _res_hit_T_89; // @[PMP.scala:46:26, :94:48, :132:61] wire res_hit_6 = _res_hit_T_78 ? _res_hit_T_79 : _res_hit_T_90; // @[PMP.scala:45:20, :71:16, :132:{8,61}] wire _res_ignore_T_6 = ~io_pmp_1_cfg_l_0; // @[PMP.scala:143:7, :164:29] wire res_ignore_6 = default_0 & _res_ignore_T_6; // @[PMP.scala:156:56, :164:{26,29}] wire [31:0] _res_aligned_straddlesLowerBound_T_104 = ~_res_aligned_straddlesLowerBound_T_103; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesLowerBound_T_105 = {_res_aligned_straddlesLowerBound_T_104[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesLowerBound_T_106 = ~_res_aligned_straddlesLowerBound_T_105; // @[PMP.scala:60:{27,48}] wire [25:0] _res_aligned_straddlesLowerBound_T_107 = _res_aligned_straddlesLowerBound_T_106[31:6]; // @[PMP.scala:60:27, :123:67] wire [25:0] _res_aligned_straddlesLowerBound_T_108 = _res_aligned_straddlesLowerBound_T_102 ^ _res_aligned_straddlesLowerBound_T_107; // @[PMP.scala:123:{35,49,67}] wire _res_aligned_straddlesLowerBound_T_109 = _res_aligned_straddlesLowerBound_T_108 == 26'h0; // @[PMP.scala:80:52, :81:54, :123:{49,67,82}] wire [31:0] _res_aligned_straddlesLowerBound_T_111 = ~_res_aligned_straddlesLowerBound_T_110; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesLowerBound_T_112 = {_res_aligned_straddlesLowerBound_T_111[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesLowerBound_T_113 = ~_res_aligned_straddlesLowerBound_T_112; // @[PMP.scala:60:{27,48}] wire [5:0] _res_aligned_straddlesLowerBound_T_114 = _res_aligned_straddlesLowerBound_T_113[5:0]; // @[PMP.scala:60:27, :123:108] wire [5:0] _res_aligned_straddlesLowerBound_T_116 = ~_res_aligned_straddlesLowerBound_T_115; // @[PMP.scala:123:{127,129}] wire [5:0] _res_aligned_straddlesLowerBound_T_117 = _res_aligned_straddlesLowerBound_T_114 & _res_aligned_straddlesLowerBound_T_116; // @[PMP.scala:123:{108,125,127}] wire _res_aligned_straddlesLowerBound_T_118 = \|_res_aligned_straddlesLowerBound_T_117; // @[PMP.scala:123:{125,147}] wire res_aligned_straddlesLowerBound_6 = _res_aligned_straddlesLowerBound_T_109 & _res_aligned_straddlesLowerBound_T_118; // @[PMP.scala:123:{82,90,147}] wire [31:0] _res_aligned_straddlesUpperBound_T_104 = ~_res_aligned_straddlesUpperBound_T_103; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesUpperBound_T_105 = {_res_aligned_straddlesUpperBound_T_104[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesUpperBound_T_106 = ~_res_aligned_straddlesUpperBound_T_105; // @[PMP.scala:60:{27,48}] wire [25:0] _res_aligned_straddlesUpperBound_T_107 = _res_aligned_straddlesUpperBound_T_106[31:6]; // @[PMP.scala:60:27, :124:62] wire [25:0] _res_aligned_straddlesUpperBound_T_108 = _res_aligned_straddlesUpperBound_T_102 ^ _res_aligned_straddlesUpperBound_T_107; // @[PMP.scala:124:{35,49,62}] wire _res_aligned_straddlesUpperBound_T_109 = _res_aligned_straddlesUpperBound_T_108 == 26'h0; // @[PMP.scala:80:52, :81:54, :123:67, :124:{49,77}] wire [31:0] _res_aligned_straddlesUpperBound_T_111 = ~_res_aligned_straddlesUpperBound_T_110; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesUpperBound_T_112 = {_res_aligned_straddlesUpperBound_T_111[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesUpperBound_T_113 = ~_res_aligned_straddlesUpperBound_T_112; // @[PMP.scala:60:{27,48}] wire [5:0] _res_aligned_straddlesUpperBound_T_114 = _res_aligned_straddlesUpperBound_T_113[5:0]; // @[PMP.scala:60:27, :124:98] wire [5:0] _res_aligned_straddlesUpperBound_T_116 = _res_aligned_straddlesUpperBound_T_115; // @[PMP.scala:124:{119,136}] wire [5:0] _res_aligned_straddlesUpperBound_T_117 = _res_aligned_straddlesUpperBound_T_114 & _res_aligned_straddlesUpperBound_T_116; // @[PMP.scala:124:{98,115,136}] wire _res_aligned_straddlesUpperBound_T_118 = \|_res_aligned_straddlesUpperBound_T_117; // @[PMP.scala:124:{115,148}] wire res_aligned_straddlesUpperBound_6 = _res_aligned_straddlesUpperBound_T_109 & _res_aligned_straddlesUpperBound_T_118; // @[PMP.scala:124:{77,85,148}] wire _res_aligned_rangeAligned_T_6 = res_aligned_straddlesLowerBound_6 \| res_aligned_straddlesUpperBound_6; // @[PMP.scala:123:90, :124:85, :125:46] wire res_aligned_rangeAligned_6 = ~_res_aligned_rangeAligned_T_6; // @[PMP.scala:125:{24,46}] wire [5:0] _res_aligned_pow2Aligned_T_19 = ~_res_aligned_pow2Aligned_T_18; // @[PMP.scala:126:{34,39}] wire res_aligned_6 = _res_aligned_T_6 \| res_aligned_rangeAligned_6; // @[PMP.scala:45:20, :125:24, :127:8] wire _res_T_270 = io_pmp_1_cfg_a_0 == 2'h0; // @[PMP.scala:143:7, :168:32] wire _GEN_31 = io_pmp_1_cfg_a_0 == 2'h1; // @[PMP.scala:143:7, :168:32] wire _res_T_271; // @[PMP.scala:168:32] assign _res_T_271 = _GEN_31; // @[PMP.scala:168:32] wire _res_T_290; // @[PMP.scala:177:61] assign _res_T_290 = _GEN_31; // @[PMP.scala:168:32, :177:61] wire _res_T_294; // @[PMP.scala:178:63] assign _res_T_294 = _GEN_31; // @[PMP.scala:168:32, :178:63] wire _GEN_32 = io_pmp_1_cfg_a_0 == 2'h2; // @[PMP.scala:143:7, :168:32] wire _res_T_272; // @[PMP.scala:168:32] assign _res_T_272 = _GEN_32; // @[PMP.scala:168:32] wire _res_T_299; // @[PMP.scala:177:61] assign _res_T_299 = _GEN_32; // @[PMP.scala:168:32, :177:61] wire _res_T_303; // @[PMP.scala:178:63] assign _res_T_303 = _GEN_32; // @[PMP.scala:168:32, :178:63] wire _res_T_273 = &io_pmp_1_cfg_a_0; // @[PMP.scala:143:7, :168:32] wire [1:0] _GEN_33 = {io_pmp_1_cfg_x_0, io_pmp_1_cfg_w_0}; // @[PMP.scala:143:7, :174:26] wire [1:0] res_hi_36; // @[PMP.scala:174:26] assign res_hi_36 = _GEN_33; // @[PMP.scala:174:26] wire [1:0] res_hi_37; // @[PMP.scala:174:26] assign res_hi_37 = _GEN_33; // @[PMP.scala:174:26] wire [1:0] res_hi_38; // @[PMP.scala:174:26] assign res_hi_38 = _GEN_33; // @[PMP.scala:174:26] wire [1:0] res_hi_39; // @[PMP.scala:174:26] assign res_hi_39 = _GEN_33; // @[PMP.scala:174:26] wire [1:0] res_hi_40; // @[PMP.scala:174:26] assign res_hi_40 = _GEN_33; // @[PMP.scala:174:26] wire [1:0] res_hi_41; // @[PMP.scala:174:26] assign res_hi_41 = _GEN_33; // @[PMP.scala:174:26] wire [2:0] _res_T_275 = {res_hi_36, io_pmp_1_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_276 = _res_T_275 == 3'h0; // @[PMP.scala:143:7, :146:14, :174:{26,60}] wire [2:0] _res_T_277 = {res_hi_37, io_pmp_1_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_278 = _res_T_277 == 3'h1; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_279 = {res_hi_38, io_pmp_1_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_280 = _res_T_279 == 3'h3; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_281 = {res_hi_39, io_pmp_1_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_282 = _res_T_281 == 3'h4; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_283 = {res_hi_40, io_pmp_1_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_284 = _res_T_283 == 3'h5; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_285 = {res_hi_41, io_pmp_1_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_286 = &_res_T_285; // @[PMP.scala:174:{26,60}] wire _res_T_287 = ~res_ignore_6; // @[PMP.scala:164:26, :177:22] wire _res_T_288 = _res_T_287 & res_hit_6; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_289 = _res_T_288 & res_aligned_6; // @[PMP.scala:127:8, :177:{30,37}] wire _res_T_291 = _res_T_289 & _res_T_290; // @[PMP.scala:177:{37,48,61}] wire _GEN_34 = io_pmp_1_cfg_l_0 & res_hit_6; // @[PMP.scala:132:8, :143:7, :178:32] wire _res_T_292; // @[PMP.scala:178:32] assign _res_T_292 = _GEN_34; // @[PMP.scala:178:32] wire _res_T_301; // @[PMP.scala:178:32] assign _res_T_301 = _GEN_34; // @[PMP.scala:178:32] wire _res_T_310; // @[PMP.scala:178:32] assign _res_T_310 = _GEN_34; // @[PMP.scala:178:32] wire _res_T_293 = _res_T_292 & res_aligned_6; // @[PMP.scala:127:8, :178:{32,39}] wire _res_T_295 = _res_T_293 & _res_T_294; // @[PMP.scala:178:{39,50,63}] wire _res_T_296 = ~res_ignore_6; // @[PMP.scala:164:26, :177:22] wire _res_T_297 = _res_T_296 & res_hit_6; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_298 = _res_T_297 & res_aligned_6; // @[PMP.scala:127:8, :177:{30,37}] wire _res_T_300 = _res_T_298 & _res_T_299; // @[PMP.scala:177:{37,48,61}] wire _res_T_302 = _res_T_301 & res_aligned_6; // @[PMP.scala:127:8, :178:{32,39}] wire _res_T_304 = _res_T_302 & _res_T_303; // @[PMP.scala:178:{39,50,63}] wire _res_T_305 = ~res_ignore_6; // @[PMP.scala:164:26, :177:22] wire _res_T_306 = _res_T_305 & res_hit_6; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_307 = _res_T_306 & res_aligned_6; // @[PMP.scala:127:8, :177:{30,37}] wire _res_T_308 = &io_pmp_1_cfg_a_0; // @[PMP.scala:143:7, :168:32, :177:61] wire _res_T_309 = _res_T_307 & _res_T_308; // @[PMP.scala:177:{37,48,61}] wire _res_T_311 = _res_T_310 & res_aligned_6; // @[PMP.scala:127:8, :178:{32,39}] wire _res_T_312 = &io_pmp_1_cfg_a_0; // @[PMP.scala:143:7, :168:32, :178:63] wire _res_T_313 = _res_T_311 & _res_T_312; // @[PMP.scala:178:{39,50,63}] wire _res_cur_cfg_x_T_13; // @[PMP.scala:184:26] wire _res_cur_cfg_w_T_13; // @[PMP.scala:183:26] wire _res_cur_cfg_r_T_13; // @[PMP.scala:182:26] wire res_cur_6_cfg_x; // @[PMP.scala:181:23] wire res_cur_6_cfg_w; // @[PMP.scala:181:23] wire res_cur_6_cfg_r; // @[PMP.scala:181:23] wire _res_cur_cfg_r_T_12 = io_pmp_1_cfg_r_0 \| res_ignore_6; // @[PMP.scala:143:7, :164:26, :182:40] assign _res_cur_cfg_r_T_13 = res_aligned_6 & _res_cur_cfg_r_T_12; // @[PMP.scala:127:8, :182:{26,40}] assign res_cur_6_cfg_r = _res_cur_cfg_r_T_13; // @[PMP.scala:181:23, :182:26] wire _res_cur_cfg_w_T_12 = io_pmp_1_cfg_w_0 \| res_ignore_6; // @[PMP.scala:143:7, :164:26, :183:40] assign _res_cur_cfg_w_T_13 = res_aligned_6 & _res_cur_cfg_w_T_12; // @[PMP.scala:127:8, :183:{26,40}] assign res_cur_6_cfg_w = _res_cur_cfg_w_T_13; // @[PMP.scala:181:23, :183:26] wire _res_cur_cfg_x_T_12 = io_pmp_1_cfg_x_0 \| res_ignore_6; // @[PMP.scala:143:7, :164:26, :184:40] assign _res_cur_cfg_x_T_13 = res_aligned_6 & _res_cur_cfg_x_T_12; // @[PMP.scala:127:8, :184:{26,40}] assign res_cur_6_cfg_x = _res_cur_cfg_x_T_13; // @[PMP.scala:181:23, :184:26] wire _res_T_314_cfg_l = res_hit_6 ? res_cur_6_cfg_l : _res_T_269_cfg_l; // @[PMP.scala:132:8, :181:23, :185:8] wire [1:0] _res_T_314_cfg_a = res_hit_6 ? res_cur_6_cfg_a : _res_T_269_cfg_a; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_T_314_cfg_x = res_hit_6 ? res_cur_6_cfg_x : _res_T_269_cfg_x; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_T_314_cfg_w = res_hit_6 ? res_cur_6_cfg_w : _res_T_269_cfg_w; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_T_314_cfg_r = res_hit_6 ? res_cur_6_cfg_r : _res_T_269_cfg_r; // @[PMP.scala:132:8, :181:23, :185:8] wire [29:0] _res_T_314_addr = res_hit_6 ? res_cur_6_addr : _res_T_269_addr; // @[PMP.scala:132:8, :181:23, :185:8] wire [31:0] _res_T_314_mask = res_hit_6 ? res_cur_6_mask : _res_T_269_mask; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_hit_T_91 = io_pmp_0_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7] wire _res_aligned_T_7 = io_pmp_0_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7] wire [25:0] _res_hit_msbMatch_T_76 = io_pmp_0_mask_0[31:6]; // @[PMP.scala:68:26, :69:72, :143:7] wire [5:0] _res_aligned_pow2Aligned_T_21 = io_pmp_0_mask_0[5:0]; // @[PMP.scala:68:26, :126:39, :143:7] wire [31:0] _res_hit_msbMatch_T_72 = ~_res_hit_msbMatch_T_71; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbMatch_T_73 = {_res_hit_msbMatch_T_72[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbMatch_T_74 = ~_res_hit_msbMatch_T_73; // @[PMP.scala:60:{27,48}] wire [25:0] _res_hit_msbMatch_T_75 = _res_hit_msbMatch_T_74[31:6]; // @[PMP.scala:60:27, :69:53] wire [25:0] _res_hit_msbMatch_T_77 = _res_hit_msbMatch_T_70 ^ _res_hit_msbMatch_T_75; // @[PMP.scala:63:47, :69:{29,53}] wire [25:0] _res_hit_msbMatch_T_78 = ~_res_hit_msbMatch_T_76; // @[PMP.scala:63:54, :69:72] wire [25:0] _res_hit_msbMatch_T_79 = _res_hit_msbMatch_T_77 & _res_hit_msbMatch_T_78; // @[PMP.scala:63:{47,52,54}] wire res_hit_msbMatch_7 = _res_hit_msbMatch_T_79 == 26'h0; // @[PMP.scala:63:{52,58}, :80:52, :81:54, :123:67] wire [31:0] _res_hit_lsbMatch_T_72 = ~_res_hit_lsbMatch_T_71; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_lsbMatch_T_73 = {_res_hit_lsbMatch_T_72[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbMatch_T_74 = ~_res_hit_lsbMatch_T_73; // @[PMP.scala:60:{27,48}] wire [5:0] _res_hit_lsbMatch_T_75 = _res_hit_lsbMatch_T_74[5:0]; // @[PMP.scala:60:27, :70:55] wire [5:0] _res_hit_lsbMatch_T_76 = res_hit_lsbMask_7[5:0]; // @[PMP.scala:68:26, :70:80] wire [5:0] _res_hit_lsbMatch_T_77 = _res_hit_lsbMatch_T_70 ^ _res_hit_lsbMatch_T_75; // @[PMP.scala:63:47, :70:{28,55}] wire [5:0] _res_hit_lsbMatch_T_78 = ~_res_hit_lsbMatch_T_76; // @[PMP.scala:63:54, :70:80] wire [5:0] _res_hit_lsbMatch_T_79 = _res_hit_lsbMatch_T_77 & _res_hit_lsbMatch_T_78; // @[PMP.scala:63:{47,52,54}] wire res_hit_lsbMatch_7 = _res_hit_lsbMatch_T_79 == 6'h0; // @[PMP.scala:63:{52,58}] wire _res_hit_T_92 = res_hit_msbMatch_7 & res_hit_lsbMatch_7; // @[PMP.scala:63:58, :71:16] wire _res_hit_T_93 = io_pmp_0_cfg_a_0[0]; // @[PMP.scala:46:26, :143:7] wire [25:0] _res_hit_msbsEqual_T_104 = _res_hit_msbsEqual_T_98; // @[PMP.scala:81:{27,41}] wire res_hit_msbsEqual_14 = _res_hit_msbsEqual_T_104 == 26'h0; // @[PMP.scala:80:52, :81:{41,54,69}, :123:67] wire [5:0] _res_hit_lsbsLess_T_99 = _res_hit_lsbsLess_T_98; // @[PMP.scala:82:{25,42}] wire [31:0] _res_hit_msbsLess_T_92 = ~_res_hit_msbsLess_T_91; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsLess_T_93 = {_res_hit_msbsLess_T_92[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsLess_T_94 = ~_res_hit_msbsLess_T_93; // @[PMP.scala:60:{27,48}] wire [25:0] _res_hit_msbsLess_T_95 = _res_hit_msbsLess_T_94[31:6]; // @[PMP.scala:60:27, :80:52] wire res_hit_msbsLess_15 = _res_hit_msbsLess_T_90 < _res_hit_msbsLess_T_95; // @[PMP.scala:80:{25,39,52}] wire [31:0] _res_hit_msbsEqual_T_107 = ~_res_hit_msbsEqual_T_106; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsEqual_T_108 = {_res_hit_msbsEqual_T_107[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsEqual_T_109 = ~_res_hit_msbsEqual_T_108; // @[PMP.scala:60:{27,48}] wire [25:0] _res_hit_msbsEqual_T_110 = _res_hit_msbsEqual_T_109[31:6]; // @[PMP.scala:60:27, :81:54] wire [25:0] _res_hit_msbsEqual_T_111 = _res_hit_msbsEqual_T_105 ^ _res_hit_msbsEqual_T_110; // @[PMP.scala:81:{27,41,54}] wire res_hit_msbsEqual_15 = _res_hit_msbsEqual_T_111 == 26'h0; // @[PMP.scala:80:52, :81:{41,54,69}, :123:67] wire [5:0] _res_hit_lsbsLess_T_106 = _res_hit_lsbsLess_T_105; // @[PMP.scala:82:{25,42}] wire [31:0] _res_hit_lsbsLess_T_108 = ~_res_hit_lsbsLess_T_107; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_lsbsLess_T_109 = {_res_hit_lsbsLess_T_108[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbsLess_T_110 = ~_res_hit_lsbsLess_T_109; // @[PMP.scala:60:{27,48}] wire [5:0] _res_hit_lsbsLess_T_111 = _res_hit_lsbsLess_T_110[5:0]; // @[PMP.scala:60:27, :82:64] wire res_hit_lsbsLess_15 = _res_hit_lsbsLess_T_106 < _res_hit_lsbsLess_T_111; // @[PMP.scala:82:{42,53,64}] wire _res_hit_T_100 = res_hit_msbsEqual_15 & res_hit_lsbsLess_15; // @[PMP.scala:81:69, :82:53, :83:30] wire _res_hit_T_101 = res_hit_msbsLess_15 \| _res_hit_T_100; // @[PMP.scala:80:39, :83:{16,30}] wire _res_hit_T_102 = _res_hit_T_101; // @[PMP.scala:83:16, :94:48] wire _res_hit_T_103 = _res_hit_T_93 & _res_hit_T_102; // @[PMP.scala:46:26, :94:48, :132:61] wire res_hit_7 = _res_hit_T_91 ? _res_hit_T_92 : _res_hit_T_103; // @[PMP.scala:45:20, :71:16, :132:{8,61}] wire _res_ignore_T_7 = ~io_pmp_0_cfg_l_0; // @[PMP.scala:143:7, :164:29] wire res_ignore_7 = default_0 & _res_ignore_T_7; // @[PMP.scala:156:56, :164:{26,29}] wire [25:0] _res_aligned_straddlesLowerBound_T_125 = _res_aligned_straddlesLowerBound_T_119; // @[PMP.scala:123:{35,49}] wire _res_aligned_straddlesLowerBound_T_126 = _res_aligned_straddlesLowerBound_T_125 == 26'h0; // @[PMP.scala:80:52, :81:54, :123:{49,67,82}] wire [5:0] _res_aligned_straddlesLowerBound_T_133 = ~_res_aligned_straddlesLowerBound_T_132; // @[PMP.scala:123:{127,129}] wire [31:0] _res_aligned_straddlesUpperBound_T_121 = ~_res_aligned_straddlesUpperBound_T_120; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesUpperBound_T_122 = {_res_aligned_straddlesUpperBound_T_121[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesUpperBound_T_123 = ~_res_aligned_straddlesUpperBound_T_122; // @[PMP.scala:60:{27,48}] wire [25:0] _res_aligned_straddlesUpperBound_T_124 = _res_aligned_straddlesUpperBound_T_123[31:6]; // @[PMP.scala:60:27, :124:62] wire [25:0] _res_aligned_straddlesUpperBound_T_125 = _res_aligned_straddlesUpperBound_T_119 ^ _res_aligned_straddlesUpperBound_T_124; // @[PMP.scala:124:{35,49,62}] wire _res_aligned_straddlesUpperBound_T_126 = _res_aligned_straddlesUpperBound_T_125 == 26'h0; // @[PMP.scala:80:52, :81:54, :123:67, :124:{49,77}] wire [31:0] _res_aligned_straddlesUpperBound_T_128 = ~_res_aligned_straddlesUpperBound_T_127; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesUpperBound_T_129 = {_res_aligned_straddlesUpperBound_T_128[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesUpperBound_T_130 = ~_res_aligned_straddlesUpperBound_T_129; // @[PMP.scala:60:{27,48}] wire [5:0] _res_aligned_straddlesUpperBound_T_131 = _res_aligned_straddlesUpperBound_T_130[5:0]; // @[PMP.scala:60:27, :124:98] wire [5:0] _res_aligned_straddlesUpperBound_T_133 = _res_aligned_straddlesUpperBound_T_132; // @[PMP.scala:124:{119,136}] wire [5:0] _res_aligned_straddlesUpperBound_T_134 = _res_aligned_straddlesUpperBound_T_131 & _res_aligned_straddlesUpperBound_T_133; // @[PMP.scala:124:{98,115,136}] wire _res_aligned_straddlesUpperBound_T_135 = \|_res_aligned_straddlesUpperBound_T_134; // @[PMP.scala:124:{115,148}] wire res_aligned_straddlesUpperBound_7 = _res_aligned_straddlesUpperBound_T_126 & _res_aligned_straddlesUpperBound_T_135; // @[PMP.scala:124:{77,85,148}] wire _res_aligned_rangeAligned_T_7 = res_aligned_straddlesUpperBound_7; // @[PMP.scala:124:85, :125:46] wire res_aligned_rangeAligned_7 = ~_res_aligned_rangeAligned_T_7; // @[PMP.scala:125:{24,46}] wire [5:0] _res_aligned_pow2Aligned_T_22 = ~_res_aligned_pow2Aligned_T_21; // @[PMP.scala:126:{34,39}] wire res_aligned_7 = _res_aligned_T_7 \| res_aligned_rangeAligned_7; // @[PMP.scala:45:20, :125:24, :127:8] wire _res_T_315 = io_pmp_0_cfg_a_0 == 2'h0; // @[PMP.scala:143:7, :168:32] wire _GEN_35 = io_pmp_0_cfg_a_0 == 2'h1; // @[PMP.scala:143:7, :168:32] wire _res_T_316; // @[PMP.scala:168:32] assign _res_T_316 = _GEN_35; // @[PMP.scala:168:32] wire _res_T_335; // @[PMP.scala:177:61] assign _res_T_335 = _GEN_35; // @[PMP.scala:168:32, :177:61] wire _res_T_339; // @[PMP.scala:178:63] assign _res_T_339 = _GEN_35; // @[PMP.scala:168:32, :178:63] wire _GEN_36 = io_pmp_0_cfg_a_0 == 2'h2; // @[PMP.scala:143:7, :168:32] wire _res_T_317; // @[PMP.scala:168:32] assign _res_T_317 = _GEN_36; // @[PMP.scala:168:32] wire _res_T_344; // @[PMP.scala:177:61] assign _res_T_344 = _GEN_36; // @[PMP.scala:168:32, :177:61] wire _res_T_348; // @[PMP.scala:178:63] assign _res_T_348 = _GEN_36; // @[PMP.scala:168:32, :178:63] wire _res_T_318 = &io_pmp_0_cfg_a_0; // @[PMP.scala:143:7, :168:32] wire [1:0] _GEN_37 = {io_pmp_0_cfg_x_0, io_pmp_0_cfg_w_0}; // @[PMP.scala:143:7, :174:26] wire [1:0] res_hi_42; // @[PMP.scala:174:26] assign res_hi_42 = _GEN_37; // @[PMP.scala:174:26] wire [1:0] res_hi_43; // @[PMP.scala:174:26] assign res_hi_43 = _GEN_37; // @[PMP.scala:174:26] wire [1:0] res_hi_44; // @[PMP.scala:174:26] assign res_hi_44 = _GEN_37; // @[PMP.scala:174:26] wire [1:0] res_hi_45; // @[PMP.scala:174:26] assign res_hi_45 = _GEN_37; // @[PMP.scala:174:26] wire [1:0] res_hi_46; // @[PMP.scala:174:26] assign res_hi_46 = _GEN_37; // @[PMP.scala:174:26] wire [1:0] res_hi_47; // @[PMP.scala:174:26] assign res_hi_47 = _GEN_37; // @[PMP.scala:174:26] wire [2:0] _res_T_320 = {res_hi_42, io_pmp_0_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_321 = _res_T_320 == 3'h0; // @[PMP.scala:143:7, :146:14, :174:{26,60}] wire [2:0] _res_T_322 = {res_hi_43, io_pmp_0_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_323 = _res_T_322 == 3'h1; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_324 = {res_hi_44, io_pmp_0_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_325 = _res_T_324 == 3'h3; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_326 = {res_hi_45, io_pmp_0_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_327 = _res_T_326 == 3'h4; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_328 = {res_hi_46, io_pmp_0_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_329 = _res_T_328 == 3'h5; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_330 = {res_hi_47, io_pmp_0_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_331 = &_res_T_330; // @[PMP.scala:174:{26,60}] wire _res_T_332 = ~res_ignore_7; // @[PMP.scala:164:26, :177:22] wire _res_T_333 = _res_T_332 & res_hit_7; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_334 = _res_T_333 & res_aligned_7; // @[PMP.scala:127:8, :177:{30,37}] wire _res_T_336 = _res_T_334 & _res_T_335; // @[PMP.scala:177:{37,48,61}] wire _GEN_38 = io_pmp_0_cfg_l_0 & res_hit_7; // @[PMP.scala:132:8, :143:7, :178:32] wire _res_T_337; // @[PMP.scala:178:32] assign _res_T_337 = _GEN_38; // @[PMP.scala:178:32] wire _res_T_346; // @[PMP.scala:178:32] assign _res_T_346 = _GEN_38; // @[PMP.scala:178:32] wire _res_T_355; // @[PMP.scala:178:32] assign _res_T_355 = _GEN_38; // @[PMP.scala:178:32] wire _res_T_338 = _res_T_337 & res_aligned_7; // @[PMP.scala:127:8, :178:{32,39}] wire _res_T_340 = _res_T_338 & _res_T_339; // @[PMP.scala:178:{39,50,63}] wire _res_T_341 = ~res_ignore_7; // @[PMP.scala:164:26, :177:22] wire _res_T_342 = _res_T_341 & res_hit_7; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_343 = _res_T_342 & res_aligned_7; // @[PMP.scala:127:8, :177:{30,37}] wire _res_T_345 = _res_T_343 & _res_T_344; // @[PMP.scala:177:{37,48,61}] wire _res_T_347 = _res_T_346 & res_aligned_7; // @[PMP.scala:127:8, :178:{32,39}] wire _res_T_349 = _res_T_347 & _res_T_348; // @[PMP.scala:178:{39,50,63}] wire _res_T_350 = ~res_ignore_7; // @[PMP.scala:164:26, :177:22] wire _res_T_351 = _res_T_350 & res_hit_7; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_352 = _res_T_351 & res_aligned_7; // @[PMP.scala:127:8, :177:{30,37}] wire _res_T_353 = &io_pmp_0_cfg_a_0; // @[PMP.scala:143:7, :168:32, :177:61] wire _res_T_354 = _res_T_352 & _res_T_353; // @[PMP.scala:177:{37,48,61}] wire _res_T_356 = _res_T_355 & res_aligned_7; // @[PMP.scala:127:8, :178:{32,39}] wire _res_T_357 = &io_pmp_0_cfg_a_0; // @[PMP.scala:143:7, :168:32, :178:63] wire _res_T_358 = _res_T_356 & _res_T_357; // @[PMP.scala:178:{39,50,63}] wire _res_cur_cfg_x_T_15; // @[PMP.scala:184:26] wire _res_cur_cfg_w_T_15; // @[PMP.scala:183:26] wire _res_cur_cfg_r_T_15; // @[PMP.scala:182:26] wire res_cur_7_cfg_x; // @[PMP.scala:181:23] wire res_cur_7_cfg_w; // @[PMP.scala:181:23] wire res_cur_7_cfg_r; // @[PMP.scala:181:23] wire _res_cur_cfg_r_T_14 = io_pmp_0_cfg_r_0 \| res_ignore_7; // @[PMP.scala:143:7, :164:26, :182:40] assign _res_cur_cfg_r_T_15 = res_aligned_7 & _res_cur_cfg_r_T_14; // @[PMP.scala:127:8, :182:{26,40}] assign res_cur_7_cfg_r = _res_cur_cfg_r_T_15; // @[PMP.scala:181:23, :182:26] wire _res_cur_cfg_w_T_14 = io_pmp_0_cfg_w_0 \| res_ignore_7; // @[PMP.scala:143:7, :164:26, :183:40] assign _res_cur_cfg_w_T_15 = res_aligned_7 & _res_cur_cfg_w_T_14; // @[PMP.scala:127:8, :183:{26,40}] assign res_cur_7_cfg_w = _res_cur_cfg_w_T_15; // @[PMP.scala:181:23, :183:26] wire _res_cur_cfg_x_T_14 = io_pmp_0_cfg_x_0 \| res_ignore_7; // @[PMP.scala:143:7, :164:26, :184:40] assign _res_cur_cfg_x_T_15 = res_aligned_7 & _res_cur_cfg_x_T_14; // @[PMP.scala:127:8, :184:{26,40}] assign res_cur_7_cfg_x = _res_cur_cfg_x_T_15; // @[PMP.scala:181:23, :184:26] wire res_cfg_l = res_hit_7 ? res_cur_7_cfg_l : _res_T_314_cfg_l; // @[PMP.scala:132:8, :181:23, :185:8] wire [1:0] res_cfg_a = res_hit_7 ? res_cur_7_cfg_a : _res_T_314_cfg_a; // @[PMP.scala:132:8, :181:23, :185:8] assign res_cfg_x = res_hit_7 ? res_cur_7_cfg_x : _res_T_314_cfg_x; // @[PMP.scala:132:8, :181:23, :185:8] assign res_cfg_w = res_hit_7 ? res_cur_7_cfg_w : _res_T_314_cfg_w; // @[PMP.scala:132:8, :181:23, :185:8] assign res_cfg_r = res_hit_7 ? res_cur_7_cfg_r : _res_T_314_cfg_r; // @[PMP.scala:132:8, :181:23, :185:8] wire [29:0] res_addr = res_hit_7 ? res_cur_7_addr : _res_T_314_addr; // @[PMP.scala:132:8, :181:23, :185:8] wire [31:0] res_mask = res_hit_7 ? res_cur_7_mask : _res_T_314_mask; // @[PMP.scala:132:8, :181:23, :185:8] assign io_x_0 = res_cfg_x; // @[PMP.scala:143:7, :185:8] assign io_w_0 = res_cfg_w; // @[PMP.scala:143:7, :185:8] assign io_r_0 = res_cfg_r; // @[PMP.scala:143:7, :185:8] assign io_r = io_r_0; // @[PMP.scala:143:7] assign io_w = io_w_0; // @[PMP.scala:143:7] assign io_x = io_x_0; // @[PMP.scala:143:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File CompareRecFN.scala: /============================================================================ This Chisel source file is part of a pre-release version of the HardFloat IEEE Floating-Point Arithmetic Package, by John R. Hauser (with some contributions from Yunsup Lee and Andrew Waterman, mainly concerning testing). Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of California. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions, and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions, and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the University nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. =============================================================================/ package hardfloat import chisel3._ class CompareRecFN(expWidth: Int, sigWidth: Int) extends RawModule { val io = IO(new Bundle { val a = Input(Bits((expWidth + sigWidth + 1).W)) val b = Input(Bits((expWidth + sigWidth + 1).W)) val signaling = Input(Bool()) val lt = Output(Bool()) val eq = Output(Bool()) val gt = Output(Bool()) val exceptionFlags = Output(Bits(5.W)) }) val rawA = rawFloatFromRecFN(expWidth, sigWidth, io.a) val rawB = rawFloatFromRecFN(expWidth, sigWidth, io.b) val ordered = ! rawA.isNaN && ! rawB.isNaN val bothInfs = rawA.isInf && rawB.isInf val bothZeros = rawA.isZero && rawB.isZero val eqExps = (rawA.sExp === rawB.sExp) val common_ltMags = (rawA.sExp < rawB.sExp) \|\| (eqExps && (rawA.sig < rawB.sig)) val common_eqMags = eqExps && (rawA.sig === rawB.sig) val ordered_lt = ! bothZeros && ((rawA.sign && ! rawB.sign) \|\| (! bothInfs && ((rawA.sign && ! common_ltMags && ! common_eqMags) \|\| (! rawB.sign && common_ltMags)))) val ordered_eq = bothZeros \|\| ((rawA.sign === rawB.sign) && (bothInfs \|\| common_eqMags)) val invalid = isSigNaNRawFloat(rawA) \|\| isSigNaNRawFloat(rawB) \|\| (io.signaling && ! ordered) io.lt := ordered && ordered_lt io.eq := ordered && ordered_eq io.gt := ordered && ! ordered_lt && ! ordered_eq io.exceptionFlags := invalid ## 0.U(4.W) } File rawFloatFromRecFN.scala: /============================================================================ This Chisel source file is part of a pre-release version of the HardFloat IEEE Floating-Point Arithmetic Package, by John R. Hauser (with some contributions from Yunsup Lee and Andrew Waterman, mainly concerning testing). Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of California. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions, and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions, and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the University nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. =============================================================================/ package hardfloat import chisel3._ import chisel3.util._ /---------------------------------------------------------------------------- \| In the result, no more than one of 'isNaN', 'isInf', and 'isZero' will be \| set. ----------------------------------------------------------------------------*/ object rawFloatFromRecFN { def apply(expWidth: Int, sigWidth: Int, in: Bits): RawFloat = { val exp = in(expWidth + sigWidth - 1, sigWidth - 1) val isZero = exp(expWidth, expWidth - 2) === 0.U val isSpecial = exp(expWidth, expWidth - 1) === 3.U val out = Wire(new RawFloat(expWidth, sigWidth)) out.isNaN := isSpecial && exp(expWidth - 2) out.isInf := isSpecial && ! exp(expWidth - 2) out.isZero := isZero out.sign := in(expWidth + sigWidth) out.sExp := exp.zext out.sig := 0.U(1.W) ## ! isZero ## in(sigWidth - 2, 0) out } }	module CompareRecFN_5( // @[CompareRecFN.scala:42:7] input [64:0] io_a, // @[CompareRecFN.scala:44:16] input [64:0] io_b, // @[CompareRecFN.scala:44:16] input io_signaling, // @[CompareRecFN.scala:44:16] output io_lt, // @[CompareRecFN.scala:44:16] output io_eq, // @[CompareRecFN.scala:44:16] output [4:0] io_exceptionFlags // @[CompareRecFN.scala:44:16] ); wire [64:0] io_a_0 = io_a; // @[CompareRecFN.scala:42:7] wire [64:0] io_b_0 = io_b; // @[CompareRecFN.scala:42:7] wire io_signaling_0 = io_signaling; // @[CompareRecFN.scala:42:7] wire _io_lt_T; // @[CompareRecFN.scala:78:22] wire _io_eq_T; // @[CompareRecFN.scala:79:22] wire _io_gt_T_3; // @[CompareRecFN.scala:80:38] wire [4:0] _io_exceptionFlags_T; // @[CompareRecFN.scala:81:34] wire io_lt_0; // @[CompareRecFN.scala:42:7] wire io_eq_0; // @[CompareRecFN.scala:42:7] wire io_gt; // @[CompareRecFN.scala:42:7] wire [4:0] io_exceptionFlags_0; // @[CompareRecFN.scala:42:7] wire [11:0] rawA_exp = io_a_0[63:52]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _rawA_isZero_T = rawA_exp[11:9]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire rawA_isZero = _rawA_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire rawA_isZero_0 = rawA_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _rawA_isSpecial_T = rawA_exp[11:10]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire rawA_isSpecial = &_rawA_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _rawA_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33] wire _rawA_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33] wire _rawA_out_sign_T; // @[rawFloatFromRecFN.scala:59:25] wire [12:0] _rawA_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27] wire [53:0] _rawA_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44] wire rawA_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire rawA_isInf; // @[rawFloatFromRecFN.scala:55:23] wire rawA_sign; // @[rawFloatFromRecFN.scala:55:23] wire [12:0] rawA_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [53:0] rawA_sig; // @[rawFloatFromRecFN.scala:55:23] wire _rawA_out_isNaN_T = rawA_exp[9]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _rawA_out_isInf_T = rawA_exp[9]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _rawA_out_isNaN_T_1 = rawA_isSpecial & _rawA_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign rawA_isNaN = _rawA_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _rawA_out_isInf_T_1 = ~_rawA_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _rawA_out_isInf_T_2 = rawA_isSpecial & _rawA_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign rawA_isInf = _rawA_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _rawA_out_sign_T = io_a_0[64]; // @[rawFloatFromRecFN.scala:59:25] assign rawA_sign = _rawA_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _rawA_out_sExp_T = {1'h0, rawA_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign rawA_sExp = _rawA_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _rawA_out_sig_T = ~rawA_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _rawA_out_sig_T_1 = {1'h0, _rawA_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [51:0] _rawA_out_sig_T_2 = io_a_0[51:0]; // @[rawFloatFromRecFN.scala:61:49] assign _rawA_out_sig_T_3 = {_rawA_out_sig_T_1, _rawA_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign rawA_sig = _rawA_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire [11:0] rawB_exp = io_b_0[63:52]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _rawB_isZero_T = rawB_exp[11:9]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire rawB_isZero = _rawB_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire rawB_isZero_0 = rawB_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _rawB_isSpecial_T = rawB_exp[11:10]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire rawB_isSpecial = &_rawB_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _rawB_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33] wire _rawB_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33] wire _rawB_out_sign_T; // @[rawFloatFromRecFN.scala:59:25] wire [12:0] _rawB_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27] wire [53:0] _rawB_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44] wire rawB_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire rawB_isInf; // @[rawFloatFromRecFN.scala:55:23] wire rawB_sign; // @[rawFloatFromRecFN.scala:55:23] wire [12:0] rawB_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [53:0] rawB_sig; // @[rawFloatFromRecFN.scala:55:23] wire _rawB_out_isNaN_T = rawB_exp[9]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _rawB_out_isInf_T = rawB_exp[9]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _rawB_out_isNaN_T_1 = rawB_isSpecial & _rawB_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign rawB_isNaN = _rawB_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _rawB_out_isInf_T_1 = ~_rawB_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _rawB_out_isInf_T_2 = rawB_isSpecial & _rawB_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign rawB_isInf = _rawB_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _rawB_out_sign_T = io_b_0[64]; // @[rawFloatFromRecFN.scala:59:25] assign rawB_sign = _rawB_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _rawB_out_sExp_T = {1'h0, rawB_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign rawB_sExp = _rawB_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _rawB_out_sig_T = ~rawB_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _rawB_out_sig_T_1 = {1'h0, _rawB_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [51:0] _rawB_out_sig_T_2 = io_b_0[51:0]; // @[rawFloatFromRecFN.scala:61:49] assign _rawB_out_sig_T_3 = {_rawB_out_sig_T_1, _rawB_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign rawB_sig = _rawB_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire _ordered_T = ~rawA_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire _ordered_T_1 = ~rawB_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire ordered = _ordered_T & _ordered_T_1; // @[CompareRecFN.scala:57:{19,32,35}] wire bothInfs = rawA_isInf & rawB_isInf; // @[rawFloatFromRecFN.scala:55:23] wire bothZeros = rawA_isZero_0 & rawB_isZero_0; // @[rawFloatFromRecFN.scala:55:23] wire eqExps = rawA_sExp == rawB_sExp; // @[rawFloatFromRecFN.scala:55:23] wire _common_ltMags_T = $signed(rawA_sExp) < $signed(rawB_sExp); // @[rawFloatFromRecFN.scala:55:23] wire _common_ltMags_T_1 = rawA_sig < rawB_sig; // @[rawFloatFromRecFN.scala:55:23] wire _common_ltMags_T_2 = eqExps & _common_ltMags_T_1; // @[CompareRecFN.scala:60:29, :62:{44,57}] wire common_ltMags = _common_ltMags_T \| _common_ltMags_T_2; // @[CompareRecFN.scala:62:{20,33,44}] wire _common_eqMags_T = rawA_sig == rawB_sig; // @[rawFloatFromRecFN.scala:55:23] wire common_eqMags = eqExps & _common_eqMags_T; // @[CompareRecFN.scala:60:29, :63:{32,45}] wire _ordered_lt_T = ~bothZeros; // @[CompareRecFN.scala:59:33, :66:9] wire _ordered_lt_T_1 = ~rawB_sign; // @[rawFloatFromRecFN.scala:55:23] wire _ordered_lt_T_2 = rawA_sign & _ordered_lt_T_1; // @[rawFloatFromRecFN.scala:55:23] wire _ordered_lt_T_3 = ~bothInfs; // @[CompareRecFN.scala:58:33, :68:19] wire _ordered_lt_T_4 = ~common_ltMags; // @[CompareRecFN.scala:62:33, :69:38] wire _ordered_lt_T_5 = rawA_sign & _ordered_lt_T_4; // @[rawFloatFromRecFN.scala:55:23] wire _ordered_lt_T_6 = ~common_eqMags; // @[CompareRecFN.scala:63:32, :69:57] wire _ordered_lt_T_7 = _ordered_lt_T_5 & _ordered_lt_T_6; // @[CompareRecFN.scala:69:{35,54,57}] wire _ordered_lt_T_8 = ~rawB_sign; // @[rawFloatFromRecFN.scala:55:23] wire _ordered_lt_T_9 = _ordered_lt_T_8 & common_ltMags; // @[CompareRecFN.scala:62:33, :70:{29,41}] wire _ordered_lt_T_10 = _ordered_lt_T_7 \| _ordered_lt_T_9; // @[CompareRecFN.scala:69:{54,74}, :70:41] wire _ordered_lt_T_11 = _ordered_lt_T_3 & _ordered_lt_T_10; // @[CompareRecFN.scala:68:{19,30}, :69:74] wire _ordered_lt_T_12 = _ordered_lt_T_2 \| _ordered_lt_T_11; // @[CompareRecFN.scala:67:{25,41}, :68:30] wire ordered_lt = _ordered_lt_T & _ordered_lt_T_12; // @[CompareRecFN.scala:66:{9,21}, :67:41] wire _ordered_eq_T = rawA_sign == rawB_sign; // @[rawFloatFromRecFN.scala:55:23] wire _ordered_eq_T_1 = bothInfs \| common_eqMags; // @[CompareRecFN.scala:58:33, :63:32, :72:62] wire _ordered_eq_T_2 = _ordered_eq_T & _ordered_eq_T_1; // @[CompareRecFN.scala:72:{34,49,62}] wire ordered_eq = bothZeros \| _ordered_eq_T_2; // @[CompareRecFN.scala:59:33, :72:{19,49}] wire _invalid_T = rawA_sig[51]; // @[rawFloatFromRecFN.scala:55:23] wire _invalid_T_1 = ~_invalid_T; // @[common.scala:82:{49,56}] wire _invalid_T_2 = rawA_isNaN & _invalid_T_1; // @[rawFloatFromRecFN.scala:55:23] wire _invalid_T_3 = rawB_sig[51]; // @[rawFloatFromRecFN.scala:55:23] wire _invalid_T_4 = ~_invalid_T_3; // @[common.scala:82:{49,56}] wire _invalid_T_5 = rawB_isNaN & _invalid_T_4; // @[rawFloatFromRecFN.scala:55:23] wire _invalid_T_6 = _invalid_T_2 \| _invalid_T_5; // @[common.scala:82:46] wire _invalid_T_7 = ~ordered; // @[CompareRecFN.scala:57:32, :76:30] wire _invalid_T_8 = io_signaling_0 & _invalid_T_7; // @[CompareRecFN.scala:42:7, :76:{27,30}] wire invalid = _invalid_T_6 \| _invalid_T_8; // @[CompareRecFN.scala:75:{32,58}, :76:27] assign _io_lt_T = ordered & ordered_lt; // @[CompareRecFN.scala:57:32, :66:21, :78:22] assign io_lt_0 = _io_lt_T; // @[CompareRecFN.scala:42:7, :78:22] assign _io_eq_T = ordered & ordered_eq; // @[CompareRecFN.scala:57:32, :72:19, :79:22] assign io_eq_0 = _io_eq_T; // @[CompareRecFN.scala:42:7, :79:22] wire _io_gt_T = ~ordered_lt; // @[CompareRecFN.scala:66:21, :80:25] wire _io_gt_T_1 = ordered & _io_gt_T; // @[CompareRecFN.scala:57:32, :80:{22,25}] wire _io_gt_T_2 = ~ordered_eq; // @[CompareRecFN.scala:72:19, :80:41] assign _io_gt_T_3 = _io_gt_T_1 & _io_gt_T_2; // @[CompareRecFN.scala:80:{22,38,41}] assign io_gt = _io_gt_T_3; // @[CompareRecFN.scala:42:7, :80:38] assign _io_exceptionFlags_T = {invalid, 4'h0}; // @[CompareRecFN.scala:75:58, :81:34] assign io_exceptionFlags_0 = _io_exceptionFlags_T; // @[CompareRecFN.scala:42:7, :81:34] assign io_lt = io_lt_0; // @[CompareRecFN.scala:42:7] assign io_eq = io_eq_0; // @[CompareRecFN.scala:42:7] assign io_exceptionFlags = io_exceptionFlags_0; // @[CompareRecFN.scala:42:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File Monitor.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceLine import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import freechips.rocketchip.diplomacy.EnableMonitors import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode} import freechips.rocketchip.util.PlusArg case class TLMonitorArgs(edge: TLEdge) abstract class TLMonitorBase(args: TLMonitorArgs) extends Module { val io = IO(new Bundle { val in = Input(new TLBundle(args.edge.bundle)) }) def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit legalize(io.in, args.edge, reset) } object TLMonitor { def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = { if (enable) { EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) } } else { node } } } class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args) { require (args.edge.params(TLMonitorStrictMode) \|\| (! args.edge.params(TestplanTestType).formal)) val cover_prop_class = PropertyClass.Default //Like assert but can flip to being an assumption for formal verification def monAssert(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir, cond, message, PropertyClass.Default) } def assume(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir.flip, cond, message, PropertyClass.Default) } def extra = { args.edge.sourceInfo match { case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)" case _ => "" } } def visible(address: UInt, source: UInt, edge: TLEdge) = edge.client.clients.map { c => !c.sourceId.contains(source) \|\| c.visibility.map(_.contains(address)).reduce(_ \|\| _) }.reduce(_ && _) def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = { //switch this flag to turn on diplomacy in error messages def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n" monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra) // Reuse these subexpressions to save some firrtl lines val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility") //The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B //TODO: check for acquireT? when (bundle.opcode === TLMessages.AcquireBlock) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra) } when (bundle.opcode === TLMessages.AcquirePerm) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra) monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra) monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra) monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra) } } def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = { monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra) monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility") // Reuse these subexpressions to save some firrtl lines val address_ok = edge.manager.containsSafe(edge.address(bundle)) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source when (bundle.opcode === TLMessages.Probe) { assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra) assume (address_ok, "'B' channel Probe carries unmanaged address" + extra) assume (legal_source, "'B' channel Probe carries source that is not first source" + extra) assume (is_aligned, "'B' channel Probe address not aligned to size" + extra) assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra) assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra) assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra) monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra) monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra) monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra) monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra) } } def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = { monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val address_ok = edge.manager.containsSafe(edge.address(bundle)) monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility") when (bundle.opcode === TLMessages.ProbeAck) { monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra) } when (bundle.opcode === TLMessages.ProbeAckData) { monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.Release) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra) monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra) } when (bundle.opcode === TLMessages.ReleaseData) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.AccessAck) { monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra) } when (bundle.opcode === TLMessages.HintAck) { monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra) } } def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = { assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val sink_ok = bundle.sink < edge.manager.endSinkId.U val deny_put_ok = edge.manager.mayDenyPut.B val deny_get_ok = edge.manager.mayDenyGet.B when (bundle.opcode === TLMessages.ReleaseAck) { assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra) assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra) assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra) } when (bundle.opcode === TLMessages.Grant) { assume (source_ok, "'D' channel Grant carries invalid source ID" + extra) assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra) assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel Grant is denied" + extra) } when (bundle.opcode === TLMessages.GrantData) { assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra) assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra) assume (!bundle.denied \|\| bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra) assume (deny_get_ok \|\| !bundle.denied, "'D' channel GrantData is denied" + extra) } when (bundle.opcode === TLMessages.AccessAck) { assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel AccessAck is denied" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra) assume (!bundle.denied \|\| bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra) assume (deny_get_ok \|\| !bundle.denied, "'D' channel AccessAckData is denied" + extra) } when (bundle.opcode === TLMessages.HintAck) { assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel HintAck is denied" + extra) } } def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = { val sink_ok = bundle.sink < edge.manager.endSinkId.U monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra) } def legalizeFormat(bundle: TLBundle, edge: TLEdge) = { when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) } when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) } when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) } when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) } } else { monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra) monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra) monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra) } } def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = { val a_first = edge.first(a.bits, a.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (a.valid && !a_first) { monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra) monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra) monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra) monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra) monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra) } when (a.fire && a_first) { opcode := a.bits.opcode param := a.bits.param size := a.bits.size source := a.bits.source address := a.bits.address } } def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = { val b_first = edge.first(b.bits, b.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (b.valid && !b_first) { monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra) monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra) monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra) monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra) monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra) } when (b.fire && b_first) { opcode := b.bits.opcode param := b.bits.param size := b.bits.size source := b.bits.source address := b.bits.address } } def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = { // Symbolic variable val sym_source = Wire(UInt(edge.client.endSourceId.W)) // TODO: Connect sym_source to a fixed value for simulation and to a // free wire in formal sym_source := 0.U // Type casting Int to UInt val maxSourceId = Wire(UInt(edge.client.endSourceId.W)) maxSourceId := edge.client.endSourceId.U // Delayed verison of sym_source val sym_source_d = Reg(UInt(edge.client.endSourceId.W)) sym_source_d := sym_source // These will be constraints for FV setup Property( MonitorDirection.Monitor, (sym_source === sym_source_d), "sym_source should remain stable", PropertyClass.Default) Property( MonitorDirection.Monitor, (sym_source <= maxSourceId), "sym_source should take legal value", PropertyClass.Default) val my_resp_pend = RegInit(false.B) val my_opcode = Reg(UInt()) val my_size = Reg(UInt()) val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire) val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire) val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source) val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source) val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat) val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend) when (my_set_resp_pend) { my_resp_pend := true.B } .elsewhen (my_clr_resp_pend) { my_resp_pend := false.B } when (my_a_first_beat) { my_opcode := bundle.a.bits.opcode my_size := bundle.a.bits.size } val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size) val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode) val my_resp_opcode_legal = Wire(Bool()) when ((my_resp_opcode === TLMessages.Get) \|\| (my_resp_opcode === TLMessages.ArithmeticData) \|\| (my_resp_opcode === TLMessages.LogicalData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData) } .elsewhen ((my_resp_opcode === TLMessages.PutFullData) \|\| (my_resp_opcode === TLMessages.PutPartialData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck) } .otherwise { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck) } monAssert (IfThen(my_resp_pend, !my_a_first_beat), "Request message should not be sent with a source ID, for which a response message" + "is already pending (not received until current cycle) for a prior request message" + "with the same source ID" + extra) assume (IfThen(my_clr_resp_pend, (my_set_resp_pend \|\| my_resp_pend)), "Response message should be accepted with a source ID only if a request message with the" + "same source ID has been accepted or is being accepted in the current cycle" + extra) assume (IfThen(my_d_first_beat, (my_a_first_beat \|\| my_resp_pend)), "Response message should be sent with a source ID only if a request message with the" + "same source ID has been accepted or is being sent in the current cycle" + extra) assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)), "If d_valid is 1, then d_size should be same as a_size of the corresponding request" + "message" + extra) assume (IfThen(my_d_first_beat, my_resp_opcode_legal), "If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" + "request message" + extra) } def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = { val c_first = edge.first(c.bits, c.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (c.valid && !c_first) { monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra) monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra) monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra) monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra) monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra) } when (c.fire && c_first) { opcode := c.bits.opcode param := c.bits.param size := c.bits.size source := c.bits.source address := c.bits.address } } def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = { val d_first = edge.first(d.bits, d.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val sink = Reg(UInt()) val denied = Reg(Bool()) when (d.valid && !d_first) { assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra) assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra) assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra) assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra) assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra) assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra) } when (d.fire && d_first) { opcode := d.bits.opcode param := d.bits.param size := d.bits.size source := d.bits.source sink := d.bits.sink denied := d.bits.denied } } def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = { legalizeMultibeatA(bundle.a, edge) legalizeMultibeatD(bundle.d, edge) if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { legalizeMultibeatB(bundle.b, edge) legalizeMultibeatC(bundle.c, edge) } } //This is left in for almond which doesn't adhere to the tilelink protocol @deprecated("Use legalizeADSource instead if possible","") def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.client.endSourceId.W)) val a_first = edge.first(bundle.a.bits, bundle.a.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val a_set = WireInit(0.U(edge.client.endSourceId.W)) when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) assume((a_set \| inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra) } if (edge.manager.minLatency > 0) { assume(a_set =/= d_clr \|\| !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight \| a_set) & ~d_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") assert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = { val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size) val log_a_size_bus_size = log2Ceil(a_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error inflight.suggestName("inflight") val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) inflight_opcodes.suggestName("inflight_opcodes") val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) inflight_sizes.suggestName("inflight_sizes") val a_first = edge.first(bundle.a.bits, bundle.a.fire) a_first.suggestName("a_first") val d_first = edge.first(bundle.d.bits, bundle.d.fire) d_first.suggestName("d_first") val a_set = WireInit(0.U(edge.client.endSourceId.W)) val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) a_set.suggestName("a_set") a_set_wo_ready.suggestName("a_set_wo_ready") val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) a_opcodes_set.suggestName("a_opcodes_set") val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) a_sizes_set.suggestName("a_sizes_set") val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W)) a_opcode_lookup.suggestName("a_opcode_lookup") a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W)) a_size_lookup.suggestName("a_size_lookup") a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant)) val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant)) val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W)) a_opcodes_set_interm.suggestName("a_opcodes_set_interm") val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W)) a_sizes_set_interm.suggestName("a_sizes_set_interm") when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) { a_set_wo_ready := UIntToOH(bundle.a.bits.source) } when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) \| 1.U a_sizes_set_interm := (bundle.a.bits.size << 1.U) \| 1.U a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U) a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U) monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) d_opcodes_clr.suggestName("d_opcodes_clr") val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) \|\| same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) \|\| (bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra) assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) \|\| (bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra) assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) { assume((!bundle.d.ready) \|\| bundle.a.ready, "ready check") } if (edge.manager.minLatency > 0) { assume(a_set_wo_ready =/= d_clr_wo_ready \|\| !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight \| a_set) & ~d_clr inflight_opcodes := (inflight_opcodes \| a_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes \| a_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = { val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size) val log_c_size_bus_size = log2Ceil(c_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) inflight.suggestName("inflight") inflight_opcodes.suggestName("inflight_opcodes") inflight_sizes.suggestName("inflight_sizes") val c_first = edge.first(bundle.c.bits, bundle.c.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) c_first.suggestName("c_first") d_first.suggestName("d_first") val c_set = WireInit(0.U(edge.client.endSourceId.W)) val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) c_set.suggestName("c_set") c_set_wo_ready.suggestName("c_set_wo_ready") c_opcodes_set.suggestName("c_opcodes_set") c_sizes_set.suggestName("c_sizes_set") val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W)) val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W)) c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U c_opcode_lookup.suggestName("c_opcode_lookup") c_size_lookup.suggestName("c_size_lookup") val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W)) val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W)) c_opcodes_set_interm.suggestName("c_opcodes_set_interm") c_sizes_set_interm.suggestName("c_sizes_set_interm") when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) { c_set_wo_ready := UIntToOH(bundle.c.bits.source) } when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) { c_set := UIntToOH(bundle.c.bits.source) c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) \| 1.U c_sizes_set_interm := (bundle.c.bits.size << 1.U) \| 1.U c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U) c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U) monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra) } val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck \|\| bundle.c.bits.opcode === TLMessages.ProbeAckData val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") d_opcodes_clr.suggestName("d_opcodes_clr") d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) \|\| same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) { assume((!bundle.d.ready) \|\| bundle.c.ready, "ready check") } if (edge.manager.minLatency > 0) { when (c_set_wo_ready.orR) { assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra) } } inflight := (inflight \| c_set) & ~d_clr inflight_opcodes := (inflight_opcodes \| c_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes \| c_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.c.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.manager.endSinkId.W)) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val e_first = true.B val d_set = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) { d_set := UIntToOH(bundle.d.bits.sink) assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra) } val e_clr = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) { e_clr := UIntToOH(bundle.e.bits.sink) monAssert((d_set \| inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra) } // edge.client.minLatency applies to BC, not DE inflight := (inflight \| d_set) & ~e_clr } def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = { val sourceBits = log2Ceil(edge.client.endSourceId) val tooBig = 14 // >16kB worth of flight information gets to be too much if (sourceBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked") } else { if (args.edge.params(TestplanTestType).simulation) { if (args.edge.params(TLMonitorStrictMode)) { legalizeADSource(bundle, edge) legalizeCDSource(bundle, edge) } else { legalizeADSourceOld(bundle, edge) } } if (args.edge.params(TestplanTestType).formal) { legalizeADSourceFormal(bundle, edge) } } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { // legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize... val sinkBits = log2Ceil(edge.manager.endSinkId) if (sinkBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked") } else { legalizeDESink(bundle, edge) } } } def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = { legalizeFormat (bundle, edge) legalizeMultibeat (bundle, edge) legalizeUnique (bundle, edge) } } File Misc.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import scala.math._ class ParameterizedBundle(implicit p: Parameters) extends Bundle trait Clocked extends Bundle { val clock = Clock() val reset = Bool() } object DecoupledHelper { def apply(rvs: Bool) = new DecoupledHelper(rvs) } class DecoupledHelper(val rvs: Seq[Bool]) { def fire(exclude: Bool, includes: Bool) = { require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!") (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _) } def fire() = { rvs.reduce(_ && _) } } object MuxT { def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2)) def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3)) def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4)) } /** Creates a cascade of n MuxTs to search for a key value. / object MuxTLookup { def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } } object ValidMux { def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]): ValidIO[T] = { apply(v1 +: v2.toSeq) } def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = { val out = Wire(Valid(valids.head.bits.cloneType)) out.valid := valids.map(_.valid).reduce(_ \|\| _) out.bits := MuxCase(valids.head.bits, valids.map(v => (v.valid -> v.bits))) out } } object Str { def apply(s: String): UInt = { var i = BigInt(0) require(s.forall(validChar _)) for (c <- s) i = (i << 8) \| c i.U((s.length8).W) } def apply(x: Char): UInt = { require(validChar(x)) x.U(8.W) } def apply(x: UInt): UInt = apply(x, 10) def apply(x: UInt, radix: Int): UInt = { val rad = radix.U val w = x.getWidth require(w > 0) var q = x var s = digit(q % rad) for (i <- 1 until ceil(log(2)/log(radix)w).toInt) { q = q / rad s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s) } s } def apply(x: SInt): UInt = apply(x, 10) def apply(x: SInt, radix: Int): UInt = { val neg = x < 0.S val abs = x.abs.asUInt if (radix != 10) { Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix)) } else { val rad = radix.U val w = abs.getWidth require(w > 0) var q = abs var s = digit(q % rad) var needSign = neg for (i <- 1 until ceil(log(2)/log(radix)w).toInt) { q = q / rad val placeSpace = q === 0.U val space = Mux(needSign, Str('-'), Str(' ')) needSign = needSign && !placeSpace s = Cat(Mux(placeSpace, space, digit(q % rad)), s) } Cat(Mux(needSign, Str('-'), Str(' ')), s) } } private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0) private def validChar(x: Char) = x == (x & 0xFF) } object Split { def apply(x: UInt, n0: Int) = { val w = x.getWidth (x.extract(w-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n2: Int, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } } object Random { def apply(mod: Int, random: UInt): UInt = { if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0) else PriorityEncoder(partition(apply(1 << log2Up(mod8), random), mod)) } def apply(mod: Int): UInt = apply(mod, randomizer) def oneHot(mod: Int, random: UInt): UInt = { if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0)) else PriorityEncoderOH(partition(apply(1 << log2Up(mod8), random), mod)).asUInt } def oneHot(mod: Int): UInt = oneHot(mod, randomizer) private def randomizer = LFSR(16) private def partition(value: UInt, slices: Int) = Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U) } object Majority { def apply(in: Set[Bool]): Bool = { val n = (in.size >> 1) + 1 val clauses = in.subsets(n).map(_.reduce(_ && _)) clauses.reduce(_ \|\| _) } def apply(in: Seq[Bool]): Bool = apply(in.toSet) def apply(in: UInt): Bool = apply(in.asBools.toSet) } object PopCountAtLeast { private def two(x: UInt): (Bool, Bool) = x.getWidth match { case 1 => (x.asBool, false.B) case n => val half = x.getWidth / 2 val (leftOne, leftTwo) = two(x(half - 1, 0)) val (rightOne, rightTwo) = two(x(x.getWidth - 1, half)) (leftOne \|\| rightOne, leftTwo \|\| rightTwo \|\| (leftOne && rightOne)) } def apply(x: UInt, n: Int): Bool = n match { case 0 => true.B case 1 => x.orR case 2 => two(x)._2 case 3 => PopCount(x) >= n.U } } // This gets used everywhere, so make the smallest circuit possible ... // Given an address and size, create a mask of beatBytes size // eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111 // groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01 object MaskGen { def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = { require (groupBy >= 1 && beatBytes >= groupBy) require (isPow2(beatBytes) && isPow2(groupBy)) val lgBytes = log2Ceil(beatBytes) val sizeOH = UIntToOH(lgSize \| 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) \| (groupBy2 - 1).U def helper(i: Int): Seq[(Bool, Bool)] = { if (i == 0) { Seq((lgSize >= lgBytes.asUInt, true.B)) } else { val sub = helper(i-1) val size = sizeOH(lgBytes - i) val bit = addr_lo(lgBytes - i) val nbit = !bit Seq.tabulate (1 << i) { j => val (sub_acc, sub_eq) = sub(j/2) val eq = sub_eq && (if (j % 2 == 1) bit else nbit) val acc = sub_acc \|\| (size && eq) (acc, eq) } } } if (groupBy == beatBytes) 1.U else Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse) } } File PlusArg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.experimental._ import chisel3.util.HasBlackBoxResource @deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05") case class PlusArgInfo(default: BigInt, docstring: String) /** Case class for PlusArg information * * @tparam A scala type of the PlusArg value * @param default optional default value * @param docstring text to include in the help * @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT) / private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String) /* Typeclass for converting a type to a doctype string * @tparam A some type / trait Doctypeable[A] { /* Return the doctype string for some option / def toDoctype(a: Option[A]): String } /* Object containing implementations of the Doctypeable typeclass / object Doctypes { /* Converts an Int => "INT" / implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" } /* Converts a BigInt => "INT" / implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" } /* Converts a String => "STRING" / implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" } } class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map( "FORMAT" -> StringParam(format), "DEFAULT" -> IntParam(default), "WIDTH" -> IntParam(width) )) with HasBlackBoxResource { val io = IO(new Bundle { val out = Output(UInt(width.W)) }) addResource("/vsrc/plusarg_reader.v") } / This wrapper class has no outputs, making it clear it is a simulation-only construct / class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module { val io = IO(new Bundle { val count = Input(UInt(width.W)) }) val max = Module(new plusarg_reader(format, default, docstring, width)).io.out when (max > 0.U) { assert (io.count < max, s"Timeout exceeded: $docstring") } } import Doctypes._ object PlusArg { /* PlusArg("foo") will return 42.U if the simulation is run with +foo=42 * Do not use this as an initial register value. The value is set in an * initial block and thus accessing it from another initial is racey. * Add a docstring to document the arg, which can be dumped in an elaboration * pass. / def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out } /* PlusArg.timeout(name, default, docstring)(count) will use chisel.assert * to kill the simulation when count exceeds the specified integer argument. * Default 0 will never assert. / def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count } } object PlusArgArtefacts { private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty / Add a new PlusArg / @deprecated( "Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05" ) def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring) /* Add a new PlusArg * * @tparam A scala type of the PlusArg value * @param name name for the PlusArg * @param default optional default value * @param docstring text to include in the help / def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit = artefacts = artefacts ++ Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default))) / From plus args, generate help text / private def serializeHelp_cHeader(tab: String = ""): String = artefacts .map{ case(arg, info) => s"""\|$tab+$arg=${info.doctype}\\n\\ \|$tab${" "20}${info.docstring}\\n\\ \|""".stripMargin ++ info.default.map{ case default => s"$tab${" "22}(default=${default})\\n\\\n"}.getOrElse("") }.toSeq.mkString("\\n\\\n") ++ "\"" / From plus args, generate a char array of their names / private def serializeArray_cHeader(tab: String = ""): String = { val prettyTab = tab + " " 44 // Length of 'static const ...' s"${tab}static const char * verilog_plusargs [] = {\\\n" ++ artefacts .map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" } .mkString("")++ s"${prettyTab}0};" } /* Generate C code to be included in emulator.cc that helps with * argument parsing based on available Verilog PlusArgs / def serialize_cHeader(): String = s"""\|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\ \|${serializeHelp_cHeader(" "7)} \|${serializeArray_cHeader()} \|""".stripMargin } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /* Like Vec.apply(idx), but tolerates indices of mismatched width / def extract(idx: UInt): T = x((idx \| 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx \| 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def \| (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a \|\| b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_\|\|_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /* Any Data subtype that has a Bool member named valid. / type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /* converts from camel case to to underscores, also removing all spaces / def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /* converts spaces or underscores to hyphens, also lowering case / def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y \| (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y \|\| y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 \| 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /* Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation / def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Bundles.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import freechips.rocketchip.util._ import scala.collection.immutable.ListMap import chisel3.util.Decoupled import chisel3.util.DecoupledIO import chisel3.reflect.DataMirror abstract class TLBundleBase(val params: TLBundleParameters) extends Bundle // common combos in lazy policy: // Put + Acquire // Release + AccessAck object TLMessages { // A B C D E def PutFullData = 0.U // . . => AccessAck def PutPartialData = 1.U // . . => AccessAck def ArithmeticData = 2.U // . . => AccessAckData def LogicalData = 3.U // . . => AccessAckData def Get = 4.U // . . => AccessAckData def Hint = 5.U // . . => HintAck def AcquireBlock = 6.U // . => Grant[Data] def AcquirePerm = 7.U // . => Grant[Data] def Probe = 6.U // . => ProbeAck[Data] def AccessAck = 0.U // . . def AccessAckData = 1.U // . . def HintAck = 2.U // . . def ProbeAck = 4.U // . def ProbeAckData = 5.U // . def Release = 6.U // . => ReleaseAck def ReleaseData = 7.U // . => ReleaseAck def Grant = 4.U // . => GrantAck def GrantData = 5.U // . => GrantAck def ReleaseAck = 6.U // . def GrantAck = 0.U // . def isA(x: UInt) = x <= AcquirePerm def isB(x: UInt) = x <= Probe def isC(x: UInt) = x <= ReleaseData def isD(x: UInt) = x <= ReleaseAck def adResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, Grant, Grant) def bcResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, ProbeAck, ProbeAck) def a = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("AcquireBlock",TLPermissions.PermMsgGrow), ("AcquirePerm",TLPermissions.PermMsgGrow)) def b = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("Probe",TLPermissions.PermMsgCap)) def c = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("ProbeAck",TLPermissions.PermMsgReport), ("ProbeAckData",TLPermissions.PermMsgReport), ("Release",TLPermissions.PermMsgReport), ("ReleaseData",TLPermissions.PermMsgReport)) def d = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("Grant",TLPermissions.PermMsgCap), ("GrantData",TLPermissions.PermMsgCap), ("ReleaseAck",TLPermissions.PermMsgReserved)) } /* * The three primary TileLink permissions are: * (T)runk: the agent is (or is on inwards path to) the global point of serialization. * (B)ranch: the agent is on an outwards path to * (N)one: * These permissions are permuted by transfer operations in various ways. * Operations can cap permissions, request for them to be grown or shrunk, * or for a report on their current status. / object TLPermissions { val aWidth = 2 val bdWidth = 2 val cWidth = 3 // Cap types (Grant = new permissions, Probe = permisions <= target) def toT = 0.U(bdWidth.W) def toB = 1.U(bdWidth.W) def toN = 2.U(bdWidth.W) def isCap(x: UInt) = x <= toN // Grow types (Acquire = permissions >= target) def NtoB = 0.U(aWidth.W) def NtoT = 1.U(aWidth.W) def BtoT = 2.U(aWidth.W) def isGrow(x: UInt) = x <= BtoT // Shrink types (ProbeAck, Release) def TtoB = 0.U(cWidth.W) def TtoN = 1.U(cWidth.W) def BtoN = 2.U(cWidth.W) def isShrink(x: UInt) = x <= BtoN // Report types (ProbeAck, Release) def TtoT = 3.U(cWidth.W) def BtoB = 4.U(cWidth.W) def NtoN = 5.U(cWidth.W) def isReport(x: UInt) = x <= NtoN def PermMsgGrow:Seq[String] = Seq("Grow NtoB", "Grow NtoT", "Grow BtoT") def PermMsgCap:Seq[String] = Seq("Cap toT", "Cap toB", "Cap toN") def PermMsgReport:Seq[String] = Seq("Shrink TtoB", "Shrink TtoN", "Shrink BtoN", "Report TotT", "Report BtoB", "Report NtoN") def PermMsgReserved:Seq[String] = Seq("Reserved") } object TLAtomics { val width = 3 // Arithmetic types def MIN = 0.U(width.W) def MAX = 1.U(width.W) def MINU = 2.U(width.W) def MAXU = 3.U(width.W) def ADD = 4.U(width.W) def isArithmetic(x: UInt) = x <= ADD // Logical types def XOR = 0.U(width.W) def OR = 1.U(width.W) def AND = 2.U(width.W) def SWAP = 3.U(width.W) def isLogical(x: UInt) = x <= SWAP def ArithMsg:Seq[String] = Seq("MIN", "MAX", "MINU", "MAXU", "ADD") def LogicMsg:Seq[String] = Seq("XOR", "OR", "AND", "SWAP") } object TLHints { val width = 1 def PREFETCH_READ = 0.U(width.W) def PREFETCH_WRITE = 1.U(width.W) def isHints(x: UInt) = x <= PREFETCH_WRITE def HintsMsg:Seq[String] = Seq("PrefetchRead", "PrefetchWrite") } sealed trait TLChannel extends TLBundleBase { val channelName: String } sealed trait TLDataChannel extends TLChannel sealed trait TLAddrChannel extends TLDataChannel final class TLBundleA(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleA_${params.shortName}" val channelName = "'A' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(List(TLAtomics.width, TLPermissions.aWidth, TLHints.width).max.W) // amo_opcode \|\| grow perms \|\| hint val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleB(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleB_${params.shortName}" val channelName = "'B' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val address = UInt(params.addressBits.W) // from // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleC(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleC_${params.shortName}" val channelName = "'C' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.cWidth.W) // shrink or report perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleD(params: TLBundleParameters) extends TLBundleBase(params) with TLDataChannel { override def typeName = s"TLBundleD_${params.shortName}" val channelName = "'D' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val sink = UInt(params.sinkBits.W) // from val denied = Bool() // implies corrupt iff Data val user = BundleMap(params.responseFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleE(params: TLBundleParameters) extends TLBundleBase(params) with TLChannel { override def typeName = s"TLBundleE_${params.shortName}" val channelName = "'E' channel" val sink = UInt(params.sinkBits.W) // to } class TLBundle(val params: TLBundleParameters) extends Record { // Emulate a Bundle with elements abcde or ad depending on params.hasBCE private val optA = Some (Decoupled(new TLBundleA(params))) private val optB = params.hasBCE.option(Flipped(Decoupled(new TLBundleB(params)))) private val optC = params.hasBCE.option(Decoupled(new TLBundleC(params))) private val optD = Some (Flipped(Decoupled(new TLBundleD(params)))) private val optE = params.hasBCE.option(Decoupled(new TLBundleE(params))) def a: DecoupledIO[TLBundleA] = optA.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleA(params))))) def b: DecoupledIO[TLBundleB] = optB.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleB(params))))) def c: DecoupledIO[TLBundleC] = optC.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleC(params))))) def d: DecoupledIO[TLBundleD] = optD.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleD(params))))) def e: DecoupledIO[TLBundleE] = optE.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleE(params))))) val elements = if (params.hasBCE) ListMap("e" -> e, "d" -> d, "c" -> c, "b" -> b, "a" -> a) else ListMap("d" -> d, "a" -> a) def tieoff(): Unit = { DataMirror.specifiedDirectionOf(a.ready) match { case SpecifiedDirection.Input => a.ready := false.B c.ready := false.B e.ready := false.B b.valid := false.B d.valid := false.B case SpecifiedDirection.Output => a.valid := false.B c.valid := false.B e.valid := false.B b.ready := false.B d.ready := false.B case _ => } } } object TLBundle { def apply(params: TLBundleParameters) = new TLBundle(params) } class TLAsyncBundleBase(val params: TLAsyncBundleParameters) extends Bundle class TLAsyncBundle(params: TLAsyncBundleParameters) extends TLAsyncBundleBase(params) { val a = new AsyncBundle(new TLBundleA(params.base), params.async) val b = Flipped(new AsyncBundle(new TLBundleB(params.base), params.async)) val c = new AsyncBundle(new TLBundleC(params.base), params.async) val d = Flipped(new AsyncBundle(new TLBundleD(params.base), params.async)) val e = new AsyncBundle(new TLBundleE(params.base), params.async) } class TLRationalBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = RationalIO(new TLBundleA(params)) val b = Flipped(RationalIO(new TLBundleB(params))) val c = RationalIO(new TLBundleC(params)) val d = Flipped(RationalIO(new TLBundleD(params))) val e = RationalIO(new TLBundleE(params)) } class TLCreditedBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = CreditedIO(new TLBundleA(params)) val b = Flipped(CreditedIO(new TLBundleB(params))) val c = CreditedIO(new TLBundleC(params)) val d = Flipped(CreditedIO(new TLBundleD(params))) val e = CreditedIO(new TLBundleE(params)) } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.nodes._ import freechips.rocketchip.diplomacy.{ AddressDecoder, AddressSet, BufferParams, DirectedBuffers, IdMap, IdMapEntry, IdRange, RegionType, TransferSizes } import freechips.rocketchip.resources.{Resource, ResourceAddress, ResourcePermissions} import freechips.rocketchip.util.{ AsyncQueueParams, BundleField, BundleFieldBase, BundleKeyBase, CreditedDelay, groupByIntoSeq, RationalDirection, SimpleProduct } import scala.math.max //These transfer sizes describe requests issued from masters on the A channel that will be responded by slaves on the D channel case class TLMasterToSlaveTransferSizes( // Supports both Acquire+Release of the following two sizes: acquireT: TransferSizes = TransferSizes.none, acquireB: TransferSizes = TransferSizes.none, arithmetic: TransferSizes = TransferSizes.none, logical: TransferSizes = TransferSizes.none, get: TransferSizes = TransferSizes.none, putFull: TransferSizes = TransferSizes.none, putPartial: TransferSizes = TransferSizes.none, hint: TransferSizes = TransferSizes.none) extends TLCommonTransferSizes { def intersect(rhs: TLMasterToSlaveTransferSizes) = TLMasterToSlaveTransferSizes( acquireT = acquireT .intersect(rhs.acquireT), acquireB = acquireB .intersect(rhs.acquireB), arithmetic = arithmetic.intersect(rhs.arithmetic), logical = logical .intersect(rhs.logical), get = get .intersect(rhs.get), putFull = putFull .intersect(rhs.putFull), putPartial = putPartial.intersect(rhs.putPartial), hint = hint .intersect(rhs.hint)) def mincover(rhs: TLMasterToSlaveTransferSizes) = TLMasterToSlaveTransferSizes( acquireT = acquireT .mincover(rhs.acquireT), acquireB = acquireB .mincover(rhs.acquireB), arithmetic = arithmetic.mincover(rhs.arithmetic), logical = logical .mincover(rhs.logical), get = get .mincover(rhs.get), putFull = putFull .mincover(rhs.putFull), putPartial = putPartial.mincover(rhs.putPartial), hint = hint .mincover(rhs.hint)) // Reduce rendering to a simple yes/no per field override def toString = { def str(x: TransferSizes, flag: String) = if (x.none) "" else flag def flags = Vector( str(acquireT, "T"), str(acquireB, "B"), str(arithmetic, "A"), str(logical, "L"), str(get, "G"), str(putFull, "F"), str(putPartial, "P"), str(hint, "H")) flags.mkString } // Prints out the actual information in a user readable way def infoString = { s"""acquireT = ${acquireT} \|acquireB = ${acquireB} \|arithmetic = ${arithmetic} \|logical = ${logical} \|get = ${get} \|putFull = ${putFull} \|putPartial = ${putPartial} \|hint = ${hint} \| \|""".stripMargin } } object TLMasterToSlaveTransferSizes { def unknownEmits = TLMasterToSlaveTransferSizes( acquireT = TransferSizes(1, 4096), acquireB = TransferSizes(1, 4096), arithmetic = TransferSizes(1, 4096), logical = TransferSizes(1, 4096), get = TransferSizes(1, 4096), putFull = TransferSizes(1, 4096), putPartial = TransferSizes(1, 4096), hint = TransferSizes(1, 4096)) def unknownSupports = TLMasterToSlaveTransferSizes() } //These transfer sizes describe requests issued from slaves on the B channel that will be responded by masters on the C channel case class TLSlaveToMasterTransferSizes( probe: TransferSizes = TransferSizes.none, arithmetic: TransferSizes = TransferSizes.none, logical: TransferSizes = TransferSizes.none, get: TransferSizes = TransferSizes.none, putFull: TransferSizes = TransferSizes.none, putPartial: TransferSizes = TransferSizes.none, hint: TransferSizes = TransferSizes.none ) extends TLCommonTransferSizes { def intersect(rhs: TLSlaveToMasterTransferSizes) = TLSlaveToMasterTransferSizes( probe = probe .intersect(rhs.probe), arithmetic = arithmetic.intersect(rhs.arithmetic), logical = logical .intersect(rhs.logical), get = get .intersect(rhs.get), putFull = putFull .intersect(rhs.putFull), putPartial = putPartial.intersect(rhs.putPartial), hint = hint .intersect(rhs.hint) ) def mincover(rhs: TLSlaveToMasterTransferSizes) = TLSlaveToMasterTransferSizes( probe = probe .mincover(rhs.probe), arithmetic = arithmetic.mincover(rhs.arithmetic), logical = logical .mincover(rhs.logical), get = get .mincover(rhs.get), putFull = putFull .mincover(rhs.putFull), putPartial = putPartial.mincover(rhs.putPartial), hint = hint .mincover(rhs.hint) ) // Reduce rendering to a simple yes/no per field override def toString = { def str(x: TransferSizes, flag: String) = if (x.none) "" else flag def flags = Vector( str(probe, "P"), str(arithmetic, "A"), str(logical, "L"), str(get, "G"), str(putFull, "F"), str(putPartial, "P"), str(hint, "H")) flags.mkString } // Prints out the actual information in a user readable way def infoString = { s"""probe = ${probe} \|arithmetic = ${arithmetic} \|logical = ${logical} \|get = ${get} \|putFull = ${putFull} \|putPartial = ${putPartial} \|hint = ${hint} \| \|""".stripMargin } } object TLSlaveToMasterTransferSizes { def unknownEmits = TLSlaveToMasterTransferSizes( arithmetic = TransferSizes(1, 4096), logical = TransferSizes(1, 4096), get = TransferSizes(1, 4096), putFull = TransferSizes(1, 4096), putPartial = TransferSizes(1, 4096), hint = TransferSizes(1, 4096), probe = TransferSizes(1, 4096)) def unknownSupports = TLSlaveToMasterTransferSizes() } trait TLCommonTransferSizes { def arithmetic: TransferSizes def logical: TransferSizes def get: TransferSizes def putFull: TransferSizes def putPartial: TransferSizes def hint: TransferSizes } class TLSlaveParameters private( val nodePath: Seq[BaseNode], val resources: Seq[Resource], setName: Option[String], val address: Seq[AddressSet], val regionType: RegionType.T, val executable: Boolean, val fifoId: Option[Int], val supports: TLMasterToSlaveTransferSizes, val emits: TLSlaveToMasterTransferSizes, // By default, slaves are forbidden from issuing 'denied' responses (it prevents Fragmentation) val alwaysGrantsT: Boolean, // typically only true for CacheCork'd read-write devices; dual: neverReleaseData // If fifoId=Some, all accesses sent to the same fifoId are executed and ACK'd in FIFO order // Note: you can only rely on this FIFO behaviour if your TLMasterParameters include requestFifo val mayDenyGet: Boolean, // applies to: AccessAckData, GrantData val mayDenyPut: Boolean) // applies to: AccessAck, Grant, HintAck // ReleaseAck may NEVER be denied extends SimpleProduct { def sortedAddress = address.sorted override def canEqual(that: Any): Boolean = that.isInstanceOf[TLSlaveParameters] override def productPrefix = "TLSlaveParameters" // We intentionally omit nodePath for equality testing / formatting def productArity: Int = 11 def productElement(n: Int): Any = n match { case 0 => name case 1 => address case 2 => resources case 3 => regionType case 4 => executable case 5 => fifoId case 6 => supports case 7 => emits case 8 => alwaysGrantsT case 9 => mayDenyGet case 10 => mayDenyPut case _ => throw new IndexOutOfBoundsException(n.toString) } def supportsAcquireT: TransferSizes = supports.acquireT def supportsAcquireB: TransferSizes = supports.acquireB def supportsArithmetic: TransferSizes = supports.arithmetic def supportsLogical: TransferSizes = supports.logical def supportsGet: TransferSizes = supports.get def supportsPutFull: TransferSizes = supports.putFull def supportsPutPartial: TransferSizes = supports.putPartial def supportsHint: TransferSizes = supports.hint require (!address.isEmpty, "Address cannot be empty") address.foreach { a => require (a.finite, "Address must be finite") } address.combinations(2).foreach { case Seq(x,y) => require (!x.overlaps(y), s"$x and $y overlap.") } require (supportsPutFull.contains(supportsPutPartial), s"PutFull($supportsPutFull) < PutPartial($supportsPutPartial)") require (supportsPutFull.contains(supportsArithmetic), s"PutFull($supportsPutFull) < Arithmetic($supportsArithmetic)") require (supportsPutFull.contains(supportsLogical), s"PutFull($supportsPutFull) < Logical($supportsLogical)") require (supportsGet.contains(supportsArithmetic), s"Get($supportsGet) < Arithmetic($supportsArithmetic)") require (supportsGet.contains(supportsLogical), s"Get($supportsGet) < Logical($supportsLogical)") require (supportsAcquireB.contains(supportsAcquireT), s"AcquireB($supportsAcquireB) < AcquireT($supportsAcquireT)") require (!alwaysGrantsT \|\| supportsAcquireT, s"Must supportAcquireT if promising to always grantT") // Make sure that the regionType agrees with the capabilities require (!supportsAcquireB \|\| regionType >= RegionType.UNCACHED) // acquire -> uncached, tracked, cached require (regionType <= RegionType.UNCACHED \|\| supportsAcquireB) // tracked, cached -> acquire require (regionType != RegionType.UNCACHED \|\| supportsGet) // uncached -> supportsGet val name = setName.orElse(nodePath.lastOption.map(_.lazyModule.name)).getOrElse("disconnected") val maxTransfer = List( // Largest supported transfer of all types supportsAcquireT.max, supportsAcquireB.max, supportsArithmetic.max, supportsLogical.max, supportsGet.max, supportsPutFull.max, supportsPutPartial.max).max val maxAddress = address.map(_.max).max val minAlignment = address.map(_.alignment).min // The device had better not support a transfer larger than its alignment require (minAlignment >= maxTransfer, s"Bad $address: minAlignment ($minAlignment) must be >= maxTransfer ($maxTransfer)") def toResource: ResourceAddress = { ResourceAddress(address, ResourcePermissions( r = supportsAcquireB \|\| supportsGet, w = supportsAcquireT \|\| supportsPutFull, x = executable, c = supportsAcquireB, a = supportsArithmetic && supportsLogical)) } def findTreeViolation() = nodePath.find { case _: MixedAdapterNode[_, _, _, _, _, _, _, _] => false case _: SinkNode[_, _, _, _, _] => false case node => node.inputs.size != 1 } def isTree = findTreeViolation() == None def infoString = { s"""Slave Name = ${name} \|Slave Address = ${address} \|supports = ${supports.infoString} \| \|""".stripMargin } def v1copy( address: Seq[AddressSet] = address, resources: Seq[Resource] = resources, regionType: RegionType.T = regionType, executable: Boolean = executable, nodePath: Seq[BaseNode] = nodePath, supportsAcquireT: TransferSizes = supports.acquireT, supportsAcquireB: TransferSizes = supports.acquireB, supportsArithmetic: TransferSizes = supports.arithmetic, supportsLogical: TransferSizes = supports.logical, supportsGet: TransferSizes = supports.get, supportsPutFull: TransferSizes = supports.putFull, supportsPutPartial: TransferSizes = supports.putPartial, supportsHint: TransferSizes = supports.hint, mayDenyGet: Boolean = mayDenyGet, mayDenyPut: Boolean = mayDenyPut, alwaysGrantsT: Boolean = alwaysGrantsT, fifoId: Option[Int] = fifoId) = { new TLSlaveParameters( setName = setName, address = address, resources = resources, regionType = regionType, executable = executable, nodePath = nodePath, supports = TLMasterToSlaveTransferSizes( acquireT = supportsAcquireT, acquireB = supportsAcquireB, arithmetic = supportsArithmetic, logical = supportsLogical, get = supportsGet, putFull = supportsPutFull, putPartial = supportsPutPartial, hint = supportsHint), emits = emits, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut, alwaysGrantsT = alwaysGrantsT, fifoId = fifoId) } def v2copy( nodePath: Seq[BaseNode] = nodePath, resources: Seq[Resource] = resources, name: Option[String] = setName, address: Seq[AddressSet] = address, regionType: RegionType.T = regionType, executable: Boolean = executable, fifoId: Option[Int] = fifoId, supports: TLMasterToSlaveTransferSizes = supports, emits: TLSlaveToMasterTransferSizes = emits, alwaysGrantsT: Boolean = alwaysGrantsT, mayDenyGet: Boolean = mayDenyGet, mayDenyPut: Boolean = mayDenyPut) = { new TLSlaveParameters( nodePath = nodePath, resources = resources, setName = name, address = address, regionType = regionType, executable = executable, fifoId = fifoId, supports = supports, emits = emits, alwaysGrantsT = alwaysGrantsT, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut) } @deprecated("Use v1copy instead of copy","") def copy( address: Seq[AddressSet] = address, resources: Seq[Resource] = resources, regionType: RegionType.T = regionType, executable: Boolean = executable, nodePath: Seq[BaseNode] = nodePath, supportsAcquireT: TransferSizes = supports.acquireT, supportsAcquireB: TransferSizes = supports.acquireB, supportsArithmetic: TransferSizes = supports.arithmetic, supportsLogical: TransferSizes = supports.logical, supportsGet: TransferSizes = supports.get, supportsPutFull: TransferSizes = supports.putFull, supportsPutPartial: TransferSizes = supports.putPartial, supportsHint: TransferSizes = supports.hint, mayDenyGet: Boolean = mayDenyGet, mayDenyPut: Boolean = mayDenyPut, alwaysGrantsT: Boolean = alwaysGrantsT, fifoId: Option[Int] = fifoId) = { v1copy( address = address, resources = resources, regionType = regionType, executable = executable, nodePath = nodePath, supportsAcquireT = supportsAcquireT, supportsAcquireB = supportsAcquireB, supportsArithmetic = supportsArithmetic, supportsLogical = supportsLogical, supportsGet = supportsGet, supportsPutFull = supportsPutFull, supportsPutPartial = supportsPutPartial, supportsHint = supportsHint, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut, alwaysGrantsT = alwaysGrantsT, fifoId = fifoId) } } object TLSlaveParameters { def v1( address: Seq[AddressSet], resources: Seq[Resource] = Seq(), regionType: RegionType.T = RegionType.GET_EFFECTS, executable: Boolean = false, nodePath: Seq[BaseNode] = Seq(), supportsAcquireT: TransferSizes = TransferSizes.none, supportsAcquireB: TransferSizes = TransferSizes.none, supportsArithmetic: TransferSizes = TransferSizes.none, supportsLogical: TransferSizes = TransferSizes.none, supportsGet: TransferSizes = TransferSizes.none, supportsPutFull: TransferSizes = TransferSizes.none, supportsPutPartial: TransferSizes = TransferSizes.none, supportsHint: TransferSizes = TransferSizes.none, mayDenyGet: Boolean = false, mayDenyPut: Boolean = false, alwaysGrantsT: Boolean = false, fifoId: Option[Int] = None) = { new TLSlaveParameters( setName = None, address = address, resources = resources, regionType = regionType, executable = executable, nodePath = nodePath, supports = TLMasterToSlaveTransferSizes( acquireT = supportsAcquireT, acquireB = supportsAcquireB, arithmetic = supportsArithmetic, logical = supportsLogical, get = supportsGet, putFull = supportsPutFull, putPartial = supportsPutPartial, hint = supportsHint), emits = TLSlaveToMasterTransferSizes.unknownEmits, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut, alwaysGrantsT = alwaysGrantsT, fifoId = fifoId) } def v2( address: Seq[AddressSet], nodePath: Seq[BaseNode] = Seq(), resources: Seq[Resource] = Seq(), name: Option[String] = None, regionType: RegionType.T = RegionType.GET_EFFECTS, executable: Boolean = false, fifoId: Option[Int] = None, supports: TLMasterToSlaveTransferSizes = TLMasterToSlaveTransferSizes.unknownSupports, emits: TLSlaveToMasterTransferSizes = TLSlaveToMasterTransferSizes.unknownEmits, alwaysGrantsT: Boolean = false, mayDenyGet: Boolean = false, mayDenyPut: Boolean = false) = { new TLSlaveParameters( nodePath = nodePath, resources = resources, setName = name, address = address, regionType = regionType, executable = executable, fifoId = fifoId, supports = supports, emits = emits, alwaysGrantsT = alwaysGrantsT, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut) } } object TLManagerParameters { @deprecated("Use TLSlaveParameters.v1 instead of TLManagerParameters","") def apply( address: Seq[AddressSet], resources: Seq[Resource] = Seq(), regionType: RegionType.T = RegionType.GET_EFFECTS, executable: Boolean = false, nodePath: Seq[BaseNode] = Seq(), supportsAcquireT: TransferSizes = TransferSizes.none, supportsAcquireB: TransferSizes = TransferSizes.none, supportsArithmetic: TransferSizes = TransferSizes.none, supportsLogical: TransferSizes = TransferSizes.none, supportsGet: TransferSizes = TransferSizes.none, supportsPutFull: TransferSizes = TransferSizes.none, supportsPutPartial: TransferSizes = TransferSizes.none, supportsHint: TransferSizes = TransferSizes.none, mayDenyGet: Boolean = false, mayDenyPut: Boolean = false, alwaysGrantsT: Boolean = false, fifoId: Option[Int] = None) = TLSlaveParameters.v1( address, resources, regionType, executable, nodePath, supportsAcquireT, supportsAcquireB, supportsArithmetic, supportsLogical, supportsGet, supportsPutFull, supportsPutPartial, supportsHint, mayDenyGet, mayDenyPut, alwaysGrantsT, fifoId, ) } case class TLChannelBeatBytes(a: Option[Int], b: Option[Int], c: Option[Int], d: Option[Int]) { def members = Seq(a, b, c, d) members.collect { case Some(beatBytes) => require (isPow2(beatBytes), "Data channel width must be a power of 2") } } object TLChannelBeatBytes{ def apply(beatBytes: Int): TLChannelBeatBytes = TLChannelBeatBytes( Some(beatBytes), Some(beatBytes), Some(beatBytes), Some(beatBytes)) def apply(): TLChannelBeatBytes = TLChannelBeatBytes( None, None, None, None) } class TLSlavePortParameters private( val slaves: Seq[TLSlaveParameters], val channelBytes: TLChannelBeatBytes, val endSinkId: Int, val minLatency: Int, val responseFields: Seq[BundleFieldBase], val requestKeys: Seq[BundleKeyBase]) extends SimpleProduct { def sortedSlaves = slaves.sortBy(_.sortedAddress.head) override def canEqual(that: Any): Boolean = that.isInstanceOf[TLSlavePortParameters] override def productPrefix = "TLSlavePortParameters" def productArity: Int = 6 def productElement(n: Int): Any = n match { case 0 => slaves case 1 => channelBytes case 2 => endSinkId case 3 => minLatency case 4 => responseFields case 5 => requestKeys case _ => throw new IndexOutOfBoundsException(n.toString) } require (!slaves.isEmpty, "Slave ports must have slaves") require (endSinkId >= 0, "Sink ids cannot be negative") require (minLatency >= 0, "Minimum required latency cannot be negative") // Using this API implies you cannot handle mixed-width busses def beatBytes = { channelBytes.members.foreach { width => require (width.isDefined && width == channelBytes.a) } channelBytes.a.get } // TODO this should be deprecated def managers = slaves def requireFifo(policy: TLFIFOFixer.Policy = TLFIFOFixer.allFIFO) = { val relevant = slaves.filter(m => policy(m)) relevant.foreach { m => require(m.fifoId == relevant.head.fifoId, s"${m.name} had fifoId ${m.fifoId}, which was not homogeneous (${slaves.map(s => (s.name, s.fifoId))}) ") } } // Bounds on required sizes def maxAddress = slaves.map(_.maxAddress).max def maxTransfer = slaves.map(_.maxTransfer).max def mayDenyGet = slaves.exists(_.mayDenyGet) def mayDenyPut = slaves.exists(_.mayDenyPut) // Diplomatically determined operation sizes emitted by all outward Slaves // as opposed to emits* which generate circuitry to check which specific addresses val allEmitClaims = slaves.map(_.emits).reduce( _ intersect _) // Operation Emitted by at least one outward Slaves // as opposed to emits* which generate circuitry to check which specific addresses val anyEmitClaims = slaves.map(_.emits).reduce(_ mincover _) // Diplomatically determined operation sizes supported by all outward Slaves // as opposed to supports* which generate circuitry to check which specific addresses val allSupportClaims = slaves.map(_.supports).reduce( _ intersect _) val allSupportAcquireT = allSupportClaims.acquireT val allSupportAcquireB = allSupportClaims.acquireB val allSupportArithmetic = allSupportClaims.arithmetic val allSupportLogical = allSupportClaims.logical val allSupportGet = allSupportClaims.get val allSupportPutFull = allSupportClaims.putFull val allSupportPutPartial = allSupportClaims.putPartial val allSupportHint = allSupportClaims.hint // Operation supported by at least one outward Slaves // as opposed to supports* which generate circuitry to check which specific addresses val anySupportClaims = slaves.map(_.supports).reduce(_ mincover _) val anySupportAcquireT = !anySupportClaims.acquireT.none val anySupportAcquireB = !anySupportClaims.acquireB.none val anySupportArithmetic = !anySupportClaims.arithmetic.none val anySupportLogical = !anySupportClaims.logical.none val anySupportGet = !anySupportClaims.get.none val anySupportPutFull = !anySupportClaims.putFull.none val anySupportPutPartial = !anySupportClaims.putPartial.none val anySupportHint = !anySupportClaims.hint.none // Supporting Acquire means being routable for GrantAck require ((endSinkId == 0) == !anySupportAcquireB) // These return Option[TLSlaveParameters] for your convenience def find(address: BigInt) = slaves.find(_.address.exists(_.contains(address))) // The safe version will check the entire address def findSafe(address: UInt) = VecInit(sortedSlaves.map(_.address.map(_.contains(address)).reduce(_ \|\| _))) // The fast version assumes the address is valid (you probably want fastProperty instead of this function) def findFast(address: UInt) = { val routingMask = AddressDecoder(slaves.map(_.address)) VecInit(sortedSlaves.map(_.address.map(_.widen(~routingMask)).distinct.map(_.contains(address)).reduce(_ \|\| _))) } // Compute the simplest AddressSets that decide a key def fastPropertyGroup[K](p: TLSlaveParameters => K): Seq[(K, Seq[AddressSet])] = { val groups = groupByIntoSeq(sortedSlaves.map(m => (p(m), m.address)))( _._1).map { case (k, vs) => k -> vs.flatMap(_._2) } val reductionMask = AddressDecoder(groups.map(_._2)) groups.map { case (k, seq) => k -> AddressSet.unify(seq.map(_.widen(~reductionMask)).distinct) } } // Select a property def fastProperty[K, D <: Data](address: UInt, p: TLSlaveParameters => K, d: K => D): D = Mux1H(fastPropertyGroup(p).map { case (v, a) => (a.map(_.contains(address)).reduce(_\|\|_), d(v)) }) // Note: returns the actual fifoId + 1 or 0 if None def findFifoIdFast(address: UInt) = fastProperty(address, _.fifoId.map(_+1).getOrElse(0), (i:Int) => i.U) def hasFifoIdFast(address: UInt) = fastProperty(address, _.fifoId.isDefined, (b:Boolean) => b.B) // Does this Port manage this ID/address? def containsSafe(address: UInt) = findSafe(address).reduce(_ \|\| _) private def addressHelper( // setting safe to false indicates that all addresses are expected to be legal, which might reduce circuit complexity safe: Boolean, // member filters out the sizes being checked based on the opcode being emitted or supported member: TLSlaveParameters => TransferSizes, address: UInt, lgSize: UInt, // range provides a limit on the sizes that are expected to be evaluated, which might reduce circuit complexity range: Option[TransferSizes]): Bool = { // trim reduces circuit complexity by intersecting checked sizes with the range argument def trim(x: TransferSizes) = range.map(_.intersect(x)).getOrElse(x) // groupBy returns an unordered map, convert back to Seq and sort the result for determinism // groupByIntoSeq is turning slaves into trimmed membership sizes // We are grouping all the slaves by their transfer size where // if they support the trimmed size then // member is the type of transfer that you are looking for (What you are trying to filter on) // When you consider membership, you are trimming the sizes to only the ones that you care about // you are filtering the slaves based on both whether they support a particular opcode and the size // Grouping the slaves based on the actual transfer size range they support // intersecting the range and checking their membership // FOR SUPPORTCASES instead of returning the list of slaves, // you are returning a map from transfer size to the set of // address sets that are supported for that transfer size // find all the slaves that support a certain type of operation and then group their addresses by the supported size // for every size there could be multiple address ranges // safety is a trade off between checking between all possible addresses vs only the addresses // that are known to have supported sizes // the trade off is 'checking all addresses is a more expensive circuit but will always give you // the right answer even if you give it an illegal address' // the not safe version is a cheaper circuit but if you give it an illegal address then it might produce the wrong answer // fast presumes address legality // This groupByIntoSeq deterministically groups all address sets for which a given `member` transfer size applies. // In the resulting Map of cases, the keys are transfer sizes and the values are all address sets which emit or support that size. val supportCases = groupByIntoSeq(slaves)(m => trim(member(m))).map { case (k: TransferSizes, vs: Seq[TLSlaveParameters]) => k -> vs.flatMap(_.address) } // safe produces a circuit that compares against all possible addresses, // whereas fast presumes that the address is legal but uses an efficient address decoder val mask = if (safe) ~BigInt(0) else AddressDecoder(supportCases.map(_._2)) // Simplified creates the most concise possible representation of each cases' address sets based on the mask. val simplified = supportCases.map { case (k, seq) => k -> AddressSet.unify(seq.map(_.widen(~mask)).distinct) } simplified.map { case (s, a) => // s is a size, you are checking for this size either the size of the operation is in s // We return an or-reduction of all the cases, checking whether any contains both the dynamic size and dynamic address on the wire. ((Some(s) == range).B \|\| s.containsLg(lgSize)) && a.map(_.contains(address)).reduce(_\|\|_) }.foldLeft(false.B)(_\|\|_) } def supportsAcquireTSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.acquireT, address, lgSize, range) def supportsAcquireBSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.acquireB, address, lgSize, range) def supportsArithmeticSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.arithmetic, address, lgSize, range) def supportsLogicalSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.logical, address, lgSize, range) def supportsGetSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.get, address, lgSize, range) def supportsPutFullSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.putFull, address, lgSize, range) def supportsPutPartialSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.putPartial, address, lgSize, range) def supportsHintSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.hint, address, lgSize, range) def supportsAcquireTFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.acquireT, address, lgSize, range) def supportsAcquireBFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.acquireB, address, lgSize, range) def supportsArithmeticFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.arithmetic, address, lgSize, range) def supportsLogicalFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.logical, address, lgSize, range) def supportsGetFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.get, address, lgSize, range) def supportsPutFullFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.putFull, address, lgSize, range) def supportsPutPartialFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.putPartial, address, lgSize, range) def supportsHintFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.hint, address, lgSize, range) def emitsProbeSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.probe, address, lgSize, range) def emitsArithmeticSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.arithmetic, address, lgSize, range) def emitsLogicalSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.logical, address, lgSize, range) def emitsGetSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.get, address, lgSize, range) def emitsPutFullSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.putFull, address, lgSize, range) def emitsPutPartialSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.putPartial, address, lgSize, range) def emitsHintSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.hint, address, lgSize, range) def findTreeViolation() = slaves.flatMap(_.findTreeViolation()).headOption def isTree = !slaves.exists(!_.isTree) def infoString = "Slave Port Beatbytes = " + beatBytes + "\n" + "Slave Port MinLatency = " + minLatency + "\n\n" + slaves.map(_.infoString).mkString def v1copy( managers: Seq[TLSlaveParameters] = slaves, beatBytes: Int = -1, endSinkId: Int = endSinkId, minLatency: Int = minLatency, responseFields: Seq[BundleFieldBase] = responseFields, requestKeys: Seq[BundleKeyBase] = requestKeys) = { new TLSlavePortParameters( slaves = managers, channelBytes = if (beatBytes != -1) TLChannelBeatBytes(beatBytes) else channelBytes, endSinkId = endSinkId, minLatency = minLatency, responseFields = responseFields, requestKeys = requestKeys) } def v2copy( slaves: Seq[TLSlaveParameters] = slaves, channelBytes: TLChannelBeatBytes = channelBytes, endSinkId: Int = endSinkId, minLatency: Int = minLatency, responseFields: Seq[BundleFieldBase] = responseFields, requestKeys: Seq[BundleKeyBase] = requestKeys) = { new TLSlavePortParameters( slaves = slaves, channelBytes = channelBytes, endSinkId = endSinkId, minLatency = minLatency, responseFields = responseFields, requestKeys = requestKeys) } @deprecated("Use v1copy instead of copy","") def copy( managers: Seq[TLSlaveParameters] = slaves, beatBytes: Int = -1, endSinkId: Int = endSinkId, minLatency: Int = minLatency, responseFields: Seq[BundleFieldBase] = responseFields, requestKeys: Seq[BundleKeyBase] = requestKeys) = { v1copy( managers, beatBytes, endSinkId, minLatency, responseFields, requestKeys) } } object TLSlavePortParameters { def v1( managers: Seq[TLSlaveParameters], beatBytes: Int, endSinkId: Int = 0, minLatency: Int = 0, responseFields: Seq[BundleFieldBase] = Nil, requestKeys: Seq[BundleKeyBase] = Nil) = { new TLSlavePortParameters( slaves = managers, channelBytes = TLChannelBeatBytes(beatBytes), endSinkId = endSinkId, minLatency = minLatency, responseFields = responseFields, requestKeys = requestKeys) } } object TLManagerPortParameters { @deprecated("Use TLSlavePortParameters.v1 instead of TLManagerPortParameters","") def apply( managers: Seq[TLSlaveParameters], beatBytes: Int, endSinkId: Int = 0, minLatency: Int = 0, responseFields: Seq[BundleFieldBase] = Nil, requestKeys: Seq[BundleKeyBase] = Nil) = { TLSlavePortParameters.v1( managers, beatBytes, endSinkId, minLatency, responseFields, requestKeys) } } class TLMasterParameters private( val nodePath: Seq[BaseNode], val resources: Seq[Resource], val name: String, val visibility: Seq[AddressSet], val unusedRegionTypes: Set[RegionType.T], val executesOnly: Boolean, val requestFifo: Boolean, // only a request, not a requirement. applies to A, not C. val supports: TLSlaveToMasterTransferSizes, val emits: TLMasterToSlaveTransferSizes, val neverReleasesData: Boolean, val sourceId: IdRange) extends SimpleProduct { override def canEqual(that: Any): Boolean = that.isInstanceOf[TLMasterParameters] override def productPrefix = "TLMasterParameters" // We intentionally omit nodePath for equality testing / formatting def productArity: Int = 10 def productElement(n: Int): Any = n match { case 0 => name case 1 => sourceId case 2 => resources case 3 => visibility case 4 => unusedRegionTypes case 5 => executesOnly case 6 => requestFifo case 7 => supports case 8 => emits case 9 => neverReleasesData case _ => throw new IndexOutOfBoundsException(n.toString) } require (!sourceId.isEmpty) require (!visibility.isEmpty) require (supports.putFull.contains(supports.putPartial)) // We only support these operations if we support Probe (ie: we're a cache) require (supports.probe.contains(supports.arithmetic)) require (supports.probe.contains(supports.logical)) require (supports.probe.contains(supports.get)) require (supports.probe.contains(supports.putFull)) require (supports.probe.contains(supports.putPartial)) require (supports.probe.contains(supports.hint)) visibility.combinations(2).foreach { case Seq(x,y) => require (!x.overlaps(y), s"$x and $y overlap.") } val maxTransfer = List( supports.probe.max, supports.arithmetic.max, supports.logical.max, supports.get.max, supports.putFull.max, supports.putPartial.max).max def infoString = { s"""Master Name = ${name} \|visibility = ${visibility} \|emits = ${emits.infoString} \|sourceId = ${sourceId} \| \|""".stripMargin } def v1copy( name: String = name, sourceId: IdRange = sourceId, nodePath: Seq[BaseNode] = nodePath, requestFifo: Boolean = requestFifo, visibility: Seq[AddressSet] = visibility, supportsProbe: TransferSizes = supports.probe, supportsArithmetic: TransferSizes = supports.arithmetic, supportsLogical: TransferSizes = supports.logical, supportsGet: TransferSizes = supports.get, supportsPutFull: TransferSizes = supports.putFull, supportsPutPartial: TransferSizes = supports.putPartial, supportsHint: TransferSizes = supports.hint) = { new TLMasterParameters( nodePath = nodePath, resources = this.resources, name = name, visibility = visibility, unusedRegionTypes = this.unusedRegionTypes, executesOnly = this.executesOnly, requestFifo = requestFifo, supports = TLSlaveToMasterTransferSizes( probe = supportsProbe, arithmetic = supportsArithmetic, logical = supportsLogical, get = supportsGet, putFull = supportsPutFull, putPartial = supportsPutPartial, hint = supportsHint), emits = this.emits, neverReleasesData = this.neverReleasesData, sourceId = sourceId) } def v2copy( nodePath: Seq[BaseNode] = nodePath, resources: Seq[Resource] = resources, name: String = name, visibility: Seq[AddressSet] = visibility, unusedRegionTypes: Set[RegionType.T] = unusedRegionTypes, executesOnly: Boolean = executesOnly, requestFifo: Boolean = requestFifo, supports: TLSlaveToMasterTransferSizes = supports, emits: TLMasterToSlaveTransferSizes = emits, neverReleasesData: Boolean = neverReleasesData, sourceId: IdRange = sourceId) = { new TLMasterParameters( nodePath = nodePath, resources = resources, name = name, visibility = visibility, unusedRegionTypes = unusedRegionTypes, executesOnly = executesOnly, requestFifo = requestFifo, supports = supports, emits = emits, neverReleasesData = neverReleasesData, sourceId = sourceId) } @deprecated("Use v1copy instead of copy","") def copy( name: String = name, sourceId: IdRange = sourceId, nodePath: Seq[BaseNode] = nodePath, requestFifo: Boolean = requestFifo, visibility: Seq[AddressSet] = visibility, supportsProbe: TransferSizes = supports.probe, supportsArithmetic: TransferSizes = supports.arithmetic, supportsLogical: TransferSizes = supports.logical, supportsGet: TransferSizes = supports.get, supportsPutFull: TransferSizes = supports.putFull, supportsPutPartial: TransferSizes = supports.putPartial, supportsHint: TransferSizes = supports.hint) = { v1copy( name = name, sourceId = sourceId, nodePath = nodePath, requestFifo = requestFifo, visibility = visibility, supportsProbe = supportsProbe, supportsArithmetic = supportsArithmetic, supportsLogical = supportsLogical, supportsGet = supportsGet, supportsPutFull = supportsPutFull, supportsPutPartial = supportsPutPartial, supportsHint = supportsHint) } } object TLMasterParameters { def v1( name: String, sourceId: IdRange = IdRange(0,1), nodePath: Seq[BaseNode] = Seq(), requestFifo: Boolean = false, visibility: Seq[AddressSet] = Seq(AddressSet(0, ~0)), supportsProbe: TransferSizes = TransferSizes.none, supportsArithmetic: TransferSizes = TransferSizes.none, supportsLogical: TransferSizes = TransferSizes.none, supportsGet: TransferSizes = TransferSizes.none, supportsPutFull: TransferSizes = TransferSizes.none, supportsPutPartial: TransferSizes = TransferSizes.none, supportsHint: TransferSizes = TransferSizes.none) = { new TLMasterParameters( nodePath = nodePath, resources = Nil, name = name, visibility = visibility, unusedRegionTypes = Set(), executesOnly = false, requestFifo = requestFifo, supports = TLSlaveToMasterTransferSizes( probe = supportsProbe, arithmetic = supportsArithmetic, logical = supportsLogical, get = supportsGet, putFull = supportsPutFull, putPartial = supportsPutPartial, hint = supportsHint), emits = TLMasterToSlaveTransferSizes.unknownEmits, neverReleasesData = false, sourceId = sourceId) } def v2( nodePath: Seq[BaseNode] = Seq(), resources: Seq[Resource] = Nil, name: String, visibility: Seq[AddressSet] = Seq(AddressSet(0, ~0)), unusedRegionTypes: Set[RegionType.T] = Set(), executesOnly: Boolean = false, requestFifo: Boolean = false, supports: TLSlaveToMasterTransferSizes = TLSlaveToMasterTransferSizes.unknownSupports, emits: TLMasterToSlaveTransferSizes = TLMasterToSlaveTransferSizes.unknownEmits, neverReleasesData: Boolean = false, sourceId: IdRange = IdRange(0,1)) = { new TLMasterParameters( nodePath = nodePath, resources = resources, name = name, visibility = visibility, unusedRegionTypes = unusedRegionTypes, executesOnly = executesOnly, requestFifo = requestFifo, supports = supports, emits = emits, neverReleasesData = neverReleasesData, sourceId = sourceId) } } object TLClientParameters { @deprecated("Use TLMasterParameters.v1 instead of TLClientParameters","") def apply( name: String, sourceId: IdRange = IdRange(0,1), nodePath: Seq[BaseNode] = Seq(), requestFifo: Boolean = false, visibility: Seq[AddressSet] = Seq(AddressSet.everything), supportsProbe: TransferSizes = TransferSizes.none, supportsArithmetic: TransferSizes = TransferSizes.none, supportsLogical: TransferSizes = TransferSizes.none, supportsGet: TransferSizes = TransferSizes.none, supportsPutFull: TransferSizes = TransferSizes.none, supportsPutPartial: TransferSizes = TransferSizes.none, supportsHint: TransferSizes = TransferSizes.none) = { TLMasterParameters.v1( name = name, sourceId = sourceId, nodePath = nodePath, requestFifo = requestFifo, visibility = visibility, supportsProbe = supportsProbe, supportsArithmetic = supportsArithmetic, supportsLogical = supportsLogical, supportsGet = supportsGet, supportsPutFull = supportsPutFull, supportsPutPartial = supportsPutPartial, supportsHint = supportsHint) } } class TLMasterPortParameters private( val masters: Seq[TLMasterParameters], val channelBytes: TLChannelBeatBytes, val minLatency: Int, val echoFields: Seq[BundleFieldBase], val requestFields: Seq[BundleFieldBase], val responseKeys: Seq[BundleKeyBase]) extends SimpleProduct { override def canEqual(that: Any): Boolean = that.isInstanceOf[TLMasterPortParameters] override def productPrefix = "TLMasterPortParameters" def productArity: Int = 6 def productElement(n: Int): Any = n match { case 0 => masters case 1 => channelBytes case 2 => minLatency case 3 => echoFields case 4 => requestFields case 5 => responseKeys case _ => throw new IndexOutOfBoundsException(n.toString) } require (!masters.isEmpty) require (minLatency >= 0) def clients = masters // Require disjoint ranges for Ids IdRange.overlaps(masters.map(_.sourceId)).foreach { case (x, y) => require (!x.overlaps(y), s"TLClientParameters.sourceId ${x} overlaps ${y}") } // Bounds on required sizes def endSourceId = masters.map(_.sourceId.end).max def maxTransfer = masters.map(_.maxTransfer).max // The unused sources < endSourceId def unusedSources: Seq[Int] = { val usedSources = masters.map(_.sourceId).sortBy(_.start) ((Seq(0) ++ usedSources.map(_.end)) zip usedSources.map(_.start)) flatMap { case (end, start) => end until start } } // Diplomatically determined operation sizes emitted by all inward Masters // as opposed to emits* which generate circuitry to check which specific addresses val allEmitClaims = masters.map(_.emits).reduce( _ intersect _) // Diplomatically determined operation sizes Emitted by at least one inward Masters // as opposed to emits* which generate circuitry to check which specific addresses val anyEmitClaims = masters.map(_.emits).reduce(_ mincover _) // Diplomatically determined operation sizes supported by all inward Masters // as opposed to supports* which generate circuitry to check which specific addresses val allSupportProbe = masters.map(_.supports.probe) .reduce(_ intersect _) val allSupportArithmetic = masters.map(_.supports.arithmetic).reduce(_ intersect _) val allSupportLogical = masters.map(_.supports.logical) .reduce(_ intersect _) val allSupportGet = masters.map(_.supports.get) .reduce(_ intersect _) val allSupportPutFull = masters.map(_.supports.putFull) .reduce(_ intersect _) val allSupportPutPartial = masters.map(_.supports.putPartial).reduce(_ intersect _) val allSupportHint = masters.map(_.supports.hint) .reduce(_ intersect _) // Diplomatically determined operation sizes supported by at least one master // as opposed to supports* which generate circuitry to check which specific addresses val anySupportProbe = masters.map(!_.supports.probe.none) .reduce(_ \|\| _) val anySupportArithmetic = masters.map(!_.supports.arithmetic.none).reduce(_ \|\| _) val anySupportLogical = masters.map(!_.supports.logical.none) .reduce(_ \|\| _) val anySupportGet = masters.map(!_.supports.get.none) .reduce(_ \|\| _) val anySupportPutFull = masters.map(!_.supports.putFull.none) .reduce(_ \|\| _) val anySupportPutPartial = masters.map(!_.supports.putPartial.none).reduce(_ \|\| _) val anySupportHint = masters.map(!_.supports.hint.none) .reduce(_ \|\| _) // These return Option[TLMasterParameters] for your convenience def find(id: Int) = masters.find(_.sourceId.contains(id)) // Synthesizable lookup methods def find(id: UInt) = VecInit(masters.map(_.sourceId.contains(id))) def contains(id: UInt) = find(id).reduce(_ \|\| _) def requestFifo(id: UInt) = Mux1H(find(id), masters.map(c => c.requestFifo.B)) // Available during RTL runtime, checks to see if (id, size) is supported by the master's (client's) diplomatic parameters private def sourceIdHelper(member: TLMasterParameters => TransferSizes)(id: UInt, lgSize: UInt) = { val allSame = masters.map(member(_) == member(masters(0))).reduce(_ && _) // this if statement is a coarse generalization of the groupBy in the sourceIdHelper2 version; // the case where there is only one group. if (allSame) member(masters(0)).containsLg(lgSize) else { // Find the master associated with ID and returns whether that particular master is able to receive transaction of lgSize Mux1H(find(id), masters.map(member(_).containsLg(lgSize))) } } // Check for support of a given operation at a specific id val supportsProbe = sourceIdHelper(_.supports.probe) _ val supportsArithmetic = sourceIdHelper(_.supports.arithmetic) _ val supportsLogical = sourceIdHelper(_.supports.logical) _ val supportsGet = sourceIdHelper(_.supports.get) _ val supportsPutFull = sourceIdHelper(_.supports.putFull) _ val supportsPutPartial = sourceIdHelper(_.supports.putPartial) _ val supportsHint = sourceIdHelper(_.supports.hint) _ // TODO: Merge sourceIdHelper2 with sourceIdHelper private def sourceIdHelper2( member: TLMasterParameters => TransferSizes, sourceId: UInt, lgSize: UInt): Bool = { // Because sourceIds are uniquely owned by each master, we use them to group the // cases that have to be checked. val emitCases = groupByIntoSeq(masters)(m => member(m)).map { case (k, vs) => k -> vs.map(_.sourceId) } emitCases.map { case (s, a) => (s.containsLg(lgSize)) && a.map(_.contains(sourceId)).reduce(_\|\|_) }.foldLeft(false.B)(_\|\|_) } // Check for emit of a given operation at a specific id def emitsAcquireT (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.acquireT, sourceId, lgSize) def emitsAcquireB (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.acquireB, sourceId, lgSize) def emitsArithmetic(sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.arithmetic, sourceId, lgSize) def emitsLogical (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.logical, sourceId, lgSize) def emitsGet (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.get, sourceId, lgSize) def emitsPutFull (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.putFull, sourceId, lgSize) def emitsPutPartial(sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.putPartial, sourceId, lgSize) def emitsHint (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.hint, sourceId, lgSize) def infoString = masters.map(_.infoString).mkString def v1copy( clients: Seq[TLMasterParameters] = masters, minLatency: Int = minLatency, echoFields: Seq[BundleFieldBase] = echoFields, requestFields: Seq[BundleFieldBase] = requestFields, responseKeys: Seq[BundleKeyBase] = responseKeys) = { new TLMasterPortParameters( masters = clients, channelBytes = channelBytes, minLatency = minLatency, echoFields = echoFields, requestFields = requestFields, responseKeys = responseKeys) } def v2copy( masters: Seq[TLMasterParameters] = masters, channelBytes: TLChannelBeatBytes = channelBytes, minLatency: Int = minLatency, echoFields: Seq[BundleFieldBase] = echoFields, requestFields: Seq[BundleFieldBase] = requestFields, responseKeys: Seq[BundleKeyBase] = responseKeys) = { new TLMasterPortParameters( masters = masters, channelBytes = channelBytes, minLatency = minLatency, echoFields = echoFields, requestFields = requestFields, responseKeys = responseKeys) } @deprecated("Use v1copy instead of copy","") def copy( clients: Seq[TLMasterParameters] = masters, minLatency: Int = minLatency, echoFields: Seq[BundleFieldBase] = echoFields, requestFields: Seq[BundleFieldBase] = requestFields, responseKeys: Seq[BundleKeyBase] = responseKeys) = { v1copy( clients, minLatency, echoFields, requestFields, responseKeys) } } object TLClientPortParameters { @deprecated("Use TLMasterPortParameters.v1 instead of TLClientPortParameters","") def apply( clients: Seq[TLMasterParameters], minLatency: Int = 0, echoFields: Seq[BundleFieldBase] = Nil, requestFields: Seq[BundleFieldBase] = Nil, responseKeys: Seq[BundleKeyBase] = Nil) = { TLMasterPortParameters.v1( clients, minLatency, echoFields, requestFields, responseKeys) } } object TLMasterPortParameters { def v1( clients: Seq[TLMasterParameters], minLatency: Int = 0, echoFields: Seq[BundleFieldBase] = Nil, requestFields: Seq[BundleFieldBase] = Nil, responseKeys: Seq[BundleKeyBase] = Nil) = { new TLMasterPortParameters( masters = clients, channelBytes = TLChannelBeatBytes(), minLatency = minLatency, echoFields = echoFields, requestFields = requestFields, responseKeys = responseKeys) } def v2( masters: Seq[TLMasterParameters], channelBytes: TLChannelBeatBytes = TLChannelBeatBytes(), minLatency: Int = 0, echoFields: Seq[BundleFieldBase] = Nil, requestFields: Seq[BundleFieldBase] = Nil, responseKeys: Seq[BundleKeyBase] = Nil) = { new TLMasterPortParameters( masters = masters, channelBytes = channelBytes, minLatency = minLatency, echoFields = echoFields, requestFields = requestFields, responseKeys = responseKeys) } } case class TLBundleParameters( addressBits: Int, dataBits: Int, sourceBits: Int, sinkBits: Int, sizeBits: Int, echoFields: Seq[BundleFieldBase], requestFields: Seq[BundleFieldBase], responseFields: Seq[BundleFieldBase], hasBCE: Boolean) { // Chisel has issues with 0-width wires require (addressBits >= 1) require (dataBits >= 8) require (sourceBits >= 1) require (sinkBits >= 1) require (sizeBits >= 1) require (isPow2(dataBits)) echoFields.foreach { f => require (f.key.isControl, s"${f} is not a legal echo field") } val addrLoBits = log2Up(dataBits/8) // Used to uniquify bus IP names def shortName = s"a${addressBits}d${dataBits}s${sourceBits}k${sinkBits}z${sizeBits}" + (if (hasBCE) "c" else "u") def union(x: TLBundleParameters) = TLBundleParameters( max(addressBits, x.addressBits), max(dataBits, x.dataBits), max(sourceBits, x.sourceBits), max(sinkBits, x.sinkBits), max(sizeBits, x.sizeBits), echoFields = BundleField.union(echoFields ++ x.echoFields), requestFields = BundleField.union(requestFields ++ x.requestFields), responseFields = BundleField.union(responseFields ++ x.responseFields), hasBCE \|\| x.hasBCE) } object TLBundleParameters { val emptyBundleParams = TLBundleParameters( addressBits = 1, dataBits = 8, sourceBits = 1, sinkBits = 1, sizeBits = 1, echoFields = Nil, requestFields = Nil, responseFields = Nil, hasBCE = false) def union(x: Seq[TLBundleParameters]) = x.foldLeft(emptyBundleParams)((x,y) => x.union(y)) def apply(master: TLMasterPortParameters, slave: TLSlavePortParameters) = new TLBundleParameters( addressBits = log2Up(slave.maxAddress + 1), dataBits = slave.beatBytes * 8, sourceBits = log2Up(master.endSourceId), sinkBits = log2Up(slave.endSinkId), sizeBits = log2Up(log2Ceil(max(master.maxTransfer, slave.maxTransfer))+1), echoFields = master.echoFields, requestFields = BundleField.accept(master.requestFields, slave.requestKeys), responseFields = BundleField.accept(slave.responseFields, master.responseKeys), hasBCE = master.anySupportProbe && slave.anySupportAcquireB) } case class TLEdgeParameters( master: TLMasterPortParameters, slave: TLSlavePortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge { // legacy names: def manager = slave def client = master val maxTransfer = max(master.maxTransfer, slave.maxTransfer) val maxLgSize = log2Ceil(maxTransfer) // Sanity check the link... require (maxTransfer >= slave.beatBytes, s"Link's max transfer (${maxTransfer}) < ${slave.slaves.map(_.name)}'s beatBytes (${slave.beatBytes})") def diplomaticClaimsMasterToSlave = master.anyEmitClaims.intersect(slave.anySupportClaims) val bundle = TLBundleParameters(master, slave) def formatEdge = master.infoString + "\n" + slave.infoString } case class TLCreditedDelay( a: CreditedDelay, b: CreditedDelay, c: CreditedDelay, d: CreditedDelay, e: CreditedDelay) { def + (that: TLCreditedDelay): TLCreditedDelay = TLCreditedDelay( a = a + that.a, b = b + that.b, c = c + that.c, d = d + that.d, e = e + that.e) override def toString = s"(${a}, ${b}, ${c}, ${d}, ${e})" } object TLCreditedDelay { def apply(delay: CreditedDelay): TLCreditedDelay = apply(delay, delay.flip, delay, delay.flip, delay) } case class TLCreditedManagerPortParameters(delay: TLCreditedDelay, base: TLSlavePortParameters) {def infoString = base.infoString} case class TLCreditedClientPortParameters(delay: TLCreditedDelay, base: TLMasterPortParameters) {def infoString = base.infoString} case class TLCreditedEdgeParameters(client: TLCreditedClientPortParameters, manager: TLCreditedManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge { val delay = client.delay + manager.delay val bundle = TLBundleParameters(client.base, manager.base) def formatEdge = client.infoString + "\n" + manager.infoString } case class TLAsyncManagerPortParameters(async: AsyncQueueParams, base: TLSlavePortParameters) {def infoString = base.infoString} case class TLAsyncClientPortParameters(base: TLMasterPortParameters) {def infoString = base.infoString} case class TLAsyncBundleParameters(async: AsyncQueueParams, base: TLBundleParameters) case class TLAsyncEdgeParameters(client: TLAsyncClientPortParameters, manager: TLAsyncManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge { val bundle = TLAsyncBundleParameters(manager.async, TLBundleParameters(client.base, manager.base)) def formatEdge = client.infoString + "\n" + manager.infoString } case class TLRationalManagerPortParameters(direction: RationalDirection, base: TLSlavePortParameters) {def infoString = base.infoString} case class TLRationalClientPortParameters(base: TLMasterPortParameters) {def infoString = base.infoString} case class TLRationalEdgeParameters(client: TLRationalClientPortParameters, manager: TLRationalManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge { val bundle = TLBundleParameters(client.base, manager.base) def formatEdge = client.infoString + "\n" + manager.infoString } // To be unified, devices must agree on all of these terms case class ManagerUnificationKey( resources: Seq[Resource], regionType: RegionType.T, executable: Boolean, supportsAcquireT: TransferSizes, supportsAcquireB: TransferSizes, supportsArithmetic: TransferSizes, supportsLogical: TransferSizes, supportsGet: TransferSizes, supportsPutFull: TransferSizes, supportsPutPartial: TransferSizes, supportsHint: TransferSizes) object ManagerUnificationKey { def apply(x: TLSlaveParameters): ManagerUnificationKey = ManagerUnificationKey( resources = x.resources, regionType = x.regionType, executable = x.executable, supportsAcquireT = x.supportsAcquireT, supportsAcquireB = x.supportsAcquireB, supportsArithmetic = x.supportsArithmetic, supportsLogical = x.supportsLogical, supportsGet = x.supportsGet, supportsPutFull = x.supportsPutFull, supportsPutPartial = x.supportsPutPartial, supportsHint = x.supportsHint) } object ManagerUnification { def apply(slaves: Seq[TLSlaveParameters]): List[TLSlaveParameters] = { slaves.groupBy(ManagerUnificationKey.apply).values.map { seq => val agree = seq.forall(_.fifoId == seq.head.fifoId) seq(0).v1copy( address = AddressSet.unify(seq.flatMap(_.address)), fifoId = if (agree) seq(0).fifoId else None) }.toList } } case class TLBufferParams( a: BufferParams = BufferParams.none, b: BufferParams = BufferParams.none, c: BufferParams = BufferParams.none, d: BufferParams = BufferParams.none, e: BufferParams = BufferParams.none ) extends DirectedBuffers[TLBufferParams] { def copyIn(x: BufferParams) = this.copy(b = x, d = x) def copyOut(x: BufferParams) = this.copy(a = x, c = x, e = x) def copyInOut(x: BufferParams) = this.copyIn(x).copyOut(x) } /** Pretty printing of TL source id maps / class TLSourceIdMap(tl: TLMasterPortParameters) extends IdMap[TLSourceIdMapEntry] { private val tlDigits = String.valueOf(tl.endSourceId-1).length() protected val fmt = s"\t[%${tlDigits}d, %${tlDigits}d) %s%s%s" private val sorted = tl.masters.sortBy(_.sourceId) val mapping: Seq[TLSourceIdMapEntry] = sorted.map { case c => TLSourceIdMapEntry(c.sourceId, c.name, c.supports.probe, c.requestFifo) } } case class TLSourceIdMapEntry(tlId: IdRange, name: String, isCache: Boolean, requestFifo: Boolean) extends IdMapEntry { val from = tlId val to = tlId val maxTransactionsInFlight = Some(tlId.size) } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportPutFull \|\| manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB \|\| manager.anySupportGet \|\| manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportPutFull \|\| client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe \|\| client.anySupportGet \|\| client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet \|\| client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull \|\| client.anySupportPutPartial \|\| client.anySupportHint \|\| client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet \|\| manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull \|\| manager.anySupportPutPartial \|\| manager.anySupportHint \|\| manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) \|\| !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.ProbeAckData \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode \| small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U \|\| beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }	module TLMonitor_11( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [3:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [31:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7] wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_a_bits_source = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_source = 1'h0; // @[Monitor.scala:36:7] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire c_set = 1'h0; // @[Monitor.scala:738:34] wire c_set_wo_ready = 1'h0; // @[Monitor.scala:739:34] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire _source_ok_T = 1'h1; // @[Parameters.scala:46:9] wire _source_ok_WIRE_0 = 1'h1; // @[Parameters.scala:1138:31] wire _source_ok_T_1 = 1'h1; // @[Parameters.scala:46:9] wire _source_ok_WIRE_1_0 = 1'h1; // @[Parameters.scala:1138:31] wire sink_ok = 1'h1; // @[Monitor.scala:309:31] wire _same_cycle_resp_T_2 = 1'h1; // @[Monitor.scala:684:113] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire _same_cycle_resp_T_8 = 1'h1; // @[Monitor.scala:795:113] wire [8:0] c_first_beats1_decode = 9'h0; // @[Edges.scala:220:59] wire [8:0] c_first_beats1 = 9'h0; // @[Edges.scala:221:14] wire [8:0] _c_first_count_T = 9'h0; // @[Edges.scala:234:27] wire [8:0] c_first_count = 9'h0; // @[Edges.scala:234:25] wire [8:0] _c_first_counter_T = 9'h0; // @[Edges.scala:236:21] wire [8:0] c_first_counter1 = 9'h1FF; // @[Edges.scala:230:28] wire [9:0] _c_first_counter1_T = 10'h3FF; // @[Edges.scala:230:28] wire [2:0] io_in_a_bits_param = 3'h0; // @[Monitor.scala:36:7] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [31:0] _c_first_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_first_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_wo_ready_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_wo_ready_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_4_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_5_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [3:0] _a_opcode_lookup_T = 4'h0; // @[Monitor.scala:637:69] wire [3:0] _a_size_lookup_T = 4'h0; // @[Monitor.scala:641:65] wire [3:0] _a_opcodes_set_T = 4'h0; // @[Monitor.scala:659:79] wire [3:0] _a_sizes_set_T = 4'h0; // @[Monitor.scala:660:77] wire [3:0] _d_opcodes_clr_T_4 = 4'h0; // @[Monitor.scala:680:101] wire [3:0] _d_sizes_clr_T_4 = 4'h0; // @[Monitor.scala:681:99] wire [3:0] _c_first_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] c_opcodes_set = 4'h0; // @[Monitor.scala:740:34] wire [3:0] _c_opcode_lookup_T = 4'h0; // @[Monitor.scala:749:69] wire [3:0] _c_size_lookup_T = 4'h0; // @[Monitor.scala:750:67] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] _c_set_wo_ready_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_wo_ready_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_sizes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_T = 4'h0; // @[Monitor.scala:767:79] wire [3:0] _c_sizes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_sizes_set_T = 4'h0; // @[Monitor.scala:768:77] wire [3:0] _c_probe_ack_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _d_opcodes_clr_T_10 = 4'h0; // @[Monitor.scala:790:101] wire [3:0] _d_sizes_clr_T_10 = 4'h0; // @[Monitor.scala:791:99] wire [3:0] _same_cycle_resp_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_4_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_5_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [30:0] _d_sizes_clr_T_5 = 31'hFF; // @[Monitor.scala:681:74] wire [30:0] _d_sizes_clr_T_11 = 31'hFF; // @[Monitor.scala:791:74] wire [15:0] _a_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _c_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hFF; // @[Monitor.scala:724:57] wire [16:0] _a_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _c_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hFF; // @[Monitor.scala:724:57] wire [15:0] _a_size_lookup_T_3 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _c_size_lookup_T_3 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h100; // @[Monitor.scala:724:51] wire [30:0] _d_opcodes_clr_T_5 = 31'hF; // @[Monitor.scala:680:76] wire [30:0] _d_opcodes_clr_T_11 = 31'hF; // @[Monitor.scala:790:76] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [1:0] _a_set_wo_ready_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _a_set_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _d_clr_wo_ready_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _d_clr_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _c_set_wo_ready_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _c_set_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _d_clr_wo_ready_T_1 = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _d_clr_T_1 = 2'h1; // @[OneHot.scala:58:35] wire [19:0] _c_sizes_set_T_1 = 20'h0; // @[Monitor.scala:768:52] wire [18:0] _c_opcodes_set_T_1 = 19'h0; // @[Monitor.scala:767:54] wire [4:0] _c_sizes_set_interm_T_1 = 5'h1; // @[Monitor.scala:766:59] wire [4:0] c_sizes_set_interm = 5'h0; // @[Monitor.scala:755:40] wire [4:0] _c_sizes_set_interm_T = 5'h0; // @[Monitor.scala:766:51] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [7:0] c_sizes_set = 8'h0; // @[Monitor.scala:741:34] wire [11:0] _c_first_beats1_decode_T_2 = 12'h0; // @[package.scala:243:46] wire [11:0] _c_first_beats1_decode_T_1 = 12'hFFF; // @[package.scala:243:76] wire [26:0] _c_first_beats1_decode_T = 27'hFFF; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [3:0] _a_size_lookup_T_2 = 4'h8; // @[Monitor.scala:641:117] wire [3:0] _d_sizes_clr_T = 4'h8; // @[Monitor.scala:681:48] wire [3:0] _c_size_lookup_T_2 = 4'h8; // @[Monitor.scala:750:119] wire [3:0] _d_sizes_clr_T_6 = 4'h8; // @[Monitor.scala:791:48] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire [26:0] _GEN = 27'hFFF << io_in_a_bits_size_0; // @[package.scala:243:71] wire [26:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [11:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [31:0] _is_aligned_T = {20'h0, io_in_a_bits_address_0[11:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 32'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 4'h2; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 \| _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 \| _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 \| _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 \| _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 \| _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 \| _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 \| _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 \| _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire _T_1222 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_1222; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_1222; // @[Decoupled.scala:51:35] wire [11:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [8:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [8:0] a_first_counter; // @[Edges.scala:229:27] wire [9:0] _a_first_counter1_T = {1'h0, a_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] a_first_counter1 = _a_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T \| _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [8:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [3:0] size; // @[Monitor.scala:389:22] reg [31:0] address; // @[Monitor.scala:391:22] wire _T_1295 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_1295; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_1295; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_1295; // @[Decoupled.scala:51:35] wire [26:0] _GEN_0 = 27'hFFF << io_in_d_bits_size_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [11:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [8:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T = {1'h0, d_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1 = _d_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T \| _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [3:0] size_1; // @[Monitor.scala:540:22] reg [2:0] sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] reg [1:0] inflight; // @[Monitor.scala:614:27] reg [3:0] inflight_opcodes; // @[Monitor.scala:616:35] wire [3:0] _a_opcode_lookup_T_1 = inflight_opcodes; // @[Monitor.scala:616:35, :637:44] reg [7:0] inflight_sizes; // @[Monitor.scala:618:33] wire [7:0] _a_size_lookup_T_1 = inflight_sizes; // @[Monitor.scala:618:33, :641:40] wire [11:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [8:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [8:0] a_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] a_first_counter1_1 = _a_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 \| _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [11:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_1 = _d_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 \| _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire a_set; // @[Monitor.scala:626:34] wire a_set_wo_ready; // @[Monitor.scala:627:34] wire [3:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [7:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [15:0] _a_opcode_lookup_T_6 = {12'h0, _a_opcode_lookup_T_1}; // @[Monitor.scala:637:{44,97}] wire [15:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [7:0] a_size_lookup; // @[Monitor.scala:639:33] wire [15:0] _a_size_lookup_T_6 = {8'h0, _a_size_lookup_T_1}; // @[Monitor.scala:641:{40,91}] wire [15:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[15:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[7:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [4:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _T_1145 = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26] assign a_set_wo_ready = _T_1145; // @[Monitor.scala:627:34, :651:26] wire _same_cycle_resp_T; // @[Monitor.scala:684:44] assign _same_cycle_resp_T = _T_1145; // @[Monitor.scala:651:26, :684:44] assign a_set = _T_1222 & a_first_1; // @[Decoupled.scala:51:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = a_set ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:626:34, :646:40, :655:70, :657:{28,61}] wire [4:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [4:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = a_set ? _a_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:626:34, :648:38, :655:70, :658:{28,59}] wire [18:0] _a_opcodes_set_T_1 = {15'h0, a_opcodes_set_interm}; // @[Monitor.scala:646:40, :659:54] assign a_opcodes_set = a_set ? _a_opcodes_set_T_1[3:0] : 4'h0; // @[Monitor.scala:626:34, :630:33, :655:70, :659:{28,54}] wire [19:0] _a_sizes_set_T_1 = {15'h0, a_sizes_set_interm}; // @[Monitor.scala:648:38, :660:52] assign a_sizes_set = a_set ? _a_sizes_set_T_1[7:0] : 8'h0; // @[Monitor.scala:626:34, :632:31, :655:70, :660:{28,52}] wire d_clr; // @[Monitor.scala:664:34] wire d_clr_wo_ready; // @[Monitor.scala:665:34] wire [3:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [7:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_1 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_1; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_1; // @[Monitor.scala:673:46, :783:46] wire _T_1194 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] assign d_clr_wo_ready = _T_1194 & ~d_release_ack; // @[Monitor.scala:665:34, :673:46, :674:{26,71,74}] assign d_clr = _T_1295 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_opcodes_clr = {4{d_clr}}; // @[Monitor.scala:664:34, :668:33, :678:89, :680:21] assign d_sizes_clr = {8{d_clr}}; // @[Monitor.scala:664:34, :670:31, :678:89, :681:21] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire same_cycle_resp = _same_cycle_resp_T_1; // @[Monitor.scala:684:{55,88}] wire [1:0] _inflight_T = {inflight[1], inflight[0] \| a_set}; // @[Monitor.scala:614:27, :626:34, :705:27] wire _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [1:0] _inflight_T_2 = {1'h0, _inflight_T[0] & _inflight_T_1}; // @[Monitor.scala:705:{27,36,38}] wire [3:0] _inflight_opcodes_T = inflight_opcodes \| a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [3:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [3:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [7:0] _inflight_sizes_T = inflight_sizes \| a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [7:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [7:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [1:0] inflight_1; // @[Monitor.scala:726:35] wire [1:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [3:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [3:0] _c_opcode_lookup_T_1 = inflight_opcodes_1; // @[Monitor.scala:727:35, :749:44] wire [3:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [7:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [7:0] _c_size_lookup_T_1 = inflight_sizes_1; // @[Monitor.scala:728:35, :750:42] wire [7:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire [11:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_2; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_2 = _d_first_counter1_T_2[8:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 \| _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [7:0] c_size_lookup; // @[Monitor.scala:748:35] wire [15:0] _c_opcode_lookup_T_6 = {12'h0, _c_opcode_lookup_T_1}; // @[Monitor.scala:749:{44,97}] wire [15:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [15:0] _c_size_lookup_T_6 = {8'h0, _c_size_lookup_T_1}; // @[Monitor.scala:750:{42,93}] wire [15:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[15:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[7:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire d_clr_1; // @[Monitor.scala:774:34] wire d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [3:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [7:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_1266 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_1266 & d_release_ack_1; // @[Monitor.scala:775:34, :783:46, :784:{26,71}] assign d_clr_1 = _T_1295 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_opcodes_clr_1 = {4{d_clr_1}}; // @[Monitor.scala:774:34, :776:34, :788:88, :790:21] assign d_sizes_clr_1 = {8{d_clr_1}}; // @[Monitor.scala:774:34, :777:34, :788:88, :791:21] wire _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [1:0] _inflight_T_5 = {1'h0, _inflight_T_3[0] & _inflight_T_4}; // @[Monitor.scala:814:{35,44,46}] wire [3:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [3:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [7:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [7:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to the following Chisel files. File Monitor.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceLine import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import freechips.rocketchip.diplomacy.EnableMonitors import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode} import freechips.rocketchip.util.PlusArg case class TLMonitorArgs(edge: TLEdge) abstract class TLMonitorBase(args: TLMonitorArgs) extends Module { val io = IO(new Bundle { val in = Input(new TLBundle(args.edge.bundle)) }) def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit legalize(io.in, args.edge, reset) } object TLMonitor { def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = { if (enable) { EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) } } else { node } } } class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args) { require (args.edge.params(TLMonitorStrictMode) \|\| (! args.edge.params(TestplanTestType).formal)) val cover_prop_class = PropertyClass.Default //Like assert but can flip to being an assumption for formal verification def monAssert(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir, cond, message, PropertyClass.Default) } def assume(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir.flip, cond, message, PropertyClass.Default) } def extra = { args.edge.sourceInfo match { case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)" case _ => "" } } def visible(address: UInt, source: UInt, edge: TLEdge) = edge.client.clients.map { c => !c.sourceId.contains(source) \|\| c.visibility.map(_.contains(address)).reduce(_ \|\| _) }.reduce(_ && _) def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = { //switch this flag to turn on diplomacy in error messages def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n" monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra) // Reuse these subexpressions to save some firrtl lines val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility") //The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B //TODO: check for acquireT? when (bundle.opcode === TLMessages.AcquireBlock) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra) } when (bundle.opcode === TLMessages.AcquirePerm) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra) monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra) monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra) monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra) } } def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = { monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra) monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility") // Reuse these subexpressions to save some firrtl lines val address_ok = edge.manager.containsSafe(edge.address(bundle)) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source when (bundle.opcode === TLMessages.Probe) { assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra) assume (address_ok, "'B' channel Probe carries unmanaged address" + extra) assume (legal_source, "'B' channel Probe carries source that is not first source" + extra) assume (is_aligned, "'B' channel Probe address not aligned to size" + extra) assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra) assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra) assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra) monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra) monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra) monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra) monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra) } } def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = { monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val address_ok = edge.manager.containsSafe(edge.address(bundle)) monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility") when (bundle.opcode === TLMessages.ProbeAck) { monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra) } when (bundle.opcode === TLMessages.ProbeAckData) { monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.Release) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra) monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra) } when (bundle.opcode === TLMessages.ReleaseData) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.AccessAck) { monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra) } when (bundle.opcode === TLMessages.HintAck) { monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra) } } def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = { assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val sink_ok = bundle.sink < edge.manager.endSinkId.U val deny_put_ok = edge.manager.mayDenyPut.B val deny_get_ok = edge.manager.mayDenyGet.B when (bundle.opcode === TLMessages.ReleaseAck) { assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra) assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra) assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra) } when (bundle.opcode === TLMessages.Grant) { assume (source_ok, "'D' channel Grant carries invalid source ID" + extra) assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra) assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel Grant is denied" + extra) } when (bundle.opcode === TLMessages.GrantData) { assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra) assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra) assume (!bundle.denied \|\| bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra) assume (deny_get_ok \|\| !bundle.denied, "'D' channel GrantData is denied" + extra) } when (bundle.opcode === TLMessages.AccessAck) { assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel AccessAck is denied" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra) assume (!bundle.denied \|\| bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra) assume (deny_get_ok \|\| !bundle.denied, "'D' channel AccessAckData is denied" + extra) } when (bundle.opcode === TLMessages.HintAck) { assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel HintAck is denied" + extra) } } def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = { val sink_ok = bundle.sink < edge.manager.endSinkId.U monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra) } def legalizeFormat(bundle: TLBundle, edge: TLEdge) = { when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) } when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) } when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) } when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) } } else { monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra) monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra) monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra) } } def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = { val a_first = edge.first(a.bits, a.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (a.valid && !a_first) { monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra) monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra) monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra) monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra) monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra) } when (a.fire && a_first) { opcode := a.bits.opcode param := a.bits.param size := a.bits.size source := a.bits.source address := a.bits.address } } def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = { val b_first = edge.first(b.bits, b.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (b.valid && !b_first) { monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra) monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra) monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra) monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra) monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra) } when (b.fire && b_first) { opcode := b.bits.opcode param := b.bits.param size := b.bits.size source := b.bits.source address := b.bits.address } } def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = { // Symbolic variable val sym_source = Wire(UInt(edge.client.endSourceId.W)) // TODO: Connect sym_source to a fixed value for simulation and to a // free wire in formal sym_source := 0.U // Type casting Int to UInt val maxSourceId = Wire(UInt(edge.client.endSourceId.W)) maxSourceId := edge.client.endSourceId.U // Delayed verison of sym_source val sym_source_d = Reg(UInt(edge.client.endSourceId.W)) sym_source_d := sym_source // These will be constraints for FV setup Property( MonitorDirection.Monitor, (sym_source === sym_source_d), "sym_source should remain stable", PropertyClass.Default) Property( MonitorDirection.Monitor, (sym_source <= maxSourceId), "sym_source should take legal value", PropertyClass.Default) val my_resp_pend = RegInit(false.B) val my_opcode = Reg(UInt()) val my_size = Reg(UInt()) val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire) val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire) val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source) val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source) val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat) val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend) when (my_set_resp_pend) { my_resp_pend := true.B } .elsewhen (my_clr_resp_pend) { my_resp_pend := false.B } when (my_a_first_beat) { my_opcode := bundle.a.bits.opcode my_size := bundle.a.bits.size } val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size) val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode) val my_resp_opcode_legal = Wire(Bool()) when ((my_resp_opcode === TLMessages.Get) \|\| (my_resp_opcode === TLMessages.ArithmeticData) \|\| (my_resp_opcode === TLMessages.LogicalData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData) } .elsewhen ((my_resp_opcode === TLMessages.PutFullData) \|\| (my_resp_opcode === TLMessages.PutPartialData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck) } .otherwise { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck) } monAssert (IfThen(my_resp_pend, !my_a_first_beat), "Request message should not be sent with a source ID, for which a response message" + "is already pending (not received until current cycle) for a prior request message" + "with the same source ID" + extra) assume (IfThen(my_clr_resp_pend, (my_set_resp_pend \|\| my_resp_pend)), "Response message should be accepted with a source ID only if a request message with the" + "same source ID has been accepted or is being accepted in the current cycle" + extra) assume (IfThen(my_d_first_beat, (my_a_first_beat \|\| my_resp_pend)), "Response message should be sent with a source ID only if a request message with the" + "same source ID has been accepted or is being sent in the current cycle" + extra) assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)), "If d_valid is 1, then d_size should be same as a_size of the corresponding request" + "message" + extra) assume (IfThen(my_d_first_beat, my_resp_opcode_legal), "If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" + "request message" + extra) } def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = { val c_first = edge.first(c.bits, c.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (c.valid && !c_first) { monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra) monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra) monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra) monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra) monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra) } when (c.fire && c_first) { opcode := c.bits.opcode param := c.bits.param size := c.bits.size source := c.bits.source address := c.bits.address } } def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = { val d_first = edge.first(d.bits, d.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val sink = Reg(UInt()) val denied = Reg(Bool()) when (d.valid && !d_first) { assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra) assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra) assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra) assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra) assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra) assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra) } when (d.fire && d_first) { opcode := d.bits.opcode param := d.bits.param size := d.bits.size source := d.bits.source sink := d.bits.sink denied := d.bits.denied } } def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = { legalizeMultibeatA(bundle.a, edge) legalizeMultibeatD(bundle.d, edge) if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { legalizeMultibeatB(bundle.b, edge) legalizeMultibeatC(bundle.c, edge) } } //This is left in for almond which doesn't adhere to the tilelink protocol @deprecated("Use legalizeADSource instead if possible","") def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.client.endSourceId.W)) val a_first = edge.first(bundle.a.bits, bundle.a.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val a_set = WireInit(0.U(edge.client.endSourceId.W)) when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) assume((a_set \| inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra) } if (edge.manager.minLatency > 0) { assume(a_set =/= d_clr \|\| !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight \| a_set) & ~d_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") assert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = { val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size) val log_a_size_bus_size = log2Ceil(a_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error inflight.suggestName("inflight") val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) inflight_opcodes.suggestName("inflight_opcodes") val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) inflight_sizes.suggestName("inflight_sizes") val a_first = edge.first(bundle.a.bits, bundle.a.fire) a_first.suggestName("a_first") val d_first = edge.first(bundle.d.bits, bundle.d.fire) d_first.suggestName("d_first") val a_set = WireInit(0.U(edge.client.endSourceId.W)) val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) a_set.suggestName("a_set") a_set_wo_ready.suggestName("a_set_wo_ready") val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) a_opcodes_set.suggestName("a_opcodes_set") val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) a_sizes_set.suggestName("a_sizes_set") val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W)) a_opcode_lookup.suggestName("a_opcode_lookup") a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W)) a_size_lookup.suggestName("a_size_lookup") a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant)) val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant)) val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W)) a_opcodes_set_interm.suggestName("a_opcodes_set_interm") val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W)) a_sizes_set_interm.suggestName("a_sizes_set_interm") when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) { a_set_wo_ready := UIntToOH(bundle.a.bits.source) } when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) \| 1.U a_sizes_set_interm := (bundle.a.bits.size << 1.U) \| 1.U a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U) a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U) monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) d_opcodes_clr.suggestName("d_opcodes_clr") val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) \|\| same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) \|\| (bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra) assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) \|\| (bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra) assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) { assume((!bundle.d.ready) \|\| bundle.a.ready, "ready check") } if (edge.manager.minLatency > 0) { assume(a_set_wo_ready =/= d_clr_wo_ready \|\| !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight \| a_set) & ~d_clr inflight_opcodes := (inflight_opcodes \| a_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes \| a_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = { val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size) val log_c_size_bus_size = log2Ceil(c_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) inflight.suggestName("inflight") inflight_opcodes.suggestName("inflight_opcodes") inflight_sizes.suggestName("inflight_sizes") val c_first = edge.first(bundle.c.bits, bundle.c.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) c_first.suggestName("c_first") d_first.suggestName("d_first") val c_set = WireInit(0.U(edge.client.endSourceId.W)) val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) c_set.suggestName("c_set") c_set_wo_ready.suggestName("c_set_wo_ready") c_opcodes_set.suggestName("c_opcodes_set") c_sizes_set.suggestName("c_sizes_set") val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W)) val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W)) c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U c_opcode_lookup.suggestName("c_opcode_lookup") c_size_lookup.suggestName("c_size_lookup") val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W)) val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W)) c_opcodes_set_interm.suggestName("c_opcodes_set_interm") c_sizes_set_interm.suggestName("c_sizes_set_interm") when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) { c_set_wo_ready := UIntToOH(bundle.c.bits.source) } when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) { c_set := UIntToOH(bundle.c.bits.source) c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) \| 1.U c_sizes_set_interm := (bundle.c.bits.size << 1.U) \| 1.U c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U) c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U) monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra) } val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck \|\| bundle.c.bits.opcode === TLMessages.ProbeAckData val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") d_opcodes_clr.suggestName("d_opcodes_clr") d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) \|\| same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) { assume((!bundle.d.ready) \|\| bundle.c.ready, "ready check") } if (edge.manager.minLatency > 0) { when (c_set_wo_ready.orR) { assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra) } } inflight := (inflight \| c_set) & ~d_clr inflight_opcodes := (inflight_opcodes \| c_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes \| c_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.c.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.manager.endSinkId.W)) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val e_first = true.B val d_set = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) { d_set := UIntToOH(bundle.d.bits.sink) assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra) } val e_clr = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) { e_clr := UIntToOH(bundle.e.bits.sink) monAssert((d_set \| inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra) } // edge.client.minLatency applies to BC, not DE inflight := (inflight \| d_set) & ~e_clr } def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = { val sourceBits = log2Ceil(edge.client.endSourceId) val tooBig = 14 // >16kB worth of flight information gets to be too much if (sourceBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked") } else { if (args.edge.params(TestplanTestType).simulation) { if (args.edge.params(TLMonitorStrictMode)) { legalizeADSource(bundle, edge) legalizeCDSource(bundle, edge) } else { legalizeADSourceOld(bundle, edge) } } if (args.edge.params(TestplanTestType).formal) { legalizeADSourceFormal(bundle, edge) } } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { // legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize... val sinkBits = log2Ceil(edge.manager.endSinkId) if (sinkBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked") } else { legalizeDESink(bundle, edge) } } } def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = { legalizeFormat (bundle, edge) legalizeMultibeat (bundle, edge) legalizeUnique (bundle, edge) } } File Misc.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import scala.math._ class ParameterizedBundle(implicit p: Parameters) extends Bundle trait Clocked extends Bundle { val clock = Clock() val reset = Bool() } object DecoupledHelper { def apply(rvs: Bool) = new DecoupledHelper(rvs) } class DecoupledHelper(val rvs: Seq[Bool]) { def fire(exclude: Bool, includes: Bool) = { require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!") (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _) } def fire() = { rvs.reduce(_ && _) } } object MuxT { def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2)) def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3)) def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4)) } /** Creates a cascade of n MuxTs to search for a key value. / object MuxTLookup { def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } } object ValidMux { def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]): ValidIO[T] = { apply(v1 +: v2.toSeq) } def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = { val out = Wire(Valid(valids.head.bits.cloneType)) out.valid := valids.map(_.valid).reduce(_ \|\| _) out.bits := MuxCase(valids.head.bits, valids.map(v => (v.valid -> v.bits))) out } } object Str { def apply(s: String): UInt = { var i = BigInt(0) require(s.forall(validChar _)) for (c <- s) i = (i << 8) \| c i.U((s.length8).W) } def apply(x: Char): UInt = { require(validChar(x)) x.U(8.W) } def apply(x: UInt): UInt = apply(x, 10) def apply(x: UInt, radix: Int): UInt = { val rad = radix.U val w = x.getWidth require(w > 0) var q = x var s = digit(q % rad) for (i <- 1 until ceil(log(2)/log(radix)w).toInt) { q = q / rad s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s) } s } def apply(x: SInt): UInt = apply(x, 10) def apply(x: SInt, radix: Int): UInt = { val neg = x < 0.S val abs = x.abs.asUInt if (radix != 10) { Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix)) } else { val rad = radix.U val w = abs.getWidth require(w > 0) var q = abs var s = digit(q % rad) var needSign = neg for (i <- 1 until ceil(log(2)/log(radix)w).toInt) { q = q / rad val placeSpace = q === 0.U val space = Mux(needSign, Str('-'), Str(' ')) needSign = needSign && !placeSpace s = Cat(Mux(placeSpace, space, digit(q % rad)), s) } Cat(Mux(needSign, Str('-'), Str(' ')), s) } } private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0) private def validChar(x: Char) = x == (x & 0xFF) } object Split { def apply(x: UInt, n0: Int) = { val w = x.getWidth (x.extract(w-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n2: Int, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } } object Random { def apply(mod: Int, random: UInt): UInt = { if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0) else PriorityEncoder(partition(apply(1 << log2Up(mod8), random), mod)) } def apply(mod: Int): UInt = apply(mod, randomizer) def oneHot(mod: Int, random: UInt): UInt = { if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0)) else PriorityEncoderOH(partition(apply(1 << log2Up(mod8), random), mod)).asUInt } def oneHot(mod: Int): UInt = oneHot(mod, randomizer) private def randomizer = LFSR(16) private def partition(value: UInt, slices: Int) = Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U) } object Majority { def apply(in: Set[Bool]): Bool = { val n = (in.size >> 1) + 1 val clauses = in.subsets(n).map(_.reduce(_ && _)) clauses.reduce(_ \|\| _) } def apply(in: Seq[Bool]): Bool = apply(in.toSet) def apply(in: UInt): Bool = apply(in.asBools.toSet) } object PopCountAtLeast { private def two(x: UInt): (Bool, Bool) = x.getWidth match { case 1 => (x.asBool, false.B) case n => val half = x.getWidth / 2 val (leftOne, leftTwo) = two(x(half - 1, 0)) val (rightOne, rightTwo) = two(x(x.getWidth - 1, half)) (leftOne \|\| rightOne, leftTwo \|\| rightTwo \|\| (leftOne && rightOne)) } def apply(x: UInt, n: Int): Bool = n match { case 0 => true.B case 1 => x.orR case 2 => two(x)._2 case 3 => PopCount(x) >= n.U } } // This gets used everywhere, so make the smallest circuit possible ... // Given an address and size, create a mask of beatBytes size // eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111 // groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01 object MaskGen { def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = { require (groupBy >= 1 && beatBytes >= groupBy) require (isPow2(beatBytes) && isPow2(groupBy)) val lgBytes = log2Ceil(beatBytes) val sizeOH = UIntToOH(lgSize \| 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) \| (groupBy2 - 1).U def helper(i: Int): Seq[(Bool, Bool)] = { if (i == 0) { Seq((lgSize >= lgBytes.asUInt, true.B)) } else { val sub = helper(i-1) val size = sizeOH(lgBytes - i) val bit = addr_lo(lgBytes - i) val nbit = !bit Seq.tabulate (1 << i) { j => val (sub_acc, sub_eq) = sub(j/2) val eq = sub_eq && (if (j % 2 == 1) bit else nbit) val acc = sub_acc \|\| (size && eq) (acc, eq) } } } if (groupBy == beatBytes) 1.U else Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse) } } File PlusArg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.experimental._ import chisel3.util.HasBlackBoxResource @deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05") case class PlusArgInfo(default: BigInt, docstring: String) /** Case class for PlusArg information * * @tparam A scala type of the PlusArg value * @param default optional default value * @param docstring text to include in the help * @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT) / private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String) /* Typeclass for converting a type to a doctype string * @tparam A some type / trait Doctypeable[A] { /* Return the doctype string for some option / def toDoctype(a: Option[A]): String } /* Object containing implementations of the Doctypeable typeclass / object Doctypes { /* Converts an Int => "INT" / implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" } /* Converts a BigInt => "INT" / implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" } /* Converts a String => "STRING" / implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" } } class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map( "FORMAT" -> StringParam(format), "DEFAULT" -> IntParam(default), "WIDTH" -> IntParam(width) )) with HasBlackBoxResource { val io = IO(new Bundle { val out = Output(UInt(width.W)) }) addResource("/vsrc/plusarg_reader.v") } / This wrapper class has no outputs, making it clear it is a simulation-only construct / class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module { val io = IO(new Bundle { val count = Input(UInt(width.W)) }) val max = Module(new plusarg_reader(format, default, docstring, width)).io.out when (max > 0.U) { assert (io.count < max, s"Timeout exceeded: $docstring") } } import Doctypes._ object PlusArg { /* PlusArg("foo") will return 42.U if the simulation is run with +foo=42 * Do not use this as an initial register value. The value is set in an * initial block and thus accessing it from another initial is racey. * Add a docstring to document the arg, which can be dumped in an elaboration * pass. / def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out } /* PlusArg.timeout(name, default, docstring)(count) will use chisel.assert * to kill the simulation when count exceeds the specified integer argument. * Default 0 will never assert. / def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count } } object PlusArgArtefacts { private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty / Add a new PlusArg / @deprecated( "Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05" ) def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring) /* Add a new PlusArg * * @tparam A scala type of the PlusArg value * @param name name for the PlusArg * @param default optional default value * @param docstring text to include in the help / def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit = artefacts = artefacts ++ Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default))) / From plus args, generate help text / private def serializeHelp_cHeader(tab: String = ""): String = artefacts .map{ case(arg, info) => s"""\|$tab+$arg=${info.doctype}\\n\\ \|$tab${" "20}${info.docstring}\\n\\ \|""".stripMargin ++ info.default.map{ case default => s"$tab${" "22}(default=${default})\\n\\\n"}.getOrElse("") }.toSeq.mkString("\\n\\\n") ++ "\"" / From plus args, generate a char array of their names / private def serializeArray_cHeader(tab: String = ""): String = { val prettyTab = tab + " " 44 // Length of 'static const ...' s"${tab}static const char * verilog_plusargs [] = {\\\n" ++ artefacts .map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" } .mkString("")++ s"${prettyTab}0};" } /* Generate C code to be included in emulator.cc that helps with * argument parsing based on available Verilog PlusArgs / def serialize_cHeader(): String = s"""\|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\ \|${serializeHelp_cHeader(" "7)} \|${serializeArray_cHeader()} \|""".stripMargin } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /* Like Vec.apply(idx), but tolerates indices of mismatched width / def extract(idx: UInt): T = x((idx \| 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx \| 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def \| (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a \|\| b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_\|\|_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /* Any Data subtype that has a Bool member named valid. / type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /* converts from camel case to to underscores, also removing all spaces / def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /* converts spaces or underscores to hyphens, also lowering case / def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y \| (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y \|\| y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 \| 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /* Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation / def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Bundles.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import freechips.rocketchip.util._ import scala.collection.immutable.ListMap import chisel3.util.Decoupled import chisel3.util.DecoupledIO import chisel3.reflect.DataMirror abstract class TLBundleBase(val params: TLBundleParameters) extends Bundle // common combos in lazy policy: // Put + Acquire // Release + AccessAck object TLMessages { // A B C D E def PutFullData = 0.U // . . => AccessAck def PutPartialData = 1.U // . . => AccessAck def ArithmeticData = 2.U // . . => AccessAckData def LogicalData = 3.U // . . => AccessAckData def Get = 4.U // . . => AccessAckData def Hint = 5.U // . . => HintAck def AcquireBlock = 6.U // . => Grant[Data] def AcquirePerm = 7.U // . => Grant[Data] def Probe = 6.U // . => ProbeAck[Data] def AccessAck = 0.U // . . def AccessAckData = 1.U // . . def HintAck = 2.U // . . def ProbeAck = 4.U // . def ProbeAckData = 5.U // . def Release = 6.U // . => ReleaseAck def ReleaseData = 7.U // . => ReleaseAck def Grant = 4.U // . => GrantAck def GrantData = 5.U // . => GrantAck def ReleaseAck = 6.U // . def GrantAck = 0.U // . def isA(x: UInt) = x <= AcquirePerm def isB(x: UInt) = x <= Probe def isC(x: UInt) = x <= ReleaseData def isD(x: UInt) = x <= ReleaseAck def adResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, Grant, Grant) def bcResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, ProbeAck, ProbeAck) def a = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("AcquireBlock",TLPermissions.PermMsgGrow), ("AcquirePerm",TLPermissions.PermMsgGrow)) def b = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("Probe",TLPermissions.PermMsgCap)) def c = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("ProbeAck",TLPermissions.PermMsgReport), ("ProbeAckData",TLPermissions.PermMsgReport), ("Release",TLPermissions.PermMsgReport), ("ReleaseData",TLPermissions.PermMsgReport)) def d = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("Grant",TLPermissions.PermMsgCap), ("GrantData",TLPermissions.PermMsgCap), ("ReleaseAck",TLPermissions.PermMsgReserved)) } /* * The three primary TileLink permissions are: * (T)runk: the agent is (or is on inwards path to) the global point of serialization. * (B)ranch: the agent is on an outwards path to * (N)one: * These permissions are permuted by transfer operations in various ways. * Operations can cap permissions, request for them to be grown or shrunk, * or for a report on their current status. / object TLPermissions { val aWidth = 2 val bdWidth = 2 val cWidth = 3 // Cap types (Grant = new permissions, Probe = permisions <= target) def toT = 0.U(bdWidth.W) def toB = 1.U(bdWidth.W) def toN = 2.U(bdWidth.W) def isCap(x: UInt) = x <= toN // Grow types (Acquire = permissions >= target) def NtoB = 0.U(aWidth.W) def NtoT = 1.U(aWidth.W) def BtoT = 2.U(aWidth.W) def isGrow(x: UInt) = x <= BtoT // Shrink types (ProbeAck, Release) def TtoB = 0.U(cWidth.W) def TtoN = 1.U(cWidth.W) def BtoN = 2.U(cWidth.W) def isShrink(x: UInt) = x <= BtoN // Report types (ProbeAck, Release) def TtoT = 3.U(cWidth.W) def BtoB = 4.U(cWidth.W) def NtoN = 5.U(cWidth.W) def isReport(x: UInt) = x <= NtoN def PermMsgGrow:Seq[String] = Seq("Grow NtoB", "Grow NtoT", "Grow BtoT") def PermMsgCap:Seq[String] = Seq("Cap toT", "Cap toB", "Cap toN") def PermMsgReport:Seq[String] = Seq("Shrink TtoB", "Shrink TtoN", "Shrink BtoN", "Report TotT", "Report BtoB", "Report NtoN") def PermMsgReserved:Seq[String] = Seq("Reserved") } object TLAtomics { val width = 3 // Arithmetic types def MIN = 0.U(width.W) def MAX = 1.U(width.W) def MINU = 2.U(width.W) def MAXU = 3.U(width.W) def ADD = 4.U(width.W) def isArithmetic(x: UInt) = x <= ADD // Logical types def XOR = 0.U(width.W) def OR = 1.U(width.W) def AND = 2.U(width.W) def SWAP = 3.U(width.W) def isLogical(x: UInt) = x <= SWAP def ArithMsg:Seq[String] = Seq("MIN", "MAX", "MINU", "MAXU", "ADD") def LogicMsg:Seq[String] = Seq("XOR", "OR", "AND", "SWAP") } object TLHints { val width = 1 def PREFETCH_READ = 0.U(width.W) def PREFETCH_WRITE = 1.U(width.W) def isHints(x: UInt) = x <= PREFETCH_WRITE def HintsMsg:Seq[String] = Seq("PrefetchRead", "PrefetchWrite") } sealed trait TLChannel extends TLBundleBase { val channelName: String } sealed trait TLDataChannel extends TLChannel sealed trait TLAddrChannel extends TLDataChannel final class TLBundleA(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleA_${params.shortName}" val channelName = "'A' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(List(TLAtomics.width, TLPermissions.aWidth, TLHints.width).max.W) // amo_opcode \|\| grow perms \|\| hint val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleB(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleB_${params.shortName}" val channelName = "'B' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val address = UInt(params.addressBits.W) // from // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleC(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleC_${params.shortName}" val channelName = "'C' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.cWidth.W) // shrink or report perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleD(params: TLBundleParameters) extends TLBundleBase(params) with TLDataChannel { override def typeName = s"TLBundleD_${params.shortName}" val channelName = "'D' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val sink = UInt(params.sinkBits.W) // from val denied = Bool() // implies corrupt iff Data val user = BundleMap(params.responseFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleE(params: TLBundleParameters) extends TLBundleBase(params) with TLChannel { override def typeName = s"TLBundleE_${params.shortName}" val channelName = "'E' channel" val sink = UInt(params.sinkBits.W) // to } class TLBundle(val params: TLBundleParameters) extends Record { // Emulate a Bundle with elements abcde or ad depending on params.hasBCE private val optA = Some (Decoupled(new TLBundleA(params))) private val optB = params.hasBCE.option(Flipped(Decoupled(new TLBundleB(params)))) private val optC = params.hasBCE.option(Decoupled(new TLBundleC(params))) private val optD = Some (Flipped(Decoupled(new TLBundleD(params)))) private val optE = params.hasBCE.option(Decoupled(new TLBundleE(params))) def a: DecoupledIO[TLBundleA] = optA.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleA(params))))) def b: DecoupledIO[TLBundleB] = optB.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleB(params))))) def c: DecoupledIO[TLBundleC] = optC.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleC(params))))) def d: DecoupledIO[TLBundleD] = optD.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleD(params))))) def e: DecoupledIO[TLBundleE] = optE.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleE(params))))) val elements = if (params.hasBCE) ListMap("e" -> e, "d" -> d, "c" -> c, "b" -> b, "a" -> a) else ListMap("d" -> d, "a" -> a) def tieoff(): Unit = { DataMirror.specifiedDirectionOf(a.ready) match { case SpecifiedDirection.Input => a.ready := false.B c.ready := false.B e.ready := false.B b.valid := false.B d.valid := false.B case SpecifiedDirection.Output => a.valid := false.B c.valid := false.B e.valid := false.B b.ready := false.B d.ready := false.B case _ => } } } object TLBundle { def apply(params: TLBundleParameters) = new TLBundle(params) } class TLAsyncBundleBase(val params: TLAsyncBundleParameters) extends Bundle class TLAsyncBundle(params: TLAsyncBundleParameters) extends TLAsyncBundleBase(params) { val a = new AsyncBundle(new TLBundleA(params.base), params.async) val b = Flipped(new AsyncBundle(new TLBundleB(params.base), params.async)) val c = new AsyncBundle(new TLBundleC(params.base), params.async) val d = Flipped(new AsyncBundle(new TLBundleD(params.base), params.async)) val e = new AsyncBundle(new TLBundleE(params.base), params.async) } class TLRationalBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = RationalIO(new TLBundleA(params)) val b = Flipped(RationalIO(new TLBundleB(params))) val c = RationalIO(new TLBundleC(params)) val d = Flipped(RationalIO(new TLBundleD(params))) val e = RationalIO(new TLBundleE(params)) } class TLCreditedBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = CreditedIO(new TLBundleA(params)) val b = Flipped(CreditedIO(new TLBundleB(params))) val c = CreditedIO(new TLBundleC(params)) val d = Flipped(CreditedIO(new TLBundleD(params))) val e = CreditedIO(new TLBundleE(params)) } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.nodes._ import freechips.rocketchip.diplomacy.{ AddressDecoder, AddressSet, BufferParams, DirectedBuffers, IdMap, IdMapEntry, IdRange, RegionType, TransferSizes } import freechips.rocketchip.resources.{Resource, ResourceAddress, ResourcePermissions} import freechips.rocketchip.util.{ AsyncQueueParams, BundleField, BundleFieldBase, BundleKeyBase, CreditedDelay, groupByIntoSeq, RationalDirection, SimpleProduct } import scala.math.max //These transfer sizes describe requests issued from masters on the A channel that will be responded by slaves on the D channel case class TLMasterToSlaveTransferSizes( // Supports both Acquire+Release of the following two sizes: acquireT: TransferSizes = TransferSizes.none, acquireB: TransferSizes = TransferSizes.none, arithmetic: TransferSizes = TransferSizes.none, logical: TransferSizes = TransferSizes.none, get: TransferSizes = TransferSizes.none, putFull: TransferSizes = TransferSizes.none, putPartial: TransferSizes = TransferSizes.none, hint: TransferSizes = TransferSizes.none) extends TLCommonTransferSizes { def intersect(rhs: TLMasterToSlaveTransferSizes) = TLMasterToSlaveTransferSizes( acquireT = acquireT .intersect(rhs.acquireT), acquireB = acquireB .intersect(rhs.acquireB), arithmetic = arithmetic.intersect(rhs.arithmetic), logical = logical .intersect(rhs.logical), get = get .intersect(rhs.get), putFull = putFull .intersect(rhs.putFull), putPartial = putPartial.intersect(rhs.putPartial), hint = hint .intersect(rhs.hint)) def mincover(rhs: TLMasterToSlaveTransferSizes) = TLMasterToSlaveTransferSizes( acquireT = acquireT .mincover(rhs.acquireT), acquireB = acquireB .mincover(rhs.acquireB), arithmetic = arithmetic.mincover(rhs.arithmetic), logical = logical .mincover(rhs.logical), get = get .mincover(rhs.get), putFull = putFull .mincover(rhs.putFull), putPartial = putPartial.mincover(rhs.putPartial), hint = hint .mincover(rhs.hint)) // Reduce rendering to a simple yes/no per field override def toString = { def str(x: TransferSizes, flag: String) = if (x.none) "" else flag def flags = Vector( str(acquireT, "T"), str(acquireB, "B"), str(arithmetic, "A"), str(logical, "L"), str(get, "G"), str(putFull, "F"), str(putPartial, "P"), str(hint, "H")) flags.mkString } // Prints out the actual information in a user readable way def infoString = { s"""acquireT = ${acquireT} \|acquireB = ${acquireB} \|arithmetic = ${arithmetic} \|logical = ${logical} \|get = ${get} \|putFull = ${putFull} \|putPartial = ${putPartial} \|hint = ${hint} \| \|""".stripMargin } } object TLMasterToSlaveTransferSizes { def unknownEmits = TLMasterToSlaveTransferSizes( acquireT = TransferSizes(1, 4096), acquireB = TransferSizes(1, 4096), arithmetic = TransferSizes(1, 4096), logical = TransferSizes(1, 4096), get = TransferSizes(1, 4096), putFull = TransferSizes(1, 4096), putPartial = TransferSizes(1, 4096), hint = TransferSizes(1, 4096)) def unknownSupports = TLMasterToSlaveTransferSizes() } //These transfer sizes describe requests issued from slaves on the B channel that will be responded by masters on the C channel case class TLSlaveToMasterTransferSizes( probe: TransferSizes = TransferSizes.none, arithmetic: TransferSizes = TransferSizes.none, logical: TransferSizes = TransferSizes.none, get: TransferSizes = TransferSizes.none, putFull: TransferSizes = TransferSizes.none, putPartial: TransferSizes = TransferSizes.none, hint: TransferSizes = TransferSizes.none ) extends TLCommonTransferSizes { def intersect(rhs: TLSlaveToMasterTransferSizes) = TLSlaveToMasterTransferSizes( probe = probe .intersect(rhs.probe), arithmetic = arithmetic.intersect(rhs.arithmetic), logical = logical .intersect(rhs.logical), get = get .intersect(rhs.get), putFull = putFull .intersect(rhs.putFull), putPartial = putPartial.intersect(rhs.putPartial), hint = hint .intersect(rhs.hint) ) def mincover(rhs: TLSlaveToMasterTransferSizes) = TLSlaveToMasterTransferSizes( probe = probe .mincover(rhs.probe), arithmetic = arithmetic.mincover(rhs.arithmetic), logical = logical .mincover(rhs.logical), get = get .mincover(rhs.get), putFull = putFull .mincover(rhs.putFull), putPartial = putPartial.mincover(rhs.putPartial), hint = hint .mincover(rhs.hint) ) // Reduce rendering to a simple yes/no per field override def toString = { def str(x: TransferSizes, flag: String) = if (x.none) "" else flag def flags = Vector( str(probe, "P"), str(arithmetic, "A"), str(logical, "L"), str(get, "G"), str(putFull, "F"), str(putPartial, "P"), str(hint, "H")) flags.mkString } // Prints out the actual information in a user readable way def infoString = { s"""probe = ${probe} \|arithmetic = ${arithmetic} \|logical = ${logical} \|get = ${get} \|putFull = ${putFull} \|putPartial = ${putPartial} \|hint = ${hint} \| \|""".stripMargin } } object TLSlaveToMasterTransferSizes { def unknownEmits = TLSlaveToMasterTransferSizes( arithmetic = TransferSizes(1, 4096), logical = TransferSizes(1, 4096), get = TransferSizes(1, 4096), putFull = TransferSizes(1, 4096), putPartial = TransferSizes(1, 4096), hint = TransferSizes(1, 4096), probe = TransferSizes(1, 4096)) def unknownSupports = TLSlaveToMasterTransferSizes() } trait TLCommonTransferSizes { def arithmetic: TransferSizes def logical: TransferSizes def get: TransferSizes def putFull: TransferSizes def putPartial: TransferSizes def hint: TransferSizes } class TLSlaveParameters private( val nodePath: Seq[BaseNode], val resources: Seq[Resource], setName: Option[String], val address: Seq[AddressSet], val regionType: RegionType.T, val executable: Boolean, val fifoId: Option[Int], val supports: TLMasterToSlaveTransferSizes, val emits: TLSlaveToMasterTransferSizes, // By default, slaves are forbidden from issuing 'denied' responses (it prevents Fragmentation) val alwaysGrantsT: Boolean, // typically only true for CacheCork'd read-write devices; dual: neverReleaseData // If fifoId=Some, all accesses sent to the same fifoId are executed and ACK'd in FIFO order // Note: you can only rely on this FIFO behaviour if your TLMasterParameters include requestFifo val mayDenyGet: Boolean, // applies to: AccessAckData, GrantData val mayDenyPut: Boolean) // applies to: AccessAck, Grant, HintAck // ReleaseAck may NEVER be denied extends SimpleProduct { def sortedAddress = address.sorted override def canEqual(that: Any): Boolean = that.isInstanceOf[TLSlaveParameters] override def productPrefix = "TLSlaveParameters" // We intentionally omit nodePath for equality testing / formatting def productArity: Int = 11 def productElement(n: Int): Any = n match { case 0 => name case 1 => address case 2 => resources case 3 => regionType case 4 => executable case 5 => fifoId case 6 => supports case 7 => emits case 8 => alwaysGrantsT case 9 => mayDenyGet case 10 => mayDenyPut case _ => throw new IndexOutOfBoundsException(n.toString) } def supportsAcquireT: TransferSizes = supports.acquireT def supportsAcquireB: TransferSizes = supports.acquireB def supportsArithmetic: TransferSizes = supports.arithmetic def supportsLogical: TransferSizes = supports.logical def supportsGet: TransferSizes = supports.get def supportsPutFull: TransferSizes = supports.putFull def supportsPutPartial: TransferSizes = supports.putPartial def supportsHint: TransferSizes = supports.hint require (!address.isEmpty, "Address cannot be empty") address.foreach { a => require (a.finite, "Address must be finite") } address.combinations(2).foreach { case Seq(x,y) => require (!x.overlaps(y), s"$x and $y overlap.") } require (supportsPutFull.contains(supportsPutPartial), s"PutFull($supportsPutFull) < PutPartial($supportsPutPartial)") require (supportsPutFull.contains(supportsArithmetic), s"PutFull($supportsPutFull) < Arithmetic($supportsArithmetic)") require (supportsPutFull.contains(supportsLogical), s"PutFull($supportsPutFull) < Logical($supportsLogical)") require (supportsGet.contains(supportsArithmetic), s"Get($supportsGet) < Arithmetic($supportsArithmetic)") require (supportsGet.contains(supportsLogical), s"Get($supportsGet) < Logical($supportsLogical)") require (supportsAcquireB.contains(supportsAcquireT), s"AcquireB($supportsAcquireB) < AcquireT($supportsAcquireT)") require (!alwaysGrantsT \|\| supportsAcquireT, s"Must supportAcquireT if promising to always grantT") // Make sure that the regionType agrees with the capabilities require (!supportsAcquireB \|\| regionType >= RegionType.UNCACHED) // acquire -> uncached, tracked, cached require (regionType <= RegionType.UNCACHED \|\| supportsAcquireB) // tracked, cached -> acquire require (regionType != RegionType.UNCACHED \|\| supportsGet) // uncached -> supportsGet val name = setName.orElse(nodePath.lastOption.map(_.lazyModule.name)).getOrElse("disconnected") val maxTransfer = List( // Largest supported transfer of all types supportsAcquireT.max, supportsAcquireB.max, supportsArithmetic.max, supportsLogical.max, supportsGet.max, supportsPutFull.max, supportsPutPartial.max).max val maxAddress = address.map(_.max).max val minAlignment = address.map(_.alignment).min // The device had better not support a transfer larger than its alignment require (minAlignment >= maxTransfer, s"Bad $address: minAlignment ($minAlignment) must be >= maxTransfer ($maxTransfer)") def toResource: ResourceAddress = { ResourceAddress(address, ResourcePermissions( r = supportsAcquireB \|\| supportsGet, w = supportsAcquireT \|\| supportsPutFull, x = executable, c = supportsAcquireB, a = supportsArithmetic && supportsLogical)) } def findTreeViolation() = nodePath.find { case _: MixedAdapterNode[_, _, _, _, _, _, _, _] => false case _: SinkNode[_, _, _, _, _] => false case node => node.inputs.size != 1 } def isTree = findTreeViolation() == None def infoString = { s"""Slave Name = ${name} \|Slave Address = ${address} \|supports = ${supports.infoString} \| \|""".stripMargin } def v1copy( address: Seq[AddressSet] = address, resources: Seq[Resource] = resources, regionType: RegionType.T = regionType, executable: Boolean = executable, nodePath: Seq[BaseNode] = nodePath, supportsAcquireT: TransferSizes = supports.acquireT, supportsAcquireB: TransferSizes = supports.acquireB, supportsArithmetic: TransferSizes = supports.arithmetic, supportsLogical: TransferSizes = supports.logical, supportsGet: TransferSizes = supports.get, supportsPutFull: TransferSizes = supports.putFull, supportsPutPartial: TransferSizes = supports.putPartial, supportsHint: TransferSizes = supports.hint, mayDenyGet: Boolean = mayDenyGet, mayDenyPut: Boolean = mayDenyPut, alwaysGrantsT: Boolean = alwaysGrantsT, fifoId: Option[Int] = fifoId) = { new TLSlaveParameters( setName = setName, address = address, resources = resources, regionType = regionType, executable = executable, nodePath = nodePath, supports = TLMasterToSlaveTransferSizes( acquireT = supportsAcquireT, acquireB = supportsAcquireB, arithmetic = supportsArithmetic, logical = supportsLogical, get = supportsGet, putFull = supportsPutFull, putPartial = supportsPutPartial, hint = supportsHint), emits = emits, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut, alwaysGrantsT = alwaysGrantsT, fifoId = fifoId) } def v2copy( nodePath: Seq[BaseNode] = nodePath, resources: Seq[Resource] = resources, name: Option[String] = setName, address: Seq[AddressSet] = address, regionType: RegionType.T = regionType, executable: Boolean = executable, fifoId: Option[Int] = fifoId, supports: TLMasterToSlaveTransferSizes = supports, emits: TLSlaveToMasterTransferSizes = emits, alwaysGrantsT: Boolean = alwaysGrantsT, mayDenyGet: Boolean = mayDenyGet, mayDenyPut: Boolean = mayDenyPut) = { new TLSlaveParameters( nodePath = nodePath, resources = resources, setName = name, address = address, regionType = regionType, executable = executable, fifoId = fifoId, supports = supports, emits = emits, alwaysGrantsT = alwaysGrantsT, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut) } @deprecated("Use v1copy instead of copy","") def copy( address: Seq[AddressSet] = address, resources: Seq[Resource] = resources, regionType: RegionType.T = regionType, executable: Boolean = executable, nodePath: Seq[BaseNode] = nodePath, supportsAcquireT: TransferSizes = supports.acquireT, supportsAcquireB: TransferSizes = supports.acquireB, supportsArithmetic: TransferSizes = supports.arithmetic, supportsLogical: TransferSizes = supports.logical, supportsGet: TransferSizes = supports.get, supportsPutFull: TransferSizes = supports.putFull, supportsPutPartial: TransferSizes = supports.putPartial, supportsHint: TransferSizes = supports.hint, mayDenyGet: Boolean = mayDenyGet, mayDenyPut: Boolean = mayDenyPut, alwaysGrantsT: Boolean = alwaysGrantsT, fifoId: Option[Int] = fifoId) = { v1copy( address = address, resources = resources, regionType = regionType, executable = executable, nodePath = nodePath, supportsAcquireT = supportsAcquireT, supportsAcquireB = supportsAcquireB, supportsArithmetic = supportsArithmetic, supportsLogical = supportsLogical, supportsGet = supportsGet, supportsPutFull = supportsPutFull, supportsPutPartial = supportsPutPartial, supportsHint = supportsHint, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut, alwaysGrantsT = alwaysGrantsT, fifoId = fifoId) } } object TLSlaveParameters { def v1( address: Seq[AddressSet], resources: Seq[Resource] = Seq(), regionType: RegionType.T = RegionType.GET_EFFECTS, executable: Boolean = false, nodePath: Seq[BaseNode] = Seq(), supportsAcquireT: TransferSizes = TransferSizes.none, supportsAcquireB: TransferSizes = TransferSizes.none, supportsArithmetic: TransferSizes = TransferSizes.none, supportsLogical: TransferSizes = TransferSizes.none, supportsGet: TransferSizes = TransferSizes.none, supportsPutFull: TransferSizes = TransferSizes.none, supportsPutPartial: TransferSizes = TransferSizes.none, supportsHint: TransferSizes = TransferSizes.none, mayDenyGet: Boolean = false, mayDenyPut: Boolean = false, alwaysGrantsT: Boolean = false, fifoId: Option[Int] = None) = { new TLSlaveParameters( setName = None, address = address, resources = resources, regionType = regionType, executable = executable, nodePath = nodePath, supports = TLMasterToSlaveTransferSizes( acquireT = supportsAcquireT, acquireB = supportsAcquireB, arithmetic = supportsArithmetic, logical = supportsLogical, get = supportsGet, putFull = supportsPutFull, putPartial = supportsPutPartial, hint = supportsHint), emits = TLSlaveToMasterTransferSizes.unknownEmits, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut, alwaysGrantsT = alwaysGrantsT, fifoId = fifoId) } def v2( address: Seq[AddressSet], nodePath: Seq[BaseNode] = Seq(), resources: Seq[Resource] = Seq(), name: Option[String] = None, regionType: RegionType.T = RegionType.GET_EFFECTS, executable: Boolean = false, fifoId: Option[Int] = None, supports: TLMasterToSlaveTransferSizes = TLMasterToSlaveTransferSizes.unknownSupports, emits: TLSlaveToMasterTransferSizes = TLSlaveToMasterTransferSizes.unknownEmits, alwaysGrantsT: Boolean = false, mayDenyGet: Boolean = false, mayDenyPut: Boolean = false) = { new TLSlaveParameters( nodePath = nodePath, resources = resources, setName = name, address = address, regionType = regionType, executable = executable, fifoId = fifoId, supports = supports, emits = emits, alwaysGrantsT = alwaysGrantsT, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut) } } object TLManagerParameters { @deprecated("Use TLSlaveParameters.v1 instead of TLManagerParameters","") def apply( address: Seq[AddressSet], resources: Seq[Resource] = Seq(), regionType: RegionType.T = RegionType.GET_EFFECTS, executable: Boolean = false, nodePath: Seq[BaseNode] = Seq(), supportsAcquireT: TransferSizes = TransferSizes.none, supportsAcquireB: TransferSizes = TransferSizes.none, supportsArithmetic: TransferSizes = TransferSizes.none, supportsLogical: TransferSizes = TransferSizes.none, supportsGet: TransferSizes = TransferSizes.none, supportsPutFull: TransferSizes = TransferSizes.none, supportsPutPartial: TransferSizes = TransferSizes.none, supportsHint: TransferSizes = TransferSizes.none, mayDenyGet: Boolean = false, mayDenyPut: Boolean = false, alwaysGrantsT: Boolean = false, fifoId: Option[Int] = None) = TLSlaveParameters.v1( address, resources, regionType, executable, nodePath, supportsAcquireT, supportsAcquireB, supportsArithmetic, supportsLogical, supportsGet, supportsPutFull, supportsPutPartial, supportsHint, mayDenyGet, mayDenyPut, alwaysGrantsT, fifoId, ) } case class TLChannelBeatBytes(a: Option[Int], b: Option[Int], c: Option[Int], d: Option[Int]) { def members = Seq(a, b, c, d) members.collect { case Some(beatBytes) => require (isPow2(beatBytes), "Data channel width must be a power of 2") } } object TLChannelBeatBytes{ def apply(beatBytes: Int): TLChannelBeatBytes = TLChannelBeatBytes( Some(beatBytes), Some(beatBytes), Some(beatBytes), Some(beatBytes)) def apply(): TLChannelBeatBytes = TLChannelBeatBytes( None, None, None, None) } class TLSlavePortParameters private( val slaves: Seq[TLSlaveParameters], val channelBytes: TLChannelBeatBytes, val endSinkId: Int, val minLatency: Int, val responseFields: Seq[BundleFieldBase], val requestKeys: Seq[BundleKeyBase]) extends SimpleProduct { def sortedSlaves = slaves.sortBy(_.sortedAddress.head) override def canEqual(that: Any): Boolean = that.isInstanceOf[TLSlavePortParameters] override def productPrefix = "TLSlavePortParameters" def productArity: Int = 6 def productElement(n: Int): Any = n match { case 0 => slaves case 1 => channelBytes case 2 => endSinkId case 3 => minLatency case 4 => responseFields case 5 => requestKeys case _ => throw new IndexOutOfBoundsException(n.toString) } require (!slaves.isEmpty, "Slave ports must have slaves") require (endSinkId >= 0, "Sink ids cannot be negative") require (minLatency >= 0, "Minimum required latency cannot be negative") // Using this API implies you cannot handle mixed-width busses def beatBytes = { channelBytes.members.foreach { width => require (width.isDefined && width == channelBytes.a) } channelBytes.a.get } // TODO this should be deprecated def managers = slaves def requireFifo(policy: TLFIFOFixer.Policy = TLFIFOFixer.allFIFO) = { val relevant = slaves.filter(m => policy(m)) relevant.foreach { m => require(m.fifoId == relevant.head.fifoId, s"${m.name} had fifoId ${m.fifoId}, which was not homogeneous (${slaves.map(s => (s.name, s.fifoId))}) ") } } // Bounds on required sizes def maxAddress = slaves.map(_.maxAddress).max def maxTransfer = slaves.map(_.maxTransfer).max def mayDenyGet = slaves.exists(_.mayDenyGet) def mayDenyPut = slaves.exists(_.mayDenyPut) // Diplomatically determined operation sizes emitted by all outward Slaves // as opposed to emits* which generate circuitry to check which specific addresses val allEmitClaims = slaves.map(_.emits).reduce( _ intersect _) // Operation Emitted by at least one outward Slaves // as opposed to emits* which generate circuitry to check which specific addresses val anyEmitClaims = slaves.map(_.emits).reduce(_ mincover _) // Diplomatically determined operation sizes supported by all outward Slaves // as opposed to supports* which generate circuitry to check which specific addresses val allSupportClaims = slaves.map(_.supports).reduce( _ intersect _) val allSupportAcquireT = allSupportClaims.acquireT val allSupportAcquireB = allSupportClaims.acquireB val allSupportArithmetic = allSupportClaims.arithmetic val allSupportLogical = allSupportClaims.logical val allSupportGet = allSupportClaims.get val allSupportPutFull = allSupportClaims.putFull val allSupportPutPartial = allSupportClaims.putPartial val allSupportHint = allSupportClaims.hint // Operation supported by at least one outward Slaves // as opposed to supports* which generate circuitry to check which specific addresses val anySupportClaims = slaves.map(_.supports).reduce(_ mincover _) val anySupportAcquireT = !anySupportClaims.acquireT.none val anySupportAcquireB = !anySupportClaims.acquireB.none val anySupportArithmetic = !anySupportClaims.arithmetic.none val anySupportLogical = !anySupportClaims.logical.none val anySupportGet = !anySupportClaims.get.none val anySupportPutFull = !anySupportClaims.putFull.none val anySupportPutPartial = !anySupportClaims.putPartial.none val anySupportHint = !anySupportClaims.hint.none // Supporting Acquire means being routable for GrantAck require ((endSinkId == 0) == !anySupportAcquireB) // These return Option[TLSlaveParameters] for your convenience def find(address: BigInt) = slaves.find(_.address.exists(_.contains(address))) // The safe version will check the entire address def findSafe(address: UInt) = VecInit(sortedSlaves.map(_.address.map(_.contains(address)).reduce(_ \|\| _))) // The fast version assumes the address is valid (you probably want fastProperty instead of this function) def findFast(address: UInt) = { val routingMask = AddressDecoder(slaves.map(_.address)) VecInit(sortedSlaves.map(_.address.map(_.widen(~routingMask)).distinct.map(_.contains(address)).reduce(_ \|\| _))) } // Compute the simplest AddressSets that decide a key def fastPropertyGroup[K](p: TLSlaveParameters => K): Seq[(K, Seq[AddressSet])] = { val groups = groupByIntoSeq(sortedSlaves.map(m => (p(m), m.address)))( _._1).map { case (k, vs) => k -> vs.flatMap(_._2) } val reductionMask = AddressDecoder(groups.map(_._2)) groups.map { case (k, seq) => k -> AddressSet.unify(seq.map(_.widen(~reductionMask)).distinct) } } // Select a property def fastProperty[K, D <: Data](address: UInt, p: TLSlaveParameters => K, d: K => D): D = Mux1H(fastPropertyGroup(p).map { case (v, a) => (a.map(_.contains(address)).reduce(_\|\|_), d(v)) }) // Note: returns the actual fifoId + 1 or 0 if None def findFifoIdFast(address: UInt) = fastProperty(address, _.fifoId.map(_+1).getOrElse(0), (i:Int) => i.U) def hasFifoIdFast(address: UInt) = fastProperty(address, _.fifoId.isDefined, (b:Boolean) => b.B) // Does this Port manage this ID/address? def containsSafe(address: UInt) = findSafe(address).reduce(_ \|\| _) private def addressHelper( // setting safe to false indicates that all addresses are expected to be legal, which might reduce circuit complexity safe: Boolean, // member filters out the sizes being checked based on the opcode being emitted or supported member: TLSlaveParameters => TransferSizes, address: UInt, lgSize: UInt, // range provides a limit on the sizes that are expected to be evaluated, which might reduce circuit complexity range: Option[TransferSizes]): Bool = { // trim reduces circuit complexity by intersecting checked sizes with the range argument def trim(x: TransferSizes) = range.map(_.intersect(x)).getOrElse(x) // groupBy returns an unordered map, convert back to Seq and sort the result for determinism // groupByIntoSeq is turning slaves into trimmed membership sizes // We are grouping all the slaves by their transfer size where // if they support the trimmed size then // member is the type of transfer that you are looking for (What you are trying to filter on) // When you consider membership, you are trimming the sizes to only the ones that you care about // you are filtering the slaves based on both whether they support a particular opcode and the size // Grouping the slaves based on the actual transfer size range they support // intersecting the range and checking their membership // FOR SUPPORTCASES instead of returning the list of slaves, // you are returning a map from transfer size to the set of // address sets that are supported for that transfer size // find all the slaves that support a certain type of operation and then group their addresses by the supported size // for every size there could be multiple address ranges // safety is a trade off between checking between all possible addresses vs only the addresses // that are known to have supported sizes // the trade off is 'checking all addresses is a more expensive circuit but will always give you // the right answer even if you give it an illegal address' // the not safe version is a cheaper circuit but if you give it an illegal address then it might produce the wrong answer // fast presumes address legality // This groupByIntoSeq deterministically groups all address sets for which a given `member` transfer size applies. // In the resulting Map of cases, the keys are transfer sizes and the values are all address sets which emit or support that size. val supportCases = groupByIntoSeq(slaves)(m => trim(member(m))).map { case (k: TransferSizes, vs: Seq[TLSlaveParameters]) => k -> vs.flatMap(_.address) } // safe produces a circuit that compares against all possible addresses, // whereas fast presumes that the address is legal but uses an efficient address decoder val mask = if (safe) ~BigInt(0) else AddressDecoder(supportCases.map(_._2)) // Simplified creates the most concise possible representation of each cases' address sets based on the mask. val simplified = supportCases.map { case (k, seq) => k -> AddressSet.unify(seq.map(_.widen(~mask)).distinct) } simplified.map { case (s, a) => // s is a size, you are checking for this size either the size of the operation is in s // We return an or-reduction of all the cases, checking whether any contains both the dynamic size and dynamic address on the wire. ((Some(s) == range).B \|\| s.containsLg(lgSize)) && a.map(_.contains(address)).reduce(_\|\|_) }.foldLeft(false.B)(_\|\|_) } def supportsAcquireTSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.acquireT, address, lgSize, range) def supportsAcquireBSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.acquireB, address, lgSize, range) def supportsArithmeticSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.arithmetic, address, lgSize, range) def supportsLogicalSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.logical, address, lgSize, range) def supportsGetSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.get, address, lgSize, range) def supportsPutFullSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.putFull, address, lgSize, range) def supportsPutPartialSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.putPartial, address, lgSize, range) def supportsHintSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.hint, address, lgSize, range) def supportsAcquireTFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.acquireT, address, lgSize, range) def supportsAcquireBFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.acquireB, address, lgSize, range) def supportsArithmeticFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.arithmetic, address, lgSize, range) def supportsLogicalFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.logical, address, lgSize, range) def supportsGetFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.get, address, lgSize, range) def supportsPutFullFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.putFull, address, lgSize, range) def supportsPutPartialFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.putPartial, address, lgSize, range) def supportsHintFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.hint, address, lgSize, range) def emitsProbeSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.probe, address, lgSize, range) def emitsArithmeticSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.arithmetic, address, lgSize, range) def emitsLogicalSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.logical, address, lgSize, range) def emitsGetSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.get, address, lgSize, range) def emitsPutFullSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.putFull, address, lgSize, range) def emitsPutPartialSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.putPartial, address, lgSize, range) def emitsHintSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.hint, address, lgSize, range) def findTreeViolation() = slaves.flatMap(_.findTreeViolation()).headOption def isTree = !slaves.exists(!_.isTree) def infoString = "Slave Port Beatbytes = " + beatBytes + "\n" + "Slave Port MinLatency = " + minLatency + "\n\n" + slaves.map(_.infoString).mkString def v1copy( managers: Seq[TLSlaveParameters] = slaves, beatBytes: Int = -1, endSinkId: Int = endSinkId, minLatency: Int = minLatency, responseFields: Seq[BundleFieldBase] = responseFields, requestKeys: Seq[BundleKeyBase] = requestKeys) = { new TLSlavePortParameters( slaves = managers, channelBytes = if (beatBytes != -1) TLChannelBeatBytes(beatBytes) else channelBytes, endSinkId = endSinkId, minLatency = minLatency, responseFields = responseFields, requestKeys = requestKeys) } def v2copy( slaves: Seq[TLSlaveParameters] = slaves, channelBytes: TLChannelBeatBytes = channelBytes, endSinkId: Int = endSinkId, minLatency: Int = minLatency, responseFields: Seq[BundleFieldBase] = responseFields, requestKeys: Seq[BundleKeyBase] = requestKeys) = { new TLSlavePortParameters( slaves = slaves, channelBytes = channelBytes, endSinkId = endSinkId, minLatency = minLatency, responseFields = responseFields, requestKeys = requestKeys) } @deprecated("Use v1copy instead of copy","") def copy( managers: Seq[TLSlaveParameters] = slaves, beatBytes: Int = -1, endSinkId: Int = endSinkId, minLatency: Int = minLatency, responseFields: Seq[BundleFieldBase] = responseFields, requestKeys: Seq[BundleKeyBase] = requestKeys) = { v1copy( managers, beatBytes, endSinkId, minLatency, responseFields, requestKeys) } } object TLSlavePortParameters { def v1( managers: Seq[TLSlaveParameters], beatBytes: Int, endSinkId: Int = 0, minLatency: Int = 0, responseFields: Seq[BundleFieldBase] = Nil, requestKeys: Seq[BundleKeyBase] = Nil) = { new TLSlavePortParameters( slaves = managers, channelBytes = TLChannelBeatBytes(beatBytes), endSinkId = endSinkId, minLatency = minLatency, responseFields = responseFields, requestKeys = requestKeys) } } object TLManagerPortParameters { @deprecated("Use TLSlavePortParameters.v1 instead of TLManagerPortParameters","") def apply( managers: Seq[TLSlaveParameters], beatBytes: Int, endSinkId: Int = 0, minLatency: Int = 0, responseFields: Seq[BundleFieldBase] = Nil, requestKeys: Seq[BundleKeyBase] = Nil) = { TLSlavePortParameters.v1( managers, beatBytes, endSinkId, minLatency, responseFields, requestKeys) } } class TLMasterParameters private( val nodePath: Seq[BaseNode], val resources: Seq[Resource], val name: String, val visibility: Seq[AddressSet], val unusedRegionTypes: Set[RegionType.T], val executesOnly: Boolean, val requestFifo: Boolean, // only a request, not a requirement. applies to A, not C. val supports: TLSlaveToMasterTransferSizes, val emits: TLMasterToSlaveTransferSizes, val neverReleasesData: Boolean, val sourceId: IdRange) extends SimpleProduct { override def canEqual(that: Any): Boolean = that.isInstanceOf[TLMasterParameters] override def productPrefix = "TLMasterParameters" // We intentionally omit nodePath for equality testing / formatting def productArity: Int = 10 def productElement(n: Int): Any = n match { case 0 => name case 1 => sourceId case 2 => resources case 3 => visibility case 4 => unusedRegionTypes case 5 => executesOnly case 6 => requestFifo case 7 => supports case 8 => emits case 9 => neverReleasesData case _ => throw new IndexOutOfBoundsException(n.toString) } require (!sourceId.isEmpty) require (!visibility.isEmpty) require (supports.putFull.contains(supports.putPartial)) // We only support these operations if we support Probe (ie: we're a cache) require (supports.probe.contains(supports.arithmetic)) require (supports.probe.contains(supports.logical)) require (supports.probe.contains(supports.get)) require (supports.probe.contains(supports.putFull)) require (supports.probe.contains(supports.putPartial)) require (supports.probe.contains(supports.hint)) visibility.combinations(2).foreach { case Seq(x,y) => require (!x.overlaps(y), s"$x and $y overlap.") } val maxTransfer = List( supports.probe.max, supports.arithmetic.max, supports.logical.max, supports.get.max, supports.putFull.max, supports.putPartial.max).max def infoString = { s"""Master Name = ${name} \|visibility = ${visibility} \|emits = ${emits.infoString} \|sourceId = ${sourceId} \| \|""".stripMargin } def v1copy( name: String = name, sourceId: IdRange = sourceId, nodePath: Seq[BaseNode] = nodePath, requestFifo: Boolean = requestFifo, visibility: Seq[AddressSet] = visibility, supportsProbe: TransferSizes = supports.probe, supportsArithmetic: TransferSizes = supports.arithmetic, supportsLogical: TransferSizes = supports.logical, supportsGet: TransferSizes = supports.get, supportsPutFull: TransferSizes = supports.putFull, supportsPutPartial: TransferSizes = supports.putPartial, supportsHint: TransferSizes = supports.hint) = { new TLMasterParameters( nodePath = nodePath, resources = this.resources, name = name, visibility = visibility, unusedRegionTypes = this.unusedRegionTypes, executesOnly = this.executesOnly, requestFifo = requestFifo, supports = TLSlaveToMasterTransferSizes( probe = supportsProbe, arithmetic = supportsArithmetic, logical = supportsLogical, get = supportsGet, putFull = supportsPutFull, putPartial = supportsPutPartial, hint = supportsHint), emits = this.emits, neverReleasesData = this.neverReleasesData, sourceId = sourceId) } def v2copy( nodePath: Seq[BaseNode] = nodePath, resources: Seq[Resource] = resources, name: String = name, visibility: Seq[AddressSet] = visibility, unusedRegionTypes: Set[RegionType.T] = unusedRegionTypes, executesOnly: Boolean = executesOnly, requestFifo: Boolean = requestFifo, supports: TLSlaveToMasterTransferSizes = supports, emits: TLMasterToSlaveTransferSizes = emits, neverReleasesData: Boolean = neverReleasesData, sourceId: IdRange = sourceId) = { new TLMasterParameters( nodePath = nodePath, resources = resources, name = name, visibility = visibility, unusedRegionTypes = unusedRegionTypes, executesOnly = executesOnly, requestFifo = requestFifo, supports = supports, emits = emits, neverReleasesData = neverReleasesData, sourceId = sourceId) } @deprecated("Use v1copy instead of copy","") def copy( name: String = name, sourceId: IdRange = sourceId, nodePath: Seq[BaseNode] = nodePath, requestFifo: Boolean = requestFifo, visibility: Seq[AddressSet] = visibility, supportsProbe: TransferSizes = supports.probe, supportsArithmetic: TransferSizes = supports.arithmetic, supportsLogical: TransferSizes = supports.logical, supportsGet: TransferSizes = supports.get, supportsPutFull: TransferSizes = supports.putFull, supportsPutPartial: TransferSizes = supports.putPartial, supportsHint: TransferSizes = supports.hint) = { v1copy( name = name, sourceId = sourceId, nodePath = nodePath, requestFifo = requestFifo, visibility = visibility, supportsProbe = supportsProbe, supportsArithmetic = supportsArithmetic, supportsLogical = supportsLogical, supportsGet = supportsGet, supportsPutFull = supportsPutFull, supportsPutPartial = supportsPutPartial, supportsHint = supportsHint) } } object TLMasterParameters { def v1( name: String, sourceId: IdRange = IdRange(0,1), nodePath: Seq[BaseNode] = Seq(), requestFifo: Boolean = false, visibility: Seq[AddressSet] = Seq(AddressSet(0, ~0)), supportsProbe: TransferSizes = TransferSizes.none, supportsArithmetic: TransferSizes = TransferSizes.none, supportsLogical: TransferSizes = TransferSizes.none, supportsGet: TransferSizes = TransferSizes.none, supportsPutFull: TransferSizes = TransferSizes.none, supportsPutPartial: TransferSizes = TransferSizes.none, supportsHint: TransferSizes = TransferSizes.none) = { new TLMasterParameters( nodePath = nodePath, resources = Nil, name = name, visibility = visibility, unusedRegionTypes = Set(), executesOnly = false, requestFifo = requestFifo, supports = TLSlaveToMasterTransferSizes( probe = supportsProbe, arithmetic = supportsArithmetic, logical = supportsLogical, get = supportsGet, putFull = supportsPutFull, putPartial = supportsPutPartial, hint = supportsHint), emits = TLMasterToSlaveTransferSizes.unknownEmits, neverReleasesData = false, sourceId = sourceId) } def v2( nodePath: Seq[BaseNode] = Seq(), resources: Seq[Resource] = Nil, name: String, visibility: Seq[AddressSet] = Seq(AddressSet(0, ~0)), unusedRegionTypes: Set[RegionType.T] = Set(), executesOnly: Boolean = false, requestFifo: Boolean = false, supports: TLSlaveToMasterTransferSizes = TLSlaveToMasterTransferSizes.unknownSupports, emits: TLMasterToSlaveTransferSizes = TLMasterToSlaveTransferSizes.unknownEmits, neverReleasesData: Boolean = false, sourceId: IdRange = IdRange(0,1)) = { new TLMasterParameters( nodePath = nodePath, resources = resources, name = name, visibility = visibility, unusedRegionTypes = unusedRegionTypes, executesOnly = executesOnly, requestFifo = requestFifo, supports = supports, emits = emits, neverReleasesData = neverReleasesData, sourceId = sourceId) } } object TLClientParameters { @deprecated("Use TLMasterParameters.v1 instead of TLClientParameters","") def apply( name: String, sourceId: IdRange = IdRange(0,1), nodePath: Seq[BaseNode] = Seq(), requestFifo: Boolean = false, visibility: Seq[AddressSet] = Seq(AddressSet.everything), supportsProbe: TransferSizes = TransferSizes.none, supportsArithmetic: TransferSizes = TransferSizes.none, supportsLogical: TransferSizes = TransferSizes.none, supportsGet: TransferSizes = TransferSizes.none, supportsPutFull: TransferSizes = TransferSizes.none, supportsPutPartial: TransferSizes = TransferSizes.none, supportsHint: TransferSizes = TransferSizes.none) = { TLMasterParameters.v1( name = name, sourceId = sourceId, nodePath = nodePath, requestFifo = requestFifo, visibility = visibility, supportsProbe = supportsProbe, supportsArithmetic = supportsArithmetic, supportsLogical = supportsLogical, supportsGet = supportsGet, supportsPutFull = supportsPutFull, supportsPutPartial = supportsPutPartial, supportsHint = supportsHint) } } class TLMasterPortParameters private( val masters: Seq[TLMasterParameters], val channelBytes: TLChannelBeatBytes, val minLatency: Int, val echoFields: Seq[BundleFieldBase], val requestFields: Seq[BundleFieldBase], val responseKeys: Seq[BundleKeyBase]) extends SimpleProduct { override def canEqual(that: Any): Boolean = that.isInstanceOf[TLMasterPortParameters] override def productPrefix = "TLMasterPortParameters" def productArity: Int = 6 def productElement(n: Int): Any = n match { case 0 => masters case 1 => channelBytes case 2 => minLatency case 3 => echoFields case 4 => requestFields case 5 => responseKeys case _ => throw new IndexOutOfBoundsException(n.toString) } require (!masters.isEmpty) require (minLatency >= 0) def clients = masters // Require disjoint ranges for Ids IdRange.overlaps(masters.map(_.sourceId)).foreach { case (x, y) => require (!x.overlaps(y), s"TLClientParameters.sourceId ${x} overlaps ${y}") } // Bounds on required sizes def endSourceId = masters.map(_.sourceId.end).max def maxTransfer = masters.map(_.maxTransfer).max // The unused sources < endSourceId def unusedSources: Seq[Int] = { val usedSources = masters.map(_.sourceId).sortBy(_.start) ((Seq(0) ++ usedSources.map(_.end)) zip usedSources.map(_.start)) flatMap { case (end, start) => end until start } } // Diplomatically determined operation sizes emitted by all inward Masters // as opposed to emits* which generate circuitry to check which specific addresses val allEmitClaims = masters.map(_.emits).reduce( _ intersect _) // Diplomatically determined operation sizes Emitted by at least one inward Masters // as opposed to emits* which generate circuitry to check which specific addresses val anyEmitClaims = masters.map(_.emits).reduce(_ mincover _) // Diplomatically determined operation sizes supported by all inward Masters // as opposed to supports* which generate circuitry to check which specific addresses val allSupportProbe = masters.map(_.supports.probe) .reduce(_ intersect _) val allSupportArithmetic = masters.map(_.supports.arithmetic).reduce(_ intersect _) val allSupportLogical = masters.map(_.supports.logical) .reduce(_ intersect _) val allSupportGet = masters.map(_.supports.get) .reduce(_ intersect _) val allSupportPutFull = masters.map(_.supports.putFull) .reduce(_ intersect _) val allSupportPutPartial = masters.map(_.supports.putPartial).reduce(_ intersect _) val allSupportHint = masters.map(_.supports.hint) .reduce(_ intersect _) // Diplomatically determined operation sizes supported by at least one master // as opposed to supports* which generate circuitry to check which specific addresses val anySupportProbe = masters.map(!_.supports.probe.none) .reduce(_ \|\| _) val anySupportArithmetic = masters.map(!_.supports.arithmetic.none).reduce(_ \|\| _) val anySupportLogical = masters.map(!_.supports.logical.none) .reduce(_ \|\| _) val anySupportGet = masters.map(!_.supports.get.none) .reduce(_ \|\| _) val anySupportPutFull = masters.map(!_.supports.putFull.none) .reduce(_ \|\| _) val anySupportPutPartial = masters.map(!_.supports.putPartial.none).reduce(_ \|\| _) val anySupportHint = masters.map(!_.supports.hint.none) .reduce(_ \|\| _) // These return Option[TLMasterParameters] for your convenience def find(id: Int) = masters.find(_.sourceId.contains(id)) // Synthesizable lookup methods def find(id: UInt) = VecInit(masters.map(_.sourceId.contains(id))) def contains(id: UInt) = find(id).reduce(_ \|\| _) def requestFifo(id: UInt) = Mux1H(find(id), masters.map(c => c.requestFifo.B)) // Available during RTL runtime, checks to see if (id, size) is supported by the master's (client's) diplomatic parameters private def sourceIdHelper(member: TLMasterParameters => TransferSizes)(id: UInt, lgSize: UInt) = { val allSame = masters.map(member(_) == member(masters(0))).reduce(_ && _) // this if statement is a coarse generalization of the groupBy in the sourceIdHelper2 version; // the case where there is only one group. if (allSame) member(masters(0)).containsLg(lgSize) else { // Find the master associated with ID and returns whether that particular master is able to receive transaction of lgSize Mux1H(find(id), masters.map(member(_).containsLg(lgSize))) } } // Check for support of a given operation at a specific id val supportsProbe = sourceIdHelper(_.supports.probe) _ val supportsArithmetic = sourceIdHelper(_.supports.arithmetic) _ val supportsLogical = sourceIdHelper(_.supports.logical) _ val supportsGet = sourceIdHelper(_.supports.get) _ val supportsPutFull = sourceIdHelper(_.supports.putFull) _ val supportsPutPartial = sourceIdHelper(_.supports.putPartial) _ val supportsHint = sourceIdHelper(_.supports.hint) _ // TODO: Merge sourceIdHelper2 with sourceIdHelper private def sourceIdHelper2( member: TLMasterParameters => TransferSizes, sourceId: UInt, lgSize: UInt): Bool = { // Because sourceIds are uniquely owned by each master, we use them to group the // cases that have to be checked. val emitCases = groupByIntoSeq(masters)(m => member(m)).map { case (k, vs) => k -> vs.map(_.sourceId) } emitCases.map { case (s, a) => (s.containsLg(lgSize)) && a.map(_.contains(sourceId)).reduce(_\|\|_) }.foldLeft(false.B)(_\|\|_) } // Check for emit of a given operation at a specific id def emitsAcquireT (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.acquireT, sourceId, lgSize) def emitsAcquireB (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.acquireB, sourceId, lgSize) def emitsArithmetic(sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.arithmetic, sourceId, lgSize) def emitsLogical (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.logical, sourceId, lgSize) def emitsGet (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.get, sourceId, lgSize) def emitsPutFull (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.putFull, sourceId, lgSize) def emitsPutPartial(sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.putPartial, sourceId, lgSize) def emitsHint (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.hint, sourceId, lgSize) def infoString = masters.map(_.infoString).mkString def v1copy( clients: Seq[TLMasterParameters] = masters, minLatency: Int = minLatency, echoFields: Seq[BundleFieldBase] = echoFields, requestFields: Seq[BundleFieldBase] = requestFields, responseKeys: Seq[BundleKeyBase] = responseKeys) = { new TLMasterPortParameters( masters = clients, channelBytes = channelBytes, minLatency = minLatency, echoFields = echoFields, requestFields = requestFields, responseKeys = responseKeys) } def v2copy( masters: Seq[TLMasterParameters] = masters, channelBytes: TLChannelBeatBytes = channelBytes, minLatency: Int = minLatency, echoFields: Seq[BundleFieldBase] = echoFields, requestFields: Seq[BundleFieldBase] = requestFields, responseKeys: Seq[BundleKeyBase] = responseKeys) = { new TLMasterPortParameters( masters = masters, channelBytes = channelBytes, minLatency = minLatency, echoFields = echoFields, requestFields = requestFields, responseKeys = responseKeys) } @deprecated("Use v1copy instead of copy","") def copy( clients: Seq[TLMasterParameters] = masters, minLatency: Int = minLatency, echoFields: Seq[BundleFieldBase] = echoFields, requestFields: Seq[BundleFieldBase] = requestFields, responseKeys: Seq[BundleKeyBase] = responseKeys) = { v1copy( clients, minLatency, echoFields, requestFields, responseKeys) } } object TLClientPortParameters { @deprecated("Use TLMasterPortParameters.v1 instead of TLClientPortParameters","") def apply( clients: Seq[TLMasterParameters], minLatency: Int = 0, echoFields: Seq[BundleFieldBase] = Nil, requestFields: Seq[BundleFieldBase] = Nil, responseKeys: Seq[BundleKeyBase] = Nil) = { TLMasterPortParameters.v1( clients, minLatency, echoFields, requestFields, responseKeys) } } object TLMasterPortParameters { def v1( clients: Seq[TLMasterParameters], minLatency: Int = 0, echoFields: Seq[BundleFieldBase] = Nil, requestFields: Seq[BundleFieldBase] = Nil, responseKeys: Seq[BundleKeyBase] = Nil) = { new TLMasterPortParameters( masters = clients, channelBytes = TLChannelBeatBytes(), minLatency = minLatency, echoFields = echoFields, requestFields = requestFields, responseKeys = responseKeys) } def v2( masters: Seq[TLMasterParameters], channelBytes: TLChannelBeatBytes = TLChannelBeatBytes(), minLatency: Int = 0, echoFields: Seq[BundleFieldBase] = Nil, requestFields: Seq[BundleFieldBase] = Nil, responseKeys: Seq[BundleKeyBase] = Nil) = { new TLMasterPortParameters( masters = masters, channelBytes = channelBytes, minLatency = minLatency, echoFields = echoFields, requestFields = requestFields, responseKeys = responseKeys) } } case class TLBundleParameters( addressBits: Int, dataBits: Int, sourceBits: Int, sinkBits: Int, sizeBits: Int, echoFields: Seq[BundleFieldBase], requestFields: Seq[BundleFieldBase], responseFields: Seq[BundleFieldBase], hasBCE: Boolean) { // Chisel has issues with 0-width wires require (addressBits >= 1) require (dataBits >= 8) require (sourceBits >= 1) require (sinkBits >= 1) require (sizeBits >= 1) require (isPow2(dataBits)) echoFields.foreach { f => require (f.key.isControl, s"${f} is not a legal echo field") } val addrLoBits = log2Up(dataBits/8) // Used to uniquify bus IP names def shortName = s"a${addressBits}d${dataBits}s${sourceBits}k${sinkBits}z${sizeBits}" + (if (hasBCE) "c" else "u") def union(x: TLBundleParameters) = TLBundleParameters( max(addressBits, x.addressBits), max(dataBits, x.dataBits), max(sourceBits, x.sourceBits), max(sinkBits, x.sinkBits), max(sizeBits, x.sizeBits), echoFields = BundleField.union(echoFields ++ x.echoFields), requestFields = BundleField.union(requestFields ++ x.requestFields), responseFields = BundleField.union(responseFields ++ x.responseFields), hasBCE \|\| x.hasBCE) } object TLBundleParameters { val emptyBundleParams = TLBundleParameters( addressBits = 1, dataBits = 8, sourceBits = 1, sinkBits = 1, sizeBits = 1, echoFields = Nil, requestFields = Nil, responseFields = Nil, hasBCE = false) def union(x: Seq[TLBundleParameters]) = x.foldLeft(emptyBundleParams)((x,y) => x.union(y)) def apply(master: TLMasterPortParameters, slave: TLSlavePortParameters) = new TLBundleParameters( addressBits = log2Up(slave.maxAddress + 1), dataBits = slave.beatBytes * 8, sourceBits = log2Up(master.endSourceId), sinkBits = log2Up(slave.endSinkId), sizeBits = log2Up(log2Ceil(max(master.maxTransfer, slave.maxTransfer))+1), echoFields = master.echoFields, requestFields = BundleField.accept(master.requestFields, slave.requestKeys), responseFields = BundleField.accept(slave.responseFields, master.responseKeys), hasBCE = master.anySupportProbe && slave.anySupportAcquireB) } case class TLEdgeParameters( master: TLMasterPortParameters, slave: TLSlavePortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge { // legacy names: def manager = slave def client = master val maxTransfer = max(master.maxTransfer, slave.maxTransfer) val maxLgSize = log2Ceil(maxTransfer) // Sanity check the link... require (maxTransfer >= slave.beatBytes, s"Link's max transfer (${maxTransfer}) < ${slave.slaves.map(_.name)}'s beatBytes (${slave.beatBytes})") def diplomaticClaimsMasterToSlave = master.anyEmitClaims.intersect(slave.anySupportClaims) val bundle = TLBundleParameters(master, slave) def formatEdge = master.infoString + "\n" + slave.infoString } case class TLCreditedDelay( a: CreditedDelay, b: CreditedDelay, c: CreditedDelay, d: CreditedDelay, e: CreditedDelay) { def + (that: TLCreditedDelay): TLCreditedDelay = TLCreditedDelay( a = a + that.a, b = b + that.b, c = c + that.c, d = d + that.d, e = e + that.e) override def toString = s"(${a}, ${b}, ${c}, ${d}, ${e})" } object TLCreditedDelay { def apply(delay: CreditedDelay): TLCreditedDelay = apply(delay, delay.flip, delay, delay.flip, delay) } case class TLCreditedManagerPortParameters(delay: TLCreditedDelay, base: TLSlavePortParameters) {def infoString = base.infoString} case class TLCreditedClientPortParameters(delay: TLCreditedDelay, base: TLMasterPortParameters) {def infoString = base.infoString} case class TLCreditedEdgeParameters(client: TLCreditedClientPortParameters, manager: TLCreditedManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge { val delay = client.delay + manager.delay val bundle = TLBundleParameters(client.base, manager.base) def formatEdge = client.infoString + "\n" + manager.infoString } case class TLAsyncManagerPortParameters(async: AsyncQueueParams, base: TLSlavePortParameters) {def infoString = base.infoString} case class TLAsyncClientPortParameters(base: TLMasterPortParameters) {def infoString = base.infoString} case class TLAsyncBundleParameters(async: AsyncQueueParams, base: TLBundleParameters) case class TLAsyncEdgeParameters(client: TLAsyncClientPortParameters, manager: TLAsyncManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge { val bundle = TLAsyncBundleParameters(manager.async, TLBundleParameters(client.base, manager.base)) def formatEdge = client.infoString + "\n" + manager.infoString } case class TLRationalManagerPortParameters(direction: RationalDirection, base: TLSlavePortParameters) {def infoString = base.infoString} case class TLRationalClientPortParameters(base: TLMasterPortParameters) {def infoString = base.infoString} case class TLRationalEdgeParameters(client: TLRationalClientPortParameters, manager: TLRationalManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge { val bundle = TLBundleParameters(client.base, manager.base) def formatEdge = client.infoString + "\n" + manager.infoString } // To be unified, devices must agree on all of these terms case class ManagerUnificationKey( resources: Seq[Resource], regionType: RegionType.T, executable: Boolean, supportsAcquireT: TransferSizes, supportsAcquireB: TransferSizes, supportsArithmetic: TransferSizes, supportsLogical: TransferSizes, supportsGet: TransferSizes, supportsPutFull: TransferSizes, supportsPutPartial: TransferSizes, supportsHint: TransferSizes) object ManagerUnificationKey { def apply(x: TLSlaveParameters): ManagerUnificationKey = ManagerUnificationKey( resources = x.resources, regionType = x.regionType, executable = x.executable, supportsAcquireT = x.supportsAcquireT, supportsAcquireB = x.supportsAcquireB, supportsArithmetic = x.supportsArithmetic, supportsLogical = x.supportsLogical, supportsGet = x.supportsGet, supportsPutFull = x.supportsPutFull, supportsPutPartial = x.supportsPutPartial, supportsHint = x.supportsHint) } object ManagerUnification { def apply(slaves: Seq[TLSlaveParameters]): List[TLSlaveParameters] = { slaves.groupBy(ManagerUnificationKey.apply).values.map { seq => val agree = seq.forall(_.fifoId == seq.head.fifoId) seq(0).v1copy( address = AddressSet.unify(seq.flatMap(_.address)), fifoId = if (agree) seq(0).fifoId else None) }.toList } } case class TLBufferParams( a: BufferParams = BufferParams.none, b: BufferParams = BufferParams.none, c: BufferParams = BufferParams.none, d: BufferParams = BufferParams.none, e: BufferParams = BufferParams.none ) extends DirectedBuffers[TLBufferParams] { def copyIn(x: BufferParams) = this.copy(b = x, d = x) def copyOut(x: BufferParams) = this.copy(a = x, c = x, e = x) def copyInOut(x: BufferParams) = this.copyIn(x).copyOut(x) } /** Pretty printing of TL source id maps / class TLSourceIdMap(tl: TLMasterPortParameters) extends IdMap[TLSourceIdMapEntry] { private val tlDigits = String.valueOf(tl.endSourceId-1).length() protected val fmt = s"\t[%${tlDigits}d, %${tlDigits}d) %s%s%s" private val sorted = tl.masters.sortBy(_.sourceId) val mapping: Seq[TLSourceIdMapEntry] = sorted.map { case c => TLSourceIdMapEntry(c.sourceId, c.name, c.supports.probe, c.requestFifo) } } case class TLSourceIdMapEntry(tlId: IdRange, name: String, isCache: Boolean, requestFifo: Boolean) extends IdMapEntry { val from = tlId val to = tlId val maxTransactionsInFlight = Some(tlId.size) } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportPutFull \|\| manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB \|\| manager.anySupportGet \|\| manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportPutFull \|\| client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe \|\| client.anySupportGet \|\| client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet \|\| client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull \|\| client.anySupportPutPartial \|\| client.anySupportHint \|\| client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet \|\| manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull \|\| manager.anySupportPutPartial \|\| manager.anySupportHint \|\| manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) \|\| !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.ProbeAckData \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode \| small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U \|\| beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }	module TLMonitor_42( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input io_in_a_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [511:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input [511:0] io_in_d_bits_data, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [31:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [511:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7] wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7] wire [511:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_bits_source = 1'h0; // @[Monitor.scala:36:7] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire c_set = 1'h0; // @[Monitor.scala:738:34] wire c_set_wo_ready = 1'h0; // @[Monitor.scala:739:34] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire _source_ok_T_1 = 1'h1; // @[Parameters.scala:46:9] wire _source_ok_WIRE_1_0 = 1'h1; // @[Parameters.scala:1138:31] wire sink_ok = 1'h1; // @[Monitor.scala:309:31] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire _same_cycle_resp_T_8 = 1'h1; // @[Monitor.scala:795:113] wire [5:0] c_first_beats1_decode = 6'h0; // @[Edges.scala:220:59] wire [5:0] c_first_beats1 = 6'h0; // @[Edges.scala:221:14] wire [5:0] _c_first_count_T = 6'h0; // @[Edges.scala:234:27] wire [5:0] c_first_count = 6'h0; // @[Edges.scala:234:25] wire [5:0] _c_first_counter_T = 6'h0; // @[Edges.scala:236:21] wire [5:0] c_first_counter1 = 6'h3F; // @[Edges.scala:230:28] wire [6:0] _c_first_counter1_T = 7'h7F; // @[Edges.scala:230:28] wire [511:0] _c_first_WIRE_bits_data = 512'h0; // @[Bundles.scala:265:74] wire [511:0] _c_first_WIRE_1_bits_data = 512'h0; // @[Bundles.scala:265:61] wire [511:0] _c_first_WIRE_2_bits_data = 512'h0; // @[Bundles.scala:265:74] wire [511:0] _c_first_WIRE_3_bits_data = 512'h0; // @[Bundles.scala:265:61] wire [511:0] _c_set_wo_ready_WIRE_bits_data = 512'h0; // @[Bundles.scala:265:74] wire [511:0] _c_set_wo_ready_WIRE_1_bits_data = 512'h0; // @[Bundles.scala:265:61] wire [511:0] _c_set_WIRE_bits_data = 512'h0; // @[Bundles.scala:265:74] wire [511:0] _c_set_WIRE_1_bits_data = 512'h0; // @[Bundles.scala:265:61] wire [511:0] _c_opcodes_set_interm_WIRE_bits_data = 512'h0; // @[Bundles.scala:265:74] wire [511:0] _c_opcodes_set_interm_WIRE_1_bits_data = 512'h0; // @[Bundles.scala:265:61] wire [511:0] _c_sizes_set_interm_WIRE_bits_data = 512'h0; // @[Bundles.scala:265:74] wire [511:0] _c_sizes_set_interm_WIRE_1_bits_data = 512'h0; // @[Bundles.scala:265:61] wire [511:0] _c_opcodes_set_WIRE_bits_data = 512'h0; // @[Bundles.scala:265:74] wire [511:0] _c_opcodes_set_WIRE_1_bits_data = 512'h0; // @[Bundles.scala:265:61] wire [511:0] _c_sizes_set_WIRE_bits_data = 512'h0; // @[Bundles.scala:265:74] wire [511:0] _c_sizes_set_WIRE_1_bits_data = 512'h0; // @[Bundles.scala:265:61] wire [511:0] _c_probe_ack_WIRE_bits_data = 512'h0; // @[Bundles.scala:265:74] wire [511:0] _c_probe_ack_WIRE_1_bits_data = 512'h0; // @[Bundles.scala:265:61] wire [511:0] _c_probe_ack_WIRE_2_bits_data = 512'h0; // @[Bundles.scala:265:74] wire [511:0] _c_probe_ack_WIRE_3_bits_data = 512'h0; // @[Bundles.scala:265:61] wire [511:0] _same_cycle_resp_WIRE_bits_data = 512'h0; // @[Bundles.scala:265:74] wire [511:0] _same_cycle_resp_WIRE_1_bits_data = 512'h0; // @[Bundles.scala:265:61] wire [511:0] _same_cycle_resp_WIRE_2_bits_data = 512'h0; // @[Bundles.scala:265:74] wire [511:0] _same_cycle_resp_WIRE_3_bits_data = 512'h0; // @[Bundles.scala:265:61] wire [511:0] _same_cycle_resp_WIRE_4_bits_data = 512'h0; // @[Bundles.scala:265:74] wire [511:0] _same_cycle_resp_WIRE_5_bits_data = 512'h0; // @[Bundles.scala:265:61] wire [31:0] _c_first_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_first_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_wo_ready_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_wo_ready_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_4_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_5_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [3:0] _a_opcode_lookup_T = 4'h0; // @[Monitor.scala:637:69] wire [3:0] _a_size_lookup_T = 4'h0; // @[Monitor.scala:641:65] wire [3:0] _d_opcodes_clr_T_4 = 4'h0; // @[Monitor.scala:680:101] wire [3:0] _d_sizes_clr_T_4 = 4'h0; // @[Monitor.scala:681:99] wire [3:0] _c_first_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] c_opcodes_set = 4'h0; // @[Monitor.scala:740:34] wire [3:0] _c_opcode_lookup_T = 4'h0; // @[Monitor.scala:749:69] wire [3:0] _c_size_lookup_T = 4'h0; // @[Monitor.scala:750:67] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] _c_set_wo_ready_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_wo_ready_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_sizes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_T = 4'h0; // @[Monitor.scala:767:79] wire [3:0] _c_sizes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_sizes_set_T = 4'h0; // @[Monitor.scala:768:77] wire [3:0] _c_probe_ack_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _d_opcodes_clr_T_10 = 4'h0; // @[Monitor.scala:790:101] wire [3:0] _d_sizes_clr_T_10 = 4'h0; // @[Monitor.scala:791:99] wire [3:0] _same_cycle_resp_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_4_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_5_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [30:0] _d_sizes_clr_T_5 = 31'hFF; // @[Monitor.scala:681:74] wire [30:0] _d_sizes_clr_T_11 = 31'hFF; // @[Monitor.scala:791:74] wire [15:0] _a_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _c_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hFF; // @[Monitor.scala:724:57] wire [16:0] _a_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _c_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hFF; // @[Monitor.scala:724:57] wire [15:0] _a_size_lookup_T_3 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _c_size_lookup_T_3 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h100; // @[Monitor.scala:724:51] wire [30:0] _d_opcodes_clr_T_5 = 31'hF; // @[Monitor.scala:680:76] wire [30:0] _d_opcodes_clr_T_11 = 31'hF; // @[Monitor.scala:790:76] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [1:0] _d_clr_wo_ready_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _d_clr_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _c_set_wo_ready_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _c_set_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _d_clr_wo_ready_T_1 = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _d_clr_T_1 = 2'h1; // @[OneHot.scala:58:35] wire [19:0] _c_sizes_set_T_1 = 20'h0; // @[Monitor.scala:768:52] wire [18:0] _c_opcodes_set_T_1 = 19'h0; // @[Monitor.scala:767:54] wire [4:0] _c_sizes_set_interm_T_1 = 5'h1; // @[Monitor.scala:766:59] wire [4:0] c_sizes_set_interm = 5'h0; // @[Monitor.scala:755:40] wire [4:0] _c_sizes_set_interm_T = 5'h0; // @[Monitor.scala:766:51] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [7:0] c_sizes_set = 8'h0; // @[Monitor.scala:741:34] wire [11:0] _c_first_beats1_decode_T_2 = 12'h0; // @[package.scala:243:46] wire [11:0] _c_first_beats1_decode_T_1 = 12'hFFF; // @[package.scala:243:76] wire [26:0] _c_first_beats1_decode_T = 27'hFFF; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [3:0] _a_size_lookup_T_2 = 4'h8; // @[Monitor.scala:641:117] wire [3:0] _d_sizes_clr_T = 4'h8; // @[Monitor.scala:681:48] wire [3:0] _c_size_lookup_T_2 = 4'h8; // @[Monitor.scala:750:119] wire [3:0] _d_sizes_clr_T_6 = 4'h8; // @[Monitor.scala:791:48] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire _source_ok_T = ~io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31] wire [26:0] _GEN = 27'hFFF << io_in_a_bits_size_0; // @[package.scala:243:71] wire [26:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [11:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [31:0] _is_aligned_T = {20'h0, io_in_a_bits_address_0[11:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 32'h0; // @[Edges.scala:21:{16,24}] wire [5:0] _mask_sizeOH_T = {2'h0, io_in_a_bits_size_0}; // @[Misc.scala:202:34] wire [2:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[2:0]; // @[OneHot.scala:64:49] wire [7:0] _mask_sizeOH_T_1 = 8'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [5:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[5:0]; // @[OneHot.scala:65:{12,27}] wire [5:0] mask_sizeOH = {_mask_sizeOH_T_2[5:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 4'h5; // @[Misc.scala:206:21] wire mask_sub_sub_sub_sub_sub_size = mask_sizeOH[5]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_sub_sub_sub_bit = io_in_a_bits_address_0[5]; // @[Misc.scala:210:26] wire mask_sub_sub_sub_sub_sub_1_2 = mask_sub_sub_sub_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_sub_sub_sub_nbit = ~mask_sub_sub_sub_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_sub_sub_sub_0_2 = mask_sub_sub_sub_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_sub_sub_sub_acc_T = mask_sub_sub_sub_sub_sub_size & mask_sub_sub_sub_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_sub_sub_sub_0_1 = mask_sub_sub_sub_sub_sub_sub_0_1 \| _mask_sub_sub_sub_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_sub_sub_sub_acc_T_1 = mask_sub_sub_sub_sub_sub_size & mask_sub_sub_sub_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_sub_sub_sub_1_1 = mask_sub_sub_sub_sub_sub_sub_0_1 \| _mask_sub_sub_sub_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_sub_sub_sub_size = mask_sizeOH[4]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_sub_sub_bit = io_in_a_bits_address_0[4]; // @[Misc.scala:210:26] wire mask_sub_sub_sub_sub_nbit = ~mask_sub_sub_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_sub_sub_0_2 = mask_sub_sub_sub_sub_sub_0_2 & mask_sub_sub_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_sub_sub_acc_T = mask_sub_sub_sub_sub_size & mask_sub_sub_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_sub_sub_0_1 = mask_sub_sub_sub_sub_sub_0_1 \| _mask_sub_sub_sub_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_sub_sub_1_2 = mask_sub_sub_sub_sub_sub_0_2 & mask_sub_sub_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_sub_sub_sub_acc_T_1 = mask_sub_sub_sub_sub_size & mask_sub_sub_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_sub_sub_1_1 = mask_sub_sub_sub_sub_sub_0_1 \| _mask_sub_sub_sub_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_sub_sub_2_2 = mask_sub_sub_sub_sub_sub_1_2 & mask_sub_sub_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_sub_sub_acc_T_2 = mask_sub_sub_sub_sub_size & mask_sub_sub_sub_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_sub_sub_2_1 = mask_sub_sub_sub_sub_sub_1_1 \| _mask_sub_sub_sub_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_sub_sub_3_2 = mask_sub_sub_sub_sub_sub_1_2 & mask_sub_sub_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_sub_sub_sub_acc_T_3 = mask_sub_sub_sub_sub_size & mask_sub_sub_sub_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_sub_sub_3_1 = mask_sub_sub_sub_sub_sub_1_1 \| _mask_sub_sub_sub_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_sub_size = mask_sizeOH[3]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_sub_bit = io_in_a_bits_address_0[3]; // @[Misc.scala:210:26] wire mask_sub_sub_sub_nbit = ~mask_sub_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_sub_0_2 = mask_sub_sub_sub_sub_0_2 & mask_sub_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_sub_acc_T = mask_sub_sub_sub_size & mask_sub_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_sub_0_1 = mask_sub_sub_sub_sub_0_1 \| _mask_sub_sub_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_sub_1_2 = mask_sub_sub_sub_sub_0_2 & mask_sub_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_sub_sub_acc_T_1 = mask_sub_sub_sub_size & mask_sub_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_sub_1_1 = mask_sub_sub_sub_sub_0_1 \| _mask_sub_sub_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_sub_2_2 = mask_sub_sub_sub_sub_1_2 & mask_sub_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_sub_acc_T_2 = mask_sub_sub_sub_size & mask_sub_sub_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_sub_2_1 = mask_sub_sub_sub_sub_1_1 \| _mask_sub_sub_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_sub_3_2 = mask_sub_sub_sub_sub_1_2 & mask_sub_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_sub_sub_acc_T_3 = mask_sub_sub_sub_size & mask_sub_sub_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_sub_3_1 = mask_sub_sub_sub_sub_1_1 \| _mask_sub_sub_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_sub_4_2 = mask_sub_sub_sub_sub_2_2 & mask_sub_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_sub_acc_T_4 = mask_sub_sub_sub_size & mask_sub_sub_sub_4_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_sub_4_1 = mask_sub_sub_sub_sub_2_1 \| _mask_sub_sub_sub_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_sub_5_2 = mask_sub_sub_sub_sub_2_2 & mask_sub_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_sub_sub_acc_T_5 = mask_sub_sub_sub_size & mask_sub_sub_sub_5_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_sub_5_1 = mask_sub_sub_sub_sub_2_1 \| _mask_sub_sub_sub_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_sub_6_2 = mask_sub_sub_sub_sub_3_2 & mask_sub_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_sub_acc_T_6 = mask_sub_sub_sub_size & mask_sub_sub_sub_6_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_sub_6_1 = mask_sub_sub_sub_sub_3_1 \| _mask_sub_sub_sub_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_sub_7_2 = mask_sub_sub_sub_sub_3_2 & mask_sub_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_sub_sub_acc_T_7 = mask_sub_sub_sub_size & mask_sub_sub_sub_7_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_sub_7_1 = mask_sub_sub_sub_sub_3_1 \| _mask_sub_sub_sub_acc_T_7; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_sub_0_2 & mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_1_2 = mask_sub_sub_sub_0_2 & mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_2_2 = mask_sub_sub_sub_1_2 & mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T_2 = mask_sub_sub_size & mask_sub_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_2_1 = mask_sub_sub_sub_1_1 \| _mask_sub_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_3_2 = mask_sub_sub_sub_1_2 & mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_sub_acc_T_3 = mask_sub_sub_size & mask_sub_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_3_1 = mask_sub_sub_sub_1_1 \| _mask_sub_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_4_2 = mask_sub_sub_sub_2_2 & mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T_4 = mask_sub_sub_size & mask_sub_sub_4_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_4_1 = mask_sub_sub_sub_2_1 \| _mask_sub_sub_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_5_2 = mask_sub_sub_sub_2_2 & mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_sub_acc_T_5 = mask_sub_sub_size & mask_sub_sub_5_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_5_1 = mask_sub_sub_sub_2_1 \| _mask_sub_sub_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_6_2 = mask_sub_sub_sub_3_2 & mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T_6 = mask_sub_sub_size & mask_sub_sub_6_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_6_1 = mask_sub_sub_sub_3_1 \| _mask_sub_sub_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_7_2 = mask_sub_sub_sub_3_2 & mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_sub_acc_T_7 = mask_sub_sub_size & mask_sub_sub_7_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_7_1 = mask_sub_sub_sub_3_1 \| _mask_sub_sub_acc_T_7; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_8_2 = mask_sub_sub_sub_4_2 & mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T_8 = mask_sub_sub_size & mask_sub_sub_8_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_8_1 = mask_sub_sub_sub_4_1 \| _mask_sub_sub_acc_T_8; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_9_2 = mask_sub_sub_sub_4_2 & mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_sub_acc_T_9 = mask_sub_sub_size & mask_sub_sub_9_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_9_1 = mask_sub_sub_sub_4_1 \| _mask_sub_sub_acc_T_9; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_10_2 = mask_sub_sub_sub_5_2 & mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T_10 = mask_sub_sub_size & mask_sub_sub_10_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_10_1 = mask_sub_sub_sub_5_1 \| _mask_sub_sub_acc_T_10; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_11_2 = mask_sub_sub_sub_5_2 & mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_sub_acc_T_11 = mask_sub_sub_size & mask_sub_sub_11_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_11_1 = mask_sub_sub_sub_5_1 \| _mask_sub_sub_acc_T_11; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_12_2 = mask_sub_sub_sub_6_2 & mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T_12 = mask_sub_sub_size & mask_sub_sub_12_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_12_1 = mask_sub_sub_sub_6_1 \| _mask_sub_sub_acc_T_12; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_13_2 = mask_sub_sub_sub_6_2 & mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_sub_acc_T_13 = mask_sub_sub_size & mask_sub_sub_13_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_13_1 = mask_sub_sub_sub_6_1 \| _mask_sub_sub_acc_T_13; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_14_2 = mask_sub_sub_sub_7_2 & mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T_14 = mask_sub_sub_size & mask_sub_sub_14_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_14_1 = mask_sub_sub_sub_7_1 \| _mask_sub_sub_acc_T_14; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_15_2 = mask_sub_sub_sub_7_2 & mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_sub_acc_T_15 = mask_sub_sub_size & mask_sub_sub_15_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_15_1 = mask_sub_sub_sub_7_1 \| _mask_sub_sub_acc_T_15; // @[Misc.scala:215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_sub_4_2 = mask_sub_sub_2_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_4 = mask_sub_size & mask_sub_4_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_4_1 = mask_sub_sub_2_1 \| _mask_sub_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_sub_5_2 = mask_sub_sub_2_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_5 = mask_sub_size & mask_sub_5_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_5_1 = mask_sub_sub_2_1 \| _mask_sub_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_sub_6_2 = mask_sub_sub_3_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_6 = mask_sub_size & mask_sub_6_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_6_1 = mask_sub_sub_3_1 \| _mask_sub_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_sub_7_2 = mask_sub_sub_3_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_7 = mask_sub_size & mask_sub_7_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_7_1 = mask_sub_sub_3_1 \| _mask_sub_acc_T_7; // @[Misc.scala:215:{29,38}] wire mask_sub_8_2 = mask_sub_sub_4_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_8 = mask_sub_size & mask_sub_8_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_8_1 = mask_sub_sub_4_1 \| _mask_sub_acc_T_8; // @[Misc.scala:215:{29,38}] wire mask_sub_9_2 = mask_sub_sub_4_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_9 = mask_sub_size & mask_sub_9_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_9_1 = mask_sub_sub_4_1 \| _mask_sub_acc_T_9; // @[Misc.scala:215:{29,38}] wire mask_sub_10_2 = mask_sub_sub_5_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_10 = mask_sub_size & mask_sub_10_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_10_1 = mask_sub_sub_5_1 \| _mask_sub_acc_T_10; // @[Misc.scala:215:{29,38}] wire mask_sub_11_2 = mask_sub_sub_5_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_11 = mask_sub_size & mask_sub_11_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_11_1 = mask_sub_sub_5_1 \| _mask_sub_acc_T_11; // @[Misc.scala:215:{29,38}] wire mask_sub_12_2 = mask_sub_sub_6_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_12 = mask_sub_size & mask_sub_12_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_12_1 = mask_sub_sub_6_1 \| _mask_sub_acc_T_12; // @[Misc.scala:215:{29,38}] wire mask_sub_13_2 = mask_sub_sub_6_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_13 = mask_sub_size & mask_sub_13_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_13_1 = mask_sub_sub_6_1 \| _mask_sub_acc_T_13; // @[Misc.scala:215:{29,38}] wire mask_sub_14_2 = mask_sub_sub_7_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_14 = mask_sub_size & mask_sub_14_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_14_1 = mask_sub_sub_7_1 \| _mask_sub_acc_T_14; // @[Misc.scala:215:{29,38}] wire mask_sub_15_2 = mask_sub_sub_7_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_15 = mask_sub_size & mask_sub_15_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_15_1 = mask_sub_sub_7_1 \| _mask_sub_acc_T_15; // @[Misc.scala:215:{29,38}] wire mask_sub_16_2 = mask_sub_sub_8_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_16 = mask_sub_size & mask_sub_16_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_16_1 = mask_sub_sub_8_1 \| _mask_sub_acc_T_16; // @[Misc.scala:215:{29,38}] wire mask_sub_17_2 = mask_sub_sub_8_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_17 = mask_sub_size & mask_sub_17_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_17_1 = mask_sub_sub_8_1 \| _mask_sub_acc_T_17; // @[Misc.scala:215:{29,38}] wire mask_sub_18_2 = mask_sub_sub_9_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_18 = mask_sub_size & mask_sub_18_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_18_1 = mask_sub_sub_9_1 \| _mask_sub_acc_T_18; // @[Misc.scala:215:{29,38}] wire mask_sub_19_2 = mask_sub_sub_9_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_19 = mask_sub_size & mask_sub_19_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_19_1 = mask_sub_sub_9_1 \| _mask_sub_acc_T_19; // @[Misc.scala:215:{29,38}] wire mask_sub_20_2 = mask_sub_sub_10_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_20 = mask_sub_size & mask_sub_20_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_20_1 = mask_sub_sub_10_1 \| _mask_sub_acc_T_20; // @[Misc.scala:215:{29,38}] wire mask_sub_21_2 = mask_sub_sub_10_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_21 = mask_sub_size & mask_sub_21_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_21_1 = mask_sub_sub_10_1 \| _mask_sub_acc_T_21; // @[Misc.scala:215:{29,38}] wire mask_sub_22_2 = mask_sub_sub_11_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_22 = mask_sub_size & mask_sub_22_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_22_1 = mask_sub_sub_11_1 \| _mask_sub_acc_T_22; // @[Misc.scala:215:{29,38}] wire mask_sub_23_2 = mask_sub_sub_11_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_23 = mask_sub_size & mask_sub_23_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_23_1 = mask_sub_sub_11_1 \| _mask_sub_acc_T_23; // @[Misc.scala:215:{29,38}] wire mask_sub_24_2 = mask_sub_sub_12_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_24 = mask_sub_size & mask_sub_24_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_24_1 = mask_sub_sub_12_1 \| _mask_sub_acc_T_24; // @[Misc.scala:215:{29,38}] wire mask_sub_25_2 = mask_sub_sub_12_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_25 = mask_sub_size & mask_sub_25_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_25_1 = mask_sub_sub_12_1 \| _mask_sub_acc_T_25; // @[Misc.scala:215:{29,38}] wire mask_sub_26_2 = mask_sub_sub_13_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_26 = mask_sub_size & mask_sub_26_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_26_1 = mask_sub_sub_13_1 \| _mask_sub_acc_T_26; // @[Misc.scala:215:{29,38}] wire mask_sub_27_2 = mask_sub_sub_13_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_27 = mask_sub_size & mask_sub_27_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_27_1 = mask_sub_sub_13_1 \| _mask_sub_acc_T_27; // @[Misc.scala:215:{29,38}] wire mask_sub_28_2 = mask_sub_sub_14_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_28 = mask_sub_size & mask_sub_28_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_28_1 = mask_sub_sub_14_1 \| _mask_sub_acc_T_28; // @[Misc.scala:215:{29,38}] wire mask_sub_29_2 = mask_sub_sub_14_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_29 = mask_sub_size & mask_sub_29_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_29_1 = mask_sub_sub_14_1 \| _mask_sub_acc_T_29; // @[Misc.scala:215:{29,38}] wire mask_sub_30_2 = mask_sub_sub_15_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_30 = mask_sub_size & mask_sub_30_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_30_1 = mask_sub_sub_15_1 \| _mask_sub_acc_T_30; // @[Misc.scala:215:{29,38}] wire mask_sub_31_2 = mask_sub_sub_15_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_31 = mask_sub_size & mask_sub_31_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_31_1 = mask_sub_sub_15_1 \| _mask_sub_acc_T_31; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 \| _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 \| _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 \| _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 \| _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 \| _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 \| _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 \| _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 \| _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire mask_eq_8 = mask_sub_4_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_8 = mask_size & mask_eq_8; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_8 = mask_sub_4_1 \| _mask_acc_T_8; // @[Misc.scala:215:{29,38}] wire mask_eq_9 = mask_sub_4_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_9 = mask_size & mask_eq_9; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_9 = mask_sub_4_1 \| _mask_acc_T_9; // @[Misc.scala:215:{29,38}] wire mask_eq_10 = mask_sub_5_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_10 = mask_size & mask_eq_10; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_10 = mask_sub_5_1 \| _mask_acc_T_10; // @[Misc.scala:215:{29,38}] wire mask_eq_11 = mask_sub_5_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_11 = mask_size & mask_eq_11; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_11 = mask_sub_5_1 \| _mask_acc_T_11; // @[Misc.scala:215:{29,38}] wire mask_eq_12 = mask_sub_6_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_12 = mask_size & mask_eq_12; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_12 = mask_sub_6_1 \| _mask_acc_T_12; // @[Misc.scala:215:{29,38}] wire mask_eq_13 = mask_sub_6_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_13 = mask_size & mask_eq_13; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_13 = mask_sub_6_1 \| _mask_acc_T_13; // @[Misc.scala:215:{29,38}] wire mask_eq_14 = mask_sub_7_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_14 = mask_size & mask_eq_14; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_14 = mask_sub_7_1 \| _mask_acc_T_14; // @[Misc.scala:215:{29,38}] wire mask_eq_15 = mask_sub_7_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_15 = mask_size & mask_eq_15; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_15 = mask_sub_7_1 \| _mask_acc_T_15; // @[Misc.scala:215:{29,38}] wire mask_eq_16 = mask_sub_8_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_16 = mask_size & mask_eq_16; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_16 = mask_sub_8_1 \| _mask_acc_T_16; // @[Misc.scala:215:{29,38}] wire mask_eq_17 = mask_sub_8_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_17 = mask_size & mask_eq_17; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_17 = mask_sub_8_1 \| _mask_acc_T_17; // @[Misc.scala:215:{29,38}] wire mask_eq_18 = mask_sub_9_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_18 = mask_size & mask_eq_18; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_18 = mask_sub_9_1 \| _mask_acc_T_18; // @[Misc.scala:215:{29,38}] wire mask_eq_19 = mask_sub_9_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_19 = mask_size & mask_eq_19; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_19 = mask_sub_9_1 \| _mask_acc_T_19; // @[Misc.scala:215:{29,38}] wire mask_eq_20 = mask_sub_10_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_20 = mask_size & mask_eq_20; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_20 = mask_sub_10_1 \| _mask_acc_T_20; // @[Misc.scala:215:{29,38}] wire mask_eq_21 = mask_sub_10_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_21 = mask_size & mask_eq_21; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_21 = mask_sub_10_1 \| _mask_acc_T_21; // @[Misc.scala:215:{29,38}] wire mask_eq_22 = mask_sub_11_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_22 = mask_size & mask_eq_22; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_22 = mask_sub_11_1 \| _mask_acc_T_22; // @[Misc.scala:215:{29,38}] wire mask_eq_23 = mask_sub_11_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_23 = mask_size & mask_eq_23; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_23 = mask_sub_11_1 \| _mask_acc_T_23; // @[Misc.scala:215:{29,38}] wire mask_eq_24 = mask_sub_12_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_24 = mask_size & mask_eq_24; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_24 = mask_sub_12_1 \| _mask_acc_T_24; // @[Misc.scala:215:{29,38}] wire mask_eq_25 = mask_sub_12_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_25 = mask_size & mask_eq_25; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_25 = mask_sub_12_1 \| _mask_acc_T_25; // @[Misc.scala:215:{29,38}] wire mask_eq_26 = mask_sub_13_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_26 = mask_size & mask_eq_26; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_26 = mask_sub_13_1 \| _mask_acc_T_26; // @[Misc.scala:215:{29,38}] wire mask_eq_27 = mask_sub_13_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_27 = mask_size & mask_eq_27; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_27 = mask_sub_13_1 \| _mask_acc_T_27; // @[Misc.scala:215:{29,38}] wire mask_eq_28 = mask_sub_14_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_28 = mask_size & mask_eq_28; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_28 = mask_sub_14_1 \| _mask_acc_T_28; // @[Misc.scala:215:{29,38}] wire mask_eq_29 = mask_sub_14_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_29 = mask_size & mask_eq_29; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_29 = mask_sub_14_1 \| _mask_acc_T_29; // @[Misc.scala:215:{29,38}] wire mask_eq_30 = mask_sub_15_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_30 = mask_size & mask_eq_30; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_30 = mask_sub_15_1 \| _mask_acc_T_30; // @[Misc.scala:215:{29,38}] wire mask_eq_31 = mask_sub_15_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_31 = mask_size & mask_eq_31; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_31 = mask_sub_15_1 \| _mask_acc_T_31; // @[Misc.scala:215:{29,38}] wire mask_eq_32 = mask_sub_16_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_32 = mask_size & mask_eq_32; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_32 = mask_sub_16_1 \| _mask_acc_T_32; // @[Misc.scala:215:{29,38}] wire mask_eq_33 = mask_sub_16_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_33 = mask_size & mask_eq_33; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_33 = mask_sub_16_1 \| _mask_acc_T_33; // @[Misc.scala:215:{29,38}] wire mask_eq_34 = mask_sub_17_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_34 = mask_size & mask_eq_34; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_34 = mask_sub_17_1 \| _mask_acc_T_34; // @[Misc.scala:215:{29,38}] wire mask_eq_35 = mask_sub_17_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_35 = mask_size & mask_eq_35; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_35 = mask_sub_17_1 \| _mask_acc_T_35; // @[Misc.scala:215:{29,38}] wire mask_eq_36 = mask_sub_18_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_36 = mask_size & mask_eq_36; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_36 = mask_sub_18_1 \| _mask_acc_T_36; // @[Misc.scala:215:{29,38}] wire mask_eq_37 = mask_sub_18_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_37 = mask_size & mask_eq_37; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_37 = mask_sub_18_1 \| _mask_acc_T_37; // @[Misc.scala:215:{29,38}] wire mask_eq_38 = mask_sub_19_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_38 = mask_size & mask_eq_38; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_38 = mask_sub_19_1 \| _mask_acc_T_38; // @[Misc.scala:215:{29,38}] wire mask_eq_39 = mask_sub_19_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_39 = mask_size & mask_eq_39; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_39 = mask_sub_19_1 \| _mask_acc_T_39; // @[Misc.scala:215:{29,38}] wire mask_eq_40 = mask_sub_20_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_40 = mask_size & mask_eq_40; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_40 = mask_sub_20_1 \| _mask_acc_T_40; // @[Misc.scala:215:{29,38}] wire mask_eq_41 = mask_sub_20_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_41 = mask_size & mask_eq_41; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_41 = mask_sub_20_1 \| _mask_acc_T_41; // @[Misc.scala:215:{29,38}] wire mask_eq_42 = mask_sub_21_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_42 = mask_size & mask_eq_42; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_42 = mask_sub_21_1 \| _mask_acc_T_42; // @[Misc.scala:215:{29,38}] wire mask_eq_43 = mask_sub_21_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_43 = mask_size & mask_eq_43; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_43 = mask_sub_21_1 \| _mask_acc_T_43; // @[Misc.scala:215:{29,38}] wire mask_eq_44 = mask_sub_22_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_44 = mask_size & mask_eq_44; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_44 = mask_sub_22_1 \| _mask_acc_T_44; // @[Misc.scala:215:{29,38}] wire mask_eq_45 = mask_sub_22_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_45 = mask_size & mask_eq_45; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_45 = mask_sub_22_1 \| _mask_acc_T_45; // @[Misc.scala:215:{29,38}] wire mask_eq_46 = mask_sub_23_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_46 = mask_size & mask_eq_46; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_46 = mask_sub_23_1 \| _mask_acc_T_46; // @[Misc.scala:215:{29,38}] wire mask_eq_47 = mask_sub_23_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_47 = mask_size & mask_eq_47; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_47 = mask_sub_23_1 \| _mask_acc_T_47; // @[Misc.scala:215:{29,38}] wire mask_eq_48 = mask_sub_24_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_48 = mask_size & mask_eq_48; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_48 = mask_sub_24_1 \| _mask_acc_T_48; // @[Misc.scala:215:{29,38}] wire mask_eq_49 = mask_sub_24_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_49 = mask_size & mask_eq_49; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_49 = mask_sub_24_1 \| _mask_acc_T_49; // @[Misc.scala:215:{29,38}] wire mask_eq_50 = mask_sub_25_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_50 = mask_size & mask_eq_50; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_50 = mask_sub_25_1 \| _mask_acc_T_50; // @[Misc.scala:215:{29,38}] wire mask_eq_51 = mask_sub_25_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_51 = mask_size & mask_eq_51; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_51 = mask_sub_25_1 \| _mask_acc_T_51; // @[Misc.scala:215:{29,38}] wire mask_eq_52 = mask_sub_26_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_52 = mask_size & mask_eq_52; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_52 = mask_sub_26_1 \| _mask_acc_T_52; // @[Misc.scala:215:{29,38}] wire mask_eq_53 = mask_sub_26_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_53 = mask_size & mask_eq_53; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_53 = mask_sub_26_1 \| _mask_acc_T_53; // @[Misc.scala:215:{29,38}] wire mask_eq_54 = mask_sub_27_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_54 = mask_size & mask_eq_54; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_54 = mask_sub_27_1 \| _mask_acc_T_54; // @[Misc.scala:215:{29,38}] wire mask_eq_55 = mask_sub_27_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_55 = mask_size & mask_eq_55; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_55 = mask_sub_27_1 \| _mask_acc_T_55; // @[Misc.scala:215:{29,38}] wire mask_eq_56 = mask_sub_28_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_56 = mask_size & mask_eq_56; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_56 = mask_sub_28_1 \| _mask_acc_T_56; // @[Misc.scala:215:{29,38}] wire mask_eq_57 = mask_sub_28_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_57 = mask_size & mask_eq_57; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_57 = mask_sub_28_1 \| _mask_acc_T_57; // @[Misc.scala:215:{29,38}] wire mask_eq_58 = mask_sub_29_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_58 = mask_size & mask_eq_58; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_58 = mask_sub_29_1 \| _mask_acc_T_58; // @[Misc.scala:215:{29,38}] wire mask_eq_59 = mask_sub_29_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_59 = mask_size & mask_eq_59; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_59 = mask_sub_29_1 \| _mask_acc_T_59; // @[Misc.scala:215:{29,38}] wire mask_eq_60 = mask_sub_30_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_60 = mask_size & mask_eq_60; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_60 = mask_sub_30_1 \| _mask_acc_T_60; // @[Misc.scala:215:{29,38}] wire mask_eq_61 = mask_sub_30_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_61 = mask_size & mask_eq_61; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_61 = mask_sub_30_1 \| _mask_acc_T_61; // @[Misc.scala:215:{29,38}] wire mask_eq_62 = mask_sub_31_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_62 = mask_size & mask_eq_62; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_62 = mask_sub_31_1 \| _mask_acc_T_62; // @[Misc.scala:215:{29,38}] wire mask_eq_63 = mask_sub_31_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_63 = mask_size & mask_eq_63; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_63 = mask_sub_31_1 \| _mask_acc_T_63; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo_lo_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_lo_lo_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo_lo_lo_lo = {mask_lo_lo_lo_lo_hi, mask_lo_lo_lo_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_lo_lo_lo_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_lo_lo_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo_lo_lo_hi = {mask_lo_lo_lo_hi_hi, mask_lo_lo_lo_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask_lo_lo_lo = {mask_lo_lo_lo_hi, mask_lo_lo_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_lo_lo_hi_lo_lo = {mask_acc_9, mask_acc_8}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_lo_hi_lo_hi = {mask_acc_11, mask_acc_10}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo_lo_hi_lo = {mask_lo_lo_hi_lo_hi, mask_lo_lo_hi_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_lo_lo_hi_hi_lo = {mask_acc_13, mask_acc_12}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_lo_hi_hi_hi = {mask_acc_15, mask_acc_14}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo_lo_hi_hi = {mask_lo_lo_hi_hi_hi, mask_lo_lo_hi_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask_lo_lo_hi = {mask_lo_lo_hi_hi, mask_lo_lo_hi_lo}; // @[Misc.scala:222:10] wire [15:0] mask_lo_lo = {mask_lo_lo_hi, mask_lo_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_lo_hi_lo_lo_lo = {mask_acc_17, mask_acc_16}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi_lo_lo_hi = {mask_acc_19, mask_acc_18}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo_hi_lo_lo = {mask_lo_hi_lo_lo_hi, mask_lo_hi_lo_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_lo_hi_lo_hi_lo = {mask_acc_21, mask_acc_20}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi_lo_hi_hi = {mask_acc_23, mask_acc_22}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo_hi_lo_hi = {mask_lo_hi_lo_hi_hi, mask_lo_hi_lo_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask_lo_hi_lo = {mask_lo_hi_lo_hi, mask_lo_hi_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_lo_hi_hi_lo_lo = {mask_acc_25, mask_acc_24}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi_hi_lo_hi = {mask_acc_27, mask_acc_26}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo_hi_hi_lo = {mask_lo_hi_hi_lo_hi, mask_lo_hi_hi_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_lo_hi_hi_hi_lo = {mask_acc_29, mask_acc_28}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi_hi_hi_hi = {mask_acc_31, mask_acc_30}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo_hi_hi_hi = {mask_lo_hi_hi_hi_hi, mask_lo_hi_hi_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask_lo_hi_hi = {mask_lo_hi_hi_hi, mask_lo_hi_hi_lo}; // @[Misc.scala:222:10] wire [15:0] mask_lo_hi = {mask_lo_hi_hi, mask_lo_hi_lo}; // @[Misc.scala:222:10] wire [31:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo_lo_lo_lo = {mask_acc_33, mask_acc_32}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_lo_lo_lo_hi = {mask_acc_35, mask_acc_34}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi_lo_lo_lo = {mask_hi_lo_lo_lo_hi, mask_hi_lo_lo_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo_lo_hi_lo = {mask_acc_37, mask_acc_36}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_lo_lo_hi_hi = {mask_acc_39, mask_acc_38}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi_lo_lo_hi = {mask_hi_lo_lo_hi_hi, mask_hi_lo_lo_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask_hi_lo_lo = {mask_hi_lo_lo_hi, mask_hi_lo_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo_hi_lo_lo = {mask_acc_41, mask_acc_40}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_lo_hi_lo_hi = {mask_acc_43, mask_acc_42}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi_lo_hi_lo = {mask_hi_lo_hi_lo_hi, mask_hi_lo_hi_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo_hi_hi_lo = {mask_acc_45, mask_acc_44}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_lo_hi_hi_hi = {mask_acc_47, mask_acc_46}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi_lo_hi_hi = {mask_hi_lo_hi_hi_hi, mask_hi_lo_hi_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask_hi_lo_hi = {mask_hi_lo_hi_hi, mask_hi_lo_hi_lo}; // @[Misc.scala:222:10] wire [15:0] mask_hi_lo = {mask_hi_lo_hi, mask_hi_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_hi_lo_lo_lo = {mask_acc_49, mask_acc_48}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi_lo_lo_hi = {mask_acc_51, mask_acc_50}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi_hi_lo_lo = {mask_hi_hi_lo_lo_hi, mask_hi_hi_lo_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_hi_lo_hi_lo = {mask_acc_53, mask_acc_52}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi_lo_hi_hi = {mask_acc_55, mask_acc_54}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi_hi_lo_hi = {mask_hi_hi_lo_hi_hi, mask_hi_hi_lo_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask_hi_hi_lo = {mask_hi_hi_lo_hi, mask_hi_hi_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_hi_hi_lo_lo = {mask_acc_57, mask_acc_56}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi_hi_lo_hi = {mask_acc_59, mask_acc_58}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi_hi_hi_lo = {mask_hi_hi_hi_lo_hi, mask_hi_hi_hi_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_hi_hi_hi_lo = {mask_acc_61, mask_acc_60}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi_hi_hi_hi = {mask_acc_63, mask_acc_62}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi_hi_hi_hi = {mask_hi_hi_hi_hi_hi, mask_hi_hi_hi_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask_hi_hi_hi = {mask_hi_hi_hi_hi, mask_hi_hi_hi_lo}; // @[Misc.scala:222:10] wire [15:0] mask_hi_hi = {mask_hi_hi_hi, mask_hi_hi_lo}; // @[Misc.scala:222:10] wire [31:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [63:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire _T_1212 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_1212; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_1212; // @[Decoupled.scala:51:35] wire [11:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [5:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[11:6]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [5:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 6'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [5:0] a_first_counter; // @[Edges.scala:229:27] wire [6:0] _a_first_counter1_T = {1'h0, a_first_counter} - 7'h1; // @[Edges.scala:229:27, :230:28] wire [5:0] a_first_counter1 = _a_first_counter1_T[5:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 6'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 6'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 6'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T \| _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [5:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [5:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [5:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [3:0] size; // @[Monitor.scala:389:22] reg source; // @[Monitor.scala:390:22] reg [31:0] address; // @[Monitor.scala:391:22] wire _T_1285 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_1285; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_1285; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_1285; // @[Decoupled.scala:51:35] wire [26:0] _GEN_0 = 27'hFFF << io_in_d_bits_size_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [11:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [5:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[11:6]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [5:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 6'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [5:0] d_first_counter; // @[Edges.scala:229:27] wire [6:0] _d_first_counter1_T = {1'h0, d_first_counter} - 7'h1; // @[Edges.scala:229:27, :230:28] wire [5:0] d_first_counter1 = _d_first_counter1_T[5:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 6'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 6'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 6'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T \| _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [5:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [5:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [5:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [3:0] size_1; // @[Monitor.scala:540:22] reg [2:0] sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] reg [1:0] inflight; // @[Monitor.scala:614:27] reg [3:0] inflight_opcodes; // @[Monitor.scala:616:35] wire [3:0] _a_opcode_lookup_T_1 = inflight_opcodes; // @[Monitor.scala:616:35, :637:44] reg [7:0] inflight_sizes; // @[Monitor.scala:618:33] wire [7:0] _a_size_lookup_T_1 = inflight_sizes; // @[Monitor.scala:618:33, :641:40] wire [11:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [5:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[11:6]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [5:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 6'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [5:0] a_first_counter_1; // @[Edges.scala:229:27] wire [6:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 7'h1; // @[Edges.scala:229:27, :230:28] wire [5:0] a_first_counter1_1 = _a_first_counter1_T_1[5:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 6'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 6'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 6'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 \| _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [5:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [5:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [5:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [11:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [5:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[11:6]; // @[package.scala:243:46] wire [5:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 6'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [5:0] d_first_counter_1; // @[Edges.scala:229:27] wire [6:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 7'h1; // @[Edges.scala:229:27, :230:28] wire [5:0] d_first_counter1_1 = _d_first_counter1_T_1[5:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 6'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 6'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 6'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 \| _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [5:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [5:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [5:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire a_set; // @[Monitor.scala:626:34] wire a_set_wo_ready; // @[Monitor.scala:627:34] wire [3:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [7:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [15:0] _a_opcode_lookup_T_6 = {12'h0, _a_opcode_lookup_T_1}; // @[Monitor.scala:637:{44,97}] wire [15:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [7:0] a_size_lookup; // @[Monitor.scala:639:33] wire [15:0] _a_size_lookup_T_6 = {8'h0, _a_size_lookup_T_1}; // @[Monitor.scala:641:{40,91}] wire [15:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[15:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[7:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [4:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [1:0] _GEN_1 = {1'h0, io_in_a_bits_source_0}; // @[OneHot.scala:58:35] wire [1:0] _GEN_2 = 2'h1 << _GEN_1; // @[OneHot.scala:58:35] wire [1:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_2; // @[OneHot.scala:58:35] wire [1:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_2; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T & _a_set_wo_ready_T[0]; // @[OneHot.scala:58:35] wire _T_1138 = _T_1212 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_1138 & _a_set_T[0]; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_1138 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [4:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [4:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_1138 ? _a_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [3:0] _a_opcodes_set_T = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [18:0] _a_opcodes_set_T_1 = {15'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_1138 ? _a_opcodes_set_T_1[3:0] : 4'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [3:0] _a_sizes_set_T = {io_in_a_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :660:77] wire [19:0] _a_sizes_set_T_1 = {15'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :660:{52,77}] assign a_sizes_set = _T_1138 ? _a_sizes_set_T_1[7:0] : 8'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire d_clr; // @[Monitor.scala:664:34] wire d_clr_wo_ready; // @[Monitor.scala:665:34] wire [3:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [7:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_3 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_3; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_3; // @[Monitor.scala:673:46, :783:46] wire _T_1184 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] assign d_clr_wo_ready = _T_1184 & ~d_release_ack; // @[Monitor.scala:665:34, :673:46, :674:{26,71,74}] assign d_clr = _T_1285 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_opcodes_clr = {4{d_clr}}; // @[Monitor.scala:664:34, :668:33, :678:89, :680:21] assign d_sizes_clr = {8{d_clr}}; // @[Monitor.scala:664:34, :670:31, :678:89, :681:21] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = ~io_in_a_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [1:0] _inflight_T = {inflight[1], inflight[0] \| a_set}; // @[Monitor.scala:614:27, :626:34, :705:27] wire _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [1:0] _inflight_T_2 = {1'h0, _inflight_T[0] & _inflight_T_1}; // @[Monitor.scala:705:{27,36,38}] wire [3:0] _inflight_opcodes_T = inflight_opcodes \| a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [3:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [3:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [7:0] _inflight_sizes_T = inflight_sizes \| a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [7:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [7:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [1:0] inflight_1; // @[Monitor.scala:726:35] wire [1:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [3:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [3:0] _c_opcode_lookup_T_1 = inflight_opcodes_1; // @[Monitor.scala:727:35, :749:44] wire [3:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [7:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [7:0] _c_size_lookup_T_1 = inflight_sizes_1; // @[Monitor.scala:728:35, :750:42] wire [7:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire [11:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [5:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[11:6]; // @[package.scala:243:46] wire [5:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 6'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [5:0] d_first_counter_2; // @[Edges.scala:229:27] wire [6:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 7'h1; // @[Edges.scala:229:27, :230:28] wire [5:0] d_first_counter1_2 = _d_first_counter1_T_2[5:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 6'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 6'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 6'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 \| _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [5:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [5:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [5:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [7:0] c_size_lookup; // @[Monitor.scala:748:35] wire [15:0] _c_opcode_lookup_T_6 = {12'h0, _c_opcode_lookup_T_1}; // @[Monitor.scala:749:{44,97}] wire [15:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [15:0] _c_size_lookup_T_6 = {8'h0, _c_size_lookup_T_1}; // @[Monitor.scala:750:{42,93}] wire [15:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[15:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[7:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire d_clr_1; // @[Monitor.scala:774:34] wire d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [3:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [7:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_1256 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_1256 & d_release_ack_1; // @[Monitor.scala:775:34, :783:46, :784:{26,71}] assign d_clr_1 = _T_1285 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_opcodes_clr_1 = {4{d_clr_1}}; // @[Monitor.scala:774:34, :776:34, :788:88, :790:21] assign d_sizes_clr_1 = {8{d_clr_1}}; // @[Monitor.scala:774:34, :777:34, :788:88, :791:21] wire _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [1:0] _inflight_T_5 = {1'h0, _inflight_T_3[0] & _inflight_T_4}; // @[Monitor.scala:814:{35,44,46}] wire [3:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [3:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [7:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [7:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to the following Chisel files. File PE.scala: // See README.md for license details. package gemmini import chisel3._ import chisel3.util._ class PEControl[T <: Data : Arithmetic](accType: T) extends Bundle { val dataflow = UInt(1.W) // TODO make this an Enum val propagate = UInt(1.W) // Which register should be propagated (and which should be accumulated)? val shift = UInt(log2Up(accType.getWidth).W) // TODO this isn't correct for Floats } class MacUnit[T <: Data](inputType: T, cType: T, dType: T) (implicit ev: Arithmetic[T]) extends Module { import ev._ val io = IO(new Bundle { val in_a = Input(inputType) val in_b = Input(inputType) val in_c = Input(cType) val out_d = Output(dType) }) io.out_d := io.in_c.mac(io.in_a, io.in_b) } // TODO update documentation /** * A PE implementing a MAC operation. Configured as fully combinational when integrated into a Mesh. * @param width Data width of operands / class PE[T <: Data](inputType: T, outputType: T, accType: T, df: Dataflow.Value, max_simultaneous_matmuls: Int) (implicit ev: Arithmetic[T]) extends Module { // Debugging variables import ev._ val io = IO(new Bundle { val in_a = Input(inputType) val in_b = Input(outputType) val in_d = Input(outputType) val out_a = Output(inputType) val out_b = Output(outputType) val out_c = Output(outputType) val in_control = Input(new PEControl(accType)) val out_control = Output(new PEControl(accType)) val in_id = Input(UInt(log2Up(max_simultaneous_matmuls).W)) val out_id = Output(UInt(log2Up(max_simultaneous_matmuls).W)) val in_last = Input(Bool()) val out_last = Output(Bool()) val in_valid = Input(Bool()) val out_valid = Output(Bool()) val bad_dataflow = Output(Bool()) }) val cType = if (df == Dataflow.WS) inputType else accType // When creating PEs that support multiple dataflows, the // elaboration/synthesis tools often fail to consolidate and de-duplicate // MAC units. To force mac circuitry to be re-used, we create a "mac_unit" // module here which just performs a single MAC operation val mac_unit = Module(new MacUnit(inputType, if (df == Dataflow.WS) outputType else accType, outputType)) val a = io.in_a val b = io.in_b val d = io.in_d val c1 = Reg(cType) val c2 = Reg(cType) val dataflow = io.in_control.dataflow val prop = io.in_control.propagate val shift = io.in_control.shift val id = io.in_id val last = io.in_last val valid = io.in_valid io.out_a := a io.out_control.dataflow := dataflow io.out_control.propagate := prop io.out_control.shift := shift io.out_id := id io.out_last := last io.out_valid := valid mac_unit.io.in_a := a val last_s = RegEnable(prop, valid) val flip = last_s =/= prop val shift_offset = Mux(flip, shift, 0.U) // Which dataflow are we using? val OUTPUT_STATIONARY = Dataflow.OS.id.U(1.W) val WEIGHT_STATIONARY = Dataflow.WS.id.U(1.W) // Is c1 being computed on, or propagated forward (in the output-stationary dataflow)? val COMPUTE = 0.U(1.W) val PROPAGATE = 1.U(1.W) io.bad_dataflow := false.B when ((df == Dataflow.OS).B \|\| ((df == Dataflow.BOTH).B && dataflow === OUTPUT_STATIONARY)) { when(prop === PROPAGATE) { io.out_c := (c1 >> shift_offset).clippedToWidthOf(outputType) io.out_b := b mac_unit.io.in_b := b.asTypeOf(inputType) mac_unit.io.in_c := c2 c2 := mac_unit.io.out_d c1 := d.withWidthOf(cType) }.otherwise { io.out_c := (c2 >> shift_offset).clippedToWidthOf(outputType) io.out_b := b mac_unit.io.in_b := b.asTypeOf(inputType) mac_unit.io.in_c := c1 c1 := mac_unit.io.out_d c2 := d.withWidthOf(cType) } }.elsewhen ((df == Dataflow.WS).B \|\| ((df == Dataflow.BOTH).B && dataflow === WEIGHT_STATIONARY)) { when(prop === PROPAGATE) { io.out_c := c1 mac_unit.io.in_b := c2.asTypeOf(inputType) mac_unit.io.in_c := b io.out_b := mac_unit.io.out_d c1 := d }.otherwise { io.out_c := c2 mac_unit.io.in_b := c1.asTypeOf(inputType) mac_unit.io.in_c := b io.out_b := mac_unit.io.out_d c2 := d } }.otherwise { io.bad_dataflow := true.B //assert(false.B, "unknown dataflow") io.out_c := DontCare io.out_b := DontCare mac_unit.io.in_b := b.asTypeOf(inputType) mac_unit.io.in_c := c2 } when (!valid) { c1 := c1 c2 := c2 mac_unit.io.in_b := DontCare mac_unit.io.in_c := DontCare } } File Arithmetic.scala: // A simple type class for Chisel datatypes that can add and multiply. To add your own type, simply create your own: // implicit MyTypeArithmetic extends Arithmetic[MyType] { ... } package gemmini import chisel3._ import chisel3.util._ import hardfloat._ // Bundles that represent the raw bits of custom datatypes case class Float(expWidth: Int, sigWidth: Int) extends Bundle { val bits = UInt((expWidth + sigWidth).W) val bias: Int = (1 << (expWidth-1)) - 1 } case class DummySInt(w: Int) extends Bundle { val bits = UInt(w.W) def dontCare: DummySInt = { val o = Wire(new DummySInt(w)) o.bits := 0.U o } } // The Arithmetic typeclass which implements various arithmetic operations on custom datatypes abstract class Arithmetic[T <: Data] { implicit def cast(t: T): ArithmeticOps[T] } abstract class ArithmeticOps[T <: Data](self: T) { def (t: T): T def mac(m1: T, m2: T): T // Returns (m1 * m2 + self) def +(t: T): T def -(t: T): T def >>(u: UInt): T // This is a rounding shift! Rounds away from 0 def >(t: T): Bool def identity: T def withWidthOf(t: T): T def clippedToWidthOf(t: T): T // Like "withWidthOf", except that it saturates def relu: T def zero: T def minimum: T // Optional parameters, which only need to be defined if you want to enable various optimizations for transformers def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[T])] = None def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[T])] = None def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = None def mult_with_reciprocal[U <: Data](reciprocal: U) = self } object Arithmetic { implicit object UIntArithmetic extends Arithmetic[UInt] { override implicit def cast(self: UInt) = new ArithmeticOps(self) { override def (t: UInt) = self t override def mac(m1: UInt, m2: UInt) = m1 * m2 + self override def +(t: UInt) = self + t override def -(t: UInt) = self - t override def >>(u: UInt) = { // The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm // TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here? val point_five = Mux(u === 0.U, 0.U, self(u - 1.U)) val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U val ones_digit = self(u) val r = point_five & (zeros \| ones_digit) (self >> u).asUInt + r } override def >(t: UInt): Bool = self > t override def withWidthOf(t: UInt) = self.asTypeOf(t) override def clippedToWidthOf(t: UInt) = { val sat = ((1 << (t.getWidth-1))-1).U Mux(self > sat, sat, self)(t.getWidth-1, 0) } override def relu: UInt = self override def zero: UInt = 0.U override def identity: UInt = 1.U override def minimum: UInt = 0.U } } implicit object SIntArithmetic extends Arithmetic[SInt] { override implicit def cast(self: SInt) = new ArithmeticOps(self) { override def (t: SInt) = self t override def mac(m1: SInt, m2: SInt) = m1 * m2 + self override def +(t: SInt) = self + t override def -(t: SInt) = self - t override def >>(u: UInt) = { // The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm // TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here? val point_five = Mux(u === 0.U, 0.U, self(u - 1.U)) val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U val ones_digit = self(u) val r = (point_five & (zeros \| ones_digit)).asBool (self >> u).asSInt + Mux(r, 1.S, 0.S) } override def >(t: SInt): Bool = self > t override def withWidthOf(t: SInt) = { if (self.getWidth >= t.getWidth) self(t.getWidth-1, 0).asSInt else { val sign_bits = t.getWidth - self.getWidth val sign = self(self.getWidth-1) Cat(Cat(Seq.fill(sign_bits)(sign)), self).asTypeOf(t) } } override def clippedToWidthOf(t: SInt): SInt = { val maxsat = ((1 << (t.getWidth-1))-1).S val minsat = (-(1 << (t.getWidth-1))).S MuxCase(self, Seq((self > maxsat) -> maxsat, (self < minsat) -> minsat))(t.getWidth-1, 0).asSInt } override def relu: SInt = Mux(self >= 0.S, self, 0.S) override def zero: SInt = 0.S override def identity: SInt = 1.S override def minimum: SInt = (-(1 << (self.getWidth-1))).S override def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = { // TODO this uses a floating point divider, but we should use an integer divider instead val input = Wire(Decoupled(denom_t.cloneType)) val output = Wire(Decoupled(self.cloneType)) // We translate our integer to floating-point form so that we can use the hardfloat divider val expWidth = log2Up(self.getWidth) + 1 val sigWidth = self.getWidth def sin_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def uin_to_float(x: UInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := false.B in_to_rec_fn.io.in := x in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def float_to_in(x: UInt) = { val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth)) rec_fn_to_in.io.signedOut := true.B rec_fn_to_in.io.in := x rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag rec_fn_to_in.io.out.asSInt } val self_rec = sin_to_float(self) val denom_rec = uin_to_float(input.bits) // Instantiate the hardloat divider val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options)) input.ready := divider.io.inReady divider.io.inValid := input.valid divider.io.sqrtOp := false.B divider.io.a := self_rec divider.io.b := denom_rec divider.io.roundingMode := consts.round_minMag divider.io.detectTininess := consts.tininess_afterRounding output.valid := divider.io.outValid_div output.bits := float_to_in(divider.io.out) assert(!output.valid \|\| output.ready) Some((input, output)) } override def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = { // TODO this uses a floating point divider, but we should use an integer divider instead val input = Wire(Decoupled(UInt(0.W))) val output = Wire(Decoupled(self.cloneType)) input.bits := DontCare // We translate our integer to floating-point form so that we can use the hardfloat divider val expWidth = log2Up(self.getWidth) + 1 val sigWidth = self.getWidth def in_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def float_to_in(x: UInt) = { val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth)) rec_fn_to_in.io.signedOut := true.B rec_fn_to_in.io.in := x rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag rec_fn_to_in.io.out.asSInt } val self_rec = in_to_float(self) // Instantiate the hardloat sqrt val sqrter = Module(new DivSqrtRecFN_small(expWidth, sigWidth, 0)) input.ready := sqrter.io.inReady sqrter.io.inValid := input.valid sqrter.io.sqrtOp := true.B sqrter.io.a := self_rec sqrter.io.b := DontCare sqrter.io.roundingMode := consts.round_minMag sqrter.io.detectTininess := consts.tininess_afterRounding output.valid := sqrter.io.outValid_sqrt output.bits := float_to_in(sqrter.io.out) assert(!output.valid \|\| output.ready) Some((input, output)) } override def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = u match { case Float(expWidth, sigWidth) => val input = Wire(Decoupled(UInt(0.W))) val output = Wire(Decoupled(u.cloneType)) input.bits := DontCare // We translate our integer to floating-point form so that we can use the hardfloat divider def in_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } val self_rec = in_to_float(self) val one_rec = in_to_float(1.S) // Instantiate the hardloat divider val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options)) input.ready := divider.io.inReady divider.io.inValid := input.valid divider.io.sqrtOp := false.B divider.io.a := one_rec divider.io.b := self_rec divider.io.roundingMode := consts.round_near_even divider.io.detectTininess := consts.tininess_afterRounding output.valid := divider.io.outValid_div output.bits := fNFromRecFN(expWidth, sigWidth, divider.io.out).asTypeOf(u) assert(!output.valid \|\| output.ready) Some((input, output)) case _ => None } override def mult_with_reciprocal[U <: Data](reciprocal: U): SInt = reciprocal match { case recip @ Float(expWidth, sigWidth) => def in_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def float_to_in(x: UInt) = { val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth)) rec_fn_to_in.io.signedOut := true.B rec_fn_to_in.io.in := x rec_fn_to_in.io.roundingMode := consts.round_minMag rec_fn_to_in.io.out.asSInt } val self_rec = in_to_float(self) val reciprocal_rec = recFNFromFN(expWidth, sigWidth, recip.bits) // Instantiate the hardloat divider val muladder = Module(new MulRecFN(expWidth, sigWidth)) muladder.io.roundingMode := consts.round_near_even muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := self_rec muladder.io.b := reciprocal_rec float_to_in(muladder.io.out) case _ => self } } } implicit object FloatArithmetic extends Arithmetic[Float] { // TODO Floating point arithmetic currently switches between recoded and standard formats for every operation. However, it should stay in the recoded format as it travels through the systolic array override implicit def cast(self: Float): ArithmeticOps[Float] = new ArithmeticOps(self) { override def (t: Float): Float = { val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth)) t_resizer.io.in := t_rec t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag t_resizer.io.detectTininess := consts.tininess_afterRounding val t_rec_resized = t_resizer.io.out val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth)) muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := self_rec muladder.io.b := t_rec_resized val out = Wire(Float(self.expWidth, self.sigWidth)) out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) out } override def mac(m1: Float, m2: Float): Float = { // Recode all operands val m1_rec = recFNFromFN(m1.expWidth, m1.sigWidth, m1.bits) val m2_rec = recFNFromFN(m2.expWidth, m2.sigWidth, m2.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Resize m1 to self's width val m1_resizer = Module(new RecFNToRecFN(m1.expWidth, m1.sigWidth, self.expWidth, self.sigWidth)) m1_resizer.io.in := m1_rec m1_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag m1_resizer.io.detectTininess := consts.tininess_afterRounding val m1_rec_resized = m1_resizer.io.out // Resize m2 to self's width val m2_resizer = Module(new RecFNToRecFN(m2.expWidth, m2.sigWidth, self.expWidth, self.sigWidth)) m2_resizer.io.in := m2_rec m2_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag m2_resizer.io.detectTininess := consts.tininess_afterRounding val m2_rec_resized = m2_resizer.io.out // Perform multiply-add val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth)) muladder.io.op := 0.U muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := m1_rec_resized muladder.io.b := m2_rec_resized muladder.io.c := self_rec // Convert result to standard format // TODO remove these intermediate recodings val out = Wire(Float(self.expWidth, self.sigWidth)) out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) out } override def +(t: Float): Float = { require(self.getWidth >= t.getWidth) // This just makes it easier to write the resizing code // Recode all operands val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Generate 1 as a float val in_to_rec_fn = Module(new INToRecFN(1, self.expWidth, self.sigWidth)) in_to_rec_fn.io.signedIn := false.B in_to_rec_fn.io.in := 1.U in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding val one_rec = in_to_rec_fn.io.out // Resize t val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth)) t_resizer.io.in := t_rec t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag t_resizer.io.detectTininess := consts.tininess_afterRounding val t_rec_resized = t_resizer.io.out // Perform addition val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth)) muladder.io.op := 0.U muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := t_rec_resized muladder.io.b := one_rec muladder.io.c := self_rec val result = Wire(Float(self.expWidth, self.sigWidth)) result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) result } override def -(t: Float): Float = { val t_sgn = t.bits(t.getWidth-1) val neg_t = Cat(~t_sgn, t.bits(t.getWidth-2,0)).asTypeOf(t) self + neg_t } override def >>(u: UInt): Float = { // Recode self val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Get 2^(-u) as a recoded float val shift_exp = Wire(UInt(self.expWidth.W)) shift_exp := self.bias.U - u val shift_fn = Cat(0.U(1.W), shift_exp, 0.U((self.sigWidth-1).W)) val shift_rec = recFNFromFN(self.expWidth, self.sigWidth, shift_fn) assert(shift_exp =/= 0.U, "scaling by denormalized numbers is not currently supported") // Multiply self and 2^(-u) val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth)) muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := self_rec muladder.io.b := shift_rec val result = Wire(Float(self.expWidth, self.sigWidth)) result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) result } override def >(t: Float): Bool = { // Recode all operands val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Resize t to self's width val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth)) t_resizer.io.in := t_rec t_resizer.io.roundingMode := consts.round_near_even t_resizer.io.detectTininess := consts.tininess_afterRounding val t_rec_resized = t_resizer.io.out val comparator = Module(new CompareRecFN(self.expWidth, self.sigWidth)) comparator.io.a := self_rec comparator.io.b := t_rec_resized comparator.io.signaling := false.B comparator.io.gt } override def withWidthOf(t: Float): Float = { val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth)) resizer.io.in := self_rec resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag resizer.io.detectTininess := consts.tininess_afterRounding val result = Wire(Float(t.expWidth, t.sigWidth)) result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out) result } override def clippedToWidthOf(t: Float): Float = { // TODO check for overflow. Right now, we just assume that overflow doesn't happen val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth)) resizer.io.in := self_rec resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag resizer.io.detectTininess := consts.tininess_afterRounding val result = Wire(Float(t.expWidth, t.sigWidth)) result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out) result } override def relu: Float = { val raw = rawFloatFromFN(self.expWidth, self.sigWidth, self.bits) val result = Wire(Float(self.expWidth, self.sigWidth)) result.bits := Mux(!raw.isZero && raw.sign, 0.U, self.bits) result } override def zero: Float = 0.U.asTypeOf(self) override def identity: Float = Cat(0.U(2.W), ~(0.U((self.expWidth-1).W)), 0.U((self.sigWidth-1).W)).asTypeOf(self) override def minimum: Float = Cat(1.U, ~(0.U(self.expWidth.W)), 0.U((self.sigWidth-1).W)).asTypeOf(self) } } implicit object DummySIntArithmetic extends Arithmetic[DummySInt] { override implicit def cast(self: DummySInt) = new ArithmeticOps(self) { override def (t: DummySInt) = self.dontCare override def mac(m1: DummySInt, m2: DummySInt) = self.dontCare override def +(t: DummySInt) = self.dontCare override def -(t: DummySInt) = self.dontCare override def >>(t: UInt) = self.dontCare override def >(t: DummySInt): Bool = false.B override def identity = self.dontCare override def withWidthOf(t: DummySInt) = self.dontCare override def clippedToWidthOf(t: DummySInt) = self.dontCare override def relu = self.dontCare override def zero = self.dontCare override def minimum: DummySInt = self.dontCare } } }	module PE_272( // @[PE.scala:31:7] input clock, // @[PE.scala:31:7] input reset, // @[PE.scala:31:7] input [7:0] io_in_a, // @[PE.scala:35:14] input [19:0] io_in_b, // @[PE.scala:35:14] input [19:0] io_in_d, // @[PE.scala:35:14] output [7:0] io_out_a, // @[PE.scala:35:14] output [19:0] io_out_b, // @[PE.scala:35:14] output [19:0] io_out_c, // @[PE.scala:35:14] input io_in_control_dataflow, // @[PE.scala:35:14] input io_in_control_propagate, // @[PE.scala:35:14] input [4:0] io_in_control_shift, // @[PE.scala:35:14] output io_out_control_dataflow, // @[PE.scala:35:14] output io_out_control_propagate, // @[PE.scala:35:14] output [4:0] io_out_control_shift, // @[PE.scala:35:14] input [2:0] io_in_id, // @[PE.scala:35:14] output [2:0] io_out_id, // @[PE.scala:35:14] input io_in_last, // @[PE.scala:35:14] output io_out_last, // @[PE.scala:35:14] input io_in_valid, // @[PE.scala:35:14] output io_out_valid // @[PE.scala:35:14] ); wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:31:7] wire [19:0] io_in_b_0 = io_in_b; // @[PE.scala:31:7] wire [19:0] io_in_d_0 = io_in_d; // @[PE.scala:31:7] wire io_in_control_dataflow_0 = io_in_control_dataflow; // @[PE.scala:31:7] wire io_in_control_propagate_0 = io_in_control_propagate; // @[PE.scala:31:7] wire [4:0] io_in_control_shift_0 = io_in_control_shift; // @[PE.scala:31:7] wire [2:0] io_in_id_0 = io_in_id; // @[PE.scala:31:7] wire io_in_last_0 = io_in_last; // @[PE.scala:31:7] wire io_in_valid_0 = io_in_valid; // @[PE.scala:31:7] wire io_bad_dataflow = 1'h0; // @[PE.scala:31:7] wire _io_out_c_T_5 = 1'h0; // @[Arithmetic.scala:125:33] wire _io_out_c_T_6 = 1'h0; // @[Arithmetic.scala:125:60] wire _io_out_c_T_16 = 1'h0; // @[Arithmetic.scala:125:33] wire _io_out_c_T_17 = 1'h0; // @[Arithmetic.scala:125:60] wire [7:0] io_out_a_0 = io_in_a_0; // @[PE.scala:31:7] wire [19:0] _mac_unit_io_in_b_T = io_in_b_0; // @[PE.scala:31:7, :106:37] wire [19:0] _mac_unit_io_in_b_T_2 = io_in_b_0; // @[PE.scala:31:7, :113:37] wire [19:0] _mac_unit_io_in_b_T_8 = io_in_b_0; // @[PE.scala:31:7, :137:35] wire io_out_control_dataflow_0 = io_in_control_dataflow_0; // @[PE.scala:31:7] wire io_out_control_propagate_0 = io_in_control_propagate_0; // @[PE.scala:31:7] wire [4:0] io_out_control_shift_0 = io_in_control_shift_0; // @[PE.scala:31:7] wire [2:0] io_out_id_0 = io_in_id_0; // @[PE.scala:31:7] wire io_out_last_0 = io_in_last_0; // @[PE.scala:31:7] wire io_out_valid_0 = io_in_valid_0; // @[PE.scala:31:7] wire [19:0] io_out_b_0; // @[PE.scala:31:7] wire [19:0] io_out_c_0; // @[PE.scala:31:7] reg [7:0] c1; // @[PE.scala:70:15] wire [7:0] _io_out_c_zeros_T_1 = c1; // @[PE.scala:70:15] wire [7:0] _mac_unit_io_in_b_T_6 = c1; // @[PE.scala:70:15, :127:38] reg [7:0] c2; // @[PE.scala:71:15] wire [7:0] _io_out_c_zeros_T_10 = c2; // @[PE.scala:71:15] wire [7:0] _mac_unit_io_in_b_T_4 = c2; // @[PE.scala:71:15, :121:38] reg last_s; // @[PE.scala:89:25] wire flip = last_s != io_in_control_propagate_0; // @[PE.scala:31:7, :89:25, :90:21] wire [4:0] shift_offset = flip ? io_in_control_shift_0 : 5'h0; // @[PE.scala:31:7, :90:21, :91:25] wire _GEN = shift_offset == 5'h0; // @[PE.scala:91:25] wire _io_out_c_point_five_T; // @[Arithmetic.scala:101:32] assign _io_out_c_point_five_T = _GEN; // @[Arithmetic.scala:101:32] wire _io_out_c_point_five_T_5; // @[Arithmetic.scala:101:32] assign _io_out_c_point_five_T_5 = _GEN; // @[Arithmetic.scala:101:32] wire [5:0] _GEN_0 = {1'h0, shift_offset} - 6'h1; // @[PE.scala:91:25] wire [5:0] _io_out_c_point_five_T_1; // @[Arithmetic.scala:101:53] assign _io_out_c_point_five_T_1 = _GEN_0; // @[Arithmetic.scala:101:53] wire [5:0] _io_out_c_zeros_T_2; // @[Arithmetic.scala:102:66] assign _io_out_c_zeros_T_2 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66] wire [5:0] _io_out_c_point_five_T_6; // @[Arithmetic.scala:101:53] assign _io_out_c_point_five_T_6 = _GEN_0; // @[Arithmetic.scala:101:53] wire [5:0] _io_out_c_zeros_T_11; // @[Arithmetic.scala:102:66] assign _io_out_c_zeros_T_11 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66] wire [4:0] _io_out_c_point_five_T_2 = _io_out_c_point_five_T_1[4:0]; // @[Arithmetic.scala:101:53] wire [7:0] _io_out_c_point_five_T_3 = $signed($signed(c1) >>> _io_out_c_point_five_T_2); // @[PE.scala:70:15] wire _io_out_c_point_five_T_4 = _io_out_c_point_five_T_3[0]; // @[Arithmetic.scala:101:50] wire io_out_c_point_five = ~_io_out_c_point_five_T & _io_out_c_point_five_T_4; // @[Arithmetic.scala:101:{29,32,50}] wire _GEN_1 = shift_offset < 5'h2; // @[PE.scala:91:25] wire _io_out_c_zeros_T; // @[Arithmetic.scala:102:27] assign _io_out_c_zeros_T = _GEN_1; // @[Arithmetic.scala:102:27] wire _io_out_c_zeros_T_9; // @[Arithmetic.scala:102:27] assign _io_out_c_zeros_T_9 = _GEN_1; // @[Arithmetic.scala:102:27] wire [4:0] _io_out_c_zeros_T_3 = _io_out_c_zeros_T_2[4:0]; // @[Arithmetic.scala:102:66] wire [31:0] _io_out_c_zeros_T_4 = 32'h1 << _io_out_c_zeros_T_3; // @[Arithmetic.scala:102:{60,66}] wire [32:0] _io_out_c_zeros_T_5 = {1'h0, _io_out_c_zeros_T_4} - 33'h1; // @[Arithmetic.scala:102:{60,81}] wire [31:0] _io_out_c_zeros_T_6 = _io_out_c_zeros_T_5[31:0]; // @[Arithmetic.scala:102:81] wire [31:0] _io_out_c_zeros_T_7 = {24'h0, _io_out_c_zeros_T_6[7:0] & _io_out_c_zeros_T_1}; // @[Arithmetic.scala:102:{45,52,81}] wire [31:0] _io_out_c_zeros_T_8 = _io_out_c_zeros_T ? 32'h0 : _io_out_c_zeros_T_7; // @[Arithmetic.scala:102:{24,27,52}] wire io_out_c_zeros = \|_io_out_c_zeros_T_8; // @[Arithmetic.scala:102:{24,89}] wire [7:0] _GEN_2 = {3'h0, shift_offset}; // @[PE.scala:91:25] wire [7:0] _GEN_3 = $signed($signed(c1) >>> _GEN_2); // @[PE.scala:70:15] wire [7:0] _io_out_c_ones_digit_T; // @[Arithmetic.scala:103:30] assign _io_out_c_ones_digit_T = _GEN_3; // @[Arithmetic.scala:103:30] wire [7:0] _io_out_c_T; // @[Arithmetic.scala:107:15] assign _io_out_c_T = _GEN_3; // @[Arithmetic.scala:103:30, :107:15] wire io_out_c_ones_digit = _io_out_c_ones_digit_T[0]; // @[Arithmetic.scala:103:30] wire _io_out_c_r_T = io_out_c_zeros \| io_out_c_ones_digit; // @[Arithmetic.scala:102:89, :103:30, :105:38] wire _io_out_c_r_T_1 = io_out_c_point_five & _io_out_c_r_T; // @[Arithmetic.scala:101:29, :105:{29,38}] wire io_out_c_r = _io_out_c_r_T_1; // @[Arithmetic.scala:105:{29,53}] wire [1:0] _io_out_c_T_1 = {1'h0, io_out_c_r}; // @[Arithmetic.scala:105:53, :107:33] wire [8:0] _io_out_c_T_2 = {_io_out_c_T[7], _io_out_c_T} + {{7{_io_out_c_T_1[1]}}, _io_out_c_T_1}; // @[Arithmetic.scala:107:{15,28,33}] wire [7:0] _io_out_c_T_3 = _io_out_c_T_2[7:0]; // @[Arithmetic.scala:107:28] wire [7:0] _io_out_c_T_4 = _io_out_c_T_3; // @[Arithmetic.scala:107:28] wire [19:0] _io_out_c_T_7 = {{12{_io_out_c_T_4[7]}}, _io_out_c_T_4}; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_8 = _io_out_c_T_7; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_9 = _io_out_c_T_8; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_10 = _io_out_c_T_9; // @[Arithmetic.scala:125:{81,99}] wire [19:0] _mac_unit_io_in_b_T_1 = _mac_unit_io_in_b_T; // @[PE.scala:106:37] wire [7:0] _mac_unit_io_in_b_WIRE = _mac_unit_io_in_b_T_1[7:0]; // @[PE.scala:106:37] wire [7:0] _c1_T = io_in_d_0[7:0]; // @[PE.scala:31:7] wire [7:0] _c2_T = io_in_d_0[7:0]; // @[PE.scala:31:7] wire [7:0] _c1_T_1 = _c1_T; // @[Arithmetic.scala:114:{15,33}] wire [4:0] _io_out_c_point_five_T_7 = _io_out_c_point_five_T_6[4:0]; // @[Arithmetic.scala:101:53] wire [7:0] _io_out_c_point_five_T_8 = $signed($signed(c2) >>> _io_out_c_point_five_T_7); // @[PE.scala:71:15] wire _io_out_c_point_five_T_9 = _io_out_c_point_five_T_8[0]; // @[Arithmetic.scala:101:50] wire io_out_c_point_five_1 = ~_io_out_c_point_five_T_5 & _io_out_c_point_five_T_9; // @[Arithmetic.scala:101:{29,32,50}] wire [4:0] _io_out_c_zeros_T_12 = _io_out_c_zeros_T_11[4:0]; // @[Arithmetic.scala:102:66] wire [31:0] _io_out_c_zeros_T_13 = 32'h1 << _io_out_c_zeros_T_12; // @[Arithmetic.scala:102:{60,66}] wire [32:0] _io_out_c_zeros_T_14 = {1'h0, _io_out_c_zeros_T_13} - 33'h1; // @[Arithmetic.scala:102:{60,81}] wire [31:0] _io_out_c_zeros_T_15 = _io_out_c_zeros_T_14[31:0]; // @[Arithmetic.scala:102:81] wire [31:0] _io_out_c_zeros_T_16 = {24'h0, _io_out_c_zeros_T_15[7:0] & _io_out_c_zeros_T_10}; // @[Arithmetic.scala:102:{45,52,81}] wire [31:0] _io_out_c_zeros_T_17 = _io_out_c_zeros_T_9 ? 32'h0 : _io_out_c_zeros_T_16; // @[Arithmetic.scala:102:{24,27,52}] wire io_out_c_zeros_1 = \|_io_out_c_zeros_T_17; // @[Arithmetic.scala:102:{24,89}] wire [7:0] _GEN_4 = $signed($signed(c2) >>> _GEN_2); // @[PE.scala:71:15] wire [7:0] _io_out_c_ones_digit_T_1; // @[Arithmetic.scala:103:30] assign _io_out_c_ones_digit_T_1 = _GEN_4; // @[Arithmetic.scala:103:30] wire [7:0] _io_out_c_T_11; // @[Arithmetic.scala:107:15] assign _io_out_c_T_11 = _GEN_4; // @[Arithmetic.scala:103:30, :107:15] wire io_out_c_ones_digit_1 = _io_out_c_ones_digit_T_1[0]; // @[Arithmetic.scala:103:30] wire _io_out_c_r_T_2 = io_out_c_zeros_1 \| io_out_c_ones_digit_1; // @[Arithmetic.scala:102:89, :103:30, :105:38] wire _io_out_c_r_T_3 = io_out_c_point_five_1 & _io_out_c_r_T_2; // @[Arithmetic.scala:101:29, :105:{29,38}] wire io_out_c_r_1 = _io_out_c_r_T_3; // @[Arithmetic.scala:105:{29,53}] wire [1:0] _io_out_c_T_12 = {1'h0, io_out_c_r_1}; // @[Arithmetic.scala:105:53, :107:33] wire [8:0] _io_out_c_T_13 = {_io_out_c_T_11[7], _io_out_c_T_11} + {{7{_io_out_c_T_12[1]}}, _io_out_c_T_12}; // @[Arithmetic.scala:107:{15,28,33}] wire [7:0] _io_out_c_T_14 = _io_out_c_T_13[7:0]; // @[Arithmetic.scala:107:28] wire [7:0] _io_out_c_T_15 = _io_out_c_T_14; // @[Arithmetic.scala:107:28] wire [19:0] _io_out_c_T_18 = {{12{_io_out_c_T_15[7]}}, _io_out_c_T_15}; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_19 = _io_out_c_T_18; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_20 = _io_out_c_T_19; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_21 = _io_out_c_T_20; // @[Arithmetic.scala:125:{81,99}] wire [19:0] _mac_unit_io_in_b_T_3 = _mac_unit_io_in_b_T_2; // @[PE.scala:113:37] wire [7:0] _mac_unit_io_in_b_WIRE_1 = _mac_unit_io_in_b_T_3[7:0]; // @[PE.scala:113:37] wire [7:0] _c2_T_1 = _c2_T; // @[Arithmetic.scala:114:{15,33}] wire [7:0] _mac_unit_io_in_b_T_5; // @[PE.scala:121:38] assign _mac_unit_io_in_b_T_5 = _mac_unit_io_in_b_T_4; // @[PE.scala:121:38] wire [7:0] _mac_unit_io_in_b_WIRE_2 = _mac_unit_io_in_b_T_5; // @[PE.scala:121:38] assign io_out_c_0 = io_in_control_propagate_0 ? {{12{c1[7]}}, c1} : {{12{c2[7]}}, c2}; // @[PE.scala:31:7, :70:15, :71:15, :119:30, :120:16, :126:16] wire [7:0] _mac_unit_io_in_b_T_7; // @[PE.scala:127:38] assign _mac_unit_io_in_b_T_7 = _mac_unit_io_in_b_T_6; // @[PE.scala:127:38] wire [7:0] _mac_unit_io_in_b_WIRE_3 = _mac_unit_io_in_b_T_7; // @[PE.scala:127:38] wire [19:0] _mac_unit_io_in_b_T_9 = _mac_unit_io_in_b_T_8; // @[PE.scala:137:35] wire [7:0] _mac_unit_io_in_b_WIRE_4 = _mac_unit_io_in_b_T_9[7:0]; // @[PE.scala:137:35] always @(posedge clock) begin // @[PE.scala:31:7] if (io_in_valid_0 & io_in_control_propagate_0) // @[PE.scala:31:7, :102:95, :141:17, :142:8] c1 <= io_in_d_0[7:0]; // @[PE.scala:31:7, :70:15] if (~(~io_in_valid_0 \| io_in_control_propagate_0)) // @[PE.scala:31:7, :71:15, :102:95, :119:30, :130:10, :141:{9,17}, :143:8] c2 <= io_in_d_0[7:0]; // @[PE.scala:31:7, :71:15] if (io_in_valid_0) // @[PE.scala:31:7] last_s <= io_in_control_propagate_0; // @[PE.scala:31:7, :89:25] always @(posedge) MacUnit_16 mac_unit ( // @[PE.scala:64:24] .clock (clock), .reset (reset), .io_in_a (io_in_a_0), // @[PE.scala:31:7] .io_in_b (io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE_2 : _mac_unit_io_in_b_WIRE_3), // @[PE.scala:31:7, :119:30, :121:{24,38}, :127:{24,38}] .io_in_c (io_in_b_0), // @[PE.scala:31:7] .io_out_d (io_out_b_0) ); // @[PE.scala:64:24] assign io_out_a = io_out_a_0; // @[PE.scala:31:7] assign io_out_b = io_out_b_0; // @[PE.scala:31:7] assign io_out_c = io_out_c_0; // @[PE.scala:31:7] assign io_out_control_dataflow = io_out_control_dataflow_0; // @[PE.scala:31:7] assign io_out_control_propagate = io_out_control_propagate_0; // @[PE.scala:31:7] assign io_out_control_shift = io_out_control_shift_0; // @[PE.scala:31:7] assign io_out_id = io_out_id_0; // @[PE.scala:31:7] assign io_out_last = io_out_last_0; // @[PE.scala:31:7] assign io_out_valid = io_out_valid_0; // @[PE.scala:31:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File ShiftReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ // Similar to the Chisel ShiftRegister but allows the user to suggest a // name to the registers that get instantiated, and // to provide a reset value. object ShiftRegInit { def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T = (0 until n).foldRight(in) { case (i, next) => { val r = RegNext(next, init) name.foreach { na => r.suggestName(s"${na}_${i}") } r } } } /** These wrap behavioral * shift registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * The different types vary in their reset behavior: * AsyncResetShiftReg -- Asynchronously reset register array * A W(width) x D(depth) sized array is constructed from D instantiations of a * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg, * but only used for timing applications / abstract class AbstractPipelineReg(w: Int = 1) extends Module { val io = IO(new Bundle { val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) } ) } object AbstractPipelineReg { def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = { val chain = Module(gen) name.foreach{ chain.suggestName(_) } chain.io.d := in.asUInt chain.io.q.asTypeOf(in) } } class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) { require(depth > 0, "Depth must be greater than 0.") override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}" val chain = List.tabulate(depth) { i => Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}") } chain.last.io.d := io.d chain.last.io.en := true.B (chain.init zip chain.tail).foreach { case (sink, source) => sink.io.d := source.io.q sink.io.en := true.B } io.q := chain.head.io.q } object AsyncResetShiftReg { def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name) def apply [T <: Data](in: T, depth: Int, name: Option[String]): T = apply(in, depth, 0, name) def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T = apply(in, depth, init.litValue.toInt, name) def apply [T <: Data](in: T, depth: Int, init: T): T = apply (in, depth, init.litValue.toInt, None) } File SynchronizerReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util.{RegEnable, Cat} /* These wrap behavioral * shift and next registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * * These are built up of ResetSynchronizerPrimitiveShiftReg, intended to be replaced by the integrator's metastable flops chains or replaced * at this level if they have a multi-bit wide synchronizer primitive. * The different types vary in their reset behavior: * NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin * AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep * 1-bit-wide shift registers. * SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg * * [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference. * * ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross * Clock Domains. */ object SynchronizerResetType extends Enumeration { val NonSync, Inferred, Sync, Async = Value } // Note: this should not be used directly. // Use the companion object to generate this with the correct reset type mixin. private class SynchronizerPrimitiveShiftReg( sync: Int, init: Boolean, resetType: SynchronizerResetType.Value) extends AbstractPipelineReg(1) { val initInt = if (init) 1 else 0 val initPostfix = resetType match { case SynchronizerResetType.NonSync => "" case _ => s"_i${initInt}" } override def desiredName = s"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}" val chain = List.tabulate(sync) { i => val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B) reg.suggestName(s"sync_$i") } chain.last := io.d.asBool (chain.init zip chain.tail).foreach { case (sink, source) => sink := source } io.q := chain.head.asUInt } private object SynchronizerPrimitiveShiftReg { def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = { val gen: () => SynchronizerPrimitiveShiftReg = resetType match { case SynchronizerResetType.NonSync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) case SynchronizerResetType.Async => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset case SynchronizerResetType.Sync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset case SynchronizerResetType.Inferred => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) } AbstractPipelineReg(gen(), in) } } // Note: This module may end up with a non-AsyncReset type reset. // But the Primitives within will always have AsyncReset type. class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asAsyncReset){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async) } } io.q := Cat(output.reverse) } object AsyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } // Note: This module may end up with a non-Bool type reset. // But the Primitives within will always have Bool reset type. @deprecated("SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.", "rocket-chip 1.2") class SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asBool){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync) } } io.q := Cat(output.reverse) } object SyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred) } io.q := Cat(output.reverse) } object ResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}" val output = Seq.tabulate(w) { i => SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync) } io.q := Cat(output.reverse) } object SynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, None) def apply [T <: Data](in: T): T = apply (in, 3, None) } class ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module { override def desiredName = s"ClockCrossingReg_w${w}" val io = IO(new Bundle{ val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) val en = Input(Bool()) }) val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en) io.q := cdc_reg } object ClockCrossingReg { def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = { val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit)) name.foreach{ cdc_reg.suggestName(_) } cdc_reg.io.d := in.asUInt cdc_reg.io.en := en cdc_reg.io.q.asTypeOf(in) } }	module AsyncResetSynchronizerShiftReg_w1_d3_i0_75( // @[SynchronizerReg.scala:80:7] input clock, // @[SynchronizerReg.scala:80:7] input reset, // @[SynchronizerReg.scala:80:7] output io_q // @[ShiftReg.scala:36:14] ); wire _output_T = reset; // @[SynchronizerReg.scala:86:21] wire io_d = 1'h1; // @[SynchronizerReg.scala:80:7, :87:41] wire _output_T_1 = 1'h1; // @[SynchronizerReg.scala:80:7, :87:41] wire output_0; // @[ShiftReg.scala:48:24] wire io_q_0; // @[SynchronizerReg.scala:80:7] assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_119 output_chain ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T), // @[SynchronizerReg.scala:86:21] .io_q (output_0) ); // @[ShiftReg.scala:45:23] assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File ShiftReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ // Similar to the Chisel ShiftRegister but allows the user to suggest a // name to the registers that get instantiated, and // to provide a reset value. object ShiftRegInit { def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T = (0 until n).foldRight(in) { case (i, next) => { val r = RegNext(next, init) name.foreach { na => r.suggestName(s"${na}_${i}") } r } } } /** These wrap behavioral * shift registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * The different types vary in their reset behavior: * AsyncResetShiftReg -- Asynchronously reset register array * A W(width) x D(depth) sized array is constructed from D instantiations of a * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg, * but only used for timing applications */ abstract class AbstractPipelineReg(w: Int = 1) extends Module { val io = IO(new Bundle { val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) } ) } object AbstractPipelineReg { def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = { val chain = Module(gen) name.foreach{ chain.suggestName(_) } chain.io.d := in.asUInt chain.io.q.asTypeOf(in) } } class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) { require(depth > 0, "Depth must be greater than 0.") override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}" val chain = List.tabulate(depth) { i => Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}") } chain.last.io.d := io.d chain.last.io.en := true.B (chain.init zip chain.tail).foreach { case (sink, source) => sink.io.d := source.io.q sink.io.en := true.B } io.q := chain.head.io.q } object AsyncResetShiftReg { def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name) def apply [T <: Data](in: T, depth: Int, name: Option[String]): T = apply(in, depth, 0, name) def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T = apply(in, depth, init.litValue.toInt, name) def apply [T <: Data](in: T, depth: Int, init: T): T = apply (in, depth, init.litValue.toInt, None) } File AsyncQueue.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ case class AsyncQueueParams( depth: Int = 8, sync: Int = 3, safe: Boolean = true, // If safe is true, then effort is made to resynchronize the crossing indices when either side is reset. // This makes it safe/possible to reset one side of the crossing (but not the other) when the queue is empty. narrow: Boolean = false) // If narrow is true then the read mux is moved to the source side of the crossing. // This reduces the number of level shifters in the case where the clock crossing is also a voltage crossing, // at the expense of a combinational path from the sink to the source and back to the sink. { require (depth > 0 && isPow2(depth)) require (sync >= 2) val bits = log2Ceil(depth) val wires = if (narrow) 1 else depth } object AsyncQueueParams { // When there is only one entry, we don't need narrow. def singleton(sync: Int = 3, safe: Boolean = true) = AsyncQueueParams(1, sync, safe, false) } class AsyncBundleSafety extends Bundle { val ridx_valid = Input (Bool()) val widx_valid = Output(Bool()) val source_reset_n = Output(Bool()) val sink_reset_n = Input (Bool()) } class AsyncBundle[T <: Data](private val gen: T, val params: AsyncQueueParams = AsyncQueueParams()) extends Bundle { // Data-path synchronization val mem = Output(Vec(params.wires, gen)) val ridx = Input (UInt((params.bits+1).W)) val widx = Output(UInt((params.bits+1).W)) val index = params.narrow.option(Input(UInt(params.bits.W))) // Signals used to self-stabilize a safe AsyncQueue val safe = params.safe.option(new AsyncBundleSafety) } object GrayCounter { def apply(bits: Int, increment: Bool = true.B, clear: Bool = false.B, name: String = "binary"): UInt = { val incremented = Wire(UInt(bits.W)) val binary = RegNext(next=incremented, init=0.U).suggestName(name) incremented := Mux(clear, 0.U, binary + increment.asUInt) incremented ^ (incremented >> 1) } } class AsyncValidSync(sync: Int, desc: String) extends RawModule { val io = IO(new Bundle { val in = Input(Bool()) val out = Output(Bool()) }) val clock = IO(Input(Clock())) val reset = IO(Input(AsyncReset())) withClockAndReset(clock, reset){ io.out := AsyncResetSynchronizerShiftReg(io.in, sync, Some(desc)) } } class AsyncQueueSource[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module { override def desiredName = s"AsyncQueueSource_${gen.typeName}" val io = IO(new Bundle { // These come from the source domain val enq = Flipped(Decoupled(gen)) // These cross to the sink clock domain val async = new AsyncBundle(gen, params) }) val bits = params.bits val sink_ready = WireInit(true.B) val mem = Reg(Vec(params.depth, gen)) // This does NOT need to be reset at all. val widx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.enq.fire, !sink_ready, "widx_bin")) val ridx = AsyncResetSynchronizerShiftReg(io.async.ridx, params.sync, Some("ridx_gray")) val ready = sink_ready && widx =/= (ridx ^ (params.depth \| params.depth >> 1).U) val index = if (bits == 0) 0.U else io.async.widx(bits-1, 0) ^ (io.async.widx(bits, bits) << (bits-1)) when (io.enq.fire) { mem(index) := io.enq.bits } val ready_reg = withReset(reset.asAsyncReset)(RegNext(next=ready, init=false.B).suggestName("ready_reg")) io.enq.ready := ready_reg && sink_ready val widx_reg = withReset(reset.asAsyncReset)(RegNext(next=widx, init=0.U).suggestName("widx_gray")) io.async.widx := widx_reg io.async.index match { case Some(index) => io.async.mem(0) := mem(index) case None => io.async.mem := mem } io.async.safe.foreach { sio => val source_valid_0 = Module(new AsyncValidSync(params.sync, "source_valid_0")) val source_valid_1 = Module(new AsyncValidSync(params.sync, "source_valid_1")) val sink_extend = Module(new AsyncValidSync(params.sync, "sink_extend")) val sink_valid = Module(new AsyncValidSync(params.sync, "sink_valid")) source_valid_0.reset := (reset.asBool \|\| !sio.sink_reset_n).asAsyncReset source_valid_1.reset := (reset.asBool \|\| !sio.sink_reset_n).asAsyncReset sink_extend .reset := (reset.asBool \|\| !sio.sink_reset_n).asAsyncReset sink_valid .reset := reset.asAsyncReset source_valid_0.clock := clock source_valid_1.clock := clock sink_extend .clock := clock sink_valid .clock := clock source_valid_0.io.in := true.B source_valid_1.io.in := source_valid_0.io.out sio.widx_valid := source_valid_1.io.out sink_extend.io.in := sio.ridx_valid sink_valid.io.in := sink_extend.io.out sink_ready := sink_valid.io.out sio.source_reset_n := !reset.asBool // Assert that if there is stuff in the queue, then reset cannot happen // Impossible to write because dequeue can occur on the receiving side, // then reset allowed to happen, but write side cannot know that dequeue // occurred. // TODO: write some sort of sanity check assertion for users // that denote don't reset when there is activity // assert (!(reset \|\| !sio.sink_reset_n) \|\| !io.enq.valid, "Enqueue while sink is reset and AsyncQueueSource is unprotected") // assert (!reset_rise \|\| prev_idx_match.asBool, "Sink reset while AsyncQueueSource not empty") } } class AsyncQueueSink[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module { override def desiredName = s"AsyncQueueSink_${gen.typeName}" val io = IO(new Bundle { // These come from the sink domain val deq = Decoupled(gen) // These cross to the source clock domain val async = Flipped(new AsyncBundle(gen, params)) }) val bits = params.bits val source_ready = WireInit(true.B) val ridx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.deq.fire, !source_ready, "ridx_bin")) val widx = AsyncResetSynchronizerShiftReg(io.async.widx, params.sync, Some("widx_gray")) val valid = source_ready && ridx =/= widx // The mux is safe because timing analysis ensures ridx has reached the register // On an ASIC, changes to the unread location cannot affect the selected value // On an FPGA, only one input changes at a time => mem updates don't cause glitches // The register only latches when the selected valued is not being written val index = if (bits == 0) 0.U else ridx(bits-1, 0) ^ (ridx(bits, bits) << (bits-1)) io.async.index.foreach { _ := index } // This register does not NEED to be reset, as its contents will not // be considered unless the asynchronously reset deq valid register is set. // It is possible that bits latches when the source domain is reset / has power cut // This is safe, because isolation gates brought mem low before the zeroed widx reached us val deq_bits_nxt = io.async.mem(if (params.narrow) 0.U else index) io.deq.bits := ClockCrossingReg(deq_bits_nxt, en = valid, doInit = false, name = Some("deq_bits_reg")) val valid_reg = withReset(reset.asAsyncReset)(RegNext(next=valid, init=false.B).suggestName("valid_reg")) io.deq.valid := valid_reg && source_ready val ridx_reg = withReset(reset.asAsyncReset)(RegNext(next=ridx, init=0.U).suggestName("ridx_gray")) io.async.ridx := ridx_reg io.async.safe.foreach { sio => val sink_valid_0 = Module(new AsyncValidSync(params.sync, "sink_valid_0")) val sink_valid_1 = Module(new AsyncValidSync(params.sync, "sink_valid_1")) val source_extend = Module(new AsyncValidSync(params.sync, "source_extend")) val source_valid = Module(new AsyncValidSync(params.sync, "source_valid")) sink_valid_0 .reset := (reset.asBool \|\| !sio.source_reset_n).asAsyncReset sink_valid_1 .reset := (reset.asBool \|\| !sio.source_reset_n).asAsyncReset source_extend.reset := (reset.asBool \|\| !sio.source_reset_n).asAsyncReset source_valid .reset := reset.asAsyncReset sink_valid_0 .clock := clock sink_valid_1 .clock := clock source_extend.clock := clock source_valid .clock := clock sink_valid_0.io.in := true.B sink_valid_1.io.in := sink_valid_0.io.out sio.ridx_valid := sink_valid_1.io.out source_extend.io.in := sio.widx_valid source_valid.io.in := source_extend.io.out source_ready := source_valid.io.out sio.sink_reset_n := !reset.asBool // TODO: write some sort of sanity check assertion for users // that denote don't reset when there is activity // // val reset_and_extend = !source_ready \|\| !sio.source_reset_n \|\| reset.asBool // val reset_and_extend_prev = RegNext(reset_and_extend, true.B) // val reset_rise = !reset_and_extend_prev && reset_and_extend // val prev_idx_match = AsyncResetReg(updateData=(io.async.widx===io.async.ridx), resetData=0) // assert (!reset_rise \|\| prev_idx_match.asBool, "Source reset while AsyncQueueSink not empty") } } object FromAsyncBundle { // Sometimes it makes sense for the sink to have different sync than the source def apply[T <: Data](x: AsyncBundle[T]): DecoupledIO[T] = apply(x, x.params.sync) def apply[T <: Data](x: AsyncBundle[T], sync: Int): DecoupledIO[T] = { val sink = Module(new AsyncQueueSink(chiselTypeOf(x.mem(0)), x.params.copy(sync = sync))) sink.io.async <> x sink.io.deq } } object ToAsyncBundle { def apply[T <: Data](x: ReadyValidIO[T], params: AsyncQueueParams = AsyncQueueParams()): AsyncBundle[T] = { val source = Module(new AsyncQueueSource(chiselTypeOf(x.bits), params)) source.io.enq <> x source.io.async } } class AsyncQueue[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Crossing[T] { val io = IO(new CrossingIO(gen)) val source = withClockAndReset(io.enq_clock, io.enq_reset) { Module(new AsyncQueueSource(gen, params)) } val sink = withClockAndReset(io.deq_clock, io.deq_reset) { Module(new AsyncQueueSink (gen, params)) } source.io.enq <> io.enq io.deq <> sink.io.deq sink.io.async <> source.io.async }	module AsyncValidSync_166( // @[AsyncQueue.scala:58:7] input io_in, // @[AsyncQueue.scala:59:14] output io_out, // @[AsyncQueue.scala:59:14] input clock, // @[AsyncQueue.scala:63:17] input reset // @[AsyncQueue.scala:64:17] ); wire io_in_0 = io_in; // @[AsyncQueue.scala:58:7] wire _io_out_WIRE; // @[ShiftReg.scala:48:24] wire io_out_0; // @[AsyncQueue.scala:58:7] assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24] AsyncResetSynchronizerShiftReg_w1_d3_i0_183 io_out_source_extend ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (reset), .io_d (io_in_0), // @[AsyncQueue.scala:58:7] .io_q (_io_out_WIRE) ); // @[ShiftReg.scala:45:23] assign io_out = io_out_0; // @[AsyncQueue.scala:58:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File ShiftReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ // Similar to the Chisel ShiftRegister but allows the user to suggest a // name to the registers that get instantiated, and // to provide a reset value. object ShiftRegInit { def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T = (0 until n).foldRight(in) { case (i, next) => { val r = RegNext(next, init) name.foreach { na => r.suggestName(s"${na}_${i}") } r } } } /** These wrap behavioral * shift registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * The different types vary in their reset behavior: * AsyncResetShiftReg -- Asynchronously reset register array * A W(width) x D(depth) sized array is constructed from D instantiations of a * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg, * but only used for timing applications / abstract class AbstractPipelineReg(w: Int = 1) extends Module { val io = IO(new Bundle { val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) } ) } object AbstractPipelineReg { def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = { val chain = Module(gen) name.foreach{ chain.suggestName(_) } chain.io.d := in.asUInt chain.io.q.asTypeOf(in) } } class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) { require(depth > 0, "Depth must be greater than 0.") override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}" val chain = List.tabulate(depth) { i => Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}") } chain.last.io.d := io.d chain.last.io.en := true.B (chain.init zip chain.tail).foreach { case (sink, source) => sink.io.d := source.io.q sink.io.en := true.B } io.q := chain.head.io.q } object AsyncResetShiftReg { def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name) def apply [T <: Data](in: T, depth: Int, name: Option[String]): T = apply(in, depth, 0, name) def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T = apply(in, depth, init.litValue.toInt, name) def apply [T <: Data](in: T, depth: Int, init: T): T = apply (in, depth, init.litValue.toInt, None) } File SynchronizerReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util.{RegEnable, Cat} /* These wrap behavioral * shift and next registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * * These are built up of ResetSynchronizerPrimitiveShiftReg, intended to be replaced by the integrator's metastable flops chains or replaced * at this level if they have a multi-bit wide synchronizer primitive. * The different types vary in their reset behavior: * NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin * AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep * 1-bit-wide shift registers. * SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg * * [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference. * * ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross * Clock Domains. */ object SynchronizerResetType extends Enumeration { val NonSync, Inferred, Sync, Async = Value } // Note: this should not be used directly. // Use the companion object to generate this with the correct reset type mixin. private class SynchronizerPrimitiveShiftReg( sync: Int, init: Boolean, resetType: SynchronizerResetType.Value) extends AbstractPipelineReg(1) { val initInt = if (init) 1 else 0 val initPostfix = resetType match { case SynchronizerResetType.NonSync => "" case _ => s"_i${initInt}" } override def desiredName = s"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}" val chain = List.tabulate(sync) { i => val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B) reg.suggestName(s"sync_$i") } chain.last := io.d.asBool (chain.init zip chain.tail).foreach { case (sink, source) => sink := source } io.q := chain.head.asUInt } private object SynchronizerPrimitiveShiftReg { def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = { val gen: () => SynchronizerPrimitiveShiftReg = resetType match { case SynchronizerResetType.NonSync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) case SynchronizerResetType.Async => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset case SynchronizerResetType.Sync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset case SynchronizerResetType.Inferred => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) } AbstractPipelineReg(gen(), in) } } // Note: This module may end up with a non-AsyncReset type reset. // But the Primitives within will always have AsyncReset type. class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asAsyncReset){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async) } } io.q := Cat(output.reverse) } object AsyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } // Note: This module may end up with a non-Bool type reset. // But the Primitives within will always have Bool reset type. @deprecated("SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.", "rocket-chip 1.2") class SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asBool){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync) } } io.q := Cat(output.reverse) } object SyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred) } io.q := Cat(output.reverse) } object ResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}" val output = Seq.tabulate(w) { i => SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync) } io.q := Cat(output.reverse) } object SynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, None) def apply [T <: Data](in: T): T = apply (in, 3, None) } class ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module { override def desiredName = s"ClockCrossingReg_w${w}" val io = IO(new Bundle{ val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) val en = Input(Bool()) }) val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en) io.q := cdc_reg } object ClockCrossingReg { def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = { val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit)) name.foreach{ cdc_reg.suggestName(_) } cdc_reg.io.d := in.asUInt cdc_reg.io.en := en cdc_reg.io.q.asTypeOf(in) } }	module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_482( // @[SynchronizerReg.scala:68:19] input clock, // @[SynchronizerReg.scala:68:19] input reset, // @[SynchronizerReg.scala:68:19] input io_d, // @[ShiftReg.scala:36:14] output io_q // @[ShiftReg.scala:36:14] ); wire io_d_0 = io_d; // @[SynchronizerReg.scala:68:19] wire _sync_2_T = io_d_0; // @[SynchronizerReg.scala:54:22, :68:19] wire io_q_0; // @[SynchronizerReg.scala:68:19] reg sync_0; // @[SynchronizerReg.scala:51:87] assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19] reg sync_1; // @[SynchronizerReg.scala:51:87] reg sync_2; // @[SynchronizerReg.scala:51:87] always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19] if (reset) begin // @[SynchronizerReg.scala:68:19] sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87] end else begin // @[SynchronizerReg.scala:68:19] sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87] sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87] sync_2 <= _sync_2_T; // @[SynchronizerReg.scala:51:87, :54:22] end always @(posedge, posedge)
Generate the Verilog code corresponding to the following Chisel files. File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /* Like Vec.apply(idx), but tolerates indices of mismatched width / def extract(idx: UInt): T = x((idx \| 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx \| 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def \| (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a \|\| b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_\|\|_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /* Any Data subtype that has a Bool member named valid. / type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /* converts from camel case to to underscores, also removing all spaces / def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /* converts spaces or underscores to hyphens, also lowering case / def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y \| (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y \|\| y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 \| 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /* Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation */ def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag }	module OptimizationBarrier_TLBEntryData_283( // @[package.scala:267:30] input clock, // @[package.scala:267:30] input reset, // @[package.scala:267:30] input [19:0] io_x_ppn, // @[package.scala:268:18] input io_x_u, // @[package.scala:268:18] input io_x_g, // @[package.scala:268:18] input io_x_ae_ptw, // @[package.scala:268:18] input io_x_ae_final, // @[package.scala:268:18] input io_x_ae_stage2, // @[package.scala:268:18] input io_x_pf, // @[package.scala:268:18] input io_x_gf, // @[package.scala:268:18] input io_x_sw, // @[package.scala:268:18] input io_x_sx, // @[package.scala:268:18] input io_x_sr, // @[package.scala:268:18] input io_x_hw, // @[package.scala:268:18] input io_x_hx, // @[package.scala:268:18] input io_x_hr, // @[package.scala:268:18] input io_x_pw, // @[package.scala:268:18] input io_x_px, // @[package.scala:268:18] input io_x_pr, // @[package.scala:268:18] input io_x_ppp, // @[package.scala:268:18] input io_x_pal, // @[package.scala:268:18] input io_x_paa, // @[package.scala:268:18] input io_x_eff, // @[package.scala:268:18] input io_x_c, // @[package.scala:268:18] input io_x_fragmented_superpage, // @[package.scala:268:18] output [19:0] io_y_ppn, // @[package.scala:268:18] output io_y_u, // @[package.scala:268:18] output io_y_ae_ptw, // @[package.scala:268:18] output io_y_ae_final, // @[package.scala:268:18] output io_y_ae_stage2, // @[package.scala:268:18] output io_y_pf, // @[package.scala:268:18] output io_y_gf, // @[package.scala:268:18] output io_y_sw, // @[package.scala:268:18] output io_y_sx, // @[package.scala:268:18] output io_y_sr, // @[package.scala:268:18] output io_y_hw, // @[package.scala:268:18] output io_y_hx, // @[package.scala:268:18] output io_y_hr, // @[package.scala:268:18] output io_y_pw, // @[package.scala:268:18] output io_y_px, // @[package.scala:268:18] output io_y_pr, // @[package.scala:268:18] output io_y_ppp, // @[package.scala:268:18] output io_y_pal, // @[package.scala:268:18] output io_y_paa, // @[package.scala:268:18] output io_y_eff, // @[package.scala:268:18] output io_y_c // @[package.scala:268:18] ); wire [19:0] io_x_ppn_0 = io_x_ppn; // @[package.scala:267:30] wire io_x_u_0 = io_x_u; // @[package.scala:267:30] wire io_x_g_0 = io_x_g; // @[package.scala:267:30] wire io_x_ae_ptw_0 = io_x_ae_ptw; // @[package.scala:267:30] wire io_x_ae_final_0 = io_x_ae_final; // @[package.scala:267:30] wire io_x_ae_stage2_0 = io_x_ae_stage2; // @[package.scala:267:30] wire io_x_pf_0 = io_x_pf; // @[package.scala:267:30] wire io_x_gf_0 = io_x_gf; // @[package.scala:267:30] wire io_x_sw_0 = io_x_sw; // @[package.scala:267:30] wire io_x_sx_0 = io_x_sx; // @[package.scala:267:30] wire io_x_sr_0 = io_x_sr; // @[package.scala:267:30] wire io_x_hw_0 = io_x_hw; // @[package.scala:267:30] wire io_x_hx_0 = io_x_hx; // @[package.scala:267:30] wire io_x_hr_0 = io_x_hr; // @[package.scala:267:30] wire io_x_pw_0 = io_x_pw; // @[package.scala:267:30] wire io_x_px_0 = io_x_px; // @[package.scala:267:30] wire io_x_pr_0 = io_x_pr; // @[package.scala:267:30] wire io_x_ppp_0 = io_x_ppp; // @[package.scala:267:30] wire io_x_pal_0 = io_x_pal; // @[package.scala:267:30] wire io_x_paa_0 = io_x_paa; // @[package.scala:267:30] wire io_x_eff_0 = io_x_eff; // @[package.scala:267:30] wire io_x_c_0 = io_x_c; // @[package.scala:267:30] wire io_x_fragmented_superpage_0 = io_x_fragmented_superpage; // @[package.scala:267:30] wire [19:0] io_y_ppn_0 = io_x_ppn_0; // @[package.scala:267:30] wire io_y_u_0 = io_x_u_0; // @[package.scala:267:30] wire io_y_g = io_x_g_0; // @[package.scala:267:30] wire io_y_ae_ptw_0 = io_x_ae_ptw_0; // @[package.scala:267:30] wire io_y_ae_final_0 = io_x_ae_final_0; // @[package.scala:267:30] wire io_y_ae_stage2_0 = io_x_ae_stage2_0; // @[package.scala:267:30] wire io_y_pf_0 = io_x_pf_0; // @[package.scala:267:30] wire io_y_gf_0 = io_x_gf_0; // @[package.scala:267:30] wire io_y_sw_0 = io_x_sw_0; // @[package.scala:267:30] wire io_y_sx_0 = io_x_sx_0; // @[package.scala:267:30] wire io_y_sr_0 = io_x_sr_0; // @[package.scala:267:30] wire io_y_hw_0 = io_x_hw_0; // @[package.scala:267:30] wire io_y_hx_0 = io_x_hx_0; // @[package.scala:267:30] wire io_y_hr_0 = io_x_hr_0; // @[package.scala:267:30] wire io_y_pw_0 = io_x_pw_0; // @[package.scala:267:30] wire io_y_px_0 = io_x_px_0; // @[package.scala:267:30] wire io_y_pr_0 = io_x_pr_0; // @[package.scala:267:30] wire io_y_ppp_0 = io_x_ppp_0; // @[package.scala:267:30] wire io_y_pal_0 = io_x_pal_0; // @[package.scala:267:30] wire io_y_paa_0 = io_x_paa_0; // @[package.scala:267:30] wire io_y_eff_0 = io_x_eff_0; // @[package.scala:267:30] wire io_y_c_0 = io_x_c_0; // @[package.scala:267:30] wire io_y_fragmented_superpage = io_x_fragmented_superpage_0; // @[package.scala:267:30] assign io_y_ppn = io_y_ppn_0; // @[package.scala:267:30] assign io_y_u = io_y_u_0; // @[package.scala:267:30] assign io_y_ae_ptw = io_y_ae_ptw_0; // @[package.scala:267:30] assign io_y_ae_final = io_y_ae_final_0; // @[package.scala:267:30] assign io_y_ae_stage2 = io_y_ae_stage2_0; // @[package.scala:267:30] assign io_y_pf = io_y_pf_0; // @[package.scala:267:30] assign io_y_gf = io_y_gf_0; // @[package.scala:267:30] assign io_y_sw = io_y_sw_0; // @[package.scala:267:30] assign io_y_sx = io_y_sx_0; // @[package.scala:267:30] assign io_y_sr = io_y_sr_0; // @[package.scala:267:30] assign io_y_hw = io_y_hw_0; // @[package.scala:267:30] assign io_y_hx = io_y_hx_0; // @[package.scala:267:30] assign io_y_hr = io_y_hr_0; // @[package.scala:267:30] assign io_y_pw = io_y_pw_0; // @[package.scala:267:30] assign io_y_px = io_y_px_0; // @[package.scala:267:30] assign io_y_pr = io_y_pr_0; // @[package.scala:267:30] assign io_y_ppp = io_y_ppp_0; // @[package.scala:267:30] assign io_y_pal = io_y_pal_0; // @[package.scala:267:30] assign io_y_paa = io_y_paa_0; // @[package.scala:267:30] assign io_y_eff = io_y_eff_0; // @[package.scala:267:30] assign io_y_c = io_y_c_0; // @[package.scala:267:30] endmodule
Generate the Verilog code corresponding to the following Chisel files. File Misc.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import scala.math._ class ParameterizedBundle(implicit p: Parameters) extends Bundle trait Clocked extends Bundle { val clock = Clock() val reset = Bool() } object DecoupledHelper { def apply(rvs: Bool) = new DecoupledHelper(rvs) } class DecoupledHelper(val rvs: Seq[Bool]) { def fire(exclude: Bool, includes: Bool) = { require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!") (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _) } def fire() = { rvs.reduce(_ && _) } } object MuxT { def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2)) def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3)) def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4)) } /** Creates a cascade of n MuxTs to search for a key value. / object MuxTLookup { def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } } object ValidMux { def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]): ValidIO[T] = { apply(v1 +: v2.toSeq) } def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = { val out = Wire(Valid(valids.head.bits.cloneType)) out.valid := valids.map(_.valid).reduce(_ \|\| _) out.bits := MuxCase(valids.head.bits, valids.map(v => (v.valid -> v.bits))) out } } object Str { def apply(s: String): UInt = { var i = BigInt(0) require(s.forall(validChar _)) for (c <- s) i = (i << 8) \| c i.U((s.length8).W) } def apply(x: Char): UInt = { require(validChar(x)) x.U(8.W) } def apply(x: UInt): UInt = apply(x, 10) def apply(x: UInt, radix: Int): UInt = { val rad = radix.U val w = x.getWidth require(w > 0) var q = x var s = digit(q % rad) for (i <- 1 until ceil(log(2)/log(radix)w).toInt) { q = q / rad s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s) } s } def apply(x: SInt): UInt = apply(x, 10) def apply(x: SInt, radix: Int): UInt = { val neg = x < 0.S val abs = x.abs.asUInt if (radix != 10) { Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix)) } else { val rad = radix.U val w = abs.getWidth require(w > 0) var q = abs var s = digit(q % rad) var needSign = neg for (i <- 1 until ceil(log(2)/log(radix)w).toInt) { q = q / rad val placeSpace = q === 0.U val space = Mux(needSign, Str('-'), Str(' ')) needSign = needSign && !placeSpace s = Cat(Mux(placeSpace, space, digit(q % rad)), s) } Cat(Mux(needSign, Str('-'), Str(' ')), s) } } private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0) private def validChar(x: Char) = x == (x & 0xFF) } object Split { def apply(x: UInt, n0: Int) = { val w = x.getWidth (x.extract(w-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n2: Int, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } } object Random { def apply(mod: Int, random: UInt): UInt = { if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0) else PriorityEncoder(partition(apply(1 << log2Up(mod8), random), mod)) } def apply(mod: Int): UInt = apply(mod, randomizer) def oneHot(mod: Int, random: UInt): UInt = { if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0)) else PriorityEncoderOH(partition(apply(1 << log2Up(mod8), random), mod)).asUInt } def oneHot(mod: Int): UInt = oneHot(mod, randomizer) private def randomizer = LFSR(16) private def partition(value: UInt, slices: Int) = Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U) } object Majority { def apply(in: Set[Bool]): Bool = { val n = (in.size >> 1) + 1 val clauses = in.subsets(n).map(_.reduce(_ && _)) clauses.reduce(_ \|\| _) } def apply(in: Seq[Bool]): Bool = apply(in.toSet) def apply(in: UInt): Bool = apply(in.asBools.toSet) } object PopCountAtLeast { private def two(x: UInt): (Bool, Bool) = x.getWidth match { case 1 => (x.asBool, false.B) case n => val half = x.getWidth / 2 val (leftOne, leftTwo) = two(x(half - 1, 0)) val (rightOne, rightTwo) = two(x(x.getWidth - 1, half)) (leftOne \|\| rightOne, leftTwo \|\| rightTwo \|\| (leftOne && rightOne)) } def apply(x: UInt, n: Int): Bool = n match { case 0 => true.B case 1 => x.orR case 2 => two(x)._2 case 3 => PopCount(x) >= n.U } } // This gets used everywhere, so make the smallest circuit possible ... // Given an address and size, create a mask of beatBytes size // eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111 // groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01 object MaskGen { def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = { require (groupBy >= 1 && beatBytes >= groupBy) require (isPow2(beatBytes) && isPow2(groupBy)) val lgBytes = log2Ceil(beatBytes) val sizeOH = UIntToOH(lgSize \| 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) \| (groupBy2 - 1).U def helper(i: Int): Seq[(Bool, Bool)] = { if (i == 0) { Seq((lgSize >= lgBytes.asUInt, true.B)) } else { val sub = helper(i-1) val size = sizeOH(lgBytes - i) val bit = addr_lo(lgBytes - i) val nbit = !bit Seq.tabulate (1 << i) { j => val (sub_acc, sub_eq) = sub(j/2) val eq = sub_eq && (if (j % 2 == 1) bit else nbit) val acc = sub_acc \|\| (size && eq) (acc, eq) } } } if (groupBy == beatBytes) 1.U else Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse) } } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /* Like Vec.apply(idx), but tolerates indices of mismatched width / def extract(idx: UInt): T = x((idx \| 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx \| 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def \| (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a \|\| b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_\|\|_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /* Any Data subtype that has a Bool member named valid. / type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /* converts from camel case to to underscores, also removing all spaces / def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /* converts spaces or underscores to hyphens, also lowering case / def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y \| (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y \|\| y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 \| 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /* Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation / def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Replacement.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import freechips.rocketchip.util.property.cover abstract class ReplacementPolicy { def nBits: Int def perSet: Boolean def way: UInt def miss: Unit def hit: Unit def access(touch_way: UInt): Unit def access(touch_ways: Seq[Valid[UInt]]): Unit def state_read: UInt def get_next_state(state: UInt, touch_way: UInt): UInt def get_next_state(state: UInt, touch_ways: Seq[Valid[UInt]]): UInt = { touch_ways.foldLeft(state)((prev, touch_way) => Mux(touch_way.valid, get_next_state(prev, touch_way.bits), prev)) } def get_replace_way(state: UInt): UInt } object ReplacementPolicy { def fromString(s: String, n_ways: Int): ReplacementPolicy = s.toLowerCase match { case "random" => new RandomReplacement(n_ways) case "lru" => new TrueLRU(n_ways) case "plru" => new PseudoLRU(n_ways) case t => throw new IllegalArgumentException(s"unknown Replacement Policy type $t") } } class RandomReplacement(n_ways: Int) extends ReplacementPolicy { private val replace = Wire(Bool()) replace := false.B def nBits = 16 def perSet = false private val lfsr = LFSR(nBits, replace) def state_read = WireDefault(lfsr) def way = Random(n_ways, lfsr) def miss = replace := true.B def hit = {} def access(touch_way: UInt) = {} def access(touch_ways: Seq[Valid[UInt]]) = {} def get_next_state(state: UInt, touch_way: UInt) = 0.U //DontCare def get_replace_way(state: UInt) = way } abstract class SeqReplacementPolicy { def access(set: UInt): Unit def update(valid: Bool, hit: Bool, set: UInt, way: UInt): Unit def way: UInt } abstract class SetAssocReplacementPolicy { def access(set: UInt, touch_way: UInt): Unit def access(sets: Seq[UInt], touch_ways: Seq[Valid[UInt]]): Unit def way(set: UInt): UInt } class SeqRandom(n_ways: Int) extends SeqReplacementPolicy { val logic = new RandomReplacement(n_ways) def access(set: UInt) = { } def update(valid: Bool, hit: Bool, set: UInt, way: UInt) = { when (valid && !hit) { logic.miss } } def way = logic.way } class TrueLRU(n_ways: Int) extends ReplacementPolicy { // True LRU replacement policy, using a triangular matrix to track which sets are more recently used than others. // The matrix is packed into a single UInt (or Bits). Example 4-way (6-bits): // [5] - 3 more recent than 2 // [4] - 3 more recent than 1 // [3] - 2 more recent than 1 // [2] - 3 more recent than 0 // [1] - 2 more recent than 0 // [0] - 1 more recent than 0 def nBits = (n_ways (n_ways-1)) / 2 def perSet = true private val state_reg = RegInit(0.U(nBits.W)) def state_read = WireDefault(state_reg) private def extractMRUVec(state: UInt): Seq[UInt] = { // Extract per-way information about which higher-indexed ways are more recently used val moreRecentVec = Wire(Vec(n_ways-1, UInt(n_ways.W))) var lsb = 0 for (i <- 0 until n_ways-1) { moreRecentVec(i) := Cat(state(lsb+n_ways-i-2,lsb), 0.U((i+1).W)) lsb = lsb + (n_ways - i - 1) } moreRecentVec } def get_next_state(state: UInt, touch_way: UInt): UInt = { val nextState = Wire(Vec(n_ways-1, UInt(n_ways.W))) val moreRecentVec = extractMRUVec(state) // reconstruct lower triangular matrix val wayDec = UIntToOH(touch_way, n_ways) // Compute next value of triangular matrix // set the touched way as more recent than every other way nextState.zipWithIndex.map { case (e, i) => e := Mux(i.U === touch_way, 0.U(n_ways.W), moreRecentVec(i) \| wayDec) } nextState.zipWithIndex.tail.foldLeft((nextState.head.apply(n_ways-1,1),0)) { case ((pe,pi),(ce,ci)) => (Cat(ce.apply(n_ways-1,ci+1), pe), ci) }._1 } def access(touch_way: UInt): Unit = { state_reg := get_next_state(state_reg, touch_way) } def access(touch_ways: Seq[Valid[UInt]]): Unit = { when (touch_ways.map(_.valid).orR) { state_reg := get_next_state(state_reg, touch_ways) } for (i <- 1 until touch_ways.size) { cover(PopCount(touch_ways.map(_.valid)) === i.U, s"LRU_UpdateCount$i", s"LRU Update $i simultaneous") } } def get_replace_way(state: UInt): UInt = { val moreRecentVec = extractMRUVec(state) // reconstruct lower triangular matrix // For each way, determine if all other ways are more recent val mruWayDec = (0 until n_ways).map { i => val upperMoreRecent = (if (i == n_ways-1) true.B else moreRecentVec(i).apply(n_ways-1,i+1).andR) val lowerMoreRecent = (if (i == 0) true.B else moreRecentVec.map(e => !e(i)).reduce(_ && _)) upperMoreRecent && lowerMoreRecent } OHToUInt(mruWayDec) } def way = get_replace_way(state_reg) def miss = access(way) def hit = {} @deprecated("replace 'replace' with 'way' from abstract class ReplacementPolicy","Rocket Chip 2020.05") def replace: UInt = way } class PseudoLRU(n_ways: Int) extends ReplacementPolicy { // Pseudo-LRU tree algorithm: https://en.wikipedia.org/wiki/Pseudo-LRU#Tree-PLRU // // // - bits storage example for 4-way PLRU binary tree: // bit[2]: ways 3+2 older than ways 1+0 // / \ // bit[1]: way 3 older than way 2 bit[0]: way 1 older than way 0 // // // - bits storage example for 3-way PLRU binary tree: // bit[1]: way 2 older than ways 1+0 // \ // bit[0]: way 1 older than way 0 // // // - bits storage example for 8-way PLRU binary tree: // bit[6]: ways 7-4 older than ways 3-0 // / \ // bit[5]: ways 7+6 > 5+4 bit[2]: ways 3+2 > 1+0 // / \ / \ // bit[4]: way 7>6 bit[3]: way 5>4 bit[1]: way 3>2 bit[0]: way 1>0 def nBits = n_ways - 1 def perSet = true private val state_reg = if (nBits == 0) Reg(UInt(0.W)) else RegInit(0.U(nBits.W)) def state_read = WireDefault(state_reg) def access(touch_way: UInt): Unit = { state_reg := get_next_state(state_reg, touch_way) } def access(touch_ways: Seq[Valid[UInt]]): Unit = { when (touch_ways.map(_.valid).orR) { state_reg := get_next_state(state_reg, touch_ways) } for (i <- 1 until touch_ways.size) { cover(PopCount(touch_ways.map(_.valid)) === i.U, s"PLRU_UpdateCount$i", s"PLRU Update $i simultaneous") } } /** @param state state_reg bits for this sub-tree * @param touch_way touched way encoded value bits for this sub-tree * @param tree_nways number of ways in this sub-tree / def get_next_state(state: UInt, touch_way: UInt, tree_nways: Int): UInt = { require(state.getWidth == (tree_nways-1), s"wrong state bits width ${state.getWidth} for $tree_nways ways") require(touch_way.getWidth == (log2Ceil(tree_nways) max 1), s"wrong encoded way width ${touch_way.getWidth} for $tree_nways ways") if (tree_nways > 2) { // we are at a branching node in the tree, so recurse val right_nways: Int = 1 << (log2Ceil(tree_nways) - 1) // number of ways in the right sub-tree val left_nways: Int = tree_nways - right_nways // number of ways in the left sub-tree val set_left_older = !touch_way(log2Ceil(tree_nways)-1) val left_subtree_state = state.extract(tree_nways-3, right_nways-1) val right_subtree_state = state(right_nways-2, 0) if (left_nways > 1) { // we are at a branching node in the tree with both left and right sub-trees, so recurse both sub-trees Cat(set_left_older, Mux(set_left_older, left_subtree_state, // if setting left sub-tree as older, do NOT recurse into left sub-tree get_next_state(left_subtree_state, touch_way.extract(log2Ceil(left_nways)-1,0), left_nways)), // recurse left if newer Mux(set_left_older, get_next_state(right_subtree_state, touch_way(log2Ceil(right_nways)-1,0), right_nways), // recurse right if newer right_subtree_state)) // if setting right sub-tree as older, do NOT recurse into right sub-tree } else { // we are at a branching node in the tree with only a right sub-tree, so recurse only right sub-tree Cat(set_left_older, Mux(set_left_older, get_next_state(right_subtree_state, touch_way(log2Ceil(right_nways)-1,0), right_nways), // recurse right if newer right_subtree_state)) // if setting right sub-tree as older, do NOT recurse into right sub-tree } } else if (tree_nways == 2) { // we are at a leaf node at the end of the tree, so set the single state bit opposite of the lsb of the touched way encoded value !touch_way(0) } else { // tree_nways <= 1 // we are at an empty node in an empty tree for 1 way, so return single zero bit for Chisel (no zero-width wires) 0.U(1.W) } } def get_next_state(state: UInt, touch_way: UInt): UInt = { val touch_way_sized = if (touch_way.getWidth < log2Ceil(n_ways)) touch_way.padTo (log2Ceil(n_ways)) else touch_way.extract(log2Ceil(n_ways)-1,0) get_next_state(state, touch_way_sized, n_ways) } /* @param state state_reg bits for this sub-tree * @param tree_nways number of ways in this sub-tree / def get_replace_way(state: UInt, tree_nways: Int): UInt = { require(state.getWidth == (tree_nways-1), s"wrong state bits width ${state.getWidth} for $tree_nways ways") // this algorithm recursively descends the binary tree, filling in the way-to-replace encoded value from msb to lsb if (tree_nways > 2) { // we are at a branching node in the tree, so recurse val right_nways: Int = 1 << (log2Ceil(tree_nways) - 1) // number of ways in the right sub-tree val left_nways: Int = tree_nways - right_nways // number of ways in the left sub-tree val left_subtree_older = state(tree_nways-2) val left_subtree_state = state.extract(tree_nways-3, right_nways-1) val right_subtree_state = state(right_nways-2, 0) if (left_nways > 1) { // we are at a branching node in the tree with both left and right sub-trees, so recurse both sub-trees Cat(left_subtree_older, // return the top state bit (current tree node) as msb of the way-to-replace encoded value Mux(left_subtree_older, // if left sub-tree is older, recurse left, else recurse right get_replace_way(left_subtree_state, left_nways), // recurse left get_replace_way(right_subtree_state, right_nways))) // recurse right } else { // we are at a branching node in the tree with only a right sub-tree, so recurse only right sub-tree Cat(left_subtree_older, // return the top state bit (current tree node) as msb of the way-to-replace encoded value Mux(left_subtree_older, // if left sub-tree is older, return and do not recurse right 0.U(1.W), get_replace_way(right_subtree_state, right_nways))) // recurse right } } else if (tree_nways == 2) { // we are at a leaf node at the end of the tree, so just return the single state bit as lsb of the way-to-replace encoded value state(0) } else { // tree_nways <= 1 // we are at an empty node in an unbalanced tree for non-power-of-2 ways, so return single zero bit as lsb of the way-to-replace encoded value 0.U(1.W) } } def get_replace_way(state: UInt): UInt = get_replace_way(state, n_ways) def way = get_replace_way(state_reg) def miss = access(way) def hit = {} } class SeqPLRU(n_sets: Int, n_ways: Int) extends SeqReplacementPolicy { val logic = new PseudoLRU(n_ways) val state = SyncReadMem(n_sets, UInt(logic.nBits.W)) val current_state = Wire(UInt(logic.nBits.W)) val next_state = Wire(UInt(logic.nBits.W)) val plru_way = logic.get_replace_way(current_state) def access(set: UInt) = { current_state := state.read(set) } def update(valid: Bool, hit: Bool, set: UInt, way: UInt) = { val update_way = Mux(hit, way, plru_way) next_state := logic.get_next_state(current_state, update_way) when (valid) { state.write(set, next_state) } } def way = plru_way } class SetAssocLRU(n_sets: Int, n_ways: Int, policy: String) extends SetAssocReplacementPolicy { val logic = policy.toLowerCase match { case "plru" => new PseudoLRU(n_ways) case "lru" => new TrueLRU(n_ways) case t => throw new IllegalArgumentException(s"unknown Replacement Policy type $t") } val state_vec = if (logic.nBits == 0) Reg(Vec(n_sets, UInt(logic.nBits.W))) // Work around elaboration error on following line else RegInit(VecInit(Seq.fill(n_sets)(0.U(logic.nBits.W)))) def access(set: UInt, touch_way: UInt) = { state_vec(set) := logic.get_next_state(state_vec(set), touch_way) } def access(sets: Seq[UInt], touch_ways: Seq[Valid[UInt]]) = { require(sets.size == touch_ways.size, "internal consistency check: should be same number of simultaneous updates for sets and touch_ways") for (set <- 0 until n_sets) { val set_touch_ways = (sets zip touch_ways).map { case (touch_set, touch_way) => Pipe(touch_way.valid && (touch_set === set.U), touch_way.bits, 0)} when (set_touch_ways.map(_.valid).orR) { state_vec(set) := logic.get_next_state(state_vec(set), set_touch_ways) } } } def way(set: UInt) = logic.get_replace_way(state_vec(set)) } // Synthesizable unit tests import freechips.rocketchip.unittest._ class PLRUTest(n_ways: Int, timeout: Int = 500) extends UnitTest(timeout) { val plru = new PseudoLRU(n_ways) // step io.finished := RegNext(true.B, false.B) val get_replace_ways = (0 until (1 << (n_ways-1))).map(state => plru.get_replace_way(state = state.U((n_ways-1).W))) val get_next_states = (0 until (1 << (n_ways-1))).map(state => (0 until n_ways).map(way => plru.get_next_state (state = state.U((n_ways-1).W), touch_way = way.U(log2Ceil(n_ways).W)))) n_ways match { case 2 => { assert(get_replace_ways(0) === 0.U(log2Ceil(n_ways).W), s"get_replace_way state=0: expected=0 actual=%d", get_replace_ways(0)) assert(get_replace_ways(1) === 1.U(log2Ceil(n_ways).W), s"get_replace_way state=1: expected=1 actual=%d", get_replace_ways(1)) assert(get_next_states(0)(0) === 1.U(plru.nBits.W), s"get_next_state state=0 way=0: expected=1 actual=%d", get_next_states(0)(0)) assert(get_next_states(0)(1) === 0.U(plru.nBits.W), s"get_next_state state=0 way=1: expected=0 actual=%d", get_next_states(0)(1)) assert(get_next_states(1)(0) === 1.U(plru.nBits.W), s"get_next_state state=1 way=0: expected=1 actual=%d", get_next_states(1)(0)) assert(get_next_states(1)(1) === 0.U(plru.nBits.W), s"get_next_state state=1 way=1: expected=0 actual=%d", get_next_states(1)(1)) } case 3 => { assert(get_replace_ways(0) === 0.U(log2Ceil(n_ways).W), s"get_replace_way state=0: expected=0 actual=%d", get_replace_ways(0)) assert(get_replace_ways(1) === 1.U(log2Ceil(n_ways).W), s"get_replace_way state=1: expected=1 actual=%d", get_replace_ways(1)) assert(get_replace_ways(2) === 2.U(log2Ceil(n_ways).W), s"get_replace_way state=2: expected=2 actual=%d", get_replace_ways(2)) assert(get_replace_ways(3) === 2.U(log2Ceil(n_ways).W), s"get_replace_way state=3: expected=2 actual=%d", get_replace_ways(3)) assert(get_next_states(0)(0) === 3.U(plru.nBits.W), s"get_next_state state=0 way=0: expected=3 actual=%d", get_next_states(0)(0)) assert(get_next_states(0)(1) === 2.U(plru.nBits.W), s"get_next_state state=0 way=1: expected=2 actual=%d", get_next_states(0)(1)) assert(get_next_states(0)(2) === 0.U(plru.nBits.W), s"get_next_state state=0 way=2: expected=0 actual=%d", get_next_states(0)(2)) assert(get_next_states(1)(0) === 3.U(plru.nBits.W), s"get_next_state state=1 way=0: expected=3 actual=%d", get_next_states(1)(0)) assert(get_next_states(1)(1) === 2.U(plru.nBits.W), s"get_next_state state=1 way=1: expected=2 actual=%d", get_next_states(1)(1)) assert(get_next_states(1)(2) === 1.U(plru.nBits.W), s"get_next_state state=1 way=2: expected=1 actual=%d", get_next_states(1)(2)) assert(get_next_states(2)(0) === 3.U(plru.nBits.W), s"get_next_state state=2 way=0: expected=3 actual=%d", get_next_states(2)(0)) assert(get_next_states(2)(1) === 2.U(plru.nBits.W), s"get_next_state state=2 way=1: expected=2 actual=%d", get_next_states(2)(1)) assert(get_next_states(2)(2) === 0.U(plru.nBits.W), s"get_next_state state=2 way=2: expected=0 actual=%d", get_next_states(2)(2)) assert(get_next_states(3)(0) === 3.U(plru.nBits.W), s"get_next_state state=3 way=0: expected=3 actual=%d", get_next_states(3)(0)) assert(get_next_states(3)(1) === 2.U(plru.nBits.W), s"get_next_state state=3 way=1: expected=2 actual=%d", get_next_states(3)(1)) assert(get_next_states(3)(2) === 1.U(plru.nBits.W), s"get_next_state state=3 way=2: expected=1 actual=%d", get_next_states(3)(2)) } case 4 => { assert(get_replace_ways(0) === 0.U(log2Ceil(n_ways).W), s"get_replace_way state=0: expected=0 actual=%d", get_replace_ways(0)) assert(get_replace_ways(1) === 1.U(log2Ceil(n_ways).W), s"get_replace_way state=1: expected=1 actual=%d", get_replace_ways(1)) assert(get_replace_ways(2) === 0.U(log2Ceil(n_ways).W), s"get_replace_way state=2: expected=0 actual=%d", get_replace_ways(2)) assert(get_replace_ways(3) === 1.U(log2Ceil(n_ways).W), s"get_replace_way state=3: expected=1 actual=%d", get_replace_ways(3)) assert(get_replace_ways(4) === 2.U(log2Ceil(n_ways).W), s"get_replace_way state=4: expected=2 actual=%d", get_replace_ways(4)) assert(get_replace_ways(5) === 2.U(log2Ceil(n_ways).W), s"get_replace_way state=5: expected=2 actual=%d", get_replace_ways(5)) assert(get_replace_ways(6) === 3.U(log2Ceil(n_ways).W), s"get_replace_way state=6: expected=3 actual=%d", get_replace_ways(6)) assert(get_replace_ways(7) === 3.U(log2Ceil(n_ways).W), s"get_replace_way state=7: expected=3 actual=%d", get_replace_ways(7)) assert(get_next_states(0)(0) === 5.U(plru.nBits.W), s"get_next_state state=0 way=0: expected=5 actual=%d", get_next_states(0)(0)) assert(get_next_states(0)(1) === 4.U(plru.nBits.W), s"get_next_state state=0 way=1: expected=4 actual=%d", get_next_states(0)(1)) assert(get_next_states(0)(2) === 2.U(plru.nBits.W), s"get_next_state state=0 way=2: expected=2 actual=%d", get_next_states(0)(2)) assert(get_next_states(0)(3) === 0.U(plru.nBits.W), s"get_next_state state=0 way=3: expected=0 actual=%d", get_next_states(0)(3)) assert(get_next_states(1)(0) === 5.U(plru.nBits.W), s"get_next_state state=1 way=0: expected=5 actual=%d", get_next_states(1)(0)) assert(get_next_states(1)(1) === 4.U(plru.nBits.W), s"get_next_state state=1 way=1: expected=4 actual=%d", get_next_states(1)(1)) assert(get_next_states(1)(2) === 3.U(plru.nBits.W), s"get_next_state state=1 way=2: expected=3 actual=%d", get_next_states(1)(2)) assert(get_next_states(1)(3) === 1.U(plru.nBits.W), s"get_next_state state=1 way=3: expected=1 actual=%d", get_next_states(1)(3)) assert(get_next_states(2)(0) === 7.U(plru.nBits.W), s"get_next_state state=2 way=0: expected=7 actual=%d", get_next_states(2)(0)) assert(get_next_states(2)(1) === 6.U(plru.nBits.W), s"get_next_state state=2 way=1: expected=6 actual=%d", get_next_states(2)(1)) assert(get_next_states(2)(2) === 2.U(plru.nBits.W), s"get_next_state state=2 way=2: expected=2 actual=%d", get_next_states(2)(2)) assert(get_next_states(2)(3) === 0.U(plru.nBits.W), s"get_next_state state=2 way=3: expected=0 actual=%d", get_next_states(2)(3)) assert(get_next_states(3)(0) === 7.U(plru.nBits.W), s"get_next_state state=3 way=0: expected=7 actual=%d", get_next_states(3)(0)) assert(get_next_states(3)(1) === 6.U(plru.nBits.W), s"get_next_state state=3 way=1: expected=6 actual=%d", get_next_states(3)(1)) assert(get_next_states(3)(2) === 3.U(plru.nBits.W), s"get_next_state state=3 way=2: expected=3 actual=%d", get_next_states(3)(2)) assert(get_next_states(3)(3) === 1.U(plru.nBits.W), s"get_next_state state=3 way=3: expected=1 actual=%d", get_next_states(3)(3)) assert(get_next_states(4)(0) === 5.U(plru.nBits.W), s"get_next_state state=4 way=0: expected=5 actual=%d", get_next_states(4)(0)) assert(get_next_states(4)(1) === 4.U(plru.nBits.W), s"get_next_state state=4 way=1: expected=4 actual=%d", get_next_states(4)(1)) assert(get_next_states(4)(2) === 2.U(plru.nBits.W), s"get_next_state state=4 way=2: expected=2 actual=%d", get_next_states(4)(2)) assert(get_next_states(4)(3) === 0.U(plru.nBits.W), s"get_next_state state=4 way=3: expected=0 actual=%d", get_next_states(4)(3)) assert(get_next_states(5)(0) === 5.U(plru.nBits.W), s"get_next_state state=5 way=0: expected=5 actual=%d", get_next_states(5)(0)) assert(get_next_states(5)(1) === 4.U(plru.nBits.W), s"get_next_state state=5 way=1: expected=4 actual=%d", get_next_states(5)(1)) assert(get_next_states(5)(2) === 3.U(plru.nBits.W), s"get_next_state state=5 way=2: expected=3 actual=%d", get_next_states(5)(2)) assert(get_next_states(5)(3) === 1.U(plru.nBits.W), s"get_next_state state=5 way=3: expected=1 actual=%d", get_next_states(5)(3)) assert(get_next_states(6)(0) === 7.U(plru.nBits.W), s"get_next_state state=6 way=0: expected=7 actual=%d", get_next_states(6)(0)) assert(get_next_states(6)(1) === 6.U(plru.nBits.W), s"get_next_state state=6 way=1: expected=6 actual=%d", get_next_states(6)(1)) assert(get_next_states(6)(2) === 2.U(plru.nBits.W), s"get_next_state state=6 way=2: expected=2 actual=%d", get_next_states(6)(2)) assert(get_next_states(6)(3) === 0.U(plru.nBits.W), s"get_next_state state=6 way=3: expected=0 actual=%d", get_next_states(6)(3)) assert(get_next_states(7)(0) === 7.U(plru.nBits.W), s"get_next_state state=7 way=0: expected=7 actual=%d", get_next_states(7)(0)) assert(get_next_states(7)(1) === 6.U(plru.nBits.W), s"get_next_state state=7 way=5: expected=6 actual=%d", get_next_states(7)(1)) assert(get_next_states(7)(2) === 3.U(plru.nBits.W), s"get_next_state state=7 way=2: expected=3 actual=%d", get_next_states(7)(2)) assert(get_next_states(7)(3) === 1.U(plru.nBits.W), s"get_next_state state=7 way=3: expected=1 actual=%d", get_next_states(7)(3)) } case 5 => { assert(get_replace_ways( 0) === 0.U(log2Ceil(n_ways).W), s"get_replace_way state=00: expected=0 actual=%d", get_replace_ways( 0)) assert(get_replace_ways( 1) === 1.U(log2Ceil(n_ways).W), s"get_replace_way state=01: expected=1 actual=%d", get_replace_ways( 1)) assert(get_replace_ways( 2) === 0.U(log2Ceil(n_ways).W), s"get_replace_way state=02: expected=0 actual=%d", get_replace_ways( 2)) assert(get_replace_ways( 3) === 1.U(log2Ceil(n_ways).W), s"get_replace_way state=03: expected=1 actual=%d", get_replace_ways( 3)) assert(get_replace_ways( 4) === 2.U(log2Ceil(n_ways).W), s"get_replace_way state=04: expected=2 actual=%d", get_replace_ways( 4)) assert(get_replace_ways( 5) === 2.U(log2Ceil(n_ways).W), s"get_replace_way state=05: expected=2 actual=%d", get_replace_ways( 5)) assert(get_replace_ways( 6) === 3.U(log2Ceil(n_ways).W), s"get_replace_way state=06: expected=3 actual=%d", get_replace_ways( 6)) assert(get_replace_ways( 7) === 3.U(log2Ceil(n_ways).W), s"get_replace_way state=07: expected=3 actual=%d", get_replace_ways( 7)) assert(get_replace_ways( 8) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=08: expected=4 actual=%d", get_replace_ways( 8)) assert(get_replace_ways( 9) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=09: expected=4 actual=%d", get_replace_ways( 9)) assert(get_replace_ways(10) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=10: expected=4 actual=%d", get_replace_ways(10)) assert(get_replace_ways(11) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=11: expected=4 actual=%d", get_replace_ways(11)) assert(get_replace_ways(12) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=12: expected=4 actual=%d", get_replace_ways(12)) assert(get_replace_ways(13) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=13: expected=4 actual=%d", get_replace_ways(13)) assert(get_replace_ways(14) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=14: expected=4 actual=%d", get_replace_ways(14)) assert(get_replace_ways(15) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=15: expected=4 actual=%d", get_replace_ways(15)) assert(get_next_states( 0)(0) === 13.U(plru.nBits.W), s"get_next_state state=00 way=0: expected=13 actual=%d", get_next_states( 0)(0)) assert(get_next_states( 0)(1) === 12.U(plru.nBits.W), s"get_next_state state=00 way=1: expected=12 actual=%d", get_next_states( 0)(1)) assert(get_next_states( 0)(2) === 10.U(plru.nBits.W), s"get_next_state state=00 way=2: expected=10 actual=%d", get_next_states( 0)(2)) assert(get_next_states( 0)(3) === 8.U(plru.nBits.W), s"get_next_state state=00 way=3: expected=08 actual=%d", get_next_states( 0)(3)) assert(get_next_states( 0)(4) === 0.U(plru.nBits.W), s"get_next_state state=00 way=4: expected=00 actual=%d", get_next_states( 0)(4)) assert(get_next_states( 1)(0) === 13.U(plru.nBits.W), s"get_next_state state=01 way=0: expected=13 actual=%d", get_next_states( 1)(0)) assert(get_next_states( 1)(1) === 12.U(plru.nBits.W), s"get_next_state state=01 way=1: expected=12 actual=%d", get_next_states( 1)(1)) assert(get_next_states( 1)(2) === 11.U(plru.nBits.W), s"get_next_state state=01 way=2: expected=11 actual=%d", get_next_states( 1)(2)) assert(get_next_states( 1)(3) === 9.U(plru.nBits.W), s"get_next_state state=01 way=3: expected=09 actual=%d", get_next_states( 1)(3)) assert(get_next_states( 1)(4) === 1.U(plru.nBits.W), s"get_next_state state=01 way=4: expected=01 actual=%d", get_next_states( 1)(4)) assert(get_next_states( 2)(0) === 15.U(plru.nBits.W), s"get_next_state state=02 way=0: expected=15 actual=%d", get_next_states( 2)(0)) assert(get_next_states( 2)(1) === 14.U(plru.nBits.W), s"get_next_state state=02 way=1: expected=14 actual=%d", get_next_states( 2)(1)) assert(get_next_states( 2)(2) === 10.U(plru.nBits.W), s"get_next_state state=02 way=2: expected=10 actual=%d", get_next_states( 2)(2)) assert(get_next_states( 2)(3) === 8.U(plru.nBits.W), s"get_next_state state=02 way=3: expected=08 actual=%d", get_next_states( 2)(3)) assert(get_next_states( 2)(4) === 2.U(plru.nBits.W), s"get_next_state state=02 way=4: expected=02 actual=%d", get_next_states( 2)(4)) assert(get_next_states( 3)(0) === 15.U(plru.nBits.W), s"get_next_state state=03 way=0: expected=15 actual=%d", get_next_states( 3)(0)) assert(get_next_states( 3)(1) === 14.U(plru.nBits.W), s"get_next_state state=03 way=1: expected=14 actual=%d", get_next_states( 3)(1)) assert(get_next_states( 3)(2) === 11.U(plru.nBits.W), s"get_next_state state=03 way=2: expected=11 actual=%d", get_next_states( 3)(2)) assert(get_next_states( 3)(3) === 9.U(plru.nBits.W), s"get_next_state state=03 way=3: expected=09 actual=%d", get_next_states( 3)(3)) assert(get_next_states( 3)(4) === 3.U(plru.nBits.W), s"get_next_state state=03 way=4: expected=03 actual=%d", get_next_states( 3)(4)) assert(get_next_states( 4)(0) === 13.U(plru.nBits.W), s"get_next_state state=04 way=0: expected=13 actual=%d", get_next_states( 4)(0)) assert(get_next_states( 4)(1) === 12.U(plru.nBits.W), s"get_next_state state=04 way=1: expected=12 actual=%d", get_next_states( 4)(1)) assert(get_next_states( 4)(2) === 10.U(plru.nBits.W), s"get_next_state state=04 way=2: expected=10 actual=%d", get_next_states( 4)(2)) assert(get_next_states( 4)(3) === 8.U(plru.nBits.W), s"get_next_state state=04 way=3: expected=08 actual=%d", get_next_states( 4)(3)) assert(get_next_states( 4)(4) === 4.U(plru.nBits.W), s"get_next_state state=04 way=4: expected=04 actual=%d", get_next_states( 4)(4)) assert(get_next_states( 5)(0) === 13.U(plru.nBits.W), s"get_next_state state=05 way=0: expected=13 actual=%d", get_next_states( 5)(0)) assert(get_next_states( 5)(1) === 12.U(plru.nBits.W), s"get_next_state state=05 way=1: expected=12 actual=%d", get_next_states( 5)(1)) assert(get_next_states( 5)(2) === 11.U(plru.nBits.W), s"get_next_state state=05 way=2: expected=11 actual=%d", get_next_states( 5)(2)) assert(get_next_states( 5)(3) === 9.U(plru.nBits.W), s"get_next_state state=05 way=3: expected=09 actual=%d", get_next_states( 5)(3)) assert(get_next_states( 5)(4) === 5.U(plru.nBits.W), s"get_next_state state=05 way=4: expected=05 actual=%d", get_next_states( 5)(4)) assert(get_next_states( 6)(0) === 15.U(plru.nBits.W), s"get_next_state state=06 way=0: expected=15 actual=%d", get_next_states( 6)(0)) assert(get_next_states( 6)(1) === 14.U(plru.nBits.W), s"get_next_state state=06 way=1: expected=14 actual=%d", get_next_states( 6)(1)) assert(get_next_states( 6)(2) === 10.U(plru.nBits.W), s"get_next_state state=06 way=2: expected=10 actual=%d", get_next_states( 6)(2)) assert(get_next_states( 6)(3) === 8.U(plru.nBits.W), s"get_next_state state=06 way=3: expected=08 actual=%d", get_next_states( 6)(3)) assert(get_next_states( 6)(4) === 6.U(plru.nBits.W), s"get_next_state state=06 way=4: expected=06 actual=%d", get_next_states( 6)(4)) assert(get_next_states( 7)(0) === 15.U(plru.nBits.W), s"get_next_state state=07 way=0: expected=15 actual=%d", get_next_states( 7)(0)) assert(get_next_states( 7)(1) === 14.U(plru.nBits.W), s"get_next_state state=07 way=5: expected=14 actual=%d", get_next_states( 7)(1)) assert(get_next_states( 7)(2) === 11.U(plru.nBits.W), s"get_next_state state=07 way=2: expected=11 actual=%d", get_next_states( 7)(2)) assert(get_next_states( 7)(3) === 9.U(plru.nBits.W), s"get_next_state state=07 way=3: expected=09 actual=%d", get_next_states( 7)(3)) assert(get_next_states( 7)(4) === 7.U(plru.nBits.W), s"get_next_state state=07 way=4: expected=07 actual=%d", get_next_states( 7)(4)) assert(get_next_states( 8)(0) === 13.U(plru.nBits.W), s"get_next_state state=08 way=0: expected=13 actual=%d", get_next_states( 8)(0)) assert(get_next_states( 8)(1) === 12.U(plru.nBits.W), s"get_next_state state=08 way=1: expected=12 actual=%d", get_next_states( 8)(1)) assert(get_next_states( 8)(2) === 10.U(plru.nBits.W), s"get_next_state state=08 way=2: expected=10 actual=%d", get_next_states( 8)(2)) assert(get_next_states( 8)(3) === 8.U(plru.nBits.W), s"get_next_state state=08 way=3: expected=08 actual=%d", get_next_states( 8)(3)) assert(get_next_states( 8)(4) === 0.U(plru.nBits.W), s"get_next_state state=08 way=4: expected=00 actual=%d", get_next_states( 8)(4)) assert(get_next_states( 9)(0) === 13.U(plru.nBits.W), s"get_next_state state=09 way=0: expected=13 actual=%d", get_next_states( 9)(0)) assert(get_next_states( 9)(1) === 12.U(plru.nBits.W), s"get_next_state state=09 way=1: expected=12 actual=%d", get_next_states( 9)(1)) assert(get_next_states( 9)(2) === 11.U(plru.nBits.W), s"get_next_state state=09 way=2: expected=11 actual=%d", get_next_states( 9)(2)) assert(get_next_states( 9)(3) === 9.U(plru.nBits.W), s"get_next_state state=09 way=3: expected=09 actual=%d", get_next_states( 9)(3)) assert(get_next_states( 9)(4) === 1.U(plru.nBits.W), s"get_next_state state=09 way=4: expected=01 actual=%d", get_next_states( 9)(4)) assert(get_next_states(10)(0) === 15.U(plru.nBits.W), s"get_next_state state=10 way=0: expected=15 actual=%d", get_next_states(10)(0)) assert(get_next_states(10)(1) === 14.U(plru.nBits.W), s"get_next_state state=10 way=1: expected=14 actual=%d", get_next_states(10)(1)) assert(get_next_states(10)(2) === 10.U(plru.nBits.W), s"get_next_state state=10 way=2: expected=10 actual=%d", get_next_states(10)(2)) assert(get_next_states(10)(3) === 8.U(plru.nBits.W), s"get_next_state state=10 way=3: expected=08 actual=%d", get_next_states(10)(3)) assert(get_next_states(10)(4) === 2.U(plru.nBits.W), s"get_next_state state=10 way=4: expected=02 actual=%d", get_next_states(10)(4)) assert(get_next_states(11)(0) === 15.U(plru.nBits.W), s"get_next_state state=11 way=0: expected=15 actual=%d", get_next_states(11)(0)) assert(get_next_states(11)(1) === 14.U(plru.nBits.W), s"get_next_state state=11 way=1: expected=14 actual=%d", get_next_states(11)(1)) assert(get_next_states(11)(2) === 11.U(plru.nBits.W), s"get_next_state state=11 way=2: expected=11 actual=%d", get_next_states(11)(2)) assert(get_next_states(11)(3) === 9.U(plru.nBits.W), s"get_next_state state=11 way=3: expected=09 actual=%d", get_next_states(11)(3)) assert(get_next_states(11)(4) === 3.U(plru.nBits.W), s"get_next_state state=11 way=4: expected=03 actual=%d", get_next_states(11)(4)) assert(get_next_states(12)(0) === 13.U(plru.nBits.W), s"get_next_state state=12 way=0: expected=13 actual=%d", get_next_states(12)(0)) assert(get_next_states(12)(1) === 12.U(plru.nBits.W), s"get_next_state state=12 way=1: expected=12 actual=%d", get_next_states(12)(1)) assert(get_next_states(12)(2) === 10.U(plru.nBits.W), s"get_next_state state=12 way=2: expected=10 actual=%d", get_next_states(12)(2)) assert(get_next_states(12)(3) === 8.U(plru.nBits.W), s"get_next_state state=12 way=3: expected=08 actual=%d", get_next_states(12)(3)) assert(get_next_states(12)(4) === 4.U(plru.nBits.W), s"get_next_state state=12 way=4: expected=04 actual=%d", get_next_states(12)(4)) assert(get_next_states(13)(0) === 13.U(plru.nBits.W), s"get_next_state state=13 way=0: expected=13 actual=%d", get_next_states(13)(0)) assert(get_next_states(13)(1) === 12.U(plru.nBits.W), s"get_next_state state=13 way=1: expected=12 actual=%d", get_next_states(13)(1)) assert(get_next_states(13)(2) === 11.U(plru.nBits.W), s"get_next_state state=13 way=2: expected=11 actual=%d", get_next_states(13)(2)) assert(get_next_states(13)(3) === 9.U(plru.nBits.W), s"get_next_state state=13 way=3: expected=09 actual=%d", get_next_states(13)(3)) assert(get_next_states(13)(4) === 5.U(plru.nBits.W), s"get_next_state state=13 way=4: expected=05 actual=%d", get_next_states(13)(4)) assert(get_next_states(14)(0) === 15.U(plru.nBits.W), s"get_next_state state=14 way=0: expected=15 actual=%d", get_next_states(14)(0)) assert(get_next_states(14)(1) === 14.U(plru.nBits.W), s"get_next_state state=14 way=1: expected=14 actual=%d", get_next_states(14)(1)) assert(get_next_states(14)(2) === 10.U(plru.nBits.W), s"get_next_state state=14 way=2: expected=10 actual=%d", get_next_states(14)(2)) assert(get_next_states(14)(3) === 8.U(plru.nBits.W), s"get_next_state state=14 way=3: expected=08 actual=%d", get_next_states(14)(3)) assert(get_next_states(14)(4) === 6.U(plru.nBits.W), s"get_next_state state=14 way=4: expected=06 actual=%d", get_next_states(14)(4)) assert(get_next_states(15)(0) === 15.U(plru.nBits.W), s"get_next_state state=15 way=0: expected=15 actual=%d", get_next_states(15)(0)) assert(get_next_states(15)(1) === 14.U(plru.nBits.W), s"get_next_state state=15 way=5: expected=14 actual=%d", get_next_states(15)(1)) assert(get_next_states(15)(2) === 11.U(plru.nBits.W), s"get_next_state state=15 way=2: expected=11 actual=%d", get_next_states(15)(2)) assert(get_next_states(15)(3) === 9.U(plru.nBits.W), s"get_next_state state=15 way=3: expected=09 actual=%d", get_next_states(15)(3)) assert(get_next_states(15)(4) === 7.U(plru.nBits.W), s"get_next_state state=15 way=4: expected=07 actual=%d", get_next_states(15)(4)) } case 6 => { assert(get_replace_ways( 0) === 0.U(log2Ceil(n_ways).W), s"get_replace_way state=00: expected=0 actual=%d", get_replace_ways( 0)) assert(get_replace_ways( 1) === 1.U(log2Ceil(n_ways).W), s"get_replace_way state=01: expected=1 actual=%d", get_replace_ways( 1)) assert(get_replace_ways( 2) === 0.U(log2Ceil(n_ways).W), s"get_replace_way state=02: expected=0 actual=%d", get_replace_ways( 2)) assert(get_replace_ways( 3) === 1.U(log2Ceil(n_ways).W), s"get_replace_way state=03: expected=1 actual=%d", get_replace_ways( 3)) assert(get_replace_ways( 4) === 2.U(log2Ceil(n_ways).W), s"get_replace_way state=04: expected=2 actual=%d", get_replace_ways( 4)) assert(get_replace_ways( 5) === 2.U(log2Ceil(n_ways).W), s"get_replace_way state=05: expected=2 actual=%d", get_replace_ways( 5)) assert(get_replace_ways( 6) === 3.U(log2Ceil(n_ways).W), s"get_replace_way state=06: expected=3 actual=%d", get_replace_ways( 6)) assert(get_replace_ways( 7) === 3.U(log2Ceil(n_ways).W), s"get_replace_way state=07: expected=3 actual=%d", get_replace_ways( 7)) assert(get_replace_ways( 8) === 0.U(log2Ceil(n_ways).W), s"get_replace_way state=08: expected=0 actual=%d", get_replace_ways( 8)) assert(get_replace_ways( 9) === 1.U(log2Ceil(n_ways).W), s"get_replace_way state=09: expected=1 actual=%d", get_replace_ways( 9)) assert(get_replace_ways(10) === 0.U(log2Ceil(n_ways).W), s"get_replace_way state=10: expected=0 actual=%d", get_replace_ways(10)) assert(get_replace_ways(11) === 1.U(log2Ceil(n_ways).W), s"get_replace_way state=11: expected=1 actual=%d", get_replace_ways(11)) assert(get_replace_ways(12) === 2.U(log2Ceil(n_ways).W), s"get_replace_way state=12: expected=2 actual=%d", get_replace_ways(12)) assert(get_replace_ways(13) === 2.U(log2Ceil(n_ways).W), s"get_replace_way state=13: expected=2 actual=%d", get_replace_ways(13)) assert(get_replace_ways(14) === 3.U(log2Ceil(n_ways).W), s"get_replace_way state=14: expected=3 actual=%d", get_replace_ways(14)) assert(get_replace_ways(15) === 3.U(log2Ceil(n_ways).W), s"get_replace_way state=15: expected=3 actual=%d", get_replace_ways(15)) assert(get_replace_ways(16) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=16: expected=4 actual=%d", get_replace_ways(16)) assert(get_replace_ways(17) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=17: expected=4 actual=%d", get_replace_ways(17)) assert(get_replace_ways(18) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=18: expected=4 actual=%d", get_replace_ways(18)) assert(get_replace_ways(19) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=19: expected=4 actual=%d", get_replace_ways(19)) assert(get_replace_ways(20) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=20: expected=4 actual=%d", get_replace_ways(20)) assert(get_replace_ways(21) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=21: expected=4 actual=%d", get_replace_ways(21)) assert(get_replace_ways(22) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=22: expected=4 actual=%d", get_replace_ways(22)) assert(get_replace_ways(23) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=23: expected=4 actual=%d", get_replace_ways(23)) assert(get_replace_ways(24) === 5.U(log2Ceil(n_ways).W), s"get_replace_way state=24: expected=5 actual=%d", get_replace_ways(24)) assert(get_replace_ways(25) === 5.U(log2Ceil(n_ways).W), s"get_replace_way state=25: expected=5 actual=%d", get_replace_ways(25)) assert(get_replace_ways(26) === 5.U(log2Ceil(n_ways).W), s"get_replace_way state=26: expected=5 actual=%d", get_replace_ways(26)) assert(get_replace_ways(27) === 5.U(log2Ceil(n_ways).W), s"get_replace_way state=27: expected=5 actual=%d", get_replace_ways(27)) assert(get_replace_ways(28) === 5.U(log2Ceil(n_ways).W), s"get_replace_way state=28: expected=5 actual=%d", get_replace_ways(28)) assert(get_replace_ways(29) === 5.U(log2Ceil(n_ways).W), s"get_replace_way state=29: expected=5 actual=%d", get_replace_ways(29)) assert(get_replace_ways(30) === 5.U(log2Ceil(n_ways).W), s"get_replace_way state=30: expected=5 actual=%d", get_replace_ways(30)) assert(get_replace_ways(31) === 5.U(log2Ceil(n_ways).W), s"get_replace_way state=31: expected=5 actual=%d", get_replace_ways(31)) } case _ => throw new IllegalArgumentException(s"no test pattern found for n_ways=$n_ways") } } File Consts.scala: // See LICENSE.Berkeley for license details. package freechips.rocketchip.rocket.constants import chisel3._ import chisel3.util._ import freechips.rocketchip.util._ trait ScalarOpConstants { val SZ_BR = 3 def BR_X = BitPat("b???") def BR_EQ = 0.U(3.W) def BR_NE = 1.U(3.W) def BR_J = 2.U(3.W) def BR_N = 3.U(3.W) def BR_LT = 4.U(3.W) def BR_GE = 5.U(3.W) def BR_LTU = 6.U(3.W) def BR_GEU = 7.U(3.W) def A1_X = BitPat("b??") def A1_ZERO = 0.U(2.W) def A1_RS1 = 1.U(2.W) def A1_PC = 2.U(2.W) def A1_RS1SHL = 3.U(2.W) def IMM_X = BitPat("b???") def IMM_S = 0.U(3.W) def IMM_SB = 1.U(3.W) def IMM_U = 2.U(3.W) def IMM_UJ = 3.U(3.W) def IMM_I = 4.U(3.W) def IMM_Z = 5.U(3.W) def A2_X = BitPat("b???") def A2_ZERO = 0.U(3.W) def A2_SIZE = 1.U(3.W) def A2_RS2 = 2.U(3.W) def A2_IMM = 3.U(3.W) def A2_RS2OH = 4.U(3.W) def A2_IMMOH = 5.U(3.W) def X = BitPat("b?") def N = BitPat("b0") def Y = BitPat("b1") val SZ_DW = 1 def DW_X = X def DW_32 = false.B def DW_64 = true.B def DW_XPR = DW_64 } trait MemoryOpConstants { val NUM_XA_OPS = 9 val M_SZ = 5 def M_X = BitPat("b?????"); def M_XRD = "b00000".U; // int load def M_XWR = "b00001".U; // int store def M_PFR = "b00010".U; // prefetch with intent to read def M_PFW = "b00011".U; // prefetch with intent to write def M_XA_SWAP = "b00100".U def M_FLUSH_ALL = "b00101".U // flush all lines def M_XLR = "b00110".U def M_XSC = "b00111".U def M_XA_ADD = "b01000".U def M_XA_XOR = "b01001".U def M_XA_OR = "b01010".U def M_XA_AND = "b01011".U def M_XA_MIN = "b01100".U def M_XA_MAX = "b01101".U def M_XA_MINU = "b01110".U def M_XA_MAXU = "b01111".U def M_FLUSH = "b10000".U // write back dirty data and cede R/W permissions def M_PWR = "b10001".U // partial (masked) store def M_PRODUCE = "b10010".U // write back dirty data and cede W permissions def M_CLEAN = "b10011".U // write back dirty data and retain R/W permissions def M_SFENCE = "b10100".U // SFENCE.VMA def M_HFENCEV = "b10101".U // HFENCE.VVMA def M_HFENCEG = "b10110".U // HFENCE.GVMA def M_WOK = "b10111".U // check write permissions but don't perform a write def M_HLVX = "b10000".U // HLVX instruction def isAMOLogical(cmd: UInt) = cmd.isOneOf(M_XA_SWAP, M_XA_XOR, M_XA_OR, M_XA_AND) def isAMOArithmetic(cmd: UInt) = cmd.isOneOf(M_XA_ADD, M_XA_MIN, M_XA_MAX, M_XA_MINU, M_XA_MAXU) def isAMO(cmd: UInt) = isAMOLogical(cmd) \|\| isAMOArithmetic(cmd) def isPrefetch(cmd: UInt) = cmd === M_PFR \|\| cmd === M_PFW def isRead(cmd: UInt) = cmd.isOneOf(M_XRD, M_HLVX, M_XLR, M_XSC) \|\| isAMO(cmd) def isWrite(cmd: UInt) = cmd === M_XWR \|\| cmd === M_PWR \|\| cmd === M_XSC \|\| isAMO(cmd) def isWriteIntent(cmd: UInt) = isWrite(cmd) \|\| cmd === M_PFW \|\| cmd === M_XLR } File TLB.scala: // See LICENSE.SiFive for license details. // See LICENSE.Berkeley for license details. package freechips.rocketchip.rocket import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config._ import freechips.rocketchip.devices.debug.DebugModuleKey import freechips.rocketchip.diplomacy.RegionType import freechips.rocketchip.subsystem.CacheBlockBytes import freechips.rocketchip.tile.{CoreModule, CoreBundle} import freechips.rocketchip.tilelink._ import freechips.rocketchip.util.{OptimizationBarrier, SetAssocLRU, PseudoLRU, PopCountAtLeast, property} import freechips.rocketchip.util.BooleanToAugmentedBoolean import freechips.rocketchip.util.IntToAugmentedInt import freechips.rocketchip.util.UIntToAugmentedUInt import freechips.rocketchip.util.UIntIsOneOf import freechips.rocketchip.util.SeqToAugmentedSeq import freechips.rocketchip.util.SeqBoolBitwiseOps case object ASIdBits extends Field[Int](0) case object VMIdBits extends Field[Int](0) /* =SFENCE= * rs1 rs2 * {{{ * 0 0 -> flush All * 0 1 -> flush by ASID * 1 1 -> flush by ADDR * 1 0 -> flush by ADDR and ASID * }}} * {{{ * If rs1=x0 and rs2=x0, the fence orders all reads and writes made to any level of the page tables, for all address spaces. * If rs1=x0 and rs2!=x0, the fence orders all reads and writes made to any level of the page tables, but only for the address space identified by integer register rs2. Accesses to global mappings (see Section 4.3.1) are not ordered. * If rs1!=x0 and rs2=x0, the fence orders only reads and writes made to the leaf page table entry corresponding to the virtual address in rs1, for all address spaces. * If rs1!=x0 and rs2!=x0, the fence orders only reads and writes made to the leaf page table entry corresponding to the virtual address in rs1, for the address space identified by integer register rs2. Accesses to global mappings are not ordered. * }}} / class SFenceReq(implicit p: Parameters) extends CoreBundle()(p) { val rs1 = Bool() val rs2 = Bool() val addr = UInt(vaddrBits.W) val asid = UInt((asIdBits max 1).W) // TODO zero-width val hv = Bool() val hg = Bool() } class TLBReq(lgMaxSize: Int)(implicit p: Parameters) extends CoreBundle()(p) { /* request address from CPU. / val vaddr = UInt(vaddrBitsExtended.W) /* don't lookup TLB, bypass vaddr as paddr / val passthrough = Bool() /* granularity / val size = UInt(log2Ceil(lgMaxSize + 1).W) /* memory command. / val cmd = Bits(M_SZ.W) val prv = UInt(PRV.SZ.W) /* virtualization mode / val v = Bool() } class TLBExceptions extends Bundle { val ld = Bool() val st = Bool() val inst = Bool() } class TLBResp(lgMaxSize: Int = 3)(implicit p: Parameters) extends CoreBundle()(p) { // lookup responses val miss = Bool() /* physical address / val paddr = UInt(paddrBits.W) val gpa = UInt(vaddrBitsExtended.W) val gpa_is_pte = Bool() /* page fault exception / val pf = new TLBExceptions /* guest page fault exception / val gf = new TLBExceptions /* access exception / val ae = new TLBExceptions /* misaligned access exception / val ma = new TLBExceptions /* if this address is cacheable / val cacheable = Bool() /* if caches must allocate this address / val must_alloc = Bool() /* if this address is prefetchable for caches/ val prefetchable = Bool() /* size/cmd of request that generated this response/ val size = UInt(log2Ceil(lgMaxSize + 1).W) val cmd = UInt(M_SZ.W) } class TLBEntryData(implicit p: Parameters) extends CoreBundle()(p) { val ppn = UInt(ppnBits.W) /* pte.u user / val u = Bool() /* pte.g global / val g = Bool() /* access exception. * D$ -> PTW -> TLB AE * Alignment failed. / val ae_ptw = Bool() val ae_final = Bool() val ae_stage2 = Bool() /* page fault / val pf = Bool() /* guest page fault / val gf = Bool() /* supervisor write / val sw = Bool() /* supervisor execute / val sx = Bool() /* supervisor read / val sr = Bool() /* hypervisor write / val hw = Bool() /* hypervisor excute / val hx = Bool() /* hypervisor read / val hr = Bool() /* prot_w / val pw = Bool() /* prot_x / val px = Bool() /* prot_r / val pr = Bool() /* PutPartial / val ppp = Bool() /* AMO logical / val pal = Bool() /* AMO arithmetic / val paa = Bool() /* get/put effects / val eff = Bool() /* cacheable / val c = Bool() /* fragmented_superpage support / val fragmented_superpage = Bool() } /* basic cell for TLB data / class TLBEntry(val nSectors: Int, val superpage: Boolean, val superpageOnly: Boolean)(implicit p: Parameters) extends CoreBundle()(p) { require(nSectors == 1 \|\| !superpage) require(!superpageOnly \|\| superpage) val level = UInt(log2Ceil(pgLevels).W) /* use vpn as tag / val tag_vpn = UInt(vpnBits.W) /* tag in vitualization mode / val tag_v = Bool() /* entry data / val data = Vec(nSectors, UInt(new TLBEntryData().getWidth.W)) /* valid bit / val valid = Vec(nSectors, Bool()) /* returns all entry data in this entry / def entry_data = data.map(_.asTypeOf(new TLBEntryData)) /* returns the index of sector / private def sectorIdx(vpn: UInt) = vpn.extract(nSectors.log2-1, 0) /* returns the entry data matched with this vpn/ def getData(vpn: UInt) = OptimizationBarrier(data(sectorIdx(vpn)).asTypeOf(new TLBEntryData)) /* returns whether a sector hits / def sectorHit(vpn: UInt, virtual: Bool) = valid.orR && sectorTagMatch(vpn, virtual) /* returns whether tag matches vpn / def sectorTagMatch(vpn: UInt, virtual: Bool) = (((tag_vpn ^ vpn) >> nSectors.log2) === 0.U) && (tag_v === virtual) /* returns hit signal / def hit(vpn: UInt, virtual: Bool): Bool = { if (superpage && usingVM) { var tagMatch = valid.head && (tag_v === virtual) for (j <- 0 until pgLevels) { val base = (pgLevels - 1 - j) pgLevelBits val n = pgLevelBits + (if (j == 0) hypervisorExtraAddrBits else 0) val ignore = level < j.U \|\| (superpageOnly && j == pgLevels - 1).B tagMatch = tagMatch && (ignore \|\| (tag_vpn ^ vpn)(base + n - 1, base) === 0.U) } tagMatch } else { val idx = sectorIdx(vpn) valid(idx) && sectorTagMatch(vpn, virtual) } } /** returns the ppn of the input TLBEntryData / def ppn(vpn: UInt, data: TLBEntryData) = { val supervisorVPNBits = pgLevels pgLevelBits if (superpage && usingVM) { var res = data.ppn >> pgLevelBits(pgLevels - 1) for (j <- 1 until pgLevels) { val ignore = level < j.U \|\| (superpageOnly && j == pgLevels - 1).B res = Cat(res, (Mux(ignore, vpn, 0.U) \| data.ppn)(supervisorVPNBits - jpgLevelBits - 1, supervisorVPNBits - (j + 1)pgLevelBits)) } res } else { data.ppn } } /* does the refill * * find the target entry with vpn tag * and replace the target entry with the input entry data / def insert(vpn: UInt, virtual: Bool, level: UInt, entry: TLBEntryData): Unit = { this.tag_vpn := vpn this.tag_v := virtual this.level := level.extract(log2Ceil(pgLevels - superpageOnly.toInt)-1, 0) val idx = sectorIdx(vpn) valid(idx) := true.B data(idx) := entry.asUInt } def invalidate(): Unit = { valid.foreach(_ := false.B) } def invalidate(virtual: Bool): Unit = { for ((v, e) <- valid zip entry_data) when (tag_v === virtual) { v := false.B } } def invalidateVPN(vpn: UInt, virtual: Bool): Unit = { if (superpage) { when (hit(vpn, virtual)) { invalidate() } } else { when (sectorTagMatch(vpn, virtual)) { for (((v, e), i) <- (valid zip entry_data).zipWithIndex) when (tag_v === virtual && i.U === sectorIdx(vpn)) { v := false.B } } } // For fragmented superpage mappings, we assume the worst (largest) // case, and zap entries whose most-significant VPNs match when (((tag_vpn ^ vpn) >> (pgLevelBits (pgLevels - 1))) === 0.U) { for ((v, e) <- valid zip entry_data) when (tag_v === virtual && e.fragmented_superpage) { v := false.B } } } def invalidateNonGlobal(virtual: Bool): Unit = { for ((v, e) <- valid zip entry_data) when (tag_v === virtual && !e.g) { v := false.B } } } /** TLB config * * @param nSets the number of sets of PTE, follow [[ICacheParams.nSets]] * @param nWays the total number of wayss of PTE, follow [[ICacheParams.nWays]] * @param nSectors the number of ways in a single PTE TLBEntry * @param nSuperpageEntries the number of SuperpageEntries / case class TLBConfig( nSets: Int, nWays: Int, nSectors: Int = 4, nSuperpageEntries: Int = 4) /* =Overview= * [[TLB]] is a TLB template which contains PMA logic and PMP checker. * * TLB caches PTE and accelerates the address translation process. * When tlb miss happens, ask PTW(L2TLB) for Page Table Walk. * Perform PMP and PMA check during the translation and throw exception if there were any. * * ==Cache Structure== * - Sectored Entry (PTE) * - set-associative or direct-mapped * - nsets = [[TLBConfig.nSets]] * - nways = [[TLBConfig.nWays]] / [[TLBConfig.nSectors]] * - PTEEntry( sectors = [[TLBConfig.nSectors]] ) * - LRU(if set-associative) * * - Superpage Entry(superpage PTE) * - fully associative * - nsets = [[TLBConfig.nSuperpageEntries]] * - PTEEntry(sectors = 1) * - PseudoLRU * * - Special Entry(PTE across PMP) * - nsets = 1 * - PTEEntry(sectors = 1) * * ==Address structure== * {{{ * \|vaddr \| * \|ppn/vpn \| pgIndex \| * \| \| \| * \| \|nSets \|nSector \| \|}}} * * ==State Machine== * {{{ * s_ready: ready to accept request from CPU. * s_request: when L1TLB(this) miss, send request to PTW(L2TLB), . * s_wait: wait for PTW to refill L1TLB. * s_wait_invalidate: L1TLB is waiting for respond from PTW, but L1TLB will invalidate respond from PTW.}}} * * ==PMP== * pmp check * - special_entry: always check * - other entry: check on refill * * ==Note== * PMA consume diplomacy parameter generate physical memory address checking logic * * Boom use Rocket ITLB, and its own DTLB. * * Accelerators:{{{ * sha3: DTLB * gemmini: DTLB * hwacha: DTLB2+ITLB}}} @param instruction true for ITLB, false for DTLB * @param lgMaxSize @todo seems granularity * @param cfg [[TLBConfig]] * @param edge collect SoC metadata. / class TLB(instruction: Boolean, lgMaxSize: Int, cfg: TLBConfig)(implicit edge: TLEdgeOut, p: Parameters) extends CoreModule()(p) { override def desiredName = if (instruction) "ITLB" else "DTLB" val io = IO(new Bundle { /* request from Core / val req = Flipped(Decoupled(new TLBReq(lgMaxSize))) /* response to Core / val resp = Output(new TLBResp(lgMaxSize)) /* SFence Input / val sfence = Flipped(Valid(new SFenceReq)) /* IO to PTW / val ptw = new TLBPTWIO /* suppress a TLB refill, one cycle after a miss / val kill = Input(Bool()) }) io.ptw.customCSRs := DontCare val pageGranularityPMPs = pmpGranularity >= (1 << pgIdxBits) val vpn = io.req.bits.vaddr(vaddrBits-1, pgIdxBits) /* index for sectored_Entry / val memIdx = vpn.extract(cfg.nSectors.log2 + cfg.nSets.log2 - 1, cfg.nSectors.log2) /* TLB Entry / val sectored_entries = Reg(Vec(cfg.nSets, Vec(cfg.nWays / cfg.nSectors, new TLBEntry(cfg.nSectors, false, false)))) /* Superpage Entry / val superpage_entries = Reg(Vec(cfg.nSuperpageEntries, new TLBEntry(1, true, true))) /* Special Entry * * If PMP granularity is less than page size, thus need additional "special" entry manage PMP. / val special_entry = (!pageGranularityPMPs).option(Reg(new TLBEntry(1, true, false))) def ordinary_entries = sectored_entries(memIdx) ++ superpage_entries def all_entries = ordinary_entries ++ special_entry def all_real_entries = sectored_entries.flatten ++ superpage_entries ++ special_entry val s_ready :: s_request :: s_wait :: s_wait_invalidate :: Nil = Enum(4) val state = RegInit(s_ready) // use vpn as refill_tag val r_refill_tag = Reg(UInt(vpnBits.W)) val r_superpage_repl_addr = Reg(UInt(log2Ceil(superpage_entries.size).W)) val r_sectored_repl_addr = Reg(UInt(log2Ceil(sectored_entries.head.size).W)) val r_sectored_hit = Reg(Valid(UInt(log2Ceil(sectored_entries.head.size).W))) val r_superpage_hit = Reg(Valid(UInt(log2Ceil(superpage_entries.size).W))) val r_vstage1_en = Reg(Bool()) val r_stage2_en = Reg(Bool()) val r_need_gpa = Reg(Bool()) val r_gpa_valid = Reg(Bool()) val r_gpa = Reg(UInt(vaddrBits.W)) val r_gpa_vpn = Reg(UInt(vpnBits.W)) val r_gpa_is_pte = Reg(Bool()) /* privilege mode / val priv = io.req.bits.prv val priv_v = usingHypervisor.B && io.req.bits.v val priv_s = priv(0) // user mode and supervisor mode val priv_uses_vm = priv <= PRV.S.U val satp = Mux(priv_v, io.ptw.vsatp, io.ptw.ptbr) val stage1_en = usingVM.B && satp.mode(satp.mode.getWidth-1) /* VS-stage translation enable / val vstage1_en = usingHypervisor.B && priv_v && io.ptw.vsatp.mode(io.ptw.vsatp.mode.getWidth-1) /* G-stage translation enable / val stage2_en = usingHypervisor.B && priv_v && io.ptw.hgatp.mode(io.ptw.hgatp.mode.getWidth-1) /* Enable Virtual Memory when: * 1. statically configured * 1. satp highest bits enabled * i. RV32: * - 0 -> Bare * - 1 -> SV32 * i. RV64: * - 0000 -> Bare * - 1000 -> SV39 * - 1001 -> SV48 * - 1010 -> SV57 * - 1011 -> SV64 * 1. In virtualization mode, vsatp highest bits enabled * 1. priv mode in U and S. * 1. in H & M mode, disable VM. * 1. no passthrough(micro-arch defined.) * * @see RV-priv spec 4.1.11 Supervisor Address Translation and Protection (satp) Register * @see RV-priv spec 8.2.18 Virtual Supervisor Address Translation and Protection Register (vsatp) / val vm_enabled = (stage1_en \|\| stage2_en) && priv_uses_vm && !io.req.bits.passthrough // flush guest entries on vsatp.MODE Bare <-> SvXX transitions val v_entries_use_stage1 = RegInit(false.B) val vsatp_mode_mismatch = priv_v && (vstage1_en =/= v_entries_use_stage1) && !io.req.bits.passthrough // share a single physical memory attribute checker (unshare if critical path) val refill_ppn = io.ptw.resp.bits.pte.ppn(ppnBits-1, 0) /* refill signal / val do_refill = usingVM.B && io.ptw.resp.valid /* sfence invalidate refill / val invalidate_refill = state.isOneOf(s_request / don't care /, s_wait_invalidate) \|\| io.sfence.valid // PMP val mpu_ppn = Mux(do_refill, refill_ppn, Mux(vm_enabled && special_entry.nonEmpty.B, special_entry.map(e => e.ppn(vpn, e.getData(vpn))).getOrElse(0.U), io.req.bits.vaddr >> pgIdxBits)) val mpu_physaddr = Cat(mpu_ppn, io.req.bits.vaddr(pgIdxBits-1, 0)) val mpu_priv = Mux[UInt](usingVM.B && (do_refill \|\| io.req.bits.passthrough / PTW /), PRV.S.U, Cat(io.ptw.status.debug, priv)) val pmp = Module(new PMPChecker(lgMaxSize)) pmp.io.addr := mpu_physaddr pmp.io.size := io.req.bits.size pmp.io.pmp := (io.ptw.pmp: Seq[PMP]) pmp.io.prv := mpu_priv val pma = Module(new PMAChecker(edge.manager)(p)) pma.io.paddr := mpu_physaddr // todo: using DataScratchpad doesn't support cacheable. val cacheable = pma.io.resp.cacheable && (instruction \|\| !usingDataScratchpad).B val homogeneous = TLBPageLookup(edge.manager.managers, xLen, p(CacheBlockBytes), BigInt(1) << pgIdxBits, 1 << lgMaxSize)(mpu_physaddr).homogeneous // In M mode, if access DM address(debug module program buffer) val deny_access_to_debug = mpu_priv <= PRV.M.U && p(DebugModuleKey).map(dmp => dmp.address.contains(mpu_physaddr)).getOrElse(false.B) val prot_r = pma.io.resp.r && !deny_access_to_debug && pmp.io.r val prot_w = pma.io.resp.w && !deny_access_to_debug && pmp.io.w val prot_pp = pma.io.resp.pp val prot_al = pma.io.resp.al val prot_aa = pma.io.resp.aa val prot_x = pma.io.resp.x && !deny_access_to_debug && pmp.io.x val prot_eff = pma.io.resp.eff // hit check val sector_hits = sectored_entries(memIdx).map(_.sectorHit(vpn, priv_v)) val superpage_hits = superpage_entries.map(_.hit(vpn, priv_v)) val hitsVec = all_entries.map(vm_enabled && _.hit(vpn, priv_v)) val real_hits = hitsVec.asUInt val hits = Cat(!vm_enabled, real_hits) // use ptw response to refill // permission bit arrays when (do_refill) { val pte = io.ptw.resp.bits.pte val refill_v = r_vstage1_en \|\| r_stage2_en val newEntry = Wire(new TLBEntryData) newEntry.ppn := pte.ppn newEntry.c := cacheable newEntry.u := pte.u newEntry.g := pte.g && pte.v newEntry.ae_ptw := io.ptw.resp.bits.ae_ptw newEntry.ae_final := io.ptw.resp.bits.ae_final newEntry.ae_stage2 := io.ptw.resp.bits.ae_final && io.ptw.resp.bits.gpa_is_pte && r_stage2_en newEntry.pf := io.ptw.resp.bits.pf newEntry.gf := io.ptw.resp.bits.gf newEntry.hr := io.ptw.resp.bits.hr newEntry.hw := io.ptw.resp.bits.hw newEntry.hx := io.ptw.resp.bits.hx newEntry.sr := pte.sr() newEntry.sw := pte.sw() newEntry.sx := pte.sx() newEntry.pr := prot_r newEntry.pw := prot_w newEntry.px := prot_x newEntry.ppp := prot_pp newEntry.pal := prot_al newEntry.paa := prot_aa newEntry.eff := prot_eff newEntry.fragmented_superpage := io.ptw.resp.bits.fragmented_superpage // refill special_entry when (special_entry.nonEmpty.B && !io.ptw.resp.bits.homogeneous) { special_entry.foreach(_.insert(r_refill_tag, refill_v, io.ptw.resp.bits.level, newEntry)) }.elsewhen (io.ptw.resp.bits.level < (pgLevels-1).U) { val waddr = Mux(r_superpage_hit.valid && usingHypervisor.B, r_superpage_hit.bits, r_superpage_repl_addr) for ((e, i) <- superpage_entries.zipWithIndex) when (r_superpage_repl_addr === i.U) { e.insert(r_refill_tag, refill_v, io.ptw.resp.bits.level, newEntry) when (invalidate_refill) { e.invalidate() } } // refill sectored_hit }.otherwise { val r_memIdx = r_refill_tag.extract(cfg.nSectors.log2 + cfg.nSets.log2 - 1, cfg.nSectors.log2) val waddr = Mux(r_sectored_hit.valid, r_sectored_hit.bits, r_sectored_repl_addr) for ((e, i) <- sectored_entries(r_memIdx).zipWithIndex) when (waddr === i.U) { when (!r_sectored_hit.valid) { e.invalidate() } e.insert(r_refill_tag, refill_v, 0.U, newEntry) when (invalidate_refill) { e.invalidate() } } } r_gpa_valid := io.ptw.resp.bits.gpa.valid r_gpa := io.ptw.resp.bits.gpa.bits r_gpa_is_pte := io.ptw.resp.bits.gpa_is_pte } // get all entries data. val entries = all_entries.map(_.getData(vpn)) val normal_entries = entries.take(ordinary_entries.size) // parallel query PPN from [[all_entries]], if VM not enabled return VPN instead val ppn = Mux1H(hitsVec :+ !vm_enabled, (all_entries zip entries).map{ case (entry, data) => entry.ppn(vpn, data) } :+ vpn(ppnBits-1, 0)) val nPhysicalEntries = 1 + special_entry.size // generally PTW misaligned load exception. val ptw_ae_array = Cat(false.B, entries.map(_.ae_ptw).asUInt) val final_ae_array = Cat(false.B, entries.map(_.ae_final).asUInt) val ptw_pf_array = Cat(false.B, entries.map(_.pf).asUInt) val ptw_gf_array = Cat(false.B, entries.map(_.gf).asUInt) val sum = Mux(priv_v, io.ptw.gstatus.sum, io.ptw.status.sum) // if in hypervisor/machine mode, cannot read/write user entries. // if in superviosr/user mode, "If the SUM bit in the sstatus register is set, supervisor mode software may also access pages with U=1.(from spec)" val priv_rw_ok = Mux(!priv_s \|\| sum, entries.map(_.u).asUInt, 0.U) \| Mux(priv_s, ~entries.map(_.u).asUInt, 0.U) // if in hypervisor/machine mode, other than user pages, all pages are executable. // if in superviosr/user mode, only user page can execute. val priv_x_ok = Mux(priv_s, ~entries.map(_.u).asUInt, entries.map(_.u).asUInt) val stage1_bypass = Fill(entries.size, usingHypervisor.B) & (Fill(entries.size, !stage1_en) \| entries.map(_.ae_stage2).asUInt) val mxr = io.ptw.status.mxr \| Mux(priv_v, io.ptw.gstatus.mxr, false.B) // "The vsstatus field MXR, which makes execute-only pages readable, only overrides VS-stage page protection.(from spec)" val r_array = Cat(true.B, (priv_rw_ok & (entries.map(_.sr).asUInt \| Mux(mxr, entries.map(_.sx).asUInt, 0.U))) \| stage1_bypass) val w_array = Cat(true.B, (priv_rw_ok & entries.map(_.sw).asUInt) \| stage1_bypass) val x_array = Cat(true.B, (priv_x_ok & entries.map(_.sx).asUInt) \| stage1_bypass) val stage2_bypass = Fill(entries.size, !stage2_en) val hr_array = Cat(true.B, entries.map(_.hr).asUInt \| Mux(io.ptw.status.mxr, entries.map(_.hx).asUInt, 0.U) \| stage2_bypass) val hw_array = Cat(true.B, entries.map(_.hw).asUInt \| stage2_bypass) val hx_array = Cat(true.B, entries.map(_.hx).asUInt \| stage2_bypass) // These array is for each TLB entries. // user mode can read: PMA OK, TLB OK, AE OK val pr_array = Cat(Fill(nPhysicalEntries, prot_r), normal_entries.map(_.pr).asUInt) & ~(ptw_ae_array \| final_ae_array) // user mode can write: PMA OK, TLB OK, AE OK val pw_array = Cat(Fill(nPhysicalEntries, prot_w), normal_entries.map(_.pw).asUInt) & ~(ptw_ae_array \| final_ae_array) // user mode can write: PMA OK, TLB OK, AE OK val px_array = Cat(Fill(nPhysicalEntries, prot_x), normal_entries.map(_.px).asUInt) & ~(ptw_ae_array \| final_ae_array) // put effect val eff_array = Cat(Fill(nPhysicalEntries, prot_eff), normal_entries.map(_.eff).asUInt) // cacheable val c_array = Cat(Fill(nPhysicalEntries, cacheable), normal_entries.map(_.c).asUInt) // put partial val ppp_array = Cat(Fill(nPhysicalEntries, prot_pp), normal_entries.map(_.ppp).asUInt) // atomic arithmetic val paa_array = Cat(Fill(nPhysicalEntries, prot_aa), normal_entries.map(_.paa).asUInt) // atomic logic val pal_array = Cat(Fill(nPhysicalEntries, prot_al), normal_entries.map(_.pal).asUInt) val ppp_array_if_cached = ppp_array \| c_array val paa_array_if_cached = paa_array \| (if(usingAtomicsInCache) c_array else 0.U) val pal_array_if_cached = pal_array \| (if(usingAtomicsInCache) c_array else 0.U) val prefetchable_array = Cat((cacheable && homogeneous) << (nPhysicalEntries-1), normal_entries.map(_.c).asUInt) // vaddr misaligned: vaddr[1:0]=b00 val misaligned = (io.req.bits.vaddr & (UIntToOH(io.req.bits.size) - 1.U)).orR def badVA(guestPA: Boolean): Bool = { val additionalPgLevels = (if (guestPA) io.ptw.hgatp else satp).additionalPgLevels val extraBits = if (guestPA) hypervisorExtraAddrBits else 0 val signed = !guestPA val nPgLevelChoices = pgLevels - minPgLevels + 1 val minVAddrBits = pgIdxBits + minPgLevels pgLevelBits + extraBits (for (i <- 0 until nPgLevelChoices) yield { val mask = ((BigInt(1) << vaddrBitsExtended) - (BigInt(1) << (minVAddrBits + i * pgLevelBits - signed.toInt))).U val maskedVAddr = io.req.bits.vaddr & mask additionalPgLevels === i.U && !(maskedVAddr === 0.U \|\| signed.B && maskedVAddr === mask) }).orR } val bad_gpa = if (!usingHypervisor) false.B else vm_enabled && !stage1_en && badVA(true) val bad_va = if (!usingVM \|\| (minPgLevels == pgLevels && vaddrBits == vaddrBitsExtended)) false.B else vm_enabled && stage1_en && badVA(false) val cmd_lrsc = usingAtomics.B && io.req.bits.cmd.isOneOf(M_XLR, M_XSC) val cmd_amo_logical = usingAtomics.B && isAMOLogical(io.req.bits.cmd) val cmd_amo_arithmetic = usingAtomics.B && isAMOArithmetic(io.req.bits.cmd) val cmd_put_partial = io.req.bits.cmd === M_PWR val cmd_read = isRead(io.req.bits.cmd) val cmd_readx = usingHypervisor.B && io.req.bits.cmd === M_HLVX val cmd_write = isWrite(io.req.bits.cmd) val cmd_write_perms = cmd_write \|\| io.req.bits.cmd.isOneOf(M_FLUSH_ALL, M_WOK) // not a write, but needs write permissions val lrscAllowed = Mux((usingDataScratchpad \|\| usingAtomicsOnlyForIO).B, 0.U, c_array) val ae_array = Mux(misaligned, eff_array, 0.U) \| Mux(cmd_lrsc, ~lrscAllowed, 0.U) // access exception needs SoC information from PMA val ae_ld_array = Mux(cmd_read, ae_array \| ~pr_array, 0.U) val ae_st_array = Mux(cmd_write_perms, ae_array \| ~pw_array, 0.U) \| Mux(cmd_put_partial, ~ppp_array_if_cached, 0.U) \| Mux(cmd_amo_logical, ~pal_array_if_cached, 0.U) \| Mux(cmd_amo_arithmetic, ~paa_array_if_cached, 0.U) val must_alloc_array = Mux(cmd_put_partial, ~ppp_array, 0.U) \| Mux(cmd_amo_logical, ~pal_array, 0.U) \| Mux(cmd_amo_arithmetic, ~paa_array, 0.U) \| Mux(cmd_lrsc, ~0.U(pal_array.getWidth.W), 0.U) val pf_ld_array = Mux(cmd_read, ((~Mux(cmd_readx, x_array, r_array) & ~ptw_ae_array) \| ptw_pf_array) & ~ptw_gf_array, 0.U) val pf_st_array = Mux(cmd_write_perms, ((~w_array & ~ptw_ae_array) \| ptw_pf_array) & ~ptw_gf_array, 0.U) val pf_inst_array = ((~x_array & ~ptw_ae_array) \| ptw_pf_array) & ~ptw_gf_array val gf_ld_array = Mux(priv_v && cmd_read, (~Mux(cmd_readx, hx_array, hr_array) \| ptw_gf_array) & ~ptw_ae_array, 0.U) val gf_st_array = Mux(priv_v && cmd_write_perms, (~hw_array \| ptw_gf_array) & ~ptw_ae_array, 0.U) val gf_inst_array = Mux(priv_v, (~hx_array \| ptw_gf_array) & ~ptw_ae_array, 0.U) val gpa_hits = { val need_gpa_mask = if (instruction) gf_inst_array else gf_ld_array \| gf_st_array val hit_mask = Fill(ordinary_entries.size, r_gpa_valid && r_gpa_vpn === vpn) \| Fill(all_entries.size, !vstage1_en) hit_mask \| ~need_gpa_mask(all_entries.size-1, 0) } val tlb_hit_if_not_gpa_miss = real_hits.orR val tlb_hit = (real_hits & gpa_hits).orR // leads to s_request val tlb_miss = vm_enabled && !vsatp_mode_mismatch && !bad_va && !tlb_hit val sectored_plru = new SetAssocLRU(cfg.nSets, sectored_entries.head.size, "plru") val superpage_plru = new PseudoLRU(superpage_entries.size) when (io.req.valid && vm_enabled) { // replace when (sector_hits.orR) { sectored_plru.access(memIdx, OHToUInt(sector_hits)) } when (superpage_hits.orR) { superpage_plru.access(OHToUInt(superpage_hits)) } } // Superpages create the possibility that two entries in the TLB may match. // This corresponds to a software bug, but we can't return complete garbage; // we must return either the old translation or the new translation. This // isn't compatible with the Mux1H approach. So, flush the TLB and report // a miss on duplicate entries. val multipleHits = PopCountAtLeast(real_hits, 2) // only pull up req.ready when this is s_ready state. io.req.ready := state === s_ready // page fault io.resp.pf.ld := (bad_va && cmd_read) \|\| (pf_ld_array & hits).orR io.resp.pf.st := (bad_va && cmd_write_perms) \|\| (pf_st_array & hits).orR io.resp.pf.inst := bad_va \|\| (pf_inst_array & hits).orR // guest page fault io.resp.gf.ld := (bad_gpa && cmd_read) \|\| (gf_ld_array & hits).orR io.resp.gf.st := (bad_gpa && cmd_write_perms) \|\| (gf_st_array & hits).orR io.resp.gf.inst := bad_gpa \|\| (gf_inst_array & hits).orR // access exception io.resp.ae.ld := (ae_ld_array & hits).orR io.resp.ae.st := (ae_st_array & hits).orR io.resp.ae.inst := (~px_array & hits).orR // misaligned io.resp.ma.ld := misaligned && cmd_read io.resp.ma.st := misaligned && cmd_write io.resp.ma.inst := false.B // this is up to the pipeline to figure out io.resp.cacheable := (c_array & hits).orR io.resp.must_alloc := (must_alloc_array & hits).orR io.resp.prefetchable := (prefetchable_array & hits).orR && edge.manager.managers.forall(m => !m.supportsAcquireB \|\| m.supportsHint).B io.resp.miss := do_refill \|\| vsatp_mode_mismatch \|\| tlb_miss \|\| multipleHits io.resp.paddr := Cat(ppn, io.req.bits.vaddr(pgIdxBits-1, 0)) io.resp.size := io.req.bits.size io.resp.cmd := io.req.bits.cmd io.resp.gpa_is_pte := vstage1_en && r_gpa_is_pte io.resp.gpa := { val page = Mux(!vstage1_en, Cat(bad_gpa, vpn), r_gpa >> pgIdxBits) val offset = Mux(io.resp.gpa_is_pte, r_gpa(pgIdxBits-1, 0), io.req.bits.vaddr(pgIdxBits-1, 0)) Cat(page, offset) } io.ptw.req.valid := state === s_request io.ptw.req.bits.valid := !io.kill io.ptw.req.bits.bits.addr := r_refill_tag io.ptw.req.bits.bits.vstage1 := r_vstage1_en io.ptw.req.bits.bits.stage2 := r_stage2_en io.ptw.req.bits.bits.need_gpa := r_need_gpa if (usingVM) { when(io.ptw.req.fire && io.ptw.req.bits.valid) { r_gpa_valid := false.B r_gpa_vpn := r_refill_tag } val sfence = io.sfence.valid // this is [[s_ready]] // handle miss/hit at the first cycle. // if miss, request PTW(L2TLB). when (io.req.fire && tlb_miss) { state := s_request r_refill_tag := vpn r_need_gpa := tlb_hit_if_not_gpa_miss r_vstage1_en := vstage1_en r_stage2_en := stage2_en r_superpage_repl_addr := replacementEntry(superpage_entries, superpage_plru.way) r_sectored_repl_addr := replacementEntry(sectored_entries(memIdx), sectored_plru.way(memIdx)) r_sectored_hit.valid := sector_hits.orR r_sectored_hit.bits := OHToUInt(sector_hits) r_superpage_hit.valid := superpage_hits.orR r_superpage_hit.bits := OHToUInt(superpage_hits) } // Handle SFENCE.VMA when send request to PTW. // SFENCE.VMA io.ptw.req.ready kill // ? ? 1 // 0 0 0 // 0 1 0 -> s_wait // 1 0 0 -> s_wait_invalidate // 1 0 0 -> s_ready when (state === s_request) { // SFENCE.VMA will kill TLB entries based on rs1 and rs2. It will take 1 cycle. when (sfence) { state := s_ready } // here should be io.ptw.req.fire, but assert(io.ptw.req.ready === true.B) // fire -> s_wait when (io.ptw.req.ready) { state := Mux(sfence, s_wait_invalidate, s_wait) } // If CPU kills request(frontend.s2_redirect) when (io.kill) { state := s_ready } } // sfence in refill will results in invalidate when (state === s_wait && sfence) { state := s_wait_invalidate } // after CPU acquire response, go back to s_ready. when (io.ptw.resp.valid) { state := s_ready } // SFENCE processing logic. when (sfence) { assert(!io.sfence.bits.rs1 \|\| (io.sfence.bits.addr >> pgIdxBits) === vpn) for (e <- all_real_entries) { val hv = usingHypervisor.B && io.sfence.bits.hv val hg = usingHypervisor.B && io.sfence.bits.hg when (!hg && io.sfence.bits.rs1) { e.invalidateVPN(vpn, hv) } .elsewhen (!hg && io.sfence.bits.rs2) { e.invalidateNonGlobal(hv) } .otherwise { e.invalidate(hv \|\| hg) } } } when(io.req.fire && vsatp_mode_mismatch) { all_real_entries.foreach(_.invalidate(true.B)) v_entries_use_stage1 := vstage1_en } when (multipleHits \|\| reset.asBool) { all_real_entries.foreach(_.invalidate()) } ccover(io.ptw.req.fire, "MISS", "TLB miss") ccover(io.ptw.req.valid && !io.ptw.req.ready, "PTW_STALL", "TLB miss, but PTW busy") ccover(state === s_wait_invalidate, "SFENCE_DURING_REFILL", "flush TLB during TLB refill") ccover(sfence && !io.sfence.bits.rs1 && !io.sfence.bits.rs2, "SFENCE_ALL", "flush TLB") ccover(sfence && !io.sfence.bits.rs1 && io.sfence.bits.rs2, "SFENCE_ASID", "flush TLB ASID") ccover(sfence && io.sfence.bits.rs1 && !io.sfence.bits.rs2, "SFENCE_LINE", "flush TLB line") ccover(sfence && io.sfence.bits.rs1 && io.sfence.bits.rs2, "SFENCE_LINE_ASID", "flush TLB line/ASID") ccover(multipleHits, "MULTIPLE_HITS", "Two matching translations in TLB") } def ccover(cond: Bool, label: String, desc: String)(implicit sourceInfo: SourceInfo) = property.cover(cond, s"${if (instruction) "I" else "D"}TLB_$label", "MemorySystem;;" + desc) /** Decides which entry to be replaced * * If there is a invalid entry, replace it with priorityencoder; * if not, replace the alt entry * * @return mask for TLBEntry replacement / def replacementEntry(set: Seq[TLBEntry], alt: UInt) = { val valids = set.map(_.valid.orR).asUInt Mux(valids.andR, alt, PriorityEncoder(~valids)) } } File TLBPermissions.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.rocket import chisel3._ import chisel3.util._ import freechips.rocketchip.diplomacy.{AddressSet, TransferSizes, RegionType, AddressDecoder} import freechips.rocketchip.tilelink.TLManagerParameters case class TLBPermissions( homogeneous: Bool, // if false, the below are undefined r: Bool, // readable w: Bool, // writeable x: Bool, // executable c: Bool, // cacheable a: Bool, // arithmetic ops l: Bool) // logical ops object TLBPageLookup { private case class TLBFixedPermissions( e: Boolean, // get-/put-effects r: Boolean, // readable w: Boolean, // writeable x: Boolean, // executable c: Boolean, // cacheable a: Boolean, // arithmetic ops l: Boolean) { // logical ops val useful = r \|\| w \|\| x \|\| c \|\| a \|\| l } private def groupRegions(managers: Seq[TLManagerParameters]): Map[TLBFixedPermissions, Seq[AddressSet]] = { val permissions = managers.map { m => (m.address, TLBFixedPermissions( e = Seq(RegionType.PUT_EFFECTS, RegionType.GET_EFFECTS) contains m.regionType, r = m.supportsGet \|\| m.supportsAcquireB, // if cached, never uses Get w = m.supportsPutFull \|\| m.supportsAcquireT, // if cached, never uses Put x = m.executable, c = m.supportsAcquireB, a = m.supportsArithmetic, l = m.supportsLogical)) } permissions .filter(_._2.useful) // get rid of no-permission devices .groupBy(_._2) // group by permission type .mapValues(seq => AddressSet.unify(seq.flatMap(_._1))) // coalesce same-permission regions .toMap } // Unmapped memory is considered to be inhomogeneous def apply(managers: Seq[TLManagerParameters], xLen: Int, cacheBlockBytes: Int, pageSize: BigInt, maxRequestBytes: Int): UInt => TLBPermissions = { require (isPow2(xLen) && xLen >= 8) require (isPow2(cacheBlockBytes) && cacheBlockBytes >= xLen/8) require (isPow2(pageSize) && pageSize >= cacheBlockBytes) val xferSizes = TransferSizes(cacheBlockBytes, cacheBlockBytes) val allSizes = TransferSizes(1, maxRequestBytes) val amoSizes = TransferSizes(4, xLen/8) val permissions = managers.foreach { m => require (!m.supportsGet \|\| m.supportsGet .contains(allSizes), s"Memory region '${m.name}' at ${m.address} only supports ${m.supportsGet} Get, but must support ${allSizes}") require (!m.supportsPutFull \|\| m.supportsPutFull .contains(allSizes), s"Memory region '${m.name}' at ${m.address} only supports ${m.supportsPutFull} PutFull, but must support ${allSizes}") require (!m.supportsPutPartial \|\| m.supportsPutPartial.contains(allSizes), s"Memory region '${m.name}' at ${m.address} only supports ${m.supportsPutPartial} PutPartial, but must support ${allSizes}") require (!m.supportsAcquireB \|\| m.supportsAcquireB .contains(xferSizes), s"Memory region '${m.name}' at ${m.address} only supports ${m.supportsAcquireB} AcquireB, but must support ${xferSizes}") require (!m.supportsAcquireT \|\| m.supportsAcquireT .contains(xferSizes), s"Memory region '${m.name}' at ${m.address} only supports ${m.supportsAcquireT} AcquireT, but must support ${xferSizes}") require (!m.supportsLogical \|\| m.supportsLogical .contains(amoSizes), s"Memory region '${m.name}' at ${m.address} only supports ${m.supportsLogical} Logical, but must support ${amoSizes}") require (!m.supportsArithmetic \|\| m.supportsArithmetic.contains(amoSizes), s"Memory region '${m.name}' at ${m.address} only supports ${m.supportsArithmetic} Arithmetic, but must support ${amoSizes}") require (!(m.supportsAcquireB && m.supportsPutFull && !m.supportsAcquireT), s"Memory region '${m.name}' supports AcquireB (cached read) and PutFull (un-cached write) but not AcquireT (cached write)") } val grouped = groupRegions(managers) .mapValues(_.filter(_.alignment >= pageSize)) // discard any region that's not big enough def lowCostProperty(prop: TLBFixedPermissions => Boolean): UInt => Bool = { val (yesm, nom) = grouped.partition { case (k, eq) => prop(k) } val (yes, no) = (yesm.values.flatten.toList, nom.values.flatten.toList) // Find the minimal bits needed to distinguish between yes and no val decisionMask = AddressDecoder(Seq(yes, no)) def simplify(x: Seq[AddressSet]) = AddressSet.unify(x.map(_.widen(~decisionMask)).distinct) val (yesf, nof) = (simplify(yes), simplify(no)) if (yesf.size < no.size) { (x: UInt) => yesf.map(_.contains(x)).foldLeft(false.B)(_ \|\| _) } else { (x: UInt) => !nof.map(_.contains(x)).foldLeft(false.B)(_ \|\| _) } } // Derive simplified property circuits (don't care when !homo) val rfn = lowCostProperty(_.r) val wfn = lowCostProperty(_.w) val xfn = lowCostProperty(_.x) val cfn = lowCostProperty(_.c) val afn = lowCostProperty(_.a) val lfn = lowCostProperty(_.l) val homo = AddressSet.unify(grouped.values.flatten.toList) (x: UInt) => TLBPermissions( homogeneous = homo.map(_.contains(x)).foldLeft(false.B)(_ \|\| _), r = rfn(x), w = wfn(x), x = xfn(x), c = cfn(x), a = afn(x), l = lfn(x)) } // Are all pageSize intervals of mapped regions homogeneous? def homogeneous(managers: Seq[TLManagerParameters], pageSize: BigInt): Boolean = { groupRegions(managers).values.forall(_.forall(_.alignment >= pageSize)) } } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.diplomacy import chisel3._ import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor} import freechips.rocketchip.util.ShiftQueue /* Options for describing the attributes of memory regions / object RegionType { // Define the 'more relaxed than' ordering val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS) sealed trait T extends Ordered[T] { def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this) } case object CACHED extends T // an intermediate agent may have cached a copy of the region for you case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively } // A non-empty half-open range; [start, end) case class IdRange(start: Int, end: Int) extends Ordered[IdRange] { require (start >= 0, s"Ids cannot be negative, but got: $start.") require (start <= end, "Id ranges cannot be negative.") def compare(x: IdRange) = { val primary = (this.start - x.start).signum val secondary = (x.end - this.end).signum if (primary != 0) primary else secondary } def overlaps(x: IdRange) = start < x.end && x.start < end def contains(x: IdRange) = start <= x.start && x.end <= end def contains(x: Int) = start <= x && x < end def contains(x: UInt) = if (size == 0) { false.B } else if (size == 1) { // simple comparison x === start.U } else { // find index of largest different bit val largestDeltaBit = log2Floor(start ^ (end-1)) val smallestCommonBit = largestDeltaBit + 1 // may not exist in x val uncommonMask = (1 << smallestCommonBit) - 1 val uncommonBits = (x \| 0.U(smallestCommonBit.W))(largestDeltaBit, 0) // the prefix must match exactly (note: may shift ALL bits away) (x >> smallestCommonBit) === (start >> smallestCommonBit).U && // firrtl constant prop range analysis can eliminate these two: (start & uncommonMask).U <= uncommonBits && uncommonBits <= ((end-1) & uncommonMask).U } def shift(x: Int) = IdRange(start+x, end+x) def size = end - start def isEmpty = end == start def range = start until end } object IdRange { def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else { val ranges = s.sorted (ranges.tail zip ranges.init) find { case (a, b) => a overlaps b } } } // An potentially empty inclusive range of 2-powers [min, max] (in bytes) case class TransferSizes(min: Int, max: Int) { def this(x: Int) = this(x, x) require (min <= max, s"Min transfer $min > max transfer $max") require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)") require (max == 0 \|\| isPow2(max), s"TransferSizes must be a power of 2, got: $max") require (min == 0 \|\| isPow2(min), s"TransferSizes must be a power of 2, got: $min") require (max == 0 \|\| min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)") def none = min == 0 def contains(x: Int) = isPow2(x) && min <= x && x <= max def containsLg(x: Int) = contains(1 << x) def containsLg(x: UInt) = if (none) false.B else if (min == max) { log2Ceil(min).U === x } else { log2Ceil(min).U <= x && x <= log2Ceil(max).U } def contains(x: TransferSizes) = x.none \|\| (min <= x.min && x.max <= max) def intersect(x: TransferSizes) = if (x.max < min \|\| max < x.min) TransferSizes.none else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max)) // Not a union, because the result may contain sizes contained by neither term // NOT TO BE CONFUSED WITH COVERPOINTS def mincover(x: TransferSizes) = { if (none) { x } else if (x.none) { this } else { TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max)) } } override def toString() = "TransferSizes[%d, %d]".format(min, max) } object TransferSizes { def apply(x: Int) = new TransferSizes(x) val none = new TransferSizes(0) def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _) def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _) implicit def asBool(x: TransferSizes) = !x.none } // AddressSets specify the address space managed by the manager // Base is the base address, and mask are the bits consumed by the manager // e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff // e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ... case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet] { // Forbid misaligned base address (and empty sets) require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}") require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous // We do allow negative mask (=> ignore all high bits) def contains(x: BigInt) = ((x ^ base) & ~mask) == 0 def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S // turn x into an address contained in this set def legalize(x: UInt): UInt = base.U \| (mask.U & x) // overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1) def overlaps(x: AddressSet) = (~(mask \| x.mask) & (base ^ x.base)) == 0 // contains iff bitwise: x.mask => mask && contains(x.base) def contains(x: AddressSet) = ((x.mask \| (base ^ x.base)) & ~mask) == 0 // The number of bytes to which the manager must be aligned def alignment = ((mask + 1) & ~mask) // Is this a contiguous memory range def contiguous = alignment == mask+1 def finite = mask >= 0 def max = { require (finite, "Max cannot be calculated on infinite mask"); base \| mask } // Widen the match function to ignore all bits in imask def widen(imask: BigInt) = AddressSet(base & ~imask, mask \| imask) // Return an AddressSet that only contains the addresses both sets contain def intersect(x: AddressSet): Option[AddressSet] = { if (!overlaps(x)) { None } else { val r_mask = mask & x.mask val r_base = base \| x.base Some(AddressSet(r_base, r_mask)) } } def subtract(x: AddressSet): Seq[AddressSet] = { intersect(x) match { case None => Seq(this) case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit => val nmask = (mask & (bit-1)) \| remove.mask val nbase = (remove.base ^ bit) & ~nmask AddressSet(nbase, nmask) } } } // AddressSets have one natural Ordering (the containment order, if contiguous) def compare(x: AddressSet) = { val primary = (this.base - x.base).signum // smallest address first val secondary = (x.mask - this.mask).signum // largest mask first if (primary != 0) primary else secondary } // We always want to see things in hex override def toString() = { if (mask >= 0) { "AddressSet(0x%x, 0x%x)".format(base, mask) } else { "AddressSet(0x%x, ~0x%x)".format(base, ~mask) } } def toRanges = { require (finite, "Ranges cannot be calculated on infinite mask") val size = alignment val fragments = mask & ~(size-1) val bits = bitIndexes(fragments) (BigInt(0) until (BigInt(1) << bits.size)).map { i => val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) } AddressRange(off, size) } } } object AddressSet { val everything = AddressSet(0, -1) def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = { if (size == 0) tail.reverse else { val maxBaseAlignment = base & (-base) // 0 for infinite (LSB) val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size val step = if (maxBaseAlignment == 0 \|\| maxBaseAlignment > maxSizeAlignment) maxSizeAlignment else maxBaseAlignment misaligned(base+step, size-step, AddressSet(base, step-1) +: tail) } } def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = { // Pair terms up by ignoring 'bit' seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) => if (seq.size == 1) { seq.head // singleton -> unaffected } else { key.copy(mask = key.mask \| bit) // pair - widen mask by bit } }.toList } def unify(seq: Seq[AddressSet]): Seq[AddressSet] = { val bits = seq.map(_.base).foldLeft(BigInt(0))(_ \| _) AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted } def enumerateMask(mask: BigInt): Seq[BigInt] = { def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] = if (id == mask) (id +: tail).reverse else helper(((~mask \| id) + 1) & mask, id +: tail) helper(0, Nil) } def enumerateBits(mask: BigInt): Seq[BigInt] = { def helper(x: BigInt): Seq[BigInt] = { if (x == 0) { Nil } else { val bit = x & (-x) bit +: helper(x & ~bit) } } helper(mask) } } case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean) { require (depth >= 0, "Buffer depth must be >= 0") def isDefined = depth > 0 def latency = if (isDefined && !flow) 1 else 0 def apply[T <: Data](x: DecoupledIO[T]) = if (isDefined) Queue(x, depth, flow=flow, pipe=pipe) else x def irrevocable[T <: Data](x: ReadyValidIO[T]) = if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe) else x def sq[T <: Data](x: DecoupledIO[T]) = if (!isDefined) x else { val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe)) sq.io.enq <> x sq.io.deq } override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "") } object BufferParams { implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false) val default = BufferParams(2) val none = BufferParams(0) val flow = BufferParams(1, true, false) val pipe = BufferParams(1, false, true) } case class TriStateValue(value: Boolean, set: Boolean) { def update(orig: Boolean) = if (set) value else orig } object TriStateValue { implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true) def unset = TriStateValue(false, false) } trait DirectedBuffers[T] { def copyIn(x: BufferParams): T def copyOut(x: BufferParams): T def copyInOut(x: BufferParams): T } trait IdMapEntry { def name: String def from: IdRange def to: IdRange def isCache: Boolean def requestFifo: Boolean def maxTransactionsInFlight: Option[Int] def pretty(fmt: String) = if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5 fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } else { fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } } abstract class IdMap[T <: IdMapEntry] { protected val fmt: String val mapping: Seq[T] def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n") } File PTW.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.rocket import chisel3._ import chisel3.util.{Arbiter, Cat, Decoupled, Enum, Mux1H, OHToUInt, PopCount, PriorityEncoder, PriorityEncoderOH, RegEnable, UIntToOH, Valid, is, isPow2, log2Ceil, switch} import chisel3.withClock import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.subsystem.CacheBlockBytes import freechips.rocketchip.tile._ import freechips.rocketchip.tilelink._ import freechips.rocketchip.util._ import freechips.rocketchip.util.property import scala.collection.mutable.ListBuffer /* PTE request from TLB to PTW * * TLB send a PTE request to PTW when L1TLB miss / class PTWReq(implicit p: Parameters) extends CoreBundle()(p) { val addr = UInt(vpnBits.W) val need_gpa = Bool() val vstage1 = Bool() val stage2 = Bool() } /* PTE info from L2TLB to TLB * * containing: target PTE, exceptions, two-satge tanslation info / class PTWResp(implicit p: Parameters) extends CoreBundle()(p) { /* ptw access exception / val ae_ptw = Bool() /* final access exception / val ae_final = Bool() /* page fault / val pf = Bool() /* guest page fault / val gf = Bool() /* hypervisor read / val hr = Bool() /* hypervisor write / val hw = Bool() /* hypervisor execute / val hx = Bool() /* PTE to refill L1TLB * * source: L2TLB / val pte = new PTE /* pte pglevel / val level = UInt(log2Ceil(pgLevels).W) /* fragmented_superpage support / val fragmented_superpage = Bool() /* homogeneous for both pma and pmp / val homogeneous = Bool() val gpa = Valid(UInt(vaddrBits.W)) val gpa_is_pte = Bool() } /* IO between TLB and PTW * * PTW receives : * - PTE request * - CSRs info * - pmp results from PMP(in TLB) / class TLBPTWIO(implicit p: Parameters) extends CoreBundle()(p) with HasCoreParameters { val req = Decoupled(Valid(new PTWReq)) val resp = Flipped(Valid(new PTWResp)) val ptbr = Input(new PTBR()) val hgatp = Input(new PTBR()) val vsatp = Input(new PTBR()) val status = Input(new MStatus()) val hstatus = Input(new HStatus()) val gstatus = Input(new MStatus()) val pmp = Input(Vec(nPMPs, new PMP)) val customCSRs = Flipped(coreParams.customCSRs) } /* PTW performance statistics / class PTWPerfEvents extends Bundle { val l2miss = Bool() val l2hit = Bool() val pte_miss = Bool() val pte_hit = Bool() } /* Datapath IO between PTW and Core * * PTW receives CSRs info, pmp checks, sfence instruction info * * PTW sends its performance statistics to core / class DatapathPTWIO(implicit p: Parameters) extends CoreBundle()(p) with HasCoreParameters { val ptbr = Input(new PTBR()) val hgatp = Input(new PTBR()) val vsatp = Input(new PTBR()) val sfence = Flipped(Valid(new SFenceReq)) val status = Input(new MStatus()) val hstatus = Input(new HStatus()) val gstatus = Input(new MStatus()) val pmp = Input(Vec(nPMPs, new PMP)) val perf = Output(new PTWPerfEvents()) val customCSRs = Flipped(coreParams.customCSRs) /* enable clock generated by ptw / val clock_enabled = Output(Bool()) } /* PTE template for transmission * * contains useful methods to check PTE attributes * @see RV-priv spec 4.3.1 for pgae table entry format / class PTE(implicit p: Parameters) extends CoreBundle()(p) { val reserved_for_future = UInt(10.W) val ppn = UInt(44.W) val reserved_for_software = Bits(2.W) /* dirty bit / val d = Bool() /* access bit / val a = Bool() /* global mapping / val g = Bool() /* user mode accessible / val u = Bool() /* whether the page is executable / val x = Bool() /* whether the page is writable / val w = Bool() /* whether the page is readable / val r = Bool() /* valid bit / val v = Bool() /* return true if find a pointer to next level page table / def table(dummy: Int = 0) = v && !r && !w && !x && !d && !a && !u && reserved_for_future === 0.U /* return true if find a leaf PTE / def leaf(dummy: Int = 0) = v && (r \|\| (x && !w)) && a /* user read / def ur(dummy: Int = 0) = sr() && u /* user write/ def uw(dummy: Int = 0) = sw() && u /* user execute / def ux(dummy: Int = 0) = sx() && u /* supervisor read / def sr(dummy: Int = 0) = leaf() && r /* supervisor write / def sw(dummy: Int = 0) = leaf() && w && d /* supervisor execute / def sx(dummy: Int = 0) = leaf() && x /* full permission: writable and executable in user mode / def isFullPerm(dummy: Int = 0) = uw() && ux() } /* L2TLB PTE template * * contains tag bits * @param nSets number of sets in L2TLB * @see RV-priv spec 4.3.1 for page table entry format / class L2TLBEntry(nSets: Int)(implicit p: Parameters) extends CoreBundle()(p) with HasCoreParameters { val idxBits = log2Ceil(nSets) val tagBits = maxSVAddrBits - pgIdxBits - idxBits + (if (usingHypervisor) 1 else 0) val tag = UInt(tagBits.W) val ppn = UInt(ppnBits.W) /* dirty bit / val d = Bool() /* access bit / val a = Bool() /* user mode accessible / val u = Bool() /* whether the page is executable / val x = Bool() /* whether the page is writable / val w = Bool() /* whether the page is readable / val r = Bool() } /* PTW contains L2TLB, and performs page table walk for high level TLB, and cache queries from L1 TLBs(I$, D$, RoCC) * * It performs hierarchy page table query to mem for the desired leaf PTE and cache them in l2tlb. * Besides leaf PTEs, it also caches non-leaf PTEs in pte_cache to accerlerate the process. * * ==Structure== * - l2tlb : for leaf PTEs * - set-associative (configurable with [[CoreParams.nL2TLBEntries]]and [[CoreParams.nL2TLBWays]])) * - PLRU * - pte_cache: for non-leaf PTEs * - set-associative * - LRU * - s2_pte_cache: for non-leaf PTEs in 2-stage translation * - set-associative * - PLRU * * l2tlb Pipeline: 3 stage * {{{ * stage 0 : read * stage 1 : decode * stage 2 : hit check * }}} * ==State Machine== * s_ready: ready to reveive request from TLB * s_req: request mem; pte_cache hit judge * s_wait1: deal with l2tlb error * s_wait2: final hit judge * s_wait3: receive mem response * s_fragment_superpage: for superpage PTE * * @note l2tlb hit happens in s_req or s_wait1 * @see RV-priv spec 4.3-4.6 for Virtual-Memory System * @see RV-priv spec 8.5 for Two-Stage Address Translation * @todo details in two-stage translation / class PTW(n: Int)(implicit edge: TLEdgeOut, p: Parameters) extends CoreModule()(p) { val io = IO(new Bundle { /* to n TLB / val requestor = Flipped(Vec(n, new TLBPTWIO)) /* to HellaCache / val mem = new HellaCacheIO /* to Core * * contains CSRs info and performance statistics / val dpath = new DatapathPTWIO }) val s_ready :: s_req :: s_wait1 :: s_dummy1 :: s_wait2 :: s_wait3 :: s_dummy2 :: s_fragment_superpage :: Nil = Enum(8) val state = RegInit(s_ready) val l2_refill_wire = Wire(Bool()) /* Arbiter to arbite request from n TLB / val arb = Module(new Arbiter(Valid(new PTWReq), n)) // use TLB req as arbitor's input arb.io.in <> io.requestor.map(_.req) // receive req only when s_ready and not in refill arb.io.out.ready := (state === s_ready) && !l2_refill_wire val resp_valid = RegNext(VecInit(Seq.fill(io.requestor.size)(false.B))) val clock_en = state =/= s_ready \|\| l2_refill_wire \|\| arb.io.out.valid \|\| io.dpath.sfence.valid \|\| io.dpath.customCSRs.disableDCacheClockGate io.dpath.clock_enabled := usingVM.B && clock_en val gated_clock = if (!usingVM \|\| !tileParams.dcache.get.clockGate) clock else ClockGate(clock, clock_en, "ptw_clock_gate") withClock (gated_clock) { // entering gated-clock domain val invalidated = Reg(Bool()) /* current PTE level * {{{ * 0 <= count <= pgLevel-1 * count = pgLevel - 1 : leaf PTE * count < pgLevel - 1 : non-leaf PTE * }}} / val count = Reg(UInt(log2Ceil(pgLevels).W)) val resp_ae_ptw = Reg(Bool()) val resp_ae_final = Reg(Bool()) val resp_pf = Reg(Bool()) val resp_gf = Reg(Bool()) val resp_hr = Reg(Bool()) val resp_hw = Reg(Bool()) val resp_hx = Reg(Bool()) val resp_fragmented_superpage = Reg(Bool()) /* tlb request / val r_req = Reg(new PTWReq) /* current selected way in arbitor / val r_req_dest = Reg(Bits()) // to respond to L1TLB : l2_hit // to construct mem.req.addr val r_pte = Reg(new PTE) val r_hgatp = Reg(new PTBR) // 2-stage pageLevel val aux_count = Reg(UInt(log2Ceil(pgLevels).W)) /* pte for 2-stage translation / val aux_pte = Reg(new PTE) val gpa_pgoff = Reg(UInt(pgIdxBits.W)) // only valid in resp_gf case val stage2 = Reg(Bool()) val stage2_final = Reg(Bool()) val satp = Mux(arb.io.out.bits.bits.vstage1, io.dpath.vsatp, io.dpath.ptbr) val r_hgatp_initial_count = pgLevels.U - minPgLevels.U - r_hgatp.additionalPgLevels /* 2-stage translation both enable / val do_both_stages = r_req.vstage1 && r_req.stage2 val max_count = count max aux_count val vpn = Mux(r_req.vstage1 && stage2, aux_pte.ppn, r_req.addr) val mem_resp_valid = RegNext(io.mem.resp.valid) val mem_resp_data = RegNext(io.mem.resp.bits.data) io.mem.uncached_resp.map { resp => assert(!(resp.valid && io.mem.resp.valid)) resp.ready := true.B when (resp.valid) { mem_resp_valid := true.B mem_resp_data := resp.bits.data } } // construct pte from mem.resp val (pte, invalid_paddr, invalid_gpa) = { val tmp = mem_resp_data.asTypeOf(new PTE()) val res = WireDefault(tmp) res.ppn := Mux(do_both_stages && !stage2, tmp.ppn(vpnBits.min(tmp.ppn.getWidth)-1, 0), tmp.ppn(ppnBits-1, 0)) when (tmp.r \|\| tmp.w \|\| tmp.x) { // for superpage mappings, make sure PPN LSBs are zero for (i <- 0 until pgLevels-1) when (count <= i.U && tmp.ppn((pgLevels-1-i)pgLevelBits-1, (pgLevels-2-i)pgLevelBits) =/= 0.U) { res.v := false.B } } (res, Mux(do_both_stages && !stage2, (tmp.ppn >> vpnBits) =/= 0.U, (tmp.ppn >> ppnBits) =/= 0.U), do_both_stages && !stage2 && checkInvalidHypervisorGPA(r_hgatp, tmp.ppn)) } // find non-leaf PTE, need traverse val traverse = pte.table() && !invalid_paddr && !invalid_gpa && count < (pgLevels-1).U /* address send to mem for enquerry / val pte_addr = if (!usingVM) 0.U else { val vpn_idxs = (0 until pgLevels).map { i => val width = pgLevelBits + (if (i <= pgLevels - minPgLevels) hypervisorExtraAddrBits else 0) (vpn >> (pgLevels - i - 1) pgLevelBits)(width - 1, 0) } val mask = Mux(stage2 && count === r_hgatp_initial_count, ((1 << (hypervisorExtraAddrBits + pgLevelBits)) - 1).U, ((1 << pgLevelBits) - 1).U) val vpn_idx = vpn_idxs(count) & mask val raw_pte_addr = ((r_pte.ppn << pgLevelBits) \| vpn_idx) << log2Ceil(xLen / 8) val size = if (usingHypervisor) vaddrBits else paddrBits //use r_pte.ppn as page table base address //use vpn slice as offset raw_pte_addr.apply(size.min(raw_pte_addr.getWidth) - 1, 0) } /** stage2_pte_cache input addr / val stage2_pte_cache_addr = if (!usingHypervisor) 0.U else { val vpn_idxs = (0 until pgLevels - 1).map { i => (r_req.addr >> (pgLevels - i - 1) pgLevelBits)(pgLevelBits - 1, 0) } val vpn_idx = vpn_idxs(aux_count) val raw_s2_pte_cache_addr = Cat(aux_pte.ppn, vpn_idx) << log2Ceil(xLen / 8) raw_s2_pte_cache_addr(vaddrBits.min(raw_s2_pte_cache_addr.getWidth) - 1, 0) } def makeFragmentedSuperpagePPN(ppn: UInt): Seq[UInt] = { (pgLevels-1 until 0 by -1).map(i => Cat(ppn >> (pgLevelBitsi), r_req.addr(((pgLevelBitsi) min vpnBits)-1, 0).padTo(pgLevelBitsi))) } /* PTECache caches non-leaf PTE * @param s2 true: 2-stage address translation / def makePTECache(s2: Boolean): (Bool, UInt) = if (coreParams.nPTECacheEntries == 0) { (false.B, 0.U) } else { val plru = new PseudoLRU(coreParams.nPTECacheEntries) val valid = RegInit(0.U(coreParams.nPTECacheEntries.W)) val tags = Reg(Vec(coreParams.nPTECacheEntries, UInt((if (usingHypervisor) 1 + vaddrBits else paddrBits).W))) // not include full pte, only ppn val data = Reg(Vec(coreParams.nPTECacheEntries, UInt((if (usingHypervisor && s2) vpnBits else ppnBits).W))) val can_hit = if (s2) count === r_hgatp_initial_count && aux_count < (pgLevels-1).U && r_req.vstage1 && stage2 && !stage2_final else count < (pgLevels-1).U && Mux(r_req.vstage1, stage2, !r_req.stage2) val can_refill = if (s2) do_both_stages && !stage2 && !stage2_final else can_hit val tag = if (s2) Cat(true.B, stage2_pte_cache_addr.padTo(vaddrBits)) else Cat(r_req.vstage1, pte_addr.padTo(if (usingHypervisor) vaddrBits else paddrBits)) val hits = tags.map(_ === tag).asUInt & valid val hit = hits.orR && can_hit // refill with mem response when (mem_resp_valid && traverse && can_refill && !hits.orR && !invalidated) { val r = Mux(valid.andR, plru.way, PriorityEncoder(~valid)) valid := valid \| UIntToOH(r) tags(r) := tag data(r) := pte.ppn plru.access(r) } // replace when (hit && state === s_req) { plru.access(OHToUInt(hits)) } when (io.dpath.sfence.valid && (!io.dpath.sfence.bits.rs1 \|\| usingHypervisor.B && io.dpath.sfence.bits.hg)) { valid := 0.U } val lcount = if (s2) aux_count else count for (i <- 0 until pgLevels-1) { ccover(hit && state === s_req && lcount === i.U, s"PTE_CACHE_HIT_L$i", s"PTE cache hit, level $i") } (hit, Mux1H(hits, data)) } // generate pte_cache val (pte_cache_hit, pte_cache_data) = makePTECache(false) // generate pte_cache with 2-stage translation val (stage2_pte_cache_hit, stage2_pte_cache_data) = makePTECache(true) // pte_cache hit or 2-stage pte_cache hit val pte_hit = RegNext(false.B) io.dpath.perf.pte_miss := false.B io.dpath.perf.pte_hit := pte_hit && (state === s_req) && !io.dpath.perf.l2hit assert(!(io.dpath.perf.l2hit && (io.dpath.perf.pte_miss \|\| io.dpath.perf.pte_hit)), "PTE Cache Hit/Miss Performance Monitor Events are lower priority than L2TLB Hit event") // l2_refill happens when find the leaf pte val l2_refill = RegNext(false.B) l2_refill_wire := l2_refill io.dpath.perf.l2miss := false.B io.dpath.perf.l2hit := false.B // l2tlb val (l2_hit, l2_error, l2_pte, l2_tlb_ram) = if (coreParams.nL2TLBEntries == 0) (false.B, false.B, WireDefault(0.U.asTypeOf(new PTE)), None) else { val code = new ParityCode require(isPow2(coreParams.nL2TLBEntries)) require(isPow2(coreParams.nL2TLBWays)) require(coreParams.nL2TLBEntries >= coreParams.nL2TLBWays) val nL2TLBSets = coreParams.nL2TLBEntries / coreParams.nL2TLBWays require(isPow2(nL2TLBSets)) val idxBits = log2Ceil(nL2TLBSets) val l2_plru = new SetAssocLRU(nL2TLBSets, coreParams.nL2TLBWays, "plru") val ram = DescribedSRAM( name = "l2_tlb_ram", desc = "L2 TLB", size = nL2TLBSets, data = Vec(coreParams.nL2TLBWays, UInt(code.width(new L2TLBEntry(nL2TLBSets).getWidth).W)) ) val g = Reg(Vec(coreParams.nL2TLBWays, UInt(nL2TLBSets.W))) val valid = RegInit(VecInit(Seq.fill(coreParams.nL2TLBWays)(0.U(nL2TLBSets.W)))) // use r_req to construct tag val (r_tag, r_idx) = Split(Cat(r_req.vstage1, r_req.addr(maxSVAddrBits-pgIdxBits-1, 0)), idxBits) /* the valid vec for the selected set(including n ways) / val r_valid_vec = valid.map(_(r_idx)).asUInt val r_valid_vec_q = Reg(UInt(coreParams.nL2TLBWays.W)) val r_l2_plru_way = Reg(UInt(log2Ceil(coreParams.nL2TLBWays max 1).W)) r_valid_vec_q := r_valid_vec // replacement way r_l2_plru_way := (if (coreParams.nL2TLBWays > 1) l2_plru.way(r_idx) else 0.U) // refill with r_pte(leaf pte) when (l2_refill && !invalidated) { val entry = Wire(new L2TLBEntry(nL2TLBSets)) entry.ppn := r_pte.ppn entry.d := r_pte.d entry.a := r_pte.a entry.u := r_pte.u entry.x := r_pte.x entry.w := r_pte.w entry.r := r_pte.r entry.tag := r_tag // if all the way are valid, use plru to select one way to be replaced, // otherwise use PriorityEncoderOH to select one val wmask = if (coreParams.nL2TLBWays > 1) Mux(r_valid_vec_q.andR, UIntToOH(r_l2_plru_way, coreParams.nL2TLBWays), PriorityEncoderOH(~r_valid_vec_q)) else 1.U(1.W) ram.write(r_idx, VecInit(Seq.fill(coreParams.nL2TLBWays)(code.encode(entry.asUInt))), wmask.asBools) val mask = UIntToOH(r_idx) for (way <- 0 until coreParams.nL2TLBWays) { when (wmask(way)) { valid(way) := valid(way) \| mask g(way) := Mux(r_pte.g, g(way) \| mask, g(way) & ~mask) } } } // sfence happens when (io.dpath.sfence.valid) { val hg = usingHypervisor.B && io.dpath.sfence.bits.hg for (way <- 0 until coreParams.nL2TLBWays) { valid(way) := Mux(!hg && io.dpath.sfence.bits.rs1, valid(way) & ~UIntToOH(io.dpath.sfence.bits.addr(idxBits+pgIdxBits-1, pgIdxBits)), Mux(!hg && io.dpath.sfence.bits.rs2, valid(way) & g(way), 0.U)) } } val s0_valid = !l2_refill && arb.io.out.fire val s0_suitable = arb.io.out.bits.bits.vstage1 === arb.io.out.bits.bits.stage2 && !arb.io.out.bits.bits.need_gpa val s1_valid = RegNext(s0_valid && s0_suitable && arb.io.out.bits.valid) val s2_valid = RegNext(s1_valid) // read from tlb idx val s1_rdata = ram.read(arb.io.out.bits.bits.addr(idxBits-1, 0), s0_valid) val s2_rdata = s1_rdata.map(s1_rdway => code.decode(RegEnable(s1_rdway, s1_valid))) val s2_valid_vec = RegEnable(r_valid_vec, s1_valid) val s2_g_vec = RegEnable(VecInit(g.map(_(r_idx))), s1_valid) val s2_error = (0 until coreParams.nL2TLBWays).map(way => s2_valid_vec(way) && s2_rdata(way).error).orR when (s2_valid && s2_error) { valid.foreach { _ := 0.U }} // decode val s2_entry_vec = s2_rdata.map(_.uncorrected.asTypeOf(new L2TLBEntry(nL2TLBSets))) val s2_hit_vec = (0 until coreParams.nL2TLBWays).map(way => s2_valid_vec(way) && (r_tag === s2_entry_vec(way).tag)) val s2_hit = s2_valid && s2_hit_vec.orR io.dpath.perf.l2miss := s2_valid && !(s2_hit_vec.orR) io.dpath.perf.l2hit := s2_hit when (s2_hit) { l2_plru.access(r_idx, OHToUInt(s2_hit_vec)) assert((PopCount(s2_hit_vec) === 1.U) \|\| s2_error, "L2 TLB multi-hit") } val s2_pte = Wire(new PTE) val s2_hit_entry = Mux1H(s2_hit_vec, s2_entry_vec) s2_pte.ppn := s2_hit_entry.ppn s2_pte.d := s2_hit_entry.d s2_pte.a := s2_hit_entry.a s2_pte.g := Mux1H(s2_hit_vec, s2_g_vec) s2_pte.u := s2_hit_entry.u s2_pte.x := s2_hit_entry.x s2_pte.w := s2_hit_entry.w s2_pte.r := s2_hit_entry.r s2_pte.v := true.B s2_pte.reserved_for_future := 0.U s2_pte.reserved_for_software := 0.U for (way <- 0 until coreParams.nL2TLBWays) { ccover(s2_hit && s2_hit_vec(way), s"L2_TLB_HIT_WAY$way", s"L2 TLB hit way$way") } (s2_hit, s2_error, s2_pte, Some(ram)) } // if SFENCE occurs during walk, don't refill PTE cache or L2 TLB until next walk invalidated := io.dpath.sfence.valid \|\| (invalidated && state =/= s_ready) // mem request io.mem.keep_clock_enabled := false.B io.mem.req.valid := state === s_req \|\| state === s_dummy1 io.mem.req.bits.phys := true.B io.mem.req.bits.cmd := M_XRD io.mem.req.bits.size := log2Ceil(xLen/8).U io.mem.req.bits.signed := false.B io.mem.req.bits.addr := pte_addr io.mem.req.bits.idx.foreach(_ := pte_addr) io.mem.req.bits.dprv := PRV.S.U // PTW accesses are S-mode by definition io.mem.req.bits.dv := do_both_stages && !stage2 io.mem.req.bits.tag := DontCare io.mem.req.bits.no_resp := false.B io.mem.req.bits.no_alloc := DontCare io.mem.req.bits.no_xcpt := DontCare io.mem.req.bits.data := DontCare io.mem.req.bits.mask := DontCare io.mem.s1_kill := l2_hit \|\| (state =/= s_wait1) \|\| resp_gf io.mem.s1_data := DontCare io.mem.s2_kill := false.B val pageGranularityPMPs = pmpGranularity >= (1 << pgIdxBits) require(!usingHypervisor \|\| pageGranularityPMPs, s"hypervisor requires pmpGranularity >= ${1<<pgIdxBits}") val pmaPgLevelHomogeneous = (0 until pgLevels) map { i => val pgSize = BigInt(1) << (pgIdxBits + ((pgLevels - 1 - i) pgLevelBits)) if (pageGranularityPMPs && i == pgLevels - 1) { require(TLBPageLookup.homogeneous(edge.manager.managers, pgSize), s"All memory regions must be $pgSize-byte aligned") true.B } else { TLBPageLookup(edge.manager.managers, xLen, p(CacheBlockBytes), pgSize, xLen/8)(r_pte.ppn << pgIdxBits).homogeneous } } val pmaHomogeneous = pmaPgLevelHomogeneous(count) val pmpHomogeneous = new PMPHomogeneityChecker(io.dpath.pmp).apply(r_pte.ppn << pgIdxBits, count) val homogeneous = pmaHomogeneous && pmpHomogeneous // response to tlb for (i <- 0 until io.requestor.size) { io.requestor(i).resp.valid := resp_valid(i) io.requestor(i).resp.bits.ae_ptw := resp_ae_ptw io.requestor(i).resp.bits.ae_final := resp_ae_final io.requestor(i).resp.bits.pf := resp_pf io.requestor(i).resp.bits.gf := resp_gf io.requestor(i).resp.bits.hr := resp_hr io.requestor(i).resp.bits.hw := resp_hw io.requestor(i).resp.bits.hx := resp_hx io.requestor(i).resp.bits.pte := r_pte io.requestor(i).resp.bits.level := max_count io.requestor(i).resp.bits.homogeneous := homogeneous \|\| pageGranularityPMPs.B io.requestor(i).resp.bits.fragmented_superpage := resp_fragmented_superpage && pageGranularityPMPs.B io.requestor(i).resp.bits.gpa.valid := r_req.need_gpa io.requestor(i).resp.bits.gpa.bits := Cat(Mux(!stage2_final \|\| !r_req.vstage1 \|\| aux_count === (pgLevels - 1).U, aux_pte.ppn, makeFragmentedSuperpagePPN(aux_pte.ppn)(aux_count)), gpa_pgoff) io.requestor(i).resp.bits.gpa_is_pte := !stage2_final io.requestor(i).ptbr := io.dpath.ptbr io.requestor(i).hgatp := io.dpath.hgatp io.requestor(i).vsatp := io.dpath.vsatp io.requestor(i).customCSRs <> io.dpath.customCSRs io.requestor(i).status := io.dpath.status io.requestor(i).hstatus := io.dpath.hstatus io.requestor(i).gstatus := io.dpath.gstatus io.requestor(i).pmp := io.dpath.pmp } // control state machine val next_state = WireDefault(state) state := OptimizationBarrier(next_state) val do_switch = WireDefault(false.B) switch (state) { is (s_ready) { when (arb.io.out.fire) { val satp_initial_count = pgLevels.U - minPgLevels.U - satp.additionalPgLevels val vsatp_initial_count = pgLevels.U - minPgLevels.U - io.dpath.vsatp.additionalPgLevels val hgatp_initial_count = pgLevels.U - minPgLevels.U - io.dpath.hgatp.additionalPgLevels val aux_ppn = Mux(arb.io.out.bits.bits.vstage1, io.dpath.vsatp.ppn, arb.io.out.bits.bits.addr) r_req := arb.io.out.bits.bits r_req_dest := arb.io.chosen next_state := Mux(arb.io.out.bits.valid, s_req, s_ready) stage2 := arb.io.out.bits.bits.stage2 stage2_final := arb.io.out.bits.bits.stage2 && !arb.io.out.bits.bits.vstage1 count := Mux(arb.io.out.bits.bits.stage2, hgatp_initial_count, satp_initial_count) aux_count := Mux(arb.io.out.bits.bits.vstage1, vsatp_initial_count, 0.U) aux_pte.ppn := aux_ppn aux_pte.reserved_for_future := 0.U resp_ae_ptw := false.B resp_ae_final := false.B resp_pf := false.B resp_gf := checkInvalidHypervisorGPA(io.dpath.hgatp, aux_ppn) && arb.io.out.bits.bits.stage2 resp_hr := true.B resp_hw := true.B resp_hx := true.B resp_fragmented_superpage := false.B r_hgatp := io.dpath.hgatp assert(!arb.io.out.bits.bits.need_gpa \|\| arb.io.out.bits.bits.stage2) } } is (s_req) { when(stage2 && count === r_hgatp_initial_count) { gpa_pgoff := Mux(aux_count === (pgLevels-1).U, r_req.addr << (xLen/8).log2, stage2_pte_cache_addr) } // pte_cache hit when (stage2_pte_cache_hit) { aux_count := aux_count + 1.U aux_pte.ppn := stage2_pte_cache_data aux_pte.reserved_for_future := 0.U pte_hit := true.B }.elsewhen (pte_cache_hit) { count := count + 1.U pte_hit := true.B }.otherwise { next_state := Mux(io.mem.req.ready, s_wait1, s_req) } when(resp_gf) { next_state := s_ready resp_valid(r_req_dest) := true.B } } is (s_wait1) { // This Mux is for the l2_error case; the l2_hit && !l2_error case is overriden below next_state := Mux(l2_hit, s_req, s_wait2) } is (s_wait2) { next_state := s_wait3 io.dpath.perf.pte_miss := count < (pgLevels-1).U when (io.mem.s2_xcpt.ae.ld) { resp_ae_ptw := true.B next_state := s_ready resp_valid(r_req_dest) := true.B } } is (s_fragment_superpage) { next_state := s_ready resp_valid(r_req_dest) := true.B when (!homogeneous) { count := (pgLevels-1).U resp_fragmented_superpage := true.B } when (do_both_stages) { resp_fragmented_superpage := true.B } } } val merged_pte = { val superpage_masks = (0 until pgLevels).map(i => ((BigInt(1) << pte.ppn.getWidth) - (BigInt(1) << (pgLevels-1-i)pgLevelBits)).U) val superpage_mask = superpage_masks(Mux(stage2_final, max_count, (pgLevels-1).U)) val stage1_ppns = (0 until pgLevels-1).map(i => Cat(pte.ppn(pte.ppn.getWidth-1, (pgLevels-i-1)pgLevelBits), aux_pte.ppn((pgLevels-i-1)pgLevelBits-1,0))) :+ pte.ppn val stage1_ppn = stage1_ppns(count) makePTE(stage1_ppn & superpage_mask, aux_pte) } r_pte := OptimizationBarrier( // l2tlb hit->find a leaf PTE(l2_pte), respond to L1TLB Mux(l2_hit && !l2_error && !resp_gf, l2_pte, // S2 PTE cache hit -> proceed to the next level of walking, update the r_pte with hgatp Mux(state === s_req && stage2_pte_cache_hit, makeHypervisorRootPTE(r_hgatp, stage2_pte_cache_data, l2_pte), // pte cache hit->find a non-leaf PTE(pte_cache),continue to request mem Mux(state === s_req && pte_cache_hit, makePTE(pte_cache_data, l2_pte), // 2-stage translation Mux(do_switch, makeHypervisorRootPTE(r_hgatp, pte.ppn, r_pte), // when mem respond, store mem.resp.pte Mux(mem_resp_valid, Mux(!traverse && r_req.vstage1 && stage2, merged_pte, pte), // fragment_superpage Mux(state === s_fragment_superpage && !homogeneous && count =/= (pgLevels - 1).U, makePTE(makeFragmentedSuperpagePPN(r_pte.ppn)(count), r_pte), // when tlb request come->request mem, use root address in satp(or vsatp,hgatp) Mux(arb.io.out.fire, Mux(arb.io.out.bits.bits.stage2, makeHypervisorRootPTE(io.dpath.hgatp, io.dpath.vsatp.ppn, r_pte), makePTE(satp.ppn, r_pte)), r_pte)))))))) when (l2_hit && !l2_error && !resp_gf) { assert(state === s_req \|\| state === s_wait1) next_state := s_ready resp_valid(r_req_dest) := true.B count := (pgLevels-1).U } when (mem_resp_valid) { assert(state === s_wait3) next_state := s_req when (traverse) { when (do_both_stages && !stage2) { do_switch := true.B } count := count + 1.U }.otherwise { val gf = (stage2 && !stage2_final && !pte.ur()) \|\| (pte.leaf() && pte.reserved_for_future === 0.U && invalid_gpa) val ae = pte.v && invalid_paddr val pf = pte.v && pte.reserved_for_future =/= 0.U val success = pte.v && !ae && !pf && !gf when (do_both_stages && !stage2_final && success) { when (stage2) { stage2 := false.B count := aux_count }.otherwise { stage2_final := true.B do_switch := true.B } }.otherwise { // find a leaf pte, start l2 refill l2_refill := success && count === (pgLevels-1).U && !r_req.need_gpa && (!r_req.vstage1 && !r_req.stage2 \|\| do_both_stages && aux_count === (pgLevels-1).U && pte.isFullPerm()) count := max_count when (pageGranularityPMPs.B && !(count === (pgLevels-1).U && (!do_both_stages \|\| aux_count === (pgLevels-1).U))) { next_state := s_fragment_superpage }.otherwise { next_state := s_ready resp_valid(r_req_dest) := true.B } resp_ae_ptw := ae && count < (pgLevels-1).U && pte.table() resp_ae_final := ae && pte.leaf() resp_pf := pf && !stage2 resp_gf := gf \|\| (pf && stage2) resp_hr := !stage2 \|\| (!pf && !gf && pte.ur()) resp_hw := !stage2 \|\| (!pf && !gf && pte.uw()) resp_hx := !stage2 \|\| (!pf && !gf && pte.ux()) } } } when (io.mem.s2_nack) { assert(state === s_wait2) next_state := s_req } when (do_switch) { aux_count := Mux(traverse, count + 1.U, count) count := r_hgatp_initial_count aux_pte := Mux(traverse, pte, { val s1_ppns = (0 until pgLevels-1).map(i => Cat(pte.ppn(pte.ppn.getWidth-1, (pgLevels-i-1)pgLevelBits), r_req.addr(((pgLevels-i-1)pgLevelBits min vpnBits)-1,0).padTo((pgLevels-i-1)pgLevelBits))) :+ pte.ppn makePTE(s1_ppns(count), pte) }) stage2 := true.B } for (i <- 0 until pgLevels) { val leaf = mem_resp_valid && !traverse && count === i.U ccover(leaf && pte.v && !invalid_paddr && !invalid_gpa && pte.reserved_for_future === 0.U, s"L$i", s"successful page-table access, level $i") ccover(leaf && pte.v && invalid_paddr, s"L${i}_BAD_PPN_MSB", s"PPN too large, level $i") ccover(leaf && pte.v && invalid_gpa, s"L${i}_BAD_GPA_MSB", s"GPA too large, level $i") ccover(leaf && pte.v && pte.reserved_for_future =/= 0.U, s"L${i}_BAD_RSV_MSB", s"reserved MSBs set, level $i") ccover(leaf && !mem_resp_data(0), s"L${i}_INVALID_PTE", s"page not present, level $i") if (i != pgLevels-1) ccover(leaf && !pte.v && mem_resp_data(0), s"L${i}_BAD_PPN_LSB", s"PPN LSBs not zero, level $i") } ccover(mem_resp_valid && count === (pgLevels-1).U && pte.table(), s"TOO_DEEP", s"page table too deep") ccover(io.mem.s2_nack, "NACK", "D$ nacked page-table access") ccover(state === s_wait2 && io.mem.s2_xcpt.ae.ld, "AE", "access exception while walking page table") } // leaving gated-clock domain private def ccover(cond: Bool, label: String, desc: String)(implicit sourceInfo: SourceInfo) = if (usingVM) property.cover(cond, s"PTW_$label", "MemorySystem;;" + desc) /** Relace PTE.ppn with ppn / private def makePTE(ppn: UInt, default: PTE) = { val pte = WireDefault(default) pte.ppn := ppn pte } /* use hgatp and vpn to construct a new ppn / private def makeHypervisorRootPTE(hgatp: PTBR, vpn: UInt, default: PTE) = { val count = pgLevels.U - minPgLevels.U - hgatp.additionalPgLevels val idxs = (0 to pgLevels-minPgLevels).map(i => (vpn >> (pgLevels-i)pgLevelBits)) val lsbs = WireDefault(UInt(maxHypervisorExtraAddrBits.W), idxs(count)) val pte = WireDefault(default) pte.ppn := Cat(hgatp.ppn >> maxHypervisorExtraAddrBits, lsbs) pte } /** use hgatp and vpn to check for gpa out of range / private def checkInvalidHypervisorGPA(hgatp: PTBR, vpn: UInt) = { val count = pgLevels.U - minPgLevels.U - hgatp.additionalPgLevels val idxs = (0 to pgLevels-minPgLevels).map(i => (vpn >> ((pgLevels-i)pgLevelBits)+maxHypervisorExtraAddrBits)) idxs.extract(count) =/= 0.U } } /** Mix-ins for constructing tiles that might have a PTW */ trait CanHavePTW extends HasTileParameters with HasHellaCache { this: BaseTile => val module: CanHavePTWModule var nPTWPorts = 1 nDCachePorts += usingPTW.toInt } trait CanHavePTWModule extends HasHellaCacheModule { val outer: CanHavePTW val ptwPorts = ListBuffer(outer.dcache.module.io.ptw) val ptw = Module(new PTW(outer.nPTWPorts)(outer.dcache.node.edges.out(0), outer.p)) ptw.io.mem <> DontCare if (outer.usingPTW) { dcachePorts += ptw.io.mem } }	module ITLB_1( // @[TLB.scala:318:7] input clock, // @[TLB.scala:318:7] input reset, // @[TLB.scala:318:7] input io_req_valid, // @[TLB.scala:320:14] input [39:0] io_req_bits_vaddr, // @[TLB.scala:320:14] input [1:0] io_req_bits_prv, // @[TLB.scala:320:14] input io_req_bits_v, // @[TLB.scala:320:14] output io_resp_miss, // @[TLB.scala:320:14] output [31:0] io_resp_paddr, // @[TLB.scala:320:14] output [39:0] io_resp_gpa, // @[TLB.scala:320:14] output io_resp_pf_ld, // @[TLB.scala:320:14] output io_resp_pf_inst, // @[TLB.scala:320:14] output io_resp_ae_ld, // @[TLB.scala:320:14] output io_resp_ae_inst, // @[TLB.scala:320:14] output io_resp_ma_ld, // @[TLB.scala:320:14] output io_resp_cacheable, // @[TLB.scala:320:14] output io_resp_prefetchable, // @[TLB.scala:320:14] input io_sfence_valid, // @[TLB.scala:320:14] input io_sfence_bits_rs1, // @[TLB.scala:320:14] input io_sfence_bits_rs2, // @[TLB.scala:320:14] input [38:0] io_sfence_bits_addr, // @[TLB.scala:320:14] input io_sfence_bits_asid, // @[TLB.scala:320:14] input io_sfence_bits_hv, // @[TLB.scala:320:14] input io_sfence_bits_hg, // @[TLB.scala:320:14] input io_ptw_req_ready, // @[TLB.scala:320:14] output io_ptw_req_valid, // @[TLB.scala:320:14] output [26:0] io_ptw_req_bits_bits_addr, // @[TLB.scala:320:14] output io_ptw_req_bits_bits_need_gpa, // @[TLB.scala:320:14] input io_ptw_resp_valid, // @[TLB.scala:320:14] input io_ptw_resp_bits_ae_ptw, // @[TLB.scala:320:14] input io_ptw_resp_bits_ae_final, // @[TLB.scala:320:14] input io_ptw_resp_bits_pf, // @[TLB.scala:320:14] input io_ptw_resp_bits_gf, // @[TLB.scala:320:14] input io_ptw_resp_bits_hr, // @[TLB.scala:320:14] input io_ptw_resp_bits_hw, // @[TLB.scala:320:14] input io_ptw_resp_bits_hx, // @[TLB.scala:320:14] input [9:0] io_ptw_resp_bits_pte_reserved_for_future, // @[TLB.scala:320:14] input [43:0] io_ptw_resp_bits_pte_ppn, // @[TLB.scala:320:14] input [1:0] io_ptw_resp_bits_pte_reserved_for_software, // @[TLB.scala:320:14] input io_ptw_resp_bits_pte_d, // @[TLB.scala:320:14] input io_ptw_resp_bits_pte_a, // @[TLB.scala:320:14] input io_ptw_resp_bits_pte_g, // @[TLB.scala:320:14] input io_ptw_resp_bits_pte_u, // @[TLB.scala:320:14] input io_ptw_resp_bits_pte_x, // @[TLB.scala:320:14] input io_ptw_resp_bits_pte_w, // @[TLB.scala:320:14] input io_ptw_resp_bits_pte_r, // @[TLB.scala:320:14] input io_ptw_resp_bits_pte_v, // @[TLB.scala:320:14] input [1:0] io_ptw_resp_bits_level, // @[TLB.scala:320:14] input io_ptw_resp_bits_homogeneous, // @[TLB.scala:320:14] input io_ptw_resp_bits_gpa_valid, // @[TLB.scala:320:14] input [38:0] io_ptw_resp_bits_gpa_bits, // @[TLB.scala:320:14] input io_ptw_resp_bits_gpa_is_pte, // @[TLB.scala:320:14] input [3:0] io_ptw_ptbr_mode, // @[TLB.scala:320:14] input [43:0] io_ptw_ptbr_ppn, // @[TLB.scala:320:14] input io_ptw_status_debug, // @[TLB.scala:320:14] input io_ptw_status_cease, // @[TLB.scala:320:14] input io_ptw_status_wfi, // @[TLB.scala:320:14] input [1:0] io_ptw_status_dprv, // @[TLB.scala:320:14] input io_ptw_status_dv, // @[TLB.scala:320:14] input [1:0] io_ptw_status_prv, // @[TLB.scala:320:14] input io_ptw_status_v, // @[TLB.scala:320:14] input io_ptw_status_sd, // @[TLB.scala:320:14] input io_ptw_status_mpv, // @[TLB.scala:320:14] input io_ptw_status_gva, // @[TLB.scala:320:14] input io_ptw_status_tsr, // @[TLB.scala:320:14] input io_ptw_status_tw, // @[TLB.scala:320:14] input io_ptw_status_tvm, // @[TLB.scala:320:14] input io_ptw_status_mxr, // @[TLB.scala:320:14] input io_ptw_status_sum, // @[TLB.scala:320:14] input io_ptw_status_mprv, // @[TLB.scala:320:14] input [1:0] io_ptw_status_fs, // @[TLB.scala:320:14] input [1:0] io_ptw_status_mpp, // @[TLB.scala:320:14] input io_ptw_status_spp, // @[TLB.scala:320:14] input io_ptw_status_mpie, // @[TLB.scala:320:14] input io_ptw_status_spie, // @[TLB.scala:320:14] input io_ptw_status_mie, // @[TLB.scala:320:14] input io_ptw_status_sie, // @[TLB.scala:320:14] input io_ptw_pmp_0_cfg_l, // @[TLB.scala:320:14] input [1:0] io_ptw_pmp_0_cfg_a, // @[TLB.scala:320:14] input io_ptw_pmp_0_cfg_x, // @[TLB.scala:320:14] input io_ptw_pmp_0_cfg_w, // @[TLB.scala:320:14] input io_ptw_pmp_0_cfg_r, // @[TLB.scala:320:14] input [29:0] io_ptw_pmp_0_addr, // @[TLB.scala:320:14] input [31:0] io_ptw_pmp_0_mask, // @[TLB.scala:320:14] input io_ptw_pmp_1_cfg_l, // @[TLB.scala:320:14] input [1:0] io_ptw_pmp_1_cfg_a, // @[TLB.scala:320:14] input io_ptw_pmp_1_cfg_x, // @[TLB.scala:320:14] input io_ptw_pmp_1_cfg_w, // @[TLB.scala:320:14] input io_ptw_pmp_1_cfg_r, // @[TLB.scala:320:14] input [29:0] io_ptw_pmp_1_addr, // @[TLB.scala:320:14] input [31:0] io_ptw_pmp_1_mask, // @[TLB.scala:320:14] input io_ptw_pmp_2_cfg_l, // @[TLB.scala:320:14] input [1:0] io_ptw_pmp_2_cfg_a, // @[TLB.scala:320:14] input io_ptw_pmp_2_cfg_x, // @[TLB.scala:320:14] input io_ptw_pmp_2_cfg_w, // @[TLB.scala:320:14] input io_ptw_pmp_2_cfg_r, // @[TLB.scala:320:14] input [29:0] io_ptw_pmp_2_addr, // @[TLB.scala:320:14] input [31:0] io_ptw_pmp_2_mask, // @[TLB.scala:320:14] input io_ptw_pmp_3_cfg_l, // @[TLB.scala:320:14] input [1:0] io_ptw_pmp_3_cfg_a, // @[TLB.scala:320:14] input io_ptw_pmp_3_cfg_x, // @[TLB.scala:320:14] input io_ptw_pmp_3_cfg_w, // @[TLB.scala:320:14] input io_ptw_pmp_3_cfg_r, // @[TLB.scala:320:14] input [29:0] io_ptw_pmp_3_addr, // @[TLB.scala:320:14] input [31:0] io_ptw_pmp_3_mask, // @[TLB.scala:320:14] input io_ptw_pmp_4_cfg_l, // @[TLB.scala:320:14] input [1:0] io_ptw_pmp_4_cfg_a, // @[TLB.scala:320:14] input io_ptw_pmp_4_cfg_x, // @[TLB.scala:320:14] input io_ptw_pmp_4_cfg_w, // @[TLB.scala:320:14] input io_ptw_pmp_4_cfg_r, // @[TLB.scala:320:14] input [29:0] io_ptw_pmp_4_addr, // @[TLB.scala:320:14] input [31:0] io_ptw_pmp_4_mask, // @[TLB.scala:320:14] input io_ptw_pmp_5_cfg_l, // @[TLB.scala:320:14] input [1:0] io_ptw_pmp_5_cfg_a, // @[TLB.scala:320:14] input io_ptw_pmp_5_cfg_x, // @[TLB.scala:320:14] input io_ptw_pmp_5_cfg_w, // @[TLB.scala:320:14] input io_ptw_pmp_5_cfg_r, // @[TLB.scala:320:14] input [29:0] io_ptw_pmp_5_addr, // @[TLB.scala:320:14] input [31:0] io_ptw_pmp_5_mask, // @[TLB.scala:320:14] input io_ptw_pmp_6_cfg_l, // @[TLB.scala:320:14] input [1:0] io_ptw_pmp_6_cfg_a, // @[TLB.scala:320:14] input io_ptw_pmp_6_cfg_x, // @[TLB.scala:320:14] input io_ptw_pmp_6_cfg_w, // @[TLB.scala:320:14] input io_ptw_pmp_6_cfg_r, // @[TLB.scala:320:14] input [29:0] io_ptw_pmp_6_addr, // @[TLB.scala:320:14] input [31:0] io_ptw_pmp_6_mask, // @[TLB.scala:320:14] input io_ptw_pmp_7_cfg_l, // @[TLB.scala:320:14] input [1:0] io_ptw_pmp_7_cfg_a, // @[TLB.scala:320:14] input io_ptw_pmp_7_cfg_x, // @[TLB.scala:320:14] input io_ptw_pmp_7_cfg_w, // @[TLB.scala:320:14] input io_ptw_pmp_7_cfg_r, // @[TLB.scala:320:14] input [29:0] io_ptw_pmp_7_addr, // @[TLB.scala:320:14] input [31:0] io_ptw_pmp_7_mask // @[TLB.scala:320:14] ); wire [19:0] _entries_barrier_12_io_y_ppn; // @[package.scala:267:25] wire _entries_barrier_12_io_y_u; // @[package.scala:267:25] wire _entries_barrier_12_io_y_ae_ptw; // @[package.scala:267:25] wire _entries_barrier_12_io_y_ae_final; // @[package.scala:267:25] wire _entries_barrier_12_io_y_ae_stage2; // @[package.scala:267:25] wire _entries_barrier_12_io_y_pf; // @[package.scala:267:25] wire _entries_barrier_12_io_y_gf; // @[package.scala:267:25] wire _entries_barrier_12_io_y_sw; // @[package.scala:267:25] wire _entries_barrier_12_io_y_sx; // @[package.scala:267:25] wire _entries_barrier_12_io_y_sr; // @[package.scala:267:25] wire _entries_barrier_12_io_y_hw; // @[package.scala:267:25] wire _entries_barrier_12_io_y_hx; // @[package.scala:267:25] wire _entries_barrier_12_io_y_hr; // @[package.scala:267:25] wire [19:0] _entries_barrier_11_io_y_ppn; // @[package.scala:267:25] wire _entries_barrier_11_io_y_u; // @[package.scala:267:25] wire _entries_barrier_11_io_y_ae_ptw; // @[package.scala:267:25] wire _entries_barrier_11_io_y_ae_final; // @[package.scala:267:25] wire _entries_barrier_11_io_y_ae_stage2; // @[package.scala:267:25] wire _entries_barrier_11_io_y_pf; // @[package.scala:267:25] wire _entries_barrier_11_io_y_gf; // @[package.scala:267:25] wire _entries_barrier_11_io_y_sw; // @[package.scala:267:25] wire _entries_barrier_11_io_y_sx; // @[package.scala:267:25] wire _entries_barrier_11_io_y_sr; // @[package.scala:267:25] wire _entries_barrier_11_io_y_hw; // @[package.scala:267:25] wire _entries_barrier_11_io_y_hx; // @[package.scala:267:25] wire _entries_barrier_11_io_y_hr; // @[package.scala:267:25] wire _entries_barrier_11_io_y_pw; // @[package.scala:267:25] wire _entries_barrier_11_io_y_px; // @[package.scala:267:25] wire _entries_barrier_11_io_y_pr; // @[package.scala:267:25] wire _entries_barrier_11_io_y_ppp; // @[package.scala:267:25] wire _entries_barrier_11_io_y_pal; // @[package.scala:267:25] wire _entries_barrier_11_io_y_paa; // @[package.scala:267:25] wire _entries_barrier_11_io_y_eff; // @[package.scala:267:25] wire _entries_barrier_11_io_y_c; // @[package.scala:267:25] wire [19:0] _entries_barrier_10_io_y_ppn; // @[package.scala:267:25] wire _entries_barrier_10_io_y_u; // @[package.scala:267:25] wire _entries_barrier_10_io_y_ae_ptw; // @[package.scala:267:25] wire _entries_barrier_10_io_y_ae_final; // @[package.scala:267:25] wire _entries_barrier_10_io_y_ae_stage2; // @[package.scala:267:25] wire _entries_barrier_10_io_y_pf; // @[package.scala:267:25] wire _entries_barrier_10_io_y_gf; // @[package.scala:267:25] wire _entries_barrier_10_io_y_sw; // @[package.scala:267:25] wire _entries_barrier_10_io_y_sx; // @[package.scala:267:25] wire _entries_barrier_10_io_y_sr; // @[package.scala:267:25] wire _entries_barrier_10_io_y_hw; // @[package.scala:267:25] wire _entries_barrier_10_io_y_hx; // @[package.scala:267:25] wire _entries_barrier_10_io_y_hr; // @[package.scala:267:25] wire _entries_barrier_10_io_y_pw; // @[package.scala:267:25] wire _entries_barrier_10_io_y_px; // @[package.scala:267:25] wire _entries_barrier_10_io_y_pr; // @[package.scala:267:25] wire _entries_barrier_10_io_y_ppp; // @[package.scala:267:25] wire _entries_barrier_10_io_y_pal; // @[package.scala:267:25] wire _entries_barrier_10_io_y_paa; // @[package.scala:267:25] wire _entries_barrier_10_io_y_eff; // @[package.scala:267:25] wire _entries_barrier_10_io_y_c; // @[package.scala:267:25] wire [19:0] _entries_barrier_9_io_y_ppn; // @[package.scala:267:25] wire _entries_barrier_9_io_y_u; // @[package.scala:267:25] wire _entries_barrier_9_io_y_ae_ptw; // @[package.scala:267:25] wire _entries_barrier_9_io_y_ae_final; // @[package.scala:267:25] wire _entries_barrier_9_io_y_ae_stage2; // @[package.scala:267:25] wire _entries_barrier_9_io_y_pf; // @[package.scala:267:25] wire _entries_barrier_9_io_y_gf; // @[package.scala:267:25] wire _entries_barrier_9_io_y_sw; // @[package.scala:267:25] wire _entries_barrier_9_io_y_sx; // @[package.scala:267:25] wire _entries_barrier_9_io_y_sr; // @[package.scala:267:25] wire _entries_barrier_9_io_y_hw; // @[package.scala:267:25] wire _entries_barrier_9_io_y_hx; // @[package.scala:267:25] wire _entries_barrier_9_io_y_hr; // @[package.scala:267:25] wire _entries_barrier_9_io_y_pw; // @[package.scala:267:25] wire _entries_barrier_9_io_y_px; // @[package.scala:267:25] wire _entries_barrier_9_io_y_pr; // @[package.scala:267:25] wire _entries_barrier_9_io_y_ppp; // @[package.scala:267:25] wire _entries_barrier_9_io_y_pal; // @[package.scala:267:25] wire _entries_barrier_9_io_y_paa; // @[package.scala:267:25] wire _entries_barrier_9_io_y_eff; // @[package.scala:267:25] wire _entries_barrier_9_io_y_c; // @[package.scala:267:25] wire [19:0] _entries_barrier_8_io_y_ppn; // @[package.scala:267:25] wire _entries_barrier_8_io_y_u; // @[package.scala:267:25] wire _entries_barrier_8_io_y_ae_ptw; // @[package.scala:267:25] wire _entries_barrier_8_io_y_ae_final; // @[package.scala:267:25] wire _entries_barrier_8_io_y_ae_stage2; // @[package.scala:267:25] wire _entries_barrier_8_io_y_pf; // @[package.scala:267:25] wire _entries_barrier_8_io_y_gf; // @[package.scala:267:25] wire _entries_barrier_8_io_y_sw; // @[package.scala:267:25] wire _entries_barrier_8_io_y_sx; // @[package.scala:267:25] wire _entries_barrier_8_io_y_sr; // @[package.scala:267:25] wire _entries_barrier_8_io_y_hw; // @[package.scala:267:25] wire _entries_barrier_8_io_y_hx; // @[package.scala:267:25] wire _entries_barrier_8_io_y_hr; // @[package.scala:267:25] wire _entries_barrier_8_io_y_pw; // @[package.scala:267:25] wire _entries_barrier_8_io_y_px; // @[package.scala:267:25] wire _entries_barrier_8_io_y_pr; // @[package.scala:267:25] wire _entries_barrier_8_io_y_ppp; // @[package.scala:267:25] wire _entries_barrier_8_io_y_pal; // @[package.scala:267:25] wire _entries_barrier_8_io_y_paa; // @[package.scala:267:25] wire _entries_barrier_8_io_y_eff; // @[package.scala:267:25] wire _entries_barrier_8_io_y_c; // @[package.scala:267:25] wire [19:0] _entries_barrier_7_io_y_ppn; // @[package.scala:267:25] wire _entries_barrier_7_io_y_u; // @[package.scala:267:25] wire _entries_barrier_7_io_y_ae_ptw; // @[package.scala:267:25] wire _entries_barrier_7_io_y_ae_final; // @[package.scala:267:25] wire _entries_barrier_7_io_y_ae_stage2; // @[package.scala:267:25] wire _entries_barrier_7_io_y_pf; // @[package.scala:267:25] wire _entries_barrier_7_io_y_gf; // @[package.scala:267:25] wire _entries_barrier_7_io_y_sw; // @[package.scala:267:25] wire _entries_barrier_7_io_y_sx; // @[package.scala:267:25] wire _entries_barrier_7_io_y_sr; // @[package.scala:267:25] wire _entries_barrier_7_io_y_hw; // @[package.scala:267:25] wire _entries_barrier_7_io_y_hx; // @[package.scala:267:25] wire _entries_barrier_7_io_y_hr; // @[package.scala:267:25] wire _entries_barrier_7_io_y_pw; // @[package.scala:267:25] wire _entries_barrier_7_io_y_px; // @[package.scala:267:25] wire _entries_barrier_7_io_y_pr; // @[package.scala:267:25] wire _entries_barrier_7_io_y_ppp; // @[package.scala:267:25] wire _entries_barrier_7_io_y_pal; // @[package.scala:267:25] wire _entries_barrier_7_io_y_paa; // @[package.scala:267:25] wire _entries_barrier_7_io_y_eff; // @[package.scala:267:25] wire _entries_barrier_7_io_y_c; // @[package.scala:267:25] wire [19:0] _entries_barrier_6_io_y_ppn; // @[package.scala:267:25] wire _entries_barrier_6_io_y_u; // @[package.scala:267:25] wire _entries_barrier_6_io_y_ae_ptw; // @[package.scala:267:25] wire _entries_barrier_6_io_y_ae_final; // @[package.scala:267:25] wire _entries_barrier_6_io_y_ae_stage2; // @[package.scala:267:25] wire _entries_barrier_6_io_y_pf; // @[package.scala:267:25] wire _entries_barrier_6_io_y_gf; // @[package.scala:267:25] wire _entries_barrier_6_io_y_sw; // @[package.scala:267:25] wire _entries_barrier_6_io_y_sx; // @[package.scala:267:25] wire _entries_barrier_6_io_y_sr; // @[package.scala:267:25] wire _entries_barrier_6_io_y_hw; // @[package.scala:267:25] wire _entries_barrier_6_io_y_hx; // @[package.scala:267:25] wire _entries_barrier_6_io_y_hr; // @[package.scala:267:25] wire _entries_barrier_6_io_y_pw; // @[package.scala:267:25] wire _entries_barrier_6_io_y_px; // @[package.scala:267:25] wire _entries_barrier_6_io_y_pr; // @[package.scala:267:25] wire _entries_barrier_6_io_y_ppp; // @[package.scala:267:25] wire _entries_barrier_6_io_y_pal; // @[package.scala:267:25] wire _entries_barrier_6_io_y_paa; // @[package.scala:267:25] wire _entries_barrier_6_io_y_eff; // @[package.scala:267:25] wire _entries_barrier_6_io_y_c; // @[package.scala:267:25] wire [19:0] _entries_barrier_5_io_y_ppn; // @[package.scala:267:25] wire _entries_barrier_5_io_y_u; // @[package.scala:267:25] wire _entries_barrier_5_io_y_ae_ptw; // @[package.scala:267:25] wire _entries_barrier_5_io_y_ae_final; // @[package.scala:267:25] wire _entries_barrier_5_io_y_ae_stage2; // @[package.scala:267:25] wire _entries_barrier_5_io_y_pf; // @[package.scala:267:25] wire _entries_barrier_5_io_y_gf; // @[package.scala:267:25] wire _entries_barrier_5_io_y_sw; // @[package.scala:267:25] wire _entries_barrier_5_io_y_sx; // @[package.scala:267:25] wire _entries_barrier_5_io_y_sr; // @[package.scala:267:25] wire _entries_barrier_5_io_y_hw; // @[package.scala:267:25] wire _entries_barrier_5_io_y_hx; // @[package.scala:267:25] wire _entries_barrier_5_io_y_hr; // @[package.scala:267:25] wire _entries_barrier_5_io_y_pw; // @[package.scala:267:25] wire _entries_barrier_5_io_y_px; // @[package.scala:267:25] wire _entries_barrier_5_io_y_pr; // @[package.scala:267:25] wire _entries_barrier_5_io_y_ppp; // @[package.scala:267:25] wire _entries_barrier_5_io_y_pal; // @[package.scala:267:25] wire _entries_barrier_5_io_y_paa; // @[package.scala:267:25] wire _entries_barrier_5_io_y_eff; // @[package.scala:267:25] wire _entries_barrier_5_io_y_c; // @[package.scala:267:25] wire [19:0] _entries_barrier_4_io_y_ppn; // @[package.scala:267:25] wire _entries_barrier_4_io_y_u; // @[package.scala:267:25] wire _entries_barrier_4_io_y_ae_ptw; // @[package.scala:267:25] wire _entries_barrier_4_io_y_ae_final; // @[package.scala:267:25] wire _entries_barrier_4_io_y_ae_stage2; // @[package.scala:267:25] wire _entries_barrier_4_io_y_pf; // @[package.scala:267:25] wire _entries_barrier_4_io_y_gf; // @[package.scala:267:25] wire _entries_barrier_4_io_y_sw; // @[package.scala:267:25] wire _entries_barrier_4_io_y_sx; // @[package.scala:267:25] wire _entries_barrier_4_io_y_sr; // @[package.scala:267:25] wire _entries_barrier_4_io_y_hw; // @[package.scala:267:25] wire _entries_barrier_4_io_y_hx; // @[package.scala:267:25] wire _entries_barrier_4_io_y_hr; // @[package.scala:267:25] wire _entries_barrier_4_io_y_pw; // @[package.scala:267:25] wire _entries_barrier_4_io_y_px; // @[package.scala:267:25] wire _entries_barrier_4_io_y_pr; // @[package.scala:267:25] wire _entries_barrier_4_io_y_ppp; // @[package.scala:267:25] wire _entries_barrier_4_io_y_pal; // @[package.scala:267:25] wire _entries_barrier_4_io_y_paa; // @[package.scala:267:25] wire _entries_barrier_4_io_y_eff; // @[package.scala:267:25] wire _entries_barrier_4_io_y_c; // @[package.scala:267:25] wire [19:0] _entries_barrier_3_io_y_ppn; // @[package.scala:267:25] wire _entries_barrier_3_io_y_u; // @[package.scala:267:25] wire _entries_barrier_3_io_y_ae_ptw; // @[package.scala:267:25] wire _entries_barrier_3_io_y_ae_final; // @[package.scala:267:25] wire _entries_barrier_3_io_y_ae_stage2; // @[package.scala:267:25] wire _entries_barrier_3_io_y_pf; // @[package.scala:267:25] wire _entries_barrier_3_io_y_gf; // @[package.scala:267:25] wire _entries_barrier_3_io_y_sw; // @[package.scala:267:25] wire _entries_barrier_3_io_y_sx; // @[package.scala:267:25] wire _entries_barrier_3_io_y_sr; // @[package.scala:267:25] wire _entries_barrier_3_io_y_hw; // @[package.scala:267:25] wire _entries_barrier_3_io_y_hx; // @[package.scala:267:25] wire _entries_barrier_3_io_y_hr; // @[package.scala:267:25] wire _entries_barrier_3_io_y_pw; // @[package.scala:267:25] wire _entries_barrier_3_io_y_px; // @[package.scala:267:25] wire _entries_barrier_3_io_y_pr; // @[package.scala:267:25] wire _entries_barrier_3_io_y_ppp; // @[package.scala:267:25] wire _entries_barrier_3_io_y_pal; // @[package.scala:267:25] wire _entries_barrier_3_io_y_paa; // @[package.scala:267:25] wire _entries_barrier_3_io_y_eff; // @[package.scala:267:25] wire _entries_barrier_3_io_y_c; // @[package.scala:267:25] wire [19:0] _entries_barrier_2_io_y_ppn; // @[package.scala:267:25] wire _entries_barrier_2_io_y_u; // @[package.scala:267:25] wire _entries_barrier_2_io_y_ae_ptw; // @[package.scala:267:25] wire _entries_barrier_2_io_y_ae_final; // @[package.scala:267:25] wire _entries_barrier_2_io_y_ae_stage2; // @[package.scala:267:25] wire _entries_barrier_2_io_y_pf; // @[package.scala:267:25] wire _entries_barrier_2_io_y_gf; // @[package.scala:267:25] wire _entries_barrier_2_io_y_sw; // @[package.scala:267:25] wire _entries_barrier_2_io_y_sx; // @[package.scala:267:25] wire _entries_barrier_2_io_y_sr; // @[package.scala:267:25] wire _entries_barrier_2_io_y_hw; // @[package.scala:267:25] wire _entries_barrier_2_io_y_hx; // @[package.scala:267:25] wire _entries_barrier_2_io_y_hr; // @[package.scala:267:25] wire _entries_barrier_2_io_y_pw; // @[package.scala:267:25] wire _entries_barrier_2_io_y_px; // @[package.scala:267:25] wire _entries_barrier_2_io_y_pr; // @[package.scala:267:25] wire _entries_barrier_2_io_y_ppp; // @[package.scala:267:25] wire _entries_barrier_2_io_y_pal; // @[package.scala:267:25] wire _entries_barrier_2_io_y_paa; // @[package.scala:267:25] wire _entries_barrier_2_io_y_eff; // @[package.scala:267:25] wire _entries_barrier_2_io_y_c; // @[package.scala:267:25] wire [19:0] _entries_barrier_1_io_y_ppn; // @[package.scala:267:25] wire _entries_barrier_1_io_y_u; // @[package.scala:267:25] wire _entries_barrier_1_io_y_ae_ptw; // @[package.scala:267:25] wire _entries_barrier_1_io_y_ae_final; // @[package.scala:267:25] wire _entries_barrier_1_io_y_ae_stage2; // @[package.scala:267:25] wire _entries_barrier_1_io_y_pf; // @[package.scala:267:25] wire _entries_barrier_1_io_y_gf; // @[package.scala:267:25] wire _entries_barrier_1_io_y_sw; // @[package.scala:267:25] wire _entries_barrier_1_io_y_sx; // @[package.scala:267:25] wire _entries_barrier_1_io_y_sr; // @[package.scala:267:25] wire _entries_barrier_1_io_y_hw; // @[package.scala:267:25] wire _entries_barrier_1_io_y_hx; // @[package.scala:267:25] wire _entries_barrier_1_io_y_hr; // @[package.scala:267:25] wire _entries_barrier_1_io_y_pw; // @[package.scala:267:25] wire _entries_barrier_1_io_y_px; // @[package.scala:267:25] wire _entries_barrier_1_io_y_pr; // @[package.scala:267:25] wire _entries_barrier_1_io_y_ppp; // @[package.scala:267:25] wire _entries_barrier_1_io_y_pal; // @[package.scala:267:25] wire _entries_barrier_1_io_y_paa; // @[package.scala:267:25] wire _entries_barrier_1_io_y_eff; // @[package.scala:267:25] wire _entries_barrier_1_io_y_c; // @[package.scala:267:25] wire [19:0] _entries_barrier_io_y_ppn; // @[package.scala:267:25] wire _entries_barrier_io_y_u; // @[package.scala:267:25] wire _entries_barrier_io_y_ae_ptw; // @[package.scala:267:25] wire _entries_barrier_io_y_ae_final; // @[package.scala:267:25] wire _entries_barrier_io_y_ae_stage2; // @[package.scala:267:25] wire _entries_barrier_io_y_pf; // @[package.scala:267:25] wire _entries_barrier_io_y_gf; // @[package.scala:267:25] wire _entries_barrier_io_y_sw; // @[package.scala:267:25] wire _entries_barrier_io_y_sx; // @[package.scala:267:25] wire _entries_barrier_io_y_sr; // @[package.scala:267:25] wire _entries_barrier_io_y_hw; // @[package.scala:267:25] wire _entries_barrier_io_y_hx; // @[package.scala:267:25] wire _entries_barrier_io_y_hr; // @[package.scala:267:25] wire _entries_barrier_io_y_pw; // @[package.scala:267:25] wire _entries_barrier_io_y_px; // @[package.scala:267:25] wire _entries_barrier_io_y_pr; // @[package.scala:267:25] wire _entries_barrier_io_y_ppp; // @[package.scala:267:25] wire _entries_barrier_io_y_pal; // @[package.scala:267:25] wire _entries_barrier_io_y_paa; // @[package.scala:267:25] wire _entries_barrier_io_y_eff; // @[package.scala:267:25] wire _entries_barrier_io_y_c; // @[package.scala:267:25] wire _pma_io_resp_r; // @[TLB.scala:422:19] wire _pma_io_resp_w; // @[TLB.scala:422:19] wire _pma_io_resp_pp; // @[TLB.scala:422:19] wire _pma_io_resp_al; // @[TLB.scala:422:19] wire _pma_io_resp_aa; // @[TLB.scala:422:19] wire _pma_io_resp_x; // @[TLB.scala:422:19] wire _pma_io_resp_eff; // @[TLB.scala:422:19] wire _pmp_io_r; // @[TLB.scala:416:19] wire _pmp_io_w; // @[TLB.scala:416:19] wire _pmp_io_x; // @[TLB.scala:416:19] wire [19:0] _mpu_ppn_barrier_io_y_ppn; // @[package.scala:267:25] wire io_req_valid_0 = io_req_valid; // @[TLB.scala:318:7] wire [39:0] io_req_bits_vaddr_0 = io_req_bits_vaddr; // @[TLB.scala:318:7] wire [1:0] io_req_bits_prv_0 = io_req_bits_prv; // @[TLB.scala:318:7] wire io_req_bits_v_0 = io_req_bits_v; // @[TLB.scala:318:7] wire io_sfence_valid_0 = io_sfence_valid; // @[TLB.scala:318:7] wire io_sfence_bits_rs1_0 = io_sfence_bits_rs1; // @[TLB.scala:318:7] wire io_sfence_bits_rs2_0 = io_sfence_bits_rs2; // @[TLB.scala:318:7] wire [38:0] io_sfence_bits_addr_0 = io_sfence_bits_addr; // @[TLB.scala:318:7] wire io_sfence_bits_asid_0 = io_sfence_bits_asid; // @[TLB.scala:318:7] wire io_sfence_bits_hv_0 = io_sfence_bits_hv; // @[TLB.scala:318:7] wire io_sfence_bits_hg_0 = io_sfence_bits_hg; // @[TLB.scala:318:7] wire io_ptw_req_ready_0 = io_ptw_req_ready; // @[TLB.scala:318:7] wire io_ptw_resp_valid_0 = io_ptw_resp_valid; // @[TLB.scala:318:7] wire io_ptw_resp_bits_ae_ptw_0 = io_ptw_resp_bits_ae_ptw; // @[TLB.scala:318:7] wire io_ptw_resp_bits_ae_final_0 = io_ptw_resp_bits_ae_final; // @[TLB.scala:318:7] wire io_ptw_resp_bits_pf_0 = io_ptw_resp_bits_pf; // @[TLB.scala:318:7] wire io_ptw_resp_bits_gf_0 = io_ptw_resp_bits_gf; // @[TLB.scala:318:7] wire io_ptw_resp_bits_hr_0 = io_ptw_resp_bits_hr; // @[TLB.scala:318:7] wire io_ptw_resp_bits_hw_0 = io_ptw_resp_bits_hw; // @[TLB.scala:318:7] wire io_ptw_resp_bits_hx_0 = io_ptw_resp_bits_hx; // @[TLB.scala:318:7] wire [9:0] io_ptw_resp_bits_pte_reserved_for_future_0 = io_ptw_resp_bits_pte_reserved_for_future; // @[TLB.scala:318:7] wire [43:0] io_ptw_resp_bits_pte_ppn_0 = io_ptw_resp_bits_pte_ppn; // @[TLB.scala:318:7] wire [1:0] io_ptw_resp_bits_pte_reserved_for_software_0 = io_ptw_resp_bits_pte_reserved_for_software; // @[TLB.scala:318:7] wire io_ptw_resp_bits_pte_d_0 = io_ptw_resp_bits_pte_d; // @[TLB.scala:318:7] wire io_ptw_resp_bits_pte_a_0 = io_ptw_resp_bits_pte_a; // @[TLB.scala:318:7] wire io_ptw_resp_bits_pte_g_0 = io_ptw_resp_bits_pte_g; // @[TLB.scala:318:7] wire io_ptw_resp_bits_pte_u_0 = io_ptw_resp_bits_pte_u; // @[TLB.scala:318:7] wire io_ptw_resp_bits_pte_x_0 = io_ptw_resp_bits_pte_x; // @[TLB.scala:318:7] wire io_ptw_resp_bits_pte_w_0 = io_ptw_resp_bits_pte_w; // @[TLB.scala:318:7] wire io_ptw_resp_bits_pte_r_0 = io_ptw_resp_bits_pte_r; // @[TLB.scala:318:7] wire io_ptw_resp_bits_pte_v_0 = io_ptw_resp_bits_pte_v; // @[TLB.scala:318:7] wire [1:0] io_ptw_resp_bits_level_0 = io_ptw_resp_bits_level; // @[TLB.scala:318:7] wire io_ptw_resp_bits_homogeneous_0 = io_ptw_resp_bits_homogeneous; // @[TLB.scala:318:7] wire io_ptw_resp_bits_gpa_valid_0 = io_ptw_resp_bits_gpa_valid; // @[TLB.scala:318:7] wire [38:0] io_ptw_resp_bits_gpa_bits_0 = io_ptw_resp_bits_gpa_bits; // @[TLB.scala:318:7] wire io_ptw_resp_bits_gpa_is_pte_0 = io_ptw_resp_bits_gpa_is_pte; // @[TLB.scala:318:7] wire [3:0] io_ptw_ptbr_mode_0 = io_ptw_ptbr_mode; // @[TLB.scala:318:7] wire [43:0] io_ptw_ptbr_ppn_0 = io_ptw_ptbr_ppn; // @[TLB.scala:318:7] wire io_ptw_status_debug_0 = io_ptw_status_debug; // @[TLB.scala:318:7] wire io_ptw_status_cease_0 = io_ptw_status_cease; // @[TLB.scala:318:7] wire io_ptw_status_wfi_0 = io_ptw_status_wfi; // @[TLB.scala:318:7] wire [1:0] io_ptw_status_dprv_0 = io_ptw_status_dprv; // @[TLB.scala:318:7] wire io_ptw_status_dv_0 = io_ptw_status_dv; // @[TLB.scala:318:7] wire [1:0] io_ptw_status_prv_0 = io_ptw_status_prv; // @[TLB.scala:318:7] wire io_ptw_status_v_0 = io_ptw_status_v; // @[TLB.scala:318:7] wire io_ptw_status_sd_0 = io_ptw_status_sd; // @[TLB.scala:318:7] wire io_ptw_status_mpv_0 = io_ptw_status_mpv; // @[TLB.scala:318:7] wire io_ptw_status_gva_0 = io_ptw_status_gva; // @[TLB.scala:318:7] wire io_ptw_status_tsr_0 = io_ptw_status_tsr; // @[TLB.scala:318:7] wire io_ptw_status_tw_0 = io_ptw_status_tw; // @[TLB.scala:318:7] wire io_ptw_status_tvm_0 = io_ptw_status_tvm; // @[TLB.scala:318:7] wire io_ptw_status_mxr_0 = io_ptw_status_mxr; // @[TLB.scala:318:7] wire io_ptw_status_sum_0 = io_ptw_status_sum; // @[TLB.scala:318:7] wire io_ptw_status_mprv_0 = io_ptw_status_mprv; // @[TLB.scala:318:7] wire [1:0] io_ptw_status_fs_0 = io_ptw_status_fs; // @[TLB.scala:318:7] wire [1:0] io_ptw_status_mpp_0 = io_ptw_status_mpp; // @[TLB.scala:318:7] wire io_ptw_status_spp_0 = io_ptw_status_spp; // @[TLB.scala:318:7] wire io_ptw_status_mpie_0 = io_ptw_status_mpie; // @[TLB.scala:318:7] wire io_ptw_status_spie_0 = io_ptw_status_spie; // @[TLB.scala:318:7] wire io_ptw_status_mie_0 = io_ptw_status_mie; // @[TLB.scala:318:7] wire io_ptw_status_sie_0 = io_ptw_status_sie; // @[TLB.scala:318:7] wire io_ptw_pmp_0_cfg_l_0 = io_ptw_pmp_0_cfg_l; // @[TLB.scala:318:7] wire [1:0] io_ptw_pmp_0_cfg_a_0 = io_ptw_pmp_0_cfg_a; // @[TLB.scala:318:7] wire io_ptw_pmp_0_cfg_x_0 = io_ptw_pmp_0_cfg_x; // @[TLB.scala:318:7] wire io_ptw_pmp_0_cfg_w_0 = io_ptw_pmp_0_cfg_w; // @[TLB.scala:318:7] wire io_ptw_pmp_0_cfg_r_0 = io_ptw_pmp_0_cfg_r; // @[TLB.scala:318:7] wire [29:0] io_ptw_pmp_0_addr_0 = io_ptw_pmp_0_addr; // @[TLB.scala:318:7] wire [31:0] io_ptw_pmp_0_mask_0 = io_ptw_pmp_0_mask; // @[TLB.scala:318:7] wire io_ptw_pmp_1_cfg_l_0 = io_ptw_pmp_1_cfg_l; // @[TLB.scala:318:7] wire [1:0] io_ptw_pmp_1_cfg_a_0 = io_ptw_pmp_1_cfg_a; // @[TLB.scala:318:7] wire io_ptw_pmp_1_cfg_x_0 = io_ptw_pmp_1_cfg_x; // @[TLB.scala:318:7] wire io_ptw_pmp_1_cfg_w_0 = io_ptw_pmp_1_cfg_w; // @[TLB.scala:318:7] wire io_ptw_pmp_1_cfg_r_0 = io_ptw_pmp_1_cfg_r; // @[TLB.scala:318:7] wire [29:0] io_ptw_pmp_1_addr_0 = io_ptw_pmp_1_addr; // @[TLB.scala:318:7] wire [31:0] io_ptw_pmp_1_mask_0 = io_ptw_pmp_1_mask; // @[TLB.scala:318:7] wire io_ptw_pmp_2_cfg_l_0 = io_ptw_pmp_2_cfg_l; // @[TLB.scala:318:7] wire [1:0] io_ptw_pmp_2_cfg_a_0 = io_ptw_pmp_2_cfg_a; // @[TLB.scala:318:7] wire io_ptw_pmp_2_cfg_x_0 = io_ptw_pmp_2_cfg_x; // @[TLB.scala:318:7] wire io_ptw_pmp_2_cfg_w_0 = io_ptw_pmp_2_cfg_w; // @[TLB.scala:318:7] wire io_ptw_pmp_2_cfg_r_0 = io_ptw_pmp_2_cfg_r; // @[TLB.scala:318:7] wire [29:0] io_ptw_pmp_2_addr_0 = io_ptw_pmp_2_addr; // @[TLB.scala:318:7] wire [31:0] io_ptw_pmp_2_mask_0 = io_ptw_pmp_2_mask; // @[TLB.scala:318:7] wire io_ptw_pmp_3_cfg_l_0 = io_ptw_pmp_3_cfg_l; // @[TLB.scala:318:7] wire [1:0] io_ptw_pmp_3_cfg_a_0 = io_ptw_pmp_3_cfg_a; // @[TLB.scala:318:7] wire io_ptw_pmp_3_cfg_x_0 = io_ptw_pmp_3_cfg_x; // @[TLB.scala:318:7] wire io_ptw_pmp_3_cfg_w_0 = io_ptw_pmp_3_cfg_w; // @[TLB.scala:318:7] wire io_ptw_pmp_3_cfg_r_0 = io_ptw_pmp_3_cfg_r; // @[TLB.scala:318:7] wire [29:0] io_ptw_pmp_3_addr_0 = io_ptw_pmp_3_addr; // @[TLB.scala:318:7] wire [31:0] io_ptw_pmp_3_mask_0 = io_ptw_pmp_3_mask; // @[TLB.scala:318:7] wire io_ptw_pmp_4_cfg_l_0 = io_ptw_pmp_4_cfg_l; // @[TLB.scala:318:7] wire [1:0] io_ptw_pmp_4_cfg_a_0 = io_ptw_pmp_4_cfg_a; // @[TLB.scala:318:7] wire io_ptw_pmp_4_cfg_x_0 = io_ptw_pmp_4_cfg_x; // @[TLB.scala:318:7] wire io_ptw_pmp_4_cfg_w_0 = io_ptw_pmp_4_cfg_w; // @[TLB.scala:318:7] wire io_ptw_pmp_4_cfg_r_0 = io_ptw_pmp_4_cfg_r; // @[TLB.scala:318:7] wire [29:0] io_ptw_pmp_4_addr_0 = io_ptw_pmp_4_addr; // @[TLB.scala:318:7] wire [31:0] io_ptw_pmp_4_mask_0 = io_ptw_pmp_4_mask; // @[TLB.scala:318:7] wire io_ptw_pmp_5_cfg_l_0 = io_ptw_pmp_5_cfg_l; // @[TLB.scala:318:7] wire [1:0] io_ptw_pmp_5_cfg_a_0 = io_ptw_pmp_5_cfg_a; // @[TLB.scala:318:7] wire io_ptw_pmp_5_cfg_x_0 = io_ptw_pmp_5_cfg_x; // @[TLB.scala:318:7] wire io_ptw_pmp_5_cfg_w_0 = io_ptw_pmp_5_cfg_w; // @[TLB.scala:318:7] wire io_ptw_pmp_5_cfg_r_0 = io_ptw_pmp_5_cfg_r; // @[TLB.scala:318:7] wire [29:0] io_ptw_pmp_5_addr_0 = io_ptw_pmp_5_addr; // @[TLB.scala:318:7] wire [31:0] io_ptw_pmp_5_mask_0 = io_ptw_pmp_5_mask; // @[TLB.scala:318:7] wire io_ptw_pmp_6_cfg_l_0 = io_ptw_pmp_6_cfg_l; // @[TLB.scala:318:7] wire [1:0] io_ptw_pmp_6_cfg_a_0 = io_ptw_pmp_6_cfg_a; // @[TLB.scala:318:7] wire io_ptw_pmp_6_cfg_x_0 = io_ptw_pmp_6_cfg_x; // @[TLB.scala:318:7] wire io_ptw_pmp_6_cfg_w_0 = io_ptw_pmp_6_cfg_w; // @[TLB.scala:318:7] wire io_ptw_pmp_6_cfg_r_0 = io_ptw_pmp_6_cfg_r; // @[TLB.scala:318:7] wire [29:0] io_ptw_pmp_6_addr_0 = io_ptw_pmp_6_addr; // @[TLB.scala:318:7] wire [31:0] io_ptw_pmp_6_mask_0 = io_ptw_pmp_6_mask; // @[TLB.scala:318:7] wire io_ptw_pmp_7_cfg_l_0 = io_ptw_pmp_7_cfg_l; // @[TLB.scala:318:7] wire [1:0] io_ptw_pmp_7_cfg_a_0 = io_ptw_pmp_7_cfg_a; // @[TLB.scala:318:7] wire io_ptw_pmp_7_cfg_x_0 = io_ptw_pmp_7_cfg_x; // @[TLB.scala:318:7] wire io_ptw_pmp_7_cfg_w_0 = io_ptw_pmp_7_cfg_w; // @[TLB.scala:318:7] wire io_ptw_pmp_7_cfg_r_0 = io_ptw_pmp_7_cfg_r; // @[TLB.scala:318:7] wire [29:0] io_ptw_pmp_7_addr_0 = io_ptw_pmp_7_addr; // @[TLB.scala:318:7] wire [31:0] io_ptw_pmp_7_mask_0 = io_ptw_pmp_7_mask; // @[TLB.scala:318:7] wire io_req_bits_passthrough = 1'h0; // @[TLB.scala:318:7] wire io_resp_gpa_is_pte = 1'h0; // @[TLB.scala:318:7] wire io_resp_pf_st = 1'h0; // @[TLB.scala:318:7] wire io_resp_gf_ld = 1'h0; // @[TLB.scala:318:7] wire io_resp_gf_st = 1'h0; // @[TLB.scala:318:7] wire io_resp_gf_inst = 1'h0; // @[TLB.scala:318:7] wire io_resp_ae_st = 1'h0; // @[TLB.scala:318:7] wire io_resp_ma_st = 1'h0; // @[TLB.scala:318:7] wire io_resp_ma_inst = 1'h0; // @[TLB.scala:318:7] wire io_resp_must_alloc = 1'h0; // @[TLB.scala:318:7] wire io_ptw_req_bits_bits_vstage1 = 1'h0; // @[TLB.scala:318:7] wire io_ptw_req_bits_bits_stage2 = 1'h0; // @[TLB.scala:318:7] wire io_ptw_resp_bits_fragmented_superpage = 1'h0; // @[TLB.scala:318:7] wire io_ptw_status_mbe = 1'h0; // @[TLB.scala:318:7] wire io_ptw_status_sbe = 1'h0; // @[TLB.scala:318:7] wire io_ptw_status_sd_rv32 = 1'h0; // @[TLB.scala:318:7] wire io_ptw_status_ube = 1'h0; // @[TLB.scala:318:7] wire io_ptw_status_upie = 1'h0; // @[TLB.scala:318:7] wire io_ptw_status_hie = 1'h0; // @[TLB.scala:318:7] wire io_ptw_status_uie = 1'h0; // @[TLB.scala:318:7] wire io_ptw_hstatus_vtsr = 1'h0; // @[TLB.scala:318:7] wire io_ptw_hstatus_vtw = 1'h0; // @[TLB.scala:318:7] wire io_ptw_hstatus_vtvm = 1'h0; // @[TLB.scala:318:7] wire io_ptw_hstatus_hu = 1'h0; // @[TLB.scala:318:7] wire io_ptw_hstatus_spvp = 1'h0; // @[TLB.scala:318:7] wire io_ptw_hstatus_spv = 1'h0; // @[TLB.scala:318:7] wire io_ptw_hstatus_gva = 1'h0; // @[TLB.scala:318:7] wire io_ptw_hstatus_vsbe = 1'h0; // @[TLB.scala:318:7] wire io_ptw_gstatus_debug = 1'h0; // @[TLB.scala:318:7] wire io_ptw_gstatus_cease = 1'h0; // @[TLB.scala:318:7] wire io_ptw_gstatus_wfi = 1'h0; // @[TLB.scala:318:7] wire io_ptw_gstatus_dv = 1'h0; // @[TLB.scala:318:7] wire io_ptw_gstatus_v = 1'h0; // @[TLB.scala:318:7] wire io_ptw_gstatus_sd = 1'h0; // @[TLB.scala:318:7] wire io_ptw_gstatus_mpv = 1'h0; // @[TLB.scala:318:7] wire io_ptw_gstatus_gva = 1'h0; // @[TLB.scala:318:7] wire io_ptw_gstatus_mbe = 1'h0; // @[TLB.scala:318:7] wire io_ptw_gstatus_sbe = 1'h0; // @[TLB.scala:318:7] wire io_ptw_gstatus_sd_rv32 = 1'h0; // @[TLB.scala:318:7] wire io_ptw_gstatus_tsr = 1'h0; // @[TLB.scala:318:7] wire io_ptw_gstatus_tw = 1'h0; // @[TLB.scala:318:7] wire io_ptw_gstatus_tvm = 1'h0; // @[TLB.scala:318:7] wire io_ptw_gstatus_mxr = 1'h0; // @[TLB.scala:318:7] wire io_ptw_gstatus_sum = 1'h0; // @[TLB.scala:318:7] wire io_ptw_gstatus_mprv = 1'h0; // @[TLB.scala:318:7] wire io_ptw_gstatus_spp = 1'h0; // @[TLB.scala:318:7] wire io_ptw_gstatus_mpie = 1'h0; // @[TLB.scala:318:7] wire io_ptw_gstatus_ube = 1'h0; // @[TLB.scala:318:7] wire io_ptw_gstatus_spie = 1'h0; // @[TLB.scala:318:7] wire io_ptw_gstatus_upie = 1'h0; // @[TLB.scala:318:7] wire io_ptw_gstatus_mie = 1'h0; // @[TLB.scala:318:7] wire io_ptw_gstatus_hie = 1'h0; // @[TLB.scala:318:7] wire io_ptw_gstatus_sie = 1'h0; // @[TLB.scala:318:7] wire io_ptw_gstatus_uie = 1'h0; // @[TLB.scala:318:7] wire io_ptw_customCSRs_csrs_0_ren = 1'h0; // @[TLB.scala:318:7] wire io_ptw_customCSRs_csrs_0_wen = 1'h0; // @[TLB.scala:318:7] wire io_ptw_customCSRs_csrs_0_stall = 1'h0; // @[TLB.scala:318:7] wire io_ptw_customCSRs_csrs_0_set = 1'h0; // @[TLB.scala:318:7] wire io_ptw_customCSRs_csrs_1_ren = 1'h0; // @[TLB.scala:318:7] wire io_ptw_customCSRs_csrs_1_wen = 1'h0; // @[TLB.scala:318:7] wire io_ptw_customCSRs_csrs_1_stall = 1'h0; // @[TLB.scala:318:7] wire io_ptw_customCSRs_csrs_1_set = 1'h0; // @[TLB.scala:318:7] wire io_kill = 1'h0; // @[TLB.scala:318:7] wire priv_v = 1'h0; // @[TLB.scala:369:34] wire _vstage1_en_T = 1'h0; // @[TLB.scala:376:38] wire _vstage1_en_T_1 = 1'h0; // @[TLB.scala:376:68] wire vstage1_en = 1'h0; // @[TLB.scala:376:48] wire _stage2_en_T = 1'h0; // @[TLB.scala:378:38] wire _stage2_en_T_1 = 1'h0; // @[TLB.scala:378:68] wire stage2_en = 1'h0; // @[TLB.scala:378:48] wire _vsatp_mode_mismatch_T = 1'h0; // @[TLB.scala:403:52] wire _vsatp_mode_mismatch_T_1 = 1'h0; // @[TLB.scala:403:37] wire vsatp_mode_mismatch = 1'h0; // @[TLB.scala:403:78] wire _superpage_hits_ignore_T = 1'h0; // @[TLB.scala:182:28] wire superpage_hits_ignore = 1'h0; // @[TLB.scala:182:34] wire _superpage_hits_ignore_T_3 = 1'h0; // @[TLB.scala:182:28] wire superpage_hits_ignore_3 = 1'h0; // @[TLB.scala:182:34] wire _superpage_hits_ignore_T_6 = 1'h0; // @[TLB.scala:182:28] wire superpage_hits_ignore_6 = 1'h0; // @[TLB.scala:182:34] wire _superpage_hits_ignore_T_9 = 1'h0; // @[TLB.scala:182:28] wire superpage_hits_ignore_9 = 1'h0; // @[TLB.scala:182:34] wire _hitsVec_ignore_T = 1'h0; // @[TLB.scala:182:28] wire hitsVec_ignore = 1'h0; // @[TLB.scala:182:34] wire _hitsVec_ignore_T_3 = 1'h0; // @[TLB.scala:182:28] wire hitsVec_ignore_3 = 1'h0; // @[TLB.scala:182:34] wire _hitsVec_ignore_T_6 = 1'h0; // @[TLB.scala:182:28] wire hitsVec_ignore_6 = 1'h0; // @[TLB.scala:182:34] wire _hitsVec_ignore_T_9 = 1'h0; // @[TLB.scala:182:28] wire hitsVec_ignore_9 = 1'h0; // @[TLB.scala:182:34] wire _hitsVec_ignore_T_12 = 1'h0; // @[TLB.scala:182:28] wire hitsVec_ignore_12 = 1'h0; // @[TLB.scala:182:34] wire refill_v = 1'h0; // @[TLB.scala:448:33] wire newEntry_ae_stage2 = 1'h0; // @[TLB.scala:449:24] wire newEntry_fragmented_superpage = 1'h0; // @[TLB.scala:449:24] wire _newEntry_ae_stage2_T_1 = 1'h0; // @[TLB.scala:456:84] wire _waddr_T = 1'h0; // @[TLB.scala:477:45] wire _mxr_T = 1'h0; // @[TLB.scala:518:36] wire _cmd_lrsc_T = 1'h0; // @[package.scala:16:47] wire _cmd_lrsc_T_1 = 1'h0; // @[package.scala:16:47] wire _cmd_lrsc_T_2 = 1'h0; // @[package.scala:81:59] wire cmd_lrsc = 1'h0; // @[TLB.scala:570:33] wire _cmd_amo_logical_T = 1'h0; // @[package.scala:16:47] wire _cmd_amo_logical_T_1 = 1'h0; // @[package.scala:16:47] wire _cmd_amo_logical_T_2 = 1'h0; // @[package.scala:16:47] wire _cmd_amo_logical_T_3 = 1'h0; // @[package.scala:16:47] wire _cmd_amo_logical_T_4 = 1'h0; // @[package.scala:81:59] wire _cmd_amo_logical_T_5 = 1'h0; // @[package.scala:81:59] wire _cmd_amo_logical_T_6 = 1'h0; // @[package.scala:81:59] wire cmd_amo_logical = 1'h0; // @[TLB.scala:571:40] wire _cmd_amo_arithmetic_T = 1'h0; // @[package.scala:16:47] wire _cmd_amo_arithmetic_T_1 = 1'h0; // @[package.scala:16:47] wire _cmd_amo_arithmetic_T_2 = 1'h0; // @[package.scala:16:47] wire _cmd_amo_arithmetic_T_3 = 1'h0; // @[package.scala:16:47] wire _cmd_amo_arithmetic_T_4 = 1'h0; // @[package.scala:16:47] wire _cmd_amo_arithmetic_T_5 = 1'h0; // @[package.scala:81:59] wire _cmd_amo_arithmetic_T_6 = 1'h0; // @[package.scala:81:59] wire _cmd_amo_arithmetic_T_7 = 1'h0; // @[package.scala:81:59] wire _cmd_amo_arithmetic_T_8 = 1'h0; // @[package.scala:81:59] wire cmd_amo_arithmetic = 1'h0; // @[TLB.scala:572:43] wire cmd_put_partial = 1'h0; // @[TLB.scala:573:41] wire _cmd_read_T_1 = 1'h0; // @[package.scala:16:47] wire _cmd_read_T_2 = 1'h0; // @[package.scala:16:47] wire _cmd_read_T_3 = 1'h0; // @[package.scala:16:47] wire _cmd_read_T_7 = 1'h0; // @[package.scala:16:47] wire _cmd_read_T_8 = 1'h0; // @[package.scala:16:47] wire _cmd_read_T_9 = 1'h0; // @[package.scala:16:47] wire _cmd_read_T_10 = 1'h0; // @[package.scala:16:47] wire _cmd_read_T_11 = 1'h0; // @[package.scala:81:59] wire _cmd_read_T_12 = 1'h0; // @[package.scala:81:59] wire _cmd_read_T_13 = 1'h0; // @[package.scala:81:59] wire _cmd_read_T_14 = 1'h0; // @[package.scala:16:47] wire _cmd_read_T_15 = 1'h0; // @[package.scala:16:47] wire _cmd_read_T_16 = 1'h0; // @[package.scala:16:47] wire _cmd_read_T_17 = 1'h0; // @[package.scala:16:47] wire _cmd_read_T_18 = 1'h0; // @[package.scala:16:47] wire _cmd_read_T_19 = 1'h0; // @[package.scala:81:59] wire _cmd_read_T_20 = 1'h0; // @[package.scala:81:59] wire _cmd_read_T_21 = 1'h0; // @[package.scala:81:59] wire _cmd_read_T_22 = 1'h0; // @[package.scala:81:59] wire _cmd_read_T_23 = 1'h0; // @[Consts.scala:87:44] wire _cmd_readx_T = 1'h0; // @[TLB.scala:575:56] wire cmd_readx = 1'h0; // @[TLB.scala:575:37] wire _cmd_write_T = 1'h0; // @[Consts.scala:90:32] wire _cmd_write_T_1 = 1'h0; // @[Consts.scala:90:49] wire _cmd_write_T_2 = 1'h0; // @[Consts.scala:90:42] wire _cmd_write_T_3 = 1'h0; // @[Consts.scala:90:66] wire _cmd_write_T_4 = 1'h0; // @[Consts.scala:90:59] wire _cmd_write_T_5 = 1'h0; // @[package.scala:16:47] wire _cmd_write_T_6 = 1'h0; // @[package.scala:16:47] wire _cmd_write_T_7 = 1'h0; // @[package.scala:16:47] wire _cmd_write_T_8 = 1'h0; // @[package.scala:16:47] wire _cmd_write_T_9 = 1'h0; // @[package.scala:81:59] wire _cmd_write_T_10 = 1'h0; // @[package.scala:81:59] wire _cmd_write_T_11 = 1'h0; // @[package.scala:81:59] wire _cmd_write_T_12 = 1'h0; // @[package.scala:16:47] wire _cmd_write_T_13 = 1'h0; // @[package.scala:16:47] wire _cmd_write_T_14 = 1'h0; // @[package.scala:16:47] wire _cmd_write_T_15 = 1'h0; // @[package.scala:16:47] wire _cmd_write_T_16 = 1'h0; // @[package.scala:16:47] wire _cmd_write_T_17 = 1'h0; // @[package.scala:81:59] wire _cmd_write_T_18 = 1'h0; // @[package.scala:81:59] wire _cmd_write_T_19 = 1'h0; // @[package.scala:81:59] wire _cmd_write_T_20 = 1'h0; // @[package.scala:81:59] wire _cmd_write_T_21 = 1'h0; // @[Consts.scala:87:44] wire cmd_write = 1'h0; // @[Consts.scala:90:76] wire _cmd_write_perms_T = 1'h0; // @[package.scala:16:47] wire _cmd_write_perms_T_1 = 1'h0; // @[package.scala:16:47] wire _cmd_write_perms_T_2 = 1'h0; // @[package.scala:81:59] wire cmd_write_perms = 1'h0; // @[TLB.scala:577:35] wire _gf_ld_array_T = 1'h0; // @[TLB.scala:600:32] wire _gf_st_array_T = 1'h0; // @[TLB.scala:601:32] wire _multipleHits_T_6 = 1'h0; // @[Misc.scala:183:37] wire _multipleHits_T_15 = 1'h0; // @[Misc.scala:183:37] wire _multipleHits_T_27 = 1'h0; // @[Misc.scala:183:37] wire _multipleHits_T_35 = 1'h0; // @[Misc.scala:183:37] wire _multipleHits_T_40 = 1'h0; // @[Misc.scala:183:37] wire _io_resp_pf_st_T = 1'h0; // @[TLB.scala:634:28] wire _io_resp_pf_st_T_2 = 1'h0; // @[TLB.scala:634:72] wire _io_resp_pf_st_T_3 = 1'h0; // @[TLB.scala:634:48] wire _io_resp_gf_ld_T = 1'h0; // @[TLB.scala:637:29] wire _io_resp_gf_ld_T_2 = 1'h0; // @[TLB.scala:637:66] wire _io_resp_gf_ld_T_3 = 1'h0; // @[TLB.scala:637:42] wire _io_resp_gf_st_T = 1'h0; // @[TLB.scala:638:29] wire _io_resp_gf_st_T_2 = 1'h0; // @[TLB.scala:638:73] wire _io_resp_gf_st_T_3 = 1'h0; // @[TLB.scala:638:49] wire _io_resp_gf_inst_T_1 = 1'h0; // @[TLB.scala:639:56] wire _io_resp_gf_inst_T_2 = 1'h0; // @[TLB.scala:639:30] wire _io_resp_ae_st_T_1 = 1'h0; // @[TLB.scala:642:41] wire _io_resp_ma_st_T = 1'h0; // @[TLB.scala:646:31] wire _io_resp_must_alloc_T_1 = 1'h0; // @[TLB.scala:649:51] wire _io_resp_gpa_is_pte_T = 1'h0; // @[TLB.scala:655:36] wire hv = 1'h0; // @[TLB.scala:721:36] wire hg = 1'h0; // @[TLB.scala:722:36] wire hv_1 = 1'h0; // @[TLB.scala:721:36] wire hg_1 = 1'h0; // @[TLB.scala:722:36] wire hv_2 = 1'h0; // @[TLB.scala:721:36] wire hg_2 = 1'h0; // @[TLB.scala:722:36] wire hv_3 = 1'h0; // @[TLB.scala:721:36] wire hg_3 = 1'h0; // @[TLB.scala:722:36] wire hv_4 = 1'h0; // @[TLB.scala:721:36] wire hg_4 = 1'h0; // @[TLB.scala:722:36] wire hv_5 = 1'h0; // @[TLB.scala:721:36] wire hg_5 = 1'h0; // @[TLB.scala:722:36] wire hv_6 = 1'h0; // @[TLB.scala:721:36] wire hg_6 = 1'h0; // @[TLB.scala:722:36] wire hv_7 = 1'h0; // @[TLB.scala:721:36] wire hg_7 = 1'h0; // @[TLB.scala:722:36] wire hv_8 = 1'h0; // @[TLB.scala:721:36] wire hg_8 = 1'h0; // @[TLB.scala:722:36] wire _ignore_T = 1'h0; // @[TLB.scala:182:28] wire ignore = 1'h0; // @[TLB.scala:182:34] wire hv_9 = 1'h0; // @[TLB.scala:721:36] wire hg_9 = 1'h0; // @[TLB.scala:722:36] wire _ignore_T_3 = 1'h0; // @[TLB.scala:182:28] wire ignore_3 = 1'h0; // @[TLB.scala:182:34] wire hv_10 = 1'h0; // @[TLB.scala:721:36] wire hg_10 = 1'h0; // @[TLB.scala:722:36] wire _ignore_T_6 = 1'h0; // @[TLB.scala:182:28] wire ignore_6 = 1'h0; // @[TLB.scala:182:34] wire hv_11 = 1'h0; // @[TLB.scala:721:36] wire hg_11 = 1'h0; // @[TLB.scala:722:36] wire _ignore_T_9 = 1'h0; // @[TLB.scala:182:28] wire ignore_9 = 1'h0; // @[TLB.scala:182:34] wire hv_12 = 1'h0; // @[TLB.scala:721:36] wire hg_12 = 1'h0; // @[TLB.scala:722:36] wire _ignore_T_12 = 1'h0; // @[TLB.scala:182:28] wire ignore_12 = 1'h0; // @[TLB.scala:182:34] wire [15:0] io_ptw_ptbr_asid = 16'h0; // @[TLB.scala:318:7] wire [15:0] io_ptw_hgatp_asid = 16'h0; // @[TLB.scala:318:7] wire [15:0] io_ptw_vsatp_asid = 16'h0; // @[TLB.scala:318:7] wire [15:0] satp_asid = 16'h0; // @[TLB.scala:373:17] wire [31:0] io_ptw_status_isa = 32'h14112D; // @[TLB.scala:318:7] wire [22:0] io_ptw_status_zero2 = 23'h0; // @[TLB.scala:318:7] wire [22:0] io_ptw_gstatus_zero2 = 23'h0; // @[TLB.scala:318:7] wire [7:0] io_ptw_status_zero1 = 8'h0; // @[TLB.scala:318:7] wire [7:0] io_ptw_gstatus_zero1 = 8'h0; // @[TLB.scala:318:7] wire [1:0] io_ptw_status_xs = 2'h0; // @[TLB.scala:318:7] wire [1:0] io_ptw_status_vs = 2'h0; // @[TLB.scala:318:7] wire [1:0] io_ptw_hstatus_vsxl = 2'h0; // @[TLB.scala:318:7] wire [1:0] io_ptw_hstatus_zero3 = 2'h0; // @[TLB.scala:318:7] wire [1:0] io_ptw_hstatus_zero2 = 2'h0; // @[TLB.scala:318:7] wire [1:0] io_ptw_gstatus_dprv = 2'h0; // @[TLB.scala:318:7] wire [1:0] io_ptw_gstatus_prv = 2'h0; // @[TLB.scala:318:7] wire [1:0] io_ptw_gstatus_sxl = 2'h0; // @[TLB.scala:318:7] wire [1:0] io_ptw_gstatus_uxl = 2'h0; // @[TLB.scala:318:7] wire [1:0] io_ptw_gstatus_xs = 2'h0; // @[TLB.scala:318:7] wire [1:0] io_ptw_gstatus_fs = 2'h0; // @[TLB.scala:318:7] wire [1:0] io_ptw_gstatus_mpp = 2'h0; // @[TLB.scala:318:7] wire [1:0] io_ptw_gstatus_vs = 2'h0; // @[TLB.scala:318:7] wire [1:0] io_ptw_pmp_0_cfg_res = 2'h0; // @[TLB.scala:318:7] wire [1:0] io_ptw_pmp_1_cfg_res = 2'h0; // @[TLB.scala:318:7] wire [1:0] io_ptw_pmp_2_cfg_res = 2'h0; // @[TLB.scala:318:7] wire [1:0] io_ptw_pmp_3_cfg_res = 2'h0; // @[TLB.scala:318:7] wire [1:0] io_ptw_pmp_4_cfg_res = 2'h0; // @[TLB.scala:318:7] wire [1:0] io_ptw_pmp_5_cfg_res = 2'h0; // @[TLB.scala:318:7] wire [1:0] io_ptw_pmp_6_cfg_res = 2'h0; // @[TLB.scala:318:7] wire [1:0] io_ptw_pmp_7_cfg_res = 2'h0; // @[TLB.scala:318:7] wire [1:0] io_req_bits_size = 2'h3; // @[TLB.scala:318:7] wire [1:0] io_resp_size = 2'h3; // @[TLB.scala:318:7] wire [4:0] io_req_bits_cmd = 5'h0; // @[TLB.scala:318:7] wire [4:0] io_resp_cmd = 5'h0; // @[TLB.scala:318:7] wire [4:0] io_ptw_hstatus_zero1 = 5'h0; // @[TLB.scala:318:7] wire io_ptw_req_bits_valid = 1'h1; // @[TLB.scala:318:7] wire _vm_enabled_T_2 = 1'h1; // @[TLB.scala:399:64] wire _vsatp_mode_mismatch_T_2 = 1'h1; // @[TLB.scala:403:81] wire _homogeneous_T_59 = 1'h1; // @[TLBPermissions.scala:87:22] wire superpage_hits_ignore_2 = 1'h1; // @[TLB.scala:182:34] wire _superpage_hits_T_13 = 1'h1; // @[TLB.scala:183:40] wire superpage_hits_ignore_5 = 1'h1; // @[TLB.scala:182:34] wire _superpage_hits_T_27 = 1'h1; // @[TLB.scala:183:40] wire superpage_hits_ignore_8 = 1'h1; // @[TLB.scala:182:34] wire _superpage_hits_T_41 = 1'h1; // @[TLB.scala:183:40] wire superpage_hits_ignore_11 = 1'h1; // @[TLB.scala:182:34] wire _superpage_hits_T_55 = 1'h1; // @[TLB.scala:183:40] wire hitsVec_ignore_2 = 1'h1; // @[TLB.scala:182:34] wire _hitsVec_T_61 = 1'h1; // @[TLB.scala:183:40] wire hitsVec_ignore_5 = 1'h1; // @[TLB.scala:182:34] wire _hitsVec_T_76 = 1'h1; // @[TLB.scala:183:40] wire hitsVec_ignore_8 = 1'h1; // @[TLB.scala:182:34] wire _hitsVec_T_91 = 1'h1; // @[TLB.scala:183:40] wire hitsVec_ignore_11 = 1'h1; // @[TLB.scala:182:34] wire _hitsVec_T_106 = 1'h1; // @[TLB.scala:183:40] wire ppn_ignore_1 = 1'h1; // @[TLB.scala:197:34] wire ppn_ignore_3 = 1'h1; // @[TLB.scala:197:34] wire ppn_ignore_5 = 1'h1; // @[TLB.scala:197:34] wire ppn_ignore_7 = 1'h1; // @[TLB.scala:197:34] wire _stage2_bypass_T = 1'h1; // @[TLB.scala:523:42] wire _bad_va_T_1 = 1'h1; // @[TLB.scala:560:26] wire _cmd_read_T = 1'h1; // @[package.scala:16:47] wire _cmd_read_T_4 = 1'h1; // @[package.scala:81:59] wire _cmd_read_T_5 = 1'h1; // @[package.scala:81:59] wire _cmd_read_T_6 = 1'h1; // @[package.scala:81:59] wire cmd_read = 1'h1; // @[Consts.scala:89:68] wire _gpa_hits_hit_mask_T_3 = 1'h1; // @[TLB.scala:606:107] wire _tlb_miss_T = 1'h1; // @[TLB.scala:613:32] wire _io_resp_gpa_page_T = 1'h1; // @[TLB.scala:657:20] wire _io_ptw_req_bits_valid_T = 1'h1; // @[TLB.scala:663:28] wire ignore_2 = 1'h1; // @[TLB.scala:182:34] wire ignore_5 = 1'h1; // @[TLB.scala:182:34] wire ignore_8 = 1'h1; // @[TLB.scala:182:34] wire ignore_11 = 1'h1; // @[TLB.scala:182:34] wire [3:0] io_ptw_hgatp_mode = 4'h0; // @[TLB.scala:318:7] wire [3:0] io_ptw_vsatp_mode = 4'h0; // @[TLB.scala:318:7] wire [43:0] io_ptw_hgatp_ppn = 44'h0; // @[TLB.scala:318:7] wire [43:0] io_ptw_vsatp_ppn = 44'h0; // @[TLB.scala:318:7] wire [1:0] io_ptw_status_sxl = 2'h2; // @[TLB.scala:318:7] wire [1:0] io_ptw_status_uxl = 2'h2; // @[TLB.scala:318:7] wire [29:0] io_ptw_hstatus_zero6 = 30'h0; // @[TLB.scala:318:7] wire [8:0] io_ptw_hstatus_zero5 = 9'h0; // @[TLB.scala:318:7] wire [5:0] io_ptw_hstatus_vgein = 6'h0; // @[TLB.scala:318:7] wire [31:0] io_ptw_gstatus_isa = 32'h0; // @[TLB.scala:318:7] wire [63:0] io_ptw_customCSRs_csrs_0_wdata = 64'h0; // @[TLB.scala:318:7] wire [63:0] io_ptw_customCSRs_csrs_0_value = 64'h0; // @[TLB.scala:318:7] wire [63:0] io_ptw_customCSRs_csrs_0_sdata = 64'h0; // @[TLB.scala:318:7] wire [63:0] io_ptw_customCSRs_csrs_1_wdata = 64'h0; // @[TLB.scala:318:7] wire [63:0] io_ptw_customCSRs_csrs_1_value = 64'h0; // @[TLB.scala:318:7] wire [63:0] io_ptw_customCSRs_csrs_1_sdata = 64'h0; // @[TLB.scala:318:7] wire [13:0] _ae_array_T_2 = 14'h0; // @[TLB.scala:583:8] wire [13:0] _ae_st_array_T_2 = 14'h0; // @[TLB.scala:588:8] wire [13:0] _ae_st_array_T_4 = 14'h0; // @[TLB.scala:589:8] wire [13:0] _ae_st_array_T_5 = 14'h0; // @[TLB.scala:588:53] wire [13:0] _ae_st_array_T_7 = 14'h0; // @[TLB.scala:590:8] wire [13:0] _ae_st_array_T_8 = 14'h0; // @[TLB.scala:589:53] wire [13:0] _ae_st_array_T_10 = 14'h0; // @[TLB.scala:591:8] wire [13:0] ae_st_array = 14'h0; // @[TLB.scala:590:53] wire [13:0] _must_alloc_array_T_1 = 14'h0; // @[TLB.scala:593:8] wire [13:0] _must_alloc_array_T_3 = 14'h0; // @[TLB.scala:594:8] wire [13:0] _must_alloc_array_T_4 = 14'h0; // @[TLB.scala:593:43] wire [13:0] _must_alloc_array_T_6 = 14'h0; // @[TLB.scala:595:8] wire [13:0] _must_alloc_array_T_7 = 14'h0; // @[TLB.scala:594:43] wire [13:0] _must_alloc_array_T_9 = 14'h0; // @[TLB.scala:596:8] wire [13:0] must_alloc_array = 14'h0; // @[TLB.scala:595:46] wire [13:0] pf_st_array = 14'h0; // @[TLB.scala:598:24] wire [13:0] _gf_ld_array_T_2 = 14'h0; // @[TLB.scala:600:46] wire [13:0] gf_ld_array = 14'h0; // @[TLB.scala:600:24] wire [13:0] _gf_st_array_T_1 = 14'h0; // @[TLB.scala:601:53] wire [13:0] gf_st_array = 14'h0; // @[TLB.scala:601:24] wire [13:0] _gf_inst_array_T = 14'h0; // @[TLB.scala:602:36] wire [13:0] gf_inst_array = 14'h0; // @[TLB.scala:602:26] wire [13:0] _io_resp_pf_st_T_1 = 14'h0; // @[TLB.scala:634:64] wire [13:0] _io_resp_gf_ld_T_1 = 14'h0; // @[TLB.scala:637:58] wire [13:0] _io_resp_gf_st_T_1 = 14'h0; // @[TLB.scala:638:65] wire [13:0] _io_resp_gf_inst_T = 14'h0; // @[TLB.scala:639:48] wire [13:0] _io_resp_ae_st_T = 14'h0; // @[TLB.scala:642:33] wire [13:0] _io_resp_must_alloc_T = 14'h0; // @[TLB.scala:649:43] wire [6:0] _state_vec_WIRE_0 = 7'h0; // @[Replacement.scala:305:25] wire [12:0] stage2_bypass = 13'h1FFF; // @[TLB.scala:523:27] wire [12:0] _hr_array_T_4 = 13'h1FFF; // @[TLB.scala:524:111] wire [12:0] _hw_array_T_1 = 13'h1FFF; // @[TLB.scala:525:55] wire [12:0] _hx_array_T_1 = 13'h1FFF; // @[TLB.scala:526:55] wire [12:0] _gpa_hits_hit_mask_T_4 = 13'h1FFF; // @[TLB.scala:606:88] wire [12:0] gpa_hits_hit_mask = 13'h1FFF; // @[TLB.scala:606:82] wire [12:0] _gpa_hits_T_1 = 13'h1FFF; // @[TLB.scala:607:16] wire [12:0] gpa_hits = 13'h1FFF; // @[TLB.scala:607:14] wire [12:0] _stage1_bypass_T = 13'h0; // @[TLB.scala:517:27] wire [12:0] stage1_bypass = 13'h0; // @[TLB.scala:517:61] wire [12:0] _gpa_hits_T = 13'h0; // @[TLB.scala:607:30] wire [13:0] hr_array = 14'h3FFF; // @[TLB.scala:524:21] wire [13:0] hw_array = 14'h3FFF; // @[TLB.scala:525:21] wire [13:0] hx_array = 14'h3FFF; // @[TLB.scala:526:21] wire [13:0] _must_alloc_array_T_8 = 14'h3FFF; // @[TLB.scala:596:19] wire [13:0] _gf_ld_array_T_1 = 14'h3FFF; // @[TLB.scala:600:50] wire [3:0] _misaligned_T_2 = 4'h7; // @[TLB.scala:550:69] wire [4:0] _misaligned_T_1 = 5'h7; // @[TLB.scala:550:69] wire [3:0] _misaligned_T = 4'h8; // @[OneHot.scala:58:35] wire _io_req_ready_T; // @[TLB.scala:631:25] wire _io_resp_miss_T_2; // @[TLB.scala:651:64] wire [31:0] _io_resp_paddr_T_1; // @[TLB.scala:652:23] wire [39:0] _io_resp_gpa_T; // @[TLB.scala:659:8] wire _io_resp_pf_ld_T_3; // @[TLB.scala:633:41] wire _io_resp_pf_inst_T_2; // @[TLB.scala:635:29] wire _io_resp_ae_ld_T_1; // @[TLB.scala:641:41] wire _io_resp_ae_inst_T_2; // @[TLB.scala:643:41] wire _io_resp_ma_ld_T; // @[TLB.scala:645:31] wire _io_resp_cacheable_T_1; // @[TLB.scala:648:41] wire _io_resp_prefetchable_T_2; // @[TLB.scala:650:59] wire _io_ptw_req_valid_T; // @[TLB.scala:662:29] wire do_refill = io_ptw_resp_valid_0; // @[TLB.scala:318:7, :408:29] wire newEntry_ae_ptw = io_ptw_resp_bits_ae_ptw_0; // @[TLB.scala:318:7, :449:24] wire newEntry_ae_final = io_ptw_resp_bits_ae_final_0; // @[TLB.scala:318:7, :449:24] wire newEntry_pf = io_ptw_resp_bits_pf_0; // @[TLB.scala:318:7, :449:24] wire newEntry_gf = io_ptw_resp_bits_gf_0; // @[TLB.scala:318:7, :449:24] wire newEntry_hr = io_ptw_resp_bits_hr_0; // @[TLB.scala:318:7, :449:24] wire newEntry_hw = io_ptw_resp_bits_hw_0; // @[TLB.scala:318:7, :449:24] wire newEntry_hx = io_ptw_resp_bits_hx_0; // @[TLB.scala:318:7, :449:24] wire newEntry_u = io_ptw_resp_bits_pte_u_0; // @[TLB.scala:318:7, :449:24] wire [1:0] _special_entry_level_T = io_ptw_resp_bits_level_0; // @[package.scala:163:13] wire [3:0] satp_mode = io_ptw_ptbr_mode_0; // @[TLB.scala:318:7, :373:17] wire [43:0] satp_ppn = io_ptw_ptbr_ppn_0; // @[TLB.scala:318:7, :373:17] wire mxr = io_ptw_status_mxr_0; // @[TLB.scala:318:7, :518:31] wire sum = io_ptw_status_sum_0; // @[TLB.scala:318:7, :510:16] wire io_req_ready; // @[TLB.scala:318:7] wire io_resp_pf_ld_0; // @[TLB.scala:318:7] wire io_resp_pf_inst_0; // @[TLB.scala:318:7] wire io_resp_ae_ld_0; // @[TLB.scala:318:7] wire io_resp_ae_inst_0; // @[TLB.scala:318:7] wire io_resp_ma_ld_0; // @[TLB.scala:318:7] wire io_resp_miss_0; // @[TLB.scala:318:7] wire [31:0] io_resp_paddr_0; // @[TLB.scala:318:7] wire [39:0] io_resp_gpa_0; // @[TLB.scala:318:7] wire io_resp_cacheable_0; // @[TLB.scala:318:7] wire io_resp_prefetchable_0; // @[TLB.scala:318:7] wire [26:0] io_ptw_req_bits_bits_addr_0; // @[TLB.scala:318:7] wire io_ptw_req_bits_bits_need_gpa_0; // @[TLB.scala:318:7] wire io_ptw_req_valid_0; // @[TLB.scala:318:7] wire [26:0] vpn = io_req_bits_vaddr_0[38:12]; // @[TLB.scala:318:7, :335:30] wire [26:0] _ppn_T_5 = vpn; // @[TLB.scala:198:28, :335:30] wire [26:0] _ppn_T_13 = vpn; // @[TLB.scala:198:28, :335:30] wire [26:0] _ppn_T_21 = vpn; // @[TLB.scala:198:28, :335:30] wire [26:0] _ppn_T_29 = vpn; // @[TLB.scala:198:28, :335:30] reg [1:0] sectored_entries_0_0_level; // @[TLB.scala:339:29] reg [26:0] sectored_entries_0_0_tag_vpn; // @[TLB.scala:339:29] reg sectored_entries_0_0_tag_v; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_0_data_0; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_0_data_1; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_0_data_2; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_0_data_3; // @[TLB.scala:339:29] reg sectored_entries_0_0_valid_0; // @[TLB.scala:339:29] reg sectored_entries_0_0_valid_1; // @[TLB.scala:339:29] reg sectored_entries_0_0_valid_2; // @[TLB.scala:339:29] reg sectored_entries_0_0_valid_3; // @[TLB.scala:339:29] reg [1:0] sectored_entries_0_1_level; // @[TLB.scala:339:29] reg [26:0] sectored_entries_0_1_tag_vpn; // @[TLB.scala:339:29] reg sectored_entries_0_1_tag_v; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_1_data_0; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_1_data_1; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_1_data_2; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_1_data_3; // @[TLB.scala:339:29] reg sectored_entries_0_1_valid_0; // @[TLB.scala:339:29] reg sectored_entries_0_1_valid_1; // @[TLB.scala:339:29] reg sectored_entries_0_1_valid_2; // @[TLB.scala:339:29] reg sectored_entries_0_1_valid_3; // @[TLB.scala:339:29] reg [1:0] sectored_entries_0_2_level; // @[TLB.scala:339:29] reg [26:0] sectored_entries_0_2_tag_vpn; // @[TLB.scala:339:29] reg sectored_entries_0_2_tag_v; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_2_data_0; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_2_data_1; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_2_data_2; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_2_data_3; // @[TLB.scala:339:29] reg sectored_entries_0_2_valid_0; // @[TLB.scala:339:29] reg sectored_entries_0_2_valid_1; // @[TLB.scala:339:29] reg sectored_entries_0_2_valid_2; // @[TLB.scala:339:29] reg sectored_entries_0_2_valid_3; // @[TLB.scala:339:29] reg [1:0] sectored_entries_0_3_level; // @[TLB.scala:339:29] reg [26:0] sectored_entries_0_3_tag_vpn; // @[TLB.scala:339:29] reg sectored_entries_0_3_tag_v; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_3_data_0; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_3_data_1; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_3_data_2; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_3_data_3; // @[TLB.scala:339:29] reg sectored_entries_0_3_valid_0; // @[TLB.scala:339:29] reg sectored_entries_0_3_valid_1; // @[TLB.scala:339:29] reg sectored_entries_0_3_valid_2; // @[TLB.scala:339:29] reg sectored_entries_0_3_valid_3; // @[TLB.scala:339:29] reg [1:0] sectored_entries_0_4_level; // @[TLB.scala:339:29] reg [26:0] sectored_entries_0_4_tag_vpn; // @[TLB.scala:339:29] reg sectored_entries_0_4_tag_v; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_4_data_0; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_4_data_1; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_4_data_2; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_4_data_3; // @[TLB.scala:339:29] reg sectored_entries_0_4_valid_0; // @[TLB.scala:339:29] reg sectored_entries_0_4_valid_1; // @[TLB.scala:339:29] reg sectored_entries_0_4_valid_2; // @[TLB.scala:339:29] reg sectored_entries_0_4_valid_3; // @[TLB.scala:339:29] reg [1:0] sectored_entries_0_5_level; // @[TLB.scala:339:29] reg [26:0] sectored_entries_0_5_tag_vpn; // @[TLB.scala:339:29] reg sectored_entries_0_5_tag_v; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_5_data_0; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_5_data_1; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_5_data_2; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_5_data_3; // @[TLB.scala:339:29] reg sectored_entries_0_5_valid_0; // @[TLB.scala:339:29] reg sectored_entries_0_5_valid_1; // @[TLB.scala:339:29] reg sectored_entries_0_5_valid_2; // @[TLB.scala:339:29] reg sectored_entries_0_5_valid_3; // @[TLB.scala:339:29] reg [1:0] sectored_entries_0_6_level; // @[TLB.scala:339:29] reg [26:0] sectored_entries_0_6_tag_vpn; // @[TLB.scala:339:29] reg sectored_entries_0_6_tag_v; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_6_data_0; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_6_data_1; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_6_data_2; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_6_data_3; // @[TLB.scala:339:29] reg sectored_entries_0_6_valid_0; // @[TLB.scala:339:29] reg sectored_entries_0_6_valid_1; // @[TLB.scala:339:29] reg sectored_entries_0_6_valid_2; // @[TLB.scala:339:29] reg sectored_entries_0_6_valid_3; // @[TLB.scala:339:29] reg [1:0] sectored_entries_0_7_level; // @[TLB.scala:339:29] reg [26:0] sectored_entries_0_7_tag_vpn; // @[TLB.scala:339:29] reg sectored_entries_0_7_tag_v; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_7_data_0; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_7_data_1; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_7_data_2; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_7_data_3; // @[TLB.scala:339:29] reg sectored_entries_0_7_valid_0; // @[TLB.scala:339:29] reg sectored_entries_0_7_valid_1; // @[TLB.scala:339:29] reg sectored_entries_0_7_valid_2; // @[TLB.scala:339:29] reg sectored_entries_0_7_valid_3; // @[TLB.scala:339:29] reg [1:0] superpage_entries_0_level; // @[TLB.scala:341:30] reg [26:0] superpage_entries_0_tag_vpn; // @[TLB.scala:341:30] reg superpage_entries_0_tag_v; // @[TLB.scala:341:30] reg [41:0] superpage_entries_0_data_0; // @[TLB.scala:341:30] wire [41:0] _entries_WIRE_17 = superpage_entries_0_data_0; // @[TLB.scala:170:77, :341:30] reg superpage_entries_0_valid_0; // @[TLB.scala:341:30] reg [1:0] superpage_entries_1_level; // @[TLB.scala:341:30] reg [26:0] superpage_entries_1_tag_vpn; // @[TLB.scala:341:30] reg superpage_entries_1_tag_v; // @[TLB.scala:341:30] reg [41:0] superpage_entries_1_data_0; // @[TLB.scala:341:30] wire [41:0] _entries_WIRE_19 = superpage_entries_1_data_0; // @[TLB.scala:170:77, :341:30] reg superpage_entries_1_valid_0; // @[TLB.scala:341:30] reg [1:0] superpage_entries_2_level; // @[TLB.scala:341:30] reg [26:0] superpage_entries_2_tag_vpn; // @[TLB.scala:341:30] reg superpage_entries_2_tag_v; // @[TLB.scala:341:30] reg [41:0] superpage_entries_2_data_0; // @[TLB.scala:341:30] wire [41:0] _entries_WIRE_21 = superpage_entries_2_data_0; // @[TLB.scala:170:77, :341:30] reg superpage_entries_2_valid_0; // @[TLB.scala:341:30] reg [1:0] superpage_entries_3_level; // @[TLB.scala:341:30] reg [26:0] superpage_entries_3_tag_vpn; // @[TLB.scala:341:30] reg superpage_entries_3_tag_v; // @[TLB.scala:341:30] reg [41:0] superpage_entries_3_data_0; // @[TLB.scala:341:30] wire [41:0] _entries_WIRE_23 = superpage_entries_3_data_0; // @[TLB.scala:170:77, :341:30] reg superpage_entries_3_valid_0; // @[TLB.scala:341:30] reg [1:0] special_entry_level; // @[TLB.scala:346:56] reg [26:0] special_entry_tag_vpn; // @[TLB.scala:346:56] reg special_entry_tag_v; // @[TLB.scala:346:56] reg [41:0] special_entry_data_0; // @[TLB.scala:346:56] wire [41:0] _mpu_ppn_WIRE_1 = special_entry_data_0; // @[TLB.scala:170:77, :346:56] wire [41:0] _entries_WIRE_25 = special_entry_data_0; // @[TLB.scala:170:77, :346:56] reg special_entry_valid_0; // @[TLB.scala:346:56] reg [1:0] state; // @[TLB.scala:352:22] reg [26:0] r_refill_tag; // @[TLB.scala:354:25] assign io_ptw_req_bits_bits_addr_0 = r_refill_tag; // @[TLB.scala:318:7, :354:25] reg [1:0] r_superpage_repl_addr; // @[TLB.scala:355:34] wire [1:0] waddr = r_superpage_repl_addr; // @[TLB.scala:355:34, :477:22] reg [2:0] r_sectored_repl_addr; // @[TLB.scala:356:33] reg r_sectored_hit_valid; // @[TLB.scala:357:27] reg [2:0] r_sectored_hit_bits; // @[TLB.scala:357:27] reg r_superpage_hit_valid; // @[TLB.scala:358:28] reg [1:0] r_superpage_hit_bits; // @[TLB.scala:358:28] reg r_need_gpa; // @[TLB.scala:361:23] assign io_ptw_req_bits_bits_need_gpa_0 = r_need_gpa; // @[TLB.scala:318:7, :361:23] reg r_gpa_valid; // @[TLB.scala:362:24] reg [38:0] r_gpa; // @[TLB.scala:363:18] reg [26:0] r_gpa_vpn; // @[TLB.scala:364:22] reg r_gpa_is_pte; // @[TLB.scala:365:25] wire priv_s = io_req_bits_prv_0[0]; // @[TLB.scala:318:7, :370:20] wire priv_uses_vm = ~(io_req_bits_prv_0[1]); // @[TLB.scala:318:7, :372:27] wire _stage1_en_T = satp_mode[3]; // @[TLB.scala:373:17, :374:41] wire stage1_en = _stage1_en_T; // @[TLB.scala:374:{29,41}] wire _vm_enabled_T = stage1_en; // @[TLB.scala:374:29, :399:31] wire _vm_enabled_T_1 = _vm_enabled_T & priv_uses_vm; // @[TLB.scala:372:27, :399:{31,45}] wire vm_enabled = _vm_enabled_T_1; // @[TLB.scala:399:{45,61}] wire _mpu_ppn_T = vm_enabled; // @[TLB.scala:399:61, :413:32] wire _tlb_miss_T_1 = vm_enabled; // @[TLB.scala:399:61, :613:29] wire [19:0] refill_ppn = io_ptw_resp_bits_pte_ppn_0[19:0]; // @[TLB.scala:318:7, :406:44] wire [19:0] newEntry_ppn = io_ptw_resp_bits_pte_ppn_0[19:0]; // @[TLB.scala:318:7, :406:44, :449:24] wire _mpu_priv_T = do_refill; // @[TLB.scala:408:29, :415:52] wire _io_resp_miss_T = do_refill; // @[TLB.scala:408:29, :651:29] wire _T_51 = state == 2'h1; // @[package.scala:16:47] wire _invalidate_refill_T; // @[package.scala:16:47] assign _invalidate_refill_T = _T_51; // @[package.scala:16:47] assign _io_ptw_req_valid_T = _T_51; // @[package.scala:16:47] wire _invalidate_refill_T_1 = &state; // @[package.scala:16:47] wire _invalidate_refill_T_2 = _invalidate_refill_T \| _invalidate_refill_T_1; // @[package.scala:16:47, :81:59] wire invalidate_refill = _invalidate_refill_T_2 \| io_sfence_valid_0; // @[package.scala:81:59] wire [19:0] _mpu_ppn_T_23; // @[TLB.scala:170:77] wire _mpu_ppn_T_22; // @[TLB.scala:170:77] wire _mpu_ppn_T_21; // @[TLB.scala:170:77] wire _mpu_ppn_T_20; // @[TLB.scala:170:77] wire _mpu_ppn_T_19; // @[TLB.scala:170:77] wire _mpu_ppn_T_18; // @[TLB.scala:170:77] wire _mpu_ppn_T_17; // @[TLB.scala:170:77] wire _mpu_ppn_T_16; // @[TLB.scala:170:77] wire _mpu_ppn_T_15; // @[TLB.scala:170:77] wire _mpu_ppn_T_14; // @[TLB.scala:170:77] wire _mpu_ppn_T_13; // @[TLB.scala:170:77] wire _mpu_ppn_T_12; // @[TLB.scala:170:77] wire _mpu_ppn_T_11; // @[TLB.scala:170:77] wire _mpu_ppn_T_10; // @[TLB.scala:170:77] wire _mpu_ppn_T_9; // @[TLB.scala:170:77] wire _mpu_ppn_T_8; // @[TLB.scala:170:77] wire _mpu_ppn_T_7; // @[TLB.scala:170:77] wire _mpu_ppn_T_6; // @[TLB.scala:170:77] wire _mpu_ppn_T_5; // @[TLB.scala:170:77] wire _mpu_ppn_T_4; // @[TLB.scala:170:77] wire _mpu_ppn_T_3; // @[TLB.scala:170:77] wire _mpu_ppn_T_2; // @[TLB.scala:170:77] wire _mpu_ppn_T_1; // @[TLB.scala:170:77] assign _mpu_ppn_T_1 = _mpu_ppn_WIRE_1[0]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_fragmented_superpage = _mpu_ppn_T_1; // @[TLB.scala:170:77] assign _mpu_ppn_T_2 = _mpu_ppn_WIRE_1[1]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_c = _mpu_ppn_T_2; // @[TLB.scala:170:77] assign _mpu_ppn_T_3 = _mpu_ppn_WIRE_1[2]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_eff = _mpu_ppn_T_3; // @[TLB.scala:170:77] assign _mpu_ppn_T_4 = _mpu_ppn_WIRE_1[3]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_paa = _mpu_ppn_T_4; // @[TLB.scala:170:77] assign _mpu_ppn_T_5 = _mpu_ppn_WIRE_1[4]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_pal = _mpu_ppn_T_5; // @[TLB.scala:170:77] assign _mpu_ppn_T_6 = _mpu_ppn_WIRE_1[5]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_ppp = _mpu_ppn_T_6; // @[TLB.scala:170:77] assign _mpu_ppn_T_7 = _mpu_ppn_WIRE_1[6]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_pr = _mpu_ppn_T_7; // @[TLB.scala:170:77] assign _mpu_ppn_T_8 = _mpu_ppn_WIRE_1[7]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_px = _mpu_ppn_T_8; // @[TLB.scala:170:77] assign _mpu_ppn_T_9 = _mpu_ppn_WIRE_1[8]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_pw = _mpu_ppn_T_9; // @[TLB.scala:170:77] assign _mpu_ppn_T_10 = _mpu_ppn_WIRE_1[9]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_hr = _mpu_ppn_T_10; // @[TLB.scala:170:77] assign _mpu_ppn_T_11 = _mpu_ppn_WIRE_1[10]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_hx = _mpu_ppn_T_11; // @[TLB.scala:170:77] assign _mpu_ppn_T_12 = _mpu_ppn_WIRE_1[11]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_hw = _mpu_ppn_T_12; // @[TLB.scala:170:77] assign _mpu_ppn_T_13 = _mpu_ppn_WIRE_1[12]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_sr = _mpu_ppn_T_13; // @[TLB.scala:170:77] assign _mpu_ppn_T_14 = _mpu_ppn_WIRE_1[13]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_sx = _mpu_ppn_T_14; // @[TLB.scala:170:77] assign _mpu_ppn_T_15 = _mpu_ppn_WIRE_1[14]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_sw = _mpu_ppn_T_15; // @[TLB.scala:170:77] assign _mpu_ppn_T_16 = _mpu_ppn_WIRE_1[15]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_gf = _mpu_ppn_T_16; // @[TLB.scala:170:77] assign _mpu_ppn_T_17 = _mpu_ppn_WIRE_1[16]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_pf = _mpu_ppn_T_17; // @[TLB.scala:170:77] assign _mpu_ppn_T_18 = _mpu_ppn_WIRE_1[17]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_ae_stage2 = _mpu_ppn_T_18; // @[TLB.scala:170:77] assign _mpu_ppn_T_19 = _mpu_ppn_WIRE_1[18]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_ae_final = _mpu_ppn_T_19; // @[TLB.scala:170:77] assign _mpu_ppn_T_20 = _mpu_ppn_WIRE_1[19]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_ae_ptw = _mpu_ppn_T_20; // @[TLB.scala:170:77] assign _mpu_ppn_T_21 = _mpu_ppn_WIRE_1[20]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_g = _mpu_ppn_T_21; // @[TLB.scala:170:77] assign _mpu_ppn_T_22 = _mpu_ppn_WIRE_1[21]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_u = _mpu_ppn_T_22; // @[TLB.scala:170:77] assign _mpu_ppn_T_23 = _mpu_ppn_WIRE_1[41:22]; // @[TLB.scala:170:77] wire [19:0] _mpu_ppn_WIRE_ppn = _mpu_ppn_T_23; // @[TLB.scala:170:77] wire [1:0] mpu_ppn_res = _mpu_ppn_barrier_io_y_ppn[19:18]; // @[package.scala:267:25] wire _GEN = special_entry_level == 2'h0; // @[TLB.scala:197:28, :346:56] wire _mpu_ppn_ignore_T; // @[TLB.scala:197:28] assign _mpu_ppn_ignore_T = _GEN; // @[TLB.scala:197:28] wire _hitsVec_ignore_T_13; // @[TLB.scala:182:28] assign _hitsVec_ignore_T_13 = _GEN; // @[TLB.scala:182:28, :197:28] wire _ppn_ignore_T_8; // @[TLB.scala:197:28] assign _ppn_ignore_T_8 = _GEN; // @[TLB.scala:197:28] wire _ignore_T_13; // @[TLB.scala:182:28] assign _ignore_T_13 = _GEN; // @[TLB.scala:182:28, :197:28] wire mpu_ppn_ignore = _mpu_ppn_ignore_T; // @[TLB.scala:197:{28,34}] wire [26:0] _mpu_ppn_T_24 = mpu_ppn_ignore ? vpn : 27'h0; // @[TLB.scala:197:34, :198:28, :335:30] wire [26:0] _mpu_ppn_T_25 = {_mpu_ppn_T_24[26:20], _mpu_ppn_T_24[19:0] \| _mpu_ppn_barrier_io_y_ppn}; // @[package.scala:267:25] wire [8:0] _mpu_ppn_T_26 = _mpu_ppn_T_25[17:9]; // @[TLB.scala:198:{47,58}] wire [10:0] _mpu_ppn_T_27 = {mpu_ppn_res, _mpu_ppn_T_26}; // @[TLB.scala:195:26, :198:{18,58}] wire _mpu_ppn_ignore_T_1 = ~(special_entry_level[1]); // @[TLB.scala:197:28, :346:56] wire mpu_ppn_ignore_1 = _mpu_ppn_ignore_T_1; // @[TLB.scala:197:{28,34}] wire [26:0] _mpu_ppn_T_28 = mpu_ppn_ignore_1 ? vpn : 27'h0; // @[TLB.scala:197:34, :198:28, :335:30] wire [26:0] _mpu_ppn_T_29 = {_mpu_ppn_T_28[26:20], _mpu_ppn_T_28[19:0] \| _mpu_ppn_barrier_io_y_ppn}; // @[package.scala:267:25] wire [8:0] _mpu_ppn_T_30 = _mpu_ppn_T_29[8:0]; // @[TLB.scala:198:{47,58}] wire [19:0] _mpu_ppn_T_31 = {_mpu_ppn_T_27, _mpu_ppn_T_30}; // @[TLB.scala:198:{18,58}] wire [27:0] _mpu_ppn_T_32 = io_req_bits_vaddr_0[39:12]; // @[TLB.scala:318:7, :413:146] wire [27:0] _mpu_ppn_T_33 = _mpu_ppn_T ? {8'h0, _mpu_ppn_T_31} : _mpu_ppn_T_32; // @[TLB.scala:198:18, :413:{20,32,146}] wire [27:0] mpu_ppn = do_refill ? {8'h0, refill_ppn} : _mpu_ppn_T_33; // @[TLB.scala:406:44, :408:29, :412:20, :413:20] wire [11:0] _mpu_physaddr_T = io_req_bits_vaddr_0[11:0]; // @[TLB.scala:318:7, :414:52] wire [11:0] _io_resp_paddr_T = io_req_bits_vaddr_0[11:0]; // @[TLB.scala:318:7, :414:52, :652:46] wire [11:0] _io_resp_gpa_offset_T_1 = io_req_bits_vaddr_0[11:0]; // @[TLB.scala:318:7, :414:52, :658:82] wire [39:0] mpu_physaddr = {mpu_ppn, _mpu_physaddr_T}; // @[TLB.scala:412:20, :414:{25,52}] wire [39:0] _homogeneous_T = mpu_physaddr; // @[TLB.scala:414:25] wire [39:0] _homogeneous_T_67 = mpu_physaddr; // @[TLB.scala:414:25] wire [39:0] _deny_access_to_debug_T_1 = mpu_physaddr; // @[TLB.scala:414:25] wire _mpu_priv_T_1 = _mpu_priv_T; // @[TLB.scala:415:{38,52}] wire [2:0] _mpu_priv_T_2 = {io_ptw_status_debug_0, io_req_bits_prv_0}; // @[TLB.scala:318:7, :415:103] wire [2:0] mpu_priv = _mpu_priv_T_1 ? 3'h1 : _mpu_priv_T_2; // @[TLB.scala:415:{27,38,103}] wire cacheable; // @[TLB.scala:425:41] wire newEntry_c = cacheable; // @[TLB.scala:425:41, :449:24] wire [40:0] _homogeneous_T_1 = {1'h0, _homogeneous_T}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_2 = _homogeneous_T_1 & 41'h1FFFFFFE000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_3 = _homogeneous_T_2; // @[Parameters.scala:137:46] wire _homogeneous_T_4 = _homogeneous_T_3 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _homogeneous_T_50 = _homogeneous_T_4; // @[TLBPermissions.scala:101:65] wire [39:0] _GEN_0 = {mpu_physaddr[39:14], mpu_physaddr[13:0] ^ 14'h3000}; // @[TLB.scala:414:25] wire [39:0] _homogeneous_T_5; // @[Parameters.scala:137:31] assign _homogeneous_T_5 = _GEN_0; // @[Parameters.scala:137:31] wire [39:0] _homogeneous_T_72; // @[Parameters.scala:137:31] assign _homogeneous_T_72 = _GEN_0; // @[Parameters.scala:137:31] wire [40:0] _homogeneous_T_6 = {1'h0, _homogeneous_T_5}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_7 = _homogeneous_T_6 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_8 = _homogeneous_T_7; // @[Parameters.scala:137:46] wire _homogeneous_T_9 = _homogeneous_T_8 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] _GEN_1 = {mpu_physaddr[39:17], mpu_physaddr[16:0] ^ 17'h10000}; // @[TLB.scala:414:25] wire [39:0] _homogeneous_T_10; // @[Parameters.scala:137:31] assign _homogeneous_T_10 = _GEN_1; // @[Parameters.scala:137:31] wire [39:0] _homogeneous_T_60; // @[Parameters.scala:137:31] assign _homogeneous_T_60 = _GEN_1; // @[Parameters.scala:137:31] wire [39:0] _homogeneous_T_77; // @[Parameters.scala:137:31] assign _homogeneous_T_77 = _GEN_1; // @[Parameters.scala:137:31] wire [39:0] _homogeneous_T_109; // @[Parameters.scala:137:31] assign _homogeneous_T_109 = _GEN_1; // @[Parameters.scala:137:31] wire [39:0] _homogeneous_T_116; // @[Parameters.scala:137:31] assign _homogeneous_T_116 = _GEN_1; // @[Parameters.scala:137:31] wire [40:0] _homogeneous_T_11 = {1'h0, _homogeneous_T_10}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_12 = _homogeneous_T_11 & 41'h1FFFFFF0000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_13 = _homogeneous_T_12; // @[Parameters.scala:137:46] wire _homogeneous_T_14 = _homogeneous_T_13 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] _homogeneous_T_15 = {mpu_physaddr[39:21], mpu_physaddr[20:0] ^ 21'h100000}; // @[TLB.scala:414:25] wire [40:0] _homogeneous_T_16 = {1'h0, _homogeneous_T_15}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_17 = _homogeneous_T_16 & 41'h1FFFFFEF000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_18 = _homogeneous_T_17; // @[Parameters.scala:137:46] wire _homogeneous_T_19 = _homogeneous_T_18 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] _homogeneous_T_20 = {mpu_physaddr[39:26], mpu_physaddr[25:0] ^ 26'h2000000}; // @[TLB.scala:414:25] wire [40:0] _homogeneous_T_21 = {1'h0, _homogeneous_T_20}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_22 = _homogeneous_T_21 & 41'h1FFFFFF0000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_23 = _homogeneous_T_22; // @[Parameters.scala:137:46] wire _homogeneous_T_24 = _homogeneous_T_23 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] _homogeneous_T_25 = {mpu_physaddr[39:26], mpu_physaddr[25:0] ^ 26'h2010000}; // @[TLB.scala:414:25] wire [40:0] _homogeneous_T_26 = {1'h0, _homogeneous_T_25}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_27 = _homogeneous_T_26 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_28 = _homogeneous_T_27; // @[Parameters.scala:137:46] wire _homogeneous_T_29 = _homogeneous_T_28 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] _GEN_2 = {mpu_physaddr[39:28], mpu_physaddr[27:0] ^ 28'h8000000}; // @[TLB.scala:414:25] wire [39:0] _homogeneous_T_30; // @[Parameters.scala:137:31] assign _homogeneous_T_30 = _GEN_2; // @[Parameters.scala:137:31] wire [39:0] _homogeneous_T_82; // @[Parameters.scala:137:31] assign _homogeneous_T_82 = _GEN_2; // @[Parameters.scala:137:31] wire [39:0] _homogeneous_T_97; // @[Parameters.scala:137:31] assign _homogeneous_T_97 = _GEN_2; // @[Parameters.scala:137:31] wire [40:0] _homogeneous_T_31 = {1'h0, _homogeneous_T_30}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_32 = _homogeneous_T_31 & 41'h1FFFFFF0000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_33 = _homogeneous_T_32; // @[Parameters.scala:137:46] wire _homogeneous_T_34 = _homogeneous_T_33 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] _homogeneous_T_35 = {mpu_physaddr[39:28], mpu_physaddr[27:0] ^ 28'hC000000}; // @[TLB.scala:414:25] wire [40:0] _homogeneous_T_36 = {1'h0, _homogeneous_T_35}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_37 = _homogeneous_T_36 & 41'h1FFFC000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_38 = _homogeneous_T_37; // @[Parameters.scala:137:46] wire _homogeneous_T_39 = _homogeneous_T_38 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] _homogeneous_T_40 = {mpu_physaddr[39:29], mpu_physaddr[28:0] ^ 29'h10020000}; // @[TLB.scala:414:25] wire [40:0] _homogeneous_T_41 = {1'h0, _homogeneous_T_40}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_42 = _homogeneous_T_41 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_43 = _homogeneous_T_42; // @[Parameters.scala:137:46] wire _homogeneous_T_44 = _homogeneous_T_43 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] _GEN_3 = {mpu_physaddr[39:32], mpu_physaddr[31:0] ^ 32'h80000000}; // @[TLB.scala:414:25, :417:15] wire [39:0] _homogeneous_T_45; // @[Parameters.scala:137:31] assign _homogeneous_T_45 = _GEN_3; // @[Parameters.scala:137:31] wire [39:0] _homogeneous_T_87; // @[Parameters.scala:137:31] assign _homogeneous_T_87 = _GEN_3; // @[Parameters.scala:137:31] wire [39:0] _homogeneous_T_102; // @[Parameters.scala:137:31] assign _homogeneous_T_102 = _GEN_3; // @[Parameters.scala:137:31] wire [40:0] _homogeneous_T_46 = {1'h0, _homogeneous_T_45}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_47 = _homogeneous_T_46 & 41'h1FFF0000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_48 = _homogeneous_T_47; // @[Parameters.scala:137:46] wire _homogeneous_T_49 = _homogeneous_T_48 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _homogeneous_T_51 = _homogeneous_T_50 \| _homogeneous_T_9; // @[TLBPermissions.scala:101:65] wire _homogeneous_T_52 = _homogeneous_T_51 \| _homogeneous_T_14; // @[TLBPermissions.scala:101:65] wire _homogeneous_T_53 = _homogeneous_T_52 \| _homogeneous_T_19; // @[TLBPermissions.scala:101:65] wire _homogeneous_T_54 = _homogeneous_T_53 \| _homogeneous_T_24; // @[TLBPermissions.scala:101:65] wire _homogeneous_T_55 = _homogeneous_T_54 \| _homogeneous_T_29; // @[TLBPermissions.scala:101:65] wire _homogeneous_T_56 = _homogeneous_T_55 \| _homogeneous_T_34; // @[TLBPermissions.scala:101:65] wire _homogeneous_T_57 = _homogeneous_T_56 \| _homogeneous_T_39; // @[TLBPermissions.scala:101:65] wire _homogeneous_T_58 = _homogeneous_T_57 \| _homogeneous_T_44; // @[TLBPermissions.scala:101:65] wire homogeneous = _homogeneous_T_58 \| _homogeneous_T_49; // @[TLBPermissions.scala:101:65] wire [40:0] _homogeneous_T_61 = {1'h0, _homogeneous_T_60}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_62 = _homogeneous_T_61 & 41'h8A110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_63 = _homogeneous_T_62; // @[Parameters.scala:137:46] wire _homogeneous_T_64 = _homogeneous_T_63 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _homogeneous_T_65 = _homogeneous_T_64; // @[TLBPermissions.scala:87:66] wire _homogeneous_T_66 = ~_homogeneous_T_65; // @[TLBPermissions.scala:87:{22,66}] wire [40:0] _homogeneous_T_68 = {1'h0, _homogeneous_T_67}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_69 = _homogeneous_T_68 & 41'h9E113000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_70 = _homogeneous_T_69; // @[Parameters.scala:137:46] wire _homogeneous_T_71 = _homogeneous_T_70 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _homogeneous_T_92 = _homogeneous_T_71; // @[TLBPermissions.scala:85:66] wire [40:0] _homogeneous_T_73 = {1'h0, _homogeneous_T_72}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_74 = _homogeneous_T_73 & 41'h9E113000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_75 = _homogeneous_T_74; // @[Parameters.scala:137:46] wire _homogeneous_T_76 = _homogeneous_T_75 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _homogeneous_T_78 = {1'h0, _homogeneous_T_77}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_79 = _homogeneous_T_78 & 41'h9E110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_80 = _homogeneous_T_79; // @[Parameters.scala:137:46] wire _homogeneous_T_81 = _homogeneous_T_80 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _homogeneous_T_83 = {1'h0, _homogeneous_T_82}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_84 = _homogeneous_T_83 & 41'h9E110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_85 = _homogeneous_T_84; // @[Parameters.scala:137:46] wire _homogeneous_T_86 = _homogeneous_T_85 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _homogeneous_T_88 = {1'h0, _homogeneous_T_87}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_89 = _homogeneous_T_88 & 41'h90000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_90 = _homogeneous_T_89; // @[Parameters.scala:137:46] wire _homogeneous_T_91 = _homogeneous_T_90 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _homogeneous_T_93 = _homogeneous_T_92 \| _homogeneous_T_76; // @[TLBPermissions.scala:85:66] wire _homogeneous_T_94 = _homogeneous_T_93 \| _homogeneous_T_81; // @[TLBPermissions.scala:85:66] wire _homogeneous_T_95 = _homogeneous_T_94 \| _homogeneous_T_86; // @[TLBPermissions.scala:85:66] wire _homogeneous_T_96 = _homogeneous_T_95 \| _homogeneous_T_91; // @[TLBPermissions.scala:85:66] wire [40:0] _homogeneous_T_98 = {1'h0, _homogeneous_T_97}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_99 = _homogeneous_T_98 & 41'h8E000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_100 = _homogeneous_T_99; // @[Parameters.scala:137:46] wire _homogeneous_T_101 = _homogeneous_T_100 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _homogeneous_T_107 = _homogeneous_T_101; // @[TLBPermissions.scala:85:66] wire [40:0] _homogeneous_T_103 = {1'h0, _homogeneous_T_102}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_104 = _homogeneous_T_103 & 41'h80000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_105 = _homogeneous_T_104; // @[Parameters.scala:137:46] wire _homogeneous_T_106 = _homogeneous_T_105 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _homogeneous_T_108 = _homogeneous_T_107 \| _homogeneous_T_106; // @[TLBPermissions.scala:85:66] wire [40:0] _homogeneous_T_110 = {1'h0, _homogeneous_T_109}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_111 = _homogeneous_T_110 & 41'h8A110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_112 = _homogeneous_T_111; // @[Parameters.scala:137:46] wire _homogeneous_T_113 = _homogeneous_T_112 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _homogeneous_T_114 = _homogeneous_T_113; // @[TLBPermissions.scala:87:66] wire _homogeneous_T_115 = ~_homogeneous_T_114; // @[TLBPermissions.scala:87:{22,66}] wire [40:0] _homogeneous_T_117 = {1'h0, _homogeneous_T_116}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_118 = _homogeneous_T_117 & 41'h8A110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_119 = _homogeneous_T_118; // @[Parameters.scala:137:46] wire _homogeneous_T_120 = _homogeneous_T_119 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _homogeneous_T_121 = _homogeneous_T_120; // @[TLBPermissions.scala:87:66] wire _homogeneous_T_122 = ~_homogeneous_T_121; // @[TLBPermissions.scala:87:{22,66}] wire _deny_access_to_debug_T = ~(mpu_priv[2]); // @[TLB.scala:415:27, :428:39] wire [40:0] _deny_access_to_debug_T_2 = {1'h0, _deny_access_to_debug_T_1}; // @[Parameters.scala:137:{31,41}] wire [40:0] _deny_access_to_debug_T_3 = _deny_access_to_debug_T_2 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}] wire [40:0] _deny_access_to_debug_T_4 = _deny_access_to_debug_T_3; // @[Parameters.scala:137:46] wire _deny_access_to_debug_T_5 = _deny_access_to_debug_T_4 == 41'h0; // @[Parameters.scala:137:{46,59}] wire deny_access_to_debug = _deny_access_to_debug_T & _deny_access_to_debug_T_5; // @[TLB.scala:428:{39,50}] wire _prot_r_T = ~deny_access_to_debug; // @[TLB.scala:428:50, :429:33] wire _prot_r_T_1 = _pma_io_resp_r & _prot_r_T; // @[TLB.scala:422:19, :429:{30,33}] wire prot_r = _prot_r_T_1 & _pmp_io_r; // @[TLB.scala:416:19, :429:{30,55}] wire newEntry_pr = prot_r; // @[TLB.scala:429:55, :449:24] wire _prot_w_T = ~deny_access_to_debug; // @[TLB.scala:428:50, :429:33, :430:33] wire _prot_w_T_1 = _pma_io_resp_w & _prot_w_T; // @[TLB.scala:422:19, :430:{30,33}] wire prot_w = _prot_w_T_1 & _pmp_io_w; // @[TLB.scala:416:19, :430:{30,55}] wire newEntry_pw = prot_w; // @[TLB.scala:430:55, :449:24] wire _prot_x_T = ~deny_access_to_debug; // @[TLB.scala:428:50, :429:33, :434:33] wire _prot_x_T_1 = _pma_io_resp_x & _prot_x_T; // @[TLB.scala:422:19, :434:{30,33}] wire prot_x = _prot_x_T_1 & _pmp_io_x; // @[TLB.scala:416:19, :434:{30,55}] wire newEntry_px = prot_x; // @[TLB.scala:434:55, :449:24] wire _GEN_4 = sectored_entries_0_0_valid_0 \| sectored_entries_0_0_valid_1; // @[package.scala:81:59] wire _sector_hits_T; // @[package.scala:81:59] assign _sector_hits_T = _GEN_4; // @[package.scala:81:59] wire _r_sectored_repl_addr_valids_T; // @[package.scala:81:59] assign _r_sectored_repl_addr_valids_T = _GEN_4; // @[package.scala:81:59] wire _sector_hits_T_1 = _sector_hits_T \| sectored_entries_0_0_valid_2; // @[package.scala:81:59] wire _sector_hits_T_2 = _sector_hits_T_1 \| sectored_entries_0_0_valid_3; // @[package.scala:81:59] wire [26:0] _T_176 = sectored_entries_0_0_tag_vpn ^ vpn; // @[TLB.scala:174:61, :335:30, :339:29] wire [26:0] _sector_hits_T_3; // @[TLB.scala:174:61] assign _sector_hits_T_3 = _T_176; // @[TLB.scala:174:61] wire [26:0] _hitsVec_T; // @[TLB.scala:174:61] assign _hitsVec_T = _T_176; // @[TLB.scala:174:61] wire [24:0] _sector_hits_T_4 = _sector_hits_T_3[26:2]; // @[TLB.scala:174:{61,68}] wire _sector_hits_T_5 = _sector_hits_T_4 == 25'h0; // @[TLB.scala:174:{68,86}] wire _sector_hits_T_6 = ~sectored_entries_0_0_tag_v; // @[TLB.scala:174:105, :339:29] wire _sector_hits_T_7 = _sector_hits_T_5 & _sector_hits_T_6; // @[TLB.scala:174:{86,95,105}] wire sector_hits_0 = _sector_hits_T_2 & _sector_hits_T_7; // @[package.scala:81:59] wire _GEN_5 = sectored_entries_0_1_valid_0 \| sectored_entries_0_1_valid_1; // @[package.scala:81:59] wire _sector_hits_T_8; // @[package.scala:81:59] assign _sector_hits_T_8 = _GEN_5; // @[package.scala:81:59] wire _r_sectored_repl_addr_valids_T_3; // @[package.scala:81:59] assign _r_sectored_repl_addr_valids_T_3 = _GEN_5; // @[package.scala:81:59] wire _sector_hits_T_9 = _sector_hits_T_8 \| sectored_entries_0_1_valid_2; // @[package.scala:81:59] wire _sector_hits_T_10 = _sector_hits_T_9 \| sectored_entries_0_1_valid_3; // @[package.scala:81:59] wire [26:0] _T_597 = sectored_entries_0_1_tag_vpn ^ vpn; // @[TLB.scala:174:61, :335:30, :339:29] wire [26:0] _sector_hits_T_11; // @[TLB.scala:174:61] assign _sector_hits_T_11 = _T_597; // @[TLB.scala:174:61] wire [26:0] _hitsVec_T_6; // @[TLB.scala:174:61] assign _hitsVec_T_6 = _T_597; // @[TLB.scala:174:61] wire [24:0] _sector_hits_T_12 = _sector_hits_T_11[26:2]; // @[TLB.scala:174:{61,68}] wire _sector_hits_T_13 = _sector_hits_T_12 == 25'h0; // @[TLB.scala:174:{68,86}] wire _sector_hits_T_14 = ~sectored_entries_0_1_tag_v; // @[TLB.scala:174:105, :339:29] wire _sector_hits_T_15 = _sector_hits_T_13 & _sector_hits_T_14; // @[TLB.scala:174:{86,95,105}] wire sector_hits_1 = _sector_hits_T_10 & _sector_hits_T_15; // @[package.scala:81:59] wire _GEN_6 = sectored_entries_0_2_valid_0 \| sectored_entries_0_2_valid_1; // @[package.scala:81:59] wire _sector_hits_T_16; // @[package.scala:81:59] assign _sector_hits_T_16 = _GEN_6; // @[package.scala:81:59] wire _r_sectored_repl_addr_valids_T_6; // @[package.scala:81:59] assign _r_sectored_repl_addr_valids_T_6 = _GEN_6; // @[package.scala:81:59] wire _sector_hits_T_17 = _sector_hits_T_16 \| sectored_entries_0_2_valid_2; // @[package.scala:81:59] wire _sector_hits_T_18 = _sector_hits_T_17 \| sectored_entries_0_2_valid_3; // @[package.scala:81:59] wire [26:0] _T_1018 = sectored_entries_0_2_tag_vpn ^ vpn; // @[TLB.scala:174:61, :335:30, :339:29] wire [26:0] _sector_hits_T_19; // @[TLB.scala:174:61] assign _sector_hits_T_19 = _T_1018; // @[TLB.scala:174:61] wire [26:0] _hitsVec_T_12; // @[TLB.scala:174:61] assign _hitsVec_T_12 = _T_1018; // @[TLB.scala:174:61] wire [24:0] _sector_hits_T_20 = _sector_hits_T_19[26:2]; // @[TLB.scala:174:{61,68}] wire _sector_hits_T_21 = _sector_hits_T_20 == 25'h0; // @[TLB.scala:174:{68,86}] wire _sector_hits_T_22 = ~sectored_entries_0_2_tag_v; // @[TLB.scala:174:105, :339:29] wire _sector_hits_T_23 = _sector_hits_T_21 & _sector_hits_T_22; // @[TLB.scala:174:{86,95,105}] wire sector_hits_2 = _sector_hits_T_18 & _sector_hits_T_23; // @[package.scala:81:59] wire _GEN_7 = sectored_entries_0_3_valid_0 \| sectored_entries_0_3_valid_1; // @[package.scala:81:59] wire _sector_hits_T_24; // @[package.scala:81:59] assign _sector_hits_T_24 = _GEN_7; // @[package.scala:81:59] wire _r_sectored_repl_addr_valids_T_9; // @[package.scala:81:59] assign _r_sectored_repl_addr_valids_T_9 = _GEN_7; // @[package.scala:81:59] wire _sector_hits_T_25 = _sector_hits_T_24 \| sectored_entries_0_3_valid_2; // @[package.scala:81:59] wire _sector_hits_T_26 = _sector_hits_T_25 \| sectored_entries_0_3_valid_3; // @[package.scala:81:59] wire [26:0] _T_1439 = sectored_entries_0_3_tag_vpn ^ vpn; // @[TLB.scala:174:61, :335:30, :339:29] wire [26:0] _sector_hits_T_27; // @[TLB.scala:174:61] assign _sector_hits_T_27 = _T_1439; // @[TLB.scala:174:61] wire [26:0] _hitsVec_T_18; // @[TLB.scala:174:61] assign _hitsVec_T_18 = _T_1439; // @[TLB.scala:174:61] wire [24:0] _sector_hits_T_28 = _sector_hits_T_27[26:2]; // @[TLB.scala:174:{61,68}] wire _sector_hits_T_29 = _sector_hits_T_28 == 25'h0; // @[TLB.scala:174:{68,86}] wire _sector_hits_T_30 = ~sectored_entries_0_3_tag_v; // @[TLB.scala:174:105, :339:29] wire _sector_hits_T_31 = _sector_hits_T_29 & _sector_hits_T_30; // @[TLB.scala:174:{86,95,105}] wire sector_hits_3 = _sector_hits_T_26 & _sector_hits_T_31; // @[package.scala:81:59] wire _GEN_8 = sectored_entries_0_4_valid_0 \| sectored_entries_0_4_valid_1; // @[package.scala:81:59] wire _sector_hits_T_32; // @[package.scala:81:59] assign _sector_hits_T_32 = _GEN_8; // @[package.scala:81:59] wire _r_sectored_repl_addr_valids_T_12; // @[package.scala:81:59] assign _r_sectored_repl_addr_valids_T_12 = _GEN_8; // @[package.scala:81:59] wire _sector_hits_T_33 = _sector_hits_T_32 \| sectored_entries_0_4_valid_2; // @[package.scala:81:59] wire _sector_hits_T_34 = _sector_hits_T_33 \| sectored_entries_0_4_valid_3; // @[package.scala:81:59] wire [26:0] _T_1860 = sectored_entries_0_4_tag_vpn ^ vpn; // @[TLB.scala:174:61, :335:30, :339:29] wire [26:0] _sector_hits_T_35; // @[TLB.scala:174:61] assign _sector_hits_T_35 = _T_1860; // @[TLB.scala:174:61] wire [26:0] _hitsVec_T_24; // @[TLB.scala:174:61] assign _hitsVec_T_24 = _T_1860; // @[TLB.scala:174:61] wire [24:0] _sector_hits_T_36 = _sector_hits_T_35[26:2]; // @[TLB.scala:174:{61,68}] wire _sector_hits_T_37 = _sector_hits_T_36 == 25'h0; // @[TLB.scala:174:{68,86}] wire _sector_hits_T_38 = ~sectored_entries_0_4_tag_v; // @[TLB.scala:174:105, :339:29] wire _sector_hits_T_39 = _sector_hits_T_37 & _sector_hits_T_38; // @[TLB.scala:174:{86,95,105}] wire sector_hits_4 = _sector_hits_T_34 & _sector_hits_T_39; // @[package.scala:81:59] wire _GEN_9 = sectored_entries_0_5_valid_0 \| sectored_entries_0_5_valid_1; // @[package.scala:81:59] wire _sector_hits_T_40; // @[package.scala:81:59] assign _sector_hits_T_40 = _GEN_9; // @[package.scala:81:59] wire _r_sectored_repl_addr_valids_T_15; // @[package.scala:81:59] assign _r_sectored_repl_addr_valids_T_15 = _GEN_9; // @[package.scala:81:59] wire _sector_hits_T_41 = _sector_hits_T_40 \| sectored_entries_0_5_valid_2; // @[package.scala:81:59] wire _sector_hits_T_42 = _sector_hits_T_41 \| sectored_entries_0_5_valid_3; // @[package.scala:81:59] wire [26:0] _T_2281 = sectored_entries_0_5_tag_vpn ^ vpn; // @[TLB.scala:174:61, :335:30, :339:29] wire [26:0] _sector_hits_T_43; // @[TLB.scala:174:61] assign _sector_hits_T_43 = _T_2281; // @[TLB.scala:174:61] wire [26:0] _hitsVec_T_30; // @[TLB.scala:174:61] assign _hitsVec_T_30 = _T_2281; // @[TLB.scala:174:61] wire [24:0] _sector_hits_T_44 = _sector_hits_T_43[26:2]; // @[TLB.scala:174:{61,68}] wire _sector_hits_T_45 = _sector_hits_T_44 == 25'h0; // @[TLB.scala:174:{68,86}] wire _sector_hits_T_46 = ~sectored_entries_0_5_tag_v; // @[TLB.scala:174:105, :339:29] wire _sector_hits_T_47 = _sector_hits_T_45 & _sector_hits_T_46; // @[TLB.scala:174:{86,95,105}] wire sector_hits_5 = _sector_hits_T_42 & _sector_hits_T_47; // @[package.scala:81:59] wire _GEN_10 = sectored_entries_0_6_valid_0 \| sectored_entries_0_6_valid_1; // @[package.scala:81:59] wire _sector_hits_T_48; // @[package.scala:81:59] assign _sector_hits_T_48 = _GEN_10; // @[package.scala:81:59] wire _r_sectored_repl_addr_valids_T_18; // @[package.scala:81:59] assign _r_sectored_repl_addr_valids_T_18 = _GEN_10; // @[package.scala:81:59] wire _sector_hits_T_49 = _sector_hits_T_48 \| sectored_entries_0_6_valid_2; // @[package.scala:81:59] wire _sector_hits_T_50 = _sector_hits_T_49 \| sectored_entries_0_6_valid_3; // @[package.scala:81:59] wire [26:0] _T_2702 = sectored_entries_0_6_tag_vpn ^ vpn; // @[TLB.scala:174:61, :335:30, :339:29] wire [26:0] _sector_hits_T_51; // @[TLB.scala:174:61] assign _sector_hits_T_51 = _T_2702; // @[TLB.scala:174:61] wire [26:0] _hitsVec_T_36; // @[TLB.scala:174:61] assign _hitsVec_T_36 = _T_2702; // @[TLB.scala:174:61] wire [24:0] _sector_hits_T_52 = _sector_hits_T_51[26:2]; // @[TLB.scala:174:{61,68}] wire _sector_hits_T_53 = _sector_hits_T_52 == 25'h0; // @[TLB.scala:174:{68,86}] wire _sector_hits_T_54 = ~sectored_entries_0_6_tag_v; // @[TLB.scala:174:105, :339:29] wire _sector_hits_T_55 = _sector_hits_T_53 & _sector_hits_T_54; // @[TLB.scala:174:{86,95,105}] wire sector_hits_6 = _sector_hits_T_50 & _sector_hits_T_55; // @[package.scala:81:59] wire _GEN_11 = sectored_entries_0_7_valid_0 \| sectored_entries_0_7_valid_1; // @[package.scala:81:59] wire _sector_hits_T_56; // @[package.scala:81:59] assign _sector_hits_T_56 = _GEN_11; // @[package.scala:81:59] wire _r_sectored_repl_addr_valids_T_21; // @[package.scala:81:59] assign _r_sectored_repl_addr_valids_T_21 = _GEN_11; // @[package.scala:81:59] wire _sector_hits_T_57 = _sector_hits_T_56 \| sectored_entries_0_7_valid_2; // @[package.scala:81:59] wire _sector_hits_T_58 = _sector_hits_T_57 \| sectored_entries_0_7_valid_3; // @[package.scala:81:59] wire [26:0] _T_3123 = sectored_entries_0_7_tag_vpn ^ vpn; // @[TLB.scala:174:61, :335:30, :339:29] wire [26:0] _sector_hits_T_59; // @[TLB.scala:174:61] assign _sector_hits_T_59 = _T_3123; // @[TLB.scala:174:61] wire [26:0] _hitsVec_T_42; // @[TLB.scala:174:61] assign _hitsVec_T_42 = _T_3123; // @[TLB.scala:174:61] wire [24:0] _sector_hits_T_60 = _sector_hits_T_59[26:2]; // @[TLB.scala:174:{61,68}] wire _sector_hits_T_61 = _sector_hits_T_60 == 25'h0; // @[TLB.scala:174:{68,86}] wire _sector_hits_T_62 = ~sectored_entries_0_7_tag_v; // @[TLB.scala:174:105, :339:29] wire _sector_hits_T_63 = _sector_hits_T_61 & _sector_hits_T_62; // @[TLB.scala:174:{86,95,105}] wire sector_hits_7 = _sector_hits_T_58 & _sector_hits_T_63; // @[package.scala:81:59] wire _superpage_hits_tagMatch_T = ~superpage_entries_0_tag_v; // @[TLB.scala:178:43, :341:30] wire superpage_hits_tagMatch = superpage_entries_0_valid_0 & _superpage_hits_tagMatch_T; // @[TLB.scala:178:{33,43}, :341:30] wire [26:0] _T_3446 = superpage_entries_0_tag_vpn ^ vpn; // @[TLB.scala:183:52, :335:30, :341:30] wire [26:0] _superpage_hits_T; // @[TLB.scala:183:52] assign _superpage_hits_T = _T_3446; // @[TLB.scala:183:52] wire [26:0] _superpage_hits_T_5; // @[TLB.scala:183:52] assign _superpage_hits_T_5 = _T_3446; // @[TLB.scala:183:52] wire [26:0] _superpage_hits_T_10; // @[TLB.scala:183:52] assign _superpage_hits_T_10 = _T_3446; // @[TLB.scala:183:52] wire [26:0] _hitsVec_T_48; // @[TLB.scala:183:52] assign _hitsVec_T_48 = _T_3446; // @[TLB.scala:183:52] wire [26:0] _hitsVec_T_53; // @[TLB.scala:183:52] assign _hitsVec_T_53 = _T_3446; // @[TLB.scala:183:52] wire [26:0] _hitsVec_T_58; // @[TLB.scala:183:52] assign _hitsVec_T_58 = _T_3446; // @[TLB.scala:183:52] wire [8:0] _superpage_hits_T_1 = _superpage_hits_T[26:18]; // @[TLB.scala:183:{52,58}] wire _superpage_hits_T_2 = _superpage_hits_T_1 == 9'h0; // @[TLB.scala:183:{58,79}] wire _superpage_hits_T_3 = _superpage_hits_T_2; // @[TLB.scala:183:{40,79}] wire _superpage_hits_T_4 = superpage_hits_tagMatch & _superpage_hits_T_3; // @[TLB.scala:178:33, :183:{29,40}] wire _GEN_12 = superpage_entries_0_level == 2'h0; // @[TLB.scala:182:28, :341:30] wire _superpage_hits_ignore_T_1; // @[TLB.scala:182:28] assign _superpage_hits_ignore_T_1 = _GEN_12; // @[TLB.scala:182:28] wire _hitsVec_ignore_T_1; // @[TLB.scala:182:28] assign _hitsVec_ignore_T_1 = _GEN_12; // @[TLB.scala:182:28] wire _ppn_ignore_T; // @[TLB.scala:197:28] assign _ppn_ignore_T = _GEN_12; // @[TLB.scala:182:28, :197:28] wire _ignore_T_1; // @[TLB.scala:182:28] assign _ignore_T_1 = _GEN_12; // @[TLB.scala:182:28] wire superpage_hits_ignore_1 = _superpage_hits_ignore_T_1; // @[TLB.scala:182:{28,34}] wire [8:0] _superpage_hits_T_6 = _superpage_hits_T_5[17:9]; // @[TLB.scala:183:{52,58}] wire _superpage_hits_T_7 = _superpage_hits_T_6 == 9'h0; // @[TLB.scala:183:{58,79}] wire _superpage_hits_T_8 = superpage_hits_ignore_1 \| _superpage_hits_T_7; // @[TLB.scala:182:34, :183:{40,79}] wire _superpage_hits_T_9 = _superpage_hits_T_4 & _superpage_hits_T_8; // @[TLB.scala:183:{29,40}] wire superpage_hits_0 = _superpage_hits_T_9; // @[TLB.scala:183:29] wire _superpage_hits_ignore_T_2 = ~(superpage_entries_0_level[1]); // @[TLB.scala:182:28, :341:30] wire [8:0] _superpage_hits_T_11 = _superpage_hits_T_10[8:0]; // @[TLB.scala:183:{52,58}] wire _superpage_hits_T_12 = _superpage_hits_T_11 == 9'h0; // @[TLB.scala:183:{58,79}] wire _superpage_hits_tagMatch_T_1 = ~superpage_entries_1_tag_v; // @[TLB.scala:178:43, :341:30] wire superpage_hits_tagMatch_1 = superpage_entries_1_valid_0 & _superpage_hits_tagMatch_T_1; // @[TLB.scala:178:{33,43}, :341:30] wire [26:0] _T_3544 = superpage_entries_1_tag_vpn ^ vpn; // @[TLB.scala:183:52, :335:30, :341:30] wire [26:0] _superpage_hits_T_14; // @[TLB.scala:183:52] assign _superpage_hits_T_14 = _T_3544; // @[TLB.scala:183:52] wire [26:0] _superpage_hits_T_19; // @[TLB.scala:183:52] assign _superpage_hits_T_19 = _T_3544; // @[TLB.scala:183:52] wire [26:0] _superpage_hits_T_24; // @[TLB.scala:183:52] assign _superpage_hits_T_24 = _T_3544; // @[TLB.scala:183:52] wire [26:0] _hitsVec_T_63; // @[TLB.scala:183:52] assign _hitsVec_T_63 = _T_3544; // @[TLB.scala:183:52] wire [26:0] _hitsVec_T_68; // @[TLB.scala:183:52] assign _hitsVec_T_68 = _T_3544; // @[TLB.scala:183:52] wire [26:0] _hitsVec_T_73; // @[TLB.scala:183:52] assign _hitsVec_T_73 = _T_3544; // @[TLB.scala:183:52] wire [8:0] _superpage_hits_T_15 = _superpage_hits_T_14[26:18]; // @[TLB.scala:183:{52,58}] wire _superpage_hits_T_16 = _superpage_hits_T_15 == 9'h0; // @[TLB.scala:183:{58,79}] wire _superpage_hits_T_17 = _superpage_hits_T_16; // @[TLB.scala:183:{40,79}] wire _superpage_hits_T_18 = superpage_hits_tagMatch_1 & _superpage_hits_T_17; // @[TLB.scala:178:33, :183:{29,40}] wire _GEN_13 = superpage_entries_1_level == 2'h0; // @[TLB.scala:182:28, :341:30] wire _superpage_hits_ignore_T_4; // @[TLB.scala:182:28] assign _superpage_hits_ignore_T_4 = _GEN_13; // @[TLB.scala:182:28] wire _hitsVec_ignore_T_4; // @[TLB.scala:182:28] assign _hitsVec_ignore_T_4 = _GEN_13; // @[TLB.scala:182:28] wire _ppn_ignore_T_2; // @[TLB.scala:197:28] assign _ppn_ignore_T_2 = _GEN_13; // @[TLB.scala:182:28, :197:28] wire _ignore_T_4; // @[TLB.scala:182:28] assign _ignore_T_4 = _GEN_13; // @[TLB.scala:182:28] wire superpage_hits_ignore_4 = _superpage_hits_ignore_T_4; // @[TLB.scala:182:{28,34}] wire [8:0] _superpage_hits_T_20 = _superpage_hits_T_19[17:9]; // @[TLB.scala:183:{52,58}] wire _superpage_hits_T_21 = _superpage_hits_T_20 == 9'h0; // @[TLB.scala:183:{58,79}] wire _superpage_hits_T_22 = superpage_hits_ignore_4 \| _superpage_hits_T_21; // @[TLB.scala:182:34, :183:{40,79}] wire _superpage_hits_T_23 = _superpage_hits_T_18 & _superpage_hits_T_22; // @[TLB.scala:183:{29,40}] wire superpage_hits_1 = _superpage_hits_T_23; // @[TLB.scala:183:29] wire _superpage_hits_ignore_T_5 = ~(superpage_entries_1_level[1]); // @[TLB.scala:182:28, :341:30] wire [8:0] _superpage_hits_T_25 = _superpage_hits_T_24[8:0]; // @[TLB.scala:183:{52,58}] wire _superpage_hits_T_26 = _superpage_hits_T_25 == 9'h0; // @[TLB.scala:183:{58,79}] wire _superpage_hits_tagMatch_T_2 = ~superpage_entries_2_tag_v; // @[TLB.scala:178:43, :341:30] wire superpage_hits_tagMatch_2 = superpage_entries_2_valid_0 & _superpage_hits_tagMatch_T_2; // @[TLB.scala:178:{33,43}, :341:30] wire [26:0] _T_3642 = superpage_entries_2_tag_vpn ^ vpn; // @[TLB.scala:183:52, :335:30, :341:30] wire [26:0] _superpage_hits_T_28; // @[TLB.scala:183:52] assign _superpage_hits_T_28 = _T_3642; // @[TLB.scala:183:52] wire [26:0] _superpage_hits_T_33; // @[TLB.scala:183:52] assign _superpage_hits_T_33 = _T_3642; // @[TLB.scala:183:52] wire [26:0] _superpage_hits_T_38; // @[TLB.scala:183:52] assign _superpage_hits_T_38 = _T_3642; // @[TLB.scala:183:52] wire [26:0] _hitsVec_T_78; // @[TLB.scala:183:52] assign _hitsVec_T_78 = _T_3642; // @[TLB.scala:183:52] wire [26:0] _hitsVec_T_83; // @[TLB.scala:183:52] assign _hitsVec_T_83 = _T_3642; // @[TLB.scala:183:52] wire [26:0] _hitsVec_T_88; // @[TLB.scala:183:52] assign _hitsVec_T_88 = _T_3642; // @[TLB.scala:183:52] wire [8:0] _superpage_hits_T_29 = _superpage_hits_T_28[26:18]; // @[TLB.scala:183:{52,58}] wire _superpage_hits_T_30 = _superpage_hits_T_29 == 9'h0; // @[TLB.scala:183:{58,79}] wire _superpage_hits_T_31 = _superpage_hits_T_30; // @[TLB.scala:183:{40,79}] wire _superpage_hits_T_32 = superpage_hits_tagMatch_2 & _superpage_hits_T_31; // @[TLB.scala:178:33, :183:{29,40}] wire _GEN_14 = superpage_entries_2_level == 2'h0; // @[TLB.scala:182:28, :341:30] wire _superpage_hits_ignore_T_7; // @[TLB.scala:182:28] assign _superpage_hits_ignore_T_7 = _GEN_14; // @[TLB.scala:182:28] wire _hitsVec_ignore_T_7; // @[TLB.scala:182:28] assign _hitsVec_ignore_T_7 = _GEN_14; // @[TLB.scala:182:28] wire _ppn_ignore_T_4; // @[TLB.scala:197:28] assign _ppn_ignore_T_4 = _GEN_14; // @[TLB.scala:182:28, :197:28] wire _ignore_T_7; // @[TLB.scala:182:28] assign _ignore_T_7 = _GEN_14; // @[TLB.scala:182:28] wire superpage_hits_ignore_7 = _superpage_hits_ignore_T_7; // @[TLB.scala:182:{28,34}] wire [8:0] _superpage_hits_T_34 = _superpage_hits_T_33[17:9]; // @[TLB.scala:183:{52,58}] wire _superpage_hits_T_35 = _superpage_hits_T_34 == 9'h0; // @[TLB.scala:183:{58,79}] wire _superpage_hits_T_36 = superpage_hits_ignore_7 \| _superpage_hits_T_35; // @[TLB.scala:182:34, :183:{40,79}] wire _superpage_hits_T_37 = _superpage_hits_T_32 & _superpage_hits_T_36; // @[TLB.scala:183:{29,40}] wire superpage_hits_2 = _superpage_hits_T_37; // @[TLB.scala:183:29] wire _superpage_hits_ignore_T_8 = ~(superpage_entries_2_level[1]); // @[TLB.scala:182:28, :341:30] wire [8:0] _superpage_hits_T_39 = _superpage_hits_T_38[8:0]; // @[TLB.scala:183:{52,58}] wire _superpage_hits_T_40 = _superpage_hits_T_39 == 9'h0; // @[TLB.scala:183:{58,79}] wire _superpage_hits_tagMatch_T_3 = ~superpage_entries_3_tag_v; // @[TLB.scala:178:43, :341:30] wire superpage_hits_tagMatch_3 = superpage_entries_3_valid_0 & _superpage_hits_tagMatch_T_3; // @[TLB.scala:178:{33,43}, :341:30] wire [26:0] _T_3740 = superpage_entries_3_tag_vpn ^ vpn; // @[TLB.scala:183:52, :335:30, :341:30] wire [26:0] _superpage_hits_T_42; // @[TLB.scala:183:52] assign _superpage_hits_T_42 = _T_3740; // @[TLB.scala:183:52] wire [26:0] _superpage_hits_T_47; // @[TLB.scala:183:52] assign _superpage_hits_T_47 = _T_3740; // @[TLB.scala:183:52] wire [26:0] _superpage_hits_T_52; // @[TLB.scala:183:52] assign _superpage_hits_T_52 = _T_3740; // @[TLB.scala:183:52] wire [26:0] _hitsVec_T_93; // @[TLB.scala:183:52] assign _hitsVec_T_93 = _T_3740; // @[TLB.scala:183:52] wire [26:0] _hitsVec_T_98; // @[TLB.scala:183:52] assign _hitsVec_T_98 = _T_3740; // @[TLB.scala:183:52] wire [26:0] _hitsVec_T_103; // @[TLB.scala:183:52] assign _hitsVec_T_103 = _T_3740; // @[TLB.scala:183:52] wire [8:0] _superpage_hits_T_43 = _superpage_hits_T_42[26:18]; // @[TLB.scala:183:{52,58}] wire _superpage_hits_T_44 = _superpage_hits_T_43 == 9'h0; // @[TLB.scala:183:{58,79}] wire _superpage_hits_T_45 = _superpage_hits_T_44; // @[TLB.scala:183:{40,79}] wire _superpage_hits_T_46 = superpage_hits_tagMatch_3 & _superpage_hits_T_45; // @[TLB.scala:178:33, :183:{29,40}] wire _GEN_15 = superpage_entries_3_level == 2'h0; // @[TLB.scala:182:28, :341:30] wire _superpage_hits_ignore_T_10; // @[TLB.scala:182:28] assign _superpage_hits_ignore_T_10 = _GEN_15; // @[TLB.scala:182:28] wire _hitsVec_ignore_T_10; // @[TLB.scala:182:28] assign _hitsVec_ignore_T_10 = _GEN_15; // @[TLB.scala:182:28] wire _ppn_ignore_T_6; // @[TLB.scala:197:28] assign _ppn_ignore_T_6 = _GEN_15; // @[TLB.scala:182:28, :197:28] wire _ignore_T_10; // @[TLB.scala:182:28] assign _ignore_T_10 = _GEN_15; // @[TLB.scala:182:28] wire superpage_hits_ignore_10 = _superpage_hits_ignore_T_10; // @[TLB.scala:182:{28,34}] wire [8:0] _superpage_hits_T_48 = _superpage_hits_T_47[17:9]; // @[TLB.scala:183:{52,58}] wire _superpage_hits_T_49 = _superpage_hits_T_48 == 9'h0; // @[TLB.scala:183:{58,79}] wire _superpage_hits_T_50 = superpage_hits_ignore_10 \| _superpage_hits_T_49; // @[TLB.scala:182:34, :183:{40,79}] wire _superpage_hits_T_51 = _superpage_hits_T_46 & _superpage_hits_T_50; // @[TLB.scala:183:{29,40}] wire superpage_hits_3 = _superpage_hits_T_51; // @[TLB.scala:183:29] wire _superpage_hits_ignore_T_11 = ~(superpage_entries_3_level[1]); // @[TLB.scala:182:28, :341:30] wire [8:0] _superpage_hits_T_53 = _superpage_hits_T_52[8:0]; // @[TLB.scala:183:{52,58}] wire _superpage_hits_T_54 = _superpage_hits_T_53 == 9'h0; // @[TLB.scala:183:{58,79}] wire [1:0] hitsVec_idx = vpn[1:0]; // @[package.scala:163:13] wire [1:0] hitsVec_idx_1 = vpn[1:0]; // @[package.scala:163:13] wire [1:0] hitsVec_idx_2 = vpn[1:0]; // @[package.scala:163:13] wire [1:0] hitsVec_idx_3 = vpn[1:0]; // @[package.scala:163:13] wire [1:0] hitsVec_idx_4 = vpn[1:0]; // @[package.scala:163:13] wire [1:0] hitsVec_idx_5 = vpn[1:0]; // @[package.scala:163:13] wire [1:0] hitsVec_idx_6 = vpn[1:0]; // @[package.scala:163:13] wire [1:0] hitsVec_idx_7 = vpn[1:0]; // @[package.scala:163:13] wire [1:0] _entries_T = vpn[1:0]; // @[package.scala:163:13] wire [1:0] _entries_T_24 = vpn[1:0]; // @[package.scala:163:13] wire [1:0] _entries_T_48 = vpn[1:0]; // @[package.scala:163:13] wire [1:0] _entries_T_72 = vpn[1:0]; // @[package.scala:163:13] wire [1:0] _entries_T_96 = vpn[1:0]; // @[package.scala:163:13] wire [1:0] _entries_T_120 = vpn[1:0]; // @[package.scala:163:13] wire [1:0] _entries_T_144 = vpn[1:0]; // @[package.scala:163:13] wire [1:0] _entries_T_168 = vpn[1:0]; // @[package.scala:163:13] wire [24:0] _hitsVec_T_1 = _hitsVec_T[26:2]; // @[TLB.scala:174:{61,68}] wire _hitsVec_T_2 = _hitsVec_T_1 == 25'h0; // @[TLB.scala:174:{68,86}] wire _hitsVec_T_3 = ~sectored_entries_0_0_tag_v; // @[TLB.scala:174:105, :339:29] wire _hitsVec_T_4 = _hitsVec_T_2 & _hitsVec_T_3; // @[TLB.scala:174:{86,95,105}] wire [3:0] _GEN_16 = {{sectored_entries_0_0_valid_3}, {sectored_entries_0_0_valid_2}, {sectored_entries_0_0_valid_1}, {sectored_entries_0_0_valid_0}}; // @[TLB.scala:188:18, :339:29] wire _hitsVec_T_5 = _GEN_16[hitsVec_idx] & _hitsVec_T_4; // @[package.scala:163:13] wire hitsVec_0 = vm_enabled & _hitsVec_T_5; // @[TLB.scala:188:18, :399:61, :440:44] wire [24:0] _hitsVec_T_7 = _hitsVec_T_6[26:2]; // @[TLB.scala:174:{61,68}] wire _hitsVec_T_8 = _hitsVec_T_7 == 25'h0; // @[TLB.scala:174:{68,86}] wire _hitsVec_T_9 = ~sectored_entries_0_1_tag_v; // @[TLB.scala:174:105, :339:29] wire _hitsVec_T_10 = _hitsVec_T_8 & _hitsVec_T_9; // @[TLB.scala:174:{86,95,105}] wire [3:0] _GEN_17 = {{sectored_entries_0_1_valid_3}, {sectored_entries_0_1_valid_2}, {sectored_entries_0_1_valid_1}, {sectored_entries_0_1_valid_0}}; // @[TLB.scala:188:18, :339:29] wire _hitsVec_T_11 = _GEN_17[hitsVec_idx_1] & _hitsVec_T_10; // @[package.scala:163:13] wire hitsVec_1 = vm_enabled & _hitsVec_T_11; // @[TLB.scala:188:18, :399:61, :440:44] wire [24:0] _hitsVec_T_13 = _hitsVec_T_12[26:2]; // @[TLB.scala:174:{61,68}] wire _hitsVec_T_14 = _hitsVec_T_13 == 25'h0; // @[TLB.scala:174:{68,86}] wire _hitsVec_T_15 = ~sectored_entries_0_2_tag_v; // @[TLB.scala:174:105, :339:29] wire _hitsVec_T_16 = _hitsVec_T_14 & _hitsVec_T_15; // @[TLB.scala:174:{86,95,105}] wire [3:0] _GEN_18 = {{sectored_entries_0_2_valid_3}, {sectored_entries_0_2_valid_2}, {sectored_entries_0_2_valid_1}, {sectored_entries_0_2_valid_0}}; // @[TLB.scala:188:18, :339:29] wire _hitsVec_T_17 = _GEN_18[hitsVec_idx_2] & _hitsVec_T_16; // @[package.scala:163:13] wire hitsVec_2 = vm_enabled & _hitsVec_T_17; // @[TLB.scala:188:18, :399:61, :440:44] wire [24:0] _hitsVec_T_19 = _hitsVec_T_18[26:2]; // @[TLB.scala:174:{61,68}] wire _hitsVec_T_20 = _hitsVec_T_19 == 25'h0; // @[TLB.scala:174:{68,86}] wire _hitsVec_T_21 = ~sectored_entries_0_3_tag_v; // @[TLB.scala:174:105, :339:29] wire _hitsVec_T_22 = _hitsVec_T_20 & _hitsVec_T_21; // @[TLB.scala:174:{86,95,105}] wire [3:0] _GEN_19 = {{sectored_entries_0_3_valid_3}, {sectored_entries_0_3_valid_2}, {sectored_entries_0_3_valid_1}, {sectored_entries_0_3_valid_0}}; // @[TLB.scala:188:18, :339:29] wire _hitsVec_T_23 = _GEN_19[hitsVec_idx_3] & _hitsVec_T_22; // @[package.scala:163:13] wire hitsVec_3 = vm_enabled & _hitsVec_T_23; // @[TLB.scala:188:18, :399:61, :440:44] wire [24:0] _hitsVec_T_25 = _hitsVec_T_24[26:2]; // @[TLB.scala:174:{61,68}] wire _hitsVec_T_26 = _hitsVec_T_25 == 25'h0; // @[TLB.scala:174:{68,86}] wire _hitsVec_T_27 = ~sectored_entries_0_4_tag_v; // @[TLB.scala:174:105, :339:29] wire _hitsVec_T_28 = _hitsVec_T_26 & _hitsVec_T_27; // @[TLB.scala:174:{86,95,105}] wire [3:0] _GEN_20 = {{sectored_entries_0_4_valid_3}, {sectored_entries_0_4_valid_2}, {sectored_entries_0_4_valid_1}, {sectored_entries_0_4_valid_0}}; // @[TLB.scala:188:18, :339:29] wire _hitsVec_T_29 = _GEN_20[hitsVec_idx_4] & _hitsVec_T_28; // @[package.scala:163:13] wire hitsVec_4 = vm_enabled & _hitsVec_T_29; // @[TLB.scala:188:18, :399:61, :440:44] wire [24:0] _hitsVec_T_31 = _hitsVec_T_30[26:2]; // @[TLB.scala:174:{61,68}] wire _hitsVec_T_32 = _hitsVec_T_31 == 25'h0; // @[TLB.scala:174:{68,86}] wire _hitsVec_T_33 = ~sectored_entries_0_5_tag_v; // @[TLB.scala:174:105, :339:29] wire _hitsVec_T_34 = _hitsVec_T_32 & _hitsVec_T_33; // @[TLB.scala:174:{86,95,105}] wire [3:0] _GEN_21 = {{sectored_entries_0_5_valid_3}, {sectored_entries_0_5_valid_2}, {sectored_entries_0_5_valid_1}, {sectored_entries_0_5_valid_0}}; // @[TLB.scala:188:18, :339:29] wire _hitsVec_T_35 = _GEN_21[hitsVec_idx_5] & _hitsVec_T_34; // @[package.scala:163:13] wire hitsVec_5 = vm_enabled & _hitsVec_T_35; // @[TLB.scala:188:18, :399:61, :440:44] wire [24:0] _hitsVec_T_37 = _hitsVec_T_36[26:2]; // @[TLB.scala:174:{61,68}] wire _hitsVec_T_38 = _hitsVec_T_37 == 25'h0; // @[TLB.scala:174:{68,86}] wire _hitsVec_T_39 = ~sectored_entries_0_6_tag_v; // @[TLB.scala:174:105, :339:29] wire _hitsVec_T_40 = _hitsVec_T_38 & _hitsVec_T_39; // @[TLB.scala:174:{86,95,105}] wire [3:0] _GEN_22 = {{sectored_entries_0_6_valid_3}, {sectored_entries_0_6_valid_2}, {sectored_entries_0_6_valid_1}, {sectored_entries_0_6_valid_0}}; // @[TLB.scala:188:18, :339:29] wire _hitsVec_T_41 = _GEN_22[hitsVec_idx_6] & _hitsVec_T_40; // @[package.scala:163:13] wire hitsVec_6 = vm_enabled & _hitsVec_T_41; // @[TLB.scala:188:18, :399:61, :440:44] wire [24:0] _hitsVec_T_43 = _hitsVec_T_42[26:2]; // @[TLB.scala:174:{61,68}] wire _hitsVec_T_44 = _hitsVec_T_43 == 25'h0; // @[TLB.scala:174:{68,86}] wire _hitsVec_T_45 = ~sectored_entries_0_7_tag_v; // @[TLB.scala:174:105, :339:29] wire _hitsVec_T_46 = _hitsVec_T_44 & _hitsVec_T_45; // @[TLB.scala:174:{86,95,105}] wire [3:0] _GEN_23 = {{sectored_entries_0_7_valid_3}, {sectored_entries_0_7_valid_2}, {sectored_entries_0_7_valid_1}, {sectored_entries_0_7_valid_0}}; // @[TLB.scala:188:18, :339:29] wire _hitsVec_T_47 = _GEN_23[hitsVec_idx_7] & _hitsVec_T_46; // @[package.scala:163:13] wire hitsVec_7 = vm_enabled & _hitsVec_T_47; // @[TLB.scala:188:18, :399:61, :440:44] wire _hitsVec_tagMatch_T = ~superpage_entries_0_tag_v; // @[TLB.scala:178:43, :341:30] wire hitsVec_tagMatch = superpage_entries_0_valid_0 & _hitsVec_tagMatch_T; // @[TLB.scala:178:{33,43}, :341:30] wire [8:0] _hitsVec_T_49 = _hitsVec_T_48[26:18]; // @[TLB.scala:183:{52,58}] wire _hitsVec_T_50 = _hitsVec_T_49 == 9'h0; // @[TLB.scala:183:{58,79}] wire _hitsVec_T_51 = _hitsVec_T_50; // @[TLB.scala:183:{40,79}] wire _hitsVec_T_52 = hitsVec_tagMatch & _hitsVec_T_51; // @[TLB.scala:178:33, :183:{29,40}] wire hitsVec_ignore_1 = _hitsVec_ignore_T_1; // @[TLB.scala:182:{28,34}] wire [8:0] _hitsVec_T_54 = _hitsVec_T_53[17:9]; // @[TLB.scala:183:{52,58}] wire _hitsVec_T_55 = _hitsVec_T_54 == 9'h0; // @[TLB.scala:183:{58,79}] wire _hitsVec_T_56 = hitsVec_ignore_1 \| _hitsVec_T_55; // @[TLB.scala:182:34, :183:{40,79}] wire _hitsVec_T_57 = _hitsVec_T_52 & _hitsVec_T_56; // @[TLB.scala:183:{29,40}] wire _hitsVec_T_62 = _hitsVec_T_57; // @[TLB.scala:183:29] wire _hitsVec_ignore_T_2 = ~(superpage_entries_0_level[1]); // @[TLB.scala:182:28, :341:30] wire [8:0] _hitsVec_T_59 = _hitsVec_T_58[8:0]; // @[TLB.scala:183:{52,58}] wire _hitsVec_T_60 = _hitsVec_T_59 == 9'h0; // @[TLB.scala:183:{58,79}] wire hitsVec_8 = vm_enabled & _hitsVec_T_62; // @[TLB.scala:183:29, :399:61, :440:44] wire _hitsVec_tagMatch_T_1 = ~superpage_entries_1_tag_v; // @[TLB.scala:178:43, :341:30] wire hitsVec_tagMatch_1 = superpage_entries_1_valid_0 & _hitsVec_tagMatch_T_1; // @[TLB.scala:178:{33,43}, :341:30] wire [8:0] _hitsVec_T_64 = _hitsVec_T_63[26:18]; // @[TLB.scala:183:{52,58}] wire _hitsVec_T_65 = _hitsVec_T_64 == 9'h0; // @[TLB.scala:183:{58,79}] wire _hitsVec_T_66 = _hitsVec_T_65; // @[TLB.scala:183:{40,79}] wire _hitsVec_T_67 = hitsVec_tagMatch_1 & _hitsVec_T_66; // @[TLB.scala:178:33, :183:{29,40}] wire hitsVec_ignore_4 = _hitsVec_ignore_T_4; // @[TLB.scala:182:{28,34}] wire [8:0] _hitsVec_T_69 = _hitsVec_T_68[17:9]; // @[TLB.scala:183:{52,58}] wire _hitsVec_T_70 = _hitsVec_T_69 == 9'h0; // @[TLB.scala:183:{58,79}] wire _hitsVec_T_71 = hitsVec_ignore_4 \| _hitsVec_T_70; // @[TLB.scala:182:34, :183:{40,79}] wire _hitsVec_T_72 = _hitsVec_T_67 & _hitsVec_T_71; // @[TLB.scala:183:{29,40}] wire _hitsVec_T_77 = _hitsVec_T_72; // @[TLB.scala:183:29] wire _hitsVec_ignore_T_5 = ~(superpage_entries_1_level[1]); // @[TLB.scala:182:28, :341:30] wire [8:0] _hitsVec_T_74 = _hitsVec_T_73[8:0]; // @[TLB.scala:183:{52,58}] wire _hitsVec_T_75 = _hitsVec_T_74 == 9'h0; // @[TLB.scala:183:{58,79}] wire hitsVec_9 = vm_enabled & _hitsVec_T_77; // @[TLB.scala:183:29, :399:61, :440:44] wire _hitsVec_tagMatch_T_2 = ~superpage_entries_2_tag_v; // @[TLB.scala:178:43, :341:30] wire hitsVec_tagMatch_2 = superpage_entries_2_valid_0 & _hitsVec_tagMatch_T_2; // @[TLB.scala:178:{33,43}, :341:30] wire [8:0] _hitsVec_T_79 = _hitsVec_T_78[26:18]; // @[TLB.scala:183:{52,58}] wire _hitsVec_T_80 = _hitsVec_T_79 == 9'h0; // @[TLB.scala:183:{58,79}] wire _hitsVec_T_81 = _hitsVec_T_80; // @[TLB.scala:183:{40,79}] wire _hitsVec_T_82 = hitsVec_tagMatch_2 & _hitsVec_T_81; // @[TLB.scala:178:33, :183:{29,40}] wire hitsVec_ignore_7 = _hitsVec_ignore_T_7; // @[TLB.scala:182:{28,34}] wire [8:0] _hitsVec_T_84 = _hitsVec_T_83[17:9]; // @[TLB.scala:183:{52,58}] wire _hitsVec_T_85 = _hitsVec_T_84 == 9'h0; // @[TLB.scala:183:{58,79}] wire _hitsVec_T_86 = hitsVec_ignore_7 \| _hitsVec_T_85; // @[TLB.scala:182:34, :183:{40,79}] wire _hitsVec_T_87 = _hitsVec_T_82 & _hitsVec_T_86; // @[TLB.scala:183:{29,40}] wire _hitsVec_T_92 = _hitsVec_T_87; // @[TLB.scala:183:29] wire _hitsVec_ignore_T_8 = ~(superpage_entries_2_level[1]); // @[TLB.scala:182:28, :341:30] wire [8:0] _hitsVec_T_89 = _hitsVec_T_88[8:0]; // @[TLB.scala:183:{52,58}] wire _hitsVec_T_90 = _hitsVec_T_89 == 9'h0; // @[TLB.scala:183:{58,79}] wire hitsVec_10 = vm_enabled & _hitsVec_T_92; // @[TLB.scala:183:29, :399:61, :440:44] wire _hitsVec_tagMatch_T_3 = ~superpage_entries_3_tag_v; // @[TLB.scala:178:43, :341:30] wire hitsVec_tagMatch_3 = superpage_entries_3_valid_0 & _hitsVec_tagMatch_T_3; // @[TLB.scala:178:{33,43}, :341:30] wire [8:0] _hitsVec_T_94 = _hitsVec_T_93[26:18]; // @[TLB.scala:183:{52,58}] wire _hitsVec_T_95 = _hitsVec_T_94 == 9'h0; // @[TLB.scala:183:{58,79}] wire _hitsVec_T_96 = _hitsVec_T_95; // @[TLB.scala:183:{40,79}] wire _hitsVec_T_97 = hitsVec_tagMatch_3 & _hitsVec_T_96; // @[TLB.scala:178:33, :183:{29,40}] wire hitsVec_ignore_10 = _hitsVec_ignore_T_10; // @[TLB.scala:182:{28,34}] wire [8:0] _hitsVec_T_99 = _hitsVec_T_98[17:9]; // @[TLB.scala:183:{52,58}] wire _hitsVec_T_100 = _hitsVec_T_99 == 9'h0; // @[TLB.scala:183:{58,79}] wire _hitsVec_T_101 = hitsVec_ignore_10 \| _hitsVec_T_100; // @[TLB.scala:182:34, :183:{40,79}] wire _hitsVec_T_102 = _hitsVec_T_97 & _hitsVec_T_101; // @[TLB.scala:183:{29,40}] wire _hitsVec_T_107 = _hitsVec_T_102; // @[TLB.scala:183:29] wire _hitsVec_ignore_T_11 = ~(superpage_entries_3_level[1]); // @[TLB.scala:182:28, :341:30] wire [8:0] _hitsVec_T_104 = _hitsVec_T_103[8:0]; // @[TLB.scala:183:{52,58}] wire _hitsVec_T_105 = _hitsVec_T_104 == 9'h0; // @[TLB.scala:183:{58,79}] wire hitsVec_11 = vm_enabled & _hitsVec_T_107; // @[TLB.scala:183:29, :399:61, :440:44] wire _hitsVec_tagMatch_T_4 = ~special_entry_tag_v; // @[TLB.scala:178:43, :346:56] wire hitsVec_tagMatch_4 = special_entry_valid_0 & _hitsVec_tagMatch_T_4; // @[TLB.scala:178:{33,43}, :346:56] wire [26:0] _T_3838 = special_entry_tag_vpn ^ vpn; // @[TLB.scala:183:52, :335:30, :346:56] wire [26:0] _hitsVec_T_108; // @[TLB.scala:183:52] assign _hitsVec_T_108 = _T_3838; // @[TLB.scala:183:52] wire [26:0] _hitsVec_T_113; // @[TLB.scala:183:52] assign _hitsVec_T_113 = _T_3838; // @[TLB.scala:183:52] wire [26:0] _hitsVec_T_118; // @[TLB.scala:183:52] assign _hitsVec_T_118 = _T_3838; // @[TLB.scala:183:52] wire [8:0] _hitsVec_T_109 = _hitsVec_T_108[26:18]; // @[TLB.scala:183:{52,58}] wire _hitsVec_T_110 = _hitsVec_T_109 == 9'h0; // @[TLB.scala:183:{58,79}] wire _hitsVec_T_111 = _hitsVec_T_110; // @[TLB.scala:183:{40,79}] wire _hitsVec_T_112 = hitsVec_tagMatch_4 & _hitsVec_T_111; // @[TLB.scala:178:33, :183:{29,40}] wire hitsVec_ignore_13 = _hitsVec_ignore_T_13; // @[TLB.scala:182:{28,34}] wire [8:0] _hitsVec_T_114 = _hitsVec_T_113[17:9]; // @[TLB.scala:183:{52,58}] wire _hitsVec_T_115 = _hitsVec_T_114 == 9'h0; // @[TLB.scala:183:{58,79}] wire _hitsVec_T_116 = hitsVec_ignore_13 \| _hitsVec_T_115; // @[TLB.scala:182:34, :183:{40,79}] wire _hitsVec_T_117 = _hitsVec_T_112 & _hitsVec_T_116; // @[TLB.scala:183:{29,40}] wire _hitsVec_ignore_T_14 = ~(special_entry_level[1]); // @[TLB.scala:182:28, :197:28, :346:56] wire hitsVec_ignore_14 = _hitsVec_ignore_T_14; // @[TLB.scala:182:{28,34}] wire [8:0] _hitsVec_T_119 = _hitsVec_T_118[8:0]; // @[TLB.scala:183:{52,58}] wire _hitsVec_T_120 = _hitsVec_T_119 == 9'h0; // @[TLB.scala:183:{58,79}] wire _hitsVec_T_121 = hitsVec_ignore_14 \| _hitsVec_T_120; // @[TLB.scala:182:34, :183:{40,79}] wire _hitsVec_T_122 = _hitsVec_T_117 & _hitsVec_T_121; // @[TLB.scala:183:{29,40}] wire hitsVec_12 = vm_enabled & _hitsVec_T_122; // @[TLB.scala:183:29, :399:61, :440:44] wire [1:0] real_hits_lo_lo_hi = {hitsVec_2, hitsVec_1}; // @[package.scala:45:27] wire [2:0] real_hits_lo_lo = {real_hits_lo_lo_hi, hitsVec_0}; // @[package.scala:45:27] wire [1:0] real_hits_lo_hi_hi = {hitsVec_5, hitsVec_4}; // @[package.scala:45:27] wire [2:0] real_hits_lo_hi = {real_hits_lo_hi_hi, hitsVec_3}; // @[package.scala:45:27] wire [5:0] real_hits_lo = {real_hits_lo_hi, real_hits_lo_lo}; // @[package.scala:45:27] wire [1:0] real_hits_hi_lo_hi = {hitsVec_8, hitsVec_7}; // @[package.scala:45:27] wire [2:0] real_hits_hi_lo = {real_hits_hi_lo_hi, hitsVec_6}; // @[package.scala:45:27] wire [1:0] real_hits_hi_hi_lo = {hitsVec_10, hitsVec_9}; // @[package.scala:45:27] wire [1:0] real_hits_hi_hi_hi = {hitsVec_12, hitsVec_11}; // @[package.scala:45:27] wire [3:0] real_hits_hi_hi = {real_hits_hi_hi_hi, real_hits_hi_hi_lo}; // @[package.scala:45:27] wire [6:0] real_hits_hi = {real_hits_hi_hi, real_hits_hi_lo}; // @[package.scala:45:27] wire [12:0] real_hits = {real_hits_hi, real_hits_lo}; // @[package.scala:45:27] wire [12:0] _tlb_hit_T = real_hits; // @[package.scala:45:27] wire _hits_T = ~vm_enabled; // @[TLB.scala:399:61, :442:18] wire [13:0] hits = {_hits_T, real_hits}; // @[package.scala:45:27] wire _newEntry_g_T; // @[TLB.scala:453:25] wire _newEntry_sw_T_6; // @[PTW.scala:151:40] wire _newEntry_sx_T_5; // @[PTW.scala:153:35] wire _newEntry_sr_T_5; // @[PTW.scala:149:35] wire newEntry_g; // @[TLB.scala:449:24] wire newEntry_sw; // @[TLB.scala:449:24] wire newEntry_sx; // @[TLB.scala:449:24] wire newEntry_sr; // @[TLB.scala:449:24] wire newEntry_ppp; // @[TLB.scala:449:24] wire newEntry_pal; // @[TLB.scala:449:24] wire newEntry_paa; // @[TLB.scala:449:24] wire newEntry_eff; // @[TLB.scala:449:24] assign _newEntry_g_T = io_ptw_resp_bits_pte_g_0 & io_ptw_resp_bits_pte_v_0; // @[TLB.scala:318:7, :453:25] assign newEntry_g = _newEntry_g_T; // @[TLB.scala:449:24, :453:25] wire _newEntry_ae_stage2_T = io_ptw_resp_bits_ae_final_0 & io_ptw_resp_bits_gpa_is_pte_0; // @[TLB.scala:318:7, :456:53] wire _newEntry_sr_T = ~io_ptw_resp_bits_pte_w_0; // @[TLB.scala:318:7] wire _newEntry_sr_T_1 = io_ptw_resp_bits_pte_x_0 & _newEntry_sr_T; // @[TLB.scala:318:7] wire _newEntry_sr_T_2 = io_ptw_resp_bits_pte_r_0 \| _newEntry_sr_T_1; // @[TLB.scala:318:7] wire _newEntry_sr_T_3 = io_ptw_resp_bits_pte_v_0 & _newEntry_sr_T_2; // @[TLB.scala:318:7] wire _newEntry_sr_T_4 = _newEntry_sr_T_3 & io_ptw_resp_bits_pte_a_0; // @[TLB.scala:318:7] assign _newEntry_sr_T_5 = _newEntry_sr_T_4 & io_ptw_resp_bits_pte_r_0; // @[TLB.scala:318:7] assign newEntry_sr = _newEntry_sr_T_5; // @[TLB.scala:449:24] wire _newEntry_sw_T = ~io_ptw_resp_bits_pte_w_0; // @[TLB.scala:318:7] wire _newEntry_sw_T_1 = io_ptw_resp_bits_pte_x_0 & _newEntry_sw_T; // @[TLB.scala:318:7] wire _newEntry_sw_T_2 = io_ptw_resp_bits_pte_r_0 \| _newEntry_sw_T_1; // @[TLB.scala:318:7] wire _newEntry_sw_T_3 = io_ptw_resp_bits_pte_v_0 & _newEntry_sw_T_2; // @[TLB.scala:318:7] wire _newEntry_sw_T_4 = _newEntry_sw_T_3 & io_ptw_resp_bits_pte_a_0; // @[TLB.scala:318:7] wire _newEntry_sw_T_5 = _newEntry_sw_T_4 & io_ptw_resp_bits_pte_w_0; // @[TLB.scala:318:7] assign _newEntry_sw_T_6 = _newEntry_sw_T_5 & io_ptw_resp_bits_pte_d_0; // @[TLB.scala:318:7] assign newEntry_sw = _newEntry_sw_T_6; // @[TLB.scala:449:24] wire _newEntry_sx_T = ~io_ptw_resp_bits_pte_w_0; // @[TLB.scala:318:7] wire _newEntry_sx_T_1 = io_ptw_resp_bits_pte_x_0 & _newEntry_sx_T; // @[TLB.scala:318:7] wire _newEntry_sx_T_2 = io_ptw_resp_bits_pte_r_0 \| _newEntry_sx_T_1; // @[TLB.scala:318:7] wire _newEntry_sx_T_3 = io_ptw_resp_bits_pte_v_0 & _newEntry_sx_T_2; // @[TLB.scala:318:7] wire _newEntry_sx_T_4 = _newEntry_sx_T_3 & io_ptw_resp_bits_pte_a_0; // @[TLB.scala:318:7] assign _newEntry_sx_T_5 = _newEntry_sx_T_4 & io_ptw_resp_bits_pte_x_0; // @[TLB.scala:318:7] assign newEntry_sx = _newEntry_sx_T_5; // @[TLB.scala:449:24] wire [1:0] _GEN_24 = {newEntry_c, 1'h0}; // @[TLB.scala:217:24, :449:24] wire [1:0] special_entry_data_0_lo_lo_lo; // @[TLB.scala:217:24] assign special_entry_data_0_lo_lo_lo = _GEN_24; // @[TLB.scala:217:24] wire [1:0] superpage_entries_0_data_0_lo_lo_lo; // @[TLB.scala:217:24] assign superpage_entries_0_data_0_lo_lo_lo = _GEN_24; // @[TLB.scala:217:24] wire [1:0] superpage_entries_1_data_0_lo_lo_lo; // @[TLB.scala:217:24] assign superpage_entries_1_data_0_lo_lo_lo = _GEN_24; // @[TLB.scala:217:24] wire [1:0] superpage_entries_2_data_0_lo_lo_lo; // @[TLB.scala:217:24] assign superpage_entries_2_data_0_lo_lo_lo = _GEN_24; // @[TLB.scala:217:24] wire [1:0] superpage_entries_3_data_0_lo_lo_lo; // @[TLB.scala:217:24] assign superpage_entries_3_data_0_lo_lo_lo = _GEN_24; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_0_data_lo_lo_lo; // @[TLB.scala:217:24] assign sectored_entries_0_0_data_lo_lo_lo = _GEN_24; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_1_data_lo_lo_lo; // @[TLB.scala:217:24] assign sectored_entries_0_1_data_lo_lo_lo = _GEN_24; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_2_data_lo_lo_lo; // @[TLB.scala:217:24] assign sectored_entries_0_2_data_lo_lo_lo = _GEN_24; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_3_data_lo_lo_lo; // @[TLB.scala:217:24] assign sectored_entries_0_3_data_lo_lo_lo = _GEN_24; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_4_data_lo_lo_lo; // @[TLB.scala:217:24] assign sectored_entries_0_4_data_lo_lo_lo = _GEN_24; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_5_data_lo_lo_lo; // @[TLB.scala:217:24] assign sectored_entries_0_5_data_lo_lo_lo = _GEN_24; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_6_data_lo_lo_lo; // @[TLB.scala:217:24] assign sectored_entries_0_6_data_lo_lo_lo = _GEN_24; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_7_data_lo_lo_lo; // @[TLB.scala:217:24] assign sectored_entries_0_7_data_lo_lo_lo = _GEN_24; // @[TLB.scala:217:24] wire [1:0] _GEN_25 = {newEntry_pal, newEntry_paa}; // @[TLB.scala:217:24, :449:24] wire [1:0] special_entry_data_0_lo_lo_hi_hi; // @[TLB.scala:217:24] assign special_entry_data_0_lo_lo_hi_hi = _GEN_25; // @[TLB.scala:217:24] wire [1:0] superpage_entries_0_data_0_lo_lo_hi_hi; // @[TLB.scala:217:24] assign superpage_entries_0_data_0_lo_lo_hi_hi = _GEN_25; // @[TLB.scala:217:24] wire [1:0] superpage_entries_1_data_0_lo_lo_hi_hi; // @[TLB.scala:217:24] assign superpage_entries_1_data_0_lo_lo_hi_hi = _GEN_25; // @[TLB.scala:217:24] wire [1:0] superpage_entries_2_data_0_lo_lo_hi_hi; // @[TLB.scala:217:24] assign superpage_entries_2_data_0_lo_lo_hi_hi = _GEN_25; // @[TLB.scala:217:24] wire [1:0] superpage_entries_3_data_0_lo_lo_hi_hi; // @[TLB.scala:217:24] assign superpage_entries_3_data_0_lo_lo_hi_hi = _GEN_25; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_0_data_lo_lo_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_0_data_lo_lo_hi_hi = _GEN_25; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_1_data_lo_lo_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_1_data_lo_lo_hi_hi = _GEN_25; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_2_data_lo_lo_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_2_data_lo_lo_hi_hi = _GEN_25; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_3_data_lo_lo_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_3_data_lo_lo_hi_hi = _GEN_25; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_4_data_lo_lo_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_4_data_lo_lo_hi_hi = _GEN_25; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_5_data_lo_lo_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_5_data_lo_lo_hi_hi = _GEN_25; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_6_data_lo_lo_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_6_data_lo_lo_hi_hi = _GEN_25; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_7_data_lo_lo_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_7_data_lo_lo_hi_hi = _GEN_25; // @[TLB.scala:217:24] wire [2:0] special_entry_data_0_lo_lo_hi = {special_entry_data_0_lo_lo_hi_hi, newEntry_eff}; // @[TLB.scala:217:24, :449:24] wire [4:0] special_entry_data_0_lo_lo = {special_entry_data_0_lo_lo_hi, special_entry_data_0_lo_lo_lo}; // @[TLB.scala:217:24] wire [1:0] _GEN_26 = {newEntry_px, newEntry_pr}; // @[TLB.scala:217:24, :449:24] wire [1:0] special_entry_data_0_lo_hi_lo_hi; // @[TLB.scala:217:24] assign special_entry_data_0_lo_hi_lo_hi = _GEN_26; // @[TLB.scala:217:24] wire [1:0] superpage_entries_0_data_0_lo_hi_lo_hi; // @[TLB.scala:217:24] assign superpage_entries_0_data_0_lo_hi_lo_hi = _GEN_26; // @[TLB.scala:217:24] wire [1:0] superpage_entries_1_data_0_lo_hi_lo_hi; // @[TLB.scala:217:24] assign superpage_entries_1_data_0_lo_hi_lo_hi = _GEN_26; // @[TLB.scala:217:24] wire [1:0] superpage_entries_2_data_0_lo_hi_lo_hi; // @[TLB.scala:217:24] assign superpage_entries_2_data_0_lo_hi_lo_hi = _GEN_26; // @[TLB.scala:217:24] wire [1:0] superpage_entries_3_data_0_lo_hi_lo_hi; // @[TLB.scala:217:24] assign superpage_entries_3_data_0_lo_hi_lo_hi = _GEN_26; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_0_data_lo_hi_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_0_0_data_lo_hi_lo_hi = _GEN_26; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_1_data_lo_hi_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_0_1_data_lo_hi_lo_hi = _GEN_26; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_2_data_lo_hi_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_0_2_data_lo_hi_lo_hi = _GEN_26; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_3_data_lo_hi_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_0_3_data_lo_hi_lo_hi = _GEN_26; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_4_data_lo_hi_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_0_4_data_lo_hi_lo_hi = _GEN_26; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_5_data_lo_hi_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_0_5_data_lo_hi_lo_hi = _GEN_26; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_6_data_lo_hi_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_0_6_data_lo_hi_lo_hi = _GEN_26; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_7_data_lo_hi_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_0_7_data_lo_hi_lo_hi = _GEN_26; // @[TLB.scala:217:24] wire [2:0] special_entry_data_0_lo_hi_lo = {special_entry_data_0_lo_hi_lo_hi, newEntry_ppp}; // @[TLB.scala:217:24, :449:24] wire [1:0] _GEN_27 = {newEntry_hx, newEntry_hr}; // @[TLB.scala:217:24, :449:24] wire [1:0] special_entry_data_0_lo_hi_hi_hi; // @[TLB.scala:217:24] assign special_entry_data_0_lo_hi_hi_hi = _GEN_27; // @[TLB.scala:217:24] wire [1:0] superpage_entries_0_data_0_lo_hi_hi_hi; // @[TLB.scala:217:24] assign superpage_entries_0_data_0_lo_hi_hi_hi = _GEN_27; // @[TLB.scala:217:24] wire [1:0] superpage_entries_1_data_0_lo_hi_hi_hi; // @[TLB.scala:217:24] assign superpage_entries_1_data_0_lo_hi_hi_hi = _GEN_27; // @[TLB.scala:217:24] wire [1:0] superpage_entries_2_data_0_lo_hi_hi_hi; // @[TLB.scala:217:24] assign superpage_entries_2_data_0_lo_hi_hi_hi = _GEN_27; // @[TLB.scala:217:24] wire [1:0] superpage_entries_3_data_0_lo_hi_hi_hi; // @[TLB.scala:217:24] assign superpage_entries_3_data_0_lo_hi_hi_hi = _GEN_27; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_0_data_lo_hi_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_0_data_lo_hi_hi_hi = _GEN_27; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_1_data_lo_hi_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_1_data_lo_hi_hi_hi = _GEN_27; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_2_data_lo_hi_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_2_data_lo_hi_hi_hi = _GEN_27; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_3_data_lo_hi_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_3_data_lo_hi_hi_hi = _GEN_27; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_4_data_lo_hi_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_4_data_lo_hi_hi_hi = _GEN_27; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_5_data_lo_hi_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_5_data_lo_hi_hi_hi = _GEN_27; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_6_data_lo_hi_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_6_data_lo_hi_hi_hi = _GEN_27; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_7_data_lo_hi_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_7_data_lo_hi_hi_hi = _GEN_27; // @[TLB.scala:217:24] wire [2:0] special_entry_data_0_lo_hi_hi = {special_entry_data_0_lo_hi_hi_hi, newEntry_pw}; // @[TLB.scala:217:24, :449:24] wire [5:0] special_entry_data_0_lo_hi = {special_entry_data_0_lo_hi_hi, special_entry_data_0_lo_hi_lo}; // @[TLB.scala:217:24] wire [10:0] special_entry_data_0_lo = {special_entry_data_0_lo_hi, special_entry_data_0_lo_lo}; // @[TLB.scala:217:24] wire [1:0] _GEN_28 = {newEntry_sx, newEntry_sr}; // @[TLB.scala:217:24, :449:24] wire [1:0] special_entry_data_0_hi_lo_lo_hi; // @[TLB.scala:217:24] assign special_entry_data_0_hi_lo_lo_hi = _GEN_28; // @[TLB.scala:217:24] wire [1:0] superpage_entries_0_data_0_hi_lo_lo_hi; // @[TLB.scala:217:24] assign superpage_entries_0_data_0_hi_lo_lo_hi = _GEN_28; // @[TLB.scala:217:24] wire [1:0] superpage_entries_1_data_0_hi_lo_lo_hi; // @[TLB.scala:217:24] assign superpage_entries_1_data_0_hi_lo_lo_hi = _GEN_28; // @[TLB.scala:217:24] wire [1:0] superpage_entries_2_data_0_hi_lo_lo_hi; // @[TLB.scala:217:24] assign superpage_entries_2_data_0_hi_lo_lo_hi = _GEN_28; // @[TLB.scala:217:24] wire [1:0] superpage_entries_3_data_0_hi_lo_lo_hi; // @[TLB.scala:217:24] assign superpage_entries_3_data_0_hi_lo_lo_hi = _GEN_28; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_0_data_hi_lo_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_0_0_data_hi_lo_lo_hi = _GEN_28; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_1_data_hi_lo_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_0_1_data_hi_lo_lo_hi = _GEN_28; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_2_data_hi_lo_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_0_2_data_hi_lo_lo_hi = _GEN_28; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_3_data_hi_lo_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_0_3_data_hi_lo_lo_hi = _GEN_28; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_4_data_hi_lo_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_0_4_data_hi_lo_lo_hi = _GEN_28; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_5_data_hi_lo_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_0_5_data_hi_lo_lo_hi = _GEN_28; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_6_data_hi_lo_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_0_6_data_hi_lo_lo_hi = _GEN_28; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_7_data_hi_lo_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_0_7_data_hi_lo_lo_hi = _GEN_28; // @[TLB.scala:217:24] wire [2:0] special_entry_data_0_hi_lo_lo = {special_entry_data_0_hi_lo_lo_hi, newEntry_hw}; // @[TLB.scala:217:24, :449:24] wire [1:0] _GEN_29 = {newEntry_pf, newEntry_gf}; // @[TLB.scala:217:24, :449:24] wire [1:0] special_entry_data_0_hi_lo_hi_hi; // @[TLB.scala:217:24] assign special_entry_data_0_hi_lo_hi_hi = _GEN_29; // @[TLB.scala:217:24] wire [1:0] superpage_entries_0_data_0_hi_lo_hi_hi; // @[TLB.scala:217:24] assign superpage_entries_0_data_0_hi_lo_hi_hi = _GEN_29; // @[TLB.scala:217:24] wire [1:0] superpage_entries_1_data_0_hi_lo_hi_hi; // @[TLB.scala:217:24] assign superpage_entries_1_data_0_hi_lo_hi_hi = _GEN_29; // @[TLB.scala:217:24] wire [1:0] superpage_entries_2_data_0_hi_lo_hi_hi; // @[TLB.scala:217:24] assign superpage_entries_2_data_0_hi_lo_hi_hi = _GEN_29; // @[TLB.scala:217:24] wire [1:0] superpage_entries_3_data_0_hi_lo_hi_hi; // @[TLB.scala:217:24] assign superpage_entries_3_data_0_hi_lo_hi_hi = _GEN_29; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_0_data_hi_lo_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_0_data_hi_lo_hi_hi = _GEN_29; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_1_data_hi_lo_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_1_data_hi_lo_hi_hi = _GEN_29; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_2_data_hi_lo_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_2_data_hi_lo_hi_hi = _GEN_29; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_3_data_hi_lo_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_3_data_hi_lo_hi_hi = _GEN_29; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_4_data_hi_lo_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_4_data_hi_lo_hi_hi = _GEN_29; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_5_data_hi_lo_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_5_data_hi_lo_hi_hi = _GEN_29; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_6_data_hi_lo_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_6_data_hi_lo_hi_hi = _GEN_29; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_7_data_hi_lo_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_7_data_hi_lo_hi_hi = _GEN_29; // @[TLB.scala:217:24] wire [2:0] special_entry_data_0_hi_lo_hi = {special_entry_data_0_hi_lo_hi_hi, newEntry_sw}; // @[TLB.scala:217:24, :449:24] wire [5:0] special_entry_data_0_hi_lo = {special_entry_data_0_hi_lo_hi, special_entry_data_0_hi_lo_lo}; // @[TLB.scala:217:24] wire [1:0] _GEN_30 = {newEntry_ae_ptw, newEntry_ae_final}; // @[TLB.scala:217:24, :449:24] wire [1:0] special_entry_data_0_hi_hi_lo_hi; // @[TLB.scala:217:24] assign special_entry_data_0_hi_hi_lo_hi = _GEN_30; // @[TLB.scala:217:24] wire [1:0] superpage_entries_0_data_0_hi_hi_lo_hi; // @[TLB.scala:217:24] assign superpage_entries_0_data_0_hi_hi_lo_hi = _GEN_30; // @[TLB.scala:217:24] wire [1:0] superpage_entries_1_data_0_hi_hi_lo_hi; // @[TLB.scala:217:24] assign superpage_entries_1_data_0_hi_hi_lo_hi = _GEN_30; // @[TLB.scala:217:24] wire [1:0] superpage_entries_2_data_0_hi_hi_lo_hi; // @[TLB.scala:217:24] assign superpage_entries_2_data_0_hi_hi_lo_hi = _GEN_30; // @[TLB.scala:217:24] wire [1:0] superpage_entries_3_data_0_hi_hi_lo_hi; // @[TLB.scala:217:24] assign superpage_entries_3_data_0_hi_hi_lo_hi = _GEN_30; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_0_data_hi_hi_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_0_0_data_hi_hi_lo_hi = _GEN_30; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_1_data_hi_hi_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_0_1_data_hi_hi_lo_hi = _GEN_30; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_2_data_hi_hi_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_0_2_data_hi_hi_lo_hi = _GEN_30; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_3_data_hi_hi_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_0_3_data_hi_hi_lo_hi = _GEN_30; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_4_data_hi_hi_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_0_4_data_hi_hi_lo_hi = _GEN_30; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_5_data_hi_hi_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_0_5_data_hi_hi_lo_hi = _GEN_30; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_6_data_hi_hi_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_0_6_data_hi_hi_lo_hi = _GEN_30; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_7_data_hi_hi_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_0_7_data_hi_hi_lo_hi = _GEN_30; // @[TLB.scala:217:24] wire [2:0] special_entry_data_0_hi_hi_lo = {special_entry_data_0_hi_hi_lo_hi, 1'h0}; // @[TLB.scala:217:24] wire [20:0] _GEN_31 = {newEntry_ppn, newEntry_u}; // @[TLB.scala:217:24, :449:24] wire [20:0] special_entry_data_0_hi_hi_hi_hi; // @[TLB.scala:217:24] assign special_entry_data_0_hi_hi_hi_hi = _GEN_31; // @[TLB.scala:217:24] wire [20:0] superpage_entries_0_data_0_hi_hi_hi_hi; // @[TLB.scala:217:24] assign superpage_entries_0_data_0_hi_hi_hi_hi = _GEN_31; // @[TLB.scala:217:24] wire [20:0] superpage_entries_1_data_0_hi_hi_hi_hi; // @[TLB.scala:217:24] assign superpage_entries_1_data_0_hi_hi_hi_hi = _GEN_31; // @[TLB.scala:217:24] wire [20:0] superpage_entries_2_data_0_hi_hi_hi_hi; // @[TLB.scala:217:24] assign superpage_entries_2_data_0_hi_hi_hi_hi = _GEN_31; // @[TLB.scala:217:24] wire [20:0] superpage_entries_3_data_0_hi_hi_hi_hi; // @[TLB.scala:217:24] assign superpage_entries_3_data_0_hi_hi_hi_hi = _GEN_31; // @[TLB.scala:217:24] wire [20:0] sectored_entries_0_0_data_hi_hi_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_0_data_hi_hi_hi_hi = _GEN_31; // @[TLB.scala:217:24] wire [20:0] sectored_entries_0_1_data_hi_hi_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_1_data_hi_hi_hi_hi = _GEN_31; // @[TLB.scala:217:24] wire [20:0] sectored_entries_0_2_data_hi_hi_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_2_data_hi_hi_hi_hi = _GEN_31; // @[TLB.scala:217:24] wire [20:0] sectored_entries_0_3_data_hi_hi_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_3_data_hi_hi_hi_hi = _GEN_31; // @[TLB.scala:217:24] wire [20:0] sectored_entries_0_4_data_hi_hi_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_4_data_hi_hi_hi_hi = _GEN_31; // @[TLB.scala:217:24] wire [20:0] sectored_entries_0_5_data_hi_hi_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_5_data_hi_hi_hi_hi = _GEN_31; // @[TLB.scala:217:24] wire [20:0] sectored_entries_0_6_data_hi_hi_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_6_data_hi_hi_hi_hi = _GEN_31; // @[TLB.scala:217:24] wire [20:0] sectored_entries_0_7_data_hi_hi_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_7_data_hi_hi_hi_hi = _GEN_31; // @[TLB.scala:217:24] wire [21:0] special_entry_data_0_hi_hi_hi = {special_entry_data_0_hi_hi_hi_hi, newEntry_g}; // @[TLB.scala:217:24, :449:24] wire [24:0] special_entry_data_0_hi_hi = {special_entry_data_0_hi_hi_hi, special_entry_data_0_hi_hi_lo}; // @[TLB.scala:217:24] wire [30:0] special_entry_data_0_hi = {special_entry_data_0_hi_hi, special_entry_data_0_hi_lo}; // @[TLB.scala:217:24] wire [41:0] _special_entry_data_0_T = {special_entry_data_0_hi, special_entry_data_0_lo}; // @[TLB.scala:217:24] wire _superpage_entries_0_level_T = io_ptw_resp_bits_level_0[0]; // @[package.scala:163:13] wire _superpage_entries_1_level_T = io_ptw_resp_bits_level_0[0]; // @[package.scala:163:13] wire _superpage_entries_2_level_T = io_ptw_resp_bits_level_0[0]; // @[package.scala:163:13] wire _superpage_entries_3_level_T = io_ptw_resp_bits_level_0[0]; // @[package.scala:163:13] wire [2:0] superpage_entries_0_data_0_lo_lo_hi = {superpage_entries_0_data_0_lo_lo_hi_hi, newEntry_eff}; // @[TLB.scala:217:24, :449:24] wire [4:0] superpage_entries_0_data_0_lo_lo = {superpage_entries_0_data_0_lo_lo_hi, superpage_entries_0_data_0_lo_lo_lo}; // @[TLB.scala:217:24] wire [2:0] superpage_entries_0_data_0_lo_hi_lo = {superpage_entries_0_data_0_lo_hi_lo_hi, newEntry_ppp}; // @[TLB.scala:217:24, :449:24] wire [2:0] superpage_entries_0_data_0_lo_hi_hi = {superpage_entries_0_data_0_lo_hi_hi_hi, newEntry_pw}; // @[TLB.scala:217:24, :449:24] wire [5:0] superpage_entries_0_data_0_lo_hi = {superpage_entries_0_data_0_lo_hi_hi, superpage_entries_0_data_0_lo_hi_lo}; // @[TLB.scala:217:24] wire [10:0] superpage_entries_0_data_0_lo = {superpage_entries_0_data_0_lo_hi, superpage_entries_0_data_0_lo_lo}; // @[TLB.scala:217:24] wire [2:0] superpage_entries_0_data_0_hi_lo_lo = {superpage_entries_0_data_0_hi_lo_lo_hi, newEntry_hw}; // @[TLB.scala:217:24, :449:24] wire [2:0] superpage_entries_0_data_0_hi_lo_hi = {superpage_entries_0_data_0_hi_lo_hi_hi, newEntry_sw}; // @[TLB.scala:217:24, :449:24] wire [5:0] superpage_entries_0_data_0_hi_lo = {superpage_entries_0_data_0_hi_lo_hi, superpage_entries_0_data_0_hi_lo_lo}; // @[TLB.scala:217:24] wire [2:0] superpage_entries_0_data_0_hi_hi_lo = {superpage_entries_0_data_0_hi_hi_lo_hi, 1'h0}; // @[TLB.scala:217:24] wire [21:0] superpage_entries_0_data_0_hi_hi_hi = {superpage_entries_0_data_0_hi_hi_hi_hi, newEntry_g}; // @[TLB.scala:217:24, :449:24] wire [24:0] superpage_entries_0_data_0_hi_hi = {superpage_entries_0_data_0_hi_hi_hi, superpage_entries_0_data_0_hi_hi_lo}; // @[TLB.scala:217:24] wire [30:0] superpage_entries_0_data_0_hi = {superpage_entries_0_data_0_hi_hi, superpage_entries_0_data_0_hi_lo}; // @[TLB.scala:217:24] wire [41:0] _superpage_entries_0_data_0_T = {superpage_entries_0_data_0_hi, superpage_entries_0_data_0_lo}; // @[TLB.scala:217:24] wire [2:0] superpage_entries_1_data_0_lo_lo_hi = {superpage_entries_1_data_0_lo_lo_hi_hi, newEntry_eff}; // @[TLB.scala:217:24, :449:24] wire [4:0] superpage_entries_1_data_0_lo_lo = {superpage_entries_1_data_0_lo_lo_hi, superpage_entries_1_data_0_lo_lo_lo}; // @[TLB.scala:217:24] wire [2:0] superpage_entries_1_data_0_lo_hi_lo = {superpage_entries_1_data_0_lo_hi_lo_hi, newEntry_ppp}; // @[TLB.scala:217:24, :449:24] wire [2:0] superpage_entries_1_data_0_lo_hi_hi = {superpage_entries_1_data_0_lo_hi_hi_hi, newEntry_pw}; // @[TLB.scala:217:24, :449:24] wire [5:0] superpage_entries_1_data_0_lo_hi = {superpage_entries_1_data_0_lo_hi_hi, superpage_entries_1_data_0_lo_hi_lo}; // @[TLB.scala:217:24] wire [10:0] superpage_entries_1_data_0_lo = {superpage_entries_1_data_0_lo_hi, superpage_entries_1_data_0_lo_lo}; // @[TLB.scala:217:24] wire [2:0] superpage_entries_1_data_0_hi_lo_lo = {superpage_entries_1_data_0_hi_lo_lo_hi, newEntry_hw}; // @[TLB.scala:217:24, :449:24] wire [2:0] superpage_entries_1_data_0_hi_lo_hi = {superpage_entries_1_data_0_hi_lo_hi_hi, newEntry_sw}; // @[TLB.scala:217:24, :449:24] wire [5:0] superpage_entries_1_data_0_hi_lo = {superpage_entries_1_data_0_hi_lo_hi, superpage_entries_1_data_0_hi_lo_lo}; // @[TLB.scala:217:24] wire [2:0] superpage_entries_1_data_0_hi_hi_lo = {superpage_entries_1_data_0_hi_hi_lo_hi, 1'h0}; // @[TLB.scala:217:24] wire [21:0] superpage_entries_1_data_0_hi_hi_hi = {superpage_entries_1_data_0_hi_hi_hi_hi, newEntry_g}; // @[TLB.scala:217:24, :449:24] wire [24:0] superpage_entries_1_data_0_hi_hi = {superpage_entries_1_data_0_hi_hi_hi, superpage_entries_1_data_0_hi_hi_lo}; // @[TLB.scala:217:24] wire [30:0] superpage_entries_1_data_0_hi = {superpage_entries_1_data_0_hi_hi, superpage_entries_1_data_0_hi_lo}; // @[TLB.scala:217:24] wire [41:0] _superpage_entries_1_data_0_T = {superpage_entries_1_data_0_hi, superpage_entries_1_data_0_lo}; // @[TLB.scala:217:24] wire [2:0] superpage_entries_2_data_0_lo_lo_hi = {superpage_entries_2_data_0_lo_lo_hi_hi, newEntry_eff}; // @[TLB.scala:217:24, :449:24] wire [4:0] superpage_entries_2_data_0_lo_lo = {superpage_entries_2_data_0_lo_lo_hi, superpage_entries_2_data_0_lo_lo_lo}; // @[TLB.scala:217:24] wire [2:0] superpage_entries_2_data_0_lo_hi_lo = {superpage_entries_2_data_0_lo_hi_lo_hi, newEntry_ppp}; // @[TLB.scala:217:24, :449:24] wire [2:0] superpage_entries_2_data_0_lo_hi_hi = {superpage_entries_2_data_0_lo_hi_hi_hi, newEntry_pw}; // @[TLB.scala:217:24, :449:24] wire [5:0] superpage_entries_2_data_0_lo_hi = {superpage_entries_2_data_0_lo_hi_hi, superpage_entries_2_data_0_lo_hi_lo}; // @[TLB.scala:217:24] wire [10:0] superpage_entries_2_data_0_lo = {superpage_entries_2_data_0_lo_hi, superpage_entries_2_data_0_lo_lo}; // @[TLB.scala:217:24] wire [2:0] superpage_entries_2_data_0_hi_lo_lo = {superpage_entries_2_data_0_hi_lo_lo_hi, newEntry_hw}; // @[TLB.scala:217:24, :449:24] wire [2:0] superpage_entries_2_data_0_hi_lo_hi = {superpage_entries_2_data_0_hi_lo_hi_hi, newEntry_sw}; // @[TLB.scala:217:24, :449:24] wire [5:0] superpage_entries_2_data_0_hi_lo = {superpage_entries_2_data_0_hi_lo_hi, superpage_entries_2_data_0_hi_lo_lo}; // @[TLB.scala:217:24] wire [2:0] superpage_entries_2_data_0_hi_hi_lo = {superpage_entries_2_data_0_hi_hi_lo_hi, 1'h0}; // @[TLB.scala:217:24] wire [21:0] superpage_entries_2_data_0_hi_hi_hi = {superpage_entries_2_data_0_hi_hi_hi_hi, newEntry_g}; // @[TLB.scala:217:24, :449:24] wire [24:0] superpage_entries_2_data_0_hi_hi = {superpage_entries_2_data_0_hi_hi_hi, superpage_entries_2_data_0_hi_hi_lo}; // @[TLB.scala:217:24] wire [30:0] superpage_entries_2_data_0_hi = {superpage_entries_2_data_0_hi_hi, superpage_entries_2_data_0_hi_lo}; // @[TLB.scala:217:24] wire [41:0] _superpage_entries_2_data_0_T = {superpage_entries_2_data_0_hi, superpage_entries_2_data_0_lo}; // @[TLB.scala:217:24] wire [2:0] superpage_entries_3_data_0_lo_lo_hi = {superpage_entries_3_data_0_lo_lo_hi_hi, newEntry_eff}; // @[TLB.scala:217:24, :449:24] wire [4:0] superpage_entries_3_data_0_lo_lo = {superpage_entries_3_data_0_lo_lo_hi, superpage_entries_3_data_0_lo_lo_lo}; // @[TLB.scala:217:24] wire [2:0] superpage_entries_3_data_0_lo_hi_lo = {superpage_entries_3_data_0_lo_hi_lo_hi, newEntry_ppp}; // @[TLB.scala:217:24, :449:24] wire [2:0] superpage_entries_3_data_0_lo_hi_hi = {superpage_entries_3_data_0_lo_hi_hi_hi, newEntry_pw}; // @[TLB.scala:217:24, :449:24] wire [5:0] superpage_entries_3_data_0_lo_hi = {superpage_entries_3_data_0_lo_hi_hi, superpage_entries_3_data_0_lo_hi_lo}; // @[TLB.scala:217:24] wire [10:0] superpage_entries_3_data_0_lo = {superpage_entries_3_data_0_lo_hi, superpage_entries_3_data_0_lo_lo}; // @[TLB.scala:217:24] wire [2:0] superpage_entries_3_data_0_hi_lo_lo = {superpage_entries_3_data_0_hi_lo_lo_hi, newEntry_hw}; // @[TLB.scala:217:24, :449:24] wire [2:0] superpage_entries_3_data_0_hi_lo_hi = {superpage_entries_3_data_0_hi_lo_hi_hi, newEntry_sw}; // @[TLB.scala:217:24, :449:24] wire [5:0] superpage_entries_3_data_0_hi_lo = {superpage_entries_3_data_0_hi_lo_hi, superpage_entries_3_data_0_hi_lo_lo}; // @[TLB.scala:217:24] wire [2:0] superpage_entries_3_data_0_hi_hi_lo = {superpage_entries_3_data_0_hi_hi_lo_hi, 1'h0}; // @[TLB.scala:217:24] wire [21:0] superpage_entries_3_data_0_hi_hi_hi = {superpage_entries_3_data_0_hi_hi_hi_hi, newEntry_g}; // @[TLB.scala:217:24, :449:24] wire [24:0] superpage_entries_3_data_0_hi_hi = {superpage_entries_3_data_0_hi_hi_hi, superpage_entries_3_data_0_hi_hi_lo}; // @[TLB.scala:217:24] wire [30:0] superpage_entries_3_data_0_hi = {superpage_entries_3_data_0_hi_hi, superpage_entries_3_data_0_hi_lo}; // @[TLB.scala:217:24] wire [41:0] _superpage_entries_3_data_0_T = {superpage_entries_3_data_0_hi, superpage_entries_3_data_0_lo}; // @[TLB.scala:217:24] wire [2:0] waddr_1 = r_sectored_hit_valid ? r_sectored_hit_bits : r_sectored_repl_addr; // @[TLB.scala:356:33, :357:27, :485:22] wire [1:0] idx = r_refill_tag[1:0]; // @[package.scala:163:13] wire [1:0] idx_1 = r_refill_tag[1:0]; // @[package.scala:163:13] wire [1:0] idx_2 = r_refill_tag[1:0]; // @[package.scala:163:13] wire [1:0] idx_3 = r_refill_tag[1:0]; // @[package.scala:163:13] wire [1:0] idx_4 = r_refill_tag[1:0]; // @[package.scala:163:13] wire [1:0] idx_5 = r_refill_tag[1:0]; // @[package.scala:163:13] wire [1:0] idx_6 = r_refill_tag[1:0]; // @[package.scala:163:13] wire [1:0] idx_7 = r_refill_tag[1:0]; // @[package.scala:163:13] wire [2:0] sectored_entries_0_0_data_lo_lo_hi = {sectored_entries_0_0_data_lo_lo_hi_hi, newEntry_eff}; // @[TLB.scala:217:24, :449:24] wire [4:0] sectored_entries_0_0_data_lo_lo = {sectored_entries_0_0_data_lo_lo_hi, sectored_entries_0_0_data_lo_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_0_data_lo_hi_lo = {sectored_entries_0_0_data_lo_hi_lo_hi, newEntry_ppp}; // @[TLB.scala:217:24, :449:24] wire [2:0] sectored_entries_0_0_data_lo_hi_hi = {sectored_entries_0_0_data_lo_hi_hi_hi, newEntry_pw}; // @[TLB.scala:217:24, :449:24] wire [5:0] sectored_entries_0_0_data_lo_hi = {sectored_entries_0_0_data_lo_hi_hi, sectored_entries_0_0_data_lo_hi_lo}; // @[TLB.scala:217:24] wire [10:0] sectored_entries_0_0_data_lo = {sectored_entries_0_0_data_lo_hi, sectored_entries_0_0_data_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_0_data_hi_lo_lo = {sectored_entries_0_0_data_hi_lo_lo_hi, newEntry_hw}; // @[TLB.scala:217:24, :449:24] wire [2:0] sectored_entries_0_0_data_hi_lo_hi = {sectored_entries_0_0_data_hi_lo_hi_hi, newEntry_sw}; // @[TLB.scala:217:24, :449:24] wire [5:0] sectored_entries_0_0_data_hi_lo = {sectored_entries_0_0_data_hi_lo_hi, sectored_entries_0_0_data_hi_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_0_data_hi_hi_lo = {sectored_entries_0_0_data_hi_hi_lo_hi, 1'h0}; // @[TLB.scala:217:24] wire [21:0] sectored_entries_0_0_data_hi_hi_hi = {sectored_entries_0_0_data_hi_hi_hi_hi, newEntry_g}; // @[TLB.scala:217:24, :449:24] wire [24:0] sectored_entries_0_0_data_hi_hi = {sectored_entries_0_0_data_hi_hi_hi, sectored_entries_0_0_data_hi_hi_lo}; // @[TLB.scala:217:24] wire [30:0] sectored_entries_0_0_data_hi = {sectored_entries_0_0_data_hi_hi, sectored_entries_0_0_data_hi_lo}; // @[TLB.scala:217:24] wire [41:0] _sectored_entries_0_0_data_T = {sectored_entries_0_0_data_hi, sectored_entries_0_0_data_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_1_data_lo_lo_hi = {sectored_entries_0_1_data_lo_lo_hi_hi, newEntry_eff}; // @[TLB.scala:217:24, :449:24] wire [4:0] sectored_entries_0_1_data_lo_lo = {sectored_entries_0_1_data_lo_lo_hi, sectored_entries_0_1_data_lo_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_1_data_lo_hi_lo = {sectored_entries_0_1_data_lo_hi_lo_hi, newEntry_ppp}; // @[TLB.scala:217:24, :449:24] wire [2:0] sectored_entries_0_1_data_lo_hi_hi = {sectored_entries_0_1_data_lo_hi_hi_hi, newEntry_pw}; // @[TLB.scala:217:24, :449:24] wire [5:0] sectored_entries_0_1_data_lo_hi = {sectored_entries_0_1_data_lo_hi_hi, sectored_entries_0_1_data_lo_hi_lo}; // @[TLB.scala:217:24] wire [10:0] sectored_entries_0_1_data_lo = {sectored_entries_0_1_data_lo_hi, sectored_entries_0_1_data_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_1_data_hi_lo_lo = {sectored_entries_0_1_data_hi_lo_lo_hi, newEntry_hw}; // @[TLB.scala:217:24, :449:24] wire [2:0] sectored_entries_0_1_data_hi_lo_hi = {sectored_entries_0_1_data_hi_lo_hi_hi, newEntry_sw}; // @[TLB.scala:217:24, :449:24] wire [5:0] sectored_entries_0_1_data_hi_lo = {sectored_entries_0_1_data_hi_lo_hi, sectored_entries_0_1_data_hi_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_1_data_hi_hi_lo = {sectored_entries_0_1_data_hi_hi_lo_hi, 1'h0}; // @[TLB.scala:217:24] wire [21:0] sectored_entries_0_1_data_hi_hi_hi = {sectored_entries_0_1_data_hi_hi_hi_hi, newEntry_g}; // @[TLB.scala:217:24, :449:24] wire [24:0] sectored_entries_0_1_data_hi_hi = {sectored_entries_0_1_data_hi_hi_hi, sectored_entries_0_1_data_hi_hi_lo}; // @[TLB.scala:217:24] wire [30:0] sectored_entries_0_1_data_hi = {sectored_entries_0_1_data_hi_hi, sectored_entries_0_1_data_hi_lo}; // @[TLB.scala:217:24] wire [41:0] _sectored_entries_0_1_data_T = {sectored_entries_0_1_data_hi, sectored_entries_0_1_data_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_2_data_lo_lo_hi = {sectored_entries_0_2_data_lo_lo_hi_hi, newEntry_eff}; // @[TLB.scala:217:24, :449:24] wire [4:0] sectored_entries_0_2_data_lo_lo = {sectored_entries_0_2_data_lo_lo_hi, sectored_entries_0_2_data_lo_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_2_data_lo_hi_lo = {sectored_entries_0_2_data_lo_hi_lo_hi, newEntry_ppp}; // @[TLB.scala:217:24, :449:24] wire [2:0] sectored_entries_0_2_data_lo_hi_hi = {sectored_entries_0_2_data_lo_hi_hi_hi, newEntry_pw}; // @[TLB.scala:217:24, :449:24] wire [5:0] sectored_entries_0_2_data_lo_hi = {sectored_entries_0_2_data_lo_hi_hi, sectored_entries_0_2_data_lo_hi_lo}; // @[TLB.scala:217:24] wire [10:0] sectored_entries_0_2_data_lo = {sectored_entries_0_2_data_lo_hi, sectored_entries_0_2_data_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_2_data_hi_lo_lo = {sectored_entries_0_2_data_hi_lo_lo_hi, newEntry_hw}; // @[TLB.scala:217:24, :449:24] wire [2:0] sectored_entries_0_2_data_hi_lo_hi = {sectored_entries_0_2_data_hi_lo_hi_hi, newEntry_sw}; // @[TLB.scala:217:24, :449:24] wire [5:0] sectored_entries_0_2_data_hi_lo = {sectored_entries_0_2_data_hi_lo_hi, sectored_entries_0_2_data_hi_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_2_data_hi_hi_lo = {sectored_entries_0_2_data_hi_hi_lo_hi, 1'h0}; // @[TLB.scala:217:24] wire [21:0] sectored_entries_0_2_data_hi_hi_hi = {sectored_entries_0_2_data_hi_hi_hi_hi, newEntry_g}; // @[TLB.scala:217:24, :449:24] wire [24:0] sectored_entries_0_2_data_hi_hi = {sectored_entries_0_2_data_hi_hi_hi, sectored_entries_0_2_data_hi_hi_lo}; // @[TLB.scala:217:24] wire [30:0] sectored_entries_0_2_data_hi = {sectored_entries_0_2_data_hi_hi, sectored_entries_0_2_data_hi_lo}; // @[TLB.scala:217:24] wire [41:0] _sectored_entries_0_2_data_T = {sectored_entries_0_2_data_hi, sectored_entries_0_2_data_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_3_data_lo_lo_hi = {sectored_entries_0_3_data_lo_lo_hi_hi, newEntry_eff}; // @[TLB.scala:217:24, :449:24] wire [4:0] sectored_entries_0_3_data_lo_lo = {sectored_entries_0_3_data_lo_lo_hi, sectored_entries_0_3_data_lo_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_3_data_lo_hi_lo = {sectored_entries_0_3_data_lo_hi_lo_hi, newEntry_ppp}; // @[TLB.scala:217:24, :449:24] wire [2:0] sectored_entries_0_3_data_lo_hi_hi = {sectored_entries_0_3_data_lo_hi_hi_hi, newEntry_pw}; // @[TLB.scala:217:24, :449:24] wire [5:0] sectored_entries_0_3_data_lo_hi = {sectored_entries_0_3_data_lo_hi_hi, sectored_entries_0_3_data_lo_hi_lo}; // @[TLB.scala:217:24] wire [10:0] sectored_entries_0_3_data_lo = {sectored_entries_0_3_data_lo_hi, sectored_entries_0_3_data_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_3_data_hi_lo_lo = {sectored_entries_0_3_data_hi_lo_lo_hi, newEntry_hw}; // @[TLB.scala:217:24, :449:24] wire [2:0] sectored_entries_0_3_data_hi_lo_hi = {sectored_entries_0_3_data_hi_lo_hi_hi, newEntry_sw}; // @[TLB.scala:217:24, :449:24] wire [5:0] sectored_entries_0_3_data_hi_lo = {sectored_entries_0_3_data_hi_lo_hi, sectored_entries_0_3_data_hi_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_3_data_hi_hi_lo = {sectored_entries_0_3_data_hi_hi_lo_hi, 1'h0}; // @[TLB.scala:217:24] wire [21:0] sectored_entries_0_3_data_hi_hi_hi = {sectored_entries_0_3_data_hi_hi_hi_hi, newEntry_g}; // @[TLB.scala:217:24, :449:24] wire [24:0] sectored_entries_0_3_data_hi_hi = {sectored_entries_0_3_data_hi_hi_hi, sectored_entries_0_3_data_hi_hi_lo}; // @[TLB.scala:217:24] wire [30:0] sectored_entries_0_3_data_hi = {sectored_entries_0_3_data_hi_hi, sectored_entries_0_3_data_hi_lo}; // @[TLB.scala:217:24] wire [41:0] _sectored_entries_0_3_data_T = {sectored_entries_0_3_data_hi, sectored_entries_0_3_data_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_4_data_lo_lo_hi = {sectored_entries_0_4_data_lo_lo_hi_hi, newEntry_eff}; // @[TLB.scala:217:24, :449:24] wire [4:0] sectored_entries_0_4_data_lo_lo = {sectored_entries_0_4_data_lo_lo_hi, sectored_entries_0_4_data_lo_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_4_data_lo_hi_lo = {sectored_entries_0_4_data_lo_hi_lo_hi, newEntry_ppp}; // @[TLB.scala:217:24, :449:24] wire [2:0] sectored_entries_0_4_data_lo_hi_hi = {sectored_entries_0_4_data_lo_hi_hi_hi, newEntry_pw}; // @[TLB.scala:217:24, :449:24] wire [5:0] sectored_entries_0_4_data_lo_hi = {sectored_entries_0_4_data_lo_hi_hi, sectored_entries_0_4_data_lo_hi_lo}; // @[TLB.scala:217:24] wire [10:0] sectored_entries_0_4_data_lo = {sectored_entries_0_4_data_lo_hi, sectored_entries_0_4_data_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_4_data_hi_lo_lo = {sectored_entries_0_4_data_hi_lo_lo_hi, newEntry_hw}; // @[TLB.scala:217:24, :449:24] wire [2:0] sectored_entries_0_4_data_hi_lo_hi = {sectored_entries_0_4_data_hi_lo_hi_hi, newEntry_sw}; // @[TLB.scala:217:24, :449:24] wire [5:0] sectored_entries_0_4_data_hi_lo = {sectored_entries_0_4_data_hi_lo_hi, sectored_entries_0_4_data_hi_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_4_data_hi_hi_lo = {sectored_entries_0_4_data_hi_hi_lo_hi, 1'h0}; // @[TLB.scala:217:24] wire [21:0] sectored_entries_0_4_data_hi_hi_hi = {sectored_entries_0_4_data_hi_hi_hi_hi, newEntry_g}; // @[TLB.scala:217:24, :449:24] wire [24:0] sectored_entries_0_4_data_hi_hi = {sectored_entries_0_4_data_hi_hi_hi, sectored_entries_0_4_data_hi_hi_lo}; // @[TLB.scala:217:24] wire [30:0] sectored_entries_0_4_data_hi = {sectored_entries_0_4_data_hi_hi, sectored_entries_0_4_data_hi_lo}; // @[TLB.scala:217:24] wire [41:0] _sectored_entries_0_4_data_T = {sectored_entries_0_4_data_hi, sectored_entries_0_4_data_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_5_data_lo_lo_hi = {sectored_entries_0_5_data_lo_lo_hi_hi, newEntry_eff}; // @[TLB.scala:217:24, :449:24] wire [4:0] sectored_entries_0_5_data_lo_lo = {sectored_entries_0_5_data_lo_lo_hi, sectored_entries_0_5_data_lo_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_5_data_lo_hi_lo = {sectored_entries_0_5_data_lo_hi_lo_hi, newEntry_ppp}; // @[TLB.scala:217:24, :449:24] wire [2:0] sectored_entries_0_5_data_lo_hi_hi = {sectored_entries_0_5_data_lo_hi_hi_hi, newEntry_pw}; // @[TLB.scala:217:24, :449:24] wire [5:0] sectored_entries_0_5_data_lo_hi = {sectored_entries_0_5_data_lo_hi_hi, sectored_entries_0_5_data_lo_hi_lo}; // @[TLB.scala:217:24] wire [10:0] sectored_entries_0_5_data_lo = {sectored_entries_0_5_data_lo_hi, sectored_entries_0_5_data_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_5_data_hi_lo_lo = {sectored_entries_0_5_data_hi_lo_lo_hi, newEntry_hw}; // @[TLB.scala:217:24, :449:24] wire [2:0] sectored_entries_0_5_data_hi_lo_hi = {sectored_entries_0_5_data_hi_lo_hi_hi, newEntry_sw}; // @[TLB.scala:217:24, :449:24] wire [5:0] sectored_entries_0_5_data_hi_lo = {sectored_entries_0_5_data_hi_lo_hi, sectored_entries_0_5_data_hi_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_5_data_hi_hi_lo = {sectored_entries_0_5_data_hi_hi_lo_hi, 1'h0}; // @[TLB.scala:217:24] wire [21:0] sectored_entries_0_5_data_hi_hi_hi = {sectored_entries_0_5_data_hi_hi_hi_hi, newEntry_g}; // @[TLB.scala:217:24, :449:24] wire [24:0] sectored_entries_0_5_data_hi_hi = {sectored_entries_0_5_data_hi_hi_hi, sectored_entries_0_5_data_hi_hi_lo}; // @[TLB.scala:217:24] wire [30:0] sectored_entries_0_5_data_hi = {sectored_entries_0_5_data_hi_hi, sectored_entries_0_5_data_hi_lo}; // @[TLB.scala:217:24] wire [41:0] _sectored_entries_0_5_data_T = {sectored_entries_0_5_data_hi, sectored_entries_0_5_data_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_6_data_lo_lo_hi = {sectored_entries_0_6_data_lo_lo_hi_hi, newEntry_eff}; // @[TLB.scala:217:24, :449:24] wire [4:0] sectored_entries_0_6_data_lo_lo = {sectored_entries_0_6_data_lo_lo_hi, sectored_entries_0_6_data_lo_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_6_data_lo_hi_lo = {sectored_entries_0_6_data_lo_hi_lo_hi, newEntry_ppp}; // @[TLB.scala:217:24, :449:24] wire [2:0] sectored_entries_0_6_data_lo_hi_hi = {sectored_entries_0_6_data_lo_hi_hi_hi, newEntry_pw}; // @[TLB.scala:217:24, :449:24] wire [5:0] sectored_entries_0_6_data_lo_hi = {sectored_entries_0_6_data_lo_hi_hi, sectored_entries_0_6_data_lo_hi_lo}; // @[TLB.scala:217:24] wire [10:0] sectored_entries_0_6_data_lo = {sectored_entries_0_6_data_lo_hi, sectored_entries_0_6_data_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_6_data_hi_lo_lo = {sectored_entries_0_6_data_hi_lo_lo_hi, newEntry_hw}; // @[TLB.scala:217:24, :449:24] wire [2:0] sectored_entries_0_6_data_hi_lo_hi = {sectored_entries_0_6_data_hi_lo_hi_hi, newEntry_sw}; // @[TLB.scala:217:24, :449:24] wire [5:0] sectored_entries_0_6_data_hi_lo = {sectored_entries_0_6_data_hi_lo_hi, sectored_entries_0_6_data_hi_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_6_data_hi_hi_lo = {sectored_entries_0_6_data_hi_hi_lo_hi, 1'h0}; // @[TLB.scala:217:24] wire [21:0] sectored_entries_0_6_data_hi_hi_hi = {sectored_entries_0_6_data_hi_hi_hi_hi, newEntry_g}; // @[TLB.scala:217:24, :449:24] wire [24:0] sectored_entries_0_6_data_hi_hi = {sectored_entries_0_6_data_hi_hi_hi, sectored_entries_0_6_data_hi_hi_lo}; // @[TLB.scala:217:24] wire [30:0] sectored_entries_0_6_data_hi = {sectored_entries_0_6_data_hi_hi, sectored_entries_0_6_data_hi_lo}; // @[TLB.scala:217:24] wire [41:0] _sectored_entries_0_6_data_T = {sectored_entries_0_6_data_hi, sectored_entries_0_6_data_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_7_data_lo_lo_hi = {sectored_entries_0_7_data_lo_lo_hi_hi, newEntry_eff}; // @[TLB.scala:217:24, :449:24] wire [4:0] sectored_entries_0_7_data_lo_lo = {sectored_entries_0_7_data_lo_lo_hi, sectored_entries_0_7_data_lo_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_7_data_lo_hi_lo = {sectored_entries_0_7_data_lo_hi_lo_hi, newEntry_ppp}; // @[TLB.scala:217:24, :449:24] wire [2:0] sectored_entries_0_7_data_lo_hi_hi = {sectored_entries_0_7_data_lo_hi_hi_hi, newEntry_pw}; // @[TLB.scala:217:24, :449:24] wire [5:0] sectored_entries_0_7_data_lo_hi = {sectored_entries_0_7_data_lo_hi_hi, sectored_entries_0_7_data_lo_hi_lo}; // @[TLB.scala:217:24] wire [10:0] sectored_entries_0_7_data_lo = {sectored_entries_0_7_data_lo_hi, sectored_entries_0_7_data_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_7_data_hi_lo_lo = {sectored_entries_0_7_data_hi_lo_lo_hi, newEntry_hw}; // @[TLB.scala:217:24, :449:24] wire [2:0] sectored_entries_0_7_data_hi_lo_hi = {sectored_entries_0_7_data_hi_lo_hi_hi, newEntry_sw}; // @[TLB.scala:217:24, :449:24] wire [5:0] sectored_entries_0_7_data_hi_lo = {sectored_entries_0_7_data_hi_lo_hi, sectored_entries_0_7_data_hi_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_7_data_hi_hi_lo = {sectored_entries_0_7_data_hi_hi_lo_hi, 1'h0}; // @[TLB.scala:217:24] wire [21:0] sectored_entries_0_7_data_hi_hi_hi = {sectored_entries_0_7_data_hi_hi_hi_hi, newEntry_g}; // @[TLB.scala:217:24, :449:24] wire [24:0] sectored_entries_0_7_data_hi_hi = {sectored_entries_0_7_data_hi_hi_hi, sectored_entries_0_7_data_hi_hi_lo}; // @[TLB.scala:217:24] wire [30:0] sectored_entries_0_7_data_hi = {sectored_entries_0_7_data_hi_hi, sectored_entries_0_7_data_hi_lo}; // @[TLB.scala:217:24] wire [41:0] _sectored_entries_0_7_data_T = {sectored_entries_0_7_data_hi, sectored_entries_0_7_data_lo}; // @[TLB.scala:217:24] wire [19:0] _entries_T_23; // @[TLB.scala:170:77] wire _entries_T_22; // @[TLB.scala:170:77] wire _entries_T_21; // @[TLB.scala:170:77] wire _entries_T_20; // @[TLB.scala:170:77] wire _entries_T_19; // @[TLB.scala:170:77] wire _entries_T_18; // @[TLB.scala:170:77] wire _entries_T_17; // @[TLB.scala:170:77] wire _entries_T_16; // @[TLB.scala:170:77] wire _entries_T_15; // @[TLB.scala:170:77] wire _entries_T_14; // @[TLB.scala:170:77] wire _entries_T_13; // @[TLB.scala:170:77] wire _entries_T_12; // @[TLB.scala:170:77] wire _entries_T_11; // @[TLB.scala:170:77] wire _entries_T_10; // @[TLB.scala:170:77] wire _entries_T_9; // @[TLB.scala:170:77] wire _entries_T_8; // @[TLB.scala:170:77] wire _entries_T_7; // @[TLB.scala:170:77] wire _entries_T_6; // @[TLB.scala:170:77] wire _entries_T_5; // @[TLB.scala:170:77] wire _entries_T_4; // @[TLB.scala:170:77] wire _entries_T_3; // @[TLB.scala:170:77] wire _entries_T_2; // @[TLB.scala:170:77] wire _entries_T_1; // @[TLB.scala:170:77] wire [3:0][41:0] _GEN_32 = {{sectored_entries_0_0_data_3}, {sectored_entries_0_0_data_2}, {sectored_entries_0_0_data_1}, {sectored_entries_0_0_data_0}}; // @[TLB.scala:170:77, :339:29] wire [41:0] _entries_WIRE_1 = _GEN_32[_entries_T]; // @[package.scala:163:13] assign _entries_T_1 = _entries_WIRE_1[0]; // @[TLB.scala:170:77] wire _entries_WIRE_fragmented_superpage = _entries_T_1; // @[TLB.scala:170:77] assign _entries_T_2 = _entries_WIRE_1[1]; // @[TLB.scala:170:77] wire _entries_WIRE_c = _entries_T_2; // @[TLB.scala:170:77] assign _entries_T_3 = _entries_WIRE_1[2]; // @[TLB.scala:170:77] wire _entries_WIRE_eff = _entries_T_3; // @[TLB.scala:170:77] assign _entries_T_4 = _entries_WIRE_1[3]; // @[TLB.scala:170:77] wire _entries_WIRE_paa = _entries_T_4; // @[TLB.scala:170:77] assign _entries_T_5 = _entries_WIRE_1[4]; // @[TLB.scala:170:77] wire _entries_WIRE_pal = _entries_T_5; // @[TLB.scala:170:77] assign _entries_T_6 = _entries_WIRE_1[5]; // @[TLB.scala:170:77] wire _entries_WIRE_ppp = _entries_T_6; // @[TLB.scala:170:77] assign _entries_T_7 = _entries_WIRE_1[6]; // @[TLB.scala:170:77] wire _entries_WIRE_pr = _entries_T_7; // @[TLB.scala:170:77] assign _entries_T_8 = _entries_WIRE_1[7]; // @[TLB.scala:170:77] wire _entries_WIRE_px = _entries_T_8; // @[TLB.scala:170:77] assign _entries_T_9 = _entries_WIRE_1[8]; // @[TLB.scala:170:77] wire _entries_WIRE_pw = _entries_T_9; // @[TLB.scala:170:77] assign _entries_T_10 = _entries_WIRE_1[9]; // @[TLB.scala:170:77] wire _entries_WIRE_hr = _entries_T_10; // @[TLB.scala:170:77] assign _entries_T_11 = _entries_WIRE_1[10]; // @[TLB.scala:170:77] wire _entries_WIRE_hx = _entries_T_11; // @[TLB.scala:170:77] assign _entries_T_12 = _entries_WIRE_1[11]; // @[TLB.scala:170:77] wire _entries_WIRE_hw = _entries_T_12; // @[TLB.scala:170:77] assign _entries_T_13 = _entries_WIRE_1[12]; // @[TLB.scala:170:77] wire _entries_WIRE_sr = _entries_T_13; // @[TLB.scala:170:77] assign _entries_T_14 = _entries_WIRE_1[13]; // @[TLB.scala:170:77] wire _entries_WIRE_sx = _entries_T_14; // @[TLB.scala:170:77] assign _entries_T_15 = _entries_WIRE_1[14]; // @[TLB.scala:170:77] wire _entries_WIRE_sw = _entries_T_15; // @[TLB.scala:170:77] assign _entries_T_16 = _entries_WIRE_1[15]; // @[TLB.scala:170:77] wire _entries_WIRE_gf = _entries_T_16; // @[TLB.scala:170:77] assign _entries_T_17 = _entries_WIRE_1[16]; // @[TLB.scala:170:77] wire _entries_WIRE_pf = _entries_T_17; // @[TLB.scala:170:77] assign _entries_T_18 = _entries_WIRE_1[17]; // @[TLB.scala:170:77] wire _entries_WIRE_ae_stage2 = _entries_T_18; // @[TLB.scala:170:77] assign _entries_T_19 = _entries_WIRE_1[18]; // @[TLB.scala:170:77] wire _entries_WIRE_ae_final = _entries_T_19; // @[TLB.scala:170:77] assign _entries_T_20 = _entries_WIRE_1[19]; // @[TLB.scala:170:77] wire _entries_WIRE_ae_ptw = _entries_T_20; // @[TLB.scala:170:77] assign _entries_T_21 = _entries_WIRE_1[20]; // @[TLB.scala:170:77] wire _entries_WIRE_g = _entries_T_21; // @[TLB.scala:170:77] assign _entries_T_22 = _entries_WIRE_1[21]; // @[TLB.scala:170:77] wire _entries_WIRE_u = _entries_T_22; // @[TLB.scala:170:77] assign _entries_T_23 = _entries_WIRE_1[41:22]; // @[TLB.scala:170:77] wire [19:0] _entries_WIRE_ppn = _entries_T_23; // @[TLB.scala:170:77] wire [19:0] _entries_T_47; // @[TLB.scala:170:77] wire _entries_T_46; // @[TLB.scala:170:77] wire _entries_T_45; // @[TLB.scala:170:77] wire _entries_T_44; // @[TLB.scala:170:77] wire _entries_T_43; // @[TLB.scala:170:77] wire _entries_T_42; // @[TLB.scala:170:77] wire _entries_T_41; // @[TLB.scala:170:77] wire _entries_T_40; // @[TLB.scala:170:77] wire _entries_T_39; // @[TLB.scala:170:77] wire _entries_T_38; // @[TLB.scala:170:77] wire _entries_T_37; // @[TLB.scala:170:77] wire _entries_T_36; // @[TLB.scala:170:77] wire _entries_T_35; // @[TLB.scala:170:77] wire _entries_T_34; // @[TLB.scala:170:77] wire _entries_T_33; // @[TLB.scala:170:77] wire _entries_T_32; // @[TLB.scala:170:77] wire _entries_T_31; // @[TLB.scala:170:77] wire _entries_T_30; // @[TLB.scala:170:77] wire _entries_T_29; // @[TLB.scala:170:77] wire _entries_T_28; // @[TLB.scala:170:77] wire _entries_T_27; // @[TLB.scala:170:77] wire _entries_T_26; // @[TLB.scala:170:77] wire _entries_T_25; // @[TLB.scala:170:77] wire [3:0][41:0] _GEN_33 = {{sectored_entries_0_1_data_3}, {sectored_entries_0_1_data_2}, {sectored_entries_0_1_data_1}, {sectored_entries_0_1_data_0}}; // @[TLB.scala:170:77, :339:29] wire [41:0] _entries_WIRE_3 = _GEN_33[_entries_T_24]; // @[package.scala:163:13] assign _entries_T_25 = _entries_WIRE_3[0]; // @[TLB.scala:170:77] wire _entries_WIRE_2_fragmented_superpage = _entries_T_25; // @[TLB.scala:170:77] assign _entries_T_26 = _entries_WIRE_3[1]; // @[TLB.scala:170:77] wire _entries_WIRE_2_c = _entries_T_26; // @[TLB.scala:170:77] assign _entries_T_27 = _entries_WIRE_3[2]; // @[TLB.scala:170:77] wire _entries_WIRE_2_eff = _entries_T_27; // @[TLB.scala:170:77] assign _entries_T_28 = _entries_WIRE_3[3]; // @[TLB.scala:170:77] wire _entries_WIRE_2_paa = _entries_T_28; // @[TLB.scala:170:77] assign _entries_T_29 = _entries_WIRE_3[4]; // @[TLB.scala:170:77] wire _entries_WIRE_2_pal = _entries_T_29; // @[TLB.scala:170:77] assign _entries_T_30 = _entries_WIRE_3[5]; // @[TLB.scala:170:77] wire _entries_WIRE_2_ppp = _entries_T_30; // @[TLB.scala:170:77] assign _entries_T_31 = _entries_WIRE_3[6]; // @[TLB.scala:170:77] wire _entries_WIRE_2_pr = _entries_T_31; // @[TLB.scala:170:77] assign _entries_T_32 = _entries_WIRE_3[7]; // @[TLB.scala:170:77] wire _entries_WIRE_2_px = _entries_T_32; // @[TLB.scala:170:77] assign _entries_T_33 = _entries_WIRE_3[8]; // @[TLB.scala:170:77] wire _entries_WIRE_2_pw = _entries_T_33; // @[TLB.scala:170:77] assign _entries_T_34 = _entries_WIRE_3[9]; // @[TLB.scala:170:77] wire _entries_WIRE_2_hr = _entries_T_34; // @[TLB.scala:170:77] assign _entries_T_35 = _entries_WIRE_3[10]; // @[TLB.scala:170:77] wire _entries_WIRE_2_hx = _entries_T_35; // @[TLB.scala:170:77] assign _entries_T_36 = _entries_WIRE_3[11]; // @[TLB.scala:170:77] wire _entries_WIRE_2_hw = _entries_T_36; // @[TLB.scala:170:77] assign _entries_T_37 = _entries_WIRE_3[12]; // @[TLB.scala:170:77] wire _entries_WIRE_2_sr = _entries_T_37; // @[TLB.scala:170:77] assign _entries_T_38 = _entries_WIRE_3[13]; // @[TLB.scala:170:77] wire _entries_WIRE_2_sx = _entries_T_38; // @[TLB.scala:170:77] assign _entries_T_39 = _entries_WIRE_3[14]; // @[TLB.scala:170:77] wire _entries_WIRE_2_sw = _entries_T_39; // @[TLB.scala:170:77] assign _entries_T_40 = _entries_WIRE_3[15]; // @[TLB.scala:170:77] wire _entries_WIRE_2_gf = _entries_T_40; // @[TLB.scala:170:77] assign _entries_T_41 = _entries_WIRE_3[16]; // @[TLB.scala:170:77] wire _entries_WIRE_2_pf = _entries_T_41; // @[TLB.scala:170:77] assign _entries_T_42 = _entries_WIRE_3[17]; // @[TLB.scala:170:77] wire _entries_WIRE_2_ae_stage2 = _entries_T_42; // @[TLB.scala:170:77] assign _entries_T_43 = _entries_WIRE_3[18]; // @[TLB.scala:170:77] wire _entries_WIRE_2_ae_final = _entries_T_43; // @[TLB.scala:170:77] assign _entries_T_44 = _entries_WIRE_3[19]; // @[TLB.scala:170:77] wire _entries_WIRE_2_ae_ptw = _entries_T_44; // @[TLB.scala:170:77] assign _entries_T_45 = _entries_WIRE_3[20]; // @[TLB.scala:170:77] wire _entries_WIRE_2_g = _entries_T_45; // @[TLB.scala:170:77] assign _entries_T_46 = _entries_WIRE_3[21]; // @[TLB.scala:170:77] wire _entries_WIRE_2_u = _entries_T_46; // @[TLB.scala:170:77] assign _entries_T_47 = _entries_WIRE_3[41:22]; // @[TLB.scala:170:77] wire [19:0] _entries_WIRE_2_ppn = _entries_T_47; // @[TLB.scala:170:77] wire [19:0] _entries_T_71; // @[TLB.scala:170:77] wire _entries_T_70; // @[TLB.scala:170:77] wire _entries_T_69; // @[TLB.scala:170:77] wire _entries_T_68; // @[TLB.scala:170:77] wire _entries_T_67; // @[TLB.scala:170:77] wire _entries_T_66; // @[TLB.scala:170:77] wire _entries_T_65; // @[TLB.scala:170:77] wire _entries_T_64; // @[TLB.scala:170:77] wire _entries_T_63; // @[TLB.scala:170:77] wire _entries_T_62; // @[TLB.scala:170:77] wire _entries_T_61; // @[TLB.scala:170:77] wire _entries_T_60; // @[TLB.scala:170:77] wire _entries_T_59; // @[TLB.scala:170:77] wire _entries_T_58; // @[TLB.scala:170:77] wire _entries_T_57; // @[TLB.scala:170:77] wire _entries_T_56; // @[TLB.scala:170:77] wire _entries_T_55; // @[TLB.scala:170:77] wire _entries_T_54; // @[TLB.scala:170:77] wire _entries_T_53; // @[TLB.scala:170:77] wire _entries_T_52; // @[TLB.scala:170:77] wire _entries_T_51; // @[TLB.scala:170:77] wire _entries_T_50; // @[TLB.scala:170:77] wire _entries_T_49; // @[TLB.scala:170:77] wire [3:0][41:0] _GEN_34 = {{sectored_entries_0_2_data_3}, {sectored_entries_0_2_data_2}, {sectored_entries_0_2_data_1}, {sectored_entries_0_2_data_0}}; // @[TLB.scala:170:77, :339:29] wire [41:0] _entries_WIRE_5 = _GEN_34[_entries_T_48]; // @[package.scala:163:13] assign _entries_T_49 = _entries_WIRE_5[0]; // @[TLB.scala:170:77] wire _entries_WIRE_4_fragmented_superpage = _entries_T_49; // @[TLB.scala:170:77] assign _entries_T_50 = _entries_WIRE_5[1]; // @[TLB.scala:170:77] wire _entries_WIRE_4_c = _entries_T_50; // @[TLB.scala:170:77] assign _entries_T_51 = _entries_WIRE_5[2]; // @[TLB.scala:170:77] wire _entries_WIRE_4_eff = _entries_T_51; // @[TLB.scala:170:77] assign _entries_T_52 = _entries_WIRE_5[3]; // @[TLB.scala:170:77] wire _entries_WIRE_4_paa = _entries_T_52; // @[TLB.scala:170:77] assign _entries_T_53 = _entries_WIRE_5[4]; // @[TLB.scala:170:77] wire _entries_WIRE_4_pal = _entries_T_53; // @[TLB.scala:170:77] assign _entries_T_54 = _entries_WIRE_5[5]; // @[TLB.scala:170:77] wire _entries_WIRE_4_ppp = _entries_T_54; // @[TLB.scala:170:77] assign _entries_T_55 = _entries_WIRE_5[6]; // @[TLB.scala:170:77] wire _entries_WIRE_4_pr = _entries_T_55; // @[TLB.scala:170:77] assign _entries_T_56 = _entries_WIRE_5[7]; // @[TLB.scala:170:77] wire _entries_WIRE_4_px = _entries_T_56; // @[TLB.scala:170:77] assign _entries_T_57 = _entries_WIRE_5[8]; // @[TLB.scala:170:77] wire _entries_WIRE_4_pw = _entries_T_57; // @[TLB.scala:170:77] assign _entries_T_58 = _entries_WIRE_5[9]; // @[TLB.scala:170:77] wire _entries_WIRE_4_hr = _entries_T_58; // @[TLB.scala:170:77] assign _entries_T_59 = _entries_WIRE_5[10]; // @[TLB.scala:170:77] wire _entries_WIRE_4_hx = _entries_T_59; // @[TLB.scala:170:77] assign _entries_T_60 = _entries_WIRE_5[11]; // @[TLB.scala:170:77] wire _entries_WIRE_4_hw = _entries_T_60; // @[TLB.scala:170:77] assign _entries_T_61 = _entries_WIRE_5[12]; // @[TLB.scala:170:77] wire _entries_WIRE_4_sr = _entries_T_61; // @[TLB.scala:170:77] assign _entries_T_62 = _entries_WIRE_5[13]; // @[TLB.scala:170:77] wire _entries_WIRE_4_sx = _entries_T_62; // @[TLB.scala:170:77] assign _entries_T_63 = _entries_WIRE_5[14]; // @[TLB.scala:170:77] wire _entries_WIRE_4_sw = _entries_T_63; // @[TLB.scala:170:77] assign _entries_T_64 = _entries_WIRE_5[15]; // @[TLB.scala:170:77] wire _entries_WIRE_4_gf = _entries_T_64; // @[TLB.scala:170:77] assign _entries_T_65 = _entries_WIRE_5[16]; // @[TLB.scala:170:77] wire _entries_WIRE_4_pf = _entries_T_65; // @[TLB.scala:170:77] assign _entries_T_66 = _entries_WIRE_5[17]; // @[TLB.scala:170:77] wire _entries_WIRE_4_ae_stage2 = _entries_T_66; // @[TLB.scala:170:77] assign _entries_T_67 = _entries_WIRE_5[18]; // @[TLB.scala:170:77] wire _entries_WIRE_4_ae_final = _entries_T_67; // @[TLB.scala:170:77] assign _entries_T_68 = _entries_WIRE_5[19]; // @[TLB.scala:170:77] wire _entries_WIRE_4_ae_ptw = _entries_T_68; // @[TLB.scala:170:77] assign _entries_T_69 = _entries_WIRE_5[20]; // @[TLB.scala:170:77] wire _entries_WIRE_4_g = _entries_T_69; // @[TLB.scala:170:77] assign _entries_T_70 = _entries_WIRE_5[21]; // @[TLB.scala:170:77] wire _entries_WIRE_4_u = _entries_T_70; // @[TLB.scala:170:77] assign _entries_T_71 = _entries_WIRE_5[41:22]; // @[TLB.scala:170:77] wire [19:0] _entries_WIRE_4_ppn = _entries_T_71; // @[TLB.scala:170:77] wire [19:0] _entries_T_95; // @[TLB.scala:170:77] wire _entries_T_94; // @[TLB.scala:170:77] wire _entries_T_93; // @[TLB.scala:170:77] wire _entries_T_92; // @[TLB.scala:170:77] wire _entries_T_91; // @[TLB.scala:170:77] wire _entries_T_90; // @[TLB.scala:170:77] wire _entries_T_89; // @[TLB.scala:170:77] wire _entries_T_88; // @[TLB.scala:170:77] wire _entries_T_87; // @[TLB.scala:170:77] wire _entries_T_86; // @[TLB.scala:170:77] wire _entries_T_85; // @[TLB.scala:170:77] wire _entries_T_84; // @[TLB.scala:170:77] wire _entries_T_83; // @[TLB.scala:170:77] wire _entries_T_82; // @[TLB.scala:170:77] wire _entries_T_81; // @[TLB.scala:170:77] wire _entries_T_80; // @[TLB.scala:170:77] wire _entries_T_79; // @[TLB.scala:170:77] wire _entries_T_78; // @[TLB.scala:170:77] wire _entries_T_77; // @[TLB.scala:170:77] wire _entries_T_76; // @[TLB.scala:170:77] wire _entries_T_75; // @[TLB.scala:170:77] wire _entries_T_74; // @[TLB.scala:170:77] wire _entries_T_73; // @[TLB.scala:170:77] wire [3:0][41:0] _GEN_35 = {{sectored_entries_0_3_data_3}, {sectored_entries_0_3_data_2}, {sectored_entries_0_3_data_1}, {sectored_entries_0_3_data_0}}; // @[TLB.scala:170:77, :339:29] wire [41:0] _entries_WIRE_7 = _GEN_35[_entries_T_72]; // @[package.scala:163:13] assign _entries_T_73 = _entries_WIRE_7[0]; // @[TLB.scala:170:77] wire _entries_WIRE_6_fragmented_superpage = _entries_T_73; // @[TLB.scala:170:77] assign _entries_T_74 = _entries_WIRE_7[1]; // @[TLB.scala:170:77] wire _entries_WIRE_6_c = _entries_T_74; // @[TLB.scala:170:77] assign _entries_T_75 = _entries_WIRE_7[2]; // @[TLB.scala:170:77] wire _entries_WIRE_6_eff = _entries_T_75; // @[TLB.scala:170:77] assign _entries_T_76 = _entries_WIRE_7[3]; // @[TLB.scala:170:77] wire _entries_WIRE_6_paa = _entries_T_76; // @[TLB.scala:170:77] assign _entries_T_77 = _entries_WIRE_7[4]; // @[TLB.scala:170:77] wire _entries_WIRE_6_pal = _entries_T_77; // @[TLB.scala:170:77] assign _entries_T_78 = _entries_WIRE_7[5]; // @[TLB.scala:170:77] wire _entries_WIRE_6_ppp = _entries_T_78; // @[TLB.scala:170:77] assign _entries_T_79 = _entries_WIRE_7[6]; // @[TLB.scala:170:77] wire _entries_WIRE_6_pr = _entries_T_79; // @[TLB.scala:170:77] assign _entries_T_80 = _entries_WIRE_7[7]; // @[TLB.scala:170:77] wire _entries_WIRE_6_px = _entries_T_80; // @[TLB.scala:170:77] assign _entries_T_81 = _entries_WIRE_7[8]; // @[TLB.scala:170:77] wire _entries_WIRE_6_pw = _entries_T_81; // @[TLB.scala:170:77] assign _entries_T_82 = _entries_WIRE_7[9]; // @[TLB.scala:170:77] wire _entries_WIRE_6_hr = _entries_T_82; // @[TLB.scala:170:77] assign _entries_T_83 = _entries_WIRE_7[10]; // @[TLB.scala:170:77] wire _entries_WIRE_6_hx = _entries_T_83; // @[TLB.scala:170:77] assign _entries_T_84 = _entries_WIRE_7[11]; // @[TLB.scala:170:77] wire _entries_WIRE_6_hw = _entries_T_84; // @[TLB.scala:170:77] assign _entries_T_85 = _entries_WIRE_7[12]; // @[TLB.scala:170:77] wire _entries_WIRE_6_sr = _entries_T_85; // @[TLB.scala:170:77] assign _entries_T_86 = _entries_WIRE_7[13]; // @[TLB.scala:170:77] wire _entries_WIRE_6_sx = _entries_T_86; // @[TLB.scala:170:77] assign _entries_T_87 = _entries_WIRE_7[14]; // @[TLB.scala:170:77] wire _entries_WIRE_6_sw = _entries_T_87; // @[TLB.scala:170:77] assign _entries_T_88 = _entries_WIRE_7[15]; // @[TLB.scala:170:77] wire _entries_WIRE_6_gf = _entries_T_88; // @[TLB.scala:170:77] assign _entries_T_89 = _entries_WIRE_7[16]; // @[TLB.scala:170:77] wire _entries_WIRE_6_pf = _entries_T_89; // @[TLB.scala:170:77] assign _entries_T_90 = _entries_WIRE_7[17]; // @[TLB.scala:170:77] wire _entries_WIRE_6_ae_stage2 = _entries_T_90; // @[TLB.scala:170:77] assign _entries_T_91 = _entries_WIRE_7[18]; // @[TLB.scala:170:77] wire _entries_WIRE_6_ae_final = _entries_T_91; // @[TLB.scala:170:77] assign _entries_T_92 = _entries_WIRE_7[19]; // @[TLB.scala:170:77] wire _entries_WIRE_6_ae_ptw = _entries_T_92; // @[TLB.scala:170:77] assign _entries_T_93 = _entries_WIRE_7[20]; // @[TLB.scala:170:77] wire _entries_WIRE_6_g = _entries_T_93; // @[TLB.scala:170:77] assign _entries_T_94 = _entries_WIRE_7[21]; // @[TLB.scala:170:77] wire _entries_WIRE_6_u = _entries_T_94; // @[TLB.scala:170:77] assign _entries_T_95 = _entries_WIRE_7[41:22]; // @[TLB.scala:170:77] wire [19:0] _entries_WIRE_6_ppn = _entries_T_95; // @[TLB.scala:170:77] wire [19:0] _entries_T_119; // @[TLB.scala:170:77] wire _entries_T_118; // @[TLB.scala:170:77] wire _entries_T_117; // @[TLB.scala:170:77] wire _entries_T_116; // @[TLB.scala:170:77] wire _entries_T_115; // @[TLB.scala:170:77] wire _entries_T_114; // @[TLB.scala:170:77] wire _entries_T_113; // @[TLB.scala:170:77] wire _entries_T_112; // @[TLB.scala:170:77] wire _entries_T_111; // @[TLB.scala:170:77] wire _entries_T_110; // @[TLB.scala:170:77] wire _entries_T_109; // @[TLB.scala:170:77] wire _entries_T_108; // @[TLB.scala:170:77] wire _entries_T_107; // @[TLB.scala:170:77] wire _entries_T_106; // @[TLB.scala:170:77] wire _entries_T_105; // @[TLB.scala:170:77] wire _entries_T_104; // @[TLB.scala:170:77] wire _entries_T_103; // @[TLB.scala:170:77] wire _entries_T_102; // @[TLB.scala:170:77] wire _entries_T_101; // @[TLB.scala:170:77] wire _entries_T_100; // @[TLB.scala:170:77] wire _entries_T_99; // @[TLB.scala:170:77] wire _entries_T_98; // @[TLB.scala:170:77] wire _entries_T_97; // @[TLB.scala:170:77] wire [3:0][41:0] _GEN_36 = {{sectored_entries_0_4_data_3}, {sectored_entries_0_4_data_2}, {sectored_entries_0_4_data_1}, {sectored_entries_0_4_data_0}}; // @[TLB.scala:170:77, :339:29] wire [41:0] _entries_WIRE_9 = _GEN_36[_entries_T_96]; // @[package.scala:163:13] assign _entries_T_97 = _entries_WIRE_9[0]; // @[TLB.scala:170:77] wire _entries_WIRE_8_fragmented_superpage = _entries_T_97; // @[TLB.scala:170:77] assign _entries_T_98 = _entries_WIRE_9[1]; // @[TLB.scala:170:77] wire _entries_WIRE_8_c = _entries_T_98; // @[TLB.scala:170:77] assign _entries_T_99 = _entries_WIRE_9[2]; // @[TLB.scala:170:77] wire _entries_WIRE_8_eff = _entries_T_99; // @[TLB.scala:170:77] assign _entries_T_100 = _entries_WIRE_9[3]; // @[TLB.scala:170:77] wire _entries_WIRE_8_paa = _entries_T_100; // @[TLB.scala:170:77] assign _entries_T_101 = _entries_WIRE_9[4]; // @[TLB.scala:170:77] wire _entries_WIRE_8_pal = _entries_T_101; // @[TLB.scala:170:77] assign _entries_T_102 = _entries_WIRE_9[5]; // @[TLB.scala:170:77] wire _entries_WIRE_8_ppp = _entries_T_102; // @[TLB.scala:170:77] assign _entries_T_103 = _entries_WIRE_9[6]; // @[TLB.scala:170:77] wire _entries_WIRE_8_pr = _entries_T_103; // @[TLB.scala:170:77] assign _entries_T_104 = _entries_WIRE_9[7]; // @[TLB.scala:170:77] wire _entries_WIRE_8_px = _entries_T_104; // @[TLB.scala:170:77] assign _entries_T_105 = _entries_WIRE_9[8]; // @[TLB.scala:170:77] wire _entries_WIRE_8_pw = _entries_T_105; // @[TLB.scala:170:77] assign _entries_T_106 = _entries_WIRE_9[9]; // @[TLB.scala:170:77] wire _entries_WIRE_8_hr = _entries_T_106; // @[TLB.scala:170:77] assign _entries_T_107 = _entries_WIRE_9[10]; // @[TLB.scala:170:77] wire _entries_WIRE_8_hx = _entries_T_107; // @[TLB.scala:170:77] assign _entries_T_108 = _entries_WIRE_9[11]; // @[TLB.scala:170:77] wire _entries_WIRE_8_hw = _entries_T_108; // @[TLB.scala:170:77] assign _entries_T_109 = _entries_WIRE_9[12]; // @[TLB.scala:170:77] wire _entries_WIRE_8_sr = _entries_T_109; // @[TLB.scala:170:77] assign _entries_T_110 = _entries_WIRE_9[13]; // @[TLB.scala:170:77] wire _entries_WIRE_8_sx = _entries_T_110; // @[TLB.scala:170:77] assign _entries_T_111 = _entries_WIRE_9[14]; // @[TLB.scala:170:77] wire _entries_WIRE_8_sw = _entries_T_111; // @[TLB.scala:170:77] assign _entries_T_112 = _entries_WIRE_9[15]; // @[TLB.scala:170:77] wire _entries_WIRE_8_gf = _entries_T_112; // @[TLB.scala:170:77] assign _entries_T_113 = _entries_WIRE_9[16]; // @[TLB.scala:170:77] wire _entries_WIRE_8_pf = _entries_T_113; // @[TLB.scala:170:77] assign _entries_T_114 = _entries_WIRE_9[17]; // @[TLB.scala:170:77] wire _entries_WIRE_8_ae_stage2 = _entries_T_114; // @[TLB.scala:170:77] assign _entries_T_115 = _entries_WIRE_9[18]; // @[TLB.scala:170:77] wire _entries_WIRE_8_ae_final = _entries_T_115; // @[TLB.scala:170:77] assign _entries_T_116 = _entries_WIRE_9[19]; // @[TLB.scala:170:77] wire _entries_WIRE_8_ae_ptw = _entries_T_116; // @[TLB.scala:170:77] assign _entries_T_117 = _entries_WIRE_9[20]; // @[TLB.scala:170:77] wire _entries_WIRE_8_g = _entries_T_117; // @[TLB.scala:170:77] assign _entries_T_118 = _entries_WIRE_9[21]; // @[TLB.scala:170:77] wire _entries_WIRE_8_u = _entries_T_118; // @[TLB.scala:170:77] assign _entries_T_119 = _entries_WIRE_9[41:22]; // @[TLB.scala:170:77] wire [19:0] _entries_WIRE_8_ppn = _entries_T_119; // @[TLB.scala:170:77] wire [19:0] _entries_T_143; // @[TLB.scala:170:77] wire _entries_T_142; // @[TLB.scala:170:77] wire _entries_T_141; // @[TLB.scala:170:77] wire _entries_T_140; // @[TLB.scala:170:77] wire _entries_T_139; // @[TLB.scala:170:77] wire _entries_T_138; // @[TLB.scala:170:77] wire _entries_T_137; // @[TLB.scala:170:77] wire _entries_T_136; // @[TLB.scala:170:77] wire _entries_T_135; // @[TLB.scala:170:77] wire _entries_T_134; // @[TLB.scala:170:77] wire _entries_T_133; // @[TLB.scala:170:77] wire _entries_T_132; // @[TLB.scala:170:77] wire _entries_T_131; // @[TLB.scala:170:77] wire _entries_T_130; // @[TLB.scala:170:77] wire _entries_T_129; // @[TLB.scala:170:77] wire _entries_T_128; // @[TLB.scala:170:77] wire _entries_T_127; // @[TLB.scala:170:77] wire _entries_T_126; // @[TLB.scala:170:77] wire _entries_T_125; // @[TLB.scala:170:77] wire _entries_T_124; // @[TLB.scala:170:77] wire _entries_T_123; // @[TLB.scala:170:77] wire _entries_T_122; // @[TLB.scala:170:77] wire _entries_T_121; // @[TLB.scala:170:77] wire [3:0][41:0] _GEN_37 = {{sectored_entries_0_5_data_3}, {sectored_entries_0_5_data_2}, {sectored_entries_0_5_data_1}, {sectored_entries_0_5_data_0}}; // @[TLB.scala:170:77, :339:29] wire [41:0] _entries_WIRE_11 = _GEN_37[_entries_T_120]; // @[package.scala:163:13] assign _entries_T_121 = _entries_WIRE_11[0]; // @[TLB.scala:170:77] wire _entries_WIRE_10_fragmented_superpage = _entries_T_121; // @[TLB.scala:170:77] assign _entries_T_122 = _entries_WIRE_11[1]; // @[TLB.scala:170:77] wire _entries_WIRE_10_c = _entries_T_122; // @[TLB.scala:170:77] assign _entries_T_123 = _entries_WIRE_11[2]; // @[TLB.scala:170:77] wire _entries_WIRE_10_eff = _entries_T_123; // @[TLB.scala:170:77] assign _entries_T_124 = _entries_WIRE_11[3]; // @[TLB.scala:170:77] wire _entries_WIRE_10_paa = _entries_T_124; // @[TLB.scala:170:77] assign _entries_T_125 = _entries_WIRE_11[4]; // @[TLB.scala:170:77] wire _entries_WIRE_10_pal = _entries_T_125; // @[TLB.scala:170:77] assign _entries_T_126 = _entries_WIRE_11[5]; // @[TLB.scala:170:77] wire _entries_WIRE_10_ppp = _entries_T_126; // @[TLB.scala:170:77] assign _entries_T_127 = _entries_WIRE_11[6]; // @[TLB.scala:170:77] wire _entries_WIRE_10_pr = _entries_T_127; // @[TLB.scala:170:77] assign _entries_T_128 = _entries_WIRE_11[7]; // @[TLB.scala:170:77] wire _entries_WIRE_10_px = _entries_T_128; // @[TLB.scala:170:77] assign _entries_T_129 = _entries_WIRE_11[8]; // @[TLB.scala:170:77] wire _entries_WIRE_10_pw = _entries_T_129; // @[TLB.scala:170:77] assign _entries_T_130 = _entries_WIRE_11[9]; // @[TLB.scala:170:77] wire _entries_WIRE_10_hr = _entries_T_130; // @[TLB.scala:170:77] assign _entries_T_131 = _entries_WIRE_11[10]; // @[TLB.scala:170:77] wire _entries_WIRE_10_hx = _entries_T_131; // @[TLB.scala:170:77] assign _entries_T_132 = _entries_WIRE_11[11]; // @[TLB.scala:170:77] wire _entries_WIRE_10_hw = _entries_T_132; // @[TLB.scala:170:77] assign _entries_T_133 = _entries_WIRE_11[12]; // @[TLB.scala:170:77] wire _entries_WIRE_10_sr = _entries_T_133; // @[TLB.scala:170:77] assign _entries_T_134 = _entries_WIRE_11[13]; // @[TLB.scala:170:77] wire _entries_WIRE_10_sx = _entries_T_134; // @[TLB.scala:170:77] assign _entries_T_135 = _entries_WIRE_11[14]; // @[TLB.scala:170:77] wire _entries_WIRE_10_sw = _entries_T_135; // @[TLB.scala:170:77] assign _entries_T_136 = _entries_WIRE_11[15]; // @[TLB.scala:170:77] wire _entries_WIRE_10_gf = _entries_T_136; // @[TLB.scala:170:77] assign _entries_T_137 = _entries_WIRE_11[16]; // @[TLB.scala:170:77] wire _entries_WIRE_10_pf = _entries_T_137; // @[TLB.scala:170:77] assign _entries_T_138 = _entries_WIRE_11[17]; // @[TLB.scala:170:77] wire _entries_WIRE_10_ae_stage2 = _entries_T_138; // @[TLB.scala:170:77] assign _entries_T_139 = _entries_WIRE_11[18]; // @[TLB.scala:170:77] wire _entries_WIRE_10_ae_final = _entries_T_139; // @[TLB.scala:170:77] assign _entries_T_140 = _entries_WIRE_11[19]; // @[TLB.scala:170:77] wire _entries_WIRE_10_ae_ptw = _entries_T_140; // @[TLB.scala:170:77] assign _entries_T_141 = _entries_WIRE_11[20]; // @[TLB.scala:170:77] wire _entries_WIRE_10_g = _entries_T_141; // @[TLB.scala:170:77] assign _entries_T_142 = _entries_WIRE_11[21]; // @[TLB.scala:170:77] wire _entries_WIRE_10_u = _entries_T_142; // @[TLB.scala:170:77] assign _entries_T_143 = _entries_WIRE_11[41:22]; // @[TLB.scala:170:77] wire [19:0] _entries_WIRE_10_ppn = _entries_T_143; // @[TLB.scala:170:77] wire [19:0] _entries_T_167; // @[TLB.scala:170:77] wire _entries_T_166; // @[TLB.scala:170:77] wire _entries_T_165; // @[TLB.scala:170:77] wire _entries_T_164; // @[TLB.scala:170:77] wire _entries_T_163; // @[TLB.scala:170:77] wire _entries_T_162; // @[TLB.scala:170:77] wire _entries_T_161; // @[TLB.scala:170:77] wire _entries_T_160; // @[TLB.scala:170:77] wire _entries_T_159; // @[TLB.scala:170:77] wire _entries_T_158; // @[TLB.scala:170:77] wire _entries_T_157; // @[TLB.scala:170:77] wire _entries_T_156; // @[TLB.scala:170:77] wire _entries_T_155; // @[TLB.scala:170:77] wire _entries_T_154; // @[TLB.scala:170:77] wire _entries_T_153; // @[TLB.scala:170:77] wire _entries_T_152; // @[TLB.scala:170:77] wire _entries_T_151; // @[TLB.scala:170:77] wire _entries_T_150; // @[TLB.scala:170:77] wire _entries_T_149; // @[TLB.scala:170:77] wire _entries_T_148; // @[TLB.scala:170:77] wire _entries_T_147; // @[TLB.scala:170:77] wire _entries_T_146; // @[TLB.scala:170:77] wire _entries_T_145; // @[TLB.scala:170:77] wire [3:0][41:0] _GEN_38 = {{sectored_entries_0_6_data_3}, {sectored_entries_0_6_data_2}, {sectored_entries_0_6_data_1}, {sectored_entries_0_6_data_0}}; // @[TLB.scala:170:77, :339:29] wire [41:0] _entries_WIRE_13 = _GEN_38[_entries_T_144]; // @[package.scala:163:13] assign _entries_T_145 = _entries_WIRE_13[0]; // @[TLB.scala:170:77] wire _entries_WIRE_12_fragmented_superpage = _entries_T_145; // @[TLB.scala:170:77] assign _entries_T_146 = _entries_WIRE_13[1]; // @[TLB.scala:170:77] wire _entries_WIRE_12_c = _entries_T_146; // @[TLB.scala:170:77] assign _entries_T_147 = _entries_WIRE_13[2]; // @[TLB.scala:170:77] wire _entries_WIRE_12_eff = _entries_T_147; // @[TLB.scala:170:77] assign _entries_T_148 = _entries_WIRE_13[3]; // @[TLB.scala:170:77] wire _entries_WIRE_12_paa = _entries_T_148; // @[TLB.scala:170:77] assign _entries_T_149 = _entries_WIRE_13[4]; // @[TLB.scala:170:77] wire _entries_WIRE_12_pal = _entries_T_149; // @[TLB.scala:170:77] assign _entries_T_150 = _entries_WIRE_13[5]; // @[TLB.scala:170:77] wire _entries_WIRE_12_ppp = _entries_T_150; // @[TLB.scala:170:77] assign _entries_T_151 = _entries_WIRE_13[6]; // @[TLB.scala:170:77] wire _entries_WIRE_12_pr = _entries_T_151; // @[TLB.scala:170:77] assign _entries_T_152 = _entries_WIRE_13[7]; // @[TLB.scala:170:77] wire _entries_WIRE_12_px = _entries_T_152; // @[TLB.scala:170:77] assign _entries_T_153 = _entries_WIRE_13[8]; // @[TLB.scala:170:77] wire _entries_WIRE_12_pw = _entries_T_153; // @[TLB.scala:170:77] assign _entries_T_154 = _entries_WIRE_13[9]; // @[TLB.scala:170:77] wire _entries_WIRE_12_hr = _entries_T_154; // @[TLB.scala:170:77] assign _entries_T_155 = _entries_WIRE_13[10]; // @[TLB.scala:170:77] wire _entries_WIRE_12_hx = _entries_T_155; // @[TLB.scala:170:77] assign _entries_T_156 = _entries_WIRE_13[11]; // @[TLB.scala:170:77] wire _entries_WIRE_12_hw = _entries_T_156; // @[TLB.scala:170:77] assign _entries_T_157 = _entries_WIRE_13[12]; // @[TLB.scala:170:77] wire _entries_WIRE_12_sr = _entries_T_157; // @[TLB.scala:170:77] assign _entries_T_158 = _entries_WIRE_13[13]; // @[TLB.scala:170:77] wire _entries_WIRE_12_sx = _entries_T_158; // @[TLB.scala:170:77] assign _entries_T_159 = _entries_WIRE_13[14]; // @[TLB.scala:170:77] wire _entries_WIRE_12_sw = _entries_T_159; // @[TLB.scala:170:77] assign _entries_T_160 = _entries_WIRE_13[15]; // @[TLB.scala:170:77] wire _entries_WIRE_12_gf = _entries_T_160; // @[TLB.scala:170:77] assign _entries_T_161 = _entries_WIRE_13[16]; // @[TLB.scala:170:77] wire _entries_WIRE_12_pf = _entries_T_161; // @[TLB.scala:170:77] assign _entries_T_162 = _entries_WIRE_13[17]; // @[TLB.scala:170:77] wire _entries_WIRE_12_ae_stage2 = _entries_T_162; // @[TLB.scala:170:77] assign _entries_T_163 = _entries_WIRE_13[18]; // @[TLB.scala:170:77] wire _entries_WIRE_12_ae_final = _entries_T_163; // @[TLB.scala:170:77] assign _entries_T_164 = _entries_WIRE_13[19]; // @[TLB.scala:170:77] wire _entries_WIRE_12_ae_ptw = _entries_T_164; // @[TLB.scala:170:77] assign _entries_T_165 = _entries_WIRE_13[20]; // @[TLB.scala:170:77] wire _entries_WIRE_12_g = _entries_T_165; // @[TLB.scala:170:77] assign _entries_T_166 = _entries_WIRE_13[21]; // @[TLB.scala:170:77] wire _entries_WIRE_12_u = _entries_T_166; // @[TLB.scala:170:77] assign _entries_T_167 = _entries_WIRE_13[41:22]; // @[TLB.scala:170:77] wire [19:0] _entries_WIRE_12_ppn = _entries_T_167; // @[TLB.scala:170:77] wire [19:0] _entries_T_191; // @[TLB.scala:170:77] wire _entries_T_190; // @[TLB.scala:170:77] wire _entries_T_189; // @[TLB.scala:170:77] wire _entries_T_188; // @[TLB.scala:170:77] wire _entries_T_187; // @[TLB.scala:170:77] wire _entries_T_186; // @[TLB.scala:170:77] wire _entries_T_185; // @[TLB.scala:170:77] wire _entries_T_184; // @[TLB.scala:170:77] wire _entries_T_183; // @[TLB.scala:170:77] wire _entries_T_182; // @[TLB.scala:170:77] wire _entries_T_181; // @[TLB.scala:170:77] wire _entries_T_180; // @[TLB.scala:170:77] wire _entries_T_179; // @[TLB.scala:170:77] wire _entries_T_178; // @[TLB.scala:170:77] wire _entries_T_177; // @[TLB.scala:170:77] wire _entries_T_176; // @[TLB.scala:170:77] wire _entries_T_175; // @[TLB.scala:170:77] wire _entries_T_174; // @[TLB.scala:170:77] wire _entries_T_173; // @[TLB.scala:170:77] wire _entries_T_172; // @[TLB.scala:170:77] wire _entries_T_171; // @[TLB.scala:170:77] wire _entries_T_170; // @[TLB.scala:170:77] wire _entries_T_169; // @[TLB.scala:170:77] wire [3:0][41:0] _GEN_39 = {{sectored_entries_0_7_data_3}, {sectored_entries_0_7_data_2}, {sectored_entries_0_7_data_1}, {sectored_entries_0_7_data_0}}; // @[TLB.scala:170:77, :339:29] wire [41:0] _entries_WIRE_15 = _GEN_39[_entries_T_168]; // @[package.scala:163:13] assign _entries_T_169 = _entries_WIRE_15[0]; // @[TLB.scala:170:77] wire _entries_WIRE_14_fragmented_superpage = _entries_T_169; // @[TLB.scala:170:77] assign _entries_T_170 = _entries_WIRE_15[1]; // @[TLB.scala:170:77] wire _entries_WIRE_14_c = _entries_T_170; // @[TLB.scala:170:77] assign _entries_T_171 = _entries_WIRE_15[2]; // @[TLB.scala:170:77] wire _entries_WIRE_14_eff = _entries_T_171; // @[TLB.scala:170:77] assign _entries_T_172 = _entries_WIRE_15[3]; // @[TLB.scala:170:77] wire _entries_WIRE_14_paa = _entries_T_172; // @[TLB.scala:170:77] assign _entries_T_173 = _entries_WIRE_15[4]; // @[TLB.scala:170:77] wire _entries_WIRE_14_pal = _entries_T_173; // @[TLB.scala:170:77] assign _entries_T_174 = _entries_WIRE_15[5]; // @[TLB.scala:170:77] wire _entries_WIRE_14_ppp = _entries_T_174; // @[TLB.scala:170:77] assign _entries_T_175 = _entries_WIRE_15[6]; // @[TLB.scala:170:77] wire _entries_WIRE_14_pr = _entries_T_175; // @[TLB.scala:170:77] assign _entries_T_176 = _entries_WIRE_15[7]; // @[TLB.scala:170:77] wire _entries_WIRE_14_px = _entries_T_176; // @[TLB.scala:170:77] assign _entries_T_177 = _entries_WIRE_15[8]; // @[TLB.scala:170:77] wire _entries_WIRE_14_pw = _entries_T_177; // @[TLB.scala:170:77] assign _entries_T_178 = _entries_WIRE_15[9]; // @[TLB.scala:170:77] wire _entries_WIRE_14_hr = _entries_T_178; // @[TLB.scala:170:77] assign _entries_T_179 = _entries_WIRE_15[10]; // @[TLB.scala:170:77] wire _entries_WIRE_14_hx = _entries_T_179; // @[TLB.scala:170:77] assign _entries_T_180 = _entries_WIRE_15[11]; // @[TLB.scala:170:77] wire _entries_WIRE_14_hw = _entries_T_180; // @[TLB.scala:170:77] assign _entries_T_181 = _entries_WIRE_15[12]; // @[TLB.scala:170:77] wire _entries_WIRE_14_sr = _entries_T_181; // @[TLB.scala:170:77] assign _entries_T_182 = _entries_WIRE_15[13]; // @[TLB.scala:170:77] wire _entries_WIRE_14_sx = _entries_T_182; // @[TLB.scala:170:77] assign _entries_T_183 = _entries_WIRE_15[14]; // @[TLB.scala:170:77] wire _entries_WIRE_14_sw = _entries_T_183; // @[TLB.scala:170:77] assign _entries_T_184 = _entries_WIRE_15[15]; // @[TLB.scala:170:77] wire _entries_WIRE_14_gf = _entries_T_184; // @[TLB.scala:170:77] assign _entries_T_185 = _entries_WIRE_15[16]; // @[TLB.scala:170:77] wire _entries_WIRE_14_pf = _entries_T_185; // @[TLB.scala:170:77] assign _entries_T_186 = _entries_WIRE_15[17]; // @[TLB.scala:170:77] wire _entries_WIRE_14_ae_stage2 = _entries_T_186; // @[TLB.scala:170:77] assign _entries_T_187 = _entries_WIRE_15[18]; // @[TLB.scala:170:77] wire _entries_WIRE_14_ae_final = _entries_T_187; // @[TLB.scala:170:77] assign _entries_T_188 = _entries_WIRE_15[19]; // @[TLB.scala:170:77] wire _entries_WIRE_14_ae_ptw = _entries_T_188; // @[TLB.scala:170:77] assign _entries_T_189 = _entries_WIRE_15[20]; // @[TLB.scala:170:77] wire _entries_WIRE_14_g = _entries_T_189; // @[TLB.scala:170:77] assign _entries_T_190 = _entries_WIRE_15[21]; // @[TLB.scala:170:77] wire _entries_WIRE_14_u = _entries_T_190; // @[TLB.scala:170:77] assign _entries_T_191 = _entries_WIRE_15[41:22]; // @[TLB.scala:170:77] wire [19:0] _entries_WIRE_14_ppn = _entries_T_191; // @[TLB.scala:170:77] wire [19:0] _entries_T_214; // @[TLB.scala:170:77] wire _entries_T_213; // @[TLB.scala:170:77] wire _entries_T_212; // @[TLB.scala:170:77] wire _entries_T_211; // @[TLB.scala:170:77] wire _entries_T_210; // @[TLB.scala:170:77] wire _entries_T_209; // @[TLB.scala:170:77] wire _entries_T_208; // @[TLB.scala:170:77] wire _entries_T_207; // @[TLB.scala:170:77] wire _entries_T_206; // @[TLB.scala:170:77] wire _entries_T_205; // @[TLB.scala:170:77] wire _entries_T_204; // @[TLB.scala:170:77] wire _entries_T_203; // @[TLB.scala:170:77] wire _entries_T_202; // @[TLB.scala:170:77] wire _entries_T_201; // @[TLB.scala:170:77] wire _entries_T_200; // @[TLB.scala:170:77] wire _entries_T_199; // @[TLB.scala:170:77] wire _entries_T_198; // @[TLB.scala:170:77] wire _entries_T_197; // @[TLB.scala:170:77] wire _entries_T_196; // @[TLB.scala:170:77] wire _entries_T_195; // @[TLB.scala:170:77] wire _entries_T_194; // @[TLB.scala:170:77] wire _entries_T_193; // @[TLB.scala:170:77] wire _entries_T_192; // @[TLB.scala:170:77] assign _entries_T_192 = _entries_WIRE_17[0]; // @[TLB.scala:170:77] wire _entries_WIRE_16_fragmented_superpage = _entries_T_192; // @[TLB.scala:170:77] assign _entries_T_193 = _entries_WIRE_17[1]; // @[TLB.scala:170:77] wire _entries_WIRE_16_c = _entries_T_193; // @[TLB.scala:170:77] assign _entries_T_194 = _entries_WIRE_17[2]; // @[TLB.scala:170:77] wire _entries_WIRE_16_eff = _entries_T_194; // @[TLB.scala:170:77] assign _entries_T_195 = _entries_WIRE_17[3]; // @[TLB.scala:170:77] wire _entries_WIRE_16_paa = _entries_T_195; // @[TLB.scala:170:77] assign _entries_T_196 = _entries_WIRE_17[4]; // @[TLB.scala:170:77] wire _entries_WIRE_16_pal = _entries_T_196; // @[TLB.scala:170:77] assign _entries_T_197 = _entries_WIRE_17[5]; // @[TLB.scala:170:77] wire _entries_WIRE_16_ppp = _entries_T_197; // @[TLB.scala:170:77] assign _entries_T_198 = _entries_WIRE_17[6]; // @[TLB.scala:170:77] wire _entries_WIRE_16_pr = _entries_T_198; // @[TLB.scala:170:77] assign _entries_T_199 = _entries_WIRE_17[7]; // @[TLB.scala:170:77] wire _entries_WIRE_16_px = _entries_T_199; // @[TLB.scala:170:77] assign _entries_T_200 = _entries_WIRE_17[8]; // @[TLB.scala:170:77] wire _entries_WIRE_16_pw = _entries_T_200; // @[TLB.scala:170:77] assign _entries_T_201 = _entries_WIRE_17[9]; // @[TLB.scala:170:77] wire _entries_WIRE_16_hr = _entries_T_201; // @[TLB.scala:170:77] assign _entries_T_202 = _entries_WIRE_17[10]; // @[TLB.scala:170:77] wire _entries_WIRE_16_hx = _entries_T_202; // @[TLB.scala:170:77] assign _entries_T_203 = _entries_WIRE_17[11]; // @[TLB.scala:170:77] wire _entries_WIRE_16_hw = _entries_T_203; // @[TLB.scala:170:77] assign _entries_T_204 = _entries_WIRE_17[12]; // @[TLB.scala:170:77] wire _entries_WIRE_16_sr = _entries_T_204; // @[TLB.scala:170:77] assign _entries_T_205 = _entries_WIRE_17[13]; // @[TLB.scala:170:77] wire _entries_WIRE_16_sx = _entries_T_205; // @[TLB.scala:170:77] assign _entries_T_206 = _entries_WIRE_17[14]; // @[TLB.scala:170:77] wire _entries_WIRE_16_sw = _entries_T_206; // @[TLB.scala:170:77] assign _entries_T_207 = _entries_WIRE_17[15]; // @[TLB.scala:170:77] wire _entries_WIRE_16_gf = _entries_T_207; // @[TLB.scala:170:77] assign _entries_T_208 = _entries_WIRE_17[16]; // @[TLB.scala:170:77] wire _entries_WIRE_16_pf = _entries_T_208; // @[TLB.scala:170:77] assign _entries_T_209 = _entries_WIRE_17[17]; // @[TLB.scala:170:77] wire _entries_WIRE_16_ae_stage2 = _entries_T_209; // @[TLB.scala:170:77] assign _entries_T_210 = _entries_WIRE_17[18]; // @[TLB.scala:170:77] wire _entries_WIRE_16_ae_final = _entries_T_210; // @[TLB.scala:170:77] assign _entries_T_211 = _entries_WIRE_17[19]; // @[TLB.scala:170:77] wire _entries_WIRE_16_ae_ptw = _entries_T_211; // @[TLB.scala:170:77] assign _entries_T_212 = _entries_WIRE_17[20]; // @[TLB.scala:170:77] wire _entries_WIRE_16_g = _entries_T_212; // @[TLB.scala:170:77] assign _entries_T_213 = _entries_WIRE_17[21]; // @[TLB.scala:170:77] wire _entries_WIRE_16_u = _entries_T_213; // @[TLB.scala:170:77] assign _entries_T_214 = _entries_WIRE_17[41:22]; // @[TLB.scala:170:77] wire [19:0] _entries_WIRE_16_ppn = _entries_T_214; // @[TLB.scala:170:77] wire [19:0] _entries_T_237; // @[TLB.scala:170:77] wire _entries_T_236; // @[TLB.scala:170:77] wire _entries_T_235; // @[TLB.scala:170:77] wire _entries_T_234; // @[TLB.scala:170:77] wire _entries_T_233; // @[TLB.scala:170:77] wire _entries_T_232; // @[TLB.scala:170:77] wire _entries_T_231; // @[TLB.scala:170:77] wire _entries_T_230; // @[TLB.scala:170:77] wire _entries_T_229; // @[TLB.scala:170:77] wire _entries_T_228; // @[TLB.scala:170:77] wire _entries_T_227; // @[TLB.scala:170:77] wire _entries_T_226; // @[TLB.scala:170:77] wire _entries_T_225; // @[TLB.scala:170:77] wire _entries_T_224; // @[TLB.scala:170:77] wire _entries_T_223; // @[TLB.scala:170:77] wire _entries_T_222; // @[TLB.scala:170:77] wire _entries_T_221; // @[TLB.scala:170:77] wire _entries_T_220; // @[TLB.scala:170:77] wire _entries_T_219; // @[TLB.scala:170:77] wire _entries_T_218; // @[TLB.scala:170:77] wire _entries_T_217; // @[TLB.scala:170:77] wire _entries_T_216; // @[TLB.scala:170:77] wire _entries_T_215; // @[TLB.scala:170:77] assign _entries_T_215 = _entries_WIRE_19[0]; // @[TLB.scala:170:77] wire _entries_WIRE_18_fragmented_superpage = _entries_T_215; // @[TLB.scala:170:77] assign _entries_T_216 = _entries_WIRE_19[1]; // @[TLB.scala:170:77] wire _entries_WIRE_18_c = _entries_T_216; // @[TLB.scala:170:77] assign _entries_T_217 = _entries_WIRE_19[2]; // @[TLB.scala:170:77] wire _entries_WIRE_18_eff = _entries_T_217; // @[TLB.scala:170:77] assign _entries_T_218 = _entries_WIRE_19[3]; // @[TLB.scala:170:77] wire _entries_WIRE_18_paa = _entries_T_218; // @[TLB.scala:170:77] assign _entries_T_219 = _entries_WIRE_19[4]; // @[TLB.scala:170:77] wire _entries_WIRE_18_pal = _entries_T_219; // @[TLB.scala:170:77] assign _entries_T_220 = _entries_WIRE_19[5]; // @[TLB.scala:170:77] wire _entries_WIRE_18_ppp = _entries_T_220; // @[TLB.scala:170:77] assign _entries_T_221 = _entries_WIRE_19[6]; // @[TLB.scala:170:77] wire _entries_WIRE_18_pr = _entries_T_221; // @[TLB.scala:170:77] assign _entries_T_222 = _entries_WIRE_19[7]; // @[TLB.scala:170:77] wire _entries_WIRE_18_px = _entries_T_222; // @[TLB.scala:170:77] assign _entries_T_223 = _entries_WIRE_19[8]; // @[TLB.scala:170:77] wire _entries_WIRE_18_pw = _entries_T_223; // @[TLB.scala:170:77] assign _entries_T_224 = _entries_WIRE_19[9]; // @[TLB.scala:170:77] wire _entries_WIRE_18_hr = _entries_T_224; // @[TLB.scala:170:77] assign _entries_T_225 = _entries_WIRE_19[10]; // @[TLB.scala:170:77] wire _entries_WIRE_18_hx = _entries_T_225; // @[TLB.scala:170:77] assign _entries_T_226 = _entries_WIRE_19[11]; // @[TLB.scala:170:77] wire _entries_WIRE_18_hw = _entries_T_226; // @[TLB.scala:170:77] assign _entries_T_227 = _entries_WIRE_19[12]; // @[TLB.scala:170:77] wire _entries_WIRE_18_sr = _entries_T_227; // @[TLB.scala:170:77] assign _entries_T_228 = _entries_WIRE_19[13]; // @[TLB.scala:170:77] wire _entries_WIRE_18_sx = _entries_T_228; // @[TLB.scala:170:77] assign _entries_T_229 = _entries_WIRE_19[14]; // @[TLB.scala:170:77] wire _entries_WIRE_18_sw = _entries_T_229; // @[TLB.scala:170:77] assign _entries_T_230 = _entries_WIRE_19[15]; // @[TLB.scala:170:77] wire _entries_WIRE_18_gf = _entries_T_230; // @[TLB.scala:170:77] assign _entries_T_231 = _entries_WIRE_19[16]; // @[TLB.scala:170:77] wire _entries_WIRE_18_pf = _entries_T_231; // @[TLB.scala:170:77] assign _entries_T_232 = _entries_WIRE_19[17]; // @[TLB.scala:170:77] wire _entries_WIRE_18_ae_stage2 = _entries_T_232; // @[TLB.scala:170:77] assign _entries_T_233 = _entries_WIRE_19[18]; // @[TLB.scala:170:77] wire _entries_WIRE_18_ae_final = _entries_T_233; // @[TLB.scala:170:77] assign _entries_T_234 = _entries_WIRE_19[19]; // @[TLB.scala:170:77] wire _entries_WIRE_18_ae_ptw = _entries_T_234; // @[TLB.scala:170:77] assign _entries_T_235 = _entries_WIRE_19[20]; // @[TLB.scala:170:77] wire _entries_WIRE_18_g = _entries_T_235; // @[TLB.scala:170:77] assign _entries_T_236 = _entries_WIRE_19[21]; // @[TLB.scala:170:77] wire _entries_WIRE_18_u = _entries_T_236; // @[TLB.scala:170:77] assign _entries_T_237 = _entries_WIRE_19[41:22]; // @[TLB.scala:170:77] wire [19:0] _entries_WIRE_18_ppn = _entries_T_237; // @[TLB.scala:170:77] wire [19:0] _entries_T_260; // @[TLB.scala:170:77] wire _entries_T_259; // @[TLB.scala:170:77] wire _entries_T_258; // @[TLB.scala:170:77] wire _entries_T_257; // @[TLB.scala:170:77] wire _entries_T_256; // @[TLB.scala:170:77] wire _entries_T_255; // @[TLB.scala:170:77] wire _entries_T_254; // @[TLB.scala:170:77] wire _entries_T_253; // @[TLB.scala:170:77] wire _entries_T_252; // @[TLB.scala:170:77] wire _entries_T_251; // @[TLB.scala:170:77] wire _entries_T_250; // @[TLB.scala:170:77] wire _entries_T_249; // @[TLB.scala:170:77] wire _entries_T_248; // @[TLB.scala:170:77] wire _entries_T_247; // @[TLB.scala:170:77] wire _entries_T_246; // @[TLB.scala:170:77] wire _entries_T_245; // @[TLB.scala:170:77] wire _entries_T_244; // @[TLB.scala:170:77] wire _entries_T_243; // @[TLB.scala:170:77] wire _entries_T_242; // @[TLB.scala:170:77] wire _entries_T_241; // @[TLB.scala:170:77] wire _entries_T_240; // @[TLB.scala:170:77] wire _entries_T_239; // @[TLB.scala:170:77] wire _entries_T_238; // @[TLB.scala:170:77] assign _entries_T_238 = _entries_WIRE_21[0]; // @[TLB.scala:170:77] wire _entries_WIRE_20_fragmented_superpage = _entries_T_238; // @[TLB.scala:170:77] assign _entries_T_239 = _entries_WIRE_21[1]; // @[TLB.scala:170:77] wire _entries_WIRE_20_c = _entries_T_239; // @[TLB.scala:170:77] assign _entries_T_240 = _entries_WIRE_21[2]; // @[TLB.scala:170:77] wire _entries_WIRE_20_eff = _entries_T_240; // @[TLB.scala:170:77] assign _entries_T_241 = _entries_WIRE_21[3]; // @[TLB.scala:170:77] wire _entries_WIRE_20_paa = _entries_T_241; // @[TLB.scala:170:77] assign _entries_T_242 = _entries_WIRE_21[4]; // @[TLB.scala:170:77] wire _entries_WIRE_20_pal = _entries_T_242; // @[TLB.scala:170:77] assign _entries_T_243 = _entries_WIRE_21[5]; // @[TLB.scala:170:77] wire _entries_WIRE_20_ppp = _entries_T_243; // @[TLB.scala:170:77] assign _entries_T_244 = _entries_WIRE_21[6]; // @[TLB.scala:170:77] wire _entries_WIRE_20_pr = _entries_T_244; // @[TLB.scala:170:77] assign _entries_T_245 = _entries_WIRE_21[7]; // @[TLB.scala:170:77] wire _entries_WIRE_20_px = _entries_T_245; // @[TLB.scala:170:77] assign _entries_T_246 = _entries_WIRE_21[8]; // @[TLB.scala:170:77] wire _entries_WIRE_20_pw = _entries_T_246; // @[TLB.scala:170:77] assign _entries_T_247 = _entries_WIRE_21[9]; // @[TLB.scala:170:77] wire _entries_WIRE_20_hr = _entries_T_247; // @[TLB.scala:170:77] assign _entries_T_248 = _entries_WIRE_21[10]; // @[TLB.scala:170:77] wire _entries_WIRE_20_hx = _entries_T_248; // @[TLB.scala:170:77] assign _entries_T_249 = _entries_WIRE_21[11]; // @[TLB.scala:170:77] wire _entries_WIRE_20_hw = _entries_T_249; // @[TLB.scala:170:77] assign _entries_T_250 = _entries_WIRE_21[12]; // @[TLB.scala:170:77] wire _entries_WIRE_20_sr = _entries_T_250; // @[TLB.scala:170:77] assign _entries_T_251 = _entries_WIRE_21[13]; // @[TLB.scala:170:77] wire _entries_WIRE_20_sx = _entries_T_251; // @[TLB.scala:170:77] assign _entries_T_252 = _entries_WIRE_21[14]; // @[TLB.scala:170:77] wire _entries_WIRE_20_sw = _entries_T_252; // @[TLB.scala:170:77] assign _entries_T_253 = _entries_WIRE_21[15]; // @[TLB.scala:170:77] wire _entries_WIRE_20_gf = _entries_T_253; // @[TLB.scala:170:77] assign _entries_T_254 = _entries_WIRE_21[16]; // @[TLB.scala:170:77] wire _entries_WIRE_20_pf = _entries_T_254; // @[TLB.scala:170:77] assign _entries_T_255 = _entries_WIRE_21[17]; // @[TLB.scala:170:77] wire _entries_WIRE_20_ae_stage2 = _entries_T_255; // @[TLB.scala:170:77] assign _entries_T_256 = _entries_WIRE_21[18]; // @[TLB.scala:170:77] wire _entries_WIRE_20_ae_final = _entries_T_256; // @[TLB.scala:170:77] assign _entries_T_257 = _entries_WIRE_21[19]; // @[TLB.scala:170:77] wire _entries_WIRE_20_ae_ptw = _entries_T_257; // @[TLB.scala:170:77] assign _entries_T_258 = _entries_WIRE_21[20]; // @[TLB.scala:170:77] wire _entries_WIRE_20_g = _entries_T_258; // @[TLB.scala:170:77] assign _entries_T_259 = _entries_WIRE_21[21]; // @[TLB.scala:170:77] wire _entries_WIRE_20_u = _entries_T_259; // @[TLB.scala:170:77] assign _entries_T_260 = _entries_WIRE_21[41:22]; // @[TLB.scala:170:77] wire [19:0] _entries_WIRE_20_ppn = _entries_T_260; // @[TLB.scala:170:77] wire [19:0] _entries_T_283; // @[TLB.scala:170:77] wire _entries_T_282; // @[TLB.scala:170:77] wire _entries_T_281; // @[TLB.scala:170:77] wire _entries_T_280; // @[TLB.scala:170:77] wire _entries_T_279; // @[TLB.scala:170:77] wire _entries_T_278; // @[TLB.scala:170:77] wire _entries_T_277; // @[TLB.scala:170:77] wire _entries_T_276; // @[TLB.scala:170:77] wire _entries_T_275; // @[TLB.scala:170:77] wire _entries_T_274; // @[TLB.scala:170:77] wire _entries_T_273; // @[TLB.scala:170:77] wire _entries_T_272; // @[TLB.scala:170:77] wire _entries_T_271; // @[TLB.scala:170:77] wire _entries_T_270; // @[TLB.scala:170:77] wire _entries_T_269; // @[TLB.scala:170:77] wire _entries_T_268; // @[TLB.scala:170:77] wire _entries_T_267; // @[TLB.scala:170:77] wire _entries_T_266; // @[TLB.scala:170:77] wire _entries_T_265; // @[TLB.scala:170:77] wire _entries_T_264; // @[TLB.scala:170:77] wire _entries_T_263; // @[TLB.scala:170:77] wire _entries_T_262; // @[TLB.scala:170:77] wire _entries_T_261; // @[TLB.scala:170:77] assign _entries_T_261 = _entries_WIRE_23[0]; // @[TLB.scala:170:77] wire _entries_WIRE_22_fragmented_superpage = _entries_T_261; // @[TLB.scala:170:77] assign _entries_T_262 = _entries_WIRE_23[1]; // @[TLB.scala:170:77] wire _entries_WIRE_22_c = _entries_T_262; // @[TLB.scala:170:77] assign _entries_T_263 = _entries_WIRE_23[2]; // @[TLB.scala:170:77] wire _entries_WIRE_22_eff = _entries_T_263; // @[TLB.scala:170:77] assign _entries_T_264 = _entries_WIRE_23[3]; // @[TLB.scala:170:77] wire _entries_WIRE_22_paa = _entries_T_264; // @[TLB.scala:170:77] assign _entries_T_265 = _entries_WIRE_23[4]; // @[TLB.scala:170:77] wire _entries_WIRE_22_pal = _entries_T_265; // @[TLB.scala:170:77] assign _entries_T_266 = _entries_WIRE_23[5]; // @[TLB.scala:170:77] wire _entries_WIRE_22_ppp = _entries_T_266; // @[TLB.scala:170:77] assign _entries_T_267 = _entries_WIRE_23[6]; // @[TLB.scala:170:77] wire _entries_WIRE_22_pr = _entries_T_267; // @[TLB.scala:170:77] assign _entries_T_268 = _entries_WIRE_23[7]; // @[TLB.scala:170:77] wire _entries_WIRE_22_px = _entries_T_268; // @[TLB.scala:170:77] assign _entries_T_269 = _entries_WIRE_23[8]; // @[TLB.scala:170:77] wire _entries_WIRE_22_pw = _entries_T_269; // @[TLB.scala:170:77] assign _entries_T_270 = _entries_WIRE_23[9]; // @[TLB.scala:170:77] wire _entries_WIRE_22_hr = _entries_T_270; // @[TLB.scala:170:77] assign _entries_T_271 = _entries_WIRE_23[10]; // @[TLB.scala:170:77] wire _entries_WIRE_22_hx = _entries_T_271; // @[TLB.scala:170:77] assign _entries_T_272 = _entries_WIRE_23[11]; // @[TLB.scala:170:77] wire _entries_WIRE_22_hw = _entries_T_272; // @[TLB.scala:170:77] assign _entries_T_273 = _entries_WIRE_23[12]; // @[TLB.scala:170:77] wire _entries_WIRE_22_sr = _entries_T_273; // @[TLB.scala:170:77] assign _entries_T_274 = _entries_WIRE_23[13]; // @[TLB.scala:170:77] wire _entries_WIRE_22_sx = _entries_T_274; // @[TLB.scala:170:77] assign _entries_T_275 = _entries_WIRE_23[14]; // @[TLB.scala:170:77] wire _entries_WIRE_22_sw = _entries_T_275; // @[TLB.scala:170:77] assign _entries_T_276 = _entries_WIRE_23[15]; // @[TLB.scala:170:77] wire _entries_WIRE_22_gf = _entries_T_276; // @[TLB.scala:170:77] assign _entries_T_277 = _entries_WIRE_23[16]; // @[TLB.scala:170:77] wire _entries_WIRE_22_pf = _entries_T_277; // @[TLB.scala:170:77] assign _entries_T_278 = _entries_WIRE_23[17]; // @[TLB.scala:170:77] wire _entries_WIRE_22_ae_stage2 = _entries_T_278; // @[TLB.scala:170:77] assign _entries_T_279 = _entries_WIRE_23[18]; // @[TLB.scala:170:77] wire _entries_WIRE_22_ae_final = _entries_T_279; // @[TLB.scala:170:77] assign _entries_T_280 = _entries_WIRE_23[19]; // @[TLB.scala:170:77] wire _entries_WIRE_22_ae_ptw = _entries_T_280; // @[TLB.scala:170:77] assign _entries_T_281 = _entries_WIRE_23[20]; // @[TLB.scala:170:77] wire _entries_WIRE_22_g = _entries_T_281; // @[TLB.scala:170:77] assign _entries_T_282 = _entries_WIRE_23[21]; // @[TLB.scala:170:77] wire _entries_WIRE_22_u = _entries_T_282; // @[TLB.scala:170:77] assign _entries_T_283 = _entries_WIRE_23[41:22]; // @[TLB.scala:170:77] wire [19:0] _entries_WIRE_22_ppn = _entries_T_283; // @[TLB.scala:170:77] wire [19:0] _entries_T_306; // @[TLB.scala:170:77] wire _entries_T_305; // @[TLB.scala:170:77] wire _entries_T_304; // @[TLB.scala:170:77] wire _entries_T_303; // @[TLB.scala:170:77] wire _entries_T_302; // @[TLB.scala:170:77] wire _entries_T_301; // @[TLB.scala:170:77] wire _entries_T_300; // @[TLB.scala:170:77] wire _entries_T_299; // @[TLB.scala:170:77] wire _entries_T_298; // @[TLB.scala:170:77] wire _entries_T_297; // @[TLB.scala:170:77] wire _entries_T_296; // @[TLB.scala:170:77] wire _entries_T_295; // @[TLB.scala:170:77] wire _entries_T_294; // @[TLB.scala:170:77] wire _entries_T_293; // @[TLB.scala:170:77] wire _entries_T_292; // @[TLB.scala:170:77] wire _entries_T_291; // @[TLB.scala:170:77] wire _entries_T_290; // @[TLB.scala:170:77] wire _entries_T_289; // @[TLB.scala:170:77] wire _entries_T_288; // @[TLB.scala:170:77] wire _entries_T_287; // @[TLB.scala:170:77] wire _entries_T_286; // @[TLB.scala:170:77] wire _entries_T_285; // @[TLB.scala:170:77] wire _entries_T_284; // @[TLB.scala:170:77] assign _entries_T_284 = _entries_WIRE_25[0]; // @[TLB.scala:170:77] wire _entries_WIRE_24_fragmented_superpage = _entries_T_284; // @[TLB.scala:170:77] assign _entries_T_285 = _entries_WIRE_25[1]; // @[TLB.scala:170:77] wire _entries_WIRE_24_c = _entries_T_285; // @[TLB.scala:170:77] assign _entries_T_286 = _entries_WIRE_25[2]; // @[TLB.scala:170:77] wire _entries_WIRE_24_eff = _entries_T_286; // @[TLB.scala:170:77] assign _entries_T_287 = _entries_WIRE_25[3]; // @[TLB.scala:170:77] wire _entries_WIRE_24_paa = _entries_T_287; // @[TLB.scala:170:77] assign _entries_T_288 = _entries_WIRE_25[4]; // @[TLB.scala:170:77] wire _entries_WIRE_24_pal = _entries_T_288; // @[TLB.scala:170:77] assign _entries_T_289 = _entries_WIRE_25[5]; // @[TLB.scala:170:77] wire _entries_WIRE_24_ppp = _entries_T_289; // @[TLB.scala:170:77] assign _entries_T_290 = _entries_WIRE_25[6]; // @[TLB.scala:170:77] wire _entries_WIRE_24_pr = _entries_T_290; // @[TLB.scala:170:77] assign _entries_T_291 = _entries_WIRE_25[7]; // @[TLB.scala:170:77] wire _entries_WIRE_24_px = _entries_T_291; // @[TLB.scala:170:77] assign _entries_T_292 = _entries_WIRE_25[8]; // @[TLB.scala:170:77] wire _entries_WIRE_24_pw = _entries_T_292; // @[TLB.scala:170:77] assign _entries_T_293 = _entries_WIRE_25[9]; // @[TLB.scala:170:77] wire _entries_WIRE_24_hr = _entries_T_293; // @[TLB.scala:170:77] assign _entries_T_294 = _entries_WIRE_25[10]; // @[TLB.scala:170:77] wire _entries_WIRE_24_hx = _entries_T_294; // @[TLB.scala:170:77] assign _entries_T_295 = _entries_WIRE_25[11]; // @[TLB.scala:170:77] wire _entries_WIRE_24_hw = _entries_T_295; // @[TLB.scala:170:77] assign _entries_T_296 = _entries_WIRE_25[12]; // @[TLB.scala:170:77] wire _entries_WIRE_24_sr = _entries_T_296; // @[TLB.scala:170:77] assign _entries_T_297 = _entries_WIRE_25[13]; // @[TLB.scala:170:77] wire _entries_WIRE_24_sx = _entries_T_297; // @[TLB.scala:170:77] assign _entries_T_298 = _entries_WIRE_25[14]; // @[TLB.scala:170:77] wire _entries_WIRE_24_sw = _entries_T_298; // @[TLB.scala:170:77] assign _entries_T_299 = _entries_WIRE_25[15]; // @[TLB.scala:170:77] wire _entries_WIRE_24_gf = _entries_T_299; // @[TLB.scala:170:77] assign _entries_T_300 = _entries_WIRE_25[16]; // @[TLB.scala:170:77] wire _entries_WIRE_24_pf = _entries_T_300; // @[TLB.scala:170:77] assign _entries_T_301 = _entries_WIRE_25[17]; // @[TLB.scala:170:77] wire _entries_WIRE_24_ae_stage2 = _entries_T_301; // @[TLB.scala:170:77] assign _entries_T_302 = _entries_WIRE_25[18]; // @[TLB.scala:170:77] wire _entries_WIRE_24_ae_final = _entries_T_302; // @[TLB.scala:170:77] assign _entries_T_303 = _entries_WIRE_25[19]; // @[TLB.scala:170:77] wire _entries_WIRE_24_ae_ptw = _entries_T_303; // @[TLB.scala:170:77] assign _entries_T_304 = _entries_WIRE_25[20]; // @[TLB.scala:170:77] wire _entries_WIRE_24_g = _entries_T_304; // @[TLB.scala:170:77] assign _entries_T_305 = _entries_WIRE_25[21]; // @[TLB.scala:170:77] wire _entries_WIRE_24_u = _entries_T_305; // @[TLB.scala:170:77] assign _entries_T_306 = _entries_WIRE_25[41:22]; // @[TLB.scala:170:77] wire [19:0] _entries_WIRE_24_ppn = _entries_T_306; // @[TLB.scala:170:77] wire _ppn_T = ~vm_enabled; // @[TLB.scala:399:61, :442:18, :502:30] wire [1:0] ppn_res = _entries_barrier_8_io_y_ppn[19:18]; // @[package.scala:267:25] wire ppn_ignore = _ppn_ignore_T; // @[TLB.scala:197:{28,34}] wire [26:0] _ppn_T_1 = ppn_ignore ? vpn : 27'h0; // @[TLB.scala:197:34, :198:28, :335:30] wire [26:0] _ppn_T_2 = {_ppn_T_1[26:20], _ppn_T_1[19:0] \| _entries_barrier_8_io_y_ppn}; // @[package.scala:267:25] wire [8:0] _ppn_T_3 = _ppn_T_2[17:9]; // @[TLB.scala:198:{47,58}] wire [10:0] _ppn_T_4 = {ppn_res, _ppn_T_3}; // @[TLB.scala:195:26, :198:{18,58}] wire _ppn_ignore_T_1 = ~(superpage_entries_0_level[1]); // @[TLB.scala:182:28, :197:28, :341:30] wire [26:0] _ppn_T_6 = {_ppn_T_5[26:20], _ppn_T_5[19:0] \| _entries_barrier_8_io_y_ppn}; // @[package.scala:267:25] wire [8:0] _ppn_T_7 = _ppn_T_6[8:0]; // @[TLB.scala:198:{47,58}] wire [19:0] _ppn_T_8 = {_ppn_T_4, _ppn_T_7}; // @[TLB.scala:198:{18,58}] wire [1:0] ppn_res_1 = _entries_barrier_9_io_y_ppn[19:18]; // @[package.scala:267:25] wire ppn_ignore_2 = _ppn_ignore_T_2; // @[TLB.scala:197:{28,34}] wire [26:0] _ppn_T_9 = ppn_ignore_2 ? vpn : 27'h0; // @[TLB.scala:197:34, :198:28, :335:30] wire [26:0] _ppn_T_10 = {_ppn_T_9[26:20], _ppn_T_9[19:0] \| _entries_barrier_9_io_y_ppn}; // @[package.scala:267:25] wire [8:0] _ppn_T_11 = _ppn_T_10[17:9]; // @[TLB.scala:198:{47,58}] wire [10:0] _ppn_T_12 = {ppn_res_1, _ppn_T_11}; // @[TLB.scala:195:26, :198:{18,58}] wire _ppn_ignore_T_3 = ~(superpage_entries_1_level[1]); // @[TLB.scala:182:28, :197:28, :341:30] wire [26:0] _ppn_T_14 = {_ppn_T_13[26:20], _ppn_T_13[19:0] \| _entries_barrier_9_io_y_ppn}; // @[package.scala:267:25] wire [8:0] _ppn_T_15 = _ppn_T_14[8:0]; // @[TLB.scala:198:{47,58}] wire [19:0] _ppn_T_16 = {_ppn_T_12, _ppn_T_15}; // @[TLB.scala:198:{18,58}] wire [1:0] ppn_res_2 = _entries_barrier_10_io_y_ppn[19:18]; // @[package.scala:267:25] wire ppn_ignore_4 = _ppn_ignore_T_4; // @[TLB.scala:197:{28,34}] wire [26:0] _ppn_T_17 = ppn_ignore_4 ? vpn : 27'h0; // @[TLB.scala:197:34, :198:28, :335:30] wire [26:0] _ppn_T_18 = {_ppn_T_17[26:20], _ppn_T_17[19:0] \| _entries_barrier_10_io_y_ppn}; // @[package.scala:267:25] wire [8:0] _ppn_T_19 = _ppn_T_18[17:9]; // @[TLB.scala:198:{47,58}] wire [10:0] _ppn_T_20 = {ppn_res_2, _ppn_T_19}; // @[TLB.scala:195:26, :198:{18,58}] wire _ppn_ignore_T_5 = ~(superpage_entries_2_level[1]); // @[TLB.scala:182:28, :197:28, :341:30] wire [26:0] _ppn_T_22 = {_ppn_T_21[26:20], _ppn_T_21[19:0] \| _entries_barrier_10_io_y_ppn}; // @[package.scala:267:25] wire [8:0] _ppn_T_23 = _ppn_T_22[8:0]; // @[TLB.scala:198:{47,58}] wire [19:0] _ppn_T_24 = {_ppn_T_20, _ppn_T_23}; // @[TLB.scala:198:{18,58}] wire [1:0] ppn_res_3 = _entries_barrier_11_io_y_ppn[19:18]; // @[package.scala:267:25] wire ppn_ignore_6 = _ppn_ignore_T_6; // @[TLB.scala:197:{28,34}] wire [26:0] _ppn_T_25 = ppn_ignore_6 ? vpn : 27'h0; // @[TLB.scala:197:34, :198:28, :335:30] wire [26:0] _ppn_T_26 = {_ppn_T_25[26:20], _ppn_T_25[19:0] \| _entries_barrier_11_io_y_ppn}; // @[package.scala:267:25] wire [8:0] _ppn_T_27 = _ppn_T_26[17:9]; // @[TLB.scala:198:{47,58}] wire [10:0] _ppn_T_28 = {ppn_res_3, _ppn_T_27}; // @[TLB.scala:195:26, :198:{18,58}] wire _ppn_ignore_T_7 = ~(superpage_entries_3_level[1]); // @[TLB.scala:182:28, :197:28, :341:30] wire [26:0] _ppn_T_30 = {_ppn_T_29[26:20], _ppn_T_29[19:0] \| _entries_barrier_11_io_y_ppn}; // @[package.scala:267:25] wire [8:0] _ppn_T_31 = _ppn_T_30[8:0]; // @[TLB.scala:198:{47,58}] wire [19:0] _ppn_T_32 = {_ppn_T_28, _ppn_T_31}; // @[TLB.scala:198:{18,58}] wire [1:0] ppn_res_4 = _entries_barrier_12_io_y_ppn[19:18]; // @[package.scala:267:25] wire ppn_ignore_8 = _ppn_ignore_T_8; // @[TLB.scala:197:{28,34}] wire [26:0] _ppn_T_33 = ppn_ignore_8 ? vpn : 27'h0; // @[TLB.scala:197:34, :198:28, :335:30] wire [26:0] _ppn_T_34 = {_ppn_T_33[26:20], _ppn_T_33[19:0] \| _entries_barrier_12_io_y_ppn}; // @[package.scala:267:25] wire [8:0] _ppn_T_35 = _ppn_T_34[17:9]; // @[TLB.scala:198:{47,58}] wire [10:0] _ppn_T_36 = {ppn_res_4, _ppn_T_35}; // @[TLB.scala:195:26, :198:{18,58}] wire _ppn_ignore_T_9 = ~(special_entry_level[1]); // @[TLB.scala:197:28, :346:56] wire ppn_ignore_9 = _ppn_ignore_T_9; // @[TLB.scala:197:{28,34}] wire [26:0] _ppn_T_37 = ppn_ignore_9 ? vpn : 27'h0; // @[TLB.scala:197:34, :198:28, :335:30] wire [26:0] _ppn_T_38 = {_ppn_T_37[26:20], _ppn_T_37[19:0] \| _entries_barrier_12_io_y_ppn}; // @[package.scala:267:25] wire [8:0] _ppn_T_39 = _ppn_T_38[8:0]; // @[TLB.scala:198:{47,58}] wire [19:0] _ppn_T_40 = {_ppn_T_36, _ppn_T_39}; // @[TLB.scala:198:{18,58}] wire [19:0] _ppn_T_41 = vpn[19:0]; // @[TLB.scala:335:30, :502:125] wire [19:0] _ppn_T_42 = hitsVec_0 ? _entries_barrier_io_y_ppn : 20'h0; // @[Mux.scala:30:73] wire [19:0] _ppn_T_43 = hitsVec_1 ? _entries_barrier_1_io_y_ppn : 20'h0; // @[Mux.scala:30:73] wire [19:0] _ppn_T_44 = hitsVec_2 ? _entries_barrier_2_io_y_ppn : 20'h0; // @[Mux.scala:30:73] wire [19:0] _ppn_T_45 = hitsVec_3 ? _entries_barrier_3_io_y_ppn : 20'h0; // @[Mux.scala:30:73] wire [19:0] _ppn_T_46 = hitsVec_4 ? _entries_barrier_4_io_y_ppn : 20'h0; // @[Mux.scala:30:73] wire [19:0] _ppn_T_47 = hitsVec_5 ? _entries_barrier_5_io_y_ppn : 20'h0; // @[Mux.scala:30:73] wire [19:0] _ppn_T_48 = hitsVec_6 ? _entries_barrier_6_io_y_ppn : 20'h0; // @[Mux.scala:30:73] wire [19:0] _ppn_T_49 = hitsVec_7 ? _entries_barrier_7_io_y_ppn : 20'h0; // @[Mux.scala:30:73] wire [19:0] _ppn_T_50 = hitsVec_8 ? _ppn_T_8 : 20'h0; // @[Mux.scala:30:73] wire [19:0] _ppn_T_51 = hitsVec_9 ? _ppn_T_16 : 20'h0; // @[Mux.scala:30:73] wire [19:0] _ppn_T_52 = hitsVec_10 ? _ppn_T_24 : 20'h0; // @[Mux.scala:30:73] wire [19:0] _ppn_T_53 = hitsVec_11 ? _ppn_T_32 : 20'h0; // @[Mux.scala:30:73] wire [19:0] _ppn_T_54 = hitsVec_12 ? _ppn_T_40 : 20'h0; // @[Mux.scala:30:73] wire [19:0] _ppn_T_55 = _ppn_T ? _ppn_T_41 : 20'h0; // @[Mux.scala:30:73] wire [19:0] _ppn_T_56 = _ppn_T_42 \| _ppn_T_43; // @[Mux.scala:30:73] wire [19:0] _ppn_T_57 = _ppn_T_56 \| _ppn_T_44; // @[Mux.scala:30:73] wire [19:0] _ppn_T_58 = _ppn_T_57 \| _ppn_T_45; // @[Mux.scala:30:73] wire [19:0] _ppn_T_59 = _ppn_T_58 \| _ppn_T_46; // @[Mux.scala:30:73] wire [19:0] _ppn_T_60 = _ppn_T_59 \| _ppn_T_47; // @[Mux.scala:30:73] wire [19:0] _ppn_T_61 = _ppn_T_60 \| _ppn_T_48; // @[Mux.scala:30:73] wire [19:0] _ppn_T_62 = _ppn_T_61 \| _ppn_T_49; // @[Mux.scala:30:73] wire [19:0] _ppn_T_63 = _ppn_T_62 \| _ppn_T_50; // @[Mux.scala:30:73] wire [19:0] _ppn_T_64 = _ppn_T_63 \| _ppn_T_51; // @[Mux.scala:30:73] wire [19:0] _ppn_T_65 = _ppn_T_64 \| _ppn_T_52; // @[Mux.scala:30:73] wire [19:0] _ppn_T_66 = _ppn_T_65 \| _ppn_T_53; // @[Mux.scala:30:73] wire [19:0] _ppn_T_67 = _ppn_T_66 \| _ppn_T_54; // @[Mux.scala:30:73] wire [19:0] _ppn_T_68 = _ppn_T_67 \| _ppn_T_55; // @[Mux.scala:30:73] wire [19:0] ppn = _ppn_T_68; // @[Mux.scala:30:73] wire [1:0] ptw_ae_array_lo_lo_hi = {_entries_barrier_2_io_y_ae_ptw, _entries_barrier_1_io_y_ae_ptw}; // @[package.scala:45:27, :267:25] wire [2:0] ptw_ae_array_lo_lo = {ptw_ae_array_lo_lo_hi, _entries_barrier_io_y_ae_ptw}; // @[package.scala:45:27, :267:25] wire [1:0] ptw_ae_array_lo_hi_hi = {_entries_barrier_5_io_y_ae_ptw, _entries_barrier_4_io_y_ae_ptw}; // @[package.scala:45:27, :267:25] wire [2:0] ptw_ae_array_lo_hi = {ptw_ae_array_lo_hi_hi, _entries_barrier_3_io_y_ae_ptw}; // @[package.scala:45:27, :267:25] wire [5:0] ptw_ae_array_lo = {ptw_ae_array_lo_hi, ptw_ae_array_lo_lo}; // @[package.scala:45:27] wire [1:0] ptw_ae_array_hi_lo_hi = {_entries_barrier_8_io_y_ae_ptw, _entries_barrier_7_io_y_ae_ptw}; // @[package.scala:45:27, :267:25] wire [2:0] ptw_ae_array_hi_lo = {ptw_ae_array_hi_lo_hi, _entries_barrier_6_io_y_ae_ptw}; // @[package.scala:45:27, :267:25] wire [1:0] ptw_ae_array_hi_hi_lo = {_entries_barrier_10_io_y_ae_ptw, _entries_barrier_9_io_y_ae_ptw}; // @[package.scala:45:27, :267:25] wire [1:0] ptw_ae_array_hi_hi_hi = {_entries_barrier_12_io_y_ae_ptw, _entries_barrier_11_io_y_ae_ptw}; // @[package.scala:45:27, :267:25] wire [3:0] ptw_ae_array_hi_hi = {ptw_ae_array_hi_hi_hi, ptw_ae_array_hi_hi_lo}; // @[package.scala:45:27] wire [6:0] ptw_ae_array_hi = {ptw_ae_array_hi_hi, ptw_ae_array_hi_lo}; // @[package.scala:45:27] wire [12:0] _ptw_ae_array_T = {ptw_ae_array_hi, ptw_ae_array_lo}; // @[package.scala:45:27] wire [13:0] ptw_ae_array = {1'h0, _ptw_ae_array_T}; // @[package.scala:45:27] wire [1:0] final_ae_array_lo_lo_hi = {_entries_barrier_2_io_y_ae_final, _entries_barrier_1_io_y_ae_final}; // @[package.scala:45:27, :267:25] wire [2:0] final_ae_array_lo_lo = {final_ae_array_lo_lo_hi, _entries_barrier_io_y_ae_final}; // @[package.scala:45:27, :267:25] wire [1:0] final_ae_array_lo_hi_hi = {_entries_barrier_5_io_y_ae_final, _entries_barrier_4_io_y_ae_final}; // @[package.scala:45:27, :267:25] wire [2:0] final_ae_array_lo_hi = {final_ae_array_lo_hi_hi, _entries_barrier_3_io_y_ae_final}; // @[package.scala:45:27, :267:25] wire [5:0] final_ae_array_lo = {final_ae_array_lo_hi, final_ae_array_lo_lo}; // @[package.scala:45:27] wire [1:0] final_ae_array_hi_lo_hi = {_entries_barrier_8_io_y_ae_final, _entries_barrier_7_io_y_ae_final}; // @[package.scala:45:27, :267:25] wire [2:0] final_ae_array_hi_lo = {final_ae_array_hi_lo_hi, _entries_barrier_6_io_y_ae_final}; // @[package.scala:45:27, :267:25] wire [1:0] final_ae_array_hi_hi_lo = {_entries_barrier_10_io_y_ae_final, _entries_barrier_9_io_y_ae_final}; // @[package.scala:45:27, :267:25] wire [1:0] final_ae_array_hi_hi_hi = {_entries_barrier_12_io_y_ae_final, _entries_barrier_11_io_y_ae_final}; // @[package.scala:45:27, :267:25] wire [3:0] final_ae_array_hi_hi = {final_ae_array_hi_hi_hi, final_ae_array_hi_hi_lo}; // @[package.scala:45:27] wire [6:0] final_ae_array_hi = {final_ae_array_hi_hi, final_ae_array_hi_lo}; // @[package.scala:45:27] wire [12:0] _final_ae_array_T = {final_ae_array_hi, final_ae_array_lo}; // @[package.scala:45:27] wire [13:0] final_ae_array = {1'h0, _final_ae_array_T}; // @[package.scala:45:27] wire [1:0] ptw_pf_array_lo_lo_hi = {_entries_barrier_2_io_y_pf, _entries_barrier_1_io_y_pf}; // @[package.scala:45:27, :267:25] wire [2:0] ptw_pf_array_lo_lo = {ptw_pf_array_lo_lo_hi, _entries_barrier_io_y_pf}; // @[package.scala:45:27, :267:25] wire [1:0] ptw_pf_array_lo_hi_hi = {_entries_barrier_5_io_y_pf, _entries_barrier_4_io_y_pf}; // @[package.scala:45:27, :267:25] wire [2:0] ptw_pf_array_lo_hi = {ptw_pf_array_lo_hi_hi, _entries_barrier_3_io_y_pf}; // @[package.scala:45:27, :267:25] wire [5:0] ptw_pf_array_lo = {ptw_pf_array_lo_hi, ptw_pf_array_lo_lo}; // @[package.scala:45:27] wire [1:0] ptw_pf_array_hi_lo_hi = {_entries_barrier_8_io_y_pf, _entries_barrier_7_io_y_pf}; // @[package.scala:45:27, :267:25] wire [2:0] ptw_pf_array_hi_lo = {ptw_pf_array_hi_lo_hi, _entries_barrier_6_io_y_pf}; // @[package.scala:45:27, :267:25] wire [1:0] ptw_pf_array_hi_hi_lo = {_entries_barrier_10_io_y_pf, _entries_barrier_9_io_y_pf}; // @[package.scala:45:27, :267:25] wire [1:0] ptw_pf_array_hi_hi_hi = {_entries_barrier_12_io_y_pf, _entries_barrier_11_io_y_pf}; // @[package.scala:45:27, :267:25] wire [3:0] ptw_pf_array_hi_hi = {ptw_pf_array_hi_hi_hi, ptw_pf_array_hi_hi_lo}; // @[package.scala:45:27] wire [6:0] ptw_pf_array_hi = {ptw_pf_array_hi_hi, ptw_pf_array_hi_lo}; // @[package.scala:45:27] wire [12:0] _ptw_pf_array_T = {ptw_pf_array_hi, ptw_pf_array_lo}; // @[package.scala:45:27] wire [13:0] ptw_pf_array = {1'h0, _ptw_pf_array_T}; // @[package.scala:45:27] wire [1:0] ptw_gf_array_lo_lo_hi = {_entries_barrier_2_io_y_gf, _entries_barrier_1_io_y_gf}; // @[package.scala:45:27, :267:25] wire [2:0] ptw_gf_array_lo_lo = {ptw_gf_array_lo_lo_hi, _entries_barrier_io_y_gf}; // @[package.scala:45:27, :267:25] wire [1:0] ptw_gf_array_lo_hi_hi = {_entries_barrier_5_io_y_gf, _entries_barrier_4_io_y_gf}; // @[package.scala:45:27, :267:25] wire [2:0] ptw_gf_array_lo_hi = {ptw_gf_array_lo_hi_hi, _entries_barrier_3_io_y_gf}; // @[package.scala:45:27, :267:25] wire [5:0] ptw_gf_array_lo = {ptw_gf_array_lo_hi, ptw_gf_array_lo_lo}; // @[package.scala:45:27] wire [1:0] ptw_gf_array_hi_lo_hi = {_entries_barrier_8_io_y_gf, _entries_barrier_7_io_y_gf}; // @[package.scala:45:27, :267:25] wire [2:0] ptw_gf_array_hi_lo = {ptw_gf_array_hi_lo_hi, _entries_barrier_6_io_y_gf}; // @[package.scala:45:27, :267:25] wire [1:0] ptw_gf_array_hi_hi_lo = {_entries_barrier_10_io_y_gf, _entries_barrier_9_io_y_gf}; // @[package.scala:45:27, :267:25] wire [1:0] ptw_gf_array_hi_hi_hi = {_entries_barrier_12_io_y_gf, _entries_barrier_11_io_y_gf}; // @[package.scala:45:27, :267:25] wire [3:0] ptw_gf_array_hi_hi = {ptw_gf_array_hi_hi_hi, ptw_gf_array_hi_hi_lo}; // @[package.scala:45:27] wire [6:0] ptw_gf_array_hi = {ptw_gf_array_hi_hi, ptw_gf_array_hi_lo}; // @[package.scala:45:27] wire [12:0] _ptw_gf_array_T = {ptw_gf_array_hi, ptw_gf_array_lo}; // @[package.scala:45:27] wire [13:0] ptw_gf_array = {1'h0, _ptw_gf_array_T}; // @[package.scala:45:27] wire [13:0] _gf_ld_array_T_3 = ptw_gf_array; // @[TLB.scala:509:25, :600:82] wire [13:0] _gf_st_array_T_2 = ptw_gf_array; // @[TLB.scala:509:25, :601:63] wire [13:0] _gf_inst_array_T_1 = ptw_gf_array; // @[TLB.scala:509:25, :602:46] wire _priv_rw_ok_T = ~priv_s; // @[TLB.scala:370:20, :513:24] wire _priv_rw_ok_T_1 = _priv_rw_ok_T \| sum; // @[TLB.scala:510:16, :513:{24,32}] wire [1:0] _GEN_40 = {_entries_barrier_2_io_y_u, _entries_barrier_1_io_y_u}; // @[package.scala:45:27, :267:25] wire [1:0] priv_rw_ok_lo_lo_hi; // @[package.scala:45:27] assign priv_rw_ok_lo_lo_hi = _GEN_40; // @[package.scala:45:27] wire [1:0] priv_rw_ok_lo_lo_hi_1; // @[package.scala:45:27] assign priv_rw_ok_lo_lo_hi_1 = _GEN_40; // @[package.scala:45:27] wire [1:0] priv_x_ok_lo_lo_hi; // @[package.scala:45:27] assign priv_x_ok_lo_lo_hi = _GEN_40; // @[package.scala:45:27] wire [1:0] priv_x_ok_lo_lo_hi_1; // @[package.scala:45:27] assign priv_x_ok_lo_lo_hi_1 = _GEN_40; // @[package.scala:45:27] wire [2:0] priv_rw_ok_lo_lo = {priv_rw_ok_lo_lo_hi, _entries_barrier_io_y_u}; // @[package.scala:45:27, :267:25] wire [1:0] _GEN_41 = {_entries_barrier_5_io_y_u, _entries_barrier_4_io_y_u}; // @[package.scala:45:27, :267:25] wire [1:0] priv_rw_ok_lo_hi_hi; // @[package.scala:45:27] assign priv_rw_ok_lo_hi_hi = _GEN_41; // @[package.scala:45:27] wire [1:0] priv_rw_ok_lo_hi_hi_1; // @[package.scala:45:27] assign priv_rw_ok_lo_hi_hi_1 = _GEN_41; // @[package.scala:45:27] wire [1:0] priv_x_ok_lo_hi_hi; // @[package.scala:45:27] assign priv_x_ok_lo_hi_hi = _GEN_41; // @[package.scala:45:27] wire [1:0] priv_x_ok_lo_hi_hi_1; // @[package.scala:45:27] assign priv_x_ok_lo_hi_hi_1 = _GEN_41; // @[package.scala:45:27] wire [2:0] priv_rw_ok_lo_hi = {priv_rw_ok_lo_hi_hi, _entries_barrier_3_io_y_u}; // @[package.scala:45:27, :267:25] wire [5:0] priv_rw_ok_lo = {priv_rw_ok_lo_hi, priv_rw_ok_lo_lo}; // @[package.scala:45:27] wire [1:0] _GEN_42 = {_entries_barrier_8_io_y_u, _entries_barrier_7_io_y_u}; // @[package.scala:45:27, :267:25] wire [1:0] priv_rw_ok_hi_lo_hi; // @[package.scala:45:27] assign priv_rw_ok_hi_lo_hi = _GEN_42; // @[package.scala:45:27] wire [1:0] priv_rw_ok_hi_lo_hi_1; // @[package.scala:45:27] assign priv_rw_ok_hi_lo_hi_1 = _GEN_42; // @[package.scala:45:27] wire [1:0] priv_x_ok_hi_lo_hi; // @[package.scala:45:27] assign priv_x_ok_hi_lo_hi = _GEN_42; // @[package.scala:45:27] wire [1:0] priv_x_ok_hi_lo_hi_1; // @[package.scala:45:27] assign priv_x_ok_hi_lo_hi_1 = _GEN_42; // @[package.scala:45:27] wire [2:0] priv_rw_ok_hi_lo = {priv_rw_ok_hi_lo_hi, _entries_barrier_6_io_y_u}; // @[package.scala:45:27, :267:25] wire [1:0] _GEN_43 = {_entries_barrier_10_io_y_u, _entries_barrier_9_io_y_u}; // @[package.scala:45:27, :267:25] wire [1:0] priv_rw_ok_hi_hi_lo; // @[package.scala:45:27] assign priv_rw_ok_hi_hi_lo = _GEN_43; // @[package.scala:45:27] wire [1:0] priv_rw_ok_hi_hi_lo_1; // @[package.scala:45:27] assign priv_rw_ok_hi_hi_lo_1 = _GEN_43; // @[package.scala:45:27] wire [1:0] priv_x_ok_hi_hi_lo; // @[package.scala:45:27] assign priv_x_ok_hi_hi_lo = _GEN_43; // @[package.scala:45:27] wire [1:0] priv_x_ok_hi_hi_lo_1; // @[package.scala:45:27] assign priv_x_ok_hi_hi_lo_1 = _GEN_43; // @[package.scala:45:27] wire [1:0] _GEN_44 = {_entries_barrier_12_io_y_u, _entries_barrier_11_io_y_u}; // @[package.scala:45:27, :267:25] wire [1:0] priv_rw_ok_hi_hi_hi; // @[package.scala:45:27] assign priv_rw_ok_hi_hi_hi = _GEN_44; // @[package.scala:45:27] wire [1:0] priv_rw_ok_hi_hi_hi_1; // @[package.scala:45:27] assign priv_rw_ok_hi_hi_hi_1 = _GEN_44; // @[package.scala:45:27] wire [1:0] priv_x_ok_hi_hi_hi; // @[package.scala:45:27] assign priv_x_ok_hi_hi_hi = _GEN_44; // @[package.scala:45:27] wire [1:0] priv_x_ok_hi_hi_hi_1; // @[package.scala:45:27] assign priv_x_ok_hi_hi_hi_1 = _GEN_44; // @[package.scala:45:27] wire [3:0] priv_rw_ok_hi_hi = {priv_rw_ok_hi_hi_hi, priv_rw_ok_hi_hi_lo}; // @[package.scala:45:27] wire [6:0] priv_rw_ok_hi = {priv_rw_ok_hi_hi, priv_rw_ok_hi_lo}; // @[package.scala:45:27] wire [12:0] _priv_rw_ok_T_2 = {priv_rw_ok_hi, priv_rw_ok_lo}; // @[package.scala:45:27] wire [12:0] _priv_rw_ok_T_3 = _priv_rw_ok_T_1 ? _priv_rw_ok_T_2 : 13'h0; // @[package.scala:45:27] wire [2:0] priv_rw_ok_lo_lo_1 = {priv_rw_ok_lo_lo_hi_1, _entries_barrier_io_y_u}; // @[package.scala:45:27, :267:25] wire [2:0] priv_rw_ok_lo_hi_1 = {priv_rw_ok_lo_hi_hi_1, _entries_barrier_3_io_y_u}; // @[package.scala:45:27, :267:25] wire [5:0] priv_rw_ok_lo_1 = {priv_rw_ok_lo_hi_1, priv_rw_ok_lo_lo_1}; // @[package.scala:45:27] wire [2:0] priv_rw_ok_hi_lo_1 = {priv_rw_ok_hi_lo_hi_1, _entries_barrier_6_io_y_u}; // @[package.scala:45:27, :267:25] wire [3:0] priv_rw_ok_hi_hi_1 = {priv_rw_ok_hi_hi_hi_1, priv_rw_ok_hi_hi_lo_1}; // @[package.scala:45:27] wire [6:0] priv_rw_ok_hi_1 = {priv_rw_ok_hi_hi_1, priv_rw_ok_hi_lo_1}; // @[package.scala:45:27] wire [12:0] _priv_rw_ok_T_4 = {priv_rw_ok_hi_1, priv_rw_ok_lo_1}; // @[package.scala:45:27] wire [12:0] _priv_rw_ok_T_5 = ~_priv_rw_ok_T_4; // @[package.scala:45:27] wire [12:0] _priv_rw_ok_T_6 = priv_s ? _priv_rw_ok_T_5 : 13'h0; // @[TLB.scala:370:20, :513:{75,84}] wire [12:0] priv_rw_ok = _priv_rw_ok_T_3 \| _priv_rw_ok_T_6; // @[TLB.scala:513:{23,70,75}] wire [2:0] priv_x_ok_lo_lo = {priv_x_ok_lo_lo_hi, _entries_barrier_io_y_u}; // @[package.scala:45:27, :267:25] wire [2:0] priv_x_ok_lo_hi = {priv_x_ok_lo_hi_hi, _entries_barrier_3_io_y_u}; // @[package.scala:45:27, :267:25] wire [5:0] priv_x_ok_lo = {priv_x_ok_lo_hi, priv_x_ok_lo_lo}; // @[package.scala:45:27] wire [2:0] priv_x_ok_hi_lo = {priv_x_ok_hi_lo_hi, _entries_barrier_6_io_y_u}; // @[package.scala:45:27, :267:25] wire [3:0] priv_x_ok_hi_hi = {priv_x_ok_hi_hi_hi, priv_x_ok_hi_hi_lo}; // @[package.scala:45:27] wire [6:0] priv_x_ok_hi = {priv_x_ok_hi_hi, priv_x_ok_hi_lo}; // @[package.scala:45:27] wire [12:0] _priv_x_ok_T = {priv_x_ok_hi, priv_x_ok_lo}; // @[package.scala:45:27] wire [12:0] _priv_x_ok_T_1 = ~_priv_x_ok_T; // @[package.scala:45:27] wire [2:0] priv_x_ok_lo_lo_1 = {priv_x_ok_lo_lo_hi_1, _entries_barrier_io_y_u}; // @[package.scala:45:27, :267:25] wire [2:0] priv_x_ok_lo_hi_1 = {priv_x_ok_lo_hi_hi_1, _entries_barrier_3_io_y_u}; // @[package.scala:45:27, :267:25] wire [5:0] priv_x_ok_lo_1 = {priv_x_ok_lo_hi_1, priv_x_ok_lo_lo_1}; // @[package.scala:45:27] wire [2:0] priv_x_ok_hi_lo_1 = {priv_x_ok_hi_lo_hi_1, _entries_barrier_6_io_y_u}; // @[package.scala:45:27, :267:25] wire [3:0] priv_x_ok_hi_hi_1 = {priv_x_ok_hi_hi_hi_1, priv_x_ok_hi_hi_lo_1}; // @[package.scala:45:27] wire [6:0] priv_x_ok_hi_1 = {priv_x_ok_hi_hi_1, priv_x_ok_hi_lo_1}; // @[package.scala:45:27] wire [12:0] _priv_x_ok_T_2 = {priv_x_ok_hi_1, priv_x_ok_lo_1}; // @[package.scala:45:27] wire [12:0] priv_x_ok = priv_s ? _priv_x_ok_T_1 : _priv_x_ok_T_2; // @[package.scala:45:27] wire _stage1_bypass_T_1 = ~stage1_en; // @[TLB.scala:374:29, :517:83] wire [12:0] _stage1_bypass_T_2 = {13{_stage1_bypass_T_1}}; // @[TLB.scala:517:{68,83}] wire [1:0] stage1_bypass_lo_lo_hi = {_entries_barrier_2_io_y_ae_stage2, _entries_barrier_1_io_y_ae_stage2}; // @[package.scala:45:27, :267:25] wire [2:0] stage1_bypass_lo_lo = {stage1_bypass_lo_lo_hi, _entries_barrier_io_y_ae_stage2}; // @[package.scala:45:27, :267:25] wire [1:0] stage1_bypass_lo_hi_hi = {_entries_barrier_5_io_y_ae_stage2, _entries_barrier_4_io_y_ae_stage2}; // @[package.scala:45:27, :267:25] wire [2:0] stage1_bypass_lo_hi = {stage1_bypass_lo_hi_hi, _entries_barrier_3_io_y_ae_stage2}; // @[package.scala:45:27, :267:25] wire [5:0] stage1_bypass_lo = {stage1_bypass_lo_hi, stage1_bypass_lo_lo}; // @[package.scala:45:27] wire [1:0] stage1_bypass_hi_lo_hi = {_entries_barrier_8_io_y_ae_stage2, _entries_barrier_7_io_y_ae_stage2}; // @[package.scala:45:27, :267:25] wire [2:0] stage1_bypass_hi_lo = {stage1_bypass_hi_lo_hi, _entries_barrier_6_io_y_ae_stage2}; // @[package.scala:45:27, :267:25] wire [1:0] stage1_bypass_hi_hi_lo = {_entries_barrier_10_io_y_ae_stage2, _entries_barrier_9_io_y_ae_stage2}; // @[package.scala:45:27, :267:25] wire [1:0] stage1_bypass_hi_hi_hi = {_entries_barrier_12_io_y_ae_stage2, _entries_barrier_11_io_y_ae_stage2}; // @[package.scala:45:27, :267:25] wire [3:0] stage1_bypass_hi_hi = {stage1_bypass_hi_hi_hi, stage1_bypass_hi_hi_lo}; // @[package.scala:45:27] wire [6:0] stage1_bypass_hi = {stage1_bypass_hi_hi, stage1_bypass_hi_lo}; // @[package.scala:45:27] wire [12:0] _stage1_bypass_T_3 = {stage1_bypass_hi, stage1_bypass_lo}; // @[package.scala:45:27] wire [12:0] _stage1_bypass_T_4 = _stage1_bypass_T_2 \| _stage1_bypass_T_3; // @[package.scala:45:27] wire [1:0] r_array_lo_lo_hi = {_entries_barrier_2_io_y_sr, _entries_barrier_1_io_y_sr}; // @[package.scala:45:27, :267:25] wire [2:0] r_array_lo_lo = {r_array_lo_lo_hi, _entries_barrier_io_y_sr}; // @[package.scala:45:27, :267:25] wire [1:0] r_array_lo_hi_hi = {_entries_barrier_5_io_y_sr, _entries_barrier_4_io_y_sr}; // @[package.scala:45:27, :267:25] wire [2:0] r_array_lo_hi = {r_array_lo_hi_hi, _entries_barrier_3_io_y_sr}; // @[package.scala:45:27, :267:25] wire [5:0] r_array_lo = {r_array_lo_hi, r_array_lo_lo}; // @[package.scala:45:27] wire [1:0] r_array_hi_lo_hi = {_entries_barrier_8_io_y_sr, _entries_barrier_7_io_y_sr}; // @[package.scala:45:27, :267:25] wire [2:0] r_array_hi_lo = {r_array_hi_lo_hi, _entries_barrier_6_io_y_sr}; // @[package.scala:45:27, :267:25] wire [1:0] r_array_hi_hi_lo = {_entries_barrier_10_io_y_sr, _entries_barrier_9_io_y_sr}; // @[package.scala:45:27, :267:25] wire [1:0] r_array_hi_hi_hi = {_entries_barrier_12_io_y_sr, _entries_barrier_11_io_y_sr}; // @[package.scala:45:27, :267:25] wire [3:0] r_array_hi_hi = {r_array_hi_hi_hi, r_array_hi_hi_lo}; // @[package.scala:45:27] wire [6:0] r_array_hi = {r_array_hi_hi, r_array_hi_lo}; // @[package.scala:45:27] wire [12:0] _r_array_T = {r_array_hi, r_array_lo}; // @[package.scala:45:27] wire [1:0] _GEN_45 = {_entries_barrier_2_io_y_sx, _entries_barrier_1_io_y_sx}; // @[package.scala:45:27, :267:25] wire [1:0] r_array_lo_lo_hi_1; // @[package.scala:45:27] assign r_array_lo_lo_hi_1 = _GEN_45; // @[package.scala:45:27] wire [1:0] x_array_lo_lo_hi; // @[package.scala:45:27] assign x_array_lo_lo_hi = _GEN_45; // @[package.scala:45:27] wire [2:0] r_array_lo_lo_1 = {r_array_lo_lo_hi_1, _entries_barrier_io_y_sx}; // @[package.scala:45:27, :267:25] wire [1:0] _GEN_46 = {_entries_barrier_5_io_y_sx, _entries_barrier_4_io_y_sx}; // @[package.scala:45:27, :267:25] wire [1:0] r_array_lo_hi_hi_1; // @[package.scala:45:27] assign r_array_lo_hi_hi_1 = _GEN_46; // @[package.scala:45:27] wire [1:0] x_array_lo_hi_hi; // @[package.scala:45:27] assign x_array_lo_hi_hi = _GEN_46; // @[package.scala:45:27] wire [2:0] r_array_lo_hi_1 = {r_array_lo_hi_hi_1, _entries_barrier_3_io_y_sx}; // @[package.scala:45:27, :267:25] wire [5:0] r_array_lo_1 = {r_array_lo_hi_1, r_array_lo_lo_1}; // @[package.scala:45:27] wire [1:0] _GEN_47 = {_entries_barrier_8_io_y_sx, _entries_barrier_7_io_y_sx}; // @[package.scala:45:27, :267:25] wire [1:0] r_array_hi_lo_hi_1; // @[package.scala:45:27] assign r_array_hi_lo_hi_1 = _GEN_47; // @[package.scala:45:27] wire [1:0] x_array_hi_lo_hi; // @[package.scala:45:27] assign x_array_hi_lo_hi = _GEN_47; // @[package.scala:45:27] wire [2:0] r_array_hi_lo_1 = {r_array_hi_lo_hi_1, _entries_barrier_6_io_y_sx}; // @[package.scala:45:27, :267:25] wire [1:0] _GEN_48 = {_entries_barrier_10_io_y_sx, _entries_barrier_9_io_y_sx}; // @[package.scala:45:27, :267:25] wire [1:0] r_array_hi_hi_lo_1; // @[package.scala:45:27] assign r_array_hi_hi_lo_1 = _GEN_48; // @[package.scala:45:27] wire [1:0] x_array_hi_hi_lo; // @[package.scala:45:27] assign x_array_hi_hi_lo = _GEN_48; // @[package.scala:45:27] wire [1:0] _GEN_49 = {_entries_barrier_12_io_y_sx, _entries_barrier_11_io_y_sx}; // @[package.scala:45:27, :267:25] wire [1:0] r_array_hi_hi_hi_1; // @[package.scala:45:27] assign r_array_hi_hi_hi_1 = _GEN_49; // @[package.scala:45:27] wire [1:0] x_array_hi_hi_hi; // @[package.scala:45:27] assign x_array_hi_hi_hi = _GEN_49; // @[package.scala:45:27] wire [3:0] r_array_hi_hi_1 = {r_array_hi_hi_hi_1, r_array_hi_hi_lo_1}; // @[package.scala:45:27] wire [6:0] r_array_hi_1 = {r_array_hi_hi_1, r_array_hi_lo_1}; // @[package.scala:45:27] wire [12:0] _r_array_T_1 = {r_array_hi_1, r_array_lo_1}; // @[package.scala:45:27] wire [12:0] _r_array_T_2 = mxr ? _r_array_T_1 : 13'h0; // @[package.scala:45:27] wire [12:0] _r_array_T_3 = _r_array_T \| _r_array_T_2; // @[package.scala:45:27] wire [12:0] _r_array_T_4 = priv_rw_ok & _r_array_T_3; // @[TLB.scala:513:70, :520:{41,69}] wire [12:0] _r_array_T_5 = _r_array_T_4; // @[TLB.scala:520:{41,113}] wire [13:0] r_array = {1'h1, _r_array_T_5}; // @[TLB.scala:520:{20,113}] wire [13:0] _pf_ld_array_T = r_array; // @[TLB.scala:520:20, :597:41] wire [1:0] w_array_lo_lo_hi = {_entries_barrier_2_io_y_sw, _entries_barrier_1_io_y_sw}; // @[package.scala:45:27, :267:25] wire [2:0] w_array_lo_lo = {w_array_lo_lo_hi, _entries_barrier_io_y_sw}; // @[package.scala:45:27, :267:25] wire [1:0] w_array_lo_hi_hi = {_entries_barrier_5_io_y_sw, _entries_barrier_4_io_y_sw}; // @[package.scala:45:27, :267:25] wire [2:0] w_array_lo_hi = {w_array_lo_hi_hi, _entries_barrier_3_io_y_sw}; // @[package.scala:45:27, :267:25] wire [5:0] w_array_lo = {w_array_lo_hi, w_array_lo_lo}; // @[package.scala:45:27] wire [1:0] w_array_hi_lo_hi = {_entries_barrier_8_io_y_sw, _entries_barrier_7_io_y_sw}; // @[package.scala:45:27, :267:25] wire [2:0] w_array_hi_lo = {w_array_hi_lo_hi, _entries_barrier_6_io_y_sw}; // @[package.scala:45:27, :267:25] wire [1:0] w_array_hi_hi_lo = {_entries_barrier_10_io_y_sw, _entries_barrier_9_io_y_sw}; // @[package.scala:45:27, :267:25] wire [1:0] w_array_hi_hi_hi = {_entries_barrier_12_io_y_sw, _entries_barrier_11_io_y_sw}; // @[package.scala:45:27, :267:25] wire [3:0] w_array_hi_hi = {w_array_hi_hi_hi, w_array_hi_hi_lo}; // @[package.scala:45:27] wire [6:0] w_array_hi = {w_array_hi_hi, w_array_hi_lo}; // @[package.scala:45:27] wire [12:0] _w_array_T = {w_array_hi, w_array_lo}; // @[package.scala:45:27] wire [12:0] _w_array_T_1 = priv_rw_ok & _w_array_T; // @[package.scala:45:27] wire [12:0] _w_array_T_2 = _w_array_T_1; // @[TLB.scala:521:{41,69}] wire [13:0] w_array = {1'h1, _w_array_T_2}; // @[TLB.scala:521:{20,69}] wire [2:0] x_array_lo_lo = {x_array_lo_lo_hi, _entries_barrier_io_y_sx}; // @[package.scala:45:27, :267:25] wire [2:0] x_array_lo_hi = {x_array_lo_hi_hi, _entries_barrier_3_io_y_sx}; // @[package.scala:45:27, :267:25] wire [5:0] x_array_lo = {x_array_lo_hi, x_array_lo_lo}; // @[package.scala:45:27] wire [2:0] x_array_hi_lo = {x_array_hi_lo_hi, _entries_barrier_6_io_y_sx}; // @[package.scala:45:27, :267:25] wire [3:0] x_array_hi_hi = {x_array_hi_hi_hi, x_array_hi_hi_lo}; // @[package.scala:45:27] wire [6:0] x_array_hi = {x_array_hi_hi, x_array_hi_lo}; // @[package.scala:45:27] wire [12:0] _x_array_T = {x_array_hi, x_array_lo}; // @[package.scala:45:27] wire [12:0] _x_array_T_1 = priv_x_ok & _x_array_T; // @[package.scala:45:27] wire [12:0] _x_array_T_2 = _x_array_T_1; // @[TLB.scala:522:{40,68}] wire [13:0] x_array = {1'h1, _x_array_T_2}; // @[TLB.scala:522:{20,68}] wire [1:0] hr_array_lo_lo_hi = {_entries_barrier_2_io_y_hr, _entries_barrier_1_io_y_hr}; // @[package.scala:45:27, :267:25] wire [2:0] hr_array_lo_lo = {hr_array_lo_lo_hi, _entries_barrier_io_y_hr}; // @[package.scala:45:27, :267:25] wire [1:0] hr_array_lo_hi_hi = {_entries_barrier_5_io_y_hr, _entries_barrier_4_io_y_hr}; // @[package.scala:45:27, :267:25] wire [2:0] hr_array_lo_hi = {hr_array_lo_hi_hi, _entries_barrier_3_io_y_hr}; // @[package.scala:45:27, :267:25] wire [5:0] hr_array_lo = {hr_array_lo_hi, hr_array_lo_lo}; // @[package.scala:45:27] wire [1:0] hr_array_hi_lo_hi = {_entries_barrier_8_io_y_hr, _entries_barrier_7_io_y_hr}; // @[package.scala:45:27, :267:25] wire [2:0] hr_array_hi_lo = {hr_array_hi_lo_hi, _entries_barrier_6_io_y_hr}; // @[package.scala:45:27, :267:25] wire [1:0] hr_array_hi_hi_lo = {_entries_barrier_10_io_y_hr, _entries_barrier_9_io_y_hr}; // @[package.scala:45:27, :267:25] wire [1:0] hr_array_hi_hi_hi = {_entries_barrier_12_io_y_hr, _entries_barrier_11_io_y_hr}; // @[package.scala:45:27, :267:25] wire [3:0] hr_array_hi_hi = {hr_array_hi_hi_hi, hr_array_hi_hi_lo}; // @[package.scala:45:27] wire [6:0] hr_array_hi = {hr_array_hi_hi, hr_array_hi_lo}; // @[package.scala:45:27] wire [12:0] _hr_array_T = {hr_array_hi, hr_array_lo}; // @[package.scala:45:27] wire [1:0] _GEN_50 = {_entries_barrier_2_io_y_hx, _entries_barrier_1_io_y_hx}; // @[package.scala:45:27, :267:25] wire [1:0] hr_array_lo_lo_hi_1; // @[package.scala:45:27] assign hr_array_lo_lo_hi_1 = _GEN_50; // @[package.scala:45:27] wire [1:0] hx_array_lo_lo_hi; // @[package.scala:45:27] assign hx_array_lo_lo_hi = _GEN_50; // @[package.scala:45:27] wire [2:0] hr_array_lo_lo_1 = {hr_array_lo_lo_hi_1, _entries_barrier_io_y_hx}; // @[package.scala:45:27, :267:25] wire [1:0] _GEN_51 = {_entries_barrier_5_io_y_hx, _entries_barrier_4_io_y_hx}; // @[package.scala:45:27, :267:25] wire [1:0] hr_array_lo_hi_hi_1; // @[package.scala:45:27] assign hr_array_lo_hi_hi_1 = _GEN_51; // @[package.scala:45:27] wire [1:0] hx_array_lo_hi_hi; // @[package.scala:45:27] assign hx_array_lo_hi_hi = _GEN_51; // @[package.scala:45:27] wire [2:0] hr_array_lo_hi_1 = {hr_array_lo_hi_hi_1, _entries_barrier_3_io_y_hx}; // @[package.scala:45:27, :267:25] wire [5:0] hr_array_lo_1 = {hr_array_lo_hi_1, hr_array_lo_lo_1}; // @[package.scala:45:27] wire [1:0] _GEN_52 = {_entries_barrier_8_io_y_hx, _entries_barrier_7_io_y_hx}; // @[package.scala:45:27, :267:25] wire [1:0] hr_array_hi_lo_hi_1; // @[package.scala:45:27] assign hr_array_hi_lo_hi_1 = _GEN_52; // @[package.scala:45:27] wire [1:0] hx_array_hi_lo_hi; // @[package.scala:45:27] assign hx_array_hi_lo_hi = _GEN_52; // @[package.scala:45:27] wire [2:0] hr_array_hi_lo_1 = {hr_array_hi_lo_hi_1, _entries_barrier_6_io_y_hx}; // @[package.scala:45:27, :267:25] wire [1:0] _GEN_53 = {_entries_barrier_10_io_y_hx, _entries_barrier_9_io_y_hx}; // @[package.scala:45:27, :267:25] wire [1:0] hr_array_hi_hi_lo_1; // @[package.scala:45:27] assign hr_array_hi_hi_lo_1 = _GEN_53; // @[package.scala:45:27] wire [1:0] hx_array_hi_hi_lo; // @[package.scala:45:27] assign hx_array_hi_hi_lo = _GEN_53; // @[package.scala:45:27] wire [1:0] _GEN_54 = {_entries_barrier_12_io_y_hx, _entries_barrier_11_io_y_hx}; // @[package.scala:45:27, :267:25] wire [1:0] hr_array_hi_hi_hi_1; // @[package.scala:45:27] assign hr_array_hi_hi_hi_1 = _GEN_54; // @[package.scala:45:27] wire [1:0] hx_array_hi_hi_hi; // @[package.scala:45:27] assign hx_array_hi_hi_hi = _GEN_54; // @[package.scala:45:27] wire [3:0] hr_array_hi_hi_1 = {hr_array_hi_hi_hi_1, hr_array_hi_hi_lo_1}; // @[package.scala:45:27] wire [6:0] hr_array_hi_1 = {hr_array_hi_hi_1, hr_array_hi_lo_1}; // @[package.scala:45:27] wire [12:0] _hr_array_T_1 = {hr_array_hi_1, hr_array_lo_1}; // @[package.scala:45:27] wire [12:0] _hr_array_T_2 = io_ptw_status_mxr_0 ? _hr_array_T_1 : 13'h0; // @[package.scala:45:27] wire [12:0] _hr_array_T_3 = _hr_array_T \| _hr_array_T_2; // @[package.scala:45:27] wire [1:0] hw_array_lo_lo_hi = {_entries_barrier_2_io_y_hw, _entries_barrier_1_io_y_hw}; // @[package.scala:45:27, :267:25] wire [2:0] hw_array_lo_lo = {hw_array_lo_lo_hi, _entries_barrier_io_y_hw}; // @[package.scala:45:27, :267:25] wire [1:0] hw_array_lo_hi_hi = {_entries_barrier_5_io_y_hw, _entries_barrier_4_io_y_hw}; // @[package.scala:45:27, :267:25] wire [2:0] hw_array_lo_hi = {hw_array_lo_hi_hi, _entries_barrier_3_io_y_hw}; // @[package.scala:45:27, :267:25] wire [5:0] hw_array_lo = {hw_array_lo_hi, hw_array_lo_lo}; // @[package.scala:45:27] wire [1:0] hw_array_hi_lo_hi = {_entries_barrier_8_io_y_hw, _entries_barrier_7_io_y_hw}; // @[package.scala:45:27, :267:25] wire [2:0] hw_array_hi_lo = {hw_array_hi_lo_hi, _entries_barrier_6_io_y_hw}; // @[package.scala:45:27, :267:25] wire [1:0] hw_array_hi_hi_lo = {_entries_barrier_10_io_y_hw, _entries_barrier_9_io_y_hw}; // @[package.scala:45:27, :267:25] wire [1:0] hw_array_hi_hi_hi = {_entries_barrier_12_io_y_hw, _entries_barrier_11_io_y_hw}; // @[package.scala:45:27, :267:25] wire [3:0] hw_array_hi_hi = {hw_array_hi_hi_hi, hw_array_hi_hi_lo}; // @[package.scala:45:27] wire [6:0] hw_array_hi = {hw_array_hi_hi, hw_array_hi_lo}; // @[package.scala:45:27] wire [12:0] _hw_array_T = {hw_array_hi, hw_array_lo}; // @[package.scala:45:27] wire [2:0] hx_array_lo_lo = {hx_array_lo_lo_hi, _entries_barrier_io_y_hx}; // @[package.scala:45:27, :267:25] wire [2:0] hx_array_lo_hi = {hx_array_lo_hi_hi, _entries_barrier_3_io_y_hx}; // @[package.scala:45:27, :267:25] wire [5:0] hx_array_lo = {hx_array_lo_hi, hx_array_lo_lo}; // @[package.scala:45:27] wire [2:0] hx_array_hi_lo = {hx_array_hi_lo_hi, _entries_barrier_6_io_y_hx}; // @[package.scala:45:27, :267:25] wire [3:0] hx_array_hi_hi = {hx_array_hi_hi_hi, hx_array_hi_hi_lo}; // @[package.scala:45:27] wire [6:0] hx_array_hi = {hx_array_hi_hi, hx_array_hi_lo}; // @[package.scala:45:27] wire [12:0] _hx_array_T = {hx_array_hi, hx_array_lo}; // @[package.scala:45:27] wire [1:0] _pr_array_T = {2{prot_r}}; // @[TLB.scala:429:55, :529:26] wire [1:0] pr_array_lo_lo_hi = {_entries_barrier_2_io_y_pr, _entries_barrier_1_io_y_pr}; // @[package.scala:45:27, :267:25] wire [2:0] pr_array_lo_lo = {pr_array_lo_lo_hi, _entries_barrier_io_y_pr}; // @[package.scala:45:27, :267:25] wire [1:0] pr_array_lo_hi_hi = {_entries_barrier_5_io_y_pr, _entries_barrier_4_io_y_pr}; // @[package.scala:45:27, :267:25] wire [2:0] pr_array_lo_hi = {pr_array_lo_hi_hi, _entries_barrier_3_io_y_pr}; // @[package.scala:45:27, :267:25] wire [5:0] pr_array_lo = {pr_array_lo_hi, pr_array_lo_lo}; // @[package.scala:45:27] wire [1:0] pr_array_hi_lo_hi = {_entries_barrier_8_io_y_pr, _entries_barrier_7_io_y_pr}; // @[package.scala:45:27, :267:25] wire [2:0] pr_array_hi_lo = {pr_array_hi_lo_hi, _entries_barrier_6_io_y_pr}; // @[package.scala:45:27, :267:25] wire [1:0] pr_array_hi_hi_hi = {_entries_barrier_11_io_y_pr, _entries_barrier_10_io_y_pr}; // @[package.scala:45:27, :267:25] wire [2:0] pr_array_hi_hi = {pr_array_hi_hi_hi, _entries_barrier_9_io_y_pr}; // @[package.scala:45:27, :267:25] wire [5:0] pr_array_hi = {pr_array_hi_hi, pr_array_hi_lo}; // @[package.scala:45:27] wire [11:0] _pr_array_T_1 = {pr_array_hi, pr_array_lo}; // @[package.scala:45:27] wire [13:0] _pr_array_T_2 = {_pr_array_T, _pr_array_T_1}; // @[package.scala:45:27] wire [13:0] _GEN_55 = ptw_ae_array \| final_ae_array; // @[TLB.scala:506:25, :507:27, :529:104] wire [13:0] _pr_array_T_3; // @[TLB.scala:529:104] assign _pr_array_T_3 = _GEN_55; // @[TLB.scala:529:104] wire [13:0] _pw_array_T_3; // @[TLB.scala:531:104] assign _pw_array_T_3 = _GEN_55; // @[TLB.scala:529:104, :531:104] wire [13:0] _px_array_T_3; // @[TLB.scala:533:104] assign _px_array_T_3 = _GEN_55; // @[TLB.scala:529:104, :533:104] wire [13:0] _pr_array_T_4 = ~_pr_array_T_3; // @[TLB.scala:529:{89,104}] wire [13:0] pr_array = _pr_array_T_2 & _pr_array_T_4; // @[TLB.scala:529:{21,87,89}] wire [1:0] _pw_array_T = {2{prot_w}}; // @[TLB.scala:430:55, :531:26] wire [1:0] pw_array_lo_lo_hi = {_entries_barrier_2_io_y_pw, _entries_barrier_1_io_y_pw}; // @[package.scala:45:27, :267:25] wire [2:0] pw_array_lo_lo = {pw_array_lo_lo_hi, _entries_barrier_io_y_pw}; // @[package.scala:45:27, :267:25] wire [1:0] pw_array_lo_hi_hi = {_entries_barrier_5_io_y_pw, _entries_barrier_4_io_y_pw}; // @[package.scala:45:27, :267:25] wire [2:0] pw_array_lo_hi = {pw_array_lo_hi_hi, _entries_barrier_3_io_y_pw}; // @[package.scala:45:27, :267:25] wire [5:0] pw_array_lo = {pw_array_lo_hi, pw_array_lo_lo}; // @[package.scala:45:27] wire [1:0] pw_array_hi_lo_hi = {_entries_barrier_8_io_y_pw, _entries_barrier_7_io_y_pw}; // @[package.scala:45:27, :267:25] wire [2:0] pw_array_hi_lo = {pw_array_hi_lo_hi, _entries_barrier_6_io_y_pw}; // @[package.scala:45:27, :267:25] wire [1:0] pw_array_hi_hi_hi = {_entries_barrier_11_io_y_pw, _entries_barrier_10_io_y_pw}; // @[package.scala:45:27, :267:25] wire [2:0] pw_array_hi_hi = {pw_array_hi_hi_hi, _entries_barrier_9_io_y_pw}; // @[package.scala:45:27, :267:25] wire [5:0] pw_array_hi = {pw_array_hi_hi, pw_array_hi_lo}; // @[package.scala:45:27] wire [11:0] _pw_array_T_1 = {pw_array_hi, pw_array_lo}; // @[package.scala:45:27] wire [13:0] _pw_array_T_2 = {_pw_array_T, _pw_array_T_1}; // @[package.scala:45:27] wire [13:0] _pw_array_T_4 = ~_pw_array_T_3; // @[TLB.scala:531:{89,104}] wire [13:0] pw_array = _pw_array_T_2 & _pw_array_T_4; // @[TLB.scala:531:{21,87,89}] wire [1:0] _px_array_T = {2{prot_x}}; // @[TLB.scala:434:55, :533:26] wire [1:0] px_array_lo_lo_hi = {_entries_barrier_2_io_y_px, _entries_barrier_1_io_y_px}; // @[package.scala:45:27, :267:25] wire [2:0] px_array_lo_lo = {px_array_lo_lo_hi, _entries_barrier_io_y_px}; // @[package.scala:45:27, :267:25] wire [1:0] px_array_lo_hi_hi = {_entries_barrier_5_io_y_px, _entries_barrier_4_io_y_px}; // @[package.scala:45:27, :267:25] wire [2:0] px_array_lo_hi = {px_array_lo_hi_hi, _entries_barrier_3_io_y_px}; // @[package.scala:45:27, :267:25] wire [5:0] px_array_lo = {px_array_lo_hi, px_array_lo_lo}; // @[package.scala:45:27] wire [1:0] px_array_hi_lo_hi = {_entries_barrier_8_io_y_px, _entries_barrier_7_io_y_px}; // @[package.scala:45:27, :267:25] wire [2:0] px_array_hi_lo = {px_array_hi_lo_hi, _entries_barrier_6_io_y_px}; // @[package.scala:45:27, :267:25] wire [1:0] px_array_hi_hi_hi = {_entries_barrier_11_io_y_px, _entries_barrier_10_io_y_px}; // @[package.scala:45:27, :267:25] wire [2:0] px_array_hi_hi = {px_array_hi_hi_hi, _entries_barrier_9_io_y_px}; // @[package.scala:45:27, :267:25] wire [5:0] px_array_hi = {px_array_hi_hi, px_array_hi_lo}; // @[package.scala:45:27] wire [11:0] _px_array_T_1 = {px_array_hi, px_array_lo}; // @[package.scala:45:27] wire [13:0] _px_array_T_2 = {_px_array_T, _px_array_T_1}; // @[package.scala:45:27] wire [13:0] _px_array_T_4 = ~_px_array_T_3; // @[TLB.scala:533:{89,104}] wire [13:0] px_array = _px_array_T_2 & _px_array_T_4; // @[TLB.scala:533:{21,87,89}] wire [1:0] _eff_array_T = {2{_pma_io_resp_eff}}; // @[TLB.scala:422:19, :535:27] wire [1:0] eff_array_lo_lo_hi = {_entries_barrier_2_io_y_eff, _entries_barrier_1_io_y_eff}; // @[package.scala:45:27, :267:25] wire [2:0] eff_array_lo_lo = {eff_array_lo_lo_hi, _entries_barrier_io_y_eff}; // @[package.scala:45:27, :267:25] wire [1:0] eff_array_lo_hi_hi = {_entries_barrier_5_io_y_eff, _entries_barrier_4_io_y_eff}; // @[package.scala:45:27, :267:25] wire [2:0] eff_array_lo_hi = {eff_array_lo_hi_hi, _entries_barrier_3_io_y_eff}; // @[package.scala:45:27, :267:25] wire [5:0] eff_array_lo = {eff_array_lo_hi, eff_array_lo_lo}; // @[package.scala:45:27] wire [1:0] eff_array_hi_lo_hi = {_entries_barrier_8_io_y_eff, _entries_barrier_7_io_y_eff}; // @[package.scala:45:27, :267:25] wire [2:0] eff_array_hi_lo = {eff_array_hi_lo_hi, _entries_barrier_6_io_y_eff}; // @[package.scala:45:27, :267:25] wire [1:0] eff_array_hi_hi_hi = {_entries_barrier_11_io_y_eff, _entries_barrier_10_io_y_eff}; // @[package.scala:45:27, :267:25] wire [2:0] eff_array_hi_hi = {eff_array_hi_hi_hi, _entries_barrier_9_io_y_eff}; // @[package.scala:45:27, :267:25] wire [5:0] eff_array_hi = {eff_array_hi_hi, eff_array_hi_lo}; // @[package.scala:45:27] wire [11:0] _eff_array_T_1 = {eff_array_hi, eff_array_lo}; // @[package.scala:45:27] wire [13:0] eff_array = {_eff_array_T, _eff_array_T_1}; // @[package.scala:45:27] wire [1:0] _c_array_T = {2{cacheable}}; // @[TLB.scala:425:41, :537:25] wire [1:0] _GEN_56 = {_entries_barrier_2_io_y_c, _entries_barrier_1_io_y_c}; // @[package.scala:45:27, :267:25] wire [1:0] c_array_lo_lo_hi; // @[package.scala:45:27] assign c_array_lo_lo_hi = _GEN_56; // @[package.scala:45:27] wire [1:0] prefetchable_array_lo_lo_hi; // @[package.scala:45:27] assign prefetchable_array_lo_lo_hi = _GEN_56; // @[package.scala:45:27] wire [2:0] c_array_lo_lo = {c_array_lo_lo_hi, _entries_barrier_io_y_c}; // @[package.scala:45:27, :267:25] wire [1:0] _GEN_57 = {_entries_barrier_5_io_y_c, _entries_barrier_4_io_y_c}; // @[package.scala:45:27, :267:25] wire [1:0] c_array_lo_hi_hi; // @[package.scala:45:27] assign c_array_lo_hi_hi = _GEN_57; // @[package.scala:45:27] wire [1:0] prefetchable_array_lo_hi_hi; // @[package.scala:45:27] assign prefetchable_array_lo_hi_hi = _GEN_57; // @[package.scala:45:27] wire [2:0] c_array_lo_hi = {c_array_lo_hi_hi, _entries_barrier_3_io_y_c}; // @[package.scala:45:27, :267:25] wire [5:0] c_array_lo = {c_array_lo_hi, c_array_lo_lo}; // @[package.scala:45:27] wire [1:0] _GEN_58 = {_entries_barrier_8_io_y_c, _entries_barrier_7_io_y_c}; // @[package.scala:45:27, :267:25] wire [1:0] c_array_hi_lo_hi; // @[package.scala:45:27] assign c_array_hi_lo_hi = _GEN_58; // @[package.scala:45:27] wire [1:0] prefetchable_array_hi_lo_hi; // @[package.scala:45:27] assign prefetchable_array_hi_lo_hi = _GEN_58; // @[package.scala:45:27] wire [2:0] c_array_hi_lo = {c_array_hi_lo_hi, _entries_barrier_6_io_y_c}; // @[package.scala:45:27, :267:25] wire [1:0] _GEN_59 = {_entries_barrier_11_io_y_c, _entries_barrier_10_io_y_c}; // @[package.scala:45:27, :267:25] wire [1:0] c_array_hi_hi_hi; // @[package.scala:45:27] assign c_array_hi_hi_hi = _GEN_59; // @[package.scala:45:27] wire [1:0] prefetchable_array_hi_hi_hi; // @[package.scala:45:27] assign prefetchable_array_hi_hi_hi = _GEN_59; // @[package.scala:45:27] wire [2:0] c_array_hi_hi = {c_array_hi_hi_hi, _entries_barrier_9_io_y_c}; // @[package.scala:45:27, :267:25] wire [5:0] c_array_hi = {c_array_hi_hi, c_array_hi_lo}; // @[package.scala:45:27] wire [11:0] _c_array_T_1 = {c_array_hi, c_array_lo}; // @[package.scala:45:27] wire [13:0] c_array = {_c_array_T, _c_array_T_1}; // @[package.scala:45:27] wire [13:0] lrscAllowed = c_array; // @[TLB.scala:537:20, :580:24] wire [1:0] _ppp_array_T = {2{_pma_io_resp_pp}}; // @[TLB.scala:422:19, :539:27] wire [1:0] ppp_array_lo_lo_hi = {_entries_barrier_2_io_y_ppp, _entries_barrier_1_io_y_ppp}; // @[package.scala:45:27, :267:25] wire [2:0] ppp_array_lo_lo = {ppp_array_lo_lo_hi, _entries_barrier_io_y_ppp}; // @[package.scala:45:27, :267:25] wire [1:0] ppp_array_lo_hi_hi = {_entries_barrier_5_io_y_ppp, _entries_barrier_4_io_y_ppp}; // @[package.scala:45:27, :267:25] wire [2:0] ppp_array_lo_hi = {ppp_array_lo_hi_hi, _entries_barrier_3_io_y_ppp}; // @[package.scala:45:27, :267:25] wire [5:0] ppp_array_lo = {ppp_array_lo_hi, ppp_array_lo_lo}; // @[package.scala:45:27] wire [1:0] ppp_array_hi_lo_hi = {_entries_barrier_8_io_y_ppp, _entries_barrier_7_io_y_ppp}; // @[package.scala:45:27, :267:25] wire [2:0] ppp_array_hi_lo = {ppp_array_hi_lo_hi, _entries_barrier_6_io_y_ppp}; // @[package.scala:45:27, :267:25] wire [1:0] ppp_array_hi_hi_hi = {_entries_barrier_11_io_y_ppp, _entries_barrier_10_io_y_ppp}; // @[package.scala:45:27, :267:25] wire [2:0] ppp_array_hi_hi = {ppp_array_hi_hi_hi, _entries_barrier_9_io_y_ppp}; // @[package.scala:45:27, :267:25] wire [5:0] ppp_array_hi = {ppp_array_hi_hi, ppp_array_hi_lo}; // @[package.scala:45:27] wire [11:0] _ppp_array_T_1 = {ppp_array_hi, ppp_array_lo}; // @[package.scala:45:27] wire [13:0] ppp_array = {_ppp_array_T, _ppp_array_T_1}; // @[package.scala:45:27] wire [1:0] _paa_array_T = {2{_pma_io_resp_aa}}; // @[TLB.scala:422:19, :541:27] wire [1:0] paa_array_lo_lo_hi = {_entries_barrier_2_io_y_paa, _entries_barrier_1_io_y_paa}; // @[package.scala:45:27, :267:25] wire [2:0] paa_array_lo_lo = {paa_array_lo_lo_hi, _entries_barrier_io_y_paa}; // @[package.scala:45:27, :267:25] wire [1:0] paa_array_lo_hi_hi = {_entries_barrier_5_io_y_paa, _entries_barrier_4_io_y_paa}; // @[package.scala:45:27, :267:25] wire [2:0] paa_array_lo_hi = {paa_array_lo_hi_hi, _entries_barrier_3_io_y_paa}; // @[package.scala:45:27, :267:25] wire [5:0] paa_array_lo = {paa_array_lo_hi, paa_array_lo_lo}; // @[package.scala:45:27] wire [1:0] paa_array_hi_lo_hi = {_entries_barrier_8_io_y_paa, _entries_barrier_7_io_y_paa}; // @[package.scala:45:27, :267:25] wire [2:0] paa_array_hi_lo = {paa_array_hi_lo_hi, _entries_barrier_6_io_y_paa}; // @[package.scala:45:27, :267:25] wire [1:0] paa_array_hi_hi_hi = {_entries_barrier_11_io_y_paa, _entries_barrier_10_io_y_paa}; // @[package.scala:45:27, :267:25] wire [2:0] paa_array_hi_hi = {paa_array_hi_hi_hi, _entries_barrier_9_io_y_paa}; // @[package.scala:45:27, :267:25] wire [5:0] paa_array_hi = {paa_array_hi_hi, paa_array_hi_lo}; // @[package.scala:45:27] wire [11:0] _paa_array_T_1 = {paa_array_hi, paa_array_lo}; // @[package.scala:45:27] wire [13:0] paa_array = {_paa_array_T, _paa_array_T_1}; // @[package.scala:45:27] wire [1:0] _pal_array_T = {2{_pma_io_resp_al}}; // @[TLB.scala:422:19, :543:27] wire [1:0] pal_array_lo_lo_hi = {_entries_barrier_2_io_y_pal, _entries_barrier_1_io_y_pal}; // @[package.scala:45:27, :267:25] wire [2:0] pal_array_lo_lo = {pal_array_lo_lo_hi, _entries_barrier_io_y_pal}; // @[package.scala:45:27, :267:25] wire [1:0] pal_array_lo_hi_hi = {_entries_barrier_5_io_y_pal, _entries_barrier_4_io_y_pal}; // @[package.scala:45:27, :267:25] wire [2:0] pal_array_lo_hi = {pal_array_lo_hi_hi, _entries_barrier_3_io_y_pal}; // @[package.scala:45:27, :267:25] wire [5:0] pal_array_lo = {pal_array_lo_hi, pal_array_lo_lo}; // @[package.scala:45:27] wire [1:0] pal_array_hi_lo_hi = {_entries_barrier_8_io_y_pal, _entries_barrier_7_io_y_pal}; // @[package.scala:45:27, :267:25] wire [2:0] pal_array_hi_lo = {pal_array_hi_lo_hi, _entries_barrier_6_io_y_pal}; // @[package.scala:45:27, :267:25] wire [1:0] pal_array_hi_hi_hi = {_entries_barrier_11_io_y_pal, _entries_barrier_10_io_y_pal}; // @[package.scala:45:27, :267:25] wire [2:0] pal_array_hi_hi = {pal_array_hi_hi_hi, _entries_barrier_9_io_y_pal}; // @[package.scala:45:27, :267:25] wire [5:0] pal_array_hi = {pal_array_hi_hi, pal_array_hi_lo}; // @[package.scala:45:27] wire [11:0] _pal_array_T_1 = {pal_array_hi, pal_array_lo}; // @[package.scala:45:27] wire [13:0] pal_array = {_pal_array_T, _pal_array_T_1}; // @[package.scala:45:27] wire [13:0] ppp_array_if_cached = ppp_array \| c_array; // @[TLB.scala:537:20, :539:22, :544:39] wire [13:0] paa_array_if_cached = paa_array \| c_array; // @[TLB.scala:537:20, :541:22, :545:39] wire [13:0] pal_array_if_cached = pal_array \| c_array; // @[TLB.scala:537:20, :543:22, :546:39] wire _prefetchable_array_T = cacheable & homogeneous; // @[TLBPermissions.scala:101:65] wire [1:0] _prefetchable_array_T_1 = {_prefetchable_array_T, 1'h0}; // @[TLB.scala:547:{43,59}] wire [2:0] prefetchable_array_lo_lo = {prefetchable_array_lo_lo_hi, _entries_barrier_io_y_c}; // @[package.scala:45:27, :267:25] wire [2:0] prefetchable_array_lo_hi = {prefetchable_array_lo_hi_hi, _entries_barrier_3_io_y_c}; // @[package.scala:45:27, :267:25] wire [5:0] prefetchable_array_lo = {prefetchable_array_lo_hi, prefetchable_array_lo_lo}; // @[package.scala:45:27] wire [2:0] prefetchable_array_hi_lo = {prefetchable_array_hi_lo_hi, _entries_barrier_6_io_y_c}; // @[package.scala:45:27, :267:25] wire [2:0] prefetchable_array_hi_hi = {prefetchable_array_hi_hi_hi, _entries_barrier_9_io_y_c}; // @[package.scala:45:27, :267:25] wire [5:0] prefetchable_array_hi = {prefetchable_array_hi_hi, prefetchable_array_hi_lo}; // @[package.scala:45:27] wire [11:0] _prefetchable_array_T_2 = {prefetchable_array_hi, prefetchable_array_lo}; // @[package.scala:45:27] wire [13:0] prefetchable_array = {_prefetchable_array_T_1, _prefetchable_array_T_2}; // @[package.scala:45:27] wire [39:0] _misaligned_T_3 = {37'h0, io_req_bits_vaddr_0[2:0]}; // @[TLB.scala:318:7, :550:39] wire misaligned = \|_misaligned_T_3; // @[TLB.scala:550:{39,77}] assign _io_resp_ma_ld_T = misaligned; // @[TLB.scala:550:77, :645:31] wire _bad_va_T = vm_enabled & stage1_en; // @[TLB.scala:374:29, :399:61, :568:21] wire [39:0] bad_va_maskedVAddr = io_req_bits_vaddr_0 & 40'hC000000000; // @[TLB.scala:318:7, :559:43] wire _bad_va_T_2 = bad_va_maskedVAddr == 40'h0; // @[TLB.scala:559:43, :560:51] wire _bad_va_T_3 = bad_va_maskedVAddr == 40'hC000000000; // @[TLB.scala:559:43, :560:86] wire _bad_va_T_4 = _bad_va_T_3; // @[TLB.scala:560:{71,86}] wire _bad_va_T_5 = _bad_va_T_2 \| _bad_va_T_4; // @[TLB.scala:560:{51,59,71}] wire _bad_va_T_6 = ~_bad_va_T_5; // @[TLB.scala:560:{37,59}] wire _bad_va_T_7 = _bad_va_T_6; // @[TLB.scala:560:{34,37}] wire bad_va = _bad_va_T & _bad_va_T_7; // @[TLB.scala:560:34, :568:{21,34}] wire _io_resp_pf_ld_T = bad_va; // @[TLB.scala:568:34, :633:28] wire [13:0] _ae_array_T = misaligned ? eff_array : 14'h0; // @[TLB.scala:535:22, :550:77, :582:8] wire [13:0] ae_array = _ae_array_T; // @[TLB.scala:582:{8,37}] wire [13:0] _ae_array_T_1 = ~lrscAllowed; // @[TLB.scala:580:24, :583:19] wire [13:0] _ae_ld_array_T = ~pr_array; // @[TLB.scala:529:87, :586:46] wire [13:0] _ae_ld_array_T_1 = ae_array \| _ae_ld_array_T; // @[TLB.scala:582:37, :586:{44,46}] wire [13:0] ae_ld_array = _ae_ld_array_T_1; // @[TLB.scala:586:{24,44}] wire [13:0] _ae_st_array_T = ~pw_array; // @[TLB.scala:531:87, :588:37] wire [13:0] _ae_st_array_T_1 = ae_array \| _ae_st_array_T; // @[TLB.scala:582:37, :588:{35,37}] wire [13:0] _ae_st_array_T_3 = ~ppp_array_if_cached; // @[TLB.scala:544:39, :589:26] wire [13:0] _ae_st_array_T_6 = ~pal_array_if_cached; // @[TLB.scala:546:39, :590:26] wire [13:0] _ae_st_array_T_9 = ~paa_array_if_cached; // @[TLB.scala:545:39, :591:29] wire [13:0] _must_alloc_array_T = ~ppp_array; // @[TLB.scala:539:22, :593:26] wire [13:0] _must_alloc_array_T_2 = ~pal_array; // @[TLB.scala:543:22, :594:26] wire [13:0] _must_alloc_array_T_5 = ~paa_array; // @[TLB.scala:541:22, :595:29] wire [13:0] _pf_ld_array_T_1 = ~_pf_ld_array_T; // @[TLB.scala:597:{37,41}] wire [13:0] _pf_ld_array_T_2 = ~ptw_ae_array; // @[TLB.scala:506:25, :597:73] wire [13:0] _pf_ld_array_T_3 = _pf_ld_array_T_1 & _pf_ld_array_T_2; // @[TLB.scala:597:{37,71,73}] wire [13:0] _pf_ld_array_T_4 = _pf_ld_array_T_3 \| ptw_pf_array; // @[TLB.scala:508:25, :597:{71,88}] wire [13:0] _pf_ld_array_T_5 = ~ptw_gf_array; // @[TLB.scala:509:25, :597:106] wire [13:0] _pf_ld_array_T_6 = _pf_ld_array_T_4 & _pf_ld_array_T_5; // @[TLB.scala:597:{88,104,106}] wire [13:0] pf_ld_array = _pf_ld_array_T_6; // @[TLB.scala:597:{24,104}] wire [13:0] _pf_st_array_T = ~w_array; // @[TLB.scala:521:20, :598:44] wire [13:0] _pf_st_array_T_1 = ~ptw_ae_array; // @[TLB.scala:506:25, :597:73, :598:55] wire [13:0] _pf_st_array_T_2 = _pf_st_array_T & _pf_st_array_T_1; // @[TLB.scala:598:{44,53,55}] wire [13:0] _pf_st_array_T_3 = _pf_st_array_T_2 \| ptw_pf_array; // @[TLB.scala:508:25, :598:{53,70}] wire [13:0] _pf_st_array_T_4 = ~ptw_gf_array; // @[TLB.scala:509:25, :597:106, :598:88] wire [13:0] _pf_st_array_T_5 = _pf_st_array_T_3 & _pf_st_array_T_4; // @[TLB.scala:598:{70,86,88}] wire [13:0] _pf_inst_array_T = ~x_array; // @[TLB.scala:522:20, :599:25] wire [13:0] _pf_inst_array_T_1 = ~ptw_ae_array; // @[TLB.scala:506:25, :597:73, :599:36] wire [13:0] _pf_inst_array_T_2 = _pf_inst_array_T & _pf_inst_array_T_1; // @[TLB.scala:599:{25,34,36}] wire [13:0] _pf_inst_array_T_3 = _pf_inst_array_T_2 \| ptw_pf_array; // @[TLB.scala:508:25, :599:{34,51}] wire [13:0] _pf_inst_array_T_4 = ~ptw_gf_array; // @[TLB.scala:509:25, :597:106, :599:69] wire [13:0] pf_inst_array = _pf_inst_array_T_3 & _pf_inst_array_T_4; // @[TLB.scala:599:{51,67,69}] wire [13:0] _gf_ld_array_T_4 = ~ptw_ae_array; // @[TLB.scala:506:25, :597:73, :600:100] wire [13:0] _gf_ld_array_T_5 = _gf_ld_array_T_3 & _gf_ld_array_T_4; // @[TLB.scala:600:{82,98,100}] wire [13:0] _gf_st_array_T_3 = ~ptw_ae_array; // @[TLB.scala:506:25, :597:73, :601:81] wire [13:0] _gf_st_array_T_4 = _gf_st_array_T_2 & _gf_st_array_T_3; // @[TLB.scala:601:{63,79,81}] wire [13:0] _gf_inst_array_T_2 = ~ptw_ae_array; // @[TLB.scala:506:25, :597:73, :602:64] wire [13:0] _gf_inst_array_T_3 = _gf_inst_array_T_1 & _gf_inst_array_T_2; // @[TLB.scala:602:{46,62,64}] wire _gpa_hits_hit_mask_T = r_gpa_vpn == vpn; // @[TLB.scala:335:30, :364:22, :606:73] wire _gpa_hits_hit_mask_T_1 = r_gpa_valid & _gpa_hits_hit_mask_T; // @[TLB.scala:362:24, :606:{60,73}] wire [11:0] _gpa_hits_hit_mask_T_2 = {12{_gpa_hits_hit_mask_T_1}}; // @[TLB.scala:606:{24,60}] wire tlb_hit_if_not_gpa_miss = \|real_hits; // @[package.scala:45:27] wire tlb_hit = \|_tlb_hit_T; // @[TLB.scala:611:{28,40}] wire _tlb_miss_T_2 = ~bad_va; // @[TLB.scala:568:34, :613:56] wire _tlb_miss_T_3 = _tlb_miss_T_1 & _tlb_miss_T_2; // @[TLB.scala:613:{29,53,56}] wire _tlb_miss_T_4 = ~tlb_hit; // @[TLB.scala:611:40, :613:67] wire tlb_miss = _tlb_miss_T_3 & _tlb_miss_T_4; // @[TLB.scala:613:{53,64,67}] reg [6:0] state_vec_0; // @[Replacement.scala:305:17] reg [2:0] state_reg_1; // @[Replacement.scala:168:70] wire [1:0] _GEN_60 = {sector_hits_1, sector_hits_0}; // @[OneHot.scala:21:45] wire [1:0] lo_lo; // @[OneHot.scala:21:45] assign lo_lo = _GEN_60; // @[OneHot.scala:21:45] wire [1:0] r_sectored_hit_bits_lo_lo; // @[OneHot.scala:21:45] assign r_sectored_hit_bits_lo_lo = _GEN_60; // @[OneHot.scala:21:45] wire [1:0] _GEN_61 = {sector_hits_3, sector_hits_2}; // @[OneHot.scala:21:45] wire [1:0] lo_hi; // @[OneHot.scala:21:45] assign lo_hi = _GEN_61; // @[OneHot.scala:21:45] wire [1:0] r_sectored_hit_bits_lo_hi; // @[OneHot.scala:21:45] assign r_sectored_hit_bits_lo_hi = _GEN_61; // @[OneHot.scala:21:45] wire [3:0] lo = {lo_hi, lo_lo}; // @[OneHot.scala:21:45] wire [3:0] lo_1 = lo; // @[OneHot.scala:21:45, :31:18] wire [1:0] _GEN_62 = {sector_hits_5, sector_hits_4}; // @[OneHot.scala:21:45] wire [1:0] hi_lo; // @[OneHot.scala:21:45] assign hi_lo = _GEN_62; // @[OneHot.scala:21:45] wire [1:0] r_sectored_hit_bits_hi_lo; // @[OneHot.scala:21:45] assign r_sectored_hit_bits_hi_lo = _GEN_62; // @[OneHot.scala:21:45] wire [1:0] _GEN_63 = {sector_hits_7, sector_hits_6}; // @[OneHot.scala:21:45] wire [1:0] hi_hi; // @[OneHot.scala:21:45] assign hi_hi = _GEN_63; // @[OneHot.scala:21:45] wire [1:0] r_sectored_hit_bits_hi_hi; // @[OneHot.scala:21:45] assign r_sectored_hit_bits_hi_hi = _GEN_63; // @[OneHot.scala:21:45] wire [3:0] hi = {hi_hi, hi_lo}; // @[OneHot.scala:21:45] wire [3:0] hi_1 = hi; // @[OneHot.scala:21:45, :30:18] wire [3:0] _T_33 = hi_1 \| lo_1; // @[OneHot.scala:30:18, :31:18, :32:28] wire [1:0] hi_2 = _T_33[3:2]; // @[OneHot.scala:30:18, :32:28] wire [1:0] lo_2 = _T_33[1:0]; // @[OneHot.scala:31:18, :32:28] wire [2:0] state_vec_0_touch_way_sized = {\|hi_1, \|hi_2, hi_2[1] \| lo_2[1]}; // @[OneHot.scala:30:18, :31:18, :32:{10,14,28}] wire _state_vec_0_set_left_older_T = state_vec_0_touch_way_sized[2]; // @[package.scala:163:13] wire state_vec_0_set_left_older = ~_state_vec_0_set_left_older_T; // @[Replacement.scala:196:{33,43}] wire [2:0] state_vec_0_left_subtree_state = state_vec_0[5:3]; // @[package.scala:163:13] wire [2:0] r_sectored_repl_addr_left_subtree_state = state_vec_0[5:3]; // @[package.scala:163:13] wire [2:0] state_vec_0_right_subtree_state = state_vec_0[2:0]; // @[Replacement.scala:198:38, :305:17] wire [2:0] r_sectored_repl_addr_right_subtree_state = state_vec_0[2:0]; // @[Replacement.scala:198:38, :245:38, :305:17] wire [1:0] _state_vec_0_T = state_vec_0_touch_way_sized[1:0]; // @[package.scala:163:13] wire [1:0] _state_vec_0_T_11 = state_vec_0_touch_way_sized[1:0]; // @[package.scala:163:13] wire _state_vec_0_set_left_older_T_1 = _state_vec_0_T[1]; // @[package.scala:163:13] wire state_vec_0_set_left_older_1 = ~_state_vec_0_set_left_older_T_1; // @[Replacement.scala:196:{33,43}] wire state_vec_0_left_subtree_state_1 = state_vec_0_left_subtree_state[1]; // @[package.scala:163:13] wire state_vec_0_right_subtree_state_1 = state_vec_0_left_subtree_state[0]; // @[package.scala:163:13] wire _state_vec_0_T_1 = _state_vec_0_T[0]; // @[package.scala:163:13] wire _state_vec_0_T_5 = _state_vec_0_T[0]; // @[package.scala:163:13] wire _state_vec_0_T_2 = _state_vec_0_T_1; // @[package.scala:163:13] wire _state_vec_0_T_3 = ~_state_vec_0_T_2; // @[Replacement.scala:218:{7,17}] wire _state_vec_0_T_4 = state_vec_0_set_left_older_1 ? state_vec_0_left_subtree_state_1 : _state_vec_0_T_3; // @[package.scala:163:13] wire _state_vec_0_T_6 = _state_vec_0_T_5; // @[Replacement.scala:207:62, :218:17] wire _state_vec_0_T_7 = ~_state_vec_0_T_6; // @[Replacement.scala:218:{7,17}] wire _state_vec_0_T_8 = state_vec_0_set_left_older_1 ? _state_vec_0_T_7 : state_vec_0_right_subtree_state_1; // @[Replacement.scala:196:33, :198:38, :206:16, :218:7] wire [1:0] state_vec_0_hi = {state_vec_0_set_left_older_1, _state_vec_0_T_4}; // @[Replacement.scala:196:33, :202:12, :203:16] wire [2:0] _state_vec_0_T_9 = {state_vec_0_hi, _state_vec_0_T_8}; // @[Replacement.scala:202:12, :206:16] wire [2:0] _state_vec_0_T_10 = state_vec_0_set_left_older ? state_vec_0_left_subtree_state : _state_vec_0_T_9; // @[package.scala:163:13] wire _state_vec_0_set_left_older_T_2 = _state_vec_0_T_11[1]; // @[Replacement.scala:196:43, :207:62] wire state_vec_0_set_left_older_2 = ~_state_vec_0_set_left_older_T_2; // @[Replacement.scala:196:{33,43}] wire state_vec_0_left_subtree_state_2 = state_vec_0_right_subtree_state[1]; // @[package.scala:163:13] wire state_vec_0_right_subtree_state_2 = state_vec_0_right_subtree_state[0]; // @[Replacement.scala:198:38] wire _state_vec_0_T_12 = _state_vec_0_T_11[0]; // @[package.scala:163:13] wire _state_vec_0_T_16 = _state_vec_0_T_11[0]; // @[package.scala:163:13] wire _state_vec_0_T_13 = _state_vec_0_T_12; // @[package.scala:163:13] wire _state_vec_0_T_14 = ~_state_vec_0_T_13; // @[Replacement.scala:218:{7,17}] wire _state_vec_0_T_15 = state_vec_0_set_left_older_2 ? state_vec_0_left_subtree_state_2 : _state_vec_0_T_14; // @[package.scala:163:13] wire _state_vec_0_T_17 = _state_vec_0_T_16; // @[Replacement.scala:207:62, :218:17] wire _state_vec_0_T_18 = ~_state_vec_0_T_17; // @[Replacement.scala:218:{7,17}] wire _state_vec_0_T_19 = state_vec_0_set_left_older_2 ? _state_vec_0_T_18 : state_vec_0_right_subtree_state_2; // @[Replacement.scala:196:33, :198:38, :206:16, :218:7] wire [1:0] state_vec_0_hi_1 = {state_vec_0_set_left_older_2, _state_vec_0_T_15}; // @[Replacement.scala:196:33, :202:12, :203:16] wire [2:0] _state_vec_0_T_20 = {state_vec_0_hi_1, _state_vec_0_T_19}; // @[Replacement.scala:202:12, :206:16] wire [2:0] _state_vec_0_T_21 = state_vec_0_set_left_older ? _state_vec_0_T_20 : state_vec_0_right_subtree_state; // @[Replacement.scala:196:33, :198:38, :202:12, :206:16] wire [3:0] state_vec_0_hi_2 = {state_vec_0_set_left_older, _state_vec_0_T_10}; // @[Replacement.scala:196:33, :202:12, :203:16] wire [6:0] _state_vec_0_T_22 = {state_vec_0_hi_2, _state_vec_0_T_21}; // @[Replacement.scala:202:12, :206:16] wire [1:0] _GEN_64 = {superpage_hits_1, superpage_hits_0}; // @[OneHot.scala:21:45] wire [1:0] lo_3; // @[OneHot.scala:21:45] assign lo_3 = _GEN_64; // @[OneHot.scala:21:45] wire [1:0] r_superpage_hit_bits_lo; // @[OneHot.scala:21:45] assign r_superpage_hit_bits_lo = _GEN_64; // @[OneHot.scala:21:45] wire [1:0] lo_4 = lo_3; // @[OneHot.scala:21:45, :31:18] wire [1:0] _GEN_65 = {superpage_hits_3, superpage_hits_2}; // @[OneHot.scala:21:45] wire [1:0] hi_3; // @[OneHot.scala:21:45] assign hi_3 = _GEN_65; // @[OneHot.scala:21:45] wire [1:0] r_superpage_hit_bits_hi; // @[OneHot.scala:21:45] assign r_superpage_hit_bits_hi = _GEN_65; // @[OneHot.scala:21:45] wire [1:0] hi_4 = hi_3; // @[OneHot.scala:21:45, :30:18] wire [1:0] state_reg_touch_way_sized = {\|hi_4, hi_4[1] \| lo_4[1]}; // @[OneHot.scala:30:18, :31:18, :32:{10,14,28}] wire _state_reg_set_left_older_T = state_reg_touch_way_sized[1]; // @[package.scala:163:13] wire state_reg_set_left_older = ~_state_reg_set_left_older_T; // @[Replacement.scala:196:{33,43}] wire state_reg_left_subtree_state = state_reg_1[1]; // @[package.scala:163:13] wire r_superpage_repl_addr_left_subtree_state = state_reg_1[1]; // @[package.scala:163:13] wire state_reg_right_subtree_state = state_reg_1[0]; // @[Replacement.scala:168:70, :198:38] wire r_superpage_repl_addr_right_subtree_state = state_reg_1[0]; // @[Replacement.scala:168:70, :198:38, :245:38] wire _state_reg_T = state_reg_touch_way_sized[0]; // @[package.scala:163:13] wire _state_reg_T_4 = state_reg_touch_way_sized[0]; // @[package.scala:163:13] wire _state_reg_T_1 = _state_reg_T; // @[package.scala:163:13] wire _state_reg_T_2 = ~_state_reg_T_1; // @[Replacement.scala:218:{7,17}] wire _state_reg_T_3 = state_reg_set_left_older ? state_reg_left_subtree_state : _state_reg_T_2; // @[package.scala:163:13] wire _state_reg_T_5 = _state_reg_T_4; // @[Replacement.scala:207:62, :218:17] wire _state_reg_T_6 = ~_state_reg_T_5; // @[Replacement.scala:218:{7,17}] wire _state_reg_T_7 = state_reg_set_left_older ? _state_reg_T_6 : state_reg_right_subtree_state; // @[Replacement.scala:196:33, :198:38, :206:16, :218:7] wire [1:0] state_reg_hi = {state_reg_set_left_older, _state_reg_T_3}; // @[Replacement.scala:196:33, :202:12, :203:16] wire [2:0] _state_reg_T_8 = {state_reg_hi, _state_reg_T_7}; // @[Replacement.scala:202:12, :206:16] wire [5:0] _multipleHits_T = real_hits[5:0]; // @[package.scala:45:27] wire [2:0] _multipleHits_T_1 = _multipleHits_T[2:0]; // @[Misc.scala:181:37] wire _multipleHits_T_2 = _multipleHits_T_1[0]; // @[Misc.scala:181:37] wire multipleHits_leftOne = _multipleHits_T_2; // @[Misc.scala:178:18, :181:37] wire [1:0] _multipleHits_T_3 = _multipleHits_T_1[2:1]; // @[Misc.scala:181:37, :182:39] wire _multipleHits_T_4 = _multipleHits_T_3[0]; // @[Misc.scala:181:37, :182:39] wire multipleHits_leftOne_1 = _multipleHits_T_4; // @[Misc.scala:178:18, :181:37] wire _multipleHits_T_5 = _multipleHits_T_3[1]; // @[Misc.scala:182:39] wire multipleHits_rightOne = _multipleHits_T_5; // @[Misc.scala:178:18, :182:39] wire multipleHits_rightOne_1 = multipleHits_leftOne_1 \| multipleHits_rightOne; // @[Misc.scala:178:18, :183:16] wire _multipleHits_T_7 = multipleHits_leftOne_1 & multipleHits_rightOne; // @[Misc.scala:178:18, :183:61] wire multipleHits_rightTwo = _multipleHits_T_7; // @[Misc.scala:183:{49,61}] wire _multipleHits_T_8 = multipleHits_rightTwo; // @[Misc.scala:183:{37,49}] wire multipleHits_leftOne_2 = multipleHits_leftOne \| multipleHits_rightOne_1; // @[Misc.scala:178:18, :183:16] wire _multipleHits_T_9 = multipleHits_leftOne & multipleHits_rightOne_1; // @[Misc.scala:178:18, :183:{16,61}] wire multipleHits_leftTwo = _multipleHits_T_8 \| _multipleHits_T_9; // @[Misc.scala:183:{37,49,61}] wire [2:0] _multipleHits_T_10 = _multipleHits_T[5:3]; // @[Misc.scala:181:37, :182:39] wire _multipleHits_T_11 = _multipleHits_T_10[0]; // @[Misc.scala:181:37, :182:39] wire multipleHits_leftOne_3 = _multipleHits_T_11; // @[Misc.scala:178:18, :181:37] wire [1:0] _multipleHits_T_12 = _multipleHits_T_10[2:1]; // @[Misc.scala:182:39] wire _multipleHits_T_13 = _multipleHits_T_12[0]; // @[Misc.scala:181:37, :182:39] wire multipleHits_leftOne_4 = _multipleHits_T_13; // @[Misc.scala:178:18, :181:37] wire _multipleHits_T_14 = _multipleHits_T_12[1]; // @[Misc.scala:182:39] wire multipleHits_rightOne_2 = _multipleHits_T_14; // @[Misc.scala:178:18, :182:39] wire multipleHits_rightOne_3 = multipleHits_leftOne_4 \| multipleHits_rightOne_2; // @[Misc.scala:178:18, :183:16] wire _multipleHits_T_16 = multipleHits_leftOne_4 & multipleHits_rightOne_2; // @[Misc.scala:178:18, :183:61] wire multipleHits_rightTwo_1 = _multipleHits_T_16; // @[Misc.scala:183:{49,61}] wire _multipleHits_T_17 = multipleHits_rightTwo_1; // @[Misc.scala:183:{37,49}] wire multipleHits_rightOne_4 = multipleHits_leftOne_3 \| multipleHits_rightOne_3; // @[Misc.scala:178:18, :183:16] wire _multipleHits_T_18 = multipleHits_leftOne_3 & multipleHits_rightOne_3; // @[Misc.scala:178:18, :183:{16,61}] wire multipleHits_rightTwo_2 = _multipleHits_T_17 \| _multipleHits_T_18; // @[Misc.scala:183:{37,49,61}] wire multipleHits_leftOne_5 = multipleHits_leftOne_2 \| multipleHits_rightOne_4; // @[Misc.scala:183:16] wire _multipleHits_T_19 = multipleHits_leftTwo \| multipleHits_rightTwo_2; // @[Misc.scala:183:{37,49}] wire _multipleHits_T_20 = multipleHits_leftOne_2 & multipleHits_rightOne_4; // @[Misc.scala:183:{16,61}] wire multipleHits_leftTwo_1 = _multipleHits_T_19 \| _multipleHits_T_20; // @[Misc.scala:183:{37,49,61}] wire [6:0] _multipleHits_T_21 = real_hits[12:6]; // @[package.scala:45:27] wire [2:0] _multipleHits_T_22 = _multipleHits_T_21[2:0]; // @[Misc.scala:181:37, :182:39] wire _multipleHits_T_23 = _multipleHits_T_22[0]; // @[Misc.scala:181:37] wire multipleHits_leftOne_6 = _multipleHits_T_23; // @[Misc.scala:178:18, :181:37] wire [1:0] _multipleHits_T_24 = _multipleHits_T_22[2:1]; // @[Misc.scala:181:37, :182:39] wire _multipleHits_T_25 = _multipleHits_T_24[0]; // @[Misc.scala:181:37, :182:39] wire multipleHits_leftOne_7 = _multipleHits_T_25; // @[Misc.scala:178:18, :181:37] wire _multipleHits_T_26 = _multipleHits_T_24[1]; // @[Misc.scala:182:39] wire multipleHits_rightOne_5 = _multipleHits_T_26; // @[Misc.scala:178:18, :182:39] wire multipleHits_rightOne_6 = multipleHits_leftOne_7 \| multipleHits_rightOne_5; // @[Misc.scala:178:18, :183:16] wire _multipleHits_T_28 = multipleHits_leftOne_7 & multipleHits_rightOne_5; // @[Misc.scala:178:18, :183:61] wire multipleHits_rightTwo_3 = _multipleHits_T_28; // @[Misc.scala:183:{49,61}] wire _multipleHits_T_29 = multipleHits_rightTwo_3; // @[Misc.scala:183:{37,49}] wire multipleHits_leftOne_8 = multipleHits_leftOne_6 \| multipleHits_rightOne_6; // @[Misc.scala:178:18, :183:16] wire _multipleHits_T_30 = multipleHits_leftOne_6 & multipleHits_rightOne_6; // @[Misc.scala:178:18, :183:{16,61}] wire multipleHits_leftTwo_2 = _multipleHits_T_29 \| _multipleHits_T_30; // @[Misc.scala:183:{37,49,61}] wire [3:0] _multipleHits_T_31 = _multipleHits_T_21[6:3]; // @[Misc.scala:182:39] wire [1:0] _multipleHits_T_32 = _multipleHits_T_31[1:0]; // @[Misc.scala:181:37, :182:39] wire _multipleHits_T_33 = _multipleHits_T_32[0]; // @[Misc.scala:181:37] wire multipleHits_leftOne_9 = _multipleHits_T_33; // @[Misc.scala:178:18, :181:37] wire _multipleHits_T_34 = _multipleHits_T_32[1]; // @[Misc.scala:181:37, :182:39] wire multipleHits_rightOne_7 = _multipleHits_T_34; // @[Misc.scala:178:18, :182:39] wire multipleHits_leftOne_10 = multipleHits_leftOne_9 \| multipleHits_rightOne_7; // @[Misc.scala:178:18, :183:16] wire _multipleHits_T_36 = multipleHits_leftOne_9 & multipleHits_rightOne_7; // @[Misc.scala:178:18, :183:61] wire multipleHits_leftTwo_3 = _multipleHits_T_36; // @[Misc.scala:183:{49,61}] wire [1:0] _multipleHits_T_37 = _multipleHits_T_31[3:2]; // @[Misc.scala:182:39] wire _multipleHits_T_38 = _multipleHits_T_37[0]; // @[Misc.scala:181:37, :182:39] wire multipleHits_leftOne_11 = _multipleHits_T_38; // @[Misc.scala:178:18, :181:37] wire _multipleHits_T_39 = _multipleHits_T_37[1]; // @[Misc.scala:182:39] wire multipleHits_rightOne_8 = _multipleHits_T_39; // @[Misc.scala:178:18, :182:39] wire multipleHits_rightOne_9 = multipleHits_leftOne_11 \| multipleHits_rightOne_8; // @[Misc.scala:178:18, :183:16] wire _multipleHits_T_41 = multipleHits_leftOne_11 & multipleHits_rightOne_8; // @[Misc.scala:178:18, :183:61] wire multipleHits_rightTwo_4 = _multipleHits_T_41; // @[Misc.scala:183:{49,61}] wire multipleHits_rightOne_10 = multipleHits_leftOne_10 \| multipleHits_rightOne_9; // @[Misc.scala:183:16] wire _multipleHits_T_42 = multipleHits_leftTwo_3 \| multipleHits_rightTwo_4; // @[Misc.scala:183:{37,49}] wire _multipleHits_T_43 = multipleHits_leftOne_10 & multipleHits_rightOne_9; // @[Misc.scala:183:{16,61}] wire multipleHits_rightTwo_5 = _multipleHits_T_42 \| _multipleHits_T_43; // @[Misc.scala:183:{37,49,61}] wire multipleHits_rightOne_11 = multipleHits_leftOne_8 \| multipleHits_rightOne_10; // @[Misc.scala:183:16] wire _multipleHits_T_44 = multipleHits_leftTwo_2 \| multipleHits_rightTwo_5; // @[Misc.scala:183:{37,49}] wire _multipleHits_T_45 = multipleHits_leftOne_8 & multipleHits_rightOne_10; // @[Misc.scala:183:{16,61}] wire multipleHits_rightTwo_6 = _multipleHits_T_44 \| _multipleHits_T_45; // @[Misc.scala:183:{37,49,61}] wire _multipleHits_T_46 = multipleHits_leftOne_5 \| multipleHits_rightOne_11; // @[Misc.scala:183:16] wire _multipleHits_T_47 = multipleHits_leftTwo_1 \| multipleHits_rightTwo_6; // @[Misc.scala:183:{37,49}] wire _multipleHits_T_48 = multipleHits_leftOne_5 & multipleHits_rightOne_11; // @[Misc.scala:183:{16,61}] wire multipleHits = _multipleHits_T_47 \| _multipleHits_T_48; // @[Misc.scala:183:{37,49,61}] assign _io_req_ready_T = state == 2'h0; // @[TLB.scala:352:22, :631:25] assign io_req_ready = _io_req_ready_T; // @[TLB.scala:318:7, :631:25] wire [13:0] _io_resp_pf_ld_T_1 = pf_ld_array & hits; // @[TLB.scala:442:17, :597:24, :633:57] wire _io_resp_pf_ld_T_2 = \|_io_resp_pf_ld_T_1; // @[TLB.scala:633:{57,65}] assign _io_resp_pf_ld_T_3 = _io_resp_pf_ld_T \| _io_resp_pf_ld_T_2; // @[TLB.scala:633:{28,41,65}] assign io_resp_pf_ld_0 = _io_resp_pf_ld_T_3; // @[TLB.scala:318:7, :633:41] wire [13:0] _io_resp_pf_inst_T = pf_inst_array & hits; // @[TLB.scala:442:17, :599:67, :635:47] wire _io_resp_pf_inst_T_1 = \|_io_resp_pf_inst_T; // @[TLB.scala:635:{47,55}] assign _io_resp_pf_inst_T_2 = bad_va \| _io_resp_pf_inst_T_1; // @[TLB.scala:568:34, :635:{29,55}] assign io_resp_pf_inst_0 = _io_resp_pf_inst_T_2; // @[TLB.scala:318:7, :635:29] wire [13:0] _io_resp_ae_ld_T = ae_ld_array & hits; // @[TLB.scala:442:17, :586:24, :641:33] assign _io_resp_ae_ld_T_1 = \|_io_resp_ae_ld_T; // @[TLB.scala:641:{33,41}] assign io_resp_ae_ld_0 = _io_resp_ae_ld_T_1; // @[TLB.scala:318:7, :641:41] wire [13:0] _io_resp_ae_inst_T = ~px_array; // @[TLB.scala:533:87, :643:23] wire [13:0] _io_resp_ae_inst_T_1 = _io_resp_ae_inst_T & hits; // @[TLB.scala:442:17, :643:{23,33}] assign _io_resp_ae_inst_T_2 = \|_io_resp_ae_inst_T_1; // @[TLB.scala:643:{33,41}] assign io_resp_ae_inst_0 = _io_resp_ae_inst_T_2; // @[TLB.scala:318:7, :643:41] assign io_resp_ma_ld_0 = _io_resp_ma_ld_T; // @[TLB.scala:318:7, :645:31] wire [13:0] _io_resp_cacheable_T = c_array & hits; // @[TLB.scala:442:17, :537:20, :648:33] assign _io_resp_cacheable_T_1 = \|_io_resp_cacheable_T; // @[TLB.scala:648:{33,41}] assign io_resp_cacheable_0 = _io_resp_cacheable_T_1; // @[TLB.scala:318:7, :648:41] wire [13:0] _io_resp_prefetchable_T = prefetchable_array & hits; // @[TLB.scala:442:17, :547:31, :650:47] wire _io_resp_prefetchable_T_1 = \|_io_resp_prefetchable_T; // @[TLB.scala:650:{47,55}] assign _io_resp_prefetchable_T_2 = _io_resp_prefetchable_T_1; // @[TLB.scala:650:{55,59}] assign io_resp_prefetchable_0 = _io_resp_prefetchable_T_2; // @[TLB.scala:318:7, :650:59] wire _io_resp_miss_T_1 = _io_resp_miss_T \| tlb_miss; // @[TLB.scala:613:64, :651:{29,52}] assign _io_resp_miss_T_2 = _io_resp_miss_T_1 \| multipleHits; // @[Misc.scala:183:49] assign io_resp_miss_0 = _io_resp_miss_T_2; // @[TLB.scala:318:7, :651:64] assign _io_resp_paddr_T_1 = {ppn, _io_resp_paddr_T}; // @[Mux.scala:30:73] assign io_resp_paddr_0 = _io_resp_paddr_T_1; // @[TLB.scala:318:7, :652:23] wire [27:0] _io_resp_gpa_page_T_1 = {1'h0, vpn}; // @[TLB.scala:335:30, :657:36] wire [27:0] io_resp_gpa_page = _io_resp_gpa_page_T_1; // @[TLB.scala:657:{19,36}] wire [26:0] _io_resp_gpa_page_T_2 = r_gpa[38:12]; // @[TLB.scala:363:18, :657:58] wire [11:0] _io_resp_gpa_offset_T = r_gpa[11:0]; // @[TLB.scala:363:18, :658:47] wire [11:0] io_resp_gpa_offset = _io_resp_gpa_offset_T_1; // @[TLB.scala:658:{21,82}] assign _io_resp_gpa_T = {io_resp_gpa_page, io_resp_gpa_offset}; // @[TLB.scala:657:19, :658:21, :659:8] assign io_resp_gpa_0 = _io_resp_gpa_T; // @[TLB.scala:318:7, :659:8] assign io_ptw_req_valid_0 = _io_ptw_req_valid_T; // @[TLB.scala:318:7, :662:29] wire r_superpage_repl_addr_left_subtree_older = state_reg_1[2]; // @[Replacement.scala:168:70, :243:38] wire _r_superpage_repl_addr_T = r_superpage_repl_addr_left_subtree_state; // @[package.scala:163:13] wire _r_superpage_repl_addr_T_1 = r_superpage_repl_addr_right_subtree_state; // @[Replacement.scala:245:38, :262:12] wire _r_superpage_repl_addr_T_2 = r_superpage_repl_addr_left_subtree_older ? _r_superpage_repl_addr_T : _r_superpage_repl_addr_T_1; // @[Replacement.scala:243:38, :250:16, :262:12] wire [1:0] _r_superpage_repl_addr_T_3 = {r_superpage_repl_addr_left_subtree_older, _r_superpage_repl_addr_T_2}; // @[Replacement.scala:243:38, :249:12, :250:16] wire [1:0] r_superpage_repl_addr_valids_lo = {superpage_entries_1_valid_0, superpage_entries_0_valid_0}; // @[package.scala:45:27] wire [1:0] r_superpage_repl_addr_valids_hi = {superpage_entries_3_valid_0, superpage_entries_2_valid_0}; // @[package.scala:45:27] wire [3:0] r_superpage_repl_addr_valids = {r_superpage_repl_addr_valids_hi, r_superpage_repl_addr_valids_lo}; // @[package.scala:45:27] wire _r_superpage_repl_addr_T_4 = &r_superpage_repl_addr_valids; // @[package.scala:45:27] wire [3:0] _r_superpage_repl_addr_T_5 = ~r_superpage_repl_addr_valids; // @[package.scala:45:27] wire _r_superpage_repl_addr_T_6 = _r_superpage_repl_addr_T_5[0]; // @[OneHot.scala:48:45] wire _r_superpage_repl_addr_T_7 = _r_superpage_repl_addr_T_5[1]; // @[OneHot.scala:48:45] wire _r_superpage_repl_addr_T_8 = _r_superpage_repl_addr_T_5[2]; // @[OneHot.scala:48:45] wire _r_superpage_repl_addr_T_9 = _r_superpage_repl_addr_T_5[3]; // @[OneHot.scala:48:45] wire [1:0] _r_superpage_repl_addr_T_10 = {1'h1, ~_r_superpage_repl_addr_T_8}; // @[OneHot.scala:48:45] wire [1:0] _r_superpage_repl_addr_T_11 = _r_superpage_repl_addr_T_7 ? 2'h1 : _r_superpage_repl_addr_T_10; // @[OneHot.scala:48:45] wire [1:0] _r_superpage_repl_addr_T_12 = _r_superpage_repl_addr_T_6 ? 2'h0 : _r_superpage_repl_addr_T_11; // @[OneHot.scala:48:45] wire [1:0] _r_superpage_repl_addr_T_13 = _r_superpage_repl_addr_T_4 ? _r_superpage_repl_addr_T_3 : _r_superpage_repl_addr_T_12; // @[Mux.scala:50:70] wire r_sectored_repl_addr_left_subtree_older = state_vec_0[6]; // @[Replacement.scala:243:38, :305:17] wire r_sectored_repl_addr_left_subtree_older_1 = r_sectored_repl_addr_left_subtree_state[2]; // @[package.scala:163:13] wire r_sectored_repl_addr_left_subtree_state_1 = r_sectored_repl_addr_left_subtree_state[1]; // @[package.scala:163:13] wire _r_sectored_repl_addr_T = r_sectored_repl_addr_left_subtree_state_1; // @[package.scala:163:13] wire r_sectored_repl_addr_right_subtree_state_1 = r_sectored_repl_addr_left_subtree_state[0]; // @[package.scala:163:13] wire _r_sectored_repl_addr_T_1 = r_sectored_repl_addr_right_subtree_state_1; // @[Replacement.scala:245:38, :262:12] wire _r_sectored_repl_addr_T_2 = r_sectored_repl_addr_left_subtree_older_1 ? _r_sectored_repl_addr_T : _r_sectored_repl_addr_T_1; // @[Replacement.scala:243:38, :250:16, :262:12] wire [1:0] _r_sectored_repl_addr_T_3 = {r_sectored_repl_addr_left_subtree_older_1, _r_sectored_repl_addr_T_2}; // @[Replacement.scala:243:38, :249:12, :250:16] wire r_sectored_repl_addr_left_subtree_older_2 = r_sectored_repl_addr_right_subtree_state[2]; // @[Replacement.scala:243:38, :245:38] wire r_sectored_repl_addr_left_subtree_state_2 = r_sectored_repl_addr_right_subtree_state[1]; // @[package.scala:163:13] wire _r_sectored_repl_addr_T_4 = r_sectored_repl_addr_left_subtree_state_2; // @[package.scala:163:13] wire r_sectored_repl_addr_right_subtree_state_2 = r_sectored_repl_addr_right_subtree_state[0]; // @[Replacement.scala:245:38] wire _r_sectored_repl_addr_T_5 = r_sectored_repl_addr_right_subtree_state_2; // @[Replacement.scala:245:38, :262:12] wire _r_sectored_repl_addr_T_6 = r_sectored_repl_addr_left_subtree_older_2 ? _r_sectored_repl_addr_T_4 : _r_sectored_repl_addr_T_5; // @[Replacement.scala:243:38, :250:16, :262:12] wire [1:0] _r_sectored_repl_addr_T_7 = {r_sectored_repl_addr_left_subtree_older_2, _r_sectored_repl_addr_T_6}; // @[Replacement.scala:243:38, :249:12, :250:16] wire [1:0] _r_sectored_repl_addr_T_8 = r_sectored_repl_addr_left_subtree_older ? _r_sectored_repl_addr_T_3 : _r_sectored_repl_addr_T_7; // @[Replacement.scala:243:38, :249:12, :250:16] wire [2:0] _r_sectored_repl_addr_T_9 = {r_sectored_repl_addr_left_subtree_older, _r_sectored_repl_addr_T_8}; // @[Replacement.scala:243:38, :249:12, :250:16] wire _r_sectored_repl_addr_valids_T_1 = _r_sectored_repl_addr_valids_T \| sectored_entries_0_0_valid_2; // @[package.scala:81:59] wire _r_sectored_repl_addr_valids_T_2 = _r_sectored_repl_addr_valids_T_1 \| sectored_entries_0_0_valid_3; // @[package.scala:81:59] wire _r_sectored_repl_addr_valids_T_4 = _r_sectored_repl_addr_valids_T_3 \| sectored_entries_0_1_valid_2; // @[package.scala:81:59] wire _r_sectored_repl_addr_valids_T_5 = _r_sectored_repl_addr_valids_T_4 \| sectored_entries_0_1_valid_3; // @[package.scala:81:59] wire _r_sectored_repl_addr_valids_T_7 = _r_sectored_repl_addr_valids_T_6 \| sectored_entries_0_2_valid_2; // @[package.scala:81:59] wire _r_sectored_repl_addr_valids_T_8 = _r_sectored_repl_addr_valids_T_7 \| sectored_entries_0_2_valid_3; // @[package.scala:81:59] wire _r_sectored_repl_addr_valids_T_10 = _r_sectored_repl_addr_valids_T_9 \| sectored_entries_0_3_valid_2; // @[package.scala:81:59] wire _r_sectored_repl_addr_valids_T_11 = _r_sectored_repl_addr_valids_T_10 \| sectored_entries_0_3_valid_3; // @[package.scala:81:59] wire _r_sectored_repl_addr_valids_T_13 = _r_sectored_repl_addr_valids_T_12 \| sectored_entries_0_4_valid_2; // @[package.scala:81:59] wire _r_sectored_repl_addr_valids_T_14 = _r_sectored_repl_addr_valids_T_13 \| sectored_entries_0_4_valid_3; // @[package.scala:81:59] wire _r_sectored_repl_addr_valids_T_16 = _r_sectored_repl_addr_valids_T_15 \| sectored_entries_0_5_valid_2; // @[package.scala:81:59] wire _r_sectored_repl_addr_valids_T_17 = _r_sectored_repl_addr_valids_T_16 \| sectored_entries_0_5_valid_3; // @[package.scala:81:59] wire _r_sectored_repl_addr_valids_T_19 = _r_sectored_repl_addr_valids_T_18 \| sectored_entries_0_6_valid_2; // @[package.scala:81:59] wire _r_sectored_repl_addr_valids_T_20 = _r_sectored_repl_addr_valids_T_19 \| sectored_entries_0_6_valid_3; // @[package.scala:81:59] wire _r_sectored_repl_addr_valids_T_22 = _r_sectored_repl_addr_valids_T_21 \| sectored_entries_0_7_valid_2; // @[package.scala:81:59] wire _r_sectored_repl_addr_valids_T_23 = _r_sectored_repl_addr_valids_T_22 \| sectored_entries_0_7_valid_3; // @[package.scala:81:59] wire [1:0] r_sectored_repl_addr_valids_lo_lo = {_r_sectored_repl_addr_valids_T_5, _r_sectored_repl_addr_valids_T_2}; // @[package.scala:45:27, :81:59] wire [1:0] r_sectored_repl_addr_valids_lo_hi = {_r_sectored_repl_addr_valids_T_11, _r_sectored_repl_addr_valids_T_8}; // @[package.scala:45:27, :81:59] wire [3:0] r_sectored_repl_addr_valids_lo = {r_sectored_repl_addr_valids_lo_hi, r_sectored_repl_addr_valids_lo_lo}; // @[package.scala:45:27] wire [1:0] r_sectored_repl_addr_valids_hi_lo = {_r_sectored_repl_addr_valids_T_17, _r_sectored_repl_addr_valids_T_14}; // @[package.scala:45:27, :81:59] wire [1:0] r_sectored_repl_addr_valids_hi_hi = {_r_sectored_repl_addr_valids_T_23, _r_sectored_repl_addr_valids_T_20}; // @[package.scala:45:27, :81:59] wire [3:0] r_sectored_repl_addr_valids_hi = {r_sectored_repl_addr_valids_hi_hi, r_sectored_repl_addr_valids_hi_lo}; // @[package.scala:45:27] wire [7:0] r_sectored_repl_addr_valids = {r_sectored_repl_addr_valids_hi, r_sectored_repl_addr_valids_lo}; // @[package.scala:45:27] wire _r_sectored_repl_addr_T_10 = &r_sectored_repl_addr_valids; // @[package.scala:45:27] wire [7:0] _r_sectored_repl_addr_T_11 = ~r_sectored_repl_addr_valids; // @[package.scala:45:27] wire _r_sectored_repl_addr_T_12 = _r_sectored_repl_addr_T_11[0]; // @[OneHot.scala:48:45] wire _r_sectored_repl_addr_T_13 = _r_sectored_repl_addr_T_11[1]; // @[OneHot.scala:48:45] wire _r_sectored_repl_addr_T_14 = _r_sectored_repl_addr_T_11[2]; // @[OneHot.scala:48:45] wire _r_sectored_repl_addr_T_15 = _r_sectored_repl_addr_T_11[3]; // @[OneHot.scala:48:45] wire _r_sectored_repl_addr_T_16 = _r_sectored_repl_addr_T_11[4]; // @[OneHot.scala:48:45] wire _r_sectored_repl_addr_T_17 = _r_sectored_repl_addr_T_11[5]; // @[OneHot.scala:48:45] wire _r_sectored_repl_addr_T_18 = _r_sectored_repl_addr_T_11[6]; // @[OneHot.scala:48:45] wire _r_sectored_repl_addr_T_19 = _r_sectored_repl_addr_T_11[7]; // @[OneHot.scala:48:45] wire [2:0] _r_sectored_repl_addr_T_20 = {2'h3, ~_r_sectored_repl_addr_T_18}; // @[OneHot.scala:48:45] wire [2:0] _r_sectored_repl_addr_T_21 = _r_sectored_repl_addr_T_17 ? 3'h5 : _r_sectored_repl_addr_T_20; // @[OneHot.scala:48:45] wire [2:0] _r_sectored_repl_addr_T_22 = _r_sectored_repl_addr_T_16 ? 3'h4 : _r_sectored_repl_addr_T_21; // @[OneHot.scala:48:45] wire [2:0] _r_sectored_repl_addr_T_23 = _r_sectored_repl_addr_T_15 ? 3'h3 : _r_sectored_repl_addr_T_22; // @[OneHot.scala:48:45] wire [2:0] _r_sectored_repl_addr_T_24 = _r_sectored_repl_addr_T_14 ? 3'h2 : _r_sectored_repl_addr_T_23; // @[OneHot.scala:48:45] wire [2:0] _r_sectored_repl_addr_T_25 = _r_sectored_repl_addr_T_13 ? 3'h1 : _r_sectored_repl_addr_T_24; // @[OneHot.scala:48:45] wire [2:0] _r_sectored_repl_addr_T_26 = _r_sectored_repl_addr_T_12 ? 3'h0 : _r_sectored_repl_addr_T_25; // @[OneHot.scala:48:45] wire [2:0] _r_sectored_repl_addr_T_27 = _r_sectored_repl_addr_T_10 ? _r_sectored_repl_addr_T_9 : _r_sectored_repl_addr_T_26; // @[Mux.scala:50:70] wire _r_sectored_hit_valid_T = sector_hits_0 \| sector_hits_1; // @[package.scala:81:59] wire _r_sectored_hit_valid_T_1 = _r_sectored_hit_valid_T \| sector_hits_2; // @[package.scala:81:59] wire _r_sectored_hit_valid_T_2 = _r_sectored_hit_valid_T_1 \| sector_hits_3; // @[package.scala:81:59] wire _r_sectored_hit_valid_T_3 = _r_sectored_hit_valid_T_2 \| sector_hits_4; // @[package.scala:81:59] wire _r_sectored_hit_valid_T_4 = _r_sectored_hit_valid_T_3 \| sector_hits_5; // @[package.scala:81:59] wire _r_sectored_hit_valid_T_5 = _r_sectored_hit_valid_T_4 \| sector_hits_6; // @[package.scala:81:59] wire _r_sectored_hit_valid_T_6 = _r_sectored_hit_valid_T_5 \| sector_hits_7; // @[package.scala:81:59] wire [3:0] r_sectored_hit_bits_lo = {r_sectored_hit_bits_lo_hi, r_sectored_hit_bits_lo_lo}; // @[OneHot.scala:21:45] wire [3:0] r_sectored_hit_bits_hi = {r_sectored_hit_bits_hi_hi, r_sectored_hit_bits_hi_lo}; // @[OneHot.scala:21:45] wire [7:0] _r_sectored_hit_bits_T = {r_sectored_hit_bits_hi, r_sectored_hit_bits_lo}; // @[OneHot.scala:21:45] wire [3:0] r_sectored_hit_bits_hi_1 = _r_sectored_hit_bits_T[7:4]; // @[OneHot.scala:21:45, :30:18] wire [3:0] r_sectored_hit_bits_lo_1 = _r_sectored_hit_bits_T[3:0]; // @[OneHot.scala:21:45, :31:18] wire _r_sectored_hit_bits_T_1 = \|r_sectored_hit_bits_hi_1; // @[OneHot.scala:30:18, :32:14] wire [3:0] _r_sectored_hit_bits_T_2 = r_sectored_hit_bits_hi_1 \| r_sectored_hit_bits_lo_1; // @[OneHot.scala:30:18, :31:18, :32:28] wire [1:0] r_sectored_hit_bits_hi_2 = _r_sectored_hit_bits_T_2[3:2]; // @[OneHot.scala:30:18, :32:28] wire [1:0] r_sectored_hit_bits_lo_2 = _r_sectored_hit_bits_T_2[1:0]; // @[OneHot.scala:31:18, :32:28] wire _r_sectored_hit_bits_T_3 = \|r_sectored_hit_bits_hi_2; // @[OneHot.scala:30:18, :32:14] wire [1:0] _r_sectored_hit_bits_T_4 = r_sectored_hit_bits_hi_2 \| r_sectored_hit_bits_lo_2; // @[OneHot.scala:30:18, :31:18, :32:28] wire _r_sectored_hit_bits_T_5 = _r_sectored_hit_bits_T_4[1]; // @[OneHot.scala:32:28] wire [1:0] _r_sectored_hit_bits_T_6 = {_r_sectored_hit_bits_T_3, _r_sectored_hit_bits_T_5}; // @[OneHot.scala:32:{10,14}] wire [2:0] _r_sectored_hit_bits_T_7 = {_r_sectored_hit_bits_T_1, _r_sectored_hit_bits_T_6}; // @[OneHot.scala:32:{10,14}] wire _r_superpage_hit_valid_T = superpage_hits_0 \| superpage_hits_1; // @[package.scala:81:59] wire _r_superpage_hit_valid_T_1 = _r_superpage_hit_valid_T \| superpage_hits_2; // @[package.scala:81:59] wire _r_superpage_hit_valid_T_2 = _r_superpage_hit_valid_T_1 \| superpage_hits_3; // @[package.scala:81:59] wire [3:0] _r_superpage_hit_bits_T = {r_superpage_hit_bits_hi, r_superpage_hit_bits_lo}; // @[OneHot.scala:21:45] wire [1:0] r_superpage_hit_bits_hi_1 = _r_superpage_hit_bits_T[3:2]; // @[OneHot.scala:21:45, :30:18] wire [1:0] r_superpage_hit_bits_lo_1 = _r_superpage_hit_bits_T[1:0]; // @[OneHot.scala:21:45, :31:18] wire _r_superpage_hit_bits_T_1 = \|r_superpage_hit_bits_hi_1; // @[OneHot.scala:30:18, :32:14] wire [1:0] _r_superpage_hit_bits_T_2 = r_superpage_hit_bits_hi_1 \| r_superpage_hit_bits_lo_1; // @[OneHot.scala:30:18, :31:18, :32:28] wire _r_superpage_hit_bits_T_3 = _r_superpage_hit_bits_T_2[1]; // @[OneHot.scala:32:28] wire [1:0] _r_superpage_hit_bits_T_4 = {_r_superpage_hit_bits_T_1, _r_superpage_hit_bits_T_3}; // @[OneHot.scala:32:{10,14}] wire [1:0] _state_T = {1'h1, io_sfence_valid_0}; // @[TLB.scala:318:7, :704:45]
Generate the Verilog code corresponding to the following Chisel files. File Monitor.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceLine import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import freechips.rocketchip.diplomacy.EnableMonitors import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode} import freechips.rocketchip.util.PlusArg case class TLMonitorArgs(edge: TLEdge) abstract class TLMonitorBase(args: TLMonitorArgs) extends Module { val io = IO(new Bundle { val in = Input(new TLBundle(args.edge.bundle)) }) def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit legalize(io.in, args.edge, reset) } object TLMonitor { def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = { if (enable) { EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) } } else { node } } } class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args) { require (args.edge.params(TLMonitorStrictMode) \|\| (! args.edge.params(TestplanTestType).formal)) val cover_prop_class = PropertyClass.Default //Like assert but can flip to being an assumption for formal verification def monAssert(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir, cond, message, PropertyClass.Default) } def assume(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir.flip, cond, message, PropertyClass.Default) } def extra = { args.edge.sourceInfo match { case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)" case _ => "" } } def visible(address: UInt, source: UInt, edge: TLEdge) = edge.client.clients.map { c => !c.sourceId.contains(source) \|\| c.visibility.map(_.contains(address)).reduce(_ \|\| _) }.reduce(_ && _) def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = { //switch this flag to turn on diplomacy in error messages def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n" monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra) // Reuse these subexpressions to save some firrtl lines val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility") //The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B //TODO: check for acquireT? when (bundle.opcode === TLMessages.AcquireBlock) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra) } when (bundle.opcode === TLMessages.AcquirePerm) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra) monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra) monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra) monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra) } } def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = { monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra) monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility") // Reuse these subexpressions to save some firrtl lines val address_ok = edge.manager.containsSafe(edge.address(bundle)) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source when (bundle.opcode === TLMessages.Probe) { assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra) assume (address_ok, "'B' channel Probe carries unmanaged address" + extra) assume (legal_source, "'B' channel Probe carries source that is not first source" + extra) assume (is_aligned, "'B' channel Probe address not aligned to size" + extra) assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra) assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra) assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra) monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra) monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra) monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra) monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra) } } def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = { monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val address_ok = edge.manager.containsSafe(edge.address(bundle)) monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility") when (bundle.opcode === TLMessages.ProbeAck) { monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra) } when (bundle.opcode === TLMessages.ProbeAckData) { monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.Release) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra) monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra) } when (bundle.opcode === TLMessages.ReleaseData) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.AccessAck) { monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra) } when (bundle.opcode === TLMessages.HintAck) { monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra) } } def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = { assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val sink_ok = bundle.sink < edge.manager.endSinkId.U val deny_put_ok = edge.manager.mayDenyPut.B val deny_get_ok = edge.manager.mayDenyGet.B when (bundle.opcode === TLMessages.ReleaseAck) { assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra) assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra) assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra) } when (bundle.opcode === TLMessages.Grant) { assume (source_ok, "'D' channel Grant carries invalid source ID" + extra) assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra) assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel Grant is denied" + extra) } when (bundle.opcode === TLMessages.GrantData) { assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra) assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra) assume (!bundle.denied \|\| bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra) assume (deny_get_ok \|\| !bundle.denied, "'D' channel GrantData is denied" + extra) } when (bundle.opcode === TLMessages.AccessAck) { assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel AccessAck is denied" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra) assume (!bundle.denied \|\| bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra) assume (deny_get_ok \|\| !bundle.denied, "'D' channel AccessAckData is denied" + extra) } when (bundle.opcode === TLMessages.HintAck) { assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel HintAck is denied" + extra) } } def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = { val sink_ok = bundle.sink < edge.manager.endSinkId.U monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra) } def legalizeFormat(bundle: TLBundle, edge: TLEdge) = { when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) } when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) } when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) } when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) } } else { monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra) monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra) monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra) } } def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = { val a_first = edge.first(a.bits, a.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (a.valid && !a_first) { monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra) monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra) monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra) monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra) monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra) } when (a.fire && a_first) { opcode := a.bits.opcode param := a.bits.param size := a.bits.size source := a.bits.source address := a.bits.address } } def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = { val b_first = edge.first(b.bits, b.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (b.valid && !b_first) { monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra) monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra) monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra) monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra) monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra) } when (b.fire && b_first) { opcode := b.bits.opcode param := b.bits.param size := b.bits.size source := b.bits.source address := b.bits.address } } def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = { // Symbolic variable val sym_source = Wire(UInt(edge.client.endSourceId.W)) // TODO: Connect sym_source to a fixed value for simulation and to a // free wire in formal sym_source := 0.U // Type casting Int to UInt val maxSourceId = Wire(UInt(edge.client.endSourceId.W)) maxSourceId := edge.client.endSourceId.U // Delayed verison of sym_source val sym_source_d = Reg(UInt(edge.client.endSourceId.W)) sym_source_d := sym_source // These will be constraints for FV setup Property( MonitorDirection.Monitor, (sym_source === sym_source_d), "sym_source should remain stable", PropertyClass.Default) Property( MonitorDirection.Monitor, (sym_source <= maxSourceId), "sym_source should take legal value", PropertyClass.Default) val my_resp_pend = RegInit(false.B) val my_opcode = Reg(UInt()) val my_size = Reg(UInt()) val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire) val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire) val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source) val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source) val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat) val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend) when (my_set_resp_pend) { my_resp_pend := true.B } .elsewhen (my_clr_resp_pend) { my_resp_pend := false.B } when (my_a_first_beat) { my_opcode := bundle.a.bits.opcode my_size := bundle.a.bits.size } val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size) val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode) val my_resp_opcode_legal = Wire(Bool()) when ((my_resp_opcode === TLMessages.Get) \|\| (my_resp_opcode === TLMessages.ArithmeticData) \|\| (my_resp_opcode === TLMessages.LogicalData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData) } .elsewhen ((my_resp_opcode === TLMessages.PutFullData) \|\| (my_resp_opcode === TLMessages.PutPartialData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck) } .otherwise { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck) } monAssert (IfThen(my_resp_pend, !my_a_first_beat), "Request message should not be sent with a source ID, for which a response message" + "is already pending (not received until current cycle) for a prior request message" + "with the same source ID" + extra) assume (IfThen(my_clr_resp_pend, (my_set_resp_pend \|\| my_resp_pend)), "Response message should be accepted with a source ID only if a request message with the" + "same source ID has been accepted or is being accepted in the current cycle" + extra) assume (IfThen(my_d_first_beat, (my_a_first_beat \|\| my_resp_pend)), "Response message should be sent with a source ID only if a request message with the" + "same source ID has been accepted or is being sent in the current cycle" + extra) assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)), "If d_valid is 1, then d_size should be same as a_size of the corresponding request" + "message" + extra) assume (IfThen(my_d_first_beat, my_resp_opcode_legal), "If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" + "request message" + extra) } def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = { val c_first = edge.first(c.bits, c.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (c.valid && !c_first) { monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra) monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra) monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra) monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra) monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra) } when (c.fire && c_first) { opcode := c.bits.opcode param := c.bits.param size := c.bits.size source := c.bits.source address := c.bits.address } } def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = { val d_first = edge.first(d.bits, d.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val sink = Reg(UInt()) val denied = Reg(Bool()) when (d.valid && !d_first) { assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra) assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra) assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra) assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra) assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra) assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra) } when (d.fire && d_first) { opcode := d.bits.opcode param := d.bits.param size := d.bits.size source := d.bits.source sink := d.bits.sink denied := d.bits.denied } } def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = { legalizeMultibeatA(bundle.a, edge) legalizeMultibeatD(bundle.d, edge) if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { legalizeMultibeatB(bundle.b, edge) legalizeMultibeatC(bundle.c, edge) } } //This is left in for almond which doesn't adhere to the tilelink protocol @deprecated("Use legalizeADSource instead if possible","") def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.client.endSourceId.W)) val a_first = edge.first(bundle.a.bits, bundle.a.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val a_set = WireInit(0.U(edge.client.endSourceId.W)) when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) assume((a_set \| inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra) } if (edge.manager.minLatency > 0) { assume(a_set =/= d_clr \|\| !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight \| a_set) & ~d_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") assert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = { val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size) val log_a_size_bus_size = log2Ceil(a_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error inflight.suggestName("inflight") val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) inflight_opcodes.suggestName("inflight_opcodes") val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) inflight_sizes.suggestName("inflight_sizes") val a_first = edge.first(bundle.a.bits, bundle.a.fire) a_first.suggestName("a_first") val d_first = edge.first(bundle.d.bits, bundle.d.fire) d_first.suggestName("d_first") val a_set = WireInit(0.U(edge.client.endSourceId.W)) val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) a_set.suggestName("a_set") a_set_wo_ready.suggestName("a_set_wo_ready") val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) a_opcodes_set.suggestName("a_opcodes_set") val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) a_sizes_set.suggestName("a_sizes_set") val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W)) a_opcode_lookup.suggestName("a_opcode_lookup") a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W)) a_size_lookup.suggestName("a_size_lookup") a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant)) val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant)) val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W)) a_opcodes_set_interm.suggestName("a_opcodes_set_interm") val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W)) a_sizes_set_interm.suggestName("a_sizes_set_interm") when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) { a_set_wo_ready := UIntToOH(bundle.a.bits.source) } when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) \| 1.U a_sizes_set_interm := (bundle.a.bits.size << 1.U) \| 1.U a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U) a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U) monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) d_opcodes_clr.suggestName("d_opcodes_clr") val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) \|\| same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) \|\| (bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra) assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) \|\| (bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra) assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) { assume((!bundle.d.ready) \|\| bundle.a.ready, "ready check") } if (edge.manager.minLatency > 0) { assume(a_set_wo_ready =/= d_clr_wo_ready \|\| !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight \| a_set) & ~d_clr inflight_opcodes := (inflight_opcodes \| a_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes \| a_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = { val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size) val log_c_size_bus_size = log2Ceil(c_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) inflight.suggestName("inflight") inflight_opcodes.suggestName("inflight_opcodes") inflight_sizes.suggestName("inflight_sizes") val c_first = edge.first(bundle.c.bits, bundle.c.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) c_first.suggestName("c_first") d_first.suggestName("d_first") val c_set = WireInit(0.U(edge.client.endSourceId.W)) val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) c_set.suggestName("c_set") c_set_wo_ready.suggestName("c_set_wo_ready") c_opcodes_set.suggestName("c_opcodes_set") c_sizes_set.suggestName("c_sizes_set") val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W)) val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W)) c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U c_opcode_lookup.suggestName("c_opcode_lookup") c_size_lookup.suggestName("c_size_lookup") val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W)) val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W)) c_opcodes_set_interm.suggestName("c_opcodes_set_interm") c_sizes_set_interm.suggestName("c_sizes_set_interm") when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) { c_set_wo_ready := UIntToOH(bundle.c.bits.source) } when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) { c_set := UIntToOH(bundle.c.bits.source) c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) \| 1.U c_sizes_set_interm := (bundle.c.bits.size << 1.U) \| 1.U c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U) c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U) monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra) } val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck \|\| bundle.c.bits.opcode === TLMessages.ProbeAckData val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") d_opcodes_clr.suggestName("d_opcodes_clr") d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) \|\| same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) { assume((!bundle.d.ready) \|\| bundle.c.ready, "ready check") } if (edge.manager.minLatency > 0) { when (c_set_wo_ready.orR) { assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra) } } inflight := (inflight \| c_set) & ~d_clr inflight_opcodes := (inflight_opcodes \| c_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes \| c_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.c.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.manager.endSinkId.W)) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val e_first = true.B val d_set = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) { d_set := UIntToOH(bundle.d.bits.sink) assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra) } val e_clr = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) { e_clr := UIntToOH(bundle.e.bits.sink) monAssert((d_set \| inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra) } // edge.client.minLatency applies to BC, not DE inflight := (inflight \| d_set) & ~e_clr } def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = { val sourceBits = log2Ceil(edge.client.endSourceId) val tooBig = 14 // >16kB worth of flight information gets to be too much if (sourceBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked") } else { if (args.edge.params(TestplanTestType).simulation) { if (args.edge.params(TLMonitorStrictMode)) { legalizeADSource(bundle, edge) legalizeCDSource(bundle, edge) } else { legalizeADSourceOld(bundle, edge) } } if (args.edge.params(TestplanTestType).formal) { legalizeADSourceFormal(bundle, edge) } } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { // legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize... val sinkBits = log2Ceil(edge.manager.endSinkId) if (sinkBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked") } else { legalizeDESink(bundle, edge) } } } def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = { legalizeFormat (bundle, edge) legalizeMultibeat (bundle, edge) legalizeUnique (bundle, edge) } } File Misc.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import scala.math._ class ParameterizedBundle(implicit p: Parameters) extends Bundle trait Clocked extends Bundle { val clock = Clock() val reset = Bool() } object DecoupledHelper { def apply(rvs: Bool) = new DecoupledHelper(rvs) } class DecoupledHelper(val rvs: Seq[Bool]) { def fire(exclude: Bool, includes: Bool) = { require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!") (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _) } def fire() = { rvs.reduce(_ && _) } } object MuxT { def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2)) def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3)) def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4)) } /** Creates a cascade of n MuxTs to search for a key value. / object MuxTLookup { def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } } object ValidMux { def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]): ValidIO[T] = { apply(v1 +: v2.toSeq) } def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = { val out = Wire(Valid(valids.head.bits.cloneType)) out.valid := valids.map(_.valid).reduce(_ \|\| _) out.bits := MuxCase(valids.head.bits, valids.map(v => (v.valid -> v.bits))) out } } object Str { def apply(s: String): UInt = { var i = BigInt(0) require(s.forall(validChar _)) for (c <- s) i = (i << 8) \| c i.U((s.length8).W) } def apply(x: Char): UInt = { require(validChar(x)) x.U(8.W) } def apply(x: UInt): UInt = apply(x, 10) def apply(x: UInt, radix: Int): UInt = { val rad = radix.U val w = x.getWidth require(w > 0) var q = x var s = digit(q % rad) for (i <- 1 until ceil(log(2)/log(radix)w).toInt) { q = q / rad s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s) } s } def apply(x: SInt): UInt = apply(x, 10) def apply(x: SInt, radix: Int): UInt = { val neg = x < 0.S val abs = x.abs.asUInt if (radix != 10) { Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix)) } else { val rad = radix.U val w = abs.getWidth require(w > 0) var q = abs var s = digit(q % rad) var needSign = neg for (i <- 1 until ceil(log(2)/log(radix)w).toInt) { q = q / rad val placeSpace = q === 0.U val space = Mux(needSign, Str('-'), Str(' ')) needSign = needSign && !placeSpace s = Cat(Mux(placeSpace, space, digit(q % rad)), s) } Cat(Mux(needSign, Str('-'), Str(' ')), s) } } private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0) private def validChar(x: Char) = x == (x & 0xFF) } object Split { def apply(x: UInt, n0: Int) = { val w = x.getWidth (x.extract(w-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n2: Int, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } } object Random { def apply(mod: Int, random: UInt): UInt = { if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0) else PriorityEncoder(partition(apply(1 << log2Up(mod8), random), mod)) } def apply(mod: Int): UInt = apply(mod, randomizer) def oneHot(mod: Int, random: UInt): UInt = { if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0)) else PriorityEncoderOH(partition(apply(1 << log2Up(mod8), random), mod)).asUInt } def oneHot(mod: Int): UInt = oneHot(mod, randomizer) private def randomizer = LFSR(16) private def partition(value: UInt, slices: Int) = Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U) } object Majority { def apply(in: Set[Bool]): Bool = { val n = (in.size >> 1) + 1 val clauses = in.subsets(n).map(_.reduce(_ && _)) clauses.reduce(_ \|\| _) } def apply(in: Seq[Bool]): Bool = apply(in.toSet) def apply(in: UInt): Bool = apply(in.asBools.toSet) } object PopCountAtLeast { private def two(x: UInt): (Bool, Bool) = x.getWidth match { case 1 => (x.asBool, false.B) case n => val half = x.getWidth / 2 val (leftOne, leftTwo) = two(x(half - 1, 0)) val (rightOne, rightTwo) = two(x(x.getWidth - 1, half)) (leftOne \|\| rightOne, leftTwo \|\| rightTwo \|\| (leftOne && rightOne)) } def apply(x: UInt, n: Int): Bool = n match { case 0 => true.B case 1 => x.orR case 2 => two(x)._2 case 3 => PopCount(x) >= n.U } } // This gets used everywhere, so make the smallest circuit possible ... // Given an address and size, create a mask of beatBytes size // eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111 // groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01 object MaskGen { def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = { require (groupBy >= 1 && beatBytes >= groupBy) require (isPow2(beatBytes) && isPow2(groupBy)) val lgBytes = log2Ceil(beatBytes) val sizeOH = UIntToOH(lgSize \| 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) \| (groupBy2 - 1).U def helper(i: Int): Seq[(Bool, Bool)] = { if (i == 0) { Seq((lgSize >= lgBytes.asUInt, true.B)) } else { val sub = helper(i-1) val size = sizeOH(lgBytes - i) val bit = addr_lo(lgBytes - i) val nbit = !bit Seq.tabulate (1 << i) { j => val (sub_acc, sub_eq) = sub(j/2) val eq = sub_eq && (if (j % 2 == 1) bit else nbit) val acc = sub_acc \|\| (size && eq) (acc, eq) } } } if (groupBy == beatBytes) 1.U else Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse) } } File PlusArg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.experimental._ import chisel3.util.HasBlackBoxResource @deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05") case class PlusArgInfo(default: BigInt, docstring: String) /** Case class for PlusArg information * * @tparam A scala type of the PlusArg value * @param default optional default value * @param docstring text to include in the help * @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT) / private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String) /* Typeclass for converting a type to a doctype string * @tparam A some type / trait Doctypeable[A] { /* Return the doctype string for some option / def toDoctype(a: Option[A]): String } /* Object containing implementations of the Doctypeable typeclass / object Doctypes { /* Converts an Int => "INT" / implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" } /* Converts a BigInt => "INT" / implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" } /* Converts a String => "STRING" / implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" } } class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map( "FORMAT" -> StringParam(format), "DEFAULT" -> IntParam(default), "WIDTH" -> IntParam(width) )) with HasBlackBoxResource { val io = IO(new Bundle { val out = Output(UInt(width.W)) }) addResource("/vsrc/plusarg_reader.v") } / This wrapper class has no outputs, making it clear it is a simulation-only construct / class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module { val io = IO(new Bundle { val count = Input(UInt(width.W)) }) val max = Module(new plusarg_reader(format, default, docstring, width)).io.out when (max > 0.U) { assert (io.count < max, s"Timeout exceeded: $docstring") } } import Doctypes._ object PlusArg { /* PlusArg("foo") will return 42.U if the simulation is run with +foo=42 * Do not use this as an initial register value. The value is set in an * initial block and thus accessing it from another initial is racey. * Add a docstring to document the arg, which can be dumped in an elaboration * pass. / def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out } /* PlusArg.timeout(name, default, docstring)(count) will use chisel.assert * to kill the simulation when count exceeds the specified integer argument. * Default 0 will never assert. / def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count } } object PlusArgArtefacts { private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty / Add a new PlusArg / @deprecated( "Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05" ) def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring) /* Add a new PlusArg * * @tparam A scala type of the PlusArg value * @param name name for the PlusArg * @param default optional default value * @param docstring text to include in the help / def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit = artefacts = artefacts ++ Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default))) / From plus args, generate help text / private def serializeHelp_cHeader(tab: String = ""): String = artefacts .map{ case(arg, info) => s"""\|$tab+$arg=${info.doctype}\\n\\ \|$tab${" "20}${info.docstring}\\n\\ \|""".stripMargin ++ info.default.map{ case default => s"$tab${" "22}(default=${default})\\n\\\n"}.getOrElse("") }.toSeq.mkString("\\n\\\n") ++ "\"" / From plus args, generate a char array of their names / private def serializeArray_cHeader(tab: String = ""): String = { val prettyTab = tab + " " 44 // Length of 'static const ...' s"${tab}static const char * verilog_plusargs [] = {\\\n" ++ artefacts .map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" } .mkString("")++ s"${prettyTab}0};" } /* Generate C code to be included in emulator.cc that helps with * argument parsing based on available Verilog PlusArgs / def serialize_cHeader(): String = s"""\|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\ \|${serializeHelp_cHeader(" "7)} \|${serializeArray_cHeader()} \|""".stripMargin } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /* Like Vec.apply(idx), but tolerates indices of mismatched width / def extract(idx: UInt): T = x((idx \| 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx \| 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def \| (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a \|\| b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_\|\|_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /* Any Data subtype that has a Bool member named valid. / type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /* converts from camel case to to underscores, also removing all spaces / def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /* converts spaces or underscores to hyphens, also lowering case / def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y \| (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y \|\| y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 \| 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /* Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation / def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.diplomacy import chisel3._ import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor} import freechips.rocketchip.util.ShiftQueue /* Options for describing the attributes of memory regions / object RegionType { // Define the 'more relaxed than' ordering val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS) sealed trait T extends Ordered[T] { def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this) } case object CACHED extends T // an intermediate agent may have cached a copy of the region for you case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively } // A non-empty half-open range; [start, end) case class IdRange(start: Int, end: Int) extends Ordered[IdRange] { require (start >= 0, s"Ids cannot be negative, but got: $start.") require (start <= end, "Id ranges cannot be negative.") def compare(x: IdRange) = { val primary = (this.start - x.start).signum val secondary = (x.end - this.end).signum if (primary != 0) primary else secondary } def overlaps(x: IdRange) = start < x.end && x.start < end def contains(x: IdRange) = start <= x.start && x.end <= end def contains(x: Int) = start <= x && x < end def contains(x: UInt) = if (size == 0) { false.B } else if (size == 1) { // simple comparison x === start.U } else { // find index of largest different bit val largestDeltaBit = log2Floor(start ^ (end-1)) val smallestCommonBit = largestDeltaBit + 1 // may not exist in x val uncommonMask = (1 << smallestCommonBit) - 1 val uncommonBits = (x \| 0.U(smallestCommonBit.W))(largestDeltaBit, 0) // the prefix must match exactly (note: may shift ALL bits away) (x >> smallestCommonBit) === (start >> smallestCommonBit).U && // firrtl constant prop range analysis can eliminate these two: (start & uncommonMask).U <= uncommonBits && uncommonBits <= ((end-1) & uncommonMask).U } def shift(x: Int) = IdRange(start+x, end+x) def size = end - start def isEmpty = end == start def range = start until end } object IdRange { def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else { val ranges = s.sorted (ranges.tail zip ranges.init) find { case (a, b) => a overlaps b } } } // An potentially empty inclusive range of 2-powers [min, max] (in bytes) case class TransferSizes(min: Int, max: Int) { def this(x: Int) = this(x, x) require (min <= max, s"Min transfer $min > max transfer $max") require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)") require (max == 0 \|\| isPow2(max), s"TransferSizes must be a power of 2, got: $max") require (min == 0 \|\| isPow2(min), s"TransferSizes must be a power of 2, got: $min") require (max == 0 \|\| min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)") def none = min == 0 def contains(x: Int) = isPow2(x) && min <= x && x <= max def containsLg(x: Int) = contains(1 << x) def containsLg(x: UInt) = if (none) false.B else if (min == max) { log2Ceil(min).U === x } else { log2Ceil(min).U <= x && x <= log2Ceil(max).U } def contains(x: TransferSizes) = x.none \|\| (min <= x.min && x.max <= max) def intersect(x: TransferSizes) = if (x.max < min \|\| max < x.min) TransferSizes.none else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max)) // Not a union, because the result may contain sizes contained by neither term // NOT TO BE CONFUSED WITH COVERPOINTS def mincover(x: TransferSizes) = { if (none) { x } else if (x.none) { this } else { TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max)) } } override def toString() = "TransferSizes[%d, %d]".format(min, max) } object TransferSizes { def apply(x: Int) = new TransferSizes(x) val none = new TransferSizes(0) def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _) def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _) implicit def asBool(x: TransferSizes) = !x.none } // AddressSets specify the address space managed by the manager // Base is the base address, and mask are the bits consumed by the manager // e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff // e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ... case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet] { // Forbid misaligned base address (and empty sets) require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}") require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous // We do allow negative mask (=> ignore all high bits) def contains(x: BigInt) = ((x ^ base) & ~mask) == 0 def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S // turn x into an address contained in this set def legalize(x: UInt): UInt = base.U \| (mask.U & x) // overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1) def overlaps(x: AddressSet) = (~(mask \| x.mask) & (base ^ x.base)) == 0 // contains iff bitwise: x.mask => mask && contains(x.base) def contains(x: AddressSet) = ((x.mask \| (base ^ x.base)) & ~mask) == 0 // The number of bytes to which the manager must be aligned def alignment = ((mask + 1) & ~mask) // Is this a contiguous memory range def contiguous = alignment == mask+1 def finite = mask >= 0 def max = { require (finite, "Max cannot be calculated on infinite mask"); base \| mask } // Widen the match function to ignore all bits in imask def widen(imask: BigInt) = AddressSet(base & ~imask, mask \| imask) // Return an AddressSet that only contains the addresses both sets contain def intersect(x: AddressSet): Option[AddressSet] = { if (!overlaps(x)) { None } else { val r_mask = mask & x.mask val r_base = base \| x.base Some(AddressSet(r_base, r_mask)) } } def subtract(x: AddressSet): Seq[AddressSet] = { intersect(x) match { case None => Seq(this) case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit => val nmask = (mask & (bit-1)) \| remove.mask val nbase = (remove.base ^ bit) & ~nmask AddressSet(nbase, nmask) } } } // AddressSets have one natural Ordering (the containment order, if contiguous) def compare(x: AddressSet) = { val primary = (this.base - x.base).signum // smallest address first val secondary = (x.mask - this.mask).signum // largest mask first if (primary != 0) primary else secondary } // We always want to see things in hex override def toString() = { if (mask >= 0) { "AddressSet(0x%x, 0x%x)".format(base, mask) } else { "AddressSet(0x%x, ~0x%x)".format(base, ~mask) } } def toRanges = { require (finite, "Ranges cannot be calculated on infinite mask") val size = alignment val fragments = mask & ~(size-1) val bits = bitIndexes(fragments) (BigInt(0) until (BigInt(1) << bits.size)).map { i => val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) } AddressRange(off, size) } } } object AddressSet { val everything = AddressSet(0, -1) def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = { if (size == 0) tail.reverse else { val maxBaseAlignment = base & (-base) // 0 for infinite (LSB) val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size val step = if (maxBaseAlignment == 0 \|\| maxBaseAlignment > maxSizeAlignment) maxSizeAlignment else maxBaseAlignment misaligned(base+step, size-step, AddressSet(base, step-1) +: tail) } } def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = { // Pair terms up by ignoring 'bit' seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) => if (seq.size == 1) { seq.head // singleton -> unaffected } else { key.copy(mask = key.mask \| bit) // pair - widen mask by bit } }.toList } def unify(seq: Seq[AddressSet]): Seq[AddressSet] = { val bits = seq.map(_.base).foldLeft(BigInt(0))(_ \| _) AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted } def enumerateMask(mask: BigInt): Seq[BigInt] = { def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] = if (id == mask) (id +: tail).reverse else helper(((~mask \| id) + 1) & mask, id +: tail) helper(0, Nil) } def enumerateBits(mask: BigInt): Seq[BigInt] = { def helper(x: BigInt): Seq[BigInt] = { if (x == 0) { Nil } else { val bit = x & (-x) bit +: helper(x & ~bit) } } helper(mask) } } case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean) { require (depth >= 0, "Buffer depth must be >= 0") def isDefined = depth > 0 def latency = if (isDefined && !flow) 1 else 0 def apply[T <: Data](x: DecoupledIO[T]) = if (isDefined) Queue(x, depth, flow=flow, pipe=pipe) else x def irrevocable[T <: Data](x: ReadyValidIO[T]) = if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe) else x def sq[T <: Data](x: DecoupledIO[T]) = if (!isDefined) x else { val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe)) sq.io.enq <> x sq.io.deq } override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "") } object BufferParams { implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false) val default = BufferParams(2) val none = BufferParams(0) val flow = BufferParams(1, true, false) val pipe = BufferParams(1, false, true) } case class TriStateValue(value: Boolean, set: Boolean) { def update(orig: Boolean) = if (set) value else orig } object TriStateValue { implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true) def unset = TriStateValue(false, false) } trait DirectedBuffers[T] { def copyIn(x: BufferParams): T def copyOut(x: BufferParams): T def copyInOut(x: BufferParams): T } trait IdMapEntry { def name: String def from: IdRange def to: IdRange def isCache: Boolean def requestFifo: Boolean def maxTransactionsInFlight: Option[Int] def pretty(fmt: String) = if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5 fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } else { fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } } abstract class IdMap[T <: IdMapEntry] { protected val fmt: String val mapping: Seq[T] def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n") } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportPutFull \|\| manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB \|\| manager.anySupportGet \|\| manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportPutFull \|\| client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe \|\| client.anySupportGet \|\| client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet \|\| client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull \|\| client.anySupportPutPartial \|\| client.anySupportHint \|\| client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet \|\| manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull \|\| manager.anySupportPutPartial \|\| manager.anySupportHint \|\| manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) \|\| !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.ProbeAckData \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode \| small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U \|\| beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }	module TLMonitor_63( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input io_in_a_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_b_ready, // @[Monitor.scala:20:14] input io_in_b_valid, // @[Monitor.scala:20:14] input [2:0] io_in_b_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_b_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_b_bits_size, // @[Monitor.scala:20:14] input io_in_b_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_b_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_b_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_b_bits_data, // @[Monitor.scala:20:14] input io_in_b_bits_corrupt, // @[Monitor.scala:20:14] input io_in_c_ready, // @[Monitor.scala:20:14] input io_in_c_valid, // @[Monitor.scala:20:14] input [2:0] io_in_c_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_c_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_c_bits_size, // @[Monitor.scala:20:14] input io_in_c_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_c_bits_address, // @[Monitor.scala:20:14] input [63:0] io_in_c_bits_data, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input io_in_d_bits_source, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt, // @[Monitor.scala:20:14] input io_in_e_ready, // @[Monitor.scala:20:14] input io_in_e_valid, // @[Monitor.scala:20:14] input [2:0] io_in_e_bits_sink // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [31:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_b_ready_0 = io_in_b_ready; // @[Monitor.scala:36:7] wire io_in_b_valid_0 = io_in_b_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_b_bits_opcode_0 = io_in_b_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_b_bits_param_0 = io_in_b_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_b_bits_size_0 = io_in_b_bits_size; // @[Monitor.scala:36:7] wire io_in_b_bits_source_0 = io_in_b_bits_source; // @[Monitor.scala:36:7] wire [31:0] io_in_b_bits_address_0 = io_in_b_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_b_bits_mask_0 = io_in_b_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_b_bits_data_0 = io_in_b_bits_data; // @[Monitor.scala:36:7] wire io_in_b_bits_corrupt_0 = io_in_b_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_c_ready_0 = io_in_c_ready; // @[Monitor.scala:36:7] wire io_in_c_valid_0 = io_in_c_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_c_bits_opcode_0 = io_in_c_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_c_bits_param_0 = io_in_c_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_c_bits_size_0 = io_in_c_bits_size; // @[Monitor.scala:36:7] wire io_in_c_bits_source_0 = io_in_c_bits_source; // @[Monitor.scala:36:7] wire [31:0] io_in_c_bits_address_0 = io_in_c_bits_address; // @[Monitor.scala:36:7] wire [63:0] io_in_c_bits_data_0 = io_in_c_bits_data; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7] wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_e_ready_0 = io_in_e_ready; // @[Monitor.scala:36:7] wire io_in_e_valid_0 = io_in_e_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_e_bits_sink_0 = io_in_e_bits_sink; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire io_in_c_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire _legal_source_T_2 = 1'h0; // @[Mux.scala:30:73] wire [15:0] _a_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _c_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hFF; // @[Monitor.scala:724:57] wire [16:0] _a_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _c_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hFF; // @[Monitor.scala:724:57] wire [15:0] _a_size_lookup_T_3 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _c_size_lookup_T_3 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [8:0] b_first_beats1 = 9'h0; // @[Edges.scala:221:14] wire [8:0] b_first_count = 9'h0; // @[Edges.scala:234:25] wire sink_ok = 1'h1; // @[Monitor.scala:309:31] wire sink_ok_1 = 1'h1; // @[Monitor.scala:367:31] wire _b_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire b_first_last = 1'h1; // @[Edges.scala:232:33] wire [3:0] _a_size_lookup_T_2 = 4'h8; // @[Monitor.scala:641:117] wire [3:0] _d_sizes_clr_T = 4'h8; // @[Monitor.scala:681:48] wire [3:0] _c_size_lookup_T_2 = 4'h8; // @[Monitor.scala:750:119] wire [3:0] _d_sizes_clr_T_6 = 4'h8; // @[Monitor.scala:791:48] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire _source_ok_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _mask_sizeOH_T_3 = io_in_b_bits_size_0; // @[Misc.scala:202:34] wire _legal_source_T_1 = io_in_b_bits_source_0; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T = io_in_b_bits_address_0; // @[Monitor.scala:36:7] wire _source_ok_T_5 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_70 = io_in_c_bits_address_0; // @[Monitor.scala:36:7] wire _source_ok_T_3 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire _source_ok_T = ~io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31] wire _source_ok_WIRE_1 = _source_ok_T_1; // @[Parameters.scala:1138:31] wire source_ok = _source_ok_WIRE_0 \| _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46] wire [26:0] _GEN = 27'hFFF << io_in_a_bits_size_0; // @[package.scala:243:71] wire [26:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [11:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [31:0] _is_aligned_T = {20'h0, io_in_a_bits_address_0[11:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 32'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 4'h2; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 \| _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 \| _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 \| _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 \| _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 \| _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 \| _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 \| _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 \| _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire _source_ok_T_2 = ~io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_0 = _source_ok_T_2; // @[Parameters.scala:1138:31] wire _source_ok_WIRE_1_1 = _source_ok_T_3; // @[Parameters.scala:1138:31] wire source_ok_1 = _source_ok_WIRE_1_0 \| _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46] wire [32:0] _address_ok_T_1 = {1'h0, _address_ok_T}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_2 = _address_ok_T_1 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_3 = _address_ok_T_2; // @[Parameters.scala:137:46] wire _address_ok_T_4 = _address_ok_T_3 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_0 = _address_ok_T_4; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_5 = {io_in_b_bits_address_0[31:13], io_in_b_bits_address_0[12:0] ^ 13'h1000}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_6 = {1'h0, _address_ok_T_5}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_7 = _address_ok_T_6 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_8 = _address_ok_T_7; // @[Parameters.scala:137:46] wire _address_ok_T_9 = _address_ok_T_8 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1 = _address_ok_T_9; // @[Parameters.scala:612:40] wire [13:0] _GEN_0 = io_in_b_bits_address_0[13:0] ^ 14'h3000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_10 = {io_in_b_bits_address_0[31:14], _GEN_0}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_11 = {1'h0, _address_ok_T_10}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_12 = _address_ok_T_11 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_13 = _address_ok_T_12; // @[Parameters.scala:137:46] wire _address_ok_T_14 = _address_ok_T_13 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_2 = _address_ok_T_14; // @[Parameters.scala:612:40] wire [16:0] _GEN_1 = io_in_b_bits_address_0[16:0] ^ 17'h10000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_15 = {io_in_b_bits_address_0[31:17], _GEN_1}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_16 = {1'h0, _address_ok_T_15}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_17 = _address_ok_T_16 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_18 = _address_ok_T_17; // @[Parameters.scala:137:46] wire _address_ok_T_19 = _address_ok_T_18 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_3 = _address_ok_T_19; // @[Parameters.scala:612:40] wire [20:0] _GEN_2 = io_in_b_bits_address_0[20:0] ^ 21'h100000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_20 = {io_in_b_bits_address_0[31:21], _GEN_2}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_21 = {1'h0, _address_ok_T_20}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_22 = _address_ok_T_21 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_23 = _address_ok_T_22; // @[Parameters.scala:137:46] wire _address_ok_T_24 = _address_ok_T_23 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_4 = _address_ok_T_24; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_25 = {io_in_b_bits_address_0[31:21], io_in_b_bits_address_0[20:0] ^ 21'h110000}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_26 = {1'h0, _address_ok_T_25}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_27 = _address_ok_T_26 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_28 = _address_ok_T_27; // @[Parameters.scala:137:46] wire _address_ok_T_29 = _address_ok_T_28 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_5 = _address_ok_T_29; // @[Parameters.scala:612:40] wire [25:0] _GEN_3 = io_in_b_bits_address_0[25:0] ^ 26'h2000000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_30 = {io_in_b_bits_address_0[31:26], _GEN_3}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_31 = {1'h0, _address_ok_T_30}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_32 = _address_ok_T_31 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_33 = _address_ok_T_32; // @[Parameters.scala:137:46] wire _address_ok_T_34 = _address_ok_T_33 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_6 = _address_ok_T_34; // @[Parameters.scala:612:40] wire [25:0] _GEN_4 = io_in_b_bits_address_0[25:0] ^ 26'h2010000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_35 = {io_in_b_bits_address_0[31:26], _GEN_4}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_36 = {1'h0, _address_ok_T_35}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_37 = _address_ok_T_36 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_38 = _address_ok_T_37; // @[Parameters.scala:137:46] wire _address_ok_T_39 = _address_ok_T_38 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_7 = _address_ok_T_39; // @[Parameters.scala:612:40] wire [27:0] _GEN_5 = io_in_b_bits_address_0[27:0] ^ 28'h8000000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_40 = {io_in_b_bits_address_0[31:28], _GEN_5}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_41 = {1'h0, _address_ok_T_40}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_42 = _address_ok_T_41 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_43 = _address_ok_T_42; // @[Parameters.scala:137:46] wire _address_ok_T_44 = _address_ok_T_43 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_8 = _address_ok_T_44; // @[Parameters.scala:612:40] wire [27:0] _GEN_6 = io_in_b_bits_address_0[27:0] ^ 28'hC000000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_45 = {io_in_b_bits_address_0[31:28], _GEN_6}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_46 = {1'h0, _address_ok_T_45}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_47 = _address_ok_T_46 & 33'h1FC000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_48 = _address_ok_T_47; // @[Parameters.scala:137:46] wire _address_ok_T_49 = _address_ok_T_48 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_9 = _address_ok_T_49; // @[Parameters.scala:612:40] wire [28:0] _GEN_7 = io_in_b_bits_address_0[28:0] ^ 29'h10020000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_50 = {io_in_b_bits_address_0[31:29], _GEN_7}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_51 = {1'h0, _address_ok_T_50}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_52 = _address_ok_T_51 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_53 = _address_ok_T_52; // @[Parameters.scala:137:46] wire _address_ok_T_54 = _address_ok_T_53 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_10 = _address_ok_T_54; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_55 = io_in_b_bits_address_0 ^ 32'h80000000; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_56 = {1'h0, _address_ok_T_55}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_57 = _address_ok_T_56 & 33'h1F0000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_58 = _address_ok_T_57; // @[Parameters.scala:137:46] wire _address_ok_T_59 = _address_ok_T_58 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_11 = _address_ok_T_59; // @[Parameters.scala:612:40] wire _address_ok_T_60 = _address_ok_WIRE_0 \| _address_ok_WIRE_1; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_61 = _address_ok_T_60 \| _address_ok_WIRE_2; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_62 = _address_ok_T_61 \| _address_ok_WIRE_3; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_63 = _address_ok_T_62 \| _address_ok_WIRE_4; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_64 = _address_ok_T_63 \| _address_ok_WIRE_5; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_65 = _address_ok_T_64 \| _address_ok_WIRE_6; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_66 = _address_ok_T_65 \| _address_ok_WIRE_7; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_67 = _address_ok_T_66 \| _address_ok_WIRE_8; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_68 = _address_ok_T_67 \| _address_ok_WIRE_9; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_69 = _address_ok_T_68 \| _address_ok_WIRE_10; // @[Parameters.scala:612:40, :636:64] wire address_ok = _address_ok_T_69 \| _address_ok_WIRE_11; // @[Parameters.scala:612:40, :636:64] wire [26:0] _GEN_8 = 27'hFFF << io_in_b_bits_size_0; // @[package.scala:243:71] wire [26:0] _is_aligned_mask_T_2; // @[package.scala:243:71] assign _is_aligned_mask_T_2 = _GEN_8; // @[package.scala:243:71] wire [26:0] _b_first_beats1_decode_T; // @[package.scala:243:71] assign _b_first_beats1_decode_T = _GEN_8; // @[package.scala:243:71] wire [11:0] _is_aligned_mask_T_3 = _is_aligned_mask_T_2[11:0]; // @[package.scala:243:{71,76}] wire [11:0] is_aligned_mask_1 = ~_is_aligned_mask_T_3; // @[package.scala:243:{46,76}] wire [31:0] _is_aligned_T_1 = {20'h0, io_in_b_bits_address_0[11:0] & is_aligned_mask_1}; // @[package.scala:243:46] wire is_aligned_1 = _is_aligned_T_1 == 32'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount_1 = _mask_sizeOH_T_3[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_4 = 4'h1 << mask_sizeOH_shiftAmount_1; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_5 = _mask_sizeOH_T_4[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH_1 = {_mask_sizeOH_T_5[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1_1 = io_in_b_bits_size_0 > 4'h2; // @[Misc.scala:206:21] wire mask_sub_sub_size_1 = mask_sizeOH_1[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit_1 = io_in_b_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2_1 = mask_sub_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit_1 = ~mask_sub_sub_bit_1; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2_1 = mask_sub_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T_2 = mask_sub_sub_size_1 & mask_sub_sub_0_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1_1 = mask_sub_sub_sub_0_1_1 \| _mask_sub_sub_acc_T_2; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_3 = mask_sub_sub_size_1 & mask_sub_sub_1_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1_1 = mask_sub_sub_sub_0_1_1 \| _mask_sub_sub_acc_T_3; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size_1 = mask_sizeOH_1[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit_1 = io_in_b_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit_1 = ~mask_sub_bit_1; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2_1 = mask_sub_sub_0_2_1 & mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_4 = mask_sub_size_1 & mask_sub_0_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1_1 = mask_sub_sub_0_1_1 \| _mask_sub_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2_1 = mask_sub_sub_0_2_1 & mask_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_5 = mask_sub_size_1 & mask_sub_1_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1_1 = mask_sub_sub_0_1_1 \| _mask_sub_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2_1 = mask_sub_sub_1_2_1 & mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_6 = mask_sub_size_1 & mask_sub_2_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1_1 = mask_sub_sub_1_1_1 \| _mask_sub_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2_1 = mask_sub_sub_1_2_1 & mask_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_7 = mask_sub_size_1 & mask_sub_3_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1_1 = mask_sub_sub_1_1_1 \| _mask_sub_acc_T_7; // @[Misc.scala:215:{29,38}] wire mask_size_1 = mask_sizeOH_1[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit_1 = io_in_b_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit_1 = ~mask_bit_1; // @[Misc.scala:210:26, :211:20] wire mask_eq_8 = mask_sub_0_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_8 = mask_size_1 & mask_eq_8; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_8 = mask_sub_0_1_1 \| _mask_acc_T_8; // @[Misc.scala:215:{29,38}] wire mask_eq_9 = mask_sub_0_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_9 = mask_size_1 & mask_eq_9; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_9 = mask_sub_0_1_1 \| _mask_acc_T_9; // @[Misc.scala:215:{29,38}] wire mask_eq_10 = mask_sub_1_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_10 = mask_size_1 & mask_eq_10; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_10 = mask_sub_1_1_1 \| _mask_acc_T_10; // @[Misc.scala:215:{29,38}] wire mask_eq_11 = mask_sub_1_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_11 = mask_size_1 & mask_eq_11; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_11 = mask_sub_1_1_1 \| _mask_acc_T_11; // @[Misc.scala:215:{29,38}] wire mask_eq_12 = mask_sub_2_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_12 = mask_size_1 & mask_eq_12; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_12 = mask_sub_2_1_1 \| _mask_acc_T_12; // @[Misc.scala:215:{29,38}] wire mask_eq_13 = mask_sub_2_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_13 = mask_size_1 & mask_eq_13; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_13 = mask_sub_2_1_1 \| _mask_acc_T_13; // @[Misc.scala:215:{29,38}] wire mask_eq_14 = mask_sub_3_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_14 = mask_size_1 & mask_eq_14; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_14 = mask_sub_3_1_1 \| _mask_acc_T_14; // @[Misc.scala:215:{29,38}] wire mask_eq_15 = mask_sub_3_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_15 = mask_size_1 & mask_eq_15; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_15 = mask_sub_3_1_1 \| _mask_acc_T_15; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo_1 = {mask_acc_9, mask_acc_8}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi_1 = {mask_acc_11, mask_acc_10}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo_1 = {mask_lo_hi_1, mask_lo_lo_1}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo_1 = {mask_acc_13, mask_acc_12}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi_1 = {mask_acc_15, mask_acc_14}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi_1 = {mask_hi_hi_1, mask_hi_lo_1}; // @[Misc.scala:222:10] wire [7:0] mask_1 = {mask_hi_1, mask_lo_1}; // @[Misc.scala:222:10] wire _legal_source_T = ~io_in_b_bits_source_0; // @[Monitor.scala:36:7] wire _legal_source_WIRE_0 = _legal_source_T; // @[Parameters.scala:1138:31] wire _legal_source_WIRE_1 = _legal_source_T_1; // @[Parameters.scala:1138:31] wire _legal_source_T_3 = _legal_source_WIRE_1; // @[Mux.scala:30:73] wire _legal_source_T_4 = _legal_source_T_3; // @[Mux.scala:30:73] wire _legal_source_WIRE_1_0 = _legal_source_T_4; // @[Mux.scala:30:73] wire legal_source = _legal_source_WIRE_1_0 == io_in_b_bits_source_0; // @[Mux.scala:30:73] wire _source_ok_T_4 = ~io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire _source_ok_WIRE_2_0 = _source_ok_T_4; // @[Parameters.scala:1138:31] wire _source_ok_WIRE_2_1 = _source_ok_T_5; // @[Parameters.scala:1138:31] wire source_ok_2 = _source_ok_WIRE_2_0 \| _source_ok_WIRE_2_1; // @[Parameters.scala:1138:31, :1139:46] wire [26:0] _GEN_9 = 27'hFFF << io_in_c_bits_size_0; // @[package.scala:243:71] wire [26:0] _is_aligned_mask_T_4; // @[package.scala:243:71] assign _is_aligned_mask_T_4 = _GEN_9; // @[package.scala:243:71] wire [26:0] _c_first_beats1_decode_T; // @[package.scala:243:71] assign _c_first_beats1_decode_T = _GEN_9; // @[package.scala:243:71] wire [26:0] _c_first_beats1_decode_T_3; // @[package.scala:243:71] assign _c_first_beats1_decode_T_3 = _GEN_9; // @[package.scala:243:71] wire [11:0] _is_aligned_mask_T_5 = _is_aligned_mask_T_4[11:0]; // @[package.scala:243:{71,76}] wire [11:0] is_aligned_mask_2 = ~_is_aligned_mask_T_5; // @[package.scala:243:{46,76}] wire [31:0] _is_aligned_T_2 = {20'h0, io_in_c_bits_address_0[11:0] & is_aligned_mask_2}; // @[package.scala:243:46] wire is_aligned_2 = _is_aligned_T_2 == 32'h0; // @[Edges.scala:21:{16,24}] wire [32:0] _address_ok_T_71 = {1'h0, _address_ok_T_70}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_72 = _address_ok_T_71 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_73 = _address_ok_T_72; // @[Parameters.scala:137:46] wire _address_ok_T_74 = _address_ok_T_73 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_0 = _address_ok_T_74; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_75 = {io_in_c_bits_address_0[31:13], io_in_c_bits_address_0[12:0] ^ 13'h1000}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_76 = {1'h0, _address_ok_T_75}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_77 = _address_ok_T_76 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_78 = _address_ok_T_77; // @[Parameters.scala:137:46] wire _address_ok_T_79 = _address_ok_T_78 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_1 = _address_ok_T_79; // @[Parameters.scala:612:40] wire [13:0] _GEN_10 = io_in_c_bits_address_0[13:0] ^ 14'h3000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_80 = {io_in_c_bits_address_0[31:14], _GEN_10}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_81 = {1'h0, _address_ok_T_80}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_82 = _address_ok_T_81 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_83 = _address_ok_T_82; // @[Parameters.scala:137:46] wire _address_ok_T_84 = _address_ok_T_83 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_2 = _address_ok_T_84; // @[Parameters.scala:612:40] wire [16:0] _GEN_11 = io_in_c_bits_address_0[16:0] ^ 17'h10000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_85 = {io_in_c_bits_address_0[31:17], _GEN_11}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_86 = {1'h0, _address_ok_T_85}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_87 = _address_ok_T_86 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_88 = _address_ok_T_87; // @[Parameters.scala:137:46] wire _address_ok_T_89 = _address_ok_T_88 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_3 = _address_ok_T_89; // @[Parameters.scala:612:40] wire [20:0] _GEN_12 = io_in_c_bits_address_0[20:0] ^ 21'h100000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_90 = {io_in_c_bits_address_0[31:21], _GEN_12}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_91 = {1'h0, _address_ok_T_90}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_92 = _address_ok_T_91 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_93 = _address_ok_T_92; // @[Parameters.scala:137:46] wire _address_ok_T_94 = _address_ok_T_93 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_4 = _address_ok_T_94; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_95 = {io_in_c_bits_address_0[31:21], io_in_c_bits_address_0[20:0] ^ 21'h110000}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_96 = {1'h0, _address_ok_T_95}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_97 = _address_ok_T_96 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_98 = _address_ok_T_97; // @[Parameters.scala:137:46] wire _address_ok_T_99 = _address_ok_T_98 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_5 = _address_ok_T_99; // @[Parameters.scala:612:40] wire [25:0] _GEN_13 = io_in_c_bits_address_0[25:0] ^ 26'h2000000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_100 = {io_in_c_bits_address_0[31:26], _GEN_13}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_101 = {1'h0, _address_ok_T_100}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_102 = _address_ok_T_101 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_103 = _address_ok_T_102; // @[Parameters.scala:137:46] wire _address_ok_T_104 = _address_ok_T_103 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_6 = _address_ok_T_104; // @[Parameters.scala:612:40] wire [25:0] _GEN_14 = io_in_c_bits_address_0[25:0] ^ 26'h2010000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_105 = {io_in_c_bits_address_0[31:26], _GEN_14}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_106 = {1'h0, _address_ok_T_105}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_107 = _address_ok_T_106 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_108 = _address_ok_T_107; // @[Parameters.scala:137:46] wire _address_ok_T_109 = _address_ok_T_108 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_7 = _address_ok_T_109; // @[Parameters.scala:612:40] wire [27:0] _GEN_15 = io_in_c_bits_address_0[27:0] ^ 28'h8000000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_110 = {io_in_c_bits_address_0[31:28], _GEN_15}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_111 = {1'h0, _address_ok_T_110}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_112 = _address_ok_T_111 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_113 = _address_ok_T_112; // @[Parameters.scala:137:46] wire _address_ok_T_114 = _address_ok_T_113 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_8 = _address_ok_T_114; // @[Parameters.scala:612:40] wire [27:0] _GEN_16 = io_in_c_bits_address_0[27:0] ^ 28'hC000000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_115 = {io_in_c_bits_address_0[31:28], _GEN_16}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_116 = {1'h0, _address_ok_T_115}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_117 = _address_ok_T_116 & 33'h1FC000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_118 = _address_ok_T_117; // @[Parameters.scala:137:46] wire _address_ok_T_119 = _address_ok_T_118 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_9 = _address_ok_T_119; // @[Parameters.scala:612:40] wire [28:0] _GEN_17 = io_in_c_bits_address_0[28:0] ^ 29'h10020000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_120 = {io_in_c_bits_address_0[31:29], _GEN_17}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_121 = {1'h0, _address_ok_T_120}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_122 = _address_ok_T_121 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_123 = _address_ok_T_122; // @[Parameters.scala:137:46] wire _address_ok_T_124 = _address_ok_T_123 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_10 = _address_ok_T_124; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_125 = io_in_c_bits_address_0 ^ 32'h80000000; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_126 = {1'h0, _address_ok_T_125}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_127 = _address_ok_T_126 & 33'h1F0000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_128 = _address_ok_T_127; // @[Parameters.scala:137:46] wire _address_ok_T_129 = _address_ok_T_128 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_11 = _address_ok_T_129; // @[Parameters.scala:612:40] wire _address_ok_T_130 = _address_ok_WIRE_1_0 \| _address_ok_WIRE_1_1; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_131 = _address_ok_T_130 \| _address_ok_WIRE_1_2; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_132 = _address_ok_T_131 \| _address_ok_WIRE_1_3; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_133 = _address_ok_T_132 \| _address_ok_WIRE_1_4; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_134 = _address_ok_T_133 \| _address_ok_WIRE_1_5; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_135 = _address_ok_T_134 \| _address_ok_WIRE_1_6; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_136 = _address_ok_T_135 \| _address_ok_WIRE_1_7; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_137 = _address_ok_T_136 \| _address_ok_WIRE_1_8; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_138 = _address_ok_T_137 \| _address_ok_WIRE_1_9; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_139 = _address_ok_T_138 \| _address_ok_WIRE_1_10; // @[Parameters.scala:612:40, :636:64] wire address_ok_1 = _address_ok_T_139 \| _address_ok_WIRE_1_11; // @[Parameters.scala:612:40, :636:64] wire _T_2389 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_2389; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_2389; // @[Decoupled.scala:51:35] wire [11:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [8:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [8:0] a_first_counter; // @[Edges.scala:229:27] wire [9:0] _a_first_counter1_T = {1'h0, a_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] a_first_counter1 = _a_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T \| _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [8:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [3:0] size; // @[Monitor.scala:389:22] reg source; // @[Monitor.scala:390:22] reg [31:0] address; // @[Monitor.scala:391:22] wire _T_2463 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_2463; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_2463; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_2463; // @[Decoupled.scala:51:35] wire _d_first_T_3; // @[Decoupled.scala:51:35] assign _d_first_T_3 = _T_2463; // @[Decoupled.scala:51:35] wire [26:0] _GEN_18 = 27'hFFF << io_in_d_bits_size_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_18; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_18; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_18; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_9; // @[package.scala:243:71] assign _d_first_beats1_decode_T_9 = _GEN_18; // @[package.scala:243:71] wire [11:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_3 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [8:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T = {1'h0, d_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1 = _d_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T \| _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [3:0] size_1; // @[Monitor.scala:540:22] reg source_1; // @[Monitor.scala:541:22] reg [2:0] sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] wire _b_first_T = io_in_b_ready_0 & io_in_b_valid_0; // @[Decoupled.scala:51:35] wire b_first_done = _b_first_T; // @[Decoupled.scala:51:35] wire [11:0] _b_first_beats1_decode_T_1 = _b_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _b_first_beats1_decode_T_2 = ~_b_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] b_first_beats1_decode = _b_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire _b_first_beats1_opdata_T = io_in_b_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire b_first_beats1_opdata = ~_b_first_beats1_opdata_T; // @[Edges.scala:97:{28,37}] reg [8:0] b_first_counter; // @[Edges.scala:229:27] wire [9:0] _b_first_counter1_T = {1'h0, b_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] b_first_counter1 = _b_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire b_first = b_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _b_first_last_T = b_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire [8:0] _b_first_count_T = ~b_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] _b_first_counter_T = b_first ? 9'h0 : b_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [2:0] opcode_2; // @[Monitor.scala:410:22] reg [1:0] param_2; // @[Monitor.scala:411:22] reg [3:0] size_2; // @[Monitor.scala:412:22] reg source_2; // @[Monitor.scala:413:22] reg [31:0] address_1; // @[Monitor.scala:414:22] wire _T_2460 = io_in_c_ready_0 & io_in_c_valid_0; // @[Decoupled.scala:51:35] wire _c_first_T; // @[Decoupled.scala:51:35] assign _c_first_T = _T_2460; // @[Decoupled.scala:51:35] wire _c_first_T_1; // @[Decoupled.scala:51:35] assign _c_first_T_1 = _T_2460; // @[Decoupled.scala:51:35] wire [11:0] _c_first_beats1_decode_T_1 = _c_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _c_first_beats1_decode_T_2 = ~_c_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] c_first_beats1_decode = _c_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire c_first_beats1_opdata = io_in_c_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire c_first_beats1_opdata_1 = io_in_c_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [8:0] c_first_beats1 = c_first_beats1_opdata ? c_first_beats1_decode : 9'h0; // @[Edges.scala:102:36, :220:59, :221:14] reg [8:0] c_first_counter; // @[Edges.scala:229:27] wire [9:0] _c_first_counter1_T = {1'h0, c_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] c_first_counter1 = _c_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire c_first = c_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _c_first_last_T = c_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _c_first_last_T_1 = c_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire c_first_last = _c_first_last_T \| _c_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire c_first_done = c_first_last & _c_first_T; // @[Decoupled.scala:51:35] wire [8:0] _c_first_count_T = ~c_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] c_first_count = c_first_beats1 & _c_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _c_first_counter_T = c_first ? c_first_beats1 : c_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_3; // @[Monitor.scala:515:22] reg [2:0] param_3; // @[Monitor.scala:516:22] reg [3:0] size_3; // @[Monitor.scala:517:22] reg source_3; // @[Monitor.scala:518:22] reg [31:0] address_2; // @[Monitor.scala:519:22] reg [1:0] inflight; // @[Monitor.scala:614:27] reg [7:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [15:0] inflight_sizes; // @[Monitor.scala:618:33] wire [11:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [8:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [8:0] a_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] a_first_counter1_1 = _a_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 \| _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [11:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_1 = _d_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 \| _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [1:0] a_set; // @[Monitor.scala:626:34] wire [1:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [7:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [15:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [3:0] _GEN_19 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [3:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_19; // @[Monitor.scala:637:69] wire [3:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_19; // @[Monitor.scala:637:69, :680:101] wire [3:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_19; // @[Monitor.scala:637:69, :749:69] wire [3:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_19; // @[Monitor.scala:637:69, :790:101] wire [7:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [15:0] _a_opcode_lookup_T_6 = {8'h0, _a_opcode_lookup_T_1 & 8'hF}; // @[Monitor.scala:637:{44,97}] wire [15:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [7:0] a_size_lookup; // @[Monitor.scala:639:33] wire [3:0] _GEN_20 = {io_in_d_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :641:65] wire [3:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_20; // @[Monitor.scala:641:65] wire [3:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_20; // @[Monitor.scala:641:65, :681:99] wire [3:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_20; // @[Monitor.scala:641:65, :750:67] wire [3:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_20; // @[Monitor.scala:641:65, :791:99] wire [15:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [15:0] _a_size_lookup_T_6 = _a_size_lookup_T_1 & 16'hFF; // @[Monitor.scala:641:{40,91}] wire [15:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[15:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[7:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [4:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [1:0] _GEN_21 = {1'h0, io_in_a_bits_source_0}; // @[OneHot.scala:58:35] wire [1:0] _GEN_22 = 2'h1 << _GEN_21; // @[OneHot.scala:58:35] wire [1:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_22; // @[OneHot.scala:58:35] wire [1:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_22; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T : 2'h0; // @[OneHot.scala:58:35] wire _T_2315 = _T_2389 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_2315 ? _a_set_T : 2'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_2315 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [4:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [4:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_2315 ? _a_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [3:0] _a_opcodes_set_T = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [18:0] _a_opcodes_set_T_1 = {15'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_2315 ? _a_opcodes_set_T_1[7:0] : 8'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [3:0] _a_sizes_set_T = {io_in_a_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :660:77] wire [19:0] _a_sizes_set_T_1 = {15'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :660:{52,77}] assign a_sizes_set = _T_2315 ? _a_sizes_set_T_1[15:0] : 16'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [1:0] d_clr; // @[Monitor.scala:664:34] wire [1:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [7:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [15:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_23 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_23; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_23; // @[Monitor.scala:673:46, :783:46] wire _T_2361 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [1:0] _GEN_24 = {1'h0, io_in_d_bits_source_0}; // @[OneHot.scala:58:35] wire [1:0] _GEN_25 = 2'h1 << _GEN_24; // @[OneHot.scala:58:35] wire [1:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_25; // @[OneHot.scala:58:35] wire [1:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_25; // @[OneHot.scala:58:35] wire [1:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_25; // @[OneHot.scala:58:35] wire [1:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_25; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_2361 & ~d_release_ack ? _d_clr_wo_ready_T : 2'h0; // @[OneHot.scala:58:35] wire _T_2330 = _T_2463 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_2330 ? _d_clr_T : 2'h0; // @[OneHot.scala:58:35] wire [30:0] _d_opcodes_clr_T_5 = 31'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_2330 ? _d_opcodes_clr_T_5[7:0] : 8'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [30:0] _d_sizes_clr_T_5 = 31'hFF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_2330 ? _d_sizes_clr_T_5[15:0] : 16'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [1:0] _inflight_T = inflight \| a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [1:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [1:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [7:0] _inflight_opcodes_T = inflight_opcodes \| a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [7:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [7:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [15:0] _inflight_sizes_T = inflight_sizes \| a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [15:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [15:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [1:0] inflight_1; // @[Monitor.scala:726:35] reg [7:0] inflight_opcodes_1; // @[Monitor.scala:727:35] reg [15:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [11:0] _c_first_beats1_decode_T_4 = _c_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _c_first_beats1_decode_T_5 = ~_c_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] c_first_beats1_decode_1 = _c_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire [8:0] c_first_beats1_1 = c_first_beats1_opdata_1 ? c_first_beats1_decode_1 : 9'h0; // @[Edges.scala:102:36, :220:59, :221:14] reg [8:0] c_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _c_first_counter1_T_1 = {1'h0, c_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] c_first_counter1_1 = _c_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire c_first_1 = c_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _c_first_last_T_2 = c_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _c_first_last_T_3 = c_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire c_first_last_1 = _c_first_last_T_2 \| _c_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire c_first_done_1 = c_first_last_1 & _c_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _c_first_count_T_1 = ~c_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] c_first_count_1 = c_first_beats1_1 & _c_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _c_first_counter_T_1 = c_first_1 ? c_first_beats1_1 : c_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [11:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_2; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_2 = _d_first_counter1_T_2[8:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 \| _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [1:0] c_set; // @[Monitor.scala:738:34] wire [1:0] c_set_wo_ready; // @[Monitor.scala:739:34] wire [7:0] c_opcodes_set; // @[Monitor.scala:740:34] wire [15:0] c_sizes_set; // @[Monitor.scala:741:34] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [7:0] c_size_lookup; // @[Monitor.scala:748:35] wire [7:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [15:0] _c_opcode_lookup_T_6 = {8'h0, _c_opcode_lookup_T_1 & 8'hF}; // @[Monitor.scala:749:{44,97}] wire [15:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [15:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [15:0] _c_size_lookup_T_6 = _c_size_lookup_T_1 & 16'hFF; // @[Monitor.scala:750:{42,93}] wire [15:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[15:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[7:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [3:0] c_opcodes_set_interm; // @[Monitor.scala:754:40] wire [4:0] c_sizes_set_interm; // @[Monitor.scala:755:40] wire _same_cycle_resp_T_3 = io_in_c_valid_0 & c_first_1; // @[Monitor.scala:36:7, :759:26, :795:44] wire _same_cycle_resp_T_4 = io_in_c_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _same_cycle_resp_T_5 = io_in_c_bits_opcode_0[1]; // @[Monitor.scala:36:7] wire [1:0] _GEN_26 = {1'h0, io_in_c_bits_source_0}; // @[OneHot.scala:58:35] wire [1:0] _GEN_27 = 2'h1 << _GEN_26; // @[OneHot.scala:58:35] wire [1:0] _c_set_wo_ready_T; // @[OneHot.scala:58:35] assign _c_set_wo_ready_T = _GEN_27; // @[OneHot.scala:58:35] wire [1:0] _c_set_T; // @[OneHot.scala:58:35] assign _c_set_T = _GEN_27; // @[OneHot.scala:58:35] assign c_set_wo_ready = _same_cycle_resp_T_3 & _same_cycle_resp_T_4 & _same_cycle_resp_T_5 ? _c_set_wo_ready_T : 2'h0; // @[OneHot.scala:58:35] wire _T_2402 = _T_2460 & c_first_1 & _same_cycle_resp_T_4 & _same_cycle_resp_T_5; // @[Decoupled.scala:51:35] assign c_set = _T_2402 ? _c_set_T : 2'h0; // @[OneHot.scala:58:35] wire [3:0] _c_opcodes_set_interm_T = {io_in_c_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :765:53] wire [3:0] _c_opcodes_set_interm_T_1 = {_c_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:765:{53,61}] assign c_opcodes_set_interm = _T_2402 ? _c_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:754:40, :763:{25,36,70}, :765:{28,61}] wire [4:0] _c_sizes_set_interm_T = {io_in_c_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :766:51] wire [4:0] _c_sizes_set_interm_T_1 = {_c_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:766:{51,59}] assign c_sizes_set_interm = _T_2402 ? _c_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:755:40, :763:{25,36,70}, :766:{28,59}] wire [3:0] _c_opcodes_set_T = {1'h0, io_in_c_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :767:79] wire [18:0] _c_opcodes_set_T_1 = {15'h0, c_opcodes_set_interm} << _c_opcodes_set_T; // @[Monitor.scala:754:40, :767:{54,79}] assign c_opcodes_set = _T_2402 ? _c_opcodes_set_T_1[7:0] : 8'h0; // @[Monitor.scala:740:34, :763:{25,36,70}, :767:{28,54}] wire [3:0] _c_sizes_set_T = {io_in_c_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :768:77] wire [19:0] _c_sizes_set_T_1 = {15'h0, c_sizes_set_interm} << _c_sizes_set_T; // @[Monitor.scala:755:40, :768:{52,77}] assign c_sizes_set = _T_2402 ? _c_sizes_set_T_1[15:0] : 16'h0; // @[Monitor.scala:741:34, :763:{25,36,70}, :768:{28,52}] wire _c_probe_ack_T = io_in_c_bits_opcode_0 == 3'h4; // @[Monitor.scala:36:7, :772:47] wire _c_probe_ack_T_1 = io_in_c_bits_opcode_0 == 3'h5; // @[Monitor.scala:36:7, :772:95] wire c_probe_ack = _c_probe_ack_T \| _c_probe_ack_T_1; // @[Monitor.scala:772:{47,71,95}] wire [1:0] d_clr_1; // @[Monitor.scala:774:34] wire [1:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [7:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [15:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_2433 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_2433 & d_release_ack_1 ? _d_clr_wo_ready_T_1 : 2'h0; // @[OneHot.scala:58:35] wire _T_2415 = _T_2463 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_2415 ? _d_clr_T_1 : 2'h0; // @[OneHot.scala:58:35] wire [30:0] _d_opcodes_clr_T_11 = 31'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_2415 ? _d_opcodes_clr_T_11[7:0] : 8'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [30:0] _d_sizes_clr_T_11 = 31'hFF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_2415 ? _d_sizes_clr_T_11[15:0] : 16'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_6 = _same_cycle_resp_T_4 & _same_cycle_resp_T_5; // @[Edges.scala:68:{36,40,51}] wire _same_cycle_resp_T_7 = _same_cycle_resp_T_3 & _same_cycle_resp_T_6; // @[Monitor.scala:795:{44,55}] wire _same_cycle_resp_T_8 = io_in_c_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :795:113] wire same_cycle_resp_1 = _same_cycle_resp_T_7 & _same_cycle_resp_T_8; // @[Monitor.scala:795:{55,88,113}] wire [1:0] _inflight_T_3 = inflight_1 \| c_set; // @[Monitor.scala:726:35, :738:34, :814:35] wire [1:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [1:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [7:0] _inflight_opcodes_T_3 = inflight_opcodes_1 \| c_opcodes_set; // @[Monitor.scala:727:35, :740:34, :815:43] wire [7:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [7:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [15:0] _inflight_sizes_T_3 = inflight_sizes_1 \| c_sizes_set; // @[Monitor.scala:728:35, :741:34, :816:41] wire [15:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [15:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27] wire [32:0] _watchdog_T_2 = {1'h0, watchdog_1} + 33'h1; // @[Monitor.scala:818:27, :823:26] wire [31:0] _watchdog_T_3 = _watchdog_T_2[31:0]; // @[Monitor.scala:823:26] reg [7:0] inflight_2; // @[Monitor.scala:828:27] wire [11:0] _d_first_beats1_decode_T_10 = _d_first_beats1_decode_T_9[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_11 = ~_d_first_beats1_decode_T_10; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_3 = _d_first_beats1_decode_T_11[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_3 = d_first_beats1_opdata_3 ? d_first_beats1_decode_3 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_3; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_3 = {1'h0, d_first_counter_3} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_3 = _d_first_counter1_T_3[8:0]; // @[Edges.scala:230:28] wire d_first_3 = d_first_counter_3 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_6 = d_first_counter_3 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_7 = d_first_beats1_3 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_3 = _d_first_last_T_6 \| _d_first_last_T_7; // @[Edges.scala:232:{25,33,43}] wire d_first_done_3 = d_first_last_3 & _d_first_T_3; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_3 = ~d_first_counter1_3; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_3 = d_first_beats1_3 & _d_first_count_T_3; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_3 = d_first_3 ? d_first_beats1_3 : d_first_counter1_3; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [7:0] d_set; // @[Monitor.scala:833:25] wire _T_2469 = _T_2463 & d_first_3 & io_in_d_bits_opcode_0[2] & ~(io_in_d_bits_opcode_0[1]); // @[Decoupled.scala:51:35] wire [7:0] _GEN_28 = {5'h0, io_in_d_bits_sink_0}; // @[OneHot.scala:58:35] wire [7:0] _d_set_T = 8'h1 << _GEN_28; // @[OneHot.scala:58:35] assign d_set = _T_2469 ? _d_set_T : 8'h0; // @[OneHot.scala:58:35] wire [7:0] e_clr; // @[Monitor.scala:839:25] wire _T_2478 = io_in_e_ready_0 & io_in_e_valid_0; // @[Decoupled.scala:51:35] wire [7:0] _GEN_29 = {5'h0, io_in_e_bits_sink_0}; // @[OneHot.scala:58:35] wire [7:0] _e_clr_T = 8'h1 << _GEN_29; // @[OneHot.scala:58:35] assign e_clr = _T_2478 ? _e_clr_T : 8'h0; // @[OneHot.scala:58:35]
Generate the Verilog code corresponding to the following Chisel files. File SynchronizerReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util.{RegEnable, Cat} /** These wrap behavioral * shift and next registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * * These are built up of ResetSynchronizerPrimitiveShiftReg, intended to be replaced by the integrator's metastable flops chains or replaced * at this level if they have a multi-bit wide synchronizer primitive. * The different types vary in their reset behavior: * NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin * AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep * 1-bit-wide shift registers. * SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg * * [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference. * * ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross * Clock Domains. */ object SynchronizerResetType extends Enumeration { val NonSync, Inferred, Sync, Async = Value } // Note: this should not be used directly. // Use the companion object to generate this with the correct reset type mixin. private class SynchronizerPrimitiveShiftReg( sync: Int, init: Boolean, resetType: SynchronizerResetType.Value) extends AbstractPipelineReg(1) { val initInt = if (init) 1 else 0 val initPostfix = resetType match { case SynchronizerResetType.NonSync => "" case _ => s"_i${initInt}" } override def desiredName = s"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}" val chain = List.tabulate(sync) { i => val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B) reg.suggestName(s"sync_$i") } chain.last := io.d.asBool (chain.init zip chain.tail).foreach { case (sink, source) => sink := source } io.q := chain.head.asUInt } private object SynchronizerPrimitiveShiftReg { def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = { val gen: () => SynchronizerPrimitiveShiftReg = resetType match { case SynchronizerResetType.NonSync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) case SynchronizerResetType.Async => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset case SynchronizerResetType.Sync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset case SynchronizerResetType.Inferred => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) } AbstractPipelineReg(gen(), in) } } // Note: This module may end up with a non-AsyncReset type reset. // But the Primitives within will always have AsyncReset type. class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asAsyncReset){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async) } } io.q := Cat(output.reverse) } object AsyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } // Note: This module may end up with a non-Bool type reset. // But the Primitives within will always have Bool reset type. @deprecated("SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.", "rocket-chip 1.2") class SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asBool){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync) } } io.q := Cat(output.reverse) } object SyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred) } io.q := Cat(output.reverse) } object ResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}" val output = Seq.tabulate(w) { i => SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync) } io.q := Cat(output.reverse) } object SynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, None) def apply [T <: Data](in: T): T = apply (in, 3, None) } class ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module { override def desiredName = s"ClockCrossingReg_w${w}" val io = IO(new Bundle{ val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) val en = Input(Bool()) }) val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en) io.q := cdc_reg } object ClockCrossingReg { def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = { val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit)) name.foreach{ cdc_reg.suggestName(_) } cdc_reg.io.d := in.asUInt cdc_reg.io.en := en cdc_reg.io.q.asTypeOf(in) } }	module ClockCrossingReg_w32_9( // @[SynchronizerReg.scala:191:7] input clock, // @[SynchronizerReg.scala:191:7] input reset, // @[SynchronizerReg.scala:191:7] input [31:0] io_d, // @[SynchronizerReg.scala:195:14] output [31:0] io_q, // @[SynchronizerReg.scala:195:14] input io_en // @[SynchronizerReg.scala:195:14] ); wire [31:0] io_d_0 = io_d; // @[SynchronizerReg.scala:191:7] wire io_en_0 = io_en; // @[SynchronizerReg.scala:191:7] wire [31:0] io_q_0; // @[SynchronizerReg.scala:191:7] reg [31:0] cdc_reg; // @[SynchronizerReg.scala:201:76] assign io_q_0 = cdc_reg; // @[SynchronizerReg.scala:191:7, :201:76] always @(posedge clock) begin // @[SynchronizerReg.scala:191:7] if (io_en_0) // @[SynchronizerReg.scala:191:7] cdc_reg <= io_d_0; // @[SynchronizerReg.scala:191:7, :201:76] always @(posedge) assign io_q = io_q_0; // @[SynchronizerReg.scala:191:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File Error.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.devices.tilelink import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.resources.SimpleDevice import freechips.rocketchip.tilelink.{TLArbiter, TLMessages, TLPermissions} /** Adds a /dev/null slave that generates TL error response messages / class TLError(params: DevNullParams, buffer: Boolean = true, beatBytes: Int = 4)(implicit p: Parameters) extends DevNullDevice(params, minLatency = if (buffer) 1 else 0, beatBytes, new SimpleDevice("error-device", Seq("sifive,error0"))) { lazy val module = new Impl class Impl extends LazyModuleImp(this) { import TLMessages._ import TLPermissions._ val (in, edge) = node.in(0) val a = if (buffer) {Queue(in.a, 1)} else in.a val da = Wire(chiselTypeOf(in.d)) val idle = RegInit(true.B) val a_last = edge.last(a) val (da_first, da_last, _) = edge.firstlast(da) assert (idle \|\| da_first) // we only send Grant, never GrantData => simplified flow control below a.ready := (da.ready && da_last && idle) \|\| !a_last da.valid := a.valid && a_last && idle da.bits.opcode := TLMessages.adResponse(a.bits.opcode) da.bits.param := 0.U // toT, but error grants must be handled transiently (ie: you don't keep permissions) da.bits.size := a.bits.size da.bits.source := a.bits.source da.bits.sink := 0.U da.bits.denied := true.B da.bits.data := 0.U da.bits.corrupt := edge.hasData(da.bits) if (params.acquire) { val c = if (buffer) {Queue(in.c, 1)} else in.c val dc = Wire(chiselTypeOf(in.d)) val c_last = edge.last(c) val dc_last = edge.last(dc) // Only allow one Grant in-flight at a time when (da.fire && da.bits.opcode === Grant) { idle := false.B } when (in.e.fire) { idle := true.B } c.ready := (dc.ready && dc_last) \|\| !c_last dc.valid := c.valid && c_last // ReleaseAck is not allowed to report failure dc.bits.opcode := ReleaseAck dc.bits.param := VecInit(toB, toN, toN)(c.bits.param(1,0)) dc.bits.size := c.bits.size dc.bits.source := c.bits.source dc.bits.sink := 0.U dc.bits.denied := false.B dc.bits.data := 0.U dc.bits.corrupt := false.B // Combine response channels TLArbiter.lowest(edge, in.d, dc, da) } else { in.d <> da } // We never probe or issue B requests in.b.valid := false.B // Sink GrantAcks in.e.ready := true.B } } File Nodes.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.nodes._ import freechips.rocketchip.util.{AsyncQueueParams,RationalDirection} case object TLMonitorBuilder extends Field[TLMonitorArgs => TLMonitorBase](args => new TLMonitor(args)) object TLImp extends NodeImp[TLMasterPortParameters, TLSlavePortParameters, TLEdgeOut, TLEdgeIn, TLBundle] { def edgeO(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeOut(pd, pu, p, sourceInfo) def edgeI(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeIn (pd, pu, p, sourceInfo) def bundleO(eo: TLEdgeOut) = TLBundle(eo.bundle) def bundleI(ei: TLEdgeIn) = TLBundle(ei.bundle) def render(ei: TLEdgeIn) = RenderedEdge(colour = "#000000" / black /, label = (ei.manager.beatBytes 8).toString) override def monitor(bundle: TLBundle, edge: TLEdgeIn): Unit = { val monitor = Module(edge.params(TLMonitorBuilder)(TLMonitorArgs(edge))) monitor.io.in := bundle } override def mixO(pd: TLMasterPortParameters, node: OutwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLMasterPortParameters = pd.v1copy(clients = pd.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }) override def mixI(pu: TLSlavePortParameters, node: InwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLSlavePortParameters = pu.v1copy(managers = pu.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }) } trait TLFormatNode extends FormatNode[TLEdgeIn, TLEdgeOut] case class TLClientNode(portParams: Seq[TLMasterPortParameters])(implicit valName: ValName) extends SourceNode(TLImp)(portParams) with TLFormatNode case class TLManagerNode(portParams: Seq[TLSlavePortParameters])(implicit valName: ValName) extends SinkNode(TLImp)(portParams) with TLFormatNode case class TLAdapterNode( clientFn: TLMasterPortParameters => TLMasterPortParameters = { s => s }, managerFn: TLSlavePortParameters => TLSlavePortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLImp)(clientFn, managerFn) with TLFormatNode case class TLJunctionNode( clientFn: Seq[TLMasterPortParameters] => Seq[TLMasterPortParameters], managerFn: Seq[TLSlavePortParameters] => Seq[TLSlavePortParameters])( implicit valName: ValName) extends JunctionNode(TLImp)(clientFn, managerFn) with TLFormatNode case class TLIdentityNode()(implicit valName: ValName) extends IdentityNode(TLImp)() with TLFormatNode object TLNameNode { def apply(name: ValName) = TLIdentityNode()(name) def apply(name: Option[String]): TLIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLIdentityNode = apply(Some(name)) } case class TLEphemeralNode()(implicit valName: ValName) extends EphemeralNode(TLImp)() object TLTempNode { def apply(): TLEphemeralNode = TLEphemeralNode()(ValName("temp")) } case class TLNexusNode( clientFn: Seq[TLMasterPortParameters] => TLMasterPortParameters, managerFn: Seq[TLSlavePortParameters] => TLSlavePortParameters)( implicit valName: ValName) extends NexusNode(TLImp)(clientFn, managerFn) with TLFormatNode abstract class TLCustomNode(implicit valName: ValName) extends CustomNode(TLImp) with TLFormatNode // Asynchronous crossings trait TLAsyncFormatNode extends FormatNode[TLAsyncEdgeParameters, TLAsyncEdgeParameters] object TLAsyncImp extends SimpleNodeImp[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncEdgeParameters, TLAsyncBundle] { def edge(pd: TLAsyncClientPortParameters, pu: TLAsyncManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLAsyncEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLAsyncEdgeParameters) = new TLAsyncBundle(e.bundle) def render(e: TLAsyncEdgeParameters) = RenderedEdge(colour = "#ff0000" /* red /, label = e.manager.async.depth.toString) override def mixO(pd: TLAsyncClientPortParameters, node: OutwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLAsyncManagerPortParameters, node: InwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLAsyncAdapterNode( clientFn: TLAsyncClientPortParameters => TLAsyncClientPortParameters = { s => s }, managerFn: TLAsyncManagerPortParameters => TLAsyncManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLAsyncImp)(clientFn, managerFn) with TLAsyncFormatNode case class TLAsyncIdentityNode()(implicit valName: ValName) extends IdentityNode(TLAsyncImp)() with TLAsyncFormatNode object TLAsyncNameNode { def apply(name: ValName) = TLAsyncIdentityNode()(name) def apply(name: Option[String]): TLAsyncIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLAsyncIdentityNode = apply(Some(name)) } case class TLAsyncSourceNode(sync: Option[Int])(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLAsyncImp)( dFn = { p => TLAsyncClientPortParameters(p) }, uFn = { p => p.base.v1copy(minLatency = p.base.minLatency + sync.getOrElse(p.async.sync)) }) with FormatNode[TLEdgeIn, TLAsyncEdgeParameters] // discard cycles in other clock domain case class TLAsyncSinkNode(async: AsyncQueueParams)(implicit valName: ValName) extends MixedAdapterNode(TLAsyncImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = p.base.minLatency + async.sync) }, uFn = { p => TLAsyncManagerPortParameters(async, p) }) with FormatNode[TLAsyncEdgeParameters, TLEdgeOut] // Rationally related crossings trait TLRationalFormatNode extends FormatNode[TLRationalEdgeParameters, TLRationalEdgeParameters] object TLRationalImp extends SimpleNodeImp[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalEdgeParameters, TLRationalBundle] { def edge(pd: TLRationalClientPortParameters, pu: TLRationalManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLRationalEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLRationalEdgeParameters) = new TLRationalBundle(e.bundle) def render(e: TLRationalEdgeParameters) = RenderedEdge(colour = "#00ff00" / green /) override def mixO(pd: TLRationalClientPortParameters, node: OutwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLRationalManagerPortParameters, node: InwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLRationalAdapterNode( clientFn: TLRationalClientPortParameters => TLRationalClientPortParameters = { s => s }, managerFn: TLRationalManagerPortParameters => TLRationalManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLRationalImp)(clientFn, managerFn) with TLRationalFormatNode case class TLRationalIdentityNode()(implicit valName: ValName) extends IdentityNode(TLRationalImp)() with TLRationalFormatNode object TLRationalNameNode { def apply(name: ValName) = TLRationalIdentityNode()(name) def apply(name: Option[String]): TLRationalIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLRationalIdentityNode = apply(Some(name)) } case class TLRationalSourceNode()(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLRationalImp)( dFn = { p => TLRationalClientPortParameters(p) }, uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLRationalEdgeParameters] // discard cycles from other clock domain case class TLRationalSinkNode(direction: RationalDirection)(implicit valName: ValName) extends MixedAdapterNode(TLRationalImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = 1) }, uFn = { p => TLRationalManagerPortParameters(direction, p) }) with FormatNode[TLRationalEdgeParameters, TLEdgeOut] // Credited version of TileLink channels trait TLCreditedFormatNode extends FormatNode[TLCreditedEdgeParameters, TLCreditedEdgeParameters] object TLCreditedImp extends SimpleNodeImp[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedEdgeParameters, TLCreditedBundle] { def edge(pd: TLCreditedClientPortParameters, pu: TLCreditedManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLCreditedEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLCreditedEdgeParameters) = new TLCreditedBundle(e.bundle) def render(e: TLCreditedEdgeParameters) = RenderedEdge(colour = "#ffff00" / yellow /, e.delay.toString) override def mixO(pd: TLCreditedClientPortParameters, node: OutwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLCreditedManagerPortParameters, node: InwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLCreditedAdapterNode( clientFn: TLCreditedClientPortParameters => TLCreditedClientPortParameters = { s => s }, managerFn: TLCreditedManagerPortParameters => TLCreditedManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLCreditedImp)(clientFn, managerFn) with TLCreditedFormatNode case class TLCreditedIdentityNode()(implicit valName: ValName) extends IdentityNode(TLCreditedImp)() with TLCreditedFormatNode object TLCreditedNameNode { def apply(name: ValName) = TLCreditedIdentityNode()(name) def apply(name: Option[String]): TLCreditedIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLCreditedIdentityNode = apply(Some(name)) } case class TLCreditedSourceNode(delay: TLCreditedDelay)(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLCreditedImp)( dFn = { p => TLCreditedClientPortParameters(delay, p) }, uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLCreditedEdgeParameters] // discard cycles from other clock domain case class TLCreditedSinkNode(delay: TLCreditedDelay)(implicit valName: ValName) extends MixedAdapterNode(TLCreditedImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = 1) }, uFn = { p => TLCreditedManagerPortParameters(delay, p) }) with FormatNode[TLCreditedEdgeParameters, TLEdgeOut] File Bundles.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import freechips.rocketchip.util._ import scala.collection.immutable.ListMap import chisel3.util.Decoupled import chisel3.util.DecoupledIO import chisel3.reflect.DataMirror abstract class TLBundleBase(val params: TLBundleParameters) extends Bundle // common combos in lazy policy: // Put + Acquire // Release + AccessAck object TLMessages { // A B C D E def PutFullData = 0.U // . . => AccessAck def PutPartialData = 1.U // . . => AccessAck def ArithmeticData = 2.U // . . => AccessAckData def LogicalData = 3.U // . . => AccessAckData def Get = 4.U // . . => AccessAckData def Hint = 5.U // . . => HintAck def AcquireBlock = 6.U // . => Grant[Data] def AcquirePerm = 7.U // . => Grant[Data] def Probe = 6.U // . => ProbeAck[Data] def AccessAck = 0.U // . . def AccessAckData = 1.U // . . def HintAck = 2.U // . . def ProbeAck = 4.U // . def ProbeAckData = 5.U // . def Release = 6.U // . => ReleaseAck def ReleaseData = 7.U // . => ReleaseAck def Grant = 4.U // . => GrantAck def GrantData = 5.U // . => GrantAck def ReleaseAck = 6.U // . def GrantAck = 0.U // . def isA(x: UInt) = x <= AcquirePerm def isB(x: UInt) = x <= Probe def isC(x: UInt) = x <= ReleaseData def isD(x: UInt) = x <= ReleaseAck def adResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, Grant, Grant) def bcResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, ProbeAck, ProbeAck) def a = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("AcquireBlock",TLPermissions.PermMsgGrow), ("AcquirePerm",TLPermissions.PermMsgGrow)) def b = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("Probe",TLPermissions.PermMsgCap)) def c = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("ProbeAck",TLPermissions.PermMsgReport), ("ProbeAckData",TLPermissions.PermMsgReport), ("Release",TLPermissions.PermMsgReport), ("ReleaseData",TLPermissions.PermMsgReport)) def d = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("Grant",TLPermissions.PermMsgCap), ("GrantData",TLPermissions.PermMsgCap), ("ReleaseAck",TLPermissions.PermMsgReserved)) } /* * The three primary TileLink permissions are: * (T)runk: the agent is (or is on inwards path to) the global point of serialization. * (B)ranch: the agent is on an outwards path to * (N)one: * These permissions are permuted by transfer operations in various ways. * Operations can cap permissions, request for them to be grown or shrunk, * or for a report on their current status. / object TLPermissions { val aWidth = 2 val bdWidth = 2 val cWidth = 3 // Cap types (Grant = new permissions, Probe = permisions <= target) def toT = 0.U(bdWidth.W) def toB = 1.U(bdWidth.W) def toN = 2.U(bdWidth.W) def isCap(x: UInt) = x <= toN // Grow types (Acquire = permissions >= target) def NtoB = 0.U(aWidth.W) def NtoT = 1.U(aWidth.W) def BtoT = 2.U(aWidth.W) def isGrow(x: UInt) = x <= BtoT // Shrink types (ProbeAck, Release) def TtoB = 0.U(cWidth.W) def TtoN = 1.U(cWidth.W) def BtoN = 2.U(cWidth.W) def isShrink(x: UInt) = x <= BtoN // Report types (ProbeAck, Release) def TtoT = 3.U(cWidth.W) def BtoB = 4.U(cWidth.W) def NtoN = 5.U(cWidth.W) def isReport(x: UInt) = x <= NtoN def PermMsgGrow:Seq[String] = Seq("Grow NtoB", "Grow NtoT", "Grow BtoT") def PermMsgCap:Seq[String] = Seq("Cap toT", "Cap toB", "Cap toN") def PermMsgReport:Seq[String] = Seq("Shrink TtoB", "Shrink TtoN", "Shrink BtoN", "Report TotT", "Report BtoB", "Report NtoN") def PermMsgReserved:Seq[String] = Seq("Reserved") } object TLAtomics { val width = 3 // Arithmetic types def MIN = 0.U(width.W) def MAX = 1.U(width.W) def MINU = 2.U(width.W) def MAXU = 3.U(width.W) def ADD = 4.U(width.W) def isArithmetic(x: UInt) = x <= ADD // Logical types def XOR = 0.U(width.W) def OR = 1.U(width.W) def AND = 2.U(width.W) def SWAP = 3.U(width.W) def isLogical(x: UInt) = x <= SWAP def ArithMsg:Seq[String] = Seq("MIN", "MAX", "MINU", "MAXU", "ADD") def LogicMsg:Seq[String] = Seq("XOR", "OR", "AND", "SWAP") } object TLHints { val width = 1 def PREFETCH_READ = 0.U(width.W) def PREFETCH_WRITE = 1.U(width.W) def isHints(x: UInt) = x <= PREFETCH_WRITE def HintsMsg:Seq[String] = Seq("PrefetchRead", "PrefetchWrite") } sealed trait TLChannel extends TLBundleBase { val channelName: String } sealed trait TLDataChannel extends TLChannel sealed trait TLAddrChannel extends TLDataChannel final class TLBundleA(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleA_${params.shortName}" val channelName = "'A' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(List(TLAtomics.width, TLPermissions.aWidth, TLHints.width).max.W) // amo_opcode \|\| grow perms \|\| hint val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleB(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleB_${params.shortName}" val channelName = "'B' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val address = UInt(params.addressBits.W) // from // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleC(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleC_${params.shortName}" val channelName = "'C' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.cWidth.W) // shrink or report perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleD(params: TLBundleParameters) extends TLBundleBase(params) with TLDataChannel { override def typeName = s"TLBundleD_${params.shortName}" val channelName = "'D' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val sink = UInt(params.sinkBits.W) // from val denied = Bool() // implies corrupt iff Data val user = BundleMap(params.responseFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleE(params: TLBundleParameters) extends TLBundleBase(params) with TLChannel { override def typeName = s"TLBundleE_${params.shortName}" val channelName = "'E' channel" val sink = UInt(params.sinkBits.W) // to } class TLBundle(val params: TLBundleParameters) extends Record { // Emulate a Bundle with elements abcde or ad depending on params.hasBCE private val optA = Some (Decoupled(new TLBundleA(params))) private val optB = params.hasBCE.option(Flipped(Decoupled(new TLBundleB(params)))) private val optC = params.hasBCE.option(Decoupled(new TLBundleC(params))) private val optD = Some (Flipped(Decoupled(new TLBundleD(params)))) private val optE = params.hasBCE.option(Decoupled(new TLBundleE(params))) def a: DecoupledIO[TLBundleA] = optA.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleA(params))))) def b: DecoupledIO[TLBundleB] = optB.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleB(params))))) def c: DecoupledIO[TLBundleC] = optC.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleC(params))))) def d: DecoupledIO[TLBundleD] = optD.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleD(params))))) def e: DecoupledIO[TLBundleE] = optE.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleE(params))))) val elements = if (params.hasBCE) ListMap("e" -> e, "d" -> d, "c" -> c, "b" -> b, "a" -> a) else ListMap("d" -> d, "a" -> a) def tieoff(): Unit = { DataMirror.specifiedDirectionOf(a.ready) match { case SpecifiedDirection.Input => a.ready := false.B c.ready := false.B e.ready := false.B b.valid := false.B d.valid := false.B case SpecifiedDirection.Output => a.valid := false.B c.valid := false.B e.valid := false.B b.ready := false.B d.ready := false.B case _ => } } } object TLBundle { def apply(params: TLBundleParameters) = new TLBundle(params) } class TLAsyncBundleBase(val params: TLAsyncBundleParameters) extends Bundle class TLAsyncBundle(params: TLAsyncBundleParameters) extends TLAsyncBundleBase(params) { val a = new AsyncBundle(new TLBundleA(params.base), params.async) val b = Flipped(new AsyncBundle(new TLBundleB(params.base), params.async)) val c = new AsyncBundle(new TLBundleC(params.base), params.async) val d = Flipped(new AsyncBundle(new TLBundleD(params.base), params.async)) val e = new AsyncBundle(new TLBundleE(params.base), params.async) } class TLRationalBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = RationalIO(new TLBundleA(params)) val b = Flipped(RationalIO(new TLBundleB(params))) val c = RationalIO(new TLBundleC(params)) val d = Flipped(RationalIO(new TLBundleD(params))) val e = RationalIO(new TLBundleE(params)) } class TLCreditedBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = CreditedIO(new TLBundleA(params)) val b = Flipped(CreditedIO(new TLBundleB(params))) val c = CreditedIO(new TLBundleC(params)) val d = Flipped(CreditedIO(new TLBundleD(params))) val e = CreditedIO(new TLBundleE(params)) } File LazyModuleImp.scala: package org.chipsalliance.diplomacy.lazymodule import chisel3.{withClockAndReset, Module, RawModule, Reset, _} import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo} import firrtl.passes.InlineAnnotation import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.nodes.Dangle import scala.collection.immutable.SortedMap /** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]]. * * This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy. / sealed trait LazyModuleImpLike extends RawModule { /* [[LazyModule]] that contains this instance. / val wrapper: LazyModule /* IOs that will be automatically "punched" for this instance. / val auto: AutoBundle /* The metadata that describes the [[HalfEdge]]s which generated [[auto]]. / protected[diplomacy] val dangles: Seq[Dangle] // [[wrapper.module]] had better not be accessed while LazyModules are still being built! require( LazyModule.scope.isEmpty, s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}" ) /* Set module name. Defaults to the containing LazyModule's desiredName. / override def desiredName: String = wrapper.desiredName suggestName(wrapper.suggestedName) /* [[Parameters]] for chisel [[Module]]s. / implicit val p: Parameters = wrapper.p /* instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and * submodules. / protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = { // 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]], // 2. return [[Dangle]]s from each module. val childDangles = wrapper.children.reverse.flatMap { c => implicit val sourceInfo: SourceInfo = c.info c.cloneProto.map { cp => // If the child is a clone, then recursively set cloneProto of its children as well def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = { require(bases.size == clones.size) (bases.zip(clones)).map { case (l, r) => require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}") l.cloneProto = Some(r) assignCloneProtos(l.children, r.children) } } assignCloneProtos(c.children, cp.children) // Clone the child module as a record, and get its [[AutoBundle]] val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName) val clonedAuto = clone("auto").asInstanceOf[AutoBundle] // Get the empty [[Dangle]]'s of the cloned child val rawDangles = c.cloneDangles() require(rawDangles.size == clonedAuto.elements.size) // Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) } dangles }.getOrElse { // For non-clones, instantiate the child module val mod = try { Module(c.module) } catch { case e: ChiselException => { println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}") throw e } } mod.dangles } } // Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]]. // This will result in a sequence of [[Dangle]] from these [[BaseNode]]s. val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate()) // Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]] val allDangles = nodeDangles ++ childDangles // Group [[allDangles]] by their [[source]]. val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _) // For each [[source]] set of [[Dangle]]s of size 2, ensure that these // can be connected as a source-sink pair (have opposite flipped value). // Make the connection and mark them as [[done]]. val done = Set() ++ pairing.values.filter(_.size == 2).map { case Seq(a, b) => require(a.flipped != b.flipped) // @todo <> in chisel3 makes directionless connection. if (a.flipped) { a.data <> b.data } else { b.data <> a.data } a.source case _ => None } // Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module. val forward = allDangles.filter(d => !done(d.source)) // Generate [[AutoBundle]] IO from [[forward]]. val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _)) // Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]] val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) => if (d.flipped) { d.data <> io } else { io <> d.data } d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name) } // Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]]. wrapper.inModuleBody.reverse.foreach { _() } if (wrapper.shouldBeInlined) { chisel3.experimental.annotate(new ChiselAnnotation { def toFirrtl = InlineAnnotation(toNamed) }) } // Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]]. (auto, dangles) } } /* Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. / class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike { /* Instantiate hardware of this `Module`. / val (auto, dangles) = instantiate() } /* Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. / class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike { // These wires are the default clock+reset for all LazyModule children. // It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the // [[LazyRawModuleImp]] children. // Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly. /* drive clock explicitly. / val childClock: Clock = Wire(Clock()) /* drive reset explicitly. / val childReset: Reset = Wire(Reset()) // the default is that these are disabled childClock := false.B.asClock childReset := chisel3.DontCare def provideImplicitClockToLazyChildren: Boolean = false val (auto, dangles) = if (provideImplicitClockToLazyChildren) { withClockAndReset(childClock, childReset) { instantiate() } } else { instantiate() } } File MixedNode.scala: package org.chipsalliance.diplomacy.nodes import chisel3.{Data, DontCare, Wire} import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.{Field, Parameters} import org.chipsalliance.diplomacy.ValName import org.chipsalliance.diplomacy.sourceLine /* One side metadata of a [[Dangle]]. * * Describes one side of an edge going into or out of a [[BaseNode]]. * * @param serial * the global [[BaseNode.serial]] number of the [[BaseNode]] that this [[HalfEdge]] connects to. * @param index * the `index` in the [[BaseNode]]'s input or output port list that this [[HalfEdge]] belongs to. / case class HalfEdge(serial: Int, index: Int) extends Ordered[HalfEdge] { import scala.math.Ordered.orderingToOrdered def compare(that: HalfEdge): Int = HalfEdge.unapply(this).compare(HalfEdge.unapply(that)) } /* [[Dangle]] captures the `IO` information of a [[LazyModule]] and which two [[BaseNode]]s the [[Edges]]/[[Bundle]] * connects. * * [[Dangle]]s are generated by [[BaseNode.instantiate]] using [[MixedNode.danglesOut]] and [[MixedNode.danglesIn]] , * [[LazyModuleImp.instantiate]] connects those that go to internal or explicit IO connections in a [[LazyModule]]. * * @param source * the source [[HalfEdge]] of this [[Dangle]], which captures the source [[BaseNode]] and the port `index` within * that [[BaseNode]]. * @param sink * sink [[HalfEdge]] of this [[Dangle]], which captures the sink [[BaseNode]] and the port `index` within that * [[BaseNode]]. * @param flipped * flip or not in [[AutoBundle.makeElements]]. If true this corresponds to `danglesOut`, if false it corresponds to * `danglesIn`. * @param dataOpt * actual [[Data]] for the hardware connection. Can be empty if this belongs to a cloned module / case class Dangle(source: HalfEdge, sink: HalfEdge, flipped: Boolean, name: String, dataOpt: Option[Data]) { def data = dataOpt.get } /* [[Edges]] is a collection of parameters describing the functionality and connection for an interface, which is often * derived from the interconnection protocol and can inform the parameterization of the hardware bundles that actually * implement the protocol. / case class Edges[EI, EO](in: Seq[EI], out: Seq[EO]) /* A field available in [[Parameters]] used to determine whether [[InwardNodeImp.monitor]] will be called. / case object MonitorsEnabled extends Field[Boolean](true) /* When rendering the edge in a graphical format, flip the order in which the edges' source and sink are presented. * * For example, when rendering graphML, yEd by default tries to put the source node vertically above the sink node, but * [[RenderFlipped]] inverts this relationship. When a particular [[LazyModule]] contains both source nodes and sink * nodes, flipping the rendering of one node's edge will usual produce a more concise visual layout for the * [[LazyModule]]. / case object RenderFlipped extends Field[Boolean](false) /* The sealed node class in the package, all node are derived from it. * * @param inner * Sink interface implementation. * @param outer * Source interface implementation. * @param valName * val name of this node. * @tparam DI * Downward-flowing parameters received on the inner side of the node. It is usually a brunch of parameters * describing the protocol parameters from a source. For an [[InwardNode]], it is determined by the connected * [[OutwardNode]]. Since it can be connected to multiple sources, this parameter is always a Seq of source port * parameters. * @tparam UI * Upward-flowing parameters generated by the inner side of the node. It is usually a brunch of parameters describing * the protocol parameters of a sink. For an [[InwardNode]], it is determined itself. * @tparam EI * Edge Parameters describing a connection on the inner side of the node. It is usually a brunch of transfers * specified for a sink according to protocol. * @tparam BI * Bundle type used when connecting to the inner side of the node. It is a hardware interface of this sink interface. * It should extends from [[chisel3.Data]], which represents the real hardware. * @tparam DO * Downward-flowing parameters generated on the outer side of the node. It is usually a brunch of parameters * describing the protocol parameters of a source. For an [[OutwardNode]], it is determined itself. * @tparam UO * Upward-flowing parameters received by the outer side of the node. It is usually a brunch of parameters describing * the protocol parameters from a sink. For an [[OutwardNode]], it is determined by the connected [[InwardNode]]. * Since it can be connected to multiple sinks, this parameter is always a Seq of sink port parameters. * @tparam EO * Edge Parameters describing a connection on the outer side of the node. It is usually a brunch of transfers * specified for a source according to protocol. * @tparam BO * Bundle type used when connecting to the outer side of the node. It is a hardware interface of this source * interface. It should extends from [[chisel3.Data]], which represents the real hardware. * * @note * Call Graph of [[MixedNode]] * - line `─`: source is process by a function and generate pass to others * - Arrow `→`: target of arrow is generated by source * * {{{ * (from the other node) * ┌─────────────────────────────────────────────────────────[[InwardNode.uiParams]]─────────────┐ * ↓ │ * (binding node when elaboration) [[OutwardNode.uoParams]]────────────────────────[[MixedNode.mapParamsU]]→──────────┐ │ * [[InwardNode.accPI]] │ │ │ * │ │ (based on protocol) │ * │ │ [[MixedNode.inner.edgeI]] │ * │ │ ↓ │ * ↓ │ │ │ * (immobilize after elaboration) (inward port from [[OutwardNode]]) │ ↓ │ * [[InwardNode.iBindings]]──┐ [[MixedNode.iDirectPorts]]────────────────────→[[MixedNode.iPorts]] [[InwardNode.uiParams]] │ * │ │ ↑ │ │ │ * │ │ │ [[OutwardNode.doParams]] │ │ * │ │ │ (from the other node) │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * │ │ │ └────────┬──────────────┤ │ * │ │ │ │ │ │ * │ │ │ │ (based on protocol) │ * │ │ │ │ [[MixedNode.inner.edgeI]] │ * │ │ │ │ │ │ * │ │ (from the other node) │ ↓ │ * │ └───[[OutwardNode.oPortMapping]] [[OutwardNode.oStar]] │ [[MixedNode.edgesIn]]───┐ │ * │ ↑ ↑ │ │ ↓ │ * │ │ │ │ │ [[MixedNode.in]] │ * │ │ │ │ ↓ ↑ │ * │ (solve star connection) │ │ │ [[MixedNode.bundleIn]]──┘ │ * ├───[[MixedNode.resolveStar]]→─┼─────────────────────────────┤ └────────────────────────────────────┐ │ * │ │ │ [[MixedNode.bundleOut]]─┐ │ │ * │ │ │ ↑ ↓ │ │ * │ │ │ │ [[MixedNode.out]] │ │ * │ ↓ ↓ │ ↑ │ │ * │ ┌─────[[InwardNode.iPortMapping]] [[InwardNode.iStar]] [[MixedNode.edgesOut]]──┘ │ │ * │ │ (from the other node) ↑ │ │ * │ │ │ │ │ │ * │ │ │ [[MixedNode.outer.edgeO]] │ │ * │ │ │ (based on protocol) │ │ * │ │ │ │ │ │ * │ │ │ ┌────────────────────────────────────────┤ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * (immobilize after elaboration)│ ↓ │ │ │ │ * [[OutwardNode.oBindings]]─┘ [[MixedNode.oDirectPorts]]───→[[MixedNode.oPorts]] [[OutwardNode.doParams]] │ │ * ↑ (inward port from [[OutwardNode]]) │ │ │ │ * │ ┌─────────────────────────────────────────┤ │ │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * [[OutwardNode.accPO]] │ ↓ │ │ │ * (binding node when elaboration) │ [[InwardNode.diParams]]─────→[[MixedNode.mapParamsD]]────────────────────────────┘ │ │ * │ ↑ │ │ * │ └──────────────────────────────────────────────────────────────────────────────────────────┘ │ * └──────────────────────────────────────────────────────────────────────────────────────────────────────────┘ * }}} / abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data]( val inner: InwardNodeImp[DI, UI, EI, BI], val outer: OutwardNodeImp[DO, UO, EO, BO] )( implicit valName: ValName) extends BaseNode with NodeHandle[DI, UI, EI, BI, DO, UO, EO, BO] with InwardNode[DI, UI, BI] with OutwardNode[DO, UO, BO] { // Generate a [[NodeHandle]] with inward and outward node are both this node. val inward = this val outward = this /* Debug info of nodes binding. / def bindingInfo: String = s"""$iBindingInfo \|$oBindingInfo \|""".stripMargin /* Debug info of ports connecting. / def connectedPortsInfo: String = s"""${oPorts.size} outward ports connected: [${oPorts.map(_._2.name).mkString(",")}] \|${iPorts.size} inward ports connected: [${iPorts.map(_._2.name).mkString(",")}] \|""".stripMargin /* Debug info of parameters propagations. / def parametersInfo: String = s"""${doParams.size} downstream outward parameters: [${doParams.mkString(",")}] \|${uoParams.size} upstream outward parameters: [${uoParams.mkString(",")}] \|${diParams.size} downstream inward parameters: [${diParams.mkString(",")}] \|${uiParams.size} upstream inward parameters: [${uiParams.mkString(",")}] \|""".stripMargin /* For a given node, converts [[OutwardNode.accPO]] and [[InwardNode.accPI]] to [[MixedNode.oPortMapping]] and * [[MixedNode.iPortMapping]]. * * Given counts of known inward and outward binding and inward and outward star bindings, return the resolved inward * stars and outward stars. * * This method will also validate the arguments and throw a runtime error if the values are unsuitable for this type * of node. * * @param iKnown * Number of known-size ([[BIND_ONCE]]) input bindings. * @param oKnown * Number of known-size ([[BIND_ONCE]]) output bindings. * @param iStar * Number of unknown size ([[BIND_STAR]]) input bindings. * @param oStar * Number of unknown size ([[BIND_STAR]]) output bindings. * @return * A Tuple of the resolved number of input and output connections. / protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStar: Int, oStar: Int): (Int, Int) /* Function to generate downward-flowing outward params from the downward-flowing input params and the current output * ports. * * @param n * The size of the output sequence to generate. * @param p * Sequence of downward-flowing input parameters of this node. * @return * A `n`-sized sequence of downward-flowing output edge parameters. / protected[diplomacy] def mapParamsD(n: Int, p: Seq[DI]): Seq[DO] /* Function to generate upward-flowing input parameters from the upward-flowing output parameters [[uiParams]]. * * @param n * Size of the output sequence. * @param p * Upward-flowing output edge parameters. * @return * A n-sized sequence of upward-flowing input edge parameters. / protected[diplomacy] def mapParamsU(n: Int, p: Seq[UO]): Seq[UI] /* @return * The sink cardinality of the node, the number of outputs bound with [[BIND_QUERY]] summed with inputs bound with * [[BIND_STAR]]. / protected[diplomacy] lazy val sinkCard: Int = oBindings.count(_._3 == BIND_QUERY) + iBindings.count(_._3 == BIND_STAR) /* @return * The source cardinality of this node, the number of inputs bound with [[BIND_QUERY]] summed with the number of * output bindings bound with [[BIND_STAR]]. / protected[diplomacy] lazy val sourceCard: Int = iBindings.count(_._3 == BIND_QUERY) + oBindings.count(_._3 == BIND_STAR) /* @return list of nodes involved in flex bindings with this node. / protected[diplomacy] lazy val flexes: Seq[BaseNode] = oBindings.filter(_._3 == BIND_FLEX).map(_._2) ++ iBindings.filter(_._3 == BIND_FLEX).map(_._2) /* Resolves the flex to be either source or sink and returns the offset where the [[BIND_STAR]] operators begin * greedily taking up the remaining connections. * * @return * A value >= 0 if it is sink cardinality, a negative value for source cardinality. The magnitude of the return * value is not relevant. / protected[diplomacy] lazy val flexOffset: Int = { /* Recursively performs a depth-first search of the [[flexes]], [[BaseNode]]s connected to this node with flex * operators. The algorithm bottoms out when we either get to a node we have already visited or when we get to a * connection that is not a flex and can set the direction for us. Otherwise, recurse by visiting the `flexes` of * each node in the current set and decide whether they should be added to the set or not. * * @return * the mapping of [[BaseNode]] indexed by their serial numbers. / def DFS(v: BaseNode, visited: Map[Int, BaseNode]): Map[Int, BaseNode] = { if (visited.contains(v.serial) \|\| !v.flexibleArityDirection) { visited } else { v.flexes.foldLeft(visited + (v.serial -> v))((sum, n) => DFS(n, sum)) } } /* Determine which [[BaseNode]] are involved in resolving the flex connections to/from this node. * * @example * {{{ * a := b := c * d := b * e := f * }}} * * `flexSet` for `a`, `b`, `c`, or `d` will be `Set(a, b, c, d)` `flexSet` for `e` or `f` will be `Set(e,f)` / val flexSet = DFS(this, Map()).values /* The total number of := operators where we're on the left. / val allSink = flexSet.map(_.sinkCard).sum /** The total number of :=* operators used when we're on the right. / val allSource = flexSet.map(_.sourceCard).sum require( allSink == 0 \|\| allSource == 0, s"The nodes ${flexSet.map(_.name)} which are inter-connected by :=* have ${allSink} := operators and ${allSource} := operators connected to them, making it impossible to determine cardinality inference direction." ) allSink - allSource } /** @return A value >= 0 if it is sink cardinality, a negative value for source cardinality. / protected[diplomacy] def edgeArityDirection(n: BaseNode): Int = { if (flexibleArityDirection) flexOffset else if (n.flexibleArityDirection) n.flexOffset else 0 } /* For a node which is connected between two nodes, select the one that will influence the direction of the flex * resolution. / protected[diplomacy] def edgeAritySelect(n: BaseNode, l: => Int, r: => Int): Int = { val dir = edgeArityDirection(n) if (dir < 0) l else if (dir > 0) r else 1 } /* Ensure that the same node is not visited twice in resolving `:=`, etc operators. / private var starCycleGuard = false /** Resolve all the star operators into concrete indicies. As connections are being made, some may be "star" * connections which need to be resolved. In some way to determine how many actual edges they correspond to. We also * need to build up the ranges of edges which correspond to each binding operator, so that We can apply the correct * edge parameters and later build up correct bundle connections. * * [[oPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that oPort (binding * operator). [[iPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that iPort * (binding operator). [[oStar]]: `Int` the value to return for this node `N` for any `N := foo` or `N :=* foo := bar` [[iStar]]: `Int` the value to return for this node `N` for any `foo :=* N` or `bar :=* foo := N` / protected[diplomacy] lazy val ( oPortMapping: Seq[(Int, Int)], iPortMapping: Seq[(Int, Int)], oStar: Int, iStar: Int ) = { try { if (starCycleGuard) throw StarCycleException() starCycleGuard = true // For a given node N... // Number of foo := N // + Number of bar :=* foo := N val oStars = oBindings.count { case (_, n, b, _, _) => b == BIND_STAR \|\| (b == BIND_FLEX && edgeArityDirection(n) < 0) } // Number of N := foo // + Number of N :=* foo := bar val iStars = iBindings.count { case (_, n, b, _, _) => b == BIND_STAR \|\| (b == BIND_FLEX && edgeArityDirection(n) > 0) } // 1 for foo := N // + bar.iStar for bar := foo := N // + foo.iStar for foo := N // + 0 for foo := N val oKnown = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, 0, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => 0 } }.sum // 1 for N := foo // + bar.oStar for N := foo :=* bar // + foo.oStar for N :=* foo // + 0 for N := foo val iKnown = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, 0) case BIND_QUERY => n.oStar case BIND_STAR => 0 } }.sum // Resolve star depends on the node subclass to implement the algorithm for this. val (iStar, oStar) = resolveStar(iKnown, oKnown, iStars, oStars) // Cumulative list of resolved outward binding range starting points val oSum = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, oStar, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => oStar } }.scanLeft(0)(_ + _) // Cumulative list of resolved inward binding range starting points val iSum = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, iStar) case BIND_QUERY => n.oStar case BIND_STAR => iStar } }.scanLeft(0)(_ + _) // Create ranges for each binding based on the running sums and return // those along with resolved values for the star operations. (oSum.init.zip(oSum.tail), iSum.init.zip(iSum.tail), oStar, iStar) } catch { case c: StarCycleException => throw c.copy(loop = context +: c.loop) } } /* Sequence of inward ports. * * This should be called after all star bindings are resolved. * * Each element is: `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. * `n` Instance of inward node. `p` View of [[Parameters]] where this connection was made. `s` Source info where this * connection was made in the source code. / protected[diplomacy] lazy val oDirectPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oBindings.flatMap { case (i, n, _, p, s) => // for each binding operator in this node, look at what it connects to val (start, end) = n.iPortMapping(i) (start until end).map { j => (j, n, p, s) } } /* Sequence of outward ports. * * This should be called after all star bindings are resolved. * * `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. `n` Instance of * outward node. `p` View of [[Parameters]] where this connection was made. `s` [[SourceInfo]] where this connection * was made in the source code. / protected[diplomacy] lazy val iDirectPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iBindings.flatMap { case (i, n, _, p, s) => // query this port index range of this node in the other side of node. val (start, end) = n.oPortMapping(i) (start until end).map { j => (j, n, p, s) } } // Ephemeral nodes ( which have non-None iForward/oForward) have in_degree = out_degree // Thus, there must exist an Eulerian path and the below algorithms terminate @scala.annotation.tailrec private def oTrace( tuple: (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) ): (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.iForward(i) match { case None => (i, n, p, s) case Some((j, m)) => oTrace((j, m, p, s)) } } @scala.annotation.tailrec private def iTrace( tuple: (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) ): (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.oForward(i) match { case None => (i, n, p, s) case Some((j, m)) => iTrace((j, m, p, s)) } } /* Final output ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - Numeric index of this binding in the [[InwardNode]] on the other end. * - [[InwardNode]] on the other end of this binding. * - A view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. / lazy val oPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oDirectPorts.map(oTrace) /* Final input ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - numeric index of this binding in [[OutwardNode]] on the other end. * - [[OutwardNode]] on the other end of this binding. * - a view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. / lazy val iPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iDirectPorts.map(iTrace) private var oParamsCycleGuard = false protected[diplomacy] lazy val diParams: Seq[DI] = iPorts.map { case (i, n, _, _) => n.doParams(i) } protected[diplomacy] lazy val doParams: Seq[DO] = { try { if (oParamsCycleGuard) throw DownwardCycleException() oParamsCycleGuard = true val o = mapParamsD(oPorts.size, diParams) require( o.size == oPorts.size, s"""Diplomacy has detected a problem with your graph: \|At the following node, the number of outward ports should equal the number of produced outward parameters. \|$context \|$connectedPortsInfo \|Downstreamed inward parameters: [${diParams.mkString(",")}] \|Produced outward parameters: [${o.mkString(",")}] \|""".stripMargin ) o.map(outer.mixO(_, this)) } catch { case c: DownwardCycleException => throw c.copy(loop = context +: c.loop) } } private var iParamsCycleGuard = false protected[diplomacy] lazy val uoParams: Seq[UO] = oPorts.map { case (o, n, _, _) => n.uiParams(o) } protected[diplomacy] lazy val uiParams: Seq[UI] = { try { if (iParamsCycleGuard) throw UpwardCycleException() iParamsCycleGuard = true val i = mapParamsU(iPorts.size, uoParams) require( i.size == iPorts.size, s"""Diplomacy has detected a problem with your graph: \|At the following node, the number of inward ports should equal the number of produced inward parameters. \|$context \|$connectedPortsInfo \|Upstreamed outward parameters: [${uoParams.mkString(",")}] \|Produced inward parameters: [${i.mkString(",")}] \|""".stripMargin ) i.map(inner.mixI(_, this)) } catch { case c: UpwardCycleException => throw c.copy(loop = context +: c.loop) } } /* Outward edge parameters. / protected[diplomacy] lazy val edgesOut: Seq[EO] = (oPorts.zip(doParams)).map { case ((i, n, p, s), o) => outer.edgeO(o, n.uiParams(i), p, s) } /* Inward edge parameters. / protected[diplomacy] lazy val edgesIn: Seq[EI] = (iPorts.zip(uiParams)).map { case ((o, n, p, s), i) => inner.edgeI(n.doParams(o), i, p, s) } /* A tuple of the input edge parameters and output edge parameters for the edges bound to this node. * * If you need to access to the edges of a foreign Node, use this method (in/out create bundles). / lazy val edges: Edges[EI, EO] = Edges(edgesIn, edgesOut) /* Create actual Wires corresponding to the Bundles parameterized by the outward edges of this node. / protected[diplomacy] lazy val bundleOut: Seq[BO] = edgesOut.map { e => val x = Wire(outer.bundleO(e)).suggestName(s"${valName.value}Out") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } /* Create actual Wires corresponding to the Bundles parameterized by the inward edges of this node. / protected[diplomacy] lazy val bundleIn: Seq[BI] = edgesIn.map { e => val x = Wire(inner.bundleI(e)).suggestName(s"${valName.value}In") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } private def emptyDanglesOut: Seq[Dangle] = oPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(serial, i), sink = HalfEdge(n.serial, j), flipped = false, name = wirePrefix + "out", dataOpt = None ) } private def emptyDanglesIn: Seq[Dangle] = iPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(n.serial, j), sink = HalfEdge(serial, i), flipped = true, name = wirePrefix + "in", dataOpt = None ) } /* Create the [[Dangle]]s which describe the connections from this node output to other nodes inputs. / protected[diplomacy] def danglesOut: Seq[Dangle] = emptyDanglesOut.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleOut(i))) } /* Create the [[Dangle]]s which describe the connections from this node input from other nodes outputs. / protected[diplomacy] def danglesIn: Seq[Dangle] = emptyDanglesIn.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleIn(i))) } private[diplomacy] var instantiated = false /* Gather Bundle and edge parameters of outward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. / def out: Seq[(BO, EO)] = { require( instantiated, s"$name.out should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleOut.zip(edgesOut) } /* Gather Bundle and edge parameters of inward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. / def in: Seq[(BI, EI)] = { require( instantiated, s"$name.in should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleIn.zip(edgesIn) } /* Actually instantiate this node during [[LazyModuleImp]] evaluation. Mark that it's safe to use the Bundle wires, * instantiate monitors on all input ports if appropriate, and return all the dangles of this node. / protected[diplomacy] def instantiate(): Seq[Dangle] = { instantiated = true if (!circuitIdentity) { (iPorts.zip(in)).foreach { case ((_, _, p, _), (b, e)) => if (p(MonitorsEnabled)) inner.monitor(b, e) } } danglesOut ++ danglesIn } protected[diplomacy] def cloneDangles(): Seq[Dangle] = emptyDanglesOut ++ emptyDanglesIn /* Connects the outward part of a node with the inward part of this node. / protected[diplomacy] def bind( h: OutwardNode[DI, UI, BI], binding: NodeBinding )( implicit p: Parameters, sourceInfo: SourceInfo ): Unit = { val x = this // x := y val y = h sourceLine(sourceInfo, " at ", "") val i = x.iPushed val o = y.oPushed y.oPush( i, x, binding match { case BIND_ONCE => BIND_ONCE case BIND_FLEX => BIND_FLEX case BIND_STAR => BIND_QUERY case BIND_QUERY => BIND_STAR } ) x.iPush(o, y, binding) } / Metadata for printing the node graph. / def inputs: Seq[(OutwardNode[DI, UI, BI], RenderedEdge)] = (iPorts.zip(edgesIn)).map { case ((_, n, p, _), e) => val re = inner.render(e) (n, re.copy(flipped = re.flipped != p(RenderFlipped))) } /* Metadata for printing the node graph / def outputs: Seq[(InwardNode[DO, UO, BO], RenderedEdge)] = oPorts.map { case (i, n, _, _) => (n, n.inputs(i)._2) } } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportPutFull \|\| manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB \|\| manager.anySupportGet \|\| manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportPutFull \|\| client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe \|\| client.anySupportGet \|\| client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet \|\| client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull \|\| client.anySupportPutPartial \|\| client.anySupportHint \|\| client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet \|\| manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull \|\| manager.anySupportPutPartial \|\| manager.anySupportHint \|\| manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) \|\| !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.ProbeAckData \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode \| small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U \|\| beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }	module TLError( // @[Error.scala:21:9] input clock, // @[Error.scala:21:9] input reset, // @[Error.scala:21:9] output auto_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [7:0] auto_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [13:0] auto_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [3:0] auto_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [7:0] auto_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_corrupt // @[LazyModuleImp.scala:107:25] ); wire _a_q_io_deq_valid; // @[Decoupled.scala:362:21] wire [2:0] _a_q_io_deq_bits_opcode; // @[Decoupled.scala:362:21] wire [3:0] _a_q_io_deq_bits_size; // @[Decoupled.scala:362:21] wire auto_in_a_valid_0 = auto_in_a_valid; // @[Error.scala:21:9] wire [2:0] auto_in_a_bits_opcode_0 = auto_in_a_bits_opcode; // @[Error.scala:21:9] wire [2:0] auto_in_a_bits_param_0 = auto_in_a_bits_param; // @[Error.scala:21:9] wire [3:0] auto_in_a_bits_size_0 = auto_in_a_bits_size; // @[Error.scala:21:9] wire [7:0] auto_in_a_bits_source_0 = auto_in_a_bits_source; // @[Error.scala:21:9] wire [13:0] auto_in_a_bits_address_0 = auto_in_a_bits_address; // @[Error.scala:21:9] wire [7:0] auto_in_a_bits_mask_0 = auto_in_a_bits_mask; // @[Error.scala:21:9] wire [63:0] auto_in_a_bits_data_0 = auto_in_a_bits_data; // @[Error.scala:21:9] wire auto_in_a_bits_corrupt_0 = auto_in_a_bits_corrupt; // @[Error.scala:21:9] wire auto_in_d_ready_0 = auto_in_d_ready; // @[Error.scala:21:9] wire [7:0][2:0] _GEN = '{3'h4, 3'h4, 3'h2, 3'h1, 3'h1, 3'h1, 3'h0, 3'h0}; wire auto_in_d_bits_denied = 1'h1; // @[Error.scala:21:9] wire nodeIn_d_bits_denied = 1'h1; // @[MixedNode.scala:551:17] wire da_bits_denied = 1'h1; // @[Error.scala:28:18] wire [1:0] auto_in_d_bits_param = 2'h0; // @[Error.scala:21:9] wire [1:0] nodeIn_d_bits_param = 2'h0; // @[MixedNode.scala:551:17] wire [1:0] da_bits_param = 2'h0; // @[Error.scala:28:18] wire auto_in_d_bits_sink = 1'h0; // @[Error.scala:21:9] wire nodeIn_d_bits_sink = 1'h0; // @[MixedNode.scala:551:17] wire da_bits_sink = 1'h0; // @[Error.scala:28:18] wire [63:0] auto_in_d_bits_data = 64'h0; // @[Error.scala:21:9] wire [63:0] nodeIn_d_bits_data = 64'h0; // @[MixedNode.scala:551:17] wire [63:0] da_bits_data = 64'h0; // @[Error.scala:28:18] wire [2:0] _da_bits_opcode_WIRE_6 = 3'h4; // @[Bundles.scala:47:27] wire [2:0] _da_bits_opcode_WIRE_7 = 3'h4; // @[Bundles.scala:47:27] wire [2:0] _da_bits_opcode_WIRE_5 = 3'h2; // @[Bundles.scala:47:27] wire [2:0] _da_bits_opcode_WIRE_2 = 3'h1; // @[Bundles.scala:47:27] wire [2:0] _da_bits_opcode_WIRE_3 = 3'h1; // @[Bundles.scala:47:27] wire [2:0] _da_bits_opcode_WIRE_4 = 3'h1; // @[Bundles.scala:47:27] wire [2:0] _da_bits_opcode_WIRE_0 = 3'h0; // @[Bundles.scala:47:27] wire [2:0] _da_bits_opcode_WIRE_1 = 3'h0; // @[Bundles.scala:47:27] wire nodeIn_a_ready; // @[MixedNode.scala:551:17] wire nodeIn_a_valid = auto_in_a_valid_0; // @[Error.scala:21:9] wire [2:0] nodeIn_a_bits_opcode = auto_in_a_bits_opcode_0; // @[Error.scala:21:9] wire [2:0] nodeIn_a_bits_param = auto_in_a_bits_param_0; // @[Error.scala:21:9] wire [3:0] nodeIn_a_bits_size = auto_in_a_bits_size_0; // @[Error.scala:21:9] wire [7:0] nodeIn_a_bits_source = auto_in_a_bits_source_0; // @[Error.scala:21:9] wire [13:0] nodeIn_a_bits_address = auto_in_a_bits_address_0; // @[Error.scala:21:9] wire [7:0] nodeIn_a_bits_mask = auto_in_a_bits_mask_0; // @[Error.scala:21:9] wire [63:0] nodeIn_a_bits_data = auto_in_a_bits_data_0; // @[Error.scala:21:9] wire nodeIn_a_bits_corrupt = auto_in_a_bits_corrupt_0; // @[Error.scala:21:9] wire nodeIn_d_ready = auto_in_d_ready_0; // @[Error.scala:21:9] wire nodeIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [3:0] nodeIn_d_bits_size; // @[MixedNode.scala:551:17] wire [7:0] nodeIn_d_bits_source; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_corrupt; // @[MixedNode.scala:551:17] wire auto_in_a_ready_0; // @[Error.scala:21:9] wire [2:0] auto_in_d_bits_opcode_0; // @[Error.scala:21:9] wire [3:0] auto_in_d_bits_size_0; // @[Error.scala:21:9] wire [7:0] auto_in_d_bits_source_0; // @[Error.scala:21:9] wire auto_in_d_bits_corrupt_0; // @[Error.scala:21:9] wire auto_in_d_valid_0; // @[Error.scala:21:9] assign auto_in_a_ready_0 = nodeIn_a_ready; // @[Error.scala:21:9] wire da_ready = nodeIn_d_ready; // @[Error.scala:28:18] wire da_valid; // @[Error.scala:28:18] assign auto_in_d_valid_0 = nodeIn_d_valid; // @[Error.scala:21:9] wire [2:0] da_bits_opcode; // @[Error.scala:28:18] assign auto_in_d_bits_opcode_0 = nodeIn_d_bits_opcode; // @[Error.scala:21:9] wire [3:0] da_bits_size; // @[Error.scala:28:18] assign auto_in_d_bits_size_0 = nodeIn_d_bits_size; // @[Error.scala:21:9] wire [7:0] da_bits_source; // @[Error.scala:28:18] assign auto_in_d_bits_source_0 = nodeIn_d_bits_source; // @[Error.scala:21:9] wire da_bits_corrupt; // @[Error.scala:28:18] assign auto_in_d_bits_corrupt_0 = nodeIn_d_bits_corrupt; // @[Error.scala:21:9] wire _da_valid_T_1; // @[Error.scala:36:35] assign nodeIn_d_valid = da_valid; // @[Error.scala:28:18] assign nodeIn_d_bits_opcode = da_bits_opcode; // @[Error.scala:28:18] assign nodeIn_d_bits_size = da_bits_size; // @[Error.scala:28:18] assign nodeIn_d_bits_source = da_bits_source; // @[Error.scala:28:18] wire da_bits_corrupt_opdata; // @[Edges.scala:106:36] assign nodeIn_d_bits_corrupt = da_bits_corrupt; // @[Error.scala:28:18] wire _q_io_deq_ready_T_3; // @[Error.scala:35:46] wire _a_last_T = _q_io_deq_ready_T_3 & _a_q_io_deq_valid; // @[Decoupled.scala:51:35, :362:21] wire [26:0] _a_last_beats1_decode_T = 27'hFFF << _a_q_io_deq_bits_size; // @[Decoupled.scala:362:21] wire [11:0] _a_last_beats1_decode_T_1 = _a_last_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_last_beats1_decode_T_2 = ~_a_last_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] a_last_beats1_decode = _a_last_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire _a_last_beats1_opdata_T = _a_q_io_deq_bits_opcode[2]; // @[Decoupled.scala:362:21] wire a_last_beats1_opdata = ~_a_last_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [8:0] a_last_beats1 = a_last_beats1_opdata ? a_last_beats1_decode : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [8:0] a_last_counter; // @[Edges.scala:229:27] wire [9:0] _a_last_counter1_T = {1'h0, a_last_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] a_last_counter1 = _a_last_counter1_T[8:0]; // @[Edges.scala:230:28] wire a_last_first = a_last_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _a_last_last_T = a_last_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _a_last_last_T_1 = a_last_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire a_last = _a_last_last_T \| _a_last_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_last_done = a_last & _a_last_T; // @[Decoupled.scala:51:35] wire [8:0] _a_last_count_T = ~a_last_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] a_last_count = a_last_beats1 & _a_last_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _a_last_counter_T = a_last_first ? a_last_beats1 : a_last_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire _T = da_ready & da_valid; // @[Decoupled.scala:51:35] wire [26:0] _r_beats1_decode_T = 27'hFFF << da_bits_size; // @[package.scala:243:71] wire [11:0] _r_beats1_decode_T_1 = _r_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _r_beats1_decode_T_2 = ~_r_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] r_beats1_decode = _r_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire r_beats1_opdata = da_bits_opcode[0]; // @[Edges.scala:106:36] assign da_bits_corrupt_opdata = da_bits_opcode[0]; // @[Edges.scala:106:36] wire [8:0] r_beats1 = r_beats1_opdata ? r_beats1_decode : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] r_counter; // @[Edges.scala:229:27] wire [9:0] _r_counter1_T = {1'h0, r_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] r_counter1 = _r_counter1_T[8:0]; // @[Edges.scala:230:28] wire da_first = r_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _r_last_T = r_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _r_last_T_1 = r_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire da_last = _r_last_T \| _r_last_T_1; // @[Edges.scala:232:{25,33,43}] wire r_3 = da_last & _T; // @[Decoupled.scala:51:35] wire [8:0] _r_count_T = ~r_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] r_4 = r_beats1 & _r_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _r_counter_T = da_first ? r_beats1 : r_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire _q_io_deq_ready_T = da_ready & da_last; // @[Edges.scala:232:33] wire _q_io_deq_ready_T_1 = _q_io_deq_ready_T; // @[Error.scala:35:{26,37}] wire _q_io_deq_ready_T_2 = ~a_last; // @[Edges.scala:232:33] assign _q_io_deq_ready_T_3 = _q_io_deq_ready_T_1 \| _q_io_deq_ready_T_2; // @[Error.scala:35:{37,46,49}] wire _da_valid_T = _a_q_io_deq_valid & a_last; // @[Decoupled.scala:362:21] assign _da_valid_T_1 = _da_valid_T; // @[Error.scala:36:{25,35}] assign da_valid = _da_valid_T_1; // @[Error.scala:28:18, :36:35] assign da_bits_opcode = _GEN[_a_q_io_deq_bits_opcode]; // @[Decoupled.scala:362:21] assign da_bits_corrupt = da_bits_corrupt_opdata; // @[Edges.scala:106:36] always @(posedge clock) begin // @[Error.scala:21:9] if (reset) begin // @[Error.scala:21:9] a_last_counter <= 9'h0; // @[Edges.scala:229:27] r_counter <= 9'h0; // @[Edges.scala:229:27] end else begin // @[Error.scala:21:9] if (_a_last_T) // @[Decoupled.scala:51:35] a_last_counter <= _a_last_counter_T; // @[Edges.scala:229:27, :236:21] if (_T) // @[Decoupled.scala:51:35] r_counter <= _r_counter_T; // @[Edges.scala:229:27, :236:21] end always @(posedge) TLMonitor_27 monitor ( // @[Nodes.scala:27:25] .clock (clock), .reset (reset), .io_in_a_ready (nodeIn_a_ready), // @[MixedNode.scala:551:17] .io_in_a_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17] .io_in_a_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17] .io_in_a_bits_param (nodeIn_a_bits_param), // @[MixedNode.scala:551:17] .io_in_a_bits_size (nodeIn_a_bits_size), // @[MixedNode.scala:551:17] .io_in_a_bits_source (nodeIn_a_bits_source), // @[MixedNode.scala:551:17] .io_in_a_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17] .io_in_a_bits_mask (nodeIn_a_bits_mask), // @[MixedNode.scala:551:17] .io_in_a_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17] .io_in_a_bits_corrupt (nodeIn_a_bits_corrupt), // @[MixedNode.scala:551:17] .io_in_d_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17] .io_in_d_valid (nodeIn_d_valid), // @[MixedNode.scala:551:17] .io_in_d_bits_opcode (nodeIn_d_bits_opcode), // @[MixedNode.scala:551:17] .io_in_d_bits_size (nodeIn_d_bits_size), // @[MixedNode.scala:551:17] .io_in_d_bits_source (nodeIn_d_bits_source), // @[MixedNode.scala:551:17] .io_in_d_bits_corrupt (nodeIn_d_bits_corrupt) // @[MixedNode.scala:551:17] ); // @[Nodes.scala:27:25] Queue1_TLBundleA_a14d64s8k1z4u a_q ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (nodeIn_a_ready), .io_enq_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17] .io_enq_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17] .io_enq_bits_param (nodeIn_a_bits_param), // @[MixedNode.scala:551:17] .io_enq_bits_size (nodeIn_a_bits_size), // @[MixedNode.scala:551:17] .io_enq_bits_source (nodeIn_a_bits_source), // @[MixedNode.scala:551:17] .io_enq_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17] .io_enq_bits_mask (nodeIn_a_bits_mask), // @[MixedNode.scala:551:17] .io_enq_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17] .io_enq_bits_corrupt (nodeIn_a_bits_corrupt), // @[MixedNode.scala:551:17] .io_deq_ready (_q_io_deq_ready_T_3), // @[Error.scala:35:46] .io_deq_valid (_a_q_io_deq_valid), .io_deq_bits_opcode (_a_q_io_deq_bits_opcode), .io_deq_bits_size (_a_q_io_deq_bits_size), .io_deq_bits_source (da_bits_source) ); // @[Decoupled.scala:362:21] assign da_bits_size = _a_q_io_deq_bits_size; // @[Decoupled.scala:362:21] assign auto_in_a_ready = auto_in_a_ready_0; // @[Error.scala:21:9] assign auto_in_d_valid = auto_in_d_valid_0; // @[Error.scala:21:9] assign auto_in_d_bits_opcode = auto_in_d_bits_opcode_0; // @[Error.scala:21:9] assign auto_in_d_bits_size = auto_in_d_bits_size_0; // @[Error.scala:21:9] assign auto_in_d_bits_source = auto_in_d_bits_source_0; // @[Error.scala:21:9] assign auto_in_d_bits_corrupt = auto_in_d_bits_corrupt_0; // @[Error.scala:21:9] endmodule
Generate the Verilog code corresponding to the following Chisel files. File Monitor.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceLine import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import freechips.rocketchip.diplomacy.EnableMonitors import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode} import freechips.rocketchip.util.PlusArg case class TLMonitorArgs(edge: TLEdge) abstract class TLMonitorBase(args: TLMonitorArgs) extends Module { val io = IO(new Bundle { val in = Input(new TLBundle(args.edge.bundle)) }) def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit legalize(io.in, args.edge, reset) } object TLMonitor { def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = { if (enable) { EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) } } else { node } } } class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args) { require (args.edge.params(TLMonitorStrictMode) \|\| (! args.edge.params(TestplanTestType).formal)) val cover_prop_class = PropertyClass.Default //Like assert but can flip to being an assumption for formal verification def monAssert(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir, cond, message, PropertyClass.Default) } def assume(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir.flip, cond, message, PropertyClass.Default) } def extra = { args.edge.sourceInfo match { case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)" case _ => "" } } def visible(address: UInt, source: UInt, edge: TLEdge) = edge.client.clients.map { c => !c.sourceId.contains(source) \|\| c.visibility.map(_.contains(address)).reduce(_ \|\| _) }.reduce(_ && _) def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = { //switch this flag to turn on diplomacy in error messages def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n" monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra) // Reuse these subexpressions to save some firrtl lines val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility") //The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B //TODO: check for acquireT? when (bundle.opcode === TLMessages.AcquireBlock) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra) } when (bundle.opcode === TLMessages.AcquirePerm) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra) monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra) monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra) monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra) } } def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = { monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra) monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility") // Reuse these subexpressions to save some firrtl lines val address_ok = edge.manager.containsSafe(edge.address(bundle)) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source when (bundle.opcode === TLMessages.Probe) { assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra) assume (address_ok, "'B' channel Probe carries unmanaged address" + extra) assume (legal_source, "'B' channel Probe carries source that is not first source" + extra) assume (is_aligned, "'B' channel Probe address not aligned to size" + extra) assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra) assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra) assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra) monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra) monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra) monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra) monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra) } } def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = { monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val address_ok = edge.manager.containsSafe(edge.address(bundle)) monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility") when (bundle.opcode === TLMessages.ProbeAck) { monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra) } when (bundle.opcode === TLMessages.ProbeAckData) { monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.Release) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra) monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra) } when (bundle.opcode === TLMessages.ReleaseData) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.AccessAck) { monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra) } when (bundle.opcode === TLMessages.HintAck) { monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra) } } def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = { assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val sink_ok = bundle.sink < edge.manager.endSinkId.U val deny_put_ok = edge.manager.mayDenyPut.B val deny_get_ok = edge.manager.mayDenyGet.B when (bundle.opcode === TLMessages.ReleaseAck) { assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra) assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra) assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra) } when (bundle.opcode === TLMessages.Grant) { assume (source_ok, "'D' channel Grant carries invalid source ID" + extra) assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra) assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel Grant is denied" + extra) } when (bundle.opcode === TLMessages.GrantData) { assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra) assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra) assume (!bundle.denied \|\| bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra) assume (deny_get_ok \|\| !bundle.denied, "'D' channel GrantData is denied" + extra) } when (bundle.opcode === TLMessages.AccessAck) { assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel AccessAck is denied" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra) assume (!bundle.denied \|\| bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra) assume (deny_get_ok \|\| !bundle.denied, "'D' channel AccessAckData is denied" + extra) } when (bundle.opcode === TLMessages.HintAck) { assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel HintAck is denied" + extra) } } def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = { val sink_ok = bundle.sink < edge.manager.endSinkId.U monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra) } def legalizeFormat(bundle: TLBundle, edge: TLEdge) = { when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) } when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) } when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) } when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) } } else { monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra) monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra) monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra) } } def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = { val a_first = edge.first(a.bits, a.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (a.valid && !a_first) { monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra) monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra) monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra) monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra) monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra) } when (a.fire && a_first) { opcode := a.bits.opcode param := a.bits.param size := a.bits.size source := a.bits.source address := a.bits.address } } def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = { val b_first = edge.first(b.bits, b.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (b.valid && !b_first) { monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra) monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra) monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra) monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra) monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra) } when (b.fire && b_first) { opcode := b.bits.opcode param := b.bits.param size := b.bits.size source := b.bits.source address := b.bits.address } } def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = { // Symbolic variable val sym_source = Wire(UInt(edge.client.endSourceId.W)) // TODO: Connect sym_source to a fixed value for simulation and to a // free wire in formal sym_source := 0.U // Type casting Int to UInt val maxSourceId = Wire(UInt(edge.client.endSourceId.W)) maxSourceId := edge.client.endSourceId.U // Delayed verison of sym_source val sym_source_d = Reg(UInt(edge.client.endSourceId.W)) sym_source_d := sym_source // These will be constraints for FV setup Property( MonitorDirection.Monitor, (sym_source === sym_source_d), "sym_source should remain stable", PropertyClass.Default) Property( MonitorDirection.Monitor, (sym_source <= maxSourceId), "sym_source should take legal value", PropertyClass.Default) val my_resp_pend = RegInit(false.B) val my_opcode = Reg(UInt()) val my_size = Reg(UInt()) val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire) val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire) val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source) val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source) val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat) val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend) when (my_set_resp_pend) { my_resp_pend := true.B } .elsewhen (my_clr_resp_pend) { my_resp_pend := false.B } when (my_a_first_beat) { my_opcode := bundle.a.bits.opcode my_size := bundle.a.bits.size } val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size) val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode) val my_resp_opcode_legal = Wire(Bool()) when ((my_resp_opcode === TLMessages.Get) \|\| (my_resp_opcode === TLMessages.ArithmeticData) \|\| (my_resp_opcode === TLMessages.LogicalData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData) } .elsewhen ((my_resp_opcode === TLMessages.PutFullData) \|\| (my_resp_opcode === TLMessages.PutPartialData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck) } .otherwise { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck) } monAssert (IfThen(my_resp_pend, !my_a_first_beat), "Request message should not be sent with a source ID, for which a response message" + "is already pending (not received until current cycle) for a prior request message" + "with the same source ID" + extra) assume (IfThen(my_clr_resp_pend, (my_set_resp_pend \|\| my_resp_pend)), "Response message should be accepted with a source ID only if a request message with the" + "same source ID has been accepted or is being accepted in the current cycle" + extra) assume (IfThen(my_d_first_beat, (my_a_first_beat \|\| my_resp_pend)), "Response message should be sent with a source ID only if a request message with the" + "same source ID has been accepted or is being sent in the current cycle" + extra) assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)), "If d_valid is 1, then d_size should be same as a_size of the corresponding request" + "message" + extra) assume (IfThen(my_d_first_beat, my_resp_opcode_legal), "If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" + "request message" + extra) } def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = { val c_first = edge.first(c.bits, c.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (c.valid && !c_first) { monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra) monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra) monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra) monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra) monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra) } when (c.fire && c_first) { opcode := c.bits.opcode param := c.bits.param size := c.bits.size source := c.bits.source address := c.bits.address } } def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = { val d_first = edge.first(d.bits, d.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val sink = Reg(UInt()) val denied = Reg(Bool()) when (d.valid && !d_first) { assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra) assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra) assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra) assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra) assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra) assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra) } when (d.fire && d_first) { opcode := d.bits.opcode param := d.bits.param size := d.bits.size source := d.bits.source sink := d.bits.sink denied := d.bits.denied } } def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = { legalizeMultibeatA(bundle.a, edge) legalizeMultibeatD(bundle.d, edge) if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { legalizeMultibeatB(bundle.b, edge) legalizeMultibeatC(bundle.c, edge) } } //This is left in for almond which doesn't adhere to the tilelink protocol @deprecated("Use legalizeADSource instead if possible","") def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.client.endSourceId.W)) val a_first = edge.first(bundle.a.bits, bundle.a.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val a_set = WireInit(0.U(edge.client.endSourceId.W)) when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) assume((a_set \| inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra) } if (edge.manager.minLatency > 0) { assume(a_set =/= d_clr \|\| !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight \| a_set) & ~d_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") assert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = { val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size) val log_a_size_bus_size = log2Ceil(a_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error inflight.suggestName("inflight") val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) inflight_opcodes.suggestName("inflight_opcodes") val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) inflight_sizes.suggestName("inflight_sizes") val a_first = edge.first(bundle.a.bits, bundle.a.fire) a_first.suggestName("a_first") val d_first = edge.first(bundle.d.bits, bundle.d.fire) d_first.suggestName("d_first") val a_set = WireInit(0.U(edge.client.endSourceId.W)) val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) a_set.suggestName("a_set") a_set_wo_ready.suggestName("a_set_wo_ready") val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) a_opcodes_set.suggestName("a_opcodes_set") val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) a_sizes_set.suggestName("a_sizes_set") val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W)) a_opcode_lookup.suggestName("a_opcode_lookup") a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W)) a_size_lookup.suggestName("a_size_lookup") a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant)) val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant)) val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W)) a_opcodes_set_interm.suggestName("a_opcodes_set_interm") val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W)) a_sizes_set_interm.suggestName("a_sizes_set_interm") when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) { a_set_wo_ready := UIntToOH(bundle.a.bits.source) } when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) \| 1.U a_sizes_set_interm := (bundle.a.bits.size << 1.U) \| 1.U a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U) a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U) monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) d_opcodes_clr.suggestName("d_opcodes_clr") val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) \|\| same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) \|\| (bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra) assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) \|\| (bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra) assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) { assume((!bundle.d.ready) \|\| bundle.a.ready, "ready check") } if (edge.manager.minLatency > 0) { assume(a_set_wo_ready =/= d_clr_wo_ready \|\| !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight \| a_set) & ~d_clr inflight_opcodes := (inflight_opcodes \| a_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes \| a_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = { val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size) val log_c_size_bus_size = log2Ceil(c_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) inflight.suggestName("inflight") inflight_opcodes.suggestName("inflight_opcodes") inflight_sizes.suggestName("inflight_sizes") val c_first = edge.first(bundle.c.bits, bundle.c.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) c_first.suggestName("c_first") d_first.suggestName("d_first") val c_set = WireInit(0.U(edge.client.endSourceId.W)) val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) c_set.suggestName("c_set") c_set_wo_ready.suggestName("c_set_wo_ready") c_opcodes_set.suggestName("c_opcodes_set") c_sizes_set.suggestName("c_sizes_set") val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W)) val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W)) c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U c_opcode_lookup.suggestName("c_opcode_lookup") c_size_lookup.suggestName("c_size_lookup") val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W)) val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W)) c_opcodes_set_interm.suggestName("c_opcodes_set_interm") c_sizes_set_interm.suggestName("c_sizes_set_interm") when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) { c_set_wo_ready := UIntToOH(bundle.c.bits.source) } when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) { c_set := UIntToOH(bundle.c.bits.source) c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) \| 1.U c_sizes_set_interm := (bundle.c.bits.size << 1.U) \| 1.U c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U) c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U) monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra) } val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck \|\| bundle.c.bits.opcode === TLMessages.ProbeAckData val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") d_opcodes_clr.suggestName("d_opcodes_clr") d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) \|\| same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) { assume((!bundle.d.ready) \|\| bundle.c.ready, "ready check") } if (edge.manager.minLatency > 0) { when (c_set_wo_ready.orR) { assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra) } } inflight := (inflight \| c_set) & ~d_clr inflight_opcodes := (inflight_opcodes \| c_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes \| c_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.c.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.manager.endSinkId.W)) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val e_first = true.B val d_set = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) { d_set := UIntToOH(bundle.d.bits.sink) assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra) } val e_clr = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) { e_clr := UIntToOH(bundle.e.bits.sink) monAssert((d_set \| inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra) } // edge.client.minLatency applies to BC, not DE inflight := (inflight \| d_set) & ~e_clr } def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = { val sourceBits = log2Ceil(edge.client.endSourceId) val tooBig = 14 // >16kB worth of flight information gets to be too much if (sourceBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked") } else { if (args.edge.params(TestplanTestType).simulation) { if (args.edge.params(TLMonitorStrictMode)) { legalizeADSource(bundle, edge) legalizeCDSource(bundle, edge) } else { legalizeADSourceOld(bundle, edge) } } if (args.edge.params(TestplanTestType).formal) { legalizeADSourceFormal(bundle, edge) } } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { // legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize... val sinkBits = log2Ceil(edge.manager.endSinkId) if (sinkBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked") } else { legalizeDESink(bundle, edge) } } } def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = { legalizeFormat (bundle, edge) legalizeMultibeat (bundle, edge) legalizeUnique (bundle, edge) } } File PlusArg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.experimental._ import chisel3.util.HasBlackBoxResource @deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05") case class PlusArgInfo(default: BigInt, docstring: String) /** Case class for PlusArg information * * @tparam A scala type of the PlusArg value * @param default optional default value * @param docstring text to include in the help * @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT) / private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String) /* Typeclass for converting a type to a doctype string * @tparam A some type / trait Doctypeable[A] { /* Return the doctype string for some option / def toDoctype(a: Option[A]): String } /* Object containing implementations of the Doctypeable typeclass / object Doctypes { /* Converts an Int => "INT" / implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" } /* Converts a BigInt => "INT" / implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" } /* Converts a String => "STRING" / implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" } } class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map( "FORMAT" -> StringParam(format), "DEFAULT" -> IntParam(default), "WIDTH" -> IntParam(width) )) with HasBlackBoxResource { val io = IO(new Bundle { val out = Output(UInt(width.W)) }) addResource("/vsrc/plusarg_reader.v") } / This wrapper class has no outputs, making it clear it is a simulation-only construct / class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module { val io = IO(new Bundle { val count = Input(UInt(width.W)) }) val max = Module(new plusarg_reader(format, default, docstring, width)).io.out when (max > 0.U) { assert (io.count < max, s"Timeout exceeded: $docstring") } } import Doctypes._ object PlusArg { /* PlusArg("foo") will return 42.U if the simulation is run with +foo=42 * Do not use this as an initial register value. The value is set in an * initial block and thus accessing it from another initial is racey. * Add a docstring to document the arg, which can be dumped in an elaboration * pass. / def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out } /* PlusArg.timeout(name, default, docstring)(count) will use chisel.assert * to kill the simulation when count exceeds the specified integer argument. * Default 0 will never assert. / def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count } } object PlusArgArtefacts { private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty / Add a new PlusArg / @deprecated( "Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05" ) def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring) /* Add a new PlusArg * * @tparam A scala type of the PlusArg value * @param name name for the PlusArg * @param default optional default value * @param docstring text to include in the help / def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit = artefacts = artefacts ++ Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default))) / From plus args, generate help text / private def serializeHelp_cHeader(tab: String = ""): String = artefacts .map{ case(arg, info) => s"""\|$tab+$arg=${info.doctype}\\n\\ \|$tab${" "20}${info.docstring}\\n\\ \|""".stripMargin ++ info.default.map{ case default => s"$tab${" "22}(default=${default})\\n\\\n"}.getOrElse("") }.toSeq.mkString("\\n\\\n") ++ "\"" / From plus args, generate a char array of their names / private def serializeArray_cHeader(tab: String = ""): String = { val prettyTab = tab + " " 44 // Length of 'static const ...' s"${tab}static const char * verilog_plusargs [] = {\\\n" ++ artefacts .map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" } .mkString("")++ s"${prettyTab}0};" } /* Generate C code to be included in emulator.cc that helps with * argument parsing based on available Verilog PlusArgs / def serialize_cHeader(): String = s"""\|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\ \|${serializeHelp_cHeader(" "7)} \|${serializeArray_cHeader()} \|""".stripMargin } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportPutFull \|\| manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB \|\| manager.anySupportGet \|\| manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportPutFull \|\| client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe \|\| client.anySupportGet \|\| client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet \|\| client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull \|\| client.anySupportPutPartial \|\| client.anySupportHint \|\| client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet \|\| manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull \|\| manager.anySupportPutPartial \|\| manager.anySupportHint \|\| manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) \|\| !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.ProbeAckData \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode \| small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U \|\| beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }	module TLMonitor_44( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [8:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire a_first_done = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala:51:35] reg a_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [8:0] address; // @[Monitor.scala:391:22] reg d_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [1:0] size_1; // @[Monitor.scala:540:22] reg sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] reg [1:0] inflight; // @[Monitor.scala:614:27] reg [3:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [3:0] inflight_sizes; // @[Monitor.scala:618:33] reg a_first_counter_1; // @[Edges.scala:229:27] reg d_first_counter_1; // @[Edges.scala:229:27] wire a_set = a_first_done & ~a_first_counter_1; // @[Decoupled.scala:51:35] wire d_release_ack = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala:673:46] wire _GEN = io_in_d_bits_opcode != 3'h6; // @[Monitor.scala:673:46, :674:74] reg [31:0] watchdog; // @[Monitor.scala:709:27] reg [1:0] inflight_1; // @[Monitor.scala:726:35] reg [3:0] inflight_sizes_1; // @[Monitor.scala:728:35] reg d_first_counter_2; // @[Edges.scala:229:27] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to the following Chisel files. File ShiftReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ // Similar to the Chisel ShiftRegister but allows the user to suggest a // name to the registers that get instantiated, and // to provide a reset value. object ShiftRegInit { def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T = (0 until n).foldRight(in) { case (i, next) => { val r = RegNext(next, init) name.foreach { na => r.suggestName(s"${na}_${i}") } r } } } /** These wrap behavioral * shift registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * The different types vary in their reset behavior: * AsyncResetShiftReg -- Asynchronously reset register array * A W(width) x D(depth) sized array is constructed from D instantiations of a * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg, * but only used for timing applications / abstract class AbstractPipelineReg(w: Int = 1) extends Module { val io = IO(new Bundle { val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) } ) } object AbstractPipelineReg { def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = { val chain = Module(gen) name.foreach{ chain.suggestName(_) } chain.io.d := in.asUInt chain.io.q.asTypeOf(in) } } class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) { require(depth > 0, "Depth must be greater than 0.") override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}" val chain = List.tabulate(depth) { i => Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}") } chain.last.io.d := io.d chain.last.io.en := true.B (chain.init zip chain.tail).foreach { case (sink, source) => sink.io.d := source.io.q sink.io.en := true.B } io.q := chain.head.io.q } object AsyncResetShiftReg { def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name) def apply [T <: Data](in: T, depth: Int, name: Option[String]): T = apply(in, depth, 0, name) def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T = apply(in, depth, init.litValue.toInt, name) def apply [T <: Data](in: T, depth: Int, init: T): T = apply (in, depth, init.litValue.toInt, None) } File SynchronizerReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util.{RegEnable, Cat} /* These wrap behavioral * shift and next registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * * These are built up of ResetSynchronizerPrimitiveShiftReg, intended to be replaced by the integrator's metastable flops chains or replaced * at this level if they have a multi-bit wide synchronizer primitive. * The different types vary in their reset behavior: * NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin * AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep * 1-bit-wide shift registers. * SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg * * [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference. * * ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross * Clock Domains. */ object SynchronizerResetType extends Enumeration { val NonSync, Inferred, Sync, Async = Value } // Note: this should not be used directly. // Use the companion object to generate this with the correct reset type mixin. private class SynchronizerPrimitiveShiftReg( sync: Int, init: Boolean, resetType: SynchronizerResetType.Value) extends AbstractPipelineReg(1) { val initInt = if (init) 1 else 0 val initPostfix = resetType match { case SynchronizerResetType.NonSync => "" case _ => s"_i${initInt}" } override def desiredName = s"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}" val chain = List.tabulate(sync) { i => val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B) reg.suggestName(s"sync_$i") } chain.last := io.d.asBool (chain.init zip chain.tail).foreach { case (sink, source) => sink := source } io.q := chain.head.asUInt } private object SynchronizerPrimitiveShiftReg { def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = { val gen: () => SynchronizerPrimitiveShiftReg = resetType match { case SynchronizerResetType.NonSync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) case SynchronizerResetType.Async => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset case SynchronizerResetType.Sync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset case SynchronizerResetType.Inferred => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) } AbstractPipelineReg(gen(), in) } } // Note: This module may end up with a non-AsyncReset type reset. // But the Primitives within will always have AsyncReset type. class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asAsyncReset){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async) } } io.q := Cat(output.reverse) } object AsyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } // Note: This module may end up with a non-Bool type reset. // But the Primitives within will always have Bool reset type. @deprecated("SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.", "rocket-chip 1.2") class SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asBool){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync) } } io.q := Cat(output.reverse) } object SyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred) } io.q := Cat(output.reverse) } object ResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}" val output = Seq.tabulate(w) { i => SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync) } io.q := Cat(output.reverse) } object SynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, None) def apply [T <: Data](in: T): T = apply (in, 3, None) } class ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module { override def desiredName = s"ClockCrossingReg_w${w}" val io = IO(new Bundle{ val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) val en = Input(Bool()) }) val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en) io.q := cdc_reg } object ClockCrossingReg { def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = { val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit)) name.foreach{ cdc_reg.suggestName(_) } cdc_reg.io.d := in.asUInt cdc_reg.io.en := en cdc_reg.io.q.asTypeOf(in) } }	module AsyncResetSynchronizerShiftReg_w1_d3_i0_239( // @[SynchronizerReg.scala:80:7] input clock, // @[SynchronizerReg.scala:80:7] input reset, // @[SynchronizerReg.scala:80:7] input io_d, // @[ShiftReg.scala:36:14] output io_q // @[ShiftReg.scala:36:14] ); wire io_d_0 = io_d; // @[SynchronizerReg.scala:80:7] wire _output_T = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_1 = io_d_0; // @[SynchronizerReg.scala:80:7, :87:41] wire output_0; // @[ShiftReg.scala:48:24] wire io_q_0; // @[SynchronizerReg.scala:80:7] assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_439 output_chain ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_1), // @[SynchronizerReg.scala:87:41] .io_q (output_0) ); // @[ShiftReg.scala:45:23] assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File Monitor.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceLine import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import freechips.rocketchip.diplomacy.EnableMonitors import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode} import freechips.rocketchip.util.PlusArg case class TLMonitorArgs(edge: TLEdge) abstract class TLMonitorBase(args: TLMonitorArgs) extends Module { val io = IO(new Bundle { val in = Input(new TLBundle(args.edge.bundle)) }) def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit legalize(io.in, args.edge, reset) } object TLMonitor { def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = { if (enable) { EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) } } else { node } } } class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args) { require (args.edge.params(TLMonitorStrictMode) \|\| (! args.edge.params(TestplanTestType).formal)) val cover_prop_class = PropertyClass.Default //Like assert but can flip to being an assumption for formal verification def monAssert(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir, cond, message, PropertyClass.Default) } def assume(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir.flip, cond, message, PropertyClass.Default) } def extra = { args.edge.sourceInfo match { case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)" case _ => "" } } def visible(address: UInt, source: UInt, edge: TLEdge) = edge.client.clients.map { c => !c.sourceId.contains(source) \|\| c.visibility.map(_.contains(address)).reduce(_ \|\| _) }.reduce(_ && _) def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = { //switch this flag to turn on diplomacy in error messages def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n" monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra) // Reuse these subexpressions to save some firrtl lines val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility") //The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B //TODO: check for acquireT? when (bundle.opcode === TLMessages.AcquireBlock) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra) } when (bundle.opcode === TLMessages.AcquirePerm) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra) monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra) monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra) monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra) } } def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = { monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra) monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility") // Reuse these subexpressions to save some firrtl lines val address_ok = edge.manager.containsSafe(edge.address(bundle)) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source when (bundle.opcode === TLMessages.Probe) { assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra) assume (address_ok, "'B' channel Probe carries unmanaged address" + extra) assume (legal_source, "'B' channel Probe carries source that is not first source" + extra) assume (is_aligned, "'B' channel Probe address not aligned to size" + extra) assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra) assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra) assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra) monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra) monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra) monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra) monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra) } } def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = { monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val address_ok = edge.manager.containsSafe(edge.address(bundle)) monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility") when (bundle.opcode === TLMessages.ProbeAck) { monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra) } when (bundle.opcode === TLMessages.ProbeAckData) { monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.Release) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra) monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra) } when (bundle.opcode === TLMessages.ReleaseData) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.AccessAck) { monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra) } when (bundle.opcode === TLMessages.HintAck) { monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra) } } def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = { assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val sink_ok = bundle.sink < edge.manager.endSinkId.U val deny_put_ok = edge.manager.mayDenyPut.B val deny_get_ok = edge.manager.mayDenyGet.B when (bundle.opcode === TLMessages.ReleaseAck) { assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra) assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra) assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra) } when (bundle.opcode === TLMessages.Grant) { assume (source_ok, "'D' channel Grant carries invalid source ID" + extra) assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra) assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel Grant is denied" + extra) } when (bundle.opcode === TLMessages.GrantData) { assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra) assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra) assume (!bundle.denied \|\| bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra) assume (deny_get_ok \|\| !bundle.denied, "'D' channel GrantData is denied" + extra) } when (bundle.opcode === TLMessages.AccessAck) { assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel AccessAck is denied" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra) assume (!bundle.denied \|\| bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra) assume (deny_get_ok \|\| !bundle.denied, "'D' channel AccessAckData is denied" + extra) } when (bundle.opcode === TLMessages.HintAck) { assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel HintAck is denied" + extra) } } def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = { val sink_ok = bundle.sink < edge.manager.endSinkId.U monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra) } def legalizeFormat(bundle: TLBundle, edge: TLEdge) = { when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) } when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) } when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) } when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) } } else { monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra) monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra) monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra) } } def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = { val a_first = edge.first(a.bits, a.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (a.valid && !a_first) { monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra) monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra) monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra) monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra) monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra) } when (a.fire && a_first) { opcode := a.bits.opcode param := a.bits.param size := a.bits.size source := a.bits.source address := a.bits.address } } def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = { val b_first = edge.first(b.bits, b.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (b.valid && !b_first) { monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra) monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra) monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra) monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra) monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra) } when (b.fire && b_first) { opcode := b.bits.opcode param := b.bits.param size := b.bits.size source := b.bits.source address := b.bits.address } } def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = { // Symbolic variable val sym_source = Wire(UInt(edge.client.endSourceId.W)) // TODO: Connect sym_source to a fixed value for simulation and to a // free wire in formal sym_source := 0.U // Type casting Int to UInt val maxSourceId = Wire(UInt(edge.client.endSourceId.W)) maxSourceId := edge.client.endSourceId.U // Delayed verison of sym_source val sym_source_d = Reg(UInt(edge.client.endSourceId.W)) sym_source_d := sym_source // These will be constraints for FV setup Property( MonitorDirection.Monitor, (sym_source === sym_source_d), "sym_source should remain stable", PropertyClass.Default) Property( MonitorDirection.Monitor, (sym_source <= maxSourceId), "sym_source should take legal value", PropertyClass.Default) val my_resp_pend = RegInit(false.B) val my_opcode = Reg(UInt()) val my_size = Reg(UInt()) val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire) val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire) val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source) val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source) val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat) val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend) when (my_set_resp_pend) { my_resp_pend := true.B } .elsewhen (my_clr_resp_pend) { my_resp_pend := false.B } when (my_a_first_beat) { my_opcode := bundle.a.bits.opcode my_size := bundle.a.bits.size } val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size) val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode) val my_resp_opcode_legal = Wire(Bool()) when ((my_resp_opcode === TLMessages.Get) \|\| (my_resp_opcode === TLMessages.ArithmeticData) \|\| (my_resp_opcode === TLMessages.LogicalData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData) } .elsewhen ((my_resp_opcode === TLMessages.PutFullData) \|\| (my_resp_opcode === TLMessages.PutPartialData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck) } .otherwise { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck) } monAssert (IfThen(my_resp_pend, !my_a_first_beat), "Request message should not be sent with a source ID, for which a response message" + "is already pending (not received until current cycle) for a prior request message" + "with the same source ID" + extra) assume (IfThen(my_clr_resp_pend, (my_set_resp_pend \|\| my_resp_pend)), "Response message should be accepted with a source ID only if a request message with the" + "same source ID has been accepted or is being accepted in the current cycle" + extra) assume (IfThen(my_d_first_beat, (my_a_first_beat \|\| my_resp_pend)), "Response message should be sent with a source ID only if a request message with the" + "same source ID has been accepted or is being sent in the current cycle" + extra) assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)), "If d_valid is 1, then d_size should be same as a_size of the corresponding request" + "message" + extra) assume (IfThen(my_d_first_beat, my_resp_opcode_legal), "If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" + "request message" + extra) } def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = { val c_first = edge.first(c.bits, c.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (c.valid && !c_first) { monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra) monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra) monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra) monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra) monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra) } when (c.fire && c_first) { opcode := c.bits.opcode param := c.bits.param size := c.bits.size source := c.bits.source address := c.bits.address } } def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = { val d_first = edge.first(d.bits, d.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val sink = Reg(UInt()) val denied = Reg(Bool()) when (d.valid && !d_first) { assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra) assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra) assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra) assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra) assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra) assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra) } when (d.fire && d_first) { opcode := d.bits.opcode param := d.bits.param size := d.bits.size source := d.bits.source sink := d.bits.sink denied := d.bits.denied } } def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = { legalizeMultibeatA(bundle.a, edge) legalizeMultibeatD(bundle.d, edge) if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { legalizeMultibeatB(bundle.b, edge) legalizeMultibeatC(bundle.c, edge) } } //This is left in for almond which doesn't adhere to the tilelink protocol @deprecated("Use legalizeADSource instead if possible","") def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.client.endSourceId.W)) val a_first = edge.first(bundle.a.bits, bundle.a.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val a_set = WireInit(0.U(edge.client.endSourceId.W)) when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) assume((a_set \| inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra) } if (edge.manager.minLatency > 0) { assume(a_set =/= d_clr \|\| !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight \| a_set) & ~d_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") assert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = { val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size) val log_a_size_bus_size = log2Ceil(a_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error inflight.suggestName("inflight") val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) inflight_opcodes.suggestName("inflight_opcodes") val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) inflight_sizes.suggestName("inflight_sizes") val a_first = edge.first(bundle.a.bits, bundle.a.fire) a_first.suggestName("a_first") val d_first = edge.first(bundle.d.bits, bundle.d.fire) d_first.suggestName("d_first") val a_set = WireInit(0.U(edge.client.endSourceId.W)) val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) a_set.suggestName("a_set") a_set_wo_ready.suggestName("a_set_wo_ready") val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) a_opcodes_set.suggestName("a_opcodes_set") val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) a_sizes_set.suggestName("a_sizes_set") val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W)) a_opcode_lookup.suggestName("a_opcode_lookup") a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W)) a_size_lookup.suggestName("a_size_lookup") a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant)) val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant)) val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W)) a_opcodes_set_interm.suggestName("a_opcodes_set_interm") val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W)) a_sizes_set_interm.suggestName("a_sizes_set_interm") when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) { a_set_wo_ready := UIntToOH(bundle.a.bits.source) } when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) \| 1.U a_sizes_set_interm := (bundle.a.bits.size << 1.U) \| 1.U a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U) a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U) monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) d_opcodes_clr.suggestName("d_opcodes_clr") val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) \|\| same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) \|\| (bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra) assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) \|\| (bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra) assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) { assume((!bundle.d.ready) \|\| bundle.a.ready, "ready check") } if (edge.manager.minLatency > 0) { assume(a_set_wo_ready =/= d_clr_wo_ready \|\| !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight \| a_set) & ~d_clr inflight_opcodes := (inflight_opcodes \| a_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes \| a_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = { val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size) val log_c_size_bus_size = log2Ceil(c_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) inflight.suggestName("inflight") inflight_opcodes.suggestName("inflight_opcodes") inflight_sizes.suggestName("inflight_sizes") val c_first = edge.first(bundle.c.bits, bundle.c.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) c_first.suggestName("c_first") d_first.suggestName("d_first") val c_set = WireInit(0.U(edge.client.endSourceId.W)) val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) c_set.suggestName("c_set") c_set_wo_ready.suggestName("c_set_wo_ready") c_opcodes_set.suggestName("c_opcodes_set") c_sizes_set.suggestName("c_sizes_set") val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W)) val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W)) c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U c_opcode_lookup.suggestName("c_opcode_lookup") c_size_lookup.suggestName("c_size_lookup") val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W)) val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W)) c_opcodes_set_interm.suggestName("c_opcodes_set_interm") c_sizes_set_interm.suggestName("c_sizes_set_interm") when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) { c_set_wo_ready := UIntToOH(bundle.c.bits.source) } when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) { c_set := UIntToOH(bundle.c.bits.source) c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) \| 1.U c_sizes_set_interm := (bundle.c.bits.size << 1.U) \| 1.U c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U) c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U) monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra) } val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck \|\| bundle.c.bits.opcode === TLMessages.ProbeAckData val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") d_opcodes_clr.suggestName("d_opcodes_clr") d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) \|\| same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) { assume((!bundle.d.ready) \|\| bundle.c.ready, "ready check") } if (edge.manager.minLatency > 0) { when (c_set_wo_ready.orR) { assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra) } } inflight := (inflight \| c_set) & ~d_clr inflight_opcodes := (inflight_opcodes \| c_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes \| c_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.c.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.manager.endSinkId.W)) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val e_first = true.B val d_set = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) { d_set := UIntToOH(bundle.d.bits.sink) assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra) } val e_clr = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) { e_clr := UIntToOH(bundle.e.bits.sink) monAssert((d_set \| inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra) } // edge.client.minLatency applies to BC, not DE inflight := (inflight \| d_set) & ~e_clr } def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = { val sourceBits = log2Ceil(edge.client.endSourceId) val tooBig = 14 // >16kB worth of flight information gets to be too much if (sourceBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked") } else { if (args.edge.params(TestplanTestType).simulation) { if (args.edge.params(TLMonitorStrictMode)) { legalizeADSource(bundle, edge) legalizeCDSource(bundle, edge) } else { legalizeADSourceOld(bundle, edge) } } if (args.edge.params(TestplanTestType).formal) { legalizeADSourceFormal(bundle, edge) } } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { // legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize... val sinkBits = log2Ceil(edge.manager.endSinkId) if (sinkBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked") } else { legalizeDESink(bundle, edge) } } } def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = { legalizeFormat (bundle, edge) legalizeMultibeat (bundle, edge) legalizeUnique (bundle, edge) } } File Misc.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import scala.math._ class ParameterizedBundle(implicit p: Parameters) extends Bundle trait Clocked extends Bundle { val clock = Clock() val reset = Bool() } object DecoupledHelper { def apply(rvs: Bool) = new DecoupledHelper(rvs) } class DecoupledHelper(val rvs: Seq[Bool]) { def fire(exclude: Bool, includes: Bool) = { require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!") (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _) } def fire() = { rvs.reduce(_ && _) } } object MuxT { def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2)) def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3)) def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4)) } /** Creates a cascade of n MuxTs to search for a key value. / object MuxTLookup { def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } } object ValidMux { def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]): ValidIO[T] = { apply(v1 +: v2.toSeq) } def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = { val out = Wire(Valid(valids.head.bits.cloneType)) out.valid := valids.map(_.valid).reduce(_ \|\| _) out.bits := MuxCase(valids.head.bits, valids.map(v => (v.valid -> v.bits))) out } } object Str { def apply(s: String): UInt = { var i = BigInt(0) require(s.forall(validChar _)) for (c <- s) i = (i << 8) \| c i.U((s.length8).W) } def apply(x: Char): UInt = { require(validChar(x)) x.U(8.W) } def apply(x: UInt): UInt = apply(x, 10) def apply(x: UInt, radix: Int): UInt = { val rad = radix.U val w = x.getWidth require(w > 0) var q = x var s = digit(q % rad) for (i <- 1 until ceil(log(2)/log(radix)w).toInt) { q = q / rad s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s) } s } def apply(x: SInt): UInt = apply(x, 10) def apply(x: SInt, radix: Int): UInt = { val neg = x < 0.S val abs = x.abs.asUInt if (radix != 10) { Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix)) } else { val rad = radix.U val w = abs.getWidth require(w > 0) var q = abs var s = digit(q % rad) var needSign = neg for (i <- 1 until ceil(log(2)/log(radix)w).toInt) { q = q / rad val placeSpace = q === 0.U val space = Mux(needSign, Str('-'), Str(' ')) needSign = needSign && !placeSpace s = Cat(Mux(placeSpace, space, digit(q % rad)), s) } Cat(Mux(needSign, Str('-'), Str(' ')), s) } } private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0) private def validChar(x: Char) = x == (x & 0xFF) } object Split { def apply(x: UInt, n0: Int) = { val w = x.getWidth (x.extract(w-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n2: Int, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } } object Random { def apply(mod: Int, random: UInt): UInt = { if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0) else PriorityEncoder(partition(apply(1 << log2Up(mod8), random), mod)) } def apply(mod: Int): UInt = apply(mod, randomizer) def oneHot(mod: Int, random: UInt): UInt = { if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0)) else PriorityEncoderOH(partition(apply(1 << log2Up(mod8), random), mod)).asUInt } def oneHot(mod: Int): UInt = oneHot(mod, randomizer) private def randomizer = LFSR(16) private def partition(value: UInt, slices: Int) = Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U) } object Majority { def apply(in: Set[Bool]): Bool = { val n = (in.size >> 1) + 1 val clauses = in.subsets(n).map(_.reduce(_ && _)) clauses.reduce(_ \|\| _) } def apply(in: Seq[Bool]): Bool = apply(in.toSet) def apply(in: UInt): Bool = apply(in.asBools.toSet) } object PopCountAtLeast { private def two(x: UInt): (Bool, Bool) = x.getWidth match { case 1 => (x.asBool, false.B) case n => val half = x.getWidth / 2 val (leftOne, leftTwo) = two(x(half - 1, 0)) val (rightOne, rightTwo) = two(x(x.getWidth - 1, half)) (leftOne \|\| rightOne, leftTwo \|\| rightTwo \|\| (leftOne && rightOne)) } def apply(x: UInt, n: Int): Bool = n match { case 0 => true.B case 1 => x.orR case 2 => two(x)._2 case 3 => PopCount(x) >= n.U } } // This gets used everywhere, so make the smallest circuit possible ... // Given an address and size, create a mask of beatBytes size // eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111 // groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01 object MaskGen { def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = { require (groupBy >= 1 && beatBytes >= groupBy) require (isPow2(beatBytes) && isPow2(groupBy)) val lgBytes = log2Ceil(beatBytes) val sizeOH = UIntToOH(lgSize \| 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) \| (groupBy2 - 1).U def helper(i: Int): Seq[(Bool, Bool)] = { if (i == 0) { Seq((lgSize >= lgBytes.asUInt, true.B)) } else { val sub = helper(i-1) val size = sizeOH(lgBytes - i) val bit = addr_lo(lgBytes - i) val nbit = !bit Seq.tabulate (1 << i) { j => val (sub_acc, sub_eq) = sub(j/2) val eq = sub_eq && (if (j % 2 == 1) bit else nbit) val acc = sub_acc \|\| (size && eq) (acc, eq) } } } if (groupBy == beatBytes) 1.U else Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse) } } File PlusArg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.experimental._ import chisel3.util.HasBlackBoxResource @deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05") case class PlusArgInfo(default: BigInt, docstring: String) /** Case class for PlusArg information * * @tparam A scala type of the PlusArg value * @param default optional default value * @param docstring text to include in the help * @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT) / private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String) /* Typeclass for converting a type to a doctype string * @tparam A some type / trait Doctypeable[A] { /* Return the doctype string for some option / def toDoctype(a: Option[A]): String } /* Object containing implementations of the Doctypeable typeclass / object Doctypes { /* Converts an Int => "INT" / implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" } /* Converts a BigInt => "INT" / implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" } /* Converts a String => "STRING" / implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" } } class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map( "FORMAT" -> StringParam(format), "DEFAULT" -> IntParam(default), "WIDTH" -> IntParam(width) )) with HasBlackBoxResource { val io = IO(new Bundle { val out = Output(UInt(width.W)) }) addResource("/vsrc/plusarg_reader.v") } / This wrapper class has no outputs, making it clear it is a simulation-only construct / class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module { val io = IO(new Bundle { val count = Input(UInt(width.W)) }) val max = Module(new plusarg_reader(format, default, docstring, width)).io.out when (max > 0.U) { assert (io.count < max, s"Timeout exceeded: $docstring") } } import Doctypes._ object PlusArg { /* PlusArg("foo") will return 42.U if the simulation is run with +foo=42 * Do not use this as an initial register value. The value is set in an * initial block and thus accessing it from another initial is racey. * Add a docstring to document the arg, which can be dumped in an elaboration * pass. / def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out } /* PlusArg.timeout(name, default, docstring)(count) will use chisel.assert * to kill the simulation when count exceeds the specified integer argument. * Default 0 will never assert. / def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count } } object PlusArgArtefacts { private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty / Add a new PlusArg / @deprecated( "Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05" ) def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring) /* Add a new PlusArg * * @tparam A scala type of the PlusArg value * @param name name for the PlusArg * @param default optional default value * @param docstring text to include in the help / def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit = artefacts = artefacts ++ Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default))) / From plus args, generate help text / private def serializeHelp_cHeader(tab: String = ""): String = artefacts .map{ case(arg, info) => s"""\|$tab+$arg=${info.doctype}\\n\\ \|$tab${" "20}${info.docstring}\\n\\ \|""".stripMargin ++ info.default.map{ case default => s"$tab${" "22}(default=${default})\\n\\\n"}.getOrElse("") }.toSeq.mkString("\\n\\\n") ++ "\"" / From plus args, generate a char array of their names / private def serializeArray_cHeader(tab: String = ""): String = { val prettyTab = tab + " " 44 // Length of 'static const ...' s"${tab}static const char * verilog_plusargs [] = {\\\n" ++ artefacts .map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" } .mkString("")++ s"${prettyTab}0};" } /* Generate C code to be included in emulator.cc that helps with * argument parsing based on available Verilog PlusArgs / def serialize_cHeader(): String = s"""\|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\ \|${serializeHelp_cHeader(" "7)} \|${serializeArray_cHeader()} \|""".stripMargin } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /* Like Vec.apply(idx), but tolerates indices of mismatched width / def extract(idx: UInt): T = x((idx \| 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx \| 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def \| (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a \|\| b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_\|\|_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /* Any Data subtype that has a Bool member named valid. / type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /* converts from camel case to to underscores, also removing all spaces / def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /* converts spaces or underscores to hyphens, also lowering case / def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y \| (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y \|\| y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 \| 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /* Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation / def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Bundles.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import freechips.rocketchip.util._ import scala.collection.immutable.ListMap import chisel3.util.Decoupled import chisel3.util.DecoupledIO import chisel3.reflect.DataMirror abstract class TLBundleBase(val params: TLBundleParameters) extends Bundle // common combos in lazy policy: // Put + Acquire // Release + AccessAck object TLMessages { // A B C D E def PutFullData = 0.U // . . => AccessAck def PutPartialData = 1.U // . . => AccessAck def ArithmeticData = 2.U // . . => AccessAckData def LogicalData = 3.U // . . => AccessAckData def Get = 4.U // . . => AccessAckData def Hint = 5.U // . . => HintAck def AcquireBlock = 6.U // . => Grant[Data] def AcquirePerm = 7.U // . => Grant[Data] def Probe = 6.U // . => ProbeAck[Data] def AccessAck = 0.U // . . def AccessAckData = 1.U // . . def HintAck = 2.U // . . def ProbeAck = 4.U // . def ProbeAckData = 5.U // . def Release = 6.U // . => ReleaseAck def ReleaseData = 7.U // . => ReleaseAck def Grant = 4.U // . => GrantAck def GrantData = 5.U // . => GrantAck def ReleaseAck = 6.U // . def GrantAck = 0.U // . def isA(x: UInt) = x <= AcquirePerm def isB(x: UInt) = x <= Probe def isC(x: UInt) = x <= ReleaseData def isD(x: UInt) = x <= ReleaseAck def adResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, Grant, Grant) def bcResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, ProbeAck, ProbeAck) def a = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("AcquireBlock",TLPermissions.PermMsgGrow), ("AcquirePerm",TLPermissions.PermMsgGrow)) def b = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("Probe",TLPermissions.PermMsgCap)) def c = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("ProbeAck",TLPermissions.PermMsgReport), ("ProbeAckData",TLPermissions.PermMsgReport), ("Release",TLPermissions.PermMsgReport), ("ReleaseData",TLPermissions.PermMsgReport)) def d = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("Grant",TLPermissions.PermMsgCap), ("GrantData",TLPermissions.PermMsgCap), ("ReleaseAck",TLPermissions.PermMsgReserved)) } /* * The three primary TileLink permissions are: * (T)runk: the agent is (or is on inwards path to) the global point of serialization. * (B)ranch: the agent is on an outwards path to * (N)one: * These permissions are permuted by transfer operations in various ways. * Operations can cap permissions, request for them to be grown or shrunk, * or for a report on their current status. / object TLPermissions { val aWidth = 2 val bdWidth = 2 val cWidth = 3 // Cap types (Grant = new permissions, Probe = permisions <= target) def toT = 0.U(bdWidth.W) def toB = 1.U(bdWidth.W) def toN = 2.U(bdWidth.W) def isCap(x: UInt) = x <= toN // Grow types (Acquire = permissions >= target) def NtoB = 0.U(aWidth.W) def NtoT = 1.U(aWidth.W) def BtoT = 2.U(aWidth.W) def isGrow(x: UInt) = x <= BtoT // Shrink types (ProbeAck, Release) def TtoB = 0.U(cWidth.W) def TtoN = 1.U(cWidth.W) def BtoN = 2.U(cWidth.W) def isShrink(x: UInt) = x <= BtoN // Report types (ProbeAck, Release) def TtoT = 3.U(cWidth.W) def BtoB = 4.U(cWidth.W) def NtoN = 5.U(cWidth.W) def isReport(x: UInt) = x <= NtoN def PermMsgGrow:Seq[String] = Seq("Grow NtoB", "Grow NtoT", "Grow BtoT") def PermMsgCap:Seq[String] = Seq("Cap toT", "Cap toB", "Cap toN") def PermMsgReport:Seq[String] = Seq("Shrink TtoB", "Shrink TtoN", "Shrink BtoN", "Report TotT", "Report BtoB", "Report NtoN") def PermMsgReserved:Seq[String] = Seq("Reserved") } object TLAtomics { val width = 3 // Arithmetic types def MIN = 0.U(width.W) def MAX = 1.U(width.W) def MINU = 2.U(width.W) def MAXU = 3.U(width.W) def ADD = 4.U(width.W) def isArithmetic(x: UInt) = x <= ADD // Logical types def XOR = 0.U(width.W) def OR = 1.U(width.W) def AND = 2.U(width.W) def SWAP = 3.U(width.W) def isLogical(x: UInt) = x <= SWAP def ArithMsg:Seq[String] = Seq("MIN", "MAX", "MINU", "MAXU", "ADD") def LogicMsg:Seq[String] = Seq("XOR", "OR", "AND", "SWAP") } object TLHints { val width = 1 def PREFETCH_READ = 0.U(width.W) def PREFETCH_WRITE = 1.U(width.W) def isHints(x: UInt) = x <= PREFETCH_WRITE def HintsMsg:Seq[String] = Seq("PrefetchRead", "PrefetchWrite") } sealed trait TLChannel extends TLBundleBase { val channelName: String } sealed trait TLDataChannel extends TLChannel sealed trait TLAddrChannel extends TLDataChannel final class TLBundleA(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleA_${params.shortName}" val channelName = "'A' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(List(TLAtomics.width, TLPermissions.aWidth, TLHints.width).max.W) // amo_opcode \|\| grow perms \|\| hint val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleB(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleB_${params.shortName}" val channelName = "'B' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val address = UInt(params.addressBits.W) // from // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleC(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleC_${params.shortName}" val channelName = "'C' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.cWidth.W) // shrink or report perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleD(params: TLBundleParameters) extends TLBundleBase(params) with TLDataChannel { override def typeName = s"TLBundleD_${params.shortName}" val channelName = "'D' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val sink = UInt(params.sinkBits.W) // from val denied = Bool() // implies corrupt iff Data val user = BundleMap(params.responseFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleE(params: TLBundleParameters) extends TLBundleBase(params) with TLChannel { override def typeName = s"TLBundleE_${params.shortName}" val channelName = "'E' channel" val sink = UInt(params.sinkBits.W) // to } class TLBundle(val params: TLBundleParameters) extends Record { // Emulate a Bundle with elements abcde or ad depending on params.hasBCE private val optA = Some (Decoupled(new TLBundleA(params))) private val optB = params.hasBCE.option(Flipped(Decoupled(new TLBundleB(params)))) private val optC = params.hasBCE.option(Decoupled(new TLBundleC(params))) private val optD = Some (Flipped(Decoupled(new TLBundleD(params)))) private val optE = params.hasBCE.option(Decoupled(new TLBundleE(params))) def a: DecoupledIO[TLBundleA] = optA.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleA(params))))) def b: DecoupledIO[TLBundleB] = optB.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleB(params))))) def c: DecoupledIO[TLBundleC] = optC.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleC(params))))) def d: DecoupledIO[TLBundleD] = optD.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleD(params))))) def e: DecoupledIO[TLBundleE] = optE.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleE(params))))) val elements = if (params.hasBCE) ListMap("e" -> e, "d" -> d, "c" -> c, "b" -> b, "a" -> a) else ListMap("d" -> d, "a" -> a) def tieoff(): Unit = { DataMirror.specifiedDirectionOf(a.ready) match { case SpecifiedDirection.Input => a.ready := false.B c.ready := false.B e.ready := false.B b.valid := false.B d.valid := false.B case SpecifiedDirection.Output => a.valid := false.B c.valid := false.B e.valid := false.B b.ready := false.B d.ready := false.B case _ => } } } object TLBundle { def apply(params: TLBundleParameters) = new TLBundle(params) } class TLAsyncBundleBase(val params: TLAsyncBundleParameters) extends Bundle class TLAsyncBundle(params: TLAsyncBundleParameters) extends TLAsyncBundleBase(params) { val a = new AsyncBundle(new TLBundleA(params.base), params.async) val b = Flipped(new AsyncBundle(new TLBundleB(params.base), params.async)) val c = new AsyncBundle(new TLBundleC(params.base), params.async) val d = Flipped(new AsyncBundle(new TLBundleD(params.base), params.async)) val e = new AsyncBundle(new TLBundleE(params.base), params.async) } class TLRationalBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = RationalIO(new TLBundleA(params)) val b = Flipped(RationalIO(new TLBundleB(params))) val c = RationalIO(new TLBundleC(params)) val d = Flipped(RationalIO(new TLBundleD(params))) val e = RationalIO(new TLBundleE(params)) } class TLCreditedBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = CreditedIO(new TLBundleA(params)) val b = Flipped(CreditedIO(new TLBundleB(params))) val c = CreditedIO(new TLBundleC(params)) val d = Flipped(CreditedIO(new TLBundleD(params))) val e = CreditedIO(new TLBundleE(params)) } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.diplomacy import chisel3._ import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor} import freechips.rocketchip.util.ShiftQueue /** Options for describing the attributes of memory regions / object RegionType { // Define the 'more relaxed than' ordering val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS) sealed trait T extends Ordered[T] { def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this) } case object CACHED extends T // an intermediate agent may have cached a copy of the region for you case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively } // A non-empty half-open range; [start, end) case class IdRange(start: Int, end: Int) extends Ordered[IdRange] { require (start >= 0, s"Ids cannot be negative, but got: $start.") require (start <= end, "Id ranges cannot be negative.") def compare(x: IdRange) = { val primary = (this.start - x.start).signum val secondary = (x.end - this.end).signum if (primary != 0) primary else secondary } def overlaps(x: IdRange) = start < x.end && x.start < end def contains(x: IdRange) = start <= x.start && x.end <= end def contains(x: Int) = start <= x && x < end def contains(x: UInt) = if (size == 0) { false.B } else if (size == 1) { // simple comparison x === start.U } else { // find index of largest different bit val largestDeltaBit = log2Floor(start ^ (end-1)) val smallestCommonBit = largestDeltaBit + 1 // may not exist in x val uncommonMask = (1 << smallestCommonBit) - 1 val uncommonBits = (x \| 0.U(smallestCommonBit.W))(largestDeltaBit, 0) // the prefix must match exactly (note: may shift ALL bits away) (x >> smallestCommonBit) === (start >> smallestCommonBit).U && // firrtl constant prop range analysis can eliminate these two: (start & uncommonMask).U <= uncommonBits && uncommonBits <= ((end-1) & uncommonMask).U } def shift(x: Int) = IdRange(start+x, end+x) def size = end - start def isEmpty = end == start def range = start until end } object IdRange { def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else { val ranges = s.sorted (ranges.tail zip ranges.init) find { case (a, b) => a overlaps b } } } // An potentially empty inclusive range of 2-powers [min, max] (in bytes) case class TransferSizes(min: Int, max: Int) { def this(x: Int) = this(x, x) require (min <= max, s"Min transfer $min > max transfer $max") require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)") require (max == 0 \|\| isPow2(max), s"TransferSizes must be a power of 2, got: $max") require (min == 0 \|\| isPow2(min), s"TransferSizes must be a power of 2, got: $min") require (max == 0 \|\| min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)") def none = min == 0 def contains(x: Int) = isPow2(x) && min <= x && x <= max def containsLg(x: Int) = contains(1 << x) def containsLg(x: UInt) = if (none) false.B else if (min == max) { log2Ceil(min).U === x } else { log2Ceil(min).U <= x && x <= log2Ceil(max).U } def contains(x: TransferSizes) = x.none \|\| (min <= x.min && x.max <= max) def intersect(x: TransferSizes) = if (x.max < min \|\| max < x.min) TransferSizes.none else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max)) // Not a union, because the result may contain sizes contained by neither term // NOT TO BE CONFUSED WITH COVERPOINTS def mincover(x: TransferSizes) = { if (none) { x } else if (x.none) { this } else { TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max)) } } override def toString() = "TransferSizes[%d, %d]".format(min, max) } object TransferSizes { def apply(x: Int) = new TransferSizes(x) val none = new TransferSizes(0) def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _) def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _) implicit def asBool(x: TransferSizes) = !x.none } // AddressSets specify the address space managed by the manager // Base is the base address, and mask are the bits consumed by the manager // e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff // e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ... case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet] { // Forbid misaligned base address (and empty sets) require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}") require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous // We do allow negative mask (=> ignore all high bits) def contains(x: BigInt) = ((x ^ base) & ~mask) == 0 def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S // turn x into an address contained in this set def legalize(x: UInt): UInt = base.U \| (mask.U & x) // overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1) def overlaps(x: AddressSet) = (~(mask \| x.mask) & (base ^ x.base)) == 0 // contains iff bitwise: x.mask => mask && contains(x.base) def contains(x: AddressSet) = ((x.mask \| (base ^ x.base)) & ~mask) == 0 // The number of bytes to which the manager must be aligned def alignment = ((mask + 1) & ~mask) // Is this a contiguous memory range def contiguous = alignment == mask+1 def finite = mask >= 0 def max = { require (finite, "Max cannot be calculated on infinite mask"); base \| mask } // Widen the match function to ignore all bits in imask def widen(imask: BigInt) = AddressSet(base & ~imask, mask \| imask) // Return an AddressSet that only contains the addresses both sets contain def intersect(x: AddressSet): Option[AddressSet] = { if (!overlaps(x)) { None } else { val r_mask = mask & x.mask val r_base = base \| x.base Some(AddressSet(r_base, r_mask)) } } def subtract(x: AddressSet): Seq[AddressSet] = { intersect(x) match { case None => Seq(this) case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit => val nmask = (mask & (bit-1)) \| remove.mask val nbase = (remove.base ^ bit) & ~nmask AddressSet(nbase, nmask) } } } // AddressSets have one natural Ordering (the containment order, if contiguous) def compare(x: AddressSet) = { val primary = (this.base - x.base).signum // smallest address first val secondary = (x.mask - this.mask).signum // largest mask first if (primary != 0) primary else secondary } // We always want to see things in hex override def toString() = { if (mask >= 0) { "AddressSet(0x%x, 0x%x)".format(base, mask) } else { "AddressSet(0x%x, ~0x%x)".format(base, ~mask) } } def toRanges = { require (finite, "Ranges cannot be calculated on infinite mask") val size = alignment val fragments = mask & ~(size-1) val bits = bitIndexes(fragments) (BigInt(0) until (BigInt(1) << bits.size)).map { i => val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) } AddressRange(off, size) } } } object AddressSet { val everything = AddressSet(0, -1) def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = { if (size == 0) tail.reverse else { val maxBaseAlignment = base & (-base) // 0 for infinite (LSB) val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size val step = if (maxBaseAlignment == 0 \|\| maxBaseAlignment > maxSizeAlignment) maxSizeAlignment else maxBaseAlignment misaligned(base+step, size-step, AddressSet(base, step-1) +: tail) } } def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = { // Pair terms up by ignoring 'bit' seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) => if (seq.size == 1) { seq.head // singleton -> unaffected } else { key.copy(mask = key.mask \| bit) // pair - widen mask by bit } }.toList } def unify(seq: Seq[AddressSet]): Seq[AddressSet] = { val bits = seq.map(_.base).foldLeft(BigInt(0))(_ \| _) AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted } def enumerateMask(mask: BigInt): Seq[BigInt] = { def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] = if (id == mask) (id +: tail).reverse else helper(((~mask \| id) + 1) & mask, id +: tail) helper(0, Nil) } def enumerateBits(mask: BigInt): Seq[BigInt] = { def helper(x: BigInt): Seq[BigInt] = { if (x == 0) { Nil } else { val bit = x & (-x) bit +: helper(x & ~bit) } } helper(mask) } } case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean) { require (depth >= 0, "Buffer depth must be >= 0") def isDefined = depth > 0 def latency = if (isDefined && !flow) 1 else 0 def apply[T <: Data](x: DecoupledIO[T]) = if (isDefined) Queue(x, depth, flow=flow, pipe=pipe) else x def irrevocable[T <: Data](x: ReadyValidIO[T]) = if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe) else x def sq[T <: Data](x: DecoupledIO[T]) = if (!isDefined) x else { val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe)) sq.io.enq <> x sq.io.deq } override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "") } object BufferParams { implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false) val default = BufferParams(2) val none = BufferParams(0) val flow = BufferParams(1, true, false) val pipe = BufferParams(1, false, true) } case class TriStateValue(value: Boolean, set: Boolean) { def update(orig: Boolean) = if (set) value else orig } object TriStateValue { implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true) def unset = TriStateValue(false, false) } trait DirectedBuffers[T] { def copyIn(x: BufferParams): T def copyOut(x: BufferParams): T def copyInOut(x: BufferParams): T } trait IdMapEntry { def name: String def from: IdRange def to: IdRange def isCache: Boolean def requestFifo: Boolean def maxTransactionsInFlight: Option[Int] def pretty(fmt: String) = if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5 fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } else { fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } } abstract class IdMap[T <: IdMapEntry] { protected val fmt: String val mapping: Seq[T] def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n") } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportPutFull \|\| manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB \|\| manager.anySupportGet \|\| manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportPutFull \|\| client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe \|\| client.anySupportGet \|\| client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet \|\| client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull \|\| client.anySupportPutPartial \|\| client.anySupportHint \|\| client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet \|\| manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull \|\| manager.anySupportPutPartial \|\| manager.anySupportHint \|\| manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) \|\| !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.ProbeAckData \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode \| small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U \|\| beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }	module TLMonitor_54( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [1:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [10:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [16:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [10:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [1:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [10:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [16:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [10:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_sink = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_denied = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire _source_ok_T = 1'h0; // @[Parameters.scala:54:10] wire _source_ok_T_6 = 1'h0; // @[Parameters.scala:54:10] wire sink_ok = 1'h0; // @[Monitor.scala:309:31] wire a_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire a_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire a_first_count = 1'h0; // @[Edges.scala:234:25] wire d_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire d_first_count = 1'h0; // @[Edges.scala:234:25] wire a_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59] wire a_first_beats1_1 = 1'h0; // @[Edges.scala:221:14] wire a_first_count_1 = 1'h0; // @[Edges.scala:234:25] wire d_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1_1 = 1'h0; // @[Edges.scala:221:14] wire d_first_count_1 = 1'h0; // @[Edges.scala:234:25] wire d_release_ack = 1'h0; // @[Monitor.scala:673:46] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire c_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_first_count_T = 1'h0; // @[Edges.scala:234:27] wire c_first_count = 1'h0; // @[Edges.scala:234:25] wire _c_first_counter_T = 1'h0; // @[Edges.scala:236:21] wire d_first_beats1_decode_2 = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1_2 = 1'h0; // @[Edges.scala:221:14] wire d_first_count_2 = 1'h0; // @[Edges.scala:234:25] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire d_release_ack_1 = 1'h0; // @[Monitor.scala:783:46] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire _source_ok_T_1 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:54:67] wire _source_ok_T_7 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_8 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:54:67] wire _a_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire a_first_last = 1'h1; // @[Edges.scala:232:33] wire d_first_beats1_opdata = 1'h1; // @[Edges.scala:106:36] wire _d_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire d_first_last = 1'h1; // @[Edges.scala:232:33] wire _a_first_last_T_3 = 1'h1; // @[Edges.scala:232:43] wire a_first_last_1 = 1'h1; // @[Edges.scala:232:33] wire d_first_beats1_opdata_1 = 1'h1; // @[Edges.scala:106:36] wire _d_first_last_T_3 = 1'h1; // @[Edges.scala:232:43] wire d_first_last_1 = 1'h1; // @[Edges.scala:232:33] wire c_first_counter1 = 1'h1; // @[Edges.scala:230:28] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire d_first_beats1_opdata_2 = 1'h1; // @[Edges.scala:106:36] wire _d_first_last_T_5 = 1'h1; // @[Edges.scala:232:43] wire d_first_last_2 = 1'h1; // @[Edges.scala:232:33] wire [1:0] _c_first_counter1_T = 2'h3; // @[Edges.scala:230:28] wire [1:0] io_in_d_bits_param = 2'h0; // @[Monitor.scala:36:7] wire [1:0] _c_first_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_first_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_first_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_first_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_set_wo_ready_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_set_wo_ready_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_opcodes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_opcodes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_sizes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_sizes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_opcodes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_opcodes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_sizes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_sizes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_probe_ack_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_probe_ack_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_probe_ack_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_probe_ack_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_4_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_5_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [2:0] io_in_d_bits_opcode = 3'h1; // @[Monitor.scala:36:7] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] _c_sizes_set_interm_T_1 = 3'h1; // @[Monitor.scala:766:59] wire [4159:0] _inflight_opcodes_T_4 = 4160'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF; // @[Monitor.scala:815:62] wire [4159:0] _inflight_sizes_T_4 = 4160'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF; // @[Monitor.scala:816:58] wire [1039:0] _inflight_T_4 = 1040'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF; // @[Monitor.scala:814:46] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [16:0] _c_first_WIRE_bits_address = 17'h0; // @[Bundles.scala:265:74] wire [16:0] _c_first_WIRE_1_bits_address = 17'h0; // @[Bundles.scala:265:61] wire [16:0] _c_first_WIRE_2_bits_address = 17'h0; // @[Bundles.scala:265:74] wire [16:0] _c_first_WIRE_3_bits_address = 17'h0; // @[Bundles.scala:265:61] wire [16:0] _c_set_wo_ready_WIRE_bits_address = 17'h0; // @[Bundles.scala:265:74] wire [16:0] _c_set_wo_ready_WIRE_1_bits_address = 17'h0; // @[Bundles.scala:265:61] wire [16:0] _c_set_WIRE_bits_address = 17'h0; // @[Bundles.scala:265:74] wire [16:0] _c_set_WIRE_1_bits_address = 17'h0; // @[Bundles.scala:265:61] wire [16:0] _c_opcodes_set_interm_WIRE_bits_address = 17'h0; // @[Bundles.scala:265:74] wire [16:0] _c_opcodes_set_interm_WIRE_1_bits_address = 17'h0; // @[Bundles.scala:265:61] wire [16:0] _c_sizes_set_interm_WIRE_bits_address = 17'h0; // @[Bundles.scala:265:74] wire [16:0] _c_sizes_set_interm_WIRE_1_bits_address = 17'h0; // @[Bundles.scala:265:61] wire [16:0] _c_opcodes_set_WIRE_bits_address = 17'h0; // @[Bundles.scala:265:74] wire [16:0] _c_opcodes_set_WIRE_1_bits_address = 17'h0; // @[Bundles.scala:265:61] wire [16:0] _c_sizes_set_WIRE_bits_address = 17'h0; // @[Bundles.scala:265:74] wire [16:0] _c_sizes_set_WIRE_1_bits_address = 17'h0; // @[Bundles.scala:265:61] wire [16:0] _c_probe_ack_WIRE_bits_address = 17'h0; // @[Bundles.scala:265:74] wire [16:0] _c_probe_ack_WIRE_1_bits_address = 17'h0; // @[Bundles.scala:265:61] wire [16:0] _c_probe_ack_WIRE_2_bits_address = 17'h0; // @[Bundles.scala:265:74] wire [16:0] _c_probe_ack_WIRE_3_bits_address = 17'h0; // @[Bundles.scala:265:61] wire [16:0] _same_cycle_resp_WIRE_bits_address = 17'h0; // @[Bundles.scala:265:74] wire [16:0] _same_cycle_resp_WIRE_1_bits_address = 17'h0; // @[Bundles.scala:265:61] wire [16:0] _same_cycle_resp_WIRE_2_bits_address = 17'h0; // @[Bundles.scala:265:74] wire [16:0] _same_cycle_resp_WIRE_3_bits_address = 17'h0; // @[Bundles.scala:265:61] wire [16:0] _same_cycle_resp_WIRE_4_bits_address = 17'h0; // @[Bundles.scala:265:74] wire [16:0] _same_cycle_resp_WIRE_5_bits_address = 17'h0; // @[Bundles.scala:265:61] wire [10:0] _c_first_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_first_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_first_WIRE_2_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_first_WIRE_3_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_set_wo_ready_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_set_wo_ready_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_set_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_set_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_opcodes_set_interm_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_opcodes_set_interm_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_sizes_set_interm_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_sizes_set_interm_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_opcodes_set_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_opcodes_set_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_sizes_set_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_sizes_set_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_probe_ack_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_probe_ack_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_probe_ack_WIRE_2_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_probe_ack_WIRE_3_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _same_cycle_resp_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _same_cycle_resp_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _same_cycle_resp_WIRE_2_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _same_cycle_resp_WIRE_3_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _same_cycle_resp_WIRE_4_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _same_cycle_resp_WIRE_5_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_beats1_decode_T_2 = 3'h0; // @[package.scala:243:46] wire [2:0] c_sizes_set_interm = 3'h0; // @[Monitor.scala:755:40] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_T = 3'h0; // @[Monitor.scala:766:51] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [4159:0] c_opcodes_set = 4160'h0; // @[Monitor.scala:740:34] wire [4159:0] c_sizes_set = 4160'h0; // @[Monitor.scala:741:34] wire [4159:0] d_opcodes_clr_1 = 4160'h0; // @[Monitor.scala:776:34] wire [4159:0] d_sizes_clr_1 = 4160'h0; // @[Monitor.scala:777:34] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [1039:0] c_set = 1040'h0; // @[Monitor.scala:738:34] wire [1039:0] c_set_wo_ready = 1040'h0; // @[Monitor.scala:739:34] wire [1039:0] d_clr_1 = 1040'h0; // @[Monitor.scala:774:34] wire [1039:0] d_clr_wo_ready_1 = 1040'h0; // @[Monitor.scala:775:34] wire [16385:0] _c_sizes_set_T_1 = 16386'h0; // @[Monitor.scala:768:52] wire [13:0] _c_opcodes_set_T = 14'h0; // @[Monitor.scala:767:79] wire [13:0] _c_sizes_set_T = 14'h0; // @[Monitor.scala:768:77] wire [16386:0] _c_opcodes_set_T_1 = 16387'h0; // @[Monitor.scala:767:54] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [2047:0] _c_set_wo_ready_T = 2048'h1; // @[OneHot.scala:58:35] wire [2047:0] _c_set_T = 2048'h1; // @[OneHot.scala:58:35] wire [2:0] _c_first_beats1_decode_T_1 = 3'h7; // @[package.scala:243:76] wire [5:0] _c_first_beats1_decode_T = 6'h7; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48] wire [10:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _source_ok_uncommonBits_T_1 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] source_ok_uncommonBits = _source_ok_uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_4 = source_ok_uncommonBits < 11'h410; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_5 = _source_ok_T_4; // @[Parameters.scala:56:48, :57:20] wire _source_ok_WIRE_0 = _source_ok_T_5; // @[Parameters.scala:1138:31] wire [5:0] _GEN = 6'h7 << io_in_a_bits_size_0; // @[package.scala:243:71] wire [5:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [5:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [5:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [2:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[2:0]; // @[package.scala:243:{71,76}] wire [2:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [16:0] _is_aligned_T = {14'h0, io_in_a_bits_address_0[2:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 17'h0; // @[Edges.scala:21:{16,24}] wire [2:0] _mask_sizeOH_T = {1'h0, io_in_a_bits_size_0}; // @[Misc.scala:202:34] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = &io_in_a_bits_size_0; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 \| _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 \| _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 \| _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 \| _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 \| _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 \| _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 \| _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 \| _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [10:0] uncommonBits = _uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_1 = _uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_2 = _uncommonBits_T_2; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_3 = _uncommonBits_T_3; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_4 = _uncommonBits_T_4; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_5 = _uncommonBits_T_5; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_6 = _uncommonBits_T_6; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_7 = _uncommonBits_T_7; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_8 = _uncommonBits_T_8; // @[Parameters.scala:52:{29,56}] wire [10:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_10 = source_ok_uncommonBits_1 < 11'h410; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_11 = _source_ok_T_10; // @[Parameters.scala:56:48, :57:20] wire _source_ok_WIRE_1_0 = _source_ok_T_11; // @[Parameters.scala:1138:31] wire _T_659 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_659; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_659; // @[Decoupled.scala:51:35] wire a_first_done = _a_first_T; // @[Decoupled.scala:51:35] wire [2:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] reg a_first_counter; // @[Edges.scala:229:27] wire _a_first_last_T = a_first_counter; // @[Edges.scala:229:27, :232:25] wire [1:0] _a_first_counter1_T = {1'h0, a_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28] wire a_first_counter1 = _a_first_counter1_T[0]; // @[Edges.scala:230:28] wire a_first = ~a_first_counter; // @[Edges.scala:229:27, :231:25] wire _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire _a_first_counter_T = ~a_first & a_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [1:0] size; // @[Monitor.scala:389:22] reg [10:0] source; // @[Monitor.scala:390:22] reg [16:0] address; // @[Monitor.scala:391:22] wire _T_727 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_727; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_727; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_727; // @[Decoupled.scala:51:35] wire d_first_done = _d_first_T; // @[Decoupled.scala:51:35] wire [5:0] _GEN_0 = 6'h7 << io_in_d_bits_size_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [2:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] reg d_first_counter; // @[Edges.scala:229:27] wire _d_first_last_T = d_first_counter; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T = {1'h0, d_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1 = _d_first_counter1_T[0]; // @[Edges.scala:230:28] wire d_first = ~d_first_counter; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T = ~d_first & d_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [1:0] size_1; // @[Monitor.scala:540:22] reg [10:0] source_1; // @[Monitor.scala:541:22] reg [1039:0] inflight; // @[Monitor.scala:614:27] reg [4159:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [4159:0] inflight_sizes; // @[Monitor.scala:618:33] wire a_first_done_1 = _a_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] reg a_first_counter_1; // @[Edges.scala:229:27] wire _a_first_last_T_2 = a_first_counter_1; // @[Edges.scala:229:27, :232:25] wire [1:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28] wire a_first_counter1_1 = _a_first_counter1_T_1[0]; // @[Edges.scala:230:28] wire a_first_1 = ~a_first_counter_1; // @[Edges.scala:229:27, :231:25] wire _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire _a_first_counter_T_1 = ~a_first_1 & a_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21] wire d_first_done_1 = _d_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] reg d_first_counter_1; // @[Edges.scala:229:27] wire _d_first_last_T_2 = d_first_counter_1; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1_1 = _d_first_counter1_T_1[0]; // @[Edges.scala:230:28] wire d_first_1 = ~d_first_counter_1; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T_1 = ~d_first_1 & d_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21] wire [1039:0] a_set; // @[Monitor.scala:626:34] wire [1039:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [4159:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [4159:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [13:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [13:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [13:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :641:65] wire [13:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [13:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :681:99] wire [13:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [13:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :750:67] wire [13:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [13:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :791:99] wire [4159:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [4159:0] _a_opcode_lookup_T_6 = {4156'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [4159:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[4159:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [3:0] a_size_lookup; // @[Monitor.scala:639:33] wire [4159:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [4159:0] _a_size_lookup_T_6 = {4156'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}] wire [4159:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[4159:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [2:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [2047:0] _GEN_2 = 2048'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [2047:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_2; // @[OneHot.scala:58:35] wire [2047:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_2; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[1039:0] : 1040'h0; // @[OneHot.scala:58:35] wire _T_592 = _T_659 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_592 ? _a_set_T[1039:0] : 1040'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_592 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [2:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [2:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[2:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_592 ? _a_sizes_set_interm_T_1 : 3'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [13:0] _GEN_3 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [13:0] _a_opcodes_set_T; // @[Monitor.scala:659:79] assign _a_opcodes_set_T = _GEN_3; // @[Monitor.scala:659:79] wire [13:0] _a_sizes_set_T; // @[Monitor.scala:660:77] assign _a_sizes_set_T = _GEN_3; // @[Monitor.scala:659:79, :660:77] wire [16386:0] _a_opcodes_set_T_1 = {16383'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_592 ? _a_opcodes_set_T_1[4159:0] : 4160'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [16385:0] _a_sizes_set_T_1 = {16383'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_592 ? _a_sizes_set_T_1[4159:0] : 4160'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [1039:0] d_clr; // @[Monitor.scala:664:34] wire [1039:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [4159:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [4159:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _T_638 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [2047:0] _GEN_4 = 2048'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [2047:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_4; // @[OneHot.scala:58:35] wire [2047:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_4; // @[OneHot.scala:58:35] wire [2047:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_4; // @[OneHot.scala:58:35] wire [2047:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_4; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_638 ? _d_clr_wo_ready_T[1039:0] : 1040'h0; // @[OneHot.scala:58:35] wire _T_605 = _T_727 & d_first_1; // @[Decoupled.scala:51:35] assign d_clr = _T_605 ? _d_clr_T[1039:0] : 1040'h0; // @[OneHot.scala:58:35] wire [16398:0] _d_opcodes_clr_T_5 = 16399'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_605 ? _d_opcodes_clr_T_5[4159:0] : 4160'h0; // @[Monitor.scala:668:33, :678:{25,89}, :680:{21,76}] wire [16398:0] _d_sizes_clr_T_5 = 16399'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_605 ? _d_sizes_clr_T_5[4159:0] : 4160'h0; // @[Monitor.scala:670:31, :678:{25,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [1039:0] _inflight_T = inflight \| a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [1039:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [1039:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [4159:0] _inflight_opcodes_T = inflight_opcodes \| a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [4159:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [4159:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [4159:0] _inflight_sizes_T = inflight_sizes \| a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [4159:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [4159:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [1039:0] inflight_1; // @[Monitor.scala:726:35] wire [1039:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [4159:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [4159:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [4159:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [4159:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire d_first_done_2 = _d_first_T_2; // @[Decoupled.scala:51:35] wire [2:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] reg d_first_counter_2; // @[Edges.scala:229:27] wire _d_first_last_T_4 = d_first_counter_2; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1_2 = _d_first_counter1_T_2[0]; // @[Edges.scala:230:28] wire d_first_2 = ~d_first_counter_2; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T_2 = ~d_first_2 & d_first_counter1_2; // @[Edges.scala:230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [3:0] c_size_lookup; // @[Monitor.scala:748:35] wire [4159:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [4159:0] _c_opcode_lookup_T_6 = {4156'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [4159:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[4159:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [4159:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [4159:0] _c_size_lookup_T_6 = {4156'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}] wire [4159:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[4159:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [16398:0] _d_opcodes_clr_T_11 = 16399'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] wire [16398:0] _d_sizes_clr_T_11 = 16399'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 11'h0; // @[Monitor.scala:36:7, :795:113] wire [1039:0] _inflight_T_5 = _inflight_T_3; // @[Monitor.scala:814:{35,44}] wire [4159:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3; // @[Monitor.scala:815:{43,60}] wire [4159:0] _inflight_sizes_T_5 = _inflight_sizes_T_3; // @[Monitor.scala:816:{41,56}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to the following Chisel files. File EgressUnit.scala: package constellation.router import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.{Field, Parameters} import freechips.rocketchip.util._ import constellation.channel._ import constellation.routing.{FlowRoutingBundle} class EgressUnit(coupleSAVA: Boolean, combineSAST: Boolean, inParams: Seq[ChannelParams], ingressParams: Seq[IngressChannelParams], cParam: EgressChannelParams) (implicit p: Parameters) extends AbstractOutputUnit(inParams, ingressParams, cParam)(p) { class EgressUnitIO extends AbstractOutputUnitIO(inParams, ingressParams, cParam) { val out = Decoupled(new EgressFlit(cParam.payloadBits)) } val io = IO(new EgressUnitIO) val channel_empty = RegInit(true.B) val flow = Reg(new FlowRoutingBundle) val q = Module(new Queue(new EgressFlit(cParam.payloadBits), 3 - (if (combineSAST) 1 else 0), flow=true)) q.io.enq.valid := io.in(0).valid q.io.enq.bits.head := io.in(0).bits.head q.io.enq.bits.tail := io.in(0).bits.tail val flows = cParam.possibleFlows.toSeq if (flows.size == 0) { q.io.enq.bits.ingress_id := 0.U(1.W) } else { q.io.enq.bits.ingress_id := Mux1H( flows.map(f => (f.ingressNode.U === io.in(0).bits.flow.ingress_node && f.ingressNodeId.U === io.in(0).bits.flow.ingress_node_id)), flows.map(f => f.ingressId.U(ingressIdBits.W)) ) } q.io.enq.bits.payload := io.in(0).bits.payload io.out <> q.io.deq assert(!(q.io.enq.valid && !q.io.enq.ready)) io.credit_available(0) := q.io.count === 0.U io.channel_status(0).occupied := !channel_empty io.channel_status(0).flow := flow when (io.credit_alloc(0).alloc && io.credit_alloc(0).tail) { channel_empty := true.B if (coupleSAVA) io.channel_status(0).occupied := false.B } when (io.allocs(0).alloc) { channel_empty := false.B flow := io.allocs(0).flow } }	module EgressUnit_15( // @[EgressUnit.scala:12:7] input clock, // @[EgressUnit.scala:12:7] input reset, // @[EgressUnit.scala:12:7] input io_in_0_valid, // @[EgressUnit.scala:18:14] input io_in_0_bits_head, // @[EgressUnit.scala:18:14] input io_in_0_bits_tail, // @[EgressUnit.scala:18:14] input [72:0] io_in_0_bits_payload, // @[EgressUnit.scala:18:14] input [3:0] io_in_0_bits_flow_ingress_node, // @[EgressUnit.scala:18:14] input [2:0] io_in_0_bits_flow_ingress_node_id, // @[EgressUnit.scala:18:14] output io_credit_available_0, // @[EgressUnit.scala:18:14] output io_channel_status_0_occupied, // @[EgressUnit.scala:18:14] input io_allocs_0_alloc, // @[EgressUnit.scala:18:14] input io_credit_alloc_0_alloc, // @[EgressUnit.scala:18:14] input io_credit_alloc_0_tail, // @[EgressUnit.scala:18:14] output io_out_valid, // @[EgressUnit.scala:18:14] output io_out_bits_head, // @[EgressUnit.scala:18:14] output io_out_bits_tail, // @[EgressUnit.scala:18:14] output [72:0] io_out_bits_payload // @[EgressUnit.scala:18:14] ); wire _q_io_enq_ready; // @[EgressUnit.scala:22:17] wire [1:0] _q_io_count; // @[EgressUnit.scala:22:17] reg channel_empty; // @[EgressUnit.scala:20:30] wire _q_io_enq_bits_ingress_id_T_10 = io_in_0_bits_flow_ingress_node_id == 3'h2; // @[EgressUnit.scala:32:27]
Generate the Verilog code corresponding to the following Chisel files. File PMA.scala: // See LICENSE.SiFive for license details. // See LICENSE.Berkeley for license details. package freechips.rocketchip.rocket import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config._ import freechips.rocketchip.devices.debug.DebugModuleKey import freechips.rocketchip.diplomacy.RegionType import freechips.rocketchip.subsystem.CacheBlockBytes import freechips.rocketchip.tile.{CoreModule, CoreBundle} import freechips.rocketchip.tilelink.{TLSlavePortParameters, TLManagerParameters} class PMAChecker(manager: TLSlavePortParameters)(implicit p: Parameters) extends CoreModule()(p) { val io = IO(new Bundle { val paddr = Input(UInt()) val resp = Output(new Bundle { val cacheable = Bool() val r = Bool() val w = Bool() val pp = Bool() val al = Bool() val aa = Bool() val x = Bool() val eff = Bool() }) }) // PMA // check exist a slave can consume this address. val legal_address = manager.findSafe(io.paddr).reduce(_\|\|_) // check utility to help check SoC property. def fastCheck(member: TLManagerParameters => Boolean) = legal_address && manager.fastProperty(io.paddr, member, (b:Boolean) => b.B) io.resp.cacheable := fastCheck(_.supportsAcquireB) io.resp.r := fastCheck(_.supportsGet) io.resp.w := fastCheck(_.supportsPutFull) io.resp.pp := fastCheck(_.supportsPutPartial) io.resp.al := fastCheck(_.supportsLogical) io.resp.aa := fastCheck(_.supportsArithmetic) io.resp.x := fastCheck(_.executable) io.resp.eff := fastCheck(Seq(RegionType.PUT_EFFECTS, RegionType.GET_EFFECTS) contains _.regionType) } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.diplomacy import chisel3._ import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor} import freechips.rocketchip.util.ShiftQueue /** Options for describing the attributes of memory regions */ object RegionType { // Define the 'more relaxed than' ordering val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS) sealed trait T extends Ordered[T] { def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this) } case object CACHED extends T // an intermediate agent may have cached a copy of the region for you case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively } // A non-empty half-open range; [start, end) case class IdRange(start: Int, end: Int) extends Ordered[IdRange] { require (start >= 0, s"Ids cannot be negative, but got: $start.") require (start <= end, "Id ranges cannot be negative.") def compare(x: IdRange) = { val primary = (this.start - x.start).signum val secondary = (x.end - this.end).signum if (primary != 0) primary else secondary } def overlaps(x: IdRange) = start < x.end && x.start < end def contains(x: IdRange) = start <= x.start && x.end <= end def contains(x: Int) = start <= x && x < end def contains(x: UInt) = if (size == 0) { false.B } else if (size == 1) { // simple comparison x === start.U } else { // find index of largest different bit val largestDeltaBit = log2Floor(start ^ (end-1)) val smallestCommonBit = largestDeltaBit + 1 // may not exist in x val uncommonMask = (1 << smallestCommonBit) - 1 val uncommonBits = (x \| 0.U(smallestCommonBit.W))(largestDeltaBit, 0) // the prefix must match exactly (note: may shift ALL bits away) (x >> smallestCommonBit) === (start >> smallestCommonBit).U && // firrtl constant prop range analysis can eliminate these two: (start & uncommonMask).U <= uncommonBits && uncommonBits <= ((end-1) & uncommonMask).U } def shift(x: Int) = IdRange(start+x, end+x) def size = end - start def isEmpty = end == start def range = start until end } object IdRange { def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else { val ranges = s.sorted (ranges.tail zip ranges.init) find { case (a, b) => a overlaps b } } } // An potentially empty inclusive range of 2-powers [min, max] (in bytes) case class TransferSizes(min: Int, max: Int) { def this(x: Int) = this(x, x) require (min <= max, s"Min transfer $min > max transfer $max") require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)") require (max == 0 \|\| isPow2(max), s"TransferSizes must be a power of 2, got: $max") require (min == 0 \|\| isPow2(min), s"TransferSizes must be a power of 2, got: $min") require (max == 0 \|\| min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)") def none = min == 0 def contains(x: Int) = isPow2(x) && min <= x && x <= max def containsLg(x: Int) = contains(1 << x) def containsLg(x: UInt) = if (none) false.B else if (min == max) { log2Ceil(min).U === x } else { log2Ceil(min).U <= x && x <= log2Ceil(max).U } def contains(x: TransferSizes) = x.none \|\| (min <= x.min && x.max <= max) def intersect(x: TransferSizes) = if (x.max < min \|\| max < x.min) TransferSizes.none else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max)) // Not a union, because the result may contain sizes contained by neither term // NOT TO BE CONFUSED WITH COVERPOINTS def mincover(x: TransferSizes) = { if (none) { x } else if (x.none) { this } else { TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max)) } } override def toString() = "TransferSizes[%d, %d]".format(min, max) } object TransferSizes { def apply(x: Int) = new TransferSizes(x) val none = new TransferSizes(0) def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _) def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _) implicit def asBool(x: TransferSizes) = !x.none } // AddressSets specify the address space managed by the manager // Base is the base address, and mask are the bits consumed by the manager // e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff // e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ... case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet] { // Forbid misaligned base address (and empty sets) require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}") require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous // We do allow negative mask (=> ignore all high bits) def contains(x: BigInt) = ((x ^ base) & ~mask) == 0 def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S // turn x into an address contained in this set def legalize(x: UInt): UInt = base.U \| (mask.U & x) // overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1) def overlaps(x: AddressSet) = (~(mask \| x.mask) & (base ^ x.base)) == 0 // contains iff bitwise: x.mask => mask && contains(x.base) def contains(x: AddressSet) = ((x.mask \| (base ^ x.base)) & ~mask) == 0 // The number of bytes to which the manager must be aligned def alignment = ((mask + 1) & ~mask) // Is this a contiguous memory range def contiguous = alignment == mask+1 def finite = mask >= 0 def max = { require (finite, "Max cannot be calculated on infinite mask"); base \| mask } // Widen the match function to ignore all bits in imask def widen(imask: BigInt) = AddressSet(base & ~imask, mask \| imask) // Return an AddressSet that only contains the addresses both sets contain def intersect(x: AddressSet): Option[AddressSet] = { if (!overlaps(x)) { None } else { val r_mask = mask & x.mask val r_base = base \| x.base Some(AddressSet(r_base, r_mask)) } } def subtract(x: AddressSet): Seq[AddressSet] = { intersect(x) match { case None => Seq(this) case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit => val nmask = (mask & (bit-1)) \| remove.mask val nbase = (remove.base ^ bit) & ~nmask AddressSet(nbase, nmask) } } } // AddressSets have one natural Ordering (the containment order, if contiguous) def compare(x: AddressSet) = { val primary = (this.base - x.base).signum // smallest address first val secondary = (x.mask - this.mask).signum // largest mask first if (primary != 0) primary else secondary } // We always want to see things in hex override def toString() = { if (mask >= 0) { "AddressSet(0x%x, 0x%x)".format(base, mask) } else { "AddressSet(0x%x, ~0x%x)".format(base, ~mask) } } def toRanges = { require (finite, "Ranges cannot be calculated on infinite mask") val size = alignment val fragments = mask & ~(size-1) val bits = bitIndexes(fragments) (BigInt(0) until (BigInt(1) << bits.size)).map { i => val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) } AddressRange(off, size) } } } object AddressSet { val everything = AddressSet(0, -1) def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = { if (size == 0) tail.reverse else { val maxBaseAlignment = base & (-base) // 0 for infinite (LSB) val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size val step = if (maxBaseAlignment == 0 \|\| maxBaseAlignment > maxSizeAlignment) maxSizeAlignment else maxBaseAlignment misaligned(base+step, size-step, AddressSet(base, step-1) +: tail) } } def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = { // Pair terms up by ignoring 'bit' seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) => if (seq.size == 1) { seq.head // singleton -> unaffected } else { key.copy(mask = key.mask \| bit) // pair - widen mask by bit } }.toList } def unify(seq: Seq[AddressSet]): Seq[AddressSet] = { val bits = seq.map(_.base).foldLeft(BigInt(0))(_ \| _) AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted } def enumerateMask(mask: BigInt): Seq[BigInt] = { def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] = if (id == mask) (id +: tail).reverse else helper(((~mask \| id) + 1) & mask, id +: tail) helper(0, Nil) } def enumerateBits(mask: BigInt): Seq[BigInt] = { def helper(x: BigInt): Seq[BigInt] = { if (x == 0) { Nil } else { val bit = x & (-x) bit +: helper(x & ~bit) } } helper(mask) } } case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean) { require (depth >= 0, "Buffer depth must be >= 0") def isDefined = depth > 0 def latency = if (isDefined && !flow) 1 else 0 def apply[T <: Data](x: DecoupledIO[T]) = if (isDefined) Queue(x, depth, flow=flow, pipe=pipe) else x def irrevocable[T <: Data](x: ReadyValidIO[T]) = if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe) else x def sq[T <: Data](x: DecoupledIO[T]) = if (!isDefined) x else { val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe)) sq.io.enq <> x sq.io.deq } override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "") } object BufferParams { implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false) val default = BufferParams(2) val none = BufferParams(0) val flow = BufferParams(1, true, false) val pipe = BufferParams(1, false, true) } case class TriStateValue(value: Boolean, set: Boolean) { def update(orig: Boolean) = if (set) value else orig } object TriStateValue { implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true) def unset = TriStateValue(false, false) } trait DirectedBuffers[T] { def copyIn(x: BufferParams): T def copyOut(x: BufferParams): T def copyInOut(x: BufferParams): T } trait IdMapEntry { def name: String def from: IdRange def to: IdRange def isCache: Boolean def requestFifo: Boolean def maxTransactionsInFlight: Option[Int] def pretty(fmt: String) = if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5 fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } else { fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } } abstract class IdMap[T <: IdMapEntry] { protected val fmt: String val mapping: Seq[T] def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n") }	module PMAChecker_2( // @[PMA.scala:18:7] input clock, // @[PMA.scala:18:7] input reset, // @[PMA.scala:18:7] input [48:0] io_paddr, // @[PMA.scala:19:14] output io_resp_cacheable, // @[PMA.scala:19:14] output io_resp_r, // @[PMA.scala:19:14] output io_resp_w, // @[PMA.scala:19:14] output io_resp_pp, // @[PMA.scala:19:14] output io_resp_al, // @[PMA.scala:19:14] output io_resp_aa, // @[PMA.scala:19:14] output io_resp_x, // @[PMA.scala:19:14] output io_resp_eff // @[PMA.scala:19:14] ); wire [48:0] io_paddr_0 = io_paddr; // @[PMA.scala:18:7] wire [49:0] _io_resp_r_T_2 = 50'h0; // @[Parameters.scala:137:46] wire [49:0] _io_resp_r_T_3 = 50'h0; // @[Parameters.scala:137:46] wire _io_resp_r_T_4 = 1'h1; // @[Parameters.scala:137:59] wire _io_resp_cacheable_T_28 = 1'h0; // @[Mux.scala:30:73] wire _io_resp_w_T_47 = 1'h0; // @[Mux.scala:30:73] wire _io_resp_pp_T_47 = 1'h0; // @[Mux.scala:30:73] wire _io_resp_al_T_47 = 1'h0; // @[Mux.scala:30:73] wire _io_resp_aa_T_47 = 1'h0; // @[Mux.scala:30:73] wire _io_resp_x_T_65 = 1'h0; // @[Mux.scala:30:73] wire _io_resp_eff_T_59 = 1'h0; // @[Mux.scala:30:73] wire [48:0] _legal_address_T = io_paddr_0; // @[PMA.scala:18:7] wire [48:0] _io_resp_cacheable_T = io_paddr_0; // @[PMA.scala:18:7] wire _io_resp_cacheable_T_31; // @[PMA.scala:39:19] wire [48:0] _io_resp_r_T = io_paddr_0; // @[PMA.scala:18:7] wire [48:0] _io_resp_w_T = io_paddr_0; // @[PMA.scala:18:7] wire [48:0] _io_resp_pp_T = io_paddr_0; // @[PMA.scala:18:7] wire [48:0] _io_resp_al_T = io_paddr_0; // @[PMA.scala:18:7] wire [48:0] _io_resp_aa_T = io_paddr_0; // @[PMA.scala:18:7] wire [48:0] _io_resp_x_T = io_paddr_0; // @[PMA.scala:18:7] wire [48:0] _io_resp_eff_T = io_paddr_0; // @[PMA.scala:18:7] wire _io_resp_r_T_5; // @[PMA.scala:39:19] wire _io_resp_w_T_49; // @[PMA.scala:39:19] wire _io_resp_pp_T_49; // @[PMA.scala:39:19] wire _io_resp_al_T_49; // @[PMA.scala:39:19] wire _io_resp_aa_T_49; // @[PMA.scala:39:19] wire _io_resp_x_T_67; // @[PMA.scala:39:19] wire _io_resp_eff_T_61; // @[PMA.scala:39:19] wire io_resp_cacheable_0; // @[PMA.scala:18:7] wire io_resp_r_0; // @[PMA.scala:18:7] wire io_resp_w_0; // @[PMA.scala:18:7] wire io_resp_pp_0; // @[PMA.scala:18:7] wire io_resp_al_0; // @[PMA.scala:18:7] wire io_resp_aa_0; // @[PMA.scala:18:7] wire io_resp_x_0; // @[PMA.scala:18:7] wire io_resp_eff_0; // @[PMA.scala:18:7] wire [49:0] _legal_address_T_1 = {1'h0, _legal_address_T}; // @[Parameters.scala:137:{31,41}] wire [49:0] _legal_address_T_2 = _legal_address_T_1 & 50'h3FFFFFFFFF000; // @[Parameters.scala:137:{41,46}] wire [49:0] _legal_address_T_3 = _legal_address_T_2; // @[Parameters.scala:137:46] wire _legal_address_T_4 = _legal_address_T_3 == 50'h0; // @[Parameters.scala:137:{46,59}] wire _legal_address_WIRE_0 = _legal_address_T_4; // @[Parameters.scala:612:40] wire [48:0] _GEN = {io_paddr_0[48:13], io_paddr_0[12:0] ^ 13'h1000}; // @[PMA.scala:18:7] wire [48:0] _legal_address_T_5; // @[Parameters.scala:137:31] assign _legal_address_T_5 = _GEN; // @[Parameters.scala:137:31] wire [48:0] _io_resp_x_T_29; // @[Parameters.scala:137:31] assign _io_resp_x_T_29 = _GEN; // @[Parameters.scala:137:31] wire [49:0] _legal_address_T_6 = {1'h0, _legal_address_T_5}; // @[Parameters.scala:137:{31,41}] wire [49:0] _legal_address_T_7 = _legal_address_T_6 & 50'h3FFFFFFFFF000; // @[Parameters.scala:137:{41,46}] wire [49:0] _legal_address_T_8 = _legal_address_T_7; // @[Parameters.scala:137:46] wire _legal_address_T_9 = _legal_address_T_8 == 50'h0; // @[Parameters.scala:137:{46,59}] wire _legal_address_WIRE_1 = _legal_address_T_9; // @[Parameters.scala:612:40] wire [48:0] _GEN_0 = {io_paddr_0[48:14], io_paddr_0[13:0] ^ 14'h3000}; // @[PMA.scala:18:7] wire [48:0] _legal_address_T_10; // @[Parameters.scala:137:31] assign _legal_address_T_10 = _GEN_0; // @[Parameters.scala:137:31] wire [48:0] _io_resp_x_T_5; // @[Parameters.scala:137:31] assign _io_resp_x_T_5 = _GEN_0; // @[Parameters.scala:137:31] wire [48:0] _io_resp_eff_T_35; // @[Parameters.scala:137:31] assign _io_resp_eff_T_35 = _GEN_0; // @[Parameters.scala:137:31] wire [49:0] _legal_address_T_11 = {1'h0, _legal_address_T_10}; // @[Parameters.scala:137:{31,41}] wire [49:0] _legal_address_T_12 = _legal_address_T_11 & 50'h3FFFFFFFFF000; // @[Parameters.scala:137:{41,46}] wire [49:0] _legal_address_T_13 = _legal_address_T_12; // @[Parameters.scala:137:46] wire _legal_address_T_14 = _legal_address_T_13 == 50'h0; // @[Parameters.scala:137:{46,59}] wire _legal_address_WIRE_2 = _legal_address_T_14; // @[Parameters.scala:612:40] wire [48:0] _GEN_1 = {io_paddr_0[48:17], io_paddr_0[16:0] ^ 17'h10000}; // @[PMA.scala:18:7] wire [48:0] _legal_address_T_15; // @[Parameters.scala:137:31] assign _legal_address_T_15 = _GEN_1; // @[Parameters.scala:137:31] wire [48:0] _io_resp_cacheable_T_5; // @[Parameters.scala:137:31] assign _io_resp_cacheable_T_5 = _GEN_1; // @[Parameters.scala:137:31] wire [48:0] _io_resp_w_T_41; // @[Parameters.scala:137:31] assign _io_resp_w_T_41 = _GEN_1; // @[Parameters.scala:137:31] wire [48:0] _io_resp_pp_T_41; // @[Parameters.scala:137:31] assign _io_resp_pp_T_41 = _GEN_1; // @[Parameters.scala:137:31] wire [48:0] _io_resp_al_T_41; // @[Parameters.scala:137:31] assign _io_resp_al_T_41 = _GEN_1; // @[Parameters.scala:137:31] wire [48:0] _io_resp_aa_T_41; // @[Parameters.scala:137:31] assign _io_resp_aa_T_41 = _GEN_1; // @[Parameters.scala:137:31] wire [48:0] _io_resp_x_T_10; // @[Parameters.scala:137:31] assign _io_resp_x_T_10 = _GEN_1; // @[Parameters.scala:137:31] wire [48:0] _io_resp_eff_T_40; // @[Parameters.scala:137:31] assign _io_resp_eff_T_40 = _GEN_1; // @[Parameters.scala:137:31] wire [49:0] _legal_address_T_16 = {1'h0, _legal_address_T_15}; // @[Parameters.scala:137:{31,41}] wire [49:0] _legal_address_T_17 = _legal_address_T_16 & 50'h3FFFFFFFF0000; // @[Parameters.scala:137:{41,46}] wire [49:0] _legal_address_T_18 = _legal_address_T_17; // @[Parameters.scala:137:46] wire _legal_address_T_19 = _legal_address_T_18 == 50'h0; // @[Parameters.scala:137:{46,59}] wire _legal_address_WIRE_3 = _legal_address_T_19; // @[Parameters.scala:612:40] wire [48:0] _GEN_2 = {io_paddr_0[48:21], io_paddr_0[20:0] ^ 21'h100000}; // @[PMA.scala:18:7] wire [48:0] _legal_address_T_20; // @[Parameters.scala:137:31] assign _legal_address_T_20 = _GEN_2; // @[Parameters.scala:137:31] wire [48:0] _io_resp_w_T_5; // @[Parameters.scala:137:31] assign _io_resp_w_T_5 = _GEN_2; // @[Parameters.scala:137:31] wire [48:0] _io_resp_pp_T_5; // @[Parameters.scala:137:31] assign _io_resp_pp_T_5 = _GEN_2; // @[Parameters.scala:137:31] wire [48:0] _io_resp_al_T_5; // @[Parameters.scala:137:31] assign _io_resp_al_T_5 = _GEN_2; // @[Parameters.scala:137:31] wire [48:0] _io_resp_aa_T_5; // @[Parameters.scala:137:31] assign _io_resp_aa_T_5 = _GEN_2; // @[Parameters.scala:137:31] wire [48:0] _io_resp_x_T_34; // @[Parameters.scala:137:31] assign _io_resp_x_T_34 = _GEN_2; // @[Parameters.scala:137:31] wire [48:0] _io_resp_eff_T_5; // @[Parameters.scala:137:31] assign _io_resp_eff_T_5 = _GEN_2; // @[Parameters.scala:137:31] wire [49:0] _legal_address_T_21 = {1'h0, _legal_address_T_20}; // @[Parameters.scala:137:{31,41}] wire [49:0] _legal_address_T_22 = _legal_address_T_21 & 50'h3FFFFFFFFF000; // @[Parameters.scala:137:{41,46}] wire [49:0] _legal_address_T_23 = _legal_address_T_22; // @[Parameters.scala:137:46] wire _legal_address_T_24 = _legal_address_T_23 == 50'h0; // @[Parameters.scala:137:{46,59}] wire _legal_address_WIRE_4 = _legal_address_T_24; // @[Parameters.scala:612:40] wire [48:0] _legal_address_T_25 = {io_paddr_0[48:21], io_paddr_0[20:0] ^ 21'h110000}; // @[PMA.scala:18:7] wire [49:0] _legal_address_T_26 = {1'h0, _legal_address_T_25}; // @[Parameters.scala:137:{31,41}] wire [49:0] _legal_address_T_27 = _legal_address_T_26 & 50'h3FFFFFFFFF000; // @[Parameters.scala:137:{41,46}] wire [49:0] _legal_address_T_28 = _legal_address_T_27; // @[Parameters.scala:137:46] wire _legal_address_T_29 = _legal_address_T_28 == 50'h0; // @[Parameters.scala:137:{46,59}] wire _legal_address_WIRE_5 = _legal_address_T_29; // @[Parameters.scala:612:40] wire [48:0] _GEN_3 = {io_paddr_0[48:26], io_paddr_0[25:0] ^ 26'h2000000}; // @[PMA.scala:18:7] wire [48:0] _legal_address_T_30; // @[Parameters.scala:137:31] assign _legal_address_T_30 = _GEN_3; // @[Parameters.scala:137:31] wire [48:0] _io_resp_x_T_39; // @[Parameters.scala:137:31] assign _io_resp_x_T_39 = _GEN_3; // @[Parameters.scala:137:31] wire [48:0] _io_resp_eff_T_10; // @[Parameters.scala:137:31] assign _io_resp_eff_T_10 = _GEN_3; // @[Parameters.scala:137:31] wire [49:0] _legal_address_T_31 = {1'h0, _legal_address_T_30}; // @[Parameters.scala:137:{31,41}] wire [49:0] _legal_address_T_32 = _legal_address_T_31 & 50'h3FFFFFFFF0000; // @[Parameters.scala:137:{41,46}] wire [49:0] _legal_address_T_33 = _legal_address_T_32; // @[Parameters.scala:137:46] wire _legal_address_T_34 = _legal_address_T_33 == 50'h0; // @[Parameters.scala:137:{46,59}] wire _legal_address_WIRE_6 = _legal_address_T_34; // @[Parameters.scala:612:40] wire [48:0] _GEN_4 = {io_paddr_0[48:26], io_paddr_0[25:0] ^ 26'h2010000}; // @[PMA.scala:18:7] wire [48:0] _legal_address_T_35; // @[Parameters.scala:137:31] assign _legal_address_T_35 = _GEN_4; // @[Parameters.scala:137:31] wire [48:0] _io_resp_w_T_10; // @[Parameters.scala:137:31] assign _io_resp_w_T_10 = _GEN_4; // @[Parameters.scala:137:31] wire [48:0] _io_resp_pp_T_10; // @[Parameters.scala:137:31] assign _io_resp_pp_T_10 = _GEN_4; // @[Parameters.scala:137:31] wire [48:0] _io_resp_al_T_10; // @[Parameters.scala:137:31] assign _io_resp_al_T_10 = _GEN_4; // @[Parameters.scala:137:31] wire [48:0] _io_resp_aa_T_10; // @[Parameters.scala:137:31] assign _io_resp_aa_T_10 = _GEN_4; // @[Parameters.scala:137:31] wire [48:0] _io_resp_x_T_44; // @[Parameters.scala:137:31] assign _io_resp_x_T_44 = _GEN_4; // @[Parameters.scala:137:31] wire [48:0] _io_resp_eff_T_15; // @[Parameters.scala:137:31] assign _io_resp_eff_T_15 = _GEN_4; // @[Parameters.scala:137:31] wire [49:0] _legal_address_T_36 = {1'h0, _legal_address_T_35}; // @[Parameters.scala:137:{31,41}] wire [49:0] _legal_address_T_37 = _legal_address_T_36 & 50'h3FFFFFFFFF000; // @[Parameters.scala:137:{41,46}] wire [49:0] _legal_address_T_38 = _legal_address_T_37; // @[Parameters.scala:137:46] wire _legal_address_T_39 = _legal_address_T_38 == 50'h0; // @[Parameters.scala:137:{46,59}] wire _legal_address_WIRE_7 = _legal_address_T_39; // @[Parameters.scala:612:40] wire [48:0] _GEN_5 = {io_paddr_0[48:28], io_paddr_0[27:0] ^ 28'h8000000}; // @[PMA.scala:18:7] wire [48:0] _legal_address_T_40; // @[Parameters.scala:137:31] assign _legal_address_T_40 = _GEN_5; // @[Parameters.scala:137:31] wire [48:0] _io_resp_cacheable_T_17; // @[Parameters.scala:137:31] assign _io_resp_cacheable_T_17 = _GEN_5; // @[Parameters.scala:137:31] wire [48:0] _io_resp_w_T_15; // @[Parameters.scala:137:31] assign _io_resp_w_T_15 = _GEN_5; // @[Parameters.scala:137:31] wire [48:0] _io_resp_w_T_20; // @[Parameters.scala:137:31] assign _io_resp_w_T_20 = _GEN_5; // @[Parameters.scala:137:31] wire [48:0] _io_resp_pp_T_15; // @[Parameters.scala:137:31] assign _io_resp_pp_T_15 = _GEN_5; // @[Parameters.scala:137:31] wire [48:0] _io_resp_pp_T_20; // @[Parameters.scala:137:31] assign _io_resp_pp_T_20 = _GEN_5; // @[Parameters.scala:137:31] wire [48:0] _io_resp_al_T_15; // @[Parameters.scala:137:31] assign _io_resp_al_T_15 = _GEN_5; // @[Parameters.scala:137:31] wire [48:0] _io_resp_al_T_20; // @[Parameters.scala:137:31] assign _io_resp_al_T_20 = _GEN_5; // @[Parameters.scala:137:31] wire [48:0] _io_resp_aa_T_15; // @[Parameters.scala:137:31] assign _io_resp_aa_T_15 = _GEN_5; // @[Parameters.scala:137:31] wire [48:0] _io_resp_aa_T_20; // @[Parameters.scala:137:31] assign _io_resp_aa_T_20 = _GEN_5; // @[Parameters.scala:137:31] wire [48:0] _io_resp_x_T_15; // @[Parameters.scala:137:31] assign _io_resp_x_T_15 = _GEN_5; // @[Parameters.scala:137:31] wire [48:0] _io_resp_eff_T_45; // @[Parameters.scala:137:31] assign _io_resp_eff_T_45 = _GEN_5; // @[Parameters.scala:137:31] wire [49:0] _legal_address_T_41 = {1'h0, _legal_address_T_40}; // @[Parameters.scala:137:{31,41}] wire [49:0] _legal_address_T_42 = _legal_address_T_41 & 50'h3FFFFFFFF0000; // @[Parameters.scala:137:{41,46}] wire [49:0] _legal_address_T_43 = _legal_address_T_42; // @[Parameters.scala:137:46] wire _legal_address_T_44 = _legal_address_T_43 == 50'h0; // @[Parameters.scala:137:{46,59}] wire _legal_address_WIRE_8 = _legal_address_T_44; // @[Parameters.scala:612:40] wire [48:0] _GEN_6 = {io_paddr_0[48:28], io_paddr_0[27:0] ^ 28'hC000000}; // @[PMA.scala:18:7] wire [48:0] _legal_address_T_45; // @[Parameters.scala:137:31] assign _legal_address_T_45 = _GEN_6; // @[Parameters.scala:137:31] wire [48:0] _io_resp_cacheable_T_10; // @[Parameters.scala:137:31] assign _io_resp_cacheable_T_10 = _GEN_6; // @[Parameters.scala:137:31] wire [48:0] _io_resp_x_T_49; // @[Parameters.scala:137:31] assign _io_resp_x_T_49 = _GEN_6; // @[Parameters.scala:137:31] wire [48:0] _io_resp_eff_T_20; // @[Parameters.scala:137:31] assign _io_resp_eff_T_20 = _GEN_6; // @[Parameters.scala:137:31] wire [49:0] _legal_address_T_46 = {1'h0, _legal_address_T_45}; // @[Parameters.scala:137:{31,41}] wire [49:0] _legal_address_T_47 = _legal_address_T_46 & 50'h3FFFFFC000000; // @[Parameters.scala:137:{41,46}] wire [49:0] _legal_address_T_48 = _legal_address_T_47; // @[Parameters.scala:137:46] wire _legal_address_T_49 = _legal_address_T_48 == 50'h0; // @[Parameters.scala:137:{46,59}] wire _legal_address_WIRE_9 = _legal_address_T_49; // @[Parameters.scala:612:40] wire [48:0] _legal_address_T_50 = {io_paddr_0[48:29], io_paddr_0[28:0] ^ 29'h10020000}; // @[PMA.scala:18:7] wire [49:0] _legal_address_T_51 = {1'h0, _legal_address_T_50}; // @[Parameters.scala:137:{31,41}] wire [49:0] _legal_address_T_52 = _legal_address_T_51 & 50'h3FFFFFFFFF000; // @[Parameters.scala:137:{41,46}] wire [49:0] _legal_address_T_53 = _legal_address_T_52; // @[Parameters.scala:137:46] wire _legal_address_T_54 = _legal_address_T_53 == 50'h0; // @[Parameters.scala:137:{46,59}] wire _legal_address_WIRE_10 = _legal_address_T_54; // @[Parameters.scala:612:40] wire [48:0] _GEN_7 = {io_paddr_0[48:32], io_paddr_0[31:0] ^ 32'h80000000}; // @[PMA.scala:18:7] wire [48:0] _legal_address_T_55; // @[Parameters.scala:137:31] assign _legal_address_T_55 = _GEN_7; // @[Parameters.scala:137:31] wire [48:0] _io_resp_cacheable_T_22; // @[Parameters.scala:137:31] assign _io_resp_cacheable_T_22 = _GEN_7; // @[Parameters.scala:137:31] wire [48:0] _io_resp_w_T_30; // @[Parameters.scala:137:31] assign _io_resp_w_T_30 = _GEN_7; // @[Parameters.scala:137:31] wire [48:0] _io_resp_pp_T_30; // @[Parameters.scala:137:31] assign _io_resp_pp_T_30 = _GEN_7; // @[Parameters.scala:137:31] wire [48:0] _io_resp_al_T_30; // @[Parameters.scala:137:31] assign _io_resp_al_T_30 = _GEN_7; // @[Parameters.scala:137:31] wire [48:0] _io_resp_aa_T_30; // @[Parameters.scala:137:31] assign _io_resp_aa_T_30 = _GEN_7; // @[Parameters.scala:137:31] wire [48:0] _io_resp_x_T_20; // @[Parameters.scala:137:31] assign _io_resp_x_T_20 = _GEN_7; // @[Parameters.scala:137:31] wire [48:0] _io_resp_eff_T_50; // @[Parameters.scala:137:31] assign _io_resp_eff_T_50 = _GEN_7; // @[Parameters.scala:137:31] wire [49:0] _legal_address_T_56 = {1'h0, _legal_address_T_55}; // @[Parameters.scala:137:{31,41}] wire [49:0] _legal_address_T_57 = _legal_address_T_56 & 50'h3FFFFF0000000; // @[Parameters.scala:137:{41,46}] wire [49:0] _legal_address_T_58 = _legal_address_T_57; // @[Parameters.scala:137:46] wire _legal_address_T_59 = _legal_address_T_58 == 50'h0; // @[Parameters.scala:137:{46,59}] wire _legal_address_WIRE_11 = _legal_address_T_59; // @[Parameters.scala:612:40] wire _legal_address_T_60 = _legal_address_WIRE_0 \| _legal_address_WIRE_1; // @[Parameters.scala:612:40] wire _legal_address_T_61 = _legal_address_T_60 \| _legal_address_WIRE_2; // @[Parameters.scala:612:40] wire _legal_address_T_62 = _legal_address_T_61 \| _legal_address_WIRE_3; // @[Parameters.scala:612:40] wire _legal_address_T_63 = _legal_address_T_62 \| _legal_address_WIRE_4; // @[Parameters.scala:612:40] wire _legal_address_T_64 = _legal_address_T_63 \| _legal_address_WIRE_5; // @[Parameters.scala:612:40] wire _legal_address_T_65 = _legal_address_T_64 \| _legal_address_WIRE_6; // @[Parameters.scala:612:40] wire _legal_address_T_66 = _legal_address_T_65 \| _legal_address_WIRE_7; // @[Parameters.scala:612:40] wire _legal_address_T_67 = _legal_address_T_66 \| _legal_address_WIRE_8; // @[Parameters.scala:612:40] wire _legal_address_T_68 = _legal_address_T_67 \| _legal_address_WIRE_9; // @[Parameters.scala:612:40] wire _legal_address_T_69 = _legal_address_T_68 \| _legal_address_WIRE_10; // @[Parameters.scala:612:40] wire legal_address = _legal_address_T_69 \| _legal_address_WIRE_11; // @[Parameters.scala:612:40] assign _io_resp_r_T_5 = legal_address; // @[PMA.scala:36:58, :39:19] wire [49:0] _io_resp_cacheable_T_1 = {1'h0, _io_resp_cacheable_T}; // @[Parameters.scala:137:{31,41}] wire [49:0] _io_resp_cacheable_T_2 = _io_resp_cacheable_T_1 & 50'h8C000000; // @[Parameters.scala:137:{41,46}] wire [49:0] _io_resp_cacheable_T_3 = _io_resp_cacheable_T_2; // @[Parameters.scala:137:46] wire _io_resp_cacheable_T_4 = _io_resp_cacheable_T_3 == 50'h0; // @[Parameters.scala:137:{46,59}] wire [49:0] _io_resp_cacheable_T_6 = {1'h0, _io_resp_cacheable_T_5}; // @[Parameters.scala:137:{31,41}] wire [49:0] _io_resp_cacheable_T_7 = _io_resp_cacheable_T_6 & 50'h8C011000; // @[Parameters.scala:137:{41,46}] wire [49:0] _io_resp_cacheable_T_8 = _io_resp_cacheable_T_7; // @[Parameters.scala:137:46] wire _io_resp_cacheable_T_9 = _io_resp_cacheable_T_8 == 50'h0; // @[Parameters.scala:137:{46,59}] wire [49:0] _io_resp_cacheable_T_11 = {1'h0, _io_resp_cacheable_T_10}; // @[Parameters.scala:137:{31,41}] wire [49:0] _io_resp_cacheable_T_12 = _io_resp_cacheable_T_11 & 50'h8C000000; // @[Parameters.scala:137:{41,46}] wire [49:0] _io_resp_cacheable_T_13 = _io_resp_cacheable_T_12; // @[Parameters.scala:137:46] wire _io_resp_cacheable_T_14 = _io_resp_cacheable_T_13 == 50'h0; // @[Parameters.scala:137:{46,59}] wire _io_resp_cacheable_T_15 = _io_resp_cacheable_T_4 \| _io_resp_cacheable_T_9; // @[Parameters.scala:629:89] wire _io_resp_cacheable_T_16 = _io_resp_cacheable_T_15 \| _io_resp_cacheable_T_14; // @[Parameters.scala:629:89] wire [49:0] _io_resp_cacheable_T_18 = {1'h0, _io_resp_cacheable_T_17}; // @[Parameters.scala:137:{31,41}] wire [49:0] _io_resp_cacheable_T_19 = _io_resp_cacheable_T_18 & 50'h8C010000; // @[Parameters.scala:137:{41,46}] wire [49:0] _io_resp_cacheable_T_20 = _io_resp_cacheable_T_19; // @[Parameters.scala:137:46] wire _io_resp_cacheable_T_21 = _io_resp_cacheable_T_20 == 50'h0; // @[Parameters.scala:137:{46,59}] wire [49:0] _io_resp_cacheable_T_23 = {1'h0, _io_resp_cacheable_T_22}; // @[Parameters.scala:137:{31,41}] wire [49:0] _io_resp_cacheable_T_24 = _io_resp_cacheable_T_23 & 50'h80000000; // @[Parameters.scala:137:{41,46}] wire [49:0] _io_resp_cacheable_T_25 = _io_resp_cacheable_T_24; // @[Parameters.scala:137:46] wire _io_resp_cacheable_T_26 = _io_resp_cacheable_T_25 == 50'h0; // @[Parameters.scala:137:{46,59}] wire _io_resp_cacheable_T_27 = _io_resp_cacheable_T_21 \| _io_resp_cacheable_T_26; // @[Parameters.scala:629:89] wire _io_resp_cacheable_T_29 = _io_resp_cacheable_T_27; // @[Mux.scala:30:73] wire _io_resp_cacheable_T_30 = _io_resp_cacheable_T_29; // @[Mux.scala:30:73] wire _io_resp_cacheable_WIRE = _io_resp_cacheable_T_30; // @[Mux.scala:30:73] assign _io_resp_cacheable_T_31 = legal_address & _io_resp_cacheable_WIRE; // @[Mux.scala:30:73] assign io_resp_cacheable_0 = _io_resp_cacheable_T_31; // @[PMA.scala:18:7, :39:19] wire [49:0] _io_resp_r_T_1 = {1'h0, _io_resp_r_T}; // @[Parameters.scala:137:{31,41}] assign io_resp_r_0 = _io_resp_r_T_5; // @[PMA.scala:18:7, :39:19] wire [49:0] _io_resp_w_T_1 = {1'h0, _io_resp_w_T}; // @[Parameters.scala:137:{31,41}] wire [49:0] _io_resp_w_T_2 = _io_resp_w_T_1 & 50'h98110000; // @[Parameters.scala:137:{41,46}] wire [49:0] _io_resp_w_T_3 = _io_resp_w_T_2; // @[Parameters.scala:137:46] wire _io_resp_w_T_4 = _io_resp_w_T_3 == 50'h0; // @[Parameters.scala:137:{46,59}] wire [49:0] _io_resp_w_T_6 = {1'h0, _io_resp_w_T_5}; // @[Parameters.scala:137:{31,41}] wire [49:0] _io_resp_w_T_7 = _io_resp_w_T_6 & 50'h9A101000; // @[Parameters.scala:137:{41,46}] wire [49:0] _io_resp_w_T_8 = _io_resp_w_T_7; // @[Parameters.scala:137:46] wire _io_resp_w_T_9 = _io_resp_w_T_8 == 50'h0; // @[Parameters.scala:137:{46,59}] wire [49:0] _io_resp_w_T_11 = {1'h0, _io_resp_w_T_10}; // @[Parameters.scala:137:{31,41}] wire [49:0] _io_resp_w_T_12 = _io_resp_w_T_11 & 50'h9A111000; // @[Parameters.scala:137:{41,46}] wire [49:0] _io_resp_w_T_13 = _io_resp_w_T_12; // @[Parameters.scala:137:46] wire _io_resp_w_T_14 = _io_resp_w_T_13 == 50'h0; // @[Parameters.scala:137:{46,59}] wire [49:0] _io_resp_w_T_16 = {1'h0, _io_resp_w_T_15}; // @[Parameters.scala:137:{31,41}] wire [49:0] _io_resp_w_T_17 = _io_resp_w_T_16 & 50'h98000000; // @[Parameters.scala:137:{41,46}] wire [49:0] _io_resp_w_T_18 = _io_resp_w_T_17; // @[Parameters.scala:137:46] wire _io_resp_w_T_19 = _io_resp_w_T_18 == 50'h0; // @[Parameters.scala:137:{46,59}] wire [49:0] _io_resp_w_T_21 = {1'h0, _io_resp_w_T_20}; // @[Parameters.scala:137:{31,41}] wire [49:0] _io_resp_w_T_22 = _io_resp_w_T_21 & 50'h9A110000; // @[Parameters.scala:137:{41,46}] wire [49:0] _io_resp_w_T_23 = _io_resp_w_T_22; // @[Parameters.scala:137:46] wire _io_resp_w_T_24 = _io_resp_w_T_23 == 50'h0; // @[Parameters.scala:137:{46,59}] wire [48:0] _GEN_8 = {io_paddr_0[48:29], io_paddr_0[28:0] ^ 29'h10000000}; // @[PMA.scala:18:7] wire [48:0] _io_resp_w_T_25; // @[Parameters.scala:137:31] assign _io_resp_w_T_25 = _GEN_8; // @[Parameters.scala:137:31] wire [48:0] _io_resp_pp_T_25; // @[Parameters.scala:137:31] assign _io_resp_pp_T_25 = _GEN_8; // @[Parameters.scala:137:31] wire [48:0] _io_resp_al_T_25; // @[Parameters.scala:137:31] assign _io_resp_al_T_25 = _GEN_8; // @[Parameters.scala:137:31] wire [48:0] _io_resp_aa_T_25; // @[Parameters.scala:137:31] assign _io_resp_aa_T_25 = _GEN_8; // @[Parameters.scala:137:31] wire [48:0] _io_resp_x_T_54; // @[Parameters.scala:137:31] assign _io_resp_x_T_54 = _GEN_8; // @[Parameters.scala:137:31] wire [48:0] _io_resp_eff_T_25; // @[Parameters.scala:137:31] assign _io_resp_eff_T_25 = _GEN_8; // @[Parameters.scala:137:31] wire [49:0] _io_resp_w_T_26 = {1'h0, _io_resp_w_T_25}; // @[Parameters.scala:137:{31,41}] wire [49:0] _io_resp_w_T_27 = _io_resp_w_T_26 & 50'h9A111000; // @[Parameters.scala:137:{41,46}] wire [49:0] _io_resp_w_T_28 = _io_resp_w_T_27; // @[Parameters.scala:137:46] wire _io_resp_w_T_29 = _io_resp_w_T_28 == 50'h0; // @[Parameters.scala:137:{46,59}] wire [49:0] _io_resp_w_T_31 = {1'h0, _io_resp_w_T_30}; // @[Parameters.scala:137:{31,41}] wire [49:0] _io_resp_w_T_32 = _io_resp_w_T_31 & 50'h90000000; // @[Parameters.scala:137:{41,46}] wire [49:0] _io_resp_w_T_33 = _io_resp_w_T_32; // @[Parameters.scala:137:46] wire _io_resp_w_T_34 = _io_resp_w_T_33 == 50'h0; // @[Parameters.scala:137:{46,59}] wire _io_resp_w_T_35 = _io_resp_w_T_4 \| _io_resp_w_T_9; // @[Parameters.scala:629:89] wire _io_resp_w_T_36 = _io_resp_w_T_35 \| _io_resp_w_T_14; // @[Parameters.scala:629:89] wire _io_resp_w_T_37 = _io_resp_w_T_36 \| _io_resp_w_T_19; // @[Parameters.scala:629:89] wire _io_resp_w_T_38 = _io_resp_w_T_37 \| _io_resp_w_T_24; // @[Parameters.scala:629:89] wire _io_resp_w_T_39 = _io_resp_w_T_38 \| _io_resp_w_T_29; // @[Parameters.scala:629:89] wire _io_resp_w_T_40 = _io_resp_w_T_39 \| _io_resp_w_T_34; // @[Parameters.scala:629:89] wire _io_resp_w_T_46 = _io_resp_w_T_40; // @[Mux.scala:30:73] wire [49:0] _io_resp_w_T_42 = {1'h0, _io_resp_w_T_41}; // @[Parameters.scala:137:{31,41}] wire [49:0] _io_resp_w_T_43 = _io_resp_w_T_42 & 50'h9A110000; // @[Parameters.scala:137:{41,46}] wire [49:0] _io_resp_w_T_44 = _io_resp_w_T_43; // @[Parameters.scala:137:46] wire _io_resp_w_T_45 = _io_resp_w_T_44 == 50'h0; // @[Parameters.scala:137:{46,59}] wire _io_resp_w_T_48 = _io_resp_w_T_46; // @[Mux.scala:30:73] wire _io_resp_w_WIRE = _io_resp_w_T_48; // @[Mux.scala:30:73] assign _io_resp_w_T_49 = legal_address & _io_resp_w_WIRE; // @[Mux.scala:30:73] assign io_resp_w_0 = _io_resp_w_T_49; // @[PMA.scala:18:7, :39:19] wire [49:0] _io_resp_pp_T_1 = {1'h0, _io_resp_pp_T}; // @[Parameters.scala:137:{31,41}] wire [49:0] _io_resp_pp_T_2 = _io_resp_pp_T_1 & 50'h98110000; // @[Parameters.scala:137:{41,46}] wire [49:0] _io_resp_pp_T_3 = _io_resp_pp_T_2; // @[Parameters.scala:137:46] wire _io_resp_pp_T_4 = _io_resp_pp_T_3 == 50'h0; // @[Parameters.scala:137:{46,59}] wire [49:0] _io_resp_pp_T_6 = {1'h0, _io_resp_pp_T_5}; // @[Parameters.scala:137:{31,41}] wire [49:0] _io_resp_pp_T_7 = _io_resp_pp_T_6 & 50'h9A101000; // @[Parameters.scala:137:{41,46}] wire [49:0] _io_resp_pp_T_8 = _io_resp_pp_T_7; // @[Parameters.scala:137:46] wire _io_resp_pp_T_9 = _io_resp_pp_T_8 == 50'h0; // @[Parameters.scala:137:{46,59}] wire [49:0] _io_resp_pp_T_11 = {1'h0, _io_resp_pp_T_10}; // @[Parameters.scala:137:{31,41}] wire [49:0] _io_resp_pp_T_12 = _io_resp_pp_T_11 & 50'h9A111000; // @[Parameters.scala:137:{41,46}] wire [49:0] _io_resp_pp_T_13 = _io_resp_pp_T_12; // @[Parameters.scala:137:46] wire _io_resp_pp_T_14 = _io_resp_pp_T_13 == 50'h0; // @[Parameters.scala:137:{46,59}] wire [49:0] _io_resp_pp_T_16 = {1'h0, _io_resp_pp_T_15}; // @[Parameters.scala:137:{31,41}] wire [49:0] _io_resp_pp_T_17 = _io_resp_pp_T_16 & 50'h98000000; // @[Parameters.scala:137:{41,46}] wire [49:0] _io_resp_pp_T_18 = _io_resp_pp_T_17; // @[Parameters.scala:137:46] wire _io_resp_pp_T_19 = _io_resp_pp_T_18 == 50'h0; // @[Parameters.scala:137:{46,59}] wire [49:0] _io_resp_pp_T_21 = {1'h0, _io_resp_pp_T_20}; // @[Parameters.scala:137:{31,41}] wire [49:0] _io_resp_pp_T_22 = _io_resp_pp_T_21 & 50'h9A110000; // @[Parameters.scala:137:{41,46}] wire [49:0] _io_resp_pp_T_23 = _io_resp_pp_T_22; // @[Parameters.scala:137:46] wire _io_resp_pp_T_24 = _io_resp_pp_T_23 == 50'h0; // @[Parameters.scala:137:{46,59}] wire [49:0] _io_resp_pp_T_26 = {1'h0, _io_resp_pp_T_25}; // @[Parameters.scala:137:{31,41}] wire [49:0] _io_resp_pp_T_27 = _io_resp_pp_T_26 & 50'h9A111000; // @[Parameters.scala:137:{41,46}] wire [49:0] _io_resp_pp_T_28 = _io_resp_pp_T_27; // @[Parameters.scala:137:46] wire _io_resp_pp_T_29 = _io_resp_pp_T_28 == 50'h0; // @[Parameters.scala:137:{46,59}] wire [49:0] _io_resp_pp_T_31 = {1'h0, _io_resp_pp_T_30}; // @[Parameters.scala:137:{31,41}] wire [49:0] _io_resp_pp_T_32 = _io_resp_pp_T_31 & 50'h90000000; // @[Parameters.scala:137:{41,46}] wire [49:0] _io_resp_pp_T_33 = _io_resp_pp_T_32; // @[Parameters.scala:137:46] wire _io_resp_pp_T_34 = _io_resp_pp_T_33 == 50'h0; // @[Parameters.scala:137:{46,59}] wire _io_resp_pp_T_35 = _io_resp_pp_T_4 \| _io_resp_pp_T_9; // @[Parameters.scala:629:89] wire _io_resp_pp_T_36 = _io_resp_pp_T_35 \| _io_resp_pp_T_14; // @[Parameters.scala:629:89] wire _io_resp_pp_T_37 = _io_resp_pp_T_36 \| _io_resp_pp_T_19; // @[Parameters.scala:629:89] wire _io_resp_pp_T_38 = _io_resp_pp_T_37 \| _io_resp_pp_T_24; // @[Parameters.scala:629:89] wire _io_resp_pp_T_39 = _io_resp_pp_T_38 \| _io_resp_pp_T_29; // @[Parameters.scala:629:89] wire _io_resp_pp_T_40 = _io_resp_pp_T_39 \| _io_resp_pp_T_34; // @[Parameters.scala:629:89] wire _io_resp_pp_T_46 = _io_resp_pp_T_40; // @[Mux.scala:30:73] wire [49:0] _io_resp_pp_T_42 = {1'h0, _io_resp_pp_T_41}; // @[Parameters.scala:137:{31,41}] wire [49:0] _io_resp_pp_T_43 = _io_resp_pp_T_42 & 50'h9A110000; // @[Parameters.scala:137:{41,46}] wire [49:0] _io_resp_pp_T_44 = _io_resp_pp_T_43; // @[Parameters.scala:137:46] wire _io_resp_pp_T_45 = _io_resp_pp_T_44 == 50'h0; // @[Parameters.scala:137:{46,59}] wire _io_resp_pp_T_48 = _io_resp_pp_T_46; // @[Mux.scala:30:73] wire _io_resp_pp_WIRE = _io_resp_pp_T_48; // @[Mux.scala:30:73] assign _io_resp_pp_T_49 = legal_address & _io_resp_pp_WIRE; // @[Mux.scala:30:73] assign io_resp_pp_0 = _io_resp_pp_T_49; // @[PMA.scala:18:7, :39:19] wire [49:0] _io_resp_al_T_1 = {1'h0, _io_resp_al_T}; // @[Parameters.scala:137:{31,41}] wire [49:0] _io_resp_al_T_2 = _io_resp_al_T_1 & 50'h98110000; // @[Parameters.scala:137:{41,46}] wire [49:0] _io_resp_al_T_3 = _io_resp_al_T_2; // @[Parameters.scala:137:46] wire _io_resp_al_T_4 = _io_resp_al_T_3 == 50'h0; // @[Parameters.scala:137:{46,59}] wire [49:0] _io_resp_al_T_6 = {1'h0, _io_resp_al_T_5}; // @[Parameters.scala:137:{31,41}] wire [49:0] _io_resp_al_T_7 = _io_resp_al_T_6 & 50'h9A101000; // @[Parameters.scala:137:{41,46}] wire [49:0] _io_resp_al_T_8 = _io_resp_al_T_7; // @[Parameters.scala:137:46] wire _io_resp_al_T_9 = _io_resp_al_T_8 == 50'h0; // @[Parameters.scala:137:{46,59}] wire [49:0] _io_resp_al_T_11 = {1'h0, _io_resp_al_T_10}; // @[Parameters.scala:137:{31,41}] wire [49:0] _io_resp_al_T_12 = _io_resp_al_T_11 & 50'h9A111000; // @[Parameters.scala:137:{41,46}] wire [49:0] _io_resp_al_T_13 = _io_resp_al_T_12; // @[Parameters.scala:137:46] wire _io_resp_al_T_14 = _io_resp_al_T_13 == 50'h0; // @[Parameters.scala:137:{46,59}] wire [49:0] _io_resp_al_T_16 = {1'h0, _io_resp_al_T_15}; // @[Parameters.scala:137:{31,41}] wire [49:0] _io_resp_al_T_17 = _io_resp_al_T_16 & 50'h98000000; // @[Parameters.scala:137:{41,46}] wire [49:0] _io_resp_al_T_18 = _io_resp_al_T_17; // @[Parameters.scala:137:46] wire _io_resp_al_T_19 = _io_resp_al_T_18 == 50'h0; // @[Parameters.scala:137:{46,59}] wire [49:0] _io_resp_al_T_21 = {1'h0, _io_resp_al_T_20}; // @[Parameters.scala:137:{31,41}] wire [49:0] _io_resp_al_T_22 = _io_resp_al_T_21 & 50'h9A110000; // @[Parameters.scala:137:{41,46}] wire [49:0] _io_resp_al_T_23 = _io_resp_al_T_22; // @[Parameters.scala:137:46] wire _io_resp_al_T_24 = _io_resp_al_T_23 == 50'h0; // @[Parameters.scala:137:{46,59}] wire [49:0] _io_resp_al_T_26 = {1'h0, _io_resp_al_T_25}; // @[Parameters.scala:137:{31,41}] wire [49:0] _io_resp_al_T_27 = _io_resp_al_T_26 & 50'h9A111000; // @[Parameters.scala:137:{41,46}] wire [49:0] _io_resp_al_T_28 = _io_resp_al_T_27; // @[Parameters.scala:137:46] wire _io_resp_al_T_29 = _io_resp_al_T_28 == 50'h0; // @[Parameters.scala:137:{46,59}] wire [49:0] _io_resp_al_T_31 = {1'h0, _io_resp_al_T_30}; // @[Parameters.scala:137:{31,41}] wire [49:0] _io_resp_al_T_32 = _io_resp_al_T_31 & 50'h90000000; // @[Parameters.scala:137:{41,46}] wire [49:0] _io_resp_al_T_33 = _io_resp_al_T_32; // @[Parameters.scala:137:46] wire _io_resp_al_T_34 = _io_resp_al_T_33 == 50'h0; // @[Parameters.scala:137:{46,59}] wire _io_resp_al_T_35 = _io_resp_al_T_4 \| _io_resp_al_T_9; // @[Parameters.scala:629:89] wire _io_resp_al_T_36 = _io_resp_al_T_35 \| _io_resp_al_T_14; // @[Parameters.scala:629:89] wire _io_resp_al_T_37 = _io_resp_al_T_36 \| _io_resp_al_T_19; // @[Parameters.scala:629:89] wire _io_resp_al_T_38 = _io_resp_al_T_37 \| _io_resp_al_T_24; // @[Parameters.scala:629:89] wire _io_resp_al_T_39 = _io_resp_al_T_38 \| _io_resp_al_T_29; // @[Parameters.scala:629:89] wire _io_resp_al_T_40 = _io_resp_al_T_39 \| _io_resp_al_T_34; // @[Parameters.scala:629:89] wire _io_resp_al_T_46 = _io_resp_al_T_40; // @[Mux.scala:30:73] wire [49:0] _io_resp_al_T_42 = {1'h0, _io_resp_al_T_41}; // @[Parameters.scala:137:{31,41}] wire [49:0] _io_resp_al_T_43 = _io_resp_al_T_42 & 50'h9A110000; // @[Parameters.scala:137:{41,46}] wire [49:0] _io_resp_al_T_44 = _io_resp_al_T_43; // @[Parameters.scala:137:46] wire _io_resp_al_T_45 = _io_resp_al_T_44 == 50'h0; // @[Parameters.scala:137:{46,59}] wire _io_resp_al_T_48 = _io_resp_al_T_46; // @[Mux.scala:30:73] wire _io_resp_al_WIRE = _io_resp_al_T_48; // @[Mux.scala:30:73] assign _io_resp_al_T_49 = legal_address & _io_resp_al_WIRE; // @[Mux.scala:30:73] assign io_resp_al_0 = _io_resp_al_T_49; // @[PMA.scala:18:7, :39:19] wire [49:0] _io_resp_aa_T_1 = {1'h0, _io_resp_aa_T}; // @[Parameters.scala:137:{31,41}] wire [49:0] _io_resp_aa_T_2 = _io_resp_aa_T_1 & 50'h98110000; // @[Parameters.scala:137:{41,46}] wire [49:0] _io_resp_aa_T_3 = _io_resp_aa_T_2; // @[Parameters.scala:137:46] wire _io_resp_aa_T_4 = _io_resp_aa_T_3 == 50'h0; // @[Parameters.scala:137:{46,59}] wire [49:0] _io_resp_aa_T_6 = {1'h0, _io_resp_aa_T_5}; // @[Parameters.scala:137:{31,41}] wire [49:0] _io_resp_aa_T_7 = _io_resp_aa_T_6 & 50'h9A101000; // @[Parameters.scala:137:{41,46}] wire [49:0] _io_resp_aa_T_8 = _io_resp_aa_T_7; // @[Parameters.scala:137:46] wire _io_resp_aa_T_9 = _io_resp_aa_T_8 == 50'h0; // @[Parameters.scala:137:{46,59}] wire [49:0] _io_resp_aa_T_11 = {1'h0, _io_resp_aa_T_10}; // @[Parameters.scala:137:{31,41}] wire [49:0] _io_resp_aa_T_12 = _io_resp_aa_T_11 & 50'h9A111000; // @[Parameters.scala:137:{41,46}] wire [49:0] _io_resp_aa_T_13 = _io_resp_aa_T_12; // @[Parameters.scala:137:46] wire _io_resp_aa_T_14 = _io_resp_aa_T_13 == 50'h0; // @[Parameters.scala:137:{46,59}] wire [49:0] _io_resp_aa_T_16 = {1'h0, _io_resp_aa_T_15}; // @[Parameters.scala:137:{31,41}] wire [49:0] _io_resp_aa_T_17 = _io_resp_aa_T_16 & 50'h98000000; // @[Parameters.scala:137:{41,46}] wire [49:0] _io_resp_aa_T_18 = _io_resp_aa_T_17; // @[Parameters.scala:137:46] wire _io_resp_aa_T_19 = _io_resp_aa_T_18 == 50'h0; // @[Parameters.scala:137:{46,59}] wire [49:0] _io_resp_aa_T_21 = {1'h0, _io_resp_aa_T_20}; // @[Parameters.scala:137:{31,41}] wire [49:0] _io_resp_aa_T_22 = _io_resp_aa_T_21 & 50'h9A110000; // @[Parameters.scala:137:{41,46}] wire [49:0] _io_resp_aa_T_23 = _io_resp_aa_T_22; // @[Parameters.scala:137:46] wire _io_resp_aa_T_24 = _io_resp_aa_T_23 == 50'h0; // @[Parameters.scala:137:{46,59}] wire [49:0] _io_resp_aa_T_26 = {1'h0, _io_resp_aa_T_25}; // @[Parameters.scala:137:{31,41}] wire [49:0] _io_resp_aa_T_27 = _io_resp_aa_T_26 & 50'h9A111000; // @[Parameters.scala:137:{41,46}] wire [49:0] _io_resp_aa_T_28 = _io_resp_aa_T_27; // @[Parameters.scala:137:46] wire _io_resp_aa_T_29 = _io_resp_aa_T_28 == 50'h0; // @[Parameters.scala:137:{46,59}] wire [49:0] _io_resp_aa_T_31 = {1'h0, _io_resp_aa_T_30}; // @[Parameters.scala:137:{31,41}] wire [49:0] _io_resp_aa_T_32 = _io_resp_aa_T_31 & 50'h90000000; // @[Parameters.scala:137:{41,46}] wire [49:0] _io_resp_aa_T_33 = _io_resp_aa_T_32; // @[Parameters.scala:137:46] wire _io_resp_aa_T_34 = _io_resp_aa_T_33 == 50'h0; // @[Parameters.scala:137:{46,59}] wire _io_resp_aa_T_35 = _io_resp_aa_T_4 \| _io_resp_aa_T_9; // @[Parameters.scala:629:89] wire _io_resp_aa_T_36 = _io_resp_aa_T_35 \| _io_resp_aa_T_14; // @[Parameters.scala:629:89] wire _io_resp_aa_T_37 = _io_resp_aa_T_36 \| _io_resp_aa_T_19; // @[Parameters.scala:629:89] wire _io_resp_aa_T_38 = _io_resp_aa_T_37 \| _io_resp_aa_T_24; // @[Parameters.scala:629:89] wire _io_resp_aa_T_39 = _io_resp_aa_T_38 \| _io_resp_aa_T_29; // @[Parameters.scala:629:89] wire _io_resp_aa_T_40 = _io_resp_aa_T_39 \| _io_resp_aa_T_34; // @[Parameters.scala:629:89] wire _io_resp_aa_T_46 = _io_resp_aa_T_40; // @[Mux.scala:30:73] wire [49:0] _io_resp_aa_T_42 = {1'h0, _io_resp_aa_T_41}; // @[Parameters.scala:137:{31,41}] wire [49:0] _io_resp_aa_T_43 = _io_resp_aa_T_42 & 50'h9A110000; // @[Parameters.scala:137:{41,46}] wire [49:0] _io_resp_aa_T_44 = _io_resp_aa_T_43; // @[Parameters.scala:137:46] wire _io_resp_aa_T_45 = _io_resp_aa_T_44 == 50'h0; // @[Parameters.scala:137:{46,59}] wire _io_resp_aa_T_48 = _io_resp_aa_T_46; // @[Mux.scala:30:73] wire _io_resp_aa_WIRE = _io_resp_aa_T_48; // @[Mux.scala:30:73] assign _io_resp_aa_T_49 = legal_address & _io_resp_aa_WIRE; // @[Mux.scala:30:73] assign io_resp_aa_0 = _io_resp_aa_T_49; // @[PMA.scala:18:7, :39:19] wire [49:0] _io_resp_x_T_1 = {1'h0, _io_resp_x_T}; // @[Parameters.scala:137:{31,41}] wire [49:0] _io_resp_x_T_2 = _io_resp_x_T_1 & 50'h9E113000; // @[Parameters.scala:137:{41,46}] wire [49:0] _io_resp_x_T_3 = _io_resp_x_T_2; // @[Parameters.scala:137:46] wire _io_resp_x_T_4 = _io_resp_x_T_3 == 50'h0; // @[Parameters.scala:137:{46,59}] wire [49:0] _io_resp_x_T_6 = {1'h0, _io_resp_x_T_5}; // @[Parameters.scala:137:{31,41}] wire [49:0] _io_resp_x_T_7 = _io_resp_x_T_6 & 50'h9E113000; // @[Parameters.scala:137:{41,46}] wire [49:0] _io_resp_x_T_8 = _io_resp_x_T_7; // @[Parameters.scala:137:46] wire _io_resp_x_T_9 = _io_resp_x_T_8 == 50'h0; // @[Parameters.scala:137:{46,59}] wire [49:0] _io_resp_x_T_11 = {1'h0, _io_resp_x_T_10}; // @[Parameters.scala:137:{31,41}] wire [49:0] _io_resp_x_T_12 = _io_resp_x_T_11 & 50'h9E110000; // @[Parameters.scala:137:{41,46}] wire [49:0] _io_resp_x_T_13 = _io_resp_x_T_12; // @[Parameters.scala:137:46] wire _io_resp_x_T_14 = _io_resp_x_T_13 == 50'h0; // @[Parameters.scala:137:{46,59}] wire [49:0] _io_resp_x_T_16 = {1'h0, _io_resp_x_T_15}; // @[Parameters.scala:137:{31,41}] wire [49:0] _io_resp_x_T_17 = _io_resp_x_T_16 & 50'h9E110000; // @[Parameters.scala:137:{41,46}] wire [49:0] _io_resp_x_T_18 = _io_resp_x_T_17; // @[Parameters.scala:137:46] wire _io_resp_x_T_19 = _io_resp_x_T_18 == 50'h0; // @[Parameters.scala:137:{46,59}] wire [49:0] _io_resp_x_T_21 = {1'h0, _io_resp_x_T_20}; // @[Parameters.scala:137:{31,41}] wire [49:0] _io_resp_x_T_22 = _io_resp_x_T_21 & 50'h90000000; // @[Parameters.scala:137:{41,46}] wire [49:0] _io_resp_x_T_23 = _io_resp_x_T_22; // @[Parameters.scala:137:46] wire _io_resp_x_T_24 = _io_resp_x_T_23 == 50'h0; // @[Parameters.scala:137:{46,59}] wire _io_resp_x_T_25 = _io_resp_x_T_4 \| _io_resp_x_T_9; // @[Parameters.scala:629:89] wire _io_resp_x_T_26 = _io_resp_x_T_25 \| _io_resp_x_T_14; // @[Parameters.scala:629:89] wire _io_resp_x_T_27 = _io_resp_x_T_26 \| _io_resp_x_T_19; // @[Parameters.scala:629:89] wire _io_resp_x_T_28 = _io_resp_x_T_27 \| _io_resp_x_T_24; // @[Parameters.scala:629:89] wire _io_resp_x_T_64 = _io_resp_x_T_28; // @[Mux.scala:30:73] wire [49:0] _io_resp_x_T_30 = {1'h0, _io_resp_x_T_29}; // @[Parameters.scala:137:{31,41}] wire [49:0] _io_resp_x_T_31 = _io_resp_x_T_30 & 50'h9E113000; // @[Parameters.scala:137:{41,46}] wire [49:0] _io_resp_x_T_32 = _io_resp_x_T_31; // @[Parameters.scala:137:46] wire _io_resp_x_T_33 = _io_resp_x_T_32 == 50'h0; // @[Parameters.scala:137:{46,59}] wire [49:0] _io_resp_x_T_35 = {1'h0, _io_resp_x_T_34}; // @[Parameters.scala:137:{31,41}] wire [49:0] _io_resp_x_T_36 = _io_resp_x_T_35 & 50'h9E103000; // @[Parameters.scala:137:{41,46}] wire [49:0] _io_resp_x_T_37 = _io_resp_x_T_36; // @[Parameters.scala:137:46] wire _io_resp_x_T_38 = _io_resp_x_T_37 == 50'h0; // @[Parameters.scala:137:{46,59}] wire [49:0] _io_resp_x_T_40 = {1'h0, _io_resp_x_T_39}; // @[Parameters.scala:137:{31,41}] wire [49:0] _io_resp_x_T_41 = _io_resp_x_T_40 & 50'h9E110000; // @[Parameters.scala:137:{41,46}] wire [49:0] _io_resp_x_T_42 = _io_resp_x_T_41; // @[Parameters.scala:137:46] wire _io_resp_x_T_43 = _io_resp_x_T_42 == 50'h0; // @[Parameters.scala:137:{46,59}] wire [49:0] _io_resp_x_T_45 = {1'h0, _io_resp_x_T_44}; // @[Parameters.scala:137:{31,41}] wire [49:0] _io_resp_x_T_46 = _io_resp_x_T_45 & 50'h9E113000; // @[Parameters.scala:137:{41,46}] wire [49:0] _io_resp_x_T_47 = _io_resp_x_T_46; // @[Parameters.scala:137:46] wire _io_resp_x_T_48 = _io_resp_x_T_47 == 50'h0; // @[Parameters.scala:137:{46,59}] wire [49:0] _io_resp_x_T_50 = {1'h0, _io_resp_x_T_49}; // @[Parameters.scala:137:{31,41}] wire [49:0] _io_resp_x_T_51 = _io_resp_x_T_50 & 50'h9C000000; // @[Parameters.scala:137:{41,46}] wire [49:0] _io_resp_x_T_52 = _io_resp_x_T_51; // @[Parameters.scala:137:46] wire _io_resp_x_T_53 = _io_resp_x_T_52 == 50'h0; // @[Parameters.scala:137:{46,59}] wire [49:0] _io_resp_x_T_55 = {1'h0, _io_resp_x_T_54}; // @[Parameters.scala:137:{31,41}] wire [49:0] _io_resp_x_T_56 = _io_resp_x_T_55 & 50'h9E113000; // @[Parameters.scala:137:{41,46}] wire [49:0] _io_resp_x_T_57 = _io_resp_x_T_56; // @[Parameters.scala:137:46] wire _io_resp_x_T_58 = _io_resp_x_T_57 == 50'h0; // @[Parameters.scala:137:{46,59}] wire _io_resp_x_T_59 = _io_resp_x_T_33 \| _io_resp_x_T_38; // @[Parameters.scala:629:89] wire _io_resp_x_T_60 = _io_resp_x_T_59 \| _io_resp_x_T_43; // @[Parameters.scala:629:89] wire _io_resp_x_T_61 = _io_resp_x_T_60 \| _io_resp_x_T_48; // @[Parameters.scala:629:89] wire _io_resp_x_T_62 = _io_resp_x_T_61 \| _io_resp_x_T_53; // @[Parameters.scala:629:89] wire _io_resp_x_T_63 = _io_resp_x_T_62 \| _io_resp_x_T_58; // @[Parameters.scala:629:89] wire _io_resp_x_T_66 = _io_resp_x_T_64; // @[Mux.scala:30:73] wire _io_resp_x_WIRE = _io_resp_x_T_66; // @[Mux.scala:30:73] assign _io_resp_x_T_67 = legal_address & _io_resp_x_WIRE; // @[Mux.scala:30:73] assign io_resp_x_0 = _io_resp_x_T_67; // @[PMA.scala:18:7, :39:19] wire [49:0] _io_resp_eff_T_1 = {1'h0, _io_resp_eff_T}; // @[Parameters.scala:137:{31,41}] wire [49:0] _io_resp_eff_T_2 = _io_resp_eff_T_1 & 50'h9E112000; // @[Parameters.scala:137:{41,46}] wire [49:0] _io_resp_eff_T_3 = _io_resp_eff_T_2; // @[Parameters.scala:137:46] wire _io_resp_eff_T_4 = _io_resp_eff_T_3 == 50'h0; // @[Parameters.scala:137:{46,59}] wire [49:0] _io_resp_eff_T_6 = {1'h0, _io_resp_eff_T_5}; // @[Parameters.scala:137:{31,41}] wire [49:0] _io_resp_eff_T_7 = _io_resp_eff_T_6 & 50'h9E103000; // @[Parameters.scala:137:{41,46}] wire [49:0] _io_resp_eff_T_8 = _io_resp_eff_T_7; // @[Parameters.scala:137:46] wire _io_resp_eff_T_9 = _io_resp_eff_T_8 == 50'h0; // @[Parameters.scala:137:{46,59}] wire [49:0] _io_resp_eff_T_11 = {1'h0, _io_resp_eff_T_10}; // @[Parameters.scala:137:{31,41}] wire [49:0] _io_resp_eff_T_12 = _io_resp_eff_T_11 & 50'h9E110000; // @[Parameters.scala:137:{41,46}] wire [49:0] _io_resp_eff_T_13 = _io_resp_eff_T_12; // @[Parameters.scala:137:46] wire _io_resp_eff_T_14 = _io_resp_eff_T_13 == 50'h0; // @[Parameters.scala:137:{46,59}] wire [49:0] _io_resp_eff_T_16 = {1'h0, _io_resp_eff_T_15}; // @[Parameters.scala:137:{31,41}] wire [49:0] _io_resp_eff_T_17 = _io_resp_eff_T_16 & 50'h9E113000; // @[Parameters.scala:137:{41,46}] wire [49:0] _io_resp_eff_T_18 = _io_resp_eff_T_17; // @[Parameters.scala:137:46] wire _io_resp_eff_T_19 = _io_resp_eff_T_18 == 50'h0; // @[Parameters.scala:137:{46,59}] wire [49:0] _io_resp_eff_T_21 = {1'h0, _io_resp_eff_T_20}; // @[Parameters.scala:137:{31,41}] wire [49:0] _io_resp_eff_T_22 = _io_resp_eff_T_21 & 50'h9C000000; // @[Parameters.scala:137:{41,46}] wire [49:0] _io_resp_eff_T_23 = _io_resp_eff_T_22; // @[Parameters.scala:137:46] wire _io_resp_eff_T_24 = _io_resp_eff_T_23 == 50'h0; // @[Parameters.scala:137:{46,59}] wire [49:0] _io_resp_eff_T_26 = {1'h0, _io_resp_eff_T_25}; // @[Parameters.scala:137:{31,41}] wire [49:0] _io_resp_eff_T_27 = _io_resp_eff_T_26 & 50'h9E113000; // @[Parameters.scala:137:{41,46}] wire [49:0] _io_resp_eff_T_28 = _io_resp_eff_T_27; // @[Parameters.scala:137:46] wire _io_resp_eff_T_29 = _io_resp_eff_T_28 == 50'h0; // @[Parameters.scala:137:{46,59}] wire _io_resp_eff_T_30 = _io_resp_eff_T_4 \| _io_resp_eff_T_9; // @[Parameters.scala:629:89] wire _io_resp_eff_T_31 = _io_resp_eff_T_30 \| _io_resp_eff_T_14; // @[Parameters.scala:629:89] wire _io_resp_eff_T_32 = _io_resp_eff_T_31 \| _io_resp_eff_T_19; // @[Parameters.scala:629:89] wire _io_resp_eff_T_33 = _io_resp_eff_T_32 \| _io_resp_eff_T_24; // @[Parameters.scala:629:89] wire _io_resp_eff_T_34 = _io_resp_eff_T_33 \| _io_resp_eff_T_29; // @[Parameters.scala:629:89] wire _io_resp_eff_T_58 = _io_resp_eff_T_34; // @[Mux.scala:30:73] wire [49:0] _io_resp_eff_T_36 = {1'h0, _io_resp_eff_T_35}; // @[Parameters.scala:137:{31,41}] wire [49:0] _io_resp_eff_T_37 = _io_resp_eff_T_36 & 50'h9E113000; // @[Parameters.scala:137:{41,46}] wire [49:0] _io_resp_eff_T_38 = _io_resp_eff_T_37; // @[Parameters.scala:137:46] wire _io_resp_eff_T_39 = _io_resp_eff_T_38 == 50'h0; // @[Parameters.scala:137:{46,59}] wire [49:0] _io_resp_eff_T_41 = {1'h0, _io_resp_eff_T_40}; // @[Parameters.scala:137:{31,41}] wire [49:0] _io_resp_eff_T_42 = _io_resp_eff_T_41 & 50'h9E110000; // @[Parameters.scala:137:{41,46}] wire [49:0] _io_resp_eff_T_43 = _io_resp_eff_T_42; // @[Parameters.scala:137:46] wire _io_resp_eff_T_44 = _io_resp_eff_T_43 == 50'h0; // @[Parameters.scala:137:{46,59}] wire [49:0] _io_resp_eff_T_46 = {1'h0, _io_resp_eff_T_45}; // @[Parameters.scala:137:{31,41}] wire [49:0] _io_resp_eff_T_47 = _io_resp_eff_T_46 & 50'h9E110000; // @[Parameters.scala:137:{41,46}] wire [49:0] _io_resp_eff_T_48 = _io_resp_eff_T_47; // @[Parameters.scala:137:46] wire _io_resp_eff_T_49 = _io_resp_eff_T_48 == 50'h0; // @[Parameters.scala:137:{46,59}] wire [49:0] _io_resp_eff_T_51 = {1'h0, _io_resp_eff_T_50}; // @[Parameters.scala:137:{31,41}] wire [49:0] _io_resp_eff_T_52 = _io_resp_eff_T_51 & 50'h90000000; // @[Parameters.scala:137:{41,46}] wire [49:0] _io_resp_eff_T_53 = _io_resp_eff_T_52; // @[Parameters.scala:137:46] wire _io_resp_eff_T_54 = _io_resp_eff_T_53 == 50'h0; // @[Parameters.scala:137:{46,59}] wire _io_resp_eff_T_55 = _io_resp_eff_T_39 \| _io_resp_eff_T_44; // @[Parameters.scala:629:89] wire _io_resp_eff_T_56 = _io_resp_eff_T_55 \| _io_resp_eff_T_49; // @[Parameters.scala:629:89] wire _io_resp_eff_T_57 = _io_resp_eff_T_56 \| _io_resp_eff_T_54; // @[Parameters.scala:629:89] wire _io_resp_eff_T_60 = _io_resp_eff_T_58; // @[Mux.scala:30:73] wire _io_resp_eff_WIRE = _io_resp_eff_T_60; // @[Mux.scala:30:73] assign _io_resp_eff_T_61 = legal_address & _io_resp_eff_WIRE; // @[Mux.scala:30:73] assign io_resp_eff_0 = _io_resp_eff_T_61; // @[PMA.scala:18:7, :39:19] assign io_resp_cacheable = io_resp_cacheable_0; // @[PMA.scala:18:7] assign io_resp_r = io_resp_r_0; // @[PMA.scala:18:7] assign io_resp_w = io_resp_w_0; // @[PMA.scala:18:7] assign io_resp_pp = io_resp_pp_0; // @[PMA.scala:18:7] assign io_resp_al = io_resp_al_0; // @[PMA.scala:18:7] assign io_resp_aa = io_resp_aa_0; // @[PMA.scala:18:7] assign io_resp_x = io_resp_x_0; // @[PMA.scala:18:7] assign io_resp_eff = io_resp_eff_0; // @[PMA.scala:18:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File ShiftReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ // Similar to the Chisel ShiftRegister but allows the user to suggest a // name to the registers that get instantiated, and // to provide a reset value. object ShiftRegInit { def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T = (0 until n).foldRight(in) { case (i, next) => { val r = RegNext(next, init) name.foreach { na => r.suggestName(s"${na}_${i}") } r } } } /** These wrap behavioral * shift registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * The different types vary in their reset behavior: * AsyncResetShiftReg -- Asynchronously reset register array * A W(width) x D(depth) sized array is constructed from D instantiations of a * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg, * but only used for timing applications / abstract class AbstractPipelineReg(w: Int = 1) extends Module { val io = IO(new Bundle { val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) } ) } object AbstractPipelineReg { def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = { val chain = Module(gen) name.foreach{ chain.suggestName(_) } chain.io.d := in.asUInt chain.io.q.asTypeOf(in) } } class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) { require(depth > 0, "Depth must be greater than 0.") override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}" val chain = List.tabulate(depth) { i => Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}") } chain.last.io.d := io.d chain.last.io.en := true.B (chain.init zip chain.tail).foreach { case (sink, source) => sink.io.d := source.io.q sink.io.en := true.B } io.q := chain.head.io.q } object AsyncResetShiftReg { def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name) def apply [T <: Data](in: T, depth: Int, name: Option[String]): T = apply(in, depth, 0, name) def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T = apply(in, depth, init.litValue.toInt, name) def apply [T <: Data](in: T, depth: Int, init: T): T = apply (in, depth, init.litValue.toInt, None) } File SynchronizerReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util.{RegEnable, Cat} /* These wrap behavioral * shift and next registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * * These are built up of ResetSynchronizerPrimitiveShiftReg, intended to be replaced by the integrator's metastable flops chains or replaced * at this level if they have a multi-bit wide synchronizer primitive. * The different types vary in their reset behavior: * NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin * AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep * 1-bit-wide shift registers. * SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg * * [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference. * * ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross * Clock Domains. */ object SynchronizerResetType extends Enumeration { val NonSync, Inferred, Sync, Async = Value } // Note: this should not be used directly. // Use the companion object to generate this with the correct reset type mixin. private class SynchronizerPrimitiveShiftReg( sync: Int, init: Boolean, resetType: SynchronizerResetType.Value) extends AbstractPipelineReg(1) { val initInt = if (init) 1 else 0 val initPostfix = resetType match { case SynchronizerResetType.NonSync => "" case _ => s"_i${initInt}" } override def desiredName = s"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}" val chain = List.tabulate(sync) { i => val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B) reg.suggestName(s"sync_$i") } chain.last := io.d.asBool (chain.init zip chain.tail).foreach { case (sink, source) => sink := source } io.q := chain.head.asUInt } private object SynchronizerPrimitiveShiftReg { def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = { val gen: () => SynchronizerPrimitiveShiftReg = resetType match { case SynchronizerResetType.NonSync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) case SynchronizerResetType.Async => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset case SynchronizerResetType.Sync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset case SynchronizerResetType.Inferred => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) } AbstractPipelineReg(gen(), in) } } // Note: This module may end up with a non-AsyncReset type reset. // But the Primitives within will always have AsyncReset type. class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asAsyncReset){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async) } } io.q := Cat(output.reverse) } object AsyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } // Note: This module may end up with a non-Bool type reset. // But the Primitives within will always have Bool reset type. @deprecated("SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.", "rocket-chip 1.2") class SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asBool){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync) } } io.q := Cat(output.reverse) } object SyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred) } io.q := Cat(output.reverse) } object ResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}" val output = Seq.tabulate(w) { i => SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync) } io.q := Cat(output.reverse) } object SynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, None) def apply [T <: Data](in: T): T = apply (in, 3, None) } class ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module { override def desiredName = s"ClockCrossingReg_w${w}" val io = IO(new Bundle{ val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) val en = Input(Bool()) }) val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en) io.q := cdc_reg } object ClockCrossingReg { def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = { val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit)) name.foreach{ cdc_reg.suggestName(_) } cdc_reg.io.d := in.asUInt cdc_reg.io.en := en cdc_reg.io.q.asTypeOf(in) } }	module AsyncResetSynchronizerShiftReg_w1_d3_i0_165( // @[SynchronizerReg.scala:80:7] input clock, // @[SynchronizerReg.scala:80:7] input reset, // @[SynchronizerReg.scala:80:7] output io_q // @[ShiftReg.scala:36:14] ); wire _output_T = reset; // @[SynchronizerReg.scala:86:21] wire io_d = 1'h1; // @[SynchronizerReg.scala:80:7, :87:41] wire _output_T_1 = 1'h1; // @[SynchronizerReg.scala:80:7, :87:41] wire output_0; // @[ShiftReg.scala:48:24] wire io_q_0; // @[SynchronizerReg.scala:80:7] assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_289 output_chain ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T), // @[SynchronizerReg.scala:86:21] .io_q (output_0) ); // @[ShiftReg.scala:45:23] assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File InputUnit.scala: package constellation.router import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.{Field, Parameters} import freechips.rocketchip.util._ import constellation.channel._ import constellation.routing.{FlowRoutingBundle} import constellation.noc.{HasNoCParams} class AbstractInputUnitIO( val cParam: BaseChannelParams, val outParams: Seq[ChannelParams], val egressParams: Seq[EgressChannelParams], )(implicit val p: Parameters) extends Bundle with HasRouterOutputParams { val nodeId = cParam.destId val router_req = Decoupled(new RouteComputerReq) val router_resp = Input(new RouteComputerResp(outParams, egressParams)) val vcalloc_req = Decoupled(new VCAllocReq(cParam, outParams, egressParams)) val vcalloc_resp = Input(new VCAllocResp(outParams, egressParams)) val out_credit_available = Input(MixedVec(allOutParams.map { u => Vec(u.nVirtualChannels, Bool()) })) val salloc_req = Vec(cParam.destSpeedup, Decoupled(new SwitchAllocReq(outParams, egressParams))) val out = Vec(cParam.destSpeedup, Valid(new SwitchBundle(outParams, egressParams))) val debug = Output(new Bundle { val va_stall = UInt(log2Ceil(cParam.nVirtualChannels).W) val sa_stall = UInt(log2Ceil(cParam.nVirtualChannels).W) }) val block = Input(Bool()) } abstract class AbstractInputUnit( val cParam: BaseChannelParams, val outParams: Seq[ChannelParams], val egressParams: Seq[EgressChannelParams] )(implicit val p: Parameters) extends Module with HasRouterOutputParams with HasNoCParams { val nodeId = cParam.destId def io: AbstractInputUnitIO } class InputBuffer(cParam: ChannelParams)(implicit p: Parameters) extends Module { val nVirtualChannels = cParam.nVirtualChannels val io = IO(new Bundle { val enq = Flipped(Vec(cParam.srcSpeedup, Valid(new Flit(cParam.payloadBits)))) val deq = Vec(cParam.nVirtualChannels, Decoupled(new BaseFlit(cParam.payloadBits))) }) val useOutputQueues = cParam.useOutputQueues val delims = if (useOutputQueues) { cParam.virtualChannelParams.map(u => if (u.traversable) u.bufferSize else 0).scanLeft(0)(_+_) } else { // If no queuing, have to add an additional slot since head == tail implies empty // TODO this should be fixed, should use all slots available cParam.virtualChannelParams.map(u => if (u.traversable) u.bufferSize + 1 else 0).scanLeft(0)(_+_) } val starts = delims.dropRight(1).zipWithIndex.map { case (s,i) => if (cParam.virtualChannelParams(i).traversable) s else 0 } val ends = delims.tail.zipWithIndex.map { case (s,i) => if (cParam.virtualChannelParams(i).traversable) s else 0 } val fullSize = delims.last // Ugly case. Use multiple queues if ((cParam.srcSpeedup > 1 \|\| cParam.destSpeedup > 1 \|\| fullSize <= 1) \|\| !cParam.unifiedBuffer) { require(useOutputQueues) val qs = cParam.virtualChannelParams.map(v => Module(new Queue(new BaseFlit(cParam.payloadBits), v.bufferSize))) qs.zipWithIndex.foreach { case (q,i) => val sel = io.enq.map(f => f.valid && f.bits.virt_channel_id === i.U) q.io.enq.valid := sel.orR q.io.enq.bits.head := Mux1H(sel, io.enq.map(_.bits.head)) q.io.enq.bits.tail := Mux1H(sel, io.enq.map(_.bits.tail)) q.io.enq.bits.payload := Mux1H(sel, io.enq.map(_.bits.payload)) io.deq(i) <> q.io.deq } } else { val mem = Mem(fullSize, new BaseFlit(cParam.payloadBits)) val heads = RegInit(VecInit(starts.map(_.U(log2Ceil(fullSize).W)))) val tails = RegInit(VecInit(starts.map(_.U(log2Ceil(fullSize).W)))) val empty = (heads zip tails).map(t => t._1 === t._2) val qs = Seq.fill(nVirtualChannels) { Module(new Queue(new BaseFlit(cParam.payloadBits), 1, pipe=true)) } qs.foreach(_.io.enq.valid := false.B) qs.foreach(_.io.enq.bits := DontCare) val vc_sel = UIntToOH(io.enq(0).bits.virt_channel_id) val flit = Wire(new BaseFlit(cParam.payloadBits)) val direct_to_q = (Mux1H(vc_sel, qs.map(_.io.enq.ready)) && Mux1H(vc_sel, empty)) && useOutputQueues.B flit.head := io.enq(0).bits.head flit.tail := io.enq(0).bits.tail flit.payload := io.enq(0).bits.payload when (io.enq(0).valid && !direct_to_q) { val tail = tails(io.enq(0).bits.virt_channel_id) mem.write(tail, flit) tails(io.enq(0).bits.virt_channel_id) := Mux( tail === Mux1H(vc_sel, ends.map(_ - 1).map(_ max 0).map(_.U)), Mux1H(vc_sel, starts.map(_.U)), tail + 1.U) } .elsewhen (io.enq(0).valid && direct_to_q) { for (i <- 0 until nVirtualChannels) { when (io.enq(0).bits.virt_channel_id === i.U) { qs(i).io.enq.valid := true.B qs(i).io.enq.bits := flit } } } if (useOutputQueues) { val can_to_q = (0 until nVirtualChannels).map { i => !empty(i) && qs(i).io.enq.ready } val to_q_oh = PriorityEncoderOH(can_to_q) val to_q = OHToUInt(to_q_oh) when (can_to_q.orR) { val head = Mux1H(to_q_oh, heads) heads(to_q) := Mux( head === Mux1H(to_q_oh, ends.map(_ - 1).map(_ max 0).map(_.U)), Mux1H(to_q_oh, starts.map(_.U)), head + 1.U) for (i <- 0 until nVirtualChannels) { when (to_q_oh(i)) { qs(i).io.enq.valid := true.B qs(i).io.enq.bits := mem.read(head) } } } for (i <- 0 until nVirtualChannels) { io.deq(i) <> qs(i).io.deq } } else { qs.map(_.io.deq.ready := false.B) val ready_sel = io.deq.map(_.ready) val fire = io.deq.map(_.fire) assert(PopCount(fire) <= 1.U) val head = Mux1H(fire, heads) when (fire.orR) { val fire_idx = OHToUInt(fire) heads(fire_idx) := Mux( head === Mux1H(fire, ends.map(_ - 1).map(_ max 0).map(_.U)), Mux1H(fire, starts.map(_.U)), head + 1.U) } val read_flit = mem.read(head) for (i <- 0 until nVirtualChannels) { io.deq(i).valid := !empty(i) io.deq(i).bits := read_flit } } } } class InputUnit(cParam: ChannelParams, outParams: Seq[ChannelParams], egressParams: Seq[EgressChannelParams], combineRCVA: Boolean, combineSAST: Boolean ) (implicit p: Parameters) extends AbstractInputUnit(cParam, outParams, egressParams)(p) { val nVirtualChannels = cParam.nVirtualChannels val virtualChannelParams = cParam.virtualChannelParams class InputUnitIO extends AbstractInputUnitIO(cParam, outParams, egressParams) { val in = Flipped(new Channel(cParam.asInstanceOf[ChannelParams])) } val io = IO(new InputUnitIO) val g_i :: g_r :: g_v :: g_a :: g_c :: Nil = Enum(5) class InputState extends Bundle { val g = UInt(3.W) val vc_sel = MixedVec(allOutParams.map { u => Vec(u.nVirtualChannels, Bool()) }) val flow = new FlowRoutingBundle val fifo_deps = UInt(nVirtualChannels.W) } val input_buffer = Module(new InputBuffer(cParam)) for (i <- 0 until cParam.srcSpeedup) { input_buffer.io.enq(i) := io.in.flit(i) } input_buffer.io.deq.foreach(_.ready := false.B) val route_arbiter = Module(new Arbiter( new RouteComputerReq, nVirtualChannels )) io.router_req <> route_arbiter.io.out val states = Reg(Vec(nVirtualChannels, new InputState)) val anyFifo = cParam.possibleFlows.map(_.fifo).reduce(_\|\|_) val allFifo = cParam.possibleFlows.map(_.fifo).reduce(_&&_) if (anyFifo) { val idle_mask = VecInit(states.map(_.g === g_i)).asUInt for (s <- states) for (i <- 0 until nVirtualChannels) s.fifo_deps := s.fifo_deps & ~idle_mask } for (i <- 0 until cParam.srcSpeedup) { when (io.in.flit(i).fire && io.in.flit(i).bits.head) { val id = io.in.flit(i).bits.virt_channel_id assert(id < nVirtualChannels.U) assert(states(id).g === g_i) val at_dest = io.in.flit(i).bits.flow.egress_node === nodeId.U states(id).g := Mux(at_dest, g_v, g_r) states(id).vc_sel.foreach(_.foreach(_ := false.B)) for (o <- 0 until nEgress) { when (o.U === io.in.flit(i).bits.flow.egress_node_id) { states(id).vc_sel(o+nOutputs)(0) := true.B } } states(id).flow := io.in.flit(i).bits.flow if (anyFifo) { val fifo = cParam.possibleFlows.filter(_.fifo).map(_.isFlow(io.in.flit(i).bits.flow)).toSeq.orR states(id).fifo_deps := VecInit(states.zipWithIndex.map { case (s, j) => s.g =/= g_i && s.flow.asUInt === io.in.flit(i).bits.flow.asUInt && j.U =/= id }).asUInt } } } (route_arbiter.io.in zip states).zipWithIndex.map { case ((i,s),idx) => if (virtualChannelParams(idx).traversable) { i.valid := s.g === g_r i.bits.flow := s.flow i.bits.src_virt_id := idx.U when (i.fire) { s.g := g_v } } else { i.valid := false.B i.bits := DontCare } } when (io.router_req.fire) { val id = io.router_req.bits.src_virt_id assert(states(id).g === g_r) states(id).g := g_v for (i <- 0 until nVirtualChannels) { when (i.U === id) { states(i).vc_sel := io.router_resp.vc_sel } } } val mask = RegInit(0.U(nVirtualChannels.W)) val vcalloc_reqs = Wire(Vec(nVirtualChannels, new VCAllocReq(cParam, outParams, egressParams))) val vcalloc_vals = Wire(Vec(nVirtualChannels, Bool())) val vcalloc_filter = PriorityEncoderOH(Cat(vcalloc_vals.asUInt, vcalloc_vals.asUInt & ~mask)) val vcalloc_sel = vcalloc_filter(nVirtualChannels-1,0) \| (vcalloc_filter >> nVirtualChannels) // Prioritize incoming packetes when (io.router_req.fire) { mask := (1.U << io.router_req.bits.src_virt_id) - 1.U } .elsewhen (vcalloc_vals.orR) { mask := Mux1H(vcalloc_sel, (0 until nVirtualChannels).map { w => ~(0.U((w+1).W)) }) } io.vcalloc_req.valid := vcalloc_vals.orR io.vcalloc_req.bits := Mux1H(vcalloc_sel, vcalloc_reqs) states.zipWithIndex.map { case (s,idx) => if (virtualChannelParams(idx).traversable) { vcalloc_vals(idx) := s.g === g_v && s.fifo_deps === 0.U vcalloc_reqs(idx).in_vc := idx.U vcalloc_reqs(idx).vc_sel := s.vc_sel vcalloc_reqs(idx).flow := s.flow when (vcalloc_vals(idx) && vcalloc_sel(idx) && io.vcalloc_req.ready) { s.g := g_a } if (combineRCVA) { when (route_arbiter.io.in(idx).fire) { vcalloc_vals(idx) := true.B vcalloc_reqs(idx).vc_sel := io.router_resp.vc_sel } } } else { vcalloc_vals(idx) := false.B vcalloc_reqs(idx) := DontCare } } io.debug.va_stall := PopCount(vcalloc_vals) - io.vcalloc_req.ready when (io.vcalloc_req.fire) { for (i <- 0 until nVirtualChannels) { when (vcalloc_sel(i)) { states(i).vc_sel := io.vcalloc_resp.vc_sel states(i).g := g_a if (!combineRCVA) { assert(states(i).g === g_v) } } } } val salloc_arb = Module(new SwitchArbiter( nVirtualChannels, cParam.destSpeedup, outParams, egressParams )) (states zip salloc_arb.io.in).zipWithIndex.map { case ((s,r),i) => if (virtualChannelParams(i).traversable) { val credit_available = (s.vc_sel.asUInt & io.out_credit_available.asUInt) =/= 0.U r.valid := s.g === g_a && credit_available && input_buffer.io.deq(i).valid r.bits.vc_sel := s.vc_sel val deq_tail = input_buffer.io.deq(i).bits.tail r.bits.tail := deq_tail when (r.fire && deq_tail) { s.g := g_i } input_buffer.io.deq(i).ready := r.ready } else { r.valid := false.B r.bits := DontCare } } io.debug.sa_stall := PopCount(salloc_arb.io.in.map(r => r.valid && !r.ready)) io.salloc_req <> salloc_arb.io.out when (io.block) { salloc_arb.io.out.foreach(_.ready := false.B) io.salloc_req.foreach(_.valid := false.B) } class OutBundle extends Bundle { val valid = Bool() val vid = UInt(virtualChannelBits.W) val out_vid = UInt(log2Up(allOutParams.map(_.nVirtualChannels).max).W) val flit = new Flit(cParam.payloadBits) } val salloc_outs = if (combineSAST) { Wire(Vec(cParam.destSpeedup, new OutBundle)) } else { Reg(Vec(cParam.destSpeedup, new OutBundle)) } io.in.credit_return := salloc_arb.io.out.zipWithIndex.map { case (o, i) => Mux(o.fire, salloc_arb.io.chosen_oh(i), 0.U) }.reduce(_\|_) io.in.vc_free := salloc_arb.io.out.zipWithIndex.map { case (o, i) => Mux(o.fire && Mux1H(salloc_arb.io.chosen_oh(i), input_buffer.io.deq.map(_.bits.tail)), salloc_arb.io.chosen_oh(i), 0.U) }.reduce(_\|_) for (i <- 0 until cParam.destSpeedup) { val salloc_out = salloc_outs(i) salloc_out.valid := salloc_arb.io.out(i).fire salloc_out.vid := OHToUInt(salloc_arb.io.chosen_oh(i)) val vc_sel = Mux1H(salloc_arb.io.chosen_oh(i), states.map(_.vc_sel)) val channel_oh = vc_sel.map(_.reduce(_\|\|_)).toSeq val virt_channel = Mux1H(channel_oh, vc_sel.map(v => OHToUInt(v)).toSeq) when (salloc_arb.io.out(i).fire) { salloc_out.out_vid := virt_channel salloc_out.flit.payload := Mux1H(salloc_arb.io.chosen_oh(i), input_buffer.io.deq.map(_.bits.payload)) salloc_out.flit.head := Mux1H(salloc_arb.io.chosen_oh(i), input_buffer.io.deq.map(_.bits.head)) salloc_out.flit.tail := Mux1H(salloc_arb.io.chosen_oh(i), input_buffer.io.deq.map(_.bits.tail)) salloc_out.flit.flow := Mux1H(salloc_arb.io.chosen_oh(i), states.map(_.flow)) } .otherwise { salloc_out.out_vid := DontCare salloc_out.flit := DontCare } salloc_out.flit.virt_channel_id := DontCare // this gets set in the switch io.out(i).valid := salloc_out.valid io.out(i).bits.flit := salloc_out.flit io.out(i).bits.out_virt_channel := salloc_out.out_vid } def filterVCSel(sel: MixedVec[Vec[Bool]], srcV: Int) = { if (virtualChannelParams(srcV).traversable) { outParams.zipWithIndex.map { case (oP, oI) => (0 until oP.nVirtualChannels).map { oV => var allow = false virtualChannelParams(srcV).possibleFlows.foreach { pI => allow = allow \|\| routingRelation( cParam.channelRoutingInfos(srcV), oP.channelRoutingInfos(oV), pI ) } if (!allow) sel(oI)(oV) := false.B } } } } (0 until nVirtualChannels).map { i => if (!virtualChannelParams(i).traversable) states(i) := DontCare filterVCSel(states(i).vc_sel, i) } when (reset.asBool) { states.foreach(_.g := g_i) } }	module InputUnit_15( // @[InputUnit.scala:158:7] input clock, // @[InputUnit.scala:158:7] input reset, // @[InputUnit.scala:158:7] output [2:0] io_router_req_bits_src_virt_id, // @[InputUnit.scala:170:14] output [2:0] io_router_req_bits_flow_vnet_id, // @[InputUnit.scala:170:14] output [4:0] io_router_req_bits_flow_ingress_node, // @[InputUnit.scala:170:14] output [1:0] io_router_req_bits_flow_ingress_node_id, // @[InputUnit.scala:170:14] output [4:0] io_router_req_bits_flow_egress_node, // @[InputUnit.scala:170:14] output [1:0] io_router_req_bits_flow_egress_node_id, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_2_1, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_2_2, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_2_3, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_2_4, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_2_5, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_2_6, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_2_7, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_0_1, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_0_2, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_0_3, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_0_4, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_0_5, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_0_6, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_0_7, // @[InputUnit.scala:170:14] input io_vcalloc_req_ready, // @[InputUnit.scala:170:14] output io_vcalloc_req_valid, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_2_1, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_2_2, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_2_3, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_2_4, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_2_5, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_2_6, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_2_7, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_0_1, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_0_2, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_0_3, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_0_4, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_0_5, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_0_6, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_0_7, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_2_1, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_2_2, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_2_3, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_2_4, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_2_5, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_2_6, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_2_7, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_0_1, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_0_2, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_0_3, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_0_4, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_0_5, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_0_6, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_0_7, // @[InputUnit.scala:170:14] input io_out_credit_available_2_1, // @[InputUnit.scala:170:14] input io_out_credit_available_2_2, // @[InputUnit.scala:170:14] input io_out_credit_available_2_3, // @[InputUnit.scala:170:14] input io_out_credit_available_2_4, // @[InputUnit.scala:170:14] input io_out_credit_available_2_5, // @[InputUnit.scala:170:14] input io_out_credit_available_2_6, // @[InputUnit.scala:170:14] input io_out_credit_available_2_7, // @[InputUnit.scala:170:14] input io_out_credit_available_1_4, // @[InputUnit.scala:170:14] input io_out_credit_available_1_5, // @[InputUnit.scala:170:14] input io_out_credit_available_1_6, // @[InputUnit.scala:170:14] input io_out_credit_available_1_7, // @[InputUnit.scala:170:14] input io_out_credit_available_0_1, // @[InputUnit.scala:170:14] input io_out_credit_available_0_2, // @[InputUnit.scala:170:14] input io_out_credit_available_0_3, // @[InputUnit.scala:170:14] input io_out_credit_available_0_4, // @[InputUnit.scala:170:14] input io_out_credit_available_0_5, // @[InputUnit.scala:170:14] input io_out_credit_available_0_6, // @[InputUnit.scala:170:14] input io_out_credit_available_0_7, // @[InputUnit.scala:170:14] input io_salloc_req_0_ready, // @[InputUnit.scala:170:14] output io_salloc_req_0_valid, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_2_0, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_2_1, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_2_2, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_2_3, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_2_4, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_2_5, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_2_6, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_2_7, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_1_0, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_1_1, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_1_2, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_1_3, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_1_4, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_1_5, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_1_6, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_1_7, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_0_1, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_0_2, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_0_3, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_0_4, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_0_5, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_0_6, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_0_7, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_tail, // @[InputUnit.scala:170:14] output io_out_0_valid, // @[InputUnit.scala:170:14] output io_out_0_bits_flit_head, // @[InputUnit.scala:170:14] output io_out_0_bits_flit_tail, // @[InputUnit.scala:170:14] output [72:0] io_out_0_bits_flit_payload, // @[InputUnit.scala:170:14] output [2:0] io_out_0_bits_flit_flow_vnet_id, // @[InputUnit.scala:170:14] output [4:0] io_out_0_bits_flit_flow_ingress_node, // @[InputUnit.scala:170:14] output [1:0] io_out_0_bits_flit_flow_ingress_node_id, // @[InputUnit.scala:170:14] output [4:0] io_out_0_bits_flit_flow_egress_node, // @[InputUnit.scala:170:14] output [1:0] io_out_0_bits_flit_flow_egress_node_id, // @[InputUnit.scala:170:14] output [2:0] io_out_0_bits_out_virt_channel, // @[InputUnit.scala:170:14] output [2:0] io_debug_va_stall, // @[InputUnit.scala:170:14] output [2:0] io_debug_sa_stall, // @[InputUnit.scala:170:14] input io_in_flit_0_valid, // @[InputUnit.scala:170:14] input io_in_flit_0_bits_head, // @[InputUnit.scala:170:14] input io_in_flit_0_bits_tail, // @[InputUnit.scala:170:14] input [72:0] io_in_flit_0_bits_payload, // @[InputUnit.scala:170:14] input [2:0] io_in_flit_0_bits_flow_vnet_id, // @[InputUnit.scala:170:14] input [4:0] io_in_flit_0_bits_flow_ingress_node, // @[InputUnit.scala:170:14] input [1:0] io_in_flit_0_bits_flow_ingress_node_id, // @[InputUnit.scala:170:14] input [4:0] io_in_flit_0_bits_flow_egress_node, // @[InputUnit.scala:170:14] input [1:0] io_in_flit_0_bits_flow_egress_node_id, // @[InputUnit.scala:170:14] input [2:0] io_in_flit_0_bits_virt_channel_id, // @[InputUnit.scala:170:14] output [7:0] io_in_credit_return, // @[InputUnit.scala:170:14] output [7:0] io_in_vc_free // @[InputUnit.scala:170:14] ); wire vcalloc_vals_7; // @[InputUnit.scala:266:32] wire vcalloc_vals_6; // @[InputUnit.scala:266:32] wire vcalloc_vals_5; // @[InputUnit.scala:266:32] wire vcalloc_vals_4; // @[InputUnit.scala:266:32] wire vcalloc_vals_3; // @[InputUnit.scala:266:32] wire vcalloc_vals_2; // @[InputUnit.scala:266:32] wire vcalloc_vals_1; // @[InputUnit.scala:266:32] wire _salloc_arb_io_in_1_ready; // @[InputUnit.scala:296:26] wire _salloc_arb_io_in_2_ready; // @[InputUnit.scala:296:26] wire _salloc_arb_io_in_3_ready; // @[InputUnit.scala:296:26] wire _salloc_arb_io_in_4_ready; // @[InputUnit.scala:296:26] wire _salloc_arb_io_in_5_ready; // @[InputUnit.scala:296:26] wire _salloc_arb_io_in_6_ready; // @[InputUnit.scala:296:26] wire _salloc_arb_io_in_7_ready; // @[InputUnit.scala:296:26] wire _salloc_arb_io_out_0_valid; // @[InputUnit.scala:296:26] wire [7:0] _salloc_arb_io_chosen_oh_0; // @[InputUnit.scala:296:26] wire _route_arbiter_io_in_1_ready; // @[InputUnit.scala:187:29] wire _route_arbiter_io_in_2_ready; // @[InputUnit.scala:187:29] wire _route_arbiter_io_in_3_ready; // @[InputUnit.scala:187:29] wire _route_arbiter_io_in_4_ready; // @[InputUnit.scala:187:29] wire _route_arbiter_io_in_5_ready; // @[InputUnit.scala:187:29] wire _route_arbiter_io_in_6_ready; // @[InputUnit.scala:187:29] wire _route_arbiter_io_in_7_ready; // @[InputUnit.scala:187:29] wire _route_arbiter_io_out_valid; // @[InputUnit.scala:187:29] wire [2:0] _route_arbiter_io_out_bits_src_virt_id; // @[InputUnit.scala:187:29] wire _input_buffer_io_deq_0_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_0_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_0_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_1_valid; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_1_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_1_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_1_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_2_valid; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_2_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_2_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_2_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_3_valid; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_3_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_3_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_3_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_4_valid; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_4_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_4_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_4_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_5_valid; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_5_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_5_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_5_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_6_valid; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_6_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_6_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_6_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_7_valid; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_7_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_7_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_7_bits_payload; // @[InputUnit.scala:181:28] reg [2:0] states_1_g; // @[InputUnit.scala:192:19] reg states_1_vc_sel_2_1; // @[InputUnit.scala:192:19] reg states_1_vc_sel_0_1; // @[InputUnit.scala:192:19] reg states_1_vc_sel_0_2; // @[InputUnit.scala:192:19] reg states_1_vc_sel_0_3; // @[InputUnit.scala:192:19] reg states_1_vc_sel_0_4; // @[InputUnit.scala:192:19] reg states_1_vc_sel_0_5; // @[InputUnit.scala:192:19] reg states_1_vc_sel_0_6; // @[InputUnit.scala:192:19] reg states_1_vc_sel_0_7; // @[InputUnit.scala:192:19] reg [2:0] states_1_flow_vnet_id; // @[InputUnit.scala:192:19] reg [4:0] states_1_flow_ingress_node; // @[InputUnit.scala:192:19] reg [1:0] states_1_flow_ingress_node_id; // @[InputUnit.scala:192:19] reg [4:0] states_1_flow_egress_node; // @[InputUnit.scala:192:19] reg [1:0] states_1_flow_egress_node_id; // @[InputUnit.scala:192:19] reg [2:0] states_2_g; // @[InputUnit.scala:192:19] reg states_2_vc_sel_2_1; // @[InputUnit.scala:192:19] reg states_2_vc_sel_2_2; // @[InputUnit.scala:192:19] reg states_2_vc_sel_2_3; // @[InputUnit.scala:192:19] reg states_2_vc_sel_2_4; // @[InputUnit.scala:192:19] reg states_2_vc_sel_2_5; // @[InputUnit.scala:192:19] reg states_2_vc_sel_2_6; // @[InputUnit.scala:192:19] reg states_2_vc_sel_2_7; // @[InputUnit.scala:192:19] reg states_2_vc_sel_0_1; // @[InputUnit.scala:192:19] reg states_2_vc_sel_0_2; // @[InputUnit.scala:192:19] reg states_2_vc_sel_0_3; // @[InputUnit.scala:192:19] reg states_2_vc_sel_0_4; // @[InputUnit.scala:192:19] reg states_2_vc_sel_0_5; // @[InputUnit.scala:192:19] reg states_2_vc_sel_0_6; // @[InputUnit.scala:192:19] reg states_2_vc_sel_0_7; // @[InputUnit.scala:192:19] reg [2:0] states_2_flow_vnet_id; // @[InputUnit.scala:192:19] reg [4:0] states_2_flow_ingress_node; // @[InputUnit.scala:192:19] reg [1:0] states_2_flow_ingress_node_id; // @[InputUnit.scala:192:19] reg [4:0] states_2_flow_egress_node; // @[InputUnit.scala:192:19] reg [1:0] states_2_flow_egress_node_id; // @[InputUnit.scala:192:19] reg [2:0] states_3_g; // @[InputUnit.scala:192:19] reg states_3_vc_sel_2_1; // @[InputUnit.scala:192:19] reg states_3_vc_sel_2_2; // @[InputUnit.scala:192:19] reg states_3_vc_sel_2_3; // @[InputUnit.scala:192:19] reg states_3_vc_sel_2_4; // @[InputUnit.scala:192:19] reg states_3_vc_sel_2_5; // @[InputUnit.scala:192:19] reg states_3_vc_sel_2_6; // @[InputUnit.scala:192:19] reg states_3_vc_sel_2_7; // @[InputUnit.scala:192:19] reg states_3_vc_sel_0_1; // @[InputUnit.scala:192:19] reg states_3_vc_sel_0_2; // @[InputUnit.scala:192:19] reg states_3_vc_sel_0_3; // @[InputUnit.scala:192:19] reg states_3_vc_sel_0_4; // @[InputUnit.scala:192:19] reg states_3_vc_sel_0_5; // @[InputUnit.scala:192:19] reg states_3_vc_sel_0_6; // @[InputUnit.scala:192:19] reg states_3_vc_sel_0_7; // @[InputUnit.scala:192:19] reg [2:0] states_3_flow_vnet_id; // @[InputUnit.scala:192:19] reg [4:0] states_3_flow_ingress_node; // @[InputUnit.scala:192:19] reg [1:0] states_3_flow_ingress_node_id; // @[InputUnit.scala:192:19] reg [4:0] states_3_flow_egress_node; // @[InputUnit.scala:192:19] reg [1:0] states_3_flow_egress_node_id; // @[InputUnit.scala:192:19] reg [2:0] states_4_g; // @[InputUnit.scala:192:19] reg states_4_vc_sel_2_1; // @[InputUnit.scala:192:19] reg states_4_vc_sel_2_2; // @[InputUnit.scala:192:19] reg states_4_vc_sel_2_3; // @[InputUnit.scala:192:19] reg states_4_vc_sel_2_4; // @[InputUnit.scala:192:19] reg states_4_vc_sel_2_5; // @[InputUnit.scala:192:19] reg states_4_vc_sel_2_6; // @[InputUnit.scala:192:19] reg states_4_vc_sel_2_7; // @[InputUnit.scala:192:19] reg states_4_vc_sel_0_1; // @[InputUnit.scala:192:19] reg states_4_vc_sel_0_2; // @[InputUnit.scala:192:19] reg states_4_vc_sel_0_3; // @[InputUnit.scala:192:19] reg states_4_vc_sel_0_4; // @[InputUnit.scala:192:19] reg states_4_vc_sel_0_5; // @[InputUnit.scala:192:19] reg states_4_vc_sel_0_6; // @[InputUnit.scala:192:19] reg states_4_vc_sel_0_7; // @[InputUnit.scala:192:19] reg [2:0] states_4_flow_vnet_id; // @[InputUnit.scala:192:19] reg [4:0] states_4_flow_ingress_node; // @[InputUnit.scala:192:19] reg [1:0] states_4_flow_ingress_node_id; // @[InputUnit.scala:192:19] reg [4:0] states_4_flow_egress_node; // @[InputUnit.scala:192:19] reg [1:0] states_4_flow_egress_node_id; // @[InputUnit.scala:192:19] reg [2:0] states_5_g; // @[InputUnit.scala:192:19] reg states_5_vc_sel_2_1; // @[InputUnit.scala:192:19] reg states_5_vc_sel_2_2; // @[InputUnit.scala:192:19] reg states_5_vc_sel_2_3; // @[InputUnit.scala:192:19] reg states_5_vc_sel_2_4; // @[InputUnit.scala:192:19] reg states_5_vc_sel_2_5; // @[InputUnit.scala:192:19] reg states_5_vc_sel_2_6; // @[InputUnit.scala:192:19] reg states_5_vc_sel_2_7; // @[InputUnit.scala:192:19] reg states_5_vc_sel_0_1; // @[InputUnit.scala:192:19] reg states_5_vc_sel_0_2; // @[InputUnit.scala:192:19] reg states_5_vc_sel_0_3; // @[InputUnit.scala:192:19] reg states_5_vc_sel_0_4; // @[InputUnit.scala:192:19] reg states_5_vc_sel_0_5; // @[InputUnit.scala:192:19] reg states_5_vc_sel_0_6; // @[InputUnit.scala:192:19] reg states_5_vc_sel_0_7; // @[InputUnit.scala:192:19] reg [2:0] states_5_flow_vnet_id; // @[InputUnit.scala:192:19] reg [4:0] states_5_flow_ingress_node; // @[InputUnit.scala:192:19] reg [1:0] states_5_flow_ingress_node_id; // @[InputUnit.scala:192:19] reg [4:0] states_5_flow_egress_node; // @[InputUnit.scala:192:19] reg [1:0] states_5_flow_egress_node_id; // @[InputUnit.scala:192:19] reg [2:0] states_6_g; // @[InputUnit.scala:192:19] reg states_6_vc_sel_2_1; // @[InputUnit.scala:192:19] reg states_6_vc_sel_2_2; // @[InputUnit.scala:192:19] reg states_6_vc_sel_2_3; // @[InputUnit.scala:192:19] reg states_6_vc_sel_2_4; // @[InputUnit.scala:192:19] reg states_6_vc_sel_2_5; // @[InputUnit.scala:192:19] reg states_6_vc_sel_2_6; // @[InputUnit.scala:192:19] reg states_6_vc_sel_2_7; // @[InputUnit.scala:192:19] reg states_6_vc_sel_0_1; // @[InputUnit.scala:192:19] reg states_6_vc_sel_0_2; // @[InputUnit.scala:192:19] reg states_6_vc_sel_0_3; // @[InputUnit.scala:192:19] reg states_6_vc_sel_0_4; // @[InputUnit.scala:192:19] reg states_6_vc_sel_0_5; // @[InputUnit.scala:192:19] reg states_6_vc_sel_0_6; // @[InputUnit.scala:192:19] reg states_6_vc_sel_0_7; // @[InputUnit.scala:192:19] reg [2:0] states_6_flow_vnet_id; // @[InputUnit.scala:192:19] reg [4:0] states_6_flow_ingress_node; // @[InputUnit.scala:192:19] reg [1:0] states_6_flow_ingress_node_id; // @[InputUnit.scala:192:19] reg [4:0] states_6_flow_egress_node; // @[InputUnit.scala:192:19] reg [1:0] states_6_flow_egress_node_id; // @[InputUnit.scala:192:19] reg [2:0] states_7_g; // @[InputUnit.scala:192:19] reg states_7_vc_sel_2_1; // @[InputUnit.scala:192:19] reg states_7_vc_sel_2_2; // @[InputUnit.scala:192:19] reg states_7_vc_sel_2_3; // @[InputUnit.scala:192:19] reg states_7_vc_sel_2_4; // @[InputUnit.scala:192:19] reg states_7_vc_sel_2_5; // @[InputUnit.scala:192:19] reg states_7_vc_sel_2_6; // @[InputUnit.scala:192:19] reg states_7_vc_sel_2_7; // @[InputUnit.scala:192:19] reg states_7_vc_sel_0_1; // @[InputUnit.scala:192:19] reg states_7_vc_sel_0_2; // @[InputUnit.scala:192:19] reg states_7_vc_sel_0_3; // @[InputUnit.scala:192:19] reg states_7_vc_sel_0_4; // @[InputUnit.scala:192:19] reg states_7_vc_sel_0_5; // @[InputUnit.scala:192:19] reg states_7_vc_sel_0_6; // @[InputUnit.scala:192:19] reg states_7_vc_sel_0_7; // @[InputUnit.scala:192:19] reg [2:0] states_7_flow_vnet_id; // @[InputUnit.scala:192:19] reg [4:0] states_7_flow_ingress_node; // @[InputUnit.scala:192:19] reg [1:0] states_7_flow_ingress_node_id; // @[InputUnit.scala:192:19] reg [4:0] states_7_flow_egress_node; // @[InputUnit.scala:192:19] reg [1:0] states_7_flow_egress_node_id; // @[InputUnit.scala:192:19] wire _GEN = io_in_flit_0_valid & io_in_flit_0_bits_head; // @[InputUnit.scala:205:30] wire route_arbiter_io_in_1_valid = states_1_g == 3'h1; // @[InputUnit.scala:192:19, :229:22] wire route_arbiter_io_in_2_valid = states_2_g == 3'h1; // @[InputUnit.scala:192:19, :229:22] wire route_arbiter_io_in_3_valid = states_3_g == 3'h1; // @[InputUnit.scala:192:19, :229:22] wire route_arbiter_io_in_4_valid = states_4_g == 3'h1; // @[InputUnit.scala:192:19, :229:22] wire route_arbiter_io_in_5_valid = states_5_g == 3'h1; // @[InputUnit.scala:192:19, :229:22] wire route_arbiter_io_in_6_valid = states_6_g == 3'h1; // @[InputUnit.scala:192:19, :229:22] wire route_arbiter_io_in_7_valid = states_7_g == 3'h1; // @[InputUnit.scala:192:19, :229:22] reg [7:0] mask; // @[InputUnit.scala:250:21] wire [7:0] _vcalloc_filter_T_3 = {vcalloc_vals_7, vcalloc_vals_6, vcalloc_vals_5, vcalloc_vals_4, vcalloc_vals_3, vcalloc_vals_2, vcalloc_vals_1, 1'h0} & ~mask; // @[InputUnit.scala:250:21, :253:{80,87,89}, :266:32] wire [15:0] vcalloc_filter = _vcalloc_filter_T_3[0] ? 16'h1 : _vcalloc_filter_T_3[1] ? 16'h2 : _vcalloc_filter_T_3[2] ? 16'h4 : _vcalloc_filter_T_3[3] ? 16'h8 : _vcalloc_filter_T_3[4] ? 16'h10 : _vcalloc_filter_T_3[5] ? 16'h20 : _vcalloc_filter_T_3[6] ? 16'h40 : _vcalloc_filter_T_3[7] ? 16'h80 : vcalloc_vals_1 ? 16'h200 : vcalloc_vals_2 ? 16'h400 : vcalloc_vals_3 ? 16'h800 : vcalloc_vals_4 ? 16'h1000 : vcalloc_vals_5 ? 16'h2000 : vcalloc_vals_6 ? 16'h4000 : {vcalloc_vals_7, 15'h0}; // @[OneHot.scala:85:71] wire [7:0] vcalloc_sel = vcalloc_filter[7:0] \| vcalloc_filter[15:8]; // @[Mux.scala:50:70] wire io_vcalloc_req_valid_0 = vcalloc_vals_1 \| vcalloc_vals_2 \| vcalloc_vals_3 \| vcalloc_vals_4 \| vcalloc_vals_5 \| vcalloc_vals_6 \| vcalloc_vals_7; // @[package.scala:81:59] assign vcalloc_vals_1 = states_1_g == 3'h2; // @[InputUnit.scala:192:19, :266:32] assign vcalloc_vals_2 = states_2_g == 3'h2; // @[InputUnit.scala:192:19, :266:32] assign vcalloc_vals_3 = states_3_g == 3'h2; // @[InputUnit.scala:192:19, :266:32] assign vcalloc_vals_4 = states_4_g == 3'h2; // @[InputUnit.scala:192:19, :266:32] assign vcalloc_vals_5 = states_5_g == 3'h2; // @[InputUnit.scala:192:19, :266:32] assign vcalloc_vals_6 = states_6_g == 3'h2; // @[InputUnit.scala:192:19, :266:32] assign vcalloc_vals_7 = states_7_g == 3'h2; // @[InputUnit.scala:192:19, :266:32] wire _GEN_0 = io_vcalloc_req_ready & io_vcalloc_req_valid_0; // @[Decoupled.scala:51:35] wire _GEN_1 = _GEN_0 & vcalloc_sel[1]; // @[Mux.scala:32:36] wire _GEN_2 = _GEN_0 & vcalloc_sel[2]; // @[Mux.scala:32:36] wire _GEN_3 = _GEN_0 & vcalloc_sel[3]; // @[Mux.scala:32:36] wire _GEN_4 = _GEN_0 & vcalloc_sel[4]; // @[Mux.scala:32:36] wire _GEN_5 = _GEN_0 & vcalloc_sel[5]; // @[Mux.scala:32:36] wire _GEN_6 = _GEN_0 & vcalloc_sel[6]; // @[Mux.scala:32:36] wire _GEN_7 = _GEN_0 & vcalloc_sel[7]; // @[Mux.scala:32:36]
Generate the Verilog code corresponding to the following Chisel files. File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /* Like Vec.apply(idx), but tolerates indices of mismatched width / def extract(idx: UInt): T = x((idx \| 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx \| 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def \| (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a \|\| b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_\|\|_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /* Any Data subtype that has a Bool member named valid. / type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /* converts from camel case to to underscores, also removing all spaces / def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /* converts spaces or underscores to hyphens, also lowering case / def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y \| (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y \|\| y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 \| 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /* Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation */ def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag }	module OptimizationBarrier_TLBEntryData_26( // @[package.scala:267:30] input clock, // @[package.scala:267:30] input reset, // @[package.scala:267:30] input [19:0] io_x_ppn, // @[package.scala:268:18] input io_x_u, // @[package.scala:268:18] input io_x_g, // @[package.scala:268:18] input io_x_ae_ptw, // @[package.scala:268:18] input io_x_ae_final, // @[package.scala:268:18] input io_x_ae_stage2, // @[package.scala:268:18] input io_x_pf, // @[package.scala:268:18] input io_x_gf, // @[package.scala:268:18] input io_x_sw, // @[package.scala:268:18] input io_x_sx, // @[package.scala:268:18] input io_x_sr, // @[package.scala:268:18] input io_x_hw, // @[package.scala:268:18] input io_x_hx, // @[package.scala:268:18] input io_x_hr, // @[package.scala:268:18] input io_x_pw, // @[package.scala:268:18] input io_x_px, // @[package.scala:268:18] input io_x_pr, // @[package.scala:268:18] input io_x_ppp, // @[package.scala:268:18] input io_x_pal, // @[package.scala:268:18] input io_x_paa, // @[package.scala:268:18] input io_x_eff, // @[package.scala:268:18] input io_x_c, // @[package.scala:268:18] input io_x_fragmented_superpage, // @[package.scala:268:18] output [19:0] io_y_ppn, // @[package.scala:268:18] output io_y_u, // @[package.scala:268:18] output io_y_ae_ptw, // @[package.scala:268:18] output io_y_ae_final, // @[package.scala:268:18] output io_y_ae_stage2, // @[package.scala:268:18] output io_y_pf, // @[package.scala:268:18] output io_y_gf, // @[package.scala:268:18] output io_y_sw, // @[package.scala:268:18] output io_y_sx, // @[package.scala:268:18] output io_y_sr, // @[package.scala:268:18] output io_y_hw, // @[package.scala:268:18] output io_y_hx, // @[package.scala:268:18] output io_y_hr, // @[package.scala:268:18] output io_y_pw, // @[package.scala:268:18] output io_y_px, // @[package.scala:268:18] output io_y_pr, // @[package.scala:268:18] output io_y_ppp, // @[package.scala:268:18] output io_y_pal, // @[package.scala:268:18] output io_y_paa, // @[package.scala:268:18] output io_y_eff, // @[package.scala:268:18] output io_y_c // @[package.scala:268:18] ); wire [19:0] io_x_ppn_0 = io_x_ppn; // @[package.scala:267:30] wire io_x_u_0 = io_x_u; // @[package.scala:267:30] wire io_x_g_0 = io_x_g; // @[package.scala:267:30] wire io_x_ae_ptw_0 = io_x_ae_ptw; // @[package.scala:267:30] wire io_x_ae_final_0 = io_x_ae_final; // @[package.scala:267:30] wire io_x_ae_stage2_0 = io_x_ae_stage2; // @[package.scala:267:30] wire io_x_pf_0 = io_x_pf; // @[package.scala:267:30] wire io_x_gf_0 = io_x_gf; // @[package.scala:267:30] wire io_x_sw_0 = io_x_sw; // @[package.scala:267:30] wire io_x_sx_0 = io_x_sx; // @[package.scala:267:30] wire io_x_sr_0 = io_x_sr; // @[package.scala:267:30] wire io_x_hw_0 = io_x_hw; // @[package.scala:267:30] wire io_x_hx_0 = io_x_hx; // @[package.scala:267:30] wire io_x_hr_0 = io_x_hr; // @[package.scala:267:30] wire io_x_pw_0 = io_x_pw; // @[package.scala:267:30] wire io_x_px_0 = io_x_px; // @[package.scala:267:30] wire io_x_pr_0 = io_x_pr; // @[package.scala:267:30] wire io_x_ppp_0 = io_x_ppp; // @[package.scala:267:30] wire io_x_pal_0 = io_x_pal; // @[package.scala:267:30] wire io_x_paa_0 = io_x_paa; // @[package.scala:267:30] wire io_x_eff_0 = io_x_eff; // @[package.scala:267:30] wire io_x_c_0 = io_x_c; // @[package.scala:267:30] wire io_x_fragmented_superpage_0 = io_x_fragmented_superpage; // @[package.scala:267:30] wire [19:0] io_y_ppn_0 = io_x_ppn_0; // @[package.scala:267:30] wire io_y_u_0 = io_x_u_0; // @[package.scala:267:30] wire io_y_g = io_x_g_0; // @[package.scala:267:30] wire io_y_ae_ptw_0 = io_x_ae_ptw_0; // @[package.scala:267:30] wire io_y_ae_final_0 = io_x_ae_final_0; // @[package.scala:267:30] wire io_y_ae_stage2_0 = io_x_ae_stage2_0; // @[package.scala:267:30] wire io_y_pf_0 = io_x_pf_0; // @[package.scala:267:30] wire io_y_gf_0 = io_x_gf_0; // @[package.scala:267:30] wire io_y_sw_0 = io_x_sw_0; // @[package.scala:267:30] wire io_y_sx_0 = io_x_sx_0; // @[package.scala:267:30] wire io_y_sr_0 = io_x_sr_0; // @[package.scala:267:30] wire io_y_hw_0 = io_x_hw_0; // @[package.scala:267:30] wire io_y_hx_0 = io_x_hx_0; // @[package.scala:267:30] wire io_y_hr_0 = io_x_hr_0; // @[package.scala:267:30] wire io_y_pw_0 = io_x_pw_0; // @[package.scala:267:30] wire io_y_px_0 = io_x_px_0; // @[package.scala:267:30] wire io_y_pr_0 = io_x_pr_0; // @[package.scala:267:30] wire io_y_ppp_0 = io_x_ppp_0; // @[package.scala:267:30] wire io_y_pal_0 = io_x_pal_0; // @[package.scala:267:30] wire io_y_paa_0 = io_x_paa_0; // @[package.scala:267:30] wire io_y_eff_0 = io_x_eff_0; // @[package.scala:267:30] wire io_y_c_0 = io_x_c_0; // @[package.scala:267:30] wire io_y_fragmented_superpage = io_x_fragmented_superpage_0; // @[package.scala:267:30] assign io_y_ppn = io_y_ppn_0; // @[package.scala:267:30] assign io_y_u = io_y_u_0; // @[package.scala:267:30] assign io_y_ae_ptw = io_y_ae_ptw_0; // @[package.scala:267:30] assign io_y_ae_final = io_y_ae_final_0; // @[package.scala:267:30] assign io_y_ae_stage2 = io_y_ae_stage2_0; // @[package.scala:267:30] assign io_y_pf = io_y_pf_0; // @[package.scala:267:30] assign io_y_gf = io_y_gf_0; // @[package.scala:267:30] assign io_y_sw = io_y_sw_0; // @[package.scala:267:30] assign io_y_sx = io_y_sx_0; // @[package.scala:267:30] assign io_y_sr = io_y_sr_0; // @[package.scala:267:30] assign io_y_hw = io_y_hw_0; // @[package.scala:267:30] assign io_y_hx = io_y_hx_0; // @[package.scala:267:30] assign io_y_hr = io_y_hr_0; // @[package.scala:267:30] assign io_y_pw = io_y_pw_0; // @[package.scala:267:30] assign io_y_px = io_y_px_0; // @[package.scala:267:30] assign io_y_pr = io_y_pr_0; // @[package.scala:267:30] assign io_y_ppp = io_y_ppp_0; // @[package.scala:267:30] assign io_y_pal = io_y_pal_0; // @[package.scala:267:30] assign io_y_paa = io_y_paa_0; // @[package.scala:267:30] assign io_y_eff = io_y_eff_0; // @[package.scala:267:30] assign io_y_c = io_y_c_0; // @[package.scala:267:30] endmodule
Generate the Verilog code corresponding to the following Chisel files. File ShiftReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ // Similar to the Chisel ShiftRegister but allows the user to suggest a // name to the registers that get instantiated, and // to provide a reset value. object ShiftRegInit { def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T = (0 until n).foldRight(in) { case (i, next) => { val r = RegNext(next, init) name.foreach { na => r.suggestName(s"${na}_${i}") } r } } } /** These wrap behavioral * shift registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * The different types vary in their reset behavior: * AsyncResetShiftReg -- Asynchronously reset register array * A W(width) x D(depth) sized array is constructed from D instantiations of a * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg, * but only used for timing applications / abstract class AbstractPipelineReg(w: Int = 1) extends Module { val io = IO(new Bundle { val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) } ) } object AbstractPipelineReg { def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = { val chain = Module(gen) name.foreach{ chain.suggestName(_) } chain.io.d := in.asUInt chain.io.q.asTypeOf(in) } } class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) { require(depth > 0, "Depth must be greater than 0.") override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}" val chain = List.tabulate(depth) { i => Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}") } chain.last.io.d := io.d chain.last.io.en := true.B (chain.init zip chain.tail).foreach { case (sink, source) => sink.io.d := source.io.q sink.io.en := true.B } io.q := chain.head.io.q } object AsyncResetShiftReg { def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name) def apply [T <: Data](in: T, depth: Int, name: Option[String]): T = apply(in, depth, 0, name) def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T = apply(in, depth, init.litValue.toInt, name) def apply [T <: Data](in: T, depth: Int, init: T): T = apply (in, depth, init.litValue.toInt, None) } File SynchronizerReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util.{RegEnable, Cat} /* These wrap behavioral * shift and next registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * * These are built up of ResetSynchronizerPrimitiveShiftReg, intended to be replaced by the integrator's metastable flops chains or replaced * at this level if they have a multi-bit wide synchronizer primitive. * The different types vary in their reset behavior: * NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin * AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep * 1-bit-wide shift registers. * SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg * * [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference. * * ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross * Clock Domains. */ object SynchronizerResetType extends Enumeration { val NonSync, Inferred, Sync, Async = Value } // Note: this should not be used directly. // Use the companion object to generate this with the correct reset type mixin. private class SynchronizerPrimitiveShiftReg( sync: Int, init: Boolean, resetType: SynchronizerResetType.Value) extends AbstractPipelineReg(1) { val initInt = if (init) 1 else 0 val initPostfix = resetType match { case SynchronizerResetType.NonSync => "" case _ => s"_i${initInt}" } override def desiredName = s"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}" val chain = List.tabulate(sync) { i => val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B) reg.suggestName(s"sync_$i") } chain.last := io.d.asBool (chain.init zip chain.tail).foreach { case (sink, source) => sink := source } io.q := chain.head.asUInt } private object SynchronizerPrimitiveShiftReg { def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = { val gen: () => SynchronizerPrimitiveShiftReg = resetType match { case SynchronizerResetType.NonSync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) case SynchronizerResetType.Async => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset case SynchronizerResetType.Sync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset case SynchronizerResetType.Inferred => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) } AbstractPipelineReg(gen(), in) } } // Note: This module may end up with a non-AsyncReset type reset. // But the Primitives within will always have AsyncReset type. class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asAsyncReset){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async) } } io.q := Cat(output.reverse) } object AsyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } // Note: This module may end up with a non-Bool type reset. // But the Primitives within will always have Bool reset type. @deprecated("SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.", "rocket-chip 1.2") class SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asBool){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync) } } io.q := Cat(output.reverse) } object SyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred) } io.q := Cat(output.reverse) } object ResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}" val output = Seq.tabulate(w) { i => SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync) } io.q := Cat(output.reverse) } object SynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, None) def apply [T <: Data](in: T): T = apply (in, 3, None) } class ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module { override def desiredName = s"ClockCrossingReg_w${w}" val io = IO(new Bundle{ val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) val en = Input(Bool()) }) val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en) io.q := cdc_reg } object ClockCrossingReg { def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = { val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit)) name.foreach{ cdc_reg.suggestName(_) } cdc_reg.io.d := in.asUInt cdc_reg.io.en := en cdc_reg.io.q.asTypeOf(in) } } File AsyncQueue.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ case class AsyncQueueParams( depth: Int = 8, sync: Int = 3, safe: Boolean = true, // If safe is true, then effort is made to resynchronize the crossing indices when either side is reset. // This makes it safe/possible to reset one side of the crossing (but not the other) when the queue is empty. narrow: Boolean = false) // If narrow is true then the read mux is moved to the source side of the crossing. // This reduces the number of level shifters in the case where the clock crossing is also a voltage crossing, // at the expense of a combinational path from the sink to the source and back to the sink. { require (depth > 0 && isPow2(depth)) require (sync >= 2) val bits = log2Ceil(depth) val wires = if (narrow) 1 else depth } object AsyncQueueParams { // When there is only one entry, we don't need narrow. def singleton(sync: Int = 3, safe: Boolean = true) = AsyncQueueParams(1, sync, safe, false) } class AsyncBundleSafety extends Bundle { val ridx_valid = Input (Bool()) val widx_valid = Output(Bool()) val source_reset_n = Output(Bool()) val sink_reset_n = Input (Bool()) } class AsyncBundle[T <: Data](private val gen: T, val params: AsyncQueueParams = AsyncQueueParams()) extends Bundle { // Data-path synchronization val mem = Output(Vec(params.wires, gen)) val ridx = Input (UInt((params.bits+1).W)) val widx = Output(UInt((params.bits+1).W)) val index = params.narrow.option(Input(UInt(params.bits.W))) // Signals used to self-stabilize a safe AsyncQueue val safe = params.safe.option(new AsyncBundleSafety) } object GrayCounter { def apply(bits: Int, increment: Bool = true.B, clear: Bool = false.B, name: String = "binary"): UInt = { val incremented = Wire(UInt(bits.W)) val binary = RegNext(next=incremented, init=0.U).suggestName(name) incremented := Mux(clear, 0.U, binary + increment.asUInt) incremented ^ (incremented >> 1) } } class AsyncValidSync(sync: Int, desc: String) extends RawModule { val io = IO(new Bundle { val in = Input(Bool()) val out = Output(Bool()) }) val clock = IO(Input(Clock())) val reset = IO(Input(AsyncReset())) withClockAndReset(clock, reset){ io.out := AsyncResetSynchronizerShiftReg(io.in, sync, Some(desc)) } } class AsyncQueueSource[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module { override def desiredName = s"AsyncQueueSource_${gen.typeName}" val io = IO(new Bundle { // These come from the source domain val enq = Flipped(Decoupled(gen)) // These cross to the sink clock domain val async = new AsyncBundle(gen, params) }) val bits = params.bits val sink_ready = WireInit(true.B) val mem = Reg(Vec(params.depth, gen)) // This does NOT need to be reset at all. val widx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.enq.fire, !sink_ready, "widx_bin")) val ridx = AsyncResetSynchronizerShiftReg(io.async.ridx, params.sync, Some("ridx_gray")) val ready = sink_ready && widx =/= (ridx ^ (params.depth \| params.depth >> 1).U) val index = if (bits == 0) 0.U else io.async.widx(bits-1, 0) ^ (io.async.widx(bits, bits) << (bits-1)) when (io.enq.fire) { mem(index) := io.enq.bits } val ready_reg = withReset(reset.asAsyncReset)(RegNext(next=ready, init=false.B).suggestName("ready_reg")) io.enq.ready := ready_reg && sink_ready val widx_reg = withReset(reset.asAsyncReset)(RegNext(next=widx, init=0.U).suggestName("widx_gray")) io.async.widx := widx_reg io.async.index match { case Some(index) => io.async.mem(0) := mem(index) case None => io.async.mem := mem } io.async.safe.foreach { sio => val source_valid_0 = Module(new AsyncValidSync(params.sync, "source_valid_0")) val source_valid_1 = Module(new AsyncValidSync(params.sync, "source_valid_1")) val sink_extend = Module(new AsyncValidSync(params.sync, "sink_extend")) val sink_valid = Module(new AsyncValidSync(params.sync, "sink_valid")) source_valid_0.reset := (reset.asBool \|\| !sio.sink_reset_n).asAsyncReset source_valid_1.reset := (reset.asBool \|\| !sio.sink_reset_n).asAsyncReset sink_extend .reset := (reset.asBool \|\| !sio.sink_reset_n).asAsyncReset sink_valid .reset := reset.asAsyncReset source_valid_0.clock := clock source_valid_1.clock := clock sink_extend .clock := clock sink_valid .clock := clock source_valid_0.io.in := true.B source_valid_1.io.in := source_valid_0.io.out sio.widx_valid := source_valid_1.io.out sink_extend.io.in := sio.ridx_valid sink_valid.io.in := sink_extend.io.out sink_ready := sink_valid.io.out sio.source_reset_n := !reset.asBool // Assert that if there is stuff in the queue, then reset cannot happen // Impossible to write because dequeue can occur on the receiving side, // then reset allowed to happen, but write side cannot know that dequeue // occurred. // TODO: write some sort of sanity check assertion for users // that denote don't reset when there is activity // assert (!(reset \|\| !sio.sink_reset_n) \|\| !io.enq.valid, "Enqueue while sink is reset and AsyncQueueSource is unprotected") // assert (!reset_rise \|\| prev_idx_match.asBool, "Sink reset while AsyncQueueSource not empty") } } class AsyncQueueSink[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module { override def desiredName = s"AsyncQueueSink_${gen.typeName}" val io = IO(new Bundle { // These come from the sink domain val deq = Decoupled(gen) // These cross to the source clock domain val async = Flipped(new AsyncBundle(gen, params)) }) val bits = params.bits val source_ready = WireInit(true.B) val ridx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.deq.fire, !source_ready, "ridx_bin")) val widx = AsyncResetSynchronizerShiftReg(io.async.widx, params.sync, Some("widx_gray")) val valid = source_ready && ridx =/= widx // The mux is safe because timing analysis ensures ridx has reached the register // On an ASIC, changes to the unread location cannot affect the selected value // On an FPGA, only one input changes at a time => mem updates don't cause glitches // The register only latches when the selected valued is not being written val index = if (bits == 0) 0.U else ridx(bits-1, 0) ^ (ridx(bits, bits) << (bits-1)) io.async.index.foreach { _ := index } // This register does not NEED to be reset, as its contents will not // be considered unless the asynchronously reset deq valid register is set. // It is possible that bits latches when the source domain is reset / has power cut // This is safe, because isolation gates brought mem low before the zeroed widx reached us val deq_bits_nxt = io.async.mem(if (params.narrow) 0.U else index) io.deq.bits := ClockCrossingReg(deq_bits_nxt, en = valid, doInit = false, name = Some("deq_bits_reg")) val valid_reg = withReset(reset.asAsyncReset)(RegNext(next=valid, init=false.B).suggestName("valid_reg")) io.deq.valid := valid_reg && source_ready val ridx_reg = withReset(reset.asAsyncReset)(RegNext(next=ridx, init=0.U).suggestName("ridx_gray")) io.async.ridx := ridx_reg io.async.safe.foreach { sio => val sink_valid_0 = Module(new AsyncValidSync(params.sync, "sink_valid_0")) val sink_valid_1 = Module(new AsyncValidSync(params.sync, "sink_valid_1")) val source_extend = Module(new AsyncValidSync(params.sync, "source_extend")) val source_valid = Module(new AsyncValidSync(params.sync, "source_valid")) sink_valid_0 .reset := (reset.asBool \|\| !sio.source_reset_n).asAsyncReset sink_valid_1 .reset := (reset.asBool \|\| !sio.source_reset_n).asAsyncReset source_extend.reset := (reset.asBool \|\| !sio.source_reset_n).asAsyncReset source_valid .reset := reset.asAsyncReset sink_valid_0 .clock := clock sink_valid_1 .clock := clock source_extend.clock := clock source_valid .clock := clock sink_valid_0.io.in := true.B sink_valid_1.io.in := sink_valid_0.io.out sio.ridx_valid := sink_valid_1.io.out source_extend.io.in := sio.widx_valid source_valid.io.in := source_extend.io.out source_ready := source_valid.io.out sio.sink_reset_n := !reset.asBool // TODO: write some sort of sanity check assertion for users // that denote don't reset when there is activity // // val reset_and_extend = !source_ready \|\| !sio.source_reset_n \|\| reset.asBool // val reset_and_extend_prev = RegNext(reset_and_extend, true.B) // val reset_rise = !reset_and_extend_prev && reset_and_extend // val prev_idx_match = AsyncResetReg(updateData=(io.async.widx===io.async.ridx), resetData=0) // assert (!reset_rise \|\| prev_idx_match.asBool, "Source reset while AsyncQueueSink not empty") } } object FromAsyncBundle { // Sometimes it makes sense for the sink to have different sync than the source def apply[T <: Data](x: AsyncBundle[T]): DecoupledIO[T] = apply(x, x.params.sync) def apply[T <: Data](x: AsyncBundle[T], sync: Int): DecoupledIO[T] = { val sink = Module(new AsyncQueueSink(chiselTypeOf(x.mem(0)), x.params.copy(sync = sync))) sink.io.async <> x sink.io.deq } } object ToAsyncBundle { def apply[T <: Data](x: ReadyValidIO[T], params: AsyncQueueParams = AsyncQueueParams()): AsyncBundle[T] = { val source = Module(new AsyncQueueSource(chiselTypeOf(x.bits), params)) source.io.enq <> x source.io.async } } class AsyncQueue[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Crossing[T] { val io = IO(new CrossingIO(gen)) val source = withClockAndReset(io.enq_clock, io.enq_reset) { Module(new AsyncQueueSource(gen, params)) } val sink = withClockAndReset(io.deq_clock, io.deq_reset) { Module(new AsyncQueueSink (gen, params)) } source.io.enq <> io.enq io.deq <> sink.io.deq sink.io.async <> source.io.async }	module AsyncQueueSink_Phit( // @[AsyncQueue.scala:136:7] input clock, // @[AsyncQueue.scala:136:7] input reset, // @[AsyncQueue.scala:136:7] input io_deq_ready, // @[AsyncQueue.scala:139:14] output io_deq_valid, // @[AsyncQueue.scala:139:14] output [31:0] io_deq_bits_phit, // @[AsyncQueue.scala:139:14] input [31:0] io_async_mem_0_phit, // @[AsyncQueue.scala:139:14] input [31:0] io_async_mem_1_phit, // @[AsyncQueue.scala:139:14] input [31:0] io_async_mem_2_phit, // @[AsyncQueue.scala:139:14] input [31:0] io_async_mem_3_phit, // @[AsyncQueue.scala:139:14] input [31:0] io_async_mem_4_phit, // @[AsyncQueue.scala:139:14] input [31:0] io_async_mem_5_phit, // @[AsyncQueue.scala:139:14] input [31:0] io_async_mem_6_phit, // @[AsyncQueue.scala:139:14] input [31:0] io_async_mem_7_phit, // @[AsyncQueue.scala:139:14] output [3:0] io_async_ridx, // @[AsyncQueue.scala:139:14] input [3:0] io_async_widx, // @[AsyncQueue.scala:139:14] output io_async_safe_ridx_valid, // @[AsyncQueue.scala:139:14] input io_async_safe_widx_valid, // @[AsyncQueue.scala:139:14] input io_async_safe_source_reset_n, // @[AsyncQueue.scala:139:14] output io_async_safe_sink_reset_n // @[AsyncQueue.scala:139:14] ); wire _source_extend_io_out; // @[AsyncQueue.scala:175:31] wire _sink_valid_0_io_out; // @[AsyncQueue.scala:172:33] wire io_deq_ready_0 = io_deq_ready; // @[AsyncQueue.scala:136:7] wire [31:0] io_async_mem_0_phit_0 = io_async_mem_0_phit; // @[AsyncQueue.scala:136:7] wire [31:0] io_async_mem_1_phit_0 = io_async_mem_1_phit; // @[AsyncQueue.scala:136:7] wire [31:0] io_async_mem_2_phit_0 = io_async_mem_2_phit; // @[AsyncQueue.scala:136:7] wire [31:0] io_async_mem_3_phit_0 = io_async_mem_3_phit; // @[AsyncQueue.scala:136:7] wire [31:0] io_async_mem_4_phit_0 = io_async_mem_4_phit; // @[AsyncQueue.scala:136:7] wire [31:0] io_async_mem_5_phit_0 = io_async_mem_5_phit; // @[AsyncQueue.scala:136:7] wire [31:0] io_async_mem_6_phit_0 = io_async_mem_6_phit; // @[AsyncQueue.scala:136:7] wire [31:0] io_async_mem_7_phit_0 = io_async_mem_7_phit; // @[AsyncQueue.scala:136:7] wire [3:0] io_async_widx_0 = io_async_widx; // @[AsyncQueue.scala:136:7] wire io_async_safe_widx_valid_0 = io_async_safe_widx_valid; // @[AsyncQueue.scala:136:7] wire io_async_safe_source_reset_n_0 = io_async_safe_source_reset_n; // @[AsyncQueue.scala:136:7] wire _ridx_T = reset; // @[AsyncQueue.scala:148:30] wire _valid_reg_T = reset; // @[AsyncQueue.scala:165:35] wire _ridx_reg_T = reset; // @[AsyncQueue.scala:168:34] wire _sink_valid_0_reset_T = reset; // @[AsyncQueue.scala:177:35] wire _sink_valid_1_reset_T = reset; // @[AsyncQueue.scala:178:35] wire _source_extend_reset_T = reset; // @[AsyncQueue.scala:179:35] wire _source_valid_reset_T = reset; // @[AsyncQueue.scala:180:34] wire _io_async_safe_sink_reset_n_T = reset; // @[AsyncQueue.scala:193:32] wire _io_deq_valid_T; // @[AsyncQueue.scala:166:29] wire [31:0] _io_deq_bits_WIRE_phit; // @[SynchronizerReg.scala:211:26] wire _io_async_safe_sink_reset_n_T_1; // @[AsyncQueue.scala:193:25] wire [31:0] io_deq_bits_phit_0; // @[AsyncQueue.scala:136:7] wire io_deq_valid_0; // @[AsyncQueue.scala:136:7] wire io_async_safe_ridx_valid_0; // @[AsyncQueue.scala:136:7] wire io_async_safe_sink_reset_n_0; // @[AsyncQueue.scala:136:7] wire [3:0] io_async_ridx_0; // @[AsyncQueue.scala:136:7] wire source_ready; // @[AsyncQueue.scala:147:30] wire _ridx_T_1 = io_deq_ready_0 & io_deq_valid_0; // @[Decoupled.scala:51:35] wire _ridx_T_2 = ~source_ready; // @[AsyncQueue.scala:147:30, :148:77] wire [3:0] _ridx_incremented_T_2; // @[AsyncQueue.scala:53:23] wire [3:0] ridx_incremented; // @[AsyncQueue.scala:51:27] reg [3:0] ridx_ridx_bin; // @[AsyncQueue.scala:52:25] wire [4:0] _ridx_incremented_T = {1'h0, ridx_ridx_bin} + {4'h0, _ridx_T_1}; // @[Decoupled.scala:51:35] wire [3:0] _ridx_incremented_T_1 = _ridx_incremented_T[3:0]; // @[AsyncQueue.scala:53:43] assign _ridx_incremented_T_2 = _ridx_T_2 ? 4'h0 : _ridx_incremented_T_1; // @[AsyncQueue.scala:52:25, :53:{23,43}, :148:77] assign ridx_incremented = _ridx_incremented_T_2; // @[AsyncQueue.scala:51:27, :53:23] wire [2:0] _ridx_T_3 = ridx_incremented[3:1]; // @[AsyncQueue.scala:51:27, :54:32] wire [3:0] ridx = {ridx_incremented[3], ridx_incremented[2:0] ^ _ridx_T_3}; // @[AsyncQueue.scala:51:27, :54:{17,32}] wire [3:0] widx; // @[ShiftReg.scala:48:24] wire _valid_T = ridx != widx; // @[ShiftReg.scala:48:24] wire valid = source_ready & _valid_T; // @[AsyncQueue.scala:147:30, :150:{28,36}] wire [2:0] _index_T = ridx[2:0]; // @[AsyncQueue.scala:54:17, :156:43] wire _index_T_1 = ridx[3]; // @[AsyncQueue.scala:54:17, :156:62] wire [2:0] _index_T_2 = {_index_T_1, 2'h0}; // @[AsyncQueue.scala:156:{62,75}] wire [2:0] index = _index_T ^ _index_T_2; // @[AsyncQueue.scala:156:{43,55,75}] wire [7:0][31:0] _GEN = {{io_async_mem_7_phit_0}, {io_async_mem_6_phit_0}, {io_async_mem_5_phit_0}, {io_async_mem_4_phit_0}, {io_async_mem_3_phit_0}, {io_async_mem_2_phit_0}, {io_async_mem_1_phit_0}, {io_async_mem_0_phit_0}}; // @[SynchronizerReg.scala:209:18] wire [31:0] _io_deq_bits_T; // @[SynchronizerReg.scala:211:26] assign io_deq_bits_phit_0 = _io_deq_bits_WIRE_phit; // @[SynchronizerReg.scala:211:26] wire [31:0] _io_deq_bits_WIRE_1; // @[SynchronizerReg.scala:211:26] assign _io_deq_bits_T = _io_deq_bits_WIRE_1; // @[SynchronizerReg.scala:211:26] assign _io_deq_bits_WIRE_phit = _io_deq_bits_T; // @[SynchronizerReg.scala:211:26] reg valid_reg; // @[AsyncQueue.scala:165:56] assign _io_deq_valid_T = valid_reg & source_ready; // @[AsyncQueue.scala:147:30, :165:56, :166:29] assign io_deq_valid_0 = _io_deq_valid_T; // @[AsyncQueue.scala:136:7, :166:29] reg [3:0] ridx_gray; // @[AsyncQueue.scala:168:55] assign io_async_ridx_0 = ridx_gray; // @[AsyncQueue.scala:136:7, :168:55] wire _sink_valid_0_reset_T_1 = ~io_async_safe_source_reset_n_0; // @[AsyncQueue.scala:136:7, :177:45] wire _sink_valid_0_reset_T_2 = _sink_valid_0_reset_T \| _sink_valid_0_reset_T_1; // @[AsyncQueue.scala:177:{35,42,45}] wire _sink_valid_0_reset_T_3 = _sink_valid_0_reset_T_2; // @[AsyncQueue.scala:177:{42,66}] wire _sink_valid_1_reset_T_1 = ~io_async_safe_source_reset_n_0; // @[AsyncQueue.scala:136:7, :177:45, :178:45] wire _sink_valid_1_reset_T_2 = _sink_valid_1_reset_T \| _sink_valid_1_reset_T_1; // @[AsyncQueue.scala:178:{35,42,45}] wire _sink_valid_1_reset_T_3 = _sink_valid_1_reset_T_2; // @[AsyncQueue.scala:178:{42,66}] wire _source_extend_reset_T_1 = ~io_async_safe_source_reset_n_0; // @[AsyncQueue.scala:136:7, :177:45, :179:45] wire _source_extend_reset_T_2 = _source_extend_reset_T \| _source_extend_reset_T_1; // @[AsyncQueue.scala:179:{35,42,45}] wire _source_extend_reset_T_3 = _source_extend_reset_T_2; // @[AsyncQueue.scala:179:{42,66}] assign _io_async_safe_sink_reset_n_T_1 = ~_io_async_safe_sink_reset_n_T; // @[AsyncQueue.scala:193:{25,32}] assign io_async_safe_sink_reset_n_0 = _io_async_safe_sink_reset_n_T_1; // @[AsyncQueue.scala:136:7, :193:25] always @(posedge clock or posedge _ridx_T) begin // @[AsyncQueue.scala:136:7, :148:30] if (_ridx_T) // @[AsyncQueue.scala:136:7, :148:30] ridx_ridx_bin <= 4'h0; // @[AsyncQueue.scala:52:25] else // @[AsyncQueue.scala:136:7] ridx_ridx_bin <= ridx_incremented; // @[AsyncQueue.scala:51:27, :52:25] always @(posedge, posedge) always @(posedge clock or posedge _valid_reg_T) begin // @[AsyncQueue.scala:136:7, :165:35] if (_valid_reg_T) // @[AsyncQueue.scala:136:7, :165:35] valid_reg <= 1'h0; // @[AsyncQueue.scala:165:56] else // @[AsyncQueue.scala:136:7] valid_reg <= valid; // @[AsyncQueue.scala:150:28, :165:56] always @(posedge, posedge) always @(posedge clock or posedge _ridx_reg_T) begin // @[AsyncQueue.scala:136:7, :168:34] if (_ridx_reg_T) // @[AsyncQueue.scala:136:7, :168:34] ridx_gray <= 4'h0; // @[AsyncQueue.scala:52:25, :168:55] else // @[AsyncQueue.scala:136:7] ridx_gray <= ridx; // @[AsyncQueue.scala:54:17, :168:55] always @(posedge, posedge)
Generate the Verilog code corresponding to the following Chisel files. File Nodes.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.nodes._ import freechips.rocketchip.util.{AsyncQueueParams,RationalDirection} case object TLMonitorBuilder extends Field[TLMonitorArgs => TLMonitorBase](args => new TLMonitor(args)) object TLImp extends NodeImp[TLMasterPortParameters, TLSlavePortParameters, TLEdgeOut, TLEdgeIn, TLBundle] { def edgeO(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeOut(pd, pu, p, sourceInfo) def edgeI(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeIn (pd, pu, p, sourceInfo) def bundleO(eo: TLEdgeOut) = TLBundle(eo.bundle) def bundleI(ei: TLEdgeIn) = TLBundle(ei.bundle) def render(ei: TLEdgeIn) = RenderedEdge(colour = "#000000" /* black /, label = (ei.manager.beatBytes 8).toString) override def monitor(bundle: TLBundle, edge: TLEdgeIn): Unit = { val monitor = Module(edge.params(TLMonitorBuilder)(TLMonitorArgs(edge))) monitor.io.in := bundle } override def mixO(pd: TLMasterPortParameters, node: OutwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLMasterPortParameters = pd.v1copy(clients = pd.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }) override def mixI(pu: TLSlavePortParameters, node: InwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLSlavePortParameters = pu.v1copy(managers = pu.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }) } trait TLFormatNode extends FormatNode[TLEdgeIn, TLEdgeOut] case class TLClientNode(portParams: Seq[TLMasterPortParameters])(implicit valName: ValName) extends SourceNode(TLImp)(portParams) with TLFormatNode case class TLManagerNode(portParams: Seq[TLSlavePortParameters])(implicit valName: ValName) extends SinkNode(TLImp)(portParams) with TLFormatNode case class TLAdapterNode( clientFn: TLMasterPortParameters => TLMasterPortParameters = { s => s }, managerFn: TLSlavePortParameters => TLSlavePortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLImp)(clientFn, managerFn) with TLFormatNode case class TLJunctionNode( clientFn: Seq[TLMasterPortParameters] => Seq[TLMasterPortParameters], managerFn: Seq[TLSlavePortParameters] => Seq[TLSlavePortParameters])( implicit valName: ValName) extends JunctionNode(TLImp)(clientFn, managerFn) with TLFormatNode case class TLIdentityNode()(implicit valName: ValName) extends IdentityNode(TLImp)() with TLFormatNode object TLNameNode { def apply(name: ValName) = TLIdentityNode()(name) def apply(name: Option[String]): TLIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLIdentityNode = apply(Some(name)) } case class TLEphemeralNode()(implicit valName: ValName) extends EphemeralNode(TLImp)() object TLTempNode { def apply(): TLEphemeralNode = TLEphemeralNode()(ValName("temp")) } case class TLNexusNode( clientFn: Seq[TLMasterPortParameters] => TLMasterPortParameters, managerFn: Seq[TLSlavePortParameters] => TLSlavePortParameters)( implicit valName: ValName) extends NexusNode(TLImp)(clientFn, managerFn) with TLFormatNode abstract class TLCustomNode(implicit valName: ValName) extends CustomNode(TLImp) with TLFormatNode // Asynchronous crossings trait TLAsyncFormatNode extends FormatNode[TLAsyncEdgeParameters, TLAsyncEdgeParameters] object TLAsyncImp extends SimpleNodeImp[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncEdgeParameters, TLAsyncBundle] { def edge(pd: TLAsyncClientPortParameters, pu: TLAsyncManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLAsyncEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLAsyncEdgeParameters) = new TLAsyncBundle(e.bundle) def render(e: TLAsyncEdgeParameters) = RenderedEdge(colour = "#ff0000" /* red /, label = e.manager.async.depth.toString) override def mixO(pd: TLAsyncClientPortParameters, node: OutwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLAsyncManagerPortParameters, node: InwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLAsyncAdapterNode( clientFn: TLAsyncClientPortParameters => TLAsyncClientPortParameters = { s => s }, managerFn: TLAsyncManagerPortParameters => TLAsyncManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLAsyncImp)(clientFn, managerFn) with TLAsyncFormatNode case class TLAsyncIdentityNode()(implicit valName: ValName) extends IdentityNode(TLAsyncImp)() with TLAsyncFormatNode object TLAsyncNameNode { def apply(name: ValName) = TLAsyncIdentityNode()(name) def apply(name: Option[String]): TLAsyncIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLAsyncIdentityNode = apply(Some(name)) } case class TLAsyncSourceNode(sync: Option[Int])(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLAsyncImp)( dFn = { p => TLAsyncClientPortParameters(p) }, uFn = { p => p.base.v1copy(minLatency = p.base.minLatency + sync.getOrElse(p.async.sync)) }) with FormatNode[TLEdgeIn, TLAsyncEdgeParameters] // discard cycles in other clock domain case class TLAsyncSinkNode(async: AsyncQueueParams)(implicit valName: ValName) extends MixedAdapterNode(TLAsyncImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = p.base.minLatency + async.sync) }, uFn = { p => TLAsyncManagerPortParameters(async, p) }) with FormatNode[TLAsyncEdgeParameters, TLEdgeOut] // Rationally related crossings trait TLRationalFormatNode extends FormatNode[TLRationalEdgeParameters, TLRationalEdgeParameters] object TLRationalImp extends SimpleNodeImp[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalEdgeParameters, TLRationalBundle] { def edge(pd: TLRationalClientPortParameters, pu: TLRationalManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLRationalEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLRationalEdgeParameters) = new TLRationalBundle(e.bundle) def render(e: TLRationalEdgeParameters) = RenderedEdge(colour = "#00ff00" / green /) override def mixO(pd: TLRationalClientPortParameters, node: OutwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLRationalManagerPortParameters, node: InwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLRationalAdapterNode( clientFn: TLRationalClientPortParameters => TLRationalClientPortParameters = { s => s }, managerFn: TLRationalManagerPortParameters => TLRationalManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLRationalImp)(clientFn, managerFn) with TLRationalFormatNode case class TLRationalIdentityNode()(implicit valName: ValName) extends IdentityNode(TLRationalImp)() with TLRationalFormatNode object TLRationalNameNode { def apply(name: ValName) = TLRationalIdentityNode()(name) def apply(name: Option[String]): TLRationalIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLRationalIdentityNode = apply(Some(name)) } case class TLRationalSourceNode()(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLRationalImp)( dFn = { p => TLRationalClientPortParameters(p) }, uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLRationalEdgeParameters] // discard cycles from other clock domain case class TLRationalSinkNode(direction: RationalDirection)(implicit valName: ValName) extends MixedAdapterNode(TLRationalImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = 1) }, uFn = { p => TLRationalManagerPortParameters(direction, p) }) with FormatNode[TLRationalEdgeParameters, TLEdgeOut] // Credited version of TileLink channels trait TLCreditedFormatNode extends FormatNode[TLCreditedEdgeParameters, TLCreditedEdgeParameters] object TLCreditedImp extends SimpleNodeImp[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedEdgeParameters, TLCreditedBundle] { def edge(pd: TLCreditedClientPortParameters, pu: TLCreditedManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLCreditedEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLCreditedEdgeParameters) = new TLCreditedBundle(e.bundle) def render(e: TLCreditedEdgeParameters) = RenderedEdge(colour = "#ffff00" / yellow /, e.delay.toString) override def mixO(pd: TLCreditedClientPortParameters, node: OutwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLCreditedManagerPortParameters, node: InwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLCreditedAdapterNode( clientFn: TLCreditedClientPortParameters => TLCreditedClientPortParameters = { s => s }, managerFn: TLCreditedManagerPortParameters => TLCreditedManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLCreditedImp)(clientFn, managerFn) with TLCreditedFormatNode case class TLCreditedIdentityNode()(implicit valName: ValName) extends IdentityNode(TLCreditedImp)() with TLCreditedFormatNode object TLCreditedNameNode { def apply(name: ValName) = TLCreditedIdentityNode()(name) def apply(name: Option[String]): TLCreditedIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLCreditedIdentityNode = apply(Some(name)) } case class TLCreditedSourceNode(delay: TLCreditedDelay)(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLCreditedImp)( dFn = { p => TLCreditedClientPortParameters(delay, p) }, uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLCreditedEdgeParameters] // discard cycles from other clock domain case class TLCreditedSinkNode(delay: TLCreditedDelay)(implicit valName: ValName) extends MixedAdapterNode(TLCreditedImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = 1) }, uFn = { p => TLCreditedManagerPortParameters(delay, p) }) with FormatNode[TLCreditedEdgeParameters, TLEdgeOut] File RegisterRouter.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.nodes._ import freechips.rocketchip.diplomacy.{AddressSet, TransferSizes} import freechips.rocketchip.resources.{Device, Resource, ResourceBindings} import freechips.rocketchip.prci.{NoCrossing} import freechips.rocketchip.regmapper.{RegField, RegMapper, RegMapperParams, RegMapperInput, RegisterRouter} import freechips.rocketchip.util.{BundleField, ControlKey, ElaborationArtefacts, GenRegDescsAnno} import scala.math.min class TLRegisterRouterExtraBundle(val sourceBits: Int, val sizeBits: Int) extends Bundle { val source = UInt((sourceBits max 1).W) val size = UInt((sizeBits max 1).W) } case object TLRegisterRouterExtra extends ControlKey[TLRegisterRouterExtraBundle]("tlrr_extra") case class TLRegisterRouterExtraField(sourceBits: Int, sizeBits: Int) extends BundleField[TLRegisterRouterExtraBundle](TLRegisterRouterExtra, Output(new TLRegisterRouterExtraBundle(sourceBits, sizeBits)), x => { x.size := 0.U x.source := 0.U }) /* TLRegisterNode is a specialized TL SinkNode that encapsulates MMIO registers. * It provides functionality for describing and outputting metdata about the registers in several formats. * It also provides a concrete implementation of a regmap function that will be used * to wire a map of internal registers associated with this node to the node's interconnect port. / case class TLRegisterNode( address: Seq[AddressSet], device: Device, deviceKey: String = "reg/control", concurrency: Int = 0, beatBytes: Int = 4, undefZero: Boolean = true, executable: Boolean = false)( implicit valName: ValName) extends SinkNode(TLImp)(Seq(TLSlavePortParameters.v1( Seq(TLSlaveParameters.v1( address = address, resources = Seq(Resource(device, deviceKey)), executable = executable, supportsGet = TransferSizes(1, beatBytes), supportsPutPartial = TransferSizes(1, beatBytes), supportsPutFull = TransferSizes(1, beatBytes), fifoId = Some(0))), // requests are handled in order beatBytes = beatBytes, minLatency = min(concurrency, 1)))) with TLFormatNode // the Queue adds at most one cycle { val size = 1 << log2Ceil(1 + address.map(_.max).max - address.map(_.base).min) require (size >= beatBytes) address.foreach { case a => require (a.widen(size-1).base == address.head.widen(size-1).base, s"TLRegisterNode addresses (${address}) must be aligned to its size ${size}") } // Calling this method causes the matching TL2 bundle to be // configured to route all requests to the listed RegFields. def regmap(mapping: RegField.Map) = { val (bundleIn, edge) = this.in(0) val a = bundleIn.a val d = bundleIn.d val fields = TLRegisterRouterExtraField(edge.bundle.sourceBits, edge.bundle.sizeBits) +: a.bits.params.echoFields val params = RegMapperParams(log2Up(size/beatBytes), beatBytes, fields) val in = Wire(Decoupled(new RegMapperInput(params))) in.bits.read := a.bits.opcode === TLMessages.Get in.bits.index := edge.addr_hi(a.bits) in.bits.data := a.bits.data in.bits.mask := a.bits.mask Connectable.waiveUnmatched(in.bits.extra, a.bits.echo) match { case (lhs, rhs) => lhs :<= rhs } val a_extra = in.bits.extra(TLRegisterRouterExtra) a_extra.source := a.bits.source a_extra.size := a.bits.size // Invoke the register map builder val out = RegMapper(beatBytes, concurrency, undefZero, in, mapping:_) // No flow control needed in.valid := a.valid a.ready := in.ready d.valid := out.valid out.ready := d.ready // We must restore the size to enable width adapters to work val d_extra = out.bits.extra(TLRegisterRouterExtra) d.bits := edge.AccessAck(toSource = d_extra.source, lgSize = d_extra.size) // avoid a Mux on the data bus by manually overriding two fields d.bits.data := out.bits.data Connectable.waiveUnmatched(d.bits.echo, out.bits.extra) match { case (lhs, rhs) => lhs :<= rhs } d.bits.opcode := Mux(out.bits.read, TLMessages.AccessAckData, TLMessages.AccessAck) // Tie off unused channels bundleIn.b.valid := false.B bundleIn.c.ready := true.B bundleIn.e.ready := true.B genRegDescsJson(mapping:_) } def genRegDescsJson(mapping: RegField.Map): Unit = { // Dump out the register map for documentation purposes. val base = address.head.base val baseHex = s"0x${base.toInt.toHexString}" val name = s"${device.describe(ResourceBindings()).name}.At${baseHex}" val json = GenRegDescsAnno.serialize(base, name, mapping:_) var suffix = 0 while( ElaborationArtefacts.contains(s"${baseHex}.${suffix}.regmap.json")) { suffix = suffix + 1 } ElaborationArtefacts.add(s"${baseHex}.${suffix}.regmap.json", json) val module = Module.currentModule.get.asInstanceOf[RawModule] GenRegDescsAnno.anno( module, base, mapping:_) } } /* Mix HasTLControlRegMap into any subclass of RegisterRouter to gain helper functions for attaching a device control register map to TileLink. * - The intended use case is that controlNode will diplomatically publish a SW-visible device's memory-mapped control registers. * - Use the clock crossing helper controlXing to externally connect controlNode to a TileLink interconnect. * - Use the mapping helper function regmap to internally fill out the space of device control registers. / trait HasTLControlRegMap { this: RegisterRouter => protected val controlNode = TLRegisterNode( address = address, device = device, deviceKey = "reg/control", concurrency = concurrency, beatBytes = beatBytes, undefZero = undefZero, executable = executable) // Externally, this helper should be used to connect the register control port to a bus val controlXing: TLInwardClockCrossingHelper = this.crossIn(controlNode) // Backwards-compatibility default node accessor with no clock crossing lazy val node: TLInwardNode = controlXing(NoCrossing) // Internally, this function should be used to populate the control port with registers protected def regmap(mapping: RegField.Map): Unit = { controlNode.regmap(mapping:_) } } File TileResetSetter.scala: package chipyard.clocking import chisel3._ import chisel3.util._ import chisel3.experimental.Analog import org.chipsalliance.cde.config._ import freechips.rocketchip.subsystem._ import freechips.rocketchip.diplomacy._ import freechips.rocketchip.prci._ import freechips.rocketchip.util._ import freechips.rocketchip.tilelink._ import freechips.rocketchip.devices.tilelink._ import freechips.rocketchip.regmapper._ import freechips.rocketchip.subsystem._ // Currently only works if all tiles are already driven by independent clock groups // TODO: After https://github.com/chipsalliance/rocket-chip/pull/2842 is merged, we should // always put all tiles on independent clock groups class TileResetSetter(address: BigInt, beatBytes: Int, tileNames: Seq[String], initResetHarts: Seq[Int])(implicit p: Parameters) extends LazyModule { val device = new SimpleDevice("tile-reset-setter", Nil) val tlNode = TLRegisterNode(Seq(AddressSet(address, 4096-1)), device, "reg/control", beatBytes=beatBytes) val clockNode = ClockGroupIdentityNode() lazy val module = new LazyModuleImp(this) { val nTiles = p(TilesLocated(InSubsystem)).size require (nTiles <= 4096 / 4) val tile_async_resets = Wire(Vec(nTiles, Reset())) val r_tile_resets = (0 until nTiles).map({ i => tile_async_resets(i) := true.B.asAsyncReset // Remove this line after https://github.com/chipsalliance/rocket-chip/pull/2842 withReset (tile_async_resets(i)) { Module(new AsyncResetRegVec(w=1, init=(if (initResetHarts.contains(i)) 1 else 0))) } }) if (nTiles > 0) tlNode.regmap((0 until nTiles).map({ i => i 4 -> Seq(RegField.rwReg(1, r_tile_resets(i).io)) }): _) val tileMap = tileNames.zipWithIndex.map({ case (n, i) => n -> (tile_async_resets(i), r_tile_resets(i).io.q, address + i 4) }) (clockNode.out zip clockNode.in).map { case ((o, _), (i, _)) => (o.member.elements zip i.member.elements).foreach { case ((name, oD), (_, iD)) => oD.clock := iD.clock oD.reset := iD.reset for ((n, (rIn, rOut, addr)) <- tileMap) { if (name.contains(n)) { println(s"${addr.toString(16)}: Tile $name reset control") // Async because the reset coming out of the AsyncResetRegVec is // clocked to the bus this is attached to, not the clock in this // clock bundle. We expect a ClockGroupResetSynchronizer downstream // to synchronize the resets // Also, this or enforces that the tiles come out of reset after the reset of the system oD.reset := (rOut.asBool \|\| iD.reset.asBool).asAsyncReset rIn := iD.reset } } } } } } File MuxLiteral.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util.log2Ceil import scala.reflect.ClassTag /* MuxLiteral creates a lookup table from a key to a list of values. * Unlike MuxLookup, the table keys must be exclusive literals. / object MuxLiteral { def apply[T <: Data:ClassTag](index: UInt, default: T, first: (UInt, T), rest: (UInt, T)): T = apply(index, default, first :: rest.toList) def apply[T <: Data:ClassTag](index: UInt, default: T, cases: Seq[(UInt, T)]): T = MuxTable(index, default, cases.map { case (k, v) => (k.litValue, v) }) } object MuxSeq { def apply[T <: Data:ClassTag](index: UInt, default: T, first: T, rest: T): T = apply(index, default, first :: rest.toList) def apply[T <: Data:ClassTag](index: UInt, default: T, cases: Seq[T]): T = MuxTable(index, default, cases.zipWithIndex.map { case (v, i) => (BigInt(i), v) }) } object MuxTable { def apply[T <: Data:ClassTag](index: UInt, default: T, first: (BigInt, T), rest: (BigInt, T)): T = apply(index, default, first :: rest.toList) def apply[T <: Data:ClassTag](index: UInt, default: T, cases: Seq[(BigInt, T)]): T = { /* All keys must be >= 0 and distinct / cases.foreach { case (k, _) => require (k >= 0) } require (cases.map(_._1).distinct.size == cases.size) / Filter out any cases identical to the default / val simple = cases.filter { case (k, v) => !default.isLit \|\| !v.isLit \|\| v.litValue != default.litValue } val maxKey = (BigInt(0) +: simple.map(_._1)).max val endIndex = BigInt(1) << log2Ceil(maxKey+1) if (simple.isEmpty) { default } else if (endIndex <= 2simple.size) { /* The dense encoding case uses a Vec / val table = Array.fill(endIndex.toInt) { default } simple.foreach { case (k, v) => table(k.toInt) = v } Mux(index >= endIndex.U, default, VecInit(table)(index)) } else { / The sparse encoding case uses switch / val out = WireDefault(default) simple.foldLeft(new chisel3.util.SwitchContext(index, None, Set.empty)) { case (acc, (k, v)) => acc.is (k.U) { out := v } } out } } } File LazyModuleImp.scala: package org.chipsalliance.diplomacy.lazymodule import chisel3.{withClockAndReset, Module, RawModule, Reset, _} import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo} import firrtl.passes.InlineAnnotation import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.nodes.Dangle import scala.collection.immutable.SortedMap /* Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]]. * * This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy. / sealed trait LazyModuleImpLike extends RawModule { /* [[LazyModule]] that contains this instance. / val wrapper: LazyModule /* IOs that will be automatically "punched" for this instance. / val auto: AutoBundle /* The metadata that describes the [[HalfEdge]]s which generated [[auto]]. / protected[diplomacy] val dangles: Seq[Dangle] // [[wrapper.module]] had better not be accessed while LazyModules are still being built! require( LazyModule.scope.isEmpty, s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}" ) /* Set module name. Defaults to the containing LazyModule's desiredName. / override def desiredName: String = wrapper.desiredName suggestName(wrapper.suggestedName) /* [[Parameters]] for chisel [[Module]]s. / implicit val p: Parameters = wrapper.p /* instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and * submodules. / protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = { // 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]], // 2. return [[Dangle]]s from each module. val childDangles = wrapper.children.reverse.flatMap { c => implicit val sourceInfo: SourceInfo = c.info c.cloneProto.map { cp => // If the child is a clone, then recursively set cloneProto of its children as well def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = { require(bases.size == clones.size) (bases.zip(clones)).map { case (l, r) => require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}") l.cloneProto = Some(r) assignCloneProtos(l.children, r.children) } } assignCloneProtos(c.children, cp.children) // Clone the child module as a record, and get its [[AutoBundle]] val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName) val clonedAuto = clone("auto").asInstanceOf[AutoBundle] // Get the empty [[Dangle]]'s of the cloned child val rawDangles = c.cloneDangles() require(rawDangles.size == clonedAuto.elements.size) // Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) } dangles }.getOrElse { // For non-clones, instantiate the child module val mod = try { Module(c.module) } catch { case e: ChiselException => { println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}") throw e } } mod.dangles } } // Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]]. // This will result in a sequence of [[Dangle]] from these [[BaseNode]]s. val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate()) // Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]] val allDangles = nodeDangles ++ childDangles // Group [[allDangles]] by their [[source]]. val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _) // For each [[source]] set of [[Dangle]]s of size 2, ensure that these // can be connected as a source-sink pair (have opposite flipped value). // Make the connection and mark them as [[done]]. val done = Set() ++ pairing.values.filter(_.size == 2).map { case Seq(a, b) => require(a.flipped != b.flipped) // @todo <> in chisel3 makes directionless connection. if (a.flipped) { a.data <> b.data } else { b.data <> a.data } a.source case _ => None } // Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module. val forward = allDangles.filter(d => !done(d.source)) // Generate [[AutoBundle]] IO from [[forward]]. val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _)) // Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]] val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) => if (d.flipped) { d.data <> io } else { io <> d.data } d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name) } // Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]]. wrapper.inModuleBody.reverse.foreach { _() } if (wrapper.shouldBeInlined) { chisel3.experimental.annotate(new ChiselAnnotation { def toFirrtl = InlineAnnotation(toNamed) }) } // Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]]. (auto, dangles) } } /* Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. / class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike { /* Instantiate hardware of this `Module`. / val (auto, dangles) = instantiate() } /* Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. / class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike { // These wires are the default clock+reset for all LazyModule children. // It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the // [[LazyRawModuleImp]] children. // Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly. /* drive clock explicitly. / val childClock: Clock = Wire(Clock()) /* drive reset explicitly. / val childReset: Reset = Wire(Reset()) // the default is that these are disabled childClock := false.B.asClock childReset := chisel3.DontCare def provideImplicitClockToLazyChildren: Boolean = false val (auto, dangles) = if (provideImplicitClockToLazyChildren) { withClockAndReset(childClock, childReset) { instantiate() } } else { instantiate() } } File MixedNode.scala: package org.chipsalliance.diplomacy.nodes import chisel3.{Data, DontCare, Wire} import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.{Field, Parameters} import org.chipsalliance.diplomacy.ValName import org.chipsalliance.diplomacy.sourceLine /* One side metadata of a [[Dangle]]. * * Describes one side of an edge going into or out of a [[BaseNode]]. * * @param serial * the global [[BaseNode.serial]] number of the [[BaseNode]] that this [[HalfEdge]] connects to. * @param index * the `index` in the [[BaseNode]]'s input or output port list that this [[HalfEdge]] belongs to. / case class HalfEdge(serial: Int, index: Int) extends Ordered[HalfEdge] { import scala.math.Ordered.orderingToOrdered def compare(that: HalfEdge): Int = HalfEdge.unapply(this).compare(HalfEdge.unapply(that)) } /* [[Dangle]] captures the `IO` information of a [[LazyModule]] and which two [[BaseNode]]s the [[Edges]]/[[Bundle]] * connects. * * [[Dangle]]s are generated by [[BaseNode.instantiate]] using [[MixedNode.danglesOut]] and [[MixedNode.danglesIn]] , * [[LazyModuleImp.instantiate]] connects those that go to internal or explicit IO connections in a [[LazyModule]]. * * @param source * the source [[HalfEdge]] of this [[Dangle]], which captures the source [[BaseNode]] and the port `index` within * that [[BaseNode]]. * @param sink * sink [[HalfEdge]] of this [[Dangle]], which captures the sink [[BaseNode]] and the port `index` within that * [[BaseNode]]. * @param flipped * flip or not in [[AutoBundle.makeElements]]. If true this corresponds to `danglesOut`, if false it corresponds to * `danglesIn`. * @param dataOpt * actual [[Data]] for the hardware connection. Can be empty if this belongs to a cloned module / case class Dangle(source: HalfEdge, sink: HalfEdge, flipped: Boolean, name: String, dataOpt: Option[Data]) { def data = dataOpt.get } /* [[Edges]] is a collection of parameters describing the functionality and connection for an interface, which is often * derived from the interconnection protocol and can inform the parameterization of the hardware bundles that actually * implement the protocol. / case class Edges[EI, EO](in: Seq[EI], out: Seq[EO]) /* A field available in [[Parameters]] used to determine whether [[InwardNodeImp.monitor]] will be called. / case object MonitorsEnabled extends Field[Boolean](true) /* When rendering the edge in a graphical format, flip the order in which the edges' source and sink are presented. * * For example, when rendering graphML, yEd by default tries to put the source node vertically above the sink node, but * [[RenderFlipped]] inverts this relationship. When a particular [[LazyModule]] contains both source nodes and sink * nodes, flipping the rendering of one node's edge will usual produce a more concise visual layout for the * [[LazyModule]]. / case object RenderFlipped extends Field[Boolean](false) /* The sealed node class in the package, all node are derived from it. * * @param inner * Sink interface implementation. * @param outer * Source interface implementation. * @param valName * val name of this node. * @tparam DI * Downward-flowing parameters received on the inner side of the node. It is usually a brunch of parameters * describing the protocol parameters from a source. For an [[InwardNode]], it is determined by the connected * [[OutwardNode]]. Since it can be connected to multiple sources, this parameter is always a Seq of source port * parameters. * @tparam UI * Upward-flowing parameters generated by the inner side of the node. It is usually a brunch of parameters describing * the protocol parameters of a sink. For an [[InwardNode]], it is determined itself. * @tparam EI * Edge Parameters describing a connection on the inner side of the node. It is usually a brunch of transfers * specified for a sink according to protocol. * @tparam BI * Bundle type used when connecting to the inner side of the node. It is a hardware interface of this sink interface. * It should extends from [[chisel3.Data]], which represents the real hardware. * @tparam DO * Downward-flowing parameters generated on the outer side of the node. It is usually a brunch of parameters * describing the protocol parameters of a source. For an [[OutwardNode]], it is determined itself. * @tparam UO * Upward-flowing parameters received by the outer side of the node. It is usually a brunch of parameters describing * the protocol parameters from a sink. For an [[OutwardNode]], it is determined by the connected [[InwardNode]]. * Since it can be connected to multiple sinks, this parameter is always a Seq of sink port parameters. * @tparam EO * Edge Parameters describing a connection on the outer side of the node. It is usually a brunch of transfers * specified for a source according to protocol. * @tparam BO * Bundle type used when connecting to the outer side of the node. It is a hardware interface of this source * interface. It should extends from [[chisel3.Data]], which represents the real hardware. * * @note * Call Graph of [[MixedNode]] * - line `─`: source is process by a function and generate pass to others * - Arrow `→`: target of arrow is generated by source * * {{{ * (from the other node) * ┌─────────────────────────────────────────────────────────[[InwardNode.uiParams]]─────────────┐ * ↓ │ * (binding node when elaboration) [[OutwardNode.uoParams]]────────────────────────[[MixedNode.mapParamsU]]→──────────┐ │ * [[InwardNode.accPI]] │ │ │ * │ │ (based on protocol) │ * │ │ [[MixedNode.inner.edgeI]] │ * │ │ ↓ │ * ↓ │ │ │ * (immobilize after elaboration) (inward port from [[OutwardNode]]) │ ↓ │ * [[InwardNode.iBindings]]──┐ [[MixedNode.iDirectPorts]]────────────────────→[[MixedNode.iPorts]] [[InwardNode.uiParams]] │ * │ │ ↑ │ │ │ * │ │ │ [[OutwardNode.doParams]] │ │ * │ │ │ (from the other node) │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * │ │ │ └────────┬──────────────┤ │ * │ │ │ │ │ │ * │ │ │ │ (based on protocol) │ * │ │ │ │ [[MixedNode.inner.edgeI]] │ * │ │ │ │ │ │ * │ │ (from the other node) │ ↓ │ * │ └───[[OutwardNode.oPortMapping]] [[OutwardNode.oStar]] │ [[MixedNode.edgesIn]]───┐ │ * │ ↑ ↑ │ │ ↓ │ * │ │ │ │ │ [[MixedNode.in]] │ * │ │ │ │ ↓ ↑ │ * │ (solve star connection) │ │ │ [[MixedNode.bundleIn]]──┘ │ * ├───[[MixedNode.resolveStar]]→─┼─────────────────────────────┤ └────────────────────────────────────┐ │ * │ │ │ [[MixedNode.bundleOut]]─┐ │ │ * │ │ │ ↑ ↓ │ │ * │ │ │ │ [[MixedNode.out]] │ │ * │ ↓ ↓ │ ↑ │ │ * │ ┌─────[[InwardNode.iPortMapping]] [[InwardNode.iStar]] [[MixedNode.edgesOut]]──┘ │ │ * │ │ (from the other node) ↑ │ │ * │ │ │ │ │ │ * │ │ │ [[MixedNode.outer.edgeO]] │ │ * │ │ │ (based on protocol) │ │ * │ │ │ │ │ │ * │ │ │ ┌────────────────────────────────────────┤ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * (immobilize after elaboration)│ ↓ │ │ │ │ * [[OutwardNode.oBindings]]─┘ [[MixedNode.oDirectPorts]]───→[[MixedNode.oPorts]] [[OutwardNode.doParams]] │ │ * ↑ (inward port from [[OutwardNode]]) │ │ │ │ * │ ┌─────────────────────────────────────────┤ │ │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * [[OutwardNode.accPO]] │ ↓ │ │ │ * (binding node when elaboration) │ [[InwardNode.diParams]]─────→[[MixedNode.mapParamsD]]────────────────────────────┘ │ │ * │ ↑ │ │ * │ └──────────────────────────────────────────────────────────────────────────────────────────┘ │ * └──────────────────────────────────────────────────────────────────────────────────────────────────────────┘ * }}} / abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data]( val inner: InwardNodeImp[DI, UI, EI, BI], val outer: OutwardNodeImp[DO, UO, EO, BO] )( implicit valName: ValName) extends BaseNode with NodeHandle[DI, UI, EI, BI, DO, UO, EO, BO] with InwardNode[DI, UI, BI] with OutwardNode[DO, UO, BO] { // Generate a [[NodeHandle]] with inward and outward node are both this node. val inward = this val outward = this /* Debug info of nodes binding. / def bindingInfo: String = s"""$iBindingInfo \|$oBindingInfo \|""".stripMargin /* Debug info of ports connecting. / def connectedPortsInfo: String = s"""${oPorts.size} outward ports connected: [${oPorts.map(_._2.name).mkString(",")}] \|${iPorts.size} inward ports connected: [${iPorts.map(_._2.name).mkString(",")}] \|""".stripMargin /* Debug info of parameters propagations. / def parametersInfo: String = s"""${doParams.size} downstream outward parameters: [${doParams.mkString(",")}] \|${uoParams.size} upstream outward parameters: [${uoParams.mkString(",")}] \|${diParams.size} downstream inward parameters: [${diParams.mkString(",")}] \|${uiParams.size} upstream inward parameters: [${uiParams.mkString(",")}] \|""".stripMargin /* For a given node, converts [[OutwardNode.accPO]] and [[InwardNode.accPI]] to [[MixedNode.oPortMapping]] and * [[MixedNode.iPortMapping]]. * * Given counts of known inward and outward binding and inward and outward star bindings, return the resolved inward * stars and outward stars. * * This method will also validate the arguments and throw a runtime error if the values are unsuitable for this type * of node. * * @param iKnown * Number of known-size ([[BIND_ONCE]]) input bindings. * @param oKnown * Number of known-size ([[BIND_ONCE]]) output bindings. * @param iStar * Number of unknown size ([[BIND_STAR]]) input bindings. * @param oStar * Number of unknown size ([[BIND_STAR]]) output bindings. * @return * A Tuple of the resolved number of input and output connections. / protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStar: Int, oStar: Int): (Int, Int) /* Function to generate downward-flowing outward params from the downward-flowing input params and the current output * ports. * * @param n * The size of the output sequence to generate. * @param p * Sequence of downward-flowing input parameters of this node. * @return * A `n`-sized sequence of downward-flowing output edge parameters. / protected[diplomacy] def mapParamsD(n: Int, p: Seq[DI]): Seq[DO] /* Function to generate upward-flowing input parameters from the upward-flowing output parameters [[uiParams]]. * * @param n * Size of the output sequence. * @param p * Upward-flowing output edge parameters. * @return * A n-sized sequence of upward-flowing input edge parameters. / protected[diplomacy] def mapParamsU(n: Int, p: Seq[UO]): Seq[UI] /* @return * The sink cardinality of the node, the number of outputs bound with [[BIND_QUERY]] summed with inputs bound with * [[BIND_STAR]]. / protected[diplomacy] lazy val sinkCard: Int = oBindings.count(_._3 == BIND_QUERY) + iBindings.count(_._3 == BIND_STAR) /* @return * The source cardinality of this node, the number of inputs bound with [[BIND_QUERY]] summed with the number of * output bindings bound with [[BIND_STAR]]. / protected[diplomacy] lazy val sourceCard: Int = iBindings.count(_._3 == BIND_QUERY) + oBindings.count(_._3 == BIND_STAR) /* @return list of nodes involved in flex bindings with this node. / protected[diplomacy] lazy val flexes: Seq[BaseNode] = oBindings.filter(_._3 == BIND_FLEX).map(_._2) ++ iBindings.filter(_._3 == BIND_FLEX).map(_._2) /* Resolves the flex to be either source or sink and returns the offset where the [[BIND_STAR]] operators begin * greedily taking up the remaining connections. * * @return * A value >= 0 if it is sink cardinality, a negative value for source cardinality. The magnitude of the return * value is not relevant. / protected[diplomacy] lazy val flexOffset: Int = { /* Recursively performs a depth-first search of the [[flexes]], [[BaseNode]]s connected to this node with flex * operators. The algorithm bottoms out when we either get to a node we have already visited or when we get to a * connection that is not a flex and can set the direction for us. Otherwise, recurse by visiting the `flexes` of * each node in the current set and decide whether they should be added to the set or not. * * @return * the mapping of [[BaseNode]] indexed by their serial numbers. / def DFS(v: BaseNode, visited: Map[Int, BaseNode]): Map[Int, BaseNode] = { if (visited.contains(v.serial) \|\| !v.flexibleArityDirection) { visited } else { v.flexes.foldLeft(visited + (v.serial -> v))((sum, n) => DFS(n, sum)) } } /* Determine which [[BaseNode]] are involved in resolving the flex connections to/from this node. * * @example * {{{ * a := b := c * d := b * e := f * }}} * * `flexSet` for `a`, `b`, `c`, or `d` will be `Set(a, b, c, d)` `flexSet` for `e` or `f` will be `Set(e,f)` / val flexSet = DFS(this, Map()).values /* The total number of := operators where we're on the left. / val allSink = flexSet.map(_.sinkCard).sum /** The total number of :=* operators used when we're on the right. / val allSource = flexSet.map(_.sourceCard).sum require( allSink == 0 \|\| allSource == 0, s"The nodes ${flexSet.map(_.name)} which are inter-connected by :=* have ${allSink} := operators and ${allSource} := operators connected to them, making it impossible to determine cardinality inference direction." ) allSink - allSource } /** @return A value >= 0 if it is sink cardinality, a negative value for source cardinality. / protected[diplomacy] def edgeArityDirection(n: BaseNode): Int = { if (flexibleArityDirection) flexOffset else if (n.flexibleArityDirection) n.flexOffset else 0 } /* For a node which is connected between two nodes, select the one that will influence the direction of the flex * resolution. / protected[diplomacy] def edgeAritySelect(n: BaseNode, l: => Int, r: => Int): Int = { val dir = edgeArityDirection(n) if (dir < 0) l else if (dir > 0) r else 1 } /* Ensure that the same node is not visited twice in resolving `:=`, etc operators. / private var starCycleGuard = false /** Resolve all the star operators into concrete indicies. As connections are being made, some may be "star" * connections which need to be resolved. In some way to determine how many actual edges they correspond to. We also * need to build up the ranges of edges which correspond to each binding operator, so that We can apply the correct * edge parameters and later build up correct bundle connections. * * [[oPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that oPort (binding * operator). [[iPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that iPort * (binding operator). [[oStar]]: `Int` the value to return for this node `N` for any `N := foo` or `N :=* foo := bar` [[iStar]]: `Int` the value to return for this node `N` for any `foo :=* N` or `bar :=* foo := N` / protected[diplomacy] lazy val ( oPortMapping: Seq[(Int, Int)], iPortMapping: Seq[(Int, Int)], oStar: Int, iStar: Int ) = { try { if (starCycleGuard) throw StarCycleException() starCycleGuard = true // For a given node N... // Number of foo := N // + Number of bar :=* foo := N val oStars = oBindings.count { case (_, n, b, _, _) => b == BIND_STAR \|\| (b == BIND_FLEX && edgeArityDirection(n) < 0) } // Number of N := foo // + Number of N :=* foo := bar val iStars = iBindings.count { case (_, n, b, _, _) => b == BIND_STAR \|\| (b == BIND_FLEX && edgeArityDirection(n) > 0) } // 1 for foo := N // + bar.iStar for bar := foo := N // + foo.iStar for foo := N // + 0 for foo := N val oKnown = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, 0, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => 0 } }.sum // 1 for N := foo // + bar.oStar for N := foo :=* bar // + foo.oStar for N :=* foo // + 0 for N := foo val iKnown = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, 0) case BIND_QUERY => n.oStar case BIND_STAR => 0 } }.sum // Resolve star depends on the node subclass to implement the algorithm for this. val (iStar, oStar) = resolveStar(iKnown, oKnown, iStars, oStars) // Cumulative list of resolved outward binding range starting points val oSum = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, oStar, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => oStar } }.scanLeft(0)(_ + _) // Cumulative list of resolved inward binding range starting points val iSum = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, iStar) case BIND_QUERY => n.oStar case BIND_STAR => iStar } }.scanLeft(0)(_ + _) // Create ranges for each binding based on the running sums and return // those along with resolved values for the star operations. (oSum.init.zip(oSum.tail), iSum.init.zip(iSum.tail), oStar, iStar) } catch { case c: StarCycleException => throw c.copy(loop = context +: c.loop) } } /* Sequence of inward ports. * * This should be called after all star bindings are resolved. * * Each element is: `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. * `n` Instance of inward node. `p` View of [[Parameters]] where this connection was made. `s` Source info where this * connection was made in the source code. / protected[diplomacy] lazy val oDirectPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oBindings.flatMap { case (i, n, _, p, s) => // for each binding operator in this node, look at what it connects to val (start, end) = n.iPortMapping(i) (start until end).map { j => (j, n, p, s) } } /* Sequence of outward ports. * * This should be called after all star bindings are resolved. * * `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. `n` Instance of * outward node. `p` View of [[Parameters]] where this connection was made. `s` [[SourceInfo]] where this connection * was made in the source code. / protected[diplomacy] lazy val iDirectPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iBindings.flatMap { case (i, n, _, p, s) => // query this port index range of this node in the other side of node. val (start, end) = n.oPortMapping(i) (start until end).map { j => (j, n, p, s) } } // Ephemeral nodes ( which have non-None iForward/oForward) have in_degree = out_degree // Thus, there must exist an Eulerian path and the below algorithms terminate @scala.annotation.tailrec private def oTrace( tuple: (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) ): (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.iForward(i) match { case None => (i, n, p, s) case Some((j, m)) => oTrace((j, m, p, s)) } } @scala.annotation.tailrec private def iTrace( tuple: (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) ): (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.oForward(i) match { case None => (i, n, p, s) case Some((j, m)) => iTrace((j, m, p, s)) } } /* Final output ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - Numeric index of this binding in the [[InwardNode]] on the other end. * - [[InwardNode]] on the other end of this binding. * - A view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. / lazy val oPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oDirectPorts.map(oTrace) /* Final input ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - numeric index of this binding in [[OutwardNode]] on the other end. * - [[OutwardNode]] on the other end of this binding. * - a view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. / lazy val iPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iDirectPorts.map(iTrace) private var oParamsCycleGuard = false protected[diplomacy] lazy val diParams: Seq[DI] = iPorts.map { case (i, n, _, _) => n.doParams(i) } protected[diplomacy] lazy val doParams: Seq[DO] = { try { if (oParamsCycleGuard) throw DownwardCycleException() oParamsCycleGuard = true val o = mapParamsD(oPorts.size, diParams) require( o.size == oPorts.size, s"""Diplomacy has detected a problem with your graph: \|At the following node, the number of outward ports should equal the number of produced outward parameters. \|$context \|$connectedPortsInfo \|Downstreamed inward parameters: [${diParams.mkString(",")}] \|Produced outward parameters: [${o.mkString(",")}] \|""".stripMargin ) o.map(outer.mixO(_, this)) } catch { case c: DownwardCycleException => throw c.copy(loop = context +: c.loop) } } private var iParamsCycleGuard = false protected[diplomacy] lazy val uoParams: Seq[UO] = oPorts.map { case (o, n, _, _) => n.uiParams(o) } protected[diplomacy] lazy val uiParams: Seq[UI] = { try { if (iParamsCycleGuard) throw UpwardCycleException() iParamsCycleGuard = true val i = mapParamsU(iPorts.size, uoParams) require( i.size == iPorts.size, s"""Diplomacy has detected a problem with your graph: \|At the following node, the number of inward ports should equal the number of produced inward parameters. \|$context \|$connectedPortsInfo \|Upstreamed outward parameters: [${uoParams.mkString(",")}] \|Produced inward parameters: [${i.mkString(",")}] \|""".stripMargin ) i.map(inner.mixI(_, this)) } catch { case c: UpwardCycleException => throw c.copy(loop = context +: c.loop) } } /* Outward edge parameters. / protected[diplomacy] lazy val edgesOut: Seq[EO] = (oPorts.zip(doParams)).map { case ((i, n, p, s), o) => outer.edgeO(o, n.uiParams(i), p, s) } /* Inward edge parameters. / protected[diplomacy] lazy val edgesIn: Seq[EI] = (iPorts.zip(uiParams)).map { case ((o, n, p, s), i) => inner.edgeI(n.doParams(o), i, p, s) } /* A tuple of the input edge parameters and output edge parameters for the edges bound to this node. * * If you need to access to the edges of a foreign Node, use this method (in/out create bundles). / lazy val edges: Edges[EI, EO] = Edges(edgesIn, edgesOut) /* Create actual Wires corresponding to the Bundles parameterized by the outward edges of this node. / protected[diplomacy] lazy val bundleOut: Seq[BO] = edgesOut.map { e => val x = Wire(outer.bundleO(e)).suggestName(s"${valName.value}Out") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } /* Create actual Wires corresponding to the Bundles parameterized by the inward edges of this node. / protected[diplomacy] lazy val bundleIn: Seq[BI] = edgesIn.map { e => val x = Wire(inner.bundleI(e)).suggestName(s"${valName.value}In") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } private def emptyDanglesOut: Seq[Dangle] = oPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(serial, i), sink = HalfEdge(n.serial, j), flipped = false, name = wirePrefix + "out", dataOpt = None ) } private def emptyDanglesIn: Seq[Dangle] = iPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(n.serial, j), sink = HalfEdge(serial, i), flipped = true, name = wirePrefix + "in", dataOpt = None ) } /* Create the [[Dangle]]s which describe the connections from this node output to other nodes inputs. / protected[diplomacy] def danglesOut: Seq[Dangle] = emptyDanglesOut.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleOut(i))) } /* Create the [[Dangle]]s which describe the connections from this node input from other nodes outputs. / protected[diplomacy] def danglesIn: Seq[Dangle] = emptyDanglesIn.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleIn(i))) } private[diplomacy] var instantiated = false /* Gather Bundle and edge parameters of outward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. / def out: Seq[(BO, EO)] = { require( instantiated, s"$name.out should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleOut.zip(edgesOut) } /* Gather Bundle and edge parameters of inward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. / def in: Seq[(BI, EI)] = { require( instantiated, s"$name.in should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleIn.zip(edgesIn) } /* Actually instantiate this node during [[LazyModuleImp]] evaluation. Mark that it's safe to use the Bundle wires, * instantiate monitors on all input ports if appropriate, and return all the dangles of this node. / protected[diplomacy] def instantiate(): Seq[Dangle] = { instantiated = true if (!circuitIdentity) { (iPorts.zip(in)).foreach { case ((_, _, p, _), (b, e)) => if (p(MonitorsEnabled)) inner.monitor(b, e) } } danglesOut ++ danglesIn } protected[diplomacy] def cloneDangles(): Seq[Dangle] = emptyDanglesOut ++ emptyDanglesIn /* Connects the outward part of a node with the inward part of this node. / protected[diplomacy] def bind( h: OutwardNode[DI, UI, BI], binding: NodeBinding )( implicit p: Parameters, sourceInfo: SourceInfo ): Unit = { val x = this // x := y val y = h sourceLine(sourceInfo, " at ", "") val i = x.iPushed val o = y.oPushed y.oPush( i, x, binding match { case BIND_ONCE => BIND_ONCE case BIND_FLEX => BIND_FLEX case BIND_STAR => BIND_QUERY case BIND_QUERY => BIND_STAR } ) x.iPush(o, y, binding) } / Metadata for printing the node graph. / def inputs: Seq[(OutwardNode[DI, UI, BI], RenderedEdge)] = (iPorts.zip(edgesIn)).map { case ((_, n, p, _), e) => val re = inner.render(e) (n, re.copy(flipped = re.flipped != p(RenderFlipped))) } /* Metadata for printing the node graph / def outputs: Seq[(InwardNode[DO, UO, BO], RenderedEdge)] = oPorts.map { case (i, n, _, _) => (n, n.inputs(i)._2) } } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportPutFull \|\| manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB \|\| manager.anySupportGet \|\| manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportPutFull \|\| client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe \|\| client.anySupportGet \|\| client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet \|\| client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull \|\| client.anySupportPutPartial \|\| client.anySupportHint \|\| client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet \|\| manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull \|\| manager.anySupportPutPartial \|\| manager.anySupportHint \|\| manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) \|\| !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.ProbeAckData \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode \| small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U \|\| beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }	module TileResetSetter( // @[TileResetSetter.scala:26:25] input clock, // @[TileResetSetter.scala:26:25] input reset, // @[TileResetSetter.scala:26:25] input auto_clock_in_member_allClocks_uncore_clock, // @[LazyModuleImp.scala:107:25] input auto_clock_in_member_allClocks_uncore_reset, // @[LazyModuleImp.scala:107:25] output auto_clock_out_member_allClocks_uncore_clock, // @[LazyModuleImp.scala:107:25] output auto_clock_out_member_allClocks_uncore_reset, // @[LazyModuleImp.scala:107:25] output auto_tl_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_tl_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_tl_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_tl_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [1:0] auto_tl_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [10:0] auto_tl_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [20:0] auto_tl_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_tl_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_tl_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_tl_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_tl_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_tl_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_tl_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_tl_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [10:0] auto_tl_in_d_bits_source // @[LazyModuleImp.scala:107:25] ); wire out_front_valid; // @[RegisterRouter.scala:87:24] wire out_front_ready; // @[RegisterRouter.scala:87:24] wire out_bits_read; // @[RegisterRouter.scala:87:24] wire [10:0] out_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:87:24] wire [8:0] in_bits_index; // @[RegisterRouter.scala:73:18] wire in_bits_read; // @[RegisterRouter.scala:73:18] wire auto_clock_in_member_allClocks_uncore_clock_0 = auto_clock_in_member_allClocks_uncore_clock; // @[TileResetSetter.scala:26:25] wire auto_clock_in_member_allClocks_uncore_reset_0 = auto_clock_in_member_allClocks_uncore_reset; // @[TileResetSetter.scala:26:25] wire auto_tl_in_a_valid_0 = auto_tl_in_a_valid; // @[TileResetSetter.scala:26:25] wire [2:0] auto_tl_in_a_bits_opcode_0 = auto_tl_in_a_bits_opcode; // @[TileResetSetter.scala:26:25] wire [2:0] auto_tl_in_a_bits_param_0 = auto_tl_in_a_bits_param; // @[TileResetSetter.scala:26:25] wire [1:0] auto_tl_in_a_bits_size_0 = auto_tl_in_a_bits_size; // @[TileResetSetter.scala:26:25] wire [10:0] auto_tl_in_a_bits_source_0 = auto_tl_in_a_bits_source; // @[TileResetSetter.scala:26:25] wire [20:0] auto_tl_in_a_bits_address_0 = auto_tl_in_a_bits_address; // @[TileResetSetter.scala:26:25] wire [7:0] auto_tl_in_a_bits_mask_0 = auto_tl_in_a_bits_mask; // @[TileResetSetter.scala:26:25] wire [63:0] auto_tl_in_a_bits_data_0 = auto_tl_in_a_bits_data; // @[TileResetSetter.scala:26:25] wire auto_tl_in_a_bits_corrupt_0 = auto_tl_in_a_bits_corrupt; // @[TileResetSetter.scala:26:25] wire auto_tl_in_d_ready_0 = auto_tl_in_d_ready; // @[TileResetSetter.scala:26:25] wire [1:0] _out_frontSel_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _out_backSel_T = 2'h1; // @[OneHot.scala:58:35] wire [8:0] out_maskMatch = 9'h1FF; // @[RegisterRouter.scala:87:24] wire tile_async_resets_0 = 1'h1; // @[TileResetSetter.scala:29:33] wire _tile_async_resets_0_T = 1'h1; // @[TileResetSetter.scala:31:38] wire out_frontSel_0 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_backSel_0 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_5 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48] wire out_rifireMux = 1'h1; // @[MuxLiteral.scala:49:10] wire out_wifireMux_out = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_6 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48] wire out_wifireMux = 1'h1; // @[MuxLiteral.scala:49:10] wire out_rofireMux_out = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_5 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48] wire out_rofireMux = 1'h1; // @[MuxLiteral.scala:49:10] wire out_wofireMux_out = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_6 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48] wire out_wofireMux = 1'h1; // @[MuxLiteral.scala:49:10] wire out_iready = 1'h1; // @[RegisterRouter.scala:87:24] wire out_oready = 1'h1; // @[RegisterRouter.scala:87:24] wire [2:0] tlNodeIn_d_bits_d_opcode = 3'h0; // @[Edges.scala:792:17] wire [1:0] auto_tl_in_d_bits_param = 2'h0; // @[TileResetSetter.scala:26:25] wire [1:0] tlNodeIn_d_bits_param = 2'h0; // @[MixedNode.scala:551:17] wire [1:0] tlNodeIn_d_bits_d_param = 2'h0; // @[Edges.scala:792:17] wire auto_tl_in_d_bits_sink = 1'h0; // @[TileResetSetter.scala:26:25] wire auto_tl_in_d_bits_denied = 1'h0; // @[TileResetSetter.scala:26:25] wire auto_tl_in_d_bits_corrupt = 1'h0; // @[TileResetSetter.scala:26:25] wire tlNodeIn_d_bits_sink = 1'h0; // @[MixedNode.scala:551:17] wire tlNodeIn_d_bits_denied = 1'h0; // @[MixedNode.scala:551:17] wire tlNodeIn_d_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17] wire _out_T_7 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_T_8 = 1'h0; // @[RegisterRouter.scala:87:24] wire out_frontSel_1 = 1'h0; // @[RegisterRouter.scala:87:24] wire out_backSel_1 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_6 = 1'h0; // @[MuxLiteral.scala:49:17] wire _out_wifireMux_T_7 = 1'h0; // @[MuxLiteral.scala:49:17] wire _out_rofireMux_T_6 = 1'h0; // @[MuxLiteral.scala:49:17] wire _out_wofireMux_T_7 = 1'h0; // @[MuxLiteral.scala:49:17] wire _out_out_bits_data_T = 1'h0; // @[MuxLiteral.scala:49:17] wire _out_out_bits_data_T_2 = 1'h0; // @[MuxLiteral.scala:49:17] wire _out_out_bits_data_WIRE_1_0 = 1'h0; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_T_3 = 1'h0; // @[MuxLiteral.scala:49:10] wire _out_out_bits_data_T_4 = 1'h0; // @[RegisterRouter.scala:87:24] wire tlNodeIn_d_bits_d_sink = 1'h0; // @[Edges.scala:792:17] wire tlNodeIn_d_bits_d_denied = 1'h0; // @[Edges.scala:792:17] wire tlNodeIn_d_bits_d_corrupt = 1'h0; // @[Edges.scala:792:17] wire [63:0] auto_tl_in_d_bits_data = 64'h0; // @[TileResetSetter.scala:26:25] wire [63:0] tlNodeIn_d_bits_data = 64'h0; // @[MixedNode.scala:551:17] wire [63:0] out_bits_data = 64'h0; // @[RegisterRouter.scala:87:24] wire [63:0] tlNodeIn_d_bits_d_data = 64'h0; // @[Edges.scala:792:17] wire clockNodeIn_member_allClocks_uncore_clock = auto_clock_in_member_allClocks_uncore_clock_0; // @[MixedNode.scala:551:17] wire clockNodeOut_member_allClocks_uncore_clock; // @[MixedNode.scala:542:17] wire clockNodeIn_member_allClocks_uncore_reset = auto_clock_in_member_allClocks_uncore_reset_0; // @[MixedNode.scala:551:17] wire clockNodeOut_member_allClocks_uncore_reset; // @[MixedNode.scala:542:17] wire tlNodeIn_a_ready; // @[MixedNode.scala:551:17] wire tlNodeIn_a_valid = auto_tl_in_a_valid_0; // @[MixedNode.scala:551:17] wire [2:0] tlNodeIn_a_bits_opcode = auto_tl_in_a_bits_opcode_0; // @[MixedNode.scala:551:17] wire [2:0] tlNodeIn_a_bits_param = auto_tl_in_a_bits_param_0; // @[MixedNode.scala:551:17] wire [1:0] tlNodeIn_a_bits_size = auto_tl_in_a_bits_size_0; // @[MixedNode.scala:551:17] wire [10:0] tlNodeIn_a_bits_source = auto_tl_in_a_bits_source_0; // @[MixedNode.scala:551:17] wire [20:0] tlNodeIn_a_bits_address = auto_tl_in_a_bits_address_0; // @[MixedNode.scala:551:17] wire [7:0] tlNodeIn_a_bits_mask = auto_tl_in_a_bits_mask_0; // @[MixedNode.scala:551:17] wire [63:0] tlNodeIn_a_bits_data = auto_tl_in_a_bits_data_0; // @[MixedNode.scala:551:17] wire tlNodeIn_a_bits_corrupt = auto_tl_in_a_bits_corrupt_0; // @[MixedNode.scala:551:17] wire tlNodeIn_d_ready = auto_tl_in_d_ready_0; // @[MixedNode.scala:551:17] wire tlNodeIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] tlNodeIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] tlNodeIn_d_bits_size; // @[MixedNode.scala:551:17] wire [10:0] tlNodeIn_d_bits_source; // @[MixedNode.scala:551:17] wire auto_clock_out_member_allClocks_uncore_clock_0; // @[TileResetSetter.scala:26:25] wire auto_clock_out_member_allClocks_uncore_reset_0; // @[TileResetSetter.scala:26:25] wire auto_tl_in_a_ready_0; // @[TileResetSetter.scala:26:25] wire [2:0] auto_tl_in_d_bits_opcode_0; // @[TileResetSetter.scala:26:25] wire [1:0] auto_tl_in_d_bits_size_0; // @[TileResetSetter.scala:26:25] wire [10:0] auto_tl_in_d_bits_source_0; // @[TileResetSetter.scala:26:25] wire auto_tl_in_d_valid_0; // @[TileResetSetter.scala:26:25] wire in_ready; // @[RegisterRouter.scala:73:18] assign auto_tl_in_a_ready_0 = tlNodeIn_a_ready; // @[MixedNode.scala:551:17] wire in_valid = tlNodeIn_a_valid; // @[RegisterRouter.scala:73:18] wire [1:0] in_bits_extra_tlrr_extra_size = tlNodeIn_a_bits_size; // @[RegisterRouter.scala:73:18] wire [10:0] in_bits_extra_tlrr_extra_source = tlNodeIn_a_bits_source; // @[RegisterRouter.scala:73:18] wire [7:0] in_bits_mask = tlNodeIn_a_bits_mask; // @[RegisterRouter.scala:73:18] wire [63:0] in_bits_data = tlNodeIn_a_bits_data; // @[RegisterRouter.scala:73:18] wire out_ready = tlNodeIn_d_ready; // @[RegisterRouter.scala:87:24] wire out_valid; // @[RegisterRouter.scala:87:24] assign auto_tl_in_d_valid_0 = tlNodeIn_d_valid; // @[MixedNode.scala:551:17] assign auto_tl_in_d_bits_opcode_0 = tlNodeIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] tlNodeIn_d_bits_d_size; // @[Edges.scala:792:17] assign auto_tl_in_d_bits_size_0 = tlNodeIn_d_bits_size; // @[MixedNode.scala:551:17] wire [10:0] tlNodeIn_d_bits_d_source; // @[Edges.scala:792:17] assign auto_tl_in_d_bits_source_0 = tlNodeIn_d_bits_source; // @[MixedNode.scala:551:17] assign auto_clock_out_member_allClocks_uncore_clock_0 = clockNodeOut_member_allClocks_uncore_clock; // @[MixedNode.scala:542:17] assign auto_clock_out_member_allClocks_uncore_reset_0 = clockNodeOut_member_allClocks_uncore_reset; // @[MixedNode.scala:542:17] assign clockNodeOut_member_allClocks_uncore_clock = clockNodeIn_member_allClocks_uncore_clock; // @[MixedNode.scala:542:17, :551:17] assign clockNodeOut_member_allClocks_uncore_reset = clockNodeIn_member_allClocks_uncore_reset; // @[MixedNode.scala:542:17, :551:17] wire _out_in_ready_T; // @[RegisterRouter.scala:87:24] assign tlNodeIn_a_ready = in_ready; // @[RegisterRouter.scala:73:18] wire _in_bits_read_T; // @[RegisterRouter.scala:74:36] wire _out_front_valid_T = in_valid; // @[RegisterRouter.scala:73:18, :87:24] wire out_front_bits_read = in_bits_read; // @[RegisterRouter.scala:73:18, :87:24] wire [8:0] out_front_bits_index = in_bits_index; // @[RegisterRouter.scala:73:18, :87:24] wire [63:0] out_front_bits_data = in_bits_data; // @[RegisterRouter.scala:73:18, :87:24] wire [7:0] out_front_bits_mask = in_bits_mask; // @[RegisterRouter.scala:73:18, :87:24] wire [10:0] out_front_bits_extra_tlrr_extra_source = in_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:73:18, :87:24] wire [1:0] out_front_bits_extra_tlrr_extra_size = in_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:73:18, :87:24] assign _in_bits_read_T = tlNodeIn_a_bits_opcode == 3'h4; // @[RegisterRouter.scala:74:36] assign in_bits_read = _in_bits_read_T; // @[RegisterRouter.scala:73:18, :74:36] wire [17:0] _in_bits_index_T = tlNodeIn_a_bits_address[20:3]; // @[Edges.scala:192:34] assign in_bits_index = _in_bits_index_T[8:0]; // @[RegisterRouter.scala:73:18, :75:19] wire _out_front_ready_T = out_ready; // @[RegisterRouter.scala:87:24] wire _out_out_valid_T; // @[RegisterRouter.scala:87:24] assign tlNodeIn_d_valid = out_valid; // @[RegisterRouter.scala:87:24] wire _tlNodeIn_d_bits_opcode_T = out_bits_read; // @[RegisterRouter.scala:87:24, :105:25] assign tlNodeIn_d_bits_d_source = out_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:87:24] wire [1:0] out_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:87:24] assign tlNodeIn_d_bits_d_size = out_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:87:24] assign _out_in_ready_T = out_front_ready; // @[RegisterRouter.scala:87:24] assign _out_out_valid_T = out_front_valid; // @[RegisterRouter.scala:87:24] assign out_bits_read = out_front_bits_read; // @[RegisterRouter.scala:87:24] wire [8:0] out_findex = out_front_bits_index; // @[RegisterRouter.scala:87:24] wire [8:0] out_bindex = out_front_bits_index; // @[RegisterRouter.scala:87:24] assign out_bits_extra_tlrr_extra_source = out_front_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:87:24] assign out_bits_extra_tlrr_extra_size = out_front_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:87:24] wire _out_T = out_findex == 9'h0; // @[RegisterRouter.scala:87:24] wire _out_T_1 = out_bindex == 9'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24] wire _out_out_bits_data_WIRE_0 = _out_T_1; // @[MuxLiteral.scala:49:48] wire out_rivalid_0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24] wire out_wivalid_0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24] wire out_roready_0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24] wire out_woready_0; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T = out_front_bits_mask[0]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T = out_front_bits_mask[0]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_1 = out_front_bits_mask[1]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_1 = out_front_bits_mask[1]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_2 = out_front_bits_mask[2]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_2 = out_front_bits_mask[2]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_3 = out_front_bits_mask[3]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_3 = out_front_bits_mask[3]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_4 = out_front_bits_mask[4]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_4 = out_front_bits_mask[4]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_5 = out_front_bits_mask[5]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_5 = out_front_bits_mask[5]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_6 = out_front_bits_mask[6]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_6 = out_front_bits_mask[6]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_7 = out_front_bits_mask[7]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_7 = out_front_bits_mask[7]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_8 = {8{_out_frontMask_T}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_9 = {8{_out_frontMask_T_1}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_10 = {8{_out_frontMask_T_2}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_11 = {8{_out_frontMask_T_3}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_12 = {8{_out_frontMask_T_4}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_13 = {8{_out_frontMask_T_5}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_14 = {8{_out_frontMask_T_6}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_15 = {8{_out_frontMask_T_7}}; // @[RegisterRouter.scala:87:24] wire [15:0] out_frontMask_lo_lo = {_out_frontMask_T_9, _out_frontMask_T_8}; // @[RegisterRouter.scala:87:24] wire [15:0] out_frontMask_lo_hi = {_out_frontMask_T_11, _out_frontMask_T_10}; // @[RegisterRouter.scala:87:24] wire [31:0] out_frontMask_lo = {out_frontMask_lo_hi, out_frontMask_lo_lo}; // @[RegisterRouter.scala:87:24] wire [15:0] out_frontMask_hi_lo = {_out_frontMask_T_13, _out_frontMask_T_12}; // @[RegisterRouter.scala:87:24] wire [15:0] out_frontMask_hi_hi = {_out_frontMask_T_15, _out_frontMask_T_14}; // @[RegisterRouter.scala:87:24] wire [31:0] out_frontMask_hi = {out_frontMask_hi_hi, out_frontMask_hi_lo}; // @[RegisterRouter.scala:87:24] wire [63:0] out_frontMask = {out_frontMask_hi, out_frontMask_lo}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_8 = {8{_out_backMask_T}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_9 = {8{_out_backMask_T_1}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_10 = {8{_out_backMask_T_2}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_11 = {8{_out_backMask_T_3}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_12 = {8{_out_backMask_T_4}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_13 = {8{_out_backMask_T_5}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_14 = {8{_out_backMask_T_6}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_15 = {8{_out_backMask_T_7}}; // @[RegisterRouter.scala:87:24] wire [15:0] out_backMask_lo_lo = {_out_backMask_T_9, _out_backMask_T_8}; // @[RegisterRouter.scala:87:24] wire [15:0] out_backMask_lo_hi = {_out_backMask_T_11, _out_backMask_T_10}; // @[RegisterRouter.scala:87:24] wire [31:0] out_backMask_lo = {out_backMask_lo_hi, out_backMask_lo_lo}; // @[RegisterRouter.scala:87:24] wire [15:0] out_backMask_hi_lo = {_out_backMask_T_13, _out_backMask_T_12}; // @[RegisterRouter.scala:87:24] wire [15:0] out_backMask_hi_hi = {_out_backMask_T_15, _out_backMask_T_14}; // @[RegisterRouter.scala:87:24] wire [31:0] out_backMask_hi = {out_backMask_hi_hi, out_backMask_hi_lo}; // @[RegisterRouter.scala:87:24] wire [63:0] out_backMask = {out_backMask_hi, out_backMask_lo}; // @[RegisterRouter.scala:87:24] wire _out_rimask_T = out_frontMask[0]; // @[RegisterRouter.scala:87:24] wire _out_wimask_T = out_frontMask[0]; // @[RegisterRouter.scala:87:24] wire out_rimask = _out_rimask_T; // @[RegisterRouter.scala:87:24] wire out_wimask = _out_wimask_T; // @[RegisterRouter.scala:87:24] wire _out_romask_T = out_backMask[0]; // @[RegisterRouter.scala:87:24] wire _out_womask_T = out_backMask[0]; // @[RegisterRouter.scala:87:24] wire out_romask = _out_romask_T; // @[RegisterRouter.scala:87:24] wire out_womask = _out_womask_T; // @[RegisterRouter.scala:87:24] wire out_f_rivalid = out_rivalid_0 & out_rimask; // @[RegisterRouter.scala:87:24] wire out_f_roready = out_roready_0 & out_romask; // @[RegisterRouter.scala:87:24] wire out_f_wivalid = out_wivalid_0 & out_wimask; // @[RegisterRouter.scala:87:24] wire out_f_woready = out_woready_0 & out_womask; // @[RegisterRouter.scala:87:24] wire _out_T_2 = out_front_bits_data[0]; // @[RegisterRouter.scala:87:24] wire _out_T_3 = ~out_rimask; // @[RegisterRouter.scala:87:24] wire _out_T_4 = ~out_wimask; // @[RegisterRouter.scala:87:24] wire _out_T_5 = ~out_romask; // @[RegisterRouter.scala:87:24] wire _out_T_6 = ~out_womask; // @[RegisterRouter.scala:87:24] wire _GEN = in_valid & out_front_ready; // @[RegisterRouter.scala:73:18, :87:24] wire _out_rifireMux_T; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T = _GEN; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T = _GEN; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1 = _out_rifireMux_T & out_front_bits_read; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_2 = _out_rifireMux_T_1; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_3 = _out_rifireMux_T_2 & _out_T; // @[RegisterRouter.scala:87:24] assign out_rivalid_0 = _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_4 = ~_out_T; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1 = ~out_front_bits_read; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_2 = _out_wifireMux_T & _out_wifireMux_T_1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_3 = _out_wifireMux_T_2; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_4 = _out_wifireMux_T_3 & _out_T; // @[RegisterRouter.scala:87:24] assign out_wivalid_0 = _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_5 = ~_out_T; // @[RegisterRouter.scala:87:24] wire _GEN_0 = out_front_valid & out_ready; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T = _GEN_0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T = _GEN_0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1 = _out_rofireMux_T & out_front_bits_read; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_2 = _out_rofireMux_T_1; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_3 = _out_rofireMux_T_2 & _out_T_1; // @[RegisterRouter.scala:87:24] assign out_roready_0 = _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_4 = ~_out_T_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1 = ~out_front_bits_read; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_2 = _out_wofireMux_T & _out_wofireMux_T_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_3 = _out_wofireMux_T_2; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_4 = _out_wofireMux_T_3 & _out_T_1; // @[RegisterRouter.scala:87:24] assign out_woready_0 = _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_5 = ~_out_T_1; // @[RegisterRouter.scala:87:24] assign in_ready = _out_in_ready_T; // @[RegisterRouter.scala:73:18, :87:24] assign out_front_valid = _out_front_valid_T; // @[RegisterRouter.scala:87:24] assign out_front_ready = _out_front_ready_T; // @[RegisterRouter.scala:87:24] assign out_valid = _out_out_valid_T; // @[RegisterRouter.scala:87:24] wire _out_out_bits_data_T_1 = _out_out_bits_data_WIRE_0; // @[MuxLiteral.scala:49:{10,48}] assign tlNodeIn_d_bits_size = tlNodeIn_d_bits_d_size; // @[Edges.scala:792:17] assign tlNodeIn_d_bits_source = tlNodeIn_d_bits_d_source; // @[Edges.scala:792:17] assign tlNodeIn_d_bits_opcode = {2'h0, _tlNodeIn_d_bits_opcode_T}; // @[RegisterRouter.scala:105:{19,25}] TLMonitor_60 monitor ( // @[Nodes.scala:27:25] .clock (clock), .reset (reset), .io_in_a_ready (tlNodeIn_a_ready), // @[MixedNode.scala:551:17] .io_in_a_valid (tlNodeIn_a_valid), // @[MixedNode.scala:551:17] .io_in_a_bits_opcode (tlNodeIn_a_bits_opcode), // @[MixedNode.scala:551:17] .io_in_a_bits_param (tlNodeIn_a_bits_param), // @[MixedNode.scala:551:17] .io_in_a_bits_size (tlNodeIn_a_bits_size), // @[MixedNode.scala:551:17] .io_in_a_bits_source (tlNodeIn_a_bits_source), // @[MixedNode.scala:551:17] .io_in_a_bits_address (tlNodeIn_a_bits_address), // @[MixedNode.scala:551:17] .io_in_a_bits_mask (tlNodeIn_a_bits_mask), // @[MixedNode.scala:551:17] .io_in_a_bits_data (tlNodeIn_a_bits_data), // @[MixedNode.scala:551:17] .io_in_a_bits_corrupt (tlNodeIn_a_bits_corrupt), // @[MixedNode.scala:551:17] .io_in_d_ready (tlNodeIn_d_ready), // @[MixedNode.scala:551:17] .io_in_d_valid (tlNodeIn_d_valid), // @[MixedNode.scala:551:17] .io_in_d_bits_opcode (tlNodeIn_d_bits_opcode), // @[MixedNode.scala:551:17] .io_in_d_bits_size (tlNodeIn_d_bits_size), // @[MixedNode.scala:551:17] .io_in_d_bits_source (tlNodeIn_d_bits_source) // @[MixedNode.scala:551:17] ); // @[Nodes.scala:27:25] AsyncResetRegVec_w1_i0_6 r_tile_resets_0 ( // @[TileResetSetter.scala:33:15] .clock (clock), .io_d (_out_T_2), // @[RegisterRouter.scala:87:24] .io_en (out_f_woready) // @[RegisterRouter.scala:87:24] ); // @[TileResetSetter.scala:33:15] assign auto_clock_out_member_allClocks_uncore_clock = auto_clock_out_member_allClocks_uncore_clock_0; // @[TileResetSetter.scala:26:25] assign auto_clock_out_member_allClocks_uncore_reset = auto_clock_out_member_allClocks_uncore_reset_0; // @[TileResetSetter.scala:26:25] assign auto_tl_in_a_ready = auto_tl_in_a_ready_0; // @[TileResetSetter.scala:26:25] assign auto_tl_in_d_valid = auto_tl_in_d_valid_0; // @[TileResetSetter.scala:26:25] assign auto_tl_in_d_bits_opcode = auto_tl_in_d_bits_opcode_0; // @[TileResetSetter.scala:26:25] assign auto_tl_in_d_bits_size = auto_tl_in_d_bits_size_0; // @[TileResetSetter.scala:26:25] assign auto_tl_in_d_bits_source = auto_tl_in_d_bits_source_0; // @[TileResetSetter.scala:26:25] endmodule
Generate the Verilog code corresponding to the following Chisel files. File Tile.scala: // See README.md for license details. package gemmini import chisel3._ import chisel3.util._ import Util._ /** * A Tile is a purely combinational 2D array of passThrough PEs. * a, b, s, and in_propag are broadcast across the entire array and are passed through to the Tile's outputs * @param width The data width of each PE in bits * @param rows Number of PEs on each row * @param columns Number of PEs on each column */ class Tile[T <: Data](inputType: T, outputType: T, accType: T, df: Dataflow.Value, tree_reduction: Boolean, max_simultaneous_matmuls: Int, val rows: Int, val columns: Int)(implicit ev: Arithmetic[T]) extends Module { val io = IO(new Bundle { val in_a = Input(Vec(rows, inputType)) val in_b = Input(Vec(columns, outputType)) // This is the output of the tile next to it val in_d = Input(Vec(columns, outputType)) val in_control = Input(Vec(columns, new PEControl(accType))) val in_id = Input(Vec(columns, UInt(log2Up(max_simultaneous_matmuls).W))) val in_last = Input(Vec(columns, Bool())) val out_a = Output(Vec(rows, inputType)) val out_c = Output(Vec(columns, outputType)) val out_b = Output(Vec(columns, outputType)) val out_control = Output(Vec(columns, new PEControl(accType))) val out_id = Output(Vec(columns, UInt(log2Up(max_simultaneous_matmuls).W))) val out_last = Output(Vec(columns, Bool())) val in_valid = Input(Vec(columns, Bool())) val out_valid = Output(Vec(columns, Bool())) val bad_dataflow = Output(Bool()) }) import ev._ val tile = Seq.fill(rows, columns)(Module(new PE(inputType, outputType, accType, df, max_simultaneous_matmuls))) val tileT = tile.transpose // TODO: abstract hori/vert broadcast, all these connections look the same // Broadcast 'a' horizontally across the Tile for (r <- 0 until rows) { tile(r).foldLeft(io.in_a(r)) { case (in_a, pe) => pe.io.in_a := in_a pe.io.out_a } } // Broadcast 'b' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_b(c)) { case (in_b, pe) => pe.io.in_b := (if (tree_reduction) in_b.zero else in_b) pe.io.out_b } } // Broadcast 'd' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_d(c)) { case (in_d, pe) => pe.io.in_d := in_d pe.io.out_c } } // Broadcast 'control' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_control(c)) { case (in_ctrl, pe) => pe.io.in_control := in_ctrl pe.io.out_control } } // Broadcast 'garbage' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_valid(c)) { case (v, pe) => pe.io.in_valid := v pe.io.out_valid } } // Broadcast 'id' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_id(c)) { case (id, pe) => pe.io.in_id := id pe.io.out_id } } // Broadcast 'last' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_last(c)) { case (last, pe) => pe.io.in_last := last pe.io.out_last } } // Drive the Tile's bottom IO for (c <- 0 until columns) { io.out_c(c) := tile(rows-1)(c).io.out_c io.out_control(c) := tile(rows-1)(c).io.out_control io.out_id(c) := tile(rows-1)(c).io.out_id io.out_last(c) := tile(rows-1)(c).io.out_last io.out_valid(c) := tile(rows-1)(c).io.out_valid io.out_b(c) := { if (tree_reduction) { val prods = tileT(c).map(_.io.out_b) accumulateTree(prods :+ io.in_b(c)) } else { tile(rows - 1)(c).io.out_b } } } io.bad_dataflow := tile.map(_.map(_.io.bad_dataflow).reduce(_\|\|_)).reduce(_\|\|_) // Drive the Tile's right IO for (r <- 0 until rows) { io.out_a(r) := tile(r)(columns-1).io.out_a } }	module Tile_80( // @[Tile.scala:16:7] input clock, // @[Tile.scala:16:7] input reset, // @[Tile.scala:16:7] input [7:0] io_in_a_0, // @[Tile.scala:17:14] input [19:0] io_in_b_0, // @[Tile.scala:17:14] input [19:0] io_in_d_0, // @[Tile.scala:17:14] input io_in_control_0_dataflow, // @[Tile.scala:17:14] input io_in_control_0_propagate, // @[Tile.scala:17:14] input [4:0] io_in_control_0_shift, // @[Tile.scala:17:14] input [2:0] io_in_id_0, // @[Tile.scala:17:14] input io_in_last_0, // @[Tile.scala:17:14] output [7:0] io_out_a_0, // @[Tile.scala:17:14] output [19:0] io_out_c_0, // @[Tile.scala:17:14] output [19:0] io_out_b_0, // @[Tile.scala:17:14] output io_out_control_0_dataflow, // @[Tile.scala:17:14] output io_out_control_0_propagate, // @[Tile.scala:17:14] output [4:0] io_out_control_0_shift, // @[Tile.scala:17:14] output [2:0] io_out_id_0, // @[Tile.scala:17:14] output io_out_last_0, // @[Tile.scala:17:14] input io_in_valid_0, // @[Tile.scala:17:14] output io_out_valid_0 // @[Tile.scala:17:14] ); wire [7:0] io_in_a_0_0 = io_in_a_0; // @[Tile.scala:16:7] wire [19:0] io_in_b_0_0 = io_in_b_0; // @[Tile.scala:16:7] wire [19:0] io_in_d_0_0 = io_in_d_0; // @[Tile.scala:16:7] wire io_in_control_0_dataflow_0 = io_in_control_0_dataflow; // @[Tile.scala:16:7] wire io_in_control_0_propagate_0 = io_in_control_0_propagate; // @[Tile.scala:16:7] wire [4:0] io_in_control_0_shift_0 = io_in_control_0_shift; // @[Tile.scala:16:7] wire [2:0] io_in_id_0_0 = io_in_id_0; // @[Tile.scala:16:7] wire io_in_last_0_0 = io_in_last_0; // @[Tile.scala:16:7] wire io_in_valid_0_0 = io_in_valid_0; // @[Tile.scala:16:7] wire io_bad_dataflow = 1'h0; // @[Tile.scala:16:7, :17:14, :42:44] wire [7:0] io_out_a_0_0; // @[Tile.scala:16:7] wire [19:0] io_out_c_0_0; // @[Tile.scala:16:7] wire [19:0] io_out_b_0_0; // @[Tile.scala:16:7] wire io_out_control_0_dataflow_0; // @[Tile.scala:16:7] wire io_out_control_0_propagate_0; // @[Tile.scala:16:7] wire [4:0] io_out_control_0_shift_0; // @[Tile.scala:16:7] wire [2:0] io_out_id_0_0; // @[Tile.scala:16:7] wire io_out_last_0_0; // @[Tile.scala:16:7] wire io_out_valid_0_0; // @[Tile.scala:16:7] PE_336 tile_0_0 ( // @[Tile.scala:42:44] .clock (clock), .reset (reset), .io_in_a (io_in_a_0_0), // @[Tile.scala:16:7] .io_in_b (io_in_b_0_0), // @[Tile.scala:16:7] .io_in_d (io_in_d_0_0), // @[Tile.scala:16:7] .io_out_a (io_out_a_0_0), .io_out_b (io_out_b_0_0), .io_out_c (io_out_c_0_0), .io_in_control_dataflow (io_in_control_0_dataflow_0), // @[Tile.scala:16:7] .io_in_control_propagate (io_in_control_0_propagate_0), // @[Tile.scala:16:7] .io_in_control_shift (io_in_control_0_shift_0), // @[Tile.scala:16:7] .io_out_control_dataflow (io_out_control_0_dataflow_0), .io_out_control_propagate (io_out_control_0_propagate_0), .io_out_control_shift (io_out_control_0_shift_0), .io_in_id (io_in_id_0_0), // @[Tile.scala:16:7] .io_out_id (io_out_id_0_0), .io_in_last (io_in_last_0_0), // @[Tile.scala:16:7] .io_out_last (io_out_last_0_0), .io_in_valid (io_in_valid_0_0), // @[Tile.scala:16:7] .io_out_valid (io_out_valid_0_0) ); // @[Tile.scala:42:44] assign io_out_a_0 = io_out_a_0_0; // @[Tile.scala:16:7] assign io_out_c_0 = io_out_c_0_0; // @[Tile.scala:16:7] assign io_out_b_0 = io_out_b_0_0; // @[Tile.scala:16:7] assign io_out_control_0_dataflow = io_out_control_0_dataflow_0; // @[Tile.scala:16:7] assign io_out_control_0_propagate = io_out_control_0_propagate_0; // @[Tile.scala:16:7] assign io_out_control_0_shift = io_out_control_0_shift_0; // @[Tile.scala:16:7] assign io_out_id_0 = io_out_id_0_0; // @[Tile.scala:16:7] assign io_out_last_0 = io_out_last_0_0; // @[Tile.scala:16:7] assign io_out_valid_0 = io_out_valid_0_0; // @[Tile.scala:16:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File RoundAnyRawFNToRecFN.scala: /============================================================================ This Chisel source file is part of a pre-release version of the HardFloat IEEE Floating-Point Arithmetic Package, by John R. Hauser (with some contributions from Yunsup Lee and Andrew Waterman, mainly concerning testing). Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the University of California. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions, and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions, and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the University nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. =============================================================================/ package hardfloat import chisel3._ import chisel3.util.Fill import consts._ //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- class RoundAnyRawFNToRecFN( inExpWidth: Int, inSigWidth: Int, outExpWidth: Int, outSigWidth: Int, options: Int ) extends RawModule { override def desiredName = s"RoundAnyRawFNToRecFN_ie${inExpWidth}_is${inSigWidth}_oe${outExpWidth}_os${outSigWidth}" val io = IO(new Bundle { val invalidExc = Input(Bool()) // overrides 'infiniteExc' and 'in' val infiniteExc = Input(Bool()) // overrides 'in' except for 'in.sign' val in = Input(new RawFloat(inExpWidth, inSigWidth)) // (allowed exponent range has limits) val roundingMode = Input(UInt(3.W)) val detectTininess = Input(UInt(1.W)) val out = Output(Bits((outExpWidth + outSigWidth + 1).W)) val exceptionFlags = Output(Bits(5.W)) }) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val sigMSBitAlwaysZero = ((options & flRoundOpt_sigMSBitAlwaysZero) != 0) val effectiveInSigWidth = if (sigMSBitAlwaysZero) inSigWidth else inSigWidth + 1 val neverUnderflows = ((options & (flRoundOpt_neverUnderflows \| flRoundOpt_subnormsAlwaysExact) ) != 0) \|\| (inExpWidth < outExpWidth) val neverOverflows = ((options & flRoundOpt_neverOverflows) != 0) \|\| (inExpWidth < outExpWidth) val outNaNExp = BigInt(7)<<(outExpWidth - 2) val outInfExp = BigInt(6)<<(outExpWidth - 2) val outMaxFiniteExp = outInfExp - 1 val outMinNormExp = (BigInt(1)<<(outExpWidth - 1)) + 2 val outMinNonzeroExp = outMinNormExp - outSigWidth + 1 //------------------------------------------------------------------------ //------------------------------------------------------------------------ val roundingMode_near_even = (io.roundingMode === round_near_even) val roundingMode_minMag = (io.roundingMode === round_minMag) val roundingMode_min = (io.roundingMode === round_min) val roundingMode_max = (io.roundingMode === round_max) val roundingMode_near_maxMag = (io.roundingMode === round_near_maxMag) val roundingMode_odd = (io.roundingMode === round_odd) val roundMagUp = (roundingMode_min && io.in.sign) \|\| (roundingMode_max && ! io.in.sign) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val sAdjustedExp = if (inExpWidth < outExpWidth) (io.in.sExp +& ((BigInt(1)<<outExpWidth) - (BigInt(1)<<inExpWidth)).S )(outExpWidth, 0).zext else if (inExpWidth == outExpWidth) io.in.sExp else io.in.sExp +& ((BigInt(1)<<outExpWidth) - (BigInt(1)<<inExpWidth)).S val adjustedSig = if (inSigWidth <= outSigWidth + 2) io.in.sig<<(outSigWidth - inSigWidth + 2) else (io.in.sig(inSigWidth, inSigWidth - outSigWidth - 1) ## io.in.sig(inSigWidth - outSigWidth - 2, 0).orR ) val doShiftSigDown1 = if (sigMSBitAlwaysZero) false.B else adjustedSig(outSigWidth + 2) val common_expOut = Wire(UInt((outExpWidth + 1).W)) val common_fractOut = Wire(UInt((outSigWidth - 1).W)) val common_overflow = Wire(Bool()) val common_totalUnderflow = Wire(Bool()) val common_underflow = Wire(Bool()) val common_inexact = Wire(Bool()) if ( neverOverflows && neverUnderflows && (effectiveInSigWidth <= outSigWidth) ) { //-------------------------------------------------------------------- //-------------------------------------------------------------------- common_expOut := sAdjustedExp(outExpWidth, 0) + doShiftSigDown1 common_fractOut := Mux(doShiftSigDown1, adjustedSig(outSigWidth + 1, 3), adjustedSig(outSigWidth, 2) ) common_overflow := false.B common_totalUnderflow := false.B common_underflow := false.B common_inexact := false.B } else { //-------------------------------------------------------------------- //-------------------------------------------------------------------- val roundMask = if (neverUnderflows) 0.U(outSigWidth.W) ## doShiftSigDown1 ## 3.U(2.W) else (lowMask( sAdjustedExp(outExpWidth, 0), outMinNormExp - outSigWidth - 1, outMinNormExp ) \| doShiftSigDown1) ## 3.U(2.W) val shiftedRoundMask = 0.U(1.W) ## roundMask>>1 val roundPosMask = ~shiftedRoundMask & roundMask val roundPosBit = (adjustedSig & roundPosMask).orR val anyRoundExtra = (adjustedSig & shiftedRoundMask).orR val anyRound = roundPosBit \|\| anyRoundExtra val roundIncr = ((roundingMode_near_even \|\| roundingMode_near_maxMag) && roundPosBit) \|\| (roundMagUp && anyRound) val roundedSig: Bits = Mux(roundIncr, (((adjustedSig \| roundMask)>>2) +& 1.U) & ~Mux(roundingMode_near_even && roundPosBit && ! anyRoundExtra, roundMask>>1, 0.U((outSigWidth + 2).W) ), (adjustedSig & ~roundMask)>>2 \| Mux(roundingMode_odd && anyRound, roundPosMask>>1, 0.U) ) //* IF SIG WIDTH IS VERY NARROW, NEED TO ACCOUNT FOR ROUND-EVEN ZEROING //* M.S. BIT OF SUBNORMAL SIG? val sRoundedExp = sAdjustedExp +& (roundedSig>>outSigWidth).asUInt.zext common_expOut := sRoundedExp(outExpWidth, 0) common_fractOut := Mux(doShiftSigDown1, roundedSig(outSigWidth - 1, 1), roundedSig(outSigWidth - 2, 0) ) common_overflow := (if (neverOverflows) false.B else //* REWRITE BASED ON BEFORE-ROUNDING EXPONENT?: (sRoundedExp>>(outExpWidth - 1) >= 3.S)) common_totalUnderflow := (if (neverUnderflows) false.B else //* WOULD BE GOOD ENOUGH TO USE EXPONENT BEFORE ROUNDING?: (sRoundedExp < outMinNonzeroExp.S)) val unboundedRange_roundPosBit = Mux(doShiftSigDown1, adjustedSig(2), adjustedSig(1)) val unboundedRange_anyRound = (doShiftSigDown1 && adjustedSig(2)) \|\| adjustedSig(1, 0).orR val unboundedRange_roundIncr = ((roundingMode_near_even \|\| roundingMode_near_maxMag) && unboundedRange_roundPosBit) \|\| (roundMagUp && unboundedRange_anyRound) val roundCarry = Mux(doShiftSigDown1, roundedSig(outSigWidth + 1), roundedSig(outSigWidth) ) common_underflow := (if (neverUnderflows) false.B else common_totalUnderflow \|\| //* IF SIG WIDTH IS VERY NARROW, NEED TO ACCOUNT FOR ROUND-EVEN ZEROING //* M.S. BIT OF SUBNORMAL SIG? (anyRound && ((sAdjustedExp>>outExpWidth) <= 0.S) && Mux(doShiftSigDown1, roundMask(3), roundMask(2)) && ! ((io.detectTininess === tininess_afterRounding) && ! Mux(doShiftSigDown1, roundMask(4), roundMask(3) ) && roundCarry && roundPosBit && unboundedRange_roundIncr))) common_inexact := common_totalUnderflow \|\| anyRound } //------------------------------------------------------------------------ //------------------------------------------------------------------------ val isNaNOut = io.invalidExc \|\| io.in.isNaN val notNaN_isSpecialInfOut = io.infiniteExc \|\| io.in.isInf val commonCase = ! isNaNOut && ! notNaN_isSpecialInfOut && ! io.in.isZero val overflow = commonCase && common_overflow val underflow = commonCase && common_underflow val inexact = overflow \|\| (commonCase && common_inexact) val overflow_roundMagUp = roundingMode_near_even \|\| roundingMode_near_maxMag \|\| roundMagUp val pegMinNonzeroMagOut = commonCase && common_totalUnderflow && (roundMagUp \|\| roundingMode_odd) val pegMaxFiniteMagOut = overflow && ! overflow_roundMagUp val notNaN_isInfOut = notNaN_isSpecialInfOut \|\| (overflow && overflow_roundMagUp) val signOut = Mux(isNaNOut, false.B, io.in.sign) val expOut = (common_expOut & ~Mux(io.in.isZero \|\| common_totalUnderflow, (BigInt(7)<<(outExpWidth - 2)).U((outExpWidth + 1).W), 0.U ) & ~Mux(pegMinNonzeroMagOut, ~outMinNonzeroExp.U((outExpWidth + 1).W), 0.U ) & ~Mux(pegMaxFiniteMagOut, (BigInt(1)<<(outExpWidth - 1)).U((outExpWidth + 1).W), 0.U ) & ~Mux(notNaN_isInfOut, (BigInt(1)<<(outExpWidth - 2)).U((outExpWidth + 1).W), 0.U )) \| Mux(pegMinNonzeroMagOut, outMinNonzeroExp.U((outExpWidth + 1).W), 0.U ) \| Mux(pegMaxFiniteMagOut, outMaxFiniteExp.U((outExpWidth + 1).W), 0.U ) \| Mux(notNaN_isInfOut, outInfExp.U((outExpWidth + 1).W), 0.U) \| Mux(isNaNOut, outNaNExp.U((outExpWidth + 1).W), 0.U) val fractOut = Mux(isNaNOut \|\| io.in.isZero \|\| common_totalUnderflow, Mux(isNaNOut, (BigInt(1)<<(outSigWidth - 2)).U, 0.U), common_fractOut ) \| Fill(outSigWidth - 1, pegMaxFiniteMagOut) io.out := signOut ## expOut ## fractOut io.exceptionFlags := io.invalidExc ## io.infiniteExc ## overflow ## underflow ## inexact } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- class RoundRawFNToRecFN(expWidth: Int, sigWidth: Int, options: Int) extends RawModule { override def desiredName = s"RoundRawFNToRecFN_e${expWidth}_s${sigWidth}" val io = IO(new Bundle { val invalidExc = Input(Bool()) // overrides 'infiniteExc' and 'in' val infiniteExc = Input(Bool()) // overrides 'in' except for 'in.sign' val in = Input(new RawFloat(expWidth, sigWidth + 2)) val roundingMode = Input(UInt(3.W)) val detectTininess = Input(UInt(1.W)) val out = Output(Bits((expWidth + sigWidth + 1).W)) val exceptionFlags = Output(Bits(5.W)) }) val roundAnyRawFNToRecFN = Module( new RoundAnyRawFNToRecFN( expWidth, sigWidth + 2, expWidth, sigWidth, options)) roundAnyRawFNToRecFN.io.invalidExc := io.invalidExc roundAnyRawFNToRecFN.io.infiniteExc := io.infiniteExc roundAnyRawFNToRecFN.io.in := io.in roundAnyRawFNToRecFN.io.roundingMode := io.roundingMode roundAnyRawFNToRecFN.io.detectTininess := io.detectTininess io.out := roundAnyRawFNToRecFN.io.out io.exceptionFlags := roundAnyRawFNToRecFN.io.exceptionFlags }	module RoundRawFNToRecFN_e8_s24_125( // @[RoundAnyRawFNToRecFN.scala:295:5] input io_invalidExc, // @[RoundAnyRawFNToRecFN.scala:299:16] input io_in_isNaN, // @[RoundAnyRawFNToRecFN.scala:299:16] input io_in_isInf, // @[RoundAnyRawFNToRecFN.scala:299:16] input io_in_isZero, // @[RoundAnyRawFNToRecFN.scala:299:16] input io_in_sign, // @[RoundAnyRawFNToRecFN.scala:299:16] input [9:0] io_in_sExp, // @[RoundAnyRawFNToRecFN.scala:299:16] input [26:0] io_in_sig, // @[RoundAnyRawFNToRecFN.scala:299:16] output [32:0] io_out, // @[RoundAnyRawFNToRecFN.scala:299:16] output [4:0] io_exceptionFlags // @[RoundAnyRawFNToRecFN.scala:299:16] ); wire io_invalidExc_0 = io_invalidExc; // @[RoundAnyRawFNToRecFN.scala:295:5] wire io_in_isNaN_0 = io_in_isNaN; // @[RoundAnyRawFNToRecFN.scala:295:5] wire io_in_isInf_0 = io_in_isInf; // @[RoundAnyRawFNToRecFN.scala:295:5] wire io_in_isZero_0 = io_in_isZero; // @[RoundAnyRawFNToRecFN.scala:295:5] wire io_in_sign_0 = io_in_sign; // @[RoundAnyRawFNToRecFN.scala:295:5] wire [9:0] io_in_sExp_0 = io_in_sExp; // @[RoundAnyRawFNToRecFN.scala:295:5] wire [26:0] io_in_sig_0 = io_in_sig; // @[RoundAnyRawFNToRecFN.scala:295:5] wire io_detectTininess = 1'h1; // @[RoundAnyRawFNToRecFN.scala:295:5, :299:16, :310:15] wire [2:0] io_roundingMode = 3'h0; // @[RoundAnyRawFNToRecFN.scala:295:5, :299:16, :310:15] wire io_infiniteExc = 1'h0; // @[RoundAnyRawFNToRecFN.scala:295:5, :299:16, :310:15] wire [32:0] io_out_0; // @[RoundAnyRawFNToRecFN.scala:295:5] wire [4:0] io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:295:5] RoundAnyRawFNToRecFN_ie8_is26_oe8_os24_125 roundAnyRawFNToRecFN ( // @[RoundAnyRawFNToRecFN.scala:310:15] .io_invalidExc (io_invalidExc_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_isNaN (io_in_isNaN_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_isInf (io_in_isInf_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_isZero (io_in_isZero_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_sign (io_in_sign_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_sExp (io_in_sExp_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_sig (io_in_sig_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_out (io_out_0), .io_exceptionFlags (io_exceptionFlags_0) ); // @[RoundAnyRawFNToRecFN.scala:310:15] assign io_out = io_out_0; // @[RoundAnyRawFNToRecFN.scala:295:5] assign io_exceptionFlags = io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:295:5] endmodule
Generate the Verilog code corresponding to the following Chisel files. File Tile.scala: // See README.md for license details. package gemmini import chisel3._ import chisel3.util._ import Util._ /** * A Tile is a purely combinational 2D array of passThrough PEs. * a, b, s, and in_propag are broadcast across the entire array and are passed through to the Tile's outputs * @param width The data width of each PE in bits * @param rows Number of PEs on each row * @param columns Number of PEs on each column */ class Tile[T <: Data](inputType: T, outputType: T, accType: T, df: Dataflow.Value, tree_reduction: Boolean, max_simultaneous_matmuls: Int, val rows: Int, val columns: Int)(implicit ev: Arithmetic[T]) extends Module { val io = IO(new Bundle { val in_a = Input(Vec(rows, inputType)) val in_b = Input(Vec(columns, outputType)) // This is the output of the tile next to it val in_d = Input(Vec(columns, outputType)) val in_control = Input(Vec(columns, new PEControl(accType))) val in_id = Input(Vec(columns, UInt(log2Up(max_simultaneous_matmuls).W))) val in_last = Input(Vec(columns, Bool())) val out_a = Output(Vec(rows, inputType)) val out_c = Output(Vec(columns, outputType)) val out_b = Output(Vec(columns, outputType)) val out_control = Output(Vec(columns, new PEControl(accType))) val out_id = Output(Vec(columns, UInt(log2Up(max_simultaneous_matmuls).W))) val out_last = Output(Vec(columns, Bool())) val in_valid = Input(Vec(columns, Bool())) val out_valid = Output(Vec(columns, Bool())) val bad_dataflow = Output(Bool()) }) import ev._ val tile = Seq.fill(rows, columns)(Module(new PE(inputType, outputType, accType, df, max_simultaneous_matmuls))) val tileT = tile.transpose // TODO: abstract hori/vert broadcast, all these connections look the same // Broadcast 'a' horizontally across the Tile for (r <- 0 until rows) { tile(r).foldLeft(io.in_a(r)) { case (in_a, pe) => pe.io.in_a := in_a pe.io.out_a } } // Broadcast 'b' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_b(c)) { case (in_b, pe) => pe.io.in_b := (if (tree_reduction) in_b.zero else in_b) pe.io.out_b } } // Broadcast 'd' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_d(c)) { case (in_d, pe) => pe.io.in_d := in_d pe.io.out_c } } // Broadcast 'control' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_control(c)) { case (in_ctrl, pe) => pe.io.in_control := in_ctrl pe.io.out_control } } // Broadcast 'garbage' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_valid(c)) { case (v, pe) => pe.io.in_valid := v pe.io.out_valid } } // Broadcast 'id' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_id(c)) { case (id, pe) => pe.io.in_id := id pe.io.out_id } } // Broadcast 'last' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_last(c)) { case (last, pe) => pe.io.in_last := last pe.io.out_last } } // Drive the Tile's bottom IO for (c <- 0 until columns) { io.out_c(c) := tile(rows-1)(c).io.out_c io.out_control(c) := tile(rows-1)(c).io.out_control io.out_id(c) := tile(rows-1)(c).io.out_id io.out_last(c) := tile(rows-1)(c).io.out_last io.out_valid(c) := tile(rows-1)(c).io.out_valid io.out_b(c) := { if (tree_reduction) { val prods = tileT(c).map(_.io.out_b) accumulateTree(prods :+ io.in_b(c)) } else { tile(rows - 1)(c).io.out_b } } } io.bad_dataflow := tile.map(_.map(_.io.bad_dataflow).reduce(_\|\|_)).reduce(_\|\|_) // Drive the Tile's right IO for (r <- 0 until rows) { io.out_a(r) := tile(r)(columns-1).io.out_a } }	module Tile_201( // @[Tile.scala:16:7] input clock, // @[Tile.scala:16:7] input reset, // @[Tile.scala:16:7] input [7:0] io_in_a_0, // @[Tile.scala:17:14] input [19:0] io_in_b_0, // @[Tile.scala:17:14] input [19:0] io_in_d_0, // @[Tile.scala:17:14] input io_in_control_0_dataflow, // @[Tile.scala:17:14] input io_in_control_0_propagate, // @[Tile.scala:17:14] input [4:0] io_in_control_0_shift, // @[Tile.scala:17:14] input [2:0] io_in_id_0, // @[Tile.scala:17:14] input io_in_last_0, // @[Tile.scala:17:14] output [7:0] io_out_a_0, // @[Tile.scala:17:14] output [19:0] io_out_c_0, // @[Tile.scala:17:14] output [19:0] io_out_b_0, // @[Tile.scala:17:14] output io_out_control_0_dataflow, // @[Tile.scala:17:14] output io_out_control_0_propagate, // @[Tile.scala:17:14] output [4:0] io_out_control_0_shift, // @[Tile.scala:17:14] output [2:0] io_out_id_0, // @[Tile.scala:17:14] output io_out_last_0, // @[Tile.scala:17:14] input io_in_valid_0, // @[Tile.scala:17:14] output io_out_valid_0 // @[Tile.scala:17:14] ); wire [7:0] io_in_a_0_0 = io_in_a_0; // @[Tile.scala:16:7] wire [19:0] io_in_b_0_0 = io_in_b_0; // @[Tile.scala:16:7] wire [19:0] io_in_d_0_0 = io_in_d_0; // @[Tile.scala:16:7] wire io_in_control_0_dataflow_0 = io_in_control_0_dataflow; // @[Tile.scala:16:7] wire io_in_control_0_propagate_0 = io_in_control_0_propagate; // @[Tile.scala:16:7] wire [4:0] io_in_control_0_shift_0 = io_in_control_0_shift; // @[Tile.scala:16:7] wire [2:0] io_in_id_0_0 = io_in_id_0; // @[Tile.scala:16:7] wire io_in_last_0_0 = io_in_last_0; // @[Tile.scala:16:7] wire io_in_valid_0_0 = io_in_valid_0; // @[Tile.scala:16:7] wire io_bad_dataflow = 1'h0; // @[Tile.scala:16:7, :17:14, :42:44] wire [7:0] io_out_a_0_0; // @[Tile.scala:16:7] wire [19:0] io_out_c_0_0; // @[Tile.scala:16:7] wire [19:0] io_out_b_0_0; // @[Tile.scala:16:7] wire io_out_control_0_dataflow_0; // @[Tile.scala:16:7] wire io_out_control_0_propagate_0; // @[Tile.scala:16:7] wire [4:0] io_out_control_0_shift_0; // @[Tile.scala:16:7] wire [2:0] io_out_id_0_0; // @[Tile.scala:16:7] wire io_out_last_0_0; // @[Tile.scala:16:7] wire io_out_valid_0_0; // @[Tile.scala:16:7] PE_457 tile_0_0 ( // @[Tile.scala:42:44] .clock (clock), .reset (reset), .io_in_a (io_in_a_0_0), // @[Tile.scala:16:7] .io_in_b (io_in_b_0_0), // @[Tile.scala:16:7] .io_in_d (io_in_d_0_0), // @[Tile.scala:16:7] .io_out_a (io_out_a_0_0), .io_out_b (io_out_b_0_0), .io_out_c (io_out_c_0_0), .io_in_control_dataflow (io_in_control_0_dataflow_0), // @[Tile.scala:16:7] .io_in_control_propagate (io_in_control_0_propagate_0), // @[Tile.scala:16:7] .io_in_control_shift (io_in_control_0_shift_0), // @[Tile.scala:16:7] .io_out_control_dataflow (io_out_control_0_dataflow_0), .io_out_control_propagate (io_out_control_0_propagate_0), .io_out_control_shift (io_out_control_0_shift_0), .io_in_id (io_in_id_0_0), // @[Tile.scala:16:7] .io_out_id (io_out_id_0_0), .io_in_last (io_in_last_0_0), // @[Tile.scala:16:7] .io_out_last (io_out_last_0_0), .io_in_valid (io_in_valid_0_0), // @[Tile.scala:16:7] .io_out_valid (io_out_valid_0_0) ); // @[Tile.scala:42:44] assign io_out_a_0 = io_out_a_0_0; // @[Tile.scala:16:7] assign io_out_c_0 = io_out_c_0_0; // @[Tile.scala:16:7] assign io_out_b_0 = io_out_b_0_0; // @[Tile.scala:16:7] assign io_out_control_0_dataflow = io_out_control_0_dataflow_0; // @[Tile.scala:16:7] assign io_out_control_0_propagate = io_out_control_0_propagate_0; // @[Tile.scala:16:7] assign io_out_control_0_shift = io_out_control_0_shift_0; // @[Tile.scala:16:7] assign io_out_id_0 = io_out_id_0_0; // @[Tile.scala:16:7] assign io_out_last_0 = io_out_last_0_0; // @[Tile.scala:16:7] assign io_out_valid_0 = io_out_valid_0_0; // @[Tile.scala:16:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File PMA.scala: // See LICENSE.SiFive for license details. // See LICENSE.Berkeley for license details. package freechips.rocketchip.rocket import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config._ import freechips.rocketchip.devices.debug.DebugModuleKey import freechips.rocketchip.diplomacy.RegionType import freechips.rocketchip.subsystem.CacheBlockBytes import freechips.rocketchip.tile.{CoreModule, CoreBundle} import freechips.rocketchip.tilelink.{TLSlavePortParameters, TLManagerParameters} class PMAChecker(manager: TLSlavePortParameters)(implicit p: Parameters) extends CoreModule()(p) { val io = IO(new Bundle { val paddr = Input(UInt()) val resp = Output(new Bundle { val cacheable = Bool() val r = Bool() val w = Bool() val pp = Bool() val al = Bool() val aa = Bool() val x = Bool() val eff = Bool() }) }) // PMA // check exist a slave can consume this address. val legal_address = manager.findSafe(io.paddr).reduce(_\|\|_) // check utility to help check SoC property. def fastCheck(member: TLManagerParameters => Boolean) = legal_address && manager.fastProperty(io.paddr, member, (b:Boolean) => b.B) io.resp.cacheable := fastCheck(_.supportsAcquireB) io.resp.r := fastCheck(_.supportsGet) io.resp.w := fastCheck(_.supportsPutFull) io.resp.pp := fastCheck(_.supportsPutPartial) io.resp.al := fastCheck(_.supportsLogical) io.resp.aa := fastCheck(_.supportsArithmetic) io.resp.x := fastCheck(_.executable) io.resp.eff := fastCheck(Seq(RegionType.PUT_EFFECTS, RegionType.GET_EFFECTS) contains _.regionType) } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.diplomacy import chisel3._ import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor} import freechips.rocketchip.util.ShiftQueue /** Options for describing the attributes of memory regions */ object RegionType { // Define the 'more relaxed than' ordering val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS) sealed trait T extends Ordered[T] { def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this) } case object CACHED extends T // an intermediate agent may have cached a copy of the region for you case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively } // A non-empty half-open range; [start, end) case class IdRange(start: Int, end: Int) extends Ordered[IdRange] { require (start >= 0, s"Ids cannot be negative, but got: $start.") require (start <= end, "Id ranges cannot be negative.") def compare(x: IdRange) = { val primary = (this.start - x.start).signum val secondary = (x.end - this.end).signum if (primary != 0) primary else secondary } def overlaps(x: IdRange) = start < x.end && x.start < end def contains(x: IdRange) = start <= x.start && x.end <= end def contains(x: Int) = start <= x && x < end def contains(x: UInt) = if (size == 0) { false.B } else if (size == 1) { // simple comparison x === start.U } else { // find index of largest different bit val largestDeltaBit = log2Floor(start ^ (end-1)) val smallestCommonBit = largestDeltaBit + 1 // may not exist in x val uncommonMask = (1 << smallestCommonBit) - 1 val uncommonBits = (x \| 0.U(smallestCommonBit.W))(largestDeltaBit, 0) // the prefix must match exactly (note: may shift ALL bits away) (x >> smallestCommonBit) === (start >> smallestCommonBit).U && // firrtl constant prop range analysis can eliminate these two: (start & uncommonMask).U <= uncommonBits && uncommonBits <= ((end-1) & uncommonMask).U } def shift(x: Int) = IdRange(start+x, end+x) def size = end - start def isEmpty = end == start def range = start until end } object IdRange { def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else { val ranges = s.sorted (ranges.tail zip ranges.init) find { case (a, b) => a overlaps b } } } // An potentially empty inclusive range of 2-powers [min, max] (in bytes) case class TransferSizes(min: Int, max: Int) { def this(x: Int) = this(x, x) require (min <= max, s"Min transfer $min > max transfer $max") require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)") require (max == 0 \|\| isPow2(max), s"TransferSizes must be a power of 2, got: $max") require (min == 0 \|\| isPow2(min), s"TransferSizes must be a power of 2, got: $min") require (max == 0 \|\| min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)") def none = min == 0 def contains(x: Int) = isPow2(x) && min <= x && x <= max def containsLg(x: Int) = contains(1 << x) def containsLg(x: UInt) = if (none) false.B else if (min == max) { log2Ceil(min).U === x } else { log2Ceil(min).U <= x && x <= log2Ceil(max).U } def contains(x: TransferSizes) = x.none \|\| (min <= x.min && x.max <= max) def intersect(x: TransferSizes) = if (x.max < min \|\| max < x.min) TransferSizes.none else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max)) // Not a union, because the result may contain sizes contained by neither term // NOT TO BE CONFUSED WITH COVERPOINTS def mincover(x: TransferSizes) = { if (none) { x } else if (x.none) { this } else { TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max)) } } override def toString() = "TransferSizes[%d, %d]".format(min, max) } object TransferSizes { def apply(x: Int) = new TransferSizes(x) val none = new TransferSizes(0) def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _) def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _) implicit def asBool(x: TransferSizes) = !x.none } // AddressSets specify the address space managed by the manager // Base is the base address, and mask are the bits consumed by the manager // e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff // e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ... case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet] { // Forbid misaligned base address (and empty sets) require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}") require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous // We do allow negative mask (=> ignore all high bits) def contains(x: BigInt) = ((x ^ base) & ~mask) == 0 def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S // turn x into an address contained in this set def legalize(x: UInt): UInt = base.U \| (mask.U & x) // overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1) def overlaps(x: AddressSet) = (~(mask \| x.mask) & (base ^ x.base)) == 0 // contains iff bitwise: x.mask => mask && contains(x.base) def contains(x: AddressSet) = ((x.mask \| (base ^ x.base)) & ~mask) == 0 // The number of bytes to which the manager must be aligned def alignment = ((mask + 1) & ~mask) // Is this a contiguous memory range def contiguous = alignment == mask+1 def finite = mask >= 0 def max = { require (finite, "Max cannot be calculated on infinite mask"); base \| mask } // Widen the match function to ignore all bits in imask def widen(imask: BigInt) = AddressSet(base & ~imask, mask \| imask) // Return an AddressSet that only contains the addresses both sets contain def intersect(x: AddressSet): Option[AddressSet] = { if (!overlaps(x)) { None } else { val r_mask = mask & x.mask val r_base = base \| x.base Some(AddressSet(r_base, r_mask)) } } def subtract(x: AddressSet): Seq[AddressSet] = { intersect(x) match { case None => Seq(this) case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit => val nmask = (mask & (bit-1)) \| remove.mask val nbase = (remove.base ^ bit) & ~nmask AddressSet(nbase, nmask) } } } // AddressSets have one natural Ordering (the containment order, if contiguous) def compare(x: AddressSet) = { val primary = (this.base - x.base).signum // smallest address first val secondary = (x.mask - this.mask).signum // largest mask first if (primary != 0) primary else secondary } // We always want to see things in hex override def toString() = { if (mask >= 0) { "AddressSet(0x%x, 0x%x)".format(base, mask) } else { "AddressSet(0x%x, ~0x%x)".format(base, ~mask) } } def toRanges = { require (finite, "Ranges cannot be calculated on infinite mask") val size = alignment val fragments = mask & ~(size-1) val bits = bitIndexes(fragments) (BigInt(0) until (BigInt(1) << bits.size)).map { i => val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) } AddressRange(off, size) } } } object AddressSet { val everything = AddressSet(0, -1) def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = { if (size == 0) tail.reverse else { val maxBaseAlignment = base & (-base) // 0 for infinite (LSB) val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size val step = if (maxBaseAlignment == 0 \|\| maxBaseAlignment > maxSizeAlignment) maxSizeAlignment else maxBaseAlignment misaligned(base+step, size-step, AddressSet(base, step-1) +: tail) } } def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = { // Pair terms up by ignoring 'bit' seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) => if (seq.size == 1) { seq.head // singleton -> unaffected } else { key.copy(mask = key.mask \| bit) // pair - widen mask by bit } }.toList } def unify(seq: Seq[AddressSet]): Seq[AddressSet] = { val bits = seq.map(_.base).foldLeft(BigInt(0))(_ \| _) AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted } def enumerateMask(mask: BigInt): Seq[BigInt] = { def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] = if (id == mask) (id +: tail).reverse else helper(((~mask \| id) + 1) & mask, id +: tail) helper(0, Nil) } def enumerateBits(mask: BigInt): Seq[BigInt] = { def helper(x: BigInt): Seq[BigInt] = { if (x == 0) { Nil } else { val bit = x & (-x) bit +: helper(x & ~bit) } } helper(mask) } } case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean) { require (depth >= 0, "Buffer depth must be >= 0") def isDefined = depth > 0 def latency = if (isDefined && !flow) 1 else 0 def apply[T <: Data](x: DecoupledIO[T]) = if (isDefined) Queue(x, depth, flow=flow, pipe=pipe) else x def irrevocable[T <: Data](x: ReadyValidIO[T]) = if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe) else x def sq[T <: Data](x: DecoupledIO[T]) = if (!isDefined) x else { val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe)) sq.io.enq <> x sq.io.deq } override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "") } object BufferParams { implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false) val default = BufferParams(2) val none = BufferParams(0) val flow = BufferParams(1, true, false) val pipe = BufferParams(1, false, true) } case class TriStateValue(value: Boolean, set: Boolean) { def update(orig: Boolean) = if (set) value else orig } object TriStateValue { implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true) def unset = TriStateValue(false, false) } trait DirectedBuffers[T] { def copyIn(x: BufferParams): T def copyOut(x: BufferParams): T def copyInOut(x: BufferParams): T } trait IdMapEntry { def name: String def from: IdRange def to: IdRange def isCache: Boolean def requestFifo: Boolean def maxTransactionsInFlight: Option[Int] def pretty(fmt: String) = if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5 fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } else { fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } } abstract class IdMap[T <: IdMapEntry] { protected val fmt: String val mapping: Seq[T] def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n") }	module PMAChecker_1( // @[PMA.scala:18:7] input clock, // @[PMA.scala:18:7] input reset, // @[PMA.scala:18:7] input [33:0] io_paddr, // @[PMA.scala:19:14] output io_resp_r, // @[PMA.scala:19:14] output io_resp_w, // @[PMA.scala:19:14] output io_resp_pp, // @[PMA.scala:19:14] output io_resp_al, // @[PMA.scala:19:14] output io_resp_aa, // @[PMA.scala:19:14] output io_resp_x, // @[PMA.scala:19:14] output io_resp_eff // @[PMA.scala:19:14] ); wire [33:0] io_paddr_0 = io_paddr; // @[PMA.scala:18:7] wire [34:0] _io_resp_cacheable_T_2 = 35'h0; // @[Parameters.scala:137:46] wire [34:0] _io_resp_cacheable_T_3 = 35'h0; // @[Parameters.scala:137:46] wire [34:0] _io_resp_r_T_2 = 35'h0; // @[Parameters.scala:137:46] wire [34:0] _io_resp_r_T_3 = 35'h0; // @[Parameters.scala:137:46] wire _io_resp_cacheable_T_4 = 1'h1; // @[Parameters.scala:137:59] wire _io_resp_r_T_4 = 1'h1; // @[Parameters.scala:137:59] wire io_resp_cacheable = 1'h0; // @[PMA.scala:18:7] wire _io_resp_cacheable_T_5 = 1'h0; // @[PMA.scala:39:19] wire _io_resp_w_T_29 = 1'h0; // @[Mux.scala:30:73] wire _io_resp_pp_T_29 = 1'h0; // @[Mux.scala:30:73] wire _io_resp_al_T_29 = 1'h0; // @[Mux.scala:30:73] wire _io_resp_aa_T_29 = 1'h0; // @[Mux.scala:30:73] wire _io_resp_x_T_59 = 1'h0; // @[Mux.scala:30:73] wire _io_resp_eff_T_47 = 1'h0; // @[Mux.scala:30:73] wire [33:0] _legal_address_T = io_paddr_0; // @[PMA.scala:18:7] wire [33:0] _io_resp_cacheable_T = io_paddr_0; // @[PMA.scala:18:7] wire [33:0] _io_resp_r_T = io_paddr_0; // @[PMA.scala:18:7] wire [33:0] _io_resp_w_T = io_paddr_0; // @[PMA.scala:18:7] wire [33:0] _io_resp_pp_T = io_paddr_0; // @[PMA.scala:18:7] wire [33:0] _io_resp_al_T = io_paddr_0; // @[PMA.scala:18:7] wire [33:0] _io_resp_aa_T = io_paddr_0; // @[PMA.scala:18:7] wire [33:0] _io_resp_x_T = io_paddr_0; // @[PMA.scala:18:7] wire [33:0] _io_resp_eff_T = io_paddr_0; // @[PMA.scala:18:7] wire _io_resp_r_T_5; // @[PMA.scala:39:19] wire _io_resp_w_T_31; // @[PMA.scala:39:19] wire _io_resp_pp_T_31; // @[PMA.scala:39:19] wire _io_resp_al_T_31; // @[PMA.scala:39:19] wire _io_resp_aa_T_31; // @[PMA.scala:39:19] wire _io_resp_x_T_61; // @[PMA.scala:39:19] wire _io_resp_eff_T_49; // @[PMA.scala:39:19] wire io_resp_r_0; // @[PMA.scala:18:7] wire io_resp_w_0; // @[PMA.scala:18:7] wire io_resp_pp_0; // @[PMA.scala:18:7] wire io_resp_al_0; // @[PMA.scala:18:7] wire io_resp_aa_0; // @[PMA.scala:18:7] wire io_resp_x_0; // @[PMA.scala:18:7] wire io_resp_eff_0; // @[PMA.scala:18:7] wire [34:0] _legal_address_T_1 = {1'h0, _legal_address_T}; // @[Parameters.scala:137:{31,41}] wire [34:0] _legal_address_T_2 = _legal_address_T_1 & 35'h7FFFFF000; // @[Parameters.scala:137:{41,46}] wire [34:0] _legal_address_T_3 = _legal_address_T_2; // @[Parameters.scala:137:46] wire _legal_address_T_4 = _legal_address_T_3 == 35'h0; // @[Parameters.scala:137:{46,59}] wire _legal_address_WIRE_0 = _legal_address_T_4; // @[Parameters.scala:612:40] wire [33:0] _GEN = {io_paddr_0[33:13], io_paddr_0[12:0] ^ 13'h1000}; // @[PMA.scala:18:7] wire [33:0] _legal_address_T_5; // @[Parameters.scala:137:31] assign _legal_address_T_5 = _GEN; // @[Parameters.scala:137:31] wire [33:0] _io_resp_x_T_29; // @[Parameters.scala:137:31] assign _io_resp_x_T_29 = _GEN; // @[Parameters.scala:137:31] wire [34:0] _legal_address_T_6 = {1'h0, _legal_address_T_5}; // @[Parameters.scala:137:{31,41}] wire [34:0] _legal_address_T_7 = _legal_address_T_6 & 35'h7FFFFF000; // @[Parameters.scala:137:{41,46}] wire [34:0] _legal_address_T_8 = _legal_address_T_7; // @[Parameters.scala:137:46] wire _legal_address_T_9 = _legal_address_T_8 == 35'h0; // @[Parameters.scala:137:{46,59}] wire _legal_address_WIRE_1 = _legal_address_T_9; // @[Parameters.scala:612:40] wire [33:0] _GEN_0 = {io_paddr_0[33:14], io_paddr_0[13:0] ^ 14'h3000}; // @[PMA.scala:18:7] wire [33:0] _legal_address_T_10; // @[Parameters.scala:137:31] assign _legal_address_T_10 = _GEN_0; // @[Parameters.scala:137:31] wire [33:0] _io_resp_x_T_5; // @[Parameters.scala:137:31] assign _io_resp_x_T_5 = _GEN_0; // @[Parameters.scala:137:31] wire [33:0] _io_resp_eff_T_29; // @[Parameters.scala:137:31] assign _io_resp_eff_T_29 = _GEN_0; // @[Parameters.scala:137:31] wire [34:0] _legal_address_T_11 = {1'h0, _legal_address_T_10}; // @[Parameters.scala:137:{31,41}] wire [34:0] _legal_address_T_12 = _legal_address_T_11 & 35'h7FFFFF000; // @[Parameters.scala:137:{41,46}] wire [34:0] _legal_address_T_13 = _legal_address_T_12; // @[Parameters.scala:137:46] wire _legal_address_T_14 = _legal_address_T_13 == 35'h0; // @[Parameters.scala:137:{46,59}] wire _legal_address_WIRE_2 = _legal_address_T_14; // @[Parameters.scala:612:40] wire [33:0] _GEN_1 = {io_paddr_0[33:17], io_paddr_0[16:0] ^ 17'h10000}; // @[PMA.scala:18:7] wire [33:0] _legal_address_T_15; // @[Parameters.scala:137:31] assign _legal_address_T_15 = _GEN_1; // @[Parameters.scala:137:31] wire [33:0] _io_resp_w_T_23; // @[Parameters.scala:137:31] assign _io_resp_w_T_23 = _GEN_1; // @[Parameters.scala:137:31] wire [33:0] _io_resp_pp_T_23; // @[Parameters.scala:137:31] assign _io_resp_pp_T_23 = _GEN_1; // @[Parameters.scala:137:31] wire [33:0] _io_resp_al_T_17; // @[Parameters.scala:137:31] assign _io_resp_al_T_17 = _GEN_1; // @[Parameters.scala:137:31] wire [33:0] _io_resp_aa_T_17; // @[Parameters.scala:137:31] assign _io_resp_aa_T_17 = _GEN_1; // @[Parameters.scala:137:31] wire [33:0] _io_resp_x_T_10; // @[Parameters.scala:137:31] assign _io_resp_x_T_10 = _GEN_1; // @[Parameters.scala:137:31] wire [33:0] _io_resp_eff_T_34; // @[Parameters.scala:137:31] assign _io_resp_eff_T_34 = _GEN_1; // @[Parameters.scala:137:31] wire [34:0] _legal_address_T_16 = {1'h0, _legal_address_T_15}; // @[Parameters.scala:137:{31,41}] wire [34:0] _legal_address_T_17 = _legal_address_T_16 & 35'h7FFFF0000; // @[Parameters.scala:137:{41,46}] wire [34:0] _legal_address_T_18 = _legal_address_T_17; // @[Parameters.scala:137:46] wire _legal_address_T_19 = _legal_address_T_18 == 35'h0; // @[Parameters.scala:137:{46,59}] wire _legal_address_WIRE_3 = _legal_address_T_19; // @[Parameters.scala:612:40] wire [33:0] _GEN_2 = {io_paddr_0[33:21], io_paddr_0[20:0] ^ 21'h100000}; // @[PMA.scala:18:7] wire [33:0] _legal_address_T_20; // @[Parameters.scala:137:31] assign _legal_address_T_20 = _GEN_2; // @[Parameters.scala:137:31] wire [33:0] _io_resp_w_T_5; // @[Parameters.scala:137:31] assign _io_resp_w_T_5 = _GEN_2; // @[Parameters.scala:137:31] wire [33:0] _io_resp_pp_T_5; // @[Parameters.scala:137:31] assign _io_resp_pp_T_5 = _GEN_2; // @[Parameters.scala:137:31] wire [33:0] _io_resp_al_T_5; // @[Parameters.scala:137:31] assign _io_resp_al_T_5 = _GEN_2; // @[Parameters.scala:137:31] wire [33:0] _io_resp_aa_T_5; // @[Parameters.scala:137:31] assign _io_resp_aa_T_5 = _GEN_2; // @[Parameters.scala:137:31] wire [33:0] _io_resp_x_T_34; // @[Parameters.scala:137:31] assign _io_resp_x_T_34 = _GEN_2; // @[Parameters.scala:137:31] wire [33:0] _io_resp_eff_T_5; // @[Parameters.scala:137:31] assign _io_resp_eff_T_5 = _GEN_2; // @[Parameters.scala:137:31] wire [34:0] _legal_address_T_21 = {1'h0, _legal_address_T_20}; // @[Parameters.scala:137:{31,41}] wire [34:0] _legal_address_T_22 = _legal_address_T_21 & 35'h7FFFFF000; // @[Parameters.scala:137:{41,46}] wire [34:0] _legal_address_T_23 = _legal_address_T_22; // @[Parameters.scala:137:46] wire _legal_address_T_24 = _legal_address_T_23 == 35'h0; // @[Parameters.scala:137:{46,59}] wire _legal_address_WIRE_4 = _legal_address_T_24; // @[Parameters.scala:612:40] wire [33:0] _legal_address_T_25 = {io_paddr_0[33:21], io_paddr_0[20:0] ^ 21'h110000}; // @[PMA.scala:18:7] wire [34:0] _legal_address_T_26 = {1'h0, _legal_address_T_25}; // @[Parameters.scala:137:{31,41}] wire [34:0] _legal_address_T_27 = _legal_address_T_26 & 35'h7FFFFF000; // @[Parameters.scala:137:{41,46}] wire [34:0] _legal_address_T_28 = _legal_address_T_27; // @[Parameters.scala:137:46] wire _legal_address_T_29 = _legal_address_T_28 == 35'h0; // @[Parameters.scala:137:{46,59}] wire _legal_address_WIRE_5 = _legal_address_T_29; // @[Parameters.scala:612:40] wire [33:0] _GEN_3 = {io_paddr_0[33:26], io_paddr_0[25:0] ^ 26'h2000000}; // @[PMA.scala:18:7] wire [33:0] _legal_address_T_30; // @[Parameters.scala:137:31] assign _legal_address_T_30 = _GEN_3; // @[Parameters.scala:137:31] wire [33:0] _io_resp_x_T_39; // @[Parameters.scala:137:31] assign _io_resp_x_T_39 = _GEN_3; // @[Parameters.scala:137:31] wire [33:0] _io_resp_eff_T_10; // @[Parameters.scala:137:31] assign _io_resp_eff_T_10 = _GEN_3; // @[Parameters.scala:137:31] wire [34:0] _legal_address_T_31 = {1'h0, _legal_address_T_30}; // @[Parameters.scala:137:{31,41}] wire [34:0] _legal_address_T_32 = _legal_address_T_31 & 35'h7FFFF0000; // @[Parameters.scala:137:{41,46}] wire [34:0] _legal_address_T_33 = _legal_address_T_32; // @[Parameters.scala:137:46] wire _legal_address_T_34 = _legal_address_T_33 == 35'h0; // @[Parameters.scala:137:{46,59}] wire _legal_address_WIRE_6 = _legal_address_T_34; // @[Parameters.scala:612:40] wire [33:0] _legal_address_T_35 = {io_paddr_0[33:28], io_paddr_0[27:0] ^ 28'hC000000}; // @[PMA.scala:18:7] wire [34:0] _legal_address_T_36 = {1'h0, _legal_address_T_35}; // @[Parameters.scala:137:{31,41}] wire [34:0] _legal_address_T_37 = _legal_address_T_36 & 35'h7FC000000; // @[Parameters.scala:137:{41,46}] wire [34:0] _legal_address_T_38 = _legal_address_T_37; // @[Parameters.scala:137:46] wire _legal_address_T_39 = _legal_address_T_38 == 35'h0; // @[Parameters.scala:137:{46,59}] wire _legal_address_WIRE_7 = _legal_address_T_39; // @[Parameters.scala:612:40] wire [33:0] _legal_address_T_40 = {io_paddr_0[33:29], io_paddr_0[28:0] ^ 29'h10020000}; // @[PMA.scala:18:7] wire [34:0] _legal_address_T_41 = {1'h0, _legal_address_T_40}; // @[Parameters.scala:137:{31,41}] wire [34:0] _legal_address_T_42 = _legal_address_T_41 & 35'h7FFFFF000; // @[Parameters.scala:137:{41,46}] wire [34:0] _legal_address_T_43 = _legal_address_T_42; // @[Parameters.scala:137:46] wire _legal_address_T_44 = _legal_address_T_43 == 35'h0; // @[Parameters.scala:137:{46,59}] wire _legal_address_WIRE_8 = _legal_address_T_44; // @[Parameters.scala:612:40] wire [33:0] _legal_address_T_45 = {io_paddr_0[33:31], io_paddr_0[30:0] ^ 31'h60000000}; // @[PMA.scala:18:7] wire [34:0] _legal_address_T_46 = {1'h0, _legal_address_T_45}; // @[Parameters.scala:137:{31,41}] wire [34:0] _legal_address_T_47 = _legal_address_T_46 & 35'h7E0000000; // @[Parameters.scala:137:{41,46}] wire [34:0] _legal_address_T_48 = _legal_address_T_47; // @[Parameters.scala:137:46] wire _legal_address_T_49 = _legal_address_T_48 == 35'h0; // @[Parameters.scala:137:{46,59}] wire _legal_address_WIRE_9 = _legal_address_T_49; // @[Parameters.scala:612:40] wire [33:0] _GEN_4 = {io_paddr_0[33:32], io_paddr_0[31:0] ^ 32'h80000000}; // @[PMA.scala:18:7] wire [33:0] _legal_address_T_50; // @[Parameters.scala:137:31] assign _legal_address_T_50 = _GEN_4; // @[Parameters.scala:137:31] wire [33:0] _io_resp_x_T_20; // @[Parameters.scala:137:31] assign _io_resp_x_T_20 = _GEN_4; // @[Parameters.scala:137:31] wire [33:0] _io_resp_eff_T_39; // @[Parameters.scala:137:31] assign _io_resp_eff_T_39 = _GEN_4; // @[Parameters.scala:137:31] wire [34:0] _legal_address_T_51 = {1'h0, _legal_address_T_50}; // @[Parameters.scala:137:{31,41}] wire [34:0] _legal_address_T_52 = _legal_address_T_51 & 35'h7FFFFC000; // @[Parameters.scala:137:{41,46}] wire [34:0] _legal_address_T_53 = _legal_address_T_52; // @[Parameters.scala:137:46] wire _legal_address_T_54 = _legal_address_T_53 == 35'h0; // @[Parameters.scala:137:{46,59}] wire _legal_address_WIRE_10 = _legal_address_T_54; // @[Parameters.scala:612:40] wire _legal_address_T_55 = _legal_address_WIRE_0 \| _legal_address_WIRE_1; // @[Parameters.scala:612:40] wire _legal_address_T_56 = _legal_address_T_55 \| _legal_address_WIRE_2; // @[Parameters.scala:612:40] wire _legal_address_T_57 = _legal_address_T_56 \| _legal_address_WIRE_3; // @[Parameters.scala:612:40] wire _legal_address_T_58 = _legal_address_T_57 \| _legal_address_WIRE_4; // @[Parameters.scala:612:40] wire _legal_address_T_59 = _legal_address_T_58 \| _legal_address_WIRE_5; // @[Parameters.scala:612:40] wire _legal_address_T_60 = _legal_address_T_59 \| _legal_address_WIRE_6; // @[Parameters.scala:612:40] wire _legal_address_T_61 = _legal_address_T_60 \| _legal_address_WIRE_7; // @[Parameters.scala:612:40] wire _legal_address_T_62 = _legal_address_T_61 \| _legal_address_WIRE_8; // @[Parameters.scala:612:40] wire _legal_address_T_63 = _legal_address_T_62 \| _legal_address_WIRE_9; // @[Parameters.scala:612:40] wire legal_address = _legal_address_T_63 \| _legal_address_WIRE_10; // @[Parameters.scala:612:40] assign _io_resp_r_T_5 = legal_address; // @[PMA.scala:36:58, :39:19] wire [34:0] _io_resp_cacheable_T_1 = {1'h0, _io_resp_cacheable_T}; // @[Parameters.scala:137:{31,41}] wire [34:0] _io_resp_r_T_1 = {1'h0, _io_resp_r_T}; // @[Parameters.scala:137:{31,41}] assign io_resp_r_0 = _io_resp_r_T_5; // @[PMA.scala:18:7, :39:19] wire [34:0] _io_resp_w_T_1 = {1'h0, _io_resp_w_T}; // @[Parameters.scala:137:{31,41}] wire [34:0] _io_resp_w_T_2 = _io_resp_w_T_1 & 35'h48110000; // @[Parameters.scala:137:{41,46}] wire [34:0] _io_resp_w_T_3 = _io_resp_w_T_2; // @[Parameters.scala:137:46] wire _io_resp_w_T_4 = _io_resp_w_T_3 == 35'h0; // @[Parameters.scala:137:{46,59}] wire [34:0] _io_resp_w_T_6 = {1'h0, _io_resp_w_T_5}; // @[Parameters.scala:137:{31,41}] wire [34:0] _io_resp_w_T_7 = _io_resp_w_T_6 & 35'hC8101000; // @[Parameters.scala:137:{41,46}] wire [34:0] _io_resp_w_T_8 = _io_resp_w_T_7; // @[Parameters.scala:137:46] wire _io_resp_w_T_9 = _io_resp_w_T_8 == 35'h0; // @[Parameters.scala:137:{46,59}] wire [33:0] _GEN_5 = {io_paddr_0[33:28], io_paddr_0[27:0] ^ 28'h8000000}; // @[PMA.scala:18:7] wire [33:0] _io_resp_w_T_10; // @[Parameters.scala:137:31] assign _io_resp_w_T_10 = _GEN_5; // @[Parameters.scala:137:31] wire [33:0] _io_resp_pp_T_10; // @[Parameters.scala:137:31] assign _io_resp_pp_T_10 = _GEN_5; // @[Parameters.scala:137:31] wire [33:0] _io_resp_al_T_10; // @[Parameters.scala:137:31] assign _io_resp_al_T_10 = _GEN_5; // @[Parameters.scala:137:31] wire [33:0] _io_resp_aa_T_10; // @[Parameters.scala:137:31] assign _io_resp_aa_T_10 = _GEN_5; // @[Parameters.scala:137:31] wire [33:0] _io_resp_x_T_44; // @[Parameters.scala:137:31] assign _io_resp_x_T_44 = _GEN_5; // @[Parameters.scala:137:31] wire [33:0] _io_resp_eff_T_15; // @[Parameters.scala:137:31] assign _io_resp_eff_T_15 = _GEN_5; // @[Parameters.scala:137:31] wire [34:0] _io_resp_w_T_11 = {1'h0, _io_resp_w_T_10}; // @[Parameters.scala:137:{31,41}] wire [34:0] _io_resp_w_T_12 = _io_resp_w_T_11 & 35'hC8000000; // @[Parameters.scala:137:{41,46}] wire [34:0] _io_resp_w_T_13 = _io_resp_w_T_12; // @[Parameters.scala:137:46] wire _io_resp_w_T_14 = _io_resp_w_T_13 == 35'h0; // @[Parameters.scala:137:{46,59}] wire [33:0] _GEN_6 = {io_paddr_0[33:31], io_paddr_0[30:0] ^ 31'h40000000}; // @[PMA.scala:18:7] wire [33:0] _io_resp_w_T_15; // @[Parameters.scala:137:31] assign _io_resp_w_T_15 = _GEN_6; // @[Parameters.scala:137:31] wire [33:0] _io_resp_pp_T_15; // @[Parameters.scala:137:31] assign _io_resp_pp_T_15 = _GEN_6; // @[Parameters.scala:137:31] wire [33:0] _io_resp_al_T_22; // @[Parameters.scala:137:31] assign _io_resp_al_T_22 = _GEN_6; // @[Parameters.scala:137:31] wire [33:0] _io_resp_aa_T_22; // @[Parameters.scala:137:31] assign _io_resp_aa_T_22 = _GEN_6; // @[Parameters.scala:137:31] wire [33:0] _io_resp_x_T_15; // @[Parameters.scala:137:31] assign _io_resp_x_T_15 = _GEN_6; // @[Parameters.scala:137:31] wire [33:0] _io_resp_eff_T_20; // @[Parameters.scala:137:31] assign _io_resp_eff_T_20 = _GEN_6; // @[Parameters.scala:137:31] wire [34:0] _io_resp_w_T_16 = {1'h0, _io_resp_w_T_15}; // @[Parameters.scala:137:{31,41}] wire [34:0] _io_resp_w_T_17 = _io_resp_w_T_16 & 35'hC0000000; // @[Parameters.scala:137:{41,46}] wire [34:0] _io_resp_w_T_18 = _io_resp_w_T_17; // @[Parameters.scala:137:46] wire _io_resp_w_T_19 = _io_resp_w_T_18 == 35'h0; // @[Parameters.scala:137:{46,59}] wire _io_resp_w_T_20 = _io_resp_w_T_4 \| _io_resp_w_T_9; // @[Parameters.scala:629:89] wire _io_resp_w_T_21 = _io_resp_w_T_20 \| _io_resp_w_T_14; // @[Parameters.scala:629:89] wire _io_resp_w_T_22 = _io_resp_w_T_21 \| _io_resp_w_T_19; // @[Parameters.scala:629:89] wire _io_resp_w_T_28 = _io_resp_w_T_22; // @[Mux.scala:30:73] wire [34:0] _io_resp_w_T_24 = {1'h0, _io_resp_w_T_23}; // @[Parameters.scala:137:{31,41}] wire [34:0] _io_resp_w_T_25 = _io_resp_w_T_24 & 35'hC8110000; // @[Parameters.scala:137:{41,46}] wire [34:0] _io_resp_w_T_26 = _io_resp_w_T_25; // @[Parameters.scala:137:46] wire _io_resp_w_T_27 = _io_resp_w_T_26 == 35'h0; // @[Parameters.scala:137:{46,59}] wire _io_resp_w_T_30 = _io_resp_w_T_28; // @[Mux.scala:30:73] wire _io_resp_w_WIRE = _io_resp_w_T_30; // @[Mux.scala:30:73] assign _io_resp_w_T_31 = legal_address & _io_resp_w_WIRE; // @[Mux.scala:30:73] assign io_resp_w_0 = _io_resp_w_T_31; // @[PMA.scala:18:7, :39:19] wire [34:0] _io_resp_pp_T_1 = {1'h0, _io_resp_pp_T}; // @[Parameters.scala:137:{31,41}] wire [34:0] _io_resp_pp_T_2 = _io_resp_pp_T_1 & 35'h48110000; // @[Parameters.scala:137:{41,46}] wire [34:0] _io_resp_pp_T_3 = _io_resp_pp_T_2; // @[Parameters.scala:137:46] wire _io_resp_pp_T_4 = _io_resp_pp_T_3 == 35'h0; // @[Parameters.scala:137:{46,59}] wire [34:0] _io_resp_pp_T_6 = {1'h0, _io_resp_pp_T_5}; // @[Parameters.scala:137:{31,41}] wire [34:0] _io_resp_pp_T_7 = _io_resp_pp_T_6 & 35'hC8101000; // @[Parameters.scala:137:{41,46}] wire [34:0] _io_resp_pp_T_8 = _io_resp_pp_T_7; // @[Parameters.scala:137:46] wire _io_resp_pp_T_9 = _io_resp_pp_T_8 == 35'h0; // @[Parameters.scala:137:{46,59}] wire [34:0] _io_resp_pp_T_11 = {1'h0, _io_resp_pp_T_10}; // @[Parameters.scala:137:{31,41}] wire [34:0] _io_resp_pp_T_12 = _io_resp_pp_T_11 & 35'hC8000000; // @[Parameters.scala:137:{41,46}] wire [34:0] _io_resp_pp_T_13 = _io_resp_pp_T_12; // @[Parameters.scala:137:46] wire _io_resp_pp_T_14 = _io_resp_pp_T_13 == 35'h0; // @[Parameters.scala:137:{46,59}] wire [34:0] _io_resp_pp_T_16 = {1'h0, _io_resp_pp_T_15}; // @[Parameters.scala:137:{31,41}] wire [34:0] _io_resp_pp_T_17 = _io_resp_pp_T_16 & 35'hC0000000; // @[Parameters.scala:137:{41,46}] wire [34:0] _io_resp_pp_T_18 = _io_resp_pp_T_17; // @[Parameters.scala:137:46] wire _io_resp_pp_T_19 = _io_resp_pp_T_18 == 35'h0; // @[Parameters.scala:137:{46,59}] wire _io_resp_pp_T_20 = _io_resp_pp_T_4 \| _io_resp_pp_T_9; // @[Parameters.scala:629:89] wire _io_resp_pp_T_21 = _io_resp_pp_T_20 \| _io_resp_pp_T_14; // @[Parameters.scala:629:89] wire _io_resp_pp_T_22 = _io_resp_pp_T_21 \| _io_resp_pp_T_19; // @[Parameters.scala:629:89] wire _io_resp_pp_T_28 = _io_resp_pp_T_22; // @[Mux.scala:30:73] wire [34:0] _io_resp_pp_T_24 = {1'h0, _io_resp_pp_T_23}; // @[Parameters.scala:137:{31,41}] wire [34:0] _io_resp_pp_T_25 = _io_resp_pp_T_24 & 35'hC8110000; // @[Parameters.scala:137:{41,46}] wire [34:0] _io_resp_pp_T_26 = _io_resp_pp_T_25; // @[Parameters.scala:137:46] wire _io_resp_pp_T_27 = _io_resp_pp_T_26 == 35'h0; // @[Parameters.scala:137:{46,59}] wire _io_resp_pp_T_30 = _io_resp_pp_T_28; // @[Mux.scala:30:73] wire _io_resp_pp_WIRE = _io_resp_pp_T_30; // @[Mux.scala:30:73] assign _io_resp_pp_T_31 = legal_address & _io_resp_pp_WIRE; // @[Mux.scala:30:73] assign io_resp_pp_0 = _io_resp_pp_T_31; // @[PMA.scala:18:7, :39:19] wire [34:0] _io_resp_al_T_1 = {1'h0, _io_resp_al_T}; // @[Parameters.scala:137:{31,41}] wire [34:0] _io_resp_al_T_2 = _io_resp_al_T_1 & 35'h48110000; // @[Parameters.scala:137:{41,46}] wire [34:0] _io_resp_al_T_3 = _io_resp_al_T_2; // @[Parameters.scala:137:46] wire _io_resp_al_T_4 = _io_resp_al_T_3 == 35'h0; // @[Parameters.scala:137:{46,59}] wire [34:0] _io_resp_al_T_6 = {1'h0, _io_resp_al_T_5}; // @[Parameters.scala:137:{31,41}] wire [34:0] _io_resp_al_T_7 = _io_resp_al_T_6 & 35'h48101000; // @[Parameters.scala:137:{41,46}] wire [34:0] _io_resp_al_T_8 = _io_resp_al_T_7; // @[Parameters.scala:137:46] wire _io_resp_al_T_9 = _io_resp_al_T_8 == 35'h0; // @[Parameters.scala:137:{46,59}] wire [34:0] _io_resp_al_T_11 = {1'h0, _io_resp_al_T_10}; // @[Parameters.scala:137:{31,41}] wire [34:0] _io_resp_al_T_12 = _io_resp_al_T_11 & 35'h48000000; // @[Parameters.scala:137:{41,46}] wire [34:0] _io_resp_al_T_13 = _io_resp_al_T_12; // @[Parameters.scala:137:46] wire _io_resp_al_T_14 = _io_resp_al_T_13 == 35'h0; // @[Parameters.scala:137:{46,59}] wire _io_resp_al_T_15 = _io_resp_al_T_4 \| _io_resp_al_T_9; // @[Parameters.scala:629:89] wire _io_resp_al_T_16 = _io_resp_al_T_15 \| _io_resp_al_T_14; // @[Parameters.scala:629:89] wire _io_resp_al_T_28 = _io_resp_al_T_16; // @[Mux.scala:30:73] wire [34:0] _io_resp_al_T_18 = {1'h0, _io_resp_al_T_17}; // @[Parameters.scala:137:{31,41}] wire [34:0] _io_resp_al_T_19 = _io_resp_al_T_18 & 35'h48110000; // @[Parameters.scala:137:{41,46}] wire [34:0] _io_resp_al_T_20 = _io_resp_al_T_19; // @[Parameters.scala:137:46] wire _io_resp_al_T_21 = _io_resp_al_T_20 == 35'h0; // @[Parameters.scala:137:{46,59}] wire [34:0] _io_resp_al_T_23 = {1'h0, _io_resp_al_T_22}; // @[Parameters.scala:137:{31,41}] wire [34:0] _io_resp_al_T_24 = _io_resp_al_T_23 & 35'h40000000; // @[Parameters.scala:137:{41,46}] wire [34:0] _io_resp_al_T_25 = _io_resp_al_T_24; // @[Parameters.scala:137:46] wire _io_resp_al_T_26 = _io_resp_al_T_25 == 35'h0; // @[Parameters.scala:137:{46,59}] wire _io_resp_al_T_27 = _io_resp_al_T_21 \| _io_resp_al_T_26; // @[Parameters.scala:629:89] wire _io_resp_al_T_30 = _io_resp_al_T_28; // @[Mux.scala:30:73] wire _io_resp_al_WIRE = _io_resp_al_T_30; // @[Mux.scala:30:73] assign _io_resp_al_T_31 = legal_address & _io_resp_al_WIRE; // @[Mux.scala:30:73] assign io_resp_al_0 = _io_resp_al_T_31; // @[PMA.scala:18:7, :39:19] wire [34:0] _io_resp_aa_T_1 = {1'h0, _io_resp_aa_T}; // @[Parameters.scala:137:{31,41}] wire [34:0] _io_resp_aa_T_2 = _io_resp_aa_T_1 & 35'h48110000; // @[Parameters.scala:137:{41,46}] wire [34:0] _io_resp_aa_T_3 = _io_resp_aa_T_2; // @[Parameters.scala:137:46] wire _io_resp_aa_T_4 = _io_resp_aa_T_3 == 35'h0; // @[Parameters.scala:137:{46,59}] wire [34:0] _io_resp_aa_T_6 = {1'h0, _io_resp_aa_T_5}; // @[Parameters.scala:137:{31,41}] wire [34:0] _io_resp_aa_T_7 = _io_resp_aa_T_6 & 35'h48101000; // @[Parameters.scala:137:{41,46}] wire [34:0] _io_resp_aa_T_8 = _io_resp_aa_T_7; // @[Parameters.scala:137:46] wire _io_resp_aa_T_9 = _io_resp_aa_T_8 == 35'h0; // @[Parameters.scala:137:{46,59}] wire [34:0] _io_resp_aa_T_11 = {1'h0, _io_resp_aa_T_10}; // @[Parameters.scala:137:{31,41}] wire [34:0] _io_resp_aa_T_12 = _io_resp_aa_T_11 & 35'h48000000; // @[Parameters.scala:137:{41,46}] wire [34:0] _io_resp_aa_T_13 = _io_resp_aa_T_12; // @[Parameters.scala:137:46] wire _io_resp_aa_T_14 = _io_resp_aa_T_13 == 35'h0; // @[Parameters.scala:137:{46,59}] wire _io_resp_aa_T_15 = _io_resp_aa_T_4 \| _io_resp_aa_T_9; // @[Parameters.scala:629:89] wire _io_resp_aa_T_16 = _io_resp_aa_T_15 \| _io_resp_aa_T_14; // @[Parameters.scala:629:89] wire _io_resp_aa_T_28 = _io_resp_aa_T_16; // @[Mux.scala:30:73] wire [34:0] _io_resp_aa_T_18 = {1'h0, _io_resp_aa_T_17}; // @[Parameters.scala:137:{31,41}] wire [34:0] _io_resp_aa_T_19 = _io_resp_aa_T_18 & 35'h48110000; // @[Parameters.scala:137:{41,46}] wire [34:0] _io_resp_aa_T_20 = _io_resp_aa_T_19; // @[Parameters.scala:137:46] wire _io_resp_aa_T_21 = _io_resp_aa_T_20 == 35'h0; // @[Parameters.scala:137:{46,59}] wire [34:0] _io_resp_aa_T_23 = {1'h0, _io_resp_aa_T_22}; // @[Parameters.scala:137:{31,41}] wire [34:0] _io_resp_aa_T_24 = _io_resp_aa_T_23 & 35'h40000000; // @[Parameters.scala:137:{41,46}] wire [34:0] _io_resp_aa_T_25 = _io_resp_aa_T_24; // @[Parameters.scala:137:46] wire _io_resp_aa_T_26 = _io_resp_aa_T_25 == 35'h0; // @[Parameters.scala:137:{46,59}] wire _io_resp_aa_T_27 = _io_resp_aa_T_21 \| _io_resp_aa_T_26; // @[Parameters.scala:629:89] wire _io_resp_aa_T_30 = _io_resp_aa_T_28; // @[Mux.scala:30:73] wire _io_resp_aa_WIRE = _io_resp_aa_T_30; // @[Mux.scala:30:73] assign _io_resp_aa_T_31 = legal_address & _io_resp_aa_WIRE; // @[Mux.scala:30:73] assign io_resp_aa_0 = _io_resp_aa_T_31; // @[PMA.scala:18:7, :39:19] wire [34:0] _io_resp_x_T_1 = {1'h0, _io_resp_x_T}; // @[Parameters.scala:137:{31,41}] wire [34:0] _io_resp_x_T_2 = _io_resp_x_T_1 & 35'hDA113000; // @[Parameters.scala:137:{41,46}] wire [34:0] _io_resp_x_T_3 = _io_resp_x_T_2; // @[Parameters.scala:137:46] wire _io_resp_x_T_4 = _io_resp_x_T_3 == 35'h0; // @[Parameters.scala:137:{46,59}] wire [34:0] _io_resp_x_T_6 = {1'h0, _io_resp_x_T_5}; // @[Parameters.scala:137:{31,41}] wire [34:0] _io_resp_x_T_7 = _io_resp_x_T_6 & 35'hDA113000; // @[Parameters.scala:137:{41,46}] wire [34:0] _io_resp_x_T_8 = _io_resp_x_T_7; // @[Parameters.scala:137:46] wire _io_resp_x_T_9 = _io_resp_x_T_8 == 35'h0; // @[Parameters.scala:137:{46,59}] wire [34:0] _io_resp_x_T_11 = {1'h0, _io_resp_x_T_10}; // @[Parameters.scala:137:{31,41}] wire [34:0] _io_resp_x_T_12 = _io_resp_x_T_11 & 35'hDA110000; // @[Parameters.scala:137:{41,46}] wire [34:0] _io_resp_x_T_13 = _io_resp_x_T_12; // @[Parameters.scala:137:46] wire _io_resp_x_T_14 = _io_resp_x_T_13 == 35'h0; // @[Parameters.scala:137:{46,59}] wire [34:0] _io_resp_x_T_16 = {1'h0, _io_resp_x_T_15}; // @[Parameters.scala:137:{31,41}] wire [34:0] _io_resp_x_T_17 = _io_resp_x_T_16 & 35'hC0000000; // @[Parameters.scala:137:{41,46}] wire [34:0] _io_resp_x_T_18 = _io_resp_x_T_17; // @[Parameters.scala:137:46] wire _io_resp_x_T_19 = _io_resp_x_T_18 == 35'h0; // @[Parameters.scala:137:{46,59}] wire [34:0] _io_resp_x_T_21 = {1'h0, _io_resp_x_T_20}; // @[Parameters.scala:137:{31,41}] wire [34:0] _io_resp_x_T_22 = _io_resp_x_T_21 & 35'hDA110000; // @[Parameters.scala:137:{41,46}] wire [34:0] _io_resp_x_T_23 = _io_resp_x_T_22; // @[Parameters.scala:137:46] wire _io_resp_x_T_24 = _io_resp_x_T_23 == 35'h0; // @[Parameters.scala:137:{46,59}] wire _io_resp_x_T_25 = _io_resp_x_T_4 \| _io_resp_x_T_9; // @[Parameters.scala:629:89] wire _io_resp_x_T_26 = _io_resp_x_T_25 \| _io_resp_x_T_14; // @[Parameters.scala:629:89] wire _io_resp_x_T_27 = _io_resp_x_T_26 \| _io_resp_x_T_19; // @[Parameters.scala:629:89] wire _io_resp_x_T_28 = _io_resp_x_T_27 \| _io_resp_x_T_24; // @[Parameters.scala:629:89] wire _io_resp_x_T_58 = _io_resp_x_T_28; // @[Mux.scala:30:73] wire [34:0] _io_resp_x_T_30 = {1'h0, _io_resp_x_T_29}; // @[Parameters.scala:137:{31,41}] wire [34:0] _io_resp_x_T_31 = _io_resp_x_T_30 & 35'hDA113000; // @[Parameters.scala:137:{41,46}] wire [34:0] _io_resp_x_T_32 = _io_resp_x_T_31; // @[Parameters.scala:137:46] wire _io_resp_x_T_33 = _io_resp_x_T_32 == 35'h0; // @[Parameters.scala:137:{46,59}] wire [34:0] _io_resp_x_T_35 = {1'h0, _io_resp_x_T_34}; // @[Parameters.scala:137:{31,41}] wire [34:0] _io_resp_x_T_36 = _io_resp_x_T_35 & 35'hDA103000; // @[Parameters.scala:137:{41,46}] wire [34:0] _io_resp_x_T_37 = _io_resp_x_T_36; // @[Parameters.scala:137:46] wire _io_resp_x_T_38 = _io_resp_x_T_37 == 35'h0; // @[Parameters.scala:137:{46,59}] wire [34:0] _io_resp_x_T_40 = {1'h0, _io_resp_x_T_39}; // @[Parameters.scala:137:{31,41}] wire [34:0] _io_resp_x_T_41 = _io_resp_x_T_40 & 35'hDA110000; // @[Parameters.scala:137:{41,46}] wire [34:0] _io_resp_x_T_42 = _io_resp_x_T_41; // @[Parameters.scala:137:46] wire _io_resp_x_T_43 = _io_resp_x_T_42 == 35'h0; // @[Parameters.scala:137:{46,59}] wire [34:0] _io_resp_x_T_45 = {1'h0, _io_resp_x_T_44}; // @[Parameters.scala:137:{31,41}] wire [34:0] _io_resp_x_T_46 = _io_resp_x_T_45 & 35'hD8000000; // @[Parameters.scala:137:{41,46}] wire [34:0] _io_resp_x_T_47 = _io_resp_x_T_46; // @[Parameters.scala:137:46] wire _io_resp_x_T_48 = _io_resp_x_T_47 == 35'h0; // @[Parameters.scala:137:{46,59}] wire [33:0] _io_resp_x_T_49 = {io_paddr_0[33:29], io_paddr_0[28:0] ^ 29'h10000000}; // @[PMA.scala:18:7] wire [34:0] _io_resp_x_T_50 = {1'h0, _io_resp_x_T_49}; // @[Parameters.scala:137:{31,41}] wire [34:0] _io_resp_x_T_51 = _io_resp_x_T_50 & 35'hDA113000; // @[Parameters.scala:137:{41,46}] wire [34:0] _io_resp_x_T_52 = _io_resp_x_T_51; // @[Parameters.scala:137:46] wire _io_resp_x_T_53 = _io_resp_x_T_52 == 35'h0; // @[Parameters.scala:137:{46,59}] wire _io_resp_x_T_54 = _io_resp_x_T_33 \| _io_resp_x_T_38; // @[Parameters.scala:629:89] wire _io_resp_x_T_55 = _io_resp_x_T_54 \| _io_resp_x_T_43; // @[Parameters.scala:629:89] wire _io_resp_x_T_56 = _io_resp_x_T_55 \| _io_resp_x_T_48; // @[Parameters.scala:629:89] wire _io_resp_x_T_57 = _io_resp_x_T_56 \| _io_resp_x_T_53; // @[Parameters.scala:629:89] wire _io_resp_x_T_60 = _io_resp_x_T_58; // @[Mux.scala:30:73] wire _io_resp_x_WIRE = _io_resp_x_T_60; // @[Mux.scala:30:73] assign _io_resp_x_T_61 = legal_address & _io_resp_x_WIRE; // @[Mux.scala:30:73] assign io_resp_x_0 = _io_resp_x_T_61; // @[PMA.scala:18:7, :39:19] wire [34:0] _io_resp_eff_T_1 = {1'h0, _io_resp_eff_T}; // @[Parameters.scala:137:{31,41}] wire [34:0] _io_resp_eff_T_2 = _io_resp_eff_T_1 & 35'hCA112000; // @[Parameters.scala:137:{41,46}] wire [34:0] _io_resp_eff_T_3 = _io_resp_eff_T_2; // @[Parameters.scala:137:46] wire _io_resp_eff_T_4 = _io_resp_eff_T_3 == 35'h0; // @[Parameters.scala:137:{46,59}] wire [34:0] _io_resp_eff_T_6 = {1'h0, _io_resp_eff_T_5}; // @[Parameters.scala:137:{31,41}] wire [34:0] _io_resp_eff_T_7 = _io_resp_eff_T_6 & 35'hCA103000; // @[Parameters.scala:137:{41,46}] wire [34:0] _io_resp_eff_T_8 = _io_resp_eff_T_7; // @[Parameters.scala:137:46] wire _io_resp_eff_T_9 = _io_resp_eff_T_8 == 35'h0; // @[Parameters.scala:137:{46,59}] wire [34:0] _io_resp_eff_T_11 = {1'h0, _io_resp_eff_T_10}; // @[Parameters.scala:137:{31,41}] wire [34:0] _io_resp_eff_T_12 = _io_resp_eff_T_11 & 35'hCA110000; // @[Parameters.scala:137:{41,46}] wire [34:0] _io_resp_eff_T_13 = _io_resp_eff_T_12; // @[Parameters.scala:137:46] wire _io_resp_eff_T_14 = _io_resp_eff_T_13 == 35'h0; // @[Parameters.scala:137:{46,59}] wire [34:0] _io_resp_eff_T_16 = {1'h0, _io_resp_eff_T_15}; // @[Parameters.scala:137:{31,41}] wire [34:0] _io_resp_eff_T_17 = _io_resp_eff_T_16 & 35'hC8000000; // @[Parameters.scala:137:{41,46}] wire [34:0] _io_resp_eff_T_18 = _io_resp_eff_T_17; // @[Parameters.scala:137:46] wire _io_resp_eff_T_19 = _io_resp_eff_T_18 == 35'h0; // @[Parameters.scala:137:{46,59}] wire [34:0] _io_resp_eff_T_21 = {1'h0, _io_resp_eff_T_20}; // @[Parameters.scala:137:{31,41}] wire [34:0] _io_resp_eff_T_22 = _io_resp_eff_T_21 & 35'hC0000000; // @[Parameters.scala:137:{41,46}] wire [34:0] _io_resp_eff_T_23 = _io_resp_eff_T_22; // @[Parameters.scala:137:46] wire _io_resp_eff_T_24 = _io_resp_eff_T_23 == 35'h0; // @[Parameters.scala:137:{46,59}] wire _io_resp_eff_T_25 = _io_resp_eff_T_4 \| _io_resp_eff_T_9; // @[Parameters.scala:629:89] wire _io_resp_eff_T_26 = _io_resp_eff_T_25 \| _io_resp_eff_T_14; // @[Parameters.scala:629:89] wire _io_resp_eff_T_27 = _io_resp_eff_T_26 \| _io_resp_eff_T_19; // @[Parameters.scala:629:89] wire _io_resp_eff_T_28 = _io_resp_eff_T_27 \| _io_resp_eff_T_24; // @[Parameters.scala:629:89] wire _io_resp_eff_T_46 = _io_resp_eff_T_28; // @[Mux.scala:30:73] wire [34:0] _io_resp_eff_T_30 = {1'h0, _io_resp_eff_T_29}; // @[Parameters.scala:137:{31,41}] wire [34:0] _io_resp_eff_T_31 = _io_resp_eff_T_30 & 35'hCA113000; // @[Parameters.scala:137:{41,46}] wire [34:0] _io_resp_eff_T_32 = _io_resp_eff_T_31; // @[Parameters.scala:137:46] wire _io_resp_eff_T_33 = _io_resp_eff_T_32 == 35'h0; // @[Parameters.scala:137:{46,59}] wire [34:0] _io_resp_eff_T_35 = {1'h0, _io_resp_eff_T_34}; // @[Parameters.scala:137:{31,41}] wire [34:0] _io_resp_eff_T_36 = _io_resp_eff_T_35 & 35'hCA110000; // @[Parameters.scala:137:{41,46}] wire [34:0] _io_resp_eff_T_37 = _io_resp_eff_T_36; // @[Parameters.scala:137:46] wire _io_resp_eff_T_38 = _io_resp_eff_T_37 == 35'h0; // @[Parameters.scala:137:{46,59}] wire [34:0] _io_resp_eff_T_40 = {1'h0, _io_resp_eff_T_39}; // @[Parameters.scala:137:{31,41}] wire [34:0] _io_resp_eff_T_41 = _io_resp_eff_T_40 & 35'hCA110000; // @[Parameters.scala:137:{41,46}] wire [34:0] _io_resp_eff_T_42 = _io_resp_eff_T_41; // @[Parameters.scala:137:46] wire _io_resp_eff_T_43 = _io_resp_eff_T_42 == 35'h0; // @[Parameters.scala:137:{46,59}] wire _io_resp_eff_T_44 = _io_resp_eff_T_33 \| _io_resp_eff_T_38; // @[Parameters.scala:629:89] wire _io_resp_eff_T_45 = _io_resp_eff_T_44 \| _io_resp_eff_T_43; // @[Parameters.scala:629:89] wire _io_resp_eff_T_48 = _io_resp_eff_T_46; // @[Mux.scala:30:73] wire _io_resp_eff_WIRE = _io_resp_eff_T_48; // @[Mux.scala:30:73] assign _io_resp_eff_T_49 = legal_address & _io_resp_eff_WIRE; // @[Mux.scala:30:73] assign io_resp_eff_0 = _io_resp_eff_T_49; // @[PMA.scala:18:7, :39:19] assign io_resp_r = io_resp_r_0; // @[PMA.scala:18:7] assign io_resp_w = io_resp_w_0; // @[PMA.scala:18:7] assign io_resp_pp = io_resp_pp_0; // @[PMA.scala:18:7] assign io_resp_al = io_resp_al_0; // @[PMA.scala:18:7] assign io_resp_aa = io_resp_aa_0; // @[PMA.scala:18:7] assign io_resp_x = io_resp_x_0; // @[PMA.scala:18:7] assign io_resp_eff = io_resp_eff_0; // @[PMA.scala:18:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File primitives.scala: /============================================================================ This Chisel source file is part of a pre-release version of the HardFloat IEEE Floating-Point Arithmetic Package, by John R. Hauser (with some contributions from Yunsup Lee and Andrew Waterman, mainly concerning testing). Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the University of California. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions, and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions, and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the University nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. =============================================================================/ package hardfloat import chisel3._ import chisel3.util._ //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- object lowMask { def apply(in: UInt, topBound: BigInt, bottomBound: BigInt): UInt = { require(topBound != bottomBound) val numInVals = BigInt(1)<<in.getWidth if (topBound < bottomBound) { lowMask(~in, numInVals - 1 - topBound, numInVals - 1 - bottomBound) } else if (numInVals > 64 /* Empirical /) { // For simulation performance, we should avoid generating // exteremely wide shifters, so we divide and conquer. // Empirically, this does not impact synthesis QoR. val mid = numInVals / 2 val msb = in(in.getWidth - 1) val lsbs = in(in.getWidth - 2, 0) if (mid < topBound) { if (mid <= bottomBound) { Mux(msb, lowMask(lsbs, topBound - mid, bottomBound - mid), 0.U ) } else { Mux(msb, lowMask(lsbs, topBound - mid, 0) ## ((BigInt(1)<<(mid - bottomBound).toInt) - 1).U, lowMask(lsbs, mid, bottomBound) ) } } else { ~Mux(msb, 0.U, ~lowMask(lsbs, topBound, bottomBound)) } } else { val shift = (BigInt(-1)<<numInVals.toInt).S>>in Reverse( shift( (numInVals - 1 - bottomBound).toInt, (numInVals - topBound).toInt ) ) } } } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- object countLeadingZeros { def apply(in: UInt): UInt = PriorityEncoder(in.asBools.reverse) } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- object orReduceBy2 { def apply(in: UInt): UInt = { val reducedWidth = (in.getWidth + 1)>>1 val reducedVec = Wire(Vec(reducedWidth, Bool())) for (ix <- 0 until reducedWidth - 1) { reducedVec(ix) := in(ix 2 + 1, ix * 2).orR } reducedVec(reducedWidth - 1) := in(in.getWidth - 1, (reducedWidth - 1) * 2).orR reducedVec.asUInt } } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- object orReduceBy4 { def apply(in: UInt): UInt = { val reducedWidth = (in.getWidth + 3)>>2 val reducedVec = Wire(Vec(reducedWidth, Bool())) for (ix <- 0 until reducedWidth - 1) { reducedVec(ix) := in(ix * 4 + 3, ix * 4).orR } reducedVec(reducedWidth - 1) := in(in.getWidth - 1, (reducedWidth - 1) * 4).orR reducedVec.asUInt } } File MulAddRecFN.scala: /============================================================================ This Chisel source file is part of a pre-release version of the HardFloat IEEE Floating-Point Arithmetic Package, by John R. Hauser (with some contributions from Yunsup Lee and Andrew Waterman, mainly concerning testing). Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the University of California. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions, and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions, and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the University nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. =============================================================================/ package hardfloat import chisel3._ import chisel3.util._ import consts._ //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- class MulAddRecFN_interIo(expWidth: Int, sigWidth: Int) extends Bundle { //*** ENCODE SOME OF THESE CASES IN FEWER BITS?: val isSigNaNAny = Bool() val isNaNAOrB = Bool() val isInfA = Bool() val isZeroA = Bool() val isInfB = Bool() val isZeroB = Bool() val signProd = Bool() val isNaNC = Bool() val isInfC = Bool() val isZeroC = Bool() val sExpSum = SInt((expWidth + 2).W) val doSubMags = Bool() val CIsDominant = Bool() val CDom_CAlignDist = UInt(log2Ceil(sigWidth + 1).W) val highAlignedSigC = UInt((sigWidth + 2).W) val bit0AlignedSigC = UInt(1.W) } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- class MulAddRecFNToRaw_preMul(expWidth: Int, sigWidth: Int) extends RawModule { override def desiredName = s"MulAddRecFNToRaw_preMul_e${expWidth}_s${sigWidth}" val io = IO(new Bundle { val op = Input(Bits(2.W)) val a = Input(Bits((expWidth + sigWidth + 1).W)) val b = Input(Bits((expWidth + sigWidth + 1).W)) val c = Input(Bits((expWidth + sigWidth + 1).W)) val mulAddA = Output(UInt(sigWidth.W)) val mulAddB = Output(UInt(sigWidth.W)) val mulAddC = Output(UInt((sigWidth * 2).W)) val toPostMul = Output(new MulAddRecFN_interIo(expWidth, sigWidth)) }) //------------------------------------------------------------------------ //------------------------------------------------------------------------ //* POSSIBLE TO REDUCE THIS BY 1 OR 2 BITS? (CURRENTLY 2 BITS BETWEEN //* UNSHIFTED C AND PRODUCT): val sigSumWidth = sigWidth * 3 + 3 //------------------------------------------------------------------------ //------------------------------------------------------------------------ val rawA = rawFloatFromRecFN(expWidth, sigWidth, io.a) val rawB = rawFloatFromRecFN(expWidth, sigWidth, io.b) val rawC = rawFloatFromRecFN(expWidth, sigWidth, io.c) val signProd = rawA.sign ^ rawB.sign ^ io.op(1) //* REVIEW THE BIAS FOR 'sExpAlignedProd': val sExpAlignedProd = rawA.sExp +& rawB.sExp + (-(BigInt(1)<<expWidth) + sigWidth + 3).S val doSubMags = signProd ^ rawC.sign ^ io.op(0) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val sNatCAlignDist = sExpAlignedProd - rawC.sExp val posNatCAlignDist = sNatCAlignDist(expWidth + 1, 0) val isMinCAlign = rawA.isZero \|\| rawB.isZero \|\| (sNatCAlignDist < 0.S) val CIsDominant = ! rawC.isZero && (isMinCAlign \|\| (posNatCAlignDist <= sigWidth.U)) val CAlignDist = Mux(isMinCAlign, 0.U, Mux(posNatCAlignDist < (sigSumWidth - 1).U, posNatCAlignDist(log2Ceil(sigSumWidth) - 1, 0), (sigSumWidth - 1).U ) ) val mainAlignedSigC = (Mux(doSubMags, ~rawC.sig, rawC.sig) ## Fill(sigSumWidth - sigWidth + 2, doSubMags)).asSInt>>CAlignDist val reduced4CExtra = (orReduceBy4(rawC.sig<<((sigSumWidth - sigWidth - 1) & 3)) & lowMask( CAlignDist>>2, //* NOT NEEDED?: // (sigSumWidth + 2)>>2, (sigSumWidth - 1)>>2, (sigSumWidth - sigWidth - 1)>>2 ) ).orR val alignedSigC = Cat(mainAlignedSigC>>3, Mux(doSubMags, mainAlignedSigC(2, 0).andR && ! reduced4CExtra, mainAlignedSigC(2, 0).orR \|\| reduced4CExtra ) ) //------------------------------------------------------------------------ //------------------------------------------------------------------------ io.mulAddA := rawA.sig io.mulAddB := rawB.sig io.mulAddC := alignedSigC(sigWidth * 2, 1) io.toPostMul.isSigNaNAny := isSigNaNRawFloat(rawA) \|\| isSigNaNRawFloat(rawB) \|\| isSigNaNRawFloat(rawC) io.toPostMul.isNaNAOrB := rawA.isNaN \|\| rawB.isNaN io.toPostMul.isInfA := rawA.isInf io.toPostMul.isZeroA := rawA.isZero io.toPostMul.isInfB := rawB.isInf io.toPostMul.isZeroB := rawB.isZero io.toPostMul.signProd := signProd io.toPostMul.isNaNC := rawC.isNaN io.toPostMul.isInfC := rawC.isInf io.toPostMul.isZeroC := rawC.isZero io.toPostMul.sExpSum := Mux(CIsDominant, rawC.sExp, sExpAlignedProd - sigWidth.S) io.toPostMul.doSubMags := doSubMags io.toPostMul.CIsDominant := CIsDominant io.toPostMul.CDom_CAlignDist := CAlignDist(log2Ceil(sigWidth + 1) - 1, 0) io.toPostMul.highAlignedSigC := alignedSigC(sigSumWidth - 1, sigWidth * 2 + 1) io.toPostMul.bit0AlignedSigC := alignedSigC(0) } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- class MulAddRecFNToRaw_postMul(expWidth: Int, sigWidth: Int) extends RawModule { override def desiredName = s"MulAddRecFNToRaw_postMul_e${expWidth}_s${sigWidth}" val io = IO(new Bundle { val fromPreMul = Input(new MulAddRecFN_interIo(expWidth, sigWidth)) val mulAddResult = Input(UInt((sigWidth * 2 + 1).W)) val roundingMode = Input(UInt(3.W)) val invalidExc = Output(Bool()) val rawOut = Output(new RawFloat(expWidth, sigWidth + 2)) }) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val sigSumWidth = sigWidth * 3 + 3 //------------------------------------------------------------------------ //------------------------------------------------------------------------ val roundingMode_min = (io.roundingMode === round_min) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val opSignC = io.fromPreMul.signProd ^ io.fromPreMul.doSubMags val sigSum = Cat(Mux(io.mulAddResult(sigWidth * 2), io.fromPreMul.highAlignedSigC + 1.U, io.fromPreMul.highAlignedSigC ), io.mulAddResult(sigWidth * 2 - 1, 0), io.fromPreMul.bit0AlignedSigC ) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val CDom_sign = opSignC val CDom_sExp = io.fromPreMul.sExpSum - io.fromPreMul.doSubMags.zext val CDom_absSigSum = Mux(io.fromPreMul.doSubMags, ~sigSum(sigSumWidth - 1, sigWidth + 1), 0.U(1.W) ## //*** IF GAP IS REDUCED TO 1 BIT, MUST REDUCE THIS COMPONENT TO 1 BIT TOO: io.fromPreMul.highAlignedSigC(sigWidth + 1, sigWidth) ## sigSum(sigSumWidth - 3, sigWidth + 2) ) val CDom_absSigSumExtra = Mux(io.fromPreMul.doSubMags, (~sigSum(sigWidth, 1)).orR, sigSum(sigWidth + 1, 1).orR ) val CDom_mainSig = (CDom_absSigSum<<io.fromPreMul.CDom_CAlignDist)( sigWidth * 2 + 1, sigWidth - 3) val CDom_reduced4SigExtra = (orReduceBy4(CDom_absSigSum(sigWidth - 1, 0)<<(~sigWidth & 3)) & lowMask(io.fromPreMul.CDom_CAlignDist>>2, 0, sigWidth>>2)).orR val CDom_sig = Cat(CDom_mainSig>>3, CDom_mainSig(2, 0).orR \|\| CDom_reduced4SigExtra \|\| CDom_absSigSumExtra ) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val notCDom_signSigSum = sigSum(sigWidth * 2 + 3) val notCDom_absSigSum = Mux(notCDom_signSigSum, ~sigSum(sigWidth * 2 + 2, 0), sigSum(sigWidth * 2 + 2, 0) + io.fromPreMul.doSubMags ) val notCDom_reduced2AbsSigSum = orReduceBy2(notCDom_absSigSum) val notCDom_normDistReduced2 = countLeadingZeros(notCDom_reduced2AbsSigSum) val notCDom_nearNormDist = notCDom_normDistReduced2<<1 val notCDom_sExp = io.fromPreMul.sExpSum - notCDom_nearNormDist.asUInt.zext val notCDom_mainSig = (notCDom_absSigSum<<notCDom_nearNormDist)( sigWidth * 2 + 3, sigWidth - 1) val notCDom_reduced4SigExtra = (orReduceBy2( notCDom_reduced2AbsSigSum(sigWidth>>1, 0)<<((sigWidth>>1) & 1)) & lowMask(notCDom_normDistReduced2>>1, 0, (sigWidth + 2)>>2) ).orR val notCDom_sig = Cat(notCDom_mainSig>>3, notCDom_mainSig(2, 0).orR \|\| notCDom_reduced4SigExtra ) val notCDom_completeCancellation = (notCDom_sig(sigWidth + 2, sigWidth + 1) === 0.U) val notCDom_sign = Mux(notCDom_completeCancellation, roundingMode_min, io.fromPreMul.signProd ^ notCDom_signSigSum ) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val notNaN_isInfProd = io.fromPreMul.isInfA \|\| io.fromPreMul.isInfB val notNaN_isInfOut = notNaN_isInfProd \|\| io.fromPreMul.isInfC val notNaN_addZeros = (io.fromPreMul.isZeroA \|\| io.fromPreMul.isZeroB) && io.fromPreMul.isZeroC io.invalidExc := io.fromPreMul.isSigNaNAny \|\| (io.fromPreMul.isInfA && io.fromPreMul.isZeroB) \|\| (io.fromPreMul.isZeroA && io.fromPreMul.isInfB) \|\| (! io.fromPreMul.isNaNAOrB && (io.fromPreMul.isInfA \|\| io.fromPreMul.isInfB) && io.fromPreMul.isInfC && io.fromPreMul.doSubMags) io.rawOut.isNaN := io.fromPreMul.isNaNAOrB \|\| io.fromPreMul.isNaNC io.rawOut.isInf := notNaN_isInfOut //*** IMPROVE?: io.rawOut.isZero := notNaN_addZeros \|\| (! io.fromPreMul.CIsDominant && notCDom_completeCancellation) io.rawOut.sign := (notNaN_isInfProd && io.fromPreMul.signProd) \|\| (io.fromPreMul.isInfC && opSignC) \|\| (notNaN_addZeros && ! roundingMode_min && io.fromPreMul.signProd && opSignC) \|\| (notNaN_addZeros && roundingMode_min && (io.fromPreMul.signProd \|\| opSignC)) \|\| (! notNaN_isInfOut && ! notNaN_addZeros && Mux(io.fromPreMul.CIsDominant, CDom_sign, notCDom_sign)) io.rawOut.sExp := Mux(io.fromPreMul.CIsDominant, CDom_sExp, notCDom_sExp) io.rawOut.sig := Mux(io.fromPreMul.CIsDominant, CDom_sig, notCDom_sig) } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- class MulAddRecFN(expWidth: Int, sigWidth: Int) extends RawModule { override def desiredName = s"MulAddRecFN_e${expWidth}_s${sigWidth}" val io = IO(new Bundle { val op = Input(Bits(2.W)) val a = Input(Bits((expWidth + sigWidth + 1).W)) val b = Input(Bits((expWidth + sigWidth + 1).W)) val c = Input(Bits((expWidth + sigWidth + 1).W)) val roundingMode = Input(UInt(3.W)) val detectTininess = Input(UInt(1.W)) val out = Output(Bits((expWidth + sigWidth + 1).W)) val exceptionFlags = Output(Bits(5.W)) }) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val mulAddRecFNToRaw_preMul = Module(new MulAddRecFNToRaw_preMul(expWidth, sigWidth)) val mulAddRecFNToRaw_postMul = Module(new MulAddRecFNToRaw_postMul(expWidth, sigWidth)) mulAddRecFNToRaw_preMul.io.op := io.op mulAddRecFNToRaw_preMul.io.a := io.a mulAddRecFNToRaw_preMul.io.b := io.b mulAddRecFNToRaw_preMul.io.c := io.c val mulAddResult = (mulAddRecFNToRaw_preMul.io.mulAddA * mulAddRecFNToRaw_preMul.io.mulAddB) +& mulAddRecFNToRaw_preMul.io.mulAddC mulAddRecFNToRaw_postMul.io.fromPreMul := mulAddRecFNToRaw_preMul.io.toPostMul mulAddRecFNToRaw_postMul.io.mulAddResult := mulAddResult mulAddRecFNToRaw_postMul.io.roundingMode := io.roundingMode //------------------------------------------------------------------------ //------------------------------------------------------------------------ val roundRawFNToRecFN = Module(new RoundRawFNToRecFN(expWidth, sigWidth, 0)) roundRawFNToRecFN.io.invalidExc := mulAddRecFNToRaw_postMul.io.invalidExc roundRawFNToRecFN.io.infiniteExc := false.B roundRawFNToRecFN.io.in := mulAddRecFNToRaw_postMul.io.rawOut roundRawFNToRecFN.io.roundingMode := io.roundingMode roundRawFNToRecFN.io.detectTininess := io.detectTininess io.out := roundRawFNToRecFN.io.out io.exceptionFlags := roundRawFNToRecFN.io.exceptionFlags } File rawFloatFromRecFN.scala: /============================================================================ This Chisel source file is part of a pre-release version of the HardFloat IEEE Floating-Point Arithmetic Package, by John R. Hauser (with some contributions from Yunsup Lee and Andrew Waterman, mainly concerning testing). Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of California. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions, and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions, and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the University nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. =============================================================================/ package hardfloat import chisel3._ import chisel3.util._ /---------------------------------------------------------------------------- \| In the result, no more than one of 'isNaN', 'isInf', and 'isZero' will be \| set. ----------------------------------------------------------------------------/ object rawFloatFromRecFN { def apply(expWidth: Int, sigWidth: Int, in: Bits): RawFloat = { val exp = in(expWidth + sigWidth - 1, sigWidth - 1) val isZero = exp(expWidth, expWidth - 2) === 0.U val isSpecial = exp(expWidth, expWidth - 1) === 3.U val out = Wire(new RawFloat(expWidth, sigWidth)) out.isNaN := isSpecial && exp(expWidth - 2) out.isInf := isSpecial && ! exp(expWidth - 2) out.isZero := isZero out.sign := in(expWidth + sigWidth) out.sExp := exp.zext out.sig := 0.U(1.W) ## ! isZero ## in(sigWidth - 2, 0) out } } File common.scala: /============================================================================ This Chisel source file is part of a pre-release version of the HardFloat IEEE Floating-Point Arithmetic Package, by John R. Hauser (with some contributions from Yunsup Lee and Andrew Waterman, mainly concerning testing). Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017, 2018 The Regents of the University of California. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions, and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions, and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the University nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. =============================================================================/ package hardfloat import chisel3._ object consts { /------------------------------------------------------------------------ \| For rounding to integer values, rounding mode 'odd' rounds to minimum \| magnitude instead, same as 'minMag'. ------------------------------------------------------------------------/ def round_near_even = "b000".U(3.W) def round_minMag = "b001".U(3.W) def round_min = "b010".U(3.W) def round_max = "b011".U(3.W) def round_near_maxMag = "b100".U(3.W) def round_odd = "b110".U(3.W) /------------------------------------------------------------------------ ------------------------------------------------------------------------/ def tininess_beforeRounding = 0.U def tininess_afterRounding = 1.U /------------------------------------------------------------------------ ------------------------------------------------------------------------/ def flRoundOpt_sigMSBitAlwaysZero = 1 def flRoundOpt_subnormsAlwaysExact = 2 def flRoundOpt_neverUnderflows = 4 def flRoundOpt_neverOverflows = 8 /------------------------------------------------------------------------ ------------------------------------------------------------------------/ def divSqrtOpt_twoBitsPerCycle = 16 } class RawFloat(val expWidth: Int, val sigWidth: Int) extends Bundle { val isNaN: Bool = Bool() // overrides all other fields val isInf: Bool = Bool() // overrides 'isZero', 'sExp', and 'sig' val isZero: Bool = Bool() // overrides 'sExp' and 'sig' val sign: Bool = Bool() val sExp: SInt = SInt((expWidth + 2).W) val sig: UInt = UInt((sigWidth + 1).W) // 2 m.s. bits cannot both be 0 } //** CHANGE THIS INTO A '.isSigNaN' METHOD OF THE 'RawFloat' CLASS: object isSigNaNRawFloat { def apply(in: RawFloat): Bool = in.isNaN && !in.sig(in.sigWidth - 2) }	module MulAddRecFNToRaw_preMul_e8_s24_63( // @[MulAddRecFN.scala:71:7] input [32:0] io_a, // @[MulAddRecFN.scala:74:16] input [32:0] io_c, // @[MulAddRecFN.scala:74:16] output [23:0] io_mulAddA, // @[MulAddRecFN.scala:74:16] output [47:0] io_mulAddC, // @[MulAddRecFN.scala:74:16] output io_toPostMul_isSigNaNAny, // @[MulAddRecFN.scala:74:16] output io_toPostMul_isNaNAOrB, // @[MulAddRecFN.scala:74:16] output io_toPostMul_isInfA, // @[MulAddRecFN.scala:74:16] output io_toPostMul_isZeroA, // @[MulAddRecFN.scala:74:16] output io_toPostMul_signProd, // @[MulAddRecFN.scala:74:16] output io_toPostMul_isNaNC, // @[MulAddRecFN.scala:74:16] output io_toPostMul_isInfC, // @[MulAddRecFN.scala:74:16] output io_toPostMul_isZeroC, // @[MulAddRecFN.scala:74:16] output [9:0] io_toPostMul_sExpSum, // @[MulAddRecFN.scala:74:16] output io_toPostMul_doSubMags, // @[MulAddRecFN.scala:74:16] output io_toPostMul_CIsDominant, // @[MulAddRecFN.scala:74:16] output [4:0] io_toPostMul_CDom_CAlignDist, // @[MulAddRecFN.scala:74:16] output [25:0] io_toPostMul_highAlignedSigC, // @[MulAddRecFN.scala:74:16] output io_toPostMul_bit0AlignedSigC // @[MulAddRecFN.scala:74:16] ); wire rawA_sign; // @[rawFloatFromRecFN.scala:55:23] wire rawA_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire [32:0] io_a_0 = io_a; // @[MulAddRecFN.scala:71:7] wire [32:0] io_c_0 = io_c; // @[MulAddRecFN.scala:71:7] wire [8:0] rawB_exp = 9'h100; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _rawB_isZero_T = 3'h4; // @[rawFloatFromRecFN.scala:52:28] wire [1:0] _rawB_isSpecial_T = 2'h2; // @[rawFloatFromRecFN.scala:53:28] wire [9:0] rawB_sExp = 10'h100; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire [9:0] _rawB_out_sExp_T = 10'h100; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire [1:0] _rawB_out_sig_T_1 = 2'h1; // @[rawFloatFromRecFN.scala:61:32] wire [22:0] _rawB_out_sig_T_2 = 23'h0; // @[rawFloatFromRecFN.scala:61:49] wire [24:0] rawB_sig = 25'h800000; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire [24:0] _rawB_out_sig_T_3 = 25'h800000; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire _rawB_out_isInf_T_1 = 1'h1; // @[rawFloatFromRecFN.scala:57:36, :61:35] wire _rawB_out_sig_T = 1'h1; // @[rawFloatFromRecFN.scala:57:36, :61:35] wire _io_toPostMul_isSigNaNAny_T_4 = 1'h1; // @[rawFloatFromRecFN.scala:57:36, :61:35] wire io_toPostMul_isInfB = 1'h0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_isZeroB = 1'h0; // @[MulAddRecFN.scala:71:7] wire rawB_isZero = 1'h0; // @[rawFloatFromRecFN.scala:52:53] wire rawB_isSpecial = 1'h0; // @[rawFloatFromRecFN.scala:53:53] wire rawB_isNaN = 1'h0; // @[rawFloatFromRecFN.scala:55:23] wire rawB_isInf = 1'h0; // @[rawFloatFromRecFN.scala:55:23] wire rawB_isZero_0 = 1'h0; // @[rawFloatFromRecFN.scala:55:23] wire rawB_sign = 1'h0; // @[rawFloatFromRecFN.scala:55:23] wire _rawB_out_isNaN_T = 1'h0; // @[rawFloatFromRecFN.scala:56:41] wire _rawB_out_isNaN_T_1 = 1'h0; // @[rawFloatFromRecFN.scala:56:33] wire _rawB_out_isInf_T = 1'h0; // @[rawFloatFromRecFN.scala:57:41] wire _rawB_out_isInf_T_2 = 1'h0; // @[rawFloatFromRecFN.scala:57:33] wire _rawB_out_sign_T = 1'h0; // @[rawFloatFromRecFN.scala:59:25] wire _signProd_T_1 = 1'h0; // @[MulAddRecFN.scala:97:49] wire _doSubMags_T_1 = 1'h0; // @[MulAddRecFN.scala:102:49] wire _io_toPostMul_isSigNaNAny_T_3 = 1'h0; // @[common.scala:82:56] wire _io_toPostMul_isSigNaNAny_T_5 = 1'h0; // @[common.scala:82:46] wire [23:0] io_mulAddB = 24'h800000; // @[MulAddRecFN.scala:71:7, :74:16, :142:16] wire [32:0] io_b = 33'h80000000; // @[MulAddRecFN.scala:71:7, :74:16] wire [1:0] io_op = 2'h0; // @[MulAddRecFN.scala:71:7, :74:16] wire [47:0] _io_mulAddC_T; // @[MulAddRecFN.scala:143:30] wire _io_toPostMul_isSigNaNAny_T_10; // @[MulAddRecFN.scala:146:58] wire _io_toPostMul_isNaNAOrB_T; // @[MulAddRecFN.scala:148:42] wire rawA_isInf; // @[rawFloatFromRecFN.scala:55:23] wire rawA_isZero; // @[rawFloatFromRecFN.scala:55:23] wire signProd; // @[MulAddRecFN.scala:97:42] wire rawC_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire rawC_isInf; // @[rawFloatFromRecFN.scala:55:23] wire rawC_isZero; // @[rawFloatFromRecFN.scala:55:23] wire doSubMags; // @[MulAddRecFN.scala:102:42] wire CIsDominant; // @[MulAddRecFN.scala:110:23] wire [4:0] _io_toPostMul_CDom_CAlignDist_T; // @[MulAddRecFN.scala:161:47] wire [25:0] _io_toPostMul_highAlignedSigC_T; // @[MulAddRecFN.scala:163:20] wire _io_toPostMul_bit0AlignedSigC_T; // @[MulAddRecFN.scala:164:48] wire io_toPostMul_isSigNaNAny_0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_isNaNAOrB_0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_isInfA_0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_isZeroA_0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_signProd_0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_isNaNC_0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_isInfC_0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_isZeroC_0; // @[MulAddRecFN.scala:71:7] wire [9:0] io_toPostMul_sExpSum_0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_doSubMags_0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_CIsDominant_0; // @[MulAddRecFN.scala:71:7] wire [4:0] io_toPostMul_CDom_CAlignDist_0; // @[MulAddRecFN.scala:71:7] wire [25:0] io_toPostMul_highAlignedSigC_0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_bit0AlignedSigC_0; // @[MulAddRecFN.scala:71:7] wire [23:0] io_mulAddA_0; // @[MulAddRecFN.scala:71:7] wire [47:0] io_mulAddC_0; // @[MulAddRecFN.scala:71:7] wire [8:0] rawA_exp = io_a_0[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _rawA_isZero_T = rawA_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire rawA_isZero_0 = _rawA_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] assign rawA_isZero = rawA_isZero_0; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _rawA_isSpecial_T = rawA_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire rawA_isSpecial = &_rawA_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _rawA_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33] wire _rawA_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33] assign _io_toPostMul_isNaNAOrB_T = rawA_isNaN; // @[rawFloatFromRecFN.scala:55:23] assign io_toPostMul_isInfA_0 = rawA_isInf; // @[rawFloatFromRecFN.scala:55:23] assign io_toPostMul_isZeroA_0 = rawA_isZero; // @[rawFloatFromRecFN.scala:55:23] wire _rawA_out_sign_T; // @[rawFloatFromRecFN.scala:59:25] wire _isMinCAlign_T = rawA_isZero; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] _rawA_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27] wire _signProd_T = rawA_sign; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] _rawA_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44] wire [9:0] rawA_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] rawA_sig; // @[rawFloatFromRecFN.scala:55:23] wire _rawA_out_isNaN_T = rawA_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _rawA_out_isInf_T = rawA_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _rawA_out_isNaN_T_1 = rawA_isSpecial & _rawA_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign rawA_isNaN = _rawA_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _rawA_out_isInf_T_1 = ~_rawA_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _rawA_out_isInf_T_2 = rawA_isSpecial & _rawA_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign rawA_isInf = _rawA_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _rawA_out_sign_T = io_a_0[32]; // @[rawFloatFromRecFN.scala:59:25] assign rawA_sign = _rawA_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _rawA_out_sExp_T = {1'h0, rawA_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign rawA_sExp = _rawA_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _rawA_out_sig_T = ~rawA_isZero_0; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _rawA_out_sig_T_1 = {1'h0, _rawA_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _rawA_out_sig_T_2 = io_a_0[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _rawA_out_sig_T_3 = {_rawA_out_sig_T_1, _rawA_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign rawA_sig = _rawA_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire [8:0] rawC_exp = io_c_0[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _rawC_isZero_T = rawC_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire rawC_isZero_0 = _rawC_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] assign rawC_isZero = rawC_isZero_0; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _rawC_isSpecial_T = rawC_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire rawC_isSpecial = &_rawC_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _rawC_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33] assign io_toPostMul_isNaNC_0 = rawC_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire _rawC_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33] assign io_toPostMul_isInfC_0 = rawC_isInf; // @[rawFloatFromRecFN.scala:55:23] assign io_toPostMul_isZeroC_0 = rawC_isZero; // @[rawFloatFromRecFN.scala:55:23] wire _rawC_out_sign_T; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _rawC_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _rawC_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44] wire rawC_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] rawC_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] rawC_sig; // @[rawFloatFromRecFN.scala:55:23] wire _rawC_out_isNaN_T = rawC_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _rawC_out_isInf_T = rawC_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _rawC_out_isNaN_T_1 = rawC_isSpecial & _rawC_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign rawC_isNaN = _rawC_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _rawC_out_isInf_T_1 = ~_rawC_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _rawC_out_isInf_T_2 = rawC_isSpecial & _rawC_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign rawC_isInf = _rawC_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _rawC_out_sign_T = io_c_0[32]; // @[rawFloatFromRecFN.scala:59:25] assign rawC_sign = _rawC_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _rawC_out_sExp_T = {1'h0, rawC_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign rawC_sExp = _rawC_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _rawC_out_sig_T = ~rawC_isZero_0; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _rawC_out_sig_T_1 = {1'h0, _rawC_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _rawC_out_sig_T_2 = io_c_0[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _rawC_out_sig_T_3 = {_rawC_out_sig_T_1, _rawC_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign rawC_sig = _rawC_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44] assign signProd = _signProd_T; // @[MulAddRecFN.scala:97:{30,42}] assign io_toPostMul_signProd_0 = signProd; // @[MulAddRecFN.scala:71:7, :97:42] wire [10:0] _sExpAlignedProd_T = {rawA_sExp[9], rawA_sExp} + 11'h100; // @[rawFloatFromRecFN.scala:55:23] wire [11:0] _sExpAlignedProd_T_1 = {_sExpAlignedProd_T[10], _sExpAlignedProd_T} - 12'hE5; // @[MulAddRecFN.scala:100:{19,32}] wire [10:0] _sExpAlignedProd_T_2 = _sExpAlignedProd_T_1[10:0]; // @[MulAddRecFN.scala:100:32] wire [10:0] sExpAlignedProd = _sExpAlignedProd_T_2; // @[MulAddRecFN.scala:100:32] wire _doSubMags_T = signProd ^ rawC_sign; // @[rawFloatFromRecFN.scala:55:23] assign doSubMags = _doSubMags_T; // @[MulAddRecFN.scala:102:{30,42}] assign io_toPostMul_doSubMags_0 = doSubMags; // @[MulAddRecFN.scala:71:7, :102:42] wire [11:0] _GEN = {sExpAlignedProd[10], sExpAlignedProd}; // @[MulAddRecFN.scala:100:32, :106:42] wire [11:0] _sNatCAlignDist_T = _GEN - {{2{rawC_sExp[9]}}, rawC_sExp}; // @[rawFloatFromRecFN.scala:55:23] wire [10:0] _sNatCAlignDist_T_1 = _sNatCAlignDist_T[10:0]; // @[MulAddRecFN.scala:106:42] wire [10:0] sNatCAlignDist = _sNatCAlignDist_T_1; // @[MulAddRecFN.scala:106:42] wire [9:0] posNatCAlignDist = sNatCAlignDist[9:0]; // @[MulAddRecFN.scala:106:42, :107:42] wire _isMinCAlign_T_1 = $signed(sNatCAlignDist) < 11'sh0; // @[MulAddRecFN.scala:106:42, :108:69] wire isMinCAlign = _isMinCAlign_T \| _isMinCAlign_T_1; // @[MulAddRecFN.scala:108:{35,50,69}] wire _CIsDominant_T = ~rawC_isZero; // @[rawFloatFromRecFN.scala:55:23] wire _CIsDominant_T_1 = posNatCAlignDist < 10'h19; // @[MulAddRecFN.scala:107:42, :110:60] wire _CIsDominant_T_2 = isMinCAlign \| _CIsDominant_T_1; // @[MulAddRecFN.scala:108:50, :110:{39,60}] assign CIsDominant = _CIsDominant_T & _CIsDominant_T_2; // @[MulAddRecFN.scala:110:{9,23,39}] assign io_toPostMul_CIsDominant_0 = CIsDominant; // @[MulAddRecFN.scala:71:7, :110:23] wire _CAlignDist_T = posNatCAlignDist < 10'h4A; // @[MulAddRecFN.scala:107:42, :114:34] wire [6:0] _CAlignDist_T_1 = posNatCAlignDist[6:0]; // @[MulAddRecFN.scala:107:42, :115:33] wire [6:0] _CAlignDist_T_2 = _CAlignDist_T ? _CAlignDist_T_1 : 7'h4A; // @[MulAddRecFN.scala:114:{16,34}, :115:33] wire [6:0] CAlignDist = isMinCAlign ? 7'h0 : _CAlignDist_T_2; // @[MulAddRecFN.scala:108:50, :112:12, :114:16] wire [24:0] _mainAlignedSigC_T = ~rawC_sig; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] _mainAlignedSigC_T_1 = doSubMags ? _mainAlignedSigC_T : rawC_sig; // @[rawFloatFromRecFN.scala:55:23] wire [52:0] _mainAlignedSigC_T_2 = {53{doSubMags}}; // @[MulAddRecFN.scala:102:42, :120:53] wire [77:0] _mainAlignedSigC_T_3 = {_mainAlignedSigC_T_1, _mainAlignedSigC_T_2}; // @[MulAddRecFN.scala:120:{13,46,53}] wire [77:0] _mainAlignedSigC_T_4 = _mainAlignedSigC_T_3; // @[MulAddRecFN.scala:120:{46,94}] wire [77:0] mainAlignedSigC = $signed($signed(_mainAlignedSigC_T_4) >>> CAlignDist); // @[MulAddRecFN.scala:112:12, :120:{94,100}] wire [26:0] _reduced4CExtra_T = {rawC_sig, 2'h0}; // @[rawFloatFromRecFN.scala:55:23] wire _reduced4CExtra_reducedVec_0_T_1; // @[primitives.scala:120:54] wire _reduced4CExtra_reducedVec_1_T_1; // @[primitives.scala:120:54] wire _reduced4CExtra_reducedVec_2_T_1; // @[primitives.scala:120:54] wire _reduced4CExtra_reducedVec_3_T_1; // @[primitives.scala:120:54] wire _reduced4CExtra_reducedVec_4_T_1; // @[primitives.scala:120:54] wire _reduced4CExtra_reducedVec_5_T_1; // @[primitives.scala:120:54] wire _reduced4CExtra_reducedVec_6_T_1; // @[primitives.scala:123:57] wire reduced4CExtra_reducedVec_0; // @[primitives.scala:118:30] wire reduced4CExtra_reducedVec_1; // @[primitives.scala:118:30] wire reduced4CExtra_reducedVec_2; // @[primitives.scala:118:30] wire reduced4CExtra_reducedVec_3; // @[primitives.scala:118:30] wire reduced4CExtra_reducedVec_4; // @[primitives.scala:118:30] wire reduced4CExtra_reducedVec_5; // @[primitives.scala:118:30] wire reduced4CExtra_reducedVec_6; // @[primitives.scala:118:30] wire [3:0] _reduced4CExtra_reducedVec_0_T = _reduced4CExtra_T[3:0]; // @[primitives.scala:120:33] assign _reduced4CExtra_reducedVec_0_T_1 = \|_reduced4CExtra_reducedVec_0_T; // @[primitives.scala:120:{33,54}] assign reduced4CExtra_reducedVec_0 = _reduced4CExtra_reducedVec_0_T_1; // @[primitives.scala:118:30, :120:54] wire [3:0] _reduced4CExtra_reducedVec_1_T = _reduced4CExtra_T[7:4]; // @[primitives.scala:120:33] assign _reduced4CExtra_reducedVec_1_T_1 = \|_reduced4CExtra_reducedVec_1_T; // @[primitives.scala:120:{33,54}] assign reduced4CExtra_reducedVec_1 = _reduced4CExtra_reducedVec_1_T_1; // @[primitives.scala:118:30, :120:54] wire [3:0] _reduced4CExtra_reducedVec_2_T = _reduced4CExtra_T[11:8]; // @[primitives.scala:120:33] assign _reduced4CExtra_reducedVec_2_T_1 = \|_reduced4CExtra_reducedVec_2_T; // @[primitives.scala:120:{33,54}] assign reduced4CExtra_reducedVec_2 = _reduced4CExtra_reducedVec_2_T_1; // @[primitives.scala:118:30, :120:54] wire [3:0] _reduced4CExtra_reducedVec_3_T = _reduced4CExtra_T[15:12]; // @[primitives.scala:120:33] assign _reduced4CExtra_reducedVec_3_T_1 = \|_reduced4CExtra_reducedVec_3_T; // @[primitives.scala:120:{33,54}] assign reduced4CExtra_reducedVec_3 = _reduced4CExtra_reducedVec_3_T_1; // @[primitives.scala:118:30, :120:54] wire [3:0] _reduced4CExtra_reducedVec_4_T = _reduced4CExtra_T[19:16]; // @[primitives.scala:120:33] assign _reduced4CExtra_reducedVec_4_T_1 = \|_reduced4CExtra_reducedVec_4_T; // @[primitives.scala:120:{33,54}] assign reduced4CExtra_reducedVec_4 = _reduced4CExtra_reducedVec_4_T_1; // @[primitives.scala:118:30, :120:54] wire [3:0] _reduced4CExtra_reducedVec_5_T = _reduced4CExtra_T[23:20]; // @[primitives.scala:120:33] assign _reduced4CExtra_reducedVec_5_T_1 = \|_reduced4CExtra_reducedVec_5_T; // @[primitives.scala:120:{33,54}] assign reduced4CExtra_reducedVec_5 = _reduced4CExtra_reducedVec_5_T_1; // @[primitives.scala:118:30, :120:54] wire [2:0] _reduced4CExtra_reducedVec_6_T = _reduced4CExtra_T[26:24]; // @[primitives.scala:123:15] assign _reduced4CExtra_reducedVec_6_T_1 = \|_reduced4CExtra_reducedVec_6_T; // @[primitives.scala:123:{15,57}] assign reduced4CExtra_reducedVec_6 = _reduced4CExtra_reducedVec_6_T_1; // @[primitives.scala:118:30, :123:57] wire [1:0] reduced4CExtra_lo_hi = {reduced4CExtra_reducedVec_2, reduced4CExtra_reducedVec_1}; // @[primitives.scala:118:30, :124:20] wire [2:0] reduced4CExtra_lo = {reduced4CExtra_lo_hi, reduced4CExtra_reducedVec_0}; // @[primitives.scala:118:30, :124:20] wire [1:0] reduced4CExtra_hi_lo = {reduced4CExtra_reducedVec_4, reduced4CExtra_reducedVec_3}; // @[primitives.scala:118:30, :124:20] wire [1:0] reduced4CExtra_hi_hi = {reduced4CExtra_reducedVec_6, reduced4CExtra_reducedVec_5}; // @[primitives.scala:118:30, :124:20] wire [3:0] reduced4CExtra_hi = {reduced4CExtra_hi_hi, reduced4CExtra_hi_lo}; // @[primitives.scala:124:20] wire [6:0] _reduced4CExtra_T_1 = {reduced4CExtra_hi, reduced4CExtra_lo}; // @[primitives.scala:124:20] wire [4:0] _reduced4CExtra_T_2 = CAlignDist[6:2]; // @[MulAddRecFN.scala:112:12, :124:28] wire [32:0] reduced4CExtra_shift = $signed(33'sh100000000 >>> _reduced4CExtra_T_2); // @[primitives.scala:76:56] wire [5:0] _reduced4CExtra_T_3 = reduced4CExtra_shift[19:14]; // @[primitives.scala:76:56, :78:22] wire [3:0] _reduced4CExtra_T_4 = _reduced4CExtra_T_3[3:0]; // @[primitives.scala:77:20, :78:22] wire [1:0] _reduced4CExtra_T_5 = _reduced4CExtra_T_4[1:0]; // @[primitives.scala:77:20] wire _reduced4CExtra_T_6 = _reduced4CExtra_T_5[0]; // @[primitives.scala:77:20] wire _reduced4CExtra_T_7 = _reduced4CExtra_T_5[1]; // @[primitives.scala:77:20] wire [1:0] _reduced4CExtra_T_8 = {_reduced4CExtra_T_6, _reduced4CExtra_T_7}; // @[primitives.scala:77:20] wire [1:0] _reduced4CExtra_T_9 = _reduced4CExtra_T_4[3:2]; // @[primitives.scala:77:20] wire _reduced4CExtra_T_10 = _reduced4CExtra_T_9[0]; // @[primitives.scala:77:20] wire _reduced4CExtra_T_11 = _reduced4CExtra_T_9[1]; // @[primitives.scala:77:20] wire [1:0] _reduced4CExtra_T_12 = {_reduced4CExtra_T_10, _reduced4CExtra_T_11}; // @[primitives.scala:77:20] wire [3:0] _reduced4CExtra_T_13 = {_reduced4CExtra_T_8, _reduced4CExtra_T_12}; // @[primitives.scala:77:20] wire [1:0] _reduced4CExtra_T_14 = _reduced4CExtra_T_3[5:4]; // @[primitives.scala:77:20, :78:22] wire _reduced4CExtra_T_15 = _reduced4CExtra_T_14[0]; // @[primitives.scala:77:20] wire _reduced4CExtra_T_16 = _reduced4CExtra_T_14[1]; // @[primitives.scala:77:20] wire [1:0] _reduced4CExtra_T_17 = {_reduced4CExtra_T_15, _reduced4CExtra_T_16}; // @[primitives.scala:77:20] wire [5:0] _reduced4CExtra_T_18 = {_reduced4CExtra_T_13, _reduced4CExtra_T_17}; // @[primitives.scala:77:20] wire [6:0] _reduced4CExtra_T_19 = {1'h0, _reduced4CExtra_T_1[5:0] & _reduced4CExtra_T_18}; // @[primitives.scala:77:20, :124:20] wire reduced4CExtra = \|_reduced4CExtra_T_19; // @[MulAddRecFN.scala:122:68, :130:11] wire [74:0] _alignedSigC_T = mainAlignedSigC[77:3]; // @[MulAddRecFN.scala:120:100, :132:28] wire [74:0] alignedSigC_hi = _alignedSigC_T; // @[MulAddRecFN.scala:132:{12,28}] wire [2:0] _alignedSigC_T_1 = mainAlignedSigC[2:0]; // @[MulAddRecFN.scala:120:100, :134:32] wire [2:0] _alignedSigC_T_5 = mainAlignedSigC[2:0]; // @[MulAddRecFN.scala:120:100, :134:32, :135:32] wire _alignedSigC_T_2 = &_alignedSigC_T_1; // @[MulAddRecFN.scala:134:{32,39}] wire _alignedSigC_T_3 = ~reduced4CExtra; // @[MulAddRecFN.scala:130:11, :134:47] wire _alignedSigC_T_4 = _alignedSigC_T_2 & _alignedSigC_T_3; // @[MulAddRecFN.scala:134:{39,44,47}] wire _alignedSigC_T_6 = \|_alignedSigC_T_5; // @[MulAddRecFN.scala:135:{32,39}] wire _alignedSigC_T_7 = _alignedSigC_T_6 \| reduced4CExtra; // @[MulAddRecFN.scala:130:11, :135:{39,44}] wire _alignedSigC_T_8 = doSubMags ? _alignedSigC_T_4 : _alignedSigC_T_7; // @[MulAddRecFN.scala:102:42, :133:16, :134:44, :135:44] wire [75:0] alignedSigC = {alignedSigC_hi, _alignedSigC_T_8}; // @[MulAddRecFN.scala:132:12, :133:16] assign io_mulAddA_0 = rawA_sig[23:0]; // @[rawFloatFromRecFN.scala:55:23] assign _io_mulAddC_T = alignedSigC[48:1]; // @[MulAddRecFN.scala:132:12, :143:30] assign io_mulAddC_0 = _io_mulAddC_T; // @[MulAddRecFN.scala:71:7, :143:30] wire _io_toPostMul_isSigNaNAny_T = rawA_sig[22]; // @[rawFloatFromRecFN.scala:55:23] wire _io_toPostMul_isSigNaNAny_T_1 = ~_io_toPostMul_isSigNaNAny_T; // @[common.scala:82:{49,56}] wire _io_toPostMul_isSigNaNAny_T_2 = rawA_isNaN & _io_toPostMul_isSigNaNAny_T_1; // @[rawFloatFromRecFN.scala:55:23] wire _io_toPostMul_isSigNaNAny_T_6 = _io_toPostMul_isSigNaNAny_T_2; // @[common.scala:82:46] wire _io_toPostMul_isSigNaNAny_T_7 = rawC_sig[22]; // @[rawFloatFromRecFN.scala:55:23] wire _io_toPostMul_isSigNaNAny_T_8 = ~_io_toPostMul_isSigNaNAny_T_7; // @[common.scala:82:{49,56}] wire _io_toPostMul_isSigNaNAny_T_9 = rawC_isNaN & _io_toPostMul_isSigNaNAny_T_8; // @[rawFloatFromRecFN.scala:55:23] assign _io_toPostMul_isSigNaNAny_T_10 = _io_toPostMul_isSigNaNAny_T_6 \| _io_toPostMul_isSigNaNAny_T_9; // @[common.scala:82:46] assign io_toPostMul_isSigNaNAny_0 = _io_toPostMul_isSigNaNAny_T_10; // @[MulAddRecFN.scala:71:7, :146:58] assign io_toPostMul_isNaNAOrB_0 = _io_toPostMul_isNaNAOrB_T; // @[MulAddRecFN.scala:71:7, :148:42] wire [11:0] _io_toPostMul_sExpSum_T = _GEN - 12'h18; // @[MulAddRecFN.scala:106:42, :158:53] wire [10:0] _io_toPostMul_sExpSum_T_1 = _io_toPostMul_sExpSum_T[10:0]; // @[MulAddRecFN.scala:158:53] wire [10:0] _io_toPostMul_sExpSum_T_2 = _io_toPostMul_sExpSum_T_1; // @[MulAddRecFN.scala:158:53] wire [10:0] _io_toPostMul_sExpSum_T_3 = CIsDominant ? {rawC_sExp[9], rawC_sExp} : _io_toPostMul_sExpSum_T_2; // @[rawFloatFromRecFN.scala:55:23] assign io_toPostMul_sExpSum_0 = _io_toPostMul_sExpSum_T_3[9:0]; // @[MulAddRecFN.scala:71:7, :157:28, :158:12] assign _io_toPostMul_CDom_CAlignDist_T = CAlignDist[4:0]; // @[MulAddRecFN.scala:112:12, :161:47] assign io_toPostMul_CDom_CAlignDist_0 = _io_toPostMul_CDom_CAlignDist_T; // @[MulAddRecFN.scala:71:7, :161:47] assign _io_toPostMul_highAlignedSigC_T = alignedSigC[74:49]; // @[MulAddRecFN.scala:132:12, :163:20] assign io_toPostMul_highAlignedSigC_0 = _io_toPostMul_highAlignedSigC_T; // @[MulAddRecFN.scala:71:7, :163:20] assign _io_toPostMul_bit0AlignedSigC_T = alignedSigC[0]; // @[MulAddRecFN.scala:132:12, :164:48] assign io_toPostMul_bit0AlignedSigC_0 = _io_toPostMul_bit0AlignedSigC_T; // @[MulAddRecFN.scala:71:7, :164:48] assign io_mulAddA = io_mulAddA_0; // @[MulAddRecFN.scala:71:7] assign io_mulAddC = io_mulAddC_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_isSigNaNAny = io_toPostMul_isSigNaNAny_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_isNaNAOrB = io_toPostMul_isNaNAOrB_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_isInfA = io_toPostMul_isInfA_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_isZeroA = io_toPostMul_isZeroA_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_signProd = io_toPostMul_signProd_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_isNaNC = io_toPostMul_isNaNC_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_isInfC = io_toPostMul_isInfC_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_isZeroC = io_toPostMul_isZeroC_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_sExpSum = io_toPostMul_sExpSum_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_doSubMags = io_toPostMul_doSubMags_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_CIsDominant = io_toPostMul_CIsDominant_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_CDom_CAlignDist = io_toPostMul_CDom_CAlignDist_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_highAlignedSigC = io_toPostMul_highAlignedSigC_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_bit0AlignedSigC = io_toPostMul_bit0AlignedSigC_0; // @[MulAddRecFN.scala:71:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File HellaQueue.scala: // See LICENSE.Berkeley for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ class HellaFlowQueue[T <: Data](val entries: Int)(data: => T) extends Module { val io = IO(new QueueIO(data, entries)) require(entries > 1) val do_flow = Wire(Bool()) val do_enq = io.enq.fire && !do_flow val do_deq = io.deq.fire && !do_flow val maybe_full = RegInit(false.B) val enq_ptr = Counter(do_enq, entries)._1 val (deq_ptr, deq_done) = Counter(do_deq, entries) when (do_enq =/= do_deq) { maybe_full := do_enq } val ptr_match = enq_ptr === deq_ptr val empty = ptr_match && !maybe_full val full = ptr_match && maybe_full val atLeastTwo = full \|\| enq_ptr - deq_ptr >= 2.U do_flow := empty && io.deq.ready val ram = SyncReadMem(entries, data) when (do_enq) { ram.write(enq_ptr, io.enq.bits) } // BUG! does not hold the output of the SRAM when !ready // ... However, HellaQueue is correct due to the pipe stage val ren = io.deq.ready && (atLeastTwo \|\| !io.deq.valid && !empty) val raddr = Mux(io.deq.valid, Mux(deq_done, 0.U, deq_ptr + 1.U), deq_ptr) val ram_out_valid = RegNext(ren) io.deq.valid := Mux(empty, io.enq.valid, ram_out_valid) io.enq.ready := !full io.deq.bits := Mux(empty, io.enq.bits, ram.read(raddr, ren)) // Count was never correctly set. To keep the same behavior across chisel3 upgrade, we are explicitly setting it to DontCare io.count := DontCare } class HellaQueue[T <: Data](val entries: Int)(data: => T) extends Module { val io = IO(new QueueIO(data, entries)) val fq = Module(new HellaFlowQueue(entries)(data)) fq.io.enq <> io.enq io.deq <> Queue(fq.io.deq, 1, pipe = true) io.count := fq.io.count } object HellaQueue { def apply[T <: Data](enq: DecoupledIO[T], entries: Int) = { val q = Module((new HellaQueue(entries)) { enq.bits }) q.io.enq.valid := enq.valid // not using <> so that override is allowed q.io.enq.bits := enq.bits enq.ready := q.io.enq.ready q.io.deq } }	module HellaQueue_1( // @[HellaQueue.scala:44:7] input clock, // @[HellaQueue.scala:44:7] input reset, // @[HellaQueue.scala:44:7] output io_enq_ready, // @[HellaQueue.scala:45:14] input io_enq_valid, // @[HellaQueue.scala:45:14] input [63:0] io_enq_bits, // @[HellaQueue.scala:45:14] input io_deq_ready, // @[HellaQueue.scala:45:14] output io_deq_valid, // @[HellaQueue.scala:45:14] output [63:0] io_deq_bits // @[HellaQueue.scala:45:14] ); wire _io_deq_q_io_enq_ready; // @[Decoupled.scala:362:21] wire _fq_io_deq_valid; // @[HellaQueue.scala:47:18] wire [63:0] _fq_io_deq_bits; // @[HellaQueue.scala:47:18] wire io_enq_valid_0 = io_enq_valid; // @[HellaQueue.scala:44:7] wire [63:0] io_enq_bits_0 = io_enq_bits; // @[HellaQueue.scala:44:7] wire io_deq_ready_0 = io_deq_ready; // @[HellaQueue.scala:44:7] wire [6:0] io_count = 7'h0; // @[HellaQueue.scala:44:7, :45:14, :47:18] wire io_enq_ready_0; // @[HellaQueue.scala:44:7] wire io_deq_valid_0; // @[HellaQueue.scala:44:7] wire [63:0] io_deq_bits_0; // @[HellaQueue.scala:44:7] HellaFlowQueue_1 fq ( // @[HellaQueue.scala:47:18] .clock (clock), .reset (reset), .io_enq_ready (io_enq_ready_0), .io_enq_valid (io_enq_valid_0), // @[HellaQueue.scala:44:7] .io_enq_bits (io_enq_bits_0), // @[HellaQueue.scala:44:7] .io_deq_ready (_io_deq_q_io_enq_ready), // @[Decoupled.scala:362:21] .io_deq_valid (_fq_io_deq_valid), .io_deq_bits (_fq_io_deq_bits) ); // @[HellaQueue.scala:47:18] Queue1_UInt64_1 io_deq_q ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (_io_deq_q_io_enq_ready), .io_enq_valid (_fq_io_deq_valid), // @[HellaQueue.scala:47:18] .io_enq_bits (_fq_io_deq_bits), // @[HellaQueue.scala:47:18] .io_deq_ready (io_deq_ready_0), // @[HellaQueue.scala:44:7] .io_deq_valid (io_deq_valid_0), .io_deq_bits (io_deq_bits_0) ); // @[Decoupled.scala:362:21] assign io_enq_ready = io_enq_ready_0; // @[HellaQueue.scala:44:7] assign io_deq_valid = io_deq_valid_0; // @[HellaQueue.scala:44:7] assign io_deq_bits = io_deq_bits_0; // @[HellaQueue.scala:44:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File ShiftReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ // Similar to the Chisel ShiftRegister but allows the user to suggest a // name to the registers that get instantiated, and // to provide a reset value. object ShiftRegInit { def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T = (0 until n).foldRight(in) { case (i, next) => { val r = RegNext(next, init) name.foreach { na => r.suggestName(s"${na}_${i}") } r } } } /** These wrap behavioral * shift registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * The different types vary in their reset behavior: * AsyncResetShiftReg -- Asynchronously reset register array * A W(width) x D(depth) sized array is constructed from D instantiations of a * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg, * but only used for timing applications */ abstract class AbstractPipelineReg(w: Int = 1) extends Module { val io = IO(new Bundle { val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) } ) } object AbstractPipelineReg { def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = { val chain = Module(gen) name.foreach{ chain.suggestName(_) } chain.io.d := in.asUInt chain.io.q.asTypeOf(in) } } class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) { require(depth > 0, "Depth must be greater than 0.") override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}" val chain = List.tabulate(depth) { i => Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}") } chain.last.io.d := io.d chain.last.io.en := true.B (chain.init zip chain.tail).foreach { case (sink, source) => sink.io.d := source.io.q sink.io.en := true.B } io.q := chain.head.io.q } object AsyncResetShiftReg { def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name) def apply [T <: Data](in: T, depth: Int, name: Option[String]): T = apply(in, depth, 0, name) def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T = apply(in, depth, init.litValue.toInt, name) def apply [T <: Data](in: T, depth: Int, init: T): T = apply (in, depth, init.litValue.toInt, None) } File AsyncQueue.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ case class AsyncQueueParams( depth: Int = 8, sync: Int = 3, safe: Boolean = true, // If safe is true, then effort is made to resynchronize the crossing indices when either side is reset. // This makes it safe/possible to reset one side of the crossing (but not the other) when the queue is empty. narrow: Boolean = false) // If narrow is true then the read mux is moved to the source side of the crossing. // This reduces the number of level shifters in the case where the clock crossing is also a voltage crossing, // at the expense of a combinational path from the sink to the source and back to the sink. { require (depth > 0 && isPow2(depth)) require (sync >= 2) val bits = log2Ceil(depth) val wires = if (narrow) 1 else depth } object AsyncQueueParams { // When there is only one entry, we don't need narrow. def singleton(sync: Int = 3, safe: Boolean = true) = AsyncQueueParams(1, sync, safe, false) } class AsyncBundleSafety extends Bundle { val ridx_valid = Input (Bool()) val widx_valid = Output(Bool()) val source_reset_n = Output(Bool()) val sink_reset_n = Input (Bool()) } class AsyncBundle[T <: Data](private val gen: T, val params: AsyncQueueParams = AsyncQueueParams()) extends Bundle { // Data-path synchronization val mem = Output(Vec(params.wires, gen)) val ridx = Input (UInt((params.bits+1).W)) val widx = Output(UInt((params.bits+1).W)) val index = params.narrow.option(Input(UInt(params.bits.W))) // Signals used to self-stabilize a safe AsyncQueue val safe = params.safe.option(new AsyncBundleSafety) } object GrayCounter { def apply(bits: Int, increment: Bool = true.B, clear: Bool = false.B, name: String = "binary"): UInt = { val incremented = Wire(UInt(bits.W)) val binary = RegNext(next=incremented, init=0.U).suggestName(name) incremented := Mux(clear, 0.U, binary + increment.asUInt) incremented ^ (incremented >> 1) } } class AsyncValidSync(sync: Int, desc: String) extends RawModule { val io = IO(new Bundle { val in = Input(Bool()) val out = Output(Bool()) }) val clock = IO(Input(Clock())) val reset = IO(Input(AsyncReset())) withClockAndReset(clock, reset){ io.out := AsyncResetSynchronizerShiftReg(io.in, sync, Some(desc)) } } class AsyncQueueSource[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module { override def desiredName = s"AsyncQueueSource_${gen.typeName}" val io = IO(new Bundle { // These come from the source domain val enq = Flipped(Decoupled(gen)) // These cross to the sink clock domain val async = new AsyncBundle(gen, params) }) val bits = params.bits val sink_ready = WireInit(true.B) val mem = Reg(Vec(params.depth, gen)) // This does NOT need to be reset at all. val widx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.enq.fire, !sink_ready, "widx_bin")) val ridx = AsyncResetSynchronizerShiftReg(io.async.ridx, params.sync, Some("ridx_gray")) val ready = sink_ready && widx =/= (ridx ^ (params.depth \| params.depth >> 1).U) val index = if (bits == 0) 0.U else io.async.widx(bits-1, 0) ^ (io.async.widx(bits, bits) << (bits-1)) when (io.enq.fire) { mem(index) := io.enq.bits } val ready_reg = withReset(reset.asAsyncReset)(RegNext(next=ready, init=false.B).suggestName("ready_reg")) io.enq.ready := ready_reg && sink_ready val widx_reg = withReset(reset.asAsyncReset)(RegNext(next=widx, init=0.U).suggestName("widx_gray")) io.async.widx := widx_reg io.async.index match { case Some(index) => io.async.mem(0) := mem(index) case None => io.async.mem := mem } io.async.safe.foreach { sio => val source_valid_0 = Module(new AsyncValidSync(params.sync, "source_valid_0")) val source_valid_1 = Module(new AsyncValidSync(params.sync, "source_valid_1")) val sink_extend = Module(new AsyncValidSync(params.sync, "sink_extend")) val sink_valid = Module(new AsyncValidSync(params.sync, "sink_valid")) source_valid_0.reset := (reset.asBool \|\| !sio.sink_reset_n).asAsyncReset source_valid_1.reset := (reset.asBool \|\| !sio.sink_reset_n).asAsyncReset sink_extend .reset := (reset.asBool \|\| !sio.sink_reset_n).asAsyncReset sink_valid .reset := reset.asAsyncReset source_valid_0.clock := clock source_valid_1.clock := clock sink_extend .clock := clock sink_valid .clock := clock source_valid_0.io.in := true.B source_valid_1.io.in := source_valid_0.io.out sio.widx_valid := source_valid_1.io.out sink_extend.io.in := sio.ridx_valid sink_valid.io.in := sink_extend.io.out sink_ready := sink_valid.io.out sio.source_reset_n := !reset.asBool // Assert that if there is stuff in the queue, then reset cannot happen // Impossible to write because dequeue can occur on the receiving side, // then reset allowed to happen, but write side cannot know that dequeue // occurred. // TODO: write some sort of sanity check assertion for users // that denote don't reset when there is activity // assert (!(reset \|\| !sio.sink_reset_n) \|\| !io.enq.valid, "Enqueue while sink is reset and AsyncQueueSource is unprotected") // assert (!reset_rise \|\| prev_idx_match.asBool, "Sink reset while AsyncQueueSource not empty") } } class AsyncQueueSink[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module { override def desiredName = s"AsyncQueueSink_${gen.typeName}" val io = IO(new Bundle { // These come from the sink domain val deq = Decoupled(gen) // These cross to the source clock domain val async = Flipped(new AsyncBundle(gen, params)) }) val bits = params.bits val source_ready = WireInit(true.B) val ridx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.deq.fire, !source_ready, "ridx_bin")) val widx = AsyncResetSynchronizerShiftReg(io.async.widx, params.sync, Some("widx_gray")) val valid = source_ready && ridx =/= widx // The mux is safe because timing analysis ensures ridx has reached the register // On an ASIC, changes to the unread location cannot affect the selected value // On an FPGA, only one input changes at a time => mem updates don't cause glitches // The register only latches when the selected valued is not being written val index = if (bits == 0) 0.U else ridx(bits-1, 0) ^ (ridx(bits, bits) << (bits-1)) io.async.index.foreach { _ := index } // This register does not NEED to be reset, as its contents will not // be considered unless the asynchronously reset deq valid register is set. // It is possible that bits latches when the source domain is reset / has power cut // This is safe, because isolation gates brought mem low before the zeroed widx reached us val deq_bits_nxt = io.async.mem(if (params.narrow) 0.U else index) io.deq.bits := ClockCrossingReg(deq_bits_nxt, en = valid, doInit = false, name = Some("deq_bits_reg")) val valid_reg = withReset(reset.asAsyncReset)(RegNext(next=valid, init=false.B).suggestName("valid_reg")) io.deq.valid := valid_reg && source_ready val ridx_reg = withReset(reset.asAsyncReset)(RegNext(next=ridx, init=0.U).suggestName("ridx_gray")) io.async.ridx := ridx_reg io.async.safe.foreach { sio => val sink_valid_0 = Module(new AsyncValidSync(params.sync, "sink_valid_0")) val sink_valid_1 = Module(new AsyncValidSync(params.sync, "sink_valid_1")) val source_extend = Module(new AsyncValidSync(params.sync, "source_extend")) val source_valid = Module(new AsyncValidSync(params.sync, "source_valid")) sink_valid_0 .reset := (reset.asBool \|\| !sio.source_reset_n).asAsyncReset sink_valid_1 .reset := (reset.asBool \|\| !sio.source_reset_n).asAsyncReset source_extend.reset := (reset.asBool \|\| !sio.source_reset_n).asAsyncReset source_valid .reset := reset.asAsyncReset sink_valid_0 .clock := clock sink_valid_1 .clock := clock source_extend.clock := clock source_valid .clock := clock sink_valid_0.io.in := true.B sink_valid_1.io.in := sink_valid_0.io.out sio.ridx_valid := sink_valid_1.io.out source_extend.io.in := sio.widx_valid source_valid.io.in := source_extend.io.out source_ready := source_valid.io.out sio.sink_reset_n := !reset.asBool // TODO: write some sort of sanity check assertion for users // that denote don't reset when there is activity // // val reset_and_extend = !source_ready \|\| !sio.source_reset_n \|\| reset.asBool // val reset_and_extend_prev = RegNext(reset_and_extend, true.B) // val reset_rise = !reset_and_extend_prev && reset_and_extend // val prev_idx_match = AsyncResetReg(updateData=(io.async.widx===io.async.ridx), resetData=0) // assert (!reset_rise \|\| prev_idx_match.asBool, "Source reset while AsyncQueueSink not empty") } } object FromAsyncBundle { // Sometimes it makes sense for the sink to have different sync than the source def apply[T <: Data](x: AsyncBundle[T]): DecoupledIO[T] = apply(x, x.params.sync) def apply[T <: Data](x: AsyncBundle[T], sync: Int): DecoupledIO[T] = { val sink = Module(new AsyncQueueSink(chiselTypeOf(x.mem(0)), x.params.copy(sync = sync))) sink.io.async <> x sink.io.deq } } object ToAsyncBundle { def apply[T <: Data](x: ReadyValidIO[T], params: AsyncQueueParams = AsyncQueueParams()): AsyncBundle[T] = { val source = Module(new AsyncQueueSource(chiselTypeOf(x.bits), params)) source.io.enq <> x source.io.async } } class AsyncQueue[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Crossing[T] { val io = IO(new CrossingIO(gen)) val source = withClockAndReset(io.enq_clock, io.enq_reset) { Module(new AsyncQueueSource(gen, params)) } val sink = withClockAndReset(io.deq_clock, io.deq_reset) { Module(new AsyncQueueSink (gen, params)) } source.io.enq <> io.enq io.deq <> sink.io.deq sink.io.async <> source.io.async }	module AsyncValidSync_115( // @[AsyncQueue.scala:58:7] input io_in, // @[AsyncQueue.scala:59:14] output io_out, // @[AsyncQueue.scala:59:14] input clock, // @[AsyncQueue.scala:63:17] input reset // @[AsyncQueue.scala:64:17] ); wire io_in_0 = io_in; // @[AsyncQueue.scala:58:7] wire _io_out_WIRE; // @[ShiftReg.scala:48:24] wire io_out_0; // @[AsyncQueue.scala:58:7] assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24] AsyncResetSynchronizerShiftReg_w1_d3_i0_130 io_out_sink_valid ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (reset), .io_d (io_in_0), // @[AsyncQueue.scala:58:7] .io_q (_io_out_WIRE) ); // @[ShiftReg.scala:45:23] assign io_out = io_out_0; // @[AsyncQueue.scala:58:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File Buffer.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.diplomacy.BufferParams class TLBufferNode ( a: BufferParams, b: BufferParams, c: BufferParams, d: BufferParams, e: BufferParams)(implicit valName: ValName) extends TLAdapterNode( clientFn = { p => p.v1copy(minLatency = p.minLatency + b.latency + c.latency) }, managerFn = { p => p.v1copy(minLatency = p.minLatency + a.latency + d.latency) } ) { override lazy val nodedebugstring = s"a:${a.toString}, b:${b.toString}, c:${c.toString}, d:${d.toString}, e:${e.toString}" override def circuitIdentity = List(a,b,c,d,e).forall(_ == BufferParams.none) } class TLBuffer( a: BufferParams, b: BufferParams, c: BufferParams, d: BufferParams, e: BufferParams)(implicit p: Parameters) extends LazyModule { def this(ace: BufferParams, bd: BufferParams)(implicit p: Parameters) = this(ace, bd, ace, bd, ace) def this(abcde: BufferParams)(implicit p: Parameters) = this(abcde, abcde) def this()(implicit p: Parameters) = this(BufferParams.default) val node = new TLBufferNode(a, b, c, d, e) lazy val module = new Impl class Impl extends LazyModuleImp(this) { def headBundle = node.out.head._2.bundle override def desiredName = (Seq("TLBuffer") ++ node.out.headOption.map(_._2.bundle.shortName)).mkString("_") (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out.a <> a(in .a) in .d <> d(out.d) if (edgeOut.manager.anySupportAcquireB && edgeOut.client.anySupportProbe) { in .b <> b(out.b) out.c <> c(in .c) out.e <> e(in .e) } else { in.b.valid := false.B in.c.ready := true.B in.e.ready := true.B out.b.ready := true.B out.c.valid := false.B out.e.valid := false.B } } } } object TLBuffer { def apply() (implicit p: Parameters): TLNode = apply(BufferParams.default) def apply(abcde: BufferParams) (implicit p: Parameters): TLNode = apply(abcde, abcde) def apply(ace: BufferParams, bd: BufferParams)(implicit p: Parameters): TLNode = apply(ace, bd, ace, bd, ace) def apply( a: BufferParams, b: BufferParams, c: BufferParams, d: BufferParams, e: BufferParams)(implicit p: Parameters): TLNode = { val buffer = LazyModule(new TLBuffer(a, b, c, d, e)) buffer.node } def chain(depth: Int, name: Option[String] = None)(implicit p: Parameters): Seq[TLNode] = { val buffers = Seq.fill(depth) { LazyModule(new TLBuffer()) } name.foreach { n => buffers.zipWithIndex.foreach { case (b, i) => b.suggestName(s"${n}_${i}") } } buffers.map(_.node) } def chainNode(depth: Int, name: Option[String] = None)(implicit p: Parameters): TLNode = { chain(depth, name) .reduceLeftOption(_ := _) .getOrElse(TLNameNode("no_buffer")) } } File Nodes.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.nodes._ import freechips.rocketchip.util.{AsyncQueueParams,RationalDirection} case object TLMonitorBuilder extends Field[TLMonitorArgs => TLMonitorBase](args => new TLMonitor(args)) object TLImp extends NodeImp[TLMasterPortParameters, TLSlavePortParameters, TLEdgeOut, TLEdgeIn, TLBundle] { def edgeO(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeOut(pd, pu, p, sourceInfo) def edgeI(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeIn (pd, pu, p, sourceInfo) def bundleO(eo: TLEdgeOut) = TLBundle(eo.bundle) def bundleI(ei: TLEdgeIn) = TLBundle(ei.bundle) def render(ei: TLEdgeIn) = RenderedEdge(colour = "#000000" /* black /, label = (ei.manager.beatBytes 8).toString) override def monitor(bundle: TLBundle, edge: TLEdgeIn): Unit = { val monitor = Module(edge.params(TLMonitorBuilder)(TLMonitorArgs(edge))) monitor.io.in := bundle } override def mixO(pd: TLMasterPortParameters, node: OutwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLMasterPortParameters = pd.v1copy(clients = pd.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }) override def mixI(pu: TLSlavePortParameters, node: InwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLSlavePortParameters = pu.v1copy(managers = pu.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }) } trait TLFormatNode extends FormatNode[TLEdgeIn, TLEdgeOut] case class TLClientNode(portParams: Seq[TLMasterPortParameters])(implicit valName: ValName) extends SourceNode(TLImp)(portParams) with TLFormatNode case class TLManagerNode(portParams: Seq[TLSlavePortParameters])(implicit valName: ValName) extends SinkNode(TLImp)(portParams) with TLFormatNode case class TLAdapterNode( clientFn: TLMasterPortParameters => TLMasterPortParameters = { s => s }, managerFn: TLSlavePortParameters => TLSlavePortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLImp)(clientFn, managerFn) with TLFormatNode case class TLJunctionNode( clientFn: Seq[TLMasterPortParameters] => Seq[TLMasterPortParameters], managerFn: Seq[TLSlavePortParameters] => Seq[TLSlavePortParameters])( implicit valName: ValName) extends JunctionNode(TLImp)(clientFn, managerFn) with TLFormatNode case class TLIdentityNode()(implicit valName: ValName) extends IdentityNode(TLImp)() with TLFormatNode object TLNameNode { def apply(name: ValName) = TLIdentityNode()(name) def apply(name: Option[String]): TLIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLIdentityNode = apply(Some(name)) } case class TLEphemeralNode()(implicit valName: ValName) extends EphemeralNode(TLImp)() object TLTempNode { def apply(): TLEphemeralNode = TLEphemeralNode()(ValName("temp")) } case class TLNexusNode( clientFn: Seq[TLMasterPortParameters] => TLMasterPortParameters, managerFn: Seq[TLSlavePortParameters] => TLSlavePortParameters)( implicit valName: ValName) extends NexusNode(TLImp)(clientFn, managerFn) with TLFormatNode abstract class TLCustomNode(implicit valName: ValName) extends CustomNode(TLImp) with TLFormatNode // Asynchronous crossings trait TLAsyncFormatNode extends FormatNode[TLAsyncEdgeParameters, TLAsyncEdgeParameters] object TLAsyncImp extends SimpleNodeImp[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncEdgeParameters, TLAsyncBundle] { def edge(pd: TLAsyncClientPortParameters, pu: TLAsyncManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLAsyncEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLAsyncEdgeParameters) = new TLAsyncBundle(e.bundle) def render(e: TLAsyncEdgeParameters) = RenderedEdge(colour = "#ff0000" /* red /, label = e.manager.async.depth.toString) override def mixO(pd: TLAsyncClientPortParameters, node: OutwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLAsyncManagerPortParameters, node: InwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLAsyncAdapterNode( clientFn: TLAsyncClientPortParameters => TLAsyncClientPortParameters = { s => s }, managerFn: TLAsyncManagerPortParameters => TLAsyncManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLAsyncImp)(clientFn, managerFn) with TLAsyncFormatNode case class TLAsyncIdentityNode()(implicit valName: ValName) extends IdentityNode(TLAsyncImp)() with TLAsyncFormatNode object TLAsyncNameNode { def apply(name: ValName) = TLAsyncIdentityNode()(name) def apply(name: Option[String]): TLAsyncIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLAsyncIdentityNode = apply(Some(name)) } case class TLAsyncSourceNode(sync: Option[Int])(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLAsyncImp)( dFn = { p => TLAsyncClientPortParameters(p) }, uFn = { p => p.base.v1copy(minLatency = p.base.minLatency + sync.getOrElse(p.async.sync)) }) with FormatNode[TLEdgeIn, TLAsyncEdgeParameters] // discard cycles in other clock domain case class TLAsyncSinkNode(async: AsyncQueueParams)(implicit valName: ValName) extends MixedAdapterNode(TLAsyncImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = p.base.minLatency + async.sync) }, uFn = { p => TLAsyncManagerPortParameters(async, p) }) with FormatNode[TLAsyncEdgeParameters, TLEdgeOut] // Rationally related crossings trait TLRationalFormatNode extends FormatNode[TLRationalEdgeParameters, TLRationalEdgeParameters] object TLRationalImp extends SimpleNodeImp[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalEdgeParameters, TLRationalBundle] { def edge(pd: TLRationalClientPortParameters, pu: TLRationalManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLRationalEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLRationalEdgeParameters) = new TLRationalBundle(e.bundle) def render(e: TLRationalEdgeParameters) = RenderedEdge(colour = "#00ff00" / green /) override def mixO(pd: TLRationalClientPortParameters, node: OutwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLRationalManagerPortParameters, node: InwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLRationalAdapterNode( clientFn: TLRationalClientPortParameters => TLRationalClientPortParameters = { s => s }, managerFn: TLRationalManagerPortParameters => TLRationalManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLRationalImp)(clientFn, managerFn) with TLRationalFormatNode case class TLRationalIdentityNode()(implicit valName: ValName) extends IdentityNode(TLRationalImp)() with TLRationalFormatNode object TLRationalNameNode { def apply(name: ValName) = TLRationalIdentityNode()(name) def apply(name: Option[String]): TLRationalIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLRationalIdentityNode = apply(Some(name)) } case class TLRationalSourceNode()(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLRationalImp)( dFn = { p => TLRationalClientPortParameters(p) }, uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLRationalEdgeParameters] // discard cycles from other clock domain case class TLRationalSinkNode(direction: RationalDirection)(implicit valName: ValName) extends MixedAdapterNode(TLRationalImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = 1) }, uFn = { p => TLRationalManagerPortParameters(direction, p) }) with FormatNode[TLRationalEdgeParameters, TLEdgeOut] // Credited version of TileLink channels trait TLCreditedFormatNode extends FormatNode[TLCreditedEdgeParameters, TLCreditedEdgeParameters] object TLCreditedImp extends SimpleNodeImp[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedEdgeParameters, TLCreditedBundle] { def edge(pd: TLCreditedClientPortParameters, pu: TLCreditedManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLCreditedEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLCreditedEdgeParameters) = new TLCreditedBundle(e.bundle) def render(e: TLCreditedEdgeParameters) = RenderedEdge(colour = "#ffff00" / yellow /, e.delay.toString) override def mixO(pd: TLCreditedClientPortParameters, node: OutwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLCreditedManagerPortParameters, node: InwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLCreditedAdapterNode( clientFn: TLCreditedClientPortParameters => TLCreditedClientPortParameters = { s => s }, managerFn: TLCreditedManagerPortParameters => TLCreditedManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLCreditedImp)(clientFn, managerFn) with TLCreditedFormatNode case class TLCreditedIdentityNode()(implicit valName: ValName) extends IdentityNode(TLCreditedImp)() with TLCreditedFormatNode object TLCreditedNameNode { def apply(name: ValName) = TLCreditedIdentityNode()(name) def apply(name: Option[String]): TLCreditedIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLCreditedIdentityNode = apply(Some(name)) } case class TLCreditedSourceNode(delay: TLCreditedDelay)(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLCreditedImp)( dFn = { p => TLCreditedClientPortParameters(delay, p) }, uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLCreditedEdgeParameters] // discard cycles from other clock domain case class TLCreditedSinkNode(delay: TLCreditedDelay)(implicit valName: ValName) extends MixedAdapterNode(TLCreditedImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = 1) }, uFn = { p => TLCreditedManagerPortParameters(delay, p) }) with FormatNode[TLCreditedEdgeParameters, TLEdgeOut] File LazyModuleImp.scala: package org.chipsalliance.diplomacy.lazymodule import chisel3.{withClockAndReset, Module, RawModule, Reset, _} import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo} import firrtl.passes.InlineAnnotation import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.nodes.Dangle import scala.collection.immutable.SortedMap /* Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]]. * * This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy. / sealed trait LazyModuleImpLike extends RawModule { /* [[LazyModule]] that contains this instance. / val wrapper: LazyModule /* IOs that will be automatically "punched" for this instance. / val auto: AutoBundle /* The metadata that describes the [[HalfEdge]]s which generated [[auto]]. / protected[diplomacy] val dangles: Seq[Dangle] // [[wrapper.module]] had better not be accessed while LazyModules are still being built! require( LazyModule.scope.isEmpty, s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}" ) /* Set module name. Defaults to the containing LazyModule's desiredName. / override def desiredName: String = wrapper.desiredName suggestName(wrapper.suggestedName) /* [[Parameters]] for chisel [[Module]]s. / implicit val p: Parameters = wrapper.p /* instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and * submodules. / protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = { // 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]], // 2. return [[Dangle]]s from each module. val childDangles = wrapper.children.reverse.flatMap { c => implicit val sourceInfo: SourceInfo = c.info c.cloneProto.map { cp => // If the child is a clone, then recursively set cloneProto of its children as well def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = { require(bases.size == clones.size) (bases.zip(clones)).map { case (l, r) => require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}") l.cloneProto = Some(r) assignCloneProtos(l.children, r.children) } } assignCloneProtos(c.children, cp.children) // Clone the child module as a record, and get its [[AutoBundle]] val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName) val clonedAuto = clone("auto").asInstanceOf[AutoBundle] // Get the empty [[Dangle]]'s of the cloned child val rawDangles = c.cloneDangles() require(rawDangles.size == clonedAuto.elements.size) // Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) } dangles }.getOrElse { // For non-clones, instantiate the child module val mod = try { Module(c.module) } catch { case e: ChiselException => { println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}") throw e } } mod.dangles } } // Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]]. // This will result in a sequence of [[Dangle]] from these [[BaseNode]]s. val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate()) // Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]] val allDangles = nodeDangles ++ childDangles // Group [[allDangles]] by their [[source]]. val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _) // For each [[source]] set of [[Dangle]]s of size 2, ensure that these // can be connected as a source-sink pair (have opposite flipped value). // Make the connection and mark them as [[done]]. val done = Set() ++ pairing.values.filter(_.size == 2).map { case Seq(a, b) => require(a.flipped != b.flipped) // @todo <> in chisel3 makes directionless connection. if (a.flipped) { a.data <> b.data } else { b.data <> a.data } a.source case _ => None } // Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module. val forward = allDangles.filter(d => !done(d.source)) // Generate [[AutoBundle]] IO from [[forward]]. val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _)) // Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]] val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) => if (d.flipped) { d.data <> io } else { io <> d.data } d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name) } // Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]]. wrapper.inModuleBody.reverse.foreach { _() } if (wrapper.shouldBeInlined) { chisel3.experimental.annotate(new ChiselAnnotation { def toFirrtl = InlineAnnotation(toNamed) }) } // Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]]. (auto, dangles) } } /* Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. / class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike { /* Instantiate hardware of this `Module`. / val (auto, dangles) = instantiate() } /* Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. / class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike { // These wires are the default clock+reset for all LazyModule children. // It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the // [[LazyRawModuleImp]] children. // Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly. /* drive clock explicitly. / val childClock: Clock = Wire(Clock()) /* drive reset explicitly. / val childReset: Reset = Wire(Reset()) // the default is that these are disabled childClock := false.B.asClock childReset := chisel3.DontCare def provideImplicitClockToLazyChildren: Boolean = false val (auto, dangles) = if (provideImplicitClockToLazyChildren) { withClockAndReset(childClock, childReset) { instantiate() } } else { instantiate() } } File MixedNode.scala: package org.chipsalliance.diplomacy.nodes import chisel3.{Data, DontCare, Wire} import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.{Field, Parameters} import org.chipsalliance.diplomacy.ValName import org.chipsalliance.diplomacy.sourceLine /* One side metadata of a [[Dangle]]. * * Describes one side of an edge going into or out of a [[BaseNode]]. * * @param serial * the global [[BaseNode.serial]] number of the [[BaseNode]] that this [[HalfEdge]] connects to. * @param index * the `index` in the [[BaseNode]]'s input or output port list that this [[HalfEdge]] belongs to. / case class HalfEdge(serial: Int, index: Int) extends Ordered[HalfEdge] { import scala.math.Ordered.orderingToOrdered def compare(that: HalfEdge): Int = HalfEdge.unapply(this).compare(HalfEdge.unapply(that)) } /* [[Dangle]] captures the `IO` information of a [[LazyModule]] and which two [[BaseNode]]s the [[Edges]]/[[Bundle]] * connects. * * [[Dangle]]s are generated by [[BaseNode.instantiate]] using [[MixedNode.danglesOut]] and [[MixedNode.danglesIn]] , * [[LazyModuleImp.instantiate]] connects those that go to internal or explicit IO connections in a [[LazyModule]]. * * @param source * the source [[HalfEdge]] of this [[Dangle]], which captures the source [[BaseNode]] and the port `index` within * that [[BaseNode]]. * @param sink * sink [[HalfEdge]] of this [[Dangle]], which captures the sink [[BaseNode]] and the port `index` within that * [[BaseNode]]. * @param flipped * flip or not in [[AutoBundle.makeElements]]. If true this corresponds to `danglesOut`, if false it corresponds to * `danglesIn`. * @param dataOpt * actual [[Data]] for the hardware connection. Can be empty if this belongs to a cloned module / case class Dangle(source: HalfEdge, sink: HalfEdge, flipped: Boolean, name: String, dataOpt: Option[Data]) { def data = dataOpt.get } /* [[Edges]] is a collection of parameters describing the functionality and connection for an interface, which is often * derived from the interconnection protocol and can inform the parameterization of the hardware bundles that actually * implement the protocol. / case class Edges[EI, EO](in: Seq[EI], out: Seq[EO]) /* A field available in [[Parameters]] used to determine whether [[InwardNodeImp.monitor]] will be called. / case object MonitorsEnabled extends Field[Boolean](true) /* When rendering the edge in a graphical format, flip the order in which the edges' source and sink are presented. * * For example, when rendering graphML, yEd by default tries to put the source node vertically above the sink node, but * [[RenderFlipped]] inverts this relationship. When a particular [[LazyModule]] contains both source nodes and sink * nodes, flipping the rendering of one node's edge will usual produce a more concise visual layout for the * [[LazyModule]]. / case object RenderFlipped extends Field[Boolean](false) /* The sealed node class in the package, all node are derived from it. * * @param inner * Sink interface implementation. * @param outer * Source interface implementation. * @param valName * val name of this node. * @tparam DI * Downward-flowing parameters received on the inner side of the node. It is usually a brunch of parameters * describing the protocol parameters from a source. For an [[InwardNode]], it is determined by the connected * [[OutwardNode]]. Since it can be connected to multiple sources, this parameter is always a Seq of source port * parameters. * @tparam UI * Upward-flowing parameters generated by the inner side of the node. It is usually a brunch of parameters describing * the protocol parameters of a sink. For an [[InwardNode]], it is determined itself. * @tparam EI * Edge Parameters describing a connection on the inner side of the node. It is usually a brunch of transfers * specified for a sink according to protocol. * @tparam BI * Bundle type used when connecting to the inner side of the node. It is a hardware interface of this sink interface. * It should extends from [[chisel3.Data]], which represents the real hardware. * @tparam DO * Downward-flowing parameters generated on the outer side of the node. It is usually a brunch of parameters * describing the protocol parameters of a source. For an [[OutwardNode]], it is determined itself. * @tparam UO * Upward-flowing parameters received by the outer side of the node. It is usually a brunch of parameters describing * the protocol parameters from a sink. For an [[OutwardNode]], it is determined by the connected [[InwardNode]]. * Since it can be connected to multiple sinks, this parameter is always a Seq of sink port parameters. * @tparam EO * Edge Parameters describing a connection on the outer side of the node. It is usually a brunch of transfers * specified for a source according to protocol. * @tparam BO * Bundle type used when connecting to the outer side of the node. It is a hardware interface of this source * interface. It should extends from [[chisel3.Data]], which represents the real hardware. * * @note * Call Graph of [[MixedNode]] * - line `─`: source is process by a function and generate pass to others * - Arrow `→`: target of arrow is generated by source * * {{{ * (from the other node) * ┌─────────────────────────────────────────────────────────[[InwardNode.uiParams]]─────────────┐ * ↓ │ * (binding node when elaboration) [[OutwardNode.uoParams]]────────────────────────[[MixedNode.mapParamsU]]→──────────┐ │ * [[InwardNode.accPI]] │ │ │ * │ │ (based on protocol) │ * │ │ [[MixedNode.inner.edgeI]] │ * │ │ ↓ │ * ↓ │ │ │ * (immobilize after elaboration) (inward port from [[OutwardNode]]) │ ↓ │ * [[InwardNode.iBindings]]──┐ [[MixedNode.iDirectPorts]]────────────────────→[[MixedNode.iPorts]] [[InwardNode.uiParams]] │ * │ │ ↑ │ │ │ * │ │ │ [[OutwardNode.doParams]] │ │ * │ │ │ (from the other node) │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * │ │ │ └────────┬──────────────┤ │ * │ │ │ │ │ │ * │ │ │ │ (based on protocol) │ * │ │ │ │ [[MixedNode.inner.edgeI]] │ * │ │ │ │ │ │ * │ │ (from the other node) │ ↓ │ * │ └───[[OutwardNode.oPortMapping]] [[OutwardNode.oStar]] │ [[MixedNode.edgesIn]]───┐ │ * │ ↑ ↑ │ │ ↓ │ * │ │ │ │ │ [[MixedNode.in]] │ * │ │ │ │ ↓ ↑ │ * │ (solve star connection) │ │ │ [[MixedNode.bundleIn]]──┘ │ * ├───[[MixedNode.resolveStar]]→─┼─────────────────────────────┤ └────────────────────────────────────┐ │ * │ │ │ [[MixedNode.bundleOut]]─┐ │ │ * │ │ │ ↑ ↓ │ │ * │ │ │ │ [[MixedNode.out]] │ │ * │ ↓ ↓ │ ↑ │ │ * │ ┌─────[[InwardNode.iPortMapping]] [[InwardNode.iStar]] [[MixedNode.edgesOut]]──┘ │ │ * │ │ (from the other node) ↑ │ │ * │ │ │ │ │ │ * │ │ │ [[MixedNode.outer.edgeO]] │ │ * │ │ │ (based on protocol) │ │ * │ │ │ │ │ │ * │ │ │ ┌────────────────────────────────────────┤ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * (immobilize after elaboration)│ ↓ │ │ │ │ * [[OutwardNode.oBindings]]─┘ [[MixedNode.oDirectPorts]]───→[[MixedNode.oPorts]] [[OutwardNode.doParams]] │ │ * ↑ (inward port from [[OutwardNode]]) │ │ │ │ * │ ┌─────────────────────────────────────────┤ │ │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * [[OutwardNode.accPO]] │ ↓ │ │ │ * (binding node when elaboration) │ [[InwardNode.diParams]]─────→[[MixedNode.mapParamsD]]────────────────────────────┘ │ │ * │ ↑ │ │ * │ └──────────────────────────────────────────────────────────────────────────────────────────┘ │ * └──────────────────────────────────────────────────────────────────────────────────────────────────────────┘ * }}} / abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data]( val inner: InwardNodeImp[DI, UI, EI, BI], val outer: OutwardNodeImp[DO, UO, EO, BO] )( implicit valName: ValName) extends BaseNode with NodeHandle[DI, UI, EI, BI, DO, UO, EO, BO] with InwardNode[DI, UI, BI] with OutwardNode[DO, UO, BO] { // Generate a [[NodeHandle]] with inward and outward node are both this node. val inward = this val outward = this /* Debug info of nodes binding. / def bindingInfo: String = s"""$iBindingInfo \|$oBindingInfo \|""".stripMargin /* Debug info of ports connecting. / def connectedPortsInfo: String = s"""${oPorts.size} outward ports connected: [${oPorts.map(_._2.name).mkString(",")}] \|${iPorts.size} inward ports connected: [${iPorts.map(_._2.name).mkString(",")}] \|""".stripMargin /* Debug info of parameters propagations. / def parametersInfo: String = s"""${doParams.size} downstream outward parameters: [${doParams.mkString(",")}] \|${uoParams.size} upstream outward parameters: [${uoParams.mkString(",")}] \|${diParams.size} downstream inward parameters: [${diParams.mkString(",")}] \|${uiParams.size} upstream inward parameters: [${uiParams.mkString(",")}] \|""".stripMargin /* For a given node, converts [[OutwardNode.accPO]] and [[InwardNode.accPI]] to [[MixedNode.oPortMapping]] and * [[MixedNode.iPortMapping]]. * * Given counts of known inward and outward binding and inward and outward star bindings, return the resolved inward * stars and outward stars. * * This method will also validate the arguments and throw a runtime error if the values are unsuitable for this type * of node. * * @param iKnown * Number of known-size ([[BIND_ONCE]]) input bindings. * @param oKnown * Number of known-size ([[BIND_ONCE]]) output bindings. * @param iStar * Number of unknown size ([[BIND_STAR]]) input bindings. * @param oStar * Number of unknown size ([[BIND_STAR]]) output bindings. * @return * A Tuple of the resolved number of input and output connections. / protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStar: Int, oStar: Int): (Int, Int) /* Function to generate downward-flowing outward params from the downward-flowing input params and the current output * ports. * * @param n * The size of the output sequence to generate. * @param p * Sequence of downward-flowing input parameters of this node. * @return * A `n`-sized sequence of downward-flowing output edge parameters. / protected[diplomacy] def mapParamsD(n: Int, p: Seq[DI]): Seq[DO] /* Function to generate upward-flowing input parameters from the upward-flowing output parameters [[uiParams]]. * * @param n * Size of the output sequence. * @param p * Upward-flowing output edge parameters. * @return * A n-sized sequence of upward-flowing input edge parameters. / protected[diplomacy] def mapParamsU(n: Int, p: Seq[UO]): Seq[UI] /* @return * The sink cardinality of the node, the number of outputs bound with [[BIND_QUERY]] summed with inputs bound with * [[BIND_STAR]]. / protected[diplomacy] lazy val sinkCard: Int = oBindings.count(_._3 == BIND_QUERY) + iBindings.count(_._3 == BIND_STAR) /* @return * The source cardinality of this node, the number of inputs bound with [[BIND_QUERY]] summed with the number of * output bindings bound with [[BIND_STAR]]. / protected[diplomacy] lazy val sourceCard: Int = iBindings.count(_._3 == BIND_QUERY) + oBindings.count(_._3 == BIND_STAR) /* @return list of nodes involved in flex bindings with this node. / protected[diplomacy] lazy val flexes: Seq[BaseNode] = oBindings.filter(_._3 == BIND_FLEX).map(_._2) ++ iBindings.filter(_._3 == BIND_FLEX).map(_._2) /* Resolves the flex to be either source or sink and returns the offset where the [[BIND_STAR]] operators begin * greedily taking up the remaining connections. * * @return * A value >= 0 if it is sink cardinality, a negative value for source cardinality. The magnitude of the return * value is not relevant. / protected[diplomacy] lazy val flexOffset: Int = { /* Recursively performs a depth-first search of the [[flexes]], [[BaseNode]]s connected to this node with flex * operators. The algorithm bottoms out when we either get to a node we have already visited or when we get to a * connection that is not a flex and can set the direction for us. Otherwise, recurse by visiting the `flexes` of * each node in the current set and decide whether they should be added to the set or not. * * @return * the mapping of [[BaseNode]] indexed by their serial numbers. / def DFS(v: BaseNode, visited: Map[Int, BaseNode]): Map[Int, BaseNode] = { if (visited.contains(v.serial) \|\| !v.flexibleArityDirection) { visited } else { v.flexes.foldLeft(visited + (v.serial -> v))((sum, n) => DFS(n, sum)) } } /* Determine which [[BaseNode]] are involved in resolving the flex connections to/from this node. * * @example * {{{ * a := b := c * d := b * e := f * }}} * * `flexSet` for `a`, `b`, `c`, or `d` will be `Set(a, b, c, d)` `flexSet` for `e` or `f` will be `Set(e,f)` / val flexSet = DFS(this, Map()).values /* The total number of := operators where we're on the left. / val allSink = flexSet.map(_.sinkCard).sum /** The total number of :=* operators used when we're on the right. / val allSource = flexSet.map(_.sourceCard).sum require( allSink == 0 \|\| allSource == 0, s"The nodes ${flexSet.map(_.name)} which are inter-connected by :=* have ${allSink} := operators and ${allSource} := operators connected to them, making it impossible to determine cardinality inference direction." ) allSink - allSource } /** @return A value >= 0 if it is sink cardinality, a negative value for source cardinality. / protected[diplomacy] def edgeArityDirection(n: BaseNode): Int = { if (flexibleArityDirection) flexOffset else if (n.flexibleArityDirection) n.flexOffset else 0 } /* For a node which is connected between two nodes, select the one that will influence the direction of the flex * resolution. / protected[diplomacy] def edgeAritySelect(n: BaseNode, l: => Int, r: => Int): Int = { val dir = edgeArityDirection(n) if (dir < 0) l else if (dir > 0) r else 1 } /* Ensure that the same node is not visited twice in resolving `:=`, etc operators. / private var starCycleGuard = false /** Resolve all the star operators into concrete indicies. As connections are being made, some may be "star" * connections which need to be resolved. In some way to determine how many actual edges they correspond to. We also * need to build up the ranges of edges which correspond to each binding operator, so that We can apply the correct * edge parameters and later build up correct bundle connections. * * [[oPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that oPort (binding * operator). [[iPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that iPort * (binding operator). [[oStar]]: `Int` the value to return for this node `N` for any `N := foo` or `N :=* foo := bar` [[iStar]]: `Int` the value to return for this node `N` for any `foo :=* N` or `bar :=* foo := N` / protected[diplomacy] lazy val ( oPortMapping: Seq[(Int, Int)], iPortMapping: Seq[(Int, Int)], oStar: Int, iStar: Int ) = { try { if (starCycleGuard) throw StarCycleException() starCycleGuard = true // For a given node N... // Number of foo := N // + Number of bar :=* foo := N val oStars = oBindings.count { case (_, n, b, _, _) => b == BIND_STAR \|\| (b == BIND_FLEX && edgeArityDirection(n) < 0) } // Number of N := foo // + Number of N :=* foo := bar val iStars = iBindings.count { case (_, n, b, _, _) => b == BIND_STAR \|\| (b == BIND_FLEX && edgeArityDirection(n) > 0) } // 1 for foo := N // + bar.iStar for bar := foo := N // + foo.iStar for foo := N // + 0 for foo := N val oKnown = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, 0, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => 0 } }.sum // 1 for N := foo // + bar.oStar for N := foo :=* bar // + foo.oStar for N :=* foo // + 0 for N := foo val iKnown = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, 0) case BIND_QUERY => n.oStar case BIND_STAR => 0 } }.sum // Resolve star depends on the node subclass to implement the algorithm for this. val (iStar, oStar) = resolveStar(iKnown, oKnown, iStars, oStars) // Cumulative list of resolved outward binding range starting points val oSum = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, oStar, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => oStar } }.scanLeft(0)(_ + _) // Cumulative list of resolved inward binding range starting points val iSum = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, iStar) case BIND_QUERY => n.oStar case BIND_STAR => iStar } }.scanLeft(0)(_ + _) // Create ranges for each binding based on the running sums and return // those along with resolved values for the star operations. (oSum.init.zip(oSum.tail), iSum.init.zip(iSum.tail), oStar, iStar) } catch { case c: StarCycleException => throw c.copy(loop = context +: c.loop) } } /* Sequence of inward ports. * * This should be called after all star bindings are resolved. * * Each element is: `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. * `n` Instance of inward node. `p` View of [[Parameters]] where this connection was made. `s` Source info where this * connection was made in the source code. / protected[diplomacy] lazy val oDirectPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oBindings.flatMap { case (i, n, _, p, s) => // for each binding operator in this node, look at what it connects to val (start, end) = n.iPortMapping(i) (start until end).map { j => (j, n, p, s) } } /* Sequence of outward ports. * * This should be called after all star bindings are resolved. * * `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. `n` Instance of * outward node. `p` View of [[Parameters]] where this connection was made. `s` [[SourceInfo]] where this connection * was made in the source code. / protected[diplomacy] lazy val iDirectPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iBindings.flatMap { case (i, n, _, p, s) => // query this port index range of this node in the other side of node. val (start, end) = n.oPortMapping(i) (start until end).map { j => (j, n, p, s) } } // Ephemeral nodes ( which have non-None iForward/oForward) have in_degree = out_degree // Thus, there must exist an Eulerian path and the below algorithms terminate @scala.annotation.tailrec private def oTrace( tuple: (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) ): (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.iForward(i) match { case None => (i, n, p, s) case Some((j, m)) => oTrace((j, m, p, s)) } } @scala.annotation.tailrec private def iTrace( tuple: (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) ): (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.oForward(i) match { case None => (i, n, p, s) case Some((j, m)) => iTrace((j, m, p, s)) } } /* Final output ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - Numeric index of this binding in the [[InwardNode]] on the other end. * - [[InwardNode]] on the other end of this binding. * - A view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. / lazy val oPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oDirectPorts.map(oTrace) /* Final input ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - numeric index of this binding in [[OutwardNode]] on the other end. * - [[OutwardNode]] on the other end of this binding. * - a view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. / lazy val iPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iDirectPorts.map(iTrace) private var oParamsCycleGuard = false protected[diplomacy] lazy val diParams: Seq[DI] = iPorts.map { case (i, n, _, _) => n.doParams(i) } protected[diplomacy] lazy val doParams: Seq[DO] = { try { if (oParamsCycleGuard) throw DownwardCycleException() oParamsCycleGuard = true val o = mapParamsD(oPorts.size, diParams) require( o.size == oPorts.size, s"""Diplomacy has detected a problem with your graph: \|At the following node, the number of outward ports should equal the number of produced outward parameters. \|$context \|$connectedPortsInfo \|Downstreamed inward parameters: [${diParams.mkString(",")}] \|Produced outward parameters: [${o.mkString(",")}] \|""".stripMargin ) o.map(outer.mixO(_, this)) } catch { case c: DownwardCycleException => throw c.copy(loop = context +: c.loop) } } private var iParamsCycleGuard = false protected[diplomacy] lazy val uoParams: Seq[UO] = oPorts.map { case (o, n, _, _) => n.uiParams(o) } protected[diplomacy] lazy val uiParams: Seq[UI] = { try { if (iParamsCycleGuard) throw UpwardCycleException() iParamsCycleGuard = true val i = mapParamsU(iPorts.size, uoParams) require( i.size == iPorts.size, s"""Diplomacy has detected a problem with your graph: \|At the following node, the number of inward ports should equal the number of produced inward parameters. \|$context \|$connectedPortsInfo \|Upstreamed outward parameters: [${uoParams.mkString(",")}] \|Produced inward parameters: [${i.mkString(",")}] \|""".stripMargin ) i.map(inner.mixI(_, this)) } catch { case c: UpwardCycleException => throw c.copy(loop = context +: c.loop) } } /* Outward edge parameters. / protected[diplomacy] lazy val edgesOut: Seq[EO] = (oPorts.zip(doParams)).map { case ((i, n, p, s), o) => outer.edgeO(o, n.uiParams(i), p, s) } /* Inward edge parameters. / protected[diplomacy] lazy val edgesIn: Seq[EI] = (iPorts.zip(uiParams)).map { case ((o, n, p, s), i) => inner.edgeI(n.doParams(o), i, p, s) } /* A tuple of the input edge parameters and output edge parameters for the edges bound to this node. * * If you need to access to the edges of a foreign Node, use this method (in/out create bundles). / lazy val edges: Edges[EI, EO] = Edges(edgesIn, edgesOut) /* Create actual Wires corresponding to the Bundles parameterized by the outward edges of this node. / protected[diplomacy] lazy val bundleOut: Seq[BO] = edgesOut.map { e => val x = Wire(outer.bundleO(e)).suggestName(s"${valName.value}Out") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } /* Create actual Wires corresponding to the Bundles parameterized by the inward edges of this node. / protected[diplomacy] lazy val bundleIn: Seq[BI] = edgesIn.map { e => val x = Wire(inner.bundleI(e)).suggestName(s"${valName.value}In") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } private def emptyDanglesOut: Seq[Dangle] = oPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(serial, i), sink = HalfEdge(n.serial, j), flipped = false, name = wirePrefix + "out", dataOpt = None ) } private def emptyDanglesIn: Seq[Dangle] = iPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(n.serial, j), sink = HalfEdge(serial, i), flipped = true, name = wirePrefix + "in", dataOpt = None ) } /* Create the [[Dangle]]s which describe the connections from this node output to other nodes inputs. / protected[diplomacy] def danglesOut: Seq[Dangle] = emptyDanglesOut.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleOut(i))) } /* Create the [[Dangle]]s which describe the connections from this node input from other nodes outputs. / protected[diplomacy] def danglesIn: Seq[Dangle] = emptyDanglesIn.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleIn(i))) } private[diplomacy] var instantiated = false /* Gather Bundle and edge parameters of outward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. / def out: Seq[(BO, EO)] = { require( instantiated, s"$name.out should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleOut.zip(edgesOut) } /* Gather Bundle and edge parameters of inward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. / def in: Seq[(BI, EI)] = { require( instantiated, s"$name.in should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleIn.zip(edgesIn) } /* Actually instantiate this node during [[LazyModuleImp]] evaluation. Mark that it's safe to use the Bundle wires, * instantiate monitors on all input ports if appropriate, and return all the dangles of this node. / protected[diplomacy] def instantiate(): Seq[Dangle] = { instantiated = true if (!circuitIdentity) { (iPorts.zip(in)).foreach { case ((_, _, p, _), (b, e)) => if (p(MonitorsEnabled)) inner.monitor(b, e) } } danglesOut ++ danglesIn } protected[diplomacy] def cloneDangles(): Seq[Dangle] = emptyDanglesOut ++ emptyDanglesIn /* Connects the outward part of a node with the inward part of this node. / protected[diplomacy] def bind( h: OutwardNode[DI, UI, BI], binding: NodeBinding )( implicit p: Parameters, sourceInfo: SourceInfo ): Unit = { val x = this // x := y val y = h sourceLine(sourceInfo, " at ", "") val i = x.iPushed val o = y.oPushed y.oPush( i, x, binding match { case BIND_ONCE => BIND_ONCE case BIND_FLEX => BIND_FLEX case BIND_STAR => BIND_QUERY case BIND_QUERY => BIND_STAR } ) x.iPush(o, y, binding) } / Metadata for printing the node graph. / def inputs: Seq[(OutwardNode[DI, UI, BI], RenderedEdge)] = (iPorts.zip(edgesIn)).map { case ((_, n, p, _), e) => val re = inner.render(e) (n, re.copy(flipped = re.flipped != p(RenderFlipped))) } /* Metadata for printing the node graph */ def outputs: Seq[(InwardNode[DO, UO, BO], RenderedEdge)] = oPorts.map { case (i, n, _, _) => (n, n.inputs(i)._2) } }	module TLBuffer_a29d64s7k1z3u( // @[Buffer.scala:40:9] input clock, // @[Buffer.scala:40:9] input reset, // @[Buffer.scala:40:9] output auto_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [6:0] auto_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [28:0] auto_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_d_bits_param, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [6:0] auto_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [63:0] auto_in_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [6:0] auto_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [28:0] auto_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [6:0] auto_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input [63:0] auto_out_d_bits_data // @[LazyModuleImp.scala:107:25] ); wire auto_in_a_valid_0 = auto_in_a_valid; // @[Buffer.scala:40:9] wire [2:0] auto_in_a_bits_opcode_0 = auto_in_a_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] auto_in_a_bits_param_0 = auto_in_a_bits_param; // @[Buffer.scala:40:9] wire [2:0] auto_in_a_bits_size_0 = auto_in_a_bits_size; // @[Buffer.scala:40:9] wire [6:0] auto_in_a_bits_source_0 = auto_in_a_bits_source; // @[Buffer.scala:40:9] wire [28:0] auto_in_a_bits_address_0 = auto_in_a_bits_address; // @[Buffer.scala:40:9] wire [7:0] auto_in_a_bits_mask_0 = auto_in_a_bits_mask; // @[Buffer.scala:40:9] wire [63:0] auto_in_a_bits_data_0 = auto_in_a_bits_data; // @[Buffer.scala:40:9] wire auto_in_a_bits_corrupt_0 = auto_in_a_bits_corrupt; // @[Buffer.scala:40:9] wire auto_in_d_ready_0 = auto_in_d_ready; // @[Buffer.scala:40:9] wire auto_out_a_ready_0 = auto_out_a_ready; // @[Buffer.scala:40:9] wire auto_out_d_valid_0 = auto_out_d_valid; // @[Buffer.scala:40:9] wire [2:0] auto_out_d_bits_opcode_0 = auto_out_d_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] auto_out_d_bits_size_0 = auto_out_d_bits_size; // @[Buffer.scala:40:9] wire [6:0] auto_out_d_bits_source_0 = auto_out_d_bits_source; // @[Buffer.scala:40:9] wire [63:0] auto_out_d_bits_data_0 = auto_out_d_bits_data; // @[Buffer.scala:40:9] wire auto_out_d_bits_sink = 1'h0; // @[Decoupled.scala:362:21] wire auto_out_d_bits_denied = 1'h0; // @[Decoupled.scala:362:21] wire auto_out_d_bits_corrupt = 1'h0; // @[Decoupled.scala:362:21] wire nodeOut_d_bits_sink = 1'h0; // @[Decoupled.scala:362:21] wire nodeOut_d_bits_denied = 1'h0; // @[Decoupled.scala:362:21] wire nodeOut_d_bits_corrupt = 1'h0; // @[Decoupled.scala:362:21] wire [1:0] auto_out_d_bits_param = 2'h0; // @[Decoupled.scala:362:21] wire nodeIn_a_ready; // @[MixedNode.scala:551:17] wire [1:0] nodeOut_d_bits_param = 2'h0; // @[Decoupled.scala:362:21] wire nodeIn_a_valid = auto_in_a_valid_0; // @[Buffer.scala:40:9] wire [2:0] nodeIn_a_bits_opcode = auto_in_a_bits_opcode_0; // @[Buffer.scala:40:9] wire [2:0] nodeIn_a_bits_param = auto_in_a_bits_param_0; // @[Buffer.scala:40:9] wire [2:0] nodeIn_a_bits_size = auto_in_a_bits_size_0; // @[Buffer.scala:40:9] wire [6:0] nodeIn_a_bits_source = auto_in_a_bits_source_0; // @[Buffer.scala:40:9] wire [28:0] nodeIn_a_bits_address = auto_in_a_bits_address_0; // @[Buffer.scala:40:9] wire [7:0] nodeIn_a_bits_mask = auto_in_a_bits_mask_0; // @[Buffer.scala:40:9] wire [63:0] nodeIn_a_bits_data = auto_in_a_bits_data_0; // @[Buffer.scala:40:9] wire nodeIn_a_bits_corrupt = auto_in_a_bits_corrupt_0; // @[Buffer.scala:40:9] wire nodeIn_d_ready = auto_in_d_ready_0; // @[Buffer.scala:40:9] wire nodeIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] nodeIn_d_bits_param; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_d_bits_size; // @[MixedNode.scala:551:17] wire [6:0] nodeIn_d_bits_source; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_sink; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_denied; // @[MixedNode.scala:551:17] wire [63:0] nodeIn_d_bits_data; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_corrupt; // @[MixedNode.scala:551:17] wire nodeOut_a_ready = auto_out_a_ready_0; // @[Buffer.scala:40:9] wire nodeOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_a_bits_param; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_a_bits_size; // @[MixedNode.scala:542:17] wire [6:0] nodeOut_a_bits_source; // @[MixedNode.scala:542:17] wire [28:0] nodeOut_a_bits_address; // @[MixedNode.scala:542:17] wire [7:0] nodeOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [63:0] nodeOut_a_bits_data; // @[MixedNode.scala:542:17] wire nodeOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire nodeOut_d_ready; // @[MixedNode.scala:542:17] wire nodeOut_d_valid = auto_out_d_valid_0; // @[Buffer.scala:40:9] wire [2:0] nodeOut_d_bits_opcode = auto_out_d_bits_opcode_0; // @[Buffer.scala:40:9] wire [2:0] nodeOut_d_bits_size = auto_out_d_bits_size_0; // @[Buffer.scala:40:9] wire [6:0] nodeOut_d_bits_source = auto_out_d_bits_source_0; // @[Buffer.scala:40:9] wire [63:0] nodeOut_d_bits_data = auto_out_d_bits_data_0; // @[Buffer.scala:40:9] wire auto_in_a_ready_0; // @[Buffer.scala:40:9] wire [2:0] auto_in_d_bits_opcode_0; // @[Buffer.scala:40:9] wire [1:0] auto_in_d_bits_param_0; // @[Buffer.scala:40:9] wire [2:0] auto_in_d_bits_size_0; // @[Buffer.scala:40:9] wire [6:0] auto_in_d_bits_source_0; // @[Buffer.scala:40:9] wire auto_in_d_bits_sink_0; // @[Buffer.scala:40:9] wire auto_in_d_bits_denied_0; // @[Buffer.scala:40:9] wire [63:0] auto_in_d_bits_data_0; // @[Buffer.scala:40:9] wire auto_in_d_bits_corrupt_0; // @[Buffer.scala:40:9] wire auto_in_d_valid_0; // @[Buffer.scala:40:9] wire [2:0] auto_out_a_bits_opcode_0; // @[Buffer.scala:40:9] wire [2:0] auto_out_a_bits_param_0; // @[Buffer.scala:40:9] wire [2:0] auto_out_a_bits_size_0; // @[Buffer.scala:40:9] wire [6:0] auto_out_a_bits_source_0; // @[Buffer.scala:40:9] wire [28:0] auto_out_a_bits_address_0; // @[Buffer.scala:40:9] wire [7:0] auto_out_a_bits_mask_0; // @[Buffer.scala:40:9] wire [63:0] auto_out_a_bits_data_0; // @[Buffer.scala:40:9] wire auto_out_a_bits_corrupt_0; // @[Buffer.scala:40:9] wire auto_out_a_valid_0; // @[Buffer.scala:40:9] wire auto_out_d_ready_0; // @[Buffer.scala:40:9] assign auto_in_a_ready_0 = nodeIn_a_ready; // @[Buffer.scala:40:9] assign auto_in_d_valid_0 = nodeIn_d_valid; // @[Buffer.scala:40:9] assign auto_in_d_bits_opcode_0 = nodeIn_d_bits_opcode; // @[Buffer.scala:40:9] assign auto_in_d_bits_param_0 = nodeIn_d_bits_param; // @[Buffer.scala:40:9] assign auto_in_d_bits_size_0 = nodeIn_d_bits_size; // @[Buffer.scala:40:9] assign auto_in_d_bits_source_0 = nodeIn_d_bits_source; // @[Buffer.scala:40:9] assign auto_in_d_bits_sink_0 = nodeIn_d_bits_sink; // @[Buffer.scala:40:9] assign auto_in_d_bits_denied_0 = nodeIn_d_bits_denied; // @[Buffer.scala:40:9] assign auto_in_d_bits_data_0 = nodeIn_d_bits_data; // @[Buffer.scala:40:9] assign auto_in_d_bits_corrupt_0 = nodeIn_d_bits_corrupt; // @[Buffer.scala:40:9] assign auto_out_a_valid_0 = nodeOut_a_valid; // @[Buffer.scala:40:9] assign auto_out_a_bits_opcode_0 = nodeOut_a_bits_opcode; // @[Buffer.scala:40:9] assign auto_out_a_bits_param_0 = nodeOut_a_bits_param; // @[Buffer.scala:40:9] assign auto_out_a_bits_size_0 = nodeOut_a_bits_size; // @[Buffer.scala:40:9] assign auto_out_a_bits_source_0 = nodeOut_a_bits_source; // @[Buffer.scala:40:9] assign auto_out_a_bits_address_0 = nodeOut_a_bits_address; // @[Buffer.scala:40:9] assign auto_out_a_bits_mask_0 = nodeOut_a_bits_mask; // @[Buffer.scala:40:9] assign auto_out_a_bits_data_0 = nodeOut_a_bits_data; // @[Buffer.scala:40:9] assign auto_out_a_bits_corrupt_0 = nodeOut_a_bits_corrupt; // @[Buffer.scala:40:9] assign auto_out_d_ready_0 = nodeOut_d_ready; // @[Buffer.scala:40:9] TLMonitor_4 monitor ( // @[Nodes.scala:27:25] .clock (clock), .reset (reset), .io_in_a_ready (nodeIn_a_ready), // @[MixedNode.scala:551:17] .io_in_a_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17] .io_in_a_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17] .io_in_a_bits_param (nodeIn_a_bits_param), // @[MixedNode.scala:551:17] .io_in_a_bits_size (nodeIn_a_bits_size), // @[MixedNode.scala:551:17] .io_in_a_bits_source (nodeIn_a_bits_source), // @[MixedNode.scala:551:17] .io_in_a_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17] .io_in_a_bits_mask (nodeIn_a_bits_mask), // @[MixedNode.scala:551:17] .io_in_a_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17] .io_in_a_bits_corrupt (nodeIn_a_bits_corrupt), // @[MixedNode.scala:551:17] .io_in_d_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17] .io_in_d_valid (nodeIn_d_valid), // @[MixedNode.scala:551:17] .io_in_d_bits_opcode (nodeIn_d_bits_opcode), // @[MixedNode.scala:551:17] .io_in_d_bits_param (nodeIn_d_bits_param), // @[MixedNode.scala:551:17] .io_in_d_bits_size (nodeIn_d_bits_size), // @[MixedNode.scala:551:17] .io_in_d_bits_source (nodeIn_d_bits_source), // @[MixedNode.scala:551:17] .io_in_d_bits_sink (nodeIn_d_bits_sink), // @[MixedNode.scala:551:17] .io_in_d_bits_denied (nodeIn_d_bits_denied), // @[MixedNode.scala:551:17] .io_in_d_bits_data (nodeIn_d_bits_data), // @[MixedNode.scala:551:17] .io_in_d_bits_corrupt (nodeIn_d_bits_corrupt) // @[MixedNode.scala:551:17] ); // @[Nodes.scala:27:25] Queue2_TLBundleA_a29d64s7k1z3u nodeOut_a_q ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (nodeIn_a_ready), .io_enq_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17] .io_enq_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17] .io_enq_bits_param (nodeIn_a_bits_param), // @[MixedNode.scala:551:17] .io_enq_bits_size (nodeIn_a_bits_size), // @[MixedNode.scala:551:17] .io_enq_bits_source (nodeIn_a_bits_source), // @[MixedNode.scala:551:17] .io_enq_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17] .io_enq_bits_mask (nodeIn_a_bits_mask), // @[MixedNode.scala:551:17] .io_enq_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17] .io_enq_bits_corrupt (nodeIn_a_bits_corrupt), // @[MixedNode.scala:551:17] .io_deq_ready (nodeOut_a_ready), // @[MixedNode.scala:542:17] .io_deq_valid (nodeOut_a_valid), .io_deq_bits_opcode (nodeOut_a_bits_opcode), .io_deq_bits_param (nodeOut_a_bits_param), .io_deq_bits_size (nodeOut_a_bits_size), .io_deq_bits_source (nodeOut_a_bits_source), .io_deq_bits_address (nodeOut_a_bits_address), .io_deq_bits_mask (nodeOut_a_bits_mask), .io_deq_bits_data (nodeOut_a_bits_data), .io_deq_bits_corrupt (nodeOut_a_bits_corrupt) ); // @[Decoupled.scala:362:21] Queue2_TLBundleD_a29d64s7k1z3u nodeIn_d_q ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (nodeOut_d_ready), .io_enq_valid (nodeOut_d_valid), // @[MixedNode.scala:542:17] .io_enq_bits_opcode (nodeOut_d_bits_opcode), // @[MixedNode.scala:542:17] .io_enq_bits_size (nodeOut_d_bits_size), // @[MixedNode.scala:542:17] .io_enq_bits_source (nodeOut_d_bits_source), // @[MixedNode.scala:542:17] .io_enq_bits_data (nodeOut_d_bits_data), // @[MixedNode.scala:542:17] .io_deq_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17] .io_deq_valid (nodeIn_d_valid), .io_deq_bits_opcode (nodeIn_d_bits_opcode), .io_deq_bits_param (nodeIn_d_bits_param), .io_deq_bits_size (nodeIn_d_bits_size), .io_deq_bits_source (nodeIn_d_bits_source), .io_deq_bits_sink (nodeIn_d_bits_sink), .io_deq_bits_denied (nodeIn_d_bits_denied), .io_deq_bits_data (nodeIn_d_bits_data), .io_deq_bits_corrupt (nodeIn_d_bits_corrupt) ); // @[Decoupled.scala:362:21] assign auto_in_a_ready = auto_in_a_ready_0; // @[Buffer.scala:40:9] assign auto_in_d_valid = auto_in_d_valid_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_opcode = auto_in_d_bits_opcode_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_param = auto_in_d_bits_param_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_size = auto_in_d_bits_size_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_source = auto_in_d_bits_source_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_sink = auto_in_d_bits_sink_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_denied = auto_in_d_bits_denied_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_data = auto_in_d_bits_data_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_corrupt = auto_in_d_bits_corrupt_0; // @[Buffer.scala:40:9] assign auto_out_a_valid = auto_out_a_valid_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_opcode = auto_out_a_bits_opcode_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_param = auto_out_a_bits_param_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_size = auto_out_a_bits_size_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_source = auto_out_a_bits_source_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_address = auto_out_a_bits_address_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_mask = auto_out_a_bits_mask_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_data = auto_out_a_bits_data_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_corrupt = auto_out_a_bits_corrupt_0; // @[Buffer.scala:40:9] assign auto_out_d_ready = auto_out_d_ready_0; // @[Buffer.scala:40:9] endmodule
Generate the Verilog code corresponding to the following Chisel files. File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /* Like Vec.apply(idx), but tolerates indices of mismatched width / def extract(idx: UInt): T = x((idx \| 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx \| 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def \| (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a \|\| b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_\|\|_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /* Any Data subtype that has a Bool member named valid. / type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /* converts from camel case to to underscores, also removing all spaces / def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /* converts spaces or underscores to hyphens, also lowering case / def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y \| (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y \|\| y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 \| 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /* Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation */ def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag }	module OptimizationBarrier_EntryData_12( // @[package.scala:267:30] input clock, // @[package.scala:267:30] input reset, // @[package.scala:267:30] input [19:0] io_x_ppn, // @[package.scala:268:18] input io_x_u, // @[package.scala:268:18] input io_x_g, // @[package.scala:268:18] input io_x_ae, // @[package.scala:268:18] input io_x_sw, // @[package.scala:268:18] input io_x_sx, // @[package.scala:268:18] input io_x_sr, // @[package.scala:268:18] input io_x_pw, // @[package.scala:268:18] input io_x_px, // @[package.scala:268:18] input io_x_pr, // @[package.scala:268:18] input io_x_pal, // @[package.scala:268:18] input io_x_paa, // @[package.scala:268:18] input io_x_eff, // @[package.scala:268:18] input io_x_c, // @[package.scala:268:18] input io_x_fragmented_superpage, // @[package.scala:268:18] output [19:0] io_y_ppn, // @[package.scala:268:18] output io_y_u, // @[package.scala:268:18] output io_y_g, // @[package.scala:268:18] output io_y_ae, // @[package.scala:268:18] output io_y_sw, // @[package.scala:268:18] output io_y_sx, // @[package.scala:268:18] output io_y_sr, // @[package.scala:268:18] output io_y_pw, // @[package.scala:268:18] output io_y_px, // @[package.scala:268:18] output io_y_pr, // @[package.scala:268:18] output io_y_pal, // @[package.scala:268:18] output io_y_paa, // @[package.scala:268:18] output io_y_eff, // @[package.scala:268:18] output io_y_c, // @[package.scala:268:18] output io_y_fragmented_superpage // @[package.scala:268:18] ); wire [19:0] io_x_ppn_0 = io_x_ppn; // @[package.scala:267:30] wire io_x_u_0 = io_x_u; // @[package.scala:267:30] wire io_x_g_0 = io_x_g; // @[package.scala:267:30] wire io_x_ae_0 = io_x_ae; // @[package.scala:267:30] wire io_x_sw_0 = io_x_sw; // @[package.scala:267:30] wire io_x_sx_0 = io_x_sx; // @[package.scala:267:30] wire io_x_sr_0 = io_x_sr; // @[package.scala:267:30] wire io_x_pw_0 = io_x_pw; // @[package.scala:267:30] wire io_x_px_0 = io_x_px; // @[package.scala:267:30] wire io_x_pr_0 = io_x_pr; // @[package.scala:267:30] wire io_x_pal_0 = io_x_pal; // @[package.scala:267:30] wire io_x_paa_0 = io_x_paa; // @[package.scala:267:30] wire io_x_eff_0 = io_x_eff; // @[package.scala:267:30] wire io_x_c_0 = io_x_c; // @[package.scala:267:30] wire io_x_fragmented_superpage_0 = io_x_fragmented_superpage; // @[package.scala:267:30] wire [19:0] io_y_ppn_0 = io_x_ppn_0; // @[package.scala:267:30] wire io_y_u_0 = io_x_u_0; // @[package.scala:267:30] wire io_y_g_0 = io_x_g_0; // @[package.scala:267:30] wire io_y_ae_0 = io_x_ae_0; // @[package.scala:267:30] wire io_y_sw_0 = io_x_sw_0; // @[package.scala:267:30] wire io_y_sx_0 = io_x_sx_0; // @[package.scala:267:30] wire io_y_sr_0 = io_x_sr_0; // @[package.scala:267:30] wire io_y_pw_0 = io_x_pw_0; // @[package.scala:267:30] wire io_y_px_0 = io_x_px_0; // @[package.scala:267:30] wire io_y_pr_0 = io_x_pr_0; // @[package.scala:267:30] wire io_y_pal_0 = io_x_pal_0; // @[package.scala:267:30] wire io_y_paa_0 = io_x_paa_0; // @[package.scala:267:30] wire io_y_eff_0 = io_x_eff_0; // @[package.scala:267:30] wire io_y_c_0 = io_x_c_0; // @[package.scala:267:30] wire io_y_fragmented_superpage_0 = io_x_fragmented_superpage_0; // @[package.scala:267:30] assign io_y_ppn = io_y_ppn_0; // @[package.scala:267:30] assign io_y_u = io_y_u_0; // @[package.scala:267:30] assign io_y_g = io_y_g_0; // @[package.scala:267:30] assign io_y_ae = io_y_ae_0; // @[package.scala:267:30] assign io_y_sw = io_y_sw_0; // @[package.scala:267:30] assign io_y_sx = io_y_sx_0; // @[package.scala:267:30] assign io_y_sr = io_y_sr_0; // @[package.scala:267:30] assign io_y_pw = io_y_pw_0; // @[package.scala:267:30] assign io_y_px = io_y_px_0; // @[package.scala:267:30] assign io_y_pr = io_y_pr_0; // @[package.scala:267:30] assign io_y_pal = io_y_pal_0; // @[package.scala:267:30] assign io_y_paa = io_y_paa_0; // @[package.scala:267:30] assign io_y_eff = io_y_eff_0; // @[package.scala:267:30] assign io_y_c = io_y_c_0; // @[package.scala:267:30] assign io_y_fragmented_superpage = io_y_fragmented_superpage_0; // @[package.scala:267:30] endmodule
Generate the Verilog code corresponding to the following Chisel files. File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /* Like Vec.apply(idx), but tolerates indices of mismatched width / def extract(idx: UInt): T = x((idx \| 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx \| 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def \| (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a \|\| b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_\|\|_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /* Any Data subtype that has a Bool member named valid. / type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /* converts from camel case to to underscores, also removing all spaces / def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /* converts spaces or underscores to hyphens, also lowering case / def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y \| (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y \|\| y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 \| 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /* Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation / def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File DCache.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.rocket import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config._ import freechips.rocketchip.amba.AMBAProt import freechips.rocketchip.diplomacy.{BufferParams} import freechips.rocketchip.prci.{ClockCrossingType, RationalCrossing, SynchronousCrossing, AsynchronousCrossing, CreditedCrossing} import freechips.rocketchip.tile.{CoreBundle, LookupByHartId} import freechips.rocketchip.tilelink.{TLFIFOFixer,ClientMetadata, TLBundleA, TLAtomics, TLBundleB, TLPermissions} import freechips.rocketchip.tilelink.TLMessages.{AccessAck, HintAck, AccessAckData, Grant, GrantData, ReleaseAck} import freechips.rocketchip.util.{CanHaveErrors, ClockGate, IdentityCode, ReplacementPolicy, DescribedSRAM, property} import freechips.rocketchip.util.BooleanToAugmentedBoolean import freechips.rocketchip.util.UIntToAugmentedUInt import freechips.rocketchip.util.UIntIsOneOf import freechips.rocketchip.util.IntToAugmentedInt import freechips.rocketchip.util.SeqToAugmentedSeq import freechips.rocketchip.util.SeqBoolBitwiseOps // TODO: delete this trait once deduplication is smart enough to avoid globally inlining matching circuits trait InlineInstance { self: chisel3.experimental.BaseModule => chisel3.experimental.annotate( new chisel3.experimental.ChiselAnnotation { def toFirrtl: firrtl.annotations.Annotation = firrtl.passes.InlineAnnotation(self.toNamed) } ) } class DCacheErrors(implicit p: Parameters) extends L1HellaCacheBundle()(p) with CanHaveErrors { val correctable = (cacheParams.tagCode.canCorrect \|\| cacheParams.dataCode.canCorrect).option(Valid(UInt(paddrBits.W))) val uncorrectable = (cacheParams.tagCode.canDetect \|\| cacheParams.dataCode.canDetect).option(Valid(UInt(paddrBits.W))) val bus = Valid(UInt(paddrBits.W)) } class DCacheDataReq(implicit p: Parameters) extends L1HellaCacheBundle()(p) { val addr = UInt(untagBits.W) val write = Bool() val wdata = UInt((encBits rowBytes / eccBytes).W) val wordMask = UInt((rowBytes / subWordBytes).W) val eccMask = UInt((wordBytes / eccBytes).W) val way_en = UInt(nWays.W) } class DCacheDataArray(implicit p: Parameters) extends L1HellaCacheModule()(p) { val io = IO(new Bundle { val req = Flipped(Valid(new DCacheDataReq)) val resp = Output(Vec(nWays, UInt((req.bits.wdata.getWidth).W))) }) require(rowBits % subWordBits == 0, "rowBits must be a multiple of subWordBits") val eccMask = if (eccBits == subWordBits) Seq(true.B) else io.req.bits.eccMask.asBools val wMask = if (nWays == 1) eccMask else (0 until nWays).flatMap(i => eccMask.map(_ && io.req.bits.way_en(i))) val wWords = io.req.bits.wdata.grouped(encBits * (subWordBits / eccBits)) val addr = io.req.bits.addr >> rowOffBits val data_arrays = Seq.tabulate(rowBits / subWordBits) { i => DescribedSRAM( name = s"${tileParams.baseName}_dcache_data_arrays_${i}", desc = "DCache Data Array", size = nSets * cacheBlockBytes / rowBytes, data = Vec(nWays * (subWordBits / eccBits), UInt(encBits.W)) ) } val rdata = for ((array , i) <- data_arrays.zipWithIndex) yield { val valid = io.req.valid && ((data_arrays.size == 1).B \|\| io.req.bits.wordMask(i)) when (valid && io.req.bits.write) { val wMaskSlice = (0 until wMask.size).filter(j => i % (wordBits/subWordBits) == (j % (wordBytes/eccBytes)) / (subWordBytes/eccBytes)).map(wMask(_)) val wData = wWords(i).grouped(encBits) array.write(addr, VecInit((0 until nWays).flatMap(i => wData)), wMaskSlice) } val data = array.read(addr, valid && !io.req.bits.write) data.grouped(subWordBits / eccBits).map(_.asUInt).toSeq } (io.resp zip rdata.transpose).foreach { case (resp, data) => resp := data.asUInt } } class DCacheMetadataReq(implicit p: Parameters) extends L1HellaCacheBundle()(p) { val write = Bool() val addr = UInt(vaddrBitsExtended.W) val idx = UInt(idxBits.W) val way_en = UInt(nWays.W) val data = UInt(cacheParams.tagCode.width(new L1Metadata().getWidth).W) } class DCache(staticIdForMetadataUseOnly: Int, val crossing: ClockCrossingType)(implicit p: Parameters) extends HellaCache(staticIdForMetadataUseOnly)(p) { override lazy val module = new DCacheModule(this) } class DCacheTLBPort(implicit p: Parameters) extends CoreBundle()(p) { val req = Flipped(Decoupled(new TLBReq(coreDataBytes.log2))) val s1_resp = Output(new TLBResp(coreDataBytes.log2)) val s2_kill = Input(Bool()) } class DCacheModule(outer: DCache) extends HellaCacheModule(outer) { val tECC = cacheParams.tagCode val dECC = cacheParams.dataCode require(subWordBits % eccBits == 0, "subWordBits must be a multiple of eccBits") require(eccBytes == 1 \|\| !dECC.isInstanceOf[IdentityCode]) require(cacheParams.silentDrop \|\| cacheParams.acquireBeforeRelease, "!silentDrop requires acquireBeforeRelease") val usingRMW = eccBytes > 1 \|\| usingAtomicsInCache val mmioOffset = outer.firstMMIO edge.manager.requireFifo(TLFIFOFixer.allVolatile) // TileLink pipelining MMIO requests val clock_en_reg = Reg(Bool()) io.cpu.clock_enabled := clock_en_reg val gated_clock = if (!cacheParams.clockGate) clock else ClockGate(clock, clock_en_reg, "dcache_clock_gate") class DCacheModuleImpl { // entering gated-clock domain val tlb = Module(new TLB(false, log2Ceil(coreDataBytes), TLBConfig(nTLBSets, nTLBWays, cacheParams.nTLBBasePageSectors, cacheParams.nTLBSuperpages))) val pma_checker = Module(new TLB(false, log2Ceil(coreDataBytes), TLBConfig(nTLBSets, nTLBWays, cacheParams.nTLBBasePageSectors, cacheParams.nTLBSuperpages)) with InlineInstance) // tags val replacer = ReplacementPolicy.fromString(cacheParams.replacementPolicy, nWays) /** Metadata Arbiter: * 0: Tag update on reset * 1: Tag update on ECC error * 2: Tag update on hit * 3: Tag update on refill * 4: Tag update on release * 5: Tag update on flush * 6: Tag update on probe * 7: Tag update on CPU request / val metaArb = Module(new Arbiter(new DCacheMetadataReq, 8) with InlineInstance) val tag_array = DescribedSRAM( name = s"${tileParams.baseName}_dcache_tag_array", desc = "DCache Tag Array", size = nSets, data = Vec(nWays, chiselTypeOf(metaArb.io.out.bits.data)) ) // data val data = Module(new DCacheDataArray) /* Data Arbiter * 0: data from pending store buffer * 1: data from TL-D refill * 2: release to TL-A * 3: hit path to CPU / val dataArb = Module(new Arbiter(new DCacheDataReq, 4) with InlineInstance) dataArb.io.in.tail.foreach(_.bits.wdata := dataArb.io.in.head.bits.wdata) // tie off write ports by default data.io.req.bits <> dataArb.io.out.bits data.io.req.valid := dataArb.io.out.valid dataArb.io.out.ready := true.B metaArb.io.out.ready := clock_en_reg val tl_out_a = Wire(chiselTypeOf(tl_out.a)) tl_out.a <> { val a_queue_depth = outer.crossing match { case RationalCrossing(_) => // TODO make this depend on the actual ratio? if (cacheParams.separateUncachedResp) (maxUncachedInFlight + 1) / 2 else 2 min maxUncachedInFlight-1 case SynchronousCrossing(BufferParams.none) => 1 // Need some buffering to guarantee livelock freedom case SynchronousCrossing(_) => 0 // Adequate buffering within the crossing case _: AsynchronousCrossing => 0 // Adequate buffering within the crossing case _: CreditedCrossing => 0 // Adequate buffering within the crossing } Queue(tl_out_a, a_queue_depth, flow = true) } val (tl_out_c, release_queue_empty) = if (cacheParams.acquireBeforeRelease) { val q = Module(new Queue(chiselTypeOf(tl_out.c.bits), cacheDataBeats, flow = true)) tl_out.c <> q.io.deq (q.io.enq, q.io.count === 0.U) } else { (tl_out.c, true.B) } val s1_valid = RegNext(io.cpu.req.fire, false.B) val s1_probe = RegNext(tl_out.b.fire, false.B) val probe_bits = RegEnable(tl_out.b.bits, tl_out.b.fire) // TODO has data now :( val s1_nack = WireDefault(false.B) val s1_valid_masked = s1_valid && !io.cpu.s1_kill val s1_valid_not_nacked = s1_valid && !s1_nack val s1_tlb_req_valid = RegNext(io.tlb_port.req.fire, false.B) val s2_tlb_req_valid = RegNext(s1_tlb_req_valid, false.B) val s0_clk_en = metaArb.io.out.valid && !metaArb.io.out.bits.write val s0_req = WireInit(io.cpu.req.bits) s0_req.addr := Cat(metaArb.io.out.bits.addr >> blockOffBits, io.cpu.req.bits.addr(blockOffBits-1,0)) s0_req.idx.foreach(_ := Cat(metaArb.io.out.bits.idx, s0_req.addr(blockOffBits-1, 0))) when (!metaArb.io.in(7).ready) { s0_req.phys := true.B } val s1_req = RegEnable(s0_req, s0_clk_en) val s1_vaddr = Cat(s1_req.idx.getOrElse(s1_req.addr) >> tagLSB, s1_req.addr(tagLSB-1, 0)) val s0_tlb_req = WireInit(io.tlb_port.req.bits) when (!io.tlb_port.req.fire) { s0_tlb_req.passthrough := s0_req.phys s0_tlb_req.vaddr := s0_req.addr s0_tlb_req.size := s0_req.size s0_tlb_req.cmd := s0_req.cmd s0_tlb_req.prv := s0_req.dprv s0_tlb_req.v := s0_req.dv } val s1_tlb_req = RegEnable(s0_tlb_req, s0_clk_en \|\| io.tlb_port.req.valid) val s1_read = isRead(s1_req.cmd) val s1_write = isWrite(s1_req.cmd) val s1_readwrite = s1_read \|\| s1_write val s1_sfence = s1_req.cmd === M_SFENCE \|\| s1_req.cmd === M_HFENCEV \|\| s1_req.cmd === M_HFENCEG val s1_flush_line = s1_req.cmd === M_FLUSH_ALL && s1_req.size(0) val s1_flush_valid = Reg(Bool()) val s1_waw_hazard = Wire(Bool()) val s_ready :: s_voluntary_writeback :: s_probe_rep_dirty :: s_probe_rep_clean :: s_probe_retry :: s_probe_rep_miss :: s_voluntary_write_meta :: s_probe_write_meta :: s_dummy :: s_voluntary_release :: Nil = Enum(10) val supports_flush = outer.flushOnFenceI \|\| coreParams.haveCFlush val flushed = RegInit(true.B) val flushing = RegInit(false.B) val flushing_req = Reg(chiselTypeOf(s1_req)) val cached_grant_wait = RegInit(false.B) val resetting = RegInit(false.B) val flushCounter = RegInit((nSets (nWays-1)).U(log2Ceil(nSets * nWays).W)) val release_ack_wait = RegInit(false.B) val release_ack_addr = Reg(UInt(paddrBits.W)) val release_state = RegInit(s_ready) val refill_way = Reg(UInt()) val any_pstore_valid = Wire(Bool()) val inWriteback = release_state.isOneOf(s_voluntary_writeback, s_probe_rep_dirty) val releaseWay = Wire(UInt()) io.cpu.req.ready := (release_state === s_ready) && !cached_grant_wait && !s1_nack // I/O MSHRs val uncachedInFlight = RegInit(VecInit(Seq.fill(maxUncachedInFlight)(false.B))) val uncachedReqs = Reg(Vec(maxUncachedInFlight, new HellaCacheReq)) val uncachedResp = WireInit(new HellaCacheReq, DontCare) // hit initiation path val s0_read = isRead(io.cpu.req.bits.cmd) dataArb.io.in(3).valid := io.cpu.req.valid && likelyNeedsRead(io.cpu.req.bits) dataArb.io.in(3).bits := dataArb.io.in(1).bits dataArb.io.in(3).bits.write := false.B dataArb.io.in(3).bits.addr := Cat(io.cpu.req.bits.idx.getOrElse(io.cpu.req.bits.addr) >> tagLSB, io.cpu.req.bits.addr(tagLSB-1, 0)) dataArb.io.in(3).bits.wordMask := { val mask = (subWordBytes.log2 until rowOffBits).foldLeft(1.U) { case (in, i) => val upper_mask = Mux((i >= wordBytes.log2).B \|\| io.cpu.req.bits.size <= i.U, 0.U, ((BigInt(1) << (1 << (i - subWordBytes.log2)))-1).U) val upper = Mux(io.cpu.req.bits.addr(i), in, 0.U) \| upper_mask val lower = Mux(io.cpu.req.bits.addr(i), 0.U, in) upper ## lower } Fill(subWordBytes / eccBytes, mask) } dataArb.io.in(3).bits.eccMask := ~0.U((wordBytes / eccBytes).W) dataArb.io.in(3).bits.way_en := ~0.U(nWays.W) when (!dataArb.io.in(3).ready && s0_read) { io.cpu.req.ready := false.B } val s1_did_read = RegEnable(dataArb.io.in(3).ready && (io.cpu.req.valid && needsRead(io.cpu.req.bits)), s0_clk_en) val s1_read_mask = RegEnable(dataArb.io.in(3).bits.wordMask, s0_clk_en) metaArb.io.in(7).valid := io.cpu.req.valid metaArb.io.in(7).bits.write := false.B metaArb.io.in(7).bits.idx := dataArb.io.in(3).bits.addr(idxMSB, idxLSB) metaArb.io.in(7).bits.addr := io.cpu.req.bits.addr metaArb.io.in(7).bits.way_en := metaArb.io.in(4).bits.way_en metaArb.io.in(7).bits.data := metaArb.io.in(4).bits.data when (!metaArb.io.in(7).ready) { io.cpu.req.ready := false.B } // address translation val s1_cmd_uses_tlb = s1_readwrite \|\| s1_flush_line \|\| s1_req.cmd === M_WOK io.ptw <> tlb.io.ptw tlb.io.kill := io.cpu.s2_kill \|\| s2_tlb_req_valid && io.tlb_port.s2_kill tlb.io.req.valid := s1_tlb_req_valid \|\| s1_valid && !io.cpu.s1_kill && s1_cmd_uses_tlb tlb.io.req.bits := s1_tlb_req when (!tlb.io.req.ready && !tlb.io.ptw.resp.valid && !io.cpu.req.bits.phys) { io.cpu.req.ready := false.B } when (!s1_tlb_req_valid && s1_valid && s1_cmd_uses_tlb && tlb.io.resp.miss) { s1_nack := true.B } tlb.io.sfence.valid := s1_valid && !io.cpu.s1_kill && s1_sfence tlb.io.sfence.bits.rs1 := s1_req.size(0) tlb.io.sfence.bits.rs2 := s1_req.size(1) tlb.io.sfence.bits.asid := io.cpu.s1_data.data tlb.io.sfence.bits.addr := s1_req.addr tlb.io.sfence.bits.hv := s1_req.cmd === M_HFENCEV tlb.io.sfence.bits.hg := s1_req.cmd === M_HFENCEG io.tlb_port.req.ready := clock_en_reg io.tlb_port.s1_resp := tlb.io.resp when (s1_tlb_req_valid && s1_valid && !(s1_req.phys && s1_req.no_xcpt)) { s1_nack := true.B } pma_checker.io <> DontCare pma_checker.io.req.bits.passthrough := true.B pma_checker.io.req.bits.vaddr := s1_req.addr pma_checker.io.req.bits.size := s1_req.size pma_checker.io.req.bits.cmd := s1_req.cmd pma_checker.io.req.bits.prv := s1_req.dprv pma_checker.io.req.bits.v := s1_req.dv val s1_paddr = Cat(Mux(s1_tlb_req_valid, s1_req.addr(paddrBits-1, pgIdxBits), tlb.io.resp.paddr >> pgIdxBits), s1_req.addr(pgIdxBits-1, 0)) val s1_victim_way = Wire(UInt()) val (s1_hit_way, s1_hit_state, s1_meta) = if (usingDataScratchpad) { val baseAddr = p(LookupByHartId)(_.dcache.flatMap(_.scratch.map(_.U)), io_hartid.get) \| io_mmio_address_prefix.get val inScratchpad = s1_paddr >= baseAddr && s1_paddr < baseAddr + (nSets * cacheBlockBytes).U val hitState = Mux(inScratchpad, ClientMetadata.maximum, ClientMetadata.onReset) val dummyMeta = L1Metadata(0.U, ClientMetadata.onReset) (inScratchpad, hitState, Seq(tECC.encode(dummyMeta.asUInt))) } else { val metaReq = metaArb.io.out val metaIdx = metaReq.bits.idx when (metaReq.valid && metaReq.bits.write) { val wmask = if (nWays == 1) Seq(true.B) else metaReq.bits.way_en.asBools tag_array.write(metaIdx, VecInit(Seq.fill(nWays)(metaReq.bits.data)), wmask) } val s1_meta = tag_array.read(metaIdx, metaReq.valid && !metaReq.bits.write) val s1_meta_uncorrected = s1_meta.map(tECC.decode(_).uncorrected.asTypeOf(new L1Metadata)) val s1_tag = s1_paddr >> tagLSB val s1_meta_hit_way = s1_meta_uncorrected.map(r => r.coh.isValid() && r.tag === s1_tag).asUInt val s1_meta_hit_state = ( s1_meta_uncorrected.map(r => Mux(r.tag === s1_tag && !s1_flush_valid, r.coh.asUInt, 0.U)) .reduce (_\|_)).asTypeOf(chiselTypeOf(ClientMetadata.onReset)) (s1_meta_hit_way, s1_meta_hit_state, s1_meta) } val s1_data_way = WireDefault(if (nWays == 1) 1.U else Mux(inWriteback, releaseWay, s1_hit_way)) val tl_d_data_encoded = Wire(chiselTypeOf(encodeData(tl_out.d.bits.data, false.B))) val s1_all_data_ways = VecInit(data.io.resp ++ (!cacheParams.separateUncachedResp).option(tl_d_data_encoded)) val s1_mask_xwr = new StoreGen(s1_req.size, s1_req.addr, 0.U, wordBytes).mask val s1_mask = Mux(s1_req.cmd === M_PWR, io.cpu.s1_data.mask, s1_mask_xwr) // for partial writes, s1_data.mask must be a subset of s1_mask_xwr assert(!(s1_valid_masked && s1_req.cmd === M_PWR) \|\| (s1_mask_xwr \| ~io.cpu.s1_data.mask).andR) val s2_valid = RegNext(s1_valid_masked && !s1_sfence, init=false.B) val s2_valid_no_xcpt = s2_valid && !io.cpu.s2_xcpt.asUInt.orR val s2_probe = RegNext(s1_probe, init=false.B) val releaseInFlight = s1_probe \|\| s2_probe \|\| release_state =/= s_ready val s2_not_nacked_in_s1 = RegNext(!s1_nack) val s2_valid_not_nacked_in_s1 = s2_valid && s2_not_nacked_in_s1 val s2_valid_masked = s2_valid_no_xcpt && s2_not_nacked_in_s1 val s2_valid_not_killed = s2_valid_masked && !io.cpu.s2_kill val s2_req = Reg(chiselTypeOf(io.cpu.req.bits)) val s2_cmd_flush_all = s2_req.cmd === M_FLUSH_ALL && !s2_req.size(0) val s2_cmd_flush_line = s2_req.cmd === M_FLUSH_ALL && s2_req.size(0) val s2_tlb_xcpt = Reg(chiselTypeOf(tlb.io.resp)) val s2_pma = Reg(chiselTypeOf(tlb.io.resp)) val s2_uncached_resp_addr = Reg(chiselTypeOf(s2_req.addr)) // should be DCE'd in synthesis when (s1_valid_not_nacked \|\| s1_flush_valid) { s2_req := s1_req s2_req.addr := s1_paddr s2_tlb_xcpt := tlb.io.resp s2_pma := Mux(s1_tlb_req_valid, pma_checker.io.resp, tlb.io.resp) } val s2_vaddr = Cat(RegEnable(s1_vaddr, s1_valid_not_nacked \|\| s1_flush_valid) >> tagLSB, s2_req.addr(tagLSB-1, 0)) val s2_read = isRead(s2_req.cmd) val s2_write = isWrite(s2_req.cmd) val s2_readwrite = s2_read \|\| s2_write val s2_flush_valid_pre_tag_ecc = RegNext(s1_flush_valid) val s1_meta_decoded = s1_meta.map(tECC.decode(_)) val s1_meta_clk_en = s1_valid_not_nacked \|\| s1_flush_valid \|\| s1_probe val s2_meta_correctable_errors = s1_meta_decoded.map(m => RegEnable(m.correctable, s1_meta_clk_en)).asUInt val s2_meta_uncorrectable_errors = s1_meta_decoded.map(m => RegEnable(m.uncorrectable, s1_meta_clk_en)).asUInt val s2_meta_error_uncorrectable = s2_meta_uncorrectable_errors.orR val s2_meta_corrected = s1_meta_decoded.map(m => RegEnable(m.corrected, s1_meta_clk_en).asTypeOf(new L1Metadata)) val s2_meta_error = (s2_meta_uncorrectable_errors \| s2_meta_correctable_errors).orR val s2_flush_valid = s2_flush_valid_pre_tag_ecc && !s2_meta_error val s2_data = { val wordsPerRow = rowBits / subWordBits val en = s1_valid \|\| inWriteback \|\| io.cpu.replay_next val word_en = Mux(inWriteback, Fill(wordsPerRow, 1.U), Mux(s1_did_read, s1_read_mask, 0.U)) val s1_way_words = s1_all_data_ways.map(_.grouped(dECC.width(eccBits) * (subWordBits / eccBits))) if (cacheParams.pipelineWayMux) { val s1_word_en = Mux(io.cpu.replay_next, 0.U, word_en) (for (i <- 0 until wordsPerRow) yield { val s2_way_en = RegEnable(Mux(s1_word_en(i), s1_data_way, 0.U), en) val s2_way_words = (0 until nWays).map(j => RegEnable(s1_way_words(j)(i), en && word_en(i))) (0 until nWays).map(j => Mux(s2_way_en(j), s2_way_words(j), 0.U)).reduce(_\|_) }).asUInt } else { val s1_word_en = Mux(!io.cpu.replay_next, word_en, UIntToOH(uncachedResp.addr.extract(log2Up(rowBits/8)-1, log2Up(wordBytes)), wordsPerRow)) (for (i <- 0 until wordsPerRow) yield { RegEnable(Mux1H(Mux(s1_word_en(i), s1_data_way, 0.U), s1_way_words.map(_(i))), en) }).asUInt } } val s2_probe_way = RegEnable(s1_hit_way, s1_probe) val s2_probe_state = RegEnable(s1_hit_state, s1_probe) val s2_hit_way = RegEnable(s1_hit_way, s1_valid_not_nacked) val s2_hit_state = RegEnable(s1_hit_state, s1_valid_not_nacked \|\| s1_flush_valid) val s2_waw_hazard = RegEnable(s1_waw_hazard, s1_valid_not_nacked) val s2_store_merge = Wire(Bool()) val s2_hit_valid = s2_hit_state.isValid() val (s2_hit, s2_grow_param, s2_new_hit_state) = s2_hit_state.onAccess(s2_req.cmd) val s2_data_decoded = decodeData(s2_data) val s2_word_idx = s2_req.addr.extract(log2Up(rowBits/8)-1, log2Up(wordBytes)) val s2_data_error = s2_data_decoded.map(_.error).orR val s2_data_error_uncorrectable = s2_data_decoded.map(_.uncorrectable).orR val s2_data_corrected = (s2_data_decoded.map(_.corrected): Seq[UInt]).asUInt val s2_data_uncorrected = (s2_data_decoded.map(_.uncorrected): Seq[UInt]).asUInt val s2_valid_hit_maybe_flush_pre_data_ecc_and_waw = s2_valid_masked && !s2_meta_error && s2_hit val s2_no_alloc_hazard = if (!usingVM \|\| pgIdxBits >= untagBits) false.B else { // make sure that any in-flight non-allocating accesses are ordered before // any allocating accesses. this can only happen if aliasing is possible. val any_no_alloc_in_flight = Reg(Bool()) when (!uncachedInFlight.asUInt.orR) { any_no_alloc_in_flight := false.B } when (s2_valid && s2_req.no_alloc) { any_no_alloc_in_flight := true.B } val s1_need_check = any_no_alloc_in_flight \|\| s2_valid && s2_req.no_alloc val concerns = (uncachedInFlight zip uncachedReqs) :+ (s2_valid && s2_req.no_alloc, s2_req) val s1_uncached_hits = concerns.map { c => val concern_wmask = new StoreGen(c._2.size, c._2.addr, 0.U, wordBytes).mask val addr_match = (c._2.addr ^ s1_paddr)(pgIdxBits+pgLevelBits-1, wordBytes.log2) === 0.U val mask_match = (concern_wmask & s1_mask_xwr).orR \|\| c._2.cmd === M_PWR \|\| s1_req.cmd === M_PWR val cmd_match = isWrite(c._2.cmd) \|\| isWrite(s1_req.cmd) c._1 && s1_need_check && cmd_match && addr_match && mask_match } val s2_uncached_hits = RegEnable(s1_uncached_hits.asUInt, s1_valid_not_nacked) s2_uncached_hits.orR } val s2_valid_hit_pre_data_ecc_and_waw = s2_valid_hit_maybe_flush_pre_data_ecc_and_waw && s2_readwrite && !s2_no_alloc_hazard val s2_valid_flush_line = s2_valid_hit_maybe_flush_pre_data_ecc_and_waw && s2_cmd_flush_line val s2_valid_hit_pre_data_ecc = s2_valid_hit_pre_data_ecc_and_waw && (!s2_waw_hazard \|\| s2_store_merge) val s2_valid_data_error = s2_valid_hit_pre_data_ecc_and_waw && s2_data_error val s2_valid_hit = s2_valid_hit_pre_data_ecc && !s2_data_error val s2_valid_miss = s2_valid_masked && s2_readwrite && !s2_meta_error && !s2_hit val s2_uncached = !s2_pma.cacheable \|\| s2_req.no_alloc && !s2_pma.must_alloc && !s2_hit_valid val s2_valid_cached_miss = s2_valid_miss && !s2_uncached && !uncachedInFlight.asUInt.orR dontTouch(s2_valid_cached_miss) val s2_want_victimize = (!usingDataScratchpad).B && (s2_valid_cached_miss \|\| s2_valid_flush_line \|\| s2_valid_data_error \|\| s2_flush_valid) val s2_cannot_victimize = !s2_flush_valid && io.cpu.s2_kill val s2_victimize = s2_want_victimize && !s2_cannot_victimize val s2_valid_uncached_pending = s2_valid_miss && s2_uncached && !uncachedInFlight.asUInt.andR val s2_victim_way = UIntToOH(RegEnable(s1_victim_way, s1_valid_not_nacked \|\| s1_flush_valid)) val s2_victim_or_hit_way = Mux(s2_hit_valid, s2_hit_way, s2_victim_way) val s2_victim_tag = Mux(s2_valid_data_error \|\| s2_valid_flush_line, s2_req.addr(paddrBits-1, tagLSB), Mux1H(s2_victim_way, s2_meta_corrected).tag) val s2_victim_state = Mux(s2_hit_valid, s2_hit_state, Mux1H(s2_victim_way, s2_meta_corrected).coh) val (s2_prb_ack_data, s2_report_param, probeNewCoh)= s2_probe_state.onProbe(probe_bits.param) val (s2_victim_dirty, s2_shrink_param, voluntaryNewCoh) = s2_victim_state.onCacheControl(M_FLUSH) dontTouch(s2_victim_dirty) val s2_update_meta = s2_hit_state =/= s2_new_hit_state val s2_dont_nack_uncached = s2_valid_uncached_pending && tl_out_a.ready val s2_dont_nack_misc = s2_valid_masked && !s2_meta_error && (supports_flush.B && s2_cmd_flush_all && flushed && !flushing \|\| supports_flush.B && s2_cmd_flush_line && !s2_hit \|\| s2_req.cmd === M_WOK) io.cpu.s2_nack := s2_valid_no_xcpt && !s2_dont_nack_uncached && !s2_dont_nack_misc && !s2_valid_hit when (io.cpu.s2_nack \|\| (s2_valid_hit_pre_data_ecc_and_waw && s2_update_meta)) { s1_nack := true.B } // tag updates on ECC errors val s2_first_meta_corrected = PriorityMux(s2_meta_correctable_errors, s2_meta_corrected) metaArb.io.in(1).valid := s2_meta_error && (s2_valid_masked \|\| s2_flush_valid_pre_tag_ecc \|\| s2_probe) metaArb.io.in(1).bits.write := true.B metaArb.io.in(1).bits.way_en := s2_meta_uncorrectable_errors \| Mux(s2_meta_error_uncorrectable, 0.U, PriorityEncoderOH(s2_meta_correctable_errors)) metaArb.io.in(1).bits.idx := Mux(s2_probe, probeIdx(probe_bits), s2_vaddr(idxMSB, idxLSB)) metaArb.io.in(1).bits.addr := Cat(io.cpu.req.bits.addr >> untagBits, metaArb.io.in(1).bits.idx << blockOffBits) metaArb.io.in(1).bits.data := tECC.encode { val new_meta = WireDefault(s2_first_meta_corrected) when (s2_meta_error_uncorrectable) { new_meta.coh := ClientMetadata.onReset } new_meta.asUInt } // tag updates on hit metaArb.io.in(2).valid := s2_valid_hit_pre_data_ecc_and_waw && s2_update_meta metaArb.io.in(2).bits.write := !io.cpu.s2_kill metaArb.io.in(2).bits.way_en := s2_victim_or_hit_way metaArb.io.in(2).bits.idx := s2_vaddr(idxMSB, idxLSB) metaArb.io.in(2).bits.addr := Cat(io.cpu.req.bits.addr >> untagBits, s2_vaddr(idxMSB, 0)) metaArb.io.in(2).bits.data := tECC.encode(L1Metadata(s2_req.addr >> tagLSB, s2_new_hit_state).asUInt) // load reservations and TL error reporting val s2_lr = (usingAtomics && !usingDataScratchpad).B && s2_req.cmd === M_XLR val s2_sc = (usingAtomics && !usingDataScratchpad).B && s2_req.cmd === M_XSC val lrscCount = RegInit(0.U) val lrscValid = lrscCount > lrscBackoff.U val lrscBackingOff = lrscCount > 0.U && !lrscValid val lrscAddr = Reg(UInt()) val lrscAddrMatch = lrscAddr === (s2_req.addr >> blockOffBits) val s2_sc_fail = s2_sc && !(lrscValid && lrscAddrMatch) when ((s2_valid_hit && s2_lr && !cached_grant_wait \|\| s2_valid_cached_miss) && !io.cpu.s2_kill) { lrscCount := Mux(s2_hit, (lrscCycles - 1).U, 0.U) lrscAddr := s2_req.addr >> blockOffBits } when (lrscCount > 0.U) { lrscCount := lrscCount - 1.U } when (s2_valid_not_killed && lrscValid) { lrscCount := lrscBackoff.U } when (s1_probe) { lrscCount := 0.U } // don't perform data correction if it might clobber a recent store val s2_correct = s2_data_error && !any_pstore_valid && !RegNext(any_pstore_valid \|\| s2_valid) && usingDataScratchpad.B // pending store buffer val s2_valid_correct = s2_valid_hit_pre_data_ecc_and_waw && s2_correct && !io.cpu.s2_kill def s2_store_valid_pre_kill = s2_valid_hit && s2_write && !s2_sc_fail def s2_store_valid = s2_store_valid_pre_kill && !io.cpu.s2_kill val pstore1_cmd = RegEnable(s1_req.cmd, s1_valid_not_nacked && s1_write) val pstore1_addr = RegEnable(s1_vaddr, s1_valid_not_nacked && s1_write) val pstore1_data = RegEnable(io.cpu.s1_data.data, s1_valid_not_nacked && s1_write) val pstore1_way = RegEnable(s1_hit_way, s1_valid_not_nacked && s1_write) val pstore1_mask = RegEnable(s1_mask, s1_valid_not_nacked && s1_write) val pstore1_storegen_data = WireDefault(pstore1_data) val pstore1_rmw = usingRMW.B && RegEnable(needsRead(s1_req), s1_valid_not_nacked && s1_write) val pstore1_merge_likely = s2_valid_not_nacked_in_s1 && s2_write && s2_store_merge val pstore1_merge = s2_store_valid && s2_store_merge val pstore2_valid = RegInit(false.B) val pstore_drain_opportunistic = !(io.cpu.req.valid && likelyNeedsRead(io.cpu.req.bits)) && !(s1_valid && s1_waw_hazard) val pstore_drain_on_miss = releaseInFlight \|\| RegNext(io.cpu.s2_nack) val pstore1_held = RegInit(false.B) val pstore1_valid_likely = s2_valid && s2_write \|\| pstore1_held def pstore1_valid_not_rmw(s2_kill: Bool) = s2_valid_hit_pre_data_ecc && s2_write && !s2_kill \|\| pstore1_held val pstore1_valid = s2_store_valid \|\| pstore1_held any_pstore_valid := pstore1_held \|\| pstore2_valid val pstore_drain_structural = pstore1_valid_likely && pstore2_valid && ((s1_valid && s1_write) \|\| pstore1_rmw) assert(pstore1_rmw \|\| pstore1_valid_not_rmw(io.cpu.s2_kill) === pstore1_valid) ccover(pstore_drain_structural, "STORE_STRUCTURAL_HAZARD", "D$ read-modify-write structural hazard") ccover(pstore1_valid && pstore_drain_on_miss, "STORE_DRAIN_ON_MISS", "D$ store buffer drain on miss") ccover(s1_valid_not_nacked && s1_waw_hazard, "WAW_HAZARD", "D$ write-after-write hazard") def should_pstore_drain(truly: Bool) = { val s2_kill = truly && io.cpu.s2_kill !pstore1_merge_likely && (usingRMW.B && pstore_drain_structural \|\| (((pstore1_valid_not_rmw(s2_kill) && !pstore1_rmw) \|\| pstore2_valid) && (pstore_drain_opportunistic \|\| pstore_drain_on_miss))) } val pstore_drain = should_pstore_drain(true.B) pstore1_held := (s2_store_valid && !s2_store_merge \|\| pstore1_held) && pstore2_valid && !pstore_drain val advance_pstore1 = (pstore1_valid \|\| s2_valid_correct) && (pstore2_valid === pstore_drain) pstore2_valid := pstore2_valid && !pstore_drain \|\| advance_pstore1 val pstore2_addr = RegEnable(Mux(s2_correct, s2_vaddr, pstore1_addr), advance_pstore1) val pstore2_way = RegEnable(Mux(s2_correct, s2_hit_way, pstore1_way), advance_pstore1) val pstore2_storegen_data = { for (i <- 0 until wordBytes) yield RegEnable(pstore1_storegen_data(8(i+1)-1, 8i), advance_pstore1 \|\| pstore1_merge && pstore1_mask(i)) }.asUInt val pstore2_storegen_mask = { val mask = Reg(UInt(wordBytes.W)) when (advance_pstore1 \|\| pstore1_merge) { val mergedMask = pstore1_mask \| Mux(pstore1_merge, mask, 0.U) mask := ~Mux(s2_correct, 0.U, ~mergedMask) } mask } s2_store_merge := (if (eccBytes == 1) false.B else { ccover(pstore1_merge, "STORE_MERGED", "D$ store merged") // only merge stores to ECC granules that are already stored-to, to avoid // WAW hazards val wordMatch = (eccMask(pstore2_storegen_mask) \| ~eccMask(pstore1_mask)).andR val idxMatch = s2_vaddr(untagBits-1, log2Ceil(wordBytes)) === pstore2_addr(untagBits-1, log2Ceil(wordBytes)) val tagMatch = (s2_hit_way & pstore2_way).orR pstore2_valid && wordMatch && idxMatch && tagMatch }) dataArb.io.in(0).valid := should_pstore_drain(false.B) dataArb.io.in(0).bits.write := pstore_drain dataArb.io.in(0).bits.addr := Mux(pstore2_valid, pstore2_addr, pstore1_addr) dataArb.io.in(0).bits.way_en := Mux(pstore2_valid, pstore2_way, pstore1_way) dataArb.io.in(0).bits.wdata := encodeData(Fill(rowWords, Mux(pstore2_valid, pstore2_storegen_data, pstore1_data)), false.B) dataArb.io.in(0).bits.wordMask := { val eccMask = dataArb.io.in(0).bits.eccMask.asBools.grouped(subWordBytes/eccBytes).map(_.orR).toSeq.asUInt val wordMask = UIntToOH(Mux(pstore2_valid, pstore2_addr, pstore1_addr).extract(rowOffBits-1, wordBytes.log2)) FillInterleaved(wordBytes/subWordBytes, wordMask) & Fill(rowBytes/wordBytes, eccMask) } dataArb.io.in(0).bits.eccMask := eccMask(Mux(pstore2_valid, pstore2_storegen_mask, pstore1_mask)) // store->load RAW hazard detection def s1Depends(addr: UInt, mask: UInt) = addr(idxMSB, wordOffBits) === s1_vaddr(idxMSB, wordOffBits) && Mux(s1_write, (eccByteMask(mask) & eccByteMask(s1_mask_xwr)).orR, (mask & s1_mask_xwr).orR) val s1_hazard = (pstore1_valid_likely && s1Depends(pstore1_addr, pstore1_mask)) \|\| (pstore2_valid && s1Depends(pstore2_addr, pstore2_storegen_mask)) val s1_raw_hazard = s1_read && s1_hazard s1_waw_hazard := (if (eccBytes == 1) false.B else { ccover(s1_valid_not_nacked && s1_waw_hazard, "WAW_HAZARD", "D$ write-after-write hazard") s1_write && (s1_hazard \|\| needsRead(s1_req) && !s1_did_read) }) when (s1_valid && s1_raw_hazard) { s1_nack := true.B } // performance hints to processor io.cpu.s2_nack_cause_raw := RegNext(s1_raw_hazard) \|\| !(!s2_waw_hazard \|\| s2_store_merge) // Prepare a TileLink request message that initiates a transaction val a_source = PriorityEncoder(~uncachedInFlight.asUInt << mmioOffset) // skip the MSHR val acquire_address = (s2_req.addr >> idxLSB) << idxLSB val access_address = s2_req.addr val a_size = s2_req.size val a_data = Fill(beatWords, pstore1_data) val a_mask = pstore1_mask << (access_address.extract(beatBytes.log2-1, wordBytes.log2) << 3) val get = edge.Get(a_source, access_address, a_size)._2 val put = edge.Put(a_source, access_address, a_size, a_data)._2 val putpartial = edge.Put(a_source, access_address, a_size, a_data, a_mask)._2 val atomics = if (edge.manager.anySupportLogical) { MuxLookup(s2_req.cmd, WireDefault(0.U.asTypeOf(new TLBundleA(edge.bundle))))(Array( M_XA_SWAP -> edge.Logical(a_source, access_address, a_size, a_data, TLAtomics.SWAP)._2, M_XA_XOR -> edge.Logical(a_source, access_address, a_size, a_data, TLAtomics.XOR) ._2, M_XA_OR -> edge.Logical(a_source, access_address, a_size, a_data, TLAtomics.OR) ._2, M_XA_AND -> edge.Logical(a_source, access_address, a_size, a_data, TLAtomics.AND) ._2, M_XA_ADD -> edge.Arithmetic(a_source, access_address, a_size, a_data, TLAtomics.ADD)._2, M_XA_MIN -> edge.Arithmetic(a_source, access_address, a_size, a_data, TLAtomics.MIN)._2, M_XA_MAX -> edge.Arithmetic(a_source, access_address, a_size, a_data, TLAtomics.MAX)._2, M_XA_MINU -> edge.Arithmetic(a_source, access_address, a_size, a_data, TLAtomics.MINU)._2, M_XA_MAXU -> edge.Arithmetic(a_source, access_address, a_size, a_data, TLAtomics.MAXU)._2)) } else { // If no managers support atomics, assert fail if processor asks for them assert (!(tl_out_a.valid && s2_read && s2_write && s2_uncached)) WireDefault(new TLBundleA(edge.bundle), DontCare) } tl_out_a.valid := !io.cpu.s2_kill && (s2_valid_uncached_pending \|\| (s2_valid_cached_miss && !(release_ack_wait && (s2_req.addr ^ release_ack_addr)(((pgIdxBits + pgLevelBits) min paddrBits) - 1, idxLSB) === 0.U) && (cacheParams.acquireBeforeRelease.B && !release_ack_wait && release_queue_empty \|\| !s2_victim_dirty))) tl_out_a.bits := Mux(!s2_uncached, acquire(s2_vaddr, s2_req.addr, s2_grow_param), Mux(!s2_write, get, Mux(s2_req.cmd === M_PWR, putpartial, Mux(!s2_read, put, atomics)))) // Drive APROT Bits tl_out_a.bits.user.lift(AMBAProt).foreach { x => val user_bit_cacheable = s2_pma.cacheable x.privileged := s2_req.dprv === PRV.M.U \|\| user_bit_cacheable // if the address is cacheable, enable outer caches x.bufferable := user_bit_cacheable x.modifiable := user_bit_cacheable x.readalloc := user_bit_cacheable x.writealloc := user_bit_cacheable // Following are always tied off x.fetch := false.B x.secure := true.B } // Set pending bits for outstanding TileLink transaction val a_sel = UIntToOH(a_source, maxUncachedInFlight+mmioOffset) >> mmioOffset when (tl_out_a.fire) { when (s2_uncached) { (a_sel.asBools zip (uncachedInFlight zip uncachedReqs)) foreach { case (s, (f, r)) => when (s) { f := true.B r := s2_req r.cmd := Mux(s2_write, Mux(s2_req.cmd === M_PWR, M_PWR, M_XWR), M_XRD) } } }.otherwise { cached_grant_wait := true.B refill_way := s2_victim_or_hit_way } } // grant val (d_first, d_last, d_done, d_address_inc) = edge.addr_inc(tl_out.d) val (d_opc, grantIsUncached, grantIsUncachedData) = { val uncachedGrantOpcodesSansData = Seq(AccessAck, HintAck) val uncachedGrantOpcodesWithData = Seq(AccessAckData) val uncachedGrantOpcodes = uncachedGrantOpcodesWithData ++ uncachedGrantOpcodesSansData val whole_opc = tl_out.d.bits.opcode if (usingDataScratchpad) { assert(!tl_out.d.valid \|\| whole_opc.isOneOf(uncachedGrantOpcodes)) // the only valid TL-D messages are uncached, so we can do some pruning val opc = whole_opc(uncachedGrantOpcodes.map(_.getWidth).max - 1, 0) val data = DecodeLogic(opc, uncachedGrantOpcodesWithData, uncachedGrantOpcodesSansData) (opc, true.B, data) } else { (whole_opc, whole_opc.isOneOf(uncachedGrantOpcodes), whole_opc.isOneOf(uncachedGrantOpcodesWithData)) } } tl_d_data_encoded := encodeData(tl_out.d.bits.data, tl_out.d.bits.corrupt && !io.ptw.customCSRs.suppressCorruptOnGrantData && !grantIsUncached) val grantIsCached = d_opc.isOneOf(Grant, GrantData) val grantIsVoluntary = d_opc === ReleaseAck // Clears a different pending bit val grantIsRefill = d_opc === GrantData // Writes the data array val grantInProgress = RegInit(false.B) val blockProbeAfterGrantCount = RegInit(0.U) when (blockProbeAfterGrantCount > 0.U) { blockProbeAfterGrantCount := blockProbeAfterGrantCount - 1.U } val canAcceptCachedGrant = !release_state.isOneOf(s_voluntary_writeback, s_voluntary_write_meta, s_voluntary_release) tl_out.d.ready := Mux(grantIsCached, (!d_first \|\| tl_out.e.ready) && canAcceptCachedGrant, true.B) val uncachedRespIdxOH = UIntToOH(tl_out.d.bits.source, maxUncachedInFlight+mmioOffset) >> mmioOffset uncachedResp := Mux1H(uncachedRespIdxOH, uncachedReqs) when (tl_out.d.fire) { when (grantIsCached) { grantInProgress := true.B assert(cached_grant_wait, "A GrantData was unexpected by the dcache.") when(d_last) { cached_grant_wait := false.B grantInProgress := false.B blockProbeAfterGrantCount := (blockProbeAfterGrantCycles - 1).U replacer.miss } } .elsewhen (grantIsUncached) { (uncachedRespIdxOH.asBools zip uncachedInFlight) foreach { case (s, f) => when (s && d_last) { assert(f, "An AccessAck was unexpected by the dcache.") // TODO must handle Ack coming back on same cycle! f := false.B } } when (grantIsUncachedData) { if (!cacheParams.separateUncachedResp) { if (!cacheParams.pipelineWayMux) s1_data_way := 1.U << nWays s2_req.cmd := M_XRD s2_req.size := uncachedResp.size s2_req.signed := uncachedResp.signed s2_req.tag := uncachedResp.tag s2_req.addr := { require(rowOffBits >= beatOffBits) val dontCareBits = s1_paddr >> rowOffBits << rowOffBits dontCareBits \| uncachedResp.addr(beatOffBits-1, 0) } s2_uncached_resp_addr := uncachedResp.addr } } } .elsewhen (grantIsVoluntary) { assert(release_ack_wait, "A ReleaseAck was unexpected by the dcache.") // TODO should handle Ack coming back on same cycle! release_ack_wait := false.B } } // Finish TileLink transaction by issuing a GrantAck tl_out.e.valid := tl_out.d.valid && d_first && grantIsCached && canAcceptCachedGrant tl_out.e.bits := edge.GrantAck(tl_out.d.bits) assert(tl_out.e.fire === (tl_out.d.fire && d_first && grantIsCached)) // data refill // note this ready-valid signaling ignores E-channel backpressure, which // benignly means the data RAM might occasionally be redundantly written dataArb.io.in(1).valid := tl_out.d.valid && grantIsRefill && canAcceptCachedGrant when (grantIsRefill && !dataArb.io.in(1).ready) { tl_out.e.valid := false.B tl_out.d.ready := false.B } if (!usingDataScratchpad) { dataArb.io.in(1).bits.write := true.B dataArb.io.in(1).bits.addr := (s2_vaddr >> idxLSB) << idxLSB \| d_address_inc dataArb.io.in(1).bits.way_en := refill_way dataArb.io.in(1).bits.wdata := tl_d_data_encoded dataArb.io.in(1).bits.wordMask := ~0.U((rowBytes / subWordBytes).W) dataArb.io.in(1).bits.eccMask := ~0.U((wordBytes / eccBytes).W) } else { dataArb.io.in(1).bits := dataArb.io.in(0).bits } // tag updates on refill // ignore backpressure from metaArb, which can only be caused by tag ECC // errors on hit-under-miss. failing to write the new tag will leave the // line invalid, so we'll simply request the line again later. metaArb.io.in(3).valid := grantIsCached && d_done && !tl_out.d.bits.denied metaArb.io.in(3).bits.write := true.B metaArb.io.in(3).bits.way_en := refill_way metaArb.io.in(3).bits.idx := s2_vaddr(idxMSB, idxLSB) metaArb.io.in(3).bits.addr := Cat(io.cpu.req.bits.addr >> untagBits, s2_vaddr(idxMSB, 0)) metaArb.io.in(3).bits.data := tECC.encode(L1Metadata(s2_req.addr >> tagLSB, s2_hit_state.onGrant(s2_req.cmd, tl_out.d.bits.param)).asUInt) if (!cacheParams.separateUncachedResp) { // don't accept uncached grants if there's a structural hazard on s2_data... val blockUncachedGrant = Reg(Bool()) blockUncachedGrant := dataArb.io.out.valid when (grantIsUncachedData && (blockUncachedGrant \|\| s1_valid)) { tl_out.d.ready := false.B // ...but insert bubble to guarantee grant's eventual forward progress when (tl_out.d.valid) { io.cpu.req.ready := false.B dataArb.io.in(1).valid := true.B dataArb.io.in(1).bits.write := false.B blockUncachedGrant := !dataArb.io.in(1).ready } } } ccover(tl_out.d.valid && !tl_out.d.ready, "BLOCK_D", "D$ D-channel blocked") // Handle an incoming TileLink Probe message val block_probe_for_core_progress = blockProbeAfterGrantCount > 0.U \|\| lrscValid val block_probe_for_pending_release_ack = release_ack_wait && (tl_out.b.bits.address ^ release_ack_addr)(((pgIdxBits + pgLevelBits) min paddrBits) - 1, idxLSB) === 0.U val block_probe_for_ordering = releaseInFlight \|\| block_probe_for_pending_release_ack \|\| grantInProgress metaArb.io.in(6).valid := tl_out.b.valid && (!block_probe_for_core_progress \|\| lrscBackingOff) tl_out.b.ready := metaArb.io.in(6).ready && !(block_probe_for_core_progress \|\| block_probe_for_ordering \|\| s1_valid \|\| s2_valid) metaArb.io.in(6).bits.write := false.B metaArb.io.in(6).bits.idx := probeIdx(tl_out.b.bits) metaArb.io.in(6).bits.addr := Cat(io.cpu.req.bits.addr >> paddrBits, tl_out.b.bits.address) metaArb.io.in(6).bits.way_en := metaArb.io.in(4).bits.way_en metaArb.io.in(6).bits.data := metaArb.io.in(4).bits.data // replacement policy s1_victim_way := (if (replacer.perSet && nWays > 1) { val repl_array = Mem(nSets, UInt(replacer.nBits.W)) val s1_repl_idx = s1_req.addr(idxBits+blockOffBits-1, blockOffBits) val s2_repl_idx = s2_vaddr(idxBits+blockOffBits-1, blockOffBits) val s2_repl_state = Reg(UInt(replacer.nBits.W)) val s2_new_repl_state = replacer.get_next_state(s2_repl_state, OHToUInt(s2_hit_way)) val s2_repl_wen = s2_valid_masked && s2_hit_way.orR && s2_repl_state =/= s2_new_repl_state val s1_repl_state = Mux(s2_repl_wen && s2_repl_idx === s1_repl_idx, s2_new_repl_state, repl_array(s1_repl_idx)) when (s1_valid_not_nacked) { s2_repl_state := s1_repl_state } val waddr = Mux(resetting, flushCounter(idxBits-1, 0), s2_repl_idx) val wdata = Mux(resetting, 0.U, s2_new_repl_state) val wen = resetting \|\| s2_repl_wen when (wen) { repl_array(waddr) := wdata } replacer.get_replace_way(s1_repl_state) } else { replacer.way }) // release val (c_first, c_last, releaseDone, c_count) = edge.count(tl_out_c) val releaseRejected = Wire(Bool()) val s1_release_data_valid = RegNext(dataArb.io.in(2).fire) val s2_release_data_valid = RegNext(s1_release_data_valid && !releaseRejected) releaseRejected := s2_release_data_valid && !tl_out_c.fire val releaseDataBeat = Cat(0.U, c_count) + Mux(releaseRejected, 0.U, s1_release_data_valid + Cat(0.U, s2_release_data_valid)) val nackResponseMessage = edge.ProbeAck(b = probe_bits, reportPermissions = TLPermissions.NtoN) val cleanReleaseMessage = edge.ProbeAck(b = probe_bits, reportPermissions = s2_report_param) val dirtyReleaseMessage = edge.ProbeAck(b = probe_bits, reportPermissions = s2_report_param, data = 0.U) tl_out_c.valid := (s2_release_data_valid \|\| (!cacheParams.silentDrop.B && release_state === s_voluntary_release)) && !(c_first && release_ack_wait) tl_out_c.bits := nackResponseMessage val newCoh = WireDefault(probeNewCoh) releaseWay := s2_probe_way if (!usingDataScratchpad) { when (s2_victimize) { assert(s2_valid_flush_line \|\| s2_flush_valid \|\| io.cpu.s2_nack) val discard_line = s2_valid_flush_line && s2_req.size(1) \|\| s2_flush_valid && flushing_req.size(1) release_state := Mux(s2_victim_dirty && !discard_line, s_voluntary_writeback, Mux(!cacheParams.silentDrop.B && !release_ack_wait && release_queue_empty && s2_victim_state.isValid() && (s2_valid_flush_line \|\| s2_flush_valid \|\| s2_readwrite && !s2_hit_valid), s_voluntary_release, s_voluntary_write_meta)) probe_bits := addressToProbe(s2_vaddr, Cat(s2_victim_tag, s2_req.addr(tagLSB-1, idxLSB)) << idxLSB) } when (s2_probe) { val probeNack = WireDefault(true.B) when (s2_meta_error) { release_state := s_probe_retry }.elsewhen (s2_prb_ack_data) { release_state := s_probe_rep_dirty }.elsewhen (s2_probe_state.isValid()) { tl_out_c.valid := true.B tl_out_c.bits := cleanReleaseMessage release_state := Mux(releaseDone, s_probe_write_meta, s_probe_rep_clean) }.otherwise { tl_out_c.valid := true.B probeNack := !releaseDone release_state := Mux(releaseDone, s_ready, s_probe_rep_miss) } when (probeNack) { s1_nack := true.B } } when (release_state === s_probe_retry) { metaArb.io.in(6).valid := true.B metaArb.io.in(6).bits.idx := probeIdx(probe_bits) metaArb.io.in(6).bits.addr := Cat(io.cpu.req.bits.addr >> paddrBits, probe_bits.address) when (metaArb.io.in(6).ready) { release_state := s_ready s1_probe := true.B } } when (release_state === s_probe_rep_miss) { tl_out_c.valid := true.B when (releaseDone) { release_state := s_ready } } when (release_state === s_probe_rep_clean) { tl_out_c.valid := true.B tl_out_c.bits := cleanReleaseMessage when (releaseDone) { release_state := s_probe_write_meta } } when (release_state === s_probe_rep_dirty) { tl_out_c.bits := dirtyReleaseMessage when (releaseDone) { release_state := s_probe_write_meta } } when (release_state.isOneOf(s_voluntary_writeback, s_voluntary_write_meta, s_voluntary_release)) { when (release_state === s_voluntary_release) { tl_out_c.bits := edge.Release(fromSource = 0.U, toAddress = 0.U, lgSize = lgCacheBlockBytes.U, shrinkPermissions = s2_shrink_param)._2 }.otherwise { tl_out_c.bits := edge.Release(fromSource = 0.U, toAddress = 0.U, lgSize = lgCacheBlockBytes.U, shrinkPermissions = s2_shrink_param, data = 0.U)._2 } newCoh := voluntaryNewCoh releaseWay := s2_victim_or_hit_way when (releaseDone) { release_state := s_voluntary_write_meta } when (tl_out_c.fire && c_first) { release_ack_wait := true.B release_ack_addr := probe_bits.address } } tl_out_c.bits.source := probe_bits.source tl_out_c.bits.address := probe_bits.address tl_out_c.bits.data := s2_data_corrected tl_out_c.bits.corrupt := inWriteback && s2_data_error_uncorrectable } tl_out_c.bits.user.lift(AMBAProt).foreach { x => x.fetch := false.B x.secure := true.B x.privileged := true.B x.bufferable := true.B x.modifiable := true.B x.readalloc := true.B x.writealloc := true.B } dataArb.io.in(2).valid := inWriteback && releaseDataBeat < refillCycles.U dataArb.io.in(2).bits := dataArb.io.in(1).bits dataArb.io.in(2).bits.write := false.B dataArb.io.in(2).bits.addr := (probeIdx(probe_bits) << blockOffBits) \| (releaseDataBeat(log2Up(refillCycles)-1,0) << rowOffBits) dataArb.io.in(2).bits.wordMask := ~0.U((rowBytes / subWordBytes).W) dataArb.io.in(2).bits.eccMask := ~0.U((wordBytes / eccBytes).W) dataArb.io.in(2).bits.way_en := ~0.U(nWays.W) metaArb.io.in(4).valid := release_state.isOneOf(s_voluntary_write_meta, s_probe_write_meta) metaArb.io.in(4).bits.write := true.B metaArb.io.in(4).bits.way_en := releaseWay metaArb.io.in(4).bits.idx := probeIdx(probe_bits) metaArb.io.in(4).bits.addr := Cat(io.cpu.req.bits.addr >> untagBits, probe_bits.address(idxMSB, 0)) metaArb.io.in(4).bits.data := tECC.encode(L1Metadata(tl_out_c.bits.address >> tagLSB, newCoh).asUInt) when (metaArb.io.in(4).fire) { release_state := s_ready } // cached response (io.cpu.resp.bits: Data).waiveAll :<>= (s2_req: Data).waiveAll io.cpu.resp.bits.has_data := s2_read io.cpu.resp.bits.replay := false.B io.cpu.s2_uncached := s2_uncached && !s2_hit io.cpu.s2_paddr := s2_req.addr io.cpu.s2_gpa := s2_tlb_xcpt.gpa io.cpu.s2_gpa_is_pte := s2_tlb_xcpt.gpa_is_pte // report whether there are any outstanding accesses. disregard any // slave-port accesses, since they don't affect local memory ordering. val s1_isSlavePortAccess = s1_req.no_xcpt val s2_isSlavePortAccess = s2_req.no_xcpt io.cpu.ordered := !(s1_valid && !s1_isSlavePortAccess \|\| s2_valid && !s2_isSlavePortAccess \|\| cached_grant_wait \|\| uncachedInFlight.asUInt.orR) io.cpu.store_pending := (cached_grant_wait && isWrite(s2_req.cmd)) \|\| uncachedInFlight.asUInt.orR val s1_xcpt_valid = tlb.io.req.valid && !s1_isSlavePortAccess && !s1_nack io.cpu.s2_xcpt := Mux(RegNext(s1_xcpt_valid), s2_tlb_xcpt, 0.U.asTypeOf(s2_tlb_xcpt)) if (usingDataScratchpad) { assert(!(s2_valid_masked && s2_req.cmd.isOneOf(M_XLR, M_XSC))) } else { ccover(tl_out.b.valid && !tl_out.b.ready, "BLOCK_B", "D$ B-channel blocked") } // uncached response val s1_uncached_data_word = { val word_idx = uncachedResp.addr.extract(log2Up(rowBits/8)-1, log2Up(wordBytes)) val words = tl_out.d.bits.data.grouped(wordBits) words(word_idx) } val s2_uncached_data_word = RegEnable(s1_uncached_data_word, io.cpu.replay_next) val doUncachedResp = RegNext(io.cpu.replay_next) io.cpu.resp.valid := (s2_valid_hit_pre_data_ecc \|\| doUncachedResp) && !s2_data_error io.cpu.replay_next := tl_out.d.fire && grantIsUncachedData && !cacheParams.separateUncachedResp.B when (doUncachedResp) { assert(!s2_valid_hit) io.cpu.resp.bits.replay := true.B io.cpu.resp.bits.addr := s2_uncached_resp_addr } io.cpu.uncached_resp.map { resp => resp.valid := tl_out.d.valid && grantIsUncachedData resp.bits.tag := uncachedResp.tag resp.bits.size := uncachedResp.size resp.bits.signed := uncachedResp.signed resp.bits.data := new LoadGen(uncachedResp.size, uncachedResp.signed, uncachedResp.addr, s1_uncached_data_word, false.B, wordBytes).data resp.bits.data_raw := s1_uncached_data_word when (grantIsUncachedData && !resp.ready) { tl_out.d.ready := false.B } } // load data subword mux/sign extension val s2_data_word = (0 until rowBits by wordBits).map(i => s2_data_uncorrected(wordBits+i-1,i)).reduce(_\|_) val s2_data_word_corrected = (0 until rowBits by wordBits).map(i => s2_data_corrected(wordBits+i-1,i)).reduce(_\|_) val s2_data_word_possibly_uncached = Mux(cacheParams.pipelineWayMux.B && doUncachedResp, s2_uncached_data_word, 0.U) \| s2_data_word val loadgen = new LoadGen(s2_req.size, s2_req.signed, s2_req.addr, s2_data_word_possibly_uncached, s2_sc, wordBytes) io.cpu.resp.bits.data := loadgen.data \| s2_sc_fail io.cpu.resp.bits.data_word_bypass := loadgen.wordData io.cpu.resp.bits.data_raw := s2_data_word io.cpu.resp.bits.store_data := pstore1_data // AMOs if (usingRMW) { val amoalus = (0 until coreDataBits / xLen).map { i => val amoalu = Module(new AMOALU(xLen)) amoalu.io.mask := pstore1_mask >> (i * xBytes) amoalu.io.cmd := (if (usingAtomicsInCache) pstore1_cmd else M_XWR) amoalu.io.lhs := s2_data_word >> (i * xLen) amoalu.io.rhs := pstore1_data >> (i * xLen) amoalu } pstore1_storegen_data := (if (!usingDataScratchpad) amoalus.map(_.io.out).asUInt else { val mask = FillInterleaved(8, Mux(s2_correct, 0.U, pstore1_mask)) amoalus.map(_.io.out_unmasked).asUInt & mask \| s2_data_word_corrected & ~mask }) } else if (!usingAtomics) { assert(!(s1_valid_masked && s1_read && s1_write), "unsupported D$ operation") } if (coreParams.useVector) { edge.manager.managers.foreach { m => // Statically ensure that no-allocate accesses are permitted. // We could consider turning some of these into dynamic PMA checks. require(!m.supportsAcquireB \|\| m.supportsGet, "With a vector unit, cacheable memory must support Get") require(!m.supportsAcquireT \|\| m.supportsPutPartial, "With a vector unit, cacheable memory must support PutPartial") } } // flushes if (!usingDataScratchpad) when (RegNext(reset.asBool)) { resetting := true.B } val flushCounterNext = flushCounter +& 1.U val flushDone = (flushCounterNext >> log2Ceil(nSets)) === nWays.U val flushCounterWrap = flushCounterNext(log2Ceil(nSets)-1, 0) ccover(s2_valid_masked && s2_cmd_flush_all && s2_meta_error, "TAG_ECC_ERROR_DURING_FENCE_I", "D$ ECC error in tag array during cache flush") ccover(s2_valid_masked && s2_cmd_flush_all && s2_data_error, "DATA_ECC_ERROR_DURING_FENCE_I", "D$ ECC error in data array during cache flush") s1_flush_valid := metaArb.io.in(5).fire && !s1_flush_valid && !s2_flush_valid_pre_tag_ecc && release_state === s_ready && !release_ack_wait metaArb.io.in(5).valid := flushing && !flushed metaArb.io.in(5).bits.write := false.B metaArb.io.in(5).bits.idx := flushCounter(idxBits-1, 0) metaArb.io.in(5).bits.addr := Cat(io.cpu.req.bits.addr >> untagBits, metaArb.io.in(5).bits.idx << blockOffBits) metaArb.io.in(5).bits.way_en := metaArb.io.in(4).bits.way_en metaArb.io.in(5).bits.data := metaArb.io.in(4).bits.data // Only flush D$ on FENCE.I if some cached executable regions are untracked. if (supports_flush) { when (s2_valid_masked && s2_cmd_flush_all) { when (!flushed && !io.cpu.s2_kill && !release_ack_wait && !uncachedInFlight.asUInt.orR) { flushing := true.B flushing_req := s2_req } } when (tl_out_a.fire && !s2_uncached) { flushed := false.B } when (flushing) { s1_victim_way := flushCounter >> log2Up(nSets) when (s2_flush_valid) { flushCounter := flushCounterNext when (flushDone) { flushed := true.B if (!isPow2(nWays)) flushCounter := flushCounterWrap } } when (flushed && release_state === s_ready && !release_ack_wait) { flushing := false.B } } } metaArb.io.in(0).valid := resetting metaArb.io.in(0).bits := metaArb.io.in(5).bits metaArb.io.in(0).bits.write := true.B metaArb.io.in(0).bits.way_en := ~0.U(nWays.W) metaArb.io.in(0).bits.data := tECC.encode(L1Metadata(0.U, ClientMetadata.onReset).asUInt) when (resetting) { flushCounter := flushCounterNext when (flushDone) { resetting := false.B if (!isPow2(nWays)) flushCounter := flushCounterWrap } } // gate the clock clock_en_reg := !cacheParams.clockGate.B \|\| io.ptw.customCSRs.disableDCacheClockGate \|\| io.cpu.keep_clock_enabled \|\| metaArb.io.out.valid \|\| // subsumes resetting \|\| flushing s1_probe \|\| s2_probe \|\| s1_valid \|\| s2_valid \|\| io.tlb_port.req.valid \|\| s1_tlb_req_valid \|\| s2_tlb_req_valid \|\| pstore1_held \|\| pstore2_valid \|\| release_state =/= s_ready \|\| release_ack_wait \|\| !release_queue_empty \|\| !tlb.io.req.ready \|\| cached_grant_wait \|\| uncachedInFlight.asUInt.orR \|\| lrscCount > 0.U \|\| blockProbeAfterGrantCount > 0.U // performance events io.cpu.perf.acquire := edge.done(tl_out_a) io.cpu.perf.release := edge.done(tl_out_c) io.cpu.perf.grant := tl_out.d.valid && d_last io.cpu.perf.tlbMiss := io.ptw.req.fire io.cpu.perf.storeBufferEmptyAfterLoad := !( (s1_valid && s1_write) \|\| ((s2_valid && s2_write && !s2_waw_hazard) \|\| pstore1_held) \|\| pstore2_valid) io.cpu.perf.storeBufferEmptyAfterStore := !( (s1_valid && s1_write) \|\| (s2_valid && s2_write && pstore1_rmw) \|\| ((s2_valid && s2_write && !s2_waw_hazard \|\| pstore1_held) && pstore2_valid)) io.cpu.perf.canAcceptStoreThenLoad := !( ((s2_valid && s2_write && pstore1_rmw) && (s1_valid && s1_write && !s1_waw_hazard)) \|\| (pstore2_valid && pstore1_valid_likely && (s1_valid && s1_write))) io.cpu.perf.canAcceptStoreThenRMW := io.cpu.perf.canAcceptStoreThenLoad && !pstore2_valid io.cpu.perf.canAcceptLoadThenLoad := !((s1_valid && s1_write && needsRead(s1_req)) && ((s2_valid && s2_write && !s2_waw_hazard \|\| pstore1_held) \|\| pstore2_valid)) io.cpu.perf.blocked := { // stop reporting blocked just before unblocking to avoid overly conservative stalling val beatsBeforeEnd = outer.crossing match { case SynchronousCrossing(_) => 2 case RationalCrossing(_) => 1 // assumes 1 < ratio <= 2; need more bookkeeping for optimal handling of >2 case _: AsynchronousCrossing => 1 // likewise case _: CreditedCrossing => 1 // likewise } val near_end_of_refill = if (cacheBlockBytes / beatBytes <= beatsBeforeEnd) tl_out.d.valid else { val refill_count = RegInit(0.U((cacheBlockBytes / beatBytes).log2.W)) when (tl_out.d.fire && grantIsRefill) { refill_count := refill_count + 1.U } refill_count >= (cacheBlockBytes / beatBytes - beatsBeforeEnd).U } cached_grant_wait && !near_end_of_refill } // report errors val (data_error, data_error_uncorrectable, data_error_addr) = if (usingDataScratchpad) (s2_valid_data_error, s2_data_error_uncorrectable, s2_req.addr) else { (RegNext(tl_out_c.fire && inWriteback && s2_data_error), RegNext(s2_data_error_uncorrectable), probe_bits.address) // This is stable for a cycle after tl_out_c.fire, so don't need a register } { val error_addr = Mux(metaArb.io.in(1).valid, Cat(s2_first_meta_corrected.tag, metaArb.io.in(1).bits.addr(tagLSB-1, idxLSB)), data_error_addr >> idxLSB) << idxLSB io.errors.uncorrectable.foreach { u => u.valid := metaArb.io.in(1).valid && s2_meta_error_uncorrectable \|\| data_error && data_error_uncorrectable u.bits := error_addr } io.errors.correctable.foreach { c => c.valid := metaArb.io.in(1).valid \|\| data_error c.bits := error_addr io.errors.uncorrectable.foreach { u => when (u.valid) { c.valid := false.B } } } io.errors.bus.valid := tl_out.d.fire && (tl_out.d.bits.denied \|\| tl_out.d.bits.corrupt) io.errors.bus.bits := Mux(grantIsCached, s2_req.addr >> idxLSB << idxLSB, 0.U) ccoverNotScratchpad(io.errors.bus.valid && grantIsCached, "D_ERROR_CACHED", "D$ D-channel error, cached") ccover(io.errors.bus.valid && !grantIsCached, "D_ERROR_UNCACHED", "D$ D-channel error, uncached") } if (usingDataScratchpad) { val data_error_cover = Seq( property.CoverBoolean(!data_error, Seq("no_data_error")), property.CoverBoolean(data_error && !data_error_uncorrectable, Seq("data_correctable_error")), property.CoverBoolean(data_error && data_error_uncorrectable, Seq("data_uncorrectable_error"))) val request_source = Seq( property.CoverBoolean(s2_isSlavePortAccess, Seq("from_TL")), property.CoverBoolean(!s2_isSlavePortAccess, Seq("from_CPU"))) property.cover(new property.CrossProperty( Seq(data_error_cover, request_source), Seq(), "MemorySystem;;Scratchpad Memory Bit Flip Cross Covers")) } else { val data_error_type = Seq( property.CoverBoolean(!s2_valid_data_error, Seq("no_data_error")), property.CoverBoolean(s2_valid_data_error && !s2_data_error_uncorrectable, Seq("data_correctable_error")), property.CoverBoolean(s2_valid_data_error && s2_data_error_uncorrectable, Seq("data_uncorrectable_error"))) val data_error_dirty = Seq( property.CoverBoolean(!s2_victim_dirty, Seq("data_clean")), property.CoverBoolean(s2_victim_dirty, Seq("data_dirty"))) val request_source = if (supports_flush) { Seq( property.CoverBoolean(!flushing, Seq("access")), property.CoverBoolean(flushing, Seq("during_flush"))) } else { Seq(property.CoverBoolean(true.B, Seq("never_flush"))) } val tag_error_cover = Seq( property.CoverBoolean( !s2_meta_error, Seq("no_tag_error")), property.CoverBoolean( s2_meta_error && !s2_meta_error_uncorrectable, Seq("tag_correctable_error")), property.CoverBoolean( s2_meta_error && s2_meta_error_uncorrectable, Seq("tag_uncorrectable_error"))) property.cover(new property.CrossProperty( Seq(data_error_type, data_error_dirty, request_source, tag_error_cover), Seq(), "MemorySystem;;Cache Memory Bit Flip Cross Covers")) } } // leaving gated-clock domain val dcacheImpl = withClock (gated_clock) { new DCacheModuleImpl } def encodeData(x: UInt, poison: Bool) = x.grouped(eccBits).map(dECC.encode(_, if (dECC.canDetect) poison else false.B)).asUInt def dummyEncodeData(x: UInt) = x.grouped(eccBits).map(dECC.swizzle(_)).asUInt def decodeData(x: UInt) = x.grouped(dECC.width(eccBits)).map(dECC.decode(_)) def eccMask(byteMask: UInt) = byteMask.grouped(eccBytes).map(_.orR).asUInt def eccByteMask(byteMask: UInt) = FillInterleaved(eccBytes, eccMask(byteMask)) def likelyNeedsRead(req: HellaCacheReq) = { val res = !req.cmd.isOneOf(M_XWR, M_PFW) \|\| req.size < log2Ceil(eccBytes).U assert(!needsRead(req) \|\| res) res } def needsRead(req: HellaCacheReq) = isRead(req.cmd) \|\| (isWrite(req.cmd) && (req.cmd === M_PWR \|\| req.size < log2Ceil(eccBytes).U)) def ccover(cond: Bool, label: String, desc: String)(implicit sourceInfo: SourceInfo) = property.cover(cond, s"DCACHE_$label", "MemorySystem;;" + desc) def ccoverNotScratchpad(cond: Bool, label: String, desc: String)(implicit sourceInfo: SourceInfo) = if (!usingDataScratchpad) ccover(cond, label, desc) require(!usingVM \|\| tagLSB <= pgIdxBits, s"D$$ set size must not exceed ${1<<(pgIdxBits-10)} KiB; got ${(nSets * cacheBlockBytes)>>10} KiB") def tagLSB: Int = untagBits def probeIdx(b: TLBundleB): UInt = b.address(idxMSB, idxLSB) def addressToProbe(vaddr: UInt, paddr: UInt): TLBundleB = { val res = Wire(new TLBundleB(edge.bundle)) res :#= DontCare res.address := paddr res.source := (mmioOffset - 1).U res } def acquire(vaddr: UInt, paddr: UInt, param: UInt): TLBundleA = { if (!edge.manager.anySupportAcquireB) WireDefault(0.U.asTypeOf(new TLBundleA(edge.bundle))) else edge.AcquireBlock(0.U, paddr >> lgCacheBlockBytes << lgCacheBlockBytes, lgCacheBlockBytes.U, param)._2 } } File DescribedSRAM.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3.{Data, SyncReadMem, Vec} import chisel3.util.log2Ceil object DescribedSRAM { def apply[T <: Data]( name: String, desc: String, size: BigInt, // depth data: T ): SyncReadMem[T] = { val mem = SyncReadMem(size, data) mem.suggestName(name) val granWidth = data match { case v: Vec[_] => v.head.getWidth case d => d.getWidth } val uid = 0 Annotated.srams( component = mem, name = name, address_width = log2Ceil(size), data_width = data.getWidth, depth = size, description = desc, write_mask_granularity = granWidth ) mem } }	module DCacheDataArray( // @[DCache.scala:49:7] input clock, // @[DCache.scala:49:7] input reset, // @[DCache.scala:49:7] input io_req_valid, // @[DCache.scala:50:14] input [11:0] io_req_bits_addr, // @[DCache.scala:50:14] input io_req_bits_write, // @[DCache.scala:50:14] input [63:0] io_req_bits_wdata, // @[DCache.scala:50:14] input io_req_bits_wordMask, // @[DCache.scala:50:14] input [7:0] io_req_bits_eccMask, // @[DCache.scala:50:14] input [7:0] io_req_bits_way_en, // @[DCache.scala:50:14] output [63:0] io_resp_0, // @[DCache.scala:50:14] output [63:0] io_resp_1, // @[DCache.scala:50:14] output [63:0] io_resp_2, // @[DCache.scala:50:14] output [63:0] io_resp_3, // @[DCache.scala:50:14] output [63:0] io_resp_4, // @[DCache.scala:50:14] output [63:0] io_resp_5, // @[DCache.scala:50:14] output [63:0] io_resp_6, // @[DCache.scala:50:14] output [63:0] io_resp_7 // @[DCache.scala:50:14] ); wire [511:0] _rockettile_dcache_data_arrays_0_RW0_rdata; // @[DescribedSRAM.scala:17:26] wire io_req_valid_0 = io_req_valid; // @[DCache.scala:49:7] wire [11:0] io_req_bits_addr_0 = io_req_bits_addr; // @[DCache.scala:49:7] wire io_req_bits_write_0 = io_req_bits_write; // @[DCache.scala:49:7] wire [63:0] io_req_bits_wdata_0 = io_req_bits_wdata; // @[DCache.scala:49:7] wire io_req_bits_wordMask_0 = io_req_bits_wordMask; // @[DCache.scala:49:7] wire [7:0] io_req_bits_eccMask_0 = io_req_bits_eccMask; // @[DCache.scala:49:7] wire [7:0] io_req_bits_way_en_0 = io_req_bits_way_en; // @[DCache.scala:49:7] wire _rdata_valid_T_1 = 1'h1; // @[DCache.scala:71:60] wire rdata_valid = io_req_valid_0; // @[DCache.scala:49:7, :71:30] wire [63:0] wWords_0 = io_req_bits_wdata_0; // @[package.scala:211:50] wire _rdata_valid_T = io_req_bits_wordMask_0; // @[DCache.scala:49:7, :71:83] wire [63:0] rdata_0_0; // @[package.scala:45:27] wire [63:0] rdata_0_1; // @[package.scala:45:27] wire [63:0] rdata_0_2; // @[package.scala:45:27] wire [63:0] rdata_0_3; // @[package.scala:45:27] wire [63:0] rdata_0_4; // @[package.scala:45:27] wire [63:0] rdata_0_5; // @[package.scala:45:27] wire [63:0] rdata_0_6; // @[package.scala:45:27] wire [63:0] rdata_0_7; // @[package.scala:45:27] wire [63:0] io_resp_0_0; // @[DCache.scala:49:7] wire [63:0] io_resp_1_0; // @[DCache.scala:49:7] wire [63:0] io_resp_2_0; // @[DCache.scala:49:7] wire [63:0] io_resp_3_0; // @[DCache.scala:49:7] wire [63:0] io_resp_4_0; // @[DCache.scala:49:7] wire [63:0] io_resp_5_0; // @[DCache.scala:49:7] wire [63:0] io_resp_6_0; // @[DCache.scala:49:7] wire [63:0] io_resp_7_0; // @[DCache.scala:49:7] wire eccMask_0 = io_req_bits_eccMask_0[0]; // @[DCache.scala:49:7, :56:82] wire eccMask_1 = io_req_bits_eccMask_0[1]; // @[DCache.scala:49:7, :56:82] wire eccMask_2 = io_req_bits_eccMask_0[2]; // @[DCache.scala:49:7, :56:82] wire eccMask_3 = io_req_bits_eccMask_0[3]; // @[DCache.scala:49:7, :56:82] wire eccMask_4 = io_req_bits_eccMask_0[4]; // @[DCache.scala:49:7, :56:82] wire eccMask_5 = io_req_bits_eccMask_0[5]; // @[DCache.scala:49:7, :56:82] wire eccMask_6 = io_req_bits_eccMask_0[6]; // @[DCache.scala:49:7, :56:82] wire eccMask_7 = io_req_bits_eccMask_0[7]; // @[DCache.scala:49:7, :56:82] wire _wMask_T = io_req_bits_way_en_0[0]; // @[DCache.scala:49:7, :57:108] wire _wMask_T_1 = io_req_bits_way_en_0[0]; // @[DCache.scala:49:7, :57:108] wire _wMask_T_2 = io_req_bits_way_en_0[0]; // @[DCache.scala:49:7, :57:108] wire _wMask_T_3 = io_req_bits_way_en_0[0]; // @[DCache.scala:49:7, :57:108] wire _wMask_T_4 = io_req_bits_way_en_0[0]; // @[DCache.scala:49:7, :57:108] wire _wMask_T_5 = io_req_bits_way_en_0[0]; // @[DCache.scala:49:7, :57:108] wire _wMask_T_6 = io_req_bits_way_en_0[0]; // @[DCache.scala:49:7, :57:108] wire _wMask_T_7 = io_req_bits_way_en_0[0]; // @[DCache.scala:49:7, :57:108] wire wMask_0 = eccMask_0 & _wMask_T; // @[DCache.scala:56:82, :57:{87,108}] wire wMask_1 = eccMask_1 & _wMask_T_1; // @[DCache.scala:56:82, :57:{87,108}] wire wMask_2 = eccMask_2 & _wMask_T_2; // @[DCache.scala:56:82, :57:{87,108}] wire wMask_3 = eccMask_3 & _wMask_T_3; // @[DCache.scala:56:82, :57:{87,108}] wire wMask_4 = eccMask_4 & _wMask_T_4; // @[DCache.scala:56:82, :57:{87,108}] wire wMask_5 = eccMask_5 & _wMask_T_5; // @[DCache.scala:56:82, :57:{87,108}] wire wMask_6 = eccMask_6 & _wMask_T_6; // @[DCache.scala:56:82, :57:{87,108}] wire wMask_7 = eccMask_7 & _wMask_T_7; // @[DCache.scala:56:82, :57:{87,108}] wire _wMask_T_8 = io_req_bits_way_en_0[1]; // @[DCache.scala:49:7, :57:108] wire _wMask_T_9 = io_req_bits_way_en_0[1]; // @[DCache.scala:49:7, :57:108] wire _wMask_T_10 = io_req_bits_way_en_0[1]; // @[DCache.scala:49:7, :57:108] wire _wMask_T_11 = io_req_bits_way_en_0[1]; // @[DCache.scala:49:7, :57:108] wire _wMask_T_12 = io_req_bits_way_en_0[1]; // @[DCache.scala:49:7, :57:108] wire _wMask_T_13 = io_req_bits_way_en_0[1]; // @[DCache.scala:49:7, :57:108] wire _wMask_T_14 = io_req_bits_way_en_0[1]; // @[DCache.scala:49:7, :57:108] wire _wMask_T_15 = io_req_bits_way_en_0[1]; // @[DCache.scala:49:7, :57:108] wire wMask_8 = eccMask_0 & _wMask_T_8; // @[DCache.scala:56:82, :57:{87,108}] wire wMask_9 = eccMask_1 & _wMask_T_9; // @[DCache.scala:56:82, :57:{87,108}] wire wMask_10 = eccMask_2 & _wMask_T_10; // @[DCache.scala:56:82, :57:{87,108}] wire wMask_11 = eccMask_3 & _wMask_T_11; // @[DCache.scala:56:82, :57:{87,108}] wire wMask_12 = eccMask_4 & _wMask_T_12; // @[DCache.scala:56:82, :57:{87,108}] wire wMask_13 = eccMask_5 & _wMask_T_13; // @[DCache.scala:56:82, :57:{87,108}] wire wMask_14 = eccMask_6 & _wMask_T_14; // @[DCache.scala:56:82, :57:{87,108}] wire wMask_15 = eccMask_7 & _wMask_T_15; // @[DCache.scala:56:82, :57:{87,108}] wire _wMask_T_16 = io_req_bits_way_en_0[2]; // @[DCache.scala:49:7, :57:108] wire _wMask_T_17 = io_req_bits_way_en_0[2]; // @[DCache.scala:49:7, :57:108] wire _wMask_T_18 = io_req_bits_way_en_0[2]; // @[DCache.scala:49:7, :57:108] wire _wMask_T_19 = io_req_bits_way_en_0[2]; // @[DCache.scala:49:7, :57:108] wire _wMask_T_20 = io_req_bits_way_en_0[2]; // @[DCache.scala:49:7, :57:108] wire _wMask_T_21 = io_req_bits_way_en_0[2]; // @[DCache.scala:49:7, :57:108] wire _wMask_T_22 = io_req_bits_way_en_0[2]; // @[DCache.scala:49:7, :57:108] wire _wMask_T_23 = io_req_bits_way_en_0[2]; // @[DCache.scala:49:7, :57:108] wire wMask_16 = eccMask_0 & _wMask_T_16; // @[DCache.scala:56:82, :57:{87,108}] wire wMask_17 = eccMask_1 & _wMask_T_17; // @[DCache.scala:56:82, :57:{87,108}] wire wMask_18 = eccMask_2 & _wMask_T_18; // @[DCache.scala:56:82, :57:{87,108}] wire wMask_19 = eccMask_3 & _wMask_T_19; // @[DCache.scala:56:82, :57:{87,108}] wire wMask_20 = eccMask_4 & _wMask_T_20; // @[DCache.scala:56:82, :57:{87,108}] wire wMask_21 = eccMask_5 & _wMask_T_21; // @[DCache.scala:56:82, :57:{87,108}] wire wMask_22 = eccMask_6 & _wMask_T_22; // @[DCache.scala:56:82, :57:{87,108}] wire wMask_23 = eccMask_7 & _wMask_T_23; // @[DCache.scala:56:82, :57:{87,108}] wire _wMask_T_24 = io_req_bits_way_en_0[3]; // @[DCache.scala:49:7, :57:108] wire _wMask_T_25 = io_req_bits_way_en_0[3]; // @[DCache.scala:49:7, :57:108] wire _wMask_T_26 = io_req_bits_way_en_0[3]; // @[DCache.scala:49:7, :57:108] wire _wMask_T_27 = io_req_bits_way_en_0[3]; // @[DCache.scala:49:7, :57:108] wire _wMask_T_28 = io_req_bits_way_en_0[3]; // @[DCache.scala:49:7, :57:108] wire _wMask_T_29 = io_req_bits_way_en_0[3]; // @[DCache.scala:49:7, :57:108] wire _wMask_T_30 = io_req_bits_way_en_0[3]; // @[DCache.scala:49:7, :57:108] wire _wMask_T_31 = io_req_bits_way_en_0[3]; // @[DCache.scala:49:7, :57:108] wire wMask_24 = eccMask_0 & _wMask_T_24; // @[DCache.scala:56:82, :57:{87,108}] wire wMask_25 = eccMask_1 & _wMask_T_25; // @[DCache.scala:56:82, :57:{87,108}] wire wMask_26 = eccMask_2 & _wMask_T_26; // @[DCache.scala:56:82, :57:{87,108}] wire wMask_27 = eccMask_3 & _wMask_T_27; // @[DCache.scala:56:82, :57:{87,108}] wire wMask_28 = eccMask_4 & _wMask_T_28; // @[DCache.scala:56:82, :57:{87,108}] wire wMask_29 = eccMask_5 & _wMask_T_29; // @[DCache.scala:56:82, :57:{87,108}] wire wMask_30 = eccMask_6 & _wMask_T_30; // @[DCache.scala:56:82, :57:{87,108}] wire wMask_31 = eccMask_7 & _wMask_T_31; // @[DCache.scala:56:82, :57:{87,108}] wire _wMask_T_32 = io_req_bits_way_en_0[4]; // @[DCache.scala:49:7, :57:108] wire _wMask_T_33 = io_req_bits_way_en_0[4]; // @[DCache.scala:49:7, :57:108] wire _wMask_T_34 = io_req_bits_way_en_0[4]; // @[DCache.scala:49:7, :57:108] wire _wMask_T_35 = io_req_bits_way_en_0[4]; // @[DCache.scala:49:7, :57:108] wire _wMask_T_36 = io_req_bits_way_en_0[4]; // @[DCache.scala:49:7, :57:108] wire _wMask_T_37 = io_req_bits_way_en_0[4]; // @[DCache.scala:49:7, :57:108] wire _wMask_T_38 = io_req_bits_way_en_0[4]; // @[DCache.scala:49:7, :57:108] wire _wMask_T_39 = io_req_bits_way_en_0[4]; // @[DCache.scala:49:7, :57:108] wire wMask_32 = eccMask_0 & _wMask_T_32; // @[DCache.scala:56:82, :57:{87,108}] wire wMask_33 = eccMask_1 & _wMask_T_33; // @[DCache.scala:56:82, :57:{87,108}] wire wMask_34 = eccMask_2 & _wMask_T_34; // @[DCache.scala:56:82, :57:{87,108}] wire wMask_35 = eccMask_3 & _wMask_T_35; // @[DCache.scala:56:82, :57:{87,108}] wire wMask_36 = eccMask_4 & _wMask_T_36; // @[DCache.scala:56:82, :57:{87,108}] wire wMask_37 = eccMask_5 & _wMask_T_37; // @[DCache.scala:56:82, :57:{87,108}] wire wMask_38 = eccMask_6 & _wMask_T_38; // @[DCache.scala:56:82, :57:{87,108}] wire wMask_39 = eccMask_7 & _wMask_T_39; // @[DCache.scala:56:82, :57:{87,108}] wire _wMask_T_40 = io_req_bits_way_en_0[5]; // @[DCache.scala:49:7, :57:108] wire _wMask_T_41 = io_req_bits_way_en_0[5]; // @[DCache.scala:49:7, :57:108] wire _wMask_T_42 = io_req_bits_way_en_0[5]; // @[DCache.scala:49:7, :57:108] wire _wMask_T_43 = io_req_bits_way_en_0[5]; // @[DCache.scala:49:7, :57:108] wire _wMask_T_44 = io_req_bits_way_en_0[5]; // @[DCache.scala:49:7, :57:108] wire _wMask_T_45 = io_req_bits_way_en_0[5]; // @[DCache.scala:49:7, :57:108] wire _wMask_T_46 = io_req_bits_way_en_0[5]; // @[DCache.scala:49:7, :57:108] wire _wMask_T_47 = io_req_bits_way_en_0[5]; // @[DCache.scala:49:7, :57:108] wire wMask_40 = eccMask_0 & _wMask_T_40; // @[DCache.scala:56:82, :57:{87,108}] wire wMask_41 = eccMask_1 & _wMask_T_41; // @[DCache.scala:56:82, :57:{87,108}] wire wMask_42 = eccMask_2 & _wMask_T_42; // @[DCache.scala:56:82, :57:{87,108}] wire wMask_43 = eccMask_3 & _wMask_T_43; // @[DCache.scala:56:82, :57:{87,108}] wire wMask_44 = eccMask_4 & _wMask_T_44; // @[DCache.scala:56:82, :57:{87,108}] wire wMask_45 = eccMask_5 & _wMask_T_45; // @[DCache.scala:56:82, :57:{87,108}] wire wMask_46 = eccMask_6 & _wMask_T_46; // @[DCache.scala:56:82, :57:{87,108}] wire wMask_47 = eccMask_7 & _wMask_T_47; // @[DCache.scala:56:82, :57:{87,108}] wire _wMask_T_48 = io_req_bits_way_en_0[6]; // @[DCache.scala:49:7, :57:108] wire _wMask_T_49 = io_req_bits_way_en_0[6]; // @[DCache.scala:49:7, :57:108] wire _wMask_T_50 = io_req_bits_way_en_0[6]; // @[DCache.scala:49:7, :57:108] wire _wMask_T_51 = io_req_bits_way_en_0[6]; // @[DCache.scala:49:7, :57:108] wire _wMask_T_52 = io_req_bits_way_en_0[6]; // @[DCache.scala:49:7, :57:108] wire _wMask_T_53 = io_req_bits_way_en_0[6]; // @[DCache.scala:49:7, :57:108] wire _wMask_T_54 = io_req_bits_way_en_0[6]; // @[DCache.scala:49:7, :57:108] wire _wMask_T_55 = io_req_bits_way_en_0[6]; // @[DCache.scala:49:7, :57:108] wire wMask_48 = eccMask_0 & _wMask_T_48; // @[DCache.scala:56:82, :57:{87,108}] wire wMask_49 = eccMask_1 & _wMask_T_49; // @[DCache.scala:56:82, :57:{87,108}] wire wMask_50 = eccMask_2 & _wMask_T_50; // @[DCache.scala:56:82, :57:{87,108}] wire wMask_51 = eccMask_3 & _wMask_T_51; // @[DCache.scala:56:82, :57:{87,108}] wire wMask_52 = eccMask_4 & _wMask_T_52; // @[DCache.scala:56:82, :57:{87,108}] wire wMask_53 = eccMask_5 & _wMask_T_53; // @[DCache.scala:56:82, :57:{87,108}] wire wMask_54 = eccMask_6 & _wMask_T_54; // @[DCache.scala:56:82, :57:{87,108}] wire wMask_55 = eccMask_7 & _wMask_T_55; // @[DCache.scala:56:82, :57:{87,108}] wire _wMask_T_56 = io_req_bits_way_en_0[7]; // @[DCache.scala:49:7, :57:108] wire _wMask_T_57 = io_req_bits_way_en_0[7]; // @[DCache.scala:49:7, :57:108] wire _wMask_T_58 = io_req_bits_way_en_0[7]; // @[DCache.scala:49:7, :57:108] wire _wMask_T_59 = io_req_bits_way_en_0[7]; // @[DCache.scala:49:7, :57:108] wire _wMask_T_60 = io_req_bits_way_en_0[7]; // @[DCache.scala:49:7, :57:108] wire _wMask_T_61 = io_req_bits_way_en_0[7]; // @[DCache.scala:49:7, :57:108] wire _wMask_T_62 = io_req_bits_way_en_0[7]; // @[DCache.scala:49:7, :57:108] wire _wMask_T_63 = io_req_bits_way_en_0[7]; // @[DCache.scala:49:7, :57:108] wire wMask_56 = eccMask_0 & _wMask_T_56; // @[DCache.scala:56:82, :57:{87,108}] wire wMask_57 = eccMask_1 & _wMask_T_57; // @[DCache.scala:56:82, :57:{87,108}] wire wMask_58 = eccMask_2 & _wMask_T_58; // @[DCache.scala:56:82, :57:{87,108}] wire wMask_59 = eccMask_3 & _wMask_T_59; // @[DCache.scala:56:82, :57:{87,108}] wire wMask_60 = eccMask_4 & _wMask_T_60; // @[DCache.scala:56:82, :57:{87,108}] wire wMask_61 = eccMask_5 & _wMask_T_61; // @[DCache.scala:56:82, :57:{87,108}] wire wMask_62 = eccMask_6 & _wMask_T_62; // @[DCache.scala:56:82, :57:{87,108}] wire wMask_63 = eccMask_7 & _wMask_T_63; // @[DCache.scala:56:82, :57:{87,108}] wire [8:0] addr = io_req_bits_addr_0[11:3]; // @[DCache.scala:49:7, :59:31] wire [8:0] _rdata_data_WIRE = addr; // @[DCache.scala:59:31, :77:26] wire _rdata_T; // @[DCache.scala:72:17] wire _rdata_data_T_1; // @[DCache.scala:77:39] wire [7:0] _rdata_WIRE_0; // @[DCache.scala:75:32] wire [7:0] _rdata_WIRE_1; // @[DCache.scala:75:32] wire [7:0] _rdata_WIRE_2; // @[DCache.scala:75:32] wire [7:0] _rdata_WIRE_3; // @[DCache.scala:75:32] wire [7:0] _rdata_WIRE_4; // @[DCache.scala:75:32] wire [7:0] _rdata_WIRE_5; // @[DCache.scala:75:32] wire [7:0] _rdata_WIRE_6; // @[DCache.scala:75:32] wire [7:0] _rdata_WIRE_7; // @[DCache.scala:75:32] wire [7:0] _rdata_WIRE_8; // @[DCache.scala:75:32] wire [7:0] _rdata_WIRE_9; // @[DCache.scala:75:32] wire [7:0] _rdata_WIRE_10; // @[DCache.scala:75:32] wire [7:0] _rdata_WIRE_11; // @[DCache.scala:75:32] wire [7:0] _rdata_WIRE_12; // @[DCache.scala:75:32] wire [7:0] _rdata_WIRE_13; // @[DCache.scala:75:32] wire [7:0] _rdata_WIRE_14; // @[DCache.scala:75:32] wire [7:0] _rdata_WIRE_15; // @[DCache.scala:75:32] wire [7:0] _rdata_WIRE_16; // @[DCache.scala:75:32] wire [7:0] _rdata_WIRE_17; // @[DCache.scala:75:32] wire [7:0] _rdata_WIRE_18; // @[DCache.scala:75:32] wire [7:0] _rdata_WIRE_19; // @[DCache.scala:75:32] wire [7:0] _rdata_WIRE_20; // @[DCache.scala:75:32] wire [7:0] _rdata_WIRE_21; // @[DCache.scala:75:32] wire [7:0] _rdata_WIRE_22; // @[DCache.scala:75:32] wire [7:0] _rdata_WIRE_23; // @[DCache.scala:75:32] wire [7:0] _rdata_WIRE_24; // @[DCache.scala:75:32] wire [7:0] _rdata_WIRE_25; // @[DCache.scala:75:32] wire [7:0] _rdata_WIRE_26; // @[DCache.scala:75:32] wire [7:0] _rdata_WIRE_27; // @[DCache.scala:75:32] wire [7:0] _rdata_WIRE_28; // @[DCache.scala:75:32] wire [7:0] _rdata_WIRE_29; // @[DCache.scala:75:32] wire [7:0] _rdata_WIRE_30; // @[DCache.scala:75:32] wire [7:0] _rdata_WIRE_31; // @[DCache.scala:75:32] wire [7:0] _rdata_WIRE_32; // @[DCache.scala:75:32] wire [7:0] _rdata_WIRE_33; // @[DCache.scala:75:32] wire [7:0] _rdata_WIRE_34; // @[DCache.scala:75:32] wire [7:0] _rdata_WIRE_35; // @[DCache.scala:75:32] wire [7:0] _rdata_WIRE_36; // @[DCache.scala:75:32] wire [7:0] _rdata_WIRE_37; // @[DCache.scala:75:32] wire [7:0] _rdata_WIRE_38; // @[DCache.scala:75:32] wire [7:0] _rdata_WIRE_39; // @[DCache.scala:75:32] wire [7:0] _rdata_WIRE_40; // @[DCache.scala:75:32] wire [7:0] _rdata_WIRE_41; // @[DCache.scala:75:32] wire [7:0] _rdata_WIRE_42; // @[DCache.scala:75:32] wire [7:0] _rdata_WIRE_43; // @[DCache.scala:75:32] wire [7:0] _rdata_WIRE_44; // @[DCache.scala:75:32] wire [7:0] _rdata_WIRE_45; // @[DCache.scala:75:32] wire [7:0] _rdata_WIRE_46; // @[DCache.scala:75:32] wire [7:0] _rdata_WIRE_47; // @[DCache.scala:75:32] wire [7:0] _rdata_WIRE_48; // @[DCache.scala:75:32] wire [7:0] _rdata_WIRE_49; // @[DCache.scala:75:32] wire [7:0] _rdata_WIRE_50; // @[DCache.scala:75:32] wire [7:0] _rdata_WIRE_51; // @[DCache.scala:75:32] wire [7:0] _rdata_WIRE_52; // @[DCache.scala:75:32] wire [7:0] _rdata_WIRE_53; // @[DCache.scala:75:32] wire [7:0] _rdata_WIRE_54; // @[DCache.scala:75:32] wire [7:0] _rdata_WIRE_55; // @[DCache.scala:75:32] wire [7:0] _rdata_WIRE_56; // @[DCache.scala:75:32] wire [7:0] _rdata_WIRE_57; // @[DCache.scala:75:32] wire [7:0] _rdata_WIRE_58; // @[DCache.scala:75:32] wire [7:0] _rdata_WIRE_59; // @[DCache.scala:75:32] wire [7:0] _rdata_WIRE_60; // @[DCache.scala:75:32] wire [7:0] _rdata_WIRE_61; // @[DCache.scala:75:32] wire [7:0] _rdata_WIRE_62; // @[DCache.scala:75:32] wire [7:0] _rdata_WIRE_63; // @[DCache.scala:75:32] assign _rdata_T = rdata_valid & io_req_bits_write_0; // @[DCache.scala:49:7, :71:30, :72:17] wire [7:0] rdata_wData_0 = wWords_0[7:0]; // @[package.scala:211:50] assign _rdata_WIRE_0 = rdata_wData_0; // @[package.scala:211:50] assign _rdata_WIRE_8 = rdata_wData_0; // @[package.scala:211:50] assign _rdata_WIRE_16 = rdata_wData_0; // @[package.scala:211:50] assign _rdata_WIRE_24 = rdata_wData_0; // @[package.scala:211:50] assign _rdata_WIRE_32 = rdata_wData_0; // @[package.scala:211:50] assign _rdata_WIRE_40 = rdata_wData_0; // @[package.scala:211:50] assign _rdata_WIRE_48 = rdata_wData_0; // @[package.scala:211:50] assign _rdata_WIRE_56 = rdata_wData_0; // @[package.scala:211:50] wire [7:0] rdata_wData_1 = wWords_0[15:8]; // @[package.scala:211:50] assign _rdata_WIRE_1 = rdata_wData_1; // @[package.scala:211:50] assign _rdata_WIRE_9 = rdata_wData_1; // @[package.scala:211:50] assign _rdata_WIRE_17 = rdata_wData_1; // @[package.scala:211:50] assign _rdata_WIRE_25 = rdata_wData_1; // @[package.scala:211:50] assign _rdata_WIRE_33 = rdata_wData_1; // @[package.scala:211:50] assign _rdata_WIRE_41 = rdata_wData_1; // @[package.scala:211:50] assign _rdata_WIRE_49 = rdata_wData_1; // @[package.scala:211:50] assign _rdata_WIRE_57 = rdata_wData_1; // @[package.scala:211:50] wire [7:0] rdata_wData_2 = wWords_0[23:16]; // @[package.scala:211:50] assign _rdata_WIRE_2 = rdata_wData_2; // @[package.scala:211:50] assign _rdata_WIRE_10 = rdata_wData_2; // @[package.scala:211:50] assign _rdata_WIRE_18 = rdata_wData_2; // @[package.scala:211:50] assign _rdata_WIRE_26 = rdata_wData_2; // @[package.scala:211:50] assign _rdata_WIRE_34 = rdata_wData_2; // @[package.scala:211:50] assign _rdata_WIRE_42 = rdata_wData_2; // @[package.scala:211:50] assign _rdata_WIRE_50 = rdata_wData_2; // @[package.scala:211:50] assign _rdata_WIRE_58 = rdata_wData_2; // @[package.scala:211:50] wire [7:0] rdata_wData_3 = wWords_0[31:24]; // @[package.scala:211:50] assign _rdata_WIRE_3 = rdata_wData_3; // @[package.scala:211:50] assign _rdata_WIRE_11 = rdata_wData_3; // @[package.scala:211:50] assign _rdata_WIRE_19 = rdata_wData_3; // @[package.scala:211:50] assign _rdata_WIRE_27 = rdata_wData_3; // @[package.scala:211:50] assign _rdata_WIRE_35 = rdata_wData_3; // @[package.scala:211:50] assign _rdata_WIRE_43 = rdata_wData_3; // @[package.scala:211:50] assign _rdata_WIRE_51 = rdata_wData_3; // @[package.scala:211:50] assign _rdata_WIRE_59 = rdata_wData_3; // @[package.scala:211:50] wire [7:0] rdata_wData_4 = wWords_0[39:32]; // @[package.scala:211:50] assign _rdata_WIRE_4 = rdata_wData_4; // @[package.scala:211:50] assign _rdata_WIRE_12 = rdata_wData_4; // @[package.scala:211:50] assign _rdata_WIRE_20 = rdata_wData_4; // @[package.scala:211:50] assign _rdata_WIRE_28 = rdata_wData_4; // @[package.scala:211:50] assign _rdata_WIRE_36 = rdata_wData_4; // @[package.scala:211:50] assign _rdata_WIRE_44 = rdata_wData_4; // @[package.scala:211:50] assign _rdata_WIRE_52 = rdata_wData_4; // @[package.scala:211:50] assign _rdata_WIRE_60 = rdata_wData_4; // @[package.scala:211:50] wire [7:0] rdata_wData_5 = wWords_0[47:40]; // @[package.scala:211:50] assign _rdata_WIRE_5 = rdata_wData_5; // @[package.scala:211:50] assign _rdata_WIRE_13 = rdata_wData_5; // @[package.scala:211:50] assign _rdata_WIRE_21 = rdata_wData_5; // @[package.scala:211:50] assign _rdata_WIRE_29 = rdata_wData_5; // @[package.scala:211:50] assign _rdata_WIRE_37 = rdata_wData_5; // @[package.scala:211:50] assign _rdata_WIRE_45 = rdata_wData_5; // @[package.scala:211:50] assign _rdata_WIRE_53 = rdata_wData_5; // @[package.scala:211:50] assign _rdata_WIRE_61 = rdata_wData_5; // @[package.scala:211:50] wire [7:0] rdata_wData_6 = wWords_0[55:48]; // @[package.scala:211:50] assign _rdata_WIRE_6 = rdata_wData_6; // @[package.scala:211:50] assign _rdata_WIRE_14 = rdata_wData_6; // @[package.scala:211:50] assign _rdata_WIRE_22 = rdata_wData_6; // @[package.scala:211:50] assign _rdata_WIRE_30 = rdata_wData_6; // @[package.scala:211:50] assign _rdata_WIRE_38 = rdata_wData_6; // @[package.scala:211:50] assign _rdata_WIRE_46 = rdata_wData_6; // @[package.scala:211:50] assign _rdata_WIRE_54 = rdata_wData_6; // @[package.scala:211:50] assign _rdata_WIRE_62 = rdata_wData_6; // @[package.scala:211:50] wire [7:0] rdata_wData_7 = wWords_0[63:56]; // @[package.scala:211:50] assign _rdata_WIRE_7 = rdata_wData_7; // @[package.scala:211:50] assign _rdata_WIRE_15 = rdata_wData_7; // @[package.scala:211:50] assign _rdata_WIRE_23 = rdata_wData_7; // @[package.scala:211:50] assign _rdata_WIRE_31 = rdata_wData_7; // @[package.scala:211:50] assign _rdata_WIRE_39 = rdata_wData_7; // @[package.scala:211:50] assign _rdata_WIRE_47 = rdata_wData_7; // @[package.scala:211:50] assign _rdata_WIRE_55 = rdata_wData_7; // @[package.scala:211:50] assign _rdata_WIRE_63 = rdata_wData_7; // @[package.scala:211:50] wire _rdata_data_T = ~io_req_bits_write_0; // @[DCache.scala:49:7, :77:42] assign _rdata_data_T_1 = rdata_valid & _rdata_data_T; // @[DCache.scala:71:30, :77:{39,42}] wire [15:0] rdata_lo_lo = _rockettile_dcache_data_arrays_0_RW0_rdata[15:0]; // @[package.scala:45:27] wire [15:0] rdata_lo_hi = _rockettile_dcache_data_arrays_0_RW0_rdata[31:16]; // @[package.scala:45:27] wire [31:0] rdata_lo = {rdata_lo_hi, rdata_lo_lo}; // @[package.scala:45:27] wire [15:0] rdata_hi_lo = _rockettile_dcache_data_arrays_0_RW0_rdata[47:32]; // @[package.scala:45:27] wire [15:0] rdata_hi_hi = _rockettile_dcache_data_arrays_0_RW0_rdata[63:48]; // @[package.scala:45:27] wire [31:0] rdata_hi = {rdata_hi_hi, rdata_hi_lo}; // @[package.scala:45:27] assign rdata_0_0 = {rdata_hi, rdata_lo}; // @[package.scala:45:27] assign io_resp_0_0 = rdata_0_0; // @[package.scala:45:27] wire [15:0] rdata_lo_lo_1 = _rockettile_dcache_data_arrays_0_RW0_rdata[79:64]; // @[package.scala:45:27] wire [15:0] rdata_lo_hi_1 = _rockettile_dcache_data_arrays_0_RW0_rdata[95:80]; // @[package.scala:45:27] wire [31:0] rdata_lo_1 = {rdata_lo_hi_1, rdata_lo_lo_1}; // @[package.scala:45:27] wire [15:0] rdata_hi_lo_1 = _rockettile_dcache_data_arrays_0_RW0_rdata[111:96]; // @[package.scala:45:27] wire [15:0] rdata_hi_hi_1 = _rockettile_dcache_data_arrays_0_RW0_rdata[127:112]; // @[package.scala:45:27] wire [31:0] rdata_hi_1 = {rdata_hi_hi_1, rdata_hi_lo_1}; // @[package.scala:45:27] assign rdata_0_1 = {rdata_hi_1, rdata_lo_1}; // @[package.scala:45:27] assign io_resp_1_0 = rdata_0_1; // @[package.scala:45:27] wire [15:0] rdata_lo_lo_2 = _rockettile_dcache_data_arrays_0_RW0_rdata[143:128]; // @[package.scala:45:27] wire [15:0] rdata_lo_hi_2 = _rockettile_dcache_data_arrays_0_RW0_rdata[159:144]; // @[package.scala:45:27] wire [31:0] rdata_lo_2 = {rdata_lo_hi_2, rdata_lo_lo_2}; // @[package.scala:45:27] wire [15:0] rdata_hi_lo_2 = _rockettile_dcache_data_arrays_0_RW0_rdata[175:160]; // @[package.scala:45:27] wire [15:0] rdata_hi_hi_2 = _rockettile_dcache_data_arrays_0_RW0_rdata[191:176]; // @[package.scala:45:27] wire [31:0] rdata_hi_2 = {rdata_hi_hi_2, rdata_hi_lo_2}; // @[package.scala:45:27] assign rdata_0_2 = {rdata_hi_2, rdata_lo_2}; // @[package.scala:45:27] assign io_resp_2_0 = rdata_0_2; // @[package.scala:45:27] wire [15:0] rdata_lo_lo_3 = _rockettile_dcache_data_arrays_0_RW0_rdata[207:192]; // @[package.scala:45:27] wire [15:0] rdata_lo_hi_3 = _rockettile_dcache_data_arrays_0_RW0_rdata[223:208]; // @[package.scala:45:27] wire [31:0] rdata_lo_3 = {rdata_lo_hi_3, rdata_lo_lo_3}; // @[package.scala:45:27] wire [15:0] rdata_hi_lo_3 = _rockettile_dcache_data_arrays_0_RW0_rdata[239:224]; // @[package.scala:45:27] wire [15:0] rdata_hi_hi_3 = _rockettile_dcache_data_arrays_0_RW0_rdata[255:240]; // @[package.scala:45:27] wire [31:0] rdata_hi_3 = {rdata_hi_hi_3, rdata_hi_lo_3}; // @[package.scala:45:27] assign rdata_0_3 = {rdata_hi_3, rdata_lo_3}; // @[package.scala:45:27] assign io_resp_3_0 = rdata_0_3; // @[package.scala:45:27] wire [15:0] rdata_lo_lo_4 = _rockettile_dcache_data_arrays_0_RW0_rdata[271:256]; // @[package.scala:45:27] wire [15:0] rdata_lo_hi_4 = _rockettile_dcache_data_arrays_0_RW0_rdata[287:272]; // @[package.scala:45:27] wire [31:0] rdata_lo_4 = {rdata_lo_hi_4, rdata_lo_lo_4}; // @[package.scala:45:27] wire [15:0] rdata_hi_lo_4 = _rockettile_dcache_data_arrays_0_RW0_rdata[303:288]; // @[package.scala:45:27] wire [15:0] rdata_hi_hi_4 = _rockettile_dcache_data_arrays_0_RW0_rdata[319:304]; // @[package.scala:45:27] wire [31:0] rdata_hi_4 = {rdata_hi_hi_4, rdata_hi_lo_4}; // @[package.scala:45:27] assign rdata_0_4 = {rdata_hi_4, rdata_lo_4}; // @[package.scala:45:27] assign io_resp_4_0 = rdata_0_4; // @[package.scala:45:27] wire [15:0] rdata_lo_lo_5 = _rockettile_dcache_data_arrays_0_RW0_rdata[335:320]; // @[package.scala:45:27] wire [15:0] rdata_lo_hi_5 = _rockettile_dcache_data_arrays_0_RW0_rdata[351:336]; // @[package.scala:45:27] wire [31:0] rdata_lo_5 = {rdata_lo_hi_5, rdata_lo_lo_5}; // @[package.scala:45:27] wire [15:0] rdata_hi_lo_5 = _rockettile_dcache_data_arrays_0_RW0_rdata[367:352]; // @[package.scala:45:27] wire [15:0] rdata_hi_hi_5 = _rockettile_dcache_data_arrays_0_RW0_rdata[383:368]; // @[package.scala:45:27] wire [31:0] rdata_hi_5 = {rdata_hi_hi_5, rdata_hi_lo_5}; // @[package.scala:45:27] assign rdata_0_5 = {rdata_hi_5, rdata_lo_5}; // @[package.scala:45:27] assign io_resp_5_0 = rdata_0_5; // @[package.scala:45:27] wire [15:0] rdata_lo_lo_6 = _rockettile_dcache_data_arrays_0_RW0_rdata[399:384]; // @[package.scala:45:27] wire [15:0] rdata_lo_hi_6 = _rockettile_dcache_data_arrays_0_RW0_rdata[415:400]; // @[package.scala:45:27] wire [31:0] rdata_lo_6 = {rdata_lo_hi_6, rdata_lo_lo_6}; // @[package.scala:45:27] wire [15:0] rdata_hi_lo_6 = _rockettile_dcache_data_arrays_0_RW0_rdata[431:416]; // @[package.scala:45:27] wire [15:0] rdata_hi_hi_6 = _rockettile_dcache_data_arrays_0_RW0_rdata[447:432]; // @[package.scala:45:27] wire [31:0] rdata_hi_6 = {rdata_hi_hi_6, rdata_hi_lo_6}; // @[package.scala:45:27] assign rdata_0_6 = {rdata_hi_6, rdata_lo_6}; // @[package.scala:45:27] assign io_resp_6_0 = rdata_0_6; // @[package.scala:45:27] wire [15:0] rdata_lo_lo_7 = _rockettile_dcache_data_arrays_0_RW0_rdata[463:448]; // @[package.scala:45:27] wire [15:0] rdata_lo_hi_7 = _rockettile_dcache_data_arrays_0_RW0_rdata[479:464]; // @[package.scala:45:27] wire [31:0] rdata_lo_7 = {rdata_lo_hi_7, rdata_lo_lo_7}; // @[package.scala:45:27] wire [15:0] rdata_hi_lo_7 = _rockettile_dcache_data_arrays_0_RW0_rdata[495:480]; // @[package.scala:45:27] wire [15:0] rdata_hi_hi_7 = _rockettile_dcache_data_arrays_0_RW0_rdata[511:496]; // @[package.scala:45:27] wire [31:0] rdata_hi_7 = {rdata_hi_hi_7, rdata_hi_lo_7}; // @[package.scala:45:27] assign rdata_0_7 = {rdata_hi_7, rdata_lo_7}; // @[package.scala:45:27] assign io_resp_7_0 = rdata_0_7; // @[package.scala:45:27] rockettile_dcache_data_arrays_0 rockettile_dcache_data_arrays_0 ( // @[DescribedSRAM.scala:17:26] .RW0_addr (_rdata_T ? addr : _rdata_data_WIRE), // @[DescribedSRAM.scala:17:26] .RW0_en (_rdata_data_T_1 \| _rdata_T), // @[DescribedSRAM.scala:17:26] .RW0_clk (clock), .RW0_wmode (io_req_bits_write_0), // @[DCache.scala:49:7] .RW0_wdata ({_rdata_WIRE_63, _rdata_WIRE_62, _rdata_WIRE_61, _rdata_WIRE_60, _rdata_WIRE_59, _rdata_WIRE_58, _rdata_WIRE_57, _rdata_WIRE_56, _rdata_WIRE_55, _rdata_WIRE_54, _rdata_WIRE_53, _rdata_WIRE_52, _rdata_WIRE_51, _rdata_WIRE_50, _rdata_WIRE_49, _rdata_WIRE_48, _rdata_WIRE_47, _rdata_WIRE_46, _rdata_WIRE_45, _rdata_WIRE_44, _rdata_WIRE_43, _rdata_WIRE_42, _rdata_WIRE_41, _rdata_WIRE_40, _rdata_WIRE_39, _rdata_WIRE_38, _rdata_WIRE_37, _rdata_WIRE_36, _rdata_WIRE_35, _rdata_WIRE_34, _rdata_WIRE_33, _rdata_WIRE_32, _rdata_WIRE_31, _rdata_WIRE_30, _rdata_WIRE_29, _rdata_WIRE_28, _rdata_WIRE_27, _rdata_WIRE_26, _rdata_WIRE_25, _rdata_WIRE_24, _rdata_WIRE_23, _rdata_WIRE_22, _rdata_WIRE_21, _rdata_WIRE_20, _rdata_WIRE_19, _rdata_WIRE_18, _rdata_WIRE_17, _rdata_WIRE_16, _rdata_WIRE_15, _rdata_WIRE_14, _rdata_WIRE_13, _rdata_WIRE_12, _rdata_WIRE_11, _rdata_WIRE_10, _rdata_WIRE_9, _rdata_WIRE_8, _rdata_WIRE_7, _rdata_WIRE_6, _rdata_WIRE_5, _rdata_WIRE_4, _rdata_WIRE_3, _rdata_WIRE_2, _rdata_WIRE_1, _rdata_WIRE_0}), // @[DescribedSRAM.scala:17:26] .RW0_rdata (_rockettile_dcache_data_arrays_0_RW0_rdata), .RW0_wmask ({wMask_63, wMask_62, wMask_61, wMask_60, wMask_59, wMask_58, wMask_57, wMask_56, wMask_55, wMask_54, wMask_53, wMask_52, wMask_51, wMask_50, wMask_49, wMask_48, wMask_47, wMask_46, wMask_45, wMask_44, wMask_43, wMask_42, wMask_41, wMask_40, wMask_39, wMask_38, wMask_37, wMask_36, wMask_35, wMask_34, wMask_33, wMask_32, wMask_31, wMask_30, wMask_29, wMask_28, wMask_27, wMask_26, wMask_25, wMask_24, wMask_23, wMask_22, wMask_21, wMask_20, wMask_19, wMask_18, wMask_17, wMask_16, wMask_15, wMask_14, wMask_13, wMask_12, wMask_11, wMask_10, wMask_9, wMask_8, wMask_7, wMask_6, wMask_5, wMask_4, wMask_3, wMask_2, wMask_1, wMask_0}) // @[DescribedSRAM.scala:17:26] ); // @[DescribedSRAM.scala:17:26] assign io_resp_0 = io_resp_0_0; // @[DCache.scala:49:7] assign io_resp_1 = io_resp_1_0; // @[DCache.scala:49:7] assign io_resp_2 = io_resp_2_0; // @[DCache.scala:49:7] assign io_resp_3 = io_resp_3_0; // @[DCache.scala:49:7] assign io_resp_4 = io_resp_4_0; // @[DCache.scala:49:7] assign io_resp_5 = io_resp_5_0; // @[DCache.scala:49:7] assign io_resp_6 = io_resp_6_0; // @[DCache.scala:49:7] assign io_resp_7 = io_resp_7_0; // @[DCache.scala:49:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File FPU.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.tile import chisel3._ import chisel3.util._ import chisel3.{DontCare, WireInit, withClock, withReset} import chisel3.experimental.SourceInfo import chisel3.experimental.dataview._ import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.rocket._ import freechips.rocketchip.rocket.Instructions._ import freechips.rocketchip.util._ import freechips.rocketchip.util.property case class FPUParams( minFLen: Int = 32, fLen: Int = 64, divSqrt: Boolean = true, sfmaLatency: Int = 3, dfmaLatency: Int = 4, fpmuLatency: Int = 2, ifpuLatency: Int = 2 ) object FPConstants { val RM_SZ = 3 val FLAGS_SZ = 5 } trait HasFPUCtrlSigs { val ldst = Bool() val wen = Bool() val ren1 = Bool() val ren2 = Bool() val ren3 = Bool() val swap12 = Bool() val swap23 = Bool() val typeTagIn = UInt(2.W) val typeTagOut = UInt(2.W) val fromint = Bool() val toint = Bool() val fastpipe = Bool() val fma = Bool() val div = Bool() val sqrt = Bool() val wflags = Bool() val vec = Bool() } class FPUCtrlSigs extends Bundle with HasFPUCtrlSigs class FPUDecoder(implicit p: Parameters) extends FPUModule()(p) { val io = IO(new Bundle { val inst = Input(Bits(32.W)) val sigs = Output(new FPUCtrlSigs()) }) private val X2 = BitPat.dontCare(2) val default = List(X,X,X,X,X,X,X,X2,X2,X,X,X,X,X,X,X,N) val h: Array[(BitPat, List[BitPat])] = Array(FLH -> List(Y,Y,N,N,N,X,X,X2,X2,N,N,N,N,N,N,N,N), FSH -> List(Y,N,N,Y,N,Y,X, I, H,N,Y,N,N,N,N,N,N), FMV_H_X -> List(N,Y,N,N,N,X,X, H, I,Y,N,N,N,N,N,N,N), FCVT_H_W -> List(N,Y,N,N,N,X,X, H, H,Y,N,N,N,N,N,Y,N), FCVT_H_WU-> List(N,Y,N,N,N,X,X, H, H,Y,N,N,N,N,N,Y,N), FCVT_H_L -> List(N,Y,N,N,N,X,X, H, H,Y,N,N,N,N,N,Y,N), FCVT_H_LU-> List(N,Y,N,N,N,X,X, H, H,Y,N,N,N,N,N,Y,N), FMV_X_H -> List(N,N,Y,N,N,N,X, I, H,N,Y,N,N,N,N,N,N), FCLASS_H -> List(N,N,Y,N,N,N,X, H, H,N,Y,N,N,N,N,N,N), FCVT_W_H -> List(N,N,Y,N,N,N,X, H,X2,N,Y,N,N,N,N,Y,N), FCVT_WU_H-> List(N,N,Y,N,N,N,X, H,X2,N,Y,N,N,N,N,Y,N), FCVT_L_H -> List(N,N,Y,N,N,N,X, H,X2,N,Y,N,N,N,N,Y,N), FCVT_LU_H-> List(N,N,Y,N,N,N,X, H,X2,N,Y,N,N,N,N,Y,N), FCVT_S_H -> List(N,Y,Y,N,N,N,X, H, S,N,N,Y,N,N,N,Y,N), FCVT_H_S -> List(N,Y,Y,N,N,N,X, S, H,N,N,Y,N,N,N,Y,N), FEQ_H -> List(N,N,Y,Y,N,N,N, H, H,N,Y,N,N,N,N,Y,N), FLT_H -> List(N,N,Y,Y,N,N,N, H, H,N,Y,N,N,N,N,Y,N), FLE_H -> List(N,N,Y,Y,N,N,N, H, H,N,Y,N,N,N,N,Y,N), FSGNJ_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,Y,N,N,N,N,N), FSGNJN_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,Y,N,N,N,N,N), FSGNJX_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,Y,N,N,N,N,N), FMIN_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,Y,N,N,N,Y,N), FMAX_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,Y,N,N,N,Y,N), FADD_H -> List(N,Y,Y,Y,N,N,Y, H, H,N,N,N,Y,N,N,Y,N), FSUB_H -> List(N,Y,Y,Y,N,N,Y, H, H,N,N,N,Y,N,N,Y,N), FMUL_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,N,Y,N,N,Y,N), FMADD_H -> List(N,Y,Y,Y,Y,N,N, H, H,N,N,N,Y,N,N,Y,N), FMSUB_H -> List(N,Y,Y,Y,Y,N,N, H, H,N,N,N,Y,N,N,Y,N), FNMADD_H -> List(N,Y,Y,Y,Y,N,N, H, H,N,N,N,Y,N,N,Y,N), FNMSUB_H -> List(N,Y,Y,Y,Y,N,N, H, H,N,N,N,Y,N,N,Y,N), FDIV_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,N,N,Y,N,Y,N), FSQRT_H -> List(N,Y,Y,N,N,N,X, H, H,N,N,N,N,N,Y,Y,N)) val f: Array[(BitPat, List[BitPat])] = Array(FLW -> List(Y,Y,N,N,N,X,X,X2,X2,N,N,N,N,N,N,N,N), FSW -> List(Y,N,N,Y,N,Y,X, I, S,N,Y,N,N,N,N,N,N), FMV_W_X -> List(N,Y,N,N,N,X,X, S, I,Y,N,N,N,N,N,N,N), FCVT_S_W -> List(N,Y,N,N,N,X,X, S, S,Y,N,N,N,N,N,Y,N), FCVT_S_WU-> List(N,Y,N,N,N,X,X, S, S,Y,N,N,N,N,N,Y,N), FCVT_S_L -> List(N,Y,N,N,N,X,X, S, S,Y,N,N,N,N,N,Y,N), FCVT_S_LU-> List(N,Y,N,N,N,X,X, S, S,Y,N,N,N,N,N,Y,N), FMV_X_W -> List(N,N,Y,N,N,N,X, I, S,N,Y,N,N,N,N,N,N), FCLASS_S -> List(N,N,Y,N,N,N,X, S, S,N,Y,N,N,N,N,N,N), FCVT_W_S -> List(N,N,Y,N,N,N,X, S,X2,N,Y,N,N,N,N,Y,N), FCVT_WU_S-> List(N,N,Y,N,N,N,X, S,X2,N,Y,N,N,N,N,Y,N), FCVT_L_S -> List(N,N,Y,N,N,N,X, S,X2,N,Y,N,N,N,N,Y,N), FCVT_LU_S-> List(N,N,Y,N,N,N,X, S,X2,N,Y,N,N,N,N,Y,N), FEQ_S -> List(N,N,Y,Y,N,N,N, S, S,N,Y,N,N,N,N,Y,N), FLT_S -> List(N,N,Y,Y,N,N,N, S, S,N,Y,N,N,N,N,Y,N), FLE_S -> List(N,N,Y,Y,N,N,N, S, S,N,Y,N,N,N,N,Y,N), FSGNJ_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,Y,N,N,N,N,N), FSGNJN_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,Y,N,N,N,N,N), FSGNJX_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,Y,N,N,N,N,N), FMIN_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,Y,N,N,N,Y,N), FMAX_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,Y,N,N,N,Y,N), FADD_S -> List(N,Y,Y,Y,N,N,Y, S, S,N,N,N,Y,N,N,Y,N), FSUB_S -> List(N,Y,Y,Y,N,N,Y, S, S,N,N,N,Y,N,N,Y,N), FMUL_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,N,Y,N,N,Y,N), FMADD_S -> List(N,Y,Y,Y,Y,N,N, S, S,N,N,N,Y,N,N,Y,N), FMSUB_S -> List(N,Y,Y,Y,Y,N,N, S, S,N,N,N,Y,N,N,Y,N), FNMADD_S -> List(N,Y,Y,Y,Y,N,N, S, S,N,N,N,Y,N,N,Y,N), FNMSUB_S -> List(N,Y,Y,Y,Y,N,N, S, S,N,N,N,Y,N,N,Y,N), FDIV_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,N,N,Y,N,Y,N), FSQRT_S -> List(N,Y,Y,N,N,N,X, S, S,N,N,N,N,N,Y,Y,N)) val d: Array[(BitPat, List[BitPat])] = Array(FLD -> List(Y,Y,N,N,N,X,X,X2,X2,N,N,N,N,N,N,N,N), FSD -> List(Y,N,N,Y,N,Y,X, I, D,N,Y,N,N,N,N,N,N), FMV_D_X -> List(N,Y,N,N,N,X,X, D, I,Y,N,N,N,N,N,N,N), FCVT_D_W -> List(N,Y,N,N,N,X,X, D, D,Y,N,N,N,N,N,Y,N), FCVT_D_WU-> List(N,Y,N,N,N,X,X, D, D,Y,N,N,N,N,N,Y,N), FCVT_D_L -> List(N,Y,N,N,N,X,X, D, D,Y,N,N,N,N,N,Y,N), FCVT_D_LU-> List(N,Y,N,N,N,X,X, D, D,Y,N,N,N,N,N,Y,N), FMV_X_D -> List(N,N,Y,N,N,N,X, I, D,N,Y,N,N,N,N,N,N), FCLASS_D -> List(N,N,Y,N,N,N,X, D, D,N,Y,N,N,N,N,N,N), FCVT_W_D -> List(N,N,Y,N,N,N,X, D,X2,N,Y,N,N,N,N,Y,N), FCVT_WU_D-> List(N,N,Y,N,N,N,X, D,X2,N,Y,N,N,N,N,Y,N), FCVT_L_D -> List(N,N,Y,N,N,N,X, D,X2,N,Y,N,N,N,N,Y,N), FCVT_LU_D-> List(N,N,Y,N,N,N,X, D,X2,N,Y,N,N,N,N,Y,N), FCVT_S_D -> List(N,Y,Y,N,N,N,X, D, S,N,N,Y,N,N,N,Y,N), FCVT_D_S -> List(N,Y,Y,N,N,N,X, S, D,N,N,Y,N,N,N,Y,N), FEQ_D -> List(N,N,Y,Y,N,N,N, D, D,N,Y,N,N,N,N,Y,N), FLT_D -> List(N,N,Y,Y,N,N,N, D, D,N,Y,N,N,N,N,Y,N), FLE_D -> List(N,N,Y,Y,N,N,N, D, D,N,Y,N,N,N,N,Y,N), FSGNJ_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,Y,N,N,N,N,N), FSGNJN_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,Y,N,N,N,N,N), FSGNJX_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,Y,N,N,N,N,N), FMIN_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,Y,N,N,N,Y,N), FMAX_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,Y,N,N,N,Y,N), FADD_D -> List(N,Y,Y,Y,N,N,Y, D, D,N,N,N,Y,N,N,Y,N), FSUB_D -> List(N,Y,Y,Y,N,N,Y, D, D,N,N,N,Y,N,N,Y,N), FMUL_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,N,Y,N,N,Y,N), FMADD_D -> List(N,Y,Y,Y,Y,N,N, D, D,N,N,N,Y,N,N,Y,N), FMSUB_D -> List(N,Y,Y,Y,Y,N,N, D, D,N,N,N,Y,N,N,Y,N), FNMADD_D -> List(N,Y,Y,Y,Y,N,N, D, D,N,N,N,Y,N,N,Y,N), FNMSUB_D -> List(N,Y,Y,Y,Y,N,N, D, D,N,N,N,Y,N,N,Y,N), FDIV_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,N,N,Y,N,Y,N), FSQRT_D -> List(N,Y,Y,N,N,N,X, D, D,N,N,N,N,N,Y,Y,N)) val fcvt_hd: Array[(BitPat, List[BitPat])] = Array(FCVT_H_D -> List(N,Y,Y,N,N,N,X, D, H,N,N,Y,N,N,N,Y,N), FCVT_D_H -> List(N,Y,Y,N,N,N,X, H, D,N,N,Y,N,N,N,Y,N)) val vfmv_f_s: Array[(BitPat, List[BitPat])] = Array(VFMV_F_S -> List(N,Y,N,N,N,N,X,X2,X2,N,N,N,N,N,N,N,Y)) val insns = ((minFLen, fLen) match { case (32, 32) => f case (16, 32) => h ++ f case (32, 64) => f ++ d case (16, 64) => h ++ f ++ d ++ fcvt_hd case other => throw new Exception(s"minFLen = ${minFLen} & fLen = ${fLen} is an unsupported configuration") }) ++ (if (usingVector) vfmv_f_s else Array[(BitPat, List[BitPat])]()) val decoder = DecodeLogic(io.inst, default, insns) val s = io.sigs val sigs = Seq(s.ldst, s.wen, s.ren1, s.ren2, s.ren3, s.swap12, s.swap23, s.typeTagIn, s.typeTagOut, s.fromint, s.toint, s.fastpipe, s.fma, s.div, s.sqrt, s.wflags, s.vec) sigs zip decoder map {case(s,d) => s := d} } class FPUCoreIO(implicit p: Parameters) extends CoreBundle()(p) { val hartid = Input(UInt(hartIdLen.W)) val time = Input(UInt(xLen.W)) val inst = Input(Bits(32.W)) val fromint_data = Input(Bits(xLen.W)) val fcsr_rm = Input(Bits(FPConstants.RM_SZ.W)) val fcsr_flags = Valid(Bits(FPConstants.FLAGS_SZ.W)) val v_sew = Input(UInt(3.W)) val store_data = Output(Bits(fLen.W)) val toint_data = Output(Bits(xLen.W)) val ll_resp_val = Input(Bool()) val ll_resp_type = Input(Bits(3.W)) val ll_resp_tag = Input(UInt(5.W)) val ll_resp_data = Input(Bits(fLen.W)) val valid = Input(Bool()) val fcsr_rdy = Output(Bool()) val nack_mem = Output(Bool()) val illegal_rm = Output(Bool()) val killx = Input(Bool()) val killm = Input(Bool()) val dec = Output(new FPUCtrlSigs()) val sboard_set = Output(Bool()) val sboard_clr = Output(Bool()) val sboard_clra = Output(UInt(5.W)) val keep_clock_enabled = Input(Bool()) } class FPUIO(implicit p: Parameters) extends FPUCoreIO ()(p) { val cp_req = Flipped(Decoupled(new FPInput())) //cp doesn't pay attn to kill sigs val cp_resp = Decoupled(new FPResult()) } class FPResult(implicit p: Parameters) extends CoreBundle()(p) { val data = Bits((fLen+1).W) val exc = Bits(FPConstants.FLAGS_SZ.W) } class IntToFPInput(implicit p: Parameters) extends CoreBundle()(p) with HasFPUCtrlSigs { val rm = Bits(FPConstants.RM_SZ.W) val typ = Bits(2.W) val in1 = Bits(xLen.W) } class FPInput(implicit p: Parameters) extends CoreBundle()(p) with HasFPUCtrlSigs { val rm = Bits(FPConstants.RM_SZ.W) val fmaCmd = Bits(2.W) val typ = Bits(2.W) val fmt = Bits(2.W) val in1 = Bits((fLen+1).W) val in2 = Bits((fLen+1).W) val in3 = Bits((fLen+1).W) } case class FType(exp: Int, sig: Int) { def ieeeWidth = exp + sig def recodedWidth = ieeeWidth + 1 def ieeeQNaN = ((BigInt(1) << (ieeeWidth - 1)) - (BigInt(1) << (sig - 2))).U(ieeeWidth.W) def qNaN = ((BigInt(7) << (exp + sig - 3)) + (BigInt(1) << (sig - 2))).U(recodedWidth.W) def isNaN(x: UInt) = x(sig + exp - 1, sig + exp - 3).andR def isSNaN(x: UInt) = isNaN(x) && !x(sig - 2) def classify(x: UInt) = { val sign = x(sig + exp) val code = x(exp + sig - 1, exp + sig - 3) val codeHi = code(2, 1) val isSpecial = codeHi === 3.U val isHighSubnormalIn = x(exp + sig - 3, sig - 1) < 2.U val isSubnormal = code === 1.U \|\| codeHi === 1.U && isHighSubnormalIn val isNormal = codeHi === 1.U && !isHighSubnormalIn \|\| codeHi === 2.U val isZero = code === 0.U val isInf = isSpecial && !code(0) val isNaN = code.andR val isSNaN = isNaN && !x(sig-2) val isQNaN = isNaN && x(sig-2) Cat(isQNaN, isSNaN, isInf && !sign, isNormal && !sign, isSubnormal && !sign, isZero && !sign, isZero && sign, isSubnormal && sign, isNormal && sign, isInf && sign) } // convert between formats, ignoring rounding, range, NaN def unsafeConvert(x: UInt, to: FType) = if (this == to) x else { val sign = x(sig + exp) val fractIn = x(sig - 2, 0) val expIn = x(sig + exp - 1, sig - 1) val fractOut = fractIn << to.sig >> sig val expOut = { val expCode = expIn(exp, exp - 2) val commonCase = (expIn + (1 << to.exp).U) - (1 << exp).U Mux(expCode === 0.U \|\| expCode >= 6.U, Cat(expCode, commonCase(to.exp - 3, 0)), commonCase(to.exp, 0)) } Cat(sign, expOut, fractOut) } private def ieeeBundle = { val expWidth = exp class IEEEBundle extends Bundle { val sign = Bool() val exp = UInt(expWidth.W) val sig = UInt((ieeeWidth-expWidth-1).W) } new IEEEBundle } def unpackIEEE(x: UInt) = x.asTypeOf(ieeeBundle) def recode(x: UInt) = hardfloat.recFNFromFN(exp, sig, x) def ieee(x: UInt) = hardfloat.fNFromRecFN(exp, sig, x) } object FType { val H = new FType(5, 11) val S = new FType(8, 24) val D = new FType(11, 53) val all = List(H, S, D) } trait HasFPUParameters { require(fLen == 0 \|\| FType.all.exists(_.ieeeWidth == fLen)) val minFLen: Int val fLen: Int def xLen: Int val minXLen = 32 val nIntTypes = log2Ceil(xLen/minXLen) + 1 def floatTypes = FType.all.filter(t => minFLen <= t.ieeeWidth && t.ieeeWidth <= fLen) def minType = floatTypes.head def maxType = floatTypes.last def prevType(t: FType) = floatTypes(typeTag(t) - 1) def maxExpWidth = maxType.exp def maxSigWidth = maxType.sig def typeTag(t: FType) = floatTypes.indexOf(t) def typeTagWbOffset = (FType.all.indexOf(minType) + 1).U def typeTagGroup(t: FType) = (if (floatTypes.contains(t)) typeTag(t) else typeTag(maxType)).U // typeTag def H = typeTagGroup(FType.H) def S = typeTagGroup(FType.S) def D = typeTagGroup(FType.D) def I = typeTag(maxType).U private def isBox(x: UInt, t: FType): Bool = x(t.sig + t.exp, t.sig + t.exp - 4).andR private def box(x: UInt, xt: FType, y: UInt, yt: FType): UInt = { require(xt.ieeeWidth == 2 * yt.ieeeWidth) val swizzledNaN = Cat( x(xt.sig + xt.exp, xt.sig + xt.exp - 3), x(xt.sig - 2, yt.recodedWidth - 1).andR, x(xt.sig + xt.exp - 5, xt.sig), y(yt.recodedWidth - 2), x(xt.sig - 2, yt.recodedWidth - 1), y(yt.recodedWidth - 1), y(yt.recodedWidth - 3, 0)) Mux(xt.isNaN(x), swizzledNaN, x) } // implement NaN unboxing for FU inputs def unbox(x: UInt, tag: UInt, exactType: Option[FType]): UInt = { val outType = exactType.getOrElse(maxType) def helper(x: UInt, t: FType): Seq[(Bool, UInt)] = { val prev = if (t == minType) { Seq() } else { val prevT = prevType(t) val unswizzled = Cat( x(prevT.sig + prevT.exp - 1), x(t.sig - 1), x(prevT.sig + prevT.exp - 2, 0)) val prev = helper(unswizzled, prevT) val isbox = isBox(x, t) prev.map(p => (isbox && p._1, p._2)) } prev :+ (true.B, t.unsafeConvert(x, outType)) } val (oks, floats) = helper(x, maxType).unzip if (exactType.isEmpty \|\| floatTypes.size == 1) { Mux(oks(tag), floats(tag), maxType.qNaN) } else { val t = exactType.get floats(typeTag(t)) \| Mux(oks(typeTag(t)), 0.U, t.qNaN) } } // make sure that the redundant bits in the NaN-boxed encoding are consistent def consistent(x: UInt): Bool = { def helper(x: UInt, t: FType): Bool = if (typeTag(t) == 0) true.B else { val prevT = prevType(t) val unswizzled = Cat( x(prevT.sig + prevT.exp - 1), x(t.sig - 1), x(prevT.sig + prevT.exp - 2, 0)) val prevOK = !isBox(x, t) \|\| helper(unswizzled, prevT) val curOK = !t.isNaN(x) \|\| x(t.sig + t.exp - 4) === x(t.sig - 2, prevT.recodedWidth - 1).andR prevOK && curOK } helper(x, maxType) } // generate a NaN box from an FU result def box(x: UInt, t: FType): UInt = { if (t == maxType) { x } else { val nt = floatTypes(typeTag(t) + 1) val bigger = box(((BigInt(1) << nt.recodedWidth)-1).U, nt, x, t) bigger \| ((BigInt(1) << maxType.recodedWidth) - (BigInt(1) << nt.recodedWidth)).U } } // generate a NaN box from an FU result def box(x: UInt, tag: UInt): UInt = { val opts = floatTypes.map(t => box(x, t)) opts(tag) } // zap bits that hardfloat thinks are don't-cares, but we do care about def sanitizeNaN(x: UInt, t: FType): UInt = { if (typeTag(t) == 0) { x } else { val maskedNaN = x & ~((BigInt(1) << (t.sig-1)) \| (BigInt(1) << (t.sig+t.exp-4))).U(t.recodedWidth.W) Mux(t.isNaN(x), maskedNaN, x) } } // implement NaN boxing and recoding for FL/fmv..x def recode(x: UInt, tag: UInt): UInt = { def helper(x: UInt, t: FType): UInt = { if (typeTag(t) == 0) { t.recode(x) } else { val prevT = prevType(t) box(t.recode(x), t, helper(x, prevT), prevT) } } // fill MSBs of subword loads to emulate a wider load of a NaN-boxed value val boxes = floatTypes.map(t => ((BigInt(1) << maxType.ieeeWidth) - (BigInt(1) << t.ieeeWidth)).U) helper(boxes(tag) \| x, maxType) } // implement NaN unboxing and un-recoding for FS/fmv.x. def ieee(x: UInt, t: FType = maxType): UInt = { if (typeTag(t) == 0) { t.ieee(x) } else { val unrecoded = t.ieee(x) val prevT = prevType(t) val prevRecoded = Cat( x(prevT.recodedWidth-2), x(t.sig-1), x(prevT.recodedWidth-3, 0)) val prevUnrecoded = ieee(prevRecoded, prevT) Cat(unrecoded >> prevT.ieeeWidth, Mux(t.isNaN(x), prevUnrecoded, unrecoded(prevT.ieeeWidth-1, 0))) } } } abstract class FPUModule(implicit val p: Parameters) extends Module with HasCoreParameters with HasFPUParameters class FPToInt(implicit p: Parameters) extends FPUModule()(p) with ShouldBeRetimed { class Output extends Bundle { val in = new FPInput val lt = Bool() val store = Bits(fLen.W) val toint = Bits(xLen.W) val exc = Bits(FPConstants.FLAGS_SZ.W) } val io = IO(new Bundle { val in = Flipped(Valid(new FPInput)) val out = Valid(new Output) }) val in = RegEnable(io.in.bits, io.in.valid) val valid = RegNext(io.in.valid) val dcmp = Module(new hardfloat.CompareRecFN(maxExpWidth, maxSigWidth)) dcmp.io.a := in.in1 dcmp.io.b := in.in2 dcmp.io.signaling := !in.rm(1) val tag = in.typeTagOut val toint_ieee = (floatTypes.map(t => if (t == FType.H) Fill(maxType.ieeeWidth / minXLen, ieee(in.in1)(15, 0).sextTo(minXLen)) else Fill(maxType.ieeeWidth / t.ieeeWidth, ieee(in.in1)(t.ieeeWidth - 1, 0))): Seq[UInt])(tag) val toint = WireDefault(toint_ieee) val intType = WireDefault(in.fmt(0)) io.out.bits.store := (floatTypes.map(t => Fill(fLen / t.ieeeWidth, ieee(in.in1)(t.ieeeWidth - 1, 0))): Seq[UInt])(tag) io.out.bits.toint := ((0 until nIntTypes).map(i => toint((minXLen << i) - 1, 0).sextTo(xLen)): Seq[UInt])(intType) io.out.bits.exc := 0.U when (in.rm(0)) { val classify_out = (floatTypes.map(t => t.classify(maxType.unsafeConvert(in.in1, t))): Seq[UInt])(tag) toint := classify_out \| (toint_ieee >> minXLen << minXLen) intType := false.B } when (in.wflags) { // feq/flt/fle, fcvt toint := (~in.rm & Cat(dcmp.io.lt, dcmp.io.eq)).orR \| (toint_ieee >> minXLen << minXLen) io.out.bits.exc := dcmp.io.exceptionFlags intType := false.B when (!in.ren2) { // fcvt val cvtType = in.typ.extract(log2Ceil(nIntTypes), 1) intType := cvtType val conv = Module(new hardfloat.RecFNToIN(maxExpWidth, maxSigWidth, xLen)) conv.io.in := in.in1 conv.io.roundingMode := in.rm conv.io.signedOut := ~in.typ(0) toint := conv.io.out io.out.bits.exc := Cat(conv.io.intExceptionFlags(2, 1).orR, 0.U(3.W), conv.io.intExceptionFlags(0)) for (i <- 0 until nIntTypes-1) { val w = minXLen << i when (cvtType === i.U) { val narrow = Module(new hardfloat.RecFNToIN(maxExpWidth, maxSigWidth, w)) narrow.io.in := in.in1 narrow.io.roundingMode := in.rm narrow.io.signedOut := ~in.typ(0) val excSign = in.in1(maxExpWidth + maxSigWidth) && !maxType.isNaN(in.in1) val excOut = Cat(conv.io.signedOut === excSign, Fill(w-1, !excSign)) val invalid = conv.io.intExceptionFlags(2) \|\| narrow.io.intExceptionFlags(1) when (invalid) { toint := Cat(conv.io.out >> w, excOut) } io.out.bits.exc := Cat(invalid, 0.U(3.W), !invalid && conv.io.intExceptionFlags(0)) } } } } io.out.valid := valid io.out.bits.lt := dcmp.io.lt \|\| (dcmp.io.a.asSInt < 0.S && dcmp.io.b.asSInt >= 0.S) io.out.bits.in := in } class IntToFP(val latency: Int)(implicit p: Parameters) extends FPUModule()(p) with ShouldBeRetimed { val io = IO(new Bundle { val in = Flipped(Valid(new IntToFPInput)) val out = Valid(new FPResult) }) val in = Pipe(io.in) val tag = in.bits.typeTagIn val mux = Wire(new FPResult) mux.exc := 0.U mux.data := recode(in.bits.in1, tag) val intValue = { val res = WireDefault(in.bits.in1.asSInt) for (i <- 0 until nIntTypes-1) { val smallInt = in.bits.in1((minXLen << i) - 1, 0) when (in.bits.typ.extract(log2Ceil(nIntTypes), 1) === i.U) { res := Mux(in.bits.typ(0), smallInt.zext, smallInt.asSInt) } } res.asUInt } when (in.bits.wflags) { // fcvt // could be improved for RVD/RVQ with a single variable-position rounding // unit, rather than N fixed-position ones val i2fResults = for (t <- floatTypes) yield { val i2f = Module(new hardfloat.INToRecFN(xLen, t.exp, t.sig)) i2f.io.signedIn := ~in.bits.typ(0) i2f.io.in := intValue i2f.io.roundingMode := in.bits.rm i2f.io.detectTininess := hardfloat.consts.tininess_afterRounding (sanitizeNaN(i2f.io.out, t), i2f.io.exceptionFlags) } val (data, exc) = i2fResults.unzip val dataPadded = data.init.map(d => Cat(data.last >> d.getWidth, d)) :+ data.last mux.data := dataPadded(tag) mux.exc := exc(tag) } io.out <> Pipe(in.valid, mux, latency-1) } class FPToFP(val latency: Int)(implicit p: Parameters) extends FPUModule()(p) with ShouldBeRetimed { val io = IO(new Bundle { val in = Flipped(Valid(new FPInput)) val out = Valid(new FPResult) val lt = Input(Bool()) // from FPToInt }) val in = Pipe(io.in) val signNum = Mux(in.bits.rm(1), in.bits.in1 ^ in.bits.in2, Mux(in.bits.rm(0), ~in.bits.in2, in.bits.in2)) val fsgnj = Cat(signNum(fLen), in.bits.in1(fLen-1, 0)) val fsgnjMux = Wire(new FPResult) fsgnjMux.exc := 0.U fsgnjMux.data := fsgnj when (in.bits.wflags) { // fmin/fmax val isnan1 = maxType.isNaN(in.bits.in1) val isnan2 = maxType.isNaN(in.bits.in2) val isInvalid = maxType.isSNaN(in.bits.in1) \|\| maxType.isSNaN(in.bits.in2) val isNaNOut = isnan1 && isnan2 val isLHS = isnan2 \|\| in.bits.rm(0) =/= io.lt && !isnan1 fsgnjMux.exc := isInvalid << 4 fsgnjMux.data := Mux(isNaNOut, maxType.qNaN, Mux(isLHS, in.bits.in1, in.bits.in2)) } val inTag = in.bits.typeTagIn val outTag = in.bits.typeTagOut val mux = WireDefault(fsgnjMux) for (t <- floatTypes.init) { when (outTag === typeTag(t).U) { mux.data := Cat(fsgnjMux.data >> t.recodedWidth, maxType.unsafeConvert(fsgnjMux.data, t)) } } when (in.bits.wflags && !in.bits.ren2) { // fcvt if (floatTypes.size > 1) { // widening conversions simply canonicalize NaN operands val widened = Mux(maxType.isNaN(in.bits.in1), maxType.qNaN, in.bits.in1) fsgnjMux.data := widened fsgnjMux.exc := maxType.isSNaN(in.bits.in1) << 4 // narrowing conversions require rounding (for RVQ, this could be // optimized to use a single variable-position rounding unit, rather // than two fixed-position ones) for (outType <- floatTypes.init) when (outTag === typeTag(outType).U && ((typeTag(outType) == 0).B \|\| outTag < inTag)) { val narrower = Module(new hardfloat.RecFNToRecFN(maxType.exp, maxType.sig, outType.exp, outType.sig)) narrower.io.in := in.bits.in1 narrower.io.roundingMode := in.bits.rm narrower.io.detectTininess := hardfloat.consts.tininess_afterRounding val narrowed = sanitizeNaN(narrower.io.out, outType) mux.data := Cat(fsgnjMux.data >> narrowed.getWidth, narrowed) mux.exc := narrower.io.exceptionFlags } } } io.out <> Pipe(in.valid, mux, latency-1) } class MulAddRecFNPipe(latency: Int, expWidth: Int, sigWidth: Int) extends Module { override def desiredName = s"MulAddRecFNPipe_l${latency}_e${expWidth}_s${sigWidth}" require(latency<=2) val io = IO(new Bundle { val validin = Input(Bool()) val op = Input(Bits(2.W)) val a = Input(Bits((expWidth + sigWidth + 1).W)) val b = Input(Bits((expWidth + sigWidth + 1).W)) val c = Input(Bits((expWidth + sigWidth + 1).W)) val roundingMode = Input(UInt(3.W)) val detectTininess = Input(UInt(1.W)) val out = Output(Bits((expWidth + sigWidth + 1).W)) val exceptionFlags = Output(Bits(5.W)) val validout = Output(Bool()) }) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val mulAddRecFNToRaw_preMul = Module(new hardfloat.MulAddRecFNToRaw_preMul(expWidth, sigWidth)) val mulAddRecFNToRaw_postMul = Module(new hardfloat.MulAddRecFNToRaw_postMul(expWidth, sigWidth)) mulAddRecFNToRaw_preMul.io.op := io.op mulAddRecFNToRaw_preMul.io.a := io.a mulAddRecFNToRaw_preMul.io.b := io.b mulAddRecFNToRaw_preMul.io.c := io.c val mulAddResult = (mulAddRecFNToRaw_preMul.io.mulAddA * mulAddRecFNToRaw_preMul.io.mulAddB) +& mulAddRecFNToRaw_preMul.io.mulAddC val valid_stage0 = Wire(Bool()) val roundingMode_stage0 = Wire(UInt(3.W)) val detectTininess_stage0 = Wire(UInt(1.W)) val postmul_regs = if(latency>0) 1 else 0 mulAddRecFNToRaw_postMul.io.fromPreMul := Pipe(io.validin, mulAddRecFNToRaw_preMul.io.toPostMul, postmul_regs).bits mulAddRecFNToRaw_postMul.io.mulAddResult := Pipe(io.validin, mulAddResult, postmul_regs).bits mulAddRecFNToRaw_postMul.io.roundingMode := Pipe(io.validin, io.roundingMode, postmul_regs).bits roundingMode_stage0 := Pipe(io.validin, io.roundingMode, postmul_regs).bits detectTininess_stage0 := Pipe(io.validin, io.detectTininess, postmul_regs).bits valid_stage0 := Pipe(io.validin, false.B, postmul_regs).valid //------------------------------------------------------------------------ //------------------------------------------------------------------------ val roundRawFNToRecFN = Module(new hardfloat.RoundRawFNToRecFN(expWidth, sigWidth, 0)) val round_regs = if(latency==2) 1 else 0 roundRawFNToRecFN.io.invalidExc := Pipe(valid_stage0, mulAddRecFNToRaw_postMul.io.invalidExc, round_regs).bits roundRawFNToRecFN.io.in := Pipe(valid_stage0, mulAddRecFNToRaw_postMul.io.rawOut, round_regs).bits roundRawFNToRecFN.io.roundingMode := Pipe(valid_stage0, roundingMode_stage0, round_regs).bits roundRawFNToRecFN.io.detectTininess := Pipe(valid_stage0, detectTininess_stage0, round_regs).bits io.validout := Pipe(valid_stage0, false.B, round_regs).valid roundRawFNToRecFN.io.infiniteExc := false.B io.out := roundRawFNToRecFN.io.out io.exceptionFlags := roundRawFNToRecFN.io.exceptionFlags } class FPUFMAPipe(val latency: Int, val t: FType) (implicit p: Parameters) extends FPUModule()(p) with ShouldBeRetimed { override def desiredName = s"FPUFMAPipe_l${latency}_f${t.ieeeWidth}" require(latency>0) val io = IO(new Bundle { val in = Flipped(Valid(new FPInput)) val out = Valid(new FPResult) }) val valid = RegNext(io.in.valid) val in = Reg(new FPInput) when (io.in.valid) { val one = 1.U << (t.sig + t.exp - 1) val zero = (io.in.bits.in1 ^ io.in.bits.in2) & (1.U << (t.sig + t.exp)) val cmd_fma = io.in.bits.ren3 val cmd_addsub = io.in.bits.swap23 in := io.in.bits when (cmd_addsub) { in.in2 := one } when (!(cmd_fma \|\| cmd_addsub)) { in.in3 := zero } } val fma = Module(new MulAddRecFNPipe((latency-1) min 2, t.exp, t.sig)) fma.io.validin := valid fma.io.op := in.fmaCmd fma.io.roundingMode := in.rm fma.io.detectTininess := hardfloat.consts.tininess_afterRounding fma.io.a := in.in1 fma.io.b := in.in2 fma.io.c := in.in3 val res = Wire(new FPResult) res.data := sanitizeNaN(fma.io.out, t) res.exc := fma.io.exceptionFlags io.out := Pipe(fma.io.validout, res, (latency-3) max 0) } class FPU(cfg: FPUParams)(implicit p: Parameters) extends FPUModule()(p) { val io = IO(new FPUIO) val (useClockGating, useDebugROB) = coreParams match { case r: RocketCoreParams => val sz = if (r.debugROB.isDefined) r.debugROB.get.size else 1 (r.clockGate, sz < 1) case _ => (false, false) } val clock_en_reg = Reg(Bool()) val clock_en = clock_en_reg \|\| io.cp_req.valid val gated_clock = if (!useClockGating) clock else ClockGate(clock, clock_en, "fpu_clock_gate") val fp_decoder = Module(new FPUDecoder) fp_decoder.io.inst := io.inst val id_ctrl = WireInit(fp_decoder.io.sigs) coreParams match { case r: RocketCoreParams => r.vector.map(v => { val v_decode = v.decoder(p) // Only need to get ren1 v_decode.io.inst := io.inst v_decode.io.vconfig := DontCare // core deals with this when (v_decode.io.legal && v_decode.io.read_frs1) { id_ctrl.ren1 := true.B id_ctrl.swap12 := false.B id_ctrl.toint := true.B id_ctrl.typeTagIn := I id_ctrl.typeTagOut := Mux(io.v_sew === 3.U, D, S) } when (v_decode.io.write_frd) { id_ctrl.wen := true.B } })} val ex_reg_valid = RegNext(io.valid, false.B) val ex_reg_inst = RegEnable(io.inst, io.valid) val ex_reg_ctrl = RegEnable(id_ctrl, io.valid) val ex_ra = List.fill(3)(Reg(UInt())) // load/vector response val load_wb = RegNext(io.ll_resp_val) val load_wb_typeTag = RegEnable(io.ll_resp_type(1,0) - typeTagWbOffset, io.ll_resp_val) val load_wb_data = RegEnable(io.ll_resp_data, io.ll_resp_val) val load_wb_tag = RegEnable(io.ll_resp_tag, io.ll_resp_val) class FPUImpl { // entering gated-clock domain val req_valid = ex_reg_valid \|\| io.cp_req.valid val ex_cp_valid = io.cp_req.fire val mem_cp_valid = RegNext(ex_cp_valid, false.B) val wb_cp_valid = RegNext(mem_cp_valid, false.B) val mem_reg_valid = RegInit(false.B) val killm = (io.killm \|\| io.nack_mem) && !mem_cp_valid // Kill X-stage instruction if M-stage is killed. This prevents it from // speculatively being sent to the div-sqrt unit, which can cause priority // inversion for two back-to-back divides, the first of which is killed. val killx = io.killx \|\| mem_reg_valid && killm mem_reg_valid := ex_reg_valid && !killx \|\| ex_cp_valid val mem_reg_inst = RegEnable(ex_reg_inst, ex_reg_valid) val wb_reg_valid = RegNext(mem_reg_valid && (!killm \|\| mem_cp_valid), false.B) val cp_ctrl = Wire(new FPUCtrlSigs) cp_ctrl :<>= io.cp_req.bits.viewAsSupertype(new FPUCtrlSigs) io.cp_resp.valid := false.B io.cp_resp.bits.data := 0.U io.cp_resp.bits.exc := DontCare val ex_ctrl = Mux(ex_cp_valid, cp_ctrl, ex_reg_ctrl) val mem_ctrl = RegEnable(ex_ctrl, req_valid) val wb_ctrl = RegEnable(mem_ctrl, mem_reg_valid) // CoreMonitorBundle to monitor fp register file writes val frfWriteBundle = Seq.fill(2)(WireInit(new CoreMonitorBundle(xLen, fLen), DontCare)) frfWriteBundle.foreach { i => i.clock := clock i.reset := reset i.hartid := io.hartid i.timer := io.time(31,0) i.valid := false.B i.wrenx := false.B i.wrenf := false.B i.excpt := false.B } // regfile val regfile = Mem(32, Bits((fLen+1).W)) when (load_wb) { val wdata = recode(load_wb_data, load_wb_typeTag) regfile(load_wb_tag) := wdata assert(consistent(wdata)) if (enableCommitLog) printf("f%d p%d 0x%x\n", load_wb_tag, load_wb_tag + 32.U, ieee(wdata)) if (useDebugROB) DebugROB.pushWb(clock, reset, io.hartid, load_wb, load_wb_tag + 32.U, ieee(wdata)) frfWriteBundle(0).wrdst := load_wb_tag frfWriteBundle(0).wrenf := true.B frfWriteBundle(0).wrdata := ieee(wdata) } val ex_rs = ex_ra.map(a => regfile(a)) when (io.valid) { when (id_ctrl.ren1) { when (!id_ctrl.swap12) { ex_ra(0) := io.inst(19,15) } when (id_ctrl.swap12) { ex_ra(1) := io.inst(19,15) } } when (id_ctrl.ren2) { when (id_ctrl.swap12) { ex_ra(0) := io.inst(24,20) } when (id_ctrl.swap23) { ex_ra(2) := io.inst(24,20) } when (!id_ctrl.swap12 && !id_ctrl.swap23) { ex_ra(1) := io.inst(24,20) } } when (id_ctrl.ren3) { ex_ra(2) := io.inst(31,27) } } val ex_rm = Mux(ex_reg_inst(14,12) === 7.U, io.fcsr_rm, ex_reg_inst(14,12)) def fuInput(minT: Option[FType]): FPInput = { val req = Wire(new FPInput) val tag = ex_ctrl.typeTagIn req.viewAsSupertype(new Bundle with HasFPUCtrlSigs) :#= ex_ctrl.viewAsSupertype(new Bundle with HasFPUCtrlSigs) req.rm := ex_rm req.in1 := unbox(ex_rs(0), tag, minT) req.in2 := unbox(ex_rs(1), tag, minT) req.in3 := unbox(ex_rs(2), tag, minT) req.typ := ex_reg_inst(21,20) req.fmt := ex_reg_inst(26,25) req.fmaCmd := ex_reg_inst(3,2) \| (!ex_ctrl.ren3 && ex_reg_inst(27)) when (ex_cp_valid) { req := io.cp_req.bits when (io.cp_req.bits.swap12) { req.in1 := io.cp_req.bits.in2 req.in2 := io.cp_req.bits.in1 } when (io.cp_req.bits.swap23) { req.in2 := io.cp_req.bits.in3 req.in3 := io.cp_req.bits.in2 } } req } val sfma = Module(new FPUFMAPipe(cfg.sfmaLatency, FType.S)) sfma.io.in.valid := req_valid && ex_ctrl.fma && ex_ctrl.typeTagOut === S sfma.io.in.bits := fuInput(Some(sfma.t)) val fpiu = Module(new FPToInt) fpiu.io.in.valid := req_valid && (ex_ctrl.toint \|\| ex_ctrl.div \|\| ex_ctrl.sqrt \|\| (ex_ctrl.fastpipe && ex_ctrl.wflags)) fpiu.io.in.bits := fuInput(None) io.store_data := fpiu.io.out.bits.store io.toint_data := fpiu.io.out.bits.toint when(fpiu.io.out.valid && mem_cp_valid && mem_ctrl.toint){ io.cp_resp.bits.data := fpiu.io.out.bits.toint io.cp_resp.valid := true.B } val ifpu = Module(new IntToFP(cfg.ifpuLatency)) ifpu.io.in.valid := req_valid && ex_ctrl.fromint ifpu.io.in.bits := fpiu.io.in.bits ifpu.io.in.bits.in1 := Mux(ex_cp_valid, io.cp_req.bits.in1, io.fromint_data) val fpmu = Module(new FPToFP(cfg.fpmuLatency)) fpmu.io.in.valid := req_valid && ex_ctrl.fastpipe fpmu.io.in.bits := fpiu.io.in.bits fpmu.io.lt := fpiu.io.out.bits.lt val divSqrt_wen = WireDefault(false.B) val divSqrt_inFlight = WireDefault(false.B) val divSqrt_waddr = Reg(UInt(5.W)) val divSqrt_cp = Reg(Bool()) val divSqrt_typeTag = Wire(UInt(log2Up(floatTypes.size).W)) val divSqrt_wdata = Wire(UInt((fLen+1).W)) val divSqrt_flags = Wire(UInt(FPConstants.FLAGS_SZ.W)) divSqrt_typeTag := DontCare divSqrt_wdata := DontCare divSqrt_flags := DontCare // writeback arbitration case class Pipe(p: Module, lat: Int, cond: (FPUCtrlSigs) => Bool, res: FPResult) val pipes = List( Pipe(fpmu, fpmu.latency, (c: FPUCtrlSigs) => c.fastpipe, fpmu.io.out.bits), Pipe(ifpu, ifpu.latency, (c: FPUCtrlSigs) => c.fromint, ifpu.io.out.bits), Pipe(sfma, sfma.latency, (c: FPUCtrlSigs) => c.fma && c.typeTagOut === S, sfma.io.out.bits)) ++ (fLen > 32).option({ val dfma = Module(new FPUFMAPipe(cfg.dfmaLatency, FType.D)) dfma.io.in.valid := req_valid && ex_ctrl.fma && ex_ctrl.typeTagOut === D dfma.io.in.bits := fuInput(Some(dfma.t)) Pipe(dfma, dfma.latency, (c: FPUCtrlSigs) => c.fma && c.typeTagOut === D, dfma.io.out.bits) }) ++ (minFLen == 16).option({ val hfma = Module(new FPUFMAPipe(cfg.sfmaLatency, FType.H)) hfma.io.in.valid := req_valid && ex_ctrl.fma && ex_ctrl.typeTagOut === H hfma.io.in.bits := fuInput(Some(hfma.t)) Pipe(hfma, hfma.latency, (c: FPUCtrlSigs) => c.fma && c.typeTagOut === H, hfma.io.out.bits) }) def latencyMask(c: FPUCtrlSigs, offset: Int) = { require(pipes.forall(_.lat >= offset)) pipes.map(p => Mux(p.cond(c), (1 << p.lat-offset).U, 0.U)).reduce(_\|_) } def pipeid(c: FPUCtrlSigs) = pipes.zipWithIndex.map(p => Mux(p._1.cond(c), p._2.U, 0.U)).reduce(_\|_) val maxLatency = pipes.map(_.lat).max val memLatencyMask = latencyMask(mem_ctrl, 2) class WBInfo extends Bundle { val rd = UInt(5.W) val typeTag = UInt(log2Up(floatTypes.size).W) val cp = Bool() val pipeid = UInt(log2Ceil(pipes.size).W) } val wen = RegInit(0.U((maxLatency-1).W)) val wbInfo = Reg(Vec(maxLatency-1, new WBInfo)) val mem_wen = mem_reg_valid && (mem_ctrl.fma \|\| mem_ctrl.fastpipe \|\| mem_ctrl.fromint) val write_port_busy = RegEnable(mem_wen && (memLatencyMask & latencyMask(ex_ctrl, 1)).orR \|\| (wen & latencyMask(ex_ctrl, 0)).orR, req_valid) ccover(mem_reg_valid && write_port_busy, "WB_STRUCTURAL", "structural hazard on writeback") for (i <- 0 until maxLatency-2) { when (wen(i+1)) { wbInfo(i) := wbInfo(i+1) } } wen := wen >> 1 when (mem_wen) { when (!killm) { wen := wen >> 1 \| memLatencyMask } for (i <- 0 until maxLatency-1) { when (!write_port_busy && memLatencyMask(i)) { wbInfo(i).cp := mem_cp_valid wbInfo(i).typeTag := mem_ctrl.typeTagOut wbInfo(i).pipeid := pipeid(mem_ctrl) wbInfo(i).rd := mem_reg_inst(11,7) } } } val waddr = Mux(divSqrt_wen, divSqrt_waddr, wbInfo(0).rd) val wb_cp = Mux(divSqrt_wen, divSqrt_cp, wbInfo(0).cp) val wtypeTag = Mux(divSqrt_wen, divSqrt_typeTag, wbInfo(0).typeTag) val wdata = box(Mux(divSqrt_wen, divSqrt_wdata, (pipes.map(_.res.data): Seq[UInt])(wbInfo(0).pipeid)), wtypeTag) val wexc = (pipes.map(_.res.exc): Seq[UInt])(wbInfo(0).pipeid) when ((!wbInfo(0).cp && wen(0)) \|\| divSqrt_wen) { assert(consistent(wdata)) regfile(waddr) := wdata if (enableCommitLog) { printf("f%d p%d 0x%x\n", waddr, waddr + 32.U, ieee(wdata)) } frfWriteBundle(1).wrdst := waddr frfWriteBundle(1).wrenf := true.B frfWriteBundle(1).wrdata := ieee(wdata) } if (useDebugROB) { DebugROB.pushWb(clock, reset, io.hartid, (!wbInfo(0).cp && wen(0)) \|\| divSqrt_wen, waddr + 32.U, ieee(wdata)) } when (wb_cp && (wen(0) \|\| divSqrt_wen)) { io.cp_resp.bits.data := wdata io.cp_resp.valid := true.B } assert(!io.cp_req.valid \|\| pipes.forall(_.lat == pipes.head.lat).B, s"FPU only supports coprocessor if FMA pipes have uniform latency ${pipes.map(_.lat)}") // Avoid structural hazards and nacking of external requests // toint responds in the MEM stage, so an incoming toint can induce a structural hazard against inflight FMAs io.cp_req.ready := !ex_reg_valid && !(cp_ctrl.toint && wen =/= 0.U) && !divSqrt_inFlight val wb_toint_valid = wb_reg_valid && wb_ctrl.toint val wb_toint_exc = RegEnable(fpiu.io.out.bits.exc, mem_ctrl.toint) io.fcsr_flags.valid := wb_toint_valid \|\| divSqrt_wen \|\| wen(0) io.fcsr_flags.bits := Mux(wb_toint_valid, wb_toint_exc, 0.U) \| Mux(divSqrt_wen, divSqrt_flags, 0.U) \| Mux(wen(0), wexc, 0.U) val divSqrt_write_port_busy = (mem_ctrl.div \|\| mem_ctrl.sqrt) && wen.orR io.fcsr_rdy := !(ex_reg_valid && ex_ctrl.wflags \|\| mem_reg_valid && mem_ctrl.wflags \|\| wb_reg_valid && wb_ctrl.toint \|\| wen.orR \|\| divSqrt_inFlight) io.nack_mem := (write_port_busy \|\| divSqrt_write_port_busy \|\| divSqrt_inFlight) && !mem_cp_valid io.dec <> id_ctrl def useScoreboard(f: ((Pipe, Int)) => Bool) = pipes.zipWithIndex.filter(_._1.lat > 3).map(x => f(x)).fold(false.B)(_\|\|_) io.sboard_set := wb_reg_valid && !wb_cp_valid && RegNext(useScoreboard(_._1.cond(mem_ctrl)) \|\| mem_ctrl.div \|\| mem_ctrl.sqrt \|\| mem_ctrl.vec) io.sboard_clr := !wb_cp_valid && (divSqrt_wen \|\| (wen(0) && useScoreboard(x => wbInfo(0).pipeid === x._2.U))) io.sboard_clra := waddr ccover(io.sboard_clr && load_wb, "DUAL_WRITEBACK", "load and FMA writeback on same cycle") // we don't currently support round-max-magnitude (rm=4) io.illegal_rm := io.inst(14,12).isOneOf(5.U, 6.U) \|\| io.inst(14,12) === 7.U && io.fcsr_rm >= 5.U if (cfg.divSqrt) { val divSqrt_inValid = mem_reg_valid && (mem_ctrl.div \|\| mem_ctrl.sqrt) && !divSqrt_inFlight val divSqrt_killed = RegNext(divSqrt_inValid && killm, true.B) when (divSqrt_inValid) { divSqrt_waddr := mem_reg_inst(11,7) divSqrt_cp := mem_cp_valid } ccover(divSqrt_inFlight && divSqrt_killed, "DIV_KILLED", "divide killed after issued to divider") ccover(divSqrt_inFlight && mem_reg_valid && (mem_ctrl.div \|\| mem_ctrl.sqrt), "DIV_BUSY", "divider structural hazard") ccover(mem_reg_valid && divSqrt_write_port_busy, "DIV_WB_STRUCTURAL", "structural hazard on division writeback") for (t <- floatTypes) { val tag = mem_ctrl.typeTagOut val divSqrt = withReset(divSqrt_killed) { Module(new hardfloat.DivSqrtRecFN_small(t.exp, t.sig, 0)) } divSqrt.io.inValid := divSqrt_inValid && tag === typeTag(t).U divSqrt.io.sqrtOp := mem_ctrl.sqrt divSqrt.io.a := maxType.unsafeConvert(fpiu.io.out.bits.in.in1, t) divSqrt.io.b := maxType.unsafeConvert(fpiu.io.out.bits.in.in2, t) divSqrt.io.roundingMode := fpiu.io.out.bits.in.rm divSqrt.io.detectTininess := hardfloat.consts.tininess_afterRounding when (!divSqrt.io.inReady) { divSqrt_inFlight := true.B } // only 1 in flight when (divSqrt.io.outValid_div \|\| divSqrt.io.outValid_sqrt) { divSqrt_wen := !divSqrt_killed divSqrt_wdata := sanitizeNaN(divSqrt.io.out, t) divSqrt_flags := divSqrt.io.exceptionFlags divSqrt_typeTag := typeTag(t).U } } when (divSqrt_killed) { divSqrt_inFlight := false.B } } else { when (id_ctrl.div \|\| id_ctrl.sqrt) { io.illegal_rm := true.B } } // gate the clock clock_en_reg := !useClockGating.B \|\| io.keep_clock_enabled \|\| // chicken bit io.valid \|\| // ID stage req_valid \|\| // EX stage mem_reg_valid \|\| mem_cp_valid \|\| // MEM stage wb_reg_valid \|\| wb_cp_valid \|\| // WB stage wen.orR \|\| divSqrt_inFlight \|\| // post-WB stage io.ll_resp_val // load writeback } // leaving gated-clock domain val fpuImpl = withClock (gated_clock) { new FPUImpl } def ccover(cond: Bool, label: String, desc: String)(implicit sourceInfo: SourceInfo) = property.cover(cond, s"FPU_$label", "Core;;" + desc) }	module FPUFMAPipe_l4_f64_2( // @[FPU.scala:697:7] input clock, // @[FPU.scala:697:7] input reset, // @[FPU.scala:697:7] input io_in_valid, // @[FPU.scala:702:14] input io_in_bits_ldst, // @[FPU.scala:702:14] input io_in_bits_wen, // @[FPU.scala:702:14] input io_in_bits_ren1, // @[FPU.scala:702:14] input io_in_bits_ren2, // @[FPU.scala:702:14] input io_in_bits_ren3, // @[FPU.scala:702:14] input io_in_bits_swap12, // @[FPU.scala:702:14] input io_in_bits_swap23, // @[FPU.scala:702:14] input [1:0] io_in_bits_typeTagIn, // @[FPU.scala:702:14] input [1:0] io_in_bits_typeTagOut, // @[FPU.scala:702:14] input io_in_bits_fromint, // @[FPU.scala:702:14] input io_in_bits_toint, // @[FPU.scala:702:14] input io_in_bits_fastpipe, // @[FPU.scala:702:14] input io_in_bits_fma, // @[FPU.scala:702:14] input io_in_bits_div, // @[FPU.scala:702:14] input io_in_bits_sqrt, // @[FPU.scala:702:14] input io_in_bits_wflags, // @[FPU.scala:702:14] input io_in_bits_vec, // @[FPU.scala:702:14] input [2:0] io_in_bits_rm, // @[FPU.scala:702:14] input [1:0] io_in_bits_fmaCmd, // @[FPU.scala:702:14] input [1:0] io_in_bits_typ, // @[FPU.scala:702:14] input [1:0] io_in_bits_fmt, // @[FPU.scala:702:14] input [64:0] io_in_bits_in1, // @[FPU.scala:702:14] input [64:0] io_in_bits_in2, // @[FPU.scala:702:14] input [64:0] io_in_bits_in3, // @[FPU.scala:702:14] output [64:0] io_out_bits_data, // @[FPU.scala:702:14] output [4:0] io_out_bits_exc // @[FPU.scala:702:14] ); wire [64:0] _fma_io_out; // @[FPU.scala:719:19] wire _fma_io_validout; // @[FPU.scala:719:19] wire io_in_valid_0 = io_in_valid; // @[FPU.scala:697:7] wire io_in_bits_ldst_0 = io_in_bits_ldst; // @[FPU.scala:697:7] wire io_in_bits_wen_0 = io_in_bits_wen; // @[FPU.scala:697:7] wire io_in_bits_ren1_0 = io_in_bits_ren1; // @[FPU.scala:697:7] wire io_in_bits_ren2_0 = io_in_bits_ren2; // @[FPU.scala:697:7] wire io_in_bits_ren3_0 = io_in_bits_ren3; // @[FPU.scala:697:7] wire io_in_bits_swap12_0 = io_in_bits_swap12; // @[FPU.scala:697:7] wire io_in_bits_swap23_0 = io_in_bits_swap23; // @[FPU.scala:697:7] wire [1:0] io_in_bits_typeTagIn_0 = io_in_bits_typeTagIn; // @[FPU.scala:697:7] wire [1:0] io_in_bits_typeTagOut_0 = io_in_bits_typeTagOut; // @[FPU.scala:697:7] wire io_in_bits_fromint_0 = io_in_bits_fromint; // @[FPU.scala:697:7] wire io_in_bits_toint_0 = io_in_bits_toint; // @[FPU.scala:697:7] wire io_in_bits_fastpipe_0 = io_in_bits_fastpipe; // @[FPU.scala:697:7] wire io_in_bits_fma_0 = io_in_bits_fma; // @[FPU.scala:697:7] wire io_in_bits_div_0 = io_in_bits_div; // @[FPU.scala:697:7] wire io_in_bits_sqrt_0 = io_in_bits_sqrt; // @[FPU.scala:697:7] wire io_in_bits_wflags_0 = io_in_bits_wflags; // @[FPU.scala:697:7] wire io_in_bits_vec_0 = io_in_bits_vec; // @[FPU.scala:697:7] wire [2:0] io_in_bits_rm_0 = io_in_bits_rm; // @[FPU.scala:697:7] wire [1:0] io_in_bits_fmaCmd_0 = io_in_bits_fmaCmd; // @[FPU.scala:697:7] wire [1:0] io_in_bits_typ_0 = io_in_bits_typ; // @[FPU.scala:697:7] wire [1:0] io_in_bits_fmt_0 = io_in_bits_fmt; // @[FPU.scala:697:7] wire [64:0] io_in_bits_in1_0 = io_in_bits_in1; // @[FPU.scala:697:7] wire [64:0] io_in_bits_in2_0 = io_in_bits_in2; // @[FPU.scala:697:7] wire [64:0] io_in_bits_in3_0 = io_in_bits_in3; // @[FPU.scala:697:7] wire [63:0] one = 64'h8000000000000000; // @[FPU.scala:710:19] wire [64:0] _zero_T_1 = 65'h10000000000000000; // @[FPU.scala:711:57] wire [64:0] _res_data_maskedNaN_T = 65'h1EFEFFFFFFFFFFFFF; // @[FPU.scala:413:27] wire io_out_pipe_out_valid; // @[Valid.scala:135:21] wire [64:0] io_out_pipe_out_bits_data; // @[Valid.scala:135:21] wire [4:0] io_out_pipe_out_bits_exc; // @[Valid.scala:135:21] wire [64:0] io_out_bits_data_0; // @[FPU.scala:697:7] wire [4:0] io_out_bits_exc_0; // @[FPU.scala:697:7] wire io_out_valid; // @[FPU.scala:697:7] reg valid; // @[FPU.scala:707:22] reg in_ldst; // @[FPU.scala:708:15] reg in_wen; // @[FPU.scala:708:15] reg in_ren1; // @[FPU.scala:708:15] reg in_ren2; // @[FPU.scala:708:15] reg in_ren3; // @[FPU.scala:708:15] reg in_swap12; // @[FPU.scala:708:15] reg in_swap23; // @[FPU.scala:708:15] reg [1:0] in_typeTagIn; // @[FPU.scala:708:15] reg [1:0] in_typeTagOut; // @[FPU.scala:708:15] reg in_fromint; // @[FPU.scala:708:15] reg in_toint; // @[FPU.scala:708:15] reg in_fastpipe; // @[FPU.scala:708:15] reg in_fma; // @[FPU.scala:708:15] reg in_div; // @[FPU.scala:708:15] reg in_sqrt; // @[FPU.scala:708:15] reg in_wflags; // @[FPU.scala:708:15] reg in_vec; // @[FPU.scala:708:15] reg [2:0] in_rm; // @[FPU.scala:708:15] reg [1:0] in_fmaCmd; // @[FPU.scala:708:15] reg [1:0] in_typ; // @[FPU.scala:708:15] reg [1:0] in_fmt; // @[FPU.scala:708:15] reg [64:0] in_in1; // @[FPU.scala:708:15] reg [64:0] in_in2; // @[FPU.scala:708:15] reg [64:0] in_in3; // @[FPU.scala:708:15] wire [64:0] _zero_T = io_in_bits_in1_0 ^ io_in_bits_in2_0; // @[FPU.scala:697:7, :711:32] wire [64:0] zero = _zero_T & 65'h10000000000000000; // @[FPU.scala:711:{32,50}] wire [64:0] _res_data_T_2; // @[FPU.scala:414:10] wire [64:0] res_data; // @[FPU.scala:728:17] wire [4:0] res_exc; // @[FPU.scala:728:17] wire [64:0] res_data_maskedNaN = _fma_io_out & 65'h1EFEFFFFFFFFFFFFF; // @[FPU.scala:413:25, :719:19] wire [2:0] _res_data_T = _fma_io_out[63:61]; // @[FPU.scala:249:25, :719:19] wire _res_data_T_1 = &_res_data_T; // @[FPU.scala:249:{25,56}] assign _res_data_T_2 = _res_data_T_1 ? res_data_maskedNaN : _fma_io_out; // @[FPU.scala:249:56, :413:25, :414:10, :719:19] assign res_data = _res_data_T_2; // @[FPU.scala:414:10, :728:17] reg io_out_pipe_v; // @[Valid.scala:141:24] assign io_out_pipe_out_valid = io_out_pipe_v; // @[Valid.scala:135:21, :141:24] reg [64:0] io_out_pipe_b_data; // @[Valid.scala:142:26] assign io_out_pipe_out_bits_data = io_out_pipe_b_data; // @[Valid.scala:135:21, :142:26] reg [4:0] io_out_pipe_b_exc; // @[Valid.scala:142:26] assign io_out_pipe_out_bits_exc = io_out_pipe_b_exc; // @[Valid.scala:135:21, :142:26] assign io_out_valid = io_out_pipe_out_valid; // @[Valid.scala:135:21] assign io_out_bits_data_0 = io_out_pipe_out_bits_data; // @[Valid.scala:135:21] assign io_out_bits_exc_0 = io_out_pipe_out_bits_exc; // @[Valid.scala:135:21] always @(posedge clock) begin // @[FPU.scala:697:7] valid <= io_in_valid_0; // @[FPU.scala:697:7, :707:22] if (io_in_valid_0) begin // @[FPU.scala:697:7] in_ldst <= io_in_bits_ldst_0; // @[FPU.scala:697:7, :708:15] in_wen <= io_in_bits_wen_0; // @[FPU.scala:697:7, :708:15] in_ren1 <= io_in_bits_ren1_0; // @[FPU.scala:697:7, :708:15] in_ren2 <= io_in_bits_ren2_0; // @[FPU.scala:697:7, :708:15] in_ren3 <= io_in_bits_ren3_0; // @[FPU.scala:697:7, :708:15] in_swap12 <= io_in_bits_swap12_0; // @[FPU.scala:697:7, :708:15] in_swap23 <= io_in_bits_swap23_0; // @[FPU.scala:697:7, :708:15] in_typeTagIn <= io_in_bits_typeTagIn_0; // @[FPU.scala:697:7, :708:15] in_typeTagOut <= io_in_bits_typeTagOut_0; // @[FPU.scala:697:7, :708:15] in_fromint <= io_in_bits_fromint_0; // @[FPU.scala:697:7, :708:15] in_toint <= io_in_bits_toint_0; // @[FPU.scala:697:7, :708:15] in_fastpipe <= io_in_bits_fastpipe_0; // @[FPU.scala:697:7, :708:15] in_fma <= io_in_bits_fma_0; // @[FPU.scala:697:7, :708:15] in_div <= io_in_bits_div_0; // @[FPU.scala:697:7, :708:15] in_sqrt <= io_in_bits_sqrt_0; // @[FPU.scala:697:7, :708:15] in_wflags <= io_in_bits_wflags_0; // @[FPU.scala:697:7, :708:15] in_vec <= io_in_bits_vec_0; // @[FPU.scala:697:7, :708:15] in_rm <= io_in_bits_rm_0; // @[FPU.scala:697:7, :708:15] in_fmaCmd <= io_in_bits_fmaCmd_0; // @[FPU.scala:697:7, :708:15] in_typ <= io_in_bits_typ_0; // @[FPU.scala:697:7, :708:15] in_fmt <= io_in_bits_fmt_0; // @[FPU.scala:697:7, :708:15] in_in1 <= io_in_bits_in1_0; // @[FPU.scala:697:7, :708:15] in_in2 <= io_in_bits_swap23_0 ? 65'h8000000000000000 : io_in_bits_in2_0; // @[FPU.scala:697:7, :708:15, :714:8, :715:{23,32}] in_in3 <= io_in_bits_ren3_0 \| io_in_bits_swap23_0 ? io_in_bits_in3_0 : zero; // @[FPU.scala:697:7, :708:15, :711:50, :714:8, :716:{21,37,46}] end if (_fma_io_validout) begin // @[FPU.scala:719:19] io_out_pipe_b_data <= res_data; // @[Valid.scala:142:26] io_out_pipe_b_exc <= res_exc; // @[Valid.scala:142:26] end if (reset) // @[FPU.scala:697:7] io_out_pipe_v <= 1'h0; // @[Valid.scala:141:24] else // @[FPU.scala:697:7] io_out_pipe_v <= _fma_io_validout; // @[Valid.scala:141:24] always @(posedge) MulAddRecFNPipe_l2_e11_s53_2 fma ( // @[FPU.scala:719:19] .clock (clock), .reset (reset), .io_validin (valid), // @[FPU.scala:707:22] .io_op (in_fmaCmd), // @[FPU.scala:708:15] .io_a (in_in1), // @[FPU.scala:708:15] .io_b (in_in2), // @[FPU.scala:708:15] .io_c (in_in3), // @[FPU.scala:708:15] .io_roundingMode (in_rm), // @[FPU.scala:708:15] .io_out (_fma_io_out), .io_exceptionFlags (res_exc), .io_validout (_fma_io_validout) ); // @[FPU.scala:719:19] assign io_out_bits_data = io_out_bits_data_0; // @[FPU.scala:697:7] assign io_out_bits_exc = io_out_bits_exc_0; // @[FPU.scala:697:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File PE.scala: // See README.md for license details. package gemmini import chisel3._ import chisel3.util._ class PEControl[T <: Data : Arithmetic](accType: T) extends Bundle { val dataflow = UInt(1.W) // TODO make this an Enum val propagate = UInt(1.W) // Which register should be propagated (and which should be accumulated)? val shift = UInt(log2Up(accType.getWidth).W) // TODO this isn't correct for Floats } class MacUnit[T <: Data](inputType: T, cType: T, dType: T) (implicit ev: Arithmetic[T]) extends Module { import ev._ val io = IO(new Bundle { val in_a = Input(inputType) val in_b = Input(inputType) val in_c = Input(cType) val out_d = Output(dType) }) io.out_d := io.in_c.mac(io.in_a, io.in_b) } // TODO update documentation /** * A PE implementing a MAC operation. Configured as fully combinational when integrated into a Mesh. * @param width Data width of operands / class PE[T <: Data](inputType: T, outputType: T, accType: T, df: Dataflow.Value, max_simultaneous_matmuls: Int) (implicit ev: Arithmetic[T]) extends Module { // Debugging variables import ev._ val io = IO(new Bundle { val in_a = Input(inputType) val in_b = Input(outputType) val in_d = Input(outputType) val out_a = Output(inputType) val out_b = Output(outputType) val out_c = Output(outputType) val in_control = Input(new PEControl(accType)) val out_control = Output(new PEControl(accType)) val in_id = Input(UInt(log2Up(max_simultaneous_matmuls).W)) val out_id = Output(UInt(log2Up(max_simultaneous_matmuls).W)) val in_last = Input(Bool()) val out_last = Output(Bool()) val in_valid = Input(Bool()) val out_valid = Output(Bool()) val bad_dataflow = Output(Bool()) }) val cType = if (df == Dataflow.WS) inputType else accType // When creating PEs that support multiple dataflows, the // elaboration/synthesis tools often fail to consolidate and de-duplicate // MAC units. To force mac circuitry to be re-used, we create a "mac_unit" // module here which just performs a single MAC operation val mac_unit = Module(new MacUnit(inputType, if (df == Dataflow.WS) outputType else accType, outputType)) val a = io.in_a val b = io.in_b val d = io.in_d val c1 = Reg(cType) val c2 = Reg(cType) val dataflow = io.in_control.dataflow val prop = io.in_control.propagate val shift = io.in_control.shift val id = io.in_id val last = io.in_last val valid = io.in_valid io.out_a := a io.out_control.dataflow := dataflow io.out_control.propagate := prop io.out_control.shift := shift io.out_id := id io.out_last := last io.out_valid := valid mac_unit.io.in_a := a val last_s = RegEnable(prop, valid) val flip = last_s =/= prop val shift_offset = Mux(flip, shift, 0.U) // Which dataflow are we using? val OUTPUT_STATIONARY = Dataflow.OS.id.U(1.W) val WEIGHT_STATIONARY = Dataflow.WS.id.U(1.W) // Is c1 being computed on, or propagated forward (in the output-stationary dataflow)? val COMPUTE = 0.U(1.W) val PROPAGATE = 1.U(1.W) io.bad_dataflow := false.B when ((df == Dataflow.OS).B \|\| ((df == Dataflow.BOTH).B && dataflow === OUTPUT_STATIONARY)) { when(prop === PROPAGATE) { io.out_c := (c1 >> shift_offset).clippedToWidthOf(outputType) io.out_b := b mac_unit.io.in_b := b.asTypeOf(inputType) mac_unit.io.in_c := c2 c2 := mac_unit.io.out_d c1 := d.withWidthOf(cType) }.otherwise { io.out_c := (c2 >> shift_offset).clippedToWidthOf(outputType) io.out_b := b mac_unit.io.in_b := b.asTypeOf(inputType) mac_unit.io.in_c := c1 c1 := mac_unit.io.out_d c2 := d.withWidthOf(cType) } }.elsewhen ((df == Dataflow.WS).B \|\| ((df == Dataflow.BOTH).B && dataflow === WEIGHT_STATIONARY)) { when(prop === PROPAGATE) { io.out_c := c1 mac_unit.io.in_b := c2.asTypeOf(inputType) mac_unit.io.in_c := b io.out_b := mac_unit.io.out_d c1 := d }.otherwise { io.out_c := c2 mac_unit.io.in_b := c1.asTypeOf(inputType) mac_unit.io.in_c := b io.out_b := mac_unit.io.out_d c2 := d } }.otherwise { io.bad_dataflow := true.B //assert(false.B, "unknown dataflow") io.out_c := DontCare io.out_b := DontCare mac_unit.io.in_b := b.asTypeOf(inputType) mac_unit.io.in_c := c2 } when (!valid) { c1 := c1 c2 := c2 mac_unit.io.in_b := DontCare mac_unit.io.in_c := DontCare } } File Arithmetic.scala: // A simple type class for Chisel datatypes that can add and multiply. To add your own type, simply create your own: // implicit MyTypeArithmetic extends Arithmetic[MyType] { ... } package gemmini import chisel3._ import chisel3.util._ import hardfloat._ // Bundles that represent the raw bits of custom datatypes case class Float(expWidth: Int, sigWidth: Int) extends Bundle { val bits = UInt((expWidth + sigWidth).W) val bias: Int = (1 << (expWidth-1)) - 1 } case class DummySInt(w: Int) extends Bundle { val bits = UInt(w.W) def dontCare: DummySInt = { val o = Wire(new DummySInt(w)) o.bits := 0.U o } } // The Arithmetic typeclass which implements various arithmetic operations on custom datatypes abstract class Arithmetic[T <: Data] { implicit def cast(t: T): ArithmeticOps[T] } abstract class ArithmeticOps[T <: Data](self: T) { def (t: T): T def mac(m1: T, m2: T): T // Returns (m1 * m2 + self) def +(t: T): T def -(t: T): T def >>(u: UInt): T // This is a rounding shift! Rounds away from 0 def >(t: T): Bool def identity: T def withWidthOf(t: T): T def clippedToWidthOf(t: T): T // Like "withWidthOf", except that it saturates def relu: T def zero: T def minimum: T // Optional parameters, which only need to be defined if you want to enable various optimizations for transformers def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[T])] = None def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[T])] = None def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = None def mult_with_reciprocal[U <: Data](reciprocal: U) = self } object Arithmetic { implicit object UIntArithmetic extends Arithmetic[UInt] { override implicit def cast(self: UInt) = new ArithmeticOps(self) { override def (t: UInt) = self t override def mac(m1: UInt, m2: UInt) = m1 * m2 + self override def +(t: UInt) = self + t override def -(t: UInt) = self - t override def >>(u: UInt) = { // The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm // TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here? val point_five = Mux(u === 0.U, 0.U, self(u - 1.U)) val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U val ones_digit = self(u) val r = point_five & (zeros \| ones_digit) (self >> u).asUInt + r } override def >(t: UInt): Bool = self > t override def withWidthOf(t: UInt) = self.asTypeOf(t) override def clippedToWidthOf(t: UInt) = { val sat = ((1 << (t.getWidth-1))-1).U Mux(self > sat, sat, self)(t.getWidth-1, 0) } override def relu: UInt = self override def zero: UInt = 0.U override def identity: UInt = 1.U override def minimum: UInt = 0.U } } implicit object SIntArithmetic extends Arithmetic[SInt] { override implicit def cast(self: SInt) = new ArithmeticOps(self) { override def (t: SInt) = self t override def mac(m1: SInt, m2: SInt) = m1 * m2 + self override def +(t: SInt) = self + t override def -(t: SInt) = self - t override def >>(u: UInt) = { // The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm // TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here? val point_five = Mux(u === 0.U, 0.U, self(u - 1.U)) val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U val ones_digit = self(u) val r = (point_five & (zeros \| ones_digit)).asBool (self >> u).asSInt + Mux(r, 1.S, 0.S) } override def >(t: SInt): Bool = self > t override def withWidthOf(t: SInt) = { if (self.getWidth >= t.getWidth) self(t.getWidth-1, 0).asSInt else { val sign_bits = t.getWidth - self.getWidth val sign = self(self.getWidth-1) Cat(Cat(Seq.fill(sign_bits)(sign)), self).asTypeOf(t) } } override def clippedToWidthOf(t: SInt): SInt = { val maxsat = ((1 << (t.getWidth-1))-1).S val minsat = (-(1 << (t.getWidth-1))).S MuxCase(self, Seq((self > maxsat) -> maxsat, (self < minsat) -> minsat))(t.getWidth-1, 0).asSInt } override def relu: SInt = Mux(self >= 0.S, self, 0.S) override def zero: SInt = 0.S override def identity: SInt = 1.S override def minimum: SInt = (-(1 << (self.getWidth-1))).S override def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = { // TODO this uses a floating point divider, but we should use an integer divider instead val input = Wire(Decoupled(denom_t.cloneType)) val output = Wire(Decoupled(self.cloneType)) // We translate our integer to floating-point form so that we can use the hardfloat divider val expWidth = log2Up(self.getWidth) + 1 val sigWidth = self.getWidth def sin_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def uin_to_float(x: UInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := false.B in_to_rec_fn.io.in := x in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def float_to_in(x: UInt) = { val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth)) rec_fn_to_in.io.signedOut := true.B rec_fn_to_in.io.in := x rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag rec_fn_to_in.io.out.asSInt } val self_rec = sin_to_float(self) val denom_rec = uin_to_float(input.bits) // Instantiate the hardloat divider val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options)) input.ready := divider.io.inReady divider.io.inValid := input.valid divider.io.sqrtOp := false.B divider.io.a := self_rec divider.io.b := denom_rec divider.io.roundingMode := consts.round_minMag divider.io.detectTininess := consts.tininess_afterRounding output.valid := divider.io.outValid_div output.bits := float_to_in(divider.io.out) assert(!output.valid \|\| output.ready) Some((input, output)) } override def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = { // TODO this uses a floating point divider, but we should use an integer divider instead val input = Wire(Decoupled(UInt(0.W))) val output = Wire(Decoupled(self.cloneType)) input.bits := DontCare // We translate our integer to floating-point form so that we can use the hardfloat divider val expWidth = log2Up(self.getWidth) + 1 val sigWidth = self.getWidth def in_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def float_to_in(x: UInt) = { val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth)) rec_fn_to_in.io.signedOut := true.B rec_fn_to_in.io.in := x rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag rec_fn_to_in.io.out.asSInt } val self_rec = in_to_float(self) // Instantiate the hardloat sqrt val sqrter = Module(new DivSqrtRecFN_small(expWidth, sigWidth, 0)) input.ready := sqrter.io.inReady sqrter.io.inValid := input.valid sqrter.io.sqrtOp := true.B sqrter.io.a := self_rec sqrter.io.b := DontCare sqrter.io.roundingMode := consts.round_minMag sqrter.io.detectTininess := consts.tininess_afterRounding output.valid := sqrter.io.outValid_sqrt output.bits := float_to_in(sqrter.io.out) assert(!output.valid \|\| output.ready) Some((input, output)) } override def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = u match { case Float(expWidth, sigWidth) => val input = Wire(Decoupled(UInt(0.W))) val output = Wire(Decoupled(u.cloneType)) input.bits := DontCare // We translate our integer to floating-point form so that we can use the hardfloat divider def in_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } val self_rec = in_to_float(self) val one_rec = in_to_float(1.S) // Instantiate the hardloat divider val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options)) input.ready := divider.io.inReady divider.io.inValid := input.valid divider.io.sqrtOp := false.B divider.io.a := one_rec divider.io.b := self_rec divider.io.roundingMode := consts.round_near_even divider.io.detectTininess := consts.tininess_afterRounding output.valid := divider.io.outValid_div output.bits := fNFromRecFN(expWidth, sigWidth, divider.io.out).asTypeOf(u) assert(!output.valid \|\| output.ready) Some((input, output)) case _ => None } override def mult_with_reciprocal[U <: Data](reciprocal: U): SInt = reciprocal match { case recip @ Float(expWidth, sigWidth) => def in_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def float_to_in(x: UInt) = { val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth)) rec_fn_to_in.io.signedOut := true.B rec_fn_to_in.io.in := x rec_fn_to_in.io.roundingMode := consts.round_minMag rec_fn_to_in.io.out.asSInt } val self_rec = in_to_float(self) val reciprocal_rec = recFNFromFN(expWidth, sigWidth, recip.bits) // Instantiate the hardloat divider val muladder = Module(new MulRecFN(expWidth, sigWidth)) muladder.io.roundingMode := consts.round_near_even muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := self_rec muladder.io.b := reciprocal_rec float_to_in(muladder.io.out) case _ => self } } } implicit object FloatArithmetic extends Arithmetic[Float] { // TODO Floating point arithmetic currently switches between recoded and standard formats for every operation. However, it should stay in the recoded format as it travels through the systolic array override implicit def cast(self: Float): ArithmeticOps[Float] = new ArithmeticOps(self) { override def (t: Float): Float = { val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth)) t_resizer.io.in := t_rec t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag t_resizer.io.detectTininess := consts.tininess_afterRounding val t_rec_resized = t_resizer.io.out val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth)) muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := self_rec muladder.io.b := t_rec_resized val out = Wire(Float(self.expWidth, self.sigWidth)) out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) out } override def mac(m1: Float, m2: Float): Float = { // Recode all operands val m1_rec = recFNFromFN(m1.expWidth, m1.sigWidth, m1.bits) val m2_rec = recFNFromFN(m2.expWidth, m2.sigWidth, m2.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Resize m1 to self's width val m1_resizer = Module(new RecFNToRecFN(m1.expWidth, m1.sigWidth, self.expWidth, self.sigWidth)) m1_resizer.io.in := m1_rec m1_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag m1_resizer.io.detectTininess := consts.tininess_afterRounding val m1_rec_resized = m1_resizer.io.out // Resize m2 to self's width val m2_resizer = Module(new RecFNToRecFN(m2.expWidth, m2.sigWidth, self.expWidth, self.sigWidth)) m2_resizer.io.in := m2_rec m2_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag m2_resizer.io.detectTininess := consts.tininess_afterRounding val m2_rec_resized = m2_resizer.io.out // Perform multiply-add val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth)) muladder.io.op := 0.U muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := m1_rec_resized muladder.io.b := m2_rec_resized muladder.io.c := self_rec // Convert result to standard format // TODO remove these intermediate recodings val out = Wire(Float(self.expWidth, self.sigWidth)) out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) out } override def +(t: Float): Float = { require(self.getWidth >= t.getWidth) // This just makes it easier to write the resizing code // Recode all operands val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Generate 1 as a float val in_to_rec_fn = Module(new INToRecFN(1, self.expWidth, self.sigWidth)) in_to_rec_fn.io.signedIn := false.B in_to_rec_fn.io.in := 1.U in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding val one_rec = in_to_rec_fn.io.out // Resize t val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth)) t_resizer.io.in := t_rec t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag t_resizer.io.detectTininess := consts.tininess_afterRounding val t_rec_resized = t_resizer.io.out // Perform addition val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth)) muladder.io.op := 0.U muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := t_rec_resized muladder.io.b := one_rec muladder.io.c := self_rec val result = Wire(Float(self.expWidth, self.sigWidth)) result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) result } override def -(t: Float): Float = { val t_sgn = t.bits(t.getWidth-1) val neg_t = Cat(~t_sgn, t.bits(t.getWidth-2,0)).asTypeOf(t) self + neg_t } override def >>(u: UInt): Float = { // Recode self val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Get 2^(-u) as a recoded float val shift_exp = Wire(UInt(self.expWidth.W)) shift_exp := self.bias.U - u val shift_fn = Cat(0.U(1.W), shift_exp, 0.U((self.sigWidth-1).W)) val shift_rec = recFNFromFN(self.expWidth, self.sigWidth, shift_fn) assert(shift_exp =/= 0.U, "scaling by denormalized numbers is not currently supported") // Multiply self and 2^(-u) val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth)) muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := self_rec muladder.io.b := shift_rec val result = Wire(Float(self.expWidth, self.sigWidth)) result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) result } override def >(t: Float): Bool = { // Recode all operands val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Resize t to self's width val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth)) t_resizer.io.in := t_rec t_resizer.io.roundingMode := consts.round_near_even t_resizer.io.detectTininess := consts.tininess_afterRounding val t_rec_resized = t_resizer.io.out val comparator = Module(new CompareRecFN(self.expWidth, self.sigWidth)) comparator.io.a := self_rec comparator.io.b := t_rec_resized comparator.io.signaling := false.B comparator.io.gt } override def withWidthOf(t: Float): Float = { val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth)) resizer.io.in := self_rec resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag resizer.io.detectTininess := consts.tininess_afterRounding val result = Wire(Float(t.expWidth, t.sigWidth)) result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out) result } override def clippedToWidthOf(t: Float): Float = { // TODO check for overflow. Right now, we just assume that overflow doesn't happen val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth)) resizer.io.in := self_rec resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag resizer.io.detectTininess := consts.tininess_afterRounding val result = Wire(Float(t.expWidth, t.sigWidth)) result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out) result } override def relu: Float = { val raw = rawFloatFromFN(self.expWidth, self.sigWidth, self.bits) val result = Wire(Float(self.expWidth, self.sigWidth)) result.bits := Mux(!raw.isZero && raw.sign, 0.U, self.bits) result } override def zero: Float = 0.U.asTypeOf(self) override def identity: Float = Cat(0.U(2.W), ~(0.U((self.expWidth-1).W)), 0.U((self.sigWidth-1).W)).asTypeOf(self) override def minimum: Float = Cat(1.U, ~(0.U(self.expWidth.W)), 0.U((self.sigWidth-1).W)).asTypeOf(self) } } implicit object DummySIntArithmetic extends Arithmetic[DummySInt] { override implicit def cast(self: DummySInt) = new ArithmeticOps(self) { override def (t: DummySInt) = self.dontCare override def mac(m1: DummySInt, m2: DummySInt) = self.dontCare override def +(t: DummySInt) = self.dontCare override def -(t: DummySInt) = self.dontCare override def >>(t: UInt) = self.dontCare override def >(t: DummySInt): Bool = false.B override def identity = self.dontCare override def withWidthOf(t: DummySInt) = self.dontCare override def clippedToWidthOf(t: DummySInt) = self.dontCare override def relu = self.dontCare override def zero = self.dontCare override def minimum: DummySInt = self.dontCare } } }	module PE_288( // @[PE.scala:31:7] input clock, // @[PE.scala:31:7] input reset, // @[PE.scala:31:7] input [7:0] io_in_a, // @[PE.scala:35:14] input [19:0] io_in_b, // @[PE.scala:35:14] input [19:0] io_in_d, // @[PE.scala:35:14] output [7:0] io_out_a, // @[PE.scala:35:14] output [19:0] io_out_b, // @[PE.scala:35:14] output [19:0] io_out_c, // @[PE.scala:35:14] input io_in_control_dataflow, // @[PE.scala:35:14] input io_in_control_propagate, // @[PE.scala:35:14] input [4:0] io_in_control_shift, // @[PE.scala:35:14] output io_out_control_dataflow, // @[PE.scala:35:14] output io_out_control_propagate, // @[PE.scala:35:14] output [4:0] io_out_control_shift, // @[PE.scala:35:14] input [2:0] io_in_id, // @[PE.scala:35:14] output [2:0] io_out_id, // @[PE.scala:35:14] input io_in_last, // @[PE.scala:35:14] output io_out_last, // @[PE.scala:35:14] input io_in_valid, // @[PE.scala:35:14] output io_out_valid // @[PE.scala:35:14] ); wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:31:7] wire [19:0] io_in_b_0 = io_in_b; // @[PE.scala:31:7] wire [19:0] io_in_d_0 = io_in_d; // @[PE.scala:31:7] wire io_in_control_dataflow_0 = io_in_control_dataflow; // @[PE.scala:31:7] wire io_in_control_propagate_0 = io_in_control_propagate; // @[PE.scala:31:7] wire [4:0] io_in_control_shift_0 = io_in_control_shift; // @[PE.scala:31:7] wire [2:0] io_in_id_0 = io_in_id; // @[PE.scala:31:7] wire io_in_last_0 = io_in_last; // @[PE.scala:31:7] wire io_in_valid_0 = io_in_valid; // @[PE.scala:31:7] wire io_bad_dataflow = 1'h0; // @[PE.scala:31:7] wire _io_out_c_T_5 = 1'h0; // @[Arithmetic.scala:125:33] wire _io_out_c_T_6 = 1'h0; // @[Arithmetic.scala:125:60] wire _io_out_c_T_16 = 1'h0; // @[Arithmetic.scala:125:33] wire _io_out_c_T_17 = 1'h0; // @[Arithmetic.scala:125:60] wire [7:0] io_out_a_0 = io_in_a_0; // @[PE.scala:31:7] wire [19:0] _mac_unit_io_in_b_T = io_in_b_0; // @[PE.scala:31:7, :106:37] wire [19:0] _mac_unit_io_in_b_T_2 = io_in_b_0; // @[PE.scala:31:7, :113:37] wire [19:0] _mac_unit_io_in_b_T_8 = io_in_b_0; // @[PE.scala:31:7, :137:35] wire io_out_control_dataflow_0 = io_in_control_dataflow_0; // @[PE.scala:31:7] wire io_out_control_propagate_0 = io_in_control_propagate_0; // @[PE.scala:31:7] wire [4:0] io_out_control_shift_0 = io_in_control_shift_0; // @[PE.scala:31:7] wire [2:0] io_out_id_0 = io_in_id_0; // @[PE.scala:31:7] wire io_out_last_0 = io_in_last_0; // @[PE.scala:31:7] wire io_out_valid_0 = io_in_valid_0; // @[PE.scala:31:7] wire [19:0] io_out_b_0; // @[PE.scala:31:7] wire [19:0] io_out_c_0; // @[PE.scala:31:7] reg [7:0] c1; // @[PE.scala:70:15] wire [7:0] _io_out_c_zeros_T_1 = c1; // @[PE.scala:70:15] wire [7:0] _mac_unit_io_in_b_T_6 = c1; // @[PE.scala:70:15, :127:38] reg [7:0] c2; // @[PE.scala:71:15] wire [7:0] _io_out_c_zeros_T_10 = c2; // @[PE.scala:71:15] wire [7:0] _mac_unit_io_in_b_T_4 = c2; // @[PE.scala:71:15, :121:38] reg last_s; // @[PE.scala:89:25] wire flip = last_s != io_in_control_propagate_0; // @[PE.scala:31:7, :89:25, :90:21] wire [4:0] shift_offset = flip ? io_in_control_shift_0 : 5'h0; // @[PE.scala:31:7, :90:21, :91:25] wire _GEN = shift_offset == 5'h0; // @[PE.scala:91:25] wire _io_out_c_point_five_T; // @[Arithmetic.scala:101:32] assign _io_out_c_point_five_T = _GEN; // @[Arithmetic.scala:101:32] wire _io_out_c_point_five_T_5; // @[Arithmetic.scala:101:32] assign _io_out_c_point_five_T_5 = _GEN; // @[Arithmetic.scala:101:32] wire [5:0] _GEN_0 = {1'h0, shift_offset} - 6'h1; // @[PE.scala:91:25] wire [5:0] _io_out_c_point_five_T_1; // @[Arithmetic.scala:101:53] assign _io_out_c_point_five_T_1 = _GEN_0; // @[Arithmetic.scala:101:53] wire [5:0] _io_out_c_zeros_T_2; // @[Arithmetic.scala:102:66] assign _io_out_c_zeros_T_2 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66] wire [5:0] _io_out_c_point_five_T_6; // @[Arithmetic.scala:101:53] assign _io_out_c_point_five_T_6 = _GEN_0; // @[Arithmetic.scala:101:53] wire [5:0] _io_out_c_zeros_T_11; // @[Arithmetic.scala:102:66] assign _io_out_c_zeros_T_11 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66] wire [4:0] _io_out_c_point_five_T_2 = _io_out_c_point_five_T_1[4:0]; // @[Arithmetic.scala:101:53] wire [7:0] _io_out_c_point_five_T_3 = $signed($signed(c1) >>> _io_out_c_point_five_T_2); // @[PE.scala:70:15] wire _io_out_c_point_five_T_4 = _io_out_c_point_five_T_3[0]; // @[Arithmetic.scala:101:50] wire io_out_c_point_five = ~_io_out_c_point_five_T & _io_out_c_point_five_T_4; // @[Arithmetic.scala:101:{29,32,50}] wire _GEN_1 = shift_offset < 5'h2; // @[PE.scala:91:25] wire _io_out_c_zeros_T; // @[Arithmetic.scala:102:27] assign _io_out_c_zeros_T = _GEN_1; // @[Arithmetic.scala:102:27] wire _io_out_c_zeros_T_9; // @[Arithmetic.scala:102:27] assign _io_out_c_zeros_T_9 = _GEN_1; // @[Arithmetic.scala:102:27] wire [4:0] _io_out_c_zeros_T_3 = _io_out_c_zeros_T_2[4:0]; // @[Arithmetic.scala:102:66] wire [31:0] _io_out_c_zeros_T_4 = 32'h1 << _io_out_c_zeros_T_3; // @[Arithmetic.scala:102:{60,66}] wire [32:0] _io_out_c_zeros_T_5 = {1'h0, _io_out_c_zeros_T_4} - 33'h1; // @[Arithmetic.scala:102:{60,81}] wire [31:0] _io_out_c_zeros_T_6 = _io_out_c_zeros_T_5[31:0]; // @[Arithmetic.scala:102:81] wire [31:0] _io_out_c_zeros_T_7 = {24'h0, _io_out_c_zeros_T_6[7:0] & _io_out_c_zeros_T_1}; // @[Arithmetic.scala:102:{45,52,81}] wire [31:0] _io_out_c_zeros_T_8 = _io_out_c_zeros_T ? 32'h0 : _io_out_c_zeros_T_7; // @[Arithmetic.scala:102:{24,27,52}] wire io_out_c_zeros = \|_io_out_c_zeros_T_8; // @[Arithmetic.scala:102:{24,89}] wire [7:0] _GEN_2 = {3'h0, shift_offset}; // @[PE.scala:91:25] wire [7:0] _GEN_3 = $signed($signed(c1) >>> _GEN_2); // @[PE.scala:70:15] wire [7:0] _io_out_c_ones_digit_T; // @[Arithmetic.scala:103:30] assign _io_out_c_ones_digit_T = _GEN_3; // @[Arithmetic.scala:103:30] wire [7:0] _io_out_c_T; // @[Arithmetic.scala:107:15] assign _io_out_c_T = _GEN_3; // @[Arithmetic.scala:103:30, :107:15] wire io_out_c_ones_digit = _io_out_c_ones_digit_T[0]; // @[Arithmetic.scala:103:30] wire _io_out_c_r_T = io_out_c_zeros \| io_out_c_ones_digit; // @[Arithmetic.scala:102:89, :103:30, :105:38] wire _io_out_c_r_T_1 = io_out_c_point_five & _io_out_c_r_T; // @[Arithmetic.scala:101:29, :105:{29,38}] wire io_out_c_r = _io_out_c_r_T_1; // @[Arithmetic.scala:105:{29,53}] wire [1:0] _io_out_c_T_1 = {1'h0, io_out_c_r}; // @[Arithmetic.scala:105:53, :107:33] wire [8:0] _io_out_c_T_2 = {_io_out_c_T[7], _io_out_c_T} + {{7{_io_out_c_T_1[1]}}, _io_out_c_T_1}; // @[Arithmetic.scala:107:{15,28,33}] wire [7:0] _io_out_c_T_3 = _io_out_c_T_2[7:0]; // @[Arithmetic.scala:107:28] wire [7:0] _io_out_c_T_4 = _io_out_c_T_3; // @[Arithmetic.scala:107:28] wire [19:0] _io_out_c_T_7 = {{12{_io_out_c_T_4[7]}}, _io_out_c_T_4}; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_8 = _io_out_c_T_7; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_9 = _io_out_c_T_8; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_10 = _io_out_c_T_9; // @[Arithmetic.scala:125:{81,99}] wire [19:0] _mac_unit_io_in_b_T_1 = _mac_unit_io_in_b_T; // @[PE.scala:106:37] wire [7:0] _mac_unit_io_in_b_WIRE = _mac_unit_io_in_b_T_1[7:0]; // @[PE.scala:106:37] wire [7:0] _c1_T = io_in_d_0[7:0]; // @[PE.scala:31:7] wire [7:0] _c2_T = io_in_d_0[7:0]; // @[PE.scala:31:7] wire [7:0] _c1_T_1 = _c1_T; // @[Arithmetic.scala:114:{15,33}] wire [4:0] _io_out_c_point_five_T_7 = _io_out_c_point_five_T_6[4:0]; // @[Arithmetic.scala:101:53] wire [7:0] _io_out_c_point_five_T_8 = $signed($signed(c2) >>> _io_out_c_point_five_T_7); // @[PE.scala:71:15] wire _io_out_c_point_five_T_9 = _io_out_c_point_five_T_8[0]; // @[Arithmetic.scala:101:50] wire io_out_c_point_five_1 = ~_io_out_c_point_five_T_5 & _io_out_c_point_five_T_9; // @[Arithmetic.scala:101:{29,32,50}] wire [4:0] _io_out_c_zeros_T_12 = _io_out_c_zeros_T_11[4:0]; // @[Arithmetic.scala:102:66] wire [31:0] _io_out_c_zeros_T_13 = 32'h1 << _io_out_c_zeros_T_12; // @[Arithmetic.scala:102:{60,66}] wire [32:0] _io_out_c_zeros_T_14 = {1'h0, _io_out_c_zeros_T_13} - 33'h1; // @[Arithmetic.scala:102:{60,81}] wire [31:0] _io_out_c_zeros_T_15 = _io_out_c_zeros_T_14[31:0]; // @[Arithmetic.scala:102:81] wire [31:0] _io_out_c_zeros_T_16 = {24'h0, _io_out_c_zeros_T_15[7:0] & _io_out_c_zeros_T_10}; // @[Arithmetic.scala:102:{45,52,81}] wire [31:0] _io_out_c_zeros_T_17 = _io_out_c_zeros_T_9 ? 32'h0 : _io_out_c_zeros_T_16; // @[Arithmetic.scala:102:{24,27,52}] wire io_out_c_zeros_1 = \|_io_out_c_zeros_T_17; // @[Arithmetic.scala:102:{24,89}] wire [7:0] _GEN_4 = $signed($signed(c2) >>> _GEN_2); // @[PE.scala:71:15] wire [7:0] _io_out_c_ones_digit_T_1; // @[Arithmetic.scala:103:30] assign _io_out_c_ones_digit_T_1 = _GEN_4; // @[Arithmetic.scala:103:30] wire [7:0] _io_out_c_T_11; // @[Arithmetic.scala:107:15] assign _io_out_c_T_11 = _GEN_4; // @[Arithmetic.scala:103:30, :107:15] wire io_out_c_ones_digit_1 = _io_out_c_ones_digit_T_1[0]; // @[Arithmetic.scala:103:30] wire _io_out_c_r_T_2 = io_out_c_zeros_1 \| io_out_c_ones_digit_1; // @[Arithmetic.scala:102:89, :103:30, :105:38] wire _io_out_c_r_T_3 = io_out_c_point_five_1 & _io_out_c_r_T_2; // @[Arithmetic.scala:101:29, :105:{29,38}] wire io_out_c_r_1 = _io_out_c_r_T_3; // @[Arithmetic.scala:105:{29,53}] wire [1:0] _io_out_c_T_12 = {1'h0, io_out_c_r_1}; // @[Arithmetic.scala:105:53, :107:33] wire [8:0] _io_out_c_T_13 = {_io_out_c_T_11[7], _io_out_c_T_11} + {{7{_io_out_c_T_12[1]}}, _io_out_c_T_12}; // @[Arithmetic.scala:107:{15,28,33}] wire [7:0] _io_out_c_T_14 = _io_out_c_T_13[7:0]; // @[Arithmetic.scala:107:28] wire [7:0] _io_out_c_T_15 = _io_out_c_T_14; // @[Arithmetic.scala:107:28] wire [19:0] _io_out_c_T_18 = {{12{_io_out_c_T_15[7]}}, _io_out_c_T_15}; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_19 = _io_out_c_T_18; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_20 = _io_out_c_T_19; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_21 = _io_out_c_T_20; // @[Arithmetic.scala:125:{81,99}] wire [19:0] _mac_unit_io_in_b_T_3 = _mac_unit_io_in_b_T_2; // @[PE.scala:113:37] wire [7:0] _mac_unit_io_in_b_WIRE_1 = _mac_unit_io_in_b_T_3[7:0]; // @[PE.scala:113:37] wire [7:0] _c2_T_1 = _c2_T; // @[Arithmetic.scala:114:{15,33}] wire [7:0] _mac_unit_io_in_b_T_5; // @[PE.scala:121:38] assign _mac_unit_io_in_b_T_5 = _mac_unit_io_in_b_T_4; // @[PE.scala:121:38] wire [7:0] _mac_unit_io_in_b_WIRE_2 = _mac_unit_io_in_b_T_5; // @[PE.scala:121:38] assign io_out_c_0 = io_in_control_propagate_0 ? {{12{c1[7]}}, c1} : {{12{c2[7]}}, c2}; // @[PE.scala:31:7, :70:15, :71:15, :119:30, :120:16, :126:16] wire [7:0] _mac_unit_io_in_b_T_7; // @[PE.scala:127:38] assign _mac_unit_io_in_b_T_7 = _mac_unit_io_in_b_T_6; // @[PE.scala:127:38] wire [7:0] _mac_unit_io_in_b_WIRE_3 = _mac_unit_io_in_b_T_7; // @[PE.scala:127:38] wire [19:0] _mac_unit_io_in_b_T_9 = _mac_unit_io_in_b_T_8; // @[PE.scala:137:35] wire [7:0] _mac_unit_io_in_b_WIRE_4 = _mac_unit_io_in_b_T_9[7:0]; // @[PE.scala:137:35] always @(posedge clock) begin // @[PE.scala:31:7] if (io_in_valid_0 & io_in_control_propagate_0) // @[PE.scala:31:7, :102:95, :141:17, :142:8] c1 <= io_in_d_0[7:0]; // @[PE.scala:31:7, :70:15] if (~(~io_in_valid_0 \| io_in_control_propagate_0)) // @[PE.scala:31:7, :71:15, :102:95, :119:30, :130:10, :141:{9,17}, :143:8] c2 <= io_in_d_0[7:0]; // @[PE.scala:31:7, :71:15] if (io_in_valid_0) // @[PE.scala:31:7] last_s <= io_in_control_propagate_0; // @[PE.scala:31:7, :89:25] always @(posedge) MacUnit_32 mac_unit ( // @[PE.scala:64:24] .clock (clock), .reset (reset), .io_in_a (io_in_a_0), // @[PE.scala:31:7] .io_in_b (io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE_2 : _mac_unit_io_in_b_WIRE_3), // @[PE.scala:31:7, :119:30, :121:{24,38}, :127:{24,38}] .io_in_c (io_in_b_0), // @[PE.scala:31:7] .io_out_d (io_out_b_0) ); // @[PE.scala:64:24] assign io_out_a = io_out_a_0; // @[PE.scala:31:7] assign io_out_b = io_out_b_0; // @[PE.scala:31:7] assign io_out_c = io_out_c_0; // @[PE.scala:31:7] assign io_out_control_dataflow = io_out_control_dataflow_0; // @[PE.scala:31:7] assign io_out_control_propagate = io_out_control_propagate_0; // @[PE.scala:31:7] assign io_out_control_shift = io_out_control_shift_0; // @[PE.scala:31:7] assign io_out_id = io_out_id_0; // @[PE.scala:31:7] assign io_out_last = io_out_last_0; // @[PE.scala:31:7] assign io_out_valid = io_out_valid_0; // @[PE.scala:31:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File util.scala: //**************************************************************************** // Copyright (c) 2015 - 2019, The Regents of the University of California (Regents). // All Rights Reserved. See LICENSE and LICENSE.SiFive for license details. //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ // Utility Functions //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ package boom.v3.util import chisel3._ import chisel3.util._ import freechips.rocketchip.rocket.Instructions._ import freechips.rocketchip.rocket._ import freechips.rocketchip.util.{Str} import org.chipsalliance.cde.config.{Parameters} import freechips.rocketchip.tile.{TileKey} import boom.v3.common.{MicroOp} import boom.v3.exu.{BrUpdateInfo} / * Object to XOR fold a input register of fullLength into a compressedLength. / object Fold { def apply(input: UInt, compressedLength: Int, fullLength: Int): UInt = { val clen = compressedLength val hlen = fullLength if (hlen <= clen) { input } else { var res = 0.U(clen.W) var remaining = input.asUInt for (i <- 0 to hlen-1 by clen) { val len = if (i + clen > hlen ) (hlen - i) else clen require(len > 0) res = res(clen-1,0) ^ remaining(len-1,0) remaining = remaining >> len.U } res } } } /* * Object to check if MicroOp was killed due to a branch mispredict. * Uses "Fast" branch masks / object IsKilledByBranch { def apply(brupdate: BrUpdateInfo, uop: MicroOp): Bool = { return maskMatch(brupdate.b1.mispredict_mask, uop.br_mask) } def apply(brupdate: BrUpdateInfo, uop_mask: UInt): Bool = { return maskMatch(brupdate.b1.mispredict_mask, uop_mask) } } /* * Object to return new MicroOp with a new BR mask given a MicroOp mask * and old BR mask. / object GetNewUopAndBrMask { def apply(uop: MicroOp, brupdate: BrUpdateInfo) (implicit p: Parameters): MicroOp = { val newuop = WireInit(uop) newuop.br_mask := uop.br_mask & ~brupdate.b1.resolve_mask newuop } } /* * Object to return a BR mask given a MicroOp mask and old BR mask. / object GetNewBrMask { def apply(brupdate: BrUpdateInfo, uop: MicroOp): UInt = { return uop.br_mask & ~brupdate.b1.resolve_mask } def apply(brupdate: BrUpdateInfo, br_mask: UInt): UInt = { return br_mask & ~brupdate.b1.resolve_mask } } object UpdateBrMask { def apply(brupdate: BrUpdateInfo, uop: MicroOp): MicroOp = { val out = WireInit(uop) out.br_mask := GetNewBrMask(brupdate, uop) out } def apply[T <: boom.v3.common.HasBoomUOP](brupdate: BrUpdateInfo, bundle: T): T = { val out = WireInit(bundle) out.uop.br_mask := GetNewBrMask(brupdate, bundle.uop.br_mask) out } def apply[T <: boom.v3.common.HasBoomUOP](brupdate: BrUpdateInfo, bundle: Valid[T]): Valid[T] = { val out = WireInit(bundle) out.bits.uop.br_mask := GetNewBrMask(brupdate, bundle.bits.uop.br_mask) out.valid := bundle.valid && !IsKilledByBranch(brupdate, bundle.bits.uop.br_mask) out } } /* * Object to check if at least 1 bit matches in two masks / object maskMatch { def apply(msk1: UInt, msk2: UInt): Bool = (msk1 & msk2) =/= 0.U } /* * Object to clear one bit in a mask given an index / object clearMaskBit { def apply(msk: UInt, idx: UInt): UInt = (msk & ~(1.U << idx))(msk.getWidth-1, 0) } /* * Object to shift a register over by one bit and concat a new one / object PerformShiftRegister { def apply(reg_val: UInt, new_bit: Bool): UInt = { reg_val := Cat(reg_val(reg_val.getWidth-1, 0).asUInt, new_bit.asUInt).asUInt reg_val } } /* * Object to shift a register over by one bit, wrapping the top bit around to the bottom * (XOR'ed with a new-bit), and evicting a bit at index HLEN. * This is used to simulate a longer HLEN-width shift register that is folded * down to a compressed CLEN. / object PerformCircularShiftRegister { def apply(csr: UInt, new_bit: Bool, evict_bit: Bool, hlen: Int, clen: Int): UInt = { val carry = csr(clen-1) val newval = Cat(csr, new_bit ^ carry) ^ (evict_bit << (hlen % clen).U) newval } } /* * Object to increment an input value, wrapping it if * necessary. / object WrapAdd { // "n" is the number of increments, so we wrap at n-1. def apply(value: UInt, amt: UInt, n: Int): UInt = { if (isPow2(n)) { (value + amt)(log2Ceil(n)-1,0) } else { val sum = Cat(0.U(1.W), value) + Cat(0.U(1.W), amt) Mux(sum >= n.U, sum - n.U, sum) } } } /* * Object to decrement an input value, wrapping it if * necessary. / object WrapSub { // "n" is the number of increments, so we wrap to n-1. def apply(value: UInt, amt: Int, n: Int): UInt = { if (isPow2(n)) { (value - amt.U)(log2Ceil(n)-1,0) } else { val v = Cat(0.U(1.W), value) val b = Cat(0.U(1.W), amt.U) Mux(value >= amt.U, value - amt.U, n.U - amt.U + value) } } } /* * Object to increment an input value, wrapping it if * necessary. / object WrapInc { // "n" is the number of increments, so we wrap at n-1. def apply(value: UInt, n: Int): UInt = { if (isPow2(n)) { (value + 1.U)(log2Ceil(n)-1,0) } else { val wrap = (value === (n-1).U) Mux(wrap, 0.U, value + 1.U) } } } /* * Object to decrement an input value, wrapping it if * necessary. / object WrapDec { // "n" is the number of increments, so we wrap at n-1. def apply(value: UInt, n: Int): UInt = { if (isPow2(n)) { (value - 1.U)(log2Ceil(n)-1,0) } else { val wrap = (value === 0.U) Mux(wrap, (n-1).U, value - 1.U) } } } /* * Object to mask off lower bits of a PC to align to a "b" * Byte boundary. / object AlignPCToBoundary { def apply(pc: UInt, b: Int): UInt = { // Invert for scenario where pc longer than b // (which would clear all bits above size(b)). ~(~pc \| (b-1).U) } } /* * Object to rotate a signal left by one / object RotateL1 { def apply(signal: UInt): UInt = { val w = signal.getWidth val out = Cat(signal(w-2,0), signal(w-1)) return out } } /* * Object to sext a value to a particular length. / object Sext { def apply(x: UInt, length: Int): UInt = { if (x.getWidth == length) return x else return Cat(Fill(length-x.getWidth, x(x.getWidth-1)), x) } } /* * Object to translate from BOOM's special "packed immediate" to a 32b signed immediate * Asking for U-type gives it shifted up 12 bits. / object ImmGen { import boom.v3.common.{LONGEST_IMM_SZ, IS_B, IS_I, IS_J, IS_S, IS_U} def apply(ip: UInt, isel: UInt): SInt = { val sign = ip(LONGEST_IMM_SZ-1).asSInt val i30_20 = Mux(isel === IS_U, ip(18,8).asSInt, sign) val i19_12 = Mux(isel === IS_U \|\| isel === IS_J, ip(7,0).asSInt, sign) val i11 = Mux(isel === IS_U, 0.S, Mux(isel === IS_J \|\| isel === IS_B, ip(8).asSInt, sign)) val i10_5 = Mux(isel === IS_U, 0.S, ip(18,14).asSInt) val i4_1 = Mux(isel === IS_U, 0.S, ip(13,9).asSInt) val i0 = Mux(isel === IS_S \|\| isel === IS_I, ip(8).asSInt, 0.S) return Cat(sign, i30_20, i19_12, i11, i10_5, i4_1, i0).asSInt } } /* * Object to get the FP rounding mode out of a packed immediate. / object ImmGenRm { def apply(ip: UInt): UInt = { return ip(2,0) } } /* * Object to get the FP function fype from a packed immediate. * Note: only works if !(IS_B or IS_S) / object ImmGenTyp { def apply(ip: UInt): UInt = { return ip(9,8) } } /* * Object to see if an instruction is a JALR. / object DebugIsJALR { def apply(inst: UInt): Bool = { // TODO Chisel not sure why this won't compile // val is_jalr = rocket.DecodeLogic(inst, List(Bool(false)), // Array( // JALR -> Bool(true))) inst(6,0) === "b1100111".U } } /* * Object to take an instruction and output its branch or jal target. Only used * for a debug assert (no where else would we jump straight from instruction * bits to a target). / object DebugGetBJImm { def apply(inst: UInt): UInt = { // TODO Chisel not sure why this won't compile //val csignals = //rocket.DecodeLogic(inst, // List(Bool(false), Bool(false)), // Array( // BEQ -> List(Bool(true ), Bool(false)), // BNE -> List(Bool(true ), Bool(false)), // BGE -> List(Bool(true ), Bool(false)), // BGEU -> List(Bool(true ), Bool(false)), // BLT -> List(Bool(true ), Bool(false)), // BLTU -> List(Bool(true ), Bool(false)) // )) //val is_br :: nothing :: Nil = csignals val is_br = (inst(6,0) === "b1100011".U) val br_targ = Cat(Fill(12, inst(31)), Fill(8,inst(31)), inst(7), inst(30,25), inst(11,8), 0.U(1.W)) val jal_targ= Cat(Fill(12, inst(31)), inst(19,12), inst(20), inst(30,25), inst(24,21), 0.U(1.W)) Mux(is_br, br_targ, jal_targ) } } /* * Object to return the lowest bit position after the head. / object AgePriorityEncoder { def apply(in: Seq[Bool], head: UInt): UInt = { val n = in.size val width = log2Ceil(in.size) val n_padded = 1 << width val temp_vec = (0 until n_padded).map(i => if (i < n) in(i) && i.U >= head else false.B) ++ in val idx = PriorityEncoder(temp_vec) idx(width-1, 0) //discard msb } } /* * Object to determine whether queue * index i0 is older than index i1. / object IsOlder { def apply(i0: UInt, i1: UInt, head: UInt) = ((i0 < i1) ^ (i0 < head) ^ (i1 < head)) } /* * Set all bits at or below the highest order '1'. / object MaskLower { def apply(in: UInt) = { val n = in.getWidth (0 until n).map(i => in >> i.U).reduce(_\|_) } } /* * Set all bits at or above the lowest order '1'. / object MaskUpper { def apply(in: UInt) = { val n = in.getWidth (0 until n).map(i => (in << i.U)(n-1,0)).reduce(_\|_) } } /* * Transpose a matrix of Chisel Vecs. / object Transpose { def apply[T <: chisel3.Data](in: Vec[Vec[T]]) = { val n = in(0).size VecInit((0 until n).map(i => VecInit(in.map(row => row(i))))) } } /* * N-wide one-hot priority encoder. / object SelectFirstN { def apply(in: UInt, n: Int) = { val sels = Wire(Vec(n, UInt(in.getWidth.W))) var mask = in for (i <- 0 until n) { sels(i) := PriorityEncoderOH(mask) mask = mask & ~sels(i) } sels } } /* * Connect the first k of n valid input interfaces to k output interfaces. / class Compactor[T <: chisel3.Data](n: Int, k: Int, gen: T) extends Module { require(n >= k) val io = IO(new Bundle { val in = Vec(n, Flipped(DecoupledIO(gen))) val out = Vec(k, DecoupledIO(gen)) }) if (n == k) { io.out <> io.in } else { val counts = io.in.map(_.valid).scanLeft(1.U(k.W)) ((c,e) => Mux(e, (c<<1)(k-1,0), c)) val sels = Transpose(VecInit(counts map (c => VecInit(c.asBools)))) map (col => (col zip io.in.map(_.valid)) map {case (c,v) => c && v}) val in_readys = counts map (row => (row.asBools zip io.out.map(_.ready)) map {case (c,r) => c && r} reduce (_\|\|_)) val out_valids = sels map (col => col.reduce(_\|\|_)) val out_data = sels map (s => Mux1H(s, io.in.map(_.bits))) in_readys zip io.in foreach {case (r,i) => i.ready := r} out_valids zip out_data zip io.out foreach {case ((v,d),o) => o.valid := v; o.bits := d} } } /* * Create a queue that can be killed with a branch kill signal. * Assumption: enq.valid only high if not killed by branch (so don't check IsKilled on io.enq). / class BranchKillableQueue[T <: boom.v3.common.HasBoomUOP](gen: T, entries: Int, flush_fn: boom.v3.common.MicroOp => Bool = u => true.B, flow: Boolean = true) (implicit p: org.chipsalliance.cde.config.Parameters) extends boom.v3.common.BoomModule()(p) with boom.v3.common.HasBoomCoreParameters { val io = IO(new Bundle { val enq = Flipped(Decoupled(gen)) val deq = Decoupled(gen) val brupdate = Input(new BrUpdateInfo()) val flush = Input(Bool()) val empty = Output(Bool()) val count = Output(UInt(log2Ceil(entries).W)) }) val ram = Mem(entries, gen) val valids = RegInit(VecInit(Seq.fill(entries) {false.B})) val uops = Reg(Vec(entries, new MicroOp)) val enq_ptr = Counter(entries) val deq_ptr = Counter(entries) val maybe_full = RegInit(false.B) val ptr_match = enq_ptr.value === deq_ptr.value io.empty := ptr_match && !maybe_full val full = ptr_match && maybe_full val do_enq = WireInit(io.enq.fire) val do_deq = WireInit((io.deq.ready \|\| !valids(deq_ptr.value)) && !io.empty) for (i <- 0 until entries) { val mask = uops(i).br_mask val uop = uops(i) valids(i) := valids(i) && !IsKilledByBranch(io.brupdate, mask) && !(io.flush && flush_fn(uop)) when (valids(i)) { uops(i).br_mask := GetNewBrMask(io.brupdate, mask) } } when (do_enq) { ram(enq_ptr.value) := io.enq.bits valids(enq_ptr.value) := true.B //!IsKilledByBranch(io.brupdate, io.enq.bits.uop) uops(enq_ptr.value) := io.enq.bits.uop uops(enq_ptr.value).br_mask := GetNewBrMask(io.brupdate, io.enq.bits.uop) enq_ptr.inc() } when (do_deq) { valids(deq_ptr.value) := false.B deq_ptr.inc() } when (do_enq =/= do_deq) { maybe_full := do_enq } io.enq.ready := !full val out = Wire(gen) out := ram(deq_ptr.value) out.uop := uops(deq_ptr.value) io.deq.valid := !io.empty && valids(deq_ptr.value) && !IsKilledByBranch(io.brupdate, out.uop) && !(io.flush && flush_fn(out.uop)) io.deq.bits := out io.deq.bits.uop.br_mask := GetNewBrMask(io.brupdate, out.uop) // For flow queue behavior. if (flow) { when (io.empty) { io.deq.valid := io.enq.valid //&& !IsKilledByBranch(io.brupdate, io.enq.bits.uop) io.deq.bits := io.enq.bits io.deq.bits.uop.br_mask := GetNewBrMask(io.brupdate, io.enq.bits.uop) do_deq := false.B when (io.deq.ready) { do_enq := false.B } } } private val ptr_diff = enq_ptr.value - deq_ptr.value if (isPow2(entries)) { io.count := Cat(maybe_full && ptr_match, ptr_diff) } else { io.count := Mux(ptr_match, Mux(maybe_full, entries.asUInt, 0.U), Mux(deq_ptr.value > enq_ptr.value, entries.asUInt + ptr_diff, ptr_diff)) } } // ------------------------------------------ // Printf helper functions // ------------------------------------------ object BoolToChar { /* * Take in a Chisel Bool and convert it into a Str * based on the Chars given * * @param c_bool Chisel Bool * @param trueChar Scala Char if bool is true * @param falseChar Scala Char if bool is false * @return UInt ASCII Char for "trueChar" or "falseChar" / def apply(c_bool: Bool, trueChar: Char, falseChar: Char = '-'): UInt = { Mux(c_bool, Str(trueChar), Str(falseChar)) } } object CfiTypeToChars { /* * Get a Vec of Strs that can be used for printing * * @param cfi_type specific cfi type * @return Vec of Strs (must be indexed to get specific char) / def apply(cfi_type: UInt) = { val strings = Seq("----", "BR ", "JAL ", "JALR") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(cfi_type) } } object BpdTypeToChars { /* * Get a Vec of Strs that can be used for printing * * @param bpd_type specific bpd type * @return Vec of Strs (must be indexed to get specific char) / def apply(bpd_type: UInt) = { val strings = Seq("BR ", "JUMP", "----", "RET ", "----", "CALL", "----", "----") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(bpd_type) } } object RobTypeToChars { /* * Get a Vec of Strs that can be used for printing * * @param rob_type specific rob type * @return Vec of Strs (must be indexed to get specific char) / def apply(rob_type: UInt) = { val strings = Seq("RST", "NML", "RBK", " WT") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(rob_type) } } object XRegToChars { /* * Get a Vec of Strs that can be used for printing * * @param xreg specific register number * @return Vec of Strs (must be indexed to get specific char) / def apply(xreg: UInt) = { val strings = Seq(" x0", " ra", " sp", " gp", " tp", " t0", " t1", " t2", " s0", " s1", " a0", " a1", " a2", " a3", " a4", " a5", " a6", " a7", " s2", " s3", " s4", " s5", " s6", " s7", " s8", " s9", "s10", "s11", " t3", " t4", " t5", " t6") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(xreg) } } object FPRegToChars { /* * Get a Vec of Strs that can be used for printing * * @param fpreg specific register number * @return Vec of Strs (must be indexed to get specific char) / def apply(fpreg: UInt) = { val strings = Seq(" ft0", " ft1", " ft2", " ft3", " ft4", " ft5", " ft6", " ft7", " fs0", " fs1", " fa0", " fa1", " fa2", " fa3", " fa4", " fa5", " fa6", " fa7", " fs2", " fs3", " fs4", " fs5", " fs6", " fs7", " fs8", " fs9", "fs10", "fs11", " ft8", " ft9", "ft10", "ft11") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(fpreg) } } object BoomCoreStringPrefix { /* * Add prefix to BOOM strings (currently only adds the hartId) * * @param strs list of strings * @return String combining the list with the prefix per line / def apply(strs: String)(implicit p: Parameters) = { val prefix = "[C" + s"${p(TileKey).tileId}" + "] " strs.map(str => prefix + str + "\n").mkString("") } } File consts.scala: //**************************************************************************** // Copyright (c) 2011 - 2018, The Regents of the University of California (Regents). // All Rights Reserved. See LICENSE and LICENSE.SiFive for license details. //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ // RISCV Processor Constants //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ package boom.v3.common.constants import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util.Str import freechips.rocketchip.rocket.RVCExpander / * Mixin for issue queue types / trait IQType { val IQT_SZ = 3 val IQT_INT = 1.U(IQT_SZ.W) val IQT_MEM = 2.U(IQT_SZ.W) val IQT_FP = 4.U(IQT_SZ.W) val IQT_MFP = 6.U(IQT_SZ.W) } /* * Mixin for scalar operation constants / trait ScalarOpConstants { val X = BitPat("b?") val Y = BitPat("b1") val N = BitPat("b0") //********************************* // Extra Constants // Which branch predictor predicted us val BSRC_SZ = 2 val BSRC_1 = 0.U(BSRC_SZ.W) // 1-cycle branch pred val BSRC_2 = 1.U(BSRC_SZ.W) // 2-cycle branch pred val BSRC_3 = 2.U(BSRC_SZ.W) // 3-cycle branch pred val BSRC_C = 3.U(BSRC_SZ.W) // core branch resolution //******************************** // Control Signals // CFI types val CFI_SZ = 3 val CFI_X = 0.U(CFI_SZ.W) // Not a CFI instruction val CFI_BR = 1.U(CFI_SZ.W) // Branch val CFI_JAL = 2.U(CFI_SZ.W) // JAL val CFI_JALR = 3.U(CFI_SZ.W) // JALR // PC Select Signal val PC_PLUS4 = 0.U(2.W) // PC + 4 val PC_BRJMP = 1.U(2.W) // brjmp_target val PC_JALR = 2.U(2.W) // jump_reg_target // Branch Type val BR_N = 0.U(4.W) // Next val BR_NE = 1.U(4.W) // Branch on NotEqual val BR_EQ = 2.U(4.W) // Branch on Equal val BR_GE = 3.U(4.W) // Branch on Greater/Equal val BR_GEU = 4.U(4.W) // Branch on Greater/Equal Unsigned val BR_LT = 5.U(4.W) // Branch on Less Than val BR_LTU = 6.U(4.W) // Branch on Less Than Unsigned val BR_J = 7.U(4.W) // Jump val BR_JR = 8.U(4.W) // Jump Register // RS1 Operand Select Signal val OP1_RS1 = 0.U(2.W) // Register Source #1 val OP1_ZERO= 1.U(2.W) val OP1_PC = 2.U(2.W) val OP1_X = BitPat("b??") // RS2 Operand Select Signal val OP2_RS2 = 0.U(3.W) // Register Source #2 val OP2_IMM = 1.U(3.W) // immediate val OP2_ZERO= 2.U(3.W) // constant 0 val OP2_NEXT= 3.U(3.W) // constant 2/4 (for PC+2/4) val OP2_IMMC= 4.U(3.W) // for CSR imm found in RS1 val OP2_X = BitPat("b???") // Register File Write Enable Signal val REN_0 = false.B val REN_1 = true.B // Is 32b Word or 64b Doubldword? val SZ_DW = 1 val DW_X = true.B // Bool(xLen==64) val DW_32 = false.B val DW_64 = true.B val DW_XPR = true.B // Bool(xLen==64) // Memory Enable Signal val MEN_0 = false.B val MEN_1 = true.B val MEN_X = false.B // Immediate Extend Select val IS_I = 0.U(3.W) // I-Type (LD,ALU) val IS_S = 1.U(3.W) // S-Type (ST) val IS_B = 2.U(3.W) // SB-Type (BR) val IS_U = 3.U(3.W) // U-Type (LUI/AUIPC) val IS_J = 4.U(3.W) // UJ-Type (J/JAL) val IS_X = BitPat("b???") // Decode Stage Control Signals val RT_FIX = 0.U(2.W) val RT_FLT = 1.U(2.W) val RT_PAS = 3.U(2.W) // pass-through (prs1 := lrs1, etc) val RT_X = 2.U(2.W) // not-a-register (but shouldn't get a busy-bit, etc.) // TODO rename RT_NAR // Micro-op opcodes // TODO change micro-op opcodes into using enum val UOPC_SZ = 7 val uopX = BitPat.dontCare(UOPC_SZ) val uopNOP = 0.U(UOPC_SZ.W) val uopLD = 1.U(UOPC_SZ.W) val uopSTA = 2.U(UOPC_SZ.W) // store address generation val uopSTD = 3.U(UOPC_SZ.W) // store data generation val uopLUI = 4.U(UOPC_SZ.W) val uopADDI = 5.U(UOPC_SZ.W) val uopANDI = 6.U(UOPC_SZ.W) val uopORI = 7.U(UOPC_SZ.W) val uopXORI = 8.U(UOPC_SZ.W) val uopSLTI = 9.U(UOPC_SZ.W) val uopSLTIU= 10.U(UOPC_SZ.W) val uopSLLI = 11.U(UOPC_SZ.W) val uopSRAI = 12.U(UOPC_SZ.W) val uopSRLI = 13.U(UOPC_SZ.W) val uopSLL = 14.U(UOPC_SZ.W) val uopADD = 15.U(UOPC_SZ.W) val uopSUB = 16.U(UOPC_SZ.W) val uopSLT = 17.U(UOPC_SZ.W) val uopSLTU = 18.U(UOPC_SZ.W) val uopAND = 19.U(UOPC_SZ.W) val uopOR = 20.U(UOPC_SZ.W) val uopXOR = 21.U(UOPC_SZ.W) val uopSRA = 22.U(UOPC_SZ.W) val uopSRL = 23.U(UOPC_SZ.W) val uopBEQ = 24.U(UOPC_SZ.W) val uopBNE = 25.U(UOPC_SZ.W) val uopBGE = 26.U(UOPC_SZ.W) val uopBGEU = 27.U(UOPC_SZ.W) val uopBLT = 28.U(UOPC_SZ.W) val uopBLTU = 29.U(UOPC_SZ.W) val uopCSRRW= 30.U(UOPC_SZ.W) val uopCSRRS= 31.U(UOPC_SZ.W) val uopCSRRC= 32.U(UOPC_SZ.W) val uopCSRRWI=33.U(UOPC_SZ.W) val uopCSRRSI=34.U(UOPC_SZ.W) val uopCSRRCI=35.U(UOPC_SZ.W) val uopJ = 36.U(UOPC_SZ.W) val uopJAL = 37.U(UOPC_SZ.W) val uopJALR = 38.U(UOPC_SZ.W) val uopAUIPC= 39.U(UOPC_SZ.W) //val uopSRET = 40.U(UOPC_SZ.W) val uopCFLSH= 41.U(UOPC_SZ.W) val uopFENCE= 42.U(UOPC_SZ.W) val uopADDIW= 43.U(UOPC_SZ.W) val uopADDW = 44.U(UOPC_SZ.W) val uopSUBW = 45.U(UOPC_SZ.W) val uopSLLIW= 46.U(UOPC_SZ.W) val uopSLLW = 47.U(UOPC_SZ.W) val uopSRAIW= 48.U(UOPC_SZ.W) val uopSRAW = 49.U(UOPC_SZ.W) val uopSRLIW= 50.U(UOPC_SZ.W) val uopSRLW = 51.U(UOPC_SZ.W) val uopMUL = 52.U(UOPC_SZ.W) val uopMULH = 53.U(UOPC_SZ.W) val uopMULHU= 54.U(UOPC_SZ.W) val uopMULHSU=55.U(UOPC_SZ.W) val uopMULW = 56.U(UOPC_SZ.W) val uopDIV = 57.U(UOPC_SZ.W) val uopDIVU = 58.U(UOPC_SZ.W) val uopREM = 59.U(UOPC_SZ.W) val uopREMU = 60.U(UOPC_SZ.W) val uopDIVW = 61.U(UOPC_SZ.W) val uopDIVUW= 62.U(UOPC_SZ.W) val uopREMW = 63.U(UOPC_SZ.W) val uopREMUW= 64.U(UOPC_SZ.W) val uopFENCEI = 65.U(UOPC_SZ.W) // = 66.U(UOPC_SZ.W) val uopAMO_AG = 67.U(UOPC_SZ.W) // AMO-address gen (use normal STD for datagen) val uopFMV_W_X = 68.U(UOPC_SZ.W) val uopFMV_D_X = 69.U(UOPC_SZ.W) val uopFMV_X_W = 70.U(UOPC_SZ.W) val uopFMV_X_D = 71.U(UOPC_SZ.W) val uopFSGNJ_S = 72.U(UOPC_SZ.W) val uopFSGNJ_D = 73.U(UOPC_SZ.W) val uopFCVT_S_D = 74.U(UOPC_SZ.W) val uopFCVT_D_S = 75.U(UOPC_SZ.W) val uopFCVT_S_X = 76.U(UOPC_SZ.W) val uopFCVT_D_X = 77.U(UOPC_SZ.W) val uopFCVT_X_S = 78.U(UOPC_SZ.W) val uopFCVT_X_D = 79.U(UOPC_SZ.W) val uopCMPR_S = 80.U(UOPC_SZ.W) val uopCMPR_D = 81.U(UOPC_SZ.W) val uopFCLASS_S = 82.U(UOPC_SZ.W) val uopFCLASS_D = 83.U(UOPC_SZ.W) val uopFMINMAX_S = 84.U(UOPC_SZ.W) val uopFMINMAX_D = 85.U(UOPC_SZ.W) // = 86.U(UOPC_SZ.W) val uopFADD_S = 87.U(UOPC_SZ.W) val uopFSUB_S = 88.U(UOPC_SZ.W) val uopFMUL_S = 89.U(UOPC_SZ.W) val uopFADD_D = 90.U(UOPC_SZ.W) val uopFSUB_D = 91.U(UOPC_SZ.W) val uopFMUL_D = 92.U(UOPC_SZ.W) val uopFMADD_S = 93.U(UOPC_SZ.W) val uopFMSUB_S = 94.U(UOPC_SZ.W) val uopFNMADD_S = 95.U(UOPC_SZ.W) val uopFNMSUB_S = 96.U(UOPC_SZ.W) val uopFMADD_D = 97.U(UOPC_SZ.W) val uopFMSUB_D = 98.U(UOPC_SZ.W) val uopFNMADD_D = 99.U(UOPC_SZ.W) val uopFNMSUB_D = 100.U(UOPC_SZ.W) val uopFDIV_S = 101.U(UOPC_SZ.W) val uopFDIV_D = 102.U(UOPC_SZ.W) val uopFSQRT_S = 103.U(UOPC_SZ.W) val uopFSQRT_D = 104.U(UOPC_SZ.W) val uopWFI = 105.U(UOPC_SZ.W) // pass uop down the CSR pipeline val uopERET = 106.U(UOPC_SZ.W) // pass uop down the CSR pipeline, also is ERET val uopSFENCE = 107.U(UOPC_SZ.W) val uopROCC = 108.U(UOPC_SZ.W) val uopMOV = 109.U(UOPC_SZ.W) // conditional mov decoded from "add rd, x0, rs2" // The Bubble Instruction (Machine generated NOP) // Insert (XOR x0,x0,x0) which is different from software compiler // generated NOPs which are (ADDI x0, x0, 0). // Reasoning for this is to let visualizers and stat-trackers differentiate // between software NOPs and machine-generated Bubbles in the pipeline. val BUBBLE = (0x4033).U(32.W) def NullMicroOp()(implicit p: Parameters): boom.v3.common.MicroOp = { val uop = Wire(new boom.v3.common.MicroOp) uop := DontCare // Overridden in the following lines uop.uopc := uopNOP // maybe not required, but helps on asserts that try to catch spurious behavior uop.bypassable := false.B uop.fp_val := false.B uop.uses_stq := false.B uop.uses_ldq := false.B uop.pdst := 0.U uop.dst_rtype := RT_X val cs = Wire(new boom.v3.common.CtrlSignals()) cs := DontCare // Overridden in the following lines cs.br_type := BR_N cs.csr_cmd := freechips.rocketchip.rocket.CSR.N cs.is_load := false.B cs.is_sta := false.B cs.is_std := false.B uop.ctrl := cs uop } } / * Mixin for RISCV constants / trait RISCVConstants { // abstract out instruction decode magic numbers val RD_MSB = 11 val RD_LSB = 7 val RS1_MSB = 19 val RS1_LSB = 15 val RS2_MSB = 24 val RS2_LSB = 20 val RS3_MSB = 31 val RS3_LSB = 27 val CSR_ADDR_MSB = 31 val CSR_ADDR_LSB = 20 val CSR_ADDR_SZ = 12 // location of the fifth bit in the shamt (for checking for illegal ops for SRAIW,etc.) val SHAMT_5_BIT = 25 val LONGEST_IMM_SZ = 20 val X0 = 0.U val RA = 1.U // return address register // memory consistency model // The C/C++ atomics MCM requires that two loads to the same address maintain program order. // The Cortex A9 does NOT enforce load/load ordering (which leads to buggy behavior). val MCM_ORDER_DEPENDENT_LOADS = true val jal_opc = (0x6f).U val jalr_opc = (0x67).U def GetUop(inst: UInt): UInt = inst(6,0) def GetRd (inst: UInt): UInt = inst(RD_MSB,RD_LSB) def GetRs1(inst: UInt): UInt = inst(RS1_MSB,RS1_LSB) def ExpandRVC(inst: UInt)(implicit p: Parameters): UInt = { val rvc_exp = Module(new RVCExpander) rvc_exp.io.in := inst Mux(rvc_exp.io.rvc, rvc_exp.io.out.bits, inst) } // Note: Accepts only EXPANDED rvc instructions def ComputeBranchTarget(pc: UInt, inst: UInt, xlen: Int)(implicit p: Parameters): UInt = { val b_imm32 = Cat(Fill(20,inst(31)), inst(7), inst(30,25), inst(11,8), 0.U(1.W)) ((pc.asSInt + b_imm32.asSInt).asSInt & (-2).S).asUInt } // Note: Accepts only EXPANDED rvc instructions def ComputeJALTarget(pc: UInt, inst: UInt, xlen: Int)(implicit p: Parameters): UInt = { val j_imm32 = Cat(Fill(12,inst(31)), inst(19,12), inst(20), inst(30,25), inst(24,21), 0.U(1.W)) ((pc.asSInt + j_imm32.asSInt).asSInt & (-2).S).asUInt } // Note: Accepts only EXPANDED rvc instructions def GetCfiType(inst: UInt)(implicit p: Parameters): UInt = { val bdecode = Module(new boom.v3.exu.BranchDecode) bdecode.io.inst := inst bdecode.io.pc := 0.U bdecode.io.out.cfi_type } } /* * Mixin for exception cause constants / trait ExcCauseConstants { // a memory disambigious misspeculation occurred val MINI_EXCEPTION_MEM_ORDERING = 16.U val MINI_EXCEPTION_CSR_REPLAY = 17.U require (!freechips.rocketchip.rocket.Causes.all.contains(16)) require (!freechips.rocketchip.rocket.Causes.all.contains(17)) } File issue-slot.scala: //*************************************************************************** // Copyright (c) 2015 - 2018, The Regents of the University of California (Regents). // All Rights Reserved. See LICENSE and LICENSE.SiFive for license details. //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ // RISCV Processor Issue Slot Logic //-------------------------------------------------------------------------- //------------------------------------------------------------------------------ // // Note: stores (and AMOs) are "broken down" into 2 uops, but stored within a single issue-slot. // TODO XXX make a separate issueSlot for MemoryIssueSlots, and only they break apart stores. // TODO Disable ldspec for FP queue. package boom.v3.exu import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.Parameters import boom.v3.common._ import boom.v3.util._ import FUConstants._ / * IO bundle to interact with Issue slot * * @param numWakeupPorts number of wakeup ports for the slot / class IssueSlotIO(val numWakeupPorts: Int)(implicit p: Parameters) extends BoomBundle { val valid = Output(Bool()) val will_be_valid = Output(Bool()) // TODO code review, do we need this signal so explicitely? val request = Output(Bool()) val request_hp = Output(Bool()) val grant = Input(Bool()) val brupdate = Input(new BrUpdateInfo()) val kill = Input(Bool()) // pipeline flush val clear = Input(Bool()) // entry being moved elsewhere (not mutually exclusive with grant) val ldspec_miss = Input(Bool()) // Previous cycle's speculative load wakeup was mispredicted. val wakeup_ports = Flipped(Vec(numWakeupPorts, Valid(new IqWakeup(maxPregSz)))) val pred_wakeup_port = Flipped(Valid(UInt(log2Ceil(ftqSz).W))) val spec_ld_wakeup = Flipped(Vec(memWidth, Valid(UInt(width=maxPregSz.W)))) val in_uop = Flipped(Valid(new MicroOp())) // if valid, this WILL overwrite an entry! val out_uop = Output(new MicroOp()) // the updated slot uop; will be shifted upwards in a collasping queue. val uop = Output(new MicroOp()) // the current Slot's uop. Sent down the pipeline when issued. val debug = { val result = new Bundle { val p1 = Bool() val p2 = Bool() val p3 = Bool() val ppred = Bool() val state = UInt(width=2.W) } Output(result) } } /* * Single issue slot. Holds a uop within the issue queue * * @param numWakeupPorts number of wakeup ports / class IssueSlot(val numWakeupPorts: Int)(implicit p: Parameters) extends BoomModule with IssueUnitConstants { val io = IO(new IssueSlotIO(numWakeupPorts)) // slot invalid? // slot is valid, holding 1 uop // slot is valid, holds 2 uops (like a store) def is_invalid = state === s_invalid def is_valid = state =/= s_invalid val next_state = Wire(UInt()) // the next state of this slot (which might then get moved to a new slot) val next_uopc = Wire(UInt()) // the next uopc of this slot (which might then get moved to a new slot) val next_lrs1_rtype = Wire(UInt()) // the next reg type of this slot (which might then get moved to a new slot) val next_lrs2_rtype = Wire(UInt()) // the next reg type of this slot (which might then get moved to a new slot) val state = RegInit(s_invalid) val p1 = RegInit(false.B) val p2 = RegInit(false.B) val p3 = RegInit(false.B) val ppred = RegInit(false.B) // Poison if woken up by speculative load. // Poison lasts 1 cycle (as ldMiss will come on the next cycle). // SO if poisoned is true, set it to false! val p1_poisoned = RegInit(false.B) val p2_poisoned = RegInit(false.B) p1_poisoned := false.B p2_poisoned := false.B val next_p1_poisoned = Mux(io.in_uop.valid, io.in_uop.bits.iw_p1_poisoned, p1_poisoned) val next_p2_poisoned = Mux(io.in_uop.valid, io.in_uop.bits.iw_p2_poisoned, p2_poisoned) val slot_uop = RegInit(NullMicroOp) val next_uop = Mux(io.in_uop.valid, io.in_uop.bits, slot_uop) //----------------------------------------------------------------------------- // next slot state computation // compute the next state for THIS entry slot (in a collasping queue, the // current uop may get moved elsewhere, and a new uop can enter when (io.kill) { state := s_invalid } .elsewhen (io.in_uop.valid) { state := io.in_uop.bits.iw_state } .elsewhen (io.clear) { state := s_invalid } .otherwise { state := next_state } //----------------------------------------------------------------------------- // "update" state // compute the next state for the micro-op in this slot. This micro-op may // be moved elsewhere, so the "next_state" travels with it. // defaults next_state := state next_uopc := slot_uop.uopc next_lrs1_rtype := slot_uop.lrs1_rtype next_lrs2_rtype := slot_uop.lrs2_rtype when (io.kill) { next_state := s_invalid } .elsewhen ((io.grant && (state === s_valid_1)) \|\| (io.grant && (state === s_valid_2) && p1 && p2 && ppred)) { // try to issue this uop. when (!(io.ldspec_miss && (p1_poisoned \|\| p2_poisoned))) { next_state := s_invalid } } .elsewhen (io.grant && (state === s_valid_2)) { when (!(io.ldspec_miss && (p1_poisoned \|\| p2_poisoned))) { next_state := s_valid_1 when (p1) { slot_uop.uopc := uopSTD next_uopc := uopSTD slot_uop.lrs1_rtype := RT_X next_lrs1_rtype := RT_X } .otherwise { slot_uop.lrs2_rtype := RT_X next_lrs2_rtype := RT_X } } } when (io.in_uop.valid) { slot_uop := io.in_uop.bits assert (is_invalid \|\| io.clear \|\| io.kill, "trying to overwrite a valid issue slot.") } // Wakeup Compare Logic // these signals are the "next_p" for the current slot's micro-op. // they are important for shifting the current slot_uop up to an other entry. val next_p1 = WireInit(p1) val next_p2 = WireInit(p2) val next_p3 = WireInit(p3) val next_ppred = WireInit(ppred) when (io.in_uop.valid) { p1 := !(io.in_uop.bits.prs1_busy) p2 := !(io.in_uop.bits.prs2_busy) p3 := !(io.in_uop.bits.prs3_busy) ppred := !(io.in_uop.bits.ppred_busy) } when (io.ldspec_miss && next_p1_poisoned) { assert(next_uop.prs1 =/= 0.U, "Poison bit can't be set for prs1=x0!") p1 := false.B } when (io.ldspec_miss && next_p2_poisoned) { assert(next_uop.prs2 =/= 0.U, "Poison bit can't be set for prs2=x0!") p2 := false.B } for (i <- 0 until numWakeupPorts) { when (io.wakeup_ports(i).valid && (io.wakeup_ports(i).bits.pdst === next_uop.prs1)) { p1 := true.B } when (io.wakeup_ports(i).valid && (io.wakeup_ports(i).bits.pdst === next_uop.prs2)) { p2 := true.B } when (io.wakeup_ports(i).valid && (io.wakeup_ports(i).bits.pdst === next_uop.prs3)) { p3 := true.B } } when (io.pred_wakeup_port.valid && io.pred_wakeup_port.bits === next_uop.ppred) { ppred := true.B } for (w <- 0 until memWidth) { assert (!(io.spec_ld_wakeup(w).valid && io.spec_ld_wakeup(w).bits === 0.U), "Loads to x0 should never speculatively wakeup other instructions") } // TODO disable if FP IQ. for (w <- 0 until memWidth) { when (io.spec_ld_wakeup(w).valid && io.spec_ld_wakeup(w).bits === next_uop.prs1 && next_uop.lrs1_rtype === RT_FIX) { p1 := true.B p1_poisoned := true.B assert (!next_p1_poisoned) } when (io.spec_ld_wakeup(w).valid && io.spec_ld_wakeup(w).bits === next_uop.prs2 && next_uop.lrs2_rtype === RT_FIX) { p2 := true.B p2_poisoned := true.B assert (!next_p2_poisoned) } } // Handle branch misspeculations val next_br_mask = GetNewBrMask(io.brupdate, slot_uop) // was this micro-op killed by a branch? if yes, we can't let it be valid if // we compact it into an other entry when (IsKilledByBranch(io.brupdate, slot_uop)) { next_state := s_invalid } when (!io.in_uop.valid) { slot_uop.br_mask := next_br_mask } //------------------------------------------------------------- // Request Logic io.request := is_valid && p1 && p2 && p3 && ppred && !io.kill val high_priority = slot_uop.is_br \|\| slot_uop.is_jal \|\| slot_uop.is_jalr io.request_hp := io.request && high_priority when (state === s_valid_1) { io.request := p1 && p2 && p3 && ppred && !io.kill } .elsewhen (state === s_valid_2) { io.request := (p1 \|\| p2) && ppred && !io.kill } .otherwise { io.request := false.B } //assign outputs io.valid := is_valid io.uop := slot_uop io.uop.iw_p1_poisoned := p1_poisoned io.uop.iw_p2_poisoned := p2_poisoned // micro-op will vacate due to grant. val may_vacate = io.grant && ((state === s_valid_1) \|\| (state === s_valid_2) && p1 && p2 && ppred) val squash_grant = io.ldspec_miss && (p1_poisoned \|\| p2_poisoned) io.will_be_valid := is_valid && !(may_vacate && !squash_grant) io.out_uop := slot_uop io.out_uop.iw_state := next_state io.out_uop.uopc := next_uopc io.out_uop.lrs1_rtype := next_lrs1_rtype io.out_uop.lrs2_rtype := next_lrs2_rtype io.out_uop.br_mask := next_br_mask io.out_uop.prs1_busy := !p1 io.out_uop.prs2_busy := !p2 io.out_uop.prs3_busy := !p3 io.out_uop.ppred_busy := !ppred io.out_uop.iw_p1_poisoned := p1_poisoned io.out_uop.iw_p2_poisoned := p2_poisoned when (state === s_valid_2) { when (p1 && p2 && ppred) { ; // send out the entire instruction as one uop } .elsewhen (p1 && ppred) { io.uop.uopc := slot_uop.uopc io.uop.lrs2_rtype := RT_X } .elsewhen (p2 && ppred) { io.uop.uopc := uopSTD io.uop.lrs1_rtype := RT_X } } // debug outputs io.debug.p1 := p1 io.debug.p2 := p2 io.debug.p3 := p3 io.debug.ppred := ppred io.debug.state := state }	module IssueSlot_7( // @[issue-slot.scala:69:7] input clock, // @[issue-slot.scala:69:7] input reset, // @[issue-slot.scala:69:7] output io_valid, // @[issue-slot.scala:73:14] output io_will_be_valid, // @[issue-slot.scala:73:14] output io_request, // @[issue-slot.scala:73:14] output io_request_hp, // @[issue-slot.scala:73:14] input io_grant, // @[issue-slot.scala:73:14] input [15:0] io_brupdate_b1_resolve_mask, // @[issue-slot.scala:73:14] input [15:0] io_brupdate_b1_mispredict_mask, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_uopc, // @[issue-slot.scala:73:14] input [31:0] io_brupdate_b2_uop_inst, // @[issue-slot.scala:73:14] input [31:0] io_brupdate_b2_uop_debug_inst, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_rvc, // @[issue-slot.scala:73:14] input [39:0] io_brupdate_b2_uop_debug_pc, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_uop_iq_type, // @[issue-slot.scala:73:14] input [9:0] io_brupdate_b2_uop_fu_code, // @[issue-slot.scala:73:14] input [3:0] io_brupdate_b2_uop_ctrl_br_type, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_ctrl_op1_sel, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_uop_ctrl_op2_sel, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_uop_ctrl_imm_sel, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_ctrl_op_fcn, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ctrl_fcn_dw, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_uop_ctrl_csr_cmd, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ctrl_is_load, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ctrl_is_sta, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ctrl_is_std, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_iw_state, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_iw_p1_poisoned, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_iw_p2_poisoned, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_br, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_jalr, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_jal, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_sfb, // @[issue-slot.scala:73:14] input [15:0] io_brupdate_b2_uop_br_mask, // @[issue-slot.scala:73:14] input [3:0] io_brupdate_b2_uop_br_tag, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_ftq_idx, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_edge_inst, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_pc_lob, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_taken, // @[issue-slot.scala:73:14] input [19:0] io_brupdate_b2_uop_imm_packed, // @[issue-slot.scala:73:14] input [11:0] io_brupdate_b2_uop_csr_addr, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_rob_idx, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_ldq_idx, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_stq_idx, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_rxq_idx, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_pdst, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_prs1, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_prs2, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_prs3, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_ppred, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_prs1_busy, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_prs2_busy, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_prs3_busy, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ppred_busy, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_stale_pdst, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_exception, // @[issue-slot.scala:73:14] input [63:0] io_brupdate_b2_uop_exc_cause, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_bypassable, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_mem_cmd, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_mem_size, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_mem_signed, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_fence, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_fencei, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_amo, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_uses_ldq, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_uses_stq, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_sys_pc2epc, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_unique, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_flush_on_commit, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ldst_is_rs1, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_ldst, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_lrs1, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_lrs2, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_lrs3, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ldst_val, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_dst_rtype, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_lrs1_rtype, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_lrs2_rtype, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_frs3_en, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_fp_val, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_fp_single, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_xcpt_pf_if, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_xcpt_ae_if, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_xcpt_ma_if, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_bp_debug_if, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_bp_xcpt_if, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_debug_fsrc, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_debug_tsrc, // @[issue-slot.scala:73:14] input io_brupdate_b2_valid, // @[issue-slot.scala:73:14] input io_brupdate_b2_mispredict, // @[issue-slot.scala:73:14] input io_brupdate_b2_taken, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_cfi_type, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_pc_sel, // @[issue-slot.scala:73:14] input [39:0] io_brupdate_b2_jalr_target, // @[issue-slot.scala:73:14] input [20:0] io_brupdate_b2_target_offset, // @[issue-slot.scala:73:14] input io_kill, // @[issue-slot.scala:73:14] input io_clear, // @[issue-slot.scala:73:14] input io_wakeup_ports_0_valid, // @[issue-slot.scala:73:14] input [6:0] io_wakeup_ports_0_bits_pdst, // @[issue-slot.scala:73:14] input io_wakeup_ports_1_valid, // @[issue-slot.scala:73:14] input [6:0] io_wakeup_ports_1_bits_pdst, // @[issue-slot.scala:73:14] input io_in_uop_valid, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_uopc, // @[issue-slot.scala:73:14] input [31:0] io_in_uop_bits_inst, // @[issue-slot.scala:73:14] input [31:0] io_in_uop_bits_debug_inst, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_rvc, // @[issue-slot.scala:73:14] input [39:0] io_in_uop_bits_debug_pc, // @[issue-slot.scala:73:14] input [2:0] io_in_uop_bits_iq_type, // @[issue-slot.scala:73:14] input [9:0] io_in_uop_bits_fu_code, // @[issue-slot.scala:73:14] input [3:0] io_in_uop_bits_ctrl_br_type, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_ctrl_op1_sel, // @[issue-slot.scala:73:14] input [2:0] io_in_uop_bits_ctrl_op2_sel, // @[issue-slot.scala:73:14] input [2:0] io_in_uop_bits_ctrl_imm_sel, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_ctrl_op_fcn, // @[issue-slot.scala:73:14] input io_in_uop_bits_ctrl_fcn_dw, // @[issue-slot.scala:73:14] input [2:0] io_in_uop_bits_ctrl_csr_cmd, // @[issue-slot.scala:73:14] input io_in_uop_bits_ctrl_is_load, // @[issue-slot.scala:73:14] input io_in_uop_bits_ctrl_is_sta, // @[issue-slot.scala:73:14] input io_in_uop_bits_ctrl_is_std, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_iw_state, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_br, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_jalr, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_jal, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_sfb, // @[issue-slot.scala:73:14] input [15:0] io_in_uop_bits_br_mask, // @[issue-slot.scala:73:14] input [3:0] io_in_uop_bits_br_tag, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_ftq_idx, // @[issue-slot.scala:73:14] input io_in_uop_bits_edge_inst, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_pc_lob, // @[issue-slot.scala:73:14] input io_in_uop_bits_taken, // @[issue-slot.scala:73:14] input [19:0] io_in_uop_bits_imm_packed, // @[issue-slot.scala:73:14] input [11:0] io_in_uop_bits_csr_addr, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_rob_idx, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_ldq_idx, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_stq_idx, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_rxq_idx, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_pdst, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_prs1, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_prs2, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_prs3, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_ppred, // @[issue-slot.scala:73:14] input io_in_uop_bits_prs1_busy, // @[issue-slot.scala:73:14] input io_in_uop_bits_prs2_busy, // @[issue-slot.scala:73:14] input io_in_uop_bits_prs3_busy, // @[issue-slot.scala:73:14] input io_in_uop_bits_ppred_busy, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_stale_pdst, // @[issue-slot.scala:73:14] input io_in_uop_bits_exception, // @[issue-slot.scala:73:14] input [63:0] io_in_uop_bits_exc_cause, // @[issue-slot.scala:73:14] input io_in_uop_bits_bypassable, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_mem_cmd, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_mem_size, // @[issue-slot.scala:73:14] input io_in_uop_bits_mem_signed, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_fence, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_fencei, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_amo, // @[issue-slot.scala:73:14] input io_in_uop_bits_uses_ldq, // @[issue-slot.scala:73:14] input io_in_uop_bits_uses_stq, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_sys_pc2epc, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_unique, // @[issue-slot.scala:73:14] input io_in_uop_bits_flush_on_commit, // @[issue-slot.scala:73:14] input io_in_uop_bits_ldst_is_rs1, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_ldst, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_lrs1, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_lrs2, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_lrs3, // @[issue-slot.scala:73:14] input io_in_uop_bits_ldst_val, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_dst_rtype, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_lrs1_rtype, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_lrs2_rtype, // @[issue-slot.scala:73:14] input io_in_uop_bits_frs3_en, // @[issue-slot.scala:73:14] input io_in_uop_bits_fp_val, // @[issue-slot.scala:73:14] input io_in_uop_bits_fp_single, // @[issue-slot.scala:73:14] input io_in_uop_bits_xcpt_pf_if, // @[issue-slot.scala:73:14] input io_in_uop_bits_xcpt_ae_if, // @[issue-slot.scala:73:14] input io_in_uop_bits_xcpt_ma_if, // @[issue-slot.scala:73:14] input io_in_uop_bits_bp_debug_if, // @[issue-slot.scala:73:14] input io_in_uop_bits_bp_xcpt_if, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_debug_fsrc, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_debug_tsrc, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_uopc, // @[issue-slot.scala:73:14] output [31:0] io_out_uop_inst, // @[issue-slot.scala:73:14] output [31:0] io_out_uop_debug_inst, // @[issue-slot.scala:73:14] output io_out_uop_is_rvc, // @[issue-slot.scala:73:14] output [39:0] io_out_uop_debug_pc, // @[issue-slot.scala:73:14] output [2:0] io_out_uop_iq_type, // @[issue-slot.scala:73:14] output [9:0] io_out_uop_fu_code, // @[issue-slot.scala:73:14] output [3:0] io_out_uop_ctrl_br_type, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_ctrl_op1_sel, // @[issue-slot.scala:73:14] output [2:0] io_out_uop_ctrl_op2_sel, // @[issue-slot.scala:73:14] output [2:0] io_out_uop_ctrl_imm_sel, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_ctrl_op_fcn, // @[issue-slot.scala:73:14] output io_out_uop_ctrl_fcn_dw, // @[issue-slot.scala:73:14] output [2:0] io_out_uop_ctrl_csr_cmd, // @[issue-slot.scala:73:14] output io_out_uop_ctrl_is_load, // @[issue-slot.scala:73:14] output io_out_uop_ctrl_is_sta, // @[issue-slot.scala:73:14] output io_out_uop_ctrl_is_std, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_iw_state, // @[issue-slot.scala:73:14] output io_out_uop_is_br, // @[issue-slot.scala:73:14] output io_out_uop_is_jalr, // @[issue-slot.scala:73:14] output io_out_uop_is_jal, // @[issue-slot.scala:73:14] output io_out_uop_is_sfb, // @[issue-slot.scala:73:14] output [15:0] io_out_uop_br_mask, // @[issue-slot.scala:73:14] output [3:0] io_out_uop_br_tag, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_ftq_idx, // @[issue-slot.scala:73:14] output io_out_uop_edge_inst, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_pc_lob, // @[issue-slot.scala:73:14] output io_out_uop_taken, // @[issue-slot.scala:73:14] output [19:0] io_out_uop_imm_packed, // @[issue-slot.scala:73:14] output [11:0] io_out_uop_csr_addr, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_rob_idx, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_ldq_idx, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_stq_idx, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_rxq_idx, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_pdst, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_prs1, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_prs2, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_prs3, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_ppred, // @[issue-slot.scala:73:14] output io_out_uop_prs1_busy, // @[issue-slot.scala:73:14] output io_out_uop_prs2_busy, // @[issue-slot.scala:73:14] output io_out_uop_prs3_busy, // @[issue-slot.scala:73:14] output io_out_uop_ppred_busy, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_stale_pdst, // @[issue-slot.scala:73:14] output io_out_uop_exception, // @[issue-slot.scala:73:14] output [63:0] io_out_uop_exc_cause, // @[issue-slot.scala:73:14] output io_out_uop_bypassable, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_mem_cmd, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_mem_size, // @[issue-slot.scala:73:14] output io_out_uop_mem_signed, // @[issue-slot.scala:73:14] output io_out_uop_is_fence, // @[issue-slot.scala:73:14] output io_out_uop_is_fencei, // @[issue-slot.scala:73:14] output io_out_uop_is_amo, // @[issue-slot.scala:73:14] output io_out_uop_uses_ldq, // @[issue-slot.scala:73:14] output io_out_uop_uses_stq, // @[issue-slot.scala:73:14] output io_out_uop_is_sys_pc2epc, // @[issue-slot.scala:73:14] output io_out_uop_is_unique, // @[issue-slot.scala:73:14] output io_out_uop_flush_on_commit, // @[issue-slot.scala:73:14] output io_out_uop_ldst_is_rs1, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_ldst, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_lrs1, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_lrs2, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_lrs3, // @[issue-slot.scala:73:14] output io_out_uop_ldst_val, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_dst_rtype, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_lrs1_rtype, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_lrs2_rtype, // @[issue-slot.scala:73:14] output io_out_uop_frs3_en, // @[issue-slot.scala:73:14] output io_out_uop_fp_val, // @[issue-slot.scala:73:14] output io_out_uop_fp_single, // @[issue-slot.scala:73:14] output io_out_uop_xcpt_pf_if, // @[issue-slot.scala:73:14] output io_out_uop_xcpt_ae_if, // @[issue-slot.scala:73:14] output io_out_uop_xcpt_ma_if, // @[issue-slot.scala:73:14] output io_out_uop_bp_debug_if, // @[issue-slot.scala:73:14] output io_out_uop_bp_xcpt_if, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_debug_fsrc, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_debug_tsrc, // @[issue-slot.scala:73:14] output [6:0] io_uop_uopc, // @[issue-slot.scala:73:14] output [31:0] io_uop_inst, // @[issue-slot.scala:73:14] output [31:0] io_uop_debug_inst, // @[issue-slot.scala:73:14] output io_uop_is_rvc, // @[issue-slot.scala:73:14] output [39:0] io_uop_debug_pc, // @[issue-slot.scala:73:14] output [2:0] io_uop_iq_type, // @[issue-slot.scala:73:14] output [9:0] io_uop_fu_code, // @[issue-slot.scala:73:14] output [3:0] io_uop_ctrl_br_type, // @[issue-slot.scala:73:14] output [1:0] io_uop_ctrl_op1_sel, // @[issue-slot.scala:73:14] output [2:0] io_uop_ctrl_op2_sel, // @[issue-slot.scala:73:14] output [2:0] io_uop_ctrl_imm_sel, // @[issue-slot.scala:73:14] output [4:0] io_uop_ctrl_op_fcn, // @[issue-slot.scala:73:14] output io_uop_ctrl_fcn_dw, // @[issue-slot.scala:73:14] output [2:0] io_uop_ctrl_csr_cmd, // @[issue-slot.scala:73:14] output io_uop_ctrl_is_load, // @[issue-slot.scala:73:14] output io_uop_ctrl_is_sta, // @[issue-slot.scala:73:14] output io_uop_ctrl_is_std, // @[issue-slot.scala:73:14] output [1:0] io_uop_iw_state, // @[issue-slot.scala:73:14] output io_uop_is_br, // @[issue-slot.scala:73:14] output io_uop_is_jalr, // @[issue-slot.scala:73:14] output io_uop_is_jal, // @[issue-slot.scala:73:14] output io_uop_is_sfb, // @[issue-slot.scala:73:14] output [15:0] io_uop_br_mask, // @[issue-slot.scala:73:14] output [3:0] io_uop_br_tag, // @[issue-slot.scala:73:14] output [4:0] io_uop_ftq_idx, // @[issue-slot.scala:73:14] output io_uop_edge_inst, // @[issue-slot.scala:73:14] output [5:0] io_uop_pc_lob, // @[issue-slot.scala:73:14] output io_uop_taken, // @[issue-slot.scala:73:14] output [19:0] io_uop_imm_packed, // @[issue-slot.scala:73:14] output [11:0] io_uop_csr_addr, // @[issue-slot.scala:73:14] output [6:0] io_uop_rob_idx, // @[issue-slot.scala:73:14] output [4:0] io_uop_ldq_idx, // @[issue-slot.scala:73:14] output [4:0] io_uop_stq_idx, // @[issue-slot.scala:73:14] output [1:0] io_uop_rxq_idx, // @[issue-slot.scala:73:14] output [6:0] io_uop_pdst, // @[issue-slot.scala:73:14] output [6:0] io_uop_prs1, // @[issue-slot.scala:73:14] output [6:0] io_uop_prs2, // @[issue-slot.scala:73:14] output [6:0] io_uop_prs3, // @[issue-slot.scala:73:14] output [4:0] io_uop_ppred, // @[issue-slot.scala:73:14] output io_uop_prs1_busy, // @[issue-slot.scala:73:14] output io_uop_prs2_busy, // @[issue-slot.scala:73:14] output io_uop_prs3_busy, // @[issue-slot.scala:73:14] output io_uop_ppred_busy, // @[issue-slot.scala:73:14] output [6:0] io_uop_stale_pdst, // @[issue-slot.scala:73:14] output io_uop_exception, // @[issue-slot.scala:73:14] output [63:0] io_uop_exc_cause, // @[issue-slot.scala:73:14] output io_uop_bypassable, // @[issue-slot.scala:73:14] output [4:0] io_uop_mem_cmd, // @[issue-slot.scala:73:14] output [1:0] io_uop_mem_size, // @[issue-slot.scala:73:14] output io_uop_mem_signed, // @[issue-slot.scala:73:14] output io_uop_is_fence, // @[issue-slot.scala:73:14] output io_uop_is_fencei, // @[issue-slot.scala:73:14] output io_uop_is_amo, // @[issue-slot.scala:73:14] output io_uop_uses_ldq, // @[issue-slot.scala:73:14] output io_uop_uses_stq, // @[issue-slot.scala:73:14] output io_uop_is_sys_pc2epc, // @[issue-slot.scala:73:14] output io_uop_is_unique, // @[issue-slot.scala:73:14] output io_uop_flush_on_commit, // @[issue-slot.scala:73:14] output io_uop_ldst_is_rs1, // @[issue-slot.scala:73:14] output [5:0] io_uop_ldst, // @[issue-slot.scala:73:14] output [5:0] io_uop_lrs1, // @[issue-slot.scala:73:14] output [5:0] io_uop_lrs2, // @[issue-slot.scala:73:14] output [5:0] io_uop_lrs3, // @[issue-slot.scala:73:14] output io_uop_ldst_val, // @[issue-slot.scala:73:14] output [1:0] io_uop_dst_rtype, // @[issue-slot.scala:73:14] output [1:0] io_uop_lrs1_rtype, // @[issue-slot.scala:73:14] output [1:0] io_uop_lrs2_rtype, // @[issue-slot.scala:73:14] output io_uop_frs3_en, // @[issue-slot.scala:73:14] output io_uop_fp_val, // @[issue-slot.scala:73:14] output io_uop_fp_single, // @[issue-slot.scala:73:14] output io_uop_xcpt_pf_if, // @[issue-slot.scala:73:14] output io_uop_xcpt_ae_if, // @[issue-slot.scala:73:14] output io_uop_xcpt_ma_if, // @[issue-slot.scala:73:14] output io_uop_bp_debug_if, // @[issue-slot.scala:73:14] output io_uop_bp_xcpt_if, // @[issue-slot.scala:73:14] output [1:0] io_uop_debug_fsrc, // @[issue-slot.scala:73:14] output [1:0] io_uop_debug_tsrc, // @[issue-slot.scala:73:14] output io_debug_p1, // @[issue-slot.scala:73:14] output io_debug_p2, // @[issue-slot.scala:73:14] output io_debug_p3, // @[issue-slot.scala:73:14] output io_debug_ppred, // @[issue-slot.scala:73:14] output [1:0] io_debug_state // @[issue-slot.scala:73:14] ); wire io_grant_0 = io_grant; // @[issue-slot.scala:69:7] wire [15:0] io_brupdate_b1_resolve_mask_0 = io_brupdate_b1_resolve_mask; // @[issue-slot.scala:69:7] wire [15:0] io_brupdate_b1_mispredict_mask_0 = io_brupdate_b1_mispredict_mask; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_uopc_0 = io_brupdate_b2_uop_uopc; // @[issue-slot.scala:69:7] wire [31:0] io_brupdate_b2_uop_inst_0 = io_brupdate_b2_uop_inst; // @[issue-slot.scala:69:7] wire [31:0] io_brupdate_b2_uop_debug_inst_0 = io_brupdate_b2_uop_debug_inst; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_rvc_0 = io_brupdate_b2_uop_is_rvc; // @[issue-slot.scala:69:7] wire [39:0] io_brupdate_b2_uop_debug_pc_0 = io_brupdate_b2_uop_debug_pc; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_uop_iq_type_0 = io_brupdate_b2_uop_iq_type; // @[issue-slot.scala:69:7] wire [9:0] io_brupdate_b2_uop_fu_code_0 = io_brupdate_b2_uop_fu_code; // @[issue-slot.scala:69:7] wire [3:0] io_brupdate_b2_uop_ctrl_br_type_0 = io_brupdate_b2_uop_ctrl_br_type; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_ctrl_op1_sel_0 = io_brupdate_b2_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_uop_ctrl_op2_sel_0 = io_brupdate_b2_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_uop_ctrl_imm_sel_0 = io_brupdate_b2_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_ctrl_op_fcn_0 = io_brupdate_b2_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ctrl_fcn_dw_0 = io_brupdate_b2_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_uop_ctrl_csr_cmd_0 = io_brupdate_b2_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ctrl_is_load_0 = io_brupdate_b2_uop_ctrl_is_load; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ctrl_is_sta_0 = io_brupdate_b2_uop_ctrl_is_sta; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ctrl_is_std_0 = io_brupdate_b2_uop_ctrl_is_std; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_iw_state_0 = io_brupdate_b2_uop_iw_state; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_iw_p1_poisoned_0 = io_brupdate_b2_uop_iw_p1_poisoned; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_iw_p2_poisoned_0 = io_brupdate_b2_uop_iw_p2_poisoned; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_br_0 = io_brupdate_b2_uop_is_br; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_jalr_0 = io_brupdate_b2_uop_is_jalr; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_jal_0 = io_brupdate_b2_uop_is_jal; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_sfb_0 = io_brupdate_b2_uop_is_sfb; // @[issue-slot.scala:69:7] wire [15:0] io_brupdate_b2_uop_br_mask_0 = io_brupdate_b2_uop_br_mask; // @[issue-slot.scala:69:7] wire [3:0] io_brupdate_b2_uop_br_tag_0 = io_brupdate_b2_uop_br_tag; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_ftq_idx_0 = io_brupdate_b2_uop_ftq_idx; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_edge_inst_0 = io_brupdate_b2_uop_edge_inst; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_pc_lob_0 = io_brupdate_b2_uop_pc_lob; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_taken_0 = io_brupdate_b2_uop_taken; // @[issue-slot.scala:69:7] wire [19:0] io_brupdate_b2_uop_imm_packed_0 = io_brupdate_b2_uop_imm_packed; // @[issue-slot.scala:69:7] wire [11:0] io_brupdate_b2_uop_csr_addr_0 = io_brupdate_b2_uop_csr_addr; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_rob_idx_0 = io_brupdate_b2_uop_rob_idx; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_ldq_idx_0 = io_brupdate_b2_uop_ldq_idx; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_stq_idx_0 = io_brupdate_b2_uop_stq_idx; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_rxq_idx_0 = io_brupdate_b2_uop_rxq_idx; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_pdst_0 = io_brupdate_b2_uop_pdst; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_prs1_0 = io_brupdate_b2_uop_prs1; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_prs2_0 = io_brupdate_b2_uop_prs2; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_prs3_0 = io_brupdate_b2_uop_prs3; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_ppred_0 = io_brupdate_b2_uop_ppred; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_prs1_busy_0 = io_brupdate_b2_uop_prs1_busy; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_prs2_busy_0 = io_brupdate_b2_uop_prs2_busy; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_prs3_busy_0 = io_brupdate_b2_uop_prs3_busy; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ppred_busy_0 = io_brupdate_b2_uop_ppred_busy; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_stale_pdst_0 = io_brupdate_b2_uop_stale_pdst; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_exception_0 = io_brupdate_b2_uop_exception; // @[issue-slot.scala:69:7] wire [63:0] io_brupdate_b2_uop_exc_cause_0 = io_brupdate_b2_uop_exc_cause; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_bypassable_0 = io_brupdate_b2_uop_bypassable; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_mem_cmd_0 = io_brupdate_b2_uop_mem_cmd; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_mem_size_0 = io_brupdate_b2_uop_mem_size; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_mem_signed_0 = io_brupdate_b2_uop_mem_signed; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_fence_0 = io_brupdate_b2_uop_is_fence; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_fencei_0 = io_brupdate_b2_uop_is_fencei; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_amo_0 = io_brupdate_b2_uop_is_amo; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_uses_ldq_0 = io_brupdate_b2_uop_uses_ldq; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_uses_stq_0 = io_brupdate_b2_uop_uses_stq; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_sys_pc2epc_0 = io_brupdate_b2_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_unique_0 = io_brupdate_b2_uop_is_unique; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_flush_on_commit_0 = io_brupdate_b2_uop_flush_on_commit; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ldst_is_rs1_0 = io_brupdate_b2_uop_ldst_is_rs1; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_ldst_0 = io_brupdate_b2_uop_ldst; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_lrs1_0 = io_brupdate_b2_uop_lrs1; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_lrs2_0 = io_brupdate_b2_uop_lrs2; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_lrs3_0 = io_brupdate_b2_uop_lrs3; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ldst_val_0 = io_brupdate_b2_uop_ldst_val; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_dst_rtype_0 = io_brupdate_b2_uop_dst_rtype; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_lrs1_rtype_0 = io_brupdate_b2_uop_lrs1_rtype; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_lrs2_rtype_0 = io_brupdate_b2_uop_lrs2_rtype; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_frs3_en_0 = io_brupdate_b2_uop_frs3_en; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_fp_val_0 = io_brupdate_b2_uop_fp_val; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_fp_single_0 = io_brupdate_b2_uop_fp_single; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_xcpt_pf_if_0 = io_brupdate_b2_uop_xcpt_pf_if; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_xcpt_ae_if_0 = io_brupdate_b2_uop_xcpt_ae_if; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_xcpt_ma_if_0 = io_brupdate_b2_uop_xcpt_ma_if; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_bp_debug_if_0 = io_brupdate_b2_uop_bp_debug_if; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_bp_xcpt_if_0 = io_brupdate_b2_uop_bp_xcpt_if; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_debug_fsrc_0 = io_brupdate_b2_uop_debug_fsrc; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_debug_tsrc_0 = io_brupdate_b2_uop_debug_tsrc; // @[issue-slot.scala:69:7] wire io_brupdate_b2_valid_0 = io_brupdate_b2_valid; // @[issue-slot.scala:69:7] wire io_brupdate_b2_mispredict_0 = io_brupdate_b2_mispredict; // @[issue-slot.scala:69:7] wire io_brupdate_b2_taken_0 = io_brupdate_b2_taken; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_cfi_type_0 = io_brupdate_b2_cfi_type; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_pc_sel_0 = io_brupdate_b2_pc_sel; // @[issue-slot.scala:69:7] wire [39:0] io_brupdate_b2_jalr_target_0 = io_brupdate_b2_jalr_target; // @[issue-slot.scala:69:7] wire [20:0] io_brupdate_b2_target_offset_0 = io_brupdate_b2_target_offset; // @[issue-slot.scala:69:7] wire io_kill_0 = io_kill; // @[issue-slot.scala:69:7] wire io_clear_0 = io_clear; // @[issue-slot.scala:69:7] wire io_wakeup_ports_0_valid_0 = io_wakeup_ports_0_valid; // @[issue-slot.scala:69:7] wire [6:0] io_wakeup_ports_0_bits_pdst_0 = io_wakeup_ports_0_bits_pdst; // @[issue-slot.scala:69:7] wire io_wakeup_ports_1_valid_0 = io_wakeup_ports_1_valid; // @[issue-slot.scala:69:7] wire [6:0] io_wakeup_ports_1_bits_pdst_0 = io_wakeup_ports_1_bits_pdst; // @[issue-slot.scala:69:7] wire io_in_uop_valid_0 = io_in_uop_valid; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_uopc_0 = io_in_uop_bits_uopc; // @[issue-slot.scala:69:7] wire [31:0] io_in_uop_bits_inst_0 = io_in_uop_bits_inst; // @[issue-slot.scala:69:7] wire [31:0] io_in_uop_bits_debug_inst_0 = io_in_uop_bits_debug_inst; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_rvc_0 = io_in_uop_bits_is_rvc; // @[issue-slot.scala:69:7] wire [39:0] io_in_uop_bits_debug_pc_0 = io_in_uop_bits_debug_pc; // @[issue-slot.scala:69:7] wire [2:0] io_in_uop_bits_iq_type_0 = io_in_uop_bits_iq_type; // @[issue-slot.scala:69:7] wire [9:0] io_in_uop_bits_fu_code_0 = io_in_uop_bits_fu_code; // @[issue-slot.scala:69:7] wire [3:0] io_in_uop_bits_ctrl_br_type_0 = io_in_uop_bits_ctrl_br_type; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_ctrl_op1_sel_0 = io_in_uop_bits_ctrl_op1_sel; // @[issue-slot.scala:69:7] wire [2:0] io_in_uop_bits_ctrl_op2_sel_0 = io_in_uop_bits_ctrl_op2_sel; // @[issue-slot.scala:69:7] wire [2:0] io_in_uop_bits_ctrl_imm_sel_0 = io_in_uop_bits_ctrl_imm_sel; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_ctrl_op_fcn_0 = io_in_uop_bits_ctrl_op_fcn; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ctrl_fcn_dw_0 = io_in_uop_bits_ctrl_fcn_dw; // @[issue-slot.scala:69:7] wire [2:0] io_in_uop_bits_ctrl_csr_cmd_0 = io_in_uop_bits_ctrl_csr_cmd; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ctrl_is_load_0 = io_in_uop_bits_ctrl_is_load; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ctrl_is_sta_0 = io_in_uop_bits_ctrl_is_sta; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ctrl_is_std_0 = io_in_uop_bits_ctrl_is_std; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_iw_state_0 = io_in_uop_bits_iw_state; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_br_0 = io_in_uop_bits_is_br; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_jalr_0 = io_in_uop_bits_is_jalr; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_jal_0 = io_in_uop_bits_is_jal; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_sfb_0 = io_in_uop_bits_is_sfb; // @[issue-slot.scala:69:7] wire [15:0] io_in_uop_bits_br_mask_0 = io_in_uop_bits_br_mask; // @[issue-slot.scala:69:7] wire [3:0] io_in_uop_bits_br_tag_0 = io_in_uop_bits_br_tag; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_ftq_idx_0 = io_in_uop_bits_ftq_idx; // @[issue-slot.scala:69:7] wire io_in_uop_bits_edge_inst_0 = io_in_uop_bits_edge_inst; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_pc_lob_0 = io_in_uop_bits_pc_lob; // @[issue-slot.scala:69:7] wire io_in_uop_bits_taken_0 = io_in_uop_bits_taken; // @[issue-slot.scala:69:7] wire [19:0] io_in_uop_bits_imm_packed_0 = io_in_uop_bits_imm_packed; // @[issue-slot.scala:69:7] wire [11:0] io_in_uop_bits_csr_addr_0 = io_in_uop_bits_csr_addr; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_rob_idx_0 = io_in_uop_bits_rob_idx; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_ldq_idx_0 = io_in_uop_bits_ldq_idx; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_stq_idx_0 = io_in_uop_bits_stq_idx; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_rxq_idx_0 = io_in_uop_bits_rxq_idx; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_pdst_0 = io_in_uop_bits_pdst; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_prs1_0 = io_in_uop_bits_prs1; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_prs2_0 = io_in_uop_bits_prs2; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_prs3_0 = io_in_uop_bits_prs3; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_ppred_0 = io_in_uop_bits_ppred; // @[issue-slot.scala:69:7] wire io_in_uop_bits_prs1_busy_0 = io_in_uop_bits_prs1_busy; // @[issue-slot.scala:69:7] wire io_in_uop_bits_prs2_busy_0 = io_in_uop_bits_prs2_busy; // @[issue-slot.scala:69:7] wire io_in_uop_bits_prs3_busy_0 = io_in_uop_bits_prs3_busy; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ppred_busy_0 = io_in_uop_bits_ppred_busy; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_stale_pdst_0 = io_in_uop_bits_stale_pdst; // @[issue-slot.scala:69:7] wire io_in_uop_bits_exception_0 = io_in_uop_bits_exception; // @[issue-slot.scala:69:7] wire [63:0] io_in_uop_bits_exc_cause_0 = io_in_uop_bits_exc_cause; // @[issue-slot.scala:69:7] wire io_in_uop_bits_bypassable_0 = io_in_uop_bits_bypassable; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_mem_cmd_0 = io_in_uop_bits_mem_cmd; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_mem_size_0 = io_in_uop_bits_mem_size; // @[issue-slot.scala:69:7] wire io_in_uop_bits_mem_signed_0 = io_in_uop_bits_mem_signed; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_fence_0 = io_in_uop_bits_is_fence; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_fencei_0 = io_in_uop_bits_is_fencei; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_amo_0 = io_in_uop_bits_is_amo; // @[issue-slot.scala:69:7] wire io_in_uop_bits_uses_ldq_0 = io_in_uop_bits_uses_ldq; // @[issue-slot.scala:69:7] wire io_in_uop_bits_uses_stq_0 = io_in_uop_bits_uses_stq; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_sys_pc2epc_0 = io_in_uop_bits_is_sys_pc2epc; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_unique_0 = io_in_uop_bits_is_unique; // @[issue-slot.scala:69:7] wire io_in_uop_bits_flush_on_commit_0 = io_in_uop_bits_flush_on_commit; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ldst_is_rs1_0 = io_in_uop_bits_ldst_is_rs1; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_ldst_0 = io_in_uop_bits_ldst; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_lrs1_0 = io_in_uop_bits_lrs1; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_lrs2_0 = io_in_uop_bits_lrs2; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_lrs3_0 = io_in_uop_bits_lrs3; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ldst_val_0 = io_in_uop_bits_ldst_val; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_dst_rtype_0 = io_in_uop_bits_dst_rtype; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_lrs1_rtype_0 = io_in_uop_bits_lrs1_rtype; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_lrs2_rtype_0 = io_in_uop_bits_lrs2_rtype; // @[issue-slot.scala:69:7] wire io_in_uop_bits_frs3_en_0 = io_in_uop_bits_frs3_en; // @[issue-slot.scala:69:7] wire io_in_uop_bits_fp_val_0 = io_in_uop_bits_fp_val; // @[issue-slot.scala:69:7] wire io_in_uop_bits_fp_single_0 = io_in_uop_bits_fp_single; // @[issue-slot.scala:69:7] wire io_in_uop_bits_xcpt_pf_if_0 = io_in_uop_bits_xcpt_pf_if; // @[issue-slot.scala:69:7] wire io_in_uop_bits_xcpt_ae_if_0 = io_in_uop_bits_xcpt_ae_if; // @[issue-slot.scala:69:7] wire io_in_uop_bits_xcpt_ma_if_0 = io_in_uop_bits_xcpt_ma_if; // @[issue-slot.scala:69:7] wire io_in_uop_bits_bp_debug_if_0 = io_in_uop_bits_bp_debug_if; // @[issue-slot.scala:69:7] wire io_in_uop_bits_bp_xcpt_if_0 = io_in_uop_bits_bp_xcpt_if; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_debug_fsrc_0 = io_in_uop_bits_debug_fsrc; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_debug_tsrc_0 = io_in_uop_bits_debug_tsrc; // @[issue-slot.scala:69:7] wire io_ldspec_miss = 1'h0; // @[issue-slot.scala:69:7] wire io_wakeup_ports_0_bits_poisoned = 1'h0; // @[issue-slot.scala:69:7] wire io_wakeup_ports_1_bits_poisoned = 1'h0; // @[issue-slot.scala:69:7] wire io_pred_wakeup_port_valid = 1'h0; // @[issue-slot.scala:69:7] wire io_spec_ld_wakeup_0_valid = 1'h0; // @[issue-slot.scala:69:7] wire io_in_uop_bits_iw_p1_poisoned = 1'h0; // @[issue-slot.scala:69:7] wire io_in_uop_bits_iw_p2_poisoned = 1'h0; // @[issue-slot.scala:69:7] wire io_out_uop_iw_p1_poisoned = 1'h0; // @[issue-slot.scala:69:7] wire io_out_uop_iw_p2_poisoned = 1'h0; // @[issue-slot.scala:69:7] wire io_uop_iw_p1_poisoned = 1'h0; // @[issue-slot.scala:69:7] wire io_uop_iw_p2_poisoned = 1'h0; // @[issue-slot.scala:69:7] wire next_p1_poisoned = 1'h0; // @[issue-slot.scala:99:29] wire next_p2_poisoned = 1'h0; // @[issue-slot.scala:100:29] wire slot_uop_uop_is_rvc = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ctrl_fcn_dw = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ctrl_is_load = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ctrl_is_sta = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ctrl_is_std = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_iw_p1_poisoned = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_iw_p2_poisoned = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_br = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_jalr = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_jal = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_sfb = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_edge_inst = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_taken = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_prs1_busy = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_prs2_busy = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_prs3_busy = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ppred_busy = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_exception = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_bypassable = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_mem_signed = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_fence = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_fencei = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_amo = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_uses_ldq = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_uses_stq = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_sys_pc2epc = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_unique = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_flush_on_commit = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ldst_is_rs1 = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ldst_val = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_frs3_en = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_fp_val = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_fp_single = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_xcpt_pf_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_xcpt_ae_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_xcpt_ma_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_bp_debug_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_bp_xcpt_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_cs_fcn_dw = 1'h0; // @[consts.scala:279:18] wire slot_uop_cs_is_load = 1'h0; // @[consts.scala:279:18] wire slot_uop_cs_is_sta = 1'h0; // @[consts.scala:279:18] wire slot_uop_cs_is_std = 1'h0; // @[consts.scala:279:18] wire _squash_grant_T = 1'h0; // @[issue-slot.scala:261:53] wire squash_grant = 1'h0; // @[issue-slot.scala:261:37] wire [4:0] io_pred_wakeup_port_bits = 5'h0; // @[issue-slot.scala:69:7] wire [4:0] slot_uop_uop_ctrl_op_fcn = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_uop_ftq_idx = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_uop_ldq_idx = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_uop_stq_idx = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_uop_ppred = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_uop_mem_cmd = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_cs_op_fcn = 5'h0; // @[consts.scala:279:18] wire [6:0] io_spec_ld_wakeup_0_bits = 7'h0; // @[issue-slot.scala:69:7] wire [6:0] slot_uop_uop_uopc = 7'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_rob_idx = 7'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_pdst = 7'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_prs1 = 7'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_prs2 = 7'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_prs3 = 7'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_stale_pdst = 7'h0; // @[consts.scala:269:19] wire _io_will_be_valid_T_1 = 1'h1; // @[issue-slot.scala:262:51] wire [1:0] slot_uop_uop_ctrl_op1_sel = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_iw_state = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_rxq_idx = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_mem_size = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_lrs1_rtype = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_lrs2_rtype = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_debug_fsrc = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_debug_tsrc = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_cs_op1_sel = 2'h0; // @[consts.scala:279:18] wire [2:0] slot_uop_uop_iq_type = 3'h0; // @[consts.scala:269:19] wire [2:0] slot_uop_uop_ctrl_op2_sel = 3'h0; // @[consts.scala:269:19] wire [2:0] slot_uop_uop_ctrl_imm_sel = 3'h0; // @[consts.scala:269:19] wire [2:0] slot_uop_uop_ctrl_csr_cmd = 3'h0; // @[consts.scala:269:19] wire [2:0] slot_uop_cs_op2_sel = 3'h0; // @[consts.scala:279:18] wire [2:0] slot_uop_cs_imm_sel = 3'h0; // @[consts.scala:279:18] wire [2:0] slot_uop_cs_csr_cmd = 3'h0; // @[consts.scala:279:18] wire [3:0] slot_uop_uop_ctrl_br_type = 4'h0; // @[consts.scala:269:19] wire [3:0] slot_uop_uop_br_tag = 4'h0; // @[consts.scala:269:19] wire [3:0] slot_uop_cs_br_type = 4'h0; // @[consts.scala:279:18] wire [1:0] slot_uop_uop_dst_rtype = 2'h2; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_pc_lob = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_ldst = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_lrs1 = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_lrs2 = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_lrs3 = 6'h0; // @[consts.scala:269:19] wire [63:0] slot_uop_uop_exc_cause = 64'h0; // @[consts.scala:269:19] wire [11:0] slot_uop_uop_csr_addr = 12'h0; // @[consts.scala:269:19] wire [19:0] slot_uop_uop_imm_packed = 20'h0; // @[consts.scala:269:19] wire [15:0] slot_uop_uop_br_mask = 16'h0; // @[consts.scala:269:19] wire [9:0] slot_uop_uop_fu_code = 10'h0; // @[consts.scala:269:19] wire [39:0] slot_uop_uop_debug_pc = 40'h0; // @[consts.scala:269:19] wire [31:0] slot_uop_uop_inst = 32'h0; // @[consts.scala:269:19] wire [31:0] slot_uop_uop_debug_inst = 32'h0; // @[consts.scala:269:19] wire _io_valid_T; // @[issue-slot.scala:79:24] wire _io_will_be_valid_T_4; // @[issue-slot.scala:262:32] wire _io_request_hp_T; // @[issue-slot.scala:243:31] wire [6:0] next_uopc; // @[issue-slot.scala:82:29] wire [1:0] next_state; // @[issue-slot.scala:81:29] wire [15:0] next_br_mask; // @[util.scala:85:25] wire _io_out_uop_prs1_busy_T; // @[issue-slot.scala:270:28] wire _io_out_uop_prs2_busy_T; // @[issue-slot.scala:271:28] wire _io_out_uop_prs3_busy_T; // @[issue-slot.scala:272:28] wire _io_out_uop_ppred_busy_T; // @[issue-slot.scala:273:28] wire [1:0] next_lrs1_rtype; // @[issue-slot.scala:83:29] wire [1:0] next_lrs2_rtype; // @[issue-slot.scala:84:29] wire [3:0] io_out_uop_ctrl_br_type_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_ctrl_op1_sel_0; // @[issue-slot.scala:69:7] wire [2:0] io_out_uop_ctrl_op2_sel_0; // @[issue-slot.scala:69:7] wire [2:0] io_out_uop_ctrl_imm_sel_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_ctrl_op_fcn_0; // @[issue-slot.scala:69:7] wire io_out_uop_ctrl_fcn_dw_0; // @[issue-slot.scala:69:7] wire [2:0] io_out_uop_ctrl_csr_cmd_0; // @[issue-slot.scala:69:7] wire io_out_uop_ctrl_is_load_0; // @[issue-slot.scala:69:7] wire io_out_uop_ctrl_is_sta_0; // @[issue-slot.scala:69:7] wire io_out_uop_ctrl_is_std_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_uopc_0; // @[issue-slot.scala:69:7] wire [31:0] io_out_uop_inst_0; // @[issue-slot.scala:69:7] wire [31:0] io_out_uop_debug_inst_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_rvc_0; // @[issue-slot.scala:69:7] wire [39:0] io_out_uop_debug_pc_0; // @[issue-slot.scala:69:7] wire [2:0] io_out_uop_iq_type_0; // @[issue-slot.scala:69:7] wire [9:0] io_out_uop_fu_code_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_iw_state_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_br_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_jalr_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_jal_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_sfb_0; // @[issue-slot.scala:69:7] wire [15:0] io_out_uop_br_mask_0; // @[issue-slot.scala:69:7] wire [3:0] io_out_uop_br_tag_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_ftq_idx_0; // @[issue-slot.scala:69:7] wire io_out_uop_edge_inst_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_pc_lob_0; // @[issue-slot.scala:69:7] wire io_out_uop_taken_0; // @[issue-slot.scala:69:7] wire [19:0] io_out_uop_imm_packed_0; // @[issue-slot.scala:69:7] wire [11:0] io_out_uop_csr_addr_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_rob_idx_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_ldq_idx_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_stq_idx_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_rxq_idx_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_pdst_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_prs1_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_prs2_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_prs3_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_ppred_0; // @[issue-slot.scala:69:7] wire io_out_uop_prs1_busy_0; // @[issue-slot.scala:69:7] wire io_out_uop_prs2_busy_0; // @[issue-slot.scala:69:7] wire io_out_uop_prs3_busy_0; // @[issue-slot.scala:69:7] wire io_out_uop_ppred_busy_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_stale_pdst_0; // @[issue-slot.scala:69:7] wire io_out_uop_exception_0; // @[issue-slot.scala:69:7] wire [63:0] io_out_uop_exc_cause_0; // @[issue-slot.scala:69:7] wire io_out_uop_bypassable_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_mem_cmd_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_mem_size_0; // @[issue-slot.scala:69:7] wire io_out_uop_mem_signed_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_fence_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_fencei_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_amo_0; // @[issue-slot.scala:69:7] wire io_out_uop_uses_ldq_0; // @[issue-slot.scala:69:7] wire io_out_uop_uses_stq_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_sys_pc2epc_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_unique_0; // @[issue-slot.scala:69:7] wire io_out_uop_flush_on_commit_0; // @[issue-slot.scala:69:7] wire io_out_uop_ldst_is_rs1_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_ldst_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_lrs1_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_lrs2_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_lrs3_0; // @[issue-slot.scala:69:7] wire io_out_uop_ldst_val_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_dst_rtype_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_lrs1_rtype_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_lrs2_rtype_0; // @[issue-slot.scala:69:7] wire io_out_uop_frs3_en_0; // @[issue-slot.scala:69:7] wire io_out_uop_fp_val_0; // @[issue-slot.scala:69:7] wire io_out_uop_fp_single_0; // @[issue-slot.scala:69:7] wire io_out_uop_xcpt_pf_if_0; // @[issue-slot.scala:69:7] wire io_out_uop_xcpt_ae_if_0; // @[issue-slot.scala:69:7] wire io_out_uop_xcpt_ma_if_0; // @[issue-slot.scala:69:7] wire io_out_uop_bp_debug_if_0; // @[issue-slot.scala:69:7] wire io_out_uop_bp_xcpt_if_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_debug_fsrc_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_debug_tsrc_0; // @[issue-slot.scala:69:7] wire [3:0] io_uop_ctrl_br_type_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_ctrl_op1_sel_0; // @[issue-slot.scala:69:7] wire [2:0] io_uop_ctrl_op2_sel_0; // @[issue-slot.scala:69:7] wire [2:0] io_uop_ctrl_imm_sel_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_ctrl_op_fcn_0; // @[issue-slot.scala:69:7] wire io_uop_ctrl_fcn_dw_0; // @[issue-slot.scala:69:7] wire [2:0] io_uop_ctrl_csr_cmd_0; // @[issue-slot.scala:69:7] wire io_uop_ctrl_is_load_0; // @[issue-slot.scala:69:7] wire io_uop_ctrl_is_sta_0; // @[issue-slot.scala:69:7] wire io_uop_ctrl_is_std_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_uopc_0; // @[issue-slot.scala:69:7] wire [31:0] io_uop_inst_0; // @[issue-slot.scala:69:7] wire [31:0] io_uop_debug_inst_0; // @[issue-slot.scala:69:7] wire io_uop_is_rvc_0; // @[issue-slot.scala:69:7] wire [39:0] io_uop_debug_pc_0; // @[issue-slot.scala:69:7] wire [2:0] io_uop_iq_type_0; // @[issue-slot.scala:69:7] wire [9:0] io_uop_fu_code_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_iw_state_0; // @[issue-slot.scala:69:7] wire io_uop_is_br_0; // @[issue-slot.scala:69:7] wire io_uop_is_jalr_0; // @[issue-slot.scala:69:7] wire io_uop_is_jal_0; // @[issue-slot.scala:69:7] wire io_uop_is_sfb_0; // @[issue-slot.scala:69:7] wire [15:0] io_uop_br_mask_0; // @[issue-slot.scala:69:7] wire [3:0] io_uop_br_tag_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_ftq_idx_0; // @[issue-slot.scala:69:7] wire io_uop_edge_inst_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_pc_lob_0; // @[issue-slot.scala:69:7] wire io_uop_taken_0; // @[issue-slot.scala:69:7] wire [19:0] io_uop_imm_packed_0; // @[issue-slot.scala:69:7] wire [11:0] io_uop_csr_addr_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_rob_idx_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_ldq_idx_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_stq_idx_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_rxq_idx_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_pdst_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_prs1_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_prs2_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_prs3_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_ppred_0; // @[issue-slot.scala:69:7] wire io_uop_prs1_busy_0; // @[issue-slot.scala:69:7] wire io_uop_prs2_busy_0; // @[issue-slot.scala:69:7] wire io_uop_prs3_busy_0; // @[issue-slot.scala:69:7] wire io_uop_ppred_busy_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_stale_pdst_0; // @[issue-slot.scala:69:7] wire io_uop_exception_0; // @[issue-slot.scala:69:7] wire [63:0] io_uop_exc_cause_0; // @[issue-slot.scala:69:7] wire io_uop_bypassable_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_mem_cmd_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_mem_size_0; // @[issue-slot.scala:69:7] wire io_uop_mem_signed_0; // @[issue-slot.scala:69:7] wire io_uop_is_fence_0; // @[issue-slot.scala:69:7] wire io_uop_is_fencei_0; // @[issue-slot.scala:69:7] wire io_uop_is_amo_0; // @[issue-slot.scala:69:7] wire io_uop_uses_ldq_0; // @[issue-slot.scala:69:7] wire io_uop_uses_stq_0; // @[issue-slot.scala:69:7] wire io_uop_is_sys_pc2epc_0; // @[issue-slot.scala:69:7] wire io_uop_is_unique_0; // @[issue-slot.scala:69:7] wire io_uop_flush_on_commit_0; // @[issue-slot.scala:69:7] wire io_uop_ldst_is_rs1_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_ldst_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_lrs1_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_lrs2_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_lrs3_0; // @[issue-slot.scala:69:7] wire io_uop_ldst_val_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_dst_rtype_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_lrs1_rtype_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_lrs2_rtype_0; // @[issue-slot.scala:69:7] wire io_uop_frs3_en_0; // @[issue-slot.scala:69:7] wire io_uop_fp_val_0; // @[issue-slot.scala:69:7] wire io_uop_fp_single_0; // @[issue-slot.scala:69:7] wire io_uop_xcpt_pf_if_0; // @[issue-slot.scala:69:7] wire io_uop_xcpt_ae_if_0; // @[issue-slot.scala:69:7] wire io_uop_xcpt_ma_if_0; // @[issue-slot.scala:69:7] wire io_uop_bp_debug_if_0; // @[issue-slot.scala:69:7] wire io_uop_bp_xcpt_if_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_debug_fsrc_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_debug_tsrc_0; // @[issue-slot.scala:69:7] wire io_debug_p1_0; // @[issue-slot.scala:69:7] wire io_debug_p2_0; // @[issue-slot.scala:69:7] wire io_debug_p3_0; // @[issue-slot.scala:69:7] wire io_debug_ppred_0; // @[issue-slot.scala:69:7] wire [1:0] io_debug_state_0; // @[issue-slot.scala:69:7] wire io_valid_0; // @[issue-slot.scala:69:7] wire io_will_be_valid_0; // @[issue-slot.scala:69:7] wire io_request_0; // @[issue-slot.scala:69:7] wire io_request_hp_0; // @[issue-slot.scala:69:7] assign io_out_uop_iw_state_0 = next_state; // @[issue-slot.scala:69:7, :81:29] assign io_out_uop_uopc_0 = next_uopc; // @[issue-slot.scala:69:7, :82:29] assign io_out_uop_lrs1_rtype_0 = next_lrs1_rtype; // @[issue-slot.scala:69:7, :83:29] assign io_out_uop_lrs2_rtype_0 = next_lrs2_rtype; // @[issue-slot.scala:69:7, :84:29] reg [1:0] state; // @[issue-slot.scala:86:22] assign io_debug_state_0 = state; // @[issue-slot.scala:69:7, :86:22] reg p1; // @[issue-slot.scala:87:22] assign io_debug_p1_0 = p1; // @[issue-slot.scala:69:7, :87:22] wire next_p1 = p1; // @[issue-slot.scala:87:22, :163:25] reg p2; // @[issue-slot.scala:88:22] assign io_debug_p2_0 = p2; // @[issue-slot.scala:69:7, :88:22] wire next_p2 = p2; // @[issue-slot.scala:88:22, :164:25] reg p3; // @[issue-slot.scala:89:22] assign io_debug_p3_0 = p3; // @[issue-slot.scala:69:7, :89:22] wire next_p3 = p3; // @[issue-slot.scala:89:22, :165:25] reg ppred; // @[issue-slot.scala:90:22] assign io_debug_ppred_0 = ppred; // @[issue-slot.scala:69:7, :90:22] wire next_ppred = ppred; // @[issue-slot.scala:90:22, :166:28] reg [6:0] slot_uop_uopc; // @[issue-slot.scala:102:25] reg [31:0] slot_uop_inst; // @[issue-slot.scala:102:25] assign io_out_uop_inst_0 = slot_uop_inst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_inst_0 = slot_uop_inst; // @[issue-slot.scala:69:7, :102:25] reg [31:0] slot_uop_debug_inst; // @[issue-slot.scala:102:25] assign io_out_uop_debug_inst_0 = slot_uop_debug_inst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_debug_inst_0 = slot_uop_debug_inst; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_rvc; // @[issue-slot.scala:102:25] assign io_out_uop_is_rvc_0 = slot_uop_is_rvc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_rvc_0 = slot_uop_is_rvc; // @[issue-slot.scala:69:7, :102:25] reg [39:0] slot_uop_debug_pc; // @[issue-slot.scala:102:25] assign io_out_uop_debug_pc_0 = slot_uop_debug_pc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_debug_pc_0 = slot_uop_debug_pc; // @[issue-slot.scala:69:7, :102:25] reg [2:0] slot_uop_iq_type; // @[issue-slot.scala:102:25] assign io_out_uop_iq_type_0 = slot_uop_iq_type; // @[issue-slot.scala:69:7, :102:25] assign io_uop_iq_type_0 = slot_uop_iq_type; // @[issue-slot.scala:69:7, :102:25] reg [9:0] slot_uop_fu_code; // @[issue-slot.scala:102:25] assign io_out_uop_fu_code_0 = slot_uop_fu_code; // @[issue-slot.scala:69:7, :102:25] assign io_uop_fu_code_0 = slot_uop_fu_code; // @[issue-slot.scala:69:7, :102:25] reg [3:0] slot_uop_ctrl_br_type; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_br_type_0 = slot_uop_ctrl_br_type; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_br_type_0 = slot_uop_ctrl_br_type; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_ctrl_op1_sel; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_op1_sel_0 = slot_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_op1_sel_0 = slot_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7, :102:25] reg [2:0] slot_uop_ctrl_op2_sel; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_op2_sel_0 = slot_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_op2_sel_0 = slot_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7, :102:25] reg [2:0] slot_uop_ctrl_imm_sel; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_imm_sel_0 = slot_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_imm_sel_0 = slot_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_ctrl_op_fcn; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_op_fcn_0 = slot_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_op_fcn_0 = slot_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_fcn_dw_0 = slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_fcn_dw_0 = slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7, :102:25] reg [2:0] slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_csr_cmd_0 = slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_csr_cmd_0 = slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ctrl_is_load; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_is_load_0 = slot_uop_ctrl_is_load; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_is_load_0 = slot_uop_ctrl_is_load; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ctrl_is_sta; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_is_sta_0 = slot_uop_ctrl_is_sta; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_is_sta_0 = slot_uop_ctrl_is_sta; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ctrl_is_std; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_is_std_0 = slot_uop_ctrl_is_std; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_is_std_0 = slot_uop_ctrl_is_std; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_iw_state; // @[issue-slot.scala:102:25] assign io_uop_iw_state_0 = slot_uop_iw_state; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_iw_p1_poisoned; // @[issue-slot.scala:102:25] reg slot_uop_iw_p2_poisoned; // @[issue-slot.scala:102:25] reg slot_uop_is_br; // @[issue-slot.scala:102:25] assign io_out_uop_is_br_0 = slot_uop_is_br; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_br_0 = slot_uop_is_br; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_jalr; // @[issue-slot.scala:102:25] assign io_out_uop_is_jalr_0 = slot_uop_is_jalr; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_jalr_0 = slot_uop_is_jalr; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_jal; // @[issue-slot.scala:102:25] assign io_out_uop_is_jal_0 = slot_uop_is_jal; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_jal_0 = slot_uop_is_jal; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_sfb; // @[issue-slot.scala:102:25] assign io_out_uop_is_sfb_0 = slot_uop_is_sfb; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_sfb_0 = slot_uop_is_sfb; // @[issue-slot.scala:69:7, :102:25] reg [15:0] slot_uop_br_mask; // @[issue-slot.scala:102:25] assign io_uop_br_mask_0 = slot_uop_br_mask; // @[issue-slot.scala:69:7, :102:25] reg [3:0] slot_uop_br_tag; // @[issue-slot.scala:102:25] assign io_out_uop_br_tag_0 = slot_uop_br_tag; // @[issue-slot.scala:69:7, :102:25] assign io_uop_br_tag_0 = slot_uop_br_tag; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_ftq_idx; // @[issue-slot.scala:102:25] assign io_out_uop_ftq_idx_0 = slot_uop_ftq_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ftq_idx_0 = slot_uop_ftq_idx; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_edge_inst; // @[issue-slot.scala:102:25] assign io_out_uop_edge_inst_0 = slot_uop_edge_inst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_edge_inst_0 = slot_uop_edge_inst; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_pc_lob; // @[issue-slot.scala:102:25] assign io_out_uop_pc_lob_0 = slot_uop_pc_lob; // @[issue-slot.scala:69:7, :102:25] assign io_uop_pc_lob_0 = slot_uop_pc_lob; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_taken; // @[issue-slot.scala:102:25] assign io_out_uop_taken_0 = slot_uop_taken; // @[issue-slot.scala:69:7, :102:25] assign io_uop_taken_0 = slot_uop_taken; // @[issue-slot.scala:69:7, :102:25] reg [19:0] slot_uop_imm_packed; // @[issue-slot.scala:102:25] assign io_out_uop_imm_packed_0 = slot_uop_imm_packed; // @[issue-slot.scala:69:7, :102:25] assign io_uop_imm_packed_0 = slot_uop_imm_packed; // @[issue-slot.scala:69:7, :102:25] reg [11:0] slot_uop_csr_addr; // @[issue-slot.scala:102:25] assign io_out_uop_csr_addr_0 = slot_uop_csr_addr; // @[issue-slot.scala:69:7, :102:25] assign io_uop_csr_addr_0 = slot_uop_csr_addr; // @[issue-slot.scala:69:7, :102:25] reg [6:0] slot_uop_rob_idx; // @[issue-slot.scala:102:25] assign io_out_uop_rob_idx_0 = slot_uop_rob_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_rob_idx_0 = slot_uop_rob_idx; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_ldq_idx; // @[issue-slot.scala:102:25] assign io_out_uop_ldq_idx_0 = slot_uop_ldq_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ldq_idx_0 = slot_uop_ldq_idx; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_stq_idx; // @[issue-slot.scala:102:25] assign io_out_uop_stq_idx_0 = slot_uop_stq_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_stq_idx_0 = slot_uop_stq_idx; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_rxq_idx; // @[issue-slot.scala:102:25] assign io_out_uop_rxq_idx_0 = slot_uop_rxq_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_rxq_idx_0 = slot_uop_rxq_idx; // @[issue-slot.scala:69:7, :102:25] reg [6:0] slot_uop_pdst; // @[issue-slot.scala:102:25] assign io_out_uop_pdst_0 = slot_uop_pdst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_pdst_0 = slot_uop_pdst; // @[issue-slot.scala:69:7, :102:25] reg [6:0] slot_uop_prs1; // @[issue-slot.scala:102:25] assign io_out_uop_prs1_0 = slot_uop_prs1; // @[issue-slot.scala:69:7, :102:25] assign io_uop_prs1_0 = slot_uop_prs1; // @[issue-slot.scala:69:7, :102:25] reg [6:0] slot_uop_prs2; // @[issue-slot.scala:102:25] assign io_out_uop_prs2_0 = slot_uop_prs2; // @[issue-slot.scala:69:7, :102:25] assign io_uop_prs2_0 = slot_uop_prs2; // @[issue-slot.scala:69:7, :102:25] reg [6:0] slot_uop_prs3; // @[issue-slot.scala:102:25] assign io_out_uop_prs3_0 = slot_uop_prs3; // @[issue-slot.scala:69:7, :102:25] assign io_uop_prs3_0 = slot_uop_prs3; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_ppred; // @[issue-slot.scala:102:25] assign io_out_uop_ppred_0 = slot_uop_ppred; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ppred_0 = slot_uop_ppred; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_prs1_busy; // @[issue-slot.scala:102:25] assign io_uop_prs1_busy_0 = slot_uop_prs1_busy; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_prs2_busy; // @[issue-slot.scala:102:25] assign io_uop_prs2_busy_0 = slot_uop_prs2_busy; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_prs3_busy; // @[issue-slot.scala:102:25] assign io_uop_prs3_busy_0 = slot_uop_prs3_busy; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ppred_busy; // @[issue-slot.scala:102:25] assign io_uop_ppred_busy_0 = slot_uop_ppred_busy; // @[issue-slot.scala:69:7, :102:25] reg [6:0] slot_uop_stale_pdst; // @[issue-slot.scala:102:25] assign io_out_uop_stale_pdst_0 = slot_uop_stale_pdst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_stale_pdst_0 = slot_uop_stale_pdst; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_exception; // @[issue-slot.scala:102:25] assign io_out_uop_exception_0 = slot_uop_exception; // @[issue-slot.scala:69:7, :102:25] assign io_uop_exception_0 = slot_uop_exception; // @[issue-slot.scala:69:7, :102:25] reg [63:0] slot_uop_exc_cause; // @[issue-slot.scala:102:25] assign io_out_uop_exc_cause_0 = slot_uop_exc_cause; // @[issue-slot.scala:69:7, :102:25] assign io_uop_exc_cause_0 = slot_uop_exc_cause; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_bypassable; // @[issue-slot.scala:102:25] assign io_out_uop_bypassable_0 = slot_uop_bypassable; // @[issue-slot.scala:69:7, :102:25] assign io_uop_bypassable_0 = slot_uop_bypassable; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_mem_cmd; // @[issue-slot.scala:102:25] assign io_out_uop_mem_cmd_0 = slot_uop_mem_cmd; // @[issue-slot.scala:69:7, :102:25] assign io_uop_mem_cmd_0 = slot_uop_mem_cmd; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_mem_size; // @[issue-slot.scala:102:25] assign io_out_uop_mem_size_0 = slot_uop_mem_size; // @[issue-slot.scala:69:7, :102:25] assign io_uop_mem_size_0 = slot_uop_mem_size; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_mem_signed; // @[issue-slot.scala:102:25] assign io_out_uop_mem_signed_0 = slot_uop_mem_signed; // @[issue-slot.scala:69:7, :102:25] assign io_uop_mem_signed_0 = slot_uop_mem_signed; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_fence; // @[issue-slot.scala:102:25] assign io_out_uop_is_fence_0 = slot_uop_is_fence; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_fence_0 = slot_uop_is_fence; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_fencei; // @[issue-slot.scala:102:25] assign io_out_uop_is_fencei_0 = slot_uop_is_fencei; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_fencei_0 = slot_uop_is_fencei; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_amo; // @[issue-slot.scala:102:25] assign io_out_uop_is_amo_0 = slot_uop_is_amo; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_amo_0 = slot_uop_is_amo; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_uses_ldq; // @[issue-slot.scala:102:25] assign io_out_uop_uses_ldq_0 = slot_uop_uses_ldq; // @[issue-slot.scala:69:7, :102:25] assign io_uop_uses_ldq_0 = slot_uop_uses_ldq; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_uses_stq; // @[issue-slot.scala:102:25] assign io_out_uop_uses_stq_0 = slot_uop_uses_stq; // @[issue-slot.scala:69:7, :102:25] assign io_uop_uses_stq_0 = slot_uop_uses_stq; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_sys_pc2epc; // @[issue-slot.scala:102:25] assign io_out_uop_is_sys_pc2epc_0 = slot_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_sys_pc2epc_0 = slot_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_unique; // @[issue-slot.scala:102:25] assign io_out_uop_is_unique_0 = slot_uop_is_unique; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_unique_0 = slot_uop_is_unique; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_flush_on_commit; // @[issue-slot.scala:102:25] assign io_out_uop_flush_on_commit_0 = slot_uop_flush_on_commit; // @[issue-slot.scala:69:7, :102:25] assign io_uop_flush_on_commit_0 = slot_uop_flush_on_commit; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ldst_is_rs1; // @[issue-slot.scala:102:25] assign io_out_uop_ldst_is_rs1_0 = slot_uop_ldst_is_rs1; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ldst_is_rs1_0 = slot_uop_ldst_is_rs1; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_ldst; // @[issue-slot.scala:102:25] assign io_out_uop_ldst_0 = slot_uop_ldst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ldst_0 = slot_uop_ldst; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_lrs1; // @[issue-slot.scala:102:25] assign io_out_uop_lrs1_0 = slot_uop_lrs1; // @[issue-slot.scala:69:7, :102:25] assign io_uop_lrs1_0 = slot_uop_lrs1; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_lrs2; // @[issue-slot.scala:102:25] assign io_out_uop_lrs2_0 = slot_uop_lrs2; // @[issue-slot.scala:69:7, :102:25] assign io_uop_lrs2_0 = slot_uop_lrs2; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_lrs3; // @[issue-slot.scala:102:25] assign io_out_uop_lrs3_0 = slot_uop_lrs3; // @[issue-slot.scala:69:7, :102:25] assign io_uop_lrs3_0 = slot_uop_lrs3; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ldst_val; // @[issue-slot.scala:102:25] assign io_out_uop_ldst_val_0 = slot_uop_ldst_val; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ldst_val_0 = slot_uop_ldst_val; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_dst_rtype; // @[issue-slot.scala:102:25] assign io_out_uop_dst_rtype_0 = slot_uop_dst_rtype; // @[issue-slot.scala:69:7, :102:25] assign io_uop_dst_rtype_0 = slot_uop_dst_rtype; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_lrs1_rtype; // @[issue-slot.scala:102:25] reg [1:0] slot_uop_lrs2_rtype; // @[issue-slot.scala:102:25] reg slot_uop_frs3_en; // @[issue-slot.scala:102:25] assign io_out_uop_frs3_en_0 = slot_uop_frs3_en; // @[issue-slot.scala:69:7, :102:25] assign io_uop_frs3_en_0 = slot_uop_frs3_en; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_fp_val; // @[issue-slot.scala:102:25] assign io_out_uop_fp_val_0 = slot_uop_fp_val; // @[issue-slot.scala:69:7, :102:25] assign io_uop_fp_val_0 = slot_uop_fp_val; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_fp_single; // @[issue-slot.scala:102:25] assign io_out_uop_fp_single_0 = slot_uop_fp_single; // @[issue-slot.scala:69:7, :102:25] assign io_uop_fp_single_0 = slot_uop_fp_single; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_xcpt_pf_if; // @[issue-slot.scala:102:25] assign io_out_uop_xcpt_pf_if_0 = slot_uop_xcpt_pf_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_xcpt_pf_if_0 = slot_uop_xcpt_pf_if; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_xcpt_ae_if; // @[issue-slot.scala:102:25] assign io_out_uop_xcpt_ae_if_0 = slot_uop_xcpt_ae_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_xcpt_ae_if_0 = slot_uop_xcpt_ae_if; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_xcpt_ma_if; // @[issue-slot.scala:102:25] assign io_out_uop_xcpt_ma_if_0 = slot_uop_xcpt_ma_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_xcpt_ma_if_0 = slot_uop_xcpt_ma_if; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_bp_debug_if; // @[issue-slot.scala:102:25] assign io_out_uop_bp_debug_if_0 = slot_uop_bp_debug_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_bp_debug_if_0 = slot_uop_bp_debug_if; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_bp_xcpt_if; // @[issue-slot.scala:102:25] assign io_out_uop_bp_xcpt_if_0 = slot_uop_bp_xcpt_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_bp_xcpt_if_0 = slot_uop_bp_xcpt_if; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_debug_fsrc; // @[issue-slot.scala:102:25] assign io_out_uop_debug_fsrc_0 = slot_uop_debug_fsrc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_debug_fsrc_0 = slot_uop_debug_fsrc; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_debug_tsrc; // @[issue-slot.scala:102:25] assign io_out_uop_debug_tsrc_0 = slot_uop_debug_tsrc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_debug_tsrc_0 = slot_uop_debug_tsrc; // @[issue-slot.scala:69:7, :102:25] wire [6:0] next_uop_uopc = io_in_uop_valid_0 ? io_in_uop_bits_uopc_0 : slot_uop_uopc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [31:0] next_uop_inst = io_in_uop_valid_0 ? io_in_uop_bits_inst_0 : slot_uop_inst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [31:0] next_uop_debug_inst = io_in_uop_valid_0 ? io_in_uop_bits_debug_inst_0 : slot_uop_debug_inst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_rvc = io_in_uop_valid_0 ? io_in_uop_bits_is_rvc_0 : slot_uop_is_rvc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [39:0] next_uop_debug_pc = io_in_uop_valid_0 ? io_in_uop_bits_debug_pc_0 : slot_uop_debug_pc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [2:0] next_uop_iq_type = io_in_uop_valid_0 ? io_in_uop_bits_iq_type_0 : slot_uop_iq_type; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [9:0] next_uop_fu_code = io_in_uop_valid_0 ? io_in_uop_bits_fu_code_0 : slot_uop_fu_code; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [3:0] next_uop_ctrl_br_type = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_br_type_0 : slot_uop_ctrl_br_type; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_ctrl_op1_sel = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_op1_sel_0 : slot_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [2:0] next_uop_ctrl_op2_sel = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_op2_sel_0 : slot_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [2:0] next_uop_ctrl_imm_sel = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_imm_sel_0 : slot_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_ctrl_op_fcn = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_op_fcn_0 : slot_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ctrl_fcn_dw = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_fcn_dw_0 : slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [2:0] next_uop_ctrl_csr_cmd = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_csr_cmd_0 : slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ctrl_is_load = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_is_load_0 : slot_uop_ctrl_is_load; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ctrl_is_sta = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_is_sta_0 : slot_uop_ctrl_is_sta; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ctrl_is_std = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_is_std_0 : slot_uop_ctrl_is_std; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_iw_state = io_in_uop_valid_0 ? io_in_uop_bits_iw_state_0 : slot_uop_iw_state; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_iw_p1_poisoned = ~io_in_uop_valid_0 & slot_uop_iw_p1_poisoned; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_iw_p2_poisoned = ~io_in_uop_valid_0 & slot_uop_iw_p2_poisoned; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_br = io_in_uop_valid_0 ? io_in_uop_bits_is_br_0 : slot_uop_is_br; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_jalr = io_in_uop_valid_0 ? io_in_uop_bits_is_jalr_0 : slot_uop_is_jalr; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_jal = io_in_uop_valid_0 ? io_in_uop_bits_is_jal_0 : slot_uop_is_jal; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_sfb = io_in_uop_valid_0 ? io_in_uop_bits_is_sfb_0 : slot_uop_is_sfb; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [15:0] next_uop_br_mask = io_in_uop_valid_0 ? io_in_uop_bits_br_mask_0 : slot_uop_br_mask; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [3:0] next_uop_br_tag = io_in_uop_valid_0 ? io_in_uop_bits_br_tag_0 : slot_uop_br_tag; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_ftq_idx = io_in_uop_valid_0 ? io_in_uop_bits_ftq_idx_0 : slot_uop_ftq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_edge_inst = io_in_uop_valid_0 ? io_in_uop_bits_edge_inst_0 : slot_uop_edge_inst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_pc_lob = io_in_uop_valid_0 ? io_in_uop_bits_pc_lob_0 : slot_uop_pc_lob; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_taken = io_in_uop_valid_0 ? io_in_uop_bits_taken_0 : slot_uop_taken; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [19:0] next_uop_imm_packed = io_in_uop_valid_0 ? io_in_uop_bits_imm_packed_0 : slot_uop_imm_packed; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [11:0] next_uop_csr_addr = io_in_uop_valid_0 ? io_in_uop_bits_csr_addr_0 : slot_uop_csr_addr; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [6:0] next_uop_rob_idx = io_in_uop_valid_0 ? io_in_uop_bits_rob_idx_0 : slot_uop_rob_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_ldq_idx = io_in_uop_valid_0 ? io_in_uop_bits_ldq_idx_0 : slot_uop_ldq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_stq_idx = io_in_uop_valid_0 ? io_in_uop_bits_stq_idx_0 : slot_uop_stq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_rxq_idx = io_in_uop_valid_0 ? io_in_uop_bits_rxq_idx_0 : slot_uop_rxq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [6:0] next_uop_pdst = io_in_uop_valid_0 ? io_in_uop_bits_pdst_0 : slot_uop_pdst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [6:0] next_uop_prs1 = io_in_uop_valid_0 ? io_in_uop_bits_prs1_0 : slot_uop_prs1; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [6:0] next_uop_prs2 = io_in_uop_valid_0 ? io_in_uop_bits_prs2_0 : slot_uop_prs2; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [6:0] next_uop_prs3 = io_in_uop_valid_0 ? io_in_uop_bits_prs3_0 : slot_uop_prs3; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_ppred = io_in_uop_valid_0 ? io_in_uop_bits_ppred_0 : slot_uop_ppred; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_prs1_busy = io_in_uop_valid_0 ? io_in_uop_bits_prs1_busy_0 : slot_uop_prs1_busy; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_prs2_busy = io_in_uop_valid_0 ? io_in_uop_bits_prs2_busy_0 : slot_uop_prs2_busy; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_prs3_busy = io_in_uop_valid_0 ? io_in_uop_bits_prs3_busy_0 : slot_uop_prs3_busy; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ppred_busy = io_in_uop_valid_0 ? io_in_uop_bits_ppred_busy_0 : slot_uop_ppred_busy; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [6:0] next_uop_stale_pdst = io_in_uop_valid_0 ? io_in_uop_bits_stale_pdst_0 : slot_uop_stale_pdst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_exception = io_in_uop_valid_0 ? io_in_uop_bits_exception_0 : slot_uop_exception; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [63:0] next_uop_exc_cause = io_in_uop_valid_0 ? io_in_uop_bits_exc_cause_0 : slot_uop_exc_cause; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_bypassable = io_in_uop_valid_0 ? io_in_uop_bits_bypassable_0 : slot_uop_bypassable; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_mem_cmd = io_in_uop_valid_0 ? io_in_uop_bits_mem_cmd_0 : slot_uop_mem_cmd; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_mem_size = io_in_uop_valid_0 ? io_in_uop_bits_mem_size_0 : slot_uop_mem_size; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_mem_signed = io_in_uop_valid_0 ? io_in_uop_bits_mem_signed_0 : slot_uop_mem_signed; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_fence = io_in_uop_valid_0 ? io_in_uop_bits_is_fence_0 : slot_uop_is_fence; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_fencei = io_in_uop_valid_0 ? io_in_uop_bits_is_fencei_0 : slot_uop_is_fencei; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_amo = io_in_uop_valid_0 ? io_in_uop_bits_is_amo_0 : slot_uop_is_amo; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_uses_ldq = io_in_uop_valid_0 ? io_in_uop_bits_uses_ldq_0 : slot_uop_uses_ldq; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_uses_stq = io_in_uop_valid_0 ? io_in_uop_bits_uses_stq_0 : slot_uop_uses_stq; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_sys_pc2epc = io_in_uop_valid_0 ? io_in_uop_bits_is_sys_pc2epc_0 : slot_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_unique = io_in_uop_valid_0 ? io_in_uop_bits_is_unique_0 : slot_uop_is_unique; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_flush_on_commit = io_in_uop_valid_0 ? io_in_uop_bits_flush_on_commit_0 : slot_uop_flush_on_commit; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ldst_is_rs1 = io_in_uop_valid_0 ? io_in_uop_bits_ldst_is_rs1_0 : slot_uop_ldst_is_rs1; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_ldst = io_in_uop_valid_0 ? io_in_uop_bits_ldst_0 : slot_uop_ldst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_lrs1 = io_in_uop_valid_0 ? io_in_uop_bits_lrs1_0 : slot_uop_lrs1; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_lrs2 = io_in_uop_valid_0 ? io_in_uop_bits_lrs2_0 : slot_uop_lrs2; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_lrs3 = io_in_uop_valid_0 ? io_in_uop_bits_lrs3_0 : slot_uop_lrs3; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ldst_val = io_in_uop_valid_0 ? io_in_uop_bits_ldst_val_0 : slot_uop_ldst_val; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_dst_rtype = io_in_uop_valid_0 ? io_in_uop_bits_dst_rtype_0 : slot_uop_dst_rtype; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_lrs1_rtype = io_in_uop_valid_0 ? io_in_uop_bits_lrs1_rtype_0 : slot_uop_lrs1_rtype; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_lrs2_rtype = io_in_uop_valid_0 ? io_in_uop_bits_lrs2_rtype_0 : slot_uop_lrs2_rtype; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_frs3_en = io_in_uop_valid_0 ? io_in_uop_bits_frs3_en_0 : slot_uop_frs3_en; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_fp_val = io_in_uop_valid_0 ? io_in_uop_bits_fp_val_0 : slot_uop_fp_val; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_fp_single = io_in_uop_valid_0 ? io_in_uop_bits_fp_single_0 : slot_uop_fp_single; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_xcpt_pf_if = io_in_uop_valid_0 ? io_in_uop_bits_xcpt_pf_if_0 : slot_uop_xcpt_pf_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_xcpt_ae_if = io_in_uop_valid_0 ? io_in_uop_bits_xcpt_ae_if_0 : slot_uop_xcpt_ae_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_xcpt_ma_if = io_in_uop_valid_0 ? io_in_uop_bits_xcpt_ma_if_0 : slot_uop_xcpt_ma_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_bp_debug_if = io_in_uop_valid_0 ? io_in_uop_bits_bp_debug_if_0 : slot_uop_bp_debug_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_bp_xcpt_if = io_in_uop_valid_0 ? io_in_uop_bits_bp_xcpt_if_0 : slot_uop_bp_xcpt_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_debug_fsrc = io_in_uop_valid_0 ? io_in_uop_bits_debug_fsrc_0 : slot_uop_debug_fsrc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_debug_tsrc = io_in_uop_valid_0 ? io_in_uop_bits_debug_tsrc_0 : slot_uop_debug_tsrc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire _T_11 = state == 2'h2; // @[issue-slot.scala:86:22, :134:25] wire _T_7 = io_grant_0 & state == 2'h1 \| io_grant_0 & _T_11 & p1 & p2 & ppred; // @[issue-slot.scala:69:7, :86:22, :87:22, :88:22, :90:22, :133:{26,36,52}, :134:{15,25,40,46,52}] wire _T_12 = io_grant_0 & _T_11; // @[issue-slot.scala:69:7, :134:25, :139:25] wire _GEN = io_kill_0 \| _T_7; // @[issue-slot.scala:69:7, :102:25, :131:18, :133:52, :134:63, :139:51] wire _GEN_0 = _GEN \| ~(_T_12 & p1); // @[issue-slot.scala:87:22, :102:25, :131:18, :134:63, :139:{25,51}, :140:62, :142:17, :143:23] assign next_uopc = _GEN_0 ? slot_uop_uopc : 7'h3; // @[issue-slot.scala:82:29, :102:25, :131:18, :134:63, :139:51] assign next_lrs1_rtype = _GEN_0 ? slot_uop_lrs1_rtype : 2'h2; // @[issue-slot.scala:83:29, :102:25, :131:18, :134:63, :139:51] wire _GEN_1 = _GEN \| ~_T_12 \| p1; // @[issue-slot.scala:87:22, :102:25, :131:18, :134:63, :139:{25,51}, :140:62, :142:17] assign next_lrs2_rtype = _GEN_1 ? slot_uop_lrs2_rtype : 2'h2; // @[issue-slot.scala:84:29, :102:25, :131:18, :134:63, :139:51, :140:62, :142:17]
Generate the Verilog code corresponding to the following Chisel files. File MulRecFN.scala: /============================================================================ This Chisel source file is part of a pre-release version of the HardFloat IEEE Floating-Point Arithmetic Package, by John R. Hauser (ported from Verilog to Chisel by Andrew Waterman). Copyright 2019, 2020 The Regents of the University of California. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions, and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions, and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the University nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. =============================================================================/ package hardfloat import chisel3._ import chisel3.util._ import consts._ //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- class MulFullRawFN(expWidth: Int, sigWidth: Int) extends chisel3.RawModule { val io = IO(new Bundle { val a = Input(new RawFloat(expWidth, sigWidth)) val b = Input(new RawFloat(expWidth, sigWidth)) val invalidExc = Output(Bool()) val rawOut = Output(new RawFloat(expWidth, sigWidth2 - 1)) }) /------------------------------------------------------------------------ ------------------------------------------------------------------------/ val notSigNaN_invalidExc = (io.a.isInf && io.b.isZero) \|\| (io.a.isZero && io.b.isInf) val notNaN_isInfOut = io.a.isInf \|\| io.b.isInf val notNaN_isZeroOut = io.a.isZero \|\| io.b.isZero val notNaN_signOut = io.a.sign ^ io.b.sign val common_sExpOut = io.a.sExp + io.b.sExp - (1<<expWidth).S val common_sigOut = (io.a.sig * io.b.sig)(sigWidth2 - 1, 0) /------------------------------------------------------------------------ ------------------------------------------------------------------------/ io.invalidExc := isSigNaNRawFloat(io.a) \|\| isSigNaNRawFloat(io.b) \|\| notSigNaN_invalidExc io.rawOut.isInf := notNaN_isInfOut io.rawOut.isZero := notNaN_isZeroOut io.rawOut.sExp := common_sExpOut io.rawOut.isNaN := io.a.isNaN \|\| io.b.isNaN io.rawOut.sign := notNaN_signOut io.rawOut.sig := common_sigOut } class MulRawFN(expWidth: Int, sigWidth: Int) extends chisel3.RawModule { val io = IO(new Bundle { val a = Input(new RawFloat(expWidth, sigWidth)) val b = Input(new RawFloat(expWidth, sigWidth)) val invalidExc = Output(Bool()) val rawOut = Output(new RawFloat(expWidth, sigWidth + 2)) }) val mulFullRaw = Module(new MulFullRawFN(expWidth, sigWidth)) mulFullRaw.io.a := io.a mulFullRaw.io.b := io.b io.invalidExc := mulFullRaw.io.invalidExc io.rawOut := mulFullRaw.io.rawOut io.rawOut.sig := { val sig = mulFullRaw.io.rawOut.sig Cat(sig >> (sigWidth - 2), sig(sigWidth - 3, 0).orR) } } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- class MulRecFN(expWidth: Int, sigWidth: Int) extends chisel3.RawModule { val io = IO(new Bundle { val a = Input(UInt((expWidth + sigWidth + 1).W)) val b = Input(UInt((expWidth + sigWidth + 1).W)) val roundingMode = Input(UInt(3.W)) val detectTininess = Input(Bool()) val out = Output(UInt((expWidth + sigWidth + 1).W)) val exceptionFlags = Output(UInt(5.W)) }) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val mulRawFN = Module(new MulRawFN(expWidth, sigWidth)) mulRawFN.io.a := rawFloatFromRecFN(expWidth, sigWidth, io.a) mulRawFN.io.b := rawFloatFromRecFN(expWidth, sigWidth, io.b) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val roundRawFNToRecFN = Module(new RoundRawFNToRecFN(expWidth, sigWidth, 0)) roundRawFNToRecFN.io.invalidExc := mulRawFN.io.invalidExc roundRawFNToRecFN.io.infiniteExc := false.B roundRawFNToRecFN.io.in := mulRawFN.io.rawOut roundRawFNToRecFN.io.roundingMode := io.roundingMode roundRawFNToRecFN.io.detectTininess := io.detectTininess io.out := roundRawFNToRecFN.io.out io.exceptionFlags := roundRawFNToRecFN.io.exceptionFlags } File rawFloatFromRecFN.scala: /============================================================================ This Chisel source file is part of a pre-release version of the HardFloat IEEE Floating-Point Arithmetic Package, by John R. Hauser (with some contributions from Yunsup Lee and Andrew Waterman, mainly concerning testing). Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of California. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions, and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions, and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the University nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. =============================================================================/ package hardfloat import chisel3._ import chisel3.util._ /---------------------------------------------------------------------------- \| In the result, no more than one of 'isNaN', 'isInf', and 'isZero' will be \| set. ----------------------------------------------------------------------------*/ object rawFloatFromRecFN { def apply(expWidth: Int, sigWidth: Int, in: Bits): RawFloat = { val exp = in(expWidth + sigWidth - 1, sigWidth - 1) val isZero = exp(expWidth, expWidth - 2) === 0.U val isSpecial = exp(expWidth, expWidth - 1) === 3.U val out = Wire(new RawFloat(expWidth, sigWidth)) out.isNaN := isSpecial && exp(expWidth - 2) out.isInf := isSpecial && ! exp(expWidth - 2) out.isZero := isZero out.sign := in(expWidth + sigWidth) out.sExp := exp.zext out.sig := 0.U(1.W) ## ! isZero ## in(sigWidth - 2, 0) out } }	module MulRecFN_43( // @[MulRecFN.scala:100:7] input [32:0] io_a, // @[MulRecFN.scala:102:16] input [32:0] io_b, // @[MulRecFN.scala:102:16] output [32:0] io_out // @[MulRecFN.scala:102:16] ); wire _mulRawFN_io_invalidExc; // @[MulRecFN.scala:113:26] wire _mulRawFN_io_rawOut_isNaN; // @[MulRecFN.scala:113:26] wire _mulRawFN_io_rawOut_isInf; // @[MulRecFN.scala:113:26] wire _mulRawFN_io_rawOut_isZero; // @[MulRecFN.scala:113:26] wire _mulRawFN_io_rawOut_sign; // @[MulRecFN.scala:113:26] wire [9:0] _mulRawFN_io_rawOut_sExp; // @[MulRecFN.scala:113:26] wire [26:0] _mulRawFN_io_rawOut_sig; // @[MulRecFN.scala:113:26] wire [32:0] io_a_0 = io_a; // @[MulRecFN.scala:100:7] wire [32:0] io_b_0 = io_b; // @[MulRecFN.scala:100:7] wire io_detectTininess = 1'h1; // @[MulRecFN.scala:100:7, :102:16, :121:15] wire [2:0] io_roundingMode = 3'h0; // @[MulRecFN.scala:100:7, :102:16, :121:15] wire [32:0] io_out_0; // @[MulRecFN.scala:100:7] wire [4:0] io_exceptionFlags; // @[MulRecFN.scala:100:7] wire [8:0] mulRawFN_io_a_exp = io_a_0[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _mulRawFN_io_a_isZero_T = mulRawFN_io_a_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire mulRawFN_io_a_isZero = _mulRawFN_io_a_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire mulRawFN_io_a_out_isZero = mulRawFN_io_a_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _mulRawFN_io_a_isSpecial_T = mulRawFN_io_a_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire mulRawFN_io_a_isSpecial = &_mulRawFN_io_a_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _mulRawFN_io_a_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33] wire _mulRawFN_io_a_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33] wire _mulRawFN_io_a_out_sign_T; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _mulRawFN_io_a_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _mulRawFN_io_a_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44] wire mulRawFN_io_a_out_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire mulRawFN_io_a_out_isInf; // @[rawFloatFromRecFN.scala:55:23] wire mulRawFN_io_a_out_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] mulRawFN_io_a_out_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] mulRawFN_io_a_out_sig; // @[rawFloatFromRecFN.scala:55:23] wire _mulRawFN_io_a_out_isNaN_T = mulRawFN_io_a_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _mulRawFN_io_a_out_isInf_T = mulRawFN_io_a_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _mulRawFN_io_a_out_isNaN_T_1 = mulRawFN_io_a_isSpecial & _mulRawFN_io_a_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign mulRawFN_io_a_out_isNaN = _mulRawFN_io_a_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _mulRawFN_io_a_out_isInf_T_1 = ~_mulRawFN_io_a_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _mulRawFN_io_a_out_isInf_T_2 = mulRawFN_io_a_isSpecial & _mulRawFN_io_a_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign mulRawFN_io_a_out_isInf = _mulRawFN_io_a_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _mulRawFN_io_a_out_sign_T = io_a_0[32]; // @[rawFloatFromRecFN.scala:59:25] assign mulRawFN_io_a_out_sign = _mulRawFN_io_a_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _mulRawFN_io_a_out_sExp_T = {1'h0, mulRawFN_io_a_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign mulRawFN_io_a_out_sExp = _mulRawFN_io_a_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _mulRawFN_io_a_out_sig_T = ~mulRawFN_io_a_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _mulRawFN_io_a_out_sig_T_1 = {1'h0, _mulRawFN_io_a_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _mulRawFN_io_a_out_sig_T_2 = io_a_0[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _mulRawFN_io_a_out_sig_T_3 = {_mulRawFN_io_a_out_sig_T_1, _mulRawFN_io_a_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign mulRawFN_io_a_out_sig = _mulRawFN_io_a_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire [8:0] mulRawFN_io_b_exp = io_b_0[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _mulRawFN_io_b_isZero_T = mulRawFN_io_b_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire mulRawFN_io_b_isZero = _mulRawFN_io_b_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire mulRawFN_io_b_out_isZero = mulRawFN_io_b_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _mulRawFN_io_b_isSpecial_T = mulRawFN_io_b_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire mulRawFN_io_b_isSpecial = &_mulRawFN_io_b_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _mulRawFN_io_b_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33] wire _mulRawFN_io_b_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33] wire _mulRawFN_io_b_out_sign_T; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _mulRawFN_io_b_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _mulRawFN_io_b_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44] wire mulRawFN_io_b_out_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire mulRawFN_io_b_out_isInf; // @[rawFloatFromRecFN.scala:55:23] wire mulRawFN_io_b_out_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] mulRawFN_io_b_out_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] mulRawFN_io_b_out_sig; // @[rawFloatFromRecFN.scala:55:23] wire _mulRawFN_io_b_out_isNaN_T = mulRawFN_io_b_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _mulRawFN_io_b_out_isInf_T = mulRawFN_io_b_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _mulRawFN_io_b_out_isNaN_T_1 = mulRawFN_io_b_isSpecial & _mulRawFN_io_b_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign mulRawFN_io_b_out_isNaN = _mulRawFN_io_b_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _mulRawFN_io_b_out_isInf_T_1 = ~_mulRawFN_io_b_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _mulRawFN_io_b_out_isInf_T_2 = mulRawFN_io_b_isSpecial & _mulRawFN_io_b_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign mulRawFN_io_b_out_isInf = _mulRawFN_io_b_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _mulRawFN_io_b_out_sign_T = io_b_0[32]; // @[rawFloatFromRecFN.scala:59:25] assign mulRawFN_io_b_out_sign = _mulRawFN_io_b_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _mulRawFN_io_b_out_sExp_T = {1'h0, mulRawFN_io_b_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign mulRawFN_io_b_out_sExp = _mulRawFN_io_b_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _mulRawFN_io_b_out_sig_T = ~mulRawFN_io_b_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _mulRawFN_io_b_out_sig_T_1 = {1'h0, _mulRawFN_io_b_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _mulRawFN_io_b_out_sig_T_2 = io_b_0[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _mulRawFN_io_b_out_sig_T_3 = {_mulRawFN_io_b_out_sig_T_1, _mulRawFN_io_b_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign mulRawFN_io_b_out_sig = _mulRawFN_io_b_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44] MulRawFN_43 mulRawFN ( // @[MulRecFN.scala:113:26] .io_a_isNaN (mulRawFN_io_a_out_isNaN), // @[rawFloatFromRecFN.scala:55:23] .io_a_isInf (mulRawFN_io_a_out_isInf), // @[rawFloatFromRecFN.scala:55:23] .io_a_isZero (mulRawFN_io_a_out_isZero), // @[rawFloatFromRecFN.scala:55:23] .io_a_sign (mulRawFN_io_a_out_sign), // @[rawFloatFromRecFN.scala:55:23] .io_a_sExp (mulRawFN_io_a_out_sExp), // @[rawFloatFromRecFN.scala:55:23] .io_a_sig (mulRawFN_io_a_out_sig), // @[rawFloatFromRecFN.scala:55:23] .io_b_isNaN (mulRawFN_io_b_out_isNaN), // @[rawFloatFromRecFN.scala:55:23] .io_b_isInf (mulRawFN_io_b_out_isInf), // @[rawFloatFromRecFN.scala:55:23] .io_b_isZero (mulRawFN_io_b_out_isZero), // @[rawFloatFromRecFN.scala:55:23] .io_b_sign (mulRawFN_io_b_out_sign), // @[rawFloatFromRecFN.scala:55:23] .io_b_sExp (mulRawFN_io_b_out_sExp), // @[rawFloatFromRecFN.scala:55:23] .io_b_sig (mulRawFN_io_b_out_sig), // @[rawFloatFromRecFN.scala:55:23] .io_invalidExc (_mulRawFN_io_invalidExc), .io_rawOut_isNaN (_mulRawFN_io_rawOut_isNaN), .io_rawOut_isInf (_mulRawFN_io_rawOut_isInf), .io_rawOut_isZero (_mulRawFN_io_rawOut_isZero), .io_rawOut_sign (_mulRawFN_io_rawOut_sign), .io_rawOut_sExp (_mulRawFN_io_rawOut_sExp), .io_rawOut_sig (_mulRawFN_io_rawOut_sig) ); // @[MulRecFN.scala:113:26] RoundRawFNToRecFN_e8_s24_117 roundRawFNToRecFN ( // @[MulRecFN.scala:121:15] .io_invalidExc (_mulRawFN_io_invalidExc), // @[MulRecFN.scala:113:26] .io_in_isNaN (_mulRawFN_io_rawOut_isNaN), // @[MulRecFN.scala:113:26] .io_in_isInf (_mulRawFN_io_rawOut_isInf), // @[MulRecFN.scala:113:26] .io_in_isZero (_mulRawFN_io_rawOut_isZero), // @[MulRecFN.scala:113:26] .io_in_sign (_mulRawFN_io_rawOut_sign), // @[MulRecFN.scala:113:26] .io_in_sExp (_mulRawFN_io_rawOut_sExp), // @[MulRecFN.scala:113:26] .io_in_sig (_mulRawFN_io_rawOut_sig), // @[MulRecFN.scala:113:26] .io_out (io_out_0), .io_exceptionFlags (io_exceptionFlags) ); // @[MulRecFN.scala:121:15] assign io_out = io_out_0; // @[MulRecFN.scala:100:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File RegMapFIFO.scala: package sifive.blocks.util import chisel3._ import chisel3.util._ import freechips.rocketchip.regmapper._ // MSB indicates full status object NonBlockingEnqueue { def apply(enq: DecoupledIO[UInt], regWidth: Int = 32): Seq[RegField] = { val enqWidth = enq.bits.getWidth val quash = Wire(Bool()) require(enqWidth > 0) require(regWidth > enqWidth) Seq( RegField(enqWidth, RegReadFn(0.U), RegWriteFn((valid, data) => { enq.valid := valid && !quash enq.bits := data true.B }), RegFieldDesc("data", "Transmit data", access=RegFieldAccessType.W)), RegField(regWidth - enqWidth - 1), RegField(1, !enq.ready, RegWriteFn((valid, data) => { quash := valid && data(0) true.B }), RegFieldDesc("full", "Transmit FIFO full", access=RegFieldAccessType.R, volatile=true))) } } // MSB indicates empty status object NonBlockingDequeue { def apply(deq: DecoupledIO[UInt], regWidth: Int = 32): Seq[RegField] = { val deqWidth = deq.bits.getWidth require(deqWidth > 0) require(regWidth > deqWidth) Seq( RegField.r(deqWidth, RegReadFn(ready => { deq.ready := ready (true.B, deq.bits) }), RegFieldDesc("data", "Receive data", volatile=true)), RegField(regWidth - deqWidth - 1), RegField.r(1, !deq.valid, RegFieldDesc("empty", "Receive FIFO empty", volatile=true))) } } /* Copyright 2016 SiFive, Inc. Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License. / File Buffer.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.diplomacy.BufferParams class TLBufferNode ( a: BufferParams, b: BufferParams, c: BufferParams, d: BufferParams, e: BufferParams)(implicit valName: ValName) extends TLAdapterNode( clientFn = { p => p.v1copy(minLatency = p.minLatency + b.latency + c.latency) }, managerFn = { p => p.v1copy(minLatency = p.minLatency + a.latency + d.latency) } ) { override lazy val nodedebugstring = s"a:${a.toString}, b:${b.toString}, c:${c.toString}, d:${d.toString}, e:${e.toString}" override def circuitIdentity = List(a,b,c,d,e).forall(_ == BufferParams.none) } class TLBuffer( a: BufferParams, b: BufferParams, c: BufferParams, d: BufferParams, e: BufferParams)(implicit p: Parameters) extends LazyModule { def this(ace: BufferParams, bd: BufferParams)(implicit p: Parameters) = this(ace, bd, ace, bd, ace) def this(abcde: BufferParams)(implicit p: Parameters) = this(abcde, abcde) def this()(implicit p: Parameters) = this(BufferParams.default) val node = new TLBufferNode(a, b, c, d, e) lazy val module = new Impl class Impl extends LazyModuleImp(this) { def headBundle = node.out.head._2.bundle override def desiredName = (Seq("TLBuffer") ++ node.out.headOption.map(_._2.bundle.shortName)).mkString("_") (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out.a <> a(in .a) in .d <> d(out.d) if (edgeOut.manager.anySupportAcquireB && edgeOut.client.anySupportProbe) { in .b <> b(out.b) out.c <> c(in .c) out.e <> e(in .e) } else { in.b.valid := false.B in.c.ready := true.B in.e.ready := true.B out.b.ready := true.B out.c.valid := false.B out.e.valid := false.B } } } } object TLBuffer { def apply() (implicit p: Parameters): TLNode = apply(BufferParams.default) def apply(abcde: BufferParams) (implicit p: Parameters): TLNode = apply(abcde, abcde) def apply(ace: BufferParams, bd: BufferParams)(implicit p: Parameters): TLNode = apply(ace, bd, ace, bd, ace) def apply( a: BufferParams, b: BufferParams, c: BufferParams, d: BufferParams, e: BufferParams)(implicit p: Parameters): TLNode = { val buffer = LazyModule(new TLBuffer(a, b, c, d, e)) buffer.node } def chain(depth: Int, name: Option[String] = None)(implicit p: Parameters): Seq[TLNode] = { val buffers = Seq.fill(depth) { LazyModule(new TLBuffer()) } name.foreach { n => buffers.zipWithIndex.foreach { case (b, i) => b.suggestName(s"${n}_${i}") } } buffers.map(_.node) } def chainNode(depth: Int, name: Option[String] = None)(implicit p: Parameters): TLNode = { chain(depth, name) .reduceLeftOption(_ :=* _) .getOrElse(TLNameNode("no_buffer")) } } File UART.scala: package sifive.blocks.devices.uart import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.{Field, Parameters} import freechips.rocketchip.diplomacy._ import freechips.rocketchip.interrupts._ import freechips.rocketchip.prci._ import freechips.rocketchip.regmapper._ import freechips.rocketchip.subsystem._ import freechips.rocketchip.tilelink._ import freechips.rocketchip.devices.tilelink._ import freechips.rocketchip.util._ import sifive.blocks.util._ /** UART parameters * * @param address uart device TL base address * @param dataBits number of bits in data frame * @param stopBits number of stop bits * @param divisorBits width of baud rate divisor * @param oversample constructs the times of sampling for every data bit * @param nSamples number of reserved Rx sampling result for decide one data bit * @param nTxEntries number of entries in fifo between TL bus and Tx * @param nRxEntries number of entries in fifo between TL bus and Rx * @param includeFourWire additional CTS/RTS ports for flow control * @param includeParity parity support * @param includeIndependentParity Tx and Rx have opposite parity modes * @param initBaudRate initial baud rate * * @note baud rate divisor = clk frequency / baud rate. It means the number of clk period for one data bit. * Calculated in [[UARTAttachParams.attachTo()]] * * @example To configure a 8N1 UART with features below: * {{{ * 8 entries of Tx and Rx fifo * Baud rate = 115200 * Rx samples each data bit 16 times * Uses 3 sample result for each data bit * }}} * Set the stopBits as below and keep the other parameter unchanged * {{{ * stopBits = 1 * }}} * / case class UARTParams( address: BigInt, dataBits: Int = 8, stopBits: Int = 2, divisorBits: Int = 16, oversample: Int = 4, nSamples: Int = 3, nTxEntries: Int = 8, nRxEntries: Int = 8, includeFourWire: Boolean = false, includeParity: Boolean = false, includeIndependentParity: Boolean = false, // Tx and Rx have opposite parity modes initBaudRate: BigInt = BigInt(115200), ) extends DeviceParams { def oversampleFactor = 1 << oversample require(divisorBits > oversample) require(oversampleFactor > nSamples) require((dataBits == 8) \|\| (dataBits == 9)) } class UARTPortIO(val c: UARTParams) extends Bundle { val txd = Output(Bool()) val rxd = Input(Bool()) val cts_n = c.includeFourWire.option(Input(Bool())) val rts_n = c.includeFourWire.option(Output(Bool())) } class UARTInterrupts extends Bundle { val rxwm = Bool() val txwm = Bool() } //abstract class UART(busWidthBytes: Int, val c: UARTParams, divisorInit: Int = 0) /* UART Module organizes Tx and Rx module with fifo and generates control signals for them according to CSRs and UART parameters. * * ==Component== * - Tx * - Tx fifo * - Rx * - Rx fifo * - TL bus to soc * * ==IO== * [[UARTPortIO]] * * ==Datapass== * {{{ * TL bus -> Tx fifo -> Tx * TL bus <- Rx fifo <- Rx * }}} * * @param divisorInit: number of clk period for one data bit / class UART(busWidthBytes: Int, val c: UARTParams, divisorInit: Int = 0) (implicit p: Parameters) extends IORegisterRouter( RegisterRouterParams( name = "serial", compat = Seq("sifive,uart0"), base = c.address, beatBytes = busWidthBytes), new UARTPortIO(c)) //with HasInterruptSources { with HasInterruptSources with HasTLControlRegMap { def nInterrupts = 1 + c.includeParity.toInt ResourceBinding { Resource(ResourceAnchors.aliases, "uart").bind(ResourceAlias(device.label)) } require(divisorInit != 0, "UART divisor wasn't initialized during instantiation") require(divisorInit >> c.divisorBits == 0, s"UART divisor reg (width $c.divisorBits) not wide enough to hold $divisorInit") lazy val module = new LazyModuleImp(this) { val txm = Module(new UARTTx(c)) val txq = Module(new Queue(UInt(c.dataBits.W), c.nTxEntries)) val rxm = Module(new UARTRx(c)) val rxq = Module(new Queue(UInt(c.dataBits.W), c.nRxEntries)) val div = RegInit(divisorInit.U(c.divisorBits.W)) private val stopCountBits = log2Up(c.stopBits) private val txCountBits = log2Floor(c.nTxEntries) + 1 private val rxCountBits = log2Floor(c.nRxEntries) + 1 val txen = RegInit(false.B) val rxen = RegInit(false.B) val enwire4 = RegInit(false.B) val invpol = RegInit(false.B) val enparity = RegInit(false.B) val parity = RegInit(false.B) // Odd parity - 1 , Even parity - 0 val errorparity = RegInit(false.B) val errie = RegInit(false.B) val txwm = RegInit(0.U(txCountBits.W)) val rxwm = RegInit(0.U(rxCountBits.W)) val nstop = RegInit(0.U(stopCountBits.W)) val data8or9 = RegInit(true.B) if (c.includeFourWire){ txm.io.en := txen && (!port.cts_n.get \|\| !enwire4) txm.io.cts_n.get := port.cts_n.get } else txm.io.en := txen txm.io.in <> txq.io.deq txm.io.div := div txm.io.nstop := nstop port.txd := txm.io.out if (c.dataBits == 9) { txm.io.data8or9.get := data8or9 rxm.io.data8or9.get := data8or9 } rxm.io.en := rxen rxm.io.in := port.rxd rxq.io.enq.valid := rxm.io.out.valid rxq.io.enq.bits := rxm.io.out.bits rxm.io.div := div val tx_busy = (txm.io.tx_busy \|\| txq.io.count.orR) && txen port.rts_n.foreach { r => r := Mux(enwire4, !(rxq.io.count < c.nRxEntries.U), tx_busy ^ invpol) } if (c.includeParity) { txm.io.enparity.get := enparity txm.io.parity.get := parity rxm.io.parity.get := parity ^ c.includeIndependentParity.B // independent parity on tx and rx rxm.io.enparity.get := enparity errorparity := rxm.io.errorparity.get \|\| errorparity interrupts(1) := errorparity && errie } val ie = RegInit(0.U.asTypeOf(new UARTInterrupts())) val ip = Wire(new UARTInterrupts) ip.txwm := (txq.io.count < txwm) ip.rxwm := (rxq.io.count > rxwm) interrupts(0) := (ip.txwm && ie.txwm) \|\| (ip.rxwm && ie.rxwm) val mapping = Seq( UARTCtrlRegs.txfifo -> RegFieldGroup("txdata",Some("Transmit data"), NonBlockingEnqueue(txq.io.enq)), UARTCtrlRegs.rxfifo -> RegFieldGroup("rxdata",Some("Receive data"), NonBlockingDequeue(rxq.io.deq)), UARTCtrlRegs.txctrl -> RegFieldGroup("txctrl",Some("Serial transmit control"),Seq( RegField(1, txen, RegFieldDesc("txen","Transmit enable", reset=Some(0))), RegField(stopCountBits, nstop, RegFieldDesc("nstop","Number of stop bits", reset=Some(0))))), UARTCtrlRegs.rxctrl -> Seq(RegField(1, rxen, RegFieldDesc("rxen","Receive enable", reset=Some(0)))), UARTCtrlRegs.txmark -> Seq(RegField(txCountBits, txwm, RegFieldDesc("txcnt","Transmit watermark level", reset=Some(0)))), UARTCtrlRegs.rxmark -> Seq(RegField(rxCountBits, rxwm, RegFieldDesc("rxcnt","Receive watermark level", reset=Some(0)))), UARTCtrlRegs.ie -> RegFieldGroup("ie",Some("Serial interrupt enable"),Seq( RegField(1, ie.txwm, RegFieldDesc("txwm_ie","Transmit watermark interrupt enable", reset=Some(0))), RegField(1, ie.rxwm, RegFieldDesc("rxwm_ie","Receive watermark interrupt enable", reset=Some(0))))), UARTCtrlRegs.ip -> RegFieldGroup("ip",Some("Serial interrupt pending"),Seq( RegField.r(1, ip.txwm, RegFieldDesc("txwm_ip","Transmit watermark interrupt pending", volatile=true)), RegField.r(1, ip.rxwm, RegFieldDesc("rxwm_ip","Receive watermark interrupt pending", volatile=true)))), UARTCtrlRegs.div -> Seq( RegField(c.divisorBits, div, RegFieldDesc("div","Baud rate divisor",reset=Some(divisorInit)))) ) val optionalparity = if (c.includeParity) Seq( UARTCtrlRegs.parity -> RegFieldGroup("paritygenandcheck",Some("Odd/Even Parity Generation/Checking"),Seq( RegField(1, enparity, RegFieldDesc("enparity","Enable Parity Generation/Checking", reset=Some(0))), RegField(1, parity, RegFieldDesc("parity","Odd(1)/Even(0) Parity", reset=Some(0))), RegField(1, errorparity, RegFieldDesc("errorparity","Parity Status Sticky Bit", reset=Some(0))), RegField(1, errie, RegFieldDesc("errie","Interrupt on error in parity enable", reset=Some(0)))))) else Nil val optionalwire4 = if (c.includeFourWire) Seq( UARTCtrlRegs.wire4 -> RegFieldGroup("wire4",Some("Configure Clear-to-send / Request-to-send ports / RS-485"),Seq( RegField(1, enwire4, RegFieldDesc("enwire4","Enable CTS/RTS(1) or RS-485(0)", reset=Some(0))), RegField(1, invpol, RegFieldDesc("invpol","Invert polarity of RTS in RS-485 mode", reset=Some(0))) ))) else Nil val optional8or9 = if (c.dataBits == 9) Seq( UARTCtrlRegs.either8or9 -> RegFieldGroup("ConfigurableDataBits",Some("Configure number of data bits to be transmitted"),Seq( RegField(1, data8or9, RegFieldDesc("databits8or9","Data Bits to be 8(1) or 9(0)", reset=Some(1)))))) else Nil regmap(mapping ++ optionalparity ++ optionalwire4 ++ optional8or9:_) } } class TLUART(busWidthBytes: Int, params: UARTParams, divinit: Int)(implicit p: Parameters) extends UART(busWidthBytes, params, divinit) with HasTLControlRegMap case class UARTLocated(loc: HierarchicalLocation) extends Field[Seq[UARTAttachParams]](Nil) case class UARTAttachParams( device: UARTParams, controlWhere: TLBusWrapperLocation = PBUS, blockerAddr: Option[BigInt] = None, controlXType: ClockCrossingType = NoCrossing, intXType: ClockCrossingType = NoCrossing) extends DeviceAttachParams { def attachTo(where: Attachable)(implicit p: Parameters): TLUART = where { val name = s"uart_${UART.nextId()}" val tlbus = where.locateTLBusWrapper(controlWhere) val divinit = (tlbus.dtsFrequency.get / device.initBaudRate).toInt val uartClockDomainWrapper = LazyModule(new ClockSinkDomain(take = None, name = Some("TLUART"))) val uart = uartClockDomainWrapper { LazyModule(new TLUART(tlbus.beatBytes, device, divinit)) } uart.suggestName(name) tlbus.coupleTo(s"device_named_$name") { bus => val blockerOpt = blockerAddr.map { a => val blocker = LazyModule(new TLClockBlocker(BasicBusBlockerParams(a, tlbus.beatBytes, tlbus.beatBytes))) tlbus.coupleTo(s"bus_blocker_for_$name") { blocker.controlNode := TLFragmenter(tlbus, Some("UART_Blocker")) := _ } blocker } uartClockDomainWrapper.clockNode := (controlXType match { case _: SynchronousCrossing => tlbus.dtsClk.map(_.bind(uart.device)) tlbus.fixedClockNode case _: RationalCrossing => tlbus.clockNode case _: AsynchronousCrossing => val uartClockGroup = ClockGroup() uartClockGroup := where.allClockGroupsNode blockerOpt.map { _.clockNode := uartClockGroup } .getOrElse { uartClockGroup } }) (uart.controlXing(controlXType) := TLFragmenter(tlbus, Some("UART")) := blockerOpt.map { _.node := bus } .getOrElse { bus }) } (intXType match { case _: SynchronousCrossing => where.ibus.fromSync case _: RationalCrossing => where.ibus.fromRational case _: AsynchronousCrossing => where.ibus.fromAsync }) := uart.intXing(intXType) uart } } object UART { val nextId = { var i = -1; () => { i += 1; i} } def makePort(node: BundleBridgeSource[UARTPortIO], name: String)(implicit p: Parameters): ModuleValue[UARTPortIO] = { val uartNode = node.makeSink() InModuleBody { uartNode.makeIO()(ValName(name)) } } def tieoff(port: UARTPortIO) { port.rxd := 1.U if (port.c.includeFourWire) { port.cts_n.foreach { ct => ct := false.B } // active-low } } def loopback(port: UARTPortIO) { port.rxd := port.txd if (port.c.includeFourWire) { port.cts_n.get := port.rts_n.get } } } /* Copyright 2016 SiFive, Inc. Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License. / File Crossing.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.interrupts import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.util.{SynchronizerShiftReg, AsyncResetReg} @deprecated("IntXing does not ensure interrupt source is glitch free. Use IntSyncSource and IntSyncSink", "rocket-chip 1.2") class IntXing(sync: Int = 3)(implicit p: Parameters) extends LazyModule { val intnode = IntAdapterNode() lazy val module = new Impl class Impl extends LazyModuleImp(this) { (intnode.in zip intnode.out) foreach { case ((in, _), (out, _)) => out := SynchronizerShiftReg(in, sync) } } } object IntSyncCrossingSource { def apply(alreadyRegistered: Boolean = false)(implicit p: Parameters) = { val intsource = LazyModule(new IntSyncCrossingSource(alreadyRegistered)) intsource.node } } class IntSyncCrossingSource(alreadyRegistered: Boolean = false)(implicit p: Parameters) extends LazyModule { val node = IntSyncSourceNode(alreadyRegistered) lazy val module = if (alreadyRegistered) (new ImplRegistered) else (new Impl) class Impl extends LazyModuleImp(this) { def outSize = node.out.headOption.map(_._1.sync.size).getOrElse(0) override def desiredName = s"IntSyncCrossingSource_n${node.out.size}x${outSize}" (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out.sync := AsyncResetReg(Cat(in.reverse)).asBools } } class ImplRegistered extends LazyRawModuleImp(this) { def outSize = node.out.headOption.map(_._1.sync.size).getOrElse(0) override def desiredName = s"IntSyncCrossingSource_n${node.out.size}x${outSize}_Registered" (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out.sync := in } } } object IntSyncCrossingSink { @deprecated("IntSyncCrossingSink which used the `sync` parameter to determine crossing type is deprecated. Use IntSyncAsyncCrossingSink, IntSyncRationalCrossingSink, or IntSyncSyncCrossingSink instead for > 1, 1, and 0 sync values respectively", "rocket-chip 1.2") def apply(sync: Int = 3)(implicit p: Parameters) = { val intsink = LazyModule(new IntSyncAsyncCrossingSink(sync)) intsink.node } } class IntSyncAsyncCrossingSink(sync: Int = 3)(implicit p: Parameters) extends LazyModule { val node = IntSyncSinkNode(sync) lazy val module = new Impl class Impl extends LazyModuleImp(this) { override def desiredName = s"IntSyncAsyncCrossingSink_n${node.out.size}x${node.out.head._1.size}" (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out := SynchronizerShiftReg(in.sync, sync) } } } object IntSyncAsyncCrossingSink { def apply(sync: Int = 3)(implicit p: Parameters) = { val intsink = LazyModule(new IntSyncAsyncCrossingSink(sync)) intsink.node } } class IntSyncSyncCrossingSink()(implicit p: Parameters) extends LazyModule { val node = IntSyncSinkNode(0) lazy val module = new Impl class Impl extends LazyRawModuleImp(this) { def outSize = node.out.headOption.map(_._1.size).getOrElse(0) override def desiredName = s"IntSyncSyncCrossingSink_n${node.out.size}x${outSize}" (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out := in.sync } } } object IntSyncSyncCrossingSink { def apply()(implicit p: Parameters) = { val intsink = LazyModule(new IntSyncSyncCrossingSink()) intsink.node } } class IntSyncRationalCrossingSink()(implicit p: Parameters) extends LazyModule { val node = IntSyncSinkNode(1) lazy val module = new Impl class Impl extends LazyModuleImp(this) { def outSize = node.out.headOption.map(_._1.size).getOrElse(0) override def desiredName = s"IntSyncRationalCrossingSink_n${node.out.size}x${outSize}" (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out := RegNext(in.sync) } } } object IntSyncRationalCrossingSink { def apply()(implicit p: Parameters) = { val intsink = LazyModule(new IntSyncRationalCrossingSink()) intsink.node } } File Nodes.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.nodes._ import freechips.rocketchip.util.{AsyncQueueParams,RationalDirection} case object TLMonitorBuilder extends Field[TLMonitorArgs => TLMonitorBase](args => new TLMonitor(args)) object TLImp extends NodeImp[TLMasterPortParameters, TLSlavePortParameters, TLEdgeOut, TLEdgeIn, TLBundle] { def edgeO(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeOut(pd, pu, p, sourceInfo) def edgeI(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeIn (pd, pu, p, sourceInfo) def bundleO(eo: TLEdgeOut) = TLBundle(eo.bundle) def bundleI(ei: TLEdgeIn) = TLBundle(ei.bundle) def render(ei: TLEdgeIn) = RenderedEdge(colour = "#000000" / black /, label = (ei.manager.beatBytes 8).toString) override def monitor(bundle: TLBundle, edge: TLEdgeIn): Unit = { val monitor = Module(edge.params(TLMonitorBuilder)(TLMonitorArgs(edge))) monitor.io.in := bundle } override def mixO(pd: TLMasterPortParameters, node: OutwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLMasterPortParameters = pd.v1copy(clients = pd.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }) override def mixI(pu: TLSlavePortParameters, node: InwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLSlavePortParameters = pu.v1copy(managers = pu.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }) } trait TLFormatNode extends FormatNode[TLEdgeIn, TLEdgeOut] case class TLClientNode(portParams: Seq[TLMasterPortParameters])(implicit valName: ValName) extends SourceNode(TLImp)(portParams) with TLFormatNode case class TLManagerNode(portParams: Seq[TLSlavePortParameters])(implicit valName: ValName) extends SinkNode(TLImp)(portParams) with TLFormatNode case class TLAdapterNode( clientFn: TLMasterPortParameters => TLMasterPortParameters = { s => s }, managerFn: TLSlavePortParameters => TLSlavePortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLImp)(clientFn, managerFn) with TLFormatNode case class TLJunctionNode( clientFn: Seq[TLMasterPortParameters] => Seq[TLMasterPortParameters], managerFn: Seq[TLSlavePortParameters] => Seq[TLSlavePortParameters])( implicit valName: ValName) extends JunctionNode(TLImp)(clientFn, managerFn) with TLFormatNode case class TLIdentityNode()(implicit valName: ValName) extends IdentityNode(TLImp)() with TLFormatNode object TLNameNode { def apply(name: ValName) = TLIdentityNode()(name) def apply(name: Option[String]): TLIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLIdentityNode = apply(Some(name)) } case class TLEphemeralNode()(implicit valName: ValName) extends EphemeralNode(TLImp)() object TLTempNode { def apply(): TLEphemeralNode = TLEphemeralNode()(ValName("temp")) } case class TLNexusNode( clientFn: Seq[TLMasterPortParameters] => TLMasterPortParameters, managerFn: Seq[TLSlavePortParameters] => TLSlavePortParameters)( implicit valName: ValName) extends NexusNode(TLImp)(clientFn, managerFn) with TLFormatNode abstract class TLCustomNode(implicit valName: ValName) extends CustomNode(TLImp) with TLFormatNode // Asynchronous crossings trait TLAsyncFormatNode extends FormatNode[TLAsyncEdgeParameters, TLAsyncEdgeParameters] object TLAsyncImp extends SimpleNodeImp[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncEdgeParameters, TLAsyncBundle] { def edge(pd: TLAsyncClientPortParameters, pu: TLAsyncManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLAsyncEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLAsyncEdgeParameters) = new TLAsyncBundle(e.bundle) def render(e: TLAsyncEdgeParameters) = RenderedEdge(colour = "#ff0000" /* red /, label = e.manager.async.depth.toString) override def mixO(pd: TLAsyncClientPortParameters, node: OutwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLAsyncManagerPortParameters, node: InwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLAsyncAdapterNode( clientFn: TLAsyncClientPortParameters => TLAsyncClientPortParameters = { s => s }, managerFn: TLAsyncManagerPortParameters => TLAsyncManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLAsyncImp)(clientFn, managerFn) with TLAsyncFormatNode case class TLAsyncIdentityNode()(implicit valName: ValName) extends IdentityNode(TLAsyncImp)() with TLAsyncFormatNode object TLAsyncNameNode { def apply(name: ValName) = TLAsyncIdentityNode()(name) def apply(name: Option[String]): TLAsyncIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLAsyncIdentityNode = apply(Some(name)) } case class TLAsyncSourceNode(sync: Option[Int])(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLAsyncImp)( dFn = { p => TLAsyncClientPortParameters(p) }, uFn = { p => p.base.v1copy(minLatency = p.base.minLatency + sync.getOrElse(p.async.sync)) }) with FormatNode[TLEdgeIn, TLAsyncEdgeParameters] // discard cycles in other clock domain case class TLAsyncSinkNode(async: AsyncQueueParams)(implicit valName: ValName) extends MixedAdapterNode(TLAsyncImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = p.base.minLatency + async.sync) }, uFn = { p => TLAsyncManagerPortParameters(async, p) }) with FormatNode[TLAsyncEdgeParameters, TLEdgeOut] // Rationally related crossings trait TLRationalFormatNode extends FormatNode[TLRationalEdgeParameters, TLRationalEdgeParameters] object TLRationalImp extends SimpleNodeImp[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalEdgeParameters, TLRationalBundle] { def edge(pd: TLRationalClientPortParameters, pu: TLRationalManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLRationalEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLRationalEdgeParameters) = new TLRationalBundle(e.bundle) def render(e: TLRationalEdgeParameters) = RenderedEdge(colour = "#00ff00" / green /) override def mixO(pd: TLRationalClientPortParameters, node: OutwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLRationalManagerPortParameters, node: InwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLRationalAdapterNode( clientFn: TLRationalClientPortParameters => TLRationalClientPortParameters = { s => s }, managerFn: TLRationalManagerPortParameters => TLRationalManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLRationalImp)(clientFn, managerFn) with TLRationalFormatNode case class TLRationalIdentityNode()(implicit valName: ValName) extends IdentityNode(TLRationalImp)() with TLRationalFormatNode object TLRationalNameNode { def apply(name: ValName) = TLRationalIdentityNode()(name) def apply(name: Option[String]): TLRationalIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLRationalIdentityNode = apply(Some(name)) } case class TLRationalSourceNode()(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLRationalImp)( dFn = { p => TLRationalClientPortParameters(p) }, uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLRationalEdgeParameters] // discard cycles from other clock domain case class TLRationalSinkNode(direction: RationalDirection)(implicit valName: ValName) extends MixedAdapterNode(TLRationalImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = 1) }, uFn = { p => TLRationalManagerPortParameters(direction, p) }) with FormatNode[TLRationalEdgeParameters, TLEdgeOut] // Credited version of TileLink channels trait TLCreditedFormatNode extends FormatNode[TLCreditedEdgeParameters, TLCreditedEdgeParameters] object TLCreditedImp extends SimpleNodeImp[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedEdgeParameters, TLCreditedBundle] { def edge(pd: TLCreditedClientPortParameters, pu: TLCreditedManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLCreditedEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLCreditedEdgeParameters) = new TLCreditedBundle(e.bundle) def render(e: TLCreditedEdgeParameters) = RenderedEdge(colour = "#ffff00" / yellow /, e.delay.toString) override def mixO(pd: TLCreditedClientPortParameters, node: OutwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLCreditedManagerPortParameters, node: InwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLCreditedAdapterNode( clientFn: TLCreditedClientPortParameters => TLCreditedClientPortParameters = { s => s }, managerFn: TLCreditedManagerPortParameters => TLCreditedManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLCreditedImp)(clientFn, managerFn) with TLCreditedFormatNode case class TLCreditedIdentityNode()(implicit valName: ValName) extends IdentityNode(TLCreditedImp)() with TLCreditedFormatNode object TLCreditedNameNode { def apply(name: ValName) = TLCreditedIdentityNode()(name) def apply(name: Option[String]): TLCreditedIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLCreditedIdentityNode = apply(Some(name)) } case class TLCreditedSourceNode(delay: TLCreditedDelay)(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLCreditedImp)( dFn = { p => TLCreditedClientPortParameters(delay, p) }, uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLCreditedEdgeParameters] // discard cycles from other clock domain case class TLCreditedSinkNode(delay: TLCreditedDelay)(implicit valName: ValName) extends MixedAdapterNode(TLCreditedImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = 1) }, uFn = { p => TLCreditedManagerPortParameters(delay, p) }) with FormatNode[TLCreditedEdgeParameters, TLEdgeOut] File RegisterRouter.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.nodes._ import freechips.rocketchip.diplomacy.{AddressSet, TransferSizes} import freechips.rocketchip.resources.{Device, Resource, ResourceBindings} import freechips.rocketchip.prci.{NoCrossing} import freechips.rocketchip.regmapper.{RegField, RegMapper, RegMapperParams, RegMapperInput, RegisterRouter} import freechips.rocketchip.util.{BundleField, ControlKey, ElaborationArtefacts, GenRegDescsAnno} import scala.math.min class TLRegisterRouterExtraBundle(val sourceBits: Int, val sizeBits: Int) extends Bundle { val source = UInt((sourceBits max 1).W) val size = UInt((sizeBits max 1).W) } case object TLRegisterRouterExtra extends ControlKey[TLRegisterRouterExtraBundle]("tlrr_extra") case class TLRegisterRouterExtraField(sourceBits: Int, sizeBits: Int) extends BundleField[TLRegisterRouterExtraBundle](TLRegisterRouterExtra, Output(new TLRegisterRouterExtraBundle(sourceBits, sizeBits)), x => { x.size := 0.U x.source := 0.U }) /* TLRegisterNode is a specialized TL SinkNode that encapsulates MMIO registers. * It provides functionality for describing and outputting metdata about the registers in several formats. * It also provides a concrete implementation of a regmap function that will be used * to wire a map of internal registers associated with this node to the node's interconnect port. / case class TLRegisterNode( address: Seq[AddressSet], device: Device, deviceKey: String = "reg/control", concurrency: Int = 0, beatBytes: Int = 4, undefZero: Boolean = true, executable: Boolean = false)( implicit valName: ValName) extends SinkNode(TLImp)(Seq(TLSlavePortParameters.v1( Seq(TLSlaveParameters.v1( address = address, resources = Seq(Resource(device, deviceKey)), executable = executable, supportsGet = TransferSizes(1, beatBytes), supportsPutPartial = TransferSizes(1, beatBytes), supportsPutFull = TransferSizes(1, beatBytes), fifoId = Some(0))), // requests are handled in order beatBytes = beatBytes, minLatency = min(concurrency, 1)))) with TLFormatNode // the Queue adds at most one cycle { val size = 1 << log2Ceil(1 + address.map(_.max).max - address.map(_.base).min) require (size >= beatBytes) address.foreach { case a => require (a.widen(size-1).base == address.head.widen(size-1).base, s"TLRegisterNode addresses (${address}) must be aligned to its size ${size}") } // Calling this method causes the matching TL2 bundle to be // configured to route all requests to the listed RegFields. def regmap(mapping: RegField.Map) = { val (bundleIn, edge) = this.in(0) val a = bundleIn.a val d = bundleIn.d val fields = TLRegisterRouterExtraField(edge.bundle.sourceBits, edge.bundle.sizeBits) +: a.bits.params.echoFields val params = RegMapperParams(log2Up(size/beatBytes), beatBytes, fields) val in = Wire(Decoupled(new RegMapperInput(params))) in.bits.read := a.bits.opcode === TLMessages.Get in.bits.index := edge.addr_hi(a.bits) in.bits.data := a.bits.data in.bits.mask := a.bits.mask Connectable.waiveUnmatched(in.bits.extra, a.bits.echo) match { case (lhs, rhs) => lhs :<= rhs } val a_extra = in.bits.extra(TLRegisterRouterExtra) a_extra.source := a.bits.source a_extra.size := a.bits.size // Invoke the register map builder val out = RegMapper(beatBytes, concurrency, undefZero, in, mapping:_) // No flow control needed in.valid := a.valid a.ready := in.ready d.valid := out.valid out.ready := d.ready // We must restore the size to enable width adapters to work val d_extra = out.bits.extra(TLRegisterRouterExtra) d.bits := edge.AccessAck(toSource = d_extra.source, lgSize = d_extra.size) // avoid a Mux on the data bus by manually overriding two fields d.bits.data := out.bits.data Connectable.waiveUnmatched(d.bits.echo, out.bits.extra) match { case (lhs, rhs) => lhs :<= rhs } d.bits.opcode := Mux(out.bits.read, TLMessages.AccessAckData, TLMessages.AccessAck) // Tie off unused channels bundleIn.b.valid := false.B bundleIn.c.ready := true.B bundleIn.e.ready := true.B genRegDescsJson(mapping:_) } def genRegDescsJson(mapping: RegField.Map): Unit = { // Dump out the register map for documentation purposes. val base = address.head.base val baseHex = s"0x${base.toInt.toHexString}" val name = s"${device.describe(ResourceBindings()).name}.At${baseHex}" val json = GenRegDescsAnno.serialize(base, name, mapping:_) var suffix = 0 while( ElaborationArtefacts.contains(s"${baseHex}.${suffix}.regmap.json")) { suffix = suffix + 1 } ElaborationArtefacts.add(s"${baseHex}.${suffix}.regmap.json", json) val module = Module.currentModule.get.asInstanceOf[RawModule] GenRegDescsAnno.anno( module, base, mapping:_) } } /* Mix HasTLControlRegMap into any subclass of RegisterRouter to gain helper functions for attaching a device control register map to TileLink. * - The intended use case is that controlNode will diplomatically publish a SW-visible device's memory-mapped control registers. * - Use the clock crossing helper controlXing to externally connect controlNode to a TileLink interconnect. * - Use the mapping helper function regmap to internally fill out the space of device control registers. / trait HasTLControlRegMap { this: RegisterRouter => protected val controlNode = TLRegisterNode( address = address, device = device, deviceKey = "reg/control", concurrency = concurrency, beatBytes = beatBytes, undefZero = undefZero, executable = executable) // Externally, this helper should be used to connect the register control port to a bus val controlXing: TLInwardClockCrossingHelper = this.crossIn(controlNode) // Backwards-compatibility default node accessor with no clock crossing lazy val node: TLInwardNode = controlXing(NoCrossing) // Internally, this function should be used to populate the control port with registers protected def regmap(mapping: RegField.Map): Unit = { controlNode.regmap(mapping:_) } } File MuxLiteral.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util.log2Ceil import scala.reflect.ClassTag / MuxLiteral creates a lookup table from a key to a list of values. * Unlike MuxLookup, the table keys must be exclusive literals. / object MuxLiteral { def apply[T <: Data:ClassTag](index: UInt, default: T, first: (UInt, T), rest: (UInt, T)): T = apply(index, default, first :: rest.toList) def apply[T <: Data:ClassTag](index: UInt, default: T, cases: Seq[(UInt, T)]): T = MuxTable(index, default, cases.map { case (k, v) => (k.litValue, v) }) } object MuxSeq { def apply[T <: Data:ClassTag](index: UInt, default: T, first: T, rest: T): T = apply(index, default, first :: rest.toList) def apply[T <: Data:ClassTag](index: UInt, default: T, cases: Seq[T]): T = MuxTable(index, default, cases.zipWithIndex.map { case (v, i) => (BigInt(i), v) }) } object MuxTable { def apply[T <: Data:ClassTag](index: UInt, default: T, first: (BigInt, T), rest: (BigInt, T)): T = apply(index, default, first :: rest.toList) def apply[T <: Data:ClassTag](index: UInt, default: T, cases: Seq[(BigInt, T)]): T = { /* All keys must be >= 0 and distinct / cases.foreach { case (k, _) => require (k >= 0) } require (cases.map(_._1).distinct.size == cases.size) / Filter out any cases identical to the default / val simple = cases.filter { case (k, v) => !default.isLit \|\| !v.isLit \|\| v.litValue != default.litValue } val maxKey = (BigInt(0) +: simple.map(_._1)).max val endIndex = BigInt(1) << log2Ceil(maxKey+1) if (simple.isEmpty) { default } else if (endIndex <= 2simple.size) { /* The dense encoding case uses a Vec / val table = Array.fill(endIndex.toInt) { default } simple.foreach { case (k, v) => table(k.toInt) = v } Mux(index >= endIndex.U, default, VecInit(table)(index)) } else { / The sparse encoding case uses switch / val out = WireDefault(default) simple.foldLeft(new chisel3.util.SwitchContext(index, None, Set.empty)) { case (acc, (k, v)) => acc.is (k.U) { out := v } } out } } } File LazyModuleImp.scala: package org.chipsalliance.diplomacy.lazymodule import chisel3.{withClockAndReset, Module, RawModule, Reset, _} import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo} import firrtl.passes.InlineAnnotation import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.nodes.Dangle import scala.collection.immutable.SortedMap /* Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]]. * * This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy. / sealed trait LazyModuleImpLike extends RawModule { /* [[LazyModule]] that contains this instance. / val wrapper: LazyModule /* IOs that will be automatically "punched" for this instance. / val auto: AutoBundle /* The metadata that describes the [[HalfEdge]]s which generated [[auto]]. / protected[diplomacy] val dangles: Seq[Dangle] // [[wrapper.module]] had better not be accessed while LazyModules are still being built! require( LazyModule.scope.isEmpty, s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}" ) /* Set module name. Defaults to the containing LazyModule's desiredName. / override def desiredName: String = wrapper.desiredName suggestName(wrapper.suggestedName) /* [[Parameters]] for chisel [[Module]]s. / implicit val p: Parameters = wrapper.p /* instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and * submodules. / protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = { // 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]], // 2. return [[Dangle]]s from each module. val childDangles = wrapper.children.reverse.flatMap { c => implicit val sourceInfo: SourceInfo = c.info c.cloneProto.map { cp => // If the child is a clone, then recursively set cloneProto of its children as well def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = { require(bases.size == clones.size) (bases.zip(clones)).map { case (l, r) => require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}") l.cloneProto = Some(r) assignCloneProtos(l.children, r.children) } } assignCloneProtos(c.children, cp.children) // Clone the child module as a record, and get its [[AutoBundle]] val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName) val clonedAuto = clone("auto").asInstanceOf[AutoBundle] // Get the empty [[Dangle]]'s of the cloned child val rawDangles = c.cloneDangles() require(rawDangles.size == clonedAuto.elements.size) // Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) } dangles }.getOrElse { // For non-clones, instantiate the child module val mod = try { Module(c.module) } catch { case e: ChiselException => { println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}") throw e } } mod.dangles } } // Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]]. // This will result in a sequence of [[Dangle]] from these [[BaseNode]]s. val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate()) // Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]] val allDangles = nodeDangles ++ childDangles // Group [[allDangles]] by their [[source]]. val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _) // For each [[source]] set of [[Dangle]]s of size 2, ensure that these // can be connected as a source-sink pair (have opposite flipped value). // Make the connection and mark them as [[done]]. val done = Set() ++ pairing.values.filter(_.size == 2).map { case Seq(a, b) => require(a.flipped != b.flipped) // @todo <> in chisel3 makes directionless connection. if (a.flipped) { a.data <> b.data } else { b.data <> a.data } a.source case _ => None } // Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module. val forward = allDangles.filter(d => !done(d.source)) // Generate [[AutoBundle]] IO from [[forward]]. val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _)) // Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]] val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) => if (d.flipped) { d.data <> io } else { io <> d.data } d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name) } // Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]]. wrapper.inModuleBody.reverse.foreach { _() } if (wrapper.shouldBeInlined) { chisel3.experimental.annotate(new ChiselAnnotation { def toFirrtl = InlineAnnotation(toNamed) }) } // Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]]. (auto, dangles) } } /* Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. / class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike { /* Instantiate hardware of this `Module`. / val (auto, dangles) = instantiate() } /* Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. / class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike { // These wires are the default clock+reset for all LazyModule children. // It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the // [[LazyRawModuleImp]] children. // Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly. /* drive clock explicitly. / val childClock: Clock = Wire(Clock()) /* drive reset explicitly. / val childReset: Reset = Wire(Reset()) // the default is that these are disabled childClock := false.B.asClock childReset := chisel3.DontCare def provideImplicitClockToLazyChildren: Boolean = false val (auto, dangles) = if (provideImplicitClockToLazyChildren) { withClockAndReset(childClock, childReset) { instantiate() } } else { instantiate() } } File MixedNode.scala: package org.chipsalliance.diplomacy.nodes import chisel3.{Data, DontCare, Wire} import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.{Field, Parameters} import org.chipsalliance.diplomacy.ValName import org.chipsalliance.diplomacy.sourceLine /* One side metadata of a [[Dangle]]. * * Describes one side of an edge going into or out of a [[BaseNode]]. * * @param serial * the global [[BaseNode.serial]] number of the [[BaseNode]] that this [[HalfEdge]] connects to. * @param index * the `index` in the [[BaseNode]]'s input or output port list that this [[HalfEdge]] belongs to. / case class HalfEdge(serial: Int, index: Int) extends Ordered[HalfEdge] { import scala.math.Ordered.orderingToOrdered def compare(that: HalfEdge): Int = HalfEdge.unapply(this).compare(HalfEdge.unapply(that)) } /* [[Dangle]] captures the `IO` information of a [[LazyModule]] and which two [[BaseNode]]s the [[Edges]]/[[Bundle]] * connects. * * [[Dangle]]s are generated by [[BaseNode.instantiate]] using [[MixedNode.danglesOut]] and [[MixedNode.danglesIn]] , * [[LazyModuleImp.instantiate]] connects those that go to internal or explicit IO connections in a [[LazyModule]]. * * @param source * the source [[HalfEdge]] of this [[Dangle]], which captures the source [[BaseNode]] and the port `index` within * that [[BaseNode]]. * @param sink * sink [[HalfEdge]] of this [[Dangle]], which captures the sink [[BaseNode]] and the port `index` within that * [[BaseNode]]. * @param flipped * flip or not in [[AutoBundle.makeElements]]. If true this corresponds to `danglesOut`, if false it corresponds to * `danglesIn`. * @param dataOpt * actual [[Data]] for the hardware connection. Can be empty if this belongs to a cloned module / case class Dangle(source: HalfEdge, sink: HalfEdge, flipped: Boolean, name: String, dataOpt: Option[Data]) { def data = dataOpt.get } /* [[Edges]] is a collection of parameters describing the functionality and connection for an interface, which is often * derived from the interconnection protocol and can inform the parameterization of the hardware bundles that actually * implement the protocol. / case class Edges[EI, EO](in: Seq[EI], out: Seq[EO]) /* A field available in [[Parameters]] used to determine whether [[InwardNodeImp.monitor]] will be called. / case object MonitorsEnabled extends Field[Boolean](true) /* When rendering the edge in a graphical format, flip the order in which the edges' source and sink are presented. * * For example, when rendering graphML, yEd by default tries to put the source node vertically above the sink node, but * [[RenderFlipped]] inverts this relationship. When a particular [[LazyModule]] contains both source nodes and sink * nodes, flipping the rendering of one node's edge will usual produce a more concise visual layout for the * [[LazyModule]]. / case object RenderFlipped extends Field[Boolean](false) /* The sealed node class in the package, all node are derived from it. * * @param inner * Sink interface implementation. * @param outer * Source interface implementation. * @param valName * val name of this node. * @tparam DI * Downward-flowing parameters received on the inner side of the node. It is usually a brunch of parameters * describing the protocol parameters from a source. For an [[InwardNode]], it is determined by the connected * [[OutwardNode]]. Since it can be connected to multiple sources, this parameter is always a Seq of source port * parameters. * @tparam UI * Upward-flowing parameters generated by the inner side of the node. It is usually a brunch of parameters describing * the protocol parameters of a sink. For an [[InwardNode]], it is determined itself. * @tparam EI * Edge Parameters describing a connection on the inner side of the node. It is usually a brunch of transfers * specified for a sink according to protocol. * @tparam BI * Bundle type used when connecting to the inner side of the node. It is a hardware interface of this sink interface. * It should extends from [[chisel3.Data]], which represents the real hardware. * @tparam DO * Downward-flowing parameters generated on the outer side of the node. It is usually a brunch of parameters * describing the protocol parameters of a source. For an [[OutwardNode]], it is determined itself. * @tparam UO * Upward-flowing parameters received by the outer side of the node. It is usually a brunch of parameters describing * the protocol parameters from a sink. For an [[OutwardNode]], it is determined by the connected [[InwardNode]]. * Since it can be connected to multiple sinks, this parameter is always a Seq of sink port parameters. * @tparam EO * Edge Parameters describing a connection on the outer side of the node. It is usually a brunch of transfers * specified for a source according to protocol. * @tparam BO * Bundle type used when connecting to the outer side of the node. It is a hardware interface of this source * interface. It should extends from [[chisel3.Data]], which represents the real hardware. * * @note * Call Graph of [[MixedNode]] * - line `─`: source is process by a function and generate pass to others * - Arrow `→`: target of arrow is generated by source * * {{{ * (from the other node) * ┌─────────────────────────────────────────────────────────[[InwardNode.uiParams]]─────────────┐ * ↓ │ * (binding node when elaboration) [[OutwardNode.uoParams]]────────────────────────[[MixedNode.mapParamsU]]→──────────┐ │ * [[InwardNode.accPI]] │ │ │ * │ │ (based on protocol) │ * │ │ [[MixedNode.inner.edgeI]] │ * │ │ ↓ │ * ↓ │ │ │ * (immobilize after elaboration) (inward port from [[OutwardNode]]) │ ↓ │ * [[InwardNode.iBindings]]──┐ [[MixedNode.iDirectPorts]]────────────────────→[[MixedNode.iPorts]] [[InwardNode.uiParams]] │ * │ │ ↑ │ │ │ * │ │ │ [[OutwardNode.doParams]] │ │ * │ │ │ (from the other node) │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * │ │ │ └────────┬──────────────┤ │ * │ │ │ │ │ │ * │ │ │ │ (based on protocol) │ * │ │ │ │ [[MixedNode.inner.edgeI]] │ * │ │ │ │ │ │ * │ │ (from the other node) │ ↓ │ * │ └───[[OutwardNode.oPortMapping]] [[OutwardNode.oStar]] │ [[MixedNode.edgesIn]]───┐ │ * │ ↑ ↑ │ │ ↓ │ * │ │ │ │ │ [[MixedNode.in]] │ * │ │ │ │ ↓ ↑ │ * │ (solve star connection) │ │ │ [[MixedNode.bundleIn]]──┘ │ * ├───[[MixedNode.resolveStar]]→─┼─────────────────────────────┤ └────────────────────────────────────┐ │ * │ │ │ [[MixedNode.bundleOut]]─┐ │ │ * │ │ │ ↑ ↓ │ │ * │ │ │ │ [[MixedNode.out]] │ │ * │ ↓ ↓ │ ↑ │ │ * │ ┌─────[[InwardNode.iPortMapping]] [[InwardNode.iStar]] [[MixedNode.edgesOut]]──┘ │ │ * │ │ (from the other node) ↑ │ │ * │ │ │ │ │ │ * │ │ │ [[MixedNode.outer.edgeO]] │ │ * │ │ │ (based on protocol) │ │ * │ │ │ │ │ │ * │ │ │ ┌────────────────────────────────────────┤ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * (immobilize after elaboration)│ ↓ │ │ │ │ * [[OutwardNode.oBindings]]─┘ [[MixedNode.oDirectPorts]]───→[[MixedNode.oPorts]] [[OutwardNode.doParams]] │ │ * ↑ (inward port from [[OutwardNode]]) │ │ │ │ * │ ┌─────────────────────────────────────────┤ │ │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * [[OutwardNode.accPO]] │ ↓ │ │ │ * (binding node when elaboration) │ [[InwardNode.diParams]]─────→[[MixedNode.mapParamsD]]────────────────────────────┘ │ │ * │ ↑ │ │ * │ └──────────────────────────────────────────────────────────────────────────────────────────┘ │ * └──────────────────────────────────────────────────────────────────────────────────────────────────────────┘ * }}} / abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data]( val inner: InwardNodeImp[DI, UI, EI, BI], val outer: OutwardNodeImp[DO, UO, EO, BO] )( implicit valName: ValName) extends BaseNode with NodeHandle[DI, UI, EI, BI, DO, UO, EO, BO] with InwardNode[DI, UI, BI] with OutwardNode[DO, UO, BO] { // Generate a [[NodeHandle]] with inward and outward node are both this node. val inward = this val outward = this /* Debug info of nodes binding. / def bindingInfo: String = s"""$iBindingInfo \|$oBindingInfo \|""".stripMargin /* Debug info of ports connecting. / def connectedPortsInfo: String = s"""${oPorts.size} outward ports connected: [${oPorts.map(_._2.name).mkString(",")}] \|${iPorts.size} inward ports connected: [${iPorts.map(_._2.name).mkString(",")}] \|""".stripMargin /* Debug info of parameters propagations. / def parametersInfo: String = s"""${doParams.size} downstream outward parameters: [${doParams.mkString(",")}] \|${uoParams.size} upstream outward parameters: [${uoParams.mkString(",")}] \|${diParams.size} downstream inward parameters: [${diParams.mkString(",")}] \|${uiParams.size} upstream inward parameters: [${uiParams.mkString(",")}] \|""".stripMargin /* For a given node, converts [[OutwardNode.accPO]] and [[InwardNode.accPI]] to [[MixedNode.oPortMapping]] and * [[MixedNode.iPortMapping]]. * * Given counts of known inward and outward binding and inward and outward star bindings, return the resolved inward * stars and outward stars. * * This method will also validate the arguments and throw a runtime error if the values are unsuitable for this type * of node. * * @param iKnown * Number of known-size ([[BIND_ONCE]]) input bindings. * @param oKnown * Number of known-size ([[BIND_ONCE]]) output bindings. * @param iStar * Number of unknown size ([[BIND_STAR]]) input bindings. * @param oStar * Number of unknown size ([[BIND_STAR]]) output bindings. * @return * A Tuple of the resolved number of input and output connections. / protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStar: Int, oStar: Int): (Int, Int) /* Function to generate downward-flowing outward params from the downward-flowing input params and the current output * ports. * * @param n * The size of the output sequence to generate. * @param p * Sequence of downward-flowing input parameters of this node. * @return * A `n`-sized sequence of downward-flowing output edge parameters. / protected[diplomacy] def mapParamsD(n: Int, p: Seq[DI]): Seq[DO] /* Function to generate upward-flowing input parameters from the upward-flowing output parameters [[uiParams]]. * * @param n * Size of the output sequence. * @param p * Upward-flowing output edge parameters. * @return * A n-sized sequence of upward-flowing input edge parameters. / protected[diplomacy] def mapParamsU(n: Int, p: Seq[UO]): Seq[UI] /* @return * The sink cardinality of the node, the number of outputs bound with [[BIND_QUERY]] summed with inputs bound with * [[BIND_STAR]]. / protected[diplomacy] lazy val sinkCard: Int = oBindings.count(_._3 == BIND_QUERY) + iBindings.count(_._3 == BIND_STAR) /* @return * The source cardinality of this node, the number of inputs bound with [[BIND_QUERY]] summed with the number of * output bindings bound with [[BIND_STAR]]. / protected[diplomacy] lazy val sourceCard: Int = iBindings.count(_._3 == BIND_QUERY) + oBindings.count(_._3 == BIND_STAR) /* @return list of nodes involved in flex bindings with this node. / protected[diplomacy] lazy val flexes: Seq[BaseNode] = oBindings.filter(_._3 == BIND_FLEX).map(_._2) ++ iBindings.filter(_._3 == BIND_FLEX).map(_._2) /* Resolves the flex to be either source or sink and returns the offset where the [[BIND_STAR]] operators begin * greedily taking up the remaining connections. * * @return * A value >= 0 if it is sink cardinality, a negative value for source cardinality. The magnitude of the return * value is not relevant. / protected[diplomacy] lazy val flexOffset: Int = { /* Recursively performs a depth-first search of the [[flexes]], [[BaseNode]]s connected to this node with flex * operators. The algorithm bottoms out when we either get to a node we have already visited or when we get to a * connection that is not a flex and can set the direction for us. Otherwise, recurse by visiting the `flexes` of * each node in the current set and decide whether they should be added to the set or not. * * @return * the mapping of [[BaseNode]] indexed by their serial numbers. / def DFS(v: BaseNode, visited: Map[Int, BaseNode]): Map[Int, BaseNode] = { if (visited.contains(v.serial) \|\| !v.flexibleArityDirection) { visited } else { v.flexes.foldLeft(visited + (v.serial -> v))((sum, n) => DFS(n, sum)) } } /* Determine which [[BaseNode]] are involved in resolving the flex connections to/from this node. * * @example * {{{ * a := b := c * d := b * e := f * }}} * * `flexSet` for `a`, `b`, `c`, or `d` will be `Set(a, b, c, d)` `flexSet` for `e` or `f` will be `Set(e,f)` / val flexSet = DFS(this, Map()).values /* The total number of := operators where we're on the left. / val allSink = flexSet.map(_.sinkCard).sum /** The total number of :=* operators used when we're on the right. / val allSource = flexSet.map(_.sourceCard).sum require( allSink == 0 \|\| allSource == 0, s"The nodes ${flexSet.map(_.name)} which are inter-connected by :=* have ${allSink} := operators and ${allSource} := operators connected to them, making it impossible to determine cardinality inference direction." ) allSink - allSource } /** @return A value >= 0 if it is sink cardinality, a negative value for source cardinality. / protected[diplomacy] def edgeArityDirection(n: BaseNode): Int = { if (flexibleArityDirection) flexOffset else if (n.flexibleArityDirection) n.flexOffset else 0 } /* For a node which is connected between two nodes, select the one that will influence the direction of the flex * resolution. / protected[diplomacy] def edgeAritySelect(n: BaseNode, l: => Int, r: => Int): Int = { val dir = edgeArityDirection(n) if (dir < 0) l else if (dir > 0) r else 1 } /* Ensure that the same node is not visited twice in resolving `:=`, etc operators. / private var starCycleGuard = false /** Resolve all the star operators into concrete indicies. As connections are being made, some may be "star" * connections which need to be resolved. In some way to determine how many actual edges they correspond to. We also * need to build up the ranges of edges which correspond to each binding operator, so that We can apply the correct * edge parameters and later build up correct bundle connections. * * [[oPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that oPort (binding * operator). [[iPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that iPort * (binding operator). [[oStar]]: `Int` the value to return for this node `N` for any `N := foo` or `N :=* foo := bar` [[iStar]]: `Int` the value to return for this node `N` for any `foo :=* N` or `bar :=* foo := N` / protected[diplomacy] lazy val ( oPortMapping: Seq[(Int, Int)], iPortMapping: Seq[(Int, Int)], oStar: Int, iStar: Int ) = { try { if (starCycleGuard) throw StarCycleException() starCycleGuard = true // For a given node N... // Number of foo := N // + Number of bar :=* foo := N val oStars = oBindings.count { case (_, n, b, _, _) => b == BIND_STAR \|\| (b == BIND_FLEX && edgeArityDirection(n) < 0) } // Number of N := foo // + Number of N :=* foo := bar val iStars = iBindings.count { case (_, n, b, _, _) => b == BIND_STAR \|\| (b == BIND_FLEX && edgeArityDirection(n) > 0) } // 1 for foo := N // + bar.iStar for bar := foo := N // + foo.iStar for foo := N // + 0 for foo := N val oKnown = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, 0, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => 0 } }.sum // 1 for N := foo // + bar.oStar for N := foo :=* bar // + foo.oStar for N :=* foo // + 0 for N := foo val iKnown = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, 0) case BIND_QUERY => n.oStar case BIND_STAR => 0 } }.sum // Resolve star depends on the node subclass to implement the algorithm for this. val (iStar, oStar) = resolveStar(iKnown, oKnown, iStars, oStars) // Cumulative list of resolved outward binding range starting points val oSum = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, oStar, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => oStar } }.scanLeft(0)(_ + _) // Cumulative list of resolved inward binding range starting points val iSum = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, iStar) case BIND_QUERY => n.oStar case BIND_STAR => iStar } }.scanLeft(0)(_ + _) // Create ranges for each binding based on the running sums and return // those along with resolved values for the star operations. (oSum.init.zip(oSum.tail), iSum.init.zip(iSum.tail), oStar, iStar) } catch { case c: StarCycleException => throw c.copy(loop = context +: c.loop) } } /* Sequence of inward ports. * * This should be called after all star bindings are resolved. * * Each element is: `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. * `n` Instance of inward node. `p` View of [[Parameters]] where this connection was made. `s` Source info where this * connection was made in the source code. / protected[diplomacy] lazy val oDirectPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oBindings.flatMap { case (i, n, _, p, s) => // for each binding operator in this node, look at what it connects to val (start, end) = n.iPortMapping(i) (start until end).map { j => (j, n, p, s) } } /* Sequence of outward ports. * * This should be called after all star bindings are resolved. * * `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. `n` Instance of * outward node. `p` View of [[Parameters]] where this connection was made. `s` [[SourceInfo]] where this connection * was made in the source code. / protected[diplomacy] lazy val iDirectPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iBindings.flatMap { case (i, n, _, p, s) => // query this port index range of this node in the other side of node. val (start, end) = n.oPortMapping(i) (start until end).map { j => (j, n, p, s) } } // Ephemeral nodes ( which have non-None iForward/oForward) have in_degree = out_degree // Thus, there must exist an Eulerian path and the below algorithms terminate @scala.annotation.tailrec private def oTrace( tuple: (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) ): (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.iForward(i) match { case None => (i, n, p, s) case Some((j, m)) => oTrace((j, m, p, s)) } } @scala.annotation.tailrec private def iTrace( tuple: (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) ): (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.oForward(i) match { case None => (i, n, p, s) case Some((j, m)) => iTrace((j, m, p, s)) } } /* Final output ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - Numeric index of this binding in the [[InwardNode]] on the other end. * - [[InwardNode]] on the other end of this binding. * - A view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. / lazy val oPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oDirectPorts.map(oTrace) /* Final input ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - numeric index of this binding in [[OutwardNode]] on the other end. * - [[OutwardNode]] on the other end of this binding. * - a view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. / lazy val iPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iDirectPorts.map(iTrace) private var oParamsCycleGuard = false protected[diplomacy] lazy val diParams: Seq[DI] = iPorts.map { case (i, n, _, _) => n.doParams(i) } protected[diplomacy] lazy val doParams: Seq[DO] = { try { if (oParamsCycleGuard) throw DownwardCycleException() oParamsCycleGuard = true val o = mapParamsD(oPorts.size, diParams) require( o.size == oPorts.size, s"""Diplomacy has detected a problem with your graph: \|At the following node, the number of outward ports should equal the number of produced outward parameters. \|$context \|$connectedPortsInfo \|Downstreamed inward parameters: [${diParams.mkString(",")}] \|Produced outward parameters: [${o.mkString(",")}] \|""".stripMargin ) o.map(outer.mixO(_, this)) } catch { case c: DownwardCycleException => throw c.copy(loop = context +: c.loop) } } private var iParamsCycleGuard = false protected[diplomacy] lazy val uoParams: Seq[UO] = oPorts.map { case (o, n, _, _) => n.uiParams(o) } protected[diplomacy] lazy val uiParams: Seq[UI] = { try { if (iParamsCycleGuard) throw UpwardCycleException() iParamsCycleGuard = true val i = mapParamsU(iPorts.size, uoParams) require( i.size == iPorts.size, s"""Diplomacy has detected a problem with your graph: \|At the following node, the number of inward ports should equal the number of produced inward parameters. \|$context \|$connectedPortsInfo \|Upstreamed outward parameters: [${uoParams.mkString(",")}] \|Produced inward parameters: [${i.mkString(",")}] \|""".stripMargin ) i.map(inner.mixI(_, this)) } catch { case c: UpwardCycleException => throw c.copy(loop = context +: c.loop) } } /* Outward edge parameters. / protected[diplomacy] lazy val edgesOut: Seq[EO] = (oPorts.zip(doParams)).map { case ((i, n, p, s), o) => outer.edgeO(o, n.uiParams(i), p, s) } /* Inward edge parameters. / protected[diplomacy] lazy val edgesIn: Seq[EI] = (iPorts.zip(uiParams)).map { case ((o, n, p, s), i) => inner.edgeI(n.doParams(o), i, p, s) } /* A tuple of the input edge parameters and output edge parameters for the edges bound to this node. * * If you need to access to the edges of a foreign Node, use this method (in/out create bundles). / lazy val edges: Edges[EI, EO] = Edges(edgesIn, edgesOut) /* Create actual Wires corresponding to the Bundles parameterized by the outward edges of this node. / protected[diplomacy] lazy val bundleOut: Seq[BO] = edgesOut.map { e => val x = Wire(outer.bundleO(e)).suggestName(s"${valName.value}Out") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } /* Create actual Wires corresponding to the Bundles parameterized by the inward edges of this node. / protected[diplomacy] lazy val bundleIn: Seq[BI] = edgesIn.map { e => val x = Wire(inner.bundleI(e)).suggestName(s"${valName.value}In") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } private def emptyDanglesOut: Seq[Dangle] = oPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(serial, i), sink = HalfEdge(n.serial, j), flipped = false, name = wirePrefix + "out", dataOpt = None ) } private def emptyDanglesIn: Seq[Dangle] = iPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(n.serial, j), sink = HalfEdge(serial, i), flipped = true, name = wirePrefix + "in", dataOpt = None ) } /* Create the [[Dangle]]s which describe the connections from this node output to other nodes inputs. / protected[diplomacy] def danglesOut: Seq[Dangle] = emptyDanglesOut.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleOut(i))) } /* Create the [[Dangle]]s which describe the connections from this node input from other nodes outputs. / protected[diplomacy] def danglesIn: Seq[Dangle] = emptyDanglesIn.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleIn(i))) } private[diplomacy] var instantiated = false /* Gather Bundle and edge parameters of outward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. / def out: Seq[(BO, EO)] = { require( instantiated, s"$name.out should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleOut.zip(edgesOut) } /* Gather Bundle and edge parameters of inward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. / def in: Seq[(BI, EI)] = { require( instantiated, s"$name.in should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleIn.zip(edgesIn) } /* Actually instantiate this node during [[LazyModuleImp]] evaluation. Mark that it's safe to use the Bundle wires, * instantiate monitors on all input ports if appropriate, and return all the dangles of this node. / protected[diplomacy] def instantiate(): Seq[Dangle] = { instantiated = true if (!circuitIdentity) { (iPorts.zip(in)).foreach { case ((_, _, p, _), (b, e)) => if (p(MonitorsEnabled)) inner.monitor(b, e) } } danglesOut ++ danglesIn } protected[diplomacy] def cloneDangles(): Seq[Dangle] = emptyDanglesOut ++ emptyDanglesIn /* Connects the outward part of a node with the inward part of this node. / protected[diplomacy] def bind( h: OutwardNode[DI, UI, BI], binding: NodeBinding )( implicit p: Parameters, sourceInfo: SourceInfo ): Unit = { val x = this // x := y val y = h sourceLine(sourceInfo, " at ", "") val i = x.iPushed val o = y.oPushed y.oPush( i, x, binding match { case BIND_ONCE => BIND_ONCE case BIND_FLEX => BIND_FLEX case BIND_STAR => BIND_QUERY case BIND_QUERY => BIND_STAR } ) x.iPush(o, y, binding) } / Metadata for printing the node graph. / def inputs: Seq[(OutwardNode[DI, UI, BI], RenderedEdge)] = (iPorts.zip(edgesIn)).map { case ((_, n, p, _), e) => val re = inner.render(e) (n, re.copy(flipped = re.flipped != p(RenderFlipped))) } /* Metadata for printing the node graph / def outputs: Seq[(InwardNode[DO, UO, BO], RenderedEdge)] = oPorts.map { case (i, n, _, _) => (n, n.inputs(i)._2) } } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportPutFull \|\| manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB \|\| manager.anySupportGet \|\| manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportPutFull \|\| client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe \|\| client.anySupportGet \|\| client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet \|\| client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull \|\| client.anySupportPutPartial \|\| client.anySupportHint \|\| client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet \|\| manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull \|\| manager.anySupportPutPartial \|\| manager.anySupportHint \|\| manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) \|\| !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.ProbeAckData \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode \| small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U \|\| beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }	module TLUART( // @[UART.scala:127:25] input clock, // @[UART.scala:127:25] input reset, // @[UART.scala:127:25] output auto_int_xing_out_sync_0, // @[LazyModuleImp.scala:107:25] output auto_control_xing_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_control_xing_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_control_xing_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_control_xing_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [1:0] auto_control_xing_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [13:0] auto_control_xing_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [28:0] auto_control_xing_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_control_xing_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_control_xing_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_control_xing_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_control_xing_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_control_xing_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_control_xing_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_control_xing_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [13:0] auto_control_xing_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output [63:0] auto_control_xing_in_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_io_out_txd, // @[LazyModuleImp.scala:107:25] input auto_io_out_rxd // @[LazyModuleImp.scala:107:25] ); wire out_front_valid; // @[RegisterRouter.scala:87:24] wire out_front_ready; // @[RegisterRouter.scala:87:24] wire out_bits_read; // @[RegisterRouter.scala:87:24] wire [13:0] out_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:87:24] wire [8:0] in_bits_index; // @[RegisterRouter.scala:73:18] wire in_bits_read; // @[RegisterRouter.scala:73:18] wire buffer_auto_out_d_valid; // @[Buffer.scala:40:9] wire buffer_auto_out_d_ready; // @[Buffer.scala:40:9] wire [63:0] buffer_auto_out_d_bits_data; // @[Buffer.scala:40:9] wire [13:0] buffer_auto_out_d_bits_source; // @[Buffer.scala:40:9] wire [1:0] buffer_auto_out_d_bits_size; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_out_d_bits_opcode; // @[Buffer.scala:40:9] wire buffer_auto_out_a_valid; // @[Buffer.scala:40:9] wire buffer_auto_out_a_ready; // @[Buffer.scala:40:9] wire buffer_auto_out_a_bits_corrupt; // @[Buffer.scala:40:9] wire [63:0] buffer_auto_out_a_bits_data; // @[Buffer.scala:40:9] wire [7:0] buffer_auto_out_a_bits_mask; // @[Buffer.scala:40:9] wire [28:0] buffer_auto_out_a_bits_address; // @[Buffer.scala:40:9] wire [13:0] buffer_auto_out_a_bits_source; // @[Buffer.scala:40:9] wire [1:0] buffer_auto_out_a_bits_size; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_out_a_bits_param; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_out_a_bits_opcode; // @[Buffer.scala:40:9] wire buffer_auto_in_d_valid; // @[Buffer.scala:40:9] wire buffer_auto_in_d_ready; // @[Buffer.scala:40:9] wire [63:0] buffer_auto_in_d_bits_data; // @[Buffer.scala:40:9] wire [13:0] buffer_auto_in_d_bits_source; // @[Buffer.scala:40:9] wire [1:0] buffer_auto_in_d_bits_size; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_in_d_bits_opcode; // @[Buffer.scala:40:9] wire buffer_auto_in_a_valid; // @[Buffer.scala:40:9] wire buffer_auto_in_a_ready; // @[Buffer.scala:40:9] wire buffer_auto_in_a_bits_corrupt; // @[Buffer.scala:40:9] wire [63:0] buffer_auto_in_a_bits_data; // @[Buffer.scala:40:9] wire [7:0] buffer_auto_in_a_bits_mask; // @[Buffer.scala:40:9] wire [28:0] buffer_auto_in_a_bits_address; // @[Buffer.scala:40:9] wire [13:0] buffer_auto_in_a_bits_source; // @[Buffer.scala:40:9] wire [1:0] buffer_auto_in_a_bits_size; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_in_a_bits_param; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_in_a_bits_opcode; // @[Buffer.scala:40:9] wire _rxq_io_deq_valid; // @[UART.scala:133:19] wire [7:0] _rxq_io_deq_bits; // @[UART.scala:133:19] wire [3:0] _rxq_io_count; // @[UART.scala:133:19] wire _rxm_io_out_valid; // @[UART.scala:132:19] wire [7:0] _rxm_io_out_bits; // @[UART.scala:132:19] wire _txq_io_enq_ready; // @[UART.scala:130:19] wire _txq_io_deq_valid; // @[UART.scala:130:19] wire [7:0] _txq_io_deq_bits; // @[UART.scala:130:19] wire [3:0] _txq_io_count; // @[UART.scala:130:19] wire _txm_io_in_ready; // @[UART.scala:129:19] wire _txm_io_tx_busy; // @[UART.scala:129:19] wire auto_control_xing_in_a_valid_0 = auto_control_xing_in_a_valid; // @[UART.scala:127:25] wire [2:0] auto_control_xing_in_a_bits_opcode_0 = auto_control_xing_in_a_bits_opcode; // @[UART.scala:127:25] wire [2:0] auto_control_xing_in_a_bits_param_0 = auto_control_xing_in_a_bits_param; // @[UART.scala:127:25] wire [1:0] auto_control_xing_in_a_bits_size_0 = auto_control_xing_in_a_bits_size; // @[UART.scala:127:25] wire [13:0] auto_control_xing_in_a_bits_source_0 = auto_control_xing_in_a_bits_source; // @[UART.scala:127:25] wire [28:0] auto_control_xing_in_a_bits_address_0 = auto_control_xing_in_a_bits_address; // @[UART.scala:127:25] wire [7:0] auto_control_xing_in_a_bits_mask_0 = auto_control_xing_in_a_bits_mask; // @[UART.scala:127:25] wire [63:0] auto_control_xing_in_a_bits_data_0 = auto_control_xing_in_a_bits_data; // @[UART.scala:127:25] wire auto_control_xing_in_a_bits_corrupt_0 = auto_control_xing_in_a_bits_corrupt; // @[UART.scala:127:25] wire auto_control_xing_in_d_ready_0 = auto_control_xing_in_d_ready; // @[UART.scala:127:25] wire auto_io_out_rxd_0 = auto_io_out_rxd; // @[UART.scala:127:25] wire [8:0] out_maskMatch = 9'h1FC; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_15 = 8'h0; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_16 = 8'h0; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T = 8'h0; // @[RegisterRouter.scala:87:24] wire [8:0] out_prepend = 9'h0; // @[RegisterRouter.scala:87:24] wire [30:0] _out_T_24 = 31'h0; // @[RegisterRouter.scala:87:24] wire [30:0] _out_T_25 = 31'h0; // @[RegisterRouter.scala:87:24] wire [30:0] _out_prepend_T_1 = 31'h0; // @[RegisterRouter.scala:87:24] wire [2:0] controlNodeIn_d_bits_d_opcode = 3'h0; // @[Edges.scala:792:17] wire [63:0] controlNodeIn_d_bits_d_data = 64'h0; // @[Edges.scala:792:17] wire auto_control_xing_in_d_bits_sink = 1'h0; // @[UART.scala:127:25] wire auto_control_xing_in_d_bits_denied = 1'h0; // @[UART.scala:127:25] wire auto_control_xing_in_d_bits_corrupt = 1'h0; // @[UART.scala:127:25] wire buffer_auto_in_d_bits_sink = 1'h0; // @[Buffer.scala:40:9] wire buffer_auto_in_d_bits_denied = 1'h0; // @[Buffer.scala:40:9] wire buffer_auto_in_d_bits_corrupt = 1'h0; // @[Buffer.scala:40:9] wire buffer_auto_out_d_bits_sink = 1'h0; // @[Buffer.scala:40:9] wire buffer_auto_out_d_bits_denied = 1'h0; // @[Buffer.scala:40:9] wire buffer_auto_out_d_bits_corrupt = 1'h0; // @[Buffer.scala:40:9] wire buffer_nodeOut_d_bits_sink = 1'h0; // @[MixedNode.scala:542:17] wire buffer_nodeOut_d_bits_denied = 1'h0; // @[MixedNode.scala:542:17] wire buffer_nodeOut_d_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17] wire buffer_nodeIn_d_bits_sink = 1'h0; // @[MixedNode.scala:551:17] wire buffer_nodeIn_d_bits_denied = 1'h0; // @[MixedNode.scala:551:17] wire buffer_nodeIn_d_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17] wire controlNodeIn_d_bits_sink = 1'h0; // @[MixedNode.scala:551:17] wire controlNodeIn_d_bits_denied = 1'h0; // @[MixedNode.scala:551:17] wire controlNodeIn_d_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17] wire controlXingOut_d_bits_sink = 1'h0; // @[MixedNode.scala:542:17] wire controlXingOut_d_bits_denied = 1'h0; // @[MixedNode.scala:542:17] wire controlXingOut_d_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17] wire controlXingIn_d_bits_sink = 1'h0; // @[MixedNode.scala:551:17] wire controlXingIn_d_bits_denied = 1'h0; // @[MixedNode.scala:551:17] wire controlXingIn_d_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17] wire _ie_WIRE_rxwm = 1'h0; // @[UART.scala:186:32] wire _ie_WIRE_txwm = 1'h0; // @[UART.scala:186:32] wire _out_rifireMux_T_18 = 1'h0; // @[MuxLiteral.scala:49:17] wire _out_wifireMux_T_19 = 1'h0; // @[MuxLiteral.scala:49:17] wire _out_rofireMux_T_18 = 1'h0; // @[MuxLiteral.scala:49:17] wire _out_wofireMux_T_19 = 1'h0; // @[MuxLiteral.scala:49:17] wire _out_out_bits_data_T = 1'h0; // @[MuxLiteral.scala:49:17] wire _out_out_bits_data_T_2 = 1'h0; // @[MuxLiteral.scala:49:17] wire controlNodeIn_d_bits_d_sink = 1'h0; // @[Edges.scala:792:17] wire controlNodeIn_d_bits_d_denied = 1'h0; // @[Edges.scala:792:17] wire controlNodeIn_d_bits_d_corrupt = 1'h0; // @[Edges.scala:792:17] wire [1:0] auto_control_xing_in_d_bits_param = 2'h0; // @[UART.scala:127:25] wire [1:0] buffer_auto_in_d_bits_param = 2'h0; // @[Buffer.scala:40:9] wire [1:0] buffer_auto_out_d_bits_param = 2'h0; // @[Buffer.scala:40:9] wire [1:0] buffer_nodeOut_d_bits_param = 2'h0; // @[MixedNode.scala:542:17] wire [1:0] buffer_nodeIn_d_bits_param = 2'h0; // @[MixedNode.scala:551:17] wire [1:0] controlNodeIn_d_bits_param = 2'h0; // @[MixedNode.scala:551:17] wire [1:0] controlXingOut_d_bits_param = 2'h0; // @[MixedNode.scala:542:17] wire [1:0] controlXingIn_d_bits_param = 2'h0; // @[MixedNode.scala:551:17] wire [1:0] controlNodeIn_d_bits_d_param = 2'h0; // @[Edges.scala:792:17] wire intXingOut_sync_0; // @[MixedNode.scala:542:17] wire out_rifireMux_out = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_5 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_1 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_9 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_2 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_13 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_3 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_17 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_2 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_3 = 1'h1; // @[MuxLiteral.scala:49:48] wire out_rifireMux = 1'h1; // @[MuxLiteral.scala:49:10] wire out_wifireMux_out = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_6 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_1 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_10 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_2 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_14 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_3 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_18 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_2 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_3 = 1'h1; // @[MuxLiteral.scala:49:48] wire out_wifireMux = 1'h1; // @[MuxLiteral.scala:49:10] wire out_rofireMux_out = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_5 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_1 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_9 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_2 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_13 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_3 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_17 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_2 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_3 = 1'h1; // @[MuxLiteral.scala:49:48] wire out_rofireMux = 1'h1; // @[MuxLiteral.scala:49:10] wire out_wofireMux_out = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_6 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_1 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_10 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_2 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_14 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_3 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_18 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_2 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_3 = 1'h1; // @[MuxLiteral.scala:49:48] wire out_wofireMux = 1'h1; // @[MuxLiteral.scala:49:10] wire out_iready = 1'h1; // @[RegisterRouter.scala:87:24] wire out_oready = 1'h1; // @[RegisterRouter.scala:87:24] wire controlXingIn_a_ready; // @[MixedNode.scala:551:17] wire controlXingIn_a_valid = auto_control_xing_in_a_valid_0; // @[UART.scala:127:25] wire [2:0] controlXingIn_a_bits_opcode = auto_control_xing_in_a_bits_opcode_0; // @[UART.scala:127:25] wire [2:0] controlXingIn_a_bits_param = auto_control_xing_in_a_bits_param_0; // @[UART.scala:127:25] wire [1:0] controlXingIn_a_bits_size = auto_control_xing_in_a_bits_size_0; // @[UART.scala:127:25] wire [13:0] controlXingIn_a_bits_source = auto_control_xing_in_a_bits_source_0; // @[UART.scala:127:25] wire [28:0] controlXingIn_a_bits_address = auto_control_xing_in_a_bits_address_0; // @[UART.scala:127:25] wire [7:0] controlXingIn_a_bits_mask = auto_control_xing_in_a_bits_mask_0; // @[UART.scala:127:25] wire [63:0] controlXingIn_a_bits_data = auto_control_xing_in_a_bits_data_0; // @[UART.scala:127:25] wire controlXingIn_a_bits_corrupt = auto_control_xing_in_a_bits_corrupt_0; // @[UART.scala:127:25] wire controlXingIn_d_ready = auto_control_xing_in_d_ready_0; // @[UART.scala:127:25] wire controlXingIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] controlXingIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] controlXingIn_d_bits_size; // @[MixedNode.scala:551:17] wire [13:0] controlXingIn_d_bits_source; // @[MixedNode.scala:551:17] wire [63:0] controlXingIn_d_bits_data; // @[MixedNode.scala:551:17] wire ioNodeOut_txd; // @[MixedNode.scala:542:17] wire ioNodeOut_rxd = auto_io_out_rxd_0; // @[UART.scala:127:25] wire auto_int_xing_out_sync_0_0; // @[UART.scala:127:25] wire auto_control_xing_in_a_ready_0; // @[UART.scala:127:25] wire [2:0] auto_control_xing_in_d_bits_opcode_0; // @[UART.scala:127:25] wire [1:0] auto_control_xing_in_d_bits_size_0; // @[UART.scala:127:25] wire [13:0] auto_control_xing_in_d_bits_source_0; // @[UART.scala:127:25] wire [63:0] auto_control_xing_in_d_bits_data_0; // @[UART.scala:127:25] wire auto_control_xing_in_d_valid_0; // @[UART.scala:127:25] wire auto_io_out_txd_0; // @[UART.scala:127:25] wire buffer_nodeIn_a_ready; // @[MixedNode.scala:551:17] wire controlXingOut_a_ready = buffer_auto_in_a_ready; // @[Buffer.scala:40:9] wire controlXingOut_a_valid; // @[MixedNode.scala:542:17] wire buffer_nodeIn_a_valid = buffer_auto_in_a_valid; // @[Buffer.scala:40:9] wire [2:0] controlXingOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] buffer_nodeIn_a_bits_opcode = buffer_auto_in_a_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] controlXingOut_a_bits_param; // @[MixedNode.scala:542:17] wire [2:0] buffer_nodeIn_a_bits_param = buffer_auto_in_a_bits_param; // @[Buffer.scala:40:9] wire [1:0] controlXingOut_a_bits_size; // @[MixedNode.scala:542:17] wire [1:0] buffer_nodeIn_a_bits_size = buffer_auto_in_a_bits_size; // @[Buffer.scala:40:9] wire [13:0] controlXingOut_a_bits_source; // @[MixedNode.scala:542:17] wire [13:0] buffer_nodeIn_a_bits_source = buffer_auto_in_a_bits_source; // @[Buffer.scala:40:9] wire [28:0] controlXingOut_a_bits_address; // @[MixedNode.scala:542:17] wire [28:0] buffer_nodeIn_a_bits_address = buffer_auto_in_a_bits_address; // @[Buffer.scala:40:9] wire [7:0] controlXingOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [7:0] buffer_nodeIn_a_bits_mask = buffer_auto_in_a_bits_mask; // @[Buffer.scala:40:9] wire [63:0] controlXingOut_a_bits_data; // @[MixedNode.scala:542:17] wire [63:0] buffer_nodeIn_a_bits_data = buffer_auto_in_a_bits_data; // @[Buffer.scala:40:9] wire controlXingOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire buffer_nodeIn_a_bits_corrupt = buffer_auto_in_a_bits_corrupt; // @[Buffer.scala:40:9] wire controlXingOut_d_ready; // @[MixedNode.scala:542:17] wire buffer_nodeIn_d_ready = buffer_auto_in_d_ready; // @[Buffer.scala:40:9] wire buffer_nodeIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] buffer_nodeIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire controlXingOut_d_valid = buffer_auto_in_d_valid; // @[Buffer.scala:40:9] wire [2:0] controlXingOut_d_bits_opcode = buffer_auto_in_d_bits_opcode; // @[Buffer.scala:40:9] wire [1:0] buffer_nodeIn_d_bits_size; // @[MixedNode.scala:551:17] wire [13:0] buffer_nodeIn_d_bits_source; // @[MixedNode.scala:551:17] wire [1:0] controlXingOut_d_bits_size = buffer_auto_in_d_bits_size; // @[Buffer.scala:40:9] wire [13:0] controlXingOut_d_bits_source = buffer_auto_in_d_bits_source; // @[Buffer.scala:40:9] wire [63:0] buffer_nodeIn_d_bits_data; // @[MixedNode.scala:551:17] wire [63:0] controlXingOut_d_bits_data = buffer_auto_in_d_bits_data; // @[Buffer.scala:40:9] wire controlNodeIn_a_ready; // @[MixedNode.scala:551:17] wire buffer_nodeOut_a_ready = buffer_auto_out_a_ready; // @[Buffer.scala:40:9] wire buffer_nodeOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] buffer_nodeOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire controlNodeIn_a_valid = buffer_auto_out_a_valid; // @[Buffer.scala:40:9] wire [2:0] buffer_nodeOut_a_bits_param; // @[MixedNode.scala:542:17] wire [2:0] controlNodeIn_a_bits_opcode = buffer_auto_out_a_bits_opcode; // @[Buffer.scala:40:9] wire [1:0] buffer_nodeOut_a_bits_size; // @[MixedNode.scala:542:17] wire [2:0] controlNodeIn_a_bits_param = buffer_auto_out_a_bits_param; // @[Buffer.scala:40:9] wire [13:0] buffer_nodeOut_a_bits_source; // @[MixedNode.scala:542:17] wire [1:0] controlNodeIn_a_bits_size = buffer_auto_out_a_bits_size; // @[Buffer.scala:40:9] wire [28:0] buffer_nodeOut_a_bits_address; // @[MixedNode.scala:542:17] wire [13:0] controlNodeIn_a_bits_source = buffer_auto_out_a_bits_source; // @[Buffer.scala:40:9] wire [7:0] buffer_nodeOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [28:0] controlNodeIn_a_bits_address = buffer_auto_out_a_bits_address; // @[Buffer.scala:40:9] wire [63:0] buffer_nodeOut_a_bits_data; // @[MixedNode.scala:542:17] wire [7:0] controlNodeIn_a_bits_mask = buffer_auto_out_a_bits_mask; // @[Buffer.scala:40:9] wire buffer_nodeOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire [63:0] controlNodeIn_a_bits_data = buffer_auto_out_a_bits_data; // @[Buffer.scala:40:9] wire buffer_nodeOut_d_ready; // @[MixedNode.scala:542:17] wire controlNodeIn_a_bits_corrupt = buffer_auto_out_a_bits_corrupt; // @[Buffer.scala:40:9] wire controlNodeIn_d_ready = buffer_auto_out_d_ready; // @[Buffer.scala:40:9] wire controlNodeIn_d_valid; // @[MixedNode.scala:551:17] wire buffer_nodeOut_d_valid = buffer_auto_out_d_valid; // @[Buffer.scala:40:9] wire [2:0] controlNodeIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [2:0] buffer_nodeOut_d_bits_opcode = buffer_auto_out_d_bits_opcode; // @[Buffer.scala:40:9] wire [1:0] controlNodeIn_d_bits_size; // @[MixedNode.scala:551:17] wire [1:0] buffer_nodeOut_d_bits_size = buffer_auto_out_d_bits_size; // @[Buffer.scala:40:9] wire [13:0] controlNodeIn_d_bits_source; // @[MixedNode.scala:551:17] wire [13:0] buffer_nodeOut_d_bits_source = buffer_auto_out_d_bits_source; // @[Buffer.scala:40:9] wire [63:0] controlNodeIn_d_bits_data; // @[MixedNode.scala:551:17] wire [63:0] buffer_nodeOut_d_bits_data = buffer_auto_out_d_bits_data; // @[Buffer.scala:40:9] assign buffer_nodeIn_a_ready = buffer_nodeOut_a_ready; // @[MixedNode.scala:542:17, :551:17] assign buffer_auto_out_a_valid = buffer_nodeOut_a_valid; // @[Buffer.scala:40:9] assign buffer_auto_out_a_bits_opcode = buffer_nodeOut_a_bits_opcode; // @[Buffer.scala:40:9] assign buffer_auto_out_a_bits_param = buffer_nodeOut_a_bits_param; // @[Buffer.scala:40:9] assign buffer_auto_out_a_bits_size = buffer_nodeOut_a_bits_size; // @[Buffer.scala:40:9] assign buffer_auto_out_a_bits_source = buffer_nodeOut_a_bits_source; // @[Buffer.scala:40:9] assign buffer_auto_out_a_bits_address = buffer_nodeOut_a_bits_address; // @[Buffer.scala:40:9] assign buffer_auto_out_a_bits_mask = buffer_nodeOut_a_bits_mask; // @[Buffer.scala:40:9] assign buffer_auto_out_a_bits_data = buffer_nodeOut_a_bits_data; // @[Buffer.scala:40:9] assign buffer_auto_out_a_bits_corrupt = buffer_nodeOut_a_bits_corrupt; // @[Buffer.scala:40:9] assign buffer_auto_out_d_ready = buffer_nodeOut_d_ready; // @[Buffer.scala:40:9] assign buffer_nodeIn_d_valid = buffer_nodeOut_d_valid; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeIn_d_bits_opcode = buffer_nodeOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeIn_d_bits_size = buffer_nodeOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeIn_d_bits_source = buffer_nodeOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeIn_d_bits_data = buffer_nodeOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17] assign buffer_auto_in_a_ready = buffer_nodeIn_a_ready; // @[Buffer.scala:40:9] assign buffer_nodeOut_a_valid = buffer_nodeIn_a_valid; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeOut_a_bits_opcode = buffer_nodeIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeOut_a_bits_param = buffer_nodeIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeOut_a_bits_size = buffer_nodeIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeOut_a_bits_source = buffer_nodeIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeOut_a_bits_address = buffer_nodeIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeOut_a_bits_mask = buffer_nodeIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeOut_a_bits_data = buffer_nodeIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeOut_a_bits_corrupt = buffer_nodeIn_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeOut_d_ready = buffer_nodeIn_d_ready; // @[MixedNode.scala:542:17, :551:17] assign buffer_auto_in_d_valid = buffer_nodeIn_d_valid; // @[Buffer.scala:40:9] assign buffer_auto_in_d_bits_opcode = buffer_nodeIn_d_bits_opcode; // @[Buffer.scala:40:9] assign buffer_auto_in_d_bits_size = buffer_nodeIn_d_bits_size; // @[Buffer.scala:40:9] assign buffer_auto_in_d_bits_source = buffer_nodeIn_d_bits_source; // @[Buffer.scala:40:9] assign buffer_auto_in_d_bits_data = buffer_nodeIn_d_bits_data; // @[Buffer.scala:40:9] assign auto_io_out_txd_0 = ioNodeOut_txd; // @[UART.scala:127:25] wire _intnodeOut_0_T_2; // @[UART.scala:191:41] wire intnodeOut_0; // @[MixedNode.scala:542:17] wire in_ready; // @[RegisterRouter.scala:73:18] assign buffer_auto_out_a_ready = controlNodeIn_a_ready; // @[Buffer.scala:40:9] wire in_valid = controlNodeIn_a_valid; // @[RegisterRouter.scala:73:18] wire [1:0] in_bits_extra_tlrr_extra_size = controlNodeIn_a_bits_size; // @[RegisterRouter.scala:73:18] wire [13:0] in_bits_extra_tlrr_extra_source = controlNodeIn_a_bits_source; // @[RegisterRouter.scala:73:18] wire [7:0] in_bits_mask = controlNodeIn_a_bits_mask; // @[RegisterRouter.scala:73:18] wire [63:0] in_bits_data = controlNodeIn_a_bits_data; // @[RegisterRouter.scala:73:18] wire out_ready = controlNodeIn_d_ready; // @[RegisterRouter.scala:87:24] wire out_valid; // @[RegisterRouter.scala:87:24] assign buffer_auto_out_d_valid = controlNodeIn_d_valid; // @[Buffer.scala:40:9] assign buffer_auto_out_d_bits_opcode = controlNodeIn_d_bits_opcode; // @[Buffer.scala:40:9] wire [1:0] controlNodeIn_d_bits_d_size; // @[Edges.scala:792:17] assign buffer_auto_out_d_bits_size = controlNodeIn_d_bits_size; // @[Buffer.scala:40:9] wire [13:0] controlNodeIn_d_bits_d_source; // @[Edges.scala:792:17] assign buffer_auto_out_d_bits_source = controlNodeIn_d_bits_source; // @[Buffer.scala:40:9] wire [63:0] out_bits_data; // @[RegisterRouter.scala:87:24] assign buffer_auto_out_d_bits_data = controlNodeIn_d_bits_data; // @[Buffer.scala:40:9] assign controlXingIn_a_ready = controlXingOut_a_ready; // @[MixedNode.scala:542:17, :551:17] assign buffer_auto_in_a_valid = controlXingOut_a_valid; // @[Buffer.scala:40:9] assign buffer_auto_in_a_bits_opcode = controlXingOut_a_bits_opcode; // @[Buffer.scala:40:9] assign buffer_auto_in_a_bits_param = controlXingOut_a_bits_param; // @[Buffer.scala:40:9] assign buffer_auto_in_a_bits_size = controlXingOut_a_bits_size; // @[Buffer.scala:40:9] assign buffer_auto_in_a_bits_source = controlXingOut_a_bits_source; // @[Buffer.scala:40:9] assign buffer_auto_in_a_bits_address = controlXingOut_a_bits_address; // @[Buffer.scala:40:9] assign buffer_auto_in_a_bits_mask = controlXingOut_a_bits_mask; // @[Buffer.scala:40:9] assign buffer_auto_in_a_bits_data = controlXingOut_a_bits_data; // @[Buffer.scala:40:9] assign buffer_auto_in_a_bits_corrupt = controlXingOut_a_bits_corrupt; // @[Buffer.scala:40:9] assign buffer_auto_in_d_ready = controlXingOut_d_ready; // @[Buffer.scala:40:9] assign controlXingIn_d_valid = controlXingOut_d_valid; // @[MixedNode.scala:542:17, :551:17] assign controlXingIn_d_bits_opcode = controlXingOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign controlXingIn_d_bits_size = controlXingOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17] assign controlXingIn_d_bits_source = controlXingOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17] assign controlXingIn_d_bits_data = controlXingOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17] assign auto_control_xing_in_a_ready_0 = controlXingIn_a_ready; // @[UART.scala:127:25] assign controlXingOut_a_valid = controlXingIn_a_valid; // @[MixedNode.scala:542:17, :551:17] assign controlXingOut_a_bits_opcode = controlXingIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign controlXingOut_a_bits_param = controlXingIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17] assign controlXingOut_a_bits_size = controlXingIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17] assign controlXingOut_a_bits_source = controlXingIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17] assign controlXingOut_a_bits_address = controlXingIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17] assign controlXingOut_a_bits_mask = controlXingIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign controlXingOut_a_bits_data = controlXingIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17] assign controlXingOut_a_bits_corrupt = controlXingIn_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign controlXingOut_d_ready = controlXingIn_d_ready; // @[MixedNode.scala:542:17, :551:17] assign auto_control_xing_in_d_valid_0 = controlXingIn_d_valid; // @[UART.scala:127:25] assign auto_control_xing_in_d_bits_opcode_0 = controlXingIn_d_bits_opcode; // @[UART.scala:127:25] assign auto_control_xing_in_d_bits_size_0 = controlXingIn_d_bits_size; // @[UART.scala:127:25] assign auto_control_xing_in_d_bits_source_0 = controlXingIn_d_bits_source; // @[UART.scala:127:25] assign auto_control_xing_in_d_bits_data_0 = controlXingIn_d_bits_data; // @[UART.scala:127:25] wire intXingIn_sync_0; // @[MixedNode.scala:551:17] assign auto_int_xing_out_sync_0_0 = intXingOut_sync_0; // @[UART.scala:127:25] assign intXingOut_sync_0 = intXingIn_sync_0; // @[MixedNode.scala:542:17, :551:17] reg [15:0] div; // @[UART.scala:135:20] wire [15:0] _out_T_166 = div; // @[RegisterRouter.scala:87:24] reg txen; // @[UART.scala:141:21] wire _out_T_71 = txen; // @[RegisterRouter.scala:87:24] reg rxen; // @[UART.scala:142:21] reg [3:0] txwm; // @[UART.scala:149:21] reg [3:0] rxwm; // @[UART.scala:150:21] reg nstop; // @[UART.scala:151:22] wire _tx_busy_T = \|_txq_io_count; // @[UART.scala:130:19, :175:49] wire _tx_busy_T_1 = _txm_io_tx_busy \| _tx_busy_T; // @[UART.scala:129:19, :175:{33,49}] wire tx_busy = _tx_busy_T_1 & txen; // @[UART.scala:141:21, :175:{33,54}] reg ie_rxwm; // @[UART.scala:186:19] reg ie_txwm; // @[UART.scala:186:19] wire _out_T_126 = ie_txwm; // @[RegisterRouter.scala:87:24] wire _ip_rxwm_T; // @[UART.scala:190:28] wire _ip_txwm_T; // @[UART.scala:189:28] wire ip_rxwm; // @[UART.scala:187:16] wire ip_txwm; // @[UART.scala:187:16] assign _ip_txwm_T = _txq_io_count < txwm; // @[UART.scala:130:19, :149:21, :189:28] assign ip_txwm = _ip_txwm_T; // @[UART.scala:187:16, :189:28] assign _ip_rxwm_T = _rxq_io_count > rxwm; // @[UART.scala:133:19, :150:21, :190:28] assign ip_rxwm = _ip_rxwm_T; // @[UART.scala:187:16, :190:28] wire _intnodeOut_0_T = ip_txwm & ie_txwm; // @[UART.scala:186:19, :187:16, :191:29] wire _intnodeOut_0_T_1 = ip_rxwm & ie_rxwm; // @[UART.scala:186:19, :187:16, :191:53] assign _intnodeOut_0_T_2 = _intnodeOut_0_T \| _intnodeOut_0_T_1; // @[UART.scala:191:{29,41,53}] assign intnodeOut_0 = _intnodeOut_0_T_2; // @[UART.scala:191:41] wire _out_quash_T_1; // @[RegMapFIFO.scala:26:26] wire quash; // @[RegMapFIFO.scala:11:21] wire _out_in_ready_T; // @[RegisterRouter.scala:87:24] assign controlNodeIn_a_ready = in_ready; // @[RegisterRouter.scala:73:18] wire _in_bits_read_T; // @[RegisterRouter.scala:74:36] wire _out_front_valid_T = in_valid; // @[RegisterRouter.scala:73:18, :87:24] wire out_front_bits_read = in_bits_read; // @[RegisterRouter.scala:73:18, :87:24] wire [8:0] out_front_bits_index = in_bits_index; // @[RegisterRouter.scala:73:18, :87:24] wire [63:0] out_front_bits_data = in_bits_data; // @[RegisterRouter.scala:73:18, :87:24] wire [7:0] out_front_bits_mask = in_bits_mask; // @[RegisterRouter.scala:73:18, :87:24] wire [13:0] out_front_bits_extra_tlrr_extra_source = in_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:73:18, :87:24] wire [1:0] out_front_bits_extra_tlrr_extra_size = in_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:73:18, :87:24] assign _in_bits_read_T = controlNodeIn_a_bits_opcode == 3'h4; // @[RegisterRouter.scala:74:36] assign in_bits_read = _in_bits_read_T; // @[RegisterRouter.scala:73:18, :74:36] wire [25:0] _in_bits_index_T = controlNodeIn_a_bits_address[28:3]; // @[Edges.scala:192:34] assign in_bits_index = _in_bits_index_T[8:0]; // @[RegisterRouter.scala:73:18, :75:19] wire _out_front_ready_T = out_ready; // @[RegisterRouter.scala:87:24] wire _out_out_valid_T; // @[RegisterRouter.scala:87:24] assign controlNodeIn_d_valid = out_valid; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_T_4; // @[RegisterRouter.scala:87:24] wire _controlNodeIn_d_bits_opcode_T = out_bits_read; // @[RegisterRouter.scala:87:24, :105:25] assign controlNodeIn_d_bits_data = out_bits_data; // @[RegisterRouter.scala:87:24] assign controlNodeIn_d_bits_d_source = out_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:87:24] wire [1:0] out_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:87:24] assign controlNodeIn_d_bits_d_size = out_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:87:24] assign _out_in_ready_T = out_front_ready; // @[RegisterRouter.scala:87:24] assign _out_out_valid_T = out_front_valid; // @[RegisterRouter.scala:87:24] assign out_bits_read = out_front_bits_read; // @[RegisterRouter.scala:87:24] assign out_bits_extra_tlrr_extra_source = out_front_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:87:24] assign out_bits_extra_tlrr_extra_size = out_front_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:87:24] wire [8:0] _GEN = out_front_bits_index & 9'h1FC; // @[RegisterRouter.scala:87:24] wire [8:0] out_findex; // @[RegisterRouter.scala:87:24] assign out_findex = _GEN; // @[RegisterRouter.scala:87:24] wire [8:0] out_bindex; // @[RegisterRouter.scala:87:24] assign out_bindex = _GEN; // @[RegisterRouter.scala:87:24] wire _GEN_0 = out_findex == 9'h0; // @[RegisterRouter.scala:87:24] wire _out_T; // @[RegisterRouter.scala:87:24] assign _out_T = _GEN_0; // @[RegisterRouter.scala:87:24] wire _out_T_2; // @[RegisterRouter.scala:87:24] assign _out_T_2 = _GEN_0; // @[RegisterRouter.scala:87:24] wire _out_T_4; // @[RegisterRouter.scala:87:24] assign _out_T_4 = _GEN_0; // @[RegisterRouter.scala:87:24] wire _out_T_6; // @[RegisterRouter.scala:87:24] assign _out_T_6 = _GEN_0; // @[RegisterRouter.scala:87:24] wire _GEN_1 = out_bindex == 9'h0; // @[RegisterRouter.scala:87:24] wire _out_T_1; // @[RegisterRouter.scala:87:24] assign _out_T_1 = _GEN_1; // @[RegisterRouter.scala:87:24] wire _out_T_3; // @[RegisterRouter.scala:87:24] assign _out_T_3 = _GEN_1; // @[RegisterRouter.scala:87:24] wire _out_T_5; // @[RegisterRouter.scala:87:24] assign _out_T_5 = _GEN_1; // @[RegisterRouter.scala:87:24] wire _out_T_7; // @[RegisterRouter.scala:87:24] assign _out_T_7 = _GEN_1; // @[RegisterRouter.scala:87:24] wire _out_out_bits_data_WIRE_0 = _out_T_1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_1 = _out_T_3; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2 = _out_T_5; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24] wire _out_out_bits_data_WIRE_3 = _out_T_7; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_T_7; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_11; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_15; // @[RegisterRouter.scala:87:24] wire out_rivalid_0; // @[RegisterRouter.scala:87:24] wire out_rivalid_1; // @[RegisterRouter.scala:87:24] wire out_rivalid_2; // @[RegisterRouter.scala:87:24] wire out_rivalid_3; // @[RegisterRouter.scala:87:24] wire out_rivalid_4; // @[RegisterRouter.scala:87:24] wire out_rivalid_5; // @[RegisterRouter.scala:87:24] wire out_rivalid_6; // @[RegisterRouter.scala:87:24] wire out_rivalid_7; // @[RegisterRouter.scala:87:24] wire out_rivalid_8; // @[RegisterRouter.scala:87:24] wire out_rivalid_9; // @[RegisterRouter.scala:87:24] wire out_rivalid_10; // @[RegisterRouter.scala:87:24] wire out_rivalid_11; // @[RegisterRouter.scala:87:24] wire out_rivalid_12; // @[RegisterRouter.scala:87:24] wire out_rivalid_13; // @[RegisterRouter.scala:87:24] wire out_rivalid_14; // @[RegisterRouter.scala:87:24] wire out_rivalid_15; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_8; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_12; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_16; // @[RegisterRouter.scala:87:24] wire out_wivalid_0; // @[RegisterRouter.scala:87:24] wire out_wivalid_1; // @[RegisterRouter.scala:87:24] wire out_wivalid_2; // @[RegisterRouter.scala:87:24] wire out_wivalid_3; // @[RegisterRouter.scala:87:24] wire out_wivalid_4; // @[RegisterRouter.scala:87:24] wire out_wivalid_5; // @[RegisterRouter.scala:87:24] wire out_wivalid_6; // @[RegisterRouter.scala:87:24] wire out_wivalid_7; // @[RegisterRouter.scala:87:24] wire out_wivalid_8; // @[RegisterRouter.scala:87:24] wire out_wivalid_9; // @[RegisterRouter.scala:87:24] wire out_wivalid_10; // @[RegisterRouter.scala:87:24] wire out_wivalid_11; // @[RegisterRouter.scala:87:24] wire out_wivalid_12; // @[RegisterRouter.scala:87:24] wire out_wivalid_13; // @[RegisterRouter.scala:87:24] wire out_wivalid_14; // @[RegisterRouter.scala:87:24] wire out_wivalid_15; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_7; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_11; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_15; // @[RegisterRouter.scala:87:24] wire out_roready_0; // @[RegisterRouter.scala:87:24] wire out_roready_1; // @[RegisterRouter.scala:87:24] wire out_roready_2; // @[RegisterRouter.scala:87:24] wire out_roready_3; // @[RegisterRouter.scala:87:24] wire out_roready_4; // @[RegisterRouter.scala:87:24] wire out_roready_5; // @[RegisterRouter.scala:87:24] wire out_roready_6; // @[RegisterRouter.scala:87:24] wire out_roready_7; // @[RegisterRouter.scala:87:24] wire out_roready_8; // @[RegisterRouter.scala:87:24] wire out_roready_9; // @[RegisterRouter.scala:87:24] wire out_roready_10; // @[RegisterRouter.scala:87:24] wire out_roready_11; // @[RegisterRouter.scala:87:24] wire out_roready_12; // @[RegisterRouter.scala:87:24] wire out_roready_13; // @[RegisterRouter.scala:87:24] wire out_roready_14; // @[RegisterRouter.scala:87:24] wire out_roready_15; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_8; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_12; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_16; // @[RegisterRouter.scala:87:24] wire out_woready_0; // @[RegisterRouter.scala:87:24] wire out_woready_1; // @[RegisterRouter.scala:87:24] wire out_woready_2; // @[RegisterRouter.scala:87:24] wire out_woready_3; // @[RegisterRouter.scala:87:24] wire out_woready_4; // @[RegisterRouter.scala:87:24] wire out_woready_5; // @[RegisterRouter.scala:87:24] wire out_woready_6; // @[RegisterRouter.scala:87:24] wire out_woready_7; // @[RegisterRouter.scala:87:24] wire out_woready_8; // @[RegisterRouter.scala:87:24] wire out_woready_9; // @[RegisterRouter.scala:87:24] wire out_woready_10; // @[RegisterRouter.scala:87:24] wire out_woready_11; // @[RegisterRouter.scala:87:24] wire out_woready_12; // @[RegisterRouter.scala:87:24] wire out_woready_13; // @[RegisterRouter.scala:87:24] wire out_woready_14; // @[RegisterRouter.scala:87:24] wire out_woready_15; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T = out_front_bits_mask[0]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T = out_front_bits_mask[0]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_1 = out_front_bits_mask[1]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_1 = out_front_bits_mask[1]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_2 = out_front_bits_mask[2]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_2 = out_front_bits_mask[2]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_3 = out_front_bits_mask[3]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_3 = out_front_bits_mask[3]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_4 = out_front_bits_mask[4]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_4 = out_front_bits_mask[4]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_5 = out_front_bits_mask[5]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_5 = out_front_bits_mask[5]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_6 = out_front_bits_mask[6]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_6 = out_front_bits_mask[6]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_7 = out_front_bits_mask[7]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_7 = out_front_bits_mask[7]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_8 = {8{_out_frontMask_T}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_9 = {8{_out_frontMask_T_1}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_10 = {8{_out_frontMask_T_2}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_11 = {8{_out_frontMask_T_3}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_12 = {8{_out_frontMask_T_4}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_13 = {8{_out_frontMask_T_5}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_14 = {8{_out_frontMask_T_6}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_15 = {8{_out_frontMask_T_7}}; // @[RegisterRouter.scala:87:24] wire [15:0] out_frontMask_lo_lo = {_out_frontMask_T_9, _out_frontMask_T_8}; // @[RegisterRouter.scala:87:24] wire [15:0] out_frontMask_lo_hi = {_out_frontMask_T_11, _out_frontMask_T_10}; // @[RegisterRouter.scala:87:24] wire [31:0] out_frontMask_lo = {out_frontMask_lo_hi, out_frontMask_lo_lo}; // @[RegisterRouter.scala:87:24] wire [15:0] out_frontMask_hi_lo = {_out_frontMask_T_13, _out_frontMask_T_12}; // @[RegisterRouter.scala:87:24] wire [15:0] out_frontMask_hi_hi = {_out_frontMask_T_15, _out_frontMask_T_14}; // @[RegisterRouter.scala:87:24] wire [31:0] out_frontMask_hi = {out_frontMask_hi_hi, out_frontMask_hi_lo}; // @[RegisterRouter.scala:87:24] wire [63:0] out_frontMask = {out_frontMask_hi, out_frontMask_lo}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_8 = {8{_out_backMask_T}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_9 = {8{_out_backMask_T_1}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_10 = {8{_out_backMask_T_2}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_11 = {8{_out_backMask_T_3}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_12 = {8{_out_backMask_T_4}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_13 = {8{_out_backMask_T_5}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_14 = {8{_out_backMask_T_6}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_15 = {8{_out_backMask_T_7}}; // @[RegisterRouter.scala:87:24] wire [15:0] out_backMask_lo_lo = {_out_backMask_T_9, _out_backMask_T_8}; // @[RegisterRouter.scala:87:24] wire [15:0] out_backMask_lo_hi = {_out_backMask_T_11, _out_backMask_T_10}; // @[RegisterRouter.scala:87:24] wire [31:0] out_backMask_lo = {out_backMask_lo_hi, out_backMask_lo_lo}; // @[RegisterRouter.scala:87:24] wire [15:0] out_backMask_hi_lo = {_out_backMask_T_13, _out_backMask_T_12}; // @[RegisterRouter.scala:87:24] wire [15:0] out_backMask_hi_hi = {_out_backMask_T_15, _out_backMask_T_14}; // @[RegisterRouter.scala:87:24] wire [31:0] out_backMask_hi = {out_backMask_hi_hi, out_backMask_hi_lo}; // @[RegisterRouter.scala:87:24] wire [63:0] out_backMask = {out_backMask_hi, out_backMask_lo}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24] wire out_rimask = \|_out_rimask_T; // @[RegisterRouter.scala:87:24] wire out_wimask = &_out_wimask_T; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T = out_backMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T = out_backMask[7:0]; // @[RegisterRouter.scala:87:24] wire out_romask = \|_out_romask_T; // @[RegisterRouter.scala:87:24] wire out_womask = &_out_womask_T; // @[RegisterRouter.scala:87:24] wire out_f_rivalid = out_rivalid_0 & out_rimask; // @[RegisterRouter.scala:87:24] wire out_f_roready = out_roready_0 & out_romask; // @[RegisterRouter.scala:87:24] wire out_f_wivalid = out_wivalid_0 & out_wimask; // @[RegisterRouter.scala:87:24] wire _out_T_9 = out_f_wivalid; // @[RegisterRouter.scala:87:24] wire out_f_woready = out_woready_0 & out_womask; // @[RegisterRouter.scala:87:24] wire _out_T_10 = out_f_woready; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8 = out_front_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire _out_txq_io_enq_valid_T = ~quash; // @[RegMapFIFO.scala:11:21, :18:33] wire _out_txq_io_enq_valid_T_1 = out_f_woready & _out_txq_io_enq_valid_T; // @[RegisterRouter.scala:87:24] wire _out_T_11 = ~out_rimask; // @[RegisterRouter.scala:87:24] wire _out_T_12 = ~out_wimask; // @[RegisterRouter.scala:87:24] wire _out_T_13 = ~out_romask; // @[RegisterRouter.scala:87:24] wire _out_T_14 = ~out_womask; // @[RegisterRouter.scala:87:24] wire [22:0] _out_rimask_T_1 = out_frontMask[30:8]; // @[RegisterRouter.scala:87:24] wire [22:0] _out_wimask_T_1 = out_frontMask[30:8]; // @[RegisterRouter.scala:87:24] wire out_rimask_1 = \|_out_rimask_T_1; // @[RegisterRouter.scala:87:24] wire out_wimask_1 = &_out_wimask_T_1; // @[RegisterRouter.scala:87:24] wire [22:0] _out_romask_T_1 = out_backMask[30:8]; // @[RegisterRouter.scala:87:24] wire [22:0] _out_womask_T_1 = out_backMask[30:8]; // @[RegisterRouter.scala:87:24] wire out_romask_1 = \|_out_romask_T_1; // @[RegisterRouter.scala:87:24] wire out_womask_1 = &_out_womask_T_1; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1 = out_rivalid_1 & out_rimask_1; // @[RegisterRouter.scala:87:24] wire _out_T_18 = out_f_rivalid_1; // @[RegisterRouter.scala:87:24] wire out_f_roready_1 = out_roready_1 & out_romask_1; // @[RegisterRouter.scala:87:24] wire _out_T_19 = out_f_roready_1; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1 = out_wivalid_1 & out_wimask_1; // @[RegisterRouter.scala:87:24] wire out_f_woready_1 = out_woready_1 & out_womask_1; // @[RegisterRouter.scala:87:24] wire [22:0] _out_T_17 = out_front_bits_data[30:8]; // @[RegisterRouter.scala:87:24] wire _out_T_20 = ~out_rimask_1; // @[RegisterRouter.scala:87:24] wire _out_T_21 = ~out_wimask_1; // @[RegisterRouter.scala:87:24] wire _out_T_22 = ~out_romask_1; // @[RegisterRouter.scala:87:24] wire _out_T_23 = ~out_womask_1; // @[RegisterRouter.scala:87:24] wire _out_rimask_T_2 = out_frontMask[31]; // @[RegisterRouter.scala:87:24] wire _out_wimask_T_2 = out_frontMask[31]; // @[RegisterRouter.scala:87:24] wire out_rimask_2 = _out_rimask_T_2; // @[RegisterRouter.scala:87:24] wire out_wimask_2 = _out_wimask_T_2; // @[RegisterRouter.scala:87:24] wire _out_romask_T_2 = out_backMask[31]; // @[RegisterRouter.scala:87:24] wire _out_womask_T_2 = out_backMask[31]; // @[RegisterRouter.scala:87:24] wire out_romask_2 = _out_romask_T_2; // @[RegisterRouter.scala:87:24] wire out_womask_2 = _out_womask_T_2; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_2 = out_rivalid_2 & out_rimask_2; // @[RegisterRouter.scala:87:24] wire _out_T_27 = out_f_rivalid_2; // @[RegisterRouter.scala:87:24] wire out_f_roready_2 = out_roready_2 & out_romask_2; // @[RegisterRouter.scala:87:24] wire _out_T_28 = out_f_roready_2; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_2 = out_wivalid_2 & out_wimask_2; // @[RegisterRouter.scala:87:24] wire out_f_woready_2 = out_woready_2 & out_womask_2; // @[RegisterRouter.scala:87:24] wire _out_T_26 = out_front_bits_data[31]; // @[RegisterRouter.scala:87:24] wire _out_quash_T = _out_T_26; // @[RegisterRouter.scala:87:24] assign _out_quash_T_1 = out_f_woready_2 & _out_quash_T; // @[RegisterRouter.scala:87:24] assign quash = _out_quash_T_1; // @[RegMapFIFO.scala:11:21, :26:26] wire _out_T_29 = ~out_rimask_2; // @[RegisterRouter.scala:87:24] wire _out_T_30 = ~out_wimask_2; // @[RegisterRouter.scala:87:24] wire _out_T_31 = ~out_romask_2; // @[RegisterRouter.scala:87:24] wire _out_T_32 = ~out_womask_2; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_1 = {~_txq_io_enq_ready, 31'h0}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_33 = out_prepend_1; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_34 = _out_T_33; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_2 = _out_T_34; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_3 = out_frontMask[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_3 = out_frontMask[39:32]; // @[RegisterRouter.scala:87:24] wire out_rimask_3 = \|_out_rimask_T_3; // @[RegisterRouter.scala:87:24] wire out_wimask_3 = &_out_wimask_T_3; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_3 = out_backMask[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_3 = out_backMask[39:32]; // @[RegisterRouter.scala:87:24] wire out_romask_3 = \|_out_romask_T_3; // @[RegisterRouter.scala:87:24] wire out_womask_3 = &_out_womask_T_3; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_3 = out_rivalid_3 & out_rimask_3; // @[RegisterRouter.scala:87:24] wire _out_T_36 = out_f_rivalid_3; // @[RegisterRouter.scala:87:24] wire out_f_roready_3 = out_roready_3 & out_romask_3; // @[RegisterRouter.scala:87:24] wire _out_T_37 = out_f_roready_3; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_3 = out_wivalid_3 & out_wimask_3; // @[RegisterRouter.scala:87:24] wire out_f_woready_3 = out_woready_3 & out_womask_3; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_35 = out_front_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire _out_T_38 = ~out_rimask_3; // @[RegisterRouter.scala:87:24] wire _out_T_39 = ~out_wimask_3; // @[RegisterRouter.scala:87:24] wire _out_T_40 = ~out_romask_3; // @[RegisterRouter.scala:87:24] wire _out_T_41 = ~out_womask_3; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_2 = {_rxq_io_deq_bits, _out_prepend_T_2}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_42 = out_prepend_2; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_43 = _out_T_42; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_3 = _out_T_43; // @[RegisterRouter.scala:87:24] wire [22:0] _out_rimask_T_4 = out_frontMask[62:40]; // @[RegisterRouter.scala:87:24] wire [22:0] _out_wimask_T_4 = out_frontMask[62:40]; // @[RegisterRouter.scala:87:24] wire out_rimask_4 = \|_out_rimask_T_4; // @[RegisterRouter.scala:87:24] wire out_wimask_4 = &_out_wimask_T_4; // @[RegisterRouter.scala:87:24] wire [22:0] _out_romask_T_4 = out_backMask[62:40]; // @[RegisterRouter.scala:87:24] wire [22:0] _out_womask_T_4 = out_backMask[62:40]; // @[RegisterRouter.scala:87:24] wire out_romask_4 = \|_out_romask_T_4; // @[RegisterRouter.scala:87:24] wire out_womask_4 = &_out_womask_T_4; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_4 = out_rivalid_4 & out_rimask_4; // @[RegisterRouter.scala:87:24] wire _out_T_45 = out_f_rivalid_4; // @[RegisterRouter.scala:87:24] wire out_f_roready_4 = out_roready_4 & out_romask_4; // @[RegisterRouter.scala:87:24] wire _out_T_46 = out_f_roready_4; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_4 = out_wivalid_4 & out_wimask_4; // @[RegisterRouter.scala:87:24] wire out_f_woready_4 = out_woready_4 & out_womask_4; // @[RegisterRouter.scala:87:24] wire [22:0] _out_T_44 = out_front_bits_data[62:40]; // @[RegisterRouter.scala:87:24] wire _out_T_47 = ~out_rimask_4; // @[RegisterRouter.scala:87:24] wire _out_T_48 = ~out_wimask_4; // @[RegisterRouter.scala:87:24] wire _out_T_49 = ~out_romask_4; // @[RegisterRouter.scala:87:24] wire _out_T_50 = ~out_womask_4; // @[RegisterRouter.scala:87:24] wire [40:0] out_prepend_3 = {1'h0, _out_prepend_T_3}; // @[RegisterRouter.scala:87:24] wire [62:0] _out_T_51 = {22'h0, out_prepend_3}; // @[RegisterRouter.scala:87:24] wire [62:0] _out_T_52 = _out_T_51; // @[RegisterRouter.scala:87:24] wire [62:0] _out_prepend_T_4 = _out_T_52; // @[RegisterRouter.scala:87:24] wire _out_rimask_T_5 = out_frontMask[63]; // @[RegisterRouter.scala:87:24] wire _out_wimask_T_5 = out_frontMask[63]; // @[RegisterRouter.scala:87:24] wire out_rimask_5 = _out_rimask_T_5; // @[RegisterRouter.scala:87:24] wire out_wimask_5 = _out_wimask_T_5; // @[RegisterRouter.scala:87:24] wire _out_romask_T_5 = out_backMask[63]; // @[RegisterRouter.scala:87:24] wire _out_womask_T_5 = out_backMask[63]; // @[RegisterRouter.scala:87:24] wire out_romask_5 = _out_romask_T_5; // @[RegisterRouter.scala:87:24] wire out_womask_5 = _out_womask_T_5; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_5 = out_rivalid_5 & out_rimask_5; // @[RegisterRouter.scala:87:24] wire _out_T_54 = out_f_rivalid_5; // @[RegisterRouter.scala:87:24] wire out_f_roready_5 = out_roready_5 & out_romask_5; // @[RegisterRouter.scala:87:24] wire _out_T_55 = out_f_roready_5; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_5 = out_wivalid_5 & out_wimask_5; // @[RegisterRouter.scala:87:24] wire out_f_woready_5 = out_woready_5 & out_womask_5; // @[RegisterRouter.scala:87:24] wire _out_T_53 = out_front_bits_data[63]; // @[RegisterRouter.scala:87:24] wire _out_T_56 = ~out_rimask_5; // @[RegisterRouter.scala:87:24] wire _out_T_57 = ~out_wimask_5; // @[RegisterRouter.scala:87:24] wire _out_T_58 = ~out_romask_5; // @[RegisterRouter.scala:87:24] wire _out_T_59 = ~out_womask_5; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_4 = {~_rxq_io_deq_valid, _out_prepend_T_4}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_60 = out_prepend_4; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_61 = _out_T_60; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_1_0 = _out_T_61; // @[MuxLiteral.scala:49:48] wire _out_rimask_T_6 = out_frontMask[0]; // @[RegisterRouter.scala:87:24] wire _out_wimask_T_6 = out_frontMask[0]; // @[RegisterRouter.scala:87:24] wire _out_rimask_T_11 = out_frontMask[0]; // @[RegisterRouter.scala:87:24] wire _out_wimask_T_11 = out_frontMask[0]; // @[RegisterRouter.scala:87:24] wire out_rimask_6 = _out_rimask_T_6; // @[RegisterRouter.scala:87:24] wire out_wimask_6 = _out_wimask_T_6; // @[RegisterRouter.scala:87:24] wire _out_romask_T_6 = out_backMask[0]; // @[RegisterRouter.scala:87:24] wire _out_womask_T_6 = out_backMask[0]; // @[RegisterRouter.scala:87:24] wire _out_romask_T_11 = out_backMask[0]; // @[RegisterRouter.scala:87:24] wire _out_womask_T_11 = out_backMask[0]; // @[RegisterRouter.scala:87:24] wire out_romask_6 = _out_romask_T_6; // @[RegisterRouter.scala:87:24] wire out_womask_6 = _out_womask_T_6; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_6 = out_rivalid_6 & out_rimask_6; // @[RegisterRouter.scala:87:24] wire _out_T_63 = out_f_rivalid_6; // @[RegisterRouter.scala:87:24] wire out_f_roready_6 = out_roready_6 & out_romask_6; // @[RegisterRouter.scala:87:24] wire _out_T_64 = out_f_roready_6; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_6 = out_wivalid_6 & out_wimask_6; // @[RegisterRouter.scala:87:24] wire _out_T_65 = out_f_wivalid_6; // @[RegisterRouter.scala:87:24] wire out_f_woready_6 = out_woready_6 & out_womask_6; // @[RegisterRouter.scala:87:24] wire _out_T_66 = out_f_woready_6; // @[RegisterRouter.scala:87:24] wire _out_T_62 = out_front_bits_data[0]; // @[RegisterRouter.scala:87:24] wire _out_T_117 = out_front_bits_data[0]; // @[RegisterRouter.scala:87:24] wire _out_T_67 = ~out_rimask_6; // @[RegisterRouter.scala:87:24] wire _out_T_68 = ~out_wimask_6; // @[RegisterRouter.scala:87:24] wire _out_T_69 = ~out_romask_6; // @[RegisterRouter.scala:87:24] wire _out_T_70 = ~out_womask_6; // @[RegisterRouter.scala:87:24] wire _out_T_72 = _out_T_71; // @[RegisterRouter.scala:87:24] wire _out_prepend_T_5 = _out_T_72; // @[RegisterRouter.scala:87:24] wire _out_rimask_T_7 = out_frontMask[1]; // @[RegisterRouter.scala:87:24] wire _out_wimask_T_7 = out_frontMask[1]; // @[RegisterRouter.scala:87:24] wire _out_rimask_T_12 = out_frontMask[1]; // @[RegisterRouter.scala:87:24] wire _out_wimask_T_12 = out_frontMask[1]; // @[RegisterRouter.scala:87:24] wire out_rimask_7 = _out_rimask_T_7; // @[RegisterRouter.scala:87:24] wire out_wimask_7 = _out_wimask_T_7; // @[RegisterRouter.scala:87:24] wire _out_romask_T_7 = out_backMask[1]; // @[RegisterRouter.scala:87:24] wire _out_womask_T_7 = out_backMask[1]; // @[RegisterRouter.scala:87:24] wire _out_romask_T_12 = out_backMask[1]; // @[RegisterRouter.scala:87:24] wire _out_womask_T_12 = out_backMask[1]; // @[RegisterRouter.scala:87:24] wire out_romask_7 = _out_romask_T_7; // @[RegisterRouter.scala:87:24] wire out_womask_7 = _out_womask_T_7; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_7 = out_rivalid_7 & out_rimask_7; // @[RegisterRouter.scala:87:24] wire _out_T_74 = out_f_rivalid_7; // @[RegisterRouter.scala:87:24] wire out_f_roready_7 = out_roready_7 & out_romask_7; // @[RegisterRouter.scala:87:24] wire _out_T_75 = out_f_roready_7; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_7 = out_wivalid_7 & out_wimask_7; // @[RegisterRouter.scala:87:24] wire _out_T_76 = out_f_wivalid_7; // @[RegisterRouter.scala:87:24] wire out_f_woready_7 = out_woready_7 & out_womask_7; // @[RegisterRouter.scala:87:24] wire _out_T_77 = out_f_woready_7; // @[RegisterRouter.scala:87:24] wire _out_T_73 = out_front_bits_data[1]; // @[RegisterRouter.scala:87:24] wire _out_T_128 = out_front_bits_data[1]; // @[RegisterRouter.scala:87:24] wire _out_T_78 = ~out_rimask_7; // @[RegisterRouter.scala:87:24] wire _out_T_79 = ~out_wimask_7; // @[RegisterRouter.scala:87:24] wire _out_T_80 = ~out_romask_7; // @[RegisterRouter.scala:87:24] wire _out_T_81 = ~out_womask_7; // @[RegisterRouter.scala:87:24] wire [1:0] out_prepend_5 = {nstop, _out_prepend_T_5}; // @[RegisterRouter.scala:87:24] wire [1:0] _out_T_82 = out_prepend_5; // @[RegisterRouter.scala:87:24] wire [1:0] _out_T_83 = _out_T_82; // @[RegisterRouter.scala:87:24] wire [3:0] _out_rimask_T_8 = out_frontMask[19:16]; // @[RegisterRouter.scala:87:24] wire [3:0] _out_wimask_T_8 = out_frontMask[19:16]; // @[RegisterRouter.scala:87:24] wire out_rimask_8 = \|_out_rimask_T_8; // @[RegisterRouter.scala:87:24] wire out_wimask_8 = &_out_wimask_T_8; // @[RegisterRouter.scala:87:24] wire [3:0] _out_romask_T_8 = out_backMask[19:16]; // @[RegisterRouter.scala:87:24] wire [3:0] _out_womask_T_8 = out_backMask[19:16]; // @[RegisterRouter.scala:87:24] wire out_romask_8 = \|_out_romask_T_8; // @[RegisterRouter.scala:87:24] wire out_womask_8 = &_out_womask_T_8; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_8 = out_rivalid_8 & out_rimask_8; // @[RegisterRouter.scala:87:24] wire _out_T_85 = out_f_rivalid_8; // @[RegisterRouter.scala:87:24] wire out_f_roready_8 = out_roready_8 & out_romask_8; // @[RegisterRouter.scala:87:24] wire _out_T_86 = out_f_roready_8; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_8 = out_wivalid_8 & out_wimask_8; // @[RegisterRouter.scala:87:24] wire _out_T_87 = out_f_wivalid_8; // @[RegisterRouter.scala:87:24] wire out_f_woready_8 = out_woready_8 & out_womask_8; // @[RegisterRouter.scala:87:24] wire _out_T_88 = out_f_woready_8; // @[RegisterRouter.scala:87:24] wire [3:0] _out_T_84 = out_front_bits_data[19:16]; // @[RegisterRouter.scala:87:24] wire _out_T_89 = ~out_rimask_8; // @[RegisterRouter.scala:87:24] wire _out_T_90 = ~out_wimask_8; // @[RegisterRouter.scala:87:24] wire _out_T_91 = ~out_romask_8; // @[RegisterRouter.scala:87:24] wire _out_T_92 = ~out_womask_8; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_6 = {14'h0, _out_T_83}; // @[RegisterRouter.scala:87:24] wire [19:0] out_prepend_6 = {txwm, _out_prepend_T_6}; // @[RegisterRouter.scala:87:24] wire [19:0] _out_T_93 = out_prepend_6; // @[RegisterRouter.scala:87:24] wire [19:0] _out_T_94 = _out_T_93; // @[RegisterRouter.scala:87:24] wire _out_rimask_T_9 = out_frontMask[32]; // @[RegisterRouter.scala:87:24] wire _out_wimask_T_9 = out_frontMask[32]; // @[RegisterRouter.scala:87:24] wire _out_rimask_T_13 = out_frontMask[32]; // @[RegisterRouter.scala:87:24] wire _out_wimask_T_13 = out_frontMask[32]; // @[RegisterRouter.scala:87:24] wire out_rimask_9 = _out_rimask_T_9; // @[RegisterRouter.scala:87:24] wire out_wimask_9 = _out_wimask_T_9; // @[RegisterRouter.scala:87:24] wire _out_romask_T_9 = out_backMask[32]; // @[RegisterRouter.scala:87:24] wire _out_womask_T_9 = out_backMask[32]; // @[RegisterRouter.scala:87:24] wire _out_romask_T_13 = out_backMask[32]; // @[RegisterRouter.scala:87:24] wire _out_womask_T_13 = out_backMask[32]; // @[RegisterRouter.scala:87:24] wire out_romask_9 = _out_romask_T_9; // @[RegisterRouter.scala:87:24] wire out_womask_9 = _out_womask_T_9; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_9 = out_rivalid_9 & out_rimask_9; // @[RegisterRouter.scala:87:24] wire _out_T_96 = out_f_rivalid_9; // @[RegisterRouter.scala:87:24] wire out_f_roready_9 = out_roready_9 & out_romask_9; // @[RegisterRouter.scala:87:24] wire _out_T_97 = out_f_roready_9; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_9 = out_wivalid_9 & out_wimask_9; // @[RegisterRouter.scala:87:24] wire _out_T_98 = out_f_wivalid_9; // @[RegisterRouter.scala:87:24] wire out_f_woready_9 = out_woready_9 & out_womask_9; // @[RegisterRouter.scala:87:24] wire _out_T_99 = out_f_woready_9; // @[RegisterRouter.scala:87:24] wire _out_T_95 = out_front_bits_data[32]; // @[RegisterRouter.scala:87:24] wire _out_T_139 = out_front_bits_data[32]; // @[RegisterRouter.scala:87:24] wire _out_T_100 = ~out_rimask_9; // @[RegisterRouter.scala:87:24] wire _out_T_101 = ~out_wimask_9; // @[RegisterRouter.scala:87:24] wire _out_T_102 = ~out_romask_9; // @[RegisterRouter.scala:87:24] wire _out_T_103 = ~out_womask_9; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_7 = {12'h0, _out_T_94}; // @[RegisterRouter.scala:87:24] wire [32:0] out_prepend_7 = {rxen, _out_prepend_T_7}; // @[RegisterRouter.scala:87:24] wire [32:0] _out_T_104 = out_prepend_7; // @[RegisterRouter.scala:87:24] wire [32:0] _out_T_105 = _out_T_104; // @[RegisterRouter.scala:87:24] wire [3:0] _out_rimask_T_10 = out_frontMask[51:48]; // @[RegisterRouter.scala:87:24] wire [3:0] _out_wimask_T_10 = out_frontMask[51:48]; // @[RegisterRouter.scala:87:24] wire out_rimask_10 = \|_out_rimask_T_10; // @[RegisterRouter.scala:87:24] wire out_wimask_10 = &_out_wimask_T_10; // @[RegisterRouter.scala:87:24] wire [3:0] _out_romask_T_10 = out_backMask[51:48]; // @[RegisterRouter.scala:87:24] wire [3:0] _out_womask_T_10 = out_backMask[51:48]; // @[RegisterRouter.scala:87:24] wire out_romask_10 = \|_out_romask_T_10; // @[RegisterRouter.scala:87:24] wire out_womask_10 = &_out_womask_T_10; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_10 = out_rivalid_10 & out_rimask_10; // @[RegisterRouter.scala:87:24] wire _out_T_107 = out_f_rivalid_10; // @[RegisterRouter.scala:87:24] wire out_f_roready_10 = out_roready_10 & out_romask_10; // @[RegisterRouter.scala:87:24] wire _out_T_108 = out_f_roready_10; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_10 = out_wivalid_10 & out_wimask_10; // @[RegisterRouter.scala:87:24] wire _out_T_109 = out_f_wivalid_10; // @[RegisterRouter.scala:87:24] wire out_f_woready_10 = out_woready_10 & out_womask_10; // @[RegisterRouter.scala:87:24] wire _out_T_110 = out_f_woready_10; // @[RegisterRouter.scala:87:24] wire [3:0] _out_T_106 = out_front_bits_data[51:48]; // @[RegisterRouter.scala:87:24] wire _out_T_111 = ~out_rimask_10; // @[RegisterRouter.scala:87:24] wire _out_T_112 = ~out_wimask_10; // @[RegisterRouter.scala:87:24] wire _out_T_113 = ~out_romask_10; // @[RegisterRouter.scala:87:24] wire _out_T_114 = ~out_womask_10; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_8 = {15'h0, _out_T_105}; // @[RegisterRouter.scala:87:24] wire [51:0] out_prepend_8 = {rxwm, _out_prepend_T_8}; // @[RegisterRouter.scala:87:24] wire [51:0] _out_T_115 = out_prepend_8; // @[RegisterRouter.scala:87:24] wire [51:0] _out_T_116 = _out_T_115; // @[RegisterRouter.scala:87:24] wire out_rimask_11 = _out_rimask_T_11; // @[RegisterRouter.scala:87:24] wire out_wimask_11 = _out_wimask_T_11; // @[RegisterRouter.scala:87:24] wire out_romask_11 = _out_romask_T_11; // @[RegisterRouter.scala:87:24] wire out_womask_11 = _out_womask_T_11; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_11 = out_rivalid_11 & out_rimask_11; // @[RegisterRouter.scala:87:24] wire _out_T_118 = out_f_rivalid_11; // @[RegisterRouter.scala:87:24] wire out_f_roready_11 = out_roready_11 & out_romask_11; // @[RegisterRouter.scala:87:24] wire _out_T_119 = out_f_roready_11; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_11 = out_wivalid_11 & out_wimask_11; // @[RegisterRouter.scala:87:24] wire _out_T_120 = out_f_wivalid_11; // @[RegisterRouter.scala:87:24] wire out_f_woready_11 = out_woready_11 & out_womask_11; // @[RegisterRouter.scala:87:24] wire _out_T_121 = out_f_woready_11; // @[RegisterRouter.scala:87:24] wire _out_T_122 = ~out_rimask_11; // @[RegisterRouter.scala:87:24] wire _out_T_123 = ~out_wimask_11; // @[RegisterRouter.scala:87:24] wire _out_T_124 = ~out_romask_11; // @[RegisterRouter.scala:87:24] wire _out_T_125 = ~out_womask_11; // @[RegisterRouter.scala:87:24] wire _out_T_127 = _out_T_126; // @[RegisterRouter.scala:87:24] wire _out_prepend_T_9 = _out_T_127; // @[RegisterRouter.scala:87:24] wire out_rimask_12 = _out_rimask_T_12; // @[RegisterRouter.scala:87:24] wire out_wimask_12 = _out_wimask_T_12; // @[RegisterRouter.scala:87:24] wire out_romask_12 = _out_romask_T_12; // @[RegisterRouter.scala:87:24] wire out_womask_12 = _out_womask_T_12; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_12 = out_rivalid_12 & out_rimask_12; // @[RegisterRouter.scala:87:24] wire _out_T_129 = out_f_rivalid_12; // @[RegisterRouter.scala:87:24] wire out_f_roready_12 = out_roready_12 & out_romask_12; // @[RegisterRouter.scala:87:24] wire _out_T_130 = out_f_roready_12; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_12 = out_wivalid_12 & out_wimask_12; // @[RegisterRouter.scala:87:24] wire _out_T_131 = out_f_wivalid_12; // @[RegisterRouter.scala:87:24] wire out_f_woready_12 = out_woready_12 & out_womask_12; // @[RegisterRouter.scala:87:24] wire _out_T_132 = out_f_woready_12; // @[RegisterRouter.scala:87:24] wire _out_T_133 = ~out_rimask_12; // @[RegisterRouter.scala:87:24] wire _out_T_134 = ~out_wimask_12; // @[RegisterRouter.scala:87:24] wire _out_T_135 = ~out_romask_12; // @[RegisterRouter.scala:87:24] wire _out_T_136 = ~out_womask_12; // @[RegisterRouter.scala:87:24] wire [1:0] out_prepend_9 = {ie_rxwm, _out_prepend_T_9}; // @[RegisterRouter.scala:87:24] wire [1:0] _out_T_137 = out_prepend_9; // @[RegisterRouter.scala:87:24] wire [1:0] _out_T_138 = _out_T_137; // @[RegisterRouter.scala:87:24] wire out_rimask_13 = _out_rimask_T_13; // @[RegisterRouter.scala:87:24] wire out_wimask_13 = _out_wimask_T_13; // @[RegisterRouter.scala:87:24] wire out_romask_13 = _out_romask_T_13; // @[RegisterRouter.scala:87:24] wire out_womask_13 = _out_womask_T_13; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_13 = out_rivalid_13 & out_rimask_13; // @[RegisterRouter.scala:87:24] wire _out_T_140 = out_f_rivalid_13; // @[RegisterRouter.scala:87:24] wire out_f_roready_13 = out_roready_13 & out_romask_13; // @[RegisterRouter.scala:87:24] wire _out_T_141 = out_f_roready_13; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_13 = out_wivalid_13 & out_wimask_13; // @[RegisterRouter.scala:87:24] wire out_f_woready_13 = out_woready_13 & out_womask_13; // @[RegisterRouter.scala:87:24] wire _out_T_142 = ~out_rimask_13; // @[RegisterRouter.scala:87:24] wire _out_T_143 = ~out_wimask_13; // @[RegisterRouter.scala:87:24] wire _out_T_144 = ~out_romask_13; // @[RegisterRouter.scala:87:24] wire _out_T_145 = ~out_womask_13; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_10 = {30'h0, _out_T_138}; // @[RegisterRouter.scala:87:24] wire [32:0] out_prepend_10 = {ip_txwm, _out_prepend_T_10}; // @[RegisterRouter.scala:87:24] wire [32:0] _out_T_146 = out_prepend_10; // @[RegisterRouter.scala:87:24] wire [32:0] _out_T_147 = _out_T_146; // @[RegisterRouter.scala:87:24] wire [32:0] _out_prepend_T_11 = _out_T_147; // @[RegisterRouter.scala:87:24] wire _out_rimask_T_14 = out_frontMask[33]; // @[RegisterRouter.scala:87:24] wire _out_wimask_T_14 = out_frontMask[33]; // @[RegisterRouter.scala:87:24] wire out_rimask_14 = _out_rimask_T_14; // @[RegisterRouter.scala:87:24] wire out_wimask_14 = _out_wimask_T_14; // @[RegisterRouter.scala:87:24] wire _out_romask_T_14 = out_backMask[33]; // @[RegisterRouter.scala:87:24] wire _out_womask_T_14 = out_backMask[33]; // @[RegisterRouter.scala:87:24] wire out_romask_14 = _out_romask_T_14; // @[RegisterRouter.scala:87:24] wire out_womask_14 = _out_womask_T_14; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_14 = out_rivalid_14 & out_rimask_14; // @[RegisterRouter.scala:87:24] wire _out_T_149 = out_f_rivalid_14; // @[RegisterRouter.scala:87:24] wire out_f_roready_14 = out_roready_14 & out_romask_14; // @[RegisterRouter.scala:87:24] wire _out_T_150 = out_f_roready_14; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_14 = out_wivalid_14 & out_wimask_14; // @[RegisterRouter.scala:87:24] wire out_f_woready_14 = out_woready_14 & out_womask_14; // @[RegisterRouter.scala:87:24] wire _out_T_148 = out_front_bits_data[33]; // @[RegisterRouter.scala:87:24] wire _out_T_151 = ~out_rimask_14; // @[RegisterRouter.scala:87:24] wire _out_T_152 = ~out_wimask_14; // @[RegisterRouter.scala:87:24] wire _out_T_153 = ~out_romask_14; // @[RegisterRouter.scala:87:24] wire _out_T_154 = ~out_womask_14; // @[RegisterRouter.scala:87:24] wire [33:0] out_prepend_11 = {ip_rxwm, _out_prepend_T_11}; // @[RegisterRouter.scala:87:24] wire [33:0] _out_T_155 = out_prepend_11; // @[RegisterRouter.scala:87:24] wire [33:0] _out_T_156 = _out_T_155; // @[RegisterRouter.scala:87:24] wire [15:0] _out_rimask_T_15 = out_frontMask[15:0]; // @[RegisterRouter.scala:87:24] wire [15:0] _out_wimask_T_15 = out_frontMask[15:0]; // @[RegisterRouter.scala:87:24] wire out_rimask_15 = \|_out_rimask_T_15; // @[RegisterRouter.scala:87:24] wire out_wimask_15 = &_out_wimask_T_15; // @[RegisterRouter.scala:87:24] wire [15:0] _out_romask_T_15 = out_backMask[15:0]; // @[RegisterRouter.scala:87:24] wire [15:0] _out_womask_T_15 = out_backMask[15:0]; // @[RegisterRouter.scala:87:24] wire out_romask_15 = \|_out_romask_T_15; // @[RegisterRouter.scala:87:24] wire out_womask_15 = &_out_womask_T_15; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_15 = out_rivalid_15 & out_rimask_15; // @[RegisterRouter.scala:87:24] wire _out_T_158 = out_f_rivalid_15; // @[RegisterRouter.scala:87:24] wire out_f_roready_15 = out_roready_15 & out_romask_15; // @[RegisterRouter.scala:87:24] wire _out_T_159 = out_f_roready_15; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_15 = out_wivalid_15 & out_wimask_15; // @[RegisterRouter.scala:87:24] wire _out_T_160 = out_f_wivalid_15; // @[RegisterRouter.scala:87:24] wire out_f_woready_15 = out_woready_15 & out_womask_15; // @[RegisterRouter.scala:87:24] wire _out_T_161 = out_f_woready_15; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_157 = out_front_bits_data[15:0]; // @[RegisterRouter.scala:87:24] wire _out_T_162 = ~out_rimask_15; // @[RegisterRouter.scala:87:24] wire _out_T_163 = ~out_wimask_15; // @[RegisterRouter.scala:87:24] wire _out_T_164 = ~out_romask_15; // @[RegisterRouter.scala:87:24] wire _out_T_165 = ~out_womask_15; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_167 = _out_T_166; // @[RegisterRouter.scala:87:24] wire _out_iindex_T = out_front_bits_index[0]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T = out_front_bits_index[0]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_1 = out_front_bits_index[1]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_1 = out_front_bits_index[1]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_2 = out_front_bits_index[2]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_2 = out_front_bits_index[2]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_3 = out_front_bits_index[3]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_3 = out_front_bits_index[3]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_4 = out_front_bits_index[4]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_4 = out_front_bits_index[4]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_5 = out_front_bits_index[5]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_5 = out_front_bits_index[5]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_6 = out_front_bits_index[6]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_6 = out_front_bits_index[6]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_7 = out_front_bits_index[7]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_7 = out_front_bits_index[7]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_8 = out_front_bits_index[8]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_8 = out_front_bits_index[8]; // @[RegisterRouter.scala:87:24] wire [1:0] out_iindex = {_out_iindex_T_1, _out_iindex_T}; // @[RegisterRouter.scala:87:24] wire [1:0] out_oindex = {_out_oindex_T_1, _out_oindex_T}; // @[RegisterRouter.scala:87:24] wire [3:0] _out_frontSel_T = 4'h1 << out_iindex; // @[OneHot.scala:58:35] wire out_frontSel_0 = _out_frontSel_T[0]; // @[OneHot.scala:58:35] wire out_frontSel_1 = _out_frontSel_T[1]; // @[OneHot.scala:58:35] wire out_frontSel_2 = _out_frontSel_T[2]; // @[OneHot.scala:58:35] wire out_frontSel_3 = _out_frontSel_T[3]; // @[OneHot.scala:58:35] wire [3:0] _out_backSel_T = 4'h1 << out_oindex; // @[OneHot.scala:58:35] wire out_backSel_0 = _out_backSel_T[0]; // @[OneHot.scala:58:35] wire out_backSel_1 = _out_backSel_T[1]; // @[OneHot.scala:58:35] wire out_backSel_2 = _out_backSel_T[2]; // @[OneHot.scala:58:35] wire out_backSel_3 = _out_backSel_T[3]; // @[OneHot.scala:58:35] wire _GEN_2 = in_valid & out_front_ready; // @[RegisterRouter.scala:73:18, :87:24] wire _out_rifireMux_T; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T = _GEN_2; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T = _GEN_2; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1 = _out_rifireMux_T & out_front_bits_read; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_2 = _out_rifireMux_T_1 & out_frontSel_0; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_3 = _out_rifireMux_T_2 & _out_T; // @[RegisterRouter.scala:87:24] assign out_rivalid_0 = _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24] assign out_rivalid_1 = _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24] assign out_rivalid_2 = _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24] assign out_rivalid_3 = _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24] assign out_rivalid_4 = _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24] assign out_rivalid_5 = _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_4 = ~_out_T; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_6 = _out_rifireMux_T_1 & out_frontSel_1; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_7 = _out_rifireMux_T_6 & _out_T_2; // @[RegisterRouter.scala:87:24] assign out_rivalid_6 = _out_rifireMux_T_7; // @[RegisterRouter.scala:87:24] assign out_rivalid_7 = _out_rifireMux_T_7; // @[RegisterRouter.scala:87:24] assign out_rivalid_8 = _out_rifireMux_T_7; // @[RegisterRouter.scala:87:24] assign out_rivalid_9 = _out_rifireMux_T_7; // @[RegisterRouter.scala:87:24] assign out_rivalid_10 = _out_rifireMux_T_7; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_8 = ~_out_T_2; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_10 = _out_rifireMux_T_1 & out_frontSel_2; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_11 = _out_rifireMux_T_10 & _out_T_4; // @[RegisterRouter.scala:87:24] assign out_rivalid_11 = _out_rifireMux_T_11; // @[RegisterRouter.scala:87:24] assign out_rivalid_12 = _out_rifireMux_T_11; // @[RegisterRouter.scala:87:24] assign out_rivalid_13 = _out_rifireMux_T_11; // @[RegisterRouter.scala:87:24] assign out_rivalid_14 = _out_rifireMux_T_11; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_12 = ~_out_T_4; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_14 = _out_rifireMux_T_1 & out_frontSel_3; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_15 = _out_rifireMux_T_14 & _out_T_6; // @[RegisterRouter.scala:87:24] assign out_rivalid_15 = _out_rifireMux_T_15; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_16 = ~_out_T_6; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1 = ~out_front_bits_read; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_2 = _out_wifireMux_T & _out_wifireMux_T_1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_3 = _out_wifireMux_T_2 & out_frontSel_0; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_4 = _out_wifireMux_T_3 & _out_T; // @[RegisterRouter.scala:87:24] assign out_wivalid_0 = _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24] assign out_wivalid_1 = _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24] assign out_wivalid_2 = _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24] assign out_wivalid_3 = _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24] assign out_wivalid_4 = _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24] assign out_wivalid_5 = _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_5 = ~_out_T; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_7 = _out_wifireMux_T_2 & out_frontSel_1; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_8 = _out_wifireMux_T_7 & _out_T_2; // @[RegisterRouter.scala:87:24] assign out_wivalid_6 = _out_wifireMux_T_8; // @[RegisterRouter.scala:87:24] assign out_wivalid_7 = _out_wifireMux_T_8; // @[RegisterRouter.scala:87:24] assign out_wivalid_8 = _out_wifireMux_T_8; // @[RegisterRouter.scala:87:24] assign out_wivalid_9 = _out_wifireMux_T_8; // @[RegisterRouter.scala:87:24] assign out_wivalid_10 = _out_wifireMux_T_8; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_9 = ~_out_T_2; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_11 = _out_wifireMux_T_2 & out_frontSel_2; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_12 = _out_wifireMux_T_11 & _out_T_4; // @[RegisterRouter.scala:87:24] assign out_wivalid_11 = _out_wifireMux_T_12; // @[RegisterRouter.scala:87:24] assign out_wivalid_12 = _out_wifireMux_T_12; // @[RegisterRouter.scala:87:24] assign out_wivalid_13 = _out_wifireMux_T_12; // @[RegisterRouter.scala:87:24] assign out_wivalid_14 = _out_wifireMux_T_12; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_13 = ~_out_T_4; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_15 = _out_wifireMux_T_2 & out_frontSel_3; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_16 = _out_wifireMux_T_15 & _out_T_6; // @[RegisterRouter.scala:87:24] assign out_wivalid_15 = _out_wifireMux_T_16; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_17 = ~_out_T_6; // @[RegisterRouter.scala:87:24] wire _GEN_3 = out_front_valid & out_ready; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T = _GEN_3; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T = _GEN_3; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1 = _out_rofireMux_T & out_front_bits_read; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_2 = _out_rofireMux_T_1 & out_backSel_0; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_3 = _out_rofireMux_T_2 & _out_T_1; // @[RegisterRouter.scala:87:24] assign out_roready_0 = _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24] assign out_roready_1 = _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24] assign out_roready_2 = _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24] assign out_roready_3 = _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24] assign out_roready_4 = _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24] assign out_roready_5 = _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_4 = ~_out_T_1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_6 = _out_rofireMux_T_1 & out_backSel_1; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_7 = _out_rofireMux_T_6 & _out_T_3; // @[RegisterRouter.scala:87:24] assign out_roready_6 = _out_rofireMux_T_7; // @[RegisterRouter.scala:87:24] assign out_roready_7 = _out_rofireMux_T_7; // @[RegisterRouter.scala:87:24] assign out_roready_8 = _out_rofireMux_T_7; // @[RegisterRouter.scala:87:24] assign out_roready_9 = _out_rofireMux_T_7; // @[RegisterRouter.scala:87:24] assign out_roready_10 = _out_rofireMux_T_7; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_8 = ~_out_T_3; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_10 = _out_rofireMux_T_1 & out_backSel_2; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_11 = _out_rofireMux_T_10 & _out_T_5; // @[RegisterRouter.scala:87:24] assign out_roready_11 = _out_rofireMux_T_11; // @[RegisterRouter.scala:87:24] assign out_roready_12 = _out_rofireMux_T_11; // @[RegisterRouter.scala:87:24] assign out_roready_13 = _out_rofireMux_T_11; // @[RegisterRouter.scala:87:24] assign out_roready_14 = _out_rofireMux_T_11; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_12 = ~_out_T_5; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_14 = _out_rofireMux_T_1 & out_backSel_3; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_15 = _out_rofireMux_T_14 & _out_T_7; // @[RegisterRouter.scala:87:24] assign out_roready_15 = _out_rofireMux_T_15; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_16 = ~_out_T_7; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1 = ~out_front_bits_read; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_2 = _out_wofireMux_T & _out_wofireMux_T_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_3 = _out_wofireMux_T_2 & out_backSel_0; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_4 = _out_wofireMux_T_3 & _out_T_1; // @[RegisterRouter.scala:87:24] assign out_woready_0 = _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24] assign out_woready_1 = _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24] assign out_woready_2 = _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24] assign out_woready_3 = _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24] assign out_woready_4 = _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24] assign out_woready_5 = _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_5 = ~_out_T_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_7 = _out_wofireMux_T_2 & out_backSel_1; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_8 = _out_wofireMux_T_7 & _out_T_3; // @[RegisterRouter.scala:87:24] assign out_woready_6 = _out_wofireMux_T_8; // @[RegisterRouter.scala:87:24] assign out_woready_7 = _out_wofireMux_T_8; // @[RegisterRouter.scala:87:24] assign out_woready_8 = _out_wofireMux_T_8; // @[RegisterRouter.scala:87:24] assign out_woready_9 = _out_wofireMux_T_8; // @[RegisterRouter.scala:87:24] assign out_woready_10 = _out_wofireMux_T_8; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_9 = ~_out_T_3; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_11 = _out_wofireMux_T_2 & out_backSel_2; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_12 = _out_wofireMux_T_11 & _out_T_5; // @[RegisterRouter.scala:87:24] assign out_woready_11 = _out_wofireMux_T_12; // @[RegisterRouter.scala:87:24] assign out_woready_12 = _out_wofireMux_T_12; // @[RegisterRouter.scala:87:24] assign out_woready_13 = _out_wofireMux_T_12; // @[RegisterRouter.scala:87:24] assign out_woready_14 = _out_wofireMux_T_12; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_13 = ~_out_T_5; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_15 = _out_wofireMux_T_2 & out_backSel_3; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_16 = _out_wofireMux_T_15 & _out_T_7; // @[RegisterRouter.scala:87:24] assign out_woready_15 = _out_wofireMux_T_16; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_17 = ~_out_T_7; // @[RegisterRouter.scala:87:24] assign in_ready = _out_in_ready_T; // @[RegisterRouter.scala:73:18, :87:24] assign out_front_valid = _out_front_valid_T; // @[RegisterRouter.scala:87:24] assign out_front_ready = _out_front_ready_T; // @[RegisterRouter.scala:87:24] assign out_valid = _out_out_valid_T; // @[RegisterRouter.scala:87:24] wire [3:0] _GEN_4 = {{_out_out_bits_data_WIRE_3}, {_out_out_bits_data_WIRE_2}, {_out_out_bits_data_WIRE_1}, {_out_out_bits_data_WIRE_0}}; // @[MuxLiteral.scala:49:{10,48}] wire _out_out_bits_data_T_1 = _GEN_4[out_oindex]; // @[MuxLiteral.scala:49:10] wire [63:0] _out_out_bits_data_WIRE_1_1 = {12'h0, _out_T_116}; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_1_2 = {30'h0, _out_T_156}; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_1_3 = {48'h0, _out_T_167}; // @[MuxLiteral.scala:49:48] wire [3:0][63:0] _GEN_5 = {{_out_out_bits_data_WIRE_1_3}, {_out_out_bits_data_WIRE_1_2}, {_out_out_bits_data_WIRE_1_1}, {_out_out_bits_data_WIRE_1_0}}; // @[MuxLiteral.scala:49:{10,48}] wire [63:0] _out_out_bits_data_T_3 = _GEN_5[out_oindex]; // @[MuxLiteral.scala:49:10] assign _out_out_bits_data_T_4 = _out_out_bits_data_T_1 ? _out_out_bits_data_T_3 : 64'h0; // @[MuxLiteral.scala:49:10] assign out_bits_data = _out_out_bits_data_T_4; // @[RegisterRouter.scala:87:24] assign controlNodeIn_d_bits_size = controlNodeIn_d_bits_d_size; // @[Edges.scala:792:17] assign controlNodeIn_d_bits_source = controlNodeIn_d_bits_d_source; // @[Edges.scala:792:17] assign controlNodeIn_d_bits_opcode = {2'h0, _controlNodeIn_d_bits_opcode_T}; // @[RegisterRouter.scala:105:{19,25}] always @(posedge clock) begin // @[UART.scala:127:25] if (reset) begin // @[UART.scala:127:25] div <= 16'h10F4; // @[UART.scala:135:20] txen <= 1'h0; // @[UART.scala:141:21] rxen <= 1'h0; // @[UART.scala:142:21] txwm <= 4'h0; // @[UART.scala:149:21] rxwm <= 4'h0; // @[UART.scala:150:21] nstop <= 1'h0; // @[UART.scala:151:22] ie_rxwm <= 1'h0; // @[UART.scala:186:19] ie_txwm <= 1'h0; // @[UART.scala:186:19] end else begin // @[UART.scala:127:25] if (out_f_woready_15) // @[RegisterRouter.scala:87:24] div <= _out_T_157; // @[RegisterRouter.scala:87:24] if (out_f_woready_6) // @[RegisterRouter.scala:87:24] txen <= _out_T_62; // @[RegisterRouter.scala:87:24] if (out_f_woready_9) // @[RegisterRouter.scala:87:24] rxen <= _out_T_95; // @[RegisterRouter.scala:87:24] if (out_f_woready_8) // @[RegisterRouter.scala:87:24] txwm <= _out_T_84; // @[RegisterRouter.scala:87:24] if (out_f_woready_10) // @[RegisterRouter.scala:87:24] rxwm <= _out_T_106; // @[RegisterRouter.scala:87:24] if (out_f_woready_7) // @[RegisterRouter.scala:87:24] nstop <= _out_T_73; // @[RegisterRouter.scala:87:24] if (out_f_woready_12) // @[RegisterRouter.scala:87:24] ie_rxwm <= _out_T_128; // @[RegisterRouter.scala:87:24] if (out_f_woready_11) // @[RegisterRouter.scala:87:24] ie_txwm <= _out_T_117; // @[RegisterRouter.scala:87:24] end always @(posedge) IntSyncCrossingSource_n1x1_5 intsource ( // @[Crossing.scala:29:31] .clock (clock), .reset (reset), .auto_in_0 (intnodeOut_0), // @[MixedNode.scala:542:17] .auto_out_sync_0 (intXingIn_sync_0) ); // @[Crossing.scala:29:31] TLMonitor_108 monitor ( // @[Nodes.scala:27:25] .clock (clock), .reset (reset), .io_in_a_ready (controlNodeIn_a_ready), // @[MixedNode.scala:551:17] .io_in_a_valid (controlNodeIn_a_valid), // @[MixedNode.scala:551:17] .io_in_a_bits_opcode (controlNodeIn_a_bits_opcode), // @[MixedNode.scala:551:17] .io_in_a_bits_param (controlNodeIn_a_bits_param), // @[MixedNode.scala:551:17] .io_in_a_bits_size (controlNodeIn_a_bits_size), // @[MixedNode.scala:551:17] .io_in_a_bits_source (controlNodeIn_a_bits_source), // @[MixedNode.scala:551:17] .io_in_a_bits_address (controlNodeIn_a_bits_address), // @[MixedNode.scala:551:17] .io_in_a_bits_mask (controlNodeIn_a_bits_mask), // @[MixedNode.scala:551:17] .io_in_a_bits_data (controlNodeIn_a_bits_data), // @[MixedNode.scala:551:17] .io_in_a_bits_corrupt (controlNodeIn_a_bits_corrupt), // @[MixedNode.scala:551:17] .io_in_d_ready (controlNodeIn_d_ready), // @[MixedNode.scala:551:17] .io_in_d_valid (controlNodeIn_d_valid), // @[MixedNode.scala:551:17] .io_in_d_bits_opcode (controlNodeIn_d_bits_opcode), // @[MixedNode.scala:551:17] .io_in_d_bits_size (controlNodeIn_d_bits_size), // @[MixedNode.scala:551:17] .io_in_d_bits_source (controlNodeIn_d_bits_source), // @[MixedNode.scala:551:17] .io_in_d_bits_data (controlNodeIn_d_bits_data) // @[MixedNode.scala:551:17] ); // @[Nodes.scala:27:25] UARTTx txm ( // @[UART.scala:129:19] .clock (clock), .reset (reset), .io_en (txen), // @[UART.scala:141:21] .io_in_ready (_txm_io_in_ready), .io_in_valid (_txq_io_deq_valid), // @[UART.scala:130:19] .io_in_bits (_txq_io_deq_bits), // @[UART.scala:130:19] .io_out (ioNodeOut_txd), .io_div (div), // @[UART.scala:135:20] .io_nstop (nstop), // @[UART.scala:151:22] .io_tx_busy (_txm_io_tx_busy) ); // @[UART.scala:129:19] Queue8_UInt8 txq ( // @[UART.scala:130:19] .clock (clock), .reset (reset), .io_enq_ready (_txq_io_enq_ready), .io_enq_valid (_out_txq_io_enq_valid_T_1), // @[RegMapFIFO.scala:18:30] .io_enq_bits (_out_T_8), // @[RegisterRouter.scala:87:24] .io_deq_ready (_txm_io_in_ready), // @[UART.scala:129:19] .io_deq_valid (_txq_io_deq_valid), .io_deq_bits (_txq_io_deq_bits), .io_count (_txq_io_count) ); // @[UART.scala:130:19] UARTRx rxm ( // @[UART.scala:132:19] .clock (clock), .reset (reset), .io_en (rxen), // @[UART.scala:142:21] .io_in (ioNodeOut_rxd), // @[MixedNode.scala:542:17] .io_out_valid (_rxm_io_out_valid), .io_out_bits (_rxm_io_out_bits), .io_div (div) // @[UART.scala:135:20] ); // @[UART.scala:132:19] Queue8_UInt8_1 rxq ( // @[UART.scala:133:19] .clock (clock), .reset (reset), .io_enq_valid (_rxm_io_out_valid), // @[UART.scala:132:19] .io_enq_bits (_rxm_io_out_bits), // @[UART.scala:132:19] .io_deq_ready (out_f_roready_3), // @[RegisterRouter.scala:87:24] .io_deq_valid (_rxq_io_deq_valid), .io_deq_bits (_rxq_io_deq_bits), .io_count (_rxq_io_count) ); // @[UART.scala:133:19] assign auto_int_xing_out_sync_0 = auto_int_xing_out_sync_0_0; // @[UART.scala:127:25] assign auto_control_xing_in_a_ready = auto_control_xing_in_a_ready_0; // @[UART.scala:127:25] assign auto_control_xing_in_d_valid = auto_control_xing_in_d_valid_0; // @[UART.scala:127:25] assign auto_control_xing_in_d_bits_opcode = auto_control_xing_in_d_bits_opcode_0; // @[UART.scala:127:25] assign auto_control_xing_in_d_bits_size = auto_control_xing_in_d_bits_size_0; // @[UART.scala:127:25] assign auto_control_xing_in_d_bits_source = auto_control_xing_in_d_bits_source_0; // @[UART.scala:127:25] assign auto_control_xing_in_d_bits_data = auto_control_xing_in_d_bits_data_0; // @[UART.scala:127:25] assign auto_io_out_txd = auto_io_out_txd_0; // @[UART.scala:127:25] endmodule
Generate the Verilog code corresponding to the following Chisel files. File ShiftReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ // Similar to the Chisel ShiftRegister but allows the user to suggest a // name to the registers that get instantiated, and // to provide a reset value. object ShiftRegInit { def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T = (0 until n).foldRight(in) { case (i, next) => { val r = RegNext(next, init) name.foreach { na => r.suggestName(s"${na}_${i}") } r } } } /** These wrap behavioral * shift registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * The different types vary in their reset behavior: * AsyncResetShiftReg -- Asynchronously reset register array * A W(width) x D(depth) sized array is constructed from D instantiations of a * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg, * but only used for timing applications / abstract class AbstractPipelineReg(w: Int = 1) extends Module { val io = IO(new Bundle { val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) } ) } object AbstractPipelineReg { def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = { val chain = Module(gen) name.foreach{ chain.suggestName(_) } chain.io.d := in.asUInt chain.io.q.asTypeOf(in) } } class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) { require(depth > 0, "Depth must be greater than 0.") override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}" val chain = List.tabulate(depth) { i => Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}") } chain.last.io.d := io.d chain.last.io.en := true.B (chain.init zip chain.tail).foreach { case (sink, source) => sink.io.d := source.io.q sink.io.en := true.B } io.q := chain.head.io.q } object AsyncResetShiftReg { def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name) def apply [T <: Data](in: T, depth: Int, name: Option[String]): T = apply(in, depth, 0, name) def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T = apply(in, depth, init.litValue.toInt, name) def apply [T <: Data](in: T, depth: Int, init: T): T = apply (in, depth, init.litValue.toInt, None) } File AsyncQueue.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ case class AsyncQueueParams( depth: Int = 8, sync: Int = 3, safe: Boolean = true, // If safe is true, then effort is made to resynchronize the crossing indices when either side is reset. // This makes it safe/possible to reset one side of the crossing (but not the other) when the queue is empty. narrow: Boolean = false) // If narrow is true then the read mux is moved to the source side of the crossing. // This reduces the number of level shifters in the case where the clock crossing is also a voltage crossing, // at the expense of a combinational path from the sink to the source and back to the sink. { require (depth > 0 && isPow2(depth)) require (sync >= 2) val bits = log2Ceil(depth) val wires = if (narrow) 1 else depth } object AsyncQueueParams { // When there is only one entry, we don't need narrow. def singleton(sync: Int = 3, safe: Boolean = true) = AsyncQueueParams(1, sync, safe, false) } class AsyncBundleSafety extends Bundle { val ridx_valid = Input (Bool()) val widx_valid = Output(Bool()) val source_reset_n = Output(Bool()) val sink_reset_n = Input (Bool()) } class AsyncBundle[T <: Data](private val gen: T, val params: AsyncQueueParams = AsyncQueueParams()) extends Bundle { // Data-path synchronization val mem = Output(Vec(params.wires, gen)) val ridx = Input (UInt((params.bits+1).W)) val widx = Output(UInt((params.bits+1).W)) val index = params.narrow.option(Input(UInt(params.bits.W))) // Signals used to self-stabilize a safe AsyncQueue val safe = params.safe.option(new AsyncBundleSafety) } object GrayCounter { def apply(bits: Int, increment: Bool = true.B, clear: Bool = false.B, name: String = "binary"): UInt = { val incremented = Wire(UInt(bits.W)) val binary = RegNext(next=incremented, init=0.U).suggestName(name) incremented := Mux(clear, 0.U, binary + increment.asUInt) incremented ^ (incremented >> 1) } } class AsyncValidSync(sync: Int, desc: String) extends RawModule { val io = IO(new Bundle { val in = Input(Bool()) val out = Output(Bool()) }) val clock = IO(Input(Clock())) val reset = IO(Input(AsyncReset())) withClockAndReset(clock, reset){ io.out := AsyncResetSynchronizerShiftReg(io.in, sync, Some(desc)) } } class AsyncQueueSource[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module { override def desiredName = s"AsyncQueueSource_${gen.typeName}" val io = IO(new Bundle { // These come from the source domain val enq = Flipped(Decoupled(gen)) // These cross to the sink clock domain val async = new AsyncBundle(gen, params) }) val bits = params.bits val sink_ready = WireInit(true.B) val mem = Reg(Vec(params.depth, gen)) // This does NOT need to be reset at all. val widx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.enq.fire, !sink_ready, "widx_bin")) val ridx = AsyncResetSynchronizerShiftReg(io.async.ridx, params.sync, Some("ridx_gray")) val ready = sink_ready && widx =/= (ridx ^ (params.depth \| params.depth >> 1).U) val index = if (bits == 0) 0.U else io.async.widx(bits-1, 0) ^ (io.async.widx(bits, bits) << (bits-1)) when (io.enq.fire) { mem(index) := io.enq.bits } val ready_reg = withReset(reset.asAsyncReset)(RegNext(next=ready, init=false.B).suggestName("ready_reg")) io.enq.ready := ready_reg && sink_ready val widx_reg = withReset(reset.asAsyncReset)(RegNext(next=widx, init=0.U).suggestName("widx_gray")) io.async.widx := widx_reg io.async.index match { case Some(index) => io.async.mem(0) := mem(index) case None => io.async.mem := mem } io.async.safe.foreach { sio => val source_valid_0 = Module(new AsyncValidSync(params.sync, "source_valid_0")) val source_valid_1 = Module(new AsyncValidSync(params.sync, "source_valid_1")) val sink_extend = Module(new AsyncValidSync(params.sync, "sink_extend")) val sink_valid = Module(new AsyncValidSync(params.sync, "sink_valid")) source_valid_0.reset := (reset.asBool \|\| !sio.sink_reset_n).asAsyncReset source_valid_1.reset := (reset.asBool \|\| !sio.sink_reset_n).asAsyncReset sink_extend .reset := (reset.asBool \|\| !sio.sink_reset_n).asAsyncReset sink_valid .reset := reset.asAsyncReset source_valid_0.clock := clock source_valid_1.clock := clock sink_extend .clock := clock sink_valid .clock := clock source_valid_0.io.in := true.B source_valid_1.io.in := source_valid_0.io.out sio.widx_valid := source_valid_1.io.out sink_extend.io.in := sio.ridx_valid sink_valid.io.in := sink_extend.io.out sink_ready := sink_valid.io.out sio.source_reset_n := !reset.asBool // Assert that if there is stuff in the queue, then reset cannot happen // Impossible to write because dequeue can occur on the receiving side, // then reset allowed to happen, but write side cannot know that dequeue // occurred. // TODO: write some sort of sanity check assertion for users // that denote don't reset when there is activity // assert (!(reset \|\| !sio.sink_reset_n) \|\| !io.enq.valid, "Enqueue while sink is reset and AsyncQueueSource is unprotected") // assert (!reset_rise \|\| prev_idx_match.asBool, "Sink reset while AsyncQueueSource not empty") } } class AsyncQueueSink[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module { override def desiredName = s"AsyncQueueSink_${gen.typeName}" val io = IO(new Bundle { // These come from the sink domain val deq = Decoupled(gen) // These cross to the source clock domain val async = Flipped(new AsyncBundle(gen, params)) }) val bits = params.bits val source_ready = WireInit(true.B) val ridx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.deq.fire, !source_ready, "ridx_bin")) val widx = AsyncResetSynchronizerShiftReg(io.async.widx, params.sync, Some("widx_gray")) val valid = source_ready && ridx =/= widx // The mux is safe because timing analysis ensures ridx has reached the register // On an ASIC, changes to the unread location cannot affect the selected value // On an FPGA, only one input changes at a time => mem updates don't cause glitches // The register only latches when the selected valued is not being written val index = if (bits == 0) 0.U else ridx(bits-1, 0) ^ (ridx(bits, bits) << (bits-1)) io.async.index.foreach { _ := index } // This register does not NEED to be reset, as its contents will not // be considered unless the asynchronously reset deq valid register is set. // It is possible that bits latches when the source domain is reset / has power cut // This is safe, because isolation gates brought mem low before the zeroed widx reached us val deq_bits_nxt = io.async.mem(if (params.narrow) 0.U else index) io.deq.bits := ClockCrossingReg(deq_bits_nxt, en = valid, doInit = false, name = Some("deq_bits_reg")) val valid_reg = withReset(reset.asAsyncReset)(RegNext(next=valid, init=false.B).suggestName("valid_reg")) io.deq.valid := valid_reg && source_ready val ridx_reg = withReset(reset.asAsyncReset)(RegNext(next=ridx, init=0.U).suggestName("ridx_gray")) io.async.ridx := ridx_reg io.async.safe.foreach { sio => val sink_valid_0 = Module(new AsyncValidSync(params.sync, "sink_valid_0")) val sink_valid_1 = Module(new AsyncValidSync(params.sync, "sink_valid_1")) val source_extend = Module(new AsyncValidSync(params.sync, "source_extend")) val source_valid = Module(new AsyncValidSync(params.sync, "source_valid")) sink_valid_0 .reset := (reset.asBool \|\| !sio.source_reset_n).asAsyncReset sink_valid_1 .reset := (reset.asBool \|\| !sio.source_reset_n).asAsyncReset source_extend.reset := (reset.asBool \|\| !sio.source_reset_n).asAsyncReset source_valid .reset := reset.asAsyncReset sink_valid_0 .clock := clock sink_valid_1 .clock := clock source_extend.clock := clock source_valid .clock := clock sink_valid_0.io.in := true.B sink_valid_1.io.in := sink_valid_0.io.out sio.ridx_valid := sink_valid_1.io.out source_extend.io.in := sio.widx_valid source_valid.io.in := source_extend.io.out source_ready := source_valid.io.out sio.sink_reset_n := !reset.asBool // TODO: write some sort of sanity check assertion for users // that denote don't reset when there is activity // // val reset_and_extend = !source_ready \|\| !sio.source_reset_n \|\| reset.asBool // val reset_and_extend_prev = RegNext(reset_and_extend, true.B) // val reset_rise = !reset_and_extend_prev && reset_and_extend // val prev_idx_match = AsyncResetReg(updateData=(io.async.widx===io.async.ridx), resetData=0) // assert (!reset_rise \|\| prev_idx_match.asBool, "Source reset while AsyncQueueSink not empty") } } object FromAsyncBundle { // Sometimes it makes sense for the sink to have different sync than the source def apply[T <: Data](x: AsyncBundle[T]): DecoupledIO[T] = apply(x, x.params.sync) def apply[T <: Data](x: AsyncBundle[T], sync: Int): DecoupledIO[T] = { val sink = Module(new AsyncQueueSink(chiselTypeOf(x.mem(0)), x.params.copy(sync = sync))) sink.io.async <> x sink.io.deq } } object ToAsyncBundle { def apply[T <: Data](x: ReadyValidIO[T], params: AsyncQueueParams = AsyncQueueParams()): AsyncBundle[T] = { val source = Module(new AsyncQueueSource(chiselTypeOf(x.bits), params)) source.io.enq <> x source.io.async } } class AsyncQueue[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Crossing[T] { val io = IO(new CrossingIO(gen)) val source = withClockAndReset(io.enq_clock, io.enq_reset) { Module(new AsyncQueueSource(gen, params)) } val sink = withClockAndReset(io.deq_clock, io.deq_reset) { Module(new AsyncQueueSink (gen, params)) } source.io.enq <> io.enq io.deq <> sink.io.deq sink.io.async <> source.io.async } File LazyModuleImp.scala: package org.chipsalliance.diplomacy.lazymodule import chisel3.{withClockAndReset, Module, RawModule, Reset, _} import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo} import firrtl.passes.InlineAnnotation import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.nodes.Dangle import scala.collection.immutable.SortedMap /* Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]]. * * This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy. / sealed trait LazyModuleImpLike extends RawModule { /* [[LazyModule]] that contains this instance. / val wrapper: LazyModule /* IOs that will be automatically "punched" for this instance. / val auto: AutoBundle /* The metadata that describes the [[HalfEdge]]s which generated [[auto]]. / protected[diplomacy] val dangles: Seq[Dangle] // [[wrapper.module]] had better not be accessed while LazyModules are still being built! require( LazyModule.scope.isEmpty, s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}" ) /* Set module name. Defaults to the containing LazyModule's desiredName. / override def desiredName: String = wrapper.desiredName suggestName(wrapper.suggestedName) /* [[Parameters]] for chisel [[Module]]s. / implicit val p: Parameters = wrapper.p /* instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and * submodules. / protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = { // 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]], // 2. return [[Dangle]]s from each module. val childDangles = wrapper.children.reverse.flatMap { c => implicit val sourceInfo: SourceInfo = c.info c.cloneProto.map { cp => // If the child is a clone, then recursively set cloneProto of its children as well def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = { require(bases.size == clones.size) (bases.zip(clones)).map { case (l, r) => require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}") l.cloneProto = Some(r) assignCloneProtos(l.children, r.children) } } assignCloneProtos(c.children, cp.children) // Clone the child module as a record, and get its [[AutoBundle]] val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName) val clonedAuto = clone("auto").asInstanceOf[AutoBundle] // Get the empty [[Dangle]]'s of the cloned child val rawDangles = c.cloneDangles() require(rawDangles.size == clonedAuto.elements.size) // Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) } dangles }.getOrElse { // For non-clones, instantiate the child module val mod = try { Module(c.module) } catch { case e: ChiselException => { println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}") throw e } } mod.dangles } } // Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]]. // This will result in a sequence of [[Dangle]] from these [[BaseNode]]s. val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate()) // Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]] val allDangles = nodeDangles ++ childDangles // Group [[allDangles]] by their [[source]]. val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _) // For each [[source]] set of [[Dangle]]s of size 2, ensure that these // can be connected as a source-sink pair (have opposite flipped value). // Make the connection and mark them as [[done]]. val done = Set() ++ pairing.values.filter(_.size == 2).map { case Seq(a, b) => require(a.flipped != b.flipped) // @todo <> in chisel3 makes directionless connection. if (a.flipped) { a.data <> b.data } else { b.data <> a.data } a.source case _ => None } // Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module. val forward = allDangles.filter(d => !done(d.source)) // Generate [[AutoBundle]] IO from [[forward]]. val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _)) // Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]] val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) => if (d.flipped) { d.data <> io } else { io <> d.data } d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name) } // Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]]. wrapper.inModuleBody.reverse.foreach { _() } if (wrapper.shouldBeInlined) { chisel3.experimental.annotate(new ChiselAnnotation { def toFirrtl = InlineAnnotation(toNamed) }) } // Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]]. (auto, dangles) } } /* Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. / class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike { /* Instantiate hardware of this `Module`. / val (auto, dangles) = instantiate() } /* Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. / class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike { // These wires are the default clock+reset for all LazyModule children. // It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the // [[LazyRawModuleImp]] children. // Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly. /* drive clock explicitly. / val childClock: Clock = Wire(Clock()) /* drive reset explicitly. / val childReset: Reset = Wire(Reset()) // the default is that these are disabled childClock := false.B.asClock childReset := chisel3.DontCare def provideImplicitClockToLazyChildren: Boolean = false val (auto, dangles) = if (provideImplicitClockToLazyChildren) { withClockAndReset(childClock, childReset) { instantiate() } } else { instantiate() } } File Debug.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.devices.debug import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.amba.apb.{APBFanout, APBToTL} import freechips.rocketchip.devices.debug.systembusaccess.{SBToTL, SystemBusAccessModule} import freechips.rocketchip.devices.tilelink.{DevNullParams, TLBusBypass, TLError} import freechips.rocketchip.diplomacy.{AddressSet, BufferParams} import freechips.rocketchip.resources.{Description, Device, Resource, ResourceBindings, ResourceString, SimpleDevice} import freechips.rocketchip.interrupts.{IntNexusNode, IntSinkParameters, IntSinkPortParameters, IntSourceParameters, IntSourcePortParameters, IntSyncCrossingSource, IntSyncIdentityNode} import freechips.rocketchip.regmapper.{RegField, RegFieldAccessType, RegFieldDesc, RegFieldGroup, RegFieldWrType, RegReadFn, RegWriteFn} import freechips.rocketchip.rocket.{CSRs, Instructions} import freechips.rocketchip.tile.MaxHartIdBits import freechips.rocketchip.tilelink.{TLAsyncCrossingSink, TLAsyncCrossingSource, TLBuffer, TLRegisterNode, TLXbar} import freechips.rocketchip.util.{Annotated, AsyncBundle, AsyncQueueParams, AsyncResetSynchronizerShiftReg, FromAsyncBundle, ParameterizedBundle, ResetSynchronizerShiftReg, ToAsyncBundle} import freechips.rocketchip.util.SeqBoolBitwiseOps import freechips.rocketchip.util.SeqToAugmentedSeq import freechips.rocketchip.util.BooleanToAugmentedBoolean object DsbBusConsts { def sbAddrWidth = 12 def sbIdWidth = 10 } object DsbRegAddrs{ // These are used by the ROM. def HALTED = 0x100 def GOING = 0x104 def RESUMING = 0x108 def EXCEPTION = 0x10C def WHERETO = 0x300 // This needs to be aligned for up to lq/sq // This shows up in HartInfo, and needs to be aligned // to enable up to LQ/SQ instructions. def DATA = 0x380 // We want DATA to immediately follow PROGBUF so that we can // use them interchangeably. Leave another slot if there is an // implicit ebreak. def PROGBUF(cfg:DebugModuleParams) = { val tmp = DATA - (cfg.nProgramBufferWords 4) if (cfg.hasImplicitEbreak) (tmp - 4) else tmp } // This is unused if hasImpEbreak is false, and just points to the end of the PROGBUF. def IMPEBREAK(cfg: DebugModuleParams) = { DATA - 4 } // We want abstract to be immediately before PROGBUF // because we auto-generate 2 (or 5) instructions. def ABSTRACT(cfg:DebugModuleParams) = PROGBUF(cfg) - (cfg.nAbstractInstructions * 4) def FLAGS = 0x400 def ROMBASE = 0x800 } /** Enumerations used both in the hardware * and in the configuration specification. / object DebugModuleAccessType extends scala.Enumeration { type DebugModuleAccessType = Value val Access8Bit, Access16Bit, Access32Bit, Access64Bit, Access128Bit = Value } object DebugAbstractCommandError extends scala.Enumeration { type DebugAbstractCommandError = Value val Success, ErrBusy, ErrNotSupported, ErrException, ErrHaltResume = Value } object DebugAbstractCommandType extends scala.Enumeration { type DebugAbstractCommandType = Value val AccessRegister, QuickAccess = Value } /* Parameters exposed to the top-level design, set based on * external requirements, etc. * * This object checks that the parameters conform to the * full specification. The implementation which receives this * object can perform more checks on what that implementation * actually supports. * @param nComponents Number of components to support debugging. * @param baseAddress Base offest for debugEntry and debugException * @param nDMIAddrSize Size of the Debug Bus Address * @param nAbstractDataWords Number of 32-bit words for Abstract Commands * @param nProgamBufferWords Number of 32-bit words for Program Buffer * @param hasBusMaster Whether or not a bus master should be included * @param clockGate Whether or not to use dmactive as the clockgate for debug module * @param maxSupportedSBAccess Maximum transaction size supported by System Bus Access logic. * @param supportQuickAccess Whether or not to support the quick access command. * @param supportHartArray Whether or not to implement the hart array register (if >1 hart). * @param nHaltGroups Number of halt groups * @param nExtTriggers Number of external triggers * @param hasHartResets Feature to reset all the currently selected harts * @param hasImplicitEbreak There is an additional RO program buffer word containing an ebreak * @param crossingHasSafeReset Include "safe" logic in Async Crossings so that only one side needs to be reset. / case class DebugModuleParams ( baseAddress : BigInt = BigInt(0), nDMIAddrSize : Int = 7, nProgramBufferWords: Int = 16, nAbstractDataWords : Int = 4, nScratch : Int = 1, hasBusMaster : Boolean = false, clockGate : Boolean = true, maxSupportedSBAccess : Int = 32, supportQuickAccess : Boolean = false, supportHartArray : Boolean = true, nHaltGroups : Int = 1, nExtTriggers : Int = 0, hasHartResets : Boolean = false, hasImplicitEbreak : Boolean = false, hasAuthentication : Boolean = false, crossingHasSafeReset : Boolean = true ) { require ((nDMIAddrSize >= 7) && (nDMIAddrSize <= 32), s"Legal DMIAddrSize is 7-32, not ${nDMIAddrSize}") require ((nAbstractDataWords > 0) && (nAbstractDataWords <= 16), s"Legal nAbstractDataWords is 0-16, not ${nAbstractDataWords}") require ((nProgramBufferWords >= 0) && (nProgramBufferWords <= 16), s"Legal nProgramBufferWords is 0-16, not ${nProgramBufferWords}") require (nHaltGroups < 32, s"Legal nHaltGroups is 0-31, not ${nHaltGroups}") require (nExtTriggers <= 16, s"Legal nExtTriggers is 0-16, not ${nExtTriggers}") if (supportQuickAccess) { // TODO: Check that quick access requirements are met. } def address = AddressSet(baseAddress, 0xFFF) /* the base address of DM / def atzero = (baseAddress == 0) /* The number of generated instructions * * When the base address is not zero, we need more instruction also, * more dscratch registers) to load/store memory mapped data register * because they may no longer be directly addressible with x0 + 12-bit imm / def nAbstractInstructions = if (atzero) 2 else 5 def debugEntry: BigInt = baseAddress + 0x800 def debugException: BigInt = baseAddress + 0x808 def nDscratch: Int = if (atzero) 1 else 2 } object DefaultDebugModuleParams { def apply(xlen:Int /TODO , val configStringAddr: Int/): DebugModuleParams = { new DebugModuleParams().copy( nAbstractDataWords = (if (xlen == 32) 1 else if (xlen == 64) 2 else 4), maxSupportedSBAccess = xlen ) } } case object DebugModuleKey extends Field[Option[DebugModuleParams]](Some(DebugModuleParams())) /* Functional parameters exposed to the design configuration. * * hartIdToHartSel: For systems where hart ids are not 1:1 with hartsel, provide the mapping. * hartSelToHartId: Provide inverse mapping of the above / case class DebugModuleHartSelFuncs ( hartIdToHartSel : (UInt) => UInt = (x:UInt) => x, hartSelToHartId : (UInt) => UInt = (x:UInt) => x ) case object DebugModuleHartSelKey extends Field(DebugModuleHartSelFuncs()) class DebugExtTriggerOut (val nExtTriggers: Int) extends Bundle { val req = Output(UInt(nExtTriggers.W)) val ack = Input(UInt(nExtTriggers.W)) } class DebugExtTriggerIn (val nExtTriggers: Int) extends Bundle { val req = Input(UInt(nExtTriggers.W)) val ack = Output(UInt(nExtTriggers.W)) } class DebugExtTriggerIO () (implicit val p: Parameters) extends ParameterizedBundle()(p) { val out = new DebugExtTriggerOut(p(DebugModuleKey).get.nExtTriggers) val in = new DebugExtTriggerIn (p(DebugModuleKey).get.nExtTriggers) } class DebugAuthenticationIO () (implicit val p: Parameters) extends ParameterizedBundle()(p) { val dmactive = Output(Bool()) val dmAuthWrite = Output(Bool()) val dmAuthRead = Output(Bool()) val dmAuthWdata = Output(UInt(32.W)) val dmAuthBusy = Input(Bool()) val dmAuthRdata = Input(UInt(32.W)) val dmAuthenticated = Input(Bool()) } // ************************************** // Module Interfaces // // ************************************* / Control signals for Inner, generated in Outer * {{{ * run control: resumreq, ackhavereset, halt-on-reset mask * hart select: hasel, hartsel and the hart array mask * }}} / class DebugInternalBundle (val nComponents: Int)(implicit val p: Parameters) extends ParameterizedBundle()(p) { /* resume request / val resumereq = Bool() /* hart select / val hartsel = UInt(10.W) /* reset acknowledge / val ackhavereset = Bool() /* hart array enable / val hasel = Bool() /* hart array mask / val hamask = Vec(nComponents, Bool()) /* halt-on-reset mask / val hrmask = Vec(nComponents, Bool()) } /* structure for top-level Debug Module signals which aren't the bus interfaces. / class DebugCtrlBundle (nComponents: Int)(implicit val p: Parameters) extends ParameterizedBundle()(p) { /* debug availability status for all harts / val debugUnavail = Input(Vec(nComponents, Bool())) /* reset signal * * for every part of the hardware platform, * including every hart, except for the DM and any * logic required to access the DM / val ndreset = Output(Bool()) /* reset signal for the DM itself / val dmactive = Output(Bool()) /* dmactive acknowlege / val dmactiveAck = Input(Bool()) } // ************************************** // Debug Module // // ************************************* / Parameterized version of the Debug Module defined in the * RISC-V Debug Specification * * DebugModule is a slave to two asynchronous masters: * The Debug Bus (DMI) -- This is driven by an external debugger * * The System Bus -- This services requests from the cores. Generally * this interface should only be active at the request * of the debugger, but the Debug Module may also * provide the default MTVEC since it is mapped * to address 0x0. * * DebugModule is responsible for control registers and RAM, and * Debug ROM. It runs partially off of the dmiClk (e.g. TCK) and * the TL clock. Therefore, it is divided into "Outer" portion (running * off dmiClock and dmiReset) and "Inner" (running off tl_clock and tl_reset). * This allows DMCONTROL.haltreq, hartsel, hasel, hawindowsel, hawindow, dmactive, * and ndreset to be modified even while the Core is in reset or not being clocked. * Not all reads from the Debugger to the Debug Module will actually complete * in these scenarios either, they will just block until tl_clock and tl_reset * allow them to complete. This is not strictly necessary for * proper debugger functionality. / // Local reg mapper function : Notify when written, but give the value as well. object WNotifyWire { def apply(n: Int, value: UInt, set: Bool, name: String, desc: String) : RegField = { RegField(n, 0.U, RegWriteFn((valid, data) => { set := valid value := data true.B }), Some(RegFieldDesc(name = name, desc = desc, access = RegFieldAccessType.W))) } } // Local reg mapper function : Notify when accessed either as read or write. object RWNotify { def apply (n: Int, rVal: UInt, wVal: UInt, rNotify: Bool, wNotify: Bool, desc: Option[RegFieldDesc] = None): RegField = { RegField(n, RegReadFn ((ready) => {rNotify := ready ; (true.B, rVal)}), RegWriteFn((valid, data) => { wNotify := valid when (valid) {wVal := data} true.B } ), desc) } } // Local reg mapper function : Notify with value when written, take read input as presented. // This allows checking or correcting the write value before storing it in the register field. object WNotifyVal { def apply(n: Int, rVal: UInt, wVal: UInt, wNotify: Bool, desc: RegFieldDesc): RegField = { RegField(n, rVal, RegWriteFn((valid, data) => { wNotify := valid wVal := data true.B } ), desc) } } class TLDebugModuleOuter(device: Device)(implicit p: Parameters) extends LazyModule { // For Shorter Register Names import DMI_RegAddrs._ val cfg = p(DebugModuleKey).get val intnode = IntNexusNode( sourceFn = { _ => IntSourcePortParameters(Seq(IntSourceParameters(1, Seq(Resource(device, "int"))))) }, sinkFn = { _ => IntSinkPortParameters(Seq(IntSinkParameters())) }, outputRequiresInput = false) val dmiNode = TLRegisterNode ( address = AddressSet.misaligned(DMI_DMCONTROL << 2, 4) ++ AddressSet.misaligned(DMI_HARTINFO << 2, 4) ++ AddressSet.misaligned(DMI_HAWINDOWSEL << 2, 4) ++ AddressSet.misaligned(DMI_HAWINDOW << 2, 4), device = device, beatBytes = 4, executable = false ) lazy val module = new Impl class Impl extends LazyModuleImp(this) { require (intnode.edges.in.size == 0, "Debug Module does not accept interrupts") val nComponents = intnode.out.size def getNComponents = () => nComponents val supportHartArray = cfg.supportHartArray && (nComponents > 1) // no hart array if only one hart val io = IO(new Bundle { /* structure for top-level Debug Module signals which aren't the bus interfaces. / val ctrl = (new DebugCtrlBundle(nComponents)) /* control signals for Inner, generated in Outer / val innerCtrl = new DecoupledIO(new DebugInternalBundle(nComponents)) /* debug interruption from Inner to Outer * * contains 2 type of debug interruption causes: * - halt group * - halt-on-reset / val hgDebugInt = Input(Vec(nComponents, Bool())) /* hart reset request to core / val hartResetReq = cfg.hasHartResets.option(Output(Vec(nComponents, Bool()))) /* authentication support / val dmAuthenticated = cfg.hasAuthentication.option(Input(Bool())) }) val omRegMap = withReset(reset.asAsyncReset) { // FIXME: Instead of casting reset to ensure it is Async, assert/require reset.Type == AsyncReset (when this feature is available) val dmAuthenticated = io.dmAuthenticated.map( dma => ResetSynchronizerShiftReg(in=dma, sync=3, name=Some("dmAuthenticated_sync"))).getOrElse(true.B) //----DMCONTROL (The whole point of 'Outer' is to maintain this register on dmiClock (e.g. TCK) domain, so that it // can be written even if 'Inner' is not being clocked or is in reset. This allows halting // harts while the rest of the system is in reset. It doesn't really allow any other // register accesses, which will keep returning 'busy' to the debugger interface. val DMCONTROLReset = WireInit(0.U.asTypeOf(new DMCONTROLFields())) val DMCONTROLNxt = WireInit(0.U.asTypeOf(new DMCONTROLFields())) val DMCONTROLReg = RegNext(next=DMCONTROLNxt, init=0.U.asTypeOf(DMCONTROLNxt)).suggestName("DMCONTROLReg") val hartsel_mask = if (nComponents > 1) ((1 << p(MaxHartIdBits)) - 1).U else 0.U val DMCONTROLWrData = WireInit(0.U.asTypeOf(new DMCONTROLFields())) val dmactiveWrEn = WireInit(false.B) val ndmresetWrEn = WireInit(false.B) val clrresethaltreqWrEn = WireInit(false.B) val setresethaltreqWrEn = WireInit(false.B) val hartselloWrEn = WireInit(false.B) val haselWrEn = WireInit(false.B) val ackhaveresetWrEn = WireInit(false.B) val hartresetWrEn = WireInit(false.B) val resumereqWrEn = WireInit(false.B) val haltreqWrEn = WireInit(false.B) val dmactive = DMCONTROLReg.dmactive DMCONTROLNxt := DMCONTROLReg when (~dmactive) { DMCONTROLNxt := DMCONTROLReset } .otherwise { when (dmAuthenticated && ndmresetWrEn) { DMCONTROLNxt.ndmreset := DMCONTROLWrData.ndmreset } when (dmAuthenticated && hartselloWrEn) { DMCONTROLNxt.hartsello := DMCONTROLWrData.hartsello & hartsel_mask} when (dmAuthenticated && haselWrEn) { DMCONTROLNxt.hasel := DMCONTROLWrData.hasel } when (dmAuthenticated && hartresetWrEn) { DMCONTROLNxt.hartreset := DMCONTROLWrData.hartreset } when (dmAuthenticated && haltreqWrEn) { DMCONTROLNxt.haltreq := DMCONTROLWrData.haltreq } } // Put this last to override its own effects. when (dmactiveWrEn) { DMCONTROLNxt.dmactive := DMCONTROLWrData.dmactive } //----HARTINFO // DATA registers are mapped to memory. The dataaddr field of HARTINFO has only // 12 bits and assumes the DM base is 0. If not at 0, then HARTINFO reads as 0 // (implying nonexistence according to the Debug Spec). val HARTINFORdData = WireInit(0.U.asTypeOf(new HARTINFOFields())) if (cfg.atzero) when (dmAuthenticated) { HARTINFORdData.dataaccess := true.B HARTINFORdData.datasize := cfg.nAbstractDataWords.U HARTINFORdData.dataaddr := DsbRegAddrs.DATA.U HARTINFORdData.nscratch := cfg.nScratch.U } //-------------------------------------------------------------- // Hart array mask and window // hamask is hart array mask(1 bit per component), which doesn't include the hart selected by dmcontrol.hartsello // HAWINDOWSEL selects a 32-bit slice of HAMASK to be visible for read/write in HAWINDOW //-------------------------------------------------------------- val hamask = WireInit(VecInit(Seq.fill(nComponents) {false.B} )) def haWindowSize = 32 // The following need to be declared even if supportHartArray is false due to reference // at compile time by dmiNode.regmap val HAWINDOWSELWrData = WireInit(0.U.asTypeOf(new HAWINDOWSELFields())) val HAWINDOWSELWrEn = WireInit(false.B) val HAWINDOWRdData = WireInit(0.U.asTypeOf(new HAWINDOWFields())) val HAWINDOWWrData = WireInit(0.U.asTypeOf(new HAWINDOWFields())) val HAWINDOWWrEn = WireInit(false.B) /* whether the hart is selected / def hartSelected(hart: Int): Bool = { ((io.innerCtrl.bits.hartsel === hart.U) \|\| (if (supportHartArray) io.innerCtrl.bits.hasel && io.innerCtrl.bits.hamask(hart) else false.B)) } val HAWINDOWSELNxt = WireInit(0.U.asTypeOf(new HAWINDOWSELFields())) val HAWINDOWSELReg = RegNext(next=HAWINDOWSELNxt, init=0.U.asTypeOf(HAWINDOWSELNxt)) if (supportHartArray) { val HAWINDOWSELReset = WireInit(0.U.asTypeOf(new HAWINDOWSELFields())) HAWINDOWSELNxt := HAWINDOWSELReg when (~dmactive \|\| ~dmAuthenticated) { HAWINDOWSELNxt := HAWINDOWSELReset } .otherwise { when (HAWINDOWSELWrEn) { // Unneeded upper bits of HAWINDOWSEL are tied to 0. Entire register is 0 if all harts fit in one window if (nComponents > haWindowSize) { HAWINDOWSELNxt.hawindowsel := HAWINDOWSELWrData.hawindowsel & ((1 << (log2Up(nComponents) - 5)) - 1).U } else { HAWINDOWSELNxt.hawindowsel := 0.U } } } val numHAMASKSlices = ((nComponents - 1)/haWindowSize)+1 HAWINDOWRdData.maskdata := 0.U // default, overridden below // for each slice,use a hamaskReg to store the selection info for (ii <- 0 until numHAMASKSlices) { val sliceMask = if (nComponents > ((iihaWindowSize) + haWindowSize-1)) (BigInt(1) << haWindowSize) - 1 // All harts in this slice exist else (BigInt(1)<<(nComponents - (iihaWindowSize))) - 1 // Partial last slice val HAMASKRst = WireInit(0.U.asTypeOf(new HAWINDOWFields())) val HAMASKNxt = WireInit(0.U.asTypeOf(new HAWINDOWFields())) val HAMASKReg = RegNext(next=HAMASKNxt, init=0.U.asTypeOf(HAMASKNxt)) when (ii.U === HAWINDOWSELReg.hawindowsel) { HAWINDOWRdData.maskdata := HAMASKReg.asUInt & sliceMask.U } HAMASKNxt.maskdata := HAMASKReg.asUInt when (~dmactive \|\| ~dmAuthenticated) { HAMASKNxt := HAMASKRst }.otherwise { when (HAWINDOWWrEn && (ii.U === HAWINDOWSELReg.hawindowsel)) { HAMASKNxt.maskdata := HAWINDOWWrData.maskdata } } // drive each slice of hamask with stored HAMASKReg or with new value being written for (jj <- 0 until haWindowSize) { if (((iihaWindowSize) + jj) < nComponents) { val tempWrData = HAWINDOWWrData.maskdata.asBools val tempMaskReg = HAMASKReg.asUInt.asBools when (HAWINDOWWrEn && (ii.U === HAWINDOWSELReg.hawindowsel)) { hamask(iihaWindowSize + jj) := tempWrData(jj) }.otherwise { hamask(iihaWindowSize + jj) := tempMaskReg(jj) } } } } } //-------------------------------------------------------------- // Halt-on-reset // hrmaskReg is current set of harts that should halt-on-reset // Reset state (dmactive=0) is all zeroes // Bits are set by writing 1 to DMCONTROL.setresethaltreq // Bits are cleared by writing 1 to DMCONTROL.clrresethaltreq // Spec says if both are 1, then clrresethaltreq is executed // hrmask is the halt-on-reset mask which will be sent to inner //-------------------------------------------------------------- val hrmask = Wire(Vec(nComponents, Bool())) val hrmaskNxt = Wire(Vec(nComponents, Bool())) val hrmaskReg = RegNext(next=hrmaskNxt, init=0.U.asTypeOf(hrmaskNxt)).suggestName("hrmaskReg") hrmaskNxt := hrmaskReg for (component <- 0 until nComponents) { when (~dmactive \|\| ~dmAuthenticated) { hrmaskNxt(component) := false.B }.elsewhen (clrresethaltreqWrEn && DMCONTROLWrData.clrresethaltreq && hartSelected(component)) { hrmaskNxt(component) := false.B }.elsewhen (setresethaltreqWrEn && DMCONTROLWrData.setresethaltreq && hartSelected(component)) { hrmaskNxt(component) := true.B } } hrmask := hrmaskNxt val dmControlRegFields = RegFieldGroup("dmcontrol", Some("debug module control register"), Seq( WNotifyVal(1, DMCONTROLReg.dmactive & io.ctrl.dmactiveAck, DMCONTROLWrData.dmactive, dmactiveWrEn, RegFieldDesc("dmactive", "debug module active", reset=Some(0))), WNotifyVal(1, DMCONTROLReg.ndmreset, DMCONTROLWrData.ndmreset, ndmresetWrEn, RegFieldDesc("ndmreset", "debug module reset output", reset=Some(0))), WNotifyVal(1, 0.U, DMCONTROLWrData.clrresethaltreq, clrresethaltreqWrEn, RegFieldDesc("clrresethaltreq", "clear reset halt request", reset=Some(0), access=RegFieldAccessType.W)), WNotifyVal(1, 0.U, DMCONTROLWrData.setresethaltreq, setresethaltreqWrEn, RegFieldDesc("setresethaltreq", "set reset halt request", reset=Some(0), access=RegFieldAccessType.W)), RegField(12), if (nComponents > 1) WNotifyVal(p(MaxHartIdBits), DMCONTROLReg.hartsello, DMCONTROLWrData.hartsello, hartselloWrEn, RegFieldDesc("hartsello", "hart select low", reset=Some(0))) else RegField(1), if (nComponents > 1) RegField(10-p(MaxHartIdBits)) else RegField(9), if (supportHartArray) WNotifyVal(1, DMCONTROLReg.hasel, DMCONTROLWrData.hasel, haselWrEn, RegFieldDesc("hasel", "hart array select", reset=Some(0))) else RegField(1), RegField(1), WNotifyVal(1, 0.U, DMCONTROLWrData.ackhavereset, ackhaveresetWrEn, RegFieldDesc("ackhavereset", "acknowledge reset", reset=Some(0), access=RegFieldAccessType.W)), if (cfg.hasHartResets) WNotifyVal(1, DMCONTROLReg.hartreset, DMCONTROLWrData.hartreset, hartresetWrEn, RegFieldDesc("hartreset", "hart reset request", reset=Some(0))) else RegField(1), WNotifyVal(1, 0.U, DMCONTROLWrData.resumereq, resumereqWrEn, RegFieldDesc("resumereq", "resume request", reset=Some(0), access=RegFieldAccessType.W)), WNotifyVal(1, DMCONTROLReg.haltreq, DMCONTROLWrData.haltreq, haltreqWrEn, // Spec says W, but maintaining previous behavior RegFieldDesc("haltreq", "halt request", reset=Some(0))) )) val hartinfoRegFields = RegFieldGroup("dmi_hartinfo", Some("hart information"), Seq( RegField.r(12, HARTINFORdData.dataaddr, RegFieldDesc("dataaddr", "data address", reset=Some(if (cfg.atzero) DsbRegAddrs.DATA else 0))), RegField.r(4, HARTINFORdData.datasize, RegFieldDesc("datasize", "number of DATA registers", reset=Some(if (cfg.atzero) cfg.nAbstractDataWords else 0))), RegField.r(1, HARTINFORdData.dataaccess, RegFieldDesc("dataaccess", "data access type", reset=Some(if (cfg.atzero) 1 else 0))), RegField(3), RegField.r(4, HARTINFORdData.nscratch, RegFieldDesc("nscratch", "number of scratch registers", reset=Some(if (cfg.atzero) cfg.nScratch else 0))) )) //-------------------------------------------------------------- // DMI register decoder for Outer //-------------------------------------------------------------- // regmap addresses are byte offsets from lowest address def DMI_DMCONTROL_OFFSET = 0 def DMI_HARTINFO_OFFSET = ((DMI_HARTINFO - DMI_DMCONTROL) << 2) def DMI_HAWINDOWSEL_OFFSET = ((DMI_HAWINDOWSEL - DMI_DMCONTROL) << 2) def DMI_HAWINDOW_OFFSET = ((DMI_HAWINDOW - DMI_DMCONTROL) << 2) val omRegMap = dmiNode.regmap( DMI_DMCONTROL_OFFSET -> dmControlRegFields, DMI_HARTINFO_OFFSET -> hartinfoRegFields, DMI_HAWINDOWSEL_OFFSET -> (if (supportHartArray && (nComponents > 32)) Seq( WNotifyVal(log2Up(nComponents)-5, HAWINDOWSELReg.hawindowsel, HAWINDOWSELWrData.hawindowsel, HAWINDOWSELWrEn, RegFieldDesc("hawindowsel", "hart array window select", reset=Some(0)))) else Nil), DMI_HAWINDOW_OFFSET -> (if (supportHartArray) Seq( WNotifyVal(if (nComponents > 31) 32 else nComponents, HAWINDOWRdData.maskdata, HAWINDOWWrData.maskdata, HAWINDOWWrEn, RegFieldDesc("hawindow", "hart array window", reset=Some(0), volatile=(nComponents > 32)))) else Nil) ) //-------------------------------------------------------------- // Interrupt Registers //-------------------------------------------------------------- val debugIntNxt = WireInit(VecInit(Seq.fill(nComponents) {false.B} )) val debugIntRegs = RegNext(next=debugIntNxt, init=0.U.asTypeOf(debugIntNxt)).suggestName("debugIntRegs") debugIntNxt := debugIntRegs val (intnode_out, _) = intnode.out.unzip for (component <- 0 until nComponents) { intnode_out(component)(0) := debugIntRegs(component) \| io.hgDebugInt(component) } // sends debug interruption to Core when dmcs.haltreq is set, for (component <- 0 until nComponents) { when (~dmactive \|\| ~dmAuthenticated) { debugIntNxt(component) := false.B }. otherwise { when (haltreqWrEn && ((DMCONTROLWrData.hartsello === component.U) \|\| (if (supportHartArray) DMCONTROLWrData.hasel && hamask(component) else false.B))) { debugIntNxt(component) := DMCONTROLWrData.haltreq } } } // Halt request registers are set & cleared by writes to DMCONTROL.haltreq // resumereq also causes the core to execute a 'dret', // so resumereq is passed through to Inner. // hartsel/hasel/hamask must also be used by the DebugModule state machine, // so it is passed to Inner. // These registers ensure that requests to dmInner are not lost if inner clock isn't running or requests occur too close together. // If the innerCtrl async queue is not ready, the notification will be posted and held until ready is received. // Additional notifications that occur while one is already waiting update the pending data so that the last value written is sent. // Volatile events resumereq and ackhavereset are registered when they occur and remain pending until ready is received. val innerCtrlValid = Wire(Bool()) val innerCtrlValidReg = RegInit(false.B).suggestName("innerCtrlValidReg") val innerCtrlResumeReqReg = RegInit(false.B).suggestName("innerCtrlResumeReqReg") val innerCtrlAckHaveResetReg = RegInit(false.B).suggestName("innerCtrlAckHaveResetReg") innerCtrlValid := hartselloWrEn \| resumereqWrEn \| ackhaveresetWrEn \| setresethaltreqWrEn \| clrresethaltreqWrEn \| haselWrEn \| (HAWINDOWWrEn & supportHartArray.B) innerCtrlValidReg := io.innerCtrl.valid & ~io.innerCtrl.ready // Hold innerctrl request until the async queue accepts it innerCtrlResumeReqReg := io.innerCtrl.bits.resumereq & ~io.innerCtrl.ready // Hold resumereq until accepted innerCtrlAckHaveResetReg := io.innerCtrl.bits.ackhavereset & ~io.innerCtrl.ready // Hold ackhavereset until accepted io.innerCtrl.valid := innerCtrlValid \| innerCtrlValidReg io.innerCtrl.bits.hartsel := Mux(hartselloWrEn, DMCONTROLWrData.hartsello, DMCONTROLReg.hartsello) io.innerCtrl.bits.resumereq := (resumereqWrEn & DMCONTROLWrData.resumereq) \| innerCtrlResumeReqReg io.innerCtrl.bits.ackhavereset := (ackhaveresetWrEn & DMCONTROLWrData.ackhavereset) \| innerCtrlAckHaveResetReg io.innerCtrl.bits.hrmask := hrmask if (supportHartArray) { io.innerCtrl.bits.hasel := Mux(haselWrEn, DMCONTROLWrData.hasel, DMCONTROLReg.hasel) io.innerCtrl.bits.hamask := hamask } else { io.innerCtrl.bits.hasel := DontCare io.innerCtrl.bits.hamask := DontCare } io.ctrl.ndreset := DMCONTROLReg.ndmreset io.ctrl.dmactive := DMCONTROLReg.dmactive // hart reset mechanism implementation if (cfg.hasHartResets) { val hartResetNxt = Wire(Vec(nComponents, Bool())) val hartResetReg = RegNext(next=hartResetNxt, init=0.U.asTypeOf(hartResetNxt)) for (component <- 0 until nComponents) { hartResetNxt(component) := DMCONTROLReg.hartreset & hartSelected(component) io.hartResetReq.get(component) := hartResetReg(component) } } omRegMap // FIXME: Remove this when withReset is removed }} } // wrap a Outer with a DMIToTL, derived by dmi clock & reset class TLDebugModuleOuterAsync(device: Device)(implicit p: Parameters) extends LazyModule { val cfg = p(DebugModuleKey).get val dmiXbar = LazyModule (new TLXbar(nameSuffix = Some("dmixbar"))) val dmi2tlOpt = (!p(ExportDebug).apb).option({ val dmi2tl = LazyModule(new DMIToTL()) dmiXbar.node := dmi2tl.node dmi2tl }) val apbNodeOpt = p(ExportDebug).apb.option({ val apb2tl = LazyModule(new APBToTL()) val apb2tlBuffer = LazyModule(new TLBuffer(BufferParams.pipe)) val dmTopAddr = (1 << cfg.nDMIAddrSize) << 2 val tlErrorParams = DevNullParams(AddressSet.misaligned(dmTopAddr, APBDebugConsts.apbDebugRegBase-dmTopAddr), maxAtomic=0, maxTransfer=4) val tlError = LazyModule(new TLError(tlErrorParams, buffer=false)) val apbXbar = LazyModule(new APBFanout()) val apbRegs = LazyModule(new APBDebugRegisters()) apbRegs.node := apbXbar.node apb2tl.node := apbXbar.node apb2tlBuffer.node := apb2tl.node dmiXbar.node := apb2tlBuffer.node tlError.node := dmiXbar.node apbXbar.node }) val dmOuter = LazyModule( new TLDebugModuleOuter(device)) val intnode = IntSyncIdentityNode() intnode := IntSyncCrossingSource(alreadyRegistered = true) := dmOuter.intnode val dmiBypass = LazyModule(new TLBusBypass(beatBytes=4, bufferError=false, maxAtomic=0, maxTransfer=4)) val dmiInnerNode = TLAsyncCrossingSource() := dmiBypass.node := dmiXbar.node dmOuter.dmiNode := dmiXbar.node lazy val module = new Impl class Impl extends LazyRawModuleImp(this) { val nComponents = dmOuter.intnode.edges.out.size val io = IO(new Bundle { val dmi_clock = Input(Clock()) val dmi_reset = Input(Reset()) /** Debug Module Interface bewteen DM and DTM * * The DTM provides access to one or more Debug Modules (DMs) using DMI / val dmi = (!p(ExportDebug).apb).option(Flipped(new DMIIO()(p))) // Optional APB Interface is fully diplomatic so is not listed here. val ctrl = new DebugCtrlBundle(nComponents) /* conrol signals for Inner, generated in Outer / val innerCtrl = new AsyncBundle(new DebugInternalBundle(nComponents), AsyncQueueParams.singleton(safe=cfg.crossingHasSafeReset)) /* debug interruption generated in Inner / val hgDebugInt = Input(Vec(nComponents, Bool())) /* hart reset request to core / val hartResetReq = p(DebugModuleKey).get.hasHartResets.option(Output(Vec(nComponents, Bool()))) /* Authentication signal from core / val dmAuthenticated = p(DebugModuleKey).get.hasAuthentication.option(Input(Bool())) }) val rf_reset = IO(Input(Reset())) // RF transform childClock := io.dmi_clock childReset := io.dmi_reset override def provideImplicitClockToLazyChildren = true withClockAndReset(childClock, childReset) { dmi2tlOpt.foreach { _.module.io.dmi <> io.dmi.get } val dmactiveAck = AsyncResetSynchronizerShiftReg(in=io.ctrl.dmactiveAck, sync=3, name=Some("dmactiveAckSync")) dmiBypass.module.io.bypass := ~io.ctrl.dmactive \| ~dmactiveAck io.ctrl <> dmOuter.module.io.ctrl dmOuter.module.io.ctrl.dmactiveAck := dmactiveAck // send synced version down to dmOuter io.innerCtrl <> ToAsyncBundle(dmOuter.module.io.innerCtrl, AsyncQueueParams.singleton(safe=cfg.crossingHasSafeReset)) dmOuter.module.io.hgDebugInt := io.hgDebugInt io.hartResetReq.foreach { x => dmOuter.module.io.hartResetReq.foreach {y => x := y}} io.dmAuthenticated.foreach { x => dmOuter.module.io.dmAuthenticated.foreach { y => y := x}} } } } class TLDebugModuleInner(device: Device, getNComponents: () => Int, beatBytes: Int)(implicit p: Parameters) extends LazyModule { // For Shorter Register Names import DMI_RegAddrs._ val cfg = p(DebugModuleKey).get def getCfg = () => cfg val dmTopAddr = (1 << cfg.nDMIAddrSize) << 2 /* dmiNode address set / val dmiNode = TLRegisterNode( // Address is range 0 to 0x1FF except DMCONTROL, HARTINFO, HAWINDOWSEL, HAWINDOW which are handled by Outer address = AddressSet.misaligned(0, DMI_DMCONTROL << 2) ++ AddressSet.misaligned((DMI_DMCONTROL + 1) << 2, ((DMI_HARTINFO << 2) - ((DMI_DMCONTROL + 1) << 2))) ++ AddressSet.misaligned((DMI_HARTINFO + 1) << 2, ((DMI_HAWINDOWSEL << 2) - ((DMI_HARTINFO + 1) << 2))) ++ AddressSet.misaligned((DMI_HAWINDOW + 1) << 2, (dmTopAddr - ((DMI_HAWINDOW + 1) << 2))), device = device, beatBytes = 4, executable = false ) val tlNode = TLRegisterNode( address=Seq(cfg.address), device=device, beatBytes=beatBytes, executable=true ) val sb2tlOpt = cfg.hasBusMaster.option(LazyModule(new SBToTL())) // If we want to support custom registers read through Abstract Commands, // provide a place to bring them into the debug module. What this connects // to is up to the implementation. val customNode = new DebugCustomSink() lazy val module = new Impl class Impl extends LazyModuleImp(this){ val nComponents = getNComponents() Annotated.params(this, cfg) val supportHartArray = cfg.supportHartArray & (nComponents > 1) val nExtTriggers = cfg.nExtTriggers val nHaltGroups = if ((nComponents > 1) \| (nExtTriggers > 0)) cfg.nHaltGroups else 0 // no halt groups possible if single hart with no external triggers val hartSelFuncs = if (getNComponents() > 1) p(DebugModuleHartSelKey) else DebugModuleHartSelFuncs( hartIdToHartSel = (x) => 0.U, hartSelToHartId = (x) => x ) val io = IO(new Bundle { /* dm reset signal passed in from Outer / val dmactive = Input(Bool()) /* conrol signals for Inner * * it's generated by Outer and comes in / val innerCtrl = Flipped(new DecoupledIO(new DebugInternalBundle(nComponents))) /* debug unavail signal passed in from Outer/ val debugUnavail = Input(Vec(nComponents, Bool())) /* debug interruption from Inner to Outer * * contain 2 type of debug interruption causes: * - halt group * - halt-on-reset / val hgDebugInt = Output(Vec(nComponents, Bool())) /* interface for trigger / val extTrigger = (nExtTriggers > 0).option(new DebugExtTriggerIO()) /* vector to indicate which hart is in reset * * dm receives it from core and sends it to Inner / val hartIsInReset = Input(Vec(nComponents, Bool())) val tl_clock = Input(Clock()) val tl_reset = Input(Reset()) /* Debug Authentication signals from core / val auth = cfg.hasAuthentication.option(new DebugAuthenticationIO()) }) sb2tlOpt.map { sb => sb.module.clock := io.tl_clock sb.module.reset := io.tl_reset sb.module.rf_reset := io.tl_reset } //-------------------------------------------------------------- // Import constants for shorter variable names //-------------------------------------------------------------- import DMI_RegAddrs._ import DsbRegAddrs._ import DsbBusConsts._ //-------------------------------------------------------------- // Sanity Check Configuration For this implementation. //-------------------------------------------------------------- require (cfg.supportQuickAccess == false, "No Quick Access support yet") require ((nHaltGroups > 0) \|\| (nExtTriggers == 0), "External triggers require at least 1 halt group") //-------------------------------------------------------------- // Register & Wire Declarations (which need to be pre-declared) //-------------------------------------------------------------- // run control regs: tracking all the harts // implements: see implementation-specific bits part /* all harts halted status / val haltedBitRegs = Reg(UInt(nComponents.W)) /* all harts resume request status / val resumeReqRegs = Reg(UInt(nComponents.W)) /* all harts have reset status / val haveResetBitRegs = Reg(UInt(nComponents.W)) // default is 1,after resume, resumeAcks get 0 /* all harts resume ack status / val resumeAcks = Wire(UInt(nComponents.W)) // --- regmapper outputs // hart state Id and En // in Hart Bus Access ROM val hartHaltedWrEn = Wire(Bool()) val hartHaltedId = Wire(UInt(sbIdWidth.W)) val hartGoingWrEn = Wire(Bool()) val hartGoingId = Wire(UInt(sbIdWidth.W)) val hartResumingWrEn = Wire(Bool()) val hartResumingId = Wire(UInt(sbIdWidth.W)) val hartExceptionWrEn = Wire(Bool()) val hartExceptionId = Wire(UInt(sbIdWidth.W)) // progbuf and abstract data: byte-addressable control logic // AccessLegal is set only when state = waiting // RdEn and WrEnMaybe : contrl signal drived by DMI bus val dmiProgramBufferRdEn = WireInit(VecInit(Seq.fill(cfg.nProgramBufferWords 4) {false.B} )) val dmiProgramBufferAccessLegal = WireInit(false.B) val dmiProgramBufferWrEnMaybe = WireInit(VecInit(Seq.fill(cfg.nProgramBufferWords * 4) {false.B} )) val dmiAbstractDataRdEn = WireInit(VecInit(Seq.fill(cfg.nAbstractDataWords * 4) {false.B} )) val dmiAbstractDataAccessLegal = WireInit(false.B) val dmiAbstractDataWrEnMaybe = WireInit(VecInit(Seq.fill(cfg.nAbstractDataWords * 4) {false.B} )) //-------------------------------------------------------------- // Registers coming from 'CONTROL' in Outer //-------------------------------------------------------------- val dmAuthenticated = io.auth.map(a => a.dmAuthenticated).getOrElse(true.B) val selectedHartReg = Reg(UInt(p(MaxHartIdBits).W)) // hamaskFull is a vector of all selected harts including hartsel, whether or not supportHartArray is true val hamaskFull = WireInit(VecInit(Seq.fill(nComponents) {false.B} )) if (nComponents > 1) { when (~io.dmactive) { selectedHartReg := 0.U }.elsewhen (io.innerCtrl.fire){ selectedHartReg := io.innerCtrl.bits.hartsel } } if (supportHartArray) { val hamaskZero = WireInit(VecInit(Seq.fill(nComponents) {false.B} )) val hamaskReg = Reg(Vec(nComponents, Bool())) when (~io.dmactive \|\| ~dmAuthenticated) { hamaskReg := hamaskZero }.elsewhen (io.innerCtrl.fire){ hamaskReg := Mux(io.innerCtrl.bits.hasel, io.innerCtrl.bits.hamask, hamaskZero) } hamaskFull := hamaskReg } // Outer.hamask doesn't consider the hart selected by dmcontrol.hartsello, // so append it here when (selectedHartReg < nComponents.U) { hamaskFull(if (nComponents == 1) 0.U(0.W) else selectedHartReg) := true.B } io.innerCtrl.ready := true.B // Construct a Vec from io.innerCtrl fields indicating whether each hart is being selected in this write // A hart may be selected by hartsel field or by hart array val hamaskWrSel = WireInit(VecInit(Seq.fill(nComponents) {false.B} )) for (component <- 0 until nComponents ) { hamaskWrSel(component) := ((io.innerCtrl.bits.hartsel === component.U) \|\| (if (supportHartArray) io.innerCtrl.bits.hasel && io.innerCtrl.bits.hamask(component) else false.B)) } //------------------------------------- // Halt-on-reset logic // hrmask is set in dmOuter and passed in // Debug interrupt is generated when a reset occurs whose corresponding hrmask bit is set // Debug interrupt is maintained until the hart enters halted state //------------------------------------- val hrReset = WireInit(VecInit(Seq.fill(nComponents) { false.B } )) val hrDebugInt = Wire(Vec(nComponents, Bool())) val hrmaskReg = RegInit(hrReset) val hartIsInResetSync = Wire(Vec(nComponents, Bool())) for (component <- 0 until nComponents) { hartIsInResetSync(component) := AsyncResetSynchronizerShiftReg(io.hartIsInReset(component), 3, Some(s"debug_hartReset_$component")) } when (~io.dmactive \|\| ~dmAuthenticated) { hrmaskReg := hrReset }.elsewhen (io.innerCtrl.fire){ hrmaskReg := io.innerCtrl.bits.hrmask } withReset(reset.asAsyncReset) { // ensure interrupt requests are negated at first clock edge val hrDebugIntReg = RegInit(VecInit(Seq.fill(nComponents) { false.B } )) when (~io.dmactive \|\| ~dmAuthenticated) { hrDebugIntReg := hrReset }.otherwise { hrDebugIntReg := hrmaskReg & (hartIsInResetSync \| // set debugInt during reset (hrDebugIntReg & ~(haltedBitRegs.asBools))) // maintain until core halts } hrDebugInt := hrDebugIntReg } //-------------------------------------------------------------- // DMI Registers //-------------------------------------------------------------- //----DMSTATUS val DMSTATUSRdData = WireInit(0.U.asTypeOf(new DMSTATUSFields())) DMSTATUSRdData.authenticated := dmAuthenticated DMSTATUSRdData.version := 2.U // Version 0.13 io.auth.map(a => DMSTATUSRdData.authbusy := a.dmAuthBusy) val resumereq = io.innerCtrl.fire && io.innerCtrl.bits.resumereq when (dmAuthenticated) { DMSTATUSRdData.hasresethaltreq := true.B DMSTATUSRdData.anynonexistent := (selectedHartReg >= nComponents.U) // only hartsel can be nonexistent // all harts nonexistent if hartsel is out of range and there are no harts selected in the hart array DMSTATUSRdData.allnonexistent := (selectedHartReg >= nComponents.U) & (~hamaskFull.reduce(_ \| _)) when (~DMSTATUSRdData.allnonexistent) { // if no existent harts selected, all other status is false DMSTATUSRdData.anyunavail := (io.debugUnavail & hamaskFull).reduce(_ \| _) DMSTATUSRdData.anyhalted := ((~io.debugUnavail & (haltedBitRegs.asBools)) & hamaskFull).reduce(_ \| _) DMSTATUSRdData.anyrunning := ((~io.debugUnavail & ~(haltedBitRegs.asBools)) & hamaskFull).reduce(_ \| _) DMSTATUSRdData.anyhavereset := (haveResetBitRegs.asBools & hamaskFull).reduce(_ \| _) DMSTATUSRdData.anyresumeack := (resumeAcks.asBools & hamaskFull).reduce(_ \| _) when (~DMSTATUSRdData.anynonexistent) { // if one hart is nonexistent, no 'all' status is set DMSTATUSRdData.allunavail := (io.debugUnavail \| ~hamaskFull).reduce(_ & _) DMSTATUSRdData.allhalted := ((~io.debugUnavail & (haltedBitRegs.asBools)) \| ~hamaskFull).reduce(_ & _) DMSTATUSRdData.allrunning := ((~io.debugUnavail & ~(haltedBitRegs.asBools)) \| ~hamaskFull).reduce(_ & _) DMSTATUSRdData.allhavereset := (haveResetBitRegs.asBools \| ~hamaskFull).reduce(_ & _) DMSTATUSRdData.allresumeack := (resumeAcks.asBools \| ~hamaskFull).reduce(_ & _) } } //TODO DMSTATUSRdData.confstrptrvalid := false.B DMSTATUSRdData.impebreak := (cfg.hasImplicitEbreak).B } when(~io.dmactive \|\| ~dmAuthenticated) { haveResetBitRegs := 0.U }.otherwise { when (io.innerCtrl.fire && io.innerCtrl.bits.ackhavereset) { haveResetBitRegs := (haveResetBitRegs & (~(hamaskWrSel.asUInt))) \| hartIsInResetSync.asUInt }.otherwise { haveResetBitRegs := haveResetBitRegs \| hartIsInResetSync.asUInt } } //----DMCS2 (Halt Groups) val DMCS2RdData = WireInit(0.U.asTypeOf(new DMCS2Fields())) val DMCS2WrData = WireInit(0.U.asTypeOf(new DMCS2Fields())) val hgselectWrEn = WireInit(false.B) val hgwriteWrEn = WireInit(false.B) val haltgroupWrEn = WireInit(false.B) val exttriggerWrEn = WireInit(false.B) val hgDebugInt = WireInit(VecInit(Seq.fill(nComponents) {false.B} )) if (nHaltGroups > 0) withReset (reset.asAsyncReset) { // async reset ensures triggers don't falsely fire during startup val hgBits = log2Up(nHaltGroups) // hgParticipate: Each entry indicates which hg that entity belongs to (1 to nHartGroups). 0 means no hg assigned. val hgParticipateHart = RegInit(VecInit(Seq.fill(nComponents)(0.U(hgBits.W)))) val hgParticipateTrig = if (nExtTriggers > 0) RegInit(VecInit(Seq.fill(nExtTriggers)(0.U(hgBits.W)))) else Nil // assign group index to current seledcted harts for (component <- 0 until nComponents) { when (~io.dmactive \|\| ~dmAuthenticated) { hgParticipateHart(component) := 0.U }.otherwise { when (haltgroupWrEn & DMCS2WrData.hgwrite & ~DMCS2WrData.hgselect & hamaskFull(component) & (DMCS2WrData.haltgroup <= nHaltGroups.U)) { hgParticipateHart(component) := DMCS2WrData.haltgroup } } } DMCS2RdData.haltgroup := hgParticipateHart(if (nComponents == 1) 0.U(0.W) else selectedHartReg) if (nExtTriggers > 0) { val hgSelect = Reg(Bool()) when (~io.dmactive \|\| ~dmAuthenticated) { hgSelect := false.B }.otherwise { when (hgselectWrEn) { hgSelect := DMCS2WrData.hgselect } } // assign group index to trigger for (trigger <- 0 until nExtTriggers) { when (~io.dmactive \|\| ~dmAuthenticated) { hgParticipateTrig(trigger) := 0.U }.otherwise { when (haltgroupWrEn & DMCS2WrData.hgwrite & DMCS2WrData.hgselect & (DMCS2WrData.exttrigger === trigger.U) & (DMCS2WrData.haltgroup <= nHaltGroups.U)) { hgParticipateTrig(trigger) := DMCS2WrData.haltgroup } } } DMCS2RdData.hgselect := hgSelect when (hgSelect) { DMCS2RdData.haltgroup := hgParticipateTrig(0) } // If there is only 1 ext trigger, then the exttrigger field is fixed at 0 // Otherwise, instantiate a register with only the number of bits required if (nExtTriggers > 1) { val trigBits = log2Up(nExtTriggers-1) val hgExtTrigger = Reg(UInt(trigBits.W)) when (~io.dmactive \|\| ~dmAuthenticated) { hgExtTrigger := 0.U }.otherwise { when (exttriggerWrEn & (DMCS2WrData.exttrigger < nExtTriggers.U)) { hgExtTrigger := DMCS2WrData.exttrigger } } DMCS2RdData.exttrigger := hgExtTrigger when (hgSelect) { DMCS2RdData.haltgroup := hgParticipateTrig(hgExtTrigger) } } } // Halt group state machine // IDLE: Go to FIRED when any hart in this hg writes to HALTED while its HaltedBitRegs=0 // or when any trigin assigned to this hg occurs // FIRED: Back to IDLE when all harts in this hg have set their haltedBitRegs // and all trig out in this hg have been acknowledged val hgFired = RegInit (VecInit(Seq.fill(nHaltGroups+1) {false.B} )) val hgHartFiring = WireInit(VecInit(Seq.fill(nHaltGroups+1) {false.B} )) // which hg's are firing due to hart halting val hgTrigFiring = WireInit(VecInit(Seq.fill(nHaltGroups+1) {false.B} )) // which hg's are firing due to trig in val hgHartsAllHalted = WireInit(VecInit(Seq.fill(nHaltGroups+1) {false.B} )) // in which hg's have all harts halted val hgTrigsAllAcked = WireInit(VecInit(Seq.fill(nHaltGroups+1) { true.B} )) // in which hg's have all trigouts been acked io.extTrigger.foreach {extTrigger => val extTriggerInReq = Wire(Vec(nExtTriggers, Bool())) val extTriggerOutAck = Wire(Vec(nExtTriggers, Bool())) extTriggerInReq := extTrigger.in.req.asBools extTriggerOutAck := extTrigger.out.ack.asBools val trigInReq = ResetSynchronizerShiftReg(in=extTriggerInReq, sync=3, name=Some("dm_extTriggerInReqSync")) val trigOutAck = ResetSynchronizerShiftReg(in=extTriggerOutAck, sync=3, name=Some("dm_extTriggerOutAckSync")) for (hg <- 1 to nHaltGroups) { hgTrigFiring(hg) := (trigInReq & ~RegNext(trigInReq) & hgParticipateTrig.map(_ === hg.U)).reduce(_ \| _) hgTrigsAllAcked(hg) := (trigOutAck \| hgParticipateTrig.map(_ =/= hg.U)).reduce(_ & _) } extTrigger.in.ack := trigInReq.asUInt } for (hg <- 1 to nHaltGroups) { hgHartFiring(hg) := hartHaltedWrEn & ~haltedBitRegs(hartHaltedId) & (hgParticipateHart(hartSelFuncs.hartIdToHartSel(hartHaltedId)) === hg.U) hgHartsAllHalted(hg) := (haltedBitRegs.asBools \| hgParticipateHart.map(_ =/= hg.U)).reduce(_ & _) when (~io.dmactive \|\| ~dmAuthenticated) { hgFired(hg) := false.B }.elsewhen (~hgFired(hg) & (hgHartFiring(hg) \| hgTrigFiring(hg))) { hgFired(hg) := true.B }.elsewhen ( hgFired(hg) & hgHartsAllHalted(hg) & hgTrigsAllAcked(hg)) { hgFired(hg) := false.B } } // For each hg that has fired, assert debug interrupt to each hart in that hg for (component <- 0 until nComponents) { hgDebugInt(component) := hgFired(hgParticipateHart(component)) } // For each hg that has fired, assert trigger out for all external triggers in that hg io.extTrigger.foreach {extTrigger => val extTriggerOutReq = RegInit(VecInit(Seq.fill(cfg.nExtTriggers) {false.B} )) for (trig <- 0 until nExtTriggers) { extTriggerOutReq(trig) := hgFired(hgParticipateTrig(trig)) } extTrigger.out.req := extTriggerOutReq.asUInt } } io.hgDebugInt := hgDebugInt \| hrDebugInt //----HALTSUM* val numHaltedStatus = ((nComponents - 1) / 32) + 1 val haltedStatus = Wire(Vec(numHaltedStatus, Bits(32.W))) for (ii <- 0 until numHaltedStatus) { when (dmAuthenticated) { haltedStatus(ii) := haltedBitRegs >> (ii32) }.otherwise { haltedStatus(ii) := 0.U } } val haltedSummary = Cat(haltedStatus.map(_.orR).reverse) val HALTSUM1RdData = haltedSummary.asTypeOf(new HALTSUM1Fields()) val selectedHaltedStatus = Mux((selectedHartReg >> 5) > numHaltedStatus.U, 0.U, haltedStatus(selectedHartReg >> 5)) val HALTSUM0RdData = selectedHaltedStatus.asTypeOf(new HALTSUM0Fields()) // Since we only support 1024 harts, we don't implement HALTSUM2 or HALTSUM3 //----ABSTRACTCS val ABSTRACTCSReset = WireInit(0.U.asTypeOf(new ABSTRACTCSFields())) ABSTRACTCSReset.datacount := cfg.nAbstractDataWords.U ABSTRACTCSReset.progbufsize := cfg.nProgramBufferWords.U val ABSTRACTCSReg = Reg(new ABSTRACTCSFields()) val ABSTRACTCSWrData = WireInit(0.U.asTypeOf(new ABSTRACTCSFields())) val ABSTRACTCSRdData = WireInit(ABSTRACTCSReg) val ABSTRACTCSRdEn = WireInit(false.B) val ABSTRACTCSWrEnMaybe = WireInit(false.B) val ABSTRACTCSWrEnLegal = WireInit(false.B) val ABSTRACTCSWrEn = ABSTRACTCSWrEnMaybe && ABSTRACTCSWrEnLegal // multiple error types // find implement in the state machine part val errorBusy = WireInit(false.B) val errorException = WireInit(false.B) val errorUnsupported = WireInit(false.B) val errorHaltResume = WireInit(false.B) when (~io.dmactive \|\| ~dmAuthenticated) { ABSTRACTCSReg := ABSTRACTCSReset }.otherwise { when (errorBusy){ ABSTRACTCSReg.cmderr := DebugAbstractCommandError.ErrBusy.id.U }.elsewhen (errorException) { ABSTRACTCSReg.cmderr := DebugAbstractCommandError.ErrException.id.U }.elsewhen (errorUnsupported) { ABSTRACTCSReg.cmderr := DebugAbstractCommandError.ErrNotSupported.id.U }.elsewhen (errorHaltResume) { ABSTRACTCSReg.cmderr := DebugAbstractCommandError.ErrHaltResume.id.U }.otherwise { //W1C when (ABSTRACTCSWrEn){ ABSTRACTCSReg.cmderr := ABSTRACTCSReg.cmderr & ~(ABSTRACTCSWrData.cmderr); } } } // For busy, see below state machine. val abstractCommandBusy = WireInit(true.B) ABSTRACTCSRdData.busy := abstractCommandBusy when (~dmAuthenticated) { // read value must be 0 when not authenticated ABSTRACTCSRdData.datacount := 0.U ABSTRACTCSRdData.progbufsize := 0.U } //---- ABSTRACTAUTO // It is a mask indicating whether datai/probufi have the autoexcution permisson // this part aims to produce 3 wires : autoexecData,autoexecProg,autoexec // first two specify which reg supports autoexec // autoexec is a control signal, meaning there is at least one enabled autoexec reg // when autoexec is set, generate instructions using COMMAND register val ABSTRACTAUTOReset = WireInit(0.U.asTypeOf(new ABSTRACTAUTOFields())) val ABSTRACTAUTOReg = Reg(new ABSTRACTAUTOFields()) val ABSTRACTAUTOWrData = WireInit(0.U.asTypeOf(new ABSTRACTAUTOFields())) val ABSTRACTAUTORdData = WireInit(ABSTRACTAUTOReg) val ABSTRACTAUTORdEn = WireInit(false.B) val autoexecdataWrEnMaybe = WireInit(false.B) val autoexecprogbufWrEnMaybe = WireInit(false.B) val ABSTRACTAUTOWrEnLegal = WireInit(false.B) when (~io.dmactive \|\| ~dmAuthenticated) { ABSTRACTAUTOReg := ABSTRACTAUTOReset }.otherwise { when (autoexecprogbufWrEnMaybe && ABSTRACTAUTOWrEnLegal) { ABSTRACTAUTOReg.autoexecprogbuf := ABSTRACTAUTOWrData.autoexecprogbuf & ( (1 << cfg.nProgramBufferWords) - 1).U } when (autoexecdataWrEnMaybe && ABSTRACTAUTOWrEnLegal) { ABSTRACTAUTOReg.autoexecdata := ABSTRACTAUTOWrData.autoexecdata & ( (1 << cfg.nAbstractDataWords) - 1).U } } // Abstract Data access vector(byte-addressable) val dmiAbstractDataAccessVec = WireInit(VecInit(Seq.fill(cfg.nAbstractDataWords 4) {false.B} )) dmiAbstractDataAccessVec := (dmiAbstractDataWrEnMaybe zip dmiAbstractDataRdEn).map{ case (r,w) => r \| w} // Program Buffer access vector(byte-addressable) val dmiProgramBufferAccessVec = WireInit(VecInit(Seq.fill(cfg.nProgramBufferWords * 4) {false.B} )) dmiProgramBufferAccessVec := (dmiProgramBufferWrEnMaybe zip dmiProgramBufferRdEn).map{ case (r,w) => r \| w} // at least one word access val dmiAbstractDataAccess = dmiAbstractDataAccessVec.reduce(_ \|\| _ ) val dmiProgramBufferAccess = dmiProgramBufferAccessVec.reduce(_ \|\| _) // This will take the shorter of the lists, which is what we want. val autoexecData = WireInit(VecInit(Seq.fill(cfg.nAbstractDataWords) {false.B} )) val autoexecProg = WireInit(VecInit(Seq.fill(cfg.nProgramBufferWords) {false.B} )) (autoexecData zip ABSTRACTAUTOReg.autoexecdata.asBools).zipWithIndex.foreach {case (t, i) => t._1 := dmiAbstractDataAccessVec(i * 4) && t._2 } (autoexecProg zip ABSTRACTAUTOReg.autoexecprogbuf.asBools).zipWithIndex.foreach {case (t, i) => t._1 := dmiProgramBufferAccessVec(i * 4) && t._2} val autoexec = autoexecData.reduce(_ \|\| _) \|\| autoexecProg.reduce(_ \|\| _) //---- COMMAND val COMMANDReset = WireInit(0.U.asTypeOf(new COMMANDFields())) val COMMANDReg = Reg(new COMMANDFields()) val COMMANDWrDataVal = WireInit(0.U(32.W)) val COMMANDWrData = WireInit(COMMANDWrDataVal.asTypeOf(new COMMANDFields())) val COMMANDWrEnMaybe = WireInit(false.B) val COMMANDWrEnLegal = WireInit(false.B) val COMMANDRdEn = WireInit(false.B) val COMMANDWrEn = COMMANDWrEnMaybe && COMMANDWrEnLegal val COMMANDRdData = COMMANDReg when (~io.dmactive \|\| ~dmAuthenticated) { COMMANDReg := COMMANDReset }.otherwise { when (COMMANDWrEn) { COMMANDReg := COMMANDWrData } } // --- Abstract Data // These are byte addressible, s.t. the Processor can use // byte-addressible instructions to store to them. val abstractDataMem = Reg(Vec(cfg.nAbstractDataWords4, UInt(8.W))) val abstractDataNxt = WireInit(abstractDataMem) // --- Program Buffer // byte-addressible mem val programBufferMem = Reg(Vec(cfg.nProgramBufferWords4, UInt(8.W))) val programBufferNxt = WireInit(programBufferMem) //-------------------------------------------------------------- // These bits are implementation-specific bits set // by harts executing code. //-------------------------------------------------------------- // Run control logic when (~io.dmactive \|\| ~dmAuthenticated) { haltedBitRegs := 0.U resumeReqRegs := 0.U }.otherwise { //remove those harts in reset resumeReqRegs := resumeReqRegs & ~(hartIsInResetSync.asUInt) val hartHaltedIdIndex = UIntToOH(hartSelFuncs.hartIdToHartSel(hartHaltedId)) val hartResumingIdIndex = UIntToOH(hartSelFuncs.hartIdToHartSel(hartResumingId)) val hartselIndex = UIntToOH(io.innerCtrl.bits.hartsel) when (hartHaltedWrEn) { // add those harts halting and remove those in reset haltedBitRegs := (haltedBitRegs \| hartHaltedIdIndex) & ~(hartIsInResetSync.asUInt) }.elsewhen (hartResumingWrEn) { // remove those harts in reset and those in resume haltedBitRegs := (haltedBitRegs & ~(hartResumingIdIndex)) & ~(hartIsInResetSync.asUInt) }.otherwise { // remove those harts in reset haltedBitRegs := haltedBitRegs & ~(hartIsInResetSync.asUInt) } when (hartResumingWrEn) { // remove those harts in resume and those in reset resumeReqRegs := (resumeReqRegs & ~(hartResumingIdIndex)) & ~(hartIsInResetSync.asUInt) } when (resumereq) { // set all sleceted harts to resumeReq, remove those in reset resumeReqRegs := (resumeReqRegs \| hamaskWrSel.asUInt) & ~(hartIsInResetSync.asUInt) } } when (resumereq) { // next cycle resumeAcls will be the negation of next cycle resumeReqRegs resumeAcks := (~resumeReqRegs & ~(hamaskWrSel.asUInt)) }.otherwise { resumeAcks := ~resumeReqRegs } //---- AUTHDATA val authRdEnMaybe = WireInit(false.B) val authWrEnMaybe = WireInit(false.B) io.auth.map { a => a.dmactive := io.dmactive a.dmAuthRead := authRdEnMaybe & ~a.dmAuthBusy a.dmAuthWrite := authWrEnMaybe & ~a.dmAuthBusy } val dmstatusRegFields = RegFieldGroup("dmi_dmstatus", Some("debug module status register"), Seq( RegField.r(4, DMSTATUSRdData.version, RegFieldDesc("version", "version", reset=Some(2))), RegField.r(1, DMSTATUSRdData.confstrptrvalid, RegFieldDesc("confstrptrvalid", "confstrptrvalid", reset=Some(0))), RegField.r(1, DMSTATUSRdData.hasresethaltreq, RegFieldDesc("hasresethaltreq", "hasresethaltreq", reset=Some(1))), RegField.r(1, DMSTATUSRdData.authbusy, RegFieldDesc("authbusy", "authbusy", reset=Some(0))), RegField.r(1, DMSTATUSRdData.authenticated, RegFieldDesc("authenticated", "authenticated", reset=Some(1))), RegField.r(1, DMSTATUSRdData.anyhalted, RegFieldDesc("anyhalted", "anyhalted", reset=Some(0))), RegField.r(1, DMSTATUSRdData.allhalted, RegFieldDesc("allhalted", "allhalted", reset=Some(0))), RegField.r(1, DMSTATUSRdData.anyrunning, RegFieldDesc("anyrunning", "anyrunning", reset=Some(1))), RegField.r(1, DMSTATUSRdData.allrunning, RegFieldDesc("allrunning", "allrunning", reset=Some(1))), RegField.r(1, DMSTATUSRdData.anyunavail, RegFieldDesc("anyunavail", "anyunavail", reset=Some(0))), RegField.r(1, DMSTATUSRdData.allunavail, RegFieldDesc("allunavail", "allunavail", reset=Some(0))), RegField.r(1, DMSTATUSRdData.anynonexistent, RegFieldDesc("anynonexistent", "anynonexistent", reset=Some(0))), RegField.r(1, DMSTATUSRdData.allnonexistent, RegFieldDesc("allnonexistent", "allnonexistent", reset=Some(0))), RegField.r(1, DMSTATUSRdData.anyresumeack, RegFieldDesc("anyresumeack", "anyresumeack", reset=Some(1))), RegField.r(1, DMSTATUSRdData.allresumeack, RegFieldDesc("allresumeack", "allresumeack", reset=Some(1))), RegField.r(1, DMSTATUSRdData.anyhavereset, RegFieldDesc("anyhavereset", "anyhavereset", reset=Some(0))), RegField.r(1, DMSTATUSRdData.allhavereset, RegFieldDesc("allhavereset", "allhavereset", reset=Some(0))), RegField(2), RegField.r(1, DMSTATUSRdData.impebreak, RegFieldDesc("impebreak", "impebreak", reset=Some(if (cfg.hasImplicitEbreak) 1 else 0))) )) val dmcs2RegFields = RegFieldGroup("dmi_dmcs2", Some("debug module control/status register 2"), Seq( WNotifyVal(1, DMCS2RdData.hgselect, DMCS2WrData.hgselect, hgselectWrEn, RegFieldDesc("hgselect", "select halt groups or external triggers", reset=Some(0), volatile=true)), WNotifyVal(1, 0.U, DMCS2WrData.hgwrite, hgwriteWrEn, RegFieldDesc("hgwrite", "write 1 to change halt groups", reset=None, access=RegFieldAccessType.W)), WNotifyVal(5, DMCS2RdData.haltgroup, DMCS2WrData.haltgroup, haltgroupWrEn, RegFieldDesc("haltgroup", "halt group", reset=Some(0), volatile=true)), if (nExtTriggers > 1) WNotifyVal(4, DMCS2RdData.exttrigger, DMCS2WrData.exttrigger, exttriggerWrEn, RegFieldDesc("exttrigger", "external trigger select", reset=Some(0), volatile=true)) else RegField(4) )) val abstractcsRegFields = RegFieldGroup("dmi_abstractcs", Some("abstract command control/status"), Seq( RegField.r(4, ABSTRACTCSRdData.datacount, RegFieldDesc("datacount", "number of DATA registers", reset=Some(cfg.nAbstractDataWords))), RegField(4), WNotifyVal(3, ABSTRACTCSRdData.cmderr, ABSTRACTCSWrData.cmderr, ABSTRACTCSWrEnMaybe, RegFieldDesc("cmderr", "command error", reset=Some(0), wrType=Some(RegFieldWrType.ONE_TO_CLEAR))), RegField(1), RegField.r(1, ABSTRACTCSRdData.busy, RegFieldDesc("busy", "busy", reset=Some(0))), RegField(11), RegField.r(5, ABSTRACTCSRdData.progbufsize, RegFieldDesc("progbufsize", "number of PROGBUF registers", reset=Some(cfg.nProgramBufferWords))) )) val (sbcsFields, sbAddrFields, sbDataFields): (Seq[RegField], Seq[Seq[RegField]], Seq[Seq[RegField]]) = sb2tlOpt.map{ sb2tl => SystemBusAccessModule(sb2tl, io.dmactive, dmAuthenticated)(p) }.getOrElse((Seq.empty[RegField], Seq.fill[Seq[RegField]](4)(Seq.empty[RegField]), Seq.fill[Seq[RegField]](4)(Seq.empty[RegField]))) //-------------------------------------------------------------- // Program Buffer Access (DMI ... System Bus can override) //-------------------------------------------------------------- val omRegMap = dmiNode.regmap( (DMI_DMSTATUS << 2) -> dmstatusRegFields, //TODO (DMI_CFGSTRADDR0 << 2) -> cfgStrAddrFields, (DMI_DMCS2 << 2) -> (if (nHaltGroups > 0) dmcs2RegFields else Nil), (DMI_HALTSUM0 << 2) -> RegFieldGroup("dmi_haltsum0", Some("Halt Summary 0"), Seq(RegField.r(32, HALTSUM0RdData.asUInt, RegFieldDesc("dmi_haltsum0", "halt summary 0")))), (DMI_HALTSUM1 << 2) -> RegFieldGroup("dmi_haltsum1", Some("Halt Summary 1"), Seq(RegField.r(32, HALTSUM1RdData.asUInt, RegFieldDesc("dmi_haltsum1", "halt summary 1")))), (DMI_ABSTRACTCS << 2) -> abstractcsRegFields, (DMI_ABSTRACTAUTO<< 2) -> RegFieldGroup("dmi_abstractauto", Some("abstract command autoexec"), Seq( WNotifyVal(cfg.nAbstractDataWords, ABSTRACTAUTORdData.autoexecdata, ABSTRACTAUTOWrData.autoexecdata, autoexecdataWrEnMaybe, RegFieldDesc("autoexecdata", "abstract command data autoexec", reset=Some(0))), RegField(16-cfg.nAbstractDataWords), WNotifyVal(cfg.nProgramBufferWords, ABSTRACTAUTORdData.autoexecprogbuf, ABSTRACTAUTOWrData.autoexecprogbuf, autoexecprogbufWrEnMaybe, RegFieldDesc("autoexecprogbuf", "abstract command progbuf autoexec", reset=Some(0))))), (DMI_COMMAND << 2) -> RegFieldGroup("dmi_command", Some("Abstract Command Register"), Seq(RWNotify(32, COMMANDRdData.asUInt, COMMANDWrDataVal, COMMANDRdEn, COMMANDWrEnMaybe, Some(RegFieldDesc("dmi_command", "abstract command register", reset=Some(0), volatile=true))))), (DMI_DATA0 << 2) -> RegFieldGroup("dmi_data", Some("abstract command data registers"), abstractDataMem.zipWithIndex.map{case (x, i) => RWNotify(8, Mux(dmAuthenticated, x, 0.U), abstractDataNxt(i), dmiAbstractDataRdEn(i), dmiAbstractDataWrEnMaybe(i), Some(RegFieldDesc(s"dmi_data_$i", s"abstract command data register $i", reset = Some(0), volatile=true)))}, false), (DMI_PROGBUF0 << 2) -> RegFieldGroup("dmi_progbuf", Some("abstract command progbuf registers"), programBufferMem.zipWithIndex.map{case (x, i) => RWNotify(8, Mux(dmAuthenticated, x, 0.U), programBufferNxt(i), dmiProgramBufferRdEn(i), dmiProgramBufferWrEnMaybe(i), Some(RegFieldDesc(s"dmi_progbuf_$i", s"abstract command progbuf register $i", reset = Some(0))))}, false), (DMI_AUTHDATA << 2) -> (if (cfg.hasAuthentication) RegFieldGroup("dmi_authdata", Some("authentication data exchange register"), Seq(RWNotify(32, io.auth.get.dmAuthRdata, io.auth.get.dmAuthWdata, authRdEnMaybe, authWrEnMaybe, Some(RegFieldDesc("authdata", "authentication data exchange", volatile=true))))) else Nil), (DMI_SBCS << 2) -> sbcsFields, (DMI_SBDATA0 << 2) -> sbDataFields(0), (DMI_SBDATA1 << 2) -> sbDataFields(1), (DMI_SBDATA2 << 2) -> sbDataFields(2), (DMI_SBDATA3 << 2) -> sbDataFields(3), (DMI_SBADDRESS0 << 2) -> sbAddrFields(0), (DMI_SBADDRESS1 << 2) -> sbAddrFields(1), (DMI_SBADDRESS2 << 2) -> sbAddrFields(2), (DMI_SBADDRESS3 << 2) -> sbAddrFields(3) ) // Abstract data mem is written by both the tile link interface and DMI... abstractDataMem.zipWithIndex.foreach { case (x, i) => when (dmAuthenticated && dmiAbstractDataWrEnMaybe(i) && dmiAbstractDataAccessLegal) { x := abstractDataNxt(i) } } // ... and also by custom register read (if implemented) val (customs, customParams) = customNode.in.unzip val needCustom = (customs.size > 0) && (customParams.head.addrs.size > 0) def getNeedCustom = () => needCustom if (needCustom) { val (custom, customP) = customNode.in.head require(customP.width % 8 == 0, s"Debug Custom width must be divisible by 8, not ${customP.width}") val custom_data = custom.data.asBools val custom_bytes = Seq.tabulate(customP.width/8){i => custom_data.slice(i8, (i+1)8).asUInt} when (custom.ready && custom.valid) { (abstractDataMem zip custom_bytes).zipWithIndex.foreach {case ((a, b), i) => a := b } } } programBufferMem.zipWithIndex.foreach { case (x, i) => when (dmAuthenticated && dmiProgramBufferWrEnMaybe(i) && dmiProgramBufferAccessLegal) { x := programBufferNxt(i) } } //-------------------------------------------------------------- // "Variable" ROM Generation //-------------------------------------------------------------- val goReg = Reg(Bool()) val goAbstract = WireInit(false.B) val goCustom = WireInit(false.B) val jalAbstract = WireInit(Instructions.JAL.value.U.asTypeOf(new GeneratedUJ())) jalAbstract.setImm(ABSTRACT(cfg) - WHERETO) when (~io.dmactive){ goReg := false.B }.otherwise { when (goAbstract) { goReg := true.B }.elsewhen (hartGoingWrEn){ assert(hartGoingId === 0.U, "Unexpected 'GOING' hart.")//Chisel3 #540 %x, expected %x", hartGoingId, 0.U) goReg := false.B } } class flagBundle extends Bundle { val reserved = UInt(6.W) val resume = Bool() val go = Bool() } val flags = WireInit(VecInit(Seq.fill(1 << selectedHartReg.getWidth) {0.U.asTypeOf(new flagBundle())} )) assert ((hartSelFuncs.hartSelToHartId(selectedHartReg) < flags.size.U), s"HartSel to HartId Mapping is illegal for this Debug Implementation, because HartID must be < ${flags.size} for it to work.") flags(hartSelFuncs.hartSelToHartId(selectedHartReg)).go := goReg for (component <- 0 until nComponents) { val componentSel = WireInit(component.U) flags(hartSelFuncs.hartSelToHartId(componentSel)).resume := resumeReqRegs(component) } //---------------------------- // Abstract Command Decoding & Generation //---------------------------- val accessRegisterCommandWr = WireInit(COMMANDWrData.asUInt.asTypeOf(new ACCESS_REGISTERFields())) /** real COMMAND/ val accessRegisterCommandReg = WireInit(COMMANDReg.asUInt.asTypeOf(new ACCESS_REGISTERFields())) // TODO: Quick Access class GeneratedI extends Bundle { val imm = UInt(12.W) val rs1 = UInt(5.W) val funct3 = UInt(3.W) val rd = UInt(5.W) val opcode = UInt(7.W) } class GeneratedS extends Bundle { val immhi = UInt(7.W) val rs2 = UInt(5.W) val rs1 = UInt(5.W) val funct3 = UInt(3.W) val immlo = UInt(5.W) val opcode = UInt(7.W) } class GeneratedCSR extends Bundle { val imm = UInt(12.W) val rs1 = UInt(5.W) val funct3 = UInt(3.W) val rd = UInt(5.W) val opcode = UInt(7.W) } class GeneratedUJ extends Bundle { val imm3 = UInt(1.W) val imm0 = UInt(10.W) val imm1 = UInt(1.W) val imm2 = UInt(8.W) val rd = UInt(5.W) val opcode = UInt(7.W) def setImm(imm: Int) : Unit = { // TODO: Check bounds of imm. require(imm % 2 == 0, "Immediate must be even for UJ encoding.") val immWire = WireInit(imm.S(21.W)) val immBits = WireInit(VecInit(immWire.asBools)) imm0 := immBits.slice(1, 1 + 10).asUInt imm1 := immBits.slice(11, 11 + 11).asUInt imm2 := immBits.slice(12, 12 + 8).asUInt imm3 := immBits.slice(20, 20 + 1).asUInt } } require((cfg.atzero && cfg.nAbstractInstructions == 2) \|\| (!cfg.atzero && cfg.nAbstractInstructions == 5), "Mismatch between DebugModuleParams atzero and nAbstractInstructions") val abstractGeneratedMem = Reg(Vec(cfg.nAbstractInstructions, (UInt(32.W)))) def abstractGeneratedI(cfg: DebugModuleParams): UInt = { val inst = Wire(new GeneratedI()) val offset = if (cfg.atzero) DATA else (DATA-0x800) & 0xFFF val base = if (cfg.atzero) 0.U else Mux(accessRegisterCommandReg.regno(0), 8.U, 9.U) inst.opcode := (Instructions.LW.value.U.asTypeOf(new GeneratedI())).opcode inst.rd := (accessRegisterCommandReg.regno & 0x1F.U) inst.funct3 := accessRegisterCommandReg.size inst.rs1 := base inst.imm := offset.U inst.asUInt } def abstractGeneratedS(cfg: DebugModuleParams): UInt = { val inst = Wire(new GeneratedS()) val offset = if (cfg.atzero) DATA else (DATA-0x800) & 0xFFF val base = if (cfg.atzero) 0.U else Mux(accessRegisterCommandReg.regno(0), 8.U, 9.U) inst.opcode := (Instructions.SW.value.U.asTypeOf(new GeneratedS())).opcode inst.immlo := (offset & 0x1F).U inst.funct3 := accessRegisterCommandReg.size inst.rs1 := base inst.rs2 := (accessRegisterCommandReg.regno & 0x1F.U) inst.immhi := (offset >> 5).U inst.asUInt } def abstractGeneratedCSR: UInt = { val inst = Wire(new GeneratedCSR()) val base = Mux(accessRegisterCommandReg.regno(0), 8.U, 9.U) // use s0 as base for odd regs, s1 as base for even regs inst := (Instructions.CSRRW.value.U.asTypeOf(new GeneratedCSR())) inst.imm := CSRs.dscratch1.U inst.rs1 := base inst.rd := base inst.asUInt } val nop = Wire(new GeneratedI()) nop := Instructions.ADDI.value.U.asTypeOf(new GeneratedI()) nop.rd := 0.U nop.rs1 := 0.U nop.imm := 0.U val isa = Wire(new GeneratedI()) isa := Instructions.ADDIW.value.U.asTypeOf(new GeneratedI()) isa.rd := 0.U isa.rs1 := 0.U isa.imm := 0.U when (goAbstract) { if (cfg.nAbstractInstructions == 2) { // ABSTRACT(0): Transfer: LW or SW, else NOP // ABSTRACT(1): Postexec: NOP else EBREAK abstractGeneratedMem(0) := Mux(accessRegisterCommandReg.transfer, Mux(accessRegisterCommandReg.write, abstractGeneratedI(cfg), abstractGeneratedS(cfg)), nop.asUInt ) abstractGeneratedMem(1) := Mux(accessRegisterCommandReg.postexec, nop.asUInt, Instructions.EBREAK.value.U) } else { // Entry: All regs in GPRs, dscratch1=offset 0x800 in DM // ABSTRACT(0): CheckISA: ADDW or NOP (exception here if size=3 and not RV64) // ABSTRACT(1): CSRRW s1,dscratch1,s1 or CSRRW s0,dscratch1,s0 // ABSTRACT(2): Transfer: LW, SW, LD, SD else NOP // ABSTRACT(3): CSRRW s1,dscratch1,s1 or CSRRW s0,dscratch1,s0 // ABSTRACT(4): Postexec: NOP else EBREAK abstractGeneratedMem(0) := Mux(accessRegisterCommandReg.transfer && accessRegisterCommandReg.size =/= 2.U, isa.asUInt, nop.asUInt) abstractGeneratedMem(1) := abstractGeneratedCSR abstractGeneratedMem(2) := Mux(accessRegisterCommandReg.transfer, Mux(accessRegisterCommandReg.write, abstractGeneratedI(cfg), abstractGeneratedS(cfg)), nop.asUInt ) abstractGeneratedMem(3) := abstractGeneratedCSR abstractGeneratedMem(4) := Mux(accessRegisterCommandReg.postexec, nop.asUInt, Instructions.EBREAK.value.U) } } //-------------------------------------------------------------- // Drive Custom Access //-------------------------------------------------------------- if (needCustom) { val (custom, customP) = customNode.in.head custom.addr := accessRegisterCommandReg.regno custom.valid := goCustom } //-------------------------------------------------------------- // Hart Bus Access //-------------------------------------------------------------- tlNode.regmap( // This memory is writable. HALTED -> Seq(WNotifyWire(sbIdWidth, hartHaltedId, hartHaltedWrEn, "debug_hart_halted", "Debug ROM Causes hart to write its hartID here when it is in Debug Mode.")), GOING -> Seq(WNotifyWire(sbIdWidth, hartGoingId, hartGoingWrEn, "debug_hart_going", "Debug ROM causes hart to write 0 here when it begins executing Debug Mode instructions.")), RESUMING -> Seq(WNotifyWire(sbIdWidth, hartResumingId, hartResumingWrEn, "debug_hart_resuming", "Debug ROM causes hart to write its hartID here when it leaves Debug Mode.")), EXCEPTION -> Seq(WNotifyWire(sbIdWidth, hartExceptionId, hartExceptionWrEn, "debug_hart_exception", "Debug ROM causes hart to write 0 here if it gets an exception in Debug Mode.")), DATA -> RegFieldGroup("debug_data", Some("Data used to communicate with Debug Module"), abstractDataMem.zipWithIndex.map {case (x, i) => RegField(8, x, RegFieldDesc(s"debug_data_$i", ""))}), PROGBUF(cfg)-> RegFieldGroup("debug_progbuf", Some("Program buffer used to communicate with Debug Module"), programBufferMem.zipWithIndex.map {case (x, i) => RegField(8, x, RegFieldDesc(s"debug_progbuf_$i", ""))}), // These sections are read-only. IMPEBREAK(cfg)-> {if (cfg.hasImplicitEbreak) Seq(RegField.r(32, Instructions.EBREAK.value.U, RegFieldDesc("debug_impebreak", "Debug Implicit EBREAK", reset=Some(Instructions.EBREAK.value)))) else Nil}, WHERETO -> Seq(RegField.r(32, jalAbstract.asUInt, RegFieldDesc("debug_whereto", "Instruction filled in by Debug Module to control hart in Debug Mode", volatile = true))), ABSTRACT(cfg) -> RegFieldGroup("debug_abstract", Some("Instructions generated by Debug Module"), abstractGeneratedMem.zipWithIndex.map{ case (x,i) => RegField.r(32, x, RegFieldDesc(s"debug_abstract_$i", "", volatile=true))}), FLAGS -> RegFieldGroup("debug_flags", Some("Memory region used to control hart going/resuming in Debug Mode"), if (nComponents == 1) { Seq.tabulate(1024) { i => RegField.r(8, flags(0).asUInt, RegFieldDesc(s"debug_flags_$i", "", volatile=true)) } } else { flags.zipWithIndex.map{case(x, i) => RegField.r(8, x.asUInt, RegFieldDesc(s"debug_flags_$i", "", volatile=true))} }), ROMBASE -> RegFieldGroup("debug_rom", Some("Debug ROM"), (if (cfg.atzero) DebugRomContents() else DebugRomNonzeroContents()).zipWithIndex.map{case (x, i) => RegField.r(8, (x & 0xFF).U(8.W), RegFieldDesc(s"debug_rom_$i", "", reset=Some(x)))}) ) // Override System Bus accesses with dmactive reset. when (~io.dmactive){ abstractDataMem.foreach {x => x := 0.U} programBufferMem.foreach {x => x := 0.U} } //-------------------------------------------------------------- // Abstract Command State Machine //-------------------------------------------------------------- object CtrlState extends scala.Enumeration { type CtrlState = Value val Waiting, CheckGenerate, Exec, Custom = Value def apply( t : Value) : UInt = { t.id.U(log2Up(values.size).W) } } import CtrlState._ // This is not an initialization! val ctrlStateReg = Reg(chiselTypeOf(CtrlState(Waiting))) val hartHalted = haltedBitRegs(if (nComponents == 1) 0.U(0.W) else selectedHartReg) val ctrlStateNxt = WireInit(ctrlStateReg) //------------------------ // DMI Register Control and Status abstractCommandBusy := (ctrlStateReg =/= CtrlState(Waiting)) ABSTRACTCSWrEnLegal := (ctrlStateReg === CtrlState(Waiting)) COMMANDWrEnLegal := (ctrlStateReg === CtrlState(Waiting)) ABSTRACTAUTOWrEnLegal := (ctrlStateReg === CtrlState(Waiting)) dmiAbstractDataAccessLegal := (ctrlStateReg === CtrlState(Waiting)) dmiProgramBufferAccessLegal := (ctrlStateReg === CtrlState(Waiting)) errorBusy := (ABSTRACTCSWrEnMaybe && ~ABSTRACTCSWrEnLegal) \|\| (autoexecdataWrEnMaybe && ~ABSTRACTAUTOWrEnLegal) \|\| (autoexecprogbufWrEnMaybe && ~ABSTRACTAUTOWrEnLegal) \|\| (COMMANDWrEnMaybe && ~COMMANDWrEnLegal) \|\| (dmiAbstractDataAccess && ~dmiAbstractDataAccessLegal) \|\| (dmiProgramBufferAccess && ~dmiProgramBufferAccessLegal) // TODO: Maybe Quick Access val commandWrIsAccessRegister = (COMMANDWrData.cmdtype === DebugAbstractCommandType.AccessRegister.id.U) val commandRegIsAccessRegister = (COMMANDReg.cmdtype === DebugAbstractCommandType.AccessRegister.id.U) val commandWrIsUnsupported = COMMANDWrEn && !commandWrIsAccessRegister val commandRegIsUnsupported = WireInit(true.B) val commandRegBadHaltResume = WireInit(false.B) // We only support abstract commands for GPRs and any custom registers, if specified. val accessRegIsLegalSize = (accessRegisterCommandReg.size === 2.U) \|\| (accessRegisterCommandReg.size === 3.U) val accessRegIsGPR = (accessRegisterCommandReg.regno >= 0x1000.U && accessRegisterCommandReg.regno <= 0x101F.U) && accessRegIsLegalSize val accessRegIsCustom = if (needCustom) { val (custom, customP) = customNode.in.head customP.addrs.foldLeft(false.B){ (result, current) => result \|\| (current.U === accessRegisterCommandReg.regno)} } else false.B when (commandRegIsAccessRegister) { when (accessRegIsCustom && accessRegisterCommandReg.transfer && accessRegisterCommandReg.write === false.B) { commandRegIsUnsupported := false.B }.elsewhen (!accessRegisterCommandReg.transfer \|\| accessRegIsGPR) { commandRegIsUnsupported := false.B commandRegBadHaltResume := ~hartHalted } } val wrAccessRegisterCommand = COMMANDWrEn && commandWrIsAccessRegister && (ABSTRACTCSReg.cmderr === 0.U) val regAccessRegisterCommand = autoexec && commandRegIsAccessRegister && (ABSTRACTCSReg.cmderr === 0.U) //------------------------ // Variable ROM STATE MACHINE // ----------------------- when (ctrlStateReg === CtrlState(Waiting)){ when (wrAccessRegisterCommand \|\| regAccessRegisterCommand) { ctrlStateNxt := CtrlState(CheckGenerate) }.elsewhen (commandWrIsUnsupported) { // These checks are really on the command type. errorUnsupported := true.B }.elsewhen (autoexec && commandRegIsUnsupported) { errorUnsupported := true.B } }.elsewhen (ctrlStateReg === CtrlState(CheckGenerate)){ // We use this state to ensure that the COMMAND has been // registered by the time that we need to use it, to avoid // generating it directly from the COMMANDWrData. // This 'commandRegIsUnsupported' is really just checking the // AccessRegisterCommand parameters (regno) when (commandRegIsUnsupported) { errorUnsupported := true.B ctrlStateNxt := CtrlState(Waiting) }.elsewhen (commandRegBadHaltResume){ errorHaltResume := true.B ctrlStateNxt := CtrlState(Waiting) }.otherwise { when(accessRegIsCustom) { ctrlStateNxt := CtrlState(Custom) }.otherwise { ctrlStateNxt := CtrlState(Exec) goAbstract := true.B } } }.elsewhen (ctrlStateReg === CtrlState(Exec)) { // We can't just look at 'hartHalted' here, because // hartHaltedWrEn is overloaded to mean 'got an ebreak' // which may have happened when we were already halted. when(goReg === false.B && hartHaltedWrEn && (hartSelFuncs.hartIdToHartSel(hartHaltedId) === selectedHartReg)){ ctrlStateNxt := CtrlState(Waiting) } when(hartExceptionWrEn) { assert(hartExceptionId === 0.U, "Unexpected 'EXCEPTION' hart")//Chisel3 #540, %x, expected %x", hartExceptionId, 0.U) ctrlStateNxt := CtrlState(Waiting) errorException := true.B } }.elsewhen (ctrlStateReg === CtrlState(Custom)) { assert(needCustom.B, "Should not be in custom state unless we need it.") goCustom := true.B val (custom, customP) = customNode.in.head when (custom.ready && custom.valid) { ctrlStateNxt := CtrlState(Waiting) } } when (~io.dmactive \|\| ~dmAuthenticated) { ctrlStateReg := CtrlState(Waiting) }.otherwise { ctrlStateReg := ctrlStateNxt } assert ((!io.dmactive \|\| !hartExceptionWrEn \|\| ctrlStateReg === CtrlState(Exec)), "Unexpected EXCEPTION write: should only get it in Debug Module EXEC state") } } // Wrapper around TL Debug Module Inner and an Async DMI Sink interface. // Handles the synchronization of dmactive, which is used as a synchronous reset // inside the Inner block. // Also is the Sink side of hartsel & resumereq fields of DMCONTROL. class TLDebugModuleInnerAsync(device: Device, getNComponents: () => Int, beatBytes: Int)(implicit p: Parameters) extends LazyModule{ val cfg = p(DebugModuleKey).get val dmInner = LazyModule(new TLDebugModuleInner(device, getNComponents, beatBytes)) val dmiXing = LazyModule(new TLAsyncCrossingSink(AsyncQueueParams.singleton(safe=cfg.crossingHasSafeReset))) val dmiNode = dmiXing.node val tlNode = dmInner.tlNode dmInner.dmiNode := dmiXing.node // Require that there are no registers in TL interface, so that spurious // processor accesses to the DM don't need to enable the clock. We don't // require this property of the SBA, because the debugger is responsible for // raising dmactive (hence enabling the clock) during these transactions. require(dmInner.tlNode.concurrency == 0) lazy val module = new Impl class Impl extends LazyRawModuleImp(this) { // Clock/reset domains: // debug_clock / debug_reset = Debug inner domain // tl_clock / tl_reset = tilelink domain (External: clock / reset) // val io = IO(new Bundle { val debug_clock = Input(Clock()) val debug_reset = Input(Reset()) val tl_clock = Input(Clock()) val tl_reset = Input(Reset()) // These are all asynchronous and come from Outer /* reset signal for DM / val dmactive = Input(Bool()) /* conrol signals for Inner * * generated in Outer / val innerCtrl = Flipped(new AsyncBundle(new DebugInternalBundle(getNComponents()), AsyncQueueParams.singleton(safe=cfg.crossingHasSafeReset))) // This comes from tlClk domain. /* debug available status / val debugUnavail = Input(Vec(getNComponents(), Bool())) /* debug interruption/ val hgDebugInt = Output(Vec(getNComponents(), Bool())) val extTrigger = (p(DebugModuleKey).get.nExtTriggers > 0).option(new DebugExtTriggerIO()) /* vector to indicate which hart is in reset * * dm receives it from core and sends it to Inner / val hartIsInReset = Input(Vec(getNComponents(), Bool())) /* Debug Authentication signals from core / val auth = p(DebugModuleKey).get.hasAuthentication.option(new DebugAuthenticationIO()) }) val rf_reset = IO(Input(Reset())) // RF transform childClock := io.debug_clock childReset := io.debug_reset override def provideImplicitClockToLazyChildren = true val dmactive_synced = withClockAndReset(childClock, childReset) { val dmactive_synced = AsyncResetSynchronizerShiftReg(in=io.dmactive, sync=3, name=Some("dmactiveSync")) dmInner.module.clock := io.debug_clock dmInner.module.reset := io.debug_reset dmInner.module.io.tl_clock := io.tl_clock dmInner.module.io.tl_reset := io.tl_reset dmInner.module.io.dmactive := dmactive_synced dmInner.module.io.innerCtrl <> FromAsyncBundle(io.innerCtrl) dmInner.module.io.debugUnavail := io.debugUnavail io.hgDebugInt := dmInner.module.io.hgDebugInt io.extTrigger.foreach { x => dmInner.module.io.extTrigger.foreach {y => x <> y}} dmInner.module.io.hartIsInReset := io.hartIsInReset io.auth.foreach { x => dmInner.module.io.auth.foreach {y => x <> y}} dmactive_synced } } } /* Create a version of the TLDebugModule which includes a synchronization interface * internally for the DMI. This is no longer optional outside of this module * because the Clock must run when tl_clock isn't running or tl_reset is asserted. / class TLDebugModule(beatBytes: Int)(implicit p: Parameters) extends LazyModule { val device = new SimpleDevice("debug-controller", Seq("sifive,debug-013","riscv,debug-013")){ override val alwaysExtended = true override def describe(resources: ResourceBindings): Description = { val Description(name, mapping) = super.describe(resources) val attach = Map( "debug-attach" -> ( (if (p(ExportDebug).apb) Seq(ResourceString("apb")) else Seq()) ++ (if (p(ExportDebug).jtag) Seq(ResourceString("jtag")) else Seq()) ++ (if (p(ExportDebug).cjtag) Seq(ResourceString("cjtag")) else Seq()) ++ (if (p(ExportDebug).dmi) Seq(ResourceString("dmi")) else Seq()))) Description(name, mapping ++ attach) } } val dmOuter : TLDebugModuleOuterAsync = LazyModule(new TLDebugModuleOuterAsync(device)(p)) val dmInner : TLDebugModuleInnerAsync = LazyModule(new TLDebugModuleInnerAsync(device, () => {dmOuter.dmOuter.intnode.edges.out.size}, beatBytes)(p)) val node = dmInner.tlNode val intnode = dmOuter.intnode val apbNodeOpt = dmOuter.apbNodeOpt dmInner.dmiNode := dmOuter.dmiInnerNode lazy val module = new Impl class Impl extends LazyRawModuleImp(this) { val nComponents = dmOuter.dmOuter.intnode.edges.out.size // Clock/reset domains: // tl_clock / tl_reset = tilelink domain // debug_clock / debug_reset = Inner debug (synchronous to tl_clock) // apb_clock / apb_reset = Outer debug with APB // dmiClock / dmiReset = Outer debug without APB // val io = IO(new Bundle { val debug_clock = Input(Clock()) val debug_reset = Input(Reset()) val tl_clock = Input(Clock()) val tl_reset = Input(Reset()) /* Debug control signals generated in Outer / val ctrl = new DebugCtrlBundle(nComponents) /* Debug Module Interface bewteen DM and DTM * * The DTM provides access to one or more Debug Modules (DMs) using DMI / val dmi = (!p(ExportDebug).apb).option(Flipped(new ClockedDMIIO())) val apb_clock = p(ExportDebug).apb.option(Input(Clock())) val apb_reset = p(ExportDebug).apb.option(Input(Reset())) val extTrigger = (p(DebugModuleKey).get.nExtTriggers > 0).option(new DebugExtTriggerIO()) /* vector to indicate which hart is in reset * * dm receives it from core and sends it to Inner / val hartIsInReset = Input(Vec(nComponents, Bool())) /* hart reset request generated by hartreset-logic in Outer / val hartResetReq = p(DebugModuleKey).get.hasHartResets.option(Output(Vec(nComponents, Bool()))) /* Debug Authentication signals from core */ val auth = p(DebugModuleKey).get.hasAuthentication.option(new DebugAuthenticationIO()) }) childClock := io.tl_clock childReset := io.tl_reset override def provideImplicitClockToLazyChildren = true dmOuter.module.io.dmi.foreach { dmOuterDMI => dmOuterDMI <> io.dmi.get.dmi dmOuter.module.io.dmi_reset := io.dmi.get.dmiReset dmOuter.module.io.dmi_clock := io.dmi.get.dmiClock dmOuter.module.rf_reset := io.dmi.get.dmiReset } (io.apb_clock zip io.apb_reset) foreach { case (c, r) => dmOuter.module.io.dmi_reset := r dmOuter.module.io.dmi_clock := c dmOuter.module.rf_reset := r } dmInner.module.rf_reset := io.debug_reset dmInner.module.io.debug_clock := io.debug_clock dmInner.module.io.debug_reset := io.debug_reset dmInner.module.io.tl_clock := io.tl_clock dmInner.module.io.tl_reset := io.tl_reset dmInner.module.io.innerCtrl <> dmOuter.module.io.innerCtrl dmInner.module.io.dmactive := dmOuter.module.io.ctrl.dmactive dmInner.module.io.debugUnavail := io.ctrl.debugUnavail dmOuter.module.io.hgDebugInt := dmInner.module.io.hgDebugInt io.ctrl <> dmOuter.module.io.ctrl io.extTrigger.foreach { x => dmInner.module.io.extTrigger.foreach {y => x <> y}} dmInner.module.io.hartIsInReset := io.hartIsInReset io.hartResetReq.foreach { x => dmOuter.module.io.hartResetReq.foreach {y => x := y}} io.auth.foreach { x => dmOuter.module.io.dmAuthenticated.get := x.dmAuthenticated } io.auth.foreach { x => dmInner.module.io.auth.foreach {y => x <> y}} } }	module TLDebugModuleInnerAsync( // @[Debug.scala:1871:9] input [2:0] auto_dmiXing_in_a_mem_0_opcode, // @[LazyModuleImp.scala:107:25] input [8:0] auto_dmiXing_in_a_mem_0_address, // @[LazyModuleImp.scala:107:25] input [31:0] auto_dmiXing_in_a_mem_0_data, // @[LazyModuleImp.scala:107:25] output auto_dmiXing_in_a_ridx, // @[LazyModuleImp.scala:107:25] input auto_dmiXing_in_a_widx, // @[LazyModuleImp.scala:107:25] output auto_dmiXing_in_a_safe_ridx_valid, // @[LazyModuleImp.scala:107:25] input auto_dmiXing_in_a_safe_widx_valid, // @[LazyModuleImp.scala:107:25] input auto_dmiXing_in_a_safe_source_reset_n, // @[LazyModuleImp.scala:107:25] output auto_dmiXing_in_a_safe_sink_reset_n, // @[LazyModuleImp.scala:107:25] output [2:0] auto_dmiXing_in_d_mem_0_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_dmiXing_in_d_mem_0_size, // @[LazyModuleImp.scala:107:25] output auto_dmiXing_in_d_mem_0_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_dmiXing_in_d_mem_0_data, // @[LazyModuleImp.scala:107:25] input auto_dmiXing_in_d_ridx, // @[LazyModuleImp.scala:107:25] output auto_dmiXing_in_d_widx, // @[LazyModuleImp.scala:107:25] input auto_dmiXing_in_d_safe_ridx_valid, // @[LazyModuleImp.scala:107:25] output auto_dmiXing_in_d_safe_widx_valid, // @[LazyModuleImp.scala:107:25] output auto_dmiXing_in_d_safe_source_reset_n, // @[LazyModuleImp.scala:107:25] input auto_dmiXing_in_d_safe_sink_reset_n, // @[LazyModuleImp.scala:107:25] input auto_dmInner_sb2tlOpt_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_dmInner_sb2tlOpt_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_dmInner_sb2tlOpt_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [3:0] auto_dmInner_sb2tlOpt_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [31:0] auto_dmInner_sb2tlOpt_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_dmInner_sb2tlOpt_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_dmInner_sb2tlOpt_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_dmInner_sb2tlOpt_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_dmInner_sb2tlOpt_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_dmInner_sb2tlOpt_out_d_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_dmInner_sb2tlOpt_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [6:0] auto_dmInner_sb2tlOpt_out_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_dmInner_sb2tlOpt_out_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [7:0] auto_dmInner_sb2tlOpt_out_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_dmInner_sb2tlOpt_out_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_dmInner_tl_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_dmInner_tl_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_dmInner_tl_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_dmInner_tl_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [1:0] auto_dmInner_tl_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [10:0] auto_dmInner_tl_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [11:0] auto_dmInner_tl_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_dmInner_tl_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_dmInner_tl_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_dmInner_tl_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_dmInner_tl_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_dmInner_tl_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_dmInner_tl_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_dmInner_tl_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [10:0] auto_dmInner_tl_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output [63:0] auto_dmInner_tl_in_d_bits_data, // @[LazyModuleImp.scala:107:25] input io_debug_clock, // @[Debug.scala:1877:16] input io_debug_reset, // @[Debug.scala:1877:16] input io_tl_clock, // @[Debug.scala:1877:16] input io_tl_reset, // @[Debug.scala:1877:16] input io_dmactive, // @[Debug.scala:1877:16] input io_innerCtrl_mem_0_resumereq, // @[Debug.scala:1877:16] input [9:0] io_innerCtrl_mem_0_hartsel, // @[Debug.scala:1877:16] input io_innerCtrl_mem_0_ackhavereset, // @[Debug.scala:1877:16] input io_innerCtrl_mem_0_hrmask_0, // @[Debug.scala:1877:16] output io_innerCtrl_ridx, // @[Debug.scala:1877:16] input io_innerCtrl_widx, // @[Debug.scala:1877:16] output io_innerCtrl_safe_ridx_valid, // @[Debug.scala:1877:16] input io_innerCtrl_safe_widx_valid, // @[Debug.scala:1877:16] input io_innerCtrl_safe_source_reset_n, // @[Debug.scala:1877:16] output io_innerCtrl_safe_sink_reset_n, // @[Debug.scala:1877:16] output io_hgDebugInt_0, // @[Debug.scala:1877:16] input io_hartIsInReset_0, // @[Debug.scala:1877:16] input rf_reset // @[Debug.scala:1904:22] ); wire _dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_valid; // @[AsyncQueue.scala:211:22] wire _dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_bits_resumereq; // @[AsyncQueue.scala:211:22] wire [9:0] _dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_bits_hartsel; // @[AsyncQueue.scala:211:22] wire _dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_bits_ackhavereset; // @[AsyncQueue.scala:211:22] wire _dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_bits_hasel; // @[AsyncQueue.scala:211:22] wire _dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_bits_hamask_0; // @[AsyncQueue.scala:211:22] wire _dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_bits_hrmask_0; // @[AsyncQueue.scala:211:22] wire _dmiXing_auto_out_a_valid; // @[Debug.scala:1858:27] wire [2:0] _dmiXing_auto_out_a_bits_opcode; // @[Debug.scala:1858:27] wire [2:0] _dmiXing_auto_out_a_bits_param; // @[Debug.scala:1858:27] wire [1:0] _dmiXing_auto_out_a_bits_size; // @[Debug.scala:1858:27] wire _dmiXing_auto_out_a_bits_source; // @[Debug.scala:1858:27] wire [8:0] _dmiXing_auto_out_a_bits_address; // @[Debug.scala:1858:27] wire [3:0] _dmiXing_auto_out_a_bits_mask; // @[Debug.scala:1858:27] wire [31:0] _dmiXing_auto_out_a_bits_data; // @[Debug.scala:1858:27] wire _dmiXing_auto_out_a_bits_corrupt; // @[Debug.scala:1858:27] wire _dmiXing_auto_out_d_ready; // @[Debug.scala:1858:27] wire _dmInner_auto_dmi_in_a_ready; // @[Debug.scala:1857:27] wire _dmInner_auto_dmi_in_d_valid; // @[Debug.scala:1857:27] wire [2:0] _dmInner_auto_dmi_in_d_bits_opcode; // @[Debug.scala:1857:27] wire [1:0] _dmInner_auto_dmi_in_d_bits_size; // @[Debug.scala:1857:27] wire _dmInner_auto_dmi_in_d_bits_source; // @[Debug.scala:1857:27] wire [31:0] _dmInner_auto_dmi_in_d_bits_data; // @[Debug.scala:1857:27] wire [2:0] auto_dmiXing_in_a_mem_0_opcode_0 = auto_dmiXing_in_a_mem_0_opcode; // @[Debug.scala:1871:9] wire [8:0] auto_dmiXing_in_a_mem_0_address_0 = auto_dmiXing_in_a_mem_0_address; // @[Debug.scala:1871:9] wire [31:0] auto_dmiXing_in_a_mem_0_data_0 = auto_dmiXing_in_a_mem_0_data; // @[Debug.scala:1871:9] wire auto_dmiXing_in_a_widx_0 = auto_dmiXing_in_a_widx; // @[Debug.scala:1871:9] wire auto_dmiXing_in_a_safe_widx_valid_0 = auto_dmiXing_in_a_safe_widx_valid; // @[Debug.scala:1871:9] wire auto_dmiXing_in_a_safe_source_reset_n_0 = auto_dmiXing_in_a_safe_source_reset_n; // @[Debug.scala:1871:9] wire auto_dmiXing_in_d_ridx_0 = auto_dmiXing_in_d_ridx; // @[Debug.scala:1871:9] wire auto_dmiXing_in_d_safe_ridx_valid_0 = auto_dmiXing_in_d_safe_ridx_valid; // @[Debug.scala:1871:9] wire auto_dmiXing_in_d_safe_sink_reset_n_0 = auto_dmiXing_in_d_safe_sink_reset_n; // @[Debug.scala:1871:9] wire auto_dmInner_sb2tlOpt_out_a_ready_0 = auto_dmInner_sb2tlOpt_out_a_ready; // @[Debug.scala:1871:9] wire auto_dmInner_sb2tlOpt_out_d_valid_0 = auto_dmInner_sb2tlOpt_out_d_valid; // @[Debug.scala:1871:9] wire [2:0] auto_dmInner_sb2tlOpt_out_d_bits_opcode_0 = auto_dmInner_sb2tlOpt_out_d_bits_opcode; // @[Debug.scala:1871:9] wire [1:0] auto_dmInner_sb2tlOpt_out_d_bits_param_0 = auto_dmInner_sb2tlOpt_out_d_bits_param; // @[Debug.scala:1871:9] wire [3:0] auto_dmInner_sb2tlOpt_out_d_bits_size_0 = auto_dmInner_sb2tlOpt_out_d_bits_size; // @[Debug.scala:1871:9] wire [6:0] auto_dmInner_sb2tlOpt_out_d_bits_sink_0 = auto_dmInner_sb2tlOpt_out_d_bits_sink; // @[Debug.scala:1871:9] wire auto_dmInner_sb2tlOpt_out_d_bits_denied_0 = auto_dmInner_sb2tlOpt_out_d_bits_denied; // @[Debug.scala:1871:9] wire [7:0] auto_dmInner_sb2tlOpt_out_d_bits_data_0 = auto_dmInner_sb2tlOpt_out_d_bits_data; // @[Debug.scala:1871:9] wire auto_dmInner_sb2tlOpt_out_d_bits_corrupt_0 = auto_dmInner_sb2tlOpt_out_d_bits_corrupt; // @[Debug.scala:1871:9] wire auto_dmInner_tl_in_a_valid_0 = auto_dmInner_tl_in_a_valid; // @[Debug.scala:1871:9] wire [2:0] auto_dmInner_tl_in_a_bits_opcode_0 = auto_dmInner_tl_in_a_bits_opcode; // @[Debug.scala:1871:9] wire [2:0] auto_dmInner_tl_in_a_bits_param_0 = auto_dmInner_tl_in_a_bits_param; // @[Debug.scala:1871:9] wire [1:0] auto_dmInner_tl_in_a_bits_size_0 = auto_dmInner_tl_in_a_bits_size; // @[Debug.scala:1871:9] wire [10:0] auto_dmInner_tl_in_a_bits_source_0 = auto_dmInner_tl_in_a_bits_source; // @[Debug.scala:1871:9] wire [11:0] auto_dmInner_tl_in_a_bits_address_0 = auto_dmInner_tl_in_a_bits_address; // @[Debug.scala:1871:9] wire [7:0] auto_dmInner_tl_in_a_bits_mask_0 = auto_dmInner_tl_in_a_bits_mask; // @[Debug.scala:1871:9] wire [63:0] auto_dmInner_tl_in_a_bits_data_0 = auto_dmInner_tl_in_a_bits_data; // @[Debug.scala:1871:9] wire auto_dmInner_tl_in_a_bits_corrupt_0 = auto_dmInner_tl_in_a_bits_corrupt; // @[Debug.scala:1871:9] wire auto_dmInner_tl_in_d_ready_0 = auto_dmInner_tl_in_d_ready; // @[Debug.scala:1871:9] wire io_debug_clock_0 = io_debug_clock; // @[Debug.scala:1871:9] wire io_debug_reset_0 = io_debug_reset; // @[Debug.scala:1871:9] wire io_tl_clock_0 = io_tl_clock; // @[Debug.scala:1871:9] wire io_tl_reset_0 = io_tl_reset; // @[Debug.scala:1871:9] wire io_dmactive_0 = io_dmactive; // @[Debug.scala:1871:9] wire io_innerCtrl_mem_0_resumereq_0 = io_innerCtrl_mem_0_resumereq; // @[Debug.scala:1871:9] wire [9:0] io_innerCtrl_mem_0_hartsel_0 = io_innerCtrl_mem_0_hartsel; // @[Debug.scala:1871:9] wire io_innerCtrl_mem_0_ackhavereset_0 = io_innerCtrl_mem_0_ackhavereset; // @[Debug.scala:1871:9] wire io_innerCtrl_mem_0_hrmask_0_0 = io_innerCtrl_mem_0_hrmask_0; // @[Debug.scala:1871:9] wire io_innerCtrl_widx_0 = io_innerCtrl_widx; // @[Debug.scala:1871:9] wire io_innerCtrl_safe_widx_valid_0 = io_innerCtrl_safe_widx_valid; // @[Debug.scala:1871:9] wire io_innerCtrl_safe_source_reset_n_0 = io_innerCtrl_safe_source_reset_n; // @[Debug.scala:1871:9] wire io_hartIsInReset_0_0 = io_hartIsInReset_0; // @[Debug.scala:1871:9] wire auto_dmiXing_in_a_mem_0_source = 1'h0; // @[Debug.scala:1871:9] wire auto_dmiXing_in_a_mem_0_corrupt = 1'h0; // @[Debug.scala:1871:9] wire auto_dmiXing_in_b_mem_0_source = 1'h0; // @[Debug.scala:1871:9] wire auto_dmiXing_in_b_mem_0_corrupt = 1'h0; // @[Debug.scala:1871:9] wire auto_dmiXing_in_b_ridx = 1'h0; // @[Debug.scala:1871:9] wire auto_dmiXing_in_b_widx = 1'h0; // @[Debug.scala:1871:9] wire auto_dmiXing_in_b_safe_ridx_valid = 1'h0; // @[Debug.scala:1871:9] wire auto_dmiXing_in_b_safe_widx_valid = 1'h0; // @[Debug.scala:1871:9] wire auto_dmiXing_in_b_safe_source_reset_n = 1'h0; // @[Debug.scala:1871:9] wire auto_dmiXing_in_b_safe_sink_reset_n = 1'h0; // @[Debug.scala:1871:9] wire auto_dmiXing_in_c_mem_0_source = 1'h0; // @[Debug.scala:1871:9] wire auto_dmiXing_in_c_mem_0_corrupt = 1'h0; // @[Debug.scala:1871:9] wire auto_dmiXing_in_c_ridx = 1'h0; // @[Debug.scala:1871:9] wire auto_dmiXing_in_c_widx = 1'h0; // @[Debug.scala:1871:9] wire auto_dmiXing_in_c_safe_ridx_valid = 1'h0; // @[Debug.scala:1871:9] wire auto_dmiXing_in_c_safe_widx_valid = 1'h0; // @[Debug.scala:1871:9] wire auto_dmiXing_in_c_safe_source_reset_n = 1'h0; // @[Debug.scala:1871:9] wire auto_dmiXing_in_c_safe_sink_reset_n = 1'h0; // @[Debug.scala:1871:9] wire auto_dmiXing_in_d_mem_0_sink = 1'h0; // @[Debug.scala:1871:9] wire auto_dmiXing_in_d_mem_0_denied = 1'h0; // @[Debug.scala:1871:9] wire auto_dmiXing_in_d_mem_0_corrupt = 1'h0; // @[Debug.scala:1871:9] wire auto_dmiXing_in_e_mem_0_sink = 1'h0; // @[Debug.scala:1871:9] wire auto_dmiXing_in_e_ridx = 1'h0; // @[Debug.scala:1871:9] wire auto_dmiXing_in_e_widx = 1'h0; // @[Debug.scala:1871:9] wire auto_dmiXing_in_e_safe_ridx_valid = 1'h0; // @[Debug.scala:1871:9] wire auto_dmiXing_in_e_safe_widx_valid = 1'h0; // @[Debug.scala:1871:9] wire auto_dmiXing_in_e_safe_source_reset_n = 1'h0; // @[Debug.scala:1871:9] wire auto_dmiXing_in_e_safe_sink_reset_n = 1'h0; // @[Debug.scala:1871:9] wire auto_dmInner_sb2tlOpt_out_a_bits_source = 1'h0; // @[Debug.scala:1871:9] wire auto_dmInner_sb2tlOpt_out_a_bits_corrupt = 1'h0; // @[Debug.scala:1871:9] wire auto_dmInner_sb2tlOpt_out_d_bits_source = 1'h0; // @[Debug.scala:1871:9] wire auto_dmInner_custom_in_addr = 1'h0; // @[Debug.scala:1871:9] wire auto_dmInner_custom_in_ready = 1'h0; // @[Debug.scala:1871:9] wire auto_dmInner_custom_in_valid = 1'h0; // @[Debug.scala:1871:9] wire auto_dmInner_tl_in_d_bits_sink = 1'h0; // @[Debug.scala:1871:9] wire auto_dmInner_tl_in_d_bits_denied = 1'h0; // @[Debug.scala:1871:9] wire auto_dmInner_tl_in_d_bits_corrupt = 1'h0; // @[Debug.scala:1871:9] wire io_innerCtrl_mem_0_hasel = 1'h0; // @[Debug.scala:1871:9] wire io_innerCtrl_mem_0_hamask_0 = 1'h0; // @[Debug.scala:1871:9] wire io_debugUnavail_0 = 1'h0; // @[Debug.scala:1871:9] wire _childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25] wire auto_dmInner_sb2tlOpt_out_a_bits_mask = 1'h1; // @[AsyncQueue.scala:211:22] wire [31:0] auto_dmiXing_in_b_mem_0_data = 32'h0; // @[Debug.scala:1858:27, :1871:9] wire [31:0] auto_dmiXing_in_c_mem_0_data = 32'h0; // @[Debug.scala:1858:27, :1871:9] wire [3:0] auto_dmiXing_in_b_mem_0_mask = 4'h0; // @[Debug.scala:1858:27, :1871:9] wire [8:0] auto_dmiXing_in_b_mem_0_address = 9'h0; // @[Debug.scala:1858:27, :1871:9] wire [8:0] auto_dmiXing_in_c_mem_0_address = 9'h0; // @[Debug.scala:1858:27, :1871:9] wire [1:0] auto_dmiXing_in_b_mem_0_param = 2'h0; // @[Debug.scala:1871:9] wire [1:0] auto_dmiXing_in_b_mem_0_size = 2'h0; // @[Debug.scala:1871:9] wire [1:0] auto_dmiXing_in_c_mem_0_size = 2'h0; // @[Debug.scala:1871:9] wire [1:0] auto_dmiXing_in_d_mem_0_param = 2'h0; // @[Debug.scala:1871:9] wire [1:0] auto_dmInner_tl_in_d_bits_param = 2'h0; // @[Debug.scala:1871:9] wire [3:0] auto_dmiXing_in_a_mem_0_mask = 4'hF; // @[Debug.scala:1858:27, :1871:9] wire [1:0] auto_dmiXing_in_a_mem_0_size = 2'h2; // @[Debug.scala:1858:27, :1871:9] wire [2:0] auto_dmiXing_in_a_mem_0_param = 3'h0; // @[Debug.scala:1871:9] wire [2:0] auto_dmiXing_in_b_mem_0_opcode = 3'h0; // @[Debug.scala:1871:9] wire [2:0] auto_dmiXing_in_c_mem_0_opcode = 3'h0; // @[Debug.scala:1871:9] wire [2:0] auto_dmiXing_in_c_mem_0_param = 3'h0; // @[Debug.scala:1871:9] wire [2:0] auto_dmInner_sb2tlOpt_out_a_bits_param = 3'h0; // @[Debug.scala:1871:9] wire childClock = io_debug_clock_0; // @[Debug.scala:1871:9] wire childReset = io_debug_reset_0; // @[Debug.scala:1871:9] wire auto_dmiXing_in_a_safe_ridx_valid_0; // @[Debug.scala:1871:9] wire auto_dmiXing_in_a_safe_sink_reset_n_0; // @[Debug.scala:1871:9] wire auto_dmiXing_in_a_ridx_0; // @[Debug.scala:1871:9] wire [2:0] auto_dmiXing_in_d_mem_0_opcode_0; // @[Debug.scala:1871:9] wire [1:0] auto_dmiXing_in_d_mem_0_size_0; // @[Debug.scala:1871:9] wire auto_dmiXing_in_d_mem_0_source_0; // @[Debug.scala:1871:9] wire [31:0] auto_dmiXing_in_d_mem_0_data_0; // @[Debug.scala:1871:9] wire auto_dmiXing_in_d_safe_widx_valid_0; // @[Debug.scala:1871:9] wire auto_dmiXing_in_d_safe_source_reset_n_0; // @[Debug.scala:1871:9] wire auto_dmiXing_in_d_widx_0; // @[Debug.scala:1871:9] wire [2:0] auto_dmInner_sb2tlOpt_out_a_bits_opcode_0; // @[Debug.scala:1871:9] wire [3:0] auto_dmInner_sb2tlOpt_out_a_bits_size_0; // @[Debug.scala:1871:9] wire [31:0] auto_dmInner_sb2tlOpt_out_a_bits_address_0; // @[Debug.scala:1871:9] wire [7:0] auto_dmInner_sb2tlOpt_out_a_bits_data_0; // @[Debug.scala:1871:9] wire auto_dmInner_sb2tlOpt_out_a_valid_0; // @[Debug.scala:1871:9] wire auto_dmInner_sb2tlOpt_out_d_ready_0; // @[Debug.scala:1871:9] wire auto_dmInner_tl_in_a_ready_0; // @[Debug.scala:1871:9] wire [2:0] auto_dmInner_tl_in_d_bits_opcode_0; // @[Debug.scala:1871:9] wire [1:0] auto_dmInner_tl_in_d_bits_size_0; // @[Debug.scala:1871:9] wire [10:0] auto_dmInner_tl_in_d_bits_source_0; // @[Debug.scala:1871:9] wire [63:0] auto_dmInner_tl_in_d_bits_data_0; // @[Debug.scala:1871:9] wire auto_dmInner_tl_in_d_valid_0; // @[Debug.scala:1871:9] wire io_innerCtrl_safe_ridx_valid_0; // @[Debug.scala:1871:9] wire io_innerCtrl_safe_sink_reset_n_0; // @[Debug.scala:1871:9] wire io_innerCtrl_ridx_0; // @[Debug.scala:1871:9] wire io_hgDebugInt_0_0; // @[Debug.scala:1871:9] wire dmactive_synced; // @[ShiftReg.scala:48:24] TLDebugModuleInner dmInner ( // @[Debug.scala:1857:27] .clock (io_debug_clock_0), // @[Debug.scala:1871:9] .reset (io_debug_reset_0), // @[Debug.scala:1871:9] .auto_sb2tlOpt_out_a_ready (auto_dmInner_sb2tlOpt_out_a_ready_0), // @[Debug.scala:1871:9] .auto_sb2tlOpt_out_a_valid (auto_dmInner_sb2tlOpt_out_a_valid_0), .auto_sb2tlOpt_out_a_bits_opcode (auto_dmInner_sb2tlOpt_out_a_bits_opcode_0), .auto_sb2tlOpt_out_a_bits_size (auto_dmInner_sb2tlOpt_out_a_bits_size_0), .auto_sb2tlOpt_out_a_bits_address (auto_dmInner_sb2tlOpt_out_a_bits_address_0), .auto_sb2tlOpt_out_a_bits_data (auto_dmInner_sb2tlOpt_out_a_bits_data_0), .auto_sb2tlOpt_out_d_ready (auto_dmInner_sb2tlOpt_out_d_ready_0), .auto_sb2tlOpt_out_d_valid (auto_dmInner_sb2tlOpt_out_d_valid_0), // @[Debug.scala:1871:9] .auto_sb2tlOpt_out_d_bits_opcode (auto_dmInner_sb2tlOpt_out_d_bits_opcode_0), // @[Debug.scala:1871:9] .auto_sb2tlOpt_out_d_bits_param (auto_dmInner_sb2tlOpt_out_d_bits_param_0), // @[Debug.scala:1871:9] .auto_sb2tlOpt_out_d_bits_size (auto_dmInner_sb2tlOpt_out_d_bits_size_0), // @[Debug.scala:1871:9] .auto_sb2tlOpt_out_d_bits_sink (auto_dmInner_sb2tlOpt_out_d_bits_sink_0), // @[Debug.scala:1871:9] .auto_sb2tlOpt_out_d_bits_denied (auto_dmInner_sb2tlOpt_out_d_bits_denied_0), // @[Debug.scala:1871:9] .auto_sb2tlOpt_out_d_bits_data (auto_dmInner_sb2tlOpt_out_d_bits_data_0), // @[Debug.scala:1871:9] .auto_sb2tlOpt_out_d_bits_corrupt (auto_dmInner_sb2tlOpt_out_d_bits_corrupt_0), // @[Debug.scala:1871:9] .auto_tl_in_a_ready (auto_dmInner_tl_in_a_ready_0), .auto_tl_in_a_valid (auto_dmInner_tl_in_a_valid_0), // @[Debug.scala:1871:9] .auto_tl_in_a_bits_opcode (auto_dmInner_tl_in_a_bits_opcode_0), // @[Debug.scala:1871:9] .auto_tl_in_a_bits_param (auto_dmInner_tl_in_a_bits_param_0), // @[Debug.scala:1871:9] .auto_tl_in_a_bits_size (auto_dmInner_tl_in_a_bits_size_0), // @[Debug.scala:1871:9] .auto_tl_in_a_bits_source (auto_dmInner_tl_in_a_bits_source_0), // @[Debug.scala:1871:9] .auto_tl_in_a_bits_address (auto_dmInner_tl_in_a_bits_address_0), // @[Debug.scala:1871:9] .auto_tl_in_a_bits_mask (auto_dmInner_tl_in_a_bits_mask_0), // @[Debug.scala:1871:9] .auto_tl_in_a_bits_data (auto_dmInner_tl_in_a_bits_data_0), // @[Debug.scala:1871:9] .auto_tl_in_a_bits_corrupt (auto_dmInner_tl_in_a_bits_corrupt_0), // @[Debug.scala:1871:9] .auto_tl_in_d_ready (auto_dmInner_tl_in_d_ready_0), // @[Debug.scala:1871:9] .auto_tl_in_d_valid (auto_dmInner_tl_in_d_valid_0), .auto_tl_in_d_bits_opcode (auto_dmInner_tl_in_d_bits_opcode_0), .auto_tl_in_d_bits_size (auto_dmInner_tl_in_d_bits_size_0), .auto_tl_in_d_bits_source (auto_dmInner_tl_in_d_bits_source_0), .auto_tl_in_d_bits_data (auto_dmInner_tl_in_d_bits_data_0), .auto_dmi_in_a_ready (_dmInner_auto_dmi_in_a_ready), .auto_dmi_in_a_valid (_dmiXing_auto_out_a_valid), // @[Debug.scala:1858:27] .auto_dmi_in_a_bits_opcode (_dmiXing_auto_out_a_bits_opcode), // @[Debug.scala:1858:27] .auto_dmi_in_a_bits_param (_dmiXing_auto_out_a_bits_param), // @[Debug.scala:1858:27] .auto_dmi_in_a_bits_size (_dmiXing_auto_out_a_bits_size), // @[Debug.scala:1858:27] .auto_dmi_in_a_bits_source (_dmiXing_auto_out_a_bits_source), // @[Debug.scala:1858:27] .auto_dmi_in_a_bits_address (_dmiXing_auto_out_a_bits_address), // @[Debug.scala:1858:27] .auto_dmi_in_a_bits_mask (_dmiXing_auto_out_a_bits_mask), // @[Debug.scala:1858:27] .auto_dmi_in_a_bits_data (_dmiXing_auto_out_a_bits_data), // @[Debug.scala:1858:27] .auto_dmi_in_a_bits_corrupt (_dmiXing_auto_out_a_bits_corrupt), // @[Debug.scala:1858:27] .auto_dmi_in_d_ready (_dmiXing_auto_out_d_ready), // @[Debug.scala:1858:27] .auto_dmi_in_d_valid (_dmInner_auto_dmi_in_d_valid), .auto_dmi_in_d_bits_opcode (_dmInner_auto_dmi_in_d_bits_opcode), .auto_dmi_in_d_bits_size (_dmInner_auto_dmi_in_d_bits_size), .auto_dmi_in_d_bits_source (_dmInner_auto_dmi_in_d_bits_source), .auto_dmi_in_d_bits_data (_dmInner_auto_dmi_in_d_bits_data), .io_dmactive (dmactive_synced), // @[ShiftReg.scala:48:24] .io_innerCtrl_valid (_dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_valid), // @[AsyncQueue.scala:211:22] .io_innerCtrl_bits_resumereq (_dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_bits_resumereq), // @[AsyncQueue.scala:211:22] .io_innerCtrl_bits_hartsel (_dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_bits_hartsel), // @[AsyncQueue.scala:211:22] .io_innerCtrl_bits_ackhavereset (_dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_bits_ackhavereset), // @[AsyncQueue.scala:211:22] .io_innerCtrl_bits_hasel (_dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_bits_hasel), // @[AsyncQueue.scala:211:22] .io_innerCtrl_bits_hamask_0 (_dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_bits_hamask_0), // @[AsyncQueue.scala:211:22] .io_innerCtrl_bits_hrmask_0 (_dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_bits_hrmask_0), // @[AsyncQueue.scala:211:22] .io_hgDebugInt_0 (io_hgDebugInt_0_0), .io_hartIsInReset_0 (io_hartIsInReset_0_0), // @[Debug.scala:1871:9] .io_tl_clock (io_tl_clock_0), // @[Debug.scala:1871:9] .io_tl_reset (io_tl_reset_0) // @[Debug.scala:1871:9] ); // @[Debug.scala:1857:27] TLAsyncCrossingSink_a9d32s1k1z2u dmiXing ( // @[Debug.scala:1858:27] .clock (childClock), // @[LazyModuleImp.scala:155:31] .reset (childReset), // @[LazyModuleImp.scala:158:31] .auto_in_a_mem_0_opcode (auto_dmiXing_in_a_mem_0_opcode_0), // @[Debug.scala:1871:9] .auto_in_a_mem_0_address (auto_dmiXing_in_a_mem_0_address_0), // @[Debug.scala:1871:9] .auto_in_a_mem_0_data (auto_dmiXing_in_a_mem_0_data_0), // @[Debug.scala:1871:9] .auto_in_a_ridx (auto_dmiXing_in_a_ridx_0), .auto_in_a_widx (auto_dmiXing_in_a_widx_0), // @[Debug.scala:1871:9] .auto_in_a_safe_ridx_valid (auto_dmiXing_in_a_safe_ridx_valid_0), .auto_in_a_safe_widx_valid (auto_dmiXing_in_a_safe_widx_valid_0), // @[Debug.scala:1871:9] .auto_in_a_safe_source_reset_n (auto_dmiXing_in_a_safe_source_reset_n_0), // @[Debug.scala:1871:9] .auto_in_a_safe_sink_reset_n (auto_dmiXing_in_a_safe_sink_reset_n_0), .auto_in_d_mem_0_opcode (auto_dmiXing_in_d_mem_0_opcode_0), .auto_in_d_mem_0_size (auto_dmiXing_in_d_mem_0_size_0), .auto_in_d_mem_0_source (auto_dmiXing_in_d_mem_0_source_0), .auto_in_d_mem_0_data (auto_dmiXing_in_d_mem_0_data_0), .auto_in_d_ridx (auto_dmiXing_in_d_ridx_0), // @[Debug.scala:1871:9] .auto_in_d_widx (auto_dmiXing_in_d_widx_0), .auto_in_d_safe_ridx_valid (auto_dmiXing_in_d_safe_ridx_valid_0), // @[Debug.scala:1871:9] .auto_in_d_safe_widx_valid (auto_dmiXing_in_d_safe_widx_valid_0), .auto_in_d_safe_source_reset_n (auto_dmiXing_in_d_safe_source_reset_n_0), .auto_in_d_safe_sink_reset_n (auto_dmiXing_in_d_safe_sink_reset_n_0), // @[Debug.scala:1871:9] .auto_out_a_ready (_dmInner_auto_dmi_in_a_ready), // @[Debug.scala:1857:27] .auto_out_a_valid (_dmiXing_auto_out_a_valid), .auto_out_a_bits_opcode (_dmiXing_auto_out_a_bits_opcode), .auto_out_a_bits_param (_dmiXing_auto_out_a_bits_param), .auto_out_a_bits_size (_dmiXing_auto_out_a_bits_size), .auto_out_a_bits_source (_dmiXing_auto_out_a_bits_source), .auto_out_a_bits_address (_dmiXing_auto_out_a_bits_address), .auto_out_a_bits_mask (_dmiXing_auto_out_a_bits_mask), .auto_out_a_bits_data (_dmiXing_auto_out_a_bits_data), .auto_out_a_bits_corrupt (_dmiXing_auto_out_a_bits_corrupt), .auto_out_d_ready (_dmiXing_auto_out_d_ready), .auto_out_d_valid (_dmInner_auto_dmi_in_d_valid), // @[Debug.scala:1857:27] .auto_out_d_bits_opcode (_dmInner_auto_dmi_in_d_bits_opcode), // @[Debug.scala:1857:27] .auto_out_d_bits_size (_dmInner_auto_dmi_in_d_bits_size), // @[Debug.scala:1857:27] .auto_out_d_bits_source (_dmInner_auto_dmi_in_d_bits_source), // @[Debug.scala:1857:27] .auto_out_d_bits_data (_dmInner_auto_dmi_in_d_bits_data) // @[Debug.scala:1857:27] ); // @[Debug.scala:1858:27] AsyncResetSynchronizerShiftReg_w1_d3_i0_27 dmactive_synced_dmactive_synced_dmactiveSync ( // @[ShiftReg.scala:45:23] .clock (childClock), // @[LazyModuleImp.scala:155:31] .reset (childReset), // @[LazyModuleImp.scala:158:31] .io_d (io_dmactive_0), // @[Debug.scala:1871:9] .io_q (dmactive_synced) ); // @[ShiftReg.scala:45:23] AsyncQueueSink_DebugInternalBundle dmactive_synced_dmInner_io_innerCtrl_sink ( // @[AsyncQueue.scala:211:22] .clock (childClock), // @[LazyModuleImp.scala:155:31] .reset (childReset), // @[LazyModuleImp.scala:158:31] .io_deq_valid (_dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_valid), .io_deq_bits_resumereq (_dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_bits_resumereq), .io_deq_bits_hartsel (_dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_bits_hartsel), .io_deq_bits_ackhavereset (_dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_bits_ackhavereset), .io_deq_bits_hasel (_dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_bits_hasel), .io_deq_bits_hamask_0 (_dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_bits_hamask_0), .io_deq_bits_hrmask_0 (_dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_bits_hrmask_0), .io_async_mem_0_resumereq (io_innerCtrl_mem_0_resumereq_0), // @[Debug.scala:1871:9] .io_async_mem_0_hartsel (io_innerCtrl_mem_0_hartsel_0), // @[Debug.scala:1871:9] .io_async_mem_0_ackhavereset (io_innerCtrl_mem_0_ackhavereset_0), // @[Debug.scala:1871:9] .io_async_mem_0_hrmask_0 (io_innerCtrl_mem_0_hrmask_0_0), // @[Debug.scala:1871:9] .io_async_ridx (io_innerCtrl_ridx_0), .io_async_widx (io_innerCtrl_widx_0), // @[Debug.scala:1871:9] .io_async_safe_ridx_valid (io_innerCtrl_safe_ridx_valid_0), .io_async_safe_widx_valid (io_innerCtrl_safe_widx_valid_0), // @[Debug.scala:1871:9] .io_async_safe_source_reset_n (io_innerCtrl_safe_source_reset_n_0), // @[Debug.scala:1871:9] .io_async_safe_sink_reset_n (io_innerCtrl_safe_sink_reset_n_0) ); // @[AsyncQueue.scala:211:22] assign auto_dmiXing_in_a_ridx = auto_dmiXing_in_a_ridx_0; // @[Debug.scala:1871:9] assign auto_dmiXing_in_a_safe_ridx_valid = auto_dmiXing_in_a_safe_ridx_valid_0; // @[Debug.scala:1871:9] assign auto_dmiXing_in_a_safe_sink_reset_n = auto_dmiXing_in_a_safe_sink_reset_n_0; // @[Debug.scala:1871:9] assign auto_dmiXing_in_d_mem_0_opcode = auto_dmiXing_in_d_mem_0_opcode_0; // @[Debug.scala:1871:9] assign auto_dmiXing_in_d_mem_0_size = auto_dmiXing_in_d_mem_0_size_0; // @[Debug.scala:1871:9] assign auto_dmiXing_in_d_mem_0_source = auto_dmiXing_in_d_mem_0_source_0; // @[Debug.scala:1871:9] assign auto_dmiXing_in_d_mem_0_data = auto_dmiXing_in_d_mem_0_data_0; // @[Debug.scala:1871:9] assign auto_dmiXing_in_d_widx = auto_dmiXing_in_d_widx_0; // @[Debug.scala:1871:9] assign auto_dmiXing_in_d_safe_widx_valid = auto_dmiXing_in_d_safe_widx_valid_0; // @[Debug.scala:1871:9] assign auto_dmiXing_in_d_safe_source_reset_n = auto_dmiXing_in_d_safe_source_reset_n_0; // @[Debug.scala:1871:9] assign auto_dmInner_sb2tlOpt_out_a_valid = auto_dmInner_sb2tlOpt_out_a_valid_0; // @[Debug.scala:1871:9] assign auto_dmInner_sb2tlOpt_out_a_bits_opcode = auto_dmInner_sb2tlOpt_out_a_bits_opcode_0; // @[Debug.scala:1871:9] assign auto_dmInner_sb2tlOpt_out_a_bits_size = auto_dmInner_sb2tlOpt_out_a_bits_size_0; // @[Debug.scala:1871:9] assign auto_dmInner_sb2tlOpt_out_a_bits_address = auto_dmInner_sb2tlOpt_out_a_bits_address_0; // @[Debug.scala:1871:9] assign auto_dmInner_sb2tlOpt_out_a_bits_data = auto_dmInner_sb2tlOpt_out_a_bits_data_0; // @[Debug.scala:1871:9] assign auto_dmInner_sb2tlOpt_out_d_ready = auto_dmInner_sb2tlOpt_out_d_ready_0; // @[Debug.scala:1871:9] assign auto_dmInner_tl_in_a_ready = auto_dmInner_tl_in_a_ready_0; // @[Debug.scala:1871:9] assign auto_dmInner_tl_in_d_valid = auto_dmInner_tl_in_d_valid_0; // @[Debug.scala:1871:9] assign auto_dmInner_tl_in_d_bits_opcode = auto_dmInner_tl_in_d_bits_opcode_0; // @[Debug.scala:1871:9] assign auto_dmInner_tl_in_d_bits_size = auto_dmInner_tl_in_d_bits_size_0; // @[Debug.scala:1871:9] assign auto_dmInner_tl_in_d_bits_source = auto_dmInner_tl_in_d_bits_source_0; // @[Debug.scala:1871:9] assign auto_dmInner_tl_in_d_bits_data = auto_dmInner_tl_in_d_bits_data_0; // @[Debug.scala:1871:9] assign io_innerCtrl_ridx = io_innerCtrl_ridx_0; // @[Debug.scala:1871:9] assign io_innerCtrl_safe_ridx_valid = io_innerCtrl_safe_ridx_valid_0; // @[Debug.scala:1871:9] assign io_innerCtrl_safe_sink_reset_n = io_innerCtrl_safe_sink_reset_n_0; // @[Debug.scala:1871:9] assign io_hgDebugInt_0 = io_hgDebugInt_0_0; // @[Debug.scala:1871:9] endmodule
Generate the Verilog code corresponding to the following Chisel files. File SourceB.scala: /* * Copyright 2019 SiFive, Inc. * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You should have received a copy of LICENSE.Apache2 along with * this software. If not, you may obtain a copy at * * https://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. / package sifive.blocks.inclusivecache import chisel3._ import chisel3.util._ import freechips.rocketchip.tilelink._ import freechips.rocketchip.util._ class SourceBRequest(params: InclusiveCacheParameters) extends InclusiveCacheBundle(params) { val param = UInt(3.W) val tag = UInt(params.tagBits.W) val set = UInt(params.setBits.W) val clients = UInt(params.clientBits.W) } class SourceB(params: InclusiveCacheParameters) extends Module { val io = IO(new Bundle { val req = Flipped(Decoupled(new SourceBRequest(params))) val b = Decoupled(new TLBundleB(params.inner.bundle)) }) if (params.firstLevel) { // Tie off unused ports io.req.ready := true.B io.b.valid := false.B io.b.bits := DontCare } else { val remain = RegInit(0.U(params.clientBits.W)) val remain_set = WireInit(init = 0.U(params.clientBits.W)) val remain_clr = WireInit(init = 0.U(params.clientBits.W)) remain := (remain \| remain_set) & ~remain_clr val busy = remain.orR val todo = Mux(busy, remain, io.req.bits.clients) val next = ~(leftOR(todo) << 1) & todo if (params.clientBits > 1) { params.ccover(PopCount(remain) > 1.U, "SOURCEB_MULTI_PROBE", "Had to probe more than one client") } assert (!io.req.valid \|\| io.req.bits.clients =/= 0.U) io.req.ready := !busy when (io.req.fire) { remain_set := io.req.bits.clients } // No restrictions on the type of buffer used here val b = Wire(chiselTypeOf(io.b)) io.b <> params.micro.innerBuf.b(b) b.valid := busy \|\| io.req.valid when (b.fire) { remain_clr := next } params.ccover(b.valid && !b.ready, "SOURCEB_STALL", "Backpressured when issuing a probe") val tag = Mux(!busy, io.req.bits.tag, RegEnable(io.req.bits.tag, io.req.fire)) val set = Mux(!busy, io.req.bits.set, RegEnable(io.req.bits.set, io.req.fire)) val param = Mux(!busy, io.req.bits.param, RegEnable(io.req.bits.param, io.req.fire)) b.bits.opcode := TLMessages.Probe b.bits.param := param b.bits.size := params.offsetBits .U b.bits.source := params.clientSource(next) b.bits.address := params.expandAddress(tag, set, 0.U) b.bits.mask := ~0.U(params.inner.manager.beatBytes.W) b.bits.data := 0.U b.bits.corrupt := false.B } } File Parameters.scala: / * Copyright 2019 SiFive, Inc. * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You should have received a copy of LICENSE.Apache2 along with * this software. If not, you may obtain a copy at * * https://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. / package sifive.blocks.inclusivecache import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config._ import freechips.rocketchip.diplomacy._ import freechips.rocketchip.tilelink._ import freechips.rocketchip.util._ import freechips.rocketchip.util.property.cover import scala.math.{min,max} case class CacheParameters( level: Int, ways: Int, sets: Int, blockBytes: Int, beatBytes: Int, // inner hintsSkipProbe: Boolean) { require (ways > 0) require (sets > 0) require (blockBytes > 0 && isPow2(blockBytes)) require (beatBytes > 0 && isPow2(beatBytes)) require (blockBytes >= beatBytes) val blocks = ways sets val sizeBytes = blocks * blockBytes val blockBeats = blockBytes/beatBytes } case class InclusiveCachePortParameters( a: BufferParams, b: BufferParams, c: BufferParams, d: BufferParams, e: BufferParams) { def apply()(implicit p: Parameters, valName: ValName) = LazyModule(new TLBuffer(a, b, c, d, e)) } object InclusiveCachePortParameters { val none = InclusiveCachePortParameters( a = BufferParams.none, b = BufferParams.none, c = BufferParams.none, d = BufferParams.none, e = BufferParams.none) val full = InclusiveCachePortParameters( a = BufferParams.default, b = BufferParams.default, c = BufferParams.default, d = BufferParams.default, e = BufferParams.default) // This removes feed-through paths from C=>A and A=>C val fullC = InclusiveCachePortParameters( a = BufferParams.none, b = BufferParams.none, c = BufferParams.default, d = BufferParams.none, e = BufferParams.none) val flowAD = InclusiveCachePortParameters( a = BufferParams.flow, b = BufferParams.none, c = BufferParams.none, d = BufferParams.flow, e = BufferParams.none) val flowAE = InclusiveCachePortParameters( a = BufferParams.flow, b = BufferParams.none, c = BufferParams.none, d = BufferParams.none, e = BufferParams.flow) // For innerBuf: // SinkA: no restrictions, flows into scheduler+putbuffer // SourceB: no restrictions, flows out of scheduler // sinkC: no restrictions, flows into scheduler+putbuffer & buffered to bankedStore // SourceD: no restrictions, flows out of bankedStore/regout // SinkE: no restrictions, flows into scheduler // // ... so while none is possible, you probably want at least flowAC to cut ready // from the scheduler delay and flowD to ease SourceD back-pressure // For outerBufer: // SourceA: must not be pipe, flows out of scheduler // SinkB: no restrictions, flows into scheduler // SourceC: pipe is useless, flows out of bankedStore/regout, parameter depth ignored // SinkD: no restrictions, flows into scheduler & bankedStore // SourceE: must not be pipe, flows out of scheduler // // ... AE take the channel ready into the scheduler, so you need at least flowAE } case class InclusiveCacheMicroParameters( writeBytes: Int, // backing store update granularity memCycles: Int = 40, // # of L2 clock cycles for a memory round-trip (50ns @ 800MHz) portFactor: Int = 4, // numSubBanks = (widest TL port * portFactor) / writeBytes dirReg: Boolean = false, innerBuf: InclusiveCachePortParameters = InclusiveCachePortParameters.fullC, // or none outerBuf: InclusiveCachePortParameters = InclusiveCachePortParameters.full) // or flowAE { require (writeBytes > 0 && isPow2(writeBytes)) require (memCycles > 0) require (portFactor >= 2) // for inner RMW and concurrent outer Relase + Grant } case class InclusiveCacheControlParameters( address: BigInt, beatBytes: Int, bankedControl: Boolean) case class InclusiveCacheParameters( cache: CacheParameters, micro: InclusiveCacheMicroParameters, control: Boolean, inner: TLEdgeIn, outer: TLEdgeOut)(implicit val p: Parameters) { require (cache.ways > 1) require (cache.sets > 1 && isPow2(cache.sets)) require (micro.writeBytes <= inner.manager.beatBytes) require (micro.writeBytes <= outer.manager.beatBytes) require (inner.manager.beatBytes <= cache.blockBytes) require (outer.manager.beatBytes <= cache.blockBytes) // Require that all cached address ranges have contiguous blocks outer.manager.managers.flatMap(_.address).foreach { a => require (a.alignment >= cache.blockBytes) } // If we are the first level cache, we do not need to support inner-BCE val firstLevel = !inner.client.clients.exists(_.supports.probe) // If we are the last level cache, we do not need to support outer-B val lastLevel = !outer.manager.managers.exists(_.regionType > RegionType.UNCACHED) require (lastLevel) // Provision enough resources to achieve full throughput with missing single-beat accesses val mshrs = InclusiveCacheParameters.all_mshrs(cache, micro) val secondary = max(mshrs, micro.memCycles - mshrs) val putLists = micro.memCycles // allow every request to be single beat val putBeats = max(2cache.blockBeats, micro.memCycles) val relLists = 2 val relBeats = relListscache.blockBeats val flatAddresses = AddressSet.unify(outer.manager.managers.flatMap(_.address)) val pickMask = AddressDecoder(flatAddresses.map(Seq(_)), flatAddresses.map(_.mask).reduce(_\|_)) def bitOffsets(x: BigInt, offset: Int = 0, tail: List[Int] = List.empty[Int]): List[Int] = if (x == 0) tail.reverse else bitOffsets(x >> 1, offset + 1, if ((x & 1) == 1) offset :: tail else tail) val addressMapping = bitOffsets(pickMask) val addressBits = addressMapping.size // println(s"addresses: ${flatAddresses} => ${pickMask} => ${addressBits}") val allClients = inner.client.clients.size val clientBitsRaw = inner.client.clients.filter(_.supports.probe).size val clientBits = max(1, clientBitsRaw) val stateBits = 2 val wayBits = log2Ceil(cache.ways) val setBits = log2Ceil(cache.sets) val offsetBits = log2Ceil(cache.blockBytes) val tagBits = addressBits - setBits - offsetBits val putBits = log2Ceil(max(putLists, relLists)) require (tagBits > 0) require (offsetBits > 0) val innerBeatBits = (offsetBits - log2Ceil(inner.manager.beatBytes)) max 1 val outerBeatBits = (offsetBits - log2Ceil(outer.manager.beatBytes)) max 1 val innerMaskBits = inner.manager.beatBytes / micro.writeBytes val outerMaskBits = outer.manager.beatBytes / micro.writeBytes def clientBit(source: UInt): UInt = { if (clientBitsRaw == 0) { 0.U } else { Cat(inner.client.clients.filter(_.supports.probe).map(_.sourceId.contains(source)).reverse) } } def clientSource(bit: UInt): UInt = { if (clientBitsRaw == 0) { 0.U } else { Mux1H(bit, inner.client.clients.filter(_.supports.probe).map(c => c.sourceId.start.U)) } } def parseAddress(x: UInt): (UInt, UInt, UInt) = { val offset = Cat(addressMapping.map(o => x(o,o)).reverse) val set = offset >> offsetBits val tag = set >> setBits (tag(tagBits-1, 0), set(setBits-1, 0), offset(offsetBits-1, 0)) } def widen(x: UInt, width: Int): UInt = { val y = x \| 0.U(width.W) assert (y >> width === 0.U) y(width-1, 0) } def expandAddress(tag: UInt, set: UInt, offset: UInt): UInt = { val base = Cat(widen(tag, tagBits), widen(set, setBits), widen(offset, offsetBits)) val bits = Array.fill(outer.bundle.addressBits) { 0.U(1.W) } addressMapping.zipWithIndex.foreach { case (a, i) => bits(a) = base(i,i) } Cat(bits.reverse) } def restoreAddress(expanded: UInt): UInt = { val missingBits = flatAddresses .map { a => (a.widen(pickMask).base, a.widen(~pickMask)) } // key is the bits to restore on match .groupBy(_._1) .view .mapValues(_.map(_._2)) val muxMask = AddressDecoder(missingBits.values.toList) val mux = missingBits.toList.map { case (bits, addrs) => val widen = addrs.map(_.widen(~muxMask)) val matches = AddressSet .unify(widen.distinct) .map(_.contains(expanded)) .reduce(_ \|\| _) (matches, bits.U) } expanded \| Mux1H(mux) } def dirReg[T <: Data](x: T, en: Bool = true.B): T = { if (micro.dirReg) RegEnable(x, en) else x } def ccover(cond: Bool, label: String, desc: String)(implicit sourceInfo: SourceInfo) = cover(cond, "CCACHE_L" + cache.level + "_" + label, "MemorySystem;;" + desc) } object MetaData { val stateBits = 2 def INVALID: UInt = 0.U(stateBits.W) // way is empty def BRANCH: UInt = 1.U(stateBits.W) // outer slave cache is trunk def TRUNK: UInt = 2.U(stateBits.W) // unique inner master cache is trunk def TIP: UInt = 3.U(stateBits.W) // we are trunk, inner masters are branch // Does a request need trunk? def needT(opcode: UInt, param: UInt): Bool = { !opcode(2) \|\| (opcode === TLMessages.Hint && param === TLHints.PREFETCH_WRITE) \|\| ((opcode === TLMessages.AcquireBlock \|\| opcode === TLMessages.AcquirePerm) && param =/= TLPermissions.NtoB) } // Does a request prove the client need not be probed? def skipProbeN(opcode: UInt, hintsSkipProbe: Boolean): Bool = { // Acquire(toB) and Get => is N, so no probe // Acquire(toT) => is N or B, but need T, so no probe // Hint => could be anything, so probe IS needed, if hintsSkipProbe is enabled, skip probe the same client // Put => is N or B, so probe IS needed opcode === TLMessages.AcquireBlock \|\| opcode === TLMessages.AcquirePerm \|\| opcode === TLMessages.Get \|\| (opcode === TLMessages.Hint && hintsSkipProbe.B) } def isToN(param: UInt): Bool = { param === TLPermissions.TtoN \|\| param === TLPermissions.BtoN \|\| param === TLPermissions.NtoN } def isToB(param: UInt): Bool = { param === TLPermissions.TtoB \|\| param === TLPermissions.BtoB } } object InclusiveCacheParameters { val lfsrBits = 10 val L2ControlAddress = 0x2010000 val L2ControlSize = 0x1000 def out_mshrs(cache: CacheParameters, micro: InclusiveCacheMicroParameters): Int = { // We need 2-3 normal MSHRs to cover the Directory latency // To fully exploit memory bandwidth-delay-product, we need memCyles/blockBeats MSHRs max(if (micro.dirReg) 3 else 2, (micro.memCycles + cache.blockBeats - 1) / cache.blockBeats) } def all_mshrs(cache: CacheParameters, micro: InclusiveCacheMicroParameters): Int = // We need a dedicated MSHR for B+C each 2 + out_mshrs(cache, micro) } class InclusiveCacheBundle(params: InclusiveCacheParameters) extends Bundle	module SourceB( // @[SourceB.scala:33:7] input clock, // @[SourceB.scala:33:7] input reset, // @[SourceB.scala:33:7] output io_req_ready, // @[SourceB.scala:35:14] input io_req_valid, // @[SourceB.scala:35:14] input [2:0] io_req_bits_param, // @[SourceB.scala:35:14] input [12:0] io_req_bits_tag, // @[SourceB.scala:35:14] input [9:0] io_req_bits_set, // @[SourceB.scala:35:14] input [3:0] io_req_bits_clients, // @[SourceB.scala:35:14] input io_b_ready, // @[SourceB.scala:35:14] output io_b_valid, // @[SourceB.scala:35:14] output [1:0] io_b_bits_param, // @[SourceB.scala:35:14] output [6:0] io_b_bits_source, // @[SourceB.scala:35:14] output [31:0] io_b_bits_address // @[SourceB.scala:35:14] ); wire io_req_valid_0 = io_req_valid; // @[SourceB.scala:33:7] wire [2:0] io_req_bits_param_0 = io_req_bits_param; // @[SourceB.scala:33:7] wire [12:0] io_req_bits_tag_0 = io_req_bits_tag; // @[SourceB.scala:33:7] wire [9:0] io_req_bits_set_0 = io_req_bits_set; // @[SourceB.scala:33:7] wire [3:0] io_req_bits_clients_0 = io_req_bits_clients; // @[SourceB.scala:33:7] wire io_b_ready_0 = io_b_ready; // @[SourceB.scala:33:7] wire _b_bits_address_base_T_2 = reset; // @[Parameters.scala:222:12] wire _b_bits_address_base_T_8 = reset; // @[Parameters.scala:222:12] wire _b_bits_address_base_T_14 = reset; // @[Parameters.scala:222:12] wire [2:0] io_b_bits_opcode = 3'h6; // @[SourceB.scala:33:7] wire [2:0] io_b_bits_size = 3'h6; // @[SourceB.scala:33:7] wire [2:0] b_bits_opcode = 3'h6; // @[SourceB.scala:65:17] wire [2:0] b_bits_size = 3'h6; // @[SourceB.scala:65:17] wire [15:0] io_b_bits_mask = 16'hFFFF; // @[SourceB.scala:33:7] wire [15:0] b_bits_mask = 16'hFFFF; // @[SourceB.scala:65:17] wire [15:0] _b_bits_mask_T = 16'hFFFF; // @[SourceB.scala:81:23] wire [127:0] io_b_bits_data = 128'h0; // @[SourceB.scala:33:7] wire [127:0] b_bits_data = 128'h0; // @[SourceB.scala:65:17] wire io_b_bits_corrupt = 1'h0; // @[SourceB.scala:33:7] wire b_bits_corrupt = 1'h0; // @[SourceB.scala:65:17] wire _b_bits_address_base_T = 1'h0; // @[Parameters.scala:222:15] wire _b_bits_address_base_T_4 = 1'h0; // @[Parameters.scala:222:12] wire _b_bits_address_base_T_6 = 1'h0; // @[Parameters.scala:222:15] wire _b_bits_address_base_T_10 = 1'h0; // @[Parameters.scala:222:12] wire _b_bits_address_base_T_12 = 1'h0; // @[Parameters.scala:222:15] wire _b_bits_address_base_T_16 = 1'h0; // @[Parameters.scala:222:12] wire [1:0] b_bits_address_hi_hi_hi_lo = 2'h0; // @[Parameters.scala:230:8] wire [5:0] b_bits_address_base_y_2 = 6'h0; // @[Parameters.scala:221:15] wire [5:0] _b_bits_address_base_T_17 = 6'h0; // @[Parameters.scala:223:6] wire _b_bits_address_base_T_1 = 1'h1; // @[Parameters.scala:222:24] wire _b_bits_address_base_T_7 = 1'h1; // @[Parameters.scala:222:24] wire _b_bits_address_base_T_13 = 1'h1; // @[Parameters.scala:222:24] wire _io_req_ready_T; // @[SourceB.scala:61:21] wire b_ready = io_b_ready_0; // @[SourceB.scala:33:7, :65:17] wire b_valid; // @[SourceB.scala:65:17] wire [1:0] b_bits_param; // @[SourceB.scala:65:17] wire [6:0] b_bits_source; // @[SourceB.scala:65:17] wire [31:0] b_bits_address; // @[SourceB.scala:65:17] wire io_req_ready_0; // @[SourceB.scala:33:7] wire [1:0] io_b_bits_param_0; // @[SourceB.scala:33:7] wire [6:0] io_b_bits_source_0; // @[SourceB.scala:33:7] wire [31:0] io_b_bits_address_0; // @[SourceB.scala:33:7] wire io_b_valid_0; // @[SourceB.scala:33:7] reg [3:0] remain; // @[SourceB.scala:46:25] wire [3:0] remain_set; // @[SourceB.scala:47:30] wire [3:0] remain_clr; // @[SourceB.scala:48:30] wire [3:0] _remain_T = remain \| remain_set; // @[SourceB.scala:46:25, :47:30, :49:23] wire [3:0] _remain_T_1 = ~remain_clr; // @[SourceB.scala:48:30, :49:39] wire [3:0] _remain_T_2 = _remain_T & _remain_T_1; // @[SourceB.scala:49:{23,37,39}] wire busy = \|remain; // @[SourceB.scala:46:25, :51:23] wire [3:0] todo = busy ? remain : io_req_bits_clients_0; // @[SourceB.scala:33:7, :46:25, :51:23, :52:19] wire [4:0] _next_T = {todo, 1'h0}; // @[package.scala:253:48] wire [3:0] _next_T_1 = _next_T[3:0]; // @[package.scala:253:{48,53}] wire [3:0] _next_T_2 = todo \| _next_T_1; // @[package.scala:253:{43,53}] wire [5:0] _next_T_3 = {_next_T_2, 2'h0}; // @[package.scala:253:{43,48}] wire [3:0] _next_T_4 = _next_T_3[3:0]; // @[package.scala:253:{48,53}] wire [3:0] _next_T_5 = _next_T_2 \| _next_T_4; // @[package.scala:253:{43,53}] wire [3:0] _next_T_6 = _next_T_5; // @[package.scala:253:43, :254:17] wire [4:0] _next_T_7 = {_next_T_6, 1'h0}; // @[package.scala:254:17] wire [4:0] _next_T_8 = ~_next_T_7; // @[SourceB.scala:53:{16,31}] wire [4:0] next = {1'h0, _next_T_8[3:0] & todo}; // @[SourceB.scala:52:19, :53:{16,37}]
Generate the Verilog code corresponding to the following Chisel files. File Nodes.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.nodes._ import freechips.rocketchip.util.{AsyncQueueParams,RationalDirection} case object TLMonitorBuilder extends Field[TLMonitorArgs => TLMonitorBase](args => new TLMonitor(args)) object TLImp extends NodeImp[TLMasterPortParameters, TLSlavePortParameters, TLEdgeOut, TLEdgeIn, TLBundle] { def edgeO(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeOut(pd, pu, p, sourceInfo) def edgeI(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeIn (pd, pu, p, sourceInfo) def bundleO(eo: TLEdgeOut) = TLBundle(eo.bundle) def bundleI(ei: TLEdgeIn) = TLBundle(ei.bundle) def render(ei: TLEdgeIn) = RenderedEdge(colour = "#000000" /* black /, label = (ei.manager.beatBytes 8).toString) override def monitor(bundle: TLBundle, edge: TLEdgeIn): Unit = { val monitor = Module(edge.params(TLMonitorBuilder)(TLMonitorArgs(edge))) monitor.io.in := bundle } override def mixO(pd: TLMasterPortParameters, node: OutwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLMasterPortParameters = pd.v1copy(clients = pd.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }) override def mixI(pu: TLSlavePortParameters, node: InwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLSlavePortParameters = pu.v1copy(managers = pu.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }) } trait TLFormatNode extends FormatNode[TLEdgeIn, TLEdgeOut] case class TLClientNode(portParams: Seq[TLMasterPortParameters])(implicit valName: ValName) extends SourceNode(TLImp)(portParams) with TLFormatNode case class TLManagerNode(portParams: Seq[TLSlavePortParameters])(implicit valName: ValName) extends SinkNode(TLImp)(portParams) with TLFormatNode case class TLAdapterNode( clientFn: TLMasterPortParameters => TLMasterPortParameters = { s => s }, managerFn: TLSlavePortParameters => TLSlavePortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLImp)(clientFn, managerFn) with TLFormatNode case class TLJunctionNode( clientFn: Seq[TLMasterPortParameters] => Seq[TLMasterPortParameters], managerFn: Seq[TLSlavePortParameters] => Seq[TLSlavePortParameters])( implicit valName: ValName) extends JunctionNode(TLImp)(clientFn, managerFn) with TLFormatNode case class TLIdentityNode()(implicit valName: ValName) extends IdentityNode(TLImp)() with TLFormatNode object TLNameNode { def apply(name: ValName) = TLIdentityNode()(name) def apply(name: Option[String]): TLIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLIdentityNode = apply(Some(name)) } case class TLEphemeralNode()(implicit valName: ValName) extends EphemeralNode(TLImp)() object TLTempNode { def apply(): TLEphemeralNode = TLEphemeralNode()(ValName("temp")) } case class TLNexusNode( clientFn: Seq[TLMasterPortParameters] => TLMasterPortParameters, managerFn: Seq[TLSlavePortParameters] => TLSlavePortParameters)( implicit valName: ValName) extends NexusNode(TLImp)(clientFn, managerFn) with TLFormatNode abstract class TLCustomNode(implicit valName: ValName) extends CustomNode(TLImp) with TLFormatNode // Asynchronous crossings trait TLAsyncFormatNode extends FormatNode[TLAsyncEdgeParameters, TLAsyncEdgeParameters] object TLAsyncImp extends SimpleNodeImp[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncEdgeParameters, TLAsyncBundle] { def edge(pd: TLAsyncClientPortParameters, pu: TLAsyncManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLAsyncEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLAsyncEdgeParameters) = new TLAsyncBundle(e.bundle) def render(e: TLAsyncEdgeParameters) = RenderedEdge(colour = "#ff0000" /* red /, label = e.manager.async.depth.toString) override def mixO(pd: TLAsyncClientPortParameters, node: OutwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLAsyncManagerPortParameters, node: InwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLAsyncAdapterNode( clientFn: TLAsyncClientPortParameters => TLAsyncClientPortParameters = { s => s }, managerFn: TLAsyncManagerPortParameters => TLAsyncManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLAsyncImp)(clientFn, managerFn) with TLAsyncFormatNode case class TLAsyncIdentityNode()(implicit valName: ValName) extends IdentityNode(TLAsyncImp)() with TLAsyncFormatNode object TLAsyncNameNode { def apply(name: ValName) = TLAsyncIdentityNode()(name) def apply(name: Option[String]): TLAsyncIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLAsyncIdentityNode = apply(Some(name)) } case class TLAsyncSourceNode(sync: Option[Int])(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLAsyncImp)( dFn = { p => TLAsyncClientPortParameters(p) }, uFn = { p => p.base.v1copy(minLatency = p.base.minLatency + sync.getOrElse(p.async.sync)) }) with FormatNode[TLEdgeIn, TLAsyncEdgeParameters] // discard cycles in other clock domain case class TLAsyncSinkNode(async: AsyncQueueParams)(implicit valName: ValName) extends MixedAdapterNode(TLAsyncImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = p.base.minLatency + async.sync) }, uFn = { p => TLAsyncManagerPortParameters(async, p) }) with FormatNode[TLAsyncEdgeParameters, TLEdgeOut] // Rationally related crossings trait TLRationalFormatNode extends FormatNode[TLRationalEdgeParameters, TLRationalEdgeParameters] object TLRationalImp extends SimpleNodeImp[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalEdgeParameters, TLRationalBundle] { def edge(pd: TLRationalClientPortParameters, pu: TLRationalManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLRationalEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLRationalEdgeParameters) = new TLRationalBundle(e.bundle) def render(e: TLRationalEdgeParameters) = RenderedEdge(colour = "#00ff00" / green /) override def mixO(pd: TLRationalClientPortParameters, node: OutwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLRationalManagerPortParameters, node: InwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLRationalAdapterNode( clientFn: TLRationalClientPortParameters => TLRationalClientPortParameters = { s => s }, managerFn: TLRationalManagerPortParameters => TLRationalManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLRationalImp)(clientFn, managerFn) with TLRationalFormatNode case class TLRationalIdentityNode()(implicit valName: ValName) extends IdentityNode(TLRationalImp)() with TLRationalFormatNode object TLRationalNameNode { def apply(name: ValName) = TLRationalIdentityNode()(name) def apply(name: Option[String]): TLRationalIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLRationalIdentityNode = apply(Some(name)) } case class TLRationalSourceNode()(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLRationalImp)( dFn = { p => TLRationalClientPortParameters(p) }, uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLRationalEdgeParameters] // discard cycles from other clock domain case class TLRationalSinkNode(direction: RationalDirection)(implicit valName: ValName) extends MixedAdapterNode(TLRationalImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = 1) }, uFn = { p => TLRationalManagerPortParameters(direction, p) }) with FormatNode[TLRationalEdgeParameters, TLEdgeOut] // Credited version of TileLink channels trait TLCreditedFormatNode extends FormatNode[TLCreditedEdgeParameters, TLCreditedEdgeParameters] object TLCreditedImp extends SimpleNodeImp[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedEdgeParameters, TLCreditedBundle] { def edge(pd: TLCreditedClientPortParameters, pu: TLCreditedManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLCreditedEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLCreditedEdgeParameters) = new TLCreditedBundle(e.bundle) def render(e: TLCreditedEdgeParameters) = RenderedEdge(colour = "#ffff00" / yellow /, e.delay.toString) override def mixO(pd: TLCreditedClientPortParameters, node: OutwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLCreditedManagerPortParameters, node: InwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLCreditedAdapterNode( clientFn: TLCreditedClientPortParameters => TLCreditedClientPortParameters = { s => s }, managerFn: TLCreditedManagerPortParameters => TLCreditedManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLCreditedImp)(clientFn, managerFn) with TLCreditedFormatNode case class TLCreditedIdentityNode()(implicit valName: ValName) extends IdentityNode(TLCreditedImp)() with TLCreditedFormatNode object TLCreditedNameNode { def apply(name: ValName) = TLCreditedIdentityNode()(name) def apply(name: Option[String]): TLCreditedIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLCreditedIdentityNode = apply(Some(name)) } case class TLCreditedSourceNode(delay: TLCreditedDelay)(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLCreditedImp)( dFn = { p => TLCreditedClientPortParameters(delay, p) }, uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLCreditedEdgeParameters] // discard cycles from other clock domain case class TLCreditedSinkNode(delay: TLCreditedDelay)(implicit valName: ValName) extends MixedAdapterNode(TLCreditedImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = 1) }, uFn = { p => TLCreditedManagerPortParameters(delay, p) }) with FormatNode[TLCreditedEdgeParameters, TLEdgeOut] File RegisterRouter.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.nodes._ import freechips.rocketchip.diplomacy.{AddressSet, TransferSizes} import freechips.rocketchip.resources.{Device, Resource, ResourceBindings} import freechips.rocketchip.prci.{NoCrossing} import freechips.rocketchip.regmapper.{RegField, RegMapper, RegMapperParams, RegMapperInput, RegisterRouter} import freechips.rocketchip.util.{BundleField, ControlKey, ElaborationArtefacts, GenRegDescsAnno} import scala.math.min class TLRegisterRouterExtraBundle(val sourceBits: Int, val sizeBits: Int) extends Bundle { val source = UInt((sourceBits max 1).W) val size = UInt((sizeBits max 1).W) } case object TLRegisterRouterExtra extends ControlKey[TLRegisterRouterExtraBundle]("tlrr_extra") case class TLRegisterRouterExtraField(sourceBits: Int, sizeBits: Int) extends BundleField[TLRegisterRouterExtraBundle](TLRegisterRouterExtra, Output(new TLRegisterRouterExtraBundle(sourceBits, sizeBits)), x => { x.size := 0.U x.source := 0.U }) /* TLRegisterNode is a specialized TL SinkNode that encapsulates MMIO registers. * It provides functionality for describing and outputting metdata about the registers in several formats. * It also provides a concrete implementation of a regmap function that will be used * to wire a map of internal registers associated with this node to the node's interconnect port. / case class TLRegisterNode( address: Seq[AddressSet], device: Device, deviceKey: String = "reg/control", concurrency: Int = 0, beatBytes: Int = 4, undefZero: Boolean = true, executable: Boolean = false)( implicit valName: ValName) extends SinkNode(TLImp)(Seq(TLSlavePortParameters.v1( Seq(TLSlaveParameters.v1( address = address, resources = Seq(Resource(device, deviceKey)), executable = executable, supportsGet = TransferSizes(1, beatBytes), supportsPutPartial = TransferSizes(1, beatBytes), supportsPutFull = TransferSizes(1, beatBytes), fifoId = Some(0))), // requests are handled in order beatBytes = beatBytes, minLatency = min(concurrency, 1)))) with TLFormatNode // the Queue adds at most one cycle { val size = 1 << log2Ceil(1 + address.map(_.max).max - address.map(_.base).min) require (size >= beatBytes) address.foreach { case a => require (a.widen(size-1).base == address.head.widen(size-1).base, s"TLRegisterNode addresses (${address}) must be aligned to its size ${size}") } // Calling this method causes the matching TL2 bundle to be // configured to route all requests to the listed RegFields. def regmap(mapping: RegField.Map) = { val (bundleIn, edge) = this.in(0) val a = bundleIn.a val d = bundleIn.d val fields = TLRegisterRouterExtraField(edge.bundle.sourceBits, edge.bundle.sizeBits) +: a.bits.params.echoFields val params = RegMapperParams(log2Up(size/beatBytes), beatBytes, fields) val in = Wire(Decoupled(new RegMapperInput(params))) in.bits.read := a.bits.opcode === TLMessages.Get in.bits.index := edge.addr_hi(a.bits) in.bits.data := a.bits.data in.bits.mask := a.bits.mask Connectable.waiveUnmatched(in.bits.extra, a.bits.echo) match { case (lhs, rhs) => lhs :<= rhs } val a_extra = in.bits.extra(TLRegisterRouterExtra) a_extra.source := a.bits.source a_extra.size := a.bits.size // Invoke the register map builder val out = RegMapper(beatBytes, concurrency, undefZero, in, mapping:_) // No flow control needed in.valid := a.valid a.ready := in.ready d.valid := out.valid out.ready := d.ready // We must restore the size to enable width adapters to work val d_extra = out.bits.extra(TLRegisterRouterExtra) d.bits := edge.AccessAck(toSource = d_extra.source, lgSize = d_extra.size) // avoid a Mux on the data bus by manually overriding two fields d.bits.data := out.bits.data Connectable.waiveUnmatched(d.bits.echo, out.bits.extra) match { case (lhs, rhs) => lhs :<= rhs } d.bits.opcode := Mux(out.bits.read, TLMessages.AccessAckData, TLMessages.AccessAck) // Tie off unused channels bundleIn.b.valid := false.B bundleIn.c.ready := true.B bundleIn.e.ready := true.B genRegDescsJson(mapping:_) } def genRegDescsJson(mapping: RegField.Map): Unit = { // Dump out the register map for documentation purposes. val base = address.head.base val baseHex = s"0x${base.toInt.toHexString}" val name = s"${device.describe(ResourceBindings()).name}.At${baseHex}" val json = GenRegDescsAnno.serialize(base, name, mapping:_) var suffix = 0 while( ElaborationArtefacts.contains(s"${baseHex}.${suffix}.regmap.json")) { suffix = suffix + 1 } ElaborationArtefacts.add(s"${baseHex}.${suffix}.regmap.json", json) val module = Module.currentModule.get.asInstanceOf[RawModule] GenRegDescsAnno.anno( module, base, mapping:_) } } /* Mix HasTLControlRegMap into any subclass of RegisterRouter to gain helper functions for attaching a device control register map to TileLink. * - The intended use case is that controlNode will diplomatically publish a SW-visible device's memory-mapped control registers. * - Use the clock crossing helper controlXing to externally connect controlNode to a TileLink interconnect. * - Use the mapping helper function regmap to internally fill out the space of device control registers. / trait HasTLControlRegMap { this: RegisterRouter => protected val controlNode = TLRegisterNode( address = address, device = device, deviceKey = "reg/control", concurrency = concurrency, beatBytes = beatBytes, undefZero = undefZero, executable = executable) // Externally, this helper should be used to connect the register control port to a bus val controlXing: TLInwardClockCrossingHelper = this.crossIn(controlNode) // Backwards-compatibility default node accessor with no clock crossing lazy val node: TLInwardNode = controlXing(NoCrossing) // Internally, this function should be used to populate the control port with registers protected def regmap(mapping: RegField.Map): Unit = { controlNode.regmap(mapping:_) } } File RegField.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.regmapper import chisel3._ import chisel3.util.{DecoupledIO, ReadyValidIO} import org.json4s.JsonDSL._ import org.json4s.JsonAST.JValue import freechips.rocketchip.util.{SimpleRegIO} case class RegReadFn private(combinational: Boolean, fn: (Bool, Bool) => (Bool, Bool, UInt)) object RegReadFn { // (ivalid: Bool, oready: Bool) => (iready: Bool, ovalid: Bool, data: UInt) // iready may combinationally depend on oready // all other combinational dependencies forbidden (e.g. ovalid <= ivalid) // effects must become visible on the cycle after ovalid && oready // data is only inspected when ovalid && oready implicit def apply(x: (Bool, Bool) => (Bool, Bool, UInt)) = new RegReadFn(false, x) implicit def apply(x: RegisterReadIO[UInt]): RegReadFn = RegReadFn((ivalid, oready) => { x.request.valid := ivalid x.response.ready := oready (x.request.ready, x.response.valid, x.response.bits) }) // (ready: Bool) => (valid: Bool, data: UInt) // valid must not combinationally depend on ready // effects must become visible on the cycle after valid && ready implicit def apply(x: Bool => (Bool, UInt)) = new RegReadFn(true, { case (_, oready) => val (ovalid, data) = x(oready) (true.B, ovalid, data) }) // read from a ReadyValidIO (only safe if there is a consistent source of data) implicit def apply(x: ReadyValidIO[UInt]):RegReadFn = RegReadFn(ready => { x.ready := ready; (x.valid, x.bits) }) // read from a register implicit def apply(x: UInt):RegReadFn = RegReadFn(ready => (true.B, x)) // noop implicit def apply(x: Unit):RegReadFn = RegReadFn(0.U) } case class RegWriteFn private(combinational: Boolean, fn: (Bool, Bool, UInt) => (Bool, Bool)) object RegWriteFn { // (ivalid: Bool, oready: Bool, data: UInt) => (iready: Bool, ovalid: Bool) // iready may combinationally depend on both oready and data // all other combinational dependencies forbidden (e.g. ovalid <= ivalid) // effects must become visible on the cycle after ovalid && oready // data should only be used for an effect when ivalid && iready implicit def apply(x: (Bool, Bool, UInt) => (Bool, Bool)) = new RegWriteFn(false, x) implicit def apply(x: RegisterWriteIO[UInt]): RegWriteFn = RegWriteFn((ivalid, oready, data) => { x.request.valid := ivalid x.request.bits := data x.response.ready := oready (x.request.ready, x.response.valid) }) // (valid: Bool, data: UInt) => (ready: Bool) // ready may combinationally depend on data (but not valid) // effects must become visible on the cycle after valid && ready implicit def apply(x: (Bool, UInt) => Bool) = // combinational => data valid on oready new RegWriteFn(true, { case (_, oready, data) => (true.B, x(oready, data)) }) // write to a DecoupledIO (only safe if there is a consistent sink draining data) // NOTE: this is not an IrrevocableIO (even on TL2) because other fields could cause a lowered valid implicit def apply(x: DecoupledIO[UInt]): RegWriteFn = RegWriteFn((valid, data) => { x.valid := valid; x.bits := data; x.ready }) // updates a register (or adds a mux to a wire) implicit def apply(x: UInt): RegWriteFn = RegWriteFn((valid, data) => { when (valid) { x := data }; true.B }) // noop implicit def apply(x: Unit): RegWriteFn = RegWriteFn((valid, data) => { true.B }) } case class RegField(width: Int, read: RegReadFn, write: RegWriteFn, desc: Option[RegFieldDesc]) { require (width >= 0, s"RegField width must be >= 0, not $width") def pipelined = !read.combinational \|\| !write.combinational def readOnly = this.copy(write = (), desc = this.desc.map(_.copy(access = RegFieldAccessType.R))) def toJson(byteOffset: Int, bitOffset: Int): JValue = { ( ("byteOffset" -> s"0x${byteOffset.toHexString}") ~ ("bitOffset" -> bitOffset) ~ ("bitWidth" -> width) ~ ("name" -> desc.map(_.name)) ~ ("description" -> desc.map{ d=> if (d.desc == "") None else Some(d.desc)}) ~ ("resetValue" -> desc.map{_.reset}) ~ ("group" -> desc.map{_.group}) ~ ("groupDesc" -> desc.map{_.groupDesc}) ~ ("accessType" -> desc.map {d => d.access.toString}) ~ ("writeType" -> desc.map {d => d.wrType.map(_.toString)}) ~ ("readAction" -> desc.map {d => d.rdAction.map(_.toString)}) ~ ("volatile" -> desc.map {d => if (d.volatile) Some(true) else None}) ~ ("enumerations" -> desc.map {d => Option(d.enumerations.map { case (key, (name, edesc)) => (("value" -> key) ~ ("name" -> name) ~ ("description" -> edesc)) }).filter(_.nonEmpty)}) ) } } object RegField { // Byte address => sequence of bitfields, lowest index => lowest address type Map = (Int, Seq[RegField]) def apply(n: Int) : RegField = apply(n, (), (), Some(RegFieldDesc.reserved)) def apply(n: Int, desc: RegFieldDesc) : RegField = apply(n, (), (), Some(desc)) def apply(n: Int, r: RegReadFn, w: RegWriteFn) : RegField = apply(n, r, w, None) def apply(n: Int, r: RegReadFn, w: RegWriteFn, desc: RegFieldDesc) : RegField = apply(n, r, w, Some(desc)) def apply(n: Int, rw: UInt) : RegField = apply(n, rw, rw, None) def apply(n: Int, rw: UInt, desc: RegFieldDesc) : RegField = apply(n, rw, rw, Some(desc)) def r(n: Int, r: RegReadFn) : RegField = apply(n, r, (), None) def r(n: Int, r: RegReadFn, desc: RegFieldDesc) : RegField = apply(n, r, (), Some(desc.copy(access = RegFieldAccessType.R))) def w(n: Int, w: RegWriteFn) : RegField = apply(n, (), w, None) def w(n: Int, w: RegWriteFn, desc: RegFieldDesc) : RegField = apply(n, (), w, Some(desc.copy(access = RegFieldAccessType.W))) // This RegField allows 'set' to set bits in 'reg'. // and to clear bits when the bus writes bits of value 1. // Setting takes priority over clearing. def w1ToClear(n: Int, reg: UInt, set: UInt, desc: Option[RegFieldDesc] = None): RegField = RegField(n, reg, RegWriteFn((valid, data) => { reg := (~((~reg) \| Mux(valid, data, 0.U))) \| set; true.B }), desc.map{_.copy(access = RegFieldAccessType.RW, wrType=Some(RegFieldWrType.ONE_TO_CLEAR), volatile = true)}) // This RegField wraps an explicit register // (e.g. Black-Boxed Register) to create a R/W register. def rwReg(n: Int, bb: SimpleRegIO, desc: Option[RegFieldDesc] = None) : RegField = RegField(n, bb.q, RegWriteFn((valid, data) => { bb.en := valid bb.d := data true.B }), desc) // Create byte-sized read-write RegFields out of a large UInt register. // It is updated when any of the (implemented) bytes are written, the non-written // bytes are just copied over from their current value. // Because the RegField are all byte-sized, this is also suitable when a register is larger // than the intended bus width of the device (atomic updates are impossible). def bytes(reg: UInt, numBytes: Int, desc: Option[RegFieldDesc]): Seq[RegField] = { require(reg.getWidth 8 >= numBytes, "Can't break a ${reg.getWidth}-bit-wide register into only ${numBytes} bytes.") val numFullBytes = reg.getWidth/8 val numPartialBytes = if ((reg.getWidth % 8) > 0) 1 else 0 val numPadBytes = numBytes - numFullBytes - numPartialBytes val pad = reg \| 0.U((8numBytes).W) val oldBytes = VecInit.tabulate(numBytes) { i => pad(8(i+1)-1, 8i) } val newBytes = WireDefault(oldBytes) val valids = WireDefault(VecInit.fill(numBytes) { false.B }) when (valids.reduce(_ \|\| _)) { reg := newBytes.asUInt } def wrFn(i: Int): RegWriteFn = RegWriteFn((valid, data) => { valids(i) := valid when (valid) {newBytes(i) := data} true.B }) val fullBytes = Seq.tabulate(numFullBytes) { i => val newDesc = desc.map {d => d.copy(name = d.name + s"_$i")} RegField(8, oldBytes(i), wrFn(i), newDesc)} val partialBytes = if (numPartialBytes > 0) { val newDesc = desc.map {d => d.copy(name = d.name + s"_$numFullBytes")} Seq(RegField(reg.getWidth % 8, oldBytes(numFullBytes), wrFn(numFullBytes), newDesc), RegField(8 - (reg.getWidth % 8))) } else Nil val padBytes = Seq.fill(numPadBytes){RegField(8)} fullBytes ++ partialBytes ++ padBytes } def bytes(reg: UInt, desc: Option[RegFieldDesc]): Seq[RegField] = { val width = reg.getWidth require (width % 8 == 0, s"RegField.bytes must be called on byte-sized reg, not ${width} bits") bytes(reg, width/8, desc) } def bytes(reg: UInt, numBytes: Int): Seq[RegField] = bytes(reg, numBytes, None) def bytes(reg: UInt): Seq[RegField] = bytes(reg, None) } trait HasRegMap { def regmap(mapping: RegField.Map): Unit val interrupts: Vec[Bool] } // See Example.scala for an example of how to use regmap File MuxLiteral.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util.log2Ceil import scala.reflect.ClassTag /* MuxLiteral creates a lookup table from a key to a list of values. * Unlike MuxLookup, the table keys must be exclusive literals. / object MuxLiteral { def apply[T <: Data:ClassTag](index: UInt, default: T, first: (UInt, T), rest: (UInt, T)): T = apply(index, default, first :: rest.toList) def apply[T <: Data:ClassTag](index: UInt, default: T, cases: Seq[(UInt, T)]): T = MuxTable(index, default, cases.map { case (k, v) => (k.litValue, v) }) } object MuxSeq { def apply[T <: Data:ClassTag](index: UInt, default: T, first: T, rest: T): T = apply(index, default, first :: rest.toList) def apply[T <: Data:ClassTag](index: UInt, default: T, cases: Seq[T]): T = MuxTable(index, default, cases.zipWithIndex.map { case (v, i) => (BigInt(i), v) }) } object MuxTable { def apply[T <: Data:ClassTag](index: UInt, default: T, first: (BigInt, T), rest: (BigInt, T)): T = apply(index, default, first :: rest.toList) def apply[T <: Data:ClassTag](index: UInt, default: T, cases: Seq[(BigInt, T)]): T = { /* All keys must be >= 0 and distinct / cases.foreach { case (k, _) => require (k >= 0) } require (cases.map(_._1).distinct.size == cases.size) / Filter out any cases identical to the default / val simple = cases.filter { case (k, v) => !default.isLit \|\| !v.isLit \|\| v.litValue != default.litValue } val maxKey = (BigInt(0) +: simple.map(_._1)).max val endIndex = BigInt(1) << log2Ceil(maxKey+1) if (simple.isEmpty) { default } else if (endIndex <= 2simple.size) { /* The dense encoding case uses a Vec / val table = Array.fill(endIndex.toInt) { default } simple.foreach { case (k, v) => table(k.toInt) = v } Mux(index >= endIndex.U, default, VecInit(table)(index)) } else { / The sparse encoding case uses switch / val out = WireDefault(default) simple.foldLeft(new chisel3.util.SwitchContext(index, None, Set.empty)) { case (acc, (k, v)) => acc.is (k.U) { out := v } } out } } } File LazyModuleImp.scala: package org.chipsalliance.diplomacy.lazymodule import chisel3.{withClockAndReset, Module, RawModule, Reset, _} import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo} import firrtl.passes.InlineAnnotation import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.nodes.Dangle import scala.collection.immutable.SortedMap /* Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]]. * * This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy. / sealed trait LazyModuleImpLike extends RawModule { /* [[LazyModule]] that contains this instance. / val wrapper: LazyModule /* IOs that will be automatically "punched" for this instance. / val auto: AutoBundle /* The metadata that describes the [[HalfEdge]]s which generated [[auto]]. / protected[diplomacy] val dangles: Seq[Dangle] // [[wrapper.module]] had better not be accessed while LazyModules are still being built! require( LazyModule.scope.isEmpty, s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}" ) /* Set module name. Defaults to the containing LazyModule's desiredName. / override def desiredName: String = wrapper.desiredName suggestName(wrapper.suggestedName) /* [[Parameters]] for chisel [[Module]]s. / implicit val p: Parameters = wrapper.p /* instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and * submodules. / protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = { // 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]], // 2. return [[Dangle]]s from each module. val childDangles = wrapper.children.reverse.flatMap { c => implicit val sourceInfo: SourceInfo = c.info c.cloneProto.map { cp => // If the child is a clone, then recursively set cloneProto of its children as well def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = { require(bases.size == clones.size) (bases.zip(clones)).map { case (l, r) => require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}") l.cloneProto = Some(r) assignCloneProtos(l.children, r.children) } } assignCloneProtos(c.children, cp.children) // Clone the child module as a record, and get its [[AutoBundle]] val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName) val clonedAuto = clone("auto").asInstanceOf[AutoBundle] // Get the empty [[Dangle]]'s of the cloned child val rawDangles = c.cloneDangles() require(rawDangles.size == clonedAuto.elements.size) // Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) } dangles }.getOrElse { // For non-clones, instantiate the child module val mod = try { Module(c.module) } catch { case e: ChiselException => { println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}") throw e } } mod.dangles } } // Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]]. // This will result in a sequence of [[Dangle]] from these [[BaseNode]]s. val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate()) // Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]] val allDangles = nodeDangles ++ childDangles // Group [[allDangles]] by their [[source]]. val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _) // For each [[source]] set of [[Dangle]]s of size 2, ensure that these // can be connected as a source-sink pair (have opposite flipped value). // Make the connection and mark them as [[done]]. val done = Set() ++ pairing.values.filter(_.size == 2).map { case Seq(a, b) => require(a.flipped != b.flipped) // @todo <> in chisel3 makes directionless connection. if (a.flipped) { a.data <> b.data } else { b.data <> a.data } a.source case _ => None } // Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module. val forward = allDangles.filter(d => !done(d.source)) // Generate [[AutoBundle]] IO from [[forward]]. val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _)) // Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]] val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) => if (d.flipped) { d.data <> io } else { io <> d.data } d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name) } // Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]]. wrapper.inModuleBody.reverse.foreach { _() } if (wrapper.shouldBeInlined) { chisel3.experimental.annotate(new ChiselAnnotation { def toFirrtl = InlineAnnotation(toNamed) }) } // Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]]. (auto, dangles) } } /* Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. / class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike { /* Instantiate hardware of this `Module`. / val (auto, dangles) = instantiate() } /* Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. / class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike { // These wires are the default clock+reset for all LazyModule children. // It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the // [[LazyRawModuleImp]] children. // Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly. /* drive clock explicitly. / val childClock: Clock = Wire(Clock()) /* drive reset explicitly. / val childReset: Reset = Wire(Reset()) // the default is that these are disabled childClock := false.B.asClock childReset := chisel3.DontCare def provideImplicitClockToLazyChildren: Boolean = false val (auto, dangles) = if (provideImplicitClockToLazyChildren) { withClockAndReset(childClock, childReset) { instantiate() } } else { instantiate() } } File MixedNode.scala: package org.chipsalliance.diplomacy.nodes import chisel3.{Data, DontCare, Wire} import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.{Field, Parameters} import org.chipsalliance.diplomacy.ValName import org.chipsalliance.diplomacy.sourceLine /* One side metadata of a [[Dangle]]. * * Describes one side of an edge going into or out of a [[BaseNode]]. * * @param serial * the global [[BaseNode.serial]] number of the [[BaseNode]] that this [[HalfEdge]] connects to. * @param index * the `index` in the [[BaseNode]]'s input or output port list that this [[HalfEdge]] belongs to. / case class HalfEdge(serial: Int, index: Int) extends Ordered[HalfEdge] { import scala.math.Ordered.orderingToOrdered def compare(that: HalfEdge): Int = HalfEdge.unapply(this).compare(HalfEdge.unapply(that)) } /* [[Dangle]] captures the `IO` information of a [[LazyModule]] and which two [[BaseNode]]s the [[Edges]]/[[Bundle]] * connects. * * [[Dangle]]s are generated by [[BaseNode.instantiate]] using [[MixedNode.danglesOut]] and [[MixedNode.danglesIn]] , * [[LazyModuleImp.instantiate]] connects those that go to internal or explicit IO connections in a [[LazyModule]]. * * @param source * the source [[HalfEdge]] of this [[Dangle]], which captures the source [[BaseNode]] and the port `index` within * that [[BaseNode]]. * @param sink * sink [[HalfEdge]] of this [[Dangle]], which captures the sink [[BaseNode]] and the port `index` within that * [[BaseNode]]. * @param flipped * flip or not in [[AutoBundle.makeElements]]. If true this corresponds to `danglesOut`, if false it corresponds to * `danglesIn`. * @param dataOpt * actual [[Data]] for the hardware connection. Can be empty if this belongs to a cloned module / case class Dangle(source: HalfEdge, sink: HalfEdge, flipped: Boolean, name: String, dataOpt: Option[Data]) { def data = dataOpt.get } /* [[Edges]] is a collection of parameters describing the functionality and connection for an interface, which is often * derived from the interconnection protocol and can inform the parameterization of the hardware bundles that actually * implement the protocol. / case class Edges[EI, EO](in: Seq[EI], out: Seq[EO]) /* A field available in [[Parameters]] used to determine whether [[InwardNodeImp.monitor]] will be called. / case object MonitorsEnabled extends Field[Boolean](true) /* When rendering the edge in a graphical format, flip the order in which the edges' source and sink are presented. * * For example, when rendering graphML, yEd by default tries to put the source node vertically above the sink node, but * [[RenderFlipped]] inverts this relationship. When a particular [[LazyModule]] contains both source nodes and sink * nodes, flipping the rendering of one node's edge will usual produce a more concise visual layout for the * [[LazyModule]]. / case object RenderFlipped extends Field[Boolean](false) /* The sealed node class in the package, all node are derived from it. * * @param inner * Sink interface implementation. * @param outer * Source interface implementation. * @param valName * val name of this node. * @tparam DI * Downward-flowing parameters received on the inner side of the node. It is usually a brunch of parameters * describing the protocol parameters from a source. For an [[InwardNode]], it is determined by the connected * [[OutwardNode]]. Since it can be connected to multiple sources, this parameter is always a Seq of source port * parameters. * @tparam UI * Upward-flowing parameters generated by the inner side of the node. It is usually a brunch of parameters describing * the protocol parameters of a sink. For an [[InwardNode]], it is determined itself. * @tparam EI * Edge Parameters describing a connection on the inner side of the node. It is usually a brunch of transfers * specified for a sink according to protocol. * @tparam BI * Bundle type used when connecting to the inner side of the node. It is a hardware interface of this sink interface. * It should extends from [[chisel3.Data]], which represents the real hardware. * @tparam DO * Downward-flowing parameters generated on the outer side of the node. It is usually a brunch of parameters * describing the protocol parameters of a source. For an [[OutwardNode]], it is determined itself. * @tparam UO * Upward-flowing parameters received by the outer side of the node. It is usually a brunch of parameters describing * the protocol parameters from a sink. For an [[OutwardNode]], it is determined by the connected [[InwardNode]]. * Since it can be connected to multiple sinks, this parameter is always a Seq of sink port parameters. * @tparam EO * Edge Parameters describing a connection on the outer side of the node. It is usually a brunch of transfers * specified for a source according to protocol. * @tparam BO * Bundle type used when connecting to the outer side of the node. It is a hardware interface of this source * interface. It should extends from [[chisel3.Data]], which represents the real hardware. * * @note * Call Graph of [[MixedNode]] * - line `─`: source is process by a function and generate pass to others * - Arrow `→`: target of arrow is generated by source * * {{{ * (from the other node) * ┌─────────────────────────────────────────────────────────[[InwardNode.uiParams]]─────────────┐ * ↓ │ * (binding node when elaboration) [[OutwardNode.uoParams]]────────────────────────[[MixedNode.mapParamsU]]→──────────┐ │ * [[InwardNode.accPI]] │ │ │ * │ │ (based on protocol) │ * │ │ [[MixedNode.inner.edgeI]] │ * │ │ ↓ │ * ↓ │ │ │ * (immobilize after elaboration) (inward port from [[OutwardNode]]) │ ↓ │ * [[InwardNode.iBindings]]──┐ [[MixedNode.iDirectPorts]]────────────────────→[[MixedNode.iPorts]] [[InwardNode.uiParams]] │ * │ │ ↑ │ │ │ * │ │ │ [[OutwardNode.doParams]] │ │ * │ │ │ (from the other node) │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * │ │ │ └────────┬──────────────┤ │ * │ │ │ │ │ │ * │ │ │ │ (based on protocol) │ * │ │ │ │ [[MixedNode.inner.edgeI]] │ * │ │ │ │ │ │ * │ │ (from the other node) │ ↓ │ * │ └───[[OutwardNode.oPortMapping]] [[OutwardNode.oStar]] │ [[MixedNode.edgesIn]]───┐ │ * │ ↑ ↑ │ │ ↓ │ * │ │ │ │ │ [[MixedNode.in]] │ * │ │ │ │ ↓ ↑ │ * │ (solve star connection) │ │ │ [[MixedNode.bundleIn]]──┘ │ * ├───[[MixedNode.resolveStar]]→─┼─────────────────────────────┤ └────────────────────────────────────┐ │ * │ │ │ [[MixedNode.bundleOut]]─┐ │ │ * │ │ │ ↑ ↓ │ │ * │ │ │ │ [[MixedNode.out]] │ │ * │ ↓ ↓ │ ↑ │ │ * │ ┌─────[[InwardNode.iPortMapping]] [[InwardNode.iStar]] [[MixedNode.edgesOut]]──┘ │ │ * │ │ (from the other node) ↑ │ │ * │ │ │ │ │ │ * │ │ │ [[MixedNode.outer.edgeO]] │ │ * │ │ │ (based on protocol) │ │ * │ │ │ │ │ │ * │ │ │ ┌────────────────────────────────────────┤ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * (immobilize after elaboration)│ ↓ │ │ │ │ * [[OutwardNode.oBindings]]─┘ [[MixedNode.oDirectPorts]]───→[[MixedNode.oPorts]] [[OutwardNode.doParams]] │ │ * ↑ (inward port from [[OutwardNode]]) │ │ │ │ * │ ┌─────────────────────────────────────────┤ │ │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * [[OutwardNode.accPO]] │ ↓ │ │ │ * (binding node when elaboration) │ [[InwardNode.diParams]]─────→[[MixedNode.mapParamsD]]────────────────────────────┘ │ │ * │ ↑ │ │ * │ └──────────────────────────────────────────────────────────────────────────────────────────┘ │ * └──────────────────────────────────────────────────────────────────────────────────────────────────────────┘ * }}} / abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data]( val inner: InwardNodeImp[DI, UI, EI, BI], val outer: OutwardNodeImp[DO, UO, EO, BO] )( implicit valName: ValName) extends BaseNode with NodeHandle[DI, UI, EI, BI, DO, UO, EO, BO] with InwardNode[DI, UI, BI] with OutwardNode[DO, UO, BO] { // Generate a [[NodeHandle]] with inward and outward node are both this node. val inward = this val outward = this /* Debug info of nodes binding. / def bindingInfo: String = s"""$iBindingInfo \|$oBindingInfo \|""".stripMargin /* Debug info of ports connecting. / def connectedPortsInfo: String = s"""${oPorts.size} outward ports connected: [${oPorts.map(_._2.name).mkString(",")}] \|${iPorts.size} inward ports connected: [${iPorts.map(_._2.name).mkString(",")}] \|""".stripMargin /* Debug info of parameters propagations. / def parametersInfo: String = s"""${doParams.size} downstream outward parameters: [${doParams.mkString(",")}] \|${uoParams.size} upstream outward parameters: [${uoParams.mkString(",")}] \|${diParams.size} downstream inward parameters: [${diParams.mkString(",")}] \|${uiParams.size} upstream inward parameters: [${uiParams.mkString(",")}] \|""".stripMargin /* For a given node, converts [[OutwardNode.accPO]] and [[InwardNode.accPI]] to [[MixedNode.oPortMapping]] and * [[MixedNode.iPortMapping]]. * * Given counts of known inward and outward binding and inward and outward star bindings, return the resolved inward * stars and outward stars. * * This method will also validate the arguments and throw a runtime error if the values are unsuitable for this type * of node. * * @param iKnown * Number of known-size ([[BIND_ONCE]]) input bindings. * @param oKnown * Number of known-size ([[BIND_ONCE]]) output bindings. * @param iStar * Number of unknown size ([[BIND_STAR]]) input bindings. * @param oStar * Number of unknown size ([[BIND_STAR]]) output bindings. * @return * A Tuple of the resolved number of input and output connections. / protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStar: Int, oStar: Int): (Int, Int) /* Function to generate downward-flowing outward params from the downward-flowing input params and the current output * ports. * * @param n * The size of the output sequence to generate. * @param p * Sequence of downward-flowing input parameters of this node. * @return * A `n`-sized sequence of downward-flowing output edge parameters. / protected[diplomacy] def mapParamsD(n: Int, p: Seq[DI]): Seq[DO] /* Function to generate upward-flowing input parameters from the upward-flowing output parameters [[uiParams]]. * * @param n * Size of the output sequence. * @param p * Upward-flowing output edge parameters. * @return * A n-sized sequence of upward-flowing input edge parameters. / protected[diplomacy] def mapParamsU(n: Int, p: Seq[UO]): Seq[UI] /* @return * The sink cardinality of the node, the number of outputs bound with [[BIND_QUERY]] summed with inputs bound with * [[BIND_STAR]]. / protected[diplomacy] lazy val sinkCard: Int = oBindings.count(_._3 == BIND_QUERY) + iBindings.count(_._3 == BIND_STAR) /* @return * The source cardinality of this node, the number of inputs bound with [[BIND_QUERY]] summed with the number of * output bindings bound with [[BIND_STAR]]. / protected[diplomacy] lazy val sourceCard: Int = iBindings.count(_._3 == BIND_QUERY) + oBindings.count(_._3 == BIND_STAR) /* @return list of nodes involved in flex bindings with this node. / protected[diplomacy] lazy val flexes: Seq[BaseNode] = oBindings.filter(_._3 == BIND_FLEX).map(_._2) ++ iBindings.filter(_._3 == BIND_FLEX).map(_._2) /* Resolves the flex to be either source or sink and returns the offset where the [[BIND_STAR]] operators begin * greedily taking up the remaining connections. * * @return * A value >= 0 if it is sink cardinality, a negative value for source cardinality. The magnitude of the return * value is not relevant. / protected[diplomacy] lazy val flexOffset: Int = { /* Recursively performs a depth-first search of the [[flexes]], [[BaseNode]]s connected to this node with flex * operators. The algorithm bottoms out when we either get to a node we have already visited or when we get to a * connection that is not a flex and can set the direction for us. Otherwise, recurse by visiting the `flexes` of * each node in the current set and decide whether they should be added to the set or not. * * @return * the mapping of [[BaseNode]] indexed by their serial numbers. / def DFS(v: BaseNode, visited: Map[Int, BaseNode]): Map[Int, BaseNode] = { if (visited.contains(v.serial) \|\| !v.flexibleArityDirection) { visited } else { v.flexes.foldLeft(visited + (v.serial -> v))((sum, n) => DFS(n, sum)) } } /* Determine which [[BaseNode]] are involved in resolving the flex connections to/from this node. * * @example * {{{ * a := b := c * d := b * e := f * }}} * * `flexSet` for `a`, `b`, `c`, or `d` will be `Set(a, b, c, d)` `flexSet` for `e` or `f` will be `Set(e,f)` / val flexSet = DFS(this, Map()).values /* The total number of := operators where we're on the left. / val allSink = flexSet.map(_.sinkCard).sum /** The total number of :=* operators used when we're on the right. / val allSource = flexSet.map(_.sourceCard).sum require( allSink == 0 \|\| allSource == 0, s"The nodes ${flexSet.map(_.name)} which are inter-connected by :=* have ${allSink} := operators and ${allSource} := operators connected to them, making it impossible to determine cardinality inference direction." ) allSink - allSource } /** @return A value >= 0 if it is sink cardinality, a negative value for source cardinality. / protected[diplomacy] def edgeArityDirection(n: BaseNode): Int = { if (flexibleArityDirection) flexOffset else if (n.flexibleArityDirection) n.flexOffset else 0 } /* For a node which is connected between two nodes, select the one that will influence the direction of the flex * resolution. / protected[diplomacy] def edgeAritySelect(n: BaseNode, l: => Int, r: => Int): Int = { val dir = edgeArityDirection(n) if (dir < 0) l else if (dir > 0) r else 1 } /* Ensure that the same node is not visited twice in resolving `:=`, etc operators. / private var starCycleGuard = false /** Resolve all the star operators into concrete indicies. As connections are being made, some may be "star" * connections which need to be resolved. In some way to determine how many actual edges they correspond to. We also * need to build up the ranges of edges which correspond to each binding operator, so that We can apply the correct * edge parameters and later build up correct bundle connections. * * [[oPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that oPort (binding * operator). [[iPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that iPort * (binding operator). [[oStar]]: `Int` the value to return for this node `N` for any `N := foo` or `N :=* foo := bar` [[iStar]]: `Int` the value to return for this node `N` for any `foo :=* N` or `bar :=* foo := N` / protected[diplomacy] lazy val ( oPortMapping: Seq[(Int, Int)], iPortMapping: Seq[(Int, Int)], oStar: Int, iStar: Int ) = { try { if (starCycleGuard) throw StarCycleException() starCycleGuard = true // For a given node N... // Number of foo := N // + Number of bar :=* foo := N val oStars = oBindings.count { case (_, n, b, _, _) => b == BIND_STAR \|\| (b == BIND_FLEX && edgeArityDirection(n) < 0) } // Number of N := foo // + Number of N :=* foo := bar val iStars = iBindings.count { case (_, n, b, _, _) => b == BIND_STAR \|\| (b == BIND_FLEX && edgeArityDirection(n) > 0) } // 1 for foo := N // + bar.iStar for bar := foo := N // + foo.iStar for foo := N // + 0 for foo := N val oKnown = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, 0, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => 0 } }.sum // 1 for N := foo // + bar.oStar for N := foo :=* bar // + foo.oStar for N :=* foo // + 0 for N := foo val iKnown = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, 0) case BIND_QUERY => n.oStar case BIND_STAR => 0 } }.sum // Resolve star depends on the node subclass to implement the algorithm for this. val (iStar, oStar) = resolveStar(iKnown, oKnown, iStars, oStars) // Cumulative list of resolved outward binding range starting points val oSum = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, oStar, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => oStar } }.scanLeft(0)(_ + _) // Cumulative list of resolved inward binding range starting points val iSum = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, iStar) case BIND_QUERY => n.oStar case BIND_STAR => iStar } }.scanLeft(0)(_ + _) // Create ranges for each binding based on the running sums and return // those along with resolved values for the star operations. (oSum.init.zip(oSum.tail), iSum.init.zip(iSum.tail), oStar, iStar) } catch { case c: StarCycleException => throw c.copy(loop = context +: c.loop) } } /* Sequence of inward ports. * * This should be called after all star bindings are resolved. * * Each element is: `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. * `n` Instance of inward node. `p` View of [[Parameters]] where this connection was made. `s` Source info where this * connection was made in the source code. / protected[diplomacy] lazy val oDirectPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oBindings.flatMap { case (i, n, _, p, s) => // for each binding operator in this node, look at what it connects to val (start, end) = n.iPortMapping(i) (start until end).map { j => (j, n, p, s) } } /* Sequence of outward ports. * * This should be called after all star bindings are resolved. * * `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. `n` Instance of * outward node. `p` View of [[Parameters]] where this connection was made. `s` [[SourceInfo]] where this connection * was made in the source code. / protected[diplomacy] lazy val iDirectPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iBindings.flatMap { case (i, n, _, p, s) => // query this port index range of this node in the other side of node. val (start, end) = n.oPortMapping(i) (start until end).map { j => (j, n, p, s) } } // Ephemeral nodes ( which have non-None iForward/oForward) have in_degree = out_degree // Thus, there must exist an Eulerian path and the below algorithms terminate @scala.annotation.tailrec private def oTrace( tuple: (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) ): (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.iForward(i) match { case None => (i, n, p, s) case Some((j, m)) => oTrace((j, m, p, s)) } } @scala.annotation.tailrec private def iTrace( tuple: (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) ): (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.oForward(i) match { case None => (i, n, p, s) case Some((j, m)) => iTrace((j, m, p, s)) } } /* Final output ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - Numeric index of this binding in the [[InwardNode]] on the other end. * - [[InwardNode]] on the other end of this binding. * - A view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. / lazy val oPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oDirectPorts.map(oTrace) /* Final input ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - numeric index of this binding in [[OutwardNode]] on the other end. * - [[OutwardNode]] on the other end of this binding. * - a view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. / lazy val iPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iDirectPorts.map(iTrace) private var oParamsCycleGuard = false protected[diplomacy] lazy val diParams: Seq[DI] = iPorts.map { case (i, n, _, _) => n.doParams(i) } protected[diplomacy] lazy val doParams: Seq[DO] = { try { if (oParamsCycleGuard) throw DownwardCycleException() oParamsCycleGuard = true val o = mapParamsD(oPorts.size, diParams) require( o.size == oPorts.size, s"""Diplomacy has detected a problem with your graph: \|At the following node, the number of outward ports should equal the number of produced outward parameters. \|$context \|$connectedPortsInfo \|Downstreamed inward parameters: [${diParams.mkString(",")}] \|Produced outward parameters: [${o.mkString(",")}] \|""".stripMargin ) o.map(outer.mixO(_, this)) } catch { case c: DownwardCycleException => throw c.copy(loop = context +: c.loop) } } private var iParamsCycleGuard = false protected[diplomacy] lazy val uoParams: Seq[UO] = oPorts.map { case (o, n, _, _) => n.uiParams(o) } protected[diplomacy] lazy val uiParams: Seq[UI] = { try { if (iParamsCycleGuard) throw UpwardCycleException() iParamsCycleGuard = true val i = mapParamsU(iPorts.size, uoParams) require( i.size == iPorts.size, s"""Diplomacy has detected a problem with your graph: \|At the following node, the number of inward ports should equal the number of produced inward parameters. \|$context \|$connectedPortsInfo \|Upstreamed outward parameters: [${uoParams.mkString(",")}] \|Produced inward parameters: [${i.mkString(",")}] \|""".stripMargin ) i.map(inner.mixI(_, this)) } catch { case c: UpwardCycleException => throw c.copy(loop = context +: c.loop) } } /* Outward edge parameters. / protected[diplomacy] lazy val edgesOut: Seq[EO] = (oPorts.zip(doParams)).map { case ((i, n, p, s), o) => outer.edgeO(o, n.uiParams(i), p, s) } /* Inward edge parameters. / protected[diplomacy] lazy val edgesIn: Seq[EI] = (iPorts.zip(uiParams)).map { case ((o, n, p, s), i) => inner.edgeI(n.doParams(o), i, p, s) } /* A tuple of the input edge parameters and output edge parameters for the edges bound to this node. * * If you need to access to the edges of a foreign Node, use this method (in/out create bundles). / lazy val edges: Edges[EI, EO] = Edges(edgesIn, edgesOut) /* Create actual Wires corresponding to the Bundles parameterized by the outward edges of this node. / protected[diplomacy] lazy val bundleOut: Seq[BO] = edgesOut.map { e => val x = Wire(outer.bundleO(e)).suggestName(s"${valName.value}Out") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } /* Create actual Wires corresponding to the Bundles parameterized by the inward edges of this node. / protected[diplomacy] lazy val bundleIn: Seq[BI] = edgesIn.map { e => val x = Wire(inner.bundleI(e)).suggestName(s"${valName.value}In") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } private def emptyDanglesOut: Seq[Dangle] = oPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(serial, i), sink = HalfEdge(n.serial, j), flipped = false, name = wirePrefix + "out", dataOpt = None ) } private def emptyDanglesIn: Seq[Dangle] = iPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(n.serial, j), sink = HalfEdge(serial, i), flipped = true, name = wirePrefix + "in", dataOpt = None ) } /* Create the [[Dangle]]s which describe the connections from this node output to other nodes inputs. / protected[diplomacy] def danglesOut: Seq[Dangle] = emptyDanglesOut.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleOut(i))) } /* Create the [[Dangle]]s which describe the connections from this node input from other nodes outputs. / protected[diplomacy] def danglesIn: Seq[Dangle] = emptyDanglesIn.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleIn(i))) } private[diplomacy] var instantiated = false /* Gather Bundle and edge parameters of outward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. / def out: Seq[(BO, EO)] = { require( instantiated, s"$name.out should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleOut.zip(edgesOut) } /* Gather Bundle and edge parameters of inward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. / def in: Seq[(BI, EI)] = { require( instantiated, s"$name.in should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleIn.zip(edgesIn) } /* Actually instantiate this node during [[LazyModuleImp]] evaluation. Mark that it's safe to use the Bundle wires, * instantiate monitors on all input ports if appropriate, and return all the dangles of this node. / protected[diplomacy] def instantiate(): Seq[Dangle] = { instantiated = true if (!circuitIdentity) { (iPorts.zip(in)).foreach { case ((_, _, p, _), (b, e)) => if (p(MonitorsEnabled)) inner.monitor(b, e) } } danglesOut ++ danglesIn } protected[diplomacy] def cloneDangles(): Seq[Dangle] = emptyDanglesOut ++ emptyDanglesIn /* Connects the outward part of a node with the inward part of this node. / protected[diplomacy] def bind( h: OutwardNode[DI, UI, BI], binding: NodeBinding )( implicit p: Parameters, sourceInfo: SourceInfo ): Unit = { val x = this // x := y val y = h sourceLine(sourceInfo, " at ", "") val i = x.iPushed val o = y.oPushed y.oPush( i, x, binding match { case BIND_ONCE => BIND_ONCE case BIND_FLEX => BIND_FLEX case BIND_STAR => BIND_QUERY case BIND_QUERY => BIND_STAR } ) x.iPush(o, y, binding) } / Metadata for printing the node graph. / def inputs: Seq[(OutwardNode[DI, UI, BI], RenderedEdge)] = (iPorts.zip(edgesIn)).map { case ((_, n, p, _), e) => val re = inner.render(e) (n, re.copy(flipped = re.flipped != p(RenderFlipped))) } /* Metadata for printing the node graph / def outputs: Seq[(InwardNode[DO, UO, BO], RenderedEdge)] = oPorts.map { case (i, n, _, _) => (n, n.inputs(i)._2) } } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportPutFull \|\| manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB \|\| manager.anySupportGet \|\| manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportPutFull \|\| client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe \|\| client.anySupportGet \|\| client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet \|\| client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull \|\| client.anySupportPutPartial \|\| client.anySupportHint \|\| client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet \|\| manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull \|\| manager.anySupportPutPartial \|\| manager.anySupportHint \|\| manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) \|\| !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.ProbeAckData \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode \| small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U \|\| beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } } File CLINT.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.devices.tilelink import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.diplomacy.{AddressSet} import freechips.rocketchip.resources.{Resource, SimpleDevice} import freechips.rocketchip.interrupts.{IntNexusNode, IntSinkParameters, IntSinkPortParameters, IntSourceParameters, IntSourcePortParameters} import freechips.rocketchip.regmapper.{RegField, RegFieldDesc, RegFieldGroup} import freechips.rocketchip.subsystem.{BaseSubsystem, CBUS, TLBusWrapperLocation} import freechips.rocketchip.tilelink.{TLFragmenter, TLRegisterNode} import freechips.rocketchip.util.Annotated object CLINTConsts { def msipOffset(hart: Int) = hart * msipBytes def timecmpOffset(hart: Int) = 0x4000 + hart * timecmpBytes def timeOffset = 0xbff8 def msipBytes = 4 def timecmpBytes = 8 def size = 0x10000 def timeWidth = 64 def ipiWidth = 32 def ints = 2 } case class CLINTParams(baseAddress: BigInt = 0x02000000, intStages: Int = 0) { def address = AddressSet(baseAddress, CLINTConsts.size-1) } case object CLINTKey extends Field[Option[CLINTParams]](None) case class CLINTAttachParams( slaveWhere: TLBusWrapperLocation = CBUS ) case object CLINTAttachKey extends Field(CLINTAttachParams()) class CLINT(params: CLINTParams, beatBytes: Int)(implicit p: Parameters) extends LazyModule { import CLINTConsts._ // clint0 => at most 4095 devices val device = new SimpleDevice("clint", Seq("riscv,clint0")) { override val alwaysExtended = true } val node: TLRegisterNode = TLRegisterNode( address = Seq(params.address), device = device, beatBytes = beatBytes) val intnode : IntNexusNode = IntNexusNode( sourceFn = { _ => IntSourcePortParameters(Seq(IntSourceParameters(ints, Seq(Resource(device, "int"))))) }, sinkFn = { _ => IntSinkPortParameters(Seq(IntSinkParameters())) }, outputRequiresInput = false) lazy val module = new Impl class Impl extends LazyModuleImp(this) { Annotated.params(this, params) require (intnode.edges.in.size == 0, "CLINT only produces interrupts; it does not accept them") val io = IO(new Bundle { val rtcTick = Input(Bool()) }) val time = RegInit(0.U(timeWidth.W)) when (io.rtcTick) { time := time + 1.U } val nTiles = intnode.out.size val timecmp = Seq.fill(nTiles) { Reg(UInt(timeWidth.W)) } val ipi = Seq.fill(nTiles) { RegInit(0.U(1.W)) } val (intnode_out, _) = intnode.out.unzip intnode_out.zipWithIndex.foreach { case (int, i) => int(0) := ShiftRegister(ipi(i)(0), params.intStages) // msip int(1) := ShiftRegister(time.asUInt >= timecmp(i).asUInt, params.intStages) // mtip } /* 0000 msip hart 0 * 0004 msip hart 1 * 4000 mtimecmp hart 0 lo * 4004 mtimecmp hart 0 hi * 4008 mtimecmp hart 1 lo * 400c mtimecmp hart 1 hi * bff8 mtime lo * bffc mtime hi / node.regmap( 0 -> RegFieldGroup ("msip", Some("MSIP Bits"), ipi.zipWithIndex.flatMap{ case (r, i) => RegField(1, r, RegFieldDesc(s"msip_$i", s"MSIP bit for Hart $i", reset=Some(0))) :: RegField(ipiWidth - 1) :: Nil }), timecmpOffset(0) -> timecmp.zipWithIndex.flatMap{ case (t, i) => RegFieldGroup(s"mtimecmp_$i", Some(s"MTIMECMP for hart $i"), RegField.bytes(t, Some(RegFieldDesc(s"mtimecmp_$i", "", reset=None))))}, timeOffset -> RegFieldGroup("mtime", Some("Timer Register"), RegField.bytes(time, Some(RegFieldDesc("mtime", "", reset=Some(0), volatile=true)))) ) } } /* Trait that will connect a CLINT to a subsystem */ trait CanHavePeripheryCLINT { this: BaseSubsystem => val (clintOpt, clintDomainOpt, clintTickOpt) = p(CLINTKey).map { params => val tlbus = locateTLBusWrapper(p(CLINTAttachKey).slaveWhere) val clintDomainWrapper = tlbus.generateSynchronousDomain("CLINT").suggestName("clint_domain") val clint = clintDomainWrapper { LazyModule(new CLINT(params, tlbus.beatBytes)) } clintDomainWrapper { clint.node := tlbus.coupleTo("clint") { TLFragmenter(tlbus, Some("CLINT")) := _ } } val clintTick = clintDomainWrapper { InModuleBody { val tick = IO(Input(Bool())) clint.module.io.rtcTick := tick tick }} (clint, clintDomainWrapper, clintTick) }.unzip3 }	module CLINT( // @[CLINT.scala:65:9] input clock, // @[CLINT.scala:65:9] input reset, // @[CLINT.scala:65:9] output auto_int_out_0, // @[LazyModuleImp.scala:107:25] output auto_int_out_1, // @[LazyModuleImp.scala:107:25] output auto_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [1:0] auto_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [12:0] auto_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [25:0] auto_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [12:0] auto_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output [63:0] auto_in_d_bits_data, // @[LazyModuleImp.scala:107:25] input io_rtcTick // @[CLINT.scala:69:16] ); wire out_front_valid; // @[RegisterRouter.scala:87:24] wire out_front_ready; // @[RegisterRouter.scala:87:24] wire out_bits_read; // @[RegisterRouter.scala:87:24] wire [12:0] out_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:87:24] wire [12:0] in_bits_index; // @[RegisterRouter.scala:73:18] wire in_bits_read; // @[RegisterRouter.scala:73:18] wire auto_in_a_valid_0 = auto_in_a_valid; // @[CLINT.scala:65:9] wire [2:0] auto_in_a_bits_opcode_0 = auto_in_a_bits_opcode; // @[CLINT.scala:65:9] wire [2:0] auto_in_a_bits_param_0 = auto_in_a_bits_param; // @[CLINT.scala:65:9] wire [1:0] auto_in_a_bits_size_0 = auto_in_a_bits_size; // @[CLINT.scala:65:9] wire [12:0] auto_in_a_bits_source_0 = auto_in_a_bits_source; // @[CLINT.scala:65:9] wire [25:0] auto_in_a_bits_address_0 = auto_in_a_bits_address; // @[CLINT.scala:65:9] wire [7:0] auto_in_a_bits_mask_0 = auto_in_a_bits_mask; // @[CLINT.scala:65:9] wire [63:0] auto_in_a_bits_data_0 = auto_in_a_bits_data; // @[CLINT.scala:65:9] wire auto_in_a_bits_corrupt_0 = auto_in_a_bits_corrupt; // @[CLINT.scala:65:9] wire auto_in_d_ready_0 = auto_in_d_ready; // @[CLINT.scala:65:9] wire io_rtcTick_0 = io_rtcTick; // @[CLINT.scala:65:9] wire [12:0] out_maskMatch = 13'h7FF; // @[RegisterRouter.scala:87:24] wire [2:0] nodeIn_d_bits_d_opcode = 3'h0; // @[Edges.scala:792:17] wire [63:0] _out_out_bits_data_WIRE_1_3 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] nodeIn_d_bits_d_data = 64'h0; // @[Edges.scala:792:17] wire auto_in_d_bits_sink = 1'h0; // @[CLINT.scala:65:9] wire auto_in_d_bits_denied = 1'h0; // @[CLINT.scala:65:9] wire auto_in_d_bits_corrupt = 1'h0; // @[CLINT.scala:65:9] wire nodeIn_d_bits_sink = 1'h0; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_denied = 1'h0; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17] wire _valids_WIRE_0 = 1'h0; // @[RegField.scala:153:53] wire _valids_WIRE_1 = 1'h0; // @[RegField.scala:153:53] wire _valids_WIRE_2 = 1'h0; // @[RegField.scala:153:53] wire _valids_WIRE_3 = 1'h0; // @[RegField.scala:153:53] wire _valids_WIRE_4 = 1'h0; // @[RegField.scala:153:53] wire _valids_WIRE_5 = 1'h0; // @[RegField.scala:153:53] wire _valids_WIRE_6 = 1'h0; // @[RegField.scala:153:53] wire _valids_WIRE_7 = 1'h0; // @[RegField.scala:153:53] wire _valids_WIRE_1_0 = 1'h0; // @[RegField.scala:153:53] wire _valids_WIRE_1_1 = 1'h0; // @[RegField.scala:153:53] wire _valids_WIRE_1_2 = 1'h0; // @[RegField.scala:153:53] wire _valids_WIRE_1_3 = 1'h0; // @[RegField.scala:153:53] wire _valids_WIRE_1_4 = 1'h0; // @[RegField.scala:153:53] wire _valids_WIRE_1_5 = 1'h0; // @[RegField.scala:153:53] wire _valids_WIRE_1_6 = 1'h0; // @[RegField.scala:153:53] wire _valids_WIRE_1_7 = 1'h0; // @[RegField.scala:153:53] wire _out_rifireMux_T_16 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_18 = 1'h0; // @[MuxLiteral.scala:49:17] wire _out_wifireMux_T_17 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_19 = 1'h0; // @[MuxLiteral.scala:49:17] wire _out_rofireMux_T_16 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_18 = 1'h0; // @[MuxLiteral.scala:49:17] wire _out_wofireMux_T_17 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_19 = 1'h0; // @[MuxLiteral.scala:49:17] wire _out_out_bits_data_T = 1'h0; // @[MuxLiteral.scala:49:17] wire _out_out_bits_data_T_2 = 1'h0; // @[MuxLiteral.scala:49:17] wire nodeIn_d_bits_d_sink = 1'h0; // @[Edges.scala:792:17] wire nodeIn_d_bits_d_denied = 1'h0; // @[Edges.scala:792:17] wire nodeIn_d_bits_d_corrupt = 1'h0; // @[Edges.scala:792:17] wire [1:0] auto_in_d_bits_param = 2'h0; // @[CLINT.scala:65:9] wire [1:0] nodeIn_d_bits_param = 2'h0; // @[MixedNode.scala:551:17] wire [1:0] nodeIn_d_bits_d_param = 2'h0; // @[Edges.scala:792:17] wire intnodeOut_0; // @[MixedNode.scala:542:17] wire out_rifireMux_out = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_5 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_1 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_9 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_2 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_13 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_3 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_17 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_2 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_3 = 1'h1; // @[MuxLiteral.scala:49:48] wire out_rifireMux = 1'h1; // @[MuxLiteral.scala:49:10] wire out_wifireMux_out = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_6 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_1 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_10 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_2 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_14 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_3 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_18 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_2 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_3 = 1'h1; // @[MuxLiteral.scala:49:48] wire out_wifireMux = 1'h1; // @[MuxLiteral.scala:49:10] wire out_rofireMux_out = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_5 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_1 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_9 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_2 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_13 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_3 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_17 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_2 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_3 = 1'h1; // @[MuxLiteral.scala:49:48] wire out_rofireMux = 1'h1; // @[MuxLiteral.scala:49:10] wire out_wofireMux_out = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_6 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_1 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_10 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_2 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_14 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_3 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_18 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_2 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_3 = 1'h1; // @[MuxLiteral.scala:49:48] wire out_wofireMux = 1'h1; // @[MuxLiteral.scala:49:10] wire out_iready = 1'h1; // @[RegisterRouter.scala:87:24] wire out_oready = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_out_bits_data_WIRE_3 = 1'h1; // @[MuxLiteral.scala:49:48] wire intnodeOut_1; // @[MixedNode.scala:542:17] wire nodeIn_a_ready; // @[MixedNode.scala:551:17] wire nodeIn_a_valid = auto_in_a_valid_0; // @[CLINT.scala:65:9] wire [2:0] nodeIn_a_bits_opcode = auto_in_a_bits_opcode_0; // @[CLINT.scala:65:9] wire [2:0] nodeIn_a_bits_param = auto_in_a_bits_param_0; // @[CLINT.scala:65:9] wire [1:0] nodeIn_a_bits_size = auto_in_a_bits_size_0; // @[CLINT.scala:65:9] wire [12:0] nodeIn_a_bits_source = auto_in_a_bits_source_0; // @[CLINT.scala:65:9] wire [25:0] nodeIn_a_bits_address = auto_in_a_bits_address_0; // @[CLINT.scala:65:9] wire [7:0] nodeIn_a_bits_mask = auto_in_a_bits_mask_0; // @[CLINT.scala:65:9] wire [63:0] nodeIn_a_bits_data = auto_in_a_bits_data_0; // @[CLINT.scala:65:9] wire nodeIn_a_bits_corrupt = auto_in_a_bits_corrupt_0; // @[CLINT.scala:65:9] wire nodeIn_d_ready = auto_in_d_ready_0; // @[CLINT.scala:65:9] wire nodeIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] nodeIn_d_bits_size; // @[MixedNode.scala:551:17] wire [12:0] nodeIn_d_bits_source; // @[MixedNode.scala:551:17] wire [63:0] nodeIn_d_bits_data; // @[MixedNode.scala:551:17] wire auto_int_out_0_0; // @[CLINT.scala:65:9] wire auto_int_out_1_0; // @[CLINT.scala:65:9] wire auto_in_a_ready_0; // @[CLINT.scala:65:9] wire [2:0] auto_in_d_bits_opcode_0; // @[CLINT.scala:65:9] wire [1:0] auto_in_d_bits_size_0; // @[CLINT.scala:65:9] wire [12:0] auto_in_d_bits_source_0; // @[CLINT.scala:65:9] wire [63:0] auto_in_d_bits_data_0; // @[CLINT.scala:65:9] wire auto_in_d_valid_0; // @[CLINT.scala:65:9] wire in_ready; // @[RegisterRouter.scala:73:18] assign auto_in_a_ready_0 = nodeIn_a_ready; // @[CLINT.scala:65:9] wire in_valid = nodeIn_a_valid; // @[RegisterRouter.scala:73:18] wire [1:0] in_bits_extra_tlrr_extra_size = nodeIn_a_bits_size; // @[RegisterRouter.scala:73:18] wire [12:0] in_bits_extra_tlrr_extra_source = nodeIn_a_bits_source; // @[RegisterRouter.scala:73:18] wire [7:0] in_bits_mask = nodeIn_a_bits_mask; // @[RegisterRouter.scala:73:18] wire [63:0] in_bits_data = nodeIn_a_bits_data; // @[RegisterRouter.scala:73:18] wire out_ready = nodeIn_d_ready; // @[RegisterRouter.scala:87:24] wire out_valid; // @[RegisterRouter.scala:87:24] assign auto_in_d_valid_0 = nodeIn_d_valid; // @[CLINT.scala:65:9] assign auto_in_d_bits_opcode_0 = nodeIn_d_bits_opcode; // @[CLINT.scala:65:9] wire [1:0] nodeIn_d_bits_d_size; // @[Edges.scala:792:17] assign auto_in_d_bits_size_0 = nodeIn_d_bits_size; // @[CLINT.scala:65:9] wire [12:0] nodeIn_d_bits_d_source; // @[Edges.scala:792:17] assign auto_in_d_bits_source_0 = nodeIn_d_bits_source; // @[CLINT.scala:65:9] wire [63:0] out_bits_data; // @[RegisterRouter.scala:87:24] assign auto_in_d_bits_data_0 = nodeIn_d_bits_data; // @[CLINT.scala:65:9] wire _intnodeOut_0_T; // @[CLINT.scala:82:37] assign auto_int_out_0_0 = intnodeOut_0; // @[CLINT.scala:65:9] wire _intnodeOut_1_T; // @[CLINT.scala:83:43] assign auto_int_out_1_0 = intnodeOut_1; // @[CLINT.scala:65:9] reg [63:0] time_0; // @[CLINT.scala:73:23] wire [63:0] pad_1 = time_0; // @[RegField.scala:150:19] wire [64:0] _time_T = {1'h0, time_0} + 65'h1; // @[CLINT.scala:73:23, :74:38] wire [63:0] _time_T_1 = _time_T[63:0]; // @[CLINT.scala:74:38] reg [63:0] timecmp_0; // @[CLINT.scala:77:41] wire [63:0] pad = timecmp_0; // @[RegField.scala:150:19] reg ipi_0; // @[CLINT.scala:78:41] assign _intnodeOut_0_T = ipi_0; // @[CLINT.scala:78:41, :82:37] wire _out_T_15 = ipi_0; // @[RegisterRouter.scala:87:24] assign intnodeOut_0 = _intnodeOut_0_T; // @[CLINT.scala:82:37] assign _intnodeOut_1_T = time_0 >= timecmp_0; // @[CLINT.scala:73:23, :77:41, :83:43] assign intnodeOut_1 = _intnodeOut_1_T; // @[CLINT.scala:83:43] wire [7:0] _oldBytes_T = pad[7:0]; // @[RegField.scala:150:19, :151:57] wire [7:0] oldBytes_0 = _oldBytes_T; // @[RegField.scala:151:{47,57}] wire [7:0] _oldBytes_T_1 = pad[15:8]; // @[RegField.scala:150:19, :151:57] wire [7:0] oldBytes_1 = _oldBytes_T_1; // @[RegField.scala:151:{47,57}] wire [7:0] _oldBytes_T_2 = pad[23:16]; // @[RegField.scala:150:19, :151:57] wire [7:0] oldBytes_2 = _oldBytes_T_2; // @[RegField.scala:151:{47,57}] wire [7:0] _oldBytes_T_3 = pad[31:24]; // @[RegField.scala:150:19, :151:57] wire [7:0] oldBytes_3 = _oldBytes_T_3; // @[RegField.scala:151:{47,57}] wire [7:0] _oldBytes_T_4 = pad[39:32]; // @[RegField.scala:150:19, :151:57] wire [7:0] oldBytes_4 = _oldBytes_T_4; // @[RegField.scala:151:{47,57}] wire [7:0] _oldBytes_T_5 = pad[47:40]; // @[RegField.scala:150:19, :151:57] wire [7:0] oldBytes_5 = _oldBytes_T_5; // @[RegField.scala:151:{47,57}] wire [7:0] _oldBytes_T_6 = pad[55:48]; // @[RegField.scala:150:19, :151:57] wire [7:0] oldBytes_6 = _oldBytes_T_6; // @[RegField.scala:151:{47,57}] wire [7:0] _oldBytes_T_7 = pad[63:56]; // @[RegField.scala:150:19, :151:57] wire [7:0] oldBytes_7 = _oldBytes_T_7; // @[RegField.scala:151:{47,57}] wire [7:0] _out_T_123 = oldBytes_0; // @[RegisterRouter.scala:87:24] wire [7:0] newBytes_0; // @[RegField.scala:152:31] wire [7:0] newBytes_1; // @[RegField.scala:152:31] wire [7:0] newBytes_2; // @[RegField.scala:152:31] wire [7:0] newBytes_3; // @[RegField.scala:152:31] wire [7:0] newBytes_4; // @[RegField.scala:152:31] wire [7:0] newBytes_5; // @[RegField.scala:152:31] wire [7:0] newBytes_6; // @[RegField.scala:152:31] wire [7:0] newBytes_7; // @[RegField.scala:152:31] wire out_f_woready_10; // @[RegisterRouter.scala:87:24] wire out_f_woready_11; // @[RegisterRouter.scala:87:24] wire out_f_woready_12; // @[RegisterRouter.scala:87:24] wire out_f_woready_13; // @[RegisterRouter.scala:87:24] wire out_f_woready_14; // @[RegisterRouter.scala:87:24] wire out_f_woready_15; // @[RegisterRouter.scala:87:24] wire out_f_woready_16; // @[RegisterRouter.scala:87:24] wire out_f_woready_17; // @[RegisterRouter.scala:87:24] wire valids_0; // @[RegField.scala:153:29] wire valids_1; // @[RegField.scala:153:29] wire valids_2; // @[RegField.scala:153:29] wire valids_3; // @[RegField.scala:153:29] wire valids_4; // @[RegField.scala:153:29] wire valids_5; // @[RegField.scala:153:29] wire valids_6; // @[RegField.scala:153:29] wire valids_7; // @[RegField.scala:153:29] wire [15:0] timecmp_0_lo_lo = {newBytes_1, newBytes_0}; // @[RegField.scala:152:31, :154:52] wire [15:0] timecmp_0_lo_hi = {newBytes_3, newBytes_2}; // @[RegField.scala:152:31, :154:52] wire [31:0] timecmp_0_lo = {timecmp_0_lo_hi, timecmp_0_lo_lo}; // @[RegField.scala:154:52] wire [15:0] timecmp_0_hi_lo = {newBytes_5, newBytes_4}; // @[RegField.scala:152:31, :154:52] wire [15:0] timecmp_0_hi_hi = {newBytes_7, newBytes_6}; // @[RegField.scala:152:31, :154:52] wire [31:0] timecmp_0_hi = {timecmp_0_hi_hi, timecmp_0_hi_lo}; // @[RegField.scala:154:52] wire [63:0] _timecmp_0_T = {timecmp_0_hi, timecmp_0_lo}; // @[RegField.scala:154:52] wire [7:0] _oldBytes_T_8 = pad_1[7:0]; // @[RegField.scala:150:19, :151:57] wire [7:0] oldBytes_1_0 = _oldBytes_T_8; // @[RegField.scala:151:{47,57}] wire [7:0] _oldBytes_T_9 = pad_1[15:8]; // @[RegField.scala:150:19, :151:57] wire [7:0] oldBytes_1_1 = _oldBytes_T_9; // @[RegField.scala:151:{47,57}] wire [7:0] _oldBytes_T_10 = pad_1[23:16]; // @[RegField.scala:150:19, :151:57] wire [7:0] oldBytes_1_2 = _oldBytes_T_10; // @[RegField.scala:151:{47,57}] wire [7:0] _oldBytes_T_11 = pad_1[31:24]; // @[RegField.scala:150:19, :151:57] wire [7:0] oldBytes_1_3 = _oldBytes_T_11; // @[RegField.scala:151:{47,57}] wire [7:0] _oldBytes_T_12 = pad_1[39:32]; // @[RegField.scala:150:19, :151:57] wire [7:0] oldBytes_1_4 = _oldBytes_T_12; // @[RegField.scala:151:{47,57}] wire [7:0] _oldBytes_T_13 = pad_1[47:40]; // @[RegField.scala:150:19, :151:57] wire [7:0] oldBytes_1_5 = _oldBytes_T_13; // @[RegField.scala:151:{47,57}] wire [7:0] _oldBytes_T_14 = pad_1[55:48]; // @[RegField.scala:150:19, :151:57] wire [7:0] oldBytes_1_6 = _oldBytes_T_14; // @[RegField.scala:151:{47,57}] wire [7:0] _oldBytes_T_15 = pad_1[63:56]; // @[RegField.scala:150:19, :151:57] wire [7:0] oldBytes_1_7 = _oldBytes_T_15; // @[RegField.scala:151:{47,57}] wire [7:0] _out_T_35 = oldBytes_1_0; // @[RegisterRouter.scala:87:24] wire [7:0] newBytes_1_0; // @[RegField.scala:152:31] wire [7:0] newBytes_1_1; // @[RegField.scala:152:31] wire [7:0] newBytes_1_2; // @[RegField.scala:152:31] wire [7:0] newBytes_1_3; // @[RegField.scala:152:31] wire [7:0] newBytes_1_4; // @[RegField.scala:152:31] wire [7:0] newBytes_1_5; // @[RegField.scala:152:31] wire [7:0] newBytes_1_6; // @[RegField.scala:152:31] wire [7:0] newBytes_1_7; // @[RegField.scala:152:31] wire out_f_woready_2; // @[RegisterRouter.scala:87:24] wire out_f_woready_3; // @[RegisterRouter.scala:87:24] wire out_f_woready_4; // @[RegisterRouter.scala:87:24] wire out_f_woready_5; // @[RegisterRouter.scala:87:24] wire out_f_woready_6; // @[RegisterRouter.scala:87:24] wire out_f_woready_7; // @[RegisterRouter.scala:87:24] wire out_f_woready_8; // @[RegisterRouter.scala:87:24] wire out_f_woready_9; // @[RegisterRouter.scala:87:24] wire valids_1_0; // @[RegField.scala:153:29] wire valids_1_1; // @[RegField.scala:153:29] wire valids_1_2; // @[RegField.scala:153:29] wire valids_1_3; // @[RegField.scala:153:29] wire valids_1_4; // @[RegField.scala:153:29] wire valids_1_5; // @[RegField.scala:153:29] wire valids_1_6; // @[RegField.scala:153:29] wire valids_1_7; // @[RegField.scala:153:29] wire [15:0] time_lo_lo = {newBytes_1_1, newBytes_1_0}; // @[RegField.scala:152:31, :154:52] wire [15:0] time_lo_hi = {newBytes_1_3, newBytes_1_2}; // @[RegField.scala:152:31, :154:52] wire [31:0] time_lo = {time_lo_hi, time_lo_lo}; // @[RegField.scala:154:52] wire [15:0] time_hi_lo = {newBytes_1_5, newBytes_1_4}; // @[RegField.scala:152:31, :154:52] wire [15:0] time_hi_hi = {newBytes_1_7, newBytes_1_6}; // @[RegField.scala:152:31, :154:52] wire [31:0] time_hi = {time_hi_hi, time_hi_lo}; // @[RegField.scala:154:52] wire [63:0] _time_T_2 = {time_hi, time_lo}; // @[RegField.scala:154:52] wire _out_in_ready_T; // @[RegisterRouter.scala:87:24] assign nodeIn_a_ready = in_ready; // @[RegisterRouter.scala:73:18] wire _in_bits_read_T; // @[RegisterRouter.scala:74:36] wire _out_front_valid_T = in_valid; // @[RegisterRouter.scala:73:18, :87:24] wire out_front_bits_read = in_bits_read; // @[RegisterRouter.scala:73:18, :87:24] wire [12:0] out_front_bits_index = in_bits_index; // @[RegisterRouter.scala:73:18, :87:24] wire [63:0] out_front_bits_data = in_bits_data; // @[RegisterRouter.scala:73:18, :87:24] wire [7:0] out_front_bits_mask = in_bits_mask; // @[RegisterRouter.scala:73:18, :87:24] wire [12:0] out_front_bits_extra_tlrr_extra_source = in_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:73:18, :87:24] wire [1:0] out_front_bits_extra_tlrr_extra_size = in_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:73:18, :87:24] assign _in_bits_read_T = nodeIn_a_bits_opcode == 3'h4; // @[RegisterRouter.scala:74:36] assign in_bits_read = _in_bits_read_T; // @[RegisterRouter.scala:73:18, :74:36] wire [22:0] _in_bits_index_T = nodeIn_a_bits_address[25:3]; // @[Edges.scala:192:34] assign in_bits_index = _in_bits_index_T[12:0]; // @[RegisterRouter.scala:73:18, :75:19] wire _out_front_ready_T = out_ready; // @[RegisterRouter.scala:87:24] wire _out_out_valid_T; // @[RegisterRouter.scala:87:24] assign nodeIn_d_valid = out_valid; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_T_4; // @[RegisterRouter.scala:87:24] wire _nodeIn_d_bits_opcode_T = out_bits_read; // @[RegisterRouter.scala:87:24, :105:25] assign nodeIn_d_bits_data = out_bits_data; // @[RegisterRouter.scala:87:24] assign nodeIn_d_bits_d_source = out_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:87:24] wire [1:0] out_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:87:24] assign nodeIn_d_bits_d_size = out_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:87:24] assign _out_in_ready_T = out_front_ready; // @[RegisterRouter.scala:87:24] assign _out_out_valid_T = out_front_valid; // @[RegisterRouter.scala:87:24] assign out_bits_read = out_front_bits_read; // @[RegisterRouter.scala:87:24] assign out_bits_extra_tlrr_extra_source = out_front_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:87:24] assign out_bits_extra_tlrr_extra_size = out_front_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:87:24] wire [12:0] _GEN = out_front_bits_index & 13'h7FF; // @[RegisterRouter.scala:87:24] wire [12:0] out_findex; // @[RegisterRouter.scala:87:24] assign out_findex = _GEN; // @[RegisterRouter.scala:87:24] wire [12:0] out_bindex; // @[RegisterRouter.scala:87:24] assign out_bindex = _GEN; // @[RegisterRouter.scala:87:24] wire _GEN_0 = out_findex == 13'h0; // @[RegisterRouter.scala:87:24] wire _out_T; // @[RegisterRouter.scala:87:24] assign _out_T = _GEN_0; // @[RegisterRouter.scala:87:24] wire _out_T_4; // @[RegisterRouter.scala:87:24] assign _out_T_4 = _GEN_0; // @[RegisterRouter.scala:87:24] wire _GEN_1 = out_bindex == 13'h0; // @[RegisterRouter.scala:87:24] wire _out_T_1; // @[RegisterRouter.scala:87:24] assign _out_T_1 = _GEN_1; // @[RegisterRouter.scala:87:24] wire _out_T_5; // @[RegisterRouter.scala:87:24] assign _out_T_5 = _GEN_1; // @[RegisterRouter.scala:87:24] wire _out_out_bits_data_WIRE_0 = _out_T_1; // @[MuxLiteral.scala:49:48] wire _out_T_2 = out_findex == 13'h7FF; // @[RegisterRouter.scala:87:24] wire _out_T_3 = out_bindex == 13'h7FF; // @[RegisterRouter.scala:87:24] wire _out_out_bits_data_WIRE_2 = _out_T_3; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24] wire _out_out_bits_data_WIRE_1 = _out_T_5; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_T_11; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_7; // @[RegisterRouter.scala:87:24] wire out_rivalid_0; // @[RegisterRouter.scala:87:24] wire out_rivalid_1; // @[RegisterRouter.scala:87:24] wire out_rivalid_2; // @[RegisterRouter.scala:87:24] wire out_rivalid_3; // @[RegisterRouter.scala:87:24] wire out_rivalid_4; // @[RegisterRouter.scala:87:24] wire out_rivalid_5; // @[RegisterRouter.scala:87:24] wire out_rivalid_6; // @[RegisterRouter.scala:87:24] wire out_rivalid_7; // @[RegisterRouter.scala:87:24] wire out_rivalid_8; // @[RegisterRouter.scala:87:24] wire out_rivalid_9; // @[RegisterRouter.scala:87:24] wire out_rivalid_10; // @[RegisterRouter.scala:87:24] wire out_rivalid_11; // @[RegisterRouter.scala:87:24] wire out_rivalid_12; // @[RegisterRouter.scala:87:24] wire out_rivalid_13; // @[RegisterRouter.scala:87:24] wire out_rivalid_14; // @[RegisterRouter.scala:87:24] wire out_rivalid_15; // @[RegisterRouter.scala:87:24] wire out_rivalid_16; // @[RegisterRouter.scala:87:24] wire out_rivalid_17; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_12; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_8; // @[RegisterRouter.scala:87:24] wire out_wivalid_0; // @[RegisterRouter.scala:87:24] wire out_wivalid_1; // @[RegisterRouter.scala:87:24] wire out_wivalid_2; // @[RegisterRouter.scala:87:24] wire out_wivalid_3; // @[RegisterRouter.scala:87:24] wire out_wivalid_4; // @[RegisterRouter.scala:87:24] wire out_wivalid_5; // @[RegisterRouter.scala:87:24] wire out_wivalid_6; // @[RegisterRouter.scala:87:24] wire out_wivalid_7; // @[RegisterRouter.scala:87:24] wire out_wivalid_8; // @[RegisterRouter.scala:87:24] wire out_wivalid_9; // @[RegisterRouter.scala:87:24] wire out_wivalid_10; // @[RegisterRouter.scala:87:24] wire out_wivalid_11; // @[RegisterRouter.scala:87:24] wire out_wivalid_12; // @[RegisterRouter.scala:87:24] wire out_wivalid_13; // @[RegisterRouter.scala:87:24] wire out_wivalid_14; // @[RegisterRouter.scala:87:24] wire out_wivalid_15; // @[RegisterRouter.scala:87:24] wire out_wivalid_16; // @[RegisterRouter.scala:87:24] wire out_wivalid_17; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_11; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_7; // @[RegisterRouter.scala:87:24] wire out_roready_0; // @[RegisterRouter.scala:87:24] wire out_roready_1; // @[RegisterRouter.scala:87:24] wire out_roready_2; // @[RegisterRouter.scala:87:24] wire out_roready_3; // @[RegisterRouter.scala:87:24] wire out_roready_4; // @[RegisterRouter.scala:87:24] wire out_roready_5; // @[RegisterRouter.scala:87:24] wire out_roready_6; // @[RegisterRouter.scala:87:24] wire out_roready_7; // @[RegisterRouter.scala:87:24] wire out_roready_8; // @[RegisterRouter.scala:87:24] wire out_roready_9; // @[RegisterRouter.scala:87:24] wire out_roready_10; // @[RegisterRouter.scala:87:24] wire out_roready_11; // @[RegisterRouter.scala:87:24] wire out_roready_12; // @[RegisterRouter.scala:87:24] wire out_roready_13; // @[RegisterRouter.scala:87:24] wire out_roready_14; // @[RegisterRouter.scala:87:24] wire out_roready_15; // @[RegisterRouter.scala:87:24] wire out_roready_16; // @[RegisterRouter.scala:87:24] wire out_roready_17; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_12; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_8; // @[RegisterRouter.scala:87:24] wire out_woready_0; // @[RegisterRouter.scala:87:24] wire out_woready_1; // @[RegisterRouter.scala:87:24] wire out_woready_2; // @[RegisterRouter.scala:87:24] wire out_woready_3; // @[RegisterRouter.scala:87:24] wire out_woready_4; // @[RegisterRouter.scala:87:24] wire out_woready_5; // @[RegisterRouter.scala:87:24] wire out_woready_6; // @[RegisterRouter.scala:87:24] wire out_woready_7; // @[RegisterRouter.scala:87:24] wire out_woready_8; // @[RegisterRouter.scala:87:24] wire out_woready_9; // @[RegisterRouter.scala:87:24] wire out_woready_10; // @[RegisterRouter.scala:87:24] wire out_woready_11; // @[RegisterRouter.scala:87:24] wire out_woready_12; // @[RegisterRouter.scala:87:24] wire out_woready_13; // @[RegisterRouter.scala:87:24] wire out_woready_14; // @[RegisterRouter.scala:87:24] wire out_woready_15; // @[RegisterRouter.scala:87:24] wire out_woready_16; // @[RegisterRouter.scala:87:24] wire out_woready_17; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T = out_front_bits_mask[0]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T = out_front_bits_mask[0]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_1 = out_front_bits_mask[1]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_1 = out_front_bits_mask[1]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_2 = out_front_bits_mask[2]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_2 = out_front_bits_mask[2]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_3 = out_front_bits_mask[3]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_3 = out_front_bits_mask[3]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_4 = out_front_bits_mask[4]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_4 = out_front_bits_mask[4]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_5 = out_front_bits_mask[5]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_5 = out_front_bits_mask[5]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_6 = out_front_bits_mask[6]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_6 = out_front_bits_mask[6]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_7 = out_front_bits_mask[7]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_7 = out_front_bits_mask[7]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_8 = {8{_out_frontMask_T}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_9 = {8{_out_frontMask_T_1}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_10 = {8{_out_frontMask_T_2}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_11 = {8{_out_frontMask_T_3}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_12 = {8{_out_frontMask_T_4}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_13 = {8{_out_frontMask_T_5}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_14 = {8{_out_frontMask_T_6}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_15 = {8{_out_frontMask_T_7}}; // @[RegisterRouter.scala:87:24] wire [15:0] out_frontMask_lo_lo = {_out_frontMask_T_9, _out_frontMask_T_8}; // @[RegisterRouter.scala:87:24] wire [15:0] out_frontMask_lo_hi = {_out_frontMask_T_11, _out_frontMask_T_10}; // @[RegisterRouter.scala:87:24] wire [31:0] out_frontMask_lo = {out_frontMask_lo_hi, out_frontMask_lo_lo}; // @[RegisterRouter.scala:87:24] wire [15:0] out_frontMask_hi_lo = {_out_frontMask_T_13, _out_frontMask_T_12}; // @[RegisterRouter.scala:87:24] wire [15:0] out_frontMask_hi_hi = {_out_frontMask_T_15, _out_frontMask_T_14}; // @[RegisterRouter.scala:87:24] wire [31:0] out_frontMask_hi = {out_frontMask_hi_hi, out_frontMask_hi_lo}; // @[RegisterRouter.scala:87:24] wire [63:0] out_frontMask = {out_frontMask_hi, out_frontMask_lo}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_8 = {8{_out_backMask_T}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_9 = {8{_out_backMask_T_1}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_10 = {8{_out_backMask_T_2}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_11 = {8{_out_backMask_T_3}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_12 = {8{_out_backMask_T_4}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_13 = {8{_out_backMask_T_5}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_14 = {8{_out_backMask_T_6}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_15 = {8{_out_backMask_T_7}}; // @[RegisterRouter.scala:87:24] wire [15:0] out_backMask_lo_lo = {_out_backMask_T_9, _out_backMask_T_8}; // @[RegisterRouter.scala:87:24] wire [15:0] out_backMask_lo_hi = {_out_backMask_T_11, _out_backMask_T_10}; // @[RegisterRouter.scala:87:24] wire [31:0] out_backMask_lo = {out_backMask_lo_hi, out_backMask_lo_lo}; // @[RegisterRouter.scala:87:24] wire [15:0] out_backMask_hi_lo = {_out_backMask_T_13, _out_backMask_T_12}; // @[RegisterRouter.scala:87:24] wire [15:0] out_backMask_hi_hi = {_out_backMask_T_15, _out_backMask_T_14}; // @[RegisterRouter.scala:87:24] wire [31:0] out_backMask_hi = {out_backMask_hi_hi, out_backMask_hi_lo}; // @[RegisterRouter.scala:87:24] wire [63:0] out_backMask = {out_backMask_hi, out_backMask_lo}; // @[RegisterRouter.scala:87:24] wire _out_rimask_T = out_frontMask[0]; // @[RegisterRouter.scala:87:24] wire _out_wimask_T = out_frontMask[0]; // @[RegisterRouter.scala:87:24] wire out_rimask = _out_rimask_T; // @[RegisterRouter.scala:87:24] wire out_wimask = _out_wimask_T; // @[RegisterRouter.scala:87:24] wire _out_romask_T = out_backMask[0]; // @[RegisterRouter.scala:87:24] wire _out_womask_T = out_backMask[0]; // @[RegisterRouter.scala:87:24] wire out_romask = _out_romask_T; // @[RegisterRouter.scala:87:24] wire out_womask = _out_womask_T; // @[RegisterRouter.scala:87:24] wire out_f_rivalid = out_rivalid_0 & out_rimask; // @[RegisterRouter.scala:87:24] wire _out_T_7 = out_f_rivalid; // @[RegisterRouter.scala:87:24] wire out_f_roready = out_roready_0 & out_romask; // @[RegisterRouter.scala:87:24] wire _out_T_8 = out_f_roready; // @[RegisterRouter.scala:87:24] wire out_f_wivalid = out_wivalid_0 & out_wimask; // @[RegisterRouter.scala:87:24] wire _out_T_9 = out_f_wivalid; // @[RegisterRouter.scala:87:24] wire out_f_woready = out_woready_0 & out_womask; // @[RegisterRouter.scala:87:24] wire _out_T_10 = out_f_woready; // @[RegisterRouter.scala:87:24] wire _out_T_6 = out_front_bits_data[0]; // @[RegisterRouter.scala:87:24] wire _out_T_11 = ~out_rimask; // @[RegisterRouter.scala:87:24] wire _out_T_12 = ~out_wimask; // @[RegisterRouter.scala:87:24] wire _out_T_13 = ~out_romask; // @[RegisterRouter.scala:87:24] wire _out_T_14 = ~out_womask; // @[RegisterRouter.scala:87:24] wire _out_T_16 = _out_T_15; // @[RegisterRouter.scala:87:24] wire _out_prepend_T = _out_T_16; // @[RegisterRouter.scala:87:24] wire [30:0] _out_rimask_T_1 = out_frontMask[31:1]; // @[RegisterRouter.scala:87:24] wire [30:0] _out_wimask_T_1 = out_frontMask[31:1]; // @[RegisterRouter.scala:87:24] wire out_rimask_1 = \|_out_rimask_T_1; // @[RegisterRouter.scala:87:24] wire out_wimask_1 = &_out_wimask_T_1; // @[RegisterRouter.scala:87:24] wire [30:0] _out_romask_T_1 = out_backMask[31:1]; // @[RegisterRouter.scala:87:24] wire [30:0] _out_womask_T_1 = out_backMask[31:1]; // @[RegisterRouter.scala:87:24] wire out_romask_1 = \|_out_romask_T_1; // @[RegisterRouter.scala:87:24] wire out_womask_1 = &_out_womask_T_1; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1 = out_rivalid_1 & out_rimask_1; // @[RegisterRouter.scala:87:24] wire _out_T_18 = out_f_rivalid_1; // @[RegisterRouter.scala:87:24] wire out_f_roready_1 = out_roready_1 & out_romask_1; // @[RegisterRouter.scala:87:24] wire _out_T_19 = out_f_roready_1; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1 = out_wivalid_1 & out_wimask_1; // @[RegisterRouter.scala:87:24] wire out_f_woready_1 = out_woready_1 & out_womask_1; // @[RegisterRouter.scala:87:24] wire [30:0] _out_T_17 = out_front_bits_data[31:1]; // @[RegisterRouter.scala:87:24] wire _out_T_20 = ~out_rimask_1; // @[RegisterRouter.scala:87:24] wire _out_T_21 = ~out_wimask_1; // @[RegisterRouter.scala:87:24] wire _out_T_22 = ~out_romask_1; // @[RegisterRouter.scala:87:24] wire _out_T_23 = ~out_womask_1; // @[RegisterRouter.scala:87:24] wire [1:0] out_prepend = {1'h0, _out_prepend_T}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_24 = {30'h0, out_prepend}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_25 = _out_T_24; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_2 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_2 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_10 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_10 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24] wire out_rimask_2 = \|_out_rimask_T_2; // @[RegisterRouter.scala:87:24] wire out_wimask_2 = &_out_wimask_T_2; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_2 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_2 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_10 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_10 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24] wire out_romask_2 = \|_out_romask_T_2; // @[RegisterRouter.scala:87:24] wire out_womask_2 = &_out_womask_T_2; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_2 = out_rivalid_2 & out_rimask_2; // @[RegisterRouter.scala:87:24] wire _out_T_27 = out_f_rivalid_2; // @[RegisterRouter.scala:87:24] wire out_f_roready_2 = out_roready_2 & out_romask_2; // @[RegisterRouter.scala:87:24] wire _out_T_28 = out_f_roready_2; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_2 = out_wivalid_2 & out_wimask_2; // @[RegisterRouter.scala:87:24] wire _out_T_29 = out_f_wivalid_2; // @[RegisterRouter.scala:87:24] assign out_f_woready_2 = out_woready_2 & out_womask_2; // @[RegisterRouter.scala:87:24] assign valids_1_0 = out_f_woready_2; // @[RegisterRouter.scala:87:24] wire _out_T_30 = out_f_woready_2; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_26 = out_front_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_114 = out_front_bits_data[7:0]; // @[RegisterRouter.scala:87:24] assign newBytes_1_0 = out_f_woready_2 ? _out_T_26 : oldBytes_1_0; // @[RegisterRouter.scala:87:24] wire _out_T_31 = ~out_rimask_2; // @[RegisterRouter.scala:87:24] wire _out_T_32 = ~out_wimask_2; // @[RegisterRouter.scala:87:24] wire _out_T_33 = ~out_romask_2; // @[RegisterRouter.scala:87:24] wire _out_T_34 = ~out_womask_2; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_36 = _out_T_35; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_1 = _out_T_36; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_3 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_3 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_11 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_11 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24] wire out_rimask_3 = \|_out_rimask_T_3; // @[RegisterRouter.scala:87:24] wire out_wimask_3 = &_out_wimask_T_3; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_3 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_3 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_11 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_11 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24] wire out_romask_3 = \|_out_romask_T_3; // @[RegisterRouter.scala:87:24] wire out_womask_3 = &_out_womask_T_3; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_3 = out_rivalid_3 & out_rimask_3; // @[RegisterRouter.scala:87:24] wire _out_T_38 = out_f_rivalid_3; // @[RegisterRouter.scala:87:24] wire out_f_roready_3 = out_roready_3 & out_romask_3; // @[RegisterRouter.scala:87:24] wire _out_T_39 = out_f_roready_3; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_3 = out_wivalid_3 & out_wimask_3; // @[RegisterRouter.scala:87:24] wire _out_T_40 = out_f_wivalid_3; // @[RegisterRouter.scala:87:24] assign out_f_woready_3 = out_woready_3 & out_womask_3; // @[RegisterRouter.scala:87:24] assign valids_1_1 = out_f_woready_3; // @[RegisterRouter.scala:87:24] wire _out_T_41 = out_f_woready_3; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_37 = out_front_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_125 = out_front_bits_data[15:8]; // @[RegisterRouter.scala:87:24] assign newBytes_1_1 = out_f_woready_3 ? _out_T_37 : oldBytes_1_1; // @[RegisterRouter.scala:87:24] wire _out_T_42 = ~out_rimask_3; // @[RegisterRouter.scala:87:24] wire _out_T_43 = ~out_wimask_3; // @[RegisterRouter.scala:87:24] wire _out_T_44 = ~out_romask_3; // @[RegisterRouter.scala:87:24] wire _out_T_45 = ~out_womask_3; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_1 = {oldBytes_1_1, _out_prepend_T_1}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_46 = out_prepend_1; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_47 = _out_T_46; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_2 = _out_T_47; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_4 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_4 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_12 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_12 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24] wire out_rimask_4 = \|_out_rimask_T_4; // @[RegisterRouter.scala:87:24] wire out_wimask_4 = &_out_wimask_T_4; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_4 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_4 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_12 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_12 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24] wire out_romask_4 = \|_out_romask_T_4; // @[RegisterRouter.scala:87:24] wire out_womask_4 = &_out_womask_T_4; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_4 = out_rivalid_4 & out_rimask_4; // @[RegisterRouter.scala:87:24] wire _out_T_49 = out_f_rivalid_4; // @[RegisterRouter.scala:87:24] wire out_f_roready_4 = out_roready_4 & out_romask_4; // @[RegisterRouter.scala:87:24] wire _out_T_50 = out_f_roready_4; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_4 = out_wivalid_4 & out_wimask_4; // @[RegisterRouter.scala:87:24] wire _out_T_51 = out_f_wivalid_4; // @[RegisterRouter.scala:87:24] assign out_f_woready_4 = out_woready_4 & out_womask_4; // @[RegisterRouter.scala:87:24] assign valids_1_2 = out_f_woready_4; // @[RegisterRouter.scala:87:24] wire _out_T_52 = out_f_woready_4; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_48 = out_front_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_136 = out_front_bits_data[23:16]; // @[RegisterRouter.scala:87:24] assign newBytes_1_2 = out_f_woready_4 ? _out_T_48 : oldBytes_1_2; // @[RegisterRouter.scala:87:24] wire _out_T_53 = ~out_rimask_4; // @[RegisterRouter.scala:87:24] wire _out_T_54 = ~out_wimask_4; // @[RegisterRouter.scala:87:24] wire _out_T_55 = ~out_romask_4; // @[RegisterRouter.scala:87:24] wire _out_T_56 = ~out_womask_4; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_2 = {oldBytes_1_2, _out_prepend_T_2}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_57 = out_prepend_2; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_58 = _out_T_57; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_3 = _out_T_58; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_5 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_5 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_13 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_13 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24] wire out_rimask_5 = \|_out_rimask_T_5; // @[RegisterRouter.scala:87:24] wire out_wimask_5 = &_out_wimask_T_5; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_5 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_5 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_13 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_13 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24] wire out_romask_5 = \|_out_romask_T_5; // @[RegisterRouter.scala:87:24] wire out_womask_5 = &_out_womask_T_5; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_5 = out_rivalid_5 & out_rimask_5; // @[RegisterRouter.scala:87:24] wire _out_T_60 = out_f_rivalid_5; // @[RegisterRouter.scala:87:24] wire out_f_roready_5 = out_roready_5 & out_romask_5; // @[RegisterRouter.scala:87:24] wire _out_T_61 = out_f_roready_5; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_5 = out_wivalid_5 & out_wimask_5; // @[RegisterRouter.scala:87:24] wire _out_T_62 = out_f_wivalid_5; // @[RegisterRouter.scala:87:24] assign out_f_woready_5 = out_woready_5 & out_womask_5; // @[RegisterRouter.scala:87:24] assign valids_1_3 = out_f_woready_5; // @[RegisterRouter.scala:87:24] wire _out_T_63 = out_f_woready_5; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_59 = out_front_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_147 = out_front_bits_data[31:24]; // @[RegisterRouter.scala:87:24] assign newBytes_1_3 = out_f_woready_5 ? _out_T_59 : oldBytes_1_3; // @[RegisterRouter.scala:87:24] wire _out_T_64 = ~out_rimask_5; // @[RegisterRouter.scala:87:24] wire _out_T_65 = ~out_wimask_5; // @[RegisterRouter.scala:87:24] wire _out_T_66 = ~out_romask_5; // @[RegisterRouter.scala:87:24] wire _out_T_67 = ~out_womask_5; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_3 = {oldBytes_1_3, _out_prepend_T_3}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_68 = out_prepend_3; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_69 = _out_T_68; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_4 = _out_T_69; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_6 = out_frontMask[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_6 = out_frontMask[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_14 = out_frontMask[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_14 = out_frontMask[39:32]; // @[RegisterRouter.scala:87:24] wire out_rimask_6 = \|_out_rimask_T_6; // @[RegisterRouter.scala:87:24] wire out_wimask_6 = &_out_wimask_T_6; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_6 = out_backMask[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_6 = out_backMask[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_14 = out_backMask[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_14 = out_backMask[39:32]; // @[RegisterRouter.scala:87:24] wire out_romask_6 = \|_out_romask_T_6; // @[RegisterRouter.scala:87:24] wire out_womask_6 = &_out_womask_T_6; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_6 = out_rivalid_6 & out_rimask_6; // @[RegisterRouter.scala:87:24] wire _out_T_71 = out_f_rivalid_6; // @[RegisterRouter.scala:87:24] wire out_f_roready_6 = out_roready_6 & out_romask_6; // @[RegisterRouter.scala:87:24] wire _out_T_72 = out_f_roready_6; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_6 = out_wivalid_6 & out_wimask_6; // @[RegisterRouter.scala:87:24] wire _out_T_73 = out_f_wivalid_6; // @[RegisterRouter.scala:87:24] assign out_f_woready_6 = out_woready_6 & out_womask_6; // @[RegisterRouter.scala:87:24] assign valids_1_4 = out_f_woready_6; // @[RegisterRouter.scala:87:24] wire _out_T_74 = out_f_woready_6; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_70 = out_front_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_158 = out_front_bits_data[39:32]; // @[RegisterRouter.scala:87:24] assign newBytes_1_4 = out_f_woready_6 ? _out_T_70 : oldBytes_1_4; // @[RegisterRouter.scala:87:24] wire _out_T_75 = ~out_rimask_6; // @[RegisterRouter.scala:87:24] wire _out_T_76 = ~out_wimask_6; // @[RegisterRouter.scala:87:24] wire _out_T_77 = ~out_romask_6; // @[RegisterRouter.scala:87:24] wire _out_T_78 = ~out_womask_6; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_4 = {oldBytes_1_4, _out_prepend_T_4}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_79 = out_prepend_4; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_80 = _out_T_79; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_5 = _out_T_80; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_7 = out_frontMask[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_7 = out_frontMask[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_15 = out_frontMask[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_15 = out_frontMask[47:40]; // @[RegisterRouter.scala:87:24] wire out_rimask_7 = \|_out_rimask_T_7; // @[RegisterRouter.scala:87:24] wire out_wimask_7 = &_out_wimask_T_7; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_7 = out_backMask[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_7 = out_backMask[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_15 = out_backMask[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_15 = out_backMask[47:40]; // @[RegisterRouter.scala:87:24] wire out_romask_7 = \|_out_romask_T_7; // @[RegisterRouter.scala:87:24] wire out_womask_7 = &_out_womask_T_7; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_7 = out_rivalid_7 & out_rimask_7; // @[RegisterRouter.scala:87:24] wire _out_T_82 = out_f_rivalid_7; // @[RegisterRouter.scala:87:24] wire out_f_roready_7 = out_roready_7 & out_romask_7; // @[RegisterRouter.scala:87:24] wire _out_T_83 = out_f_roready_7; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_7 = out_wivalid_7 & out_wimask_7; // @[RegisterRouter.scala:87:24] wire _out_T_84 = out_f_wivalid_7; // @[RegisterRouter.scala:87:24] assign out_f_woready_7 = out_woready_7 & out_womask_7; // @[RegisterRouter.scala:87:24] assign valids_1_5 = out_f_woready_7; // @[RegisterRouter.scala:87:24] wire _out_T_85 = out_f_woready_7; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_81 = out_front_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_169 = out_front_bits_data[47:40]; // @[RegisterRouter.scala:87:24] assign newBytes_1_5 = out_f_woready_7 ? _out_T_81 : oldBytes_1_5; // @[RegisterRouter.scala:87:24] wire _out_T_86 = ~out_rimask_7; // @[RegisterRouter.scala:87:24] wire _out_T_87 = ~out_wimask_7; // @[RegisterRouter.scala:87:24] wire _out_T_88 = ~out_romask_7; // @[RegisterRouter.scala:87:24] wire _out_T_89 = ~out_womask_7; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_5 = {oldBytes_1_5, _out_prepend_T_5}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_90 = out_prepend_5; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_91 = _out_T_90; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_6 = _out_T_91; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_8 = out_frontMask[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_8 = out_frontMask[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_16 = out_frontMask[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_16 = out_frontMask[55:48]; // @[RegisterRouter.scala:87:24] wire out_rimask_8 = \|_out_rimask_T_8; // @[RegisterRouter.scala:87:24] wire out_wimask_8 = &_out_wimask_T_8; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_8 = out_backMask[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_8 = out_backMask[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_16 = out_backMask[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_16 = out_backMask[55:48]; // @[RegisterRouter.scala:87:24] wire out_romask_8 = \|_out_romask_T_8; // @[RegisterRouter.scala:87:24] wire out_womask_8 = &_out_womask_T_8; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_8 = out_rivalid_8 & out_rimask_8; // @[RegisterRouter.scala:87:24] wire _out_T_93 = out_f_rivalid_8; // @[RegisterRouter.scala:87:24] wire out_f_roready_8 = out_roready_8 & out_romask_8; // @[RegisterRouter.scala:87:24] wire _out_T_94 = out_f_roready_8; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_8 = out_wivalid_8 & out_wimask_8; // @[RegisterRouter.scala:87:24] wire _out_T_95 = out_f_wivalid_8; // @[RegisterRouter.scala:87:24] assign out_f_woready_8 = out_woready_8 & out_womask_8; // @[RegisterRouter.scala:87:24] assign valids_1_6 = out_f_woready_8; // @[RegisterRouter.scala:87:24] wire _out_T_96 = out_f_woready_8; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_92 = out_front_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_180 = out_front_bits_data[55:48]; // @[RegisterRouter.scala:87:24] assign newBytes_1_6 = out_f_woready_8 ? _out_T_92 : oldBytes_1_6; // @[RegisterRouter.scala:87:24] wire _out_T_97 = ~out_rimask_8; // @[RegisterRouter.scala:87:24] wire _out_T_98 = ~out_wimask_8; // @[RegisterRouter.scala:87:24] wire _out_T_99 = ~out_romask_8; // @[RegisterRouter.scala:87:24] wire _out_T_100 = ~out_womask_8; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_6 = {oldBytes_1_6, _out_prepend_T_6}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_101 = out_prepend_6; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_102 = _out_T_101; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_7 = _out_T_102; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_9 = out_frontMask[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_9 = out_frontMask[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_17 = out_frontMask[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_17 = out_frontMask[63:56]; // @[RegisterRouter.scala:87:24] wire out_rimask_9 = \|_out_rimask_T_9; // @[RegisterRouter.scala:87:24] wire out_wimask_9 = &_out_wimask_T_9; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_9 = out_backMask[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_9 = out_backMask[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_17 = out_backMask[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_17 = out_backMask[63:56]; // @[RegisterRouter.scala:87:24] wire out_romask_9 = \|_out_romask_T_9; // @[RegisterRouter.scala:87:24] wire out_womask_9 = &_out_womask_T_9; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_9 = out_rivalid_9 & out_rimask_9; // @[RegisterRouter.scala:87:24] wire _out_T_104 = out_f_rivalid_9; // @[RegisterRouter.scala:87:24] wire out_f_roready_9 = out_roready_9 & out_romask_9; // @[RegisterRouter.scala:87:24] wire _out_T_105 = out_f_roready_9; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_9 = out_wivalid_9 & out_wimask_9; // @[RegisterRouter.scala:87:24] wire _out_T_106 = out_f_wivalid_9; // @[RegisterRouter.scala:87:24] assign out_f_woready_9 = out_woready_9 & out_womask_9; // @[RegisterRouter.scala:87:24] assign valids_1_7 = out_f_woready_9; // @[RegisterRouter.scala:87:24] wire _out_T_107 = out_f_woready_9; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_103 = out_front_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_191 = out_front_bits_data[63:56]; // @[RegisterRouter.scala:87:24] assign newBytes_1_7 = out_f_woready_9 ? _out_T_103 : oldBytes_1_7; // @[RegisterRouter.scala:87:24] wire _out_T_108 = ~out_rimask_9; // @[RegisterRouter.scala:87:24] wire _out_T_109 = ~out_wimask_9; // @[RegisterRouter.scala:87:24] wire _out_T_110 = ~out_romask_9; // @[RegisterRouter.scala:87:24] wire _out_T_111 = ~out_womask_9; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_7 = {oldBytes_1_7, _out_prepend_T_7}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_112 = out_prepend_7; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_113 = _out_T_112; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_1_2 = _out_T_113; // @[MuxLiteral.scala:49:48] wire out_rimask_10 = \|_out_rimask_T_10; // @[RegisterRouter.scala:87:24] wire out_wimask_10 = &_out_wimask_T_10; // @[RegisterRouter.scala:87:24] wire out_romask_10 = \|_out_romask_T_10; // @[RegisterRouter.scala:87:24] wire out_womask_10 = &_out_womask_T_10; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_10 = out_rivalid_10 & out_rimask_10; // @[RegisterRouter.scala:87:24] wire _out_T_115 = out_f_rivalid_10; // @[RegisterRouter.scala:87:24] wire out_f_roready_10 = out_roready_10 & out_romask_10; // @[RegisterRouter.scala:87:24] wire _out_T_116 = out_f_roready_10; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_10 = out_wivalid_10 & out_wimask_10; // @[RegisterRouter.scala:87:24] wire _out_T_117 = out_f_wivalid_10; // @[RegisterRouter.scala:87:24] assign out_f_woready_10 = out_woready_10 & out_womask_10; // @[RegisterRouter.scala:87:24] assign valids_0 = out_f_woready_10; // @[RegisterRouter.scala:87:24] wire _out_T_118 = out_f_woready_10; // @[RegisterRouter.scala:87:24] assign newBytes_0 = out_f_woready_10 ? _out_T_114 : oldBytes_0; // @[RegisterRouter.scala:87:24] wire _out_T_119 = ~out_rimask_10; // @[RegisterRouter.scala:87:24] wire _out_T_120 = ~out_wimask_10; // @[RegisterRouter.scala:87:24] wire _out_T_121 = ~out_romask_10; // @[RegisterRouter.scala:87:24] wire _out_T_122 = ~out_womask_10; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_124 = _out_T_123; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_8 = _out_T_124; // @[RegisterRouter.scala:87:24] wire out_rimask_11 = \|_out_rimask_T_11; // @[RegisterRouter.scala:87:24] wire out_wimask_11 = &_out_wimask_T_11; // @[RegisterRouter.scala:87:24] wire out_romask_11 = \|_out_romask_T_11; // @[RegisterRouter.scala:87:24] wire out_womask_11 = &_out_womask_T_11; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_11 = out_rivalid_11 & out_rimask_11; // @[RegisterRouter.scala:87:24] wire _out_T_126 = out_f_rivalid_11; // @[RegisterRouter.scala:87:24] wire out_f_roready_11 = out_roready_11 & out_romask_11; // @[RegisterRouter.scala:87:24] wire _out_T_127 = out_f_roready_11; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_11 = out_wivalid_11 & out_wimask_11; // @[RegisterRouter.scala:87:24] wire _out_T_128 = out_f_wivalid_11; // @[RegisterRouter.scala:87:24] assign out_f_woready_11 = out_woready_11 & out_womask_11; // @[RegisterRouter.scala:87:24] assign valids_1 = out_f_woready_11; // @[RegisterRouter.scala:87:24] wire _out_T_129 = out_f_woready_11; // @[RegisterRouter.scala:87:24] assign newBytes_1 = out_f_woready_11 ? _out_T_125 : oldBytes_1; // @[RegisterRouter.scala:87:24] wire _out_T_130 = ~out_rimask_11; // @[RegisterRouter.scala:87:24] wire _out_T_131 = ~out_wimask_11; // @[RegisterRouter.scala:87:24] wire _out_T_132 = ~out_romask_11; // @[RegisterRouter.scala:87:24] wire _out_T_133 = ~out_womask_11; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_8 = {oldBytes_1, _out_prepend_T_8}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_134 = out_prepend_8; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_135 = _out_T_134; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_9 = _out_T_135; // @[RegisterRouter.scala:87:24] wire out_rimask_12 = \|_out_rimask_T_12; // @[RegisterRouter.scala:87:24] wire out_wimask_12 = &_out_wimask_T_12; // @[RegisterRouter.scala:87:24] wire out_romask_12 = \|_out_romask_T_12; // @[RegisterRouter.scala:87:24] wire out_womask_12 = &_out_womask_T_12; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_12 = out_rivalid_12 & out_rimask_12; // @[RegisterRouter.scala:87:24] wire _out_T_137 = out_f_rivalid_12; // @[RegisterRouter.scala:87:24] wire out_f_roready_12 = out_roready_12 & out_romask_12; // @[RegisterRouter.scala:87:24] wire _out_T_138 = out_f_roready_12; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_12 = out_wivalid_12 & out_wimask_12; // @[RegisterRouter.scala:87:24] wire _out_T_139 = out_f_wivalid_12; // @[RegisterRouter.scala:87:24] assign out_f_woready_12 = out_woready_12 & out_womask_12; // @[RegisterRouter.scala:87:24] assign valids_2 = out_f_woready_12; // @[RegisterRouter.scala:87:24] wire _out_T_140 = out_f_woready_12; // @[RegisterRouter.scala:87:24] assign newBytes_2 = out_f_woready_12 ? _out_T_136 : oldBytes_2; // @[RegisterRouter.scala:87:24] wire _out_T_141 = ~out_rimask_12; // @[RegisterRouter.scala:87:24] wire _out_T_142 = ~out_wimask_12; // @[RegisterRouter.scala:87:24] wire _out_T_143 = ~out_romask_12; // @[RegisterRouter.scala:87:24] wire _out_T_144 = ~out_womask_12; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_9 = {oldBytes_2, _out_prepend_T_9}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_145 = out_prepend_9; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_146 = _out_T_145; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_10 = _out_T_146; // @[RegisterRouter.scala:87:24] wire out_rimask_13 = \|_out_rimask_T_13; // @[RegisterRouter.scala:87:24] wire out_wimask_13 = &_out_wimask_T_13; // @[RegisterRouter.scala:87:24] wire out_romask_13 = \|_out_romask_T_13; // @[RegisterRouter.scala:87:24] wire out_womask_13 = &_out_womask_T_13; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_13 = out_rivalid_13 & out_rimask_13; // @[RegisterRouter.scala:87:24] wire _out_T_148 = out_f_rivalid_13; // @[RegisterRouter.scala:87:24] wire out_f_roready_13 = out_roready_13 & out_romask_13; // @[RegisterRouter.scala:87:24] wire _out_T_149 = out_f_roready_13; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_13 = out_wivalid_13 & out_wimask_13; // @[RegisterRouter.scala:87:24] wire _out_T_150 = out_f_wivalid_13; // @[RegisterRouter.scala:87:24] assign out_f_woready_13 = out_woready_13 & out_womask_13; // @[RegisterRouter.scala:87:24] assign valids_3 = out_f_woready_13; // @[RegisterRouter.scala:87:24] wire _out_T_151 = out_f_woready_13; // @[RegisterRouter.scala:87:24] assign newBytes_3 = out_f_woready_13 ? _out_T_147 : oldBytes_3; // @[RegisterRouter.scala:87:24] wire _out_T_152 = ~out_rimask_13; // @[RegisterRouter.scala:87:24] wire _out_T_153 = ~out_wimask_13; // @[RegisterRouter.scala:87:24] wire _out_T_154 = ~out_romask_13; // @[RegisterRouter.scala:87:24] wire _out_T_155 = ~out_womask_13; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_10 = {oldBytes_3, _out_prepend_T_10}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_156 = out_prepend_10; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_157 = _out_T_156; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_11 = _out_T_157; // @[RegisterRouter.scala:87:24] wire out_rimask_14 = \|_out_rimask_T_14; // @[RegisterRouter.scala:87:24] wire out_wimask_14 = &_out_wimask_T_14; // @[RegisterRouter.scala:87:24] wire out_romask_14 = \|_out_romask_T_14; // @[RegisterRouter.scala:87:24] wire out_womask_14 = &_out_womask_T_14; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_14 = out_rivalid_14 & out_rimask_14; // @[RegisterRouter.scala:87:24] wire _out_T_159 = out_f_rivalid_14; // @[RegisterRouter.scala:87:24] wire out_f_roready_14 = out_roready_14 & out_romask_14; // @[RegisterRouter.scala:87:24] wire _out_T_160 = out_f_roready_14; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_14 = out_wivalid_14 & out_wimask_14; // @[RegisterRouter.scala:87:24] wire _out_T_161 = out_f_wivalid_14; // @[RegisterRouter.scala:87:24] assign out_f_woready_14 = out_woready_14 & out_womask_14; // @[RegisterRouter.scala:87:24] assign valids_4 = out_f_woready_14; // @[RegisterRouter.scala:87:24] wire _out_T_162 = out_f_woready_14; // @[RegisterRouter.scala:87:24] assign newBytes_4 = out_f_woready_14 ? _out_T_158 : oldBytes_4; // @[RegisterRouter.scala:87:24] wire _out_T_163 = ~out_rimask_14; // @[RegisterRouter.scala:87:24] wire _out_T_164 = ~out_wimask_14; // @[RegisterRouter.scala:87:24] wire _out_T_165 = ~out_romask_14; // @[RegisterRouter.scala:87:24] wire _out_T_166 = ~out_womask_14; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_11 = {oldBytes_4, _out_prepend_T_11}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_167 = out_prepend_11; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_168 = _out_T_167; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_12 = _out_T_168; // @[RegisterRouter.scala:87:24] wire out_rimask_15 = \|_out_rimask_T_15; // @[RegisterRouter.scala:87:24] wire out_wimask_15 = &_out_wimask_T_15; // @[RegisterRouter.scala:87:24] wire out_romask_15 = \|_out_romask_T_15; // @[RegisterRouter.scala:87:24] wire out_womask_15 = &_out_womask_T_15; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_15 = out_rivalid_15 & out_rimask_15; // @[RegisterRouter.scala:87:24] wire _out_T_170 = out_f_rivalid_15; // @[RegisterRouter.scala:87:24] wire out_f_roready_15 = out_roready_15 & out_romask_15; // @[RegisterRouter.scala:87:24] wire _out_T_171 = out_f_roready_15; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_15 = out_wivalid_15 & out_wimask_15; // @[RegisterRouter.scala:87:24] wire _out_T_172 = out_f_wivalid_15; // @[RegisterRouter.scala:87:24] assign out_f_woready_15 = out_woready_15 & out_womask_15; // @[RegisterRouter.scala:87:24] assign valids_5 = out_f_woready_15; // @[RegisterRouter.scala:87:24] wire _out_T_173 = out_f_woready_15; // @[RegisterRouter.scala:87:24] assign newBytes_5 = out_f_woready_15 ? _out_T_169 : oldBytes_5; // @[RegisterRouter.scala:87:24] wire _out_T_174 = ~out_rimask_15; // @[RegisterRouter.scala:87:24] wire _out_T_175 = ~out_wimask_15; // @[RegisterRouter.scala:87:24] wire _out_T_176 = ~out_romask_15; // @[RegisterRouter.scala:87:24] wire _out_T_177 = ~out_womask_15; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_12 = {oldBytes_5, _out_prepend_T_12}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_178 = out_prepend_12; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_179 = _out_T_178; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_13 = _out_T_179; // @[RegisterRouter.scala:87:24] wire out_rimask_16 = \|_out_rimask_T_16; // @[RegisterRouter.scala:87:24] wire out_wimask_16 = &_out_wimask_T_16; // @[RegisterRouter.scala:87:24] wire out_romask_16 = \|_out_romask_T_16; // @[RegisterRouter.scala:87:24] wire out_womask_16 = &_out_womask_T_16; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_16 = out_rivalid_16 & out_rimask_16; // @[RegisterRouter.scala:87:24] wire _out_T_181 = out_f_rivalid_16; // @[RegisterRouter.scala:87:24] wire out_f_roready_16 = out_roready_16 & out_romask_16; // @[RegisterRouter.scala:87:24] wire _out_T_182 = out_f_roready_16; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_16 = out_wivalid_16 & out_wimask_16; // @[RegisterRouter.scala:87:24] wire _out_T_183 = out_f_wivalid_16; // @[RegisterRouter.scala:87:24] assign out_f_woready_16 = out_woready_16 & out_womask_16; // @[RegisterRouter.scala:87:24] assign valids_6 = out_f_woready_16; // @[RegisterRouter.scala:87:24] wire _out_T_184 = out_f_woready_16; // @[RegisterRouter.scala:87:24] assign newBytes_6 = out_f_woready_16 ? _out_T_180 : oldBytes_6; // @[RegisterRouter.scala:87:24] wire _out_T_185 = ~out_rimask_16; // @[RegisterRouter.scala:87:24] wire _out_T_186 = ~out_wimask_16; // @[RegisterRouter.scala:87:24] wire _out_T_187 = ~out_romask_16; // @[RegisterRouter.scala:87:24] wire _out_T_188 = ~out_womask_16; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_13 = {oldBytes_6, _out_prepend_T_13}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_189 = out_prepend_13; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_190 = _out_T_189; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_14 = _out_T_190; // @[RegisterRouter.scala:87:24] wire out_rimask_17 = \|_out_rimask_T_17; // @[RegisterRouter.scala:87:24] wire out_wimask_17 = &_out_wimask_T_17; // @[RegisterRouter.scala:87:24] wire out_romask_17 = \|_out_romask_T_17; // @[RegisterRouter.scala:87:24] wire out_womask_17 = &_out_womask_T_17; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_17 = out_rivalid_17 & out_rimask_17; // @[RegisterRouter.scala:87:24] wire _out_T_192 = out_f_rivalid_17; // @[RegisterRouter.scala:87:24] wire out_f_roready_17 = out_roready_17 & out_romask_17; // @[RegisterRouter.scala:87:24] wire _out_T_193 = out_f_roready_17; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_17 = out_wivalid_17 & out_wimask_17; // @[RegisterRouter.scala:87:24] wire _out_T_194 = out_f_wivalid_17; // @[RegisterRouter.scala:87:24] assign out_f_woready_17 = out_woready_17 & out_womask_17; // @[RegisterRouter.scala:87:24] assign valids_7 = out_f_woready_17; // @[RegisterRouter.scala:87:24] wire _out_T_195 = out_f_woready_17; // @[RegisterRouter.scala:87:24] assign newBytes_7 = out_f_woready_17 ? _out_T_191 : oldBytes_7; // @[RegisterRouter.scala:87:24] wire _out_T_196 = ~out_rimask_17; // @[RegisterRouter.scala:87:24] wire _out_T_197 = ~out_wimask_17; // @[RegisterRouter.scala:87:24] wire _out_T_198 = ~out_romask_17; // @[RegisterRouter.scala:87:24] wire _out_T_199 = ~out_womask_17; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_14 = {oldBytes_7, _out_prepend_T_14}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_200 = out_prepend_14; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_201 = _out_T_200; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_1_1 = _out_T_201; // @[MuxLiteral.scala:49:48] wire _out_iindex_T = out_front_bits_index[0]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T = out_front_bits_index[0]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_1 = out_front_bits_index[1]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_1 = out_front_bits_index[1]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_2 = out_front_bits_index[2]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_2 = out_front_bits_index[2]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_3 = out_front_bits_index[3]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_3 = out_front_bits_index[3]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_4 = out_front_bits_index[4]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_4 = out_front_bits_index[4]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_5 = out_front_bits_index[5]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_5 = out_front_bits_index[5]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_6 = out_front_bits_index[6]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_6 = out_front_bits_index[6]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_7 = out_front_bits_index[7]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_7 = out_front_bits_index[7]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_8 = out_front_bits_index[8]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_8 = out_front_bits_index[8]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_9 = out_front_bits_index[9]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_9 = out_front_bits_index[9]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_10 = out_front_bits_index[10]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_10 = out_front_bits_index[10]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_11 = out_front_bits_index[11]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_11 = out_front_bits_index[11]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_12 = out_front_bits_index[12]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_12 = out_front_bits_index[12]; // @[RegisterRouter.scala:87:24] wire [1:0] out_iindex = {_out_iindex_T_12, _out_iindex_T_11}; // @[RegisterRouter.scala:87:24] wire [1:0] out_oindex = {_out_oindex_T_12, _out_oindex_T_11}; // @[RegisterRouter.scala:87:24] wire [3:0] _out_frontSel_T = 4'h1 << out_iindex; // @[OneHot.scala:58:35] wire out_frontSel_0 = _out_frontSel_T[0]; // @[OneHot.scala:58:35] wire out_frontSel_1 = _out_frontSel_T[1]; // @[OneHot.scala:58:35] wire out_frontSel_2 = _out_frontSel_T[2]; // @[OneHot.scala:58:35] wire out_frontSel_3 = _out_frontSel_T[3]; // @[OneHot.scala:58:35] wire [3:0] _out_backSel_T = 4'h1 << out_oindex; // @[OneHot.scala:58:35] wire out_backSel_0 = _out_backSel_T[0]; // @[OneHot.scala:58:35] wire out_backSel_1 = _out_backSel_T[1]; // @[OneHot.scala:58:35] wire out_backSel_2 = _out_backSel_T[2]; // @[OneHot.scala:58:35] wire out_backSel_3 = _out_backSel_T[3]; // @[OneHot.scala:58:35] wire _GEN_2 = in_valid & out_front_ready; // @[RegisterRouter.scala:73:18, :87:24] wire _out_rifireMux_T; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T = _GEN_2; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T = _GEN_2; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1 = _out_rifireMux_T & out_front_bits_read; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_2 = _out_rifireMux_T_1 & out_frontSel_0; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_3 = _out_rifireMux_T_2 & _out_T; // @[RegisterRouter.scala:87:24] assign out_rivalid_0 = _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24] assign out_rivalid_1 = _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_4 = ~_out_T; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_6 = _out_rifireMux_T_1 & out_frontSel_1; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_7 = _out_rifireMux_T_6 & _out_T_4; // @[RegisterRouter.scala:87:24] assign out_rivalid_10 = _out_rifireMux_T_7; // @[RegisterRouter.scala:87:24] assign out_rivalid_11 = _out_rifireMux_T_7; // @[RegisterRouter.scala:87:24] assign out_rivalid_12 = _out_rifireMux_T_7; // @[RegisterRouter.scala:87:24] assign out_rivalid_13 = _out_rifireMux_T_7; // @[RegisterRouter.scala:87:24] assign out_rivalid_14 = _out_rifireMux_T_7; // @[RegisterRouter.scala:87:24] assign out_rivalid_15 = _out_rifireMux_T_7; // @[RegisterRouter.scala:87:24] assign out_rivalid_16 = _out_rifireMux_T_7; // @[RegisterRouter.scala:87:24] assign out_rivalid_17 = _out_rifireMux_T_7; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_8 = ~_out_T_4; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_10 = _out_rifireMux_T_1 & out_frontSel_2; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_11 = _out_rifireMux_T_10 & _out_T_2; // @[RegisterRouter.scala:87:24] assign out_rivalid_2 = _out_rifireMux_T_11; // @[RegisterRouter.scala:87:24] assign out_rivalid_3 = _out_rifireMux_T_11; // @[RegisterRouter.scala:87:24] assign out_rivalid_4 = _out_rifireMux_T_11; // @[RegisterRouter.scala:87:24] assign out_rivalid_5 = _out_rifireMux_T_11; // @[RegisterRouter.scala:87:24] assign out_rivalid_6 = _out_rifireMux_T_11; // @[RegisterRouter.scala:87:24] assign out_rivalid_7 = _out_rifireMux_T_11; // @[RegisterRouter.scala:87:24] assign out_rivalid_8 = _out_rifireMux_T_11; // @[RegisterRouter.scala:87:24] assign out_rivalid_9 = _out_rifireMux_T_11; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_12 = ~_out_T_2; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_14 = _out_rifireMux_T_1 & out_frontSel_3; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_15 = _out_rifireMux_T_14; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1 = ~out_front_bits_read; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_2 = _out_wifireMux_T & _out_wifireMux_T_1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_3 = _out_wifireMux_T_2 & out_frontSel_0; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_4 = _out_wifireMux_T_3 & _out_T; // @[RegisterRouter.scala:87:24] assign out_wivalid_0 = _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24] assign out_wivalid_1 = _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_5 = ~_out_T; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_7 = _out_wifireMux_T_2 & out_frontSel_1; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_8 = _out_wifireMux_T_7 & _out_T_4; // @[RegisterRouter.scala:87:24] assign out_wivalid_10 = _out_wifireMux_T_8; // @[RegisterRouter.scala:87:24] assign out_wivalid_11 = _out_wifireMux_T_8; // @[RegisterRouter.scala:87:24] assign out_wivalid_12 = _out_wifireMux_T_8; // @[RegisterRouter.scala:87:24] assign out_wivalid_13 = _out_wifireMux_T_8; // @[RegisterRouter.scala:87:24] assign out_wivalid_14 = _out_wifireMux_T_8; // @[RegisterRouter.scala:87:24] assign out_wivalid_15 = _out_wifireMux_T_8; // @[RegisterRouter.scala:87:24] assign out_wivalid_16 = _out_wifireMux_T_8; // @[RegisterRouter.scala:87:24] assign out_wivalid_17 = _out_wifireMux_T_8; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_9 = ~_out_T_4; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_11 = _out_wifireMux_T_2 & out_frontSel_2; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_12 = _out_wifireMux_T_11 & _out_T_2; // @[RegisterRouter.scala:87:24] assign out_wivalid_2 = _out_wifireMux_T_12; // @[RegisterRouter.scala:87:24] assign out_wivalid_3 = _out_wifireMux_T_12; // @[RegisterRouter.scala:87:24] assign out_wivalid_4 = _out_wifireMux_T_12; // @[RegisterRouter.scala:87:24] assign out_wivalid_5 = _out_wifireMux_T_12; // @[RegisterRouter.scala:87:24] assign out_wivalid_6 = _out_wifireMux_T_12; // @[RegisterRouter.scala:87:24] assign out_wivalid_7 = _out_wifireMux_T_12; // @[RegisterRouter.scala:87:24] assign out_wivalid_8 = _out_wifireMux_T_12; // @[RegisterRouter.scala:87:24] assign out_wivalid_9 = _out_wifireMux_T_12; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_13 = ~_out_T_2; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_15 = _out_wifireMux_T_2 & out_frontSel_3; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_16 = _out_wifireMux_T_15; // @[RegisterRouter.scala:87:24] wire _GEN_3 = out_front_valid & out_ready; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T = _GEN_3; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T = _GEN_3; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1 = _out_rofireMux_T & out_front_bits_read; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_2 = _out_rofireMux_T_1 & out_backSel_0; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_3 = _out_rofireMux_T_2 & _out_T_1; // @[RegisterRouter.scala:87:24] assign out_roready_0 = _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24] assign out_roready_1 = _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_4 = ~_out_T_1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_6 = _out_rofireMux_T_1 & out_backSel_1; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_7 = _out_rofireMux_T_6 & _out_T_5; // @[RegisterRouter.scala:87:24] assign out_roready_10 = _out_rofireMux_T_7; // @[RegisterRouter.scala:87:24] assign out_roready_11 = _out_rofireMux_T_7; // @[RegisterRouter.scala:87:24] assign out_roready_12 = _out_rofireMux_T_7; // @[RegisterRouter.scala:87:24] assign out_roready_13 = _out_rofireMux_T_7; // @[RegisterRouter.scala:87:24] assign out_roready_14 = _out_rofireMux_T_7; // @[RegisterRouter.scala:87:24] assign out_roready_15 = _out_rofireMux_T_7; // @[RegisterRouter.scala:87:24] assign out_roready_16 = _out_rofireMux_T_7; // @[RegisterRouter.scala:87:24] assign out_roready_17 = _out_rofireMux_T_7; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_8 = ~_out_T_5; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_10 = _out_rofireMux_T_1 & out_backSel_2; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_11 = _out_rofireMux_T_10 & _out_T_3; // @[RegisterRouter.scala:87:24] assign out_roready_2 = _out_rofireMux_T_11; // @[RegisterRouter.scala:87:24] assign out_roready_3 = _out_rofireMux_T_11; // @[RegisterRouter.scala:87:24] assign out_roready_4 = _out_rofireMux_T_11; // @[RegisterRouter.scala:87:24] assign out_roready_5 = _out_rofireMux_T_11; // @[RegisterRouter.scala:87:24] assign out_roready_6 = _out_rofireMux_T_11; // @[RegisterRouter.scala:87:24] assign out_roready_7 = _out_rofireMux_T_11; // @[RegisterRouter.scala:87:24] assign out_roready_8 = _out_rofireMux_T_11; // @[RegisterRouter.scala:87:24] assign out_roready_9 = _out_rofireMux_T_11; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_12 = ~_out_T_3; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_14 = _out_rofireMux_T_1 & out_backSel_3; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_15 = _out_rofireMux_T_14; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1 = ~out_front_bits_read; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_2 = _out_wofireMux_T & _out_wofireMux_T_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_3 = _out_wofireMux_T_2 & out_backSel_0; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_4 = _out_wofireMux_T_3 & _out_T_1; // @[RegisterRouter.scala:87:24] assign out_woready_0 = _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24] assign out_woready_1 = _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_5 = ~_out_T_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_7 = _out_wofireMux_T_2 & out_backSel_1; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_8 = _out_wofireMux_T_7 & _out_T_5; // @[RegisterRouter.scala:87:24] assign out_woready_10 = _out_wofireMux_T_8; // @[RegisterRouter.scala:87:24] assign out_woready_11 = _out_wofireMux_T_8; // @[RegisterRouter.scala:87:24] assign out_woready_12 = _out_wofireMux_T_8; // @[RegisterRouter.scala:87:24] assign out_woready_13 = _out_wofireMux_T_8; // @[RegisterRouter.scala:87:24] assign out_woready_14 = _out_wofireMux_T_8; // @[RegisterRouter.scala:87:24] assign out_woready_15 = _out_wofireMux_T_8; // @[RegisterRouter.scala:87:24] assign out_woready_16 = _out_wofireMux_T_8; // @[RegisterRouter.scala:87:24] assign out_woready_17 = _out_wofireMux_T_8; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_9 = ~_out_T_5; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_11 = _out_wofireMux_T_2 & out_backSel_2; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_12 = _out_wofireMux_T_11 & _out_T_3; // @[RegisterRouter.scala:87:24] assign out_woready_2 = _out_wofireMux_T_12; // @[RegisterRouter.scala:87:24] assign out_woready_3 = _out_wofireMux_T_12; // @[RegisterRouter.scala:87:24] assign out_woready_4 = _out_wofireMux_T_12; // @[RegisterRouter.scala:87:24] assign out_woready_5 = _out_wofireMux_T_12; // @[RegisterRouter.scala:87:24] assign out_woready_6 = _out_wofireMux_T_12; // @[RegisterRouter.scala:87:24] assign out_woready_7 = _out_wofireMux_T_12; // @[RegisterRouter.scala:87:24] assign out_woready_8 = _out_wofireMux_T_12; // @[RegisterRouter.scala:87:24] assign out_woready_9 = _out_wofireMux_T_12; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_13 = ~_out_T_3; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_15 = _out_wofireMux_T_2 & out_backSel_3; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_16 = _out_wofireMux_T_15; // @[RegisterRouter.scala:87:24] assign in_ready = _out_in_ready_T; // @[RegisterRouter.scala:73:18, :87:24] assign out_front_valid = _out_front_valid_T; // @[RegisterRouter.scala:87:24] assign out_front_ready = _out_front_ready_T; // @[RegisterRouter.scala:87:24] assign out_valid = _out_out_valid_T; // @[RegisterRouter.scala:87:24] wire [3:0] _GEN_4 = {{1'h1}, {_out_out_bits_data_WIRE_2}, {_out_out_bits_data_WIRE_1}, {_out_out_bits_data_WIRE_0}}; // @[MuxLiteral.scala:49:{10,48}] wire _out_out_bits_data_T_1 = _GEN_4[out_oindex]; // @[MuxLiteral.scala:49:10] wire [63:0] _out_out_bits_data_WIRE_1_0 = {32'h0, _out_T_25}; // @[MuxLiteral.scala:49:48] wire [3:0][63:0] _GEN_5 = {{64'h0}, {_out_out_bits_data_WIRE_1_2}, {_out_out_bits_data_WIRE_1_1}, {_out_out_bits_data_WIRE_1_0}}; // @[MuxLiteral.scala:49:{10,48}] wire [63:0] _out_out_bits_data_T_3 = _GEN_5[out_oindex]; // @[MuxLiteral.scala:49:10] assign _out_out_bits_data_T_4 = _out_out_bits_data_T_1 ? _out_out_bits_data_T_3 : 64'h0; // @[MuxLiteral.scala:49:10] assign out_bits_data = _out_out_bits_data_T_4; // @[RegisterRouter.scala:87:24] assign nodeIn_d_bits_size = nodeIn_d_bits_d_size; // @[Edges.scala:792:17] assign nodeIn_d_bits_source = nodeIn_d_bits_d_source; // @[Edges.scala:792:17] assign nodeIn_d_bits_opcode = {2'h0, _nodeIn_d_bits_opcode_T}; // @[RegisterRouter.scala:105:{19,25}] always @(posedge clock) begin // @[CLINT.scala:65:9] if (reset) begin // @[CLINT.scala:65:9] time_0 <= 64'h0; // @[CLINT.scala:73:23] ipi_0 <= 1'h0; // @[CLINT.scala:78:41] end else begin // @[CLINT.scala:65:9] if (valids_1_0 \| valids_1_1 \| valids_1_2 \| valids_1_3 \| valids_1_4 \| valids_1_5 \| valids_1_6 \| valids_1_7) // @[RegField.scala:153:29, :154:27] time_0 <= _time_T_2; // @[RegField.scala:154:52] else if (io_rtcTick_0) // @[CLINT.scala:65:9] time_0 <= _time_T_1; // @[CLINT.scala:73:23, :74:38] if (out_f_woready) // @[RegisterRouter.scala:87:24] ipi_0 <= _out_T_6; // @[RegisterRouter.scala:87:24] end if (valids_0 \| valids_1 \| valids_2 \| valids_3 \| valids_4 \| valids_5 \| valids_6 \| valids_7) // @[RegField.scala:153:29, :154:27] timecmp_0 <= _timecmp_0_T; // @[RegField.scala:154:52] always @(posedge) TLMonitor_42 monitor ( // @[Nodes.scala:27:25] .clock (clock), .reset (reset), .io_in_a_ready (nodeIn_a_ready), // @[MixedNode.scala:551:17] .io_in_a_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17] .io_in_a_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17] .io_in_a_bits_param (nodeIn_a_bits_param), // @[MixedNode.scala:551:17] .io_in_a_bits_size (nodeIn_a_bits_size), // @[MixedNode.scala:551:17] .io_in_a_bits_source (nodeIn_a_bits_source), // @[MixedNode.scala:551:17] .io_in_a_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17] .io_in_a_bits_mask (nodeIn_a_bits_mask), // @[MixedNode.scala:551:17] .io_in_a_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17] .io_in_a_bits_corrupt (nodeIn_a_bits_corrupt), // @[MixedNode.scala:551:17] .io_in_d_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17] .io_in_d_valid (nodeIn_d_valid), // @[MixedNode.scala:551:17] .io_in_d_bits_opcode (nodeIn_d_bits_opcode), // @[MixedNode.scala:551:17] .io_in_d_bits_size (nodeIn_d_bits_size), // @[MixedNode.scala:551:17] .io_in_d_bits_source (nodeIn_d_bits_source), // @[MixedNode.scala:551:17] .io_in_d_bits_data (nodeIn_d_bits_data) // @[MixedNode.scala:551:17] ); // @[Nodes.scala:27:25] assign auto_int_out_0 = auto_int_out_0_0; // @[CLINT.scala:65:9] assign auto_int_out_1 = auto_int_out_1_0; // @[CLINT.scala:65:9] assign auto_in_a_ready = auto_in_a_ready_0; // @[CLINT.scala:65:9] assign auto_in_d_valid = auto_in_d_valid_0; // @[CLINT.scala:65:9] assign auto_in_d_bits_opcode = auto_in_d_bits_opcode_0; // @[CLINT.scala:65:9] assign auto_in_d_bits_size = auto_in_d_bits_size_0; // @[CLINT.scala:65:9] assign auto_in_d_bits_source = auto_in_d_bits_source_0; // @[CLINT.scala:65:9] assign auto_in_d_bits_data = auto_in_d_bits_data_0; // @[CLINT.scala:65:9] endmodule
Generate the Verilog code corresponding to the following Chisel files. File Monitor.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceLine import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import freechips.rocketchip.diplomacy.EnableMonitors import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode} import freechips.rocketchip.util.PlusArg case class TLMonitorArgs(edge: TLEdge) abstract class TLMonitorBase(args: TLMonitorArgs) extends Module { val io = IO(new Bundle { val in = Input(new TLBundle(args.edge.bundle)) }) def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit legalize(io.in, args.edge, reset) } object TLMonitor { def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = { if (enable) { EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) } } else { node } } } class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args) { require (args.edge.params(TLMonitorStrictMode) \|\| (! args.edge.params(TestplanTestType).formal)) val cover_prop_class = PropertyClass.Default //Like assert but can flip to being an assumption for formal verification def monAssert(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir, cond, message, PropertyClass.Default) } def assume(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir.flip, cond, message, PropertyClass.Default) } def extra = { args.edge.sourceInfo match { case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)" case _ => "" } } def visible(address: UInt, source: UInt, edge: TLEdge) = edge.client.clients.map { c => !c.sourceId.contains(source) \|\| c.visibility.map(_.contains(address)).reduce(_ \|\| _) }.reduce(_ && _) def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = { //switch this flag to turn on diplomacy in error messages def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n" monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra) // Reuse these subexpressions to save some firrtl lines val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility") //The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B //TODO: check for acquireT? when (bundle.opcode === TLMessages.AcquireBlock) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra) } when (bundle.opcode === TLMessages.AcquirePerm) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra) monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra) monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra) monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra) } } def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = { monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra) monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility") // Reuse these subexpressions to save some firrtl lines val address_ok = edge.manager.containsSafe(edge.address(bundle)) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source when (bundle.opcode === TLMessages.Probe) { assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra) assume (address_ok, "'B' channel Probe carries unmanaged address" + extra) assume (legal_source, "'B' channel Probe carries source that is not first source" + extra) assume (is_aligned, "'B' channel Probe address not aligned to size" + extra) assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra) assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra) assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra) monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra) monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra) monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra) monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra) } } def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = { monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val address_ok = edge.manager.containsSafe(edge.address(bundle)) monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility") when (bundle.opcode === TLMessages.ProbeAck) { monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra) } when (bundle.opcode === TLMessages.ProbeAckData) { monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.Release) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra) monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra) } when (bundle.opcode === TLMessages.ReleaseData) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.AccessAck) { monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra) } when (bundle.opcode === TLMessages.HintAck) { monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra) } } def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = { assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val sink_ok = bundle.sink < edge.manager.endSinkId.U val deny_put_ok = edge.manager.mayDenyPut.B val deny_get_ok = edge.manager.mayDenyGet.B when (bundle.opcode === TLMessages.ReleaseAck) { assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra) assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra) assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra) } when (bundle.opcode === TLMessages.Grant) { assume (source_ok, "'D' channel Grant carries invalid source ID" + extra) assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra) assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel Grant is denied" + extra) } when (bundle.opcode === TLMessages.GrantData) { assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra) assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra) assume (!bundle.denied \|\| bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra) assume (deny_get_ok \|\| !bundle.denied, "'D' channel GrantData is denied" + extra) } when (bundle.opcode === TLMessages.AccessAck) { assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel AccessAck is denied" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra) assume (!bundle.denied \|\| bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra) assume (deny_get_ok \|\| !bundle.denied, "'D' channel AccessAckData is denied" + extra) } when (bundle.opcode === TLMessages.HintAck) { assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel HintAck is denied" + extra) } } def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = { val sink_ok = bundle.sink < edge.manager.endSinkId.U monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra) } def legalizeFormat(bundle: TLBundle, edge: TLEdge) = { when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) } when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) } when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) } when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) } } else { monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra) monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra) monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra) } } def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = { val a_first = edge.first(a.bits, a.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (a.valid && !a_first) { monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra) monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra) monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra) monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra) monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra) } when (a.fire && a_first) { opcode := a.bits.opcode param := a.bits.param size := a.bits.size source := a.bits.source address := a.bits.address } } def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = { val b_first = edge.first(b.bits, b.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (b.valid && !b_first) { monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra) monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra) monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra) monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra) monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra) } when (b.fire && b_first) { opcode := b.bits.opcode param := b.bits.param size := b.bits.size source := b.bits.source address := b.bits.address } } def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = { // Symbolic variable val sym_source = Wire(UInt(edge.client.endSourceId.W)) // TODO: Connect sym_source to a fixed value for simulation and to a // free wire in formal sym_source := 0.U // Type casting Int to UInt val maxSourceId = Wire(UInt(edge.client.endSourceId.W)) maxSourceId := edge.client.endSourceId.U // Delayed verison of sym_source val sym_source_d = Reg(UInt(edge.client.endSourceId.W)) sym_source_d := sym_source // These will be constraints for FV setup Property( MonitorDirection.Monitor, (sym_source === sym_source_d), "sym_source should remain stable", PropertyClass.Default) Property( MonitorDirection.Monitor, (sym_source <= maxSourceId), "sym_source should take legal value", PropertyClass.Default) val my_resp_pend = RegInit(false.B) val my_opcode = Reg(UInt()) val my_size = Reg(UInt()) val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire) val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire) val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source) val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source) val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat) val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend) when (my_set_resp_pend) { my_resp_pend := true.B } .elsewhen (my_clr_resp_pend) { my_resp_pend := false.B } when (my_a_first_beat) { my_opcode := bundle.a.bits.opcode my_size := bundle.a.bits.size } val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size) val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode) val my_resp_opcode_legal = Wire(Bool()) when ((my_resp_opcode === TLMessages.Get) \|\| (my_resp_opcode === TLMessages.ArithmeticData) \|\| (my_resp_opcode === TLMessages.LogicalData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData) } .elsewhen ((my_resp_opcode === TLMessages.PutFullData) \|\| (my_resp_opcode === TLMessages.PutPartialData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck) } .otherwise { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck) } monAssert (IfThen(my_resp_pend, !my_a_first_beat), "Request message should not be sent with a source ID, for which a response message" + "is already pending (not received until current cycle) for a prior request message" + "with the same source ID" + extra) assume (IfThen(my_clr_resp_pend, (my_set_resp_pend \|\| my_resp_pend)), "Response message should be accepted with a source ID only if a request message with the" + "same source ID has been accepted or is being accepted in the current cycle" + extra) assume (IfThen(my_d_first_beat, (my_a_first_beat \|\| my_resp_pend)), "Response message should be sent with a source ID only if a request message with the" + "same source ID has been accepted or is being sent in the current cycle" + extra) assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)), "If d_valid is 1, then d_size should be same as a_size of the corresponding request" + "message" + extra) assume (IfThen(my_d_first_beat, my_resp_opcode_legal), "If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" + "request message" + extra) } def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = { val c_first = edge.first(c.bits, c.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (c.valid && !c_first) { monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra) monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra) monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra) monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra) monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra) } when (c.fire && c_first) { opcode := c.bits.opcode param := c.bits.param size := c.bits.size source := c.bits.source address := c.bits.address } } def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = { val d_first = edge.first(d.bits, d.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val sink = Reg(UInt()) val denied = Reg(Bool()) when (d.valid && !d_first) { assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra) assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra) assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra) assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra) assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra) assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra) } when (d.fire && d_first) { opcode := d.bits.opcode param := d.bits.param size := d.bits.size source := d.bits.source sink := d.bits.sink denied := d.bits.denied } } def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = { legalizeMultibeatA(bundle.a, edge) legalizeMultibeatD(bundle.d, edge) if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { legalizeMultibeatB(bundle.b, edge) legalizeMultibeatC(bundle.c, edge) } } //This is left in for almond which doesn't adhere to the tilelink protocol @deprecated("Use legalizeADSource instead if possible","") def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.client.endSourceId.W)) val a_first = edge.first(bundle.a.bits, bundle.a.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val a_set = WireInit(0.U(edge.client.endSourceId.W)) when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) assume((a_set \| inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra) } if (edge.manager.minLatency > 0) { assume(a_set =/= d_clr \|\| !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight \| a_set) & ~d_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") assert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = { val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size) val log_a_size_bus_size = log2Ceil(a_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error inflight.suggestName("inflight") val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) inflight_opcodes.suggestName("inflight_opcodes") val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) inflight_sizes.suggestName("inflight_sizes") val a_first = edge.first(bundle.a.bits, bundle.a.fire) a_first.suggestName("a_first") val d_first = edge.first(bundle.d.bits, bundle.d.fire) d_first.suggestName("d_first") val a_set = WireInit(0.U(edge.client.endSourceId.W)) val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) a_set.suggestName("a_set") a_set_wo_ready.suggestName("a_set_wo_ready") val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) a_opcodes_set.suggestName("a_opcodes_set") val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) a_sizes_set.suggestName("a_sizes_set") val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W)) a_opcode_lookup.suggestName("a_opcode_lookup") a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W)) a_size_lookup.suggestName("a_size_lookup") a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant)) val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant)) val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W)) a_opcodes_set_interm.suggestName("a_opcodes_set_interm") val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W)) a_sizes_set_interm.suggestName("a_sizes_set_interm") when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) { a_set_wo_ready := UIntToOH(bundle.a.bits.source) } when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) \| 1.U a_sizes_set_interm := (bundle.a.bits.size << 1.U) \| 1.U a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U) a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U) monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) d_opcodes_clr.suggestName("d_opcodes_clr") val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) \|\| same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) \|\| (bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra) assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) \|\| (bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra) assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) { assume((!bundle.d.ready) \|\| bundle.a.ready, "ready check") } if (edge.manager.minLatency > 0) { assume(a_set_wo_ready =/= d_clr_wo_ready \|\| !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight \| a_set) & ~d_clr inflight_opcodes := (inflight_opcodes \| a_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes \| a_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = { val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size) val log_c_size_bus_size = log2Ceil(c_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) inflight.suggestName("inflight") inflight_opcodes.suggestName("inflight_opcodes") inflight_sizes.suggestName("inflight_sizes") val c_first = edge.first(bundle.c.bits, bundle.c.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) c_first.suggestName("c_first") d_first.suggestName("d_first") val c_set = WireInit(0.U(edge.client.endSourceId.W)) val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) c_set.suggestName("c_set") c_set_wo_ready.suggestName("c_set_wo_ready") c_opcodes_set.suggestName("c_opcodes_set") c_sizes_set.suggestName("c_sizes_set") val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W)) val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W)) c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U c_opcode_lookup.suggestName("c_opcode_lookup") c_size_lookup.suggestName("c_size_lookup") val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W)) val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W)) c_opcodes_set_interm.suggestName("c_opcodes_set_interm") c_sizes_set_interm.suggestName("c_sizes_set_interm") when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) { c_set_wo_ready := UIntToOH(bundle.c.bits.source) } when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) { c_set := UIntToOH(bundle.c.bits.source) c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) \| 1.U c_sizes_set_interm := (bundle.c.bits.size << 1.U) \| 1.U c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U) c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U) monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra) } val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck \|\| bundle.c.bits.opcode === TLMessages.ProbeAckData val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") d_opcodes_clr.suggestName("d_opcodes_clr") d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) \|\| same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) { assume((!bundle.d.ready) \|\| bundle.c.ready, "ready check") } if (edge.manager.minLatency > 0) { when (c_set_wo_ready.orR) { assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra) } } inflight := (inflight \| c_set) & ~d_clr inflight_opcodes := (inflight_opcodes \| c_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes \| c_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.c.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.manager.endSinkId.W)) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val e_first = true.B val d_set = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) { d_set := UIntToOH(bundle.d.bits.sink) assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra) } val e_clr = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) { e_clr := UIntToOH(bundle.e.bits.sink) monAssert((d_set \| inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra) } // edge.client.minLatency applies to BC, not DE inflight := (inflight \| d_set) & ~e_clr } def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = { val sourceBits = log2Ceil(edge.client.endSourceId) val tooBig = 14 // >16kB worth of flight information gets to be too much if (sourceBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked") } else { if (args.edge.params(TestplanTestType).simulation) { if (args.edge.params(TLMonitorStrictMode)) { legalizeADSource(bundle, edge) legalizeCDSource(bundle, edge) } else { legalizeADSourceOld(bundle, edge) } } if (args.edge.params(TestplanTestType).formal) { legalizeADSourceFormal(bundle, edge) } } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { // legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize... val sinkBits = log2Ceil(edge.manager.endSinkId) if (sinkBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked") } else { legalizeDESink(bundle, edge) } } } def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = { legalizeFormat (bundle, edge) legalizeMultibeat (bundle, edge) legalizeUnique (bundle, edge) } } File Misc.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import scala.math._ class ParameterizedBundle(implicit p: Parameters) extends Bundle trait Clocked extends Bundle { val clock = Clock() val reset = Bool() } object DecoupledHelper { def apply(rvs: Bool) = new DecoupledHelper(rvs) } class DecoupledHelper(val rvs: Seq[Bool]) { def fire(exclude: Bool, includes: Bool) = { require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!") (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _) } def fire() = { rvs.reduce(_ && _) } } object MuxT { def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2)) def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3)) def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4)) } /** Creates a cascade of n MuxTs to search for a key value. / object MuxTLookup { def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } } object ValidMux { def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]): ValidIO[T] = { apply(v1 +: v2.toSeq) } def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = { val out = Wire(Valid(valids.head.bits.cloneType)) out.valid := valids.map(_.valid).reduce(_ \|\| _) out.bits := MuxCase(valids.head.bits, valids.map(v => (v.valid -> v.bits))) out } } object Str { def apply(s: String): UInt = { var i = BigInt(0) require(s.forall(validChar _)) for (c <- s) i = (i << 8) \| c i.U((s.length8).W) } def apply(x: Char): UInt = { require(validChar(x)) x.U(8.W) } def apply(x: UInt): UInt = apply(x, 10) def apply(x: UInt, radix: Int): UInt = { val rad = radix.U val w = x.getWidth require(w > 0) var q = x var s = digit(q % rad) for (i <- 1 until ceil(log(2)/log(radix)w).toInt) { q = q / rad s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s) } s } def apply(x: SInt): UInt = apply(x, 10) def apply(x: SInt, radix: Int): UInt = { val neg = x < 0.S val abs = x.abs.asUInt if (radix != 10) { Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix)) } else { val rad = radix.U val w = abs.getWidth require(w > 0) var q = abs var s = digit(q % rad) var needSign = neg for (i <- 1 until ceil(log(2)/log(radix)w).toInt) { q = q / rad val placeSpace = q === 0.U val space = Mux(needSign, Str('-'), Str(' ')) needSign = needSign && !placeSpace s = Cat(Mux(placeSpace, space, digit(q % rad)), s) } Cat(Mux(needSign, Str('-'), Str(' ')), s) } } private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0) private def validChar(x: Char) = x == (x & 0xFF) } object Split { def apply(x: UInt, n0: Int) = { val w = x.getWidth (x.extract(w-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n2: Int, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } } object Random { def apply(mod: Int, random: UInt): UInt = { if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0) else PriorityEncoder(partition(apply(1 << log2Up(mod8), random), mod)) } def apply(mod: Int): UInt = apply(mod, randomizer) def oneHot(mod: Int, random: UInt): UInt = { if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0)) else PriorityEncoderOH(partition(apply(1 << log2Up(mod8), random), mod)).asUInt } def oneHot(mod: Int): UInt = oneHot(mod, randomizer) private def randomizer = LFSR(16) private def partition(value: UInt, slices: Int) = Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U) } object Majority { def apply(in: Set[Bool]): Bool = { val n = (in.size >> 1) + 1 val clauses = in.subsets(n).map(_.reduce(_ && _)) clauses.reduce(_ \|\| _) } def apply(in: Seq[Bool]): Bool = apply(in.toSet) def apply(in: UInt): Bool = apply(in.asBools.toSet) } object PopCountAtLeast { private def two(x: UInt): (Bool, Bool) = x.getWidth match { case 1 => (x.asBool, false.B) case n => val half = x.getWidth / 2 val (leftOne, leftTwo) = two(x(half - 1, 0)) val (rightOne, rightTwo) = two(x(x.getWidth - 1, half)) (leftOne \|\| rightOne, leftTwo \|\| rightTwo \|\| (leftOne && rightOne)) } def apply(x: UInt, n: Int): Bool = n match { case 0 => true.B case 1 => x.orR case 2 => two(x)._2 case 3 => PopCount(x) >= n.U } } // This gets used everywhere, so make the smallest circuit possible ... // Given an address and size, create a mask of beatBytes size // eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111 // groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01 object MaskGen { def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = { require (groupBy >= 1 && beatBytes >= groupBy) require (isPow2(beatBytes) && isPow2(groupBy)) val lgBytes = log2Ceil(beatBytes) val sizeOH = UIntToOH(lgSize \| 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) \| (groupBy2 - 1).U def helper(i: Int): Seq[(Bool, Bool)] = { if (i == 0) { Seq((lgSize >= lgBytes.asUInt, true.B)) } else { val sub = helper(i-1) val size = sizeOH(lgBytes - i) val bit = addr_lo(lgBytes - i) val nbit = !bit Seq.tabulate (1 << i) { j => val (sub_acc, sub_eq) = sub(j/2) val eq = sub_eq && (if (j % 2 == 1) bit else nbit) val acc = sub_acc \|\| (size && eq) (acc, eq) } } } if (groupBy == beatBytes) 1.U else Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse) } } File PlusArg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.experimental._ import chisel3.util.HasBlackBoxResource @deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05") case class PlusArgInfo(default: BigInt, docstring: String) /** Case class for PlusArg information * * @tparam A scala type of the PlusArg value * @param default optional default value * @param docstring text to include in the help * @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT) / private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String) /* Typeclass for converting a type to a doctype string * @tparam A some type / trait Doctypeable[A] { /* Return the doctype string for some option / def toDoctype(a: Option[A]): String } /* Object containing implementations of the Doctypeable typeclass / object Doctypes { /* Converts an Int => "INT" / implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" } /* Converts a BigInt => "INT" / implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" } /* Converts a String => "STRING" / implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" } } class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map( "FORMAT" -> StringParam(format), "DEFAULT" -> IntParam(default), "WIDTH" -> IntParam(width) )) with HasBlackBoxResource { val io = IO(new Bundle { val out = Output(UInt(width.W)) }) addResource("/vsrc/plusarg_reader.v") } / This wrapper class has no outputs, making it clear it is a simulation-only construct / class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module { val io = IO(new Bundle { val count = Input(UInt(width.W)) }) val max = Module(new plusarg_reader(format, default, docstring, width)).io.out when (max > 0.U) { assert (io.count < max, s"Timeout exceeded: $docstring") } } import Doctypes._ object PlusArg { /* PlusArg("foo") will return 42.U if the simulation is run with +foo=42 * Do not use this as an initial register value. The value is set in an * initial block and thus accessing it from another initial is racey. * Add a docstring to document the arg, which can be dumped in an elaboration * pass. / def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out } /* PlusArg.timeout(name, default, docstring)(count) will use chisel.assert * to kill the simulation when count exceeds the specified integer argument. * Default 0 will never assert. / def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count } } object PlusArgArtefacts { private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty / Add a new PlusArg / @deprecated( "Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05" ) def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring) /* Add a new PlusArg * * @tparam A scala type of the PlusArg value * @param name name for the PlusArg * @param default optional default value * @param docstring text to include in the help / def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit = artefacts = artefacts ++ Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default))) / From plus args, generate help text / private def serializeHelp_cHeader(tab: String = ""): String = artefacts .map{ case(arg, info) => s"""\|$tab+$arg=${info.doctype}\\n\\ \|$tab${" "20}${info.docstring}\\n\\ \|""".stripMargin ++ info.default.map{ case default => s"$tab${" "22}(default=${default})\\n\\\n"}.getOrElse("") }.toSeq.mkString("\\n\\\n") ++ "\"" / From plus args, generate a char array of their names / private def serializeArray_cHeader(tab: String = ""): String = { val prettyTab = tab + " " 44 // Length of 'static const ...' s"${tab}static const char * verilog_plusargs [] = {\\\n" ++ artefacts .map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" } .mkString("")++ s"${prettyTab}0};" } /* Generate C code to be included in emulator.cc that helps with * argument parsing based on available Verilog PlusArgs / def serialize_cHeader(): String = s"""\|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\ \|${serializeHelp_cHeader(" "7)} \|${serializeArray_cHeader()} \|""".stripMargin } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /* Like Vec.apply(idx), but tolerates indices of mismatched width / def extract(idx: UInt): T = x((idx \| 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx \| 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def \| (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a \|\| b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_\|\|_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /* Any Data subtype that has a Bool member named valid. / type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /* converts from camel case to to underscores, also removing all spaces / def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /* converts spaces or underscores to hyphens, also lowering case / def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y \| (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y \|\| y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 \| 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /* Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation / def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.diplomacy import chisel3._ import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor} import freechips.rocketchip.util.ShiftQueue /* Options for describing the attributes of memory regions / object RegionType { // Define the 'more relaxed than' ordering val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS) sealed trait T extends Ordered[T] { def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this) } case object CACHED extends T // an intermediate agent may have cached a copy of the region for you case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively } // A non-empty half-open range; [start, end) case class IdRange(start: Int, end: Int) extends Ordered[IdRange] { require (start >= 0, s"Ids cannot be negative, but got: $start.") require (start <= end, "Id ranges cannot be negative.") def compare(x: IdRange) = { val primary = (this.start - x.start).signum val secondary = (x.end - this.end).signum if (primary != 0) primary else secondary } def overlaps(x: IdRange) = start < x.end && x.start < end def contains(x: IdRange) = start <= x.start && x.end <= end def contains(x: Int) = start <= x && x < end def contains(x: UInt) = if (size == 0) { false.B } else if (size == 1) { // simple comparison x === start.U } else { // find index of largest different bit val largestDeltaBit = log2Floor(start ^ (end-1)) val smallestCommonBit = largestDeltaBit + 1 // may not exist in x val uncommonMask = (1 << smallestCommonBit) - 1 val uncommonBits = (x \| 0.U(smallestCommonBit.W))(largestDeltaBit, 0) // the prefix must match exactly (note: may shift ALL bits away) (x >> smallestCommonBit) === (start >> smallestCommonBit).U && // firrtl constant prop range analysis can eliminate these two: (start & uncommonMask).U <= uncommonBits && uncommonBits <= ((end-1) & uncommonMask).U } def shift(x: Int) = IdRange(start+x, end+x) def size = end - start def isEmpty = end == start def range = start until end } object IdRange { def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else { val ranges = s.sorted (ranges.tail zip ranges.init) find { case (a, b) => a overlaps b } } } // An potentially empty inclusive range of 2-powers [min, max] (in bytes) case class TransferSizes(min: Int, max: Int) { def this(x: Int) = this(x, x) require (min <= max, s"Min transfer $min > max transfer $max") require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)") require (max == 0 \|\| isPow2(max), s"TransferSizes must be a power of 2, got: $max") require (min == 0 \|\| isPow2(min), s"TransferSizes must be a power of 2, got: $min") require (max == 0 \|\| min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)") def none = min == 0 def contains(x: Int) = isPow2(x) && min <= x && x <= max def containsLg(x: Int) = contains(1 << x) def containsLg(x: UInt) = if (none) false.B else if (min == max) { log2Ceil(min).U === x } else { log2Ceil(min).U <= x && x <= log2Ceil(max).U } def contains(x: TransferSizes) = x.none \|\| (min <= x.min && x.max <= max) def intersect(x: TransferSizes) = if (x.max < min \|\| max < x.min) TransferSizes.none else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max)) // Not a union, because the result may contain sizes contained by neither term // NOT TO BE CONFUSED WITH COVERPOINTS def mincover(x: TransferSizes) = { if (none) { x } else if (x.none) { this } else { TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max)) } } override def toString() = "TransferSizes[%d, %d]".format(min, max) } object TransferSizes { def apply(x: Int) = new TransferSizes(x) val none = new TransferSizes(0) def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _) def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _) implicit def asBool(x: TransferSizes) = !x.none } // AddressSets specify the address space managed by the manager // Base is the base address, and mask are the bits consumed by the manager // e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff // e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ... case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet] { // Forbid misaligned base address (and empty sets) require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}") require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous // We do allow negative mask (=> ignore all high bits) def contains(x: BigInt) = ((x ^ base) & ~mask) == 0 def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S // turn x into an address contained in this set def legalize(x: UInt): UInt = base.U \| (mask.U & x) // overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1) def overlaps(x: AddressSet) = (~(mask \| x.mask) & (base ^ x.base)) == 0 // contains iff bitwise: x.mask => mask && contains(x.base) def contains(x: AddressSet) = ((x.mask \| (base ^ x.base)) & ~mask) == 0 // The number of bytes to which the manager must be aligned def alignment = ((mask + 1) & ~mask) // Is this a contiguous memory range def contiguous = alignment == mask+1 def finite = mask >= 0 def max = { require (finite, "Max cannot be calculated on infinite mask"); base \| mask } // Widen the match function to ignore all bits in imask def widen(imask: BigInt) = AddressSet(base & ~imask, mask \| imask) // Return an AddressSet that only contains the addresses both sets contain def intersect(x: AddressSet): Option[AddressSet] = { if (!overlaps(x)) { None } else { val r_mask = mask & x.mask val r_base = base \| x.base Some(AddressSet(r_base, r_mask)) } } def subtract(x: AddressSet): Seq[AddressSet] = { intersect(x) match { case None => Seq(this) case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit => val nmask = (mask & (bit-1)) \| remove.mask val nbase = (remove.base ^ bit) & ~nmask AddressSet(nbase, nmask) } } } // AddressSets have one natural Ordering (the containment order, if contiguous) def compare(x: AddressSet) = { val primary = (this.base - x.base).signum // smallest address first val secondary = (x.mask - this.mask).signum // largest mask first if (primary != 0) primary else secondary } // We always want to see things in hex override def toString() = { if (mask >= 0) { "AddressSet(0x%x, 0x%x)".format(base, mask) } else { "AddressSet(0x%x, ~0x%x)".format(base, ~mask) } } def toRanges = { require (finite, "Ranges cannot be calculated on infinite mask") val size = alignment val fragments = mask & ~(size-1) val bits = bitIndexes(fragments) (BigInt(0) until (BigInt(1) << bits.size)).map { i => val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) } AddressRange(off, size) } } } object AddressSet { val everything = AddressSet(0, -1) def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = { if (size == 0) tail.reverse else { val maxBaseAlignment = base & (-base) // 0 for infinite (LSB) val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size val step = if (maxBaseAlignment == 0 \|\| maxBaseAlignment > maxSizeAlignment) maxSizeAlignment else maxBaseAlignment misaligned(base+step, size-step, AddressSet(base, step-1) +: tail) } } def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = { // Pair terms up by ignoring 'bit' seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) => if (seq.size == 1) { seq.head // singleton -> unaffected } else { key.copy(mask = key.mask \| bit) // pair - widen mask by bit } }.toList } def unify(seq: Seq[AddressSet]): Seq[AddressSet] = { val bits = seq.map(_.base).foldLeft(BigInt(0))(_ \| _) AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted } def enumerateMask(mask: BigInt): Seq[BigInt] = { def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] = if (id == mask) (id +: tail).reverse else helper(((~mask \| id) + 1) & mask, id +: tail) helper(0, Nil) } def enumerateBits(mask: BigInt): Seq[BigInt] = { def helper(x: BigInt): Seq[BigInt] = { if (x == 0) { Nil } else { val bit = x & (-x) bit +: helper(x & ~bit) } } helper(mask) } } case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean) { require (depth >= 0, "Buffer depth must be >= 0") def isDefined = depth > 0 def latency = if (isDefined && !flow) 1 else 0 def apply[T <: Data](x: DecoupledIO[T]) = if (isDefined) Queue(x, depth, flow=flow, pipe=pipe) else x def irrevocable[T <: Data](x: ReadyValidIO[T]) = if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe) else x def sq[T <: Data](x: DecoupledIO[T]) = if (!isDefined) x else { val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe)) sq.io.enq <> x sq.io.deq } override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "") } object BufferParams { implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false) val default = BufferParams(2) val none = BufferParams(0) val flow = BufferParams(1, true, false) val pipe = BufferParams(1, false, true) } case class TriStateValue(value: Boolean, set: Boolean) { def update(orig: Boolean) = if (set) value else orig } object TriStateValue { implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true) def unset = TriStateValue(false, false) } trait DirectedBuffers[T] { def copyIn(x: BufferParams): T def copyOut(x: BufferParams): T def copyInOut(x: BufferParams): T } trait IdMapEntry { def name: String def from: IdRange def to: IdRange def isCache: Boolean def requestFifo: Boolean def maxTransactionsInFlight: Option[Int] def pretty(fmt: String) = if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5 fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } else { fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } } abstract class IdMap[T <: IdMapEntry] { protected val fmt: String val mapping: Seq[T] def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n") } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportPutFull \|\| manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB \|\| manager.anySupportGet \|\| manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportPutFull \|\| client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe \|\| client.anySupportGet \|\| client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet \|\| client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull \|\| client.anySupportPutPartial \|\| client.anySupportHint \|\| client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet \|\| manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull \|\| manager.anySupportPutPartial \|\| manager.anySupportHint \|\| manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) \|\| !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.ProbeAckData \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode \| small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U \|\| beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }	module TLMonitor_60( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [1:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [11:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [11:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [11:0] io_in_d_bits_source // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire a_first_done = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala:51:35] reg a_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [1:0] size; // @[Monitor.scala:389:22] reg [11:0] source; // @[Monitor.scala:390:22] reg [11:0] address; // @[Monitor.scala:391:22] reg d_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] size_1; // @[Monitor.scala:540:22] reg [11:0] source_1; // @[Monitor.scala:541:22] reg [2063:0] inflight; // @[Monitor.scala:614:27] reg [8255:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [8255:0] inflight_sizes; // @[Monitor.scala:618:33] reg a_first_counter_1; // @[Edges.scala:229:27] reg d_first_counter_1; // @[Edges.scala:229:27] wire _GEN = a_first_done & ~a_first_counter_1; // @[Decoupled.scala:51:35] wire d_release_ack = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala:673:46] wire _GEN_0 = io_in_d_bits_opcode != 3'h6; // @[Monitor.scala:673:46, :674:74] reg [31:0] watchdog; // @[Monitor.scala:709:27] reg [2063:0] inflight_1; // @[Monitor.scala:726:35] reg [8255:0] inflight_sizes_1; // @[Monitor.scala:728:35] reg d_first_counter_2; // @[Edges.scala:229:27] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to the following Chisel files. File FIFOFixer.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.lazymodule._ import org.chipsalliance.diplomacy.nodes._ import freechips.rocketchip.diplomacy.RegionType import freechips.rocketchip.util.property class TLFIFOFixer(policy: TLFIFOFixer.Policy = TLFIFOFixer.all)(implicit p: Parameters) extends LazyModule { private def fifoMap(seq: Seq[TLSlaveParameters]) = { val (flatManagers, keepManagers) = seq.partition(policy) // We need to be careful if one flatManager and one keepManager share an existing domain // Erring on the side of caution, we will also flatten the keepManager in this case val flatDomains = Set(flatManagers.flatMap(_.fifoId):_) // => ID 0 val keepDomains = Set(keepManagers.flatMap(_.fifoId):_) -- flatDomains // => IDs compacted // Calculate what the FIFO domains look like after the fixer is applied val flatMap = flatDomains.map { x => (x, 0) }.toMap val keepMap = keepDomains.scanLeft((-1,0)) { case ((_,s),x) => (x, s+1) }.toMap val map = flatMap ++ keepMap val fixMap = seq.map { m => m.fifoId match { case None => if (policy(m)) Some(0) else None case Some(id) => Some(map(id)) // also flattens some who did not ask } } // Compress the FIFO domain space of those we are combining val reMap = flatDomains.scanLeft((-1,-1)) { case ((_,s),x) => (x, s+1) }.toMap val splatMap = seq.map { m => m.fifoId match { case None => None case Some(id) => reMap.lift(id) } } (fixMap, splatMap) } val node = new AdapterNode(TLImp)( { cp => cp }, { mp => val (fixMap, _) = fifoMap(mp.managers) mp.v1copy(managers = (fixMap zip mp.managers) map { case (id, m) => m.v1copy(fifoId = id) }) }) with TLFormatNode { override def circuitIdentity = edges.in.map(_.client.clients.filter(c => c.requestFifo && c.sourceId.size > 1).size).sum == 0 } lazy val module = new Impl class Impl extends LazyModuleImp(this) { (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => val (fixMap, splatMap) = fifoMap(edgeOut.manager.managers) // Do we need to serialize the request to this manager? val a_notFIFO = edgeIn.manager.fastProperty(in.a.bits.address, _.fifoId != Some(0), (b:Boolean) => b.B) // Compact the IDs of the cases we serialize val compacted = ((fixMap zip splatMap) zip edgeOut.manager.managers) flatMap { case ((f, s), m) => if (f == Some(0)) Some(m.v1copy(fifoId = s)) else None } val sinks = if (compacted.exists(_.supportsAcquireB)) edgeOut.manager.endSinkId else 0 val a_id = if (compacted.isEmpty) 0.U else edgeOut.manager.v1copy(managers = compacted, endSinkId = sinks).findFifoIdFast(in.a.bits.address) val a_noDomain = a_id === 0.U if (false) { println(s"FIFOFixer for: ${edgeIn.client.clients.map(_.name).mkString(", ")}") println(s"make FIFO: ${edgeIn.manager.managers.filter(_.fifoId==Some(0)).map(_.name).mkString(", ")}") println(s"not FIFO: ${edgeIn.manager.managers.filter(_.fifoId!=Some(0)).map(_.name).mkString(", ")}") println(s"domains: ${compacted.groupBy(_.name).mapValues(_.map(_.fifoId))}") println("") } // Count beats val a_first = edgeIn.first(in.a) val d_first = edgeOut.first(out.d) && out.d.bits.opcode =/= TLMessages.ReleaseAck // Keep one bit for each source recording if there is an outstanding request that must be made FIFO // Sources unused in the stall signal calculation should be pruned by DCE val flight = RegInit(VecInit(Seq.fill(edgeIn.client.endSourceId) { false.B })) when (a_first && in.a.fire) { flight(in.a.bits.source) := !a_notFIFO } when (d_first && in.d.fire) { flight(in.d.bits.source) := false.B } val stalls = edgeIn.client.clients.filter(c => c.requestFifo && c.sourceId.size > 1).map { c => val a_sel = c.sourceId.contains(in.a.bits.source) val id = RegEnable(a_id, in.a.fire && a_sel && !a_notFIFO) val track = flight.slice(c.sourceId.start, c.sourceId.end) a_sel && a_first && track.reduce(_ \|\| _) && (a_noDomain \|\| id =/= a_id) } val stall = stalls.foldLeft(false.B)(_\|\|_) out.a <> in.a in.d <> out.d out.a.valid := in.a.valid && (a_notFIFO \|\| !stall) in.a.ready := out.a.ready && (a_notFIFO \|\| !stall) if (edgeOut.manager.anySupportAcquireB && edgeOut.client.anySupportProbe) { in .b <> out.b out.c <> in .c out.e <> in .e } else { in.b.valid := false.B in.c.ready := true.B in.e.ready := true.B out.b.ready := true.B out.c.valid := false.B out.e.valid := false.B } //Functional cover properties property.cover(in.a.valid && stall, "COVER FIFOFIXER STALL", "Cover: Stall occured for a valid transaction") val SourceIdFIFOed = RegInit(0.U(edgeIn.client.endSourceId.W)) val SourceIdSet = WireDefault(0.U(edgeIn.client.endSourceId.W)) val SourceIdClear = WireDefault(0.U(edgeIn.client.endSourceId.W)) when (a_first && in.a.fire && !a_notFIFO) { SourceIdSet := UIntToOH(in.a.bits.source) } when (d_first && in.d.fire) { SourceIdClear := UIntToOH(in.d.bits.source) } SourceIdFIFOed := SourceIdFIFOed \| SourceIdSet val allIDs_FIFOed = SourceIdFIFOed===Fill(SourceIdFIFOed.getWidth, 1.U) property.cover(allIDs_FIFOed, "COVER all sources", "Cover: FIFOFIXER covers all Source IDs") //property.cover(flight.reduce(_ && _), "COVER full", "Cover: FIFO is full with all Source IDs") property.cover(!(flight.reduce(_ \|\| _)), "COVER empty", "Cover: FIFO is empty") property.cover(SourceIdSet > 0.U, "COVER at least one push", "Cover: At least one Source ID is pushed") property.cover(SourceIdClear > 0.U, "COVER at least one pop", "Cover: At least one Source ID is popped") } } } object TLFIFOFixer { // Which slaves should have their FIFOness combined? // NOTE: this transformation is still only applied for masters with requestFifo type Policy = TLSlaveParameters => Boolean import RegionType._ val all: Policy = m => true val allFIFO: Policy = m => m.fifoId.isDefined val allVolatile: Policy = m => m.regionType <= VOLATILE def apply(policy: Policy = all)(implicit p: Parameters): TLNode = { val fixer = LazyModule(new TLFIFOFixer(policy)) fixer.node } } File Buffer.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.diplomacy.BufferParams class TLBufferNode ( a: BufferParams, b: BufferParams, c: BufferParams, d: BufferParams, e: BufferParams)(implicit valName: ValName) extends TLAdapterNode( clientFn = { p => p.v1copy(minLatency = p.minLatency + b.latency + c.latency) }, managerFn = { p => p.v1copy(minLatency = p.minLatency + a.latency + d.latency) } ) { override lazy val nodedebugstring = s"a:${a.toString}, b:${b.toString}, c:${c.toString}, d:${d.toString}, e:${e.toString}" override def circuitIdentity = List(a,b,c,d,e).forall(_ == BufferParams.none) } class TLBuffer( a: BufferParams, b: BufferParams, c: BufferParams, d: BufferParams, e: BufferParams)(implicit p: Parameters) extends LazyModule { def this(ace: BufferParams, bd: BufferParams)(implicit p: Parameters) = this(ace, bd, ace, bd, ace) def this(abcde: BufferParams)(implicit p: Parameters) = this(abcde, abcde) def this()(implicit p: Parameters) = this(BufferParams.default) val node = new TLBufferNode(a, b, c, d, e) lazy val module = new Impl class Impl extends LazyModuleImp(this) { def headBundle = node.out.head._2.bundle override def desiredName = (Seq("TLBuffer") ++ node.out.headOption.map(_._2.bundle.shortName)).mkString("_") (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out.a <> a(in .a) in .d <> d(out.d) if (edgeOut.manager.anySupportAcquireB && edgeOut.client.anySupportProbe) { in .b <> b(out.b) out.c <> c(in .c) out.e <> e(in .e) } else { in.b.valid := false.B in.c.ready := true.B in.e.ready := true.B out.b.ready := true.B out.c.valid := false.B out.e.valid := false.B } } } } object TLBuffer { def apply() (implicit p: Parameters): TLNode = apply(BufferParams.default) def apply(abcde: BufferParams) (implicit p: Parameters): TLNode = apply(abcde, abcde) def apply(ace: BufferParams, bd: BufferParams)(implicit p: Parameters): TLNode = apply(ace, bd, ace, bd, ace) def apply( a: BufferParams, b: BufferParams, c: BufferParams, d: BufferParams, e: BufferParams)(implicit p: Parameters): TLNode = { val buffer = LazyModule(new TLBuffer(a, b, c, d, e)) buffer.node } def chain(depth: Int, name: Option[String] = None)(implicit p: Parameters): Seq[TLNode] = { val buffers = Seq.fill(depth) { LazyModule(new TLBuffer()) } name.foreach { n => buffers.zipWithIndex.foreach { case (b, i) => b.suggestName(s"${n}_${i}") } } buffers.map(_.node) } def chainNode(depth: Int, name: Option[String] = None)(implicit p: Parameters): TLNode = { chain(depth, name) .reduceLeftOption(_ := _) .getOrElse(TLNameNode("no_buffer")) } } File Misc.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import scala.math._ class ParameterizedBundle(implicit p: Parameters) extends Bundle trait Clocked extends Bundle { val clock = Clock() val reset = Bool() } object DecoupledHelper { def apply(rvs: Bool) = new DecoupledHelper(rvs) } class DecoupledHelper(val rvs: Seq[Bool]) { def fire(exclude: Bool, includes: Bool) = { require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!") (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _) } def fire() = { rvs.reduce(_ && _) } } object MuxT { def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2)) def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3)) def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4)) } /** Creates a cascade of n MuxTs to search for a key value. / object MuxTLookup { def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } } object ValidMux { def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]): ValidIO[T] = { apply(v1 +: v2.toSeq) } def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = { val out = Wire(Valid(valids.head.bits.cloneType)) out.valid := valids.map(_.valid).reduce(_ \|\| _) out.bits := MuxCase(valids.head.bits, valids.map(v => (v.valid -> v.bits))) out } } object Str { def apply(s: String): UInt = { var i = BigInt(0) require(s.forall(validChar _)) for (c <- s) i = (i << 8) \| c i.U((s.length8).W) } def apply(x: Char): UInt = { require(validChar(x)) x.U(8.W) } def apply(x: UInt): UInt = apply(x, 10) def apply(x: UInt, radix: Int): UInt = { val rad = radix.U val w = x.getWidth require(w > 0) var q = x var s = digit(q % rad) for (i <- 1 until ceil(log(2)/log(radix)w).toInt) { q = q / rad s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s) } s } def apply(x: SInt): UInt = apply(x, 10) def apply(x: SInt, radix: Int): UInt = { val neg = x < 0.S val abs = x.abs.asUInt if (radix != 10) { Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix)) } else { val rad = radix.U val w = abs.getWidth require(w > 0) var q = abs var s = digit(q % rad) var needSign = neg for (i <- 1 until ceil(log(2)/log(radix)w).toInt) { q = q / rad val placeSpace = q === 0.U val space = Mux(needSign, Str('-'), Str(' ')) needSign = needSign && !placeSpace s = Cat(Mux(placeSpace, space, digit(q % rad)), s) } Cat(Mux(needSign, Str('-'), Str(' ')), s) } } private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0) private def validChar(x: Char) = x == (x & 0xFF) } object Split { def apply(x: UInt, n0: Int) = { val w = x.getWidth (x.extract(w-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n2: Int, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } } object Random { def apply(mod: Int, random: UInt): UInt = { if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0) else PriorityEncoder(partition(apply(1 << log2Up(mod8), random), mod)) } def apply(mod: Int): UInt = apply(mod, randomizer) def oneHot(mod: Int, random: UInt): UInt = { if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0)) else PriorityEncoderOH(partition(apply(1 << log2Up(mod8), random), mod)).asUInt } def oneHot(mod: Int): UInt = oneHot(mod, randomizer) private def randomizer = LFSR(16) private def partition(value: UInt, slices: Int) = Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U) } object Majority { def apply(in: Set[Bool]): Bool = { val n = (in.size >> 1) + 1 val clauses = in.subsets(n).map(_.reduce(_ && _)) clauses.reduce(_ \|\| _) } def apply(in: Seq[Bool]): Bool = apply(in.toSet) def apply(in: UInt): Bool = apply(in.asBools.toSet) } object PopCountAtLeast { private def two(x: UInt): (Bool, Bool) = x.getWidth match { case 1 => (x.asBool, false.B) case n => val half = x.getWidth / 2 val (leftOne, leftTwo) = two(x(half - 1, 0)) val (rightOne, rightTwo) = two(x(x.getWidth - 1, half)) (leftOne \|\| rightOne, leftTwo \|\| rightTwo \|\| (leftOne && rightOne)) } def apply(x: UInt, n: Int): Bool = n match { case 0 => true.B case 1 => x.orR case 2 => two(x)._2 case 3 => PopCount(x) >= n.U } } // This gets used everywhere, so make the smallest circuit possible ... // Given an address and size, create a mask of beatBytes size // eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111 // groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01 object MaskGen { def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = { require (groupBy >= 1 && beatBytes >= groupBy) require (isPow2(beatBytes) && isPow2(groupBy)) val lgBytes = log2Ceil(beatBytes) val sizeOH = UIntToOH(lgSize \| 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) \| (groupBy2 - 1).U def helper(i: Int): Seq[(Bool, Bool)] = { if (i == 0) { Seq((lgSize >= lgBytes.asUInt, true.B)) } else { val sub = helper(i-1) val size = sizeOH(lgBytes - i) val bit = addr_lo(lgBytes - i) val nbit = !bit Seq.tabulate (1 << i) { j => val (sub_acc, sub_eq) = sub(j/2) val eq = sub_eq && (if (j % 2 == 1) bit else nbit) val acc = sub_acc \|\| (size && eq) (acc, eq) } } } if (groupBy == beatBytes) 1.U else Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse) } } File AtomicAutomata.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.diplomacy.{AddressSet, TransferSizes} import freechips.rocketchip.util.leftOR import scala.math.{min,max} // Ensures that all downstream RW managers support Atomic operations. // If !passthrough, intercept all Atomics. Otherwise, only intercept those unsupported downstream. class TLAtomicAutomata(logical: Boolean = true, arithmetic: Boolean = true, concurrency: Int = 1, passthrough: Boolean = true)(implicit p: Parameters) extends LazyModule { require (concurrency >= 1) val node = TLAdapterNode( managerFn = { case mp => mp.v1copy(managers = mp.managers.map { m => val ourSupport = TransferSizes(1, mp.beatBytes) def widen(x: TransferSizes) = if (passthrough && x.min <= 2mp.beatBytes) TransferSizes(1, max(mp.beatBytes, x.max)) else ourSupport val canDoit = m.supportsPutFull.contains(ourSupport) && m.supportsGet.contains(ourSupport) // Blow up if there are devices to which we cannot add Atomics, because their R\|W are too inflexible require (!m.supportsPutFull \|\| !m.supportsGet \|\| canDoit, s"${m.name} has $ourSupport, needed PutFull(${m.supportsPutFull}) or Get(${m.supportsGet})") m.v1copy( supportsArithmetic = if (!arithmetic \|\| !canDoit) m.supportsArithmetic else widen(m.supportsArithmetic), supportsLogical = if (!logical \|\| !canDoit) m.supportsLogical else widen(m.supportsLogical), mayDenyGet = m.mayDenyGet \|\| m.mayDenyPut) })}) lazy val module = new Impl class Impl extends LazyModuleImp(this) { (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => val managers = edgeOut.manager.managers val beatBytes = edgeOut.manager.beatBytes // To which managers are we adding atomic support? val ourSupport = TransferSizes(1, beatBytes) val managersNeedingHelp = managers.filter { m => m.supportsPutFull.contains(ourSupport) && m.supportsGet.contains(ourSupport) && ((logical && !m.supportsLogical .contains(ourSupport)) \|\| (arithmetic && !m.supportsArithmetic.contains(ourSupport)) \|\| !passthrough) // we will do atomics for everyone we can } // Managers that need help with atomics must necessarily have this node as the root of a tree in the node graph. // (But they must also ensure no sideband operations can get between the read and write.) val violations = managersNeedingHelp.flatMap(_.findTreeViolation()).map { node => (node.name, node.inputs.map(_._1.name)) } require(violations.isEmpty, s"AtomicAutomata can only help nodes for which it is at the root of a diplomatic node tree," + "but the following violations were found:\n" + violations.map(v => s"(${v._1} has parents ${v._2})").mkString("\n")) // We cannot add atomics to a non-FIFO manager managersNeedingHelp foreach { m => require (m.fifoId.isDefined) } // We need to preserve FIFO semantics across FIFO domains, not managers // Suppose you have Put(42) Atomic(+1) both inflight; valid results: 42 or 43 // If we allow Put(42) Get() Put(+1) concurrent; valid results: 42 43 OR undef // Making non-FIFO work requires waiting for all Acks to come back (=> use FIFOFixer) val domainsNeedingHelp = managersNeedingHelp.map(_.fifoId.get).distinct // Don't overprovision the CAM val camSize = min(domainsNeedingHelp.size, concurrency) // Compact the fifoIds to only those we care about def camFifoId(m: TLSlaveParameters) = m.fifoId.map(id => max(0, domainsNeedingHelp.indexOf(id))).getOrElse(0) // CAM entry state machine val FREE = 0.U // unused waiting on Atomic from A val GET = 3.U // Get sent down A waiting on AccessDataAck from D val AMO = 2.U // AccessDataAck sent up D waiting for A availability val ACK = 1.U // Put sent down A waiting for PutAck from D val params = TLAtomicAutomata.CAMParams(out.a.bits.params, domainsNeedingHelp.size) // Do we need to do anything at all? if (camSize > 0) { val initval = Wire(new TLAtomicAutomata.CAM_S(params)) initval.state := FREE val cam_s = RegInit(VecInit.fill(camSize)(initval)) val cam_a = Reg(Vec(camSize, new TLAtomicAutomata.CAM_A(params))) val cam_d = Reg(Vec(camSize, new TLAtomicAutomata.CAM_D(params))) val cam_free = cam_s.map(_.state === FREE) val cam_amo = cam_s.map(_.state === AMO) val cam_abusy = cam_s.map(e => e.state === GET \|\| e.state === AMO) // A is blocked val cam_dmatch = cam_s.map(e => e.state =/= FREE) // D should inspect these entries // Can the manager already handle this message? val a_address = edgeIn.address(in.a.bits) val a_size = edgeIn.size(in.a.bits) val a_canLogical = passthrough.B && edgeOut.manager.supportsLogicalFast (a_address, a_size) val a_canArithmetic = passthrough.B && edgeOut.manager.supportsArithmeticFast(a_address, a_size) val a_isLogical = in.a.bits.opcode === TLMessages.LogicalData val a_isArithmetic = in.a.bits.opcode === TLMessages.ArithmeticData val a_isSupported = Mux(a_isLogical, a_canLogical, Mux(a_isArithmetic, a_canArithmetic, true.B)) // Must we do a Put? val a_cam_any_put = cam_amo.reduce(_ \|\| _) val a_cam_por_put = cam_amo.scanLeft(false.B)(_\|\|_).init val a_cam_sel_put = (cam_amo zip a_cam_por_put) map { case (a, b) => a && !b } val a_cam_a = PriorityMux(cam_amo, cam_a) val a_cam_d = PriorityMux(cam_amo, cam_d) val a_a = a_cam_a.bits.data val a_d = a_cam_d.data // Does the A request conflict with an inflight AMO? val a_fifoId = edgeOut.manager.fastProperty(a_address, camFifoId _, (i:Int) => i.U) val a_cam_busy = (cam_abusy zip cam_a.map(_.fifoId === a_fifoId)) map { case (a,b) => a&&b } reduce (_\|\|_) // (Where) are we are allocating in the CAM? val a_cam_any_free = cam_free.reduce(_ \|\| _) val a_cam_por_free = cam_free.scanLeft(false.B)(_\|\|_).init val a_cam_sel_free = (cam_free zip a_cam_por_free) map { case (a,b) => a && !b } // Logical AMO val indexes = Seq.tabulate(beatBytes8) { i => Cat(a_a(i,i), a_d(i,i)) } val logic_out = Cat(indexes.map(x => a_cam_a.lut(x).asUInt).reverse) // Arithmetic AMO val unsigned = a_cam_a.bits.param(1) val take_max = a_cam_a.bits.param(0) val adder = a_cam_a.bits.param(2) val mask = a_cam_a.bits.mask val signSel = ~(~mask \| (mask >> 1)) val signbits_a = Cat(Seq.tabulate(beatBytes) { i => a_a(8i+7,8i+7) } .reverse) val signbits_d = Cat(Seq.tabulate(beatBytes) { i => a_d(8i+7,8i+7) } .reverse) // Move the selected sign bit into the first byte position it will extend val signbit_a = ((signbits_a & signSel) << 1)(beatBytes-1, 0) val signbit_d = ((signbits_d & signSel) << 1)(beatBytes-1, 0) val signext_a = FillInterleaved(8, leftOR(signbit_a)) val signext_d = FillInterleaved(8, leftOR(signbit_d)) // NOTE: sign-extension does not change the relative ordering in EITHER unsigned or signed arithmetic val wide_mask = FillInterleaved(8, mask) val a_a_ext = (a_a & wide_mask) \| signext_a val a_d_ext = (a_d & wide_mask) \| signext_d val a_d_inv = Mux(adder, a_d_ext, ~a_d_ext) val adder_out = a_a_ext + a_d_inv val h = 8beatBytes-1 // now sign-extended; use biggest bit val a_bigger_uneq = unsigned === a_a_ext(h) // result if high bits are unequal val a_bigger = Mux(a_a_ext(h) === a_d_ext(h), !adder_out(h), a_bigger_uneq) val pick_a = take_max === a_bigger val arith_out = Mux(adder, adder_out, Mux(pick_a, a_a, a_d)) // AMO result data val amo_data = if (!logical) arith_out else if (!arithmetic) logic_out else Mux(a_cam_a.bits.opcode(0), logic_out, arith_out) // Potentially mutate the message from inner val source_i = Wire(chiselTypeOf(in.a)) val a_allow = !a_cam_busy && (a_isSupported \|\| a_cam_any_free) in.a.ready := source_i.ready && a_allow source_i.valid := in.a.valid && a_allow source_i.bits := in.a.bits when (!a_isSupported) { // minimal mux difference source_i.bits.opcode := TLMessages.Get source_i.bits.param := 0.U } // Potentially take the message from the CAM val source_c = Wire(chiselTypeOf(in.a)) source_c.valid := a_cam_any_put source_c.bits := edgeOut.Put( fromSource = a_cam_a.bits.source, toAddress = edgeIn.address(a_cam_a.bits), lgSize = a_cam_a.bits.size, data = amo_data, corrupt = a_cam_a.bits.corrupt \|\| a_cam_d.corrupt)._2 source_c.bits.user :<= a_cam_a.bits.user source_c.bits.echo :<= a_cam_a.bits.echo // Finishing an AMO from the CAM has highest priority TLArbiter(TLArbiter.lowestIndexFirst)(out.a, (0.U, source_c), (edgeOut.numBeats1(in.a.bits), source_i)) // Capture the A state into the CAM when (source_i.fire && !a_isSupported) { (a_cam_sel_free zip cam_a) foreach { case (en, r) => when (en) { r.fifoId := a_fifoId r.bits := in.a.bits r.lut := MuxLookup(in.a.bits.param(1, 0), 0.U(4.W))(Array( TLAtomics.AND -> 0x8.U, TLAtomics.OR -> 0xe.U, TLAtomics.XOR -> 0x6.U, TLAtomics.SWAP -> 0xc.U)) } } (a_cam_sel_free zip cam_s) foreach { case (en, r) => when (en) { r.state := GET } } } // Advance the put state when (source_c.fire) { (a_cam_sel_put zip cam_s) foreach { case (en, r) => when (en) { r.state := ACK } } } // We need to deal with a potential D response in the same cycle as the A request val d_first = edgeOut.first(out.d) val d_cam_sel_raw = cam_a.map(_.bits.source === in.d.bits.source) val d_cam_sel_match = (d_cam_sel_raw zip cam_dmatch) map { case (a,b) => a&&b } val d_cam_data = Mux1H(d_cam_sel_match, cam_d.map(_.data)) val d_cam_denied = Mux1H(d_cam_sel_match, cam_d.map(_.denied)) val d_cam_corrupt = Mux1H(d_cam_sel_match, cam_d.map(_.corrupt)) val d_cam_sel_bypass = if (edgeOut.manager.minLatency > 0) false.B else out.d.bits.source === in.a.bits.source && in.a.valid && !a_isSupported val d_cam_sel = (a_cam_sel_free zip d_cam_sel_match) map { case (a,d) => Mux(d_cam_sel_bypass, a, d) } val d_cam_sel_any = d_cam_sel_bypass \|\| d_cam_sel_match.reduce(_ \|\| _) val d_ackd = out.d.bits.opcode === TLMessages.AccessAckData val d_ack = out.d.bits.opcode === TLMessages.AccessAck when (out.d.fire && d_first) { (d_cam_sel zip cam_d) foreach { case (en, r) => when (en && d_ackd) { r.data := out.d.bits.data r.denied := out.d.bits.denied r.corrupt := out.d.bits.corrupt } } (d_cam_sel zip cam_s) foreach { case (en, r) => when (en) { // Note: it is important that this comes AFTER the := GET, so we can go FREE=>GET=>AMO in one cycle r.state := Mux(d_ackd, AMO, FREE) } } } val d_drop = d_first && d_ackd && d_cam_sel_any val d_replace = d_first && d_ack && d_cam_sel_match.reduce(_ \|\| _) in.d.valid := out.d.valid && !d_drop out.d.ready := in.d.ready \|\| d_drop in.d.bits := out.d.bits when (d_replace) { // minimal muxes in.d.bits.opcode := TLMessages.AccessAckData in.d.bits.data := d_cam_data in.d.bits.corrupt := d_cam_corrupt \|\| out.d.bits.denied in.d.bits.denied := d_cam_denied \|\| out.d.bits.denied } } else { out.a.valid := in.a.valid in.a.ready := out.a.ready out.a.bits := in.a.bits in.d.valid := out.d.valid out.d.ready := in.d.ready in.d.bits := out.d.bits } if (edgeOut.manager.anySupportAcquireB && edgeIn.client.anySupportProbe) { in.b.valid := out.b.valid out.b.ready := in.b.ready in.b.bits := out.b.bits out.c.valid := in.c.valid in.c.ready := out.c.ready out.c.bits := in.c.bits out.e.valid := in.e.valid in.e.ready := out.e.ready out.e.bits := in.e.bits } else { in.b.valid := false.B in.c.ready := true.B in.e.ready := true.B out.b.ready := true.B out.c.valid := false.B out.e.valid := false.B } } } } object TLAtomicAutomata { def apply(logical: Boolean = true, arithmetic: Boolean = true, concurrency: Int = 1, passthrough: Boolean = true, nameSuffix: Option[String] = None)(implicit p: Parameters): TLNode = { val atomics = LazyModule(new TLAtomicAutomata(logical, arithmetic, concurrency, passthrough) { override lazy val desiredName = (Seq("TLAtomicAutomata") ++ nameSuffix).mkString("_") }) atomics.node } case class CAMParams(a: TLBundleParameters, domainsNeedingHelp: Int) class CAM_S(val params: CAMParams) extends Bundle { val state = UInt(2.W) } class CAM_A(val params: CAMParams) extends Bundle { val bits = new TLBundleA(params.a) val fifoId = UInt(log2Up(params.domainsNeedingHelp).W) val lut = UInt(4.W) } class CAM_D(val params: CAMParams) extends Bundle { val data = UInt(params.a.dataBits.W) val denied = Bool() val corrupt = Bool() } } // Synthesizable unit tests import freechips.rocketchip.unittest._ class TLRAMAtomicAutomata(txns: Int)(implicit p: Parameters) extends LazyModule { val fuzz = LazyModule(new TLFuzzer(txns)) val model = LazyModule(new TLRAMModel("AtomicAutomata")) val ram = LazyModule(new TLRAM(AddressSet(0x0, 0x3ff))) // Confirm that the AtomicAutomata combines read + write errors import TLMessages._ val test = new RequestPattern({a: TLBundleA => val doesA = a.opcode === ArithmeticData \|\| a.opcode === LogicalData val doesR = a.opcode === Get \|\| doesA val doesW = a.opcode === PutFullData \|\| a.opcode === PutPartialData \|\| doesA (doesR && RequestPattern.overlaps(Seq(AddressSet(0x08, ~0x08)))(a)) \|\| (doesW && RequestPattern.overlaps(Seq(AddressSet(0x10, ~0x10)))(a)) }) (ram.node := TLErrorEvaluator(test) := TLFragmenter(4, 256) := TLDelayer(0.1) := TLAtomicAutomata() := TLDelayer(0.1) := TLErrorEvaluator(test, testOn=true, testOff=true) := model.node := fuzz.node) lazy val module = new Impl class Impl extends LazyModuleImp(this) with UnitTestModule { io.finished := fuzz.module.io.finished } } class TLRAMAtomicAutomataTest(txns: Int = 5000, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) { val dut = Module(LazyModule(new TLRAMAtomicAutomata(txns)).module) io.finished := dut.io.finished dut.io.start := io.start } File ClockDomain.scala: package freechips.rocketchip.prci import chisel3._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.lazymodule._ abstract class Domain(implicit p: Parameters) extends LazyModule with HasDomainCrossing { def clockBundle: ClockBundle lazy val module = new Impl class Impl extends LazyRawModuleImp(this) { childClock := clockBundle.clock childReset := clockBundle.reset override def provideImplicitClockToLazyChildren = true // these are just for backwards compatibility with external devices // that were manually wiring themselves to the domain's clock/reset input: val clock = IO(Output(chiselTypeOf(clockBundle.clock))) val reset = IO(Output(chiselTypeOf(clockBundle.reset))) clock := clockBundle.clock reset := clockBundle.reset } } abstract class ClockDomain(implicit p: Parameters) extends Domain with HasClockDomainCrossing class ClockSinkDomain(val clockSinkParams: ClockSinkParameters)(implicit p: Parameters) extends ClockDomain { def this(take: Option[ClockParameters] = None, name: Option[String] = None)(implicit p: Parameters) = this(ClockSinkParameters(take = take, name = name)) val clockNode = ClockSinkNode(Seq(clockSinkParams)) def clockBundle = clockNode.in.head._1 override lazy val desiredName = (clockSinkParams.name.toSeq :+ "ClockSinkDomain").mkString } class ClockSourceDomain(val clockSourceParams: ClockSourceParameters)(implicit p: Parameters) extends ClockDomain { def this(give: Option[ClockParameters] = None, name: Option[String] = None)(implicit p: Parameters) = this(ClockSourceParameters(give = give, name = name)) val clockNode = ClockSourceNode(Seq(clockSourceParams)) def clockBundle = clockNode.out.head._1 override lazy val desiredName = (clockSourceParams.name.toSeq :+ "ClockSourceDomain").mkString } abstract class ResetDomain(implicit p: Parameters) extends Domain with HasResetDomainCrossing File PeripheryBus.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.subsystem import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.devices.tilelink.{BuiltInZeroDeviceParams, BuiltInErrorDeviceParams, HasBuiltInDeviceParams, BuiltInDevices} import freechips.rocketchip.diplomacy.BufferParams import freechips.rocketchip.tilelink.{ RegionReplicator, ReplicatedRegion, HasTLBusParams, HasRegionReplicatorParams, TLBusWrapper, TLBusWrapperInstantiationLike, TLFIFOFixer, TLNode, TLXbar, TLInwardNode, TLOutwardNode, TLBuffer, TLWidthWidget, TLAtomicAutomata, TLEdge } import freechips.rocketchip.util.Location case class BusAtomics( arithmetic: Boolean = true, buffer: BufferParams = BufferParams.default, widenBytes: Option[Int] = None ) case class PeripheryBusParams( beatBytes: Int, blockBytes: Int, atomics: Option[BusAtomics] = Some(BusAtomics()), dtsFrequency: Option[BigInt] = None, zeroDevice: Option[BuiltInZeroDeviceParams] = None, errorDevice: Option[BuiltInErrorDeviceParams] = None, replication: Option[ReplicatedRegion] = None) extends HasTLBusParams with HasBuiltInDeviceParams with HasRegionReplicatorParams with TLBusWrapperInstantiationLike { def instantiate(context: HasTileLinkLocations, loc: Location[TLBusWrapper])(implicit p: Parameters): PeripheryBus = { val pbus = LazyModule(new PeripheryBus(this, loc.name)) pbus.suggestName(loc.name) context.tlBusWrapperLocationMap += (loc -> pbus) pbus } } class PeripheryBus(params: PeripheryBusParams, name: String)(implicit p: Parameters) extends TLBusWrapper(params, name) { override lazy val desiredName = s"PeripheryBus_$name" private val replicator = params.replication.map(r => LazyModule(new RegionReplicator(r))) val prefixNode = replicator.map { r => r.prefix := addressPrefixNexusNode addressPrefixNexusNode } private val fixer = LazyModule(new TLFIFOFixer(TLFIFOFixer.all)) private val node: TLNode = params.atomics.map { pa => val in_xbar = LazyModule(new TLXbar(nameSuffix = Some(s"${name}_in"))) val out_xbar = LazyModule(new TLXbar(nameSuffix = Some(s"${name}_out"))) val fixer_node = replicator.map(fixer.node := _.node).getOrElse(fixer.node) (out_xbar.node := fixer_node := TLBuffer(pa.buffer) := (pa.widenBytes.filter(_ > beatBytes).map { w => TLWidthWidget(w) := TLAtomicAutomata(arithmetic = pa.arithmetic, nameSuffix = Some(name)) } .getOrElse { TLAtomicAutomata(arithmetic = pa.arithmetic, nameSuffix = Some(name)) }) := in_xbar.node) } .getOrElse { TLXbar() := fixer.node } def inwardNode: TLInwardNode = node def outwardNode: TLOutwardNode = node def busView: TLEdge = fixer.node.edges.in.head val builtInDevices: BuiltInDevices = BuiltInDevices.attach(params, outwardNode) } File ClockGroup.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.prci import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.lazymodule._ import org.chipsalliance.diplomacy.nodes._ import freechips.rocketchip.resources.FixedClockResource case class ClockGroupingNode(groupName: String)(implicit valName: ValName) extends MixedNexusNode(ClockGroupImp, ClockImp)( dFn = { _ => ClockSourceParameters() }, uFn = { seq => ClockGroupSinkParameters(name = groupName, members = seq) }) { override def circuitIdentity = outputs.size == 1 } class ClockGroup(groupName: String)(implicit p: Parameters) extends LazyModule { val node = ClockGroupingNode(groupName) lazy val module = new Impl class Impl extends LazyRawModuleImp(this) { val (in, _) = node.in(0) val (out, _) = node.out.unzip require (node.in.size == 1) require (in.member.size == out.size) (in.member.data zip out) foreach { case (i, o) => o := i } } } object ClockGroup { def apply()(implicit p: Parameters, valName: ValName) = LazyModule(new ClockGroup(valName.name)).node } case class ClockGroupAggregateNode(groupName: String)(implicit valName: ValName) extends NexusNode(ClockGroupImp)( dFn = { _ => ClockGroupSourceParameters() }, uFn = { seq => ClockGroupSinkParameters(name = groupName, members = seq.flatMap(_.members))}) { override def circuitIdentity = outputs.size == 1 } class ClockGroupAggregator(groupName: String)(implicit p: Parameters) extends LazyModule { val node = ClockGroupAggregateNode(groupName) override lazy val desiredName = s"ClockGroupAggregator_$groupName" lazy val module = new Impl class Impl extends LazyRawModuleImp(this) { val (in, _) = node.in.unzip val (out, _) = node.out.unzip val outputs = out.flatMap(_.member.data) require (node.in.size == 1, s"Aggregator for groupName: ${groupName} had ${node.in.size} inward edges instead of 1") require (in.head.member.size == outputs.size) in.head.member.data.zip(outputs).foreach { case (i, o) => o := i } } } object ClockGroupAggregator { def apply()(implicit p: Parameters, valName: ValName) = LazyModule(new ClockGroupAggregator(valName.name)).node } class SimpleClockGroupSource(numSources: Int = 1)(implicit p: Parameters) extends LazyModule { val node = ClockGroupSourceNode(List.fill(numSources) { ClockGroupSourceParameters() }) lazy val module = new Impl class Impl extends LazyModuleImp(this) { val (out, _) = node.out.unzip out.map { out: ClockGroupBundle => out.member.data.foreach { o => o.clock := clock; o.reset := reset } } } } object SimpleClockGroupSource { def apply(num: Int = 1)(implicit p: Parameters, valName: ValName) = LazyModule(new SimpleClockGroupSource(num)).node } case class FixedClockBroadcastNode(fixedClockOpt: Option[ClockParameters])(implicit valName: ValName) extends NexusNode(ClockImp)( dFn = { seq => fixedClockOpt.map(_ => ClockSourceParameters(give = fixedClockOpt)).orElse(seq.headOption).getOrElse(ClockSourceParameters()) }, uFn = { seq => fixedClockOpt.map(_ => ClockSinkParameters(take = fixedClockOpt)).orElse(seq.headOption).getOrElse(ClockSinkParameters()) }, inputRequiresOutput = false) { def fixedClockResources(name: String, prefix: String = "soc/"): Seq[Option[FixedClockResource]] = Seq(fixedClockOpt.map(t => new FixedClockResource(name, t.freqMHz, prefix))) } class FixedClockBroadcast(fixedClockOpt: Option[ClockParameters])(implicit p: Parameters) extends LazyModule { val node = new FixedClockBroadcastNode(fixedClockOpt) { override def circuitIdentity = outputs.size == 1 } lazy val module = new Impl class Impl extends LazyRawModuleImp(this) { val (in, _) = node.in(0) val (out, _) = node.out.unzip override def desiredName = s"FixedClockBroadcast_${out.size}" require (node.in.size == 1, "FixedClockBroadcast can only broadcast a single clock") out.foreach { _ := in } } } object FixedClockBroadcast { def apply(fixedClockOpt: Option[ClockParameters] = None)(implicit p: Parameters, valName: ValName) = LazyModule(new FixedClockBroadcast(fixedClockOpt)).node } case class PRCIClockGroupNode()(implicit valName: ValName) extends NexusNode(ClockGroupImp)( dFn = { _ => ClockGroupSourceParameters() }, uFn = { _ => ClockGroupSinkParameters("prci", Nil) }, outputRequiresInput = false) File WidthWidget.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.diplomacy.AddressSet import freechips.rocketchip.util.{Repeater, UIntToOH1} // innBeatBytes => the new client-facing bus width class TLWidthWidget(innerBeatBytes: Int)(implicit p: Parameters) extends LazyModule { private def noChangeRequired(manager: TLManagerPortParameters) = manager.beatBytes == innerBeatBytes val node = new TLAdapterNode( clientFn = { case c => c }, managerFn = { case m => m.v1copy(beatBytes = innerBeatBytes) }){ override def circuitIdentity = edges.out.map(_.manager).forall(noChangeRequired) } override lazy val desiredName = s"TLWidthWidget$innerBeatBytes" lazy val module = new Impl class Impl extends LazyModuleImp(this) { def merge[T <: TLDataChannel](edgeIn: TLEdge, in: DecoupledIO[T], edgeOut: TLEdge, out: DecoupledIO[T]) = { val inBytes = edgeIn.manager.beatBytes val outBytes = edgeOut.manager.beatBytes val ratio = outBytes / inBytes val keepBits = log2Ceil(outBytes) val dropBits = log2Ceil(inBytes) val countBits = log2Ceil(ratio) val size = edgeIn.size(in.bits) val hasData = edgeIn.hasData(in.bits) val limit = UIntToOH1(size, keepBits) >> dropBits val count = RegInit(0.U(countBits.W)) val first = count === 0.U val last = count === limit \|\| !hasData val enable = Seq.tabulate(ratio) { i => !((count ^ i.U) & limit).orR } val corrupt_reg = RegInit(false.B) val corrupt_in = edgeIn.corrupt(in.bits) val corrupt_out = corrupt_in \|\| corrupt_reg when (in.fire) { count := count + 1.U corrupt_reg := corrupt_out when (last) { count := 0.U corrupt_reg := false.B } } def helper(idata: UInt): UInt = { // rdata is X until the first time a multi-beat write occurs. // Prevent the X from leaking outside by jamming the mux control until // the first time rdata is written (and hence no longer X). val rdata_written_once = RegInit(false.B) val masked_enable = enable.map(_ \|\| !rdata_written_once) val odata = Seq.fill(ratio) { WireInit(idata) } val rdata = Reg(Vec(ratio-1, chiselTypeOf(idata))) val pdata = rdata :+ idata val mdata = (masked_enable zip (odata zip pdata)) map { case (e, (o, p)) => Mux(e, o, p) } when (in.fire && !last) { rdata_written_once := true.B (rdata zip mdata) foreach { case (r, m) => r := m } } Cat(mdata.reverse) } in.ready := out.ready \|\| !last out.valid := in.valid && last out.bits := in.bits // Don't put down hardware if we never carry data edgeOut.data(out.bits) := (if (edgeIn.staticHasData(in.bits) == Some(false)) 0.U else helper(edgeIn.data(in.bits))) edgeOut.corrupt(out.bits) := corrupt_out (out.bits, in.bits) match { case (o: TLBundleA, i: TLBundleA) => o.mask := edgeOut.mask(o.address, o.size) & Mux(hasData, helper(i.mask), ~0.U(outBytes.W)) case (o: TLBundleB, i: TLBundleB) => o.mask := edgeOut.mask(o.address, o.size) & Mux(hasData, helper(i.mask), ~0.U(outBytes.W)) case (o: TLBundleC, i: TLBundleC) => () case (o: TLBundleD, i: TLBundleD) => () case _ => require(false, "Impossible bundle combination in WidthWidget") } } def split[T <: TLDataChannel](edgeIn: TLEdge, in: DecoupledIO[T], edgeOut: TLEdge, out: DecoupledIO[T], sourceMap: UInt => UInt) = { val inBytes = edgeIn.manager.beatBytes val outBytes = edgeOut.manager.beatBytes val ratio = inBytes / outBytes val keepBits = log2Ceil(inBytes) val dropBits = log2Ceil(outBytes) val countBits = log2Ceil(ratio) val size = edgeIn.size(in.bits) val hasData = edgeIn.hasData(in.bits) val limit = UIntToOH1(size, keepBits) >> dropBits val count = RegInit(0.U(countBits.W)) val first = count === 0.U val last = count === limit \|\| !hasData when (out.fire) { count := count + 1.U when (last) { count := 0.U } } // For sub-beat transfer, extract which part matters val sel = in.bits match { case a: TLBundleA => a.address(keepBits-1, dropBits) case b: TLBundleB => b.address(keepBits-1, dropBits) case c: TLBundleC => c.address(keepBits-1, dropBits) case d: TLBundleD => { val sel = sourceMap(d.source) val hold = Mux(first, sel, RegEnable(sel, first)) // a_first is not for whole xfer hold & ~limit // if more than one a_first/xfer, the address must be aligned anyway } } val index = sel \| count def helper(idata: UInt, width: Int): UInt = { val mux = VecInit.tabulate(ratio) { i => idata((i+1)outByteswidth-1, ioutByteswidth) } mux(index) } out.bits := in.bits out.valid := in.valid in.ready := out.ready // Don't put down hardware if we never carry data edgeOut.data(out.bits) := (if (edgeIn.staticHasData(in.bits) == Some(false)) 0.U else helper(edgeIn.data(in.bits), 8)) (out.bits, in.bits) match { case (o: TLBundleA, i: TLBundleA) => o.mask := helper(i.mask, 1) case (o: TLBundleB, i: TLBundleB) => o.mask := helper(i.mask, 1) case (o: TLBundleC, i: TLBundleC) => () // replicating corrupt to all beats is ok case (o: TLBundleD, i: TLBundleD) => () case _ => require(false, "Impossbile bundle combination in WidthWidget") } // Repeat the input if we're not last !last } def splice[T <: TLDataChannel](edgeIn: TLEdge, in: DecoupledIO[T], edgeOut: TLEdge, out: DecoupledIO[T], sourceMap: UInt => UInt) = { if (edgeIn.manager.beatBytes == edgeOut.manager.beatBytes) { // nothing to do; pass it through out.bits := in.bits out.valid := in.valid in.ready := out.ready } else if (edgeIn.manager.beatBytes > edgeOut.manager.beatBytes) { // split input to output val repeat = Wire(Bool()) val repeated = Repeater(in, repeat) val cated = Wire(chiselTypeOf(repeated)) cated <> repeated edgeIn.data(cated.bits) := Cat( edgeIn.data(repeated.bits)(edgeIn.manager.beatBytes8-1, edgeOut.manager.beatBytes8), edgeIn.data(in.bits)(edgeOut.manager.beatBytes8-1, 0)) repeat := split(edgeIn, cated, edgeOut, out, sourceMap) } else { // merge input to output merge(edgeIn, in, edgeOut, out) } } (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => // If the master is narrower than the slave, the D channel must be narrowed. // This is tricky, because the D channel has no address data. // Thus, you don't know which part of a sub-beat transfer to extract. // To fix this, we record the relevant address bits for all sources. // The assumption is that this sort of situation happens only where // you connect a narrow master to the system bus, so there are few sources. def sourceMap(source_bits: UInt) = { val source = if (edgeIn.client.endSourceId == 1) 0.U(0.W) else source_bits require (edgeOut.manager.beatBytes > edgeIn.manager.beatBytes) val keepBits = log2Ceil(edgeOut.manager.beatBytes) val dropBits = log2Ceil(edgeIn.manager.beatBytes) val sources = Reg(Vec(edgeIn.client.endSourceId, UInt((keepBits-dropBits).W))) val a_sel = in.a.bits.address(keepBits-1, dropBits) when (in.a.fire) { if (edgeIn.client.endSourceId == 1) { // avoid extraction-index-width warning sources(0) := a_sel } else { sources(in.a.bits.source) := a_sel } } // depopulate unused source registers: edgeIn.client.unusedSources.foreach { id => sources(id) := 0.U } val bypass = in.a.valid && in.a.bits.source === source if (edgeIn.manager.minLatency > 0) sources(source) else Mux(bypass, a_sel, sources(source)) } splice(edgeIn, in.a, edgeOut, out.a, sourceMap) splice(edgeOut, out.d, edgeIn, in.d, sourceMap) if (edgeOut.manager.anySupportAcquireB && edgeIn.client.anySupportProbe) { splice(edgeOut, out.b, edgeIn, in.b, sourceMap) splice(edgeIn, in.c, edgeOut, out.c, sourceMap) out.e.valid := in.e.valid out.e.bits := in.e.bits in.e.ready := out.e.ready } else { in.b.valid := false.B in.c.ready := true.B in.e.ready := true.B out.b.ready := true.B out.c.valid := false.B out.e.valid := false.B } } } } object TLWidthWidget { def apply(innerBeatBytes: Int)(implicit p: Parameters): TLNode = { val widget = LazyModule(new TLWidthWidget(innerBeatBytes)) widget.node } def apply(wrapper: TLBusWrapper)(implicit p: Parameters): TLNode = apply(wrapper.beatBytes) } // Synthesizable unit tests import freechips.rocketchip.unittest._ class TLRAMWidthWidget(first: Int, second: Int, txns: Int)(implicit p: Parameters) extends LazyModule { val fuzz = LazyModule(new TLFuzzer(txns)) val model = LazyModule(new TLRAMModel("WidthWidget")) val ram = LazyModule(new TLRAM(AddressSet(0x0, 0x3ff))) (ram.node := TLDelayer(0.1) := TLFragmenter(4, 256) := TLWidthWidget(second) := TLWidthWidget(first) := TLDelayer(0.1) := model.node := fuzz.node) lazy val module = new Impl class Impl extends LazyModuleImp(this) with UnitTestModule { io.finished := fuzz.module.io.finished } } class TLRAMWidthWidgetTest(little: Int, big: Int, txns: Int = 5000, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) { val dut = Module(LazyModule(new TLRAMWidthWidget(little,big,txns)).module) dut.io.start := DontCare io.finished := dut.io.finished } File LazyModuleImp.scala: package org.chipsalliance.diplomacy.lazymodule import chisel3.{withClockAndReset, Module, RawModule, Reset, _} import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo} import firrtl.passes.InlineAnnotation import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.nodes.Dangle import scala.collection.immutable.SortedMap /* Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]]. * * This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy. / sealed trait LazyModuleImpLike extends RawModule { /* [[LazyModule]] that contains this instance. / val wrapper: LazyModule /* IOs that will be automatically "punched" for this instance. / val auto: AutoBundle /* The metadata that describes the [[HalfEdge]]s which generated [[auto]]. / protected[diplomacy] val dangles: Seq[Dangle] // [[wrapper.module]] had better not be accessed while LazyModules are still being built! require( LazyModule.scope.isEmpty, s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}" ) /* Set module name. Defaults to the containing LazyModule's desiredName. / override def desiredName: String = wrapper.desiredName suggestName(wrapper.suggestedName) /* [[Parameters]] for chisel [[Module]]s. / implicit val p: Parameters = wrapper.p /* instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and * submodules. / protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = { // 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]], // 2. return [[Dangle]]s from each module. val childDangles = wrapper.children.reverse.flatMap { c => implicit val sourceInfo: SourceInfo = c.info c.cloneProto.map { cp => // If the child is a clone, then recursively set cloneProto of its children as well def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = { require(bases.size == clones.size) (bases.zip(clones)).map { case (l, r) => require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}") l.cloneProto = Some(r) assignCloneProtos(l.children, r.children) } } assignCloneProtos(c.children, cp.children) // Clone the child module as a record, and get its [[AutoBundle]] val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName) val clonedAuto = clone("auto").asInstanceOf[AutoBundle] // Get the empty [[Dangle]]'s of the cloned child val rawDangles = c.cloneDangles() require(rawDangles.size == clonedAuto.elements.size) // Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) } dangles }.getOrElse { // For non-clones, instantiate the child module val mod = try { Module(c.module) } catch { case e: ChiselException => { println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}") throw e } } mod.dangles } } // Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]]. // This will result in a sequence of [[Dangle]] from these [[BaseNode]]s. val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate()) // Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]] val allDangles = nodeDangles ++ childDangles // Group [[allDangles]] by their [[source]]. val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _) // For each [[source]] set of [[Dangle]]s of size 2, ensure that these // can be connected as a source-sink pair (have opposite flipped value). // Make the connection and mark them as [[done]]. val done = Set() ++ pairing.values.filter(_.size == 2).map { case Seq(a, b) => require(a.flipped != b.flipped) // @todo <> in chisel3 makes directionless connection. if (a.flipped) { a.data <> b.data } else { b.data <> a.data } a.source case _ => None } // Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module. val forward = allDangles.filter(d => !done(d.source)) // Generate [[AutoBundle]] IO from [[forward]]. val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _)) // Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]] val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) => if (d.flipped) { d.data <> io } else { io <> d.data } d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name) } // Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]]. wrapper.inModuleBody.reverse.foreach { _() } if (wrapper.shouldBeInlined) { chisel3.experimental.annotate(new ChiselAnnotation { def toFirrtl = InlineAnnotation(toNamed) }) } // Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]]. (auto, dangles) } } /* Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. / class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike { /* Instantiate hardware of this `Module`. / val (auto, dangles) = instantiate() } /* Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. / class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike { // These wires are the default clock+reset for all LazyModule children. // It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the // [[LazyRawModuleImp]] children. // Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly. /* drive clock explicitly. / val childClock: Clock = Wire(Clock()) /* drive reset explicitly. / val childReset: Reset = Wire(Reset()) // the default is that these are disabled childClock := false.B.asClock childReset := chisel3.DontCare def provideImplicitClockToLazyChildren: Boolean = false val (auto, dangles) = if (provideImplicitClockToLazyChildren) { withClockAndReset(childClock, childReset) { instantiate() } } else { instantiate() } } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.nodes._ import freechips.rocketchip.diplomacy.{ AddressDecoder, AddressSet, BufferParams, DirectedBuffers, IdMap, IdMapEntry, IdRange, RegionType, TransferSizes } import freechips.rocketchip.resources.{Resource, ResourceAddress, ResourcePermissions} import freechips.rocketchip.util.{ AsyncQueueParams, BundleField, BundleFieldBase, BundleKeyBase, CreditedDelay, groupByIntoSeq, RationalDirection, SimpleProduct } import scala.math.max //These transfer sizes describe requests issued from masters on the A channel that will be responded by slaves on the D channel case class TLMasterToSlaveTransferSizes( // Supports both Acquire+Release of the following two sizes: acquireT: TransferSizes = TransferSizes.none, acquireB: TransferSizes = TransferSizes.none, arithmetic: TransferSizes = TransferSizes.none, logical: TransferSizes = TransferSizes.none, get: TransferSizes = TransferSizes.none, putFull: TransferSizes = TransferSizes.none, putPartial: TransferSizes = TransferSizes.none, hint: TransferSizes = TransferSizes.none) extends TLCommonTransferSizes { def intersect(rhs: TLMasterToSlaveTransferSizes) = TLMasterToSlaveTransferSizes( acquireT = acquireT .intersect(rhs.acquireT), acquireB = acquireB .intersect(rhs.acquireB), arithmetic = arithmetic.intersect(rhs.arithmetic), logical = logical .intersect(rhs.logical), get = get .intersect(rhs.get), putFull = putFull .intersect(rhs.putFull), putPartial = putPartial.intersect(rhs.putPartial), hint = hint .intersect(rhs.hint)) def mincover(rhs: TLMasterToSlaveTransferSizes) = TLMasterToSlaveTransferSizes( acquireT = acquireT .mincover(rhs.acquireT), acquireB = acquireB .mincover(rhs.acquireB), arithmetic = arithmetic.mincover(rhs.arithmetic), logical = logical .mincover(rhs.logical), get = get .mincover(rhs.get), putFull = putFull .mincover(rhs.putFull), putPartial = putPartial.mincover(rhs.putPartial), hint = hint .mincover(rhs.hint)) // Reduce rendering to a simple yes/no per field override def toString = { def str(x: TransferSizes, flag: String) = if (x.none) "" else flag def flags = Vector( str(acquireT, "T"), str(acquireB, "B"), str(arithmetic, "A"), str(logical, "L"), str(get, "G"), str(putFull, "F"), str(putPartial, "P"), str(hint, "H")) flags.mkString } // Prints out the actual information in a user readable way def infoString = { s"""acquireT = ${acquireT} \|acquireB = ${acquireB} \|arithmetic = ${arithmetic} \|logical = ${logical} \|get = ${get} \|putFull = ${putFull} \|putPartial = ${putPartial} \|hint = ${hint} \| \|""".stripMargin } } object TLMasterToSlaveTransferSizes { def unknownEmits = TLMasterToSlaveTransferSizes( acquireT = TransferSizes(1, 4096), acquireB = TransferSizes(1, 4096), arithmetic = TransferSizes(1, 4096), logical = TransferSizes(1, 4096), get = TransferSizes(1, 4096), putFull = TransferSizes(1, 4096), putPartial = TransferSizes(1, 4096), hint = TransferSizes(1, 4096)) def unknownSupports = TLMasterToSlaveTransferSizes() } //These transfer sizes describe requests issued from slaves on the B channel that will be responded by masters on the C channel case class TLSlaveToMasterTransferSizes( probe: TransferSizes = TransferSizes.none, arithmetic: TransferSizes = TransferSizes.none, logical: TransferSizes = TransferSizes.none, get: TransferSizes = TransferSizes.none, putFull: TransferSizes = TransferSizes.none, putPartial: TransferSizes = TransferSizes.none, hint: TransferSizes = TransferSizes.none ) extends TLCommonTransferSizes { def intersect(rhs: TLSlaveToMasterTransferSizes) = TLSlaveToMasterTransferSizes( probe = probe .intersect(rhs.probe), arithmetic = arithmetic.intersect(rhs.arithmetic), logical = logical .intersect(rhs.logical), get = get .intersect(rhs.get), putFull = putFull .intersect(rhs.putFull), putPartial = putPartial.intersect(rhs.putPartial), hint = hint .intersect(rhs.hint) ) def mincover(rhs: TLSlaveToMasterTransferSizes) = TLSlaveToMasterTransferSizes( probe = probe .mincover(rhs.probe), arithmetic = arithmetic.mincover(rhs.arithmetic), logical = logical .mincover(rhs.logical), get = get .mincover(rhs.get), putFull = putFull .mincover(rhs.putFull), putPartial = putPartial.mincover(rhs.putPartial), hint = hint .mincover(rhs.hint) ) // Reduce rendering to a simple yes/no per field override def toString = { def str(x: TransferSizes, flag: String) = if (x.none) "" else flag def flags = Vector( str(probe, "P"), str(arithmetic, "A"), str(logical, "L"), str(get, "G"), str(putFull, "F"), str(putPartial, "P"), str(hint, "H")) flags.mkString } // Prints out the actual information in a user readable way def infoString = { s"""probe = ${probe} \|arithmetic = ${arithmetic} \|logical = ${logical} \|get = ${get} \|putFull = ${putFull} \|putPartial = ${putPartial} \|hint = ${hint} \| \|""".stripMargin } } object TLSlaveToMasterTransferSizes { def unknownEmits = TLSlaveToMasterTransferSizes( arithmetic = TransferSizes(1, 4096), logical = TransferSizes(1, 4096), get = TransferSizes(1, 4096), putFull = TransferSizes(1, 4096), putPartial = TransferSizes(1, 4096), hint = TransferSizes(1, 4096), probe = TransferSizes(1, 4096)) def unknownSupports = TLSlaveToMasterTransferSizes() } trait TLCommonTransferSizes { def arithmetic: TransferSizes def logical: TransferSizes def get: TransferSizes def putFull: TransferSizes def putPartial: TransferSizes def hint: TransferSizes } class TLSlaveParameters private( val nodePath: Seq[BaseNode], val resources: Seq[Resource], setName: Option[String], val address: Seq[AddressSet], val regionType: RegionType.T, val executable: Boolean, val fifoId: Option[Int], val supports: TLMasterToSlaveTransferSizes, val emits: TLSlaveToMasterTransferSizes, // By default, slaves are forbidden from issuing 'denied' responses (it prevents Fragmentation) val alwaysGrantsT: Boolean, // typically only true for CacheCork'd read-write devices; dual: neverReleaseData // If fifoId=Some, all accesses sent to the same fifoId are executed and ACK'd in FIFO order // Note: you can only rely on this FIFO behaviour if your TLMasterParameters include requestFifo val mayDenyGet: Boolean, // applies to: AccessAckData, GrantData val mayDenyPut: Boolean) // applies to: AccessAck, Grant, HintAck // ReleaseAck may NEVER be denied extends SimpleProduct { def sortedAddress = address.sorted override def canEqual(that: Any): Boolean = that.isInstanceOf[TLSlaveParameters] override def productPrefix = "TLSlaveParameters" // We intentionally omit nodePath for equality testing / formatting def productArity: Int = 11 def productElement(n: Int): Any = n match { case 0 => name case 1 => address case 2 => resources case 3 => regionType case 4 => executable case 5 => fifoId case 6 => supports case 7 => emits case 8 => alwaysGrantsT case 9 => mayDenyGet case 10 => mayDenyPut case _ => throw new IndexOutOfBoundsException(n.toString) } def supportsAcquireT: TransferSizes = supports.acquireT def supportsAcquireB: TransferSizes = supports.acquireB def supportsArithmetic: TransferSizes = supports.arithmetic def supportsLogical: TransferSizes = supports.logical def supportsGet: TransferSizes = supports.get def supportsPutFull: TransferSizes = supports.putFull def supportsPutPartial: TransferSizes = supports.putPartial def supportsHint: TransferSizes = supports.hint require (!address.isEmpty, "Address cannot be empty") address.foreach { a => require (a.finite, "Address must be finite") } address.combinations(2).foreach { case Seq(x,y) => require (!x.overlaps(y), s"$x and $y overlap.") } require (supportsPutFull.contains(supportsPutPartial), s"PutFull($supportsPutFull) < PutPartial($supportsPutPartial)") require (supportsPutFull.contains(supportsArithmetic), s"PutFull($supportsPutFull) < Arithmetic($supportsArithmetic)") require (supportsPutFull.contains(supportsLogical), s"PutFull($supportsPutFull) < Logical($supportsLogical)") require (supportsGet.contains(supportsArithmetic), s"Get($supportsGet) < Arithmetic($supportsArithmetic)") require (supportsGet.contains(supportsLogical), s"Get($supportsGet) < Logical($supportsLogical)") require (supportsAcquireB.contains(supportsAcquireT), s"AcquireB($supportsAcquireB) < AcquireT($supportsAcquireT)") require (!alwaysGrantsT \|\| supportsAcquireT, s"Must supportAcquireT if promising to always grantT") // Make sure that the regionType agrees with the capabilities require (!supportsAcquireB \|\| regionType >= RegionType.UNCACHED) // acquire -> uncached, tracked, cached require (regionType <= RegionType.UNCACHED \|\| supportsAcquireB) // tracked, cached -> acquire require (regionType != RegionType.UNCACHED \|\| supportsGet) // uncached -> supportsGet val name = setName.orElse(nodePath.lastOption.map(_.lazyModule.name)).getOrElse("disconnected") val maxTransfer = List( // Largest supported transfer of all types supportsAcquireT.max, supportsAcquireB.max, supportsArithmetic.max, supportsLogical.max, supportsGet.max, supportsPutFull.max, supportsPutPartial.max).max val maxAddress = address.map(_.max).max val minAlignment = address.map(_.alignment).min // The device had better not support a transfer larger than its alignment require (minAlignment >= maxTransfer, s"Bad $address: minAlignment ($minAlignment) must be >= maxTransfer ($maxTransfer)") def toResource: ResourceAddress = { ResourceAddress(address, ResourcePermissions( r = supportsAcquireB \|\| supportsGet, w = supportsAcquireT \|\| supportsPutFull, x = executable, c = supportsAcquireB, a = supportsArithmetic && supportsLogical)) } def findTreeViolation() = nodePath.find { case _: MixedAdapterNode[_, _, _, _, _, _, _, _] => false case _: SinkNode[_, _, _, _, _] => false case node => node.inputs.size != 1 } def isTree = findTreeViolation() == None def infoString = { s"""Slave Name = ${name} \|Slave Address = ${address} \|supports = ${supports.infoString} \| \|""".stripMargin } def v1copy( address: Seq[AddressSet] = address, resources: Seq[Resource] = resources, regionType: RegionType.T = regionType, executable: Boolean = executable, nodePath: Seq[BaseNode] = nodePath, supportsAcquireT: TransferSizes = supports.acquireT, supportsAcquireB: TransferSizes = supports.acquireB, supportsArithmetic: TransferSizes = supports.arithmetic, supportsLogical: TransferSizes = supports.logical, supportsGet: TransferSizes = supports.get, supportsPutFull: TransferSizes = supports.putFull, supportsPutPartial: TransferSizes = supports.putPartial, supportsHint: TransferSizes = supports.hint, mayDenyGet: Boolean = mayDenyGet, mayDenyPut: Boolean = mayDenyPut, alwaysGrantsT: Boolean = alwaysGrantsT, fifoId: Option[Int] = fifoId) = { new TLSlaveParameters( setName = setName, address = address, resources = resources, regionType = regionType, executable = executable, nodePath = nodePath, supports = TLMasterToSlaveTransferSizes( acquireT = supportsAcquireT, acquireB = supportsAcquireB, arithmetic = supportsArithmetic, logical = supportsLogical, get = supportsGet, putFull = supportsPutFull, putPartial = supportsPutPartial, hint = supportsHint), emits = emits, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut, alwaysGrantsT = alwaysGrantsT, fifoId = fifoId) } def v2copy( nodePath: Seq[BaseNode] = nodePath, resources: Seq[Resource] = resources, name: Option[String] = setName, address: Seq[AddressSet] = address, regionType: RegionType.T = regionType, executable: Boolean = executable, fifoId: Option[Int] = fifoId, supports: TLMasterToSlaveTransferSizes = supports, emits: TLSlaveToMasterTransferSizes = emits, alwaysGrantsT: Boolean = alwaysGrantsT, mayDenyGet: Boolean = mayDenyGet, mayDenyPut: Boolean = mayDenyPut) = { new TLSlaveParameters( nodePath = nodePath, resources = resources, setName = name, address = address, regionType = regionType, executable = executable, fifoId = fifoId, supports = supports, emits = emits, alwaysGrantsT = alwaysGrantsT, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut) } @deprecated("Use v1copy instead of copy","") def copy( address: Seq[AddressSet] = address, resources: Seq[Resource] = resources, regionType: RegionType.T = regionType, executable: Boolean = executable, nodePath: Seq[BaseNode] = nodePath, supportsAcquireT: TransferSizes = supports.acquireT, supportsAcquireB: TransferSizes = supports.acquireB, supportsArithmetic: TransferSizes = supports.arithmetic, supportsLogical: TransferSizes = supports.logical, supportsGet: TransferSizes = supports.get, supportsPutFull: TransferSizes = supports.putFull, supportsPutPartial: TransferSizes = supports.putPartial, supportsHint: TransferSizes = supports.hint, mayDenyGet: Boolean = mayDenyGet, mayDenyPut: Boolean = mayDenyPut, alwaysGrantsT: Boolean = alwaysGrantsT, fifoId: Option[Int] = fifoId) = { v1copy( address = address, resources = resources, regionType = regionType, executable = executable, nodePath = nodePath, supportsAcquireT = supportsAcquireT, supportsAcquireB = supportsAcquireB, supportsArithmetic = supportsArithmetic, supportsLogical = supportsLogical, supportsGet = supportsGet, supportsPutFull = supportsPutFull, supportsPutPartial = supportsPutPartial, supportsHint = supportsHint, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut, alwaysGrantsT = alwaysGrantsT, fifoId = fifoId) } } object TLSlaveParameters { def v1( address: Seq[AddressSet], resources: Seq[Resource] = Seq(), regionType: RegionType.T = RegionType.GET_EFFECTS, executable: Boolean = false, nodePath: Seq[BaseNode] = Seq(), supportsAcquireT: TransferSizes = TransferSizes.none, supportsAcquireB: TransferSizes = TransferSizes.none, supportsArithmetic: TransferSizes = TransferSizes.none, supportsLogical: TransferSizes = TransferSizes.none, supportsGet: TransferSizes = TransferSizes.none, supportsPutFull: TransferSizes = TransferSizes.none, supportsPutPartial: TransferSizes = TransferSizes.none, supportsHint: TransferSizes = TransferSizes.none, mayDenyGet: Boolean = false, mayDenyPut: Boolean = false, alwaysGrantsT: Boolean = false, fifoId: Option[Int] = None) = { new TLSlaveParameters( setName = None, address = address, resources = resources, regionType = regionType, executable = executable, nodePath = nodePath, supports = TLMasterToSlaveTransferSizes( acquireT = supportsAcquireT, acquireB = supportsAcquireB, arithmetic = supportsArithmetic, logical = supportsLogical, get = supportsGet, putFull = supportsPutFull, putPartial = supportsPutPartial, hint = supportsHint), emits = TLSlaveToMasterTransferSizes.unknownEmits, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut, alwaysGrantsT = alwaysGrantsT, fifoId = fifoId) } def v2( address: Seq[AddressSet], nodePath: Seq[BaseNode] = Seq(), resources: Seq[Resource] = Seq(), name: Option[String] = None, regionType: RegionType.T = RegionType.GET_EFFECTS, executable: Boolean = false, fifoId: Option[Int] = None, supports: TLMasterToSlaveTransferSizes = TLMasterToSlaveTransferSizes.unknownSupports, emits: TLSlaveToMasterTransferSizes = TLSlaveToMasterTransferSizes.unknownEmits, alwaysGrantsT: Boolean = false, mayDenyGet: Boolean = false, mayDenyPut: Boolean = false) = { new TLSlaveParameters( nodePath = nodePath, resources = resources, setName = name, address = address, regionType = regionType, executable = executable, fifoId = fifoId, supports = supports, emits = emits, alwaysGrantsT = alwaysGrantsT, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut) } } object TLManagerParameters { @deprecated("Use TLSlaveParameters.v1 instead of TLManagerParameters","") def apply( address: Seq[AddressSet], resources: Seq[Resource] = Seq(), regionType: RegionType.T = RegionType.GET_EFFECTS, executable: Boolean = false, nodePath: Seq[BaseNode] = Seq(), supportsAcquireT: TransferSizes = TransferSizes.none, supportsAcquireB: TransferSizes = TransferSizes.none, supportsArithmetic: TransferSizes = TransferSizes.none, supportsLogical: TransferSizes = TransferSizes.none, supportsGet: TransferSizes = TransferSizes.none, supportsPutFull: TransferSizes = TransferSizes.none, supportsPutPartial: TransferSizes = TransferSizes.none, supportsHint: TransferSizes = TransferSizes.none, mayDenyGet: Boolean = false, mayDenyPut: Boolean = false, alwaysGrantsT: Boolean = false, fifoId: Option[Int] = None) = TLSlaveParameters.v1( address, resources, regionType, executable, nodePath, supportsAcquireT, supportsAcquireB, supportsArithmetic, supportsLogical, supportsGet, supportsPutFull, supportsPutPartial, supportsHint, mayDenyGet, mayDenyPut, alwaysGrantsT, fifoId, ) } case class TLChannelBeatBytes(a: Option[Int], b: Option[Int], c: Option[Int], d: Option[Int]) { def members = Seq(a, b, c, d) members.collect { case Some(beatBytes) => require (isPow2(beatBytes), "Data channel width must be a power of 2") } } object TLChannelBeatBytes{ def apply(beatBytes: Int): TLChannelBeatBytes = TLChannelBeatBytes( Some(beatBytes), Some(beatBytes), Some(beatBytes), Some(beatBytes)) def apply(): TLChannelBeatBytes = TLChannelBeatBytes( None, None, None, None) } class TLSlavePortParameters private( val slaves: Seq[TLSlaveParameters], val channelBytes: TLChannelBeatBytes, val endSinkId: Int, val minLatency: Int, val responseFields: Seq[BundleFieldBase], val requestKeys: Seq[BundleKeyBase]) extends SimpleProduct { def sortedSlaves = slaves.sortBy(_.sortedAddress.head) override def canEqual(that: Any): Boolean = that.isInstanceOf[TLSlavePortParameters] override def productPrefix = "TLSlavePortParameters" def productArity: Int = 6 def productElement(n: Int): Any = n match { case 0 => slaves case 1 => channelBytes case 2 => endSinkId case 3 => minLatency case 4 => responseFields case 5 => requestKeys case _ => throw new IndexOutOfBoundsException(n.toString) } require (!slaves.isEmpty, "Slave ports must have slaves") require (endSinkId >= 0, "Sink ids cannot be negative") require (minLatency >= 0, "Minimum required latency cannot be negative") // Using this API implies you cannot handle mixed-width busses def beatBytes = { channelBytes.members.foreach { width => require (width.isDefined && width == channelBytes.a) } channelBytes.a.get } // TODO this should be deprecated def managers = slaves def requireFifo(policy: TLFIFOFixer.Policy = TLFIFOFixer.allFIFO) = { val relevant = slaves.filter(m => policy(m)) relevant.foreach { m => require(m.fifoId == relevant.head.fifoId, s"${m.name} had fifoId ${m.fifoId}, which was not homogeneous (${slaves.map(s => (s.name, s.fifoId))}) ") } } // Bounds on required sizes def maxAddress = slaves.map(_.maxAddress).max def maxTransfer = slaves.map(_.maxTransfer).max def mayDenyGet = slaves.exists(_.mayDenyGet) def mayDenyPut = slaves.exists(_.mayDenyPut) // Diplomatically determined operation sizes emitted by all outward Slaves // as opposed to emits which generate circuitry to check which specific addresses val allEmitClaims = slaves.map(_.emits).reduce( _ intersect _) // Operation Emitted by at least one outward Slaves // as opposed to emits* which generate circuitry to check which specific addresses val anyEmitClaims = slaves.map(_.emits).reduce(_ mincover _) // Diplomatically determined operation sizes supported by all outward Slaves // as opposed to supports* which generate circuitry to check which specific addresses val allSupportClaims = slaves.map(_.supports).reduce( _ intersect _) val allSupportAcquireT = allSupportClaims.acquireT val allSupportAcquireB = allSupportClaims.acquireB val allSupportArithmetic = allSupportClaims.arithmetic val allSupportLogical = allSupportClaims.logical val allSupportGet = allSupportClaims.get val allSupportPutFull = allSupportClaims.putFull val allSupportPutPartial = allSupportClaims.putPartial val allSupportHint = allSupportClaims.hint // Operation supported by at least one outward Slaves // as opposed to supports* which generate circuitry to check which specific addresses val anySupportClaims = slaves.map(_.supports).reduce(_ mincover _) val anySupportAcquireT = !anySupportClaims.acquireT.none val anySupportAcquireB = !anySupportClaims.acquireB.none val anySupportArithmetic = !anySupportClaims.arithmetic.none val anySupportLogical = !anySupportClaims.logical.none val anySupportGet = !anySupportClaims.get.none val anySupportPutFull = !anySupportClaims.putFull.none val anySupportPutPartial = !anySupportClaims.putPartial.none val anySupportHint = !anySupportClaims.hint.none // Supporting Acquire means being routable for GrantAck require ((endSinkId == 0) == !anySupportAcquireB) // These return Option[TLSlaveParameters] for your convenience def find(address: BigInt) = slaves.find(_.address.exists(_.contains(address))) // The safe version will check the entire address def findSafe(address: UInt) = VecInit(sortedSlaves.map(_.address.map(_.contains(address)).reduce(_ \|\| _))) // The fast version assumes the address is valid (you probably want fastProperty instead of this function) def findFast(address: UInt) = { val routingMask = AddressDecoder(slaves.map(_.address)) VecInit(sortedSlaves.map(_.address.map(_.widen(~routingMask)).distinct.map(_.contains(address)).reduce(_ \|\| _))) } // Compute the simplest AddressSets that decide a key def fastPropertyGroup[K](p: TLSlaveParameters => K): Seq[(K, Seq[AddressSet])] = { val groups = groupByIntoSeq(sortedSlaves.map(m => (p(m), m.address)))( _._1).map { case (k, vs) => k -> vs.flatMap(_._2) } val reductionMask = AddressDecoder(groups.map(_._2)) groups.map { case (k, seq) => k -> AddressSet.unify(seq.map(_.widen(~reductionMask)).distinct) } } // Select a property def fastProperty[K, D <: Data](address: UInt, p: TLSlaveParameters => K, d: K => D): D = Mux1H(fastPropertyGroup(p).map { case (v, a) => (a.map(_.contains(address)).reduce(_\|\|_), d(v)) }) // Note: returns the actual fifoId + 1 or 0 if None def findFifoIdFast(address: UInt) = fastProperty(address, _.fifoId.map(_+1).getOrElse(0), (i:Int) => i.U) def hasFifoIdFast(address: UInt) = fastProperty(address, _.fifoId.isDefined, (b:Boolean) => b.B) // Does this Port manage this ID/address? def containsSafe(address: UInt) = findSafe(address).reduce(_ \|\| _) private def addressHelper( // setting safe to false indicates that all addresses are expected to be legal, which might reduce circuit complexity safe: Boolean, // member filters out the sizes being checked based on the opcode being emitted or supported member: TLSlaveParameters => TransferSizes, address: UInt, lgSize: UInt, // range provides a limit on the sizes that are expected to be evaluated, which might reduce circuit complexity range: Option[TransferSizes]): Bool = { // trim reduces circuit complexity by intersecting checked sizes with the range argument def trim(x: TransferSizes) = range.map(_.intersect(x)).getOrElse(x) // groupBy returns an unordered map, convert back to Seq and sort the result for determinism // groupByIntoSeq is turning slaves into trimmed membership sizes // We are grouping all the slaves by their transfer size where // if they support the trimmed size then // member is the type of transfer that you are looking for (What you are trying to filter on) // When you consider membership, you are trimming the sizes to only the ones that you care about // you are filtering the slaves based on both whether they support a particular opcode and the size // Grouping the slaves based on the actual transfer size range they support // intersecting the range and checking their membership // FOR SUPPORTCASES instead of returning the list of slaves, // you are returning a map from transfer size to the set of // address sets that are supported for that transfer size // find all the slaves that support a certain type of operation and then group their addresses by the supported size // for every size there could be multiple address ranges // safety is a trade off between checking between all possible addresses vs only the addresses // that are known to have supported sizes // the trade off is 'checking all addresses is a more expensive circuit but will always give you // the right answer even if you give it an illegal address' // the not safe version is a cheaper circuit but if you give it an illegal address then it might produce the wrong answer // fast presumes address legality // This groupByIntoSeq deterministically groups all address sets for which a given `member` transfer size applies. // In the resulting Map of cases, the keys are transfer sizes and the values are all address sets which emit or support that size. val supportCases = groupByIntoSeq(slaves)(m => trim(member(m))).map { case (k: TransferSizes, vs: Seq[TLSlaveParameters]) => k -> vs.flatMap(_.address) } // safe produces a circuit that compares against all possible addresses, // whereas fast presumes that the address is legal but uses an efficient address decoder val mask = if (safe) ~BigInt(0) else AddressDecoder(supportCases.map(_._2)) // Simplified creates the most concise possible representation of each cases' address sets based on the mask. val simplified = supportCases.map { case (k, seq) => k -> AddressSet.unify(seq.map(_.widen(~mask)).distinct) } simplified.map { case (s, a) => // s is a size, you are checking for this size either the size of the operation is in s // We return an or-reduction of all the cases, checking whether any contains both the dynamic size and dynamic address on the wire. ((Some(s) == range).B \|\| s.containsLg(lgSize)) && a.map(_.contains(address)).reduce(_\|\|_) }.foldLeft(false.B)(_\|\|_) } def supportsAcquireTSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.acquireT, address, lgSize, range) def supportsAcquireBSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.acquireB, address, lgSize, range) def supportsArithmeticSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.arithmetic, address, lgSize, range) def supportsLogicalSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.logical, address, lgSize, range) def supportsGetSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.get, address, lgSize, range) def supportsPutFullSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.putFull, address, lgSize, range) def supportsPutPartialSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.putPartial, address, lgSize, range) def supportsHintSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.hint, address, lgSize, range) def supportsAcquireTFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.acquireT, address, lgSize, range) def supportsAcquireBFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.acquireB, address, lgSize, range) def supportsArithmeticFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.arithmetic, address, lgSize, range) def supportsLogicalFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.logical, address, lgSize, range) def supportsGetFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.get, address, lgSize, range) def supportsPutFullFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.putFull, address, lgSize, range) def supportsPutPartialFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.putPartial, address, lgSize, range) def supportsHintFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.hint, address, lgSize, range) def emitsProbeSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.probe, address, lgSize, range) def emitsArithmeticSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.arithmetic, address, lgSize, range) def emitsLogicalSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.logical, address, lgSize, range) def emitsGetSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.get, address, lgSize, range) def emitsPutFullSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.putFull, address, lgSize, range) def emitsPutPartialSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.putPartial, address, lgSize, range) def emitsHintSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.hint, address, lgSize, range) def findTreeViolation() = slaves.flatMap(_.findTreeViolation()).headOption def isTree = !slaves.exists(!_.isTree) def infoString = "Slave Port Beatbytes = " + beatBytes + "\n" + "Slave Port MinLatency = " + minLatency + "\n\n" + slaves.map(_.infoString).mkString def v1copy( managers: Seq[TLSlaveParameters] = slaves, beatBytes: Int = -1, endSinkId: Int = endSinkId, minLatency: Int = minLatency, responseFields: Seq[BundleFieldBase] = responseFields, requestKeys: Seq[BundleKeyBase] = requestKeys) = { new TLSlavePortParameters( slaves = managers, channelBytes = if (beatBytes != -1) TLChannelBeatBytes(beatBytes) else channelBytes, endSinkId = endSinkId, minLatency = minLatency, responseFields = responseFields, requestKeys = requestKeys) } def v2copy( slaves: Seq[TLSlaveParameters] = slaves, channelBytes: TLChannelBeatBytes = channelBytes, endSinkId: Int = endSinkId, minLatency: Int = minLatency, responseFields: Seq[BundleFieldBase] = responseFields, requestKeys: Seq[BundleKeyBase] = requestKeys) = { new TLSlavePortParameters( slaves = slaves, channelBytes = channelBytes, endSinkId = endSinkId, minLatency = minLatency, responseFields = responseFields, requestKeys = requestKeys) } @deprecated("Use v1copy instead of copy","") def copy( managers: Seq[TLSlaveParameters] = slaves, beatBytes: Int = -1, endSinkId: Int = endSinkId, minLatency: Int = minLatency, responseFields: Seq[BundleFieldBase] = responseFields, requestKeys: Seq[BundleKeyBase] = requestKeys) = { v1copy( managers, beatBytes, endSinkId, minLatency, responseFields, requestKeys) } } object TLSlavePortParameters { def v1( managers: Seq[TLSlaveParameters], beatBytes: Int, endSinkId: Int = 0, minLatency: Int = 0, responseFields: Seq[BundleFieldBase] = Nil, requestKeys: Seq[BundleKeyBase] = Nil) = { new TLSlavePortParameters( slaves = managers, channelBytes = TLChannelBeatBytes(beatBytes), endSinkId = endSinkId, minLatency = minLatency, responseFields = responseFields, requestKeys = requestKeys) } } object TLManagerPortParameters { @deprecated("Use TLSlavePortParameters.v1 instead of TLManagerPortParameters","") def apply( managers: Seq[TLSlaveParameters], beatBytes: Int, endSinkId: Int = 0, minLatency: Int = 0, responseFields: Seq[BundleFieldBase] = Nil, requestKeys: Seq[BundleKeyBase] = Nil) = { TLSlavePortParameters.v1( managers, beatBytes, endSinkId, minLatency, responseFields, requestKeys) } } class TLMasterParameters private( val nodePath: Seq[BaseNode], val resources: Seq[Resource], val name: String, val visibility: Seq[AddressSet], val unusedRegionTypes: Set[RegionType.T], val executesOnly: Boolean, val requestFifo: Boolean, // only a request, not a requirement. applies to A, not C. val supports: TLSlaveToMasterTransferSizes, val emits: TLMasterToSlaveTransferSizes, val neverReleasesData: Boolean, val sourceId: IdRange) extends SimpleProduct { override def canEqual(that: Any): Boolean = that.isInstanceOf[TLMasterParameters] override def productPrefix = "TLMasterParameters" // We intentionally omit nodePath for equality testing / formatting def productArity: Int = 10 def productElement(n: Int): Any = n match { case 0 => name case 1 => sourceId case 2 => resources case 3 => visibility case 4 => unusedRegionTypes case 5 => executesOnly case 6 => requestFifo case 7 => supports case 8 => emits case 9 => neverReleasesData case _ => throw new IndexOutOfBoundsException(n.toString) } require (!sourceId.isEmpty) require (!visibility.isEmpty) require (supports.putFull.contains(supports.putPartial)) // We only support these operations if we support Probe (ie: we're a cache) require (supports.probe.contains(supports.arithmetic)) require (supports.probe.contains(supports.logical)) require (supports.probe.contains(supports.get)) require (supports.probe.contains(supports.putFull)) require (supports.probe.contains(supports.putPartial)) require (supports.probe.contains(supports.hint)) visibility.combinations(2).foreach { case Seq(x,y) => require (!x.overlaps(y), s"$x and $y overlap.") } val maxTransfer = List( supports.probe.max, supports.arithmetic.max, supports.logical.max, supports.get.max, supports.putFull.max, supports.putPartial.max).max def infoString = { s"""Master Name = ${name} \|visibility = ${visibility} \|emits = ${emits.infoString} \|sourceId = ${sourceId} \| \|""".stripMargin } def v1copy( name: String = name, sourceId: IdRange = sourceId, nodePath: Seq[BaseNode] = nodePath, requestFifo: Boolean = requestFifo, visibility: Seq[AddressSet] = visibility, supportsProbe: TransferSizes = supports.probe, supportsArithmetic: TransferSizes = supports.arithmetic, supportsLogical: TransferSizes = supports.logical, supportsGet: TransferSizes = supports.get, supportsPutFull: TransferSizes = supports.putFull, supportsPutPartial: TransferSizes = supports.putPartial, supportsHint: TransferSizes = supports.hint) = { new TLMasterParameters( nodePath = nodePath, resources = this.resources, name = name, visibility = visibility, unusedRegionTypes = this.unusedRegionTypes, executesOnly = this.executesOnly, requestFifo = requestFifo, supports = TLSlaveToMasterTransferSizes( probe = supportsProbe, arithmetic = supportsArithmetic, logical = supportsLogical, get = supportsGet, putFull = supportsPutFull, putPartial = supportsPutPartial, hint = supportsHint), emits = this.emits, neverReleasesData = this.neverReleasesData, sourceId = sourceId) } def v2copy( nodePath: Seq[BaseNode] = nodePath, resources: Seq[Resource] = resources, name: String = name, visibility: Seq[AddressSet] = visibility, unusedRegionTypes: Set[RegionType.T] = unusedRegionTypes, executesOnly: Boolean = executesOnly, requestFifo: Boolean = requestFifo, supports: TLSlaveToMasterTransferSizes = supports, emits: TLMasterToSlaveTransferSizes = emits, neverReleasesData: Boolean = neverReleasesData, sourceId: IdRange = sourceId) = { new TLMasterParameters( nodePath = nodePath, resources = resources, name = name, visibility = visibility, unusedRegionTypes = unusedRegionTypes, executesOnly = executesOnly, requestFifo = requestFifo, supports = supports, emits = emits, neverReleasesData = neverReleasesData, sourceId = sourceId) } @deprecated("Use v1copy instead of copy","") def copy( name: String = name, sourceId: IdRange = sourceId, nodePath: Seq[BaseNode] = nodePath, requestFifo: Boolean = requestFifo, visibility: Seq[AddressSet] = visibility, supportsProbe: TransferSizes = supports.probe, supportsArithmetic: TransferSizes = supports.arithmetic, supportsLogical: TransferSizes = supports.logical, supportsGet: TransferSizes = supports.get, supportsPutFull: TransferSizes = supports.putFull, supportsPutPartial: TransferSizes = supports.putPartial, supportsHint: TransferSizes = supports.hint) = { v1copy( name = name, sourceId = sourceId, nodePath = nodePath, requestFifo = requestFifo, visibility = visibility, supportsProbe = supportsProbe, supportsArithmetic = supportsArithmetic, supportsLogical = supportsLogical, supportsGet = supportsGet, supportsPutFull = supportsPutFull, supportsPutPartial = supportsPutPartial, supportsHint = supportsHint) } } object TLMasterParameters { def v1( name: String, sourceId: IdRange = IdRange(0,1), nodePath: Seq[BaseNode] = Seq(), requestFifo: Boolean = false, visibility: Seq[AddressSet] = Seq(AddressSet(0, ~0)), supportsProbe: TransferSizes = TransferSizes.none, supportsArithmetic: TransferSizes = TransferSizes.none, supportsLogical: TransferSizes = TransferSizes.none, supportsGet: TransferSizes = TransferSizes.none, supportsPutFull: TransferSizes = TransferSizes.none, supportsPutPartial: TransferSizes = TransferSizes.none, supportsHint: TransferSizes = TransferSizes.none) = { new TLMasterParameters( nodePath = nodePath, resources = Nil, name = name, visibility = visibility, unusedRegionTypes = Set(), executesOnly = false, requestFifo = requestFifo, supports = TLSlaveToMasterTransferSizes( probe = supportsProbe, arithmetic = supportsArithmetic, logical = supportsLogical, get = supportsGet, putFull = supportsPutFull, putPartial = supportsPutPartial, hint = supportsHint), emits = TLMasterToSlaveTransferSizes.unknownEmits, neverReleasesData = false, sourceId = sourceId) } def v2( nodePath: Seq[BaseNode] = Seq(), resources: Seq[Resource] = Nil, name: String, visibility: Seq[AddressSet] = Seq(AddressSet(0, ~0)), unusedRegionTypes: Set[RegionType.T] = Set(), executesOnly: Boolean = false, requestFifo: Boolean = false, supports: TLSlaveToMasterTransferSizes = TLSlaveToMasterTransferSizes.unknownSupports, emits: TLMasterToSlaveTransferSizes = TLMasterToSlaveTransferSizes.unknownEmits, neverReleasesData: Boolean = false, sourceId: IdRange = IdRange(0,1)) = { new TLMasterParameters( nodePath = nodePath, resources = resources, name = name, visibility = visibility, unusedRegionTypes = unusedRegionTypes, executesOnly = executesOnly, requestFifo = requestFifo, supports = supports, emits = emits, neverReleasesData = neverReleasesData, sourceId = sourceId) } } object TLClientParameters { @deprecated("Use TLMasterParameters.v1 instead of TLClientParameters","") def apply( name: String, sourceId: IdRange = IdRange(0,1), nodePath: Seq[BaseNode] = Seq(), requestFifo: Boolean = false, visibility: Seq[AddressSet] = Seq(AddressSet.everything), supportsProbe: TransferSizes = TransferSizes.none, supportsArithmetic: TransferSizes = TransferSizes.none, supportsLogical: TransferSizes = TransferSizes.none, supportsGet: TransferSizes = TransferSizes.none, supportsPutFull: TransferSizes = TransferSizes.none, supportsPutPartial: TransferSizes = TransferSizes.none, supportsHint: TransferSizes = TransferSizes.none) = { TLMasterParameters.v1( name = name, sourceId = sourceId, nodePath = nodePath, requestFifo = requestFifo, visibility = visibility, supportsProbe = supportsProbe, supportsArithmetic = supportsArithmetic, supportsLogical = supportsLogical, supportsGet = supportsGet, supportsPutFull = supportsPutFull, supportsPutPartial = supportsPutPartial, supportsHint = supportsHint) } } class TLMasterPortParameters private( val masters: Seq[TLMasterParameters], val channelBytes: TLChannelBeatBytes, val minLatency: Int, val echoFields: Seq[BundleFieldBase], val requestFields: Seq[BundleFieldBase], val responseKeys: Seq[BundleKeyBase]) extends SimpleProduct { override def canEqual(that: Any): Boolean = that.isInstanceOf[TLMasterPortParameters] override def productPrefix = "TLMasterPortParameters" def productArity: Int = 6 def productElement(n: Int): Any = n match { case 0 => masters case 1 => channelBytes case 2 => minLatency case 3 => echoFields case 4 => requestFields case 5 => responseKeys case _ => throw new IndexOutOfBoundsException(n.toString) } require (!masters.isEmpty) require (minLatency >= 0) def clients = masters // Require disjoint ranges for Ids IdRange.overlaps(masters.map(_.sourceId)).foreach { case (x, y) => require (!x.overlaps(y), s"TLClientParameters.sourceId ${x} overlaps ${y}") } // Bounds on required sizes def endSourceId = masters.map(_.sourceId.end).max def maxTransfer = masters.map(_.maxTransfer).max // The unused sources < endSourceId def unusedSources: Seq[Int] = { val usedSources = masters.map(_.sourceId).sortBy(_.start) ((Seq(0) ++ usedSources.map(_.end)) zip usedSources.map(_.start)) flatMap { case (end, start) => end until start } } // Diplomatically determined operation sizes emitted by all inward Masters // as opposed to emits* which generate circuitry to check which specific addresses val allEmitClaims = masters.map(_.emits).reduce( _ intersect _) // Diplomatically determined operation sizes Emitted by at least one inward Masters // as opposed to emits* which generate circuitry to check which specific addresses val anyEmitClaims = masters.map(_.emits).reduce(_ mincover _) // Diplomatically determined operation sizes supported by all inward Masters // as opposed to supports* which generate circuitry to check which specific addresses val allSupportProbe = masters.map(_.supports.probe) .reduce(_ intersect _) val allSupportArithmetic = masters.map(_.supports.arithmetic).reduce(_ intersect _) val allSupportLogical = masters.map(_.supports.logical) .reduce(_ intersect _) val allSupportGet = masters.map(_.supports.get) .reduce(_ intersect _) val allSupportPutFull = masters.map(_.supports.putFull) .reduce(_ intersect _) val allSupportPutPartial = masters.map(_.supports.putPartial).reduce(_ intersect _) val allSupportHint = masters.map(_.supports.hint) .reduce(_ intersect _) // Diplomatically determined operation sizes supported by at least one master // as opposed to supports* which generate circuitry to check which specific addresses val anySupportProbe = masters.map(!_.supports.probe.none) .reduce(_ \|\| _) val anySupportArithmetic = masters.map(!_.supports.arithmetic.none).reduce(_ \|\| _) val anySupportLogical = masters.map(!_.supports.logical.none) .reduce(_ \|\| _) val anySupportGet = masters.map(!_.supports.get.none) .reduce(_ \|\| _) val anySupportPutFull = masters.map(!_.supports.putFull.none) .reduce(_ \|\| _) val anySupportPutPartial = masters.map(!_.supports.putPartial.none).reduce(_ \|\| _) val anySupportHint = masters.map(!_.supports.hint.none) .reduce(_ \|\| _) // These return Option[TLMasterParameters] for your convenience def find(id: Int) = masters.find(_.sourceId.contains(id)) // Synthesizable lookup methods def find(id: UInt) = VecInit(masters.map(_.sourceId.contains(id))) def contains(id: UInt) = find(id).reduce(_ \|\| _) def requestFifo(id: UInt) = Mux1H(find(id), masters.map(c => c.requestFifo.B)) // Available during RTL runtime, checks to see if (id, size) is supported by the master's (client's) diplomatic parameters private def sourceIdHelper(member: TLMasterParameters => TransferSizes)(id: UInt, lgSize: UInt) = { val allSame = masters.map(member(_) == member(masters(0))).reduce(_ && _) // this if statement is a coarse generalization of the groupBy in the sourceIdHelper2 version; // the case where there is only one group. if (allSame) member(masters(0)).containsLg(lgSize) else { // Find the master associated with ID and returns whether that particular master is able to receive transaction of lgSize Mux1H(find(id), masters.map(member(_).containsLg(lgSize))) } } // Check for support of a given operation at a specific id val supportsProbe = sourceIdHelper(_.supports.probe) _ val supportsArithmetic = sourceIdHelper(_.supports.arithmetic) _ val supportsLogical = sourceIdHelper(_.supports.logical) _ val supportsGet = sourceIdHelper(_.supports.get) _ val supportsPutFull = sourceIdHelper(_.supports.putFull) _ val supportsPutPartial = sourceIdHelper(_.supports.putPartial) _ val supportsHint = sourceIdHelper(_.supports.hint) _ // TODO: Merge sourceIdHelper2 with sourceIdHelper private def sourceIdHelper2( member: TLMasterParameters => TransferSizes, sourceId: UInt, lgSize: UInt): Bool = { // Because sourceIds are uniquely owned by each master, we use them to group the // cases that have to be checked. val emitCases = groupByIntoSeq(masters)(m => member(m)).map { case (k, vs) => k -> vs.map(_.sourceId) } emitCases.map { case (s, a) => (s.containsLg(lgSize)) && a.map(_.contains(sourceId)).reduce(_\|\|_) }.foldLeft(false.B)(_\|\|_) } // Check for emit of a given operation at a specific id def emitsAcquireT (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.acquireT, sourceId, lgSize) def emitsAcquireB (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.acquireB, sourceId, lgSize) def emitsArithmetic(sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.arithmetic, sourceId, lgSize) def emitsLogical (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.logical, sourceId, lgSize) def emitsGet (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.get, sourceId, lgSize) def emitsPutFull (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.putFull, sourceId, lgSize) def emitsPutPartial(sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.putPartial, sourceId, lgSize) def emitsHint (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.hint, sourceId, lgSize) def infoString = masters.map(_.infoString).mkString def v1copy( clients: Seq[TLMasterParameters] = masters, minLatency: Int = minLatency, echoFields: Seq[BundleFieldBase] = echoFields, requestFields: Seq[BundleFieldBase] = requestFields, responseKeys: Seq[BundleKeyBase] = responseKeys) = { new TLMasterPortParameters( masters = clients, channelBytes = channelBytes, minLatency = minLatency, echoFields = echoFields, requestFields = requestFields, responseKeys = responseKeys) } def v2copy( masters: Seq[TLMasterParameters] = masters, channelBytes: TLChannelBeatBytes = channelBytes, minLatency: Int = minLatency, echoFields: Seq[BundleFieldBase] = echoFields, requestFields: Seq[BundleFieldBase] = requestFields, responseKeys: Seq[BundleKeyBase] = responseKeys) = { new TLMasterPortParameters( masters = masters, channelBytes = channelBytes, minLatency = minLatency, echoFields = echoFields, requestFields = requestFields, responseKeys = responseKeys) } @deprecated("Use v1copy instead of copy","") def copy( clients: Seq[TLMasterParameters] = masters, minLatency: Int = minLatency, echoFields: Seq[BundleFieldBase] = echoFields, requestFields: Seq[BundleFieldBase] = requestFields, responseKeys: Seq[BundleKeyBase] = responseKeys) = { v1copy( clients, minLatency, echoFields, requestFields, responseKeys) } } object TLClientPortParameters { @deprecated("Use TLMasterPortParameters.v1 instead of TLClientPortParameters","") def apply( clients: Seq[TLMasterParameters], minLatency: Int = 0, echoFields: Seq[BundleFieldBase] = Nil, requestFields: Seq[BundleFieldBase] = Nil, responseKeys: Seq[BundleKeyBase] = Nil) = { TLMasterPortParameters.v1( clients, minLatency, echoFields, requestFields, responseKeys) } } object TLMasterPortParameters { def v1( clients: Seq[TLMasterParameters], minLatency: Int = 0, echoFields: Seq[BundleFieldBase] = Nil, requestFields: Seq[BundleFieldBase] = Nil, responseKeys: Seq[BundleKeyBase] = Nil) = { new TLMasterPortParameters( masters = clients, channelBytes = TLChannelBeatBytes(), minLatency = minLatency, echoFields = echoFields, requestFields = requestFields, responseKeys = responseKeys) } def v2( masters: Seq[TLMasterParameters], channelBytes: TLChannelBeatBytes = TLChannelBeatBytes(), minLatency: Int = 0, echoFields: Seq[BundleFieldBase] = Nil, requestFields: Seq[BundleFieldBase] = Nil, responseKeys: Seq[BundleKeyBase] = Nil) = { new TLMasterPortParameters( masters = masters, channelBytes = channelBytes, minLatency = minLatency, echoFields = echoFields, requestFields = requestFields, responseKeys = responseKeys) } } case class TLBundleParameters( addressBits: Int, dataBits: Int, sourceBits: Int, sinkBits: Int, sizeBits: Int, echoFields: Seq[BundleFieldBase], requestFields: Seq[BundleFieldBase], responseFields: Seq[BundleFieldBase], hasBCE: Boolean) { // Chisel has issues with 0-width wires require (addressBits >= 1) require (dataBits >= 8) require (sourceBits >= 1) require (sinkBits >= 1) require (sizeBits >= 1) require (isPow2(dataBits)) echoFields.foreach { f => require (f.key.isControl, s"${f} is not a legal echo field") } val addrLoBits = log2Up(dataBits/8) // Used to uniquify bus IP names def shortName = s"a${addressBits}d${dataBits}s${sourceBits}k${sinkBits}z${sizeBits}" + (if (hasBCE) "c" else "u") def union(x: TLBundleParameters) = TLBundleParameters( max(addressBits, x.addressBits), max(dataBits, x.dataBits), max(sourceBits, x.sourceBits), max(sinkBits, x.sinkBits), max(sizeBits, x.sizeBits), echoFields = BundleField.union(echoFields ++ x.echoFields), requestFields = BundleField.union(requestFields ++ x.requestFields), responseFields = BundleField.union(responseFields ++ x.responseFields), hasBCE \|\| x.hasBCE) } object TLBundleParameters { val emptyBundleParams = TLBundleParameters( addressBits = 1, dataBits = 8, sourceBits = 1, sinkBits = 1, sizeBits = 1, echoFields = Nil, requestFields = Nil, responseFields = Nil, hasBCE = false) def union(x: Seq[TLBundleParameters]) = x.foldLeft(emptyBundleParams)((x,y) => x.union(y)) def apply(master: TLMasterPortParameters, slave: TLSlavePortParameters) = new TLBundleParameters( addressBits = log2Up(slave.maxAddress + 1), dataBits = slave.beatBytes * 8, sourceBits = log2Up(master.endSourceId), sinkBits = log2Up(slave.endSinkId), sizeBits = log2Up(log2Ceil(max(master.maxTransfer, slave.maxTransfer))+1), echoFields = master.echoFields, requestFields = BundleField.accept(master.requestFields, slave.requestKeys), responseFields = BundleField.accept(slave.responseFields, master.responseKeys), hasBCE = master.anySupportProbe && slave.anySupportAcquireB) } case class TLEdgeParameters( master: TLMasterPortParameters, slave: TLSlavePortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge { // legacy names: def manager = slave def client = master val maxTransfer = max(master.maxTransfer, slave.maxTransfer) val maxLgSize = log2Ceil(maxTransfer) // Sanity check the link... require (maxTransfer >= slave.beatBytes, s"Link's max transfer (${maxTransfer}) < ${slave.slaves.map(_.name)}'s beatBytes (${slave.beatBytes})") def diplomaticClaimsMasterToSlave = master.anyEmitClaims.intersect(slave.anySupportClaims) val bundle = TLBundleParameters(master, slave) def formatEdge = master.infoString + "\n" + slave.infoString } case class TLCreditedDelay( a: CreditedDelay, b: CreditedDelay, c: CreditedDelay, d: CreditedDelay, e: CreditedDelay) { def + (that: TLCreditedDelay): TLCreditedDelay = TLCreditedDelay( a = a + that.a, b = b + that.b, c = c + that.c, d = d + that.d, e = e + that.e) override def toString = s"(${a}, ${b}, ${c}, ${d}, ${e})" } object TLCreditedDelay { def apply(delay: CreditedDelay): TLCreditedDelay = apply(delay, delay.flip, delay, delay.flip, delay) } case class TLCreditedManagerPortParameters(delay: TLCreditedDelay, base: TLSlavePortParameters) {def infoString = base.infoString} case class TLCreditedClientPortParameters(delay: TLCreditedDelay, base: TLMasterPortParameters) {def infoString = base.infoString} case class TLCreditedEdgeParameters(client: TLCreditedClientPortParameters, manager: TLCreditedManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge { val delay = client.delay + manager.delay val bundle = TLBundleParameters(client.base, manager.base) def formatEdge = client.infoString + "\n" + manager.infoString } case class TLAsyncManagerPortParameters(async: AsyncQueueParams, base: TLSlavePortParameters) {def infoString = base.infoString} case class TLAsyncClientPortParameters(base: TLMasterPortParameters) {def infoString = base.infoString} case class TLAsyncBundleParameters(async: AsyncQueueParams, base: TLBundleParameters) case class TLAsyncEdgeParameters(client: TLAsyncClientPortParameters, manager: TLAsyncManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge { val bundle = TLAsyncBundleParameters(manager.async, TLBundleParameters(client.base, manager.base)) def formatEdge = client.infoString + "\n" + manager.infoString } case class TLRationalManagerPortParameters(direction: RationalDirection, base: TLSlavePortParameters) {def infoString = base.infoString} case class TLRationalClientPortParameters(base: TLMasterPortParameters) {def infoString = base.infoString} case class TLRationalEdgeParameters(client: TLRationalClientPortParameters, manager: TLRationalManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge { val bundle = TLBundleParameters(client.base, manager.base) def formatEdge = client.infoString + "\n" + manager.infoString } // To be unified, devices must agree on all of these terms case class ManagerUnificationKey( resources: Seq[Resource], regionType: RegionType.T, executable: Boolean, supportsAcquireT: TransferSizes, supportsAcquireB: TransferSizes, supportsArithmetic: TransferSizes, supportsLogical: TransferSizes, supportsGet: TransferSizes, supportsPutFull: TransferSizes, supportsPutPartial: TransferSizes, supportsHint: TransferSizes) object ManagerUnificationKey { def apply(x: TLSlaveParameters): ManagerUnificationKey = ManagerUnificationKey( resources = x.resources, regionType = x.regionType, executable = x.executable, supportsAcquireT = x.supportsAcquireT, supportsAcquireB = x.supportsAcquireB, supportsArithmetic = x.supportsArithmetic, supportsLogical = x.supportsLogical, supportsGet = x.supportsGet, supportsPutFull = x.supportsPutFull, supportsPutPartial = x.supportsPutPartial, supportsHint = x.supportsHint) } object ManagerUnification { def apply(slaves: Seq[TLSlaveParameters]): List[TLSlaveParameters] = { slaves.groupBy(ManagerUnificationKey.apply).values.map { seq => val agree = seq.forall(_.fifoId == seq.head.fifoId) seq(0).v1copy( address = AddressSet.unify(seq.flatMap(_.address)), fifoId = if (agree) seq(0).fifoId else None) }.toList } } case class TLBufferParams( a: BufferParams = BufferParams.none, b: BufferParams = BufferParams.none, c: BufferParams = BufferParams.none, d: BufferParams = BufferParams.none, e: BufferParams = BufferParams.none ) extends DirectedBuffers[TLBufferParams] { def copyIn(x: BufferParams) = this.copy(b = x, d = x) def copyOut(x: BufferParams) = this.copy(a = x, c = x, e = x) def copyInOut(x: BufferParams) = this.copyIn(x).copyOut(x) } /** Pretty printing of TL source id maps / class TLSourceIdMap(tl: TLMasterPortParameters) extends IdMap[TLSourceIdMapEntry] { private val tlDigits = String.valueOf(tl.endSourceId-1).length() protected val fmt = s"\t[%${tlDigits}d, %${tlDigits}d) %s%s%s" private val sorted = tl.masters.sortBy(_.sourceId) val mapping: Seq[TLSourceIdMapEntry] = sorted.map { case c => TLSourceIdMapEntry(c.sourceId, c.name, c.supports.probe, c.requestFifo) } } case class TLSourceIdMapEntry(tlId: IdRange, name: String, isCache: Boolean, requestFifo: Boolean) extends IdMapEntry { val from = tlId val to = tlId val maxTransactionsInFlight = Some(tlId.size) } File MixedNode.scala: package org.chipsalliance.diplomacy.nodes import chisel3.{Data, DontCare, Wire} import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.{Field, Parameters} import org.chipsalliance.diplomacy.ValName import org.chipsalliance.diplomacy.sourceLine /* One side metadata of a [[Dangle]]. * * Describes one side of an edge going into or out of a [[BaseNode]]. * * @param serial * the global [[BaseNode.serial]] number of the [[BaseNode]] that this [[HalfEdge]] connects to. * @param index * the `index` in the [[BaseNode]]'s input or output port list that this [[HalfEdge]] belongs to. / case class HalfEdge(serial: Int, index: Int) extends Ordered[HalfEdge] { import scala.math.Ordered.orderingToOrdered def compare(that: HalfEdge): Int = HalfEdge.unapply(this).compare(HalfEdge.unapply(that)) } /* [[Dangle]] captures the `IO` information of a [[LazyModule]] and which two [[BaseNode]]s the [[Edges]]/[[Bundle]] * connects. * * [[Dangle]]s are generated by [[BaseNode.instantiate]] using [[MixedNode.danglesOut]] and [[MixedNode.danglesIn]] , * [[LazyModuleImp.instantiate]] connects those that go to internal or explicit IO connections in a [[LazyModule]]. * * @param source * the source [[HalfEdge]] of this [[Dangle]], which captures the source [[BaseNode]] and the port `index` within * that [[BaseNode]]. * @param sink * sink [[HalfEdge]] of this [[Dangle]], which captures the sink [[BaseNode]] and the port `index` within that * [[BaseNode]]. * @param flipped * flip or not in [[AutoBundle.makeElements]]. If true this corresponds to `danglesOut`, if false it corresponds to * `danglesIn`. * @param dataOpt * actual [[Data]] for the hardware connection. Can be empty if this belongs to a cloned module / case class Dangle(source: HalfEdge, sink: HalfEdge, flipped: Boolean, name: String, dataOpt: Option[Data]) { def data = dataOpt.get } /* [[Edges]] is a collection of parameters describing the functionality and connection for an interface, which is often * derived from the interconnection protocol and can inform the parameterization of the hardware bundles that actually * implement the protocol. / case class Edges[EI, EO](in: Seq[EI], out: Seq[EO]) /* A field available in [[Parameters]] used to determine whether [[InwardNodeImp.monitor]] will be called. / case object MonitorsEnabled extends Field[Boolean](true) /* When rendering the edge in a graphical format, flip the order in which the edges' source and sink are presented. * * For example, when rendering graphML, yEd by default tries to put the source node vertically above the sink node, but * [[RenderFlipped]] inverts this relationship. When a particular [[LazyModule]] contains both source nodes and sink * nodes, flipping the rendering of one node's edge will usual produce a more concise visual layout for the * [[LazyModule]]. / case object RenderFlipped extends Field[Boolean](false) /* The sealed node class in the package, all node are derived from it. * * @param inner * Sink interface implementation. * @param outer * Source interface implementation. * @param valName * val name of this node. * @tparam DI * Downward-flowing parameters received on the inner side of the node. It is usually a brunch of parameters * describing the protocol parameters from a source. For an [[InwardNode]], it is determined by the connected * [[OutwardNode]]. Since it can be connected to multiple sources, this parameter is always a Seq of source port * parameters. * @tparam UI * Upward-flowing parameters generated by the inner side of the node. It is usually a brunch of parameters describing * the protocol parameters of a sink. For an [[InwardNode]], it is determined itself. * @tparam EI * Edge Parameters describing a connection on the inner side of the node. It is usually a brunch of transfers * specified for a sink according to protocol. * @tparam BI * Bundle type used when connecting to the inner side of the node. It is a hardware interface of this sink interface. * It should extends from [[chisel3.Data]], which represents the real hardware. * @tparam DO * Downward-flowing parameters generated on the outer side of the node. It is usually a brunch of parameters * describing the protocol parameters of a source. For an [[OutwardNode]], it is determined itself. * @tparam UO * Upward-flowing parameters received by the outer side of the node. It is usually a brunch of parameters describing * the protocol parameters from a sink. For an [[OutwardNode]], it is determined by the connected [[InwardNode]]. * Since it can be connected to multiple sinks, this parameter is always a Seq of sink port parameters. * @tparam EO * Edge Parameters describing a connection on the outer side of the node. It is usually a brunch of transfers * specified for a source according to protocol. * @tparam BO * Bundle type used when connecting to the outer side of the node. It is a hardware interface of this source * interface. It should extends from [[chisel3.Data]], which represents the real hardware. * * @note * Call Graph of [[MixedNode]] * - line `─`: source is process by a function and generate pass to others * - Arrow `→`: target of arrow is generated by source * * {{{ * (from the other node) * ┌─────────────────────────────────────────────────────────[[InwardNode.uiParams]]─────────────┐ * ↓ │ * (binding node when elaboration) [[OutwardNode.uoParams]]────────────────────────[[MixedNode.mapParamsU]]→──────────┐ │ * [[InwardNode.accPI]] │ │ │ * │ │ (based on protocol) │ * │ │ [[MixedNode.inner.edgeI]] │ * │ │ ↓ │ * ↓ │ │ │ * (immobilize after elaboration) (inward port from [[OutwardNode]]) │ ↓ │ * [[InwardNode.iBindings]]──┐ [[MixedNode.iDirectPorts]]────────────────────→[[MixedNode.iPorts]] [[InwardNode.uiParams]] │ * │ │ ↑ │ │ │ * │ │ │ [[OutwardNode.doParams]] │ │ * │ │ │ (from the other node) │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * │ │ │ └────────┬──────────────┤ │ * │ │ │ │ │ │ * │ │ │ │ (based on protocol) │ * │ │ │ │ [[MixedNode.inner.edgeI]] │ * │ │ │ │ │ │ * │ │ (from the other node) │ ↓ │ * │ └───[[OutwardNode.oPortMapping]] [[OutwardNode.oStar]] │ [[MixedNode.edgesIn]]───┐ │ * │ ↑ ↑ │ │ ↓ │ * │ │ │ │ │ [[MixedNode.in]] │ * │ │ │ │ ↓ ↑ │ * │ (solve star connection) │ │ │ [[MixedNode.bundleIn]]──┘ │ * ├───[[MixedNode.resolveStar]]→─┼─────────────────────────────┤ └────────────────────────────────────┐ │ * │ │ │ [[MixedNode.bundleOut]]─┐ │ │ * │ │ │ ↑ ↓ │ │ * │ │ │ │ [[MixedNode.out]] │ │ * │ ↓ ↓ │ ↑ │ │ * │ ┌─────[[InwardNode.iPortMapping]] [[InwardNode.iStar]] [[MixedNode.edgesOut]]──┘ │ │ * │ │ (from the other node) ↑ │ │ * │ │ │ │ │ │ * │ │ │ [[MixedNode.outer.edgeO]] │ │ * │ │ │ (based on protocol) │ │ * │ │ │ │ │ │ * │ │ │ ┌────────────────────────────────────────┤ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * (immobilize after elaboration)│ ↓ │ │ │ │ * [[OutwardNode.oBindings]]─┘ [[MixedNode.oDirectPorts]]───→[[MixedNode.oPorts]] [[OutwardNode.doParams]] │ │ * ↑ (inward port from [[OutwardNode]]) │ │ │ │ * │ ┌─────────────────────────────────────────┤ │ │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * [[OutwardNode.accPO]] │ ↓ │ │ │ * (binding node when elaboration) │ [[InwardNode.diParams]]─────→[[MixedNode.mapParamsD]]────────────────────────────┘ │ │ * │ ↑ │ │ * │ └──────────────────────────────────────────────────────────────────────────────────────────┘ │ * └──────────────────────────────────────────────────────────────────────────────────────────────────────────┘ * }}} / abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data]( val inner: InwardNodeImp[DI, UI, EI, BI], val outer: OutwardNodeImp[DO, UO, EO, BO] )( implicit valName: ValName) extends BaseNode with NodeHandle[DI, UI, EI, BI, DO, UO, EO, BO] with InwardNode[DI, UI, BI] with OutwardNode[DO, UO, BO] { // Generate a [[NodeHandle]] with inward and outward node are both this node. val inward = this val outward = this /* Debug info of nodes binding. / def bindingInfo: String = s"""$iBindingInfo \|$oBindingInfo \|""".stripMargin /* Debug info of ports connecting. / def connectedPortsInfo: String = s"""${oPorts.size} outward ports connected: [${oPorts.map(_._2.name).mkString(",")}] \|${iPorts.size} inward ports connected: [${iPorts.map(_._2.name).mkString(",")}] \|""".stripMargin /* Debug info of parameters propagations. / def parametersInfo: String = s"""${doParams.size} downstream outward parameters: [${doParams.mkString(",")}] \|${uoParams.size} upstream outward parameters: [${uoParams.mkString(",")}] \|${diParams.size} downstream inward parameters: [${diParams.mkString(",")}] \|${uiParams.size} upstream inward parameters: [${uiParams.mkString(",")}] \|""".stripMargin /* For a given node, converts [[OutwardNode.accPO]] and [[InwardNode.accPI]] to [[MixedNode.oPortMapping]] and * [[MixedNode.iPortMapping]]. * * Given counts of known inward and outward binding and inward and outward star bindings, return the resolved inward * stars and outward stars. * * This method will also validate the arguments and throw a runtime error if the values are unsuitable for this type * of node. * * @param iKnown * Number of known-size ([[BIND_ONCE]]) input bindings. * @param oKnown * Number of known-size ([[BIND_ONCE]]) output bindings. * @param iStar * Number of unknown size ([[BIND_STAR]]) input bindings. * @param oStar * Number of unknown size ([[BIND_STAR]]) output bindings. * @return * A Tuple of the resolved number of input and output connections. / protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStar: Int, oStar: Int): (Int, Int) /* Function to generate downward-flowing outward params from the downward-flowing input params and the current output * ports. * * @param n * The size of the output sequence to generate. * @param p * Sequence of downward-flowing input parameters of this node. * @return * A `n`-sized sequence of downward-flowing output edge parameters. / protected[diplomacy] def mapParamsD(n: Int, p: Seq[DI]): Seq[DO] /* Function to generate upward-flowing input parameters from the upward-flowing output parameters [[uiParams]]. * * @param n * Size of the output sequence. * @param p * Upward-flowing output edge parameters. * @return * A n-sized sequence of upward-flowing input edge parameters. / protected[diplomacy] def mapParamsU(n: Int, p: Seq[UO]): Seq[UI] /* @return * The sink cardinality of the node, the number of outputs bound with [[BIND_QUERY]] summed with inputs bound with * [[BIND_STAR]]. / protected[diplomacy] lazy val sinkCard: Int = oBindings.count(_._3 == BIND_QUERY) + iBindings.count(_._3 == BIND_STAR) /* @return * The source cardinality of this node, the number of inputs bound with [[BIND_QUERY]] summed with the number of * output bindings bound with [[BIND_STAR]]. / protected[diplomacy] lazy val sourceCard: Int = iBindings.count(_._3 == BIND_QUERY) + oBindings.count(_._3 == BIND_STAR) /* @return list of nodes involved in flex bindings with this node. / protected[diplomacy] lazy val flexes: Seq[BaseNode] = oBindings.filter(_._3 == BIND_FLEX).map(_._2) ++ iBindings.filter(_._3 == BIND_FLEX).map(_._2) /* Resolves the flex to be either source or sink and returns the offset where the [[BIND_STAR]] operators begin * greedily taking up the remaining connections. * * @return * A value >= 0 if it is sink cardinality, a negative value for source cardinality. The magnitude of the return * value is not relevant. / protected[diplomacy] lazy val flexOffset: Int = { /* Recursively performs a depth-first search of the [[flexes]], [[BaseNode]]s connected to this node with flex * operators. The algorithm bottoms out when we either get to a node we have already visited or when we get to a * connection that is not a flex and can set the direction for us. Otherwise, recurse by visiting the `flexes` of * each node in the current set and decide whether they should be added to the set or not. * * @return * the mapping of [[BaseNode]] indexed by their serial numbers. / def DFS(v: BaseNode, visited: Map[Int, BaseNode]): Map[Int, BaseNode] = { if (visited.contains(v.serial) \|\| !v.flexibleArityDirection) { visited } else { v.flexes.foldLeft(visited + (v.serial -> v))((sum, n) => DFS(n, sum)) } } /* Determine which [[BaseNode]] are involved in resolving the flex connections to/from this node. * * @example * {{{ * a := b := c * d := b * e := f * }}} * * `flexSet` for `a`, `b`, `c`, or `d` will be `Set(a, b, c, d)` `flexSet` for `e` or `f` will be `Set(e,f)` / val flexSet = DFS(this, Map()).values /* The total number of := operators where we're on the left. / val allSink = flexSet.map(_.sinkCard).sum /** The total number of :=* operators used when we're on the right. / val allSource = flexSet.map(_.sourceCard).sum require( allSink == 0 \|\| allSource == 0, s"The nodes ${flexSet.map(_.name)} which are inter-connected by :=* have ${allSink} := operators and ${allSource} := operators connected to them, making it impossible to determine cardinality inference direction." ) allSink - allSource } /** @return A value >= 0 if it is sink cardinality, a negative value for source cardinality. / protected[diplomacy] def edgeArityDirection(n: BaseNode): Int = { if (flexibleArityDirection) flexOffset else if (n.flexibleArityDirection) n.flexOffset else 0 } /* For a node which is connected between two nodes, select the one that will influence the direction of the flex * resolution. / protected[diplomacy] def edgeAritySelect(n: BaseNode, l: => Int, r: => Int): Int = { val dir = edgeArityDirection(n) if (dir < 0) l else if (dir > 0) r else 1 } /* Ensure that the same node is not visited twice in resolving `:=`, etc operators. / private var starCycleGuard = false /** Resolve all the star operators into concrete indicies. As connections are being made, some may be "star" * connections which need to be resolved. In some way to determine how many actual edges they correspond to. We also * need to build up the ranges of edges which correspond to each binding operator, so that We can apply the correct * edge parameters and later build up correct bundle connections. * * [[oPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that oPort (binding * operator). [[iPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that iPort * (binding operator). [[oStar]]: `Int` the value to return for this node `N` for any `N := foo` or `N :=* foo := bar` [[iStar]]: `Int` the value to return for this node `N` for any `foo :=* N` or `bar :=* foo := N` / protected[diplomacy] lazy val ( oPortMapping: Seq[(Int, Int)], iPortMapping: Seq[(Int, Int)], oStar: Int, iStar: Int ) = { try { if (starCycleGuard) throw StarCycleException() starCycleGuard = true // For a given node N... // Number of foo := N // + Number of bar :=* foo := N val oStars = oBindings.count { case (_, n, b, _, _) => b == BIND_STAR \|\| (b == BIND_FLEX && edgeArityDirection(n) < 0) } // Number of N := foo // + Number of N :=* foo := bar val iStars = iBindings.count { case (_, n, b, _, _) => b == BIND_STAR \|\| (b == BIND_FLEX && edgeArityDirection(n) > 0) } // 1 for foo := N // + bar.iStar for bar := foo := N // + foo.iStar for foo := N // + 0 for foo := N val oKnown = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, 0, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => 0 } }.sum // 1 for N := foo // + bar.oStar for N := foo :=* bar // + foo.oStar for N :=* foo // + 0 for N := foo val iKnown = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, 0) case BIND_QUERY => n.oStar case BIND_STAR => 0 } }.sum // Resolve star depends on the node subclass to implement the algorithm for this. val (iStar, oStar) = resolveStar(iKnown, oKnown, iStars, oStars) // Cumulative list of resolved outward binding range starting points val oSum = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, oStar, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => oStar } }.scanLeft(0)(_ + _) // Cumulative list of resolved inward binding range starting points val iSum = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, iStar) case BIND_QUERY => n.oStar case BIND_STAR => iStar } }.scanLeft(0)(_ + _) // Create ranges for each binding based on the running sums and return // those along with resolved values for the star operations. (oSum.init.zip(oSum.tail), iSum.init.zip(iSum.tail), oStar, iStar) } catch { case c: StarCycleException => throw c.copy(loop = context +: c.loop) } } /* Sequence of inward ports. * * This should be called after all star bindings are resolved. * * Each element is: `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. * `n` Instance of inward node. `p` View of [[Parameters]] where this connection was made. `s` Source info where this * connection was made in the source code. / protected[diplomacy] lazy val oDirectPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oBindings.flatMap { case (i, n, _, p, s) => // for each binding operator in this node, look at what it connects to val (start, end) = n.iPortMapping(i) (start until end).map { j => (j, n, p, s) } } /* Sequence of outward ports. * * This should be called after all star bindings are resolved. * * `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. `n` Instance of * outward node. `p` View of [[Parameters]] where this connection was made. `s` [[SourceInfo]] where this connection * was made in the source code. / protected[diplomacy] lazy val iDirectPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iBindings.flatMap { case (i, n, _, p, s) => // query this port index range of this node in the other side of node. val (start, end) = n.oPortMapping(i) (start until end).map { j => (j, n, p, s) } } // Ephemeral nodes ( which have non-None iForward/oForward) have in_degree = out_degree // Thus, there must exist an Eulerian path and the below algorithms terminate @scala.annotation.tailrec private def oTrace( tuple: (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) ): (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.iForward(i) match { case None => (i, n, p, s) case Some((j, m)) => oTrace((j, m, p, s)) } } @scala.annotation.tailrec private def iTrace( tuple: (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) ): (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.oForward(i) match { case None => (i, n, p, s) case Some((j, m)) => iTrace((j, m, p, s)) } } /* Final output ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - Numeric index of this binding in the [[InwardNode]] on the other end. * - [[InwardNode]] on the other end of this binding. * - A view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. / lazy val oPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oDirectPorts.map(oTrace) /* Final input ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - numeric index of this binding in [[OutwardNode]] on the other end. * - [[OutwardNode]] on the other end of this binding. * - a view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. / lazy val iPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iDirectPorts.map(iTrace) private var oParamsCycleGuard = false protected[diplomacy] lazy val diParams: Seq[DI] = iPorts.map { case (i, n, _, _) => n.doParams(i) } protected[diplomacy] lazy val doParams: Seq[DO] = { try { if (oParamsCycleGuard) throw DownwardCycleException() oParamsCycleGuard = true val o = mapParamsD(oPorts.size, diParams) require( o.size == oPorts.size, s"""Diplomacy has detected a problem with your graph: \|At the following node, the number of outward ports should equal the number of produced outward parameters. \|$context \|$connectedPortsInfo \|Downstreamed inward parameters: [${diParams.mkString(",")}] \|Produced outward parameters: [${o.mkString(",")}] \|""".stripMargin ) o.map(outer.mixO(_, this)) } catch { case c: DownwardCycleException => throw c.copy(loop = context +: c.loop) } } private var iParamsCycleGuard = false protected[diplomacy] lazy val uoParams: Seq[UO] = oPorts.map { case (o, n, _, _) => n.uiParams(o) } protected[diplomacy] lazy val uiParams: Seq[UI] = { try { if (iParamsCycleGuard) throw UpwardCycleException() iParamsCycleGuard = true val i = mapParamsU(iPorts.size, uoParams) require( i.size == iPorts.size, s"""Diplomacy has detected a problem with your graph: \|At the following node, the number of inward ports should equal the number of produced inward parameters. \|$context \|$connectedPortsInfo \|Upstreamed outward parameters: [${uoParams.mkString(",")}] \|Produced inward parameters: [${i.mkString(",")}] \|""".stripMargin ) i.map(inner.mixI(_, this)) } catch { case c: UpwardCycleException => throw c.copy(loop = context +: c.loop) } } /* Outward edge parameters. / protected[diplomacy] lazy val edgesOut: Seq[EO] = (oPorts.zip(doParams)).map { case ((i, n, p, s), o) => outer.edgeO(o, n.uiParams(i), p, s) } /* Inward edge parameters. / protected[diplomacy] lazy val edgesIn: Seq[EI] = (iPorts.zip(uiParams)).map { case ((o, n, p, s), i) => inner.edgeI(n.doParams(o), i, p, s) } /* A tuple of the input edge parameters and output edge parameters for the edges bound to this node. * * If you need to access to the edges of a foreign Node, use this method (in/out create bundles). / lazy val edges: Edges[EI, EO] = Edges(edgesIn, edgesOut) /* Create actual Wires corresponding to the Bundles parameterized by the outward edges of this node. / protected[diplomacy] lazy val bundleOut: Seq[BO] = edgesOut.map { e => val x = Wire(outer.bundleO(e)).suggestName(s"${valName.value}Out") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } /* Create actual Wires corresponding to the Bundles parameterized by the inward edges of this node. / protected[diplomacy] lazy val bundleIn: Seq[BI] = edgesIn.map { e => val x = Wire(inner.bundleI(e)).suggestName(s"${valName.value}In") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } private def emptyDanglesOut: Seq[Dangle] = oPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(serial, i), sink = HalfEdge(n.serial, j), flipped = false, name = wirePrefix + "out", dataOpt = None ) } private def emptyDanglesIn: Seq[Dangle] = iPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(n.serial, j), sink = HalfEdge(serial, i), flipped = true, name = wirePrefix + "in", dataOpt = None ) } /* Create the [[Dangle]]s which describe the connections from this node output to other nodes inputs. / protected[diplomacy] def danglesOut: Seq[Dangle] = emptyDanglesOut.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleOut(i))) } /* Create the [[Dangle]]s which describe the connections from this node input from other nodes outputs. / protected[diplomacy] def danglesIn: Seq[Dangle] = emptyDanglesIn.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleIn(i))) } private[diplomacy] var instantiated = false /* Gather Bundle and edge parameters of outward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. / def out: Seq[(BO, EO)] = { require( instantiated, s"$name.out should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleOut.zip(edgesOut) } /* Gather Bundle and edge parameters of inward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. / def in: Seq[(BI, EI)] = { require( instantiated, s"$name.in should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleIn.zip(edgesIn) } /* Actually instantiate this node during [[LazyModuleImp]] evaluation. Mark that it's safe to use the Bundle wires, * instantiate monitors on all input ports if appropriate, and return all the dangles of this node. / protected[diplomacy] def instantiate(): Seq[Dangle] = { instantiated = true if (!circuitIdentity) { (iPorts.zip(in)).foreach { case ((_, _, p, _), (b, e)) => if (p(MonitorsEnabled)) inner.monitor(b, e) } } danglesOut ++ danglesIn } protected[diplomacy] def cloneDangles(): Seq[Dangle] = emptyDanglesOut ++ emptyDanglesIn /* Connects the outward part of a node with the inward part of this node. / protected[diplomacy] def bind( h: OutwardNode[DI, UI, BI], binding: NodeBinding )( implicit p: Parameters, sourceInfo: SourceInfo ): Unit = { val x = this // x := y val y = h sourceLine(sourceInfo, " at ", "") val i = x.iPushed val o = y.oPushed y.oPush( i, x, binding match { case BIND_ONCE => BIND_ONCE case BIND_FLEX => BIND_FLEX case BIND_STAR => BIND_QUERY case BIND_QUERY => BIND_STAR } ) x.iPush(o, y, binding) } / Metadata for printing the node graph. / def inputs: Seq[(OutwardNode[DI, UI, BI], RenderedEdge)] = (iPorts.zip(edgesIn)).map { case ((_, n, p, _), e) => val re = inner.render(e) (n, re.copy(flipped = re.flipped != p(RenderFlipped))) } /* Metadata for printing the node graph / def outputs: Seq[(InwardNode[DO, UO, BO], RenderedEdge)] = oPorts.map { case (i, n, _, _) => (n, n.inputs(i)._2) } } File CustomBootPin.scala: package testchipip.boot import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config._ import freechips.rocketchip.diplomacy._ import freechips.rocketchip.tilelink._ import freechips.rocketchip.devices.tilelink._ import freechips.rocketchip.regmapper._ import freechips.rocketchip.subsystem._ case class CustomBootPinParams( customBootAddress: BigInt = 0x80000000L, // Default is DRAM_BASE masterWhere: TLBusWrapperLocation = CBUS // This needs to write to clint and bootaddrreg, which are on CBUS/PBUS ) case object CustomBootPinKey extends Field[Option[CustomBootPinParams]](None) trait CanHavePeripheryCustomBootPin { this: BaseSubsystem => val custom_boot_pin = p(CustomBootPinKey).map { params => require(p(BootAddrRegKey).isDefined, "CustomBootPin relies on existence of BootAddrReg") val tlbus = locateTLBusWrapper(params.masterWhere) val clientParams = TLMasterPortParameters.v1( clients = Seq(TLMasterParameters.v1( name = "custom-boot", sourceId = IdRange(0, 1), )), minLatency = 1 ) val inner_io = tlbus { val node = TLClientNode(Seq(clientParams)) tlbus.coupleFrom(s"port_named_custom_boot_pin") ({ _ := node }) InModuleBody { val custom_boot = IO(Input(Bool())).suggestName("custom_boot") val (tl, edge) = node.out(0) val inactive :: waiting_bootaddr_reg_a :: waiting_bootaddr_reg_d :: waiting_msip_a :: waiting_msip_d :: dead :: Nil = Enum(6) val state = RegInit(inactive) tl.a.valid := false.B tl.a.bits := DontCare tl.d.ready := true.B switch (state) { is (inactive) { when (custom_boot) { state := waiting_bootaddr_reg_a } } is (waiting_bootaddr_reg_a) { tl.a.valid := true.B tl.a.bits := edge.Put( toAddress = p(BootAddrRegKey).get.bootRegAddress.U, fromSource = 0.U, lgSize = 2.U, data = params.customBootAddress.U )._2 when (tl.a.fire) { state := waiting_bootaddr_reg_d } } is (waiting_bootaddr_reg_d) { when (tl.d.fire) { state := waiting_msip_a } } is (waiting_msip_a) { tl.a.valid := true.B tl.a.bits := edge.Put( toAddress = (p(CLINTKey).get.baseAddress + CLINTConsts.msipOffset(0)).U, // msip for hart0 fromSource = 0.U, lgSize = log2Ceil(CLINTConsts.msipBytes).U, data = 1.U )._2 when (tl.a.fire) { state := waiting_msip_d } } is (waiting_msip_d) { when (tl.d.fire) { state := dead } } is (dead) { when (!custom_boot) { state := inactive } } } custom_boot } } val outer_io = InModuleBody { val custom_boot = IO(Input(Bool())).suggestName("custom_boot") inner_io := custom_boot custom_boot } outer_io } } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportPutFull \|\| manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB \|\| manager.anySupportGet \|\| manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportPutFull \|\| client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe \|\| client.anySupportGet \|\| client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet \|\| client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull \|\| client.anySupportPutPartial \|\| client.anySupportHint \|\| client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet \|\| manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull \|\| manager.anySupportPutPartial \|\| manager.anySupportHint \|\| manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) \|\| !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.ProbeAckData \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode \| small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U \|\| beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } } File LazyScope.scala: package org.chipsalliance.diplomacy.lazymodule import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.ValName /** Allows dynamic creation of [[Module]] hierarchy and "shoving" logic into a [[LazyModule]]. / trait LazyScope { this: LazyModule => override def toString: String = s"LazyScope named $name" /* Evaluate `body` in the current [[LazyModule.scope]] / def apply[T](body: => T): T = { // Preserve the previous value of the [[LazyModule.scope]], because when calling [[apply]] function, // [[LazyModule.scope]] will be altered. val saved = LazyModule.scope // [[LazyModule.scope]] stack push. LazyModule.scope = Some(this) // Evaluate [[body]] in the current `scope`, saving the result to [[out]]. val out = body // Check that the `scope` after evaluating `body` is the same as when we started. require(LazyModule.scope.isDefined, s"LazyScope $name tried to exit, but scope was empty!") require( LazyModule.scope.get eq this, s"LazyScope $name exited before LazyModule ${LazyModule.scope.get.name} was closed" ) // [[LazyModule.scope]] stack pop. LazyModule.scope = saved out } } /* Used to automatically create a level of module hierarchy (a [[SimpleLazyModule]]) within which [[LazyModule]]s can * be instantiated and connected. * * It will instantiate a [[SimpleLazyModule]] to manage evaluation of `body` and evaluate `body` code snippets in this * scope. / object LazyScope { /* Create a [[LazyScope]] with an implicit instance name. * * @param body * code executed within the generated [[SimpleLazyModule]]. * @param valName * instance name of generated [[SimpleLazyModule]]. * @param p * [[Parameters]] propagated to [[SimpleLazyModule]]. / def apply[T]( body: => T )( implicit valName: ValName, p: Parameters ): T = { apply(valName.value, "SimpleLazyModule", None)(body)(p) } /* Create a [[LazyScope]] with an explicitly defined instance name. * * @param name * instance name of generated [[SimpleLazyModule]]. * @param body * code executed within the generated `SimpleLazyModule` * @param p * [[Parameters]] propagated to [[SimpleLazyModule]]. / def apply[T]( name: String )(body: => T )( implicit p: Parameters ): T = { apply(name, "SimpleLazyModule", None)(body)(p) } /* Create a [[LazyScope]] with an explicit instance and class name, and control inlining. * * @param name * instance name of generated [[SimpleLazyModule]]. * @param desiredModuleName * class name of generated [[SimpleLazyModule]]. * @param overrideInlining * tell FIRRTL that this [[SimpleLazyModule]]'s module should be inlined. * @param body * code executed within the generated `SimpleLazyModule` * @param p * [[Parameters]] propagated to [[SimpleLazyModule]]. / def apply[T]( name: String, desiredModuleName: String, overrideInlining: Option[Boolean] = None )(body: => T )( implicit p: Parameters ): T = { val scope = LazyModule(new SimpleLazyModule with LazyScope { override lazy val desiredName = desiredModuleName override def shouldBeInlined = overrideInlining.getOrElse(super.shouldBeInlined) }).suggestName(name) scope { body } } /* Create a [[LazyScope]] to temporarily group children for some reason, but tell Firrtl to inline it. * * For example, we might want to control a set of children's clocks but then not keep the parent wrapper. * * @param body * code executed within the generated `SimpleLazyModule` * @param p * [[Parameters]] propagated to [[SimpleLazyModule]]. */ def inline[T]( body: => T )( implicit p: Parameters ): T = { apply("noname", "ShouldBeInlined", Some(false))(body)(p) } }	module PeripheryBus_cbus( // @[ClockDomain.scala:14:9] input auto_coupler_to_prci_ctrl_fixer_anon_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_prci_ctrl_fixer_anon_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [2:0] auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [8:0] auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [20:0] auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_prci_ctrl_fixer_anon_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_coupler_to_prci_ctrl_fixer_anon_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_coupler_to_prci_ctrl_fixer_anon_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_coupler_to_prci_ctrl_fixer_anon_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [8:0] auto_coupler_to_prci_ctrl_fixer_anon_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input [63:0] auto_coupler_to_prci_ctrl_fixer_anon_out_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_coupler_to_bootrom_fragmenter_anon_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_bootrom_fragmenter_anon_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [1:0] auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [12:0] auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [16:0] auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_bootrom_fragmenter_anon_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_coupler_to_bootrom_fragmenter_anon_out_d_valid, // @[LazyModuleImp.scala:107:25] input [1:0] auto_coupler_to_bootrom_fragmenter_anon_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [12:0] auto_coupler_to_bootrom_fragmenter_anon_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input [63:0] auto_coupler_to_bootrom_fragmenter_anon_out_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_coupler_to_debug_fragmenter_anon_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_debug_fragmenter_anon_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_coupler_to_debug_fragmenter_anon_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_coupler_to_debug_fragmenter_anon_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [1:0] auto_coupler_to_debug_fragmenter_anon_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [12:0] auto_coupler_to_debug_fragmenter_anon_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [11:0] auto_coupler_to_debug_fragmenter_anon_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_coupler_to_debug_fragmenter_anon_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_coupler_to_debug_fragmenter_anon_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_debug_fragmenter_anon_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_debug_fragmenter_anon_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_coupler_to_debug_fragmenter_anon_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_coupler_to_debug_fragmenter_anon_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_coupler_to_debug_fragmenter_anon_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [12:0] auto_coupler_to_debug_fragmenter_anon_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input [63:0] auto_coupler_to_debug_fragmenter_anon_out_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_coupler_to_plic_fragmenter_anon_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_plic_fragmenter_anon_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_coupler_to_plic_fragmenter_anon_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_coupler_to_plic_fragmenter_anon_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [1:0] auto_coupler_to_plic_fragmenter_anon_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [12:0] auto_coupler_to_plic_fragmenter_anon_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [27:0] auto_coupler_to_plic_fragmenter_anon_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_coupler_to_plic_fragmenter_anon_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_coupler_to_plic_fragmenter_anon_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_plic_fragmenter_anon_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_plic_fragmenter_anon_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_coupler_to_plic_fragmenter_anon_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_coupler_to_plic_fragmenter_anon_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_coupler_to_plic_fragmenter_anon_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [12:0] auto_coupler_to_plic_fragmenter_anon_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input [63:0] auto_coupler_to_plic_fragmenter_anon_out_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_coupler_to_clint_fragmenter_anon_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_clint_fragmenter_anon_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_coupler_to_clint_fragmenter_anon_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_coupler_to_clint_fragmenter_anon_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [1:0] auto_coupler_to_clint_fragmenter_anon_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [12:0] auto_coupler_to_clint_fragmenter_anon_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [25:0] auto_coupler_to_clint_fragmenter_anon_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_coupler_to_clint_fragmenter_anon_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_coupler_to_clint_fragmenter_anon_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_clint_fragmenter_anon_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_clint_fragmenter_anon_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_coupler_to_clint_fragmenter_anon_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_coupler_to_clint_fragmenter_anon_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_coupler_to_clint_fragmenter_anon_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [12:0] auto_coupler_to_clint_fragmenter_anon_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input [63:0] auto_coupler_to_clint_fragmenter_anon_out_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_coupler_to_bus_named_pbus_bus_xing_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_bus_named_pbus_bus_xing_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [2:0] auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [8:0] auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [28:0] auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_bus_named_pbus_bus_xing_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_coupler_to_bus_named_pbus_bus_xing_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_coupler_to_bus_named_pbus_bus_xing_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_coupler_to_bus_named_pbus_bus_xing_out_d_bits_param, // @[LazyModuleImp.scala:107:25] input [2:0] auto_coupler_to_bus_named_pbus_bus_xing_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [8:0] auto_coupler_to_bus_named_pbus_bus_xing_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input auto_coupler_to_bus_named_pbus_bus_xing_out_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_coupler_to_bus_named_pbus_bus_xing_out_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_coupler_to_bus_named_pbus_bus_xing_out_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_coupler_to_bus_named_pbus_bus_xing_out_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_coupler_to_l2_ctrl_buffer_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_l2_ctrl_buffer_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_coupler_to_l2_ctrl_buffer_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_coupler_to_l2_ctrl_buffer_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [1:0] auto_coupler_to_l2_ctrl_buffer_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [12:0] auto_coupler_to_l2_ctrl_buffer_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [25:0] auto_coupler_to_l2_ctrl_buffer_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_coupler_to_l2_ctrl_buffer_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_coupler_to_l2_ctrl_buffer_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_l2_ctrl_buffer_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_l2_ctrl_buffer_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_coupler_to_l2_ctrl_buffer_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_coupler_to_l2_ctrl_buffer_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_coupler_to_l2_ctrl_buffer_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [12:0] auto_coupler_to_l2_ctrl_buffer_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input [63:0] auto_coupler_to_l2_ctrl_buffer_out_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_fixedClockNode_anon_out_5_clock, // @[LazyModuleImp.scala:107:25] output auto_fixedClockNode_anon_out_5_reset, // @[LazyModuleImp.scala:107:25] output auto_fixedClockNode_anon_out_4_clock, // @[LazyModuleImp.scala:107:25] output auto_fixedClockNode_anon_out_4_reset, // @[LazyModuleImp.scala:107:25] output auto_fixedClockNode_anon_out_3_clock, // @[LazyModuleImp.scala:107:25] output auto_fixedClockNode_anon_out_3_reset, // @[LazyModuleImp.scala:107:25] output auto_fixedClockNode_anon_out_2_clock, // @[LazyModuleImp.scala:107:25] output auto_fixedClockNode_anon_out_2_reset, // @[LazyModuleImp.scala:107:25] output auto_fixedClockNode_anon_out_1_clock, // @[LazyModuleImp.scala:107:25] output auto_fixedClockNode_anon_out_1_reset, // @[LazyModuleImp.scala:107:25] output auto_fixedClockNode_anon_out_0_clock, // @[LazyModuleImp.scala:107:25] output auto_fixedClockNode_anon_out_0_reset, // @[LazyModuleImp.scala:107:25] input auto_cbus_clock_groups_in_member_cbus_0_clock, // @[LazyModuleImp.scala:107:25] input auto_cbus_clock_groups_in_member_cbus_0_reset, // @[LazyModuleImp.scala:107:25] output auto_bus_xing_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_bus_xing_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_bus_xing_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_bus_xing_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_bus_xing_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [7:0] auto_bus_xing_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [28:0] auto_bus_xing_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_bus_xing_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_bus_xing_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_bus_xing_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_bus_xing_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_bus_xing_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_bus_xing_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_bus_xing_in_d_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_bus_xing_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [7:0] auto_bus_xing_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output auto_bus_xing_in_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_bus_xing_in_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [63:0] auto_bus_xing_in_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_bus_xing_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input custom_boot // @[CustomBootPin.scala:36:29] ); wire coupler_from_port_named_custom_boot_pin_auto_tl_out_d_valid; // @[LazyModuleImp.scala:138:7] wire coupler_from_port_named_custom_boot_pin_auto_tl_out_d_bits_corrupt; // @[LazyModuleImp.scala:138:7] wire [63:0] coupler_from_port_named_custom_boot_pin_auto_tl_out_d_bits_data; // @[LazyModuleImp.scala:138:7] wire coupler_from_port_named_custom_boot_pin_auto_tl_out_d_bits_denied; // @[LazyModuleImp.scala:138:7] wire coupler_from_port_named_custom_boot_pin_auto_tl_out_d_bits_sink; // @[LazyModuleImp.scala:138:7] wire [3:0] coupler_from_port_named_custom_boot_pin_auto_tl_out_d_bits_size; // @[LazyModuleImp.scala:138:7] wire [1:0] coupler_from_port_named_custom_boot_pin_auto_tl_out_d_bits_param; // @[LazyModuleImp.scala:138:7] wire [2:0] coupler_from_port_named_custom_boot_pin_auto_tl_out_d_bits_opcode; // @[LazyModuleImp.scala:138:7] wire coupler_from_port_named_custom_boot_pin_auto_tl_out_a_ready; // @[LazyModuleImp.scala:138:7] wire coupler_from_port_named_custom_boot_pin_auto_tl_in_d_valid; // @[LazyModuleImp.scala:138:7] wire coupler_from_port_named_custom_boot_pin_auto_tl_in_d_bits_corrupt; // @[LazyModuleImp.scala:138:7] wire [63:0] coupler_from_port_named_custom_boot_pin_auto_tl_in_d_bits_data; // @[LazyModuleImp.scala:138:7] wire coupler_from_port_named_custom_boot_pin_auto_tl_in_d_bits_denied; // @[LazyModuleImp.scala:138:7] wire coupler_from_port_named_custom_boot_pin_auto_tl_in_d_bits_sink; // @[LazyModuleImp.scala:138:7] wire [3:0] coupler_from_port_named_custom_boot_pin_auto_tl_in_d_bits_size; // @[LazyModuleImp.scala:138:7] wire [1:0] coupler_from_port_named_custom_boot_pin_auto_tl_in_d_bits_param; // @[LazyModuleImp.scala:138:7] wire [2:0] coupler_from_port_named_custom_boot_pin_auto_tl_in_d_bits_opcode; // @[LazyModuleImp.scala:138:7] wire coupler_from_port_named_custom_boot_pin_auto_tl_in_a_valid; // @[LazyModuleImp.scala:138:7] wire coupler_from_port_named_custom_boot_pin_auto_tl_in_a_ready; // @[LazyModuleImp.scala:138:7] wire [63:0] coupler_from_port_named_custom_boot_pin_auto_tl_in_a_bits_data; // @[LazyModuleImp.scala:138:7] wire [28:0] coupler_from_port_named_custom_boot_pin_auto_tl_in_a_bits_address; // @[LazyModuleImp.scala:138:7] wire coupler_to_bus_named_pbus_widget_auto_anon_out_d_valid; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_pbus_widget_auto_anon_out_d_ready; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_pbus_widget_auto_anon_out_d_bits_corrupt; // @[WidthWidget.scala:27:9] wire [63:0] coupler_to_bus_named_pbus_widget_auto_anon_out_d_bits_data; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_pbus_widget_auto_anon_out_d_bits_denied; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_pbus_widget_auto_anon_out_d_bits_sink; // @[WidthWidget.scala:27:9] wire [8:0] coupler_to_bus_named_pbus_widget_auto_anon_out_d_bits_source; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_pbus_widget_auto_anon_out_d_bits_size; // @[WidthWidget.scala:27:9] wire [1:0] coupler_to_bus_named_pbus_widget_auto_anon_out_d_bits_param; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_pbus_widget_auto_anon_out_d_bits_opcode; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_pbus_widget_auto_anon_out_a_valid; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_pbus_widget_auto_anon_out_a_ready; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_pbus_widget_auto_anon_out_a_bits_corrupt; // @[WidthWidget.scala:27:9] wire [63:0] coupler_to_bus_named_pbus_widget_auto_anon_out_a_bits_data; // @[WidthWidget.scala:27:9] wire [7:0] coupler_to_bus_named_pbus_widget_auto_anon_out_a_bits_mask; // @[WidthWidget.scala:27:9] wire [28:0] coupler_to_bus_named_pbus_widget_auto_anon_out_a_bits_address; // @[WidthWidget.scala:27:9] wire [8:0] coupler_to_bus_named_pbus_widget_auto_anon_out_a_bits_source; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_pbus_widget_auto_anon_out_a_bits_size; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_pbus_widget_auto_anon_out_a_bits_param; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_pbus_widget_auto_anon_out_a_bits_opcode; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_pbus_auto_widget_anon_in_d_ready; // @[LazyModuleImp.scala:138:7] wire coupler_to_bus_named_pbus_auto_widget_anon_in_a_valid; // @[LazyModuleImp.scala:138:7] wire coupler_to_bus_named_pbus_auto_widget_anon_in_a_bits_corrupt; // @[LazyModuleImp.scala:138:7] wire [63:0] coupler_to_bus_named_pbus_auto_widget_anon_in_a_bits_data; // @[LazyModuleImp.scala:138:7] wire [7:0] coupler_to_bus_named_pbus_auto_widget_anon_in_a_bits_mask; // @[LazyModuleImp.scala:138:7] wire [28:0] coupler_to_bus_named_pbus_auto_widget_anon_in_a_bits_address; // @[LazyModuleImp.scala:138:7] wire [8:0] coupler_to_bus_named_pbus_auto_widget_anon_in_a_bits_source; // @[LazyModuleImp.scala:138:7] wire [2:0] coupler_to_bus_named_pbus_auto_widget_anon_in_a_bits_size; // @[LazyModuleImp.scala:138:7] wire [2:0] coupler_to_bus_named_pbus_auto_widget_anon_in_a_bits_param; // @[LazyModuleImp.scala:138:7] wire [2:0] coupler_to_bus_named_pbus_auto_widget_anon_in_a_bits_opcode; // @[LazyModuleImp.scala:138:7] wire buffer_1_auto_out_d_valid; // @[Buffer.scala:40:9] wire buffer_1_auto_out_d_bits_corrupt; // @[Buffer.scala:40:9] wire [63:0] buffer_1_auto_out_d_bits_data; // @[Buffer.scala:40:9] wire buffer_1_auto_out_d_bits_denied; // @[Buffer.scala:40:9] wire buffer_1_auto_out_d_bits_sink; // @[Buffer.scala:40:9] wire [7:0] buffer_1_auto_out_d_bits_source; // @[Buffer.scala:40:9] wire [3:0] buffer_1_auto_out_d_bits_size; // @[Buffer.scala:40:9] wire [1:0] buffer_1_auto_out_d_bits_param; // @[Buffer.scala:40:9] wire [2:0] buffer_1_auto_out_d_bits_opcode; // @[Buffer.scala:40:9] wire buffer_1_auto_out_a_ready; // @[Buffer.scala:40:9] wire buffer_1_auto_in_d_valid; // @[Buffer.scala:40:9] wire buffer_1_auto_in_d_ready; // @[Buffer.scala:40:9] wire buffer_1_auto_in_d_bits_corrupt; // @[Buffer.scala:40:9] wire [63:0] buffer_1_auto_in_d_bits_data; // @[Buffer.scala:40:9] wire buffer_1_auto_in_d_bits_denied; // @[Buffer.scala:40:9] wire buffer_1_auto_in_d_bits_sink; // @[Buffer.scala:40:9] wire [7:0] buffer_1_auto_in_d_bits_source; // @[Buffer.scala:40:9] wire [3:0] buffer_1_auto_in_d_bits_size; // @[Buffer.scala:40:9] wire [1:0] buffer_1_auto_in_d_bits_param; // @[Buffer.scala:40:9] wire [2:0] buffer_1_auto_in_d_bits_opcode; // @[Buffer.scala:40:9] wire buffer_1_auto_in_a_valid; // @[Buffer.scala:40:9] wire buffer_1_auto_in_a_ready; // @[Buffer.scala:40:9] wire buffer_1_auto_in_a_bits_corrupt; // @[Buffer.scala:40:9] wire [63:0] buffer_1_auto_in_a_bits_data; // @[Buffer.scala:40:9] wire [7:0] buffer_1_auto_in_a_bits_mask; // @[Buffer.scala:40:9] wire [28:0] buffer_1_auto_in_a_bits_address; // @[Buffer.scala:40:9] wire [7:0] buffer_1_auto_in_a_bits_source; // @[Buffer.scala:40:9] wire [3:0] buffer_1_auto_in_a_bits_size; // @[Buffer.scala:40:9] wire [2:0] buffer_1_auto_in_a_bits_param; // @[Buffer.scala:40:9] wire [2:0] buffer_1_auto_in_a_bits_opcode; // @[Buffer.scala:40:9] wire fixer_auto_anon_out_d_valid; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_out_d_bits_corrupt; // @[FIFOFixer.scala:50:9] wire [63:0] fixer_auto_anon_out_d_bits_data; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_out_d_bits_denied; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_out_d_bits_sink; // @[FIFOFixer.scala:50:9] wire [8:0] fixer_auto_anon_out_d_bits_source; // @[FIFOFixer.scala:50:9] wire [3:0] fixer_auto_anon_out_d_bits_size; // @[FIFOFixer.scala:50:9] wire [1:0] fixer_auto_anon_out_d_bits_param; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_auto_anon_out_d_bits_opcode; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_out_a_ready; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_in_d_ready; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_in_a_valid; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_in_a_bits_corrupt; // @[FIFOFixer.scala:50:9] wire [63:0] fixer_auto_anon_in_a_bits_data; // @[FIFOFixer.scala:50:9] wire [7:0] fixer_auto_anon_in_a_bits_mask; // @[FIFOFixer.scala:50:9] wire [28:0] fixer_auto_anon_in_a_bits_address; // @[FIFOFixer.scala:50:9] wire [8:0] fixer_auto_anon_in_a_bits_source; // @[FIFOFixer.scala:50:9] wire [3:0] fixer_auto_anon_in_a_bits_size; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_auto_anon_in_a_bits_param; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_auto_anon_in_a_bits_opcode; // @[FIFOFixer.scala:50:9] wire cbus_clock_groups_auto_out_member_cbus_0_reset; // @[ClockGroup.scala:53:9] wire cbus_clock_groups_auto_out_member_cbus_0_clock; // @[ClockGroup.scala:53:9] wire _coupler_to_prci_ctrl_auto_tl_in_a_ready; // @[LazyScope.scala:98:27] wire _coupler_to_prci_ctrl_auto_tl_in_d_valid; // @[LazyScope.scala:98:27] wire [2:0] _coupler_to_prci_ctrl_auto_tl_in_d_bits_opcode; // @[LazyScope.scala:98:27] wire [1:0] _coupler_to_prci_ctrl_auto_tl_in_d_bits_param; // @[LazyScope.scala:98:27] wire [2:0] _coupler_to_prci_ctrl_auto_tl_in_d_bits_size; // @[LazyScope.scala:98:27] wire [8:0] _coupler_to_prci_ctrl_auto_tl_in_d_bits_source; // @[LazyScope.scala:98:27] wire _coupler_to_prci_ctrl_auto_tl_in_d_bits_sink; // @[LazyScope.scala:98:27] wire _coupler_to_prci_ctrl_auto_tl_in_d_bits_denied; // @[LazyScope.scala:98:27] wire [63:0] _coupler_to_prci_ctrl_auto_tl_in_d_bits_data; // @[LazyScope.scala:98:27] wire _coupler_to_prci_ctrl_auto_tl_in_d_bits_corrupt; // @[LazyScope.scala:98:27] wire _coupler_to_bootrom_auto_tl_in_a_ready; // @[LazyScope.scala:98:27] wire _coupler_to_bootrom_auto_tl_in_d_valid; // @[LazyScope.scala:98:27] wire [2:0] _coupler_to_bootrom_auto_tl_in_d_bits_size; // @[LazyScope.scala:98:27] wire [8:0] _coupler_to_bootrom_auto_tl_in_d_bits_source; // @[LazyScope.scala:98:27] wire [63:0] _coupler_to_bootrom_auto_tl_in_d_bits_data; // @[LazyScope.scala:98:27] wire _coupler_to_debug_auto_tl_in_a_ready; // @[LazyScope.scala:98:27] wire _coupler_to_debug_auto_tl_in_d_valid; // @[LazyScope.scala:98:27] wire [2:0] _coupler_to_debug_auto_tl_in_d_bits_opcode; // @[LazyScope.scala:98:27] wire [2:0] _coupler_to_debug_auto_tl_in_d_bits_size; // @[LazyScope.scala:98:27] wire [8:0] _coupler_to_debug_auto_tl_in_d_bits_source; // @[LazyScope.scala:98:27] wire [63:0] _coupler_to_debug_auto_tl_in_d_bits_data; // @[LazyScope.scala:98:27] wire _coupler_to_plic_auto_tl_in_a_ready; // @[LazyScope.scala:98:27] wire _coupler_to_plic_auto_tl_in_d_valid; // @[LazyScope.scala:98:27] wire [2:0] _coupler_to_plic_auto_tl_in_d_bits_opcode; // @[LazyScope.scala:98:27] wire [2:0] _coupler_to_plic_auto_tl_in_d_bits_size; // @[LazyScope.scala:98:27] wire [8:0] _coupler_to_plic_auto_tl_in_d_bits_source; // @[LazyScope.scala:98:27] wire [63:0] _coupler_to_plic_auto_tl_in_d_bits_data; // @[LazyScope.scala:98:27] wire _coupler_to_clint_auto_tl_in_a_ready; // @[LazyScope.scala:98:27] wire _coupler_to_clint_auto_tl_in_d_valid; // @[LazyScope.scala:98:27] wire [2:0] _coupler_to_clint_auto_tl_in_d_bits_opcode; // @[LazyScope.scala:98:27] wire [2:0] _coupler_to_clint_auto_tl_in_d_bits_size; // @[LazyScope.scala:98:27] wire [8:0] _coupler_to_clint_auto_tl_in_d_bits_source; // @[LazyScope.scala:98:27] wire [63:0] _coupler_to_clint_auto_tl_in_d_bits_data; // @[LazyScope.scala:98:27] wire _coupler_to_l2_ctrl_auto_tl_in_a_ready; // @[LazyScope.scala:98:27] wire _coupler_to_l2_ctrl_auto_tl_in_d_valid; // @[LazyScope.scala:98:27] wire [2:0] _coupler_to_l2_ctrl_auto_tl_in_d_bits_opcode; // @[LazyScope.scala:98:27] wire [1:0] _coupler_to_l2_ctrl_auto_tl_in_d_bits_param; // @[LazyScope.scala:98:27] wire [2:0] _coupler_to_l2_ctrl_auto_tl_in_d_bits_size; // @[LazyScope.scala:98:27] wire [8:0] _coupler_to_l2_ctrl_auto_tl_in_d_bits_source; // @[LazyScope.scala:98:27] wire _coupler_to_l2_ctrl_auto_tl_in_d_bits_sink; // @[LazyScope.scala:98:27] wire _coupler_to_l2_ctrl_auto_tl_in_d_bits_denied; // @[LazyScope.scala:98:27] wire [63:0] _coupler_to_l2_ctrl_auto_tl_in_d_bits_data; // @[LazyScope.scala:98:27] wire _coupler_to_l2_ctrl_auto_tl_in_d_bits_corrupt; // @[LazyScope.scala:98:27] wire _wrapped_error_device_auto_buffer_in_a_ready; // @[LazyScope.scala:98:27] wire _wrapped_error_device_auto_buffer_in_d_valid; // @[LazyScope.scala:98:27] wire [2:0] _wrapped_error_device_auto_buffer_in_d_bits_opcode; // @[LazyScope.scala:98:27] wire [1:0] _wrapped_error_device_auto_buffer_in_d_bits_param; // @[LazyScope.scala:98:27] wire [3:0] _wrapped_error_device_auto_buffer_in_d_bits_size; // @[LazyScope.scala:98:27] wire [8:0] _wrapped_error_device_auto_buffer_in_d_bits_source; // @[LazyScope.scala:98:27] wire _wrapped_error_device_auto_buffer_in_d_bits_sink; // @[LazyScope.scala:98:27] wire _wrapped_error_device_auto_buffer_in_d_bits_denied; // @[LazyScope.scala:98:27] wire [63:0] _wrapped_error_device_auto_buffer_in_d_bits_data; // @[LazyScope.scala:98:27] wire _wrapped_error_device_auto_buffer_in_d_bits_corrupt; // @[LazyScope.scala:98:27] wire _atomics_auto_in_a_ready; // @[AtomicAutomata.scala:289:29] wire _atomics_auto_in_d_valid; // @[AtomicAutomata.scala:289:29] wire [2:0] _atomics_auto_in_d_bits_opcode; // @[AtomicAutomata.scala:289:29] wire [1:0] _atomics_auto_in_d_bits_param; // @[AtomicAutomata.scala:289:29] wire [3:0] _atomics_auto_in_d_bits_size; // @[AtomicAutomata.scala:289:29] wire [8:0] _atomics_auto_in_d_bits_source; // @[AtomicAutomata.scala:289:29] wire _atomics_auto_in_d_bits_sink; // @[AtomicAutomata.scala:289:29] wire _atomics_auto_in_d_bits_denied; // @[AtomicAutomata.scala:289:29] wire [63:0] _atomics_auto_in_d_bits_data; // @[AtomicAutomata.scala:289:29] wire _atomics_auto_in_d_bits_corrupt; // @[AtomicAutomata.scala:289:29] wire _atomics_auto_out_a_valid; // @[AtomicAutomata.scala:289:29] wire [2:0] _atomics_auto_out_a_bits_opcode; // @[AtomicAutomata.scala:289:29] wire [2:0] _atomics_auto_out_a_bits_param; // @[AtomicAutomata.scala:289:29] wire [3:0] _atomics_auto_out_a_bits_size; // @[AtomicAutomata.scala:289:29] wire [8:0] _atomics_auto_out_a_bits_source; // @[AtomicAutomata.scala:289:29] wire [28:0] _atomics_auto_out_a_bits_address; // @[AtomicAutomata.scala:289:29] wire [7:0] _atomics_auto_out_a_bits_mask; // @[AtomicAutomata.scala:289:29] wire [63:0] _atomics_auto_out_a_bits_data; // @[AtomicAutomata.scala:289:29] wire _atomics_auto_out_a_bits_corrupt; // @[AtomicAutomata.scala:289:29] wire _atomics_auto_out_d_ready; // @[AtomicAutomata.scala:289:29] wire _buffer_auto_in_a_ready; // @[Buffer.scala:75:28] wire _buffer_auto_in_d_valid; // @[Buffer.scala:75:28] wire [2:0] _buffer_auto_in_d_bits_opcode; // @[Buffer.scala:75:28] wire [1:0] _buffer_auto_in_d_bits_param; // @[Buffer.scala:75:28] wire [3:0] _buffer_auto_in_d_bits_size; // @[Buffer.scala:75:28] wire [8:0] _buffer_auto_in_d_bits_source; // @[Buffer.scala:75:28] wire _buffer_auto_in_d_bits_sink; // @[Buffer.scala:75:28] wire _buffer_auto_in_d_bits_denied; // @[Buffer.scala:75:28] wire [63:0] _buffer_auto_in_d_bits_data; // @[Buffer.scala:75:28] wire _buffer_auto_in_d_bits_corrupt; // @[Buffer.scala:75:28] wire _out_xbar_auto_anon_out_7_a_valid; // @[PeripheryBus.scala:57:30] wire [2:0] _out_xbar_auto_anon_out_7_a_bits_opcode; // @[PeripheryBus.scala:57:30] wire [2:0] _out_xbar_auto_anon_out_7_a_bits_param; // @[PeripheryBus.scala:57:30] wire [2:0] _out_xbar_auto_anon_out_7_a_bits_size; // @[PeripheryBus.scala:57:30] wire [8:0] _out_xbar_auto_anon_out_7_a_bits_source; // @[PeripheryBus.scala:57:30] wire [20:0] _out_xbar_auto_anon_out_7_a_bits_address; // @[PeripheryBus.scala:57:30] wire [7:0] _out_xbar_auto_anon_out_7_a_bits_mask; // @[PeripheryBus.scala:57:30] wire [63:0] _out_xbar_auto_anon_out_7_a_bits_data; // @[PeripheryBus.scala:57:30] wire _out_xbar_auto_anon_out_7_a_bits_corrupt; // @[PeripheryBus.scala:57:30] wire _out_xbar_auto_anon_out_7_d_ready; // @[PeripheryBus.scala:57:30] wire _out_xbar_auto_anon_out_6_a_valid; // @[PeripheryBus.scala:57:30] wire [2:0] _out_xbar_auto_anon_out_6_a_bits_opcode; // @[PeripheryBus.scala:57:30] wire [2:0] _out_xbar_auto_anon_out_6_a_bits_param; // @[PeripheryBus.scala:57:30] wire [2:0] _out_xbar_auto_anon_out_6_a_bits_size; // @[PeripheryBus.scala:57:30] wire [8:0] _out_xbar_auto_anon_out_6_a_bits_source; // @[PeripheryBus.scala:57:30] wire [16:0] _out_xbar_auto_anon_out_6_a_bits_address; // @[PeripheryBus.scala:57:30] wire [7:0] _out_xbar_auto_anon_out_6_a_bits_mask; // @[PeripheryBus.scala:57:30] wire [63:0] _out_xbar_auto_anon_out_6_a_bits_data; // @[PeripheryBus.scala:57:30] wire _out_xbar_auto_anon_out_6_a_bits_corrupt; // @[PeripheryBus.scala:57:30] wire _out_xbar_auto_anon_out_6_d_ready; // @[PeripheryBus.scala:57:30] wire _out_xbar_auto_anon_out_5_a_valid; // @[PeripheryBus.scala:57:30] wire [2:0] _out_xbar_auto_anon_out_5_a_bits_opcode; // @[PeripheryBus.scala:57:30] wire [2:0] _out_xbar_auto_anon_out_5_a_bits_param; // @[PeripheryBus.scala:57:30] wire [2:0] _out_xbar_auto_anon_out_5_a_bits_size; // @[PeripheryBus.scala:57:30] wire [8:0] _out_xbar_auto_anon_out_5_a_bits_source; // @[PeripheryBus.scala:57:30] wire [11:0] _out_xbar_auto_anon_out_5_a_bits_address; // @[PeripheryBus.scala:57:30] wire [7:0] _out_xbar_auto_anon_out_5_a_bits_mask; // @[PeripheryBus.scala:57:30] wire [63:0] _out_xbar_auto_anon_out_5_a_bits_data; // @[PeripheryBus.scala:57:30] wire _out_xbar_auto_anon_out_5_a_bits_corrupt; // @[PeripheryBus.scala:57:30] wire _out_xbar_auto_anon_out_5_d_ready; // @[PeripheryBus.scala:57:30] wire _out_xbar_auto_anon_out_4_a_valid; // @[PeripheryBus.scala:57:30] wire [2:0] _out_xbar_auto_anon_out_4_a_bits_opcode; // @[PeripheryBus.scala:57:30] wire [2:0] _out_xbar_auto_anon_out_4_a_bits_param; // @[PeripheryBus.scala:57:30] wire [2:0] _out_xbar_auto_anon_out_4_a_bits_size; // @[PeripheryBus.scala:57:30] wire [8:0] _out_xbar_auto_anon_out_4_a_bits_source; // @[PeripheryBus.scala:57:30] wire [27:0] _out_xbar_auto_anon_out_4_a_bits_address; // @[PeripheryBus.scala:57:30] wire [7:0] _out_xbar_auto_anon_out_4_a_bits_mask; // @[PeripheryBus.scala:57:30] wire [63:0] _out_xbar_auto_anon_out_4_a_bits_data; // @[PeripheryBus.scala:57:30] wire _out_xbar_auto_anon_out_4_a_bits_corrupt; // @[PeripheryBus.scala:57:30] wire _out_xbar_auto_anon_out_4_d_ready; // @[PeripheryBus.scala:57:30] wire _out_xbar_auto_anon_out_3_a_valid; // @[PeripheryBus.scala:57:30] wire [2:0] _out_xbar_auto_anon_out_3_a_bits_opcode; // @[PeripheryBus.scala:57:30] wire [2:0] _out_xbar_auto_anon_out_3_a_bits_param; // @[PeripheryBus.scala:57:30] wire [2:0] _out_xbar_auto_anon_out_3_a_bits_size; // @[PeripheryBus.scala:57:30] wire [8:0] _out_xbar_auto_anon_out_3_a_bits_source; // @[PeripheryBus.scala:57:30] wire [25:0] _out_xbar_auto_anon_out_3_a_bits_address; // @[PeripheryBus.scala:57:30] wire [7:0] _out_xbar_auto_anon_out_3_a_bits_mask; // @[PeripheryBus.scala:57:30] wire [63:0] _out_xbar_auto_anon_out_3_a_bits_data; // @[PeripheryBus.scala:57:30] wire _out_xbar_auto_anon_out_3_a_bits_corrupt; // @[PeripheryBus.scala:57:30] wire _out_xbar_auto_anon_out_3_d_ready; // @[PeripheryBus.scala:57:30] wire _out_xbar_auto_anon_out_1_a_valid; // @[PeripheryBus.scala:57:30] wire [2:0] _out_xbar_auto_anon_out_1_a_bits_opcode; // @[PeripheryBus.scala:57:30] wire [2:0] _out_xbar_auto_anon_out_1_a_bits_param; // @[PeripheryBus.scala:57:30] wire [2:0] _out_xbar_auto_anon_out_1_a_bits_size; // @[PeripheryBus.scala:57:30] wire [8:0] _out_xbar_auto_anon_out_1_a_bits_source; // @[PeripheryBus.scala:57:30] wire [25:0] _out_xbar_auto_anon_out_1_a_bits_address; // @[PeripheryBus.scala:57:30] wire [7:0] _out_xbar_auto_anon_out_1_a_bits_mask; // @[PeripheryBus.scala:57:30] wire [63:0] _out_xbar_auto_anon_out_1_a_bits_data; // @[PeripheryBus.scala:57:30] wire _out_xbar_auto_anon_out_1_a_bits_corrupt; // @[PeripheryBus.scala:57:30] wire _out_xbar_auto_anon_out_1_d_ready; // @[PeripheryBus.scala:57:30] wire _out_xbar_auto_anon_out_0_a_valid; // @[PeripheryBus.scala:57:30] wire [2:0] _out_xbar_auto_anon_out_0_a_bits_opcode; // @[PeripheryBus.scala:57:30] wire [2:0] _out_xbar_auto_anon_out_0_a_bits_param; // @[PeripheryBus.scala:57:30] wire [3:0] _out_xbar_auto_anon_out_0_a_bits_size; // @[PeripheryBus.scala:57:30] wire [8:0] _out_xbar_auto_anon_out_0_a_bits_source; // @[PeripheryBus.scala:57:30] wire [13:0] _out_xbar_auto_anon_out_0_a_bits_address; // @[PeripheryBus.scala:57:30] wire [7:0] _out_xbar_auto_anon_out_0_a_bits_mask; // @[PeripheryBus.scala:57:30] wire [63:0] _out_xbar_auto_anon_out_0_a_bits_data; // @[PeripheryBus.scala:57:30] wire _out_xbar_auto_anon_out_0_a_bits_corrupt; // @[PeripheryBus.scala:57:30] wire _out_xbar_auto_anon_out_0_d_ready; // @[PeripheryBus.scala:57:30] wire _in_xbar_auto_anon_out_a_valid; // @[PeripheryBus.scala:56:29] wire [2:0] _in_xbar_auto_anon_out_a_bits_opcode; // @[PeripheryBus.scala:56:29] wire [2:0] _in_xbar_auto_anon_out_a_bits_param; // @[PeripheryBus.scala:56:29] wire [3:0] _in_xbar_auto_anon_out_a_bits_size; // @[PeripheryBus.scala:56:29] wire [8:0] _in_xbar_auto_anon_out_a_bits_source; // @[PeripheryBus.scala:56:29] wire [28:0] _in_xbar_auto_anon_out_a_bits_address; // @[PeripheryBus.scala:56:29] wire [7:0] _in_xbar_auto_anon_out_a_bits_mask; // @[PeripheryBus.scala:56:29] wire [63:0] _in_xbar_auto_anon_out_a_bits_data; // @[PeripheryBus.scala:56:29] wire _in_xbar_auto_anon_out_a_bits_corrupt; // @[PeripheryBus.scala:56:29] wire _in_xbar_auto_anon_out_d_ready; // @[PeripheryBus.scala:56:29] wire auto_coupler_to_prci_ctrl_fixer_anon_out_a_ready_0 = auto_coupler_to_prci_ctrl_fixer_anon_out_a_ready; // @[ClockDomain.scala:14:9] wire auto_coupler_to_prci_ctrl_fixer_anon_out_d_valid_0 = auto_coupler_to_prci_ctrl_fixer_anon_out_d_valid; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_to_prci_ctrl_fixer_anon_out_d_bits_opcode_0 = auto_coupler_to_prci_ctrl_fixer_anon_out_d_bits_opcode; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_to_prci_ctrl_fixer_anon_out_d_bits_size_0 = auto_coupler_to_prci_ctrl_fixer_anon_out_d_bits_size; // @[ClockDomain.scala:14:9] wire [8:0] auto_coupler_to_prci_ctrl_fixer_anon_out_d_bits_source_0 = auto_coupler_to_prci_ctrl_fixer_anon_out_d_bits_source; // @[ClockDomain.scala:14:9] wire [63:0] auto_coupler_to_prci_ctrl_fixer_anon_out_d_bits_data_0 = auto_coupler_to_prci_ctrl_fixer_anon_out_d_bits_data; // @[ClockDomain.scala:14:9] wire auto_coupler_to_bootrom_fragmenter_anon_out_a_ready_0 = auto_coupler_to_bootrom_fragmenter_anon_out_a_ready; // @[ClockDomain.scala:14:9] wire auto_coupler_to_bootrom_fragmenter_anon_out_d_valid_0 = auto_coupler_to_bootrom_fragmenter_anon_out_d_valid; // @[ClockDomain.scala:14:9] wire [1:0] auto_coupler_to_bootrom_fragmenter_anon_out_d_bits_size_0 = auto_coupler_to_bootrom_fragmenter_anon_out_d_bits_size; // @[ClockDomain.scala:14:9] wire [12:0] auto_coupler_to_bootrom_fragmenter_anon_out_d_bits_source_0 = auto_coupler_to_bootrom_fragmenter_anon_out_d_bits_source; // @[ClockDomain.scala:14:9] wire [63:0] auto_coupler_to_bootrom_fragmenter_anon_out_d_bits_data_0 = auto_coupler_to_bootrom_fragmenter_anon_out_d_bits_data; // @[ClockDomain.scala:14:9] wire auto_coupler_to_debug_fragmenter_anon_out_a_ready_0 = auto_coupler_to_debug_fragmenter_anon_out_a_ready; // @[ClockDomain.scala:14:9] wire auto_coupler_to_debug_fragmenter_anon_out_d_valid_0 = auto_coupler_to_debug_fragmenter_anon_out_d_valid; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_to_debug_fragmenter_anon_out_d_bits_opcode_0 = auto_coupler_to_debug_fragmenter_anon_out_d_bits_opcode; // @[ClockDomain.scala:14:9] wire [1:0] auto_coupler_to_debug_fragmenter_anon_out_d_bits_size_0 = auto_coupler_to_debug_fragmenter_anon_out_d_bits_size; // @[ClockDomain.scala:14:9] wire [12:0] auto_coupler_to_debug_fragmenter_anon_out_d_bits_source_0 = auto_coupler_to_debug_fragmenter_anon_out_d_bits_source; // @[ClockDomain.scala:14:9] wire [63:0] auto_coupler_to_debug_fragmenter_anon_out_d_bits_data_0 = auto_coupler_to_debug_fragmenter_anon_out_d_bits_data; // @[ClockDomain.scala:14:9] wire auto_coupler_to_plic_fragmenter_anon_out_a_ready_0 = auto_coupler_to_plic_fragmenter_anon_out_a_ready; // @[ClockDomain.scala:14:9] wire auto_coupler_to_plic_fragmenter_anon_out_d_valid_0 = auto_coupler_to_plic_fragmenter_anon_out_d_valid; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_to_plic_fragmenter_anon_out_d_bits_opcode_0 = auto_coupler_to_plic_fragmenter_anon_out_d_bits_opcode; // @[ClockDomain.scala:14:9] wire [1:0] auto_coupler_to_plic_fragmenter_anon_out_d_bits_size_0 = auto_coupler_to_plic_fragmenter_anon_out_d_bits_size; // @[ClockDomain.scala:14:9] wire [12:0] auto_coupler_to_plic_fragmenter_anon_out_d_bits_source_0 = auto_coupler_to_plic_fragmenter_anon_out_d_bits_source; // @[ClockDomain.scala:14:9] wire [63:0] auto_coupler_to_plic_fragmenter_anon_out_d_bits_data_0 = auto_coupler_to_plic_fragmenter_anon_out_d_bits_data; // @[ClockDomain.scala:14:9] wire auto_coupler_to_clint_fragmenter_anon_out_a_ready_0 = auto_coupler_to_clint_fragmenter_anon_out_a_ready; // @[ClockDomain.scala:14:9] wire auto_coupler_to_clint_fragmenter_anon_out_d_valid_0 = auto_coupler_to_clint_fragmenter_anon_out_d_valid; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_to_clint_fragmenter_anon_out_d_bits_opcode_0 = auto_coupler_to_clint_fragmenter_anon_out_d_bits_opcode; // @[ClockDomain.scala:14:9] wire [1:0] auto_coupler_to_clint_fragmenter_anon_out_d_bits_size_0 = auto_coupler_to_clint_fragmenter_anon_out_d_bits_size; // @[ClockDomain.scala:14:9] wire [12:0] auto_coupler_to_clint_fragmenter_anon_out_d_bits_source_0 = auto_coupler_to_clint_fragmenter_anon_out_d_bits_source; // @[ClockDomain.scala:14:9] wire [63:0] auto_coupler_to_clint_fragmenter_anon_out_d_bits_data_0 = auto_coupler_to_clint_fragmenter_anon_out_d_bits_data; // @[ClockDomain.scala:14:9] wire auto_coupler_to_bus_named_pbus_bus_xing_out_a_ready_0 = auto_coupler_to_bus_named_pbus_bus_xing_out_a_ready; // @[ClockDomain.scala:14:9] wire auto_coupler_to_bus_named_pbus_bus_xing_out_d_valid_0 = auto_coupler_to_bus_named_pbus_bus_xing_out_d_valid; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_to_bus_named_pbus_bus_xing_out_d_bits_opcode_0 = auto_coupler_to_bus_named_pbus_bus_xing_out_d_bits_opcode; // @[ClockDomain.scala:14:9] wire [1:0] auto_coupler_to_bus_named_pbus_bus_xing_out_d_bits_param_0 = auto_coupler_to_bus_named_pbus_bus_xing_out_d_bits_param; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_to_bus_named_pbus_bus_xing_out_d_bits_size_0 = auto_coupler_to_bus_named_pbus_bus_xing_out_d_bits_size; // @[ClockDomain.scala:14:9] wire [8:0] auto_coupler_to_bus_named_pbus_bus_xing_out_d_bits_source_0 = auto_coupler_to_bus_named_pbus_bus_xing_out_d_bits_source; // @[ClockDomain.scala:14:9] wire auto_coupler_to_bus_named_pbus_bus_xing_out_d_bits_sink_0 = auto_coupler_to_bus_named_pbus_bus_xing_out_d_bits_sink; // @[ClockDomain.scala:14:9] wire auto_coupler_to_bus_named_pbus_bus_xing_out_d_bits_denied_0 = auto_coupler_to_bus_named_pbus_bus_xing_out_d_bits_denied; // @[ClockDomain.scala:14:9] wire [63:0] auto_coupler_to_bus_named_pbus_bus_xing_out_d_bits_data_0 = auto_coupler_to_bus_named_pbus_bus_xing_out_d_bits_data; // @[ClockDomain.scala:14:9] wire auto_coupler_to_bus_named_pbus_bus_xing_out_d_bits_corrupt_0 = auto_coupler_to_bus_named_pbus_bus_xing_out_d_bits_corrupt; // @[ClockDomain.scala:14:9] wire auto_coupler_to_l2_ctrl_buffer_out_a_ready_0 = auto_coupler_to_l2_ctrl_buffer_out_a_ready; // @[ClockDomain.scala:14:9] wire auto_coupler_to_l2_ctrl_buffer_out_d_valid_0 = auto_coupler_to_l2_ctrl_buffer_out_d_valid; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_to_l2_ctrl_buffer_out_d_bits_opcode_0 = auto_coupler_to_l2_ctrl_buffer_out_d_bits_opcode; // @[ClockDomain.scala:14:9] wire [1:0] auto_coupler_to_l2_ctrl_buffer_out_d_bits_size_0 = auto_coupler_to_l2_ctrl_buffer_out_d_bits_size; // @[ClockDomain.scala:14:9] wire [12:0] auto_coupler_to_l2_ctrl_buffer_out_d_bits_source_0 = auto_coupler_to_l2_ctrl_buffer_out_d_bits_source; // @[ClockDomain.scala:14:9] wire [63:0] auto_coupler_to_l2_ctrl_buffer_out_d_bits_data_0 = auto_coupler_to_l2_ctrl_buffer_out_d_bits_data; // @[ClockDomain.scala:14:9] wire auto_cbus_clock_groups_in_member_cbus_0_clock_0 = auto_cbus_clock_groups_in_member_cbus_0_clock; // @[ClockDomain.scala:14:9] wire auto_cbus_clock_groups_in_member_cbus_0_reset_0 = auto_cbus_clock_groups_in_member_cbus_0_reset; // @[ClockDomain.scala:14:9] wire auto_bus_xing_in_a_valid_0 = auto_bus_xing_in_a_valid; // @[ClockDomain.scala:14:9] wire [2:0] auto_bus_xing_in_a_bits_opcode_0 = auto_bus_xing_in_a_bits_opcode; // @[ClockDomain.scala:14:9] wire [2:0] auto_bus_xing_in_a_bits_param_0 = auto_bus_xing_in_a_bits_param; // @[ClockDomain.scala:14:9] wire [3:0] auto_bus_xing_in_a_bits_size_0 = auto_bus_xing_in_a_bits_size; // @[ClockDomain.scala:14:9] wire [7:0] auto_bus_xing_in_a_bits_source_0 = auto_bus_xing_in_a_bits_source; // @[ClockDomain.scala:14:9] wire [28:0] auto_bus_xing_in_a_bits_address_0 = auto_bus_xing_in_a_bits_address; // @[ClockDomain.scala:14:9] wire [7:0] auto_bus_xing_in_a_bits_mask_0 = auto_bus_xing_in_a_bits_mask; // @[ClockDomain.scala:14:9] wire [63:0] auto_bus_xing_in_a_bits_data_0 = auto_bus_xing_in_a_bits_data; // @[ClockDomain.scala:14:9] wire auto_bus_xing_in_a_bits_corrupt_0 = auto_bus_xing_in_a_bits_corrupt; // @[ClockDomain.scala:14:9] wire auto_bus_xing_in_d_ready_0 = auto_bus_xing_in_d_ready; // @[ClockDomain.scala:14:9] wire [1:0] auto_coupler_to_prci_ctrl_fixer_anon_out_d_bits_param = 2'h0; // @[ClockDomain.scala:14:9] wire [1:0] auto_coupler_to_bootrom_fragmenter_anon_out_d_bits_param = 2'h0; // @[ClockDomain.scala:14:9] wire [1:0] auto_coupler_to_debug_fragmenter_anon_out_d_bits_param = 2'h0; // @[ClockDomain.scala:14:9] wire [1:0] auto_coupler_to_plic_fragmenter_anon_out_d_bits_param = 2'h0; // @[ClockDomain.scala:14:9] wire [1:0] auto_coupler_to_clint_fragmenter_anon_out_d_bits_param = 2'h0; // @[ClockDomain.scala:14:9] wire [1:0] auto_coupler_to_l2_ctrl_buffer_out_d_bits_param = 2'h0; // @[ClockDomain.scala:14:9] wire [1:0] nodeOut_a_bits_a_mask_hi_lo = 2'h0; // @[Misc.scala:222:10] wire [1:0] nodeOut_a_bits_a_mask_hi_hi = 2'h0; // @[Misc.scala:222:10] wire [1:0] nodeOut_a_bits_a_mask_hi_lo_1 = 2'h0; // @[Misc.scala:222:10] wire [1:0] nodeOut_a_bits_a_mask_hi_hi_1 = 2'h0; // @[Misc.scala:222:10] wire auto_coupler_to_prci_ctrl_fixer_anon_out_d_bits_sink = 1'h0; // @[ClockDomain.scala:14:9] wire auto_coupler_to_prci_ctrl_fixer_anon_out_d_bits_denied = 1'h0; // @[ClockDomain.scala:14:9] wire auto_coupler_to_prci_ctrl_fixer_anon_out_d_bits_corrupt = 1'h0; // @[ClockDomain.scala:14:9] wire auto_coupler_to_bootrom_fragmenter_anon_out_d_bits_sink = 1'h0; // @[ClockDomain.scala:14:9] wire auto_coupler_to_bootrom_fragmenter_anon_out_d_bits_denied = 1'h0; // @[ClockDomain.scala:14:9] wire auto_coupler_to_bootrom_fragmenter_anon_out_d_bits_corrupt = 1'h0; // @[ClockDomain.scala:14:9] wire auto_coupler_to_debug_fragmenter_anon_out_d_bits_sink = 1'h0; // @[ClockDomain.scala:14:9] wire auto_coupler_to_debug_fragmenter_anon_out_d_bits_denied = 1'h0; // @[ClockDomain.scala:14:9] wire auto_coupler_to_debug_fragmenter_anon_out_d_bits_corrupt = 1'h0; // @[ClockDomain.scala:14:9] wire auto_coupler_to_plic_fragmenter_anon_out_d_bits_sink = 1'h0; // @[ClockDomain.scala:14:9] wire auto_coupler_to_plic_fragmenter_anon_out_d_bits_denied = 1'h0; // @[ClockDomain.scala:14:9] wire auto_coupler_to_plic_fragmenter_anon_out_d_bits_corrupt = 1'h0; // @[ClockDomain.scala:14:9] wire auto_coupler_to_clint_fragmenter_anon_out_d_bits_sink = 1'h0; // @[ClockDomain.scala:14:9] wire auto_coupler_to_clint_fragmenter_anon_out_d_bits_denied = 1'h0; // @[ClockDomain.scala:14:9] wire auto_coupler_to_clint_fragmenter_anon_out_d_bits_corrupt = 1'h0; // @[ClockDomain.scala:14:9] wire auto_coupler_to_l2_ctrl_buffer_out_d_bits_sink = 1'h0; // @[ClockDomain.scala:14:9] wire auto_coupler_to_l2_ctrl_buffer_out_d_bits_denied = 1'h0; // @[ClockDomain.scala:14:9] wire auto_coupler_to_l2_ctrl_buffer_out_d_bits_corrupt = 1'h0; // @[ClockDomain.scala:14:9] wire _childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25] wire cbus_clock_groups_childClock = 1'h0; // @[LazyModuleImp.scala:155:31] wire cbus_clock_groups_childReset = 1'h0; // @[LazyModuleImp.scala:158:31] wire cbus_clock_groups__childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25] wire clockGroup_childClock = 1'h0; // @[LazyModuleImp.scala:155:31] wire clockGroup_childReset = 1'h0; // @[LazyModuleImp.scala:158:31] wire clockGroup__childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25] wire broadcast_childClock = 1'h0; // @[LazyModuleImp.scala:155:31] wire broadcast_childReset = 1'h0; // @[LazyModuleImp.scala:158:31] wire broadcast__childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25] wire fixer__flight_WIRE_0 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_1 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_2 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_3 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_4 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_5 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_6 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_7 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_8 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_9 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_10 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_11 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_12 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_13 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_14 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_15 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_16 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_17 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_18 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_19 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_20 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_21 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_22 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_23 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_24 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_25 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_26 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_27 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_28 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_29 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_30 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_31 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_32 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_33 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_34 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_35 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_36 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_37 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_38 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_39 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_40 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_41 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_42 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_43 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_44 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_45 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_46 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_47 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_48 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_49 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_50 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_51 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_52 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_53 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_54 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_55 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_56 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_57 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_58 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_59 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_60 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_61 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_62 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_63 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_64 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_65 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_66 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_67 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_68 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_69 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_70 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_71 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_72 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_73 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_74 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_75 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_76 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_77 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_78 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_79 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_80 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_81 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_82 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_83 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_84 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_85 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_86 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_87 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_88 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_89 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_90 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_91 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_92 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_93 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_94 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_95 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_96 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_97 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_98 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_99 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_100 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_101 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_102 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_103 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_104 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_105 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_106 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_107 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_108 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_109 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_110 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_111 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_112 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_113 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_114 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_115 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_116 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_117 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_118 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_119 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_120 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_121 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_122 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_123 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_124 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_125 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_126 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_127 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_128 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_129 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_130 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_131 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_132 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_133 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_134 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_135 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_136 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_137 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_138 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_139 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_140 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_141 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_142 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_143 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_144 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_145 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_146 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_147 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_148 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_149 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_150 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_151 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_152 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_153 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_154 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_155 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_156 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_157 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_158 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_159 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_160 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_161 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_162 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_163 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_164 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_165 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_166 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_167 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_168 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_169 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_170 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_171 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_172 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_173 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_174 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_175 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_176 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_177 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_178 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_179 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_180 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_181 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_182 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_183 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_184 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_185 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_186 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_187 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_188 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_189 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_190 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_191 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_192 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_193 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_194 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_195 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_196 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_197 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_198 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_199 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_200 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_201 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_202 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_203 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_204 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_205 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_206 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_207 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_208 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_209 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_210 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_211 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_212 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_213 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_214 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_215 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_216 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_217 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_218 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_219 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_220 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_221 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_222 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_223 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_224 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_225 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_226 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_227 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_228 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_229 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_230 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_231 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_232 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_233 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_234 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_235 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_236 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_237 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_238 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_239 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_240 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_241 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_242 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_243 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_244 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_245 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_246 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_247 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_248 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_249 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_250 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_251 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_252 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_253 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_254 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_255 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_256 = 1'h0; // @[FIFOFixer.scala:79:35] wire coupler_from_port_named_custom_boot_pin_auto_tl_in_a_bits_source = 1'h0; // @[LazyModuleImp.scala:138:7] wire coupler_from_port_named_custom_boot_pin_auto_tl_in_a_bits_corrupt = 1'h0; // @[LazyModuleImp.scala:138:7] wire coupler_from_port_named_custom_boot_pin_auto_tl_in_d_bits_source = 1'h0; // @[LazyModuleImp.scala:138:7] wire coupler_from_port_named_custom_boot_pin_auto_tl_out_a_bits_source = 1'h0; // @[LazyModuleImp.scala:138:7] wire coupler_from_port_named_custom_boot_pin_auto_tl_out_a_bits_corrupt = 1'h0; // @[LazyModuleImp.scala:138:7] wire coupler_from_port_named_custom_boot_pin_auto_tl_out_d_bits_source = 1'h0; // @[LazyModuleImp.scala:138:7] wire coupler_from_port_named_custom_boot_pin_tlOut_a_bits_source = 1'h0; // @[MixedNode.scala:542:17] wire coupler_from_port_named_custom_boot_pin_tlOut_a_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17] wire coupler_from_port_named_custom_boot_pin_tlOut_d_bits_source = 1'h0; // @[MixedNode.scala:542:17] wire coupler_from_port_named_custom_boot_pin_tlIn_a_bits_source = 1'h0; // @[MixedNode.scala:551:17] wire coupler_from_port_named_custom_boot_pin_tlIn_a_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17] wire coupler_from_port_named_custom_boot_pin_tlIn_d_bits_source = 1'h0; // @[MixedNode.scala:551:17] wire nodeOut_a_bits_source = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_a_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_d_bits_source = 1'h0; // @[MixedNode.scala:542:17] wire _nodeOut_a_bits_legal_T_8 = 1'h0; // @[Parameters.scala:137:59] wire _nodeOut_a_bits_legal_T_9 = 1'h0; // @[Parameters.scala:684:54] wire _nodeOut_a_bits_legal_T_23 = 1'h0; // @[Parameters.scala:137:59] wire _nodeOut_a_bits_legal_T_28 = 1'h0; // @[Parameters.scala:137:59] wire _nodeOut_a_bits_legal_T_33 = 1'h0; // @[Parameters.scala:137:59] wire _nodeOut_a_bits_legal_T_38 = 1'h0; // @[Parameters.scala:137:59] wire _nodeOut_a_bits_legal_T_43 = 1'h0; // @[Parameters.scala:137:59] wire _nodeOut_a_bits_legal_T_50 = 1'h0; // @[Parameters.scala:684:29] wire _nodeOut_a_bits_legal_T_55 = 1'h0; // @[Parameters.scala:137:59] wire _nodeOut_a_bits_legal_T_56 = 1'h0; // @[Parameters.scala:684:54] wire _nodeOut_a_bits_legal_T_57 = 1'h0; // @[Parameters.scala:686:26] wire nodeOut_a_bits_a_source = 1'h0; // @[Edges.scala:480:17] wire nodeOut_a_bits_a_corrupt = 1'h0; // @[Edges.scala:480:17] wire nodeOut_a_bits_a_mask_sub_sub_sub_0_1 = 1'h0; // @[Misc.scala:206:21] wire nodeOut_a_bits_a_mask_sub_sub_1_2 = 1'h0; // @[Misc.scala:214:27] wire _nodeOut_a_bits_a_mask_sub_sub_acc_T_1 = 1'h0; // @[Misc.scala:215:38] wire nodeOut_a_bits_a_mask_sub_sub_1_1 = 1'h0; // @[Misc.scala:215:29] wire nodeOut_a_bits_a_mask_sub_size = 1'h0; // @[Misc.scala:209:26] wire _nodeOut_a_bits_a_mask_sub_acc_T = 1'h0; // @[Misc.scala:215:38] wire nodeOut_a_bits_a_mask_sub_1_2 = 1'h0; // @[Misc.scala:214:27] wire _nodeOut_a_bits_a_mask_sub_acc_T_1 = 1'h0; // @[Misc.scala:215:38] wire nodeOut_a_bits_a_mask_sub_2_2 = 1'h0; // @[Misc.scala:214:27] wire _nodeOut_a_bits_a_mask_sub_acc_T_2 = 1'h0; // @[Misc.scala:215:38] wire nodeOut_a_bits_a_mask_sub_2_1 = 1'h0; // @[Misc.scala:215:29] wire nodeOut_a_bits_a_mask_sub_3_2 = 1'h0; // @[Misc.scala:214:27] wire _nodeOut_a_bits_a_mask_sub_acc_T_3 = 1'h0; // @[Misc.scala:215:38] wire nodeOut_a_bits_a_mask_sub_3_1 = 1'h0; // @[Misc.scala:215:29] wire nodeOut_a_bits_a_mask_eq_1 = 1'h0; // @[Misc.scala:214:27] wire _nodeOut_a_bits_a_mask_acc_T_1 = 1'h0; // @[Misc.scala:215:38] wire nodeOut_a_bits_a_mask_eq_2 = 1'h0; // @[Misc.scala:214:27] wire _nodeOut_a_bits_a_mask_acc_T_2 = 1'h0; // @[Misc.scala:215:38] wire nodeOut_a_bits_a_mask_eq_3 = 1'h0; // @[Misc.scala:214:27] wire _nodeOut_a_bits_a_mask_acc_T_3 = 1'h0; // @[Misc.scala:215:38] wire nodeOut_a_bits_a_mask_eq_4 = 1'h0; // @[Misc.scala:214:27] wire _nodeOut_a_bits_a_mask_acc_T_4 = 1'h0; // @[Misc.scala:215:38] wire nodeOut_a_bits_a_mask_acc_4 = 1'h0; // @[Misc.scala:215:29] wire nodeOut_a_bits_a_mask_eq_5 = 1'h0; // @[Misc.scala:214:27] wire _nodeOut_a_bits_a_mask_acc_T_5 = 1'h0; // @[Misc.scala:215:38] wire nodeOut_a_bits_a_mask_acc_5 = 1'h0; // @[Misc.scala:215:29] wire nodeOut_a_bits_a_mask_eq_6 = 1'h0; // @[Misc.scala:214:27] wire _nodeOut_a_bits_a_mask_acc_T_6 = 1'h0; // @[Misc.scala:215:38] wire nodeOut_a_bits_a_mask_acc_6 = 1'h0; // @[Misc.scala:215:29] wire nodeOut_a_bits_a_mask_eq_7 = 1'h0; // @[Misc.scala:214:27] wire _nodeOut_a_bits_a_mask_acc_T_7 = 1'h0; // @[Misc.scala:215:38] wire nodeOut_a_bits_a_mask_acc_7 = 1'h0; // @[Misc.scala:215:29] wire _nodeOut_a_bits_legal_T_67 = 1'h0; // @[Parameters.scala:137:59] wire _nodeOut_a_bits_legal_T_68 = 1'h0; // @[Parameters.scala:684:54] wire _nodeOut_a_bits_legal_T_77 = 1'h0; // @[Parameters.scala:137:59] wire _nodeOut_a_bits_legal_T_82 = 1'h0; // @[Parameters.scala:137:59] wire _nodeOut_a_bits_legal_T_92 = 1'h0; // @[Parameters.scala:137:59] wire _nodeOut_a_bits_legal_T_97 = 1'h0; // @[Parameters.scala:137:59] wire _nodeOut_a_bits_legal_T_102 = 1'h0; // @[Parameters.scala:137:59] wire _nodeOut_a_bits_legal_T_103 = 1'h0; // @[Parameters.scala:685:42] wire _nodeOut_a_bits_legal_T_109 = 1'h0; // @[Parameters.scala:684:29] wire _nodeOut_a_bits_legal_T_114 = 1'h0; // @[Parameters.scala:137:59] wire _nodeOut_a_bits_legal_T_115 = 1'h0; // @[Parameters.scala:684:54] wire _nodeOut_a_bits_legal_T_116 = 1'h0; // @[Parameters.scala:686:26] wire nodeOut_a_bits_a_1_source = 1'h0; // @[Edges.scala:480:17] wire nodeOut_a_bits_a_1_corrupt = 1'h0; // @[Edges.scala:480:17] wire nodeOut_a_bits_a_mask_sub_sub_sub_0_1_1 = 1'h0; // @[Misc.scala:206:21] wire nodeOut_a_bits_a_mask_sub_sub_1_2_1 = 1'h0; // @[Misc.scala:214:27] wire _nodeOut_a_bits_a_mask_sub_sub_acc_T_3 = 1'h0; // @[Misc.scala:215:38] wire nodeOut_a_bits_a_mask_sub_sub_1_1_1 = 1'h0; // @[Misc.scala:215:29] wire nodeOut_a_bits_a_mask_sub_size_1 = 1'h0; // @[Misc.scala:209:26] wire _nodeOut_a_bits_a_mask_sub_acc_T_4 = 1'h0; // @[Misc.scala:215:38] wire nodeOut_a_bits_a_mask_sub_1_2_1 = 1'h0; // @[Misc.scala:214:27] wire _nodeOut_a_bits_a_mask_sub_acc_T_5 = 1'h0; // @[Misc.scala:215:38] wire nodeOut_a_bits_a_mask_sub_2_2_1 = 1'h0; // @[Misc.scala:214:27] wire _nodeOut_a_bits_a_mask_sub_acc_T_6 = 1'h0; // @[Misc.scala:215:38] wire nodeOut_a_bits_a_mask_sub_2_1_1 = 1'h0; // @[Misc.scala:215:29] wire nodeOut_a_bits_a_mask_sub_3_2_1 = 1'h0; // @[Misc.scala:214:27] wire _nodeOut_a_bits_a_mask_sub_acc_T_7 = 1'h0; // @[Misc.scala:215:38] wire nodeOut_a_bits_a_mask_sub_3_1_1 = 1'h0; // @[Misc.scala:215:29] wire nodeOut_a_bits_a_mask_eq_9 = 1'h0; // @[Misc.scala:214:27] wire _nodeOut_a_bits_a_mask_acc_T_9 = 1'h0; // @[Misc.scala:215:38] wire nodeOut_a_bits_a_mask_eq_10 = 1'h0; // @[Misc.scala:214:27] wire _nodeOut_a_bits_a_mask_acc_T_10 = 1'h0; // @[Misc.scala:215:38] wire nodeOut_a_bits_a_mask_eq_11 = 1'h0; // @[Misc.scala:214:27] wire _nodeOut_a_bits_a_mask_acc_T_11 = 1'h0; // @[Misc.scala:215:38] wire nodeOut_a_bits_a_mask_eq_12 = 1'h0; // @[Misc.scala:214:27] wire _nodeOut_a_bits_a_mask_acc_T_12 = 1'h0; // @[Misc.scala:215:38] wire nodeOut_a_bits_a_mask_acc_12 = 1'h0; // @[Misc.scala:215:29] wire nodeOut_a_bits_a_mask_eq_13 = 1'h0; // @[Misc.scala:214:27] wire _nodeOut_a_bits_a_mask_acc_T_13 = 1'h0; // @[Misc.scala:215:38] wire nodeOut_a_bits_a_mask_acc_13 = 1'h0; // @[Misc.scala:215:29] wire nodeOut_a_bits_a_mask_eq_14 = 1'h0; // @[Misc.scala:214:27] wire _nodeOut_a_bits_a_mask_acc_T_14 = 1'h0; // @[Misc.scala:215:38] wire nodeOut_a_bits_a_mask_acc_14 = 1'h0; // @[Misc.scala:215:29] wire nodeOut_a_bits_a_mask_eq_15 = 1'h0; // @[Misc.scala:214:27] wire _nodeOut_a_bits_a_mask_acc_T_15 = 1'h0; // @[Misc.scala:215:38] wire nodeOut_a_bits_a_mask_acc_15 = 1'h0; // @[Misc.scala:215:29] wire [2:0] auto_coupler_to_bootrom_fragmenter_anon_out_d_bits_opcode = 3'h1; // @[ClockDomain.scala:14:9] wire [7:0] coupler_from_port_named_custom_boot_pin_auto_tl_in_a_bits_mask = 8'hF; // @[LazyModuleImp.scala:138:7] wire [7:0] coupler_from_port_named_custom_boot_pin_auto_tl_out_a_bits_mask = 8'hF; // @[LazyModuleImp.scala:138:7] wire [7:0] coupler_from_port_named_custom_boot_pin_tlOut_a_bits_mask = 8'hF; // @[MixedNode.scala:542:17] wire [7:0] coupler_from_port_named_custom_boot_pin_tlIn_a_bits_mask = 8'hF; // @[MixedNode.scala:551:17] wire [7:0] nodeOut_a_bits_mask = 8'hF; // @[MixedNode.scala:542:17] wire [7:0] nodeOut_a_bits_a_mask = 8'hF; // @[Edges.scala:480:17] wire [7:0] _nodeOut_a_bits_a_mask_T = 8'hF; // @[Misc.scala:222:10] wire [7:0] nodeOut_a_bits_a_1_mask = 8'hF; // @[Edges.scala:480:17] wire [7:0] _nodeOut_a_bits_a_mask_T_1 = 8'hF; // @[Misc.scala:222:10] wire [3:0] coupler_from_port_named_custom_boot_pin_auto_tl_in_a_bits_size = 4'h2; // @[LazyModuleImp.scala:138:7] wire [3:0] coupler_from_port_named_custom_boot_pin_auto_tl_out_a_bits_size = 4'h2; // @[LazyModuleImp.scala:138:7] wire [3:0] coupler_from_port_named_custom_boot_pin_tlOut_a_bits_size = 4'h2; // @[MixedNode.scala:542:17] wire [3:0] coupler_from_port_named_custom_boot_pin_tlIn_a_bits_size = 4'h2; // @[MixedNode.scala:551:17] wire [3:0] nodeOut_a_bits_size = 4'h2; // @[MixedNode.scala:542:17] wire [3:0] nodeOut_a_bits_a_size = 4'h2; // @[Edges.scala:480:17] wire [3:0] nodeOut_a_bits_a_1_size = 4'h2; // @[Edges.scala:480:17] wire [2:0] coupler_from_port_named_custom_boot_pin_auto_tl_in_a_bits_opcode = 3'h0; // @[LazyModuleImp.scala:138:7] wire [2:0] coupler_from_port_named_custom_boot_pin_auto_tl_in_a_bits_param = 3'h0; // @[LazyModuleImp.scala:138:7] wire [2:0] coupler_from_port_named_custom_boot_pin_auto_tl_out_a_bits_opcode = 3'h0; // @[LazyModuleImp.scala:138:7] wire [2:0] coupler_from_port_named_custom_boot_pin_auto_tl_out_a_bits_param = 3'h0; // @[LazyModuleImp.scala:138:7] wire [2:0] coupler_from_port_named_custom_boot_pin_tlOut_a_bits_opcode = 3'h0; // @[MixedNode.scala:542:17] wire [2:0] coupler_from_port_named_custom_boot_pin_tlOut_a_bits_param = 3'h0; // @[MixedNode.scala:542:17] wire [2:0] coupler_from_port_named_custom_boot_pin_tlIn_a_bits_opcode = 3'h0; // @[MixedNode.scala:551:17] wire [2:0] coupler_from_port_named_custom_boot_pin_tlIn_a_bits_param = 3'h0; // @[MixedNode.scala:551:17] wire [2:0] nodeOut_a_bits_opcode = 3'h0; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_a_bits_param = 3'h0; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_a_bits_a_opcode = 3'h0; // @[Edges.scala:480:17] wire [2:0] nodeOut_a_bits_a_param = 3'h0; // @[Edges.scala:480:17] wire [2:0] nodeOut_a_bits_a_1_opcode = 3'h0; // @[Edges.scala:480:17] wire [2:0] nodeOut_a_bits_a_1_param = 3'h0; // @[Edges.scala:480:17] wire [3:0] nodeOut_a_bits_a_mask_hi = 4'h0; // @[Misc.scala:222:10] wire [3:0] nodeOut_a_bits_a_mask_hi_1 = 4'h0; // @[Misc.scala:222:10] wire [3:0] nodeOut_a_bits_a_mask_lo = 4'hF; // @[Misc.scala:222:10] wire [3:0] nodeOut_a_bits_a_mask_lo_1 = 4'hF; // @[Misc.scala:222:10] wire [1:0] nodeOut_a_bits_a_mask_lo_lo = 2'h3; // @[Misc.scala:222:10] wire [1:0] nodeOut_a_bits_a_mask_lo_hi = 2'h3; // @[Misc.scala:222:10] wire [1:0] nodeOut_a_bits_a_mask_lo_lo_1 = 2'h3; // @[Misc.scala:222:10] wire [1:0] nodeOut_a_bits_a_mask_lo_hi_1 = 2'h3; // @[Misc.scala:222:10] wire fixer__a_notFIFO_T_4 = 1'h1; // @[Parameters.scala:137:59] wire fixer__flight_T = 1'h1; // @[FIFOFixer.scala:80:65] wire fixer__anonOut_a_valid_T = 1'h1; // @[FIFOFixer.scala:95:50] wire fixer__anonOut_a_valid_T_1 = 1'h1; // @[FIFOFixer.scala:95:47] wire fixer__anonIn_a_ready_T = 1'h1; // @[FIFOFixer.scala:96:50] wire fixer__anonIn_a_ready_T_1 = 1'h1; // @[FIFOFixer.scala:96:47] wire coupler_from_port_named_custom_boot_pin_auto_tl_in_d_ready = 1'h1; // @[LazyModuleImp.scala:138:7] wire coupler_from_port_named_custom_boot_pin_auto_tl_out_d_ready = 1'h1; // @[LazyModuleImp.scala:138:7] wire coupler_from_port_named_custom_boot_pin_tlOut_d_ready = 1'h1; // @[MixedNode.scala:542:17] wire coupler_from_port_named_custom_boot_pin_tlIn_d_ready = 1'h1; // @[MixedNode.scala:551:17] wire nodeOut_d_ready = 1'h1; // @[MixedNode.scala:542:17] wire _nodeOut_a_bits_legal_T = 1'h1; // @[Parameters.scala:92:28] wire _nodeOut_a_bits_legal_T_1 = 1'h1; // @[Parameters.scala:92:38] wire _nodeOut_a_bits_legal_T_2 = 1'h1; // @[Parameters.scala:92:33] wire _nodeOut_a_bits_legal_T_3 = 1'h1; // @[Parameters.scala:684:29] wire _nodeOut_a_bits_legal_T_10 = 1'h1; // @[Parameters.scala:92:28] wire _nodeOut_a_bits_legal_T_11 = 1'h1; // @[Parameters.scala:92:38] wire _nodeOut_a_bits_legal_T_12 = 1'h1; // @[Parameters.scala:92:33] wire _nodeOut_a_bits_legal_T_13 = 1'h1; // @[Parameters.scala:684:29] wire _nodeOut_a_bits_legal_T_18 = 1'h1; // @[Parameters.scala:137:59] wire _nodeOut_a_bits_legal_T_44 = 1'h1; // @[Parameters.scala:685:42] wire _nodeOut_a_bits_legal_T_45 = 1'h1; // @[Parameters.scala:685:42] wire _nodeOut_a_bits_legal_T_46 = 1'h1; // @[Parameters.scala:685:42] wire _nodeOut_a_bits_legal_T_47 = 1'h1; // @[Parameters.scala:685:42] wire _nodeOut_a_bits_legal_T_48 = 1'h1; // @[Parameters.scala:685:42] wire _nodeOut_a_bits_legal_T_49 = 1'h1; // @[Parameters.scala:684:54] wire _nodeOut_a_bits_legal_T_58 = 1'h1; // @[Parameters.scala:686:26] wire nodeOut_a_bits_legal = 1'h1; // @[Parameters.scala:686:26] wire nodeOut_a_bits_a_mask_sub_sub_size = 1'h1; // @[Misc.scala:209:26] wire nodeOut_a_bits_a_mask_sub_sub_nbit = 1'h1; // @[Misc.scala:211:20] wire nodeOut_a_bits_a_mask_sub_sub_0_2 = 1'h1; // @[Misc.scala:214:27] wire _nodeOut_a_bits_a_mask_sub_sub_acc_T = 1'h1; // @[Misc.scala:215:38] wire nodeOut_a_bits_a_mask_sub_sub_0_1 = 1'h1; // @[Misc.scala:215:29] wire nodeOut_a_bits_a_mask_sub_nbit = 1'h1; // @[Misc.scala:211:20] wire nodeOut_a_bits_a_mask_sub_0_2 = 1'h1; // @[Misc.scala:214:27] wire nodeOut_a_bits_a_mask_sub_0_1 = 1'h1; // @[Misc.scala:215:29] wire nodeOut_a_bits_a_mask_sub_1_1 = 1'h1; // @[Misc.scala:215:29] wire nodeOut_a_bits_a_mask_size = 1'h1; // @[Misc.scala:209:26] wire nodeOut_a_bits_a_mask_nbit = 1'h1; // @[Misc.scala:211:20] wire nodeOut_a_bits_a_mask_eq = 1'h1; // @[Misc.scala:214:27] wire _nodeOut_a_bits_a_mask_acc_T = 1'h1; // @[Misc.scala:215:38] wire nodeOut_a_bits_a_mask_acc = 1'h1; // @[Misc.scala:215:29] wire nodeOut_a_bits_a_mask_acc_1 = 1'h1; // @[Misc.scala:215:29] wire nodeOut_a_bits_a_mask_acc_2 = 1'h1; // @[Misc.scala:215:29] wire nodeOut_a_bits_a_mask_acc_3 = 1'h1; // @[Misc.scala:215:29] wire _nodeOut_a_bits_legal_T_59 = 1'h1; // @[Parameters.scala:92:28] wire _nodeOut_a_bits_legal_T_60 = 1'h1; // @[Parameters.scala:92:38] wire _nodeOut_a_bits_legal_T_61 = 1'h1; // @[Parameters.scala:92:33] wire _nodeOut_a_bits_legal_T_62 = 1'h1; // @[Parameters.scala:684:29] wire _nodeOut_a_bits_legal_T_69 = 1'h1; // @[Parameters.scala:92:28] wire _nodeOut_a_bits_legal_T_70 = 1'h1; // @[Parameters.scala:92:38] wire _nodeOut_a_bits_legal_T_71 = 1'h1; // @[Parameters.scala:92:33] wire _nodeOut_a_bits_legal_T_72 = 1'h1; // @[Parameters.scala:684:29] wire _nodeOut_a_bits_legal_T_87 = 1'h1; // @[Parameters.scala:137:59] wire _nodeOut_a_bits_legal_T_104 = 1'h1; // @[Parameters.scala:685:42] wire _nodeOut_a_bits_legal_T_105 = 1'h1; // @[Parameters.scala:685:42] wire _nodeOut_a_bits_legal_T_106 = 1'h1; // @[Parameters.scala:685:42] wire _nodeOut_a_bits_legal_T_107 = 1'h1; // @[Parameters.scala:685:42] wire _nodeOut_a_bits_legal_T_108 = 1'h1; // @[Parameters.scala:684:54] wire _nodeOut_a_bits_legal_T_117 = 1'h1; // @[Parameters.scala:686:26] wire nodeOut_a_bits_legal_1 = 1'h1; // @[Parameters.scala:686:26] wire nodeOut_a_bits_a_mask_sub_sub_size_1 = 1'h1; // @[Misc.scala:209:26] wire nodeOut_a_bits_a_mask_sub_sub_nbit_1 = 1'h1; // @[Misc.scala:211:20] wire nodeOut_a_bits_a_mask_sub_sub_0_2_1 = 1'h1; // @[Misc.scala:214:27] wire _nodeOut_a_bits_a_mask_sub_sub_acc_T_2 = 1'h1; // @[Misc.scala:215:38] wire nodeOut_a_bits_a_mask_sub_sub_0_1_1 = 1'h1; // @[Misc.scala:215:29] wire nodeOut_a_bits_a_mask_sub_nbit_1 = 1'h1; // @[Misc.scala:211:20] wire nodeOut_a_bits_a_mask_sub_0_2_1 = 1'h1; // @[Misc.scala:214:27] wire nodeOut_a_bits_a_mask_sub_0_1_1 = 1'h1; // @[Misc.scala:215:29] wire nodeOut_a_bits_a_mask_sub_1_1_1 = 1'h1; // @[Misc.scala:215:29] wire nodeOut_a_bits_a_mask_size_1 = 1'h1; // @[Misc.scala:209:26] wire nodeOut_a_bits_a_mask_nbit_1 = 1'h1; // @[Misc.scala:211:20] wire nodeOut_a_bits_a_mask_eq_8 = 1'h1; // @[Misc.scala:214:27] wire _nodeOut_a_bits_a_mask_acc_T_8 = 1'h1; // @[Misc.scala:215:38] wire nodeOut_a_bits_a_mask_acc_8 = 1'h1; // @[Misc.scala:215:29] wire nodeOut_a_bits_a_mask_acc_9 = 1'h1; // @[Misc.scala:215:29] wire nodeOut_a_bits_a_mask_acc_10 = 1'h1; // @[Misc.scala:215:29] wire nodeOut_a_bits_a_mask_acc_11 = 1'h1; // @[Misc.scala:215:29] wire [2:0] nodeOut_a_bits_a_mask_sizeOH = 3'h5; // @[Misc.scala:202:81] wire [2:0] nodeOut_a_bits_a_mask_sizeOH_1 = 3'h5; // @[Misc.scala:202:81] wire [2:0] _nodeOut_a_bits_a_mask_sizeOH_T_2 = 3'h4; // @[OneHot.scala:65:27] wire [2:0] _nodeOut_a_bits_a_mask_sizeOH_T_5 = 3'h4; // @[OneHot.scala:65:27] wire [3:0] _nodeOut_a_bits_a_mask_sizeOH_T_1 = 4'h4; // @[OneHot.scala:65:12] wire [3:0] _nodeOut_a_bits_a_mask_sizeOH_T_4 = 4'h4; // @[OneHot.scala:65:12] wire [1:0] nodeOut_a_bits_a_mask_sizeOH_shiftAmount = 2'h2; // @[OneHot.scala:64:49] wire [1:0] nodeOut_a_bits_a_mask_sizeOH_shiftAmount_1 = 2'h2; // @[OneHot.scala:64:49] wire [63:0] nodeOut_a_bits_a_1_data = 64'h1; // @[Edges.scala:480:17] wire [28:0] nodeOut_a_bits_a_1_address = 29'h2000000; // @[Edges.scala:480:17] wire [29:0] _nodeOut_a_bits_legal_T_112 = 30'h2010000; // @[Parameters.scala:137:46] wire [29:0] _nodeOut_a_bits_legal_T_113 = 30'h2010000; // @[Parameters.scala:137:46] wire [26:0] _nodeOut_a_bits_legal_T_111 = 27'h2010000; // @[Parameters.scala:137:41] wire [29:0] _nodeOut_a_bits_legal_T_99 = 30'h12000000; // @[Parameters.scala:137:41] wire [29:0] _nodeOut_a_bits_legal_T_100 = 30'h12000000; // @[Parameters.scala:137:46] wire [29:0] _nodeOut_a_bits_legal_T_101 = 30'h12000000; // @[Parameters.scala:137:46] wire [29:0] _nodeOut_a_bits_legal_T_36 = 30'h8000000; // @[Parameters.scala:137:46] wire [29:0] _nodeOut_a_bits_legal_T_37 = 30'h8000000; // @[Parameters.scala:137:46] wire [29:0] _nodeOut_a_bits_legal_T_95 = 30'h8000000; // @[Parameters.scala:137:46] wire [29:0] _nodeOut_a_bits_legal_T_96 = 30'h8000000; // @[Parameters.scala:137:46] wire [28:0] _nodeOut_a_bits_legal_T_94 = 29'hA000000; // @[Parameters.scala:137:41] wire [29:0] _nodeOut_a_bits_legal_T_53 = 30'h10000; // @[Parameters.scala:137:46] wire [29:0] _nodeOut_a_bits_legal_T_54 = 30'h10000; // @[Parameters.scala:137:46] wire [29:0] _nodeOut_a_bits_legal_T_90 = 30'h10000; // @[Parameters.scala:137:46] wire [29:0] _nodeOut_a_bits_legal_T_91 = 30'h10000; // @[Parameters.scala:137:46] wire [26:0] _nodeOut_a_bits_legal_T_89 = 27'h10000; // @[Parameters.scala:137:41] wire [29:0] fixer__a_notFIFO_T_2 = 30'h0; // @[Parameters.scala:137:46] wire [29:0] fixer__a_notFIFO_T_3 = 30'h0; // @[Parameters.scala:137:46] wire [29:0] _nodeOut_a_bits_legal_T_16 = 30'h0; // @[Parameters.scala:137:46] wire [29:0] _nodeOut_a_bits_legal_T_17 = 30'h0; // @[Parameters.scala:137:46] wire [29:0] _nodeOut_a_bits_legal_T_85 = 30'h0; // @[Parameters.scala:137:46] wire [29:0] _nodeOut_a_bits_legal_T_86 = 30'h0; // @[Parameters.scala:137:46] wire [26:0] _nodeOut_a_bits_legal_T_84 = 27'h0; // @[Parameters.scala:137:41] wire [29:0] _nodeOut_a_bits_legal_T_80 = 30'h2100000; // @[Parameters.scala:137:46] wire [29:0] _nodeOut_a_bits_legal_T_81 = 30'h2100000; // @[Parameters.scala:137:46] wire [26:0] _nodeOut_a_bits_legal_T_79 = 27'h2100000; // @[Parameters.scala:137:41] wire [29:0] _nodeOut_a_bits_legal_T_26 = 30'h2000000; // @[Parameters.scala:137:46] wire [29:0] _nodeOut_a_bits_legal_T_27 = 30'h2000000; // @[Parameters.scala:137:46] wire [29:0] _nodeOut_a_bits_legal_T_75 = 30'h2000000; // @[Parameters.scala:137:46] wire [29:0] _nodeOut_a_bits_legal_T_76 = 30'h2000000; // @[Parameters.scala:137:46] wire [26:0] _nodeOut_a_bits_legal_T_74 = 27'h2000000; // @[Parameters.scala:137:41] wire [29:0] _nodeOut_a_bits_legal_T_65 = 30'h2003000; // @[Parameters.scala:137:46] wire [29:0] _nodeOut_a_bits_legal_T_66 = 30'h2003000; // @[Parameters.scala:137:46] wire [26:0] _nodeOut_a_bits_legal_T_64 = 27'h2003000; // @[Parameters.scala:137:41] wire [63:0] nodeOut_a_bits_a_data = 64'h80000000; // @[Edges.scala:480:17] wire [28:0] nodeOut_a_bits_a_address = 29'h1000; // @[Edges.scala:480:17] wire [17:0] _nodeOut_a_bits_legal_T_52 = 18'h11000; // @[Parameters.scala:137:41] wire [29:0] _nodeOut_a_bits_legal_T_40 = 30'h10001000; // @[Parameters.scala:137:41] wire [29:0] _nodeOut_a_bits_legal_T_41 = 30'h10001000; // @[Parameters.scala:137:46] wire [29:0] _nodeOut_a_bits_legal_T_42 = 30'h10001000; // @[Parameters.scala:137:46] wire [28:0] _nodeOut_a_bits_legal_T_35 = 29'h8001000; // @[Parameters.scala:137:41] wire [29:0] _nodeOut_a_bits_legal_T_31 = 30'h2011000; // @[Parameters.scala:137:46] wire [29:0] _nodeOut_a_bits_legal_T_32 = 30'h2011000; // @[Parameters.scala:137:46] wire [26:0] _nodeOut_a_bits_legal_T_30 = 27'h2011000; // @[Parameters.scala:137:41] wire [26:0] _nodeOut_a_bits_legal_T_25 = 27'h2001000; // @[Parameters.scala:137:41] wire [29:0] _nodeOut_a_bits_legal_T_21 = 30'h101000; // @[Parameters.scala:137:46] wire [29:0] _nodeOut_a_bits_legal_T_22 = 30'h101000; // @[Parameters.scala:137:46] wire [21:0] _nodeOut_a_bits_legal_T_20 = 22'h101000; // @[Parameters.scala:137:41] wire [13:0] _nodeOut_a_bits_legal_T_15 = 14'h1000; // @[Parameters.scala:137:41] wire [29:0] _nodeOut_a_bits_legal_T_6 = 30'h2000; // @[Parameters.scala:137:46] wire [29:0] _nodeOut_a_bits_legal_T_7 = 30'h2000; // @[Parameters.scala:137:46] wire [14:0] _nodeOut_a_bits_legal_T_5 = 15'h2000; // @[Parameters.scala:137:41] wire [256:0] fixer__allIDs_FIFOed_T = 257'h1FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF; // @[FIFOFixer.scala:127:48] wire [28:0] _nodeOut_a_bits_legal_T_98 = 29'h12000000; // @[Parameters.scala:137:31] wire [27:0] _nodeOut_a_bits_legal_T_93 = 28'hA000000; // @[Parameters.scala:137:31] wire [25:0] _nodeOut_a_bits_legal_T_88 = 26'h10000; // @[Parameters.scala:137:31] wire [25:0] _nodeOut_a_bits_legal_T_83 = 26'h0; // @[Parameters.scala:137:31] wire [25:0] _nodeOut_a_bits_legal_T_78 = 26'h2100000; // @[Parameters.scala:137:31] wire [25:0] _nodeOut_a_bits_legal_T_63 = 26'h2003000; // @[Parameters.scala:137:31] wire [16:0] _nodeOut_a_bits_legal_T_51 = 17'h11000; // @[Parameters.scala:137:31] wire [28:0] _nodeOut_a_bits_legal_T_39 = 29'h10001000; // @[Parameters.scala:137:31] wire [27:0] _nodeOut_a_bits_legal_T_34 = 28'h8001000; // @[Parameters.scala:137:31] wire [25:0] _nodeOut_a_bits_legal_T_29 = 26'h2011000; // @[Parameters.scala:137:31] wire [25:0] _nodeOut_a_bits_legal_T_24 = 26'h2001000; // @[Parameters.scala:137:31] wire [20:0] _nodeOut_a_bits_legal_T_19 = 21'h101000; // @[Parameters.scala:137:31] wire [13:0] _nodeOut_a_bits_legal_T_4 = 14'h2000; // @[Parameters.scala:137:31] wire [2:0] _nodeOut_a_bits_a_mask_sizeOH_T = 3'h2; // @[Misc.scala:202:34] wire [2:0] _nodeOut_a_bits_a_mask_sizeOH_T_3 = 3'h2; // @[Misc.scala:202:34] wire [25:0] _nodeOut_a_bits_legal_T_110 = 26'h2010000; // @[Parameters.scala:137:31] wire [25:0] _nodeOut_a_bits_legal_T_73 = 26'h2000000; // @[Parameters.scala:137:31] wire [12:0] _nodeOut_a_bits_legal_T_14 = 13'h1000; // @[Parameters.scala:137:31] wire coupler_to_bus_named_pbus_auto_bus_xing_out_a_ready = auto_coupler_to_bus_named_pbus_bus_xing_out_a_ready_0; // @[ClockDomain.scala:14:9] wire coupler_to_bus_named_pbus_auto_bus_xing_out_a_valid; // @[LazyModuleImp.scala:138:7] wire [2:0] coupler_to_bus_named_pbus_auto_bus_xing_out_a_bits_opcode; // @[LazyModuleImp.scala:138:7] wire [2:0] coupler_to_bus_named_pbus_auto_bus_xing_out_a_bits_param; // @[LazyModuleImp.scala:138:7] wire [2:0] coupler_to_bus_named_pbus_auto_bus_xing_out_a_bits_size; // @[LazyModuleImp.scala:138:7] wire [8:0] coupler_to_bus_named_pbus_auto_bus_xing_out_a_bits_source; // @[LazyModuleImp.scala:138:7] wire [28:0] coupler_to_bus_named_pbus_auto_bus_xing_out_a_bits_address; // @[LazyModuleImp.scala:138:7] wire [7:0] coupler_to_bus_named_pbus_auto_bus_xing_out_a_bits_mask; // @[LazyModuleImp.scala:138:7] wire [63:0] coupler_to_bus_named_pbus_auto_bus_xing_out_a_bits_data; // @[LazyModuleImp.scala:138:7] wire coupler_to_bus_named_pbus_auto_bus_xing_out_a_bits_corrupt; // @[LazyModuleImp.scala:138:7] wire coupler_to_bus_named_pbus_auto_bus_xing_out_d_ready; // @[LazyModuleImp.scala:138:7] wire coupler_to_bus_named_pbus_auto_bus_xing_out_d_valid = auto_coupler_to_bus_named_pbus_bus_xing_out_d_valid_0; // @[ClockDomain.scala:14:9] wire [2:0] coupler_to_bus_named_pbus_auto_bus_xing_out_d_bits_opcode = auto_coupler_to_bus_named_pbus_bus_xing_out_d_bits_opcode_0; // @[ClockDomain.scala:14:9] wire [1:0] coupler_to_bus_named_pbus_auto_bus_xing_out_d_bits_param = auto_coupler_to_bus_named_pbus_bus_xing_out_d_bits_param_0; // @[ClockDomain.scala:14:9] wire [2:0] coupler_to_bus_named_pbus_auto_bus_xing_out_d_bits_size = auto_coupler_to_bus_named_pbus_bus_xing_out_d_bits_size_0; // @[ClockDomain.scala:14:9] wire [8:0] coupler_to_bus_named_pbus_auto_bus_xing_out_d_bits_source = auto_coupler_to_bus_named_pbus_bus_xing_out_d_bits_source_0; // @[ClockDomain.scala:14:9] wire coupler_to_bus_named_pbus_auto_bus_xing_out_d_bits_sink = auto_coupler_to_bus_named_pbus_bus_xing_out_d_bits_sink_0; // @[ClockDomain.scala:14:9] wire coupler_to_bus_named_pbus_auto_bus_xing_out_d_bits_denied = auto_coupler_to_bus_named_pbus_bus_xing_out_d_bits_denied_0; // @[ClockDomain.scala:14:9] wire [63:0] coupler_to_bus_named_pbus_auto_bus_xing_out_d_bits_data = auto_coupler_to_bus_named_pbus_bus_xing_out_d_bits_data_0; // @[ClockDomain.scala:14:9] wire coupler_to_bus_named_pbus_auto_bus_xing_out_d_bits_corrupt = auto_coupler_to_bus_named_pbus_bus_xing_out_d_bits_corrupt_0; // @[ClockDomain.scala:14:9] wire cbus_clock_groups_auto_in_member_cbus_0_clock = auto_cbus_clock_groups_in_member_cbus_0_clock_0; // @[ClockGroup.scala:53:9] wire cbus_clock_groups_auto_in_member_cbus_0_reset = auto_cbus_clock_groups_in_member_cbus_0_reset_0; // @[ClockGroup.scala:53:9] wire bus_xingIn_a_ready; // @[MixedNode.scala:551:17] wire bus_xingIn_a_valid = auto_bus_xing_in_a_valid_0; // @[ClockDomain.scala:14:9] wire [2:0] bus_xingIn_a_bits_opcode = auto_bus_xing_in_a_bits_opcode_0; // @[ClockDomain.scala:14:9] wire [2:0] bus_xingIn_a_bits_param = auto_bus_xing_in_a_bits_param_0; // @[ClockDomain.scala:14:9] wire [3:0] bus_xingIn_a_bits_size = auto_bus_xing_in_a_bits_size_0; // @[ClockDomain.scala:14:9] wire [7:0] bus_xingIn_a_bits_source = auto_bus_xing_in_a_bits_source_0; // @[ClockDomain.scala:14:9] wire [28:0] bus_xingIn_a_bits_address = auto_bus_xing_in_a_bits_address_0; // @[ClockDomain.scala:14:9] wire [7:0] bus_xingIn_a_bits_mask = auto_bus_xing_in_a_bits_mask_0; // @[ClockDomain.scala:14:9] wire [63:0] bus_xingIn_a_bits_data = auto_bus_xing_in_a_bits_data_0; // @[ClockDomain.scala:14:9] wire bus_xingIn_a_bits_corrupt = auto_bus_xing_in_a_bits_corrupt_0; // @[ClockDomain.scala:14:9] wire bus_xingIn_d_ready = auto_bus_xing_in_d_ready_0; // @[ClockDomain.scala:14:9] wire bus_xingIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] bus_xingIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] bus_xingIn_d_bits_param; // @[MixedNode.scala:551:17] wire [3:0] bus_xingIn_d_bits_size; // @[MixedNode.scala:551:17] wire [7:0] bus_xingIn_d_bits_source; // @[MixedNode.scala:551:17] wire bus_xingIn_d_bits_sink; // @[MixedNode.scala:551:17] wire bus_xingIn_d_bits_denied; // @[MixedNode.scala:551:17] wire [63:0] bus_xingIn_d_bits_data; // @[MixedNode.scala:551:17] wire bus_xingIn_d_bits_corrupt; // @[MixedNode.scala:551:17] wire [2:0] auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_opcode_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_param_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_size_0; // @[ClockDomain.scala:14:9] wire [8:0] auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_source_0; // @[ClockDomain.scala:14:9] wire [20:0] auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_address_0; // @[ClockDomain.scala:14:9] wire [7:0] auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_mask_0; // @[ClockDomain.scala:14:9] wire [63:0] auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_data_0; // @[ClockDomain.scala:14:9] wire auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_corrupt_0; // @[ClockDomain.scala:14:9] wire auto_coupler_to_prci_ctrl_fixer_anon_out_a_valid_0; // @[ClockDomain.scala:14:9] wire auto_coupler_to_prci_ctrl_fixer_anon_out_d_ready_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_opcode_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_param_0; // @[ClockDomain.scala:14:9] wire [1:0] auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_size_0; // @[ClockDomain.scala:14:9] wire [12:0] auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_source_0; // @[ClockDomain.scala:14:9] wire [16:0] auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_address_0; // @[ClockDomain.scala:14:9] wire [7:0] auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_mask_0; // @[ClockDomain.scala:14:9] wire [63:0] auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_data_0; // @[ClockDomain.scala:14:9] wire auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_corrupt_0; // @[ClockDomain.scala:14:9] wire auto_coupler_to_bootrom_fragmenter_anon_out_a_valid_0; // @[ClockDomain.scala:14:9] wire auto_coupler_to_bootrom_fragmenter_anon_out_d_ready_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_to_debug_fragmenter_anon_out_a_bits_opcode_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_to_debug_fragmenter_anon_out_a_bits_param_0; // @[ClockDomain.scala:14:9] wire [1:0] auto_coupler_to_debug_fragmenter_anon_out_a_bits_size_0; // @[ClockDomain.scala:14:9] wire [12:0] auto_coupler_to_debug_fragmenter_anon_out_a_bits_source_0; // @[ClockDomain.scala:14:9] wire [11:0] auto_coupler_to_debug_fragmenter_anon_out_a_bits_address_0; // @[ClockDomain.scala:14:9] wire [7:0] auto_coupler_to_debug_fragmenter_anon_out_a_bits_mask_0; // @[ClockDomain.scala:14:9] wire [63:0] auto_coupler_to_debug_fragmenter_anon_out_a_bits_data_0; // @[ClockDomain.scala:14:9] wire auto_coupler_to_debug_fragmenter_anon_out_a_bits_corrupt_0; // @[ClockDomain.scala:14:9] wire auto_coupler_to_debug_fragmenter_anon_out_a_valid_0; // @[ClockDomain.scala:14:9] wire auto_coupler_to_debug_fragmenter_anon_out_d_ready_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_to_plic_fragmenter_anon_out_a_bits_opcode_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_to_plic_fragmenter_anon_out_a_bits_param_0; // @[ClockDomain.scala:14:9] wire [1:0] auto_coupler_to_plic_fragmenter_anon_out_a_bits_size_0; // @[ClockDomain.scala:14:9] wire [12:0] auto_coupler_to_plic_fragmenter_anon_out_a_bits_source_0; // @[ClockDomain.scala:14:9] wire [27:0] auto_coupler_to_plic_fragmenter_anon_out_a_bits_address_0; // @[ClockDomain.scala:14:9] wire [7:0] auto_coupler_to_plic_fragmenter_anon_out_a_bits_mask_0; // @[ClockDomain.scala:14:9] wire [63:0] auto_coupler_to_plic_fragmenter_anon_out_a_bits_data_0; // @[ClockDomain.scala:14:9] wire auto_coupler_to_plic_fragmenter_anon_out_a_bits_corrupt_0; // @[ClockDomain.scala:14:9] wire auto_coupler_to_plic_fragmenter_anon_out_a_valid_0; // @[ClockDomain.scala:14:9] wire auto_coupler_to_plic_fragmenter_anon_out_d_ready_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_to_clint_fragmenter_anon_out_a_bits_opcode_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_to_clint_fragmenter_anon_out_a_bits_param_0; // @[ClockDomain.scala:14:9] wire [1:0] auto_coupler_to_clint_fragmenter_anon_out_a_bits_size_0; // @[ClockDomain.scala:14:9] wire [12:0] auto_coupler_to_clint_fragmenter_anon_out_a_bits_source_0; // @[ClockDomain.scala:14:9] wire [25:0] auto_coupler_to_clint_fragmenter_anon_out_a_bits_address_0; // @[ClockDomain.scala:14:9] wire [7:0] auto_coupler_to_clint_fragmenter_anon_out_a_bits_mask_0; // @[ClockDomain.scala:14:9] wire [63:0] auto_coupler_to_clint_fragmenter_anon_out_a_bits_data_0; // @[ClockDomain.scala:14:9] wire auto_coupler_to_clint_fragmenter_anon_out_a_bits_corrupt_0; // @[ClockDomain.scala:14:9] wire auto_coupler_to_clint_fragmenter_anon_out_a_valid_0; // @[ClockDomain.scala:14:9] wire auto_coupler_to_clint_fragmenter_anon_out_d_ready_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_opcode_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_param_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_size_0; // @[ClockDomain.scala:14:9] wire [8:0] auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_source_0; // @[ClockDomain.scala:14:9] wire [28:0] auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_address_0; // @[ClockDomain.scala:14:9] wire [7:0] auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_mask_0; // @[ClockDomain.scala:14:9] wire [63:0] auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_data_0; // @[ClockDomain.scala:14:9] wire auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_corrupt_0; // @[ClockDomain.scala:14:9] wire auto_coupler_to_bus_named_pbus_bus_xing_out_a_valid_0; // @[ClockDomain.scala:14:9] wire auto_coupler_to_bus_named_pbus_bus_xing_out_d_ready_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_to_l2_ctrl_buffer_out_a_bits_opcode_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_to_l2_ctrl_buffer_out_a_bits_param_0; // @[ClockDomain.scala:14:9] wire [1:0] auto_coupler_to_l2_ctrl_buffer_out_a_bits_size_0; // @[ClockDomain.scala:14:9] wire [12:0] auto_coupler_to_l2_ctrl_buffer_out_a_bits_source_0; // @[ClockDomain.scala:14:9] wire [25:0] auto_coupler_to_l2_ctrl_buffer_out_a_bits_address_0; // @[ClockDomain.scala:14:9] wire [7:0] auto_coupler_to_l2_ctrl_buffer_out_a_bits_mask_0; // @[ClockDomain.scala:14:9] wire [63:0] auto_coupler_to_l2_ctrl_buffer_out_a_bits_data_0; // @[ClockDomain.scala:14:9] wire auto_coupler_to_l2_ctrl_buffer_out_a_bits_corrupt_0; // @[ClockDomain.scala:14:9] wire auto_coupler_to_l2_ctrl_buffer_out_a_valid_0; // @[ClockDomain.scala:14:9] wire auto_coupler_to_l2_ctrl_buffer_out_d_ready_0; // @[ClockDomain.scala:14:9] wire auto_fixedClockNode_anon_out_5_clock_0; // @[ClockDomain.scala:14:9] wire auto_fixedClockNode_anon_out_5_reset_0; // @[ClockDomain.scala:14:9] wire auto_fixedClockNode_anon_out_4_clock_0; // @[ClockDomain.scala:14:9] wire auto_fixedClockNode_anon_out_4_reset_0; // @[ClockDomain.scala:14:9] wire auto_fixedClockNode_anon_out_3_clock_0; // @[ClockDomain.scala:14:9] wire auto_fixedClockNode_anon_out_3_reset_0; // @[ClockDomain.scala:14:9] wire auto_fixedClockNode_anon_out_2_clock_0; // @[ClockDomain.scala:14:9] wire auto_fixedClockNode_anon_out_2_reset_0; // @[ClockDomain.scala:14:9] wire auto_fixedClockNode_anon_out_1_clock_0; // @[ClockDomain.scala:14:9] wire auto_fixedClockNode_anon_out_1_reset_0; // @[ClockDomain.scala:14:9] wire auto_fixedClockNode_anon_out_0_clock_0; // @[ClockDomain.scala:14:9] wire auto_fixedClockNode_anon_out_0_reset_0; // @[ClockDomain.scala:14:9] wire auto_bus_xing_in_a_ready_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_bus_xing_in_d_bits_opcode_0; // @[ClockDomain.scala:14:9] wire [1:0] auto_bus_xing_in_d_bits_param_0; // @[ClockDomain.scala:14:9] wire [3:0] auto_bus_xing_in_d_bits_size_0; // @[ClockDomain.scala:14:9] wire [7:0] auto_bus_xing_in_d_bits_source_0; // @[ClockDomain.scala:14:9] wire auto_bus_xing_in_d_bits_sink_0; // @[ClockDomain.scala:14:9] wire auto_bus_xing_in_d_bits_denied_0; // @[ClockDomain.scala:14:9] wire [63:0] auto_bus_xing_in_d_bits_data_0; // @[ClockDomain.scala:14:9] wire auto_bus_xing_in_d_bits_corrupt_0; // @[ClockDomain.scala:14:9] wire auto_bus_xing_in_d_valid_0; // @[ClockDomain.scala:14:9] wire clockSinkNodeIn_clock; // @[MixedNode.scala:551:17] wire clockSinkNodeIn_reset; // @[MixedNode.scala:551:17] wire childClock; // @[LazyModuleImp.scala:155:31] wire childReset; // @[LazyModuleImp.scala:158:31] wire cbus_clock_groups_nodeIn_member_cbus_0_clock = cbus_clock_groups_auto_in_member_cbus_0_clock; // @[ClockGroup.scala:53:9] wire cbus_clock_groups_nodeOut_member_cbus_0_clock; // @[MixedNode.scala:542:17] wire cbus_clock_groups_nodeIn_member_cbus_0_reset = cbus_clock_groups_auto_in_member_cbus_0_reset; // @[ClockGroup.scala:53:9] wire cbus_clock_groups_nodeOut_member_cbus_0_reset; // @[MixedNode.scala:542:17] wire clockGroup_auto_in_member_cbus_0_clock = cbus_clock_groups_auto_out_member_cbus_0_clock; // @[ClockGroup.scala:24:9, :53:9] wire clockGroup_auto_in_member_cbus_0_reset = cbus_clock_groups_auto_out_member_cbus_0_reset; // @[ClockGroup.scala:24:9, :53:9] assign cbus_clock_groups_auto_out_member_cbus_0_clock = cbus_clock_groups_nodeOut_member_cbus_0_clock; // @[ClockGroup.scala:53:9] assign cbus_clock_groups_auto_out_member_cbus_0_reset = cbus_clock_groups_nodeOut_member_cbus_0_reset; // @[ClockGroup.scala:53:9] assign cbus_clock_groups_nodeOut_member_cbus_0_clock = cbus_clock_groups_nodeIn_member_cbus_0_clock; // @[MixedNode.scala:542:17, :551:17] assign cbus_clock_groups_nodeOut_member_cbus_0_reset = cbus_clock_groups_nodeIn_member_cbus_0_reset; // @[MixedNode.scala:542:17, :551:17] wire clockGroup_nodeIn_member_cbus_0_clock = clockGroup_auto_in_member_cbus_0_clock; // @[ClockGroup.scala:24:9] wire clockGroup_nodeOut_clock; // @[MixedNode.scala:542:17] wire clockGroup_nodeIn_member_cbus_0_reset = clockGroup_auto_in_member_cbus_0_reset; // @[ClockGroup.scala:24:9] wire clockGroup_nodeOut_reset; // @[MixedNode.scala:542:17] wire clockGroup_auto_out_clock; // @[ClockGroup.scala:24:9] wire clockGroup_auto_out_reset; // @[ClockGroup.scala:24:9] assign clockGroup_auto_out_clock = clockGroup_nodeOut_clock; // @[ClockGroup.scala:24:9] assign clockGroup_auto_out_reset = clockGroup_nodeOut_reset; // @[ClockGroup.scala:24:9] assign clockGroup_nodeOut_clock = clockGroup_nodeIn_member_cbus_0_clock; // @[MixedNode.scala:542:17, :551:17] assign clockGroup_nodeOut_reset = clockGroup_nodeIn_member_cbus_0_reset; // @[MixedNode.scala:542:17, :551:17] wire fixer_anonIn_a_ready; // @[MixedNode.scala:551:17] wire fixer_anonIn_a_valid = fixer_auto_anon_in_a_valid; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_anonIn_a_bits_opcode = fixer_auto_anon_in_a_bits_opcode; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_anonIn_a_bits_param = fixer_auto_anon_in_a_bits_param; // @[FIFOFixer.scala:50:9] wire [3:0] fixer_anonIn_a_bits_size = fixer_auto_anon_in_a_bits_size; // @[FIFOFixer.scala:50:9] wire [8:0] fixer_anonIn_a_bits_source = fixer_auto_anon_in_a_bits_source; // @[FIFOFixer.scala:50:9] wire [28:0] fixer_anonIn_a_bits_address = fixer_auto_anon_in_a_bits_address; // @[FIFOFixer.scala:50:9] wire [7:0] fixer_anonIn_a_bits_mask = fixer_auto_anon_in_a_bits_mask; // @[FIFOFixer.scala:50:9] wire [63:0] fixer_anonIn_a_bits_data = fixer_auto_anon_in_a_bits_data; // @[FIFOFixer.scala:50:9] wire fixer_anonIn_a_bits_corrupt = fixer_auto_anon_in_a_bits_corrupt; // @[FIFOFixer.scala:50:9] wire fixer_anonIn_d_ready = fixer_auto_anon_in_d_ready; // @[FIFOFixer.scala:50:9] wire fixer_anonIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] fixer_anonIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] fixer_anonIn_d_bits_param; // @[MixedNode.scala:551:17] wire [3:0] fixer_anonIn_d_bits_size; // @[MixedNode.scala:551:17] wire [8:0] fixer_anonIn_d_bits_source; // @[MixedNode.scala:551:17] wire fixer_anonIn_d_bits_sink; // @[MixedNode.scala:551:17] wire fixer_anonIn_d_bits_denied; // @[MixedNode.scala:551:17] wire [63:0] fixer_anonIn_d_bits_data; // @[MixedNode.scala:551:17] wire fixer_anonIn_d_bits_corrupt; // @[MixedNode.scala:551:17] wire fixer_anonOut_a_ready = fixer_auto_anon_out_a_ready; // @[FIFOFixer.scala:50:9] wire fixer_anonOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] fixer_anonOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] fixer_anonOut_a_bits_param; // @[MixedNode.scala:542:17] wire [3:0] fixer_anonOut_a_bits_size; // @[MixedNode.scala:542:17] wire [8:0] fixer_anonOut_a_bits_source; // @[MixedNode.scala:542:17] wire [28:0] fixer_anonOut_a_bits_address; // @[MixedNode.scala:542:17] wire [7:0] fixer_anonOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [63:0] fixer_anonOut_a_bits_data; // @[MixedNode.scala:542:17] wire fixer_anonOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire fixer_anonOut_d_ready; // @[MixedNode.scala:542:17] wire fixer_anonOut_d_valid = fixer_auto_anon_out_d_valid; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_anonOut_d_bits_opcode = fixer_auto_anon_out_d_bits_opcode; // @[FIFOFixer.scala:50:9] wire [1:0] fixer_anonOut_d_bits_param = fixer_auto_anon_out_d_bits_param; // @[FIFOFixer.scala:50:9] wire [3:0] fixer_anonOut_d_bits_size = fixer_auto_anon_out_d_bits_size; // @[FIFOFixer.scala:50:9] wire [8:0] fixer_anonOut_d_bits_source = fixer_auto_anon_out_d_bits_source; // @[FIFOFixer.scala:50:9] wire fixer_anonOut_d_bits_sink = fixer_auto_anon_out_d_bits_sink; // @[FIFOFixer.scala:50:9] wire fixer_anonOut_d_bits_denied = fixer_auto_anon_out_d_bits_denied; // @[FIFOFixer.scala:50:9] wire [63:0] fixer_anonOut_d_bits_data = fixer_auto_anon_out_d_bits_data; // @[FIFOFixer.scala:50:9] wire fixer_anonOut_d_bits_corrupt = fixer_auto_anon_out_d_bits_corrupt; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_in_a_ready; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_auto_anon_in_d_bits_opcode; // @[FIFOFixer.scala:50:9] wire [1:0] fixer_auto_anon_in_d_bits_param; // @[FIFOFixer.scala:50:9] wire [3:0] fixer_auto_anon_in_d_bits_size; // @[FIFOFixer.scala:50:9] wire [8:0] fixer_auto_anon_in_d_bits_source; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_in_d_bits_sink; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_in_d_bits_denied; // @[FIFOFixer.scala:50:9] wire [63:0] fixer_auto_anon_in_d_bits_data; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_in_d_bits_corrupt; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_in_d_valid; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_auto_anon_out_a_bits_opcode; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_auto_anon_out_a_bits_param; // @[FIFOFixer.scala:50:9] wire [3:0] fixer_auto_anon_out_a_bits_size; // @[FIFOFixer.scala:50:9] wire [8:0] fixer_auto_anon_out_a_bits_source; // @[FIFOFixer.scala:50:9] wire [28:0] fixer_auto_anon_out_a_bits_address; // @[FIFOFixer.scala:50:9] wire [7:0] fixer_auto_anon_out_a_bits_mask; // @[FIFOFixer.scala:50:9] wire [63:0] fixer_auto_anon_out_a_bits_data; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_out_a_bits_corrupt; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_out_a_valid; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_out_d_ready; // @[FIFOFixer.scala:50:9] wire fixer__anonOut_a_valid_T_2; // @[FIFOFixer.scala:95:33] wire fixer__anonIn_a_ready_T_2 = fixer_anonOut_a_ready; // @[FIFOFixer.scala:96:33] assign fixer_auto_anon_out_a_valid = fixer_anonOut_a_valid; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_out_a_bits_opcode = fixer_anonOut_a_bits_opcode; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_out_a_bits_param = fixer_anonOut_a_bits_param; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_out_a_bits_size = fixer_anonOut_a_bits_size; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_out_a_bits_source = fixer_anonOut_a_bits_source; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_out_a_bits_address = fixer_anonOut_a_bits_address; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_out_a_bits_mask = fixer_anonOut_a_bits_mask; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_out_a_bits_data = fixer_anonOut_a_bits_data; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_out_a_bits_corrupt = fixer_anonOut_a_bits_corrupt; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_out_d_ready = fixer_anonOut_d_ready; // @[FIFOFixer.scala:50:9] assign fixer_anonIn_d_valid = fixer_anonOut_d_valid; // @[MixedNode.scala:542:17, :551:17] assign fixer_anonIn_d_bits_opcode = fixer_anonOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign fixer_anonIn_d_bits_param = fixer_anonOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17] assign fixer_anonIn_d_bits_size = fixer_anonOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17] assign fixer_anonIn_d_bits_source = fixer_anonOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17] assign fixer_anonIn_d_bits_sink = fixer_anonOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17] assign fixer_anonIn_d_bits_denied = fixer_anonOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17] assign fixer_anonIn_d_bits_data = fixer_anonOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17] assign fixer_anonIn_d_bits_corrupt = fixer_anonOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign fixer_auto_anon_in_a_ready = fixer_anonIn_a_ready; // @[FIFOFixer.scala:50:9] assign fixer__anonOut_a_valid_T_2 = fixer_anonIn_a_valid; // @[FIFOFixer.scala:95:33] assign fixer_anonOut_a_bits_opcode = fixer_anonIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign fixer_anonOut_a_bits_param = fixer_anonIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17] assign fixer_anonOut_a_bits_size = fixer_anonIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17] assign fixer_anonOut_a_bits_source = fixer_anonIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17] assign fixer_anonOut_a_bits_address = fixer_anonIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17] wire [28:0] fixer__a_notFIFO_T = fixer_anonIn_a_bits_address; // @[Parameters.scala:137:31] wire [28:0] fixer__a_id_T = fixer_anonIn_a_bits_address; // @[Parameters.scala:137:31] assign fixer_anonOut_a_bits_mask = fixer_anonIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign fixer_anonOut_a_bits_data = fixer_anonIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17] assign fixer_anonOut_a_bits_corrupt = fixer_anonIn_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign fixer_anonOut_d_ready = fixer_anonIn_d_ready; // @[MixedNode.scala:542:17, :551:17] assign fixer_auto_anon_in_d_valid = fixer_anonIn_d_valid; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_in_d_bits_opcode = fixer_anonIn_d_bits_opcode; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_in_d_bits_param = fixer_anonIn_d_bits_param; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_in_d_bits_size = fixer_anonIn_d_bits_size; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_in_d_bits_source = fixer_anonIn_d_bits_source; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_in_d_bits_sink = fixer_anonIn_d_bits_sink; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_in_d_bits_denied = fixer_anonIn_d_bits_denied; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_in_d_bits_data = fixer_anonIn_d_bits_data; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_in_d_bits_corrupt = fixer_anonIn_d_bits_corrupt; // @[FIFOFixer.scala:50:9] wire [29:0] fixer__a_notFIFO_T_1 = {1'h0, fixer__a_notFIFO_T}; // @[Parameters.scala:137:{31,41}] wire [29:0] fixer__a_id_T_1 = {1'h0, fixer__a_id_T}; // @[Parameters.scala:137:{31,41}] wire [29:0] fixer__a_id_T_2 = fixer__a_id_T_1 & 30'h1A113000; // @[Parameters.scala:137:{41,46}] wire [29:0] fixer__a_id_T_3 = fixer__a_id_T_2; // @[Parameters.scala:137:46] wire fixer__a_id_T_4 = fixer__a_id_T_3 == 30'h0; // @[Parameters.scala:137:{46,59}] wire [28:0] fixer__a_id_T_5 = {fixer_anonIn_a_bits_address[28:13], fixer_anonIn_a_bits_address[12:0] ^ 13'h1000}; // @[Parameters.scala:137:31] wire [29:0] fixer__a_id_T_6 = {1'h0, fixer__a_id_T_5}; // @[Parameters.scala:137:{31,41}] wire [29:0] fixer__a_id_T_7 = fixer__a_id_T_6 & 30'h1A113000; // @[Parameters.scala:137:{41,46}] wire [29:0] fixer__a_id_T_8 = fixer__a_id_T_7; // @[Parameters.scala:137:46] wire fixer__a_id_T_9 = fixer__a_id_T_8 == 30'h0; // @[Parameters.scala:137:{46,59}] wire [28:0] fixer__a_id_T_10 = fixer_anonIn_a_bits_address ^ 29'h10000000; // @[Parameters.scala:137:31] wire [29:0] fixer__a_id_T_11 = {1'h0, fixer__a_id_T_10}; // @[Parameters.scala:137:{31,41}] wire [29:0] fixer__a_id_T_12 = fixer__a_id_T_11 & 30'h1A113000; // @[Parameters.scala:137:{41,46}] wire [29:0] fixer__a_id_T_13 = fixer__a_id_T_12; // @[Parameters.scala:137:46] wire fixer__a_id_T_14 = fixer__a_id_T_13 == 30'h0; // @[Parameters.scala:137:{46,59}] wire fixer__a_id_T_15 = fixer__a_id_T_9 \| fixer__a_id_T_14; // @[Parameters.scala:629:89] wire [28:0] fixer__a_id_T_16 = {fixer_anonIn_a_bits_address[28:14], fixer_anonIn_a_bits_address[13:0] ^ 14'h3000}; // @[Parameters.scala:137:31] wire [29:0] fixer__a_id_T_17 = {1'h0, fixer__a_id_T_16}; // @[Parameters.scala:137:{31,41}] wire [29:0] fixer__a_id_T_18 = fixer__a_id_T_17 & 30'h1A113000; // @[Parameters.scala:137:{41,46}] wire [29:0] fixer__a_id_T_19 = fixer__a_id_T_18; // @[Parameters.scala:137:46] wire fixer__a_id_T_20 = fixer__a_id_T_19 == 30'h0; // @[Parameters.scala:137:{46,59}] wire fixer__a_id_T_48 = fixer__a_id_T_20; // @[Mux.scala:30:73] wire [28:0] fixer__a_id_T_21 = {fixer_anonIn_a_bits_address[28:17], fixer_anonIn_a_bits_address[16:0] ^ 17'h10000}; // @[Parameters.scala:137:31] wire [29:0] fixer__a_id_T_22 = {1'h0, fixer__a_id_T_21}; // @[Parameters.scala:137:{31,41}] wire [29:0] fixer__a_id_T_23 = fixer__a_id_T_22 & 30'h1A110000; // @[Parameters.scala:137:{41,46}] wire [29:0] fixer__a_id_T_24 = fixer__a_id_T_23; // @[Parameters.scala:137:46] wire fixer__a_id_T_25 = fixer__a_id_T_24 == 30'h0; // @[Parameters.scala:137:{46,59}] wire [28:0] fixer__a_id_T_26 = {fixer_anonIn_a_bits_address[28:21], fixer_anonIn_a_bits_address[20:0] ^ 21'h100000}; // @[Parameters.scala:137:31] wire [29:0] fixer__a_id_T_27 = {1'h0, fixer__a_id_T_26}; // @[Parameters.scala:137:{31,41}] wire [29:0] fixer__a_id_T_28 = fixer__a_id_T_27 & 30'h1A103000; // @[Parameters.scala:137:{41,46}] wire [29:0] fixer__a_id_T_29 = fixer__a_id_T_28; // @[Parameters.scala:137:46] wire fixer__a_id_T_30 = fixer__a_id_T_29 == 30'h0; // @[Parameters.scala:137:{46,59}] wire [28:0] fixer__a_id_T_31 = {fixer_anonIn_a_bits_address[28:26], fixer_anonIn_a_bits_address[25:0] ^ 26'h2000000}; // @[Parameters.scala:137:31] wire [29:0] fixer__a_id_T_32 = {1'h0, fixer__a_id_T_31}; // @[Parameters.scala:137:{31,41}] wire [29:0] fixer__a_id_T_33 = fixer__a_id_T_32 & 30'h1A110000; // @[Parameters.scala:137:{41,46}] wire [29:0] fixer__a_id_T_34 = fixer__a_id_T_33; // @[Parameters.scala:137:46] wire fixer__a_id_T_35 = fixer__a_id_T_34 == 30'h0; // @[Parameters.scala:137:{46,59}] wire [28:0] fixer__a_id_T_36 = {fixer_anonIn_a_bits_address[28:26], fixer_anonIn_a_bits_address[25:0] ^ 26'h2010000}; // @[Parameters.scala:137:31] wire [29:0] fixer__a_id_T_37 = {1'h0, fixer__a_id_T_36}; // @[Parameters.scala:137:{31,41}] wire [29:0] fixer__a_id_T_38 = fixer__a_id_T_37 & 30'h1A113000; // @[Parameters.scala:137:{41,46}] wire [29:0] fixer__a_id_T_39 = fixer__a_id_T_38; // @[Parameters.scala:137:46] wire fixer__a_id_T_40 = fixer__a_id_T_39 == 30'h0; // @[Parameters.scala:137:{46,59}] wire [28:0] fixer__a_id_T_41 = {fixer_anonIn_a_bits_address[28], fixer_anonIn_a_bits_address[27:0] ^ 28'h8000000}; // @[Parameters.scala:137:31] wire [29:0] fixer__a_id_T_42 = {1'h0, fixer__a_id_T_41}; // @[Parameters.scala:137:{31,41}] wire [29:0] fixer__a_id_T_43 = fixer__a_id_T_42 & 30'h18000000; // @[Parameters.scala:137:{41,46}] wire [29:0] fixer__a_id_T_44 = fixer__a_id_T_43; // @[Parameters.scala:137:46] wire fixer__a_id_T_45 = fixer__a_id_T_44 == 30'h0; // @[Parameters.scala:137:{46,59}] wire [1:0] fixer__a_id_T_46 = {fixer__a_id_T_4, 1'h0}; // @[Mux.scala:30:73] wire [2:0] fixer__a_id_T_47 = fixer__a_id_T_15 ? 3'h5 : 3'h0; // @[Mux.scala:30:73] wire [2:0] fixer__a_id_T_49 = {fixer__a_id_T_25, 2'h0}; // @[Mux.scala:30:73] wire [2:0] fixer__a_id_T_50 = fixer__a_id_T_30 ? 3'h6 : 3'h0; // @[Mux.scala:30:73] wire [2:0] fixer__a_id_T_51 = {3{fixer__a_id_T_35}}; // @[Mux.scala:30:73] wire [1:0] fixer__a_id_T_52 = {2{fixer__a_id_T_40}}; // @[Mux.scala:30:73] wire [3:0] fixer__a_id_T_53 = {fixer__a_id_T_45, 3'h0}; // @[Mux.scala:30:73] wire [2:0] fixer__a_id_T_54 = {1'h0, fixer__a_id_T_46} \| fixer__a_id_T_47; // @[Mux.scala:30:73] wire [2:0] fixer__a_id_T_55 = {fixer__a_id_T_54[2:1], fixer__a_id_T_54[0] \| fixer__a_id_T_48}; // @[Mux.scala:30:73] wire [2:0] fixer__a_id_T_56 = fixer__a_id_T_55 \| fixer__a_id_T_49; // @[Mux.scala:30:73] wire [2:0] fixer__a_id_T_57 = fixer__a_id_T_56 \| fixer__a_id_T_50; // @[Mux.scala:30:73] wire [2:0] fixer__a_id_T_58 = fixer__a_id_T_57 \| fixer__a_id_T_51; // @[Mux.scala:30:73] wire [2:0] fixer__a_id_T_59 = {fixer__a_id_T_58[2], fixer__a_id_T_58[1:0] \| fixer__a_id_T_52}; // @[Mux.scala:30:73] wire [3:0] fixer__a_id_T_60 = {1'h0, fixer__a_id_T_59} \| fixer__a_id_T_53; // @[Mux.scala:30:73] wire [3:0] fixer_a_id = fixer__a_id_T_60; // @[Mux.scala:30:73] wire fixer_a_noDomain = fixer_a_id == 4'h0; // @[Mux.scala:30:73] wire fixer__a_first_T = fixer_anonIn_a_ready & fixer_anonIn_a_valid; // @[Decoupled.scala:51:35] wire [26:0] fixer__a_first_beats1_decode_T = 27'hFFF << fixer_anonIn_a_bits_size; // @[package.scala:243:71] wire [11:0] fixer__a_first_beats1_decode_T_1 = fixer__a_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] fixer__a_first_beats1_decode_T_2 = ~fixer__a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] fixer_a_first_beats1_decode = fixer__a_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire fixer__a_first_beats1_opdata_T = fixer_anonIn_a_bits_opcode[2]; // @[Edges.scala:92:37] wire fixer_a_first_beats1_opdata = ~fixer__a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [8:0] fixer_a_first_beats1 = fixer_a_first_beats1_opdata ? fixer_a_first_beats1_decode : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [8:0] fixer_a_first_counter; // @[Edges.scala:229:27] wire [9:0] fixer__a_first_counter1_T = {1'h0, fixer_a_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] fixer_a_first_counter1 = fixer__a_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire fixer_a_first = fixer_a_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire fixer__a_first_last_T = fixer_a_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire fixer__a_first_last_T_1 = fixer_a_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire fixer_a_first_last = fixer__a_first_last_T \| fixer__a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire fixer_a_first_done = fixer_a_first_last & fixer__a_first_T; // @[Decoupled.scala:51:35] wire [8:0] fixer__a_first_count_T = ~fixer_a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] fixer_a_first_count = fixer_a_first_beats1 & fixer__a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] fixer__a_first_counter_T = fixer_a_first ? fixer_a_first_beats1 : fixer_a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire fixer__d_first_T = fixer_anonOut_d_ready & fixer_anonOut_d_valid; // @[Decoupled.scala:51:35] wire [26:0] fixer__d_first_beats1_decode_T = 27'hFFF << fixer_anonOut_d_bits_size; // @[package.scala:243:71] wire [11:0] fixer__d_first_beats1_decode_T_1 = fixer__d_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] fixer__d_first_beats1_decode_T_2 = ~fixer__d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] fixer_d_first_beats1_decode = fixer__d_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire fixer_d_first_beats1_opdata = fixer_anonOut_d_bits_opcode[0]; // @[Edges.scala:106:36] wire [8:0] fixer_d_first_beats1 = fixer_d_first_beats1_opdata ? fixer_d_first_beats1_decode : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] fixer_d_first_counter; // @[Edges.scala:229:27] wire [9:0] fixer__d_first_counter1_T = {1'h0, fixer_d_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] fixer_d_first_counter1 = fixer__d_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire fixer_d_first_first = fixer_d_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire fixer__d_first_last_T = fixer_d_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire fixer__d_first_last_T_1 = fixer_d_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire fixer_d_first_last = fixer__d_first_last_T \| fixer__d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire fixer_d_first_done = fixer_d_first_last & fixer__d_first_T; // @[Decoupled.scala:51:35] wire [8:0] fixer__d_first_count_T = ~fixer_d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] fixer_d_first_count = fixer_d_first_beats1 & fixer__d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] fixer__d_first_counter_T = fixer_d_first_first ? fixer_d_first_beats1 : fixer_d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire fixer__d_first_T_1 = fixer_anonOut_d_bits_opcode != 3'h6; // @[FIFOFixer.scala:75:63] wire fixer_d_first = fixer_d_first_first & fixer__d_first_T_1; // @[FIFOFixer.scala:75:{42,63}] reg fixer_flight_0; // @[FIFOFixer.scala:79:27] reg fixer_flight_1; // @[FIFOFixer.scala:79:27] reg fixer_flight_2; // @[FIFOFixer.scala:79:27] reg fixer_flight_3; // @[FIFOFixer.scala:79:27] reg fixer_flight_4; // @[FIFOFixer.scala:79:27] reg fixer_flight_5; // @[FIFOFixer.scala:79:27] reg fixer_flight_6; // @[FIFOFixer.scala:79:27] reg fixer_flight_7; // @[FIFOFixer.scala:79:27] reg fixer_flight_8; // @[FIFOFixer.scala:79:27] reg fixer_flight_9; // @[FIFOFixer.scala:79:27] reg fixer_flight_10; // @[FIFOFixer.scala:79:27] reg fixer_flight_11; // @[FIFOFixer.scala:79:27] reg fixer_flight_12; // @[FIFOFixer.scala:79:27] reg fixer_flight_13; // @[FIFOFixer.scala:79:27] reg fixer_flight_14; // @[FIFOFixer.scala:79:27] reg fixer_flight_15; // @[FIFOFixer.scala:79:27] reg fixer_flight_16; // @[FIFOFixer.scala:79:27] reg fixer_flight_17; // @[FIFOFixer.scala:79:27] reg fixer_flight_18; // @[FIFOFixer.scala:79:27] reg fixer_flight_19; // @[FIFOFixer.scala:79:27] reg fixer_flight_20; // @[FIFOFixer.scala:79:27] reg fixer_flight_21; // @[FIFOFixer.scala:79:27] reg fixer_flight_22; // @[FIFOFixer.scala:79:27] reg fixer_flight_23; // @[FIFOFixer.scala:79:27] reg fixer_flight_24; // @[FIFOFixer.scala:79:27] reg fixer_flight_25; // @[FIFOFixer.scala:79:27] reg fixer_flight_26; // @[FIFOFixer.scala:79:27] reg fixer_flight_27; // @[FIFOFixer.scala:79:27] reg fixer_flight_28; // @[FIFOFixer.scala:79:27] reg fixer_flight_29; // @[FIFOFixer.scala:79:27] reg fixer_flight_30; // @[FIFOFixer.scala:79:27] reg fixer_flight_31; // @[FIFOFixer.scala:79:27] reg fixer_flight_32; // @[FIFOFixer.scala:79:27] reg fixer_flight_33; // @[FIFOFixer.scala:79:27] reg fixer_flight_34; // @[FIFOFixer.scala:79:27] reg fixer_flight_35; // @[FIFOFixer.scala:79:27] reg fixer_flight_36; // @[FIFOFixer.scala:79:27] reg fixer_flight_37; // @[FIFOFixer.scala:79:27] reg fixer_flight_38; // @[FIFOFixer.scala:79:27] reg fixer_flight_39; // @[FIFOFixer.scala:79:27] reg fixer_flight_40; // @[FIFOFixer.scala:79:27] reg fixer_flight_41; // @[FIFOFixer.scala:79:27] reg fixer_flight_42; // @[FIFOFixer.scala:79:27] reg fixer_flight_43; // @[FIFOFixer.scala:79:27] reg fixer_flight_44; // @[FIFOFixer.scala:79:27] reg fixer_flight_45; // @[FIFOFixer.scala:79:27] reg fixer_flight_46; // @[FIFOFixer.scala:79:27] reg fixer_flight_47; // @[FIFOFixer.scala:79:27] reg fixer_flight_48; // @[FIFOFixer.scala:79:27] reg fixer_flight_49; // @[FIFOFixer.scala:79:27] reg fixer_flight_50; // @[FIFOFixer.scala:79:27] reg fixer_flight_51; // @[FIFOFixer.scala:79:27] reg fixer_flight_52; // @[FIFOFixer.scala:79:27] reg fixer_flight_53; // @[FIFOFixer.scala:79:27] reg fixer_flight_54; // @[FIFOFixer.scala:79:27] reg fixer_flight_55; // @[FIFOFixer.scala:79:27] reg fixer_flight_56; // @[FIFOFixer.scala:79:27] reg fixer_flight_57; // @[FIFOFixer.scala:79:27] reg fixer_flight_58; // @[FIFOFixer.scala:79:27] reg fixer_flight_59; // @[FIFOFixer.scala:79:27] reg fixer_flight_60; // @[FIFOFixer.scala:79:27] reg fixer_flight_61; // @[FIFOFixer.scala:79:27] reg fixer_flight_62; // @[FIFOFixer.scala:79:27] reg fixer_flight_63; // @[FIFOFixer.scala:79:27] reg fixer_flight_64; // @[FIFOFixer.scala:79:27] reg fixer_flight_65; // @[FIFOFixer.scala:79:27] reg fixer_flight_66; // @[FIFOFixer.scala:79:27] reg fixer_flight_67; // @[FIFOFixer.scala:79:27] reg fixer_flight_68; // @[FIFOFixer.scala:79:27] reg fixer_flight_69; // @[FIFOFixer.scala:79:27] reg fixer_flight_70; // @[FIFOFixer.scala:79:27] reg fixer_flight_71; // @[FIFOFixer.scala:79:27] reg fixer_flight_72; // @[FIFOFixer.scala:79:27] reg fixer_flight_73; // @[FIFOFixer.scala:79:27] reg fixer_flight_74; // @[FIFOFixer.scala:79:27] reg fixer_flight_75; // @[FIFOFixer.scala:79:27] reg fixer_flight_76; // @[FIFOFixer.scala:79:27] reg fixer_flight_77; // @[FIFOFixer.scala:79:27] reg fixer_flight_78; // @[FIFOFixer.scala:79:27] reg fixer_flight_79; // @[FIFOFixer.scala:79:27] reg fixer_flight_80; // @[FIFOFixer.scala:79:27] reg fixer_flight_81; // @[FIFOFixer.scala:79:27] reg fixer_flight_82; // @[FIFOFixer.scala:79:27] reg fixer_flight_83; // @[FIFOFixer.scala:79:27] reg fixer_flight_84; // @[FIFOFixer.scala:79:27] reg fixer_flight_85; // @[FIFOFixer.scala:79:27] reg fixer_flight_86; // @[FIFOFixer.scala:79:27] reg fixer_flight_87; // @[FIFOFixer.scala:79:27] reg fixer_flight_88; // @[FIFOFixer.scala:79:27] reg fixer_flight_89; // @[FIFOFixer.scala:79:27] reg fixer_flight_90; // @[FIFOFixer.scala:79:27] reg fixer_flight_91; // @[FIFOFixer.scala:79:27] reg fixer_flight_92; // @[FIFOFixer.scala:79:27] reg fixer_flight_93; // @[FIFOFixer.scala:79:27] reg fixer_flight_94; // @[FIFOFixer.scala:79:27] reg fixer_flight_95; // @[FIFOFixer.scala:79:27] reg fixer_flight_96; // @[FIFOFixer.scala:79:27] reg fixer_flight_97; // @[FIFOFixer.scala:79:27] reg fixer_flight_98; // @[FIFOFixer.scala:79:27] reg fixer_flight_99; // @[FIFOFixer.scala:79:27] reg fixer_flight_100; // @[FIFOFixer.scala:79:27] reg fixer_flight_101; // @[FIFOFixer.scala:79:27] reg fixer_flight_102; // @[FIFOFixer.scala:79:27] reg fixer_flight_103; // @[FIFOFixer.scala:79:27] reg fixer_flight_104; // @[FIFOFixer.scala:79:27] reg fixer_flight_105; // @[FIFOFixer.scala:79:27] reg fixer_flight_106; // @[FIFOFixer.scala:79:27] reg fixer_flight_107; // @[FIFOFixer.scala:79:27] reg fixer_flight_108; // @[FIFOFixer.scala:79:27] reg fixer_flight_109; // @[FIFOFixer.scala:79:27] reg fixer_flight_110; // @[FIFOFixer.scala:79:27] reg fixer_flight_111; // @[FIFOFixer.scala:79:27] reg fixer_flight_112; // @[FIFOFixer.scala:79:27] reg fixer_flight_113; // @[FIFOFixer.scala:79:27] reg fixer_flight_114; // @[FIFOFixer.scala:79:27] reg fixer_flight_115; // @[FIFOFixer.scala:79:27] reg fixer_flight_116; // @[FIFOFixer.scala:79:27] reg fixer_flight_117; // @[FIFOFixer.scala:79:27] reg fixer_flight_118; // @[FIFOFixer.scala:79:27] reg fixer_flight_119; // @[FIFOFixer.scala:79:27] reg fixer_flight_120; // @[FIFOFixer.scala:79:27] reg fixer_flight_121; // @[FIFOFixer.scala:79:27] reg fixer_flight_122; // @[FIFOFixer.scala:79:27] reg fixer_flight_123; // @[FIFOFixer.scala:79:27] reg fixer_flight_124; // @[FIFOFixer.scala:79:27] reg fixer_flight_125; // @[FIFOFixer.scala:79:27] reg fixer_flight_126; // @[FIFOFixer.scala:79:27] reg fixer_flight_127; // @[FIFOFixer.scala:79:27] reg fixer_flight_128; // @[FIFOFixer.scala:79:27] reg fixer_flight_129; // @[FIFOFixer.scala:79:27] reg fixer_flight_130; // @[FIFOFixer.scala:79:27] reg fixer_flight_131; // @[FIFOFixer.scala:79:27] reg fixer_flight_132; // @[FIFOFixer.scala:79:27] reg fixer_flight_133; // @[FIFOFixer.scala:79:27] reg fixer_flight_134; // @[FIFOFixer.scala:79:27] reg fixer_flight_135; // @[FIFOFixer.scala:79:27] reg fixer_flight_136; // @[FIFOFixer.scala:79:27] reg fixer_flight_137; // @[FIFOFixer.scala:79:27] reg fixer_flight_138; // @[FIFOFixer.scala:79:27] reg fixer_flight_139; // @[FIFOFixer.scala:79:27] reg fixer_flight_140; // @[FIFOFixer.scala:79:27] reg fixer_flight_141; // @[FIFOFixer.scala:79:27] reg fixer_flight_142; // @[FIFOFixer.scala:79:27] reg fixer_flight_143; // @[FIFOFixer.scala:79:27] reg fixer_flight_144; // @[FIFOFixer.scala:79:27] reg fixer_flight_145; // @[FIFOFixer.scala:79:27] reg fixer_flight_146; // @[FIFOFixer.scala:79:27] reg fixer_flight_147; // @[FIFOFixer.scala:79:27] reg fixer_flight_148; // @[FIFOFixer.scala:79:27] reg fixer_flight_149; // @[FIFOFixer.scala:79:27] reg fixer_flight_150; // @[FIFOFixer.scala:79:27] reg fixer_flight_151; // @[FIFOFixer.scala:79:27] reg fixer_flight_152; // @[FIFOFixer.scala:79:27] reg fixer_flight_153; // @[FIFOFixer.scala:79:27] reg fixer_flight_154; // @[FIFOFixer.scala:79:27] reg fixer_flight_155; // @[FIFOFixer.scala:79:27] reg fixer_flight_156; // @[FIFOFixer.scala:79:27] reg fixer_flight_157; // @[FIFOFixer.scala:79:27] reg fixer_flight_158; // @[FIFOFixer.scala:79:27] reg fixer_flight_159; // @[FIFOFixer.scala:79:27] reg fixer_flight_160; // @[FIFOFixer.scala:79:27] reg fixer_flight_161; // @[FIFOFixer.scala:79:27] reg fixer_flight_162; // @[FIFOFixer.scala:79:27] reg fixer_flight_163; // @[FIFOFixer.scala:79:27] reg fixer_flight_164; // @[FIFOFixer.scala:79:27] reg fixer_flight_165; // @[FIFOFixer.scala:79:27] reg fixer_flight_166; // @[FIFOFixer.scala:79:27] reg fixer_flight_167; // @[FIFOFixer.scala:79:27] reg fixer_flight_168; // @[FIFOFixer.scala:79:27] reg fixer_flight_169; // @[FIFOFixer.scala:79:27] reg fixer_flight_170; // @[FIFOFixer.scala:79:27] reg fixer_flight_171; // @[FIFOFixer.scala:79:27] reg fixer_flight_172; // @[FIFOFixer.scala:79:27] reg fixer_flight_173; // @[FIFOFixer.scala:79:27] reg fixer_flight_174; // @[FIFOFixer.scala:79:27] reg fixer_flight_175; // @[FIFOFixer.scala:79:27] reg fixer_flight_176; // @[FIFOFixer.scala:79:27] reg fixer_flight_177; // @[FIFOFixer.scala:79:27] reg fixer_flight_178; // @[FIFOFixer.scala:79:27] reg fixer_flight_179; // @[FIFOFixer.scala:79:27] reg fixer_flight_180; // @[FIFOFixer.scala:79:27] reg fixer_flight_181; // @[FIFOFixer.scala:79:27] reg fixer_flight_182; // @[FIFOFixer.scala:79:27] reg fixer_flight_183; // @[FIFOFixer.scala:79:27] reg fixer_flight_184; // @[FIFOFixer.scala:79:27] reg fixer_flight_185; // @[FIFOFixer.scala:79:27] reg fixer_flight_186; // @[FIFOFixer.scala:79:27] reg fixer_flight_187; // @[FIFOFixer.scala:79:27] reg fixer_flight_188; // @[FIFOFixer.scala:79:27] reg fixer_flight_189; // @[FIFOFixer.scala:79:27] reg fixer_flight_190; // @[FIFOFixer.scala:79:27] reg fixer_flight_191; // @[FIFOFixer.scala:79:27] reg fixer_flight_192; // @[FIFOFixer.scala:79:27] reg fixer_flight_193; // @[FIFOFixer.scala:79:27] reg fixer_flight_194; // @[FIFOFixer.scala:79:27] reg fixer_flight_195; // @[FIFOFixer.scala:79:27] reg fixer_flight_196; // @[FIFOFixer.scala:79:27] reg fixer_flight_197; // @[FIFOFixer.scala:79:27] reg fixer_flight_198; // @[FIFOFixer.scala:79:27] reg fixer_flight_199; // @[FIFOFixer.scala:79:27] reg fixer_flight_200; // @[FIFOFixer.scala:79:27] reg fixer_flight_201; // @[FIFOFixer.scala:79:27] reg fixer_flight_202; // @[FIFOFixer.scala:79:27] reg fixer_flight_203; // @[FIFOFixer.scala:79:27] reg fixer_flight_204; // @[FIFOFixer.scala:79:27] reg fixer_flight_205; // @[FIFOFixer.scala:79:27] reg fixer_flight_206; // @[FIFOFixer.scala:79:27] reg fixer_flight_207; // @[FIFOFixer.scala:79:27] reg fixer_flight_208; // @[FIFOFixer.scala:79:27] reg fixer_flight_209; // @[FIFOFixer.scala:79:27] reg fixer_flight_210; // @[FIFOFixer.scala:79:27] reg fixer_flight_211; // @[FIFOFixer.scala:79:27] reg fixer_flight_212; // @[FIFOFixer.scala:79:27] reg fixer_flight_213; // @[FIFOFixer.scala:79:27] reg fixer_flight_214; // @[FIFOFixer.scala:79:27] reg fixer_flight_215; // @[FIFOFixer.scala:79:27] reg fixer_flight_216; // @[FIFOFixer.scala:79:27] reg fixer_flight_217; // @[FIFOFixer.scala:79:27] reg fixer_flight_218; // @[FIFOFixer.scala:79:27] reg fixer_flight_219; // @[FIFOFixer.scala:79:27] reg fixer_flight_220; // @[FIFOFixer.scala:79:27] reg fixer_flight_221; // @[FIFOFixer.scala:79:27] reg fixer_flight_222; // @[FIFOFixer.scala:79:27] reg fixer_flight_223; // @[FIFOFixer.scala:79:27] reg fixer_flight_224; // @[FIFOFixer.scala:79:27] reg fixer_flight_225; // @[FIFOFixer.scala:79:27] reg fixer_flight_226; // @[FIFOFixer.scala:79:27] reg fixer_flight_227; // @[FIFOFixer.scala:79:27] reg fixer_flight_228; // @[FIFOFixer.scala:79:27] reg fixer_flight_229; // @[FIFOFixer.scala:79:27] reg fixer_flight_230; // @[FIFOFixer.scala:79:27] reg fixer_flight_231; // @[FIFOFixer.scala:79:27] reg fixer_flight_232; // @[FIFOFixer.scala:79:27] reg fixer_flight_233; // @[FIFOFixer.scala:79:27] reg fixer_flight_234; // @[FIFOFixer.scala:79:27] reg fixer_flight_235; // @[FIFOFixer.scala:79:27] reg fixer_flight_236; // @[FIFOFixer.scala:79:27] reg fixer_flight_237; // @[FIFOFixer.scala:79:27] reg fixer_flight_238; // @[FIFOFixer.scala:79:27] reg fixer_flight_239; // @[FIFOFixer.scala:79:27] reg fixer_flight_240; // @[FIFOFixer.scala:79:27] reg fixer_flight_241; // @[FIFOFixer.scala:79:27] reg fixer_flight_242; // @[FIFOFixer.scala:79:27] reg fixer_flight_243; // @[FIFOFixer.scala:79:27] reg fixer_flight_244; // @[FIFOFixer.scala:79:27] reg fixer_flight_245; // @[FIFOFixer.scala:79:27] reg fixer_flight_246; // @[FIFOFixer.scala:79:27] reg fixer_flight_247; // @[FIFOFixer.scala:79:27] reg fixer_flight_248; // @[FIFOFixer.scala:79:27] reg fixer_flight_249; // @[FIFOFixer.scala:79:27] reg fixer_flight_250; // @[FIFOFixer.scala:79:27] reg fixer_flight_251; // @[FIFOFixer.scala:79:27] reg fixer_flight_252; // @[FIFOFixer.scala:79:27] reg fixer_flight_253; // @[FIFOFixer.scala:79:27] reg fixer_flight_254; // @[FIFOFixer.scala:79:27] reg fixer_flight_255; // @[FIFOFixer.scala:79:27] reg fixer_flight_256; // @[FIFOFixer.scala:79:27] wire fixer__T_2 = fixer_anonIn_d_ready & fixer_anonIn_d_valid; // @[Decoupled.scala:51:35] assign fixer_anonOut_a_valid = fixer__anonOut_a_valid_T_2; // @[FIFOFixer.scala:95:33] assign fixer_anonIn_a_ready = fixer__anonIn_a_ready_T_2; // @[FIFOFixer.scala:96:33] reg [256:0] fixer_SourceIdFIFOed; // @[FIFOFixer.scala:115:35] wire [256:0] fixer_SourceIdSet; // @[FIFOFixer.scala:116:36] wire [256:0] fixer_SourceIdClear; // @[FIFOFixer.scala:117:38] wire [511:0] fixer__SourceIdSet_T = 512'h1 << fixer_anonIn_a_bits_source; // @[OneHot.scala:58:35] assign fixer_SourceIdSet = fixer_a_first & fixer__a_first_T ? fixer__SourceIdSet_T[256:0] : 257'h0; // @[OneHot.scala:58:35] wire [511:0] fixer__SourceIdClear_T = 512'h1 << fixer_anonIn_d_bits_source; // @[OneHot.scala:58:35] assign fixer_SourceIdClear = fixer_d_first & fixer__T_2 ? fixer__SourceIdClear_T[256:0] : 257'h0; // @[OneHot.scala:58:35] wire [256:0] fixer__SourceIdFIFOed_T = fixer_SourceIdFIFOed \| fixer_SourceIdSet; // @[FIFOFixer.scala:115:35, :116:36, :126:40] wire fixer_allIDs_FIFOed = &fixer_SourceIdFIFOed; // @[FIFOFixer.scala:115:35, :127:41] wire buffer_1_nodeIn_a_ready; // @[MixedNode.scala:551:17] wire bus_xingOut_a_ready = buffer_1_auto_in_a_ready; // @[Buffer.scala:40:9] wire bus_xingOut_a_valid; // @[MixedNode.scala:542:17] wire buffer_1_nodeIn_a_valid = buffer_1_auto_in_a_valid; // @[Buffer.scala:40:9] wire [2:0] bus_xingOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] buffer_1_nodeIn_a_bits_opcode = buffer_1_auto_in_a_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] bus_xingOut_a_bits_param; // @[MixedNode.scala:542:17] wire [2:0] buffer_1_nodeIn_a_bits_param = buffer_1_auto_in_a_bits_param; // @[Buffer.scala:40:9] wire [3:0] bus_xingOut_a_bits_size; // @[MixedNode.scala:542:17] wire [3:0] buffer_1_nodeIn_a_bits_size = buffer_1_auto_in_a_bits_size; // @[Buffer.scala:40:9] wire [7:0] bus_xingOut_a_bits_source; // @[MixedNode.scala:542:17] wire [7:0] buffer_1_nodeIn_a_bits_source = buffer_1_auto_in_a_bits_source; // @[Buffer.scala:40:9] wire [28:0] bus_xingOut_a_bits_address; // @[MixedNode.scala:542:17] wire [28:0] buffer_1_nodeIn_a_bits_address = buffer_1_auto_in_a_bits_address; // @[Buffer.scala:40:9] wire [7:0] bus_xingOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [7:0] buffer_1_nodeIn_a_bits_mask = buffer_1_auto_in_a_bits_mask; // @[Buffer.scala:40:9] wire [63:0] bus_xingOut_a_bits_data; // @[MixedNode.scala:542:17] wire [63:0] buffer_1_nodeIn_a_bits_data = buffer_1_auto_in_a_bits_data; // @[Buffer.scala:40:9] wire bus_xingOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire buffer_1_nodeIn_a_bits_corrupt = buffer_1_auto_in_a_bits_corrupt; // @[Buffer.scala:40:9] wire bus_xingOut_d_ready; // @[MixedNode.scala:542:17] wire buffer_1_nodeIn_d_ready = buffer_1_auto_in_d_ready; // @[Buffer.scala:40:9] wire buffer_1_nodeIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] buffer_1_nodeIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire bus_xingOut_d_valid = buffer_1_auto_in_d_valid; // @[Buffer.scala:40:9] wire [1:0] buffer_1_nodeIn_d_bits_param; // @[MixedNode.scala:551:17] wire [2:0] bus_xingOut_d_bits_opcode = buffer_1_auto_in_d_bits_opcode; // @[Buffer.scala:40:9] wire [3:0] buffer_1_nodeIn_d_bits_size; // @[MixedNode.scala:551:17] wire [1:0] bus_xingOut_d_bits_param = buffer_1_auto_in_d_bits_param; // @[Buffer.scala:40:9] wire [7:0] buffer_1_nodeIn_d_bits_source; // @[MixedNode.scala:551:17] wire [3:0] bus_xingOut_d_bits_size = buffer_1_auto_in_d_bits_size; // @[Buffer.scala:40:9] wire buffer_1_nodeIn_d_bits_sink; // @[MixedNode.scala:551:17] wire [7:0] bus_xingOut_d_bits_source = buffer_1_auto_in_d_bits_source; // @[Buffer.scala:40:9] wire buffer_1_nodeIn_d_bits_denied; // @[MixedNode.scala:551:17] wire bus_xingOut_d_bits_sink = buffer_1_auto_in_d_bits_sink; // @[Buffer.scala:40:9] wire [63:0] buffer_1_nodeIn_d_bits_data; // @[MixedNode.scala:551:17] wire bus_xingOut_d_bits_denied = buffer_1_auto_in_d_bits_denied; // @[Buffer.scala:40:9] wire buffer_1_nodeIn_d_bits_corrupt; // @[MixedNode.scala:551:17] wire [63:0] bus_xingOut_d_bits_data = buffer_1_auto_in_d_bits_data; // @[Buffer.scala:40:9] wire bus_xingOut_d_bits_corrupt = buffer_1_auto_in_d_bits_corrupt; // @[Buffer.scala:40:9] wire buffer_1_nodeOut_a_ready = buffer_1_auto_out_a_ready; // @[Buffer.scala:40:9] wire buffer_1_nodeOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] buffer_1_nodeOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] buffer_1_nodeOut_a_bits_param; // @[MixedNode.scala:542:17] wire [3:0] buffer_1_nodeOut_a_bits_size; // @[MixedNode.scala:542:17] wire [7:0] buffer_1_nodeOut_a_bits_source; // @[MixedNode.scala:542:17] wire [28:0] buffer_1_nodeOut_a_bits_address; // @[MixedNode.scala:542:17] wire [7:0] buffer_1_nodeOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [63:0] buffer_1_nodeOut_a_bits_data; // @[MixedNode.scala:542:17] wire buffer_1_nodeOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire buffer_1_nodeOut_d_ready; // @[MixedNode.scala:542:17] wire buffer_1_nodeOut_d_valid = buffer_1_auto_out_d_valid; // @[Buffer.scala:40:9] wire [2:0] buffer_1_nodeOut_d_bits_opcode = buffer_1_auto_out_d_bits_opcode; // @[Buffer.scala:40:9] wire [1:0] buffer_1_nodeOut_d_bits_param = buffer_1_auto_out_d_bits_param; // @[Buffer.scala:40:9] wire [3:0] buffer_1_nodeOut_d_bits_size = buffer_1_auto_out_d_bits_size; // @[Buffer.scala:40:9] wire [7:0] buffer_1_nodeOut_d_bits_source = buffer_1_auto_out_d_bits_source; // @[Buffer.scala:40:9] wire buffer_1_nodeOut_d_bits_sink = buffer_1_auto_out_d_bits_sink; // @[Buffer.scala:40:9] wire buffer_1_nodeOut_d_bits_denied = buffer_1_auto_out_d_bits_denied; // @[Buffer.scala:40:9] wire [63:0] buffer_1_nodeOut_d_bits_data = buffer_1_auto_out_d_bits_data; // @[Buffer.scala:40:9] wire buffer_1_nodeOut_d_bits_corrupt = buffer_1_auto_out_d_bits_corrupt; // @[Buffer.scala:40:9] wire [2:0] buffer_1_auto_out_a_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] buffer_1_auto_out_a_bits_param; // @[Buffer.scala:40:9] wire [3:0] buffer_1_auto_out_a_bits_size; // @[Buffer.scala:40:9] wire [7:0] buffer_1_auto_out_a_bits_source; // @[Buffer.scala:40:9] wire [28:0] buffer_1_auto_out_a_bits_address; // @[Buffer.scala:40:9] wire [7:0] buffer_1_auto_out_a_bits_mask; // @[Buffer.scala:40:9] wire [63:0] buffer_1_auto_out_a_bits_data; // @[Buffer.scala:40:9] wire buffer_1_auto_out_a_bits_corrupt; // @[Buffer.scala:40:9] wire buffer_1_auto_out_a_valid; // @[Buffer.scala:40:9] wire buffer_1_auto_out_d_ready; // @[Buffer.scala:40:9] assign buffer_1_nodeIn_a_ready = buffer_1_nodeOut_a_ready; // @[MixedNode.scala:542:17, :551:17] assign buffer_1_auto_out_a_valid = buffer_1_nodeOut_a_valid; // @[Buffer.scala:40:9] assign buffer_1_auto_out_a_bits_opcode = buffer_1_nodeOut_a_bits_opcode; // @[Buffer.scala:40:9] assign buffer_1_auto_out_a_bits_param = buffer_1_nodeOut_a_bits_param; // @[Buffer.scala:40:9] assign buffer_1_auto_out_a_bits_size = buffer_1_nodeOut_a_bits_size; // @[Buffer.scala:40:9] assign buffer_1_auto_out_a_bits_source = buffer_1_nodeOut_a_bits_source; // @[Buffer.scala:40:9] assign buffer_1_auto_out_a_bits_address = buffer_1_nodeOut_a_bits_address; // @[Buffer.scala:40:9] assign buffer_1_auto_out_a_bits_mask = buffer_1_nodeOut_a_bits_mask; // @[Buffer.scala:40:9] assign buffer_1_auto_out_a_bits_data = buffer_1_nodeOut_a_bits_data; // @[Buffer.scala:40:9] assign buffer_1_auto_out_a_bits_corrupt = buffer_1_nodeOut_a_bits_corrupt; // @[Buffer.scala:40:9] assign buffer_1_auto_out_d_ready = buffer_1_nodeOut_d_ready; // @[Buffer.scala:40:9] assign buffer_1_nodeIn_d_valid = buffer_1_nodeOut_d_valid; // @[MixedNode.scala:542:17, :551:17] assign buffer_1_nodeIn_d_bits_opcode = buffer_1_nodeOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign buffer_1_nodeIn_d_bits_param = buffer_1_nodeOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17] assign buffer_1_nodeIn_d_bits_size = buffer_1_nodeOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17] assign buffer_1_nodeIn_d_bits_source = buffer_1_nodeOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17] assign buffer_1_nodeIn_d_bits_sink = buffer_1_nodeOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17] assign buffer_1_nodeIn_d_bits_denied = buffer_1_nodeOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17] assign buffer_1_nodeIn_d_bits_data = buffer_1_nodeOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17] assign buffer_1_nodeIn_d_bits_corrupt = buffer_1_nodeOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign buffer_1_auto_in_a_ready = buffer_1_nodeIn_a_ready; // @[Buffer.scala:40:9] assign buffer_1_nodeOut_a_valid = buffer_1_nodeIn_a_valid; // @[MixedNode.scala:542:17, :551:17] assign buffer_1_nodeOut_a_bits_opcode = buffer_1_nodeIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign buffer_1_nodeOut_a_bits_param = buffer_1_nodeIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17] assign buffer_1_nodeOut_a_bits_size = buffer_1_nodeIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17] assign buffer_1_nodeOut_a_bits_source = buffer_1_nodeIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17] assign buffer_1_nodeOut_a_bits_address = buffer_1_nodeIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17] assign buffer_1_nodeOut_a_bits_mask = buffer_1_nodeIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign buffer_1_nodeOut_a_bits_data = buffer_1_nodeIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17] assign buffer_1_nodeOut_a_bits_corrupt = buffer_1_nodeIn_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign buffer_1_nodeOut_d_ready = buffer_1_nodeIn_d_ready; // @[MixedNode.scala:542:17, :551:17] assign buffer_1_auto_in_d_valid = buffer_1_nodeIn_d_valid; // @[Buffer.scala:40:9] assign buffer_1_auto_in_d_bits_opcode = buffer_1_nodeIn_d_bits_opcode; // @[Buffer.scala:40:9] assign buffer_1_auto_in_d_bits_param = buffer_1_nodeIn_d_bits_param; // @[Buffer.scala:40:9] assign buffer_1_auto_in_d_bits_size = buffer_1_nodeIn_d_bits_size; // @[Buffer.scala:40:9] assign buffer_1_auto_in_d_bits_source = buffer_1_nodeIn_d_bits_source; // @[Buffer.scala:40:9] assign buffer_1_auto_in_d_bits_sink = buffer_1_nodeIn_d_bits_sink; // @[Buffer.scala:40:9] assign buffer_1_auto_in_d_bits_denied = buffer_1_nodeIn_d_bits_denied; // @[Buffer.scala:40:9] assign buffer_1_auto_in_d_bits_data = buffer_1_nodeIn_d_bits_data; // @[Buffer.scala:40:9] assign buffer_1_auto_in_d_bits_corrupt = buffer_1_nodeIn_d_bits_corrupt; // @[Buffer.scala:40:9] wire coupler_to_bus_named_pbus_widget_auto_anon_in_a_ready; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_pbus_widget_auto_anon_in_a_valid = coupler_to_bus_named_pbus_auto_widget_anon_in_a_valid; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_pbus_widget_auto_anon_in_a_bits_opcode = coupler_to_bus_named_pbus_auto_widget_anon_in_a_bits_opcode; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_pbus_widget_auto_anon_in_a_bits_param = coupler_to_bus_named_pbus_auto_widget_anon_in_a_bits_param; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_pbus_widget_auto_anon_in_a_bits_size = coupler_to_bus_named_pbus_auto_widget_anon_in_a_bits_size; // @[WidthWidget.scala:27:9] wire [8:0] coupler_to_bus_named_pbus_widget_auto_anon_in_a_bits_source = coupler_to_bus_named_pbus_auto_widget_anon_in_a_bits_source; // @[WidthWidget.scala:27:9] wire [28:0] coupler_to_bus_named_pbus_widget_auto_anon_in_a_bits_address = coupler_to_bus_named_pbus_auto_widget_anon_in_a_bits_address; // @[WidthWidget.scala:27:9] wire [7:0] coupler_to_bus_named_pbus_widget_auto_anon_in_a_bits_mask = coupler_to_bus_named_pbus_auto_widget_anon_in_a_bits_mask; // @[WidthWidget.scala:27:9] wire [63:0] coupler_to_bus_named_pbus_widget_auto_anon_in_a_bits_data = coupler_to_bus_named_pbus_auto_widget_anon_in_a_bits_data; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_pbus_widget_auto_anon_in_a_bits_corrupt = coupler_to_bus_named_pbus_auto_widget_anon_in_a_bits_corrupt; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_pbus_widget_auto_anon_in_d_ready = coupler_to_bus_named_pbus_auto_widget_anon_in_d_ready; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_pbus_widget_auto_anon_in_d_valid; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_pbus_widget_auto_anon_in_d_bits_opcode; // @[WidthWidget.scala:27:9] wire [1:0] coupler_to_bus_named_pbus_widget_auto_anon_in_d_bits_param; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_pbus_widget_auto_anon_in_d_bits_size; // @[WidthWidget.scala:27:9] wire [8:0] coupler_to_bus_named_pbus_widget_auto_anon_in_d_bits_source; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_pbus_widget_auto_anon_in_d_bits_sink; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_pbus_widget_auto_anon_in_d_bits_denied; // @[WidthWidget.scala:27:9] wire [63:0] coupler_to_bus_named_pbus_widget_auto_anon_in_d_bits_data; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_pbus_widget_auto_anon_in_d_bits_corrupt; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_pbus_bus_xingOut_a_ready = coupler_to_bus_named_pbus_auto_bus_xing_out_a_ready; // @[MixedNode.scala:542:17] wire coupler_to_bus_named_pbus_bus_xingOut_a_valid; // @[MixedNode.scala:542:17] assign auto_coupler_to_bus_named_pbus_bus_xing_out_a_valid_0 = coupler_to_bus_named_pbus_auto_bus_xing_out_a_valid; // @[ClockDomain.scala:14:9] wire [2:0] coupler_to_bus_named_pbus_bus_xingOut_a_bits_opcode; // @[MixedNode.scala:542:17] assign auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_opcode_0 = coupler_to_bus_named_pbus_auto_bus_xing_out_a_bits_opcode; // @[ClockDomain.scala:14:9] wire [2:0] coupler_to_bus_named_pbus_bus_xingOut_a_bits_param; // @[MixedNode.scala:542:17] assign auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_param_0 = coupler_to_bus_named_pbus_auto_bus_xing_out_a_bits_param; // @[ClockDomain.scala:14:9] wire [2:0] coupler_to_bus_named_pbus_bus_xingOut_a_bits_size; // @[MixedNode.scala:542:17] assign auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_size_0 = coupler_to_bus_named_pbus_auto_bus_xing_out_a_bits_size; // @[ClockDomain.scala:14:9] wire [8:0] coupler_to_bus_named_pbus_bus_xingOut_a_bits_source; // @[MixedNode.scala:542:17] assign auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_source_0 = coupler_to_bus_named_pbus_auto_bus_xing_out_a_bits_source; // @[ClockDomain.scala:14:9] wire [28:0] coupler_to_bus_named_pbus_bus_xingOut_a_bits_address; // @[MixedNode.scala:542:17] assign auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_address_0 = coupler_to_bus_named_pbus_auto_bus_xing_out_a_bits_address; // @[ClockDomain.scala:14:9] wire [7:0] coupler_to_bus_named_pbus_bus_xingOut_a_bits_mask; // @[MixedNode.scala:542:17] assign auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_mask_0 = coupler_to_bus_named_pbus_auto_bus_xing_out_a_bits_mask; // @[ClockDomain.scala:14:9] wire [63:0] coupler_to_bus_named_pbus_bus_xingOut_a_bits_data; // @[MixedNode.scala:542:17] assign auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_data_0 = coupler_to_bus_named_pbus_auto_bus_xing_out_a_bits_data; // @[ClockDomain.scala:14:9] wire coupler_to_bus_named_pbus_bus_xingOut_a_bits_corrupt; // @[MixedNode.scala:542:17] assign auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_corrupt_0 = coupler_to_bus_named_pbus_auto_bus_xing_out_a_bits_corrupt; // @[ClockDomain.scala:14:9] wire coupler_to_bus_named_pbus_bus_xingOut_d_ready; // @[MixedNode.scala:542:17] assign auto_coupler_to_bus_named_pbus_bus_xing_out_d_ready_0 = coupler_to_bus_named_pbus_auto_bus_xing_out_d_ready; // @[ClockDomain.scala:14:9] wire coupler_to_bus_named_pbus_bus_xingOut_d_valid = coupler_to_bus_named_pbus_auto_bus_xing_out_d_valid; // @[MixedNode.scala:542:17] wire [2:0] coupler_to_bus_named_pbus_bus_xingOut_d_bits_opcode = coupler_to_bus_named_pbus_auto_bus_xing_out_d_bits_opcode; // @[MixedNode.scala:542:17] wire [1:0] coupler_to_bus_named_pbus_bus_xingOut_d_bits_param = coupler_to_bus_named_pbus_auto_bus_xing_out_d_bits_param; // @[MixedNode.scala:542:17] wire [2:0] coupler_to_bus_named_pbus_bus_xingOut_d_bits_size = coupler_to_bus_named_pbus_auto_bus_xing_out_d_bits_size; // @[MixedNode.scala:542:17] wire [8:0] coupler_to_bus_named_pbus_bus_xingOut_d_bits_source = coupler_to_bus_named_pbus_auto_bus_xing_out_d_bits_source; // @[MixedNode.scala:542:17] wire coupler_to_bus_named_pbus_bus_xingOut_d_bits_sink = coupler_to_bus_named_pbus_auto_bus_xing_out_d_bits_sink; // @[MixedNode.scala:542:17] wire coupler_to_bus_named_pbus_bus_xingOut_d_bits_denied = coupler_to_bus_named_pbus_auto_bus_xing_out_d_bits_denied; // @[MixedNode.scala:542:17] wire [63:0] coupler_to_bus_named_pbus_bus_xingOut_d_bits_data = coupler_to_bus_named_pbus_auto_bus_xing_out_d_bits_data; // @[MixedNode.scala:542:17] wire coupler_to_bus_named_pbus_bus_xingOut_d_bits_corrupt = coupler_to_bus_named_pbus_auto_bus_xing_out_d_bits_corrupt; // @[MixedNode.scala:542:17] wire coupler_to_bus_named_pbus_auto_widget_anon_in_a_ready; // @[LazyModuleImp.scala:138:7] wire [2:0] coupler_to_bus_named_pbus_auto_widget_anon_in_d_bits_opcode; // @[LazyModuleImp.scala:138:7] wire [1:0] coupler_to_bus_named_pbus_auto_widget_anon_in_d_bits_param; // @[LazyModuleImp.scala:138:7] wire [2:0] coupler_to_bus_named_pbus_auto_widget_anon_in_d_bits_size; // @[LazyModuleImp.scala:138:7] wire [8:0] coupler_to_bus_named_pbus_auto_widget_anon_in_d_bits_source; // @[LazyModuleImp.scala:138:7] wire coupler_to_bus_named_pbus_auto_widget_anon_in_d_bits_sink; // @[LazyModuleImp.scala:138:7] wire coupler_to_bus_named_pbus_auto_widget_anon_in_d_bits_denied; // @[LazyModuleImp.scala:138:7] wire [63:0] coupler_to_bus_named_pbus_auto_widget_anon_in_d_bits_data; // @[LazyModuleImp.scala:138:7] wire coupler_to_bus_named_pbus_auto_widget_anon_in_d_bits_corrupt; // @[LazyModuleImp.scala:138:7] wire coupler_to_bus_named_pbus_auto_widget_anon_in_d_valid; // @[LazyModuleImp.scala:138:7] wire coupler_to_bus_named_pbus_widget_anonIn_a_ready; // @[MixedNode.scala:551:17] assign coupler_to_bus_named_pbus_auto_widget_anon_in_a_ready = coupler_to_bus_named_pbus_widget_auto_anon_in_a_ready; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_pbus_widget_anonIn_a_valid = coupler_to_bus_named_pbus_widget_auto_anon_in_a_valid; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_pbus_widget_anonIn_a_bits_opcode = coupler_to_bus_named_pbus_widget_auto_anon_in_a_bits_opcode; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_pbus_widget_anonIn_a_bits_param = coupler_to_bus_named_pbus_widget_auto_anon_in_a_bits_param; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_pbus_widget_anonIn_a_bits_size = coupler_to_bus_named_pbus_widget_auto_anon_in_a_bits_size; // @[WidthWidget.scala:27:9] wire [8:0] coupler_to_bus_named_pbus_widget_anonIn_a_bits_source = coupler_to_bus_named_pbus_widget_auto_anon_in_a_bits_source; // @[WidthWidget.scala:27:9] wire [28:0] coupler_to_bus_named_pbus_widget_anonIn_a_bits_address = coupler_to_bus_named_pbus_widget_auto_anon_in_a_bits_address; // @[WidthWidget.scala:27:9] wire [7:0] coupler_to_bus_named_pbus_widget_anonIn_a_bits_mask = coupler_to_bus_named_pbus_widget_auto_anon_in_a_bits_mask; // @[WidthWidget.scala:27:9] wire [63:0] coupler_to_bus_named_pbus_widget_anonIn_a_bits_data = coupler_to_bus_named_pbus_widget_auto_anon_in_a_bits_data; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_pbus_widget_anonIn_a_bits_corrupt = coupler_to_bus_named_pbus_widget_auto_anon_in_a_bits_corrupt; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_pbus_widget_anonIn_d_ready = coupler_to_bus_named_pbus_widget_auto_anon_in_d_ready; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_pbus_widget_anonIn_d_valid; // @[MixedNode.scala:551:17] assign coupler_to_bus_named_pbus_auto_widget_anon_in_d_valid = coupler_to_bus_named_pbus_widget_auto_anon_in_d_valid; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_pbus_widget_anonIn_d_bits_opcode; // @[MixedNode.scala:551:17] assign coupler_to_bus_named_pbus_auto_widget_anon_in_d_bits_opcode = coupler_to_bus_named_pbus_widget_auto_anon_in_d_bits_opcode; // @[WidthWidget.scala:27:9] wire [1:0] coupler_to_bus_named_pbus_widget_anonIn_d_bits_param; // @[MixedNode.scala:551:17] assign coupler_to_bus_named_pbus_auto_widget_anon_in_d_bits_param = coupler_to_bus_named_pbus_widget_auto_anon_in_d_bits_param; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_pbus_widget_anonIn_d_bits_size; // @[MixedNode.scala:551:17] assign coupler_to_bus_named_pbus_auto_widget_anon_in_d_bits_size = coupler_to_bus_named_pbus_widget_auto_anon_in_d_bits_size; // @[WidthWidget.scala:27:9] wire [8:0] coupler_to_bus_named_pbus_widget_anonIn_d_bits_source; // @[MixedNode.scala:551:17] assign coupler_to_bus_named_pbus_auto_widget_anon_in_d_bits_source = coupler_to_bus_named_pbus_widget_auto_anon_in_d_bits_source; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_pbus_widget_anonIn_d_bits_sink; // @[MixedNode.scala:551:17] assign coupler_to_bus_named_pbus_auto_widget_anon_in_d_bits_sink = coupler_to_bus_named_pbus_widget_auto_anon_in_d_bits_sink; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_pbus_widget_anonIn_d_bits_denied; // @[MixedNode.scala:551:17] assign coupler_to_bus_named_pbus_auto_widget_anon_in_d_bits_denied = coupler_to_bus_named_pbus_widget_auto_anon_in_d_bits_denied; // @[WidthWidget.scala:27:9] wire [63:0] coupler_to_bus_named_pbus_widget_anonIn_d_bits_data; // @[MixedNode.scala:551:17] assign coupler_to_bus_named_pbus_auto_widget_anon_in_d_bits_data = coupler_to_bus_named_pbus_widget_auto_anon_in_d_bits_data; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_pbus_widget_anonIn_d_bits_corrupt; // @[MixedNode.scala:551:17] assign coupler_to_bus_named_pbus_auto_widget_anon_in_d_bits_corrupt = coupler_to_bus_named_pbus_widget_auto_anon_in_d_bits_corrupt; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_pbus_bus_xingIn_a_ready; // @[MixedNode.scala:551:17] wire coupler_to_bus_named_pbus_widget_anonOut_a_ready = coupler_to_bus_named_pbus_widget_auto_anon_out_a_ready; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_pbus_widget_anonOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] coupler_to_bus_named_pbus_widget_anonOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire coupler_to_bus_named_pbus_bus_xingIn_a_valid = coupler_to_bus_named_pbus_widget_auto_anon_out_a_valid; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_pbus_widget_anonOut_a_bits_param; // @[MixedNode.scala:542:17] wire [2:0] coupler_to_bus_named_pbus_bus_xingIn_a_bits_opcode = coupler_to_bus_named_pbus_widget_auto_anon_out_a_bits_opcode; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_pbus_widget_anonOut_a_bits_size; // @[MixedNode.scala:542:17] wire [2:0] coupler_to_bus_named_pbus_bus_xingIn_a_bits_param = coupler_to_bus_named_pbus_widget_auto_anon_out_a_bits_param; // @[WidthWidget.scala:27:9] wire [8:0] coupler_to_bus_named_pbus_widget_anonOut_a_bits_source; // @[MixedNode.scala:542:17] wire [2:0] coupler_to_bus_named_pbus_bus_xingIn_a_bits_size = coupler_to_bus_named_pbus_widget_auto_anon_out_a_bits_size; // @[WidthWidget.scala:27:9] wire [28:0] coupler_to_bus_named_pbus_widget_anonOut_a_bits_address; // @[MixedNode.scala:542:17] wire [8:0] coupler_to_bus_named_pbus_bus_xingIn_a_bits_source = coupler_to_bus_named_pbus_widget_auto_anon_out_a_bits_source; // @[WidthWidget.scala:27:9] wire [7:0] coupler_to_bus_named_pbus_widget_anonOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [28:0] coupler_to_bus_named_pbus_bus_xingIn_a_bits_address = coupler_to_bus_named_pbus_widget_auto_anon_out_a_bits_address; // @[WidthWidget.scala:27:9] wire [63:0] coupler_to_bus_named_pbus_widget_anonOut_a_bits_data; // @[MixedNode.scala:542:17] wire [7:0] coupler_to_bus_named_pbus_bus_xingIn_a_bits_mask = coupler_to_bus_named_pbus_widget_auto_anon_out_a_bits_mask; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_pbus_widget_anonOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire [63:0] coupler_to_bus_named_pbus_bus_xingIn_a_bits_data = coupler_to_bus_named_pbus_widget_auto_anon_out_a_bits_data; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_pbus_widget_anonOut_d_ready; // @[MixedNode.scala:542:17] wire coupler_to_bus_named_pbus_bus_xingIn_a_bits_corrupt = coupler_to_bus_named_pbus_widget_auto_anon_out_a_bits_corrupt; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_pbus_bus_xingIn_d_ready = coupler_to_bus_named_pbus_widget_auto_anon_out_d_ready; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_pbus_bus_xingIn_d_valid; // @[MixedNode.scala:551:17] wire coupler_to_bus_named_pbus_widget_anonOut_d_valid = coupler_to_bus_named_pbus_widget_auto_anon_out_d_valid; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_pbus_bus_xingIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [2:0] coupler_to_bus_named_pbus_widget_anonOut_d_bits_opcode = coupler_to_bus_named_pbus_widget_auto_anon_out_d_bits_opcode; // @[WidthWidget.scala:27:9] wire [1:0] coupler_to_bus_named_pbus_bus_xingIn_d_bits_param; // @[MixedNode.scala:551:17] wire [1:0] coupler_to_bus_named_pbus_widget_anonOut_d_bits_param = coupler_to_bus_named_pbus_widget_auto_anon_out_d_bits_param; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_pbus_bus_xingIn_d_bits_size; // @[MixedNode.scala:551:17] wire [2:0] coupler_to_bus_named_pbus_widget_anonOut_d_bits_size = coupler_to_bus_named_pbus_widget_auto_anon_out_d_bits_size; // @[WidthWidget.scala:27:9] wire [8:0] coupler_to_bus_named_pbus_bus_xingIn_d_bits_source; // @[MixedNode.scala:551:17] wire [8:0] coupler_to_bus_named_pbus_widget_anonOut_d_bits_source = coupler_to_bus_named_pbus_widget_auto_anon_out_d_bits_source; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_pbus_bus_xingIn_d_bits_sink; // @[MixedNode.scala:551:17] wire coupler_to_bus_named_pbus_widget_anonOut_d_bits_sink = coupler_to_bus_named_pbus_widget_auto_anon_out_d_bits_sink; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_pbus_bus_xingIn_d_bits_denied; // @[MixedNode.scala:551:17] wire coupler_to_bus_named_pbus_widget_anonOut_d_bits_denied = coupler_to_bus_named_pbus_widget_auto_anon_out_d_bits_denied; // @[WidthWidget.scala:27:9] wire [63:0] coupler_to_bus_named_pbus_bus_xingIn_d_bits_data; // @[MixedNode.scala:551:17] wire [63:0] coupler_to_bus_named_pbus_widget_anonOut_d_bits_data = coupler_to_bus_named_pbus_widget_auto_anon_out_d_bits_data; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_pbus_bus_xingIn_d_bits_corrupt; // @[MixedNode.scala:551:17] wire coupler_to_bus_named_pbus_widget_anonOut_d_bits_corrupt = coupler_to_bus_named_pbus_widget_auto_anon_out_d_bits_corrupt; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_pbus_widget_anonIn_a_ready = coupler_to_bus_named_pbus_widget_anonOut_a_ready; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_pbus_widget_auto_anon_out_a_valid = coupler_to_bus_named_pbus_widget_anonOut_a_valid; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_pbus_widget_auto_anon_out_a_bits_opcode = coupler_to_bus_named_pbus_widget_anonOut_a_bits_opcode; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_pbus_widget_auto_anon_out_a_bits_param = coupler_to_bus_named_pbus_widget_anonOut_a_bits_param; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_pbus_widget_auto_anon_out_a_bits_size = coupler_to_bus_named_pbus_widget_anonOut_a_bits_size; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_pbus_widget_auto_anon_out_a_bits_source = coupler_to_bus_named_pbus_widget_anonOut_a_bits_source; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_pbus_widget_auto_anon_out_a_bits_address = coupler_to_bus_named_pbus_widget_anonOut_a_bits_address; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_pbus_widget_auto_anon_out_a_bits_mask = coupler_to_bus_named_pbus_widget_anonOut_a_bits_mask; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_pbus_widget_auto_anon_out_a_bits_data = coupler_to_bus_named_pbus_widget_anonOut_a_bits_data; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_pbus_widget_auto_anon_out_a_bits_corrupt = coupler_to_bus_named_pbus_widget_anonOut_a_bits_corrupt; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_pbus_widget_auto_anon_out_d_ready = coupler_to_bus_named_pbus_widget_anonOut_d_ready; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_pbus_widget_anonIn_d_valid = coupler_to_bus_named_pbus_widget_anonOut_d_valid; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_pbus_widget_anonIn_d_bits_opcode = coupler_to_bus_named_pbus_widget_anonOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_pbus_widget_anonIn_d_bits_param = coupler_to_bus_named_pbus_widget_anonOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_pbus_widget_anonIn_d_bits_size = coupler_to_bus_named_pbus_widget_anonOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_pbus_widget_anonIn_d_bits_source = coupler_to_bus_named_pbus_widget_anonOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_pbus_widget_anonIn_d_bits_sink = coupler_to_bus_named_pbus_widget_anonOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_pbus_widget_anonIn_d_bits_denied = coupler_to_bus_named_pbus_widget_anonOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_pbus_widget_anonIn_d_bits_data = coupler_to_bus_named_pbus_widget_anonOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_pbus_widget_anonIn_d_bits_corrupt = coupler_to_bus_named_pbus_widget_anonOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_pbus_widget_auto_anon_in_a_ready = coupler_to_bus_named_pbus_widget_anonIn_a_ready; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_pbus_widget_anonOut_a_valid = coupler_to_bus_named_pbus_widget_anonIn_a_valid; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_pbus_widget_anonOut_a_bits_opcode = coupler_to_bus_named_pbus_widget_anonIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_pbus_widget_anonOut_a_bits_param = coupler_to_bus_named_pbus_widget_anonIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_pbus_widget_anonOut_a_bits_size = coupler_to_bus_named_pbus_widget_anonIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_pbus_widget_anonOut_a_bits_source = coupler_to_bus_named_pbus_widget_anonIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_pbus_widget_anonOut_a_bits_address = coupler_to_bus_named_pbus_widget_anonIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_pbus_widget_anonOut_a_bits_mask = coupler_to_bus_named_pbus_widget_anonIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_pbus_widget_anonOut_a_bits_data = coupler_to_bus_named_pbus_widget_anonIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_pbus_widget_anonOut_a_bits_corrupt = coupler_to_bus_named_pbus_widget_anonIn_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_pbus_widget_anonOut_d_ready = coupler_to_bus_named_pbus_widget_anonIn_d_ready; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_pbus_widget_auto_anon_in_d_valid = coupler_to_bus_named_pbus_widget_anonIn_d_valid; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_pbus_widget_auto_anon_in_d_bits_opcode = coupler_to_bus_named_pbus_widget_anonIn_d_bits_opcode; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_pbus_widget_auto_anon_in_d_bits_param = coupler_to_bus_named_pbus_widget_anonIn_d_bits_param; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_pbus_widget_auto_anon_in_d_bits_size = coupler_to_bus_named_pbus_widget_anonIn_d_bits_size; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_pbus_widget_auto_anon_in_d_bits_source = coupler_to_bus_named_pbus_widget_anonIn_d_bits_source; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_pbus_widget_auto_anon_in_d_bits_sink = coupler_to_bus_named_pbus_widget_anonIn_d_bits_sink; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_pbus_widget_auto_anon_in_d_bits_denied = coupler_to_bus_named_pbus_widget_anonIn_d_bits_denied; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_pbus_widget_auto_anon_in_d_bits_data = coupler_to_bus_named_pbus_widget_anonIn_d_bits_data; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_pbus_widget_auto_anon_in_d_bits_corrupt = coupler_to_bus_named_pbus_widget_anonIn_d_bits_corrupt; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_pbus_bus_xingIn_a_ready = coupler_to_bus_named_pbus_bus_xingOut_a_ready; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_pbus_auto_bus_xing_out_a_valid = coupler_to_bus_named_pbus_bus_xingOut_a_valid; // @[MixedNode.scala:542:17] assign coupler_to_bus_named_pbus_auto_bus_xing_out_a_bits_opcode = coupler_to_bus_named_pbus_bus_xingOut_a_bits_opcode; // @[MixedNode.scala:542:17] assign coupler_to_bus_named_pbus_auto_bus_xing_out_a_bits_param = coupler_to_bus_named_pbus_bus_xingOut_a_bits_param; // @[MixedNode.scala:542:17] assign coupler_to_bus_named_pbus_auto_bus_xing_out_a_bits_size = coupler_to_bus_named_pbus_bus_xingOut_a_bits_size; // @[MixedNode.scala:542:17] assign coupler_to_bus_named_pbus_auto_bus_xing_out_a_bits_source = coupler_to_bus_named_pbus_bus_xingOut_a_bits_source; // @[MixedNode.scala:542:17] assign coupler_to_bus_named_pbus_auto_bus_xing_out_a_bits_address = coupler_to_bus_named_pbus_bus_xingOut_a_bits_address; // @[MixedNode.scala:542:17] assign coupler_to_bus_named_pbus_auto_bus_xing_out_a_bits_mask = coupler_to_bus_named_pbus_bus_xingOut_a_bits_mask; // @[MixedNode.scala:542:17] assign coupler_to_bus_named_pbus_auto_bus_xing_out_a_bits_data = coupler_to_bus_named_pbus_bus_xingOut_a_bits_data; // @[MixedNode.scala:542:17] assign coupler_to_bus_named_pbus_auto_bus_xing_out_a_bits_corrupt = coupler_to_bus_named_pbus_bus_xingOut_a_bits_corrupt; // @[MixedNode.scala:542:17] assign coupler_to_bus_named_pbus_auto_bus_xing_out_d_ready = coupler_to_bus_named_pbus_bus_xingOut_d_ready; // @[MixedNode.scala:542:17] assign coupler_to_bus_named_pbus_bus_xingIn_d_valid = coupler_to_bus_named_pbus_bus_xingOut_d_valid; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_pbus_bus_xingIn_d_bits_opcode = coupler_to_bus_named_pbus_bus_xingOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_pbus_bus_xingIn_d_bits_param = coupler_to_bus_named_pbus_bus_xingOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_pbus_bus_xingIn_d_bits_size = coupler_to_bus_named_pbus_bus_xingOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_pbus_bus_xingIn_d_bits_source = coupler_to_bus_named_pbus_bus_xingOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_pbus_bus_xingIn_d_bits_sink = coupler_to_bus_named_pbus_bus_xingOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_pbus_bus_xingIn_d_bits_denied = coupler_to_bus_named_pbus_bus_xingOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_pbus_bus_xingIn_d_bits_data = coupler_to_bus_named_pbus_bus_xingOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_pbus_bus_xingIn_d_bits_corrupt = coupler_to_bus_named_pbus_bus_xingOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_pbus_widget_auto_anon_out_a_ready = coupler_to_bus_named_pbus_bus_xingIn_a_ready; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_pbus_bus_xingOut_a_valid = coupler_to_bus_named_pbus_bus_xingIn_a_valid; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_pbus_bus_xingOut_a_bits_opcode = coupler_to_bus_named_pbus_bus_xingIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_pbus_bus_xingOut_a_bits_param = coupler_to_bus_named_pbus_bus_xingIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_pbus_bus_xingOut_a_bits_size = coupler_to_bus_named_pbus_bus_xingIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_pbus_bus_xingOut_a_bits_source = coupler_to_bus_named_pbus_bus_xingIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_pbus_bus_xingOut_a_bits_address = coupler_to_bus_named_pbus_bus_xingIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_pbus_bus_xingOut_a_bits_mask = coupler_to_bus_named_pbus_bus_xingIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_pbus_bus_xingOut_a_bits_data = coupler_to_bus_named_pbus_bus_xingIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_pbus_bus_xingOut_a_bits_corrupt = coupler_to_bus_named_pbus_bus_xingIn_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_pbus_bus_xingOut_d_ready = coupler_to_bus_named_pbus_bus_xingIn_d_ready; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_pbus_widget_auto_anon_out_d_valid = coupler_to_bus_named_pbus_bus_xingIn_d_valid; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_pbus_widget_auto_anon_out_d_bits_opcode = coupler_to_bus_named_pbus_bus_xingIn_d_bits_opcode; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_pbus_widget_auto_anon_out_d_bits_param = coupler_to_bus_named_pbus_bus_xingIn_d_bits_param; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_pbus_widget_auto_anon_out_d_bits_size = coupler_to_bus_named_pbus_bus_xingIn_d_bits_size; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_pbus_widget_auto_anon_out_d_bits_source = coupler_to_bus_named_pbus_bus_xingIn_d_bits_source; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_pbus_widget_auto_anon_out_d_bits_sink = coupler_to_bus_named_pbus_bus_xingIn_d_bits_sink; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_pbus_widget_auto_anon_out_d_bits_denied = coupler_to_bus_named_pbus_bus_xingIn_d_bits_denied; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_pbus_widget_auto_anon_out_d_bits_data = coupler_to_bus_named_pbus_bus_xingIn_d_bits_data; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_pbus_widget_auto_anon_out_d_bits_corrupt = coupler_to_bus_named_pbus_bus_xingIn_d_bits_corrupt; // @[WidthWidget.scala:27:9] wire coupler_from_port_named_custom_boot_pin_tlIn_a_ready; // @[MixedNode.scala:551:17] wire nodeOut_a_ready = coupler_from_port_named_custom_boot_pin_auto_tl_in_a_ready; // @[MixedNode.scala:542:17] wire nodeOut_a_valid; // @[MixedNode.scala:542:17] wire coupler_from_port_named_custom_boot_pin_tlIn_a_valid = coupler_from_port_named_custom_boot_pin_auto_tl_in_a_valid; // @[MixedNode.scala:551:17] wire [28:0] nodeOut_a_bits_address; // @[MixedNode.scala:542:17] wire [28:0] coupler_from_port_named_custom_boot_pin_tlIn_a_bits_address = coupler_from_port_named_custom_boot_pin_auto_tl_in_a_bits_address; // @[MixedNode.scala:551:17] wire [63:0] nodeOut_a_bits_data; // @[MixedNode.scala:542:17] wire [63:0] coupler_from_port_named_custom_boot_pin_tlIn_a_bits_data = coupler_from_port_named_custom_boot_pin_auto_tl_in_a_bits_data; // @[MixedNode.scala:551:17] wire coupler_from_port_named_custom_boot_pin_tlIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] coupler_from_port_named_custom_boot_pin_tlIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire nodeOut_d_valid = coupler_from_port_named_custom_boot_pin_auto_tl_in_d_valid; // @[MixedNode.scala:542:17] wire [1:0] coupler_from_port_named_custom_boot_pin_tlIn_d_bits_param; // @[MixedNode.scala:551:17] wire [2:0] nodeOut_d_bits_opcode = coupler_from_port_named_custom_boot_pin_auto_tl_in_d_bits_opcode; // @[MixedNode.scala:542:17] wire [3:0] coupler_from_port_named_custom_boot_pin_tlIn_d_bits_size; // @[MixedNode.scala:551:17] wire [1:0] nodeOut_d_bits_param = coupler_from_port_named_custom_boot_pin_auto_tl_in_d_bits_param; // @[MixedNode.scala:542:17] wire [3:0] nodeOut_d_bits_size = coupler_from_port_named_custom_boot_pin_auto_tl_in_d_bits_size; // @[MixedNode.scala:542:17] wire coupler_from_port_named_custom_boot_pin_tlIn_d_bits_sink; // @[MixedNode.scala:551:17] wire coupler_from_port_named_custom_boot_pin_tlIn_d_bits_denied; // @[MixedNode.scala:551:17] wire nodeOut_d_bits_sink = coupler_from_port_named_custom_boot_pin_auto_tl_in_d_bits_sink; // @[MixedNode.scala:542:17] wire [63:0] coupler_from_port_named_custom_boot_pin_tlIn_d_bits_data; // @[MixedNode.scala:551:17] wire nodeOut_d_bits_denied = coupler_from_port_named_custom_boot_pin_auto_tl_in_d_bits_denied; // @[MixedNode.scala:542:17] wire coupler_from_port_named_custom_boot_pin_tlIn_d_bits_corrupt; // @[MixedNode.scala:551:17] wire [63:0] nodeOut_d_bits_data = coupler_from_port_named_custom_boot_pin_auto_tl_in_d_bits_data; // @[MixedNode.scala:542:17] wire nodeOut_d_bits_corrupt = coupler_from_port_named_custom_boot_pin_auto_tl_in_d_bits_corrupt; // @[MixedNode.scala:542:17] wire coupler_from_port_named_custom_boot_pin_tlOut_a_ready = coupler_from_port_named_custom_boot_pin_auto_tl_out_a_ready; // @[MixedNode.scala:542:17] wire coupler_from_port_named_custom_boot_pin_tlOut_a_valid; // @[MixedNode.scala:542:17] wire [28:0] coupler_from_port_named_custom_boot_pin_tlOut_a_bits_address; // @[MixedNode.scala:542:17] wire [63:0] coupler_from_port_named_custom_boot_pin_tlOut_a_bits_data; // @[MixedNode.scala:542:17] wire coupler_from_port_named_custom_boot_pin_tlOut_d_valid = coupler_from_port_named_custom_boot_pin_auto_tl_out_d_valid; // @[MixedNode.scala:542:17] wire [2:0] coupler_from_port_named_custom_boot_pin_tlOut_d_bits_opcode = coupler_from_port_named_custom_boot_pin_auto_tl_out_d_bits_opcode; // @[MixedNode.scala:542:17] wire [1:0] coupler_from_port_named_custom_boot_pin_tlOut_d_bits_param = coupler_from_port_named_custom_boot_pin_auto_tl_out_d_bits_param; // @[MixedNode.scala:542:17] wire [3:0] coupler_from_port_named_custom_boot_pin_tlOut_d_bits_size = coupler_from_port_named_custom_boot_pin_auto_tl_out_d_bits_size; // @[MixedNode.scala:542:17] wire coupler_from_port_named_custom_boot_pin_tlOut_d_bits_sink = coupler_from_port_named_custom_boot_pin_auto_tl_out_d_bits_sink; // @[MixedNode.scala:542:17] wire coupler_from_port_named_custom_boot_pin_tlOut_d_bits_denied = coupler_from_port_named_custom_boot_pin_auto_tl_out_d_bits_denied; // @[MixedNode.scala:542:17] wire [63:0] coupler_from_port_named_custom_boot_pin_tlOut_d_bits_data = coupler_from_port_named_custom_boot_pin_auto_tl_out_d_bits_data; // @[MixedNode.scala:542:17] wire coupler_from_port_named_custom_boot_pin_tlOut_d_bits_corrupt = coupler_from_port_named_custom_boot_pin_auto_tl_out_d_bits_corrupt; // @[MixedNode.scala:542:17] wire [28:0] coupler_from_port_named_custom_boot_pin_auto_tl_out_a_bits_address; // @[LazyModuleImp.scala:138:7] wire [63:0] coupler_from_port_named_custom_boot_pin_auto_tl_out_a_bits_data; // @[LazyModuleImp.scala:138:7] wire coupler_from_port_named_custom_boot_pin_auto_tl_out_a_valid; // @[LazyModuleImp.scala:138:7] assign coupler_from_port_named_custom_boot_pin_tlIn_a_ready = coupler_from_port_named_custom_boot_pin_tlOut_a_ready; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_port_named_custom_boot_pin_auto_tl_out_a_valid = coupler_from_port_named_custom_boot_pin_tlOut_a_valid; // @[MixedNode.scala:542:17] assign coupler_from_port_named_custom_boot_pin_auto_tl_out_a_bits_address = coupler_from_port_named_custom_boot_pin_tlOut_a_bits_address; // @[MixedNode.scala:542:17] assign coupler_from_port_named_custom_boot_pin_auto_tl_out_a_bits_data = coupler_from_port_named_custom_boot_pin_tlOut_a_bits_data; // @[MixedNode.scala:542:17] assign coupler_from_port_named_custom_boot_pin_tlIn_d_valid = coupler_from_port_named_custom_boot_pin_tlOut_d_valid; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_port_named_custom_boot_pin_tlIn_d_bits_opcode = coupler_from_port_named_custom_boot_pin_tlOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_port_named_custom_boot_pin_tlIn_d_bits_param = coupler_from_port_named_custom_boot_pin_tlOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_port_named_custom_boot_pin_tlIn_d_bits_size = coupler_from_port_named_custom_boot_pin_tlOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_port_named_custom_boot_pin_tlIn_d_bits_sink = coupler_from_port_named_custom_boot_pin_tlOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_port_named_custom_boot_pin_tlIn_d_bits_denied = coupler_from_port_named_custom_boot_pin_tlOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_port_named_custom_boot_pin_tlIn_d_bits_data = coupler_from_port_named_custom_boot_pin_tlOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_port_named_custom_boot_pin_tlIn_d_bits_corrupt = coupler_from_port_named_custom_boot_pin_tlOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_port_named_custom_boot_pin_auto_tl_in_a_ready = coupler_from_port_named_custom_boot_pin_tlIn_a_ready; // @[MixedNode.scala:551:17] assign coupler_from_port_named_custom_boot_pin_tlOut_a_valid = coupler_from_port_named_custom_boot_pin_tlIn_a_valid; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_port_named_custom_boot_pin_tlOut_a_bits_address = coupler_from_port_named_custom_boot_pin_tlIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_port_named_custom_boot_pin_tlOut_a_bits_data = coupler_from_port_named_custom_boot_pin_tlIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_port_named_custom_boot_pin_auto_tl_in_d_valid = coupler_from_port_named_custom_boot_pin_tlIn_d_valid; // @[MixedNode.scala:551:17] assign coupler_from_port_named_custom_boot_pin_auto_tl_in_d_bits_opcode = coupler_from_port_named_custom_boot_pin_tlIn_d_bits_opcode; // @[MixedNode.scala:551:17] assign coupler_from_port_named_custom_boot_pin_auto_tl_in_d_bits_param = coupler_from_port_named_custom_boot_pin_tlIn_d_bits_param; // @[MixedNode.scala:551:17] assign coupler_from_port_named_custom_boot_pin_auto_tl_in_d_bits_size = coupler_from_port_named_custom_boot_pin_tlIn_d_bits_size; // @[MixedNode.scala:551:17] assign coupler_from_port_named_custom_boot_pin_auto_tl_in_d_bits_sink = coupler_from_port_named_custom_boot_pin_tlIn_d_bits_sink; // @[MixedNode.scala:551:17] assign coupler_from_port_named_custom_boot_pin_auto_tl_in_d_bits_denied = coupler_from_port_named_custom_boot_pin_tlIn_d_bits_denied; // @[MixedNode.scala:551:17] assign coupler_from_port_named_custom_boot_pin_auto_tl_in_d_bits_data = coupler_from_port_named_custom_boot_pin_tlIn_d_bits_data; // @[MixedNode.scala:551:17] assign coupler_from_port_named_custom_boot_pin_auto_tl_in_d_bits_corrupt = coupler_from_port_named_custom_boot_pin_tlIn_d_bits_corrupt; // @[MixedNode.scala:551:17] assign childClock = clockSinkNodeIn_clock; // @[MixedNode.scala:551:17] assign childReset = clockSinkNodeIn_reset; // @[MixedNode.scala:551:17] assign bus_xingIn_a_ready = bus_xingOut_a_ready; // @[MixedNode.scala:542:17, :551:17] assign buffer_1_auto_in_a_valid = bus_xingOut_a_valid; // @[Buffer.scala:40:9] assign buffer_1_auto_in_a_bits_opcode = bus_xingOut_a_bits_opcode; // @[Buffer.scala:40:9] assign buffer_1_auto_in_a_bits_param = bus_xingOut_a_bits_param; // @[Buffer.scala:40:9] assign buffer_1_auto_in_a_bits_size = bus_xingOut_a_bits_size; // @[Buffer.scala:40:9] assign buffer_1_auto_in_a_bits_source = bus_xingOut_a_bits_source; // @[Buffer.scala:40:9] assign buffer_1_auto_in_a_bits_address = bus_xingOut_a_bits_address; // @[Buffer.scala:40:9] assign buffer_1_auto_in_a_bits_mask = bus_xingOut_a_bits_mask; // @[Buffer.scala:40:9] assign buffer_1_auto_in_a_bits_data = bus_xingOut_a_bits_data; // @[Buffer.scala:40:9] assign buffer_1_auto_in_a_bits_corrupt = bus_xingOut_a_bits_corrupt; // @[Buffer.scala:40:9] assign buffer_1_auto_in_d_ready = bus_xingOut_d_ready; // @[Buffer.scala:40:9] assign bus_xingIn_d_valid = bus_xingOut_d_valid; // @[MixedNode.scala:542:17, :551:17] assign bus_xingIn_d_bits_opcode = bus_xingOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign bus_xingIn_d_bits_param = bus_xingOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17] assign bus_xingIn_d_bits_size = bus_xingOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17] assign bus_xingIn_d_bits_source = bus_xingOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17] assign bus_xingIn_d_bits_sink = bus_xingOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17] assign bus_xingIn_d_bits_denied = bus_xingOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17] assign bus_xingIn_d_bits_data = bus_xingOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17] assign bus_xingIn_d_bits_corrupt = bus_xingOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign auto_bus_xing_in_a_ready_0 = bus_xingIn_a_ready; // @[ClockDomain.scala:14:9] assign bus_xingOut_a_valid = bus_xingIn_a_valid; // @[MixedNode.scala:542:17, :551:17] assign bus_xingOut_a_bits_opcode = bus_xingIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign bus_xingOut_a_bits_param = bus_xingIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17] assign bus_xingOut_a_bits_size = bus_xingIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17] assign bus_xingOut_a_bits_source = bus_xingIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17] assign bus_xingOut_a_bits_address = bus_xingIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17] assign bus_xingOut_a_bits_mask = bus_xingIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign bus_xingOut_a_bits_data = bus_xingIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17] assign bus_xingOut_a_bits_corrupt = bus_xingIn_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign bus_xingOut_d_ready = bus_xingIn_d_ready; // @[MixedNode.scala:542:17, :551:17] assign auto_bus_xing_in_d_valid_0 = bus_xingIn_d_valid; // @[ClockDomain.scala:14:9] assign auto_bus_xing_in_d_bits_opcode_0 = bus_xingIn_d_bits_opcode; // @[ClockDomain.scala:14:9] assign auto_bus_xing_in_d_bits_param_0 = bus_xingIn_d_bits_param; // @[ClockDomain.scala:14:9] assign auto_bus_xing_in_d_bits_size_0 = bus_xingIn_d_bits_size; // @[ClockDomain.scala:14:9] assign auto_bus_xing_in_d_bits_source_0 = bus_xingIn_d_bits_source; // @[ClockDomain.scala:14:9] assign auto_bus_xing_in_d_bits_sink_0 = bus_xingIn_d_bits_sink; // @[ClockDomain.scala:14:9] assign auto_bus_xing_in_d_bits_denied_0 = bus_xingIn_d_bits_denied; // @[ClockDomain.scala:14:9] assign auto_bus_xing_in_d_bits_data_0 = bus_xingIn_d_bits_data; // @[ClockDomain.scala:14:9] assign auto_bus_xing_in_d_bits_corrupt_0 = bus_xingIn_d_bits_corrupt; // @[ClockDomain.scala:14:9] assign coupler_from_port_named_custom_boot_pin_auto_tl_in_a_valid = nodeOut_a_valid; // @[MixedNode.scala:542:17] assign coupler_from_port_named_custom_boot_pin_auto_tl_in_a_bits_address = nodeOut_a_bits_address; // @[MixedNode.scala:542:17] assign coupler_from_port_named_custom_boot_pin_auto_tl_in_a_bits_data = nodeOut_a_bits_data; // @[MixedNode.scala:542:17] reg [2:0] state; // @[CustomBootPin.scala:39:28] wire _T_1 = state == 3'h1; // @[CustomBootPin.scala:39:28, :43:24] assign nodeOut_a_valid = (\|state) & (_T_1 \| state != 3'h2 & state == 3'h3); // @[CustomBootPin.scala:39:28, :40:20, :43:24, :46:24] assign nodeOut_a_bits_address = _T_1 ? 29'h1000 : 29'h2000000; // @[CustomBootPin.scala:43:24, :47:23] assign nodeOut_a_bits_data = _T_1 ? 64'h80000000 : 64'h1; // @[CustomBootPin.scala:43:24, :47:23] wire fixer__T_1 = fixer_a_first & fixer__a_first_T; // @[Decoupled.scala:51:35] wire fixer__T_3 = fixer_d_first & fixer__T_2; // @[Decoupled.scala:51:35] wire [2:0] _GEN = state == 3'h5 & ~custom_boot ? 3'h0 : state; // @[CustomBootPin.scala:39:28, :43:24, :67:{29,43,51}] wire [7:0][2:0] _GEN_0 = {{_GEN}, {_GEN}, {_GEN}, {nodeOut_d_valid ? 3'h5 : state}, {nodeOut_a_ready & nodeOut_a_valid ? 3'h4 : state}, {nodeOut_d_valid ? 3'h3 : state}, {nodeOut_a_ready & nodeOut_a_valid ? 3'h2 : state}, {custom_boot ? 3'h1 : state}}; // @[Decoupled.scala:51:35] always @(posedge childClock) begin // @[LazyModuleImp.scala:155:31] if (childReset) begin // @[LazyModuleImp.scala:155:31, :158:31] fixer_a_first_counter <= 9'h0; // @[Edges.scala:229:27] fixer_d_first_counter <= 9'h0; // @[Edges.scala:229:27] fixer_flight_0 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_1 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_2 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_3 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_4 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_5 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_6 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_7 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_8 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_9 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_10 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_11 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_12 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_13 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_14 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_15 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_16 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_17 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_18 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_19 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_20 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_21 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_22 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_23 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_24 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_25 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_26 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_27 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_28 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_29 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_30 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_31 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_32 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_33 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_34 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_35 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_36 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_37 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_38 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_39 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_40 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_41 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_42 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_43 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_44 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_45 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_46 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_47 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_48 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_49 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_50 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_51 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_52 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_53 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_54 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_55 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_56 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_57 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_58 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_59 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_60 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_61 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_62 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_63 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_64 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_65 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_66 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_67 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_68 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_69 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_70 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_71 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_72 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_73 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_74 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_75 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_76 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_77 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_78 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_79 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_80 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_81 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_82 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_83 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_84 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_85 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_86 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_87 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_88 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_89 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_90 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_91 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_92 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_93 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_94 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_95 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_96 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_97 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_98 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_99 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_100 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_101 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_102 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_103 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_104 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_105 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_106 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_107 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_108 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_109 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_110 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_111 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_112 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_113 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_114 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_115 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_116 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_117 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_118 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_119 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_120 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_121 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_122 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_123 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_124 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_125 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_126 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_127 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_128 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_129 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_130 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_131 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_132 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_133 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_134 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_135 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_136 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_137 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_138 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_139 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_140 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_141 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_142 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_143 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_144 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_145 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_146 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_147 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_148 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_149 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_150 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_151 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_152 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_153 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_154 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_155 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_156 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_157 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_158 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_159 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_160 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_161 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_162 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_163 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_164 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_165 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_166 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_167 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_168 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_169 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_170 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_171 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_172 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_173 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_174 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_175 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_176 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_177 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_178 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_179 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_180 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_181 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_182 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_183 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_184 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_185 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_186 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_187 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_188 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_189 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_190 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_191 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_192 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_193 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_194 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_195 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_196 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_197 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_198 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_199 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_200 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_201 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_202 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_203 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_204 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_205 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_206 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_207 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_208 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_209 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_210 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_211 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_212 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_213 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_214 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_215 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_216 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_217 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_218 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_219 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_220 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_221 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_222 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_223 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_224 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_225 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_226 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_227 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_228 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_229 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_230 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_231 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_232 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_233 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_234 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_235 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_236 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_237 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_238 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_239 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_240 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_241 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_242 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_243 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_244 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_245 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_246 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_247 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_248 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_249 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_250 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_251 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_252 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_253 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_254 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_255 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_256 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_SourceIdFIFOed <= 257'h0; // @[FIFOFixer.scala:115:35] state <= 3'h0; // @[CustomBootPin.scala:39:28] end else begin // @[LazyModuleImp.scala:155:31] if (fixer__a_first_T) // @[Decoupled.scala:51:35] fixer_a_first_counter <= fixer__a_first_counter_T; // @[Edges.scala:229:27, :236:21] if (fixer__d_first_T) // @[Decoupled.scala:51:35] fixer_d_first_counter <= fixer__d_first_counter_T; // @[Edges.scala:229:27, :236:21] fixer_flight_0 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'h0) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'h0 \| fixer_flight_0); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_1 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'h1) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'h1 \| fixer_flight_1); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_2 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'h2) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'h2 \| fixer_flight_2); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_3 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'h3) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'h3 \| fixer_flight_3); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_4 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'h4) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'h4 \| fixer_flight_4); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_5 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'h5) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'h5 \| fixer_flight_5); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_6 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'h6) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'h6 \| fixer_flight_6); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_7 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'h7) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'h7 \| fixer_flight_7); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_8 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'h8) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'h8 \| fixer_flight_8); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_9 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'h9) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'h9 \| fixer_flight_9); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_10 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'hA) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'hA \| fixer_flight_10); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_11 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'hB) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'hB \| fixer_flight_11); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_12 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'hC) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'hC \| fixer_flight_12); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_13 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'hD) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'hD \| fixer_flight_13); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_14 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'hE) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'hE \| fixer_flight_14); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_15 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'hF) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'hF \| fixer_flight_15); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_16 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'h10) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'h10 \| fixer_flight_16); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_17 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'h11) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'h11 \| fixer_flight_17); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_18 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'h12) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'h12 \| fixer_flight_18); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_19 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'h13) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'h13 \| fixer_flight_19); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_20 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'h14) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'h14 \| fixer_flight_20); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_21 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'h15) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'h15 \| fixer_flight_21); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_22 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'h16) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'h16 \| fixer_flight_22); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_23 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'h17) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'h17 \| fixer_flight_23); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_24 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'h18) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'h18 \| fixer_flight_24); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_25 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'h19) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'h19 \| fixer_flight_25); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_26 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'h1A) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'h1A \| fixer_flight_26); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_27 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'h1B) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'h1B \| fixer_flight_27); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_28 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'h1C) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'h1C \| fixer_flight_28); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_29 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'h1D) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'h1D \| fixer_flight_29); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_30 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'h1E) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'h1E \| fixer_flight_30); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_31 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'h1F) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'h1F \| fixer_flight_31); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_32 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'h20) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'h20 \| fixer_flight_32); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_33 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'h21) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'h21 \| fixer_flight_33); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_34 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'h22) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'h22 \| fixer_flight_34); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_35 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'h23) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'h23 \| fixer_flight_35); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_36 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'h24) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'h24 \| fixer_flight_36); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_37 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'h25) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'h25 \| fixer_flight_37); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_38 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'h26) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'h26 \| fixer_flight_38); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_39 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'h27) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'h27 \| fixer_flight_39); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_40 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'h28) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'h28 \| fixer_flight_40); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_41 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'h29) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'h29 \| fixer_flight_41); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_42 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'h2A) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'h2A \| fixer_flight_42); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_43 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'h2B) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'h2B \| fixer_flight_43); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_44 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'h2C) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'h2C \| fixer_flight_44); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_45 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'h2D) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'h2D \| fixer_flight_45); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_46 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'h2E) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'h2E \| fixer_flight_46); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_47 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'h2F) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'h2F \| fixer_flight_47); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_48 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'h30) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'h30 \| fixer_flight_48); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_49 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'h31) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'h31 \| fixer_flight_49); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_50 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'h32) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'h32 \| fixer_flight_50); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_51 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'h33) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'h33 \| fixer_flight_51); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_52 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'h34) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'h34 \| fixer_flight_52); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_53 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'h35) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'h35 \| fixer_flight_53); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_54 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'h36) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'h36 \| fixer_flight_54); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_55 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'h37) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'h37 \| fixer_flight_55); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_56 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'h38) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'h38 \| fixer_flight_56); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_57 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'h39) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'h39 \| fixer_flight_57); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_58 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'h3A) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'h3A \| fixer_flight_58); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_59 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'h3B) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'h3B \| fixer_flight_59); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_60 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'h3C) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'h3C \| fixer_flight_60); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_61 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'h3D) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'h3D \| fixer_flight_61); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_62 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'h3E) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'h3E \| fixer_flight_62); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_63 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'h3F) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'h3F \| fixer_flight_63); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_64 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'h40) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'h40 \| fixer_flight_64); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_65 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'h41) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'h41 \| fixer_flight_65); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_66 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'h42) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'h42 \| fixer_flight_66); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_67 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'h43) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'h43 \| fixer_flight_67); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_68 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'h44) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'h44 \| fixer_flight_68); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_69 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'h45) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'h45 \| fixer_flight_69); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_70 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'h46) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'h46 \| fixer_flight_70); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_71 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'h47) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'h47 \| fixer_flight_71); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_72 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'h48) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'h48 \| fixer_flight_72); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_73 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'h49) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'h49 \| fixer_flight_73); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_74 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'h4A) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'h4A \| fixer_flight_74); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_75 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'h4B) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'h4B \| fixer_flight_75); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_76 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'h4C) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'h4C \| fixer_flight_76); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_77 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'h4D) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'h4D \| fixer_flight_77); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_78 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'h4E) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'h4E \| fixer_flight_78); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_79 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'h4F) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'h4F \| fixer_flight_79); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_80 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'h50) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'h50 \| fixer_flight_80); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_81 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'h51) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'h51 \| fixer_flight_81); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_82 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'h52) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'h52 \| fixer_flight_82); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_83 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'h53) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'h53 \| fixer_flight_83); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_84 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'h54) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'h54 \| fixer_flight_84); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_85 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'h55) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'h55 \| fixer_flight_85); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_86 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'h56) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'h56 \| fixer_flight_86); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_87 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'h57) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'h57 \| fixer_flight_87); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_88 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'h58) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'h58 \| fixer_flight_88); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_89 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'h59) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'h59 \| fixer_flight_89); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_90 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'h5A) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'h5A \| fixer_flight_90); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_91 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'h5B) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'h5B \| fixer_flight_91); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_92 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'h5C) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'h5C \| fixer_flight_92); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_93 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'h5D) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'h5D \| fixer_flight_93); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_94 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'h5E) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'h5E \| fixer_flight_94); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_95 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'h5F) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'h5F \| fixer_flight_95); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_96 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'h60) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'h60 \| fixer_flight_96); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_97 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'h61) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'h61 \| fixer_flight_97); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_98 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'h62) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'h62 \| fixer_flight_98); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_99 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'h63) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'h63 \| fixer_flight_99); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_100 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'h64) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'h64 \| fixer_flight_100); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_101 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'h65) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'h65 \| fixer_flight_101); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_102 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'h66) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'h66 \| fixer_flight_102); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_103 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'h67) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'h67 \| fixer_flight_103); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_104 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'h68) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'h68 \| fixer_flight_104); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_105 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'h69) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'h69 \| fixer_flight_105); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_106 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'h6A) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'h6A \| fixer_flight_106); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_107 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'h6B) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'h6B \| fixer_flight_107); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_108 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'h6C) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'h6C \| fixer_flight_108); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_109 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'h6D) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'h6D \| fixer_flight_109); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_110 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'h6E) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'h6E \| fixer_flight_110); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_111 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'h6F) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'h6F \| fixer_flight_111); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_112 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'h70) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'h70 \| fixer_flight_112); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_113 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'h71) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'h71 \| fixer_flight_113); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_114 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'h72) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'h72 \| fixer_flight_114); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_115 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'h73) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'h73 \| fixer_flight_115); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_116 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'h74) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'h74 \| fixer_flight_116); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_117 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'h75) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'h75 \| fixer_flight_117); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_118 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'h76) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'h76 \| fixer_flight_118); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_119 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'h77) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'h77 \| fixer_flight_119); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_120 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'h78) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'h78 \| fixer_flight_120); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_121 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'h79) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'h79 \| fixer_flight_121); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_122 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'h7A) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'h7A \| fixer_flight_122); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_123 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'h7B) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'h7B \| fixer_flight_123); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_124 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'h7C) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'h7C \| fixer_flight_124); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_125 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'h7D) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'h7D \| fixer_flight_125); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_126 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'h7E) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'h7E \| fixer_flight_126); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_127 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'h7F) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'h7F \| fixer_flight_127); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_128 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'h80) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'h80 \| fixer_flight_128); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_129 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'h81) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'h81 \| fixer_flight_129); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_130 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'h82) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'h82 \| fixer_flight_130); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_131 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'h83) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'h83 \| fixer_flight_131); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_132 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'h84) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'h84 \| fixer_flight_132); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_133 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'h85) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'h85 \| fixer_flight_133); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_134 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'h86) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'h86 \| fixer_flight_134); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_135 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'h87) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'h87 \| fixer_flight_135); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_136 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'h88) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'h88 \| fixer_flight_136); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_137 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'h89) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'h89 \| fixer_flight_137); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_138 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'h8A) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'h8A \| fixer_flight_138); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_139 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'h8B) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'h8B \| fixer_flight_139); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_140 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'h8C) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'h8C \| fixer_flight_140); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_141 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'h8D) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'h8D \| fixer_flight_141); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_142 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'h8E) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'h8E \| fixer_flight_142); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_143 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'h8F) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'h8F \| fixer_flight_143); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_144 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'h90) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'h90 \| fixer_flight_144); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_145 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'h91) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'h91 \| fixer_flight_145); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_146 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'h92) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'h92 \| fixer_flight_146); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_147 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'h93) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'h93 \| fixer_flight_147); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_148 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'h94) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'h94 \| fixer_flight_148); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_149 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'h95) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'h95 \| fixer_flight_149); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_150 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'h96) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'h96 \| fixer_flight_150); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_151 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'h97) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'h97 \| fixer_flight_151); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_152 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'h98) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'h98 \| fixer_flight_152); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_153 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'h99) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'h99 \| fixer_flight_153); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_154 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'h9A) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'h9A \| fixer_flight_154); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_155 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'h9B) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'h9B \| fixer_flight_155); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_156 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'h9C) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'h9C \| fixer_flight_156); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_157 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'h9D) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'h9D \| fixer_flight_157); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_158 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'h9E) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'h9E \| fixer_flight_158); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_159 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'h9F) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'h9F \| fixer_flight_159); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_160 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'hA0) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'hA0 \| fixer_flight_160); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_161 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'hA1) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'hA1 \| fixer_flight_161); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_162 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'hA2) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'hA2 \| fixer_flight_162); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_163 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'hA3) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'hA3 \| fixer_flight_163); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_164 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'hA4) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'hA4 \| fixer_flight_164); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_165 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'hA5) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'hA5 \| fixer_flight_165); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_166 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'hA6) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'hA6 \| fixer_flight_166); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_167 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'hA7) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'hA7 \| fixer_flight_167); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_168 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'hA8) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'hA8 \| fixer_flight_168); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_169 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'hA9) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'hA9 \| fixer_flight_169); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_170 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'hAA) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'hAA \| fixer_flight_170); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_171 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'hAB) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'hAB \| fixer_flight_171); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_172 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'hAC) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'hAC \| fixer_flight_172); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_173 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'hAD) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'hAD \| fixer_flight_173); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_174 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'hAE) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'hAE \| fixer_flight_174); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_175 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'hAF) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'hAF \| fixer_flight_175); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_176 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'hB0) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'hB0 \| fixer_flight_176); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_177 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'hB1) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'hB1 \| fixer_flight_177); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_178 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'hB2) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'hB2 \| fixer_flight_178); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_179 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'hB3) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'hB3 \| fixer_flight_179); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_180 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'hB4) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'hB4 \| fixer_flight_180); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_181 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'hB5) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'hB5 \| fixer_flight_181); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_182 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'hB6) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'hB6 \| fixer_flight_182); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_183 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'hB7) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'hB7 \| fixer_flight_183); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_184 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'hB8) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'hB8 \| fixer_flight_184); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_185 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'hB9) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'hB9 \| fixer_flight_185); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_186 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'hBA) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'hBA \| fixer_flight_186); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_187 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'hBB) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'hBB \| fixer_flight_187); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_188 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'hBC) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'hBC \| fixer_flight_188); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_189 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'hBD) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'hBD \| fixer_flight_189); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_190 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'hBE) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'hBE \| fixer_flight_190); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_191 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'hBF) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'hBF \| fixer_flight_191); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_192 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'hC0) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'hC0 \| fixer_flight_192); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_193 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'hC1) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'hC1 \| fixer_flight_193); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_194 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'hC2) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'hC2 \| fixer_flight_194); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_195 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'hC3) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'hC3 \| fixer_flight_195); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_196 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'hC4) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'hC4 \| fixer_flight_196); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_197 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'hC5) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'hC5 \| fixer_flight_197); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_198 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'hC6) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'hC6 \| fixer_flight_198); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_199 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'hC7) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'hC7 \| fixer_flight_199); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_200 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'hC8) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'hC8 \| fixer_flight_200); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_201 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'hC9) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'hC9 \| fixer_flight_201); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_202 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'hCA) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'hCA \| fixer_flight_202); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_203 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'hCB) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'hCB \| fixer_flight_203); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_204 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'hCC) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'hCC \| fixer_flight_204); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_205 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'hCD) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'hCD \| fixer_flight_205); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_206 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'hCE) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'hCE \| fixer_flight_206); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_207 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'hCF) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'hCF \| fixer_flight_207); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_208 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'hD0) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'hD0 \| fixer_flight_208); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_209 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'hD1) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'hD1 \| fixer_flight_209); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_210 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'hD2) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'hD2 \| fixer_flight_210); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_211 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'hD3) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'hD3 \| fixer_flight_211); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_212 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'hD4) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'hD4 \| fixer_flight_212); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_213 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'hD5) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'hD5 \| fixer_flight_213); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_214 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'hD6) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'hD6 \| fixer_flight_214); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_215 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'hD7) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'hD7 \| fixer_flight_215); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_216 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'hD8) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'hD8 \| fixer_flight_216); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_217 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'hD9) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'hD9 \| fixer_flight_217); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_218 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'hDA) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'hDA \| fixer_flight_218); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_219 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'hDB) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'hDB \| fixer_flight_219); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_220 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'hDC) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'hDC \| fixer_flight_220); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_221 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'hDD) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'hDD \| fixer_flight_221); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_222 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'hDE) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'hDE \| fixer_flight_222); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_223 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'hDF) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'hDF \| fixer_flight_223); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_224 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'hE0) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'hE0 \| fixer_flight_224); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_225 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'hE1) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'hE1 \| fixer_flight_225); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_226 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'hE2) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'hE2 \| fixer_flight_226); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_227 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'hE3) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'hE3 \| fixer_flight_227); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_228 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'hE4) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'hE4 \| fixer_flight_228); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_229 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'hE5) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'hE5 \| fixer_flight_229); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_230 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'hE6) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'hE6 \| fixer_flight_230); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_231 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'hE7) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'hE7 \| fixer_flight_231); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_232 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'hE8) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'hE8 \| fixer_flight_232); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_233 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'hE9) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'hE9 \| fixer_flight_233); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_234 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'hEA) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'hEA \| fixer_flight_234); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_235 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'hEB) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'hEB \| fixer_flight_235); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_236 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'hEC) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'hEC \| fixer_flight_236); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_237 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'hED) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'hED \| fixer_flight_237); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_238 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'hEE) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'hEE \| fixer_flight_238); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_239 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'hEF) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'hEF \| fixer_flight_239); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_240 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'hF0) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'hF0 \| fixer_flight_240); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_241 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'hF1) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'hF1 \| fixer_flight_241); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_242 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'hF2) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'hF2 \| fixer_flight_242); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_243 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'hF3) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'hF3 \| fixer_flight_243); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_244 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'hF4) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'hF4 \| fixer_flight_244); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_245 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'hF5) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'hF5 \| fixer_flight_245); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_246 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'hF6) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'hF6 \| fixer_flight_246); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_247 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'hF7) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'hF7 \| fixer_flight_247); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_248 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'hF8) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'hF8 \| fixer_flight_248); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_249 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'hF9) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'hF9 \| fixer_flight_249); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_250 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'hFA) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'hFA \| fixer_flight_250); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_251 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'hFB) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'hFB \| fixer_flight_251); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_252 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'hFC) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'hFC \| fixer_flight_252); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_253 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'hFD) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'hFD \| fixer_flight_253); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_254 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'hFE) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'hFE \| fixer_flight_254); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_255 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'hFF) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'hFF \| fixer_flight_255); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_256 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'h100) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'h100 \| fixer_flight_256); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_SourceIdFIFOed <= fixer__SourceIdFIFOed_T; // @[FIFOFixer.scala:115:35, :126:40] state <= _GEN_0[state]; // @[CustomBootPin.scala:39:28, :43:24, :44:46, :53:30, :55:58, :64:30, :66:50] end always @(posedge) FixedClockBroadcast_7 fixedClockNode ( // @[ClockGroup.scala:115:114] .auto_anon_in_clock (clockGroup_auto_out_clock), // @[ClockGroup.scala:24:9] .auto_anon_in_reset (clockGroup_auto_out_reset), // @[ClockGroup.scala:24:9] .auto_anon_out_6_clock (auto_fixedClockNode_anon_out_5_clock_0), .auto_anon_out_6_reset (auto_fixedClockNode_anon_out_5_reset_0), .auto_anon_out_5_clock (auto_fixedClockNode_anon_out_4_clock_0), .auto_anon_out_5_reset (auto_fixedClockNode_anon_out_4_reset_0), .auto_anon_out_4_clock (auto_fixedClockNode_anon_out_3_clock_0), .auto_anon_out_4_reset (auto_fixedClockNode_anon_out_3_reset_0), .auto_anon_out_3_clock (auto_fixedClockNode_anon_out_2_clock_0), .auto_anon_out_3_reset (auto_fixedClockNode_anon_out_2_reset_0), .auto_anon_out_2_clock (auto_fixedClockNode_anon_out_1_clock_0), .auto_anon_out_2_reset (auto_fixedClockNode_anon_out_1_reset_0), .auto_anon_out_1_clock (auto_fixedClockNode_anon_out_0_clock_0), .auto_anon_out_1_reset (auto_fixedClockNode_anon_out_0_reset_0), .auto_anon_out_0_clock (clockSinkNodeIn_clock), .auto_anon_out_0_reset (clockSinkNodeIn_reset) ); // @[ClockGroup.scala:115:114] TLXbar_cbus_in_i2_o1_a29d64s9k1z4u in_xbar ( // @[PeripheryBus.scala:56:29] .clock (childClock), // @[LazyModuleImp.scala:155:31] .reset (childReset), // @[LazyModuleImp.scala:158:31] .auto_anon_in_1_a_ready (coupler_from_port_named_custom_boot_pin_auto_tl_out_a_ready), .auto_anon_in_1_a_valid (coupler_from_port_named_custom_boot_pin_auto_tl_out_a_valid), // @[LazyModuleImp.scala:138:7] .auto_anon_in_1_a_bits_address (coupler_from_port_named_custom_boot_pin_auto_tl_out_a_bits_address), // @[LazyModuleImp.scala:138:7] .auto_anon_in_1_a_bits_data (coupler_from_port_named_custom_boot_pin_auto_tl_out_a_bits_data), // @[LazyModuleImp.scala:138:7] .auto_anon_in_1_d_valid (coupler_from_port_named_custom_boot_pin_auto_tl_out_d_valid), .auto_anon_in_1_d_bits_opcode (coupler_from_port_named_custom_boot_pin_auto_tl_out_d_bits_opcode), .auto_anon_in_1_d_bits_param (coupler_from_port_named_custom_boot_pin_auto_tl_out_d_bits_param), .auto_anon_in_1_d_bits_size (coupler_from_port_named_custom_boot_pin_auto_tl_out_d_bits_size), .auto_anon_in_1_d_bits_sink (coupler_from_port_named_custom_boot_pin_auto_tl_out_d_bits_sink), .auto_anon_in_1_d_bits_denied (coupler_from_port_named_custom_boot_pin_auto_tl_out_d_bits_denied), .auto_anon_in_1_d_bits_data (coupler_from_port_named_custom_boot_pin_auto_tl_out_d_bits_data), .auto_anon_in_1_d_bits_corrupt (coupler_from_port_named_custom_boot_pin_auto_tl_out_d_bits_corrupt), .auto_anon_in_0_a_ready (buffer_1_auto_out_a_ready), .auto_anon_in_0_a_valid (buffer_1_auto_out_a_valid), // @[Buffer.scala:40:9] .auto_anon_in_0_a_bits_opcode (buffer_1_auto_out_a_bits_opcode), // @[Buffer.scala:40:9] .auto_anon_in_0_a_bits_param (buffer_1_auto_out_a_bits_param), // @[Buffer.scala:40:9] .auto_anon_in_0_a_bits_size (buffer_1_auto_out_a_bits_size), // @[Buffer.scala:40:9] .auto_anon_in_0_a_bits_source (buffer_1_auto_out_a_bits_source), // @[Buffer.scala:40:9] .auto_anon_in_0_a_bits_address (buffer_1_auto_out_a_bits_address), // @[Buffer.scala:40:9] .auto_anon_in_0_a_bits_mask (buffer_1_auto_out_a_bits_mask), // @[Buffer.scala:40:9] .auto_anon_in_0_a_bits_data (buffer_1_auto_out_a_bits_data), // @[Buffer.scala:40:9] .auto_anon_in_0_a_bits_corrupt (buffer_1_auto_out_a_bits_corrupt), // @[Buffer.scala:40:9] .auto_anon_in_0_d_ready (buffer_1_auto_out_d_ready), // @[Buffer.scala:40:9] .auto_anon_in_0_d_valid (buffer_1_auto_out_d_valid), .auto_anon_in_0_d_bits_opcode (buffer_1_auto_out_d_bits_opcode), .auto_anon_in_0_d_bits_param (buffer_1_auto_out_d_bits_param), .auto_anon_in_0_d_bits_size (buffer_1_auto_out_d_bits_size), .auto_anon_in_0_d_bits_source (buffer_1_auto_out_d_bits_source), .auto_anon_in_0_d_bits_sink (buffer_1_auto_out_d_bits_sink), .auto_anon_in_0_d_bits_denied (buffer_1_auto_out_d_bits_denied), .auto_anon_in_0_d_bits_data (buffer_1_auto_out_d_bits_data), .auto_anon_in_0_d_bits_corrupt (buffer_1_auto_out_d_bits_corrupt), .auto_anon_out_a_ready (_atomics_auto_in_a_ready), // @[AtomicAutomata.scala:289:29] .auto_anon_out_a_valid (_in_xbar_auto_anon_out_a_valid), .auto_anon_out_a_bits_opcode (_in_xbar_auto_anon_out_a_bits_opcode), .auto_anon_out_a_bits_param (_in_xbar_auto_anon_out_a_bits_param), .auto_anon_out_a_bits_size (_in_xbar_auto_anon_out_a_bits_size), .auto_anon_out_a_bits_source (_in_xbar_auto_anon_out_a_bits_source), .auto_anon_out_a_bits_address (_in_xbar_auto_anon_out_a_bits_address), .auto_anon_out_a_bits_mask (_in_xbar_auto_anon_out_a_bits_mask), .auto_anon_out_a_bits_data (_in_xbar_auto_anon_out_a_bits_data), .auto_anon_out_a_bits_corrupt (_in_xbar_auto_anon_out_a_bits_corrupt), .auto_anon_out_d_ready (_in_xbar_auto_anon_out_d_ready), .auto_anon_out_d_valid (_atomics_auto_in_d_valid), // @[AtomicAutomata.scala:289:29] .auto_anon_out_d_bits_opcode (_atomics_auto_in_d_bits_opcode), // @[AtomicAutomata.scala:289:29] .auto_anon_out_d_bits_param (_atomics_auto_in_d_bits_param), // @[AtomicAutomata.scala:289:29] .auto_anon_out_d_bits_size (_atomics_auto_in_d_bits_size), // @[AtomicAutomata.scala:289:29] .auto_anon_out_d_bits_source (_atomics_auto_in_d_bits_source), // @[AtomicAutomata.scala:289:29] .auto_anon_out_d_bits_sink (_atomics_auto_in_d_bits_sink), // @[AtomicAutomata.scala:289:29] .auto_anon_out_d_bits_denied (_atomics_auto_in_d_bits_denied), // @[AtomicAutomata.scala:289:29] .auto_anon_out_d_bits_data (_atomics_auto_in_d_bits_data), // @[AtomicAutomata.scala:289:29] .auto_anon_out_d_bits_corrupt (_atomics_auto_in_d_bits_corrupt) // @[AtomicAutomata.scala:289:29] ); // @[PeripheryBus.scala:56:29] TLXbar_cbus_out_i1_o8_a29d64s9k1z4u out_xbar ( // @[PeripheryBus.scala:57:30] .clock (childClock), // @[LazyModuleImp.scala:155:31] .reset (childReset), // @[LazyModuleImp.scala:158:31] .auto_anon_in_a_ready (fixer_auto_anon_out_a_ready), .auto_anon_in_a_valid (fixer_auto_anon_out_a_valid), // @[FIFOFixer.scala:50:9] .auto_anon_in_a_bits_opcode (fixer_auto_anon_out_a_bits_opcode), // @[FIFOFixer.scala:50:9] .auto_anon_in_a_bits_param (fixer_auto_anon_out_a_bits_param), // @[FIFOFixer.scala:50:9] .auto_anon_in_a_bits_size (fixer_auto_anon_out_a_bits_size), // @[FIFOFixer.scala:50:9] .auto_anon_in_a_bits_source (fixer_auto_anon_out_a_bits_source), // @[FIFOFixer.scala:50:9] .auto_anon_in_a_bits_address (fixer_auto_anon_out_a_bits_address), // @[FIFOFixer.scala:50:9] .auto_anon_in_a_bits_mask (fixer_auto_anon_out_a_bits_mask), // @[FIFOFixer.scala:50:9] .auto_anon_in_a_bits_data (fixer_auto_anon_out_a_bits_data), // @[FIFOFixer.scala:50:9] .auto_anon_in_a_bits_corrupt (fixer_auto_anon_out_a_bits_corrupt), // @[FIFOFixer.scala:50:9] .auto_anon_in_d_ready (fixer_auto_anon_out_d_ready), // @[FIFOFixer.scala:50:9] .auto_anon_in_d_valid (fixer_auto_anon_out_d_valid), .auto_anon_in_d_bits_opcode (fixer_auto_anon_out_d_bits_opcode), .auto_anon_in_d_bits_param (fixer_auto_anon_out_d_bits_param), .auto_anon_in_d_bits_size (fixer_auto_anon_out_d_bits_size), .auto_anon_in_d_bits_source (fixer_auto_anon_out_d_bits_source), .auto_anon_in_d_bits_sink (fixer_auto_anon_out_d_bits_sink), .auto_anon_in_d_bits_denied (fixer_auto_anon_out_d_bits_denied), .auto_anon_in_d_bits_data (fixer_auto_anon_out_d_bits_data), .auto_anon_in_d_bits_corrupt (fixer_auto_anon_out_d_bits_corrupt), .auto_anon_out_7_a_ready (_coupler_to_prci_ctrl_auto_tl_in_a_ready), // @[LazyScope.scala:98:27] .auto_anon_out_7_a_valid (_out_xbar_auto_anon_out_7_a_valid), .auto_anon_out_7_a_bits_opcode (_out_xbar_auto_anon_out_7_a_bits_opcode), .auto_anon_out_7_a_bits_param (_out_xbar_auto_anon_out_7_a_bits_param), .auto_anon_out_7_a_bits_size (_out_xbar_auto_anon_out_7_a_bits_size), .auto_anon_out_7_a_bits_source (_out_xbar_auto_anon_out_7_a_bits_source), .auto_anon_out_7_a_bits_address (_out_xbar_auto_anon_out_7_a_bits_address), .auto_anon_out_7_a_bits_mask (_out_xbar_auto_anon_out_7_a_bits_mask), .auto_anon_out_7_a_bits_data (_out_xbar_auto_anon_out_7_a_bits_data), .auto_anon_out_7_a_bits_corrupt (_out_xbar_auto_anon_out_7_a_bits_corrupt), .auto_anon_out_7_d_ready (_out_xbar_auto_anon_out_7_d_ready), .auto_anon_out_7_d_valid (_coupler_to_prci_ctrl_auto_tl_in_d_valid), // @[LazyScope.scala:98:27] .auto_anon_out_7_d_bits_opcode (_coupler_to_prci_ctrl_auto_tl_in_d_bits_opcode), // @[LazyScope.scala:98:27] .auto_anon_out_7_d_bits_param (_coupler_to_prci_ctrl_auto_tl_in_d_bits_param), // @[LazyScope.scala:98:27] .auto_anon_out_7_d_bits_size (_coupler_to_prci_ctrl_auto_tl_in_d_bits_size), // @[LazyScope.scala:98:27] .auto_anon_out_7_d_bits_source (_coupler_to_prci_ctrl_auto_tl_in_d_bits_source), // @[LazyScope.scala:98:27] .auto_anon_out_7_d_bits_sink (_coupler_to_prci_ctrl_auto_tl_in_d_bits_sink), // @[LazyScope.scala:98:27] .auto_anon_out_7_d_bits_denied (_coupler_to_prci_ctrl_auto_tl_in_d_bits_denied), // @[LazyScope.scala:98:27] .auto_anon_out_7_d_bits_data (_coupler_to_prci_ctrl_auto_tl_in_d_bits_data), // @[LazyScope.scala:98:27] .auto_anon_out_7_d_bits_corrupt (_coupler_to_prci_ctrl_auto_tl_in_d_bits_corrupt), // @[LazyScope.scala:98:27] .auto_anon_out_6_a_ready (_coupler_to_bootrom_auto_tl_in_a_ready), // @[LazyScope.scala:98:27] .auto_anon_out_6_a_valid (_out_xbar_auto_anon_out_6_a_valid), .auto_anon_out_6_a_bits_opcode (_out_xbar_auto_anon_out_6_a_bits_opcode), .auto_anon_out_6_a_bits_param (_out_xbar_auto_anon_out_6_a_bits_param), .auto_anon_out_6_a_bits_size (_out_xbar_auto_anon_out_6_a_bits_size), .auto_anon_out_6_a_bits_source (_out_xbar_auto_anon_out_6_a_bits_source), .auto_anon_out_6_a_bits_address (_out_xbar_auto_anon_out_6_a_bits_address), .auto_anon_out_6_a_bits_mask (_out_xbar_auto_anon_out_6_a_bits_mask), .auto_anon_out_6_a_bits_data (_out_xbar_auto_anon_out_6_a_bits_data), .auto_anon_out_6_a_bits_corrupt (_out_xbar_auto_anon_out_6_a_bits_corrupt), .auto_anon_out_6_d_ready (_out_xbar_auto_anon_out_6_d_ready), .auto_anon_out_6_d_valid (_coupler_to_bootrom_auto_tl_in_d_valid), // @[LazyScope.scala:98:27] .auto_anon_out_6_d_bits_size (_coupler_to_bootrom_auto_tl_in_d_bits_size), // @[LazyScope.scala:98:27] .auto_anon_out_6_d_bits_source (_coupler_to_bootrom_auto_tl_in_d_bits_source), // @[LazyScope.scala:98:27] .auto_anon_out_6_d_bits_data (_coupler_to_bootrom_auto_tl_in_d_bits_data), // @[LazyScope.scala:98:27] .auto_anon_out_5_a_ready (_coupler_to_debug_auto_tl_in_a_ready), // @[LazyScope.scala:98:27] .auto_anon_out_5_a_valid (_out_xbar_auto_anon_out_5_a_valid), .auto_anon_out_5_a_bits_opcode (_out_xbar_auto_anon_out_5_a_bits_opcode), .auto_anon_out_5_a_bits_param (_out_xbar_auto_anon_out_5_a_bits_param), .auto_anon_out_5_a_bits_size (_out_xbar_auto_anon_out_5_a_bits_size), .auto_anon_out_5_a_bits_source (_out_xbar_auto_anon_out_5_a_bits_source), .auto_anon_out_5_a_bits_address (_out_xbar_auto_anon_out_5_a_bits_address), .auto_anon_out_5_a_bits_mask (_out_xbar_auto_anon_out_5_a_bits_mask), .auto_anon_out_5_a_bits_data (_out_xbar_auto_anon_out_5_a_bits_data), .auto_anon_out_5_a_bits_corrupt (_out_xbar_auto_anon_out_5_a_bits_corrupt), .auto_anon_out_5_d_ready (_out_xbar_auto_anon_out_5_d_ready), .auto_anon_out_5_d_valid (_coupler_to_debug_auto_tl_in_d_valid), // @[LazyScope.scala:98:27] .auto_anon_out_5_d_bits_opcode (_coupler_to_debug_auto_tl_in_d_bits_opcode), // @[LazyScope.scala:98:27] .auto_anon_out_5_d_bits_size (_coupler_to_debug_auto_tl_in_d_bits_size), // @[LazyScope.scala:98:27] .auto_anon_out_5_d_bits_source (_coupler_to_debug_auto_tl_in_d_bits_source), // @[LazyScope.scala:98:27] .auto_anon_out_5_d_bits_data (_coupler_to_debug_auto_tl_in_d_bits_data), // @[LazyScope.scala:98:27] .auto_anon_out_4_a_ready (_coupler_to_plic_auto_tl_in_a_ready), // @[LazyScope.scala:98:27] .auto_anon_out_4_a_valid (_out_xbar_auto_anon_out_4_a_valid), .auto_anon_out_4_a_bits_opcode (_out_xbar_auto_anon_out_4_a_bits_opcode), .auto_anon_out_4_a_bits_param (_out_xbar_auto_anon_out_4_a_bits_param), .auto_anon_out_4_a_bits_size (_out_xbar_auto_anon_out_4_a_bits_size), .auto_anon_out_4_a_bits_source (_out_xbar_auto_anon_out_4_a_bits_source), .auto_anon_out_4_a_bits_address (_out_xbar_auto_anon_out_4_a_bits_address), .auto_anon_out_4_a_bits_mask (_out_xbar_auto_anon_out_4_a_bits_mask), .auto_anon_out_4_a_bits_data (_out_xbar_auto_anon_out_4_a_bits_data), .auto_anon_out_4_a_bits_corrupt (_out_xbar_auto_anon_out_4_a_bits_corrupt), .auto_anon_out_4_d_ready (_out_xbar_auto_anon_out_4_d_ready), .auto_anon_out_4_d_valid (_coupler_to_plic_auto_tl_in_d_valid), // @[LazyScope.scala:98:27] .auto_anon_out_4_d_bits_opcode (_coupler_to_plic_auto_tl_in_d_bits_opcode), // @[LazyScope.scala:98:27] .auto_anon_out_4_d_bits_size (_coupler_to_plic_auto_tl_in_d_bits_size), // @[LazyScope.scala:98:27] .auto_anon_out_4_d_bits_source (_coupler_to_plic_auto_tl_in_d_bits_source), // @[LazyScope.scala:98:27] .auto_anon_out_4_d_bits_data (_coupler_to_plic_auto_tl_in_d_bits_data), // @[LazyScope.scala:98:27] .auto_anon_out_3_a_ready (_coupler_to_clint_auto_tl_in_a_ready), // @[LazyScope.scala:98:27] .auto_anon_out_3_a_valid (_out_xbar_auto_anon_out_3_a_valid), .auto_anon_out_3_a_bits_opcode (_out_xbar_auto_anon_out_3_a_bits_opcode), .auto_anon_out_3_a_bits_param (_out_xbar_auto_anon_out_3_a_bits_param), .auto_anon_out_3_a_bits_size (_out_xbar_auto_anon_out_3_a_bits_size), .auto_anon_out_3_a_bits_source (_out_xbar_auto_anon_out_3_a_bits_source), .auto_anon_out_3_a_bits_address (_out_xbar_auto_anon_out_3_a_bits_address), .auto_anon_out_3_a_bits_mask (_out_xbar_auto_anon_out_3_a_bits_mask), .auto_anon_out_3_a_bits_data (_out_xbar_auto_anon_out_3_a_bits_data), .auto_anon_out_3_a_bits_corrupt (_out_xbar_auto_anon_out_3_a_bits_corrupt), .auto_anon_out_3_d_ready (_out_xbar_auto_anon_out_3_d_ready), .auto_anon_out_3_d_valid (_coupler_to_clint_auto_tl_in_d_valid), // @[LazyScope.scala:98:27] .auto_anon_out_3_d_bits_opcode (_coupler_to_clint_auto_tl_in_d_bits_opcode), // @[LazyScope.scala:98:27] .auto_anon_out_3_d_bits_size (_coupler_to_clint_auto_tl_in_d_bits_size), // @[LazyScope.scala:98:27] .auto_anon_out_3_d_bits_source (_coupler_to_clint_auto_tl_in_d_bits_source), // @[LazyScope.scala:98:27] .auto_anon_out_3_d_bits_data (_coupler_to_clint_auto_tl_in_d_bits_data), // @[LazyScope.scala:98:27] .auto_anon_out_2_a_ready (coupler_to_bus_named_pbus_auto_widget_anon_in_a_ready), // @[LazyModuleImp.scala:138:7] .auto_anon_out_2_a_valid (coupler_to_bus_named_pbus_auto_widget_anon_in_a_valid), .auto_anon_out_2_a_bits_opcode (coupler_to_bus_named_pbus_auto_widget_anon_in_a_bits_opcode), .auto_anon_out_2_a_bits_param (coupler_to_bus_named_pbus_auto_widget_anon_in_a_bits_param), .auto_anon_out_2_a_bits_size (coupler_to_bus_named_pbus_auto_widget_anon_in_a_bits_size), .auto_anon_out_2_a_bits_source (coupler_to_bus_named_pbus_auto_widget_anon_in_a_bits_source), .auto_anon_out_2_a_bits_address (coupler_to_bus_named_pbus_auto_widget_anon_in_a_bits_address), .auto_anon_out_2_a_bits_mask (coupler_to_bus_named_pbus_auto_widget_anon_in_a_bits_mask), .auto_anon_out_2_a_bits_data (coupler_to_bus_named_pbus_auto_widget_anon_in_a_bits_data), .auto_anon_out_2_a_bits_corrupt (coupler_to_bus_named_pbus_auto_widget_anon_in_a_bits_corrupt), .auto_anon_out_2_d_ready (coupler_to_bus_named_pbus_auto_widget_anon_in_d_ready), .auto_anon_out_2_d_valid (coupler_to_bus_named_pbus_auto_widget_anon_in_d_valid), // @[LazyModuleImp.scala:138:7] .auto_anon_out_2_d_bits_opcode (coupler_to_bus_named_pbus_auto_widget_anon_in_d_bits_opcode), // @[LazyModuleImp.scala:138:7] .auto_anon_out_2_d_bits_param (coupler_to_bus_named_pbus_auto_widget_anon_in_d_bits_param), // @[LazyModuleImp.scala:138:7] .auto_anon_out_2_d_bits_size (coupler_to_bus_named_pbus_auto_widget_anon_in_d_bits_size), // @[LazyModuleImp.scala:138:7] .auto_anon_out_2_d_bits_source (coupler_to_bus_named_pbus_auto_widget_anon_in_d_bits_source), // @[LazyModuleImp.scala:138:7] .auto_anon_out_2_d_bits_sink (coupler_to_bus_named_pbus_auto_widget_anon_in_d_bits_sink), // @[LazyModuleImp.scala:138:7] .auto_anon_out_2_d_bits_denied (coupler_to_bus_named_pbus_auto_widget_anon_in_d_bits_denied), // @[LazyModuleImp.scala:138:7] .auto_anon_out_2_d_bits_data (coupler_to_bus_named_pbus_auto_widget_anon_in_d_bits_data), // @[LazyModuleImp.scala:138:7] .auto_anon_out_2_d_bits_corrupt (coupler_to_bus_named_pbus_auto_widget_anon_in_d_bits_corrupt), // @[LazyModuleImp.scala:138:7] .auto_anon_out_1_a_ready (_coupler_to_l2_ctrl_auto_tl_in_a_ready), // @[LazyScope.scala:98:27] .auto_anon_out_1_a_valid (_out_xbar_auto_anon_out_1_a_valid), .auto_anon_out_1_a_bits_opcode (_out_xbar_auto_anon_out_1_a_bits_opcode), .auto_anon_out_1_a_bits_param (_out_xbar_auto_anon_out_1_a_bits_param), .auto_anon_out_1_a_bits_size (_out_xbar_auto_anon_out_1_a_bits_size), .auto_anon_out_1_a_bits_source (_out_xbar_auto_anon_out_1_a_bits_source), .auto_anon_out_1_a_bits_address (_out_xbar_auto_anon_out_1_a_bits_address), .auto_anon_out_1_a_bits_mask (_out_xbar_auto_anon_out_1_a_bits_mask), .auto_anon_out_1_a_bits_data (_out_xbar_auto_anon_out_1_a_bits_data), .auto_anon_out_1_a_bits_corrupt (_out_xbar_auto_anon_out_1_a_bits_corrupt), .auto_anon_out_1_d_ready (_out_xbar_auto_anon_out_1_d_ready), .auto_anon_out_1_d_valid (_coupler_to_l2_ctrl_auto_tl_in_d_valid), // @[LazyScope.scala:98:27] .auto_anon_out_1_d_bits_opcode (_coupler_to_l2_ctrl_auto_tl_in_d_bits_opcode), // @[LazyScope.scala:98:27] .auto_anon_out_1_d_bits_param (_coupler_to_l2_ctrl_auto_tl_in_d_bits_param), // @[LazyScope.scala:98:27] .auto_anon_out_1_d_bits_size (_coupler_to_l2_ctrl_auto_tl_in_d_bits_size), // @[LazyScope.scala:98:27] .auto_anon_out_1_d_bits_source (_coupler_to_l2_ctrl_auto_tl_in_d_bits_source), // @[LazyScope.scala:98:27] .auto_anon_out_1_d_bits_sink (_coupler_to_l2_ctrl_auto_tl_in_d_bits_sink), // @[LazyScope.scala:98:27] .auto_anon_out_1_d_bits_denied (_coupler_to_l2_ctrl_auto_tl_in_d_bits_denied), // @[LazyScope.scala:98:27] .auto_anon_out_1_d_bits_data (_coupler_to_l2_ctrl_auto_tl_in_d_bits_data), // @[LazyScope.scala:98:27] .auto_anon_out_1_d_bits_corrupt (_coupler_to_l2_ctrl_auto_tl_in_d_bits_corrupt), // @[LazyScope.scala:98:27] .auto_anon_out_0_a_ready (_wrapped_error_device_auto_buffer_in_a_ready), // @[LazyScope.scala:98:27] .auto_anon_out_0_a_valid (_out_xbar_auto_anon_out_0_a_valid), .auto_anon_out_0_a_bits_opcode (_out_xbar_auto_anon_out_0_a_bits_opcode), .auto_anon_out_0_a_bits_param (_out_xbar_auto_anon_out_0_a_bits_param), .auto_anon_out_0_a_bits_size (_out_xbar_auto_anon_out_0_a_bits_size), .auto_anon_out_0_a_bits_source (_out_xbar_auto_anon_out_0_a_bits_source), .auto_anon_out_0_a_bits_address (_out_xbar_auto_anon_out_0_a_bits_address), .auto_anon_out_0_a_bits_mask (_out_xbar_auto_anon_out_0_a_bits_mask), .auto_anon_out_0_a_bits_data (_out_xbar_auto_anon_out_0_a_bits_data), .auto_anon_out_0_a_bits_corrupt (_out_xbar_auto_anon_out_0_a_bits_corrupt), .auto_anon_out_0_d_ready (_out_xbar_auto_anon_out_0_d_ready), .auto_anon_out_0_d_valid (_wrapped_error_device_auto_buffer_in_d_valid), // @[LazyScope.scala:98:27] .auto_anon_out_0_d_bits_opcode (_wrapped_error_device_auto_buffer_in_d_bits_opcode), // @[LazyScope.scala:98:27] .auto_anon_out_0_d_bits_param (_wrapped_error_device_auto_buffer_in_d_bits_param), // @[LazyScope.scala:98:27] .auto_anon_out_0_d_bits_size (_wrapped_error_device_auto_buffer_in_d_bits_size), // @[LazyScope.scala:98:27] .auto_anon_out_0_d_bits_source (_wrapped_error_device_auto_buffer_in_d_bits_source), // @[LazyScope.scala:98:27] .auto_anon_out_0_d_bits_sink (_wrapped_error_device_auto_buffer_in_d_bits_sink), // @[LazyScope.scala:98:27] .auto_anon_out_0_d_bits_denied (_wrapped_error_device_auto_buffer_in_d_bits_denied), // @[LazyScope.scala:98:27] .auto_anon_out_0_d_bits_data (_wrapped_error_device_auto_buffer_in_d_bits_data), // @[LazyScope.scala:98:27] .auto_anon_out_0_d_bits_corrupt (_wrapped_error_device_auto_buffer_in_d_bits_corrupt) // @[LazyScope.scala:98:27] ); // @[PeripheryBus.scala:57:30] TLBuffer_a29d64s9k1z4u buffer ( // @[Buffer.scala:75:28] .clock (childClock), // @[LazyModuleImp.scala:155:31] .reset (childReset), // @[LazyModuleImp.scala:158:31] .auto_in_a_ready (_buffer_auto_in_a_ready), .auto_in_a_valid (_atomics_auto_out_a_valid), // @[AtomicAutomata.scala:289:29] .auto_in_a_bits_opcode (_atomics_auto_out_a_bits_opcode), // @[AtomicAutomata.scala:289:29] .auto_in_a_bits_param (_atomics_auto_out_a_bits_param), // @[AtomicAutomata.scala:289:29] .auto_in_a_bits_size (_atomics_auto_out_a_bits_size), // @[AtomicAutomata.scala:289:29] .auto_in_a_bits_source (_atomics_auto_out_a_bits_source), // @[AtomicAutomata.scala:289:29] .auto_in_a_bits_address (_atomics_auto_out_a_bits_address), // @[AtomicAutomata.scala:289:29] .auto_in_a_bits_mask (_atomics_auto_out_a_bits_mask), // @[AtomicAutomata.scala:289:29] .auto_in_a_bits_data (_atomics_auto_out_a_bits_data), // @[AtomicAutomata.scala:289:29] .auto_in_a_bits_corrupt (_atomics_auto_out_a_bits_corrupt), // @[AtomicAutomata.scala:289:29] .auto_in_d_ready (_atomics_auto_out_d_ready), // @[AtomicAutomata.scala:289:29] .auto_in_d_valid (_buffer_auto_in_d_valid), .auto_in_d_bits_opcode (_buffer_auto_in_d_bits_opcode), .auto_in_d_bits_param (_buffer_auto_in_d_bits_param), .auto_in_d_bits_size (_buffer_auto_in_d_bits_size), .auto_in_d_bits_source (_buffer_auto_in_d_bits_source), .auto_in_d_bits_sink (_buffer_auto_in_d_bits_sink), .auto_in_d_bits_denied (_buffer_auto_in_d_bits_denied), .auto_in_d_bits_data (_buffer_auto_in_d_bits_data), .auto_in_d_bits_corrupt (_buffer_auto_in_d_bits_corrupt), .auto_out_a_ready (fixer_auto_anon_in_a_ready), // @[FIFOFixer.scala:50:9] .auto_out_a_valid (fixer_auto_anon_in_a_valid), .auto_out_a_bits_opcode (fixer_auto_anon_in_a_bits_opcode), .auto_out_a_bits_param (fixer_auto_anon_in_a_bits_param), .auto_out_a_bits_size (fixer_auto_anon_in_a_bits_size), .auto_out_a_bits_source (fixer_auto_anon_in_a_bits_source), .auto_out_a_bits_address (fixer_auto_anon_in_a_bits_address), .auto_out_a_bits_mask (fixer_auto_anon_in_a_bits_mask), .auto_out_a_bits_data (fixer_auto_anon_in_a_bits_data), .auto_out_a_bits_corrupt (fixer_auto_anon_in_a_bits_corrupt), .auto_out_d_ready (fixer_auto_anon_in_d_ready), .auto_out_d_valid (fixer_auto_anon_in_d_valid), // @[FIFOFixer.scala:50:9] .auto_out_d_bits_opcode (fixer_auto_anon_in_d_bits_opcode), // @[FIFOFixer.scala:50:9] .auto_out_d_bits_param (fixer_auto_anon_in_d_bits_param), // @[FIFOFixer.scala:50:9] .auto_out_d_bits_size (fixer_auto_anon_in_d_bits_size), // @[FIFOFixer.scala:50:9] .auto_out_d_bits_source (fixer_auto_anon_in_d_bits_source), // @[FIFOFixer.scala:50:9] .auto_out_d_bits_sink (fixer_auto_anon_in_d_bits_sink), // @[FIFOFixer.scala:50:9] .auto_out_d_bits_denied (fixer_auto_anon_in_d_bits_denied), // @[FIFOFixer.scala:50:9] .auto_out_d_bits_data (fixer_auto_anon_in_d_bits_data), // @[FIFOFixer.scala:50:9] .auto_out_d_bits_corrupt (fixer_auto_anon_in_d_bits_corrupt) // @[FIFOFixer.scala:50:9] ); // @[Buffer.scala:75:28] TLAtomicAutomata_cbus atomics ( // @[AtomicAutomata.scala:289:29] .clock (childClock), // @[LazyModuleImp.scala:155:31] .reset (childReset), // @[LazyModuleImp.scala:158:31] .auto_in_a_ready (_atomics_auto_in_a_ready), .auto_in_a_valid (_in_xbar_auto_anon_out_a_valid), // @[PeripheryBus.scala:56:29] .auto_in_a_bits_opcode (_in_xbar_auto_anon_out_a_bits_opcode), // @[PeripheryBus.scala:56:29] .auto_in_a_bits_param (_in_xbar_auto_anon_out_a_bits_param), // @[PeripheryBus.scala:56:29] .auto_in_a_bits_size (_in_xbar_auto_anon_out_a_bits_size), // @[PeripheryBus.scala:56:29] .auto_in_a_bits_source (_in_xbar_auto_anon_out_a_bits_source), // @[PeripheryBus.scala:56:29] .auto_in_a_bits_address (_in_xbar_auto_anon_out_a_bits_address), // @[PeripheryBus.scala:56:29] .auto_in_a_bits_mask (_in_xbar_auto_anon_out_a_bits_mask), // @[PeripheryBus.scala:56:29] .auto_in_a_bits_data (_in_xbar_auto_anon_out_a_bits_data), // @[PeripheryBus.scala:56:29] .auto_in_a_bits_corrupt (_in_xbar_auto_anon_out_a_bits_corrupt), // @[PeripheryBus.scala:56:29] .auto_in_d_ready (_in_xbar_auto_anon_out_d_ready), // @[PeripheryBus.scala:56:29] .auto_in_d_valid (_atomics_auto_in_d_valid), .auto_in_d_bits_opcode (_atomics_auto_in_d_bits_opcode), .auto_in_d_bits_param (_atomics_auto_in_d_bits_param), .auto_in_d_bits_size (_atomics_auto_in_d_bits_size), .auto_in_d_bits_source (_atomics_auto_in_d_bits_source), .auto_in_d_bits_sink (_atomics_auto_in_d_bits_sink), .auto_in_d_bits_denied (_atomics_auto_in_d_bits_denied), .auto_in_d_bits_data (_atomics_auto_in_d_bits_data), .auto_in_d_bits_corrupt (_atomics_auto_in_d_bits_corrupt), .auto_out_a_ready (_buffer_auto_in_a_ready), // @[Buffer.scala:75:28] .auto_out_a_valid (_atomics_auto_out_a_valid), .auto_out_a_bits_opcode (_atomics_auto_out_a_bits_opcode), .auto_out_a_bits_param (_atomics_auto_out_a_bits_param), .auto_out_a_bits_size (_atomics_auto_out_a_bits_size), .auto_out_a_bits_source (_atomics_auto_out_a_bits_source), .auto_out_a_bits_address (_atomics_auto_out_a_bits_address), .auto_out_a_bits_mask (_atomics_auto_out_a_bits_mask), .auto_out_a_bits_data (_atomics_auto_out_a_bits_data), .auto_out_a_bits_corrupt (_atomics_auto_out_a_bits_corrupt), .auto_out_d_ready (_atomics_auto_out_d_ready), .auto_out_d_valid (_buffer_auto_in_d_valid), // @[Buffer.scala:75:28] .auto_out_d_bits_opcode (_buffer_auto_in_d_bits_opcode), // @[Buffer.scala:75:28] .auto_out_d_bits_param (_buffer_auto_in_d_bits_param), // @[Buffer.scala:75:28] .auto_out_d_bits_size (_buffer_auto_in_d_bits_size), // @[Buffer.scala:75:28] .auto_out_d_bits_source (_buffer_auto_in_d_bits_source), // @[Buffer.scala:75:28] .auto_out_d_bits_sink (_buffer_auto_in_d_bits_sink), // @[Buffer.scala:75:28] .auto_out_d_bits_denied (_buffer_auto_in_d_bits_denied), // @[Buffer.scala:75:28] .auto_out_d_bits_data (_buffer_auto_in_d_bits_data), // @[Buffer.scala:75:28] .auto_out_d_bits_corrupt (_buffer_auto_in_d_bits_corrupt) // @[Buffer.scala:75:28] ); // @[AtomicAutomata.scala:289:29] ErrorDeviceWrapper wrapped_error_device ( // @[LazyScope.scala:98:27] .clock (childClock), // @[LazyModuleImp.scala:155:31] .reset (childReset), // @[LazyModuleImp.scala:158:31] .auto_buffer_in_a_ready (_wrapped_error_device_auto_buffer_in_a_ready), .auto_buffer_in_a_valid (_out_xbar_auto_anon_out_0_a_valid), // @[PeripheryBus.scala:57:30] .auto_buffer_in_a_bits_opcode (_out_xbar_auto_anon_out_0_a_bits_opcode), // @[PeripheryBus.scala:57:30] .auto_buffer_in_a_bits_param (_out_xbar_auto_anon_out_0_a_bits_param), // @[PeripheryBus.scala:57:30] .auto_buffer_in_a_bits_size (_out_xbar_auto_anon_out_0_a_bits_size), // @[PeripheryBus.scala:57:30] .auto_buffer_in_a_bits_source (_out_xbar_auto_anon_out_0_a_bits_source), // @[PeripheryBus.scala:57:30] .auto_buffer_in_a_bits_address (_out_xbar_auto_anon_out_0_a_bits_address), // @[PeripheryBus.scala:57:30] .auto_buffer_in_a_bits_mask (_out_xbar_auto_anon_out_0_a_bits_mask), // @[PeripheryBus.scala:57:30] .auto_buffer_in_a_bits_data (_out_xbar_auto_anon_out_0_a_bits_data), // @[PeripheryBus.scala:57:30] .auto_buffer_in_a_bits_corrupt (_out_xbar_auto_anon_out_0_a_bits_corrupt), // @[PeripheryBus.scala:57:30] .auto_buffer_in_d_ready (_out_xbar_auto_anon_out_0_d_ready), // @[PeripheryBus.scala:57:30] .auto_buffer_in_d_valid (_wrapped_error_device_auto_buffer_in_d_valid), .auto_buffer_in_d_bits_opcode (_wrapped_error_device_auto_buffer_in_d_bits_opcode), .auto_buffer_in_d_bits_param (_wrapped_error_device_auto_buffer_in_d_bits_param), .auto_buffer_in_d_bits_size (_wrapped_error_device_auto_buffer_in_d_bits_size), .auto_buffer_in_d_bits_source (_wrapped_error_device_auto_buffer_in_d_bits_source), .auto_buffer_in_d_bits_sink (_wrapped_error_device_auto_buffer_in_d_bits_sink), .auto_buffer_in_d_bits_denied (_wrapped_error_device_auto_buffer_in_d_bits_denied), .auto_buffer_in_d_bits_data (_wrapped_error_device_auto_buffer_in_d_bits_data), .auto_buffer_in_d_bits_corrupt (_wrapped_error_device_auto_buffer_in_d_bits_corrupt) ); // @[LazyScope.scala:98:27] TLInterconnectCoupler_cbus_to_l2_ctrl coupler_to_l2_ctrl ( // @[LazyScope.scala:98:27] .clock (childClock), // @[LazyModuleImp.scala:155:31] .reset (childReset), // @[LazyModuleImp.scala:158:31] .auto_buffer_out_a_ready (auto_coupler_to_l2_ctrl_buffer_out_a_ready_0), // @[ClockDomain.scala:14:9] .auto_buffer_out_a_valid (auto_coupler_to_l2_ctrl_buffer_out_a_valid_0), .auto_buffer_out_a_bits_opcode (auto_coupler_to_l2_ctrl_buffer_out_a_bits_opcode_0), .auto_buffer_out_a_bits_param (auto_coupler_to_l2_ctrl_buffer_out_a_bits_param_0), .auto_buffer_out_a_bits_size (auto_coupler_to_l2_ctrl_buffer_out_a_bits_size_0), .auto_buffer_out_a_bits_source (auto_coupler_to_l2_ctrl_buffer_out_a_bits_source_0), .auto_buffer_out_a_bits_address (auto_coupler_to_l2_ctrl_buffer_out_a_bits_address_0), .auto_buffer_out_a_bits_mask (auto_coupler_to_l2_ctrl_buffer_out_a_bits_mask_0), .auto_buffer_out_a_bits_data (auto_coupler_to_l2_ctrl_buffer_out_a_bits_data_0), .auto_buffer_out_a_bits_corrupt (auto_coupler_to_l2_ctrl_buffer_out_a_bits_corrupt_0), .auto_buffer_out_d_ready (auto_coupler_to_l2_ctrl_buffer_out_d_ready_0), .auto_buffer_out_d_valid (auto_coupler_to_l2_ctrl_buffer_out_d_valid_0), // @[ClockDomain.scala:14:9] .auto_buffer_out_d_bits_opcode (auto_coupler_to_l2_ctrl_buffer_out_d_bits_opcode_0), // @[ClockDomain.scala:14:9] .auto_buffer_out_d_bits_size (auto_coupler_to_l2_ctrl_buffer_out_d_bits_size_0), // @[ClockDomain.scala:14:9] .auto_buffer_out_d_bits_source (auto_coupler_to_l2_ctrl_buffer_out_d_bits_source_0), // @[ClockDomain.scala:14:9] .auto_buffer_out_d_bits_data (auto_coupler_to_l2_ctrl_buffer_out_d_bits_data_0), // @[ClockDomain.scala:14:9] .auto_tl_in_a_ready (_coupler_to_l2_ctrl_auto_tl_in_a_ready), .auto_tl_in_a_valid (_out_xbar_auto_anon_out_1_a_valid), // @[PeripheryBus.scala:57:30] .auto_tl_in_a_bits_opcode (_out_xbar_auto_anon_out_1_a_bits_opcode), // @[PeripheryBus.scala:57:30] .auto_tl_in_a_bits_param (_out_xbar_auto_anon_out_1_a_bits_param), // @[PeripheryBus.scala:57:30] .auto_tl_in_a_bits_size (_out_xbar_auto_anon_out_1_a_bits_size), // @[PeripheryBus.scala:57:30] .auto_tl_in_a_bits_source (_out_xbar_auto_anon_out_1_a_bits_source), // @[PeripheryBus.scala:57:30] .auto_tl_in_a_bits_address (_out_xbar_auto_anon_out_1_a_bits_address), // @[PeripheryBus.scala:57:30] .auto_tl_in_a_bits_mask (_out_xbar_auto_anon_out_1_a_bits_mask), // @[PeripheryBus.scala:57:30] .auto_tl_in_a_bits_data (_out_xbar_auto_anon_out_1_a_bits_data), // @[PeripheryBus.scala:57:30] .auto_tl_in_a_bits_corrupt (_out_xbar_auto_anon_out_1_a_bits_corrupt), // @[PeripheryBus.scala:57:30] .auto_tl_in_d_ready (_out_xbar_auto_anon_out_1_d_ready), // @[PeripheryBus.scala:57:30] .auto_tl_in_d_valid (_coupler_to_l2_ctrl_auto_tl_in_d_valid), .auto_tl_in_d_bits_opcode (_coupler_to_l2_ctrl_auto_tl_in_d_bits_opcode), .auto_tl_in_d_bits_param (_coupler_to_l2_ctrl_auto_tl_in_d_bits_param), .auto_tl_in_d_bits_size (_coupler_to_l2_ctrl_auto_tl_in_d_bits_size), .auto_tl_in_d_bits_source (_coupler_to_l2_ctrl_auto_tl_in_d_bits_source), .auto_tl_in_d_bits_sink (_coupler_to_l2_ctrl_auto_tl_in_d_bits_sink), .auto_tl_in_d_bits_denied (_coupler_to_l2_ctrl_auto_tl_in_d_bits_denied), .auto_tl_in_d_bits_data (_coupler_to_l2_ctrl_auto_tl_in_d_bits_data), .auto_tl_in_d_bits_corrupt (_coupler_to_l2_ctrl_auto_tl_in_d_bits_corrupt) ); // @[LazyScope.scala:98:27] TLInterconnectCoupler_cbus_to_clint coupler_to_clint ( // @[LazyScope.scala:98:27] .clock (childClock), // @[LazyModuleImp.scala:155:31] .reset (childReset), // @[LazyModuleImp.scala:158:31] .auto_fragmenter_anon_out_a_ready (auto_coupler_to_clint_fragmenter_anon_out_a_ready_0), // @[ClockDomain.scala:14:9] .auto_fragmenter_anon_out_a_valid (auto_coupler_to_clint_fragmenter_anon_out_a_valid_0), .auto_fragmenter_anon_out_a_bits_opcode (auto_coupler_to_clint_fragmenter_anon_out_a_bits_opcode_0), .auto_fragmenter_anon_out_a_bits_param (auto_coupler_to_clint_fragmenter_anon_out_a_bits_param_0), .auto_fragmenter_anon_out_a_bits_size (auto_coupler_to_clint_fragmenter_anon_out_a_bits_size_0), .auto_fragmenter_anon_out_a_bits_source (auto_coupler_to_clint_fragmenter_anon_out_a_bits_source_0), .auto_fragmenter_anon_out_a_bits_address (auto_coupler_to_clint_fragmenter_anon_out_a_bits_address_0), .auto_fragmenter_anon_out_a_bits_mask (auto_coupler_to_clint_fragmenter_anon_out_a_bits_mask_0), .auto_fragmenter_anon_out_a_bits_data (auto_coupler_to_clint_fragmenter_anon_out_a_bits_data_0), .auto_fragmenter_anon_out_a_bits_corrupt (auto_coupler_to_clint_fragmenter_anon_out_a_bits_corrupt_0), .auto_fragmenter_anon_out_d_ready (auto_coupler_to_clint_fragmenter_anon_out_d_ready_0), .auto_fragmenter_anon_out_d_valid (auto_coupler_to_clint_fragmenter_anon_out_d_valid_0), // @[ClockDomain.scala:14:9] .auto_fragmenter_anon_out_d_bits_opcode (auto_coupler_to_clint_fragmenter_anon_out_d_bits_opcode_0), // @[ClockDomain.scala:14:9] .auto_fragmenter_anon_out_d_bits_size (auto_coupler_to_clint_fragmenter_anon_out_d_bits_size_0), // @[ClockDomain.scala:14:9] .auto_fragmenter_anon_out_d_bits_source (auto_coupler_to_clint_fragmenter_anon_out_d_bits_source_0), // @[ClockDomain.scala:14:9] .auto_fragmenter_anon_out_d_bits_data (auto_coupler_to_clint_fragmenter_anon_out_d_bits_data_0), // @[ClockDomain.scala:14:9] .auto_tl_in_a_ready (_coupler_to_clint_auto_tl_in_a_ready), .auto_tl_in_a_valid (_out_xbar_auto_anon_out_3_a_valid), // @[PeripheryBus.scala:57:30] .auto_tl_in_a_bits_opcode (_out_xbar_auto_anon_out_3_a_bits_opcode), // @[PeripheryBus.scala:57:30] .auto_tl_in_a_bits_param (_out_xbar_auto_anon_out_3_a_bits_param), // @[PeripheryBus.scala:57:30] .auto_tl_in_a_bits_size (_out_xbar_auto_anon_out_3_a_bits_size), // @[PeripheryBus.scala:57:30] .auto_tl_in_a_bits_source (_out_xbar_auto_anon_out_3_a_bits_source), // @[PeripheryBus.scala:57:30] .auto_tl_in_a_bits_address (_out_xbar_auto_anon_out_3_a_bits_address), // @[PeripheryBus.scala:57:30] .auto_tl_in_a_bits_mask (_out_xbar_auto_anon_out_3_a_bits_mask), // @[PeripheryBus.scala:57:30] .auto_tl_in_a_bits_data (_out_xbar_auto_anon_out_3_a_bits_data), // @[PeripheryBus.scala:57:30] .auto_tl_in_a_bits_corrupt (_out_xbar_auto_anon_out_3_a_bits_corrupt), // @[PeripheryBus.scala:57:30] .auto_tl_in_d_ready (_out_xbar_auto_anon_out_3_d_ready), // @[PeripheryBus.scala:57:30] .auto_tl_in_d_valid (_coupler_to_clint_auto_tl_in_d_valid), .auto_tl_in_d_bits_opcode (_coupler_to_clint_auto_tl_in_d_bits_opcode), .auto_tl_in_d_bits_size (_coupler_to_clint_auto_tl_in_d_bits_size), .auto_tl_in_d_bits_source (_coupler_to_clint_auto_tl_in_d_bits_source), .auto_tl_in_d_bits_data (_coupler_to_clint_auto_tl_in_d_bits_data) ); // @[LazyScope.scala:98:27] TLInterconnectCoupler_cbus_to_plic coupler_to_plic ( // @[LazyScope.scala:98:27] .clock (childClock), // @[LazyModuleImp.scala:155:31] .reset (childReset), // @[LazyModuleImp.scala:158:31] .auto_fragmenter_anon_out_a_ready (auto_coupler_to_plic_fragmenter_anon_out_a_ready_0), // @[ClockDomain.scala:14:9] .auto_fragmenter_anon_out_a_valid (auto_coupler_to_plic_fragmenter_anon_out_a_valid_0), .auto_fragmenter_anon_out_a_bits_opcode (auto_coupler_to_plic_fragmenter_anon_out_a_bits_opcode_0), .auto_fragmenter_anon_out_a_bits_param (auto_coupler_to_plic_fragmenter_anon_out_a_bits_param_0), .auto_fragmenter_anon_out_a_bits_size (auto_coupler_to_plic_fragmenter_anon_out_a_bits_size_0), .auto_fragmenter_anon_out_a_bits_source (auto_coupler_to_plic_fragmenter_anon_out_a_bits_source_0), .auto_fragmenter_anon_out_a_bits_address (auto_coupler_to_plic_fragmenter_anon_out_a_bits_address_0), .auto_fragmenter_anon_out_a_bits_mask (auto_coupler_to_plic_fragmenter_anon_out_a_bits_mask_0), .auto_fragmenter_anon_out_a_bits_data (auto_coupler_to_plic_fragmenter_anon_out_a_bits_data_0), .auto_fragmenter_anon_out_a_bits_corrupt (auto_coupler_to_plic_fragmenter_anon_out_a_bits_corrupt_0), .auto_fragmenter_anon_out_d_ready (auto_coupler_to_plic_fragmenter_anon_out_d_ready_0), .auto_fragmenter_anon_out_d_valid (auto_coupler_to_plic_fragmenter_anon_out_d_valid_0), // @[ClockDomain.scala:14:9] .auto_fragmenter_anon_out_d_bits_opcode (auto_coupler_to_plic_fragmenter_anon_out_d_bits_opcode_0), // @[ClockDomain.scala:14:9] .auto_fragmenter_anon_out_d_bits_size (auto_coupler_to_plic_fragmenter_anon_out_d_bits_size_0), // @[ClockDomain.scala:14:9] .auto_fragmenter_anon_out_d_bits_source (auto_coupler_to_plic_fragmenter_anon_out_d_bits_source_0), // @[ClockDomain.scala:14:9] .auto_fragmenter_anon_out_d_bits_data (auto_coupler_to_plic_fragmenter_anon_out_d_bits_data_0), // @[ClockDomain.scala:14:9] .auto_tl_in_a_ready (_coupler_to_plic_auto_tl_in_a_ready), .auto_tl_in_a_valid (_out_xbar_auto_anon_out_4_a_valid), // @[PeripheryBus.scala:57:30] .auto_tl_in_a_bits_opcode (_out_xbar_auto_anon_out_4_a_bits_opcode), // @[PeripheryBus.scala:57:30] .auto_tl_in_a_bits_param (_out_xbar_auto_anon_out_4_a_bits_param), // @[PeripheryBus.scala:57:30] .auto_tl_in_a_bits_size (_out_xbar_auto_anon_out_4_a_bits_size), // @[PeripheryBus.scala:57:30] .auto_tl_in_a_bits_source (_out_xbar_auto_anon_out_4_a_bits_source), // @[PeripheryBus.scala:57:30] .auto_tl_in_a_bits_address (_out_xbar_auto_anon_out_4_a_bits_address), // @[PeripheryBus.scala:57:30] .auto_tl_in_a_bits_mask (_out_xbar_auto_anon_out_4_a_bits_mask), // @[PeripheryBus.scala:57:30] .auto_tl_in_a_bits_data (_out_xbar_auto_anon_out_4_a_bits_data), // @[PeripheryBus.scala:57:30] .auto_tl_in_a_bits_corrupt (_out_xbar_auto_anon_out_4_a_bits_corrupt), // @[PeripheryBus.scala:57:30] .auto_tl_in_d_ready (_out_xbar_auto_anon_out_4_d_ready), // @[PeripheryBus.scala:57:30] .auto_tl_in_d_valid (_coupler_to_plic_auto_tl_in_d_valid), .auto_tl_in_d_bits_opcode (_coupler_to_plic_auto_tl_in_d_bits_opcode), .auto_tl_in_d_bits_size (_coupler_to_plic_auto_tl_in_d_bits_size), .auto_tl_in_d_bits_source (_coupler_to_plic_auto_tl_in_d_bits_source), .auto_tl_in_d_bits_data (_coupler_to_plic_auto_tl_in_d_bits_data) ); // @[LazyScope.scala:98:27] TLInterconnectCoupler_cbus_to_debug coupler_to_debug ( // @[LazyScope.scala:98:27] .clock (childClock), // @[LazyModuleImp.scala:155:31] .reset (childReset), // @[LazyModuleImp.scala:158:31] .auto_fragmenter_anon_out_a_ready (auto_coupler_to_debug_fragmenter_anon_out_a_ready_0), // @[ClockDomain.scala:14:9] .auto_fragmenter_anon_out_a_valid (auto_coupler_to_debug_fragmenter_anon_out_a_valid_0), .auto_fragmenter_anon_out_a_bits_opcode (auto_coupler_to_debug_fragmenter_anon_out_a_bits_opcode_0), .auto_fragmenter_anon_out_a_bits_param (auto_coupler_to_debug_fragmenter_anon_out_a_bits_param_0), .auto_fragmenter_anon_out_a_bits_size (auto_coupler_to_debug_fragmenter_anon_out_a_bits_size_0), .auto_fragmenter_anon_out_a_bits_source (auto_coupler_to_debug_fragmenter_anon_out_a_bits_source_0), .auto_fragmenter_anon_out_a_bits_address (auto_coupler_to_debug_fragmenter_anon_out_a_bits_address_0), .auto_fragmenter_anon_out_a_bits_mask (auto_coupler_to_debug_fragmenter_anon_out_a_bits_mask_0), .auto_fragmenter_anon_out_a_bits_data (auto_coupler_to_debug_fragmenter_anon_out_a_bits_data_0), .auto_fragmenter_anon_out_a_bits_corrupt (auto_coupler_to_debug_fragmenter_anon_out_a_bits_corrupt_0), .auto_fragmenter_anon_out_d_ready (auto_coupler_to_debug_fragmenter_anon_out_d_ready_0), .auto_fragmenter_anon_out_d_valid (auto_coupler_to_debug_fragmenter_anon_out_d_valid_0), // @[ClockDomain.scala:14:9] .auto_fragmenter_anon_out_d_bits_opcode (auto_coupler_to_debug_fragmenter_anon_out_d_bits_opcode_0), // @[ClockDomain.scala:14:9] .auto_fragmenter_anon_out_d_bits_size (auto_coupler_to_debug_fragmenter_anon_out_d_bits_size_0), // @[ClockDomain.scala:14:9] .auto_fragmenter_anon_out_d_bits_source (auto_coupler_to_debug_fragmenter_anon_out_d_bits_source_0), // @[ClockDomain.scala:14:9] .auto_fragmenter_anon_out_d_bits_data (auto_coupler_to_debug_fragmenter_anon_out_d_bits_data_0), // @[ClockDomain.scala:14:9] .auto_tl_in_a_ready (_coupler_to_debug_auto_tl_in_a_ready), .auto_tl_in_a_valid (_out_xbar_auto_anon_out_5_a_valid), // @[PeripheryBus.scala:57:30] .auto_tl_in_a_bits_opcode (_out_xbar_auto_anon_out_5_a_bits_opcode), // @[PeripheryBus.scala:57:30] .auto_tl_in_a_bits_param (_out_xbar_auto_anon_out_5_a_bits_param), // @[PeripheryBus.scala:57:30] .auto_tl_in_a_bits_size (_out_xbar_auto_anon_out_5_a_bits_size), // @[PeripheryBus.scala:57:30] .auto_tl_in_a_bits_source (_out_xbar_auto_anon_out_5_a_bits_source), // @[PeripheryBus.scala:57:30] .auto_tl_in_a_bits_address (_out_xbar_auto_anon_out_5_a_bits_address), // @[PeripheryBus.scala:57:30] .auto_tl_in_a_bits_mask (_out_xbar_auto_anon_out_5_a_bits_mask), // @[PeripheryBus.scala:57:30] .auto_tl_in_a_bits_data (_out_xbar_auto_anon_out_5_a_bits_data), // @[PeripheryBus.scala:57:30] .auto_tl_in_a_bits_corrupt (_out_xbar_auto_anon_out_5_a_bits_corrupt), // @[PeripheryBus.scala:57:30] .auto_tl_in_d_ready (_out_xbar_auto_anon_out_5_d_ready), // @[PeripheryBus.scala:57:30] .auto_tl_in_d_valid (_coupler_to_debug_auto_tl_in_d_valid), .auto_tl_in_d_bits_opcode (_coupler_to_debug_auto_tl_in_d_bits_opcode), .auto_tl_in_d_bits_size (_coupler_to_debug_auto_tl_in_d_bits_size), .auto_tl_in_d_bits_source (_coupler_to_debug_auto_tl_in_d_bits_source), .auto_tl_in_d_bits_data (_coupler_to_debug_auto_tl_in_d_bits_data) ); // @[LazyScope.scala:98:27] TLInterconnectCoupler_cbus_to_bootrom coupler_to_bootrom ( // @[LazyScope.scala:98:27] .clock (childClock), // @[LazyModuleImp.scala:155:31] .reset (childReset), // @[LazyModuleImp.scala:158:31] .auto_fragmenter_anon_out_a_ready (auto_coupler_to_bootrom_fragmenter_anon_out_a_ready_0), // @[ClockDomain.scala:14:9] .auto_fragmenter_anon_out_a_valid (auto_coupler_to_bootrom_fragmenter_anon_out_a_valid_0), .auto_fragmenter_anon_out_a_bits_opcode (auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_opcode_0), .auto_fragmenter_anon_out_a_bits_param (auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_param_0), .auto_fragmenter_anon_out_a_bits_size (auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_size_0), .auto_fragmenter_anon_out_a_bits_source (auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_source_0), .auto_fragmenter_anon_out_a_bits_address (auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_address_0), .auto_fragmenter_anon_out_a_bits_mask (auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_mask_0), .auto_fragmenter_anon_out_a_bits_data (auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_data_0), .auto_fragmenter_anon_out_a_bits_corrupt (auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_corrupt_0), .auto_fragmenter_anon_out_d_ready (auto_coupler_to_bootrom_fragmenter_anon_out_d_ready_0), .auto_fragmenter_anon_out_d_valid (auto_coupler_to_bootrom_fragmenter_anon_out_d_valid_0), // @[ClockDomain.scala:14:9] .auto_fragmenter_anon_out_d_bits_size (auto_coupler_to_bootrom_fragmenter_anon_out_d_bits_size_0), // @[ClockDomain.scala:14:9] .auto_fragmenter_anon_out_d_bits_source (auto_coupler_to_bootrom_fragmenter_anon_out_d_bits_source_0), // @[ClockDomain.scala:14:9] .auto_fragmenter_anon_out_d_bits_data (auto_coupler_to_bootrom_fragmenter_anon_out_d_bits_data_0), // @[ClockDomain.scala:14:9] .auto_tl_in_a_ready (_coupler_to_bootrom_auto_tl_in_a_ready), .auto_tl_in_a_valid (_out_xbar_auto_anon_out_6_a_valid), // @[PeripheryBus.scala:57:30] .auto_tl_in_a_bits_opcode (_out_xbar_auto_anon_out_6_a_bits_opcode), // @[PeripheryBus.scala:57:30] .auto_tl_in_a_bits_param (_out_xbar_auto_anon_out_6_a_bits_param), // @[PeripheryBus.scala:57:30] .auto_tl_in_a_bits_size (_out_xbar_auto_anon_out_6_a_bits_size), // @[PeripheryBus.scala:57:30] .auto_tl_in_a_bits_source (_out_xbar_auto_anon_out_6_a_bits_source), // @[PeripheryBus.scala:57:30] .auto_tl_in_a_bits_address (_out_xbar_auto_anon_out_6_a_bits_address), // @[PeripheryBus.scala:57:30] .auto_tl_in_a_bits_mask (_out_xbar_auto_anon_out_6_a_bits_mask), // @[PeripheryBus.scala:57:30] .auto_tl_in_a_bits_data (_out_xbar_auto_anon_out_6_a_bits_data), // @[PeripheryBus.scala:57:30] .auto_tl_in_a_bits_corrupt (_out_xbar_auto_anon_out_6_a_bits_corrupt), // @[PeripheryBus.scala:57:30] .auto_tl_in_d_ready (_out_xbar_auto_anon_out_6_d_ready), // @[PeripheryBus.scala:57:30] .auto_tl_in_d_valid (_coupler_to_bootrom_auto_tl_in_d_valid), .auto_tl_in_d_bits_size (_coupler_to_bootrom_auto_tl_in_d_bits_size), .auto_tl_in_d_bits_source (_coupler_to_bootrom_auto_tl_in_d_bits_source), .auto_tl_in_d_bits_data (_coupler_to_bootrom_auto_tl_in_d_bits_data) ); // @[LazyScope.scala:98:27] TLInterconnectCoupler_cbus_to_prci_ctrl coupler_to_prci_ctrl ( // @[LazyScope.scala:98:27] .clock (childClock), // @[LazyModuleImp.scala:155:31] .reset (childReset), // @[LazyModuleImp.scala:158:31] .auto_fixer_anon_out_a_ready (auto_coupler_to_prci_ctrl_fixer_anon_out_a_ready_0), // @[ClockDomain.scala:14:9] .auto_fixer_anon_out_a_valid (auto_coupler_to_prci_ctrl_fixer_anon_out_a_valid_0), .auto_fixer_anon_out_a_bits_opcode (auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_opcode_0), .auto_fixer_anon_out_a_bits_param (auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_param_0), .auto_fixer_anon_out_a_bits_size (auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_size_0), .auto_fixer_anon_out_a_bits_source (auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_source_0), .auto_fixer_anon_out_a_bits_address (auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_address_0), .auto_fixer_anon_out_a_bits_mask (auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_mask_0), .auto_fixer_anon_out_a_bits_data (auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_data_0), .auto_fixer_anon_out_a_bits_corrupt (auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_corrupt_0), .auto_fixer_anon_out_d_ready (auto_coupler_to_prci_ctrl_fixer_anon_out_d_ready_0), .auto_fixer_anon_out_d_valid (auto_coupler_to_prci_ctrl_fixer_anon_out_d_valid_0), // @[ClockDomain.scala:14:9] .auto_fixer_anon_out_d_bits_opcode (auto_coupler_to_prci_ctrl_fixer_anon_out_d_bits_opcode_0), // @[ClockDomain.scala:14:9] .auto_fixer_anon_out_d_bits_size (auto_coupler_to_prci_ctrl_fixer_anon_out_d_bits_size_0), // @[ClockDomain.scala:14:9] .auto_fixer_anon_out_d_bits_source (auto_coupler_to_prci_ctrl_fixer_anon_out_d_bits_source_0), // @[ClockDomain.scala:14:9] .auto_fixer_anon_out_d_bits_data (auto_coupler_to_prci_ctrl_fixer_anon_out_d_bits_data_0), // @[ClockDomain.scala:14:9] .auto_tl_in_a_ready (_coupler_to_prci_ctrl_auto_tl_in_a_ready), .auto_tl_in_a_valid (_out_xbar_auto_anon_out_7_a_valid), // @[PeripheryBus.scala:57:30] .auto_tl_in_a_bits_opcode (_out_xbar_auto_anon_out_7_a_bits_opcode), // @[PeripheryBus.scala:57:30] .auto_tl_in_a_bits_param (_out_xbar_auto_anon_out_7_a_bits_param), // @[PeripheryBus.scala:57:30] .auto_tl_in_a_bits_size (_out_xbar_auto_anon_out_7_a_bits_size), // @[PeripheryBus.scala:57:30] .auto_tl_in_a_bits_source (_out_xbar_auto_anon_out_7_a_bits_source), // @[PeripheryBus.scala:57:30] .auto_tl_in_a_bits_address (_out_xbar_auto_anon_out_7_a_bits_address), // @[PeripheryBus.scala:57:30] .auto_tl_in_a_bits_mask (_out_xbar_auto_anon_out_7_a_bits_mask), // @[PeripheryBus.scala:57:30] .auto_tl_in_a_bits_data (_out_xbar_auto_anon_out_7_a_bits_data), // @[PeripheryBus.scala:57:30] .auto_tl_in_a_bits_corrupt (_out_xbar_auto_anon_out_7_a_bits_corrupt), // @[PeripheryBus.scala:57:30] .auto_tl_in_d_ready (_out_xbar_auto_anon_out_7_d_ready), // @[PeripheryBus.scala:57:30] .auto_tl_in_d_valid (_coupler_to_prci_ctrl_auto_tl_in_d_valid), .auto_tl_in_d_bits_opcode (_coupler_to_prci_ctrl_auto_tl_in_d_bits_opcode), .auto_tl_in_d_bits_param (_coupler_to_prci_ctrl_auto_tl_in_d_bits_param), .auto_tl_in_d_bits_size (_coupler_to_prci_ctrl_auto_tl_in_d_bits_size), .auto_tl_in_d_bits_source (_coupler_to_prci_ctrl_auto_tl_in_d_bits_source), .auto_tl_in_d_bits_sink (_coupler_to_prci_ctrl_auto_tl_in_d_bits_sink), .auto_tl_in_d_bits_denied (_coupler_to_prci_ctrl_auto_tl_in_d_bits_denied), .auto_tl_in_d_bits_data (_coupler_to_prci_ctrl_auto_tl_in_d_bits_data), .auto_tl_in_d_bits_corrupt (_coupler_to_prci_ctrl_auto_tl_in_d_bits_corrupt) ); // @[LazyScope.scala:98:27] assign auto_coupler_to_prci_ctrl_fixer_anon_out_a_valid = auto_coupler_to_prci_ctrl_fixer_anon_out_a_valid_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_opcode = auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_opcode_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_param = auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_param_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_size = auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_size_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_source = auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_source_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_address = auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_address_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_mask = auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_mask_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_data = auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_data_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_corrupt = auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_corrupt_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_prci_ctrl_fixer_anon_out_d_ready = auto_coupler_to_prci_ctrl_fixer_anon_out_d_ready_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bootrom_fragmenter_anon_out_a_valid = auto_coupler_to_bootrom_fragmenter_anon_out_a_valid_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_opcode = auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_opcode_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_param = auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_param_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_size = auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_size_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_source = auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_source_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_address = auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_address_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_mask = auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_mask_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_data = auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_data_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_corrupt = auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_corrupt_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bootrom_fragmenter_anon_out_d_ready = auto_coupler_to_bootrom_fragmenter_anon_out_d_ready_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_debug_fragmenter_anon_out_a_valid = auto_coupler_to_debug_fragmenter_anon_out_a_valid_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_debug_fragmenter_anon_out_a_bits_opcode = auto_coupler_to_debug_fragmenter_anon_out_a_bits_opcode_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_debug_fragmenter_anon_out_a_bits_param = auto_coupler_to_debug_fragmenter_anon_out_a_bits_param_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_debug_fragmenter_anon_out_a_bits_size = auto_coupler_to_debug_fragmenter_anon_out_a_bits_size_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_debug_fragmenter_anon_out_a_bits_source = auto_coupler_to_debug_fragmenter_anon_out_a_bits_source_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_debug_fragmenter_anon_out_a_bits_address = auto_coupler_to_debug_fragmenter_anon_out_a_bits_address_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_debug_fragmenter_anon_out_a_bits_mask = auto_coupler_to_debug_fragmenter_anon_out_a_bits_mask_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_debug_fragmenter_anon_out_a_bits_data = auto_coupler_to_debug_fragmenter_anon_out_a_bits_data_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_debug_fragmenter_anon_out_a_bits_corrupt = auto_coupler_to_debug_fragmenter_anon_out_a_bits_corrupt_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_debug_fragmenter_anon_out_d_ready = auto_coupler_to_debug_fragmenter_anon_out_d_ready_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_plic_fragmenter_anon_out_a_valid = auto_coupler_to_plic_fragmenter_anon_out_a_valid_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_plic_fragmenter_anon_out_a_bits_opcode = auto_coupler_to_plic_fragmenter_anon_out_a_bits_opcode_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_plic_fragmenter_anon_out_a_bits_param = auto_coupler_to_plic_fragmenter_anon_out_a_bits_param_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_plic_fragmenter_anon_out_a_bits_size = auto_coupler_to_plic_fragmenter_anon_out_a_bits_size_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_plic_fragmenter_anon_out_a_bits_source = auto_coupler_to_plic_fragmenter_anon_out_a_bits_source_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_plic_fragmenter_anon_out_a_bits_address = auto_coupler_to_plic_fragmenter_anon_out_a_bits_address_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_plic_fragmenter_anon_out_a_bits_mask = auto_coupler_to_plic_fragmenter_anon_out_a_bits_mask_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_plic_fragmenter_anon_out_a_bits_data = auto_coupler_to_plic_fragmenter_anon_out_a_bits_data_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_plic_fragmenter_anon_out_a_bits_corrupt = auto_coupler_to_plic_fragmenter_anon_out_a_bits_corrupt_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_plic_fragmenter_anon_out_d_ready = auto_coupler_to_plic_fragmenter_anon_out_d_ready_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_clint_fragmenter_anon_out_a_valid = auto_coupler_to_clint_fragmenter_anon_out_a_valid_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_clint_fragmenter_anon_out_a_bits_opcode = auto_coupler_to_clint_fragmenter_anon_out_a_bits_opcode_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_clint_fragmenter_anon_out_a_bits_param = auto_coupler_to_clint_fragmenter_anon_out_a_bits_param_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_clint_fragmenter_anon_out_a_bits_size = auto_coupler_to_clint_fragmenter_anon_out_a_bits_size_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_clint_fragmenter_anon_out_a_bits_source = auto_coupler_to_clint_fragmenter_anon_out_a_bits_source_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_clint_fragmenter_anon_out_a_bits_address = auto_coupler_to_clint_fragmenter_anon_out_a_bits_address_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_clint_fragmenter_anon_out_a_bits_mask = auto_coupler_to_clint_fragmenter_anon_out_a_bits_mask_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_clint_fragmenter_anon_out_a_bits_data = auto_coupler_to_clint_fragmenter_anon_out_a_bits_data_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_clint_fragmenter_anon_out_a_bits_corrupt = auto_coupler_to_clint_fragmenter_anon_out_a_bits_corrupt_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_clint_fragmenter_anon_out_d_ready = auto_coupler_to_clint_fragmenter_anon_out_d_ready_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bus_named_pbus_bus_xing_out_a_valid = auto_coupler_to_bus_named_pbus_bus_xing_out_a_valid_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_opcode = auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_opcode_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_param = auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_param_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_size = auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_size_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_source = auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_source_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_address = auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_address_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_mask = auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_mask_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_data = auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_data_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_corrupt = auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_corrupt_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bus_named_pbus_bus_xing_out_d_ready = auto_coupler_to_bus_named_pbus_bus_xing_out_d_ready_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_l2_ctrl_buffer_out_a_valid = auto_coupler_to_l2_ctrl_buffer_out_a_valid_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_l2_ctrl_buffer_out_a_bits_opcode = auto_coupler_to_l2_ctrl_buffer_out_a_bits_opcode_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_l2_ctrl_buffer_out_a_bits_param = auto_coupler_to_l2_ctrl_buffer_out_a_bits_param_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_l2_ctrl_buffer_out_a_bits_size = auto_coupler_to_l2_ctrl_buffer_out_a_bits_size_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_l2_ctrl_buffer_out_a_bits_source = auto_coupler_to_l2_ctrl_buffer_out_a_bits_source_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_l2_ctrl_buffer_out_a_bits_address = auto_coupler_to_l2_ctrl_buffer_out_a_bits_address_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_l2_ctrl_buffer_out_a_bits_mask = auto_coupler_to_l2_ctrl_buffer_out_a_bits_mask_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_l2_ctrl_buffer_out_a_bits_data = auto_coupler_to_l2_ctrl_buffer_out_a_bits_data_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_l2_ctrl_buffer_out_a_bits_corrupt = auto_coupler_to_l2_ctrl_buffer_out_a_bits_corrupt_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_l2_ctrl_buffer_out_d_ready = auto_coupler_to_l2_ctrl_buffer_out_d_ready_0; // @[ClockDomain.scala:14:9] assign auto_fixedClockNode_anon_out_5_clock = auto_fixedClockNode_anon_out_5_clock_0; // @[ClockDomain.scala:14:9] assign auto_fixedClockNode_anon_out_5_reset = auto_fixedClockNode_anon_out_5_reset_0; // @[ClockDomain.scala:14:9] assign auto_fixedClockNode_anon_out_4_clock = auto_fixedClockNode_anon_out_4_clock_0; // @[ClockDomain.scala:14:9] assign auto_fixedClockNode_anon_out_4_reset = auto_fixedClockNode_anon_out_4_reset_0; // @[ClockDomain.scala:14:9] assign auto_fixedClockNode_anon_out_3_clock = auto_fixedClockNode_anon_out_3_clock_0; // @[ClockDomain.scala:14:9] assign auto_fixedClockNode_anon_out_3_reset = auto_fixedClockNode_anon_out_3_reset_0; // @[ClockDomain.scala:14:9] assign auto_fixedClockNode_anon_out_2_clock = auto_fixedClockNode_anon_out_2_clock_0; // @[ClockDomain.scala:14:9] assign auto_fixedClockNode_anon_out_2_reset = auto_fixedClockNode_anon_out_2_reset_0; // @[ClockDomain.scala:14:9] assign auto_fixedClockNode_anon_out_1_clock = auto_fixedClockNode_anon_out_1_clock_0; // @[ClockDomain.scala:14:9] assign auto_fixedClockNode_anon_out_1_reset = auto_fixedClockNode_anon_out_1_reset_0; // @[ClockDomain.scala:14:9] assign auto_fixedClockNode_anon_out_0_clock = auto_fixedClockNode_anon_out_0_clock_0; // @[ClockDomain.scala:14:9] assign auto_fixedClockNode_anon_out_0_reset = auto_fixedClockNode_anon_out_0_reset_0; // @[ClockDomain.scala:14:9] assign auto_bus_xing_in_a_ready = auto_bus_xing_in_a_ready_0; // @[ClockDomain.scala:14:9] assign auto_bus_xing_in_d_valid = auto_bus_xing_in_d_valid_0; // @[ClockDomain.scala:14:9] assign auto_bus_xing_in_d_bits_opcode = auto_bus_xing_in_d_bits_opcode_0; // @[ClockDomain.scala:14:9] assign auto_bus_xing_in_d_bits_param = auto_bus_xing_in_d_bits_param_0; // @[ClockDomain.scala:14:9] assign auto_bus_xing_in_d_bits_size = auto_bus_xing_in_d_bits_size_0; // @[ClockDomain.scala:14:9] assign auto_bus_xing_in_d_bits_source = auto_bus_xing_in_d_bits_source_0; // @[ClockDomain.scala:14:9] assign auto_bus_xing_in_d_bits_sink = auto_bus_xing_in_d_bits_sink_0; // @[ClockDomain.scala:14:9] assign auto_bus_xing_in_d_bits_denied = auto_bus_xing_in_d_bits_denied_0; // @[ClockDomain.scala:14:9] assign auto_bus_xing_in_d_bits_data = auto_bus_xing_in_d_bits_data_0; // @[ClockDomain.scala:14:9] assign auto_bus_xing_in_d_bits_corrupt = auto_bus_xing_in_d_bits_corrupt_0; // @[ClockDomain.scala:14:9] endmodule
Generate the Verilog code corresponding to the following Chisel files. File Monitor.scala: package constellation.channel import chisel3._ import chisel3.util._ import freechips.rocketchip.diplomacy._ import org.chipsalliance.cde.config.{Parameters} import freechips.rocketchip.util._ import constellation.noc.{HasNoCParams} class NoCMonitor(val cParam: ChannelParams)(implicit val p: Parameters) extends Module with HasNoCParams { val io = IO(new Bundle { val in = Input(new Channel(cParam)) }) val in_flight = RegInit(VecInit(Seq.fill(cParam.nVirtualChannels) { false.B })) for (i <- 0 until cParam.srcSpeedup) { val flit = io.in.flit(i) when (flit.valid) { when (flit.bits.head) { in_flight(flit.bits.virt_channel_id) := true.B assert (!in_flight(flit.bits.virt_channel_id), "Flit head/tail sequencing is broken") } when (flit.bits.tail) { in_flight(flit.bits.virt_channel_id) := false.B } } val possibleFlows = cParam.possibleFlows when (flit.valid && flit.bits.head) { cParam match { case n: ChannelParams => n.virtualChannelParams.zipWithIndex.foreach { case (v,i) => assert(flit.bits.virt_channel_id =/= i.U \|\| v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR) } case _ => assert(cParam.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR) } } } } File Types.scala: package constellation.routing import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.{Parameters} import constellation.noc.{HasNoCParams} import constellation.channel.{Flit} /** A representation for 1 specific virtual channel in wormhole routing * * @param src the source node * @param vc ID for the virtual channel * @param dst the destination node * @param n_vc the number of virtual channels / // BEGIN: ChannelRoutingInfo case class ChannelRoutingInfo( src: Int, dst: Int, vc: Int, n_vc: Int ) { // END: ChannelRoutingInfo require (src >= -1 && dst >= -1 && vc >= 0, s"Illegal $this") require (!(src == -1 && dst == -1), s"Illegal $this") require (vc < n_vc, s"Illegal $this") val isIngress = src == -1 val isEgress = dst == -1 } /* Represents the properties of a packet that are relevant for routing * ingressId and egressId uniquely identify a flow, but vnet and dst are used here * to simplify the implementation of routingrelations * * @param ingressId packet's source ingress point * @param egressId packet's destination egress point * @param vNet virtual subnetwork identifier * @param dst packet's destination node ID */ // BEGIN: FlowRoutingInfo case class FlowRoutingInfo( ingressId: Int, egressId: Int, vNetId: Int, ingressNode: Int, ingressNodeId: Int, egressNode: Int, egressNodeId: Int, fifo: Boolean ) { // END: FlowRoutingInfo def isFlow(f: FlowRoutingBundle): Bool = { (f.ingress_node === ingressNode.U && f.egress_node === egressNode.U && f.ingress_node_id === ingressNodeId.U && f.egress_node_id === egressNodeId.U) } def asLiteral(b: FlowRoutingBundle): BigInt = { Seq( (vNetId , b.vnet_id), (ingressNode , b.ingress_node), (ingressNodeId , b.ingress_node_id), (egressNode , b.egress_node), (egressNodeId , b.egress_node_id) ).foldLeft(0)((l, t) => { (l << t._2.getWidth) \| t._1 }) } } class FlowRoutingBundle(implicit val p: Parameters) extends Bundle with HasNoCParams { // Instead of tracking ingress/egress ID, track the physical destination id and the offset at the destination // This simplifies the routing tables val vnet_id = UInt(log2Ceil(nVirtualNetworks).W) val ingress_node = UInt(log2Ceil(nNodes).W) val ingress_node_id = UInt(log2Ceil(maxIngressesAtNode).W) val egress_node = UInt(log2Ceil(nNodes).W) val egress_node_id = UInt(log2Ceil(maxEgressesAtNode).W) }	module NoCMonitor_53( // @[Monitor.scala:11:7] input clock, // @[Monitor.scala:11:7] input reset, // @[Monitor.scala:11:7] input io_in_flit_0_valid, // @[Monitor.scala:12:14] input io_in_flit_0_bits_head, // @[Monitor.scala:12:14] input io_in_flit_0_bits_tail, // @[Monitor.scala:12:14] input [5:0] io_in_flit_0_bits_flow_ingress_node, // @[Monitor.scala:12:14] input [2:0] io_in_flit_0_bits_flow_ingress_node_id, // @[Monitor.scala:12:14] input [5:0] io_in_flit_0_bits_flow_egress_node, // @[Monitor.scala:12:14] input [2:0] io_in_flit_0_bits_flow_egress_node_id, // @[Monitor.scala:12:14] input [4:0] io_in_flit_0_bits_virt_channel_id // @[Monitor.scala:12:14] ); reg in_flight_0; // @[Monitor.scala:16:26] reg in_flight_1; // @[Monitor.scala:16:26] reg in_flight_2; // @[Monitor.scala:16:26] reg in_flight_3; // @[Monitor.scala:16:26] reg in_flight_4; // @[Monitor.scala:16:26] reg in_flight_5; // @[Monitor.scala:16:26] reg in_flight_6; // @[Monitor.scala:16:26] reg in_flight_7; // @[Monitor.scala:16:26] reg in_flight_8; // @[Monitor.scala:16:26] reg in_flight_9; // @[Monitor.scala:16:26] reg in_flight_10; // @[Monitor.scala:16:26] reg in_flight_11; // @[Monitor.scala:16:26] reg in_flight_12; // @[Monitor.scala:16:26] reg in_flight_13; // @[Monitor.scala:16:26] reg in_flight_14; // @[Monitor.scala:16:26] reg in_flight_15; // @[Monitor.scala:16:26] reg in_flight_16; // @[Monitor.scala:16:26] reg in_flight_17; // @[Monitor.scala:16:26] reg in_flight_18; // @[Monitor.scala:16:26] reg in_flight_19; // @[Monitor.scala:16:26] reg in_flight_20; // @[Monitor.scala:16:26] reg in_flight_21; // @[Monitor.scala:16:26] wire _GEN = io_in_flit_0_bits_virt_channel_id == 5'h0; // @[Monitor.scala:21:46] wire _GEN_0 = io_in_flit_0_bits_virt_channel_id == 5'h1; // @[Monitor.scala:21:46] wire _GEN_1 = io_in_flit_0_bits_virt_channel_id == 5'h2; // @[Monitor.scala:21:46] wire _GEN_2 = io_in_flit_0_bits_virt_channel_id == 5'h3; // @[Monitor.scala:21:46] wire _GEN_3 = io_in_flit_0_bits_virt_channel_id == 5'h4; // @[Monitor.scala:21:46] wire _GEN_4 = io_in_flit_0_bits_virt_channel_id == 5'h5; // @[Monitor.scala:21:46] wire _GEN_5 = io_in_flit_0_bits_virt_channel_id == 5'h6; // @[Monitor.scala:21:46] wire _GEN_6 = io_in_flit_0_bits_virt_channel_id == 5'h7; // @[Monitor.scala:21:46] wire _GEN_7 = io_in_flit_0_bits_virt_channel_id == 5'h8; // @[Monitor.scala:21:46] wire _GEN_8 = io_in_flit_0_bits_virt_channel_id == 5'h9; // @[Monitor.scala:21:46] wire _GEN_9 = io_in_flit_0_bits_virt_channel_id == 5'hA; // @[Monitor.scala:21:46] wire _GEN_10 = io_in_flit_0_bits_virt_channel_id == 5'hB; // @[Monitor.scala:21:46] wire _GEN_11 = io_in_flit_0_bits_virt_channel_id == 5'hE; // @[Monitor.scala:21:46] wire _GEN_12 = io_in_flit_0_bits_virt_channel_id == 5'hF; // @[Monitor.scala:21:46] wire _GEN_13 = io_in_flit_0_bits_virt_channel_id == 5'h12; // @[Monitor.scala:21:46] wire _GEN_14 = io_in_flit_0_bits_virt_channel_id == 5'h13; // @[Monitor.scala:21:46]
Generate the Verilog code corresponding to the following Chisel files. File Fragmenter.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.diplomacy.{AddressSet, BufferParams, IdRange, TransferSizes} import freechips.rocketchip.util.{Repeater, OH1ToUInt, UIntToOH1} import scala.math.min import freechips.rocketchip.util.DataToAugmentedData object EarlyAck { sealed trait T case object AllPuts extends T case object PutFulls extends T case object None extends T } // minSize: minimum size of transfers supported by all outward managers // maxSize: maximum size of transfers supported after the Fragmenter is applied // alwaysMin: fragment all requests down to minSize (else fragment to maximum supported by manager) // earlyAck: should a multibeat Put should be acknowledged on the first beat or last beat // holdFirstDeny: allow the Fragmenter to unsafely combine multibeat Gets by taking the first denied for the whole burst // nameSuffix: appends a suffix to the module name // Fragmenter modifies: PutFull, PutPartial, LogicalData, Get, Hint // Fragmenter passes: ArithmeticData (truncated to minSize if alwaysMin) // Fragmenter cannot modify acquire (could livelock); thus it is unsafe to put caches on both sides class TLFragmenter(val minSize: Int, val maxSize: Int, val alwaysMin: Boolean = false, val earlyAck: EarlyAck.T = EarlyAck.None, val holdFirstDeny: Boolean = false, val nameSuffix: Option[String] = None)(implicit p: Parameters) extends LazyModule { require(isPow2 (maxSize), s"TLFragmenter expects pow2(maxSize), but got $maxSize") require(isPow2 (minSize), s"TLFragmenter expects pow2(minSize), but got $minSize") require(minSize <= maxSize, s"TLFragmenter expects min <= max, but got $minSize > $maxSize") val fragmentBits = log2Ceil(maxSize / minSize) val fullBits = if (earlyAck == EarlyAck.PutFulls) 1 else 0 val toggleBits = 1 val addedBits = fragmentBits + toggleBits + fullBits def expandTransfer(x: TransferSizes, op: String) = if (!x) x else { // validate that we can apply the fragmenter correctly require (x.max >= minSize, s"TLFragmenter (with parent $parent) max transfer size $op(${x.max}) must be >= min transfer size (${minSize})") TransferSizes(x.min, maxSize) } private def noChangeRequired = minSize == maxSize private def shrinkTransfer(x: TransferSizes) = if (!alwaysMin) x else if (x.min <= minSize) TransferSizes(x.min, min(minSize, x.max)) else TransferSizes.none private def mapManager(m: TLSlaveParameters) = m.v1copy( supportsArithmetic = shrinkTransfer(m.supportsArithmetic), supportsLogical = shrinkTransfer(m.supportsLogical), supportsGet = expandTransfer(m.supportsGet, "Get"), supportsPutFull = expandTransfer(m.supportsPutFull, "PutFull"), supportsPutPartial = expandTransfer(m.supportsPutPartial, "PutParital"), supportsHint = expandTransfer(m.supportsHint, "Hint")) val node = new TLAdapterNode( // We require that all the responses are mutually FIFO // Thus we need to compact all of the masters into one big master clientFn = { c => (if (noChangeRequired) c else c.v2copy( masters = Seq(TLMasterParameters.v2( name = "TLFragmenter", sourceId = IdRange(0, if (minSize == maxSize) c.endSourceId else (c.endSourceId << addedBits)), requestFifo = true, emits = TLMasterToSlaveTransferSizes( acquireT = shrinkTransfer(c.masters.map(_.emits.acquireT) .reduce(_ mincover _)), acquireB = shrinkTransfer(c.masters.map(_.emits.acquireB) .reduce(_ mincover _)), arithmetic = shrinkTransfer(c.masters.map(_.emits.arithmetic).reduce(_ mincover _)), logical = shrinkTransfer(c.masters.map(_.emits.logical) .reduce(_ mincover _)), get = shrinkTransfer(c.masters.map(_.emits.get) .reduce(_ mincover _)), putFull = shrinkTransfer(c.masters.map(_.emits.putFull) .reduce(_ mincover _)), putPartial = shrinkTransfer(c.masters.map(_.emits.putPartial).reduce(_ mincover _)), hint = shrinkTransfer(c.masters.map(_.emits.hint) .reduce(_ mincover _)) ) )) ))}, managerFn = { m => if (noChangeRequired) m else m.v2copy(slaves = m.slaves.map(mapManager)) } ) { override def circuitIdentity = noChangeRequired } lazy val module = new Impl class Impl extends LazyModuleImp(this) { override def desiredName = (Seq("TLFragmenter") ++ nameSuffix).mkString("_") (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => if (noChangeRequired) { out <> in } else { // All managers must share a common FIFO domain (responses might end up interleaved) val manager = edgeOut.manager val managers = manager.managers val beatBytes = manager.beatBytes val fifoId = managers(0).fifoId require (fifoId.isDefined && managers.map(_.fifoId == fifoId).reduce(_ && _)) require (!manager.anySupportAcquireB \|\| !edgeOut.client.anySupportProbe, s"TLFragmenter (with parent $parent) can't fragment a caching client's requests into a cacheable region") require (minSize >= beatBytes, s"TLFragmenter (with parent $parent) can't support fragmenting ($minSize) to sub-beat ($beatBytes) accesses") // We can't support devices which are cached on both sides of us require (!edgeOut.manager.anySupportAcquireB \|\| !edgeIn.client.anySupportProbe) // We can't support denied because we reassemble fragments require (!edgeOut.manager.mayDenyGet \|\| holdFirstDeny, s"TLFragmenter (with parent $parent) can't support denials without holdFirstDeny=true") require (!edgeOut.manager.mayDenyPut \|\| earlyAck == EarlyAck.None) /* The Fragmenter is a bit tricky, because there are 5 sizes in play: * max size -- the maximum transfer size possible * orig size -- the original pre-fragmenter size * frag size -- the modified post-fragmenter size * min size -- the threshold below which frag=orig * beat size -- the amount transfered on any given beat * * The relationships are as follows: * max >= orig >= frag * max > min >= beat * It IS possible that orig <= min (then frag=orig; ie: no fragmentation) * * The fragment# (sent via TL.source) is measured in multiples of min size. * Meanwhile, to track the progress, counters measure in multiples of beat size. * * Here is an example of a bus with max=256, min=8, beat=4 and a device supporting 16. * * in.A out.A (frag#) out.D (frag#) in.D gen# ack# * get64 get16 6 ackD16 6 ackD64 12 15 * ackD16 6 ackD64 14 * ackD16 6 ackD64 13 * ackD16 6 ackD64 12 * get16 4 ackD16 4 ackD64 8 11 * ackD16 4 ackD64 10 * ackD16 4 ackD64 9 * ackD16 4 ackD64 8 * get16 2 ackD16 2 ackD64 4 7 * ackD16 2 ackD64 6 * ackD16 2 ackD64 5 * ackD16 2 ackD64 4 * get16 0 ackD16 0 ackD64 0 3 * ackD16 0 ackD64 2 * ackD16 0 ackD64 1 * ackD16 0 ackD64 0 * * get8 get8 0 ackD8 0 ackD8 0 1 * ackD8 0 ackD8 0 * * get4 get4 0 ackD4 0 ackD4 0 0 * get1 get1 0 ackD1 0 ackD1 0 0 * * put64 put16 6 15 * put64 put16 6 14 * put64 put16 6 13 * put64 put16 6 ack16 6 12 12 * put64 put16 4 11 * put64 put16 4 10 * put64 put16 4 9 * put64 put16 4 ack16 4 8 8 * put64 put16 2 7 * put64 put16 2 6 * put64 put16 2 5 * put64 put16 2 ack16 2 4 4 * put64 put16 0 3 * put64 put16 0 2 * put64 put16 0 1 * put64 put16 0 ack16 0 ack64 0 0 * * put8 put8 0 1 * put8 put8 0 ack8 0 ack8 0 0 * * put4 put4 0 ack4 0 ack4 0 0 * put1 put1 0 ack1 0 ack1 0 0 / val counterBits = log2Up(maxSize/beatBytes) val maxDownSize = if (alwaysMin) minSize else min(manager.maxTransfer, maxSize) // Consider the following waveform for two 4-beat bursts: // ---A----A------------ // -------D-----DDD-DDDD // Under TL rules, the second A can use the same source as the first A, // because the source is released for reuse on the first response beat. // // However, if we fragment the requests, it looks like this: // ---3210-3210--------- // -------3-----210-3210 // ... now we've broken the rules because 210 are twice inflight. // // This phenomenon means we can have essentially 2maxSize/minSize-1 // fragmented transactions in flight per original transaction source. // // To keep the source unique, we encode the beat counter in the low // bits of the source. To solve the overlap, we use a toggle bit. // Whatever toggle bit the D is reassembling, A will use the opposite. // First, handle the return path val acknum = RegInit(0.U(counterBits.W)) val dOrig = Reg(UInt()) val dToggle = RegInit(false.B) val dFragnum = out.d.bits.source(fragmentBits-1, 0) val dFirst = acknum === 0.U val dLast = dFragnum === 0.U // only for AccessAck (!Data) val dsizeOH = UIntToOH (out.d.bits.size, log2Ceil(maxDownSize)+1) val dsizeOH1 = UIntToOH1(out.d.bits.size, log2Up(maxDownSize)) val dHasData = edgeOut.hasData(out.d.bits) // calculate new acknum val acknum_fragment = dFragnum << log2Ceil(minSize/beatBytes) val acknum_size = dsizeOH1 >> log2Ceil(beatBytes) assert (!out.d.valid \|\| (acknum_fragment & acknum_size) === 0.U) val dFirst_acknum = acknum_fragment \| Mux(dHasData, acknum_size, 0.U) val ack_decrement = Mux(dHasData, 1.U, dsizeOH >> log2Ceil(beatBytes)) // calculate the original size val dFirst_size = OH1ToUInt((dFragnum << log2Ceil(minSize)) \| dsizeOH1) when (out.d.fire) { acknum := Mux(dFirst, dFirst_acknum, acknum - ack_decrement) when (dFirst) { dOrig := dFirst_size dToggle := out.d.bits.source(fragmentBits) } } // Swallow up non-data ack fragments val doEarlyAck = earlyAck match { case EarlyAck.AllPuts => true.B case EarlyAck.PutFulls => out.d.bits.source(fragmentBits+1) case EarlyAck.None => false.B } val drop = !dHasData && !Mux(doEarlyAck, dFirst, dLast) out.d.ready := in.d.ready \|\| drop in.d.valid := out.d.valid && !drop in.d.bits := out.d.bits // pass most stuff unchanged in.d.bits.source := out.d.bits.source >> addedBits in.d.bits.size := Mux(dFirst, dFirst_size, dOrig) if (edgeOut.manager.mayDenyPut) { val r_denied = Reg(Bool()) val d_denied = (!dFirst && r_denied) \|\| out.d.bits.denied when (out.d.fire) { r_denied := d_denied } in.d.bits.denied := d_denied } if (edgeOut.manager.mayDenyGet) { // Take denied only from the first beat and hold that value val d_denied = out.d.bits.denied holdUnless dFirst when (dHasData) { in.d.bits.denied := d_denied in.d.bits.corrupt := d_denied \|\| out.d.bits.corrupt } } // What maximum transfer sizes do downstream devices support? val maxArithmetics = managers.map(_.supportsArithmetic.max) val maxLogicals = managers.map(_.supportsLogical.max) val maxGets = managers.map(_.supportsGet.max) val maxPutFulls = managers.map(_.supportsPutFull.max) val maxPutPartials = managers.map(_.supportsPutPartial.max) val maxHints = managers.map(m => if (m.supportsHint) maxDownSize else 0) // We assume that the request is valid => size 0 is impossible val lgMinSize = log2Ceil(minSize).U val maxLgArithmetics = maxArithmetics.map(m => if (m == 0) lgMinSize else log2Ceil(m).U) val maxLgLogicals = maxLogicals .map(m => if (m == 0) lgMinSize else log2Ceil(m).U) val maxLgGets = maxGets .map(m => if (m == 0) lgMinSize else log2Ceil(m).U) val maxLgPutFulls = maxPutFulls .map(m => if (m == 0) lgMinSize else log2Ceil(m).U) val maxLgPutPartials = maxPutPartials.map(m => if (m == 0) lgMinSize else log2Ceil(m).U) val maxLgHints = maxHints .map(m => if (m == 0) lgMinSize else log2Ceil(m).U) // Make the request repeatable val repeater = Module(new Repeater(in.a.bits)) repeater.io.enq <> in.a val in_a = repeater.io.deq // If this is infront of a single manager, these become constants val find = manager.findFast(edgeIn.address(in_a.bits)) val maxLgArithmetic = Mux1H(find, maxLgArithmetics) val maxLgLogical = Mux1H(find, maxLgLogicals) val maxLgGet = Mux1H(find, maxLgGets) val maxLgPutFull = Mux1H(find, maxLgPutFulls) val maxLgPutPartial = Mux1H(find, maxLgPutPartials) val maxLgHint = Mux1H(find, maxLgHints) val limit = if (alwaysMin) lgMinSize else MuxLookup(in_a.bits.opcode, lgMinSize)(Array( TLMessages.PutFullData -> maxLgPutFull, TLMessages.PutPartialData -> maxLgPutPartial, TLMessages.ArithmeticData -> maxLgArithmetic, TLMessages.LogicalData -> maxLgLogical, TLMessages.Get -> maxLgGet, TLMessages.Hint -> maxLgHint)) val aOrig = in_a.bits.size val aFrag = Mux(aOrig > limit, limit, aOrig) val aOrigOH1 = UIntToOH1(aOrig, log2Ceil(maxSize)) val aFragOH1 = UIntToOH1(aFrag, log2Up(maxDownSize)) val aHasData = edgeIn.hasData(in_a.bits) val aMask = Mux(aHasData, 0.U, aFragOH1) val gennum = RegInit(0.U(counterBits.W)) val aFirst = gennum === 0.U val old_gennum1 = Mux(aFirst, aOrigOH1 >> log2Ceil(beatBytes), gennum - 1.U) val new_gennum = ~(~old_gennum1 \| (aMask >> log2Ceil(beatBytes))) // ~(~x\|y) is width safe val aFragnum = ~(~(old_gennum1 >> log2Ceil(minSize/beatBytes)) \| (aFragOH1 >> log2Ceil(minSize))) val aLast = aFragnum === 0.U val aToggle = !Mux(aFirst, dToggle, RegEnable(dToggle, aFirst)) val aFull = if (earlyAck == EarlyAck.PutFulls) Some(in_a.bits.opcode === TLMessages.PutFullData) else None when (out.a.fire) { gennum := new_gennum } repeater.io.repeat := !aHasData && aFragnum =/= 0.U out.a <> in_a out.a.bits.address := in_a.bits.address \| ~(old_gennum1 << log2Ceil(beatBytes) \| ~aOrigOH1 \| aFragOH1 \| (minSize-1).U) out.a.bits.source := Cat(Seq(in_a.bits.source) ++ aFull ++ Seq(aToggle.asUInt, aFragnum)) out.a.bits.size := aFrag // Optimize away some of the Repeater's registers assert (!repeater.io.full \|\| !aHasData) out.a.bits.data := in.a.bits.data val fullMask = ((BigInt(1) << beatBytes) - 1).U assert (!repeater.io.full \|\| in_a.bits.mask === fullMask) out.a.bits.mask := Mux(repeater.io.full, fullMask, in.a.bits.mask) out.a.bits.user.waiveAll :<= in.a.bits.user.subset(_.isData) // Tie off unused channels in.b.valid := false.B in.c.ready := true.B in.e.ready := true.B out.b.ready := true.B out.c.valid := false.B out.e.valid := false.B } } } } object TLFragmenter { def apply(minSize: Int, maxSize: Int, alwaysMin: Boolean = false, earlyAck: EarlyAck.T = EarlyAck.None, holdFirstDeny: Boolean = false, nameSuffix: Option[String] = None)(implicit p: Parameters): TLNode = { if (minSize <= maxSize) { val fragmenter = LazyModule(new TLFragmenter(minSize, maxSize, alwaysMin, earlyAck, holdFirstDeny, nameSuffix)) fragmenter.node } else { TLEphemeralNode()(ValName("no_fragmenter")) } } def apply(wrapper: TLBusWrapper, nameSuffix: Option[String])(implicit p: Parameters): TLNode = apply(wrapper.beatBytes, wrapper.blockBytes, nameSuffix = nameSuffix) def apply(wrapper: TLBusWrapper)(implicit p: Parameters): TLNode = apply(wrapper, None) } // Synthesizable unit tests import freechips.rocketchip.unittest._ class TLRAMFragmenter(ramBeatBytes: Int, maxSize: Int, txns: Int)(implicit p: Parameters) extends LazyModule { val fuzz = LazyModule(new TLFuzzer(txns)) val model = LazyModule(new TLRAMModel("Fragmenter")) val ram = LazyModule(new TLRAM(AddressSet(0x0, 0x3ff), beatBytes = ramBeatBytes)) (ram.node := TLDelayer(0.1) := TLBuffer(BufferParams.flow) := TLDelayer(0.1) := TLFragmenter(ramBeatBytes, maxSize, earlyAck = EarlyAck.AllPuts) := TLDelayer(0.1) := TLBuffer(BufferParams.flow) := TLFragmenter(ramBeatBytes, maxSize/2) := TLDelayer(0.1) := TLBuffer(BufferParams.flow) := model.node := fuzz.node) lazy val module = new Impl class Impl extends LazyModuleImp(this) with UnitTestModule { io.finished := fuzz.module.io.finished } } class TLRAMFragmenterTest(ramBeatBytes: Int, maxSize: Int, txns: Int = 5000, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) { val dut = Module(LazyModule(new TLRAMFragmenter(ramBeatBytes,maxSize,txns)).module) io.finished := dut.io.finished dut.io.start := io.start } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /* Like Vec.apply(idx), but tolerates indices of mismatched width / def extract(idx: UInt): T = x((idx \| 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx \| 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def \| (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a \|\| b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_\|\|_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /* Any Data subtype that has a Bool member named valid. / type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /* converts from camel case to to underscores, also removing all spaces / def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /* converts spaces or underscores to hyphens, also lowering case / def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y \| (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y \|\| y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 \| 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /* Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation / def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Nodes.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.nodes._ import freechips.rocketchip.util.{AsyncQueueParams,RationalDirection} case object TLMonitorBuilder extends Field[TLMonitorArgs => TLMonitorBase](args => new TLMonitor(args)) object TLImp extends NodeImp[TLMasterPortParameters, TLSlavePortParameters, TLEdgeOut, TLEdgeIn, TLBundle] { def edgeO(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeOut(pd, pu, p, sourceInfo) def edgeI(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeIn (pd, pu, p, sourceInfo) def bundleO(eo: TLEdgeOut) = TLBundle(eo.bundle) def bundleI(ei: TLEdgeIn) = TLBundle(ei.bundle) def render(ei: TLEdgeIn) = RenderedEdge(colour = "#000000" / black /, label = (ei.manager.beatBytes 8).toString) override def monitor(bundle: TLBundle, edge: TLEdgeIn): Unit = { val monitor = Module(edge.params(TLMonitorBuilder)(TLMonitorArgs(edge))) monitor.io.in := bundle } override def mixO(pd: TLMasterPortParameters, node: OutwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLMasterPortParameters = pd.v1copy(clients = pd.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }) override def mixI(pu: TLSlavePortParameters, node: InwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLSlavePortParameters = pu.v1copy(managers = pu.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }) } trait TLFormatNode extends FormatNode[TLEdgeIn, TLEdgeOut] case class TLClientNode(portParams: Seq[TLMasterPortParameters])(implicit valName: ValName) extends SourceNode(TLImp)(portParams) with TLFormatNode case class TLManagerNode(portParams: Seq[TLSlavePortParameters])(implicit valName: ValName) extends SinkNode(TLImp)(portParams) with TLFormatNode case class TLAdapterNode( clientFn: TLMasterPortParameters => TLMasterPortParameters = { s => s }, managerFn: TLSlavePortParameters => TLSlavePortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLImp)(clientFn, managerFn) with TLFormatNode case class TLJunctionNode( clientFn: Seq[TLMasterPortParameters] => Seq[TLMasterPortParameters], managerFn: Seq[TLSlavePortParameters] => Seq[TLSlavePortParameters])( implicit valName: ValName) extends JunctionNode(TLImp)(clientFn, managerFn) with TLFormatNode case class TLIdentityNode()(implicit valName: ValName) extends IdentityNode(TLImp)() with TLFormatNode object TLNameNode { def apply(name: ValName) = TLIdentityNode()(name) def apply(name: Option[String]): TLIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLIdentityNode = apply(Some(name)) } case class TLEphemeralNode()(implicit valName: ValName) extends EphemeralNode(TLImp)() object TLTempNode { def apply(): TLEphemeralNode = TLEphemeralNode()(ValName("temp")) } case class TLNexusNode( clientFn: Seq[TLMasterPortParameters] => TLMasterPortParameters, managerFn: Seq[TLSlavePortParameters] => TLSlavePortParameters)( implicit valName: ValName) extends NexusNode(TLImp)(clientFn, managerFn) with TLFormatNode abstract class TLCustomNode(implicit valName: ValName) extends CustomNode(TLImp) with TLFormatNode // Asynchronous crossings trait TLAsyncFormatNode extends FormatNode[TLAsyncEdgeParameters, TLAsyncEdgeParameters] object TLAsyncImp extends SimpleNodeImp[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncEdgeParameters, TLAsyncBundle] { def edge(pd: TLAsyncClientPortParameters, pu: TLAsyncManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLAsyncEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLAsyncEdgeParameters) = new TLAsyncBundle(e.bundle) def render(e: TLAsyncEdgeParameters) = RenderedEdge(colour = "#ff0000" /* red /, label = e.manager.async.depth.toString) override def mixO(pd: TLAsyncClientPortParameters, node: OutwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLAsyncManagerPortParameters, node: InwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLAsyncAdapterNode( clientFn: TLAsyncClientPortParameters => TLAsyncClientPortParameters = { s => s }, managerFn: TLAsyncManagerPortParameters => TLAsyncManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLAsyncImp)(clientFn, managerFn) with TLAsyncFormatNode case class TLAsyncIdentityNode()(implicit valName: ValName) extends IdentityNode(TLAsyncImp)() with TLAsyncFormatNode object TLAsyncNameNode { def apply(name: ValName) = TLAsyncIdentityNode()(name) def apply(name: Option[String]): TLAsyncIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLAsyncIdentityNode = apply(Some(name)) } case class TLAsyncSourceNode(sync: Option[Int])(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLAsyncImp)( dFn = { p => TLAsyncClientPortParameters(p) }, uFn = { p => p.base.v1copy(minLatency = p.base.minLatency + sync.getOrElse(p.async.sync)) }) with FormatNode[TLEdgeIn, TLAsyncEdgeParameters] // discard cycles in other clock domain case class TLAsyncSinkNode(async: AsyncQueueParams)(implicit valName: ValName) extends MixedAdapterNode(TLAsyncImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = p.base.minLatency + async.sync) }, uFn = { p => TLAsyncManagerPortParameters(async, p) }) with FormatNode[TLAsyncEdgeParameters, TLEdgeOut] // Rationally related crossings trait TLRationalFormatNode extends FormatNode[TLRationalEdgeParameters, TLRationalEdgeParameters] object TLRationalImp extends SimpleNodeImp[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalEdgeParameters, TLRationalBundle] { def edge(pd: TLRationalClientPortParameters, pu: TLRationalManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLRationalEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLRationalEdgeParameters) = new TLRationalBundle(e.bundle) def render(e: TLRationalEdgeParameters) = RenderedEdge(colour = "#00ff00" / green /) override def mixO(pd: TLRationalClientPortParameters, node: OutwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLRationalManagerPortParameters, node: InwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLRationalAdapterNode( clientFn: TLRationalClientPortParameters => TLRationalClientPortParameters = { s => s }, managerFn: TLRationalManagerPortParameters => TLRationalManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLRationalImp)(clientFn, managerFn) with TLRationalFormatNode case class TLRationalIdentityNode()(implicit valName: ValName) extends IdentityNode(TLRationalImp)() with TLRationalFormatNode object TLRationalNameNode { def apply(name: ValName) = TLRationalIdentityNode()(name) def apply(name: Option[String]): TLRationalIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLRationalIdentityNode = apply(Some(name)) } case class TLRationalSourceNode()(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLRationalImp)( dFn = { p => TLRationalClientPortParameters(p) }, uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLRationalEdgeParameters] // discard cycles from other clock domain case class TLRationalSinkNode(direction: RationalDirection)(implicit valName: ValName) extends MixedAdapterNode(TLRationalImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = 1) }, uFn = { p => TLRationalManagerPortParameters(direction, p) }) with FormatNode[TLRationalEdgeParameters, TLEdgeOut] // Credited version of TileLink channels trait TLCreditedFormatNode extends FormatNode[TLCreditedEdgeParameters, TLCreditedEdgeParameters] object TLCreditedImp extends SimpleNodeImp[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedEdgeParameters, TLCreditedBundle] { def edge(pd: TLCreditedClientPortParameters, pu: TLCreditedManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLCreditedEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLCreditedEdgeParameters) = new TLCreditedBundle(e.bundle) def render(e: TLCreditedEdgeParameters) = RenderedEdge(colour = "#ffff00" / yellow /, e.delay.toString) override def mixO(pd: TLCreditedClientPortParameters, node: OutwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLCreditedManagerPortParameters, node: InwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLCreditedAdapterNode( clientFn: TLCreditedClientPortParameters => TLCreditedClientPortParameters = { s => s }, managerFn: TLCreditedManagerPortParameters => TLCreditedManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLCreditedImp)(clientFn, managerFn) with TLCreditedFormatNode case class TLCreditedIdentityNode()(implicit valName: ValName) extends IdentityNode(TLCreditedImp)() with TLCreditedFormatNode object TLCreditedNameNode { def apply(name: ValName) = TLCreditedIdentityNode()(name) def apply(name: Option[String]): TLCreditedIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLCreditedIdentityNode = apply(Some(name)) } case class TLCreditedSourceNode(delay: TLCreditedDelay)(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLCreditedImp)( dFn = { p => TLCreditedClientPortParameters(delay, p) }, uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLCreditedEdgeParameters] // discard cycles from other clock domain case class TLCreditedSinkNode(delay: TLCreditedDelay)(implicit valName: ValName) extends MixedAdapterNode(TLCreditedImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = 1) }, uFn = { p => TLCreditedManagerPortParameters(delay, p) }) with FormatNode[TLCreditedEdgeParameters, TLEdgeOut] File LazyModuleImp.scala: package org.chipsalliance.diplomacy.lazymodule import chisel3.{withClockAndReset, Module, RawModule, Reset, _} import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo} import firrtl.passes.InlineAnnotation import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.nodes.Dangle import scala.collection.immutable.SortedMap /* Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]]. * * This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy. / sealed trait LazyModuleImpLike extends RawModule { /* [[LazyModule]] that contains this instance. / val wrapper: LazyModule /* IOs that will be automatically "punched" for this instance. / val auto: AutoBundle /* The metadata that describes the [[HalfEdge]]s which generated [[auto]]. / protected[diplomacy] val dangles: Seq[Dangle] // [[wrapper.module]] had better not be accessed while LazyModules are still being built! require( LazyModule.scope.isEmpty, s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}" ) /* Set module name. Defaults to the containing LazyModule's desiredName. / override def desiredName: String = wrapper.desiredName suggestName(wrapper.suggestedName) /* [[Parameters]] for chisel [[Module]]s. / implicit val p: Parameters = wrapper.p /* instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and * submodules. / protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = { // 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]], // 2. return [[Dangle]]s from each module. val childDangles = wrapper.children.reverse.flatMap { c => implicit val sourceInfo: SourceInfo = c.info c.cloneProto.map { cp => // If the child is a clone, then recursively set cloneProto of its children as well def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = { require(bases.size == clones.size) (bases.zip(clones)).map { case (l, r) => require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}") l.cloneProto = Some(r) assignCloneProtos(l.children, r.children) } } assignCloneProtos(c.children, cp.children) // Clone the child module as a record, and get its [[AutoBundle]] val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName) val clonedAuto = clone("auto").asInstanceOf[AutoBundle] // Get the empty [[Dangle]]'s of the cloned child val rawDangles = c.cloneDangles() require(rawDangles.size == clonedAuto.elements.size) // Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) } dangles }.getOrElse { // For non-clones, instantiate the child module val mod = try { Module(c.module) } catch { case e: ChiselException => { println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}") throw e } } mod.dangles } } // Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]]. // This will result in a sequence of [[Dangle]] from these [[BaseNode]]s. val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate()) // Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]] val allDangles = nodeDangles ++ childDangles // Group [[allDangles]] by their [[source]]. val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _) // For each [[source]] set of [[Dangle]]s of size 2, ensure that these // can be connected as a source-sink pair (have opposite flipped value). // Make the connection and mark them as [[done]]. val done = Set() ++ pairing.values.filter(_.size == 2).map { case Seq(a, b) => require(a.flipped != b.flipped) // @todo <> in chisel3 makes directionless connection. if (a.flipped) { a.data <> b.data } else { b.data <> a.data } a.source case _ => None } // Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module. val forward = allDangles.filter(d => !done(d.source)) // Generate [[AutoBundle]] IO from [[forward]]. val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _)) // Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]] val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) => if (d.flipped) { d.data <> io } else { io <> d.data } d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name) } // Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]]. wrapper.inModuleBody.reverse.foreach { _() } if (wrapper.shouldBeInlined) { chisel3.experimental.annotate(new ChiselAnnotation { def toFirrtl = InlineAnnotation(toNamed) }) } // Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]]. (auto, dangles) } } /* Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. / class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike { /* Instantiate hardware of this `Module`. / val (auto, dangles) = instantiate() } /* Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. / class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike { // These wires are the default clock+reset for all LazyModule children. // It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the // [[LazyRawModuleImp]] children. // Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly. /* drive clock explicitly. / val childClock: Clock = Wire(Clock()) /* drive reset explicitly. */ val childReset: Reset = Wire(Reset()) // the default is that these are disabled childClock := false.B.asClock childReset := chisel3.DontCare def provideImplicitClockToLazyChildren: Boolean = false val (auto, dangles) = if (provideImplicitClockToLazyChildren) { withClockAndReset(childClock, childReset) { instantiate() } } else { instantiate() } }	module TLFragmenter_TileResetSetter( // @[Fragmenter.scala:92:9] input clock, // @[Fragmenter.scala:92:9] input reset, // @[Fragmenter.scala:92:9] output auto_anon_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_anon_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [6:0] auto_anon_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [20:0] auto_anon_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_anon_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input auto_anon_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_anon_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_anon_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [6:0] auto_anon_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output [63:0] auto_anon_in_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_anon_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_anon_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [1:0] auto_anon_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [10:0] auto_anon_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [20:0] auto_anon_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_anon_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output auto_anon_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_anon_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_anon_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_anon_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [10:0] auto_anon_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input [63:0] auto_anon_out_d_bits_data // @[LazyModuleImp.scala:107:25] ); wire _repeater_io_full; // @[Fragmenter.scala:274:30] wire _repeater_io_enq_ready; // @[Fragmenter.scala:274:30] wire _repeater_io_deq_valid; // @[Fragmenter.scala:274:30] wire [2:0] _repeater_io_deq_bits_opcode; // @[Fragmenter.scala:274:30] wire [2:0] _repeater_io_deq_bits_size; // @[Fragmenter.scala:274:30] wire [6:0] _repeater_io_deq_bits_source; // @[Fragmenter.scala:274:30] wire [20:0] _repeater_io_deq_bits_address; // @[Fragmenter.scala:274:30] wire [7:0] _repeater_io_deq_bits_mask; // @[Fragmenter.scala:274:30] reg [2:0] acknum; // @[Fragmenter.scala:201:29] reg [2:0] dOrig; // @[Fragmenter.scala:202:24] reg dToggle; // @[Fragmenter.scala:203:30] wire dFirst = acknum == 3'h0; // @[Fragmenter.scala:201:29, :205:29] wire [5:0] _dsizeOH1_T = 6'h7 << auto_anon_out_d_bits_size; // @[package.scala:243:71] wire [2:0] _GEN = ~(auto_anon_out_d_bits_source[2:0]); // @[package.scala:241:49] wire [2:0] dFirst_size_hi = auto_anon_out_d_bits_source[2:0] & {1'h1, _GEN[2:1]}; // @[OneHot.scala:30:18] wire [2:0] _dFirst_size_T_8 = {1'h0, dFirst_size_hi[2:1]} \| ~(_dsizeOH1_T[2:0]) & {_GEN[0], _dsizeOH1_T[2:1]}; // @[OneHot.scala:30:18, :31:18, :32:28] wire [2:0] dFirst_size = {\|dFirst_size_hi, \|(_dFirst_size_T_8[2:1]), _dFirst_size_T_8[2] \| _dFirst_size_T_8[0]}; // @[OneHot.scala:30:18, :31:18, :32:{10,14,28}] wire drop = ~(auto_anon_out_d_bits_opcode[0]) & (\|(auto_anon_out_d_bits_source[2:0])); // @[Fragmenter.scala:204:41, :206:30, :234:{20,30}] wire anonOut_d_ready = auto_anon_in_d_ready \| drop; // @[Fragmenter.scala:234:30, :235:35] wire anonIn_d_valid = auto_anon_out_d_valid & ~drop; // @[Fragmenter.scala:234:30, :236:{36,39}] wire [2:0] anonIn_d_bits_size = dFirst ? dFirst_size : dOrig; // @[OneHot.scala:32:10] wire [12:0] _aOrigOH1_T = 13'h3F << _repeater_io_deq_bits_size; // @[package.scala:243:71] reg [2:0] gennum; // @[Fragmenter.scala:303:29] wire aFirst = gennum == 3'h0; // @[Fragmenter.scala:303:29, :304:29] wire [2:0] aFragnum = aFirst ? ~(_aOrigOH1_T[5:3]) : gennum - 3'h1; // @[package.scala:243:{46,71,76}] reg aToggle_r; // @[Fragmenter.scala:309:54]
Generate the Verilog code corresponding to the following Chisel files. File ShiftReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ // Similar to the Chisel ShiftRegister but allows the user to suggest a // name to the registers that get instantiated, and // to provide a reset value. object ShiftRegInit { def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T = (0 until n).foldRight(in) { case (i, next) => { val r = RegNext(next, init) name.foreach { na => r.suggestName(s"${na}_${i}") } r } } } /** These wrap behavioral * shift registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * The different types vary in their reset behavior: * AsyncResetShiftReg -- Asynchronously reset register array * A W(width) x D(depth) sized array is constructed from D instantiations of a * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg, * but only used for timing applications */ abstract class AbstractPipelineReg(w: Int = 1) extends Module { val io = IO(new Bundle { val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) } ) } object AbstractPipelineReg { def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = { val chain = Module(gen) name.foreach{ chain.suggestName(_) } chain.io.d := in.asUInt chain.io.q.asTypeOf(in) } } class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) { require(depth > 0, "Depth must be greater than 0.") override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}" val chain = List.tabulate(depth) { i => Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}") } chain.last.io.d := io.d chain.last.io.en := true.B (chain.init zip chain.tail).foreach { case (sink, source) => sink.io.d := source.io.q sink.io.en := true.B } io.q := chain.head.io.q } object AsyncResetShiftReg { def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name) def apply [T <: Data](in: T, depth: Int, name: Option[String]): T = apply(in, depth, 0, name) def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T = apply(in, depth, init.litValue.toInt, name) def apply [T <: Data](in: T, depth: Int, init: T): T = apply (in, depth, init.litValue.toInt, None) } File AsyncQueue.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ case class AsyncQueueParams( depth: Int = 8, sync: Int = 3, safe: Boolean = true, // If safe is true, then effort is made to resynchronize the crossing indices when either side is reset. // This makes it safe/possible to reset one side of the crossing (but not the other) when the queue is empty. narrow: Boolean = false) // If narrow is true then the read mux is moved to the source side of the crossing. // This reduces the number of level shifters in the case where the clock crossing is also a voltage crossing, // at the expense of a combinational path from the sink to the source and back to the sink. { require (depth > 0 && isPow2(depth)) require (sync >= 2) val bits = log2Ceil(depth) val wires = if (narrow) 1 else depth } object AsyncQueueParams { // When there is only one entry, we don't need narrow. def singleton(sync: Int = 3, safe: Boolean = true) = AsyncQueueParams(1, sync, safe, false) } class AsyncBundleSafety extends Bundle { val ridx_valid = Input (Bool()) val widx_valid = Output(Bool()) val source_reset_n = Output(Bool()) val sink_reset_n = Input (Bool()) } class AsyncBundle[T <: Data](private val gen: T, val params: AsyncQueueParams = AsyncQueueParams()) extends Bundle { // Data-path synchronization val mem = Output(Vec(params.wires, gen)) val ridx = Input (UInt((params.bits+1).W)) val widx = Output(UInt((params.bits+1).W)) val index = params.narrow.option(Input(UInt(params.bits.W))) // Signals used to self-stabilize a safe AsyncQueue val safe = params.safe.option(new AsyncBundleSafety) } object GrayCounter { def apply(bits: Int, increment: Bool = true.B, clear: Bool = false.B, name: String = "binary"): UInt = { val incremented = Wire(UInt(bits.W)) val binary = RegNext(next=incremented, init=0.U).suggestName(name) incremented := Mux(clear, 0.U, binary + increment.asUInt) incremented ^ (incremented >> 1) } } class AsyncValidSync(sync: Int, desc: String) extends RawModule { val io = IO(new Bundle { val in = Input(Bool()) val out = Output(Bool()) }) val clock = IO(Input(Clock())) val reset = IO(Input(AsyncReset())) withClockAndReset(clock, reset){ io.out := AsyncResetSynchronizerShiftReg(io.in, sync, Some(desc)) } } class AsyncQueueSource[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module { override def desiredName = s"AsyncQueueSource_${gen.typeName}" val io = IO(new Bundle { // These come from the source domain val enq = Flipped(Decoupled(gen)) // These cross to the sink clock domain val async = new AsyncBundle(gen, params) }) val bits = params.bits val sink_ready = WireInit(true.B) val mem = Reg(Vec(params.depth, gen)) // This does NOT need to be reset at all. val widx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.enq.fire, !sink_ready, "widx_bin")) val ridx = AsyncResetSynchronizerShiftReg(io.async.ridx, params.sync, Some("ridx_gray")) val ready = sink_ready && widx =/= (ridx ^ (params.depth \| params.depth >> 1).U) val index = if (bits == 0) 0.U else io.async.widx(bits-1, 0) ^ (io.async.widx(bits, bits) << (bits-1)) when (io.enq.fire) { mem(index) := io.enq.bits } val ready_reg = withReset(reset.asAsyncReset)(RegNext(next=ready, init=false.B).suggestName("ready_reg")) io.enq.ready := ready_reg && sink_ready val widx_reg = withReset(reset.asAsyncReset)(RegNext(next=widx, init=0.U).suggestName("widx_gray")) io.async.widx := widx_reg io.async.index match { case Some(index) => io.async.mem(0) := mem(index) case None => io.async.mem := mem } io.async.safe.foreach { sio => val source_valid_0 = Module(new AsyncValidSync(params.sync, "source_valid_0")) val source_valid_1 = Module(new AsyncValidSync(params.sync, "source_valid_1")) val sink_extend = Module(new AsyncValidSync(params.sync, "sink_extend")) val sink_valid = Module(new AsyncValidSync(params.sync, "sink_valid")) source_valid_0.reset := (reset.asBool \|\| !sio.sink_reset_n).asAsyncReset source_valid_1.reset := (reset.asBool \|\| !sio.sink_reset_n).asAsyncReset sink_extend .reset := (reset.asBool \|\| !sio.sink_reset_n).asAsyncReset sink_valid .reset := reset.asAsyncReset source_valid_0.clock := clock source_valid_1.clock := clock sink_extend .clock := clock sink_valid .clock := clock source_valid_0.io.in := true.B source_valid_1.io.in := source_valid_0.io.out sio.widx_valid := source_valid_1.io.out sink_extend.io.in := sio.ridx_valid sink_valid.io.in := sink_extend.io.out sink_ready := sink_valid.io.out sio.source_reset_n := !reset.asBool // Assert that if there is stuff in the queue, then reset cannot happen // Impossible to write because dequeue can occur on the receiving side, // then reset allowed to happen, but write side cannot know that dequeue // occurred. // TODO: write some sort of sanity check assertion for users // that denote don't reset when there is activity // assert (!(reset \|\| !sio.sink_reset_n) \|\| !io.enq.valid, "Enqueue while sink is reset and AsyncQueueSource is unprotected") // assert (!reset_rise \|\| prev_idx_match.asBool, "Sink reset while AsyncQueueSource not empty") } } class AsyncQueueSink[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module { override def desiredName = s"AsyncQueueSink_${gen.typeName}" val io = IO(new Bundle { // These come from the sink domain val deq = Decoupled(gen) // These cross to the source clock domain val async = Flipped(new AsyncBundle(gen, params)) }) val bits = params.bits val source_ready = WireInit(true.B) val ridx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.deq.fire, !source_ready, "ridx_bin")) val widx = AsyncResetSynchronizerShiftReg(io.async.widx, params.sync, Some("widx_gray")) val valid = source_ready && ridx =/= widx // The mux is safe because timing analysis ensures ridx has reached the register // On an ASIC, changes to the unread location cannot affect the selected value // On an FPGA, only one input changes at a time => mem updates don't cause glitches // The register only latches when the selected valued is not being written val index = if (bits == 0) 0.U else ridx(bits-1, 0) ^ (ridx(bits, bits) << (bits-1)) io.async.index.foreach { _ := index } // This register does not NEED to be reset, as its contents will not // be considered unless the asynchronously reset deq valid register is set. // It is possible that bits latches when the source domain is reset / has power cut // This is safe, because isolation gates brought mem low before the zeroed widx reached us val deq_bits_nxt = io.async.mem(if (params.narrow) 0.U else index) io.deq.bits := ClockCrossingReg(deq_bits_nxt, en = valid, doInit = false, name = Some("deq_bits_reg")) val valid_reg = withReset(reset.asAsyncReset)(RegNext(next=valid, init=false.B).suggestName("valid_reg")) io.deq.valid := valid_reg && source_ready val ridx_reg = withReset(reset.asAsyncReset)(RegNext(next=ridx, init=0.U).suggestName("ridx_gray")) io.async.ridx := ridx_reg io.async.safe.foreach { sio => val sink_valid_0 = Module(new AsyncValidSync(params.sync, "sink_valid_0")) val sink_valid_1 = Module(new AsyncValidSync(params.sync, "sink_valid_1")) val source_extend = Module(new AsyncValidSync(params.sync, "source_extend")) val source_valid = Module(new AsyncValidSync(params.sync, "source_valid")) sink_valid_0 .reset := (reset.asBool \|\| !sio.source_reset_n).asAsyncReset sink_valid_1 .reset := (reset.asBool \|\| !sio.source_reset_n).asAsyncReset source_extend.reset := (reset.asBool \|\| !sio.source_reset_n).asAsyncReset source_valid .reset := reset.asAsyncReset sink_valid_0 .clock := clock sink_valid_1 .clock := clock source_extend.clock := clock source_valid .clock := clock sink_valid_0.io.in := true.B sink_valid_1.io.in := sink_valid_0.io.out sio.ridx_valid := sink_valid_1.io.out source_extend.io.in := sio.widx_valid source_valid.io.in := source_extend.io.out source_ready := source_valid.io.out sio.sink_reset_n := !reset.asBool // TODO: write some sort of sanity check assertion for users // that denote don't reset when there is activity // // val reset_and_extend = !source_ready \|\| !sio.source_reset_n \|\| reset.asBool // val reset_and_extend_prev = RegNext(reset_and_extend, true.B) // val reset_rise = !reset_and_extend_prev && reset_and_extend // val prev_idx_match = AsyncResetReg(updateData=(io.async.widx===io.async.ridx), resetData=0) // assert (!reset_rise \|\| prev_idx_match.asBool, "Source reset while AsyncQueueSink not empty") } } object FromAsyncBundle { // Sometimes it makes sense for the sink to have different sync than the source def apply[T <: Data](x: AsyncBundle[T]): DecoupledIO[T] = apply(x, x.params.sync) def apply[T <: Data](x: AsyncBundle[T], sync: Int): DecoupledIO[T] = { val sink = Module(new AsyncQueueSink(chiselTypeOf(x.mem(0)), x.params.copy(sync = sync))) sink.io.async <> x sink.io.deq } } object ToAsyncBundle { def apply[T <: Data](x: ReadyValidIO[T], params: AsyncQueueParams = AsyncQueueParams()): AsyncBundle[T] = { val source = Module(new AsyncQueueSource(chiselTypeOf(x.bits), params)) source.io.enq <> x source.io.async } } class AsyncQueue[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Crossing[T] { val io = IO(new CrossingIO(gen)) val source = withClockAndReset(io.enq_clock, io.enq_reset) { Module(new AsyncQueueSource(gen, params)) } val sink = withClockAndReset(io.deq_clock, io.deq_reset) { Module(new AsyncQueueSink (gen, params)) } source.io.enq <> io.enq io.deq <> sink.io.deq sink.io.async <> source.io.async }	module AsyncValidSync_28( // @[AsyncQueue.scala:58:7] output io_out, // @[AsyncQueue.scala:59:14] input clock, // @[AsyncQueue.scala:63:17] input reset // @[AsyncQueue.scala:64:17] ); wire io_in = 1'h1; // @[ShiftReg.scala:45:23] wire _io_out_WIRE; // @[ShiftReg.scala:48:24] wire io_out_0; // @[AsyncQueue.scala:58:7] assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24] AsyncResetSynchronizerShiftReg_w1_d3_i0_38 io_out_sink_valid_0 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (reset), .io_q (_io_out_WIRE) ); // @[ShiftReg.scala:45:23] assign io_out = io_out_0; // @[AsyncQueue.scala:58:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File ShiftReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ // Similar to the Chisel ShiftRegister but allows the user to suggest a // name to the registers that get instantiated, and // to provide a reset value. object ShiftRegInit { def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T = (0 until n).foldRight(in) { case (i, next) => { val r = RegNext(next, init) name.foreach { na => r.suggestName(s"${na}_${i}") } r } } } /** These wrap behavioral * shift registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * The different types vary in their reset behavior: * AsyncResetShiftReg -- Asynchronously reset register array * A W(width) x D(depth) sized array is constructed from D instantiations of a * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg, * but only used for timing applications / abstract class AbstractPipelineReg(w: Int = 1) extends Module { val io = IO(new Bundle { val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) } ) } object AbstractPipelineReg { def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = { val chain = Module(gen) name.foreach{ chain.suggestName(_) } chain.io.d := in.asUInt chain.io.q.asTypeOf(in) } } class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) { require(depth > 0, "Depth must be greater than 0.") override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}" val chain = List.tabulate(depth) { i => Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}") } chain.last.io.d := io.d chain.last.io.en := true.B (chain.init zip chain.tail).foreach { case (sink, source) => sink.io.d := source.io.q sink.io.en := true.B } io.q := chain.head.io.q } object AsyncResetShiftReg { def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name) def apply [T <: Data](in: T, depth: Int, name: Option[String]): T = apply(in, depth, 0, name) def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T = apply(in, depth, init.litValue.toInt, name) def apply [T <: Data](in: T, depth: Int, init: T): T = apply (in, depth, init.litValue.toInt, None) } File SynchronizerReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util.{RegEnable, Cat} /* These wrap behavioral * shift and next registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * * These are built up of ResetSynchronizerPrimitiveShiftReg, intended to be replaced by the integrator's metastable flops chains or replaced * at this level if they have a multi-bit wide synchronizer primitive. * The different types vary in their reset behavior: * NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin * AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep * 1-bit-wide shift registers. * SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg * * [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference. * * ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross * Clock Domains. */ object SynchronizerResetType extends Enumeration { val NonSync, Inferred, Sync, Async = Value } // Note: this should not be used directly. // Use the companion object to generate this with the correct reset type mixin. private class SynchronizerPrimitiveShiftReg( sync: Int, init: Boolean, resetType: SynchronizerResetType.Value) extends AbstractPipelineReg(1) { val initInt = if (init) 1 else 0 val initPostfix = resetType match { case SynchronizerResetType.NonSync => "" case _ => s"_i${initInt}" } override def desiredName = s"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}" val chain = List.tabulate(sync) { i => val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B) reg.suggestName(s"sync_$i") } chain.last := io.d.asBool (chain.init zip chain.tail).foreach { case (sink, source) => sink := source } io.q := chain.head.asUInt } private object SynchronizerPrimitiveShiftReg { def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = { val gen: () => SynchronizerPrimitiveShiftReg = resetType match { case SynchronizerResetType.NonSync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) case SynchronizerResetType.Async => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset case SynchronizerResetType.Sync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset case SynchronizerResetType.Inferred => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) } AbstractPipelineReg(gen(), in) } } // Note: This module may end up with a non-AsyncReset type reset. // But the Primitives within will always have AsyncReset type. class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asAsyncReset){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async) } } io.q := Cat(output.reverse) } object AsyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } // Note: This module may end up with a non-Bool type reset. // But the Primitives within will always have Bool reset type. @deprecated("SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.", "rocket-chip 1.2") class SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asBool){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync) } } io.q := Cat(output.reverse) } object SyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred) } io.q := Cat(output.reverse) } object ResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}" val output = Seq.tabulate(w) { i => SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync) } io.q := Cat(output.reverse) } object SynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, None) def apply [T <: Data](in: T): T = apply (in, 3, None) } class ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module { override def desiredName = s"ClockCrossingReg_w${w}" val io = IO(new Bundle{ val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) val en = Input(Bool()) }) val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en) io.q := cdc_reg } object ClockCrossingReg { def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = { val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit)) name.foreach{ cdc_reg.suggestName(_) } cdc_reg.io.d := in.asUInt cdc_reg.io.en := en cdc_reg.io.q.asTypeOf(in) } }	module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_103( // @[SynchronizerReg.scala:68:19] input clock, // @[SynchronizerReg.scala:68:19] input reset, // @[SynchronizerReg.scala:68:19] output io_q // @[ShiftReg.scala:36:14] ); wire io_d = 1'h1; // @[SynchronizerReg.scala:54:22, :68:19] wire _sync_2_T = 1'h1; // @[SynchronizerReg.scala:54:22, :68:19] wire io_q_0; // @[SynchronizerReg.scala:68:19] reg sync_0; // @[SynchronizerReg.scala:51:87] assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19] reg sync_1; // @[SynchronizerReg.scala:51:87] reg sync_2; // @[SynchronizerReg.scala:51:87] always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19] if (reset) begin // @[SynchronizerReg.scala:68:19] sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87] end else begin // @[SynchronizerReg.scala:68:19] sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87] sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87] sync_2 <= 1'h1; // @[SynchronizerReg.scala:51:87, :54:22, :68:19] end always @(posedge, posedge)
Generate the Verilog code corresponding to the following Chisel files. File SinkC.scala: /* * Copyright 2019 SiFive, Inc. * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You should have received a copy of LICENSE.Apache2 along with * this software. If not, you may obtain a copy at * * https://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. / package sifive.blocks.inclusivecache import chisel3._ import chisel3.util._ import freechips.rocketchip.tilelink._ import freechips.rocketchip.util._ class SinkCResponse(params: InclusiveCacheParameters) extends InclusiveCacheBundle(params) { val last = Bool() val set = UInt(params.setBits.W) val tag = UInt(params.tagBits.W) val source = UInt(params.inner.bundle.sourceBits.W) val param = UInt(3.W) val data = Bool() } class PutBufferCEntry(params: InclusiveCacheParameters) extends InclusiveCacheBundle(params) { val data = UInt(params.inner.bundle.dataBits.W) val corrupt = Bool() } class SinkC(params: InclusiveCacheParameters) extends Module { val io = IO(new Bundle { val req = Decoupled(new FullRequest(params)) // Release val resp = Valid(new SinkCResponse(params)) // ProbeAck val c = Flipped(Decoupled(new TLBundleC(params.inner.bundle))) // Find 'way' via MSHR CAM lookup val set = UInt(params.setBits.W) val way = Flipped(UInt(params.wayBits.W)) // ProbeAck write-back val bs_adr = Decoupled(new BankedStoreInnerAddress(params)) val bs_dat = new BankedStoreInnerPoison(params) // SourceD sideband val rel_pop = Flipped(Decoupled(new PutBufferPop(params))) val rel_beat = new PutBufferCEntry(params) }) if (params.firstLevel) { // Tie off unused ports io.req.valid := false.B io.req.bits := DontCare io.resp.valid := false.B io.resp.bits := DontCare io.c.ready := true.B io.set := 0.U io.bs_adr.valid := false.B io.bs_adr.bits := DontCare io.bs_dat := DontCare io.rel_pop.ready := true.B io.rel_beat := DontCare } else { // No restrictions on the type of buffer val c = params.micro.innerBuf.c(io.c) val (tag, set, offset) = params.parseAddress(c.bits.address) val (first, last, _, beat) = params.inner.count(c) val hasData = params.inner.hasData(c.bits) val raw_resp = c.bits.opcode === TLMessages.ProbeAck \|\| c.bits.opcode === TLMessages.ProbeAckData val resp = Mux(c.valid, raw_resp, RegEnable(raw_resp, c.valid)) // Handling of C is broken into two cases: // ProbeAck // if hasData, must be written to BankedStore // if last beat, trigger resp // Release // if first beat, trigger req // if hasData, go to putBuffer // if hasData && first beat, must claim a list assert (!(c.valid && c.bits.corrupt), "Data poisoning unavailable") io.set := Mux(c.valid, set, RegEnable(set, c.valid)) // finds us the way // Cut path from inner C to the BankedStore SRAM setup // ... this makes it easier to layout the L2 data banks far away val bs_adr = Wire(chiselTypeOf(io.bs_adr)) io.bs_adr <> Queue(bs_adr, 1, pipe=true) io.bs_dat.data := RegEnable(c.bits.data, bs_adr.fire) bs_adr.valid := resp && (!first \|\| (c.valid && hasData)) bs_adr.bits.noop := !c.valid bs_adr.bits.way := io.way bs_adr.bits.set := io.set bs_adr.bits.beat := Mux(c.valid, beat, RegEnable(beat + bs_adr.ready.asUInt, c.valid)) bs_adr.bits.mask := ~0.U(params.innerMaskBits.W) params.ccover(bs_adr.valid && !bs_adr.ready, "SINKC_SRAM_STALL", "Data SRAM busy") io.resp.valid := resp && c.valid && (first \|\| last) && (!hasData \|\| bs_adr.ready) io.resp.bits.last := last io.resp.bits.set := set io.resp.bits.tag := tag io.resp.bits.source := c.bits.source io.resp.bits.param := c.bits.param io.resp.bits.data := hasData val putbuffer = Module(new ListBuffer(ListBufferParameters(new PutBufferCEntry(params), params.relLists, params.relBeats, false))) val lists = RegInit(0.U(params.relLists.W)) val lists_set = WireInit(init = 0.U(params.relLists.W)) val lists_clr = WireInit(init = 0.U(params.relLists.W)) lists := (lists \| lists_set) & ~lists_clr val free = !lists.andR val freeOH = ~(leftOR(~lists) << 1) & ~lists val freeIdx = OHToUInt(freeOH) val req_block = first && !io.req.ready val buf_block = hasData && !putbuffer.io.push.ready val set_block = hasData && first && !free params.ccover(c.valid && !raw_resp && req_block, "SINKC_REQ_STALL", "No MSHR available to sink request") params.ccover(c.valid && !raw_resp && buf_block, "SINKC_BUF_STALL", "No space in putbuffer for beat") params.ccover(c.valid && !raw_resp && set_block, "SINKC_SET_STALL", "No space in putbuffer for request") c.ready := Mux(raw_resp, !hasData \|\| bs_adr.ready, !req_block && !buf_block && !set_block) io.req.valid := !resp && c.valid && first && !buf_block && !set_block putbuffer.io.push.valid := !resp && c.valid && hasData && !req_block && !set_block when (!resp && c.valid && first && hasData && !req_block && !buf_block) { lists_set := freeOH } val put = Mux(first, freeIdx, RegEnable(freeIdx, first)) io.req.bits.prio := VecInit(4.U(3.W).asBools) io.req.bits.control:= false.B io.req.bits.opcode := c.bits.opcode io.req.bits.param := c.bits.param io.req.bits.size := c.bits.size io.req.bits.source := c.bits.source io.req.bits.offset := offset io.req.bits.set := set io.req.bits.tag := tag io.req.bits.put := put putbuffer.io.push.bits.index := put putbuffer.io.push.bits.data.data := c.bits.data putbuffer.io.push.bits.data.corrupt := c.bits.corrupt // Grant access to pop the data putbuffer.io.pop.bits := io.rel_pop.bits.index putbuffer.io.pop.valid := io.rel_pop.fire io.rel_pop.ready := putbuffer.io.valid(io.rel_pop.bits.index(log2Ceil(params.relLists)-1,0)) io.rel_beat := putbuffer.io.data when (io.rel_pop.fire && io.rel_pop.bits.last) { lists_clr := UIntToOH(io.rel_pop.bits.index, params.relLists) } } } File Parameters.scala: / * Copyright 2019 SiFive, Inc. * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You should have received a copy of LICENSE.Apache2 along with * this software. If not, you may obtain a copy at * * https://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. / package sifive.blocks.inclusivecache import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config._ import freechips.rocketchip.diplomacy._ import freechips.rocketchip.tilelink._ import freechips.rocketchip.util._ import freechips.rocketchip.util.property.cover import scala.math.{min,max} case class CacheParameters( level: Int, ways: Int, sets: Int, blockBytes: Int, beatBytes: Int, // inner hintsSkipProbe: Boolean) { require (ways > 0) require (sets > 0) require (blockBytes > 0 && isPow2(blockBytes)) require (beatBytes > 0 && isPow2(beatBytes)) require (blockBytes >= beatBytes) val blocks = ways sets val sizeBytes = blocks * blockBytes val blockBeats = blockBytes/beatBytes } case class InclusiveCachePortParameters( a: BufferParams, b: BufferParams, c: BufferParams, d: BufferParams, e: BufferParams) { def apply()(implicit p: Parameters, valName: ValName) = LazyModule(new TLBuffer(a, b, c, d, e)) } object InclusiveCachePortParameters { val none = InclusiveCachePortParameters( a = BufferParams.none, b = BufferParams.none, c = BufferParams.none, d = BufferParams.none, e = BufferParams.none) val full = InclusiveCachePortParameters( a = BufferParams.default, b = BufferParams.default, c = BufferParams.default, d = BufferParams.default, e = BufferParams.default) // This removes feed-through paths from C=>A and A=>C val fullC = InclusiveCachePortParameters( a = BufferParams.none, b = BufferParams.none, c = BufferParams.default, d = BufferParams.none, e = BufferParams.none) val flowAD = InclusiveCachePortParameters( a = BufferParams.flow, b = BufferParams.none, c = BufferParams.none, d = BufferParams.flow, e = BufferParams.none) val flowAE = InclusiveCachePortParameters( a = BufferParams.flow, b = BufferParams.none, c = BufferParams.none, d = BufferParams.none, e = BufferParams.flow) // For innerBuf: // SinkA: no restrictions, flows into scheduler+putbuffer // SourceB: no restrictions, flows out of scheduler // sinkC: no restrictions, flows into scheduler+putbuffer & buffered to bankedStore // SourceD: no restrictions, flows out of bankedStore/regout // SinkE: no restrictions, flows into scheduler // // ... so while none is possible, you probably want at least flowAC to cut ready // from the scheduler delay and flowD to ease SourceD back-pressure // For outerBufer: // SourceA: must not be pipe, flows out of scheduler // SinkB: no restrictions, flows into scheduler // SourceC: pipe is useless, flows out of bankedStore/regout, parameter depth ignored // SinkD: no restrictions, flows into scheduler & bankedStore // SourceE: must not be pipe, flows out of scheduler // // ... AE take the channel ready into the scheduler, so you need at least flowAE } case class InclusiveCacheMicroParameters( writeBytes: Int, // backing store update granularity memCycles: Int = 40, // # of L2 clock cycles for a memory round-trip (50ns @ 800MHz) portFactor: Int = 4, // numSubBanks = (widest TL port * portFactor) / writeBytes dirReg: Boolean = false, innerBuf: InclusiveCachePortParameters = InclusiveCachePortParameters.fullC, // or none outerBuf: InclusiveCachePortParameters = InclusiveCachePortParameters.full) // or flowAE { require (writeBytes > 0 && isPow2(writeBytes)) require (memCycles > 0) require (portFactor >= 2) // for inner RMW and concurrent outer Relase + Grant } case class InclusiveCacheControlParameters( address: BigInt, beatBytes: Int, bankedControl: Boolean) case class InclusiveCacheParameters( cache: CacheParameters, micro: InclusiveCacheMicroParameters, control: Boolean, inner: TLEdgeIn, outer: TLEdgeOut)(implicit val p: Parameters) { require (cache.ways > 1) require (cache.sets > 1 && isPow2(cache.sets)) require (micro.writeBytes <= inner.manager.beatBytes) require (micro.writeBytes <= outer.manager.beatBytes) require (inner.manager.beatBytes <= cache.blockBytes) require (outer.manager.beatBytes <= cache.blockBytes) // Require that all cached address ranges have contiguous blocks outer.manager.managers.flatMap(_.address).foreach { a => require (a.alignment >= cache.blockBytes) } // If we are the first level cache, we do not need to support inner-BCE val firstLevel = !inner.client.clients.exists(_.supports.probe) // If we are the last level cache, we do not need to support outer-B val lastLevel = !outer.manager.managers.exists(_.regionType > RegionType.UNCACHED) require (lastLevel) // Provision enough resources to achieve full throughput with missing single-beat accesses val mshrs = InclusiveCacheParameters.all_mshrs(cache, micro) val secondary = max(mshrs, micro.memCycles - mshrs) val putLists = micro.memCycles // allow every request to be single beat val putBeats = max(2cache.blockBeats, micro.memCycles) val relLists = 2 val relBeats = relListscache.blockBeats val flatAddresses = AddressSet.unify(outer.manager.managers.flatMap(_.address)) val pickMask = AddressDecoder(flatAddresses.map(Seq(_)), flatAddresses.map(_.mask).reduce(_\|_)) def bitOffsets(x: BigInt, offset: Int = 0, tail: List[Int] = List.empty[Int]): List[Int] = if (x == 0) tail.reverse else bitOffsets(x >> 1, offset + 1, if ((x & 1) == 1) offset :: tail else tail) val addressMapping = bitOffsets(pickMask) val addressBits = addressMapping.size // println(s"addresses: ${flatAddresses} => ${pickMask} => ${addressBits}") val allClients = inner.client.clients.size val clientBitsRaw = inner.client.clients.filter(_.supports.probe).size val clientBits = max(1, clientBitsRaw) val stateBits = 2 val wayBits = log2Ceil(cache.ways) val setBits = log2Ceil(cache.sets) val offsetBits = log2Ceil(cache.blockBytes) val tagBits = addressBits - setBits - offsetBits val putBits = log2Ceil(max(putLists, relLists)) require (tagBits > 0) require (offsetBits > 0) val innerBeatBits = (offsetBits - log2Ceil(inner.manager.beatBytes)) max 1 val outerBeatBits = (offsetBits - log2Ceil(outer.manager.beatBytes)) max 1 val innerMaskBits = inner.manager.beatBytes / micro.writeBytes val outerMaskBits = outer.manager.beatBytes / micro.writeBytes def clientBit(source: UInt): UInt = { if (clientBitsRaw == 0) { 0.U } else { Cat(inner.client.clients.filter(_.supports.probe).map(_.sourceId.contains(source)).reverse) } } def clientSource(bit: UInt): UInt = { if (clientBitsRaw == 0) { 0.U } else { Mux1H(bit, inner.client.clients.filter(_.supports.probe).map(c => c.sourceId.start.U)) } } def parseAddress(x: UInt): (UInt, UInt, UInt) = { val offset = Cat(addressMapping.map(o => x(o,o)).reverse) val set = offset >> offsetBits val tag = set >> setBits (tag(tagBits-1, 0), set(setBits-1, 0), offset(offsetBits-1, 0)) } def widen(x: UInt, width: Int): UInt = { val y = x \| 0.U(width.W) assert (y >> width === 0.U) y(width-1, 0) } def expandAddress(tag: UInt, set: UInt, offset: UInt): UInt = { val base = Cat(widen(tag, tagBits), widen(set, setBits), widen(offset, offsetBits)) val bits = Array.fill(outer.bundle.addressBits) { 0.U(1.W) } addressMapping.zipWithIndex.foreach { case (a, i) => bits(a) = base(i,i) } Cat(bits.reverse) } def restoreAddress(expanded: UInt): UInt = { val missingBits = flatAddresses .map { a => (a.widen(pickMask).base, a.widen(~pickMask)) } // key is the bits to restore on match .groupBy(_._1) .view .mapValues(_.map(_._2)) val muxMask = AddressDecoder(missingBits.values.toList) val mux = missingBits.toList.map { case (bits, addrs) => val widen = addrs.map(_.widen(~muxMask)) val matches = AddressSet .unify(widen.distinct) .map(_.contains(expanded)) .reduce(_ \|\| _) (matches, bits.U) } expanded \| Mux1H(mux) } def dirReg[T <: Data](x: T, en: Bool = true.B): T = { if (micro.dirReg) RegEnable(x, en) else x } def ccover(cond: Bool, label: String, desc: String)(implicit sourceInfo: SourceInfo) = cover(cond, "CCACHE_L" + cache.level + "_" + label, "MemorySystem;;" + desc) } object MetaData { val stateBits = 2 def INVALID: UInt = 0.U(stateBits.W) // way is empty def BRANCH: UInt = 1.U(stateBits.W) // outer slave cache is trunk def TRUNK: UInt = 2.U(stateBits.W) // unique inner master cache is trunk def TIP: UInt = 3.U(stateBits.W) // we are trunk, inner masters are branch // Does a request need trunk? def needT(opcode: UInt, param: UInt): Bool = { !opcode(2) \|\| (opcode === TLMessages.Hint && param === TLHints.PREFETCH_WRITE) \|\| ((opcode === TLMessages.AcquireBlock \|\| opcode === TLMessages.AcquirePerm) && param =/= TLPermissions.NtoB) } // Does a request prove the client need not be probed? def skipProbeN(opcode: UInt, hintsSkipProbe: Boolean): Bool = { // Acquire(toB) and Get => is N, so no probe // Acquire(toT) => is N or B, but need T, so no probe // Hint => could be anything, so probe IS needed, if hintsSkipProbe is enabled, skip probe the same client // Put => is N or B, so probe IS needed opcode === TLMessages.AcquireBlock \|\| opcode === TLMessages.AcquirePerm \|\| opcode === TLMessages.Get \|\| (opcode === TLMessages.Hint && hintsSkipProbe.B) } def isToN(param: UInt): Bool = { param === TLPermissions.TtoN \|\| param === TLPermissions.BtoN \|\| param === TLPermissions.NtoN } def isToB(param: UInt): Bool = { param === TLPermissions.TtoB \|\| param === TLPermissions.BtoB } } object InclusiveCacheParameters { val lfsrBits = 10 val L2ControlAddress = 0x2010000 val L2ControlSize = 0x1000 def out_mshrs(cache: CacheParameters, micro: InclusiveCacheMicroParameters): Int = { // We need 2-3 normal MSHRs to cover the Directory latency // To fully exploit memory bandwidth-delay-product, we need memCyles/blockBeats MSHRs max(if (micro.dirReg) 3 else 2, (micro.memCycles + cache.blockBeats - 1) / cache.blockBeats) } def all_mshrs(cache: CacheParameters, micro: InclusiveCacheMicroParameters): Int = // We need a dedicated MSHR for B+C each 2 + out_mshrs(cache, micro) } class InclusiveCacheBundle(params: InclusiveCacheParameters) extends Bundle File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportPutFull \|\| manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB \|\| manager.anySupportGet \|\| manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportPutFull \|\| client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe \|\| client.anySupportGet \|\| client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet \|\| client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull \|\| client.anySupportPutPartial \|\| client.anySupportHint \|\| client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet \|\| manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull \|\| manager.anySupportPutPartial \|\| manager.anySupportHint \|\| manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) \|\| !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.ProbeAckData \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode \| small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U \|\| beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }	module SinkC( // @[SinkC.scala:41:7] input clock, // @[SinkC.scala:41:7] input reset, // @[SinkC.scala:41:7] input io_req_ready, // @[SinkC.scala:43:14] output io_req_valid, // @[SinkC.scala:43:14] output [2:0] io_req_bits_opcode, // @[SinkC.scala:43:14] output [2:0] io_req_bits_param, // @[SinkC.scala:43:14] output [2:0] io_req_bits_size, // @[SinkC.scala:43:14] output [7:0] io_req_bits_source, // @[SinkC.scala:43:14] output [12:0] io_req_bits_tag, // @[SinkC.scala:43:14] output [5:0] io_req_bits_offset, // @[SinkC.scala:43:14] output [5:0] io_req_bits_put, // @[SinkC.scala:43:14] output [9:0] io_req_bits_set, // @[SinkC.scala:43:14] output io_resp_valid, // @[SinkC.scala:43:14] output io_resp_bits_last, // @[SinkC.scala:43:14] output [9:0] io_resp_bits_set, // @[SinkC.scala:43:14] output [12:0] io_resp_bits_tag, // @[SinkC.scala:43:14] output [7:0] io_resp_bits_source, // @[SinkC.scala:43:14] output [2:0] io_resp_bits_param, // @[SinkC.scala:43:14] output io_resp_bits_data, // @[SinkC.scala:43:14] output io_c_ready, // @[SinkC.scala:43:14] input io_c_valid, // @[SinkC.scala:43:14] input [2:0] io_c_bits_opcode, // @[SinkC.scala:43:14] input [2:0] io_c_bits_param, // @[SinkC.scala:43:14] input [2:0] io_c_bits_size, // @[SinkC.scala:43:14] input [7:0] io_c_bits_source, // @[SinkC.scala:43:14] input [31:0] io_c_bits_address, // @[SinkC.scala:43:14] input [127:0] io_c_bits_data, // @[SinkC.scala:43:14] input io_c_bits_corrupt, // @[SinkC.scala:43:14] output [9:0] io_set, // @[SinkC.scala:43:14] input [2:0] io_way, // @[SinkC.scala:43:14] input io_bs_adr_ready, // @[SinkC.scala:43:14] output io_bs_adr_valid, // @[SinkC.scala:43:14] output io_bs_adr_bits_noop, // @[SinkC.scala:43:14] output [2:0] io_bs_adr_bits_way, // @[SinkC.scala:43:14] output [9:0] io_bs_adr_bits_set, // @[SinkC.scala:43:14] output [1:0] io_bs_adr_bits_beat, // @[SinkC.scala:43:14] output [1:0] io_bs_adr_bits_mask, // @[SinkC.scala:43:14] output [127:0] io_bs_dat_data, // @[SinkC.scala:43:14] output io_rel_pop_ready, // @[SinkC.scala:43:14] input io_rel_pop_valid, // @[SinkC.scala:43:14] input [5:0] io_rel_pop_bits_index, // @[SinkC.scala:43:14] input io_rel_pop_bits_last, // @[SinkC.scala:43:14] output [127:0] io_rel_beat_data, // @[SinkC.scala:43:14] output io_rel_beat_corrupt // @[SinkC.scala:43:14] ); wire [9:0] io_set_0; // @[SinkC.scala:41:7] wire _putbuffer_io_push_ready; // @[SinkC.scala:115:27] wire [1:0] _putbuffer_io_valid; // @[SinkC.scala:115:27] wire _c_q_io_deq_valid; // @[Decoupled.scala:362:21] wire [2:0] _c_q_io_deq_bits_opcode; // @[Decoupled.scala:362:21] wire [2:0] _c_q_io_deq_bits_param; // @[Decoupled.scala:362:21] wire [2:0] _c_q_io_deq_bits_size; // @[Decoupled.scala:362:21] wire [7:0] _c_q_io_deq_bits_source; // @[Decoupled.scala:362:21] wire [31:0] _c_q_io_deq_bits_address; // @[Decoupled.scala:362:21] wire [127:0] _c_q_io_deq_bits_data; // @[Decoupled.scala:362:21] wire _c_q_io_deq_bits_corrupt; // @[Decoupled.scala:362:21] wire io_req_ready_0 = io_req_ready; // @[SinkC.scala:41:7] wire io_c_valid_0 = io_c_valid; // @[SinkC.scala:41:7] wire [2:0] io_c_bits_opcode_0 = io_c_bits_opcode; // @[SinkC.scala:41:7] wire [2:0] io_c_bits_param_0 = io_c_bits_param; // @[SinkC.scala:41:7] wire [2:0] io_c_bits_size_0 = io_c_bits_size; // @[SinkC.scala:41:7] wire [7:0] io_c_bits_source_0 = io_c_bits_source; // @[SinkC.scala:41:7] wire [31:0] io_c_bits_address_0 = io_c_bits_address; // @[SinkC.scala:41:7] wire [127:0] io_c_bits_data_0 = io_c_bits_data; // @[SinkC.scala:41:7] wire io_c_bits_corrupt_0 = io_c_bits_corrupt; // @[SinkC.scala:41:7] wire [2:0] io_way_0 = io_way; // @[SinkC.scala:41:7] wire io_bs_adr_ready_0 = io_bs_adr_ready; // @[SinkC.scala:41:7] wire io_rel_pop_valid_0 = io_rel_pop_valid; // @[SinkC.scala:41:7] wire [5:0] io_rel_pop_bits_index_0 = io_rel_pop_bits_index; // @[SinkC.scala:41:7] wire io_rel_pop_bits_last_0 = io_rel_pop_bits_last; // @[SinkC.scala:41:7] wire io_req_bits_prio_0 = 1'h0; // @[SinkC.scala:41:7] wire io_req_bits_prio_1 = 1'h0; // @[SinkC.scala:41:7] wire io_req_bits_control = 1'h0; // @[SinkC.scala:41:7] wire io_req_bits_prio_2 = 1'h1; // @[SinkC.scala:41:7] wire [1:0] bs_adr_bits_mask = 2'h3; // @[SinkC.scala:96:22] wire [1:0] _bs_adr_bits_mask_T = 2'h3; // @[SinkC.scala:104:25] wire _io_req_valid_T_6; // @[SinkC.scala:136:61] wire [12:0] tag_1; // @[Parameters.scala:217:9] wire [5:0] offset_1; // @[Parameters.scala:217:50] wire [9:0] set_1; // @[Parameters.scala:217:28] wire _io_resp_valid_T_5; // @[SinkC.scala:107:57] wire last; // @[Edges.scala:232:33] wire hasData; // @[Edges.scala:102:36] wire [9:0] _io_set_T; // @[SinkC.scala:92:18] wire [9:0] bs_adr_bits_set = io_set_0; // @[SinkC.scala:41:7, :96:22] wire [2:0] bs_adr_bits_way = io_way_0; // @[SinkC.scala:41:7, :96:22] wire _io_rel_pop_ready_T_2; // @[SinkC.scala:160:43] wire [2:0] io_req_bits_opcode_0; // @[SinkC.scala:41:7] wire [2:0] io_req_bits_param_0; // @[SinkC.scala:41:7] wire [2:0] io_req_bits_size_0; // @[SinkC.scala:41:7] wire [7:0] io_req_bits_source_0; // @[SinkC.scala:41:7] wire [12:0] io_req_bits_tag_0; // @[SinkC.scala:41:7] wire [5:0] io_req_bits_offset_0; // @[SinkC.scala:41:7] wire [5:0] io_req_bits_put_0; // @[SinkC.scala:41:7] wire [9:0] io_req_bits_set_0; // @[SinkC.scala:41:7] wire io_req_valid_0; // @[SinkC.scala:41:7] wire io_resp_bits_last_0; // @[SinkC.scala:41:7] wire [9:0] io_resp_bits_set_0; // @[SinkC.scala:41:7] wire [12:0] io_resp_bits_tag_0; // @[SinkC.scala:41:7] wire [7:0] io_resp_bits_source_0; // @[SinkC.scala:41:7] wire [2:0] io_resp_bits_param_0; // @[SinkC.scala:41:7] wire io_resp_bits_data_0; // @[SinkC.scala:41:7] wire io_resp_valid_0; // @[SinkC.scala:41:7] wire io_c_ready_0; // @[SinkC.scala:41:7] wire io_bs_adr_bits_noop_0; // @[SinkC.scala:41:7] wire [2:0] io_bs_adr_bits_way_0; // @[SinkC.scala:41:7] wire [9:0] io_bs_adr_bits_set_0; // @[SinkC.scala:41:7] wire [1:0] io_bs_adr_bits_beat_0; // @[SinkC.scala:41:7] wire [1:0] io_bs_adr_bits_mask_0; // @[SinkC.scala:41:7] wire io_bs_adr_valid_0; // @[SinkC.scala:41:7] wire [127:0] io_bs_dat_data_0; // @[SinkC.scala:41:7] wire io_rel_pop_ready_0; // @[SinkC.scala:41:7] wire [127:0] io_rel_beat_data_0; // @[SinkC.scala:41:7] wire io_rel_beat_corrupt_0; // @[SinkC.scala:41:7] wire _offset_T = _c_q_io_deq_bits_address[0]; // @[Decoupled.scala:362:21] wire _offset_T_1 = _c_q_io_deq_bits_address[1]; // @[Decoupled.scala:362:21] wire _offset_T_2 = _c_q_io_deq_bits_address[2]; // @[Decoupled.scala:362:21] wire _offset_T_3 = _c_q_io_deq_bits_address[3]; // @[Decoupled.scala:362:21] wire _offset_T_4 = _c_q_io_deq_bits_address[4]; // @[Decoupled.scala:362:21] wire _offset_T_5 = _c_q_io_deq_bits_address[5]; // @[Decoupled.scala:362:21] wire _offset_T_6 = _c_q_io_deq_bits_address[6]; // @[Decoupled.scala:362:21] wire _offset_T_7 = _c_q_io_deq_bits_address[7]; // @[Decoupled.scala:362:21] wire _offset_T_8 = _c_q_io_deq_bits_address[8]; // @[Decoupled.scala:362:21] wire _offset_T_9 = _c_q_io_deq_bits_address[9]; // @[Decoupled.scala:362:21] wire _offset_T_10 = _c_q_io_deq_bits_address[10]; // @[Decoupled.scala:362:21] wire _offset_T_11 = _c_q_io_deq_bits_address[11]; // @[Decoupled.scala:362:21] wire _offset_T_12 = _c_q_io_deq_bits_address[12]; // @[Decoupled.scala:362:21] wire _offset_T_13 = _c_q_io_deq_bits_address[13]; // @[Decoupled.scala:362:21] wire _offset_T_14 = _c_q_io_deq_bits_address[14]; // @[Decoupled.scala:362:21] wire _offset_T_15 = _c_q_io_deq_bits_address[15]; // @[Decoupled.scala:362:21] wire _offset_T_16 = _c_q_io_deq_bits_address[16]; // @[Decoupled.scala:362:21] wire _offset_T_17 = _c_q_io_deq_bits_address[17]; // @[Decoupled.scala:362:21] wire _offset_T_18 = _c_q_io_deq_bits_address[18]; // @[Decoupled.scala:362:21] wire _offset_T_19 = _c_q_io_deq_bits_address[19]; // @[Decoupled.scala:362:21] wire _offset_T_20 = _c_q_io_deq_bits_address[20]; // @[Decoupled.scala:362:21] wire _offset_T_21 = _c_q_io_deq_bits_address[21]; // @[Decoupled.scala:362:21] wire _offset_T_22 = _c_q_io_deq_bits_address[22]; // @[Decoupled.scala:362:21] wire _offset_T_23 = _c_q_io_deq_bits_address[23]; // @[Decoupled.scala:362:21] wire _offset_T_24 = _c_q_io_deq_bits_address[24]; // @[Decoupled.scala:362:21] wire _offset_T_25 = _c_q_io_deq_bits_address[25]; // @[Decoupled.scala:362:21] wire _offset_T_26 = _c_q_io_deq_bits_address[26]; // @[Decoupled.scala:362:21] wire _offset_T_27 = _c_q_io_deq_bits_address[27]; // @[Decoupled.scala:362:21] wire _offset_T_28 = _c_q_io_deq_bits_address[31]; // @[Decoupled.scala:362:21] wire [1:0] offset_lo_lo_lo_hi = {_offset_T_2, _offset_T_1}; // @[Parameters.scala:214:{21,47}] wire [2:0] offset_lo_lo_lo = {offset_lo_lo_lo_hi, _offset_T}; // @[Parameters.scala:214:{21,47}] wire [1:0] offset_lo_lo_hi_lo = {_offset_T_4, _offset_T_3}; // @[Parameters.scala:214:{21,47}] wire [1:0] offset_lo_lo_hi_hi = {_offset_T_6, _offset_T_5}; // @[Parameters.scala:214:{21,47}] wire [3:0] offset_lo_lo_hi = {offset_lo_lo_hi_hi, offset_lo_lo_hi_lo}; // @[Parameters.scala:214:21] wire [6:0] offset_lo_lo = {offset_lo_lo_hi, offset_lo_lo_lo}; // @[Parameters.scala:214:21] wire [1:0] offset_lo_hi_lo_hi = {_offset_T_9, _offset_T_8}; // @[Parameters.scala:214:{21,47}] wire [2:0] offset_lo_hi_lo = {offset_lo_hi_lo_hi, _offset_T_7}; // @[Parameters.scala:214:{21,47}] wire [1:0] offset_lo_hi_hi_lo = {_offset_T_11, _offset_T_10}; // @[Parameters.scala:214:{21,47}] wire [1:0] offset_lo_hi_hi_hi = {_offset_T_13, _offset_T_12}; // @[Parameters.scala:214:{21,47}] wire [3:0] offset_lo_hi_hi = {offset_lo_hi_hi_hi, offset_lo_hi_hi_lo}; // @[Parameters.scala:214:21] wire [6:0] offset_lo_hi = {offset_lo_hi_hi, offset_lo_hi_lo}; // @[Parameters.scala:214:21] wire [13:0] offset_lo = {offset_lo_hi, offset_lo_lo}; // @[Parameters.scala:214:21] wire [1:0] offset_hi_lo_lo_hi = {_offset_T_16, _offset_T_15}; // @[Parameters.scala:214:{21,47}] wire [2:0] offset_hi_lo_lo = {offset_hi_lo_lo_hi, _offset_T_14}; // @[Parameters.scala:214:{21,47}] wire [1:0] offset_hi_lo_hi_lo = {_offset_T_18, _offset_T_17}; // @[Parameters.scala:214:{21,47}] wire [1:0] offset_hi_lo_hi_hi = {_offset_T_20, _offset_T_19}; // @[Parameters.scala:214:{21,47}] wire [3:0] offset_hi_lo_hi = {offset_hi_lo_hi_hi, offset_hi_lo_hi_lo}; // @[Parameters.scala:214:21] wire [6:0] offset_hi_lo = {offset_hi_lo_hi, offset_hi_lo_lo}; // @[Parameters.scala:214:21] wire [1:0] offset_hi_hi_lo_lo = {_offset_T_22, _offset_T_21}; // @[Parameters.scala:214:{21,47}] wire [1:0] offset_hi_hi_lo_hi = {_offset_T_24, _offset_T_23}; // @[Parameters.scala:214:{21,47}] wire [3:0] offset_hi_hi_lo = {offset_hi_hi_lo_hi, offset_hi_hi_lo_lo}; // @[Parameters.scala:214:21] wire [1:0] offset_hi_hi_hi_lo = {_offset_T_26, _offset_T_25}; // @[Parameters.scala:214:{21,47}] wire [1:0] offset_hi_hi_hi_hi = {_offset_T_28, _offset_T_27}; // @[Parameters.scala:214:{21,47}] wire [3:0] offset_hi_hi_hi = {offset_hi_hi_hi_hi, offset_hi_hi_hi_lo}; // @[Parameters.scala:214:21] wire [7:0] offset_hi_hi = {offset_hi_hi_hi, offset_hi_hi_lo}; // @[Parameters.scala:214:21] wire [14:0] offset_hi = {offset_hi_hi, offset_hi_lo}; // @[Parameters.scala:214:21] wire [28:0] offset = {offset_hi, offset_lo}; // @[Parameters.scala:214:21] wire [22:0] set = offset[28:6]; // @[Parameters.scala:214:21, :215:22] wire [12:0] tag = set[22:10]; // @[Parameters.scala:215:22, :216:19] assign tag_1 = tag; // @[Parameters.scala:216:19, :217:9] assign io_req_bits_tag_0 = tag_1; // @[SinkC.scala:41:7] assign io_resp_bits_tag_0 = tag_1; // @[SinkC.scala:41:7] assign set_1 = set[9:0]; // @[Parameters.scala:215:22, :217:28] assign io_req_bits_set_0 = set_1; // @[SinkC.scala:41:7] assign io_resp_bits_set_0 = set_1; // @[SinkC.scala:41:7] assign offset_1 = offset[5:0]; // @[Parameters.scala:214:21, :217:50] assign io_req_bits_offset_0 = offset_1; // @[SinkC.scala:41:7] wire _q_io_deq_ready_T_7; // @[SinkC.scala:134:19] wire _T = _q_io_deq_ready_T_7 & _c_q_io_deq_valid; // @[Decoupled.scala:51:35, :362:21] wire [12:0] _r_beats1_decode_T = 13'h3F << _c_q_io_deq_bits_size; // @[Decoupled.scala:362:21] wire [5:0] _r_beats1_decode_T_1 = _r_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _r_beats1_decode_T_2 = ~_r_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [1:0] r_beats1_decode = _r_beats1_decode_T_2[5:4]; // @[package.scala:243:46] wire r_beats1_opdata = _c_q_io_deq_bits_opcode[0]; // @[Decoupled.scala:362:21] assign hasData = _c_q_io_deq_bits_opcode[0]; // @[Decoupled.scala:362:21] wire [1:0] r_beats1 = r_beats1_opdata ? r_beats1_decode : 2'h0; // @[Edges.scala:102:36, :220:59, :221:14] reg [1:0] r_counter; // @[Edges.scala:229:27] wire [2:0] _r_counter1_T = {1'h0, r_counter} - 3'h1; // @[Edges.scala:229:27, :230:28] wire [1:0] r_counter1 = _r_counter1_T[1:0]; // @[Edges.scala:230:28] wire first = r_counter == 2'h0; // @[Edges.scala:229:27, :231:25] wire _r_last_T = r_counter == 2'h1; // @[Edges.scala:229:27, :232:25] wire _r_last_T_1 = r_beats1 == 2'h0; // @[Edges.scala:221:14, :232:43] assign last = _r_last_T \| _r_last_T_1; // @[Edges.scala:232:{25,33,43}] assign io_resp_bits_last_0 = last; // @[Edges.scala:232:33] wire r_3 = last & _T; // @[Decoupled.scala:51:35] wire [1:0] _r_count_T = ~r_counter1; // @[Edges.scala:230:28, :234:27] wire [1:0] beat = r_beats1 & _r_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [1:0] _r_counter_T = first ? r_beats1 : r_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] assign io_resp_bits_data_0 = hasData; // @[Edges.scala:102:36] wire _raw_resp_T = _c_q_io_deq_bits_opcode == 3'h4; // @[Decoupled.scala:362:21] wire _raw_resp_T_1 = _c_q_io_deq_bits_opcode == 3'h5; // @[Decoupled.scala:362:21] wire raw_resp = _raw_resp_T \| _raw_resp_T_1; // @[SinkC.scala:78:{34,58,75}] reg resp_r; // @[SinkC.scala:79:48] wire resp = _c_q_io_deq_valid ? raw_resp : resp_r; // @[Decoupled.scala:362:21]
Generate the Verilog code corresponding to the following Chisel files. File DescribedSRAM.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3.{Data, SyncReadMem, Vec} import chisel3.util.log2Ceil object DescribedSRAM { def apply[T <: Data]( name: String, desc: String, size: BigInt, // depth data: T ): SyncReadMem[T] = { val mem = SyncReadMem(size, data) mem.suggestName(name) val granWidth = data match { case v: Vec[_] => v.head.getWidth case d => d.getWidth } val uid = 0 Annotated.srams( component = mem, name = name, address_width = log2Ceil(size), data_width = data.getWidth, depth = size, description = desc, write_mask_granularity = granWidth ) mem } }	module rerocc_tile_dcache_tag_array_3( // @[DescribedSRAM.scala:17:26] input [1:0] RW0_addr, input RW0_en, input RW0_clk, input RW0_wmode, input [103:0] RW0_wdata, output [103:0] RW0_rdata, input [3:0] RW0_wmask ); rerocc_tile_dcache_tag_array_ext rerocc_tile_dcache_tag_array_ext ( // @[DescribedSRAM.scala:17:26] .RW0_addr (RW0_addr), .RW0_en (RW0_en), .RW0_clk (RW0_clk), .RW0_wmode (RW0_wmode), .RW0_wdata (RW0_wdata), .RW0_rdata (RW0_rdata), .RW0_wmask (RW0_wmask) ); // @[DescribedSRAM.scala:17:26] endmodule
Generate the Verilog code corresponding to the following Chisel files. File Tile.scala: // See README.md for license details. package gemmini import chisel3._ import chisel3.util._ import Util._ /** * A Tile is a purely combinational 2D array of passThrough PEs. * a, b, s, and in_propag are broadcast across the entire array and are passed through to the Tile's outputs * @param width The data width of each PE in bits * @param rows Number of PEs on each row * @param columns Number of PEs on each column */ class Tile[T <: Data](inputType: T, outputType: T, accType: T, df: Dataflow.Value, tree_reduction: Boolean, max_simultaneous_matmuls: Int, val rows: Int, val columns: Int)(implicit ev: Arithmetic[T]) extends Module { val io = IO(new Bundle { val in_a = Input(Vec(rows, inputType)) val in_b = Input(Vec(columns, outputType)) // This is the output of the tile next to it val in_d = Input(Vec(columns, outputType)) val in_control = Input(Vec(columns, new PEControl(accType))) val in_id = Input(Vec(columns, UInt(log2Up(max_simultaneous_matmuls).W))) val in_last = Input(Vec(columns, Bool())) val out_a = Output(Vec(rows, inputType)) val out_c = Output(Vec(columns, outputType)) val out_b = Output(Vec(columns, outputType)) val out_control = Output(Vec(columns, new PEControl(accType))) val out_id = Output(Vec(columns, UInt(log2Up(max_simultaneous_matmuls).W))) val out_last = Output(Vec(columns, Bool())) val in_valid = Input(Vec(columns, Bool())) val out_valid = Output(Vec(columns, Bool())) val bad_dataflow = Output(Bool()) }) import ev._ val tile = Seq.fill(rows, columns)(Module(new PE(inputType, outputType, accType, df, max_simultaneous_matmuls))) val tileT = tile.transpose // TODO: abstract hori/vert broadcast, all these connections look the same // Broadcast 'a' horizontally across the Tile for (r <- 0 until rows) { tile(r).foldLeft(io.in_a(r)) { case (in_a, pe) => pe.io.in_a := in_a pe.io.out_a } } // Broadcast 'b' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_b(c)) { case (in_b, pe) => pe.io.in_b := (if (tree_reduction) in_b.zero else in_b) pe.io.out_b } } // Broadcast 'd' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_d(c)) { case (in_d, pe) => pe.io.in_d := in_d pe.io.out_c } } // Broadcast 'control' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_control(c)) { case (in_ctrl, pe) => pe.io.in_control := in_ctrl pe.io.out_control } } // Broadcast 'garbage' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_valid(c)) { case (v, pe) => pe.io.in_valid := v pe.io.out_valid } } // Broadcast 'id' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_id(c)) { case (id, pe) => pe.io.in_id := id pe.io.out_id } } // Broadcast 'last' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_last(c)) { case (last, pe) => pe.io.in_last := last pe.io.out_last } } // Drive the Tile's bottom IO for (c <- 0 until columns) { io.out_c(c) := tile(rows-1)(c).io.out_c io.out_control(c) := tile(rows-1)(c).io.out_control io.out_id(c) := tile(rows-1)(c).io.out_id io.out_last(c) := tile(rows-1)(c).io.out_last io.out_valid(c) := tile(rows-1)(c).io.out_valid io.out_b(c) := { if (tree_reduction) { val prods = tileT(c).map(_.io.out_b) accumulateTree(prods :+ io.in_b(c)) } else { tile(rows - 1)(c).io.out_b } } } io.bad_dataflow := tile.map(_.map(_.io.bad_dataflow).reduce(_\|\|_)).reduce(_\|\|_) // Drive the Tile's right IO for (r <- 0 until rows) { io.out_a(r) := tile(r)(columns-1).io.out_a } }	module Tile_55( // @[Tile.scala:16:7] input clock, // @[Tile.scala:16:7] input reset, // @[Tile.scala:16:7] input [7:0] io_in_a_0, // @[Tile.scala:17:14] input [19:0] io_in_b_0, // @[Tile.scala:17:14] input [19:0] io_in_d_0, // @[Tile.scala:17:14] input io_in_control_0_dataflow, // @[Tile.scala:17:14] input io_in_control_0_propagate, // @[Tile.scala:17:14] input [4:0] io_in_control_0_shift, // @[Tile.scala:17:14] input [2:0] io_in_id_0, // @[Tile.scala:17:14] input io_in_last_0, // @[Tile.scala:17:14] output [7:0] io_out_a_0, // @[Tile.scala:17:14] output [19:0] io_out_c_0, // @[Tile.scala:17:14] output [19:0] io_out_b_0, // @[Tile.scala:17:14] output io_out_control_0_dataflow, // @[Tile.scala:17:14] output io_out_control_0_propagate, // @[Tile.scala:17:14] output [4:0] io_out_control_0_shift, // @[Tile.scala:17:14] output [2:0] io_out_id_0, // @[Tile.scala:17:14] output io_out_last_0, // @[Tile.scala:17:14] input io_in_valid_0, // @[Tile.scala:17:14] output io_out_valid_0, // @[Tile.scala:17:14] output io_bad_dataflow // @[Tile.scala:17:14] ); wire [7:0] io_in_a_0_0 = io_in_a_0; // @[Tile.scala:16:7] wire [19:0] io_in_b_0_0 = io_in_b_0; // @[Tile.scala:16:7] wire [19:0] io_in_d_0_0 = io_in_d_0; // @[Tile.scala:16:7] wire io_in_control_0_dataflow_0 = io_in_control_0_dataflow; // @[Tile.scala:16:7] wire io_in_control_0_propagate_0 = io_in_control_0_propagate; // @[Tile.scala:16:7] wire [4:0] io_in_control_0_shift_0 = io_in_control_0_shift; // @[Tile.scala:16:7] wire [2:0] io_in_id_0_0 = io_in_id_0; // @[Tile.scala:16:7] wire io_in_last_0_0 = io_in_last_0; // @[Tile.scala:16:7] wire io_in_valid_0_0 = io_in_valid_0; // @[Tile.scala:16:7] wire [7:0] io_out_a_0_0; // @[Tile.scala:16:7] wire [19:0] io_out_c_0_0; // @[Tile.scala:16:7] wire [19:0] io_out_b_0_0; // @[Tile.scala:16:7] wire io_out_control_0_dataflow_0; // @[Tile.scala:16:7] wire io_out_control_0_propagate_0; // @[Tile.scala:16:7] wire [4:0] io_out_control_0_shift_0; // @[Tile.scala:16:7] wire [2:0] io_out_id_0_0; // @[Tile.scala:16:7] wire io_out_last_0_0; // @[Tile.scala:16:7] wire io_out_valid_0_0; // @[Tile.scala:16:7] wire io_bad_dataflow_0; // @[Tile.scala:16:7] PE_311 tile_0_0 ( // @[Tile.scala:42:44] .clock (clock), .reset (reset), .io_in_a (io_in_a_0_0), // @[Tile.scala:16:7] .io_in_b (io_in_b_0_0), // @[Tile.scala:16:7] .io_in_d (io_in_d_0_0), // @[Tile.scala:16:7] .io_out_a (io_out_a_0_0), .io_out_b (io_out_b_0_0), .io_out_c (io_out_c_0_0), .io_in_control_dataflow (io_in_control_0_dataflow_0), // @[Tile.scala:16:7] .io_in_control_propagate (io_in_control_0_propagate_0), // @[Tile.scala:16:7] .io_in_control_shift (io_in_control_0_shift_0), // @[Tile.scala:16:7] .io_out_control_dataflow (io_out_control_0_dataflow_0), .io_out_control_propagate (io_out_control_0_propagate_0), .io_out_control_shift (io_out_control_0_shift_0), .io_in_id (io_in_id_0_0), // @[Tile.scala:16:7] .io_out_id (io_out_id_0_0), .io_in_last (io_in_last_0_0), // @[Tile.scala:16:7] .io_out_last (io_out_last_0_0), .io_in_valid (io_in_valid_0_0), // @[Tile.scala:16:7] .io_out_valid (io_out_valid_0_0), .io_bad_dataflow (io_bad_dataflow_0) ); // @[Tile.scala:42:44] assign io_out_a_0 = io_out_a_0_0; // @[Tile.scala:16:7] assign io_out_c_0 = io_out_c_0_0; // @[Tile.scala:16:7] assign io_out_b_0 = io_out_b_0_0; // @[Tile.scala:16:7] assign io_out_control_0_dataflow = io_out_control_0_dataflow_0; // @[Tile.scala:16:7] assign io_out_control_0_propagate = io_out_control_0_propagate_0; // @[Tile.scala:16:7] assign io_out_control_0_shift = io_out_control_0_shift_0; // @[Tile.scala:16:7] assign io_out_id_0 = io_out_id_0_0; // @[Tile.scala:16:7] assign io_out_last_0 = io_out_last_0_0; // @[Tile.scala:16:7] assign io_out_valid_0 = io_out_valid_0_0; // @[Tile.scala:16:7] assign io_bad_dataflow = io_bad_dataflow_0; // @[Tile.scala:16:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File ShiftReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ // Similar to the Chisel ShiftRegister but allows the user to suggest a // name to the registers that get instantiated, and // to provide a reset value. object ShiftRegInit { def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T = (0 until n).foldRight(in) { case (i, next) => { val r = RegNext(next, init) name.foreach { na => r.suggestName(s"${na}_${i}") } r } } } /** These wrap behavioral * shift registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * The different types vary in their reset behavior: * AsyncResetShiftReg -- Asynchronously reset register array * A W(width) x D(depth) sized array is constructed from D instantiations of a * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg, * but only used for timing applications / abstract class AbstractPipelineReg(w: Int = 1) extends Module { val io = IO(new Bundle { val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) } ) } object AbstractPipelineReg { def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = { val chain = Module(gen) name.foreach{ chain.suggestName(_) } chain.io.d := in.asUInt chain.io.q.asTypeOf(in) } } class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) { require(depth > 0, "Depth must be greater than 0.") override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}" val chain = List.tabulate(depth) { i => Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}") } chain.last.io.d := io.d chain.last.io.en := true.B (chain.init zip chain.tail).foreach { case (sink, source) => sink.io.d := source.io.q sink.io.en := true.B } io.q := chain.head.io.q } object AsyncResetShiftReg { def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name) def apply [T <: Data](in: T, depth: Int, name: Option[String]): T = apply(in, depth, 0, name) def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T = apply(in, depth, init.litValue.toInt, name) def apply [T <: Data](in: T, depth: Int, init: T): T = apply (in, depth, init.litValue.toInt, None) } File SynchronizerReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util.{RegEnable, Cat} /* These wrap behavioral * shift and next registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * * These are built up of ResetSynchronizerPrimitiveShiftReg, intended to be replaced by the integrator's metastable flops chains or replaced * at this level if they have a multi-bit wide synchronizer primitive. * The different types vary in their reset behavior: * NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin * AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep * 1-bit-wide shift registers. * SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg * * [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference. * * ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross * Clock Domains. */ object SynchronizerResetType extends Enumeration { val NonSync, Inferred, Sync, Async = Value } // Note: this should not be used directly. // Use the companion object to generate this with the correct reset type mixin. private class SynchronizerPrimitiveShiftReg( sync: Int, init: Boolean, resetType: SynchronizerResetType.Value) extends AbstractPipelineReg(1) { val initInt = if (init) 1 else 0 val initPostfix = resetType match { case SynchronizerResetType.NonSync => "" case _ => s"_i${initInt}" } override def desiredName = s"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}" val chain = List.tabulate(sync) { i => val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B) reg.suggestName(s"sync_$i") } chain.last := io.d.asBool (chain.init zip chain.tail).foreach { case (sink, source) => sink := source } io.q := chain.head.asUInt } private object SynchronizerPrimitiveShiftReg { def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = { val gen: () => SynchronizerPrimitiveShiftReg = resetType match { case SynchronizerResetType.NonSync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) case SynchronizerResetType.Async => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset case SynchronizerResetType.Sync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset case SynchronizerResetType.Inferred => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) } AbstractPipelineReg(gen(), in) } } // Note: This module may end up with a non-AsyncReset type reset. // But the Primitives within will always have AsyncReset type. class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asAsyncReset){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async) } } io.q := Cat(output.reverse) } object AsyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } // Note: This module may end up with a non-Bool type reset. // But the Primitives within will always have Bool reset type. @deprecated("SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.", "rocket-chip 1.2") class SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asBool){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync) } } io.q := Cat(output.reverse) } object SyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred) } io.q := Cat(output.reverse) } object ResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}" val output = Seq.tabulate(w) { i => SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync) } io.q := Cat(output.reverse) } object SynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, None) def apply [T <: Data](in: T): T = apply (in, 3, None) } class ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module { override def desiredName = s"ClockCrossingReg_w${w}" val io = IO(new Bundle{ val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) val en = Input(Bool()) }) val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en) io.q := cdc_reg } object ClockCrossingReg { def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = { val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit)) name.foreach{ cdc_reg.suggestName(_) } cdc_reg.io.d := in.asUInt cdc_reg.io.en := en cdc_reg.io.q.asTypeOf(in) } }	module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_265( // @[SynchronizerReg.scala:68:19] input clock, // @[SynchronizerReg.scala:68:19] input reset, // @[SynchronizerReg.scala:68:19] input io_d, // @[ShiftReg.scala:36:14] output io_q // @[ShiftReg.scala:36:14] ); wire io_d_0 = io_d; // @[SynchronizerReg.scala:68:19] wire _sync_2_T = io_d_0; // @[SynchronizerReg.scala:54:22, :68:19] wire io_q_0; // @[SynchronizerReg.scala:68:19] reg sync_0; // @[SynchronizerReg.scala:51:87] assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19] reg sync_1; // @[SynchronizerReg.scala:51:87] reg sync_2; // @[SynchronizerReg.scala:51:87] always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19] if (reset) begin // @[SynchronizerReg.scala:68:19] sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87] end else begin // @[SynchronizerReg.scala:68:19] sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87] sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87] sync_2 <= _sync_2_T; // @[SynchronizerReg.scala:51:87, :54:22] end always @(posedge, posedge)
Generate the Verilog code corresponding to the following Chisel files. File PE.scala: // See README.md for license details. package gemmini import chisel3._ import chisel3.util._ class PEControl[T <: Data : Arithmetic](accType: T) extends Bundle { val dataflow = UInt(1.W) // TODO make this an Enum val propagate = UInt(1.W) // Which register should be propagated (and which should be accumulated)? val shift = UInt(log2Up(accType.getWidth).W) // TODO this isn't correct for Floats } class MacUnit[T <: Data](inputType: T, cType: T, dType: T) (implicit ev: Arithmetic[T]) extends Module { import ev._ val io = IO(new Bundle { val in_a = Input(inputType) val in_b = Input(inputType) val in_c = Input(cType) val out_d = Output(dType) }) io.out_d := io.in_c.mac(io.in_a, io.in_b) } // TODO update documentation /** * A PE implementing a MAC operation. Configured as fully combinational when integrated into a Mesh. * @param width Data width of operands / class PE[T <: Data](inputType: T, outputType: T, accType: T, df: Dataflow.Value, max_simultaneous_matmuls: Int) (implicit ev: Arithmetic[T]) extends Module { // Debugging variables import ev._ val io = IO(new Bundle { val in_a = Input(inputType) val in_b = Input(outputType) val in_d = Input(outputType) val out_a = Output(inputType) val out_b = Output(outputType) val out_c = Output(outputType) val in_control = Input(new PEControl(accType)) val out_control = Output(new PEControl(accType)) val in_id = Input(UInt(log2Up(max_simultaneous_matmuls).W)) val out_id = Output(UInt(log2Up(max_simultaneous_matmuls).W)) val in_last = Input(Bool()) val out_last = Output(Bool()) val in_valid = Input(Bool()) val out_valid = Output(Bool()) val bad_dataflow = Output(Bool()) }) val cType = if (df == Dataflow.WS) inputType else accType // When creating PEs that support multiple dataflows, the // elaboration/synthesis tools often fail to consolidate and de-duplicate // MAC units. To force mac circuitry to be re-used, we create a "mac_unit" // module here which just performs a single MAC operation val mac_unit = Module(new MacUnit(inputType, if (df == Dataflow.WS) outputType else accType, outputType)) val a = io.in_a val b = io.in_b val d = io.in_d val c1 = Reg(cType) val c2 = Reg(cType) val dataflow = io.in_control.dataflow val prop = io.in_control.propagate val shift = io.in_control.shift val id = io.in_id val last = io.in_last val valid = io.in_valid io.out_a := a io.out_control.dataflow := dataflow io.out_control.propagate := prop io.out_control.shift := shift io.out_id := id io.out_last := last io.out_valid := valid mac_unit.io.in_a := a val last_s = RegEnable(prop, valid) val flip = last_s =/= prop val shift_offset = Mux(flip, shift, 0.U) // Which dataflow are we using? val OUTPUT_STATIONARY = Dataflow.OS.id.U(1.W) val WEIGHT_STATIONARY = Dataflow.WS.id.U(1.W) // Is c1 being computed on, or propagated forward (in the output-stationary dataflow)? val COMPUTE = 0.U(1.W) val PROPAGATE = 1.U(1.W) io.bad_dataflow := false.B when ((df == Dataflow.OS).B \|\| ((df == Dataflow.BOTH).B && dataflow === OUTPUT_STATIONARY)) { when(prop === PROPAGATE) { io.out_c := (c1 >> shift_offset).clippedToWidthOf(outputType) io.out_b := b mac_unit.io.in_b := b.asTypeOf(inputType) mac_unit.io.in_c := c2 c2 := mac_unit.io.out_d c1 := d.withWidthOf(cType) }.otherwise { io.out_c := (c2 >> shift_offset).clippedToWidthOf(outputType) io.out_b := b mac_unit.io.in_b := b.asTypeOf(inputType) mac_unit.io.in_c := c1 c1 := mac_unit.io.out_d c2 := d.withWidthOf(cType) } }.elsewhen ((df == Dataflow.WS).B \|\| ((df == Dataflow.BOTH).B && dataflow === WEIGHT_STATIONARY)) { when(prop === PROPAGATE) { io.out_c := c1 mac_unit.io.in_b := c2.asTypeOf(inputType) mac_unit.io.in_c := b io.out_b := mac_unit.io.out_d c1 := d }.otherwise { io.out_c := c2 mac_unit.io.in_b := c1.asTypeOf(inputType) mac_unit.io.in_c := b io.out_b := mac_unit.io.out_d c2 := d } }.otherwise { io.bad_dataflow := true.B //assert(false.B, "unknown dataflow") io.out_c := DontCare io.out_b := DontCare mac_unit.io.in_b := b.asTypeOf(inputType) mac_unit.io.in_c := c2 } when (!valid) { c1 := c1 c2 := c2 mac_unit.io.in_b := DontCare mac_unit.io.in_c := DontCare } } File Arithmetic.scala: // A simple type class for Chisel datatypes that can add and multiply. To add your own type, simply create your own: // implicit MyTypeArithmetic extends Arithmetic[MyType] { ... } package gemmini import chisel3._ import chisel3.util._ import hardfloat._ // Bundles that represent the raw bits of custom datatypes case class Float(expWidth: Int, sigWidth: Int) extends Bundle { val bits = UInt((expWidth + sigWidth).W) val bias: Int = (1 << (expWidth-1)) - 1 } case class DummySInt(w: Int) extends Bundle { val bits = UInt(w.W) def dontCare: DummySInt = { val o = Wire(new DummySInt(w)) o.bits := 0.U o } } // The Arithmetic typeclass which implements various arithmetic operations on custom datatypes abstract class Arithmetic[T <: Data] { implicit def cast(t: T): ArithmeticOps[T] } abstract class ArithmeticOps[T <: Data](self: T) { def (t: T): T def mac(m1: T, m2: T): T // Returns (m1 * m2 + self) def +(t: T): T def -(t: T): T def >>(u: UInt): T // This is a rounding shift! Rounds away from 0 def >(t: T): Bool def identity: T def withWidthOf(t: T): T def clippedToWidthOf(t: T): T // Like "withWidthOf", except that it saturates def relu: T def zero: T def minimum: T // Optional parameters, which only need to be defined if you want to enable various optimizations for transformers def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[T])] = None def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[T])] = None def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = None def mult_with_reciprocal[U <: Data](reciprocal: U) = self } object Arithmetic { implicit object UIntArithmetic extends Arithmetic[UInt] { override implicit def cast(self: UInt) = new ArithmeticOps(self) { override def (t: UInt) = self t override def mac(m1: UInt, m2: UInt) = m1 * m2 + self override def +(t: UInt) = self + t override def -(t: UInt) = self - t override def >>(u: UInt) = { // The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm // TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here? val point_five = Mux(u === 0.U, 0.U, self(u - 1.U)) val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U val ones_digit = self(u) val r = point_five & (zeros \| ones_digit) (self >> u).asUInt + r } override def >(t: UInt): Bool = self > t override def withWidthOf(t: UInt) = self.asTypeOf(t) override def clippedToWidthOf(t: UInt) = { val sat = ((1 << (t.getWidth-1))-1).U Mux(self > sat, sat, self)(t.getWidth-1, 0) } override def relu: UInt = self override def zero: UInt = 0.U override def identity: UInt = 1.U override def minimum: UInt = 0.U } } implicit object SIntArithmetic extends Arithmetic[SInt] { override implicit def cast(self: SInt) = new ArithmeticOps(self) { override def (t: SInt) = self t override def mac(m1: SInt, m2: SInt) = m1 * m2 + self override def +(t: SInt) = self + t override def -(t: SInt) = self - t override def >>(u: UInt) = { // The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm // TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here? val point_five = Mux(u === 0.U, 0.U, self(u - 1.U)) val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U val ones_digit = self(u) val r = (point_five & (zeros \| ones_digit)).asBool (self >> u).asSInt + Mux(r, 1.S, 0.S) } override def >(t: SInt): Bool = self > t override def withWidthOf(t: SInt) = { if (self.getWidth >= t.getWidth) self(t.getWidth-1, 0).asSInt else { val sign_bits = t.getWidth - self.getWidth val sign = self(self.getWidth-1) Cat(Cat(Seq.fill(sign_bits)(sign)), self).asTypeOf(t) } } override def clippedToWidthOf(t: SInt): SInt = { val maxsat = ((1 << (t.getWidth-1))-1).S val minsat = (-(1 << (t.getWidth-1))).S MuxCase(self, Seq((self > maxsat) -> maxsat, (self < minsat) -> minsat))(t.getWidth-1, 0).asSInt } override def relu: SInt = Mux(self >= 0.S, self, 0.S) override def zero: SInt = 0.S override def identity: SInt = 1.S override def minimum: SInt = (-(1 << (self.getWidth-1))).S override def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = { // TODO this uses a floating point divider, but we should use an integer divider instead val input = Wire(Decoupled(denom_t.cloneType)) val output = Wire(Decoupled(self.cloneType)) // We translate our integer to floating-point form so that we can use the hardfloat divider val expWidth = log2Up(self.getWidth) + 1 val sigWidth = self.getWidth def sin_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def uin_to_float(x: UInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := false.B in_to_rec_fn.io.in := x in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def float_to_in(x: UInt) = { val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth)) rec_fn_to_in.io.signedOut := true.B rec_fn_to_in.io.in := x rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag rec_fn_to_in.io.out.asSInt } val self_rec = sin_to_float(self) val denom_rec = uin_to_float(input.bits) // Instantiate the hardloat divider val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options)) input.ready := divider.io.inReady divider.io.inValid := input.valid divider.io.sqrtOp := false.B divider.io.a := self_rec divider.io.b := denom_rec divider.io.roundingMode := consts.round_minMag divider.io.detectTininess := consts.tininess_afterRounding output.valid := divider.io.outValid_div output.bits := float_to_in(divider.io.out) assert(!output.valid \|\| output.ready) Some((input, output)) } override def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = { // TODO this uses a floating point divider, but we should use an integer divider instead val input = Wire(Decoupled(UInt(0.W))) val output = Wire(Decoupled(self.cloneType)) input.bits := DontCare // We translate our integer to floating-point form so that we can use the hardfloat divider val expWidth = log2Up(self.getWidth) + 1 val sigWidth = self.getWidth def in_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def float_to_in(x: UInt) = { val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth)) rec_fn_to_in.io.signedOut := true.B rec_fn_to_in.io.in := x rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag rec_fn_to_in.io.out.asSInt } val self_rec = in_to_float(self) // Instantiate the hardloat sqrt val sqrter = Module(new DivSqrtRecFN_small(expWidth, sigWidth, 0)) input.ready := sqrter.io.inReady sqrter.io.inValid := input.valid sqrter.io.sqrtOp := true.B sqrter.io.a := self_rec sqrter.io.b := DontCare sqrter.io.roundingMode := consts.round_minMag sqrter.io.detectTininess := consts.tininess_afterRounding output.valid := sqrter.io.outValid_sqrt output.bits := float_to_in(sqrter.io.out) assert(!output.valid \|\| output.ready) Some((input, output)) } override def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = u match { case Float(expWidth, sigWidth) => val input = Wire(Decoupled(UInt(0.W))) val output = Wire(Decoupled(u.cloneType)) input.bits := DontCare // We translate our integer to floating-point form so that we can use the hardfloat divider def in_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } val self_rec = in_to_float(self) val one_rec = in_to_float(1.S) // Instantiate the hardloat divider val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options)) input.ready := divider.io.inReady divider.io.inValid := input.valid divider.io.sqrtOp := false.B divider.io.a := one_rec divider.io.b := self_rec divider.io.roundingMode := consts.round_near_even divider.io.detectTininess := consts.tininess_afterRounding output.valid := divider.io.outValid_div output.bits := fNFromRecFN(expWidth, sigWidth, divider.io.out).asTypeOf(u) assert(!output.valid \|\| output.ready) Some((input, output)) case _ => None } override def mult_with_reciprocal[U <: Data](reciprocal: U): SInt = reciprocal match { case recip @ Float(expWidth, sigWidth) => def in_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def float_to_in(x: UInt) = { val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth)) rec_fn_to_in.io.signedOut := true.B rec_fn_to_in.io.in := x rec_fn_to_in.io.roundingMode := consts.round_minMag rec_fn_to_in.io.out.asSInt } val self_rec = in_to_float(self) val reciprocal_rec = recFNFromFN(expWidth, sigWidth, recip.bits) // Instantiate the hardloat divider val muladder = Module(new MulRecFN(expWidth, sigWidth)) muladder.io.roundingMode := consts.round_near_even muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := self_rec muladder.io.b := reciprocal_rec float_to_in(muladder.io.out) case _ => self } } } implicit object FloatArithmetic extends Arithmetic[Float] { // TODO Floating point arithmetic currently switches between recoded and standard formats for every operation. However, it should stay in the recoded format as it travels through the systolic array override implicit def cast(self: Float): ArithmeticOps[Float] = new ArithmeticOps(self) { override def (t: Float): Float = { val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth)) t_resizer.io.in := t_rec t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag t_resizer.io.detectTininess := consts.tininess_afterRounding val t_rec_resized = t_resizer.io.out val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth)) muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := self_rec muladder.io.b := t_rec_resized val out = Wire(Float(self.expWidth, self.sigWidth)) out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) out } override def mac(m1: Float, m2: Float): Float = { // Recode all operands val m1_rec = recFNFromFN(m1.expWidth, m1.sigWidth, m1.bits) val m2_rec = recFNFromFN(m2.expWidth, m2.sigWidth, m2.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Resize m1 to self's width val m1_resizer = Module(new RecFNToRecFN(m1.expWidth, m1.sigWidth, self.expWidth, self.sigWidth)) m1_resizer.io.in := m1_rec m1_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag m1_resizer.io.detectTininess := consts.tininess_afterRounding val m1_rec_resized = m1_resizer.io.out // Resize m2 to self's width val m2_resizer = Module(new RecFNToRecFN(m2.expWidth, m2.sigWidth, self.expWidth, self.sigWidth)) m2_resizer.io.in := m2_rec m2_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag m2_resizer.io.detectTininess := consts.tininess_afterRounding val m2_rec_resized = m2_resizer.io.out // Perform multiply-add val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth)) muladder.io.op := 0.U muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := m1_rec_resized muladder.io.b := m2_rec_resized muladder.io.c := self_rec // Convert result to standard format // TODO remove these intermediate recodings val out = Wire(Float(self.expWidth, self.sigWidth)) out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) out } override def +(t: Float): Float = { require(self.getWidth >= t.getWidth) // This just makes it easier to write the resizing code // Recode all operands val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Generate 1 as a float val in_to_rec_fn = Module(new INToRecFN(1, self.expWidth, self.sigWidth)) in_to_rec_fn.io.signedIn := false.B in_to_rec_fn.io.in := 1.U in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding val one_rec = in_to_rec_fn.io.out // Resize t val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth)) t_resizer.io.in := t_rec t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag t_resizer.io.detectTininess := consts.tininess_afterRounding val t_rec_resized = t_resizer.io.out // Perform addition val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth)) muladder.io.op := 0.U muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := t_rec_resized muladder.io.b := one_rec muladder.io.c := self_rec val result = Wire(Float(self.expWidth, self.sigWidth)) result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) result } override def -(t: Float): Float = { val t_sgn = t.bits(t.getWidth-1) val neg_t = Cat(~t_sgn, t.bits(t.getWidth-2,0)).asTypeOf(t) self + neg_t } override def >>(u: UInt): Float = { // Recode self val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Get 2^(-u) as a recoded float val shift_exp = Wire(UInt(self.expWidth.W)) shift_exp := self.bias.U - u val shift_fn = Cat(0.U(1.W), shift_exp, 0.U((self.sigWidth-1).W)) val shift_rec = recFNFromFN(self.expWidth, self.sigWidth, shift_fn) assert(shift_exp =/= 0.U, "scaling by denormalized numbers is not currently supported") // Multiply self and 2^(-u) val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth)) muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := self_rec muladder.io.b := shift_rec val result = Wire(Float(self.expWidth, self.sigWidth)) result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) result } override def >(t: Float): Bool = { // Recode all operands val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Resize t to self's width val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth)) t_resizer.io.in := t_rec t_resizer.io.roundingMode := consts.round_near_even t_resizer.io.detectTininess := consts.tininess_afterRounding val t_rec_resized = t_resizer.io.out val comparator = Module(new CompareRecFN(self.expWidth, self.sigWidth)) comparator.io.a := self_rec comparator.io.b := t_rec_resized comparator.io.signaling := false.B comparator.io.gt } override def withWidthOf(t: Float): Float = { val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth)) resizer.io.in := self_rec resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag resizer.io.detectTininess := consts.tininess_afterRounding val result = Wire(Float(t.expWidth, t.sigWidth)) result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out) result } override def clippedToWidthOf(t: Float): Float = { // TODO check for overflow. Right now, we just assume that overflow doesn't happen val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth)) resizer.io.in := self_rec resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag resizer.io.detectTininess := consts.tininess_afterRounding val result = Wire(Float(t.expWidth, t.sigWidth)) result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out) result } override def relu: Float = { val raw = rawFloatFromFN(self.expWidth, self.sigWidth, self.bits) val result = Wire(Float(self.expWidth, self.sigWidth)) result.bits := Mux(!raw.isZero && raw.sign, 0.U, self.bits) result } override def zero: Float = 0.U.asTypeOf(self) override def identity: Float = Cat(0.U(2.W), ~(0.U((self.expWidth-1).W)), 0.U((self.sigWidth-1).W)).asTypeOf(self) override def minimum: Float = Cat(1.U, ~(0.U(self.expWidth.W)), 0.U((self.sigWidth-1).W)).asTypeOf(self) } } implicit object DummySIntArithmetic extends Arithmetic[DummySInt] { override implicit def cast(self: DummySInt) = new ArithmeticOps(self) { override def (t: DummySInt) = self.dontCare override def mac(m1: DummySInt, m2: DummySInt) = self.dontCare override def +(t: DummySInt) = self.dontCare override def -(t: DummySInt) = self.dontCare override def >>(t: UInt) = self.dontCare override def >(t: DummySInt): Bool = false.B override def identity = self.dontCare override def withWidthOf(t: DummySInt) = self.dontCare override def clippedToWidthOf(t: DummySInt) = self.dontCare override def relu = self.dontCare override def zero = self.dontCare override def minimum: DummySInt = self.dontCare } } }	module PE_350( // @[PE.scala:31:7] input clock, // @[PE.scala:31:7] input reset, // @[PE.scala:31:7] input [7:0] io_in_a, // @[PE.scala:35:14] input [19:0] io_in_b, // @[PE.scala:35:14] input [19:0] io_in_d, // @[PE.scala:35:14] output [7:0] io_out_a, // @[PE.scala:35:14] output [19:0] io_out_b, // @[PE.scala:35:14] output [19:0] io_out_c, // @[PE.scala:35:14] input io_in_control_dataflow, // @[PE.scala:35:14] input io_in_control_propagate, // @[PE.scala:35:14] input [4:0] io_in_control_shift, // @[PE.scala:35:14] output io_out_control_dataflow, // @[PE.scala:35:14] output io_out_control_propagate, // @[PE.scala:35:14] output [4:0] io_out_control_shift, // @[PE.scala:35:14] input [2:0] io_in_id, // @[PE.scala:35:14] output [2:0] io_out_id, // @[PE.scala:35:14] input io_in_last, // @[PE.scala:35:14] output io_out_last, // @[PE.scala:35:14] input io_in_valid, // @[PE.scala:35:14] output io_out_valid // @[PE.scala:35:14] ); wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:31:7] wire [19:0] io_in_b_0 = io_in_b; // @[PE.scala:31:7] wire [19:0] io_in_d_0 = io_in_d; // @[PE.scala:31:7] wire io_in_control_dataflow_0 = io_in_control_dataflow; // @[PE.scala:31:7] wire io_in_control_propagate_0 = io_in_control_propagate; // @[PE.scala:31:7] wire [4:0] io_in_control_shift_0 = io_in_control_shift; // @[PE.scala:31:7] wire [2:0] io_in_id_0 = io_in_id; // @[PE.scala:31:7] wire io_in_last_0 = io_in_last; // @[PE.scala:31:7] wire io_in_valid_0 = io_in_valid; // @[PE.scala:31:7] wire io_bad_dataflow = 1'h0; // @[PE.scala:31:7] wire _io_out_c_T_5 = 1'h0; // @[Arithmetic.scala:125:33] wire _io_out_c_T_6 = 1'h0; // @[Arithmetic.scala:125:60] wire _io_out_c_T_16 = 1'h0; // @[Arithmetic.scala:125:33] wire _io_out_c_T_17 = 1'h0; // @[Arithmetic.scala:125:60] wire [7:0] io_out_a_0 = io_in_a_0; // @[PE.scala:31:7] wire [19:0] _mac_unit_io_in_b_T = io_in_b_0; // @[PE.scala:31:7, :106:37] wire [19:0] _mac_unit_io_in_b_T_2 = io_in_b_0; // @[PE.scala:31:7, :113:37] wire [19:0] _mac_unit_io_in_b_T_8 = io_in_b_0; // @[PE.scala:31:7, :137:35] wire io_out_control_dataflow_0 = io_in_control_dataflow_0; // @[PE.scala:31:7] wire io_out_control_propagate_0 = io_in_control_propagate_0; // @[PE.scala:31:7] wire [4:0] io_out_control_shift_0 = io_in_control_shift_0; // @[PE.scala:31:7] wire [2:0] io_out_id_0 = io_in_id_0; // @[PE.scala:31:7] wire io_out_last_0 = io_in_last_0; // @[PE.scala:31:7] wire io_out_valid_0 = io_in_valid_0; // @[PE.scala:31:7] wire [19:0] io_out_b_0; // @[PE.scala:31:7] wire [19:0] io_out_c_0; // @[PE.scala:31:7] reg [7:0] c1; // @[PE.scala:70:15] wire [7:0] _io_out_c_zeros_T_1 = c1; // @[PE.scala:70:15] wire [7:0] _mac_unit_io_in_b_T_6 = c1; // @[PE.scala:70:15, :127:38] reg [7:0] c2; // @[PE.scala:71:15] wire [7:0] _io_out_c_zeros_T_10 = c2; // @[PE.scala:71:15] wire [7:0] _mac_unit_io_in_b_T_4 = c2; // @[PE.scala:71:15, :121:38] reg last_s; // @[PE.scala:89:25] wire flip = last_s != io_in_control_propagate_0; // @[PE.scala:31:7, :89:25, :90:21] wire [4:0] shift_offset = flip ? io_in_control_shift_0 : 5'h0; // @[PE.scala:31:7, :90:21, :91:25] wire _GEN = shift_offset == 5'h0; // @[PE.scala:91:25] wire _io_out_c_point_five_T; // @[Arithmetic.scala:101:32] assign _io_out_c_point_five_T = _GEN; // @[Arithmetic.scala:101:32] wire _io_out_c_point_five_T_5; // @[Arithmetic.scala:101:32] assign _io_out_c_point_five_T_5 = _GEN; // @[Arithmetic.scala:101:32] wire [5:0] _GEN_0 = {1'h0, shift_offset} - 6'h1; // @[PE.scala:91:25] wire [5:0] _io_out_c_point_five_T_1; // @[Arithmetic.scala:101:53] assign _io_out_c_point_five_T_1 = _GEN_0; // @[Arithmetic.scala:101:53] wire [5:0] _io_out_c_zeros_T_2; // @[Arithmetic.scala:102:66] assign _io_out_c_zeros_T_2 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66] wire [5:0] _io_out_c_point_five_T_6; // @[Arithmetic.scala:101:53] assign _io_out_c_point_five_T_6 = _GEN_0; // @[Arithmetic.scala:101:53] wire [5:0] _io_out_c_zeros_T_11; // @[Arithmetic.scala:102:66] assign _io_out_c_zeros_T_11 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66] wire [4:0] _io_out_c_point_five_T_2 = _io_out_c_point_five_T_1[4:0]; // @[Arithmetic.scala:101:53] wire [7:0] _io_out_c_point_five_T_3 = $signed($signed(c1) >>> _io_out_c_point_five_T_2); // @[PE.scala:70:15] wire _io_out_c_point_five_T_4 = _io_out_c_point_five_T_3[0]; // @[Arithmetic.scala:101:50] wire io_out_c_point_five = ~_io_out_c_point_five_T & _io_out_c_point_five_T_4; // @[Arithmetic.scala:101:{29,32,50}] wire _GEN_1 = shift_offset < 5'h2; // @[PE.scala:91:25] wire _io_out_c_zeros_T; // @[Arithmetic.scala:102:27] assign _io_out_c_zeros_T = _GEN_1; // @[Arithmetic.scala:102:27] wire _io_out_c_zeros_T_9; // @[Arithmetic.scala:102:27] assign _io_out_c_zeros_T_9 = _GEN_1; // @[Arithmetic.scala:102:27] wire [4:0] _io_out_c_zeros_T_3 = _io_out_c_zeros_T_2[4:0]; // @[Arithmetic.scala:102:66] wire [31:0] _io_out_c_zeros_T_4 = 32'h1 << _io_out_c_zeros_T_3; // @[Arithmetic.scala:102:{60,66}] wire [32:0] _io_out_c_zeros_T_5 = {1'h0, _io_out_c_zeros_T_4} - 33'h1; // @[Arithmetic.scala:102:{60,81}] wire [31:0] _io_out_c_zeros_T_6 = _io_out_c_zeros_T_5[31:0]; // @[Arithmetic.scala:102:81] wire [31:0] _io_out_c_zeros_T_7 = {24'h0, _io_out_c_zeros_T_6[7:0] & _io_out_c_zeros_T_1}; // @[Arithmetic.scala:102:{45,52,81}] wire [31:0] _io_out_c_zeros_T_8 = _io_out_c_zeros_T ? 32'h0 : _io_out_c_zeros_T_7; // @[Arithmetic.scala:102:{24,27,52}] wire io_out_c_zeros = \|_io_out_c_zeros_T_8; // @[Arithmetic.scala:102:{24,89}] wire [7:0] _GEN_2 = {3'h0, shift_offset}; // @[PE.scala:91:25] wire [7:0] _GEN_3 = $signed($signed(c1) >>> _GEN_2); // @[PE.scala:70:15] wire [7:0] _io_out_c_ones_digit_T; // @[Arithmetic.scala:103:30] assign _io_out_c_ones_digit_T = _GEN_3; // @[Arithmetic.scala:103:30] wire [7:0] _io_out_c_T; // @[Arithmetic.scala:107:15] assign _io_out_c_T = _GEN_3; // @[Arithmetic.scala:103:30, :107:15] wire io_out_c_ones_digit = _io_out_c_ones_digit_T[0]; // @[Arithmetic.scala:103:30] wire _io_out_c_r_T = io_out_c_zeros \| io_out_c_ones_digit; // @[Arithmetic.scala:102:89, :103:30, :105:38] wire _io_out_c_r_T_1 = io_out_c_point_five & _io_out_c_r_T; // @[Arithmetic.scala:101:29, :105:{29,38}] wire io_out_c_r = _io_out_c_r_T_1; // @[Arithmetic.scala:105:{29,53}] wire [1:0] _io_out_c_T_1 = {1'h0, io_out_c_r}; // @[Arithmetic.scala:105:53, :107:33] wire [8:0] _io_out_c_T_2 = {_io_out_c_T[7], _io_out_c_T} + {{7{_io_out_c_T_1[1]}}, _io_out_c_T_1}; // @[Arithmetic.scala:107:{15,28,33}] wire [7:0] _io_out_c_T_3 = _io_out_c_T_2[7:0]; // @[Arithmetic.scala:107:28] wire [7:0] _io_out_c_T_4 = _io_out_c_T_3; // @[Arithmetic.scala:107:28] wire [19:0] _io_out_c_T_7 = {{12{_io_out_c_T_4[7]}}, _io_out_c_T_4}; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_8 = _io_out_c_T_7; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_9 = _io_out_c_T_8; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_10 = _io_out_c_T_9; // @[Arithmetic.scala:125:{81,99}] wire [19:0] _mac_unit_io_in_b_T_1 = _mac_unit_io_in_b_T; // @[PE.scala:106:37] wire [7:0] _mac_unit_io_in_b_WIRE = _mac_unit_io_in_b_T_1[7:0]; // @[PE.scala:106:37] wire [7:0] _c1_T = io_in_d_0[7:0]; // @[PE.scala:31:7] wire [7:0] _c2_T = io_in_d_0[7:0]; // @[PE.scala:31:7] wire [7:0] _c1_T_1 = _c1_T; // @[Arithmetic.scala:114:{15,33}] wire [4:0] _io_out_c_point_five_T_7 = _io_out_c_point_five_T_6[4:0]; // @[Arithmetic.scala:101:53] wire [7:0] _io_out_c_point_five_T_8 = $signed($signed(c2) >>> _io_out_c_point_five_T_7); // @[PE.scala:71:15] wire _io_out_c_point_five_T_9 = _io_out_c_point_five_T_8[0]; // @[Arithmetic.scala:101:50] wire io_out_c_point_five_1 = ~_io_out_c_point_five_T_5 & _io_out_c_point_five_T_9; // @[Arithmetic.scala:101:{29,32,50}] wire [4:0] _io_out_c_zeros_T_12 = _io_out_c_zeros_T_11[4:0]; // @[Arithmetic.scala:102:66] wire [31:0] _io_out_c_zeros_T_13 = 32'h1 << _io_out_c_zeros_T_12; // @[Arithmetic.scala:102:{60,66}] wire [32:0] _io_out_c_zeros_T_14 = {1'h0, _io_out_c_zeros_T_13} - 33'h1; // @[Arithmetic.scala:102:{60,81}] wire [31:0] _io_out_c_zeros_T_15 = _io_out_c_zeros_T_14[31:0]; // @[Arithmetic.scala:102:81] wire [31:0] _io_out_c_zeros_T_16 = {24'h0, _io_out_c_zeros_T_15[7:0] & _io_out_c_zeros_T_10}; // @[Arithmetic.scala:102:{45,52,81}] wire [31:0] _io_out_c_zeros_T_17 = _io_out_c_zeros_T_9 ? 32'h0 : _io_out_c_zeros_T_16; // @[Arithmetic.scala:102:{24,27,52}] wire io_out_c_zeros_1 = \|_io_out_c_zeros_T_17; // @[Arithmetic.scala:102:{24,89}] wire [7:0] _GEN_4 = $signed($signed(c2) >>> _GEN_2); // @[PE.scala:71:15] wire [7:0] _io_out_c_ones_digit_T_1; // @[Arithmetic.scala:103:30] assign _io_out_c_ones_digit_T_1 = _GEN_4; // @[Arithmetic.scala:103:30] wire [7:0] _io_out_c_T_11; // @[Arithmetic.scala:107:15] assign _io_out_c_T_11 = _GEN_4; // @[Arithmetic.scala:103:30, :107:15] wire io_out_c_ones_digit_1 = _io_out_c_ones_digit_T_1[0]; // @[Arithmetic.scala:103:30] wire _io_out_c_r_T_2 = io_out_c_zeros_1 \| io_out_c_ones_digit_1; // @[Arithmetic.scala:102:89, :103:30, :105:38] wire _io_out_c_r_T_3 = io_out_c_point_five_1 & _io_out_c_r_T_2; // @[Arithmetic.scala:101:29, :105:{29,38}] wire io_out_c_r_1 = _io_out_c_r_T_3; // @[Arithmetic.scala:105:{29,53}] wire [1:0] _io_out_c_T_12 = {1'h0, io_out_c_r_1}; // @[Arithmetic.scala:105:53, :107:33] wire [8:0] _io_out_c_T_13 = {_io_out_c_T_11[7], _io_out_c_T_11} + {{7{_io_out_c_T_12[1]}}, _io_out_c_T_12}; // @[Arithmetic.scala:107:{15,28,33}] wire [7:0] _io_out_c_T_14 = _io_out_c_T_13[7:0]; // @[Arithmetic.scala:107:28] wire [7:0] _io_out_c_T_15 = _io_out_c_T_14; // @[Arithmetic.scala:107:28] wire [19:0] _io_out_c_T_18 = {{12{_io_out_c_T_15[7]}}, _io_out_c_T_15}; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_19 = _io_out_c_T_18; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_20 = _io_out_c_T_19; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_21 = _io_out_c_T_20; // @[Arithmetic.scala:125:{81,99}] wire [19:0] _mac_unit_io_in_b_T_3 = _mac_unit_io_in_b_T_2; // @[PE.scala:113:37] wire [7:0] _mac_unit_io_in_b_WIRE_1 = _mac_unit_io_in_b_T_3[7:0]; // @[PE.scala:113:37] wire [7:0] _c2_T_1 = _c2_T; // @[Arithmetic.scala:114:{15,33}] wire [7:0] _mac_unit_io_in_b_T_5; // @[PE.scala:121:38] assign _mac_unit_io_in_b_T_5 = _mac_unit_io_in_b_T_4; // @[PE.scala:121:38] wire [7:0] _mac_unit_io_in_b_WIRE_2 = _mac_unit_io_in_b_T_5; // @[PE.scala:121:38] assign io_out_c_0 = io_in_control_propagate_0 ? {{12{c1[7]}}, c1} : {{12{c2[7]}}, c2}; // @[PE.scala:31:7, :70:15, :71:15, :119:30, :120:16, :126:16] wire [7:0] _mac_unit_io_in_b_T_7; // @[PE.scala:127:38] assign _mac_unit_io_in_b_T_7 = _mac_unit_io_in_b_T_6; // @[PE.scala:127:38] wire [7:0] _mac_unit_io_in_b_WIRE_3 = _mac_unit_io_in_b_T_7; // @[PE.scala:127:38] wire [19:0] _mac_unit_io_in_b_T_9 = _mac_unit_io_in_b_T_8; // @[PE.scala:137:35] wire [7:0] _mac_unit_io_in_b_WIRE_4 = _mac_unit_io_in_b_T_9[7:0]; // @[PE.scala:137:35] always @(posedge clock) begin // @[PE.scala:31:7] if (io_in_valid_0 & io_in_control_propagate_0) // @[PE.scala:31:7, :102:95, :141:17, :142:8] c1 <= io_in_d_0[7:0]; // @[PE.scala:31:7, :70:15] if (~(~io_in_valid_0 \| io_in_control_propagate_0)) // @[PE.scala:31:7, :71:15, :102:95, :119:30, :130:10, :141:{9,17}, :143:8] c2 <= io_in_d_0[7:0]; // @[PE.scala:31:7, :71:15] if (io_in_valid_0) // @[PE.scala:31:7] last_s <= io_in_control_propagate_0; // @[PE.scala:31:7, :89:25] always @(posedge) MacUnit_94 mac_unit ( // @[PE.scala:64:24] .clock (clock), .reset (reset), .io_in_a (io_in_a_0), // @[PE.scala:31:7] .io_in_b (io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE_2 : _mac_unit_io_in_b_WIRE_3), // @[PE.scala:31:7, :119:30, :121:{24,38}, :127:{24,38}] .io_in_c (io_in_b_0), // @[PE.scala:31:7] .io_out_d (io_out_b_0) ); // @[PE.scala:64:24] assign io_out_a = io_out_a_0; // @[PE.scala:31:7] assign io_out_b = io_out_b_0; // @[PE.scala:31:7] assign io_out_c = io_out_c_0; // @[PE.scala:31:7] assign io_out_control_dataflow = io_out_control_dataflow_0; // @[PE.scala:31:7] assign io_out_control_propagate = io_out_control_propagate_0; // @[PE.scala:31:7] assign io_out_control_shift = io_out_control_shift_0; // @[PE.scala:31:7] assign io_out_id = io_out_id_0; // @[PE.scala:31:7] assign io_out_last = io_out_last_0; // @[PE.scala:31:7] assign io_out_valid = io_out_valid_0; // @[PE.scala:31:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File UnsafeAXI4ToTL.scala: package ara import chisel3._ import chisel3.util._ import freechips.rocketchip.amba._ import freechips.rocketchip.amba.axi4._ import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.diplomacy._ import freechips.rocketchip.tilelink._ import freechips.rocketchip.util._ class ReorderData(val dataWidth: Int, val respWidth: Int, val userFields: Seq[BundleFieldBase]) extends Bundle { val data = UInt(dataWidth.W) val resp = UInt(respWidth.W) val last = Bool() val user = BundleMap(userFields) } /** Parameters for [[BaseReservableListBuffer]] and all child classes. * * @param numEntries Total number of elements that can be stored in the 'data' RAM * @param numLists Maximum number of linked lists * @param numBeats Maximum number of beats per entry / case class ReservableListBufferParameters(numEntries: Int, numLists: Int, numBeats: Int) { // Avoid zero-width wires when we call 'log2Ceil' val entryBits = if (numEntries == 1) 1 else log2Ceil(numEntries) val listBits = if (numLists == 1) 1 else log2Ceil(numLists) val beatBits = if (numBeats == 1) 1 else log2Ceil(numBeats) } case class UnsafeAXI4ToTLNode(numTlTxns: Int, wcorrupt: Boolean)(implicit valName: ValName) extends MixedAdapterNode(AXI4Imp, TLImp)( dFn = { case mp => TLMasterPortParameters.v2( masters = mp.masters.zipWithIndex.map { case (m, i) => // Support 'numTlTxns' read requests and 'numTlTxns' write requests at once. val numSourceIds = numTlTxns 2 TLMasterParameters.v2( name = m.name, sourceId = IdRange(i * numSourceIds, (i + 1) * numSourceIds), nodePath = m.nodePath ) }, echoFields = mp.echoFields, requestFields = AMBAProtField() +: mp.requestFields, responseKeys = mp.responseKeys ) }, uFn = { mp => AXI4SlavePortParameters( slaves = mp.managers.map { m => val maxXfer = TransferSizes(1, mp.beatBytes * (1 << AXI4Parameters.lenBits)) AXI4SlaveParameters( address = m.address, resources = m.resources, regionType = m.regionType, executable = m.executable, nodePath = m.nodePath, supportsWrite = m.supportsPutPartial.intersect(maxXfer), supportsRead = m.supportsGet.intersect(maxXfer), interleavedId = Some(0) // TL2 never interleaves D beats ) }, beatBytes = mp.beatBytes, minLatency = mp.minLatency, responseFields = mp.responseFields, requestKeys = (if (wcorrupt) Seq(AMBACorrupt) else Seq()) ++ mp.requestKeys.filter(_ != AMBAProt) ) } ) class UnsafeAXI4ToTL(numTlTxns: Int, wcorrupt: Boolean)(implicit p: Parameters) extends LazyModule { require(numTlTxns >= 1) require(isPow2(numTlTxns), s"Number of TileLink transactions ($numTlTxns) must be a power of 2") val node = UnsafeAXI4ToTLNode(numTlTxns, wcorrupt) lazy val module = new LazyModuleImp(this) { (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => edgeIn.master.masters.foreach { m => require(m.aligned, "AXI4ToTL requires aligned requests") } val numIds = edgeIn.master.endId val beatBytes = edgeOut.slave.beatBytes val maxTransfer = edgeOut.slave.maxTransfer val maxBeats = maxTransfer / beatBytes // Look for an Error device to redirect bad requests val errorDevs = edgeOut.slave.managers.filter(_.nodePath.last.lazyModule.className == "TLError") require(!errorDevs.isEmpty, "There is no TLError reachable from AXI4ToTL. One must be instantiated.") val errorDev = errorDevs.maxBy(_.maxTransfer) val errorDevAddr = errorDev.address.head.base require( errorDev.supportsPutPartial.contains(maxTransfer), s"Error device supports ${errorDev.supportsPutPartial} PutPartial but must support $maxTransfer" ) require( errorDev.supportsGet.contains(maxTransfer), s"Error device supports ${errorDev.supportsGet} Get but must support $maxTransfer" ) // All of the read-response reordering logic. val listBufData = new ReorderData(beatBytes * 8, edgeIn.bundle.respBits, out.d.bits.user.fields) val listBufParams = ReservableListBufferParameters(numTlTxns, numIds, maxBeats) val listBuffer = if (numTlTxns > 1) { Module(new ReservableListBuffer(listBufData, listBufParams)) } else { Module(new PassthroughListBuffer(listBufData, listBufParams)) } // To differentiate between read and write transaction IDs, we will set the MSB of the TileLink 'source' field to // 0 for read requests and 1 for write requests. val isReadSourceBit = 0.U(1.W) val isWriteSourceBit = 1.U(1.W) /* Read request logic / val rOut = Wire(Decoupled(new TLBundleA(edgeOut.bundle))) val rBytes1 = in.ar.bits.bytes1() val rSize = OH1ToUInt(rBytes1) val rOk = edgeOut.slave.supportsGetSafe(in.ar.bits.addr, rSize) val rId = if (numTlTxns > 1) { Cat(isReadSourceBit, listBuffer.ioReservedIndex) } else { isReadSourceBit } val rAddr = Mux(rOk, in.ar.bits.addr, errorDevAddr.U \| in.ar.bits.addr(log2Ceil(beatBytes) - 1, 0)) // Indicates if there are still valid TileLink source IDs left to use. val canIssueR = listBuffer.ioReserve.ready listBuffer.ioReserve.bits := in.ar.bits.id listBuffer.ioReserve.valid := in.ar.valid && rOut.ready in.ar.ready := rOut.ready && canIssueR rOut.valid := in.ar.valid && canIssueR rOut.bits :<= edgeOut.Get(rId, rAddr, rSize)._2 rOut.bits.user :<= in.ar.bits.user rOut.bits.user.lift(AMBAProt).foreach { rProt => rProt.privileged := in.ar.bits.prot(0) rProt.secure := !in.ar.bits.prot(1) rProt.fetch := in.ar.bits.prot(2) rProt.bufferable := in.ar.bits.cache(0) rProt.modifiable := in.ar.bits.cache(1) rProt.readalloc := in.ar.bits.cache(2) rProt.writealloc := in.ar.bits.cache(3) } / Write request logic / // Strip off the MSB, which identifies the transaction as read vs write. val strippedResponseSourceId = if (numTlTxns > 1) { out.d.bits.source((out.d.bits.source).getWidth - 2, 0) } else { // When there's only 1 TileLink transaction allowed for read/write, then this field is always 0. 0.U(1.W) } // Track when a write request burst is in progress. val writeBurstBusy = RegInit(false.B) when(in.w.fire) { writeBurstBusy := !in.w.bits.last } val usedWriteIds = RegInit(0.U(numTlTxns.W)) val canIssueW = !usedWriteIds.andR val usedWriteIdsSet = WireDefault(0.U(numTlTxns.W)) val usedWriteIdsClr = WireDefault(0.U(numTlTxns.W)) usedWriteIds := (usedWriteIds & ~usedWriteIdsClr) \| usedWriteIdsSet // Since write responses can show up in the middle of a write burst, we need to ensure the write burst ID doesn't // change mid-burst. val freeWriteIdOHRaw = Wire(UInt(numTlTxns.W)) val freeWriteIdOH = freeWriteIdOHRaw holdUnless !writeBurstBusy val freeWriteIdIndex = OHToUInt(freeWriteIdOH) freeWriteIdOHRaw := ~(leftOR(~usedWriteIds) << 1) & ~usedWriteIds val wOut = Wire(Decoupled(new TLBundleA(edgeOut.bundle))) val wBytes1 = in.aw.bits.bytes1() val wSize = OH1ToUInt(wBytes1) val wOk = edgeOut.slave.supportsPutPartialSafe(in.aw.bits.addr, wSize) val wId = if (numTlTxns > 1) { Cat(isWriteSourceBit, freeWriteIdIndex) } else { isWriteSourceBit } val wAddr = Mux(wOk, in.aw.bits.addr, errorDevAddr.U \| in.aw.bits.addr(log2Ceil(beatBytes) - 1, 0)) // Here, we're taking advantage of the Irrevocable behavior of AXI4 (once 'valid' is asserted it must remain // asserted until the handshake occurs). We will only accept W-channel beats when we have a valid AW beat, but // the AW-channel beat won't fire until the final W-channel beat fires. So, we have stable address/size/strb // bits during a W-channel burst. in.aw.ready := wOut.ready && in.w.valid && in.w.bits.last && canIssueW in.w.ready := wOut.ready && in.aw.valid && canIssueW wOut.valid := in.aw.valid && in.w.valid && canIssueW wOut.bits :<= edgeOut.Put(wId, wAddr, wSize, in.w.bits.data, in.w.bits.strb)._2 in.w.bits.user.lift(AMBACorrupt).foreach { wOut.bits.corrupt := _ } wOut.bits.user :<= in.aw.bits.user wOut.bits.user.lift(AMBAProt).foreach { wProt => wProt.privileged := in.aw.bits.prot(0) wProt.secure := !in.aw.bits.prot(1) wProt.fetch := in.aw.bits.prot(2) wProt.bufferable := in.aw.bits.cache(0) wProt.modifiable := in.aw.bits.cache(1) wProt.readalloc := in.aw.bits.cache(2) wProt.writealloc := in.aw.bits.cache(3) } // Merge the AXI4 read/write requests into the TL-A channel. TLArbiter(TLArbiter.roundRobin)(out.a, (0.U, rOut), (in.aw.bits.len, wOut)) / Read/write response logic / val okB = Wire(Irrevocable(new AXI4BundleB(edgeIn.bundle))) val okR = Wire(Irrevocable(new AXI4BundleR(edgeIn.bundle))) val dResp = Mux(out.d.bits.denied \|\| out.d.bits.corrupt, AXI4Parameters.RESP_SLVERR, AXI4Parameters.RESP_OKAY) val dHasData = edgeOut.hasData(out.d.bits) val (_dFirst, dLast, _dDone, dCount) = edgeOut.count(out.d) val dNumBeats1 = edgeOut.numBeats1(out.d.bits) // Handle cases where writeack arrives before write is done val writeEarlyAck = (UIntToOH(strippedResponseSourceId) & usedWriteIds) === 0.U out.d.ready := Mux(dHasData, listBuffer.ioResponse.ready, okB.ready && !writeEarlyAck) listBuffer.ioDataOut.ready := okR.ready okR.valid := listBuffer.ioDataOut.valid okB.valid := out.d.valid && !dHasData && !writeEarlyAck listBuffer.ioResponse.valid := out.d.valid && dHasData listBuffer.ioResponse.bits.index := strippedResponseSourceId listBuffer.ioResponse.bits.data.data := out.d.bits.data listBuffer.ioResponse.bits.data.resp := dResp listBuffer.ioResponse.bits.data.last := dLast listBuffer.ioResponse.bits.data.user :<= out.d.bits.user listBuffer.ioResponse.bits.count := dCount listBuffer.ioResponse.bits.numBeats1 := dNumBeats1 okR.bits.id := listBuffer.ioDataOut.bits.listIndex okR.bits.data := listBuffer.ioDataOut.bits.payload.data okR.bits.resp := listBuffer.ioDataOut.bits.payload.resp okR.bits.last := listBuffer.ioDataOut.bits.payload.last okR.bits.user :<= listBuffer.ioDataOut.bits.payload.user // Upon the final beat in a write request, record a mapping from TileLink source ID to AXI write ID. Upon a write // response, mark the write transaction as complete. val writeIdMap = Mem(numTlTxns, UInt(log2Ceil(numIds).W)) val writeResponseId = writeIdMap.read(strippedResponseSourceId) when(wOut.fire) { writeIdMap.write(freeWriteIdIndex, in.aw.bits.id) } when(edgeOut.done(wOut)) { usedWriteIdsSet := freeWriteIdOH } when(okB.fire) { usedWriteIdsClr := UIntToOH(strippedResponseSourceId, numTlTxns) } okB.bits.id := writeResponseId okB.bits.resp := dResp okB.bits.user :<= out.d.bits.user // AXI4 needs irrevocable behaviour in.r <> Queue.irrevocable(okR, 1, flow = true) in.b <> Queue.irrevocable(okB, 1, flow = true) // Unused channels out.b.ready := true.B out.c.valid := false.B out.e.valid := false.B / Alignment constraints. The AXI4Fragmenter should guarantee all of these constraints. / def checkRequest[T <: AXI4BundleA](a: IrrevocableIO[T], reqType: String): Unit = { val lReqType = reqType.toLowerCase when(a.valid) { assert(a.bits.len < maxBeats.U, s"$reqType burst length (%d) must be less than $maxBeats", a.bits.len + 1.U) // Narrow transfers and FIXED bursts must be single-beat bursts. when(a.bits.len =/= 0.U) { assert( a.bits.size === log2Ceil(beatBytes).U, s"Narrow $lReqType transfers (%d < $beatBytes bytes) can't be multi-beat bursts (%d beats)", 1.U << a.bits.size, a.bits.len + 1.U ) assert( a.bits.burst =/= AXI4Parameters.BURST_FIXED, s"Fixed $lReqType bursts can't be multi-beat bursts (%d beats)", a.bits.len + 1.U ) } // Furthermore, the transfer size (a.bits.bytes1() + 1.U) must be naturally-aligned to the address (in // particular, during both WRAP and INCR bursts), but this constraint is already checked by TileLink // Monitors. Note that this alignment requirement means that WRAP bursts are identical to INCR bursts. } } checkRequest(in.ar, "Read") checkRequest(in.aw, "Write") } } } object UnsafeAXI4ToTL { def apply(numTlTxns: Int = 1, wcorrupt: Boolean = true)(implicit p: Parameters) = { val axi42tl = LazyModule(new UnsafeAXI4ToTL(numTlTxns, wcorrupt)) axi42tl.node } } / ReservableListBuffer logic, and associated classes. / class ResponsePayload[T <: Data](val data: T, val params: ReservableListBufferParameters) extends Bundle { val index = UInt(params.entryBits.W) val count = UInt(params.beatBits.W) val numBeats1 = UInt(params.beatBits.W) } class DataOutPayload[T <: Data](val payload: T, val params: ReservableListBufferParameters) extends Bundle { val listIndex = UInt(params.listBits.W) } /* Abstract base class to unify [[ReservableListBuffer]] and [[PassthroughListBuffer]]. / abstract class BaseReservableListBuffer[T <: Data](gen: T, params: ReservableListBufferParameters) extends Module { require(params.numEntries > 0) require(params.numLists > 0) val ioReserve = IO(Flipped(Decoupled(UInt(params.listBits.W)))) val ioReservedIndex = IO(Output(UInt(params.entryBits.W))) val ioResponse = IO(Flipped(Decoupled(new ResponsePayload(gen, params)))) val ioDataOut = IO(Decoupled(new DataOutPayload(gen, params))) } /* A modified version of 'ListBuffer' from 'sifive/block-inclusivecache-sifive'. This module forces users to reserve * linked list entries (through the 'ioReserve' port) before writing data into those linked lists (through the * 'ioResponse' port). Each response is tagged to indicate which linked list it is written into. The responses for a * given linked list can come back out-of-order, but they will be read out through the 'ioDataOut' port in-order. * * ==Constructor== * @param gen Chisel type of linked list data element * @param params Other parameters * * ==Module IO== * @param ioReserve Index of list to reserve a new element in * @param ioReservedIndex Index of the entry that was reserved in the linked list, valid when 'ioReserve.fire' * @param ioResponse Payload containing response data and linked-list-entry index * @param ioDataOut Payload containing data read from response linked list and linked list index / class ReservableListBuffer[T <: Data](gen: T, params: ReservableListBufferParameters) extends BaseReservableListBuffer(gen, params) { val valid = RegInit(0.U(params.numLists.W)) val head = Mem(params.numLists, UInt(params.entryBits.W)) val tail = Mem(params.numLists, UInt(params.entryBits.W)) val used = RegInit(0.U(params.numEntries.W)) val next = Mem(params.numEntries, UInt(params.entryBits.W)) val map = Mem(params.numEntries, UInt(params.listBits.W)) val dataMems = Seq.fill(params.numBeats) { SyncReadMem(params.numEntries, gen) } val dataIsPresent = RegInit(0.U(params.numEntries.W)) val beats = Mem(params.numEntries, UInt(params.beatBits.W)) // The 'data' SRAM should be single-ported (read-or-write), since dual-ported SRAMs are significantly slower. val dataMemReadEnable = WireDefault(false.B) val dataMemWriteEnable = WireDefault(false.B) assert(!(dataMemReadEnable && dataMemWriteEnable)) // 'freeOH' has a single bit set, which is the least-significant bit that is cleared in 'used'. So, it's the // lowest-index entry in the 'data' RAM which is free. val freeOH = Wire(UInt(params.numEntries.W)) val freeIndex = OHToUInt(freeOH) freeOH := ~(leftOR(~used) << 1) & ~used ioReservedIndex := freeIndex val validSet = WireDefault(0.U(params.numLists.W)) val validClr = WireDefault(0.U(params.numLists.W)) val usedSet = WireDefault(0.U(params.numEntries.W)) val usedClr = WireDefault(0.U(params.numEntries.W)) val dataIsPresentSet = WireDefault(0.U(params.numEntries.W)) val dataIsPresentClr = WireDefault(0.U(params.numEntries.W)) valid := (valid & ~validClr) \| validSet used := (used & ~usedClr) \| usedSet dataIsPresent := (dataIsPresent & ~dataIsPresentClr) \| dataIsPresentSet / Reservation logic signals / val reserveTail = Wire(UInt(params.entryBits.W)) val reserveIsValid = Wire(Bool()) / Response logic signals / val responseIndex = Wire(UInt(params.entryBits.W)) val responseListIndex = Wire(UInt(params.listBits.W)) val responseHead = Wire(UInt(params.entryBits.W)) val responseTail = Wire(UInt(params.entryBits.W)) val nextResponseHead = Wire(UInt(params.entryBits.W)) val nextDataIsPresent = Wire(Bool()) val isResponseInOrder = Wire(Bool()) val isEndOfList = Wire(Bool()) val isLastBeat = Wire(Bool()) val isLastResponseBeat = Wire(Bool()) val isLastUnwindBeat = Wire(Bool()) / Reservation logic / reserveTail := tail.read(ioReserve.bits) reserveIsValid := valid(ioReserve.bits) ioReserve.ready := !used.andR // When we want to append-to and destroy the same linked list on the same cycle, we need to take special care that we // actually start a new list, rather than appending to a list that's about to disappear. val reserveResponseSameList = ioReserve.bits === responseListIndex val appendToAndDestroyList = ioReserve.fire && ioDataOut.fire && reserveResponseSameList && isEndOfList && isLastBeat when(ioReserve.fire) { validSet := UIntToOH(ioReserve.bits, params.numLists) usedSet := freeOH when(reserveIsValid && !appendToAndDestroyList) { next.write(reserveTail, freeIndex) }.otherwise { head.write(ioReserve.bits, freeIndex) } tail.write(ioReserve.bits, freeIndex) map.write(freeIndex, ioReserve.bits) } / Response logic / // The majority of the response logic (reading from and writing to the various RAMs) is common between the // response-from-IO case (ioResponse.fire) and the response-from-unwind case (unwindDataIsValid). // The read from the 'next' RAM should be performed at the address given by 'responseHead'. However, we only use the // 'nextResponseHead' signal when 'isResponseInOrder' is asserted (both in the response-from-IO and // response-from-unwind cases), which implies that 'responseHead' equals 'responseIndex'. 'responseHead' comes after // two back-to-back RAM reads, so indexing into the 'next' RAM with 'responseIndex' is much quicker. responseHead := head.read(responseListIndex) responseTail := tail.read(responseListIndex) nextResponseHead := next.read(responseIndex) nextDataIsPresent := dataIsPresent(nextResponseHead) // Note that when 'isEndOfList' is asserted, 'nextResponseHead' (and therefore 'nextDataIsPresent') is invalid, since // there isn't a next element in the linked list. isResponseInOrder := responseHead === responseIndex isEndOfList := responseHead === responseTail isLastResponseBeat := ioResponse.bits.count === ioResponse.bits.numBeats1 // When a response's last beat is sent to the output channel, mark it as completed. This can happen in two // situations: // 1. We receive an in-order response, which travels straight from 'ioResponse' to 'ioDataOut'. The 'data' SRAM // reservation was never needed. // 2. An entry is read out of the 'data' SRAM (within the unwind FSM). when(ioDataOut.fire && isLastBeat) { // Mark the reservation as no-longer-used. usedClr := UIntToOH(responseIndex, params.numEntries) // If the response is in-order, then we're popping an element from this linked list. when(isEndOfList) { // Once we pop the last element from a linked list, mark it as no-longer-present. validClr := UIntToOH(responseListIndex, params.numLists) }.otherwise { // Move the linked list's head pointer to the new head pointer. head.write(responseListIndex, nextResponseHead) } } // If we get an out-of-order response, then stash it in the 'data' SRAM for later unwinding. when(ioResponse.fire && !isResponseInOrder) { dataMemWriteEnable := true.B when(isLastResponseBeat) { dataIsPresentSet := UIntToOH(ioResponse.bits.index, params.numEntries) beats.write(ioResponse.bits.index, ioResponse.bits.numBeats1) } } // Use the 'ioResponse.bits.count' index (AKA the beat number) to select which 'data' SRAM to write to. val responseCountOH = UIntToOH(ioResponse.bits.count, params.numBeats) (responseCountOH.asBools zip dataMems) foreach { case (select, seqMem) => when(select && dataMemWriteEnable) { seqMem.write(ioResponse.bits.index, ioResponse.bits.data) } } / Response unwind logic / // Unwind FSM state definitions val sIdle :: sUnwinding :: Nil = Enum(2) val unwindState = RegInit(sIdle) val busyUnwinding = unwindState === sUnwinding val startUnwind = Wire(Bool()) val stopUnwind = Wire(Bool()) when(startUnwind) { unwindState := sUnwinding }.elsewhen(stopUnwind) { unwindState := sIdle } assert(!(startUnwind && stopUnwind)) // Start the unwind FSM when there is an old out-of-order response stored in the 'data' SRAM that is now about to // become the next in-order response. As noted previously, when 'isEndOfList' is asserted, 'nextDataIsPresent' is // invalid. // // Note that since an in-order response from 'ioResponse' to 'ioDataOut' starts the unwind FSM, we don't have to // worry about overwriting the 'data' SRAM's output when we start the unwind FSM. startUnwind := ioResponse.fire && isResponseInOrder && isLastResponseBeat && !isEndOfList && nextDataIsPresent // Stop the unwind FSM when the output channel consumes the final beat of an element from the unwind FSM, and one of // two things happens: // 1. We're still waiting for the next in-order response for this list (!nextDataIsPresent) // 2. There are no more outstanding responses in this list (isEndOfList) // // Including 'busyUnwinding' ensures this is a single-cycle pulse, and it never fires while in-order transactions are // passing from 'ioResponse' to 'ioDataOut'. stopUnwind := busyUnwinding && ioDataOut.fire && isLastUnwindBeat && (!nextDataIsPresent \|\| isEndOfList) val isUnwindBurstOver = Wire(Bool()) val startNewBurst = startUnwind \|\| (isUnwindBurstOver && dataMemReadEnable) // Track the number of beats left to unwind for each list entry. At the start of a new burst, we flop the number of // beats in this burst (minus 1) into 'unwindBeats1', and we reset the 'beatCounter' counter. With each beat, we // increment 'beatCounter' until it reaches 'unwindBeats1'. val unwindBeats1 = Reg(UInt(params.beatBits.W)) val nextBeatCounter = Wire(UInt(params.beatBits.W)) val beatCounter = RegNext(nextBeatCounter) isUnwindBurstOver := beatCounter === unwindBeats1 when(startNewBurst) { unwindBeats1 := beats.read(nextResponseHead) nextBeatCounter := 0.U }.elsewhen(dataMemReadEnable) { nextBeatCounter := beatCounter + 1.U }.otherwise { nextBeatCounter := beatCounter } // When unwinding, feed the next linked-list head pointer (read out of the 'next' RAM) back so we can unwind the next // entry in this linked list. Only update the pointer when we're actually moving to the next 'data' SRAM entry (which // happens at the start of reading a new stored burst). val unwindResponseIndex = RegEnable(nextResponseHead, startNewBurst) responseIndex := Mux(busyUnwinding, unwindResponseIndex, ioResponse.bits.index) // Hold 'nextResponseHead' static while we're in the middle of unwinding a multi-beat burst entry. We don't want the // SRAM read address to shift while reading beats from a burst. Note that this is identical to 'nextResponseHead // holdUnless startNewBurst', but 'unwindResponseIndex' already implements the 'RegEnable' signal in 'holdUnless'. val unwindReadAddress = Mux(startNewBurst, nextResponseHead, unwindResponseIndex) // The 'data' SRAM's output is valid if we read from the SRAM on the previous cycle. The SRAM's output stays valid // until it is consumed by the output channel (and if we don't read from the SRAM again on that same cycle). val unwindDataIsValid = RegInit(false.B) when(dataMemReadEnable) { unwindDataIsValid := true.B }.elsewhen(ioDataOut.fire) { unwindDataIsValid := false.B } isLastUnwindBeat := isUnwindBurstOver && unwindDataIsValid // Indicates if this is the last beat for both 'ioResponse'-to-'ioDataOut' and unwind-to-'ioDataOut' beats. isLastBeat := Mux(busyUnwinding, isLastUnwindBeat, isLastResponseBeat) // Select which SRAM to read from based on the beat counter. val dataOutputVec = Wire(Vec(params.numBeats, gen)) val nextBeatCounterOH = UIntToOH(nextBeatCounter, params.numBeats) (nextBeatCounterOH.asBools zip dataMems).zipWithIndex foreach { case ((select, seqMem), i) => dataOutputVec(i) := seqMem.read(unwindReadAddress, select && dataMemReadEnable) } // Select the current 'data' SRAM output beat, and save the output in a register in case we're being back-pressured // by 'ioDataOut'. This implements the functionality of 'readAndHold', but only on the single SRAM we're reading // from. val dataOutput = dataOutputVec(beatCounter) holdUnless RegNext(dataMemReadEnable) // Mark 'data' burst entries as no-longer-present as they get read out of the SRAM. when(dataMemReadEnable) { dataIsPresentClr := UIntToOH(unwindReadAddress, params.numEntries) } // As noted above, when starting the unwind FSM, we know the 'data' SRAM's output isn't valid, so it's safe to issue // a read command. Otherwise, only issue an SRAM read when the next 'unwindState' is 'sUnwinding', and if we know // we're not going to overwrite the SRAM's current output (the SRAM output is already valid, and it's not going to be // consumed by the output channel). val dontReadFromDataMem = unwindDataIsValid && !ioDataOut.ready dataMemReadEnable := startUnwind \|\| (busyUnwinding && !stopUnwind && !dontReadFromDataMem) // While unwinding, prevent new reservations from overwriting the current 'map' entry that we're using. We need // 'responseListIndex' to be coherent for the entire unwind process. val rawResponseListIndex = map.read(responseIndex) val unwindResponseListIndex = RegEnable(rawResponseListIndex, startNewBurst) responseListIndex := Mux(busyUnwinding, unwindResponseListIndex, rawResponseListIndex) // Accept responses either when they can be passed through to the output channel, or if they're out-of-order and are // just going to be stashed in the 'data' SRAM. Never accept a response payload when we're busy unwinding, since that // could result in reading from and writing to the 'data' SRAM in the same cycle, and we want that SRAM to be // single-ported. ioResponse.ready := (ioDataOut.ready \|\| !isResponseInOrder) && !busyUnwinding // Either pass an in-order response to the output channel, or data read from the unwind FSM. ioDataOut.valid := Mux(busyUnwinding, unwindDataIsValid, ioResponse.valid && isResponseInOrder) ioDataOut.bits.listIndex := responseListIndex ioDataOut.bits.payload := Mux(busyUnwinding, dataOutput, ioResponse.bits.data) // It's an error to get a response that isn't associated with a valid linked list. when(ioResponse.fire \|\| unwindDataIsValid) { assert( valid(responseListIndex), "No linked list exists at index %d, mapped from %d", responseListIndex, responseIndex ) } when(busyUnwinding && dataMemReadEnable) { assert(isResponseInOrder, "Unwind FSM must read entries from SRAM in order") } } /* Specialized version of [[ReservableListBuffer]] for the case of numEntries == 1. * * Much of the complex logic in [[ReservableListBuffer]] can disappear in this case. For instance, we don't have to * reorder any responses, or store any linked lists. */ class PassthroughListBuffer[T <: Data](gen: T, params: ReservableListBufferParameters) extends BaseReservableListBuffer(gen, params) { require(params.numEntries == 1, s"PassthroughListBuffer is only valid when 'numEntries' (${params.numEntries}) is 1") val used = RegInit(0.U(params.numEntries.W)) val map = Mem(params.numEntries, UInt(params.listBits.W)) val usedSet = WireDefault(0.U(params.numEntries.W)) val usedClr = WireDefault(0.U(params.numEntries.W)) used := (used & ~usedClr) \| usedSet ioReserve.ready := used === 0.U // Store which list index was reserved, we need to return this value when we get a response. when(ioReserve.fire) { usedSet := 1.U map.write(0.U, ioReserve.bits) } // There's only one valid linked list entry, which is at index 0. ioReservedIndex := 0.U val isLastResponseBeat = ioResponse.bits.count === ioResponse.bits.numBeats1 // Mark the linked list as empty when we get the last beat in a response. // Note that 'ioResponse.fire === ioDataOut.fire'. when(ioResponse.fire && isLastResponseBeat) { usedClr := 1.U } // Always pass the response data straight through, since we never need to reorder the response data. ioDataOut.bits.listIndex := map.read(0.U) ioDataOut.bits.payload := ioResponse.bits.data ioDataOut.valid := ioResponse.valid ioResponse.ready := ioDataOut.ready }	module dataMems_333( // @[UnsafeAXI4ToTL.scala:365:62] input [4:0] R0_addr, input R0_en, input R0_clk, output [66:0] R0_data, input [4:0] W0_addr, input W0_en, input W0_clk, input [66:0] W0_data ); dataMems_0_ext dataMems_0_ext ( // @[UnsafeAXI4ToTL.scala:365:62] .R0_addr (R0_addr), .R0_en (R0_en), .R0_clk (R0_clk), .R0_data (R0_data), .W0_addr (W0_addr), .W0_en (W0_en), .W0_clk (W0_clk), .W0_data (W0_data) ); // @[UnsafeAXI4ToTL.scala:365:62] endmodule
Generate the Verilog code corresponding to the following Chisel files. File util.scala: //**************************************************************************** // Copyright (c) 2015 - 2019, The Regents of the University of California (Regents). // All Rights Reserved. See LICENSE and LICENSE.SiFive for license details. //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ // Utility Functions //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ package boom.v3.util import chisel3._ import chisel3.util._ import freechips.rocketchip.rocket.Instructions._ import freechips.rocketchip.rocket._ import freechips.rocketchip.util.{Str} import org.chipsalliance.cde.config.{Parameters} import freechips.rocketchip.tile.{TileKey} import boom.v3.common.{MicroOp} import boom.v3.exu.{BrUpdateInfo} / * Object to XOR fold a input register of fullLength into a compressedLength. / object Fold { def apply(input: UInt, compressedLength: Int, fullLength: Int): UInt = { val clen = compressedLength val hlen = fullLength if (hlen <= clen) { input } else { var res = 0.U(clen.W) var remaining = input.asUInt for (i <- 0 to hlen-1 by clen) { val len = if (i + clen > hlen ) (hlen - i) else clen require(len > 0) res = res(clen-1,0) ^ remaining(len-1,0) remaining = remaining >> len.U } res } } } /* * Object to check if MicroOp was killed due to a branch mispredict. * Uses "Fast" branch masks / object IsKilledByBranch { def apply(brupdate: BrUpdateInfo, uop: MicroOp): Bool = { return maskMatch(brupdate.b1.mispredict_mask, uop.br_mask) } def apply(brupdate: BrUpdateInfo, uop_mask: UInt): Bool = { return maskMatch(brupdate.b1.mispredict_mask, uop_mask) } } /* * Object to return new MicroOp with a new BR mask given a MicroOp mask * and old BR mask. / object GetNewUopAndBrMask { def apply(uop: MicroOp, brupdate: BrUpdateInfo) (implicit p: Parameters): MicroOp = { val newuop = WireInit(uop) newuop.br_mask := uop.br_mask & ~brupdate.b1.resolve_mask newuop } } /* * Object to return a BR mask given a MicroOp mask and old BR mask. / object GetNewBrMask { def apply(brupdate: BrUpdateInfo, uop: MicroOp): UInt = { return uop.br_mask & ~brupdate.b1.resolve_mask } def apply(brupdate: BrUpdateInfo, br_mask: UInt): UInt = { return br_mask & ~brupdate.b1.resolve_mask } } object UpdateBrMask { def apply(brupdate: BrUpdateInfo, uop: MicroOp): MicroOp = { val out = WireInit(uop) out.br_mask := GetNewBrMask(brupdate, uop) out } def apply[T <: boom.v3.common.HasBoomUOP](brupdate: BrUpdateInfo, bundle: T): T = { val out = WireInit(bundle) out.uop.br_mask := GetNewBrMask(brupdate, bundle.uop.br_mask) out } def apply[T <: boom.v3.common.HasBoomUOP](brupdate: BrUpdateInfo, bundle: Valid[T]): Valid[T] = { val out = WireInit(bundle) out.bits.uop.br_mask := GetNewBrMask(brupdate, bundle.bits.uop.br_mask) out.valid := bundle.valid && !IsKilledByBranch(brupdate, bundle.bits.uop.br_mask) out } } /* * Object to check if at least 1 bit matches in two masks / object maskMatch { def apply(msk1: UInt, msk2: UInt): Bool = (msk1 & msk2) =/= 0.U } /* * Object to clear one bit in a mask given an index / object clearMaskBit { def apply(msk: UInt, idx: UInt): UInt = (msk & ~(1.U << idx))(msk.getWidth-1, 0) } /* * Object to shift a register over by one bit and concat a new one / object PerformShiftRegister { def apply(reg_val: UInt, new_bit: Bool): UInt = { reg_val := Cat(reg_val(reg_val.getWidth-1, 0).asUInt, new_bit.asUInt).asUInt reg_val } } /* * Object to shift a register over by one bit, wrapping the top bit around to the bottom * (XOR'ed with a new-bit), and evicting a bit at index HLEN. * This is used to simulate a longer HLEN-width shift register that is folded * down to a compressed CLEN. / object PerformCircularShiftRegister { def apply(csr: UInt, new_bit: Bool, evict_bit: Bool, hlen: Int, clen: Int): UInt = { val carry = csr(clen-1) val newval = Cat(csr, new_bit ^ carry) ^ (evict_bit << (hlen % clen).U) newval } } /* * Object to increment an input value, wrapping it if * necessary. / object WrapAdd { // "n" is the number of increments, so we wrap at n-1. def apply(value: UInt, amt: UInt, n: Int): UInt = { if (isPow2(n)) { (value + amt)(log2Ceil(n)-1,0) } else { val sum = Cat(0.U(1.W), value) + Cat(0.U(1.W), amt) Mux(sum >= n.U, sum - n.U, sum) } } } /* * Object to decrement an input value, wrapping it if * necessary. / object WrapSub { // "n" is the number of increments, so we wrap to n-1. def apply(value: UInt, amt: Int, n: Int): UInt = { if (isPow2(n)) { (value - amt.U)(log2Ceil(n)-1,0) } else { val v = Cat(0.U(1.W), value) val b = Cat(0.U(1.W), amt.U) Mux(value >= amt.U, value - amt.U, n.U - amt.U + value) } } } /* * Object to increment an input value, wrapping it if * necessary. / object WrapInc { // "n" is the number of increments, so we wrap at n-1. def apply(value: UInt, n: Int): UInt = { if (isPow2(n)) { (value + 1.U)(log2Ceil(n)-1,0) } else { val wrap = (value === (n-1).U) Mux(wrap, 0.U, value + 1.U) } } } /* * Object to decrement an input value, wrapping it if * necessary. / object WrapDec { // "n" is the number of increments, so we wrap at n-1. def apply(value: UInt, n: Int): UInt = { if (isPow2(n)) { (value - 1.U)(log2Ceil(n)-1,0) } else { val wrap = (value === 0.U) Mux(wrap, (n-1).U, value - 1.U) } } } /* * Object to mask off lower bits of a PC to align to a "b" * Byte boundary. / object AlignPCToBoundary { def apply(pc: UInt, b: Int): UInt = { // Invert for scenario where pc longer than b // (which would clear all bits above size(b)). ~(~pc \| (b-1).U) } } /* * Object to rotate a signal left by one / object RotateL1 { def apply(signal: UInt): UInt = { val w = signal.getWidth val out = Cat(signal(w-2,0), signal(w-1)) return out } } /* * Object to sext a value to a particular length. / object Sext { def apply(x: UInt, length: Int): UInt = { if (x.getWidth == length) return x else return Cat(Fill(length-x.getWidth, x(x.getWidth-1)), x) } } /* * Object to translate from BOOM's special "packed immediate" to a 32b signed immediate * Asking for U-type gives it shifted up 12 bits. / object ImmGen { import boom.v3.common.{LONGEST_IMM_SZ, IS_B, IS_I, IS_J, IS_S, IS_U} def apply(ip: UInt, isel: UInt): SInt = { val sign = ip(LONGEST_IMM_SZ-1).asSInt val i30_20 = Mux(isel === IS_U, ip(18,8).asSInt, sign) val i19_12 = Mux(isel === IS_U \|\| isel === IS_J, ip(7,0).asSInt, sign) val i11 = Mux(isel === IS_U, 0.S, Mux(isel === IS_J \|\| isel === IS_B, ip(8).asSInt, sign)) val i10_5 = Mux(isel === IS_U, 0.S, ip(18,14).asSInt) val i4_1 = Mux(isel === IS_U, 0.S, ip(13,9).asSInt) val i0 = Mux(isel === IS_S \|\| isel === IS_I, ip(8).asSInt, 0.S) return Cat(sign, i30_20, i19_12, i11, i10_5, i4_1, i0).asSInt } } /* * Object to get the FP rounding mode out of a packed immediate. / object ImmGenRm { def apply(ip: UInt): UInt = { return ip(2,0) } } /* * Object to get the FP function fype from a packed immediate. * Note: only works if !(IS_B or IS_S) / object ImmGenTyp { def apply(ip: UInt): UInt = { return ip(9,8) } } /* * Object to see if an instruction is a JALR. / object DebugIsJALR { def apply(inst: UInt): Bool = { // TODO Chisel not sure why this won't compile // val is_jalr = rocket.DecodeLogic(inst, List(Bool(false)), // Array( // JALR -> Bool(true))) inst(6,0) === "b1100111".U } } /* * Object to take an instruction and output its branch or jal target. Only used * for a debug assert (no where else would we jump straight from instruction * bits to a target). / object DebugGetBJImm { def apply(inst: UInt): UInt = { // TODO Chisel not sure why this won't compile //val csignals = //rocket.DecodeLogic(inst, // List(Bool(false), Bool(false)), // Array( // BEQ -> List(Bool(true ), Bool(false)), // BNE -> List(Bool(true ), Bool(false)), // BGE -> List(Bool(true ), Bool(false)), // BGEU -> List(Bool(true ), Bool(false)), // BLT -> List(Bool(true ), Bool(false)), // BLTU -> List(Bool(true ), Bool(false)) // )) //val is_br :: nothing :: Nil = csignals val is_br = (inst(6,0) === "b1100011".U) val br_targ = Cat(Fill(12, inst(31)), Fill(8,inst(31)), inst(7), inst(30,25), inst(11,8), 0.U(1.W)) val jal_targ= Cat(Fill(12, inst(31)), inst(19,12), inst(20), inst(30,25), inst(24,21), 0.U(1.W)) Mux(is_br, br_targ, jal_targ) } } /* * Object to return the lowest bit position after the head. / object AgePriorityEncoder { def apply(in: Seq[Bool], head: UInt): UInt = { val n = in.size val width = log2Ceil(in.size) val n_padded = 1 << width val temp_vec = (0 until n_padded).map(i => if (i < n) in(i) && i.U >= head else false.B) ++ in val idx = PriorityEncoder(temp_vec) idx(width-1, 0) //discard msb } } /* * Object to determine whether queue * index i0 is older than index i1. / object IsOlder { def apply(i0: UInt, i1: UInt, head: UInt) = ((i0 < i1) ^ (i0 < head) ^ (i1 < head)) } /* * Set all bits at or below the highest order '1'. / object MaskLower { def apply(in: UInt) = { val n = in.getWidth (0 until n).map(i => in >> i.U).reduce(_\|_) } } /* * Set all bits at or above the lowest order '1'. / object MaskUpper { def apply(in: UInt) = { val n = in.getWidth (0 until n).map(i => (in << i.U)(n-1,0)).reduce(_\|_) } } /* * Transpose a matrix of Chisel Vecs. / object Transpose { def apply[T <: chisel3.Data](in: Vec[Vec[T]]) = { val n = in(0).size VecInit((0 until n).map(i => VecInit(in.map(row => row(i))))) } } /* * N-wide one-hot priority encoder. / object SelectFirstN { def apply(in: UInt, n: Int) = { val sels = Wire(Vec(n, UInt(in.getWidth.W))) var mask = in for (i <- 0 until n) { sels(i) := PriorityEncoderOH(mask) mask = mask & ~sels(i) } sels } } /* * Connect the first k of n valid input interfaces to k output interfaces. / class Compactor[T <: chisel3.Data](n: Int, k: Int, gen: T) extends Module { require(n >= k) val io = IO(new Bundle { val in = Vec(n, Flipped(DecoupledIO(gen))) val out = Vec(k, DecoupledIO(gen)) }) if (n == k) { io.out <> io.in } else { val counts = io.in.map(_.valid).scanLeft(1.U(k.W)) ((c,e) => Mux(e, (c<<1)(k-1,0), c)) val sels = Transpose(VecInit(counts map (c => VecInit(c.asBools)))) map (col => (col zip io.in.map(_.valid)) map {case (c,v) => c && v}) val in_readys = counts map (row => (row.asBools zip io.out.map(_.ready)) map {case (c,r) => c && r} reduce (_\|\|_)) val out_valids = sels map (col => col.reduce(_\|\|_)) val out_data = sels map (s => Mux1H(s, io.in.map(_.bits))) in_readys zip io.in foreach {case (r,i) => i.ready := r} out_valids zip out_data zip io.out foreach {case ((v,d),o) => o.valid := v; o.bits := d} } } /* * Create a queue that can be killed with a branch kill signal. * Assumption: enq.valid only high if not killed by branch (so don't check IsKilled on io.enq). / class BranchKillableQueue[T <: boom.v3.common.HasBoomUOP](gen: T, entries: Int, flush_fn: boom.v3.common.MicroOp => Bool = u => true.B, flow: Boolean = true) (implicit p: org.chipsalliance.cde.config.Parameters) extends boom.v3.common.BoomModule()(p) with boom.v3.common.HasBoomCoreParameters { val io = IO(new Bundle { val enq = Flipped(Decoupled(gen)) val deq = Decoupled(gen) val brupdate = Input(new BrUpdateInfo()) val flush = Input(Bool()) val empty = Output(Bool()) val count = Output(UInt(log2Ceil(entries).W)) }) val ram = Mem(entries, gen) val valids = RegInit(VecInit(Seq.fill(entries) {false.B})) val uops = Reg(Vec(entries, new MicroOp)) val enq_ptr = Counter(entries) val deq_ptr = Counter(entries) val maybe_full = RegInit(false.B) val ptr_match = enq_ptr.value === deq_ptr.value io.empty := ptr_match && !maybe_full val full = ptr_match && maybe_full val do_enq = WireInit(io.enq.fire) val do_deq = WireInit((io.deq.ready \|\| !valids(deq_ptr.value)) && !io.empty) for (i <- 0 until entries) { val mask = uops(i).br_mask val uop = uops(i) valids(i) := valids(i) && !IsKilledByBranch(io.brupdate, mask) && !(io.flush && flush_fn(uop)) when (valids(i)) { uops(i).br_mask := GetNewBrMask(io.brupdate, mask) } } when (do_enq) { ram(enq_ptr.value) := io.enq.bits valids(enq_ptr.value) := true.B //!IsKilledByBranch(io.brupdate, io.enq.bits.uop) uops(enq_ptr.value) := io.enq.bits.uop uops(enq_ptr.value).br_mask := GetNewBrMask(io.brupdate, io.enq.bits.uop) enq_ptr.inc() } when (do_deq) { valids(deq_ptr.value) := false.B deq_ptr.inc() } when (do_enq =/= do_deq) { maybe_full := do_enq } io.enq.ready := !full val out = Wire(gen) out := ram(deq_ptr.value) out.uop := uops(deq_ptr.value) io.deq.valid := !io.empty && valids(deq_ptr.value) && !IsKilledByBranch(io.brupdate, out.uop) && !(io.flush && flush_fn(out.uop)) io.deq.bits := out io.deq.bits.uop.br_mask := GetNewBrMask(io.brupdate, out.uop) // For flow queue behavior. if (flow) { when (io.empty) { io.deq.valid := io.enq.valid //&& !IsKilledByBranch(io.brupdate, io.enq.bits.uop) io.deq.bits := io.enq.bits io.deq.bits.uop.br_mask := GetNewBrMask(io.brupdate, io.enq.bits.uop) do_deq := false.B when (io.deq.ready) { do_enq := false.B } } } private val ptr_diff = enq_ptr.value - deq_ptr.value if (isPow2(entries)) { io.count := Cat(maybe_full && ptr_match, ptr_diff) } else { io.count := Mux(ptr_match, Mux(maybe_full, entries.asUInt, 0.U), Mux(deq_ptr.value > enq_ptr.value, entries.asUInt + ptr_diff, ptr_diff)) } } // ------------------------------------------ // Printf helper functions // ------------------------------------------ object BoolToChar { /* * Take in a Chisel Bool and convert it into a Str * based on the Chars given * * @param c_bool Chisel Bool * @param trueChar Scala Char if bool is true * @param falseChar Scala Char if bool is false * @return UInt ASCII Char for "trueChar" or "falseChar" / def apply(c_bool: Bool, trueChar: Char, falseChar: Char = '-'): UInt = { Mux(c_bool, Str(trueChar), Str(falseChar)) } } object CfiTypeToChars { /* * Get a Vec of Strs that can be used for printing * * @param cfi_type specific cfi type * @return Vec of Strs (must be indexed to get specific char) / def apply(cfi_type: UInt) = { val strings = Seq("----", "BR ", "JAL ", "JALR") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(cfi_type) } } object BpdTypeToChars { /* * Get a Vec of Strs that can be used for printing * * @param bpd_type specific bpd type * @return Vec of Strs (must be indexed to get specific char) / def apply(bpd_type: UInt) = { val strings = Seq("BR ", "JUMP", "----", "RET ", "----", "CALL", "----", "----") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(bpd_type) } } object RobTypeToChars { /* * Get a Vec of Strs that can be used for printing * * @param rob_type specific rob type * @return Vec of Strs (must be indexed to get specific char) / def apply(rob_type: UInt) = { val strings = Seq("RST", "NML", "RBK", " WT") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(rob_type) } } object XRegToChars { /* * Get a Vec of Strs that can be used for printing * * @param xreg specific register number * @return Vec of Strs (must be indexed to get specific char) / def apply(xreg: UInt) = { val strings = Seq(" x0", " ra", " sp", " gp", " tp", " t0", " t1", " t2", " s0", " s1", " a0", " a1", " a2", " a3", " a4", " a5", " a6", " a7", " s2", " s3", " s4", " s5", " s6", " s7", " s8", " s9", "s10", "s11", " t3", " t4", " t5", " t6") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(xreg) } } object FPRegToChars { /* * Get a Vec of Strs that can be used for printing * * @param fpreg specific register number * @return Vec of Strs (must be indexed to get specific char) / def apply(fpreg: UInt) = { val strings = Seq(" ft0", " ft1", " ft2", " ft3", " ft4", " ft5", " ft6", " ft7", " fs0", " fs1", " fa0", " fa1", " fa2", " fa3", " fa4", " fa5", " fa6", " fa7", " fs2", " fs3", " fs4", " fs5", " fs6", " fs7", " fs8", " fs9", "fs10", "fs11", " ft8", " ft9", "ft10", "ft11") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(fpreg) } } object BoomCoreStringPrefix { /* * Add prefix to BOOM strings (currently only adds the hartId) * * @param strs list of strings * @return String combining the list with the prefix per line / def apply(strs: String)(implicit p: Parameters) = { val prefix = "[C" + s"${p(TileKey).tileId}" + "] " strs.map(str => prefix + str + "\n").mkString("") } } File consts.scala: //**************************************************************************** // Copyright (c) 2011 - 2018, The Regents of the University of California (Regents). // All Rights Reserved. See LICENSE and LICENSE.SiFive for license details. //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ // RISCV Processor Constants //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ package boom.v3.common.constants import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util.Str import freechips.rocketchip.rocket.RVCExpander / * Mixin for issue queue types / trait IQType { val IQT_SZ = 3 val IQT_INT = 1.U(IQT_SZ.W) val IQT_MEM = 2.U(IQT_SZ.W) val IQT_FP = 4.U(IQT_SZ.W) val IQT_MFP = 6.U(IQT_SZ.W) } /* * Mixin for scalar operation constants / trait ScalarOpConstants { val X = BitPat("b?") val Y = BitPat("b1") val N = BitPat("b0") //********************************* // Extra Constants // Which branch predictor predicted us val BSRC_SZ = 2 val BSRC_1 = 0.U(BSRC_SZ.W) // 1-cycle branch pred val BSRC_2 = 1.U(BSRC_SZ.W) // 2-cycle branch pred val BSRC_3 = 2.U(BSRC_SZ.W) // 3-cycle branch pred val BSRC_C = 3.U(BSRC_SZ.W) // core branch resolution //******************************** // Control Signals // CFI types val CFI_SZ = 3 val CFI_X = 0.U(CFI_SZ.W) // Not a CFI instruction val CFI_BR = 1.U(CFI_SZ.W) // Branch val CFI_JAL = 2.U(CFI_SZ.W) // JAL val CFI_JALR = 3.U(CFI_SZ.W) // JALR // PC Select Signal val PC_PLUS4 = 0.U(2.W) // PC + 4 val PC_BRJMP = 1.U(2.W) // brjmp_target val PC_JALR = 2.U(2.W) // jump_reg_target // Branch Type val BR_N = 0.U(4.W) // Next val BR_NE = 1.U(4.W) // Branch on NotEqual val BR_EQ = 2.U(4.W) // Branch on Equal val BR_GE = 3.U(4.W) // Branch on Greater/Equal val BR_GEU = 4.U(4.W) // Branch on Greater/Equal Unsigned val BR_LT = 5.U(4.W) // Branch on Less Than val BR_LTU = 6.U(4.W) // Branch on Less Than Unsigned val BR_J = 7.U(4.W) // Jump val BR_JR = 8.U(4.W) // Jump Register // RS1 Operand Select Signal val OP1_RS1 = 0.U(2.W) // Register Source #1 val OP1_ZERO= 1.U(2.W) val OP1_PC = 2.U(2.W) val OP1_X = BitPat("b??") // RS2 Operand Select Signal val OP2_RS2 = 0.U(3.W) // Register Source #2 val OP2_IMM = 1.U(3.W) // immediate val OP2_ZERO= 2.U(3.W) // constant 0 val OP2_NEXT= 3.U(3.W) // constant 2/4 (for PC+2/4) val OP2_IMMC= 4.U(3.W) // for CSR imm found in RS1 val OP2_X = BitPat("b???") // Register File Write Enable Signal val REN_0 = false.B val REN_1 = true.B // Is 32b Word or 64b Doubldword? val SZ_DW = 1 val DW_X = true.B // Bool(xLen==64) val DW_32 = false.B val DW_64 = true.B val DW_XPR = true.B // Bool(xLen==64) // Memory Enable Signal val MEN_0 = false.B val MEN_1 = true.B val MEN_X = false.B // Immediate Extend Select val IS_I = 0.U(3.W) // I-Type (LD,ALU) val IS_S = 1.U(3.W) // S-Type (ST) val IS_B = 2.U(3.W) // SB-Type (BR) val IS_U = 3.U(3.W) // U-Type (LUI/AUIPC) val IS_J = 4.U(3.W) // UJ-Type (J/JAL) val IS_X = BitPat("b???") // Decode Stage Control Signals val RT_FIX = 0.U(2.W) val RT_FLT = 1.U(2.W) val RT_PAS = 3.U(2.W) // pass-through (prs1 := lrs1, etc) val RT_X = 2.U(2.W) // not-a-register (but shouldn't get a busy-bit, etc.) // TODO rename RT_NAR // Micro-op opcodes // TODO change micro-op opcodes into using enum val UOPC_SZ = 7 val uopX = BitPat.dontCare(UOPC_SZ) val uopNOP = 0.U(UOPC_SZ.W) val uopLD = 1.U(UOPC_SZ.W) val uopSTA = 2.U(UOPC_SZ.W) // store address generation val uopSTD = 3.U(UOPC_SZ.W) // store data generation val uopLUI = 4.U(UOPC_SZ.W) val uopADDI = 5.U(UOPC_SZ.W) val uopANDI = 6.U(UOPC_SZ.W) val uopORI = 7.U(UOPC_SZ.W) val uopXORI = 8.U(UOPC_SZ.W) val uopSLTI = 9.U(UOPC_SZ.W) val uopSLTIU= 10.U(UOPC_SZ.W) val uopSLLI = 11.U(UOPC_SZ.W) val uopSRAI = 12.U(UOPC_SZ.W) val uopSRLI = 13.U(UOPC_SZ.W) val uopSLL = 14.U(UOPC_SZ.W) val uopADD = 15.U(UOPC_SZ.W) val uopSUB = 16.U(UOPC_SZ.W) val uopSLT = 17.U(UOPC_SZ.W) val uopSLTU = 18.U(UOPC_SZ.W) val uopAND = 19.U(UOPC_SZ.W) val uopOR = 20.U(UOPC_SZ.W) val uopXOR = 21.U(UOPC_SZ.W) val uopSRA = 22.U(UOPC_SZ.W) val uopSRL = 23.U(UOPC_SZ.W) val uopBEQ = 24.U(UOPC_SZ.W) val uopBNE = 25.U(UOPC_SZ.W) val uopBGE = 26.U(UOPC_SZ.W) val uopBGEU = 27.U(UOPC_SZ.W) val uopBLT = 28.U(UOPC_SZ.W) val uopBLTU = 29.U(UOPC_SZ.W) val uopCSRRW= 30.U(UOPC_SZ.W) val uopCSRRS= 31.U(UOPC_SZ.W) val uopCSRRC= 32.U(UOPC_SZ.W) val uopCSRRWI=33.U(UOPC_SZ.W) val uopCSRRSI=34.U(UOPC_SZ.W) val uopCSRRCI=35.U(UOPC_SZ.W) val uopJ = 36.U(UOPC_SZ.W) val uopJAL = 37.U(UOPC_SZ.W) val uopJALR = 38.U(UOPC_SZ.W) val uopAUIPC= 39.U(UOPC_SZ.W) //val uopSRET = 40.U(UOPC_SZ.W) val uopCFLSH= 41.U(UOPC_SZ.W) val uopFENCE= 42.U(UOPC_SZ.W) val uopADDIW= 43.U(UOPC_SZ.W) val uopADDW = 44.U(UOPC_SZ.W) val uopSUBW = 45.U(UOPC_SZ.W) val uopSLLIW= 46.U(UOPC_SZ.W) val uopSLLW = 47.U(UOPC_SZ.W) val uopSRAIW= 48.U(UOPC_SZ.W) val uopSRAW = 49.U(UOPC_SZ.W) val uopSRLIW= 50.U(UOPC_SZ.W) val uopSRLW = 51.U(UOPC_SZ.W) val uopMUL = 52.U(UOPC_SZ.W) val uopMULH = 53.U(UOPC_SZ.W) val uopMULHU= 54.U(UOPC_SZ.W) val uopMULHSU=55.U(UOPC_SZ.W) val uopMULW = 56.U(UOPC_SZ.W) val uopDIV = 57.U(UOPC_SZ.W) val uopDIVU = 58.U(UOPC_SZ.W) val uopREM = 59.U(UOPC_SZ.W) val uopREMU = 60.U(UOPC_SZ.W) val uopDIVW = 61.U(UOPC_SZ.W) val uopDIVUW= 62.U(UOPC_SZ.W) val uopREMW = 63.U(UOPC_SZ.W) val uopREMUW= 64.U(UOPC_SZ.W) val uopFENCEI = 65.U(UOPC_SZ.W) // = 66.U(UOPC_SZ.W) val uopAMO_AG = 67.U(UOPC_SZ.W) // AMO-address gen (use normal STD for datagen) val uopFMV_W_X = 68.U(UOPC_SZ.W) val uopFMV_D_X = 69.U(UOPC_SZ.W) val uopFMV_X_W = 70.U(UOPC_SZ.W) val uopFMV_X_D = 71.U(UOPC_SZ.W) val uopFSGNJ_S = 72.U(UOPC_SZ.W) val uopFSGNJ_D = 73.U(UOPC_SZ.W) val uopFCVT_S_D = 74.U(UOPC_SZ.W) val uopFCVT_D_S = 75.U(UOPC_SZ.W) val uopFCVT_S_X = 76.U(UOPC_SZ.W) val uopFCVT_D_X = 77.U(UOPC_SZ.W) val uopFCVT_X_S = 78.U(UOPC_SZ.W) val uopFCVT_X_D = 79.U(UOPC_SZ.W) val uopCMPR_S = 80.U(UOPC_SZ.W) val uopCMPR_D = 81.U(UOPC_SZ.W) val uopFCLASS_S = 82.U(UOPC_SZ.W) val uopFCLASS_D = 83.U(UOPC_SZ.W) val uopFMINMAX_S = 84.U(UOPC_SZ.W) val uopFMINMAX_D = 85.U(UOPC_SZ.W) // = 86.U(UOPC_SZ.W) val uopFADD_S = 87.U(UOPC_SZ.W) val uopFSUB_S = 88.U(UOPC_SZ.W) val uopFMUL_S = 89.U(UOPC_SZ.W) val uopFADD_D = 90.U(UOPC_SZ.W) val uopFSUB_D = 91.U(UOPC_SZ.W) val uopFMUL_D = 92.U(UOPC_SZ.W) val uopFMADD_S = 93.U(UOPC_SZ.W) val uopFMSUB_S = 94.U(UOPC_SZ.W) val uopFNMADD_S = 95.U(UOPC_SZ.W) val uopFNMSUB_S = 96.U(UOPC_SZ.W) val uopFMADD_D = 97.U(UOPC_SZ.W) val uopFMSUB_D = 98.U(UOPC_SZ.W) val uopFNMADD_D = 99.U(UOPC_SZ.W) val uopFNMSUB_D = 100.U(UOPC_SZ.W) val uopFDIV_S = 101.U(UOPC_SZ.W) val uopFDIV_D = 102.U(UOPC_SZ.W) val uopFSQRT_S = 103.U(UOPC_SZ.W) val uopFSQRT_D = 104.U(UOPC_SZ.W) val uopWFI = 105.U(UOPC_SZ.W) // pass uop down the CSR pipeline val uopERET = 106.U(UOPC_SZ.W) // pass uop down the CSR pipeline, also is ERET val uopSFENCE = 107.U(UOPC_SZ.W) val uopROCC = 108.U(UOPC_SZ.W) val uopMOV = 109.U(UOPC_SZ.W) // conditional mov decoded from "add rd, x0, rs2" // The Bubble Instruction (Machine generated NOP) // Insert (XOR x0,x0,x0) which is different from software compiler // generated NOPs which are (ADDI x0, x0, 0). // Reasoning for this is to let visualizers and stat-trackers differentiate // between software NOPs and machine-generated Bubbles in the pipeline. val BUBBLE = (0x4033).U(32.W) def NullMicroOp()(implicit p: Parameters): boom.v3.common.MicroOp = { val uop = Wire(new boom.v3.common.MicroOp) uop := DontCare // Overridden in the following lines uop.uopc := uopNOP // maybe not required, but helps on asserts that try to catch spurious behavior uop.bypassable := false.B uop.fp_val := false.B uop.uses_stq := false.B uop.uses_ldq := false.B uop.pdst := 0.U uop.dst_rtype := RT_X val cs = Wire(new boom.v3.common.CtrlSignals()) cs := DontCare // Overridden in the following lines cs.br_type := BR_N cs.csr_cmd := freechips.rocketchip.rocket.CSR.N cs.is_load := false.B cs.is_sta := false.B cs.is_std := false.B uop.ctrl := cs uop } } / * Mixin for RISCV constants / trait RISCVConstants { // abstract out instruction decode magic numbers val RD_MSB = 11 val RD_LSB = 7 val RS1_MSB = 19 val RS1_LSB = 15 val RS2_MSB = 24 val RS2_LSB = 20 val RS3_MSB = 31 val RS3_LSB = 27 val CSR_ADDR_MSB = 31 val CSR_ADDR_LSB = 20 val CSR_ADDR_SZ = 12 // location of the fifth bit in the shamt (for checking for illegal ops for SRAIW,etc.) val SHAMT_5_BIT = 25 val LONGEST_IMM_SZ = 20 val X0 = 0.U val RA = 1.U // return address register // memory consistency model // The C/C++ atomics MCM requires that two loads to the same address maintain program order. // The Cortex A9 does NOT enforce load/load ordering (which leads to buggy behavior). val MCM_ORDER_DEPENDENT_LOADS = true val jal_opc = (0x6f).U val jalr_opc = (0x67).U def GetUop(inst: UInt): UInt = inst(6,0) def GetRd (inst: UInt): UInt = inst(RD_MSB,RD_LSB) def GetRs1(inst: UInt): UInt = inst(RS1_MSB,RS1_LSB) def ExpandRVC(inst: UInt)(implicit p: Parameters): UInt = { val rvc_exp = Module(new RVCExpander) rvc_exp.io.in := inst Mux(rvc_exp.io.rvc, rvc_exp.io.out.bits, inst) } // Note: Accepts only EXPANDED rvc instructions def ComputeBranchTarget(pc: UInt, inst: UInt, xlen: Int)(implicit p: Parameters): UInt = { val b_imm32 = Cat(Fill(20,inst(31)), inst(7), inst(30,25), inst(11,8), 0.U(1.W)) ((pc.asSInt + b_imm32.asSInt).asSInt & (-2).S).asUInt } // Note: Accepts only EXPANDED rvc instructions def ComputeJALTarget(pc: UInt, inst: UInt, xlen: Int)(implicit p: Parameters): UInt = { val j_imm32 = Cat(Fill(12,inst(31)), inst(19,12), inst(20), inst(30,25), inst(24,21), 0.U(1.W)) ((pc.asSInt + j_imm32.asSInt).asSInt & (-2).S).asUInt } // Note: Accepts only EXPANDED rvc instructions def GetCfiType(inst: UInt)(implicit p: Parameters): UInt = { val bdecode = Module(new boom.v3.exu.BranchDecode) bdecode.io.inst := inst bdecode.io.pc := 0.U bdecode.io.out.cfi_type } } /* * Mixin for exception cause constants / trait ExcCauseConstants { // a memory disambigious misspeculation occurred val MINI_EXCEPTION_MEM_ORDERING = 16.U val MINI_EXCEPTION_CSR_REPLAY = 17.U require (!freechips.rocketchip.rocket.Causes.all.contains(16)) require (!freechips.rocketchip.rocket.Causes.all.contains(17)) } File issue-slot.scala: //*************************************************************************** // Copyright (c) 2015 - 2018, The Regents of the University of California (Regents). // All Rights Reserved. See LICENSE and LICENSE.SiFive for license details. //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ // RISCV Processor Issue Slot Logic //-------------------------------------------------------------------------- //------------------------------------------------------------------------------ // // Note: stores (and AMOs) are "broken down" into 2 uops, but stored within a single issue-slot. // TODO XXX make a separate issueSlot for MemoryIssueSlots, and only they break apart stores. // TODO Disable ldspec for FP queue. package boom.v3.exu import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.Parameters import boom.v3.common._ import boom.v3.util._ import FUConstants._ / * IO bundle to interact with Issue slot * * @param numWakeupPorts number of wakeup ports for the slot / class IssueSlotIO(val numWakeupPorts: Int)(implicit p: Parameters) extends BoomBundle { val valid = Output(Bool()) val will_be_valid = Output(Bool()) // TODO code review, do we need this signal so explicitely? val request = Output(Bool()) val request_hp = Output(Bool()) val grant = Input(Bool()) val brupdate = Input(new BrUpdateInfo()) val kill = Input(Bool()) // pipeline flush val clear = Input(Bool()) // entry being moved elsewhere (not mutually exclusive with grant) val ldspec_miss = Input(Bool()) // Previous cycle's speculative load wakeup was mispredicted. val wakeup_ports = Flipped(Vec(numWakeupPorts, Valid(new IqWakeup(maxPregSz)))) val pred_wakeup_port = Flipped(Valid(UInt(log2Ceil(ftqSz).W))) val spec_ld_wakeup = Flipped(Vec(memWidth, Valid(UInt(width=maxPregSz.W)))) val in_uop = Flipped(Valid(new MicroOp())) // if valid, this WILL overwrite an entry! val out_uop = Output(new MicroOp()) // the updated slot uop; will be shifted upwards in a collasping queue. val uop = Output(new MicroOp()) // the current Slot's uop. Sent down the pipeline when issued. val debug = { val result = new Bundle { val p1 = Bool() val p2 = Bool() val p3 = Bool() val ppred = Bool() val state = UInt(width=2.W) } Output(result) } } /* * Single issue slot. Holds a uop within the issue queue * * @param numWakeupPorts number of wakeup ports / class IssueSlot(val numWakeupPorts: Int)(implicit p: Parameters) extends BoomModule with IssueUnitConstants { val io = IO(new IssueSlotIO(numWakeupPorts)) // slot invalid? // slot is valid, holding 1 uop // slot is valid, holds 2 uops (like a store) def is_invalid = state === s_invalid def is_valid = state =/= s_invalid val next_state = Wire(UInt()) // the next state of this slot (which might then get moved to a new slot) val next_uopc = Wire(UInt()) // the next uopc of this slot (which might then get moved to a new slot) val next_lrs1_rtype = Wire(UInt()) // the next reg type of this slot (which might then get moved to a new slot) val next_lrs2_rtype = Wire(UInt()) // the next reg type of this slot (which might then get moved to a new slot) val state = RegInit(s_invalid) val p1 = RegInit(false.B) val p2 = RegInit(false.B) val p3 = RegInit(false.B) val ppred = RegInit(false.B) // Poison if woken up by speculative load. // Poison lasts 1 cycle (as ldMiss will come on the next cycle). // SO if poisoned is true, set it to false! val p1_poisoned = RegInit(false.B) val p2_poisoned = RegInit(false.B) p1_poisoned := false.B p2_poisoned := false.B val next_p1_poisoned = Mux(io.in_uop.valid, io.in_uop.bits.iw_p1_poisoned, p1_poisoned) val next_p2_poisoned = Mux(io.in_uop.valid, io.in_uop.bits.iw_p2_poisoned, p2_poisoned) val slot_uop = RegInit(NullMicroOp) val next_uop = Mux(io.in_uop.valid, io.in_uop.bits, slot_uop) //----------------------------------------------------------------------------- // next slot state computation // compute the next state for THIS entry slot (in a collasping queue, the // current uop may get moved elsewhere, and a new uop can enter when (io.kill) { state := s_invalid } .elsewhen (io.in_uop.valid) { state := io.in_uop.bits.iw_state } .elsewhen (io.clear) { state := s_invalid } .otherwise { state := next_state } //----------------------------------------------------------------------------- // "update" state // compute the next state for the micro-op in this slot. This micro-op may // be moved elsewhere, so the "next_state" travels with it. // defaults next_state := state next_uopc := slot_uop.uopc next_lrs1_rtype := slot_uop.lrs1_rtype next_lrs2_rtype := slot_uop.lrs2_rtype when (io.kill) { next_state := s_invalid } .elsewhen ((io.grant && (state === s_valid_1)) \|\| (io.grant && (state === s_valid_2) && p1 && p2 && ppred)) { // try to issue this uop. when (!(io.ldspec_miss && (p1_poisoned \|\| p2_poisoned))) { next_state := s_invalid } } .elsewhen (io.grant && (state === s_valid_2)) { when (!(io.ldspec_miss && (p1_poisoned \|\| p2_poisoned))) { next_state := s_valid_1 when (p1) { slot_uop.uopc := uopSTD next_uopc := uopSTD slot_uop.lrs1_rtype := RT_X next_lrs1_rtype := RT_X } .otherwise { slot_uop.lrs2_rtype := RT_X next_lrs2_rtype := RT_X } } } when (io.in_uop.valid) { slot_uop := io.in_uop.bits assert (is_invalid \|\| io.clear \|\| io.kill, "trying to overwrite a valid issue slot.") } // Wakeup Compare Logic // these signals are the "next_p" for the current slot's micro-op. // they are important for shifting the current slot_uop up to an other entry. val next_p1 = WireInit(p1) val next_p2 = WireInit(p2) val next_p3 = WireInit(p3) val next_ppred = WireInit(ppred) when (io.in_uop.valid) { p1 := !(io.in_uop.bits.prs1_busy) p2 := !(io.in_uop.bits.prs2_busy) p3 := !(io.in_uop.bits.prs3_busy) ppred := !(io.in_uop.bits.ppred_busy) } when (io.ldspec_miss && next_p1_poisoned) { assert(next_uop.prs1 =/= 0.U, "Poison bit can't be set for prs1=x0!") p1 := false.B } when (io.ldspec_miss && next_p2_poisoned) { assert(next_uop.prs2 =/= 0.U, "Poison bit can't be set for prs2=x0!") p2 := false.B } for (i <- 0 until numWakeupPorts) { when (io.wakeup_ports(i).valid && (io.wakeup_ports(i).bits.pdst === next_uop.prs1)) { p1 := true.B } when (io.wakeup_ports(i).valid && (io.wakeup_ports(i).bits.pdst === next_uop.prs2)) { p2 := true.B } when (io.wakeup_ports(i).valid && (io.wakeup_ports(i).bits.pdst === next_uop.prs3)) { p3 := true.B } } when (io.pred_wakeup_port.valid && io.pred_wakeup_port.bits === next_uop.ppred) { ppred := true.B } for (w <- 0 until memWidth) { assert (!(io.spec_ld_wakeup(w).valid && io.spec_ld_wakeup(w).bits === 0.U), "Loads to x0 should never speculatively wakeup other instructions") } // TODO disable if FP IQ. for (w <- 0 until memWidth) { when (io.spec_ld_wakeup(w).valid && io.spec_ld_wakeup(w).bits === next_uop.prs1 && next_uop.lrs1_rtype === RT_FIX) { p1 := true.B p1_poisoned := true.B assert (!next_p1_poisoned) } when (io.spec_ld_wakeup(w).valid && io.spec_ld_wakeup(w).bits === next_uop.prs2 && next_uop.lrs2_rtype === RT_FIX) { p2 := true.B p2_poisoned := true.B assert (!next_p2_poisoned) } } // Handle branch misspeculations val next_br_mask = GetNewBrMask(io.brupdate, slot_uop) // was this micro-op killed by a branch? if yes, we can't let it be valid if // we compact it into an other entry when (IsKilledByBranch(io.brupdate, slot_uop)) { next_state := s_invalid } when (!io.in_uop.valid) { slot_uop.br_mask := next_br_mask } //------------------------------------------------------------- // Request Logic io.request := is_valid && p1 && p2 && p3 && ppred && !io.kill val high_priority = slot_uop.is_br \|\| slot_uop.is_jal \|\| slot_uop.is_jalr io.request_hp := io.request && high_priority when (state === s_valid_1) { io.request := p1 && p2 && p3 && ppred && !io.kill } .elsewhen (state === s_valid_2) { io.request := (p1 \|\| p2) && ppred && !io.kill } .otherwise { io.request := false.B } //assign outputs io.valid := is_valid io.uop := slot_uop io.uop.iw_p1_poisoned := p1_poisoned io.uop.iw_p2_poisoned := p2_poisoned // micro-op will vacate due to grant. val may_vacate = io.grant && ((state === s_valid_1) \|\| (state === s_valid_2) && p1 && p2 && ppred) val squash_grant = io.ldspec_miss && (p1_poisoned \|\| p2_poisoned) io.will_be_valid := is_valid && !(may_vacate && !squash_grant) io.out_uop := slot_uop io.out_uop.iw_state := next_state io.out_uop.uopc := next_uopc io.out_uop.lrs1_rtype := next_lrs1_rtype io.out_uop.lrs2_rtype := next_lrs2_rtype io.out_uop.br_mask := next_br_mask io.out_uop.prs1_busy := !p1 io.out_uop.prs2_busy := !p2 io.out_uop.prs3_busy := !p3 io.out_uop.ppred_busy := !ppred io.out_uop.iw_p1_poisoned := p1_poisoned io.out_uop.iw_p2_poisoned := p2_poisoned when (state === s_valid_2) { when (p1 && p2 && ppred) { ; // send out the entire instruction as one uop } .elsewhen (p1 && ppred) { io.uop.uopc := slot_uop.uopc io.uop.lrs2_rtype := RT_X } .elsewhen (p2 && ppred) { io.uop.uopc := uopSTD io.uop.lrs1_rtype := RT_X } } // debug outputs io.debug.p1 := p1 io.debug.p2 := p2 io.debug.p3 := p3 io.debug.ppred := ppred io.debug.state := state }	module IssueSlot_36( // @[issue-slot.scala:69:7] input clock, // @[issue-slot.scala:69:7] input reset, // @[issue-slot.scala:69:7] output io_valid, // @[issue-slot.scala:73:14] output io_will_be_valid, // @[issue-slot.scala:73:14] output io_request, // @[issue-slot.scala:73:14] output io_request_hp, // @[issue-slot.scala:73:14] input io_grant, // @[issue-slot.scala:73:14] input [7:0] io_brupdate_b1_resolve_mask, // @[issue-slot.scala:73:14] input [7:0] io_brupdate_b1_mispredict_mask, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_uopc, // @[issue-slot.scala:73:14] input [31:0] io_brupdate_b2_uop_inst, // @[issue-slot.scala:73:14] input [31:0] io_brupdate_b2_uop_debug_inst, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_rvc, // @[issue-slot.scala:73:14] input [39:0] io_brupdate_b2_uop_debug_pc, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_uop_iq_type, // @[issue-slot.scala:73:14] input [9:0] io_brupdate_b2_uop_fu_code, // @[issue-slot.scala:73:14] input [3:0] io_brupdate_b2_uop_ctrl_br_type, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_ctrl_op1_sel, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_uop_ctrl_op2_sel, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_uop_ctrl_imm_sel, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_ctrl_op_fcn, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ctrl_fcn_dw, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_uop_ctrl_csr_cmd, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ctrl_is_load, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ctrl_is_sta, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ctrl_is_std, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_iw_state, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_iw_p1_poisoned, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_iw_p2_poisoned, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_br, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_jalr, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_jal, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_sfb, // @[issue-slot.scala:73:14] input [7:0] io_brupdate_b2_uop_br_mask, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_uop_br_tag, // @[issue-slot.scala:73:14] input [3:0] io_brupdate_b2_uop_ftq_idx, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_edge_inst, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_pc_lob, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_taken, // @[issue-slot.scala:73:14] input [19:0] io_brupdate_b2_uop_imm_packed, // @[issue-slot.scala:73:14] input [11:0] io_brupdate_b2_uop_csr_addr, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_rob_idx, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_uop_ldq_idx, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_uop_stq_idx, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_rxq_idx, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_pdst, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_prs1, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_prs2, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_prs3, // @[issue-slot.scala:73:14] input [3:0] io_brupdate_b2_uop_ppred, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_prs1_busy, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_prs2_busy, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_prs3_busy, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ppred_busy, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_stale_pdst, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_exception, // @[issue-slot.scala:73:14] input [63:0] io_brupdate_b2_uop_exc_cause, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_bypassable, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_mem_cmd, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_mem_size, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_mem_signed, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_fence, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_fencei, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_amo, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_uses_ldq, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_uses_stq, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_sys_pc2epc, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_unique, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_flush_on_commit, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ldst_is_rs1, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_ldst, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_lrs1, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_lrs2, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_lrs3, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ldst_val, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_dst_rtype, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_lrs1_rtype, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_lrs2_rtype, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_frs3_en, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_fp_val, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_fp_single, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_xcpt_pf_if, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_xcpt_ae_if, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_xcpt_ma_if, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_bp_debug_if, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_bp_xcpt_if, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_debug_fsrc, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_debug_tsrc, // @[issue-slot.scala:73:14] input io_brupdate_b2_valid, // @[issue-slot.scala:73:14] input io_brupdate_b2_mispredict, // @[issue-slot.scala:73:14] input io_brupdate_b2_taken, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_cfi_type, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_pc_sel, // @[issue-slot.scala:73:14] input [39:0] io_brupdate_b2_jalr_target, // @[issue-slot.scala:73:14] input [20:0] io_brupdate_b2_target_offset, // @[issue-slot.scala:73:14] input io_kill, // @[issue-slot.scala:73:14] input io_clear, // @[issue-slot.scala:73:14] input io_ldspec_miss, // @[issue-slot.scala:73:14] input io_wakeup_ports_0_valid, // @[issue-slot.scala:73:14] input [5:0] io_wakeup_ports_0_bits_pdst, // @[issue-slot.scala:73:14] input io_wakeup_ports_0_bits_poisoned, // @[issue-slot.scala:73:14] input io_wakeup_ports_1_valid, // @[issue-slot.scala:73:14] input [5:0] io_wakeup_ports_1_bits_pdst, // @[issue-slot.scala:73:14] input io_wakeup_ports_1_bits_poisoned, // @[issue-slot.scala:73:14] input io_wakeup_ports_2_valid, // @[issue-slot.scala:73:14] input [5:0] io_wakeup_ports_2_bits_pdst, // @[issue-slot.scala:73:14] input io_wakeup_ports_2_bits_poisoned, // @[issue-slot.scala:73:14] input io_spec_ld_wakeup_0_valid, // @[issue-slot.scala:73:14] input [5:0] io_spec_ld_wakeup_0_bits, // @[issue-slot.scala:73:14] input io_in_uop_valid, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_uopc, // @[issue-slot.scala:73:14] input [31:0] io_in_uop_bits_inst, // @[issue-slot.scala:73:14] input [31:0] io_in_uop_bits_debug_inst, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_rvc, // @[issue-slot.scala:73:14] input [39:0] io_in_uop_bits_debug_pc, // @[issue-slot.scala:73:14] input [2:0] io_in_uop_bits_iq_type, // @[issue-slot.scala:73:14] input [9:0] io_in_uop_bits_fu_code, // @[issue-slot.scala:73:14] input [3:0] io_in_uop_bits_ctrl_br_type, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_ctrl_op1_sel, // @[issue-slot.scala:73:14] input [2:0] io_in_uop_bits_ctrl_op2_sel, // @[issue-slot.scala:73:14] input [2:0] io_in_uop_bits_ctrl_imm_sel, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_ctrl_op_fcn, // @[issue-slot.scala:73:14] input io_in_uop_bits_ctrl_fcn_dw, // @[issue-slot.scala:73:14] input [2:0] io_in_uop_bits_ctrl_csr_cmd, // @[issue-slot.scala:73:14] input io_in_uop_bits_ctrl_is_load, // @[issue-slot.scala:73:14] input io_in_uop_bits_ctrl_is_sta, // @[issue-slot.scala:73:14] input io_in_uop_bits_ctrl_is_std, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_iw_state, // @[issue-slot.scala:73:14] input io_in_uop_bits_iw_p1_poisoned, // @[issue-slot.scala:73:14] input io_in_uop_bits_iw_p2_poisoned, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_br, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_jalr, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_jal, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_sfb, // @[issue-slot.scala:73:14] input [7:0] io_in_uop_bits_br_mask, // @[issue-slot.scala:73:14] input [2:0] io_in_uop_bits_br_tag, // @[issue-slot.scala:73:14] input [3:0] io_in_uop_bits_ftq_idx, // @[issue-slot.scala:73:14] input io_in_uop_bits_edge_inst, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_pc_lob, // @[issue-slot.scala:73:14] input io_in_uop_bits_taken, // @[issue-slot.scala:73:14] input [19:0] io_in_uop_bits_imm_packed, // @[issue-slot.scala:73:14] input [11:0] io_in_uop_bits_csr_addr, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_rob_idx, // @[issue-slot.scala:73:14] input [2:0] io_in_uop_bits_ldq_idx, // @[issue-slot.scala:73:14] input [2:0] io_in_uop_bits_stq_idx, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_rxq_idx, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_pdst, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_prs1, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_prs2, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_prs3, // @[issue-slot.scala:73:14] input [3:0] io_in_uop_bits_ppred, // @[issue-slot.scala:73:14] input io_in_uop_bits_prs1_busy, // @[issue-slot.scala:73:14] input io_in_uop_bits_prs2_busy, // @[issue-slot.scala:73:14] input io_in_uop_bits_prs3_busy, // @[issue-slot.scala:73:14] input io_in_uop_bits_ppred_busy, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_stale_pdst, // @[issue-slot.scala:73:14] input io_in_uop_bits_exception, // @[issue-slot.scala:73:14] input [63:0] io_in_uop_bits_exc_cause, // @[issue-slot.scala:73:14] input io_in_uop_bits_bypassable, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_mem_cmd, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_mem_size, // @[issue-slot.scala:73:14] input io_in_uop_bits_mem_signed, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_fence, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_fencei, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_amo, // @[issue-slot.scala:73:14] input io_in_uop_bits_uses_ldq, // @[issue-slot.scala:73:14] input io_in_uop_bits_uses_stq, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_sys_pc2epc, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_unique, // @[issue-slot.scala:73:14] input io_in_uop_bits_flush_on_commit, // @[issue-slot.scala:73:14] input io_in_uop_bits_ldst_is_rs1, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_ldst, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_lrs1, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_lrs2, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_lrs3, // @[issue-slot.scala:73:14] input io_in_uop_bits_ldst_val, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_dst_rtype, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_lrs1_rtype, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_lrs2_rtype, // @[issue-slot.scala:73:14] input io_in_uop_bits_frs3_en, // @[issue-slot.scala:73:14] input io_in_uop_bits_fp_val, // @[issue-slot.scala:73:14] input io_in_uop_bits_fp_single, // @[issue-slot.scala:73:14] input io_in_uop_bits_xcpt_pf_if, // @[issue-slot.scala:73:14] input io_in_uop_bits_xcpt_ae_if, // @[issue-slot.scala:73:14] input io_in_uop_bits_xcpt_ma_if, // @[issue-slot.scala:73:14] input io_in_uop_bits_bp_debug_if, // @[issue-slot.scala:73:14] input io_in_uop_bits_bp_xcpt_if, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_debug_fsrc, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_debug_tsrc, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_uopc, // @[issue-slot.scala:73:14] output [31:0] io_out_uop_inst, // @[issue-slot.scala:73:14] output [31:0] io_out_uop_debug_inst, // @[issue-slot.scala:73:14] output io_out_uop_is_rvc, // @[issue-slot.scala:73:14] output [39:0] io_out_uop_debug_pc, // @[issue-slot.scala:73:14] output [2:0] io_out_uop_iq_type, // @[issue-slot.scala:73:14] output [9:0] io_out_uop_fu_code, // @[issue-slot.scala:73:14] output [3:0] io_out_uop_ctrl_br_type, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_ctrl_op1_sel, // @[issue-slot.scala:73:14] output [2:0] io_out_uop_ctrl_op2_sel, // @[issue-slot.scala:73:14] output [2:0] io_out_uop_ctrl_imm_sel, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_ctrl_op_fcn, // @[issue-slot.scala:73:14] output io_out_uop_ctrl_fcn_dw, // @[issue-slot.scala:73:14] output [2:0] io_out_uop_ctrl_csr_cmd, // @[issue-slot.scala:73:14] output io_out_uop_ctrl_is_load, // @[issue-slot.scala:73:14] output io_out_uop_ctrl_is_sta, // @[issue-slot.scala:73:14] output io_out_uop_ctrl_is_std, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_iw_state, // @[issue-slot.scala:73:14] output io_out_uop_iw_p1_poisoned, // @[issue-slot.scala:73:14] output io_out_uop_iw_p2_poisoned, // @[issue-slot.scala:73:14] output io_out_uop_is_br, // @[issue-slot.scala:73:14] output io_out_uop_is_jalr, // @[issue-slot.scala:73:14] output io_out_uop_is_jal, // @[issue-slot.scala:73:14] output io_out_uop_is_sfb, // @[issue-slot.scala:73:14] output [7:0] io_out_uop_br_mask, // @[issue-slot.scala:73:14] output [2:0] io_out_uop_br_tag, // @[issue-slot.scala:73:14] output [3:0] io_out_uop_ftq_idx, // @[issue-slot.scala:73:14] output io_out_uop_edge_inst, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_pc_lob, // @[issue-slot.scala:73:14] output io_out_uop_taken, // @[issue-slot.scala:73:14] output [19:0] io_out_uop_imm_packed, // @[issue-slot.scala:73:14] output [11:0] io_out_uop_csr_addr, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_rob_idx, // @[issue-slot.scala:73:14] output [2:0] io_out_uop_ldq_idx, // @[issue-slot.scala:73:14] output [2:0] io_out_uop_stq_idx, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_rxq_idx, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_pdst, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_prs1, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_prs2, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_prs3, // @[issue-slot.scala:73:14] output [3:0] io_out_uop_ppred, // @[issue-slot.scala:73:14] output io_out_uop_prs1_busy, // @[issue-slot.scala:73:14] output io_out_uop_prs2_busy, // @[issue-slot.scala:73:14] output io_out_uop_prs3_busy, // @[issue-slot.scala:73:14] output io_out_uop_ppred_busy, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_stale_pdst, // @[issue-slot.scala:73:14] output io_out_uop_exception, // @[issue-slot.scala:73:14] output [63:0] io_out_uop_exc_cause, // @[issue-slot.scala:73:14] output io_out_uop_bypassable, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_mem_cmd, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_mem_size, // @[issue-slot.scala:73:14] output io_out_uop_mem_signed, // @[issue-slot.scala:73:14] output io_out_uop_is_fence, // @[issue-slot.scala:73:14] output io_out_uop_is_fencei, // @[issue-slot.scala:73:14] output io_out_uop_is_amo, // @[issue-slot.scala:73:14] output io_out_uop_uses_ldq, // @[issue-slot.scala:73:14] output io_out_uop_uses_stq, // @[issue-slot.scala:73:14] output io_out_uop_is_sys_pc2epc, // @[issue-slot.scala:73:14] output io_out_uop_is_unique, // @[issue-slot.scala:73:14] output io_out_uop_flush_on_commit, // @[issue-slot.scala:73:14] output io_out_uop_ldst_is_rs1, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_ldst, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_lrs1, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_lrs2, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_lrs3, // @[issue-slot.scala:73:14] output io_out_uop_ldst_val, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_dst_rtype, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_lrs1_rtype, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_lrs2_rtype, // @[issue-slot.scala:73:14] output io_out_uop_frs3_en, // @[issue-slot.scala:73:14] output io_out_uop_fp_val, // @[issue-slot.scala:73:14] output io_out_uop_fp_single, // @[issue-slot.scala:73:14] output io_out_uop_xcpt_pf_if, // @[issue-slot.scala:73:14] output io_out_uop_xcpt_ae_if, // @[issue-slot.scala:73:14] output io_out_uop_xcpt_ma_if, // @[issue-slot.scala:73:14] output io_out_uop_bp_debug_if, // @[issue-slot.scala:73:14] output io_out_uop_bp_xcpt_if, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_debug_fsrc, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_debug_tsrc, // @[issue-slot.scala:73:14] output [6:0] io_uop_uopc, // @[issue-slot.scala:73:14] output [31:0] io_uop_inst, // @[issue-slot.scala:73:14] output [31:0] io_uop_debug_inst, // @[issue-slot.scala:73:14] output io_uop_is_rvc, // @[issue-slot.scala:73:14] output [39:0] io_uop_debug_pc, // @[issue-slot.scala:73:14] output [2:0] io_uop_iq_type, // @[issue-slot.scala:73:14] output [9:0] io_uop_fu_code, // @[issue-slot.scala:73:14] output [3:0] io_uop_ctrl_br_type, // @[issue-slot.scala:73:14] output [1:0] io_uop_ctrl_op1_sel, // @[issue-slot.scala:73:14] output [2:0] io_uop_ctrl_op2_sel, // @[issue-slot.scala:73:14] output [2:0] io_uop_ctrl_imm_sel, // @[issue-slot.scala:73:14] output [4:0] io_uop_ctrl_op_fcn, // @[issue-slot.scala:73:14] output io_uop_ctrl_fcn_dw, // @[issue-slot.scala:73:14] output [2:0] io_uop_ctrl_csr_cmd, // @[issue-slot.scala:73:14] output io_uop_ctrl_is_load, // @[issue-slot.scala:73:14] output io_uop_ctrl_is_sta, // @[issue-slot.scala:73:14] output io_uop_ctrl_is_std, // @[issue-slot.scala:73:14] output [1:0] io_uop_iw_state, // @[issue-slot.scala:73:14] output io_uop_iw_p1_poisoned, // @[issue-slot.scala:73:14] output io_uop_iw_p2_poisoned, // @[issue-slot.scala:73:14] output io_uop_is_br, // @[issue-slot.scala:73:14] output io_uop_is_jalr, // @[issue-slot.scala:73:14] output io_uop_is_jal, // @[issue-slot.scala:73:14] output io_uop_is_sfb, // @[issue-slot.scala:73:14] output [7:0] io_uop_br_mask, // @[issue-slot.scala:73:14] output [2:0] io_uop_br_tag, // @[issue-slot.scala:73:14] output [3:0] io_uop_ftq_idx, // @[issue-slot.scala:73:14] output io_uop_edge_inst, // @[issue-slot.scala:73:14] output [5:0] io_uop_pc_lob, // @[issue-slot.scala:73:14] output io_uop_taken, // @[issue-slot.scala:73:14] output [19:0] io_uop_imm_packed, // @[issue-slot.scala:73:14] output [11:0] io_uop_csr_addr, // @[issue-slot.scala:73:14] output [4:0] io_uop_rob_idx, // @[issue-slot.scala:73:14] output [2:0] io_uop_ldq_idx, // @[issue-slot.scala:73:14] output [2:0] io_uop_stq_idx, // @[issue-slot.scala:73:14] output [1:0] io_uop_rxq_idx, // @[issue-slot.scala:73:14] output [5:0] io_uop_pdst, // @[issue-slot.scala:73:14] output [5:0] io_uop_prs1, // @[issue-slot.scala:73:14] output [5:0] io_uop_prs2, // @[issue-slot.scala:73:14] output [5:0] io_uop_prs3, // @[issue-slot.scala:73:14] output [3:0] io_uop_ppred, // @[issue-slot.scala:73:14] output io_uop_prs1_busy, // @[issue-slot.scala:73:14] output io_uop_prs2_busy, // @[issue-slot.scala:73:14] output io_uop_prs3_busy, // @[issue-slot.scala:73:14] output io_uop_ppred_busy, // @[issue-slot.scala:73:14] output [5:0] io_uop_stale_pdst, // @[issue-slot.scala:73:14] output io_uop_exception, // @[issue-slot.scala:73:14] output [63:0] io_uop_exc_cause, // @[issue-slot.scala:73:14] output io_uop_bypassable, // @[issue-slot.scala:73:14] output [4:0] io_uop_mem_cmd, // @[issue-slot.scala:73:14] output [1:0] io_uop_mem_size, // @[issue-slot.scala:73:14] output io_uop_mem_signed, // @[issue-slot.scala:73:14] output io_uop_is_fence, // @[issue-slot.scala:73:14] output io_uop_is_fencei, // @[issue-slot.scala:73:14] output io_uop_is_amo, // @[issue-slot.scala:73:14] output io_uop_uses_ldq, // @[issue-slot.scala:73:14] output io_uop_uses_stq, // @[issue-slot.scala:73:14] output io_uop_is_sys_pc2epc, // @[issue-slot.scala:73:14] output io_uop_is_unique, // @[issue-slot.scala:73:14] output io_uop_flush_on_commit, // @[issue-slot.scala:73:14] output io_uop_ldst_is_rs1, // @[issue-slot.scala:73:14] output [5:0] io_uop_ldst, // @[issue-slot.scala:73:14] output [5:0] io_uop_lrs1, // @[issue-slot.scala:73:14] output [5:0] io_uop_lrs2, // @[issue-slot.scala:73:14] output [5:0] io_uop_lrs3, // @[issue-slot.scala:73:14] output io_uop_ldst_val, // @[issue-slot.scala:73:14] output [1:0] io_uop_dst_rtype, // @[issue-slot.scala:73:14] output [1:0] io_uop_lrs1_rtype, // @[issue-slot.scala:73:14] output [1:0] io_uop_lrs2_rtype, // @[issue-slot.scala:73:14] output io_uop_frs3_en, // @[issue-slot.scala:73:14] output io_uop_fp_val, // @[issue-slot.scala:73:14] output io_uop_fp_single, // @[issue-slot.scala:73:14] output io_uop_xcpt_pf_if, // @[issue-slot.scala:73:14] output io_uop_xcpt_ae_if, // @[issue-slot.scala:73:14] output io_uop_xcpt_ma_if, // @[issue-slot.scala:73:14] output io_uop_bp_debug_if, // @[issue-slot.scala:73:14] output io_uop_bp_xcpt_if, // @[issue-slot.scala:73:14] output [1:0] io_uop_debug_fsrc, // @[issue-slot.scala:73:14] output [1:0] io_uop_debug_tsrc, // @[issue-slot.scala:73:14] output io_debug_p1, // @[issue-slot.scala:73:14] output io_debug_p2, // @[issue-slot.scala:73:14] output io_debug_p3, // @[issue-slot.scala:73:14] output io_debug_ppred, // @[issue-slot.scala:73:14] output [1:0] io_debug_state // @[issue-slot.scala:73:14] ); wire io_grant_0 = io_grant; // @[issue-slot.scala:69:7] wire [7:0] io_brupdate_b1_resolve_mask_0 = io_brupdate_b1_resolve_mask; // @[issue-slot.scala:69:7] wire [7:0] io_brupdate_b1_mispredict_mask_0 = io_brupdate_b1_mispredict_mask; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_uopc_0 = io_brupdate_b2_uop_uopc; // @[issue-slot.scala:69:7] wire [31:0] io_brupdate_b2_uop_inst_0 = io_brupdate_b2_uop_inst; // @[issue-slot.scala:69:7] wire [31:0] io_brupdate_b2_uop_debug_inst_0 = io_brupdate_b2_uop_debug_inst; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_rvc_0 = io_brupdate_b2_uop_is_rvc; // @[issue-slot.scala:69:7] wire [39:0] io_brupdate_b2_uop_debug_pc_0 = io_brupdate_b2_uop_debug_pc; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_uop_iq_type_0 = io_brupdate_b2_uop_iq_type; // @[issue-slot.scala:69:7] wire [9:0] io_brupdate_b2_uop_fu_code_0 = io_brupdate_b2_uop_fu_code; // @[issue-slot.scala:69:7] wire [3:0] io_brupdate_b2_uop_ctrl_br_type_0 = io_brupdate_b2_uop_ctrl_br_type; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_ctrl_op1_sel_0 = io_brupdate_b2_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_uop_ctrl_op2_sel_0 = io_brupdate_b2_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_uop_ctrl_imm_sel_0 = io_brupdate_b2_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_ctrl_op_fcn_0 = io_brupdate_b2_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ctrl_fcn_dw_0 = io_brupdate_b2_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_uop_ctrl_csr_cmd_0 = io_brupdate_b2_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ctrl_is_load_0 = io_brupdate_b2_uop_ctrl_is_load; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ctrl_is_sta_0 = io_brupdate_b2_uop_ctrl_is_sta; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ctrl_is_std_0 = io_brupdate_b2_uop_ctrl_is_std; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_iw_state_0 = io_brupdate_b2_uop_iw_state; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_iw_p1_poisoned_0 = io_brupdate_b2_uop_iw_p1_poisoned; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_iw_p2_poisoned_0 = io_brupdate_b2_uop_iw_p2_poisoned; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_br_0 = io_brupdate_b2_uop_is_br; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_jalr_0 = io_brupdate_b2_uop_is_jalr; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_jal_0 = io_brupdate_b2_uop_is_jal; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_sfb_0 = io_brupdate_b2_uop_is_sfb; // @[issue-slot.scala:69:7] wire [7:0] io_brupdate_b2_uop_br_mask_0 = io_brupdate_b2_uop_br_mask; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_uop_br_tag_0 = io_brupdate_b2_uop_br_tag; // @[issue-slot.scala:69:7] wire [3:0] io_brupdate_b2_uop_ftq_idx_0 = io_brupdate_b2_uop_ftq_idx; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_edge_inst_0 = io_brupdate_b2_uop_edge_inst; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_pc_lob_0 = io_brupdate_b2_uop_pc_lob; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_taken_0 = io_brupdate_b2_uop_taken; // @[issue-slot.scala:69:7] wire [19:0] io_brupdate_b2_uop_imm_packed_0 = io_brupdate_b2_uop_imm_packed; // @[issue-slot.scala:69:7] wire [11:0] io_brupdate_b2_uop_csr_addr_0 = io_brupdate_b2_uop_csr_addr; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_rob_idx_0 = io_brupdate_b2_uop_rob_idx; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_uop_ldq_idx_0 = io_brupdate_b2_uop_ldq_idx; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_uop_stq_idx_0 = io_brupdate_b2_uop_stq_idx; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_rxq_idx_0 = io_brupdate_b2_uop_rxq_idx; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_pdst_0 = io_brupdate_b2_uop_pdst; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_prs1_0 = io_brupdate_b2_uop_prs1; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_prs2_0 = io_brupdate_b2_uop_prs2; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_prs3_0 = io_brupdate_b2_uop_prs3; // @[issue-slot.scala:69:7] wire [3:0] io_brupdate_b2_uop_ppred_0 = io_brupdate_b2_uop_ppred; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_prs1_busy_0 = io_brupdate_b2_uop_prs1_busy; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_prs2_busy_0 = io_brupdate_b2_uop_prs2_busy; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_prs3_busy_0 = io_brupdate_b2_uop_prs3_busy; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ppred_busy_0 = io_brupdate_b2_uop_ppred_busy; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_stale_pdst_0 = io_brupdate_b2_uop_stale_pdst; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_exception_0 = io_brupdate_b2_uop_exception; // @[issue-slot.scala:69:7] wire [63:0] io_brupdate_b2_uop_exc_cause_0 = io_brupdate_b2_uop_exc_cause; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_bypassable_0 = io_brupdate_b2_uop_bypassable; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_mem_cmd_0 = io_brupdate_b2_uop_mem_cmd; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_mem_size_0 = io_brupdate_b2_uop_mem_size; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_mem_signed_0 = io_brupdate_b2_uop_mem_signed; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_fence_0 = io_brupdate_b2_uop_is_fence; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_fencei_0 = io_brupdate_b2_uop_is_fencei; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_amo_0 = io_brupdate_b2_uop_is_amo; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_uses_ldq_0 = io_brupdate_b2_uop_uses_ldq; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_uses_stq_0 = io_brupdate_b2_uop_uses_stq; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_sys_pc2epc_0 = io_brupdate_b2_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_unique_0 = io_brupdate_b2_uop_is_unique; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_flush_on_commit_0 = io_brupdate_b2_uop_flush_on_commit; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ldst_is_rs1_0 = io_brupdate_b2_uop_ldst_is_rs1; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_ldst_0 = io_brupdate_b2_uop_ldst; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_lrs1_0 = io_brupdate_b2_uop_lrs1; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_lrs2_0 = io_brupdate_b2_uop_lrs2; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_lrs3_0 = io_brupdate_b2_uop_lrs3; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ldst_val_0 = io_brupdate_b2_uop_ldst_val; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_dst_rtype_0 = io_brupdate_b2_uop_dst_rtype; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_lrs1_rtype_0 = io_brupdate_b2_uop_lrs1_rtype; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_lrs2_rtype_0 = io_brupdate_b2_uop_lrs2_rtype; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_frs3_en_0 = io_brupdate_b2_uop_frs3_en; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_fp_val_0 = io_brupdate_b2_uop_fp_val; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_fp_single_0 = io_brupdate_b2_uop_fp_single; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_xcpt_pf_if_0 = io_brupdate_b2_uop_xcpt_pf_if; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_xcpt_ae_if_0 = io_brupdate_b2_uop_xcpt_ae_if; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_xcpt_ma_if_0 = io_brupdate_b2_uop_xcpt_ma_if; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_bp_debug_if_0 = io_brupdate_b2_uop_bp_debug_if; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_bp_xcpt_if_0 = io_brupdate_b2_uop_bp_xcpt_if; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_debug_fsrc_0 = io_brupdate_b2_uop_debug_fsrc; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_debug_tsrc_0 = io_brupdate_b2_uop_debug_tsrc; // @[issue-slot.scala:69:7] wire io_brupdate_b2_valid_0 = io_brupdate_b2_valid; // @[issue-slot.scala:69:7] wire io_brupdate_b2_mispredict_0 = io_brupdate_b2_mispredict; // @[issue-slot.scala:69:7] wire io_brupdate_b2_taken_0 = io_brupdate_b2_taken; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_cfi_type_0 = io_brupdate_b2_cfi_type; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_pc_sel_0 = io_brupdate_b2_pc_sel; // @[issue-slot.scala:69:7] wire [39:0] io_brupdate_b2_jalr_target_0 = io_brupdate_b2_jalr_target; // @[issue-slot.scala:69:7] wire [20:0] io_brupdate_b2_target_offset_0 = io_brupdate_b2_target_offset; // @[issue-slot.scala:69:7] wire io_kill_0 = io_kill; // @[issue-slot.scala:69:7] wire io_clear_0 = io_clear; // @[issue-slot.scala:69:7] wire io_ldspec_miss_0 = io_ldspec_miss; // @[issue-slot.scala:69:7] wire io_wakeup_ports_0_valid_0 = io_wakeup_ports_0_valid; // @[issue-slot.scala:69:7] wire [5:0] io_wakeup_ports_0_bits_pdst_0 = io_wakeup_ports_0_bits_pdst; // @[issue-slot.scala:69:7] wire io_wakeup_ports_0_bits_poisoned_0 = io_wakeup_ports_0_bits_poisoned; // @[issue-slot.scala:69:7] wire io_wakeup_ports_1_valid_0 = io_wakeup_ports_1_valid; // @[issue-slot.scala:69:7] wire [5:0] io_wakeup_ports_1_bits_pdst_0 = io_wakeup_ports_1_bits_pdst; // @[issue-slot.scala:69:7] wire io_wakeup_ports_1_bits_poisoned_0 = io_wakeup_ports_1_bits_poisoned; // @[issue-slot.scala:69:7] wire io_wakeup_ports_2_valid_0 = io_wakeup_ports_2_valid; // @[issue-slot.scala:69:7] wire [5:0] io_wakeup_ports_2_bits_pdst_0 = io_wakeup_ports_2_bits_pdst; // @[issue-slot.scala:69:7] wire io_wakeup_ports_2_bits_poisoned_0 = io_wakeup_ports_2_bits_poisoned; // @[issue-slot.scala:69:7] wire io_spec_ld_wakeup_0_valid_0 = io_spec_ld_wakeup_0_valid; // @[issue-slot.scala:69:7] wire [5:0] io_spec_ld_wakeup_0_bits_0 = io_spec_ld_wakeup_0_bits; // @[issue-slot.scala:69:7] wire io_in_uop_valid_0 = io_in_uop_valid; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_uopc_0 = io_in_uop_bits_uopc; // @[issue-slot.scala:69:7] wire [31:0] io_in_uop_bits_inst_0 = io_in_uop_bits_inst; // @[issue-slot.scala:69:7] wire [31:0] io_in_uop_bits_debug_inst_0 = io_in_uop_bits_debug_inst; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_rvc_0 = io_in_uop_bits_is_rvc; // @[issue-slot.scala:69:7] wire [39:0] io_in_uop_bits_debug_pc_0 = io_in_uop_bits_debug_pc; // @[issue-slot.scala:69:7] wire [2:0] io_in_uop_bits_iq_type_0 = io_in_uop_bits_iq_type; // @[issue-slot.scala:69:7] wire [9:0] io_in_uop_bits_fu_code_0 = io_in_uop_bits_fu_code; // @[issue-slot.scala:69:7] wire [3:0] io_in_uop_bits_ctrl_br_type_0 = io_in_uop_bits_ctrl_br_type; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_ctrl_op1_sel_0 = io_in_uop_bits_ctrl_op1_sel; // @[issue-slot.scala:69:7] wire [2:0] io_in_uop_bits_ctrl_op2_sel_0 = io_in_uop_bits_ctrl_op2_sel; // @[issue-slot.scala:69:7] wire [2:0] io_in_uop_bits_ctrl_imm_sel_0 = io_in_uop_bits_ctrl_imm_sel; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_ctrl_op_fcn_0 = io_in_uop_bits_ctrl_op_fcn; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ctrl_fcn_dw_0 = io_in_uop_bits_ctrl_fcn_dw; // @[issue-slot.scala:69:7] wire [2:0] io_in_uop_bits_ctrl_csr_cmd_0 = io_in_uop_bits_ctrl_csr_cmd; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ctrl_is_load_0 = io_in_uop_bits_ctrl_is_load; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ctrl_is_sta_0 = io_in_uop_bits_ctrl_is_sta; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ctrl_is_std_0 = io_in_uop_bits_ctrl_is_std; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_iw_state_0 = io_in_uop_bits_iw_state; // @[issue-slot.scala:69:7] wire io_in_uop_bits_iw_p1_poisoned_0 = io_in_uop_bits_iw_p1_poisoned; // @[issue-slot.scala:69:7] wire io_in_uop_bits_iw_p2_poisoned_0 = io_in_uop_bits_iw_p2_poisoned; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_br_0 = io_in_uop_bits_is_br; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_jalr_0 = io_in_uop_bits_is_jalr; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_jal_0 = io_in_uop_bits_is_jal; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_sfb_0 = io_in_uop_bits_is_sfb; // @[issue-slot.scala:69:7] wire [7:0] io_in_uop_bits_br_mask_0 = io_in_uop_bits_br_mask; // @[issue-slot.scala:69:7] wire [2:0] io_in_uop_bits_br_tag_0 = io_in_uop_bits_br_tag; // @[issue-slot.scala:69:7] wire [3:0] io_in_uop_bits_ftq_idx_0 = io_in_uop_bits_ftq_idx; // @[issue-slot.scala:69:7] wire io_in_uop_bits_edge_inst_0 = io_in_uop_bits_edge_inst; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_pc_lob_0 = io_in_uop_bits_pc_lob; // @[issue-slot.scala:69:7] wire io_in_uop_bits_taken_0 = io_in_uop_bits_taken; // @[issue-slot.scala:69:7] wire [19:0] io_in_uop_bits_imm_packed_0 = io_in_uop_bits_imm_packed; // @[issue-slot.scala:69:7] wire [11:0] io_in_uop_bits_csr_addr_0 = io_in_uop_bits_csr_addr; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_rob_idx_0 = io_in_uop_bits_rob_idx; // @[issue-slot.scala:69:7] wire [2:0] io_in_uop_bits_ldq_idx_0 = io_in_uop_bits_ldq_idx; // @[issue-slot.scala:69:7] wire [2:0] io_in_uop_bits_stq_idx_0 = io_in_uop_bits_stq_idx; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_rxq_idx_0 = io_in_uop_bits_rxq_idx; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_pdst_0 = io_in_uop_bits_pdst; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_prs1_0 = io_in_uop_bits_prs1; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_prs2_0 = io_in_uop_bits_prs2; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_prs3_0 = io_in_uop_bits_prs3; // @[issue-slot.scala:69:7] wire [3:0] io_in_uop_bits_ppred_0 = io_in_uop_bits_ppred; // @[issue-slot.scala:69:7] wire io_in_uop_bits_prs1_busy_0 = io_in_uop_bits_prs1_busy; // @[issue-slot.scala:69:7] wire io_in_uop_bits_prs2_busy_0 = io_in_uop_bits_prs2_busy; // @[issue-slot.scala:69:7] wire io_in_uop_bits_prs3_busy_0 = io_in_uop_bits_prs3_busy; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ppred_busy_0 = io_in_uop_bits_ppred_busy; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_stale_pdst_0 = io_in_uop_bits_stale_pdst; // @[issue-slot.scala:69:7] wire io_in_uop_bits_exception_0 = io_in_uop_bits_exception; // @[issue-slot.scala:69:7] wire [63:0] io_in_uop_bits_exc_cause_0 = io_in_uop_bits_exc_cause; // @[issue-slot.scala:69:7] wire io_in_uop_bits_bypassable_0 = io_in_uop_bits_bypassable; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_mem_cmd_0 = io_in_uop_bits_mem_cmd; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_mem_size_0 = io_in_uop_bits_mem_size; // @[issue-slot.scala:69:7] wire io_in_uop_bits_mem_signed_0 = io_in_uop_bits_mem_signed; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_fence_0 = io_in_uop_bits_is_fence; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_fencei_0 = io_in_uop_bits_is_fencei; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_amo_0 = io_in_uop_bits_is_amo; // @[issue-slot.scala:69:7] wire io_in_uop_bits_uses_ldq_0 = io_in_uop_bits_uses_ldq; // @[issue-slot.scala:69:7] wire io_in_uop_bits_uses_stq_0 = io_in_uop_bits_uses_stq; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_sys_pc2epc_0 = io_in_uop_bits_is_sys_pc2epc; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_unique_0 = io_in_uop_bits_is_unique; // @[issue-slot.scala:69:7] wire io_in_uop_bits_flush_on_commit_0 = io_in_uop_bits_flush_on_commit; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ldst_is_rs1_0 = io_in_uop_bits_ldst_is_rs1; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_ldst_0 = io_in_uop_bits_ldst; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_lrs1_0 = io_in_uop_bits_lrs1; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_lrs2_0 = io_in_uop_bits_lrs2; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_lrs3_0 = io_in_uop_bits_lrs3; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ldst_val_0 = io_in_uop_bits_ldst_val; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_dst_rtype_0 = io_in_uop_bits_dst_rtype; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_lrs1_rtype_0 = io_in_uop_bits_lrs1_rtype; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_lrs2_rtype_0 = io_in_uop_bits_lrs2_rtype; // @[issue-slot.scala:69:7] wire io_in_uop_bits_frs3_en_0 = io_in_uop_bits_frs3_en; // @[issue-slot.scala:69:7] wire io_in_uop_bits_fp_val_0 = io_in_uop_bits_fp_val; // @[issue-slot.scala:69:7] wire io_in_uop_bits_fp_single_0 = io_in_uop_bits_fp_single; // @[issue-slot.scala:69:7] wire io_in_uop_bits_xcpt_pf_if_0 = io_in_uop_bits_xcpt_pf_if; // @[issue-slot.scala:69:7] wire io_in_uop_bits_xcpt_ae_if_0 = io_in_uop_bits_xcpt_ae_if; // @[issue-slot.scala:69:7] wire io_in_uop_bits_xcpt_ma_if_0 = io_in_uop_bits_xcpt_ma_if; // @[issue-slot.scala:69:7] wire io_in_uop_bits_bp_debug_if_0 = io_in_uop_bits_bp_debug_if; // @[issue-slot.scala:69:7] wire io_in_uop_bits_bp_xcpt_if_0 = io_in_uop_bits_bp_xcpt_if; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_debug_fsrc_0 = io_in_uop_bits_debug_fsrc; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_debug_tsrc_0 = io_in_uop_bits_debug_tsrc; // @[issue-slot.scala:69:7] wire io_pred_wakeup_port_valid = 1'h0; // @[issue-slot.scala:69:7] wire slot_uop_uop_is_rvc = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ctrl_fcn_dw = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ctrl_is_load = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ctrl_is_sta = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ctrl_is_std = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_iw_p1_poisoned = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_iw_p2_poisoned = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_br = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_jalr = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_jal = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_sfb = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_edge_inst = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_taken = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_prs1_busy = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_prs2_busy = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_prs3_busy = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ppred_busy = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_exception = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_bypassable = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_mem_signed = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_fence = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_fencei = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_amo = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_uses_ldq = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_uses_stq = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_sys_pc2epc = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_unique = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_flush_on_commit = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ldst_is_rs1 = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ldst_val = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_frs3_en = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_fp_val = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_fp_single = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_xcpt_pf_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_xcpt_ae_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_xcpt_ma_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_bp_debug_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_bp_xcpt_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_cs_fcn_dw = 1'h0; // @[consts.scala:279:18] wire slot_uop_cs_is_load = 1'h0; // @[consts.scala:279:18] wire slot_uop_cs_is_sta = 1'h0; // @[consts.scala:279:18] wire slot_uop_cs_is_std = 1'h0; // @[consts.scala:279:18] wire [3:0] io_pred_wakeup_port_bits = 4'h0; // @[issue-slot.scala:69:7] wire [3:0] slot_uop_uop_ctrl_br_type = 4'h0; // @[consts.scala:269:19] wire [3:0] slot_uop_uop_ftq_idx = 4'h0; // @[consts.scala:269:19] wire [3:0] slot_uop_uop_ppred = 4'h0; // @[consts.scala:269:19] wire [3:0] slot_uop_cs_br_type = 4'h0; // @[consts.scala:279:18] wire [2:0] slot_uop_uop_iq_type = 3'h0; // @[consts.scala:269:19] wire [2:0] slot_uop_uop_ctrl_op2_sel = 3'h0; // @[consts.scala:269:19] wire [2:0] slot_uop_uop_ctrl_imm_sel = 3'h0; // @[consts.scala:269:19] wire [2:0] slot_uop_uop_ctrl_csr_cmd = 3'h0; // @[consts.scala:269:19] wire [2:0] slot_uop_uop_br_tag = 3'h0; // @[consts.scala:269:19] wire [2:0] slot_uop_uop_ldq_idx = 3'h0; // @[consts.scala:269:19] wire [2:0] slot_uop_uop_stq_idx = 3'h0; // @[consts.scala:269:19] wire [2:0] slot_uop_cs_op2_sel = 3'h0; // @[consts.scala:279:18] wire [2:0] slot_uop_cs_imm_sel = 3'h0; // @[consts.scala:279:18] wire [2:0] slot_uop_cs_csr_cmd = 3'h0; // @[consts.scala:279:18] wire [4:0] slot_uop_uop_ctrl_op_fcn = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_uop_rob_idx = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_uop_mem_cmd = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_cs_op_fcn = 5'h0; // @[consts.scala:279:18] wire [1:0] slot_uop_uop_ctrl_op1_sel = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_iw_state = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_rxq_idx = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_mem_size = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_lrs1_rtype = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_lrs2_rtype = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_debug_fsrc = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_debug_tsrc = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_cs_op1_sel = 2'h0; // @[consts.scala:279:18] wire [1:0] slot_uop_uop_dst_rtype = 2'h2; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_pc_lob = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_pdst = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_prs1 = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_prs2 = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_prs3 = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_stale_pdst = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_ldst = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_lrs1 = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_lrs2 = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_lrs3 = 6'h0; // @[consts.scala:269:19] wire [63:0] slot_uop_uop_exc_cause = 64'h0; // @[consts.scala:269:19] wire [11:0] slot_uop_uop_csr_addr = 12'h0; // @[consts.scala:269:19] wire [19:0] slot_uop_uop_imm_packed = 20'h0; // @[consts.scala:269:19] wire [7:0] slot_uop_uop_br_mask = 8'h0; // @[consts.scala:269:19] wire [9:0] slot_uop_uop_fu_code = 10'h0; // @[consts.scala:269:19] wire [39:0] slot_uop_uop_debug_pc = 40'h0; // @[consts.scala:269:19] wire [31:0] slot_uop_uop_inst = 32'h0; // @[consts.scala:269:19] wire [31:0] slot_uop_uop_debug_inst = 32'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_uopc = 7'h0; // @[consts.scala:269:19] wire _io_valid_T; // @[issue-slot.scala:79:24] wire _io_will_be_valid_T_4; // @[issue-slot.scala:262:32] wire _io_request_hp_T; // @[issue-slot.scala:243:31] wire [6:0] next_uopc; // @[issue-slot.scala:82:29] wire [1:0] next_state; // @[issue-slot.scala:81:29] wire [7:0] next_br_mask; // @[util.scala:85:25] wire _io_out_uop_prs1_busy_T; // @[issue-slot.scala:270:28] wire _io_out_uop_prs2_busy_T; // @[issue-slot.scala:271:28] wire _io_out_uop_prs3_busy_T; // @[issue-slot.scala:272:28] wire _io_out_uop_ppred_busy_T; // @[issue-slot.scala:273:28] wire [1:0] next_lrs1_rtype; // @[issue-slot.scala:83:29] wire [1:0] next_lrs2_rtype; // @[issue-slot.scala:84:29] wire [3:0] io_out_uop_ctrl_br_type_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_ctrl_op1_sel_0; // @[issue-slot.scala:69:7] wire [2:0] io_out_uop_ctrl_op2_sel_0; // @[issue-slot.scala:69:7] wire [2:0] io_out_uop_ctrl_imm_sel_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_ctrl_op_fcn_0; // @[issue-slot.scala:69:7] wire io_out_uop_ctrl_fcn_dw_0; // @[issue-slot.scala:69:7] wire [2:0] io_out_uop_ctrl_csr_cmd_0; // @[issue-slot.scala:69:7] wire io_out_uop_ctrl_is_load_0; // @[issue-slot.scala:69:7] wire io_out_uop_ctrl_is_sta_0; // @[issue-slot.scala:69:7] wire io_out_uop_ctrl_is_std_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_uopc_0; // @[issue-slot.scala:69:7] wire [31:0] io_out_uop_inst_0; // @[issue-slot.scala:69:7] wire [31:0] io_out_uop_debug_inst_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_rvc_0; // @[issue-slot.scala:69:7] wire [39:0] io_out_uop_debug_pc_0; // @[issue-slot.scala:69:7] wire [2:0] io_out_uop_iq_type_0; // @[issue-slot.scala:69:7] wire [9:0] io_out_uop_fu_code_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_iw_state_0; // @[issue-slot.scala:69:7] wire io_out_uop_iw_p1_poisoned_0; // @[issue-slot.scala:69:7] wire io_out_uop_iw_p2_poisoned_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_br_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_jalr_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_jal_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_sfb_0; // @[issue-slot.scala:69:7] wire [7:0] io_out_uop_br_mask_0; // @[issue-slot.scala:69:7] wire [2:0] io_out_uop_br_tag_0; // @[issue-slot.scala:69:7] wire [3:0] io_out_uop_ftq_idx_0; // @[issue-slot.scala:69:7] wire io_out_uop_edge_inst_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_pc_lob_0; // @[issue-slot.scala:69:7] wire io_out_uop_taken_0; // @[issue-slot.scala:69:7] wire [19:0] io_out_uop_imm_packed_0; // @[issue-slot.scala:69:7] wire [11:0] io_out_uop_csr_addr_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_rob_idx_0; // @[issue-slot.scala:69:7] wire [2:0] io_out_uop_ldq_idx_0; // @[issue-slot.scala:69:7] wire [2:0] io_out_uop_stq_idx_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_rxq_idx_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_pdst_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_prs1_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_prs2_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_prs3_0; // @[issue-slot.scala:69:7] wire [3:0] io_out_uop_ppred_0; // @[issue-slot.scala:69:7] wire io_out_uop_prs1_busy_0; // @[issue-slot.scala:69:7] wire io_out_uop_prs2_busy_0; // @[issue-slot.scala:69:7] wire io_out_uop_prs3_busy_0; // @[issue-slot.scala:69:7] wire io_out_uop_ppred_busy_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_stale_pdst_0; // @[issue-slot.scala:69:7] wire io_out_uop_exception_0; // @[issue-slot.scala:69:7] wire [63:0] io_out_uop_exc_cause_0; // @[issue-slot.scala:69:7] wire io_out_uop_bypassable_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_mem_cmd_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_mem_size_0; // @[issue-slot.scala:69:7] wire io_out_uop_mem_signed_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_fence_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_fencei_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_amo_0; // @[issue-slot.scala:69:7] wire io_out_uop_uses_ldq_0; // @[issue-slot.scala:69:7] wire io_out_uop_uses_stq_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_sys_pc2epc_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_unique_0; // @[issue-slot.scala:69:7] wire io_out_uop_flush_on_commit_0; // @[issue-slot.scala:69:7] wire io_out_uop_ldst_is_rs1_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_ldst_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_lrs1_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_lrs2_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_lrs3_0; // @[issue-slot.scala:69:7] wire io_out_uop_ldst_val_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_dst_rtype_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_lrs1_rtype_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_lrs2_rtype_0; // @[issue-slot.scala:69:7] wire io_out_uop_frs3_en_0; // @[issue-slot.scala:69:7] wire io_out_uop_fp_val_0; // @[issue-slot.scala:69:7] wire io_out_uop_fp_single_0; // @[issue-slot.scala:69:7] wire io_out_uop_xcpt_pf_if_0; // @[issue-slot.scala:69:7] wire io_out_uop_xcpt_ae_if_0; // @[issue-slot.scala:69:7] wire io_out_uop_xcpt_ma_if_0; // @[issue-slot.scala:69:7] wire io_out_uop_bp_debug_if_0; // @[issue-slot.scala:69:7] wire io_out_uop_bp_xcpt_if_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_debug_fsrc_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_debug_tsrc_0; // @[issue-slot.scala:69:7] wire [3:0] io_uop_ctrl_br_type_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_ctrl_op1_sel_0; // @[issue-slot.scala:69:7] wire [2:0] io_uop_ctrl_op2_sel_0; // @[issue-slot.scala:69:7] wire [2:0] io_uop_ctrl_imm_sel_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_ctrl_op_fcn_0; // @[issue-slot.scala:69:7] wire io_uop_ctrl_fcn_dw_0; // @[issue-slot.scala:69:7] wire [2:0] io_uop_ctrl_csr_cmd_0; // @[issue-slot.scala:69:7] wire io_uop_ctrl_is_load_0; // @[issue-slot.scala:69:7] wire io_uop_ctrl_is_sta_0; // @[issue-slot.scala:69:7] wire io_uop_ctrl_is_std_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_uopc_0; // @[issue-slot.scala:69:7] wire [31:0] io_uop_inst_0; // @[issue-slot.scala:69:7] wire [31:0] io_uop_debug_inst_0; // @[issue-slot.scala:69:7] wire io_uop_is_rvc_0; // @[issue-slot.scala:69:7] wire [39:0] io_uop_debug_pc_0; // @[issue-slot.scala:69:7] wire [2:0] io_uop_iq_type_0; // @[issue-slot.scala:69:7] wire [9:0] io_uop_fu_code_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_iw_state_0; // @[issue-slot.scala:69:7] wire io_uop_iw_p1_poisoned_0; // @[issue-slot.scala:69:7] wire io_uop_iw_p2_poisoned_0; // @[issue-slot.scala:69:7] wire io_uop_is_br_0; // @[issue-slot.scala:69:7] wire io_uop_is_jalr_0; // @[issue-slot.scala:69:7] wire io_uop_is_jal_0; // @[issue-slot.scala:69:7] wire io_uop_is_sfb_0; // @[issue-slot.scala:69:7] wire [7:0] io_uop_br_mask_0; // @[issue-slot.scala:69:7] wire [2:0] io_uop_br_tag_0; // @[issue-slot.scala:69:7] wire [3:0] io_uop_ftq_idx_0; // @[issue-slot.scala:69:7] wire io_uop_edge_inst_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_pc_lob_0; // @[issue-slot.scala:69:7] wire io_uop_taken_0; // @[issue-slot.scala:69:7] wire [19:0] io_uop_imm_packed_0; // @[issue-slot.scala:69:7] wire [11:0] io_uop_csr_addr_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_rob_idx_0; // @[issue-slot.scala:69:7] wire [2:0] io_uop_ldq_idx_0; // @[issue-slot.scala:69:7] wire [2:0] io_uop_stq_idx_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_rxq_idx_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_pdst_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_prs1_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_prs2_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_prs3_0; // @[issue-slot.scala:69:7] wire [3:0] io_uop_ppred_0; // @[issue-slot.scala:69:7] wire io_uop_prs1_busy_0; // @[issue-slot.scala:69:7] wire io_uop_prs2_busy_0; // @[issue-slot.scala:69:7] wire io_uop_prs3_busy_0; // @[issue-slot.scala:69:7] wire io_uop_ppred_busy_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_stale_pdst_0; // @[issue-slot.scala:69:7] wire io_uop_exception_0; // @[issue-slot.scala:69:7] wire [63:0] io_uop_exc_cause_0; // @[issue-slot.scala:69:7] wire io_uop_bypassable_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_mem_cmd_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_mem_size_0; // @[issue-slot.scala:69:7] wire io_uop_mem_signed_0; // @[issue-slot.scala:69:7] wire io_uop_is_fence_0; // @[issue-slot.scala:69:7] wire io_uop_is_fencei_0; // @[issue-slot.scala:69:7] wire io_uop_is_amo_0; // @[issue-slot.scala:69:7] wire io_uop_uses_ldq_0; // @[issue-slot.scala:69:7] wire io_uop_uses_stq_0; // @[issue-slot.scala:69:7] wire io_uop_is_sys_pc2epc_0; // @[issue-slot.scala:69:7] wire io_uop_is_unique_0; // @[issue-slot.scala:69:7] wire io_uop_flush_on_commit_0; // @[issue-slot.scala:69:7] wire io_uop_ldst_is_rs1_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_ldst_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_lrs1_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_lrs2_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_lrs3_0; // @[issue-slot.scala:69:7] wire io_uop_ldst_val_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_dst_rtype_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_lrs1_rtype_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_lrs2_rtype_0; // @[issue-slot.scala:69:7] wire io_uop_frs3_en_0; // @[issue-slot.scala:69:7] wire io_uop_fp_val_0; // @[issue-slot.scala:69:7] wire io_uop_fp_single_0; // @[issue-slot.scala:69:7] wire io_uop_xcpt_pf_if_0; // @[issue-slot.scala:69:7] wire io_uop_xcpt_ae_if_0; // @[issue-slot.scala:69:7] wire io_uop_xcpt_ma_if_0; // @[issue-slot.scala:69:7] wire io_uop_bp_debug_if_0; // @[issue-slot.scala:69:7] wire io_uop_bp_xcpt_if_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_debug_fsrc_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_debug_tsrc_0; // @[issue-slot.scala:69:7] wire io_debug_p1_0; // @[issue-slot.scala:69:7] wire io_debug_p2_0; // @[issue-slot.scala:69:7] wire io_debug_p3_0; // @[issue-slot.scala:69:7] wire io_debug_ppred_0; // @[issue-slot.scala:69:7] wire [1:0] io_debug_state_0; // @[issue-slot.scala:69:7] wire io_valid_0; // @[issue-slot.scala:69:7] wire io_will_be_valid_0; // @[issue-slot.scala:69:7] wire io_request_0; // @[issue-slot.scala:69:7] wire io_request_hp_0; // @[issue-slot.scala:69:7] assign io_out_uop_iw_state_0 = next_state; // @[issue-slot.scala:69:7, :81:29] assign io_out_uop_uopc_0 = next_uopc; // @[issue-slot.scala:69:7, :82:29] assign io_out_uop_lrs1_rtype_0 = next_lrs1_rtype; // @[issue-slot.scala:69:7, :83:29] assign io_out_uop_lrs2_rtype_0 = next_lrs2_rtype; // @[issue-slot.scala:69:7, :84:29] reg [1:0] state; // @[issue-slot.scala:86:22] assign io_debug_state_0 = state; // @[issue-slot.scala:69:7, :86:22] reg p1; // @[issue-slot.scala:87:22] assign io_debug_p1_0 = p1; // @[issue-slot.scala:69:7, :87:22] wire next_p1 = p1; // @[issue-slot.scala:87:22, :163:25] reg p2; // @[issue-slot.scala:88:22] assign io_debug_p2_0 = p2; // @[issue-slot.scala:69:7, :88:22] wire next_p2 = p2; // @[issue-slot.scala:88:22, :164:25] reg p3; // @[issue-slot.scala:89:22] assign io_debug_p3_0 = p3; // @[issue-slot.scala:69:7, :89:22] wire next_p3 = p3; // @[issue-slot.scala:89:22, :165:25] reg ppred; // @[issue-slot.scala:90:22] assign io_debug_ppred_0 = ppred; // @[issue-slot.scala:69:7, :90:22] wire next_ppred = ppred; // @[issue-slot.scala:90:22, :166:28] reg p1_poisoned; // @[issue-slot.scala:95:28] assign io_out_uop_iw_p1_poisoned_0 = p1_poisoned; // @[issue-slot.scala:69:7, :95:28] assign io_uop_iw_p1_poisoned_0 = p1_poisoned; // @[issue-slot.scala:69:7, :95:28] reg p2_poisoned; // @[issue-slot.scala:96:28] assign io_out_uop_iw_p2_poisoned_0 = p2_poisoned; // @[issue-slot.scala:69:7, :96:28] assign io_uop_iw_p2_poisoned_0 = p2_poisoned; // @[issue-slot.scala:69:7, :96:28] wire next_p1_poisoned = io_in_uop_valid_0 ? io_in_uop_bits_iw_p1_poisoned_0 : p1_poisoned; // @[issue-slot.scala:69:7, :95:28, :99:29] wire next_p2_poisoned = io_in_uop_valid_0 ? io_in_uop_bits_iw_p2_poisoned_0 : p2_poisoned; // @[issue-slot.scala:69:7, :96:28, :100:29] reg [6:0] slot_uop_uopc; // @[issue-slot.scala:102:25] reg [31:0] slot_uop_inst; // @[issue-slot.scala:102:25] assign io_out_uop_inst_0 = slot_uop_inst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_inst_0 = slot_uop_inst; // @[issue-slot.scala:69:7, :102:25] reg [31:0] slot_uop_debug_inst; // @[issue-slot.scala:102:25] assign io_out_uop_debug_inst_0 = slot_uop_debug_inst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_debug_inst_0 = slot_uop_debug_inst; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_rvc; // @[issue-slot.scala:102:25] assign io_out_uop_is_rvc_0 = slot_uop_is_rvc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_rvc_0 = slot_uop_is_rvc; // @[issue-slot.scala:69:7, :102:25] reg [39:0] slot_uop_debug_pc; // @[issue-slot.scala:102:25] assign io_out_uop_debug_pc_0 = slot_uop_debug_pc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_debug_pc_0 = slot_uop_debug_pc; // @[issue-slot.scala:69:7, :102:25] reg [2:0] slot_uop_iq_type; // @[issue-slot.scala:102:25] assign io_out_uop_iq_type_0 = slot_uop_iq_type; // @[issue-slot.scala:69:7, :102:25] assign io_uop_iq_type_0 = slot_uop_iq_type; // @[issue-slot.scala:69:7, :102:25] reg [9:0] slot_uop_fu_code; // @[issue-slot.scala:102:25] assign io_out_uop_fu_code_0 = slot_uop_fu_code; // @[issue-slot.scala:69:7, :102:25] assign io_uop_fu_code_0 = slot_uop_fu_code; // @[issue-slot.scala:69:7, :102:25] reg [3:0] slot_uop_ctrl_br_type; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_br_type_0 = slot_uop_ctrl_br_type; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_br_type_0 = slot_uop_ctrl_br_type; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_ctrl_op1_sel; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_op1_sel_0 = slot_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_op1_sel_0 = slot_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7, :102:25] reg [2:0] slot_uop_ctrl_op2_sel; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_op2_sel_0 = slot_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_op2_sel_0 = slot_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7, :102:25] reg [2:0] slot_uop_ctrl_imm_sel; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_imm_sel_0 = slot_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_imm_sel_0 = slot_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_ctrl_op_fcn; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_op_fcn_0 = slot_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_op_fcn_0 = slot_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_fcn_dw_0 = slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_fcn_dw_0 = slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7, :102:25] reg [2:0] slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_csr_cmd_0 = slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_csr_cmd_0 = slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ctrl_is_load; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_is_load_0 = slot_uop_ctrl_is_load; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_is_load_0 = slot_uop_ctrl_is_load; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ctrl_is_sta; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_is_sta_0 = slot_uop_ctrl_is_sta; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_is_sta_0 = slot_uop_ctrl_is_sta; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ctrl_is_std; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_is_std_0 = slot_uop_ctrl_is_std; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_is_std_0 = slot_uop_ctrl_is_std; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_iw_state; // @[issue-slot.scala:102:25] assign io_uop_iw_state_0 = slot_uop_iw_state; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_iw_p1_poisoned; // @[issue-slot.scala:102:25] reg slot_uop_iw_p2_poisoned; // @[issue-slot.scala:102:25] reg slot_uop_is_br; // @[issue-slot.scala:102:25] assign io_out_uop_is_br_0 = slot_uop_is_br; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_br_0 = slot_uop_is_br; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_jalr; // @[issue-slot.scala:102:25] assign io_out_uop_is_jalr_0 = slot_uop_is_jalr; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_jalr_0 = slot_uop_is_jalr; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_jal; // @[issue-slot.scala:102:25] assign io_out_uop_is_jal_0 = slot_uop_is_jal; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_jal_0 = slot_uop_is_jal; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_sfb; // @[issue-slot.scala:102:25] assign io_out_uop_is_sfb_0 = slot_uop_is_sfb; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_sfb_0 = slot_uop_is_sfb; // @[issue-slot.scala:69:7, :102:25] reg [7:0] slot_uop_br_mask; // @[issue-slot.scala:102:25] assign io_uop_br_mask_0 = slot_uop_br_mask; // @[issue-slot.scala:69:7, :102:25] reg [2:0] slot_uop_br_tag; // @[issue-slot.scala:102:25] assign io_out_uop_br_tag_0 = slot_uop_br_tag; // @[issue-slot.scala:69:7, :102:25] assign io_uop_br_tag_0 = slot_uop_br_tag; // @[issue-slot.scala:69:7, :102:25] reg [3:0] slot_uop_ftq_idx; // @[issue-slot.scala:102:25] assign io_out_uop_ftq_idx_0 = slot_uop_ftq_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ftq_idx_0 = slot_uop_ftq_idx; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_edge_inst; // @[issue-slot.scala:102:25] assign io_out_uop_edge_inst_0 = slot_uop_edge_inst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_edge_inst_0 = slot_uop_edge_inst; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_pc_lob; // @[issue-slot.scala:102:25] assign io_out_uop_pc_lob_0 = slot_uop_pc_lob; // @[issue-slot.scala:69:7, :102:25] assign io_uop_pc_lob_0 = slot_uop_pc_lob; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_taken; // @[issue-slot.scala:102:25] assign io_out_uop_taken_0 = slot_uop_taken; // @[issue-slot.scala:69:7, :102:25] assign io_uop_taken_0 = slot_uop_taken; // @[issue-slot.scala:69:7, :102:25] reg [19:0] slot_uop_imm_packed; // @[issue-slot.scala:102:25] assign io_out_uop_imm_packed_0 = slot_uop_imm_packed; // @[issue-slot.scala:69:7, :102:25] assign io_uop_imm_packed_0 = slot_uop_imm_packed; // @[issue-slot.scala:69:7, :102:25] reg [11:0] slot_uop_csr_addr; // @[issue-slot.scala:102:25] assign io_out_uop_csr_addr_0 = slot_uop_csr_addr; // @[issue-slot.scala:69:7, :102:25] assign io_uop_csr_addr_0 = slot_uop_csr_addr; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_rob_idx; // @[issue-slot.scala:102:25] assign io_out_uop_rob_idx_0 = slot_uop_rob_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_rob_idx_0 = slot_uop_rob_idx; // @[issue-slot.scala:69:7, :102:25] reg [2:0] slot_uop_ldq_idx; // @[issue-slot.scala:102:25] assign io_out_uop_ldq_idx_0 = slot_uop_ldq_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ldq_idx_0 = slot_uop_ldq_idx; // @[issue-slot.scala:69:7, :102:25] reg [2:0] slot_uop_stq_idx; // @[issue-slot.scala:102:25] assign io_out_uop_stq_idx_0 = slot_uop_stq_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_stq_idx_0 = slot_uop_stq_idx; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_rxq_idx; // @[issue-slot.scala:102:25] assign io_out_uop_rxq_idx_0 = slot_uop_rxq_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_rxq_idx_0 = slot_uop_rxq_idx; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_pdst; // @[issue-slot.scala:102:25] assign io_out_uop_pdst_0 = slot_uop_pdst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_pdst_0 = slot_uop_pdst; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_prs1; // @[issue-slot.scala:102:25] assign io_out_uop_prs1_0 = slot_uop_prs1; // @[issue-slot.scala:69:7, :102:25] assign io_uop_prs1_0 = slot_uop_prs1; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_prs2; // @[issue-slot.scala:102:25] assign io_out_uop_prs2_0 = slot_uop_prs2; // @[issue-slot.scala:69:7, :102:25] assign io_uop_prs2_0 = slot_uop_prs2; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_prs3; // @[issue-slot.scala:102:25] assign io_out_uop_prs3_0 = slot_uop_prs3; // @[issue-slot.scala:69:7, :102:25] assign io_uop_prs3_0 = slot_uop_prs3; // @[issue-slot.scala:69:7, :102:25] reg [3:0] slot_uop_ppred; // @[issue-slot.scala:102:25] assign io_out_uop_ppred_0 = slot_uop_ppred; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ppred_0 = slot_uop_ppred; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_prs1_busy; // @[issue-slot.scala:102:25] assign io_uop_prs1_busy_0 = slot_uop_prs1_busy; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_prs2_busy; // @[issue-slot.scala:102:25] assign io_uop_prs2_busy_0 = slot_uop_prs2_busy; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_prs3_busy; // @[issue-slot.scala:102:25] assign io_uop_prs3_busy_0 = slot_uop_prs3_busy; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ppred_busy; // @[issue-slot.scala:102:25] assign io_uop_ppred_busy_0 = slot_uop_ppred_busy; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_stale_pdst; // @[issue-slot.scala:102:25] assign io_out_uop_stale_pdst_0 = slot_uop_stale_pdst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_stale_pdst_0 = slot_uop_stale_pdst; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_exception; // @[issue-slot.scala:102:25] assign io_out_uop_exception_0 = slot_uop_exception; // @[issue-slot.scala:69:7, :102:25] assign io_uop_exception_0 = slot_uop_exception; // @[issue-slot.scala:69:7, :102:25] reg [63:0] slot_uop_exc_cause; // @[issue-slot.scala:102:25] assign io_out_uop_exc_cause_0 = slot_uop_exc_cause; // @[issue-slot.scala:69:7, :102:25] assign io_uop_exc_cause_0 = slot_uop_exc_cause; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_bypassable; // @[issue-slot.scala:102:25] assign io_out_uop_bypassable_0 = slot_uop_bypassable; // @[issue-slot.scala:69:7, :102:25] assign io_uop_bypassable_0 = slot_uop_bypassable; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_mem_cmd; // @[issue-slot.scala:102:25] assign io_out_uop_mem_cmd_0 = slot_uop_mem_cmd; // @[issue-slot.scala:69:7, :102:25] assign io_uop_mem_cmd_0 = slot_uop_mem_cmd; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_mem_size; // @[issue-slot.scala:102:25] assign io_out_uop_mem_size_0 = slot_uop_mem_size; // @[issue-slot.scala:69:7, :102:25] assign io_uop_mem_size_0 = slot_uop_mem_size; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_mem_signed; // @[issue-slot.scala:102:25] assign io_out_uop_mem_signed_0 = slot_uop_mem_signed; // @[issue-slot.scala:69:7, :102:25] assign io_uop_mem_signed_0 = slot_uop_mem_signed; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_fence; // @[issue-slot.scala:102:25] assign io_out_uop_is_fence_0 = slot_uop_is_fence; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_fence_0 = slot_uop_is_fence; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_fencei; // @[issue-slot.scala:102:25] assign io_out_uop_is_fencei_0 = slot_uop_is_fencei; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_fencei_0 = slot_uop_is_fencei; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_amo; // @[issue-slot.scala:102:25] assign io_out_uop_is_amo_0 = slot_uop_is_amo; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_amo_0 = slot_uop_is_amo; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_uses_ldq; // @[issue-slot.scala:102:25] assign io_out_uop_uses_ldq_0 = slot_uop_uses_ldq; // @[issue-slot.scala:69:7, :102:25] assign io_uop_uses_ldq_0 = slot_uop_uses_ldq; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_uses_stq; // @[issue-slot.scala:102:25] assign io_out_uop_uses_stq_0 = slot_uop_uses_stq; // @[issue-slot.scala:69:7, :102:25] assign io_uop_uses_stq_0 = slot_uop_uses_stq; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_sys_pc2epc; // @[issue-slot.scala:102:25] assign io_out_uop_is_sys_pc2epc_0 = slot_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_sys_pc2epc_0 = slot_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_unique; // @[issue-slot.scala:102:25] assign io_out_uop_is_unique_0 = slot_uop_is_unique; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_unique_0 = slot_uop_is_unique; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_flush_on_commit; // @[issue-slot.scala:102:25] assign io_out_uop_flush_on_commit_0 = slot_uop_flush_on_commit; // @[issue-slot.scala:69:7, :102:25] assign io_uop_flush_on_commit_0 = slot_uop_flush_on_commit; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ldst_is_rs1; // @[issue-slot.scala:102:25] assign io_out_uop_ldst_is_rs1_0 = slot_uop_ldst_is_rs1; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ldst_is_rs1_0 = slot_uop_ldst_is_rs1; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_ldst; // @[issue-slot.scala:102:25] assign io_out_uop_ldst_0 = slot_uop_ldst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ldst_0 = slot_uop_ldst; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_lrs1; // @[issue-slot.scala:102:25] assign io_out_uop_lrs1_0 = slot_uop_lrs1; // @[issue-slot.scala:69:7, :102:25] assign io_uop_lrs1_0 = slot_uop_lrs1; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_lrs2; // @[issue-slot.scala:102:25] assign io_out_uop_lrs2_0 = slot_uop_lrs2; // @[issue-slot.scala:69:7, :102:25] assign io_uop_lrs2_0 = slot_uop_lrs2; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_lrs3; // @[issue-slot.scala:102:25] assign io_out_uop_lrs3_0 = slot_uop_lrs3; // @[issue-slot.scala:69:7, :102:25] assign io_uop_lrs3_0 = slot_uop_lrs3; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ldst_val; // @[issue-slot.scala:102:25] assign io_out_uop_ldst_val_0 = slot_uop_ldst_val; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ldst_val_0 = slot_uop_ldst_val; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_dst_rtype; // @[issue-slot.scala:102:25] assign io_out_uop_dst_rtype_0 = slot_uop_dst_rtype; // @[issue-slot.scala:69:7, :102:25] assign io_uop_dst_rtype_0 = slot_uop_dst_rtype; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_lrs1_rtype; // @[issue-slot.scala:102:25] reg [1:0] slot_uop_lrs2_rtype; // @[issue-slot.scala:102:25] reg slot_uop_frs3_en; // @[issue-slot.scala:102:25] assign io_out_uop_frs3_en_0 = slot_uop_frs3_en; // @[issue-slot.scala:69:7, :102:25] assign io_uop_frs3_en_0 = slot_uop_frs3_en; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_fp_val; // @[issue-slot.scala:102:25] assign io_out_uop_fp_val_0 = slot_uop_fp_val; // @[issue-slot.scala:69:7, :102:25] assign io_uop_fp_val_0 = slot_uop_fp_val; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_fp_single; // @[issue-slot.scala:102:25] assign io_out_uop_fp_single_0 = slot_uop_fp_single; // @[issue-slot.scala:69:7, :102:25] assign io_uop_fp_single_0 = slot_uop_fp_single; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_xcpt_pf_if; // @[issue-slot.scala:102:25] assign io_out_uop_xcpt_pf_if_0 = slot_uop_xcpt_pf_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_xcpt_pf_if_0 = slot_uop_xcpt_pf_if; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_xcpt_ae_if; // @[issue-slot.scala:102:25] assign io_out_uop_xcpt_ae_if_0 = slot_uop_xcpt_ae_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_xcpt_ae_if_0 = slot_uop_xcpt_ae_if; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_xcpt_ma_if; // @[issue-slot.scala:102:25] assign io_out_uop_xcpt_ma_if_0 = slot_uop_xcpt_ma_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_xcpt_ma_if_0 = slot_uop_xcpt_ma_if; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_bp_debug_if; // @[issue-slot.scala:102:25] assign io_out_uop_bp_debug_if_0 = slot_uop_bp_debug_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_bp_debug_if_0 = slot_uop_bp_debug_if; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_bp_xcpt_if; // @[issue-slot.scala:102:25] assign io_out_uop_bp_xcpt_if_0 = slot_uop_bp_xcpt_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_bp_xcpt_if_0 = slot_uop_bp_xcpt_if; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_debug_fsrc; // @[issue-slot.scala:102:25] assign io_out_uop_debug_fsrc_0 = slot_uop_debug_fsrc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_debug_fsrc_0 = slot_uop_debug_fsrc; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_debug_tsrc; // @[issue-slot.scala:102:25] assign io_out_uop_debug_tsrc_0 = slot_uop_debug_tsrc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_debug_tsrc_0 = slot_uop_debug_tsrc; // @[issue-slot.scala:69:7, :102:25] wire [6:0] next_uop_uopc = io_in_uop_valid_0 ? io_in_uop_bits_uopc_0 : slot_uop_uopc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [31:0] next_uop_inst = io_in_uop_valid_0 ? io_in_uop_bits_inst_0 : slot_uop_inst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [31:0] next_uop_debug_inst = io_in_uop_valid_0 ? io_in_uop_bits_debug_inst_0 : slot_uop_debug_inst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_rvc = io_in_uop_valid_0 ? io_in_uop_bits_is_rvc_0 : slot_uop_is_rvc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [39:0] next_uop_debug_pc = io_in_uop_valid_0 ? io_in_uop_bits_debug_pc_0 : slot_uop_debug_pc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [2:0] next_uop_iq_type = io_in_uop_valid_0 ? io_in_uop_bits_iq_type_0 : slot_uop_iq_type; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [9:0] next_uop_fu_code = io_in_uop_valid_0 ? io_in_uop_bits_fu_code_0 : slot_uop_fu_code; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [3:0] next_uop_ctrl_br_type = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_br_type_0 : slot_uop_ctrl_br_type; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_ctrl_op1_sel = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_op1_sel_0 : slot_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [2:0] next_uop_ctrl_op2_sel = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_op2_sel_0 : slot_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [2:0] next_uop_ctrl_imm_sel = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_imm_sel_0 : slot_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_ctrl_op_fcn = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_op_fcn_0 : slot_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ctrl_fcn_dw = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_fcn_dw_0 : slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [2:0] next_uop_ctrl_csr_cmd = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_csr_cmd_0 : slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ctrl_is_load = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_is_load_0 : slot_uop_ctrl_is_load; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ctrl_is_sta = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_is_sta_0 : slot_uop_ctrl_is_sta; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ctrl_is_std = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_is_std_0 : slot_uop_ctrl_is_std; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_iw_state = io_in_uop_valid_0 ? io_in_uop_bits_iw_state_0 : slot_uop_iw_state; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_iw_p1_poisoned = io_in_uop_valid_0 ? io_in_uop_bits_iw_p1_poisoned_0 : slot_uop_iw_p1_poisoned; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_iw_p2_poisoned = io_in_uop_valid_0 ? io_in_uop_bits_iw_p2_poisoned_0 : slot_uop_iw_p2_poisoned; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_br = io_in_uop_valid_0 ? io_in_uop_bits_is_br_0 : slot_uop_is_br; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_jalr = io_in_uop_valid_0 ? io_in_uop_bits_is_jalr_0 : slot_uop_is_jalr; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_jal = io_in_uop_valid_0 ? io_in_uop_bits_is_jal_0 : slot_uop_is_jal; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_sfb = io_in_uop_valid_0 ? io_in_uop_bits_is_sfb_0 : slot_uop_is_sfb; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [7:0] next_uop_br_mask = io_in_uop_valid_0 ? io_in_uop_bits_br_mask_0 : slot_uop_br_mask; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [2:0] next_uop_br_tag = io_in_uop_valid_0 ? io_in_uop_bits_br_tag_0 : slot_uop_br_tag; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [3:0] next_uop_ftq_idx = io_in_uop_valid_0 ? io_in_uop_bits_ftq_idx_0 : slot_uop_ftq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_edge_inst = io_in_uop_valid_0 ? io_in_uop_bits_edge_inst_0 : slot_uop_edge_inst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_pc_lob = io_in_uop_valid_0 ? io_in_uop_bits_pc_lob_0 : slot_uop_pc_lob; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_taken = io_in_uop_valid_0 ? io_in_uop_bits_taken_0 : slot_uop_taken; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [19:0] next_uop_imm_packed = io_in_uop_valid_0 ? io_in_uop_bits_imm_packed_0 : slot_uop_imm_packed; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [11:0] next_uop_csr_addr = io_in_uop_valid_0 ? io_in_uop_bits_csr_addr_0 : slot_uop_csr_addr; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_rob_idx = io_in_uop_valid_0 ? io_in_uop_bits_rob_idx_0 : slot_uop_rob_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [2:0] next_uop_ldq_idx = io_in_uop_valid_0 ? io_in_uop_bits_ldq_idx_0 : slot_uop_ldq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [2:0] next_uop_stq_idx = io_in_uop_valid_0 ? io_in_uop_bits_stq_idx_0 : slot_uop_stq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_rxq_idx = io_in_uop_valid_0 ? io_in_uop_bits_rxq_idx_0 : slot_uop_rxq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_pdst = io_in_uop_valid_0 ? io_in_uop_bits_pdst_0 : slot_uop_pdst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_prs1 = io_in_uop_valid_0 ? io_in_uop_bits_prs1_0 : slot_uop_prs1; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_prs2 = io_in_uop_valid_0 ? io_in_uop_bits_prs2_0 : slot_uop_prs2; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_prs3 = io_in_uop_valid_0 ? io_in_uop_bits_prs3_0 : slot_uop_prs3; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [3:0] next_uop_ppred = io_in_uop_valid_0 ? io_in_uop_bits_ppred_0 : slot_uop_ppred; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_prs1_busy = io_in_uop_valid_0 ? io_in_uop_bits_prs1_busy_0 : slot_uop_prs1_busy; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_prs2_busy = io_in_uop_valid_0 ? io_in_uop_bits_prs2_busy_0 : slot_uop_prs2_busy; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_prs3_busy = io_in_uop_valid_0 ? io_in_uop_bits_prs3_busy_0 : slot_uop_prs3_busy; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ppred_busy = io_in_uop_valid_0 ? io_in_uop_bits_ppred_busy_0 : slot_uop_ppred_busy; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_stale_pdst = io_in_uop_valid_0 ? io_in_uop_bits_stale_pdst_0 : slot_uop_stale_pdst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_exception = io_in_uop_valid_0 ? io_in_uop_bits_exception_0 : slot_uop_exception; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [63:0] next_uop_exc_cause = io_in_uop_valid_0 ? io_in_uop_bits_exc_cause_0 : slot_uop_exc_cause; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_bypassable = io_in_uop_valid_0 ? io_in_uop_bits_bypassable_0 : slot_uop_bypassable; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_mem_cmd = io_in_uop_valid_0 ? io_in_uop_bits_mem_cmd_0 : slot_uop_mem_cmd; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_mem_size = io_in_uop_valid_0 ? io_in_uop_bits_mem_size_0 : slot_uop_mem_size; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_mem_signed = io_in_uop_valid_0 ? io_in_uop_bits_mem_signed_0 : slot_uop_mem_signed; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_fence = io_in_uop_valid_0 ? io_in_uop_bits_is_fence_0 : slot_uop_is_fence; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_fencei = io_in_uop_valid_0 ? io_in_uop_bits_is_fencei_0 : slot_uop_is_fencei; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_amo = io_in_uop_valid_0 ? io_in_uop_bits_is_amo_0 : slot_uop_is_amo; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_uses_ldq = io_in_uop_valid_0 ? io_in_uop_bits_uses_ldq_0 : slot_uop_uses_ldq; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_uses_stq = io_in_uop_valid_0 ? io_in_uop_bits_uses_stq_0 : slot_uop_uses_stq; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_sys_pc2epc = io_in_uop_valid_0 ? io_in_uop_bits_is_sys_pc2epc_0 : slot_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_unique = io_in_uop_valid_0 ? io_in_uop_bits_is_unique_0 : slot_uop_is_unique; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_flush_on_commit = io_in_uop_valid_0 ? io_in_uop_bits_flush_on_commit_0 : slot_uop_flush_on_commit; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ldst_is_rs1 = io_in_uop_valid_0 ? io_in_uop_bits_ldst_is_rs1_0 : slot_uop_ldst_is_rs1; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_ldst = io_in_uop_valid_0 ? io_in_uop_bits_ldst_0 : slot_uop_ldst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_lrs1 = io_in_uop_valid_0 ? io_in_uop_bits_lrs1_0 : slot_uop_lrs1; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_lrs2 = io_in_uop_valid_0 ? io_in_uop_bits_lrs2_0 : slot_uop_lrs2; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_lrs3 = io_in_uop_valid_0 ? io_in_uop_bits_lrs3_0 : slot_uop_lrs3; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ldst_val = io_in_uop_valid_0 ? io_in_uop_bits_ldst_val_0 : slot_uop_ldst_val; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_dst_rtype = io_in_uop_valid_0 ? io_in_uop_bits_dst_rtype_0 : slot_uop_dst_rtype; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_lrs1_rtype = io_in_uop_valid_0 ? io_in_uop_bits_lrs1_rtype_0 : slot_uop_lrs1_rtype; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_lrs2_rtype = io_in_uop_valid_0 ? io_in_uop_bits_lrs2_rtype_0 : slot_uop_lrs2_rtype; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_frs3_en = io_in_uop_valid_0 ? io_in_uop_bits_frs3_en_0 : slot_uop_frs3_en; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_fp_val = io_in_uop_valid_0 ? io_in_uop_bits_fp_val_0 : slot_uop_fp_val; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_fp_single = io_in_uop_valid_0 ? io_in_uop_bits_fp_single_0 : slot_uop_fp_single; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_xcpt_pf_if = io_in_uop_valid_0 ? io_in_uop_bits_xcpt_pf_if_0 : slot_uop_xcpt_pf_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_xcpt_ae_if = io_in_uop_valid_0 ? io_in_uop_bits_xcpt_ae_if_0 : slot_uop_xcpt_ae_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_xcpt_ma_if = io_in_uop_valid_0 ? io_in_uop_bits_xcpt_ma_if_0 : slot_uop_xcpt_ma_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_bp_debug_if = io_in_uop_valid_0 ? io_in_uop_bits_bp_debug_if_0 : slot_uop_bp_debug_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_bp_xcpt_if = io_in_uop_valid_0 ? io_in_uop_bits_bp_xcpt_if_0 : slot_uop_bp_xcpt_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_debug_fsrc = io_in_uop_valid_0 ? io_in_uop_bits_debug_fsrc_0 : slot_uop_debug_fsrc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_debug_tsrc = io_in_uop_valid_0 ? io_in_uop_bits_debug_tsrc_0 : slot_uop_debug_tsrc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire _T_11 = state == 2'h2; // @[issue-slot.scala:86:22, :134:25] wire _T_7 = io_grant_0 & state == 2'h1 \| io_grant_0 & _T_11 & p1 & p2 & ppred; // @[issue-slot.scala:69:7, :86:22, :87:22, :88:22, :90:22, :133:{26,36,52}, :134:{15,25,40,46,52}] wire _T_12 = io_grant_0 & _T_11; // @[issue-slot.scala:69:7, :134:25, :139:25] wire _T_14 = io_ldspec_miss_0 & (p1_poisoned \| p2_poisoned); // @[issue-slot.scala:69:7, :95:28, :96:28, :140:{28,44}] wire _GEN = _T_12 & ~_T_14; // @[issue-slot.scala:126:14, :139:{25,51}, :140:{11,28,62}, :141:18] wire _GEN_0 = io_kill_0 \| _T_7; // @[issue-slot.scala:69:7, :102:25, :131:18, :133:52, :134:63, :139:51] wire _GEN_1 = _GEN_0 \| ~(_T_12 & ~_T_14 & p1); // @[issue-slot.scala:87:22, :102:25, :131:18, :134:63, :139:{25,51}, :140:{11,28,62}, :142:17, :143:23] assign next_uopc = _GEN_1 ? slot_uop_uopc : 7'h3; // @[issue-slot.scala:82:29, :102:25, :131:18, :134:63, :139:51] assign next_lrs1_rtype = _GEN_1 ? slot_uop_lrs1_rtype : 2'h2; // @[issue-slot.scala:83:29, :102:25, :131:18, :134:63, :139:51] wire _GEN_2 = _GEN_0 \| ~_GEN \| p1; // @[issue-slot.scala:87:22, :102:25, :126:14, :131:18, :134:63, :139:51, :140:62, :141:18, :142:17] assign next_lrs2_rtype = _GEN_2 ? slot_uop_lrs2_rtype : 2'h2; // @[issue-slot.scala:84:29, :102:25, :131:18, :134:63, :139:51, :140:62, :142:17] wire _p1_T = ~io_in_uop_bits_prs1_busy_0; // @[issue-slot.scala:69:7, :169:11] wire _p2_T = ~io_in_uop_bits_prs2_busy_0; // @[issue-slot.scala:69:7, :170:11] wire _p3_T = ~io_in_uop_bits_prs3_busy_0; // @[issue-slot.scala:69:7, :171:11] wire _ppred_T = ~io_in_uop_bits_ppred_busy_0; // @[issue-slot.scala:69:7, :172:14] wire _T_22 = io_ldspec_miss_0 & next_p1_poisoned; // @[issue-slot.scala:69:7, :99:29, :175:24] wire _T_27 = io_ldspec_miss_0 & next_p2_poisoned; // @[issue-slot.scala:69:7, :100:29, :179:24] wire _T_61 = io_spec_ld_wakeup_0_valid_0 & io_spec_ld_wakeup_0_bits_0 == next_uop_prs1 & next_uop_lrs1_rtype == 2'h0; // @[issue-slot.scala:69:7, :103:21, :209:38, :210:{33,51}, :211:27] wire _T_69 = io_spec_ld_wakeup_0_valid_0 & io_spec_ld_wakeup_0_bits_0 == next_uop_prs2 & next_uop_lrs2_rtype == 2'h0; // @[issue-slot.scala:69:7, :103:21, :216:38, :217:{33,51}, :218:27]
Generate the Verilog code corresponding to the following Chisel files. File Tile.scala: // See README.md for license details. package gemmini import chisel3._ import chisel3.util._ import Util._ /** * A Tile is a purely combinational 2D array of passThrough PEs. * a, b, s, and in_propag are broadcast across the entire array and are passed through to the Tile's outputs * @param width The data width of each PE in bits * @param rows Number of PEs on each row * @param columns Number of PEs on each column */ class Tile[T <: Data](inputType: T, outputType: T, accType: T, df: Dataflow.Value, tree_reduction: Boolean, max_simultaneous_matmuls: Int, val rows: Int, val columns: Int)(implicit ev: Arithmetic[T]) extends Module { val io = IO(new Bundle { val in_a = Input(Vec(rows, inputType)) val in_b = Input(Vec(columns, outputType)) // This is the output of the tile next to it val in_d = Input(Vec(columns, outputType)) val in_control = Input(Vec(columns, new PEControl(accType))) val in_id = Input(Vec(columns, UInt(log2Up(max_simultaneous_matmuls).W))) val in_last = Input(Vec(columns, Bool())) val out_a = Output(Vec(rows, inputType)) val out_c = Output(Vec(columns, outputType)) val out_b = Output(Vec(columns, outputType)) val out_control = Output(Vec(columns, new PEControl(accType))) val out_id = Output(Vec(columns, UInt(log2Up(max_simultaneous_matmuls).W))) val out_last = Output(Vec(columns, Bool())) val in_valid = Input(Vec(columns, Bool())) val out_valid = Output(Vec(columns, Bool())) val bad_dataflow = Output(Bool()) }) import ev._ val tile = Seq.fill(rows, columns)(Module(new PE(inputType, outputType, accType, df, max_simultaneous_matmuls))) val tileT = tile.transpose // TODO: abstract hori/vert broadcast, all these connections look the same // Broadcast 'a' horizontally across the Tile for (r <- 0 until rows) { tile(r).foldLeft(io.in_a(r)) { case (in_a, pe) => pe.io.in_a := in_a pe.io.out_a } } // Broadcast 'b' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_b(c)) { case (in_b, pe) => pe.io.in_b := (if (tree_reduction) in_b.zero else in_b) pe.io.out_b } } // Broadcast 'd' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_d(c)) { case (in_d, pe) => pe.io.in_d := in_d pe.io.out_c } } // Broadcast 'control' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_control(c)) { case (in_ctrl, pe) => pe.io.in_control := in_ctrl pe.io.out_control } } // Broadcast 'garbage' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_valid(c)) { case (v, pe) => pe.io.in_valid := v pe.io.out_valid } } // Broadcast 'id' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_id(c)) { case (id, pe) => pe.io.in_id := id pe.io.out_id } } // Broadcast 'last' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_last(c)) { case (last, pe) => pe.io.in_last := last pe.io.out_last } } // Drive the Tile's bottom IO for (c <- 0 until columns) { io.out_c(c) := tile(rows-1)(c).io.out_c io.out_control(c) := tile(rows-1)(c).io.out_control io.out_id(c) := tile(rows-1)(c).io.out_id io.out_last(c) := tile(rows-1)(c).io.out_last io.out_valid(c) := tile(rows-1)(c).io.out_valid io.out_b(c) := { if (tree_reduction) { val prods = tileT(c).map(_.io.out_b) accumulateTree(prods :+ io.in_b(c)) } else { tile(rows - 1)(c).io.out_b } } } io.bad_dataflow := tile.map(_.map(_.io.bad_dataflow).reduce(_\|\|_)).reduce(_\|\|_) // Drive the Tile's right IO for (r <- 0 until rows) { io.out_a(r) := tile(r)(columns-1).io.out_a } }	module Tile_166( // @[Tile.scala:16:7] input clock, // @[Tile.scala:16:7] input reset, // @[Tile.scala:16:7] input [7:0] io_in_a_0, // @[Tile.scala:17:14] input [19:0] io_in_b_0, // @[Tile.scala:17:14] input [19:0] io_in_d_0, // @[Tile.scala:17:14] input io_in_control_0_dataflow, // @[Tile.scala:17:14] input io_in_control_0_propagate, // @[Tile.scala:17:14] input [4:0] io_in_control_0_shift, // @[Tile.scala:17:14] input [2:0] io_in_id_0, // @[Tile.scala:17:14] input io_in_last_0, // @[Tile.scala:17:14] output [7:0] io_out_a_0, // @[Tile.scala:17:14] output [19:0] io_out_c_0, // @[Tile.scala:17:14] output [19:0] io_out_b_0, // @[Tile.scala:17:14] output io_out_control_0_dataflow, // @[Tile.scala:17:14] output io_out_control_0_propagate, // @[Tile.scala:17:14] output [4:0] io_out_control_0_shift, // @[Tile.scala:17:14] output [2:0] io_out_id_0, // @[Tile.scala:17:14] output io_out_last_0, // @[Tile.scala:17:14] input io_in_valid_0, // @[Tile.scala:17:14] output io_out_valid_0, // @[Tile.scala:17:14] output io_bad_dataflow // @[Tile.scala:17:14] ); wire [7:0] io_in_a_0_0 = io_in_a_0; // @[Tile.scala:16:7] wire [19:0] io_in_b_0_0 = io_in_b_0; // @[Tile.scala:16:7] wire [19:0] io_in_d_0_0 = io_in_d_0; // @[Tile.scala:16:7] wire io_in_control_0_dataflow_0 = io_in_control_0_dataflow; // @[Tile.scala:16:7] wire io_in_control_0_propagate_0 = io_in_control_0_propagate; // @[Tile.scala:16:7] wire [4:0] io_in_control_0_shift_0 = io_in_control_0_shift; // @[Tile.scala:16:7] wire [2:0] io_in_id_0_0 = io_in_id_0; // @[Tile.scala:16:7] wire io_in_last_0_0 = io_in_last_0; // @[Tile.scala:16:7] wire io_in_valid_0_0 = io_in_valid_0; // @[Tile.scala:16:7] wire [7:0] io_out_a_0_0; // @[Tile.scala:16:7] wire [19:0] io_out_c_0_0; // @[Tile.scala:16:7] wire [19:0] io_out_b_0_0; // @[Tile.scala:16:7] wire io_out_control_0_dataflow_0; // @[Tile.scala:16:7] wire io_out_control_0_propagate_0; // @[Tile.scala:16:7] wire [4:0] io_out_control_0_shift_0; // @[Tile.scala:16:7] wire [2:0] io_out_id_0_0; // @[Tile.scala:16:7] wire io_out_last_0_0; // @[Tile.scala:16:7] wire io_out_valid_0_0; // @[Tile.scala:16:7] wire io_bad_dataflow_0; // @[Tile.scala:16:7] PE_422 tile_0_0 ( // @[Tile.scala:42:44] .clock (clock), .reset (reset), .io_in_a (io_in_a_0_0), // @[Tile.scala:16:7] .io_in_b (io_in_b_0_0), // @[Tile.scala:16:7] .io_in_d (io_in_d_0_0), // @[Tile.scala:16:7] .io_out_a (io_out_a_0_0), .io_out_b (io_out_b_0_0), .io_out_c (io_out_c_0_0), .io_in_control_dataflow (io_in_control_0_dataflow_0), // @[Tile.scala:16:7] .io_in_control_propagate (io_in_control_0_propagate_0), // @[Tile.scala:16:7] .io_in_control_shift (io_in_control_0_shift_0), // @[Tile.scala:16:7] .io_out_control_dataflow (io_out_control_0_dataflow_0), .io_out_control_propagate (io_out_control_0_propagate_0), .io_out_control_shift (io_out_control_0_shift_0), .io_in_id (io_in_id_0_0), // @[Tile.scala:16:7] .io_out_id (io_out_id_0_0), .io_in_last (io_in_last_0_0), // @[Tile.scala:16:7] .io_out_last (io_out_last_0_0), .io_in_valid (io_in_valid_0_0), // @[Tile.scala:16:7] .io_out_valid (io_out_valid_0_0), .io_bad_dataflow (io_bad_dataflow_0) ); // @[Tile.scala:42:44] assign io_out_a_0 = io_out_a_0_0; // @[Tile.scala:16:7] assign io_out_c_0 = io_out_c_0_0; // @[Tile.scala:16:7] assign io_out_b_0 = io_out_b_0_0; // @[Tile.scala:16:7] assign io_out_control_0_dataflow = io_out_control_0_dataflow_0; // @[Tile.scala:16:7] assign io_out_control_0_propagate = io_out_control_0_propagate_0; // @[Tile.scala:16:7] assign io_out_control_0_shift = io_out_control_0_shift_0; // @[Tile.scala:16:7] assign io_out_id_0 = io_out_id_0_0; // @[Tile.scala:16:7] assign io_out_last_0 = io_out_last_0_0; // @[Tile.scala:16:7] assign io_out_valid_0 = io_out_valid_0_0; // @[Tile.scala:16:7] assign io_bad_dataflow = io_bad_dataflow_0; // @[Tile.scala:16:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File Tile.scala: // See README.md for license details. package gemmini import chisel3._ import chisel3.util._ import Util._ /** * A Tile is a purely combinational 2D array of passThrough PEs. * a, b, s, and in_propag are broadcast across the entire array and are passed through to the Tile's outputs * @param width The data width of each PE in bits * @param rows Number of PEs on each row * @param columns Number of PEs on each column */ class Tile[T <: Data](inputType: T, outputType: T, accType: T, df: Dataflow.Value, tree_reduction: Boolean, max_simultaneous_matmuls: Int, val rows: Int, val columns: Int)(implicit ev: Arithmetic[T]) extends Module { val io = IO(new Bundle { val in_a = Input(Vec(rows, inputType)) val in_b = Input(Vec(columns, outputType)) // This is the output of the tile next to it val in_d = Input(Vec(columns, outputType)) val in_control = Input(Vec(columns, new PEControl(accType))) val in_id = Input(Vec(columns, UInt(log2Up(max_simultaneous_matmuls).W))) val in_last = Input(Vec(columns, Bool())) val out_a = Output(Vec(rows, inputType)) val out_c = Output(Vec(columns, outputType)) val out_b = Output(Vec(columns, outputType)) val out_control = Output(Vec(columns, new PEControl(accType))) val out_id = Output(Vec(columns, UInt(log2Up(max_simultaneous_matmuls).W))) val out_last = Output(Vec(columns, Bool())) val in_valid = Input(Vec(columns, Bool())) val out_valid = Output(Vec(columns, Bool())) val bad_dataflow = Output(Bool()) }) import ev._ val tile = Seq.fill(rows, columns)(Module(new PE(inputType, outputType, accType, df, max_simultaneous_matmuls))) val tileT = tile.transpose // TODO: abstract hori/vert broadcast, all these connections look the same // Broadcast 'a' horizontally across the Tile for (r <- 0 until rows) { tile(r).foldLeft(io.in_a(r)) { case (in_a, pe) => pe.io.in_a := in_a pe.io.out_a } } // Broadcast 'b' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_b(c)) { case (in_b, pe) => pe.io.in_b := (if (tree_reduction) in_b.zero else in_b) pe.io.out_b } } // Broadcast 'd' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_d(c)) { case (in_d, pe) => pe.io.in_d := in_d pe.io.out_c } } // Broadcast 'control' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_control(c)) { case (in_ctrl, pe) => pe.io.in_control := in_ctrl pe.io.out_control } } // Broadcast 'garbage' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_valid(c)) { case (v, pe) => pe.io.in_valid := v pe.io.out_valid } } // Broadcast 'id' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_id(c)) { case (id, pe) => pe.io.in_id := id pe.io.out_id } } // Broadcast 'last' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_last(c)) { case (last, pe) => pe.io.in_last := last pe.io.out_last } } // Drive the Tile's bottom IO for (c <- 0 until columns) { io.out_c(c) := tile(rows-1)(c).io.out_c io.out_control(c) := tile(rows-1)(c).io.out_control io.out_id(c) := tile(rows-1)(c).io.out_id io.out_last(c) := tile(rows-1)(c).io.out_last io.out_valid(c) := tile(rows-1)(c).io.out_valid io.out_b(c) := { if (tree_reduction) { val prods = tileT(c).map(_.io.out_b) accumulateTree(prods :+ io.in_b(c)) } else { tile(rows - 1)(c).io.out_b } } } io.bad_dataflow := tile.map(_.map(_.io.bad_dataflow).reduce(_\|\|_)).reduce(_\|\|_) // Drive the Tile's right IO for (r <- 0 until rows) { io.out_a(r) := tile(r)(columns-1).io.out_a } }	module Tile_230( // @[Tile.scala:16:7] input clock, // @[Tile.scala:16:7] input reset, // @[Tile.scala:16:7] input [7:0] io_in_a_0, // @[Tile.scala:17:14] input [19:0] io_in_b_0, // @[Tile.scala:17:14] input [19:0] io_in_d_0, // @[Tile.scala:17:14] input io_in_control_0_dataflow, // @[Tile.scala:17:14] input io_in_control_0_propagate, // @[Tile.scala:17:14] input [4:0] io_in_control_0_shift, // @[Tile.scala:17:14] input [2:0] io_in_id_0, // @[Tile.scala:17:14] input io_in_last_0, // @[Tile.scala:17:14] output [7:0] io_out_a_0, // @[Tile.scala:17:14] output [19:0] io_out_c_0, // @[Tile.scala:17:14] output [19:0] io_out_b_0, // @[Tile.scala:17:14] output io_out_control_0_dataflow, // @[Tile.scala:17:14] output io_out_control_0_propagate, // @[Tile.scala:17:14] output [4:0] io_out_control_0_shift, // @[Tile.scala:17:14] output [2:0] io_out_id_0, // @[Tile.scala:17:14] output io_out_last_0, // @[Tile.scala:17:14] input io_in_valid_0, // @[Tile.scala:17:14] output io_out_valid_0 // @[Tile.scala:17:14] ); wire [7:0] io_in_a_0_0 = io_in_a_0; // @[Tile.scala:16:7] wire [19:0] io_in_b_0_0 = io_in_b_0; // @[Tile.scala:16:7] wire [19:0] io_in_d_0_0 = io_in_d_0; // @[Tile.scala:16:7] wire io_in_control_0_dataflow_0 = io_in_control_0_dataflow; // @[Tile.scala:16:7] wire io_in_control_0_propagate_0 = io_in_control_0_propagate; // @[Tile.scala:16:7] wire [4:0] io_in_control_0_shift_0 = io_in_control_0_shift; // @[Tile.scala:16:7] wire [2:0] io_in_id_0_0 = io_in_id_0; // @[Tile.scala:16:7] wire io_in_last_0_0 = io_in_last_0; // @[Tile.scala:16:7] wire io_in_valid_0_0 = io_in_valid_0; // @[Tile.scala:16:7] wire io_bad_dataflow = 1'h0; // @[Tile.scala:16:7, :17:14, :42:44] wire [7:0] io_out_a_0_0; // @[Tile.scala:16:7] wire [19:0] io_out_c_0_0; // @[Tile.scala:16:7] wire [19:0] io_out_b_0_0; // @[Tile.scala:16:7] wire io_out_control_0_dataflow_0; // @[Tile.scala:16:7] wire io_out_control_0_propagate_0; // @[Tile.scala:16:7] wire [4:0] io_out_control_0_shift_0; // @[Tile.scala:16:7] wire [2:0] io_out_id_0_0; // @[Tile.scala:16:7] wire io_out_last_0_0; // @[Tile.scala:16:7] wire io_out_valid_0_0; // @[Tile.scala:16:7] PE_486 tile_0_0 ( // @[Tile.scala:42:44] .clock (clock), .reset (reset), .io_in_a (io_in_a_0_0), // @[Tile.scala:16:7] .io_in_b (io_in_b_0_0), // @[Tile.scala:16:7] .io_in_d (io_in_d_0_0), // @[Tile.scala:16:7] .io_out_a (io_out_a_0_0), .io_out_b (io_out_b_0_0), .io_out_c (io_out_c_0_0), .io_in_control_dataflow (io_in_control_0_dataflow_0), // @[Tile.scala:16:7] .io_in_control_propagate (io_in_control_0_propagate_0), // @[Tile.scala:16:7] .io_in_control_shift (io_in_control_0_shift_0), // @[Tile.scala:16:7] .io_out_control_dataflow (io_out_control_0_dataflow_0), .io_out_control_propagate (io_out_control_0_propagate_0), .io_out_control_shift (io_out_control_0_shift_0), .io_in_id (io_in_id_0_0), // @[Tile.scala:16:7] .io_out_id (io_out_id_0_0), .io_in_last (io_in_last_0_0), // @[Tile.scala:16:7] .io_out_last (io_out_last_0_0), .io_in_valid (io_in_valid_0_0), // @[Tile.scala:16:7] .io_out_valid (io_out_valid_0_0) ); // @[Tile.scala:42:44] assign io_out_a_0 = io_out_a_0_0; // @[Tile.scala:16:7] assign io_out_c_0 = io_out_c_0_0; // @[Tile.scala:16:7] assign io_out_b_0 = io_out_b_0_0; // @[Tile.scala:16:7] assign io_out_control_0_dataflow = io_out_control_0_dataflow_0; // @[Tile.scala:16:7] assign io_out_control_0_propagate = io_out_control_0_propagate_0; // @[Tile.scala:16:7] assign io_out_control_0_shift = io_out_control_0_shift_0; // @[Tile.scala:16:7] assign io_out_id_0 = io_out_id_0_0; // @[Tile.scala:16:7] assign io_out_last_0 = io_out_last_0_0; // @[Tile.scala:16:7] assign io_out_valid_0 = io_out_valid_0_0; // @[Tile.scala:16:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File HellaCache.scala: // See LICENSE.SiFive for license details. // See LICENSE.Berkeley for license details. package freechips.rocketchip.rocket import chisel3.{dontTouch, _} import chisel3.util._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.bundlebridge._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.amba.AMBAProtField import freechips.rocketchip.diplomacy.{IdRange, TransferSizes, RegionType} import freechips.rocketchip.tile.{L1CacheParams, HasL1CacheParameters, HasCoreParameters, CoreBundle, HasNonDiplomaticTileParameters, BaseTile, HasTileParameters} import freechips.rocketchip.tilelink.{TLMasterParameters, TLClientNode, TLMasterPortParameters, TLEdgeOut, TLWidthWidget, TLFIFOFixer, ClientMetadata} import freechips.rocketchip.util.{Code, RandomReplacement, ParameterizedBundle} import freechips.rocketchip.util.{BooleanToAugmentedBoolean, IntToAugmentedInt} import scala.collection.mutable.ListBuffer case class DCacheParams( nSets: Int = 64, nWays: Int = 4, rowBits: Int = 64, subWordBits: Option[Int] = None, replacementPolicy: String = "random", nTLBSets: Int = 1, nTLBWays: Int = 32, nTLBBasePageSectors: Int = 4, nTLBSuperpages: Int = 4, tagECC: Option[String] = None, dataECC: Option[String] = None, dataECCBytes: Int = 1, nMSHRs: Int = 1, nSDQ: Int = 17, nRPQ: Int = 16, nMMIOs: Int = 1, blockBytes: Int = 64, separateUncachedResp: Boolean = false, acquireBeforeRelease: Boolean = false, pipelineWayMux: Boolean = false, clockGate: Boolean = false, scratch: Option[BigInt] = None) extends L1CacheParams { def tagCode: Code = Code.fromString(tagECC) def dataCode: Code = Code.fromString(dataECC) def dataScratchpadBytes: Int = scratch.map(_ => nSetsblockBytes).getOrElse(0) def replacement = new RandomReplacement(nWays) def silentDrop: Boolean = !acquireBeforeRelease require((!scratch.isDefined \|\| nWays == 1), "Scratchpad only allowed in direct-mapped cache.") require((!scratch.isDefined \|\| nMSHRs == 0), "Scratchpad only allowed in blocking cache.") if (scratch.isEmpty) require(isPow2(nSets), s"nSets($nSets) must be pow2") } trait HasL1HellaCacheParameters extends HasL1CacheParameters with HasCoreParameters { val cacheParams = tileParams.dcache.get val cfg = cacheParams def wordBits = coreDataBits def wordBytes = coreDataBytes def subWordBits = cacheParams.subWordBits.getOrElse(wordBits) def subWordBytes = subWordBits / 8 def wordOffBits = log2Up(wordBytes) def beatBytes = cacheBlockBytes / cacheDataBeats def beatWords = beatBytes / wordBytes def beatOffBits = log2Up(beatBytes) def idxMSB = untagBits-1 def idxLSB = blockOffBits def offsetmsb = idxLSB-1 def offsetlsb = wordOffBits def rowWords = rowBits/wordBits def doNarrowRead = coreDataBits nWays % rowBits == 0 def eccBytes = cacheParams.dataECCBytes val eccBits = cacheParams.dataECCBytes * 8 val encBits = cacheParams.dataCode.width(eccBits) val encWordBits = encBits * (wordBits / eccBits) def encDataBits = cacheParams.dataCode.width(coreDataBits) // NBDCache only def encRowBits = encDataBitsrowWords def lrscCycles = coreParams.lrscCycles // ISA requires 16-insn LRSC sequences to succeed def lrscBackoff = 3 // disallow LRSC reacquisition briefly def blockProbeAfterGrantCycles = 8 // give the processor some time to issue a request after a grant def nIOMSHRs = cacheParams.nMMIOs def maxUncachedInFlight = cacheParams.nMMIOs def dataScratchpadSize = cacheParams.dataScratchpadBytes require(rowBits >= coreDataBits, s"rowBits($rowBits) < coreDataBits($coreDataBits)") if (!usingDataScratchpad) require(rowBits == cacheDataBits, s"rowBits($rowBits) != cacheDataBits($cacheDataBits)") // would need offset addr for puts if data width < xlen require(xLen <= cacheDataBits, s"xLen($xLen) > cacheDataBits($cacheDataBits)") } abstract class L1HellaCacheModule(implicit val p: Parameters) extends Module with HasL1HellaCacheParameters abstract class L1HellaCacheBundle(implicit val p: Parameters) extends ParameterizedBundle()(p) with HasL1HellaCacheParameters /* Bundle definitions for HellaCache interfaces / trait HasCoreMemOp extends HasL1HellaCacheParameters { val addr = UInt(coreMaxAddrBits.W) val idx = (usingVM && untagBits > pgIdxBits).option(UInt(coreMaxAddrBits.W)) val tag = UInt((coreParams.dcacheReqTagBits + log2Ceil(dcacheArbPorts)).W) val cmd = UInt(M_SZ.W) val size = UInt(log2Ceil(coreDataBytes.log2 + 1).W) val signed = Bool() val dprv = UInt(PRV.SZ.W) val dv = Bool() } trait HasCoreData extends HasCoreParameters { val data = UInt(coreDataBits.W) val mask = UInt(coreDataBytes.W) } class HellaCacheReqInternal(implicit p: Parameters) extends CoreBundle()(p) with HasCoreMemOp { val phys = Bool() val no_resp = Bool() // The dcache may omit generating a response for this request val no_alloc = Bool() val no_xcpt = Bool() } class HellaCacheReq(implicit p: Parameters) extends HellaCacheReqInternal()(p) with HasCoreData class HellaCacheResp(implicit p: Parameters) extends CoreBundle()(p) with HasCoreMemOp with HasCoreData { val replay = Bool() val has_data = Bool() val data_word_bypass = UInt(coreDataBits.W) val data_raw = UInt(coreDataBits.W) val store_data = UInt(coreDataBits.W) } class AlignmentExceptions extends Bundle { val ld = Bool() val st = Bool() } class HellaCacheExceptions extends Bundle { val ma = new AlignmentExceptions val pf = new AlignmentExceptions val gf = new AlignmentExceptions val ae = new AlignmentExceptions } class HellaCacheWriteData(implicit p: Parameters) extends CoreBundle()(p) with HasCoreData class HellaCachePerfEvents extends Bundle { val acquire = Bool() val release = Bool() val grant = Bool() val tlbMiss = Bool() val blocked = Bool() val canAcceptStoreThenLoad = Bool() val canAcceptStoreThenRMW = Bool() val canAcceptLoadThenLoad = Bool() val storeBufferEmptyAfterLoad = Bool() val storeBufferEmptyAfterStore = Bool() } // interface between D$ and processor/DTLB class HellaCacheIO(implicit p: Parameters) extends CoreBundle()(p) { val req = Decoupled(new HellaCacheReq) val s1_kill = Output(Bool()) // kill previous cycle's req val s1_data = Output(new HellaCacheWriteData()) // data for previous cycle's req val s2_nack = Input(Bool()) // req from two cycles ago is rejected val s2_nack_cause_raw = Input(Bool()) // reason for nack is store-load RAW hazard (performance hint) val s2_kill = Output(Bool()) // kill req from two cycles ago val s2_uncached = Input(Bool()) // advisory signal that the access is MMIO val s2_paddr = Input(UInt(paddrBits.W)) // translated address val resp = Flipped(Valid(new HellaCacheResp)) val replay_next = Input(Bool()) val s2_xcpt = Input(new HellaCacheExceptions) val s2_gpa = Input(UInt(vaddrBitsExtended.W)) val s2_gpa_is_pte = Input(Bool()) val uncached_resp = tileParams.dcache.get.separateUncachedResp.option(Flipped(Decoupled(new HellaCacheResp))) val ordered = Input(Bool()) val store_pending = Input(Bool()) // there is a store in a store buffer somewhere val perf = Input(new HellaCachePerfEvents()) val keep_clock_enabled = Output(Bool()) // should D$ avoid clock-gating itself? val clock_enabled = Input(Bool()) // is D$ currently being clocked? } /* Base classes for Diplomatic TL2 HellaCaches / abstract class HellaCache(tileId: Int)(implicit p: Parameters) extends LazyModule with HasNonDiplomaticTileParameters { protected val cfg = tileParams.dcache.get protected def cacheClientParameters = cfg.scratch.map(x => Seq()).getOrElse(Seq(TLMasterParameters.v1( name = s"Core ${tileId} DCache", sourceId = IdRange(0, 1 max cfg.nMSHRs), supportsProbe = TransferSizes(cfg.blockBytes, cfg.blockBytes)))) protected def mmioClientParameters = Seq(TLMasterParameters.v1( name = s"Core ${tileId} DCache MMIO", sourceId = IdRange(firstMMIO, firstMMIO + cfg.nMMIOs), requestFifo = true)) def firstMMIO = (cacheClientParameters.map(_.sourceId.end) :+ 0).max val node = TLClientNode(Seq(TLMasterPortParameters.v1( clients = cacheClientParameters ++ mmioClientParameters, minLatency = 1, requestFields = tileParams.core.useVM.option(Seq()).getOrElse(Seq(AMBAProtField()))))) val hartIdSinkNodeOpt = cfg.scratch.map(_ => BundleBridgeSink[UInt]()) val mmioAddressPrefixSinkNodeOpt = cfg.scratch.map(_ => BundleBridgeSink[UInt]()) val module: HellaCacheModule def flushOnFenceI = cfg.scratch.isEmpty && !node.edges.out(0).manager.managers.forall(m => !m.supportsAcquireB \|\| !m.executable \|\| m.regionType >= RegionType.TRACKED \|\| m.regionType <= RegionType.IDEMPOTENT) def canSupportCFlushLine = !usingVM \|\| cfg.blockBytes cfg.nSets <= (1 << pgIdxBits) require(!tileParams.core.haveCFlush \|\| cfg.scratch.isEmpty, "CFLUSH_D_L1 instruction requires a D$") } class HellaCacheBundle(implicit p: Parameters) extends CoreBundle()(p) { val cpu = Flipped(new HellaCacheIO) val ptw = new TLBPTWIO() val errors = new DCacheErrors val tlb_port = new DCacheTLBPort } class HellaCacheModule(outer: HellaCache) extends LazyModuleImp(outer) with HasL1HellaCacheParameters { implicit val edge: TLEdgeOut = outer.node.edges.out(0) val (tl_out, _) = outer.node.out(0) val io = IO(new HellaCacheBundle) val io_hartid = outer.hartIdSinkNodeOpt.map(_.bundle) val io_mmio_address_prefix = outer.mmioAddressPrefixSinkNodeOpt.map(_.bundle) dontTouch(io.cpu.resp) // Users like to monitor these fields even if the core ignores some signals dontTouch(io.cpu.s1_data) require(rowBits == edge.bundle.dataBits) private val fifoManagers = edge.manager.managers.filter(TLFIFOFixer.allVolatile) fifoManagers.foreach { m => require (m.fifoId == fifoManagers.head.fifoId, s"IOMSHRs must be FIFO for all regions with effects, but HellaCache sees\n"+ s"${m.nodePath.map(_.name)}\nversus\n${fifoManagers.head.nodePath.map(_.name)}") } } /** Support overriding which HellaCache is instantiated / case object BuildHellaCache extends Field[BaseTile => Parameters => HellaCache](HellaCacheFactory.apply) object HellaCacheFactory { def apply(tile: BaseTile)(p: Parameters): HellaCache = { if (tile.tileParams.dcache.get.nMSHRs == 0) new DCache(tile.tileId, tile.crossing)(p) else new NonBlockingDCache(tile.tileId)(p) } } /* Mix-ins for constructing tiles that have a HellaCache / trait HasHellaCache { this: BaseTile => val module: HasHellaCacheModule implicit val p: Parameters var nDCachePorts = 0 lazy val dcache: HellaCache = LazyModule(p(BuildHellaCache)(this)(p)) tlMasterXbar.node := TLWidthWidget(tileParams.dcache.get.rowBits/8) := dcache.node dcache.hartIdSinkNodeOpt.map { _ := hartIdNexusNode } dcache.mmioAddressPrefixSinkNodeOpt.map { _ := mmioAddressPrefixNexusNode } InModuleBody { dcache.module.io.tlb_port := DontCare } } trait HasHellaCacheModule { val outer: HasHellaCache with HasTileParameters implicit val p: Parameters val dcachePorts = ListBuffer[HellaCacheIO]() val dcacheArb = Module(new HellaCacheArbiter(outer.nDCachePorts)(outer.p)) outer.dcache.module.io.cpu <> dcacheArb.io.mem } /* Metadata array used for all HellaCaches / class L1Metadata(implicit p: Parameters) extends L1HellaCacheBundle()(p) { val coh = new ClientMetadata val tag = UInt(tagBits.W) } object L1Metadata { def apply(tag: Bits, coh: ClientMetadata)(implicit p: Parameters) = { val meta = Wire(new L1Metadata) meta.tag := tag meta.coh := coh meta } } class L1MetaReadReq(implicit p: Parameters) extends L1HellaCacheBundle()(p) { val idx = UInt(idxBits.W) val way_en = UInt(nWays.W) val tag = UInt(tagBits.W) } class L1MetaWriteReq(implicit p: Parameters) extends L1MetaReadReq()(p) { val data = new L1Metadata } class L1MetadataArray[T <: L1Metadata](onReset: () => T)(implicit p: Parameters) extends L1HellaCacheModule()(p) { val rstVal = onReset() val io = IO(new Bundle { val read = Flipped(Decoupled(new L1MetaReadReq)) val write = Flipped(Decoupled(new L1MetaWriteReq)) val resp = Output(Vec(nWays, rstVal.cloneType)) }) val rst_cnt = RegInit(0.U(log2Up(nSets+1).W)) val rst = rst_cnt < nSets.U val waddr = Mux(rst, rst_cnt, io.write.bits.idx) val wdata = Mux(rst, rstVal, io.write.bits.data).asUInt val wmask = Mux(rst \|\| (nWays == 1).B, (-1).S, io.write.bits.way_en.asSInt).asBools val rmask = Mux(rst \|\| (nWays == 1).B, (-1).S, io.read.bits.way_en.asSInt).asBools when (rst) { rst_cnt := rst_cnt+1.U } val metabits = rstVal.getWidth val tag_array = SyncReadMem(nSets, Vec(nWays, UInt(metabits.W))) val wen = rst \|\| io.write.valid when (wen) { tag_array.write(waddr, VecInit.fill(nWays)(wdata), wmask) } io.resp := tag_array.read(io.read.bits.idx, io.read.fire).map(_.asTypeOf(chiselTypeOf(rstVal))) io.read.ready := !wen // so really this could be a 6T RAM io.write.ready := !rst } File Interrupts.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tile import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import freechips.rocketchip.resources.{Device, DeviceSnippet, Description, ResourceBinding, ResourceInt} import freechips.rocketchip.interrupts.{IntIdentityNode, IntSinkNode, IntSinkPortSimple, IntSourceNode, IntSourcePortSimple} import freechips.rocketchip.util.CanHaveErrors import freechips.rocketchip.resources.{IntToProperty, StringToProperty} import freechips.rocketchip.util.BooleanToAugmentedBoolean class NMI(val w: Int) extends Bundle { val rnmi = Bool() val rnmi_interrupt_vector = UInt(w.W) val rnmi_exception_vector = UInt(w.W) } class TileInterrupts(implicit p: Parameters) extends CoreBundle()(p) { val debug = Bool() val mtip = Bool() val msip = Bool() val meip = Bool() val seip = usingSupervisor.option(Bool()) val lip = Vec(coreParams.nLocalInterrupts, Bool()) val nmi = usingNMI.option(new NMI(resetVectorLen)) } // Use diplomatic interrupts to external interrupts from the subsystem into the tile trait SinksExternalInterrupts { this: BaseTile => val intInwardNode = intXbar.intnode := IntIdentityNode()(ValName("int_local")) protected val intSinkNode = IntSinkNode(IntSinkPortSimple()) intSinkNode := intXbar.intnode def cpuDevice: Device val intcDevice = new DeviceSnippet { override def parent = Some(cpuDevice) def describe(): Description = { Description("interrupt-controller", Map( "compatible" -> "riscv,cpu-intc".asProperty, "interrupt-controller" -> Nil, "#interrupt-cells" -> 1.asProperty)) } } ResourceBinding { intSinkNode.edges.in.flatMap(_.source.sources).map { case s => for (i <- s.range.start until s.range.end) { csrIntMap.lift(i).foreach { j => s.resources.foreach { r => r.bind(intcDevice, ResourceInt(j)) } } } } } // TODO: the order of the following two functions must match, and // also match the order which things are connected to the // per-tile crossbar in subsystem.HasTiles.connectInterrupts // debug, msip, mtip, meip, seip, lip offsets in CSRs def csrIntMap: List[Int] = { val nlips = tileParams.core.nLocalInterrupts val seip = if (usingSupervisor) Seq(9) else Nil List(65535, 3, 7, 11) ++ seip ++ List.tabulate(nlips)(_ + 16) } // go from flat diplomatic Interrupts to bundled TileInterrupts def decodeCoreInterrupts(core: TileInterrupts): Unit = { val async_ips = Seq(core.debug) val periph_ips = Seq( core.msip, core.mtip, core.meip) val seip = if (core.seip.isDefined) Seq(core.seip.get) else Nil val core_ips = core.lip val (interrupts, _) = intSinkNode.in(0) (async_ips ++ periph_ips ++ seip ++ core_ips).zip(interrupts).foreach { case(c, i) => c := i } } } trait SourcesExternalNotifications { this: BaseTile => // Report unrecoverable error conditions val haltNode = IntSourceNode(IntSourcePortSimple()) def reportHalt(could_halt: Option[Bool]): Unit = { val (halt_and_catch_fire, _) = haltNode.out(0) halt_and_catch_fire(0) := could_halt.map(RegEnable(true.B, false.B, _)).getOrElse(false.B) } def reportHalt(errors: Seq[CanHaveErrors]): Unit = { reportHalt(errors.flatMap(_.uncorrectable).map(_.valid).reduceOption(_\|\|_)) } // Report when the tile has ceased to retire instructions val ceaseNode = IntSourceNode(IntSourcePortSimple()) def reportCease(could_cease: Option[Bool], quiescenceCycles: Int = 8): Unit = { def waitForQuiescence(cease: Bool): Bool = { // don't report cease until signal is stable for longer than any pipeline depth val count = RegInit(0.U(log2Ceil(quiescenceCycles + 1).W)) val saturated = count >= quiescenceCycles.U when (!cease) { count := 0.U } when (cease && !saturated) { count := count + 1.U } saturated } val (cease, _) = ceaseNode.out(0) cease(0) := could_cease.map{ c => val cease = (waitForQuiescence(c)) // Test-Only Code -- val prev_cease = RegNext(cease, false.B) assert(!(prev_cease & !cease), "CEASE line can not glitch once raised") cease }.getOrElse(false.B) } // Report when the tile is waiting for an interrupt val wfiNode = IntSourceNode(IntSourcePortSimple()) def reportWFI(could_wfi: Option[Bool]): Unit = { val (wfi, _) = wfiNode.out(0) wfi(0) := could_wfi.map(RegNext(_, init=false.B)).getOrElse(false.B) } } File Frontend.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.rocket import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.bundlebridge._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.tile.{CoreBundle, BaseTile} import freechips.rocketchip.tilelink.{TLWidthWidget, TLEdgeOut} import freechips.rocketchip.util.{ClockGate, ShiftQueue, property} import freechips.rocketchip.util.UIntToAugmentedUInt class FrontendReq(implicit p: Parameters) extends CoreBundle()(p) { val pc = UInt(vaddrBitsExtended.W) val speculative = Bool() } class FrontendExceptions extends Bundle { val pf = new Bundle { val inst = Bool() } val gf = new Bundle { val inst = Bool() } val ae = new Bundle { val inst = Bool() } } class FrontendResp(implicit p: Parameters) extends CoreBundle()(p) { val btb = new BTBResp val pc = UInt(vaddrBitsExtended.W) // ID stage PC val data = UInt((fetchWidth * coreInstBits).W) val mask = Bits(fetchWidth.W) val xcpt = new FrontendExceptions val replay = Bool() } class FrontendPerfEvents extends Bundle { val acquire = Bool() val tlbMiss = Bool() } class FrontendIO(implicit p: Parameters) extends CoreBundle()(p) { val might_request = Output(Bool()) val clock_enabled = Input(Bool()) val req = Valid(new FrontendReq) val sfence = Valid(new SFenceReq) val resp = Flipped(Decoupled(new FrontendResp)) val gpa = Flipped(Valid(UInt(vaddrBitsExtended.W))) val gpa_is_pte = Input(Bool()) val btb_update = Valid(new BTBUpdate) val bht_update = Valid(new BHTUpdate) val ras_update = Valid(new RASUpdate) val flush_icache = Output(Bool()) val npc = Input(UInt(vaddrBitsExtended.W)) val perf = Input(new FrontendPerfEvents()) val progress = Output(Bool()) } class Frontend(val icacheParams: ICacheParams, tileId: Int)(implicit p: Parameters) extends LazyModule { lazy val module = new FrontendModule(this) val icache = LazyModule(new ICache(icacheParams, tileId)) val masterNode = icache.masterNode val slaveNode = icache.slaveNode val resetVectorSinkNode = BundleBridgeSink[UInt](Some(() => UInt(masterNode.edges.out.head.bundle.addressBits.W))) } class FrontendBundle(val outer: Frontend) extends CoreBundle()(outer.p) { val cpu = Flipped(new FrontendIO()) val ptw = new TLBPTWIO() val errors = new ICacheErrors } class FrontendModule(outer: Frontend) extends LazyModuleImp(outer) with HasRocketCoreParameters with HasL1ICacheParameters { val io = IO(new FrontendBundle(outer)) val io_reset_vector = outer.resetVectorSinkNode.bundle implicit val edge: TLEdgeOut = outer.masterNode.edges.out(0) val icache = outer.icache.module require(fetchWidthcoreInstBytes == outer.icacheParams.fetchBytes) val fq = withReset(reset.asBool \|\| io.cpu.req.valid) { Module(new ShiftQueue(new FrontendResp, 5, flow = true)) } val clock_en_reg = Reg(Bool()) val clock_en = clock_en_reg \|\| io.cpu.might_request io.cpu.clock_enabled := clock_en assert(!(io.cpu.req.valid \|\| io.cpu.sfence.valid \|\| io.cpu.flush_icache \|\| io.cpu.bht_update.valid \|\| io.cpu.btb_update.valid) \|\| io.cpu.might_request) val gated_clock = if (!rocketParams.clockGate) clock else ClockGate(clock, clock_en, "icache_clock_gate") icache.clock := gated_clock icache.io.clock_enabled := clock_en withClock (gated_clock) { // entering gated-clock domain val tlb = Module(new TLB(true, log2Ceil(fetchBytes), TLBConfig(nTLBSets, nTLBWays, outer.icacheParams.nTLBBasePageSectors, outer.icacheParams.nTLBSuperpages))) val s1_valid = Reg(Bool()) val s2_valid = RegInit(false.B) val s0_fq_has_space = !fq.io.mask(fq.io.mask.getWidth-3) \|\| (!fq.io.mask(fq.io.mask.getWidth-2) && (!s1_valid \|\| !s2_valid)) \|\| (!fq.io.mask(fq.io.mask.getWidth-1) && (!s1_valid && !s2_valid)) val s0_valid = io.cpu.req.valid \|\| s0_fq_has_space s1_valid := s0_valid val s1_pc = Reg(UInt(vaddrBitsExtended.W)) val s1_speculative = Reg(Bool()) val s2_pc = RegInit(t = UInt(vaddrBitsExtended.W), alignPC(io_reset_vector)) val s2_btb_resp_valid = if (usingBTB) Reg(Bool()) else false.B val s2_btb_resp_bits = Reg(new BTBResp) val s2_btb_taken = s2_btb_resp_valid && s2_btb_resp_bits.taken val s2_tlb_resp = Reg(tlb.io.resp.cloneType) val s2_xcpt = s2_tlb_resp.ae.inst \|\| s2_tlb_resp.pf.inst \|\| s2_tlb_resp.gf.inst val s2_speculative = RegInit(false.B) val s2_partial_insn_valid = RegInit(false.B) val s2_partial_insn = Reg(UInt(coreInstBits.W)) val wrong_path = RegInit(false.B) val s1_base_pc = ~(~s1_pc \| (fetchBytes - 1).U) val ntpc = s1_base_pc + fetchBytes.U val predicted_npc = WireDefault(ntpc) val predicted_taken = WireDefault(false.B) val s2_replay = Wire(Bool()) s2_replay := (s2_valid && !fq.io.enq.fire) \|\| RegNext(s2_replay && !s0_valid, true.B) val npc = Mux(s2_replay, s2_pc, predicted_npc) s1_pc := io.cpu.npc // consider RVC fetches across blocks to be non-speculative if the first // part was non-speculative val s0_speculative = if (usingCompressed) s1_speculative \|\| s2_valid && !s2_speculative \|\| predicted_taken else true.B s1_speculative := Mux(io.cpu.req.valid, io.cpu.req.bits.speculative, Mux(s2_replay, s2_speculative, s0_speculative)) val s2_redirect = WireDefault(io.cpu.req.valid) s2_valid := false.B when (!s2_replay) { s2_valid := !s2_redirect s2_pc := s1_pc s2_speculative := s1_speculative s2_tlb_resp := tlb.io.resp } val recent_progress_counter_init = 3.U val recent_progress_counter = RegInit(recent_progress_counter_init) val recent_progress = recent_progress_counter > 0.U when(io.ptw.req.fire && recent_progress) { recent_progress_counter := recent_progress_counter - 1.U } when(io.cpu.progress) { recent_progress_counter := recent_progress_counter_init } val s2_kill_speculative_tlb_refill = s2_speculative && !recent_progress io.ptw <> tlb.io.ptw tlb.io.req.valid := s1_valid && !s2_replay tlb.io.req.bits.cmd := M_XRD // Frontend only reads tlb.io.req.bits.vaddr := s1_pc tlb.io.req.bits.passthrough := false.B tlb.io.req.bits.size := log2Ceil(coreInstBytesfetchWidth).U tlb.io.req.bits.prv := io.ptw.status.prv tlb.io.req.bits.v := io.ptw.status.v tlb.io.sfence := io.cpu.sfence tlb.io.kill := !s2_valid \|\| s2_kill_speculative_tlb_refill icache.io.req.valid := s0_valid icache.io.req.bits.addr := io.cpu.npc icache.io.invalidate := io.cpu.flush_icache icache.io.s1_paddr := tlb.io.resp.paddr icache.io.s2_vaddr := s2_pc icache.io.s1_kill := s2_redirect \|\| tlb.io.resp.miss \|\| s2_replay val s2_can_speculatively_refill = s2_tlb_resp.cacheable && !io.ptw.customCSRs.asInstanceOf[RocketCustomCSRs].disableSpeculativeICacheRefill icache.io.s2_kill := s2_speculative && !s2_can_speculatively_refill \|\| s2_xcpt icache.io.s2_cacheable := s2_tlb_resp.cacheable icache.io.s2_prefetch := s2_tlb_resp.prefetchable && !io.ptw.customCSRs.asInstanceOf[RocketCustomCSRs].disableICachePrefetch fq.io.enq.valid := RegNext(s1_valid) && s2_valid && (icache.io.resp.valid \|\| (s2_kill_speculative_tlb_refill && s2_tlb_resp.miss) \|\| (!s2_tlb_resp.miss && icache.io.s2_kill)) fq.io.enq.bits.pc := s2_pc io.cpu.npc := alignPC(Mux(io.cpu.req.valid, io.cpu.req.bits.pc, npc)) fq.io.enq.bits.data := icache.io.resp.bits.data fq.io.enq.bits.mask := ((1 << fetchWidth)-1).U << s2_pc.extract(log2Ceil(fetchWidth)+log2Ceil(coreInstBytes)-1, log2Ceil(coreInstBytes)) fq.io.enq.bits.replay := (icache.io.resp.bits.replay \|\| icache.io.s2_kill && !icache.io.resp.valid && !s2_xcpt) \|\| (s2_kill_speculative_tlb_refill && s2_tlb_resp.miss) fq.io.enq.bits.btb := s2_btb_resp_bits fq.io.enq.bits.btb.taken := s2_btb_taken fq.io.enq.bits.xcpt := s2_tlb_resp assert(!(s2_speculative && io.ptw.customCSRs.asInstanceOf[RocketCustomCSRs].disableSpeculativeICacheRefill && !icache.io.s2_kill)) when (icache.io.resp.valid && icache.io.resp.bits.ae) { fq.io.enq.bits.xcpt.ae.inst := true.B } if (usingBTB) { val btb = Module(new BTB) btb.io.flush := false.B btb.io.req.valid := false.B btb.io.req.bits.addr := s1_pc btb.io.btb_update := io.cpu.btb_update btb.io.bht_update := io.cpu.bht_update btb.io.ras_update.valid := false.B btb.io.ras_update.bits := DontCare btb.io.bht_advance.valid := false.B btb.io.bht_advance.bits := DontCare when (!s2_replay) { btb.io.req.valid := !s2_redirect s2_btb_resp_valid := btb.io.resp.valid s2_btb_resp_bits := btb.io.resp.bits } when (btb.io.resp.valid && btb.io.resp.bits.taken) { predicted_npc := btb.io.resp.bits.target.sextTo(vaddrBitsExtended) predicted_taken := true.B } val force_taken = io.ptw.customCSRs.bpmStatic when (io.ptw.customCSRs.flushBTB) { btb.io.flush := true.B } when (force_taken) { btb.io.bht_update.valid := false.B } val s2_base_pc = ~(~s2_pc \| (fetchBytes-1).U) val taken_idx = Wire(UInt()) val after_idx = Wire(UInt()) val useRAS = WireDefault(false.B) val updateBTB = WireDefault(false.B) // If !prevTaken, ras_update / bht_update is always invalid. taken_idx := DontCare after_idx := DontCare def scanInsns(idx: Int, prevValid: Bool, prevBits: UInt, prevTaken: Bool): Bool = { def insnIsRVC(bits: UInt) = bits(1,0) =/= 3.U val prevRVI = prevValid && !insnIsRVC(prevBits) val valid = fq.io.enq.bits.mask(idx) && !prevRVI val bits = fq.io.enq.bits.data(coreInstBits(idx+1)-1, coreInstBitsidx) val rvc = insnIsRVC(bits) val rviBits = Cat(bits, prevBits) val rviBranch = rviBits(6,0) === Instructions.BEQ.value.U.extract(6,0) val rviJump = rviBits(6,0) === Instructions.JAL.value.U.extract(6,0) val rviJALR = rviBits(6,0) === Instructions.JALR.value.U.extract(6,0) val rviReturn = rviJALR && !rviBits(7) && BitPat("b00?01") === rviBits(19,15) val rviCall = (rviJALR \|\| rviJump) && rviBits(7) val rvcBranch = bits === Instructions.C_BEQZ \|\| bits === Instructions.C_BNEZ val rvcJAL = (xLen == 32).B && bits === Instructions32.C_JAL val rvcJump = bits === Instructions.C_J \|\| rvcJAL val rvcImm = Mux(bits(14), new RVCDecoder(bits, xLen, fLen).bImm.asSInt, new RVCDecoder(bits, xLen, fLen).jImm.asSInt) val rvcJR = bits === Instructions.C_MV && bits(6,2) === 0.U val rvcReturn = rvcJR && BitPat("b00?01") === bits(11,7) val rvcJALR = bits === Instructions.C_ADD && bits(6,2) === 0.U val rvcCall = rvcJAL \|\| rvcJALR val rviImm = Mux(rviBits(3), ImmGen(IMM_UJ, rviBits), ImmGen(IMM_SB, rviBits)) val predict_taken = s2_btb_resp_bits.bht.taken \|\| force_taken val taken = prevRVI && (rviJump \|\| rviJALR \|\| rviBranch && predict_taken) \|\| valid && (rvcJump \|\| rvcJALR \|\| rvcJR \|\| rvcBranch && predict_taken) val predictReturn = btb.io.ras_head.valid && (prevRVI && rviReturn \|\| valid && rvcReturn) val predictJump = prevRVI && rviJump \|\| valid && rvcJump val predictBranch = predict_taken && (prevRVI && rviBranch \|\| valid && rvcBranch) when (s2_valid && s2_btb_resp_valid && s2_btb_resp_bits.bridx === idx.U && valid && !rvc) { // The BTB has predicted that the middle of an RVI instruction is // a branch! Flush the BTB and the pipeline. btb.io.flush := true.B fq.io.enq.bits.replay := true.B wrong_path := true.B ccover(wrong_path, "BTB_NON_CFI_ON_WRONG_PATH", "BTB predicted a non-branch was taken while on the wrong path") } when (!prevTaken) { taken_idx := idx.U after_idx := (idx + 1).U btb.io.ras_update.valid := fq.io.enq.fire && !wrong_path && (prevRVI && (rviCall \|\| rviReturn) \|\| valid && (rvcCall \|\| rvcReturn)) btb.io.ras_update.bits.cfiType := Mux(Mux(prevRVI, rviReturn, rvcReturn), CFIType.ret, Mux(Mux(prevRVI, rviCall, rvcCall), CFIType.call, Mux(Mux(prevRVI, rviBranch, rvcBranch) && !force_taken, CFIType.branch, CFIType.jump))) when (!s2_btb_taken) { when (fq.io.enq.fire && taken && !predictBranch && !predictJump && !predictReturn) { wrong_path := true.B } when (s2_valid && predictReturn) { useRAS := true.B } when (s2_valid && (predictBranch \|\| predictJump)) { val pc = s2_base_pc \| (idxcoreInstBytes).U val npc = if (idx == 0) pc.asSInt + Mux(prevRVI, rviImm -& 2.S, rvcImm) else Mux(prevRVI, pc - coreInstBytes.U, pc).asSInt + Mux(prevRVI, rviImm, rvcImm) predicted_npc := npc.asUInt } } when (prevRVI && rviBranch \|\| valid && rvcBranch) { btb.io.bht_advance.valid := fq.io.enq.fire && !wrong_path btb.io.bht_advance.bits := s2_btb_resp_bits } when (!s2_btb_resp_valid && (predictBranch && s2_btb_resp_bits.bht.strongly_taken \|\| predictJump \|\| predictReturn)) { updateBTB := true.B } } if (idx == fetchWidth-1) { when (fq.io.enq.fire) { s2_partial_insn_valid := false.B when (valid && !prevTaken && !rvc) { s2_partial_insn_valid := true.B s2_partial_insn := bits \| 0x3.U } } prevTaken \|\| taken } else { scanInsns(idx + 1, valid, bits, prevTaken \|\| taken) } } when (!io.cpu.btb_update.valid) { val fetch_bubble_likely = !fq.io.mask(1) btb.io.btb_update.valid := fq.io.enq.fire && !wrong_path && fetch_bubble_likely && updateBTB btb.io.btb_update.bits.prediction.entry := tileParams.btb.get.nEntries.U btb.io.btb_update.bits.isValid := true.B btb.io.btb_update.bits.cfiType := btb.io.ras_update.bits.cfiType btb.io.btb_update.bits.br_pc := s2_base_pc \| (taken_idx << log2Ceil(coreInstBytes)) btb.io.btb_update.bits.pc := s2_base_pc } btb.io.ras_update.bits.returnAddr := s2_base_pc + (after_idx << log2Ceil(coreInstBytes)) val taken = scanInsns(0, s2_partial_insn_valid, s2_partial_insn, false.B) when (useRAS) { predicted_npc := btb.io.ras_head.bits } when (fq.io.enq.fire && (s2_btb_taken \|\| taken)) { s2_partial_insn_valid := false.B } when (!s2_btb_taken) { when (taken) { fq.io.enq.bits.btb.bridx := taken_idx fq.io.enq.bits.btb.taken := true.B fq.io.enq.bits.btb.entry := tileParams.btb.get.nEntries.U when (fq.io.enq.fire) { s2_redirect := true.B } } } assert(!s2_partial_insn_valid \|\| fq.io.enq.bits.mask(0)) when (s2_redirect) { s2_partial_insn_valid := false.B } when (io.cpu.req.valid) { wrong_path := false.B } } io.cpu.resp <> fq.io.deq // supply guest physical address to commit stage val gpa_valid = Reg(Bool()) val gpa = Reg(UInt(vaddrBitsExtended.W)) val gpa_is_pte = Reg(Bool()) when (fq.io.enq.fire && s2_tlb_resp.gf.inst) { when (!gpa_valid) { gpa := s2_tlb_resp.gpa gpa_is_pte := s2_tlb_resp.gpa_is_pte } gpa_valid := true.B } when (io.cpu.req.valid) { gpa_valid := false.B } io.cpu.gpa.valid := gpa_valid io.cpu.gpa.bits := gpa io.cpu.gpa_is_pte := gpa_is_pte // performance events io.cpu.perf.acquire := icache.io.perf.acquire io.cpu.perf.tlbMiss := io.ptw.req.fire io.errors := icache.io.errors // gate the clock clock_en_reg := !rocketParams.clockGate.B \|\| io.cpu.might_request \|\| // chicken bit icache.io.keep_clock_enabled \|\| // I$ miss or ITIM access s1_valid \|\| s2_valid \|\| // some fetch in flight !tlb.io.req.ready \|\| // handling TLB miss !fq.io.mask(fq.io.mask.getWidth-1) // queue not full } // leaving gated-clock domain def alignPC(pc: UInt) = ~(~pc \| (coreInstBytes - 1).U) def ccover(cond: Bool, label: String, desc: String)(implicit sourceInfo: SourceInfo) = property.cover(cond, s"FRONTEND_$label", "Rocket;;" + desc) } /* Mix-ins for constructing tiles that have an ICache-based pipeline frontend / trait HasICacheFrontend extends CanHavePTW { this: BaseTile => val module: HasICacheFrontendModule val frontend = LazyModule(new Frontend(tileParams.icache.get, tileId)) tlMasterXbar.node := TLWidthWidget(tileParams.icache.get.rowBits/8) := frontend.masterNode connectTLSlave(frontend.slaveNode, tileParams.core.fetchBytes) frontend.icache.hartIdSinkNodeOpt.foreach { _ := hartIdNexusNode } frontend.icache.mmioAddressPrefixSinkNodeOpt.foreach { _ := mmioAddressPrefixNexusNode } frontend.resetVectorSinkNode := resetVectorNexusNode nPTWPorts += 1 // This should be a None in the case of not having an ITIM address, when we // don't actually use the device that is instantiated in the frontend. private val deviceOpt = if (tileParams.icache.get.itimAddr.isDefined) Some(frontend.icache.device) else None } trait HasICacheFrontendModule extends CanHavePTWModule { val outer: HasICacheFrontend ptwPorts += outer.frontend.module.io.ptw } File LazyModuleImp.scala: package org.chipsalliance.diplomacy.lazymodule import chisel3.{withClockAndReset, Module, RawModule, Reset, _} import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo} import firrtl.passes.InlineAnnotation import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.nodes.Dangle import scala.collection.immutable.SortedMap /* Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]]. * * This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy. / sealed trait LazyModuleImpLike extends RawModule { /* [[LazyModule]] that contains this instance. / val wrapper: LazyModule /* IOs that will be automatically "punched" for this instance. / val auto: AutoBundle /* The metadata that describes the [[HalfEdge]]s which generated [[auto]]. / protected[diplomacy] val dangles: Seq[Dangle] // [[wrapper.module]] had better not be accessed while LazyModules are still being built! require( LazyModule.scope.isEmpty, s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}" ) /* Set module name. Defaults to the containing LazyModule's desiredName. / override def desiredName: String = wrapper.desiredName suggestName(wrapper.suggestedName) /* [[Parameters]] for chisel [[Module]]s. / implicit val p: Parameters = wrapper.p /* instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and * submodules. / protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = { // 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]], // 2. return [[Dangle]]s from each module. val childDangles = wrapper.children.reverse.flatMap { c => implicit val sourceInfo: SourceInfo = c.info c.cloneProto.map { cp => // If the child is a clone, then recursively set cloneProto of its children as well def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = { require(bases.size == clones.size) (bases.zip(clones)).map { case (l, r) => require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}") l.cloneProto = Some(r) assignCloneProtos(l.children, r.children) } } assignCloneProtos(c.children, cp.children) // Clone the child module as a record, and get its [[AutoBundle]] val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName) val clonedAuto = clone("auto").asInstanceOf[AutoBundle] // Get the empty [[Dangle]]'s of the cloned child val rawDangles = c.cloneDangles() require(rawDangles.size == clonedAuto.elements.size) // Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) } dangles }.getOrElse { // For non-clones, instantiate the child module val mod = try { Module(c.module) } catch { case e: ChiselException => { println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}") throw e } } mod.dangles } } // Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]]. // This will result in a sequence of [[Dangle]] from these [[BaseNode]]s. val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate()) // Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]] val allDangles = nodeDangles ++ childDangles // Group [[allDangles]] by their [[source]]. val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _) // For each [[source]] set of [[Dangle]]s of size 2, ensure that these // can be connected as a source-sink pair (have opposite flipped value). // Make the connection and mark them as [[done]]. val done = Set() ++ pairing.values.filter(_.size == 2).map { case Seq(a, b) => require(a.flipped != b.flipped) // @todo <> in chisel3 makes directionless connection. if (a.flipped) { a.data <> b.data } else { b.data <> a.data } a.source case _ => None } // Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module. val forward = allDangles.filter(d => !done(d.source)) // Generate [[AutoBundle]] IO from [[forward]]. val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _)) // Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]] val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) => if (d.flipped) { d.data <> io } else { io <> d.data } d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name) } // Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]]. wrapper.inModuleBody.reverse.foreach { _() } if (wrapper.shouldBeInlined) { chisel3.experimental.annotate(new ChiselAnnotation { def toFirrtl = InlineAnnotation(toNamed) }) } // Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]]. (auto, dangles) } } /* Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. / class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike { /* Instantiate hardware of this `Module`. / val (auto, dangles) = instantiate() } /* Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. / class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike { // These wires are the default clock+reset for all LazyModule children. // It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the // [[LazyRawModuleImp]] children. // Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly. /* drive clock explicitly. / val childClock: Clock = Wire(Clock()) /* drive reset explicitly. / val childReset: Reset = Wire(Reset()) // the default is that these are disabled childClock := false.B.asClock childReset := chisel3.DontCare def provideImplicitClockToLazyChildren: Boolean = false val (auto, dangles) = if (provideImplicitClockToLazyChildren) { withClockAndReset(childClock, childReset) { instantiate() } } else { instantiate() } } File PTW.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.rocket import chisel3._ import chisel3.util.{Arbiter, Cat, Decoupled, Enum, Mux1H, OHToUInt, PopCount, PriorityEncoder, PriorityEncoderOH, RegEnable, UIntToOH, Valid, is, isPow2, log2Ceil, switch} import chisel3.withClock import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.subsystem.CacheBlockBytes import freechips.rocketchip.tile._ import freechips.rocketchip.tilelink._ import freechips.rocketchip.util._ import freechips.rocketchip.util.property import scala.collection.mutable.ListBuffer /* PTE request from TLB to PTW * * TLB send a PTE request to PTW when L1TLB miss / class PTWReq(implicit p: Parameters) extends CoreBundle()(p) { val addr = UInt(vpnBits.W) val need_gpa = Bool() val vstage1 = Bool() val stage2 = Bool() } /* PTE info from L2TLB to TLB * * containing: target PTE, exceptions, two-satge tanslation info / class PTWResp(implicit p: Parameters) extends CoreBundle()(p) { /* ptw access exception / val ae_ptw = Bool() /* final access exception / val ae_final = Bool() /* page fault / val pf = Bool() /* guest page fault / val gf = Bool() /* hypervisor read / val hr = Bool() /* hypervisor write / val hw = Bool() /* hypervisor execute / val hx = Bool() /* PTE to refill L1TLB * * source: L2TLB / val pte = new PTE /* pte pglevel / val level = UInt(log2Ceil(pgLevels).W) /* fragmented_superpage support / val fragmented_superpage = Bool() /* homogeneous for both pma and pmp / val homogeneous = Bool() val gpa = Valid(UInt(vaddrBits.W)) val gpa_is_pte = Bool() } /* IO between TLB and PTW * * PTW receives : * - PTE request * - CSRs info * - pmp results from PMP(in TLB) / class TLBPTWIO(implicit p: Parameters) extends CoreBundle()(p) with HasCoreParameters { val req = Decoupled(Valid(new PTWReq)) val resp = Flipped(Valid(new PTWResp)) val ptbr = Input(new PTBR()) val hgatp = Input(new PTBR()) val vsatp = Input(new PTBR()) val status = Input(new MStatus()) val hstatus = Input(new HStatus()) val gstatus = Input(new MStatus()) val pmp = Input(Vec(nPMPs, new PMP)) val customCSRs = Flipped(coreParams.customCSRs) } /* PTW performance statistics / class PTWPerfEvents extends Bundle { val l2miss = Bool() val l2hit = Bool() val pte_miss = Bool() val pte_hit = Bool() } /* Datapath IO between PTW and Core * * PTW receives CSRs info, pmp checks, sfence instruction info * * PTW sends its performance statistics to core / class DatapathPTWIO(implicit p: Parameters) extends CoreBundle()(p) with HasCoreParameters { val ptbr = Input(new PTBR()) val hgatp = Input(new PTBR()) val vsatp = Input(new PTBR()) val sfence = Flipped(Valid(new SFenceReq)) val status = Input(new MStatus()) val hstatus = Input(new HStatus()) val gstatus = Input(new MStatus()) val pmp = Input(Vec(nPMPs, new PMP)) val perf = Output(new PTWPerfEvents()) val customCSRs = Flipped(coreParams.customCSRs) /* enable clock generated by ptw / val clock_enabled = Output(Bool()) } /* PTE template for transmission * * contains useful methods to check PTE attributes * @see RV-priv spec 4.3.1 for pgae table entry format / class PTE(implicit p: Parameters) extends CoreBundle()(p) { val reserved_for_future = UInt(10.W) val ppn = UInt(44.W) val reserved_for_software = Bits(2.W) /* dirty bit / val d = Bool() /* access bit / val a = Bool() /* global mapping / val g = Bool() /* user mode accessible / val u = Bool() /* whether the page is executable / val x = Bool() /* whether the page is writable / val w = Bool() /* whether the page is readable / val r = Bool() /* valid bit / val v = Bool() /* return true if find a pointer to next level page table / def table(dummy: Int = 0) = v && !r && !w && !x && !d && !a && !u && reserved_for_future === 0.U /* return true if find a leaf PTE / def leaf(dummy: Int = 0) = v && (r \|\| (x && !w)) && a /* user read / def ur(dummy: Int = 0) = sr() && u /* user write/ def uw(dummy: Int = 0) = sw() && u /* user execute / def ux(dummy: Int = 0) = sx() && u /* supervisor read / def sr(dummy: Int = 0) = leaf() && r /* supervisor write / def sw(dummy: Int = 0) = leaf() && w && d /* supervisor execute / def sx(dummy: Int = 0) = leaf() && x /* full permission: writable and executable in user mode / def isFullPerm(dummy: Int = 0) = uw() && ux() } /* L2TLB PTE template * * contains tag bits * @param nSets number of sets in L2TLB * @see RV-priv spec 4.3.1 for page table entry format / class L2TLBEntry(nSets: Int)(implicit p: Parameters) extends CoreBundle()(p) with HasCoreParameters { val idxBits = log2Ceil(nSets) val tagBits = maxSVAddrBits - pgIdxBits - idxBits + (if (usingHypervisor) 1 else 0) val tag = UInt(tagBits.W) val ppn = UInt(ppnBits.W) /* dirty bit / val d = Bool() /* access bit / val a = Bool() /* user mode accessible / val u = Bool() /* whether the page is executable / val x = Bool() /* whether the page is writable / val w = Bool() /* whether the page is readable / val r = Bool() } /* PTW contains L2TLB, and performs page table walk for high level TLB, and cache queries from L1 TLBs(I$, D$, RoCC) * * It performs hierarchy page table query to mem for the desired leaf PTE and cache them in l2tlb. * Besides leaf PTEs, it also caches non-leaf PTEs in pte_cache to accerlerate the process. * * ==Structure== * - l2tlb : for leaf PTEs * - set-associative (configurable with [[CoreParams.nL2TLBEntries]]and [[CoreParams.nL2TLBWays]])) * - PLRU * - pte_cache: for non-leaf PTEs * - set-associative * - LRU * - s2_pte_cache: for non-leaf PTEs in 2-stage translation * - set-associative * - PLRU * * l2tlb Pipeline: 3 stage * {{{ * stage 0 : read * stage 1 : decode * stage 2 : hit check * }}} * ==State Machine== * s_ready: ready to reveive request from TLB * s_req: request mem; pte_cache hit judge * s_wait1: deal with l2tlb error * s_wait2: final hit judge * s_wait3: receive mem response * s_fragment_superpage: for superpage PTE * * @note l2tlb hit happens in s_req or s_wait1 * @see RV-priv spec 4.3-4.6 for Virtual-Memory System * @see RV-priv spec 8.5 for Two-Stage Address Translation * @todo details in two-stage translation / class PTW(n: Int)(implicit edge: TLEdgeOut, p: Parameters) extends CoreModule()(p) { val io = IO(new Bundle { /* to n TLB / val requestor = Flipped(Vec(n, new TLBPTWIO)) /* to HellaCache / val mem = new HellaCacheIO /* to Core * * contains CSRs info and performance statistics / val dpath = new DatapathPTWIO }) val s_ready :: s_req :: s_wait1 :: s_dummy1 :: s_wait2 :: s_wait3 :: s_dummy2 :: s_fragment_superpage :: Nil = Enum(8) val state = RegInit(s_ready) val l2_refill_wire = Wire(Bool()) /* Arbiter to arbite request from n TLB / val arb = Module(new Arbiter(Valid(new PTWReq), n)) // use TLB req as arbitor's input arb.io.in <> io.requestor.map(_.req) // receive req only when s_ready and not in refill arb.io.out.ready := (state === s_ready) && !l2_refill_wire val resp_valid = RegNext(VecInit(Seq.fill(io.requestor.size)(false.B))) val clock_en = state =/= s_ready \|\| l2_refill_wire \|\| arb.io.out.valid \|\| io.dpath.sfence.valid \|\| io.dpath.customCSRs.disableDCacheClockGate io.dpath.clock_enabled := usingVM.B && clock_en val gated_clock = if (!usingVM \|\| !tileParams.dcache.get.clockGate) clock else ClockGate(clock, clock_en, "ptw_clock_gate") withClock (gated_clock) { // entering gated-clock domain val invalidated = Reg(Bool()) /* current PTE level * {{{ * 0 <= count <= pgLevel-1 * count = pgLevel - 1 : leaf PTE * count < pgLevel - 1 : non-leaf PTE * }}} / val count = Reg(UInt(log2Ceil(pgLevels).W)) val resp_ae_ptw = Reg(Bool()) val resp_ae_final = Reg(Bool()) val resp_pf = Reg(Bool()) val resp_gf = Reg(Bool()) val resp_hr = Reg(Bool()) val resp_hw = Reg(Bool()) val resp_hx = Reg(Bool()) val resp_fragmented_superpage = Reg(Bool()) /* tlb request / val r_req = Reg(new PTWReq) /* current selected way in arbitor / val r_req_dest = Reg(Bits()) // to respond to L1TLB : l2_hit // to construct mem.req.addr val r_pte = Reg(new PTE) val r_hgatp = Reg(new PTBR) // 2-stage pageLevel val aux_count = Reg(UInt(log2Ceil(pgLevels).W)) /* pte for 2-stage translation / val aux_pte = Reg(new PTE) val gpa_pgoff = Reg(UInt(pgIdxBits.W)) // only valid in resp_gf case val stage2 = Reg(Bool()) val stage2_final = Reg(Bool()) val satp = Mux(arb.io.out.bits.bits.vstage1, io.dpath.vsatp, io.dpath.ptbr) val r_hgatp_initial_count = pgLevels.U - minPgLevels.U - r_hgatp.additionalPgLevels /* 2-stage translation both enable / val do_both_stages = r_req.vstage1 && r_req.stage2 val max_count = count max aux_count val vpn = Mux(r_req.vstage1 && stage2, aux_pte.ppn, r_req.addr) val mem_resp_valid = RegNext(io.mem.resp.valid) val mem_resp_data = RegNext(io.mem.resp.bits.data) io.mem.uncached_resp.map { resp => assert(!(resp.valid && io.mem.resp.valid)) resp.ready := true.B when (resp.valid) { mem_resp_valid := true.B mem_resp_data := resp.bits.data } } // construct pte from mem.resp val (pte, invalid_paddr, invalid_gpa) = { val tmp = mem_resp_data.asTypeOf(new PTE()) val res = WireDefault(tmp) res.ppn := Mux(do_both_stages && !stage2, tmp.ppn(vpnBits.min(tmp.ppn.getWidth)-1, 0), tmp.ppn(ppnBits-1, 0)) when (tmp.r \|\| tmp.w \|\| tmp.x) { // for superpage mappings, make sure PPN LSBs are zero for (i <- 0 until pgLevels-1) when (count <= i.U && tmp.ppn((pgLevels-1-i)pgLevelBits-1, (pgLevels-2-i)pgLevelBits) =/= 0.U) { res.v := false.B } } (res, Mux(do_both_stages && !stage2, (tmp.ppn >> vpnBits) =/= 0.U, (tmp.ppn >> ppnBits) =/= 0.U), do_both_stages && !stage2 && checkInvalidHypervisorGPA(r_hgatp, tmp.ppn)) } // find non-leaf PTE, need traverse val traverse = pte.table() && !invalid_paddr && !invalid_gpa && count < (pgLevels-1).U /* address send to mem for enquerry / val pte_addr = if (!usingVM) 0.U else { val vpn_idxs = (0 until pgLevels).map { i => val width = pgLevelBits + (if (i <= pgLevels - minPgLevels) hypervisorExtraAddrBits else 0) (vpn >> (pgLevels - i - 1) pgLevelBits)(width - 1, 0) } val mask = Mux(stage2 && count === r_hgatp_initial_count, ((1 << (hypervisorExtraAddrBits + pgLevelBits)) - 1).U, ((1 << pgLevelBits) - 1).U) val vpn_idx = vpn_idxs(count) & mask val raw_pte_addr = ((r_pte.ppn << pgLevelBits) \| vpn_idx) << log2Ceil(xLen / 8) val size = if (usingHypervisor) vaddrBits else paddrBits //use r_pte.ppn as page table base address //use vpn slice as offset raw_pte_addr.apply(size.min(raw_pte_addr.getWidth) - 1, 0) } /** stage2_pte_cache input addr / val stage2_pte_cache_addr = if (!usingHypervisor) 0.U else { val vpn_idxs = (0 until pgLevels - 1).map { i => (r_req.addr >> (pgLevels - i - 1) pgLevelBits)(pgLevelBits - 1, 0) } val vpn_idx = vpn_idxs(aux_count) val raw_s2_pte_cache_addr = Cat(aux_pte.ppn, vpn_idx) << log2Ceil(xLen / 8) raw_s2_pte_cache_addr(vaddrBits.min(raw_s2_pte_cache_addr.getWidth) - 1, 0) } def makeFragmentedSuperpagePPN(ppn: UInt): Seq[UInt] = { (pgLevels-1 until 0 by -1).map(i => Cat(ppn >> (pgLevelBitsi), r_req.addr(((pgLevelBitsi) min vpnBits)-1, 0).padTo(pgLevelBitsi))) } /* PTECache caches non-leaf PTE * @param s2 true: 2-stage address translation / def makePTECache(s2: Boolean): (Bool, UInt) = if (coreParams.nPTECacheEntries == 0) { (false.B, 0.U) } else { val plru = new PseudoLRU(coreParams.nPTECacheEntries) val valid = RegInit(0.U(coreParams.nPTECacheEntries.W)) val tags = Reg(Vec(coreParams.nPTECacheEntries, UInt((if (usingHypervisor) 1 + vaddrBits else paddrBits).W))) // not include full pte, only ppn val data = Reg(Vec(coreParams.nPTECacheEntries, UInt((if (usingHypervisor && s2) vpnBits else ppnBits).W))) val can_hit = if (s2) count === r_hgatp_initial_count && aux_count < (pgLevels-1).U && r_req.vstage1 && stage2 && !stage2_final else count < (pgLevels-1).U && Mux(r_req.vstage1, stage2, !r_req.stage2) val can_refill = if (s2) do_both_stages && !stage2 && !stage2_final else can_hit val tag = if (s2) Cat(true.B, stage2_pte_cache_addr.padTo(vaddrBits)) else Cat(r_req.vstage1, pte_addr.padTo(if (usingHypervisor) vaddrBits else paddrBits)) val hits = tags.map(_ === tag).asUInt & valid val hit = hits.orR && can_hit // refill with mem response when (mem_resp_valid && traverse && can_refill && !hits.orR && !invalidated) { val r = Mux(valid.andR, plru.way, PriorityEncoder(~valid)) valid := valid \| UIntToOH(r) tags(r) := tag data(r) := pte.ppn plru.access(r) } // replace when (hit && state === s_req) { plru.access(OHToUInt(hits)) } when (io.dpath.sfence.valid && (!io.dpath.sfence.bits.rs1 \|\| usingHypervisor.B && io.dpath.sfence.bits.hg)) { valid := 0.U } val lcount = if (s2) aux_count else count for (i <- 0 until pgLevels-1) { ccover(hit && state === s_req && lcount === i.U, s"PTE_CACHE_HIT_L$i", s"PTE cache hit, level $i") } (hit, Mux1H(hits, data)) } // generate pte_cache val (pte_cache_hit, pte_cache_data) = makePTECache(false) // generate pte_cache with 2-stage translation val (stage2_pte_cache_hit, stage2_pte_cache_data) = makePTECache(true) // pte_cache hit or 2-stage pte_cache hit val pte_hit = RegNext(false.B) io.dpath.perf.pte_miss := false.B io.dpath.perf.pte_hit := pte_hit && (state === s_req) && !io.dpath.perf.l2hit assert(!(io.dpath.perf.l2hit && (io.dpath.perf.pte_miss \|\| io.dpath.perf.pte_hit)), "PTE Cache Hit/Miss Performance Monitor Events are lower priority than L2TLB Hit event") // l2_refill happens when find the leaf pte val l2_refill = RegNext(false.B) l2_refill_wire := l2_refill io.dpath.perf.l2miss := false.B io.dpath.perf.l2hit := false.B // l2tlb val (l2_hit, l2_error, l2_pte, l2_tlb_ram) = if (coreParams.nL2TLBEntries == 0) (false.B, false.B, WireDefault(0.U.asTypeOf(new PTE)), None) else { val code = new ParityCode require(isPow2(coreParams.nL2TLBEntries)) require(isPow2(coreParams.nL2TLBWays)) require(coreParams.nL2TLBEntries >= coreParams.nL2TLBWays) val nL2TLBSets = coreParams.nL2TLBEntries / coreParams.nL2TLBWays require(isPow2(nL2TLBSets)) val idxBits = log2Ceil(nL2TLBSets) val l2_plru = new SetAssocLRU(nL2TLBSets, coreParams.nL2TLBWays, "plru") val ram = DescribedSRAM( name = "l2_tlb_ram", desc = "L2 TLB", size = nL2TLBSets, data = Vec(coreParams.nL2TLBWays, UInt(code.width(new L2TLBEntry(nL2TLBSets).getWidth).W)) ) val g = Reg(Vec(coreParams.nL2TLBWays, UInt(nL2TLBSets.W))) val valid = RegInit(VecInit(Seq.fill(coreParams.nL2TLBWays)(0.U(nL2TLBSets.W)))) // use r_req to construct tag val (r_tag, r_idx) = Split(Cat(r_req.vstage1, r_req.addr(maxSVAddrBits-pgIdxBits-1, 0)), idxBits) /* the valid vec for the selected set(including n ways) / val r_valid_vec = valid.map(_(r_idx)).asUInt val r_valid_vec_q = Reg(UInt(coreParams.nL2TLBWays.W)) val r_l2_plru_way = Reg(UInt(log2Ceil(coreParams.nL2TLBWays max 1).W)) r_valid_vec_q := r_valid_vec // replacement way r_l2_plru_way := (if (coreParams.nL2TLBWays > 1) l2_plru.way(r_idx) else 0.U) // refill with r_pte(leaf pte) when (l2_refill && !invalidated) { val entry = Wire(new L2TLBEntry(nL2TLBSets)) entry.ppn := r_pte.ppn entry.d := r_pte.d entry.a := r_pte.a entry.u := r_pte.u entry.x := r_pte.x entry.w := r_pte.w entry.r := r_pte.r entry.tag := r_tag // if all the way are valid, use plru to select one way to be replaced, // otherwise use PriorityEncoderOH to select one val wmask = if (coreParams.nL2TLBWays > 1) Mux(r_valid_vec_q.andR, UIntToOH(r_l2_plru_way, coreParams.nL2TLBWays), PriorityEncoderOH(~r_valid_vec_q)) else 1.U(1.W) ram.write(r_idx, VecInit(Seq.fill(coreParams.nL2TLBWays)(code.encode(entry.asUInt))), wmask.asBools) val mask = UIntToOH(r_idx) for (way <- 0 until coreParams.nL2TLBWays) { when (wmask(way)) { valid(way) := valid(way) \| mask g(way) := Mux(r_pte.g, g(way) \| mask, g(way) & ~mask) } } } // sfence happens when (io.dpath.sfence.valid) { val hg = usingHypervisor.B && io.dpath.sfence.bits.hg for (way <- 0 until coreParams.nL2TLBWays) { valid(way) := Mux(!hg && io.dpath.sfence.bits.rs1, valid(way) & ~UIntToOH(io.dpath.sfence.bits.addr(idxBits+pgIdxBits-1, pgIdxBits)), Mux(!hg && io.dpath.sfence.bits.rs2, valid(way) & g(way), 0.U)) } } val s0_valid = !l2_refill && arb.io.out.fire val s0_suitable = arb.io.out.bits.bits.vstage1 === arb.io.out.bits.bits.stage2 && !arb.io.out.bits.bits.need_gpa val s1_valid = RegNext(s0_valid && s0_suitable && arb.io.out.bits.valid) val s2_valid = RegNext(s1_valid) // read from tlb idx val s1_rdata = ram.read(arb.io.out.bits.bits.addr(idxBits-1, 0), s0_valid) val s2_rdata = s1_rdata.map(s1_rdway => code.decode(RegEnable(s1_rdway, s1_valid))) val s2_valid_vec = RegEnable(r_valid_vec, s1_valid) val s2_g_vec = RegEnable(VecInit(g.map(_(r_idx))), s1_valid) val s2_error = (0 until coreParams.nL2TLBWays).map(way => s2_valid_vec(way) && s2_rdata(way).error).orR when (s2_valid && s2_error) { valid.foreach { _ := 0.U }} // decode val s2_entry_vec = s2_rdata.map(_.uncorrected.asTypeOf(new L2TLBEntry(nL2TLBSets))) val s2_hit_vec = (0 until coreParams.nL2TLBWays).map(way => s2_valid_vec(way) && (r_tag === s2_entry_vec(way).tag)) val s2_hit = s2_valid && s2_hit_vec.orR io.dpath.perf.l2miss := s2_valid && !(s2_hit_vec.orR) io.dpath.perf.l2hit := s2_hit when (s2_hit) { l2_plru.access(r_idx, OHToUInt(s2_hit_vec)) assert((PopCount(s2_hit_vec) === 1.U) \|\| s2_error, "L2 TLB multi-hit") } val s2_pte = Wire(new PTE) val s2_hit_entry = Mux1H(s2_hit_vec, s2_entry_vec) s2_pte.ppn := s2_hit_entry.ppn s2_pte.d := s2_hit_entry.d s2_pte.a := s2_hit_entry.a s2_pte.g := Mux1H(s2_hit_vec, s2_g_vec) s2_pte.u := s2_hit_entry.u s2_pte.x := s2_hit_entry.x s2_pte.w := s2_hit_entry.w s2_pte.r := s2_hit_entry.r s2_pte.v := true.B s2_pte.reserved_for_future := 0.U s2_pte.reserved_for_software := 0.U for (way <- 0 until coreParams.nL2TLBWays) { ccover(s2_hit && s2_hit_vec(way), s"L2_TLB_HIT_WAY$way", s"L2 TLB hit way$way") } (s2_hit, s2_error, s2_pte, Some(ram)) } // if SFENCE occurs during walk, don't refill PTE cache or L2 TLB until next walk invalidated := io.dpath.sfence.valid \|\| (invalidated && state =/= s_ready) // mem request io.mem.keep_clock_enabled := false.B io.mem.req.valid := state === s_req \|\| state === s_dummy1 io.mem.req.bits.phys := true.B io.mem.req.bits.cmd := M_XRD io.mem.req.bits.size := log2Ceil(xLen/8).U io.mem.req.bits.signed := false.B io.mem.req.bits.addr := pte_addr io.mem.req.bits.idx.foreach(_ := pte_addr) io.mem.req.bits.dprv := PRV.S.U // PTW accesses are S-mode by definition io.mem.req.bits.dv := do_both_stages && !stage2 io.mem.req.bits.tag := DontCare io.mem.req.bits.no_resp := false.B io.mem.req.bits.no_alloc := DontCare io.mem.req.bits.no_xcpt := DontCare io.mem.req.bits.data := DontCare io.mem.req.bits.mask := DontCare io.mem.s1_kill := l2_hit \|\| (state =/= s_wait1) \|\| resp_gf io.mem.s1_data := DontCare io.mem.s2_kill := false.B val pageGranularityPMPs = pmpGranularity >= (1 << pgIdxBits) require(!usingHypervisor \|\| pageGranularityPMPs, s"hypervisor requires pmpGranularity >= ${1<<pgIdxBits}") val pmaPgLevelHomogeneous = (0 until pgLevels) map { i => val pgSize = BigInt(1) << (pgIdxBits + ((pgLevels - 1 - i) pgLevelBits)) if (pageGranularityPMPs && i == pgLevels - 1) { require(TLBPageLookup.homogeneous(edge.manager.managers, pgSize), s"All memory regions must be $pgSize-byte aligned") true.B } else { TLBPageLookup(edge.manager.managers, xLen, p(CacheBlockBytes), pgSize, xLen/8)(r_pte.ppn << pgIdxBits).homogeneous } } val pmaHomogeneous = pmaPgLevelHomogeneous(count) val pmpHomogeneous = new PMPHomogeneityChecker(io.dpath.pmp).apply(r_pte.ppn << pgIdxBits, count) val homogeneous = pmaHomogeneous && pmpHomogeneous // response to tlb for (i <- 0 until io.requestor.size) { io.requestor(i).resp.valid := resp_valid(i) io.requestor(i).resp.bits.ae_ptw := resp_ae_ptw io.requestor(i).resp.bits.ae_final := resp_ae_final io.requestor(i).resp.bits.pf := resp_pf io.requestor(i).resp.bits.gf := resp_gf io.requestor(i).resp.bits.hr := resp_hr io.requestor(i).resp.bits.hw := resp_hw io.requestor(i).resp.bits.hx := resp_hx io.requestor(i).resp.bits.pte := r_pte io.requestor(i).resp.bits.level := max_count io.requestor(i).resp.bits.homogeneous := homogeneous \|\| pageGranularityPMPs.B io.requestor(i).resp.bits.fragmented_superpage := resp_fragmented_superpage && pageGranularityPMPs.B io.requestor(i).resp.bits.gpa.valid := r_req.need_gpa io.requestor(i).resp.bits.gpa.bits := Cat(Mux(!stage2_final \|\| !r_req.vstage1 \|\| aux_count === (pgLevels - 1).U, aux_pte.ppn, makeFragmentedSuperpagePPN(aux_pte.ppn)(aux_count)), gpa_pgoff) io.requestor(i).resp.bits.gpa_is_pte := !stage2_final io.requestor(i).ptbr := io.dpath.ptbr io.requestor(i).hgatp := io.dpath.hgatp io.requestor(i).vsatp := io.dpath.vsatp io.requestor(i).customCSRs <> io.dpath.customCSRs io.requestor(i).status := io.dpath.status io.requestor(i).hstatus := io.dpath.hstatus io.requestor(i).gstatus := io.dpath.gstatus io.requestor(i).pmp := io.dpath.pmp } // control state machine val next_state = WireDefault(state) state := OptimizationBarrier(next_state) val do_switch = WireDefault(false.B) switch (state) { is (s_ready) { when (arb.io.out.fire) { val satp_initial_count = pgLevels.U - minPgLevels.U - satp.additionalPgLevels val vsatp_initial_count = pgLevels.U - minPgLevels.U - io.dpath.vsatp.additionalPgLevels val hgatp_initial_count = pgLevels.U - minPgLevels.U - io.dpath.hgatp.additionalPgLevels val aux_ppn = Mux(arb.io.out.bits.bits.vstage1, io.dpath.vsatp.ppn, arb.io.out.bits.bits.addr) r_req := arb.io.out.bits.bits r_req_dest := arb.io.chosen next_state := Mux(arb.io.out.bits.valid, s_req, s_ready) stage2 := arb.io.out.bits.bits.stage2 stage2_final := arb.io.out.bits.bits.stage2 && !arb.io.out.bits.bits.vstage1 count := Mux(arb.io.out.bits.bits.stage2, hgatp_initial_count, satp_initial_count) aux_count := Mux(arb.io.out.bits.bits.vstage1, vsatp_initial_count, 0.U) aux_pte.ppn := aux_ppn aux_pte.reserved_for_future := 0.U resp_ae_ptw := false.B resp_ae_final := false.B resp_pf := false.B resp_gf := checkInvalidHypervisorGPA(io.dpath.hgatp, aux_ppn) && arb.io.out.bits.bits.stage2 resp_hr := true.B resp_hw := true.B resp_hx := true.B resp_fragmented_superpage := false.B r_hgatp := io.dpath.hgatp assert(!arb.io.out.bits.bits.need_gpa \|\| arb.io.out.bits.bits.stage2) } } is (s_req) { when(stage2 && count === r_hgatp_initial_count) { gpa_pgoff := Mux(aux_count === (pgLevels-1).U, r_req.addr << (xLen/8).log2, stage2_pte_cache_addr) } // pte_cache hit when (stage2_pte_cache_hit) { aux_count := aux_count + 1.U aux_pte.ppn := stage2_pte_cache_data aux_pte.reserved_for_future := 0.U pte_hit := true.B }.elsewhen (pte_cache_hit) { count := count + 1.U pte_hit := true.B }.otherwise { next_state := Mux(io.mem.req.ready, s_wait1, s_req) } when(resp_gf) { next_state := s_ready resp_valid(r_req_dest) := true.B } } is (s_wait1) { // This Mux is for the l2_error case; the l2_hit && !l2_error case is overriden below next_state := Mux(l2_hit, s_req, s_wait2) } is (s_wait2) { next_state := s_wait3 io.dpath.perf.pte_miss := count < (pgLevels-1).U when (io.mem.s2_xcpt.ae.ld) { resp_ae_ptw := true.B next_state := s_ready resp_valid(r_req_dest) := true.B } } is (s_fragment_superpage) { next_state := s_ready resp_valid(r_req_dest) := true.B when (!homogeneous) { count := (pgLevels-1).U resp_fragmented_superpage := true.B } when (do_both_stages) { resp_fragmented_superpage := true.B } } } val merged_pte = { val superpage_masks = (0 until pgLevels).map(i => ((BigInt(1) << pte.ppn.getWidth) - (BigInt(1) << (pgLevels-1-i)pgLevelBits)).U) val superpage_mask = superpage_masks(Mux(stage2_final, max_count, (pgLevels-1).U)) val stage1_ppns = (0 until pgLevels-1).map(i => Cat(pte.ppn(pte.ppn.getWidth-1, (pgLevels-i-1)pgLevelBits), aux_pte.ppn((pgLevels-i-1)pgLevelBits-1,0))) :+ pte.ppn val stage1_ppn = stage1_ppns(count) makePTE(stage1_ppn & superpage_mask, aux_pte) } r_pte := OptimizationBarrier( // l2tlb hit->find a leaf PTE(l2_pte), respond to L1TLB Mux(l2_hit && !l2_error && !resp_gf, l2_pte, // S2 PTE cache hit -> proceed to the next level of walking, update the r_pte with hgatp Mux(state === s_req && stage2_pte_cache_hit, makeHypervisorRootPTE(r_hgatp, stage2_pte_cache_data, l2_pte), // pte cache hit->find a non-leaf PTE(pte_cache),continue to request mem Mux(state === s_req && pte_cache_hit, makePTE(pte_cache_data, l2_pte), // 2-stage translation Mux(do_switch, makeHypervisorRootPTE(r_hgatp, pte.ppn, r_pte), // when mem respond, store mem.resp.pte Mux(mem_resp_valid, Mux(!traverse && r_req.vstage1 && stage2, merged_pte, pte), // fragment_superpage Mux(state === s_fragment_superpage && !homogeneous && count =/= (pgLevels - 1).U, makePTE(makeFragmentedSuperpagePPN(r_pte.ppn)(count), r_pte), // when tlb request come->request mem, use root address in satp(or vsatp,hgatp) Mux(arb.io.out.fire, Mux(arb.io.out.bits.bits.stage2, makeHypervisorRootPTE(io.dpath.hgatp, io.dpath.vsatp.ppn, r_pte), makePTE(satp.ppn, r_pte)), r_pte)))))))) when (l2_hit && !l2_error && !resp_gf) { assert(state === s_req \|\| state === s_wait1) next_state := s_ready resp_valid(r_req_dest) := true.B count := (pgLevels-1).U } when (mem_resp_valid) { assert(state === s_wait3) next_state := s_req when (traverse) { when (do_both_stages && !stage2) { do_switch := true.B } count := count + 1.U }.otherwise { val gf = (stage2 && !stage2_final && !pte.ur()) \|\| (pte.leaf() && pte.reserved_for_future === 0.U && invalid_gpa) val ae = pte.v && invalid_paddr val pf = pte.v && pte.reserved_for_future =/= 0.U val success = pte.v && !ae && !pf && !gf when (do_both_stages && !stage2_final && success) { when (stage2) { stage2 := false.B count := aux_count }.otherwise { stage2_final := true.B do_switch := true.B } }.otherwise { // find a leaf pte, start l2 refill l2_refill := success && count === (pgLevels-1).U && !r_req.need_gpa && (!r_req.vstage1 && !r_req.stage2 \|\| do_both_stages && aux_count === (pgLevels-1).U && pte.isFullPerm()) count := max_count when (pageGranularityPMPs.B && !(count === (pgLevels-1).U && (!do_both_stages \|\| aux_count === (pgLevels-1).U))) { next_state := s_fragment_superpage }.otherwise { next_state := s_ready resp_valid(r_req_dest) := true.B } resp_ae_ptw := ae && count < (pgLevels-1).U && pte.table() resp_ae_final := ae && pte.leaf() resp_pf := pf && !stage2 resp_gf := gf \|\| (pf && stage2) resp_hr := !stage2 \|\| (!pf && !gf && pte.ur()) resp_hw := !stage2 \|\| (!pf && !gf && pte.uw()) resp_hx := !stage2 \|\| (!pf && !gf && pte.ux()) } } } when (io.mem.s2_nack) { assert(state === s_wait2) next_state := s_req } when (do_switch) { aux_count := Mux(traverse, count + 1.U, count) count := r_hgatp_initial_count aux_pte := Mux(traverse, pte, { val s1_ppns = (0 until pgLevels-1).map(i => Cat(pte.ppn(pte.ppn.getWidth-1, (pgLevels-i-1)pgLevelBits), r_req.addr(((pgLevels-i-1)pgLevelBits min vpnBits)-1,0).padTo((pgLevels-i-1)pgLevelBits))) :+ pte.ppn makePTE(s1_ppns(count), pte) }) stage2 := true.B } for (i <- 0 until pgLevels) { val leaf = mem_resp_valid && !traverse && count === i.U ccover(leaf && pte.v && !invalid_paddr && !invalid_gpa && pte.reserved_for_future === 0.U, s"L$i", s"successful page-table access, level $i") ccover(leaf && pte.v && invalid_paddr, s"L${i}_BAD_PPN_MSB", s"PPN too large, level $i") ccover(leaf && pte.v && invalid_gpa, s"L${i}_BAD_GPA_MSB", s"GPA too large, level $i") ccover(leaf && pte.v && pte.reserved_for_future =/= 0.U, s"L${i}_BAD_RSV_MSB", s"reserved MSBs set, level $i") ccover(leaf && !mem_resp_data(0), s"L${i}_INVALID_PTE", s"page not present, level $i") if (i != pgLevels-1) ccover(leaf && !pte.v && mem_resp_data(0), s"L${i}_BAD_PPN_LSB", s"PPN LSBs not zero, level $i") } ccover(mem_resp_valid && count === (pgLevels-1).U && pte.table(), s"TOO_DEEP", s"page table too deep") ccover(io.mem.s2_nack, "NACK", "D$ nacked page-table access") ccover(state === s_wait2 && io.mem.s2_xcpt.ae.ld, "AE", "access exception while walking page table") } // leaving gated-clock domain private def ccover(cond: Bool, label: String, desc: String)(implicit sourceInfo: SourceInfo) = if (usingVM) property.cover(cond, s"PTW_$label", "MemorySystem;;" + desc) /** Relace PTE.ppn with ppn / private def makePTE(ppn: UInt, default: PTE) = { val pte = WireDefault(default) pte.ppn := ppn pte } /* use hgatp and vpn to construct a new ppn / private def makeHypervisorRootPTE(hgatp: PTBR, vpn: UInt, default: PTE) = { val count = pgLevels.U - minPgLevels.U - hgatp.additionalPgLevels val idxs = (0 to pgLevels-minPgLevels).map(i => (vpn >> (pgLevels-i)pgLevelBits)) val lsbs = WireDefault(UInt(maxHypervisorExtraAddrBits.W), idxs(count)) val pte = WireDefault(default) pte.ppn := Cat(hgatp.ppn >> maxHypervisorExtraAddrBits, lsbs) pte } /** use hgatp and vpn to check for gpa out of range / private def checkInvalidHypervisorGPA(hgatp: PTBR, vpn: UInt) = { val count = pgLevels.U - minPgLevels.U - hgatp.additionalPgLevels val idxs = (0 to pgLevels-minPgLevels).map(i => (vpn >> ((pgLevels-i)pgLevelBits)+maxHypervisorExtraAddrBits)) idxs.extract(count) =/= 0.U } } /** Mix-ins for constructing tiles that might have a PTW / trait CanHavePTW extends HasTileParameters with HasHellaCache { this: BaseTile => val module: CanHavePTWModule var nPTWPorts = 1 nDCachePorts += usingPTW.toInt } trait CanHavePTWModule extends HasHellaCacheModule { val outer: CanHavePTW val ptwPorts = ListBuffer(outer.dcache.module.io.ptw) val ptw = Module(new PTW(outer.nPTWPorts)(outer.dcache.node.edges.out(0), outer.p)) ptw.io.mem <> DontCare if (outer.usingPTW) { dcachePorts += ptw.io.mem } } File HierarchicalElement.scala: package freechips.rocketchip.subsystem import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.devices.debug.TLDebugModule import freechips.rocketchip.diplomacy.{BufferParams} import freechips.rocketchip.interrupts.IntXbar import freechips.rocketchip.prci.{ClockSinkParameters, ResetCrossingType, ClockCrossingType} import freechips.rocketchip.tile.{LookupByHartIdImpl, TraceBundle} import freechips.rocketchip.tilelink.{TLNode, TLIdentityNode, TLXbar, TLBuffer, TLInwardNode, TLOutwardNode} trait HierarchicalElementParams { val baseName: String // duplicated instances shouuld share a base name val uniqueName: String val clockSinkParams: ClockSinkParameters } abstract class InstantiableHierarchicalElementParams[ElementType <: BaseHierarchicalElement] extends HierarchicalElementParams /* An interface for describing the parameteization of how HierarchicalElements are connected to interconnects / trait HierarchicalElementCrossingParamsLike { /* The type of clock crossing that should be inserted at the element boundary. / def crossingType: ClockCrossingType /* Parameters describing the contents and behavior of the point where the element is attached as an interconnect master. / def master: HierarchicalElementPortParamsLike /* Parameters describing the contents and behavior of the point where the element is attached as an interconnect slave. / def slave: HierarchicalElementPortParamsLike /* The subnetwork location of the device selecting the apparent base address of MMIO devices inside the element / def mmioBaseAddressPrefixWhere: TLBusWrapperLocation /* Inject a reset management subgraph that effects the element child reset only / def resetCrossingType: ResetCrossingType /* Keep the element clock separate from the interconnect clock (e.g. even if they are synchronous to one another) / def forceSeparateClockReset: Boolean } /* An interface for describing the parameterization of how a particular element port is connected to an interconnect / trait HierarchicalElementPortParamsLike { /* The subnetwork location of the interconnect to which this element port should be connected. / def where: TLBusWrapperLocation /* Allows port-specific adapters to be injected into the interconnect side of the attachment point. / def injectNode(context: Attachable)(implicit p: Parameters): TLNode } abstract class BaseHierarchicalElement (val crossing: ClockCrossingType)(implicit p: Parameters) extends LazyModule()(p) with CrossesToOnlyOneClockDomain { def module: BaseHierarchicalElementModuleImp[BaseHierarchicalElement] protected val tlOtherMastersNode = TLIdentityNode() protected val tlMasterXbar = LazyModule(new TLXbar(nameSuffix = Some(s"MasterXbar_$desiredName"))) protected val tlSlaveXbar = LazyModule(new TLXbar(nameSuffix = Some(s"SlaveXbar_$desiredName"))) protected val intXbar = LazyModule(new IntXbar) def masterNode: TLOutwardNode def slaveNode: TLInwardNode /* Helper function to insert additional buffers on master ports at the boundary of the tile. * * The boundary buffering needed to cut feed-through paths is * microarchitecture specific, so this may need to be overridden * in subclasses of this class. / def makeMasterBoundaryBuffers(crossing: ClockCrossingType)(implicit p: Parameters) = TLBuffer(BufferParams.none) /* Helper function to insert additional buffers on slave ports at the boundary of the tile. * * The boundary buffering needed to cut feed-through paths is * microarchitecture specific, so this may need to be overridden * in subclasses of this class. / def makeSlaveBoundaryBuffers(crossing: ClockCrossingType)(implicit p: Parameters) = TLBuffer(BufferParams.none) } abstract class BaseHierarchicalElementModuleImp[+L <: BaseHierarchicalElement](val outer: L) extends LazyModuleImp(outer) File RocketTile.scala: // See LICENSE.SiFive for license details. // See LICENSE.Berkeley for license details. package freechips.rocketchip.tile import chisel3._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.devices.tilelink.{BasicBusBlockerParams, BasicBusBlocker} import freechips.rocketchip.diplomacy.{ AddressSet, DisableMonitors, BufferParams } import freechips.rocketchip.resources.{ SimpleDevice, Description, ResourceAnchors, ResourceBindings, ResourceBinding, Resource, ResourceAddress, } import freechips.rocketchip.interrupts.IntIdentityNode import freechips.rocketchip.tilelink.{TLIdentityNode, TLBuffer} import freechips.rocketchip.rocket.{ RocketCoreParams, ICacheParams, DCacheParams, BTBParams, HasHellaCache, HasICacheFrontend, ScratchpadSlavePort, HasICacheFrontendModule, Rocket } import freechips.rocketchip.subsystem.HierarchicalElementCrossingParamsLike import freechips.rocketchip.prci.{ClockSinkParameters, RationalCrossing, ClockCrossingType} import freechips.rocketchip.util.{Annotated, InOrderArbiter} import freechips.rocketchip.util.BooleanToAugmentedBoolean case class RocketTileBoundaryBufferParams(force: Boolean = false) case class RocketTileParams( core: RocketCoreParams = RocketCoreParams(), icache: Option[ICacheParams] = Some(ICacheParams()), dcache: Option[DCacheParams] = Some(DCacheParams()), btb: Option[BTBParams] = Some(BTBParams()), dataScratchpadBytes: Int = 0, tileId: Int = 0, beuAddr: Option[BigInt] = None, blockerCtrlAddr: Option[BigInt] = None, clockSinkParams: ClockSinkParameters = ClockSinkParameters(), boundaryBuffers: Option[RocketTileBoundaryBufferParams] = None ) extends InstantiableTileParams[RocketTile] { require(icache.isDefined) require(dcache.isDefined) val baseName = "rockettile" val uniqueName = s"${baseName}_$tileId" def instantiate(crossing: HierarchicalElementCrossingParamsLike, lookup: LookupByHartIdImpl)(implicit p: Parameters): RocketTile = { new RocketTile(this, crossing, lookup) } } class RocketTile private( val rocketParams: RocketTileParams, crossing: ClockCrossingType, lookup: LookupByHartIdImpl, q: Parameters) extends BaseTile(rocketParams, crossing, lookup, q) with SinksExternalInterrupts with SourcesExternalNotifications with HasLazyRoCC // implies CanHaveSharedFPU with CanHavePTW with HasHellaCache with HasHellaCache with HasICacheFrontend { // Private constructor ensures altered LazyModule.p is used implicitly def this(params: RocketTileParams, crossing: HierarchicalElementCrossingParamsLike, lookup: LookupByHartIdImpl)(implicit p: Parameters) = this(params, crossing.crossingType, lookup, p) val intOutwardNode = rocketParams.beuAddr map { _ => IntIdentityNode() } val slaveNode = TLIdentityNode() val masterNode = visibilityNode val dtim_adapter = tileParams.dcache.flatMap { d => d.scratch.map { s => LazyModule(new ScratchpadSlavePort(AddressSet.misaligned(s, d.dataScratchpadBytes), lazyCoreParamsView.coreDataBytes, tileParams.core.useAtomics && !tileParams.core.useAtomicsOnlyForIO)) }} dtim_adapter.foreach(lm => connectTLSlave(lm.node, lm.node.portParams.head.beatBytes)) val bus_error_unit = rocketParams.beuAddr map { a => val beu = LazyModule(new BusErrorUnit(new L1BusErrors, BusErrorUnitParams(a), xLen/8)) intOutwardNode.get := beu.intNode connectTLSlave(beu.node, xBytes) beu } val tile_master_blocker = tileParams.blockerCtrlAddr .map(BasicBusBlockerParams(_, xBytes, masterPortBeatBytes, deadlock = true)) .map(bp => LazyModule(new BasicBusBlocker(bp))) tile_master_blocker.foreach(lm => connectTLSlave(lm.controlNode, xBytes)) // TODO: this doesn't block other masters, e.g. RoCCs tlOtherMastersNode := tile_master_blocker.map { _.node := tlMasterXbar.node } getOrElse { tlMasterXbar.node } masterNode := tlOtherMastersNode DisableMonitors { implicit p => tlSlaveXbar.node := slaveNode } nDCachePorts += 1 /core / + (dtim_adapter.isDefined).toInt + rocketParams.core.vector.map(_.useDCache.toInt).getOrElse(0) val dtimProperty = dtim_adapter.map(d => Map( "sifive,dtim" -> d.device.asProperty)).getOrElse(Nil) val itimProperty = frontend.icache.itimProperty.toSeq.flatMap(p => Map("sifive,itim" -> p)) val beuProperty = bus_error_unit.map(d => Map( "sifive,buserror" -> d.device.asProperty)).getOrElse(Nil) val cpuDevice: SimpleDevice = new SimpleDevice("cpu", Seq("sifive,rocket0", "riscv")) { override def parent = Some(ResourceAnchors.cpus) override def describe(resources: ResourceBindings): Description = { val Description(name, mapping) = super.describe(resources) Description(name, mapping ++ cpuProperties ++ nextLevelCacheProperty ++ tileProperties ++ dtimProperty ++ itimProperty ++ beuProperty) } } val vector_unit = rocketParams.core.vector.map(v => LazyModule(v.build(p))) vector_unit.foreach(vu => tlMasterXbar.node := vu.atlNode) vector_unit.foreach(vu => tlOtherMastersNode :=* vu.tlNode) ResourceBinding { Resource(cpuDevice, "reg").bind(ResourceAddress(tileId)) } override lazy val module = new RocketTileModuleImp(this) override def makeMasterBoundaryBuffers(crossing: ClockCrossingType)(implicit p: Parameters) = (rocketParams.boundaryBuffers, crossing) match { case (Some(RocketTileBoundaryBufferParams(true )), _) => TLBuffer() case (Some(RocketTileBoundaryBufferParams(false)), _: RationalCrossing) => TLBuffer(BufferParams.none, BufferParams.flow, BufferParams.none, BufferParams.flow, BufferParams(1)) case _ => TLBuffer(BufferParams.none) } override def makeSlaveBoundaryBuffers(crossing: ClockCrossingType)(implicit p: Parameters) = (rocketParams.boundaryBuffers, crossing) match { case (Some(RocketTileBoundaryBufferParams(true )), _) => TLBuffer() case (Some(RocketTileBoundaryBufferParams(false)), _: RationalCrossing) => TLBuffer(BufferParams.flow, BufferParams.none, BufferParams.none, BufferParams.none, BufferParams.none) case _ => TLBuffer(BufferParams.none) } } class RocketTileModuleImp(outer: RocketTile) extends BaseTileModuleImp(outer) with HasFpuOpt with HasLazyRoCCModule with HasICacheFrontendModule { Annotated.params(this, outer.rocketParams) val core = Module(new Rocket(outer)(outer.p)) outer.vector_unit.foreach { v => core.io.vector.get <> v.module.io.core v.module.io.tlb <> outer.dcache.module.io.tlb_port } // reset vector is connected in the Frontend to s2_pc core.io.reset_vector := DontCare // Report unrecoverable error conditions; for now the only cause is cache ECC errors outer.reportHalt(List(outer.dcache.module.io.errors)) // Report when the tile has ceased to retire instructions; for now the only cause is clock gating outer.reportCease(outer.rocketParams.core.clockGate.option( !outer.dcache.module.io.cpu.clock_enabled && !outer.frontend.module.io.cpu.clock_enabled && !ptw.io.dpath.clock_enabled && core.io.cease)) outer.reportWFI(Some(core.io.wfi)) outer.decodeCoreInterrupts(core.io.interrupts) // Decode the interrupt vector outer.bus_error_unit.foreach { beu => core.io.interrupts.buserror.get := beu.module.io.interrupt beu.module.io.errors.dcache := outer.dcache.module.io.errors beu.module.io.errors.icache := outer.frontend.module.io.errors } core.io.interrupts.nmi.foreach { nmi => nmi := outer.nmiSinkNode.get.bundle } // Pass through various external constants and reports that were bundle-bridged into the tile outer.traceSourceNode.bundle <> core.io.trace core.io.traceStall := outer.traceAuxSinkNode.bundle.stall outer.bpwatchSourceNode.bundle <> core.io.bpwatch core.io.hartid := outer.hartIdSinkNode.bundle require(core.io.hartid.getWidth >= outer.hartIdSinkNode.bundle.getWidth, s"core hartid wire (${core.io.hartid.getWidth}b) truncates external hartid wire (${outer.hartIdSinkNode.bundle.getWidth}b)") // Connect the core pipeline to other intra-tile modules outer.frontend.module.io.cpu <> core.io.imem dcachePorts += core.io.dmem // TODO outer.dcachePorts += () => module.core.io.dmem ?? fpuOpt foreach { fpu => core.io.fpu :<>= fpu.io.waiveAs[FPUCoreIO](_.cp_req, _.cp_resp) } if (fpuOpt.isEmpty) { core.io.fpu := DontCare } outer.vector_unit foreach { v => if (outer.rocketParams.core.vector.get.useDCache) { dcachePorts += v.module.io.dmem } else { v.module.io.dmem := DontCare } } core.io.ptw <> ptw.io.dpath // Connect the coprocessor interfaces if (outer.roccs.size > 0) { cmdRouter.get.io.in <> core.io.rocc.cmd outer.roccs.foreach{ lm => lm.module.io.exception := core.io.rocc.exception lm.module.io.fpu_req.ready := DontCare lm.module.io.fpu_resp.valid := DontCare lm.module.io.fpu_resp.bits.data := DontCare lm.module.io.fpu_resp.bits.exc := DontCare } core.io.rocc.resp <> respArb.get.io.out core.io.rocc.busy <> (cmdRouter.get.io.busy \|\| outer.roccs.map(_.module.io.busy).reduce(_ \|\| _)) core.io.rocc.interrupt := outer.roccs.map(_.module.io.interrupt).reduce(_ \|\| _) (core.io.rocc.csrs zip roccCSRIOs.flatten).foreach { t => t._2 <> t._1 } } else { // tie off core.io.rocc.cmd.ready := false.B core.io.rocc.resp.valid := false.B core.io.rocc.resp.bits := DontCare core.io.rocc.busy := DontCare core.io.rocc.interrupt := DontCare } // Dont care mem since not all RoCC need accessing memory core.io.rocc.mem := DontCare // Rocket has higher priority to DTIM than other TileLink clients outer.dtim_adapter.foreach { lm => dcachePorts += lm.module.io.dmem } // TODO eliminate this redundancy val h = dcachePorts.size val c = core.dcacheArbPorts val o = outer.nDCachePorts require(h == c, s"port list size was $h, core expected $c") require(h == o, s"port list size was $h, outer counted $o") // TODO figure out how to move the below into their respective mix-ins dcacheArb.io.requestor <> dcachePorts.toSeq ptw.io.requestor <> ptwPorts.toSeq } trait HasFpuOpt { this: RocketTileModuleImp => val fpuOpt = outer.tileParams.core.fpu.map(params => Module(new FPU(params)(outer.p))) fpuOpt.foreach { fpu => val nRoCCFPUPorts = outer.roccs.count(_.usesFPU) val nFPUPorts = nRoCCFPUPorts + outer.rocketParams.core.useVector.toInt if (nFPUPorts > 0) { val fpArb = Module(new InOrderArbiter(new FPInput()(outer.p), new FPResult()(outer.p), nFPUPorts)) fpu.io.cp_req <> fpArb.io.out_req fpArb.io.out_resp <> fpu.io.cp_resp val fp_rocc_ios = outer.roccs.filter(_.usesFPU).map(_.module.io) for (i <- 0 until nRoCCFPUPorts) { fpArb.io.in_req(i) <> fp_rocc_ios(i).fpu_req fp_rocc_ios(i).fpu_resp <> fpArb.io.in_resp(i) } outer.vector_unit.foreach(vu => { fpArb.io.in_req(nRoCCFPUPorts) <> vu.module.io.fp_req vu.module.io.fp_resp <> fpArb.io.in_resp(nRoCCFPUPorts) }) } else { fpu.io.cp_req.valid := false.B fpu.io.cp_req.bits := DontCare fpu.io.cp_resp.ready := false.B } } }	module RocketTile( // @[RocketTile.scala:141:7] input clock, // @[RocketTile.scala:141:7] input reset, // @[RocketTile.scala:141:7] input auto_buffer_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_buffer_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_buffer_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_buffer_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_buffer_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [5:0] auto_buffer_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_buffer_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_buffer_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_buffer_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_buffer_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_buffer_out_b_ready, // @[LazyModuleImp.scala:107:25] input auto_buffer_out_b_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_buffer_out_b_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_buffer_out_b_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_buffer_out_b_bits_size, // @[LazyModuleImp.scala:107:25] input [5:0] auto_buffer_out_b_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_buffer_out_b_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_buffer_out_b_bits_mask, // @[LazyModuleImp.scala:107:25] input auto_buffer_out_b_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_buffer_out_c_ready, // @[LazyModuleImp.scala:107:25] output auto_buffer_out_c_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_buffer_out_c_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_buffer_out_c_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_buffer_out_c_bits_size, // @[LazyModuleImp.scala:107:25] output [5:0] auto_buffer_out_c_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_buffer_out_c_bits_address, // @[LazyModuleImp.scala:107:25] output [63:0] auto_buffer_out_c_bits_data, // @[LazyModuleImp.scala:107:25] output auto_buffer_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_buffer_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_buffer_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_buffer_out_d_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_buffer_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [5:0] auto_buffer_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input [2:0] auto_buffer_out_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_buffer_out_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_buffer_out_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_buffer_out_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_buffer_out_e_ready, // @[LazyModuleImp.scala:107:25] output auto_buffer_out_e_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_buffer_out_e_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_wfi_out_0, // @[LazyModuleImp.scala:107:25] input auto_int_local_in_3_0, // @[LazyModuleImp.scala:107:25] input auto_int_local_in_2_0, // @[LazyModuleImp.scala:107:25] input auto_int_local_in_1_0, // @[LazyModuleImp.scala:107:25] input auto_int_local_in_1_1, // @[LazyModuleImp.scala:107:25] input auto_int_local_in_0_0, // @[LazyModuleImp.scala:107:25] input auto_hartid_in // @[LazyModuleImp.scala:107:25] ); wire _core_io_imem_might_request; // @[RocketTile.scala:147:20] wire _core_io_imem_req_valid; // @[RocketTile.scala:147:20] wire [39:0] _core_io_imem_req_bits_pc; // @[RocketTile.scala:147:20] wire _core_io_imem_req_bits_speculative; // @[RocketTile.scala:147:20] wire _core_io_imem_sfence_valid; // @[RocketTile.scala:147:20] wire _core_io_imem_sfence_bits_rs1; // @[RocketTile.scala:147:20] wire _core_io_imem_sfence_bits_rs2; // @[RocketTile.scala:147:20] wire [38:0] _core_io_imem_sfence_bits_addr; // @[RocketTile.scala:147:20] wire _core_io_imem_resp_ready; // @[RocketTile.scala:147:20] wire _core_io_imem_btb_update_valid; // @[RocketTile.scala:147:20] wire [4:0] _core_io_imem_btb_update_bits_prediction_entry; // @[RocketTile.scala:147:20] wire [38:0] _core_io_imem_btb_update_bits_pc; // @[RocketTile.scala:147:20] wire _core_io_imem_btb_update_bits_isValid; // @[RocketTile.scala:147:20] wire [38:0] _core_io_imem_btb_update_bits_br_pc; // @[RocketTile.scala:147:20] wire [1:0] _core_io_imem_btb_update_bits_cfiType; // @[RocketTile.scala:147:20] wire _core_io_imem_bht_update_valid; // @[RocketTile.scala:147:20] wire [7:0] _core_io_imem_bht_update_bits_prediction_history; // @[RocketTile.scala:147:20] wire [38:0] _core_io_imem_bht_update_bits_pc; // @[RocketTile.scala:147:20] wire _core_io_imem_bht_update_bits_branch; // @[RocketTile.scala:147:20] wire _core_io_imem_bht_update_bits_taken; // @[RocketTile.scala:147:20] wire _core_io_imem_bht_update_bits_mispredict; // @[RocketTile.scala:147:20] wire _core_io_imem_flush_icache; // @[RocketTile.scala:147:20] wire _core_io_imem_progress; // @[RocketTile.scala:147:20] wire _core_io_dmem_req_valid; // @[RocketTile.scala:147:20] wire [39:0] _core_io_dmem_req_bits_addr; // @[RocketTile.scala:147:20] wire [7:0] _core_io_dmem_req_bits_tag; // @[RocketTile.scala:147:20] wire [4:0] _core_io_dmem_req_bits_cmd; // @[RocketTile.scala:147:20] wire [1:0] _core_io_dmem_req_bits_size; // @[RocketTile.scala:147:20] wire _core_io_dmem_req_bits_signed; // @[RocketTile.scala:147:20] wire [1:0] _core_io_dmem_req_bits_dprv; // @[RocketTile.scala:147:20] wire _core_io_dmem_req_bits_dv; // @[RocketTile.scala:147:20] wire _core_io_dmem_s1_kill; // @[RocketTile.scala:147:20] wire [63:0] _core_io_dmem_s1_data_data; // @[RocketTile.scala:147:20] wire [3:0] _core_io_ptw_ptbr_mode; // @[RocketTile.scala:147:20] wire [43:0] _core_io_ptw_ptbr_ppn; // @[RocketTile.scala:147:20] wire _core_io_ptw_sfence_valid; // @[RocketTile.scala:147:20] wire _core_io_ptw_sfence_bits_rs1; // @[RocketTile.scala:147:20] wire _core_io_ptw_status_debug; // @[RocketTile.scala:147:20] wire [1:0] _core_io_ptw_status_prv; // @[RocketTile.scala:147:20] wire _core_io_ptw_status_mxr; // @[RocketTile.scala:147:20] wire _core_io_ptw_status_sum; // @[RocketTile.scala:147:20] wire _core_io_ptw_pmp_0_cfg_l; // @[RocketTile.scala:147:20] wire [1:0] _core_io_ptw_pmp_0_cfg_a; // @[RocketTile.scala:147:20] wire _core_io_ptw_pmp_0_cfg_x; // @[RocketTile.scala:147:20] wire _core_io_ptw_pmp_0_cfg_w; // @[RocketTile.scala:147:20] wire _core_io_ptw_pmp_0_cfg_r; // @[RocketTile.scala:147:20] wire [29:0] _core_io_ptw_pmp_0_addr; // @[RocketTile.scala:147:20] wire [31:0] _core_io_ptw_pmp_0_mask; // @[RocketTile.scala:147:20] wire _core_io_ptw_pmp_1_cfg_l; // @[RocketTile.scala:147:20] wire [1:0] _core_io_ptw_pmp_1_cfg_a; // @[RocketTile.scala:147:20] wire _core_io_ptw_pmp_1_cfg_x; // @[RocketTile.scala:147:20] wire _core_io_ptw_pmp_1_cfg_w; // @[RocketTile.scala:147:20] wire _core_io_ptw_pmp_1_cfg_r; // @[RocketTile.scala:147:20] wire [29:0] _core_io_ptw_pmp_1_addr; // @[RocketTile.scala:147:20] wire [31:0] _core_io_ptw_pmp_1_mask; // @[RocketTile.scala:147:20] wire _core_io_ptw_pmp_2_cfg_l; // @[RocketTile.scala:147:20] wire [1:0] _core_io_ptw_pmp_2_cfg_a; // @[RocketTile.scala:147:20] wire _core_io_ptw_pmp_2_cfg_x; // @[RocketTile.scala:147:20] wire _core_io_ptw_pmp_2_cfg_w; // @[RocketTile.scala:147:20] wire _core_io_ptw_pmp_2_cfg_r; // @[RocketTile.scala:147:20] wire [29:0] _core_io_ptw_pmp_2_addr; // @[RocketTile.scala:147:20] wire [31:0] _core_io_ptw_pmp_2_mask; // @[RocketTile.scala:147:20] wire _core_io_ptw_pmp_3_cfg_l; // @[RocketTile.scala:147:20] wire [1:0] _core_io_ptw_pmp_3_cfg_a; // @[RocketTile.scala:147:20] wire _core_io_ptw_pmp_3_cfg_x; // @[RocketTile.scala:147:20] wire _core_io_ptw_pmp_3_cfg_w; // @[RocketTile.scala:147:20] wire _core_io_ptw_pmp_3_cfg_r; // @[RocketTile.scala:147:20] wire [29:0] _core_io_ptw_pmp_3_addr; // @[RocketTile.scala:147:20] wire [31:0] _core_io_ptw_pmp_3_mask; // @[RocketTile.scala:147:20] wire _core_io_ptw_pmp_4_cfg_l; // @[RocketTile.scala:147:20] wire [1:0] _core_io_ptw_pmp_4_cfg_a; // @[RocketTile.scala:147:20] wire _core_io_ptw_pmp_4_cfg_x; // @[RocketTile.scala:147:20] wire _core_io_ptw_pmp_4_cfg_w; // @[RocketTile.scala:147:20] wire _core_io_ptw_pmp_4_cfg_r; // @[RocketTile.scala:147:20] wire [29:0] _core_io_ptw_pmp_4_addr; // @[RocketTile.scala:147:20] wire [31:0] _core_io_ptw_pmp_4_mask; // @[RocketTile.scala:147:20] wire _core_io_ptw_pmp_5_cfg_l; // @[RocketTile.scala:147:20] wire [1:0] _core_io_ptw_pmp_5_cfg_a; // @[RocketTile.scala:147:20] wire _core_io_ptw_pmp_5_cfg_x; // @[RocketTile.scala:147:20] wire _core_io_ptw_pmp_5_cfg_w; // @[RocketTile.scala:147:20] wire _core_io_ptw_pmp_5_cfg_r; // @[RocketTile.scala:147:20] wire [29:0] _core_io_ptw_pmp_5_addr; // @[RocketTile.scala:147:20] wire [31:0] _core_io_ptw_pmp_5_mask; // @[RocketTile.scala:147:20] wire _core_io_ptw_pmp_6_cfg_l; // @[RocketTile.scala:147:20] wire [1:0] _core_io_ptw_pmp_6_cfg_a; // @[RocketTile.scala:147:20] wire _core_io_ptw_pmp_6_cfg_x; // @[RocketTile.scala:147:20] wire _core_io_ptw_pmp_6_cfg_w; // @[RocketTile.scala:147:20] wire _core_io_ptw_pmp_6_cfg_r; // @[RocketTile.scala:147:20] wire [29:0] _core_io_ptw_pmp_6_addr; // @[RocketTile.scala:147:20] wire [31:0] _core_io_ptw_pmp_6_mask; // @[RocketTile.scala:147:20] wire _core_io_ptw_pmp_7_cfg_l; // @[RocketTile.scala:147:20] wire [1:0] _core_io_ptw_pmp_7_cfg_a; // @[RocketTile.scala:147:20] wire _core_io_ptw_pmp_7_cfg_x; // @[RocketTile.scala:147:20] wire _core_io_ptw_pmp_7_cfg_w; // @[RocketTile.scala:147:20] wire _core_io_ptw_pmp_7_cfg_r; // @[RocketTile.scala:147:20] wire [29:0] _core_io_ptw_pmp_7_addr; // @[RocketTile.scala:147:20] wire [31:0] _core_io_ptw_pmp_7_mask; // @[RocketTile.scala:147:20] wire [63:0] _core_io_ptw_customCSRs_csrs_0_value; // @[RocketTile.scala:147:20] wire [31:0] _core_io_fpu_inst; // @[RocketTile.scala:147:20] wire [63:0] _core_io_fpu_fromint_data; // @[RocketTile.scala:147:20] wire [2:0] _core_io_fpu_fcsr_rm; // @[RocketTile.scala:147:20] wire [2:0] _core_io_fpu_v_sew; // @[RocketTile.scala:147:20] wire _core_io_fpu_ll_resp_val; // @[RocketTile.scala:147:20] wire [2:0] _core_io_fpu_ll_resp_type; // @[RocketTile.scala:147:20] wire [4:0] _core_io_fpu_ll_resp_tag; // @[RocketTile.scala:147:20] wire [63:0] _core_io_fpu_ll_resp_data; // @[RocketTile.scala:147:20] wire _core_io_fpu_valid; // @[RocketTile.scala:147:20] wire _core_io_fpu_killx; // @[RocketTile.scala:147:20] wire _core_io_fpu_killm; // @[RocketTile.scala:147:20] wire _core_io_wfi; // @[RocketTile.scala:147:20] wire _core_io_vector_status_dv; // @[RocketTile.scala:147:20] wire [1:0] _core_io_vector_status_prv; // @[RocketTile.scala:147:20] wire _core_io_vector_ex_valid; // @[RocketTile.scala:147:20] wire [31:0] _core_io_vector_ex_inst; // @[RocketTile.scala:147:20] wire [39:0] _core_io_vector_ex_pc; // @[RocketTile.scala:147:20] wire [8:0] _core_io_vector_ex_vconfig_vl; // @[RocketTile.scala:147:20] wire _core_io_vector_ex_vconfig_vtype_vill; // @[RocketTile.scala:147:20] wire [54:0] _core_io_vector_ex_vconfig_vtype_reserved; // @[RocketTile.scala:147:20] wire _core_io_vector_ex_vconfig_vtype_vma; // @[RocketTile.scala:147:20] wire _core_io_vector_ex_vconfig_vtype_vta; // @[RocketTile.scala:147:20] wire [2:0] _core_io_vector_ex_vconfig_vtype_vsew; // @[RocketTile.scala:147:20] wire _core_io_vector_ex_vconfig_vtype_vlmul_sign; // @[RocketTile.scala:147:20] wire [1:0] _core_io_vector_ex_vconfig_vtype_vlmul_mag; // @[RocketTile.scala:147:20] wire [7:0] _core_io_vector_ex_vstart; // @[RocketTile.scala:147:20] wire [63:0] _core_io_vector_ex_rs1; // @[RocketTile.scala:147:20] wire [63:0] _core_io_vector_ex_rs2; // @[RocketTile.scala:147:20] wire _core_io_vector_killm; // @[RocketTile.scala:147:20] wire [63:0] _core_io_vector_mem_frs1; // @[RocketTile.scala:147:20] wire _core_io_vector_wb_store_pending; // @[RocketTile.scala:147:20] wire [1:0] _core_io_vector_wb_vxrm; // @[RocketTile.scala:147:20] wire [2:0] _core_io_vector_wb_frm; // @[RocketTile.scala:147:20] wire _core_io_vector_resp_ready; // @[RocketTile.scala:147:20] wire _ptw_io_requestor_0_req_ready; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_resp_valid; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_resp_bits_ae_ptw; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_resp_bits_ae_final; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_resp_bits_pf; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_resp_bits_gf; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_resp_bits_hr; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_resp_bits_hw; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_resp_bits_hx; // @[PTW.scala:802:19] wire [43:0] _ptw_io_requestor_0_resp_bits_pte_ppn; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_resp_bits_pte_d; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_resp_bits_pte_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_resp_bits_pte_g; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_resp_bits_pte_u; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_resp_bits_pte_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_resp_bits_pte_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_resp_bits_pte_r; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_resp_bits_pte_v; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_0_resp_bits_level; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_resp_bits_homogeneous; // @[PTW.scala:802:19] wire [3:0] _ptw_io_requestor_0_ptbr_mode; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_status_debug; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_status_mxr; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_status_sum; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_pmp_0_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_0_pmp_0_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_pmp_0_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_pmp_0_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_pmp_0_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_0_pmp_0_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_0_pmp_0_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_pmp_1_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_0_pmp_1_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_pmp_1_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_pmp_1_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_pmp_1_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_0_pmp_1_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_0_pmp_1_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_pmp_2_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_0_pmp_2_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_pmp_2_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_pmp_2_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_pmp_2_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_0_pmp_2_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_0_pmp_2_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_pmp_3_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_0_pmp_3_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_pmp_3_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_pmp_3_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_pmp_3_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_0_pmp_3_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_0_pmp_3_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_pmp_4_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_0_pmp_4_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_pmp_4_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_pmp_4_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_pmp_4_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_0_pmp_4_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_0_pmp_4_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_pmp_5_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_0_pmp_5_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_pmp_5_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_pmp_5_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_pmp_5_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_0_pmp_5_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_0_pmp_5_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_pmp_6_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_0_pmp_6_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_pmp_6_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_pmp_6_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_pmp_6_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_0_pmp_6_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_0_pmp_6_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_pmp_7_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_0_pmp_7_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_pmp_7_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_pmp_7_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_pmp_7_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_0_pmp_7_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_0_pmp_7_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_req_ready; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_resp_valid; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_resp_bits_ae_ptw; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_resp_bits_ae_final; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_resp_bits_pf; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_resp_bits_gf; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_resp_bits_hr; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_resp_bits_hw; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_resp_bits_hx; // @[PTW.scala:802:19] wire [43:0] _ptw_io_requestor_1_resp_bits_pte_ppn; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_resp_bits_pte_d; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_resp_bits_pte_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_resp_bits_pte_g; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_resp_bits_pte_u; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_resp_bits_pte_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_resp_bits_pte_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_resp_bits_pte_r; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_resp_bits_pte_v; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_1_resp_bits_level; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_resp_bits_homogeneous; // @[PTW.scala:802:19] wire [3:0] _ptw_io_requestor_1_ptbr_mode; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_status_debug; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_1_status_prv; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_pmp_0_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_1_pmp_0_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_pmp_0_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_pmp_0_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_pmp_0_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_1_pmp_0_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_1_pmp_0_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_pmp_1_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_1_pmp_1_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_pmp_1_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_pmp_1_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_pmp_1_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_1_pmp_1_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_1_pmp_1_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_pmp_2_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_1_pmp_2_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_pmp_2_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_pmp_2_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_pmp_2_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_1_pmp_2_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_1_pmp_2_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_pmp_3_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_1_pmp_3_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_pmp_3_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_pmp_3_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_pmp_3_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_1_pmp_3_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_1_pmp_3_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_pmp_4_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_1_pmp_4_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_pmp_4_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_pmp_4_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_pmp_4_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_1_pmp_4_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_1_pmp_4_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_pmp_5_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_1_pmp_5_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_pmp_5_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_pmp_5_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_pmp_5_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_1_pmp_5_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_1_pmp_5_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_pmp_6_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_1_pmp_6_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_pmp_6_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_pmp_6_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_pmp_6_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_1_pmp_6_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_1_pmp_6_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_pmp_7_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_1_pmp_7_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_pmp_7_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_pmp_7_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_pmp_7_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_1_pmp_7_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_1_pmp_7_mask; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_1_customCSRs_csrs_0_value; // @[PTW.scala:802:19] wire _ptw_io_mem_req_valid; // @[PTW.scala:802:19] wire [39:0] _ptw_io_mem_req_bits_addr; // @[PTW.scala:802:19] wire _ptw_io_mem_s1_kill; // @[PTW.scala:802:19] wire _dcacheArb_io_requestor_0_req_ready; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_0_s2_nack; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_0_resp_valid; // @[HellaCache.scala:292:25] wire [63:0] _dcacheArb_io_requestor_0_resp_bits_data; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_0_s2_xcpt_ae_ld; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_1_req_ready; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_1_s2_nack; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_1_resp_valid; // @[HellaCache.scala:292:25] wire [7:0] _dcacheArb_io_requestor_1_resp_bits_tag; // @[HellaCache.scala:292:25] wire [1:0] _dcacheArb_io_requestor_1_resp_bits_size; // @[HellaCache.scala:292:25] wire [63:0] _dcacheArb_io_requestor_1_resp_bits_data; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_1_resp_bits_replay; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_1_resp_bits_has_data; // @[HellaCache.scala:292:25] wire [63:0] _dcacheArb_io_requestor_1_resp_bits_data_word_bypass; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_1_replay_next; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_1_s2_xcpt_ma_ld; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_1_s2_xcpt_ma_st; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_1_s2_xcpt_pf_ld; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_1_s2_xcpt_pf_st; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_1_s2_xcpt_ae_ld; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_1_s2_xcpt_ae_st; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_1_ordered; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_1_store_pending; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_1_perf_release; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_1_perf_grant; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_2_req_ready; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_2_s2_nack; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_2_resp_valid; // @[HellaCache.scala:292:25] wire [7:0] _dcacheArb_io_requestor_2_resp_bits_tag; // @[HellaCache.scala:292:25] wire [63:0] _dcacheArb_io_requestor_2_resp_bits_data_raw; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_2_s2_xcpt_ma_ld; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_2_s2_xcpt_ma_st; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_2_s2_xcpt_pf_ld; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_2_s2_xcpt_pf_st; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_2_s2_xcpt_ae_ld; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_2_s2_xcpt_ae_st; // @[HellaCache.scala:292:25] wire _dcacheArb_io_mem_req_valid; // @[HellaCache.scala:292:25] wire [39:0] _dcacheArb_io_mem_req_bits_addr; // @[HellaCache.scala:292:25] wire [7:0] _dcacheArb_io_mem_req_bits_tag; // @[HellaCache.scala:292:25] wire [4:0] _dcacheArb_io_mem_req_bits_cmd; // @[HellaCache.scala:292:25] wire [1:0] _dcacheArb_io_mem_req_bits_size; // @[HellaCache.scala:292:25] wire _dcacheArb_io_mem_req_bits_signed; // @[HellaCache.scala:292:25] wire [1:0] _dcacheArb_io_mem_req_bits_dprv; // @[HellaCache.scala:292:25] wire _dcacheArb_io_mem_req_bits_dv; // @[HellaCache.scala:292:25] wire _dcacheArb_io_mem_req_bits_phys; // @[HellaCache.scala:292:25] wire _dcacheArb_io_mem_req_bits_no_alloc; // @[HellaCache.scala:292:25] wire _dcacheArb_io_mem_req_bits_no_xcpt; // @[HellaCache.scala:292:25] wire [7:0] _dcacheArb_io_mem_req_bits_mask; // @[HellaCache.scala:292:25] wire _dcacheArb_io_mem_s1_kill; // @[HellaCache.scala:292:25] wire [63:0] _dcacheArb_io_mem_s1_data_data; // @[HellaCache.scala:292:25] wire [7:0] _dcacheArb_io_mem_s1_data_mask; // @[HellaCache.scala:292:25] wire _fpArb_io_in_req_0_ready; // @[RocketTile.scala:247:25] wire _fpArb_io_in_resp_0_valid; // @[RocketTile.scala:247:25] wire [64:0] _fpArb_io_in_resp_0_bits_data; // @[RocketTile.scala:247:25] wire _fpArb_io_out_req_valid; // @[RocketTile.scala:247:25] wire _fpArb_io_out_req_bits_ren2; // @[RocketTile.scala:247:25] wire [1:0] _fpArb_io_out_req_bits_typeTagIn; // @[RocketTile.scala:247:25] wire [1:0] _fpArb_io_out_req_bits_typeTagOut; // @[RocketTile.scala:247:25] wire _fpArb_io_out_req_bits_fromint; // @[RocketTile.scala:247:25] wire _fpArb_io_out_req_bits_toint; // @[RocketTile.scala:247:25] wire _fpArb_io_out_req_bits_fastpipe; // @[RocketTile.scala:247:25] wire _fpArb_io_out_req_bits_div; // @[RocketTile.scala:247:25] wire _fpArb_io_out_req_bits_sqrt; // @[RocketTile.scala:247:25] wire _fpArb_io_out_req_bits_wflags; // @[RocketTile.scala:247:25] wire [2:0] _fpArb_io_out_req_bits_rm; // @[RocketTile.scala:247:25] wire [1:0] _fpArb_io_out_req_bits_typ; // @[RocketTile.scala:247:25] wire [64:0] _fpArb_io_out_req_bits_in1; // @[RocketTile.scala:247:25] wire [64:0] _fpArb_io_out_req_bits_in2; // @[RocketTile.scala:247:25] wire _fpuOpt_io_fcsr_flags_valid; // @[RocketTile.scala:242:62] wire [4:0] _fpuOpt_io_fcsr_flags_bits; // @[RocketTile.scala:242:62] wire [63:0] _fpuOpt_io_store_data; // @[RocketTile.scala:242:62] wire [63:0] _fpuOpt_io_toint_data; // @[RocketTile.scala:242:62] wire _fpuOpt_io_fcsr_rdy; // @[RocketTile.scala:242:62] wire _fpuOpt_io_nack_mem; // @[RocketTile.scala:242:62] wire _fpuOpt_io_illegal_rm; // @[RocketTile.scala:242:62] wire _fpuOpt_io_dec_wen; // @[RocketTile.scala:242:62] wire _fpuOpt_io_dec_ren1; // @[RocketTile.scala:242:62] wire _fpuOpt_io_dec_ren2; // @[RocketTile.scala:242:62] wire _fpuOpt_io_dec_ren3; // @[RocketTile.scala:242:62] wire _fpuOpt_io_sboard_set; // @[RocketTile.scala:242:62] wire _fpuOpt_io_sboard_clr; // @[RocketTile.scala:242:62] wire [4:0] _fpuOpt_io_sboard_clra; // @[RocketTile.scala:242:62] wire _fpuOpt_io_cp_req_ready; // @[RocketTile.scala:242:62] wire _fpuOpt_io_cp_resp_valid; // @[RocketTile.scala:242:62] wire [64:0] _fpuOpt_io_cp_resp_bits_data; // @[RocketTile.scala:242:62] wire _vector_unit_auto_atl_out_a_valid; // @[RocketTile.scala:117:65] wire [2:0] _vector_unit_auto_atl_out_a_bits_opcode; // @[RocketTile.scala:117:65] wire [2:0] _vector_unit_auto_atl_out_a_bits_param; // @[RocketTile.scala:117:65] wire [3:0] _vector_unit_auto_atl_out_a_bits_size; // @[RocketTile.scala:117:65] wire [4:0] _vector_unit_auto_atl_out_a_bits_source; // @[RocketTile.scala:117:65] wire [31:0] _vector_unit_auto_atl_out_a_bits_address; // @[RocketTile.scala:117:65] wire [7:0] _vector_unit_auto_atl_out_a_bits_mask; // @[RocketTile.scala:117:65] wire [63:0] _vector_unit_auto_atl_out_a_bits_data; // @[RocketTile.scala:117:65] wire _vector_unit_auto_atl_out_a_bits_corrupt; // @[RocketTile.scala:117:65] wire _vector_unit_auto_atl_out_d_ready; // @[RocketTile.scala:117:65] wire _vector_unit_io_core_ex_ready; // @[RocketTile.scala:117:65] wire _vector_unit_io_core_mem_block_mem; // @[RocketTile.scala:117:65] wire _vector_unit_io_core_mem_block_all; // @[RocketTile.scala:117:65] wire _vector_unit_io_core_wb_replay; // @[RocketTile.scala:117:65] wire _vector_unit_io_core_wb_retire; // @[RocketTile.scala:117:65] wire [31:0] _vector_unit_io_core_wb_inst; // @[RocketTile.scala:117:65] wire [39:0] _vector_unit_io_core_wb_pc; // @[RocketTile.scala:117:65] wire _vector_unit_io_core_wb_xcpt; // @[RocketTile.scala:117:65] wire [4:0] _vector_unit_io_core_wb_cause; // @[RocketTile.scala:117:65] wire [39:0] _vector_unit_io_core_wb_tval; // @[RocketTile.scala:117:65] wire _vector_unit_io_core_resp_valid; // @[RocketTile.scala:117:65] wire _vector_unit_io_core_resp_bits_fp; // @[RocketTile.scala:117:65] wire [1:0] _vector_unit_io_core_resp_bits_size; // @[RocketTile.scala:117:65] wire [4:0] _vector_unit_io_core_resp_bits_rd; // @[RocketTile.scala:117:65] wire [63:0] _vector_unit_io_core_resp_bits_data; // @[RocketTile.scala:117:65] wire _vector_unit_io_core_set_vstart_valid; // @[RocketTile.scala:117:65] wire [7:0] _vector_unit_io_core_set_vstart_bits; // @[RocketTile.scala:117:65] wire _vector_unit_io_core_set_vxsat; // @[RocketTile.scala:117:65] wire _vector_unit_io_core_set_vconfig_valid; // @[RocketTile.scala:117:65] wire [8:0] _vector_unit_io_core_set_vconfig_bits_vl; // @[RocketTile.scala:117:65] wire _vector_unit_io_core_set_vconfig_bits_vtype_vill; // @[RocketTile.scala:117:65] wire [54:0] _vector_unit_io_core_set_vconfig_bits_vtype_reserved; // @[RocketTile.scala:117:65] wire _vector_unit_io_core_set_vconfig_bits_vtype_vma; // @[RocketTile.scala:117:65] wire _vector_unit_io_core_set_vconfig_bits_vtype_vta; // @[RocketTile.scala:117:65] wire [2:0] _vector_unit_io_core_set_vconfig_bits_vtype_vsew; // @[RocketTile.scala:117:65] wire _vector_unit_io_core_set_vconfig_bits_vtype_vlmul_sign; // @[RocketTile.scala:117:65] wire [1:0] _vector_unit_io_core_set_vconfig_bits_vtype_vlmul_mag; // @[RocketTile.scala:117:65] wire _vector_unit_io_core_set_fflags_valid; // @[RocketTile.scala:117:65] wire [4:0] _vector_unit_io_core_set_fflags_bits; // @[RocketTile.scala:117:65] wire _vector_unit_io_core_trap_check_busy; // @[RocketTile.scala:117:65] wire _vector_unit_io_core_backend_busy; // @[RocketTile.scala:117:65] wire _vector_unit_io_tlb_req_valid; // @[RocketTile.scala:117:65] wire [39:0] _vector_unit_io_tlb_req_bits_vaddr; // @[RocketTile.scala:117:65] wire [1:0] _vector_unit_io_tlb_req_bits_size; // @[RocketTile.scala:117:65] wire [4:0] _vector_unit_io_tlb_req_bits_cmd; // @[RocketTile.scala:117:65] wire [1:0] _vector_unit_io_tlb_req_bits_prv; // @[RocketTile.scala:117:65] wire _vector_unit_io_dmem_req_valid; // @[RocketTile.scala:117:65] wire [39:0] _vector_unit_io_dmem_req_bits_addr; // @[RocketTile.scala:117:65] wire [7:0] _vector_unit_io_dmem_req_bits_tag; // @[RocketTile.scala:117:65] wire [4:0] _vector_unit_io_dmem_req_bits_cmd; // @[RocketTile.scala:117:65] wire [1:0] _vector_unit_io_dmem_req_bits_size; // @[RocketTile.scala:117:65] wire _vector_unit_io_dmem_req_bits_signed; // @[RocketTile.scala:117:65] wire [1:0] _vector_unit_io_dmem_req_bits_dprv; // @[RocketTile.scala:117:65] wire _vector_unit_io_dmem_req_bits_dv; // @[RocketTile.scala:117:65] wire _vector_unit_io_dmem_req_bits_phys; // @[RocketTile.scala:117:65] wire _vector_unit_io_dmem_req_bits_no_alloc; // @[RocketTile.scala:117:65] wire _vector_unit_io_dmem_req_bits_no_xcpt; // @[RocketTile.scala:117:65] wire [7:0] _vector_unit_io_dmem_req_bits_mask; // @[RocketTile.scala:117:65] wire [63:0] _vector_unit_io_dmem_s1_data_data; // @[RocketTile.scala:117:65] wire [7:0] _vector_unit_io_dmem_s1_data_mask; // @[RocketTile.scala:117:65] wire _vector_unit_io_fp_req_valid; // @[RocketTile.scala:117:65] wire _vector_unit_io_fp_req_bits_ren2; // @[RocketTile.scala:117:65] wire [1:0] _vector_unit_io_fp_req_bits_typeTagIn; // @[RocketTile.scala:117:65] wire [1:0] _vector_unit_io_fp_req_bits_typeTagOut; // @[RocketTile.scala:117:65] wire _vector_unit_io_fp_req_bits_fromint; // @[RocketTile.scala:117:65] wire _vector_unit_io_fp_req_bits_toint; // @[RocketTile.scala:117:65] wire _vector_unit_io_fp_req_bits_fastpipe; // @[RocketTile.scala:117:65] wire _vector_unit_io_fp_req_bits_div; // @[RocketTile.scala:117:65] wire _vector_unit_io_fp_req_bits_sqrt; // @[RocketTile.scala:117:65] wire _vector_unit_io_fp_req_bits_wflags; // @[RocketTile.scala:117:65] wire [2:0] _vector_unit_io_fp_req_bits_rm; // @[RocketTile.scala:117:65] wire [1:0] _vector_unit_io_fp_req_bits_typ; // @[RocketTile.scala:117:65] wire [64:0] _vector_unit_io_fp_req_bits_in1; // @[RocketTile.scala:117:65] wire [64:0] _vector_unit_io_fp_req_bits_in2; // @[RocketTile.scala:117:65] wire _frontend_auto_icache_master_out_a_valid; // @[Frontend.scala:393:28] wire [31:0] _frontend_auto_icache_master_out_a_bits_address; // @[Frontend.scala:393:28] wire _frontend_io_cpu_resp_valid; // @[Frontend.scala:393:28] wire _frontend_io_cpu_resp_bits_btb_taken; // @[Frontend.scala:393:28] wire _frontend_io_cpu_resp_bits_btb_bridx; // @[Frontend.scala:393:28] wire [4:0] _frontend_io_cpu_resp_bits_btb_entry; // @[Frontend.scala:393:28] wire [7:0] _frontend_io_cpu_resp_bits_btb_bht_history; // @[Frontend.scala:393:28] wire [39:0] _frontend_io_cpu_resp_bits_pc; // @[Frontend.scala:393:28] wire [31:0] _frontend_io_cpu_resp_bits_data; // @[Frontend.scala:393:28] wire _frontend_io_cpu_resp_bits_xcpt_pf_inst; // @[Frontend.scala:393:28] wire _frontend_io_cpu_resp_bits_xcpt_gf_inst; // @[Frontend.scala:393:28] wire _frontend_io_cpu_resp_bits_xcpt_ae_inst; // @[Frontend.scala:393:28] wire _frontend_io_cpu_resp_bits_replay; // @[Frontend.scala:393:28] wire _frontend_io_ptw_req_valid; // @[Frontend.scala:393:28] wire _frontend_io_ptw_req_bits_valid; // @[Frontend.scala:393:28] wire [26:0] _frontend_io_ptw_req_bits_bits_addr; // @[Frontend.scala:393:28] wire _frontend_io_ptw_req_bits_bits_need_gpa; // @[Frontend.scala:393:28] wire _dcache_auto_out_a_valid; // @[HellaCache.scala:278:43] wire [2:0] _dcache_auto_out_a_bits_opcode; // @[HellaCache.scala:278:43] wire [2:0] _dcache_auto_out_a_bits_param; // @[HellaCache.scala:278:43] wire [3:0] _dcache_auto_out_a_bits_size; // @[HellaCache.scala:278:43] wire _dcache_auto_out_a_bits_source; // @[HellaCache.scala:278:43] wire [31:0] _dcache_auto_out_a_bits_address; // @[HellaCache.scala:278:43] wire [7:0] _dcache_auto_out_a_bits_mask; // @[HellaCache.scala:278:43] wire [63:0] _dcache_auto_out_a_bits_data; // @[HellaCache.scala:278:43] wire _dcache_auto_out_b_ready; // @[HellaCache.scala:278:43] wire _dcache_auto_out_c_valid; // @[HellaCache.scala:278:43] wire [2:0] _dcache_auto_out_c_bits_opcode; // @[HellaCache.scala:278:43] wire [2:0] _dcache_auto_out_c_bits_param; // @[HellaCache.scala:278:43] wire [3:0] _dcache_auto_out_c_bits_size; // @[HellaCache.scala:278:43] wire _dcache_auto_out_c_bits_source; // @[HellaCache.scala:278:43] wire [31:0] _dcache_auto_out_c_bits_address; // @[HellaCache.scala:278:43] wire [63:0] _dcache_auto_out_c_bits_data; // @[HellaCache.scala:278:43] wire _dcache_auto_out_d_ready; // @[HellaCache.scala:278:43] wire _dcache_auto_out_e_valid; // @[HellaCache.scala:278:43] wire [2:0] _dcache_auto_out_e_bits_sink; // @[HellaCache.scala:278:43] wire _dcache_io_cpu_req_ready; // @[HellaCache.scala:278:43] wire _dcache_io_cpu_s2_nack; // @[HellaCache.scala:278:43] wire _dcache_io_cpu_resp_valid; // @[HellaCache.scala:278:43] wire [7:0] _dcache_io_cpu_resp_bits_tag; // @[HellaCache.scala:278:43] wire [1:0] _dcache_io_cpu_resp_bits_size; // @[HellaCache.scala:278:43] wire [63:0] _dcache_io_cpu_resp_bits_data; // @[HellaCache.scala:278:43] wire _dcache_io_cpu_resp_bits_replay; // @[HellaCache.scala:278:43] wire _dcache_io_cpu_resp_bits_has_data; // @[HellaCache.scala:278:43] wire [63:0] _dcache_io_cpu_resp_bits_data_word_bypass; // @[HellaCache.scala:278:43] wire [63:0] _dcache_io_cpu_resp_bits_data_raw; // @[HellaCache.scala:278:43] wire _dcache_io_cpu_replay_next; // @[HellaCache.scala:278:43] wire _dcache_io_cpu_s2_xcpt_ma_ld; // @[HellaCache.scala:278:43] wire _dcache_io_cpu_s2_xcpt_ma_st; // @[HellaCache.scala:278:43] wire _dcache_io_cpu_s2_xcpt_pf_ld; // @[HellaCache.scala:278:43] wire _dcache_io_cpu_s2_xcpt_pf_st; // @[HellaCache.scala:278:43] wire _dcache_io_cpu_s2_xcpt_ae_ld; // @[HellaCache.scala:278:43] wire _dcache_io_cpu_s2_xcpt_ae_st; // @[HellaCache.scala:278:43] wire _dcache_io_cpu_ordered; // @[HellaCache.scala:278:43] wire _dcache_io_cpu_store_pending; // @[HellaCache.scala:278:43] wire _dcache_io_cpu_perf_release; // @[HellaCache.scala:278:43] wire _dcache_io_cpu_perf_grant; // @[HellaCache.scala:278:43] wire _dcache_io_ptw_req_valid; // @[HellaCache.scala:278:43] wire [26:0] _dcache_io_ptw_req_bits_bits_addr; // @[HellaCache.scala:278:43] wire _dcache_io_ptw_req_bits_bits_need_gpa; // @[HellaCache.scala:278:43] wire _dcache_io_tlb_port_s1_resp_miss; // @[HellaCache.scala:278:43] wire [31:0] _dcache_io_tlb_port_s1_resp_paddr; // @[HellaCache.scala:278:43] wire _dcache_io_tlb_port_s1_resp_pf_ld; // @[HellaCache.scala:278:43] wire _dcache_io_tlb_port_s1_resp_pf_st; // @[HellaCache.scala:278:43] wire _dcache_io_tlb_port_s1_resp_ae_ld; // @[HellaCache.scala:278:43] wire _dcache_io_tlb_port_s1_resp_ae_st; // @[HellaCache.scala:278:43] wire _dcache_io_tlb_port_s1_resp_ma_ld; // @[HellaCache.scala:278:43] wire _dcache_io_tlb_port_s1_resp_ma_st; // @[HellaCache.scala:278:43] wire [4:0] _dcache_io_tlb_port_s1_resp_cmd; // @[HellaCache.scala:278:43] wire _intXbar_auto_anon_out_0; // @[HierarchicalElement.scala:57:37] wire _intXbar_auto_anon_out_1; // @[HierarchicalElement.scala:57:37] wire _intXbar_auto_anon_out_2; // @[HierarchicalElement.scala:57:37] wire _intXbar_auto_anon_out_3; // @[HierarchicalElement.scala:57:37] wire _intXbar_auto_anon_out_4; // @[HierarchicalElement.scala:57:37] wire _tlMasterXbar_auto_anon_in_2_a_ready; // @[HierarchicalElement.scala:55:42] wire _tlMasterXbar_auto_anon_in_2_d_valid; // @[HierarchicalElement.scala:55:42] wire [2:0] _tlMasterXbar_auto_anon_in_2_d_bits_opcode; // @[HierarchicalElement.scala:55:42] wire [1:0] _tlMasterXbar_auto_anon_in_2_d_bits_param; // @[HierarchicalElement.scala:55:42] wire [3:0] _tlMasterXbar_auto_anon_in_2_d_bits_size; // @[HierarchicalElement.scala:55:42] wire [4:0] _tlMasterXbar_auto_anon_in_2_d_bits_source; // @[HierarchicalElement.scala:55:42] wire [2:0] _tlMasterXbar_auto_anon_in_2_d_bits_sink; // @[HierarchicalElement.scala:55:42] wire _tlMasterXbar_auto_anon_in_2_d_bits_denied; // @[HierarchicalElement.scala:55:42] wire [63:0] _tlMasterXbar_auto_anon_in_2_d_bits_data; // @[HierarchicalElement.scala:55:42] wire _tlMasterXbar_auto_anon_in_2_d_bits_corrupt; // @[HierarchicalElement.scala:55:42] wire _tlMasterXbar_auto_anon_in_1_a_ready; // @[HierarchicalElement.scala:55:42] wire _tlMasterXbar_auto_anon_in_1_d_valid; // @[HierarchicalElement.scala:55:42] wire [2:0] _tlMasterXbar_auto_anon_in_1_d_bits_opcode; // @[HierarchicalElement.scala:55:42] wire [3:0] _tlMasterXbar_auto_anon_in_1_d_bits_size; // @[HierarchicalElement.scala:55:42] wire [63:0] _tlMasterXbar_auto_anon_in_1_d_bits_data; // @[HierarchicalElement.scala:55:42] wire _tlMasterXbar_auto_anon_in_1_d_bits_corrupt; // @[HierarchicalElement.scala:55:42] wire _tlMasterXbar_auto_anon_in_0_a_ready; // @[HierarchicalElement.scala:55:42] wire _tlMasterXbar_auto_anon_in_0_b_valid; // @[HierarchicalElement.scala:55:42] wire [1:0] _tlMasterXbar_auto_anon_in_0_b_bits_param; // @[HierarchicalElement.scala:55:42] wire [3:0] _tlMasterXbar_auto_anon_in_0_b_bits_size; // @[HierarchicalElement.scala:55:42] wire _tlMasterXbar_auto_anon_in_0_b_bits_source; // @[HierarchicalElement.scala:55:42] wire [31:0] _tlMasterXbar_auto_anon_in_0_b_bits_address; // @[HierarchicalElement.scala:55:42] wire _tlMasterXbar_auto_anon_in_0_c_ready; // @[HierarchicalElement.scala:55:42] wire _tlMasterXbar_auto_anon_in_0_d_valid; // @[HierarchicalElement.scala:55:42] wire [2:0] _tlMasterXbar_auto_anon_in_0_d_bits_opcode; // @[HierarchicalElement.scala:55:42] wire [1:0] _tlMasterXbar_auto_anon_in_0_d_bits_param; // @[HierarchicalElement.scala:55:42] wire [3:0] _tlMasterXbar_auto_anon_in_0_d_bits_size; // @[HierarchicalElement.scala:55:42] wire _tlMasterXbar_auto_anon_in_0_d_bits_source; // @[HierarchicalElement.scala:55:42] wire [2:0] _tlMasterXbar_auto_anon_in_0_d_bits_sink; // @[HierarchicalElement.scala:55:42] wire _tlMasterXbar_auto_anon_in_0_d_bits_denied; // @[HierarchicalElement.scala:55:42] wire [63:0] _tlMasterXbar_auto_anon_in_0_d_bits_data; // @[HierarchicalElement.scala:55:42] wire _tlMasterXbar_auto_anon_in_0_e_ready; // @[HierarchicalElement.scala:55:42] reg wfiNodeOut_0_REG; // @[Interrupts.scala:131:36] always @(posedge clock) begin // @[RocketTile.scala:141:7] if (reset) // @[RocketTile.scala:141:7] wfiNodeOut_0_REG <= 1'h0; // @[RocketTile.scala:141:7] else // @[RocketTile.scala:141:7] wfiNodeOut_0_REG <= _core_io_wfi; // @[RocketTile.scala:147:20] always @(posedge)
Generate the Verilog code corresponding to the following Chisel files. File INToRecFN.scala: /============================================================================ This Chisel source file is part of a pre-release version of the HardFloat IEEE Floating-Point Arithmetic Package, by John R. Hauser (with some contributions from Yunsup Lee and Andrew Waterman, mainly concerning testing). Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of California. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions, and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions, and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the University nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. =============================================================================/ package hardfloat import chisel3._ import consts._ class INToRecFN(intWidth: Int, expWidth: Int, sigWidth: Int) extends RawModule { override def desiredName = s"INToRecFN_i${intWidth}_e${expWidth}_s${sigWidth}" val io = IO(new Bundle { val signedIn = Input(Bool()) val in = Input(Bits(intWidth.W)) val roundingMode = Input(UInt(3.W)) val detectTininess = Input(UInt(1.W)) val out = Output(Bits((expWidth + sigWidth + 1).W)) val exceptionFlags = Output(Bits(5.W)) }) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val intAsRawFloat = rawFloatFromIN(io.signedIn, io.in); val roundAnyRawFNToRecFN = Module( new RoundAnyRawFNToRecFN( intAsRawFloat.expWidth, intWidth, expWidth, sigWidth, flRoundOpt_sigMSBitAlwaysZero \| flRoundOpt_neverUnderflows )) roundAnyRawFNToRecFN.io.invalidExc := false.B roundAnyRawFNToRecFN.io.infiniteExc := false.B roundAnyRawFNToRecFN.io.in := intAsRawFloat roundAnyRawFNToRecFN.io.roundingMode := io.roundingMode roundAnyRawFNToRecFN.io.detectTininess := io.detectTininess io.out := roundAnyRawFNToRecFN.io.out io.exceptionFlags := roundAnyRawFNToRecFN.io.exceptionFlags } File primitives.scala: /============================================================================ This Chisel source file is part of a pre-release version of the HardFloat IEEE Floating-Point Arithmetic Package, by John R. Hauser (with some contributions from Yunsup Lee and Andrew Waterman, mainly concerning testing). Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the University of California. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions, and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions, and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the University nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. =============================================================================/ package hardfloat import chisel3._ import chisel3.util._ //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- object lowMask { def apply(in: UInt, topBound: BigInt, bottomBound: BigInt): UInt = { require(topBound != bottomBound) val numInVals = BigInt(1)<<in.getWidth if (topBound < bottomBound) { lowMask(~in, numInVals - 1 - topBound, numInVals - 1 - bottomBound) } else if (numInVals > 64 /* Empirical /) { // For simulation performance, we should avoid generating // exteremely wide shifters, so we divide and conquer. // Empirically, this does not impact synthesis QoR. val mid = numInVals / 2 val msb = in(in.getWidth - 1) val lsbs = in(in.getWidth - 2, 0) if (mid < topBound) { if (mid <= bottomBound) { Mux(msb, lowMask(lsbs, topBound - mid, bottomBound - mid), 0.U ) } else { Mux(msb, lowMask(lsbs, topBound - mid, 0) ## ((BigInt(1)<<(mid - bottomBound).toInt) - 1).U, lowMask(lsbs, mid, bottomBound) ) } } else { ~Mux(msb, 0.U, ~lowMask(lsbs, topBound, bottomBound)) } } else { val shift = (BigInt(-1)<<numInVals.toInt).S>>in Reverse( shift( (numInVals - 1 - bottomBound).toInt, (numInVals - topBound).toInt ) ) } } } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- object countLeadingZeros { def apply(in: UInt): UInt = PriorityEncoder(in.asBools.reverse) } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- object orReduceBy2 { def apply(in: UInt): UInt = { val reducedWidth = (in.getWidth + 1)>>1 val reducedVec = Wire(Vec(reducedWidth, Bool())) for (ix <- 0 until reducedWidth - 1) { reducedVec(ix) := in(ix 2 + 1, ix * 2).orR } reducedVec(reducedWidth - 1) := in(in.getWidth - 1, (reducedWidth - 1) * 2).orR reducedVec.asUInt } } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- object orReduceBy4 { def apply(in: UInt): UInt = { val reducedWidth = (in.getWidth + 3)>>2 val reducedVec = Wire(Vec(reducedWidth, Bool())) for (ix <- 0 until reducedWidth - 1) { reducedVec(ix) := in(ix * 4 + 3, ix * 4).orR } reducedVec(reducedWidth - 1) := in(in.getWidth - 1, (reducedWidth - 1) * 4).orR reducedVec.asUInt } } File rawFloatFromIN.scala: /============================================================================ This Chisel source file is part of a pre-release version of the HardFloat IEEE Floating-Point Arithmetic Package, by John R. Hauser (with some contributions from Yunsup Lee and Andrew Waterman, mainly concerning testing). Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the University of California. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions, and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions, and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the University nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. =============================================================================/ package hardfloat import chisel3._ import chisel3.util._ object rawFloatFromIN { def apply(signedIn: Bool, in: Bits): RawFloat = { val expWidth = log2Up(in.getWidth) + 1 //*** CHANGE THIS; CAN BE VERY LARGE: val extIntWidth = 1<<(expWidth - 1) val sign = signedIn && in(in.getWidth - 1) val absIn = Mux(sign, -in.asUInt, in.asUInt) val extAbsIn = (0.U(extIntWidth.W) ## absIn)(extIntWidth - 1, 0) val adjustedNormDist = countLeadingZeros(extAbsIn) val sig = (extAbsIn<<adjustedNormDist)( extIntWidth - 1, extIntWidth - in.getWidth) val out = Wire(new RawFloat(expWidth, in.getWidth)) out.isNaN := false.B out.isInf := false.B out.isZero := ! sig(in.getWidth - 1) out.sign := sign out.sExp := (2.U(2.W) ## ~adjustedNormDist(expWidth - 2, 0)).zext out.sig := sig out } }	module INToRecFN_i1_e8_s24_15(); // @[INToRecFN.scala:43:7] wire [1:0] _intAsRawFloat_absIn_T = 2'h3; // @[rawFloatFromIN.scala:52:31] wire [2:0] _intAsRawFloat_extAbsIn_T = 3'h1; // @[rawFloatFromIN.scala:53:44] wire [2:0] _intAsRawFloat_sig_T = 3'h2; // @[rawFloatFromIN.scala:56:22] wire [2:0] _intAsRawFloat_out_sExp_T_2 = 3'h4; // @[rawFloatFromIN.scala:64:33] wire [3:0] intAsRawFloat_sExp = 4'h4; // @[rawFloatFromIN.scala:59:23, :64:72] wire [3:0] _intAsRawFloat_out_sExp_T_3 = 4'h4; // @[rawFloatFromIN.scala:59:23, :64:72] wire [1:0] intAsRawFloat_extAbsIn = 2'h1; // @[rawFloatFromIN.scala:53:53, :59:23, :65:20] wire [1:0] intAsRawFloat_sig = 2'h1; // @[rawFloatFromIN.scala:53:53, :59:23, :65:20] wire [4:0] io_exceptionFlags = 5'h0; // @[INToRecFN.scala:43:7, :46:16, :60:15] wire [32:0] io_out = 33'h80000000; // @[INToRecFN.scala:43:7, :46:16, :60:15] wire [2:0] io_roundingMode = 3'h0; // @[INToRecFN.scala:43:7, :46:16, :60:15] wire io_in = 1'h1; // @[Mux.scala:50:70] wire io_detectTininess = 1'h1; // @[Mux.scala:50:70] wire _intAsRawFloat_sign_T = 1'h1; // @[Mux.scala:50:70] wire _intAsRawFloat_absIn_T_1 = 1'h1; // @[Mux.scala:50:70] wire intAsRawFloat_absIn = 1'h1; // @[Mux.scala:50:70] wire _intAsRawFloat_adjustedNormDist_T = 1'h1; // @[Mux.scala:50:70] wire intAsRawFloat_adjustedNormDist = 1'h1; // @[Mux.scala:50:70] wire intAsRawFloat_sig_0 = 1'h1; // @[Mux.scala:50:70] wire _intAsRawFloat_out_isZero_T = 1'h1; // @[Mux.scala:50:70] wire _intAsRawFloat_out_sExp_T = 1'h1; // @[Mux.scala:50:70] wire io_signedIn = 1'h0; // @[INToRecFN.scala:43:7] wire intAsRawFloat_sign = 1'h0; // @[rawFloatFromIN.scala:51:29] wire _intAsRawFloat_adjustedNormDist_T_1 = 1'h0; // @[primitives.scala:91:52] wire intAsRawFloat_isNaN = 1'h0; // @[rawFloatFromIN.scala:59:23] wire intAsRawFloat_isInf = 1'h0; // @[rawFloatFromIN.scala:59:23] wire intAsRawFloat_isZero = 1'h0; // @[rawFloatFromIN.scala:59:23] wire intAsRawFloat_sign_0 = 1'h0; // @[rawFloatFromIN.scala:59:23] wire _intAsRawFloat_out_isZero_T_1 = 1'h0; // @[rawFloatFromIN.scala:62:23] wire _intAsRawFloat_out_sExp_T_1 = 1'h0; // @[rawFloatFromIN.scala:64:36] RoundAnyRawFNToRecFN_ie2_is1_oe8_os24_15 roundAnyRawFNToRecFN (); // @[INToRecFN.scala:60:15] endmodule
Generate the Verilog code corresponding to the following Chisel files. File ExecutionUnit.scala: package saturn.exu import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config._ import freechips.rocketchip.rocket._ import freechips.rocketchip.util._ import freechips.rocketchip.tile._ import saturn.common._ class ExecutionUnit(genFUs: Seq[FunctionalUnitFactory])(implicit p: Parameters) extends CoreModule()(p) with HasVectorParams { val fus = genFUs.map(gen => Module(gen.generate(p))) val pipe_fus: Seq[PipelinedFunctionalUnit] = fus.collect { case p: PipelinedFunctionalUnit => p } val iter_fus: Seq[IterativeFunctionalUnit] = fus.collect { case i: IterativeFunctionalUnit => i } val pipe_depth = (pipe_fus.map(_.depth) :+ 0).max val io = IO(new Bundle { val iss = Flipped(Decoupled(new ExecuteMicroOp)) val iter_hazards = Output(Vec(iter_fus.size, Valid(new PipeHazard(pipe_depth)))) val iter_write = Decoupled(new VectorWrite(dLen)) val pipe_write = Output(Valid(new VectorWrite(dLen))) val acc_write = Output(Valid(new VectorWrite(dLen))) val scalar_write = Decoupled(new ScalarWrite) val pipe_hazards = Output(Vec(pipe_depth, Valid(new PipeHazard(pipe_depth)))) val issue_pipe_latency = Output(UInt((log2Ceil(pipe_depth) + 1).W)) val shared_fp_req = Decoupled(new FPInput()) val shared_fp_resp = Flipped(Valid(new FPResult())) val set_vxsat = Output(Bool()) val set_fflags = Output(Valid(UInt(5.W))) val busy = Output(Bool()) }) val sharedFPUnits = fus.collect { case fp: HasSharedFPUIO => fp } val hasSharedFPUnits = sharedFPUnits.size > 0 io.shared_fp_req.valid := false.B io.shared_fp_req.bits := DontCare if (sharedFPUnits.size > 0) { val shared_fp_arb = Module(new Arbiter(new FPInput, sharedFPUnits.size)) for ((u, i) <- sharedFPUnits.zipWithIndex) { val otherUnits = sharedFPUnits.zipWithIndex.filter(_._2 != i).map(_._1) val other_busy = otherUnits.map(_.io_fp_active).orR u.io_fp_req.ready := shared_fp_arb.io.in(i).ready && !other_busy shared_fp_arb.io.in(i).valid := u.io_fp_req.valid && !other_busy shared_fp_arb.io.in(i).bits := u.io_fp_req.bits u.io_fp_resp := io.shared_fp_resp } io.shared_fp_req <> shared_fp_arb.io.out } val pipe_stall = WireInit(false.B) fus.foreach { fu => fu.io.iss.op := io.iss.bits fu.io.iss.valid := io.iss.valid && !pipe_stall } val pipe_write_hazard = WireInit(false.B) val readies = fus.map(_.io.iss.ready) io.iss.ready := readies.orR && !pipe_write_hazard && !pipe_stall when (io.iss.valid) { assert(PopCount(readies) <= 1.U) } io.issue_pipe_latency := Mux1H(pipe_fus.map(_.io.iss.ready), pipe_fus.map(_.depth.U)) val pipe_write = WireInit(false.B) io.pipe_write.valid := false.B io.pipe_write.bits := DontCare io.iter_write.valid := false.B io.iter_write.bits := DontCare io.acc_write.valid := false.B io.acc_write.bits := DontCare io.busy := false.B io.set_vxsat := fus.map(_.io.set_vxsat).orR io.set_fflags.valid := fus.map(_.io.set_fflags.valid).orR io.set_fflags.bits := fus.map(f => Mux(f.io.set_fflags.valid, f.io.set_fflags.bits, 0.U)).reduce(_\|_) val scalar_write_arb = Module(new Arbiter(new ScalarWrite, fus.size)) scalar_write_arb.io.in.zip(fus.map(_.io.scalar_write)).foreach { case (l, r) => l <> r } io.scalar_write <> scalar_write_arb.io.out if (pipe_fus.size > 0) { val pipe_iss_depth = Mux1H(pipe_fus.map(_.io.iss.ready), pipe_fus.map(_.depth.U)) val pipe_valids = Seq.fill(pipe_depth)(RegInit(false.B)) val pipe_sels = Seq.fill(pipe_depth)(Reg(UInt(pipe_fus.size.W))) val pipe_bits = Seq.fill(pipe_depth)(Reg(new ExecuteMicroOp)) val pipe_latencies = Seq.fill(pipe_depth)(Reg(UInt(log2Ceil(pipe_depth).W))) pipe_stall := Mux1H(pipe_sels.head, pipe_fus.map(_.io.pipe0_stall)) pipe_write_hazard := (0 until pipe_depth).map { i => pipe_valids(i) && pipe_latencies(i) === pipe_iss_depth }.orR val pipe_iss = io.iss.fire && pipe_fus.map(_.io.iss.ready).orR when (!pipe_stall) { pipe_valids.head := pipe_iss when (pipe_iss) { pipe_bits.head := io.iss.bits pipe_latencies.head := pipe_iss_depth - 1.U pipe_sels.head := VecInit(pipe_fus.map(_.io.iss.ready)).asUInt } } for (i <- 1 until pipe_depth) { val fire = pipe_valids(i-1) && pipe_latencies(i-1) =/= 0.U && !((i == 1).B && pipe_stall) pipe_valids(i) := fire when (fire) { pipe_bits(i) := pipe_bits(i-1) pipe_latencies(i) := pipe_latencies(i-1) - 1.U pipe_sels(i) := pipe_sels(i-1) } } for ((fu, j) <- pipe_fus.zipWithIndex) { for (i <- 0 until fu.depth) { fu.io.pipe(i).valid := pipe_valids(i) && pipe_sels(i)(j) fu.io.pipe(i).bits := Mux(pipe_valids(i) && pipe_sels(i)(j), pipe_bits(i), 0.U.asTypeOf(new ExecuteMicroOp)) } } val write_sel = pipe_valids.zip(pipe_latencies).map { case (v,l) => v && l === 0.U } val fu_sel = Mux1H(write_sel, pipe_sels) pipe_write := write_sel.orR when (write_sel.orR) { val acc = Mux1H(write_sel, pipe_bits.map(_.acc)) val tail = Mux1H(write_sel, pipe_bits.map(_.tail)) io.pipe_write.valid := Mux1H(fu_sel, pipe_fus.map(_.io.write.valid)) && (!acc \|\| tail) io.pipe_write.bits := Mux1H(fu_sel, pipe_fus.map(_.io.write.bits)) io.acc_write.valid := acc && !tail io.acc_write.bits := Mux1H(fu_sel, pipe_fus.map(_.io.write.bits)) } when (pipe_valids.orR) { io.busy := true.B } for (i <- 0 until pipe_depth) { io.pipe_hazards(i).valid := pipe_valids(i) io.pipe_hazards(i).bits.eg := pipe_bits(i).wvd_eg when (pipe_latencies(i) === 0.U) { // hack to deal with compress unit io.pipe_hazards(i).bits.eg := Mux1H(pipe_sels(i), pipe_fus.map(_.io.write.bits.eg)) } io.pipe_hazards(i).bits.latency := pipe_latencies(i) } } if (iter_fus.size > 0) { val iter_write_arb = Module(new Arbiter(new VectorWrite(dLen), iter_fus.size)) iter_write_arb.io.in.zip(iter_fus.map(_.io.write)).foreach { case (l,r) => l <> r } iter_write_arb.io.out.ready := !pipe_write && io.iter_write.ready val acc = Mux1H(iter_write_arb.io.in.map(_.fire), iter_fus.map(_.io.acc)) val tail = Mux1H(iter_write_arb.io.in.map(_.fire), iter_fus.map(_.io.tail)) io.iter_write.valid := iter_write_arb.io.out.valid && (!acc \|\| tail) && !pipe_write io.iter_write.bits.eg := iter_write_arb.io.out.bits.eg io.iter_write.bits.mask := iter_write_arb.io.out.bits.mask io.iter_write.bits.data := iter_write_arb.io.out.bits.data when (!pipe_write) { io.acc_write.valid := iter_write_arb.io.out.valid && acc io.acc_write.bits.eg := Mux1H(iter_write_arb.io.in.map(_.fire), iter_fus.map(_.io.write.bits.eg)) io.acc_write.bits.data := Mux1H(iter_write_arb.io.in.map(_.fire), iter_fus.map(_.io.write.bits.data)) io.acc_write.bits.mask := Mux1H(iter_write_arb.io.in.map(_.fire), iter_fus.map(_.io.write.bits.mask)) } when (iter_fus.map(_.io.busy).orR) { io.busy := true.B } for (i <- 0 until iter_fus.size) { io.iter_hazards(i) := iter_fus(i).io.hazard } } } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /* Like Vec.apply(idx), but tolerates indices of mismatched width / def extract(idx: UInt): T = x((idx \| 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx \| 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def \| (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a \|\| b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_\|\|_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /* Any Data subtype that has a Bool member named valid. / type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /* converts from camel case to to underscores, also removing all spaces / def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /* converts spaces or underscores to hyphens, also lowering case / def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y \| (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y \|\| y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 \| 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /* Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation */ def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag }	module ExecutionUnit( // @[ExecutionUnit.scala:11:7] input clock, // @[ExecutionUnit.scala:11:7] input reset, // @[ExecutionUnit.scala:11:7] output io_iss_ready, // @[ExecutionUnit.scala:19:14] input io_iss_valid, // @[ExecutionUnit.scala:19:14] input [5:0] io_iss_bits_eidx, // @[ExecutionUnit.scala:19:14] input [6:0] io_iss_bits_vl, // @[ExecutionUnit.scala:19:14] input [63:0] io_iss_bits_rvs1_data, // @[ExecutionUnit.scala:19:14] input [63:0] io_iss_bits_rvs2_data, // @[ExecutionUnit.scala:19:14] input [63:0] io_iss_bits_rvm_data, // @[ExecutionUnit.scala:19:14] input [63:0] io_iss_bits_rvs1_elem, // @[ExecutionUnit.scala:19:14] input [63:0] io_iss_bits_rvs2_elem, // @[ExecutionUnit.scala:19:14] input [63:0] io_iss_bits_rvd_elem, // @[ExecutionUnit.scala:19:14] input [1:0] io_iss_bits_rvs1_eew, // @[ExecutionUnit.scala:19:14] input [1:0] io_iss_bits_rvs2_eew, // @[ExecutionUnit.scala:19:14] input [1:0] io_iss_bits_rvd_eew, // @[ExecutionUnit.scala:19:14] input [1:0] io_iss_bits_vd_eew, // @[ExecutionUnit.scala:19:14] input [7:0] io_iss_bits_rmask, // @[ExecutionUnit.scala:19:14] input [7:0] io_iss_bits_wmask, // @[ExecutionUnit.scala:19:14] input [63:0] io_iss_bits_full_tail_mask, // @[ExecutionUnit.scala:19:14] input [4:0] io_iss_bits_wvd_eg, // @[ExecutionUnit.scala:19:14] input [2:0] io_iss_bits_funct3, // @[ExecutionUnit.scala:19:14] input [5:0] io_iss_bits_funct6, // @[ExecutionUnit.scala:19:14] input [4:0] io_iss_bits_rs1, // @[ExecutionUnit.scala:19:14] input [4:0] io_iss_bits_rs2, // @[ExecutionUnit.scala:19:14] input [4:0] io_iss_bits_rd, // @[ExecutionUnit.scala:19:14] input io_iss_bits_vm, // @[ExecutionUnit.scala:19:14] input io_iss_bits_head, // @[ExecutionUnit.scala:19:14] input io_iss_bits_tail, // @[ExecutionUnit.scala:19:14] input io_iss_bits_acc, // @[ExecutionUnit.scala:19:14] input [2:0] io_iss_bits_rm, // @[ExecutionUnit.scala:19:14] output io_iter_hazards_0_valid, // @[ExecutionUnit.scala:19:14] output [4:0] io_iter_hazards_0_bits_eg, // @[ExecutionUnit.scala:19:14] output io_iter_hazards_1_valid, // @[ExecutionUnit.scala:19:14] output [4:0] io_iter_hazards_1_bits_eg, // @[ExecutionUnit.scala:19:14] input io_iter_write_ready, // @[ExecutionUnit.scala:19:14] output io_iter_write_valid, // @[ExecutionUnit.scala:19:14] output [4:0] io_iter_write_bits_eg, // @[ExecutionUnit.scala:19:14] output [63:0] io_iter_write_bits_data, // @[ExecutionUnit.scala:19:14] output [63:0] io_iter_write_bits_mask, // @[ExecutionUnit.scala:19:14] output io_pipe_write_valid, // @[ExecutionUnit.scala:19:14] output [4:0] io_pipe_write_bits_eg, // @[ExecutionUnit.scala:19:14] output [63:0] io_pipe_write_bits_data, // @[ExecutionUnit.scala:19:14] output [63:0] io_pipe_write_bits_mask, // @[ExecutionUnit.scala:19:14] output io_acc_write_valid, // @[ExecutionUnit.scala:19:14] output [63:0] io_acc_write_bits_data, // @[ExecutionUnit.scala:19:14] output [63:0] io_acc_write_bits_mask, // @[ExecutionUnit.scala:19:14] input io_scalar_write_ready, // @[ExecutionUnit.scala:19:14] output io_scalar_write_valid, // @[ExecutionUnit.scala:19:14] output [63:0] io_scalar_write_bits_data, // @[ExecutionUnit.scala:19:14] output io_scalar_write_bits_fp, // @[ExecutionUnit.scala:19:14] output [1:0] io_scalar_write_bits_size, // @[ExecutionUnit.scala:19:14] output [4:0] io_scalar_write_bits_rd, // @[ExecutionUnit.scala:19:14] output io_pipe_hazards_0_valid, // @[ExecutionUnit.scala:19:14] output [4:0] io_pipe_hazards_0_bits_eg, // @[ExecutionUnit.scala:19:14] output io_pipe_hazards_1_valid, // @[ExecutionUnit.scala:19:14] output [4:0] io_pipe_hazards_1_bits_eg, // @[ExecutionUnit.scala:19:14] output io_pipe_hazards_2_valid, // @[ExecutionUnit.scala:19:14] output [4:0] io_pipe_hazards_2_bits_eg, // @[ExecutionUnit.scala:19:14] output io_pipe_hazards_3_valid, // @[ExecutionUnit.scala:19:14] output [4:0] io_pipe_hazards_3_bits_eg, // @[ExecutionUnit.scala:19:14] input io_shared_fp_req_ready, // @[ExecutionUnit.scala:19:14] output io_shared_fp_req_valid, // @[ExecutionUnit.scala:19:14] output io_shared_fp_req_bits_ren2, // @[ExecutionUnit.scala:19:14] output io_shared_fp_req_bits_ren3, // @[ExecutionUnit.scala:19:14] output io_shared_fp_req_bits_swap23, // @[ExecutionUnit.scala:19:14] output [1:0] io_shared_fp_req_bits_typeTagIn, // @[ExecutionUnit.scala:19:14] output [1:0] io_shared_fp_req_bits_typeTagOut, // @[ExecutionUnit.scala:19:14] output io_shared_fp_req_bits_fromint, // @[ExecutionUnit.scala:19:14] output io_shared_fp_req_bits_toint, // @[ExecutionUnit.scala:19:14] output io_shared_fp_req_bits_fastpipe, // @[ExecutionUnit.scala:19:14] output io_shared_fp_req_bits_fma, // @[ExecutionUnit.scala:19:14] output io_shared_fp_req_bits_div, // @[ExecutionUnit.scala:19:14] output io_shared_fp_req_bits_sqrt, // @[ExecutionUnit.scala:19:14] output io_shared_fp_req_bits_wflags, // @[ExecutionUnit.scala:19:14] output [2:0] io_shared_fp_req_bits_rm, // @[ExecutionUnit.scala:19:14] output [1:0] io_shared_fp_req_bits_fmaCmd, // @[ExecutionUnit.scala:19:14] output [1:0] io_shared_fp_req_bits_typ, // @[ExecutionUnit.scala:19:14] output [64:0] io_shared_fp_req_bits_in1, // @[ExecutionUnit.scala:19:14] output [64:0] io_shared_fp_req_bits_in2, // @[ExecutionUnit.scala:19:14] output [64:0] io_shared_fp_req_bits_in3, // @[ExecutionUnit.scala:19:14] input io_shared_fp_resp_valid, // @[ExecutionUnit.scala:19:14] input [64:0] io_shared_fp_resp_bits_data, // @[ExecutionUnit.scala:19:14] output io_set_vxsat, // @[ExecutionUnit.scala:19:14] output io_busy // @[ExecutionUnit.scala:19:14] ); wire pipe_write_hazard; // @[package.scala:81:59] wire _pipe_stall_T_13; // @[Mux.scala:30:73] wire _iter_write_arb_io_in_0_ready; // @[ExecutionUnit.scala:152:32] wire _iter_write_arb_io_in_1_ready; // @[ExecutionUnit.scala:152:32] wire _iter_write_arb_io_out_valid; // @[ExecutionUnit.scala:152:32] wire _scalar_write_arb_io_in_4_ready; // @[ExecutionUnit.scala:84:32] wire _shared_fp_arb_io_in_0_ready; // @[ExecutionUnit.scala:44:31] wire _shared_fp_arb_io_in_1_ready; // @[ExecutionUnit.scala:44:31] wire _fus_8_io_iss_ready; // @[ExecutionUnit.scala:12:37] wire _fus_8_io_write_valid; // @[ExecutionUnit.scala:12:37] wire [4:0] _fus_8_io_write_bits_eg; // @[ExecutionUnit.scala:12:37] wire [63:0] _fus_8_io_write_bits_data; // @[ExecutionUnit.scala:12:37] wire [63:0] _fus_8_io_write_bits_mask; // @[ExecutionUnit.scala:12:37] wire _fus_8_io_acc; // @[ExecutionUnit.scala:12:37] wire _fus_8_io_tail; // @[ExecutionUnit.scala:12:37] wire _fus_8_io_busy; // @[ExecutionUnit.scala:12:37] wire _fus_8_io_fp_req_valid; // @[ExecutionUnit.scala:12:37] wire _fus_8_io_fp_req_bits_ren2; // @[ExecutionUnit.scala:12:37] wire [1:0] _fus_8_io_fp_req_bits_typeTagIn; // @[ExecutionUnit.scala:12:37] wire [1:0] _fus_8_io_fp_req_bits_typeTagOut; // @[ExecutionUnit.scala:12:37] wire _fus_8_io_fp_req_bits_fromint; // @[ExecutionUnit.scala:12:37] wire _fus_8_io_fp_req_bits_toint; // @[ExecutionUnit.scala:12:37] wire _fus_8_io_fp_req_bits_fastpipe; // @[ExecutionUnit.scala:12:37] wire _fus_8_io_fp_req_bits_div; // @[ExecutionUnit.scala:12:37] wire _fus_8_io_fp_req_bits_sqrt; // @[ExecutionUnit.scala:12:37] wire _fus_8_io_fp_req_bits_wflags; // @[ExecutionUnit.scala:12:37] wire [2:0] _fus_8_io_fp_req_bits_rm; // @[ExecutionUnit.scala:12:37] wire [1:0] _fus_8_io_fp_req_bits_typ; // @[ExecutionUnit.scala:12:37] wire [64:0] _fus_8_io_fp_req_bits_in1; // @[ExecutionUnit.scala:12:37] wire [64:0] _fus_8_io_fp_req_bits_in2; // @[ExecutionUnit.scala:12:37] wire _fus_8_io_fp_active; // @[ExecutionUnit.scala:12:37] wire _fus_7_io_iss_ready; // @[ExecutionUnit.scala:12:37] wire _fus_7_io_write_valid; // @[ExecutionUnit.scala:12:37] wire [4:0] _fus_7_io_write_bits_eg; // @[ExecutionUnit.scala:12:37] wire [63:0] _fus_7_io_write_bits_data; // @[ExecutionUnit.scala:12:37] wire [63:0] _fus_7_io_write_bits_mask; // @[ExecutionUnit.scala:12:37] wire _fus_7_io_pipe0_stall; // @[ExecutionUnit.scala:12:37] wire _fus_7_io_fp_req_valid; // @[ExecutionUnit.scala:12:37] wire _fus_7_io_fp_req_bits_ren3; // @[ExecutionUnit.scala:12:37] wire _fus_7_io_fp_req_bits_swap23; // @[ExecutionUnit.scala:12:37] wire [1:0] _fus_7_io_fp_req_bits_typeTagIn; // @[ExecutionUnit.scala:12:37] wire [1:0] _fus_7_io_fp_req_bits_typeTagOut; // @[ExecutionUnit.scala:12:37] wire [2:0] _fus_7_io_fp_req_bits_rm; // @[ExecutionUnit.scala:12:37] wire [1:0] _fus_7_io_fp_req_bits_fmaCmd; // @[ExecutionUnit.scala:12:37] wire [64:0] _fus_7_io_fp_req_bits_in1; // @[ExecutionUnit.scala:12:37] wire [64:0] _fus_7_io_fp_req_bits_in2; // @[ExecutionUnit.scala:12:37] wire [64:0] _fus_7_io_fp_req_bits_in3; // @[ExecutionUnit.scala:12:37] wire _fus_7_io_fp_active; // @[ExecutionUnit.scala:12:37] wire _fus_6_io_iss_ready; // @[ExecutionUnit.scala:12:37] wire _fus_6_io_set_vxsat; // @[ExecutionUnit.scala:12:37] wire _fus_6_io_write_valid; // @[ExecutionUnit.scala:12:37] wire [4:0] _fus_6_io_write_bits_eg; // @[ExecutionUnit.scala:12:37] wire [63:0] _fus_6_io_write_bits_data; // @[ExecutionUnit.scala:12:37] wire [63:0] _fus_6_io_write_bits_mask; // @[ExecutionUnit.scala:12:37] wire _fus_5_io_iss_ready; // @[ExecutionUnit.scala:12:37] wire _fus_5_io_write_valid; // @[ExecutionUnit.scala:12:37] wire [4:0] _fus_5_io_write_bits_eg; // @[ExecutionUnit.scala:12:37] wire [63:0] _fus_5_io_write_bits_data; // @[ExecutionUnit.scala:12:37] wire [63:0] _fus_5_io_write_bits_mask; // @[ExecutionUnit.scala:12:37] wire _fus_4_io_iss_ready; // @[ExecutionUnit.scala:12:37] wire _fus_4_io_scalar_write_valid; // @[ExecutionUnit.scala:12:37] wire [63:0] _fus_4_io_scalar_write_bits_data; // @[ExecutionUnit.scala:12:37] wire _fus_4_io_scalar_write_bits_fp; // @[ExecutionUnit.scala:12:37] wire [1:0] _fus_4_io_scalar_write_bits_size; // @[ExecutionUnit.scala:12:37] wire [4:0] _fus_4_io_scalar_write_bits_rd; // @[ExecutionUnit.scala:12:37] wire _fus_4_io_write_valid; // @[ExecutionUnit.scala:12:37] wire [4:0] _fus_4_io_write_bits_eg; // @[ExecutionUnit.scala:12:37] wire [63:0] _fus_4_io_write_bits_data; // @[ExecutionUnit.scala:12:37] wire [63:0] _fus_4_io_write_bits_mask; // @[ExecutionUnit.scala:12:37] wire _fus_3_io_iss_ready; // @[ExecutionUnit.scala:12:37] wire _fus_3_io_write_valid; // @[ExecutionUnit.scala:12:37] wire [4:0] _fus_3_io_write_bits_eg; // @[ExecutionUnit.scala:12:37] wire [63:0] _fus_3_io_write_bits_data; // @[ExecutionUnit.scala:12:37] wire [63:0] _fus_3_io_write_bits_mask; // @[ExecutionUnit.scala:12:37] wire _fus_3_io_busy; // @[ExecutionUnit.scala:12:37] wire _fus_2_io_iss_ready; // @[ExecutionUnit.scala:12:37] wire _fus_2_io_write_valid; // @[ExecutionUnit.scala:12:37] wire [4:0] _fus_2_io_write_bits_eg; // @[ExecutionUnit.scala:12:37] wire [63:0] _fus_2_io_write_bits_data; // @[ExecutionUnit.scala:12:37] wire [63:0] _fus_2_io_write_bits_mask; // @[ExecutionUnit.scala:12:37] wire _fus_1_io_iss_ready; // @[ExecutionUnit.scala:12:37] wire _fus_1_io_set_vxsat; // @[ExecutionUnit.scala:12:37] wire _fus_1_io_write_valid; // @[ExecutionUnit.scala:12:37] wire [4:0] _fus_1_io_write_bits_eg; // @[ExecutionUnit.scala:12:37] wire [63:0] _fus_1_io_write_bits_data; // @[ExecutionUnit.scala:12:37] wire [63:0] _fus_1_io_write_bits_mask; // @[ExecutionUnit.scala:12:37] wire _fus_0_io_iss_ready; // @[ExecutionUnit.scala:12:37] wire _fus_0_io_set_vxsat; // @[ExecutionUnit.scala:12:37] wire _fus_0_io_write_valid; // @[ExecutionUnit.scala:12:37] wire [4:0] _fus_0_io_write_bits_eg; // @[ExecutionUnit.scala:12:37] wire [63:0] _fus_0_io_write_bits_data; // @[ExecutionUnit.scala:12:37] wire [63:0] _fus_0_io_write_bits_mask; // @[ExecutionUnit.scala:12:37] wire _pipe_iss_T_1 = _fus_0_io_iss_ready \| _fus_1_io_iss_ready; // @[ExecutionUnit.scala:12:37] wire io_iss_ready_0 = (_pipe_iss_T_1 \| _fus_2_io_iss_ready \| _fus_3_io_iss_ready \| _fus_4_io_iss_ready \| _fus_5_io_iss_ready \| _fus_6_io_iss_ready \| _fus_7_io_iss_ready \| _fus_8_io_iss_ready) & ~pipe_write_hazard & ~_pipe_stall_T_13; // @[Mux.scala:30:73]
Generate the Verilog code corresponding to the following Chisel files. File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /* Like Vec.apply(idx), but tolerates indices of mismatched width / def extract(idx: UInt): T = x((idx \| 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx \| 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def \| (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a \|\| b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_\|\|_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /* Any Data subtype that has a Bool member named valid. / type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /* converts from camel case to to underscores, also removing all spaces / def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /* converts spaces or underscores to hyphens, also lowering case / def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y \| (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y \|\| y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 \| 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /* Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation */ def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag }	module OptimizationBarrier_TLBEntryData( // @[package.scala:267:30] input clock, // @[package.scala:267:30] input reset, // @[package.scala:267:30] input [19:0] io_x_ppn, // @[package.scala:268:18] input io_x_u, // @[package.scala:268:18] input io_x_g, // @[package.scala:268:18] input io_x_ae_ptw, // @[package.scala:268:18] input io_x_ae_final, // @[package.scala:268:18] input io_x_ae_stage2, // @[package.scala:268:18] input io_x_pf, // @[package.scala:268:18] input io_x_gf, // @[package.scala:268:18] input io_x_sw, // @[package.scala:268:18] input io_x_sx, // @[package.scala:268:18] input io_x_sr, // @[package.scala:268:18] input io_x_hw, // @[package.scala:268:18] input io_x_hx, // @[package.scala:268:18] input io_x_hr, // @[package.scala:268:18] input io_x_pw, // @[package.scala:268:18] input io_x_px, // @[package.scala:268:18] input io_x_pr, // @[package.scala:268:18] input io_x_ppp, // @[package.scala:268:18] input io_x_pal, // @[package.scala:268:18] input io_x_paa, // @[package.scala:268:18] input io_x_eff, // @[package.scala:268:18] input io_x_c, // @[package.scala:268:18] input io_x_fragmented_superpage, // @[package.scala:268:18] output [19:0] io_y_ppn // @[package.scala:268:18] ); wire [19:0] io_x_ppn_0 = io_x_ppn; // @[package.scala:267:30] wire io_x_u_0 = io_x_u; // @[package.scala:267:30] wire io_x_g_0 = io_x_g; // @[package.scala:267:30] wire io_x_ae_ptw_0 = io_x_ae_ptw; // @[package.scala:267:30] wire io_x_ae_final_0 = io_x_ae_final; // @[package.scala:267:30] wire io_x_ae_stage2_0 = io_x_ae_stage2; // @[package.scala:267:30] wire io_x_pf_0 = io_x_pf; // @[package.scala:267:30] wire io_x_gf_0 = io_x_gf; // @[package.scala:267:30] wire io_x_sw_0 = io_x_sw; // @[package.scala:267:30] wire io_x_sx_0 = io_x_sx; // @[package.scala:267:30] wire io_x_sr_0 = io_x_sr; // @[package.scala:267:30] wire io_x_hw_0 = io_x_hw; // @[package.scala:267:30] wire io_x_hx_0 = io_x_hx; // @[package.scala:267:30] wire io_x_hr_0 = io_x_hr; // @[package.scala:267:30] wire io_x_pw_0 = io_x_pw; // @[package.scala:267:30] wire io_x_px_0 = io_x_px; // @[package.scala:267:30] wire io_x_pr_0 = io_x_pr; // @[package.scala:267:30] wire io_x_ppp_0 = io_x_ppp; // @[package.scala:267:30] wire io_x_pal_0 = io_x_pal; // @[package.scala:267:30] wire io_x_paa_0 = io_x_paa; // @[package.scala:267:30] wire io_x_eff_0 = io_x_eff; // @[package.scala:267:30] wire io_x_c_0 = io_x_c; // @[package.scala:267:30] wire io_x_fragmented_superpage_0 = io_x_fragmented_superpage; // @[package.scala:267:30] wire [19:0] io_y_ppn_0 = io_x_ppn_0; // @[package.scala:267:30] wire io_y_u = io_x_u_0; // @[package.scala:267:30] wire io_y_g = io_x_g_0; // @[package.scala:267:30] wire io_y_ae_ptw = io_x_ae_ptw_0; // @[package.scala:267:30] wire io_y_ae_final = io_x_ae_final_0; // @[package.scala:267:30] wire io_y_ae_stage2 = io_x_ae_stage2_0; // @[package.scala:267:30] wire io_y_pf = io_x_pf_0; // @[package.scala:267:30] wire io_y_gf = io_x_gf_0; // @[package.scala:267:30] wire io_y_sw = io_x_sw_0; // @[package.scala:267:30] wire io_y_sx = io_x_sx_0; // @[package.scala:267:30] wire io_y_sr = io_x_sr_0; // @[package.scala:267:30] wire io_y_hw = io_x_hw_0; // @[package.scala:267:30] wire io_y_hx = io_x_hx_0; // @[package.scala:267:30] wire io_y_hr = io_x_hr_0; // @[package.scala:267:30] wire io_y_pw = io_x_pw_0; // @[package.scala:267:30] wire io_y_px = io_x_px_0; // @[package.scala:267:30] wire io_y_pr = io_x_pr_0; // @[package.scala:267:30] wire io_y_ppp = io_x_ppp_0; // @[package.scala:267:30] wire io_y_pal = io_x_pal_0; // @[package.scala:267:30] wire io_y_paa = io_x_paa_0; // @[package.scala:267:30] wire io_y_eff = io_x_eff_0; // @[package.scala:267:30] wire io_y_c = io_x_c_0; // @[package.scala:267:30] wire io_y_fragmented_superpage = io_x_fragmented_superpage_0; // @[package.scala:267:30] assign io_y_ppn = io_y_ppn_0; // @[package.scala:267:30] endmodule
Generate the Verilog code corresponding to the following Chisel files. File Tile.scala: // See README.md for license details. package gemmini import chisel3._ import chisel3.util._ import Util._ /** * A Tile is a purely combinational 2D array of passThrough PEs. * a, b, s, and in_propag are broadcast across the entire array and are passed through to the Tile's outputs * @param width The data width of each PE in bits * @param rows Number of PEs on each row * @param columns Number of PEs on each column */ class Tile[T <: Data](inputType: T, outputType: T, accType: T, df: Dataflow.Value, tree_reduction: Boolean, max_simultaneous_matmuls: Int, val rows: Int, val columns: Int)(implicit ev: Arithmetic[T]) extends Module { val io = IO(new Bundle { val in_a = Input(Vec(rows, inputType)) val in_b = Input(Vec(columns, outputType)) // This is the output of the tile next to it val in_d = Input(Vec(columns, outputType)) val in_control = Input(Vec(columns, new PEControl(accType))) val in_id = Input(Vec(columns, UInt(log2Up(max_simultaneous_matmuls).W))) val in_last = Input(Vec(columns, Bool())) val out_a = Output(Vec(rows, inputType)) val out_c = Output(Vec(columns, outputType)) val out_b = Output(Vec(columns, outputType)) val out_control = Output(Vec(columns, new PEControl(accType))) val out_id = Output(Vec(columns, UInt(log2Up(max_simultaneous_matmuls).W))) val out_last = Output(Vec(columns, Bool())) val in_valid = Input(Vec(columns, Bool())) val out_valid = Output(Vec(columns, Bool())) val bad_dataflow = Output(Bool()) }) import ev._ val tile = Seq.fill(rows, columns)(Module(new PE(inputType, outputType, accType, df, max_simultaneous_matmuls))) val tileT = tile.transpose // TODO: abstract hori/vert broadcast, all these connections look the same // Broadcast 'a' horizontally across the Tile for (r <- 0 until rows) { tile(r).foldLeft(io.in_a(r)) { case (in_a, pe) => pe.io.in_a := in_a pe.io.out_a } } // Broadcast 'b' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_b(c)) { case (in_b, pe) => pe.io.in_b := (if (tree_reduction) in_b.zero else in_b) pe.io.out_b } } // Broadcast 'd' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_d(c)) { case (in_d, pe) => pe.io.in_d := in_d pe.io.out_c } } // Broadcast 'control' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_control(c)) { case (in_ctrl, pe) => pe.io.in_control := in_ctrl pe.io.out_control } } // Broadcast 'garbage' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_valid(c)) { case (v, pe) => pe.io.in_valid := v pe.io.out_valid } } // Broadcast 'id' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_id(c)) { case (id, pe) => pe.io.in_id := id pe.io.out_id } } // Broadcast 'last' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_last(c)) { case (last, pe) => pe.io.in_last := last pe.io.out_last } } // Drive the Tile's bottom IO for (c <- 0 until columns) { io.out_c(c) := tile(rows-1)(c).io.out_c io.out_control(c) := tile(rows-1)(c).io.out_control io.out_id(c) := tile(rows-1)(c).io.out_id io.out_last(c) := tile(rows-1)(c).io.out_last io.out_valid(c) := tile(rows-1)(c).io.out_valid io.out_b(c) := { if (tree_reduction) { val prods = tileT(c).map(_.io.out_b) accumulateTree(prods :+ io.in_b(c)) } else { tile(rows - 1)(c).io.out_b } } } io.bad_dataflow := tile.map(_.map(_.io.bad_dataflow).reduce(_\|\|_)).reduce(_\|\|_) // Drive the Tile's right IO for (r <- 0 until rows) { io.out_a(r) := tile(r)(columns-1).io.out_a } }	module Tile_208( // @[Tile.scala:16:7] input clock, // @[Tile.scala:16:7] input reset, // @[Tile.scala:16:7] input [7:0] io_in_a_0, // @[Tile.scala:17:14] input [19:0] io_in_b_0, // @[Tile.scala:17:14] input [19:0] io_in_d_0, // @[Tile.scala:17:14] input io_in_control_0_dataflow, // @[Tile.scala:17:14] input io_in_control_0_propagate, // @[Tile.scala:17:14] input [4:0] io_in_control_0_shift, // @[Tile.scala:17:14] input [2:0] io_in_id_0, // @[Tile.scala:17:14] input io_in_last_0, // @[Tile.scala:17:14] output [7:0] io_out_a_0, // @[Tile.scala:17:14] output [19:0] io_out_c_0, // @[Tile.scala:17:14] output [19:0] io_out_b_0, // @[Tile.scala:17:14] output io_out_control_0_dataflow, // @[Tile.scala:17:14] output io_out_control_0_propagate, // @[Tile.scala:17:14] output [4:0] io_out_control_0_shift, // @[Tile.scala:17:14] output [2:0] io_out_id_0, // @[Tile.scala:17:14] output io_out_last_0, // @[Tile.scala:17:14] input io_in_valid_0, // @[Tile.scala:17:14] output io_out_valid_0, // @[Tile.scala:17:14] output io_bad_dataflow // @[Tile.scala:17:14] ); wire [7:0] io_in_a_0_0 = io_in_a_0; // @[Tile.scala:16:7] wire [19:0] io_in_b_0_0 = io_in_b_0; // @[Tile.scala:16:7] wire [19:0] io_in_d_0_0 = io_in_d_0; // @[Tile.scala:16:7] wire io_in_control_0_dataflow_0 = io_in_control_0_dataflow; // @[Tile.scala:16:7] wire io_in_control_0_propagate_0 = io_in_control_0_propagate; // @[Tile.scala:16:7] wire [4:0] io_in_control_0_shift_0 = io_in_control_0_shift; // @[Tile.scala:16:7] wire [2:0] io_in_id_0_0 = io_in_id_0; // @[Tile.scala:16:7] wire io_in_last_0_0 = io_in_last_0; // @[Tile.scala:16:7] wire io_in_valid_0_0 = io_in_valid_0; // @[Tile.scala:16:7] wire [7:0] io_out_a_0_0; // @[Tile.scala:16:7] wire [19:0] io_out_c_0_0; // @[Tile.scala:16:7] wire [19:0] io_out_b_0_0; // @[Tile.scala:16:7] wire io_out_control_0_dataflow_0; // @[Tile.scala:16:7] wire io_out_control_0_propagate_0; // @[Tile.scala:16:7] wire [4:0] io_out_control_0_shift_0; // @[Tile.scala:16:7] wire [2:0] io_out_id_0_0; // @[Tile.scala:16:7] wire io_out_last_0_0; // @[Tile.scala:16:7] wire io_out_valid_0_0; // @[Tile.scala:16:7] wire io_bad_dataflow_0; // @[Tile.scala:16:7] PE_464 tile_0_0 ( // @[Tile.scala:42:44] .clock (clock), .reset (reset), .io_in_a (io_in_a_0_0), // @[Tile.scala:16:7] .io_in_b (io_in_b_0_0), // @[Tile.scala:16:7] .io_in_d (io_in_d_0_0), // @[Tile.scala:16:7] .io_out_a (io_out_a_0_0), .io_out_b (io_out_b_0_0), .io_out_c (io_out_c_0_0), .io_in_control_dataflow (io_in_control_0_dataflow_0), // @[Tile.scala:16:7] .io_in_control_propagate (io_in_control_0_propagate_0), // @[Tile.scala:16:7] .io_in_control_shift (io_in_control_0_shift_0), // @[Tile.scala:16:7] .io_out_control_dataflow (io_out_control_0_dataflow_0), .io_out_control_propagate (io_out_control_0_propagate_0), .io_out_control_shift (io_out_control_0_shift_0), .io_in_id (io_in_id_0_0), // @[Tile.scala:16:7] .io_out_id (io_out_id_0_0), .io_in_last (io_in_last_0_0), // @[Tile.scala:16:7] .io_out_last (io_out_last_0_0), .io_in_valid (io_in_valid_0_0), // @[Tile.scala:16:7] .io_out_valid (io_out_valid_0_0), .io_bad_dataflow (io_bad_dataflow_0) ); // @[Tile.scala:42:44] assign io_out_a_0 = io_out_a_0_0; // @[Tile.scala:16:7] assign io_out_c_0 = io_out_c_0_0; // @[Tile.scala:16:7] assign io_out_b_0 = io_out_b_0_0; // @[Tile.scala:16:7] assign io_out_control_0_dataflow = io_out_control_0_dataflow_0; // @[Tile.scala:16:7] assign io_out_control_0_propagate = io_out_control_0_propagate_0; // @[Tile.scala:16:7] assign io_out_control_0_shift = io_out_control_0_shift_0; // @[Tile.scala:16:7] assign io_out_id_0 = io_out_id_0_0; // @[Tile.scala:16:7] assign io_out_last_0 = io_out_last_0_0; // @[Tile.scala:16:7] assign io_out_valid_0 = io_out_valid_0_0; // @[Tile.scala:16:7] assign io_bad_dataflow = io_bad_dataflow_0; // @[Tile.scala:16:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File ShiftReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ // Similar to the Chisel ShiftRegister but allows the user to suggest a // name to the registers that get instantiated, and // to provide a reset value. object ShiftRegInit { def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T = (0 until n).foldRight(in) { case (i, next) => { val r = RegNext(next, init) name.foreach { na => r.suggestName(s"${na}_${i}") } r } } } /** These wrap behavioral * shift registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * The different types vary in their reset behavior: * AsyncResetShiftReg -- Asynchronously reset register array * A W(width) x D(depth) sized array is constructed from D instantiations of a * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg, * but only used for timing applications */ abstract class AbstractPipelineReg(w: Int = 1) extends Module { val io = IO(new Bundle { val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) } ) } object AbstractPipelineReg { def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = { val chain = Module(gen) name.foreach{ chain.suggestName(_) } chain.io.d := in.asUInt chain.io.q.asTypeOf(in) } } class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) { require(depth > 0, "Depth must be greater than 0.") override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}" val chain = List.tabulate(depth) { i => Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}") } chain.last.io.d := io.d chain.last.io.en := true.B (chain.init zip chain.tail).foreach { case (sink, source) => sink.io.d := source.io.q sink.io.en := true.B } io.q := chain.head.io.q } object AsyncResetShiftReg { def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name) def apply [T <: Data](in: T, depth: Int, name: Option[String]): T = apply(in, depth, 0, name) def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T = apply(in, depth, init.litValue.toInt, name) def apply [T <: Data](in: T, depth: Int, init: T): T = apply (in, depth, init.litValue.toInt, None) } File AsyncQueue.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ case class AsyncQueueParams( depth: Int = 8, sync: Int = 3, safe: Boolean = true, // If safe is true, then effort is made to resynchronize the crossing indices when either side is reset. // This makes it safe/possible to reset one side of the crossing (but not the other) when the queue is empty. narrow: Boolean = false) // If narrow is true then the read mux is moved to the source side of the crossing. // This reduces the number of level shifters in the case where the clock crossing is also a voltage crossing, // at the expense of a combinational path from the sink to the source and back to the sink. { require (depth > 0 && isPow2(depth)) require (sync >= 2) val bits = log2Ceil(depth) val wires = if (narrow) 1 else depth } object AsyncQueueParams { // When there is only one entry, we don't need narrow. def singleton(sync: Int = 3, safe: Boolean = true) = AsyncQueueParams(1, sync, safe, false) } class AsyncBundleSafety extends Bundle { val ridx_valid = Input (Bool()) val widx_valid = Output(Bool()) val source_reset_n = Output(Bool()) val sink_reset_n = Input (Bool()) } class AsyncBundle[T <: Data](private val gen: T, val params: AsyncQueueParams = AsyncQueueParams()) extends Bundle { // Data-path synchronization val mem = Output(Vec(params.wires, gen)) val ridx = Input (UInt((params.bits+1).W)) val widx = Output(UInt((params.bits+1).W)) val index = params.narrow.option(Input(UInt(params.bits.W))) // Signals used to self-stabilize a safe AsyncQueue val safe = params.safe.option(new AsyncBundleSafety) } object GrayCounter { def apply(bits: Int, increment: Bool = true.B, clear: Bool = false.B, name: String = "binary"): UInt = { val incremented = Wire(UInt(bits.W)) val binary = RegNext(next=incremented, init=0.U).suggestName(name) incremented := Mux(clear, 0.U, binary + increment.asUInt) incremented ^ (incremented >> 1) } } class AsyncValidSync(sync: Int, desc: String) extends RawModule { val io = IO(new Bundle { val in = Input(Bool()) val out = Output(Bool()) }) val clock = IO(Input(Clock())) val reset = IO(Input(AsyncReset())) withClockAndReset(clock, reset){ io.out := AsyncResetSynchronizerShiftReg(io.in, sync, Some(desc)) } } class AsyncQueueSource[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module { override def desiredName = s"AsyncQueueSource_${gen.typeName}" val io = IO(new Bundle { // These come from the source domain val enq = Flipped(Decoupled(gen)) // These cross to the sink clock domain val async = new AsyncBundle(gen, params) }) val bits = params.bits val sink_ready = WireInit(true.B) val mem = Reg(Vec(params.depth, gen)) // This does NOT need to be reset at all. val widx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.enq.fire, !sink_ready, "widx_bin")) val ridx = AsyncResetSynchronizerShiftReg(io.async.ridx, params.sync, Some("ridx_gray")) val ready = sink_ready && widx =/= (ridx ^ (params.depth \| params.depth >> 1).U) val index = if (bits == 0) 0.U else io.async.widx(bits-1, 0) ^ (io.async.widx(bits, bits) << (bits-1)) when (io.enq.fire) { mem(index) := io.enq.bits } val ready_reg = withReset(reset.asAsyncReset)(RegNext(next=ready, init=false.B).suggestName("ready_reg")) io.enq.ready := ready_reg && sink_ready val widx_reg = withReset(reset.asAsyncReset)(RegNext(next=widx, init=0.U).suggestName("widx_gray")) io.async.widx := widx_reg io.async.index match { case Some(index) => io.async.mem(0) := mem(index) case None => io.async.mem := mem } io.async.safe.foreach { sio => val source_valid_0 = Module(new AsyncValidSync(params.sync, "source_valid_0")) val source_valid_1 = Module(new AsyncValidSync(params.sync, "source_valid_1")) val sink_extend = Module(new AsyncValidSync(params.sync, "sink_extend")) val sink_valid = Module(new AsyncValidSync(params.sync, "sink_valid")) source_valid_0.reset := (reset.asBool \|\| !sio.sink_reset_n).asAsyncReset source_valid_1.reset := (reset.asBool \|\| !sio.sink_reset_n).asAsyncReset sink_extend .reset := (reset.asBool \|\| !sio.sink_reset_n).asAsyncReset sink_valid .reset := reset.asAsyncReset source_valid_0.clock := clock source_valid_1.clock := clock sink_extend .clock := clock sink_valid .clock := clock source_valid_0.io.in := true.B source_valid_1.io.in := source_valid_0.io.out sio.widx_valid := source_valid_1.io.out sink_extend.io.in := sio.ridx_valid sink_valid.io.in := sink_extend.io.out sink_ready := sink_valid.io.out sio.source_reset_n := !reset.asBool // Assert that if there is stuff in the queue, then reset cannot happen // Impossible to write because dequeue can occur on the receiving side, // then reset allowed to happen, but write side cannot know that dequeue // occurred. // TODO: write some sort of sanity check assertion for users // that denote don't reset when there is activity // assert (!(reset \|\| !sio.sink_reset_n) \|\| !io.enq.valid, "Enqueue while sink is reset and AsyncQueueSource is unprotected") // assert (!reset_rise \|\| prev_idx_match.asBool, "Sink reset while AsyncQueueSource not empty") } } class AsyncQueueSink[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module { override def desiredName = s"AsyncQueueSink_${gen.typeName}" val io = IO(new Bundle { // These come from the sink domain val deq = Decoupled(gen) // These cross to the source clock domain val async = Flipped(new AsyncBundle(gen, params)) }) val bits = params.bits val source_ready = WireInit(true.B) val ridx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.deq.fire, !source_ready, "ridx_bin")) val widx = AsyncResetSynchronizerShiftReg(io.async.widx, params.sync, Some("widx_gray")) val valid = source_ready && ridx =/= widx // The mux is safe because timing analysis ensures ridx has reached the register // On an ASIC, changes to the unread location cannot affect the selected value // On an FPGA, only one input changes at a time => mem updates don't cause glitches // The register only latches when the selected valued is not being written val index = if (bits == 0) 0.U else ridx(bits-1, 0) ^ (ridx(bits, bits) << (bits-1)) io.async.index.foreach { _ := index } // This register does not NEED to be reset, as its contents will not // be considered unless the asynchronously reset deq valid register is set. // It is possible that bits latches when the source domain is reset / has power cut // This is safe, because isolation gates brought mem low before the zeroed widx reached us val deq_bits_nxt = io.async.mem(if (params.narrow) 0.U else index) io.deq.bits := ClockCrossingReg(deq_bits_nxt, en = valid, doInit = false, name = Some("deq_bits_reg")) val valid_reg = withReset(reset.asAsyncReset)(RegNext(next=valid, init=false.B).suggestName("valid_reg")) io.deq.valid := valid_reg && source_ready val ridx_reg = withReset(reset.asAsyncReset)(RegNext(next=ridx, init=0.U).suggestName("ridx_gray")) io.async.ridx := ridx_reg io.async.safe.foreach { sio => val sink_valid_0 = Module(new AsyncValidSync(params.sync, "sink_valid_0")) val sink_valid_1 = Module(new AsyncValidSync(params.sync, "sink_valid_1")) val source_extend = Module(new AsyncValidSync(params.sync, "source_extend")) val source_valid = Module(new AsyncValidSync(params.sync, "source_valid")) sink_valid_0 .reset := (reset.asBool \|\| !sio.source_reset_n).asAsyncReset sink_valid_1 .reset := (reset.asBool \|\| !sio.source_reset_n).asAsyncReset source_extend.reset := (reset.asBool \|\| !sio.source_reset_n).asAsyncReset source_valid .reset := reset.asAsyncReset sink_valid_0 .clock := clock sink_valid_1 .clock := clock source_extend.clock := clock source_valid .clock := clock sink_valid_0.io.in := true.B sink_valid_1.io.in := sink_valid_0.io.out sio.ridx_valid := sink_valid_1.io.out source_extend.io.in := sio.widx_valid source_valid.io.in := source_extend.io.out source_ready := source_valid.io.out sio.sink_reset_n := !reset.asBool // TODO: write some sort of sanity check assertion for users // that denote don't reset when there is activity // // val reset_and_extend = !source_ready \|\| !sio.source_reset_n \|\| reset.asBool // val reset_and_extend_prev = RegNext(reset_and_extend, true.B) // val reset_rise = !reset_and_extend_prev && reset_and_extend // val prev_idx_match = AsyncResetReg(updateData=(io.async.widx===io.async.ridx), resetData=0) // assert (!reset_rise \|\| prev_idx_match.asBool, "Source reset while AsyncQueueSink not empty") } } object FromAsyncBundle { // Sometimes it makes sense for the sink to have different sync than the source def apply[T <: Data](x: AsyncBundle[T]): DecoupledIO[T] = apply(x, x.params.sync) def apply[T <: Data](x: AsyncBundle[T], sync: Int): DecoupledIO[T] = { val sink = Module(new AsyncQueueSink(chiselTypeOf(x.mem(0)), x.params.copy(sync = sync))) sink.io.async <> x sink.io.deq } } object ToAsyncBundle { def apply[T <: Data](x: ReadyValidIO[T], params: AsyncQueueParams = AsyncQueueParams()): AsyncBundle[T] = { val source = Module(new AsyncQueueSource(chiselTypeOf(x.bits), params)) source.io.enq <> x source.io.async } } class AsyncQueue[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Crossing[T] { val io = IO(new CrossingIO(gen)) val source = withClockAndReset(io.enq_clock, io.enq_reset) { Module(new AsyncQueueSource(gen, params)) } val sink = withClockAndReset(io.deq_clock, io.deq_reset) { Module(new AsyncQueueSink (gen, params)) } source.io.enq <> io.enq io.deq <> sink.io.deq sink.io.async <> source.io.async }	module AsyncValidSync_61( // @[AsyncQueue.scala:58:7] input io_in, // @[AsyncQueue.scala:59:14] output io_out, // @[AsyncQueue.scala:59:14] input clock, // @[AsyncQueue.scala:63:17] input reset // @[AsyncQueue.scala:64:17] ); wire io_in_0 = io_in; // @[AsyncQueue.scala:58:7] wire _io_out_WIRE; // @[ShiftReg.scala:48:24] wire io_out_0; // @[AsyncQueue.scala:58:7] assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24] AsyncResetSynchronizerShiftReg_w1_d3_i0_74 io_out_sink_valid_1 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (reset), .io_d (io_in_0), // @[AsyncQueue.scala:58:7] .io_q (_io_out_WIRE) ); // @[ShiftReg.scala:45:23] assign io_out = io_out_0; // @[AsyncQueue.scala:58:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File SinkA.scala: /* * Copyright 2019 SiFive, Inc. * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You should have received a copy of LICENSE.Apache2 along with * this software. If not, you may obtain a copy at * * https://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. / package sifive.blocks.inclusivecache import chisel3._ import chisel3.util._ import freechips.rocketchip.tilelink._ import freechips.rocketchip.util._ class PutBufferAEntry(params: InclusiveCacheParameters) extends InclusiveCacheBundle(params) { val data = UInt(params.inner.bundle.dataBits.W) val mask = UInt((params.inner.bundle.dataBits/8).W) val corrupt = Bool() } class PutBufferPop(params: InclusiveCacheParameters) extends InclusiveCacheBundle(params) { val index = UInt(params.putBits.W) val last = Bool() } class SinkA(params: InclusiveCacheParameters) extends Module { val io = IO(new Bundle { val req = Decoupled(new FullRequest(params)) val a = Flipped(Decoupled(new TLBundleA(params.inner.bundle))) // for use by SourceD: val pb_pop = Flipped(Decoupled(new PutBufferPop(params))) val pb_beat = new PutBufferAEntry(params) }) // No restrictions on the type of buffer val a = params.micro.innerBuf.a(io.a) val putbuffer = Module(new ListBuffer(ListBufferParameters(new PutBufferAEntry(params), params.putLists, params.putBeats, false))) val lists = RegInit((0.U(params.putLists.W))) val lists_set = WireInit(init = 0.U(params.putLists.W)) val lists_clr = WireInit(init = 0.U(params.putLists.W)) lists := (lists \| lists_set) & ~lists_clr val free = !lists.andR val freeOH = ~(leftOR(~lists) << 1) & ~lists val freeIdx = OHToUInt(freeOH) val first = params.inner.first(a) val hasData = params.inner.hasData(a.bits) // We need to split the A input to three places: // If it is the first beat, it must go to req // If it has Data, it must go to the putbuffer // If it has Data AND is the first beat, it must claim a list val req_block = first && !io.req.ready val buf_block = hasData && !putbuffer.io.push.ready val set_block = hasData && first && !free params.ccover(a.valid && req_block, "SINKA_REQ_STALL", "No MSHR available to sink request") params.ccover(a.valid && buf_block, "SINKA_BUF_STALL", "No space in putbuffer for beat") params.ccover(a.valid && set_block, "SINKA_SET_STALL", "No space in putbuffer for request") a.ready := !req_block && !buf_block && !set_block io.req.valid := a.valid && first && !buf_block && !set_block putbuffer.io.push.valid := a.valid && hasData && !req_block && !set_block when (a.valid && first && hasData && !req_block && !buf_block) { lists_set := freeOH } val (tag, set, offset) = params.parseAddress(a.bits.address) val put = Mux(first, freeIdx, RegEnable(freeIdx, first)) io.req.bits.prio := VecInit(1.U(3.W).asBools) io.req.bits.control:= false.B io.req.bits.opcode := a.bits.opcode io.req.bits.param := a.bits.param io.req.bits.size := a.bits.size io.req.bits.source := a.bits.source io.req.bits.offset := offset io.req.bits.set := set io.req.bits.tag := tag io.req.bits.put := put putbuffer.io.push.bits.index := put putbuffer.io.push.bits.data.data := a.bits.data putbuffer.io.push.bits.data.mask := a.bits.mask putbuffer.io.push.bits.data.corrupt := a.bits.corrupt // Grant access to pop the data putbuffer.io.pop.bits := io.pb_pop.bits.index putbuffer.io.pop.valid := io.pb_pop.fire io.pb_pop.ready := putbuffer.io.valid(io.pb_pop.bits.index) io.pb_beat := putbuffer.io.data when (io.pb_pop.fire && io.pb_pop.bits.last) { lists_clr := UIntToOH(io.pb_pop.bits.index, params.putLists) } } File Parameters.scala: / * Copyright 2019 SiFive, Inc. * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You should have received a copy of LICENSE.Apache2 along with * this software. If not, you may obtain a copy at * * https://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. / package sifive.blocks.inclusivecache import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config._ import freechips.rocketchip.diplomacy._ import freechips.rocketchip.tilelink._ import freechips.rocketchip.util._ import freechips.rocketchip.util.property.cover import scala.math.{min,max} case class CacheParameters( level: Int, ways: Int, sets: Int, blockBytes: Int, beatBytes: Int, // inner hintsSkipProbe: Boolean) { require (ways > 0) require (sets > 0) require (blockBytes > 0 && isPow2(blockBytes)) require (beatBytes > 0 && isPow2(beatBytes)) require (blockBytes >= beatBytes) val blocks = ways sets val sizeBytes = blocks * blockBytes val blockBeats = blockBytes/beatBytes } case class InclusiveCachePortParameters( a: BufferParams, b: BufferParams, c: BufferParams, d: BufferParams, e: BufferParams) { def apply()(implicit p: Parameters, valName: ValName) = LazyModule(new TLBuffer(a, b, c, d, e)) } object InclusiveCachePortParameters { val none = InclusiveCachePortParameters( a = BufferParams.none, b = BufferParams.none, c = BufferParams.none, d = BufferParams.none, e = BufferParams.none) val full = InclusiveCachePortParameters( a = BufferParams.default, b = BufferParams.default, c = BufferParams.default, d = BufferParams.default, e = BufferParams.default) // This removes feed-through paths from C=>A and A=>C val fullC = InclusiveCachePortParameters( a = BufferParams.none, b = BufferParams.none, c = BufferParams.default, d = BufferParams.none, e = BufferParams.none) val flowAD = InclusiveCachePortParameters( a = BufferParams.flow, b = BufferParams.none, c = BufferParams.none, d = BufferParams.flow, e = BufferParams.none) val flowAE = InclusiveCachePortParameters( a = BufferParams.flow, b = BufferParams.none, c = BufferParams.none, d = BufferParams.none, e = BufferParams.flow) // For innerBuf: // SinkA: no restrictions, flows into scheduler+putbuffer // SourceB: no restrictions, flows out of scheduler // sinkC: no restrictions, flows into scheduler+putbuffer & buffered to bankedStore // SourceD: no restrictions, flows out of bankedStore/regout // SinkE: no restrictions, flows into scheduler // // ... so while none is possible, you probably want at least flowAC to cut ready // from the scheduler delay and flowD to ease SourceD back-pressure // For outerBufer: // SourceA: must not be pipe, flows out of scheduler // SinkB: no restrictions, flows into scheduler // SourceC: pipe is useless, flows out of bankedStore/regout, parameter depth ignored // SinkD: no restrictions, flows into scheduler & bankedStore // SourceE: must not be pipe, flows out of scheduler // // ... AE take the channel ready into the scheduler, so you need at least flowAE } case class InclusiveCacheMicroParameters( writeBytes: Int, // backing store update granularity memCycles: Int = 40, // # of L2 clock cycles for a memory round-trip (50ns @ 800MHz) portFactor: Int = 4, // numSubBanks = (widest TL port * portFactor) / writeBytes dirReg: Boolean = false, innerBuf: InclusiveCachePortParameters = InclusiveCachePortParameters.fullC, // or none outerBuf: InclusiveCachePortParameters = InclusiveCachePortParameters.full) // or flowAE { require (writeBytes > 0 && isPow2(writeBytes)) require (memCycles > 0) require (portFactor >= 2) // for inner RMW and concurrent outer Relase + Grant } case class InclusiveCacheControlParameters( address: BigInt, beatBytes: Int, bankedControl: Boolean) case class InclusiveCacheParameters( cache: CacheParameters, micro: InclusiveCacheMicroParameters, control: Boolean, inner: TLEdgeIn, outer: TLEdgeOut)(implicit val p: Parameters) { require (cache.ways > 1) require (cache.sets > 1 && isPow2(cache.sets)) require (micro.writeBytes <= inner.manager.beatBytes) require (micro.writeBytes <= outer.manager.beatBytes) require (inner.manager.beatBytes <= cache.blockBytes) require (outer.manager.beatBytes <= cache.blockBytes) // Require that all cached address ranges have contiguous blocks outer.manager.managers.flatMap(_.address).foreach { a => require (a.alignment >= cache.blockBytes) } // If we are the first level cache, we do not need to support inner-BCE val firstLevel = !inner.client.clients.exists(_.supports.probe) // If we are the last level cache, we do not need to support outer-B val lastLevel = !outer.manager.managers.exists(_.regionType > RegionType.UNCACHED) require (lastLevel) // Provision enough resources to achieve full throughput with missing single-beat accesses val mshrs = InclusiveCacheParameters.all_mshrs(cache, micro) val secondary = max(mshrs, micro.memCycles - mshrs) val putLists = micro.memCycles // allow every request to be single beat val putBeats = max(2cache.blockBeats, micro.memCycles) val relLists = 2 val relBeats = relListscache.blockBeats val flatAddresses = AddressSet.unify(outer.manager.managers.flatMap(_.address)) val pickMask = AddressDecoder(flatAddresses.map(Seq(_)), flatAddresses.map(_.mask).reduce(_\|_)) def bitOffsets(x: BigInt, offset: Int = 0, tail: List[Int] = List.empty[Int]): List[Int] = if (x == 0) tail.reverse else bitOffsets(x >> 1, offset + 1, if ((x & 1) == 1) offset :: tail else tail) val addressMapping = bitOffsets(pickMask) val addressBits = addressMapping.size // println(s"addresses: ${flatAddresses} => ${pickMask} => ${addressBits}") val allClients = inner.client.clients.size val clientBitsRaw = inner.client.clients.filter(_.supports.probe).size val clientBits = max(1, clientBitsRaw) val stateBits = 2 val wayBits = log2Ceil(cache.ways) val setBits = log2Ceil(cache.sets) val offsetBits = log2Ceil(cache.blockBytes) val tagBits = addressBits - setBits - offsetBits val putBits = log2Ceil(max(putLists, relLists)) require (tagBits > 0) require (offsetBits > 0) val innerBeatBits = (offsetBits - log2Ceil(inner.manager.beatBytes)) max 1 val outerBeatBits = (offsetBits - log2Ceil(outer.manager.beatBytes)) max 1 val innerMaskBits = inner.manager.beatBytes / micro.writeBytes val outerMaskBits = outer.manager.beatBytes / micro.writeBytes def clientBit(source: UInt): UInt = { if (clientBitsRaw == 0) { 0.U } else { Cat(inner.client.clients.filter(_.supports.probe).map(_.sourceId.contains(source)).reverse) } } def clientSource(bit: UInt): UInt = { if (clientBitsRaw == 0) { 0.U } else { Mux1H(bit, inner.client.clients.filter(_.supports.probe).map(c => c.sourceId.start.U)) } } def parseAddress(x: UInt): (UInt, UInt, UInt) = { val offset = Cat(addressMapping.map(o => x(o,o)).reverse) val set = offset >> offsetBits val tag = set >> setBits (tag(tagBits-1, 0), set(setBits-1, 0), offset(offsetBits-1, 0)) } def widen(x: UInt, width: Int): UInt = { val y = x \| 0.U(width.W) assert (y >> width === 0.U) y(width-1, 0) } def expandAddress(tag: UInt, set: UInt, offset: UInt): UInt = { val base = Cat(widen(tag, tagBits), widen(set, setBits), widen(offset, offsetBits)) val bits = Array.fill(outer.bundle.addressBits) { 0.U(1.W) } addressMapping.zipWithIndex.foreach { case (a, i) => bits(a) = base(i,i) } Cat(bits.reverse) } def restoreAddress(expanded: UInt): UInt = { val missingBits = flatAddresses .map { a => (a.widen(pickMask).base, a.widen(~pickMask)) } // key is the bits to restore on match .groupBy(_._1) .view .mapValues(_.map(_._2)) val muxMask = AddressDecoder(missingBits.values.toList) val mux = missingBits.toList.map { case (bits, addrs) => val widen = addrs.map(_.widen(~muxMask)) val matches = AddressSet .unify(widen.distinct) .map(_.contains(expanded)) .reduce(_ \|\| _) (matches, bits.U) } expanded \| Mux1H(mux) } def dirReg[T <: Data](x: T, en: Bool = true.B): T = { if (micro.dirReg) RegEnable(x, en) else x } def ccover(cond: Bool, label: String, desc: String)(implicit sourceInfo: SourceInfo) = cover(cond, "CCACHE_L" + cache.level + "_" + label, "MemorySystem;;" + desc) } object MetaData { val stateBits = 2 def INVALID: UInt = 0.U(stateBits.W) // way is empty def BRANCH: UInt = 1.U(stateBits.W) // outer slave cache is trunk def TRUNK: UInt = 2.U(stateBits.W) // unique inner master cache is trunk def TIP: UInt = 3.U(stateBits.W) // we are trunk, inner masters are branch // Does a request need trunk? def needT(opcode: UInt, param: UInt): Bool = { !opcode(2) \|\| (opcode === TLMessages.Hint && param === TLHints.PREFETCH_WRITE) \|\| ((opcode === TLMessages.AcquireBlock \|\| opcode === TLMessages.AcquirePerm) && param =/= TLPermissions.NtoB) } // Does a request prove the client need not be probed? def skipProbeN(opcode: UInt, hintsSkipProbe: Boolean): Bool = { // Acquire(toB) and Get => is N, so no probe // Acquire(toT) => is N or B, but need T, so no probe // Hint => could be anything, so probe IS needed, if hintsSkipProbe is enabled, skip probe the same client // Put => is N or B, so probe IS needed opcode === TLMessages.AcquireBlock \|\| opcode === TLMessages.AcquirePerm \|\| opcode === TLMessages.Get \|\| (opcode === TLMessages.Hint && hintsSkipProbe.B) } def isToN(param: UInt): Bool = { param === TLPermissions.TtoN \|\| param === TLPermissions.BtoN \|\| param === TLPermissions.NtoN } def isToB(param: UInt): Bool = { param === TLPermissions.TtoB \|\| param === TLPermissions.BtoB } } object InclusiveCacheParameters { val lfsrBits = 10 val L2ControlAddress = 0x2010000 val L2ControlSize = 0x1000 def out_mshrs(cache: CacheParameters, micro: InclusiveCacheMicroParameters): Int = { // We need 2-3 normal MSHRs to cover the Directory latency // To fully exploit memory bandwidth-delay-product, we need memCyles/blockBeats MSHRs max(if (micro.dirReg) 3 else 2, (micro.memCycles + cache.blockBeats - 1) / cache.blockBeats) } def all_mshrs(cache: CacheParameters, micro: InclusiveCacheMicroParameters): Int = // We need a dedicated MSHR for B+C each 2 + out_mshrs(cache, micro) } class InclusiveCacheBundle(params: InclusiveCacheParameters) extends Bundle File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportPutFull \|\| manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB \|\| manager.anySupportGet \|\| manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportPutFull \|\| client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe \|\| client.anySupportGet \|\| client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet \|\| client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull \|\| client.anySupportPutPartial \|\| client.anySupportHint \|\| client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet \|\| manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull \|\| manager.anySupportPutPartial \|\| manager.anySupportHint \|\| manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) \|\| !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.ProbeAckData \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode \| small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U \|\| beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }	module SinkA( // @[SinkA.scala:38:7] input clock, // @[SinkA.scala:38:7] input reset, // @[SinkA.scala:38:7] input io_req_ready, // @[SinkA.scala:40:14] output io_req_valid, // @[SinkA.scala:40:14] output [2:0] io_req_bits_opcode, // @[SinkA.scala:40:14] output [2:0] io_req_bits_param, // @[SinkA.scala:40:14] output [2:0] io_req_bits_size, // @[SinkA.scala:40:14] output [7:0] io_req_bits_source, // @[SinkA.scala:40:14] output [12:0] io_req_bits_tag, // @[SinkA.scala:40:14] output [5:0] io_req_bits_offset, // @[SinkA.scala:40:14] output [5:0] io_req_bits_put, // @[SinkA.scala:40:14] output [9:0] io_req_bits_set, // @[SinkA.scala:40:14] output io_a_ready, // @[SinkA.scala:40:14] input io_a_valid, // @[SinkA.scala:40:14] input [2:0] io_a_bits_opcode, // @[SinkA.scala:40:14] input [2:0] io_a_bits_param, // @[SinkA.scala:40:14] input [2:0] io_a_bits_size, // @[SinkA.scala:40:14] input [7:0] io_a_bits_source, // @[SinkA.scala:40:14] input [31:0] io_a_bits_address, // @[SinkA.scala:40:14] input [31:0] io_a_bits_mask, // @[SinkA.scala:40:14] input [255:0] io_a_bits_data, // @[SinkA.scala:40:14] input io_a_bits_corrupt, // @[SinkA.scala:40:14] output io_pb_pop_ready, // @[SinkA.scala:40:14] input io_pb_pop_valid, // @[SinkA.scala:40:14] input [5:0] io_pb_pop_bits_index, // @[SinkA.scala:40:14] input io_pb_pop_bits_last, // @[SinkA.scala:40:14] output [255:0] io_pb_beat_data, // @[SinkA.scala:40:14] output [31:0] io_pb_beat_mask, // @[SinkA.scala:40:14] output io_pb_beat_corrupt // @[SinkA.scala:40:14] ); wire _putbuffer_io_push_ready; // @[SinkA.scala:51:25] wire [39:0] _putbuffer_io_valid; // @[SinkA.scala:51:25] wire io_req_ready_0 = io_req_ready; // @[SinkA.scala:38:7] wire io_a_valid_0 = io_a_valid; // @[SinkA.scala:38:7] wire [2:0] io_a_bits_opcode_0 = io_a_bits_opcode; // @[SinkA.scala:38:7] wire [2:0] io_a_bits_param_0 = io_a_bits_param; // @[SinkA.scala:38:7] wire [2:0] io_a_bits_size_0 = io_a_bits_size; // @[SinkA.scala:38:7] wire [7:0] io_a_bits_source_0 = io_a_bits_source; // @[SinkA.scala:38:7] wire [31:0] io_a_bits_address_0 = io_a_bits_address; // @[SinkA.scala:38:7] wire [31:0] io_a_bits_mask_0 = io_a_bits_mask; // @[SinkA.scala:38:7] wire [255:0] io_a_bits_data_0 = io_a_bits_data; // @[SinkA.scala:38:7] wire io_a_bits_corrupt_0 = io_a_bits_corrupt; // @[SinkA.scala:38:7] wire io_pb_pop_valid_0 = io_pb_pop_valid; // @[SinkA.scala:38:7] wire [5:0] io_pb_pop_bits_index_0 = io_pb_pop_bits_index; // @[SinkA.scala:38:7] wire io_pb_pop_bits_last_0 = io_pb_pop_bits_last; // @[SinkA.scala:38:7] wire io_req_bits_prio_1 = 1'h0; // @[SinkA.scala:38:7] wire io_req_bits_prio_2 = 1'h0; // @[SinkA.scala:38:7] wire io_req_bits_control = 1'h0; // @[SinkA.scala:38:7] wire io_req_bits_prio_0 = 1'h1; // @[SinkA.scala:38:7] wire _io_req_valid_T_4; // @[SinkA.scala:79:50] wire [12:0] tag_1; // @[Parameters.scala:217:9] wire [5:0] offset_1; // @[Parameters.scala:217:50] wire [5:0] put; // @[SinkA.scala:84:16] wire [9:0] set_1; // @[Parameters.scala:217:28] wire _io_a_ready_T_4; // @[SinkA.scala:78:39] wire [2:0] io_req_bits_opcode_0 = io_a_bits_opcode_0; // @[SinkA.scala:38:7] wire [2:0] io_req_bits_param_0 = io_a_bits_param_0; // @[SinkA.scala:38:7] wire [2:0] io_req_bits_size_0 = io_a_bits_size_0; // @[SinkA.scala:38:7] wire [7:0] io_req_bits_source_0 = io_a_bits_source_0; // @[SinkA.scala:38:7] wire _io_pb_pop_ready_T_1; // @[SinkA.scala:105:40] wire [5:0] lists_clr_shiftAmount = io_pb_pop_bits_index_0; // @[OneHot.scala:64:49] wire [12:0] io_req_bits_tag_0; // @[SinkA.scala:38:7] wire [5:0] io_req_bits_offset_0; // @[SinkA.scala:38:7] wire [5:0] io_req_bits_put_0; // @[SinkA.scala:38:7] wire [9:0] io_req_bits_set_0; // @[SinkA.scala:38:7] wire io_req_valid_0; // @[SinkA.scala:38:7] wire io_a_ready_0; // @[SinkA.scala:38:7] wire io_pb_pop_ready_0; // @[SinkA.scala:38:7] wire [255:0] io_pb_beat_data_0; // @[SinkA.scala:38:7] wire [31:0] io_pb_beat_mask_0; // @[SinkA.scala:38:7] wire io_pb_beat_corrupt_0; // @[SinkA.scala:38:7] reg [39:0] lists; // @[SinkA.scala:52:22] wire [39:0] lists_set; // @[SinkA.scala:54:27] wire [39:0] lists_clr; // @[SinkA.scala:55:27] wire [39:0] _lists_T = lists \| lists_set; // @[SinkA.scala:52:22, :54:27, :56:19] wire [39:0] _lists_T_1 = ~lists_clr; // @[SinkA.scala:55:27, :56:34] wire [39:0] _lists_T_2 = _lists_T & _lists_T_1; // @[SinkA.scala:56:{19,32,34}] wire _free_T = &lists; // @[SinkA.scala:52:22, :58:21] wire free = ~_free_T; // @[SinkA.scala:58:{14,21}] wire [39:0] _freeOH_T = ~lists; // @[SinkA.scala:52:22, :59:25] wire [40:0] _freeOH_T_1 = {_freeOH_T, 1'h0}; // @[package.scala:253:48] wire [39:0] _freeOH_T_2 = _freeOH_T_1[39:0]; // @[package.scala:253:{48,53}] wire [39:0] _freeOH_T_3 = _freeOH_T \| _freeOH_T_2; // @[package.scala:253:{43,53}] wire [41:0] _freeOH_T_4 = {_freeOH_T_3, 2'h0}; // @[package.scala:253:{43,48}] wire [39:0] _freeOH_T_5 = _freeOH_T_4[39:0]; // @[package.scala:253:{48,53}] wire [39:0] _freeOH_T_6 = _freeOH_T_3 \| _freeOH_T_5; // @[package.scala:253:{43,53}] wire [43:0] _freeOH_T_7 = {_freeOH_T_6, 4'h0}; // @[package.scala:253:{43,48}] wire [39:0] _freeOH_T_8 = _freeOH_T_7[39:0]; // @[package.scala:253:{48,53}] wire [39:0] _freeOH_T_9 = _freeOH_T_6 \| _freeOH_T_8; // @[package.scala:253:{43,53}] wire [47:0] _freeOH_T_10 = {_freeOH_T_9, 8'h0}; // @[package.scala:253:{43,48}] wire [39:0] _freeOH_T_11 = _freeOH_T_10[39:0]; // @[package.scala:253:{48,53}] wire [39:0] _freeOH_T_12 = _freeOH_T_9 \| _freeOH_T_11; // @[package.scala:253:{43,53}] wire [55:0] _freeOH_T_13 = {_freeOH_T_12, 16'h0}; // @[package.scala:253:{43,48}] wire [39:0] _freeOH_T_14 = _freeOH_T_13[39:0]; // @[package.scala:253:{48,53}] wire [39:0] _freeOH_T_15 = _freeOH_T_12 \| _freeOH_T_14; // @[package.scala:253:{43,53}] wire [71:0] _freeOH_T_16 = {_freeOH_T_15, 32'h0}; // @[package.scala:253:{43,48}] wire [39:0] _freeOH_T_17 = _freeOH_T_16[39:0]; // @[package.scala:253:{48,53}] wire [39:0] _freeOH_T_18 = _freeOH_T_15 \| _freeOH_T_17; // @[package.scala:253:{43,53}] wire [39:0] _freeOH_T_19 = _freeOH_T_18; // @[package.scala:253:43, :254:17] wire [40:0] _freeOH_T_20 = {_freeOH_T_19, 1'h0}; // @[package.scala:254:17] wire [40:0] _freeOH_T_21 = ~_freeOH_T_20; // @[SinkA.scala:59:{16,33}] wire [39:0] _freeOH_T_22 = ~lists; // @[SinkA.scala:52:22, :59:{25,41}] wire [40:0] freeOH = {1'h0, _freeOH_T_21[39:0] & _freeOH_T_22}; // @[SinkA.scala:59:{16,39,41}] wire [8:0] freeIdx_hi = freeOH[40:32]; // @[OneHot.scala:30:18] wire [31:0] freeIdx_lo = freeOH[31:0]; // @[OneHot.scala:31:18] wire _freeIdx_T = \|freeIdx_hi; // @[OneHot.scala:30:18, :32:14] wire [31:0] _freeIdx_T_1 = {23'h0, freeIdx_hi} \| freeIdx_lo; // @[OneHot.scala:30:18, :31:18, :32:28] wire [15:0] freeIdx_hi_1 = _freeIdx_T_1[31:16]; // @[OneHot.scala:30:18, :32:28] wire [15:0] freeIdx_lo_1 = _freeIdx_T_1[15:0]; // @[OneHot.scala:31:18, :32:28] wire _freeIdx_T_2 = \|freeIdx_hi_1; // @[OneHot.scala:30:18, :32:14] wire [15:0] _freeIdx_T_3 = freeIdx_hi_1 \| freeIdx_lo_1; // @[OneHot.scala:30:18, :31:18, :32:28] wire [7:0] freeIdx_hi_2 = _freeIdx_T_3[15:8]; // @[OneHot.scala:30:18, :32:28] wire [7:0] freeIdx_lo_2 = _freeIdx_T_3[7:0]; // @[OneHot.scala:31:18, :32:28] wire _freeIdx_T_4 = \|freeIdx_hi_2; // @[OneHot.scala:30:18, :32:14] wire [7:0] _freeIdx_T_5 = freeIdx_hi_2 \| freeIdx_lo_2; // @[OneHot.scala:30:18, :31:18, :32:28] wire [3:0] freeIdx_hi_3 = _freeIdx_T_5[7:4]; // @[OneHot.scala:30:18, :32:28] wire [3:0] freeIdx_lo_3 = _freeIdx_T_5[3:0]; // @[OneHot.scala:31:18, :32:28] wire _freeIdx_T_6 = \|freeIdx_hi_3; // @[OneHot.scala:30:18, :32:14] wire [3:0] _freeIdx_T_7 = freeIdx_hi_3 \| freeIdx_lo_3; // @[OneHot.scala:30:18, :31:18, :32:28] wire [1:0] freeIdx_hi_4 = _freeIdx_T_7[3:2]; // @[OneHot.scala:30:18, :32:28] wire [1:0] freeIdx_lo_4 = _freeIdx_T_7[1:0]; // @[OneHot.scala:31:18, :32:28] wire _freeIdx_T_8 = \|freeIdx_hi_4; // @[OneHot.scala:30:18, :32:14] wire [1:0] _freeIdx_T_9 = freeIdx_hi_4 \| freeIdx_lo_4; // @[OneHot.scala:30:18, :31:18, :32:28] wire _freeIdx_T_10 = _freeIdx_T_9[1]; // @[OneHot.scala:32:28] wire [1:0] _freeIdx_T_11 = {_freeIdx_T_8, _freeIdx_T_10}; // @[OneHot.scala:32:{10,14}] wire [2:0] _freeIdx_T_12 = {_freeIdx_T_6, _freeIdx_T_11}; // @[OneHot.scala:32:{10,14}] wire [3:0] _freeIdx_T_13 = {_freeIdx_T_4, _freeIdx_T_12}; // @[OneHot.scala:32:{10,14}] wire [4:0] _freeIdx_T_14 = {_freeIdx_T_2, _freeIdx_T_13}; // @[OneHot.scala:32:{10,14}] wire [5:0] freeIdx = {_freeIdx_T, _freeIdx_T_14}; // @[OneHot.scala:32:{10,14}] wire _first_T = io_a_ready_0 & io_a_valid_0; // @[Decoupled.scala:51:35] wire [12:0] _first_beats1_decode_T = 13'h3F << io_a_bits_size_0; // @[package.scala:243:71] wire [5:0] _first_beats1_decode_T_1 = _first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _first_beats1_decode_T_2 = ~_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire first_beats1_decode = _first_beats1_decode_T_2[5]; // @[package.scala:243:46] wire _first_beats1_opdata_T = io_a_bits_opcode_0[2]; // @[Edges.scala:92:37] wire _hasData_opdata_T = io_a_bits_opcode_0[2]; // @[Edges.scala:92:37] wire first_beats1_opdata = ~_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire first_beats1 = first_beats1_opdata & first_beats1_decode; // @[Edges.scala:92:28, :220:59, :221:14] reg first_counter; // @[Edges.scala:229:27] wire _first_last_T = first_counter; // @[Edges.scala:229:27, :232:25] wire [1:0] _first_counter1_T = {1'h0, first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28] wire first_counter1 = _first_counter1_T[0]; // @[Edges.scala:230:28] wire first = ~first_counter; // @[Edges.scala:229:27, :231:25] wire _first_last_T_1 = ~first_beats1; // @[Edges.scala:221:14, :232:43] wire first_last = _first_last_T \| _first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire first_done = first_last & _first_T; // @[Decoupled.scala:51:35] wire _first_count_T = ~first_counter1; // @[Edges.scala:230:28, :234:27] wire first_count = first_beats1 & _first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire _first_counter_T = first ? first_beats1 : first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire hasData = ~_hasData_opdata_T; // @[Edges.scala:92:{28,37}] wire _req_block_T = ~io_req_ready_0; // @[SinkA.scala:38:7, :70:28] wire req_block = first & _req_block_T; // @[Edges.scala:231:25] wire _buf_block_T = ~_putbuffer_io_push_ready; // @[SinkA.scala:51:25, :71:30] wire buf_block = hasData & _buf_block_T; // @[Edges.scala:92:28] wire _set_block_T = hasData & first; // @[Edges.scala:92:28, :231:25] wire _set_block_T_1 = ~free; // @[SinkA.scala:58:14, :72:39] wire set_block = _set_block_T & _set_block_T_1; // @[SinkA.scala:72:{27,36,39}] wire _io_a_ready_T = ~req_block; // @[SinkA.scala:70:25, :78:14] wire _io_a_ready_T_1 = ~buf_block; // @[SinkA.scala:71:27, :78:28] wire _io_a_ready_T_2 = _io_a_ready_T & _io_a_ready_T_1; // @[SinkA.scala:78:{14,25,28}] wire _io_a_ready_T_3 = ~set_block; // @[SinkA.scala:72:36, :78:42] assign _io_a_ready_T_4 = _io_a_ready_T_2 & _io_a_ready_T_3; // @[SinkA.scala:78:{25,39,42}] assign io_a_ready_0 = _io_a_ready_T_4; // @[SinkA.scala:38:7, :78:39] wire _io_req_valid_T = io_a_valid_0 & first; // @[Edges.scala:231:25] wire _io_req_valid_T_1 = ~buf_block; // @[SinkA.scala:71:27, :78:28, :79:39] wire _io_req_valid_T_2 = _io_req_valid_T & _io_req_valid_T_1; // @[SinkA.scala:79:{27,36,39}] wire _io_req_valid_T_3 = ~set_block; // @[SinkA.scala:72:36, :78:42, :79:53] assign _io_req_valid_T_4 = _io_req_valid_T_2 & _io_req_valid_T_3; // @[SinkA.scala:79:{36,50,53}] assign io_req_valid_0 = _io_req_valid_T_4; // @[SinkA.scala:38:7, :79:50] wire _putbuffer_io_push_valid_T = io_a_valid_0 & hasData; // @[Edges.scala:92:28] wire _putbuffer_io_push_valid_T_1 = ~req_block; // @[SinkA.scala:70:25, :78:14, :80:52] wire _putbuffer_io_push_valid_T_2 = _putbuffer_io_push_valid_T & _putbuffer_io_push_valid_T_1; // @[SinkA.scala:80:{38,49,52}] wire _putbuffer_io_push_valid_T_3 = ~set_block; // @[SinkA.scala:72:36, :78:42, :80:66] wire _putbuffer_io_push_valid_T_4 = _putbuffer_io_push_valid_T_2 & _putbuffer_io_push_valid_T_3; // @[SinkA.scala:80:{49,63,66}] assign lists_set = _io_req_valid_T & hasData & ~req_block & ~buf_block ? freeOH[39:0] : 40'h0; // @[Edges.scala:92:28] wire _offset_T = io_a_bits_address_0[0]; // @[SinkA.scala:38:7] wire _offset_T_1 = io_a_bits_address_0[1]; // @[SinkA.scala:38:7] wire _offset_T_2 = io_a_bits_address_0[2]; // @[SinkA.scala:38:7] wire _offset_T_3 = io_a_bits_address_0[3]; // @[SinkA.scala:38:7] wire _offset_T_4 = io_a_bits_address_0[4]; // @[SinkA.scala:38:7] wire _offset_T_5 = io_a_bits_address_0[5]; // @[SinkA.scala:38:7] wire _offset_T_6 = io_a_bits_address_0[6]; // @[SinkA.scala:38:7] wire _offset_T_7 = io_a_bits_address_0[7]; // @[SinkA.scala:38:7] wire _offset_T_8 = io_a_bits_address_0[8]; // @[SinkA.scala:38:7] wire _offset_T_9 = io_a_bits_address_0[9]; // @[SinkA.scala:38:7] wire _offset_T_10 = io_a_bits_address_0[10]; // @[SinkA.scala:38:7] wire _offset_T_11 = io_a_bits_address_0[11]; // @[SinkA.scala:38:7] wire _offset_T_12 = io_a_bits_address_0[12]; // @[SinkA.scala:38:7] wire _offset_T_13 = io_a_bits_address_0[13]; // @[SinkA.scala:38:7] wire _offset_T_14 = io_a_bits_address_0[14]; // @[SinkA.scala:38:7] wire _offset_T_15 = io_a_bits_address_0[15]; // @[SinkA.scala:38:7] wire _offset_T_16 = io_a_bits_address_0[16]; // @[SinkA.scala:38:7] wire _offset_T_17 = io_a_bits_address_0[17]; // @[SinkA.scala:38:7] wire _offset_T_18 = io_a_bits_address_0[18]; // @[SinkA.scala:38:7] wire _offset_T_19 = io_a_bits_address_0[19]; // @[SinkA.scala:38:7] wire _offset_T_20 = io_a_bits_address_0[20]; // @[SinkA.scala:38:7] wire _offset_T_21 = io_a_bits_address_0[21]; // @[SinkA.scala:38:7] wire _offset_T_22 = io_a_bits_address_0[22]; // @[SinkA.scala:38:7] wire _offset_T_23 = io_a_bits_address_0[23]; // @[SinkA.scala:38:7] wire _offset_T_24 = io_a_bits_address_0[24]; // @[SinkA.scala:38:7] wire _offset_T_25 = io_a_bits_address_0[25]; // @[SinkA.scala:38:7] wire _offset_T_26 = io_a_bits_address_0[26]; // @[SinkA.scala:38:7] wire _offset_T_27 = io_a_bits_address_0[27]; // @[SinkA.scala:38:7] wire _offset_T_28 = io_a_bits_address_0[31]; // @[SinkA.scala:38:7] wire [1:0] offset_lo_lo_lo_hi = {_offset_T_2, _offset_T_1}; // @[Parameters.scala:214:{21,47}] wire [2:0] offset_lo_lo_lo = {offset_lo_lo_lo_hi, _offset_T}; // @[Parameters.scala:214:{21,47}] wire [1:0] offset_lo_lo_hi_lo = {_offset_T_4, _offset_T_3}; // @[Parameters.scala:214:{21,47}] wire [1:0] offset_lo_lo_hi_hi = {_offset_T_6, _offset_T_5}; // @[Parameters.scala:214:{21,47}] wire [3:0] offset_lo_lo_hi = {offset_lo_lo_hi_hi, offset_lo_lo_hi_lo}; // @[Parameters.scala:214:21] wire [6:0] offset_lo_lo = {offset_lo_lo_hi, offset_lo_lo_lo}; // @[Parameters.scala:214:21] wire [1:0] offset_lo_hi_lo_hi = {_offset_T_9, _offset_T_8}; // @[Parameters.scala:214:{21,47}] wire [2:0] offset_lo_hi_lo = {offset_lo_hi_lo_hi, _offset_T_7}; // @[Parameters.scala:214:{21,47}] wire [1:0] offset_lo_hi_hi_lo = {_offset_T_11, _offset_T_10}; // @[Parameters.scala:214:{21,47}] wire [1:0] offset_lo_hi_hi_hi = {_offset_T_13, _offset_T_12}; // @[Parameters.scala:214:{21,47}] wire [3:0] offset_lo_hi_hi = {offset_lo_hi_hi_hi, offset_lo_hi_hi_lo}; // @[Parameters.scala:214:21] wire [6:0] offset_lo_hi = {offset_lo_hi_hi, offset_lo_hi_lo}; // @[Parameters.scala:214:21] wire [13:0] offset_lo = {offset_lo_hi, offset_lo_lo}; // @[Parameters.scala:214:21] wire [1:0] offset_hi_lo_lo_hi = {_offset_T_16, _offset_T_15}; // @[Parameters.scala:214:{21,47}] wire [2:0] offset_hi_lo_lo = {offset_hi_lo_lo_hi, _offset_T_14}; // @[Parameters.scala:214:{21,47}] wire [1:0] offset_hi_lo_hi_lo = {_offset_T_18, _offset_T_17}; // @[Parameters.scala:214:{21,47}] wire [1:0] offset_hi_lo_hi_hi = {_offset_T_20, _offset_T_19}; // @[Parameters.scala:214:{21,47}] wire [3:0] offset_hi_lo_hi = {offset_hi_lo_hi_hi, offset_hi_lo_hi_lo}; // @[Parameters.scala:214:21] wire [6:0] offset_hi_lo = {offset_hi_lo_hi, offset_hi_lo_lo}; // @[Parameters.scala:214:21] wire [1:0] offset_hi_hi_lo_lo = {_offset_T_22, _offset_T_21}; // @[Parameters.scala:214:{21,47}] wire [1:0] offset_hi_hi_lo_hi = {_offset_T_24, _offset_T_23}; // @[Parameters.scala:214:{21,47}] wire [3:0] offset_hi_hi_lo = {offset_hi_hi_lo_hi, offset_hi_hi_lo_lo}; // @[Parameters.scala:214:21] wire [1:0] offset_hi_hi_hi_lo = {_offset_T_26, _offset_T_25}; // @[Parameters.scala:214:{21,47}] wire [1:0] offset_hi_hi_hi_hi = {_offset_T_28, _offset_T_27}; // @[Parameters.scala:214:{21,47}] wire [3:0] offset_hi_hi_hi = {offset_hi_hi_hi_hi, offset_hi_hi_hi_lo}; // @[Parameters.scala:214:21] wire [7:0] offset_hi_hi = {offset_hi_hi_hi, offset_hi_hi_lo}; // @[Parameters.scala:214:21] wire [14:0] offset_hi = {offset_hi_hi, offset_hi_lo}; // @[Parameters.scala:214:21] wire [28:0] offset = {offset_hi, offset_lo}; // @[Parameters.scala:214:21] wire [22:0] set = offset[28:6]; // @[Parameters.scala:214:21, :215:22] wire [12:0] tag = set[22:10]; // @[Parameters.scala:215:22, :216:19] assign tag_1 = tag; // @[Parameters.scala:216:19, :217:9] assign io_req_bits_tag_0 = tag_1; // @[SinkA.scala:38:7] assign set_1 = set[9:0]; // @[Parameters.scala:215:22, :217:28] assign io_req_bits_set_0 = set_1; // @[SinkA.scala:38:7] assign offset_1 = offset[5:0]; // @[Parameters.scala:214:21, :217:50] assign io_req_bits_offset_0 = offset_1; // @[SinkA.scala:38:7] reg [5:0] put_r; // @[SinkA.scala:84:42] assign put = first ? freeIdx : put_r; // @[OneHot.scala:32:10] assign io_req_bits_put_0 = put; // @[SinkA.scala:38:7, :84:16] wire _putbuffer_io_pop_valid_T = io_pb_pop_ready_0 & io_pb_pop_valid_0; // @[Decoupled.scala:51:35] wire [39:0] _io_pb_pop_ready_T = _putbuffer_io_valid >> io_pb_pop_bits_index_0; // @[SinkA.scala:38:7, :51:25, :105:40] assign _io_pb_pop_ready_T_1 = _io_pb_pop_ready_T[0]; // @[SinkA.scala:105:40] assign io_pb_pop_ready_0 = _io_pb_pop_ready_T_1; // @[SinkA.scala:38:7, :105:40] wire [63:0] _lists_clr_T = 64'h1 << lists_clr_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [39:0] _lists_clr_T_1 = _lists_clr_T[39:0]; // @[OneHot.scala:65:{12,27}] assign lists_clr = _putbuffer_io_pop_valid_T & io_pb_pop_bits_last_0 ? _lists_clr_T_1 : 40'h0; // @[OneHot.scala:65:27] always @(posedge clock) begin // @[SinkA.scala:38:7] if (reset) begin // @[SinkA.scala:38:7] lists <= 40'h0; // @[SinkA.scala:52:22] first_counter <= 1'h0; // @[Edges.scala:229:27] end else begin // @[SinkA.scala:38:7] lists <= _lists_T_2; // @[SinkA.scala:52:22, :56:32] if (_first_T) // @[Decoupled.scala:51:35] first_counter <= _first_counter_T; // @[Edges.scala:229:27, :236:21] end if (first) // @[Edges.scala:231:25] put_r <= freeIdx; // @[OneHot.scala:32:10] always @(posedge) ListBuffer_PutBufferAEntry_q40_e40 putbuffer ( // @[SinkA.scala:51:25] .clock (clock), .reset (reset), .io_push_ready (_putbuffer_io_push_ready), .io_push_valid (_putbuffer_io_push_valid_T_4), // @[SinkA.scala:80:63] .io_push_bits_index (put), // @[SinkA.scala:84:16] .io_push_bits_data_data (io_a_bits_data_0), // @[SinkA.scala:38:7] .io_push_bits_data_mask (io_a_bits_mask_0), // @[SinkA.scala:38:7] .io_push_bits_data_corrupt (io_a_bits_corrupt_0), // @[SinkA.scala:38:7] .io_valid (_putbuffer_io_valid), .io_pop_valid (_putbuffer_io_pop_valid_T), // @[Decoupled.scala:51:35] .io_pop_bits (io_pb_pop_bits_index_0), // @[SinkA.scala:38:7] .io_data_data (io_pb_beat_data_0), .io_data_mask (io_pb_beat_mask_0), .io_data_corrupt (io_pb_beat_corrupt_0) ); // @[SinkA.scala:51:25] assign io_req_valid = io_req_valid_0; // @[SinkA.scala:38:7] assign io_req_bits_opcode = io_req_bits_opcode_0; // @[SinkA.scala:38:7] assign io_req_bits_param = io_req_bits_param_0; // @[SinkA.scala:38:7] assign io_req_bits_size = io_req_bits_size_0; // @[SinkA.scala:38:7] assign io_req_bits_source = io_req_bits_source_0; // @[SinkA.scala:38:7] assign io_req_bits_tag = io_req_bits_tag_0; // @[SinkA.scala:38:7] assign io_req_bits_offset = io_req_bits_offset_0; // @[SinkA.scala:38:7] assign io_req_bits_put = io_req_bits_put_0; // @[SinkA.scala:38:7] assign io_req_bits_set = io_req_bits_set_0; // @[SinkA.scala:38:7] assign io_a_ready = io_a_ready_0; // @[SinkA.scala:38:7] assign io_pb_pop_ready = io_pb_pop_ready_0; // @[SinkA.scala:38:7] assign io_pb_beat_data = io_pb_beat_data_0; // @[SinkA.scala:38:7] assign io_pb_beat_mask = io_pb_beat_mask_0; // @[SinkA.scala:38:7] assign io_pb_beat_corrupt = io_pb_beat_corrupt_0; // @[SinkA.scala:38:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File Repeater.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util.{Decoupled, DecoupledIO} // A Repeater passes its input to its output, unless repeat is asserted. // When repeat is asserted, the Repeater copies the input and repeats it next cycle. class Repeater[T <: Data](gen: T) extends Module { override def desiredName = s"Repeater_${gen.typeName}" val io = IO( new Bundle { val repeat = Input(Bool()) val full = Output(Bool()) val enq = Flipped(Decoupled(gen.cloneType)) val deq = Decoupled(gen.cloneType) } ) val full = RegInit(false.B) val saved = Reg(gen.cloneType) // When !full, a repeater is pass-through io.deq.valid := io.enq.valid \|\| full io.enq.ready := io.deq.ready && !full io.deq.bits := Mux(full, saved, io.enq.bits) io.full := full when (io.enq.fire && io.repeat) { full := true.B; saved := io.enq.bits } when (io.deq.fire && !io.repeat) { full := false.B } } object Repeater { def apply[T <: Data](enq: DecoupledIO[T], repeat: Bool): DecoupledIO[T] = { val repeater = Module(new Repeater(chiselTypeOf(enq.bits))) repeater.io.repeat := repeat repeater.io.enq <> enq repeater.io.deq } }	module Repeater_TLBundleA_a13d64s10k1z3u( // @[Repeater.scala:10:7] input clock, // @[Repeater.scala:10:7] input reset, // @[Repeater.scala:10:7] input io_repeat, // @[Repeater.scala:13:14] output io_full, // @[Repeater.scala:13:14] output io_enq_ready, // @[Repeater.scala:13:14] input io_enq_valid, // @[Repeater.scala:13:14] input [2:0] io_enq_bits_opcode, // @[Repeater.scala:13:14] input [2:0] io_enq_bits_param, // @[Repeater.scala:13:14] input [2:0] io_enq_bits_size, // @[Repeater.scala:13:14] input [9:0] io_enq_bits_source, // @[Repeater.scala:13:14] input [12:0] io_enq_bits_address, // @[Repeater.scala:13:14] input [7:0] io_enq_bits_mask, // @[Repeater.scala:13:14] input [63:0] io_enq_bits_data, // @[Repeater.scala:13:14] input io_enq_bits_corrupt, // @[Repeater.scala:13:14] input io_deq_ready, // @[Repeater.scala:13:14] output io_deq_valid, // @[Repeater.scala:13:14] output [2:0] io_deq_bits_opcode, // @[Repeater.scala:13:14] output [2:0] io_deq_bits_param, // @[Repeater.scala:13:14] output [2:0] io_deq_bits_size, // @[Repeater.scala:13:14] output [9:0] io_deq_bits_source, // @[Repeater.scala:13:14] output [12:0] io_deq_bits_address, // @[Repeater.scala:13:14] output [7:0] io_deq_bits_mask, // @[Repeater.scala:13:14] output io_deq_bits_corrupt // @[Repeater.scala:13:14] ); wire io_repeat_0 = io_repeat; // @[Repeater.scala:10:7] wire io_enq_valid_0 = io_enq_valid; // @[Repeater.scala:10:7] wire [2:0] io_enq_bits_opcode_0 = io_enq_bits_opcode; // @[Repeater.scala:10:7] wire [2:0] io_enq_bits_param_0 = io_enq_bits_param; // @[Repeater.scala:10:7] wire [2:0] io_enq_bits_size_0 = io_enq_bits_size; // @[Repeater.scala:10:7] wire [9:0] io_enq_bits_source_0 = io_enq_bits_source; // @[Repeater.scala:10:7] wire [12:0] io_enq_bits_address_0 = io_enq_bits_address; // @[Repeater.scala:10:7] wire [7:0] io_enq_bits_mask_0 = io_enq_bits_mask; // @[Repeater.scala:10:7] wire [63:0] io_enq_bits_data_0 = io_enq_bits_data; // @[Repeater.scala:10:7] wire io_enq_bits_corrupt_0 = io_enq_bits_corrupt; // @[Repeater.scala:10:7] wire io_deq_ready_0 = io_deq_ready; // @[Repeater.scala:10:7] wire _io_enq_ready_T_1; // @[Repeater.scala:25:32] wire _io_deq_valid_T; // @[Repeater.scala:24:32] wire [2:0] _io_deq_bits_T_opcode; // @[Repeater.scala:26:21] wire [2:0] _io_deq_bits_T_param; // @[Repeater.scala:26:21] wire [2:0] _io_deq_bits_T_size; // @[Repeater.scala:26:21] wire [9:0] _io_deq_bits_T_source; // @[Repeater.scala:26:21] wire [12:0] _io_deq_bits_T_address; // @[Repeater.scala:26:21] wire [7:0] _io_deq_bits_T_mask; // @[Repeater.scala:26:21] wire [63:0] _io_deq_bits_T_data; // @[Repeater.scala:26:21] wire _io_deq_bits_T_corrupt; // @[Repeater.scala:26:21] wire io_enq_ready_0; // @[Repeater.scala:10:7] wire [2:0] io_deq_bits_opcode_0; // @[Repeater.scala:10:7] wire [2:0] io_deq_bits_param_0; // @[Repeater.scala:10:7] wire [2:0] io_deq_bits_size_0; // @[Repeater.scala:10:7] wire [9:0] io_deq_bits_source_0; // @[Repeater.scala:10:7] wire [12:0] io_deq_bits_address_0; // @[Repeater.scala:10:7] wire [7:0] io_deq_bits_mask_0; // @[Repeater.scala:10:7] wire [63:0] io_deq_bits_data; // @[Repeater.scala:10:7] wire io_deq_bits_corrupt_0; // @[Repeater.scala:10:7] wire io_deq_valid_0; // @[Repeater.scala:10:7] wire io_full_0; // @[Repeater.scala:10:7] reg full; // @[Repeater.scala:20:21] assign io_full_0 = full; // @[Repeater.scala:10:7, :20:21] reg [2:0] saved_opcode; // @[Repeater.scala:21:18] reg [2:0] saved_param; // @[Repeater.scala:21:18] reg [2:0] saved_size; // @[Repeater.scala:21:18] reg [9:0] saved_source; // @[Repeater.scala:21:18] reg [12:0] saved_address; // @[Repeater.scala:21:18] reg [7:0] saved_mask; // @[Repeater.scala:21:18] reg [63:0] saved_data; // @[Repeater.scala:21:18] reg saved_corrupt; // @[Repeater.scala:21:18] assign _io_deq_valid_T = io_enq_valid_0 \| full; // @[Repeater.scala:10:7, :20:21, :24:32] assign io_deq_valid_0 = _io_deq_valid_T; // @[Repeater.scala:10:7, :24:32] wire _io_enq_ready_T = ~full; // @[Repeater.scala:20:21, :25:35] assign _io_enq_ready_T_1 = io_deq_ready_0 & _io_enq_ready_T; // @[Repeater.scala:10:7, :25:{32,35}] assign io_enq_ready_0 = _io_enq_ready_T_1; // @[Repeater.scala:10:7, :25:32] assign _io_deq_bits_T_opcode = full ? saved_opcode : io_enq_bits_opcode_0; // @[Repeater.scala:10:7, :20:21, :21:18, :26:21] assign _io_deq_bits_T_param = full ? saved_param : io_enq_bits_param_0; // @[Repeater.scala:10:7, :20:21, :21:18, :26:21] assign _io_deq_bits_T_size = full ? saved_size : io_enq_bits_size_0; // @[Repeater.scala:10:7, :20:21, :21:18, :26:21] assign _io_deq_bits_T_source = full ? saved_source : io_enq_bits_source_0; // @[Repeater.scala:10:7, :20:21, :21:18, :26:21] assign _io_deq_bits_T_address = full ? saved_address : io_enq_bits_address_0; // @[Repeater.scala:10:7, :20:21, :21:18, :26:21] assign _io_deq_bits_T_mask = full ? saved_mask : io_enq_bits_mask_0; // @[Repeater.scala:10:7, :20:21, :21:18, :26:21] assign _io_deq_bits_T_data = full ? saved_data : io_enq_bits_data_0; // @[Repeater.scala:10:7, :20:21, :21:18, :26:21] assign _io_deq_bits_T_corrupt = full ? saved_corrupt : io_enq_bits_corrupt_0; // @[Repeater.scala:10:7, :20:21, :21:18, :26:21] assign io_deq_bits_opcode_0 = _io_deq_bits_T_opcode; // @[Repeater.scala:10:7, :26:21] assign io_deq_bits_param_0 = _io_deq_bits_T_param; // @[Repeater.scala:10:7, :26:21] assign io_deq_bits_size_0 = _io_deq_bits_T_size; // @[Repeater.scala:10:7, :26:21] assign io_deq_bits_source_0 = _io_deq_bits_T_source; // @[Repeater.scala:10:7, :26:21] assign io_deq_bits_address_0 = _io_deq_bits_T_address; // @[Repeater.scala:10:7, :26:21] assign io_deq_bits_mask_0 = _io_deq_bits_T_mask; // @[Repeater.scala:10:7, :26:21] assign io_deq_bits_data = _io_deq_bits_T_data; // @[Repeater.scala:10:7, :26:21] assign io_deq_bits_corrupt_0 = _io_deq_bits_T_corrupt; // @[Repeater.scala:10:7, :26:21] wire _T_1 = io_enq_ready_0 & io_enq_valid_0 & io_repeat_0; // @[Decoupled.scala:51:35] always @(posedge clock) begin // @[Repeater.scala:10:7] if (reset) // @[Repeater.scala:10:7] full <= 1'h0; // @[Repeater.scala:20:21] else // @[Repeater.scala:10:7] full <= ~(io_deq_ready_0 & io_deq_valid_0 & ~io_repeat_0) & (_T_1 \| full); // @[Decoupled.scala:51:35] if (_T_1) begin // @[Decoupled.scala:51:35] saved_opcode <= io_enq_bits_opcode_0; // @[Repeater.scala:10:7, :21:18] saved_param <= io_enq_bits_param_0; // @[Repeater.scala:10:7, :21:18] saved_size <= io_enq_bits_size_0; // @[Repeater.scala:10:7, :21:18] saved_source <= io_enq_bits_source_0; // @[Repeater.scala:10:7, :21:18] saved_address <= io_enq_bits_address_0; // @[Repeater.scala:10:7, :21:18] saved_mask <= io_enq_bits_mask_0; // @[Repeater.scala:10:7, :21:18] saved_data <= io_enq_bits_data_0; // @[Repeater.scala:10:7, :21:18] saved_corrupt <= io_enq_bits_corrupt_0; // @[Repeater.scala:10:7, :21:18] end always @(posedge) assign io_full = io_full_0; // @[Repeater.scala:10:7] assign io_enq_ready = io_enq_ready_0; // @[Repeater.scala:10:7] assign io_deq_valid = io_deq_valid_0; // @[Repeater.scala:10:7] assign io_deq_bits_opcode = io_deq_bits_opcode_0; // @[Repeater.scala:10:7] assign io_deq_bits_param = io_deq_bits_param_0; // @[Repeater.scala:10:7] assign io_deq_bits_size = io_deq_bits_size_0; // @[Repeater.scala:10:7] assign io_deq_bits_source = io_deq_bits_source_0; // @[Repeater.scala:10:7] assign io_deq_bits_address = io_deq_bits_address_0; // @[Repeater.scala:10:7] assign io_deq_bits_mask = io_deq_bits_mask_0; // @[Repeater.scala:10:7] assign io_deq_bits_corrupt = io_deq_bits_corrupt_0; // @[Repeater.scala:10:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File RecFNToRecFN.scala: /============================================================================ This Chisel source file is part of a pre-release version of the HardFloat IEEE Floating-Point Arithmetic Package, by John R. Hauser (with some contributions from Yunsup Lee and Andrew Waterman, mainly concerning testing). Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of California. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions, and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions, and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the University nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. =============================================================================/ package hardfloat import chisel3._ import consts._ class RecFNToRecFN( inExpWidth: Int, inSigWidth: Int, outExpWidth: Int, outSigWidth: Int) extends chisel3.RawModule { val io = IO(new Bundle { val in = Input(Bits((inExpWidth + inSigWidth + 1).W)) val roundingMode = Input(UInt(3.W)) val detectTininess = Input(UInt(1.W)) val out = Output(Bits((outExpWidth + outSigWidth + 1).W)) val exceptionFlags = Output(Bits(5.W)) }) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val rawIn = rawFloatFromRecFN(inExpWidth, inSigWidth, io.in); if ((inExpWidth == outExpWidth) && (inSigWidth <= outSigWidth)) { //-------------------------------------------------------------------- //-------------------------------------------------------------------- io.out := io.in<<(outSigWidth - inSigWidth) io.exceptionFlags := isSigNaNRawFloat(rawIn) ## 0.U(4.W) } else { //-------------------------------------------------------------------- //-------------------------------------------------------------------- val roundAnyRawFNToRecFN = Module( new RoundAnyRawFNToRecFN( inExpWidth, inSigWidth, outExpWidth, outSigWidth, flRoundOpt_sigMSBitAlwaysZero )) roundAnyRawFNToRecFN.io.invalidExc := isSigNaNRawFloat(rawIn) roundAnyRawFNToRecFN.io.infiniteExc := false.B roundAnyRawFNToRecFN.io.in := rawIn roundAnyRawFNToRecFN.io.roundingMode := io.roundingMode roundAnyRawFNToRecFN.io.detectTininess := io.detectTininess io.out := roundAnyRawFNToRecFN.io.out io.exceptionFlags := roundAnyRawFNToRecFN.io.exceptionFlags } } File rawFloatFromRecFN.scala: /============================================================================ This Chisel source file is part of a pre-release version of the HardFloat IEEE Floating-Point Arithmetic Package, by John R. Hauser (with some contributions from Yunsup Lee and Andrew Waterman, mainly concerning testing). Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of California. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions, and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions, and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the University nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. =============================================================================/ package hardfloat import chisel3._ import chisel3.util._ /---------------------------------------------------------------------------- \| In the result, no more than one of 'isNaN', 'isInf', and 'isZero' will be \| set. ----------------------------------------------------------------------------*/ object rawFloatFromRecFN { def apply(expWidth: Int, sigWidth: Int, in: Bits): RawFloat = { val exp = in(expWidth + sigWidth - 1, sigWidth - 1) val isZero = exp(expWidth, expWidth - 2) === 0.U val isSpecial = exp(expWidth, expWidth - 1) === 3.U val out = Wire(new RawFloat(expWidth, sigWidth)) out.isNaN := isSpecial && exp(expWidth - 2) out.isInf := isSpecial && ! exp(expWidth - 2) out.isZero := isZero out.sign := in(expWidth + sigWidth) out.sExp := exp.zext out.sig := 0.U(1.W) ## ! isZero ## in(sigWidth - 2, 0) out } }	module RecFNToRecFN_148( // @[RecFNToRecFN.scala:44:5] input [32:0] io_in, // @[RecFNToRecFN.scala:48:16] output [32:0] io_out // @[RecFNToRecFN.scala:48:16] ); wire [32:0] io_in_0 = io_in; // @[RecFNToRecFN.scala:44:5] wire io_detectTininess = 1'h1; // @[RecFNToRecFN.scala:44:5, :48:16] wire [2:0] io_roundingMode = 3'h0; // @[RecFNToRecFN.scala:44:5, :48:16] wire [32:0] _io_out_T = io_in_0; // @[RecFNToRecFN.scala:44:5, :64:35] wire [4:0] _io_exceptionFlags_T_3; // @[RecFNToRecFN.scala:65:54] wire [32:0] io_out_0; // @[RecFNToRecFN.scala:44:5] wire [4:0] io_exceptionFlags; // @[RecFNToRecFN.scala:44:5] wire [8:0] rawIn_exp = io_in_0[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _rawIn_isZero_T = rawIn_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire rawIn_isZero = _rawIn_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire rawIn_isZero_0 = rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _rawIn_isSpecial_T = rawIn_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire rawIn_isSpecial = &_rawIn_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33] wire _rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33] wire _rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44] wire rawIn_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23] wire rawIn_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] rawIn_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] rawIn_sig; // @[rawFloatFromRecFN.scala:55:23] wire _rawIn_out_isNaN_T = rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _rawIn_out_isInf_T = rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _rawIn_out_isNaN_T_1 = rawIn_isSpecial & _rawIn_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign rawIn_isNaN = _rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _rawIn_out_isInf_T_1 = ~_rawIn_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _rawIn_out_isInf_T_2 = rawIn_isSpecial & _rawIn_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign rawIn_isInf = _rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _rawIn_out_sign_T = io_in_0[32]; // @[rawFloatFromRecFN.scala:59:25] assign rawIn_sign = _rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _rawIn_out_sExp_T = {1'h0, rawIn_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign rawIn_sExp = _rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _rawIn_out_sig_T = ~rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _rawIn_out_sig_T_1 = {1'h0, _rawIn_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _rawIn_out_sig_T_2 = io_in_0[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _rawIn_out_sig_T_3 = {_rawIn_out_sig_T_1, _rawIn_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign rawIn_sig = _rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44] assign io_out_0 = _io_out_T; // @[RecFNToRecFN.scala:44:5, :64:35] wire _io_exceptionFlags_T = rawIn_sig[22]; // @[rawFloatFromRecFN.scala:55:23] wire _io_exceptionFlags_T_1 = ~_io_exceptionFlags_T; // @[common.scala:82:{49,56}] wire _io_exceptionFlags_T_2 = rawIn_isNaN & _io_exceptionFlags_T_1; // @[rawFloatFromRecFN.scala:55:23] assign _io_exceptionFlags_T_3 = {_io_exceptionFlags_T_2, 4'h0}; // @[common.scala:82:46] assign io_exceptionFlags = _io_exceptionFlags_T_3; // @[RecFNToRecFN.scala:44:5, :65:54] assign io_out = io_out_0; // @[RecFNToRecFN.scala:44:5] endmodule
Generate the Verilog code corresponding to the following Chisel files. File InputUnit.scala: package constellation.router import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.{Field, Parameters} import freechips.rocketchip.util._ import constellation.channel._ import constellation.routing.{FlowRoutingBundle} import constellation.noc.{HasNoCParams} class AbstractInputUnitIO( val cParam: BaseChannelParams, val outParams: Seq[ChannelParams], val egressParams: Seq[EgressChannelParams], )(implicit val p: Parameters) extends Bundle with HasRouterOutputParams { val nodeId = cParam.destId val router_req = Decoupled(new RouteComputerReq) val router_resp = Input(new RouteComputerResp(outParams, egressParams)) val vcalloc_req = Decoupled(new VCAllocReq(cParam, outParams, egressParams)) val vcalloc_resp = Input(new VCAllocResp(outParams, egressParams)) val out_credit_available = Input(MixedVec(allOutParams.map { u => Vec(u.nVirtualChannels, Bool()) })) val salloc_req = Vec(cParam.destSpeedup, Decoupled(new SwitchAllocReq(outParams, egressParams))) val out = Vec(cParam.destSpeedup, Valid(new SwitchBundle(outParams, egressParams))) val debug = Output(new Bundle { val va_stall = UInt(log2Ceil(cParam.nVirtualChannels).W) val sa_stall = UInt(log2Ceil(cParam.nVirtualChannels).W) }) val block = Input(Bool()) } abstract class AbstractInputUnit( val cParam: BaseChannelParams, val outParams: Seq[ChannelParams], val egressParams: Seq[EgressChannelParams] )(implicit val p: Parameters) extends Module with HasRouterOutputParams with HasNoCParams { val nodeId = cParam.destId def io: AbstractInputUnitIO } class InputBuffer(cParam: ChannelParams)(implicit p: Parameters) extends Module { val nVirtualChannels = cParam.nVirtualChannels val io = IO(new Bundle { val enq = Flipped(Vec(cParam.srcSpeedup, Valid(new Flit(cParam.payloadBits)))) val deq = Vec(cParam.nVirtualChannels, Decoupled(new BaseFlit(cParam.payloadBits))) }) val useOutputQueues = cParam.useOutputQueues val delims = if (useOutputQueues) { cParam.virtualChannelParams.map(u => if (u.traversable) u.bufferSize else 0).scanLeft(0)(_+_) } else { // If no queuing, have to add an additional slot since head == tail implies empty // TODO this should be fixed, should use all slots available cParam.virtualChannelParams.map(u => if (u.traversable) u.bufferSize + 1 else 0).scanLeft(0)(_+_) } val starts = delims.dropRight(1).zipWithIndex.map { case (s,i) => if (cParam.virtualChannelParams(i).traversable) s else 0 } val ends = delims.tail.zipWithIndex.map { case (s,i) => if (cParam.virtualChannelParams(i).traversable) s else 0 } val fullSize = delims.last // Ugly case. Use multiple queues if ((cParam.srcSpeedup > 1 \|\| cParam.destSpeedup > 1 \|\| fullSize <= 1) \|\| !cParam.unifiedBuffer) { require(useOutputQueues) val qs = cParam.virtualChannelParams.map(v => Module(new Queue(new BaseFlit(cParam.payloadBits), v.bufferSize))) qs.zipWithIndex.foreach { case (q,i) => val sel = io.enq.map(f => f.valid && f.bits.virt_channel_id === i.U) q.io.enq.valid := sel.orR q.io.enq.bits.head := Mux1H(sel, io.enq.map(_.bits.head)) q.io.enq.bits.tail := Mux1H(sel, io.enq.map(_.bits.tail)) q.io.enq.bits.payload := Mux1H(sel, io.enq.map(_.bits.payload)) io.deq(i) <> q.io.deq } } else { val mem = Mem(fullSize, new BaseFlit(cParam.payloadBits)) val heads = RegInit(VecInit(starts.map(_.U(log2Ceil(fullSize).W)))) val tails = RegInit(VecInit(starts.map(_.U(log2Ceil(fullSize).W)))) val empty = (heads zip tails).map(t => t._1 === t._2) val qs = Seq.fill(nVirtualChannels) { Module(new Queue(new BaseFlit(cParam.payloadBits), 1, pipe=true)) } qs.foreach(_.io.enq.valid := false.B) qs.foreach(_.io.enq.bits := DontCare) val vc_sel = UIntToOH(io.enq(0).bits.virt_channel_id) val flit = Wire(new BaseFlit(cParam.payloadBits)) val direct_to_q = (Mux1H(vc_sel, qs.map(_.io.enq.ready)) && Mux1H(vc_sel, empty)) && useOutputQueues.B flit.head := io.enq(0).bits.head flit.tail := io.enq(0).bits.tail flit.payload := io.enq(0).bits.payload when (io.enq(0).valid && !direct_to_q) { val tail = tails(io.enq(0).bits.virt_channel_id) mem.write(tail, flit) tails(io.enq(0).bits.virt_channel_id) := Mux( tail === Mux1H(vc_sel, ends.map(_ - 1).map(_ max 0).map(_.U)), Mux1H(vc_sel, starts.map(_.U)), tail + 1.U) } .elsewhen (io.enq(0).valid && direct_to_q) { for (i <- 0 until nVirtualChannels) { when (io.enq(0).bits.virt_channel_id === i.U) { qs(i).io.enq.valid := true.B qs(i).io.enq.bits := flit } } } if (useOutputQueues) { val can_to_q = (0 until nVirtualChannels).map { i => !empty(i) && qs(i).io.enq.ready } val to_q_oh = PriorityEncoderOH(can_to_q) val to_q = OHToUInt(to_q_oh) when (can_to_q.orR) { val head = Mux1H(to_q_oh, heads) heads(to_q) := Mux( head === Mux1H(to_q_oh, ends.map(_ - 1).map(_ max 0).map(_.U)), Mux1H(to_q_oh, starts.map(_.U)), head + 1.U) for (i <- 0 until nVirtualChannels) { when (to_q_oh(i)) { qs(i).io.enq.valid := true.B qs(i).io.enq.bits := mem.read(head) } } } for (i <- 0 until nVirtualChannels) { io.deq(i) <> qs(i).io.deq } } else { qs.map(_.io.deq.ready := false.B) val ready_sel = io.deq.map(_.ready) val fire = io.deq.map(_.fire) assert(PopCount(fire) <= 1.U) val head = Mux1H(fire, heads) when (fire.orR) { val fire_idx = OHToUInt(fire) heads(fire_idx) := Mux( head === Mux1H(fire, ends.map(_ - 1).map(_ max 0).map(_.U)), Mux1H(fire, starts.map(_.U)), head + 1.U) } val read_flit = mem.read(head) for (i <- 0 until nVirtualChannels) { io.deq(i).valid := !empty(i) io.deq(i).bits := read_flit } } } } class InputUnit(cParam: ChannelParams, outParams: Seq[ChannelParams], egressParams: Seq[EgressChannelParams], combineRCVA: Boolean, combineSAST: Boolean ) (implicit p: Parameters) extends AbstractInputUnit(cParam, outParams, egressParams)(p) { val nVirtualChannels = cParam.nVirtualChannels val virtualChannelParams = cParam.virtualChannelParams class InputUnitIO extends AbstractInputUnitIO(cParam, outParams, egressParams) { val in = Flipped(new Channel(cParam.asInstanceOf[ChannelParams])) } val io = IO(new InputUnitIO) val g_i :: g_r :: g_v :: g_a :: g_c :: Nil = Enum(5) class InputState extends Bundle { val g = UInt(3.W) val vc_sel = MixedVec(allOutParams.map { u => Vec(u.nVirtualChannels, Bool()) }) val flow = new FlowRoutingBundle val fifo_deps = UInt(nVirtualChannels.W) } val input_buffer = Module(new InputBuffer(cParam)) for (i <- 0 until cParam.srcSpeedup) { input_buffer.io.enq(i) := io.in.flit(i) } input_buffer.io.deq.foreach(_.ready := false.B) val route_arbiter = Module(new Arbiter( new RouteComputerReq, nVirtualChannels )) io.router_req <> route_arbiter.io.out val states = Reg(Vec(nVirtualChannels, new InputState)) val anyFifo = cParam.possibleFlows.map(_.fifo).reduce(_\|\|_) val allFifo = cParam.possibleFlows.map(_.fifo).reduce(_&&_) if (anyFifo) { val idle_mask = VecInit(states.map(_.g === g_i)).asUInt for (s <- states) for (i <- 0 until nVirtualChannels) s.fifo_deps := s.fifo_deps & ~idle_mask } for (i <- 0 until cParam.srcSpeedup) { when (io.in.flit(i).fire && io.in.flit(i).bits.head) { val id = io.in.flit(i).bits.virt_channel_id assert(id < nVirtualChannels.U) assert(states(id).g === g_i) val at_dest = io.in.flit(i).bits.flow.egress_node === nodeId.U states(id).g := Mux(at_dest, g_v, g_r) states(id).vc_sel.foreach(_.foreach(_ := false.B)) for (o <- 0 until nEgress) { when (o.U === io.in.flit(i).bits.flow.egress_node_id) { states(id).vc_sel(o+nOutputs)(0) := true.B } } states(id).flow := io.in.flit(i).bits.flow if (anyFifo) { val fifo = cParam.possibleFlows.filter(_.fifo).map(_.isFlow(io.in.flit(i).bits.flow)).toSeq.orR states(id).fifo_deps := VecInit(states.zipWithIndex.map { case (s, j) => s.g =/= g_i && s.flow.asUInt === io.in.flit(i).bits.flow.asUInt && j.U =/= id }).asUInt } } } (route_arbiter.io.in zip states).zipWithIndex.map { case ((i,s),idx) => if (virtualChannelParams(idx).traversable) { i.valid := s.g === g_r i.bits.flow := s.flow i.bits.src_virt_id := idx.U when (i.fire) { s.g := g_v } } else { i.valid := false.B i.bits := DontCare } } when (io.router_req.fire) { val id = io.router_req.bits.src_virt_id assert(states(id).g === g_r) states(id).g := g_v for (i <- 0 until nVirtualChannels) { when (i.U === id) { states(i).vc_sel := io.router_resp.vc_sel } } } val mask = RegInit(0.U(nVirtualChannels.W)) val vcalloc_reqs = Wire(Vec(nVirtualChannels, new VCAllocReq(cParam, outParams, egressParams))) val vcalloc_vals = Wire(Vec(nVirtualChannels, Bool())) val vcalloc_filter = PriorityEncoderOH(Cat(vcalloc_vals.asUInt, vcalloc_vals.asUInt & ~mask)) val vcalloc_sel = vcalloc_filter(nVirtualChannels-1,0) \| (vcalloc_filter >> nVirtualChannels) // Prioritize incoming packetes when (io.router_req.fire) { mask := (1.U << io.router_req.bits.src_virt_id) - 1.U } .elsewhen (vcalloc_vals.orR) { mask := Mux1H(vcalloc_sel, (0 until nVirtualChannels).map { w => ~(0.U((w+1).W)) }) } io.vcalloc_req.valid := vcalloc_vals.orR io.vcalloc_req.bits := Mux1H(vcalloc_sel, vcalloc_reqs) states.zipWithIndex.map { case (s,idx) => if (virtualChannelParams(idx).traversable) { vcalloc_vals(idx) := s.g === g_v && s.fifo_deps === 0.U vcalloc_reqs(idx).in_vc := idx.U vcalloc_reqs(idx).vc_sel := s.vc_sel vcalloc_reqs(idx).flow := s.flow when (vcalloc_vals(idx) && vcalloc_sel(idx) && io.vcalloc_req.ready) { s.g := g_a } if (combineRCVA) { when (route_arbiter.io.in(idx).fire) { vcalloc_vals(idx) := true.B vcalloc_reqs(idx).vc_sel := io.router_resp.vc_sel } } } else { vcalloc_vals(idx) := false.B vcalloc_reqs(idx) := DontCare } } io.debug.va_stall := PopCount(vcalloc_vals) - io.vcalloc_req.ready when (io.vcalloc_req.fire) { for (i <- 0 until nVirtualChannels) { when (vcalloc_sel(i)) { states(i).vc_sel := io.vcalloc_resp.vc_sel states(i).g := g_a if (!combineRCVA) { assert(states(i).g === g_v) } } } } val salloc_arb = Module(new SwitchArbiter( nVirtualChannels, cParam.destSpeedup, outParams, egressParams )) (states zip salloc_arb.io.in).zipWithIndex.map { case ((s,r),i) => if (virtualChannelParams(i).traversable) { val credit_available = (s.vc_sel.asUInt & io.out_credit_available.asUInt) =/= 0.U r.valid := s.g === g_a && credit_available && input_buffer.io.deq(i).valid r.bits.vc_sel := s.vc_sel val deq_tail = input_buffer.io.deq(i).bits.tail r.bits.tail := deq_tail when (r.fire && deq_tail) { s.g := g_i } input_buffer.io.deq(i).ready := r.ready } else { r.valid := false.B r.bits := DontCare } } io.debug.sa_stall := PopCount(salloc_arb.io.in.map(r => r.valid && !r.ready)) io.salloc_req <> salloc_arb.io.out when (io.block) { salloc_arb.io.out.foreach(_.ready := false.B) io.salloc_req.foreach(_.valid := false.B) } class OutBundle extends Bundle { val valid = Bool() val vid = UInt(virtualChannelBits.W) val out_vid = UInt(log2Up(allOutParams.map(_.nVirtualChannels).max).W) val flit = new Flit(cParam.payloadBits) } val salloc_outs = if (combineSAST) { Wire(Vec(cParam.destSpeedup, new OutBundle)) } else { Reg(Vec(cParam.destSpeedup, new OutBundle)) } io.in.credit_return := salloc_arb.io.out.zipWithIndex.map { case (o, i) => Mux(o.fire, salloc_arb.io.chosen_oh(i), 0.U) }.reduce(_\|_) io.in.vc_free := salloc_arb.io.out.zipWithIndex.map { case (o, i) => Mux(o.fire && Mux1H(salloc_arb.io.chosen_oh(i), input_buffer.io.deq.map(_.bits.tail)), salloc_arb.io.chosen_oh(i), 0.U) }.reduce(_\|_) for (i <- 0 until cParam.destSpeedup) { val salloc_out = salloc_outs(i) salloc_out.valid := salloc_arb.io.out(i).fire salloc_out.vid := OHToUInt(salloc_arb.io.chosen_oh(i)) val vc_sel = Mux1H(salloc_arb.io.chosen_oh(i), states.map(_.vc_sel)) val channel_oh = vc_sel.map(_.reduce(_\|\|_)).toSeq val virt_channel = Mux1H(channel_oh, vc_sel.map(v => OHToUInt(v)).toSeq) when (salloc_arb.io.out(i).fire) { salloc_out.out_vid := virt_channel salloc_out.flit.payload := Mux1H(salloc_arb.io.chosen_oh(i), input_buffer.io.deq.map(_.bits.payload)) salloc_out.flit.head := Mux1H(salloc_arb.io.chosen_oh(i), input_buffer.io.deq.map(_.bits.head)) salloc_out.flit.tail := Mux1H(salloc_arb.io.chosen_oh(i), input_buffer.io.deq.map(_.bits.tail)) salloc_out.flit.flow := Mux1H(salloc_arb.io.chosen_oh(i), states.map(_.flow)) } .otherwise { salloc_out.out_vid := DontCare salloc_out.flit := DontCare } salloc_out.flit.virt_channel_id := DontCare // this gets set in the switch io.out(i).valid := salloc_out.valid io.out(i).bits.flit := salloc_out.flit io.out(i).bits.out_virt_channel := salloc_out.out_vid } def filterVCSel(sel: MixedVec[Vec[Bool]], srcV: Int) = { if (virtualChannelParams(srcV).traversable) { outParams.zipWithIndex.map { case (oP, oI) => (0 until oP.nVirtualChannels).map { oV => var allow = false virtualChannelParams(srcV).possibleFlows.foreach { pI => allow = allow \|\| routingRelation( cParam.channelRoutingInfos(srcV), oP.channelRoutingInfos(oV), pI ) } if (!allow) sel(oI)(oV) := false.B } } } } (0 until nVirtualChannels).map { i => if (!virtualChannelParams(i).traversable) states(i) := DontCare filterVCSel(states(i).vc_sel, i) } when (reset.asBool) { states.foreach(_.g := g_i) } }	module InputUnit_80( // @[InputUnit.scala:158:7] input clock, // @[InputUnit.scala:158:7] input reset, // @[InputUnit.scala:158:7] input io_vcalloc_req_ready, // @[InputUnit.scala:170:14] output io_vcalloc_req_valid, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_3_0, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_2_0, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_1_0, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_3_0, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_2_0, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_1_0, // @[InputUnit.scala:170:14] input io_out_credit_available_3_0, // @[InputUnit.scala:170:14] input io_out_credit_available_2_0, // @[InputUnit.scala:170:14] input io_out_credit_available_1_0, // @[InputUnit.scala:170:14] input io_out_credit_available_0_1, // @[InputUnit.scala:170:14] input io_salloc_req_0_ready, // @[InputUnit.scala:170:14] output io_salloc_req_0_valid, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_3_0, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_2_0, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_1_0, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_tail, // @[InputUnit.scala:170:14] output io_out_0_valid, // @[InputUnit.scala:170:14] output io_out_0_bits_flit_head, // @[InputUnit.scala:170:14] output io_out_0_bits_flit_tail, // @[InputUnit.scala:170:14] output [72:0] io_out_0_bits_flit_payload, // @[InputUnit.scala:170:14] output [2:0] io_out_0_bits_flit_flow_vnet_id, // @[InputUnit.scala:170:14] output [4:0] io_out_0_bits_flit_flow_ingress_node, // @[InputUnit.scala:170:14] output [1:0] io_out_0_bits_flit_flow_ingress_node_id, // @[InputUnit.scala:170:14] output [4:0] io_out_0_bits_flit_flow_egress_node, // @[InputUnit.scala:170:14] output [1:0] io_out_0_bits_flit_flow_egress_node_id, // @[InputUnit.scala:170:14] output [2:0] io_debug_va_stall, // @[InputUnit.scala:170:14] output [2:0] io_debug_sa_stall, // @[InputUnit.scala:170:14] input io_in_flit_0_valid, // @[InputUnit.scala:170:14] input io_in_flit_0_bits_head, // @[InputUnit.scala:170:14] input io_in_flit_0_bits_tail, // @[InputUnit.scala:170:14] input [72:0] io_in_flit_0_bits_payload, // @[InputUnit.scala:170:14] input [2:0] io_in_flit_0_bits_flow_vnet_id, // @[InputUnit.scala:170:14] input [4:0] io_in_flit_0_bits_flow_ingress_node, // @[InputUnit.scala:170:14] input [1:0] io_in_flit_0_bits_flow_ingress_node_id, // @[InputUnit.scala:170:14] input [4:0] io_in_flit_0_bits_flow_egress_node, // @[InputUnit.scala:170:14] input [1:0] io_in_flit_0_bits_flow_egress_node_id, // @[InputUnit.scala:170:14] input [2:0] io_in_flit_0_bits_virt_channel_id, // @[InputUnit.scala:170:14] output [4:0] io_in_credit_return, // @[InputUnit.scala:170:14] output [4:0] io_in_vc_free // @[InputUnit.scala:170:14] ); wire vcalloc_vals_4; // @[InputUnit.scala:266:32] wire _salloc_arb_io_in_4_ready; // @[InputUnit.scala:296:26] wire _salloc_arb_io_out_0_valid; // @[InputUnit.scala:296:26] wire [4:0] _salloc_arb_io_chosen_oh_0; // @[InputUnit.scala:296:26] wire _route_arbiter_io_in_4_ready; // @[InputUnit.scala:187:29] wire _route_arbiter_io_out_valid; // @[InputUnit.scala:187:29] wire [2:0] _route_arbiter_io_out_bits_src_virt_id; // @[InputUnit.scala:187:29] wire _input_buffer_io_deq_0_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_0_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_0_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_1_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_1_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_1_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_2_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_2_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_2_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_3_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_3_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_3_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_4_valid; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_4_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_4_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_4_bits_payload; // @[InputUnit.scala:181:28] reg [2:0] states_4_g; // @[InputUnit.scala:192:19] reg states_4_vc_sel_3_0; // @[InputUnit.scala:192:19] reg states_4_vc_sel_2_0; // @[InputUnit.scala:192:19] reg states_4_vc_sel_1_0; // @[InputUnit.scala:192:19] reg [2:0] states_4_flow_vnet_id; // @[InputUnit.scala:192:19] reg [4:0] states_4_flow_ingress_node; // @[InputUnit.scala:192:19] reg [1:0] states_4_flow_ingress_node_id; // @[InputUnit.scala:192:19] reg [4:0] states_4_flow_egress_node; // @[InputUnit.scala:192:19] reg [1:0] states_4_flow_egress_node_id; // @[InputUnit.scala:192:19] wire _GEN = io_in_flit_0_valid & io_in_flit_0_bits_head; // @[InputUnit.scala:205:30] wire route_arbiter_io_in_4_valid = states_4_g == 3'h1; // @[InputUnit.scala:192:19, :229:22] reg [4:0] mask; // @[InputUnit.scala:250:21] wire [4:0] _vcalloc_filter_T_3 = {vcalloc_vals_4, 4'h0} & ~mask; // @[InputUnit.scala:158:7, :250:21, :253:{80,87,89}, :266:32] wire [9:0] vcalloc_filter = _vcalloc_filter_T_3[0] ? 10'h1 : _vcalloc_filter_T_3[1] ? 10'h2 : _vcalloc_filter_T_3[2] ? 10'h4 : _vcalloc_filter_T_3[3] ? 10'h8 : _vcalloc_filter_T_3[4] ? 10'h10 : {vcalloc_vals_4, 9'h0}; // @[OneHot.scala:85:71] wire [4:0] vcalloc_sel = vcalloc_filter[4:0] \| vcalloc_filter[9:5]; // @[Mux.scala:50:70] assign vcalloc_vals_4 = states_4_g == 3'h2; // @[InputUnit.scala:192:19, :266:32] wire _GEN_0 = io_vcalloc_req_ready & vcalloc_vals_4; // @[Decoupled.scala:51:35] wire _GEN_1 = _GEN_0 & vcalloc_sel[4]; // @[Mux.scala:32:36]
Generate the Verilog code corresponding to the following Chisel files. File ShiftReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ // Similar to the Chisel ShiftRegister but allows the user to suggest a // name to the registers that get instantiated, and // to provide a reset value. object ShiftRegInit { def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T = (0 until n).foldRight(in) { case (i, next) => { val r = RegNext(next, init) name.foreach { na => r.suggestName(s"${na}_${i}") } r } } } /** These wrap behavioral * shift registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * The different types vary in their reset behavior: * AsyncResetShiftReg -- Asynchronously reset register array * A W(width) x D(depth) sized array is constructed from D instantiations of a * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg, * but only used for timing applications */ abstract class AbstractPipelineReg(w: Int = 1) extends Module { val io = IO(new Bundle { val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) } ) } object AbstractPipelineReg { def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = { val chain = Module(gen) name.foreach{ chain.suggestName(_) } chain.io.d := in.asUInt chain.io.q.asTypeOf(in) } } class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) { require(depth > 0, "Depth must be greater than 0.") override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}" val chain = List.tabulate(depth) { i => Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}") } chain.last.io.d := io.d chain.last.io.en := true.B (chain.init zip chain.tail).foreach { case (sink, source) => sink.io.d := source.io.q sink.io.en := true.B } io.q := chain.head.io.q } object AsyncResetShiftReg { def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name) def apply [T <: Data](in: T, depth: Int, name: Option[String]): T = apply(in, depth, 0, name) def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T = apply(in, depth, init.litValue.toInt, name) def apply [T <: Data](in: T, depth: Int, init: T): T = apply (in, depth, init.litValue.toInt, None) } File AsyncQueue.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ case class AsyncQueueParams( depth: Int = 8, sync: Int = 3, safe: Boolean = true, // If safe is true, then effort is made to resynchronize the crossing indices when either side is reset. // This makes it safe/possible to reset one side of the crossing (but not the other) when the queue is empty. narrow: Boolean = false) // If narrow is true then the read mux is moved to the source side of the crossing. // This reduces the number of level shifters in the case where the clock crossing is also a voltage crossing, // at the expense of a combinational path from the sink to the source and back to the sink. { require (depth > 0 && isPow2(depth)) require (sync >= 2) val bits = log2Ceil(depth) val wires = if (narrow) 1 else depth } object AsyncQueueParams { // When there is only one entry, we don't need narrow. def singleton(sync: Int = 3, safe: Boolean = true) = AsyncQueueParams(1, sync, safe, false) } class AsyncBundleSafety extends Bundle { val ridx_valid = Input (Bool()) val widx_valid = Output(Bool()) val source_reset_n = Output(Bool()) val sink_reset_n = Input (Bool()) } class AsyncBundle[T <: Data](private val gen: T, val params: AsyncQueueParams = AsyncQueueParams()) extends Bundle { // Data-path synchronization val mem = Output(Vec(params.wires, gen)) val ridx = Input (UInt((params.bits+1).W)) val widx = Output(UInt((params.bits+1).W)) val index = params.narrow.option(Input(UInt(params.bits.W))) // Signals used to self-stabilize a safe AsyncQueue val safe = params.safe.option(new AsyncBundleSafety) } object GrayCounter { def apply(bits: Int, increment: Bool = true.B, clear: Bool = false.B, name: String = "binary"): UInt = { val incremented = Wire(UInt(bits.W)) val binary = RegNext(next=incremented, init=0.U).suggestName(name) incremented := Mux(clear, 0.U, binary + increment.asUInt) incremented ^ (incremented >> 1) } } class AsyncValidSync(sync: Int, desc: String) extends RawModule { val io = IO(new Bundle { val in = Input(Bool()) val out = Output(Bool()) }) val clock = IO(Input(Clock())) val reset = IO(Input(AsyncReset())) withClockAndReset(clock, reset){ io.out := AsyncResetSynchronizerShiftReg(io.in, sync, Some(desc)) } } class AsyncQueueSource[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module { override def desiredName = s"AsyncQueueSource_${gen.typeName}" val io = IO(new Bundle { // These come from the source domain val enq = Flipped(Decoupled(gen)) // These cross to the sink clock domain val async = new AsyncBundle(gen, params) }) val bits = params.bits val sink_ready = WireInit(true.B) val mem = Reg(Vec(params.depth, gen)) // This does NOT need to be reset at all. val widx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.enq.fire, !sink_ready, "widx_bin")) val ridx = AsyncResetSynchronizerShiftReg(io.async.ridx, params.sync, Some("ridx_gray")) val ready = sink_ready && widx =/= (ridx ^ (params.depth \| params.depth >> 1).U) val index = if (bits == 0) 0.U else io.async.widx(bits-1, 0) ^ (io.async.widx(bits, bits) << (bits-1)) when (io.enq.fire) { mem(index) := io.enq.bits } val ready_reg = withReset(reset.asAsyncReset)(RegNext(next=ready, init=false.B).suggestName("ready_reg")) io.enq.ready := ready_reg && sink_ready val widx_reg = withReset(reset.asAsyncReset)(RegNext(next=widx, init=0.U).suggestName("widx_gray")) io.async.widx := widx_reg io.async.index match { case Some(index) => io.async.mem(0) := mem(index) case None => io.async.mem := mem } io.async.safe.foreach { sio => val source_valid_0 = Module(new AsyncValidSync(params.sync, "source_valid_0")) val source_valid_1 = Module(new AsyncValidSync(params.sync, "source_valid_1")) val sink_extend = Module(new AsyncValidSync(params.sync, "sink_extend")) val sink_valid = Module(new AsyncValidSync(params.sync, "sink_valid")) source_valid_0.reset := (reset.asBool \|\| !sio.sink_reset_n).asAsyncReset source_valid_1.reset := (reset.asBool \|\| !sio.sink_reset_n).asAsyncReset sink_extend .reset := (reset.asBool \|\| !sio.sink_reset_n).asAsyncReset sink_valid .reset := reset.asAsyncReset source_valid_0.clock := clock source_valid_1.clock := clock sink_extend .clock := clock sink_valid .clock := clock source_valid_0.io.in := true.B source_valid_1.io.in := source_valid_0.io.out sio.widx_valid := source_valid_1.io.out sink_extend.io.in := sio.ridx_valid sink_valid.io.in := sink_extend.io.out sink_ready := sink_valid.io.out sio.source_reset_n := !reset.asBool // Assert that if there is stuff in the queue, then reset cannot happen // Impossible to write because dequeue can occur on the receiving side, // then reset allowed to happen, but write side cannot know that dequeue // occurred. // TODO: write some sort of sanity check assertion for users // that denote don't reset when there is activity // assert (!(reset \|\| !sio.sink_reset_n) \|\| !io.enq.valid, "Enqueue while sink is reset and AsyncQueueSource is unprotected") // assert (!reset_rise \|\| prev_idx_match.asBool, "Sink reset while AsyncQueueSource not empty") } } class AsyncQueueSink[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module { override def desiredName = s"AsyncQueueSink_${gen.typeName}" val io = IO(new Bundle { // These come from the sink domain val deq = Decoupled(gen) // These cross to the source clock domain val async = Flipped(new AsyncBundle(gen, params)) }) val bits = params.bits val source_ready = WireInit(true.B) val ridx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.deq.fire, !source_ready, "ridx_bin")) val widx = AsyncResetSynchronizerShiftReg(io.async.widx, params.sync, Some("widx_gray")) val valid = source_ready && ridx =/= widx // The mux is safe because timing analysis ensures ridx has reached the register // On an ASIC, changes to the unread location cannot affect the selected value // On an FPGA, only one input changes at a time => mem updates don't cause glitches // The register only latches when the selected valued is not being written val index = if (bits == 0) 0.U else ridx(bits-1, 0) ^ (ridx(bits, bits) << (bits-1)) io.async.index.foreach { _ := index } // This register does not NEED to be reset, as its contents will not // be considered unless the asynchronously reset deq valid register is set. // It is possible that bits latches when the source domain is reset / has power cut // This is safe, because isolation gates brought mem low before the zeroed widx reached us val deq_bits_nxt = io.async.mem(if (params.narrow) 0.U else index) io.deq.bits := ClockCrossingReg(deq_bits_nxt, en = valid, doInit = false, name = Some("deq_bits_reg")) val valid_reg = withReset(reset.asAsyncReset)(RegNext(next=valid, init=false.B).suggestName("valid_reg")) io.deq.valid := valid_reg && source_ready val ridx_reg = withReset(reset.asAsyncReset)(RegNext(next=ridx, init=0.U).suggestName("ridx_gray")) io.async.ridx := ridx_reg io.async.safe.foreach { sio => val sink_valid_0 = Module(new AsyncValidSync(params.sync, "sink_valid_0")) val sink_valid_1 = Module(new AsyncValidSync(params.sync, "sink_valid_1")) val source_extend = Module(new AsyncValidSync(params.sync, "source_extend")) val source_valid = Module(new AsyncValidSync(params.sync, "source_valid")) sink_valid_0 .reset := (reset.asBool \|\| !sio.source_reset_n).asAsyncReset sink_valid_1 .reset := (reset.asBool \|\| !sio.source_reset_n).asAsyncReset source_extend.reset := (reset.asBool \|\| !sio.source_reset_n).asAsyncReset source_valid .reset := reset.asAsyncReset sink_valid_0 .clock := clock sink_valid_1 .clock := clock source_extend.clock := clock source_valid .clock := clock sink_valid_0.io.in := true.B sink_valid_1.io.in := sink_valid_0.io.out sio.ridx_valid := sink_valid_1.io.out source_extend.io.in := sio.widx_valid source_valid.io.in := source_extend.io.out source_ready := source_valid.io.out sio.sink_reset_n := !reset.asBool // TODO: write some sort of sanity check assertion for users // that denote don't reset when there is activity // // val reset_and_extend = !source_ready \|\| !sio.source_reset_n \|\| reset.asBool // val reset_and_extend_prev = RegNext(reset_and_extend, true.B) // val reset_rise = !reset_and_extend_prev && reset_and_extend // val prev_idx_match = AsyncResetReg(updateData=(io.async.widx===io.async.ridx), resetData=0) // assert (!reset_rise \|\| prev_idx_match.asBool, "Source reset while AsyncQueueSink not empty") } } object FromAsyncBundle { // Sometimes it makes sense for the sink to have different sync than the source def apply[T <: Data](x: AsyncBundle[T]): DecoupledIO[T] = apply(x, x.params.sync) def apply[T <: Data](x: AsyncBundle[T], sync: Int): DecoupledIO[T] = { val sink = Module(new AsyncQueueSink(chiselTypeOf(x.mem(0)), x.params.copy(sync = sync))) sink.io.async <> x sink.io.deq } } object ToAsyncBundle { def apply[T <: Data](x: ReadyValidIO[T], params: AsyncQueueParams = AsyncQueueParams()): AsyncBundle[T] = { val source = Module(new AsyncQueueSource(chiselTypeOf(x.bits), params)) source.io.enq <> x source.io.async } } class AsyncQueue[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Crossing[T] { val io = IO(new CrossingIO(gen)) val source = withClockAndReset(io.enq_clock, io.enq_reset) { Module(new AsyncQueueSource(gen, params)) } val sink = withClockAndReset(io.deq_clock, io.deq_reset) { Module(new AsyncQueueSink (gen, params)) } source.io.enq <> io.enq io.deq <> sink.io.deq sink.io.async <> source.io.async }	module AsyncValidSync_72( // @[AsyncQueue.scala:58:7] output io_out, // @[AsyncQueue.scala:59:14] input clock, // @[AsyncQueue.scala:63:17] input reset // @[AsyncQueue.scala:64:17] ); wire io_in = 1'h1; // @[ShiftReg.scala:45:23] wire _io_out_WIRE; // @[ShiftReg.scala:48:24] wire io_out_0; // @[AsyncQueue.scala:58:7] assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24] AsyncResetSynchronizerShiftReg_w1_d3_i0_83 io_out_source_valid_0 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (reset), .io_q (_io_out_WIRE) ); // @[ShiftReg.scala:45:23] assign io_out = io_out_0; // @[AsyncQueue.scala:58:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File Monitor.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceLine import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import freechips.rocketchip.diplomacy.EnableMonitors import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode} import freechips.rocketchip.util.PlusArg case class TLMonitorArgs(edge: TLEdge) abstract class TLMonitorBase(args: TLMonitorArgs) extends Module { val io = IO(new Bundle { val in = Input(new TLBundle(args.edge.bundle)) }) def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit legalize(io.in, args.edge, reset) } object TLMonitor { def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = { if (enable) { EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) } } else { node } } } class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args) { require (args.edge.params(TLMonitorStrictMode) \|\| (! args.edge.params(TestplanTestType).formal)) val cover_prop_class = PropertyClass.Default //Like assert but can flip to being an assumption for formal verification def monAssert(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir, cond, message, PropertyClass.Default) } def assume(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir.flip, cond, message, PropertyClass.Default) } def extra = { args.edge.sourceInfo match { case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)" case _ => "" } } def visible(address: UInt, source: UInt, edge: TLEdge) = edge.client.clients.map { c => !c.sourceId.contains(source) \|\| c.visibility.map(_.contains(address)).reduce(_ \|\| _) }.reduce(_ && _) def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = { //switch this flag to turn on diplomacy in error messages def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n" monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra) // Reuse these subexpressions to save some firrtl lines val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility") //The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B //TODO: check for acquireT? when (bundle.opcode === TLMessages.AcquireBlock) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra) } when (bundle.opcode === TLMessages.AcquirePerm) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra) monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra) monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra) monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra) } } def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = { monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra) monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility") // Reuse these subexpressions to save some firrtl lines val address_ok = edge.manager.containsSafe(edge.address(bundle)) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source when (bundle.opcode === TLMessages.Probe) { assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra) assume (address_ok, "'B' channel Probe carries unmanaged address" + extra) assume (legal_source, "'B' channel Probe carries source that is not first source" + extra) assume (is_aligned, "'B' channel Probe address not aligned to size" + extra) assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra) assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra) assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra) monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra) monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra) monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra) monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra) } } def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = { monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val address_ok = edge.manager.containsSafe(edge.address(bundle)) monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility") when (bundle.opcode === TLMessages.ProbeAck) { monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra) } when (bundle.opcode === TLMessages.ProbeAckData) { monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.Release) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra) monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra) } when (bundle.opcode === TLMessages.ReleaseData) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.AccessAck) { monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra) } when (bundle.opcode === TLMessages.HintAck) { monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra) } } def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = { assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val sink_ok = bundle.sink < edge.manager.endSinkId.U val deny_put_ok = edge.manager.mayDenyPut.B val deny_get_ok = edge.manager.mayDenyGet.B when (bundle.opcode === TLMessages.ReleaseAck) { assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra) assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra) assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra) } when (bundle.opcode === TLMessages.Grant) { assume (source_ok, "'D' channel Grant carries invalid source ID" + extra) assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra) assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel Grant is denied" + extra) } when (bundle.opcode === TLMessages.GrantData) { assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra) assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra) assume (!bundle.denied \|\| bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra) assume (deny_get_ok \|\| !bundle.denied, "'D' channel GrantData is denied" + extra) } when (bundle.opcode === TLMessages.AccessAck) { assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel AccessAck is denied" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra) assume (!bundle.denied \|\| bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra) assume (deny_get_ok \|\| !bundle.denied, "'D' channel AccessAckData is denied" + extra) } when (bundle.opcode === TLMessages.HintAck) { assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel HintAck is denied" + extra) } } def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = { val sink_ok = bundle.sink < edge.manager.endSinkId.U monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra) } def legalizeFormat(bundle: TLBundle, edge: TLEdge) = { when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) } when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) } when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) } when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) } } else { monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra) monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra) monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra) } } def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = { val a_first = edge.first(a.bits, a.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (a.valid && !a_first) { monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra) monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra) monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra) monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra) monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra) } when (a.fire && a_first) { opcode := a.bits.opcode param := a.bits.param size := a.bits.size source := a.bits.source address := a.bits.address } } def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = { val b_first = edge.first(b.bits, b.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (b.valid && !b_first) { monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra) monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra) monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra) monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra) monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra) } when (b.fire && b_first) { opcode := b.bits.opcode param := b.bits.param size := b.bits.size source := b.bits.source address := b.bits.address } } def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = { // Symbolic variable val sym_source = Wire(UInt(edge.client.endSourceId.W)) // TODO: Connect sym_source to a fixed value for simulation and to a // free wire in formal sym_source := 0.U // Type casting Int to UInt val maxSourceId = Wire(UInt(edge.client.endSourceId.W)) maxSourceId := edge.client.endSourceId.U // Delayed verison of sym_source val sym_source_d = Reg(UInt(edge.client.endSourceId.W)) sym_source_d := sym_source // These will be constraints for FV setup Property( MonitorDirection.Monitor, (sym_source === sym_source_d), "sym_source should remain stable", PropertyClass.Default) Property( MonitorDirection.Monitor, (sym_source <= maxSourceId), "sym_source should take legal value", PropertyClass.Default) val my_resp_pend = RegInit(false.B) val my_opcode = Reg(UInt()) val my_size = Reg(UInt()) val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire) val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire) val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source) val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source) val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat) val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend) when (my_set_resp_pend) { my_resp_pend := true.B } .elsewhen (my_clr_resp_pend) { my_resp_pend := false.B } when (my_a_first_beat) { my_opcode := bundle.a.bits.opcode my_size := bundle.a.bits.size } val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size) val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode) val my_resp_opcode_legal = Wire(Bool()) when ((my_resp_opcode === TLMessages.Get) \|\| (my_resp_opcode === TLMessages.ArithmeticData) \|\| (my_resp_opcode === TLMessages.LogicalData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData) } .elsewhen ((my_resp_opcode === TLMessages.PutFullData) \|\| (my_resp_opcode === TLMessages.PutPartialData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck) } .otherwise { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck) } monAssert (IfThen(my_resp_pend, !my_a_first_beat), "Request message should not be sent with a source ID, for which a response message" + "is already pending (not received until current cycle) for a prior request message" + "with the same source ID" + extra) assume (IfThen(my_clr_resp_pend, (my_set_resp_pend \|\| my_resp_pend)), "Response message should be accepted with a source ID only if a request message with the" + "same source ID has been accepted or is being accepted in the current cycle" + extra) assume (IfThen(my_d_first_beat, (my_a_first_beat \|\| my_resp_pend)), "Response message should be sent with a source ID only if a request message with the" + "same source ID has been accepted or is being sent in the current cycle" + extra) assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)), "If d_valid is 1, then d_size should be same as a_size of the corresponding request" + "message" + extra) assume (IfThen(my_d_first_beat, my_resp_opcode_legal), "If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" + "request message" + extra) } def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = { val c_first = edge.first(c.bits, c.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (c.valid && !c_first) { monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra) monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra) monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra) monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra) monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra) } when (c.fire && c_first) { opcode := c.bits.opcode param := c.bits.param size := c.bits.size source := c.bits.source address := c.bits.address } } def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = { val d_first = edge.first(d.bits, d.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val sink = Reg(UInt()) val denied = Reg(Bool()) when (d.valid && !d_first) { assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra) assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra) assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra) assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra) assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra) assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra) } when (d.fire && d_first) { opcode := d.bits.opcode param := d.bits.param size := d.bits.size source := d.bits.source sink := d.bits.sink denied := d.bits.denied } } def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = { legalizeMultibeatA(bundle.a, edge) legalizeMultibeatD(bundle.d, edge) if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { legalizeMultibeatB(bundle.b, edge) legalizeMultibeatC(bundle.c, edge) } } //This is left in for almond which doesn't adhere to the tilelink protocol @deprecated("Use legalizeADSource instead if possible","") def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.client.endSourceId.W)) val a_first = edge.first(bundle.a.bits, bundle.a.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val a_set = WireInit(0.U(edge.client.endSourceId.W)) when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) assume((a_set \| inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra) } if (edge.manager.minLatency > 0) { assume(a_set =/= d_clr \|\| !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight \| a_set) & ~d_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") assert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = { val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size) val log_a_size_bus_size = log2Ceil(a_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error inflight.suggestName("inflight") val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) inflight_opcodes.suggestName("inflight_opcodes") val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) inflight_sizes.suggestName("inflight_sizes") val a_first = edge.first(bundle.a.bits, bundle.a.fire) a_first.suggestName("a_first") val d_first = edge.first(bundle.d.bits, bundle.d.fire) d_first.suggestName("d_first") val a_set = WireInit(0.U(edge.client.endSourceId.W)) val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) a_set.suggestName("a_set") a_set_wo_ready.suggestName("a_set_wo_ready") val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) a_opcodes_set.suggestName("a_opcodes_set") val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) a_sizes_set.suggestName("a_sizes_set") val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W)) a_opcode_lookup.suggestName("a_opcode_lookup") a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W)) a_size_lookup.suggestName("a_size_lookup") a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant)) val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant)) val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W)) a_opcodes_set_interm.suggestName("a_opcodes_set_interm") val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W)) a_sizes_set_interm.suggestName("a_sizes_set_interm") when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) { a_set_wo_ready := UIntToOH(bundle.a.bits.source) } when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) \| 1.U a_sizes_set_interm := (bundle.a.bits.size << 1.U) \| 1.U a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U) a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U) monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) d_opcodes_clr.suggestName("d_opcodes_clr") val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) \|\| same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) \|\| (bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra) assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) \|\| (bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra) assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) { assume((!bundle.d.ready) \|\| bundle.a.ready, "ready check") } if (edge.manager.minLatency > 0) { assume(a_set_wo_ready =/= d_clr_wo_ready \|\| !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight \| a_set) & ~d_clr inflight_opcodes := (inflight_opcodes \| a_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes \| a_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = { val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size) val log_c_size_bus_size = log2Ceil(c_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) inflight.suggestName("inflight") inflight_opcodes.suggestName("inflight_opcodes") inflight_sizes.suggestName("inflight_sizes") val c_first = edge.first(bundle.c.bits, bundle.c.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) c_first.suggestName("c_first") d_first.suggestName("d_first") val c_set = WireInit(0.U(edge.client.endSourceId.W)) val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) c_set.suggestName("c_set") c_set_wo_ready.suggestName("c_set_wo_ready") c_opcodes_set.suggestName("c_opcodes_set") c_sizes_set.suggestName("c_sizes_set") val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W)) val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W)) c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U c_opcode_lookup.suggestName("c_opcode_lookup") c_size_lookup.suggestName("c_size_lookup") val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W)) val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W)) c_opcodes_set_interm.suggestName("c_opcodes_set_interm") c_sizes_set_interm.suggestName("c_sizes_set_interm") when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) { c_set_wo_ready := UIntToOH(bundle.c.bits.source) } when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) { c_set := UIntToOH(bundle.c.bits.source) c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) \| 1.U c_sizes_set_interm := (bundle.c.bits.size << 1.U) \| 1.U c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U) c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U) monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra) } val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck \|\| bundle.c.bits.opcode === TLMessages.ProbeAckData val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") d_opcodes_clr.suggestName("d_opcodes_clr") d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) \|\| same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) { assume((!bundle.d.ready) \|\| bundle.c.ready, "ready check") } if (edge.manager.minLatency > 0) { when (c_set_wo_ready.orR) { assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra) } } inflight := (inflight \| c_set) & ~d_clr inflight_opcodes := (inflight_opcodes \| c_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes \| c_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.c.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.manager.endSinkId.W)) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val e_first = true.B val d_set = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) { d_set := UIntToOH(bundle.d.bits.sink) assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra) } val e_clr = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) { e_clr := UIntToOH(bundle.e.bits.sink) monAssert((d_set \| inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra) } // edge.client.minLatency applies to BC, not DE inflight := (inflight \| d_set) & ~e_clr } def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = { val sourceBits = log2Ceil(edge.client.endSourceId) val tooBig = 14 // >16kB worth of flight information gets to be too much if (sourceBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked") } else { if (args.edge.params(TestplanTestType).simulation) { if (args.edge.params(TLMonitorStrictMode)) { legalizeADSource(bundle, edge) legalizeCDSource(bundle, edge) } else { legalizeADSourceOld(bundle, edge) } } if (args.edge.params(TestplanTestType).formal) { legalizeADSourceFormal(bundle, edge) } } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { // legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize... val sinkBits = log2Ceil(edge.manager.endSinkId) if (sinkBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked") } else { legalizeDESink(bundle, edge) } } } def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = { legalizeFormat (bundle, edge) legalizeMultibeat (bundle, edge) legalizeUnique (bundle, edge) } } File Misc.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import scala.math._ class ParameterizedBundle(implicit p: Parameters) extends Bundle trait Clocked extends Bundle { val clock = Clock() val reset = Bool() } object DecoupledHelper { def apply(rvs: Bool) = new DecoupledHelper(rvs) } class DecoupledHelper(val rvs: Seq[Bool]) { def fire(exclude: Bool, includes: Bool) = { require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!") (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _) } def fire() = { rvs.reduce(_ && _) } } object MuxT { def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2)) def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3)) def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4)) } /** Creates a cascade of n MuxTs to search for a key value. / object MuxTLookup { def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } } object ValidMux { def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]): ValidIO[T] = { apply(v1 +: v2.toSeq) } def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = { val out = Wire(Valid(valids.head.bits.cloneType)) out.valid := valids.map(_.valid).reduce(_ \|\| _) out.bits := MuxCase(valids.head.bits, valids.map(v => (v.valid -> v.bits))) out } } object Str { def apply(s: String): UInt = { var i = BigInt(0) require(s.forall(validChar _)) for (c <- s) i = (i << 8) \| c i.U((s.length8).W) } def apply(x: Char): UInt = { require(validChar(x)) x.U(8.W) } def apply(x: UInt): UInt = apply(x, 10) def apply(x: UInt, radix: Int): UInt = { val rad = radix.U val w = x.getWidth require(w > 0) var q = x var s = digit(q % rad) for (i <- 1 until ceil(log(2)/log(radix)w).toInt) { q = q / rad s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s) } s } def apply(x: SInt): UInt = apply(x, 10) def apply(x: SInt, radix: Int): UInt = { val neg = x < 0.S val abs = x.abs.asUInt if (radix != 10) { Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix)) } else { val rad = radix.U val w = abs.getWidth require(w > 0) var q = abs var s = digit(q % rad) var needSign = neg for (i <- 1 until ceil(log(2)/log(radix)w).toInt) { q = q / rad val placeSpace = q === 0.U val space = Mux(needSign, Str('-'), Str(' ')) needSign = needSign && !placeSpace s = Cat(Mux(placeSpace, space, digit(q % rad)), s) } Cat(Mux(needSign, Str('-'), Str(' ')), s) } } private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0) private def validChar(x: Char) = x == (x & 0xFF) } object Split { def apply(x: UInt, n0: Int) = { val w = x.getWidth (x.extract(w-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n2: Int, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } } object Random { def apply(mod: Int, random: UInt): UInt = { if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0) else PriorityEncoder(partition(apply(1 << log2Up(mod8), random), mod)) } def apply(mod: Int): UInt = apply(mod, randomizer) def oneHot(mod: Int, random: UInt): UInt = { if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0)) else PriorityEncoderOH(partition(apply(1 << log2Up(mod8), random), mod)).asUInt } def oneHot(mod: Int): UInt = oneHot(mod, randomizer) private def randomizer = LFSR(16) private def partition(value: UInt, slices: Int) = Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U) } object Majority { def apply(in: Set[Bool]): Bool = { val n = (in.size >> 1) + 1 val clauses = in.subsets(n).map(_.reduce(_ && _)) clauses.reduce(_ \|\| _) } def apply(in: Seq[Bool]): Bool = apply(in.toSet) def apply(in: UInt): Bool = apply(in.asBools.toSet) } object PopCountAtLeast { private def two(x: UInt): (Bool, Bool) = x.getWidth match { case 1 => (x.asBool, false.B) case n => val half = x.getWidth / 2 val (leftOne, leftTwo) = two(x(half - 1, 0)) val (rightOne, rightTwo) = two(x(x.getWidth - 1, half)) (leftOne \|\| rightOne, leftTwo \|\| rightTwo \|\| (leftOne && rightOne)) } def apply(x: UInt, n: Int): Bool = n match { case 0 => true.B case 1 => x.orR case 2 => two(x)._2 case 3 => PopCount(x) >= n.U } } // This gets used everywhere, so make the smallest circuit possible ... // Given an address and size, create a mask of beatBytes size // eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111 // groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01 object MaskGen { def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = { require (groupBy >= 1 && beatBytes >= groupBy) require (isPow2(beatBytes) && isPow2(groupBy)) val lgBytes = log2Ceil(beatBytes) val sizeOH = UIntToOH(lgSize \| 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) \| (groupBy2 - 1).U def helper(i: Int): Seq[(Bool, Bool)] = { if (i == 0) { Seq((lgSize >= lgBytes.asUInt, true.B)) } else { val sub = helper(i-1) val size = sizeOH(lgBytes - i) val bit = addr_lo(lgBytes - i) val nbit = !bit Seq.tabulate (1 << i) { j => val (sub_acc, sub_eq) = sub(j/2) val eq = sub_eq && (if (j % 2 == 1) bit else nbit) val acc = sub_acc \|\| (size && eq) (acc, eq) } } } if (groupBy == beatBytes) 1.U else Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse) } } File PlusArg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.experimental._ import chisel3.util.HasBlackBoxResource @deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05") case class PlusArgInfo(default: BigInt, docstring: String) /** Case class for PlusArg information * * @tparam A scala type of the PlusArg value * @param default optional default value * @param docstring text to include in the help * @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT) / private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String) /* Typeclass for converting a type to a doctype string * @tparam A some type / trait Doctypeable[A] { /* Return the doctype string for some option / def toDoctype(a: Option[A]): String } /* Object containing implementations of the Doctypeable typeclass / object Doctypes { /* Converts an Int => "INT" / implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" } /* Converts a BigInt => "INT" / implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" } /* Converts a String => "STRING" / implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" } } class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map( "FORMAT" -> StringParam(format), "DEFAULT" -> IntParam(default), "WIDTH" -> IntParam(width) )) with HasBlackBoxResource { val io = IO(new Bundle { val out = Output(UInt(width.W)) }) addResource("/vsrc/plusarg_reader.v") } / This wrapper class has no outputs, making it clear it is a simulation-only construct / class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module { val io = IO(new Bundle { val count = Input(UInt(width.W)) }) val max = Module(new plusarg_reader(format, default, docstring, width)).io.out when (max > 0.U) { assert (io.count < max, s"Timeout exceeded: $docstring") } } import Doctypes._ object PlusArg { /* PlusArg("foo") will return 42.U if the simulation is run with +foo=42 * Do not use this as an initial register value. The value is set in an * initial block and thus accessing it from another initial is racey. * Add a docstring to document the arg, which can be dumped in an elaboration * pass. / def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out } /* PlusArg.timeout(name, default, docstring)(count) will use chisel.assert * to kill the simulation when count exceeds the specified integer argument. * Default 0 will never assert. / def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count } } object PlusArgArtefacts { private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty / Add a new PlusArg / @deprecated( "Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05" ) def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring) /* Add a new PlusArg * * @tparam A scala type of the PlusArg value * @param name name for the PlusArg * @param default optional default value * @param docstring text to include in the help / def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit = artefacts = artefacts ++ Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default))) / From plus args, generate help text / private def serializeHelp_cHeader(tab: String = ""): String = artefacts .map{ case(arg, info) => s"""\|$tab+$arg=${info.doctype}\\n\\ \|$tab${" "20}${info.docstring}\\n\\ \|""".stripMargin ++ info.default.map{ case default => s"$tab${" "22}(default=${default})\\n\\\n"}.getOrElse("") }.toSeq.mkString("\\n\\\n") ++ "\"" / From plus args, generate a char array of their names / private def serializeArray_cHeader(tab: String = ""): String = { val prettyTab = tab + " " 44 // Length of 'static const ...' s"${tab}static const char * verilog_plusargs [] = {\\\n" ++ artefacts .map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" } .mkString("")++ s"${prettyTab}0};" } /* Generate C code to be included in emulator.cc that helps with * argument parsing based on available Verilog PlusArgs / def serialize_cHeader(): String = s"""\|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\ \|${serializeHelp_cHeader(" "7)} \|${serializeArray_cHeader()} \|""".stripMargin } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /* Like Vec.apply(idx), but tolerates indices of mismatched width / def extract(idx: UInt): T = x((idx \| 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx \| 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def \| (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a \|\| b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_\|\|_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /* Any Data subtype that has a Bool member named valid. / type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /* converts from camel case to to underscores, also removing all spaces / def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /* converts spaces or underscores to hyphens, also lowering case / def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y \| (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y \|\| y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 \| 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /* Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation / def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.diplomacy import chisel3._ import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor} import freechips.rocketchip.util.ShiftQueue /* Options for describing the attributes of memory regions / object RegionType { // Define the 'more relaxed than' ordering val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS) sealed trait T extends Ordered[T] { def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this) } case object CACHED extends T // an intermediate agent may have cached a copy of the region for you case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively } // A non-empty half-open range; [start, end) case class IdRange(start: Int, end: Int) extends Ordered[IdRange] { require (start >= 0, s"Ids cannot be negative, but got: $start.") require (start <= end, "Id ranges cannot be negative.") def compare(x: IdRange) = { val primary = (this.start - x.start).signum val secondary = (x.end - this.end).signum if (primary != 0) primary else secondary } def overlaps(x: IdRange) = start < x.end && x.start < end def contains(x: IdRange) = start <= x.start && x.end <= end def contains(x: Int) = start <= x && x < end def contains(x: UInt) = if (size == 0) { false.B } else if (size == 1) { // simple comparison x === start.U } else { // find index of largest different bit val largestDeltaBit = log2Floor(start ^ (end-1)) val smallestCommonBit = largestDeltaBit + 1 // may not exist in x val uncommonMask = (1 << smallestCommonBit) - 1 val uncommonBits = (x \| 0.U(smallestCommonBit.W))(largestDeltaBit, 0) // the prefix must match exactly (note: may shift ALL bits away) (x >> smallestCommonBit) === (start >> smallestCommonBit).U && // firrtl constant prop range analysis can eliminate these two: (start & uncommonMask).U <= uncommonBits && uncommonBits <= ((end-1) & uncommonMask).U } def shift(x: Int) = IdRange(start+x, end+x) def size = end - start def isEmpty = end == start def range = start until end } object IdRange { def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else { val ranges = s.sorted (ranges.tail zip ranges.init) find { case (a, b) => a overlaps b } } } // An potentially empty inclusive range of 2-powers [min, max] (in bytes) case class TransferSizes(min: Int, max: Int) { def this(x: Int) = this(x, x) require (min <= max, s"Min transfer $min > max transfer $max") require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)") require (max == 0 \|\| isPow2(max), s"TransferSizes must be a power of 2, got: $max") require (min == 0 \|\| isPow2(min), s"TransferSizes must be a power of 2, got: $min") require (max == 0 \|\| min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)") def none = min == 0 def contains(x: Int) = isPow2(x) && min <= x && x <= max def containsLg(x: Int) = contains(1 << x) def containsLg(x: UInt) = if (none) false.B else if (min == max) { log2Ceil(min).U === x } else { log2Ceil(min).U <= x && x <= log2Ceil(max).U } def contains(x: TransferSizes) = x.none \|\| (min <= x.min && x.max <= max) def intersect(x: TransferSizes) = if (x.max < min \|\| max < x.min) TransferSizes.none else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max)) // Not a union, because the result may contain sizes contained by neither term // NOT TO BE CONFUSED WITH COVERPOINTS def mincover(x: TransferSizes) = { if (none) { x } else if (x.none) { this } else { TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max)) } } override def toString() = "TransferSizes[%d, %d]".format(min, max) } object TransferSizes { def apply(x: Int) = new TransferSizes(x) val none = new TransferSizes(0) def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _) def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _) implicit def asBool(x: TransferSizes) = !x.none } // AddressSets specify the address space managed by the manager // Base is the base address, and mask are the bits consumed by the manager // e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff // e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ... case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet] { // Forbid misaligned base address (and empty sets) require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}") require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous // We do allow negative mask (=> ignore all high bits) def contains(x: BigInt) = ((x ^ base) & ~mask) == 0 def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S // turn x into an address contained in this set def legalize(x: UInt): UInt = base.U \| (mask.U & x) // overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1) def overlaps(x: AddressSet) = (~(mask \| x.mask) & (base ^ x.base)) == 0 // contains iff bitwise: x.mask => mask && contains(x.base) def contains(x: AddressSet) = ((x.mask \| (base ^ x.base)) & ~mask) == 0 // The number of bytes to which the manager must be aligned def alignment = ((mask + 1) & ~mask) // Is this a contiguous memory range def contiguous = alignment == mask+1 def finite = mask >= 0 def max = { require (finite, "Max cannot be calculated on infinite mask"); base \| mask } // Widen the match function to ignore all bits in imask def widen(imask: BigInt) = AddressSet(base & ~imask, mask \| imask) // Return an AddressSet that only contains the addresses both sets contain def intersect(x: AddressSet): Option[AddressSet] = { if (!overlaps(x)) { None } else { val r_mask = mask & x.mask val r_base = base \| x.base Some(AddressSet(r_base, r_mask)) } } def subtract(x: AddressSet): Seq[AddressSet] = { intersect(x) match { case None => Seq(this) case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit => val nmask = (mask & (bit-1)) \| remove.mask val nbase = (remove.base ^ bit) & ~nmask AddressSet(nbase, nmask) } } } // AddressSets have one natural Ordering (the containment order, if contiguous) def compare(x: AddressSet) = { val primary = (this.base - x.base).signum // smallest address first val secondary = (x.mask - this.mask).signum // largest mask first if (primary != 0) primary else secondary } // We always want to see things in hex override def toString() = { if (mask >= 0) { "AddressSet(0x%x, 0x%x)".format(base, mask) } else { "AddressSet(0x%x, ~0x%x)".format(base, ~mask) } } def toRanges = { require (finite, "Ranges cannot be calculated on infinite mask") val size = alignment val fragments = mask & ~(size-1) val bits = bitIndexes(fragments) (BigInt(0) until (BigInt(1) << bits.size)).map { i => val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) } AddressRange(off, size) } } } object AddressSet { val everything = AddressSet(0, -1) def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = { if (size == 0) tail.reverse else { val maxBaseAlignment = base & (-base) // 0 for infinite (LSB) val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size val step = if (maxBaseAlignment == 0 \|\| maxBaseAlignment > maxSizeAlignment) maxSizeAlignment else maxBaseAlignment misaligned(base+step, size-step, AddressSet(base, step-1) +: tail) } } def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = { // Pair terms up by ignoring 'bit' seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) => if (seq.size == 1) { seq.head // singleton -> unaffected } else { key.copy(mask = key.mask \| bit) // pair - widen mask by bit } }.toList } def unify(seq: Seq[AddressSet]): Seq[AddressSet] = { val bits = seq.map(_.base).foldLeft(BigInt(0))(_ \| _) AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted } def enumerateMask(mask: BigInt): Seq[BigInt] = { def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] = if (id == mask) (id +: tail).reverse else helper(((~mask \| id) + 1) & mask, id +: tail) helper(0, Nil) } def enumerateBits(mask: BigInt): Seq[BigInt] = { def helper(x: BigInt): Seq[BigInt] = { if (x == 0) { Nil } else { val bit = x & (-x) bit +: helper(x & ~bit) } } helper(mask) } } case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean) { require (depth >= 0, "Buffer depth must be >= 0") def isDefined = depth > 0 def latency = if (isDefined && !flow) 1 else 0 def apply[T <: Data](x: DecoupledIO[T]) = if (isDefined) Queue(x, depth, flow=flow, pipe=pipe) else x def irrevocable[T <: Data](x: ReadyValidIO[T]) = if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe) else x def sq[T <: Data](x: DecoupledIO[T]) = if (!isDefined) x else { val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe)) sq.io.enq <> x sq.io.deq } override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "") } object BufferParams { implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false) val default = BufferParams(2) val none = BufferParams(0) val flow = BufferParams(1, true, false) val pipe = BufferParams(1, false, true) } case class TriStateValue(value: Boolean, set: Boolean) { def update(orig: Boolean) = if (set) value else orig } object TriStateValue { implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true) def unset = TriStateValue(false, false) } trait DirectedBuffers[T] { def copyIn(x: BufferParams): T def copyOut(x: BufferParams): T def copyInOut(x: BufferParams): T } trait IdMapEntry { def name: String def from: IdRange def to: IdRange def isCache: Boolean def requestFifo: Boolean def maxTransactionsInFlight: Option[Int] def pretty(fmt: String) = if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5 fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } else { fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } } abstract class IdMap[T <: IdMapEntry] { protected val fmt: String val mapping: Seq[T] def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n") } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportPutFull \|\| manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB \|\| manager.anySupportGet \|\| manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportPutFull \|\| client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe \|\| client.anySupportGet \|\| client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet \|\| client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull \|\| client.anySupportPutPartial \|\| client.anySupportHint \|\| client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet \|\| manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull \|\| manager.anySupportPutPartial \|\| manager.anySupportHint \|\| manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) \|\| !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.ProbeAckData \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode \| small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U \|\| beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }	module TLMonitor_25( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [11:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [7:0] io_in_d_bits_source // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire [12:0] _GEN = {10'h0, io_in_a_bits_size}; // @[package.scala:243:71] wire _a_first_T_1 = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala:51:35] reg [2:0] a_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [2:0] size; // @[Monitor.scala:389:22] reg [7:0] source; // @[Monitor.scala:390:22] reg [11:0] address; // @[Monitor.scala:391:22] reg [2:0] d_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [2:0] size_1; // @[Monitor.scala:540:22] reg [7:0] source_1; // @[Monitor.scala:541:22] reg [128:0] inflight; // @[Monitor.scala:614:27] reg [515:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [515:0] inflight_sizes; // @[Monitor.scala:618:33] reg [2:0] a_first_counter_1; // @[Edges.scala:229:27] wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] reg [2:0] d_first_counter_1; // @[Edges.scala:229:27] wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _GEN_0 = _a_first_T_1 & a_first_1; // @[Decoupled.scala:51:35] wire d_release_ack = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala:673:46] wire _GEN_1 = io_in_d_bits_opcode != 3'h6; // @[Monitor.scala:673:46, :674:74] reg [31:0] watchdog; // @[Monitor.scala:709:27] reg [128:0] inflight_1; // @[Monitor.scala:726:35] reg [515:0] inflight_sizes_1; // @[Monitor.scala:728:35] reg [2:0] d_first_counter_2; // @[Edges.scala:229:27] wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to the following Chisel files. File Nodes.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.nodes._ import freechips.rocketchip.util.{AsyncQueueParams,RationalDirection} case object TLMonitorBuilder extends Field[TLMonitorArgs => TLMonitorBase](args => new TLMonitor(args)) object TLImp extends NodeImp[TLMasterPortParameters, TLSlavePortParameters, TLEdgeOut, TLEdgeIn, TLBundle] { def edgeO(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeOut(pd, pu, p, sourceInfo) def edgeI(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeIn (pd, pu, p, sourceInfo) def bundleO(eo: TLEdgeOut) = TLBundle(eo.bundle) def bundleI(ei: TLEdgeIn) = TLBundle(ei.bundle) def render(ei: TLEdgeIn) = RenderedEdge(colour = "#000000" /* black /, label = (ei.manager.beatBytes 8).toString) override def monitor(bundle: TLBundle, edge: TLEdgeIn): Unit = { val monitor = Module(edge.params(TLMonitorBuilder)(TLMonitorArgs(edge))) monitor.io.in := bundle } override def mixO(pd: TLMasterPortParameters, node: OutwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLMasterPortParameters = pd.v1copy(clients = pd.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }) override def mixI(pu: TLSlavePortParameters, node: InwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLSlavePortParameters = pu.v1copy(managers = pu.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }) } trait TLFormatNode extends FormatNode[TLEdgeIn, TLEdgeOut] case class TLClientNode(portParams: Seq[TLMasterPortParameters])(implicit valName: ValName) extends SourceNode(TLImp)(portParams) with TLFormatNode case class TLManagerNode(portParams: Seq[TLSlavePortParameters])(implicit valName: ValName) extends SinkNode(TLImp)(portParams) with TLFormatNode case class TLAdapterNode( clientFn: TLMasterPortParameters => TLMasterPortParameters = { s => s }, managerFn: TLSlavePortParameters => TLSlavePortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLImp)(clientFn, managerFn) with TLFormatNode case class TLJunctionNode( clientFn: Seq[TLMasterPortParameters] => Seq[TLMasterPortParameters], managerFn: Seq[TLSlavePortParameters] => Seq[TLSlavePortParameters])( implicit valName: ValName) extends JunctionNode(TLImp)(clientFn, managerFn) with TLFormatNode case class TLIdentityNode()(implicit valName: ValName) extends IdentityNode(TLImp)() with TLFormatNode object TLNameNode { def apply(name: ValName) = TLIdentityNode()(name) def apply(name: Option[String]): TLIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLIdentityNode = apply(Some(name)) } case class TLEphemeralNode()(implicit valName: ValName) extends EphemeralNode(TLImp)() object TLTempNode { def apply(): TLEphemeralNode = TLEphemeralNode()(ValName("temp")) } case class TLNexusNode( clientFn: Seq[TLMasterPortParameters] => TLMasterPortParameters, managerFn: Seq[TLSlavePortParameters] => TLSlavePortParameters)( implicit valName: ValName) extends NexusNode(TLImp)(clientFn, managerFn) with TLFormatNode abstract class TLCustomNode(implicit valName: ValName) extends CustomNode(TLImp) with TLFormatNode // Asynchronous crossings trait TLAsyncFormatNode extends FormatNode[TLAsyncEdgeParameters, TLAsyncEdgeParameters] object TLAsyncImp extends SimpleNodeImp[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncEdgeParameters, TLAsyncBundle] { def edge(pd: TLAsyncClientPortParameters, pu: TLAsyncManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLAsyncEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLAsyncEdgeParameters) = new TLAsyncBundle(e.bundle) def render(e: TLAsyncEdgeParameters) = RenderedEdge(colour = "#ff0000" /* red /, label = e.manager.async.depth.toString) override def mixO(pd: TLAsyncClientPortParameters, node: OutwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLAsyncManagerPortParameters, node: InwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLAsyncAdapterNode( clientFn: TLAsyncClientPortParameters => TLAsyncClientPortParameters = { s => s }, managerFn: TLAsyncManagerPortParameters => TLAsyncManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLAsyncImp)(clientFn, managerFn) with TLAsyncFormatNode case class TLAsyncIdentityNode()(implicit valName: ValName) extends IdentityNode(TLAsyncImp)() with TLAsyncFormatNode object TLAsyncNameNode { def apply(name: ValName) = TLAsyncIdentityNode()(name) def apply(name: Option[String]): TLAsyncIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLAsyncIdentityNode = apply(Some(name)) } case class TLAsyncSourceNode(sync: Option[Int])(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLAsyncImp)( dFn = { p => TLAsyncClientPortParameters(p) }, uFn = { p => p.base.v1copy(minLatency = p.base.minLatency + sync.getOrElse(p.async.sync)) }) with FormatNode[TLEdgeIn, TLAsyncEdgeParameters] // discard cycles in other clock domain case class TLAsyncSinkNode(async: AsyncQueueParams)(implicit valName: ValName) extends MixedAdapterNode(TLAsyncImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = p.base.minLatency + async.sync) }, uFn = { p => TLAsyncManagerPortParameters(async, p) }) with FormatNode[TLAsyncEdgeParameters, TLEdgeOut] // Rationally related crossings trait TLRationalFormatNode extends FormatNode[TLRationalEdgeParameters, TLRationalEdgeParameters] object TLRationalImp extends SimpleNodeImp[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalEdgeParameters, TLRationalBundle] { def edge(pd: TLRationalClientPortParameters, pu: TLRationalManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLRationalEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLRationalEdgeParameters) = new TLRationalBundle(e.bundle) def render(e: TLRationalEdgeParameters) = RenderedEdge(colour = "#00ff00" / green /) override def mixO(pd: TLRationalClientPortParameters, node: OutwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLRationalManagerPortParameters, node: InwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLRationalAdapterNode( clientFn: TLRationalClientPortParameters => TLRationalClientPortParameters = { s => s }, managerFn: TLRationalManagerPortParameters => TLRationalManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLRationalImp)(clientFn, managerFn) with TLRationalFormatNode case class TLRationalIdentityNode()(implicit valName: ValName) extends IdentityNode(TLRationalImp)() with TLRationalFormatNode object TLRationalNameNode { def apply(name: ValName) = TLRationalIdentityNode()(name) def apply(name: Option[String]): TLRationalIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLRationalIdentityNode = apply(Some(name)) } case class TLRationalSourceNode()(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLRationalImp)( dFn = { p => TLRationalClientPortParameters(p) }, uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLRationalEdgeParameters] // discard cycles from other clock domain case class TLRationalSinkNode(direction: RationalDirection)(implicit valName: ValName) extends MixedAdapterNode(TLRationalImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = 1) }, uFn = { p => TLRationalManagerPortParameters(direction, p) }) with FormatNode[TLRationalEdgeParameters, TLEdgeOut] // Credited version of TileLink channels trait TLCreditedFormatNode extends FormatNode[TLCreditedEdgeParameters, TLCreditedEdgeParameters] object TLCreditedImp extends SimpleNodeImp[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedEdgeParameters, TLCreditedBundle] { def edge(pd: TLCreditedClientPortParameters, pu: TLCreditedManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLCreditedEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLCreditedEdgeParameters) = new TLCreditedBundle(e.bundle) def render(e: TLCreditedEdgeParameters) = RenderedEdge(colour = "#ffff00" / yellow /, e.delay.toString) override def mixO(pd: TLCreditedClientPortParameters, node: OutwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLCreditedManagerPortParameters, node: InwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLCreditedAdapterNode( clientFn: TLCreditedClientPortParameters => TLCreditedClientPortParameters = { s => s }, managerFn: TLCreditedManagerPortParameters => TLCreditedManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLCreditedImp)(clientFn, managerFn) with TLCreditedFormatNode case class TLCreditedIdentityNode()(implicit valName: ValName) extends IdentityNode(TLCreditedImp)() with TLCreditedFormatNode object TLCreditedNameNode { def apply(name: ValName) = TLCreditedIdentityNode()(name) def apply(name: Option[String]): TLCreditedIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLCreditedIdentityNode = apply(Some(name)) } case class TLCreditedSourceNode(delay: TLCreditedDelay)(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLCreditedImp)( dFn = { p => TLCreditedClientPortParameters(delay, p) }, uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLCreditedEdgeParameters] // discard cycles from other clock domain case class TLCreditedSinkNode(delay: TLCreditedDelay)(implicit valName: ValName) extends MixedAdapterNode(TLCreditedImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = 1) }, uFn = { p => TLCreditedManagerPortParameters(delay, p) }) with FormatNode[TLCreditedEdgeParameters, TLEdgeOut] File AsyncQueue.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ case class AsyncQueueParams( depth: Int = 8, sync: Int = 3, safe: Boolean = true, // If safe is true, then effort is made to resynchronize the crossing indices when either side is reset. // This makes it safe/possible to reset one side of the crossing (but not the other) when the queue is empty. narrow: Boolean = false) // If narrow is true then the read mux is moved to the source side of the crossing. // This reduces the number of level shifters in the case where the clock crossing is also a voltage crossing, // at the expense of a combinational path from the sink to the source and back to the sink. { require (depth > 0 && isPow2(depth)) require (sync >= 2) val bits = log2Ceil(depth) val wires = if (narrow) 1 else depth } object AsyncQueueParams { // When there is only one entry, we don't need narrow. def singleton(sync: Int = 3, safe: Boolean = true) = AsyncQueueParams(1, sync, safe, false) } class AsyncBundleSafety extends Bundle { val ridx_valid = Input (Bool()) val widx_valid = Output(Bool()) val source_reset_n = Output(Bool()) val sink_reset_n = Input (Bool()) } class AsyncBundle[T <: Data](private val gen: T, val params: AsyncQueueParams = AsyncQueueParams()) extends Bundle { // Data-path synchronization val mem = Output(Vec(params.wires, gen)) val ridx = Input (UInt((params.bits+1).W)) val widx = Output(UInt((params.bits+1).W)) val index = params.narrow.option(Input(UInt(params.bits.W))) // Signals used to self-stabilize a safe AsyncQueue val safe = params.safe.option(new AsyncBundleSafety) } object GrayCounter { def apply(bits: Int, increment: Bool = true.B, clear: Bool = false.B, name: String = "binary"): UInt = { val incremented = Wire(UInt(bits.W)) val binary = RegNext(next=incremented, init=0.U).suggestName(name) incremented := Mux(clear, 0.U, binary + increment.asUInt) incremented ^ (incremented >> 1) } } class AsyncValidSync(sync: Int, desc: String) extends RawModule { val io = IO(new Bundle { val in = Input(Bool()) val out = Output(Bool()) }) val clock = IO(Input(Clock())) val reset = IO(Input(AsyncReset())) withClockAndReset(clock, reset){ io.out := AsyncResetSynchronizerShiftReg(io.in, sync, Some(desc)) } } class AsyncQueueSource[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module { override def desiredName = s"AsyncQueueSource_${gen.typeName}" val io = IO(new Bundle { // These come from the source domain val enq = Flipped(Decoupled(gen)) // These cross to the sink clock domain val async = new AsyncBundle(gen, params) }) val bits = params.bits val sink_ready = WireInit(true.B) val mem = Reg(Vec(params.depth, gen)) // This does NOT need to be reset at all. val widx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.enq.fire, !sink_ready, "widx_bin")) val ridx = AsyncResetSynchronizerShiftReg(io.async.ridx, params.sync, Some("ridx_gray")) val ready = sink_ready && widx =/= (ridx ^ (params.depth \| params.depth >> 1).U) val index = if (bits == 0) 0.U else io.async.widx(bits-1, 0) ^ (io.async.widx(bits, bits) << (bits-1)) when (io.enq.fire) { mem(index) := io.enq.bits } val ready_reg = withReset(reset.asAsyncReset)(RegNext(next=ready, init=false.B).suggestName("ready_reg")) io.enq.ready := ready_reg && sink_ready val widx_reg = withReset(reset.asAsyncReset)(RegNext(next=widx, init=0.U).suggestName("widx_gray")) io.async.widx := widx_reg io.async.index match { case Some(index) => io.async.mem(0) := mem(index) case None => io.async.mem := mem } io.async.safe.foreach { sio => val source_valid_0 = Module(new AsyncValidSync(params.sync, "source_valid_0")) val source_valid_1 = Module(new AsyncValidSync(params.sync, "source_valid_1")) val sink_extend = Module(new AsyncValidSync(params.sync, "sink_extend")) val sink_valid = Module(new AsyncValidSync(params.sync, "sink_valid")) source_valid_0.reset := (reset.asBool \|\| !sio.sink_reset_n).asAsyncReset source_valid_1.reset := (reset.asBool \|\| !sio.sink_reset_n).asAsyncReset sink_extend .reset := (reset.asBool \|\| !sio.sink_reset_n).asAsyncReset sink_valid .reset := reset.asAsyncReset source_valid_0.clock := clock source_valid_1.clock := clock sink_extend .clock := clock sink_valid .clock := clock source_valid_0.io.in := true.B source_valid_1.io.in := source_valid_0.io.out sio.widx_valid := source_valid_1.io.out sink_extend.io.in := sio.ridx_valid sink_valid.io.in := sink_extend.io.out sink_ready := sink_valid.io.out sio.source_reset_n := !reset.asBool // Assert that if there is stuff in the queue, then reset cannot happen // Impossible to write because dequeue can occur on the receiving side, // then reset allowed to happen, but write side cannot know that dequeue // occurred. // TODO: write some sort of sanity check assertion for users // that denote don't reset when there is activity // assert (!(reset \|\| !sio.sink_reset_n) \|\| !io.enq.valid, "Enqueue while sink is reset and AsyncQueueSource is unprotected") // assert (!reset_rise \|\| prev_idx_match.asBool, "Sink reset while AsyncQueueSource not empty") } } class AsyncQueueSink[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module { override def desiredName = s"AsyncQueueSink_${gen.typeName}" val io = IO(new Bundle { // These come from the sink domain val deq = Decoupled(gen) // These cross to the source clock domain val async = Flipped(new AsyncBundle(gen, params)) }) val bits = params.bits val source_ready = WireInit(true.B) val ridx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.deq.fire, !source_ready, "ridx_bin")) val widx = AsyncResetSynchronizerShiftReg(io.async.widx, params.sync, Some("widx_gray")) val valid = source_ready && ridx =/= widx // The mux is safe because timing analysis ensures ridx has reached the register // On an ASIC, changes to the unread location cannot affect the selected value // On an FPGA, only one input changes at a time => mem updates don't cause glitches // The register only latches when the selected valued is not being written val index = if (bits == 0) 0.U else ridx(bits-1, 0) ^ (ridx(bits, bits) << (bits-1)) io.async.index.foreach { _ := index } // This register does not NEED to be reset, as its contents will not // be considered unless the asynchronously reset deq valid register is set. // It is possible that bits latches when the source domain is reset / has power cut // This is safe, because isolation gates brought mem low before the zeroed widx reached us val deq_bits_nxt = io.async.mem(if (params.narrow) 0.U else index) io.deq.bits := ClockCrossingReg(deq_bits_nxt, en = valid, doInit = false, name = Some("deq_bits_reg")) val valid_reg = withReset(reset.asAsyncReset)(RegNext(next=valid, init=false.B).suggestName("valid_reg")) io.deq.valid := valid_reg && source_ready val ridx_reg = withReset(reset.asAsyncReset)(RegNext(next=ridx, init=0.U).suggestName("ridx_gray")) io.async.ridx := ridx_reg io.async.safe.foreach { sio => val sink_valid_0 = Module(new AsyncValidSync(params.sync, "sink_valid_0")) val sink_valid_1 = Module(new AsyncValidSync(params.sync, "sink_valid_1")) val source_extend = Module(new AsyncValidSync(params.sync, "source_extend")) val source_valid = Module(new AsyncValidSync(params.sync, "source_valid")) sink_valid_0 .reset := (reset.asBool \|\| !sio.source_reset_n).asAsyncReset sink_valid_1 .reset := (reset.asBool \|\| !sio.source_reset_n).asAsyncReset source_extend.reset := (reset.asBool \|\| !sio.source_reset_n).asAsyncReset source_valid .reset := reset.asAsyncReset sink_valid_0 .clock := clock sink_valid_1 .clock := clock source_extend.clock := clock source_valid .clock := clock sink_valid_0.io.in := true.B sink_valid_1.io.in := sink_valid_0.io.out sio.ridx_valid := sink_valid_1.io.out source_extend.io.in := sio.widx_valid source_valid.io.in := source_extend.io.out source_ready := source_valid.io.out sio.sink_reset_n := !reset.asBool // TODO: write some sort of sanity check assertion for users // that denote don't reset when there is activity // // val reset_and_extend = !source_ready \|\| !sio.source_reset_n \|\| reset.asBool // val reset_and_extend_prev = RegNext(reset_and_extend, true.B) // val reset_rise = !reset_and_extend_prev && reset_and_extend // val prev_idx_match = AsyncResetReg(updateData=(io.async.widx===io.async.ridx), resetData=0) // assert (!reset_rise \|\| prev_idx_match.asBool, "Source reset while AsyncQueueSink not empty") } } object FromAsyncBundle { // Sometimes it makes sense for the sink to have different sync than the source def apply[T <: Data](x: AsyncBundle[T]): DecoupledIO[T] = apply(x, x.params.sync) def apply[T <: Data](x: AsyncBundle[T], sync: Int): DecoupledIO[T] = { val sink = Module(new AsyncQueueSink(chiselTypeOf(x.mem(0)), x.params.copy(sync = sync))) sink.io.async <> x sink.io.deq } } object ToAsyncBundle { def apply[T <: Data](x: ReadyValidIO[T], params: AsyncQueueParams = AsyncQueueParams()): AsyncBundle[T] = { val source = Module(new AsyncQueueSource(chiselTypeOf(x.bits), params)) source.io.enq <> x source.io.async } } class AsyncQueue[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Crossing[T] { val io = IO(new CrossingIO(gen)) val source = withClockAndReset(io.enq_clock, io.enq_reset) { Module(new AsyncQueueSource(gen, params)) } val sink = withClockAndReset(io.deq_clock, io.deq_reset) { Module(new AsyncQueueSink (gen, params)) } source.io.enq <> io.enq io.deq <> sink.io.deq sink.io.async <> source.io.async } File AsyncCrossing.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.diplomacy.{AddressSet, NodeHandle} import freechips.rocketchip.prci.{AsynchronousCrossing} import freechips.rocketchip.subsystem.CrossingWrapper import freechips.rocketchip.util.{AsyncQueueParams, ToAsyncBundle, FromAsyncBundle, Pow2ClockDivider, property} class TLAsyncCrossingSource(sync: Option[Int])(implicit p: Parameters) extends LazyModule { def this(x: Int)(implicit p: Parameters) = this(Some(x)) def this()(implicit p: Parameters) = this(None) val node = TLAsyncSourceNode(sync) lazy val module = new Impl class Impl extends LazyModuleImp(this) { override def desiredName = (Seq("TLAsyncCrossingSource") ++ node.in.headOption.map(_._2.bundle.shortName)).mkString("_") (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => val bce = edgeIn.manager.anySupportAcquireB && edgeIn.client.anySupportProbe val psync = sync.getOrElse(edgeOut.manager.async.sync) val params = edgeOut.manager.async.copy(sync = psync) out.a <> ToAsyncBundle(in.a, params) in.d <> FromAsyncBundle(out.d, psync) property.cover(in.a, "TL_ASYNC_CROSSING_SOURCE_A", "MemorySystem;;TLAsyncCrossingSource Channel A") property.cover(in.d, "TL_ASYNC_CROSSING_SOURCE_D", "MemorySystem;;TLAsyncCrossingSource Channel D") if (bce) { in.b <> FromAsyncBundle(out.b, psync) out.c <> ToAsyncBundle(in.c, params) out.e <> ToAsyncBundle(in.e, params) property.cover(in.b, "TL_ASYNC_CROSSING_SOURCE_B", "MemorySystem;;TLAsyncCrossingSource Channel B") property.cover(in.c, "TL_ASYNC_CROSSING_SOURCE_C", "MemorySystem;;TLAsyncCrossingSource Channel C") property.cover(in.e, "TL_ASYNC_CROSSING_SOURCE_E", "MemorySystem;;TLAsyncCrossingSource Channel E") } else { in.b.valid := false.B in.c.ready := true.B in.e.ready := true.B out.b.ridx := 0.U out.c.widx := 0.U out.e.widx := 0.U } } } } class TLAsyncCrossingSink(params: AsyncQueueParams = AsyncQueueParams())(implicit p: Parameters) extends LazyModule { val node = TLAsyncSinkNode(params) lazy val module = new Impl class Impl extends LazyModuleImp(this) { override def desiredName = (Seq("TLAsyncCrossingSink") ++ node.out.headOption.map(_._2.bundle.shortName)).mkString("_") (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => val bce = edgeOut.manager.anySupportAcquireB && edgeOut.client.anySupportProbe out.a <> FromAsyncBundle(in.a, params.sync) in.d <> ToAsyncBundle(out.d, params) property.cover(out.a, "TL_ASYNC_CROSSING_SINK_A", "MemorySystem;;TLAsyncCrossingSink Channel A") property.cover(out.d, "TL_ASYNC_CROSSING_SINK_D", "MemorySystem;;TLAsyncCrossingSink Channel D") if (bce) { in.b <> ToAsyncBundle(out.b, params) out.c <> FromAsyncBundle(in.c, params.sync) out.e <> FromAsyncBundle(in.e, params.sync) property.cover(out.b, "TL_ASYNC_CROSSING_SINK_B", "MemorySystem;;TLAsyncCrossingSinkChannel B") property.cover(out.c, "TL_ASYNC_CROSSING_SINK_C", "MemorySystem;;TLAsyncCrossingSink Channel C") property.cover(out.e, "TL_ASYNC_CROSSING_SINK_E", "MemorySystem;;TLAsyncCrossingSink Channel E") } else { in.b.widx := 0.U in.c.ridx := 0.U in.e.ridx := 0.U out.b.ready := true.B out.c.valid := false.B out.e.valid := false.B } } } } object TLAsyncCrossingSource { def apply()(implicit p: Parameters): TLAsyncSourceNode = apply(None) def apply(sync: Int)(implicit p: Parameters): TLAsyncSourceNode = apply(Some(sync)) def apply(sync: Option[Int])(implicit p: Parameters): TLAsyncSourceNode = { val asource = LazyModule(new TLAsyncCrossingSource(sync)) asource.node } } object TLAsyncCrossingSink { def apply(params: AsyncQueueParams = AsyncQueueParams())(implicit p: Parameters) = { val asink = LazyModule(new TLAsyncCrossingSink(params)) asink.node } } @deprecated("TLAsyncCrossing is fragile. Use TLAsyncCrossingSource and TLAsyncCrossingSink", "rocket-chip 1.2") class TLAsyncCrossing(params: AsyncQueueParams = AsyncQueueParams())(implicit p: Parameters) extends LazyModule { val source = LazyModule(new TLAsyncCrossingSource()) val sink = LazyModule(new TLAsyncCrossingSink(params)) val node = NodeHandle(source.node, sink.node) sink.node := source.node lazy val module = new Impl class Impl extends LazyModuleImp(this) { val io = IO(new Bundle { val in_clock = Input(Clock()) val in_reset = Input(Bool()) val out_clock = Input(Clock()) val out_reset = Input(Bool()) }) source.module.clock := io.in_clock source.module.reset := io.in_reset sink.module.clock := io.out_clock sink.module.reset := io.out_reset } } // Synthesizable unit tests import freechips.rocketchip.unittest._ class TLRAMAsyncCrossing(txns: Int, params: AsynchronousCrossing = AsynchronousCrossing())(implicit p: Parameters) extends LazyModule { val model = LazyModule(new TLRAMModel("AsyncCrossing")) val fuzz = LazyModule(new TLFuzzer(txns)) val island = LazyModule(new CrossingWrapper(params)) val ram = island { LazyModule(new TLRAM(AddressSet(0x0, 0x3ff))) } island.crossTLIn(ram.node) := TLFragmenter(4, 256) := TLDelayer(0.1) := model.node := fuzz.node lazy val module = new Impl class Impl extends LazyModuleImp(this) with UnitTestModule { io.finished := fuzz.module.io.finished // Shove the RAM into another clock domain val clocks = Module(new Pow2ClockDivider(2)) island.module.clock := clocks.io.clock_out } } class TLRAMAsyncCrossingTest(txns: Int = 5000, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) { val dut_wide = Module(LazyModule(new TLRAMAsyncCrossing(txns)).module) val dut_narrow = Module(LazyModule(new TLRAMAsyncCrossing(txns, AsynchronousCrossing(safe = false, narrow = true))).module) io.finished := dut_wide.io.finished && dut_narrow.io.finished dut_wide.io.start := io.start dut_narrow.io.start := io.start } File LazyModuleImp.scala: package org.chipsalliance.diplomacy.lazymodule import chisel3.{withClockAndReset, Module, RawModule, Reset, _} import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo} import firrtl.passes.InlineAnnotation import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.nodes.Dangle import scala.collection.immutable.SortedMap /* Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]]. * * This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy. / sealed trait LazyModuleImpLike extends RawModule { /* [[LazyModule]] that contains this instance. / val wrapper: LazyModule /* IOs that will be automatically "punched" for this instance. / val auto: AutoBundle /* The metadata that describes the [[HalfEdge]]s which generated [[auto]]. / protected[diplomacy] val dangles: Seq[Dangle] // [[wrapper.module]] had better not be accessed while LazyModules are still being built! require( LazyModule.scope.isEmpty, s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}" ) /* Set module name. Defaults to the containing LazyModule's desiredName. / override def desiredName: String = wrapper.desiredName suggestName(wrapper.suggestedName) /* [[Parameters]] for chisel [[Module]]s. / implicit val p: Parameters = wrapper.p /* instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and * submodules. / protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = { // 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]], // 2. return [[Dangle]]s from each module. val childDangles = wrapper.children.reverse.flatMap { c => implicit val sourceInfo: SourceInfo = c.info c.cloneProto.map { cp => // If the child is a clone, then recursively set cloneProto of its children as well def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = { require(bases.size == clones.size) (bases.zip(clones)).map { case (l, r) => require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}") l.cloneProto = Some(r) assignCloneProtos(l.children, r.children) } } assignCloneProtos(c.children, cp.children) // Clone the child module as a record, and get its [[AutoBundle]] val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName) val clonedAuto = clone("auto").asInstanceOf[AutoBundle] // Get the empty [[Dangle]]'s of the cloned child val rawDangles = c.cloneDangles() require(rawDangles.size == clonedAuto.elements.size) // Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) } dangles }.getOrElse { // For non-clones, instantiate the child module val mod = try { Module(c.module) } catch { case e: ChiselException => { println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}") throw e } } mod.dangles } } // Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]]. // This will result in a sequence of [[Dangle]] from these [[BaseNode]]s. val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate()) // Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]] val allDangles = nodeDangles ++ childDangles // Group [[allDangles]] by their [[source]]. val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _) // For each [[source]] set of [[Dangle]]s of size 2, ensure that these // can be connected as a source-sink pair (have opposite flipped value). // Make the connection and mark them as [[done]]. val done = Set() ++ pairing.values.filter(_.size == 2).map { case Seq(a, b) => require(a.flipped != b.flipped) // @todo <> in chisel3 makes directionless connection. if (a.flipped) { a.data <> b.data } else { b.data <> a.data } a.source case _ => None } // Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module. val forward = allDangles.filter(d => !done(d.source)) // Generate [[AutoBundle]] IO from [[forward]]. val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _)) // Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]] val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) => if (d.flipped) { d.data <> io } else { io <> d.data } d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name) } // Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]]. wrapper.inModuleBody.reverse.foreach { _() } if (wrapper.shouldBeInlined) { chisel3.experimental.annotate(new ChiselAnnotation { def toFirrtl = InlineAnnotation(toNamed) }) } // Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]]. (auto, dangles) } } /* Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. / class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike { /* Instantiate hardware of this `Module`. / val (auto, dangles) = instantiate() } /* Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. / class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike { // These wires are the default clock+reset for all LazyModule children. // It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the // [[LazyRawModuleImp]] children. // Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly. /* drive clock explicitly. / val childClock: Clock = Wire(Clock()) /* drive reset explicitly. / val childReset: Reset = Wire(Reset()) // the default is that these are disabled childClock := false.B.asClock childReset := chisel3.DontCare def provideImplicitClockToLazyChildren: Boolean = false val (auto, dangles) = if (provideImplicitClockToLazyChildren) { withClockAndReset(childClock, childReset) { instantiate() } } else { instantiate() } } File MixedNode.scala: package org.chipsalliance.diplomacy.nodes import chisel3.{Data, DontCare, Wire} import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.{Field, Parameters} import org.chipsalliance.diplomacy.ValName import org.chipsalliance.diplomacy.sourceLine /* One side metadata of a [[Dangle]]. * * Describes one side of an edge going into or out of a [[BaseNode]]. * * @param serial * the global [[BaseNode.serial]] number of the [[BaseNode]] that this [[HalfEdge]] connects to. * @param index * the `index` in the [[BaseNode]]'s input or output port list that this [[HalfEdge]] belongs to. / case class HalfEdge(serial: Int, index: Int) extends Ordered[HalfEdge] { import scala.math.Ordered.orderingToOrdered def compare(that: HalfEdge): Int = HalfEdge.unapply(this).compare(HalfEdge.unapply(that)) } /* [[Dangle]] captures the `IO` information of a [[LazyModule]] and which two [[BaseNode]]s the [[Edges]]/[[Bundle]] * connects. * * [[Dangle]]s are generated by [[BaseNode.instantiate]] using [[MixedNode.danglesOut]] and [[MixedNode.danglesIn]] , * [[LazyModuleImp.instantiate]] connects those that go to internal or explicit IO connections in a [[LazyModule]]. * * @param source * the source [[HalfEdge]] of this [[Dangle]], which captures the source [[BaseNode]] and the port `index` within * that [[BaseNode]]. * @param sink * sink [[HalfEdge]] of this [[Dangle]], which captures the sink [[BaseNode]] and the port `index` within that * [[BaseNode]]. * @param flipped * flip or not in [[AutoBundle.makeElements]]. If true this corresponds to `danglesOut`, if false it corresponds to * `danglesIn`. * @param dataOpt * actual [[Data]] for the hardware connection. Can be empty if this belongs to a cloned module / case class Dangle(source: HalfEdge, sink: HalfEdge, flipped: Boolean, name: String, dataOpt: Option[Data]) { def data = dataOpt.get } /* [[Edges]] is a collection of parameters describing the functionality and connection for an interface, which is often * derived from the interconnection protocol and can inform the parameterization of the hardware bundles that actually * implement the protocol. / case class Edges[EI, EO](in: Seq[EI], out: Seq[EO]) /* A field available in [[Parameters]] used to determine whether [[InwardNodeImp.monitor]] will be called. / case object MonitorsEnabled extends Field[Boolean](true) /* When rendering the edge in a graphical format, flip the order in which the edges' source and sink are presented. * * For example, when rendering graphML, yEd by default tries to put the source node vertically above the sink node, but * [[RenderFlipped]] inverts this relationship. When a particular [[LazyModule]] contains both source nodes and sink * nodes, flipping the rendering of one node's edge will usual produce a more concise visual layout for the * [[LazyModule]]. / case object RenderFlipped extends Field[Boolean](false) /* The sealed node class in the package, all node are derived from it. * * @param inner * Sink interface implementation. * @param outer * Source interface implementation. * @param valName * val name of this node. * @tparam DI * Downward-flowing parameters received on the inner side of the node. It is usually a brunch of parameters * describing the protocol parameters from a source. For an [[InwardNode]], it is determined by the connected * [[OutwardNode]]. Since it can be connected to multiple sources, this parameter is always a Seq of source port * parameters. * @tparam UI * Upward-flowing parameters generated by the inner side of the node. It is usually a brunch of parameters describing * the protocol parameters of a sink. For an [[InwardNode]], it is determined itself. * @tparam EI * Edge Parameters describing a connection on the inner side of the node. It is usually a brunch of transfers * specified for a sink according to protocol. * @tparam BI * Bundle type used when connecting to the inner side of the node. It is a hardware interface of this sink interface. * It should extends from [[chisel3.Data]], which represents the real hardware. * @tparam DO * Downward-flowing parameters generated on the outer side of the node. It is usually a brunch of parameters * describing the protocol parameters of a source. For an [[OutwardNode]], it is determined itself. * @tparam UO * Upward-flowing parameters received by the outer side of the node. It is usually a brunch of parameters describing * the protocol parameters from a sink. For an [[OutwardNode]], it is determined by the connected [[InwardNode]]. * Since it can be connected to multiple sinks, this parameter is always a Seq of sink port parameters. * @tparam EO * Edge Parameters describing a connection on the outer side of the node. It is usually a brunch of transfers * specified for a source according to protocol. * @tparam BO * Bundle type used when connecting to the outer side of the node. It is a hardware interface of this source * interface. It should extends from [[chisel3.Data]], which represents the real hardware. * * @note * Call Graph of [[MixedNode]] * - line `─`: source is process by a function and generate pass to others * - Arrow `→`: target of arrow is generated by source * * {{{ * (from the other node) * ┌─────────────────────────────────────────────────────────[[InwardNode.uiParams]]─────────────┐ * ↓ │ * (binding node when elaboration) [[OutwardNode.uoParams]]────────────────────────[[MixedNode.mapParamsU]]→──────────┐ │ * [[InwardNode.accPI]] │ │ │ * │ │ (based on protocol) │ * │ │ [[MixedNode.inner.edgeI]] │ * │ │ ↓ │ * ↓ │ │ │ * (immobilize after elaboration) (inward port from [[OutwardNode]]) │ ↓ │ * [[InwardNode.iBindings]]──┐ [[MixedNode.iDirectPorts]]────────────────────→[[MixedNode.iPorts]] [[InwardNode.uiParams]] │ * │ │ ↑ │ │ │ * │ │ │ [[OutwardNode.doParams]] │ │ * │ │ │ (from the other node) │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * │ │ │ └────────┬──────────────┤ │ * │ │ │ │ │ │ * │ │ │ │ (based on protocol) │ * │ │ │ │ [[MixedNode.inner.edgeI]] │ * │ │ │ │ │ │ * │ │ (from the other node) │ ↓ │ * │ └───[[OutwardNode.oPortMapping]] [[OutwardNode.oStar]] │ [[MixedNode.edgesIn]]───┐ │ * │ ↑ ↑ │ │ ↓ │ * │ │ │ │ │ [[MixedNode.in]] │ * │ │ │ │ ↓ ↑ │ * │ (solve star connection) │ │ │ [[MixedNode.bundleIn]]──┘ │ * ├───[[MixedNode.resolveStar]]→─┼─────────────────────────────┤ └────────────────────────────────────┐ │ * │ │ │ [[MixedNode.bundleOut]]─┐ │ │ * │ │ │ ↑ ↓ │ │ * │ │ │ │ [[MixedNode.out]] │ │ * │ ↓ ↓ │ ↑ │ │ * │ ┌─────[[InwardNode.iPortMapping]] [[InwardNode.iStar]] [[MixedNode.edgesOut]]──┘ │ │ * │ │ (from the other node) ↑ │ │ * │ │ │ │ │ │ * │ │ │ [[MixedNode.outer.edgeO]] │ │ * │ │ │ (based on protocol) │ │ * │ │ │ │ │ │ * │ │ │ ┌────────────────────────────────────────┤ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * (immobilize after elaboration)│ ↓ │ │ │ │ * [[OutwardNode.oBindings]]─┘ [[MixedNode.oDirectPorts]]───→[[MixedNode.oPorts]] [[OutwardNode.doParams]] │ │ * ↑ (inward port from [[OutwardNode]]) │ │ │ │ * │ ┌─────────────────────────────────────────┤ │ │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * [[OutwardNode.accPO]] │ ↓ │ │ │ * (binding node when elaboration) │ [[InwardNode.diParams]]─────→[[MixedNode.mapParamsD]]────────────────────────────┘ │ │ * │ ↑ │ │ * │ └──────────────────────────────────────────────────────────────────────────────────────────┘ │ * └──────────────────────────────────────────────────────────────────────────────────────────────────────────┘ * }}} / abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data]( val inner: InwardNodeImp[DI, UI, EI, BI], val outer: OutwardNodeImp[DO, UO, EO, BO] )( implicit valName: ValName) extends BaseNode with NodeHandle[DI, UI, EI, BI, DO, UO, EO, BO] with InwardNode[DI, UI, BI] with OutwardNode[DO, UO, BO] { // Generate a [[NodeHandle]] with inward and outward node are both this node. val inward = this val outward = this /* Debug info of nodes binding. / def bindingInfo: String = s"""$iBindingInfo \|$oBindingInfo \|""".stripMargin /* Debug info of ports connecting. / def connectedPortsInfo: String = s"""${oPorts.size} outward ports connected: [${oPorts.map(_._2.name).mkString(",")}] \|${iPorts.size} inward ports connected: [${iPorts.map(_._2.name).mkString(",")}] \|""".stripMargin /* Debug info of parameters propagations. / def parametersInfo: String = s"""${doParams.size} downstream outward parameters: [${doParams.mkString(",")}] \|${uoParams.size} upstream outward parameters: [${uoParams.mkString(",")}] \|${diParams.size} downstream inward parameters: [${diParams.mkString(",")}] \|${uiParams.size} upstream inward parameters: [${uiParams.mkString(",")}] \|""".stripMargin /* For a given node, converts [[OutwardNode.accPO]] and [[InwardNode.accPI]] to [[MixedNode.oPortMapping]] and * [[MixedNode.iPortMapping]]. * * Given counts of known inward and outward binding and inward and outward star bindings, return the resolved inward * stars and outward stars. * * This method will also validate the arguments and throw a runtime error if the values are unsuitable for this type * of node. * * @param iKnown * Number of known-size ([[BIND_ONCE]]) input bindings. * @param oKnown * Number of known-size ([[BIND_ONCE]]) output bindings. * @param iStar * Number of unknown size ([[BIND_STAR]]) input bindings. * @param oStar * Number of unknown size ([[BIND_STAR]]) output bindings. * @return * A Tuple of the resolved number of input and output connections. / protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStar: Int, oStar: Int): (Int, Int) /* Function to generate downward-flowing outward params from the downward-flowing input params and the current output * ports. * * @param n * The size of the output sequence to generate. * @param p * Sequence of downward-flowing input parameters of this node. * @return * A `n`-sized sequence of downward-flowing output edge parameters. / protected[diplomacy] def mapParamsD(n: Int, p: Seq[DI]): Seq[DO] /* Function to generate upward-flowing input parameters from the upward-flowing output parameters [[uiParams]]. * * @param n * Size of the output sequence. * @param p * Upward-flowing output edge parameters. * @return * A n-sized sequence of upward-flowing input edge parameters. / protected[diplomacy] def mapParamsU(n: Int, p: Seq[UO]): Seq[UI] /* @return * The sink cardinality of the node, the number of outputs bound with [[BIND_QUERY]] summed with inputs bound with * [[BIND_STAR]]. / protected[diplomacy] lazy val sinkCard: Int = oBindings.count(_._3 == BIND_QUERY) + iBindings.count(_._3 == BIND_STAR) /* @return * The source cardinality of this node, the number of inputs bound with [[BIND_QUERY]] summed with the number of * output bindings bound with [[BIND_STAR]]. / protected[diplomacy] lazy val sourceCard: Int = iBindings.count(_._3 == BIND_QUERY) + oBindings.count(_._3 == BIND_STAR) /* @return list of nodes involved in flex bindings with this node. / protected[diplomacy] lazy val flexes: Seq[BaseNode] = oBindings.filter(_._3 == BIND_FLEX).map(_._2) ++ iBindings.filter(_._3 == BIND_FLEX).map(_._2) /* Resolves the flex to be either source or sink and returns the offset where the [[BIND_STAR]] operators begin * greedily taking up the remaining connections. * * @return * A value >= 0 if it is sink cardinality, a negative value for source cardinality. The magnitude of the return * value is not relevant. / protected[diplomacy] lazy val flexOffset: Int = { /* Recursively performs a depth-first search of the [[flexes]], [[BaseNode]]s connected to this node with flex * operators. The algorithm bottoms out when we either get to a node we have already visited or when we get to a * connection that is not a flex and can set the direction for us. Otherwise, recurse by visiting the `flexes` of * each node in the current set and decide whether they should be added to the set or not. * * @return * the mapping of [[BaseNode]] indexed by their serial numbers. / def DFS(v: BaseNode, visited: Map[Int, BaseNode]): Map[Int, BaseNode] = { if (visited.contains(v.serial) \|\| !v.flexibleArityDirection) { visited } else { v.flexes.foldLeft(visited + (v.serial -> v))((sum, n) => DFS(n, sum)) } } /* Determine which [[BaseNode]] are involved in resolving the flex connections to/from this node. * * @example * {{{ * a := b := c * d := b * e := f * }}} * * `flexSet` for `a`, `b`, `c`, or `d` will be `Set(a, b, c, d)` `flexSet` for `e` or `f` will be `Set(e,f)` / val flexSet = DFS(this, Map()).values /* The total number of := operators where we're on the left. / val allSink = flexSet.map(_.sinkCard).sum /** The total number of :=* operators used when we're on the right. / val allSource = flexSet.map(_.sourceCard).sum require( allSink == 0 \|\| allSource == 0, s"The nodes ${flexSet.map(_.name)} which are inter-connected by :=* have ${allSink} := operators and ${allSource} := operators connected to them, making it impossible to determine cardinality inference direction." ) allSink - allSource } /** @return A value >= 0 if it is sink cardinality, a negative value for source cardinality. / protected[diplomacy] def edgeArityDirection(n: BaseNode): Int = { if (flexibleArityDirection) flexOffset else if (n.flexibleArityDirection) n.flexOffset else 0 } /* For a node which is connected between two nodes, select the one that will influence the direction of the flex * resolution. / protected[diplomacy] def edgeAritySelect(n: BaseNode, l: => Int, r: => Int): Int = { val dir = edgeArityDirection(n) if (dir < 0) l else if (dir > 0) r else 1 } /* Ensure that the same node is not visited twice in resolving `:=`, etc operators. / private var starCycleGuard = false /** Resolve all the star operators into concrete indicies. As connections are being made, some may be "star" * connections which need to be resolved. In some way to determine how many actual edges they correspond to. We also * need to build up the ranges of edges which correspond to each binding operator, so that We can apply the correct * edge parameters and later build up correct bundle connections. * * [[oPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that oPort (binding * operator). [[iPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that iPort * (binding operator). [[oStar]]: `Int` the value to return for this node `N` for any `N := foo` or `N :=* foo := bar` [[iStar]]: `Int` the value to return for this node `N` for any `foo :=* N` or `bar :=* foo := N` / protected[diplomacy] lazy val ( oPortMapping: Seq[(Int, Int)], iPortMapping: Seq[(Int, Int)], oStar: Int, iStar: Int ) = { try { if (starCycleGuard) throw StarCycleException() starCycleGuard = true // For a given node N... // Number of foo := N // + Number of bar :=* foo := N val oStars = oBindings.count { case (_, n, b, _, _) => b == BIND_STAR \|\| (b == BIND_FLEX && edgeArityDirection(n) < 0) } // Number of N := foo // + Number of N :=* foo := bar val iStars = iBindings.count { case (_, n, b, _, _) => b == BIND_STAR \|\| (b == BIND_FLEX && edgeArityDirection(n) > 0) } // 1 for foo := N // + bar.iStar for bar := foo := N // + foo.iStar for foo := N // + 0 for foo := N val oKnown = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, 0, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => 0 } }.sum // 1 for N := foo // + bar.oStar for N := foo :=* bar // + foo.oStar for N :=* foo // + 0 for N := foo val iKnown = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, 0) case BIND_QUERY => n.oStar case BIND_STAR => 0 } }.sum // Resolve star depends on the node subclass to implement the algorithm for this. val (iStar, oStar) = resolveStar(iKnown, oKnown, iStars, oStars) // Cumulative list of resolved outward binding range starting points val oSum = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, oStar, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => oStar } }.scanLeft(0)(_ + _) // Cumulative list of resolved inward binding range starting points val iSum = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, iStar) case BIND_QUERY => n.oStar case BIND_STAR => iStar } }.scanLeft(0)(_ + _) // Create ranges for each binding based on the running sums and return // those along with resolved values for the star operations. (oSum.init.zip(oSum.tail), iSum.init.zip(iSum.tail), oStar, iStar) } catch { case c: StarCycleException => throw c.copy(loop = context +: c.loop) } } /* Sequence of inward ports. * * This should be called after all star bindings are resolved. * * Each element is: `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. * `n` Instance of inward node. `p` View of [[Parameters]] where this connection was made. `s` Source info where this * connection was made in the source code. / protected[diplomacy] lazy val oDirectPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oBindings.flatMap { case (i, n, _, p, s) => // for each binding operator in this node, look at what it connects to val (start, end) = n.iPortMapping(i) (start until end).map { j => (j, n, p, s) } } /* Sequence of outward ports. * * This should be called after all star bindings are resolved. * * `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. `n` Instance of * outward node. `p` View of [[Parameters]] where this connection was made. `s` [[SourceInfo]] where this connection * was made in the source code. / protected[diplomacy] lazy val iDirectPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iBindings.flatMap { case (i, n, _, p, s) => // query this port index range of this node in the other side of node. val (start, end) = n.oPortMapping(i) (start until end).map { j => (j, n, p, s) } } // Ephemeral nodes ( which have non-None iForward/oForward) have in_degree = out_degree // Thus, there must exist an Eulerian path and the below algorithms terminate @scala.annotation.tailrec private def oTrace( tuple: (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) ): (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.iForward(i) match { case None => (i, n, p, s) case Some((j, m)) => oTrace((j, m, p, s)) } } @scala.annotation.tailrec private def iTrace( tuple: (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) ): (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.oForward(i) match { case None => (i, n, p, s) case Some((j, m)) => iTrace((j, m, p, s)) } } /* Final output ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - Numeric index of this binding in the [[InwardNode]] on the other end. * - [[InwardNode]] on the other end of this binding. * - A view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. / lazy val oPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oDirectPorts.map(oTrace) /* Final input ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - numeric index of this binding in [[OutwardNode]] on the other end. * - [[OutwardNode]] on the other end of this binding. * - a view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. / lazy val iPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iDirectPorts.map(iTrace) private var oParamsCycleGuard = false protected[diplomacy] lazy val diParams: Seq[DI] = iPorts.map { case (i, n, _, _) => n.doParams(i) } protected[diplomacy] lazy val doParams: Seq[DO] = { try { if (oParamsCycleGuard) throw DownwardCycleException() oParamsCycleGuard = true val o = mapParamsD(oPorts.size, diParams) require( o.size == oPorts.size, s"""Diplomacy has detected a problem with your graph: \|At the following node, the number of outward ports should equal the number of produced outward parameters. \|$context \|$connectedPortsInfo \|Downstreamed inward parameters: [${diParams.mkString(",")}] \|Produced outward parameters: [${o.mkString(",")}] \|""".stripMargin ) o.map(outer.mixO(_, this)) } catch { case c: DownwardCycleException => throw c.copy(loop = context +: c.loop) } } private var iParamsCycleGuard = false protected[diplomacy] lazy val uoParams: Seq[UO] = oPorts.map { case (o, n, _, _) => n.uiParams(o) } protected[diplomacy] lazy val uiParams: Seq[UI] = { try { if (iParamsCycleGuard) throw UpwardCycleException() iParamsCycleGuard = true val i = mapParamsU(iPorts.size, uoParams) require( i.size == iPorts.size, s"""Diplomacy has detected a problem with your graph: \|At the following node, the number of inward ports should equal the number of produced inward parameters. \|$context \|$connectedPortsInfo \|Upstreamed outward parameters: [${uoParams.mkString(",")}] \|Produced inward parameters: [${i.mkString(",")}] \|""".stripMargin ) i.map(inner.mixI(_, this)) } catch { case c: UpwardCycleException => throw c.copy(loop = context +: c.loop) } } /* Outward edge parameters. / protected[diplomacy] lazy val edgesOut: Seq[EO] = (oPorts.zip(doParams)).map { case ((i, n, p, s), o) => outer.edgeO(o, n.uiParams(i), p, s) } /* Inward edge parameters. / protected[diplomacy] lazy val edgesIn: Seq[EI] = (iPorts.zip(uiParams)).map { case ((o, n, p, s), i) => inner.edgeI(n.doParams(o), i, p, s) } /* A tuple of the input edge parameters and output edge parameters for the edges bound to this node. * * If you need to access to the edges of a foreign Node, use this method (in/out create bundles). / lazy val edges: Edges[EI, EO] = Edges(edgesIn, edgesOut) /* Create actual Wires corresponding to the Bundles parameterized by the outward edges of this node. / protected[diplomacy] lazy val bundleOut: Seq[BO] = edgesOut.map { e => val x = Wire(outer.bundleO(e)).suggestName(s"${valName.value}Out") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } /* Create actual Wires corresponding to the Bundles parameterized by the inward edges of this node. / protected[diplomacy] lazy val bundleIn: Seq[BI] = edgesIn.map { e => val x = Wire(inner.bundleI(e)).suggestName(s"${valName.value}In") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } private def emptyDanglesOut: Seq[Dangle] = oPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(serial, i), sink = HalfEdge(n.serial, j), flipped = false, name = wirePrefix + "out", dataOpt = None ) } private def emptyDanglesIn: Seq[Dangle] = iPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(n.serial, j), sink = HalfEdge(serial, i), flipped = true, name = wirePrefix + "in", dataOpt = None ) } /* Create the [[Dangle]]s which describe the connections from this node output to other nodes inputs. / protected[diplomacy] def danglesOut: Seq[Dangle] = emptyDanglesOut.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleOut(i))) } /* Create the [[Dangle]]s which describe the connections from this node input from other nodes outputs. / protected[diplomacy] def danglesIn: Seq[Dangle] = emptyDanglesIn.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleIn(i))) } private[diplomacy] var instantiated = false /* Gather Bundle and edge parameters of outward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. / def out: Seq[(BO, EO)] = { require( instantiated, s"$name.out should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleOut.zip(edgesOut) } /* Gather Bundle and edge parameters of inward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. / def in: Seq[(BI, EI)] = { require( instantiated, s"$name.in should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleIn.zip(edgesIn) } /* Actually instantiate this node during [[LazyModuleImp]] evaluation. Mark that it's safe to use the Bundle wires, * instantiate monitors on all input ports if appropriate, and return all the dangles of this node. / protected[diplomacy] def instantiate(): Seq[Dangle] = { instantiated = true if (!circuitIdentity) { (iPorts.zip(in)).foreach { case ((_, _, p, _), (b, e)) => if (p(MonitorsEnabled)) inner.monitor(b, e) } } danglesOut ++ danglesIn } protected[diplomacy] def cloneDangles(): Seq[Dangle] = emptyDanglesOut ++ emptyDanglesIn /* Connects the outward part of a node with the inward part of this node. / protected[diplomacy] def bind( h: OutwardNode[DI, UI, BI], binding: NodeBinding )( implicit p: Parameters, sourceInfo: SourceInfo ): Unit = { val x = this // x := y val y = h sourceLine(sourceInfo, " at ", "") val i = x.iPushed val o = y.oPushed y.oPush( i, x, binding match { case BIND_ONCE => BIND_ONCE case BIND_FLEX => BIND_FLEX case BIND_STAR => BIND_QUERY case BIND_QUERY => BIND_STAR } ) x.iPush(o, y, binding) } / Metadata for printing the node graph. / def inputs: Seq[(OutwardNode[DI, UI, BI], RenderedEdge)] = (iPorts.zip(edgesIn)).map { case ((_, n, p, _), e) => val re = inner.render(e) (n, re.copy(flipped = re.flipped != p(RenderFlipped))) } /* Metadata for printing the node graph */ def outputs: Seq[(InwardNode[DO, UO, BO], RenderedEdge)] = oPorts.map { case (i, n, _, _) => (n, n.inputs(i)._2) } }	module TLAsyncCrossingSource_a9d32s1k1z2u( // @[AsyncCrossing.scala:23:9] input clock, // @[AsyncCrossing.scala:23:9] input reset, // @[AsyncCrossing.scala:23:9] output auto_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [8:0] auto_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [31:0] auto_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_d_bits_param, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [31:0] auto_in_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_mem_0_opcode, // @[LazyModuleImp.scala:107:25] output [8:0] auto_out_a_mem_0_address, // @[LazyModuleImp.scala:107:25] output [31:0] auto_out_a_mem_0_data, // @[LazyModuleImp.scala:107:25] input auto_out_a_ridx, // @[LazyModuleImp.scala:107:25] output auto_out_a_widx, // @[LazyModuleImp.scala:107:25] input auto_out_a_safe_ridx_valid, // @[LazyModuleImp.scala:107:25] output auto_out_a_safe_widx_valid, // @[LazyModuleImp.scala:107:25] output auto_out_a_safe_source_reset_n, // @[LazyModuleImp.scala:107:25] input auto_out_a_safe_sink_reset_n, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_d_mem_0_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_out_d_mem_0_size, // @[LazyModuleImp.scala:107:25] input auto_out_d_mem_0_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_out_d_mem_0_data, // @[LazyModuleImp.scala:107:25] output auto_out_d_ridx, // @[LazyModuleImp.scala:107:25] input auto_out_d_widx, // @[LazyModuleImp.scala:107:25] output auto_out_d_safe_ridx_valid, // @[LazyModuleImp.scala:107:25] input auto_out_d_safe_widx_valid, // @[LazyModuleImp.scala:107:25] input auto_out_d_safe_source_reset_n, // @[LazyModuleImp.scala:107:25] output auto_out_d_safe_sink_reset_n // @[LazyModuleImp.scala:107:25] ); wire auto_in_a_valid_0 = auto_in_a_valid; // @[AsyncCrossing.scala:23:9] wire [2:0] auto_in_a_bits_opcode_0 = auto_in_a_bits_opcode; // @[AsyncCrossing.scala:23:9] wire [8:0] auto_in_a_bits_address_0 = auto_in_a_bits_address; // @[AsyncCrossing.scala:23:9] wire [31:0] auto_in_a_bits_data_0 = auto_in_a_bits_data; // @[AsyncCrossing.scala:23:9] wire auto_in_d_ready_0 = auto_in_d_ready; // @[AsyncCrossing.scala:23:9] wire auto_out_a_ridx_0 = auto_out_a_ridx; // @[AsyncCrossing.scala:23:9] wire auto_out_a_safe_ridx_valid_0 = auto_out_a_safe_ridx_valid; // @[AsyncCrossing.scala:23:9] wire auto_out_a_safe_sink_reset_n_0 = auto_out_a_safe_sink_reset_n; // @[AsyncCrossing.scala:23:9] wire [2:0] auto_out_d_mem_0_opcode_0 = auto_out_d_mem_0_opcode; // @[AsyncCrossing.scala:23:9] wire [1:0] auto_out_d_mem_0_size_0 = auto_out_d_mem_0_size; // @[AsyncCrossing.scala:23:9] wire auto_out_d_mem_0_source_0 = auto_out_d_mem_0_source; // @[AsyncCrossing.scala:23:9] wire [31:0] auto_out_d_mem_0_data_0 = auto_out_d_mem_0_data; // @[AsyncCrossing.scala:23:9] wire auto_out_d_widx_0 = auto_out_d_widx; // @[AsyncCrossing.scala:23:9] wire auto_out_d_safe_widx_valid_0 = auto_out_d_safe_widx_valid; // @[AsyncCrossing.scala:23:9] wire auto_out_d_safe_source_reset_n_0 = auto_out_d_safe_source_reset_n; // @[AsyncCrossing.scala:23:9] wire [31:0] auto_out_b_mem_0_data = 32'h0; // @[AsyncCrossing.scala:23:9] wire [31:0] auto_out_c_mem_0_data = 32'h0; // @[AsyncCrossing.scala:23:9] wire [31:0] nodeOut_b_mem_0_data = 32'h0; // @[MixedNode.scala:542:17] wire [31:0] nodeOut_c_mem_0_data = 32'h0; // @[MixedNode.scala:542:17] wire [3:0] auto_out_b_mem_0_mask = 4'h0; // @[AsyncCrossing.scala:23:9] wire [3:0] nodeOut_b_mem_0_mask = 4'h0; // @[AsyncCrossing.scala:23:9] wire [8:0] auto_out_b_mem_0_address = 9'h0; // @[AsyncCrossing.scala:23:9] wire [8:0] auto_out_c_mem_0_address = 9'h0; // @[AsyncCrossing.scala:23:9] wire [8:0] nodeOut_b_mem_0_address = 9'h0; // @[MixedNode.scala:542:17] wire [8:0] nodeOut_c_mem_0_address = 9'h0; // @[MixedNode.scala:542:17] wire [1:0] auto_out_b_mem_0_param = 2'h0; // @[AsyncCrossing.scala:23:9] wire [1:0] auto_out_b_mem_0_size = 2'h0; // @[AsyncCrossing.scala:23:9] wire [1:0] auto_out_c_mem_0_size = 2'h0; // @[AsyncCrossing.scala:23:9] wire [1:0] auto_out_d_mem_0_param = 2'h0; // @[AsyncCrossing.scala:23:9] wire [1:0] nodeOut_b_mem_0_param = 2'h0; // @[MixedNode.scala:542:17] wire [1:0] nodeOut_b_mem_0_size = 2'h0; // @[MixedNode.scala:542:17] wire [1:0] nodeOut_c_mem_0_size = 2'h0; // @[MixedNode.scala:542:17] wire [1:0] nodeOut_d_mem_0_param = 2'h0; // @[MixedNode.scala:542:17] wire [3:0] auto_in_a_bits_mask = 4'hF; // @[AsyncCrossing.scala:23:9] wire [3:0] auto_out_a_mem_0_mask = 4'hF; // @[AsyncCrossing.scala:23:9] wire [3:0] nodeIn_a_bits_mask = 4'hF; // @[MixedNode.scala:551:17] wire [3:0] nodeOut_a_mem_0_mask = 4'hF; // @[MixedNode.scala:542:17] wire auto_in_a_bits_source = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_in_a_bits_corrupt = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_out_a_mem_0_source = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_out_a_mem_0_corrupt = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_out_b_mem_0_source = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_out_b_mem_0_corrupt = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_out_b_ridx = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_out_b_widx = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_out_b_safe_ridx_valid = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_out_b_safe_widx_valid = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_out_b_safe_source_reset_n = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_out_b_safe_sink_reset_n = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_out_c_mem_0_source = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_out_c_mem_0_corrupt = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_out_c_ridx = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_out_c_widx = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_out_c_safe_ridx_valid = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_out_c_safe_widx_valid = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_out_c_safe_source_reset_n = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_out_c_safe_sink_reset_n = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_out_d_mem_0_sink = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_out_d_mem_0_denied = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_out_d_mem_0_corrupt = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_out_e_mem_0_sink = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_out_e_ridx = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_out_e_widx = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_out_e_safe_ridx_valid = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_out_e_safe_widx_valid = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_out_e_safe_source_reset_n = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_out_e_safe_sink_reset_n = 1'h0; // @[AsyncCrossing.scala:23:9] wire nodeIn_a_bits_source = 1'h0; // @[MixedNode.scala:551:17] wire nodeIn_a_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17] wire nodeOut_a_mem_0_source = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_a_mem_0_corrupt = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_b_mem_0_source = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_b_mem_0_corrupt = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_b_ridx = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_b_widx = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_b_safe_ridx_valid = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_b_safe_widx_valid = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_b_safe_source_reset_n = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_b_safe_sink_reset_n = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_c_mem_0_source = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_c_mem_0_corrupt = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_c_ridx = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_c_widx = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_c_safe_ridx_valid = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_c_safe_widx_valid = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_c_safe_source_reset_n = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_c_safe_sink_reset_n = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_d_mem_0_sink = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_d_mem_0_denied = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_d_mem_0_corrupt = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_e_mem_0_sink = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_e_ridx = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_e_widx = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_e_safe_ridx_valid = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_e_safe_widx_valid = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_e_safe_source_reset_n = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_e_safe_sink_reset_n = 1'h0; // @[MixedNode.scala:542:17] wire [1:0] auto_in_a_bits_size = 2'h2; // @[AsyncCrossing.scala:23:9] wire [1:0] auto_out_a_mem_0_size = 2'h2; // @[AsyncCrossing.scala:23:9] wire [1:0] nodeIn_a_bits_size = 2'h2; // @[MixedNode.scala:551:17] wire [1:0] nodeOut_a_mem_0_size = 2'h2; // @[MixedNode.scala:542:17] wire [2:0] auto_in_a_bits_param = 3'h0; // @[AsyncCrossing.scala:23:9] wire [2:0] auto_out_a_mem_0_param = 3'h0; // @[AsyncCrossing.scala:23:9] wire [2:0] auto_out_b_mem_0_opcode = 3'h0; // @[AsyncCrossing.scala:23:9] wire [2:0] auto_out_c_mem_0_opcode = 3'h0; // @[AsyncCrossing.scala:23:9] wire [2:0] auto_out_c_mem_0_param = 3'h0; // @[AsyncCrossing.scala:23:9] wire nodeIn_a_ready; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_a_bits_param = 3'h0; // @[MixedNode.scala:551:17] wire [2:0] nodeOut_a_mem_0_param = 3'h0; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_b_mem_0_opcode = 3'h0; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_c_mem_0_opcode = 3'h0; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_c_mem_0_param = 3'h0; // @[MixedNode.scala:542:17] wire nodeIn_a_valid = auto_in_a_valid_0; // @[AsyncCrossing.scala:23:9] wire [2:0] nodeIn_a_bits_opcode = auto_in_a_bits_opcode_0; // @[AsyncCrossing.scala:23:9] wire [8:0] nodeIn_a_bits_address = auto_in_a_bits_address_0; // @[AsyncCrossing.scala:23:9] wire [31:0] nodeIn_a_bits_data = auto_in_a_bits_data_0; // @[AsyncCrossing.scala:23:9] wire nodeIn_d_ready = auto_in_d_ready_0; // @[AsyncCrossing.scala:23:9] wire nodeIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] nodeIn_d_bits_param; // @[MixedNode.scala:551:17] wire [1:0] nodeIn_d_bits_size; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_source; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_sink; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_denied; // @[MixedNode.scala:551:17] wire [31:0] nodeIn_d_bits_data; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_corrupt; // @[MixedNode.scala:551:17] wire [2:0] nodeOut_a_mem_0_opcode; // @[MixedNode.scala:542:17] wire [8:0] nodeOut_a_mem_0_address; // @[MixedNode.scala:542:17] wire [31:0] nodeOut_a_mem_0_data; // @[MixedNode.scala:542:17] wire nodeOut_a_ridx = auto_out_a_ridx_0; // @[AsyncCrossing.scala:23:9] wire nodeOut_a_widx; // @[MixedNode.scala:542:17] wire nodeOut_a_safe_ridx_valid = auto_out_a_safe_ridx_valid_0; // @[AsyncCrossing.scala:23:9] wire nodeOut_a_safe_widx_valid; // @[MixedNode.scala:542:17] wire nodeOut_a_safe_source_reset_n; // @[MixedNode.scala:542:17] wire nodeOut_a_safe_sink_reset_n = auto_out_a_safe_sink_reset_n_0; // @[AsyncCrossing.scala:23:9] wire [2:0] nodeOut_d_mem_0_opcode = auto_out_d_mem_0_opcode_0; // @[AsyncCrossing.scala:23:9] wire [1:0] nodeOut_d_mem_0_size = auto_out_d_mem_0_size_0; // @[AsyncCrossing.scala:23:9] wire nodeOut_d_mem_0_source = auto_out_d_mem_0_source_0; // @[AsyncCrossing.scala:23:9] wire [31:0] nodeOut_d_mem_0_data = auto_out_d_mem_0_data_0; // @[AsyncCrossing.scala:23:9] wire nodeOut_d_ridx; // @[MixedNode.scala:542:17] wire nodeOut_d_widx = auto_out_d_widx_0; // @[AsyncCrossing.scala:23:9] wire nodeOut_d_safe_ridx_valid; // @[MixedNode.scala:542:17] wire nodeOut_d_safe_widx_valid = auto_out_d_safe_widx_valid_0; // @[AsyncCrossing.scala:23:9] wire nodeOut_d_safe_source_reset_n = auto_out_d_safe_source_reset_n_0; // @[AsyncCrossing.scala:23:9] wire nodeOut_d_safe_sink_reset_n; // @[MixedNode.scala:542:17] wire auto_in_a_ready_0; // @[AsyncCrossing.scala:23:9] wire [2:0] auto_in_d_bits_opcode_0; // @[AsyncCrossing.scala:23:9] wire [1:0] auto_in_d_bits_param_0; // @[AsyncCrossing.scala:23:9] wire [1:0] auto_in_d_bits_size_0; // @[AsyncCrossing.scala:23:9] wire auto_in_d_bits_source_0; // @[AsyncCrossing.scala:23:9] wire auto_in_d_bits_sink_0; // @[AsyncCrossing.scala:23:9] wire auto_in_d_bits_denied_0; // @[AsyncCrossing.scala:23:9] wire [31:0] auto_in_d_bits_data_0; // @[AsyncCrossing.scala:23:9] wire auto_in_d_bits_corrupt_0; // @[AsyncCrossing.scala:23:9] wire auto_in_d_valid_0; // @[AsyncCrossing.scala:23:9] wire [2:0] auto_out_a_mem_0_opcode_0; // @[AsyncCrossing.scala:23:9] wire [8:0] auto_out_a_mem_0_address_0; // @[AsyncCrossing.scala:23:9] wire [31:0] auto_out_a_mem_0_data_0; // @[AsyncCrossing.scala:23:9] wire auto_out_a_safe_widx_valid_0; // @[AsyncCrossing.scala:23:9] wire auto_out_a_safe_source_reset_n_0; // @[AsyncCrossing.scala:23:9] wire auto_out_a_widx_0; // @[AsyncCrossing.scala:23:9] wire auto_out_d_safe_ridx_valid_0; // @[AsyncCrossing.scala:23:9] wire auto_out_d_safe_sink_reset_n_0; // @[AsyncCrossing.scala:23:9] wire auto_out_d_ridx_0; // @[AsyncCrossing.scala:23:9] assign auto_in_a_ready_0 = nodeIn_a_ready; // @[AsyncCrossing.scala:23:9] assign auto_in_d_valid_0 = nodeIn_d_valid; // @[AsyncCrossing.scala:23:9] assign auto_in_d_bits_opcode_0 = nodeIn_d_bits_opcode; // @[AsyncCrossing.scala:23:9] assign auto_in_d_bits_param_0 = nodeIn_d_bits_param; // @[AsyncCrossing.scala:23:9] assign auto_in_d_bits_size_0 = nodeIn_d_bits_size; // @[AsyncCrossing.scala:23:9] assign auto_in_d_bits_source_0 = nodeIn_d_bits_source; // @[AsyncCrossing.scala:23:9] assign auto_in_d_bits_sink_0 = nodeIn_d_bits_sink; // @[AsyncCrossing.scala:23:9] assign auto_in_d_bits_denied_0 = nodeIn_d_bits_denied; // @[AsyncCrossing.scala:23:9] assign auto_in_d_bits_data_0 = nodeIn_d_bits_data; // @[AsyncCrossing.scala:23:9] assign auto_in_d_bits_corrupt_0 = nodeIn_d_bits_corrupt; // @[AsyncCrossing.scala:23:9] assign auto_out_a_mem_0_opcode_0 = nodeOut_a_mem_0_opcode; // @[AsyncCrossing.scala:23:9] assign auto_out_a_mem_0_address_0 = nodeOut_a_mem_0_address; // @[AsyncCrossing.scala:23:9] assign auto_out_a_mem_0_data_0 = nodeOut_a_mem_0_data; // @[AsyncCrossing.scala:23:9] assign auto_out_a_widx_0 = nodeOut_a_widx; // @[AsyncCrossing.scala:23:9] assign auto_out_a_safe_widx_valid_0 = nodeOut_a_safe_widx_valid; // @[AsyncCrossing.scala:23:9] assign auto_out_a_safe_source_reset_n_0 = nodeOut_a_safe_source_reset_n; // @[AsyncCrossing.scala:23:9] assign auto_out_d_ridx_0 = nodeOut_d_ridx; // @[AsyncCrossing.scala:23:9] assign auto_out_d_safe_ridx_valid_0 = nodeOut_d_safe_ridx_valid; // @[AsyncCrossing.scala:23:9] assign auto_out_d_safe_sink_reset_n_0 = nodeOut_d_safe_sink_reset_n; // @[AsyncCrossing.scala:23:9] TLMonitor_39 monitor ( // @[Nodes.scala:27:25] .clock (clock), .reset (reset), .io_in_a_ready (nodeIn_a_ready), // @[MixedNode.scala:551:17] .io_in_a_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17] .io_in_a_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17] .io_in_a_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17] .io_in_a_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17] .io_in_d_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17] .io_in_d_valid (nodeIn_d_valid), // @[MixedNode.scala:551:17] .io_in_d_bits_opcode (nodeIn_d_bits_opcode), // @[MixedNode.scala:551:17] .io_in_d_bits_param (nodeIn_d_bits_param), // @[MixedNode.scala:551:17] .io_in_d_bits_size (nodeIn_d_bits_size), // @[MixedNode.scala:551:17] .io_in_d_bits_source (nodeIn_d_bits_source), // @[MixedNode.scala:551:17] .io_in_d_bits_sink (nodeIn_d_bits_sink), // @[MixedNode.scala:551:17] .io_in_d_bits_denied (nodeIn_d_bits_denied), // @[MixedNode.scala:551:17] .io_in_d_bits_data (nodeIn_d_bits_data), // @[MixedNode.scala:551:17] .io_in_d_bits_corrupt (nodeIn_d_bits_corrupt) // @[MixedNode.scala:551:17] ); // @[Nodes.scala:27:25] AsyncQueueSource_TLBundleA_a9d32s1k1z2u nodeOut_a_source ( // @[AsyncQueue.scala:220:24] .clock (clock), .reset (reset), .io_enq_ready (nodeIn_a_ready), .io_enq_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17] .io_enq_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17] .io_enq_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17] .io_enq_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17] .io_async_mem_0_opcode (nodeOut_a_mem_0_opcode), .io_async_mem_0_address (nodeOut_a_mem_0_address), .io_async_mem_0_data (nodeOut_a_mem_0_data), .io_async_ridx (nodeOut_a_ridx), // @[MixedNode.scala:542:17] .io_async_widx (nodeOut_a_widx), .io_async_safe_ridx_valid (nodeOut_a_safe_ridx_valid), // @[MixedNode.scala:542:17] .io_async_safe_widx_valid (nodeOut_a_safe_widx_valid), .io_async_safe_source_reset_n (nodeOut_a_safe_source_reset_n), .io_async_safe_sink_reset_n (nodeOut_a_safe_sink_reset_n) // @[MixedNode.scala:542:17] ); // @[AsyncQueue.scala:220:24] AsyncQueueSink_TLBundleD_a9d32s1k1z2u nodeIn_d_sink ( // @[AsyncQueue.scala:211:22] .clock (clock), .reset (reset), .io_deq_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17] .io_deq_valid (nodeIn_d_valid), .io_deq_bits_opcode (nodeIn_d_bits_opcode), .io_deq_bits_param (nodeIn_d_bits_param), .io_deq_bits_size (nodeIn_d_bits_size), .io_deq_bits_source (nodeIn_d_bits_source), .io_deq_bits_sink (nodeIn_d_bits_sink), .io_deq_bits_denied (nodeIn_d_bits_denied), .io_deq_bits_data (nodeIn_d_bits_data), .io_deq_bits_corrupt (nodeIn_d_bits_corrupt), .io_async_mem_0_opcode (nodeOut_d_mem_0_opcode), // @[MixedNode.scala:542:17] .io_async_mem_0_size (nodeOut_d_mem_0_size), // @[MixedNode.scala:542:17] .io_async_mem_0_source (nodeOut_d_mem_0_source), // @[MixedNode.scala:542:17] .io_async_mem_0_data (nodeOut_d_mem_0_data), // @[MixedNode.scala:542:17] .io_async_ridx (nodeOut_d_ridx), .io_async_widx (nodeOut_d_widx), // @[MixedNode.scala:542:17] .io_async_safe_ridx_valid (nodeOut_d_safe_ridx_valid), .io_async_safe_widx_valid (nodeOut_d_safe_widx_valid), // @[MixedNode.scala:542:17] .io_async_safe_source_reset_n (nodeOut_d_safe_source_reset_n), // @[MixedNode.scala:542:17] .io_async_safe_sink_reset_n (nodeOut_d_safe_sink_reset_n) ); // @[AsyncQueue.scala:211:22] assign auto_in_a_ready = auto_in_a_ready_0; // @[AsyncCrossing.scala:23:9] assign auto_in_d_valid = auto_in_d_valid_0; // @[AsyncCrossing.scala:23:9] assign auto_in_d_bits_opcode = auto_in_d_bits_opcode_0; // @[AsyncCrossing.scala:23:9] assign auto_in_d_bits_param = auto_in_d_bits_param_0; // @[AsyncCrossing.scala:23:9] assign auto_in_d_bits_size = auto_in_d_bits_size_0; // @[AsyncCrossing.scala:23:9] assign auto_in_d_bits_source = auto_in_d_bits_source_0; // @[AsyncCrossing.scala:23:9] assign auto_in_d_bits_sink = auto_in_d_bits_sink_0; // @[AsyncCrossing.scala:23:9] assign auto_in_d_bits_denied = auto_in_d_bits_denied_0; // @[AsyncCrossing.scala:23:9] assign auto_in_d_bits_data = auto_in_d_bits_data_0; // @[AsyncCrossing.scala:23:9] assign auto_in_d_bits_corrupt = auto_in_d_bits_corrupt_0; // @[AsyncCrossing.scala:23:9] assign auto_out_a_mem_0_opcode = auto_out_a_mem_0_opcode_0; // @[AsyncCrossing.scala:23:9] assign auto_out_a_mem_0_address = auto_out_a_mem_0_address_0; // @[AsyncCrossing.scala:23:9] assign auto_out_a_mem_0_data = auto_out_a_mem_0_data_0; // @[AsyncCrossing.scala:23:9] assign auto_out_a_widx = auto_out_a_widx_0; // @[AsyncCrossing.scala:23:9] assign auto_out_a_safe_widx_valid = auto_out_a_safe_widx_valid_0; // @[AsyncCrossing.scala:23:9] assign auto_out_a_safe_source_reset_n = auto_out_a_safe_source_reset_n_0; // @[AsyncCrossing.scala:23:9] assign auto_out_d_ridx = auto_out_d_ridx_0; // @[AsyncCrossing.scala:23:9] assign auto_out_d_safe_ridx_valid = auto_out_d_safe_ridx_valid_0; // @[AsyncCrossing.scala:23:9] assign auto_out_d_safe_sink_reset_n = auto_out_d_safe_sink_reset_n_0; // @[AsyncCrossing.scala:23:9] endmodule
Generate the Verilog code corresponding to the following Chisel files. File util.scala: //**************************************************************************** // Copyright (c) 2015 - 2019, The Regents of the University of California (Regents). // All Rights Reserved. See LICENSE and LICENSE.SiFive for license details. //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ // Utility Functions //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ package boom.v4.util import chisel3._ import chisel3.util._ import freechips.rocketchip.rocket.Instructions._ import freechips.rocketchip.rocket._ import freechips.rocketchip.util.{Str} import org.chipsalliance.cde.config.{Parameters} import freechips.rocketchip.tile.{TileKey} import boom.v4.common.{MicroOp} import boom.v4.exu.{BrUpdateInfo} / * Object to XOR fold a input register of fullLength into a compressedLength. / object Fold { def apply(input: UInt, compressedLength: Int, fullLength: Int): UInt = { val clen = compressedLength val hlen = fullLength if (hlen <= clen) { input } else { var res = 0.U(clen.W) var remaining = input.asUInt for (i <- 0 to hlen-1 by clen) { val len = if (i + clen > hlen ) (hlen - i) else clen require(len > 0) res = res(clen-1,0) ^ remaining(len-1,0) remaining = remaining >> len.U } res } } } /* * Object to check if MicroOp was killed due to a branch mispredict. * Uses "Fast" branch masks / object IsKilledByBranch { def apply(brupdate: BrUpdateInfo, flush: Bool, uop: MicroOp): Bool = { return apply(brupdate, flush, uop.br_mask) } def apply(brupdate: BrUpdateInfo, flush: Bool, uop_mask: UInt): Bool = { return maskMatch(brupdate.b1.mispredict_mask, uop_mask) \|\| flush } def apply[T <: boom.v4.common.HasBoomUOP](brupdate: BrUpdateInfo, flush: Bool, bundle: T): Bool = { return apply(brupdate, flush, bundle.uop) } def apply[T <: boom.v4.common.HasBoomUOP](brupdate: BrUpdateInfo, flush: Bool, bundle: Valid[T]): Bool = { return apply(brupdate, flush, bundle.bits) } } /* * Object to return new MicroOp with a new BR mask given a MicroOp mask * and old BR mask. / object GetNewUopAndBrMask { def apply(uop: MicroOp, brupdate: BrUpdateInfo) (implicit p: Parameters): MicroOp = { val newuop = WireInit(uop) newuop.br_mask := uop.br_mask & ~brupdate.b1.resolve_mask newuop } } /* * Object to return a BR mask given a MicroOp mask and old BR mask. / object GetNewBrMask { def apply(brupdate: BrUpdateInfo, uop: MicroOp): UInt = { return uop.br_mask & ~brupdate.b1.resolve_mask } def apply(brupdate: BrUpdateInfo, br_mask: UInt): UInt = { return br_mask & ~brupdate.b1.resolve_mask } } object UpdateBrMask { def apply(brupdate: BrUpdateInfo, uop: MicroOp): MicroOp = { val out = WireInit(uop) out.br_mask := GetNewBrMask(brupdate, uop) out } def apply[T <: boom.v4.common.HasBoomUOP](brupdate: BrUpdateInfo, bundle: T): T = { val out = WireInit(bundle) out.uop.br_mask := GetNewBrMask(brupdate, bundle.uop.br_mask) out } def apply[T <: boom.v4.common.HasBoomUOP](brupdate: BrUpdateInfo, flush: Bool, bundle: Valid[T]): Valid[T] = { val out = WireInit(bundle) out.bits.uop.br_mask := GetNewBrMask(brupdate, bundle.bits.uop.br_mask) out.valid := bundle.valid && !IsKilledByBranch(brupdate, flush, bundle.bits.uop.br_mask) out } } /* * Object to check if at least 1 bit matches in two masks / object maskMatch { def apply(msk1: UInt, msk2: UInt): Bool = (msk1 & msk2) =/= 0.U } /* * Object to clear one bit in a mask given an index / object clearMaskBit { def apply(msk: UInt, idx: UInt): UInt = (msk & ~(1.U << idx))(msk.getWidth-1, 0) } /* * Object to shift a register over by one bit and concat a new one / object PerformShiftRegister { def apply(reg_val: UInt, new_bit: Bool): UInt = { reg_val := Cat(reg_val(reg_val.getWidth-1, 0).asUInt, new_bit.asUInt).asUInt reg_val } } /* * Object to shift a register over by one bit, wrapping the top bit around to the bottom * (XOR'ed with a new-bit), and evicting a bit at index HLEN. * This is used to simulate a longer HLEN-width shift register that is folded * down to a compressed CLEN. / object PerformCircularShiftRegister { def apply(csr: UInt, new_bit: Bool, evict_bit: Bool, hlen: Int, clen: Int): UInt = { val carry = csr(clen-1) val newval = Cat(csr, new_bit ^ carry) ^ (evict_bit << (hlen % clen).U) newval } } /* * Object to increment an input value, wrapping it if * necessary. / object WrapAdd { // "n" is the number of increments, so we wrap at n-1. def apply(value: UInt, amt: UInt, n: Int): UInt = { if (isPow2(n)) { (value + amt)(log2Ceil(n)-1,0) } else { val sum = Cat(0.U(1.W), value) + Cat(0.U(1.W), amt) Mux(sum >= n.U, sum - n.U, sum) } } } /* * Object to decrement an input value, wrapping it if * necessary. / object WrapSub { // "n" is the number of increments, so we wrap to n-1. def apply(value: UInt, amt: Int, n: Int): UInt = { if (isPow2(n)) { (value - amt.U)(log2Ceil(n)-1,0) } else { val v = Cat(0.U(1.W), value) val b = Cat(0.U(1.W), amt.U) Mux(value >= amt.U, value - amt.U, n.U - amt.U + value) } } } /* * Object to increment an input value, wrapping it if * necessary. / object WrapInc { // "n" is the number of increments, so we wrap at n-1. def apply(value: UInt, n: Int): UInt = { if (isPow2(n)) { (value + 1.U)(log2Ceil(n)-1,0) } else { val wrap = (value === (n-1).U) Mux(wrap, 0.U, value + 1.U) } } } /* * Object to decrement an input value, wrapping it if * necessary. / object WrapDec { // "n" is the number of increments, so we wrap at n-1. def apply(value: UInt, n: Int): UInt = { if (isPow2(n)) { (value - 1.U)(log2Ceil(n)-1,0) } else { val wrap = (value === 0.U) Mux(wrap, (n-1).U, value - 1.U) } } } /* * Object to mask off lower bits of a PC to align to a "b" * Byte boundary. / object AlignPCToBoundary { def apply(pc: UInt, b: Int): UInt = { // Invert for scenario where pc longer than b // (which would clear all bits above size(b)). ~(~pc \| (b-1).U) } } /* * Object to rotate a signal left by one / object RotateL1 { def apply(signal: UInt): UInt = { val w = signal.getWidth val out = Cat(signal(w-2,0), signal(w-1)) return out } } /* * Object to sext a value to a particular length. / object Sext { def apply(x: UInt, length: Int): UInt = { if (x.getWidth == length) return x else return Cat(Fill(length-x.getWidth, x(x.getWidth-1)), x) } } /* * Object to translate from BOOM's special "packed immediate" to a 32b signed immediate * Asking for U-type gives it shifted up 12 bits. / object ImmGen { import boom.v4.common.{LONGEST_IMM_SZ, IS_B, IS_I, IS_J, IS_S, IS_U, IS_N} def apply(i: UInt, isel: UInt): UInt = { val ip = Mux(isel === IS_N, 0.U(LONGEST_IMM_SZ.W), i) val sign = ip(LONGEST_IMM_SZ-1).asSInt val i30_20 = Mux(isel === IS_U, ip(18,8).asSInt, sign) val i19_12 = Mux(isel === IS_U \|\| isel === IS_J, ip(7,0).asSInt, sign) val i11 = Mux(isel === IS_U, 0.S, Mux(isel === IS_J \|\| isel === IS_B, ip(8).asSInt, sign)) val i10_5 = Mux(isel === IS_U, 0.S, ip(18,14).asSInt) val i4_1 = Mux(isel === IS_U, 0.S, ip(13,9).asSInt) val i0 = Mux(isel === IS_S \|\| isel === IS_I, ip(8).asSInt, 0.S) return Cat(sign, i30_20, i19_12, i11, i10_5, i4_1, i0) } } /* * Object to see if an instruction is a JALR. / object DebugIsJALR { def apply(inst: UInt): Bool = { // TODO Chisel not sure why this won't compile // val is_jalr = rocket.DecodeLogic(inst, List(Bool(false)), // Array( // JALR -> Bool(true))) inst(6,0) === "b1100111".U } } /* * Object to take an instruction and output its branch or jal target. Only used * for a debug assert (no where else would we jump straight from instruction * bits to a target). / object DebugGetBJImm { def apply(inst: UInt): UInt = { // TODO Chisel not sure why this won't compile //val csignals = //rocket.DecodeLogic(inst, // List(Bool(false), Bool(false)), // Array( // BEQ -> List(Bool(true ), Bool(false)), // BNE -> List(Bool(true ), Bool(false)), // BGE -> List(Bool(true ), Bool(false)), // BGEU -> List(Bool(true ), Bool(false)), // BLT -> List(Bool(true ), Bool(false)), // BLTU -> List(Bool(true ), Bool(false)) // )) //val is_br :: nothing :: Nil = csignals val is_br = (inst(6,0) === "b1100011".U) val br_targ = Cat(Fill(12, inst(31)), Fill(8,inst(31)), inst(7), inst(30,25), inst(11,8), 0.U(1.W)) val jal_targ= Cat(Fill(12, inst(31)), inst(19,12), inst(20), inst(30,25), inst(24,21), 0.U(1.W)) Mux(is_br, br_targ, jal_targ) } } /* * Object to return the lowest bit position after the head. / object AgePriorityEncoder { def apply(in: Seq[Bool], head: UInt): UInt = { val n = in.size val width = log2Ceil(in.size) val n_padded = 1 << width val temp_vec = (0 until n_padded).map(i => if (i < n) in(i) && i.U >= head else false.B) ++ in val idx = PriorityEncoder(temp_vec) idx(width-1, 0) //discard msb } } /* * Object to determine whether queue * index i0 is older than index i1. / object IsOlder { def apply(i0: UInt, i1: UInt, head: UInt) = ((i0 < i1) ^ (i0 < head) ^ (i1 < head)) } object IsYoungerMask { def apply(i: UInt, head: UInt, n: Integer): UInt = { val hi_mask = ~MaskLower(UIntToOH(i)(n-1,0)) val lo_mask = ~MaskUpper(UIntToOH(head)(n-1,0)) Mux(i < head, hi_mask & lo_mask, hi_mask \| lo_mask)(n-1,0) } } /* * Set all bits at or below the highest order '1'. / object MaskLower { def apply(in: UInt) = { val n = in.getWidth (0 until n).map(i => in >> i.U).reduce(_\|_) } } /* * Set all bits at or above the lowest order '1'. / object MaskUpper { def apply(in: UInt) = { val n = in.getWidth (0 until n).map(i => (in << i.U)(n-1,0)).reduce(_\|_) } } /* * Transpose a matrix of Chisel Vecs. / object Transpose { def apply[T <: chisel3.Data](in: Vec[Vec[T]]) = { val n = in(0).size VecInit((0 until n).map(i => VecInit(in.map(row => row(i))))) } } /* * N-wide one-hot priority encoder. / object SelectFirstN { def apply(in: UInt, n: Int) = { val sels = Wire(Vec(n, UInt(in.getWidth.W))) var mask = in for (i <- 0 until n) { sels(i) := PriorityEncoderOH(mask) mask = mask & ~sels(i) } sels } } /* * Connect the first k of n valid input interfaces to k output interfaces. / class Compactor[T <: chisel3.Data](n: Int, k: Int, gen: T) extends Module { require(n >= k) val io = IO(new Bundle { val in = Vec(n, Flipped(DecoupledIO(gen))) val out = Vec(k, DecoupledIO(gen)) }) if (n == k) { io.out <> io.in } else { val counts = io.in.map(_.valid).scanLeft(1.U(k.W)) ((c,e) => Mux(e, (c<<1)(k-1,0), c)) val sels = Transpose(VecInit(counts map (c => VecInit(c.asBools)))) map (col => (col zip io.in.map(_.valid)) map {case (c,v) => c && v}) val in_readys = counts map (row => (row.asBools zip io.out.map(_.ready)) map {case (c,r) => c && r} reduce (_\|\|_)) val out_valids = sels map (col => col.reduce(_\|\|_)) val out_data = sels map (s => Mux1H(s, io.in.map(_.bits))) in_readys zip io.in foreach {case (r,i) => i.ready := r} out_valids zip out_data zip io.out foreach {case ((v,d),o) => o.valid := v; o.bits := d} } } /* * Create a queue that can be killed with a branch kill signal. * Assumption: enq.valid only high if not killed by branch (so don't check IsKilled on io.enq). / class BranchKillableQueue[T <: boom.v4.common.HasBoomUOP](gen: T, entries: Int, flush_fn: boom.v4.common.MicroOp => Bool = u => true.B, fastDeq: Boolean = false) (implicit p: org.chipsalliance.cde.config.Parameters) extends boom.v4.common.BoomModule()(p) with boom.v4.common.HasBoomCoreParameters { val io = IO(new Bundle { val enq = Flipped(Decoupled(gen)) val deq = Decoupled(gen) val brupdate = Input(new BrUpdateInfo()) val flush = Input(Bool()) val empty = Output(Bool()) val count = Output(UInt(log2Ceil(entries).W)) }) if (fastDeq && entries > 1) { // Pipeline dequeue selection so the mux gets an entire cycle val main = Module(new BranchKillableQueue(gen, entries-1, flush_fn, false)) val out_reg = Reg(gen) val out_valid = RegInit(false.B) val out_uop = Reg(new MicroOp) main.io.enq <> io.enq main.io.brupdate := io.brupdate main.io.flush := io.flush io.empty := main.io.empty && !out_valid io.count := main.io.count + out_valid io.deq.valid := out_valid io.deq.bits := out_reg io.deq.bits.uop := out_uop out_uop := UpdateBrMask(io.brupdate, out_uop) out_valid := out_valid && !IsKilledByBranch(io.brupdate, false.B, out_uop) && !(io.flush && flush_fn(out_uop)) main.io.deq.ready := false.B when (io.deq.fire \|\| !out_valid) { out_valid := main.io.deq.valid && !IsKilledByBranch(io.brupdate, false.B, main.io.deq.bits.uop) && !(io.flush && flush_fn(main.io.deq.bits.uop)) out_reg := main.io.deq.bits out_uop := UpdateBrMask(io.brupdate, main.io.deq.bits.uop) main.io.deq.ready := true.B } } else { val ram = Mem(entries, gen) val valids = RegInit(VecInit(Seq.fill(entries) {false.B})) val uops = Reg(Vec(entries, new MicroOp)) val enq_ptr = Counter(entries) val deq_ptr = Counter(entries) val maybe_full = RegInit(false.B) val ptr_match = enq_ptr.value === deq_ptr.value io.empty := ptr_match && !maybe_full val full = ptr_match && maybe_full val do_enq = WireInit(io.enq.fire && !IsKilledByBranch(io.brupdate, false.B, io.enq.bits.uop) && !(io.flush && flush_fn(io.enq.bits.uop))) val do_deq = WireInit((io.deq.ready \|\| !valids(deq_ptr.value)) && !io.empty) for (i <- 0 until entries) { val mask = uops(i).br_mask val uop = uops(i) valids(i) := valids(i) && !IsKilledByBranch(io.brupdate, false.B, mask) && !(io.flush && flush_fn(uop)) when (valids(i)) { uops(i).br_mask := GetNewBrMask(io.brupdate, mask) } } when (do_enq) { ram(enq_ptr.value) := io.enq.bits valids(enq_ptr.value) := true.B uops(enq_ptr.value) := io.enq.bits.uop uops(enq_ptr.value).br_mask := GetNewBrMask(io.brupdate, io.enq.bits.uop) enq_ptr.inc() } when (do_deq) { valids(deq_ptr.value) := false.B deq_ptr.inc() } when (do_enq =/= do_deq) { maybe_full := do_enq } io.enq.ready := !full val out = Wire(gen) out := ram(deq_ptr.value) out.uop := uops(deq_ptr.value) io.deq.valid := !io.empty && valids(deq_ptr.value) io.deq.bits := out val ptr_diff = enq_ptr.value - deq_ptr.value if (isPow2(entries)) { io.count := Cat(maybe_full && ptr_match, ptr_diff) } else { io.count := Mux(ptr_match, Mux(maybe_full, entries.asUInt, 0.U), Mux(deq_ptr.value > enq_ptr.value, entries.asUInt + ptr_diff, ptr_diff)) } } } // ------------------------------------------ // Printf helper functions // ------------------------------------------ object BoolToChar { /* * Take in a Chisel Bool and convert it into a Str * based on the Chars given * * @param c_bool Chisel Bool * @param trueChar Scala Char if bool is true * @param falseChar Scala Char if bool is false * @return UInt ASCII Char for "trueChar" or "falseChar" / def apply(c_bool: Bool, trueChar: Char, falseChar: Char = '-'): UInt = { Mux(c_bool, Str(trueChar), Str(falseChar)) } } object CfiTypeToChars { /* * Get a Vec of Strs that can be used for printing * * @param cfi_type specific cfi type * @return Vec of Strs (must be indexed to get specific char) / def apply(cfi_type: UInt) = { val strings = Seq("----", "BR ", "JAL ", "JALR") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(cfi_type) } } object BpdTypeToChars { /* * Get a Vec of Strs that can be used for printing * * @param bpd_type specific bpd type * @return Vec of Strs (must be indexed to get specific char) / def apply(bpd_type: UInt) = { val strings = Seq("BR ", "JUMP", "----", "RET ", "----", "CALL", "----", "----") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(bpd_type) } } object RobTypeToChars { /* * Get a Vec of Strs that can be used for printing * * @param rob_type specific rob type * @return Vec of Strs (must be indexed to get specific char) / def apply(rob_type: UInt) = { val strings = Seq("RST", "NML", "RBK", " WT") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(rob_type) } } object XRegToChars { /* * Get a Vec of Strs that can be used for printing * * @param xreg specific register number * @return Vec of Strs (must be indexed to get specific char) / def apply(xreg: UInt) = { val strings = Seq(" x0", " ra", " sp", " gp", " tp", " t0", " t1", " t2", " s0", " s1", " a0", " a1", " a2", " a3", " a4", " a5", " a6", " a7", " s2", " s3", " s4", " s5", " s6", " s7", " s8", " s9", "s10", "s11", " t3", " t4", " t5", " t6") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(xreg) } } object FPRegToChars { /* * Get a Vec of Strs that can be used for printing * * @param fpreg specific register number * @return Vec of Strs (must be indexed to get specific char) / def apply(fpreg: UInt) = { val strings = Seq(" ft0", " ft1", " ft2", " ft3", " ft4", " ft5", " ft6", " ft7", " fs0", " fs1", " fa0", " fa1", " fa2", " fa3", " fa4", " fa5", " fa6", " fa7", " fs2", " fs3", " fs4", " fs5", " fs6", " fs7", " fs8", " fs9", "fs10", "fs11", " ft8", " ft9", "ft10", "ft11") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(fpreg) } } object BoomCoreStringPrefix { /* * Add prefix to BOOM strings (currently only adds the hartId) * * @param strs list of strings * @return String combining the list with the prefix per line / def apply(strs: String)(implicit p: Parameters) = { val prefix = "[C" + s"${p(TileKey).tileId}" + "] " strs.map(str => prefix + str + "\n").mkString("") } } class BranchKillablePipeline[T <: boom.v4.common.HasBoomUOP](gen: T, stages: Int) (implicit p: org.chipsalliance.cde.config.Parameters) extends boom.v4.common.BoomModule()(p) with boom.v4.common.HasBoomCoreParameters { val io = IO(new Bundle { val req = Input(Valid(gen)) val flush = Input(Bool()) val brupdate = Input(new BrUpdateInfo) val resp = Output(Vec(stages, Valid(gen))) }) require(stages > 0) val uops = Reg(Vec(stages, Valid(gen))) uops(0).valid := io.req.valid && !IsKilledByBranch(io.brupdate, io.flush, io.req.bits) uops(0).bits := UpdateBrMask(io.brupdate, io.req.bits) for (i <- 1 until stages) { uops(i).valid := uops(i-1).valid && !IsKilledByBranch(io.brupdate, io.flush, uops(i-1).bits) uops(i).bits := UpdateBrMask(io.brupdate, uops(i-1).bits) } for (i <- 0 until stages) { when (reset.asBool) { uops(i).valid := false.B } } io.resp := uops } File issue-slot.scala: //****************************************************************************** // Copyright (c) 2015 - 2018, The Regents of the University of California (Regents). // All Rights Reserved. See LICENSE and LICENSE.SiFive for license details. //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ // RISCV Processor Issue Slot Logic //-------------------------------------------------------------------------- //------------------------------------------------------------------------------ // // Note: stores (and AMOs) are "broken down" into 2 uops, but stored within a single issue-slot. // TODO XXX make a separate issueSlot for MemoryIssueSlots, and only they break apart stores. // TODO Disable ldspec for FP queue. package boom.v4.exu import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.Parameters import boom.v4.common._ import boom.v4.util._ class IssueSlotIO(val numWakeupPorts: Int)(implicit p: Parameters) extends BoomBundle { val valid = Output(Bool()) val will_be_valid = Output(Bool()) // TODO code review, do we need this signal so explicitely? val request = Output(Bool()) val grant = Input(Bool()) val iss_uop = Output(new MicroOp()) val in_uop = Input(Valid(new MicroOp())) // if valid, this WILL overwrite an entry! val out_uop = Output(new MicroOp()) val brupdate = Input(new BrUpdateInfo()) val kill = Input(Bool()) // pipeline flush val clear = Input(Bool()) // entry being moved elsewhere (not mutually exclusive with grant) val squash_grant = Input(Bool()) val wakeup_ports = Flipped(Vec(numWakeupPorts, Valid(new Wakeup))) val pred_wakeup_port = Flipped(Valid(UInt(log2Ceil(ftqSz).W))) val child_rebusys = Input(UInt(aluWidth.W)) } class IssueSlot(val numWakeupPorts: Int, val isMem: Boolean, val isFp: Boolean)(implicit p: Parameters) extends BoomModule { val io = IO(new IssueSlotIO(numWakeupPorts)) val slot_valid = RegInit(false.B) val slot_uop = Reg(new MicroOp()) val next_valid = WireInit(slot_valid) val next_uop = WireInit(UpdateBrMask(io.brupdate, slot_uop)) val killed = IsKilledByBranch(io.brupdate, io.kill, slot_uop) io.valid := slot_valid io.out_uop := next_uop io.will_be_valid := next_valid && !killed when (io.kill) { slot_valid := false.B } .elsewhen (io.in_uop.valid) { slot_valid := true.B } .elsewhen (io.clear) { slot_valid := false.B } .otherwise { slot_valid := next_valid && !killed } when (io.in_uop.valid) { slot_uop := io.in_uop.bits assert (!slot_valid \|\| io.clear \|\| io.kill) } .otherwise { slot_uop := next_uop } // Wakeups next_uop.iw_p1_bypass_hint := false.B next_uop.iw_p2_bypass_hint := false.B next_uop.iw_p3_bypass_hint := false.B next_uop.iw_p1_speculative_child := 0.U next_uop.iw_p2_speculative_child := 0.U val rebusied_prs1 = WireInit(false.B) val rebusied_prs2 = WireInit(false.B) val rebusied = rebusied_prs1 \|\| rebusied_prs2 val prs1_matches = io.wakeup_ports.map { w => w.bits.uop.pdst === slot_uop.prs1 } val prs2_matches = io.wakeup_ports.map { w => w.bits.uop.pdst === slot_uop.prs2 } val prs3_matches = io.wakeup_ports.map { w => w.bits.uop.pdst === slot_uop.prs3 } val prs1_wakeups = (io.wakeup_ports zip prs1_matches).map { case (w,m) => w.valid && m } val prs2_wakeups = (io.wakeup_ports zip prs2_matches).map { case (w,m) => w.valid && m } val prs3_wakeups = (io.wakeup_ports zip prs3_matches).map { case (w,m) => w.valid && m } val prs1_rebusys = (io.wakeup_ports zip prs1_matches).map { case (w,m) => w.bits.rebusy && m } val prs2_rebusys = (io.wakeup_ports zip prs2_matches).map { case (w,m) => w.bits.rebusy && m } val bypassables = io.wakeup_ports.map { w => w.bits.bypassable } val speculative_masks = io.wakeup_ports.map { w => w.bits.speculative_mask } when (prs1_wakeups.reduce(_\|\|_)) { next_uop.prs1_busy := false.B next_uop.iw_p1_speculative_child := Mux1H(prs1_wakeups, speculative_masks) next_uop.iw_p1_bypass_hint := Mux1H(prs1_wakeups, bypassables) } when ((prs1_rebusys.reduce(_\|\|_) \|\| ((io.child_rebusys & slot_uop.iw_p1_speculative_child) =/= 0.U)) && slot_uop.lrs1_rtype === RT_FIX) { next_uop.prs1_busy := true.B rebusied_prs1 := true.B } when (prs2_wakeups.reduce(_\|\|_)) { next_uop.prs2_busy := false.B next_uop.iw_p2_speculative_child := Mux1H(prs2_wakeups, speculative_masks) next_uop.iw_p2_bypass_hint := Mux1H(prs2_wakeups, bypassables) } when ((prs2_rebusys.reduce(_\|\|_) \|\| ((io.child_rebusys & slot_uop.iw_p2_speculative_child) =/= 0.U)) && slot_uop.lrs2_rtype === RT_FIX) { next_uop.prs2_busy := true.B rebusied_prs2 := true.B } when (prs3_wakeups.reduce(_\|\|_)) { next_uop.prs3_busy := false.B next_uop.iw_p3_bypass_hint := Mux1H(prs3_wakeups, bypassables) } when (io.pred_wakeup_port.valid && io.pred_wakeup_port.bits === slot_uop.ppred) { next_uop.ppred_busy := false.B } val iss_ready = !slot_uop.prs1_busy && !slot_uop.prs2_busy && !(slot_uop.ppred_busy && enableSFBOpt.B) && !(slot_uop.prs3_busy && isFp.B) val agen_ready = (slot_uop.fu_code(FC_AGEN) && !slot_uop.prs1_busy && !(slot_uop.ppred_busy && enableSFBOpt.B) && isMem.B) val dgen_ready = (slot_uop.fu_code(FC_DGEN) && !slot_uop.prs2_busy && !(slot_uop.ppred_busy && enableSFBOpt.B) && isMem.B) io.request := slot_valid && !slot_uop.iw_issued && ( iss_ready \|\| agen_ready \|\| dgen_ready ) io.iss_uop := slot_uop // Update state for current micro-op based on grant next_uop.iw_issued := false.B next_uop.iw_issued_partial_agen := false.B next_uop.iw_issued_partial_dgen := false.B when (io.grant && !io.squash_grant) { next_uop.iw_issued := true.B } if (isMem) { when (slot_uop.fu_code(FC_AGEN) && slot_uop.fu_code(FC_DGEN)) { when (agen_ready) { // Issue the AGEN, next slot entry is a DGEN when (io.grant && !io.squash_grant) { next_uop.iw_issued_partial_agen := true.B } io.iss_uop.fu_code(FC_AGEN) := true.B io.iss_uop.fu_code(FC_DGEN) := false.B } .otherwise { // Issue the DGEN, next slot entry is the AGEN when (io.grant && !io.squash_grant) { next_uop.iw_issued_partial_dgen := true.B } io.iss_uop.fu_code(FC_AGEN) := false.B io.iss_uop.fu_code(FC_DGEN) := true.B io.iss_uop.imm_sel := IS_N io.iss_uop.prs1 := slot_uop.prs2 io.iss_uop.lrs1_rtype := slot_uop.lrs2_rtype io.iss_uop.iw_p1_bypass_hint := slot_uop.iw_p2_bypass_hint } } .elsewhen (slot_uop.fu_code(FC_DGEN)) { io.iss_uop.imm_sel := IS_N io.iss_uop.prs1 := slot_uop.prs2 io.iss_uop.lrs1_rtype := slot_uop.lrs2_rtype io.iss_uop.iw_p1_bypass_hint := slot_uop.iw_p2_bypass_hint } io.iss_uop.lrs2_rtype := RT_X io.iss_uop.prs2 := io.iss_uop.prs1 // helps with DCE } when (slot_valid && slot_uop.iw_issued) { next_valid := rebusied if (isMem) { when (slot_uop.iw_issued_partial_agen) { next_valid := true.B when (!rebusied_prs1) { next_uop.fu_code(FC_AGEN) := false.B next_uop.fu_code(FC_DGEN) := true.B } } .elsewhen (slot_uop.iw_issued_partial_dgen) { next_valid := true.B when (!rebusied_prs2) { next_uop.fu_code(FC_AGEN) := true.B next_uop.fu_code(FC_DGEN) := false.B } } } } }	module IssueSlot_56( // @[issue-slot.scala:49:7] input clock, // @[issue-slot.scala:49:7] input reset, // @[issue-slot.scala:49:7] output io_valid, // @[issue-slot.scala:52:14] output io_will_be_valid, // @[issue-slot.scala:52:14] output io_request, // @[issue-slot.scala:52:14] input io_grant, // @[issue-slot.scala:52:14] output [31:0] io_iss_uop_inst, // @[issue-slot.scala:52:14] output [31:0] io_iss_uop_debug_inst, // @[issue-slot.scala:52:14] output io_iss_uop_is_rvc, // @[issue-slot.scala:52:14] output [39:0] io_iss_uop_debug_pc, // @[issue-slot.scala:52:14] output io_iss_uop_iq_type_0, // @[issue-slot.scala:52:14] output io_iss_uop_iq_type_1, // @[issue-slot.scala:52:14] output io_iss_uop_iq_type_2, // @[issue-slot.scala:52:14] output io_iss_uop_iq_type_3, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_0, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_1, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_2, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_3, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_4, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_5, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_6, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_7, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_8, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_9, // @[issue-slot.scala:52:14] output io_iss_uop_iw_issued, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14] output io_iss_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] output io_iss_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] output io_iss_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_dis_col_sel, // @[issue-slot.scala:52:14] output [15:0] io_iss_uop_br_mask, // @[issue-slot.scala:52:14] output [3:0] io_iss_uop_br_tag, // @[issue-slot.scala:52:14] output [3:0] io_iss_uop_br_type, // @[issue-slot.scala:52:14] output io_iss_uop_is_sfb, // @[issue-slot.scala:52:14] output io_iss_uop_is_fence, // @[issue-slot.scala:52:14] output io_iss_uop_is_fencei, // @[issue-slot.scala:52:14] output io_iss_uop_is_sfence, // @[issue-slot.scala:52:14] output io_iss_uop_is_amo, // @[issue-slot.scala:52:14] output io_iss_uop_is_eret, // @[issue-slot.scala:52:14] output io_iss_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14] output io_iss_uop_is_rocc, // @[issue-slot.scala:52:14] output io_iss_uop_is_mov, // @[issue-slot.scala:52:14] output [4:0] io_iss_uop_ftq_idx, // @[issue-slot.scala:52:14] output io_iss_uop_edge_inst, // @[issue-slot.scala:52:14] output [5:0] io_iss_uop_pc_lob, // @[issue-slot.scala:52:14] output io_iss_uop_taken, // @[issue-slot.scala:52:14] output io_iss_uop_imm_rename, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_imm_sel, // @[issue-slot.scala:52:14] output [4:0] io_iss_uop_pimm, // @[issue-slot.scala:52:14] output [19:0] io_iss_uop_imm_packed, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_op1_sel, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_op2_sel, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_div, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14] output [6:0] io_iss_uop_rob_idx, // @[issue-slot.scala:52:14] output [4:0] io_iss_uop_ldq_idx, // @[issue-slot.scala:52:14] output [4:0] io_iss_uop_stq_idx, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_rxq_idx, // @[issue-slot.scala:52:14] output [6:0] io_iss_uop_pdst, // @[issue-slot.scala:52:14] output [6:0] io_iss_uop_prs1, // @[issue-slot.scala:52:14] output [6:0] io_iss_uop_prs2, // @[issue-slot.scala:52:14] output [6:0] io_iss_uop_prs3, // @[issue-slot.scala:52:14] output [4:0] io_iss_uop_ppred, // @[issue-slot.scala:52:14] output io_iss_uop_prs1_busy, // @[issue-slot.scala:52:14] output io_iss_uop_prs2_busy, // @[issue-slot.scala:52:14] output io_iss_uop_prs3_busy, // @[issue-slot.scala:52:14] output io_iss_uop_ppred_busy, // @[issue-slot.scala:52:14] output [6:0] io_iss_uop_stale_pdst, // @[issue-slot.scala:52:14] output io_iss_uop_exception, // @[issue-slot.scala:52:14] output [63:0] io_iss_uop_exc_cause, // @[issue-slot.scala:52:14] output [4:0] io_iss_uop_mem_cmd, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_mem_size, // @[issue-slot.scala:52:14] output io_iss_uop_mem_signed, // @[issue-slot.scala:52:14] output io_iss_uop_uses_ldq, // @[issue-slot.scala:52:14] output io_iss_uop_uses_stq, // @[issue-slot.scala:52:14] output io_iss_uop_is_unique, // @[issue-slot.scala:52:14] output io_iss_uop_flush_on_commit, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_csr_cmd, // @[issue-slot.scala:52:14] output io_iss_uop_ldst_is_rs1, // @[issue-slot.scala:52:14] output [5:0] io_iss_uop_ldst, // @[issue-slot.scala:52:14] output [5:0] io_iss_uop_lrs1, // @[issue-slot.scala:52:14] output [5:0] io_iss_uop_lrs2, // @[issue-slot.scala:52:14] output [5:0] io_iss_uop_lrs3, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_dst_rtype, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_lrs1_rtype, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_lrs2_rtype, // @[issue-slot.scala:52:14] output io_iss_uop_frs3_en, // @[issue-slot.scala:52:14] output io_iss_uop_fcn_dw, // @[issue-slot.scala:52:14] output [4:0] io_iss_uop_fcn_op, // @[issue-slot.scala:52:14] output io_iss_uop_fp_val, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_fp_rm, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_fp_typ, // @[issue-slot.scala:52:14] output io_iss_uop_xcpt_pf_if, // @[issue-slot.scala:52:14] output io_iss_uop_xcpt_ae_if, // @[issue-slot.scala:52:14] output io_iss_uop_xcpt_ma_if, // @[issue-slot.scala:52:14] output io_iss_uop_bp_debug_if, // @[issue-slot.scala:52:14] output io_iss_uop_bp_xcpt_if, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_debug_fsrc, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_debug_tsrc, // @[issue-slot.scala:52:14] input io_in_uop_valid, // @[issue-slot.scala:52:14] input [31:0] io_in_uop_bits_inst, // @[issue-slot.scala:52:14] input [31:0] io_in_uop_bits_debug_inst, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_rvc, // @[issue-slot.scala:52:14] input [39:0] io_in_uop_bits_debug_pc, // @[issue-slot.scala:52:14] input io_in_uop_bits_iq_type_0, // @[issue-slot.scala:52:14] input io_in_uop_bits_iq_type_1, // @[issue-slot.scala:52:14] input io_in_uop_bits_iq_type_2, // @[issue-slot.scala:52:14] input io_in_uop_bits_iq_type_3, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_0, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_1, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_2, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_3, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_4, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_5, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_6, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_7, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_8, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_9, // @[issue-slot.scala:52:14] input io_in_uop_bits_iw_issued, // @[issue-slot.scala:52:14] input [2:0] io_in_uop_bits_iw_p1_speculative_child, // @[issue-slot.scala:52:14] input [2:0] io_in_uop_bits_iw_p2_speculative_child, // @[issue-slot.scala:52:14] input io_in_uop_bits_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] input io_in_uop_bits_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] input io_in_uop_bits_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] input [2:0] io_in_uop_bits_dis_col_sel, // @[issue-slot.scala:52:14] input [15:0] io_in_uop_bits_br_mask, // @[issue-slot.scala:52:14] input [3:0] io_in_uop_bits_br_tag, // @[issue-slot.scala:52:14] input [3:0] io_in_uop_bits_br_type, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_sfb, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_fence, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_fencei, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_sfence, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_amo, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_eret, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_sys_pc2epc, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_rocc, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_mov, // @[issue-slot.scala:52:14] input [4:0] io_in_uop_bits_ftq_idx, // @[issue-slot.scala:52:14] input io_in_uop_bits_edge_inst, // @[issue-slot.scala:52:14] input [5:0] io_in_uop_bits_pc_lob, // @[issue-slot.scala:52:14] input io_in_uop_bits_taken, // @[issue-slot.scala:52:14] input io_in_uop_bits_imm_rename, // @[issue-slot.scala:52:14] input [2:0] io_in_uop_bits_imm_sel, // @[issue-slot.scala:52:14] input [4:0] io_in_uop_bits_pimm, // @[issue-slot.scala:52:14] input [19:0] io_in_uop_bits_imm_packed, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_op1_sel, // @[issue-slot.scala:52:14] input [2:0] io_in_uop_bits_op2_sel, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_ldst, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_wen, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_ren1, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_ren2, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_ren3, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_swap12, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_swap23, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_fromint, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_toint, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_fma, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_div, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_wflags, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_vec, // @[issue-slot.scala:52:14] input [6:0] io_in_uop_bits_rob_idx, // @[issue-slot.scala:52:14] input [4:0] io_in_uop_bits_ldq_idx, // @[issue-slot.scala:52:14] input [4:0] io_in_uop_bits_stq_idx, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_rxq_idx, // @[issue-slot.scala:52:14] input [6:0] io_in_uop_bits_pdst, // @[issue-slot.scala:52:14] input [6:0] io_in_uop_bits_prs1, // @[issue-slot.scala:52:14] input [6:0] io_in_uop_bits_prs2, // @[issue-slot.scala:52:14] input [6:0] io_in_uop_bits_prs3, // @[issue-slot.scala:52:14] input [4:0] io_in_uop_bits_ppred, // @[issue-slot.scala:52:14] input io_in_uop_bits_prs1_busy, // @[issue-slot.scala:52:14] input io_in_uop_bits_prs2_busy, // @[issue-slot.scala:52:14] input io_in_uop_bits_prs3_busy, // @[issue-slot.scala:52:14] input io_in_uop_bits_ppred_busy, // @[issue-slot.scala:52:14] input [6:0] io_in_uop_bits_stale_pdst, // @[issue-slot.scala:52:14] input io_in_uop_bits_exception, // @[issue-slot.scala:52:14] input [63:0] io_in_uop_bits_exc_cause, // @[issue-slot.scala:52:14] input [4:0] io_in_uop_bits_mem_cmd, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_mem_size, // @[issue-slot.scala:52:14] input io_in_uop_bits_mem_signed, // @[issue-slot.scala:52:14] input io_in_uop_bits_uses_ldq, // @[issue-slot.scala:52:14] input io_in_uop_bits_uses_stq, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_unique, // @[issue-slot.scala:52:14] input io_in_uop_bits_flush_on_commit, // @[issue-slot.scala:52:14] input [2:0] io_in_uop_bits_csr_cmd, // @[issue-slot.scala:52:14] input io_in_uop_bits_ldst_is_rs1, // @[issue-slot.scala:52:14] input [5:0] io_in_uop_bits_ldst, // @[issue-slot.scala:52:14] input [5:0] io_in_uop_bits_lrs1, // @[issue-slot.scala:52:14] input [5:0] io_in_uop_bits_lrs2, // @[issue-slot.scala:52:14] input [5:0] io_in_uop_bits_lrs3, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_dst_rtype, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_lrs1_rtype, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_lrs2_rtype, // @[issue-slot.scala:52:14] input io_in_uop_bits_frs3_en, // @[issue-slot.scala:52:14] input io_in_uop_bits_fcn_dw, // @[issue-slot.scala:52:14] input [4:0] io_in_uop_bits_fcn_op, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_val, // @[issue-slot.scala:52:14] input [2:0] io_in_uop_bits_fp_rm, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_fp_typ, // @[issue-slot.scala:52:14] input io_in_uop_bits_xcpt_pf_if, // @[issue-slot.scala:52:14] input io_in_uop_bits_xcpt_ae_if, // @[issue-slot.scala:52:14] input io_in_uop_bits_xcpt_ma_if, // @[issue-slot.scala:52:14] input io_in_uop_bits_bp_debug_if, // @[issue-slot.scala:52:14] input io_in_uop_bits_bp_xcpt_if, // @[issue-slot.scala:52:14] input [2:0] io_in_uop_bits_debug_fsrc, // @[issue-slot.scala:52:14] input [2:0] io_in_uop_bits_debug_tsrc, // @[issue-slot.scala:52:14] output [31:0] io_out_uop_inst, // @[issue-slot.scala:52:14] output [31:0] io_out_uop_debug_inst, // @[issue-slot.scala:52:14] output io_out_uop_is_rvc, // @[issue-slot.scala:52:14] output [39:0] io_out_uop_debug_pc, // @[issue-slot.scala:52:14] output io_out_uop_iq_type_0, // @[issue-slot.scala:52:14] output io_out_uop_iq_type_1, // @[issue-slot.scala:52:14] output io_out_uop_iq_type_2, // @[issue-slot.scala:52:14] output io_out_uop_iq_type_3, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_0, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_1, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_2, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_3, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_4, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_5, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_6, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_7, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_8, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_9, // @[issue-slot.scala:52:14] output io_out_uop_iw_issued, // @[issue-slot.scala:52:14] output [2:0] io_out_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14] output [2:0] io_out_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14] output io_out_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] output io_out_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] output io_out_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] output [2:0] io_out_uop_dis_col_sel, // @[issue-slot.scala:52:14] output [15:0] io_out_uop_br_mask, // @[issue-slot.scala:52:14] output [3:0] io_out_uop_br_tag, // @[issue-slot.scala:52:14] output [3:0] io_out_uop_br_type, // @[issue-slot.scala:52:14] output io_out_uop_is_sfb, // @[issue-slot.scala:52:14] output io_out_uop_is_fence, // @[issue-slot.scala:52:14] output io_out_uop_is_fencei, // @[issue-slot.scala:52:14] output io_out_uop_is_sfence, // @[issue-slot.scala:52:14] output io_out_uop_is_amo, // @[issue-slot.scala:52:14] output io_out_uop_is_eret, // @[issue-slot.scala:52:14] output io_out_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14] output io_out_uop_is_rocc, // @[issue-slot.scala:52:14] output io_out_uop_is_mov, // @[issue-slot.scala:52:14] output [4:0] io_out_uop_ftq_idx, // @[issue-slot.scala:52:14] output io_out_uop_edge_inst, // @[issue-slot.scala:52:14] output [5:0] io_out_uop_pc_lob, // @[issue-slot.scala:52:14] output io_out_uop_taken, // @[issue-slot.scala:52:14] output io_out_uop_imm_rename, // @[issue-slot.scala:52:14] output [2:0] io_out_uop_imm_sel, // @[issue-slot.scala:52:14] output [4:0] io_out_uop_pimm, // @[issue-slot.scala:52:14] output [19:0] io_out_uop_imm_packed, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_op1_sel, // @[issue-slot.scala:52:14] output [2:0] io_out_uop_op2_sel, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_div, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14] output [6:0] io_out_uop_rob_idx, // @[issue-slot.scala:52:14] output [4:0] io_out_uop_ldq_idx, // @[issue-slot.scala:52:14] output [4:0] io_out_uop_stq_idx, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_rxq_idx, // @[issue-slot.scala:52:14] output [6:0] io_out_uop_pdst, // @[issue-slot.scala:52:14] output [6:0] io_out_uop_prs1, // @[issue-slot.scala:52:14] output [6:0] io_out_uop_prs2, // @[issue-slot.scala:52:14] output [6:0] io_out_uop_prs3, // @[issue-slot.scala:52:14] output [4:0] io_out_uop_ppred, // @[issue-slot.scala:52:14] output io_out_uop_prs1_busy, // @[issue-slot.scala:52:14] output io_out_uop_prs2_busy, // @[issue-slot.scala:52:14] output io_out_uop_prs3_busy, // @[issue-slot.scala:52:14] output io_out_uop_ppred_busy, // @[issue-slot.scala:52:14] output [6:0] io_out_uop_stale_pdst, // @[issue-slot.scala:52:14] output io_out_uop_exception, // @[issue-slot.scala:52:14] output [63:0] io_out_uop_exc_cause, // @[issue-slot.scala:52:14] output [4:0] io_out_uop_mem_cmd, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_mem_size, // @[issue-slot.scala:52:14] output io_out_uop_mem_signed, // @[issue-slot.scala:52:14] output io_out_uop_uses_ldq, // @[issue-slot.scala:52:14] output io_out_uop_uses_stq, // @[issue-slot.scala:52:14] output io_out_uop_is_unique, // @[issue-slot.scala:52:14] output io_out_uop_flush_on_commit, // @[issue-slot.scala:52:14] output [2:0] io_out_uop_csr_cmd, // @[issue-slot.scala:52:14] output io_out_uop_ldst_is_rs1, // @[issue-slot.scala:52:14] output [5:0] io_out_uop_ldst, // @[issue-slot.scala:52:14] output [5:0] io_out_uop_lrs1, // @[issue-slot.scala:52:14] output [5:0] io_out_uop_lrs2, // @[issue-slot.scala:52:14] output [5:0] io_out_uop_lrs3, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_dst_rtype, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_lrs1_rtype, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_lrs2_rtype, // @[issue-slot.scala:52:14] output io_out_uop_frs3_en, // @[issue-slot.scala:52:14] output io_out_uop_fcn_dw, // @[issue-slot.scala:52:14] output [4:0] io_out_uop_fcn_op, // @[issue-slot.scala:52:14] output io_out_uop_fp_val, // @[issue-slot.scala:52:14] output [2:0] io_out_uop_fp_rm, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_fp_typ, // @[issue-slot.scala:52:14] output io_out_uop_xcpt_pf_if, // @[issue-slot.scala:52:14] output io_out_uop_xcpt_ae_if, // @[issue-slot.scala:52:14] output io_out_uop_xcpt_ma_if, // @[issue-slot.scala:52:14] output io_out_uop_bp_debug_if, // @[issue-slot.scala:52:14] output io_out_uop_bp_xcpt_if, // @[issue-slot.scala:52:14] output [2:0] io_out_uop_debug_fsrc, // @[issue-slot.scala:52:14] output [2:0] io_out_uop_debug_tsrc, // @[issue-slot.scala:52:14] input [15:0] io_brupdate_b1_resolve_mask, // @[issue-slot.scala:52:14] input [15:0] io_brupdate_b1_mispredict_mask, // @[issue-slot.scala:52:14] input [31:0] io_brupdate_b2_uop_inst, // @[issue-slot.scala:52:14] input [31:0] io_brupdate_b2_uop_debug_inst, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_rvc, // @[issue-slot.scala:52:14] input [39:0] io_brupdate_b2_uop_debug_pc, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iq_type_0, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iq_type_1, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iq_type_2, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iq_type_3, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_0, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_1, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_2, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_3, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_4, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_5, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_6, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_7, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_8, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_9, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iw_issued, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iw_issued_partial_agen, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iw_issued_partial_dgen, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_dis_col_sel, // @[issue-slot.scala:52:14] input [15:0] io_brupdate_b2_uop_br_mask, // @[issue-slot.scala:52:14] input [3:0] io_brupdate_b2_uop_br_tag, // @[issue-slot.scala:52:14] input [3:0] io_brupdate_b2_uop_br_type, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_sfb, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_fence, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_fencei, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_sfence, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_amo, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_eret, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_rocc, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_mov, // @[issue-slot.scala:52:14] input [4:0] io_brupdate_b2_uop_ftq_idx, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_edge_inst, // @[issue-slot.scala:52:14] input [5:0] io_brupdate_b2_uop_pc_lob, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_taken, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_imm_rename, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_imm_sel, // @[issue-slot.scala:52:14] input [4:0] io_brupdate_b2_uop_pimm, // @[issue-slot.scala:52:14] input [19:0] io_brupdate_b2_uop_imm_packed, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_op1_sel, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_op2_sel, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_div, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14] input [6:0] io_brupdate_b2_uop_rob_idx, // @[issue-slot.scala:52:14] input [4:0] io_brupdate_b2_uop_ldq_idx, // @[issue-slot.scala:52:14] input [4:0] io_brupdate_b2_uop_stq_idx, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_rxq_idx, // @[issue-slot.scala:52:14] input [6:0] io_brupdate_b2_uop_pdst, // @[issue-slot.scala:52:14] input [6:0] io_brupdate_b2_uop_prs1, // @[issue-slot.scala:52:14] input [6:0] io_brupdate_b2_uop_prs2, // @[issue-slot.scala:52:14] input [6:0] io_brupdate_b2_uop_prs3, // @[issue-slot.scala:52:14] input [4:0] io_brupdate_b2_uop_ppred, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_prs1_busy, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_prs2_busy, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_prs3_busy, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_ppred_busy, // @[issue-slot.scala:52:14] input [6:0] io_brupdate_b2_uop_stale_pdst, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_exception, // @[issue-slot.scala:52:14] input [63:0] io_brupdate_b2_uop_exc_cause, // @[issue-slot.scala:52:14] input [4:0] io_brupdate_b2_uop_mem_cmd, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_mem_size, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_mem_signed, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_uses_ldq, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_uses_stq, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_unique, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_flush_on_commit, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_csr_cmd, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_ldst_is_rs1, // @[issue-slot.scala:52:14] input [5:0] io_brupdate_b2_uop_ldst, // @[issue-slot.scala:52:14] input [5:0] io_brupdate_b2_uop_lrs1, // @[issue-slot.scala:52:14] input [5:0] io_brupdate_b2_uop_lrs2, // @[issue-slot.scala:52:14] input [5:0] io_brupdate_b2_uop_lrs3, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_dst_rtype, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_lrs1_rtype, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_lrs2_rtype, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_frs3_en, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fcn_dw, // @[issue-slot.scala:52:14] input [4:0] io_brupdate_b2_uop_fcn_op, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_val, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_fp_rm, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_fp_typ, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_xcpt_pf_if, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_xcpt_ae_if, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_xcpt_ma_if, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_bp_debug_if, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_bp_xcpt_if, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_debug_fsrc, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_debug_tsrc, // @[issue-slot.scala:52:14] input io_brupdate_b2_mispredict, // @[issue-slot.scala:52:14] input io_brupdate_b2_taken, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_cfi_type, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_pc_sel, // @[issue-slot.scala:52:14] input [39:0] io_brupdate_b2_jalr_target, // @[issue-slot.scala:52:14] input [20:0] io_brupdate_b2_target_offset, // @[issue-slot.scala:52:14] input io_kill, // @[issue-slot.scala:52:14] input io_squash_grant, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_valid, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_0_bits_uop_inst, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_0_bits_uop_debug_inst, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_rvc, // @[issue-slot.scala:52:14] input [39:0] io_wakeup_ports_0_bits_uop_debug_pc, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iq_type_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iq_type_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iq_type_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iq_type_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_4, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_5, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_6, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_7, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_8, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_9, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iw_issued, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iw_issued_partial_agen, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_dis_col_sel, // @[issue-slot.scala:52:14] input [15:0] io_wakeup_ports_0_bits_uop_br_mask, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_0_bits_uop_br_tag, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_0_bits_uop_br_type, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_sfb, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_fence, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_fencei, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_sfence, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_amo, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_eret, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_rocc, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_mov, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_0_bits_uop_ftq_idx, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_edge_inst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_0_bits_uop_pc_lob, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_taken, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_imm_rename, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_imm_sel, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_0_bits_uop_pimm, // @[issue-slot.scala:52:14] input [19:0] io_wakeup_ports_0_bits_uop_imm_packed, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_op1_sel, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_op2_sel, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_div, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_0_bits_uop_rob_idx, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_0_bits_uop_ldq_idx, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_0_bits_uop_stq_idx, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_rxq_idx, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_0_bits_uop_pdst, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_0_bits_uop_prs1, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_0_bits_uop_prs2, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_0_bits_uop_prs3, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_0_bits_uop_ppred, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_prs1_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_prs2_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_prs3_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_ppred_busy, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_0_bits_uop_stale_pdst, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_exception, // @[issue-slot.scala:52:14] input [63:0] io_wakeup_ports_0_bits_uop_exc_cause, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_0_bits_uop_mem_cmd, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_mem_size, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_mem_signed, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_uses_ldq, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_uses_stq, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_unique, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_flush_on_commit, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_csr_cmd, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_ldst_is_rs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_0_bits_uop_ldst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_0_bits_uop_lrs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_0_bits_uop_lrs2, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_0_bits_uop_lrs3, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_dst_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_lrs1_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_lrs2_rtype, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_frs3_en, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fcn_dw, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_0_bits_uop_fcn_op, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_val, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_fp_rm, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_fp_typ, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_xcpt_pf_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_xcpt_ae_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_xcpt_ma_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_bp_debug_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_bp_xcpt_if, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_debug_fsrc, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_debug_tsrc, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_bypassable, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_speculative_mask, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_rebusy, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_valid, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_1_bits_uop_inst, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_1_bits_uop_debug_inst, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_rvc, // @[issue-slot.scala:52:14] input [39:0] io_wakeup_ports_1_bits_uop_debug_pc, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iq_type_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iq_type_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iq_type_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iq_type_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_4, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_5, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_6, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_7, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_8, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_9, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iw_issued, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iw_issued_partial_agen, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_dis_col_sel, // @[issue-slot.scala:52:14] input [15:0] io_wakeup_ports_1_bits_uop_br_mask, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_1_bits_uop_br_tag, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_1_bits_uop_br_type, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_sfb, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_fence, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_fencei, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_sfence, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_amo, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_eret, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_rocc, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_mov, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_1_bits_uop_ftq_idx, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_edge_inst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_1_bits_uop_pc_lob, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_taken, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_imm_rename, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_imm_sel, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_1_bits_uop_pimm, // @[issue-slot.scala:52:14] input [19:0] io_wakeup_ports_1_bits_uop_imm_packed, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_op1_sel, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_op2_sel, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_div, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_1_bits_uop_rob_idx, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_1_bits_uop_ldq_idx, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_1_bits_uop_stq_idx, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_rxq_idx, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_1_bits_uop_pdst, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_1_bits_uop_prs1, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_1_bits_uop_prs2, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_1_bits_uop_prs3, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_1_bits_uop_ppred, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_prs1_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_prs2_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_prs3_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_ppred_busy, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_1_bits_uop_stale_pdst, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_exception, // @[issue-slot.scala:52:14] input [63:0] io_wakeup_ports_1_bits_uop_exc_cause, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_1_bits_uop_mem_cmd, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_mem_size, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_mem_signed, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_uses_ldq, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_uses_stq, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_unique, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_flush_on_commit, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_csr_cmd, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_ldst_is_rs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_1_bits_uop_ldst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_1_bits_uop_lrs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_1_bits_uop_lrs2, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_1_bits_uop_lrs3, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_dst_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_lrs1_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_lrs2_rtype, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_frs3_en, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fcn_dw, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_1_bits_uop_fcn_op, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_val, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_fp_rm, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_fp_typ, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_xcpt_pf_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_xcpt_ae_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_xcpt_ma_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_bp_debug_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_bp_xcpt_if, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_debug_fsrc, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_debug_tsrc, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_valid, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_2_bits_uop_inst, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_2_bits_uop_debug_inst, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_rvc, // @[issue-slot.scala:52:14] input [39:0] io_wakeup_ports_2_bits_uop_debug_pc, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_iq_type_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_iq_type_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_iq_type_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_iq_type_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_4, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_5, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_6, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_7, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_8, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_9, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_iw_issued, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_2_bits_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_2_bits_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_2_bits_uop_dis_col_sel, // @[issue-slot.scala:52:14] input [15:0] io_wakeup_ports_2_bits_uop_br_mask, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_2_bits_uop_br_tag, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_2_bits_uop_br_type, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_sfb, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_fence, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_fencei, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_sfence, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_amo, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_eret, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_rocc, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_mov, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_2_bits_uop_ftq_idx, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_edge_inst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_2_bits_uop_pc_lob, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_taken, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_imm_rename, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_2_bits_uop_imm_sel, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_2_bits_uop_pimm, // @[issue-slot.scala:52:14] input [19:0] io_wakeup_ports_2_bits_uop_imm_packed, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_op1_sel, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_2_bits_uop_op2_sel, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_div, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_2_bits_uop_rob_idx, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_2_bits_uop_ldq_idx, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_2_bits_uop_stq_idx, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_rxq_idx, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_2_bits_uop_pdst, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_2_bits_uop_prs1, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_2_bits_uop_prs2, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_2_bits_uop_prs3, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_2_bits_uop_ppred, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_prs1_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_prs2_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_prs3_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_ppred_busy, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_2_bits_uop_stale_pdst, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_exception, // @[issue-slot.scala:52:14] input [63:0] io_wakeup_ports_2_bits_uop_exc_cause, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_2_bits_uop_mem_cmd, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_mem_size, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_mem_signed, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_uses_ldq, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_uses_stq, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_unique, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_flush_on_commit, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_2_bits_uop_csr_cmd, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_ldst_is_rs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_2_bits_uop_ldst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_2_bits_uop_lrs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_2_bits_uop_lrs2, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_2_bits_uop_lrs3, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_dst_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_lrs1_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_lrs2_rtype, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_frs3_en, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fcn_dw, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_2_bits_uop_fcn_op, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_val, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_2_bits_uop_fp_rm, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_fp_typ, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_xcpt_pf_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_xcpt_ae_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_xcpt_ma_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_bp_debug_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_bp_xcpt_if, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_2_bits_uop_debug_fsrc, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_2_bits_uop_debug_tsrc, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_valid, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_3_bits_uop_inst, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_3_bits_uop_debug_inst, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_rvc, // @[issue-slot.scala:52:14] input [39:0] io_wakeup_ports_3_bits_uop_debug_pc, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_iq_type_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_iq_type_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_iq_type_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_iq_type_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_4, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_5, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_6, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_7, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_8, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_9, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_iw_issued, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_3_bits_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_3_bits_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_3_bits_uop_dis_col_sel, // @[issue-slot.scala:52:14] input [15:0] io_wakeup_ports_3_bits_uop_br_mask, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_3_bits_uop_br_tag, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_3_bits_uop_br_type, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_sfb, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_fence, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_fencei, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_sfence, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_amo, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_eret, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_rocc, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_mov, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_3_bits_uop_ftq_idx, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_edge_inst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_3_bits_uop_pc_lob, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_taken, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_imm_rename, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_3_bits_uop_imm_sel, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_3_bits_uop_pimm, // @[issue-slot.scala:52:14] input [19:0] io_wakeup_ports_3_bits_uop_imm_packed, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_op1_sel, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_3_bits_uop_op2_sel, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_div, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_3_bits_uop_rob_idx, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_3_bits_uop_ldq_idx, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_3_bits_uop_stq_idx, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_rxq_idx, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_3_bits_uop_pdst, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_3_bits_uop_prs1, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_3_bits_uop_prs2, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_3_bits_uop_prs3, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_3_bits_uop_ppred, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_prs1_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_prs2_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_prs3_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_ppred_busy, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_3_bits_uop_stale_pdst, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_exception, // @[issue-slot.scala:52:14] input [63:0] io_wakeup_ports_3_bits_uop_exc_cause, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_3_bits_uop_mem_cmd, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_mem_size, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_mem_signed, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_uses_ldq, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_uses_stq, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_unique, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_flush_on_commit, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_3_bits_uop_csr_cmd, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_ldst_is_rs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_3_bits_uop_ldst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_3_bits_uop_lrs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_3_bits_uop_lrs2, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_3_bits_uop_lrs3, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_dst_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_lrs1_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_lrs2_rtype, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_frs3_en, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fcn_dw, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_3_bits_uop_fcn_op, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_val, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_3_bits_uop_fp_rm, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_fp_typ, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_xcpt_pf_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_xcpt_ae_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_xcpt_ma_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_bp_debug_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_bp_xcpt_if, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_3_bits_uop_debug_fsrc, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_3_bits_uop_debug_tsrc, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_valid, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_4_bits_uop_inst, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_4_bits_uop_debug_inst, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_is_rvc, // @[issue-slot.scala:52:14] input [39:0] io_wakeup_ports_4_bits_uop_debug_pc, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_iq_type_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_iq_type_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_iq_type_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_iq_type_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fu_code_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fu_code_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fu_code_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fu_code_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fu_code_4, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fu_code_5, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fu_code_6, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fu_code_7, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fu_code_8, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fu_code_9, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_iw_issued, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_4_bits_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_4_bits_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_4_bits_uop_dis_col_sel, // @[issue-slot.scala:52:14] input [15:0] io_wakeup_ports_4_bits_uop_br_mask, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_4_bits_uop_br_tag, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_4_bits_uop_br_type, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_is_sfb, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_is_fence, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_is_fencei, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_is_sfence, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_is_amo, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_is_eret, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_is_rocc, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_is_mov, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_4_bits_uop_ftq_idx, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_edge_inst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_4_bits_uop_pc_lob, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_taken, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_imm_rename, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_4_bits_uop_imm_sel, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_4_bits_uop_pimm, // @[issue-slot.scala:52:14] input [19:0] io_wakeup_ports_4_bits_uop_imm_packed, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_4_bits_uop_op1_sel, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_4_bits_uop_op2_sel, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_4_bits_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_4_bits_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_div, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_4_bits_uop_rob_idx, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_4_bits_uop_ldq_idx, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_4_bits_uop_stq_idx, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_4_bits_uop_rxq_idx, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_4_bits_uop_pdst, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_4_bits_uop_prs1, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_4_bits_uop_prs2, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_4_bits_uop_prs3, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_4_bits_uop_ppred, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_prs1_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_prs2_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_prs3_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_ppred_busy, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_4_bits_uop_stale_pdst, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_exception, // @[issue-slot.scala:52:14] input [63:0] io_wakeup_ports_4_bits_uop_exc_cause, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_4_bits_uop_mem_cmd, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_4_bits_uop_mem_size, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_mem_signed, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_uses_ldq, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_uses_stq, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_is_unique, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_flush_on_commit, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_4_bits_uop_csr_cmd, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_ldst_is_rs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_4_bits_uop_ldst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_4_bits_uop_lrs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_4_bits_uop_lrs2, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_4_bits_uop_lrs3, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_4_bits_uop_dst_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_4_bits_uop_lrs1_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_4_bits_uop_lrs2_rtype, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_frs3_en, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fcn_dw, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_4_bits_uop_fcn_op, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fp_val, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_4_bits_uop_fp_rm, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_4_bits_uop_fp_typ, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_xcpt_pf_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_xcpt_ae_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_xcpt_ma_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_bp_debug_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_bp_xcpt_if, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_4_bits_uop_debug_fsrc, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_4_bits_uop_debug_tsrc, // @[issue-slot.scala:52:14] input io_pred_wakeup_port_valid, // @[issue-slot.scala:52:14] input [4:0] io_pred_wakeup_port_bits, // @[issue-slot.scala:52:14] input [2:0] io_child_rebusys // @[issue-slot.scala:52:14] ); wire [15:0] next_uop_out_br_mask; // @[util.scala:104:23] wire io_grant_0 = io_grant; // @[issue-slot.scala:49:7] wire io_in_uop_valid_0 = io_in_uop_valid; // @[issue-slot.scala:49:7] wire [31:0] io_in_uop_bits_inst_0 = io_in_uop_bits_inst; // @[issue-slot.scala:49:7] wire [31:0] io_in_uop_bits_debug_inst_0 = io_in_uop_bits_debug_inst; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_rvc_0 = io_in_uop_bits_is_rvc; // @[issue-slot.scala:49:7] wire [39:0] io_in_uop_bits_debug_pc_0 = io_in_uop_bits_debug_pc; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iq_type_0_0 = io_in_uop_bits_iq_type_0; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iq_type_1_0 = io_in_uop_bits_iq_type_1; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iq_type_2_0 = io_in_uop_bits_iq_type_2; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iq_type_3_0 = io_in_uop_bits_iq_type_3; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_0_0 = io_in_uop_bits_fu_code_0; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_1_0 = io_in_uop_bits_fu_code_1; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_2_0 = io_in_uop_bits_fu_code_2; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_3_0 = io_in_uop_bits_fu_code_3; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_4_0 = io_in_uop_bits_fu_code_4; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_5_0 = io_in_uop_bits_fu_code_5; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_6_0 = io_in_uop_bits_fu_code_6; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_7_0 = io_in_uop_bits_fu_code_7; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_8_0 = io_in_uop_bits_fu_code_8; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_9_0 = io_in_uop_bits_fu_code_9; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iw_issued_0 = io_in_uop_bits_iw_issued; // @[issue-slot.scala:49:7] wire [2:0] io_in_uop_bits_iw_p1_speculative_child_0 = io_in_uop_bits_iw_p1_speculative_child; // @[issue-slot.scala:49:7] wire [2:0] io_in_uop_bits_iw_p2_speculative_child_0 = io_in_uop_bits_iw_p2_speculative_child; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iw_p1_bypass_hint_0 = io_in_uop_bits_iw_p1_bypass_hint; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iw_p2_bypass_hint_0 = io_in_uop_bits_iw_p2_bypass_hint; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iw_p3_bypass_hint_0 = io_in_uop_bits_iw_p3_bypass_hint; // @[issue-slot.scala:49:7] wire [2:0] io_in_uop_bits_dis_col_sel_0 = io_in_uop_bits_dis_col_sel; // @[issue-slot.scala:49:7] wire [15:0] io_in_uop_bits_br_mask_0 = io_in_uop_bits_br_mask; // @[issue-slot.scala:49:7] wire [3:0] io_in_uop_bits_br_tag_0 = io_in_uop_bits_br_tag; // @[issue-slot.scala:49:7] wire [3:0] io_in_uop_bits_br_type_0 = io_in_uop_bits_br_type; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_sfb_0 = io_in_uop_bits_is_sfb; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_fence_0 = io_in_uop_bits_is_fence; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_fencei_0 = io_in_uop_bits_is_fencei; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_sfence_0 = io_in_uop_bits_is_sfence; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_amo_0 = io_in_uop_bits_is_amo; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_eret_0 = io_in_uop_bits_is_eret; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_sys_pc2epc_0 = io_in_uop_bits_is_sys_pc2epc; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_rocc_0 = io_in_uop_bits_is_rocc; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_mov_0 = io_in_uop_bits_is_mov; // @[issue-slot.scala:49:7] wire [4:0] io_in_uop_bits_ftq_idx_0 = io_in_uop_bits_ftq_idx; // @[issue-slot.scala:49:7] wire io_in_uop_bits_edge_inst_0 = io_in_uop_bits_edge_inst; // @[issue-slot.scala:49:7] wire [5:0] io_in_uop_bits_pc_lob_0 = io_in_uop_bits_pc_lob; // @[issue-slot.scala:49:7] wire io_in_uop_bits_taken_0 = io_in_uop_bits_taken; // @[issue-slot.scala:49:7] wire io_in_uop_bits_imm_rename_0 = io_in_uop_bits_imm_rename; // @[issue-slot.scala:49:7] wire [2:0] io_in_uop_bits_imm_sel_0 = io_in_uop_bits_imm_sel; // @[issue-slot.scala:49:7] wire [4:0] io_in_uop_bits_pimm_0 = io_in_uop_bits_pimm; // @[issue-slot.scala:49:7] wire [19:0] io_in_uop_bits_imm_packed_0 = io_in_uop_bits_imm_packed; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_op1_sel_0 = io_in_uop_bits_op1_sel; // @[issue-slot.scala:49:7] wire [2:0] io_in_uop_bits_op2_sel_0 = io_in_uop_bits_op2_sel; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_ldst_0 = io_in_uop_bits_fp_ctrl_ldst; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_wen_0 = io_in_uop_bits_fp_ctrl_wen; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_ren1_0 = io_in_uop_bits_fp_ctrl_ren1; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_ren2_0 = io_in_uop_bits_fp_ctrl_ren2; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_ren3_0 = io_in_uop_bits_fp_ctrl_ren3; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_swap12_0 = io_in_uop_bits_fp_ctrl_swap12; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_swap23_0 = io_in_uop_bits_fp_ctrl_swap23; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_fp_ctrl_typeTagIn_0 = io_in_uop_bits_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_fp_ctrl_typeTagOut_0 = io_in_uop_bits_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_fromint_0 = io_in_uop_bits_fp_ctrl_fromint; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_toint_0 = io_in_uop_bits_fp_ctrl_toint; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_fastpipe_0 = io_in_uop_bits_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_fma_0 = io_in_uop_bits_fp_ctrl_fma; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_div_0 = io_in_uop_bits_fp_ctrl_div; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_sqrt_0 = io_in_uop_bits_fp_ctrl_sqrt; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_wflags_0 = io_in_uop_bits_fp_ctrl_wflags; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_vec_0 = io_in_uop_bits_fp_ctrl_vec; // @[issue-slot.scala:49:7] wire [6:0] io_in_uop_bits_rob_idx_0 = io_in_uop_bits_rob_idx; // @[issue-slot.scala:49:7] wire [4:0] io_in_uop_bits_ldq_idx_0 = io_in_uop_bits_ldq_idx; // @[issue-slot.scala:49:7] wire [4:0] io_in_uop_bits_stq_idx_0 = io_in_uop_bits_stq_idx; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_rxq_idx_0 = io_in_uop_bits_rxq_idx; // @[issue-slot.scala:49:7] wire [6:0] io_in_uop_bits_pdst_0 = io_in_uop_bits_pdst; // @[issue-slot.scala:49:7] wire [6:0] io_in_uop_bits_prs1_0 = io_in_uop_bits_prs1; // @[issue-slot.scala:49:7] wire [6:0] io_in_uop_bits_prs2_0 = io_in_uop_bits_prs2; // @[issue-slot.scala:49:7] wire [6:0] io_in_uop_bits_prs3_0 = io_in_uop_bits_prs3; // @[issue-slot.scala:49:7] wire [4:0] io_in_uop_bits_ppred_0 = io_in_uop_bits_ppred; // @[issue-slot.scala:49:7] wire io_in_uop_bits_prs1_busy_0 = io_in_uop_bits_prs1_busy; // @[issue-slot.scala:49:7] wire io_in_uop_bits_prs2_busy_0 = io_in_uop_bits_prs2_busy; // @[issue-slot.scala:49:7] wire io_in_uop_bits_prs3_busy_0 = io_in_uop_bits_prs3_busy; // @[issue-slot.scala:49:7] wire io_in_uop_bits_ppred_busy_0 = io_in_uop_bits_ppred_busy; // @[issue-slot.scala:49:7] wire [6:0] io_in_uop_bits_stale_pdst_0 = io_in_uop_bits_stale_pdst; // @[issue-slot.scala:49:7] wire io_in_uop_bits_exception_0 = io_in_uop_bits_exception; // @[issue-slot.scala:49:7] wire [63:0] io_in_uop_bits_exc_cause_0 = io_in_uop_bits_exc_cause; // @[issue-slot.scala:49:7] wire [4:0] io_in_uop_bits_mem_cmd_0 = io_in_uop_bits_mem_cmd; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_mem_size_0 = io_in_uop_bits_mem_size; // @[issue-slot.scala:49:7] wire io_in_uop_bits_mem_signed_0 = io_in_uop_bits_mem_signed; // @[issue-slot.scala:49:7] wire io_in_uop_bits_uses_ldq_0 = io_in_uop_bits_uses_ldq; // @[issue-slot.scala:49:7] wire io_in_uop_bits_uses_stq_0 = io_in_uop_bits_uses_stq; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_unique_0 = io_in_uop_bits_is_unique; // @[issue-slot.scala:49:7] wire io_in_uop_bits_flush_on_commit_0 = io_in_uop_bits_flush_on_commit; // @[issue-slot.scala:49:7] wire [2:0] io_in_uop_bits_csr_cmd_0 = io_in_uop_bits_csr_cmd; // @[issue-slot.scala:49:7] wire io_in_uop_bits_ldst_is_rs1_0 = io_in_uop_bits_ldst_is_rs1; // @[issue-slot.scala:49:7] wire [5:0] io_in_uop_bits_ldst_0 = io_in_uop_bits_ldst; // @[issue-slot.scala:49:7] wire [5:0] io_in_uop_bits_lrs1_0 = io_in_uop_bits_lrs1; // @[issue-slot.scala:49:7] wire [5:0] io_in_uop_bits_lrs2_0 = io_in_uop_bits_lrs2; // @[issue-slot.scala:49:7] wire [5:0] io_in_uop_bits_lrs3_0 = io_in_uop_bits_lrs3; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_dst_rtype_0 = io_in_uop_bits_dst_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_lrs1_rtype_0 = io_in_uop_bits_lrs1_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_lrs2_rtype_0 = io_in_uop_bits_lrs2_rtype; // @[issue-slot.scala:49:7] wire io_in_uop_bits_frs3_en_0 = io_in_uop_bits_frs3_en; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fcn_dw_0 = io_in_uop_bits_fcn_dw; // @[issue-slot.scala:49:7] wire [4:0] io_in_uop_bits_fcn_op_0 = io_in_uop_bits_fcn_op; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_val_0 = io_in_uop_bits_fp_val; // @[issue-slot.scala:49:7] wire [2:0] io_in_uop_bits_fp_rm_0 = io_in_uop_bits_fp_rm; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_fp_typ_0 = io_in_uop_bits_fp_typ; // @[issue-slot.scala:49:7] wire io_in_uop_bits_xcpt_pf_if_0 = io_in_uop_bits_xcpt_pf_if; // @[issue-slot.scala:49:7] wire io_in_uop_bits_xcpt_ae_if_0 = io_in_uop_bits_xcpt_ae_if; // @[issue-slot.scala:49:7] wire io_in_uop_bits_xcpt_ma_if_0 = io_in_uop_bits_xcpt_ma_if; // @[issue-slot.scala:49:7] wire io_in_uop_bits_bp_debug_if_0 = io_in_uop_bits_bp_debug_if; // @[issue-slot.scala:49:7] wire io_in_uop_bits_bp_xcpt_if_0 = io_in_uop_bits_bp_xcpt_if; // @[issue-slot.scala:49:7] wire [2:0] io_in_uop_bits_debug_fsrc_0 = io_in_uop_bits_debug_fsrc; // @[issue-slot.scala:49:7] wire [2:0] io_in_uop_bits_debug_tsrc_0 = io_in_uop_bits_debug_tsrc; // @[issue-slot.scala:49:7] wire [15:0] io_brupdate_b1_resolve_mask_0 = io_brupdate_b1_resolve_mask; // @[issue-slot.scala:49:7] wire [15:0] io_brupdate_b1_mispredict_mask_0 = io_brupdate_b1_mispredict_mask; // @[issue-slot.scala:49:7] wire [31:0] io_brupdate_b2_uop_inst_0 = io_brupdate_b2_uop_inst; // @[issue-slot.scala:49:7] wire [31:0] io_brupdate_b2_uop_debug_inst_0 = io_brupdate_b2_uop_debug_inst; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_rvc_0 = io_brupdate_b2_uop_is_rvc; // @[issue-slot.scala:49:7] wire [39:0] io_brupdate_b2_uop_debug_pc_0 = io_brupdate_b2_uop_debug_pc; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iq_type_0_0 = io_brupdate_b2_uop_iq_type_0; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iq_type_1_0 = io_brupdate_b2_uop_iq_type_1; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iq_type_2_0 = io_brupdate_b2_uop_iq_type_2; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iq_type_3_0 = io_brupdate_b2_uop_iq_type_3; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_0_0 = io_brupdate_b2_uop_fu_code_0; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_1_0 = io_brupdate_b2_uop_fu_code_1; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_2_0 = io_brupdate_b2_uop_fu_code_2; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_3_0 = io_brupdate_b2_uop_fu_code_3; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_4_0 = io_brupdate_b2_uop_fu_code_4; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_5_0 = io_brupdate_b2_uop_fu_code_5; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_6_0 = io_brupdate_b2_uop_fu_code_6; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_7_0 = io_brupdate_b2_uop_fu_code_7; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_8_0 = io_brupdate_b2_uop_fu_code_8; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_9_0 = io_brupdate_b2_uop_fu_code_9; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iw_issued_0 = io_brupdate_b2_uop_iw_issued; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iw_issued_partial_agen_0 = io_brupdate_b2_uop_iw_issued_partial_agen; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iw_issued_partial_dgen_0 = io_brupdate_b2_uop_iw_issued_partial_dgen; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_iw_p1_speculative_child_0 = io_brupdate_b2_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_iw_p2_speculative_child_0 = io_brupdate_b2_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iw_p1_bypass_hint_0 = io_brupdate_b2_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iw_p2_bypass_hint_0 = io_brupdate_b2_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iw_p3_bypass_hint_0 = io_brupdate_b2_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_dis_col_sel_0 = io_brupdate_b2_uop_dis_col_sel; // @[issue-slot.scala:49:7] wire [15:0] io_brupdate_b2_uop_br_mask_0 = io_brupdate_b2_uop_br_mask; // @[issue-slot.scala:49:7] wire [3:0] io_brupdate_b2_uop_br_tag_0 = io_brupdate_b2_uop_br_tag; // @[issue-slot.scala:49:7] wire [3:0] io_brupdate_b2_uop_br_type_0 = io_brupdate_b2_uop_br_type; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_sfb_0 = io_brupdate_b2_uop_is_sfb; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_fence_0 = io_brupdate_b2_uop_is_fence; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_fencei_0 = io_brupdate_b2_uop_is_fencei; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_sfence_0 = io_brupdate_b2_uop_is_sfence; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_amo_0 = io_brupdate_b2_uop_is_amo; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_eret_0 = io_brupdate_b2_uop_is_eret; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_sys_pc2epc_0 = io_brupdate_b2_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_rocc_0 = io_brupdate_b2_uop_is_rocc; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_mov_0 = io_brupdate_b2_uop_is_mov; // @[issue-slot.scala:49:7] wire [4:0] io_brupdate_b2_uop_ftq_idx_0 = io_brupdate_b2_uop_ftq_idx; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_edge_inst_0 = io_brupdate_b2_uop_edge_inst; // @[issue-slot.scala:49:7] wire [5:0] io_brupdate_b2_uop_pc_lob_0 = io_brupdate_b2_uop_pc_lob; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_taken_0 = io_brupdate_b2_uop_taken; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_imm_rename_0 = io_brupdate_b2_uop_imm_rename; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_imm_sel_0 = io_brupdate_b2_uop_imm_sel; // @[issue-slot.scala:49:7] wire [4:0] io_brupdate_b2_uop_pimm_0 = io_brupdate_b2_uop_pimm; // @[issue-slot.scala:49:7] wire [19:0] io_brupdate_b2_uop_imm_packed_0 = io_brupdate_b2_uop_imm_packed; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_op1_sel_0 = io_brupdate_b2_uop_op1_sel; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_op2_sel_0 = io_brupdate_b2_uop_op2_sel; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_ldst_0 = io_brupdate_b2_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_wen_0 = io_brupdate_b2_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_ren1_0 = io_brupdate_b2_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_ren2_0 = io_brupdate_b2_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_ren3_0 = io_brupdate_b2_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_swap12_0 = io_brupdate_b2_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_swap23_0 = io_brupdate_b2_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagIn_0 = io_brupdate_b2_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagOut_0 = io_brupdate_b2_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_fromint_0 = io_brupdate_b2_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_toint_0 = io_brupdate_b2_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_fastpipe_0 = io_brupdate_b2_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_fma_0 = io_brupdate_b2_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_div_0 = io_brupdate_b2_uop_fp_ctrl_div; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_sqrt_0 = io_brupdate_b2_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_wflags_0 = io_brupdate_b2_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_vec_0 = io_brupdate_b2_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7] wire [6:0] io_brupdate_b2_uop_rob_idx_0 = io_brupdate_b2_uop_rob_idx; // @[issue-slot.scala:49:7] wire [4:0] io_brupdate_b2_uop_ldq_idx_0 = io_brupdate_b2_uop_ldq_idx; // @[issue-slot.scala:49:7] wire [4:0] io_brupdate_b2_uop_stq_idx_0 = io_brupdate_b2_uop_stq_idx; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_rxq_idx_0 = io_brupdate_b2_uop_rxq_idx; // @[issue-slot.scala:49:7] wire [6:0] io_brupdate_b2_uop_pdst_0 = io_brupdate_b2_uop_pdst; // @[issue-slot.scala:49:7] wire [6:0] io_brupdate_b2_uop_prs1_0 = io_brupdate_b2_uop_prs1; // @[issue-slot.scala:49:7] wire [6:0] io_brupdate_b2_uop_prs2_0 = io_brupdate_b2_uop_prs2; // @[issue-slot.scala:49:7] wire [6:0] io_brupdate_b2_uop_prs3_0 = io_brupdate_b2_uop_prs3; // @[issue-slot.scala:49:7] wire [4:0] io_brupdate_b2_uop_ppred_0 = io_brupdate_b2_uop_ppred; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_prs1_busy_0 = io_brupdate_b2_uop_prs1_busy; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_prs2_busy_0 = io_brupdate_b2_uop_prs2_busy; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_prs3_busy_0 = io_brupdate_b2_uop_prs3_busy; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_ppred_busy_0 = io_brupdate_b2_uop_ppred_busy; // @[issue-slot.scala:49:7] wire [6:0] io_brupdate_b2_uop_stale_pdst_0 = io_brupdate_b2_uop_stale_pdst; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_exception_0 = io_brupdate_b2_uop_exception; // @[issue-slot.scala:49:7] wire [63:0] io_brupdate_b2_uop_exc_cause_0 = io_brupdate_b2_uop_exc_cause; // @[issue-slot.scala:49:7] wire [4:0] io_brupdate_b2_uop_mem_cmd_0 = io_brupdate_b2_uop_mem_cmd; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_mem_size_0 = io_brupdate_b2_uop_mem_size; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_mem_signed_0 = io_brupdate_b2_uop_mem_signed; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_uses_ldq_0 = io_brupdate_b2_uop_uses_ldq; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_uses_stq_0 = io_brupdate_b2_uop_uses_stq; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_unique_0 = io_brupdate_b2_uop_is_unique; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_flush_on_commit_0 = io_brupdate_b2_uop_flush_on_commit; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_csr_cmd_0 = io_brupdate_b2_uop_csr_cmd; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_ldst_is_rs1_0 = io_brupdate_b2_uop_ldst_is_rs1; // @[issue-slot.scala:49:7] wire [5:0] io_brupdate_b2_uop_ldst_0 = io_brupdate_b2_uop_ldst; // @[issue-slot.scala:49:7] wire [5:0] io_brupdate_b2_uop_lrs1_0 = io_brupdate_b2_uop_lrs1; // @[issue-slot.scala:49:7] wire [5:0] io_brupdate_b2_uop_lrs2_0 = io_brupdate_b2_uop_lrs2; // @[issue-slot.scala:49:7] wire [5:0] io_brupdate_b2_uop_lrs3_0 = io_brupdate_b2_uop_lrs3; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_dst_rtype_0 = io_brupdate_b2_uop_dst_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_lrs1_rtype_0 = io_brupdate_b2_uop_lrs1_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_lrs2_rtype_0 = io_brupdate_b2_uop_lrs2_rtype; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_frs3_en_0 = io_brupdate_b2_uop_frs3_en; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fcn_dw_0 = io_brupdate_b2_uop_fcn_dw; // @[issue-slot.scala:49:7] wire [4:0] io_brupdate_b2_uop_fcn_op_0 = io_brupdate_b2_uop_fcn_op; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_val_0 = io_brupdate_b2_uop_fp_val; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_fp_rm_0 = io_brupdate_b2_uop_fp_rm; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_fp_typ_0 = io_brupdate_b2_uop_fp_typ; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_xcpt_pf_if_0 = io_brupdate_b2_uop_xcpt_pf_if; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_xcpt_ae_if_0 = io_brupdate_b2_uop_xcpt_ae_if; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_xcpt_ma_if_0 = io_brupdate_b2_uop_xcpt_ma_if; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_bp_debug_if_0 = io_brupdate_b2_uop_bp_debug_if; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_bp_xcpt_if_0 = io_brupdate_b2_uop_bp_xcpt_if; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_debug_fsrc_0 = io_brupdate_b2_uop_debug_fsrc; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_debug_tsrc_0 = io_brupdate_b2_uop_debug_tsrc; // @[issue-slot.scala:49:7] wire io_brupdate_b2_mispredict_0 = io_brupdate_b2_mispredict; // @[issue-slot.scala:49:7] wire io_brupdate_b2_taken_0 = io_brupdate_b2_taken; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_cfi_type_0 = io_brupdate_b2_cfi_type; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_pc_sel_0 = io_brupdate_b2_pc_sel; // @[issue-slot.scala:49:7] wire [39:0] io_brupdate_b2_jalr_target_0 = io_brupdate_b2_jalr_target; // @[issue-slot.scala:49:7] wire [20:0] io_brupdate_b2_target_offset_0 = io_brupdate_b2_target_offset; // @[issue-slot.scala:49:7] wire io_kill_0 = io_kill; // @[issue-slot.scala:49:7] wire io_squash_grant_0 = io_squash_grant; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_valid_0 = io_wakeup_ports_0_valid; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_0_bits_uop_inst_0 = io_wakeup_ports_0_bits_uop_inst; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_0_bits_uop_debug_inst_0 = io_wakeup_ports_0_bits_uop_debug_inst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_rvc_0 = io_wakeup_ports_0_bits_uop_is_rvc; // @[issue-slot.scala:49:7] wire [39:0] io_wakeup_ports_0_bits_uop_debug_pc_0 = io_wakeup_ports_0_bits_uop_debug_pc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iq_type_0_0 = io_wakeup_ports_0_bits_uop_iq_type_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iq_type_1_0 = io_wakeup_ports_0_bits_uop_iq_type_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iq_type_2_0 = io_wakeup_ports_0_bits_uop_iq_type_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iq_type_3_0 = io_wakeup_ports_0_bits_uop_iq_type_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_0_0 = io_wakeup_ports_0_bits_uop_fu_code_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_1_0 = io_wakeup_ports_0_bits_uop_fu_code_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_2_0 = io_wakeup_ports_0_bits_uop_fu_code_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_3_0 = io_wakeup_ports_0_bits_uop_fu_code_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_4_0 = io_wakeup_ports_0_bits_uop_fu_code_4; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_5_0 = io_wakeup_ports_0_bits_uop_fu_code_5; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_6_0 = io_wakeup_ports_0_bits_uop_fu_code_6; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_7_0 = io_wakeup_ports_0_bits_uop_fu_code_7; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_8_0 = io_wakeup_ports_0_bits_uop_fu_code_8; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_9_0 = io_wakeup_ports_0_bits_uop_fu_code_9; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iw_issued_0 = io_wakeup_ports_0_bits_uop_iw_issued; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iw_issued_partial_agen_0 = io_wakeup_ports_0_bits_uop_iw_issued_partial_agen; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen_0 = io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_iw_p1_speculative_child_0 = io_wakeup_ports_0_bits_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_iw_p2_speculative_child_0 = io_wakeup_ports_0_bits_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint_0 = io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint_0 = io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint_0 = io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_dis_col_sel_0 = io_wakeup_ports_0_bits_uop_dis_col_sel; // @[issue-slot.scala:49:7] wire [15:0] io_wakeup_ports_0_bits_uop_br_mask_0 = io_wakeup_ports_0_bits_uop_br_mask; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_0_bits_uop_br_tag_0 = io_wakeup_ports_0_bits_uop_br_tag; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_0_bits_uop_br_type_0 = io_wakeup_ports_0_bits_uop_br_type; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_sfb_0 = io_wakeup_ports_0_bits_uop_is_sfb; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_fence_0 = io_wakeup_ports_0_bits_uop_is_fence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_fencei_0 = io_wakeup_ports_0_bits_uop_is_fencei; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_sfence_0 = io_wakeup_ports_0_bits_uop_is_sfence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_amo_0 = io_wakeup_ports_0_bits_uop_is_amo; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_eret_0 = io_wakeup_ports_0_bits_uop_is_eret; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_sys_pc2epc_0 = io_wakeup_ports_0_bits_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_rocc_0 = io_wakeup_ports_0_bits_uop_is_rocc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_mov_0 = io_wakeup_ports_0_bits_uop_is_mov; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_0_bits_uop_ftq_idx_0 = io_wakeup_ports_0_bits_uop_ftq_idx; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_edge_inst_0 = io_wakeup_ports_0_bits_uop_edge_inst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_0_bits_uop_pc_lob_0 = io_wakeup_ports_0_bits_uop_pc_lob; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_taken_0 = io_wakeup_ports_0_bits_uop_taken; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_imm_rename_0 = io_wakeup_ports_0_bits_uop_imm_rename; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_imm_sel_0 = io_wakeup_ports_0_bits_uop_imm_sel; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_0_bits_uop_pimm_0 = io_wakeup_ports_0_bits_uop_pimm; // @[issue-slot.scala:49:7] wire [19:0] io_wakeup_ports_0_bits_uop_imm_packed_0 = io_wakeup_ports_0_bits_uop_imm_packed; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_op1_sel_0 = io_wakeup_ports_0_bits_uop_op1_sel; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_op2_sel_0 = io_wakeup_ports_0_bits_uop_op2_sel; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_ldst_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_wen_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_ren1_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_ren2_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_ren3_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_swap12_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_swap23_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_fromint_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_toint_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_fma_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_div_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_div; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_wflags_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_vec_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_0_bits_uop_rob_idx_0 = io_wakeup_ports_0_bits_uop_rob_idx; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_0_bits_uop_ldq_idx_0 = io_wakeup_ports_0_bits_uop_ldq_idx; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_0_bits_uop_stq_idx_0 = io_wakeup_ports_0_bits_uop_stq_idx; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_rxq_idx_0 = io_wakeup_ports_0_bits_uop_rxq_idx; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_0_bits_uop_pdst_0 = io_wakeup_ports_0_bits_uop_pdst; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_0_bits_uop_prs1_0 = io_wakeup_ports_0_bits_uop_prs1; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_0_bits_uop_prs2_0 = io_wakeup_ports_0_bits_uop_prs2; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_0_bits_uop_prs3_0 = io_wakeup_ports_0_bits_uop_prs3; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_0_bits_uop_ppred_0 = io_wakeup_ports_0_bits_uop_ppred; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_prs1_busy_0 = io_wakeup_ports_0_bits_uop_prs1_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_prs2_busy_0 = io_wakeup_ports_0_bits_uop_prs2_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_prs3_busy_0 = io_wakeup_ports_0_bits_uop_prs3_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_ppred_busy_0 = io_wakeup_ports_0_bits_uop_ppred_busy; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_0_bits_uop_stale_pdst_0 = io_wakeup_ports_0_bits_uop_stale_pdst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_exception_0 = io_wakeup_ports_0_bits_uop_exception; // @[issue-slot.scala:49:7] wire [63:0] io_wakeup_ports_0_bits_uop_exc_cause_0 = io_wakeup_ports_0_bits_uop_exc_cause; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_0_bits_uop_mem_cmd_0 = io_wakeup_ports_0_bits_uop_mem_cmd; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_mem_size_0 = io_wakeup_ports_0_bits_uop_mem_size; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_mem_signed_0 = io_wakeup_ports_0_bits_uop_mem_signed; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_uses_ldq_0 = io_wakeup_ports_0_bits_uop_uses_ldq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_uses_stq_0 = io_wakeup_ports_0_bits_uop_uses_stq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_unique_0 = io_wakeup_ports_0_bits_uop_is_unique; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_flush_on_commit_0 = io_wakeup_ports_0_bits_uop_flush_on_commit; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_csr_cmd_0 = io_wakeup_ports_0_bits_uop_csr_cmd; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_ldst_is_rs1_0 = io_wakeup_ports_0_bits_uop_ldst_is_rs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_0_bits_uop_ldst_0 = io_wakeup_ports_0_bits_uop_ldst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_0_bits_uop_lrs1_0 = io_wakeup_ports_0_bits_uop_lrs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_0_bits_uop_lrs2_0 = io_wakeup_ports_0_bits_uop_lrs2; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_0_bits_uop_lrs3_0 = io_wakeup_ports_0_bits_uop_lrs3; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_dst_rtype_0 = io_wakeup_ports_0_bits_uop_dst_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_lrs1_rtype_0 = io_wakeup_ports_0_bits_uop_lrs1_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_lrs2_rtype_0 = io_wakeup_ports_0_bits_uop_lrs2_rtype; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_frs3_en_0 = io_wakeup_ports_0_bits_uop_frs3_en; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fcn_dw_0 = io_wakeup_ports_0_bits_uop_fcn_dw; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_0_bits_uop_fcn_op_0 = io_wakeup_ports_0_bits_uop_fcn_op; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_val_0 = io_wakeup_ports_0_bits_uop_fp_val; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_fp_rm_0 = io_wakeup_ports_0_bits_uop_fp_rm; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_fp_typ_0 = io_wakeup_ports_0_bits_uop_fp_typ; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_xcpt_pf_if_0 = io_wakeup_ports_0_bits_uop_xcpt_pf_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_xcpt_ae_if_0 = io_wakeup_ports_0_bits_uop_xcpt_ae_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_xcpt_ma_if_0 = io_wakeup_ports_0_bits_uop_xcpt_ma_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_bp_debug_if_0 = io_wakeup_ports_0_bits_uop_bp_debug_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_bp_xcpt_if_0 = io_wakeup_ports_0_bits_uop_bp_xcpt_if; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_debug_fsrc_0 = io_wakeup_ports_0_bits_uop_debug_fsrc; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_debug_tsrc_0 = io_wakeup_ports_0_bits_uop_debug_tsrc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_bypassable_0 = io_wakeup_ports_0_bits_bypassable; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_speculative_mask_0 = io_wakeup_ports_0_bits_speculative_mask; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_rebusy_0 = io_wakeup_ports_0_bits_rebusy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_valid_0 = io_wakeup_ports_1_valid; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_1_bits_uop_inst_0 = io_wakeup_ports_1_bits_uop_inst; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_1_bits_uop_debug_inst_0 = io_wakeup_ports_1_bits_uop_debug_inst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_rvc_0 = io_wakeup_ports_1_bits_uop_is_rvc; // @[issue-slot.scala:49:7] wire [39:0] io_wakeup_ports_1_bits_uop_debug_pc_0 = io_wakeup_ports_1_bits_uop_debug_pc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iq_type_0_0 = io_wakeup_ports_1_bits_uop_iq_type_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iq_type_1_0 = io_wakeup_ports_1_bits_uop_iq_type_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iq_type_2_0 = io_wakeup_ports_1_bits_uop_iq_type_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iq_type_3_0 = io_wakeup_ports_1_bits_uop_iq_type_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_0_0 = io_wakeup_ports_1_bits_uop_fu_code_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_1_0 = io_wakeup_ports_1_bits_uop_fu_code_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_2_0 = io_wakeup_ports_1_bits_uop_fu_code_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_3_0 = io_wakeup_ports_1_bits_uop_fu_code_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_4_0 = io_wakeup_ports_1_bits_uop_fu_code_4; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_5_0 = io_wakeup_ports_1_bits_uop_fu_code_5; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_6_0 = io_wakeup_ports_1_bits_uop_fu_code_6; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_7_0 = io_wakeup_ports_1_bits_uop_fu_code_7; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_8_0 = io_wakeup_ports_1_bits_uop_fu_code_8; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_9_0 = io_wakeup_ports_1_bits_uop_fu_code_9; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iw_issued_0 = io_wakeup_ports_1_bits_uop_iw_issued; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iw_issued_partial_agen_0 = io_wakeup_ports_1_bits_uop_iw_issued_partial_agen; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen_0 = io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_iw_p1_speculative_child_0 = io_wakeup_ports_1_bits_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_iw_p2_speculative_child_0 = io_wakeup_ports_1_bits_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint_0 = io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint_0 = io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint_0 = io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_dis_col_sel_0 = io_wakeup_ports_1_bits_uop_dis_col_sel; // @[issue-slot.scala:49:7] wire [15:0] io_wakeup_ports_1_bits_uop_br_mask_0 = io_wakeup_ports_1_bits_uop_br_mask; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_1_bits_uop_br_tag_0 = io_wakeup_ports_1_bits_uop_br_tag; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_1_bits_uop_br_type_0 = io_wakeup_ports_1_bits_uop_br_type; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_sfb_0 = io_wakeup_ports_1_bits_uop_is_sfb; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_fence_0 = io_wakeup_ports_1_bits_uop_is_fence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_fencei_0 = io_wakeup_ports_1_bits_uop_is_fencei; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_sfence_0 = io_wakeup_ports_1_bits_uop_is_sfence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_amo_0 = io_wakeup_ports_1_bits_uop_is_amo; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_eret_0 = io_wakeup_ports_1_bits_uop_is_eret; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_sys_pc2epc_0 = io_wakeup_ports_1_bits_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_rocc_0 = io_wakeup_ports_1_bits_uop_is_rocc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_mov_0 = io_wakeup_ports_1_bits_uop_is_mov; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_1_bits_uop_ftq_idx_0 = io_wakeup_ports_1_bits_uop_ftq_idx; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_edge_inst_0 = io_wakeup_ports_1_bits_uop_edge_inst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_1_bits_uop_pc_lob_0 = io_wakeup_ports_1_bits_uop_pc_lob; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_taken_0 = io_wakeup_ports_1_bits_uop_taken; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_imm_rename_0 = io_wakeup_ports_1_bits_uop_imm_rename; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_imm_sel_0 = io_wakeup_ports_1_bits_uop_imm_sel; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_1_bits_uop_pimm_0 = io_wakeup_ports_1_bits_uop_pimm; // @[issue-slot.scala:49:7] wire [19:0] io_wakeup_ports_1_bits_uop_imm_packed_0 = io_wakeup_ports_1_bits_uop_imm_packed; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_op1_sel_0 = io_wakeup_ports_1_bits_uop_op1_sel; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_op2_sel_0 = io_wakeup_ports_1_bits_uop_op2_sel; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_ldst_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_wen_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_ren1_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_ren2_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_ren3_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_swap12_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_swap23_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_fromint_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_toint_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_fma_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_div_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_div; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_wflags_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_vec_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_1_bits_uop_rob_idx_0 = io_wakeup_ports_1_bits_uop_rob_idx; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_1_bits_uop_ldq_idx_0 = io_wakeup_ports_1_bits_uop_ldq_idx; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_1_bits_uop_stq_idx_0 = io_wakeup_ports_1_bits_uop_stq_idx; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_rxq_idx_0 = io_wakeup_ports_1_bits_uop_rxq_idx; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_1_bits_uop_pdst_0 = io_wakeup_ports_1_bits_uop_pdst; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_1_bits_uop_prs1_0 = io_wakeup_ports_1_bits_uop_prs1; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_1_bits_uop_prs2_0 = io_wakeup_ports_1_bits_uop_prs2; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_1_bits_uop_prs3_0 = io_wakeup_ports_1_bits_uop_prs3; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_1_bits_uop_ppred_0 = io_wakeup_ports_1_bits_uop_ppred; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_prs1_busy_0 = io_wakeup_ports_1_bits_uop_prs1_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_prs2_busy_0 = io_wakeup_ports_1_bits_uop_prs2_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_prs3_busy_0 = io_wakeup_ports_1_bits_uop_prs3_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_ppred_busy_0 = io_wakeup_ports_1_bits_uop_ppred_busy; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_1_bits_uop_stale_pdst_0 = io_wakeup_ports_1_bits_uop_stale_pdst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_exception_0 = io_wakeup_ports_1_bits_uop_exception; // @[issue-slot.scala:49:7] wire [63:0] io_wakeup_ports_1_bits_uop_exc_cause_0 = io_wakeup_ports_1_bits_uop_exc_cause; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_1_bits_uop_mem_cmd_0 = io_wakeup_ports_1_bits_uop_mem_cmd; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_mem_size_0 = io_wakeup_ports_1_bits_uop_mem_size; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_mem_signed_0 = io_wakeup_ports_1_bits_uop_mem_signed; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_uses_ldq_0 = io_wakeup_ports_1_bits_uop_uses_ldq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_uses_stq_0 = io_wakeup_ports_1_bits_uop_uses_stq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_unique_0 = io_wakeup_ports_1_bits_uop_is_unique; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_flush_on_commit_0 = io_wakeup_ports_1_bits_uop_flush_on_commit; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_csr_cmd_0 = io_wakeup_ports_1_bits_uop_csr_cmd; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_ldst_is_rs1_0 = io_wakeup_ports_1_bits_uop_ldst_is_rs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_1_bits_uop_ldst_0 = io_wakeup_ports_1_bits_uop_ldst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_1_bits_uop_lrs1_0 = io_wakeup_ports_1_bits_uop_lrs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_1_bits_uop_lrs2_0 = io_wakeup_ports_1_bits_uop_lrs2; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_1_bits_uop_lrs3_0 = io_wakeup_ports_1_bits_uop_lrs3; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_dst_rtype_0 = io_wakeup_ports_1_bits_uop_dst_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_lrs1_rtype_0 = io_wakeup_ports_1_bits_uop_lrs1_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_lrs2_rtype_0 = io_wakeup_ports_1_bits_uop_lrs2_rtype; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_frs3_en_0 = io_wakeup_ports_1_bits_uop_frs3_en; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fcn_dw_0 = io_wakeup_ports_1_bits_uop_fcn_dw; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_1_bits_uop_fcn_op_0 = io_wakeup_ports_1_bits_uop_fcn_op; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_val_0 = io_wakeup_ports_1_bits_uop_fp_val; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_fp_rm_0 = io_wakeup_ports_1_bits_uop_fp_rm; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_fp_typ_0 = io_wakeup_ports_1_bits_uop_fp_typ; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_xcpt_pf_if_0 = io_wakeup_ports_1_bits_uop_xcpt_pf_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_xcpt_ae_if_0 = io_wakeup_ports_1_bits_uop_xcpt_ae_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_xcpt_ma_if_0 = io_wakeup_ports_1_bits_uop_xcpt_ma_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_bp_debug_if_0 = io_wakeup_ports_1_bits_uop_bp_debug_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_bp_xcpt_if_0 = io_wakeup_ports_1_bits_uop_bp_xcpt_if; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_debug_fsrc_0 = io_wakeup_ports_1_bits_uop_debug_fsrc; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_debug_tsrc_0 = io_wakeup_ports_1_bits_uop_debug_tsrc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_valid_0 = io_wakeup_ports_2_valid; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_2_bits_uop_inst_0 = io_wakeup_ports_2_bits_uop_inst; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_2_bits_uop_debug_inst_0 = io_wakeup_ports_2_bits_uop_debug_inst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_rvc_0 = io_wakeup_ports_2_bits_uop_is_rvc; // @[issue-slot.scala:49:7] wire [39:0] io_wakeup_ports_2_bits_uop_debug_pc_0 = io_wakeup_ports_2_bits_uop_debug_pc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iq_type_0_0 = io_wakeup_ports_2_bits_uop_iq_type_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iq_type_1_0 = io_wakeup_ports_2_bits_uop_iq_type_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iq_type_2_0 = io_wakeup_ports_2_bits_uop_iq_type_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iq_type_3_0 = io_wakeup_ports_2_bits_uop_iq_type_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_0_0 = io_wakeup_ports_2_bits_uop_fu_code_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_1_0 = io_wakeup_ports_2_bits_uop_fu_code_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_2_0 = io_wakeup_ports_2_bits_uop_fu_code_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_3_0 = io_wakeup_ports_2_bits_uop_fu_code_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_4_0 = io_wakeup_ports_2_bits_uop_fu_code_4; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_5_0 = io_wakeup_ports_2_bits_uop_fu_code_5; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_6_0 = io_wakeup_ports_2_bits_uop_fu_code_6; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_7_0 = io_wakeup_ports_2_bits_uop_fu_code_7; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_8_0 = io_wakeup_ports_2_bits_uop_fu_code_8; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_9_0 = io_wakeup_ports_2_bits_uop_fu_code_9; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iw_issued_0 = io_wakeup_ports_2_bits_uop_iw_issued; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_2_bits_uop_iw_p1_speculative_child_0 = io_wakeup_ports_2_bits_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_2_bits_uop_iw_p2_speculative_child_0 = io_wakeup_ports_2_bits_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iw_p1_bypass_hint_0 = io_wakeup_ports_2_bits_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iw_p2_bypass_hint_0 = io_wakeup_ports_2_bits_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iw_p3_bypass_hint_0 = io_wakeup_ports_2_bits_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_2_bits_uop_dis_col_sel_0 = io_wakeup_ports_2_bits_uop_dis_col_sel; // @[issue-slot.scala:49:7] wire [15:0] io_wakeup_ports_2_bits_uop_br_mask_0 = io_wakeup_ports_2_bits_uop_br_mask; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_2_bits_uop_br_tag_0 = io_wakeup_ports_2_bits_uop_br_tag; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_2_bits_uop_br_type_0 = io_wakeup_ports_2_bits_uop_br_type; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_sfb_0 = io_wakeup_ports_2_bits_uop_is_sfb; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_fence_0 = io_wakeup_ports_2_bits_uop_is_fence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_fencei_0 = io_wakeup_ports_2_bits_uop_is_fencei; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_sfence_0 = io_wakeup_ports_2_bits_uop_is_sfence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_amo_0 = io_wakeup_ports_2_bits_uop_is_amo; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_eret_0 = io_wakeup_ports_2_bits_uop_is_eret; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_sys_pc2epc_0 = io_wakeup_ports_2_bits_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_rocc_0 = io_wakeup_ports_2_bits_uop_is_rocc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_mov_0 = io_wakeup_ports_2_bits_uop_is_mov; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_2_bits_uop_ftq_idx_0 = io_wakeup_ports_2_bits_uop_ftq_idx; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_edge_inst_0 = io_wakeup_ports_2_bits_uop_edge_inst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_2_bits_uop_pc_lob_0 = io_wakeup_ports_2_bits_uop_pc_lob; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_taken_0 = io_wakeup_ports_2_bits_uop_taken; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_imm_rename_0 = io_wakeup_ports_2_bits_uop_imm_rename; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_2_bits_uop_imm_sel_0 = io_wakeup_ports_2_bits_uop_imm_sel; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_2_bits_uop_pimm_0 = io_wakeup_ports_2_bits_uop_pimm; // @[issue-slot.scala:49:7] wire [19:0] io_wakeup_ports_2_bits_uop_imm_packed_0 = io_wakeup_ports_2_bits_uop_imm_packed; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_op1_sel_0 = io_wakeup_ports_2_bits_uop_op1_sel; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_2_bits_uop_op2_sel_0 = io_wakeup_ports_2_bits_uop_op2_sel; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_ldst_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_wen_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_ren1_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_ren2_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_ren3_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_swap12_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_swap23_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_fromint_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_toint_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_fma_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_div_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_div; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_sqrt_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_wflags_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_vec_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_2_bits_uop_rob_idx_0 = io_wakeup_ports_2_bits_uop_rob_idx; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_2_bits_uop_ldq_idx_0 = io_wakeup_ports_2_bits_uop_ldq_idx; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_2_bits_uop_stq_idx_0 = io_wakeup_ports_2_bits_uop_stq_idx; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_rxq_idx_0 = io_wakeup_ports_2_bits_uop_rxq_idx; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_2_bits_uop_pdst_0 = io_wakeup_ports_2_bits_uop_pdst; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_2_bits_uop_prs1_0 = io_wakeup_ports_2_bits_uop_prs1; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_2_bits_uop_prs2_0 = io_wakeup_ports_2_bits_uop_prs2; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_2_bits_uop_prs3_0 = io_wakeup_ports_2_bits_uop_prs3; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_2_bits_uop_ppred_0 = io_wakeup_ports_2_bits_uop_ppred; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_prs1_busy_0 = io_wakeup_ports_2_bits_uop_prs1_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_prs2_busy_0 = io_wakeup_ports_2_bits_uop_prs2_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_prs3_busy_0 = io_wakeup_ports_2_bits_uop_prs3_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_ppred_busy_0 = io_wakeup_ports_2_bits_uop_ppred_busy; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_2_bits_uop_stale_pdst_0 = io_wakeup_ports_2_bits_uop_stale_pdst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_exception_0 = io_wakeup_ports_2_bits_uop_exception; // @[issue-slot.scala:49:7] wire [63:0] io_wakeup_ports_2_bits_uop_exc_cause_0 = io_wakeup_ports_2_bits_uop_exc_cause; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_2_bits_uop_mem_cmd_0 = io_wakeup_ports_2_bits_uop_mem_cmd; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_mem_size_0 = io_wakeup_ports_2_bits_uop_mem_size; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_mem_signed_0 = io_wakeup_ports_2_bits_uop_mem_signed; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_uses_ldq_0 = io_wakeup_ports_2_bits_uop_uses_ldq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_uses_stq_0 = io_wakeup_ports_2_bits_uop_uses_stq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_unique_0 = io_wakeup_ports_2_bits_uop_is_unique; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_flush_on_commit_0 = io_wakeup_ports_2_bits_uop_flush_on_commit; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_2_bits_uop_csr_cmd_0 = io_wakeup_ports_2_bits_uop_csr_cmd; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_ldst_is_rs1_0 = io_wakeup_ports_2_bits_uop_ldst_is_rs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_2_bits_uop_ldst_0 = io_wakeup_ports_2_bits_uop_ldst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_2_bits_uop_lrs1_0 = io_wakeup_ports_2_bits_uop_lrs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_2_bits_uop_lrs2_0 = io_wakeup_ports_2_bits_uop_lrs2; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_2_bits_uop_lrs3_0 = io_wakeup_ports_2_bits_uop_lrs3; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_dst_rtype_0 = io_wakeup_ports_2_bits_uop_dst_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_lrs1_rtype_0 = io_wakeup_ports_2_bits_uop_lrs1_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_lrs2_rtype_0 = io_wakeup_ports_2_bits_uop_lrs2_rtype; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_frs3_en_0 = io_wakeup_ports_2_bits_uop_frs3_en; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fcn_dw_0 = io_wakeup_ports_2_bits_uop_fcn_dw; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_2_bits_uop_fcn_op_0 = io_wakeup_ports_2_bits_uop_fcn_op; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_val_0 = io_wakeup_ports_2_bits_uop_fp_val; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_2_bits_uop_fp_rm_0 = io_wakeup_ports_2_bits_uop_fp_rm; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_fp_typ_0 = io_wakeup_ports_2_bits_uop_fp_typ; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_xcpt_pf_if_0 = io_wakeup_ports_2_bits_uop_xcpt_pf_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_xcpt_ae_if_0 = io_wakeup_ports_2_bits_uop_xcpt_ae_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_xcpt_ma_if_0 = io_wakeup_ports_2_bits_uop_xcpt_ma_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_bp_debug_if_0 = io_wakeup_ports_2_bits_uop_bp_debug_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_bp_xcpt_if_0 = io_wakeup_ports_2_bits_uop_bp_xcpt_if; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_2_bits_uop_debug_fsrc_0 = io_wakeup_ports_2_bits_uop_debug_fsrc; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_2_bits_uop_debug_tsrc_0 = io_wakeup_ports_2_bits_uop_debug_tsrc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_valid_0 = io_wakeup_ports_3_valid; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_3_bits_uop_inst_0 = io_wakeup_ports_3_bits_uop_inst; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_3_bits_uop_debug_inst_0 = io_wakeup_ports_3_bits_uop_debug_inst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_rvc_0 = io_wakeup_ports_3_bits_uop_is_rvc; // @[issue-slot.scala:49:7] wire [39:0] io_wakeup_ports_3_bits_uop_debug_pc_0 = io_wakeup_ports_3_bits_uop_debug_pc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iq_type_0_0 = io_wakeup_ports_3_bits_uop_iq_type_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iq_type_1_0 = io_wakeup_ports_3_bits_uop_iq_type_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iq_type_2_0 = io_wakeup_ports_3_bits_uop_iq_type_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iq_type_3_0 = io_wakeup_ports_3_bits_uop_iq_type_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_0_0 = io_wakeup_ports_3_bits_uop_fu_code_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_1_0 = io_wakeup_ports_3_bits_uop_fu_code_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_2_0 = io_wakeup_ports_3_bits_uop_fu_code_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_3_0 = io_wakeup_ports_3_bits_uop_fu_code_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_4_0 = io_wakeup_ports_3_bits_uop_fu_code_4; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_5_0 = io_wakeup_ports_3_bits_uop_fu_code_5; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_6_0 = io_wakeup_ports_3_bits_uop_fu_code_6; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_7_0 = io_wakeup_ports_3_bits_uop_fu_code_7; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_8_0 = io_wakeup_ports_3_bits_uop_fu_code_8; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_9_0 = io_wakeup_ports_3_bits_uop_fu_code_9; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iw_issued_0 = io_wakeup_ports_3_bits_uop_iw_issued; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_3_bits_uop_iw_p1_speculative_child_0 = io_wakeup_ports_3_bits_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_3_bits_uop_iw_p2_speculative_child_0 = io_wakeup_ports_3_bits_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iw_p1_bypass_hint_0 = io_wakeup_ports_3_bits_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iw_p2_bypass_hint_0 = io_wakeup_ports_3_bits_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iw_p3_bypass_hint_0 = io_wakeup_ports_3_bits_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_3_bits_uop_dis_col_sel_0 = io_wakeup_ports_3_bits_uop_dis_col_sel; // @[issue-slot.scala:49:7] wire [15:0] io_wakeup_ports_3_bits_uop_br_mask_0 = io_wakeup_ports_3_bits_uop_br_mask; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_3_bits_uop_br_tag_0 = io_wakeup_ports_3_bits_uop_br_tag; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_3_bits_uop_br_type_0 = io_wakeup_ports_3_bits_uop_br_type; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_sfb_0 = io_wakeup_ports_3_bits_uop_is_sfb; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_fence_0 = io_wakeup_ports_3_bits_uop_is_fence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_fencei_0 = io_wakeup_ports_3_bits_uop_is_fencei; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_sfence_0 = io_wakeup_ports_3_bits_uop_is_sfence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_amo_0 = io_wakeup_ports_3_bits_uop_is_amo; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_eret_0 = io_wakeup_ports_3_bits_uop_is_eret; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_sys_pc2epc_0 = io_wakeup_ports_3_bits_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_rocc_0 = io_wakeup_ports_3_bits_uop_is_rocc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_mov_0 = io_wakeup_ports_3_bits_uop_is_mov; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_3_bits_uop_ftq_idx_0 = io_wakeup_ports_3_bits_uop_ftq_idx; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_edge_inst_0 = io_wakeup_ports_3_bits_uop_edge_inst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_3_bits_uop_pc_lob_0 = io_wakeup_ports_3_bits_uop_pc_lob; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_taken_0 = io_wakeup_ports_3_bits_uop_taken; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_imm_rename_0 = io_wakeup_ports_3_bits_uop_imm_rename; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_3_bits_uop_imm_sel_0 = io_wakeup_ports_3_bits_uop_imm_sel; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_3_bits_uop_pimm_0 = io_wakeup_ports_3_bits_uop_pimm; // @[issue-slot.scala:49:7] wire [19:0] io_wakeup_ports_3_bits_uop_imm_packed_0 = io_wakeup_ports_3_bits_uop_imm_packed; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_op1_sel_0 = io_wakeup_ports_3_bits_uop_op1_sel; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_3_bits_uop_op2_sel_0 = io_wakeup_ports_3_bits_uop_op2_sel; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_ldst_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_wen_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_ren1_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_ren2_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_ren3_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_swap12_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_swap23_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_fromint_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_toint_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_fma_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_div_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_div; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_sqrt_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_wflags_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_vec_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_3_bits_uop_rob_idx_0 = io_wakeup_ports_3_bits_uop_rob_idx; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_3_bits_uop_ldq_idx_0 = io_wakeup_ports_3_bits_uop_ldq_idx; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_3_bits_uop_stq_idx_0 = io_wakeup_ports_3_bits_uop_stq_idx; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_rxq_idx_0 = io_wakeup_ports_3_bits_uop_rxq_idx; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_3_bits_uop_pdst_0 = io_wakeup_ports_3_bits_uop_pdst; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_3_bits_uop_prs1_0 = io_wakeup_ports_3_bits_uop_prs1; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_3_bits_uop_prs2_0 = io_wakeup_ports_3_bits_uop_prs2; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_3_bits_uop_prs3_0 = io_wakeup_ports_3_bits_uop_prs3; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_3_bits_uop_ppred_0 = io_wakeup_ports_3_bits_uop_ppred; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_prs1_busy_0 = io_wakeup_ports_3_bits_uop_prs1_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_prs2_busy_0 = io_wakeup_ports_3_bits_uop_prs2_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_prs3_busy_0 = io_wakeup_ports_3_bits_uop_prs3_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_ppred_busy_0 = io_wakeup_ports_3_bits_uop_ppred_busy; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_3_bits_uop_stale_pdst_0 = io_wakeup_ports_3_bits_uop_stale_pdst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_exception_0 = io_wakeup_ports_3_bits_uop_exception; // @[issue-slot.scala:49:7] wire [63:0] io_wakeup_ports_3_bits_uop_exc_cause_0 = io_wakeup_ports_3_bits_uop_exc_cause; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_3_bits_uop_mem_cmd_0 = io_wakeup_ports_3_bits_uop_mem_cmd; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_mem_size_0 = io_wakeup_ports_3_bits_uop_mem_size; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_mem_signed_0 = io_wakeup_ports_3_bits_uop_mem_signed; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_uses_ldq_0 = io_wakeup_ports_3_bits_uop_uses_ldq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_uses_stq_0 = io_wakeup_ports_3_bits_uop_uses_stq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_unique_0 = io_wakeup_ports_3_bits_uop_is_unique; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_flush_on_commit_0 = io_wakeup_ports_3_bits_uop_flush_on_commit; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_3_bits_uop_csr_cmd_0 = io_wakeup_ports_3_bits_uop_csr_cmd; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_ldst_is_rs1_0 = io_wakeup_ports_3_bits_uop_ldst_is_rs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_3_bits_uop_ldst_0 = io_wakeup_ports_3_bits_uop_ldst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_3_bits_uop_lrs1_0 = io_wakeup_ports_3_bits_uop_lrs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_3_bits_uop_lrs2_0 = io_wakeup_ports_3_bits_uop_lrs2; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_3_bits_uop_lrs3_0 = io_wakeup_ports_3_bits_uop_lrs3; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_dst_rtype_0 = io_wakeup_ports_3_bits_uop_dst_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_lrs1_rtype_0 = io_wakeup_ports_3_bits_uop_lrs1_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_lrs2_rtype_0 = io_wakeup_ports_3_bits_uop_lrs2_rtype; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_frs3_en_0 = io_wakeup_ports_3_bits_uop_frs3_en; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fcn_dw_0 = io_wakeup_ports_3_bits_uop_fcn_dw; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_3_bits_uop_fcn_op_0 = io_wakeup_ports_3_bits_uop_fcn_op; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_val_0 = io_wakeup_ports_3_bits_uop_fp_val; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_3_bits_uop_fp_rm_0 = io_wakeup_ports_3_bits_uop_fp_rm; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_fp_typ_0 = io_wakeup_ports_3_bits_uop_fp_typ; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_xcpt_pf_if_0 = io_wakeup_ports_3_bits_uop_xcpt_pf_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_xcpt_ae_if_0 = io_wakeup_ports_3_bits_uop_xcpt_ae_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_xcpt_ma_if_0 = io_wakeup_ports_3_bits_uop_xcpt_ma_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_bp_debug_if_0 = io_wakeup_ports_3_bits_uop_bp_debug_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_bp_xcpt_if_0 = io_wakeup_ports_3_bits_uop_bp_xcpt_if; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_3_bits_uop_debug_fsrc_0 = io_wakeup_ports_3_bits_uop_debug_fsrc; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_3_bits_uop_debug_tsrc_0 = io_wakeup_ports_3_bits_uop_debug_tsrc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_valid_0 = io_wakeup_ports_4_valid; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_4_bits_uop_inst_0 = io_wakeup_ports_4_bits_uop_inst; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_4_bits_uop_debug_inst_0 = io_wakeup_ports_4_bits_uop_debug_inst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_is_rvc_0 = io_wakeup_ports_4_bits_uop_is_rvc; // @[issue-slot.scala:49:7] wire [39:0] io_wakeup_ports_4_bits_uop_debug_pc_0 = io_wakeup_ports_4_bits_uop_debug_pc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_iq_type_0_0 = io_wakeup_ports_4_bits_uop_iq_type_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_iq_type_1_0 = io_wakeup_ports_4_bits_uop_iq_type_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_iq_type_2_0 = io_wakeup_ports_4_bits_uop_iq_type_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_iq_type_3_0 = io_wakeup_ports_4_bits_uop_iq_type_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fu_code_0_0 = io_wakeup_ports_4_bits_uop_fu_code_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fu_code_1_0 = io_wakeup_ports_4_bits_uop_fu_code_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fu_code_2_0 = io_wakeup_ports_4_bits_uop_fu_code_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fu_code_3_0 = io_wakeup_ports_4_bits_uop_fu_code_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fu_code_4_0 = io_wakeup_ports_4_bits_uop_fu_code_4; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fu_code_5_0 = io_wakeup_ports_4_bits_uop_fu_code_5; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fu_code_6_0 = io_wakeup_ports_4_bits_uop_fu_code_6; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fu_code_7_0 = io_wakeup_ports_4_bits_uop_fu_code_7; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fu_code_8_0 = io_wakeup_ports_4_bits_uop_fu_code_8; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fu_code_9_0 = io_wakeup_ports_4_bits_uop_fu_code_9; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_iw_issued_0 = io_wakeup_ports_4_bits_uop_iw_issued; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_4_bits_uop_iw_p1_speculative_child_0 = io_wakeup_ports_4_bits_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_4_bits_uop_iw_p2_speculative_child_0 = io_wakeup_ports_4_bits_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_iw_p1_bypass_hint_0 = io_wakeup_ports_4_bits_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_iw_p2_bypass_hint_0 = io_wakeup_ports_4_bits_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_iw_p3_bypass_hint_0 = io_wakeup_ports_4_bits_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_4_bits_uop_dis_col_sel_0 = io_wakeup_ports_4_bits_uop_dis_col_sel; // @[issue-slot.scala:49:7] wire [15:0] io_wakeup_ports_4_bits_uop_br_mask_0 = io_wakeup_ports_4_bits_uop_br_mask; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_4_bits_uop_br_tag_0 = io_wakeup_ports_4_bits_uop_br_tag; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_4_bits_uop_br_type_0 = io_wakeup_ports_4_bits_uop_br_type; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_is_sfb_0 = io_wakeup_ports_4_bits_uop_is_sfb; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_is_fence_0 = io_wakeup_ports_4_bits_uop_is_fence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_is_fencei_0 = io_wakeup_ports_4_bits_uop_is_fencei; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_is_sfence_0 = io_wakeup_ports_4_bits_uop_is_sfence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_is_amo_0 = io_wakeup_ports_4_bits_uop_is_amo; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_is_eret_0 = io_wakeup_ports_4_bits_uop_is_eret; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_is_sys_pc2epc_0 = io_wakeup_ports_4_bits_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_is_rocc_0 = io_wakeup_ports_4_bits_uop_is_rocc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_is_mov_0 = io_wakeup_ports_4_bits_uop_is_mov; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_4_bits_uop_ftq_idx_0 = io_wakeup_ports_4_bits_uop_ftq_idx; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_edge_inst_0 = io_wakeup_ports_4_bits_uop_edge_inst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_4_bits_uop_pc_lob_0 = io_wakeup_ports_4_bits_uop_pc_lob; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_taken_0 = io_wakeup_ports_4_bits_uop_taken; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_imm_rename_0 = io_wakeup_ports_4_bits_uop_imm_rename; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_4_bits_uop_imm_sel_0 = io_wakeup_ports_4_bits_uop_imm_sel; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_4_bits_uop_pimm_0 = io_wakeup_ports_4_bits_uop_pimm; // @[issue-slot.scala:49:7] wire [19:0] io_wakeup_ports_4_bits_uop_imm_packed_0 = io_wakeup_ports_4_bits_uop_imm_packed; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_4_bits_uop_op1_sel_0 = io_wakeup_ports_4_bits_uop_op1_sel; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_4_bits_uop_op2_sel_0 = io_wakeup_ports_4_bits_uop_op2_sel; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_ldst_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_wen_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_ren1_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_ren2_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_ren3_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_swap12_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_swap23_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_4_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_4_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_fromint_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_toint_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_fastpipe_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_fma_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_div_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_div; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_sqrt_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_wflags_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_vec_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_4_bits_uop_rob_idx_0 = io_wakeup_ports_4_bits_uop_rob_idx; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_4_bits_uop_ldq_idx_0 = io_wakeup_ports_4_bits_uop_ldq_idx; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_4_bits_uop_stq_idx_0 = io_wakeup_ports_4_bits_uop_stq_idx; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_4_bits_uop_rxq_idx_0 = io_wakeup_ports_4_bits_uop_rxq_idx; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_4_bits_uop_pdst_0 = io_wakeup_ports_4_bits_uop_pdst; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_4_bits_uop_prs1_0 = io_wakeup_ports_4_bits_uop_prs1; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_4_bits_uop_prs2_0 = io_wakeup_ports_4_bits_uop_prs2; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_4_bits_uop_prs3_0 = io_wakeup_ports_4_bits_uop_prs3; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_4_bits_uop_ppred_0 = io_wakeup_ports_4_bits_uop_ppred; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_prs1_busy_0 = io_wakeup_ports_4_bits_uop_prs1_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_prs2_busy_0 = io_wakeup_ports_4_bits_uop_prs2_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_prs3_busy_0 = io_wakeup_ports_4_bits_uop_prs3_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_ppred_busy_0 = io_wakeup_ports_4_bits_uop_ppred_busy; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_4_bits_uop_stale_pdst_0 = io_wakeup_ports_4_bits_uop_stale_pdst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_exception_0 = io_wakeup_ports_4_bits_uop_exception; // @[issue-slot.scala:49:7] wire [63:0] io_wakeup_ports_4_bits_uop_exc_cause_0 = io_wakeup_ports_4_bits_uop_exc_cause; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_4_bits_uop_mem_cmd_0 = io_wakeup_ports_4_bits_uop_mem_cmd; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_4_bits_uop_mem_size_0 = io_wakeup_ports_4_bits_uop_mem_size; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_mem_signed_0 = io_wakeup_ports_4_bits_uop_mem_signed; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_uses_ldq_0 = io_wakeup_ports_4_bits_uop_uses_ldq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_uses_stq_0 = io_wakeup_ports_4_bits_uop_uses_stq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_is_unique_0 = io_wakeup_ports_4_bits_uop_is_unique; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_flush_on_commit_0 = io_wakeup_ports_4_bits_uop_flush_on_commit; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_4_bits_uop_csr_cmd_0 = io_wakeup_ports_4_bits_uop_csr_cmd; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_ldst_is_rs1_0 = io_wakeup_ports_4_bits_uop_ldst_is_rs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_4_bits_uop_ldst_0 = io_wakeup_ports_4_bits_uop_ldst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_4_bits_uop_lrs1_0 = io_wakeup_ports_4_bits_uop_lrs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_4_bits_uop_lrs2_0 = io_wakeup_ports_4_bits_uop_lrs2; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_4_bits_uop_lrs3_0 = io_wakeup_ports_4_bits_uop_lrs3; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_4_bits_uop_dst_rtype_0 = io_wakeup_ports_4_bits_uop_dst_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_4_bits_uop_lrs1_rtype_0 = io_wakeup_ports_4_bits_uop_lrs1_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_4_bits_uop_lrs2_rtype_0 = io_wakeup_ports_4_bits_uop_lrs2_rtype; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_frs3_en_0 = io_wakeup_ports_4_bits_uop_frs3_en; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fcn_dw_0 = io_wakeup_ports_4_bits_uop_fcn_dw; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_4_bits_uop_fcn_op_0 = io_wakeup_ports_4_bits_uop_fcn_op; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fp_val_0 = io_wakeup_ports_4_bits_uop_fp_val; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_4_bits_uop_fp_rm_0 = io_wakeup_ports_4_bits_uop_fp_rm; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_4_bits_uop_fp_typ_0 = io_wakeup_ports_4_bits_uop_fp_typ; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_xcpt_pf_if_0 = io_wakeup_ports_4_bits_uop_xcpt_pf_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_xcpt_ae_if_0 = io_wakeup_ports_4_bits_uop_xcpt_ae_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_xcpt_ma_if_0 = io_wakeup_ports_4_bits_uop_xcpt_ma_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_bp_debug_if_0 = io_wakeup_ports_4_bits_uop_bp_debug_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_bp_xcpt_if_0 = io_wakeup_ports_4_bits_uop_bp_xcpt_if; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_4_bits_uop_debug_fsrc_0 = io_wakeup_ports_4_bits_uop_debug_fsrc; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_4_bits_uop_debug_tsrc_0 = io_wakeup_ports_4_bits_uop_debug_tsrc; // @[issue-slot.scala:49:7] wire io_pred_wakeup_port_valid_0 = io_pred_wakeup_port_valid; // @[issue-slot.scala:49:7] wire [4:0] io_pred_wakeup_port_bits_0 = io_pred_wakeup_port_bits; // @[issue-slot.scala:49:7] wire [2:0] io_child_rebusys_0 = io_child_rebusys; // @[issue-slot.scala:49:7] wire io_iss_uop_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:49:7] wire io_iss_uop_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:49:7] wire io_out_uop_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:49:7] wire io_out_uop_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:49:7] wire io_clear = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_bypassable = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_rebusy = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_rebusy = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_rebusy = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_rebusy = 1'h0; // @[issue-slot.scala:49:7] wire next_uop_out_iw_issued_partial_agen = 1'h0; // @[util.scala:104:23] wire next_uop_out_iw_issued_partial_dgen = 1'h0; // @[util.scala:104:23] wire next_uop_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:59:28] wire next_uop_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:59:28] wire prs1_rebusys_1 = 1'h0; // @[issue-slot.scala:102:91] wire prs1_rebusys_2 = 1'h0; // @[issue-slot.scala:102:91] wire prs1_rebusys_3 = 1'h0; // @[issue-slot.scala:102:91] wire prs1_rebusys_4 = 1'h0; // @[issue-slot.scala:102:91] wire prs2_rebusys_1 = 1'h0; // @[issue-slot.scala:103:91] wire prs2_rebusys_2 = 1'h0; // @[issue-slot.scala:103:91] wire prs2_rebusys_3 = 1'h0; // @[issue-slot.scala:103:91] wire prs2_rebusys_4 = 1'h0; // @[issue-slot.scala:103:91] wire _next_uop_iw_p1_bypass_hint_T_1 = 1'h0; // @[Mux.scala:30:73] wire _next_uop_iw_p2_bypass_hint_T_1 = 1'h0; // @[Mux.scala:30:73] wire _next_uop_iw_p3_bypass_hint_T_1 = 1'h0; // @[Mux.scala:30:73] wire _iss_ready_T_6 = 1'h0; // @[issue-slot.scala:136:131] wire agen_ready = 1'h0; // @[issue-slot.scala:137:114] wire dgen_ready = 1'h0; // @[issue-slot.scala:138:114] wire [2:0] io_wakeup_ports_1_bits_speculative_mask = 3'h0; // @[issue-slot.scala:49:7] wire [2:0] _next_uop_iw_p1_speculative_child_T_1 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _next_uop_iw_p2_speculative_child_T_1 = 3'h0; // @[Mux.scala:30:73] wire io_wakeup_ports_2_bits_bypassable = 1'h1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_bypassable = 1'h1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_bypassable = 1'h1; // @[issue-slot.scala:49:7] wire _iss_ready_T_7 = 1'h1; // @[issue-slot.scala:136:110] wire [2:0] io_wakeup_ports_2_bits_speculative_mask = 3'h1; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_3_bits_speculative_mask = 3'h2; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_4_bits_speculative_mask = 3'h4; // @[issue-slot.scala:49:7] wire _io_will_be_valid_T_1; // @[issue-slot.scala:65:34] wire _io_request_T_4; // @[issue-slot.scala:140:51] wire [31:0] next_uop_inst; // @[issue-slot.scala:59:28] wire [31:0] next_uop_debug_inst; // @[issue-slot.scala:59:28] wire next_uop_is_rvc; // @[issue-slot.scala:59:28] wire [39:0] next_uop_debug_pc; // @[issue-slot.scala:59:28] wire next_uop_iq_type_0; // @[issue-slot.scala:59:28] wire next_uop_iq_type_1; // @[issue-slot.scala:59:28] wire next_uop_iq_type_2; // @[issue-slot.scala:59:28] wire next_uop_iq_type_3; // @[issue-slot.scala:59:28] wire next_uop_fu_code_0; // @[issue-slot.scala:59:28] wire next_uop_fu_code_1; // @[issue-slot.scala:59:28] wire next_uop_fu_code_2; // @[issue-slot.scala:59:28] wire next_uop_fu_code_3; // @[issue-slot.scala:59:28] wire next_uop_fu_code_4; // @[issue-slot.scala:59:28] wire next_uop_fu_code_5; // @[issue-slot.scala:59:28] wire next_uop_fu_code_6; // @[issue-slot.scala:59:28] wire next_uop_fu_code_7; // @[issue-slot.scala:59:28] wire next_uop_fu_code_8; // @[issue-slot.scala:59:28] wire next_uop_fu_code_9; // @[issue-slot.scala:59:28] wire next_uop_iw_issued; // @[issue-slot.scala:59:28] wire [2:0] next_uop_iw_p1_speculative_child; // @[issue-slot.scala:59:28] wire [2:0] next_uop_iw_p2_speculative_child; // @[issue-slot.scala:59:28] wire next_uop_iw_p1_bypass_hint; // @[issue-slot.scala:59:28] wire next_uop_iw_p2_bypass_hint; // @[issue-slot.scala:59:28] wire next_uop_iw_p3_bypass_hint; // @[issue-slot.scala:59:28] wire [2:0] next_uop_dis_col_sel; // @[issue-slot.scala:59:28] wire [15:0] next_uop_br_mask; // @[issue-slot.scala:59:28] wire [3:0] next_uop_br_tag; // @[issue-slot.scala:59:28] wire [3:0] next_uop_br_type; // @[issue-slot.scala:59:28] wire next_uop_is_sfb; // @[issue-slot.scala:59:28] wire next_uop_is_fence; // @[issue-slot.scala:59:28] wire next_uop_is_fencei; // @[issue-slot.scala:59:28] wire next_uop_is_sfence; // @[issue-slot.scala:59:28] wire next_uop_is_amo; // @[issue-slot.scala:59:28] wire next_uop_is_eret; // @[issue-slot.scala:59:28] wire next_uop_is_sys_pc2epc; // @[issue-slot.scala:59:28] wire next_uop_is_rocc; // @[issue-slot.scala:59:28] wire next_uop_is_mov; // @[issue-slot.scala:59:28] wire [4:0] next_uop_ftq_idx; // @[issue-slot.scala:59:28] wire next_uop_edge_inst; // @[issue-slot.scala:59:28] wire [5:0] next_uop_pc_lob; // @[issue-slot.scala:59:28] wire next_uop_taken; // @[issue-slot.scala:59:28] wire next_uop_imm_rename; // @[issue-slot.scala:59:28] wire [2:0] next_uop_imm_sel; // @[issue-slot.scala:59:28] wire [4:0] next_uop_pimm; // @[issue-slot.scala:59:28] wire [19:0] next_uop_imm_packed; // @[issue-slot.scala:59:28] wire [1:0] next_uop_op1_sel; // @[issue-slot.scala:59:28] wire [2:0] next_uop_op2_sel; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_ldst; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_wen; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_ren1; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_ren2; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_ren3; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_swap12; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_swap23; // @[issue-slot.scala:59:28] wire [1:0] next_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:59:28] wire [1:0] next_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_fromint; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_toint; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_fma; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_div; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_sqrt; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_wflags; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_vec; // @[issue-slot.scala:59:28] wire [6:0] next_uop_rob_idx; // @[issue-slot.scala:59:28] wire [4:0] next_uop_ldq_idx; // @[issue-slot.scala:59:28] wire [4:0] next_uop_stq_idx; // @[issue-slot.scala:59:28] wire [1:0] next_uop_rxq_idx; // @[issue-slot.scala:59:28] wire [6:0] next_uop_pdst; // @[issue-slot.scala:59:28] wire [6:0] next_uop_prs1; // @[issue-slot.scala:59:28] wire [6:0] next_uop_prs2; // @[issue-slot.scala:59:28] wire [6:0] next_uop_prs3; // @[issue-slot.scala:59:28] wire [4:0] next_uop_ppred; // @[issue-slot.scala:59:28] wire next_uop_prs1_busy; // @[issue-slot.scala:59:28] wire next_uop_prs2_busy; // @[issue-slot.scala:59:28] wire next_uop_prs3_busy; // @[issue-slot.scala:59:28] wire next_uop_ppred_busy; // @[issue-slot.scala:59:28] wire [6:0] next_uop_stale_pdst; // @[issue-slot.scala:59:28] wire next_uop_exception; // @[issue-slot.scala:59:28] wire [63:0] next_uop_exc_cause; // @[issue-slot.scala:59:28] wire [4:0] next_uop_mem_cmd; // @[issue-slot.scala:59:28] wire [1:0] next_uop_mem_size; // @[issue-slot.scala:59:28] wire next_uop_mem_signed; // @[issue-slot.scala:59:28] wire next_uop_uses_ldq; // @[issue-slot.scala:59:28] wire next_uop_uses_stq; // @[issue-slot.scala:59:28] wire next_uop_is_unique; // @[issue-slot.scala:59:28] wire next_uop_flush_on_commit; // @[issue-slot.scala:59:28] wire [2:0] next_uop_csr_cmd; // @[issue-slot.scala:59:28] wire next_uop_ldst_is_rs1; // @[issue-slot.scala:59:28] wire [5:0] next_uop_ldst; // @[issue-slot.scala:59:28] wire [5:0] next_uop_lrs1; // @[issue-slot.scala:59:28] wire [5:0] next_uop_lrs2; // @[issue-slot.scala:59:28] wire [5:0] next_uop_lrs3; // @[issue-slot.scala:59:28] wire [1:0] next_uop_dst_rtype; // @[issue-slot.scala:59:28] wire [1:0] next_uop_lrs1_rtype; // @[issue-slot.scala:59:28] wire [1:0] next_uop_lrs2_rtype; // @[issue-slot.scala:59:28] wire next_uop_frs3_en; // @[issue-slot.scala:59:28] wire next_uop_fcn_dw; // @[issue-slot.scala:59:28] wire [4:0] next_uop_fcn_op; // @[issue-slot.scala:59:28] wire next_uop_fp_val; // @[issue-slot.scala:59:28] wire [2:0] next_uop_fp_rm; // @[issue-slot.scala:59:28] wire [1:0] next_uop_fp_typ; // @[issue-slot.scala:59:28] wire next_uop_xcpt_pf_if; // @[issue-slot.scala:59:28] wire next_uop_xcpt_ae_if; // @[issue-slot.scala:59:28] wire next_uop_xcpt_ma_if; // @[issue-slot.scala:59:28] wire next_uop_bp_debug_if; // @[issue-slot.scala:59:28] wire next_uop_bp_xcpt_if; // @[issue-slot.scala:59:28] wire [2:0] next_uop_debug_fsrc; // @[issue-slot.scala:59:28] wire [2:0] next_uop_debug_tsrc; // @[issue-slot.scala:59:28] wire io_iss_uop_iq_type_0_0; // @[issue-slot.scala:49:7] wire io_iss_uop_iq_type_1_0; // @[issue-slot.scala:49:7] wire io_iss_uop_iq_type_2_0; // @[issue-slot.scala:49:7] wire io_iss_uop_iq_type_3_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_0_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_1_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_2_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_3_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_4_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_5_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_6_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_7_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_8_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_9_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_ldst_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_wen_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_ren1_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_ren2_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_ren3_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_swap12_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_swap23_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_fp_ctrl_typeTagIn_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_fp_ctrl_typeTagOut_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_fromint_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_toint_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_fastpipe_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_fma_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_div_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_sqrt_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_wflags_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_vec_0; // @[issue-slot.scala:49:7] wire [31:0] io_iss_uop_inst_0; // @[issue-slot.scala:49:7] wire [31:0] io_iss_uop_debug_inst_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_rvc_0; // @[issue-slot.scala:49:7] wire [39:0] io_iss_uop_debug_pc_0; // @[issue-slot.scala:49:7] wire io_iss_uop_iw_issued_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_iw_p1_speculative_child_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_iw_p2_speculative_child_0; // @[issue-slot.scala:49:7] wire io_iss_uop_iw_p1_bypass_hint_0; // @[issue-slot.scala:49:7] wire io_iss_uop_iw_p2_bypass_hint_0; // @[issue-slot.scala:49:7] wire io_iss_uop_iw_p3_bypass_hint_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_dis_col_sel_0; // @[issue-slot.scala:49:7] wire [15:0] io_iss_uop_br_mask_0; // @[issue-slot.scala:49:7] wire [3:0] io_iss_uop_br_tag_0; // @[issue-slot.scala:49:7] wire [3:0] io_iss_uop_br_type_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_sfb_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_fence_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_fencei_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_sfence_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_amo_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_eret_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_sys_pc2epc_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_rocc_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_mov_0; // @[issue-slot.scala:49:7] wire [4:0] io_iss_uop_ftq_idx_0; // @[issue-slot.scala:49:7] wire io_iss_uop_edge_inst_0; // @[issue-slot.scala:49:7] wire [5:0] io_iss_uop_pc_lob_0; // @[issue-slot.scala:49:7] wire io_iss_uop_taken_0; // @[issue-slot.scala:49:7] wire io_iss_uop_imm_rename_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_imm_sel_0; // @[issue-slot.scala:49:7] wire [4:0] io_iss_uop_pimm_0; // @[issue-slot.scala:49:7] wire [19:0] io_iss_uop_imm_packed_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_op1_sel_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_op2_sel_0; // @[issue-slot.scala:49:7] wire [6:0] io_iss_uop_rob_idx_0; // @[issue-slot.scala:49:7] wire [4:0] io_iss_uop_ldq_idx_0; // @[issue-slot.scala:49:7] wire [4:0] io_iss_uop_stq_idx_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_rxq_idx_0; // @[issue-slot.scala:49:7] wire [6:0] io_iss_uop_pdst_0; // @[issue-slot.scala:49:7] wire [6:0] io_iss_uop_prs1_0; // @[issue-slot.scala:49:7] wire [6:0] io_iss_uop_prs2_0; // @[issue-slot.scala:49:7] wire [6:0] io_iss_uop_prs3_0; // @[issue-slot.scala:49:7] wire [4:0] io_iss_uop_ppred_0; // @[issue-slot.scala:49:7] wire io_iss_uop_prs1_busy_0; // @[issue-slot.scala:49:7] wire io_iss_uop_prs2_busy_0; // @[issue-slot.scala:49:7] wire io_iss_uop_prs3_busy_0; // @[issue-slot.scala:49:7] wire io_iss_uop_ppred_busy_0; // @[issue-slot.scala:49:7] wire [6:0] io_iss_uop_stale_pdst_0; // @[issue-slot.scala:49:7] wire io_iss_uop_exception_0; // @[issue-slot.scala:49:7] wire [63:0] io_iss_uop_exc_cause_0; // @[issue-slot.scala:49:7] wire [4:0] io_iss_uop_mem_cmd_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_mem_size_0; // @[issue-slot.scala:49:7] wire io_iss_uop_mem_signed_0; // @[issue-slot.scala:49:7] wire io_iss_uop_uses_ldq_0; // @[issue-slot.scala:49:7] wire io_iss_uop_uses_stq_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_unique_0; // @[issue-slot.scala:49:7] wire io_iss_uop_flush_on_commit_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_csr_cmd_0; // @[issue-slot.scala:49:7] wire io_iss_uop_ldst_is_rs1_0; // @[issue-slot.scala:49:7] wire [5:0] io_iss_uop_ldst_0; // @[issue-slot.scala:49:7] wire [5:0] io_iss_uop_lrs1_0; // @[issue-slot.scala:49:7] wire [5:0] io_iss_uop_lrs2_0; // @[issue-slot.scala:49:7] wire [5:0] io_iss_uop_lrs3_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_dst_rtype_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_lrs1_rtype_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_lrs2_rtype_0; // @[issue-slot.scala:49:7] wire io_iss_uop_frs3_en_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fcn_dw_0; // @[issue-slot.scala:49:7] wire [4:0] io_iss_uop_fcn_op_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_val_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_fp_rm_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_fp_typ_0; // @[issue-slot.scala:49:7] wire io_iss_uop_xcpt_pf_if_0; // @[issue-slot.scala:49:7] wire io_iss_uop_xcpt_ae_if_0; // @[issue-slot.scala:49:7] wire io_iss_uop_xcpt_ma_if_0; // @[issue-slot.scala:49:7] wire io_iss_uop_bp_debug_if_0; // @[issue-slot.scala:49:7] wire io_iss_uop_bp_xcpt_if_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_debug_fsrc_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_debug_tsrc_0; // @[issue-slot.scala:49:7] wire io_out_uop_iq_type_0_0; // @[issue-slot.scala:49:7] wire io_out_uop_iq_type_1_0; // @[issue-slot.scala:49:7] wire io_out_uop_iq_type_2_0; // @[issue-slot.scala:49:7] wire io_out_uop_iq_type_3_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_0_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_1_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_2_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_3_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_4_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_5_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_6_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_7_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_8_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_9_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_ldst_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_wen_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_ren1_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_ren2_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_ren3_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_swap12_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_swap23_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_fp_ctrl_typeTagIn_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_fp_ctrl_typeTagOut_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_fromint_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_toint_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_fastpipe_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_fma_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_div_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_sqrt_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_wflags_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_vec_0; // @[issue-slot.scala:49:7] wire [31:0] io_out_uop_inst_0; // @[issue-slot.scala:49:7] wire [31:0] io_out_uop_debug_inst_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_rvc_0; // @[issue-slot.scala:49:7] wire [39:0] io_out_uop_debug_pc_0; // @[issue-slot.scala:49:7] wire io_out_uop_iw_issued_0; // @[issue-slot.scala:49:7] wire [2:0] io_out_uop_iw_p1_speculative_child_0; // @[issue-slot.scala:49:7] wire [2:0] io_out_uop_iw_p2_speculative_child_0; // @[issue-slot.scala:49:7] wire io_out_uop_iw_p1_bypass_hint_0; // @[issue-slot.scala:49:7] wire io_out_uop_iw_p2_bypass_hint_0; // @[issue-slot.scala:49:7] wire io_out_uop_iw_p3_bypass_hint_0; // @[issue-slot.scala:49:7] wire [2:0] io_out_uop_dis_col_sel_0; // @[issue-slot.scala:49:7] wire [15:0] io_out_uop_br_mask_0; // @[issue-slot.scala:49:7] wire [3:0] io_out_uop_br_tag_0; // @[issue-slot.scala:49:7] wire [3:0] io_out_uop_br_type_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_sfb_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_fence_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_fencei_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_sfence_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_amo_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_eret_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_sys_pc2epc_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_rocc_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_mov_0; // @[issue-slot.scala:49:7] wire [4:0] io_out_uop_ftq_idx_0; // @[issue-slot.scala:49:7] wire io_out_uop_edge_inst_0; // @[issue-slot.scala:49:7] wire [5:0] io_out_uop_pc_lob_0; // @[issue-slot.scala:49:7] wire io_out_uop_taken_0; // @[issue-slot.scala:49:7] wire io_out_uop_imm_rename_0; // @[issue-slot.scala:49:7] wire [2:0] io_out_uop_imm_sel_0; // @[issue-slot.scala:49:7] wire [4:0] io_out_uop_pimm_0; // @[issue-slot.scala:49:7] wire [19:0] io_out_uop_imm_packed_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_op1_sel_0; // @[issue-slot.scala:49:7] wire [2:0] io_out_uop_op2_sel_0; // @[issue-slot.scala:49:7] wire [6:0] io_out_uop_rob_idx_0; // @[issue-slot.scala:49:7] wire [4:0] io_out_uop_ldq_idx_0; // @[issue-slot.scala:49:7] wire [4:0] io_out_uop_stq_idx_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_rxq_idx_0; // @[issue-slot.scala:49:7] wire [6:0] io_out_uop_pdst_0; // @[issue-slot.scala:49:7] wire [6:0] io_out_uop_prs1_0; // @[issue-slot.scala:49:7] wire [6:0] io_out_uop_prs2_0; // @[issue-slot.scala:49:7] wire [6:0] io_out_uop_prs3_0; // @[issue-slot.scala:49:7] wire [4:0] io_out_uop_ppred_0; // @[issue-slot.scala:49:7] wire io_out_uop_prs1_busy_0; // @[issue-slot.scala:49:7] wire io_out_uop_prs2_busy_0; // @[issue-slot.scala:49:7] wire io_out_uop_prs3_busy_0; // @[issue-slot.scala:49:7] wire io_out_uop_ppred_busy_0; // @[issue-slot.scala:49:7] wire [6:0] io_out_uop_stale_pdst_0; // @[issue-slot.scala:49:7] wire io_out_uop_exception_0; // @[issue-slot.scala:49:7] wire [63:0] io_out_uop_exc_cause_0; // @[issue-slot.scala:49:7] wire [4:0] io_out_uop_mem_cmd_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_mem_size_0; // @[issue-slot.scala:49:7] wire io_out_uop_mem_signed_0; // @[issue-slot.scala:49:7] wire io_out_uop_uses_ldq_0; // @[issue-slot.scala:49:7] wire io_out_uop_uses_stq_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_unique_0; // @[issue-slot.scala:49:7] wire io_out_uop_flush_on_commit_0; // @[issue-slot.scala:49:7] wire [2:0] io_out_uop_csr_cmd_0; // @[issue-slot.scala:49:7] wire io_out_uop_ldst_is_rs1_0; // @[issue-slot.scala:49:7] wire [5:0] io_out_uop_ldst_0; // @[issue-slot.scala:49:7] wire [5:0] io_out_uop_lrs1_0; // @[issue-slot.scala:49:7] wire [5:0] io_out_uop_lrs2_0; // @[issue-slot.scala:49:7] wire [5:0] io_out_uop_lrs3_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_dst_rtype_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_lrs1_rtype_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_lrs2_rtype_0; // @[issue-slot.scala:49:7] wire io_out_uop_frs3_en_0; // @[issue-slot.scala:49:7] wire io_out_uop_fcn_dw_0; // @[issue-slot.scala:49:7] wire [4:0] io_out_uop_fcn_op_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_val_0; // @[issue-slot.scala:49:7] wire [2:0] io_out_uop_fp_rm_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_fp_typ_0; // @[issue-slot.scala:49:7] wire io_out_uop_xcpt_pf_if_0; // @[issue-slot.scala:49:7] wire io_out_uop_xcpt_ae_if_0; // @[issue-slot.scala:49:7] wire io_out_uop_xcpt_ma_if_0; // @[issue-slot.scala:49:7] wire io_out_uop_bp_debug_if_0; // @[issue-slot.scala:49:7] wire io_out_uop_bp_xcpt_if_0; // @[issue-slot.scala:49:7] wire [2:0] io_out_uop_debug_fsrc_0; // @[issue-slot.scala:49:7] wire [2:0] io_out_uop_debug_tsrc_0; // @[issue-slot.scala:49:7] wire io_valid_0; // @[issue-slot.scala:49:7] wire io_will_be_valid_0; // @[issue-slot.scala:49:7] wire io_request_0; // @[issue-slot.scala:49:7] reg slot_valid; // @[issue-slot.scala:55:27] assign io_valid_0 = slot_valid; // @[issue-slot.scala:49:7, :55:27] reg [31:0] slot_uop_inst; // @[issue-slot.scala:56:21] assign io_iss_uop_inst_0 = slot_uop_inst; // @[issue-slot.scala:49:7, :56:21] wire [31:0] next_uop_out_inst = slot_uop_inst; // @[util.scala:104:23] reg [31:0] slot_uop_debug_inst; // @[issue-slot.scala:56:21] assign io_iss_uop_debug_inst_0 = slot_uop_debug_inst; // @[issue-slot.scala:49:7, :56:21] wire [31:0] next_uop_out_debug_inst = slot_uop_debug_inst; // @[util.scala:104:23] reg slot_uop_is_rvc; // @[issue-slot.scala:56:21] assign io_iss_uop_is_rvc_0 = slot_uop_is_rvc; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_rvc = slot_uop_is_rvc; // @[util.scala:104:23] reg [39:0] slot_uop_debug_pc; // @[issue-slot.scala:56:21] assign io_iss_uop_debug_pc_0 = slot_uop_debug_pc; // @[issue-slot.scala:49:7, :56:21] wire [39:0] next_uop_out_debug_pc = slot_uop_debug_pc; // @[util.scala:104:23] reg slot_uop_iq_type_0; // @[issue-slot.scala:56:21] assign io_iss_uop_iq_type_0_0 = slot_uop_iq_type_0; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iq_type_0 = slot_uop_iq_type_0; // @[util.scala:104:23] reg slot_uop_iq_type_1; // @[issue-slot.scala:56:21] assign io_iss_uop_iq_type_1_0 = slot_uop_iq_type_1; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iq_type_1 = slot_uop_iq_type_1; // @[util.scala:104:23] reg slot_uop_iq_type_2; // @[issue-slot.scala:56:21] assign io_iss_uop_iq_type_2_0 = slot_uop_iq_type_2; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iq_type_2 = slot_uop_iq_type_2; // @[util.scala:104:23] reg slot_uop_iq_type_3; // @[issue-slot.scala:56:21] assign io_iss_uop_iq_type_3_0 = slot_uop_iq_type_3; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iq_type_3 = slot_uop_iq_type_3; // @[util.scala:104:23] reg slot_uop_fu_code_0; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_0_0 = slot_uop_fu_code_0; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_0 = slot_uop_fu_code_0; // @[util.scala:104:23] reg slot_uop_fu_code_1; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_1_0 = slot_uop_fu_code_1; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_1 = slot_uop_fu_code_1; // @[util.scala:104:23] reg slot_uop_fu_code_2; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_2_0 = slot_uop_fu_code_2; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_2 = slot_uop_fu_code_2; // @[util.scala:104:23] reg slot_uop_fu_code_3; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_3_0 = slot_uop_fu_code_3; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_3 = slot_uop_fu_code_3; // @[util.scala:104:23] reg slot_uop_fu_code_4; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_4_0 = slot_uop_fu_code_4; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_4 = slot_uop_fu_code_4; // @[util.scala:104:23] reg slot_uop_fu_code_5; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_5_0 = slot_uop_fu_code_5; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_5 = slot_uop_fu_code_5; // @[util.scala:104:23] reg slot_uop_fu_code_6; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_6_0 = slot_uop_fu_code_6; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_6 = slot_uop_fu_code_6; // @[util.scala:104:23] reg slot_uop_fu_code_7; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_7_0 = slot_uop_fu_code_7; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_7 = slot_uop_fu_code_7; // @[util.scala:104:23] reg slot_uop_fu_code_8; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_8_0 = slot_uop_fu_code_8; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_8 = slot_uop_fu_code_8; // @[util.scala:104:23] reg slot_uop_fu_code_9; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_9_0 = slot_uop_fu_code_9; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_9 = slot_uop_fu_code_9; // @[util.scala:104:23] reg slot_uop_iw_issued; // @[issue-slot.scala:56:21] assign io_iss_uop_iw_issued_0 = slot_uop_iw_issued; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iw_issued = slot_uop_iw_issued; // @[util.scala:104:23] reg [2:0] slot_uop_iw_p1_speculative_child; // @[issue-slot.scala:56:21] assign io_iss_uop_iw_p1_speculative_child_0 = slot_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7, :56:21] wire [2:0] next_uop_out_iw_p1_speculative_child = slot_uop_iw_p1_speculative_child; // @[util.scala:104:23] reg [2:0] slot_uop_iw_p2_speculative_child; // @[issue-slot.scala:56:21] assign io_iss_uop_iw_p2_speculative_child_0 = slot_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7, :56:21] wire [2:0] next_uop_out_iw_p2_speculative_child = slot_uop_iw_p2_speculative_child; // @[util.scala:104:23] reg slot_uop_iw_p1_bypass_hint; // @[issue-slot.scala:56:21] assign io_iss_uop_iw_p1_bypass_hint_0 = slot_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iw_p1_bypass_hint = slot_uop_iw_p1_bypass_hint; // @[util.scala:104:23] reg slot_uop_iw_p2_bypass_hint; // @[issue-slot.scala:56:21] assign io_iss_uop_iw_p2_bypass_hint_0 = slot_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iw_p2_bypass_hint = slot_uop_iw_p2_bypass_hint; // @[util.scala:104:23] reg slot_uop_iw_p3_bypass_hint; // @[issue-slot.scala:56:21] assign io_iss_uop_iw_p3_bypass_hint_0 = slot_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iw_p3_bypass_hint = slot_uop_iw_p3_bypass_hint; // @[util.scala:104:23] reg [2:0] slot_uop_dis_col_sel; // @[issue-slot.scala:56:21] assign io_iss_uop_dis_col_sel_0 = slot_uop_dis_col_sel; // @[issue-slot.scala:49:7, :56:21] wire [2:0] next_uop_out_dis_col_sel = slot_uop_dis_col_sel; // @[util.scala:104:23] reg [15:0] slot_uop_br_mask; // @[issue-slot.scala:56:21] assign io_iss_uop_br_mask_0 = slot_uop_br_mask; // @[issue-slot.scala:49:7, :56:21] reg [3:0] slot_uop_br_tag; // @[issue-slot.scala:56:21] assign io_iss_uop_br_tag_0 = slot_uop_br_tag; // @[issue-slot.scala:49:7, :56:21] wire [3:0] next_uop_out_br_tag = slot_uop_br_tag; // @[util.scala:104:23] reg [3:0] slot_uop_br_type; // @[issue-slot.scala:56:21] assign io_iss_uop_br_type_0 = slot_uop_br_type; // @[issue-slot.scala:49:7, :56:21] wire [3:0] next_uop_out_br_type = slot_uop_br_type; // @[util.scala:104:23] reg slot_uop_is_sfb; // @[issue-slot.scala:56:21] assign io_iss_uop_is_sfb_0 = slot_uop_is_sfb; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_sfb = slot_uop_is_sfb; // @[util.scala:104:23] reg slot_uop_is_fence; // @[issue-slot.scala:56:21] assign io_iss_uop_is_fence_0 = slot_uop_is_fence; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_fence = slot_uop_is_fence; // @[util.scala:104:23] reg slot_uop_is_fencei; // @[issue-slot.scala:56:21] assign io_iss_uop_is_fencei_0 = slot_uop_is_fencei; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_fencei = slot_uop_is_fencei; // @[util.scala:104:23] reg slot_uop_is_sfence; // @[issue-slot.scala:56:21] assign io_iss_uop_is_sfence_0 = slot_uop_is_sfence; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_sfence = slot_uop_is_sfence; // @[util.scala:104:23] reg slot_uop_is_amo; // @[issue-slot.scala:56:21] assign io_iss_uop_is_amo_0 = slot_uop_is_amo; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_amo = slot_uop_is_amo; // @[util.scala:104:23] reg slot_uop_is_eret; // @[issue-slot.scala:56:21] assign io_iss_uop_is_eret_0 = slot_uop_is_eret; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_eret = slot_uop_is_eret; // @[util.scala:104:23] reg slot_uop_is_sys_pc2epc; // @[issue-slot.scala:56:21] assign io_iss_uop_is_sys_pc2epc_0 = slot_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_sys_pc2epc = slot_uop_is_sys_pc2epc; // @[util.scala:104:23] reg slot_uop_is_rocc; // @[issue-slot.scala:56:21] assign io_iss_uop_is_rocc_0 = slot_uop_is_rocc; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_rocc = slot_uop_is_rocc; // @[util.scala:104:23] reg slot_uop_is_mov; // @[issue-slot.scala:56:21] assign io_iss_uop_is_mov_0 = slot_uop_is_mov; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_mov = slot_uop_is_mov; // @[util.scala:104:23] reg [4:0] slot_uop_ftq_idx; // @[issue-slot.scala:56:21] assign io_iss_uop_ftq_idx_0 = slot_uop_ftq_idx; // @[issue-slot.scala:49:7, :56:21] wire [4:0] next_uop_out_ftq_idx = slot_uop_ftq_idx; // @[util.scala:104:23] reg slot_uop_edge_inst; // @[issue-slot.scala:56:21] assign io_iss_uop_edge_inst_0 = slot_uop_edge_inst; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_edge_inst = slot_uop_edge_inst; // @[util.scala:104:23] reg [5:0] slot_uop_pc_lob; // @[issue-slot.scala:56:21] assign io_iss_uop_pc_lob_0 = slot_uop_pc_lob; // @[issue-slot.scala:49:7, :56:21] wire [5:0] next_uop_out_pc_lob = slot_uop_pc_lob; // @[util.scala:104:23] reg slot_uop_taken; // @[issue-slot.scala:56:21] assign io_iss_uop_taken_0 = slot_uop_taken; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_taken = slot_uop_taken; // @[util.scala:104:23] reg slot_uop_imm_rename; // @[issue-slot.scala:56:21] assign io_iss_uop_imm_rename_0 = slot_uop_imm_rename; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_imm_rename = slot_uop_imm_rename; // @[util.scala:104:23] reg [2:0] slot_uop_imm_sel; // @[issue-slot.scala:56:21] assign io_iss_uop_imm_sel_0 = slot_uop_imm_sel; // @[issue-slot.scala:49:7, :56:21] wire [2:0] next_uop_out_imm_sel = slot_uop_imm_sel; // @[util.scala:104:23] reg [4:0] slot_uop_pimm; // @[issue-slot.scala:56:21] assign io_iss_uop_pimm_0 = slot_uop_pimm; // @[issue-slot.scala:49:7, :56:21] wire [4:0] next_uop_out_pimm = slot_uop_pimm; // @[util.scala:104:23] reg [19:0] slot_uop_imm_packed; // @[issue-slot.scala:56:21] assign io_iss_uop_imm_packed_0 = slot_uop_imm_packed; // @[issue-slot.scala:49:7, :56:21] wire [19:0] next_uop_out_imm_packed = slot_uop_imm_packed; // @[util.scala:104:23] reg [1:0] slot_uop_op1_sel; // @[issue-slot.scala:56:21] assign io_iss_uop_op1_sel_0 = slot_uop_op1_sel; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_op1_sel = slot_uop_op1_sel; // @[util.scala:104:23] reg [2:0] slot_uop_op2_sel; // @[issue-slot.scala:56:21] assign io_iss_uop_op2_sel_0 = slot_uop_op2_sel; // @[issue-slot.scala:49:7, :56:21] wire [2:0] next_uop_out_op2_sel = slot_uop_op2_sel; // @[util.scala:104:23] reg slot_uop_fp_ctrl_ldst; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_ldst_0 = slot_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_ldst = slot_uop_fp_ctrl_ldst; // @[util.scala:104:23] reg slot_uop_fp_ctrl_wen; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_wen_0 = slot_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_wen = slot_uop_fp_ctrl_wen; // @[util.scala:104:23] reg slot_uop_fp_ctrl_ren1; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_ren1_0 = slot_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_ren1 = slot_uop_fp_ctrl_ren1; // @[util.scala:104:23] reg slot_uop_fp_ctrl_ren2; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_ren2_0 = slot_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_ren2 = slot_uop_fp_ctrl_ren2; // @[util.scala:104:23] reg slot_uop_fp_ctrl_ren3; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_ren3_0 = slot_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_ren3 = slot_uop_fp_ctrl_ren3; // @[util.scala:104:23] reg slot_uop_fp_ctrl_swap12; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_swap12_0 = slot_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_swap12 = slot_uop_fp_ctrl_swap12; // @[util.scala:104:23] reg slot_uop_fp_ctrl_swap23; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_swap23_0 = slot_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_swap23 = slot_uop_fp_ctrl_swap23; // @[util.scala:104:23] reg [1:0] slot_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_typeTagIn_0 = slot_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_fp_ctrl_typeTagIn = slot_uop_fp_ctrl_typeTagIn; // @[util.scala:104:23] reg [1:0] slot_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_typeTagOut_0 = slot_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_fp_ctrl_typeTagOut = slot_uop_fp_ctrl_typeTagOut; // @[util.scala:104:23] reg slot_uop_fp_ctrl_fromint; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_fromint_0 = slot_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_fromint = slot_uop_fp_ctrl_fromint; // @[util.scala:104:23] reg slot_uop_fp_ctrl_toint; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_toint_0 = slot_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_toint = slot_uop_fp_ctrl_toint; // @[util.scala:104:23] reg slot_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_fastpipe_0 = slot_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_fastpipe = slot_uop_fp_ctrl_fastpipe; // @[util.scala:104:23] reg slot_uop_fp_ctrl_fma; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_fma_0 = slot_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_fma = slot_uop_fp_ctrl_fma; // @[util.scala:104:23] reg slot_uop_fp_ctrl_div; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_div_0 = slot_uop_fp_ctrl_div; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_div = slot_uop_fp_ctrl_div; // @[util.scala:104:23] reg slot_uop_fp_ctrl_sqrt; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_sqrt_0 = slot_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_sqrt = slot_uop_fp_ctrl_sqrt; // @[util.scala:104:23] reg slot_uop_fp_ctrl_wflags; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_wflags_0 = slot_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_wflags = slot_uop_fp_ctrl_wflags; // @[util.scala:104:23] reg slot_uop_fp_ctrl_vec; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_vec_0 = slot_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_vec = slot_uop_fp_ctrl_vec; // @[util.scala:104:23] reg [6:0] slot_uop_rob_idx; // @[issue-slot.scala:56:21] assign io_iss_uop_rob_idx_0 = slot_uop_rob_idx; // @[issue-slot.scala:49:7, :56:21] wire [6:0] next_uop_out_rob_idx = slot_uop_rob_idx; // @[util.scala:104:23] reg [4:0] slot_uop_ldq_idx; // @[issue-slot.scala:56:21] assign io_iss_uop_ldq_idx_0 = slot_uop_ldq_idx; // @[issue-slot.scala:49:7, :56:21] wire [4:0] next_uop_out_ldq_idx = slot_uop_ldq_idx; // @[util.scala:104:23] reg [4:0] slot_uop_stq_idx; // @[issue-slot.scala:56:21] assign io_iss_uop_stq_idx_0 = slot_uop_stq_idx; // @[issue-slot.scala:49:7, :56:21] wire [4:0] next_uop_out_stq_idx = slot_uop_stq_idx; // @[util.scala:104:23] reg [1:0] slot_uop_rxq_idx; // @[issue-slot.scala:56:21] assign io_iss_uop_rxq_idx_0 = slot_uop_rxq_idx; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_rxq_idx = slot_uop_rxq_idx; // @[util.scala:104:23] reg [6:0] slot_uop_pdst; // @[issue-slot.scala:56:21] assign io_iss_uop_pdst_0 = slot_uop_pdst; // @[issue-slot.scala:49:7, :56:21] wire [6:0] next_uop_out_pdst = slot_uop_pdst; // @[util.scala:104:23] reg [6:0] slot_uop_prs1; // @[issue-slot.scala:56:21] assign io_iss_uop_prs1_0 = slot_uop_prs1; // @[issue-slot.scala:49:7, :56:21] wire [6:0] next_uop_out_prs1 = slot_uop_prs1; // @[util.scala:104:23] reg [6:0] slot_uop_prs2; // @[issue-slot.scala:56:21] assign io_iss_uop_prs2_0 = slot_uop_prs2; // @[issue-slot.scala:49:7, :56:21] wire [6:0] next_uop_out_prs2 = slot_uop_prs2; // @[util.scala:104:23] reg [6:0] slot_uop_prs3; // @[issue-slot.scala:56:21] assign io_iss_uop_prs3_0 = slot_uop_prs3; // @[issue-slot.scala:49:7, :56:21] wire [6:0] next_uop_out_prs3 = slot_uop_prs3; // @[util.scala:104:23] reg [4:0] slot_uop_ppred; // @[issue-slot.scala:56:21] assign io_iss_uop_ppred_0 = slot_uop_ppred; // @[issue-slot.scala:49:7, :56:21] wire [4:0] next_uop_out_ppred = slot_uop_ppred; // @[util.scala:104:23] reg slot_uop_prs1_busy; // @[issue-slot.scala:56:21] assign io_iss_uop_prs1_busy_0 = slot_uop_prs1_busy; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_prs1_busy = slot_uop_prs1_busy; // @[util.scala:104:23] reg slot_uop_prs2_busy; // @[issue-slot.scala:56:21] assign io_iss_uop_prs2_busy_0 = slot_uop_prs2_busy; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_prs2_busy = slot_uop_prs2_busy; // @[util.scala:104:23] reg slot_uop_prs3_busy; // @[issue-slot.scala:56:21] assign io_iss_uop_prs3_busy_0 = slot_uop_prs3_busy; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_prs3_busy = slot_uop_prs3_busy; // @[util.scala:104:23] reg slot_uop_ppred_busy; // @[issue-slot.scala:56:21] assign io_iss_uop_ppred_busy_0 = slot_uop_ppred_busy; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_ppred_busy = slot_uop_ppred_busy; // @[util.scala:104:23] wire _iss_ready_T_3 = slot_uop_ppred_busy; // @[issue-slot.scala:56:21, :136:88] wire _agen_ready_T_2 = slot_uop_ppred_busy; // @[issue-slot.scala:56:21, :137:95] wire _dgen_ready_T_2 = slot_uop_ppred_busy; // @[issue-slot.scala:56:21, :138:95] reg [6:0] slot_uop_stale_pdst; // @[issue-slot.scala:56:21] assign io_iss_uop_stale_pdst_0 = slot_uop_stale_pdst; // @[issue-slot.scala:49:7, :56:21] wire [6:0] next_uop_out_stale_pdst = slot_uop_stale_pdst; // @[util.scala:104:23] reg slot_uop_exception; // @[issue-slot.scala:56:21] assign io_iss_uop_exception_0 = slot_uop_exception; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_exception = slot_uop_exception; // @[util.scala:104:23] reg [63:0] slot_uop_exc_cause; // @[issue-slot.scala:56:21] assign io_iss_uop_exc_cause_0 = slot_uop_exc_cause; // @[issue-slot.scala:49:7, :56:21] wire [63:0] next_uop_out_exc_cause = slot_uop_exc_cause; // @[util.scala:104:23] reg [4:0] slot_uop_mem_cmd; // @[issue-slot.scala:56:21] assign io_iss_uop_mem_cmd_0 = slot_uop_mem_cmd; // @[issue-slot.scala:49:7, :56:21] wire [4:0] next_uop_out_mem_cmd = slot_uop_mem_cmd; // @[util.scala:104:23] reg [1:0] slot_uop_mem_size; // @[issue-slot.scala:56:21] assign io_iss_uop_mem_size_0 = slot_uop_mem_size; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_mem_size = slot_uop_mem_size; // @[util.scala:104:23] reg slot_uop_mem_signed; // @[issue-slot.scala:56:21] assign io_iss_uop_mem_signed_0 = slot_uop_mem_signed; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_mem_signed = slot_uop_mem_signed; // @[util.scala:104:23] reg slot_uop_uses_ldq; // @[issue-slot.scala:56:21] assign io_iss_uop_uses_ldq_0 = slot_uop_uses_ldq; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_uses_ldq = slot_uop_uses_ldq; // @[util.scala:104:23] reg slot_uop_uses_stq; // @[issue-slot.scala:56:21] assign io_iss_uop_uses_stq_0 = slot_uop_uses_stq; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_uses_stq = slot_uop_uses_stq; // @[util.scala:104:23] reg slot_uop_is_unique; // @[issue-slot.scala:56:21] assign io_iss_uop_is_unique_0 = slot_uop_is_unique; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_unique = slot_uop_is_unique; // @[util.scala:104:23] reg slot_uop_flush_on_commit; // @[issue-slot.scala:56:21] assign io_iss_uop_flush_on_commit_0 = slot_uop_flush_on_commit; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_flush_on_commit = slot_uop_flush_on_commit; // @[util.scala:104:23] reg [2:0] slot_uop_csr_cmd; // @[issue-slot.scala:56:21] assign io_iss_uop_csr_cmd_0 = slot_uop_csr_cmd; // @[issue-slot.scala:49:7, :56:21] wire [2:0] next_uop_out_csr_cmd = slot_uop_csr_cmd; // @[util.scala:104:23] reg slot_uop_ldst_is_rs1; // @[issue-slot.scala:56:21] assign io_iss_uop_ldst_is_rs1_0 = slot_uop_ldst_is_rs1; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_ldst_is_rs1 = slot_uop_ldst_is_rs1; // @[util.scala:104:23] reg [5:0] slot_uop_ldst; // @[issue-slot.scala:56:21] assign io_iss_uop_ldst_0 = slot_uop_ldst; // @[issue-slot.scala:49:7, :56:21] wire [5:0] next_uop_out_ldst = slot_uop_ldst; // @[util.scala:104:23] reg [5:0] slot_uop_lrs1; // @[issue-slot.scala:56:21] assign io_iss_uop_lrs1_0 = slot_uop_lrs1; // @[issue-slot.scala:49:7, :56:21] wire [5:0] next_uop_out_lrs1 = slot_uop_lrs1; // @[util.scala:104:23] reg [5:0] slot_uop_lrs2; // @[issue-slot.scala:56:21] assign io_iss_uop_lrs2_0 = slot_uop_lrs2; // @[issue-slot.scala:49:7, :56:21] wire [5:0] next_uop_out_lrs2 = slot_uop_lrs2; // @[util.scala:104:23] reg [5:0] slot_uop_lrs3; // @[issue-slot.scala:56:21] assign io_iss_uop_lrs3_0 = slot_uop_lrs3; // @[issue-slot.scala:49:7, :56:21] wire [5:0] next_uop_out_lrs3 = slot_uop_lrs3; // @[util.scala:104:23] reg [1:0] slot_uop_dst_rtype; // @[issue-slot.scala:56:21] assign io_iss_uop_dst_rtype_0 = slot_uop_dst_rtype; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_dst_rtype = slot_uop_dst_rtype; // @[util.scala:104:23] reg [1:0] slot_uop_lrs1_rtype; // @[issue-slot.scala:56:21] assign io_iss_uop_lrs1_rtype_0 = slot_uop_lrs1_rtype; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_lrs1_rtype = slot_uop_lrs1_rtype; // @[util.scala:104:23] reg [1:0] slot_uop_lrs2_rtype; // @[issue-slot.scala:56:21] assign io_iss_uop_lrs2_rtype_0 = slot_uop_lrs2_rtype; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_lrs2_rtype = slot_uop_lrs2_rtype; // @[util.scala:104:23] reg slot_uop_frs3_en; // @[issue-slot.scala:56:21] assign io_iss_uop_frs3_en_0 = slot_uop_frs3_en; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_frs3_en = slot_uop_frs3_en; // @[util.scala:104:23] reg slot_uop_fcn_dw; // @[issue-slot.scala:56:21] assign io_iss_uop_fcn_dw_0 = slot_uop_fcn_dw; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fcn_dw = slot_uop_fcn_dw; // @[util.scala:104:23] reg [4:0] slot_uop_fcn_op; // @[issue-slot.scala:56:21] assign io_iss_uop_fcn_op_0 = slot_uop_fcn_op; // @[issue-slot.scala:49:7, :56:21] wire [4:0] next_uop_out_fcn_op = slot_uop_fcn_op; // @[util.scala:104:23] reg slot_uop_fp_val; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_val_0 = slot_uop_fp_val; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_val = slot_uop_fp_val; // @[util.scala:104:23] reg [2:0] slot_uop_fp_rm; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_rm_0 = slot_uop_fp_rm; // @[issue-slot.scala:49:7, :56:21] wire [2:0] next_uop_out_fp_rm = slot_uop_fp_rm; // @[util.scala:104:23] reg [1:0] slot_uop_fp_typ; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_typ_0 = slot_uop_fp_typ; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_fp_typ = slot_uop_fp_typ; // @[util.scala:104:23] reg slot_uop_xcpt_pf_if; // @[issue-slot.scala:56:21] assign io_iss_uop_xcpt_pf_if_0 = slot_uop_xcpt_pf_if; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_xcpt_pf_if = slot_uop_xcpt_pf_if; // @[util.scala:104:23] reg slot_uop_xcpt_ae_if; // @[issue-slot.scala:56:21] assign io_iss_uop_xcpt_ae_if_0 = slot_uop_xcpt_ae_if; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_xcpt_ae_if = slot_uop_xcpt_ae_if; // @[util.scala:104:23] reg slot_uop_xcpt_ma_if; // @[issue-slot.scala:56:21] assign io_iss_uop_xcpt_ma_if_0 = slot_uop_xcpt_ma_if; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_xcpt_ma_if = slot_uop_xcpt_ma_if; // @[util.scala:104:23] reg slot_uop_bp_debug_if; // @[issue-slot.scala:56:21] assign io_iss_uop_bp_debug_if_0 = slot_uop_bp_debug_if; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_bp_debug_if = slot_uop_bp_debug_if; // @[util.scala:104:23] reg slot_uop_bp_xcpt_if; // @[issue-slot.scala:56:21] assign io_iss_uop_bp_xcpt_if_0 = slot_uop_bp_xcpt_if; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_bp_xcpt_if = slot_uop_bp_xcpt_if; // @[util.scala:104:23] reg [2:0] slot_uop_debug_fsrc; // @[issue-slot.scala:56:21] assign io_iss_uop_debug_fsrc_0 = slot_uop_debug_fsrc; // @[issue-slot.scala:49:7, :56:21] wire [2:0] next_uop_out_debug_fsrc = slot_uop_debug_fsrc; // @[util.scala:104:23] reg [2:0] slot_uop_debug_tsrc; // @[issue-slot.scala:56:21] assign io_iss_uop_debug_tsrc_0 = slot_uop_debug_tsrc; // @[issue-slot.scala:49:7, :56:21] wire [2:0] next_uop_out_debug_tsrc = slot_uop_debug_tsrc; // @[util.scala:104:23] wire next_valid; // @[issue-slot.scala:58:28] assign next_uop_inst = next_uop_out_inst; // @[util.scala:104:23] assign next_uop_debug_inst = next_uop_out_debug_inst; // @[util.scala:104:23] assign next_uop_is_rvc = next_uop_out_is_rvc; // @[util.scala:104:23] assign next_uop_debug_pc = next_uop_out_debug_pc; // @[util.scala:104:23] assign next_uop_iq_type_0 = next_uop_out_iq_type_0; // @[util.scala:104:23] assign next_uop_iq_type_1 = next_uop_out_iq_type_1; // @[util.scala:104:23] assign next_uop_iq_type_2 = next_uop_out_iq_type_2; // @[util.scala:104:23] assign next_uop_iq_type_3 = next_uop_out_iq_type_3; // @[util.scala:104:23] assign next_uop_fu_code_0 = next_uop_out_fu_code_0; // @[util.scala:104:23] assign next_uop_fu_code_1 = next_uop_out_fu_code_1; // @[util.scala:104:23] assign next_uop_fu_code_2 = next_uop_out_fu_code_2; // @[util.scala:104:23] assign next_uop_fu_code_3 = next_uop_out_fu_code_3; // @[util.scala:104:23] assign next_uop_fu_code_4 = next_uop_out_fu_code_4; // @[util.scala:104:23] assign next_uop_fu_code_5 = next_uop_out_fu_code_5; // @[util.scala:104:23] assign next_uop_fu_code_6 = next_uop_out_fu_code_6; // @[util.scala:104:23] assign next_uop_fu_code_7 = next_uop_out_fu_code_7; // @[util.scala:104:23] assign next_uop_fu_code_8 = next_uop_out_fu_code_8; // @[util.scala:104:23] assign next_uop_fu_code_9 = next_uop_out_fu_code_9; // @[util.scala:104:23] wire [15:0] _next_uop_out_br_mask_T_1; // @[util.scala:93:25] assign next_uop_dis_col_sel = next_uop_out_dis_col_sel; // @[util.scala:104:23] assign next_uop_br_mask = next_uop_out_br_mask; // @[util.scala:104:23] assign next_uop_br_tag = next_uop_out_br_tag; // @[util.scala:104:23] assign next_uop_br_type = next_uop_out_br_type; // @[util.scala:104:23] assign next_uop_is_sfb = next_uop_out_is_sfb; // @[util.scala:104:23] assign next_uop_is_fence = next_uop_out_is_fence; // @[util.scala:104:23] assign next_uop_is_fencei = next_uop_out_is_fencei; // @[util.scala:104:23] assign next_uop_is_sfence = next_uop_out_is_sfence; // @[util.scala:104:23] assign next_uop_is_amo = next_uop_out_is_amo; // @[util.scala:104:23] assign next_uop_is_eret = next_uop_out_is_eret; // @[util.scala:104:23] assign next_uop_is_sys_pc2epc = next_uop_out_is_sys_pc2epc; // @[util.scala:104:23] assign next_uop_is_rocc = next_uop_out_is_rocc; // @[util.scala:104:23] assign next_uop_is_mov = next_uop_out_is_mov; // @[util.scala:104:23] assign next_uop_ftq_idx = next_uop_out_ftq_idx; // @[util.scala:104:23] assign next_uop_edge_inst = next_uop_out_edge_inst; // @[util.scala:104:23] assign next_uop_pc_lob = next_uop_out_pc_lob; // @[util.scala:104:23] assign next_uop_taken = next_uop_out_taken; // @[util.scala:104:23] assign next_uop_imm_rename = next_uop_out_imm_rename; // @[util.scala:104:23] assign next_uop_imm_sel = next_uop_out_imm_sel; // @[util.scala:104:23] assign next_uop_pimm = next_uop_out_pimm; // @[util.scala:104:23] assign next_uop_imm_packed = next_uop_out_imm_packed; // @[util.scala:104:23] assign next_uop_op1_sel = next_uop_out_op1_sel; // @[util.scala:104:23] assign next_uop_op2_sel = next_uop_out_op2_sel; // @[util.scala:104:23] assign next_uop_fp_ctrl_ldst = next_uop_out_fp_ctrl_ldst; // @[util.scala:104:23] assign next_uop_fp_ctrl_wen = next_uop_out_fp_ctrl_wen; // @[util.scala:104:23] assign next_uop_fp_ctrl_ren1 = next_uop_out_fp_ctrl_ren1; // @[util.scala:104:23] assign next_uop_fp_ctrl_ren2 = next_uop_out_fp_ctrl_ren2; // @[util.scala:104:23] assign next_uop_fp_ctrl_ren3 = next_uop_out_fp_ctrl_ren3; // @[util.scala:104:23] assign next_uop_fp_ctrl_swap12 = next_uop_out_fp_ctrl_swap12; // @[util.scala:104:23] assign next_uop_fp_ctrl_swap23 = next_uop_out_fp_ctrl_swap23; // @[util.scala:104:23] assign next_uop_fp_ctrl_typeTagIn = next_uop_out_fp_ctrl_typeTagIn; // @[util.scala:104:23] assign next_uop_fp_ctrl_typeTagOut = next_uop_out_fp_ctrl_typeTagOut; // @[util.scala:104:23] assign next_uop_fp_ctrl_fromint = next_uop_out_fp_ctrl_fromint; // @[util.scala:104:23] assign next_uop_fp_ctrl_toint = next_uop_out_fp_ctrl_toint; // @[util.scala:104:23] assign next_uop_fp_ctrl_fastpipe = next_uop_out_fp_ctrl_fastpipe; // @[util.scala:104:23] assign next_uop_fp_ctrl_fma = next_uop_out_fp_ctrl_fma; // @[util.scala:104:23] assign next_uop_fp_ctrl_div = next_uop_out_fp_ctrl_div; // @[util.scala:104:23] assign next_uop_fp_ctrl_sqrt = next_uop_out_fp_ctrl_sqrt; // @[util.scala:104:23] assign next_uop_fp_ctrl_wflags = next_uop_out_fp_ctrl_wflags; // @[util.scala:104:23] assign next_uop_fp_ctrl_vec = next_uop_out_fp_ctrl_vec; // @[util.scala:104:23] assign next_uop_rob_idx = next_uop_out_rob_idx; // @[util.scala:104:23] assign next_uop_ldq_idx = next_uop_out_ldq_idx; // @[util.scala:104:23] assign next_uop_stq_idx = next_uop_out_stq_idx; // @[util.scala:104:23] assign next_uop_rxq_idx = next_uop_out_rxq_idx; // @[util.scala:104:23] assign next_uop_pdst = next_uop_out_pdst; // @[util.scala:104:23] assign next_uop_prs1 = next_uop_out_prs1; // @[util.scala:104:23] assign next_uop_prs2 = next_uop_out_prs2; // @[util.scala:104:23] assign next_uop_prs3 = next_uop_out_prs3; // @[util.scala:104:23] assign next_uop_ppred = next_uop_out_ppred; // @[util.scala:104:23] assign next_uop_stale_pdst = next_uop_out_stale_pdst; // @[util.scala:104:23] assign next_uop_exception = next_uop_out_exception; // @[util.scala:104:23] assign next_uop_exc_cause = next_uop_out_exc_cause; // @[util.scala:104:23] assign next_uop_mem_cmd = next_uop_out_mem_cmd; // @[util.scala:104:23] assign next_uop_mem_size = next_uop_out_mem_size; // @[util.scala:104:23] assign next_uop_mem_signed = next_uop_out_mem_signed; // @[util.scala:104:23] assign next_uop_uses_ldq = next_uop_out_uses_ldq; // @[util.scala:104:23] assign next_uop_uses_stq = next_uop_out_uses_stq; // @[util.scala:104:23] assign next_uop_is_unique = next_uop_out_is_unique; // @[util.scala:104:23] assign next_uop_flush_on_commit = next_uop_out_flush_on_commit; // @[util.scala:104:23] assign next_uop_csr_cmd = next_uop_out_csr_cmd; // @[util.scala:104:23] assign next_uop_ldst_is_rs1 = next_uop_out_ldst_is_rs1; // @[util.scala:104:23] assign next_uop_ldst = next_uop_out_ldst; // @[util.scala:104:23] assign next_uop_lrs1 = next_uop_out_lrs1; // @[util.scala:104:23] assign next_uop_lrs2 = next_uop_out_lrs2; // @[util.scala:104:23] assign next_uop_lrs3 = next_uop_out_lrs3; // @[util.scala:104:23] assign next_uop_dst_rtype = next_uop_out_dst_rtype; // @[util.scala:104:23] assign next_uop_lrs1_rtype = next_uop_out_lrs1_rtype; // @[util.scala:104:23] assign next_uop_lrs2_rtype = next_uop_out_lrs2_rtype; // @[util.scala:104:23] assign next_uop_frs3_en = next_uop_out_frs3_en; // @[util.scala:104:23] assign next_uop_fcn_dw = next_uop_out_fcn_dw; // @[util.scala:104:23] assign next_uop_fcn_op = next_uop_out_fcn_op; // @[util.scala:104:23] assign next_uop_fp_val = next_uop_out_fp_val; // @[util.scala:104:23] assign next_uop_fp_rm = next_uop_out_fp_rm; // @[util.scala:104:23] assign next_uop_fp_typ = next_uop_out_fp_typ; // @[util.scala:104:23] assign next_uop_xcpt_pf_if = next_uop_out_xcpt_pf_if; // @[util.scala:104:23] assign next_uop_xcpt_ae_if = next_uop_out_xcpt_ae_if; // @[util.scala:104:23] assign next_uop_xcpt_ma_if = next_uop_out_xcpt_ma_if; // @[util.scala:104:23] assign next_uop_bp_debug_if = next_uop_out_bp_debug_if; // @[util.scala:104:23] assign next_uop_bp_xcpt_if = next_uop_out_bp_xcpt_if; // @[util.scala:104:23] assign next_uop_debug_fsrc = next_uop_out_debug_fsrc; // @[util.scala:104:23] assign next_uop_debug_tsrc = next_uop_out_debug_tsrc; // @[util.scala:104:23] wire [15:0] _next_uop_out_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:93:27] assign _next_uop_out_br_mask_T_1 = slot_uop_br_mask & _next_uop_out_br_mask_T; // @[util.scala:93:{25,27}] assign next_uop_out_br_mask = _next_uop_out_br_mask_T_1; // @[util.scala:93:25, :104:23] assign io_out_uop_inst_0 = next_uop_inst; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_debug_inst_0 = next_uop_debug_inst; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_rvc_0 = next_uop_is_rvc; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_debug_pc_0 = next_uop_debug_pc; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iq_type_0_0 = next_uop_iq_type_0; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iq_type_1_0 = next_uop_iq_type_1; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iq_type_2_0 = next_uop_iq_type_2; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iq_type_3_0 = next_uop_iq_type_3; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_0_0 = next_uop_fu_code_0; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_1_0 = next_uop_fu_code_1; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_2_0 = next_uop_fu_code_2; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_3_0 = next_uop_fu_code_3; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_4_0 = next_uop_fu_code_4; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_5_0 = next_uop_fu_code_5; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_6_0 = next_uop_fu_code_6; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_7_0 = next_uop_fu_code_7; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_8_0 = next_uop_fu_code_8; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_9_0 = next_uop_fu_code_9; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iw_issued_0 = next_uop_iw_issued; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iw_p1_speculative_child_0 = next_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iw_p2_speculative_child_0 = next_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iw_p1_bypass_hint_0 = next_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iw_p2_bypass_hint_0 = next_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iw_p3_bypass_hint_0 = next_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_dis_col_sel_0 = next_uop_dis_col_sel; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_br_mask_0 = next_uop_br_mask; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_br_tag_0 = next_uop_br_tag; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_br_type_0 = next_uop_br_type; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_sfb_0 = next_uop_is_sfb; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_fence_0 = next_uop_is_fence; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_fencei_0 = next_uop_is_fencei; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_sfence_0 = next_uop_is_sfence; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_amo_0 = next_uop_is_amo; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_eret_0 = next_uop_is_eret; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_sys_pc2epc_0 = next_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_rocc_0 = next_uop_is_rocc; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_mov_0 = next_uop_is_mov; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_ftq_idx_0 = next_uop_ftq_idx; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_edge_inst_0 = next_uop_edge_inst; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_pc_lob_0 = next_uop_pc_lob; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_taken_0 = next_uop_taken; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_imm_rename_0 = next_uop_imm_rename; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_imm_sel_0 = next_uop_imm_sel; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_pimm_0 = next_uop_pimm; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_imm_packed_0 = next_uop_imm_packed; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_op1_sel_0 = next_uop_op1_sel; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_op2_sel_0 = next_uop_op2_sel; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_ldst_0 = next_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_wen_0 = next_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_ren1_0 = next_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_ren2_0 = next_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_ren3_0 = next_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_swap12_0 = next_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_swap23_0 = next_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_typeTagIn_0 = next_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_typeTagOut_0 = next_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_fromint_0 = next_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_toint_0 = next_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_fastpipe_0 = next_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_fma_0 = next_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_div_0 = next_uop_fp_ctrl_div; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_sqrt_0 = next_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_wflags_0 = next_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_vec_0 = next_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_rob_idx_0 = next_uop_rob_idx; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_ldq_idx_0 = next_uop_ldq_idx; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_stq_idx_0 = next_uop_stq_idx; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_rxq_idx_0 = next_uop_rxq_idx; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_pdst_0 = next_uop_pdst; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_prs1_0 = next_uop_prs1; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_prs2_0 = next_uop_prs2; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_prs3_0 = next_uop_prs3; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_ppred_0 = next_uop_ppred; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_prs1_busy_0 = next_uop_prs1_busy; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_prs2_busy_0 = next_uop_prs2_busy; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_prs3_busy_0 = next_uop_prs3_busy; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_ppred_busy_0 = next_uop_ppred_busy; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_stale_pdst_0 = next_uop_stale_pdst; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_exception_0 = next_uop_exception; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_exc_cause_0 = next_uop_exc_cause; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_mem_cmd_0 = next_uop_mem_cmd; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_mem_size_0 = next_uop_mem_size; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_mem_signed_0 = next_uop_mem_signed; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_uses_ldq_0 = next_uop_uses_ldq; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_uses_stq_0 = next_uop_uses_stq; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_unique_0 = next_uop_is_unique; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_flush_on_commit_0 = next_uop_flush_on_commit; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_csr_cmd_0 = next_uop_csr_cmd; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_ldst_is_rs1_0 = next_uop_ldst_is_rs1; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_ldst_0 = next_uop_ldst; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_lrs1_0 = next_uop_lrs1; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_lrs2_0 = next_uop_lrs2; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_lrs3_0 = next_uop_lrs3; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_dst_rtype_0 = next_uop_dst_rtype; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_lrs1_rtype_0 = next_uop_lrs1_rtype; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_lrs2_rtype_0 = next_uop_lrs2_rtype; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_frs3_en_0 = next_uop_frs3_en; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fcn_dw_0 = next_uop_fcn_dw; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fcn_op_0 = next_uop_fcn_op; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_val_0 = next_uop_fp_val; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_rm_0 = next_uop_fp_rm; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_typ_0 = next_uop_fp_typ; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_xcpt_pf_if_0 = next_uop_xcpt_pf_if; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_xcpt_ae_if_0 = next_uop_xcpt_ae_if; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_xcpt_ma_if_0 = next_uop_xcpt_ma_if; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_bp_debug_if_0 = next_uop_bp_debug_if; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_bp_xcpt_if_0 = next_uop_bp_xcpt_if; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_debug_fsrc_0 = next_uop_debug_fsrc; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_debug_tsrc_0 = next_uop_debug_tsrc; // @[issue-slot.scala:49:7, :59:28] wire [15:0] _killed_T = io_brupdate_b1_mispredict_mask_0 & slot_uop_br_mask; // @[util.scala:126:51] wire _killed_T_1 = \|_killed_T; // @[util.scala:126:{51,59}] wire killed = _killed_T_1 \| io_kill_0; // @[util.scala:61:61, :126:59] wire _io_will_be_valid_T = ~killed; // @[util.scala:61:61] assign _io_will_be_valid_T_1 = next_valid & _io_will_be_valid_T; // @[issue-slot.scala:58:28, :65:{34,37}] assign io_will_be_valid_0 = _io_will_be_valid_T_1; // @[issue-slot.scala:49:7, :65:34] wire _slot_valid_T = ~killed; // @[util.scala:61:61] wire _slot_valid_T_1 = next_valid & _slot_valid_T; // @[issue-slot.scala:58:28, :74:{30,33}]
Generate the Verilog code corresponding to the following Chisel files. File Transposer.scala: package gemmini import chisel3._ import chisel3.util._ import Util._ trait Transposer[T <: Data] extends Module { def dim: Int def dataType: T val io = IO(new Bundle { val inRow = Flipped(Decoupled(Vec(dim, dataType))) val outCol = Decoupled(Vec(dim, dataType)) }) } class PipelinedTransposer[T <: Data](val dim: Int, val dataType: T) extends Transposer[T] { require(isPow2(dim)) val regArray = Seq.fill(dim, dim)(Reg(dataType)) val regArrayT = regArray.transpose val sMoveUp :: sMoveLeft :: Nil = Enum(2) val state = RegInit(sMoveUp) val leftCounter = RegInit(0.U(log2Ceil(dim+1).W)) //(io.inRow.fire && state === sMoveLeft, dim+1) val upCounter = RegInit(0.U(log2Ceil(dim+1).W)) //Counter(io.inRow.fire && state === sMoveUp, dim+1) io.outCol.valid := 0.U io.inRow.ready := 0.U switch(state) { is(sMoveUp) { io.inRow.ready := upCounter <= dim.U io.outCol.valid := leftCounter > 0.U when(io.inRow.fire) { upCounter := upCounter + 1.U } when(upCounter === (dim-1).U) { state := sMoveLeft leftCounter := 0.U } when(io.outCol.fire) { leftCounter := leftCounter - 1.U } } is(sMoveLeft) { io.inRow.ready := leftCounter <= dim.U // TODO: this is naive io.outCol.valid := upCounter > 0.U when(leftCounter === (dim-1).U) { state := sMoveUp } when(io.inRow.fire) { leftCounter := leftCounter + 1.U upCounter := 0.U } when(io.outCol.fire) { upCounter := upCounter - 1.U } } } // Propagate input from bottom row to top row systolically in the move up phase // TODO: need to iterate over columns to connect Chisel values of type T // Should be able to operate directly on the Vec, but Seq and Vec don't mix (try Array?) for (colIdx <- 0 until dim) { regArray.foldRight(io.inRow.bits(colIdx)) { case (regRow, prevReg) => when (state === sMoveUp) { regRow(colIdx) := prevReg } regRow(colIdx) } } // Propagate input from right side to left side systolically in the move left phase for (rowIdx <- 0 until dim) { regArrayT.foldRight(io.inRow.bits(rowIdx)) { case (regCol, prevReg) => when (state === sMoveLeft) { regCol(rowIdx) := prevReg } regCol(rowIdx) } } // Pull from the left side or the top side based on the state for (idx <- 0 until dim) { when (state === sMoveUp) { io.outCol.bits(idx) := regArray(0)(idx) }.elsewhen(state === sMoveLeft) { io.outCol.bits(idx) := regArrayT(0)(idx) }.otherwise { io.outCol.bits(idx) := DontCare } } } class AlwaysOutTransposer[T <: Data](val dim: Int, val dataType: T) extends Transposer[T] { require(isPow2(dim)) val LEFT_DIR = 0.U(1.W) val UP_DIR = 1.U(1.W) class PE extends Module { val io = IO(new Bundle { val inR = Input(dataType) val inD = Input(dataType) val outL = Output(dataType) val outU = Output(dataType) val dir = Input(UInt(1.W)) val en = Input(Bool()) }) val reg = RegEnable(Mux(io.dir === LEFT_DIR, io.inR, io.inD), io.en) io.outU := reg io.outL := reg } val pes = Seq.fill(dim,dim)(Module(new PE)) val counter = RegInit(0.U((log2Ceil(dim) max 1).W)) // TODO replace this with a standard Chisel counter val dir = RegInit(LEFT_DIR) // Wire up horizontal signals for (row <- 0 until dim; col <- 0 until dim) { val right_in = if (col == dim-1) io.inRow.bits(row) else pes(row)(col+1).io.outL pes(row)(col).io.inR := right_in } // Wire up vertical signals for (row <- 0 until dim; col <- 0 until dim) { val down_in = if (row == dim-1) io.inRow.bits(col) else pes(row+1)(col).io.outU pes(row)(col).io.inD := down_in } // Wire up global signals pes.flatten.foreach(_.io.dir := dir) pes.flatten.foreach(_.io.en := io.inRow.fire) io.outCol.valid := true.B io.inRow.ready := true.B val left_out = VecInit(pes.transpose.head.map(_.io.outL)) val up_out = VecInit(pes.head.map(_.io.outU)) io.outCol.bits := Mux(dir === LEFT_DIR, left_out, up_out) when (io.inRow.fire) { counter := wrappingAdd(counter, 1.U, dim) } when (counter === (dim-1).U && io.inRow.fire) { dir := ~dir } } class NaiveTransposer[T <: Data](val dim: Int, val dataType: T) extends Transposer[T] { val regArray = Seq.fill(dim, dim)(Reg(dataType)) val regArrayT = regArray.transpose // state = 0 => filling regArray row-wise, state = 1 => draining regArray column-wise val state = RegInit(0.U(1.W)) val countInc = io.inRow.fire \|\| io.outCol.fire val (countValue, countWrap) = Counter(countInc, dim) io.inRow.ready := state === 0.U io.outCol.valid := state === 1.U for (i <- 0 until dim) { for (j <- 0 until dim) { when(countValue === i.U && io.inRow.fire) { regArray(i)(j) := io.inRow.bits(j) } } } for (i <- 0 until dim) { io.outCol.bits(i) := 0.U for (j <- 0 until dim) { when(countValue === j.U) { io.outCol.bits(i) := regArrayT(j)(i) } } } when (io.inRow.fire && countWrap) { state := 1.U } when (io.outCol.fire && countWrap) { state := 0.U } assert(!(state === 0.U) \|\| !io.outCol.fire) assert(!(state === 1.U) \|\| !io.inRow.fire) }	module PE_154( // @[Transposer.scala:100:9] input clock, // @[Transposer.scala:100:9] input reset, // @[Transposer.scala:100:9] input [7:0] io_inR, // @[Transposer.scala:101:16] input [7:0] io_inD, // @[Transposer.scala:101:16] output [7:0] io_outL, // @[Transposer.scala:101:16] output [7:0] io_outU, // @[Transposer.scala:101:16] input io_dir, // @[Transposer.scala:101:16] input io_en // @[Transposer.scala:101:16] ); wire [7:0] io_inR_0 = io_inR; // @[Transposer.scala:100:9] wire [7:0] io_inD_0 = io_inD; // @[Transposer.scala:100:9] wire io_dir_0 = io_dir; // @[Transposer.scala:100:9] wire io_en_0 = io_en; // @[Transposer.scala:100:9] wire [7:0] io_outL_0; // @[Transposer.scala:100:9] wire [7:0] io_outU_0; // @[Transposer.scala:100:9] wire _reg_T = ~io_dir_0; // @[Transposer.scala:100:9, :110:36] wire [7:0] _reg_T_1 = _reg_T ? io_inR_0 : io_inD_0; // @[Transposer.scala:100:9, :110:{28,36}] reg [7:0] reg_0; // @[Transposer.scala:110:24] assign io_outL_0 = reg_0; // @[Transposer.scala:100:9, :110:24] assign io_outU_0 = reg_0; // @[Transposer.scala:100:9, :110:24] always @(posedge clock) begin // @[Transposer.scala:100:9] if (io_en_0) // @[Transposer.scala:100:9] reg_0 <= _reg_T_1; // @[Transposer.scala:110:{24,28}] always @(posedge) assign io_outL = io_outL_0; // @[Transposer.scala:100:9] assign io_outU = io_outU_0; // @[Transposer.scala:100:9] endmodule
Generate the Verilog code corresponding to the following Chisel files. File Monitor.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceLine import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import freechips.rocketchip.diplomacy.EnableMonitors import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode} import freechips.rocketchip.util.PlusArg case class TLMonitorArgs(edge: TLEdge) abstract class TLMonitorBase(args: TLMonitorArgs) extends Module { val io = IO(new Bundle { val in = Input(new TLBundle(args.edge.bundle)) }) def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit legalize(io.in, args.edge, reset) } object TLMonitor { def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = { if (enable) { EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) } } else { node } } } class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args) { require (args.edge.params(TLMonitorStrictMode) \|\| (! args.edge.params(TestplanTestType).formal)) val cover_prop_class = PropertyClass.Default //Like assert but can flip to being an assumption for formal verification def monAssert(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir, cond, message, PropertyClass.Default) } def assume(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir.flip, cond, message, PropertyClass.Default) } def extra = { args.edge.sourceInfo match { case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)" case _ => "" } } def visible(address: UInt, source: UInt, edge: TLEdge) = edge.client.clients.map { c => !c.sourceId.contains(source) \|\| c.visibility.map(_.contains(address)).reduce(_ \|\| _) }.reduce(_ && _) def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = { //switch this flag to turn on diplomacy in error messages def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n" monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra) // Reuse these subexpressions to save some firrtl lines val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility") //The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B //TODO: check for acquireT? when (bundle.opcode === TLMessages.AcquireBlock) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra) } when (bundle.opcode === TLMessages.AcquirePerm) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra) monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra) monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra) monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra) } } def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = { monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra) monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility") // Reuse these subexpressions to save some firrtl lines val address_ok = edge.manager.containsSafe(edge.address(bundle)) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source when (bundle.opcode === TLMessages.Probe) { assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra) assume (address_ok, "'B' channel Probe carries unmanaged address" + extra) assume (legal_source, "'B' channel Probe carries source that is not first source" + extra) assume (is_aligned, "'B' channel Probe address not aligned to size" + extra) assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra) assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra) assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra) monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra) monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra) monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra) monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra) } } def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = { monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val address_ok = edge.manager.containsSafe(edge.address(bundle)) monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility") when (bundle.opcode === TLMessages.ProbeAck) { monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra) } when (bundle.opcode === TLMessages.ProbeAckData) { monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.Release) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra) monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra) } when (bundle.opcode === TLMessages.ReleaseData) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.AccessAck) { monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra) } when (bundle.opcode === TLMessages.HintAck) { monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra) } } def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = { assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val sink_ok = bundle.sink < edge.manager.endSinkId.U val deny_put_ok = edge.manager.mayDenyPut.B val deny_get_ok = edge.manager.mayDenyGet.B when (bundle.opcode === TLMessages.ReleaseAck) { assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra) assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra) assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra) } when (bundle.opcode === TLMessages.Grant) { assume (source_ok, "'D' channel Grant carries invalid source ID" + extra) assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra) assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel Grant is denied" + extra) } when (bundle.opcode === TLMessages.GrantData) { assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra) assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra) assume (!bundle.denied \|\| bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra) assume (deny_get_ok \|\| !bundle.denied, "'D' channel GrantData is denied" + extra) } when (bundle.opcode === TLMessages.AccessAck) { assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel AccessAck is denied" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra) assume (!bundle.denied \|\| bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra) assume (deny_get_ok \|\| !bundle.denied, "'D' channel AccessAckData is denied" + extra) } when (bundle.opcode === TLMessages.HintAck) { assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel HintAck is denied" + extra) } } def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = { val sink_ok = bundle.sink < edge.manager.endSinkId.U monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra) } def legalizeFormat(bundle: TLBundle, edge: TLEdge) = { when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) } when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) } when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) } when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) } } else { monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra) monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra) monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra) } } def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = { val a_first = edge.first(a.bits, a.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (a.valid && !a_first) { monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra) monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra) monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra) monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra) monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra) } when (a.fire && a_first) { opcode := a.bits.opcode param := a.bits.param size := a.bits.size source := a.bits.source address := a.bits.address } } def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = { val b_first = edge.first(b.bits, b.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (b.valid && !b_first) { monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra) monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra) monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra) monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra) monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra) } when (b.fire && b_first) { opcode := b.bits.opcode param := b.bits.param size := b.bits.size source := b.bits.source address := b.bits.address } } def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = { // Symbolic variable val sym_source = Wire(UInt(edge.client.endSourceId.W)) // TODO: Connect sym_source to a fixed value for simulation and to a // free wire in formal sym_source := 0.U // Type casting Int to UInt val maxSourceId = Wire(UInt(edge.client.endSourceId.W)) maxSourceId := edge.client.endSourceId.U // Delayed verison of sym_source val sym_source_d = Reg(UInt(edge.client.endSourceId.W)) sym_source_d := sym_source // These will be constraints for FV setup Property( MonitorDirection.Monitor, (sym_source === sym_source_d), "sym_source should remain stable", PropertyClass.Default) Property( MonitorDirection.Monitor, (sym_source <= maxSourceId), "sym_source should take legal value", PropertyClass.Default) val my_resp_pend = RegInit(false.B) val my_opcode = Reg(UInt()) val my_size = Reg(UInt()) val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire) val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire) val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source) val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source) val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat) val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend) when (my_set_resp_pend) { my_resp_pend := true.B } .elsewhen (my_clr_resp_pend) { my_resp_pend := false.B } when (my_a_first_beat) { my_opcode := bundle.a.bits.opcode my_size := bundle.a.bits.size } val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size) val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode) val my_resp_opcode_legal = Wire(Bool()) when ((my_resp_opcode === TLMessages.Get) \|\| (my_resp_opcode === TLMessages.ArithmeticData) \|\| (my_resp_opcode === TLMessages.LogicalData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData) } .elsewhen ((my_resp_opcode === TLMessages.PutFullData) \|\| (my_resp_opcode === TLMessages.PutPartialData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck) } .otherwise { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck) } monAssert (IfThen(my_resp_pend, !my_a_first_beat), "Request message should not be sent with a source ID, for which a response message" + "is already pending (not received until current cycle) for a prior request message" + "with the same source ID" + extra) assume (IfThen(my_clr_resp_pend, (my_set_resp_pend \|\| my_resp_pend)), "Response message should be accepted with a source ID only if a request message with the" + "same source ID has been accepted or is being accepted in the current cycle" + extra) assume (IfThen(my_d_first_beat, (my_a_first_beat \|\| my_resp_pend)), "Response message should be sent with a source ID only if a request message with the" + "same source ID has been accepted or is being sent in the current cycle" + extra) assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)), "If d_valid is 1, then d_size should be same as a_size of the corresponding request" + "message" + extra) assume (IfThen(my_d_first_beat, my_resp_opcode_legal), "If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" + "request message" + extra) } def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = { val c_first = edge.first(c.bits, c.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (c.valid && !c_first) { monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra) monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra) monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra) monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra) monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra) } when (c.fire && c_first) { opcode := c.bits.opcode param := c.bits.param size := c.bits.size source := c.bits.source address := c.bits.address } } def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = { val d_first = edge.first(d.bits, d.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val sink = Reg(UInt()) val denied = Reg(Bool()) when (d.valid && !d_first) { assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra) assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra) assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra) assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra) assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra) assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra) } when (d.fire && d_first) { opcode := d.bits.opcode param := d.bits.param size := d.bits.size source := d.bits.source sink := d.bits.sink denied := d.bits.denied } } def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = { legalizeMultibeatA(bundle.a, edge) legalizeMultibeatD(bundle.d, edge) if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { legalizeMultibeatB(bundle.b, edge) legalizeMultibeatC(bundle.c, edge) } } //This is left in for almond which doesn't adhere to the tilelink protocol @deprecated("Use legalizeADSource instead if possible","") def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.client.endSourceId.W)) val a_first = edge.first(bundle.a.bits, bundle.a.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val a_set = WireInit(0.U(edge.client.endSourceId.W)) when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) assume((a_set \| inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra) } if (edge.manager.minLatency > 0) { assume(a_set =/= d_clr \|\| !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight \| a_set) & ~d_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") assert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = { val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size) val log_a_size_bus_size = log2Ceil(a_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error inflight.suggestName("inflight") val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) inflight_opcodes.suggestName("inflight_opcodes") val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) inflight_sizes.suggestName("inflight_sizes") val a_first = edge.first(bundle.a.bits, bundle.a.fire) a_first.suggestName("a_first") val d_first = edge.first(bundle.d.bits, bundle.d.fire) d_first.suggestName("d_first") val a_set = WireInit(0.U(edge.client.endSourceId.W)) val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) a_set.suggestName("a_set") a_set_wo_ready.suggestName("a_set_wo_ready") val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) a_opcodes_set.suggestName("a_opcodes_set") val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) a_sizes_set.suggestName("a_sizes_set") val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W)) a_opcode_lookup.suggestName("a_opcode_lookup") a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W)) a_size_lookup.suggestName("a_size_lookup") a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant)) val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant)) val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W)) a_opcodes_set_interm.suggestName("a_opcodes_set_interm") val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W)) a_sizes_set_interm.suggestName("a_sizes_set_interm") when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) { a_set_wo_ready := UIntToOH(bundle.a.bits.source) } when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) \| 1.U a_sizes_set_interm := (bundle.a.bits.size << 1.U) \| 1.U a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U) a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U) monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) d_opcodes_clr.suggestName("d_opcodes_clr") val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) \|\| same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) \|\| (bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra) assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) \|\| (bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra) assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) { assume((!bundle.d.ready) \|\| bundle.a.ready, "ready check") } if (edge.manager.minLatency > 0) { assume(a_set_wo_ready =/= d_clr_wo_ready \|\| !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight \| a_set) & ~d_clr inflight_opcodes := (inflight_opcodes \| a_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes \| a_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = { val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size) val log_c_size_bus_size = log2Ceil(c_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) inflight.suggestName("inflight") inflight_opcodes.suggestName("inflight_opcodes") inflight_sizes.suggestName("inflight_sizes") val c_first = edge.first(bundle.c.bits, bundle.c.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) c_first.suggestName("c_first") d_first.suggestName("d_first") val c_set = WireInit(0.U(edge.client.endSourceId.W)) val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) c_set.suggestName("c_set") c_set_wo_ready.suggestName("c_set_wo_ready") c_opcodes_set.suggestName("c_opcodes_set") c_sizes_set.suggestName("c_sizes_set") val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W)) val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W)) c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U c_opcode_lookup.suggestName("c_opcode_lookup") c_size_lookup.suggestName("c_size_lookup") val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W)) val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W)) c_opcodes_set_interm.suggestName("c_opcodes_set_interm") c_sizes_set_interm.suggestName("c_sizes_set_interm") when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) { c_set_wo_ready := UIntToOH(bundle.c.bits.source) } when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) { c_set := UIntToOH(bundle.c.bits.source) c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) \| 1.U c_sizes_set_interm := (bundle.c.bits.size << 1.U) \| 1.U c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U) c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U) monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra) } val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck \|\| bundle.c.bits.opcode === TLMessages.ProbeAckData val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") d_opcodes_clr.suggestName("d_opcodes_clr") d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) \|\| same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) { assume((!bundle.d.ready) \|\| bundle.c.ready, "ready check") } if (edge.manager.minLatency > 0) { when (c_set_wo_ready.orR) { assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra) } } inflight := (inflight \| c_set) & ~d_clr inflight_opcodes := (inflight_opcodes \| c_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes \| c_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.c.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.manager.endSinkId.W)) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val e_first = true.B val d_set = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) { d_set := UIntToOH(bundle.d.bits.sink) assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra) } val e_clr = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) { e_clr := UIntToOH(bundle.e.bits.sink) monAssert((d_set \| inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra) } // edge.client.minLatency applies to BC, not DE inflight := (inflight \| d_set) & ~e_clr } def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = { val sourceBits = log2Ceil(edge.client.endSourceId) val tooBig = 14 // >16kB worth of flight information gets to be too much if (sourceBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked") } else { if (args.edge.params(TestplanTestType).simulation) { if (args.edge.params(TLMonitorStrictMode)) { legalizeADSource(bundle, edge) legalizeCDSource(bundle, edge) } else { legalizeADSourceOld(bundle, edge) } } if (args.edge.params(TestplanTestType).formal) { legalizeADSourceFormal(bundle, edge) } } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { // legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize... val sinkBits = log2Ceil(edge.manager.endSinkId) if (sinkBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked") } else { legalizeDESink(bundle, edge) } } } def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = { legalizeFormat (bundle, edge) legalizeMultibeat (bundle, edge) legalizeUnique (bundle, edge) } } File Misc.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import scala.math._ class ParameterizedBundle(implicit p: Parameters) extends Bundle trait Clocked extends Bundle { val clock = Clock() val reset = Bool() } object DecoupledHelper { def apply(rvs: Bool) = new DecoupledHelper(rvs) } class DecoupledHelper(val rvs: Seq[Bool]) { def fire(exclude: Bool, includes: Bool) = { require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!") (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _) } def fire() = { rvs.reduce(_ && _) } } object MuxT { def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2)) def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3)) def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4)) } /** Creates a cascade of n MuxTs to search for a key value. / object MuxTLookup { def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } } object ValidMux { def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]): ValidIO[T] = { apply(v1 +: v2.toSeq) } def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = { val out = Wire(Valid(valids.head.bits.cloneType)) out.valid := valids.map(_.valid).reduce(_ \|\| _) out.bits := MuxCase(valids.head.bits, valids.map(v => (v.valid -> v.bits))) out } } object Str { def apply(s: String): UInt = { var i = BigInt(0) require(s.forall(validChar _)) for (c <- s) i = (i << 8) \| c i.U((s.length8).W) } def apply(x: Char): UInt = { require(validChar(x)) x.U(8.W) } def apply(x: UInt): UInt = apply(x, 10) def apply(x: UInt, radix: Int): UInt = { val rad = radix.U val w = x.getWidth require(w > 0) var q = x var s = digit(q % rad) for (i <- 1 until ceil(log(2)/log(radix)w).toInt) { q = q / rad s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s) } s } def apply(x: SInt): UInt = apply(x, 10) def apply(x: SInt, radix: Int): UInt = { val neg = x < 0.S val abs = x.abs.asUInt if (radix != 10) { Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix)) } else { val rad = radix.U val w = abs.getWidth require(w > 0) var q = abs var s = digit(q % rad) var needSign = neg for (i <- 1 until ceil(log(2)/log(radix)w).toInt) { q = q / rad val placeSpace = q === 0.U val space = Mux(needSign, Str('-'), Str(' ')) needSign = needSign && !placeSpace s = Cat(Mux(placeSpace, space, digit(q % rad)), s) } Cat(Mux(needSign, Str('-'), Str(' ')), s) } } private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0) private def validChar(x: Char) = x == (x & 0xFF) } object Split { def apply(x: UInt, n0: Int) = { val w = x.getWidth (x.extract(w-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n2: Int, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } } object Random { def apply(mod: Int, random: UInt): UInt = { if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0) else PriorityEncoder(partition(apply(1 << log2Up(mod8), random), mod)) } def apply(mod: Int): UInt = apply(mod, randomizer) def oneHot(mod: Int, random: UInt): UInt = { if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0)) else PriorityEncoderOH(partition(apply(1 << log2Up(mod8), random), mod)).asUInt } def oneHot(mod: Int): UInt = oneHot(mod, randomizer) private def randomizer = LFSR(16) private def partition(value: UInt, slices: Int) = Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U) } object Majority { def apply(in: Set[Bool]): Bool = { val n = (in.size >> 1) + 1 val clauses = in.subsets(n).map(_.reduce(_ && _)) clauses.reduce(_ \|\| _) } def apply(in: Seq[Bool]): Bool = apply(in.toSet) def apply(in: UInt): Bool = apply(in.asBools.toSet) } object PopCountAtLeast { private def two(x: UInt): (Bool, Bool) = x.getWidth match { case 1 => (x.asBool, false.B) case n => val half = x.getWidth / 2 val (leftOne, leftTwo) = two(x(half - 1, 0)) val (rightOne, rightTwo) = two(x(x.getWidth - 1, half)) (leftOne \|\| rightOne, leftTwo \|\| rightTwo \|\| (leftOne && rightOne)) } def apply(x: UInt, n: Int): Bool = n match { case 0 => true.B case 1 => x.orR case 2 => two(x)._2 case 3 => PopCount(x) >= n.U } } // This gets used everywhere, so make the smallest circuit possible ... // Given an address and size, create a mask of beatBytes size // eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111 // groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01 object MaskGen { def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = { require (groupBy >= 1 && beatBytes >= groupBy) require (isPow2(beatBytes) && isPow2(groupBy)) val lgBytes = log2Ceil(beatBytes) val sizeOH = UIntToOH(lgSize \| 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) \| (groupBy2 - 1).U def helper(i: Int): Seq[(Bool, Bool)] = { if (i == 0) { Seq((lgSize >= lgBytes.asUInt, true.B)) } else { val sub = helper(i-1) val size = sizeOH(lgBytes - i) val bit = addr_lo(lgBytes - i) val nbit = !bit Seq.tabulate (1 << i) { j => val (sub_acc, sub_eq) = sub(j/2) val eq = sub_eq && (if (j % 2 == 1) bit else nbit) val acc = sub_acc \|\| (size && eq) (acc, eq) } } } if (groupBy == beatBytes) 1.U else Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse) } } File PlusArg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.experimental._ import chisel3.util.HasBlackBoxResource @deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05") case class PlusArgInfo(default: BigInt, docstring: String) /** Case class for PlusArg information * * @tparam A scala type of the PlusArg value * @param default optional default value * @param docstring text to include in the help * @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT) / private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String) /* Typeclass for converting a type to a doctype string * @tparam A some type / trait Doctypeable[A] { /* Return the doctype string for some option / def toDoctype(a: Option[A]): String } /* Object containing implementations of the Doctypeable typeclass / object Doctypes { /* Converts an Int => "INT" / implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" } /* Converts a BigInt => "INT" / implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" } /* Converts a String => "STRING" / implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" } } class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map( "FORMAT" -> StringParam(format), "DEFAULT" -> IntParam(default), "WIDTH" -> IntParam(width) )) with HasBlackBoxResource { val io = IO(new Bundle { val out = Output(UInt(width.W)) }) addResource("/vsrc/plusarg_reader.v") } / This wrapper class has no outputs, making it clear it is a simulation-only construct / class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module { val io = IO(new Bundle { val count = Input(UInt(width.W)) }) val max = Module(new plusarg_reader(format, default, docstring, width)).io.out when (max > 0.U) { assert (io.count < max, s"Timeout exceeded: $docstring") } } import Doctypes._ object PlusArg { /* PlusArg("foo") will return 42.U if the simulation is run with +foo=42 * Do not use this as an initial register value. The value is set in an * initial block and thus accessing it from another initial is racey. * Add a docstring to document the arg, which can be dumped in an elaboration * pass. / def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out } /* PlusArg.timeout(name, default, docstring)(count) will use chisel.assert * to kill the simulation when count exceeds the specified integer argument. * Default 0 will never assert. / def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count } } object PlusArgArtefacts { private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty / Add a new PlusArg / @deprecated( "Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05" ) def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring) /* Add a new PlusArg * * @tparam A scala type of the PlusArg value * @param name name for the PlusArg * @param default optional default value * @param docstring text to include in the help / def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit = artefacts = artefacts ++ Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default))) / From plus args, generate help text / private def serializeHelp_cHeader(tab: String = ""): String = artefacts .map{ case(arg, info) => s"""\|$tab+$arg=${info.doctype}\\n\\ \|$tab${" "20}${info.docstring}\\n\\ \|""".stripMargin ++ info.default.map{ case default => s"$tab${" "22}(default=${default})\\n\\\n"}.getOrElse("") }.toSeq.mkString("\\n\\\n") ++ "\"" / From plus args, generate a char array of their names / private def serializeArray_cHeader(tab: String = ""): String = { val prettyTab = tab + " " 44 // Length of 'static const ...' s"${tab}static const char * verilog_plusargs [] = {\\\n" ++ artefacts .map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" } .mkString("")++ s"${prettyTab}0};" } /* Generate C code to be included in emulator.cc that helps with * argument parsing based on available Verilog PlusArgs / def serialize_cHeader(): String = s"""\|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\ \|${serializeHelp_cHeader(" "7)} \|${serializeArray_cHeader()} \|""".stripMargin } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /* Like Vec.apply(idx), but tolerates indices of mismatched width / def extract(idx: UInt): T = x((idx \| 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx \| 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def \| (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a \|\| b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_\|\|_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /* Any Data subtype that has a Bool member named valid. / type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /* converts from camel case to to underscores, also removing all spaces / def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /* converts spaces or underscores to hyphens, also lowering case / def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y \| (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y \|\| y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 \| 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /* Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation / def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Bundles.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import freechips.rocketchip.util._ import scala.collection.immutable.ListMap import chisel3.util.Decoupled import chisel3.util.DecoupledIO import chisel3.reflect.DataMirror abstract class TLBundleBase(val params: TLBundleParameters) extends Bundle // common combos in lazy policy: // Put + Acquire // Release + AccessAck object TLMessages { // A B C D E def PutFullData = 0.U // . . => AccessAck def PutPartialData = 1.U // . . => AccessAck def ArithmeticData = 2.U // . . => AccessAckData def LogicalData = 3.U // . . => AccessAckData def Get = 4.U // . . => AccessAckData def Hint = 5.U // . . => HintAck def AcquireBlock = 6.U // . => Grant[Data] def AcquirePerm = 7.U // . => Grant[Data] def Probe = 6.U // . => ProbeAck[Data] def AccessAck = 0.U // . . def AccessAckData = 1.U // . . def HintAck = 2.U // . . def ProbeAck = 4.U // . def ProbeAckData = 5.U // . def Release = 6.U // . => ReleaseAck def ReleaseData = 7.U // . => ReleaseAck def Grant = 4.U // . => GrantAck def GrantData = 5.U // . => GrantAck def ReleaseAck = 6.U // . def GrantAck = 0.U // . def isA(x: UInt) = x <= AcquirePerm def isB(x: UInt) = x <= Probe def isC(x: UInt) = x <= ReleaseData def isD(x: UInt) = x <= ReleaseAck def adResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, Grant, Grant) def bcResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, ProbeAck, ProbeAck) def a = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("AcquireBlock",TLPermissions.PermMsgGrow), ("AcquirePerm",TLPermissions.PermMsgGrow)) def b = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("Probe",TLPermissions.PermMsgCap)) def c = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("ProbeAck",TLPermissions.PermMsgReport), ("ProbeAckData",TLPermissions.PermMsgReport), ("Release",TLPermissions.PermMsgReport), ("ReleaseData",TLPermissions.PermMsgReport)) def d = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("Grant",TLPermissions.PermMsgCap), ("GrantData",TLPermissions.PermMsgCap), ("ReleaseAck",TLPermissions.PermMsgReserved)) } /* * The three primary TileLink permissions are: * (T)runk: the agent is (or is on inwards path to) the global point of serialization. * (B)ranch: the agent is on an outwards path to * (N)one: * These permissions are permuted by transfer operations in various ways. * Operations can cap permissions, request for them to be grown or shrunk, * or for a report on their current status. / object TLPermissions { val aWidth = 2 val bdWidth = 2 val cWidth = 3 // Cap types (Grant = new permissions, Probe = permisions <= target) def toT = 0.U(bdWidth.W) def toB = 1.U(bdWidth.W) def toN = 2.U(bdWidth.W) def isCap(x: UInt) = x <= toN // Grow types (Acquire = permissions >= target) def NtoB = 0.U(aWidth.W) def NtoT = 1.U(aWidth.W) def BtoT = 2.U(aWidth.W) def isGrow(x: UInt) = x <= BtoT // Shrink types (ProbeAck, Release) def TtoB = 0.U(cWidth.W) def TtoN = 1.U(cWidth.W) def BtoN = 2.U(cWidth.W) def isShrink(x: UInt) = x <= BtoN // Report types (ProbeAck, Release) def TtoT = 3.U(cWidth.W) def BtoB = 4.U(cWidth.W) def NtoN = 5.U(cWidth.W) def isReport(x: UInt) = x <= NtoN def PermMsgGrow:Seq[String] = Seq("Grow NtoB", "Grow NtoT", "Grow BtoT") def PermMsgCap:Seq[String] = Seq("Cap toT", "Cap toB", "Cap toN") def PermMsgReport:Seq[String] = Seq("Shrink TtoB", "Shrink TtoN", "Shrink BtoN", "Report TotT", "Report BtoB", "Report NtoN") def PermMsgReserved:Seq[String] = Seq("Reserved") } object TLAtomics { val width = 3 // Arithmetic types def MIN = 0.U(width.W) def MAX = 1.U(width.W) def MINU = 2.U(width.W) def MAXU = 3.U(width.W) def ADD = 4.U(width.W) def isArithmetic(x: UInt) = x <= ADD // Logical types def XOR = 0.U(width.W) def OR = 1.U(width.W) def AND = 2.U(width.W) def SWAP = 3.U(width.W) def isLogical(x: UInt) = x <= SWAP def ArithMsg:Seq[String] = Seq("MIN", "MAX", "MINU", "MAXU", "ADD") def LogicMsg:Seq[String] = Seq("XOR", "OR", "AND", "SWAP") } object TLHints { val width = 1 def PREFETCH_READ = 0.U(width.W) def PREFETCH_WRITE = 1.U(width.W) def isHints(x: UInt) = x <= PREFETCH_WRITE def HintsMsg:Seq[String] = Seq("PrefetchRead", "PrefetchWrite") } sealed trait TLChannel extends TLBundleBase { val channelName: String } sealed trait TLDataChannel extends TLChannel sealed trait TLAddrChannel extends TLDataChannel final class TLBundleA(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleA_${params.shortName}" val channelName = "'A' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(List(TLAtomics.width, TLPermissions.aWidth, TLHints.width).max.W) // amo_opcode \|\| grow perms \|\| hint val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleB(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleB_${params.shortName}" val channelName = "'B' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val address = UInt(params.addressBits.W) // from // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleC(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleC_${params.shortName}" val channelName = "'C' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.cWidth.W) // shrink or report perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleD(params: TLBundleParameters) extends TLBundleBase(params) with TLDataChannel { override def typeName = s"TLBundleD_${params.shortName}" val channelName = "'D' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val sink = UInt(params.sinkBits.W) // from val denied = Bool() // implies corrupt iff Data val user = BundleMap(params.responseFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleE(params: TLBundleParameters) extends TLBundleBase(params) with TLChannel { override def typeName = s"TLBundleE_${params.shortName}" val channelName = "'E' channel" val sink = UInt(params.sinkBits.W) // to } class TLBundle(val params: TLBundleParameters) extends Record { // Emulate a Bundle with elements abcde or ad depending on params.hasBCE private val optA = Some (Decoupled(new TLBundleA(params))) private val optB = params.hasBCE.option(Flipped(Decoupled(new TLBundleB(params)))) private val optC = params.hasBCE.option(Decoupled(new TLBundleC(params))) private val optD = Some (Flipped(Decoupled(new TLBundleD(params)))) private val optE = params.hasBCE.option(Decoupled(new TLBundleE(params))) def a: DecoupledIO[TLBundleA] = optA.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleA(params))))) def b: DecoupledIO[TLBundleB] = optB.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleB(params))))) def c: DecoupledIO[TLBundleC] = optC.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleC(params))))) def d: DecoupledIO[TLBundleD] = optD.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleD(params))))) def e: DecoupledIO[TLBundleE] = optE.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleE(params))))) val elements = if (params.hasBCE) ListMap("e" -> e, "d" -> d, "c" -> c, "b" -> b, "a" -> a) else ListMap("d" -> d, "a" -> a) def tieoff(): Unit = { DataMirror.specifiedDirectionOf(a.ready) match { case SpecifiedDirection.Input => a.ready := false.B c.ready := false.B e.ready := false.B b.valid := false.B d.valid := false.B case SpecifiedDirection.Output => a.valid := false.B c.valid := false.B e.valid := false.B b.ready := false.B d.ready := false.B case _ => } } } object TLBundle { def apply(params: TLBundleParameters) = new TLBundle(params) } class TLAsyncBundleBase(val params: TLAsyncBundleParameters) extends Bundle class TLAsyncBundle(params: TLAsyncBundleParameters) extends TLAsyncBundleBase(params) { val a = new AsyncBundle(new TLBundleA(params.base), params.async) val b = Flipped(new AsyncBundle(new TLBundleB(params.base), params.async)) val c = new AsyncBundle(new TLBundleC(params.base), params.async) val d = Flipped(new AsyncBundle(new TLBundleD(params.base), params.async)) val e = new AsyncBundle(new TLBundleE(params.base), params.async) } class TLRationalBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = RationalIO(new TLBundleA(params)) val b = Flipped(RationalIO(new TLBundleB(params))) val c = RationalIO(new TLBundleC(params)) val d = Flipped(RationalIO(new TLBundleD(params))) val e = RationalIO(new TLBundleE(params)) } class TLCreditedBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = CreditedIO(new TLBundleA(params)) val b = Flipped(CreditedIO(new TLBundleB(params))) val c = CreditedIO(new TLBundleC(params)) val d = Flipped(CreditedIO(new TLBundleD(params))) val e = CreditedIO(new TLBundleE(params)) } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.diplomacy import chisel3._ import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor} import freechips.rocketchip.util.ShiftQueue /** Options for describing the attributes of memory regions / object RegionType { // Define the 'more relaxed than' ordering val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS) sealed trait T extends Ordered[T] { def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this) } case object CACHED extends T // an intermediate agent may have cached a copy of the region for you case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively } // A non-empty half-open range; [start, end) case class IdRange(start: Int, end: Int) extends Ordered[IdRange] { require (start >= 0, s"Ids cannot be negative, but got: $start.") require (start <= end, "Id ranges cannot be negative.") def compare(x: IdRange) = { val primary = (this.start - x.start).signum val secondary = (x.end - this.end).signum if (primary != 0) primary else secondary } def overlaps(x: IdRange) = start < x.end && x.start < end def contains(x: IdRange) = start <= x.start && x.end <= end def contains(x: Int) = start <= x && x < end def contains(x: UInt) = if (size == 0) { false.B } else if (size == 1) { // simple comparison x === start.U } else { // find index of largest different bit val largestDeltaBit = log2Floor(start ^ (end-1)) val smallestCommonBit = largestDeltaBit + 1 // may not exist in x val uncommonMask = (1 << smallestCommonBit) - 1 val uncommonBits = (x \| 0.U(smallestCommonBit.W))(largestDeltaBit, 0) // the prefix must match exactly (note: may shift ALL bits away) (x >> smallestCommonBit) === (start >> smallestCommonBit).U && // firrtl constant prop range analysis can eliminate these two: (start & uncommonMask).U <= uncommonBits && uncommonBits <= ((end-1) & uncommonMask).U } def shift(x: Int) = IdRange(start+x, end+x) def size = end - start def isEmpty = end == start def range = start until end } object IdRange { def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else { val ranges = s.sorted (ranges.tail zip ranges.init) find { case (a, b) => a overlaps b } } } // An potentially empty inclusive range of 2-powers [min, max] (in bytes) case class TransferSizes(min: Int, max: Int) { def this(x: Int) = this(x, x) require (min <= max, s"Min transfer $min > max transfer $max") require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)") require (max == 0 \|\| isPow2(max), s"TransferSizes must be a power of 2, got: $max") require (min == 0 \|\| isPow2(min), s"TransferSizes must be a power of 2, got: $min") require (max == 0 \|\| min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)") def none = min == 0 def contains(x: Int) = isPow2(x) && min <= x && x <= max def containsLg(x: Int) = contains(1 << x) def containsLg(x: UInt) = if (none) false.B else if (min == max) { log2Ceil(min).U === x } else { log2Ceil(min).U <= x && x <= log2Ceil(max).U } def contains(x: TransferSizes) = x.none \|\| (min <= x.min && x.max <= max) def intersect(x: TransferSizes) = if (x.max < min \|\| max < x.min) TransferSizes.none else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max)) // Not a union, because the result may contain sizes contained by neither term // NOT TO BE CONFUSED WITH COVERPOINTS def mincover(x: TransferSizes) = { if (none) { x } else if (x.none) { this } else { TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max)) } } override def toString() = "TransferSizes[%d, %d]".format(min, max) } object TransferSizes { def apply(x: Int) = new TransferSizes(x) val none = new TransferSizes(0) def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _) def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _) implicit def asBool(x: TransferSizes) = !x.none } // AddressSets specify the address space managed by the manager // Base is the base address, and mask are the bits consumed by the manager // e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff // e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ... case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet] { // Forbid misaligned base address (and empty sets) require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}") require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous // We do allow negative mask (=> ignore all high bits) def contains(x: BigInt) = ((x ^ base) & ~mask) == 0 def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S // turn x into an address contained in this set def legalize(x: UInt): UInt = base.U \| (mask.U & x) // overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1) def overlaps(x: AddressSet) = (~(mask \| x.mask) & (base ^ x.base)) == 0 // contains iff bitwise: x.mask => mask && contains(x.base) def contains(x: AddressSet) = ((x.mask \| (base ^ x.base)) & ~mask) == 0 // The number of bytes to which the manager must be aligned def alignment = ((mask + 1) & ~mask) // Is this a contiguous memory range def contiguous = alignment == mask+1 def finite = mask >= 0 def max = { require (finite, "Max cannot be calculated on infinite mask"); base \| mask } // Widen the match function to ignore all bits in imask def widen(imask: BigInt) = AddressSet(base & ~imask, mask \| imask) // Return an AddressSet that only contains the addresses both sets contain def intersect(x: AddressSet): Option[AddressSet] = { if (!overlaps(x)) { None } else { val r_mask = mask & x.mask val r_base = base \| x.base Some(AddressSet(r_base, r_mask)) } } def subtract(x: AddressSet): Seq[AddressSet] = { intersect(x) match { case None => Seq(this) case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit => val nmask = (mask & (bit-1)) \| remove.mask val nbase = (remove.base ^ bit) & ~nmask AddressSet(nbase, nmask) } } } // AddressSets have one natural Ordering (the containment order, if contiguous) def compare(x: AddressSet) = { val primary = (this.base - x.base).signum // smallest address first val secondary = (x.mask - this.mask).signum // largest mask first if (primary != 0) primary else secondary } // We always want to see things in hex override def toString() = { if (mask >= 0) { "AddressSet(0x%x, 0x%x)".format(base, mask) } else { "AddressSet(0x%x, ~0x%x)".format(base, ~mask) } } def toRanges = { require (finite, "Ranges cannot be calculated on infinite mask") val size = alignment val fragments = mask & ~(size-1) val bits = bitIndexes(fragments) (BigInt(0) until (BigInt(1) << bits.size)).map { i => val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) } AddressRange(off, size) } } } object AddressSet { val everything = AddressSet(0, -1) def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = { if (size == 0) tail.reverse else { val maxBaseAlignment = base & (-base) // 0 for infinite (LSB) val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size val step = if (maxBaseAlignment == 0 \|\| maxBaseAlignment > maxSizeAlignment) maxSizeAlignment else maxBaseAlignment misaligned(base+step, size-step, AddressSet(base, step-1) +: tail) } } def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = { // Pair terms up by ignoring 'bit' seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) => if (seq.size == 1) { seq.head // singleton -> unaffected } else { key.copy(mask = key.mask \| bit) // pair - widen mask by bit } }.toList } def unify(seq: Seq[AddressSet]): Seq[AddressSet] = { val bits = seq.map(_.base).foldLeft(BigInt(0))(_ \| _) AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted } def enumerateMask(mask: BigInt): Seq[BigInt] = { def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] = if (id == mask) (id +: tail).reverse else helper(((~mask \| id) + 1) & mask, id +: tail) helper(0, Nil) } def enumerateBits(mask: BigInt): Seq[BigInt] = { def helper(x: BigInt): Seq[BigInt] = { if (x == 0) { Nil } else { val bit = x & (-x) bit +: helper(x & ~bit) } } helper(mask) } } case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean) { require (depth >= 0, "Buffer depth must be >= 0") def isDefined = depth > 0 def latency = if (isDefined && !flow) 1 else 0 def apply[T <: Data](x: DecoupledIO[T]) = if (isDefined) Queue(x, depth, flow=flow, pipe=pipe) else x def irrevocable[T <: Data](x: ReadyValidIO[T]) = if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe) else x def sq[T <: Data](x: DecoupledIO[T]) = if (!isDefined) x else { val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe)) sq.io.enq <> x sq.io.deq } override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "") } object BufferParams { implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false) val default = BufferParams(2) val none = BufferParams(0) val flow = BufferParams(1, true, false) val pipe = BufferParams(1, false, true) } case class TriStateValue(value: Boolean, set: Boolean) { def update(orig: Boolean) = if (set) value else orig } object TriStateValue { implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true) def unset = TriStateValue(false, false) } trait DirectedBuffers[T] { def copyIn(x: BufferParams): T def copyOut(x: BufferParams): T def copyInOut(x: BufferParams): T } trait IdMapEntry { def name: String def from: IdRange def to: IdRange def isCache: Boolean def requestFifo: Boolean def maxTransactionsInFlight: Option[Int] def pretty(fmt: String) = if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5 fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } else { fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } } abstract class IdMap[T <: IdMapEntry] { protected val fmt: String val mapping: Seq[T] def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n") } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportPutFull \|\| manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB \|\| manager.anySupportGet \|\| manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportPutFull \|\| client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe \|\| client.anySupportGet \|\| client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet \|\| client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull \|\| client.anySupportPutPartial \|\| client.anySupportHint \|\| client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet \|\| manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull \|\| manager.anySupportPutPartial \|\| manager.anySupportHint \|\| manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) \|\| !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.ProbeAckData \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode \| small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U \|\| beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }	module TLMonitor_64( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [8:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [20:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [8:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [8:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [20:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [8:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_sink = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_denied = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire sink_ok = 1'h0; // @[Monitor.scala:309:31] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] c_first_beats1_decode = 3'h0; // @[Edges.scala:220:59] wire [2:0] c_first_beats1 = 3'h0; // @[Edges.scala:221:14] wire [2:0] _c_first_count_T = 3'h0; // @[Edges.scala:234:27] wire [2:0] c_first_count = 3'h0; // @[Edges.scala:234:25] wire [2:0] _c_first_counter_T = 3'h0; // @[Edges.scala:236:21] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_size = 3'h0; // @[Bundles.scala:265:61] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_5 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_11 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_15 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_17 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_21 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_23 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_27 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_29 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_33 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_35 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_53 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_55 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_59 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_61 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_65 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_67 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_71 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_73 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_77 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_79 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_83 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_85 = 1'h1; // @[Parameters.scala:57:20] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire [2:0] c_first_counter1 = 3'h7; // @[Edges.scala:230:28] wire [3:0] _c_first_counter1_T = 4'hF; // @[Edges.scala:230:28] wire [1:0] io_in_d_bits_param = 2'h0; // @[Monitor.scala:36:7] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [20:0] _c_first_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_first_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_first_WIRE_2_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_first_WIRE_3_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_set_wo_ready_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_set_wo_ready_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_set_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_set_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_opcodes_set_interm_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_opcodes_set_interm_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_sizes_set_interm_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_sizes_set_interm_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_opcodes_set_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_opcodes_set_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_sizes_set_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_sizes_set_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_probe_ack_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_probe_ack_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_probe_ack_WIRE_2_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_probe_ack_WIRE_3_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _same_cycle_resp_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _same_cycle_resp_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _same_cycle_resp_WIRE_2_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _same_cycle_resp_WIRE_3_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _same_cycle_resp_WIRE_4_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _same_cycle_resp_WIRE_5_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [8:0] _c_first_WIRE_bits_source = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _c_first_WIRE_1_bits_source = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _c_first_WIRE_2_bits_source = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _c_first_WIRE_3_bits_source = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _c_set_wo_ready_WIRE_bits_source = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _c_set_wo_ready_WIRE_1_bits_source = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _c_set_WIRE_bits_source = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _c_set_WIRE_1_bits_source = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _c_opcodes_set_interm_WIRE_bits_source = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _c_opcodes_set_interm_WIRE_1_bits_source = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _c_sizes_set_interm_WIRE_bits_source = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _c_sizes_set_interm_WIRE_1_bits_source = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _c_opcodes_set_WIRE_bits_source = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _c_opcodes_set_WIRE_1_bits_source = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _c_sizes_set_WIRE_bits_source = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _c_sizes_set_WIRE_1_bits_source = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _c_probe_ack_WIRE_bits_source = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _c_probe_ack_WIRE_1_bits_source = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _c_probe_ack_WIRE_2_bits_source = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _c_probe_ack_WIRE_3_bits_source = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _same_cycle_resp_WIRE_bits_source = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _same_cycle_resp_WIRE_1_bits_source = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _same_cycle_resp_WIRE_2_bits_source = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _same_cycle_resp_WIRE_3_bits_source = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _same_cycle_resp_WIRE_4_bits_source = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _same_cycle_resp_WIRE_5_bits_source = 9'h0; // @[Bundles.scala:265:61] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [4098:0] _c_opcodes_set_T_1 = 4099'h0; // @[Monitor.scala:767:54] wire [4098:0] _c_sizes_set_T_1 = 4099'h0; // @[Monitor.scala:768:52] wire [11:0] _c_opcodes_set_T = 12'h0; // @[Monitor.scala:767:79] wire [11:0] _c_sizes_set_T = 12'h0; // @[Monitor.scala:768:77] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [3:0] _c_sizes_set_interm_T_1 = 4'h1; // @[Monitor.scala:766:59] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] c_sizes_set_interm = 4'h0; // @[Monitor.scala:755:40] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_sizes_set_interm_T = 4'h0; // @[Monitor.scala:766:51] wire [511:0] _c_set_wo_ready_T = 512'h1; // @[OneHot.scala:58:35] wire [511:0] _c_set_T = 512'h1; // @[OneHot.scala:58:35] wire [1027:0] c_opcodes_set = 1028'h0; // @[Monitor.scala:740:34] wire [1027:0] c_sizes_set = 1028'h0; // @[Monitor.scala:741:34] wire [256:0] c_set = 257'h0; // @[Monitor.scala:738:34] wire [256:0] c_set_wo_ready = 257'h0; // @[Monitor.scala:739:34] wire [5:0] _c_first_beats1_decode_T_2 = 6'h0; // @[package.scala:243:46] wire [5:0] _c_first_beats1_decode_T_1 = 6'h3F; // @[package.scala:243:76] wire [12:0] _c_first_beats1_decode_T = 13'h3F; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48] wire [2:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire [8:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _source_ok_uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _source_ok_uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _source_ok_uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _source_ok_uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _source_ok_uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_11 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_12 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_13 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_14 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_15 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_16 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_17 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_18 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_19 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_20 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_21 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_22 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_23 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_24 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_25 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_26 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_27 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_28 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_29 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_30 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_31 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_32 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_33 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_34 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_35 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_36 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_37 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_38 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_39 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_40 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_41 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_42 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_43 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_44 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_45 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_46 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_47 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_48 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_49 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_50 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_51 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_52 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_53 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_54 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_55 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_56 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_57 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_58 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_59 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_60 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_61 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_62 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_63 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_64 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_65 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _source_ok_uncommonBits_T_6 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _source_ok_uncommonBits_T_7 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _source_ok_uncommonBits_T_8 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _source_ok_uncommonBits_T_9 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _source_ok_uncommonBits_T_10 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _source_ok_uncommonBits_T_11 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire _source_ok_T = io_in_a_bits_source_0 == 9'h90; // @[Monitor.scala:36:7] wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [6:0] _source_ok_T_1 = io_in_a_bits_source_0[8:2]; // @[Monitor.scala:36:7] wire [6:0] _source_ok_T_7 = io_in_a_bits_source_0[8:2]; // @[Monitor.scala:36:7] wire [6:0] _source_ok_T_13 = io_in_a_bits_source_0[8:2]; // @[Monitor.scala:36:7] wire [6:0] _source_ok_T_19 = io_in_a_bits_source_0[8:2]; // @[Monitor.scala:36:7] wire _source_ok_T_2 = _source_ok_T_1 == 7'h20; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_4 = _source_ok_T_2; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_6 = _source_ok_T_4; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1 = _source_ok_T_6; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_8 = _source_ok_T_7 == 7'h21; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_10 = _source_ok_T_8; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_12 = _source_ok_T_10; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_2 = _source_ok_T_12; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_14 = _source_ok_T_13 == 7'h22; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_16 = _source_ok_T_14; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_18 = _source_ok_T_16; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_3 = _source_ok_T_18; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_3 = _source_ok_uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_20 = _source_ok_T_19 == 7'h23; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_22 = _source_ok_T_20; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_24 = _source_ok_T_22; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_4 = _source_ok_T_24; // @[Parameters.scala:1138:31] wire [5:0] source_ok_uncommonBits_4 = _source_ok_uncommonBits_T_4[5:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] _source_ok_T_25 = io_in_a_bits_source_0[8:6]; // @[Monitor.scala:36:7] wire [2:0] _source_ok_T_31 = io_in_a_bits_source_0[8:6]; // @[Monitor.scala:36:7] wire _source_ok_T_26 = _source_ok_T_25 == 3'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_28 = _source_ok_T_26; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_30 = _source_ok_T_28; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_5 = _source_ok_T_30; // @[Parameters.scala:1138:31] wire [5:0] source_ok_uncommonBits_5 = _source_ok_uncommonBits_T_5[5:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_32 = _source_ok_T_31 == 3'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_34 = _source_ok_T_32; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_36 = _source_ok_T_34; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_6 = _source_ok_T_36; // @[Parameters.scala:1138:31] wire _source_ok_T_37 = io_in_a_bits_source_0 == 9'hA0; // @[Monitor.scala:36:7] wire _source_ok_WIRE_7 = _source_ok_T_37; // @[Parameters.scala:1138:31] wire _source_ok_T_38 = io_in_a_bits_source_0 == 9'hA1; // @[Monitor.scala:36:7] wire _source_ok_WIRE_8 = _source_ok_T_38; // @[Parameters.scala:1138:31] wire _source_ok_T_39 = io_in_a_bits_source_0 == 9'hA2; // @[Monitor.scala:36:7] wire _source_ok_WIRE_9 = _source_ok_T_39; // @[Parameters.scala:1138:31] wire _source_ok_T_40 = io_in_a_bits_source_0 == 9'h100; // @[Monitor.scala:36:7] wire _source_ok_WIRE_10 = _source_ok_T_40; // @[Parameters.scala:1138:31] wire _source_ok_T_41 = _source_ok_WIRE_0 \| _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_42 = _source_ok_T_41 \| _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_43 = _source_ok_T_42 \| _source_ok_WIRE_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_44 = _source_ok_T_43 \| _source_ok_WIRE_4; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_45 = _source_ok_T_44 \| _source_ok_WIRE_5; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_46 = _source_ok_T_45 \| _source_ok_WIRE_6; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_47 = _source_ok_T_46 \| _source_ok_WIRE_7; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_48 = _source_ok_T_47 \| _source_ok_WIRE_8; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_49 = _source_ok_T_48 \| _source_ok_WIRE_9; // @[Parameters.scala:1138:31, :1139:46] wire source_ok = _source_ok_T_49 \| _source_ok_WIRE_10; // @[Parameters.scala:1138:31, :1139:46] wire [12:0] _GEN = 13'h3F << io_in_a_bits_size_0; // @[package.scala:243:71] wire [12:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [12:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [12:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [5:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [20:0] _is_aligned_T = {15'h0, io_in_a_bits_address_0[5:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 21'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 3'h2; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 \| _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 \| _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 \| _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 \| _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 \| _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 \| _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 \| _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 \| _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [1:0] uncommonBits = _uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_1 = _uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_2 = _uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_3 = _uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire [5:0] uncommonBits_4 = _uncommonBits_T_4[5:0]; // @[Parameters.scala:52:{29,56}] wire [5:0] uncommonBits_5 = _uncommonBits_T_5[5:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_6 = _uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_7 = _uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_8 = _uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_9 = _uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}] wire [5:0] uncommonBits_10 = _uncommonBits_T_10[5:0]; // @[Parameters.scala:52:{29,56}] wire [5:0] uncommonBits_11 = _uncommonBits_T_11[5:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_12 = _uncommonBits_T_12[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_13 = _uncommonBits_T_13[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_14 = _uncommonBits_T_14[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_15 = _uncommonBits_T_15[1:0]; // @[Parameters.scala:52:{29,56}] wire [5:0] uncommonBits_16 = _uncommonBits_T_16[5:0]; // @[Parameters.scala:52:{29,56}] wire [5:0] uncommonBits_17 = _uncommonBits_T_17[5:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_18 = _uncommonBits_T_18[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_19 = _uncommonBits_T_19[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_20 = _uncommonBits_T_20[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_21 = _uncommonBits_T_21[1:0]; // @[Parameters.scala:52:{29,56}] wire [5:0] uncommonBits_22 = _uncommonBits_T_22[5:0]; // @[Parameters.scala:52:{29,56}] wire [5:0] uncommonBits_23 = _uncommonBits_T_23[5:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_24 = _uncommonBits_T_24[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_25 = _uncommonBits_T_25[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_26 = _uncommonBits_T_26[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_27 = _uncommonBits_T_27[1:0]; // @[Parameters.scala:52:{29,56}] wire [5:0] uncommonBits_28 = _uncommonBits_T_28[5:0]; // @[Parameters.scala:52:{29,56}] wire [5:0] uncommonBits_29 = _uncommonBits_T_29[5:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_30 = _uncommonBits_T_30[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_31 = _uncommonBits_T_31[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_32 = _uncommonBits_T_32[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_33 = _uncommonBits_T_33[1:0]; // @[Parameters.scala:52:{29,56}] wire [5:0] uncommonBits_34 = _uncommonBits_T_34[5:0]; // @[Parameters.scala:52:{29,56}] wire [5:0] uncommonBits_35 = _uncommonBits_T_35[5:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_36 = _uncommonBits_T_36[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_37 = _uncommonBits_T_37[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_38 = _uncommonBits_T_38[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_39 = _uncommonBits_T_39[1:0]; // @[Parameters.scala:52:{29,56}] wire [5:0] uncommonBits_40 = _uncommonBits_T_40[5:0]; // @[Parameters.scala:52:{29,56}] wire [5:0] uncommonBits_41 = _uncommonBits_T_41[5:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_42 = _uncommonBits_T_42[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_43 = _uncommonBits_T_43[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_44 = _uncommonBits_T_44[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_45 = _uncommonBits_T_45[1:0]; // @[Parameters.scala:52:{29,56}] wire [5:0] uncommonBits_46 = _uncommonBits_T_46[5:0]; // @[Parameters.scala:52:{29,56}] wire [5:0] uncommonBits_47 = _uncommonBits_T_47[5:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_48 = _uncommonBits_T_48[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_49 = _uncommonBits_T_49[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_50 = _uncommonBits_T_50[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_51 = _uncommonBits_T_51[1:0]; // @[Parameters.scala:52:{29,56}] wire [5:0] uncommonBits_52 = _uncommonBits_T_52[5:0]; // @[Parameters.scala:52:{29,56}] wire [5:0] uncommonBits_53 = _uncommonBits_T_53[5:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_54 = _uncommonBits_T_54[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_55 = _uncommonBits_T_55[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_56 = _uncommonBits_T_56[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_57 = _uncommonBits_T_57[1:0]; // @[Parameters.scala:52:{29,56}] wire [5:0] uncommonBits_58 = _uncommonBits_T_58[5:0]; // @[Parameters.scala:52:{29,56}] wire [5:0] uncommonBits_59 = _uncommonBits_T_59[5:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_60 = _uncommonBits_T_60[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_61 = _uncommonBits_T_61[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_62 = _uncommonBits_T_62[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_63 = _uncommonBits_T_63[1:0]; // @[Parameters.scala:52:{29,56}] wire [5:0] uncommonBits_64 = _uncommonBits_T_64[5:0]; // @[Parameters.scala:52:{29,56}] wire [5:0] uncommonBits_65 = _uncommonBits_T_65[5:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_50 = io_in_d_bits_source_0 == 9'h90; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_0 = _source_ok_T_50; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_6 = _source_ok_uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}] wire [6:0] _source_ok_T_51 = io_in_d_bits_source_0[8:2]; // @[Monitor.scala:36:7] wire [6:0] _source_ok_T_57 = io_in_d_bits_source_0[8:2]; // @[Monitor.scala:36:7] wire [6:0] _source_ok_T_63 = io_in_d_bits_source_0[8:2]; // @[Monitor.scala:36:7] wire [6:0] _source_ok_T_69 = io_in_d_bits_source_0[8:2]; // @[Monitor.scala:36:7] wire _source_ok_T_52 = _source_ok_T_51 == 7'h20; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_54 = _source_ok_T_52; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_56 = _source_ok_T_54; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_1 = _source_ok_T_56; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_7 = _source_ok_uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_58 = _source_ok_T_57 == 7'h21; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_60 = _source_ok_T_58; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_62 = _source_ok_T_60; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_2 = _source_ok_T_62; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_8 = _source_ok_uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_64 = _source_ok_T_63 == 7'h22; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_66 = _source_ok_T_64; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_68 = _source_ok_T_66; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_3 = _source_ok_T_68; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_9 = _source_ok_uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_70 = _source_ok_T_69 == 7'h23; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_72 = _source_ok_T_70; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_74 = _source_ok_T_72; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_4 = _source_ok_T_74; // @[Parameters.scala:1138:31] wire [5:0] source_ok_uncommonBits_10 = _source_ok_uncommonBits_T_10[5:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] _source_ok_T_75 = io_in_d_bits_source_0[8:6]; // @[Monitor.scala:36:7] wire [2:0] _source_ok_T_81 = io_in_d_bits_source_0[8:6]; // @[Monitor.scala:36:7] wire _source_ok_T_76 = _source_ok_T_75 == 3'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_78 = _source_ok_T_76; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_80 = _source_ok_T_78; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_5 = _source_ok_T_80; // @[Parameters.scala:1138:31] wire [5:0] source_ok_uncommonBits_11 = _source_ok_uncommonBits_T_11[5:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_82 = _source_ok_T_81 == 3'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_84 = _source_ok_T_82; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_86 = _source_ok_T_84; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_6 = _source_ok_T_86; // @[Parameters.scala:1138:31] wire _source_ok_T_87 = io_in_d_bits_source_0 == 9'hA0; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_7 = _source_ok_T_87; // @[Parameters.scala:1138:31] wire _source_ok_T_88 = io_in_d_bits_source_0 == 9'hA1; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_8 = _source_ok_T_88; // @[Parameters.scala:1138:31] wire _source_ok_T_89 = io_in_d_bits_source_0 == 9'hA2; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_9 = _source_ok_T_89; // @[Parameters.scala:1138:31] wire _source_ok_T_90 = io_in_d_bits_source_0 == 9'h100; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_10 = _source_ok_T_90; // @[Parameters.scala:1138:31] wire _source_ok_T_91 = _source_ok_WIRE_1_0 \| _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_92 = _source_ok_T_91 \| _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_93 = _source_ok_T_92 \| _source_ok_WIRE_1_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_94 = _source_ok_T_93 \| _source_ok_WIRE_1_4; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_95 = _source_ok_T_94 \| _source_ok_WIRE_1_5; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_96 = _source_ok_T_95 \| _source_ok_WIRE_1_6; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_97 = _source_ok_T_96 \| _source_ok_WIRE_1_7; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_98 = _source_ok_T_97 \| _source_ok_WIRE_1_8; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_99 = _source_ok_T_98 \| _source_ok_WIRE_1_9; // @[Parameters.scala:1138:31, :1139:46] wire source_ok_1 = _source_ok_T_99 \| _source_ok_WIRE_1_10; // @[Parameters.scala:1138:31, :1139:46] wire _T_1266 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_1266; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_1266; // @[Decoupled.scala:51:35] wire [5:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [2:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [2:0] a_first_counter; // @[Edges.scala:229:27] wire [3:0] _a_first_counter1_T = {1'h0, a_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] a_first_counter1 = _a_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T \| _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [2:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [2:0] size; // @[Monitor.scala:389:22] reg [8:0] source; // @[Monitor.scala:390:22] reg [20:0] address; // @[Monitor.scala:391:22] wire _T_1334 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_1334; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_1334; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_1334; // @[Decoupled.scala:51:35] wire [12:0] _GEN_0 = 13'h3F << io_in_d_bits_size_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [2:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T = {1'h0, d_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1 = _d_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T \| _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [2:0] size_1; // @[Monitor.scala:540:22] reg [8:0] source_1; // @[Monitor.scala:541:22] reg [256:0] inflight; // @[Monitor.scala:614:27] reg [1027:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [1027:0] inflight_sizes; // @[Monitor.scala:618:33] wire [5:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [2:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [2:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [2:0] a_first_counter_1; // @[Edges.scala:229:27] wire [3:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] a_first_counter1_1 = _a_first_counter1_T_1[2:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 \| _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [2:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [5:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46] wire [2:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter_1; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1_1 = _d_first_counter1_T_1[2:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 \| _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [256:0] a_set; // @[Monitor.scala:626:34] wire [256:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [1027:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [1027:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [11:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [11:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [11:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :641:65] wire [11:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [11:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :681:99] wire [11:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [11:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :750:67] wire [11:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [11:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :791:99] wire [1027:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [1027:0] _a_opcode_lookup_T_6 = {1024'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [1027:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[1027:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [3:0] a_size_lookup; // @[Monitor.scala:639:33] wire [1027:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [1027:0] _a_size_lookup_T_6 = {1024'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}] wire [1027:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[1027:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [3:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [511:0] _GEN_2 = 512'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [511:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_2; // @[OneHot.scala:58:35] wire [511:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_2; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[256:0] : 257'h0; // @[OneHot.scala:58:35] wire _T_1199 = _T_1266 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_1199 ? _a_set_T[256:0] : 257'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_1199 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [3:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [3:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_1199 ? _a_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [11:0] _GEN_3 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [11:0] _a_opcodes_set_T; // @[Monitor.scala:659:79] assign _a_opcodes_set_T = _GEN_3; // @[Monitor.scala:659:79] wire [11:0] _a_sizes_set_T; // @[Monitor.scala:660:77] assign _a_sizes_set_T = _GEN_3; // @[Monitor.scala:659:79, :660:77] wire [4098:0] _a_opcodes_set_T_1 = {4095'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_1199 ? _a_opcodes_set_T_1[1027:0] : 1028'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [4098:0] _a_sizes_set_T_1 = {4095'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_1199 ? _a_sizes_set_T_1[1027:0] : 1028'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [256:0] d_clr; // @[Monitor.scala:664:34] wire [256:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [1027:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [1027:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46] wire _T_1245 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [511:0] _GEN_5 = 512'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [511:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35] wire [511:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35] wire [511:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35] wire [511:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_1245 & ~d_release_ack ? _d_clr_wo_ready_T[256:0] : 257'h0; // @[OneHot.scala:58:35] wire _T_1214 = _T_1334 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_1214 ? _d_clr_T[256:0] : 257'h0; // @[OneHot.scala:58:35] wire [4110:0] _d_opcodes_clr_T_5 = 4111'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_1214 ? _d_opcodes_clr_T_5[1027:0] : 1028'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [4110:0] _d_sizes_clr_T_5 = 4111'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_1214 ? _d_sizes_clr_T_5[1027:0] : 1028'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [256:0] _inflight_T = inflight \| a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [256:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [256:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [1027:0] _inflight_opcodes_T = inflight_opcodes \| a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [1027:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [1027:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [1027:0] _inflight_sizes_T = inflight_sizes \| a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [1027:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [1027:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [256:0] inflight_1; // @[Monitor.scala:726:35] wire [256:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [1027:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [1027:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [1027:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [1027:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire [5:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[5:3]; // @[package.scala:243:46] wire [2:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter_2; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1_2 = _d_first_counter1_T_2[2:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 \| _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [3:0] c_size_lookup; // @[Monitor.scala:748:35] wire [1027:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [1027:0] _c_opcode_lookup_T_6 = {1024'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [1027:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[1027:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [1027:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [1027:0] _c_size_lookup_T_6 = {1024'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}] wire [1027:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[1027:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [256:0] d_clr_1; // @[Monitor.scala:774:34] wire [256:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [1027:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [1027:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_1310 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_1310 & d_release_ack_1 ? _d_clr_wo_ready_T_1[256:0] : 257'h0; // @[OneHot.scala:58:35] wire _T_1292 = _T_1334 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_1292 ? _d_clr_T_1[256:0] : 257'h0; // @[OneHot.scala:58:35] wire [4110:0] _d_opcodes_clr_T_11 = 4111'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_1292 ? _d_opcodes_clr_T_11[1027:0] : 1028'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [4110:0] _d_sizes_clr_T_11 = 4111'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_1292 ? _d_sizes_clr_T_11[1027:0] : 1028'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 9'h0; // @[Monitor.scala:36:7, :795:113] wire [256:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [256:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [1027:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [1027:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [1027:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [1027:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to the following Chisel files. File Crossing.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.interrupts import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.util.{SynchronizerShiftReg, AsyncResetReg} @deprecated("IntXing does not ensure interrupt source is glitch free. Use IntSyncSource and IntSyncSink", "rocket-chip 1.2") class IntXing(sync: Int = 3)(implicit p: Parameters) extends LazyModule { val intnode = IntAdapterNode() lazy val module = new Impl class Impl extends LazyModuleImp(this) { (intnode.in zip intnode.out) foreach { case ((in, _), (out, _)) => out := SynchronizerShiftReg(in, sync) } } } object IntSyncCrossingSource { def apply(alreadyRegistered: Boolean = false)(implicit p: Parameters) = { val intsource = LazyModule(new IntSyncCrossingSource(alreadyRegistered)) intsource.node } } class IntSyncCrossingSource(alreadyRegistered: Boolean = false)(implicit p: Parameters) extends LazyModule { val node = IntSyncSourceNode(alreadyRegistered) lazy val module = if (alreadyRegistered) (new ImplRegistered) else (new Impl) class Impl extends LazyModuleImp(this) { def outSize = node.out.headOption.map(_._1.sync.size).getOrElse(0) override def desiredName = s"IntSyncCrossingSource_n${node.out.size}x${outSize}" (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out.sync := AsyncResetReg(Cat(in.reverse)).asBools } } class ImplRegistered extends LazyRawModuleImp(this) { def outSize = node.out.headOption.map(_._1.sync.size).getOrElse(0) override def desiredName = s"IntSyncCrossingSource_n${node.out.size}x${outSize}_Registered" (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out.sync := in } } } object IntSyncCrossingSink { @deprecated("IntSyncCrossingSink which used the `sync` parameter to determine crossing type is deprecated. Use IntSyncAsyncCrossingSink, IntSyncRationalCrossingSink, or IntSyncSyncCrossingSink instead for > 1, 1, and 0 sync values respectively", "rocket-chip 1.2") def apply(sync: Int = 3)(implicit p: Parameters) = { val intsink = LazyModule(new IntSyncAsyncCrossingSink(sync)) intsink.node } } class IntSyncAsyncCrossingSink(sync: Int = 3)(implicit p: Parameters) extends LazyModule { val node = IntSyncSinkNode(sync) lazy val module = new Impl class Impl extends LazyModuleImp(this) { override def desiredName = s"IntSyncAsyncCrossingSink_n${node.out.size}x${node.out.head._1.size}" (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out := SynchronizerShiftReg(in.sync, sync) } } } object IntSyncAsyncCrossingSink { def apply(sync: Int = 3)(implicit p: Parameters) = { val intsink = LazyModule(new IntSyncAsyncCrossingSink(sync)) intsink.node } } class IntSyncSyncCrossingSink()(implicit p: Parameters) extends LazyModule { val node = IntSyncSinkNode(0) lazy val module = new Impl class Impl extends LazyRawModuleImp(this) { def outSize = node.out.headOption.map(_._1.size).getOrElse(0) override def desiredName = s"IntSyncSyncCrossingSink_n${node.out.size}x${outSize}" (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out := in.sync } } } object IntSyncSyncCrossingSink { def apply()(implicit p: Parameters) = { val intsink = LazyModule(new IntSyncSyncCrossingSink()) intsink.node } } class IntSyncRationalCrossingSink()(implicit p: Parameters) extends LazyModule { val node = IntSyncSinkNode(1) lazy val module = new Impl class Impl extends LazyModuleImp(this) { def outSize = node.out.headOption.map(_._1.size).getOrElse(0) override def desiredName = s"IntSyncRationalCrossingSink_n${node.out.size}x${outSize}" (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out := RegNext(in.sync) } } } object IntSyncRationalCrossingSink { def apply()(implicit p: Parameters) = { val intsink = LazyModule(new IntSyncRationalCrossingSink()) intsink.node } } File LazyModuleImp.scala: package org.chipsalliance.diplomacy.lazymodule import chisel3.{withClockAndReset, Module, RawModule, Reset, _} import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo} import firrtl.passes.InlineAnnotation import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.nodes.Dangle import scala.collection.immutable.SortedMap /** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]]. * * This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy. / sealed trait LazyModuleImpLike extends RawModule { /* [[LazyModule]] that contains this instance. / val wrapper: LazyModule /* IOs that will be automatically "punched" for this instance. / val auto: AutoBundle /* The metadata that describes the [[HalfEdge]]s which generated [[auto]]. / protected[diplomacy] val dangles: Seq[Dangle] // [[wrapper.module]] had better not be accessed while LazyModules are still being built! require( LazyModule.scope.isEmpty, s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}" ) /* Set module name. Defaults to the containing LazyModule's desiredName. / override def desiredName: String = wrapper.desiredName suggestName(wrapper.suggestedName) /* [[Parameters]] for chisel [[Module]]s. / implicit val p: Parameters = wrapper.p /* instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and * submodules. / protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = { // 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]], // 2. return [[Dangle]]s from each module. val childDangles = wrapper.children.reverse.flatMap { c => implicit val sourceInfo: SourceInfo = c.info c.cloneProto.map { cp => // If the child is a clone, then recursively set cloneProto of its children as well def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = { require(bases.size == clones.size) (bases.zip(clones)).map { case (l, r) => require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}") l.cloneProto = Some(r) assignCloneProtos(l.children, r.children) } } assignCloneProtos(c.children, cp.children) // Clone the child module as a record, and get its [[AutoBundle]] val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName) val clonedAuto = clone("auto").asInstanceOf[AutoBundle] // Get the empty [[Dangle]]'s of the cloned child val rawDangles = c.cloneDangles() require(rawDangles.size == clonedAuto.elements.size) // Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) } dangles }.getOrElse { // For non-clones, instantiate the child module val mod = try { Module(c.module) } catch { case e: ChiselException => { println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}") throw e } } mod.dangles } } // Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]]. // This will result in a sequence of [[Dangle]] from these [[BaseNode]]s. val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate()) // Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]] val allDangles = nodeDangles ++ childDangles // Group [[allDangles]] by their [[source]]. val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _) // For each [[source]] set of [[Dangle]]s of size 2, ensure that these // can be connected as a source-sink pair (have opposite flipped value). // Make the connection and mark them as [[done]]. val done = Set() ++ pairing.values.filter(_.size == 2).map { case Seq(a, b) => require(a.flipped != b.flipped) // @todo <> in chisel3 makes directionless connection. if (a.flipped) { a.data <> b.data } else { b.data <> a.data } a.source case _ => None } // Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module. val forward = allDangles.filter(d => !done(d.source)) // Generate [[AutoBundle]] IO from [[forward]]. val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _)) // Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]] val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) => if (d.flipped) { d.data <> io } else { io <> d.data } d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name) } // Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]]. wrapper.inModuleBody.reverse.foreach { _() } if (wrapper.shouldBeInlined) { chisel3.experimental.annotate(new ChiselAnnotation { def toFirrtl = InlineAnnotation(toNamed) }) } // Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]]. (auto, dangles) } } /* Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. / class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike { /* Instantiate hardware of this `Module`. / val (auto, dangles) = instantiate() } /* Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. / class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike { // These wires are the default clock+reset for all LazyModule children. // It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the // [[LazyRawModuleImp]] children. // Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly. /* drive clock explicitly. / val childClock: Clock = Wire(Clock()) /* drive reset explicitly. / val childReset: Reset = Wire(Reset()) // the default is that these are disabled childClock := false.B.asClock childReset := chisel3.DontCare def provideImplicitClockToLazyChildren: Boolean = false val (auto, dangles) = if (provideImplicitClockToLazyChildren) { withClockAndReset(childClock, childReset) { instantiate() } } else { instantiate() } } File MixedNode.scala: package org.chipsalliance.diplomacy.nodes import chisel3.{Data, DontCare, Wire} import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.{Field, Parameters} import org.chipsalliance.diplomacy.ValName import org.chipsalliance.diplomacy.sourceLine /* One side metadata of a [[Dangle]]. * * Describes one side of an edge going into or out of a [[BaseNode]]. * * @param serial * the global [[BaseNode.serial]] number of the [[BaseNode]] that this [[HalfEdge]] connects to. * @param index * the `index` in the [[BaseNode]]'s input or output port list that this [[HalfEdge]] belongs to. / case class HalfEdge(serial: Int, index: Int) extends Ordered[HalfEdge] { import scala.math.Ordered.orderingToOrdered def compare(that: HalfEdge): Int = HalfEdge.unapply(this).compare(HalfEdge.unapply(that)) } /* [[Dangle]] captures the `IO` information of a [[LazyModule]] and which two [[BaseNode]]s the [[Edges]]/[[Bundle]] * connects. * * [[Dangle]]s are generated by [[BaseNode.instantiate]] using [[MixedNode.danglesOut]] and [[MixedNode.danglesIn]] , * [[LazyModuleImp.instantiate]] connects those that go to internal or explicit IO connections in a [[LazyModule]]. * * @param source * the source [[HalfEdge]] of this [[Dangle]], which captures the source [[BaseNode]] and the port `index` within * that [[BaseNode]]. * @param sink * sink [[HalfEdge]] of this [[Dangle]], which captures the sink [[BaseNode]] and the port `index` within that * [[BaseNode]]. * @param flipped * flip or not in [[AutoBundle.makeElements]]. If true this corresponds to `danglesOut`, if false it corresponds to * `danglesIn`. * @param dataOpt * actual [[Data]] for the hardware connection. Can be empty if this belongs to a cloned module / case class Dangle(source: HalfEdge, sink: HalfEdge, flipped: Boolean, name: String, dataOpt: Option[Data]) { def data = dataOpt.get } /* [[Edges]] is a collection of parameters describing the functionality and connection for an interface, which is often * derived from the interconnection protocol and can inform the parameterization of the hardware bundles that actually * implement the protocol. / case class Edges[EI, EO](in: Seq[EI], out: Seq[EO]) /* A field available in [[Parameters]] used to determine whether [[InwardNodeImp.monitor]] will be called. / case object MonitorsEnabled extends Field[Boolean](true) /* When rendering the edge in a graphical format, flip the order in which the edges' source and sink are presented. * * For example, when rendering graphML, yEd by default tries to put the source node vertically above the sink node, but * [[RenderFlipped]] inverts this relationship. When a particular [[LazyModule]] contains both source nodes and sink * nodes, flipping the rendering of one node's edge will usual produce a more concise visual layout for the * [[LazyModule]]. / case object RenderFlipped extends Field[Boolean](false) /* The sealed node class in the package, all node are derived from it. * * @param inner * Sink interface implementation. * @param outer * Source interface implementation. * @param valName * val name of this node. * @tparam DI * Downward-flowing parameters received on the inner side of the node. It is usually a brunch of parameters * describing the protocol parameters from a source. For an [[InwardNode]], it is determined by the connected * [[OutwardNode]]. Since it can be connected to multiple sources, this parameter is always a Seq of source port * parameters. * @tparam UI * Upward-flowing parameters generated by the inner side of the node. It is usually a brunch of parameters describing * the protocol parameters of a sink. For an [[InwardNode]], it is determined itself. * @tparam EI * Edge Parameters describing a connection on the inner side of the node. It is usually a brunch of transfers * specified for a sink according to protocol. * @tparam BI * Bundle type used when connecting to the inner side of the node. It is a hardware interface of this sink interface. * It should extends from [[chisel3.Data]], which represents the real hardware. * @tparam DO * Downward-flowing parameters generated on the outer side of the node. It is usually a brunch of parameters * describing the protocol parameters of a source. For an [[OutwardNode]], it is determined itself. * @tparam UO * Upward-flowing parameters received by the outer side of the node. It is usually a brunch of parameters describing * the protocol parameters from a sink. For an [[OutwardNode]], it is determined by the connected [[InwardNode]]. * Since it can be connected to multiple sinks, this parameter is always a Seq of sink port parameters. * @tparam EO * Edge Parameters describing a connection on the outer side of the node. It is usually a brunch of transfers * specified for a source according to protocol. * @tparam BO * Bundle type used when connecting to the outer side of the node. It is a hardware interface of this source * interface. It should extends from [[chisel3.Data]], which represents the real hardware. * * @note * Call Graph of [[MixedNode]] * - line `─`: source is process by a function and generate pass to others * - Arrow `→`: target of arrow is generated by source * * {{{ * (from the other node) * ┌─────────────────────────────────────────────────────────[[InwardNode.uiParams]]─────────────┐ * ↓ │ * (binding node when elaboration) [[OutwardNode.uoParams]]────────────────────────[[MixedNode.mapParamsU]]→──────────┐ │ * [[InwardNode.accPI]] │ │ │ * │ │ (based on protocol) │ * │ │ [[MixedNode.inner.edgeI]] │ * │ │ ↓ │ * ↓ │ │ │ * (immobilize after elaboration) (inward port from [[OutwardNode]]) │ ↓ │ * [[InwardNode.iBindings]]──┐ [[MixedNode.iDirectPorts]]────────────────────→[[MixedNode.iPorts]] [[InwardNode.uiParams]] │ * │ │ ↑ │ │ │ * │ │ │ [[OutwardNode.doParams]] │ │ * │ │ │ (from the other node) │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * │ │ │ └────────┬──────────────┤ │ * │ │ │ │ │ │ * │ │ │ │ (based on protocol) │ * │ │ │ │ [[MixedNode.inner.edgeI]] │ * │ │ │ │ │ │ * │ │ (from the other node) │ ↓ │ * │ └───[[OutwardNode.oPortMapping]] [[OutwardNode.oStar]] │ [[MixedNode.edgesIn]]───┐ │ * │ ↑ ↑ │ │ ↓ │ * │ │ │ │ │ [[MixedNode.in]] │ * │ │ │ │ ↓ ↑ │ * │ (solve star connection) │ │ │ [[MixedNode.bundleIn]]──┘ │ * ├───[[MixedNode.resolveStar]]→─┼─────────────────────────────┤ └────────────────────────────────────┐ │ * │ │ │ [[MixedNode.bundleOut]]─┐ │ │ * │ │ │ ↑ ↓ │ │ * │ │ │ │ [[MixedNode.out]] │ │ * │ ↓ ↓ │ ↑ │ │ * │ ┌─────[[InwardNode.iPortMapping]] [[InwardNode.iStar]] [[MixedNode.edgesOut]]──┘ │ │ * │ │ (from the other node) ↑ │ │ * │ │ │ │ │ │ * │ │ │ [[MixedNode.outer.edgeO]] │ │ * │ │ │ (based on protocol) │ │ * │ │ │ │ │ │ * │ │ │ ┌────────────────────────────────────────┤ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * (immobilize after elaboration)│ ↓ │ │ │ │ * [[OutwardNode.oBindings]]─┘ [[MixedNode.oDirectPorts]]───→[[MixedNode.oPorts]] [[OutwardNode.doParams]] │ │ * ↑ (inward port from [[OutwardNode]]) │ │ │ │ * │ ┌─────────────────────────────────────────┤ │ │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * [[OutwardNode.accPO]] │ ↓ │ │ │ * (binding node when elaboration) │ [[InwardNode.diParams]]─────→[[MixedNode.mapParamsD]]────────────────────────────┘ │ │ * │ ↑ │ │ * │ └──────────────────────────────────────────────────────────────────────────────────────────┘ │ * └──────────────────────────────────────────────────────────────────────────────────────────────────────────┘ * }}} / abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data]( val inner: InwardNodeImp[DI, UI, EI, BI], val outer: OutwardNodeImp[DO, UO, EO, BO] )( implicit valName: ValName) extends BaseNode with NodeHandle[DI, UI, EI, BI, DO, UO, EO, BO] with InwardNode[DI, UI, BI] with OutwardNode[DO, UO, BO] { // Generate a [[NodeHandle]] with inward and outward node are both this node. val inward = this val outward = this /* Debug info of nodes binding. / def bindingInfo: String = s"""$iBindingInfo \|$oBindingInfo \|""".stripMargin /* Debug info of ports connecting. / def connectedPortsInfo: String = s"""${oPorts.size} outward ports connected: [${oPorts.map(_._2.name).mkString(",")}] \|${iPorts.size} inward ports connected: [${iPorts.map(_._2.name).mkString(",")}] \|""".stripMargin /* Debug info of parameters propagations. / def parametersInfo: String = s"""${doParams.size} downstream outward parameters: [${doParams.mkString(",")}] \|${uoParams.size} upstream outward parameters: [${uoParams.mkString(",")}] \|${diParams.size} downstream inward parameters: [${diParams.mkString(",")}] \|${uiParams.size} upstream inward parameters: [${uiParams.mkString(",")}] \|""".stripMargin /* For a given node, converts [[OutwardNode.accPO]] and [[InwardNode.accPI]] to [[MixedNode.oPortMapping]] and * [[MixedNode.iPortMapping]]. * * Given counts of known inward and outward binding and inward and outward star bindings, return the resolved inward * stars and outward stars. * * This method will also validate the arguments and throw a runtime error if the values are unsuitable for this type * of node. * * @param iKnown * Number of known-size ([[BIND_ONCE]]) input bindings. * @param oKnown * Number of known-size ([[BIND_ONCE]]) output bindings. * @param iStar * Number of unknown size ([[BIND_STAR]]) input bindings. * @param oStar * Number of unknown size ([[BIND_STAR]]) output bindings. * @return * A Tuple of the resolved number of input and output connections. / protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStar: Int, oStar: Int): (Int, Int) /* Function to generate downward-flowing outward params from the downward-flowing input params and the current output * ports. * * @param n * The size of the output sequence to generate. * @param p * Sequence of downward-flowing input parameters of this node. * @return * A `n`-sized sequence of downward-flowing output edge parameters. / protected[diplomacy] def mapParamsD(n: Int, p: Seq[DI]): Seq[DO] /* Function to generate upward-flowing input parameters from the upward-flowing output parameters [[uiParams]]. * * @param n * Size of the output sequence. * @param p * Upward-flowing output edge parameters. * @return * A n-sized sequence of upward-flowing input edge parameters. / protected[diplomacy] def mapParamsU(n: Int, p: Seq[UO]): Seq[UI] /* @return * The sink cardinality of the node, the number of outputs bound with [[BIND_QUERY]] summed with inputs bound with * [[BIND_STAR]]. / protected[diplomacy] lazy val sinkCard: Int = oBindings.count(_._3 == BIND_QUERY) + iBindings.count(_._3 == BIND_STAR) /* @return * The source cardinality of this node, the number of inputs bound with [[BIND_QUERY]] summed with the number of * output bindings bound with [[BIND_STAR]]. / protected[diplomacy] lazy val sourceCard: Int = iBindings.count(_._3 == BIND_QUERY) + oBindings.count(_._3 == BIND_STAR) /* @return list of nodes involved in flex bindings with this node. / protected[diplomacy] lazy val flexes: Seq[BaseNode] = oBindings.filter(_._3 == BIND_FLEX).map(_._2) ++ iBindings.filter(_._3 == BIND_FLEX).map(_._2) /* Resolves the flex to be either source or sink and returns the offset where the [[BIND_STAR]] operators begin * greedily taking up the remaining connections. * * @return * A value >= 0 if it is sink cardinality, a negative value for source cardinality. The magnitude of the return * value is not relevant. / protected[diplomacy] lazy val flexOffset: Int = { /* Recursively performs a depth-first search of the [[flexes]], [[BaseNode]]s connected to this node with flex * operators. The algorithm bottoms out when we either get to a node we have already visited or when we get to a * connection that is not a flex and can set the direction for us. Otherwise, recurse by visiting the `flexes` of * each node in the current set and decide whether they should be added to the set or not. * * @return * the mapping of [[BaseNode]] indexed by their serial numbers. / def DFS(v: BaseNode, visited: Map[Int, BaseNode]): Map[Int, BaseNode] = { if (visited.contains(v.serial) \|\| !v.flexibleArityDirection) { visited } else { v.flexes.foldLeft(visited + (v.serial -> v))((sum, n) => DFS(n, sum)) } } /* Determine which [[BaseNode]] are involved in resolving the flex connections to/from this node. * * @example * {{{ * a := b := c * d := b * e := f * }}} * * `flexSet` for `a`, `b`, `c`, or `d` will be `Set(a, b, c, d)` `flexSet` for `e` or `f` will be `Set(e,f)` / val flexSet = DFS(this, Map()).values /* The total number of := operators where we're on the left. / val allSink = flexSet.map(_.sinkCard).sum /** The total number of :=* operators used when we're on the right. / val allSource = flexSet.map(_.sourceCard).sum require( allSink == 0 \|\| allSource == 0, s"The nodes ${flexSet.map(_.name)} which are inter-connected by :=* have ${allSink} := operators and ${allSource} := operators connected to them, making it impossible to determine cardinality inference direction." ) allSink - allSource } /** @return A value >= 0 if it is sink cardinality, a negative value for source cardinality. / protected[diplomacy] def edgeArityDirection(n: BaseNode): Int = { if (flexibleArityDirection) flexOffset else if (n.flexibleArityDirection) n.flexOffset else 0 } /* For a node which is connected between two nodes, select the one that will influence the direction of the flex * resolution. / protected[diplomacy] def edgeAritySelect(n: BaseNode, l: => Int, r: => Int): Int = { val dir = edgeArityDirection(n) if (dir < 0) l else if (dir > 0) r else 1 } /* Ensure that the same node is not visited twice in resolving `:=`, etc operators. / private var starCycleGuard = false /** Resolve all the star operators into concrete indicies. As connections are being made, some may be "star" * connections which need to be resolved. In some way to determine how many actual edges they correspond to. We also * need to build up the ranges of edges which correspond to each binding operator, so that We can apply the correct * edge parameters and later build up correct bundle connections. * * [[oPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that oPort (binding * operator). [[iPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that iPort * (binding operator). [[oStar]]: `Int` the value to return for this node `N` for any `N := foo` or `N :=* foo := bar` [[iStar]]: `Int` the value to return for this node `N` for any `foo :=* N` or `bar :=* foo := N` / protected[diplomacy] lazy val ( oPortMapping: Seq[(Int, Int)], iPortMapping: Seq[(Int, Int)], oStar: Int, iStar: Int ) = { try { if (starCycleGuard) throw StarCycleException() starCycleGuard = true // For a given node N... // Number of foo := N // + Number of bar :=* foo := N val oStars = oBindings.count { case (_, n, b, _, _) => b == BIND_STAR \|\| (b == BIND_FLEX && edgeArityDirection(n) < 0) } // Number of N := foo // + Number of N :=* foo := bar val iStars = iBindings.count { case (_, n, b, _, _) => b == BIND_STAR \|\| (b == BIND_FLEX && edgeArityDirection(n) > 0) } // 1 for foo := N // + bar.iStar for bar := foo := N // + foo.iStar for foo := N // + 0 for foo := N val oKnown = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, 0, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => 0 } }.sum // 1 for N := foo // + bar.oStar for N := foo :=* bar // + foo.oStar for N :=* foo // + 0 for N := foo val iKnown = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, 0) case BIND_QUERY => n.oStar case BIND_STAR => 0 } }.sum // Resolve star depends on the node subclass to implement the algorithm for this. val (iStar, oStar) = resolveStar(iKnown, oKnown, iStars, oStars) // Cumulative list of resolved outward binding range starting points val oSum = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, oStar, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => oStar } }.scanLeft(0)(_ + _) // Cumulative list of resolved inward binding range starting points val iSum = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, iStar) case BIND_QUERY => n.oStar case BIND_STAR => iStar } }.scanLeft(0)(_ + _) // Create ranges for each binding based on the running sums and return // those along with resolved values for the star operations. (oSum.init.zip(oSum.tail), iSum.init.zip(iSum.tail), oStar, iStar) } catch { case c: StarCycleException => throw c.copy(loop = context +: c.loop) } } /* Sequence of inward ports. * * This should be called after all star bindings are resolved. * * Each element is: `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. * `n` Instance of inward node. `p` View of [[Parameters]] where this connection was made. `s` Source info where this * connection was made in the source code. / protected[diplomacy] lazy val oDirectPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oBindings.flatMap { case (i, n, _, p, s) => // for each binding operator in this node, look at what it connects to val (start, end) = n.iPortMapping(i) (start until end).map { j => (j, n, p, s) } } /* Sequence of outward ports. * * This should be called after all star bindings are resolved. * * `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. `n` Instance of * outward node. `p` View of [[Parameters]] where this connection was made. `s` [[SourceInfo]] where this connection * was made in the source code. / protected[diplomacy] lazy val iDirectPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iBindings.flatMap { case (i, n, _, p, s) => // query this port index range of this node in the other side of node. val (start, end) = n.oPortMapping(i) (start until end).map { j => (j, n, p, s) } } // Ephemeral nodes ( which have non-None iForward/oForward) have in_degree = out_degree // Thus, there must exist an Eulerian path and the below algorithms terminate @scala.annotation.tailrec private def oTrace( tuple: (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) ): (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.iForward(i) match { case None => (i, n, p, s) case Some((j, m)) => oTrace((j, m, p, s)) } } @scala.annotation.tailrec private def iTrace( tuple: (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) ): (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.oForward(i) match { case None => (i, n, p, s) case Some((j, m)) => iTrace((j, m, p, s)) } } /* Final output ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - Numeric index of this binding in the [[InwardNode]] on the other end. * - [[InwardNode]] on the other end of this binding. * - A view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. / lazy val oPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oDirectPorts.map(oTrace) /* Final input ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - numeric index of this binding in [[OutwardNode]] on the other end. * - [[OutwardNode]] on the other end of this binding. * - a view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. / lazy val iPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iDirectPorts.map(iTrace) private var oParamsCycleGuard = false protected[diplomacy] lazy val diParams: Seq[DI] = iPorts.map { case (i, n, _, _) => n.doParams(i) } protected[diplomacy] lazy val doParams: Seq[DO] = { try { if (oParamsCycleGuard) throw DownwardCycleException() oParamsCycleGuard = true val o = mapParamsD(oPorts.size, diParams) require( o.size == oPorts.size, s"""Diplomacy has detected a problem with your graph: \|At the following node, the number of outward ports should equal the number of produced outward parameters. \|$context \|$connectedPortsInfo \|Downstreamed inward parameters: [${diParams.mkString(",")}] \|Produced outward parameters: [${o.mkString(",")}] \|""".stripMargin ) o.map(outer.mixO(_, this)) } catch { case c: DownwardCycleException => throw c.copy(loop = context +: c.loop) } } private var iParamsCycleGuard = false protected[diplomacy] lazy val uoParams: Seq[UO] = oPorts.map { case (o, n, _, _) => n.uiParams(o) } protected[diplomacy] lazy val uiParams: Seq[UI] = { try { if (iParamsCycleGuard) throw UpwardCycleException() iParamsCycleGuard = true val i = mapParamsU(iPorts.size, uoParams) require( i.size == iPorts.size, s"""Diplomacy has detected a problem with your graph: \|At the following node, the number of inward ports should equal the number of produced inward parameters. \|$context \|$connectedPortsInfo \|Upstreamed outward parameters: [${uoParams.mkString(",")}] \|Produced inward parameters: [${i.mkString(",")}] \|""".stripMargin ) i.map(inner.mixI(_, this)) } catch { case c: UpwardCycleException => throw c.copy(loop = context +: c.loop) } } /* Outward edge parameters. / protected[diplomacy] lazy val edgesOut: Seq[EO] = (oPorts.zip(doParams)).map { case ((i, n, p, s), o) => outer.edgeO(o, n.uiParams(i), p, s) } /* Inward edge parameters. / protected[diplomacy] lazy val edgesIn: Seq[EI] = (iPorts.zip(uiParams)).map { case ((o, n, p, s), i) => inner.edgeI(n.doParams(o), i, p, s) } /* A tuple of the input edge parameters and output edge parameters for the edges bound to this node. * * If you need to access to the edges of a foreign Node, use this method (in/out create bundles). / lazy val edges: Edges[EI, EO] = Edges(edgesIn, edgesOut) /* Create actual Wires corresponding to the Bundles parameterized by the outward edges of this node. / protected[diplomacy] lazy val bundleOut: Seq[BO] = edgesOut.map { e => val x = Wire(outer.bundleO(e)).suggestName(s"${valName.value}Out") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } /* Create actual Wires corresponding to the Bundles parameterized by the inward edges of this node. / protected[diplomacy] lazy val bundleIn: Seq[BI] = edgesIn.map { e => val x = Wire(inner.bundleI(e)).suggestName(s"${valName.value}In") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } private def emptyDanglesOut: Seq[Dangle] = oPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(serial, i), sink = HalfEdge(n.serial, j), flipped = false, name = wirePrefix + "out", dataOpt = None ) } private def emptyDanglesIn: Seq[Dangle] = iPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(n.serial, j), sink = HalfEdge(serial, i), flipped = true, name = wirePrefix + "in", dataOpt = None ) } /* Create the [[Dangle]]s which describe the connections from this node output to other nodes inputs. / protected[diplomacy] def danglesOut: Seq[Dangle] = emptyDanglesOut.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleOut(i))) } /* Create the [[Dangle]]s which describe the connections from this node input from other nodes outputs. / protected[diplomacy] def danglesIn: Seq[Dangle] = emptyDanglesIn.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleIn(i))) } private[diplomacy] var instantiated = false /* Gather Bundle and edge parameters of outward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. / def out: Seq[(BO, EO)] = { require( instantiated, s"$name.out should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleOut.zip(edgesOut) } /* Gather Bundle and edge parameters of inward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. / def in: Seq[(BI, EI)] = { require( instantiated, s"$name.in should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleIn.zip(edgesIn) } /* Actually instantiate this node during [[LazyModuleImp]] evaluation. Mark that it's safe to use the Bundle wires, * instantiate monitors on all input ports if appropriate, and return all the dangles of this node. / protected[diplomacy] def instantiate(): Seq[Dangle] = { instantiated = true if (!circuitIdentity) { (iPorts.zip(in)).foreach { case ((_, _, p, _), (b, e)) => if (p(MonitorsEnabled)) inner.monitor(b, e) } } danglesOut ++ danglesIn } protected[diplomacy] def cloneDangles(): Seq[Dangle] = emptyDanglesOut ++ emptyDanglesIn /* Connects the outward part of a node with the inward part of this node. / protected[diplomacy] def bind( h: OutwardNode[DI, UI, BI], binding: NodeBinding )( implicit p: Parameters, sourceInfo: SourceInfo ): Unit = { val x = this // x := y val y = h sourceLine(sourceInfo, " at ", "") val i = x.iPushed val o = y.oPushed y.oPush( i, x, binding match { case BIND_ONCE => BIND_ONCE case BIND_FLEX => BIND_FLEX case BIND_STAR => BIND_QUERY case BIND_QUERY => BIND_STAR } ) x.iPush(o, y, binding) } / Metadata for printing the node graph. / def inputs: Seq[(OutwardNode[DI, UI, BI], RenderedEdge)] = (iPorts.zip(edgesIn)).map { case ((_, n, p, _), e) => val re = inner.render(e) (n, re.copy(flipped = re.flipped != p(RenderFlipped))) } /* Metadata for printing the node graph */ def outputs: Seq[(InwardNode[DO, UO, BO], RenderedEdge)] = oPorts.map { case (i, n, _, _) => (n, n.inputs(i)._2) } }	module IntSyncSyncCrossingSink_n1x2_9( // @[Crossing.scala:96:9] input auto_in_sync_0, // @[LazyModuleImp.scala:107:25] input auto_in_sync_1, // @[LazyModuleImp.scala:107:25] output auto_out_0, // @[LazyModuleImp.scala:107:25] output auto_out_1 // @[LazyModuleImp.scala:107:25] ); wire auto_in_sync_0_0 = auto_in_sync_0; // @[Crossing.scala:96:9] wire auto_in_sync_1_0 = auto_in_sync_1; // @[Crossing.scala:96:9] wire childClock = 1'h0; // @[LazyModuleImp.scala:155:31] wire childReset = 1'h0; // @[LazyModuleImp.scala:158:31] wire _childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25] wire nodeIn_sync_0 = auto_in_sync_0_0; // @[Crossing.scala:96:9] wire nodeIn_sync_1 = auto_in_sync_1_0; // @[Crossing.scala:96:9] wire nodeOut_0; // @[MixedNode.scala:542:17] wire nodeOut_1; // @[MixedNode.scala:542:17] wire auto_out_0_0; // @[Crossing.scala:96:9] wire auto_out_1_0; // @[Crossing.scala:96:9] assign nodeOut_0 = nodeIn_sync_0; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_1 = nodeIn_sync_1; // @[MixedNode.scala:542:17, :551:17] assign auto_out_0_0 = nodeOut_0; // @[Crossing.scala:96:9] assign auto_out_1_0 = nodeOut_1; // @[Crossing.scala:96:9] assign auto_out_0 = auto_out_0_0; // @[Crossing.scala:96:9] assign auto_out_1 = auto_out_1_0; // @[Crossing.scala:96:9] endmodule
Generate the Verilog code corresponding to the following Chisel files. File Monitor.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceLine import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import freechips.rocketchip.diplomacy.EnableMonitors import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode} import freechips.rocketchip.util.PlusArg case class TLMonitorArgs(edge: TLEdge) abstract class TLMonitorBase(args: TLMonitorArgs) extends Module { val io = IO(new Bundle { val in = Input(new TLBundle(args.edge.bundle)) }) def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit legalize(io.in, args.edge, reset) } object TLMonitor { def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = { if (enable) { EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) } } else { node } } } class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args) { require (args.edge.params(TLMonitorStrictMode) \|\| (! args.edge.params(TestplanTestType).formal)) val cover_prop_class = PropertyClass.Default //Like assert but can flip to being an assumption for formal verification def monAssert(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir, cond, message, PropertyClass.Default) } def assume(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir.flip, cond, message, PropertyClass.Default) } def extra = { args.edge.sourceInfo match { case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)" case _ => "" } } def visible(address: UInt, source: UInt, edge: TLEdge) = edge.client.clients.map { c => !c.sourceId.contains(source) \|\| c.visibility.map(_.contains(address)).reduce(_ \|\| _) }.reduce(_ && _) def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = { //switch this flag to turn on diplomacy in error messages def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n" monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra) // Reuse these subexpressions to save some firrtl lines val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility") //The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B //TODO: check for acquireT? when (bundle.opcode === TLMessages.AcquireBlock) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra) } when (bundle.opcode === TLMessages.AcquirePerm) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra) monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra) monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra) monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra) } } def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = { monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra) monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility") // Reuse these subexpressions to save some firrtl lines val address_ok = edge.manager.containsSafe(edge.address(bundle)) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source when (bundle.opcode === TLMessages.Probe) { assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra) assume (address_ok, "'B' channel Probe carries unmanaged address" + extra) assume (legal_source, "'B' channel Probe carries source that is not first source" + extra) assume (is_aligned, "'B' channel Probe address not aligned to size" + extra) assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra) assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra) assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra) monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra) monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra) monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra) monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra) } } def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = { monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val address_ok = edge.manager.containsSafe(edge.address(bundle)) monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility") when (bundle.opcode === TLMessages.ProbeAck) { monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra) } when (bundle.opcode === TLMessages.ProbeAckData) { monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.Release) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra) monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra) } when (bundle.opcode === TLMessages.ReleaseData) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.AccessAck) { monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra) } when (bundle.opcode === TLMessages.HintAck) { monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra) } } def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = { assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val sink_ok = bundle.sink < edge.manager.endSinkId.U val deny_put_ok = edge.manager.mayDenyPut.B val deny_get_ok = edge.manager.mayDenyGet.B when (bundle.opcode === TLMessages.ReleaseAck) { assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra) assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra) assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra) } when (bundle.opcode === TLMessages.Grant) { assume (source_ok, "'D' channel Grant carries invalid source ID" + extra) assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra) assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel Grant is denied" + extra) } when (bundle.opcode === TLMessages.GrantData) { assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra) assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra) assume (!bundle.denied \|\| bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra) assume (deny_get_ok \|\| !bundle.denied, "'D' channel GrantData is denied" + extra) } when (bundle.opcode === TLMessages.AccessAck) { assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel AccessAck is denied" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra) assume (!bundle.denied \|\| bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra) assume (deny_get_ok \|\| !bundle.denied, "'D' channel AccessAckData is denied" + extra) } when (bundle.opcode === TLMessages.HintAck) { assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel HintAck is denied" + extra) } } def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = { val sink_ok = bundle.sink < edge.manager.endSinkId.U monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra) } def legalizeFormat(bundle: TLBundle, edge: TLEdge) = { when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) } when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) } when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) } when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) } } else { monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra) monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra) monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra) } } def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = { val a_first = edge.first(a.bits, a.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (a.valid && !a_first) { monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra) monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra) monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra) monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra) monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra) } when (a.fire && a_first) { opcode := a.bits.opcode param := a.bits.param size := a.bits.size source := a.bits.source address := a.bits.address } } def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = { val b_first = edge.first(b.bits, b.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (b.valid && !b_first) { monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra) monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra) monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra) monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra) monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra) } when (b.fire && b_first) { opcode := b.bits.opcode param := b.bits.param size := b.bits.size source := b.bits.source address := b.bits.address } } def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = { // Symbolic variable val sym_source = Wire(UInt(edge.client.endSourceId.W)) // TODO: Connect sym_source to a fixed value for simulation and to a // free wire in formal sym_source := 0.U // Type casting Int to UInt val maxSourceId = Wire(UInt(edge.client.endSourceId.W)) maxSourceId := edge.client.endSourceId.U // Delayed verison of sym_source val sym_source_d = Reg(UInt(edge.client.endSourceId.W)) sym_source_d := sym_source // These will be constraints for FV setup Property( MonitorDirection.Monitor, (sym_source === sym_source_d), "sym_source should remain stable", PropertyClass.Default) Property( MonitorDirection.Monitor, (sym_source <= maxSourceId), "sym_source should take legal value", PropertyClass.Default) val my_resp_pend = RegInit(false.B) val my_opcode = Reg(UInt()) val my_size = Reg(UInt()) val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire) val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire) val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source) val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source) val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat) val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend) when (my_set_resp_pend) { my_resp_pend := true.B } .elsewhen (my_clr_resp_pend) { my_resp_pend := false.B } when (my_a_first_beat) { my_opcode := bundle.a.bits.opcode my_size := bundle.a.bits.size } val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size) val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode) val my_resp_opcode_legal = Wire(Bool()) when ((my_resp_opcode === TLMessages.Get) \|\| (my_resp_opcode === TLMessages.ArithmeticData) \|\| (my_resp_opcode === TLMessages.LogicalData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData) } .elsewhen ((my_resp_opcode === TLMessages.PutFullData) \|\| (my_resp_opcode === TLMessages.PutPartialData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck) } .otherwise { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck) } monAssert (IfThen(my_resp_pend, !my_a_first_beat), "Request message should not be sent with a source ID, for which a response message" + "is already pending (not received until current cycle) for a prior request message" + "with the same source ID" + extra) assume (IfThen(my_clr_resp_pend, (my_set_resp_pend \|\| my_resp_pend)), "Response message should be accepted with a source ID only if a request message with the" + "same source ID has been accepted or is being accepted in the current cycle" + extra) assume (IfThen(my_d_first_beat, (my_a_first_beat \|\| my_resp_pend)), "Response message should be sent with a source ID only if a request message with the" + "same source ID has been accepted or is being sent in the current cycle" + extra) assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)), "If d_valid is 1, then d_size should be same as a_size of the corresponding request" + "message" + extra) assume (IfThen(my_d_first_beat, my_resp_opcode_legal), "If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" + "request message" + extra) } def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = { val c_first = edge.first(c.bits, c.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (c.valid && !c_first) { monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra) monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra) monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra) monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra) monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra) } when (c.fire && c_first) { opcode := c.bits.opcode param := c.bits.param size := c.bits.size source := c.bits.source address := c.bits.address } } def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = { val d_first = edge.first(d.bits, d.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val sink = Reg(UInt()) val denied = Reg(Bool()) when (d.valid && !d_first) { assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra) assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra) assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra) assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra) assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra) assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra) } when (d.fire && d_first) { opcode := d.bits.opcode param := d.bits.param size := d.bits.size source := d.bits.source sink := d.bits.sink denied := d.bits.denied } } def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = { legalizeMultibeatA(bundle.a, edge) legalizeMultibeatD(bundle.d, edge) if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { legalizeMultibeatB(bundle.b, edge) legalizeMultibeatC(bundle.c, edge) } } //This is left in for almond which doesn't adhere to the tilelink protocol @deprecated("Use legalizeADSource instead if possible","") def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.client.endSourceId.W)) val a_first = edge.first(bundle.a.bits, bundle.a.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val a_set = WireInit(0.U(edge.client.endSourceId.W)) when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) assume((a_set \| inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra) } if (edge.manager.minLatency > 0) { assume(a_set =/= d_clr \|\| !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight \| a_set) & ~d_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") assert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = { val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size) val log_a_size_bus_size = log2Ceil(a_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error inflight.suggestName("inflight") val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) inflight_opcodes.suggestName("inflight_opcodes") val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) inflight_sizes.suggestName("inflight_sizes") val a_first = edge.first(bundle.a.bits, bundle.a.fire) a_first.suggestName("a_first") val d_first = edge.first(bundle.d.bits, bundle.d.fire) d_first.suggestName("d_first") val a_set = WireInit(0.U(edge.client.endSourceId.W)) val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) a_set.suggestName("a_set") a_set_wo_ready.suggestName("a_set_wo_ready") val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) a_opcodes_set.suggestName("a_opcodes_set") val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) a_sizes_set.suggestName("a_sizes_set") val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W)) a_opcode_lookup.suggestName("a_opcode_lookup") a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W)) a_size_lookup.suggestName("a_size_lookup") a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant)) val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant)) val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W)) a_opcodes_set_interm.suggestName("a_opcodes_set_interm") val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W)) a_sizes_set_interm.suggestName("a_sizes_set_interm") when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) { a_set_wo_ready := UIntToOH(bundle.a.bits.source) } when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) \| 1.U a_sizes_set_interm := (bundle.a.bits.size << 1.U) \| 1.U a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U) a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U) monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) d_opcodes_clr.suggestName("d_opcodes_clr") val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) \|\| same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) \|\| (bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra) assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) \|\| (bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra) assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) { assume((!bundle.d.ready) \|\| bundle.a.ready, "ready check") } if (edge.manager.minLatency > 0) { assume(a_set_wo_ready =/= d_clr_wo_ready \|\| !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight \| a_set) & ~d_clr inflight_opcodes := (inflight_opcodes \| a_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes \| a_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = { val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size) val log_c_size_bus_size = log2Ceil(c_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) inflight.suggestName("inflight") inflight_opcodes.suggestName("inflight_opcodes") inflight_sizes.suggestName("inflight_sizes") val c_first = edge.first(bundle.c.bits, bundle.c.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) c_first.suggestName("c_first") d_first.suggestName("d_first") val c_set = WireInit(0.U(edge.client.endSourceId.W)) val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) c_set.suggestName("c_set") c_set_wo_ready.suggestName("c_set_wo_ready") c_opcodes_set.suggestName("c_opcodes_set") c_sizes_set.suggestName("c_sizes_set") val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W)) val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W)) c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U c_opcode_lookup.suggestName("c_opcode_lookup") c_size_lookup.suggestName("c_size_lookup") val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W)) val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W)) c_opcodes_set_interm.suggestName("c_opcodes_set_interm") c_sizes_set_interm.suggestName("c_sizes_set_interm") when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) { c_set_wo_ready := UIntToOH(bundle.c.bits.source) } when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) { c_set := UIntToOH(bundle.c.bits.source) c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) \| 1.U c_sizes_set_interm := (bundle.c.bits.size << 1.U) \| 1.U c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U) c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U) monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra) } val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck \|\| bundle.c.bits.opcode === TLMessages.ProbeAckData val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") d_opcodes_clr.suggestName("d_opcodes_clr") d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) \|\| same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) { assume((!bundle.d.ready) \|\| bundle.c.ready, "ready check") } if (edge.manager.minLatency > 0) { when (c_set_wo_ready.orR) { assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra) } } inflight := (inflight \| c_set) & ~d_clr inflight_opcodes := (inflight_opcodes \| c_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes \| c_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.c.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.manager.endSinkId.W)) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val e_first = true.B val d_set = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) { d_set := UIntToOH(bundle.d.bits.sink) assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra) } val e_clr = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) { e_clr := UIntToOH(bundle.e.bits.sink) monAssert((d_set \| inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra) } // edge.client.minLatency applies to BC, not DE inflight := (inflight \| d_set) & ~e_clr } def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = { val sourceBits = log2Ceil(edge.client.endSourceId) val tooBig = 14 // >16kB worth of flight information gets to be too much if (sourceBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked") } else { if (args.edge.params(TestplanTestType).simulation) { if (args.edge.params(TLMonitorStrictMode)) { legalizeADSource(bundle, edge) legalizeCDSource(bundle, edge) } else { legalizeADSourceOld(bundle, edge) } } if (args.edge.params(TestplanTestType).formal) { legalizeADSourceFormal(bundle, edge) } } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { // legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize... val sinkBits = log2Ceil(edge.manager.endSinkId) if (sinkBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked") } else { legalizeDESink(bundle, edge) } } } def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = { legalizeFormat (bundle, edge) legalizeMultibeat (bundle, edge) legalizeUnique (bundle, edge) } } File Misc.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import scala.math._ class ParameterizedBundle(implicit p: Parameters) extends Bundle trait Clocked extends Bundle { val clock = Clock() val reset = Bool() } object DecoupledHelper { def apply(rvs: Bool) = new DecoupledHelper(rvs) } class DecoupledHelper(val rvs: Seq[Bool]) { def fire(exclude: Bool, includes: Bool) = { require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!") (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _) } def fire() = { rvs.reduce(_ && _) } } object MuxT { def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2)) def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3)) def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4)) } /** Creates a cascade of n MuxTs to search for a key value. / object MuxTLookup { def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } } object ValidMux { def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]): ValidIO[T] = { apply(v1 +: v2.toSeq) } def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = { val out = Wire(Valid(valids.head.bits.cloneType)) out.valid := valids.map(_.valid).reduce(_ \|\| _) out.bits := MuxCase(valids.head.bits, valids.map(v => (v.valid -> v.bits))) out } } object Str { def apply(s: String): UInt = { var i = BigInt(0) require(s.forall(validChar _)) for (c <- s) i = (i << 8) \| c i.U((s.length8).W) } def apply(x: Char): UInt = { require(validChar(x)) x.U(8.W) } def apply(x: UInt): UInt = apply(x, 10) def apply(x: UInt, radix: Int): UInt = { val rad = radix.U val w = x.getWidth require(w > 0) var q = x var s = digit(q % rad) for (i <- 1 until ceil(log(2)/log(radix)w).toInt) { q = q / rad s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s) } s } def apply(x: SInt): UInt = apply(x, 10) def apply(x: SInt, radix: Int): UInt = { val neg = x < 0.S val abs = x.abs.asUInt if (radix != 10) { Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix)) } else { val rad = radix.U val w = abs.getWidth require(w > 0) var q = abs var s = digit(q % rad) var needSign = neg for (i <- 1 until ceil(log(2)/log(radix)w).toInt) { q = q / rad val placeSpace = q === 0.U val space = Mux(needSign, Str('-'), Str(' ')) needSign = needSign && !placeSpace s = Cat(Mux(placeSpace, space, digit(q % rad)), s) } Cat(Mux(needSign, Str('-'), Str(' ')), s) } } private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0) private def validChar(x: Char) = x == (x & 0xFF) } object Split { def apply(x: UInt, n0: Int) = { val w = x.getWidth (x.extract(w-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n2: Int, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } } object Random { def apply(mod: Int, random: UInt): UInt = { if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0) else PriorityEncoder(partition(apply(1 << log2Up(mod8), random), mod)) } def apply(mod: Int): UInt = apply(mod, randomizer) def oneHot(mod: Int, random: UInt): UInt = { if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0)) else PriorityEncoderOH(partition(apply(1 << log2Up(mod8), random), mod)).asUInt } def oneHot(mod: Int): UInt = oneHot(mod, randomizer) private def randomizer = LFSR(16) private def partition(value: UInt, slices: Int) = Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U) } object Majority { def apply(in: Set[Bool]): Bool = { val n = (in.size >> 1) + 1 val clauses = in.subsets(n).map(_.reduce(_ && _)) clauses.reduce(_ \|\| _) } def apply(in: Seq[Bool]): Bool = apply(in.toSet) def apply(in: UInt): Bool = apply(in.asBools.toSet) } object PopCountAtLeast { private def two(x: UInt): (Bool, Bool) = x.getWidth match { case 1 => (x.asBool, false.B) case n => val half = x.getWidth / 2 val (leftOne, leftTwo) = two(x(half - 1, 0)) val (rightOne, rightTwo) = two(x(x.getWidth - 1, half)) (leftOne \|\| rightOne, leftTwo \|\| rightTwo \|\| (leftOne && rightOne)) } def apply(x: UInt, n: Int): Bool = n match { case 0 => true.B case 1 => x.orR case 2 => two(x)._2 case 3 => PopCount(x) >= n.U } } // This gets used everywhere, so make the smallest circuit possible ... // Given an address and size, create a mask of beatBytes size // eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111 // groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01 object MaskGen { def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = { require (groupBy >= 1 && beatBytes >= groupBy) require (isPow2(beatBytes) && isPow2(groupBy)) val lgBytes = log2Ceil(beatBytes) val sizeOH = UIntToOH(lgSize \| 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) \| (groupBy2 - 1).U def helper(i: Int): Seq[(Bool, Bool)] = { if (i == 0) { Seq((lgSize >= lgBytes.asUInt, true.B)) } else { val sub = helper(i-1) val size = sizeOH(lgBytes - i) val bit = addr_lo(lgBytes - i) val nbit = !bit Seq.tabulate (1 << i) { j => val (sub_acc, sub_eq) = sub(j/2) val eq = sub_eq && (if (j % 2 == 1) bit else nbit) val acc = sub_acc \|\| (size && eq) (acc, eq) } } } if (groupBy == beatBytes) 1.U else Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse) } } File PlusArg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.experimental._ import chisel3.util.HasBlackBoxResource @deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05") case class PlusArgInfo(default: BigInt, docstring: String) /** Case class for PlusArg information * * @tparam A scala type of the PlusArg value * @param default optional default value * @param docstring text to include in the help * @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT) / private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String) /* Typeclass for converting a type to a doctype string * @tparam A some type / trait Doctypeable[A] { /* Return the doctype string for some option / def toDoctype(a: Option[A]): String } /* Object containing implementations of the Doctypeable typeclass / object Doctypes { /* Converts an Int => "INT" / implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" } /* Converts a BigInt => "INT" / implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" } /* Converts a String => "STRING" / implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" } } class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map( "FORMAT" -> StringParam(format), "DEFAULT" -> IntParam(default), "WIDTH" -> IntParam(width) )) with HasBlackBoxResource { val io = IO(new Bundle { val out = Output(UInt(width.W)) }) addResource("/vsrc/plusarg_reader.v") } / This wrapper class has no outputs, making it clear it is a simulation-only construct / class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module { val io = IO(new Bundle { val count = Input(UInt(width.W)) }) val max = Module(new plusarg_reader(format, default, docstring, width)).io.out when (max > 0.U) { assert (io.count < max, s"Timeout exceeded: $docstring") } } import Doctypes._ object PlusArg { /* PlusArg("foo") will return 42.U if the simulation is run with +foo=42 * Do not use this as an initial register value. The value is set in an * initial block and thus accessing it from another initial is racey. * Add a docstring to document the arg, which can be dumped in an elaboration * pass. / def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out } /* PlusArg.timeout(name, default, docstring)(count) will use chisel.assert * to kill the simulation when count exceeds the specified integer argument. * Default 0 will never assert. / def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count } } object PlusArgArtefacts { private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty / Add a new PlusArg / @deprecated( "Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05" ) def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring) /* Add a new PlusArg * * @tparam A scala type of the PlusArg value * @param name name for the PlusArg * @param default optional default value * @param docstring text to include in the help / def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit = artefacts = artefacts ++ Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default))) / From plus args, generate help text / private def serializeHelp_cHeader(tab: String = ""): String = artefacts .map{ case(arg, info) => s"""\|$tab+$arg=${info.doctype}\\n\\ \|$tab${" "20}${info.docstring}\\n\\ \|""".stripMargin ++ info.default.map{ case default => s"$tab${" "22}(default=${default})\\n\\\n"}.getOrElse("") }.toSeq.mkString("\\n\\\n") ++ "\"" / From plus args, generate a char array of their names / private def serializeArray_cHeader(tab: String = ""): String = { val prettyTab = tab + " " 44 // Length of 'static const ...' s"${tab}static const char * verilog_plusargs [] = {\\\n" ++ artefacts .map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" } .mkString("")++ s"${prettyTab}0};" } /* Generate C code to be included in emulator.cc that helps with * argument parsing based on available Verilog PlusArgs / def serialize_cHeader(): String = s"""\|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\ \|${serializeHelp_cHeader(" "7)} \|${serializeArray_cHeader()} \|""".stripMargin } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /* Like Vec.apply(idx), but tolerates indices of mismatched width / def extract(idx: UInt): T = x((idx \| 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx \| 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def \| (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a \|\| b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_\|\|_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /* Any Data subtype that has a Bool member named valid. / type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /* converts from camel case to to underscores, also removing all spaces / def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /* converts spaces or underscores to hyphens, also lowering case / def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y \| (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y \|\| y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 \| 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /* Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation / def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Bundles.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import freechips.rocketchip.util._ import scala.collection.immutable.ListMap import chisel3.util.Decoupled import chisel3.util.DecoupledIO import chisel3.reflect.DataMirror abstract class TLBundleBase(val params: TLBundleParameters) extends Bundle // common combos in lazy policy: // Put + Acquire // Release + AccessAck object TLMessages { // A B C D E def PutFullData = 0.U // . . => AccessAck def PutPartialData = 1.U // . . => AccessAck def ArithmeticData = 2.U // . . => AccessAckData def LogicalData = 3.U // . . => AccessAckData def Get = 4.U // . . => AccessAckData def Hint = 5.U // . . => HintAck def AcquireBlock = 6.U // . => Grant[Data] def AcquirePerm = 7.U // . => Grant[Data] def Probe = 6.U // . => ProbeAck[Data] def AccessAck = 0.U // . . def AccessAckData = 1.U // . . def HintAck = 2.U // . . def ProbeAck = 4.U // . def ProbeAckData = 5.U // . def Release = 6.U // . => ReleaseAck def ReleaseData = 7.U // . => ReleaseAck def Grant = 4.U // . => GrantAck def GrantData = 5.U // . => GrantAck def ReleaseAck = 6.U // . def GrantAck = 0.U // . def isA(x: UInt) = x <= AcquirePerm def isB(x: UInt) = x <= Probe def isC(x: UInt) = x <= ReleaseData def isD(x: UInt) = x <= ReleaseAck def adResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, Grant, Grant) def bcResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, ProbeAck, ProbeAck) def a = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("AcquireBlock",TLPermissions.PermMsgGrow), ("AcquirePerm",TLPermissions.PermMsgGrow)) def b = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("Probe",TLPermissions.PermMsgCap)) def c = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("ProbeAck",TLPermissions.PermMsgReport), ("ProbeAckData",TLPermissions.PermMsgReport), ("Release",TLPermissions.PermMsgReport), ("ReleaseData",TLPermissions.PermMsgReport)) def d = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("Grant",TLPermissions.PermMsgCap), ("GrantData",TLPermissions.PermMsgCap), ("ReleaseAck",TLPermissions.PermMsgReserved)) } /* * The three primary TileLink permissions are: * (T)runk: the agent is (or is on inwards path to) the global point of serialization. * (B)ranch: the agent is on an outwards path to * (N)one: * These permissions are permuted by transfer operations in various ways. * Operations can cap permissions, request for them to be grown or shrunk, * or for a report on their current status. / object TLPermissions { val aWidth = 2 val bdWidth = 2 val cWidth = 3 // Cap types (Grant = new permissions, Probe = permisions <= target) def toT = 0.U(bdWidth.W) def toB = 1.U(bdWidth.W) def toN = 2.U(bdWidth.W) def isCap(x: UInt) = x <= toN // Grow types (Acquire = permissions >= target) def NtoB = 0.U(aWidth.W) def NtoT = 1.U(aWidth.W) def BtoT = 2.U(aWidth.W) def isGrow(x: UInt) = x <= BtoT // Shrink types (ProbeAck, Release) def TtoB = 0.U(cWidth.W) def TtoN = 1.U(cWidth.W) def BtoN = 2.U(cWidth.W) def isShrink(x: UInt) = x <= BtoN // Report types (ProbeAck, Release) def TtoT = 3.U(cWidth.W) def BtoB = 4.U(cWidth.W) def NtoN = 5.U(cWidth.W) def isReport(x: UInt) = x <= NtoN def PermMsgGrow:Seq[String] = Seq("Grow NtoB", "Grow NtoT", "Grow BtoT") def PermMsgCap:Seq[String] = Seq("Cap toT", "Cap toB", "Cap toN") def PermMsgReport:Seq[String] = Seq("Shrink TtoB", "Shrink TtoN", "Shrink BtoN", "Report TotT", "Report BtoB", "Report NtoN") def PermMsgReserved:Seq[String] = Seq("Reserved") } object TLAtomics { val width = 3 // Arithmetic types def MIN = 0.U(width.W) def MAX = 1.U(width.W) def MINU = 2.U(width.W) def MAXU = 3.U(width.W) def ADD = 4.U(width.W) def isArithmetic(x: UInt) = x <= ADD // Logical types def XOR = 0.U(width.W) def OR = 1.U(width.W) def AND = 2.U(width.W) def SWAP = 3.U(width.W) def isLogical(x: UInt) = x <= SWAP def ArithMsg:Seq[String] = Seq("MIN", "MAX", "MINU", "MAXU", "ADD") def LogicMsg:Seq[String] = Seq("XOR", "OR", "AND", "SWAP") } object TLHints { val width = 1 def PREFETCH_READ = 0.U(width.W) def PREFETCH_WRITE = 1.U(width.W) def isHints(x: UInt) = x <= PREFETCH_WRITE def HintsMsg:Seq[String] = Seq("PrefetchRead", "PrefetchWrite") } sealed trait TLChannel extends TLBundleBase { val channelName: String } sealed trait TLDataChannel extends TLChannel sealed trait TLAddrChannel extends TLDataChannel final class TLBundleA(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleA_${params.shortName}" val channelName = "'A' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(List(TLAtomics.width, TLPermissions.aWidth, TLHints.width).max.W) // amo_opcode \|\| grow perms \|\| hint val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleB(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleB_${params.shortName}" val channelName = "'B' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val address = UInt(params.addressBits.W) // from // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleC(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleC_${params.shortName}" val channelName = "'C' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.cWidth.W) // shrink or report perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleD(params: TLBundleParameters) extends TLBundleBase(params) with TLDataChannel { override def typeName = s"TLBundleD_${params.shortName}" val channelName = "'D' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val sink = UInt(params.sinkBits.W) // from val denied = Bool() // implies corrupt iff Data val user = BundleMap(params.responseFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleE(params: TLBundleParameters) extends TLBundleBase(params) with TLChannel { override def typeName = s"TLBundleE_${params.shortName}" val channelName = "'E' channel" val sink = UInt(params.sinkBits.W) // to } class TLBundle(val params: TLBundleParameters) extends Record { // Emulate a Bundle with elements abcde or ad depending on params.hasBCE private val optA = Some (Decoupled(new TLBundleA(params))) private val optB = params.hasBCE.option(Flipped(Decoupled(new TLBundleB(params)))) private val optC = params.hasBCE.option(Decoupled(new TLBundleC(params))) private val optD = Some (Flipped(Decoupled(new TLBundleD(params)))) private val optE = params.hasBCE.option(Decoupled(new TLBundleE(params))) def a: DecoupledIO[TLBundleA] = optA.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleA(params))))) def b: DecoupledIO[TLBundleB] = optB.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleB(params))))) def c: DecoupledIO[TLBundleC] = optC.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleC(params))))) def d: DecoupledIO[TLBundleD] = optD.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleD(params))))) def e: DecoupledIO[TLBundleE] = optE.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleE(params))))) val elements = if (params.hasBCE) ListMap("e" -> e, "d" -> d, "c" -> c, "b" -> b, "a" -> a) else ListMap("d" -> d, "a" -> a) def tieoff(): Unit = { DataMirror.specifiedDirectionOf(a.ready) match { case SpecifiedDirection.Input => a.ready := false.B c.ready := false.B e.ready := false.B b.valid := false.B d.valid := false.B case SpecifiedDirection.Output => a.valid := false.B c.valid := false.B e.valid := false.B b.ready := false.B d.ready := false.B case _ => } } } object TLBundle { def apply(params: TLBundleParameters) = new TLBundle(params) } class TLAsyncBundleBase(val params: TLAsyncBundleParameters) extends Bundle class TLAsyncBundle(params: TLAsyncBundleParameters) extends TLAsyncBundleBase(params) { val a = new AsyncBundle(new TLBundleA(params.base), params.async) val b = Flipped(new AsyncBundle(new TLBundleB(params.base), params.async)) val c = new AsyncBundle(new TLBundleC(params.base), params.async) val d = Flipped(new AsyncBundle(new TLBundleD(params.base), params.async)) val e = new AsyncBundle(new TLBundleE(params.base), params.async) } class TLRationalBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = RationalIO(new TLBundleA(params)) val b = Flipped(RationalIO(new TLBundleB(params))) val c = RationalIO(new TLBundleC(params)) val d = Flipped(RationalIO(new TLBundleD(params))) val e = RationalIO(new TLBundleE(params)) } class TLCreditedBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = CreditedIO(new TLBundleA(params)) val b = Flipped(CreditedIO(new TLBundleB(params))) val c = CreditedIO(new TLBundleC(params)) val d = Flipped(CreditedIO(new TLBundleD(params))) val e = CreditedIO(new TLBundleE(params)) } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.nodes._ import freechips.rocketchip.diplomacy.{ AddressDecoder, AddressSet, BufferParams, DirectedBuffers, IdMap, IdMapEntry, IdRange, RegionType, TransferSizes } import freechips.rocketchip.resources.{Resource, ResourceAddress, ResourcePermissions} import freechips.rocketchip.util.{ AsyncQueueParams, BundleField, BundleFieldBase, BundleKeyBase, CreditedDelay, groupByIntoSeq, RationalDirection, SimpleProduct } import scala.math.max //These transfer sizes describe requests issued from masters on the A channel that will be responded by slaves on the D channel case class TLMasterToSlaveTransferSizes( // Supports both Acquire+Release of the following two sizes: acquireT: TransferSizes = TransferSizes.none, acquireB: TransferSizes = TransferSizes.none, arithmetic: TransferSizes = TransferSizes.none, logical: TransferSizes = TransferSizes.none, get: TransferSizes = TransferSizes.none, putFull: TransferSizes = TransferSizes.none, putPartial: TransferSizes = TransferSizes.none, hint: TransferSizes = TransferSizes.none) extends TLCommonTransferSizes { def intersect(rhs: TLMasterToSlaveTransferSizes) = TLMasterToSlaveTransferSizes( acquireT = acquireT .intersect(rhs.acquireT), acquireB = acquireB .intersect(rhs.acquireB), arithmetic = arithmetic.intersect(rhs.arithmetic), logical = logical .intersect(rhs.logical), get = get .intersect(rhs.get), putFull = putFull .intersect(rhs.putFull), putPartial = putPartial.intersect(rhs.putPartial), hint = hint .intersect(rhs.hint)) def mincover(rhs: TLMasterToSlaveTransferSizes) = TLMasterToSlaveTransferSizes( acquireT = acquireT .mincover(rhs.acquireT), acquireB = acquireB .mincover(rhs.acquireB), arithmetic = arithmetic.mincover(rhs.arithmetic), logical = logical .mincover(rhs.logical), get = get .mincover(rhs.get), putFull = putFull .mincover(rhs.putFull), putPartial = putPartial.mincover(rhs.putPartial), hint = hint .mincover(rhs.hint)) // Reduce rendering to a simple yes/no per field override def toString = { def str(x: TransferSizes, flag: String) = if (x.none) "" else flag def flags = Vector( str(acquireT, "T"), str(acquireB, "B"), str(arithmetic, "A"), str(logical, "L"), str(get, "G"), str(putFull, "F"), str(putPartial, "P"), str(hint, "H")) flags.mkString } // Prints out the actual information in a user readable way def infoString = { s"""acquireT = ${acquireT} \|acquireB = ${acquireB} \|arithmetic = ${arithmetic} \|logical = ${logical} \|get = ${get} \|putFull = ${putFull} \|putPartial = ${putPartial} \|hint = ${hint} \| \|""".stripMargin } } object TLMasterToSlaveTransferSizes { def unknownEmits = TLMasterToSlaveTransferSizes( acquireT = TransferSizes(1, 4096), acquireB = TransferSizes(1, 4096), arithmetic = TransferSizes(1, 4096), logical = TransferSizes(1, 4096), get = TransferSizes(1, 4096), putFull = TransferSizes(1, 4096), putPartial = TransferSizes(1, 4096), hint = TransferSizes(1, 4096)) def unknownSupports = TLMasterToSlaveTransferSizes() } //These transfer sizes describe requests issued from slaves on the B channel that will be responded by masters on the C channel case class TLSlaveToMasterTransferSizes( probe: TransferSizes = TransferSizes.none, arithmetic: TransferSizes = TransferSizes.none, logical: TransferSizes = TransferSizes.none, get: TransferSizes = TransferSizes.none, putFull: TransferSizes = TransferSizes.none, putPartial: TransferSizes = TransferSizes.none, hint: TransferSizes = TransferSizes.none ) extends TLCommonTransferSizes { def intersect(rhs: TLSlaveToMasterTransferSizes) = TLSlaveToMasterTransferSizes( probe = probe .intersect(rhs.probe), arithmetic = arithmetic.intersect(rhs.arithmetic), logical = logical .intersect(rhs.logical), get = get .intersect(rhs.get), putFull = putFull .intersect(rhs.putFull), putPartial = putPartial.intersect(rhs.putPartial), hint = hint .intersect(rhs.hint) ) def mincover(rhs: TLSlaveToMasterTransferSizes) = TLSlaveToMasterTransferSizes( probe = probe .mincover(rhs.probe), arithmetic = arithmetic.mincover(rhs.arithmetic), logical = logical .mincover(rhs.logical), get = get .mincover(rhs.get), putFull = putFull .mincover(rhs.putFull), putPartial = putPartial.mincover(rhs.putPartial), hint = hint .mincover(rhs.hint) ) // Reduce rendering to a simple yes/no per field override def toString = { def str(x: TransferSizes, flag: String) = if (x.none) "" else flag def flags = Vector( str(probe, "P"), str(arithmetic, "A"), str(logical, "L"), str(get, "G"), str(putFull, "F"), str(putPartial, "P"), str(hint, "H")) flags.mkString } // Prints out the actual information in a user readable way def infoString = { s"""probe = ${probe} \|arithmetic = ${arithmetic} \|logical = ${logical} \|get = ${get} \|putFull = ${putFull} \|putPartial = ${putPartial} \|hint = ${hint} \| \|""".stripMargin } } object TLSlaveToMasterTransferSizes { def unknownEmits = TLSlaveToMasterTransferSizes( arithmetic = TransferSizes(1, 4096), logical = TransferSizes(1, 4096), get = TransferSizes(1, 4096), putFull = TransferSizes(1, 4096), putPartial = TransferSizes(1, 4096), hint = TransferSizes(1, 4096), probe = TransferSizes(1, 4096)) def unknownSupports = TLSlaveToMasterTransferSizes() } trait TLCommonTransferSizes { def arithmetic: TransferSizes def logical: TransferSizes def get: TransferSizes def putFull: TransferSizes def putPartial: TransferSizes def hint: TransferSizes } class TLSlaveParameters private( val nodePath: Seq[BaseNode], val resources: Seq[Resource], setName: Option[String], val address: Seq[AddressSet], val regionType: RegionType.T, val executable: Boolean, val fifoId: Option[Int], val supports: TLMasterToSlaveTransferSizes, val emits: TLSlaveToMasterTransferSizes, // By default, slaves are forbidden from issuing 'denied' responses (it prevents Fragmentation) val alwaysGrantsT: Boolean, // typically only true for CacheCork'd read-write devices; dual: neverReleaseData // If fifoId=Some, all accesses sent to the same fifoId are executed and ACK'd in FIFO order // Note: you can only rely on this FIFO behaviour if your TLMasterParameters include requestFifo val mayDenyGet: Boolean, // applies to: AccessAckData, GrantData val mayDenyPut: Boolean) // applies to: AccessAck, Grant, HintAck // ReleaseAck may NEVER be denied extends SimpleProduct { def sortedAddress = address.sorted override def canEqual(that: Any): Boolean = that.isInstanceOf[TLSlaveParameters] override def productPrefix = "TLSlaveParameters" // We intentionally omit nodePath for equality testing / formatting def productArity: Int = 11 def productElement(n: Int): Any = n match { case 0 => name case 1 => address case 2 => resources case 3 => regionType case 4 => executable case 5 => fifoId case 6 => supports case 7 => emits case 8 => alwaysGrantsT case 9 => mayDenyGet case 10 => mayDenyPut case _ => throw new IndexOutOfBoundsException(n.toString) } def supportsAcquireT: TransferSizes = supports.acquireT def supportsAcquireB: TransferSizes = supports.acquireB def supportsArithmetic: TransferSizes = supports.arithmetic def supportsLogical: TransferSizes = supports.logical def supportsGet: TransferSizes = supports.get def supportsPutFull: TransferSizes = supports.putFull def supportsPutPartial: TransferSizes = supports.putPartial def supportsHint: TransferSizes = supports.hint require (!address.isEmpty, "Address cannot be empty") address.foreach { a => require (a.finite, "Address must be finite") } address.combinations(2).foreach { case Seq(x,y) => require (!x.overlaps(y), s"$x and $y overlap.") } require (supportsPutFull.contains(supportsPutPartial), s"PutFull($supportsPutFull) < PutPartial($supportsPutPartial)") require (supportsPutFull.contains(supportsArithmetic), s"PutFull($supportsPutFull) < Arithmetic($supportsArithmetic)") require (supportsPutFull.contains(supportsLogical), s"PutFull($supportsPutFull) < Logical($supportsLogical)") require (supportsGet.contains(supportsArithmetic), s"Get($supportsGet) < Arithmetic($supportsArithmetic)") require (supportsGet.contains(supportsLogical), s"Get($supportsGet) < Logical($supportsLogical)") require (supportsAcquireB.contains(supportsAcquireT), s"AcquireB($supportsAcquireB) < AcquireT($supportsAcquireT)") require (!alwaysGrantsT \|\| supportsAcquireT, s"Must supportAcquireT if promising to always grantT") // Make sure that the regionType agrees with the capabilities require (!supportsAcquireB \|\| regionType >= RegionType.UNCACHED) // acquire -> uncached, tracked, cached require (regionType <= RegionType.UNCACHED \|\| supportsAcquireB) // tracked, cached -> acquire require (regionType != RegionType.UNCACHED \|\| supportsGet) // uncached -> supportsGet val name = setName.orElse(nodePath.lastOption.map(_.lazyModule.name)).getOrElse("disconnected") val maxTransfer = List( // Largest supported transfer of all types supportsAcquireT.max, supportsAcquireB.max, supportsArithmetic.max, supportsLogical.max, supportsGet.max, supportsPutFull.max, supportsPutPartial.max).max val maxAddress = address.map(_.max).max val minAlignment = address.map(_.alignment).min // The device had better not support a transfer larger than its alignment require (minAlignment >= maxTransfer, s"Bad $address: minAlignment ($minAlignment) must be >= maxTransfer ($maxTransfer)") def toResource: ResourceAddress = { ResourceAddress(address, ResourcePermissions( r = supportsAcquireB \|\| supportsGet, w = supportsAcquireT \|\| supportsPutFull, x = executable, c = supportsAcquireB, a = supportsArithmetic && supportsLogical)) } def findTreeViolation() = nodePath.find { case _: MixedAdapterNode[_, _, _, _, _, _, _, _] => false case _: SinkNode[_, _, _, _, _] => false case node => node.inputs.size != 1 } def isTree = findTreeViolation() == None def infoString = { s"""Slave Name = ${name} \|Slave Address = ${address} \|supports = ${supports.infoString} \| \|""".stripMargin } def v1copy( address: Seq[AddressSet] = address, resources: Seq[Resource] = resources, regionType: RegionType.T = regionType, executable: Boolean = executable, nodePath: Seq[BaseNode] = nodePath, supportsAcquireT: TransferSizes = supports.acquireT, supportsAcquireB: TransferSizes = supports.acquireB, supportsArithmetic: TransferSizes = supports.arithmetic, supportsLogical: TransferSizes = supports.logical, supportsGet: TransferSizes = supports.get, supportsPutFull: TransferSizes = supports.putFull, supportsPutPartial: TransferSizes = supports.putPartial, supportsHint: TransferSizes = supports.hint, mayDenyGet: Boolean = mayDenyGet, mayDenyPut: Boolean = mayDenyPut, alwaysGrantsT: Boolean = alwaysGrantsT, fifoId: Option[Int] = fifoId) = { new TLSlaveParameters( setName = setName, address = address, resources = resources, regionType = regionType, executable = executable, nodePath = nodePath, supports = TLMasterToSlaveTransferSizes( acquireT = supportsAcquireT, acquireB = supportsAcquireB, arithmetic = supportsArithmetic, logical = supportsLogical, get = supportsGet, putFull = supportsPutFull, putPartial = supportsPutPartial, hint = supportsHint), emits = emits, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut, alwaysGrantsT = alwaysGrantsT, fifoId = fifoId) } def v2copy( nodePath: Seq[BaseNode] = nodePath, resources: Seq[Resource] = resources, name: Option[String] = setName, address: Seq[AddressSet] = address, regionType: RegionType.T = regionType, executable: Boolean = executable, fifoId: Option[Int] = fifoId, supports: TLMasterToSlaveTransferSizes = supports, emits: TLSlaveToMasterTransferSizes = emits, alwaysGrantsT: Boolean = alwaysGrantsT, mayDenyGet: Boolean = mayDenyGet, mayDenyPut: Boolean = mayDenyPut) = { new TLSlaveParameters( nodePath = nodePath, resources = resources, setName = name, address = address, regionType = regionType, executable = executable, fifoId = fifoId, supports = supports, emits = emits, alwaysGrantsT = alwaysGrantsT, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut) } @deprecated("Use v1copy instead of copy","") def copy( address: Seq[AddressSet] = address, resources: Seq[Resource] = resources, regionType: RegionType.T = regionType, executable: Boolean = executable, nodePath: Seq[BaseNode] = nodePath, supportsAcquireT: TransferSizes = supports.acquireT, supportsAcquireB: TransferSizes = supports.acquireB, supportsArithmetic: TransferSizes = supports.arithmetic, supportsLogical: TransferSizes = supports.logical, supportsGet: TransferSizes = supports.get, supportsPutFull: TransferSizes = supports.putFull, supportsPutPartial: TransferSizes = supports.putPartial, supportsHint: TransferSizes = supports.hint, mayDenyGet: Boolean = mayDenyGet, mayDenyPut: Boolean = mayDenyPut, alwaysGrantsT: Boolean = alwaysGrantsT, fifoId: Option[Int] = fifoId) = { v1copy( address = address, resources = resources, regionType = regionType, executable = executable, nodePath = nodePath, supportsAcquireT = supportsAcquireT, supportsAcquireB = supportsAcquireB, supportsArithmetic = supportsArithmetic, supportsLogical = supportsLogical, supportsGet = supportsGet, supportsPutFull = supportsPutFull, supportsPutPartial = supportsPutPartial, supportsHint = supportsHint, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut, alwaysGrantsT = alwaysGrantsT, fifoId = fifoId) } } object TLSlaveParameters { def v1( address: Seq[AddressSet], resources: Seq[Resource] = Seq(), regionType: RegionType.T = RegionType.GET_EFFECTS, executable: Boolean = false, nodePath: Seq[BaseNode] = Seq(), supportsAcquireT: TransferSizes = TransferSizes.none, supportsAcquireB: TransferSizes = TransferSizes.none, supportsArithmetic: TransferSizes = TransferSizes.none, supportsLogical: TransferSizes = TransferSizes.none, supportsGet: TransferSizes = TransferSizes.none, supportsPutFull: TransferSizes = TransferSizes.none, supportsPutPartial: TransferSizes = TransferSizes.none, supportsHint: TransferSizes = TransferSizes.none, mayDenyGet: Boolean = false, mayDenyPut: Boolean = false, alwaysGrantsT: Boolean = false, fifoId: Option[Int] = None) = { new TLSlaveParameters( setName = None, address = address, resources = resources, regionType = regionType, executable = executable, nodePath = nodePath, supports = TLMasterToSlaveTransferSizes( acquireT = supportsAcquireT, acquireB = supportsAcquireB, arithmetic = supportsArithmetic, logical = supportsLogical, get = supportsGet, putFull = supportsPutFull, putPartial = supportsPutPartial, hint = supportsHint), emits = TLSlaveToMasterTransferSizes.unknownEmits, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut, alwaysGrantsT = alwaysGrantsT, fifoId = fifoId) } def v2( address: Seq[AddressSet], nodePath: Seq[BaseNode] = Seq(), resources: Seq[Resource] = Seq(), name: Option[String] = None, regionType: RegionType.T = RegionType.GET_EFFECTS, executable: Boolean = false, fifoId: Option[Int] = None, supports: TLMasterToSlaveTransferSizes = TLMasterToSlaveTransferSizes.unknownSupports, emits: TLSlaveToMasterTransferSizes = TLSlaveToMasterTransferSizes.unknownEmits, alwaysGrantsT: Boolean = false, mayDenyGet: Boolean = false, mayDenyPut: Boolean = false) = { new TLSlaveParameters( nodePath = nodePath, resources = resources, setName = name, address = address, regionType = regionType, executable = executable, fifoId = fifoId, supports = supports, emits = emits, alwaysGrantsT = alwaysGrantsT, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut) } } object TLManagerParameters { @deprecated("Use TLSlaveParameters.v1 instead of TLManagerParameters","") def apply( address: Seq[AddressSet], resources: Seq[Resource] = Seq(), regionType: RegionType.T = RegionType.GET_EFFECTS, executable: Boolean = false, nodePath: Seq[BaseNode] = Seq(), supportsAcquireT: TransferSizes = TransferSizes.none, supportsAcquireB: TransferSizes = TransferSizes.none, supportsArithmetic: TransferSizes = TransferSizes.none, supportsLogical: TransferSizes = TransferSizes.none, supportsGet: TransferSizes = TransferSizes.none, supportsPutFull: TransferSizes = TransferSizes.none, supportsPutPartial: TransferSizes = TransferSizes.none, supportsHint: TransferSizes = TransferSizes.none, mayDenyGet: Boolean = false, mayDenyPut: Boolean = false, alwaysGrantsT: Boolean = false, fifoId: Option[Int] = None) = TLSlaveParameters.v1( address, resources, regionType, executable, nodePath, supportsAcquireT, supportsAcquireB, supportsArithmetic, supportsLogical, supportsGet, supportsPutFull, supportsPutPartial, supportsHint, mayDenyGet, mayDenyPut, alwaysGrantsT, fifoId, ) } case class TLChannelBeatBytes(a: Option[Int], b: Option[Int], c: Option[Int], d: Option[Int]) { def members = Seq(a, b, c, d) members.collect { case Some(beatBytes) => require (isPow2(beatBytes), "Data channel width must be a power of 2") } } object TLChannelBeatBytes{ def apply(beatBytes: Int): TLChannelBeatBytes = TLChannelBeatBytes( Some(beatBytes), Some(beatBytes), Some(beatBytes), Some(beatBytes)) def apply(): TLChannelBeatBytes = TLChannelBeatBytes( None, None, None, None) } class TLSlavePortParameters private( val slaves: Seq[TLSlaveParameters], val channelBytes: TLChannelBeatBytes, val endSinkId: Int, val minLatency: Int, val responseFields: Seq[BundleFieldBase], val requestKeys: Seq[BundleKeyBase]) extends SimpleProduct { def sortedSlaves = slaves.sortBy(_.sortedAddress.head) override def canEqual(that: Any): Boolean = that.isInstanceOf[TLSlavePortParameters] override def productPrefix = "TLSlavePortParameters" def productArity: Int = 6 def productElement(n: Int): Any = n match { case 0 => slaves case 1 => channelBytes case 2 => endSinkId case 3 => minLatency case 4 => responseFields case 5 => requestKeys case _ => throw new IndexOutOfBoundsException(n.toString) } require (!slaves.isEmpty, "Slave ports must have slaves") require (endSinkId >= 0, "Sink ids cannot be negative") require (minLatency >= 0, "Minimum required latency cannot be negative") // Using this API implies you cannot handle mixed-width busses def beatBytes = { channelBytes.members.foreach { width => require (width.isDefined && width == channelBytes.a) } channelBytes.a.get } // TODO this should be deprecated def managers = slaves def requireFifo(policy: TLFIFOFixer.Policy = TLFIFOFixer.allFIFO) = { val relevant = slaves.filter(m => policy(m)) relevant.foreach { m => require(m.fifoId == relevant.head.fifoId, s"${m.name} had fifoId ${m.fifoId}, which was not homogeneous (${slaves.map(s => (s.name, s.fifoId))}) ") } } // Bounds on required sizes def maxAddress = slaves.map(_.maxAddress).max def maxTransfer = slaves.map(_.maxTransfer).max def mayDenyGet = slaves.exists(_.mayDenyGet) def mayDenyPut = slaves.exists(_.mayDenyPut) // Diplomatically determined operation sizes emitted by all outward Slaves // as opposed to emits* which generate circuitry to check which specific addresses val allEmitClaims = slaves.map(_.emits).reduce( _ intersect _) // Operation Emitted by at least one outward Slaves // as opposed to emits* which generate circuitry to check which specific addresses val anyEmitClaims = slaves.map(_.emits).reduce(_ mincover _) // Diplomatically determined operation sizes supported by all outward Slaves // as opposed to supports* which generate circuitry to check which specific addresses val allSupportClaims = slaves.map(_.supports).reduce( _ intersect _) val allSupportAcquireT = allSupportClaims.acquireT val allSupportAcquireB = allSupportClaims.acquireB val allSupportArithmetic = allSupportClaims.arithmetic val allSupportLogical = allSupportClaims.logical val allSupportGet = allSupportClaims.get val allSupportPutFull = allSupportClaims.putFull val allSupportPutPartial = allSupportClaims.putPartial val allSupportHint = allSupportClaims.hint // Operation supported by at least one outward Slaves // as opposed to supports* which generate circuitry to check which specific addresses val anySupportClaims = slaves.map(_.supports).reduce(_ mincover _) val anySupportAcquireT = !anySupportClaims.acquireT.none val anySupportAcquireB = !anySupportClaims.acquireB.none val anySupportArithmetic = !anySupportClaims.arithmetic.none val anySupportLogical = !anySupportClaims.logical.none val anySupportGet = !anySupportClaims.get.none val anySupportPutFull = !anySupportClaims.putFull.none val anySupportPutPartial = !anySupportClaims.putPartial.none val anySupportHint = !anySupportClaims.hint.none // Supporting Acquire means being routable for GrantAck require ((endSinkId == 0) == !anySupportAcquireB) // These return Option[TLSlaveParameters] for your convenience def find(address: BigInt) = slaves.find(_.address.exists(_.contains(address))) // The safe version will check the entire address def findSafe(address: UInt) = VecInit(sortedSlaves.map(_.address.map(_.contains(address)).reduce(_ \|\| _))) // The fast version assumes the address is valid (you probably want fastProperty instead of this function) def findFast(address: UInt) = { val routingMask = AddressDecoder(slaves.map(_.address)) VecInit(sortedSlaves.map(_.address.map(_.widen(~routingMask)).distinct.map(_.contains(address)).reduce(_ \|\| _))) } // Compute the simplest AddressSets that decide a key def fastPropertyGroup[K](p: TLSlaveParameters => K): Seq[(K, Seq[AddressSet])] = { val groups = groupByIntoSeq(sortedSlaves.map(m => (p(m), m.address)))( _._1).map { case (k, vs) => k -> vs.flatMap(_._2) } val reductionMask = AddressDecoder(groups.map(_._2)) groups.map { case (k, seq) => k -> AddressSet.unify(seq.map(_.widen(~reductionMask)).distinct) } } // Select a property def fastProperty[K, D <: Data](address: UInt, p: TLSlaveParameters => K, d: K => D): D = Mux1H(fastPropertyGroup(p).map { case (v, a) => (a.map(_.contains(address)).reduce(_\|\|_), d(v)) }) // Note: returns the actual fifoId + 1 or 0 if None def findFifoIdFast(address: UInt) = fastProperty(address, _.fifoId.map(_+1).getOrElse(0), (i:Int) => i.U) def hasFifoIdFast(address: UInt) = fastProperty(address, _.fifoId.isDefined, (b:Boolean) => b.B) // Does this Port manage this ID/address? def containsSafe(address: UInt) = findSafe(address).reduce(_ \|\| _) private def addressHelper( // setting safe to false indicates that all addresses are expected to be legal, which might reduce circuit complexity safe: Boolean, // member filters out the sizes being checked based on the opcode being emitted or supported member: TLSlaveParameters => TransferSizes, address: UInt, lgSize: UInt, // range provides a limit on the sizes that are expected to be evaluated, which might reduce circuit complexity range: Option[TransferSizes]): Bool = { // trim reduces circuit complexity by intersecting checked sizes with the range argument def trim(x: TransferSizes) = range.map(_.intersect(x)).getOrElse(x) // groupBy returns an unordered map, convert back to Seq and sort the result for determinism // groupByIntoSeq is turning slaves into trimmed membership sizes // We are grouping all the slaves by their transfer size where // if they support the trimmed size then // member is the type of transfer that you are looking for (What you are trying to filter on) // When you consider membership, you are trimming the sizes to only the ones that you care about // you are filtering the slaves based on both whether they support a particular opcode and the size // Grouping the slaves based on the actual transfer size range they support // intersecting the range and checking their membership // FOR SUPPORTCASES instead of returning the list of slaves, // you are returning a map from transfer size to the set of // address sets that are supported for that transfer size // find all the slaves that support a certain type of operation and then group their addresses by the supported size // for every size there could be multiple address ranges // safety is a trade off between checking between all possible addresses vs only the addresses // that are known to have supported sizes // the trade off is 'checking all addresses is a more expensive circuit but will always give you // the right answer even if you give it an illegal address' // the not safe version is a cheaper circuit but if you give it an illegal address then it might produce the wrong answer // fast presumes address legality // This groupByIntoSeq deterministically groups all address sets for which a given `member` transfer size applies. // In the resulting Map of cases, the keys are transfer sizes and the values are all address sets which emit or support that size. val supportCases = groupByIntoSeq(slaves)(m => trim(member(m))).map { case (k: TransferSizes, vs: Seq[TLSlaveParameters]) => k -> vs.flatMap(_.address) } // safe produces a circuit that compares against all possible addresses, // whereas fast presumes that the address is legal but uses an efficient address decoder val mask = if (safe) ~BigInt(0) else AddressDecoder(supportCases.map(_._2)) // Simplified creates the most concise possible representation of each cases' address sets based on the mask. val simplified = supportCases.map { case (k, seq) => k -> AddressSet.unify(seq.map(_.widen(~mask)).distinct) } simplified.map { case (s, a) => // s is a size, you are checking for this size either the size of the operation is in s // We return an or-reduction of all the cases, checking whether any contains both the dynamic size and dynamic address on the wire. ((Some(s) == range).B \|\| s.containsLg(lgSize)) && a.map(_.contains(address)).reduce(_\|\|_) }.foldLeft(false.B)(_\|\|_) } def supportsAcquireTSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.acquireT, address, lgSize, range) def supportsAcquireBSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.acquireB, address, lgSize, range) def supportsArithmeticSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.arithmetic, address, lgSize, range) def supportsLogicalSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.logical, address, lgSize, range) def supportsGetSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.get, address, lgSize, range) def supportsPutFullSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.putFull, address, lgSize, range) def supportsPutPartialSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.putPartial, address, lgSize, range) def supportsHintSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.hint, address, lgSize, range) def supportsAcquireTFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.acquireT, address, lgSize, range) def supportsAcquireBFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.acquireB, address, lgSize, range) def supportsArithmeticFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.arithmetic, address, lgSize, range) def supportsLogicalFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.logical, address, lgSize, range) def supportsGetFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.get, address, lgSize, range) def supportsPutFullFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.putFull, address, lgSize, range) def supportsPutPartialFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.putPartial, address, lgSize, range) def supportsHintFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.hint, address, lgSize, range) def emitsProbeSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.probe, address, lgSize, range) def emitsArithmeticSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.arithmetic, address, lgSize, range) def emitsLogicalSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.logical, address, lgSize, range) def emitsGetSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.get, address, lgSize, range) def emitsPutFullSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.putFull, address, lgSize, range) def emitsPutPartialSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.putPartial, address, lgSize, range) def emitsHintSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.hint, address, lgSize, range) def findTreeViolation() = slaves.flatMap(_.findTreeViolation()).headOption def isTree = !slaves.exists(!_.isTree) def infoString = "Slave Port Beatbytes = " + beatBytes + "\n" + "Slave Port MinLatency = " + minLatency + "\n\n" + slaves.map(_.infoString).mkString def v1copy( managers: Seq[TLSlaveParameters] = slaves, beatBytes: Int = -1, endSinkId: Int = endSinkId, minLatency: Int = minLatency, responseFields: Seq[BundleFieldBase] = responseFields, requestKeys: Seq[BundleKeyBase] = requestKeys) = { new TLSlavePortParameters( slaves = managers, channelBytes = if (beatBytes != -1) TLChannelBeatBytes(beatBytes) else channelBytes, endSinkId = endSinkId, minLatency = minLatency, responseFields = responseFields, requestKeys = requestKeys) } def v2copy( slaves: Seq[TLSlaveParameters] = slaves, channelBytes: TLChannelBeatBytes = channelBytes, endSinkId: Int = endSinkId, minLatency: Int = minLatency, responseFields: Seq[BundleFieldBase] = responseFields, requestKeys: Seq[BundleKeyBase] = requestKeys) = { new TLSlavePortParameters( slaves = slaves, channelBytes = channelBytes, endSinkId = endSinkId, minLatency = minLatency, responseFields = responseFields, requestKeys = requestKeys) } @deprecated("Use v1copy instead of copy","") def copy( managers: Seq[TLSlaveParameters] = slaves, beatBytes: Int = -1, endSinkId: Int = endSinkId, minLatency: Int = minLatency, responseFields: Seq[BundleFieldBase] = responseFields, requestKeys: Seq[BundleKeyBase] = requestKeys) = { v1copy( managers, beatBytes, endSinkId, minLatency, responseFields, requestKeys) } } object TLSlavePortParameters { def v1( managers: Seq[TLSlaveParameters], beatBytes: Int, endSinkId: Int = 0, minLatency: Int = 0, responseFields: Seq[BundleFieldBase] = Nil, requestKeys: Seq[BundleKeyBase] = Nil) = { new TLSlavePortParameters( slaves = managers, channelBytes = TLChannelBeatBytes(beatBytes), endSinkId = endSinkId, minLatency = minLatency, responseFields = responseFields, requestKeys = requestKeys) } } object TLManagerPortParameters { @deprecated("Use TLSlavePortParameters.v1 instead of TLManagerPortParameters","") def apply( managers: Seq[TLSlaveParameters], beatBytes: Int, endSinkId: Int = 0, minLatency: Int = 0, responseFields: Seq[BundleFieldBase] = Nil, requestKeys: Seq[BundleKeyBase] = Nil) = { TLSlavePortParameters.v1( managers, beatBytes, endSinkId, minLatency, responseFields, requestKeys) } } class TLMasterParameters private( val nodePath: Seq[BaseNode], val resources: Seq[Resource], val name: String, val visibility: Seq[AddressSet], val unusedRegionTypes: Set[RegionType.T], val executesOnly: Boolean, val requestFifo: Boolean, // only a request, not a requirement. applies to A, not C. val supports: TLSlaveToMasterTransferSizes, val emits: TLMasterToSlaveTransferSizes, val neverReleasesData: Boolean, val sourceId: IdRange) extends SimpleProduct { override def canEqual(that: Any): Boolean = that.isInstanceOf[TLMasterParameters] override def productPrefix = "TLMasterParameters" // We intentionally omit nodePath for equality testing / formatting def productArity: Int = 10 def productElement(n: Int): Any = n match { case 0 => name case 1 => sourceId case 2 => resources case 3 => visibility case 4 => unusedRegionTypes case 5 => executesOnly case 6 => requestFifo case 7 => supports case 8 => emits case 9 => neverReleasesData case _ => throw new IndexOutOfBoundsException(n.toString) } require (!sourceId.isEmpty) require (!visibility.isEmpty) require (supports.putFull.contains(supports.putPartial)) // We only support these operations if we support Probe (ie: we're a cache) require (supports.probe.contains(supports.arithmetic)) require (supports.probe.contains(supports.logical)) require (supports.probe.contains(supports.get)) require (supports.probe.contains(supports.putFull)) require (supports.probe.contains(supports.putPartial)) require (supports.probe.contains(supports.hint)) visibility.combinations(2).foreach { case Seq(x,y) => require (!x.overlaps(y), s"$x and $y overlap.") } val maxTransfer = List( supports.probe.max, supports.arithmetic.max, supports.logical.max, supports.get.max, supports.putFull.max, supports.putPartial.max).max def infoString = { s"""Master Name = ${name} \|visibility = ${visibility} \|emits = ${emits.infoString} \|sourceId = ${sourceId} \| \|""".stripMargin } def v1copy( name: String = name, sourceId: IdRange = sourceId, nodePath: Seq[BaseNode] = nodePath, requestFifo: Boolean = requestFifo, visibility: Seq[AddressSet] = visibility, supportsProbe: TransferSizes = supports.probe, supportsArithmetic: TransferSizes = supports.arithmetic, supportsLogical: TransferSizes = supports.logical, supportsGet: TransferSizes = supports.get, supportsPutFull: TransferSizes = supports.putFull, supportsPutPartial: TransferSizes = supports.putPartial, supportsHint: TransferSizes = supports.hint) = { new TLMasterParameters( nodePath = nodePath, resources = this.resources, name = name, visibility = visibility, unusedRegionTypes = this.unusedRegionTypes, executesOnly = this.executesOnly, requestFifo = requestFifo, supports = TLSlaveToMasterTransferSizes( probe = supportsProbe, arithmetic = supportsArithmetic, logical = supportsLogical, get = supportsGet, putFull = supportsPutFull, putPartial = supportsPutPartial, hint = supportsHint), emits = this.emits, neverReleasesData = this.neverReleasesData, sourceId = sourceId) } def v2copy( nodePath: Seq[BaseNode] = nodePath, resources: Seq[Resource] = resources, name: String = name, visibility: Seq[AddressSet] = visibility, unusedRegionTypes: Set[RegionType.T] = unusedRegionTypes, executesOnly: Boolean = executesOnly, requestFifo: Boolean = requestFifo, supports: TLSlaveToMasterTransferSizes = supports, emits: TLMasterToSlaveTransferSizes = emits, neverReleasesData: Boolean = neverReleasesData, sourceId: IdRange = sourceId) = { new TLMasterParameters( nodePath = nodePath, resources = resources, name = name, visibility = visibility, unusedRegionTypes = unusedRegionTypes, executesOnly = executesOnly, requestFifo = requestFifo, supports = supports, emits = emits, neverReleasesData = neverReleasesData, sourceId = sourceId) } @deprecated("Use v1copy instead of copy","") def copy( name: String = name, sourceId: IdRange = sourceId, nodePath: Seq[BaseNode] = nodePath, requestFifo: Boolean = requestFifo, visibility: Seq[AddressSet] = visibility, supportsProbe: TransferSizes = supports.probe, supportsArithmetic: TransferSizes = supports.arithmetic, supportsLogical: TransferSizes = supports.logical, supportsGet: TransferSizes = supports.get, supportsPutFull: TransferSizes = supports.putFull, supportsPutPartial: TransferSizes = supports.putPartial, supportsHint: TransferSizes = supports.hint) = { v1copy( name = name, sourceId = sourceId, nodePath = nodePath, requestFifo = requestFifo, visibility = visibility, supportsProbe = supportsProbe, supportsArithmetic = supportsArithmetic, supportsLogical = supportsLogical, supportsGet = supportsGet, supportsPutFull = supportsPutFull, supportsPutPartial = supportsPutPartial, supportsHint = supportsHint) } } object TLMasterParameters { def v1( name: String, sourceId: IdRange = IdRange(0,1), nodePath: Seq[BaseNode] = Seq(), requestFifo: Boolean = false, visibility: Seq[AddressSet] = Seq(AddressSet(0, ~0)), supportsProbe: TransferSizes = TransferSizes.none, supportsArithmetic: TransferSizes = TransferSizes.none, supportsLogical: TransferSizes = TransferSizes.none, supportsGet: TransferSizes = TransferSizes.none, supportsPutFull: TransferSizes = TransferSizes.none, supportsPutPartial: TransferSizes = TransferSizes.none, supportsHint: TransferSizes = TransferSizes.none) = { new TLMasterParameters( nodePath = nodePath, resources = Nil, name = name, visibility = visibility, unusedRegionTypes = Set(), executesOnly = false, requestFifo = requestFifo, supports = TLSlaveToMasterTransferSizes( probe = supportsProbe, arithmetic = supportsArithmetic, logical = supportsLogical, get = supportsGet, putFull = supportsPutFull, putPartial = supportsPutPartial, hint = supportsHint), emits = TLMasterToSlaveTransferSizes.unknownEmits, neverReleasesData = false, sourceId = sourceId) } def v2( nodePath: Seq[BaseNode] = Seq(), resources: Seq[Resource] = Nil, name: String, visibility: Seq[AddressSet] = Seq(AddressSet(0, ~0)), unusedRegionTypes: Set[RegionType.T] = Set(), executesOnly: Boolean = false, requestFifo: Boolean = false, supports: TLSlaveToMasterTransferSizes = TLSlaveToMasterTransferSizes.unknownSupports, emits: TLMasterToSlaveTransferSizes = TLMasterToSlaveTransferSizes.unknownEmits, neverReleasesData: Boolean = false, sourceId: IdRange = IdRange(0,1)) = { new TLMasterParameters( nodePath = nodePath, resources = resources, name = name, visibility = visibility, unusedRegionTypes = unusedRegionTypes, executesOnly = executesOnly, requestFifo = requestFifo, supports = supports, emits = emits, neverReleasesData = neverReleasesData, sourceId = sourceId) } } object TLClientParameters { @deprecated("Use TLMasterParameters.v1 instead of TLClientParameters","") def apply( name: String, sourceId: IdRange = IdRange(0,1), nodePath: Seq[BaseNode] = Seq(), requestFifo: Boolean = false, visibility: Seq[AddressSet] = Seq(AddressSet.everything), supportsProbe: TransferSizes = TransferSizes.none, supportsArithmetic: TransferSizes = TransferSizes.none, supportsLogical: TransferSizes = TransferSizes.none, supportsGet: TransferSizes = TransferSizes.none, supportsPutFull: TransferSizes = TransferSizes.none, supportsPutPartial: TransferSizes = TransferSizes.none, supportsHint: TransferSizes = TransferSizes.none) = { TLMasterParameters.v1( name = name, sourceId = sourceId, nodePath = nodePath, requestFifo = requestFifo, visibility = visibility, supportsProbe = supportsProbe, supportsArithmetic = supportsArithmetic, supportsLogical = supportsLogical, supportsGet = supportsGet, supportsPutFull = supportsPutFull, supportsPutPartial = supportsPutPartial, supportsHint = supportsHint) } } class TLMasterPortParameters private( val masters: Seq[TLMasterParameters], val channelBytes: TLChannelBeatBytes, val minLatency: Int, val echoFields: Seq[BundleFieldBase], val requestFields: Seq[BundleFieldBase], val responseKeys: Seq[BundleKeyBase]) extends SimpleProduct { override def canEqual(that: Any): Boolean = that.isInstanceOf[TLMasterPortParameters] override def productPrefix = "TLMasterPortParameters" def productArity: Int = 6 def productElement(n: Int): Any = n match { case 0 => masters case 1 => channelBytes case 2 => minLatency case 3 => echoFields case 4 => requestFields case 5 => responseKeys case _ => throw new IndexOutOfBoundsException(n.toString) } require (!masters.isEmpty) require (minLatency >= 0) def clients = masters // Require disjoint ranges for Ids IdRange.overlaps(masters.map(_.sourceId)).foreach { case (x, y) => require (!x.overlaps(y), s"TLClientParameters.sourceId ${x} overlaps ${y}") } // Bounds on required sizes def endSourceId = masters.map(_.sourceId.end).max def maxTransfer = masters.map(_.maxTransfer).max // The unused sources < endSourceId def unusedSources: Seq[Int] = { val usedSources = masters.map(_.sourceId).sortBy(_.start) ((Seq(0) ++ usedSources.map(_.end)) zip usedSources.map(_.start)) flatMap { case (end, start) => end until start } } // Diplomatically determined operation sizes emitted by all inward Masters // as opposed to emits* which generate circuitry to check which specific addresses val allEmitClaims = masters.map(_.emits).reduce( _ intersect _) // Diplomatically determined operation sizes Emitted by at least one inward Masters // as opposed to emits* which generate circuitry to check which specific addresses val anyEmitClaims = masters.map(_.emits).reduce(_ mincover _) // Diplomatically determined operation sizes supported by all inward Masters // as opposed to supports* which generate circuitry to check which specific addresses val allSupportProbe = masters.map(_.supports.probe) .reduce(_ intersect _) val allSupportArithmetic = masters.map(_.supports.arithmetic).reduce(_ intersect _) val allSupportLogical = masters.map(_.supports.logical) .reduce(_ intersect _) val allSupportGet = masters.map(_.supports.get) .reduce(_ intersect _) val allSupportPutFull = masters.map(_.supports.putFull) .reduce(_ intersect _) val allSupportPutPartial = masters.map(_.supports.putPartial).reduce(_ intersect _) val allSupportHint = masters.map(_.supports.hint) .reduce(_ intersect _) // Diplomatically determined operation sizes supported by at least one master // as opposed to supports* which generate circuitry to check which specific addresses val anySupportProbe = masters.map(!_.supports.probe.none) .reduce(_ \|\| _) val anySupportArithmetic = masters.map(!_.supports.arithmetic.none).reduce(_ \|\| _) val anySupportLogical = masters.map(!_.supports.logical.none) .reduce(_ \|\| _) val anySupportGet = masters.map(!_.supports.get.none) .reduce(_ \|\| _) val anySupportPutFull = masters.map(!_.supports.putFull.none) .reduce(_ \|\| _) val anySupportPutPartial = masters.map(!_.supports.putPartial.none).reduce(_ \|\| _) val anySupportHint = masters.map(!_.supports.hint.none) .reduce(_ \|\| _) // These return Option[TLMasterParameters] for your convenience def find(id: Int) = masters.find(_.sourceId.contains(id)) // Synthesizable lookup methods def find(id: UInt) = VecInit(masters.map(_.sourceId.contains(id))) def contains(id: UInt) = find(id).reduce(_ \|\| _) def requestFifo(id: UInt) = Mux1H(find(id), masters.map(c => c.requestFifo.B)) // Available during RTL runtime, checks to see if (id, size) is supported by the master's (client's) diplomatic parameters private def sourceIdHelper(member: TLMasterParameters => TransferSizes)(id: UInt, lgSize: UInt) = { val allSame = masters.map(member(_) == member(masters(0))).reduce(_ && _) // this if statement is a coarse generalization of the groupBy in the sourceIdHelper2 version; // the case where there is only one group. if (allSame) member(masters(0)).containsLg(lgSize) else { // Find the master associated with ID and returns whether that particular master is able to receive transaction of lgSize Mux1H(find(id), masters.map(member(_).containsLg(lgSize))) } } // Check for support of a given operation at a specific id val supportsProbe = sourceIdHelper(_.supports.probe) _ val supportsArithmetic = sourceIdHelper(_.supports.arithmetic) _ val supportsLogical = sourceIdHelper(_.supports.logical) _ val supportsGet = sourceIdHelper(_.supports.get) _ val supportsPutFull = sourceIdHelper(_.supports.putFull) _ val supportsPutPartial = sourceIdHelper(_.supports.putPartial) _ val supportsHint = sourceIdHelper(_.supports.hint) _ // TODO: Merge sourceIdHelper2 with sourceIdHelper private def sourceIdHelper2( member: TLMasterParameters => TransferSizes, sourceId: UInt, lgSize: UInt): Bool = { // Because sourceIds are uniquely owned by each master, we use them to group the // cases that have to be checked. val emitCases = groupByIntoSeq(masters)(m => member(m)).map { case (k, vs) => k -> vs.map(_.sourceId) } emitCases.map { case (s, a) => (s.containsLg(lgSize)) && a.map(_.contains(sourceId)).reduce(_\|\|_) }.foldLeft(false.B)(_\|\|_) } // Check for emit of a given operation at a specific id def emitsAcquireT (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.acquireT, sourceId, lgSize) def emitsAcquireB (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.acquireB, sourceId, lgSize) def emitsArithmetic(sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.arithmetic, sourceId, lgSize) def emitsLogical (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.logical, sourceId, lgSize) def emitsGet (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.get, sourceId, lgSize) def emitsPutFull (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.putFull, sourceId, lgSize) def emitsPutPartial(sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.putPartial, sourceId, lgSize) def emitsHint (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.hint, sourceId, lgSize) def infoString = masters.map(_.infoString).mkString def v1copy( clients: Seq[TLMasterParameters] = masters, minLatency: Int = minLatency, echoFields: Seq[BundleFieldBase] = echoFields, requestFields: Seq[BundleFieldBase] = requestFields, responseKeys: Seq[BundleKeyBase] = responseKeys) = { new TLMasterPortParameters( masters = clients, channelBytes = channelBytes, minLatency = minLatency, echoFields = echoFields, requestFields = requestFields, responseKeys = responseKeys) } def v2copy( masters: Seq[TLMasterParameters] = masters, channelBytes: TLChannelBeatBytes = channelBytes, minLatency: Int = minLatency, echoFields: Seq[BundleFieldBase] = echoFields, requestFields: Seq[BundleFieldBase] = requestFields, responseKeys: Seq[BundleKeyBase] = responseKeys) = { new TLMasterPortParameters( masters = masters, channelBytes = channelBytes, minLatency = minLatency, echoFields = echoFields, requestFields = requestFields, responseKeys = responseKeys) } @deprecated("Use v1copy instead of copy","") def copy( clients: Seq[TLMasterParameters] = masters, minLatency: Int = minLatency, echoFields: Seq[BundleFieldBase] = echoFields, requestFields: Seq[BundleFieldBase] = requestFields, responseKeys: Seq[BundleKeyBase] = responseKeys) = { v1copy( clients, minLatency, echoFields, requestFields, responseKeys) } } object TLClientPortParameters { @deprecated("Use TLMasterPortParameters.v1 instead of TLClientPortParameters","") def apply( clients: Seq[TLMasterParameters], minLatency: Int = 0, echoFields: Seq[BundleFieldBase] = Nil, requestFields: Seq[BundleFieldBase] = Nil, responseKeys: Seq[BundleKeyBase] = Nil) = { TLMasterPortParameters.v1( clients, minLatency, echoFields, requestFields, responseKeys) } } object TLMasterPortParameters { def v1( clients: Seq[TLMasterParameters], minLatency: Int = 0, echoFields: Seq[BundleFieldBase] = Nil, requestFields: Seq[BundleFieldBase] = Nil, responseKeys: Seq[BundleKeyBase] = Nil) = { new TLMasterPortParameters( masters = clients, channelBytes = TLChannelBeatBytes(), minLatency = minLatency, echoFields = echoFields, requestFields = requestFields, responseKeys = responseKeys) } def v2( masters: Seq[TLMasterParameters], channelBytes: TLChannelBeatBytes = TLChannelBeatBytes(), minLatency: Int = 0, echoFields: Seq[BundleFieldBase] = Nil, requestFields: Seq[BundleFieldBase] = Nil, responseKeys: Seq[BundleKeyBase] = Nil) = { new TLMasterPortParameters( masters = masters, channelBytes = channelBytes, minLatency = minLatency, echoFields = echoFields, requestFields = requestFields, responseKeys = responseKeys) } } case class TLBundleParameters( addressBits: Int, dataBits: Int, sourceBits: Int, sinkBits: Int, sizeBits: Int, echoFields: Seq[BundleFieldBase], requestFields: Seq[BundleFieldBase], responseFields: Seq[BundleFieldBase], hasBCE: Boolean) { // Chisel has issues with 0-width wires require (addressBits >= 1) require (dataBits >= 8) require (sourceBits >= 1) require (sinkBits >= 1) require (sizeBits >= 1) require (isPow2(dataBits)) echoFields.foreach { f => require (f.key.isControl, s"${f} is not a legal echo field") } val addrLoBits = log2Up(dataBits/8) // Used to uniquify bus IP names def shortName = s"a${addressBits}d${dataBits}s${sourceBits}k${sinkBits}z${sizeBits}" + (if (hasBCE) "c" else "u") def union(x: TLBundleParameters) = TLBundleParameters( max(addressBits, x.addressBits), max(dataBits, x.dataBits), max(sourceBits, x.sourceBits), max(sinkBits, x.sinkBits), max(sizeBits, x.sizeBits), echoFields = BundleField.union(echoFields ++ x.echoFields), requestFields = BundleField.union(requestFields ++ x.requestFields), responseFields = BundleField.union(responseFields ++ x.responseFields), hasBCE \|\| x.hasBCE) } object TLBundleParameters { val emptyBundleParams = TLBundleParameters( addressBits = 1, dataBits = 8, sourceBits = 1, sinkBits = 1, sizeBits = 1, echoFields = Nil, requestFields = Nil, responseFields = Nil, hasBCE = false) def union(x: Seq[TLBundleParameters]) = x.foldLeft(emptyBundleParams)((x,y) => x.union(y)) def apply(master: TLMasterPortParameters, slave: TLSlavePortParameters) = new TLBundleParameters( addressBits = log2Up(slave.maxAddress + 1), dataBits = slave.beatBytes * 8, sourceBits = log2Up(master.endSourceId), sinkBits = log2Up(slave.endSinkId), sizeBits = log2Up(log2Ceil(max(master.maxTransfer, slave.maxTransfer))+1), echoFields = master.echoFields, requestFields = BundleField.accept(master.requestFields, slave.requestKeys), responseFields = BundleField.accept(slave.responseFields, master.responseKeys), hasBCE = master.anySupportProbe && slave.anySupportAcquireB) } case class TLEdgeParameters( master: TLMasterPortParameters, slave: TLSlavePortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge { // legacy names: def manager = slave def client = master val maxTransfer = max(master.maxTransfer, slave.maxTransfer) val maxLgSize = log2Ceil(maxTransfer) // Sanity check the link... require (maxTransfer >= slave.beatBytes, s"Link's max transfer (${maxTransfer}) < ${slave.slaves.map(_.name)}'s beatBytes (${slave.beatBytes})") def diplomaticClaimsMasterToSlave = master.anyEmitClaims.intersect(slave.anySupportClaims) val bundle = TLBundleParameters(master, slave) def formatEdge = master.infoString + "\n" + slave.infoString } case class TLCreditedDelay( a: CreditedDelay, b: CreditedDelay, c: CreditedDelay, d: CreditedDelay, e: CreditedDelay) { def + (that: TLCreditedDelay): TLCreditedDelay = TLCreditedDelay( a = a + that.a, b = b + that.b, c = c + that.c, d = d + that.d, e = e + that.e) override def toString = s"(${a}, ${b}, ${c}, ${d}, ${e})" } object TLCreditedDelay { def apply(delay: CreditedDelay): TLCreditedDelay = apply(delay, delay.flip, delay, delay.flip, delay) } case class TLCreditedManagerPortParameters(delay: TLCreditedDelay, base: TLSlavePortParameters) {def infoString = base.infoString} case class TLCreditedClientPortParameters(delay: TLCreditedDelay, base: TLMasterPortParameters) {def infoString = base.infoString} case class TLCreditedEdgeParameters(client: TLCreditedClientPortParameters, manager: TLCreditedManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge { val delay = client.delay + manager.delay val bundle = TLBundleParameters(client.base, manager.base) def formatEdge = client.infoString + "\n" + manager.infoString } case class TLAsyncManagerPortParameters(async: AsyncQueueParams, base: TLSlavePortParameters) {def infoString = base.infoString} case class TLAsyncClientPortParameters(base: TLMasterPortParameters) {def infoString = base.infoString} case class TLAsyncBundleParameters(async: AsyncQueueParams, base: TLBundleParameters) case class TLAsyncEdgeParameters(client: TLAsyncClientPortParameters, manager: TLAsyncManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge { val bundle = TLAsyncBundleParameters(manager.async, TLBundleParameters(client.base, manager.base)) def formatEdge = client.infoString + "\n" + manager.infoString } case class TLRationalManagerPortParameters(direction: RationalDirection, base: TLSlavePortParameters) {def infoString = base.infoString} case class TLRationalClientPortParameters(base: TLMasterPortParameters) {def infoString = base.infoString} case class TLRationalEdgeParameters(client: TLRationalClientPortParameters, manager: TLRationalManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge { val bundle = TLBundleParameters(client.base, manager.base) def formatEdge = client.infoString + "\n" + manager.infoString } // To be unified, devices must agree on all of these terms case class ManagerUnificationKey( resources: Seq[Resource], regionType: RegionType.T, executable: Boolean, supportsAcquireT: TransferSizes, supportsAcquireB: TransferSizes, supportsArithmetic: TransferSizes, supportsLogical: TransferSizes, supportsGet: TransferSizes, supportsPutFull: TransferSizes, supportsPutPartial: TransferSizes, supportsHint: TransferSizes) object ManagerUnificationKey { def apply(x: TLSlaveParameters): ManagerUnificationKey = ManagerUnificationKey( resources = x.resources, regionType = x.regionType, executable = x.executable, supportsAcquireT = x.supportsAcquireT, supportsAcquireB = x.supportsAcquireB, supportsArithmetic = x.supportsArithmetic, supportsLogical = x.supportsLogical, supportsGet = x.supportsGet, supportsPutFull = x.supportsPutFull, supportsPutPartial = x.supportsPutPartial, supportsHint = x.supportsHint) } object ManagerUnification { def apply(slaves: Seq[TLSlaveParameters]): List[TLSlaveParameters] = { slaves.groupBy(ManagerUnificationKey.apply).values.map { seq => val agree = seq.forall(_.fifoId == seq.head.fifoId) seq(0).v1copy( address = AddressSet.unify(seq.flatMap(_.address)), fifoId = if (agree) seq(0).fifoId else None) }.toList } } case class TLBufferParams( a: BufferParams = BufferParams.none, b: BufferParams = BufferParams.none, c: BufferParams = BufferParams.none, d: BufferParams = BufferParams.none, e: BufferParams = BufferParams.none ) extends DirectedBuffers[TLBufferParams] { def copyIn(x: BufferParams) = this.copy(b = x, d = x) def copyOut(x: BufferParams) = this.copy(a = x, c = x, e = x) def copyInOut(x: BufferParams) = this.copyIn(x).copyOut(x) } /** Pretty printing of TL source id maps / class TLSourceIdMap(tl: TLMasterPortParameters) extends IdMap[TLSourceIdMapEntry] { private val tlDigits = String.valueOf(tl.endSourceId-1).length() protected val fmt = s"\t[%${tlDigits}d, %${tlDigits}d) %s%s%s" private val sorted = tl.masters.sortBy(_.sourceId) val mapping: Seq[TLSourceIdMapEntry] = sorted.map { case c => TLSourceIdMapEntry(c.sourceId, c.name, c.supports.probe, c.requestFifo) } } case class TLSourceIdMapEntry(tlId: IdRange, name: String, isCache: Boolean, requestFifo: Boolean) extends IdMapEntry { val from = tlId val to = tlId val maxTransactionsInFlight = Some(tlId.size) } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportPutFull \|\| manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB \|\| manager.anySupportGet \|\| manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportPutFull \|\| client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe \|\| client.anySupportGet \|\| client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet \|\| client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull \|\| client.anySupportPutPartial \|\| client.anySupportHint \|\| client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet \|\| manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull \|\| manager.anySupportPutPartial \|\| manager.anySupportHint \|\| manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) \|\| !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.ProbeAckData \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode \| small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U \|\| beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }	module TLMonitor_14( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input [7:0] io_in_d_bits_data, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [3:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [31:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7] wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7] wire [7:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_a_bits_source = 1'h0; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_source = 1'h0; // @[Monitor.scala:36:7] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire c_set = 1'h0; // @[Monitor.scala:738:34] wire c_set_wo_ready = 1'h0; // @[Monitor.scala:739:34] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire io_in_a_bits_mask = 1'h1; // @[Monitor.scala:36:7] wire _source_ok_T = 1'h1; // @[Parameters.scala:46:9] wire _source_ok_WIRE_0 = 1'h1; // @[Parameters.scala:1138:31] wire mask_sizeOH = 1'h1; // @[Misc.scala:202:81] wire _source_ok_T_1 = 1'h1; // @[Parameters.scala:46:9] wire _source_ok_WIRE_1_0 = 1'h1; // @[Parameters.scala:1138:31] wire sink_ok = 1'h1; // @[Monitor.scala:309:31] wire _same_cycle_resp_T_2 = 1'h1; // @[Monitor.scala:684:113] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire _same_cycle_resp_T_8 = 1'h1; // @[Monitor.scala:795:113] wire [3:0] _a_opcode_lookup_T = 4'h0; // @[Monitor.scala:637:69] wire [3:0] _a_size_lookup_T = 4'h0; // @[Monitor.scala:641:65] wire [3:0] _a_opcodes_set_T = 4'h0; // @[Monitor.scala:659:79] wire [3:0] _a_sizes_set_T = 4'h0; // @[Monitor.scala:660:77] wire [3:0] _d_opcodes_clr_T_4 = 4'h0; // @[Monitor.scala:680:101] wire [3:0] _d_sizes_clr_T_4 = 4'h0; // @[Monitor.scala:681:99] wire [3:0] _c_first_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] c_opcodes_set = 4'h0; // @[Monitor.scala:740:34] wire [3:0] _c_opcode_lookup_T = 4'h0; // @[Monitor.scala:749:69] wire [3:0] _c_size_lookup_T = 4'h0; // @[Monitor.scala:750:67] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] _c_set_wo_ready_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_wo_ready_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_sizes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_T = 4'h0; // @[Monitor.scala:767:79] wire [3:0] _c_sizes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_sizes_set_T = 4'h0; // @[Monitor.scala:768:77] wire [3:0] _c_probe_ack_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _d_opcodes_clr_T_10 = 4'h0; // @[Monitor.scala:790:101] wire [3:0] _d_sizes_clr_T_10 = 4'h0; // @[Monitor.scala:791:99] wire [3:0] _same_cycle_resp_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_4_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_5_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [30:0] _d_sizes_clr_T_5 = 31'hFF; // @[Monitor.scala:681:74] wire [30:0] _d_sizes_clr_T_11 = 31'hFF; // @[Monitor.scala:791:74] wire [30:0] _d_opcodes_clr_T_5 = 31'hF; // @[Monitor.scala:680:76] wire [30:0] _d_opcodes_clr_T_11 = 31'hF; // @[Monitor.scala:790:76] wire [1:0] _a_set_wo_ready_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _a_set_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _d_clr_wo_ready_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _d_clr_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _c_set_wo_ready_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _c_set_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _d_clr_wo_ready_T_1 = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _d_clr_T_1 = 2'h1; // @[OneHot.scala:58:35] wire [11:0] _c_first_beats1_decode_T_2 = 12'h0; // @[package.scala:243:46] wire [11:0] c_first_beats1_decode = 12'h0; // @[Edges.scala:220:59] wire [11:0] c_first_beats1 = 12'h0; // @[Edges.scala:221:14] wire [11:0] _c_first_count_T = 12'h0; // @[Edges.scala:234:27] wire [11:0] c_first_count = 12'h0; // @[Edges.scala:234:25] wire [11:0] _c_first_counter_T = 12'h0; // @[Edges.scala:236:21] wire [11:0] _c_first_beats1_decode_T_1 = 12'hFFF; // @[package.scala:243:76] wire [11:0] c_first_counter1 = 12'hFFF; // @[Edges.scala:230:28] wire [12:0] _c_first_counter1_T = 13'h1FFF; // @[Edges.scala:230:28] wire [2:0] io_in_a_bits_param = 3'h0; // @[Monitor.scala:36:7] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [7:0] _c_first_WIRE_bits_data = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_first_WIRE_1_bits_data = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_first_WIRE_2_bits_data = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_first_WIRE_3_bits_data = 8'h0; // @[Bundles.scala:265:61] wire [7:0] c_sizes_set = 8'h0; // @[Monitor.scala:741:34] wire [7:0] _c_set_wo_ready_WIRE_bits_data = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_set_wo_ready_WIRE_1_bits_data = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_set_WIRE_bits_data = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_set_WIRE_1_bits_data = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_opcodes_set_interm_WIRE_bits_data = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_opcodes_set_interm_WIRE_1_bits_data = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_sizes_set_interm_WIRE_bits_data = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_sizes_set_interm_WIRE_1_bits_data = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_opcodes_set_WIRE_bits_data = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_opcodes_set_WIRE_1_bits_data = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_sizes_set_WIRE_bits_data = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_sizes_set_WIRE_1_bits_data = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_probe_ack_WIRE_bits_data = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_probe_ack_WIRE_1_bits_data = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_probe_ack_WIRE_2_bits_data = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_probe_ack_WIRE_3_bits_data = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _same_cycle_resp_WIRE_bits_data = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _same_cycle_resp_WIRE_1_bits_data = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _same_cycle_resp_WIRE_2_bits_data = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _same_cycle_resp_WIRE_3_bits_data = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _same_cycle_resp_WIRE_4_bits_data = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _same_cycle_resp_WIRE_5_bits_data = 8'h0; // @[Bundles.scala:265:61] wire [31:0] _c_first_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_first_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_wo_ready_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_wo_ready_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_4_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_5_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [15:0] _a_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _c_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hFF; // @[Monitor.scala:724:57] wire [16:0] _a_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _c_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hFF; // @[Monitor.scala:724:57] wire [15:0] _a_size_lookup_T_3 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _c_size_lookup_T_3 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [19:0] _c_sizes_set_T_1 = 20'h0; // @[Monitor.scala:768:52] wire [18:0] _c_opcodes_set_T_1 = 19'h0; // @[Monitor.scala:767:54] wire [4:0] _c_sizes_set_interm_T_1 = 5'h1; // @[Monitor.scala:766:59] wire [4:0] c_sizes_set_interm = 5'h0; // @[Monitor.scala:755:40] wire [4:0] _c_sizes_set_interm_T = 5'h0; // @[Monitor.scala:766:51] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [26:0] _c_first_beats1_decode_T = 27'hFFF; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [3:0] _a_size_lookup_T_2 = 4'h8; // @[Monitor.scala:641:117] wire [3:0] _d_sizes_clr_T = 4'h8; // @[Monitor.scala:681:48] wire [3:0] _c_size_lookup_T_2 = 4'h8; // @[Monitor.scala:750:119] wire [3:0] _d_sizes_clr_T_6 = 4'h8; // @[Monitor.scala:791:48] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire [26:0] _GEN = 27'hFFF << io_in_a_bits_size_0; // @[package.scala:243:71] wire [26:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [11:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [31:0] _is_aligned_T = {20'h0, io_in_a_bits_address_0[11:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 32'h0; // @[Edges.scala:21:{16,24}] wire _T_1222 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_1222; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_1222; // @[Decoupled.scala:51:35] wire [11:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [11:0] a_first_beats1_decode = _a_first_beats1_decode_T_2; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [11:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 12'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [11:0] a_first_counter; // @[Edges.scala:229:27] wire [12:0] _a_first_counter1_T = {1'h0, a_first_counter} - 13'h1; // @[Edges.scala:229:27, :230:28] wire [11:0] a_first_counter1 = _a_first_counter1_T[11:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 12'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 12'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 12'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T \| _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [11:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [11:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [11:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [3:0] size; // @[Monitor.scala:389:22] reg [31:0] address; // @[Monitor.scala:391:22] wire _T_1295 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_1295; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_1295; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_1295; // @[Decoupled.scala:51:35] wire [26:0] _GEN_0 = 27'hFFF << io_in_d_bits_size_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [11:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [11:0] d_first_beats1_decode = _d_first_beats1_decode_T_2; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [11:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 12'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [11:0] d_first_counter; // @[Edges.scala:229:27] wire [12:0] _d_first_counter1_T = {1'h0, d_first_counter} - 13'h1; // @[Edges.scala:229:27, :230:28] wire [11:0] d_first_counter1 = _d_first_counter1_T[11:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 12'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 12'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 12'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T \| _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [11:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [11:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [11:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [3:0] size_1; // @[Monitor.scala:540:22] reg source_1; // @[Monitor.scala:541:22] reg [2:0] sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] reg [1:0] inflight; // @[Monitor.scala:614:27] reg [3:0] inflight_opcodes; // @[Monitor.scala:616:35] wire [3:0] _a_opcode_lookup_T_1 = inflight_opcodes; // @[Monitor.scala:616:35, :637:44] reg [7:0] inflight_sizes; // @[Monitor.scala:618:33] wire [7:0] _a_size_lookup_T_1 = inflight_sizes; // @[Monitor.scala:618:33, :641:40] wire [11:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [11:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [11:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 12'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [11:0] a_first_counter_1; // @[Edges.scala:229:27] wire [12:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 13'h1; // @[Edges.scala:229:27, :230:28] wire [11:0] a_first_counter1_1 = _a_first_counter1_T_1[11:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 12'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 12'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 12'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 \| _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [11:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [11:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [11:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [11:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [11:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5; // @[package.scala:243:46] wire [11:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 12'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [11:0] d_first_counter_1; // @[Edges.scala:229:27] wire [12:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 13'h1; // @[Edges.scala:229:27, :230:28] wire [11:0] d_first_counter1_1 = _d_first_counter1_T_1[11:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 12'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 12'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 12'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 \| _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [11:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [11:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [11:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire a_set; // @[Monitor.scala:626:34] wire a_set_wo_ready; // @[Monitor.scala:627:34] wire [3:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [7:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [15:0] _a_opcode_lookup_T_6 = {12'h0, _a_opcode_lookup_T_1}; // @[Monitor.scala:637:{44,97}] wire [15:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [7:0] a_size_lookup; // @[Monitor.scala:639:33] wire [15:0] _a_size_lookup_T_6 = {8'h0, _a_size_lookup_T_1}; // @[Monitor.scala:641:{40,91}] wire [15:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[15:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[7:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [4:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _T_1145 = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26] assign a_set_wo_ready = _T_1145; // @[Monitor.scala:627:34, :651:26] wire _same_cycle_resp_T; // @[Monitor.scala:684:44] assign _same_cycle_resp_T = _T_1145; // @[Monitor.scala:651:26, :684:44] assign a_set = _T_1222 & a_first_1; // @[Decoupled.scala:51:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = a_set ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:626:34, :646:40, :655:70, :657:{28,61}] wire [4:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [4:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = a_set ? _a_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:626:34, :648:38, :655:70, :658:{28,59}] wire [18:0] _a_opcodes_set_T_1 = {15'h0, a_opcodes_set_interm}; // @[Monitor.scala:646:40, :659:54] assign a_opcodes_set = a_set ? _a_opcodes_set_T_1[3:0] : 4'h0; // @[Monitor.scala:626:34, :630:33, :655:70, :659:{28,54}] wire [19:0] _a_sizes_set_T_1 = {15'h0, a_sizes_set_interm}; // @[Monitor.scala:648:38, :660:52] assign a_sizes_set = a_set ? _a_sizes_set_T_1[7:0] : 8'h0; // @[Monitor.scala:626:34, :632:31, :655:70, :660:{28,52}] wire d_clr; // @[Monitor.scala:664:34] wire d_clr_wo_ready; // @[Monitor.scala:665:34] wire [3:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [7:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_1 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_1; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_1; // @[Monitor.scala:673:46, :783:46] wire _T_1194 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] assign d_clr_wo_ready = _T_1194 & ~d_release_ack; // @[Monitor.scala:665:34, :673:46, :674:{26,71,74}] assign d_clr = _T_1295 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_opcodes_clr = {4{d_clr}}; // @[Monitor.scala:664:34, :668:33, :678:89, :680:21] assign d_sizes_clr = {8{d_clr}}; // @[Monitor.scala:664:34, :670:31, :678:89, :681:21] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire same_cycle_resp = _same_cycle_resp_T_1; // @[Monitor.scala:684:{55,88}] wire [1:0] _inflight_T = {inflight[1], inflight[0] \| a_set}; // @[Monitor.scala:614:27, :626:34, :705:27] wire _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [1:0] _inflight_T_2 = {1'h0, _inflight_T[0] & _inflight_T_1}; // @[Monitor.scala:705:{27,36,38}] wire [3:0] _inflight_opcodes_T = inflight_opcodes \| a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [3:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [3:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [7:0] _inflight_sizes_T = inflight_sizes \| a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [7:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [7:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [1:0] inflight_1; // @[Monitor.scala:726:35] wire [1:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [3:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [3:0] _c_opcode_lookup_T_1 = inflight_opcodes_1; // @[Monitor.scala:727:35, :749:44] wire [3:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [7:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [7:0] _c_size_lookup_T_1 = inflight_sizes_1; // @[Monitor.scala:728:35, :750:42] wire [7:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire [11:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [11:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8; // @[package.scala:243:46] wire [11:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 12'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [11:0] d_first_counter_2; // @[Edges.scala:229:27] wire [12:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 13'h1; // @[Edges.scala:229:27, :230:28] wire [11:0] d_first_counter1_2 = _d_first_counter1_T_2[11:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 12'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 12'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 12'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 \| _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [11:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [11:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [11:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [7:0] c_size_lookup; // @[Monitor.scala:748:35] wire [15:0] _c_opcode_lookup_T_6 = {12'h0, _c_opcode_lookup_T_1}; // @[Monitor.scala:749:{44,97}] wire [15:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [15:0] _c_size_lookup_T_6 = {8'h0, _c_size_lookup_T_1}; // @[Monitor.scala:750:{42,93}] wire [15:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[15:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[7:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire d_clr_1; // @[Monitor.scala:774:34] wire d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [3:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [7:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_1266 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_1266 & d_release_ack_1; // @[Monitor.scala:775:34, :783:46, :784:{26,71}] assign d_clr_1 = _T_1295 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_opcodes_clr_1 = {4{d_clr_1}}; // @[Monitor.scala:774:34, :776:34, :788:88, :790:21] assign d_sizes_clr_1 = {8{d_clr_1}}; // @[Monitor.scala:774:34, :777:34, :788:88, :791:21] wire _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [1:0] _inflight_T_5 = {1'h0, _inflight_T_3[0] & _inflight_T_4}; // @[Monitor.scala:814:{35,44,46}] wire [3:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [3:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [7:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [7:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to the following Chisel files. File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /* Like Vec.apply(idx), but tolerates indices of mismatched width / def extract(idx: UInt): T = x((idx \| 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx \| 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def \| (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a \|\| b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_\|\|_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /* Any Data subtype that has a Bool member named valid. / type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /* converts from camel case to to underscores, also removing all spaces / def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /* converts spaces or underscores to hyphens, also lowering case / def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y \| (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y \|\| y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 \| 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /* Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation */ def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag }	module OptimizationBarrier_TLBEntryData_172( // @[package.scala:267:30] input clock, // @[package.scala:267:30] input reset, // @[package.scala:267:30] input [19:0] io_x_ppn, // @[package.scala:268:18] input io_x_u, // @[package.scala:268:18] input io_x_g, // @[package.scala:268:18] input io_x_ae_ptw, // @[package.scala:268:18] input io_x_ae_final, // @[package.scala:268:18] input io_x_ae_stage2, // @[package.scala:268:18] input io_x_pf, // @[package.scala:268:18] input io_x_gf, // @[package.scala:268:18] input io_x_sw, // @[package.scala:268:18] input io_x_sx, // @[package.scala:268:18] input io_x_sr, // @[package.scala:268:18] input io_x_hw, // @[package.scala:268:18] input io_x_hx, // @[package.scala:268:18] input io_x_hr, // @[package.scala:268:18] input io_x_pw, // @[package.scala:268:18] input io_x_px, // @[package.scala:268:18] input io_x_pr, // @[package.scala:268:18] input io_x_ppp, // @[package.scala:268:18] input io_x_pal, // @[package.scala:268:18] input io_x_paa, // @[package.scala:268:18] input io_x_eff, // @[package.scala:268:18] input io_x_c, // @[package.scala:268:18] input io_x_fragmented_superpage, // @[package.scala:268:18] output io_y_u, // @[package.scala:268:18] output io_y_ae_ptw, // @[package.scala:268:18] output io_y_ae_final, // @[package.scala:268:18] output io_y_ae_stage2, // @[package.scala:268:18] output io_y_pf, // @[package.scala:268:18] output io_y_gf, // @[package.scala:268:18] output io_y_sw, // @[package.scala:268:18] output io_y_sx, // @[package.scala:268:18] output io_y_sr, // @[package.scala:268:18] output io_y_hw, // @[package.scala:268:18] output io_y_hx, // @[package.scala:268:18] output io_y_hr, // @[package.scala:268:18] output io_y_pw, // @[package.scala:268:18] output io_y_px, // @[package.scala:268:18] output io_y_pr, // @[package.scala:268:18] output io_y_ppp, // @[package.scala:268:18] output io_y_pal, // @[package.scala:268:18] output io_y_paa, // @[package.scala:268:18] output io_y_eff, // @[package.scala:268:18] output io_y_c // @[package.scala:268:18] ); wire [19:0] io_x_ppn_0 = io_x_ppn; // @[package.scala:267:30] wire io_x_u_0 = io_x_u; // @[package.scala:267:30] wire io_x_g_0 = io_x_g; // @[package.scala:267:30] wire io_x_ae_ptw_0 = io_x_ae_ptw; // @[package.scala:267:30] wire io_x_ae_final_0 = io_x_ae_final; // @[package.scala:267:30] wire io_x_ae_stage2_0 = io_x_ae_stage2; // @[package.scala:267:30] wire io_x_pf_0 = io_x_pf; // @[package.scala:267:30] wire io_x_gf_0 = io_x_gf; // @[package.scala:267:30] wire io_x_sw_0 = io_x_sw; // @[package.scala:267:30] wire io_x_sx_0 = io_x_sx; // @[package.scala:267:30] wire io_x_sr_0 = io_x_sr; // @[package.scala:267:30] wire io_x_hw_0 = io_x_hw; // @[package.scala:267:30] wire io_x_hx_0 = io_x_hx; // @[package.scala:267:30] wire io_x_hr_0 = io_x_hr; // @[package.scala:267:30] wire io_x_pw_0 = io_x_pw; // @[package.scala:267:30] wire io_x_px_0 = io_x_px; // @[package.scala:267:30] wire io_x_pr_0 = io_x_pr; // @[package.scala:267:30] wire io_x_ppp_0 = io_x_ppp; // @[package.scala:267:30] wire io_x_pal_0 = io_x_pal; // @[package.scala:267:30] wire io_x_paa_0 = io_x_paa; // @[package.scala:267:30] wire io_x_eff_0 = io_x_eff; // @[package.scala:267:30] wire io_x_c_0 = io_x_c; // @[package.scala:267:30] wire io_x_fragmented_superpage_0 = io_x_fragmented_superpage; // @[package.scala:267:30] wire [19:0] io_y_ppn = io_x_ppn_0; // @[package.scala:267:30] wire io_y_u_0 = io_x_u_0; // @[package.scala:267:30] wire io_y_g = io_x_g_0; // @[package.scala:267:30] wire io_y_ae_ptw_0 = io_x_ae_ptw_0; // @[package.scala:267:30] wire io_y_ae_final_0 = io_x_ae_final_0; // @[package.scala:267:30] wire io_y_ae_stage2_0 = io_x_ae_stage2_0; // @[package.scala:267:30] wire io_y_pf_0 = io_x_pf_0; // @[package.scala:267:30] wire io_y_gf_0 = io_x_gf_0; // @[package.scala:267:30] wire io_y_sw_0 = io_x_sw_0; // @[package.scala:267:30] wire io_y_sx_0 = io_x_sx_0; // @[package.scala:267:30] wire io_y_sr_0 = io_x_sr_0; // @[package.scala:267:30] wire io_y_hw_0 = io_x_hw_0; // @[package.scala:267:30] wire io_y_hx_0 = io_x_hx_0; // @[package.scala:267:30] wire io_y_hr_0 = io_x_hr_0; // @[package.scala:267:30] wire io_y_pw_0 = io_x_pw_0; // @[package.scala:267:30] wire io_y_px_0 = io_x_px_0; // @[package.scala:267:30] wire io_y_pr_0 = io_x_pr_0; // @[package.scala:267:30] wire io_y_ppp_0 = io_x_ppp_0; // @[package.scala:267:30] wire io_y_pal_0 = io_x_pal_0; // @[package.scala:267:30] wire io_y_paa_0 = io_x_paa_0; // @[package.scala:267:30] wire io_y_eff_0 = io_x_eff_0; // @[package.scala:267:30] wire io_y_c_0 = io_x_c_0; // @[package.scala:267:30] wire io_y_fragmented_superpage = io_x_fragmented_superpage_0; // @[package.scala:267:30] assign io_y_u = io_y_u_0; // @[package.scala:267:30] assign io_y_ae_ptw = io_y_ae_ptw_0; // @[package.scala:267:30] assign io_y_ae_final = io_y_ae_final_0; // @[package.scala:267:30] assign io_y_ae_stage2 = io_y_ae_stage2_0; // @[package.scala:267:30] assign io_y_pf = io_y_pf_0; // @[package.scala:267:30] assign io_y_gf = io_y_gf_0; // @[package.scala:267:30] assign io_y_sw = io_y_sw_0; // @[package.scala:267:30] assign io_y_sx = io_y_sx_0; // @[package.scala:267:30] assign io_y_sr = io_y_sr_0; // @[package.scala:267:30] assign io_y_hw = io_y_hw_0; // @[package.scala:267:30] assign io_y_hx = io_y_hx_0; // @[package.scala:267:30] assign io_y_hr = io_y_hr_0; // @[package.scala:267:30] assign io_y_pw = io_y_pw_0; // @[package.scala:267:30] assign io_y_px = io_y_px_0; // @[package.scala:267:30] assign io_y_pr = io_y_pr_0; // @[package.scala:267:30] assign io_y_ppp = io_y_ppp_0; // @[package.scala:267:30] assign io_y_pal = io_y_pal_0; // @[package.scala:267:30] assign io_y_paa = io_y_paa_0; // @[package.scala:267:30] assign io_y_eff = io_y_eff_0; // @[package.scala:267:30] assign io_y_c = io_y_c_0; // @[package.scala:267:30] endmodule
Generate the Verilog code corresponding to the following Chisel files. File Monitor.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceLine import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import freechips.rocketchip.diplomacy.EnableMonitors import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode} import freechips.rocketchip.util.PlusArg case class TLMonitorArgs(edge: TLEdge) abstract class TLMonitorBase(args: TLMonitorArgs) extends Module { val io = IO(new Bundle { val in = Input(new TLBundle(args.edge.bundle)) }) def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit legalize(io.in, args.edge, reset) } object TLMonitor { def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = { if (enable) { EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) } } else { node } } } class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args) { require (args.edge.params(TLMonitorStrictMode) \|\| (! args.edge.params(TestplanTestType).formal)) val cover_prop_class = PropertyClass.Default //Like assert but can flip to being an assumption for formal verification def monAssert(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir, cond, message, PropertyClass.Default) } def assume(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir.flip, cond, message, PropertyClass.Default) } def extra = { args.edge.sourceInfo match { case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)" case _ => "" } } def visible(address: UInt, source: UInt, edge: TLEdge) = edge.client.clients.map { c => !c.sourceId.contains(source) \|\| c.visibility.map(_.contains(address)).reduce(_ \|\| _) }.reduce(_ && _) def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = { //switch this flag to turn on diplomacy in error messages def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n" monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra) // Reuse these subexpressions to save some firrtl lines val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility") //The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B //TODO: check for acquireT? when (bundle.opcode === TLMessages.AcquireBlock) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra) } when (bundle.opcode === TLMessages.AcquirePerm) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra) monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra) monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra) monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra) } } def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = { monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra) monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility") // Reuse these subexpressions to save some firrtl lines val address_ok = edge.manager.containsSafe(edge.address(bundle)) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source when (bundle.opcode === TLMessages.Probe) { assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra) assume (address_ok, "'B' channel Probe carries unmanaged address" + extra) assume (legal_source, "'B' channel Probe carries source that is not first source" + extra) assume (is_aligned, "'B' channel Probe address not aligned to size" + extra) assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra) assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra) assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra) monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra) monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra) monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra) monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra) } } def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = { monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val address_ok = edge.manager.containsSafe(edge.address(bundle)) monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility") when (bundle.opcode === TLMessages.ProbeAck) { monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra) } when (bundle.opcode === TLMessages.ProbeAckData) { monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.Release) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra) monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra) } when (bundle.opcode === TLMessages.ReleaseData) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.AccessAck) { monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra) } when (bundle.opcode === TLMessages.HintAck) { monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra) } } def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = { assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val sink_ok = bundle.sink < edge.manager.endSinkId.U val deny_put_ok = edge.manager.mayDenyPut.B val deny_get_ok = edge.manager.mayDenyGet.B when (bundle.opcode === TLMessages.ReleaseAck) { assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra) assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra) assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra) } when (bundle.opcode === TLMessages.Grant) { assume (source_ok, "'D' channel Grant carries invalid source ID" + extra) assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra) assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel Grant is denied" + extra) } when (bundle.opcode === TLMessages.GrantData) { assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra) assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra) assume (!bundle.denied \|\| bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra) assume (deny_get_ok \|\| !bundle.denied, "'D' channel GrantData is denied" + extra) } when (bundle.opcode === TLMessages.AccessAck) { assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel AccessAck is denied" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra) assume (!bundle.denied \|\| bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra) assume (deny_get_ok \|\| !bundle.denied, "'D' channel AccessAckData is denied" + extra) } when (bundle.opcode === TLMessages.HintAck) { assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel HintAck is denied" + extra) } } def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = { val sink_ok = bundle.sink < edge.manager.endSinkId.U monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra) } def legalizeFormat(bundle: TLBundle, edge: TLEdge) = { when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) } when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) } when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) } when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) } } else { monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra) monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra) monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra) } } def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = { val a_first = edge.first(a.bits, a.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (a.valid && !a_first) { monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra) monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra) monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra) monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra) monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra) } when (a.fire && a_first) { opcode := a.bits.opcode param := a.bits.param size := a.bits.size source := a.bits.source address := a.bits.address } } def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = { val b_first = edge.first(b.bits, b.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (b.valid && !b_first) { monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra) monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra) monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra) monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra) monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra) } when (b.fire && b_first) { opcode := b.bits.opcode param := b.bits.param size := b.bits.size source := b.bits.source address := b.bits.address } } def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = { // Symbolic variable val sym_source = Wire(UInt(edge.client.endSourceId.W)) // TODO: Connect sym_source to a fixed value for simulation and to a // free wire in formal sym_source := 0.U // Type casting Int to UInt val maxSourceId = Wire(UInt(edge.client.endSourceId.W)) maxSourceId := edge.client.endSourceId.U // Delayed verison of sym_source val sym_source_d = Reg(UInt(edge.client.endSourceId.W)) sym_source_d := sym_source // These will be constraints for FV setup Property( MonitorDirection.Monitor, (sym_source === sym_source_d), "sym_source should remain stable", PropertyClass.Default) Property( MonitorDirection.Monitor, (sym_source <= maxSourceId), "sym_source should take legal value", PropertyClass.Default) val my_resp_pend = RegInit(false.B) val my_opcode = Reg(UInt()) val my_size = Reg(UInt()) val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire) val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire) val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source) val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source) val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat) val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend) when (my_set_resp_pend) { my_resp_pend := true.B } .elsewhen (my_clr_resp_pend) { my_resp_pend := false.B } when (my_a_first_beat) { my_opcode := bundle.a.bits.opcode my_size := bundle.a.bits.size } val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size) val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode) val my_resp_opcode_legal = Wire(Bool()) when ((my_resp_opcode === TLMessages.Get) \|\| (my_resp_opcode === TLMessages.ArithmeticData) \|\| (my_resp_opcode === TLMessages.LogicalData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData) } .elsewhen ((my_resp_opcode === TLMessages.PutFullData) \|\| (my_resp_opcode === TLMessages.PutPartialData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck) } .otherwise { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck) } monAssert (IfThen(my_resp_pend, !my_a_first_beat), "Request message should not be sent with a source ID, for which a response message" + "is already pending (not received until current cycle) for a prior request message" + "with the same source ID" + extra) assume (IfThen(my_clr_resp_pend, (my_set_resp_pend \|\| my_resp_pend)), "Response message should be accepted with a source ID only if a request message with the" + "same source ID has been accepted or is being accepted in the current cycle" + extra) assume (IfThen(my_d_first_beat, (my_a_first_beat \|\| my_resp_pend)), "Response message should be sent with a source ID only if a request message with the" + "same source ID has been accepted or is being sent in the current cycle" + extra) assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)), "If d_valid is 1, then d_size should be same as a_size of the corresponding request" + "message" + extra) assume (IfThen(my_d_first_beat, my_resp_opcode_legal), "If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" + "request message" + extra) } def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = { val c_first = edge.first(c.bits, c.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (c.valid && !c_first) { monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra) monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra) monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra) monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra) monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra) } when (c.fire && c_first) { opcode := c.bits.opcode param := c.bits.param size := c.bits.size source := c.bits.source address := c.bits.address } } def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = { val d_first = edge.first(d.bits, d.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val sink = Reg(UInt()) val denied = Reg(Bool()) when (d.valid && !d_first) { assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra) assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra) assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra) assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra) assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra) assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra) } when (d.fire && d_first) { opcode := d.bits.opcode param := d.bits.param size := d.bits.size source := d.bits.source sink := d.bits.sink denied := d.bits.denied } } def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = { legalizeMultibeatA(bundle.a, edge) legalizeMultibeatD(bundle.d, edge) if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { legalizeMultibeatB(bundle.b, edge) legalizeMultibeatC(bundle.c, edge) } } //This is left in for almond which doesn't adhere to the tilelink protocol @deprecated("Use legalizeADSource instead if possible","") def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.client.endSourceId.W)) val a_first = edge.first(bundle.a.bits, bundle.a.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val a_set = WireInit(0.U(edge.client.endSourceId.W)) when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) assume((a_set \| inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra) } if (edge.manager.minLatency > 0) { assume(a_set =/= d_clr \|\| !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight \| a_set) & ~d_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") assert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = { val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size) val log_a_size_bus_size = log2Ceil(a_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error inflight.suggestName("inflight") val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) inflight_opcodes.suggestName("inflight_opcodes") val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) inflight_sizes.suggestName("inflight_sizes") val a_first = edge.first(bundle.a.bits, bundle.a.fire) a_first.suggestName("a_first") val d_first = edge.first(bundle.d.bits, bundle.d.fire) d_first.suggestName("d_first") val a_set = WireInit(0.U(edge.client.endSourceId.W)) val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) a_set.suggestName("a_set") a_set_wo_ready.suggestName("a_set_wo_ready") val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) a_opcodes_set.suggestName("a_opcodes_set") val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) a_sizes_set.suggestName("a_sizes_set") val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W)) a_opcode_lookup.suggestName("a_opcode_lookup") a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W)) a_size_lookup.suggestName("a_size_lookup") a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant)) val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant)) val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W)) a_opcodes_set_interm.suggestName("a_opcodes_set_interm") val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W)) a_sizes_set_interm.suggestName("a_sizes_set_interm") when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) { a_set_wo_ready := UIntToOH(bundle.a.bits.source) } when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) \| 1.U a_sizes_set_interm := (bundle.a.bits.size << 1.U) \| 1.U a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U) a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U) monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) d_opcodes_clr.suggestName("d_opcodes_clr") val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) \|\| same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) \|\| (bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra) assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) \|\| (bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra) assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) { assume((!bundle.d.ready) \|\| bundle.a.ready, "ready check") } if (edge.manager.minLatency > 0) { assume(a_set_wo_ready =/= d_clr_wo_ready \|\| !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight \| a_set) & ~d_clr inflight_opcodes := (inflight_opcodes \| a_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes \| a_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = { val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size) val log_c_size_bus_size = log2Ceil(c_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) inflight.suggestName("inflight") inflight_opcodes.suggestName("inflight_opcodes") inflight_sizes.suggestName("inflight_sizes") val c_first = edge.first(bundle.c.bits, bundle.c.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) c_first.suggestName("c_first") d_first.suggestName("d_first") val c_set = WireInit(0.U(edge.client.endSourceId.W)) val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) c_set.suggestName("c_set") c_set_wo_ready.suggestName("c_set_wo_ready") c_opcodes_set.suggestName("c_opcodes_set") c_sizes_set.suggestName("c_sizes_set") val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W)) val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W)) c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U c_opcode_lookup.suggestName("c_opcode_lookup") c_size_lookup.suggestName("c_size_lookup") val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W)) val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W)) c_opcodes_set_interm.suggestName("c_opcodes_set_interm") c_sizes_set_interm.suggestName("c_sizes_set_interm") when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) { c_set_wo_ready := UIntToOH(bundle.c.bits.source) } when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) { c_set := UIntToOH(bundle.c.bits.source) c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) \| 1.U c_sizes_set_interm := (bundle.c.bits.size << 1.U) \| 1.U c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U) c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U) monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra) } val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck \|\| bundle.c.bits.opcode === TLMessages.ProbeAckData val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") d_opcodes_clr.suggestName("d_opcodes_clr") d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) \|\| same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) { assume((!bundle.d.ready) \|\| bundle.c.ready, "ready check") } if (edge.manager.minLatency > 0) { when (c_set_wo_ready.orR) { assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra) } } inflight := (inflight \| c_set) & ~d_clr inflight_opcodes := (inflight_opcodes \| c_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes \| c_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.c.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.manager.endSinkId.W)) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val e_first = true.B val d_set = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) { d_set := UIntToOH(bundle.d.bits.sink) assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra) } val e_clr = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) { e_clr := UIntToOH(bundle.e.bits.sink) monAssert((d_set \| inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra) } // edge.client.minLatency applies to BC, not DE inflight := (inflight \| d_set) & ~e_clr } def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = { val sourceBits = log2Ceil(edge.client.endSourceId) val tooBig = 14 // >16kB worth of flight information gets to be too much if (sourceBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked") } else { if (args.edge.params(TestplanTestType).simulation) { if (args.edge.params(TLMonitorStrictMode)) { legalizeADSource(bundle, edge) legalizeCDSource(bundle, edge) } else { legalizeADSourceOld(bundle, edge) } } if (args.edge.params(TestplanTestType).formal) { legalizeADSourceFormal(bundle, edge) } } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { // legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize... val sinkBits = log2Ceil(edge.manager.endSinkId) if (sinkBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked") } else { legalizeDESink(bundle, edge) } } } def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = { legalizeFormat (bundle, edge) legalizeMultibeat (bundle, edge) legalizeUnique (bundle, edge) } } File Misc.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import scala.math._ class ParameterizedBundle(implicit p: Parameters) extends Bundle trait Clocked extends Bundle { val clock = Clock() val reset = Bool() } object DecoupledHelper { def apply(rvs: Bool) = new DecoupledHelper(rvs) } class DecoupledHelper(val rvs: Seq[Bool]) { def fire(exclude: Bool, includes: Bool) = { require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!") (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _) } def fire() = { rvs.reduce(_ && _) } } object MuxT { def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2)) def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3)) def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4)) } /** Creates a cascade of n MuxTs to search for a key value. / object MuxTLookup { def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } } object ValidMux { def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]): ValidIO[T] = { apply(v1 +: v2.toSeq) } def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = { val out = Wire(Valid(valids.head.bits.cloneType)) out.valid := valids.map(_.valid).reduce(_ \|\| _) out.bits := MuxCase(valids.head.bits, valids.map(v => (v.valid -> v.bits))) out } } object Str { def apply(s: String): UInt = { var i = BigInt(0) require(s.forall(validChar _)) for (c <- s) i = (i << 8) \| c i.U((s.length8).W) } def apply(x: Char): UInt = { require(validChar(x)) x.U(8.W) } def apply(x: UInt): UInt = apply(x, 10) def apply(x: UInt, radix: Int): UInt = { val rad = radix.U val w = x.getWidth require(w > 0) var q = x var s = digit(q % rad) for (i <- 1 until ceil(log(2)/log(radix)w).toInt) { q = q / rad s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s) } s } def apply(x: SInt): UInt = apply(x, 10) def apply(x: SInt, radix: Int): UInt = { val neg = x < 0.S val abs = x.abs.asUInt if (radix != 10) { Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix)) } else { val rad = radix.U val w = abs.getWidth require(w > 0) var q = abs var s = digit(q % rad) var needSign = neg for (i <- 1 until ceil(log(2)/log(radix)w).toInt) { q = q / rad val placeSpace = q === 0.U val space = Mux(needSign, Str('-'), Str(' ')) needSign = needSign && !placeSpace s = Cat(Mux(placeSpace, space, digit(q % rad)), s) } Cat(Mux(needSign, Str('-'), Str(' ')), s) } } private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0) private def validChar(x: Char) = x == (x & 0xFF) } object Split { def apply(x: UInt, n0: Int) = { val w = x.getWidth (x.extract(w-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n2: Int, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } } object Random { def apply(mod: Int, random: UInt): UInt = { if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0) else PriorityEncoder(partition(apply(1 << log2Up(mod8), random), mod)) } def apply(mod: Int): UInt = apply(mod, randomizer) def oneHot(mod: Int, random: UInt): UInt = { if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0)) else PriorityEncoderOH(partition(apply(1 << log2Up(mod8), random), mod)).asUInt } def oneHot(mod: Int): UInt = oneHot(mod, randomizer) private def randomizer = LFSR(16) private def partition(value: UInt, slices: Int) = Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U) } object Majority { def apply(in: Set[Bool]): Bool = { val n = (in.size >> 1) + 1 val clauses = in.subsets(n).map(_.reduce(_ && _)) clauses.reduce(_ \|\| _) } def apply(in: Seq[Bool]): Bool = apply(in.toSet) def apply(in: UInt): Bool = apply(in.asBools.toSet) } object PopCountAtLeast { private def two(x: UInt): (Bool, Bool) = x.getWidth match { case 1 => (x.asBool, false.B) case n => val half = x.getWidth / 2 val (leftOne, leftTwo) = two(x(half - 1, 0)) val (rightOne, rightTwo) = two(x(x.getWidth - 1, half)) (leftOne \|\| rightOne, leftTwo \|\| rightTwo \|\| (leftOne && rightOne)) } def apply(x: UInt, n: Int): Bool = n match { case 0 => true.B case 1 => x.orR case 2 => two(x)._2 case 3 => PopCount(x) >= n.U } } // This gets used everywhere, so make the smallest circuit possible ... // Given an address and size, create a mask of beatBytes size // eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111 // groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01 object MaskGen { def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = { require (groupBy >= 1 && beatBytes >= groupBy) require (isPow2(beatBytes) && isPow2(groupBy)) val lgBytes = log2Ceil(beatBytes) val sizeOH = UIntToOH(lgSize \| 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) \| (groupBy2 - 1).U def helper(i: Int): Seq[(Bool, Bool)] = { if (i == 0) { Seq((lgSize >= lgBytes.asUInt, true.B)) } else { val sub = helper(i-1) val size = sizeOH(lgBytes - i) val bit = addr_lo(lgBytes - i) val nbit = !bit Seq.tabulate (1 << i) { j => val (sub_acc, sub_eq) = sub(j/2) val eq = sub_eq && (if (j % 2 == 1) bit else nbit) val acc = sub_acc \|\| (size && eq) (acc, eq) } } } if (groupBy == beatBytes) 1.U else Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse) } } File PlusArg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.experimental._ import chisel3.util.HasBlackBoxResource @deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05") case class PlusArgInfo(default: BigInt, docstring: String) /** Case class for PlusArg information * * @tparam A scala type of the PlusArg value * @param default optional default value * @param docstring text to include in the help * @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT) / private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String) /* Typeclass for converting a type to a doctype string * @tparam A some type / trait Doctypeable[A] { /* Return the doctype string for some option / def toDoctype(a: Option[A]): String } /* Object containing implementations of the Doctypeable typeclass / object Doctypes { /* Converts an Int => "INT" / implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" } /* Converts a BigInt => "INT" / implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" } /* Converts a String => "STRING" / implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" } } class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map( "FORMAT" -> StringParam(format), "DEFAULT" -> IntParam(default), "WIDTH" -> IntParam(width) )) with HasBlackBoxResource { val io = IO(new Bundle { val out = Output(UInt(width.W)) }) addResource("/vsrc/plusarg_reader.v") } / This wrapper class has no outputs, making it clear it is a simulation-only construct / class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module { val io = IO(new Bundle { val count = Input(UInt(width.W)) }) val max = Module(new plusarg_reader(format, default, docstring, width)).io.out when (max > 0.U) { assert (io.count < max, s"Timeout exceeded: $docstring") } } import Doctypes._ object PlusArg { /* PlusArg("foo") will return 42.U if the simulation is run with +foo=42 * Do not use this as an initial register value. The value is set in an * initial block and thus accessing it from another initial is racey. * Add a docstring to document the arg, which can be dumped in an elaboration * pass. / def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out } /* PlusArg.timeout(name, default, docstring)(count) will use chisel.assert * to kill the simulation when count exceeds the specified integer argument. * Default 0 will never assert. / def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count } } object PlusArgArtefacts { private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty / Add a new PlusArg / @deprecated( "Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05" ) def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring) /* Add a new PlusArg * * @tparam A scala type of the PlusArg value * @param name name for the PlusArg * @param default optional default value * @param docstring text to include in the help / def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit = artefacts = artefacts ++ Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default))) / From plus args, generate help text / private def serializeHelp_cHeader(tab: String = ""): String = artefacts .map{ case(arg, info) => s"""\|$tab+$arg=${info.doctype}\\n\\ \|$tab${" "20}${info.docstring}\\n\\ \|""".stripMargin ++ info.default.map{ case default => s"$tab${" "22}(default=${default})\\n\\\n"}.getOrElse("") }.toSeq.mkString("\\n\\\n") ++ "\"" / From plus args, generate a char array of their names / private def serializeArray_cHeader(tab: String = ""): String = { val prettyTab = tab + " " 44 // Length of 'static const ...' s"${tab}static const char * verilog_plusargs [] = {\\\n" ++ artefacts .map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" } .mkString("")++ s"${prettyTab}0};" } /* Generate C code to be included in emulator.cc that helps with * argument parsing based on available Verilog PlusArgs / def serialize_cHeader(): String = s"""\|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\ \|${serializeHelp_cHeader(" "7)} \|${serializeArray_cHeader()} \|""".stripMargin } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /* Like Vec.apply(idx), but tolerates indices of mismatched width / def extract(idx: UInt): T = x((idx \| 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx \| 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def \| (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a \|\| b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_\|\|_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /* Any Data subtype that has a Bool member named valid. / type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /* converts from camel case to to underscores, also removing all spaces / def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /* converts spaces or underscores to hyphens, also lowering case / def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y \| (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y \|\| y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 \| 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /* Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation / def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Bundles.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import freechips.rocketchip.util._ import scala.collection.immutable.ListMap import chisel3.util.Decoupled import chisel3.util.DecoupledIO import chisel3.reflect.DataMirror abstract class TLBundleBase(val params: TLBundleParameters) extends Bundle // common combos in lazy policy: // Put + Acquire // Release + AccessAck object TLMessages { // A B C D E def PutFullData = 0.U // . . => AccessAck def PutPartialData = 1.U // . . => AccessAck def ArithmeticData = 2.U // . . => AccessAckData def LogicalData = 3.U // . . => AccessAckData def Get = 4.U // . . => AccessAckData def Hint = 5.U // . . => HintAck def AcquireBlock = 6.U // . => Grant[Data] def AcquirePerm = 7.U // . => Grant[Data] def Probe = 6.U // . => ProbeAck[Data] def AccessAck = 0.U // . . def AccessAckData = 1.U // . . def HintAck = 2.U // . . def ProbeAck = 4.U // . def ProbeAckData = 5.U // . def Release = 6.U // . => ReleaseAck def ReleaseData = 7.U // . => ReleaseAck def Grant = 4.U // . => GrantAck def GrantData = 5.U // . => GrantAck def ReleaseAck = 6.U // . def GrantAck = 0.U // . def isA(x: UInt) = x <= AcquirePerm def isB(x: UInt) = x <= Probe def isC(x: UInt) = x <= ReleaseData def isD(x: UInt) = x <= ReleaseAck def adResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, Grant, Grant) def bcResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, ProbeAck, ProbeAck) def a = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("AcquireBlock",TLPermissions.PermMsgGrow), ("AcquirePerm",TLPermissions.PermMsgGrow)) def b = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("Probe",TLPermissions.PermMsgCap)) def c = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("ProbeAck",TLPermissions.PermMsgReport), ("ProbeAckData",TLPermissions.PermMsgReport), ("Release",TLPermissions.PermMsgReport), ("ReleaseData",TLPermissions.PermMsgReport)) def d = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("Grant",TLPermissions.PermMsgCap), ("GrantData",TLPermissions.PermMsgCap), ("ReleaseAck",TLPermissions.PermMsgReserved)) } /* * The three primary TileLink permissions are: * (T)runk: the agent is (or is on inwards path to) the global point of serialization. * (B)ranch: the agent is on an outwards path to * (N)one: * These permissions are permuted by transfer operations in various ways. * Operations can cap permissions, request for them to be grown or shrunk, * or for a report on their current status. / object TLPermissions { val aWidth = 2 val bdWidth = 2 val cWidth = 3 // Cap types (Grant = new permissions, Probe = permisions <= target) def toT = 0.U(bdWidth.W) def toB = 1.U(bdWidth.W) def toN = 2.U(bdWidth.W) def isCap(x: UInt) = x <= toN // Grow types (Acquire = permissions >= target) def NtoB = 0.U(aWidth.W) def NtoT = 1.U(aWidth.W) def BtoT = 2.U(aWidth.W) def isGrow(x: UInt) = x <= BtoT // Shrink types (ProbeAck, Release) def TtoB = 0.U(cWidth.W) def TtoN = 1.U(cWidth.W) def BtoN = 2.U(cWidth.W) def isShrink(x: UInt) = x <= BtoN // Report types (ProbeAck, Release) def TtoT = 3.U(cWidth.W) def BtoB = 4.U(cWidth.W) def NtoN = 5.U(cWidth.W) def isReport(x: UInt) = x <= NtoN def PermMsgGrow:Seq[String] = Seq("Grow NtoB", "Grow NtoT", "Grow BtoT") def PermMsgCap:Seq[String] = Seq("Cap toT", "Cap toB", "Cap toN") def PermMsgReport:Seq[String] = Seq("Shrink TtoB", "Shrink TtoN", "Shrink BtoN", "Report TotT", "Report BtoB", "Report NtoN") def PermMsgReserved:Seq[String] = Seq("Reserved") } object TLAtomics { val width = 3 // Arithmetic types def MIN = 0.U(width.W) def MAX = 1.U(width.W) def MINU = 2.U(width.W) def MAXU = 3.U(width.W) def ADD = 4.U(width.W) def isArithmetic(x: UInt) = x <= ADD // Logical types def XOR = 0.U(width.W) def OR = 1.U(width.W) def AND = 2.U(width.W) def SWAP = 3.U(width.W) def isLogical(x: UInt) = x <= SWAP def ArithMsg:Seq[String] = Seq("MIN", "MAX", "MINU", "MAXU", "ADD") def LogicMsg:Seq[String] = Seq("XOR", "OR", "AND", "SWAP") } object TLHints { val width = 1 def PREFETCH_READ = 0.U(width.W) def PREFETCH_WRITE = 1.U(width.W) def isHints(x: UInt) = x <= PREFETCH_WRITE def HintsMsg:Seq[String] = Seq("PrefetchRead", "PrefetchWrite") } sealed trait TLChannel extends TLBundleBase { val channelName: String } sealed trait TLDataChannel extends TLChannel sealed trait TLAddrChannel extends TLDataChannel final class TLBundleA(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleA_${params.shortName}" val channelName = "'A' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(List(TLAtomics.width, TLPermissions.aWidth, TLHints.width).max.W) // amo_opcode \|\| grow perms \|\| hint val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleB(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleB_${params.shortName}" val channelName = "'B' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val address = UInt(params.addressBits.W) // from // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleC(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleC_${params.shortName}" val channelName = "'C' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.cWidth.W) // shrink or report perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleD(params: TLBundleParameters) extends TLBundleBase(params) with TLDataChannel { override def typeName = s"TLBundleD_${params.shortName}" val channelName = "'D' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val sink = UInt(params.sinkBits.W) // from val denied = Bool() // implies corrupt iff Data val user = BundleMap(params.responseFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleE(params: TLBundleParameters) extends TLBundleBase(params) with TLChannel { override def typeName = s"TLBundleE_${params.shortName}" val channelName = "'E' channel" val sink = UInt(params.sinkBits.W) // to } class TLBundle(val params: TLBundleParameters) extends Record { // Emulate a Bundle with elements abcde or ad depending on params.hasBCE private val optA = Some (Decoupled(new TLBundleA(params))) private val optB = params.hasBCE.option(Flipped(Decoupled(new TLBundleB(params)))) private val optC = params.hasBCE.option(Decoupled(new TLBundleC(params))) private val optD = Some (Flipped(Decoupled(new TLBundleD(params)))) private val optE = params.hasBCE.option(Decoupled(new TLBundleE(params))) def a: DecoupledIO[TLBundleA] = optA.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleA(params))))) def b: DecoupledIO[TLBundleB] = optB.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleB(params))))) def c: DecoupledIO[TLBundleC] = optC.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleC(params))))) def d: DecoupledIO[TLBundleD] = optD.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleD(params))))) def e: DecoupledIO[TLBundleE] = optE.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleE(params))))) val elements = if (params.hasBCE) ListMap("e" -> e, "d" -> d, "c" -> c, "b" -> b, "a" -> a) else ListMap("d" -> d, "a" -> a) def tieoff(): Unit = { DataMirror.specifiedDirectionOf(a.ready) match { case SpecifiedDirection.Input => a.ready := false.B c.ready := false.B e.ready := false.B b.valid := false.B d.valid := false.B case SpecifiedDirection.Output => a.valid := false.B c.valid := false.B e.valid := false.B b.ready := false.B d.ready := false.B case _ => } } } object TLBundle { def apply(params: TLBundleParameters) = new TLBundle(params) } class TLAsyncBundleBase(val params: TLAsyncBundleParameters) extends Bundle class TLAsyncBundle(params: TLAsyncBundleParameters) extends TLAsyncBundleBase(params) { val a = new AsyncBundle(new TLBundleA(params.base), params.async) val b = Flipped(new AsyncBundle(new TLBundleB(params.base), params.async)) val c = new AsyncBundle(new TLBundleC(params.base), params.async) val d = Flipped(new AsyncBundle(new TLBundleD(params.base), params.async)) val e = new AsyncBundle(new TLBundleE(params.base), params.async) } class TLRationalBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = RationalIO(new TLBundleA(params)) val b = Flipped(RationalIO(new TLBundleB(params))) val c = RationalIO(new TLBundleC(params)) val d = Flipped(RationalIO(new TLBundleD(params))) val e = RationalIO(new TLBundleE(params)) } class TLCreditedBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = CreditedIO(new TLBundleA(params)) val b = Flipped(CreditedIO(new TLBundleB(params))) val c = CreditedIO(new TLBundleC(params)) val d = Flipped(CreditedIO(new TLBundleD(params))) val e = CreditedIO(new TLBundleE(params)) } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.nodes._ import freechips.rocketchip.diplomacy.{ AddressDecoder, AddressSet, BufferParams, DirectedBuffers, IdMap, IdMapEntry, IdRange, RegionType, TransferSizes } import freechips.rocketchip.resources.{Resource, ResourceAddress, ResourcePermissions} import freechips.rocketchip.util.{ AsyncQueueParams, BundleField, BundleFieldBase, BundleKeyBase, CreditedDelay, groupByIntoSeq, RationalDirection, SimpleProduct } import scala.math.max //These transfer sizes describe requests issued from masters on the A channel that will be responded by slaves on the D channel case class TLMasterToSlaveTransferSizes( // Supports both Acquire+Release of the following two sizes: acquireT: TransferSizes = TransferSizes.none, acquireB: TransferSizes = TransferSizes.none, arithmetic: TransferSizes = TransferSizes.none, logical: TransferSizes = TransferSizes.none, get: TransferSizes = TransferSizes.none, putFull: TransferSizes = TransferSizes.none, putPartial: TransferSizes = TransferSizes.none, hint: TransferSizes = TransferSizes.none) extends TLCommonTransferSizes { def intersect(rhs: TLMasterToSlaveTransferSizes) = TLMasterToSlaveTransferSizes( acquireT = acquireT .intersect(rhs.acquireT), acquireB = acquireB .intersect(rhs.acquireB), arithmetic = arithmetic.intersect(rhs.arithmetic), logical = logical .intersect(rhs.logical), get = get .intersect(rhs.get), putFull = putFull .intersect(rhs.putFull), putPartial = putPartial.intersect(rhs.putPartial), hint = hint .intersect(rhs.hint)) def mincover(rhs: TLMasterToSlaveTransferSizes) = TLMasterToSlaveTransferSizes( acquireT = acquireT .mincover(rhs.acquireT), acquireB = acquireB .mincover(rhs.acquireB), arithmetic = arithmetic.mincover(rhs.arithmetic), logical = logical .mincover(rhs.logical), get = get .mincover(rhs.get), putFull = putFull .mincover(rhs.putFull), putPartial = putPartial.mincover(rhs.putPartial), hint = hint .mincover(rhs.hint)) // Reduce rendering to a simple yes/no per field override def toString = { def str(x: TransferSizes, flag: String) = if (x.none) "" else flag def flags = Vector( str(acquireT, "T"), str(acquireB, "B"), str(arithmetic, "A"), str(logical, "L"), str(get, "G"), str(putFull, "F"), str(putPartial, "P"), str(hint, "H")) flags.mkString } // Prints out the actual information in a user readable way def infoString = { s"""acquireT = ${acquireT} \|acquireB = ${acquireB} \|arithmetic = ${arithmetic} \|logical = ${logical} \|get = ${get} \|putFull = ${putFull} \|putPartial = ${putPartial} \|hint = ${hint} \| \|""".stripMargin } } object TLMasterToSlaveTransferSizes { def unknownEmits = TLMasterToSlaveTransferSizes( acquireT = TransferSizes(1, 4096), acquireB = TransferSizes(1, 4096), arithmetic = TransferSizes(1, 4096), logical = TransferSizes(1, 4096), get = TransferSizes(1, 4096), putFull = TransferSizes(1, 4096), putPartial = TransferSizes(1, 4096), hint = TransferSizes(1, 4096)) def unknownSupports = TLMasterToSlaveTransferSizes() } //These transfer sizes describe requests issued from slaves on the B channel that will be responded by masters on the C channel case class TLSlaveToMasterTransferSizes( probe: TransferSizes = TransferSizes.none, arithmetic: TransferSizes = TransferSizes.none, logical: TransferSizes = TransferSizes.none, get: TransferSizes = TransferSizes.none, putFull: TransferSizes = TransferSizes.none, putPartial: TransferSizes = TransferSizes.none, hint: TransferSizes = TransferSizes.none ) extends TLCommonTransferSizes { def intersect(rhs: TLSlaveToMasterTransferSizes) = TLSlaveToMasterTransferSizes( probe = probe .intersect(rhs.probe), arithmetic = arithmetic.intersect(rhs.arithmetic), logical = logical .intersect(rhs.logical), get = get .intersect(rhs.get), putFull = putFull .intersect(rhs.putFull), putPartial = putPartial.intersect(rhs.putPartial), hint = hint .intersect(rhs.hint) ) def mincover(rhs: TLSlaveToMasterTransferSizes) = TLSlaveToMasterTransferSizes( probe = probe .mincover(rhs.probe), arithmetic = arithmetic.mincover(rhs.arithmetic), logical = logical .mincover(rhs.logical), get = get .mincover(rhs.get), putFull = putFull .mincover(rhs.putFull), putPartial = putPartial.mincover(rhs.putPartial), hint = hint .mincover(rhs.hint) ) // Reduce rendering to a simple yes/no per field override def toString = { def str(x: TransferSizes, flag: String) = if (x.none) "" else flag def flags = Vector( str(probe, "P"), str(arithmetic, "A"), str(logical, "L"), str(get, "G"), str(putFull, "F"), str(putPartial, "P"), str(hint, "H")) flags.mkString } // Prints out the actual information in a user readable way def infoString = { s"""probe = ${probe} \|arithmetic = ${arithmetic} \|logical = ${logical} \|get = ${get} \|putFull = ${putFull} \|putPartial = ${putPartial} \|hint = ${hint} \| \|""".stripMargin } } object TLSlaveToMasterTransferSizes { def unknownEmits = TLSlaveToMasterTransferSizes( arithmetic = TransferSizes(1, 4096), logical = TransferSizes(1, 4096), get = TransferSizes(1, 4096), putFull = TransferSizes(1, 4096), putPartial = TransferSizes(1, 4096), hint = TransferSizes(1, 4096), probe = TransferSizes(1, 4096)) def unknownSupports = TLSlaveToMasterTransferSizes() } trait TLCommonTransferSizes { def arithmetic: TransferSizes def logical: TransferSizes def get: TransferSizes def putFull: TransferSizes def putPartial: TransferSizes def hint: TransferSizes } class TLSlaveParameters private( val nodePath: Seq[BaseNode], val resources: Seq[Resource], setName: Option[String], val address: Seq[AddressSet], val regionType: RegionType.T, val executable: Boolean, val fifoId: Option[Int], val supports: TLMasterToSlaveTransferSizes, val emits: TLSlaveToMasterTransferSizes, // By default, slaves are forbidden from issuing 'denied' responses (it prevents Fragmentation) val alwaysGrantsT: Boolean, // typically only true for CacheCork'd read-write devices; dual: neverReleaseData // If fifoId=Some, all accesses sent to the same fifoId are executed and ACK'd in FIFO order // Note: you can only rely on this FIFO behaviour if your TLMasterParameters include requestFifo val mayDenyGet: Boolean, // applies to: AccessAckData, GrantData val mayDenyPut: Boolean) // applies to: AccessAck, Grant, HintAck // ReleaseAck may NEVER be denied extends SimpleProduct { def sortedAddress = address.sorted override def canEqual(that: Any): Boolean = that.isInstanceOf[TLSlaveParameters] override def productPrefix = "TLSlaveParameters" // We intentionally omit nodePath for equality testing / formatting def productArity: Int = 11 def productElement(n: Int): Any = n match { case 0 => name case 1 => address case 2 => resources case 3 => regionType case 4 => executable case 5 => fifoId case 6 => supports case 7 => emits case 8 => alwaysGrantsT case 9 => mayDenyGet case 10 => mayDenyPut case _ => throw new IndexOutOfBoundsException(n.toString) } def supportsAcquireT: TransferSizes = supports.acquireT def supportsAcquireB: TransferSizes = supports.acquireB def supportsArithmetic: TransferSizes = supports.arithmetic def supportsLogical: TransferSizes = supports.logical def supportsGet: TransferSizes = supports.get def supportsPutFull: TransferSizes = supports.putFull def supportsPutPartial: TransferSizes = supports.putPartial def supportsHint: TransferSizes = supports.hint require (!address.isEmpty, "Address cannot be empty") address.foreach { a => require (a.finite, "Address must be finite") } address.combinations(2).foreach { case Seq(x,y) => require (!x.overlaps(y), s"$x and $y overlap.") } require (supportsPutFull.contains(supportsPutPartial), s"PutFull($supportsPutFull) < PutPartial($supportsPutPartial)") require (supportsPutFull.contains(supportsArithmetic), s"PutFull($supportsPutFull) < Arithmetic($supportsArithmetic)") require (supportsPutFull.contains(supportsLogical), s"PutFull($supportsPutFull) < Logical($supportsLogical)") require (supportsGet.contains(supportsArithmetic), s"Get($supportsGet) < Arithmetic($supportsArithmetic)") require (supportsGet.contains(supportsLogical), s"Get($supportsGet) < Logical($supportsLogical)") require (supportsAcquireB.contains(supportsAcquireT), s"AcquireB($supportsAcquireB) < AcquireT($supportsAcquireT)") require (!alwaysGrantsT \|\| supportsAcquireT, s"Must supportAcquireT if promising to always grantT") // Make sure that the regionType agrees with the capabilities require (!supportsAcquireB \|\| regionType >= RegionType.UNCACHED) // acquire -> uncached, tracked, cached require (regionType <= RegionType.UNCACHED \|\| supportsAcquireB) // tracked, cached -> acquire require (regionType != RegionType.UNCACHED \|\| supportsGet) // uncached -> supportsGet val name = setName.orElse(nodePath.lastOption.map(_.lazyModule.name)).getOrElse("disconnected") val maxTransfer = List( // Largest supported transfer of all types supportsAcquireT.max, supportsAcquireB.max, supportsArithmetic.max, supportsLogical.max, supportsGet.max, supportsPutFull.max, supportsPutPartial.max).max val maxAddress = address.map(_.max).max val minAlignment = address.map(_.alignment).min // The device had better not support a transfer larger than its alignment require (minAlignment >= maxTransfer, s"Bad $address: minAlignment ($minAlignment) must be >= maxTransfer ($maxTransfer)") def toResource: ResourceAddress = { ResourceAddress(address, ResourcePermissions( r = supportsAcquireB \|\| supportsGet, w = supportsAcquireT \|\| supportsPutFull, x = executable, c = supportsAcquireB, a = supportsArithmetic && supportsLogical)) } def findTreeViolation() = nodePath.find { case _: MixedAdapterNode[_, _, _, _, _, _, _, _] => false case _: SinkNode[_, _, _, _, _] => false case node => node.inputs.size != 1 } def isTree = findTreeViolation() == None def infoString = { s"""Slave Name = ${name} \|Slave Address = ${address} \|supports = ${supports.infoString} \| \|""".stripMargin } def v1copy( address: Seq[AddressSet] = address, resources: Seq[Resource] = resources, regionType: RegionType.T = regionType, executable: Boolean = executable, nodePath: Seq[BaseNode] = nodePath, supportsAcquireT: TransferSizes = supports.acquireT, supportsAcquireB: TransferSizes = supports.acquireB, supportsArithmetic: TransferSizes = supports.arithmetic, supportsLogical: TransferSizes = supports.logical, supportsGet: TransferSizes = supports.get, supportsPutFull: TransferSizes = supports.putFull, supportsPutPartial: TransferSizes = supports.putPartial, supportsHint: TransferSizes = supports.hint, mayDenyGet: Boolean = mayDenyGet, mayDenyPut: Boolean = mayDenyPut, alwaysGrantsT: Boolean = alwaysGrantsT, fifoId: Option[Int] = fifoId) = { new TLSlaveParameters( setName = setName, address = address, resources = resources, regionType = regionType, executable = executable, nodePath = nodePath, supports = TLMasterToSlaveTransferSizes( acquireT = supportsAcquireT, acquireB = supportsAcquireB, arithmetic = supportsArithmetic, logical = supportsLogical, get = supportsGet, putFull = supportsPutFull, putPartial = supportsPutPartial, hint = supportsHint), emits = emits, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut, alwaysGrantsT = alwaysGrantsT, fifoId = fifoId) } def v2copy( nodePath: Seq[BaseNode] = nodePath, resources: Seq[Resource] = resources, name: Option[String] = setName, address: Seq[AddressSet] = address, regionType: RegionType.T = regionType, executable: Boolean = executable, fifoId: Option[Int] = fifoId, supports: TLMasterToSlaveTransferSizes = supports, emits: TLSlaveToMasterTransferSizes = emits, alwaysGrantsT: Boolean = alwaysGrantsT, mayDenyGet: Boolean = mayDenyGet, mayDenyPut: Boolean = mayDenyPut) = { new TLSlaveParameters( nodePath = nodePath, resources = resources, setName = name, address = address, regionType = regionType, executable = executable, fifoId = fifoId, supports = supports, emits = emits, alwaysGrantsT = alwaysGrantsT, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut) } @deprecated("Use v1copy instead of copy","") def copy( address: Seq[AddressSet] = address, resources: Seq[Resource] = resources, regionType: RegionType.T = regionType, executable: Boolean = executable, nodePath: Seq[BaseNode] = nodePath, supportsAcquireT: TransferSizes = supports.acquireT, supportsAcquireB: TransferSizes = supports.acquireB, supportsArithmetic: TransferSizes = supports.arithmetic, supportsLogical: TransferSizes = supports.logical, supportsGet: TransferSizes = supports.get, supportsPutFull: TransferSizes = supports.putFull, supportsPutPartial: TransferSizes = supports.putPartial, supportsHint: TransferSizes = supports.hint, mayDenyGet: Boolean = mayDenyGet, mayDenyPut: Boolean = mayDenyPut, alwaysGrantsT: Boolean = alwaysGrantsT, fifoId: Option[Int] = fifoId) = { v1copy( address = address, resources = resources, regionType = regionType, executable = executable, nodePath = nodePath, supportsAcquireT = supportsAcquireT, supportsAcquireB = supportsAcquireB, supportsArithmetic = supportsArithmetic, supportsLogical = supportsLogical, supportsGet = supportsGet, supportsPutFull = supportsPutFull, supportsPutPartial = supportsPutPartial, supportsHint = supportsHint, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut, alwaysGrantsT = alwaysGrantsT, fifoId = fifoId) } } object TLSlaveParameters { def v1( address: Seq[AddressSet], resources: Seq[Resource] = Seq(), regionType: RegionType.T = RegionType.GET_EFFECTS, executable: Boolean = false, nodePath: Seq[BaseNode] = Seq(), supportsAcquireT: TransferSizes = TransferSizes.none, supportsAcquireB: TransferSizes = TransferSizes.none, supportsArithmetic: TransferSizes = TransferSizes.none, supportsLogical: TransferSizes = TransferSizes.none, supportsGet: TransferSizes = TransferSizes.none, supportsPutFull: TransferSizes = TransferSizes.none, supportsPutPartial: TransferSizes = TransferSizes.none, supportsHint: TransferSizes = TransferSizes.none, mayDenyGet: Boolean = false, mayDenyPut: Boolean = false, alwaysGrantsT: Boolean = false, fifoId: Option[Int] = None) = { new TLSlaveParameters( setName = None, address = address, resources = resources, regionType = regionType, executable = executable, nodePath = nodePath, supports = TLMasterToSlaveTransferSizes( acquireT = supportsAcquireT, acquireB = supportsAcquireB, arithmetic = supportsArithmetic, logical = supportsLogical, get = supportsGet, putFull = supportsPutFull, putPartial = supportsPutPartial, hint = supportsHint), emits = TLSlaveToMasterTransferSizes.unknownEmits, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut, alwaysGrantsT = alwaysGrantsT, fifoId = fifoId) } def v2( address: Seq[AddressSet], nodePath: Seq[BaseNode] = Seq(), resources: Seq[Resource] = Seq(), name: Option[String] = None, regionType: RegionType.T = RegionType.GET_EFFECTS, executable: Boolean = false, fifoId: Option[Int] = None, supports: TLMasterToSlaveTransferSizes = TLMasterToSlaveTransferSizes.unknownSupports, emits: TLSlaveToMasterTransferSizes = TLSlaveToMasterTransferSizes.unknownEmits, alwaysGrantsT: Boolean = false, mayDenyGet: Boolean = false, mayDenyPut: Boolean = false) = { new TLSlaveParameters( nodePath = nodePath, resources = resources, setName = name, address = address, regionType = regionType, executable = executable, fifoId = fifoId, supports = supports, emits = emits, alwaysGrantsT = alwaysGrantsT, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut) } } object TLManagerParameters { @deprecated("Use TLSlaveParameters.v1 instead of TLManagerParameters","") def apply( address: Seq[AddressSet], resources: Seq[Resource] = Seq(), regionType: RegionType.T = RegionType.GET_EFFECTS, executable: Boolean = false, nodePath: Seq[BaseNode] = Seq(), supportsAcquireT: TransferSizes = TransferSizes.none, supportsAcquireB: TransferSizes = TransferSizes.none, supportsArithmetic: TransferSizes = TransferSizes.none, supportsLogical: TransferSizes = TransferSizes.none, supportsGet: TransferSizes = TransferSizes.none, supportsPutFull: TransferSizes = TransferSizes.none, supportsPutPartial: TransferSizes = TransferSizes.none, supportsHint: TransferSizes = TransferSizes.none, mayDenyGet: Boolean = false, mayDenyPut: Boolean = false, alwaysGrantsT: Boolean = false, fifoId: Option[Int] = None) = TLSlaveParameters.v1( address, resources, regionType, executable, nodePath, supportsAcquireT, supportsAcquireB, supportsArithmetic, supportsLogical, supportsGet, supportsPutFull, supportsPutPartial, supportsHint, mayDenyGet, mayDenyPut, alwaysGrantsT, fifoId, ) } case class TLChannelBeatBytes(a: Option[Int], b: Option[Int], c: Option[Int], d: Option[Int]) { def members = Seq(a, b, c, d) members.collect { case Some(beatBytes) => require (isPow2(beatBytes), "Data channel width must be a power of 2") } } object TLChannelBeatBytes{ def apply(beatBytes: Int): TLChannelBeatBytes = TLChannelBeatBytes( Some(beatBytes), Some(beatBytes), Some(beatBytes), Some(beatBytes)) def apply(): TLChannelBeatBytes = TLChannelBeatBytes( None, None, None, None) } class TLSlavePortParameters private( val slaves: Seq[TLSlaveParameters], val channelBytes: TLChannelBeatBytes, val endSinkId: Int, val minLatency: Int, val responseFields: Seq[BundleFieldBase], val requestKeys: Seq[BundleKeyBase]) extends SimpleProduct { def sortedSlaves = slaves.sortBy(_.sortedAddress.head) override def canEqual(that: Any): Boolean = that.isInstanceOf[TLSlavePortParameters] override def productPrefix = "TLSlavePortParameters" def productArity: Int = 6 def productElement(n: Int): Any = n match { case 0 => slaves case 1 => channelBytes case 2 => endSinkId case 3 => minLatency case 4 => responseFields case 5 => requestKeys case _ => throw new IndexOutOfBoundsException(n.toString) } require (!slaves.isEmpty, "Slave ports must have slaves") require (endSinkId >= 0, "Sink ids cannot be negative") require (minLatency >= 0, "Minimum required latency cannot be negative") // Using this API implies you cannot handle mixed-width busses def beatBytes = { channelBytes.members.foreach { width => require (width.isDefined && width == channelBytes.a) } channelBytes.a.get } // TODO this should be deprecated def managers = slaves def requireFifo(policy: TLFIFOFixer.Policy = TLFIFOFixer.allFIFO) = { val relevant = slaves.filter(m => policy(m)) relevant.foreach { m => require(m.fifoId == relevant.head.fifoId, s"${m.name} had fifoId ${m.fifoId}, which was not homogeneous (${slaves.map(s => (s.name, s.fifoId))}) ") } } // Bounds on required sizes def maxAddress = slaves.map(_.maxAddress).max def maxTransfer = slaves.map(_.maxTransfer).max def mayDenyGet = slaves.exists(_.mayDenyGet) def mayDenyPut = slaves.exists(_.mayDenyPut) // Diplomatically determined operation sizes emitted by all outward Slaves // as opposed to emits* which generate circuitry to check which specific addresses val allEmitClaims = slaves.map(_.emits).reduce( _ intersect _) // Operation Emitted by at least one outward Slaves // as opposed to emits* which generate circuitry to check which specific addresses val anyEmitClaims = slaves.map(_.emits).reduce(_ mincover _) // Diplomatically determined operation sizes supported by all outward Slaves // as opposed to supports* which generate circuitry to check which specific addresses val allSupportClaims = slaves.map(_.supports).reduce( _ intersect _) val allSupportAcquireT = allSupportClaims.acquireT val allSupportAcquireB = allSupportClaims.acquireB val allSupportArithmetic = allSupportClaims.arithmetic val allSupportLogical = allSupportClaims.logical val allSupportGet = allSupportClaims.get val allSupportPutFull = allSupportClaims.putFull val allSupportPutPartial = allSupportClaims.putPartial val allSupportHint = allSupportClaims.hint // Operation supported by at least one outward Slaves // as opposed to supports* which generate circuitry to check which specific addresses val anySupportClaims = slaves.map(_.supports).reduce(_ mincover _) val anySupportAcquireT = !anySupportClaims.acquireT.none val anySupportAcquireB = !anySupportClaims.acquireB.none val anySupportArithmetic = !anySupportClaims.arithmetic.none val anySupportLogical = !anySupportClaims.logical.none val anySupportGet = !anySupportClaims.get.none val anySupportPutFull = !anySupportClaims.putFull.none val anySupportPutPartial = !anySupportClaims.putPartial.none val anySupportHint = !anySupportClaims.hint.none // Supporting Acquire means being routable for GrantAck require ((endSinkId == 0) == !anySupportAcquireB) // These return Option[TLSlaveParameters] for your convenience def find(address: BigInt) = slaves.find(_.address.exists(_.contains(address))) // The safe version will check the entire address def findSafe(address: UInt) = VecInit(sortedSlaves.map(_.address.map(_.contains(address)).reduce(_ \|\| _))) // The fast version assumes the address is valid (you probably want fastProperty instead of this function) def findFast(address: UInt) = { val routingMask = AddressDecoder(slaves.map(_.address)) VecInit(sortedSlaves.map(_.address.map(_.widen(~routingMask)).distinct.map(_.contains(address)).reduce(_ \|\| _))) } // Compute the simplest AddressSets that decide a key def fastPropertyGroup[K](p: TLSlaveParameters => K): Seq[(K, Seq[AddressSet])] = { val groups = groupByIntoSeq(sortedSlaves.map(m => (p(m), m.address)))( _._1).map { case (k, vs) => k -> vs.flatMap(_._2) } val reductionMask = AddressDecoder(groups.map(_._2)) groups.map { case (k, seq) => k -> AddressSet.unify(seq.map(_.widen(~reductionMask)).distinct) } } // Select a property def fastProperty[K, D <: Data](address: UInt, p: TLSlaveParameters => K, d: K => D): D = Mux1H(fastPropertyGroup(p).map { case (v, a) => (a.map(_.contains(address)).reduce(_\|\|_), d(v)) }) // Note: returns the actual fifoId + 1 or 0 if None def findFifoIdFast(address: UInt) = fastProperty(address, _.fifoId.map(_+1).getOrElse(0), (i:Int) => i.U) def hasFifoIdFast(address: UInt) = fastProperty(address, _.fifoId.isDefined, (b:Boolean) => b.B) // Does this Port manage this ID/address? def containsSafe(address: UInt) = findSafe(address).reduce(_ \|\| _) private def addressHelper( // setting safe to false indicates that all addresses are expected to be legal, which might reduce circuit complexity safe: Boolean, // member filters out the sizes being checked based on the opcode being emitted or supported member: TLSlaveParameters => TransferSizes, address: UInt, lgSize: UInt, // range provides a limit on the sizes that are expected to be evaluated, which might reduce circuit complexity range: Option[TransferSizes]): Bool = { // trim reduces circuit complexity by intersecting checked sizes with the range argument def trim(x: TransferSizes) = range.map(_.intersect(x)).getOrElse(x) // groupBy returns an unordered map, convert back to Seq and sort the result for determinism // groupByIntoSeq is turning slaves into trimmed membership sizes // We are grouping all the slaves by their transfer size where // if they support the trimmed size then // member is the type of transfer that you are looking for (What you are trying to filter on) // When you consider membership, you are trimming the sizes to only the ones that you care about // you are filtering the slaves based on both whether they support a particular opcode and the size // Grouping the slaves based on the actual transfer size range they support // intersecting the range and checking their membership // FOR SUPPORTCASES instead of returning the list of slaves, // you are returning a map from transfer size to the set of // address sets that are supported for that transfer size // find all the slaves that support a certain type of operation and then group their addresses by the supported size // for every size there could be multiple address ranges // safety is a trade off between checking between all possible addresses vs only the addresses // that are known to have supported sizes // the trade off is 'checking all addresses is a more expensive circuit but will always give you // the right answer even if you give it an illegal address' // the not safe version is a cheaper circuit but if you give it an illegal address then it might produce the wrong answer // fast presumes address legality // This groupByIntoSeq deterministically groups all address sets for which a given `member` transfer size applies. // In the resulting Map of cases, the keys are transfer sizes and the values are all address sets which emit or support that size. val supportCases = groupByIntoSeq(slaves)(m => trim(member(m))).map { case (k: TransferSizes, vs: Seq[TLSlaveParameters]) => k -> vs.flatMap(_.address) } // safe produces a circuit that compares against all possible addresses, // whereas fast presumes that the address is legal but uses an efficient address decoder val mask = if (safe) ~BigInt(0) else AddressDecoder(supportCases.map(_._2)) // Simplified creates the most concise possible representation of each cases' address sets based on the mask. val simplified = supportCases.map { case (k, seq) => k -> AddressSet.unify(seq.map(_.widen(~mask)).distinct) } simplified.map { case (s, a) => // s is a size, you are checking for this size either the size of the operation is in s // We return an or-reduction of all the cases, checking whether any contains both the dynamic size and dynamic address on the wire. ((Some(s) == range).B \|\| s.containsLg(lgSize)) && a.map(_.contains(address)).reduce(_\|\|_) }.foldLeft(false.B)(_\|\|_) } def supportsAcquireTSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.acquireT, address, lgSize, range) def supportsAcquireBSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.acquireB, address, lgSize, range) def supportsArithmeticSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.arithmetic, address, lgSize, range) def supportsLogicalSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.logical, address, lgSize, range) def supportsGetSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.get, address, lgSize, range) def supportsPutFullSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.putFull, address, lgSize, range) def supportsPutPartialSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.putPartial, address, lgSize, range) def supportsHintSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.hint, address, lgSize, range) def supportsAcquireTFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.acquireT, address, lgSize, range) def supportsAcquireBFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.acquireB, address, lgSize, range) def supportsArithmeticFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.arithmetic, address, lgSize, range) def supportsLogicalFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.logical, address, lgSize, range) def supportsGetFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.get, address, lgSize, range) def supportsPutFullFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.putFull, address, lgSize, range) def supportsPutPartialFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.putPartial, address, lgSize, range) def supportsHintFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.hint, address, lgSize, range) def emitsProbeSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.probe, address, lgSize, range) def emitsArithmeticSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.arithmetic, address, lgSize, range) def emitsLogicalSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.logical, address, lgSize, range) def emitsGetSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.get, address, lgSize, range) def emitsPutFullSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.putFull, address, lgSize, range) def emitsPutPartialSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.putPartial, address, lgSize, range) def emitsHintSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.hint, address, lgSize, range) def findTreeViolation() = slaves.flatMap(_.findTreeViolation()).headOption def isTree = !slaves.exists(!_.isTree) def infoString = "Slave Port Beatbytes = " + beatBytes + "\n" + "Slave Port MinLatency = " + minLatency + "\n\n" + slaves.map(_.infoString).mkString def v1copy( managers: Seq[TLSlaveParameters] = slaves, beatBytes: Int = -1, endSinkId: Int = endSinkId, minLatency: Int = minLatency, responseFields: Seq[BundleFieldBase] = responseFields, requestKeys: Seq[BundleKeyBase] = requestKeys) = { new TLSlavePortParameters( slaves = managers, channelBytes = if (beatBytes != -1) TLChannelBeatBytes(beatBytes) else channelBytes, endSinkId = endSinkId, minLatency = minLatency, responseFields = responseFields, requestKeys = requestKeys) } def v2copy( slaves: Seq[TLSlaveParameters] = slaves, channelBytes: TLChannelBeatBytes = channelBytes, endSinkId: Int = endSinkId, minLatency: Int = minLatency, responseFields: Seq[BundleFieldBase] = responseFields, requestKeys: Seq[BundleKeyBase] = requestKeys) = { new TLSlavePortParameters( slaves = slaves, channelBytes = channelBytes, endSinkId = endSinkId, minLatency = minLatency, responseFields = responseFields, requestKeys = requestKeys) } @deprecated("Use v1copy instead of copy","") def copy( managers: Seq[TLSlaveParameters] = slaves, beatBytes: Int = -1, endSinkId: Int = endSinkId, minLatency: Int = minLatency, responseFields: Seq[BundleFieldBase] = responseFields, requestKeys: Seq[BundleKeyBase] = requestKeys) = { v1copy( managers, beatBytes, endSinkId, minLatency, responseFields, requestKeys) } } object TLSlavePortParameters { def v1( managers: Seq[TLSlaveParameters], beatBytes: Int, endSinkId: Int = 0, minLatency: Int = 0, responseFields: Seq[BundleFieldBase] = Nil, requestKeys: Seq[BundleKeyBase] = Nil) = { new TLSlavePortParameters( slaves = managers, channelBytes = TLChannelBeatBytes(beatBytes), endSinkId = endSinkId, minLatency = minLatency, responseFields = responseFields, requestKeys = requestKeys) } } object TLManagerPortParameters { @deprecated("Use TLSlavePortParameters.v1 instead of TLManagerPortParameters","") def apply( managers: Seq[TLSlaveParameters], beatBytes: Int, endSinkId: Int = 0, minLatency: Int = 0, responseFields: Seq[BundleFieldBase] = Nil, requestKeys: Seq[BundleKeyBase] = Nil) = { TLSlavePortParameters.v1( managers, beatBytes, endSinkId, minLatency, responseFields, requestKeys) } } class TLMasterParameters private( val nodePath: Seq[BaseNode], val resources: Seq[Resource], val name: String, val visibility: Seq[AddressSet], val unusedRegionTypes: Set[RegionType.T], val executesOnly: Boolean, val requestFifo: Boolean, // only a request, not a requirement. applies to A, not C. val supports: TLSlaveToMasterTransferSizes, val emits: TLMasterToSlaveTransferSizes, val neverReleasesData: Boolean, val sourceId: IdRange) extends SimpleProduct { override def canEqual(that: Any): Boolean = that.isInstanceOf[TLMasterParameters] override def productPrefix = "TLMasterParameters" // We intentionally omit nodePath for equality testing / formatting def productArity: Int = 10 def productElement(n: Int): Any = n match { case 0 => name case 1 => sourceId case 2 => resources case 3 => visibility case 4 => unusedRegionTypes case 5 => executesOnly case 6 => requestFifo case 7 => supports case 8 => emits case 9 => neverReleasesData case _ => throw new IndexOutOfBoundsException(n.toString) } require (!sourceId.isEmpty) require (!visibility.isEmpty) require (supports.putFull.contains(supports.putPartial)) // We only support these operations if we support Probe (ie: we're a cache) require (supports.probe.contains(supports.arithmetic)) require (supports.probe.contains(supports.logical)) require (supports.probe.contains(supports.get)) require (supports.probe.contains(supports.putFull)) require (supports.probe.contains(supports.putPartial)) require (supports.probe.contains(supports.hint)) visibility.combinations(2).foreach { case Seq(x,y) => require (!x.overlaps(y), s"$x and $y overlap.") } val maxTransfer = List( supports.probe.max, supports.arithmetic.max, supports.logical.max, supports.get.max, supports.putFull.max, supports.putPartial.max).max def infoString = { s"""Master Name = ${name} \|visibility = ${visibility} \|emits = ${emits.infoString} \|sourceId = ${sourceId} \| \|""".stripMargin } def v1copy( name: String = name, sourceId: IdRange = sourceId, nodePath: Seq[BaseNode] = nodePath, requestFifo: Boolean = requestFifo, visibility: Seq[AddressSet] = visibility, supportsProbe: TransferSizes = supports.probe, supportsArithmetic: TransferSizes = supports.arithmetic, supportsLogical: TransferSizes = supports.logical, supportsGet: TransferSizes = supports.get, supportsPutFull: TransferSizes = supports.putFull, supportsPutPartial: TransferSizes = supports.putPartial, supportsHint: TransferSizes = supports.hint) = { new TLMasterParameters( nodePath = nodePath, resources = this.resources, name = name, visibility = visibility, unusedRegionTypes = this.unusedRegionTypes, executesOnly = this.executesOnly, requestFifo = requestFifo, supports = TLSlaveToMasterTransferSizes( probe = supportsProbe, arithmetic = supportsArithmetic, logical = supportsLogical, get = supportsGet, putFull = supportsPutFull, putPartial = supportsPutPartial, hint = supportsHint), emits = this.emits, neverReleasesData = this.neverReleasesData, sourceId = sourceId) } def v2copy( nodePath: Seq[BaseNode] = nodePath, resources: Seq[Resource] = resources, name: String = name, visibility: Seq[AddressSet] = visibility, unusedRegionTypes: Set[RegionType.T] = unusedRegionTypes, executesOnly: Boolean = executesOnly, requestFifo: Boolean = requestFifo, supports: TLSlaveToMasterTransferSizes = supports, emits: TLMasterToSlaveTransferSizes = emits, neverReleasesData: Boolean = neverReleasesData, sourceId: IdRange = sourceId) = { new TLMasterParameters( nodePath = nodePath, resources = resources, name = name, visibility = visibility, unusedRegionTypes = unusedRegionTypes, executesOnly = executesOnly, requestFifo = requestFifo, supports = supports, emits = emits, neverReleasesData = neverReleasesData, sourceId = sourceId) } @deprecated("Use v1copy instead of copy","") def copy( name: String = name, sourceId: IdRange = sourceId, nodePath: Seq[BaseNode] = nodePath, requestFifo: Boolean = requestFifo, visibility: Seq[AddressSet] = visibility, supportsProbe: TransferSizes = supports.probe, supportsArithmetic: TransferSizes = supports.arithmetic, supportsLogical: TransferSizes = supports.logical, supportsGet: TransferSizes = supports.get, supportsPutFull: TransferSizes = supports.putFull, supportsPutPartial: TransferSizes = supports.putPartial, supportsHint: TransferSizes = supports.hint) = { v1copy( name = name, sourceId = sourceId, nodePath = nodePath, requestFifo = requestFifo, visibility = visibility, supportsProbe = supportsProbe, supportsArithmetic = supportsArithmetic, supportsLogical = supportsLogical, supportsGet = supportsGet, supportsPutFull = supportsPutFull, supportsPutPartial = supportsPutPartial, supportsHint = supportsHint) } } object TLMasterParameters { def v1( name: String, sourceId: IdRange = IdRange(0,1), nodePath: Seq[BaseNode] = Seq(), requestFifo: Boolean = false, visibility: Seq[AddressSet] = Seq(AddressSet(0, ~0)), supportsProbe: TransferSizes = TransferSizes.none, supportsArithmetic: TransferSizes = TransferSizes.none, supportsLogical: TransferSizes = TransferSizes.none, supportsGet: TransferSizes = TransferSizes.none, supportsPutFull: TransferSizes = TransferSizes.none, supportsPutPartial: TransferSizes = TransferSizes.none, supportsHint: TransferSizes = TransferSizes.none) = { new TLMasterParameters( nodePath = nodePath, resources = Nil, name = name, visibility = visibility, unusedRegionTypes = Set(), executesOnly = false, requestFifo = requestFifo, supports = TLSlaveToMasterTransferSizes( probe = supportsProbe, arithmetic = supportsArithmetic, logical = supportsLogical, get = supportsGet, putFull = supportsPutFull, putPartial = supportsPutPartial, hint = supportsHint), emits = TLMasterToSlaveTransferSizes.unknownEmits, neverReleasesData = false, sourceId = sourceId) } def v2( nodePath: Seq[BaseNode] = Seq(), resources: Seq[Resource] = Nil, name: String, visibility: Seq[AddressSet] = Seq(AddressSet(0, ~0)), unusedRegionTypes: Set[RegionType.T] = Set(), executesOnly: Boolean = false, requestFifo: Boolean = false, supports: TLSlaveToMasterTransferSizes = TLSlaveToMasterTransferSizes.unknownSupports, emits: TLMasterToSlaveTransferSizes = TLMasterToSlaveTransferSizes.unknownEmits, neverReleasesData: Boolean = false, sourceId: IdRange = IdRange(0,1)) = { new TLMasterParameters( nodePath = nodePath, resources = resources, name = name, visibility = visibility, unusedRegionTypes = unusedRegionTypes, executesOnly = executesOnly, requestFifo = requestFifo, supports = supports, emits = emits, neverReleasesData = neverReleasesData, sourceId = sourceId) } } object TLClientParameters { @deprecated("Use TLMasterParameters.v1 instead of TLClientParameters","") def apply( name: String, sourceId: IdRange = IdRange(0,1), nodePath: Seq[BaseNode] = Seq(), requestFifo: Boolean = false, visibility: Seq[AddressSet] = Seq(AddressSet.everything), supportsProbe: TransferSizes = TransferSizes.none, supportsArithmetic: TransferSizes = TransferSizes.none, supportsLogical: TransferSizes = TransferSizes.none, supportsGet: TransferSizes = TransferSizes.none, supportsPutFull: TransferSizes = TransferSizes.none, supportsPutPartial: TransferSizes = TransferSizes.none, supportsHint: TransferSizes = TransferSizes.none) = { TLMasterParameters.v1( name = name, sourceId = sourceId, nodePath = nodePath, requestFifo = requestFifo, visibility = visibility, supportsProbe = supportsProbe, supportsArithmetic = supportsArithmetic, supportsLogical = supportsLogical, supportsGet = supportsGet, supportsPutFull = supportsPutFull, supportsPutPartial = supportsPutPartial, supportsHint = supportsHint) } } class TLMasterPortParameters private( val masters: Seq[TLMasterParameters], val channelBytes: TLChannelBeatBytes, val minLatency: Int, val echoFields: Seq[BundleFieldBase], val requestFields: Seq[BundleFieldBase], val responseKeys: Seq[BundleKeyBase]) extends SimpleProduct { override def canEqual(that: Any): Boolean = that.isInstanceOf[TLMasterPortParameters] override def productPrefix = "TLMasterPortParameters" def productArity: Int = 6 def productElement(n: Int): Any = n match { case 0 => masters case 1 => channelBytes case 2 => minLatency case 3 => echoFields case 4 => requestFields case 5 => responseKeys case _ => throw new IndexOutOfBoundsException(n.toString) } require (!masters.isEmpty) require (minLatency >= 0) def clients = masters // Require disjoint ranges for Ids IdRange.overlaps(masters.map(_.sourceId)).foreach { case (x, y) => require (!x.overlaps(y), s"TLClientParameters.sourceId ${x} overlaps ${y}") } // Bounds on required sizes def endSourceId = masters.map(_.sourceId.end).max def maxTransfer = masters.map(_.maxTransfer).max // The unused sources < endSourceId def unusedSources: Seq[Int] = { val usedSources = masters.map(_.sourceId).sortBy(_.start) ((Seq(0) ++ usedSources.map(_.end)) zip usedSources.map(_.start)) flatMap { case (end, start) => end until start } } // Diplomatically determined operation sizes emitted by all inward Masters // as opposed to emits* which generate circuitry to check which specific addresses val allEmitClaims = masters.map(_.emits).reduce( _ intersect _) // Diplomatically determined operation sizes Emitted by at least one inward Masters // as opposed to emits* which generate circuitry to check which specific addresses val anyEmitClaims = masters.map(_.emits).reduce(_ mincover _) // Diplomatically determined operation sizes supported by all inward Masters // as opposed to supports* which generate circuitry to check which specific addresses val allSupportProbe = masters.map(_.supports.probe) .reduce(_ intersect _) val allSupportArithmetic = masters.map(_.supports.arithmetic).reduce(_ intersect _) val allSupportLogical = masters.map(_.supports.logical) .reduce(_ intersect _) val allSupportGet = masters.map(_.supports.get) .reduce(_ intersect _) val allSupportPutFull = masters.map(_.supports.putFull) .reduce(_ intersect _) val allSupportPutPartial = masters.map(_.supports.putPartial).reduce(_ intersect _) val allSupportHint = masters.map(_.supports.hint) .reduce(_ intersect _) // Diplomatically determined operation sizes supported by at least one master // as opposed to supports* which generate circuitry to check which specific addresses val anySupportProbe = masters.map(!_.supports.probe.none) .reduce(_ \|\| _) val anySupportArithmetic = masters.map(!_.supports.arithmetic.none).reduce(_ \|\| _) val anySupportLogical = masters.map(!_.supports.logical.none) .reduce(_ \|\| _) val anySupportGet = masters.map(!_.supports.get.none) .reduce(_ \|\| _) val anySupportPutFull = masters.map(!_.supports.putFull.none) .reduce(_ \|\| _) val anySupportPutPartial = masters.map(!_.supports.putPartial.none).reduce(_ \|\| _) val anySupportHint = masters.map(!_.supports.hint.none) .reduce(_ \|\| _) // These return Option[TLMasterParameters] for your convenience def find(id: Int) = masters.find(_.sourceId.contains(id)) // Synthesizable lookup methods def find(id: UInt) = VecInit(masters.map(_.sourceId.contains(id))) def contains(id: UInt) = find(id).reduce(_ \|\| _) def requestFifo(id: UInt) = Mux1H(find(id), masters.map(c => c.requestFifo.B)) // Available during RTL runtime, checks to see if (id, size) is supported by the master's (client's) diplomatic parameters private def sourceIdHelper(member: TLMasterParameters => TransferSizes)(id: UInt, lgSize: UInt) = { val allSame = masters.map(member(_) == member(masters(0))).reduce(_ && _) // this if statement is a coarse generalization of the groupBy in the sourceIdHelper2 version; // the case where there is only one group. if (allSame) member(masters(0)).containsLg(lgSize) else { // Find the master associated with ID and returns whether that particular master is able to receive transaction of lgSize Mux1H(find(id), masters.map(member(_).containsLg(lgSize))) } } // Check for support of a given operation at a specific id val supportsProbe = sourceIdHelper(_.supports.probe) _ val supportsArithmetic = sourceIdHelper(_.supports.arithmetic) _ val supportsLogical = sourceIdHelper(_.supports.logical) _ val supportsGet = sourceIdHelper(_.supports.get) _ val supportsPutFull = sourceIdHelper(_.supports.putFull) _ val supportsPutPartial = sourceIdHelper(_.supports.putPartial) _ val supportsHint = sourceIdHelper(_.supports.hint) _ // TODO: Merge sourceIdHelper2 with sourceIdHelper private def sourceIdHelper2( member: TLMasterParameters => TransferSizes, sourceId: UInt, lgSize: UInt): Bool = { // Because sourceIds are uniquely owned by each master, we use them to group the // cases that have to be checked. val emitCases = groupByIntoSeq(masters)(m => member(m)).map { case (k, vs) => k -> vs.map(_.sourceId) } emitCases.map { case (s, a) => (s.containsLg(lgSize)) && a.map(_.contains(sourceId)).reduce(_\|\|_) }.foldLeft(false.B)(_\|\|_) } // Check for emit of a given operation at a specific id def emitsAcquireT (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.acquireT, sourceId, lgSize) def emitsAcquireB (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.acquireB, sourceId, lgSize) def emitsArithmetic(sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.arithmetic, sourceId, lgSize) def emitsLogical (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.logical, sourceId, lgSize) def emitsGet (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.get, sourceId, lgSize) def emitsPutFull (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.putFull, sourceId, lgSize) def emitsPutPartial(sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.putPartial, sourceId, lgSize) def emitsHint (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.hint, sourceId, lgSize) def infoString = masters.map(_.infoString).mkString def v1copy( clients: Seq[TLMasterParameters] = masters, minLatency: Int = minLatency, echoFields: Seq[BundleFieldBase] = echoFields, requestFields: Seq[BundleFieldBase] = requestFields, responseKeys: Seq[BundleKeyBase] = responseKeys) = { new TLMasterPortParameters( masters = clients, channelBytes = channelBytes, minLatency = minLatency, echoFields = echoFields, requestFields = requestFields, responseKeys = responseKeys) } def v2copy( masters: Seq[TLMasterParameters] = masters, channelBytes: TLChannelBeatBytes = channelBytes, minLatency: Int = minLatency, echoFields: Seq[BundleFieldBase] = echoFields, requestFields: Seq[BundleFieldBase] = requestFields, responseKeys: Seq[BundleKeyBase] = responseKeys) = { new TLMasterPortParameters( masters = masters, channelBytes = channelBytes, minLatency = minLatency, echoFields = echoFields, requestFields = requestFields, responseKeys = responseKeys) } @deprecated("Use v1copy instead of copy","") def copy( clients: Seq[TLMasterParameters] = masters, minLatency: Int = minLatency, echoFields: Seq[BundleFieldBase] = echoFields, requestFields: Seq[BundleFieldBase] = requestFields, responseKeys: Seq[BundleKeyBase] = responseKeys) = { v1copy( clients, minLatency, echoFields, requestFields, responseKeys) } } object TLClientPortParameters { @deprecated("Use TLMasterPortParameters.v1 instead of TLClientPortParameters","") def apply( clients: Seq[TLMasterParameters], minLatency: Int = 0, echoFields: Seq[BundleFieldBase] = Nil, requestFields: Seq[BundleFieldBase] = Nil, responseKeys: Seq[BundleKeyBase] = Nil) = { TLMasterPortParameters.v1( clients, minLatency, echoFields, requestFields, responseKeys) } } object TLMasterPortParameters { def v1( clients: Seq[TLMasterParameters], minLatency: Int = 0, echoFields: Seq[BundleFieldBase] = Nil, requestFields: Seq[BundleFieldBase] = Nil, responseKeys: Seq[BundleKeyBase] = Nil) = { new TLMasterPortParameters( masters = clients, channelBytes = TLChannelBeatBytes(), minLatency = minLatency, echoFields = echoFields, requestFields = requestFields, responseKeys = responseKeys) } def v2( masters: Seq[TLMasterParameters], channelBytes: TLChannelBeatBytes = TLChannelBeatBytes(), minLatency: Int = 0, echoFields: Seq[BundleFieldBase] = Nil, requestFields: Seq[BundleFieldBase] = Nil, responseKeys: Seq[BundleKeyBase] = Nil) = { new TLMasterPortParameters( masters = masters, channelBytes = channelBytes, minLatency = minLatency, echoFields = echoFields, requestFields = requestFields, responseKeys = responseKeys) } } case class TLBundleParameters( addressBits: Int, dataBits: Int, sourceBits: Int, sinkBits: Int, sizeBits: Int, echoFields: Seq[BundleFieldBase], requestFields: Seq[BundleFieldBase], responseFields: Seq[BundleFieldBase], hasBCE: Boolean) { // Chisel has issues with 0-width wires require (addressBits >= 1) require (dataBits >= 8) require (sourceBits >= 1) require (sinkBits >= 1) require (sizeBits >= 1) require (isPow2(dataBits)) echoFields.foreach { f => require (f.key.isControl, s"${f} is not a legal echo field") } val addrLoBits = log2Up(dataBits/8) // Used to uniquify bus IP names def shortName = s"a${addressBits}d${dataBits}s${sourceBits}k${sinkBits}z${sizeBits}" + (if (hasBCE) "c" else "u") def union(x: TLBundleParameters) = TLBundleParameters( max(addressBits, x.addressBits), max(dataBits, x.dataBits), max(sourceBits, x.sourceBits), max(sinkBits, x.sinkBits), max(sizeBits, x.sizeBits), echoFields = BundleField.union(echoFields ++ x.echoFields), requestFields = BundleField.union(requestFields ++ x.requestFields), responseFields = BundleField.union(responseFields ++ x.responseFields), hasBCE \|\| x.hasBCE) } object TLBundleParameters { val emptyBundleParams = TLBundleParameters( addressBits = 1, dataBits = 8, sourceBits = 1, sinkBits = 1, sizeBits = 1, echoFields = Nil, requestFields = Nil, responseFields = Nil, hasBCE = false) def union(x: Seq[TLBundleParameters]) = x.foldLeft(emptyBundleParams)((x,y) => x.union(y)) def apply(master: TLMasterPortParameters, slave: TLSlavePortParameters) = new TLBundleParameters( addressBits = log2Up(slave.maxAddress + 1), dataBits = slave.beatBytes * 8, sourceBits = log2Up(master.endSourceId), sinkBits = log2Up(slave.endSinkId), sizeBits = log2Up(log2Ceil(max(master.maxTransfer, slave.maxTransfer))+1), echoFields = master.echoFields, requestFields = BundleField.accept(master.requestFields, slave.requestKeys), responseFields = BundleField.accept(slave.responseFields, master.responseKeys), hasBCE = master.anySupportProbe && slave.anySupportAcquireB) } case class TLEdgeParameters( master: TLMasterPortParameters, slave: TLSlavePortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge { // legacy names: def manager = slave def client = master val maxTransfer = max(master.maxTransfer, slave.maxTransfer) val maxLgSize = log2Ceil(maxTransfer) // Sanity check the link... require (maxTransfer >= slave.beatBytes, s"Link's max transfer (${maxTransfer}) < ${slave.slaves.map(_.name)}'s beatBytes (${slave.beatBytes})") def diplomaticClaimsMasterToSlave = master.anyEmitClaims.intersect(slave.anySupportClaims) val bundle = TLBundleParameters(master, slave) def formatEdge = master.infoString + "\n" + slave.infoString } case class TLCreditedDelay( a: CreditedDelay, b: CreditedDelay, c: CreditedDelay, d: CreditedDelay, e: CreditedDelay) { def + (that: TLCreditedDelay): TLCreditedDelay = TLCreditedDelay( a = a + that.a, b = b + that.b, c = c + that.c, d = d + that.d, e = e + that.e) override def toString = s"(${a}, ${b}, ${c}, ${d}, ${e})" } object TLCreditedDelay { def apply(delay: CreditedDelay): TLCreditedDelay = apply(delay, delay.flip, delay, delay.flip, delay) } case class TLCreditedManagerPortParameters(delay: TLCreditedDelay, base: TLSlavePortParameters) {def infoString = base.infoString} case class TLCreditedClientPortParameters(delay: TLCreditedDelay, base: TLMasterPortParameters) {def infoString = base.infoString} case class TLCreditedEdgeParameters(client: TLCreditedClientPortParameters, manager: TLCreditedManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge { val delay = client.delay + manager.delay val bundle = TLBundleParameters(client.base, manager.base) def formatEdge = client.infoString + "\n" + manager.infoString } case class TLAsyncManagerPortParameters(async: AsyncQueueParams, base: TLSlavePortParameters) {def infoString = base.infoString} case class TLAsyncClientPortParameters(base: TLMasterPortParameters) {def infoString = base.infoString} case class TLAsyncBundleParameters(async: AsyncQueueParams, base: TLBundleParameters) case class TLAsyncEdgeParameters(client: TLAsyncClientPortParameters, manager: TLAsyncManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge { val bundle = TLAsyncBundleParameters(manager.async, TLBundleParameters(client.base, manager.base)) def formatEdge = client.infoString + "\n" + manager.infoString } case class TLRationalManagerPortParameters(direction: RationalDirection, base: TLSlavePortParameters) {def infoString = base.infoString} case class TLRationalClientPortParameters(base: TLMasterPortParameters) {def infoString = base.infoString} case class TLRationalEdgeParameters(client: TLRationalClientPortParameters, manager: TLRationalManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge { val bundle = TLBundleParameters(client.base, manager.base) def formatEdge = client.infoString + "\n" + manager.infoString } // To be unified, devices must agree on all of these terms case class ManagerUnificationKey( resources: Seq[Resource], regionType: RegionType.T, executable: Boolean, supportsAcquireT: TransferSizes, supportsAcquireB: TransferSizes, supportsArithmetic: TransferSizes, supportsLogical: TransferSizes, supportsGet: TransferSizes, supportsPutFull: TransferSizes, supportsPutPartial: TransferSizes, supportsHint: TransferSizes) object ManagerUnificationKey { def apply(x: TLSlaveParameters): ManagerUnificationKey = ManagerUnificationKey( resources = x.resources, regionType = x.regionType, executable = x.executable, supportsAcquireT = x.supportsAcquireT, supportsAcquireB = x.supportsAcquireB, supportsArithmetic = x.supportsArithmetic, supportsLogical = x.supportsLogical, supportsGet = x.supportsGet, supportsPutFull = x.supportsPutFull, supportsPutPartial = x.supportsPutPartial, supportsHint = x.supportsHint) } object ManagerUnification { def apply(slaves: Seq[TLSlaveParameters]): List[TLSlaveParameters] = { slaves.groupBy(ManagerUnificationKey.apply).values.map { seq => val agree = seq.forall(_.fifoId == seq.head.fifoId) seq(0).v1copy( address = AddressSet.unify(seq.flatMap(_.address)), fifoId = if (agree) seq(0).fifoId else None) }.toList } } case class TLBufferParams( a: BufferParams = BufferParams.none, b: BufferParams = BufferParams.none, c: BufferParams = BufferParams.none, d: BufferParams = BufferParams.none, e: BufferParams = BufferParams.none ) extends DirectedBuffers[TLBufferParams] { def copyIn(x: BufferParams) = this.copy(b = x, d = x) def copyOut(x: BufferParams) = this.copy(a = x, c = x, e = x) def copyInOut(x: BufferParams) = this.copyIn(x).copyOut(x) } /** Pretty printing of TL source id maps / class TLSourceIdMap(tl: TLMasterPortParameters) extends IdMap[TLSourceIdMapEntry] { private val tlDigits = String.valueOf(tl.endSourceId-1).length() protected val fmt = s"\t[%${tlDigits}d, %${tlDigits}d) %s%s%s" private val sorted = tl.masters.sortBy(_.sourceId) val mapping: Seq[TLSourceIdMapEntry] = sorted.map { case c => TLSourceIdMapEntry(c.sourceId, c.name, c.supports.probe, c.requestFifo) } } case class TLSourceIdMapEntry(tlId: IdRange, name: String, isCache: Boolean, requestFifo: Boolean) extends IdMapEntry { val from = tlId val to = tlId val maxTransactionsInFlight = Some(tlId.size) } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportPutFull \|\| manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB \|\| manager.anySupportGet \|\| manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportPutFull \|\| client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe \|\| client.anySupportGet \|\| client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet \|\| client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull \|\| client.anySupportPutPartial \|\| client.anySupportHint \|\| client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet \|\| manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull \|\| manager.anySupportPutPartial \|\| manager.anySupportHint \|\| manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) \|\| !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.ProbeAckData \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode \| small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U \|\| beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }	module TLMonitor_8( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [3:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [31:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7] wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_a_bits_source = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_source = 1'h0; // @[Monitor.scala:36:7] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire c_set = 1'h0; // @[Monitor.scala:738:34] wire c_set_wo_ready = 1'h0; // @[Monitor.scala:739:34] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire _source_ok_T = 1'h1; // @[Parameters.scala:46:9] wire _source_ok_WIRE_0 = 1'h1; // @[Parameters.scala:1138:31] wire _source_ok_T_1 = 1'h1; // @[Parameters.scala:46:9] wire _source_ok_WIRE_1_0 = 1'h1; // @[Parameters.scala:1138:31] wire sink_ok = 1'h1; // @[Monitor.scala:309:31] wire _same_cycle_resp_T_2 = 1'h1; // @[Monitor.scala:684:113] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire _same_cycle_resp_T_8 = 1'h1; // @[Monitor.scala:795:113] wire [8:0] c_first_beats1_decode = 9'h0; // @[Edges.scala:220:59] wire [8:0] c_first_beats1 = 9'h0; // @[Edges.scala:221:14] wire [8:0] _c_first_count_T = 9'h0; // @[Edges.scala:234:27] wire [8:0] c_first_count = 9'h0; // @[Edges.scala:234:25] wire [8:0] _c_first_counter_T = 9'h0; // @[Edges.scala:236:21] wire [8:0] c_first_counter1 = 9'h1FF; // @[Edges.scala:230:28] wire [9:0] _c_first_counter1_T = 10'h3FF; // @[Edges.scala:230:28] wire [2:0] io_in_a_bits_param = 3'h0; // @[Monitor.scala:36:7] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [31:0] _c_first_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_first_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_wo_ready_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_wo_ready_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_4_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_5_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [3:0] _a_opcode_lookup_T = 4'h0; // @[Monitor.scala:637:69] wire [3:0] _a_size_lookup_T = 4'h0; // @[Monitor.scala:641:65] wire [3:0] _a_opcodes_set_T = 4'h0; // @[Monitor.scala:659:79] wire [3:0] _a_sizes_set_T = 4'h0; // @[Monitor.scala:660:77] wire [3:0] _d_opcodes_clr_T_4 = 4'h0; // @[Monitor.scala:680:101] wire [3:0] _d_sizes_clr_T_4 = 4'h0; // @[Monitor.scala:681:99] wire [3:0] _c_first_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] c_opcodes_set = 4'h0; // @[Monitor.scala:740:34] wire [3:0] _c_opcode_lookup_T = 4'h0; // @[Monitor.scala:749:69] wire [3:0] _c_size_lookup_T = 4'h0; // @[Monitor.scala:750:67] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] _c_set_wo_ready_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_wo_ready_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_sizes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_T = 4'h0; // @[Monitor.scala:767:79] wire [3:0] _c_sizes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_sizes_set_T = 4'h0; // @[Monitor.scala:768:77] wire [3:0] _c_probe_ack_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _d_opcodes_clr_T_10 = 4'h0; // @[Monitor.scala:790:101] wire [3:0] _d_sizes_clr_T_10 = 4'h0; // @[Monitor.scala:791:99] wire [3:0] _same_cycle_resp_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_4_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_5_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [30:0] _d_sizes_clr_T_5 = 31'hFF; // @[Monitor.scala:681:74] wire [30:0] _d_sizes_clr_T_11 = 31'hFF; // @[Monitor.scala:791:74] wire [15:0] _a_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _c_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hFF; // @[Monitor.scala:724:57] wire [16:0] _a_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _c_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hFF; // @[Monitor.scala:724:57] wire [15:0] _a_size_lookup_T_3 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _c_size_lookup_T_3 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h100; // @[Monitor.scala:724:51] wire [30:0] _d_opcodes_clr_T_5 = 31'hF; // @[Monitor.scala:680:76] wire [30:0] _d_opcodes_clr_T_11 = 31'hF; // @[Monitor.scala:790:76] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [1:0] _a_set_wo_ready_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _a_set_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _d_clr_wo_ready_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _d_clr_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _c_set_wo_ready_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _c_set_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _d_clr_wo_ready_T_1 = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _d_clr_T_1 = 2'h1; // @[OneHot.scala:58:35] wire [19:0] _c_sizes_set_T_1 = 20'h0; // @[Monitor.scala:768:52] wire [18:0] _c_opcodes_set_T_1 = 19'h0; // @[Monitor.scala:767:54] wire [4:0] _c_sizes_set_interm_T_1 = 5'h1; // @[Monitor.scala:766:59] wire [4:0] c_sizes_set_interm = 5'h0; // @[Monitor.scala:755:40] wire [4:0] _c_sizes_set_interm_T = 5'h0; // @[Monitor.scala:766:51] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [7:0] c_sizes_set = 8'h0; // @[Monitor.scala:741:34] wire [11:0] _c_first_beats1_decode_T_2 = 12'h0; // @[package.scala:243:46] wire [11:0] _c_first_beats1_decode_T_1 = 12'hFFF; // @[package.scala:243:76] wire [26:0] _c_first_beats1_decode_T = 27'hFFF; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [3:0] _a_size_lookup_T_2 = 4'h8; // @[Monitor.scala:641:117] wire [3:0] _d_sizes_clr_T = 4'h8; // @[Monitor.scala:681:48] wire [3:0] _c_size_lookup_T_2 = 4'h8; // @[Monitor.scala:750:119] wire [3:0] _d_sizes_clr_T_6 = 4'h8; // @[Monitor.scala:791:48] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire [26:0] _GEN = 27'hFFF << io_in_a_bits_size_0; // @[package.scala:243:71] wire [26:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [11:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [31:0] _is_aligned_T = {20'h0, io_in_a_bits_address_0[11:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 32'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 4'h2; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 \| _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 \| _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 \| _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 \| _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 \| _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 \| _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 \| _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 \| _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire _T_1212 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_1212; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_1212; // @[Decoupled.scala:51:35] wire [11:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [8:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [8:0] a_first_counter; // @[Edges.scala:229:27] wire [9:0] _a_first_counter1_T = {1'h0, a_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] a_first_counter1 = _a_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T \| _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [8:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [3:0] size; // @[Monitor.scala:389:22] reg [31:0] address; // @[Monitor.scala:391:22] wire _T_1285 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_1285; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_1285; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_1285; // @[Decoupled.scala:51:35] wire [26:0] _GEN_0 = 27'hFFF << io_in_d_bits_size_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [11:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [8:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T = {1'h0, d_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1 = _d_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T \| _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [3:0] size_1; // @[Monitor.scala:540:22] reg [2:0] sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] reg [1:0] inflight; // @[Monitor.scala:614:27] reg [3:0] inflight_opcodes; // @[Monitor.scala:616:35] wire [3:0] _a_opcode_lookup_T_1 = inflight_opcodes; // @[Monitor.scala:616:35, :637:44] reg [7:0] inflight_sizes; // @[Monitor.scala:618:33] wire [7:0] _a_size_lookup_T_1 = inflight_sizes; // @[Monitor.scala:618:33, :641:40] wire [11:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [8:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [8:0] a_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] a_first_counter1_1 = _a_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 \| _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [11:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_1 = _d_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 \| _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire a_set; // @[Monitor.scala:626:34] wire a_set_wo_ready; // @[Monitor.scala:627:34] wire [3:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [7:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [15:0] _a_opcode_lookup_T_6 = {12'h0, _a_opcode_lookup_T_1}; // @[Monitor.scala:637:{44,97}] wire [15:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [7:0] a_size_lookup; // @[Monitor.scala:639:33] wire [15:0] _a_size_lookup_T_6 = {8'h0, _a_size_lookup_T_1}; // @[Monitor.scala:641:{40,91}] wire [15:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[15:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[7:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [4:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _T_1135 = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26] assign a_set_wo_ready = _T_1135; // @[Monitor.scala:627:34, :651:26] wire _same_cycle_resp_T; // @[Monitor.scala:684:44] assign _same_cycle_resp_T = _T_1135; // @[Monitor.scala:651:26, :684:44] assign a_set = _T_1212 & a_first_1; // @[Decoupled.scala:51:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = a_set ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:626:34, :646:40, :655:70, :657:{28,61}] wire [4:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [4:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = a_set ? _a_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:626:34, :648:38, :655:70, :658:{28,59}] wire [18:0] _a_opcodes_set_T_1 = {15'h0, a_opcodes_set_interm}; // @[Monitor.scala:646:40, :659:54] assign a_opcodes_set = a_set ? _a_opcodes_set_T_1[3:0] : 4'h0; // @[Monitor.scala:626:34, :630:33, :655:70, :659:{28,54}] wire [19:0] _a_sizes_set_T_1 = {15'h0, a_sizes_set_interm}; // @[Monitor.scala:648:38, :660:52] assign a_sizes_set = a_set ? _a_sizes_set_T_1[7:0] : 8'h0; // @[Monitor.scala:626:34, :632:31, :655:70, :660:{28,52}] wire d_clr; // @[Monitor.scala:664:34] wire d_clr_wo_ready; // @[Monitor.scala:665:34] wire [3:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [7:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_1 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_1; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_1; // @[Monitor.scala:673:46, :783:46] wire _T_1184 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] assign d_clr_wo_ready = _T_1184 & ~d_release_ack; // @[Monitor.scala:665:34, :673:46, :674:{26,71,74}] assign d_clr = _T_1285 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_opcodes_clr = {4{d_clr}}; // @[Monitor.scala:664:34, :668:33, :678:89, :680:21] assign d_sizes_clr = {8{d_clr}}; // @[Monitor.scala:664:34, :670:31, :678:89, :681:21] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire same_cycle_resp = _same_cycle_resp_T_1; // @[Monitor.scala:684:{55,88}] wire [1:0] _inflight_T = {inflight[1], inflight[0] \| a_set}; // @[Monitor.scala:614:27, :626:34, :705:27] wire _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [1:0] _inflight_T_2 = {1'h0, _inflight_T[0] & _inflight_T_1}; // @[Monitor.scala:705:{27,36,38}] wire [3:0] _inflight_opcodes_T = inflight_opcodes \| a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [3:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [3:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [7:0] _inflight_sizes_T = inflight_sizes \| a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [7:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [7:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [1:0] inflight_1; // @[Monitor.scala:726:35] wire [1:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [3:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [3:0] _c_opcode_lookup_T_1 = inflight_opcodes_1; // @[Monitor.scala:727:35, :749:44] wire [3:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [7:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [7:0] _c_size_lookup_T_1 = inflight_sizes_1; // @[Monitor.scala:728:35, :750:42] wire [7:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire [11:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_2; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_2 = _d_first_counter1_T_2[8:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 \| _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [7:0] c_size_lookup; // @[Monitor.scala:748:35] wire [15:0] _c_opcode_lookup_T_6 = {12'h0, _c_opcode_lookup_T_1}; // @[Monitor.scala:749:{44,97}] wire [15:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [15:0] _c_size_lookup_T_6 = {8'h0, _c_size_lookup_T_1}; // @[Monitor.scala:750:{42,93}] wire [15:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[15:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[7:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire d_clr_1; // @[Monitor.scala:774:34] wire d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [3:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [7:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_1256 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_1256 & d_release_ack_1; // @[Monitor.scala:775:34, :783:46, :784:{26,71}] assign d_clr_1 = _T_1285 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_opcodes_clr_1 = {4{d_clr_1}}; // @[Monitor.scala:774:34, :776:34, :788:88, :790:21] assign d_sizes_clr_1 = {8{d_clr_1}}; // @[Monitor.scala:774:34, :777:34, :788:88, :791:21] wire _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [1:0] _inflight_T_5 = {1'h0, _inflight_T_3[0] & _inflight_T_4}; // @[Monitor.scala:814:{35,44,46}] wire [3:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [3:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [7:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [7:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to the following Chisel files. File FPU.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.tile import chisel3._ import chisel3.util._ import chisel3.{DontCare, WireInit, withClock, withReset} import chisel3.experimental.SourceInfo import chisel3.experimental.dataview._ import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.rocket._ import freechips.rocketchip.rocket.Instructions._ import freechips.rocketchip.util._ import freechips.rocketchip.util.property case class FPUParams( minFLen: Int = 32, fLen: Int = 64, divSqrt: Boolean = true, sfmaLatency: Int = 3, dfmaLatency: Int = 4, fpmuLatency: Int = 2, ifpuLatency: Int = 2 ) object FPConstants { val RM_SZ = 3 val FLAGS_SZ = 5 } trait HasFPUCtrlSigs { val ldst = Bool() val wen = Bool() val ren1 = Bool() val ren2 = Bool() val ren3 = Bool() val swap12 = Bool() val swap23 = Bool() val typeTagIn = UInt(2.W) val typeTagOut = UInt(2.W) val fromint = Bool() val toint = Bool() val fastpipe = Bool() val fma = Bool() val div = Bool() val sqrt = Bool() val wflags = Bool() val vec = Bool() } class FPUCtrlSigs extends Bundle with HasFPUCtrlSigs class FPUDecoder(implicit p: Parameters) extends FPUModule()(p) { val io = IO(new Bundle { val inst = Input(Bits(32.W)) val sigs = Output(new FPUCtrlSigs()) }) private val X2 = BitPat.dontCare(2) val default = List(X,X,X,X,X,X,X,X2,X2,X,X,X,X,X,X,X,N) val h: Array[(BitPat, List[BitPat])] = Array(FLH -> List(Y,Y,N,N,N,X,X,X2,X2,N,N,N,N,N,N,N,N), FSH -> List(Y,N,N,Y,N,Y,X, I, H,N,Y,N,N,N,N,N,N), FMV_H_X -> List(N,Y,N,N,N,X,X, H, I,Y,N,N,N,N,N,N,N), FCVT_H_W -> List(N,Y,N,N,N,X,X, H, H,Y,N,N,N,N,N,Y,N), FCVT_H_WU-> List(N,Y,N,N,N,X,X, H, H,Y,N,N,N,N,N,Y,N), FCVT_H_L -> List(N,Y,N,N,N,X,X, H, H,Y,N,N,N,N,N,Y,N), FCVT_H_LU-> List(N,Y,N,N,N,X,X, H, H,Y,N,N,N,N,N,Y,N), FMV_X_H -> List(N,N,Y,N,N,N,X, I, H,N,Y,N,N,N,N,N,N), FCLASS_H -> List(N,N,Y,N,N,N,X, H, H,N,Y,N,N,N,N,N,N), FCVT_W_H -> List(N,N,Y,N,N,N,X, H,X2,N,Y,N,N,N,N,Y,N), FCVT_WU_H-> List(N,N,Y,N,N,N,X, H,X2,N,Y,N,N,N,N,Y,N), FCVT_L_H -> List(N,N,Y,N,N,N,X, H,X2,N,Y,N,N,N,N,Y,N), FCVT_LU_H-> List(N,N,Y,N,N,N,X, H,X2,N,Y,N,N,N,N,Y,N), FCVT_S_H -> List(N,Y,Y,N,N,N,X, H, S,N,N,Y,N,N,N,Y,N), FCVT_H_S -> List(N,Y,Y,N,N,N,X, S, H,N,N,Y,N,N,N,Y,N), FEQ_H -> List(N,N,Y,Y,N,N,N, H, H,N,Y,N,N,N,N,Y,N), FLT_H -> List(N,N,Y,Y,N,N,N, H, H,N,Y,N,N,N,N,Y,N), FLE_H -> List(N,N,Y,Y,N,N,N, H, H,N,Y,N,N,N,N,Y,N), FSGNJ_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,Y,N,N,N,N,N), FSGNJN_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,Y,N,N,N,N,N), FSGNJX_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,Y,N,N,N,N,N), FMIN_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,Y,N,N,N,Y,N), FMAX_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,Y,N,N,N,Y,N), FADD_H -> List(N,Y,Y,Y,N,N,Y, H, H,N,N,N,Y,N,N,Y,N), FSUB_H -> List(N,Y,Y,Y,N,N,Y, H, H,N,N,N,Y,N,N,Y,N), FMUL_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,N,Y,N,N,Y,N), FMADD_H -> List(N,Y,Y,Y,Y,N,N, H, H,N,N,N,Y,N,N,Y,N), FMSUB_H -> List(N,Y,Y,Y,Y,N,N, H, H,N,N,N,Y,N,N,Y,N), FNMADD_H -> List(N,Y,Y,Y,Y,N,N, H, H,N,N,N,Y,N,N,Y,N), FNMSUB_H -> List(N,Y,Y,Y,Y,N,N, H, H,N,N,N,Y,N,N,Y,N), FDIV_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,N,N,Y,N,Y,N), FSQRT_H -> List(N,Y,Y,N,N,N,X, H, H,N,N,N,N,N,Y,Y,N)) val f: Array[(BitPat, List[BitPat])] = Array(FLW -> List(Y,Y,N,N,N,X,X,X2,X2,N,N,N,N,N,N,N,N), FSW -> List(Y,N,N,Y,N,Y,X, I, S,N,Y,N,N,N,N,N,N), FMV_W_X -> List(N,Y,N,N,N,X,X, S, I,Y,N,N,N,N,N,N,N), FCVT_S_W -> List(N,Y,N,N,N,X,X, S, S,Y,N,N,N,N,N,Y,N), FCVT_S_WU-> List(N,Y,N,N,N,X,X, S, S,Y,N,N,N,N,N,Y,N), FCVT_S_L -> List(N,Y,N,N,N,X,X, S, S,Y,N,N,N,N,N,Y,N), FCVT_S_LU-> List(N,Y,N,N,N,X,X, S, S,Y,N,N,N,N,N,Y,N), FMV_X_W -> List(N,N,Y,N,N,N,X, I, S,N,Y,N,N,N,N,N,N), FCLASS_S -> List(N,N,Y,N,N,N,X, S, S,N,Y,N,N,N,N,N,N), FCVT_W_S -> List(N,N,Y,N,N,N,X, S,X2,N,Y,N,N,N,N,Y,N), FCVT_WU_S-> List(N,N,Y,N,N,N,X, S,X2,N,Y,N,N,N,N,Y,N), FCVT_L_S -> List(N,N,Y,N,N,N,X, S,X2,N,Y,N,N,N,N,Y,N), FCVT_LU_S-> List(N,N,Y,N,N,N,X, S,X2,N,Y,N,N,N,N,Y,N), FEQ_S -> List(N,N,Y,Y,N,N,N, S, S,N,Y,N,N,N,N,Y,N), FLT_S -> List(N,N,Y,Y,N,N,N, S, S,N,Y,N,N,N,N,Y,N), FLE_S -> List(N,N,Y,Y,N,N,N, S, S,N,Y,N,N,N,N,Y,N), FSGNJ_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,Y,N,N,N,N,N), FSGNJN_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,Y,N,N,N,N,N), FSGNJX_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,Y,N,N,N,N,N), FMIN_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,Y,N,N,N,Y,N), FMAX_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,Y,N,N,N,Y,N), FADD_S -> List(N,Y,Y,Y,N,N,Y, S, S,N,N,N,Y,N,N,Y,N), FSUB_S -> List(N,Y,Y,Y,N,N,Y, S, S,N,N,N,Y,N,N,Y,N), FMUL_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,N,Y,N,N,Y,N), FMADD_S -> List(N,Y,Y,Y,Y,N,N, S, S,N,N,N,Y,N,N,Y,N), FMSUB_S -> List(N,Y,Y,Y,Y,N,N, S, S,N,N,N,Y,N,N,Y,N), FNMADD_S -> List(N,Y,Y,Y,Y,N,N, S, S,N,N,N,Y,N,N,Y,N), FNMSUB_S -> List(N,Y,Y,Y,Y,N,N, S, S,N,N,N,Y,N,N,Y,N), FDIV_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,N,N,Y,N,Y,N), FSQRT_S -> List(N,Y,Y,N,N,N,X, S, S,N,N,N,N,N,Y,Y,N)) val d: Array[(BitPat, List[BitPat])] = Array(FLD -> List(Y,Y,N,N,N,X,X,X2,X2,N,N,N,N,N,N,N,N), FSD -> List(Y,N,N,Y,N,Y,X, I, D,N,Y,N,N,N,N,N,N), FMV_D_X -> List(N,Y,N,N,N,X,X, D, I,Y,N,N,N,N,N,N,N), FCVT_D_W -> List(N,Y,N,N,N,X,X, D, D,Y,N,N,N,N,N,Y,N), FCVT_D_WU-> List(N,Y,N,N,N,X,X, D, D,Y,N,N,N,N,N,Y,N), FCVT_D_L -> List(N,Y,N,N,N,X,X, D, D,Y,N,N,N,N,N,Y,N), FCVT_D_LU-> List(N,Y,N,N,N,X,X, D, D,Y,N,N,N,N,N,Y,N), FMV_X_D -> List(N,N,Y,N,N,N,X, I, D,N,Y,N,N,N,N,N,N), FCLASS_D -> List(N,N,Y,N,N,N,X, D, D,N,Y,N,N,N,N,N,N), FCVT_W_D -> List(N,N,Y,N,N,N,X, D,X2,N,Y,N,N,N,N,Y,N), FCVT_WU_D-> List(N,N,Y,N,N,N,X, D,X2,N,Y,N,N,N,N,Y,N), FCVT_L_D -> List(N,N,Y,N,N,N,X, D,X2,N,Y,N,N,N,N,Y,N), FCVT_LU_D-> List(N,N,Y,N,N,N,X, D,X2,N,Y,N,N,N,N,Y,N), FCVT_S_D -> List(N,Y,Y,N,N,N,X, D, S,N,N,Y,N,N,N,Y,N), FCVT_D_S -> List(N,Y,Y,N,N,N,X, S, D,N,N,Y,N,N,N,Y,N), FEQ_D -> List(N,N,Y,Y,N,N,N, D, D,N,Y,N,N,N,N,Y,N), FLT_D -> List(N,N,Y,Y,N,N,N, D, D,N,Y,N,N,N,N,Y,N), FLE_D -> List(N,N,Y,Y,N,N,N, D, D,N,Y,N,N,N,N,Y,N), FSGNJ_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,Y,N,N,N,N,N), FSGNJN_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,Y,N,N,N,N,N), FSGNJX_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,Y,N,N,N,N,N), FMIN_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,Y,N,N,N,Y,N), FMAX_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,Y,N,N,N,Y,N), FADD_D -> List(N,Y,Y,Y,N,N,Y, D, D,N,N,N,Y,N,N,Y,N), FSUB_D -> List(N,Y,Y,Y,N,N,Y, D, D,N,N,N,Y,N,N,Y,N), FMUL_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,N,Y,N,N,Y,N), FMADD_D -> List(N,Y,Y,Y,Y,N,N, D, D,N,N,N,Y,N,N,Y,N), FMSUB_D -> List(N,Y,Y,Y,Y,N,N, D, D,N,N,N,Y,N,N,Y,N), FNMADD_D -> List(N,Y,Y,Y,Y,N,N, D, D,N,N,N,Y,N,N,Y,N), FNMSUB_D -> List(N,Y,Y,Y,Y,N,N, D, D,N,N,N,Y,N,N,Y,N), FDIV_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,N,N,Y,N,Y,N), FSQRT_D -> List(N,Y,Y,N,N,N,X, D, D,N,N,N,N,N,Y,Y,N)) val fcvt_hd: Array[(BitPat, List[BitPat])] = Array(FCVT_H_D -> List(N,Y,Y,N,N,N,X, D, H,N,N,Y,N,N,N,Y,N), FCVT_D_H -> List(N,Y,Y,N,N,N,X, H, D,N,N,Y,N,N,N,Y,N)) val vfmv_f_s: Array[(BitPat, List[BitPat])] = Array(VFMV_F_S -> List(N,Y,N,N,N,N,X,X2,X2,N,N,N,N,N,N,N,Y)) val insns = ((minFLen, fLen) match { case (32, 32) => f case (16, 32) => h ++ f case (32, 64) => f ++ d case (16, 64) => h ++ f ++ d ++ fcvt_hd case other => throw new Exception(s"minFLen = ${minFLen} & fLen = ${fLen} is an unsupported configuration") }) ++ (if (usingVector) vfmv_f_s else Array[(BitPat, List[BitPat])]()) val decoder = DecodeLogic(io.inst, default, insns) val s = io.sigs val sigs = Seq(s.ldst, s.wen, s.ren1, s.ren2, s.ren3, s.swap12, s.swap23, s.typeTagIn, s.typeTagOut, s.fromint, s.toint, s.fastpipe, s.fma, s.div, s.sqrt, s.wflags, s.vec) sigs zip decoder map {case(s,d) => s := d} } class FPUCoreIO(implicit p: Parameters) extends CoreBundle()(p) { val hartid = Input(UInt(hartIdLen.W)) val time = Input(UInt(xLen.W)) val inst = Input(Bits(32.W)) val fromint_data = Input(Bits(xLen.W)) val fcsr_rm = Input(Bits(FPConstants.RM_SZ.W)) val fcsr_flags = Valid(Bits(FPConstants.FLAGS_SZ.W)) val v_sew = Input(UInt(3.W)) val store_data = Output(Bits(fLen.W)) val toint_data = Output(Bits(xLen.W)) val ll_resp_val = Input(Bool()) val ll_resp_type = Input(Bits(3.W)) val ll_resp_tag = Input(UInt(5.W)) val ll_resp_data = Input(Bits(fLen.W)) val valid = Input(Bool()) val fcsr_rdy = Output(Bool()) val nack_mem = Output(Bool()) val illegal_rm = Output(Bool()) val killx = Input(Bool()) val killm = Input(Bool()) val dec = Output(new FPUCtrlSigs()) val sboard_set = Output(Bool()) val sboard_clr = Output(Bool()) val sboard_clra = Output(UInt(5.W)) val keep_clock_enabled = Input(Bool()) } class FPUIO(implicit p: Parameters) extends FPUCoreIO ()(p) { val cp_req = Flipped(Decoupled(new FPInput())) //cp doesn't pay attn to kill sigs val cp_resp = Decoupled(new FPResult()) } class FPResult(implicit p: Parameters) extends CoreBundle()(p) { val data = Bits((fLen+1).W) val exc = Bits(FPConstants.FLAGS_SZ.W) } class IntToFPInput(implicit p: Parameters) extends CoreBundle()(p) with HasFPUCtrlSigs { val rm = Bits(FPConstants.RM_SZ.W) val typ = Bits(2.W) val in1 = Bits(xLen.W) } class FPInput(implicit p: Parameters) extends CoreBundle()(p) with HasFPUCtrlSigs { val rm = Bits(FPConstants.RM_SZ.W) val fmaCmd = Bits(2.W) val typ = Bits(2.W) val fmt = Bits(2.W) val in1 = Bits((fLen+1).W) val in2 = Bits((fLen+1).W) val in3 = Bits((fLen+1).W) } case class FType(exp: Int, sig: Int) { def ieeeWidth = exp + sig def recodedWidth = ieeeWidth + 1 def ieeeQNaN = ((BigInt(1) << (ieeeWidth - 1)) - (BigInt(1) << (sig - 2))).U(ieeeWidth.W) def qNaN = ((BigInt(7) << (exp + sig - 3)) + (BigInt(1) << (sig - 2))).U(recodedWidth.W) def isNaN(x: UInt) = x(sig + exp - 1, sig + exp - 3).andR def isSNaN(x: UInt) = isNaN(x) && !x(sig - 2) def classify(x: UInt) = { val sign = x(sig + exp) val code = x(exp + sig - 1, exp + sig - 3) val codeHi = code(2, 1) val isSpecial = codeHi === 3.U val isHighSubnormalIn = x(exp + sig - 3, sig - 1) < 2.U val isSubnormal = code === 1.U \|\| codeHi === 1.U && isHighSubnormalIn val isNormal = codeHi === 1.U && !isHighSubnormalIn \|\| codeHi === 2.U val isZero = code === 0.U val isInf = isSpecial && !code(0) val isNaN = code.andR val isSNaN = isNaN && !x(sig-2) val isQNaN = isNaN && x(sig-2) Cat(isQNaN, isSNaN, isInf && !sign, isNormal && !sign, isSubnormal && !sign, isZero && !sign, isZero && sign, isSubnormal && sign, isNormal && sign, isInf && sign) } // convert between formats, ignoring rounding, range, NaN def unsafeConvert(x: UInt, to: FType) = if (this == to) x else { val sign = x(sig + exp) val fractIn = x(sig - 2, 0) val expIn = x(sig + exp - 1, sig - 1) val fractOut = fractIn << to.sig >> sig val expOut = { val expCode = expIn(exp, exp - 2) val commonCase = (expIn + (1 << to.exp).U) - (1 << exp).U Mux(expCode === 0.U \|\| expCode >= 6.U, Cat(expCode, commonCase(to.exp - 3, 0)), commonCase(to.exp, 0)) } Cat(sign, expOut, fractOut) } private def ieeeBundle = { val expWidth = exp class IEEEBundle extends Bundle { val sign = Bool() val exp = UInt(expWidth.W) val sig = UInt((ieeeWidth-expWidth-1).W) } new IEEEBundle } def unpackIEEE(x: UInt) = x.asTypeOf(ieeeBundle) def recode(x: UInt) = hardfloat.recFNFromFN(exp, sig, x) def ieee(x: UInt) = hardfloat.fNFromRecFN(exp, sig, x) } object FType { val H = new FType(5, 11) val S = new FType(8, 24) val D = new FType(11, 53) val all = List(H, S, D) } trait HasFPUParameters { require(fLen == 0 \|\| FType.all.exists(_.ieeeWidth == fLen)) val minFLen: Int val fLen: Int def xLen: Int val minXLen = 32 val nIntTypes = log2Ceil(xLen/minXLen) + 1 def floatTypes = FType.all.filter(t => minFLen <= t.ieeeWidth && t.ieeeWidth <= fLen) def minType = floatTypes.head def maxType = floatTypes.last def prevType(t: FType) = floatTypes(typeTag(t) - 1) def maxExpWidth = maxType.exp def maxSigWidth = maxType.sig def typeTag(t: FType) = floatTypes.indexOf(t) def typeTagWbOffset = (FType.all.indexOf(minType) + 1).U def typeTagGroup(t: FType) = (if (floatTypes.contains(t)) typeTag(t) else typeTag(maxType)).U // typeTag def H = typeTagGroup(FType.H) def S = typeTagGroup(FType.S) def D = typeTagGroup(FType.D) def I = typeTag(maxType).U private def isBox(x: UInt, t: FType): Bool = x(t.sig + t.exp, t.sig + t.exp - 4).andR private def box(x: UInt, xt: FType, y: UInt, yt: FType): UInt = { require(xt.ieeeWidth == 2 * yt.ieeeWidth) val swizzledNaN = Cat( x(xt.sig + xt.exp, xt.sig + xt.exp - 3), x(xt.sig - 2, yt.recodedWidth - 1).andR, x(xt.sig + xt.exp - 5, xt.sig), y(yt.recodedWidth - 2), x(xt.sig - 2, yt.recodedWidth - 1), y(yt.recodedWidth - 1), y(yt.recodedWidth - 3, 0)) Mux(xt.isNaN(x), swizzledNaN, x) } // implement NaN unboxing for FU inputs def unbox(x: UInt, tag: UInt, exactType: Option[FType]): UInt = { val outType = exactType.getOrElse(maxType) def helper(x: UInt, t: FType): Seq[(Bool, UInt)] = { val prev = if (t == minType) { Seq() } else { val prevT = prevType(t) val unswizzled = Cat( x(prevT.sig + prevT.exp - 1), x(t.sig - 1), x(prevT.sig + prevT.exp - 2, 0)) val prev = helper(unswizzled, prevT) val isbox = isBox(x, t) prev.map(p => (isbox && p._1, p._2)) } prev :+ (true.B, t.unsafeConvert(x, outType)) } val (oks, floats) = helper(x, maxType).unzip if (exactType.isEmpty \|\| floatTypes.size == 1) { Mux(oks(tag), floats(tag), maxType.qNaN) } else { val t = exactType.get floats(typeTag(t)) \| Mux(oks(typeTag(t)), 0.U, t.qNaN) } } // make sure that the redundant bits in the NaN-boxed encoding are consistent def consistent(x: UInt): Bool = { def helper(x: UInt, t: FType): Bool = if (typeTag(t) == 0) true.B else { val prevT = prevType(t) val unswizzled = Cat( x(prevT.sig + prevT.exp - 1), x(t.sig - 1), x(prevT.sig + prevT.exp - 2, 0)) val prevOK = !isBox(x, t) \|\| helper(unswizzled, prevT) val curOK = !t.isNaN(x) \|\| x(t.sig + t.exp - 4) === x(t.sig - 2, prevT.recodedWidth - 1).andR prevOK && curOK } helper(x, maxType) } // generate a NaN box from an FU result def box(x: UInt, t: FType): UInt = { if (t == maxType) { x } else { val nt = floatTypes(typeTag(t) + 1) val bigger = box(((BigInt(1) << nt.recodedWidth)-1).U, nt, x, t) bigger \| ((BigInt(1) << maxType.recodedWidth) - (BigInt(1) << nt.recodedWidth)).U } } // generate a NaN box from an FU result def box(x: UInt, tag: UInt): UInt = { val opts = floatTypes.map(t => box(x, t)) opts(tag) } // zap bits that hardfloat thinks are don't-cares, but we do care about def sanitizeNaN(x: UInt, t: FType): UInt = { if (typeTag(t) == 0) { x } else { val maskedNaN = x & ~((BigInt(1) << (t.sig-1)) \| (BigInt(1) << (t.sig+t.exp-4))).U(t.recodedWidth.W) Mux(t.isNaN(x), maskedNaN, x) } } // implement NaN boxing and recoding for FL/fmv..x def recode(x: UInt, tag: UInt): UInt = { def helper(x: UInt, t: FType): UInt = { if (typeTag(t) == 0) { t.recode(x) } else { val prevT = prevType(t) box(t.recode(x), t, helper(x, prevT), prevT) } } // fill MSBs of subword loads to emulate a wider load of a NaN-boxed value val boxes = floatTypes.map(t => ((BigInt(1) << maxType.ieeeWidth) - (BigInt(1) << t.ieeeWidth)).U) helper(boxes(tag) \| x, maxType) } // implement NaN unboxing and un-recoding for FS/fmv.x. def ieee(x: UInt, t: FType = maxType): UInt = { if (typeTag(t) == 0) { t.ieee(x) } else { val unrecoded = t.ieee(x) val prevT = prevType(t) val prevRecoded = Cat( x(prevT.recodedWidth-2), x(t.sig-1), x(prevT.recodedWidth-3, 0)) val prevUnrecoded = ieee(prevRecoded, prevT) Cat(unrecoded >> prevT.ieeeWidth, Mux(t.isNaN(x), prevUnrecoded, unrecoded(prevT.ieeeWidth-1, 0))) } } } abstract class FPUModule(implicit val p: Parameters) extends Module with HasCoreParameters with HasFPUParameters class FPToInt(implicit p: Parameters) extends FPUModule()(p) with ShouldBeRetimed { class Output extends Bundle { val in = new FPInput val lt = Bool() val store = Bits(fLen.W) val toint = Bits(xLen.W) val exc = Bits(FPConstants.FLAGS_SZ.W) } val io = IO(new Bundle { val in = Flipped(Valid(new FPInput)) val out = Valid(new Output) }) val in = RegEnable(io.in.bits, io.in.valid) val valid = RegNext(io.in.valid) val dcmp = Module(new hardfloat.CompareRecFN(maxExpWidth, maxSigWidth)) dcmp.io.a := in.in1 dcmp.io.b := in.in2 dcmp.io.signaling := !in.rm(1) val tag = in.typeTagOut val toint_ieee = (floatTypes.map(t => if (t == FType.H) Fill(maxType.ieeeWidth / minXLen, ieee(in.in1)(15, 0).sextTo(minXLen)) else Fill(maxType.ieeeWidth / t.ieeeWidth, ieee(in.in1)(t.ieeeWidth - 1, 0))): Seq[UInt])(tag) val toint = WireDefault(toint_ieee) val intType = WireDefault(in.fmt(0)) io.out.bits.store := (floatTypes.map(t => Fill(fLen / t.ieeeWidth, ieee(in.in1)(t.ieeeWidth - 1, 0))): Seq[UInt])(tag) io.out.bits.toint := ((0 until nIntTypes).map(i => toint((minXLen << i) - 1, 0).sextTo(xLen)): Seq[UInt])(intType) io.out.bits.exc := 0.U when (in.rm(0)) { val classify_out = (floatTypes.map(t => t.classify(maxType.unsafeConvert(in.in1, t))): Seq[UInt])(tag) toint := classify_out \| (toint_ieee >> minXLen << minXLen) intType := false.B } when (in.wflags) { // feq/flt/fle, fcvt toint := (~in.rm & Cat(dcmp.io.lt, dcmp.io.eq)).orR \| (toint_ieee >> minXLen << minXLen) io.out.bits.exc := dcmp.io.exceptionFlags intType := false.B when (!in.ren2) { // fcvt val cvtType = in.typ.extract(log2Ceil(nIntTypes), 1) intType := cvtType val conv = Module(new hardfloat.RecFNToIN(maxExpWidth, maxSigWidth, xLen)) conv.io.in := in.in1 conv.io.roundingMode := in.rm conv.io.signedOut := ~in.typ(0) toint := conv.io.out io.out.bits.exc := Cat(conv.io.intExceptionFlags(2, 1).orR, 0.U(3.W), conv.io.intExceptionFlags(0)) for (i <- 0 until nIntTypes-1) { val w = minXLen << i when (cvtType === i.U) { val narrow = Module(new hardfloat.RecFNToIN(maxExpWidth, maxSigWidth, w)) narrow.io.in := in.in1 narrow.io.roundingMode := in.rm narrow.io.signedOut := ~in.typ(0) val excSign = in.in1(maxExpWidth + maxSigWidth) && !maxType.isNaN(in.in1) val excOut = Cat(conv.io.signedOut === excSign, Fill(w-1, !excSign)) val invalid = conv.io.intExceptionFlags(2) \|\| narrow.io.intExceptionFlags(1) when (invalid) { toint := Cat(conv.io.out >> w, excOut) } io.out.bits.exc := Cat(invalid, 0.U(3.W), !invalid && conv.io.intExceptionFlags(0)) } } } } io.out.valid := valid io.out.bits.lt := dcmp.io.lt \|\| (dcmp.io.a.asSInt < 0.S && dcmp.io.b.asSInt >= 0.S) io.out.bits.in := in } class IntToFP(val latency: Int)(implicit p: Parameters) extends FPUModule()(p) with ShouldBeRetimed { val io = IO(new Bundle { val in = Flipped(Valid(new IntToFPInput)) val out = Valid(new FPResult) }) val in = Pipe(io.in) val tag = in.bits.typeTagIn val mux = Wire(new FPResult) mux.exc := 0.U mux.data := recode(in.bits.in1, tag) val intValue = { val res = WireDefault(in.bits.in1.asSInt) for (i <- 0 until nIntTypes-1) { val smallInt = in.bits.in1((minXLen << i) - 1, 0) when (in.bits.typ.extract(log2Ceil(nIntTypes), 1) === i.U) { res := Mux(in.bits.typ(0), smallInt.zext, smallInt.asSInt) } } res.asUInt } when (in.bits.wflags) { // fcvt // could be improved for RVD/RVQ with a single variable-position rounding // unit, rather than N fixed-position ones val i2fResults = for (t <- floatTypes) yield { val i2f = Module(new hardfloat.INToRecFN(xLen, t.exp, t.sig)) i2f.io.signedIn := ~in.bits.typ(0) i2f.io.in := intValue i2f.io.roundingMode := in.bits.rm i2f.io.detectTininess := hardfloat.consts.tininess_afterRounding (sanitizeNaN(i2f.io.out, t), i2f.io.exceptionFlags) } val (data, exc) = i2fResults.unzip val dataPadded = data.init.map(d => Cat(data.last >> d.getWidth, d)) :+ data.last mux.data := dataPadded(tag) mux.exc := exc(tag) } io.out <> Pipe(in.valid, mux, latency-1) } class FPToFP(val latency: Int)(implicit p: Parameters) extends FPUModule()(p) with ShouldBeRetimed { val io = IO(new Bundle { val in = Flipped(Valid(new FPInput)) val out = Valid(new FPResult) val lt = Input(Bool()) // from FPToInt }) val in = Pipe(io.in) val signNum = Mux(in.bits.rm(1), in.bits.in1 ^ in.bits.in2, Mux(in.bits.rm(0), ~in.bits.in2, in.bits.in2)) val fsgnj = Cat(signNum(fLen), in.bits.in1(fLen-1, 0)) val fsgnjMux = Wire(new FPResult) fsgnjMux.exc := 0.U fsgnjMux.data := fsgnj when (in.bits.wflags) { // fmin/fmax val isnan1 = maxType.isNaN(in.bits.in1) val isnan2 = maxType.isNaN(in.bits.in2) val isInvalid = maxType.isSNaN(in.bits.in1) \|\| maxType.isSNaN(in.bits.in2) val isNaNOut = isnan1 && isnan2 val isLHS = isnan2 \|\| in.bits.rm(0) =/= io.lt && !isnan1 fsgnjMux.exc := isInvalid << 4 fsgnjMux.data := Mux(isNaNOut, maxType.qNaN, Mux(isLHS, in.bits.in1, in.bits.in2)) } val inTag = in.bits.typeTagIn val outTag = in.bits.typeTagOut val mux = WireDefault(fsgnjMux) for (t <- floatTypes.init) { when (outTag === typeTag(t).U) { mux.data := Cat(fsgnjMux.data >> t.recodedWidth, maxType.unsafeConvert(fsgnjMux.data, t)) } } when (in.bits.wflags && !in.bits.ren2) { // fcvt if (floatTypes.size > 1) { // widening conversions simply canonicalize NaN operands val widened = Mux(maxType.isNaN(in.bits.in1), maxType.qNaN, in.bits.in1) fsgnjMux.data := widened fsgnjMux.exc := maxType.isSNaN(in.bits.in1) << 4 // narrowing conversions require rounding (for RVQ, this could be // optimized to use a single variable-position rounding unit, rather // than two fixed-position ones) for (outType <- floatTypes.init) when (outTag === typeTag(outType).U && ((typeTag(outType) == 0).B \|\| outTag < inTag)) { val narrower = Module(new hardfloat.RecFNToRecFN(maxType.exp, maxType.sig, outType.exp, outType.sig)) narrower.io.in := in.bits.in1 narrower.io.roundingMode := in.bits.rm narrower.io.detectTininess := hardfloat.consts.tininess_afterRounding val narrowed = sanitizeNaN(narrower.io.out, outType) mux.data := Cat(fsgnjMux.data >> narrowed.getWidth, narrowed) mux.exc := narrower.io.exceptionFlags } } } io.out <> Pipe(in.valid, mux, latency-1) } class MulAddRecFNPipe(latency: Int, expWidth: Int, sigWidth: Int) extends Module { override def desiredName = s"MulAddRecFNPipe_l${latency}_e${expWidth}_s${sigWidth}" require(latency<=2) val io = IO(new Bundle { val validin = Input(Bool()) val op = Input(Bits(2.W)) val a = Input(Bits((expWidth + sigWidth + 1).W)) val b = Input(Bits((expWidth + sigWidth + 1).W)) val c = Input(Bits((expWidth + sigWidth + 1).W)) val roundingMode = Input(UInt(3.W)) val detectTininess = Input(UInt(1.W)) val out = Output(Bits((expWidth + sigWidth + 1).W)) val exceptionFlags = Output(Bits(5.W)) val validout = Output(Bool()) }) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val mulAddRecFNToRaw_preMul = Module(new hardfloat.MulAddRecFNToRaw_preMul(expWidth, sigWidth)) val mulAddRecFNToRaw_postMul = Module(new hardfloat.MulAddRecFNToRaw_postMul(expWidth, sigWidth)) mulAddRecFNToRaw_preMul.io.op := io.op mulAddRecFNToRaw_preMul.io.a := io.a mulAddRecFNToRaw_preMul.io.b := io.b mulAddRecFNToRaw_preMul.io.c := io.c val mulAddResult = (mulAddRecFNToRaw_preMul.io.mulAddA * mulAddRecFNToRaw_preMul.io.mulAddB) +& mulAddRecFNToRaw_preMul.io.mulAddC val valid_stage0 = Wire(Bool()) val roundingMode_stage0 = Wire(UInt(3.W)) val detectTininess_stage0 = Wire(UInt(1.W)) val postmul_regs = if(latency>0) 1 else 0 mulAddRecFNToRaw_postMul.io.fromPreMul := Pipe(io.validin, mulAddRecFNToRaw_preMul.io.toPostMul, postmul_regs).bits mulAddRecFNToRaw_postMul.io.mulAddResult := Pipe(io.validin, mulAddResult, postmul_regs).bits mulAddRecFNToRaw_postMul.io.roundingMode := Pipe(io.validin, io.roundingMode, postmul_regs).bits roundingMode_stage0 := Pipe(io.validin, io.roundingMode, postmul_regs).bits detectTininess_stage0 := Pipe(io.validin, io.detectTininess, postmul_regs).bits valid_stage0 := Pipe(io.validin, false.B, postmul_regs).valid //------------------------------------------------------------------------ //------------------------------------------------------------------------ val roundRawFNToRecFN = Module(new hardfloat.RoundRawFNToRecFN(expWidth, sigWidth, 0)) val round_regs = if(latency==2) 1 else 0 roundRawFNToRecFN.io.invalidExc := Pipe(valid_stage0, mulAddRecFNToRaw_postMul.io.invalidExc, round_regs).bits roundRawFNToRecFN.io.in := Pipe(valid_stage0, mulAddRecFNToRaw_postMul.io.rawOut, round_regs).bits roundRawFNToRecFN.io.roundingMode := Pipe(valid_stage0, roundingMode_stage0, round_regs).bits roundRawFNToRecFN.io.detectTininess := Pipe(valid_stage0, detectTininess_stage0, round_regs).bits io.validout := Pipe(valid_stage0, false.B, round_regs).valid roundRawFNToRecFN.io.infiniteExc := false.B io.out := roundRawFNToRecFN.io.out io.exceptionFlags := roundRawFNToRecFN.io.exceptionFlags } class FPUFMAPipe(val latency: Int, val t: FType) (implicit p: Parameters) extends FPUModule()(p) with ShouldBeRetimed { override def desiredName = s"FPUFMAPipe_l${latency}_f${t.ieeeWidth}" require(latency>0) val io = IO(new Bundle { val in = Flipped(Valid(new FPInput)) val out = Valid(new FPResult) }) val valid = RegNext(io.in.valid) val in = Reg(new FPInput) when (io.in.valid) { val one = 1.U << (t.sig + t.exp - 1) val zero = (io.in.bits.in1 ^ io.in.bits.in2) & (1.U << (t.sig + t.exp)) val cmd_fma = io.in.bits.ren3 val cmd_addsub = io.in.bits.swap23 in := io.in.bits when (cmd_addsub) { in.in2 := one } when (!(cmd_fma \|\| cmd_addsub)) { in.in3 := zero } } val fma = Module(new MulAddRecFNPipe((latency-1) min 2, t.exp, t.sig)) fma.io.validin := valid fma.io.op := in.fmaCmd fma.io.roundingMode := in.rm fma.io.detectTininess := hardfloat.consts.tininess_afterRounding fma.io.a := in.in1 fma.io.b := in.in2 fma.io.c := in.in3 val res = Wire(new FPResult) res.data := sanitizeNaN(fma.io.out, t) res.exc := fma.io.exceptionFlags io.out := Pipe(fma.io.validout, res, (latency-3) max 0) } class FPU(cfg: FPUParams)(implicit p: Parameters) extends FPUModule()(p) { val io = IO(new FPUIO) val (useClockGating, useDebugROB) = coreParams match { case r: RocketCoreParams => val sz = if (r.debugROB.isDefined) r.debugROB.get.size else 1 (r.clockGate, sz < 1) case _ => (false, false) } val clock_en_reg = Reg(Bool()) val clock_en = clock_en_reg \|\| io.cp_req.valid val gated_clock = if (!useClockGating) clock else ClockGate(clock, clock_en, "fpu_clock_gate") val fp_decoder = Module(new FPUDecoder) fp_decoder.io.inst := io.inst val id_ctrl = WireInit(fp_decoder.io.sigs) coreParams match { case r: RocketCoreParams => r.vector.map(v => { val v_decode = v.decoder(p) // Only need to get ren1 v_decode.io.inst := io.inst v_decode.io.vconfig := DontCare // core deals with this when (v_decode.io.legal && v_decode.io.read_frs1) { id_ctrl.ren1 := true.B id_ctrl.swap12 := false.B id_ctrl.toint := true.B id_ctrl.typeTagIn := I id_ctrl.typeTagOut := Mux(io.v_sew === 3.U, D, S) } when (v_decode.io.write_frd) { id_ctrl.wen := true.B } })} val ex_reg_valid = RegNext(io.valid, false.B) val ex_reg_inst = RegEnable(io.inst, io.valid) val ex_reg_ctrl = RegEnable(id_ctrl, io.valid) val ex_ra = List.fill(3)(Reg(UInt())) // load/vector response val load_wb = RegNext(io.ll_resp_val) val load_wb_typeTag = RegEnable(io.ll_resp_type(1,0) - typeTagWbOffset, io.ll_resp_val) val load_wb_data = RegEnable(io.ll_resp_data, io.ll_resp_val) val load_wb_tag = RegEnable(io.ll_resp_tag, io.ll_resp_val) class FPUImpl { // entering gated-clock domain val req_valid = ex_reg_valid \|\| io.cp_req.valid val ex_cp_valid = io.cp_req.fire val mem_cp_valid = RegNext(ex_cp_valid, false.B) val wb_cp_valid = RegNext(mem_cp_valid, false.B) val mem_reg_valid = RegInit(false.B) val killm = (io.killm \|\| io.nack_mem) && !mem_cp_valid // Kill X-stage instruction if M-stage is killed. This prevents it from // speculatively being sent to the div-sqrt unit, which can cause priority // inversion for two back-to-back divides, the first of which is killed. val killx = io.killx \|\| mem_reg_valid && killm mem_reg_valid := ex_reg_valid && !killx \|\| ex_cp_valid val mem_reg_inst = RegEnable(ex_reg_inst, ex_reg_valid) val wb_reg_valid = RegNext(mem_reg_valid && (!killm \|\| mem_cp_valid), false.B) val cp_ctrl = Wire(new FPUCtrlSigs) cp_ctrl :<>= io.cp_req.bits.viewAsSupertype(new FPUCtrlSigs) io.cp_resp.valid := false.B io.cp_resp.bits.data := 0.U io.cp_resp.bits.exc := DontCare val ex_ctrl = Mux(ex_cp_valid, cp_ctrl, ex_reg_ctrl) val mem_ctrl = RegEnable(ex_ctrl, req_valid) val wb_ctrl = RegEnable(mem_ctrl, mem_reg_valid) // CoreMonitorBundle to monitor fp register file writes val frfWriteBundle = Seq.fill(2)(WireInit(new CoreMonitorBundle(xLen, fLen), DontCare)) frfWriteBundle.foreach { i => i.clock := clock i.reset := reset i.hartid := io.hartid i.timer := io.time(31,0) i.valid := false.B i.wrenx := false.B i.wrenf := false.B i.excpt := false.B } // regfile val regfile = Mem(32, Bits((fLen+1).W)) when (load_wb) { val wdata = recode(load_wb_data, load_wb_typeTag) regfile(load_wb_tag) := wdata assert(consistent(wdata)) if (enableCommitLog) printf("f%d p%d 0x%x\n", load_wb_tag, load_wb_tag + 32.U, ieee(wdata)) if (useDebugROB) DebugROB.pushWb(clock, reset, io.hartid, load_wb, load_wb_tag + 32.U, ieee(wdata)) frfWriteBundle(0).wrdst := load_wb_tag frfWriteBundle(0).wrenf := true.B frfWriteBundle(0).wrdata := ieee(wdata) } val ex_rs = ex_ra.map(a => regfile(a)) when (io.valid) { when (id_ctrl.ren1) { when (!id_ctrl.swap12) { ex_ra(0) := io.inst(19,15) } when (id_ctrl.swap12) { ex_ra(1) := io.inst(19,15) } } when (id_ctrl.ren2) { when (id_ctrl.swap12) { ex_ra(0) := io.inst(24,20) } when (id_ctrl.swap23) { ex_ra(2) := io.inst(24,20) } when (!id_ctrl.swap12 && !id_ctrl.swap23) { ex_ra(1) := io.inst(24,20) } } when (id_ctrl.ren3) { ex_ra(2) := io.inst(31,27) } } val ex_rm = Mux(ex_reg_inst(14,12) === 7.U, io.fcsr_rm, ex_reg_inst(14,12)) def fuInput(minT: Option[FType]): FPInput = { val req = Wire(new FPInput) val tag = ex_ctrl.typeTagIn req.viewAsSupertype(new Bundle with HasFPUCtrlSigs) :#= ex_ctrl.viewAsSupertype(new Bundle with HasFPUCtrlSigs) req.rm := ex_rm req.in1 := unbox(ex_rs(0), tag, minT) req.in2 := unbox(ex_rs(1), tag, minT) req.in3 := unbox(ex_rs(2), tag, minT) req.typ := ex_reg_inst(21,20) req.fmt := ex_reg_inst(26,25) req.fmaCmd := ex_reg_inst(3,2) \| (!ex_ctrl.ren3 && ex_reg_inst(27)) when (ex_cp_valid) { req := io.cp_req.bits when (io.cp_req.bits.swap12) { req.in1 := io.cp_req.bits.in2 req.in2 := io.cp_req.bits.in1 } when (io.cp_req.bits.swap23) { req.in2 := io.cp_req.bits.in3 req.in3 := io.cp_req.bits.in2 } } req } val sfma = Module(new FPUFMAPipe(cfg.sfmaLatency, FType.S)) sfma.io.in.valid := req_valid && ex_ctrl.fma && ex_ctrl.typeTagOut === S sfma.io.in.bits := fuInput(Some(sfma.t)) val fpiu = Module(new FPToInt) fpiu.io.in.valid := req_valid && (ex_ctrl.toint \|\| ex_ctrl.div \|\| ex_ctrl.sqrt \|\| (ex_ctrl.fastpipe && ex_ctrl.wflags)) fpiu.io.in.bits := fuInput(None) io.store_data := fpiu.io.out.bits.store io.toint_data := fpiu.io.out.bits.toint when(fpiu.io.out.valid && mem_cp_valid && mem_ctrl.toint){ io.cp_resp.bits.data := fpiu.io.out.bits.toint io.cp_resp.valid := true.B } val ifpu = Module(new IntToFP(cfg.ifpuLatency)) ifpu.io.in.valid := req_valid && ex_ctrl.fromint ifpu.io.in.bits := fpiu.io.in.bits ifpu.io.in.bits.in1 := Mux(ex_cp_valid, io.cp_req.bits.in1, io.fromint_data) val fpmu = Module(new FPToFP(cfg.fpmuLatency)) fpmu.io.in.valid := req_valid && ex_ctrl.fastpipe fpmu.io.in.bits := fpiu.io.in.bits fpmu.io.lt := fpiu.io.out.bits.lt val divSqrt_wen = WireDefault(false.B) val divSqrt_inFlight = WireDefault(false.B) val divSqrt_waddr = Reg(UInt(5.W)) val divSqrt_cp = Reg(Bool()) val divSqrt_typeTag = Wire(UInt(log2Up(floatTypes.size).W)) val divSqrt_wdata = Wire(UInt((fLen+1).W)) val divSqrt_flags = Wire(UInt(FPConstants.FLAGS_SZ.W)) divSqrt_typeTag := DontCare divSqrt_wdata := DontCare divSqrt_flags := DontCare // writeback arbitration case class Pipe(p: Module, lat: Int, cond: (FPUCtrlSigs) => Bool, res: FPResult) val pipes = List( Pipe(fpmu, fpmu.latency, (c: FPUCtrlSigs) => c.fastpipe, fpmu.io.out.bits), Pipe(ifpu, ifpu.latency, (c: FPUCtrlSigs) => c.fromint, ifpu.io.out.bits), Pipe(sfma, sfma.latency, (c: FPUCtrlSigs) => c.fma && c.typeTagOut === S, sfma.io.out.bits)) ++ (fLen > 32).option({ val dfma = Module(new FPUFMAPipe(cfg.dfmaLatency, FType.D)) dfma.io.in.valid := req_valid && ex_ctrl.fma && ex_ctrl.typeTagOut === D dfma.io.in.bits := fuInput(Some(dfma.t)) Pipe(dfma, dfma.latency, (c: FPUCtrlSigs) => c.fma && c.typeTagOut === D, dfma.io.out.bits) }) ++ (minFLen == 16).option({ val hfma = Module(new FPUFMAPipe(cfg.sfmaLatency, FType.H)) hfma.io.in.valid := req_valid && ex_ctrl.fma && ex_ctrl.typeTagOut === H hfma.io.in.bits := fuInput(Some(hfma.t)) Pipe(hfma, hfma.latency, (c: FPUCtrlSigs) => c.fma && c.typeTagOut === H, hfma.io.out.bits) }) def latencyMask(c: FPUCtrlSigs, offset: Int) = { require(pipes.forall(_.lat >= offset)) pipes.map(p => Mux(p.cond(c), (1 << p.lat-offset).U, 0.U)).reduce(_\|_) } def pipeid(c: FPUCtrlSigs) = pipes.zipWithIndex.map(p => Mux(p._1.cond(c), p._2.U, 0.U)).reduce(_\|_) val maxLatency = pipes.map(_.lat).max val memLatencyMask = latencyMask(mem_ctrl, 2) class WBInfo extends Bundle { val rd = UInt(5.W) val typeTag = UInt(log2Up(floatTypes.size).W) val cp = Bool() val pipeid = UInt(log2Ceil(pipes.size).W) } val wen = RegInit(0.U((maxLatency-1).W)) val wbInfo = Reg(Vec(maxLatency-1, new WBInfo)) val mem_wen = mem_reg_valid && (mem_ctrl.fma \|\| mem_ctrl.fastpipe \|\| mem_ctrl.fromint) val write_port_busy = RegEnable(mem_wen && (memLatencyMask & latencyMask(ex_ctrl, 1)).orR \|\| (wen & latencyMask(ex_ctrl, 0)).orR, req_valid) ccover(mem_reg_valid && write_port_busy, "WB_STRUCTURAL", "structural hazard on writeback") for (i <- 0 until maxLatency-2) { when (wen(i+1)) { wbInfo(i) := wbInfo(i+1) } } wen := wen >> 1 when (mem_wen) { when (!killm) { wen := wen >> 1 \| memLatencyMask } for (i <- 0 until maxLatency-1) { when (!write_port_busy && memLatencyMask(i)) { wbInfo(i).cp := mem_cp_valid wbInfo(i).typeTag := mem_ctrl.typeTagOut wbInfo(i).pipeid := pipeid(mem_ctrl) wbInfo(i).rd := mem_reg_inst(11,7) } } } val waddr = Mux(divSqrt_wen, divSqrt_waddr, wbInfo(0).rd) val wb_cp = Mux(divSqrt_wen, divSqrt_cp, wbInfo(0).cp) val wtypeTag = Mux(divSqrt_wen, divSqrt_typeTag, wbInfo(0).typeTag) val wdata = box(Mux(divSqrt_wen, divSqrt_wdata, (pipes.map(_.res.data): Seq[UInt])(wbInfo(0).pipeid)), wtypeTag) val wexc = (pipes.map(_.res.exc): Seq[UInt])(wbInfo(0).pipeid) when ((!wbInfo(0).cp && wen(0)) \|\| divSqrt_wen) { assert(consistent(wdata)) regfile(waddr) := wdata if (enableCommitLog) { printf("f%d p%d 0x%x\n", waddr, waddr + 32.U, ieee(wdata)) } frfWriteBundle(1).wrdst := waddr frfWriteBundle(1).wrenf := true.B frfWriteBundle(1).wrdata := ieee(wdata) } if (useDebugROB) { DebugROB.pushWb(clock, reset, io.hartid, (!wbInfo(0).cp && wen(0)) \|\| divSqrt_wen, waddr + 32.U, ieee(wdata)) } when (wb_cp && (wen(0) \|\| divSqrt_wen)) { io.cp_resp.bits.data := wdata io.cp_resp.valid := true.B } assert(!io.cp_req.valid \|\| pipes.forall(_.lat == pipes.head.lat).B, s"FPU only supports coprocessor if FMA pipes have uniform latency ${pipes.map(_.lat)}") // Avoid structural hazards and nacking of external requests // toint responds in the MEM stage, so an incoming toint can induce a structural hazard against inflight FMAs io.cp_req.ready := !ex_reg_valid && !(cp_ctrl.toint && wen =/= 0.U) && !divSqrt_inFlight val wb_toint_valid = wb_reg_valid && wb_ctrl.toint val wb_toint_exc = RegEnable(fpiu.io.out.bits.exc, mem_ctrl.toint) io.fcsr_flags.valid := wb_toint_valid \|\| divSqrt_wen \|\| wen(0) io.fcsr_flags.bits := Mux(wb_toint_valid, wb_toint_exc, 0.U) \| Mux(divSqrt_wen, divSqrt_flags, 0.U) \| Mux(wen(0), wexc, 0.U) val divSqrt_write_port_busy = (mem_ctrl.div \|\| mem_ctrl.sqrt) && wen.orR io.fcsr_rdy := !(ex_reg_valid && ex_ctrl.wflags \|\| mem_reg_valid && mem_ctrl.wflags \|\| wb_reg_valid && wb_ctrl.toint \|\| wen.orR \|\| divSqrt_inFlight) io.nack_mem := (write_port_busy \|\| divSqrt_write_port_busy \|\| divSqrt_inFlight) && !mem_cp_valid io.dec <> id_ctrl def useScoreboard(f: ((Pipe, Int)) => Bool) = pipes.zipWithIndex.filter(_._1.lat > 3).map(x => f(x)).fold(false.B)(_\|\|_) io.sboard_set := wb_reg_valid && !wb_cp_valid && RegNext(useScoreboard(_._1.cond(mem_ctrl)) \|\| mem_ctrl.div \|\| mem_ctrl.sqrt \|\| mem_ctrl.vec) io.sboard_clr := !wb_cp_valid && (divSqrt_wen \|\| (wen(0) && useScoreboard(x => wbInfo(0).pipeid === x._2.U))) io.sboard_clra := waddr ccover(io.sboard_clr && load_wb, "DUAL_WRITEBACK", "load and FMA writeback on same cycle") // we don't currently support round-max-magnitude (rm=4) io.illegal_rm := io.inst(14,12).isOneOf(5.U, 6.U) \|\| io.inst(14,12) === 7.U && io.fcsr_rm >= 5.U if (cfg.divSqrt) { val divSqrt_inValid = mem_reg_valid && (mem_ctrl.div \|\| mem_ctrl.sqrt) && !divSqrt_inFlight val divSqrt_killed = RegNext(divSqrt_inValid && killm, true.B) when (divSqrt_inValid) { divSqrt_waddr := mem_reg_inst(11,7) divSqrt_cp := mem_cp_valid } ccover(divSqrt_inFlight && divSqrt_killed, "DIV_KILLED", "divide killed after issued to divider") ccover(divSqrt_inFlight && mem_reg_valid && (mem_ctrl.div \|\| mem_ctrl.sqrt), "DIV_BUSY", "divider structural hazard") ccover(mem_reg_valid && divSqrt_write_port_busy, "DIV_WB_STRUCTURAL", "structural hazard on division writeback") for (t <- floatTypes) { val tag = mem_ctrl.typeTagOut val divSqrt = withReset(divSqrt_killed) { Module(new hardfloat.DivSqrtRecFN_small(t.exp, t.sig, 0)) } divSqrt.io.inValid := divSqrt_inValid && tag === typeTag(t).U divSqrt.io.sqrtOp := mem_ctrl.sqrt divSqrt.io.a := maxType.unsafeConvert(fpiu.io.out.bits.in.in1, t) divSqrt.io.b := maxType.unsafeConvert(fpiu.io.out.bits.in.in2, t) divSqrt.io.roundingMode := fpiu.io.out.bits.in.rm divSqrt.io.detectTininess := hardfloat.consts.tininess_afterRounding when (!divSqrt.io.inReady) { divSqrt_inFlight := true.B } // only 1 in flight when (divSqrt.io.outValid_div \|\| divSqrt.io.outValid_sqrt) { divSqrt_wen := !divSqrt_killed divSqrt_wdata := sanitizeNaN(divSqrt.io.out, t) divSqrt_flags := divSqrt.io.exceptionFlags divSqrt_typeTag := typeTag(t).U } } when (divSqrt_killed) { divSqrt_inFlight := false.B } } else { when (id_ctrl.div \|\| id_ctrl.sqrt) { io.illegal_rm := true.B } } // gate the clock clock_en_reg := !useClockGating.B \|\| io.keep_clock_enabled \|\| // chicken bit io.valid \|\| // ID stage req_valid \|\| // EX stage mem_reg_valid \|\| mem_cp_valid \|\| // MEM stage wb_reg_valid \|\| wb_cp_valid \|\| // WB stage wen.orR \|\| divSqrt_inFlight \|\| // post-WB stage io.ll_resp_val // load writeback } // leaving gated-clock domain val fpuImpl = withClock (gated_clock) { new FPUImpl } def ccover(cond: Bool, label: String, desc: String)(implicit sourceInfo: SourceInfo) = property.cover(cond, s"FPU_$label", "Core;;" + desc) }	module FPUFMAPipe_l3_f16_6( // @[FPU.scala:697:7] input clock, // @[FPU.scala:697:7] input reset, // @[FPU.scala:697:7] input io_in_valid, // @[FPU.scala:702:14] input io_in_bits_ldst, // @[FPU.scala:702:14] input io_in_bits_wen, // @[FPU.scala:702:14] input io_in_bits_ren1, // @[FPU.scala:702:14] input io_in_bits_ren2, // @[FPU.scala:702:14] input io_in_bits_ren3, // @[FPU.scala:702:14] input io_in_bits_swap12, // @[FPU.scala:702:14] input io_in_bits_swap23, // @[FPU.scala:702:14] input [1:0] io_in_bits_typeTagIn, // @[FPU.scala:702:14] input [1:0] io_in_bits_typeTagOut, // @[FPU.scala:702:14] input io_in_bits_fromint, // @[FPU.scala:702:14] input io_in_bits_toint, // @[FPU.scala:702:14] input io_in_bits_fastpipe, // @[FPU.scala:702:14] input io_in_bits_fma, // @[FPU.scala:702:14] input io_in_bits_div, // @[FPU.scala:702:14] input io_in_bits_sqrt, // @[FPU.scala:702:14] input io_in_bits_wflags, // @[FPU.scala:702:14] input io_in_bits_vec, // @[FPU.scala:702:14] input [2:0] io_in_bits_rm, // @[FPU.scala:702:14] input [1:0] io_in_bits_fmaCmd, // @[FPU.scala:702:14] input [1:0] io_in_bits_typ, // @[FPU.scala:702:14] input [1:0] io_in_bits_fmt, // @[FPU.scala:702:14] input [64:0] io_in_bits_in1, // @[FPU.scala:702:14] input [64:0] io_in_bits_in2, // @[FPU.scala:702:14] input [64:0] io_in_bits_in3, // @[FPU.scala:702:14] output [64:0] io_out_bits_data, // @[FPU.scala:702:14] output [4:0] io_out_bits_exc // @[FPU.scala:702:14] ); wire [64:0] res_data; // @[FPU.scala:728:17] wire [16:0] _fma_io_out; // @[FPU.scala:719:19] wire io_in_valid_0 = io_in_valid; // @[FPU.scala:697:7] wire io_in_bits_ldst_0 = io_in_bits_ldst; // @[FPU.scala:697:7] wire io_in_bits_wen_0 = io_in_bits_wen; // @[FPU.scala:697:7] wire io_in_bits_ren1_0 = io_in_bits_ren1; // @[FPU.scala:697:7] wire io_in_bits_ren2_0 = io_in_bits_ren2; // @[FPU.scala:697:7] wire io_in_bits_ren3_0 = io_in_bits_ren3; // @[FPU.scala:697:7] wire io_in_bits_swap12_0 = io_in_bits_swap12; // @[FPU.scala:697:7] wire io_in_bits_swap23_0 = io_in_bits_swap23; // @[FPU.scala:697:7] wire [1:0] io_in_bits_typeTagIn_0 = io_in_bits_typeTagIn; // @[FPU.scala:697:7] wire [1:0] io_in_bits_typeTagOut_0 = io_in_bits_typeTagOut; // @[FPU.scala:697:7] wire io_in_bits_fromint_0 = io_in_bits_fromint; // @[FPU.scala:697:7] wire io_in_bits_toint_0 = io_in_bits_toint; // @[FPU.scala:697:7] wire io_in_bits_fastpipe_0 = io_in_bits_fastpipe; // @[FPU.scala:697:7] wire io_in_bits_fma_0 = io_in_bits_fma; // @[FPU.scala:697:7] wire io_in_bits_div_0 = io_in_bits_div; // @[FPU.scala:697:7] wire io_in_bits_sqrt_0 = io_in_bits_sqrt; // @[FPU.scala:697:7] wire io_in_bits_wflags_0 = io_in_bits_wflags; // @[FPU.scala:697:7] wire io_in_bits_vec_0 = io_in_bits_vec; // @[FPU.scala:697:7] wire [2:0] io_in_bits_rm_0 = io_in_bits_rm; // @[FPU.scala:697:7] wire [1:0] io_in_bits_fmaCmd_0 = io_in_bits_fmaCmd; // @[FPU.scala:697:7] wire [1:0] io_in_bits_typ_0 = io_in_bits_typ; // @[FPU.scala:697:7] wire [1:0] io_in_bits_fmt_0 = io_in_bits_fmt; // @[FPU.scala:697:7] wire [64:0] io_in_bits_in1_0 = io_in_bits_in1; // @[FPU.scala:697:7] wire [64:0] io_in_bits_in2_0 = io_in_bits_in2; // @[FPU.scala:697:7] wire [64:0] io_in_bits_in3_0 = io_in_bits_in3; // @[FPU.scala:697:7] wire [15:0] one = 16'h8000; // @[FPU.scala:710:19] wire [16:0] _zero_T_1 = 17'h10000; // @[FPU.scala:711:57] wire io_out_out_valid; // @[Valid.scala:135:21] wire [64:0] io_out_out_bits_data; // @[Valid.scala:135:21] wire [4:0] io_out_out_bits_exc; // @[Valid.scala:135:21] wire [64:0] io_out_bits_data_0; // @[FPU.scala:697:7] wire [4:0] io_out_bits_exc_0; // @[FPU.scala:697:7] wire io_out_valid; // @[FPU.scala:697:7] reg valid; // @[FPU.scala:707:22] reg in_ldst; // @[FPU.scala:708:15] reg in_wen; // @[FPU.scala:708:15] reg in_ren1; // @[FPU.scala:708:15] reg in_ren2; // @[FPU.scala:708:15] reg in_ren3; // @[FPU.scala:708:15] reg in_swap12; // @[FPU.scala:708:15] reg in_swap23; // @[FPU.scala:708:15] reg [1:0] in_typeTagIn; // @[FPU.scala:708:15] reg [1:0] in_typeTagOut; // @[FPU.scala:708:15] reg in_fromint; // @[FPU.scala:708:15] reg in_toint; // @[FPU.scala:708:15] reg in_fastpipe; // @[FPU.scala:708:15] reg in_fma; // @[FPU.scala:708:15] reg in_div; // @[FPU.scala:708:15] reg in_sqrt; // @[FPU.scala:708:15] reg in_wflags; // @[FPU.scala:708:15] reg in_vec; // @[FPU.scala:708:15] reg [2:0] in_rm; // @[FPU.scala:708:15] reg [1:0] in_fmaCmd; // @[FPU.scala:708:15] reg [1:0] in_typ; // @[FPU.scala:708:15] reg [1:0] in_fmt; // @[FPU.scala:708:15] reg [64:0] in_in1; // @[FPU.scala:708:15] reg [64:0] in_in2; // @[FPU.scala:708:15] reg [64:0] in_in3; // @[FPU.scala:708:15] wire [64:0] _zero_T = io_in_bits_in1_0 ^ io_in_bits_in2_0; // @[FPU.scala:697:7, :711:32] wire [64:0] zero = {48'h0, _zero_T[16], 16'h0}; // @[FPU.scala:711:{32,50}] assign io_out_out_bits_data = res_data; // @[Valid.scala:135:21] wire [4:0] res_exc; // @[FPU.scala:728:17] assign io_out_out_bits_exc = res_exc; // @[Valid.scala:135:21] assign res_data = {48'h0, _fma_io_out}; // @[FPU.scala:711:50, :719:19, :728:17, :729:12] assign io_out_valid = io_out_out_valid; // @[Valid.scala:135:21] assign io_out_bits_data_0 = io_out_out_bits_data; // @[Valid.scala:135:21] assign io_out_bits_exc_0 = io_out_out_bits_exc; // @[Valid.scala:135:21] always @(posedge clock) begin // @[FPU.scala:697:7] valid <= io_in_valid_0; // @[FPU.scala:697:7, :707:22] if (io_in_valid_0) begin // @[FPU.scala:697:7] in_ldst <= io_in_bits_ldst_0; // @[FPU.scala:697:7, :708:15] in_wen <= io_in_bits_wen_0; // @[FPU.scala:697:7, :708:15] in_ren1 <= io_in_bits_ren1_0; // @[FPU.scala:697:7, :708:15] in_ren2 <= io_in_bits_ren2_0; // @[FPU.scala:697:7, :708:15] in_ren3 <= io_in_bits_ren3_0; // @[FPU.scala:697:7, :708:15] in_swap12 <= io_in_bits_swap12_0; // @[FPU.scala:697:7, :708:15] in_swap23 <= io_in_bits_swap23_0; // @[FPU.scala:697:7, :708:15] in_typeTagIn <= io_in_bits_typeTagIn_0; // @[FPU.scala:697:7, :708:15] in_typeTagOut <= io_in_bits_typeTagOut_0; // @[FPU.scala:697:7, :708:15] in_fromint <= io_in_bits_fromint_0; // @[FPU.scala:697:7, :708:15] in_toint <= io_in_bits_toint_0; // @[FPU.scala:697:7, :708:15] in_fastpipe <= io_in_bits_fastpipe_0; // @[FPU.scala:697:7, :708:15] in_fma <= io_in_bits_fma_0; // @[FPU.scala:697:7, :708:15] in_div <= io_in_bits_div_0; // @[FPU.scala:697:7, :708:15] in_sqrt <= io_in_bits_sqrt_0; // @[FPU.scala:697:7, :708:15] in_wflags <= io_in_bits_wflags_0; // @[FPU.scala:697:7, :708:15] in_vec <= io_in_bits_vec_0; // @[FPU.scala:697:7, :708:15] in_rm <= io_in_bits_rm_0; // @[FPU.scala:697:7, :708:15] in_fmaCmd <= io_in_bits_fmaCmd_0; // @[FPU.scala:697:7, :708:15] in_typ <= io_in_bits_typ_0; // @[FPU.scala:697:7, :708:15] in_fmt <= io_in_bits_fmt_0; // @[FPU.scala:697:7, :708:15] in_in1 <= io_in_bits_in1_0; // @[FPU.scala:697:7, :708:15] in_in2 <= io_in_bits_swap23_0 ? 65'h8000 : io_in_bits_in2_0; // @[FPU.scala:697:7, :708:15, :714:8, :715:{23,32}] in_in3 <= io_in_bits_ren3_0 \| io_in_bits_swap23_0 ? io_in_bits_in3_0 : zero; // @[FPU.scala:697:7, :708:15, :711:50, :714:8, :716:{21,37,46}] end always @(posedge) MulAddRecFNPipe_l2_e5_s11_6 fma ( // @[FPU.scala:719:19] .clock (clock), .reset (reset), .io_validin (valid), // @[FPU.scala:707:22] .io_op (in_fmaCmd), // @[FPU.scala:708:15] .io_a (in_in1[16:0]), // @[FPU.scala:708:15, :724:12] .io_b (in_in2[16:0]), // @[FPU.scala:708:15, :725:12] .io_c (in_in3[16:0]), // @[FPU.scala:708:15, :726:12] .io_roundingMode (in_rm), // @[FPU.scala:708:15] .io_out (_fma_io_out), .io_exceptionFlags (res_exc), .io_validout (io_out_out_valid) ); // @[FPU.scala:719:19] assign io_out_bits_data = io_out_bits_data_0; // @[FPU.scala:697:7] assign io_out_bits_exc = io_out_bits_exc_0; // @[FPU.scala:697:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File Misc.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import scala.math._ class ParameterizedBundle(implicit p: Parameters) extends Bundle trait Clocked extends Bundle { val clock = Clock() val reset = Bool() } object DecoupledHelper { def apply(rvs: Bool) = new DecoupledHelper(rvs) } class DecoupledHelper(val rvs: Seq[Bool]) { def fire(exclude: Bool, includes: Bool) = { require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!") (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _) } def fire() = { rvs.reduce(_ && _) } } object MuxT { def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2)) def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3)) def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4)) } /** Creates a cascade of n MuxTs to search for a key value. / object MuxTLookup { def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } } object ValidMux { def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]): ValidIO[T] = { apply(v1 +: v2.toSeq) } def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = { val out = Wire(Valid(valids.head.bits.cloneType)) out.valid := valids.map(_.valid).reduce(_ \|\| _) out.bits := MuxCase(valids.head.bits, valids.map(v => (v.valid -> v.bits))) out } } object Str { def apply(s: String): UInt = { var i = BigInt(0) require(s.forall(validChar _)) for (c <- s) i = (i << 8) \| c i.U((s.length8).W) } def apply(x: Char): UInt = { require(validChar(x)) x.U(8.W) } def apply(x: UInt): UInt = apply(x, 10) def apply(x: UInt, radix: Int): UInt = { val rad = radix.U val w = x.getWidth require(w > 0) var q = x var s = digit(q % rad) for (i <- 1 until ceil(log(2)/log(radix)w).toInt) { q = q / rad s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s) } s } def apply(x: SInt): UInt = apply(x, 10) def apply(x: SInt, radix: Int): UInt = { val neg = x < 0.S val abs = x.abs.asUInt if (radix != 10) { Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix)) } else { val rad = radix.U val w = abs.getWidth require(w > 0) var q = abs var s = digit(q % rad) var needSign = neg for (i <- 1 until ceil(log(2)/log(radix)w).toInt) { q = q / rad val placeSpace = q === 0.U val space = Mux(needSign, Str('-'), Str(' ')) needSign = needSign && !placeSpace s = Cat(Mux(placeSpace, space, digit(q % rad)), s) } Cat(Mux(needSign, Str('-'), Str(' ')), s) } } private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0) private def validChar(x: Char) = x == (x & 0xFF) } object Split { def apply(x: UInt, n0: Int) = { val w = x.getWidth (x.extract(w-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n2: Int, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } } object Random { def apply(mod: Int, random: UInt): UInt = { if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0) else PriorityEncoder(partition(apply(1 << log2Up(mod8), random), mod)) } def apply(mod: Int): UInt = apply(mod, randomizer) def oneHot(mod: Int, random: UInt): UInt = { if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0)) else PriorityEncoderOH(partition(apply(1 << log2Up(mod8), random), mod)).asUInt } def oneHot(mod: Int): UInt = oneHot(mod, randomizer) private def randomizer = LFSR(16) private def partition(value: UInt, slices: Int) = Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U) } object Majority { def apply(in: Set[Bool]): Bool = { val n = (in.size >> 1) + 1 val clauses = in.subsets(n).map(_.reduce(_ && _)) clauses.reduce(_ \|\| _) } def apply(in: Seq[Bool]): Bool = apply(in.toSet) def apply(in: UInt): Bool = apply(in.asBools.toSet) } object PopCountAtLeast { private def two(x: UInt): (Bool, Bool) = x.getWidth match { case 1 => (x.asBool, false.B) case n => val half = x.getWidth / 2 val (leftOne, leftTwo) = two(x(half - 1, 0)) val (rightOne, rightTwo) = two(x(x.getWidth - 1, half)) (leftOne \|\| rightOne, leftTwo \|\| rightTwo \|\| (leftOne && rightOne)) } def apply(x: UInt, n: Int): Bool = n match { case 0 => true.B case 1 => x.orR case 2 => two(x)._2 case 3 => PopCount(x) >= n.U } } // This gets used everywhere, so make the smallest circuit possible ... // Given an address and size, create a mask of beatBytes size // eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111 // groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01 object MaskGen { def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = { require (groupBy >= 1 && beatBytes >= groupBy) require (isPow2(beatBytes) && isPow2(groupBy)) val lgBytes = log2Ceil(beatBytes) val sizeOH = UIntToOH(lgSize \| 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) \| (groupBy2 - 1).U def helper(i: Int): Seq[(Bool, Bool)] = { if (i == 0) { Seq((lgSize >= lgBytes.asUInt, true.B)) } else { val sub = helper(i-1) val size = sizeOH(lgBytes - i) val bit = addr_lo(lgBytes - i) val nbit = !bit Seq.tabulate (1 << i) { j => val (sub_acc, sub_eq) = sub(j/2) val eq = sub_eq && (if (j % 2 == 1) bit else nbit) val acc = sub_acc \|\| (size && eq) (acc, eq) } } } if (groupBy == beatBytes) 1.U else Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse) } } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /* Like Vec.apply(idx), but tolerates indices of mismatched width / def extract(idx: UInt): T = x((idx \| 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx \| 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def \| (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a \|\| b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_\|\|_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /* Any Data subtype that has a Bool member named valid. / type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /* converts from camel case to to underscores, also removing all spaces / def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /* converts spaces or underscores to hyphens, also lowering case / def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y \| (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y \|\| y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 \| 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /* Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation / def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File SourceD.scala: / * Copyright 2019 SiFive, Inc. * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You should have received a copy of LICENSE.Apache2 along with * this software. If not, you may obtain a copy at * * https://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. / package sifive.blocks.inclusivecache import chisel3._ import chisel3.util._ import freechips.rocketchip.tilelink._ import freechips.rocketchip.util._ import TLMessages._ import TLAtomics._ import TLPermissions._ class SourceDRequest(params: InclusiveCacheParameters) extends FullRequest(params) { val sink = UInt(params.inner.bundle.sinkBits.W) val way = UInt(params.wayBits.W) val bad = Bool() } class SourceDHazard(params: InclusiveCacheParameters) extends InclusiveCacheBundle(params) { val set = UInt(params.setBits.W) val way = UInt(params.wayBits.W) } class PutBufferACEntry(params: InclusiveCacheParameters) extends InclusiveCacheBundle(params) { val data = UInt(params.inner.bundle.dataBits.W) val mask = UInt((params.inner.bundle.dataBits/8).W) val corrupt = Bool() } class SourceD(params: InclusiveCacheParameters) extends Module { val io = IO(new Bundle { val req = Flipped(Decoupled(new SourceDRequest(params))) val d = Decoupled(new TLBundleD(params.inner.bundle)) // Put data from SinkA val pb_pop = Decoupled(new PutBufferPop(params)) val pb_beat = Flipped(new PutBufferAEntry(params)) // Release data from SinkC val rel_pop = Decoupled(new PutBufferPop(params)) val rel_beat = Flipped(new PutBufferCEntry(params)) // Access to the BankedStore val bs_radr = Decoupled(new BankedStoreInnerAddress(params)) val bs_rdat = Flipped(new BankedStoreInnerDecoded(params)) val bs_wadr = Decoupled(new BankedStoreInnerAddress(params)) val bs_wdat = new BankedStoreInnerPoison(params) // Is it safe to evict/replace this way? val evict_req = Flipped(new SourceDHazard(params)) val evict_safe = Bool() val grant_req = Flipped(new SourceDHazard(params)) val grant_safe = Bool() }) val beatBytes = params.inner.manager.beatBytes val writeBytes = params.micro.writeBytes val s1_valid = Wire(Bool()) val s2_valid = Wire(Bool()) val s3_valid = Wire(Bool()) val s2_ready = Wire(Bool()) val s3_ready = Wire(Bool()) val s4_ready = Wire(Bool()) ////////////////////////////////////// STAGE 1 ////////////////////////////////////// // Reform the request beats val busy = RegInit(false.B) val s1_block_r = RegInit(false.B) val s1_counter = RegInit(0.U(params.innerBeatBits.W)) val s1_req_reg = RegEnable(io.req.bits, !busy && io.req.valid) val s1_req = Mux(!busy, io.req.bits, s1_req_reg) val s1_x_bypass = Wire(UInt((beatBytes/writeBytes).W)) // might go from high=>low during stall val s1_latch_bypass = RegNext(!(busy \|\| io.req.valid) \|\| s2_ready) val s1_bypass = Mux(s1_latch_bypass, s1_x_bypass, RegEnable(s1_x_bypass, s1_latch_bypass)) val s1_mask = MaskGen(s1_req.offset, s1_req.size, beatBytes, writeBytes) & ~s1_bypass val s1_grant = (s1_req.opcode === AcquireBlock && s1_req.param === BtoT) \|\| s1_req.opcode === AcquirePerm val s1_need_r = s1_mask.orR && s1_req.prio(0) && s1_req.opcode =/= Hint && !s1_grant && (s1_req.opcode =/= PutFullData \|\| s1_req.size < log2Ceil(writeBytes).U ) val s1_valid_r = (busy \|\| io.req.valid) && s1_need_r && !s1_block_r val s1_need_pb = Mux(s1_req.prio(0), !s1_req.opcode(2), s1_req.opcode(0)) // hasData val s1_single = Mux(s1_req.prio(0), s1_req.opcode === Hint \|\| s1_grant, s1_req.opcode === Release) val s1_retires = !s1_single // retire all operations with data in s3 for bypass (saves energy) // Alternatively: val s1_retires = s1_need_pb // retire only updates for bypass (less backpressure from WB) val s1_beats1 = Mux(s1_single, 0.U, UIntToOH1(s1_req.size, log2Up(params.cache.blockBytes)) >> log2Ceil(beatBytes)) val s1_beat = (s1_req.offset >> log2Ceil(beatBytes)) \| s1_counter val s1_last = s1_counter === s1_beats1 val s1_first = s1_counter === 0.U params.ccover(s1_block_r, "SOURCED_1_SRAM_HOLD", "SRAM read-out successful, but stalled by stage 2") params.ccover(!s1_latch_bypass, "SOURCED_1_BYPASS_HOLD", "Bypass match successful, but stalled by stage 2") params.ccover((busy \|\| io.req.valid) && !s1_need_r, "SOURCED_1_NO_MODIFY", "Transaction servicable without SRAM") io.bs_radr.valid := s1_valid_r io.bs_radr.bits.noop := false.B io.bs_radr.bits.way := s1_req.way io.bs_radr.bits.set := s1_req.set io.bs_radr.bits.beat := s1_beat io.bs_radr.bits.mask := s1_mask params.ccover(io.bs_radr.valid && !io.bs_radr.ready, "SOURCED_1_READ_STALL", "Data readout stalled") // Make a queue to catch BS readout during stalls val queue = Module(new Queue(chiselTypeOf(io.bs_rdat), 3, flow=true)) queue.io.enq.valid := RegNext(RegNext(io.bs_radr.fire)) queue.io.enq.bits := io.bs_rdat assert (!queue.io.enq.valid \|\| queue.io.enq.ready) params.ccover(!queue.io.enq.ready, "SOURCED_1_QUEUE_FULL", "Filled SRAM skidpad queue completely") when (io.bs_radr.fire) { s1_block_r := true.B } when (io.req.valid) { busy := true.B } when (s1_valid && s2_ready) { s1_counter := s1_counter + 1.U s1_block_r := false.B when (s1_last) { s1_counter := 0.U busy := false.B } } params.ccover(s1_valid && !s2_ready, "SOURCED_1_STALL", "Stage 1 pipeline blocked") io.req.ready := !busy s1_valid := (busy \|\| io.req.valid) && (!s1_valid_r \|\| io.bs_radr.ready) ////////////////////////////////////// STAGE 2 ////////////////////////////////////// // Fetch the request data val s2_latch = s1_valid && s2_ready val s2_full = RegInit(false.B) val s2_valid_pb = RegInit(false.B) val s2_beat = RegEnable(s1_beat, s2_latch) val s2_bypass = RegEnable(s1_bypass, s2_latch) val s2_req = RegEnable(s1_req, s2_latch) val s2_last = RegEnable(s1_last, s2_latch) val s2_need_r = RegEnable(s1_need_r, s2_latch) val s2_need_pb = RegEnable(s1_need_pb, s2_latch) val s2_retires = RegEnable(s1_retires, s2_latch) val s2_need_d = RegEnable(!s1_need_pb \|\| s1_first, s2_latch) val s2_pdata_raw = Wire(new PutBufferACEntry(params)) val s2_pdata = s2_pdata_raw holdUnless s2_valid_pb s2_pdata_raw.data := Mux(s2_req.prio(0), io.pb_beat.data, io.rel_beat.data) s2_pdata_raw.mask := Mux(s2_req.prio(0), io.pb_beat.mask, ~0.U(params.inner.manager.beatBytes.W)) s2_pdata_raw.corrupt := Mux(s2_req.prio(0), io.pb_beat.corrupt, io.rel_beat.corrupt) io.pb_pop.valid := s2_valid_pb && s2_req.prio(0) io.pb_pop.bits.index := s2_req.put io.pb_pop.bits.last := s2_last io.rel_pop.valid := s2_valid_pb && !s2_req.prio(0) io.rel_pop.bits.index := s2_req.put io.rel_pop.bits.last := s2_last params.ccover(io.pb_pop.valid && !io.pb_pop.ready, "SOURCED_2_PUTA_STALL", "Channel A put buffer was not ready in time") if (!params.firstLevel) params.ccover(io.rel_pop.valid && !io.rel_pop.ready, "SOURCED_2_PUTC_STALL", "Channel C put buffer was not ready in time") val pb_ready = Mux(s2_req.prio(0), io.pb_pop.ready, io.rel_pop.ready) when (pb_ready) { s2_valid_pb := false.B } when (s2_valid && s3_ready) { s2_full := false.B } when (s2_latch) { s2_valid_pb := s1_need_pb } when (s2_latch) { s2_full := true.B } params.ccover(s2_valid && !s3_ready, "SOURCED_2_STALL", "Stage 2 pipeline blocked") s2_valid := s2_full && (!s2_valid_pb \|\| pb_ready) s2_ready := !s2_full \|\| (s3_ready && (!s2_valid_pb \|\| pb_ready)) ////////////////////////////////////// STAGE 3 ////////////////////////////////////// // Send D response val s3_latch = s2_valid && s3_ready val s3_full = RegInit(false.B) val s3_valid_d = RegInit(false.B) val s3_beat = RegEnable(s2_beat, s3_latch) val s3_bypass = RegEnable(s2_bypass, s3_latch) val s3_req = RegEnable(s2_req, s3_latch) val s3_adjusted_opcode = Mux(s3_req.bad, Get, s3_req.opcode) // kill update when denied val s3_last = RegEnable(s2_last, s3_latch) val s3_pdata = RegEnable(s2_pdata, s3_latch) val s3_need_pb = RegEnable(s2_need_pb, s3_latch) val s3_retires = RegEnable(s2_retires, s3_latch) val s3_need_r = RegEnable(s2_need_r, s3_latch) val s3_need_bs = s3_need_pb val s3_acq = s3_req.opcode === AcquireBlock \|\| s3_req.opcode === AcquirePerm // Collect s3's data from either the BankedStore or bypass // NOTE: we use the s3_bypass passed down from s1_bypass, because s2-s4 were guarded by the hazard checks and not stale val s3_bypass_data = Wire(UInt()) def chunk(x: UInt): Seq[UInt] = Seq.tabulate(beatBytes/writeBytes) { i => x((i+1)writeBytes8-1, iwriteBytes*8) } def chop (x: UInt): Seq[Bool] = Seq.tabulate(beatBytes/writeBytes) { i => x(i) } def bypass(sel: UInt, x: UInt, y: UInt) = (chop(sel) zip (chunk(x) zip chunk(y))) .map { case (s, (x, y)) => Mux(s, x, y) } .asUInt val s3_rdata = bypass(s3_bypass, s3_bypass_data, queue.io.deq.bits.data) // Lookup table for response codes val grant = Mux(s3_req.param === BtoT, Grant, GrantData) val resp_opcode = VecInit(Seq(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, grant, Grant)) // No restrictions on the type of buffer used here val d = Wire(chiselTypeOf(io.d)) io.d <> params.micro.innerBuf.d(d) d.valid := s3_valid_d d.bits.opcode := Mux(s3_req.prio(0), resp_opcode(s3_req.opcode), ReleaseAck) d.bits.param := Mux(s3_req.prio(0) && s3_acq, Mux(s3_req.param =/= NtoB, toT, toB), 0.U) d.bits.size := s3_req.size d.bits.source := s3_req.source d.bits.sink := s3_req.sink d.bits.denied := s3_req.bad d.bits.data := s3_rdata d.bits.corrupt := s3_req.bad && d.bits.opcode(0) queue.io.deq.ready := s3_valid && s4_ready && s3_need_r assert (!s3_full \|\| !s3_need_r \|\| queue.io.deq.valid) when (d.ready) { s3_valid_d := false.B } when (s3_valid && s4_ready) { s3_full := false.B } when (s3_latch) { s3_valid_d := s2_need_d } when (s3_latch) { s3_full := true.B } params.ccover(s3_valid && !s4_ready, "SOURCED_3_STALL", "Stage 3 pipeline blocked") s3_valid := s3_full && (!s3_valid_d \|\| d.ready) s3_ready := !s3_full \|\| (s4_ready && (!s3_valid_d \|\| d.ready)) ////////////////////////////////////// STAGE 4 ////////////////////////////////////// // Writeback updated data val s4_latch = s3_valid && s3_retires && s4_ready val s4_full = RegInit(false.B) val s4_beat = RegEnable(s3_beat, s4_latch) val s4_need_r = RegEnable(s3_need_r, s4_latch) val s4_need_bs = RegEnable(s3_need_bs, s4_latch) val s4_need_pb = RegEnable(s3_need_pb, s4_latch) val s4_req = RegEnable(s3_req, s4_latch) val s4_adjusted_opcode = RegEnable(s3_adjusted_opcode, s4_latch) val s4_pdata = RegEnable(s3_pdata, s4_latch) val s4_rdata = RegEnable(s3_rdata, s4_latch) val atomics = Module(new Atomics(params.inner.bundle)) atomics.io.write := s4_req.prio(2) atomics.io.a.opcode := s4_adjusted_opcode atomics.io.a.param := s4_req.param atomics.io.a.size := 0.U atomics.io.a.source := 0.U atomics.io.a.address := 0.U atomics.io.a.mask := s4_pdata.mask atomics.io.a.data := s4_pdata.data atomics.io.a.corrupt := DontCare atomics.io.data_in := s4_rdata io.bs_wadr.valid := s4_full && s4_need_bs io.bs_wadr.bits.noop := false.B io.bs_wadr.bits.way := s4_req.way io.bs_wadr.bits.set := s4_req.set io.bs_wadr.bits.beat := s4_beat io.bs_wadr.bits.mask := Cat(s4_pdata.mask.asBools.grouped(writeBytes).map(_.reduce(_\|\|_)).toList.reverse) io.bs_wdat.data := atomics.io.data_out assert (!(s4_full && s4_need_pb && s4_pdata.corrupt), "Data poisoning unsupported") params.ccover(io.bs_wadr.valid && !io.bs_wadr.ready, "SOURCED_4_WRITEBACK_STALL", "Data writeback stalled") params.ccover(s4_req.prio(0) && s4_req.opcode === ArithmeticData && s4_req.param === MIN, "SOURCED_4_ATOMIC_MIN", "Evaluated a signed minimum atomic") params.ccover(s4_req.prio(0) && s4_req.opcode === ArithmeticData && s4_req.param === MAX, "SOURCED_4_ATOMIC_MAX", "Evaluated a signed maximum atomic") params.ccover(s4_req.prio(0) && s4_req.opcode === ArithmeticData && s4_req.param === MINU, "SOURCED_4_ATOMIC_MINU", "Evaluated an unsigned minimum atomic") params.ccover(s4_req.prio(0) && s4_req.opcode === ArithmeticData && s4_req.param === MAXU, "SOURCED_4_ATOMIC_MAXU", "Evaluated an unsigned minimum atomic") params.ccover(s4_req.prio(0) && s4_req.opcode === ArithmeticData && s4_req.param === ADD, "SOURCED_4_ATOMIC_ADD", "Evaluated an addition atomic") params.ccover(s4_req.prio(0) && s4_req.opcode === LogicalData && s4_req.param === XOR, "SOURCED_4_ATOMIC_XOR", "Evaluated a bitwise XOR atomic") params.ccover(s4_req.prio(0) && s4_req.opcode === LogicalData && s4_req.param === OR, "SOURCED_4_ATOMIC_OR", "Evaluated a bitwise OR atomic") params.ccover(s4_req.prio(0) && s4_req.opcode === LogicalData && s4_req.param === AND, "SOURCED_4_ATOMIC_AND", "Evaluated a bitwise AND atomic") params.ccover(s4_req.prio(0) && s4_req.opcode === LogicalData && s4_req.param === SWAP, "SOURCED_4_ATOMIC_SWAP", "Evaluated a bitwise SWAP atomic") when (io.bs_wadr.ready \|\| !s4_need_bs) { s4_full := false.B } when (s4_latch) { s4_full := true.B } s4_ready := !s3_retires \|\| !s4_full \|\| io.bs_wadr.ready \|\| !s4_need_bs ////////////////////////////////////// RETIRED ////////////////////////////////////// // Record for bypass the last three retired writebacks // We need 3 slots to collect what was in s2, s3, s4 when the request was in s1 // ... you can't rely on s4 being full if bubbles got introduced between s1 and s2 val retire = s4_full && (io.bs_wadr.ready \|\| !s4_need_bs) val s5_req = RegEnable(s4_req, retire) val s5_beat = RegEnable(s4_beat, retire) val s5_dat = RegEnable(atomics.io.data_out, retire) val s6_req = RegEnable(s5_req, retire) val s6_beat = RegEnable(s5_beat, retire) val s6_dat = RegEnable(s5_dat, retire) val s7_dat = RegEnable(s6_dat, retire) ////////////////////////////////////// BYPASSS ////////////////////////////////////// // Manually retime this circuit to pull a register stage forward val pre_s3_req = Mux(s3_latch, s2_req, s3_req) val pre_s4_req = Mux(s4_latch, s3_req, s4_req) val pre_s5_req = Mux(retire, s4_req, s5_req) val pre_s6_req = Mux(retire, s5_req, s6_req) val pre_s3_beat = Mux(s3_latch, s2_beat, s3_beat) val pre_s4_beat = Mux(s4_latch, s3_beat, s4_beat) val pre_s5_beat = Mux(retire, s4_beat, s5_beat) val pre_s6_beat = Mux(retire, s5_beat, s6_beat) val pre_s5_dat = Mux(retire, atomics.io.data_out, s5_dat) val pre_s6_dat = Mux(retire, s5_dat, s6_dat) val pre_s7_dat = Mux(retire, s6_dat, s7_dat) val pre_s4_full = s4_latch \|\| (!(io.bs_wadr.ready \|\| !s4_need_bs) && s4_full) val pre_s3_4_match = pre_s4_req.set === pre_s3_req.set && pre_s4_req.way === pre_s3_req.way && pre_s4_beat === pre_s3_beat && pre_s4_full val pre_s3_5_match = pre_s5_req.set === pre_s3_req.set && pre_s5_req.way === pre_s3_req.way && pre_s5_beat === pre_s3_beat val pre_s3_6_match = pre_s6_req.set === pre_s3_req.set && pre_s6_req.way === pre_s3_req.way && pre_s6_beat === pre_s3_beat val pre_s3_4_bypass = Mux(pre_s3_4_match, MaskGen(pre_s4_req.offset, pre_s4_req.size, beatBytes, writeBytes), 0.U) val pre_s3_5_bypass = Mux(pre_s3_5_match, MaskGen(pre_s5_req.offset, pre_s5_req.size, beatBytes, writeBytes), 0.U) val pre_s3_6_bypass = Mux(pre_s3_6_match, MaskGen(pre_s6_req.offset, pre_s6_req.size, beatBytes, writeBytes), 0.U) s3_bypass_data := bypass(RegNext(pre_s3_4_bypass), atomics.io.data_out, RegNext( bypass(pre_s3_5_bypass, pre_s5_dat, bypass(pre_s3_6_bypass, pre_s6_dat, pre_s7_dat)))) // Detect which parts of s1 will be bypassed from later pipeline stages (s1-s4) // Note: we also bypass from reads ahead in the pipeline to save power val s1_2_match = s2_req.set === s1_req.set && s2_req.way === s1_req.way && s2_beat === s1_beat && s2_full && s2_retires val s1_3_match = s3_req.set === s1_req.set && s3_req.way === s1_req.way && s3_beat === s1_beat && s3_full && s3_retires val s1_4_match = s4_req.set === s1_req.set && s4_req.way === s1_req.way && s4_beat === s1_beat && s4_full for (i <- 0 until 8) { val cover = 1.U val s2 = s1_2_match === cover(0) val s3 = s1_3_match === cover(1) val s4 = s1_4_match === cover(2) params.ccover(io.req.valid && s2 && s3 && s4, "SOURCED_BYPASS_CASE_" + i, "Bypass data from all subsets of pipeline stages") } val s1_2_bypass = Mux(s1_2_match, MaskGen(s2_req.offset, s2_req.size, beatBytes, writeBytes), 0.U) val s1_3_bypass = Mux(s1_3_match, MaskGen(s3_req.offset, s3_req.size, beatBytes, writeBytes), 0.U) val s1_4_bypass = Mux(s1_4_match, MaskGen(s4_req.offset, s4_req.size, beatBytes, writeBytes), 0.U) s1_x_bypass := s1_2_bypass \| s1_3_bypass \| s1_4_bypass ////////////////////////////////////// HAZARDS ////////////////////////////////////// // SinkC, SourceC, and SinkD can never interfer with each other because their operation // is fully contained with an execution plan of an MSHR. That MSHR owns the entire set, so // there is no way for a data race. // However, SourceD is special. We allow it to run ahead after the MSHR and scheduler have // released control of a set+way. This is necessary to allow single cycle occupancy for // hits. Thus, we need to be careful about data hazards between SourceD and the other ports // of the BankedStore. We can at least compare to registers 's1_req_reg', because the first // cycle of SourceD falls within the occupancy of the MSHR's plan. // Must ReleaseData=> be interlocked? RaW hazard io.evict_safe := (!busy \|\| io.evict_req.way =/= s1_req_reg.way \|\| io.evict_req.set =/= s1_req_reg.set) && (!s2_full \|\| io.evict_req.way =/= s2_req.way \|\| io.evict_req.set =/= s2_req.set) && (!s3_full \|\| io.evict_req.way =/= s3_req.way \|\| io.evict_req.set =/= s3_req.set) && (!s4_full \|\| io.evict_req.way =/= s4_req.way \|\| io.evict_req.set =/= s4_req.set) // Must =>GrantData be interlocked? WaR hazard io.grant_safe := (!busy \|\| io.grant_req.way =/= s1_req_reg.way \|\| io.grant_req.set =/= s1_req_reg.set) && (!s2_full \|\| io.grant_req.way =/= s2_req.way \|\| io.grant_req.set =/= s2_req.set) && (!s3_full \|\| io.grant_req.way =/= s3_req.way \|\| io.grant_req.set =/= s3_req.set) && (!s4_full \|\| io.grant_req.way =/= s4_req.way \|\| io.grant_req.set =/= s4_req.set) // SourceD cannot overlap with SinkC b/c the only way inner caches could become // dirty such that they want to put data in via SinkC is if we Granted them permissions, // which must flow through the SourecD pipeline. }	module SourceD( // @[SourceD.scala:48:7] input clock, // @[SourceD.scala:48:7] input reset, // @[SourceD.scala:48:7] output io_req_ready, // @[SourceD.scala:50:14] input io_req_valid, // @[SourceD.scala:50:14] input io_req_bits_prio_0, // @[SourceD.scala:50:14] input io_req_bits_prio_1, // @[SourceD.scala:50:14] input io_req_bits_prio_2, // @[SourceD.scala:50:14] input io_req_bits_control, // @[SourceD.scala:50:14] input [2:0] io_req_bits_opcode, // @[SourceD.scala:50:14] input [2:0] io_req_bits_param, // @[SourceD.scala:50:14] input [2:0] io_req_bits_size, // @[SourceD.scala:50:14] input [4:0] io_req_bits_source, // @[SourceD.scala:50:14] input [11:0] io_req_bits_tag, // @[SourceD.scala:50:14] input [5:0] io_req_bits_offset, // @[SourceD.scala:50:14] input [5:0] io_req_bits_put, // @[SourceD.scala:50:14] input [9:0] io_req_bits_set, // @[SourceD.scala:50:14] input [2:0] io_req_bits_sink, // @[SourceD.scala:50:14] input [2:0] io_req_bits_way, // @[SourceD.scala:50:14] input io_req_bits_bad, // @[SourceD.scala:50:14] input io_d_ready, // @[SourceD.scala:50:14] output io_d_valid, // @[SourceD.scala:50:14] output [2:0] io_d_bits_opcode, // @[SourceD.scala:50:14] output [1:0] io_d_bits_param, // @[SourceD.scala:50:14] output [2:0] io_d_bits_size, // @[SourceD.scala:50:14] output [4:0] io_d_bits_source, // @[SourceD.scala:50:14] output [2:0] io_d_bits_sink, // @[SourceD.scala:50:14] output io_d_bits_denied, // @[SourceD.scala:50:14] output [63:0] io_d_bits_data, // @[SourceD.scala:50:14] output io_d_bits_corrupt, // @[SourceD.scala:50:14] input io_pb_pop_ready, // @[SourceD.scala:50:14] output io_pb_pop_valid, // @[SourceD.scala:50:14] output [5:0] io_pb_pop_bits_index, // @[SourceD.scala:50:14] output io_pb_pop_bits_last, // @[SourceD.scala:50:14] input [63:0] io_pb_beat_data, // @[SourceD.scala:50:14] input [7:0] io_pb_beat_mask, // @[SourceD.scala:50:14] input io_pb_beat_corrupt, // @[SourceD.scala:50:14] input io_rel_pop_ready, // @[SourceD.scala:50:14] output io_rel_pop_valid, // @[SourceD.scala:50:14] output [5:0] io_rel_pop_bits_index, // @[SourceD.scala:50:14] output io_rel_pop_bits_last, // @[SourceD.scala:50:14] input [63:0] io_rel_beat_data, // @[SourceD.scala:50:14] input io_rel_beat_corrupt, // @[SourceD.scala:50:14] input io_bs_radr_ready, // @[SourceD.scala:50:14] output io_bs_radr_valid, // @[SourceD.scala:50:14] output [2:0] io_bs_radr_bits_way, // @[SourceD.scala:50:14] output [9:0] io_bs_radr_bits_set, // @[SourceD.scala:50:14] output [2:0] io_bs_radr_bits_beat, // @[SourceD.scala:50:14] output io_bs_radr_bits_mask, // @[SourceD.scala:50:14] input [63:0] io_bs_rdat_data, // @[SourceD.scala:50:14] input io_bs_wadr_ready, // @[SourceD.scala:50:14] output io_bs_wadr_valid, // @[SourceD.scala:50:14] output [2:0] io_bs_wadr_bits_way, // @[SourceD.scala:50:14] output [9:0] io_bs_wadr_bits_set, // @[SourceD.scala:50:14] output [2:0] io_bs_wadr_bits_beat, // @[SourceD.scala:50:14] output io_bs_wadr_bits_mask, // @[SourceD.scala:50:14] output [63:0] io_bs_wdat_data, // @[SourceD.scala:50:14] input [9:0] io_evict_req_set, // @[SourceD.scala:50:14] input [2:0] io_evict_req_way, // @[SourceD.scala:50:14] output io_evict_safe, // @[SourceD.scala:50:14] input [9:0] io_grant_req_set, // @[SourceD.scala:50:14] input [2:0] io_grant_req_way, // @[SourceD.scala:50:14] output io_grant_safe // @[SourceD.scala:50:14] ); wire [63:0] _atomics_io_data_out; // @[SourceD.scala:258:23] wire _queue_io_enq_ready; // @[SourceD.scala:120:21] wire _queue_io_deq_valid; // @[SourceD.scala:120:21] wire io_req_valid_0 = io_req_valid; // @[SourceD.scala:48:7] wire io_req_bits_prio_0_0 = io_req_bits_prio_0; // @[SourceD.scala:48:7] wire io_req_bits_prio_1_0 = io_req_bits_prio_1; // @[SourceD.scala:48:7] wire io_req_bits_prio_2_0 = io_req_bits_prio_2; // @[SourceD.scala:48:7] wire io_req_bits_control_0 = io_req_bits_control; // @[SourceD.scala:48:7] wire [2:0] io_req_bits_opcode_0 = io_req_bits_opcode; // @[SourceD.scala:48:7] wire [2:0] io_req_bits_param_0 = io_req_bits_param; // @[SourceD.scala:48:7] wire [2:0] io_req_bits_size_0 = io_req_bits_size; // @[SourceD.scala:48:7] wire [4:0] io_req_bits_source_0 = io_req_bits_source; // @[SourceD.scala:48:7] wire [11:0] io_req_bits_tag_0 = io_req_bits_tag; // @[SourceD.scala:48:7] wire [5:0] io_req_bits_offset_0 = io_req_bits_offset; // @[SourceD.scala:48:7] wire [5:0] io_req_bits_put_0 = io_req_bits_put; // @[SourceD.scala:48:7] wire [9:0] io_req_bits_set_0 = io_req_bits_set; // @[SourceD.scala:48:7] wire [2:0] io_req_bits_sink_0 = io_req_bits_sink; // @[SourceD.scala:48:7] wire [2:0] io_req_bits_way_0 = io_req_bits_way; // @[SourceD.scala:48:7] wire io_req_bits_bad_0 = io_req_bits_bad; // @[SourceD.scala:48:7] wire io_d_ready_0 = io_d_ready; // @[SourceD.scala:48:7] wire io_pb_pop_ready_0 = io_pb_pop_ready; // @[SourceD.scala:48:7] wire [63:0] io_pb_beat_data_0 = io_pb_beat_data; // @[SourceD.scala:48:7] wire [7:0] io_pb_beat_mask_0 = io_pb_beat_mask; // @[SourceD.scala:48:7] wire io_pb_beat_corrupt_0 = io_pb_beat_corrupt; // @[SourceD.scala:48:7] wire io_rel_pop_ready_0 = io_rel_pop_ready; // @[SourceD.scala:48:7] wire [63:0] io_rel_beat_data_0 = io_rel_beat_data; // @[SourceD.scala:48:7] wire io_rel_beat_corrupt_0 = io_rel_beat_corrupt; // @[SourceD.scala:48:7] wire io_bs_radr_ready_0 = io_bs_radr_ready; // @[SourceD.scala:48:7] wire [63:0] io_bs_rdat_data_0 = io_bs_rdat_data; // @[SourceD.scala:48:7] wire io_bs_wadr_ready_0 = io_bs_wadr_ready; // @[SourceD.scala:48:7] wire [9:0] io_evict_req_set_0 = io_evict_req_set; // @[SourceD.scala:48:7] wire [2:0] io_evict_req_way_0 = io_evict_req_way; // @[SourceD.scala:48:7] wire [9:0] io_grant_req_set_0 = io_grant_req_set; // @[SourceD.scala:48:7] wire [2:0] io_grant_req_way_0 = io_grant_req_way; // @[SourceD.scala:48:7] wire io_bs_radr_bits_noop = 1'h0; // @[SourceD.scala:48:7] wire io_bs_wadr_bits_noop = 1'h0; // @[SourceD.scala:48:7] wire [3:0] s1_mask_sizeOH = 4'hF; // @[Misc.scala:202:81] wire [3:0] pre_s3_4_bypass_sizeOH = 4'hF; // @[Misc.scala:202:81] wire [3:0] pre_s3_5_bypass_sizeOH = 4'hF; // @[Misc.scala:202:81] wire [3:0] pre_s3_6_bypass_sizeOH = 4'hF; // @[Misc.scala:202:81] wire [3:0] s1_2_bypass_sizeOH = 4'hF; // @[Misc.scala:202:81] wire [3:0] s1_3_bypass_sizeOH = 4'hF; // @[Misc.scala:202:81] wire [3:0] s1_4_bypass_sizeOH = 4'hF; // @[Misc.scala:202:81] wire [2:0] resp_opcode_0 = 3'h0; // @[SourceD.scala:215:28] wire [2:0] resp_opcode_1 = 3'h0; // @[SourceD.scala:215:28] wire [2:0] resp_opcode_7 = 3'h4; // @[SourceD.scala:215:28] wire [2:0] resp_opcode_5 = 3'h2; // @[SourceD.scala:215:28] wire [2:0] resp_opcode_2 = 3'h1; // @[SourceD.scala:215:28] wire [2:0] resp_opcode_3 = 3'h1; // @[SourceD.scala:215:28] wire [2:0] resp_opcode_4 = 3'h1; // @[SourceD.scala:215:28] wire [7:0] _s2_pdata_raw_mask_T = 8'hFF; // @[SourceD.scala:161:64] wire _io_req_ready_T; // @[SourceD.scala:140:19] wire d_ready = io_d_ready_0; // @[SourceD.scala:48:7, :218:15] wire d_valid; // @[SourceD.scala:218:15] wire [2:0] d_bits_opcode; // @[SourceD.scala:218:15] wire [1:0] d_bits_param; // @[SourceD.scala:218:15] wire [2:0] d_bits_size; // @[SourceD.scala:218:15] wire [4:0] d_bits_source; // @[SourceD.scala:218:15] wire [2:0] d_bits_sink; // @[SourceD.scala:218:15] wire d_bits_denied; // @[SourceD.scala:218:15] wire [63:0] d_bits_data; // @[SourceD.scala:218:15] wire d_bits_corrupt; // @[SourceD.scala:218:15] wire _io_pb_pop_valid_T; // @[SourceD.scala:164:34] wire _io_rel_pop_valid_T_1; // @[SourceD.scala:167:35] wire s1_valid_r; // @[SourceD.scala:96:56] wire [2:0] s1_req_way; // @[SourceD.scala:88:19] wire [9:0] s1_req_set; // @[SourceD.scala:88:19] wire [2:0] s1_beat; // @[SourceD.scala:102:56] wire s1_mask; // @[SourceD.scala:92:76] wire _io_bs_wadr_valid_T; // @[SourceD.scala:270:31] wire _io_bs_wadr_bits_mask_T_14; // @[SourceD.scala:275:87] wire _io_evict_safe_T_22; // @[SourceD.scala:378:90] wire _io_grant_safe_T_22; // @[SourceD.scala:385:90] wire io_req_ready_0; // @[SourceD.scala:48:7] wire [2:0] io_d_bits_opcode_0; // @[SourceD.scala:48:7] wire [1:0] io_d_bits_param_0; // @[SourceD.scala:48:7] wire [2:0] io_d_bits_size_0; // @[SourceD.scala:48:7] wire [4:0] io_d_bits_source_0; // @[SourceD.scala:48:7] wire [2:0] io_d_bits_sink_0; // @[SourceD.scala:48:7] wire io_d_bits_denied_0; // @[SourceD.scala:48:7] wire [63:0] io_d_bits_data_0; // @[SourceD.scala:48:7] wire io_d_bits_corrupt_0; // @[SourceD.scala:48:7] wire io_d_valid_0; // @[SourceD.scala:48:7] wire [5:0] io_pb_pop_bits_index_0; // @[SourceD.scala:48:7] wire io_pb_pop_bits_last_0; // @[SourceD.scala:48:7] wire io_pb_pop_valid_0; // @[SourceD.scala:48:7] wire [5:0] io_rel_pop_bits_index_0; // @[SourceD.scala:48:7] wire io_rel_pop_bits_last_0; // @[SourceD.scala:48:7] wire io_rel_pop_valid_0; // @[SourceD.scala:48:7] wire [2:0] io_bs_radr_bits_way_0; // @[SourceD.scala:48:7] wire [9:0] io_bs_radr_bits_set_0; // @[SourceD.scala:48:7] wire [2:0] io_bs_radr_bits_beat_0; // @[SourceD.scala:48:7] wire io_bs_radr_bits_mask_0; // @[SourceD.scala:48:7] wire io_bs_radr_valid_0; // @[SourceD.scala:48:7] wire [2:0] io_bs_wadr_bits_way_0; // @[SourceD.scala:48:7] wire [9:0] io_bs_wadr_bits_set_0; // @[SourceD.scala:48:7] wire [2:0] io_bs_wadr_bits_beat_0; // @[SourceD.scala:48:7] wire io_bs_wadr_bits_mask_0; // @[SourceD.scala:48:7] wire io_bs_wadr_valid_0; // @[SourceD.scala:48:7] wire [63:0] io_bs_wdat_data_0; // @[SourceD.scala:48:7] wire io_evict_safe_0; // @[SourceD.scala:48:7] wire io_grant_safe_0; // @[SourceD.scala:48:7] wire _s1_valid_T_3; // @[SourceD.scala:141:38] wire s1_valid; // @[SourceD.scala:74:22] wire _s2_valid_T_2; // @[SourceD.scala:183:23] wire s2_valid; // @[SourceD.scala:75:22] wire _s3_valid_T_2; // @[SourceD.scala:241:23] wire s3_valid; // @[SourceD.scala:76:22] wire _s2_ready_T_4; // @[SourceD.scala:184:24] wire s2_ready; // @[SourceD.scala:77:22] wire _s3_ready_T_4; // @[SourceD.scala:242:24] wire s3_ready; // @[SourceD.scala:78:22] wire _s4_ready_T_5; // @[SourceD.scala:293:59] wire s4_ready; // @[SourceD.scala:79:22] reg busy; // @[SourceD.scala:84:21] reg s1_block_r; // @[SourceD.scala:85:27] reg [2:0] s1_counter; // @[SourceD.scala:86:27] wire _s1_req_reg_T = ~busy; // @[SourceD.scala:84:21, :87:43] wire _s1_req_reg_T_1 = _s1_req_reg_T & io_req_valid_0; // @[SourceD.scala:48:7, :87:{43,49}] reg s1_req_reg_prio_0; // @[SourceD.scala:87:29] reg s1_req_reg_prio_1; // @[SourceD.scala:87:29] reg s1_req_reg_prio_2; // @[SourceD.scala:87:29] reg s1_req_reg_control; // @[SourceD.scala:87:29] reg [2:0] s1_req_reg_opcode; // @[SourceD.scala:87:29] reg [2:0] s1_req_reg_param; // @[SourceD.scala:87:29] reg [2:0] s1_req_reg_size; // @[SourceD.scala:87:29] reg [4:0] s1_req_reg_source; // @[SourceD.scala:87:29] reg [11:0] s1_req_reg_tag; // @[SourceD.scala:87:29] reg [5:0] s1_req_reg_offset; // @[SourceD.scala:87:29] reg [5:0] s1_req_reg_put; // @[SourceD.scala:87:29] reg [9:0] s1_req_reg_set; // @[SourceD.scala:87:29] reg [2:0] s1_req_reg_sink; // @[SourceD.scala:87:29] reg [2:0] s1_req_reg_way; // @[SourceD.scala:87:29] reg s1_req_reg_bad; // @[SourceD.scala:87:29] wire _s1_req_T = ~busy; // @[SourceD.scala:84:21, :87:43, :88:20] wire s1_req_prio_0 = _s1_req_T ? io_req_bits_prio_0_0 : s1_req_reg_prio_0; // @[SourceD.scala:48:7, :87:29, :88:{19,20}] wire s1_req_prio_1 = _s1_req_T ? io_req_bits_prio_1_0 : s1_req_reg_prio_1; // @[SourceD.scala:48:7, :87:29, :88:{19,20}] wire s1_req_prio_2 = _s1_req_T ? io_req_bits_prio_2_0 : s1_req_reg_prio_2; // @[SourceD.scala:48:7, :87:29, :88:{19,20}] wire s1_req_control = _s1_req_T ? io_req_bits_control_0 : s1_req_reg_control; // @[SourceD.scala:48:7, :87:29, :88:{19,20}] wire [2:0] s1_req_opcode = _s1_req_T ? io_req_bits_opcode_0 : s1_req_reg_opcode; // @[SourceD.scala:48:7, :87:29, :88:{19,20}] wire [2:0] s1_req_param = _s1_req_T ? io_req_bits_param_0 : s1_req_reg_param; // @[SourceD.scala:48:7, :87:29, :88:{19,20}] wire [2:0] s1_req_size = _s1_req_T ? io_req_bits_size_0 : s1_req_reg_size; // @[SourceD.scala:48:7, :87:29, :88:{19,20}] wire [4:0] s1_req_source = _s1_req_T ? io_req_bits_source_0 : s1_req_reg_source; // @[SourceD.scala:48:7, :87:29, :88:{19,20}] wire [11:0] s1_req_tag = _s1_req_T ? io_req_bits_tag_0 : s1_req_reg_tag; // @[SourceD.scala:48:7, :87:29, :88:{19,20}] wire [5:0] s1_req_offset = _s1_req_T ? io_req_bits_offset_0 : s1_req_reg_offset; // @[SourceD.scala:48:7, :87:29, :88:{19,20}] wire [5:0] s1_req_put = _s1_req_T ? io_req_bits_put_0 : s1_req_reg_put; // @[SourceD.scala:48:7, :87:29, :88:{19,20}] assign s1_req_set = _s1_req_T ? io_req_bits_set_0 : s1_req_reg_set; // @[SourceD.scala:48:7, :87:29, :88:{19,20}] wire [2:0] s1_req_sink = _s1_req_T ? io_req_bits_sink_0 : s1_req_reg_sink; // @[SourceD.scala:48:7, :87:29, :88:{19,20}] assign s1_req_way = _s1_req_T ? io_req_bits_way_0 : s1_req_reg_way; // @[SourceD.scala:48:7, :87:29, :88:{19,20}] wire s1_req_bad = _s1_req_T ? io_req_bits_bad_0 : s1_req_reg_bad; // @[SourceD.scala:48:7, :87:29, :88:{19,20}] wire [2:0] _s1_mask_sizeOH_T = s1_req_size; // @[Misc.scala:202:34] assign io_bs_radr_bits_set_0 = s1_req_set; // @[SourceD.scala:48:7, :88:19] assign io_bs_radr_bits_way_0 = s1_req_way; // @[SourceD.scala:48:7, :88:19] wire _s1_x_bypass_T_1; // @[SourceD.scala:360:44] wire s1_x_bypass; // @[SourceD.scala:89:25] wire _T_1 = busy \| io_req_valid_0; // @[SourceD.scala:48:7, :84:21, :90:40] wire _s1_latch_bypass_T; // @[SourceD.scala:90:40] assign _s1_latch_bypass_T = _T_1; // @[SourceD.scala:90:40] wire _s1_valid_r_T; // @[SourceD.scala:96:26] assign _s1_valid_r_T = _T_1; // @[SourceD.scala:90:40, :96:26] wire _s1_valid_T; // @[SourceD.scala:141:21] assign _s1_valid_T = _T_1; // @[SourceD.scala:90:40, :141:21] wire _s1_latch_bypass_T_1 = ~_s1_latch_bypass_T; // @[SourceD.scala:90:{33,40}] wire _s1_latch_bypass_T_2 = _s1_latch_bypass_T_1 \| s2_ready; // @[SourceD.scala:77:22, :90:{33,57}] reg s1_latch_bypass; // @[SourceD.scala:90:32] reg s1_bypass_r; // @[SourceD.scala:91:62] wire s1_bypass = s1_latch_bypass ? s1_x_bypass : s1_bypass_r; // @[SourceD.scala:89:25, :90:32, :91:{22,62}] wire [1:0] s1_mask_sizeOH_shiftAmount = _s1_mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _s1_mask_sizeOH_T_1 = 4'h1 << s1_mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _s1_mask_sizeOH_T_2 = _s1_mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire _s1_mask_T = ~s1_bypass; // @[SourceD.scala:91:22, :92:78] assign s1_mask = _s1_mask_T; // @[SourceD.scala:92:{76,78}] assign io_bs_radr_bits_mask_0 = s1_mask; // @[SourceD.scala:48:7, :92:76] wire _s1_need_r_T = s1_mask; // @[SourceD.scala:92:76, :94:27] wire _GEN = s1_req_opcode == 3'h6; // @[SourceD.scala:88:19, :93:33] wire _s1_grant_T; // @[SourceD.scala:93:33] assign _s1_grant_T = _GEN; // @[SourceD.scala:93:33] wire _s1_single_T_2; // @[SourceD.scala:98:89] assign _s1_single_T_2 = _GEN; // @[SourceD.scala:93:33, :98:89] wire _s1_grant_T_1 = s1_req_param == 3'h2; // @[SourceD.scala:88:19, :93:66] wire _s1_grant_T_2 = _s1_grant_T & _s1_grant_T_1; // @[SourceD.scala:93:{33,50,66}] wire _s1_grant_T_3 = &s1_req_opcode; // @[SourceD.scala:88:19, :93:93] wire s1_grant = _s1_grant_T_2 \| _s1_grant_T_3; // @[SourceD.scala:93:{50,76,93}] wire _s1_need_r_T_1 = _s1_need_r_T & s1_req_prio_0; // @[SourceD.scala:88:19, :94:{27,31}] wire _s1_need_r_T_2 = s1_req_opcode != 3'h5; // @[SourceD.scala:88:19, :94:66] wire _s1_need_r_T_3 = _s1_need_r_T_1 & _s1_need_r_T_2; // @[SourceD.scala:94:{31,49,66}] wire _s1_need_r_T_4 = ~s1_grant; // @[SourceD.scala:93:76, :94:78] wire _s1_need_r_T_5 = _s1_need_r_T_3 & _s1_need_r_T_4; // @[SourceD.scala:94:{49,75,78}] wire _s1_need_r_T_6 = \|s1_req_opcode; // @[SourceD.scala:88:19, :95:34] wire _s1_need_r_T_7 = s1_req_size < 3'h3; // @[SourceD.scala:88:19, :95:65] wire _s1_need_r_T_8 = _s1_need_r_T_6 \| _s1_need_r_T_7; // @[SourceD.scala:95:{34,50,65}] wire s1_need_r = _s1_need_r_T_5 & _s1_need_r_T_8; // @[SourceD.scala:94:{75,88}, :95:50] wire _s1_valid_r_T_1 = _s1_valid_r_T & s1_need_r; // @[SourceD.scala:94:88, :96:{26,43}] wire _s1_valid_r_T_2 = ~s1_block_r; // @[SourceD.scala:85:27, :96:59] assign s1_valid_r = _s1_valid_r_T_1 & _s1_valid_r_T_2; // @[SourceD.scala:96:{43,56,59}] assign io_bs_radr_valid_0 = s1_valid_r; // @[SourceD.scala:48:7, :96:56] wire _s1_need_pb_T = s1_req_opcode[2]; // @[SourceD.scala:88:19, :97:54] wire _s1_need_pb_T_1 = ~_s1_need_pb_T; // @[SourceD.scala:97:{40,54}] wire _s1_need_pb_T_2 = s1_req_opcode[0]; // @[SourceD.scala:88:19, :97:72] wire s1_need_pb = s1_req_prio_0 ? _s1_need_pb_T_1 : _s1_need_pb_T_2; // @[SourceD.scala:88:19, :97:{23,40,72}] wire _s1_single_T = s1_req_opcode == 3'h5; // @[SourceD.scala:88:19, :98:53] wire _s1_single_T_1 = _s1_single_T \| s1_grant; // @[SourceD.scala:93:76, :98:{53,62}] wire s1_single = s1_req_prio_0 ? _s1_single_T_1 : _s1_single_T_2; // @[SourceD.scala:88:19, :98:{22,62,89}] wire s1_retires = ~s1_single; // @[SourceD.scala:98:22, :99:20] wire [12:0] _s1_beats1_T = 13'h3F << s1_req_size; // @[package.scala:243:71] wire [5:0] _s1_beats1_T_1 = _s1_beats1_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _s1_beats1_T_2 = ~_s1_beats1_T_1; // @[package.scala:243:{46,76}] wire [2:0] _s1_beats1_T_3 = _s1_beats1_T_2[5:3]; // @[package.scala:243:46] wire [2:0] s1_beats1 = s1_single ? 3'h0 : _s1_beats1_T_3; // @[SourceD.scala:98:22, :101:{22,95}] wire [2:0] _s1_beat_T = s1_req_offset[5:3]; // @[SourceD.scala:88:19, :102:32] assign s1_beat = _s1_beat_T \| s1_counter; // @[SourceD.scala:86:27, :102:{32,56}] assign io_bs_radr_bits_beat_0 = s1_beat; // @[SourceD.scala:48:7, :102:56] wire s1_last = s1_counter == s1_beats1; // @[SourceD.scala:86:27, :101:22, :103:28] wire s1_first = s1_counter == 3'h0; // @[SourceD.scala:86:27, :104:29] wire _queue_io_enq_valid_T = io_bs_radr_ready_0 & io_bs_radr_valid_0; // @[Decoupled.scala:51:35] reg queue_io_enq_valid_REG; // @[SourceD.scala:121:40] reg queue_io_enq_valid_REG_1; // @[SourceD.scala:121:32] wire s2_latch = s1_valid & s2_ready; // @[SourceD.scala:74:22, :77:22, :129:18, :146:27] wire [3:0] _s1_counter_T = {1'h0, s1_counter} + 4'h1; // @[SourceD.scala:86:27, :130:30] wire [2:0] _s1_counter_T_1 = _s1_counter_T[2:0]; // @[SourceD.scala:130:30] assign _io_req_ready_T = ~busy; // @[SourceD.scala:84:21, :87:43, :140:19] assign io_req_ready_0 = _io_req_ready_T; // @[SourceD.scala:48:7, :140:19] wire _s1_valid_T_1 = ~s1_valid_r; // @[SourceD.scala:96:56, :141:42] wire _s1_valid_T_2 = _s1_valid_T_1 \| io_bs_radr_ready_0; // @[SourceD.scala:48:7, :141:{42,54}] assign _s1_valid_T_3 = _s1_valid_T & _s1_valid_T_2; // @[SourceD.scala:141:{21,38,54}] assign s1_valid = _s1_valid_T_3; // @[SourceD.scala:74:22, :141:38] reg s2_full; // @[SourceD.scala:147:24] reg s2_valid_pb; // @[SourceD.scala:148:28] reg [2:0] s2_beat; // @[SourceD.scala:149:26] reg s2_bypass; // @[SourceD.scala:150:28] reg s2_req_prio_0; // @[SourceD.scala:151:25] reg s2_req_prio_1; // @[SourceD.scala:151:25] reg s2_req_prio_2; // @[SourceD.scala:151:25] reg s2_req_control; // @[SourceD.scala:151:25] reg [2:0] s2_req_opcode; // @[SourceD.scala:151:25] reg [2:0] s2_req_param; // @[SourceD.scala:151:25] reg [2:0] s2_req_size; // @[SourceD.scala:151:25] wire [2:0] _s1_2_bypass_sizeOH_T = s2_req_size; // @[Misc.scala:202:34] reg [4:0] s2_req_source; // @[SourceD.scala:151:25] reg [11:0] s2_req_tag; // @[SourceD.scala:151:25] reg [5:0] s2_req_offset; // @[SourceD.scala:151:25] reg [5:0] s2_req_put; // @[SourceD.scala:151:25] assign io_pb_pop_bits_index_0 = s2_req_put; // @[SourceD.scala:48:7, :151:25] assign io_rel_pop_bits_index_0 = s2_req_put; // @[SourceD.scala:48:7, :151:25] reg [9:0] s2_req_set; // @[SourceD.scala:151:25] reg [2:0] s2_req_sink; // @[SourceD.scala:151:25] reg [2:0] s2_req_way; // @[SourceD.scala:151:25] reg s2_req_bad; // @[SourceD.scala:151:25] reg s2_last; // @[SourceD.scala:152:26] assign io_pb_pop_bits_last_0 = s2_last; // @[SourceD.scala:48:7, :152:26] assign io_rel_pop_bits_last_0 = s2_last; // @[SourceD.scala:48:7, :152:26] reg s2_need_r; // @[SourceD.scala:153:28] reg s2_need_pb; // @[SourceD.scala:154:29] reg s2_retires; // @[SourceD.scala:155:29] wire _s2_need_d_T = ~s1_need_pb; // @[SourceD.scala:97:23, :156:29] wire _s2_need_d_T_1 = _s2_need_d_T \| s1_first; // @[SourceD.scala:104:29, :156:{29,41}] reg s2_need_d; // @[SourceD.scala:156:28] wire [63:0] _s2_pdata_raw_data_T; // @[SourceD.scala:160:30] wire [7:0] _s2_pdata_raw_mask_T_1; // @[SourceD.scala:161:30] wire _s2_pdata_raw_corrupt_T; // @[SourceD.scala:162:30] wire [63:0] s2_pdata_raw_data; // @[SourceD.scala:157:26] wire [7:0] s2_pdata_raw_mask; // @[SourceD.scala:157:26] wire s2_pdata_raw_corrupt; // @[SourceD.scala:157:26] reg [63:0] s2_pdata_r_data; // @[package.scala:88:63] reg [7:0] s2_pdata_r_mask; // @[package.scala:88:63] reg s2_pdata_r_corrupt; // @[package.scala:88:63] wire [63:0] s2_pdata_data = s2_valid_pb ? s2_pdata_raw_data : s2_pdata_r_data; // @[package.scala:88:{42,63}] wire [7:0] s2_pdata_mask = s2_valid_pb ? s2_pdata_raw_mask : s2_pdata_r_mask; // @[package.scala:88:{42,63}] wire s2_pdata_corrupt = s2_valid_pb ? s2_pdata_raw_corrupt : s2_pdata_r_corrupt; // @[package.scala:88:{42,63}] assign _s2_pdata_raw_data_T = s2_req_prio_0 ? io_pb_beat_data_0 : io_rel_beat_data_0; // @[SourceD.scala:48:7, :151:25, :160:30] assign s2_pdata_raw_data = _s2_pdata_raw_data_T; // @[SourceD.scala:157:26, :160:30] assign _s2_pdata_raw_mask_T_1 = s2_req_prio_0 ? io_pb_beat_mask_0 : 8'hFF; // @[SourceD.scala:48:7, :151:25, :161:30] assign s2_pdata_raw_mask = _s2_pdata_raw_mask_T_1; // @[SourceD.scala:157:26, :161:30] assign _s2_pdata_raw_corrupt_T = s2_req_prio_0 ? io_pb_beat_corrupt_0 : io_rel_beat_corrupt_0; // @[SourceD.scala:48:7, :151:25, :162:30] assign s2_pdata_raw_corrupt = _s2_pdata_raw_corrupt_T; // @[SourceD.scala:157:26, :162:30] assign _io_pb_pop_valid_T = s2_valid_pb & s2_req_prio_0; // @[SourceD.scala:148:28, :151:25, :164:34] assign io_pb_pop_valid_0 = _io_pb_pop_valid_T; // @[SourceD.scala:48:7, :164:34] wire _io_rel_pop_valid_T = ~s2_req_prio_0; // @[SourceD.scala:151:25, :167:38] assign _io_rel_pop_valid_T_1 = s2_valid_pb & _io_rel_pop_valid_T; // @[SourceD.scala:148:28, :167:{35,38}] assign io_rel_pop_valid_0 = _io_rel_pop_valid_T_1; // @[SourceD.scala:48:7, :167:35] wire pb_ready = s2_req_prio_0 ? io_pb_pop_ready_0 : io_rel_pop_ready_0; // @[SourceD.scala:48:7, :151:25, :175:21] wire s3_latch = s2_valid & s3_ready; // @[SourceD.scala:75:22, :78:22, :177:18, :189:27] wire _s2_valid_T = ~s2_valid_pb; // @[SourceD.scala:148:28, :183:27] wire _s2_valid_T_1 = _s2_valid_T \| pb_ready; // @[SourceD.scala:175:21, :183:{27,40}] assign _s2_valid_T_2 = s2_full & _s2_valid_T_1; // @[SourceD.scala:147:24, :183:{23,40}] assign s2_valid = _s2_valid_T_2; // @[SourceD.scala:75:22, :183:23] wire _s2_ready_T = ~s2_full; // @[SourceD.scala:147:24, :184:15] wire _s2_ready_T_1 = ~s2_valid_pb; // @[SourceD.scala:148:28, :183:27, :184:41] wire _s2_ready_T_2 = _s2_ready_T_1 \| pb_ready; // @[SourceD.scala:175:21, :184:{41,54}] wire _s2_ready_T_3 = s3_ready & _s2_ready_T_2; // @[SourceD.scala:78:22, :184:{37,54}] assign _s2_ready_T_4 = _s2_ready_T \| _s2_ready_T_3; // @[SourceD.scala:184:{15,24,37}] assign s2_ready = _s2_ready_T_4; // @[SourceD.scala:77:22, :184:24] reg s3_full; // @[SourceD.scala:190:24] reg s3_valid_d; // @[SourceD.scala:191:27] assign d_valid = s3_valid_d; // @[SourceD.scala:191:27, :218:15] reg [2:0] s3_beat; // @[SourceD.scala:192:26] wire [2:0] pre_s3_beat = s3_latch ? s2_beat : s3_beat; // @[SourceD.scala:149:26, :189:27, :192:26, :319:24] reg s3_bypass; // @[SourceD.scala:193:28] wire _s3_rdata_T = s3_bypass; // @[SourceD.scala:193:28, :208:78] reg s3_req_prio_0; // @[SourceD.scala:194:25] reg s3_req_prio_1; // @[SourceD.scala:194:25] reg s3_req_prio_2; // @[SourceD.scala:194:25] reg s3_req_control; // @[SourceD.scala:194:25] reg [2:0] s3_req_opcode; // @[SourceD.scala:194:25] reg [2:0] s3_req_param; // @[SourceD.scala:194:25] reg [2:0] s3_req_size; // @[SourceD.scala:194:25] assign d_bits_size = s3_req_size; // @[SourceD.scala:194:25, :218:15] wire [2:0] _s1_3_bypass_sizeOH_T = s3_req_size; // @[Misc.scala:202:34] reg [4:0] s3_req_source; // @[SourceD.scala:194:25] assign d_bits_source = s3_req_source; // @[SourceD.scala:194:25, :218:15] reg [11:0] s3_req_tag; // @[SourceD.scala:194:25] reg [5:0] s3_req_offset; // @[SourceD.scala:194:25] reg [5:0] s3_req_put; // @[SourceD.scala:194:25] reg [9:0] s3_req_set; // @[SourceD.scala:194:25] reg [2:0] s3_req_sink; // @[SourceD.scala:194:25] assign d_bits_sink = s3_req_sink; // @[SourceD.scala:194:25, :218:15] reg [2:0] s3_req_way; // @[SourceD.scala:194:25] reg s3_req_bad; // @[SourceD.scala:194:25] assign d_bits_denied = s3_req_bad; // @[SourceD.scala:194:25, :218:15] wire pre_s3_req_prio_0 = s3_latch ? s2_req_prio_0 : s3_req_prio_0; // @[SourceD.scala:151:25, :189:27, :194:25, :315:24] wire pre_s3_req_prio_1 = s3_latch ? s2_req_prio_1 : s3_req_prio_1; // @[SourceD.scala:151:25, :189:27, :194:25, :315:24] wire pre_s3_req_prio_2 = s3_latch ? s2_req_prio_2 : s3_req_prio_2; // @[SourceD.scala:151:25, :189:27, :194:25, :315:24] wire pre_s3_req_control = s3_latch ? s2_req_control : s3_req_control; // @[SourceD.scala:151:25, :189:27, :194:25, :315:24] wire [2:0] pre_s3_req_opcode = s3_latch ? s2_req_opcode : s3_req_opcode; // @[SourceD.scala:151:25, :189:27, :194:25, :315:24] wire [2:0] pre_s3_req_param = s3_latch ? s2_req_param : s3_req_param; // @[SourceD.scala:151:25, :189:27, :194:25, :315:24] wire [2:0] pre_s3_req_size = s3_latch ? s2_req_size : s3_req_size; // @[SourceD.scala:151:25, :189:27, :194:25, :315:24] wire [4:0] pre_s3_req_source = s3_latch ? s2_req_source : s3_req_source; // @[SourceD.scala:151:25, :189:27, :194:25, :315:24] wire [11:0] pre_s3_req_tag = s3_latch ? s2_req_tag : s3_req_tag; // @[SourceD.scala:151:25, :189:27, :194:25, :315:24] wire [5:0] pre_s3_req_offset = s3_latch ? s2_req_offset : s3_req_offset; // @[SourceD.scala:151:25, :189:27, :194:25, :315:24] wire [5:0] pre_s3_req_put = s3_latch ? s2_req_put : s3_req_put; // @[SourceD.scala:151:25, :189:27, :194:25, :315:24] wire [9:0] pre_s3_req_set = s3_latch ? s2_req_set : s3_req_set; // @[SourceD.scala:151:25, :189:27, :194:25, :315:24] wire [2:0] pre_s3_req_sink = s3_latch ? s2_req_sink : s3_req_sink; // @[SourceD.scala:151:25, :189:27, :194:25, :315:24] wire [2:0] pre_s3_req_way = s3_latch ? s2_req_way : s3_req_way; // @[SourceD.scala:151:25, :189:27, :194:25, :315:24] wire pre_s3_req_bad = s3_latch ? s2_req_bad : s3_req_bad; // @[SourceD.scala:151:25, :189:27, :194:25, :315:24] wire [2:0] s3_adjusted_opcode = s3_req_bad ? 3'h4 : s3_req_opcode; // @[SourceD.scala:194:25, :195:31] reg s3_last; // @[SourceD.scala:196:26] reg [63:0] s3_pdata_data; // @[SourceD.scala:197:27] reg [7:0] s3_pdata_mask; // @[SourceD.scala:197:27] reg s3_pdata_corrupt; // @[SourceD.scala:197:27] reg s3_need_pb; // @[SourceD.scala:198:29] reg s3_retires; // @[SourceD.scala:199:29] reg s3_need_r; // @[SourceD.scala:200:28] wire _s3_acq_T = s3_req_opcode == 3'h6; // @[SourceD.scala:194:25, :202:30] wire _s3_acq_T_1 = &s3_req_opcode; // @[SourceD.scala:194:25, :202:64] wire s3_acq = _s3_acq_T \| _s3_acq_T_1; // @[SourceD.scala:202:{30,47,64}] wire [63:0] _s3_bypass_data_T_11; // @[SourceD.scala:210:75] wire [63:0] s3_bypass_data; // @[SourceD.scala:206:28] wire [63:0] _s3_rdata_T_1 = s3_bypass_data; // @[SourceD.scala:206:28, :207:78] wire [63:0] _s3_rdata_T_2; // @[SourceD.scala:207:78] wire [63:0] s3_rdata = _s3_rdata_T ? _s3_rdata_T_1 : _s3_rdata_T_2; // @[SourceD.scala:207:78, :208:78, :210:75] assign d_bits_data = s3_rdata; // @[SourceD.scala:210:75, :218:15] wire _grant_T = s3_req_param == 3'h2; // @[SourceD.scala:194:25, :214:32] wire [2:0] grant = {2'h2, ~_grant_T}; // @[SourceD.scala:214:{18,32}] wire [2:0] resp_opcode_6 = grant; // @[SourceD.scala:214:18, :215:28] assign io_d_valid_0 = d_valid; // @[SourceD.scala:48:7, :218:15] wire [2:0] _d_bits_opcode_T; // @[SourceD.scala:222:24] assign io_d_bits_opcode_0 = d_bits_opcode; // @[SourceD.scala:48:7, :218:15] wire [1:0] _d_bits_param_T_3; // @[SourceD.scala:223:24] assign io_d_bits_param_0 = d_bits_param; // @[SourceD.scala:48:7, :218:15] assign io_d_bits_size_0 = d_bits_size; // @[SourceD.scala:48:7, :218:15] assign io_d_bits_source_0 = d_bits_source; // @[SourceD.scala:48:7, :218:15] assign io_d_bits_sink_0 = d_bits_sink; // @[SourceD.scala:48:7, :218:15] assign io_d_bits_denied_0 = d_bits_denied; // @[SourceD.scala:48:7, :218:15] assign io_d_bits_data_0 = d_bits_data; // @[SourceD.scala:48:7, :218:15] wire _d_bits_corrupt_T_1; // @[SourceD.scala:229:32] assign io_d_bits_corrupt_0 = d_bits_corrupt; // @[SourceD.scala:48:7, :218:15] wire [7:0][2:0] _GEN_0 = {{3'h4}, {resp_opcode_6}, {3'h2}, {3'h1}, {3'h1}, {3'h1}, {3'h0}, {3'h0}}; // @[SourceD.scala:215:28, :222:24] assign _d_bits_opcode_T = s3_req_prio_0 ? _GEN_0[s3_req_opcode] : 3'h6; // @[SourceD.scala:194:25, :222:24] assign d_bits_opcode = _d_bits_opcode_T; // @[SourceD.scala:218:15, :222:24] wire _d_bits_param_T = s3_req_prio_0 & s3_acq; // @[SourceD.scala:194:25, :202:47, :223:40] wire _d_bits_param_T_1 = \|s3_req_param; // @[SourceD.scala:194:25, :223:68] wire [1:0] _d_bits_param_T_2 = {1'h0, ~_d_bits_param_T_1}; // @[SourceD.scala:223:{54,68}] assign _d_bits_param_T_3 = _d_bits_param_T ? _d_bits_param_T_2 : 2'h0; // @[SourceD.scala:223:{24,40,54}] assign d_bits_param = _d_bits_param_T_3; // @[SourceD.scala:218:15, :223:24] wire _d_bits_corrupt_T = d_bits_opcode[0]; // @[SourceD.scala:218:15, :229:48] assign _d_bits_corrupt_T_1 = s3_req_bad & _d_bits_corrupt_T; // @[SourceD.scala:194:25, :229:{32,48}] assign d_bits_corrupt = _d_bits_corrupt_T_1; // @[SourceD.scala:218:15, :229:32] wire _queue_io_deq_ready_T = s3_valid & s4_ready; // @[SourceD.scala:76:22, :79:22, :231:34] wire _queue_io_deq_ready_T_1 = _queue_io_deq_ready_T & s3_need_r; // @[SourceD.scala:200:28, :231:{34,46}] wire _s3_valid_T = ~s3_valid_d; // @[SourceD.scala:191:27, :241:27] wire _s3_valid_T_1 = _s3_valid_T \| d_ready; // @[SourceD.scala:218:15, :241:{27,39}] assign _s3_valid_T_2 = s3_full & _s3_valid_T_1; // @[SourceD.scala:190:24, :241:{23,39}] assign s3_valid = _s3_valid_T_2; // @[SourceD.scala:76:22, :241:23] wire _s3_ready_T = ~s3_full; // @[SourceD.scala:190:24, :232:11, :242:15] wire _s3_ready_T_1 = ~s3_valid_d; // @[SourceD.scala:191:27, :241:27, :242:41] wire _s3_ready_T_2 = _s3_ready_T_1 \| d_ready; // @[SourceD.scala:218:15, :242:{41,53}] wire _s3_ready_T_3 = s4_ready & _s3_ready_T_2; // @[SourceD.scala:79:22, :242:{37,53}] assign _s3_ready_T_4 = _s3_ready_T \| _s3_ready_T_3; // @[SourceD.scala:242:{15,24,37}] assign s3_ready = _s3_ready_T_4; // @[SourceD.scala:78:22, :242:24] wire _s4_latch_T = s3_valid & s3_retires; // @[SourceD.scala:76:22, :199:29, :247:27] wire s4_latch = _s4_latch_T & s4_ready; // @[SourceD.scala:79:22, :247:{27,41}] reg s4_full; // @[SourceD.scala:248:24] reg [2:0] s4_beat; // @[SourceD.scala:249:26] assign io_bs_wadr_bits_beat_0 = s4_beat; // @[SourceD.scala:48:7, :249:26] wire [2:0] pre_s4_beat = s4_latch ? s3_beat : s4_beat; // @[SourceD.scala:192:26, :247:41, :249:26, :320:24] reg s4_need_r; // @[SourceD.scala:250:28] reg s4_need_bs; // @[SourceD.scala:251:29] reg s4_need_pb; // @[SourceD.scala:252:29] reg s4_req_prio_0; // @[SourceD.scala:253:25] reg s4_req_prio_1; // @[SourceD.scala:253:25] reg s4_req_prio_2; // @[SourceD.scala:253:25] reg s4_req_control; // @[SourceD.scala:253:25] reg [2:0] s4_req_opcode; // @[SourceD.scala:253:25] reg [2:0] s4_req_param; // @[SourceD.scala:253:25] reg [2:0] s4_req_size; // @[SourceD.scala:253:25] wire [2:0] _s1_4_bypass_sizeOH_T = s4_req_size; // @[Misc.scala:202:34] reg [4:0] s4_req_source; // @[SourceD.scala:253:25] reg [11:0] s4_req_tag; // @[SourceD.scala:253:25] reg [5:0] s4_req_offset; // @[SourceD.scala:253:25] reg [5:0] s4_req_put; // @[SourceD.scala:253:25] reg [9:0] s4_req_set; // @[SourceD.scala:253:25] assign io_bs_wadr_bits_set_0 = s4_req_set; // @[SourceD.scala:48:7, :253:25] reg [2:0] s4_req_sink; // @[SourceD.scala:253:25] reg [2:0] s4_req_way; // @[SourceD.scala:253:25] assign io_bs_wadr_bits_way_0 = s4_req_way; // @[SourceD.scala:48:7, :253:25] reg s4_req_bad; // @[SourceD.scala:253:25] wire pre_s4_req_prio_0 = s4_latch ? s3_req_prio_0 : s4_req_prio_0; // @[SourceD.scala:194:25, :247:41, :253:25, :316:24] wire pre_s4_req_prio_1 = s4_latch ? s3_req_prio_1 : s4_req_prio_1; // @[SourceD.scala:194:25, :247:41, :253:25, :316:24] wire pre_s4_req_prio_2 = s4_latch ? s3_req_prio_2 : s4_req_prio_2; // @[SourceD.scala:194:25, :247:41, :253:25, :316:24] wire pre_s4_req_control = s4_latch ? s3_req_control : s4_req_control; // @[SourceD.scala:194:25, :247:41, :253:25, :316:24] wire [2:0] pre_s4_req_opcode = s4_latch ? s3_req_opcode : s4_req_opcode; // @[SourceD.scala:194:25, :247:41, :253:25, :316:24] wire [2:0] pre_s4_req_param = s4_latch ? s3_req_param : s4_req_param; // @[SourceD.scala:194:25, :247:41, :253:25, :316:24] wire [2:0] pre_s4_req_size = s4_latch ? s3_req_size : s4_req_size; // @[SourceD.scala:194:25, :247:41, :253:25, :316:24] wire [4:0] pre_s4_req_source = s4_latch ? s3_req_source : s4_req_source; // @[SourceD.scala:194:25, :247:41, :253:25, :316:24] wire [11:0] pre_s4_req_tag = s4_latch ? s3_req_tag : s4_req_tag; // @[SourceD.scala:194:25, :247:41, :253:25, :316:24] wire [5:0] pre_s4_req_offset = s4_latch ? s3_req_offset : s4_req_offset; // @[SourceD.scala:194:25, :247:41, :253:25, :316:24] wire [5:0] pre_s4_req_put = s4_latch ? s3_req_put : s4_req_put; // @[SourceD.scala:194:25, :247:41, :253:25, :316:24] wire [9:0] pre_s4_req_set = s4_latch ? s3_req_set : s4_req_set; // @[SourceD.scala:194:25, :247:41, :253:25, :316:24] wire [2:0] pre_s4_req_sink = s4_latch ? s3_req_sink : s4_req_sink; // @[SourceD.scala:194:25, :247:41, :253:25, :316:24] wire [2:0] pre_s4_req_way = s4_latch ? s3_req_way : s4_req_way; // @[SourceD.scala:194:25, :247:41, :253:25, :316:24] wire pre_s4_req_bad = s4_latch ? s3_req_bad : s4_req_bad; // @[SourceD.scala:194:25, :247:41, :253:25, :316:24] reg [2:0] s4_adjusted_opcode; // @[SourceD.scala:254:37] reg [63:0] s4_pdata_data; // @[SourceD.scala:255:27] reg [7:0] s4_pdata_mask; // @[SourceD.scala:255:27] reg s4_pdata_corrupt; // @[SourceD.scala:255:27] reg [63:0] s4_rdata; // @[SourceD.scala:256:27] assign _io_bs_wadr_valid_T = s4_full & s4_need_bs; // @[SourceD.scala:248:24, :251:29, :270:31] assign io_bs_wadr_valid_0 = _io_bs_wadr_valid_T; // @[SourceD.scala:48:7, :270:31] wire _io_bs_wadr_bits_mask_T = s4_pdata_mask[0]; // @[SourceD.scala:255:27, :275:45] wire _io_bs_wadr_bits_mask_T_1 = s4_pdata_mask[1]; // @[SourceD.scala:255:27, :275:45] wire _io_bs_wadr_bits_mask_T_2 = s4_pdata_mask[2]; // @[SourceD.scala:255:27, :275:45] wire _io_bs_wadr_bits_mask_T_3 = s4_pdata_mask[3]; // @[SourceD.scala:255:27, :275:45] wire _io_bs_wadr_bits_mask_T_4 = s4_pdata_mask[4]; // @[SourceD.scala:255:27, :275:45] wire _io_bs_wadr_bits_mask_T_5 = s4_pdata_mask[5]; // @[SourceD.scala:255:27, :275:45] wire _io_bs_wadr_bits_mask_T_6 = s4_pdata_mask[6]; // @[SourceD.scala:255:27, :275:45] wire _io_bs_wadr_bits_mask_T_7 = s4_pdata_mask[7]; // @[SourceD.scala:255:27, :275:45] wire _io_bs_wadr_bits_mask_T_8 = _io_bs_wadr_bits_mask_T \| _io_bs_wadr_bits_mask_T_1; // @[SourceD.scala:275:{45,87}] wire _io_bs_wadr_bits_mask_T_9 = _io_bs_wadr_bits_mask_T_8 \| _io_bs_wadr_bits_mask_T_2; // @[SourceD.scala:275:{45,87}] wire _io_bs_wadr_bits_mask_T_10 = _io_bs_wadr_bits_mask_T_9 \| _io_bs_wadr_bits_mask_T_3; // @[SourceD.scala:275:{45,87}] wire _io_bs_wadr_bits_mask_T_11 = _io_bs_wadr_bits_mask_T_10 \| _io_bs_wadr_bits_mask_T_4; // @[SourceD.scala:275:{45,87}] wire _io_bs_wadr_bits_mask_T_12 = _io_bs_wadr_bits_mask_T_11 \| _io_bs_wadr_bits_mask_T_5; // @[SourceD.scala:275:{45,87}] wire _io_bs_wadr_bits_mask_T_13 = _io_bs_wadr_bits_mask_T_12 \| _io_bs_wadr_bits_mask_T_6; // @[SourceD.scala:275:{45,87}] assign _io_bs_wadr_bits_mask_T_14 = _io_bs_wadr_bits_mask_T_13 \| _io_bs_wadr_bits_mask_T_7; // @[SourceD.scala:275:{45,87}] assign io_bs_wadr_bits_mask_0 = _io_bs_wadr_bits_mask_T_14; // @[SourceD.scala:48:7, :275:87]

Generate the Verilog code corresponding to the following Chisel files. File loop.scala: package boom.v3.ifu import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.{Field, Parameters} import freechips.rocketchip.diplomacy._ import freechips.rocketchip.tilelink._ import boom.v3.common._ import boom.v3.util.{BoomCoreStringPrefix} import scala.math.min case class BoomLoopPredictorParams( nWays: Int = 4, threshold: Int = 7 ) class LoopBranchPredictorBank(implicit p: Parameters) extends BranchPredictorBank()(p) { val tagSz = 10 override val nSets = 16 class LoopMeta extends Bundle { val s_cnt = UInt(10.W) } class LoopEntry extends Bundle { val tag = UInt(tagSz.W) val conf = UInt(3.W) val age = UInt(3.W) val p_cnt = UInt(10.W) val s_cnt = UInt(10.W) } class LoopBranchPredictorColumn extends Module { val io = IO(new Bundle { val f2_req_valid = Input(Bool()) val f2_req_idx = Input(UInt()) val f3_req_fire = Input(Bool()) val f3_pred_in = Input(Bool()) val f3_pred = Output(Bool()) val f3_meta = Output(new LoopMeta) val update_mispredict = Input(Bool()) val update_repair = Input(Bool()) val update_idx = Input(UInt()) val update_resolve_dir = Input(Bool()) val update_meta = Input(new LoopMeta) }) val doing_reset = RegInit(true.B) val reset_idx = RegInit(0.U(log2Ceil(nSets).W)) reset_idx := reset_idx + doing_reset when (reset_idx === (nSets-1).U) { doing_reset := false.B } val entries = Reg(Vec(nSets, new LoopEntry)) val f2_entry = WireInit(entries(io.f2_req_idx)) when (io.update_repair && io.update_idx === io.f2_req_idx) { f2_entry.s_cnt := io.update_meta.s_cnt } .elsewhen (io.update_mispredict && io.update_idx === io.f2_req_idx) { f2_entry.s_cnt := 0.U } val f3_entry = RegNext(f2_entry) val f3_scnt = Mux(io.update_repair && io.update_idx === RegNext(io.f2_req_idx), io.update_meta.s_cnt, f3_entry.s_cnt) val f3_tag = RegNext(io.f2_req_idx(tagSz+log2Ceil(nSets)-1,log2Ceil(nSets))) io.f3_pred := io.f3_pred_in io.f3_meta.s_cnt := f3_scnt when (f3_entry.tag === f3_tag) { when (f3_scnt === f3_entry.p_cnt && f3_entry.conf === 7.U) { io.f3_pred := !io.f3_pred_in } } val f4_fire = RegNext(io.f3_req_fire) val f4_entry = RegNext(f3_entry) val f4_tag = RegNext(f3_tag) val f4_scnt = RegNext(f3_scnt) val f4_idx = RegNext(RegNext(io.f2_req_idx)) when (f4_fire) { when (f4_entry.tag === f4_tag) { when (f4_scnt === f4_entry.p_cnt && f4_entry.conf === 7.U) { entries(f4_idx).age := 7.U entries(f4_idx).s_cnt := 0.U } .otherwise { entries(f4_idx).s_cnt := f4_scnt + 1.U entries(f4_idx).age := Mux(f4_entry.age === 7.U, 7.U, f4_entry.age + 1.U) } } } val entry = entries(io.update_idx) val tag = io.update_idx(tagSz+log2Ceil(nSets)-1,log2Ceil(nSets)) val tag_match = entry.tag === tag val ctr_match = entry.p_cnt === io.update_meta.s_cnt val wentry = WireInit(entry) when (io.update_mispredict && !doing_reset) { // Learned, tag match -> decrement confidence when (entry.conf === 7.U && tag_match) { wentry.s_cnt := 0.U wentry.conf := 0.U // Learned, no tag match -> do nothing? Don't evict super-confident entries? } .elsewhen (entry.conf === 7.U && !tag_match) { // Confident, tag match, ctr_match -> increment confidence, reset counter } .elsewhen (entry.conf =/= 0.U && tag_match && ctr_match) { wentry.conf := entry.conf + 1.U wentry.s_cnt := 0.U // Confident, tag match, no ctr match -> zero confidence, reset counter, set previous counter } .elsewhen (entry.conf =/= 0.U && tag_match && !ctr_match) { wentry.conf := 0.U wentry.s_cnt := 0.U wentry.p_cnt := io.update_meta.s_cnt // Confident, no tag match, age is 0 -> replace this entry with our own, set our age high to avoid ping-pong } .elsewhen (entry.conf =/= 0.U && !tag_match && entry.age === 0.U) { wentry.tag := tag wentry.conf := 1.U wentry.s_cnt := 0.U wentry.p_cnt := io.update_meta.s_cnt // Confident, no tag match, age > 0 -> decrement age } .elsewhen (entry.conf =/= 0.U && !tag_match && entry.age =/= 0.U) { wentry.age := entry.age - 1.U // Unconfident, tag match, ctr match -> increment confidence } .elsewhen (entry.conf === 0.U && tag_match && ctr_match) { wentry.conf := 1.U wentry.age := 7.U wentry.s_cnt := 0.U // Unconfident, tag match, no ctr match -> set previous counter } .elsewhen (entry.conf === 0.U && tag_match && !ctr_match) { wentry.p_cnt := io.update_meta.s_cnt wentry.age := 7.U wentry.s_cnt := 0.U // Unconfident, no tag match -> set previous counter and tag } .elsewhen (entry.conf === 0.U && !tag_match) { wentry.tag := tag wentry.conf := 1.U wentry.age := 7.U wentry.s_cnt := 0.U wentry.p_cnt := io.update_meta.s_cnt } entries(io.update_idx) := wentry } .elsewhen (io.update_repair && !doing_reset) { when (tag_match && !(f4_fire && io.update_idx === f4_idx)) { wentry.s_cnt := io.update_meta.s_cnt entries(io.update_idx) := wentry } } when (doing_reset) { entries(reset_idx) := (0.U).asTypeOf(new LoopEntry) } } val columns = Seq.fill(bankWidth) { Module(new LoopBranchPredictorColumn) } val mems = Nil // TODO fix val f3_meta = Wire(Vec(bankWidth, new LoopMeta)) override val metaSz = f3_meta.asUInt.getWidth val update_meta = s1_update.bits.meta.asTypeOf(Vec(bankWidth, new LoopMeta)) for (w <- 0 until bankWidth) { columns(w).io.f2_req_valid := s2_valid columns(w).io.f2_req_idx := s2_idx columns(w).io.f3_req_fire := (s3_valid && s3_mask(w) && io.f3_fire && RegNext(io.resp_in(0).f2(w).predicted_pc.valid && io.resp_in(0).f2(w).is_br)) columns(w).io.f3_pred_in := io.resp_in(0).f3(w).taken io.resp.f3(w).taken := columns(w).io.f3_pred columns(w).io.update_mispredict := (s1_update.valid && s1_update.bits.br_mask(w) && s1_update.bits.is_mispredict_update && s1_update.bits.cfi_mispredicted) columns(w).io.update_repair := (s1_update.valid && s1_update.bits.br_mask(w) && s1_update.bits.is_repair_update) columns(w).io.update_idx := s1_update_idx columns(w).io.update_resolve_dir := s1_update.bits.cfi_taken columns(w).io.update_meta := update_meta(w) f3_meta(w) := columns(w).io.f3_meta } io.f3_meta := f3_meta.asUInt } File predictor.scala: package boom.v3.ifu import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.{Field, Parameters} import freechips.rocketchip.diplomacy._ import freechips.rocketchip.tilelink._ import boom.v3.common._ import boom.v3.util.{BoomCoreStringPrefix} // A branch prediction for a single instruction class BranchPrediction(implicit p: Parameters) extends BoomBundle()(p) { // If this is a branch, do we take it? val taken = Bool() // Is this a branch? val is_br = Bool() // Is this a JAL? val is_jal = Bool() // What is the target of his branch/jump? Do we know the target? val predicted_pc = Valid(UInt(vaddrBitsExtended.W)) } // A branch prediction for a entire fetch-width worth of instructions // This is typically merged from individual predictions from the banked // predictor class BranchPredictionBundle(implicit p: Parameters) extends BoomBundle()(p) with HasBoomFrontendParameters { val pc = UInt(vaddrBitsExtended.W) val preds = Vec(fetchWidth, new BranchPrediction) val meta = Output(Vec(nBanks, UInt(bpdMaxMetaLength.W))) val lhist = Output(Vec(nBanks, UInt(localHistoryLength.W))) } // A branch update for a fetch-width worth of instructions class BranchPredictionUpdate(implicit p: Parameters) extends BoomBundle()(p) with HasBoomFrontendParameters { // Indicates that this update is due to a speculated misprediction // Local predictors typically update themselves with speculative info // Global predictors only care about non-speculative updates val is_mispredict_update = Bool() val is_repair_update = Bool() val btb_mispredicts = UInt(fetchWidth.W) def is_btb_mispredict_update = btb_mispredicts =/= 0.U def is_commit_update = !(is_mispredict_update || is_repair_update || is_btb_mispredict_update) val pc = UInt(vaddrBitsExtended.W) // Mask of instructions which are branches. // If these are not cfi_idx, then they were predicted not taken val br_mask = UInt(fetchWidth.W) // Which CFI was taken/mispredicted (if any) val cfi_idx = Valid(UInt(log2Ceil(fetchWidth).W)) // Was the cfi taken? val cfi_taken = Bool() // Was the cfi mispredicted from the original prediction? val cfi_mispredicted = Bool() // Was the cfi a br? val cfi_is_br = Bool() // Was the cfi a jal/jalr? val cfi_is_jal = Bool() // Was the cfi a jalr val cfi_is_jalr = Bool() //val cfi_is_ret = Bool() val ghist = new GlobalHistory val lhist = Vec(nBanks, UInt(localHistoryLength.W)) // What did this CFI jump to? val target = UInt(vaddrBitsExtended.W) val meta = Vec(nBanks, UInt(bpdMaxMetaLength.W)) } // A branch update to a single bank class BranchPredictionBankUpdate(implicit p: Parameters) extends BoomBundle()(p) with HasBoomFrontendParameters { val is_mispredict_update = Bool() val is_repair_update = Bool() val btb_mispredicts = UInt(bankWidth.W) def is_btb_mispredict_update = btb_mispredicts =/= 0.U def is_commit_update = !(is_mispredict_update || is_repair_update || is_btb_mispredict_update) val pc = UInt(vaddrBitsExtended.W) val br_mask = UInt(bankWidth.W) val cfi_idx = Valid(UInt(log2Ceil(bankWidth).W)) val cfi_taken = Bool() val cfi_mispredicted = Bool() val cfi_is_br = Bool() val cfi_is_jal = Bool() val cfi_is_jalr = Bool() val ghist = UInt(globalHistoryLength.W) val lhist = UInt(localHistoryLength.W) val target = UInt(vaddrBitsExtended.W) val meta = UInt(bpdMaxMetaLength.W) } class BranchPredictionRequest(implicit p: Parameters) extends BoomBundle()(p) { val pc = UInt(vaddrBitsExtended.W) val ghist = new GlobalHistory } class BranchPredictionBankResponse(implicit p: Parameters) extends BoomBundle()(p) with HasBoomFrontendParameters { val f1 = Vec(bankWidth, new BranchPrediction) val f2 = Vec(bankWidth, new BranchPrediction) val f3 = Vec(bankWidth, new BranchPrediction) } abstract class BranchPredictorBank(implicit p: Parameters) extends BoomModule()(p) with HasBoomFrontendParameters { val metaSz = 0 def nInputs = 1 val mems: Seq[Tuple3[String, Int, Int]] val io = IO(new Bundle { val f0_valid = Input(Bool()) val f0_pc = Input(UInt(vaddrBitsExtended.W)) val f0_mask = Input(UInt(bankWidth.W)) // Local history not available until end of f1 val f1_ghist = Input(UInt(globalHistoryLength.W)) val f1_lhist = Input(UInt(localHistoryLength.W)) val resp_in = Input(Vec(nInputs, new BranchPredictionBankResponse)) val resp = Output(new BranchPredictionBankResponse) // Store the meta as a UInt, use width inference to figure out the shape val f3_meta = Output(UInt(bpdMaxMetaLength.W)) val f3_fire = Input(Bool()) val update = Input(Valid(new BranchPredictionBankUpdate)) }) io.resp := io.resp_in(0) io.f3_meta := 0.U val s0_idx = fetchIdx(io.f0_pc) val s1_idx = RegNext(s0_idx) val s2_idx = RegNext(s1_idx) val s3_idx = RegNext(s2_idx) val s0_valid = io.f0_valid val s1_valid = RegNext(s0_valid) val s2_valid = RegNext(s1_valid) val s3_valid = RegNext(s2_valid) val s0_mask = io.f0_mask val s1_mask = RegNext(s0_mask) val s2_mask = RegNext(s1_mask) val s3_mask = RegNext(s2_mask) val s0_pc = io.f0_pc val s1_pc = RegNext(s0_pc) val s0_update = io.update val s0_update_idx = fetchIdx(io.update.bits.pc) val s0_update_valid = io.update.valid val s1_update = RegNext(s0_update) val s1_update_idx = RegNext(s0_update_idx) val s1_update_valid = RegNext(s0_update_valid) } class BranchPredictor(implicit p: Parameters) extends BoomModule()(p) with HasBoomFrontendParameters { val io = IO(new Bundle { // Requests and responses val f0_req = Input(Valid(new BranchPredictionRequest)) val resp = Output(new Bundle { val f1 = new BranchPredictionBundle val f2 = new BranchPredictionBundle val f3 = new BranchPredictionBundle }) val f3_fire = Input(Bool()) // Update val update = Input(Valid(new BranchPredictionUpdate)) }) var total_memsize = 0 val bpdStr = new StringBuilder bpdStr.append(BoomCoreStringPrefix("==Branch Predictor Memory Sizes==\n")) val banked_predictors = (0 until nBanks) map ( b => { val m = Module(if (useBPD) new ComposedBranchPredictorBank else new NullBranchPredictorBank) for ((n, d, w) <- m.mems) { bpdStr.append(BoomCoreStringPrefix(f"bank$b $n: $d x $w = ${d * w / 8}")) total_memsize = total_memsize + d * w / 8 } m }) bpdStr.append(BoomCoreStringPrefix(f"Total bpd size: ${total_memsize / 1024} KB\n")) override def toString: String = bpdStr.toString val banked_lhist_providers = Seq.fill(nBanks) { Module(if (localHistoryNSets > 0) new LocalBranchPredictorBank else new NullLocalBranchPredictorBank) } if (nBanks == 1) { banked_lhist_providers(0).io.f0_valid := io.f0_req.valid banked_lhist_providers(0).io.f0_pc := bankAlign(io.f0_req.bits.pc) banked_predictors(0).io.f0_valid := io.f0_req.valid banked_predictors(0).io.f0_pc := bankAlign(io.f0_req.bits.pc) banked_predictors(0).io.f0_mask := fetchMask(io.f0_req.bits.pc) banked_predictors(0).io.f1_ghist := RegNext(io.f0_req.bits.ghist.histories(0)) banked_predictors(0).io.f1_lhist := banked_lhist_providers(0).io.f1_lhist banked_predictors(0).io.resp_in(0) := (0.U).asTypeOf(new BranchPredictionBankResponse) } else { require(nBanks == 2) banked_predictors(0).io.resp_in(0) := (0.U).asTypeOf(new BranchPredictionBankResponse) banked_predictors(1).io.resp_in(0) := (0.U).asTypeOf(new BranchPredictionBankResponse) banked_predictors(0).io.f1_lhist := banked_lhist_providers(0).io.f1_lhist banked_predictors(1).io.f1_lhist := banked_lhist_providers(1).io.f1_lhist when (bank(io.f0_req.bits.pc) === 0.U) { banked_lhist_providers(0).io.f0_valid := io.f0_req.valid banked_lhist_providers(0).io.f0_pc := bankAlign(io.f0_req.bits.pc) banked_lhist_providers(1).io.f0_valid := io.f0_req.valid banked_lhist_providers(1).io.f0_pc := nextBank(io.f0_req.bits.pc) banked_predictors(0).io.f0_valid := io.f0_req.valid banked_predictors(0).io.f0_pc := bankAlign(io.f0_req.bits.pc) banked_predictors(0).io.f0_mask := fetchMask(io.f0_req.bits.pc) banked_predictors(1).io.f0_valid := io.f0_req.valid banked_predictors(1).io.f0_pc := nextBank(io.f0_req.bits.pc) banked_predictors(1).io.f0_mask := ~(0.U(bankWidth.W)) } .otherwise { banked_lhist_providers(0).io.f0_valid := io.f0_req.valid && !mayNotBeDualBanked(io.f0_req.bits.pc) banked_lhist_providers(0).io.f0_pc := nextBank(io.f0_req.bits.pc) banked_lhist_providers(1).io.f0_valid := io.f0_req.valid banked_lhist_providers(1).io.f0_pc := bankAlign(io.f0_req.bits.pc) banked_predictors(0).io.f0_valid := io.f0_req.valid && !mayNotBeDualBanked(io.f0_req.bits.pc) banked_predictors(0).io.f0_pc := nextBank(io.f0_req.bits.pc) banked_predictors(0).io.f0_mask := ~(0.U(bankWidth.W)) banked_predictors(1).io.f0_valid := io.f0_req.valid banked_predictors(1).io.f0_pc := bankAlign(io.f0_req.bits.pc) banked_predictors(1).io.f0_mask := fetchMask(io.f0_req.bits.pc) } when (RegNext(bank(io.f0_req.bits.pc) === 0.U)) { banked_predictors(0).io.f1_ghist := RegNext(io.f0_req.bits.ghist.histories(0)) banked_predictors(1).io.f1_ghist := RegNext(io.f0_req.bits.ghist.histories(1)) } .otherwise { banked_predictors(0).io.f1_ghist := RegNext(io.f0_req.bits.ghist.histories(1)) banked_predictors(1).io.f1_ghist := RegNext(io.f0_req.bits.ghist.histories(0)) } } for (i <- 0 until nBanks) { banked_lhist_providers(i).io.f3_taken_br := banked_predictors(i).io.resp.f3.map ( p => p.is_br && p.predicted_pc.valid && p.taken ).reduce(_||_) } if (nBanks == 1) { io.resp.f1.preds := banked_predictors(0).io.resp.f1 io.resp.f2.preds := banked_predictors(0).io.resp.f2 io.resp.f3.preds := banked_predictors(0).io.resp.f3 io.resp.f3.meta(0) := banked_predictors(0).io.f3_meta io.resp.f3.lhist(0) := banked_lhist_providers(0).io.f3_lhist banked_predictors(0).io.f3_fire := io.f3_fire banked_lhist_providers(0).io.f3_fire := io.f3_fire } else { require(nBanks == 2) val b0_fire = io.f3_fire && RegNext(RegNext(RegNext(banked_predictors(0).io.f0_valid))) val b1_fire = io.f3_fire && RegNext(RegNext(RegNext(banked_predictors(1).io.f0_valid))) banked_predictors(0).io.f3_fire := b0_fire banked_predictors(1).io.f3_fire := b1_fire banked_lhist_providers(0).io.f3_fire := b0_fire banked_lhist_providers(1).io.f3_fire := b1_fire // The branch prediction metadata is stored un-shuffled io.resp.f3.meta(0) := banked_predictors(0).io.f3_meta io.resp.f3.meta(1) := banked_predictors(1).io.f3_meta io.resp.f3.lhist(0) := banked_lhist_providers(0).io.f3_lhist io.resp.f3.lhist(1) := banked_lhist_providers(1).io.f3_lhist when (bank(io.resp.f1.pc) === 0.U) { for (i <- 0 until bankWidth) { io.resp.f1.preds(i) := banked_predictors(0).io.resp.f1(i) io.resp.f1.preds(i+bankWidth) := banked_predictors(1).io.resp.f1(i) } } .otherwise { for (i <- 0 until bankWidth) { io.resp.f1.preds(i) := banked_predictors(1).io.resp.f1(i) io.resp.f1.preds(i+bankWidth) := banked_predictors(0).io.resp.f1(i) } } when (bank(io.resp.f2.pc) === 0.U) { for (i <- 0 until bankWidth) { io.resp.f2.preds(i) := banked_predictors(0).io.resp.f2(i) io.resp.f2.preds(i+bankWidth) := banked_predictors(1).io.resp.f2(i) } } .otherwise { for (i <- 0 until bankWidth) { io.resp.f2.preds(i) := banked_predictors(1).io.resp.f2(i) io.resp.f2.preds(i+bankWidth) := banked_predictors(0).io.resp.f2(i) } } when (bank(io.resp.f3.pc) === 0.U) { for (i <- 0 until bankWidth) { io.resp.f3.preds(i) := banked_predictors(0).io.resp.f3(i) io.resp.f3.preds(i+bankWidth) := banked_predictors(1).io.resp.f3(i) } } .otherwise { for (i <- 0 until bankWidth) { io.resp.f3.preds(i) := banked_predictors(1).io.resp.f3(i) io.resp.f3.preds(i+bankWidth) := banked_predictors(0).io.resp.f3(i) } } } io.resp.f1.pc := RegNext(io.f0_req.bits.pc) io.resp.f2.pc := RegNext(io.resp.f1.pc) io.resp.f3.pc := RegNext(io.resp.f2.pc) // We don't care about meta from the f1 and f2 resps // Use the meta from the latest resp io.resp.f1.meta := DontCare io.resp.f2.meta := DontCare io.resp.f1.lhist := DontCare io.resp.f2.lhist := DontCare for (i <- 0 until nBanks) { banked_predictors(i).io.update.bits.is_mispredict_update := io.update.bits.is_mispredict_update banked_predictors(i).io.update.bits.is_repair_update := io.update.bits.is_repair_update banked_predictors(i).io.update.bits.meta := io.update.bits.meta(i) banked_predictors(i).io.update.bits.lhist := io.update.bits.lhist(i) banked_predictors(i).io.update.bits.cfi_idx.bits := io.update.bits.cfi_idx.bits banked_predictors(i).io.update.bits.cfi_taken := io.update.bits.cfi_taken banked_predictors(i).io.update.bits.cfi_mispredicted := io.update.bits.cfi_mispredicted banked_predictors(i).io.update.bits.cfi_is_br := io.update.bits.cfi_is_br banked_predictors(i).io.update.bits.cfi_is_jal := io.update.bits.cfi_is_jal banked_predictors(i).io.update.bits.cfi_is_jalr := io.update.bits.cfi_is_jalr banked_predictors(i).io.update.bits.target := io.update.bits.target banked_lhist_providers(i).io.update.mispredict := io.update.bits.is_mispredict_update banked_lhist_providers(i).io.update.repair := io.update.bits.is_repair_update banked_lhist_providers(i).io.update.lhist := io.update.bits.lhist(i) } if (nBanks == 1) { banked_predictors(0).io.update.valid := io.update.valid banked_predictors(0).io.update.bits.pc := bankAlign(io.update.bits.pc) banked_predictors(0).io.update.bits.br_mask := io.update.bits.br_mask banked_predictors(0).io.update.bits.btb_mispredicts := io.update.bits.btb_mispredicts banked_predictors(0).io.update.bits.cfi_idx.valid := io.update.bits.cfi_idx.valid banked_predictors(0).io.update.bits.ghist := io.update.bits.ghist.histories(0) banked_lhist_providers(0).io.update.valid := io.update.valid && io.update.bits.br_mask =/= 0.U banked_lhist_providers(0).io.update.pc := bankAlign(io.update.bits.pc) } else { require(nBanks == 2) // Split the single update bundle for the fetchpacket into two updates // 1 for each bank. when (bank(io.update.bits.pc) === 0.U) { val b1_update_valid = io.update.valid && (!io.update.bits.cfi_idx.valid || io.update.bits.cfi_idx.bits >= bankWidth.U) banked_lhist_providers(0).io.update.valid := io.update.valid && io.update.bits.br_mask(bankWidth-1,0) =/= 0.U banked_lhist_providers(1).io.update.valid := b1_update_valid && io.update.bits.br_mask(fetchWidth-1,bankWidth) =/= 0.U banked_lhist_providers(0).io.update.pc := bankAlign(io.update.bits.pc) banked_lhist_providers(1).io.update.pc := nextBank(io.update.bits.pc) banked_predictors(0).io.update.valid := io.update.valid banked_predictors(1).io.update.valid := b1_update_valid banked_predictors(0).io.update.bits.pc := bankAlign(io.update.bits.pc) banked_predictors(1).io.update.bits.pc := nextBank(io.update.bits.pc) banked_predictors(0).io.update.bits.br_mask := io.update.bits.br_mask banked_predictors(1).io.update.bits.br_mask := io.update.bits.br_mask >> bankWidth banked_predictors(0).io.update.bits.btb_mispredicts := io.update.bits.btb_mispredicts banked_predictors(1).io.update.bits.btb_mispredicts := io.update.bits.btb_mispredicts >> bankWidth banked_predictors(0).io.update.bits.cfi_idx.valid := io.update.bits.cfi_idx.valid && io.update.bits.cfi_idx.bits < bankWidth.U banked_predictors(1).io.update.bits.cfi_idx.valid := io.update.bits.cfi_idx.valid && io.update.bits.cfi_idx.bits >= bankWidth.U banked_predictors(0).io.update.bits.ghist := io.update.bits.ghist.histories(0) banked_predictors(1).io.update.bits.ghist := io.update.bits.ghist.histories(1) } .otherwise { val b0_update_valid = io.update.valid && !mayNotBeDualBanked(io.update.bits.pc) && (!io.update.bits.cfi_idx.valid || io.update.bits.cfi_idx.bits >= bankWidth.U) banked_lhist_providers(1).io.update.valid := io.update.valid && io.update.bits.br_mask(bankWidth-1,0) =/= 0.U banked_lhist_providers(0).io.update.valid := b0_update_valid && io.update.bits.br_mask(fetchWidth-1,bankWidth) =/= 0.U banked_lhist_providers(1).io.update.pc := bankAlign(io.update.bits.pc) banked_lhist_providers(0).io.update.pc := nextBank(io.update.bits.pc) banked_predictors(1).io.update.valid := io.update.valid banked_predictors(0).io.update.valid := b0_update_valid banked_predictors(1).io.update.bits.pc := bankAlign(io.update.bits.pc) banked_predictors(0).io.update.bits.pc := nextBank(io.update.bits.pc) banked_predictors(1).io.update.bits.br_mask := io.update.bits.br_mask banked_predictors(0).io.update.bits.br_mask := io.update.bits.br_mask >> bankWidth banked_predictors(1).io.update.bits.btb_mispredicts := io.update.bits.btb_mispredicts banked_predictors(0).io.update.bits.btb_mispredicts := io.update.bits.btb_mispredicts >> bankWidth banked_predictors(1).io.update.bits.cfi_idx.valid := io.update.bits.cfi_idx.valid && io.update.bits.cfi_idx.bits < bankWidth.U banked_predictors(0).io.update.bits.cfi_idx.valid := io.update.bits.cfi_idx.valid && io.update.bits.cfi_idx.bits >= bankWidth.U banked_predictors(1).io.update.bits.ghist := io.update.bits.ghist.histories(0) banked_predictors(0).io.update.bits.ghist := io.update.bits.ghist.histories(1) } } when (io.update.valid) { when (io.update.bits.cfi_is_br && io.update.bits.cfi_idx.valid) { assert(io.update.bits.br_mask(io.update.bits.cfi_idx.bits)) } } } class NullBranchPredictorBank(implicit p: Parameters) extends BranchPredictorBank()(p) { val mems = Nil }

module LoopBranchPredictorBank( // @[loop.scala:20:7] input clock, // @[loop.scala:20:7] input reset, // @[loop.scala:20:7] input io_f0_valid, // @[predictor.scala:140:14] input [39:0] io_f0_pc, // @[predictor.scala:140:14] input [3:0] io_f0_mask, // @[predictor.scala:140:14] input [63:0] io_f1_ghist, // @[predictor.scala:140:14] input io_resp_in_0_f1_0_taken, // @[predictor.scala:140:14] input io_resp_in_0_f1_0_is_br, // @[predictor.scala:140:14] input io_resp_in_0_f1_0_is_jal, // @[predictor.scala:140:14] input io_resp_in_0_f1_0_predicted_pc_valid, // @[predictor.scala:140:14] input [39:0] io_resp_in_0_f1_0_predicted_pc_bits, // @[predictor.scala:140:14] input io_resp_in_0_f1_1_taken, // @[predictor.scala:140:14] input io_resp_in_0_f1_1_is_br, // @[predictor.scala:140:14] input io_resp_in_0_f1_1_is_jal, // @[predictor.scala:140:14] input io_resp_in_0_f1_1_predicted_pc_valid, // @[predictor.scala:140:14] input [39:0] io_resp_in_0_f1_1_predicted_pc_bits, // @[predictor.scala:140:14] input io_resp_in_0_f1_2_taken, // @[predictor.scala:140:14] input io_resp_in_0_f1_2_is_br, // @[predictor.scala:140:14] input io_resp_in_0_f1_2_is_jal, // @[predictor.scala:140:14] input io_resp_in_0_f1_2_predicted_pc_valid, // @[predictor.scala:140:14] input [39:0] io_resp_in_0_f1_2_predicted_pc_bits, // @[predictor.scala:140:14] input io_resp_in_0_f1_3_taken, // @[predictor.scala:140:14] input io_resp_in_0_f1_3_is_br, // @[predictor.scala:140:14] input io_resp_in_0_f1_3_is_jal, // @[predictor.scala:140:14] input io_resp_in_0_f1_3_predicted_pc_valid, // @[predictor.scala:140:14] input [39:0] io_resp_in_0_f1_3_predicted_pc_bits, // @[predictor.scala:140:14] input io_resp_in_0_f2_0_taken, // @[predictor.scala:140:14] input io_resp_in_0_f2_0_is_br, // @[predictor.scala:140:14] input io_resp_in_0_f2_0_is_jal, // @[predictor.scala:140:14] input io_resp_in_0_f2_0_predicted_pc_valid, // @[predictor.scala:140:14] input [39:0] io_resp_in_0_f2_0_predicted_pc_bits, // @[predictor.scala:140:14] input io_resp_in_0_f2_1_taken, // @[predictor.scala:140:14] input io_resp_in_0_f2_1_is_br, // @[predictor.scala:140:14] input io_resp_in_0_f2_1_is_jal, // @[predictor.scala:140:14] input io_resp_in_0_f2_1_predicted_pc_valid, // @[predictor.scala:140:14] input [39:0] io_resp_in_0_f2_1_predicted_pc_bits, // @[predictor.scala:140:14] input io_resp_in_0_f2_2_taken, // @[predictor.scala:140:14] input io_resp_in_0_f2_2_is_br, // @[predictor.scala:140:14] input io_resp_in_0_f2_2_is_jal, // @[predictor.scala:140:14] input io_resp_in_0_f2_2_predicted_pc_valid, // @[predictor.scala:140:14] input [39:0] io_resp_in_0_f2_2_predicted_pc_bits, // @[predictor.scala:140:14] input io_resp_in_0_f2_3_taken, // @[predictor.scala:140:14] input io_resp_in_0_f2_3_is_br, // @[predictor.scala:140:14] input io_resp_in_0_f2_3_is_jal, // @[predictor.scala:140:14] input io_resp_in_0_f2_3_predicted_pc_valid, // @[predictor.scala:140:14] input [39:0] io_resp_in_0_f2_3_predicted_pc_bits, // @[predictor.scala:140:14] input io_resp_in_0_f3_0_taken, // @[predictor.scala:140:14] input io_resp_in_0_f3_0_is_br, // @[predictor.scala:140:14] input io_resp_in_0_f3_0_is_jal, // @[predictor.scala:140:14] input io_resp_in_0_f3_0_predicted_pc_valid, // @[predictor.scala:140:14] input [39:0] io_resp_in_0_f3_0_predicted_pc_bits, // @[predictor.scala:140:14] input io_resp_in_0_f3_1_taken, // @[predictor.scala:140:14] input io_resp_in_0_f3_1_is_br, // @[predictor.scala:140:14] input io_resp_in_0_f3_1_is_jal, // @[predictor.scala:140:14] input io_resp_in_0_f3_1_predicted_pc_valid, // @[predictor.scala:140:14] input [39:0] io_resp_in_0_f3_1_predicted_pc_bits, // @[predictor.scala:140:14] input io_resp_in_0_f3_2_taken, // @[predictor.scala:140:14] input io_resp_in_0_f3_2_is_br, // @[predictor.scala:140:14] input io_resp_in_0_f3_2_is_jal, // @[predictor.scala:140:14] input io_resp_in_0_f3_2_predicted_pc_valid, // @[predictor.scala:140:14] input [39:0] io_resp_in_0_f3_2_predicted_pc_bits, // @[predictor.scala:140:14] input io_resp_in_0_f3_3_taken, // @[predictor.scala:140:14] input io_resp_in_0_f3_3_is_br, // @[predictor.scala:140:14] input io_resp_in_0_f3_3_is_jal, // @[predictor.scala:140:14] input io_resp_in_0_f3_3_predicted_pc_valid, // @[predictor.scala:140:14] input [39:0] io_resp_in_0_f3_3_predicted_pc_bits, // @[predictor.scala:140:14] output io_resp_f1_0_taken, // @[predictor.scala:140:14] output io_resp_f1_0_is_br, // @[predictor.scala:140:14] output io_resp_f1_0_is_jal, // @[predictor.scala:140:14] output io_resp_f1_0_predicted_pc_valid, // @[predictor.scala:140:14] output [39:0] io_resp_f1_0_predicted_pc_bits, // @[predictor.scala:140:14] output io_resp_f1_1_taken, // @[predictor.scala:140:14] output io_resp_f1_1_is_br, // @[predictor.scala:140:14] output io_resp_f1_1_is_jal, // @[predictor.scala:140:14] output io_resp_f1_1_predicted_pc_valid, // @[predictor.scala:140:14] output [39:0] io_resp_f1_1_predicted_pc_bits, // @[predictor.scala:140:14] output io_resp_f1_2_taken, // @[predictor.scala:140:14] output io_resp_f1_2_is_br, // @[predictor.scala:140:14] output io_resp_f1_2_is_jal, // @[predictor.scala:140:14] output io_resp_f1_2_predicted_pc_valid, // @[predictor.scala:140:14] output [39:0] io_resp_f1_2_predicted_pc_bits, // @[predictor.scala:140:14] output io_resp_f1_3_taken, // @[predictor.scala:140:14] output io_resp_f1_3_is_br, // @[predictor.scala:140:14] output io_resp_f1_3_is_jal, // @[predictor.scala:140:14] output io_resp_f1_3_predicted_pc_valid, // @[predictor.scala:140:14] output [39:0] io_resp_f1_3_predicted_pc_bits, // @[predictor.scala:140:14] output io_resp_f2_0_taken, // @[predictor.scala:140:14] output io_resp_f2_0_is_br, // @[predictor.scala:140:14] output io_resp_f2_0_is_jal, // @[predictor.scala:140:14] output io_resp_f2_0_predicted_pc_valid, // @[predictor.scala:140:14] output [39:0] io_resp_f2_0_predicted_pc_bits, // @[predictor.scala:140:14] output io_resp_f2_1_taken, // @[predictor.scala:140:14] output io_resp_f2_1_is_br, // @[predictor.scala:140:14] output io_resp_f2_1_is_jal, // @[predictor.scala:140:14] output io_resp_f2_1_predicted_pc_valid, // @[predictor.scala:140:14] output [39:0] io_resp_f2_1_predicted_pc_bits, // @[predictor.scala:140:14] output io_resp_f2_2_taken, // @[predictor.scala:140:14] output io_resp_f2_2_is_br, // @[predictor.scala:140:14] output io_resp_f2_2_is_jal, // @[predictor.scala:140:14] output io_resp_f2_2_predicted_pc_valid, // @[predictor.scala:140:14] output [39:0] io_resp_f2_2_predicted_pc_bits, // @[predictor.scala:140:14] output io_resp_f2_3_taken, // @[predictor.scala:140:14] output io_resp_f2_3_is_br, // @[predictor.scala:140:14] output io_resp_f2_3_is_jal, // @[predictor.scala:140:14] output io_resp_f2_3_predicted_pc_valid, // @[predictor.scala:140:14] output [39:0] io_resp_f2_3_predicted_pc_bits, // @[predictor.scala:140:14] output io_resp_f3_0_taken, // @[predictor.scala:140:14] output io_resp_f3_0_is_br, // @[predictor.scala:140:14] output io_resp_f3_0_is_jal, // @[predictor.scala:140:14] output io_resp_f3_0_predicted_pc_valid, // @[predictor.scala:140:14] output [39:0] io_resp_f3_0_predicted_pc_bits, // @[predictor.scala:140:14] output io_resp_f3_1_taken, // @[predictor.scala:140:14] output io_resp_f3_1_is_br, // @[predictor.scala:140:14] output io_resp_f3_1_is_jal, // @[predictor.scala:140:14] output io_resp_f3_1_predicted_pc_valid, // @[predictor.scala:140:14] output [39:0] io_resp_f3_1_predicted_pc_bits, // @[predictor.scala:140:14] output io_resp_f3_2_taken, // @[predictor.scala:140:14] output io_resp_f3_2_is_br, // @[predictor.scala:140:14] output io_resp_f3_2_is_jal, // @[predictor.scala:140:14] output io_resp_f3_2_predicted_pc_valid, // @[predictor.scala:140:14] output [39:0] io_resp_f3_2_predicted_pc_bits, // @[predictor.scala:140:14] output io_resp_f3_3_taken, // @[predictor.scala:140:14] output io_resp_f3_3_is_br, // @[predictor.scala:140:14] output io_resp_f3_3_is_jal, // @[predictor.scala:140:14] output io_resp_f3_3_predicted_pc_valid, // @[predictor.scala:140:14] output [39:0] io_resp_f3_3_predicted_pc_bits, // @[predictor.scala:140:14] output [119:0] io_f3_meta, // @[predictor.scala:140:14] input io_f3_fire, // @[predictor.scala:140:14] input io_update_valid, // @[predictor.scala:140:14] input io_update_bits_is_mispredict_update, // @[predictor.scala:140:14] input io_update_bits_is_repair_update, // @[predictor.scala:140:14] input [3:0] io_update_bits_btb_mispredicts, // @[predictor.scala:140:14] input [39:0] io_update_bits_pc, // @[predictor.scala:140:14] input [3:0] io_update_bits_br_mask, // @[predictor.scala:140:14] input io_update_bits_cfi_idx_valid, // @[predictor.scala:140:14] input [1:0] io_update_bits_cfi_idx_bits, // @[predictor.scala:140:14] input io_update_bits_cfi_taken, // @[predictor.scala:140:14] input io_update_bits_cfi_mispredicted, // @[predictor.scala:140:14] input io_update_bits_cfi_is_br, // @[predictor.scala:140:14] input io_update_bits_cfi_is_jal, // @[predictor.scala:140:14] input io_update_bits_cfi_is_jalr, // @[predictor.scala:140:14] input [63:0] io_update_bits_ghist, // @[predictor.scala:140:14] input io_update_bits_lhist, // @[predictor.scala:140:14] input [39:0] io_update_bits_target, // @[predictor.scala:140:14] input [119:0] io_update_bits_meta // @[predictor.scala:140:14] ); wire io_f0_valid_0 = io_f0_valid; // @[loop.scala:20:7] wire [39:0] io_f0_pc_0 = io_f0_pc; // @[loop.scala:20:7] wire [3:0] io_f0_mask_0 = io_f0_mask; // @[loop.scala:20:7] wire [63:0] io_f1_ghist_0 = io_f1_ghist; // @[loop.scala:20:7] wire io_resp_in_0_f1_0_taken_0 = io_resp_in_0_f1_0_taken; // @[loop.scala:20:7] wire io_resp_in_0_f1_0_is_br_0 = io_resp_in_0_f1_0_is_br; // @[loop.scala:20:7] wire io_resp_in_0_f1_0_is_jal_0 = io_resp_in_0_f1_0_is_jal; // @[loop.scala:20:7] wire io_resp_in_0_f1_0_predicted_pc_valid_0 = io_resp_in_0_f1_0_predicted_pc_valid; // @[loop.scala:20:7] wire [39:0] io_resp_in_0_f1_0_predicted_pc_bits_0 = io_resp_in_0_f1_0_predicted_pc_bits; // @[loop.scala:20:7] wire io_resp_in_0_f1_1_taken_0 = io_resp_in_0_f1_1_taken; // @[loop.scala:20:7] wire io_resp_in_0_f1_1_is_br_0 = io_resp_in_0_f1_1_is_br; // @[loop.scala:20:7] wire io_resp_in_0_f1_1_is_jal_0 = io_resp_in_0_f1_1_is_jal; // @[loop.scala:20:7] wire io_resp_in_0_f1_1_predicted_pc_valid_0 = io_resp_in_0_f1_1_predicted_pc_valid; // @[loop.scala:20:7] wire [39:0] io_resp_in_0_f1_1_predicted_pc_bits_0 = io_resp_in_0_f1_1_predicted_pc_bits; // @[loop.scala:20:7] wire io_resp_in_0_f1_2_taken_0 = io_resp_in_0_f1_2_taken; // @[loop.scala:20:7] wire io_resp_in_0_f1_2_is_br_0 = io_resp_in_0_f1_2_is_br; // @[loop.scala:20:7] wire io_resp_in_0_f1_2_is_jal_0 = io_resp_in_0_f1_2_is_jal; // @[loop.scala:20:7] wire io_resp_in_0_f1_2_predicted_pc_valid_0 = io_resp_in_0_f1_2_predicted_pc_valid; // @[loop.scala:20:7] wire [39:0] io_resp_in_0_f1_2_predicted_pc_bits_0 = io_resp_in_0_f1_2_predicted_pc_bits; // @[loop.scala:20:7] wire io_resp_in_0_f1_3_taken_0 = io_resp_in_0_f1_3_taken; // @[loop.scala:20:7] wire io_resp_in_0_f1_3_is_br_0 = io_resp_in_0_f1_3_is_br; // @[loop.scala:20:7] wire io_resp_in_0_f1_3_is_jal_0 = io_resp_in_0_f1_3_is_jal; // @[loop.scala:20:7] wire io_resp_in_0_f1_3_predicted_pc_valid_0 = io_resp_in_0_f1_3_predicted_pc_valid; // @[loop.scala:20:7] wire [39:0] io_resp_in_0_f1_3_predicted_pc_bits_0 = io_resp_in_0_f1_3_predicted_pc_bits; // @[loop.scala:20:7] wire io_resp_in_0_f2_0_taken_0 = io_resp_in_0_f2_0_taken; // @[loop.scala:20:7] wire io_resp_in_0_f2_0_is_br_0 = io_resp_in_0_f2_0_is_br; // @[loop.scala:20:7] wire io_resp_in_0_f2_0_is_jal_0 = io_resp_in_0_f2_0_is_jal; // @[loop.scala:20:7] wire io_resp_in_0_f2_0_predicted_pc_valid_0 = io_resp_in_0_f2_0_predicted_pc_valid; // @[loop.scala:20:7] wire [39:0] io_resp_in_0_f2_0_predicted_pc_bits_0 = io_resp_in_0_f2_0_predicted_pc_bits; // @[loop.scala:20:7] wire io_resp_in_0_f2_1_taken_0 = io_resp_in_0_f2_1_taken; // @[loop.scala:20:7] wire io_resp_in_0_f2_1_is_br_0 = io_resp_in_0_f2_1_is_br; // @[loop.scala:20:7] wire io_resp_in_0_f2_1_is_jal_0 = io_resp_in_0_f2_1_is_jal; // @[loop.scala:20:7] wire io_resp_in_0_f2_1_predicted_pc_valid_0 = io_resp_in_0_f2_1_predicted_pc_valid; // @[loop.scala:20:7] wire [39:0] io_resp_in_0_f2_1_predicted_pc_bits_0 = io_resp_in_0_f2_1_predicted_pc_bits; // @[loop.scala:20:7] wire io_resp_in_0_f2_2_taken_0 = io_resp_in_0_f2_2_taken; // @[loop.scala:20:7] wire io_resp_in_0_f2_2_is_br_0 = io_resp_in_0_f2_2_is_br; // @[loop.scala:20:7] wire io_resp_in_0_f2_2_is_jal_0 = io_resp_in_0_f2_2_is_jal; // @[loop.scala:20:7] wire io_resp_in_0_f2_2_predicted_pc_valid_0 = io_resp_in_0_f2_2_predicted_pc_valid; // @[loop.scala:20:7] wire [39:0] io_resp_in_0_f2_2_predicted_pc_bits_0 = io_resp_in_0_f2_2_predicted_pc_bits; // @[loop.scala:20:7] wire io_resp_in_0_f2_3_taken_0 = io_resp_in_0_f2_3_taken; // @[loop.scala:20:7] wire io_resp_in_0_f2_3_is_br_0 = io_resp_in_0_f2_3_is_br; // @[loop.scala:20:7] wire io_resp_in_0_f2_3_is_jal_0 = io_resp_in_0_f2_3_is_jal; // @[loop.scala:20:7] wire io_resp_in_0_f2_3_predicted_pc_valid_0 = io_resp_in_0_f2_3_predicted_pc_valid; // @[loop.scala:20:7] wire [39:0] io_resp_in_0_f2_3_predicted_pc_bits_0 = io_resp_in_0_f2_3_predicted_pc_bits; // @[loop.scala:20:7] wire io_resp_in_0_f3_0_taken_0 = io_resp_in_0_f3_0_taken; // @[loop.scala:20:7] wire io_resp_in_0_f3_0_is_br_0 = io_resp_in_0_f3_0_is_br; // @[loop.scala:20:7] wire io_resp_in_0_f3_0_is_jal_0 = io_resp_in_0_f3_0_is_jal; // @[loop.scala:20:7] wire io_resp_in_0_f3_0_predicted_pc_valid_0 = io_resp_in_0_f3_0_predicted_pc_valid; // @[loop.scala:20:7] wire [39:0] io_resp_in_0_f3_0_predicted_pc_bits_0 = io_resp_in_0_f3_0_predicted_pc_bits; // @[loop.scala:20:7] wire io_resp_in_0_f3_1_taken_0 = io_resp_in_0_f3_1_taken; // @[loop.scala:20:7] wire io_resp_in_0_f3_1_is_br_0 = io_resp_in_0_f3_1_is_br; // @[loop.scala:20:7] wire io_resp_in_0_f3_1_is_jal_0 = io_resp_in_0_f3_1_is_jal; // @[loop.scala:20:7] wire io_resp_in_0_f3_1_predicted_pc_valid_0 = io_resp_in_0_f3_1_predicted_pc_valid; // @[loop.scala:20:7] wire [39:0] io_resp_in_0_f3_1_predicted_pc_bits_0 = io_resp_in_0_f3_1_predicted_pc_bits; // @[loop.scala:20:7] wire io_resp_in_0_f3_2_taken_0 = io_resp_in_0_f3_2_taken; // @[loop.scala:20:7] wire io_resp_in_0_f3_2_is_br_0 = io_resp_in_0_f3_2_is_br; // @[loop.scala:20:7] wire io_resp_in_0_f3_2_is_jal_0 = io_resp_in_0_f3_2_is_jal; // @[loop.scala:20:7] wire io_resp_in_0_f3_2_predicted_pc_valid_0 = io_resp_in_0_f3_2_predicted_pc_valid; // @[loop.scala:20:7] wire [39:0] io_resp_in_0_f3_2_predicted_pc_bits_0 = io_resp_in_0_f3_2_predicted_pc_bits; // @[loop.scala:20:7] wire io_resp_in_0_f3_3_taken_0 = io_resp_in_0_f3_3_taken; // @[loop.scala:20:7] wire io_resp_in_0_f3_3_is_br_0 = io_resp_in_0_f3_3_is_br; // @[loop.scala:20:7] wire io_resp_in_0_f3_3_is_jal_0 = io_resp_in_0_f3_3_is_jal; // @[loop.scala:20:7] wire io_resp_in_0_f3_3_predicted_pc_valid_0 = io_resp_in_0_f3_3_predicted_pc_valid; // @[loop.scala:20:7] wire [39:0] io_resp_in_0_f3_3_predicted_pc_bits_0 = io_resp_in_0_f3_3_predicted_pc_bits; // @[loop.scala:20:7] wire io_f3_fire_0 = io_f3_fire; // @[loop.scala:20:7] wire io_update_valid_0 = io_update_valid; // @[loop.scala:20:7] wire io_update_bits_is_mispredict_update_0 = io_update_bits_is_mispredict_update; // @[loop.scala:20:7] wire io_update_bits_is_repair_update_0 = io_update_bits_is_repair_update; // @[loop.scala:20:7] wire [3:0] io_update_bits_btb_mispredicts_0 = io_update_bits_btb_mispredicts; // @[loop.scala:20:7] wire [39:0] io_update_bits_pc_0 = io_update_bits_pc; // @[loop.scala:20:7] wire [3:0] io_update_bits_br_mask_0 = io_update_bits_br_mask; // @[loop.scala:20:7] wire io_update_bits_cfi_idx_valid_0 = io_update_bits_cfi_idx_valid; // @[loop.scala:20:7] wire [1:0] io_update_bits_cfi_idx_bits_0 = io_update_bits_cfi_idx_bits; // @[loop.scala:20:7] wire io_update_bits_cfi_taken_0 = io_update_bits_cfi_taken; // @[loop.scala:20:7] wire io_update_bits_cfi_mispredicted_0 = io_update_bits_cfi_mispredicted; // @[loop.scala:20:7] wire io_update_bits_cfi_is_br_0 = io_update_bits_cfi_is_br; // @[loop.scala:20:7] wire io_update_bits_cfi_is_jal_0 = io_update_bits_cfi_is_jal; // @[loop.scala:20:7] wire io_update_bits_cfi_is_jalr_0 = io_update_bits_cfi_is_jalr; // @[loop.scala:20:7] wire [63:0] io_update_bits_ghist_0 = io_update_bits_ghist; // @[loop.scala:20:7] wire io_update_bits_lhist_0 = io_update_bits_lhist; // @[loop.scala:20:7] wire [39:0] io_update_bits_target_0 = io_update_bits_target; // @[loop.scala:20:7] wire [119:0] io_update_bits_meta_0 = io_update_bits_meta; // @[loop.scala:20:7] wire io_f1_lhist = 1'h0; // @[predictor.scala:140:14] wire io_resp_f1_0_taken_0 = io_resp_in_0_f1_0_taken_0; // @[loop.scala:20:7] wire io_resp_f1_0_is_br_0 = io_resp_in_0_f1_0_is_br_0; // @[loop.scala:20:7] wire io_resp_f1_0_is_jal_0 = io_resp_in_0_f1_0_is_jal_0; // @[loop.scala:20:7] wire io_resp_f1_0_predicted_pc_valid_0 = io_resp_in_0_f1_0_predicted_pc_valid_0; // @[loop.scala:20:7] wire [39:0] io_resp_f1_0_predicted_pc_bits_0 = io_resp_in_0_f1_0_predicted_pc_bits_0; // @[loop.scala:20:7] wire io_resp_f1_1_taken_0 = io_resp_in_0_f1_1_taken_0; // @[loop.scala:20:7] wire io_resp_f1_1_is_br_0 = io_resp_in_0_f1_1_is_br_0; // @[loop.scala:20:7] wire io_resp_f1_1_is_jal_0 = io_resp_in_0_f1_1_is_jal_0; // @[loop.scala:20:7] wire io_resp_f1_1_predicted_pc_valid_0 = io_resp_in_0_f1_1_predicted_pc_valid_0; // @[loop.scala:20:7] wire [39:0] io_resp_f1_1_predicted_pc_bits_0 = io_resp_in_0_f1_1_predicted_pc_bits_0; // @[loop.scala:20:7] wire io_resp_f1_2_taken_0 = io_resp_in_0_f1_2_taken_0; // @[loop.scala:20:7] wire io_resp_f1_2_is_br_0 = io_resp_in_0_f1_2_is_br_0; // @[loop.scala:20:7] wire io_resp_f1_2_is_jal_0 = io_resp_in_0_f1_2_is_jal_0; // @[loop.scala:20:7] wire io_resp_f1_2_predicted_pc_valid_0 = io_resp_in_0_f1_2_predicted_pc_valid_0; // @[loop.scala:20:7] wire [39:0] io_resp_f1_2_predicted_pc_bits_0 = io_resp_in_0_f1_2_predicted_pc_bits_0; // @[loop.scala:20:7] wire io_resp_f1_3_taken_0 = io_resp_in_0_f1_3_taken_0; // @[loop.scala:20:7] wire io_resp_f1_3_is_br_0 = io_resp_in_0_f1_3_is_br_0; // @[loop.scala:20:7] wire io_resp_f1_3_is_jal_0 = io_resp_in_0_f1_3_is_jal_0; // @[loop.scala:20:7] wire io_resp_f1_3_predicted_pc_valid_0 = io_resp_in_0_f1_3_predicted_pc_valid_0; // @[loop.scala:20:7] wire [39:0] io_resp_f1_3_predicted_pc_bits_0 = io_resp_in_0_f1_3_predicted_pc_bits_0; // @[loop.scala:20:7] wire io_resp_f2_0_taken_0 = io_resp_in_0_f2_0_taken_0; // @[loop.scala:20:7] wire io_resp_f2_0_is_br_0 = io_resp_in_0_f2_0_is_br_0; // @[loop.scala:20:7] wire io_resp_f2_0_is_jal_0 = io_resp_in_0_f2_0_is_jal_0; // @[loop.scala:20:7] wire io_resp_f2_0_predicted_pc_valid_0 = io_resp_in_0_f2_0_predicted_pc_valid_0; // @[loop.scala:20:7] wire [39:0] io_resp_f2_0_predicted_pc_bits_0 = io_resp_in_0_f2_0_predicted_pc_bits_0; // @[loop.scala:20:7] wire io_resp_f2_1_taken_0 = io_resp_in_0_f2_1_taken_0; // @[loop.scala:20:7] wire io_resp_f2_1_is_br_0 = io_resp_in_0_f2_1_is_br_0; // @[loop.scala:20:7] wire io_resp_f2_1_is_jal_0 = io_resp_in_0_f2_1_is_jal_0; // @[loop.scala:20:7] wire io_resp_f2_1_predicted_pc_valid_0 = io_resp_in_0_f2_1_predicted_pc_valid_0; // @[loop.scala:20:7] wire [39:0] io_resp_f2_1_predicted_pc_bits_0 = io_resp_in_0_f2_1_predicted_pc_bits_0; // @[loop.scala:20:7] wire io_resp_f2_2_taken_0 = io_resp_in_0_f2_2_taken_0; // @[loop.scala:20:7] wire io_resp_f2_2_is_br_0 = io_resp_in_0_f2_2_is_br_0; // @[loop.scala:20:7] wire io_resp_f2_2_is_jal_0 = io_resp_in_0_f2_2_is_jal_0; // @[loop.scala:20:7] wire io_resp_f2_2_predicted_pc_valid_0 = io_resp_in_0_f2_2_predicted_pc_valid_0; // @[loop.scala:20:7] wire [39:0] io_resp_f2_2_predicted_pc_bits_0 = io_resp_in_0_f2_2_predicted_pc_bits_0; // @[loop.scala:20:7] wire io_resp_f2_3_taken_0 = io_resp_in_0_f2_3_taken_0; // @[loop.scala:20:7] wire io_resp_f2_3_is_br_0 = io_resp_in_0_f2_3_is_br_0; // @[loop.scala:20:7] wire io_resp_f2_3_is_jal_0 = io_resp_in_0_f2_3_is_jal_0; // @[loop.scala:20:7] wire io_resp_f2_3_predicted_pc_valid_0 = io_resp_in_0_f2_3_predicted_pc_valid_0; // @[loop.scala:20:7] wire [39:0] io_resp_f2_3_predicted_pc_bits_0 = io_resp_in_0_f2_3_predicted_pc_bits_0; // @[loop.scala:20:7] wire io_resp_f3_0_is_br_0 = io_resp_in_0_f3_0_is_br_0; // @[loop.scala:20:7] wire io_resp_f3_0_is_jal_0 = io_resp_in_0_f3_0_is_jal_0; // @[loop.scala:20:7] wire io_resp_f3_0_predicted_pc_valid_0 = io_resp_in_0_f3_0_predicted_pc_valid_0; // @[loop.scala:20:7] wire [39:0] io_resp_f3_0_predicted_pc_bits_0 = io_resp_in_0_f3_0_predicted_pc_bits_0; // @[loop.scala:20:7] wire io_resp_f3_1_is_br_0 = io_resp_in_0_f3_1_is_br_0; // @[loop.scala:20:7] wire io_resp_f3_1_is_jal_0 = io_resp_in_0_f3_1_is_jal_0; // @[loop.scala:20:7] wire io_resp_f3_1_predicted_pc_valid_0 = io_resp_in_0_f3_1_predicted_pc_valid_0; // @[loop.scala:20:7] wire [39:0] io_resp_f3_1_predicted_pc_bits_0 = io_resp_in_0_f3_1_predicted_pc_bits_0; // @[loop.scala:20:7] wire io_resp_f3_2_is_br_0 = io_resp_in_0_f3_2_is_br_0; // @[loop.scala:20:7] wire io_resp_f3_2_is_jal_0 = io_resp_in_0_f3_2_is_jal_0; // @[loop.scala:20:7] wire io_resp_f3_2_predicted_pc_valid_0 = io_resp_in_0_f3_2_predicted_pc_valid_0; // @[loop.scala:20:7] wire [39:0] io_resp_f3_2_predicted_pc_bits_0 = io_resp_in_0_f3_2_predicted_pc_bits_0; // @[loop.scala:20:7] wire io_resp_f3_3_is_br_0 = io_resp_in_0_f3_3_is_br_0; // @[loop.scala:20:7] wire io_resp_f3_3_is_jal_0 = io_resp_in_0_f3_3_is_jal_0; // @[loop.scala:20:7] wire io_resp_f3_3_predicted_pc_valid_0 = io_resp_in_0_f3_3_predicted_pc_valid_0; // @[loop.scala:20:7] wire [39:0] io_resp_f3_3_predicted_pc_bits_0 = io_resp_in_0_f3_3_predicted_pc_bits_0; // @[loop.scala:20:7] wire io_resp_f3_0_taken_0; // @[loop.scala:20:7] wire io_resp_f3_1_taken_0; // @[loop.scala:20:7] wire io_resp_f3_2_taken_0; // @[loop.scala:20:7] wire io_resp_f3_3_taken_0; // @[loop.scala:20:7] wire [119:0] io_f3_meta_0; // @[loop.scala:20:7] wire [35:0] s0_idx = io_f0_pc_0[39:4]; // @[frontend.scala:162:35] reg [35:0] s1_idx; // @[predictor.scala:163:29] reg [35:0] s2_idx; // @[predictor.scala:164:29] reg [35:0] s3_idx; // @[predictor.scala:165:29] reg s1_valid; // @[predictor.scala:168:25] reg s2_valid; // @[predictor.scala:169:25] reg s3_valid; // @[predictor.scala:170:25] reg [3:0] s1_mask; // @[predictor.scala:173:24] reg [3:0] s2_mask; // @[predictor.scala:174:24] reg [3:0] s3_mask; // @[predictor.scala:175:24] reg [39:0] s1_pc; // @[predictor.scala:178:22] wire [35:0] s0_update_idx = io_update_bits_pc_0[39:4]; // @[frontend.scala:162:35] reg s1_update_valid; // @[predictor.scala:184:30] reg s1_update_bits_is_mispredict_update; // @[predictor.scala:184:30] reg s1_update_bits_is_repair_update; // @[predictor.scala:184:30] reg [3:0] s1_update_bits_btb_mispredicts; // @[predictor.scala:184:30] reg [39:0] s1_update_bits_pc; // @[predictor.scala:184:30] reg [3:0] s1_update_bits_br_mask; // @[predictor.scala:184:30] reg s1_update_bits_cfi_idx_valid; // @[predictor.scala:184:30] reg [1:0] s1_update_bits_cfi_idx_bits; // @[predictor.scala:184:30] reg s1_update_bits_cfi_taken; // @[predictor.scala:184:30] reg s1_update_bits_cfi_mispredicted; // @[predictor.scala:184:30] reg s1_update_bits_cfi_is_br; // @[predictor.scala:184:30] reg s1_update_bits_cfi_is_jal; // @[predictor.scala:184:30] reg s1_update_bits_cfi_is_jalr; // @[predictor.scala:184:30] reg [63:0] s1_update_bits_ghist; // @[predictor.scala:184:30] reg s1_update_bits_lhist; // @[predictor.scala:184:30] reg [39:0] s1_update_bits_target; // @[predictor.scala:184:30] reg [119:0] s1_update_bits_meta; // @[predictor.scala:184:30] reg [35:0] s1_update_idx; // @[predictor.scala:185:30] reg s1_update_valid_0; // @[predictor.scala:186:32] wire [9:0] f3_meta_0_s_cnt; // @[loop.scala:184:21] wire [9:0] f3_meta_1_s_cnt; // @[loop.scala:184:21] wire [9:0] f3_meta_2_s_cnt; // @[loop.scala:184:21] wire [9:0] f3_meta_3_s_cnt; // @[loop.scala:184:21] wire [19:0] _GEN = {f3_meta_1_s_cnt, f3_meta_0_s_cnt}; // @[loop.scala:184:21, :185:33] wire [19:0] lo; // @[loop.scala:185:33] assign lo = _GEN; // @[loop.scala:185:33] wire [19:0] io_f3_meta_lo; // @[loop.scala:212:25] assign io_f3_meta_lo = _GEN; // @[loop.scala:185:33, :212:25] wire [19:0] _GEN_0 = {f3_meta_3_s_cnt, f3_meta_2_s_cnt}; // @[loop.scala:184:21, :185:33] wire [19:0] hi; // @[loop.scala:185:33] assign hi = _GEN_0; // @[loop.scala:185:33] wire [19:0] io_f3_meta_hi; // @[loop.scala:212:25] assign io_f3_meta_hi = _GEN_0; // @[loop.scala:185:33, :212:25] wire [9:0] _update_meta_T; // @[loop.scala:187:49] wire [9:0] _update_meta_T_1; // @[loop.scala:187:49] wire [9:0] _update_meta_T_2; // @[loop.scala:187:49] wire [9:0] _update_meta_T_3; // @[loop.scala:187:49] wire [9:0] update_meta_0_s_cnt; // @[loop.scala:187:49] wire [9:0] update_meta_1_s_cnt; // @[loop.scala:187:49] wire [9:0] update_meta_2_s_cnt; // @[loop.scala:187:49] wire [9:0] update_meta_3_s_cnt; // @[loop.scala:187:49] wire [39:0] _update_meta_WIRE = s1_update_bits_meta[39:0]; // @[predictor.scala:184:30] assign _update_meta_T = _update_meta_WIRE[9:0]; // @[loop.scala:187:49] assign update_meta_0_s_cnt = _update_meta_T; // @[loop.scala:187:49] assign _update_meta_T_1 = _update_meta_WIRE[19:10]; // @[loop.scala:187:49] assign update_meta_1_s_cnt = _update_meta_T_1; // @[loop.scala:187:49] assign _update_meta_T_2 = _update_meta_WIRE[29:20]; // @[loop.scala:187:49] assign update_meta_2_s_cnt = _update_meta_T_2; // @[loop.scala:187:49] assign _update_meta_T_3 = _update_meta_WIRE[39:30]; // @[loop.scala:187:49] assign update_meta_3_s_cnt = _update_meta_T_3; // @[loop.scala:187:49] wire _columns_0_io_f3_req_fire_T = s3_mask[0]; // @[predictor.scala:175:24] wire _columns_0_io_f3_req_fire_T_1 = s3_valid & _columns_0_io_f3_req_fire_T; // @[predictor.scala:170:25] wire _columns_0_io_f3_req_fire_T_2 = _columns_0_io_f3_req_fire_T_1 & io_f3_fire_0; // @[loop.scala:20:7, :192:{44,58}] wire _columns_0_io_f3_req_fire_T_3 = io_resp_in_0_f2_0_predicted_pc_valid_0 & io_resp_in_0_f2_0_is_br_0; // @[loop.scala:20:7, :193:54] reg columns_0_io_f3_req_fire_REG; // @[loop.scala:193:14] wire _columns_0_io_f3_req_fire_T_4 = _columns_0_io_f3_req_fire_T_2 & columns_0_io_f3_req_fire_REG; // @[loop.scala:192:{58,72}, :193:14] wire _columns_0_io_update_mispredict_T = s1_update_bits_br_mask[0]; // @[predictor.scala:184:30] wire _columns_0_io_update_repair_T = s1_update_bits_br_mask[0]; // @[predictor.scala:184:30] wire _columns_0_io_update_mispredict_T_1 = s1_update_valid & _columns_0_io_update_mispredict_T; // @[predictor.scala:184:30] wire _columns_0_io_update_mispredict_T_2 = _columns_0_io_update_mispredict_T_1 & s1_update_bits_is_mispredict_update; // @[predictor.scala:184:30] wire _columns_0_io_update_mispredict_T_3 = _columns_0_io_update_mispredict_T_2 & s1_update_bits_cfi_mispredicted; // @[predictor.scala:184:30] wire _columns_0_io_update_repair_T_1 = s1_update_valid & _columns_0_io_update_repair_T; // @[predictor.scala:184:30] wire _columns_0_io_update_repair_T_2 = _columns_0_io_update_repair_T_1 & s1_update_bits_is_repair_update; // @[predictor.scala:184:30] wire _columns_1_io_f3_req_fire_T = s3_mask[1]; // @[predictor.scala:175:24] wire _columns_1_io_f3_req_fire_T_1 = s3_valid & _columns_1_io_f3_req_fire_T; // @[predictor.scala:170:25] wire _columns_1_io_f3_req_fire_T_2 = _columns_1_io_f3_req_fire_T_1 & io_f3_fire_0; // @[loop.scala:20:7, :192:{44,58}] wire _columns_1_io_f3_req_fire_T_3 = io_resp_in_0_f2_1_predicted_pc_valid_0 & io_resp_in_0_f2_1_is_br_0; // @[loop.scala:20:7, :193:54] reg columns_1_io_f3_req_fire_REG; // @[loop.scala:193:14] wire _columns_1_io_f3_req_fire_T_4 = _columns_1_io_f3_req_fire_T_2 & columns_1_io_f3_req_fire_REG; // @[loop.scala:192:{58,72}, :193:14] wire _columns_1_io_update_mispredict_T = s1_update_bits_br_mask[1]; // @[predictor.scala:184:30] wire _columns_1_io_update_repair_T = s1_update_bits_br_mask[1]; // @[predictor.scala:184:30] wire _columns_1_io_update_mispredict_T_1 = s1_update_valid & _columns_1_io_update_mispredict_T; // @[predictor.scala:184:30] wire _columns_1_io_update_mispredict_T_2 = _columns_1_io_update_mispredict_T_1 & s1_update_bits_is_mispredict_update; // @[predictor.scala:184:30] wire _columns_1_io_update_mispredict_T_3 = _columns_1_io_update_mispredict_T_2 & s1_update_bits_cfi_mispredicted; // @[predictor.scala:184:30] wire _columns_1_io_update_repair_T_1 = s1_update_valid & _columns_1_io_update_repair_T; // @[predictor.scala:184:30] wire _columns_1_io_update_repair_T_2 = _columns_1_io_update_repair_T_1 & s1_update_bits_is_repair_update; // @[predictor.scala:184:30] wire _columns_2_io_f3_req_fire_T = s3_mask[2]; // @[predictor.scala:175:24] wire _columns_2_io_f3_req_fire_T_1 = s3_valid & _columns_2_io_f3_req_fire_T; // @[predictor.scala:170:25] wire _columns_2_io_f3_req_fire_T_2 = _columns_2_io_f3_req_fire_T_1 & io_f3_fire_0; // @[loop.scala:20:7, :192:{44,58}] wire _columns_2_io_f3_req_fire_T_3 = io_resp_in_0_f2_2_predicted_pc_valid_0 & io_resp_in_0_f2_2_is_br_0; // @[loop.scala:20:7, :193:54] reg columns_2_io_f3_req_fire_REG; // @[loop.scala:193:14] wire _columns_2_io_f3_req_fire_T_4 = _columns_2_io_f3_req_fire_T_2 & columns_2_io_f3_req_fire_REG; // @[loop.scala:192:{58,72}, :193:14] wire _columns_2_io_update_mispredict_T = s1_update_bits_br_mask[2]; // @[predictor.scala:184:30] wire _columns_2_io_update_repair_T = s1_update_bits_br_mask[2]; // @[predictor.scala:184:30] wire _columns_2_io_update_mispredict_T_1 = s1_update_valid & _columns_2_io_update_mispredict_T; // @[predictor.scala:184:30] wire _columns_2_io_update_mispredict_T_2 = _columns_2_io_update_mispredict_T_1 & s1_update_bits_is_mispredict_update; // @[predictor.scala:184:30] wire _columns_2_io_update_mispredict_T_3 = _columns_2_io_update_mispredict_T_2 & s1_update_bits_cfi_mispredicted; // @[predictor.scala:184:30] wire _columns_2_io_update_repair_T_1 = s1_update_valid & _columns_2_io_update_repair_T; // @[predictor.scala:184:30] wire _columns_2_io_update_repair_T_2 = _columns_2_io_update_repair_T_1 & s1_update_bits_is_repair_update; // @[predictor.scala:184:30] wire _columns_3_io_f3_req_fire_T = s3_mask[3]; // @[predictor.scala:175:24] wire _columns_3_io_f3_req_fire_T_1 = s3_valid & _columns_3_io_f3_req_fire_T; // @[predictor.scala:170:25] wire _columns_3_io_f3_req_fire_T_2 = _columns_3_io_f3_req_fire_T_1 & io_f3_fire_0; // @[loop.scala:20:7, :192:{44,58}] wire _columns_3_io_f3_req_fire_T_3 = io_resp_in_0_f2_3_predicted_pc_valid_0 & io_resp_in_0_f2_3_is_br_0; // @[loop.scala:20:7, :193:54] reg columns_3_io_f3_req_fire_REG; // @[loop.scala:193:14] wire _columns_3_io_f3_req_fire_T_4 = _columns_3_io_f3_req_fire_T_2 & columns_3_io_f3_req_fire_REG; // @[loop.scala:192:{58,72}, :193:14] wire _columns_3_io_update_mispredict_T = s1_update_bits_br_mask[3]; // @[predictor.scala:184:30] wire _columns_3_io_update_repair_T = s1_update_bits_br_mask[3]; // @[predictor.scala:184:30] wire _columns_3_io_update_mispredict_T_1 = s1_update_valid & _columns_3_io_update_mispredict_T; // @[predictor.scala:184:30] wire _columns_3_io_update_mispredict_T_2 = _columns_3_io_update_mispredict_T_1 & s1_update_bits_is_mispredict_update; // @[predictor.scala:184:30] wire _columns_3_io_update_mispredict_T_3 = _columns_3_io_update_mispredict_T_2 & s1_update_bits_cfi_mispredicted; // @[predictor.scala:184:30] wire _columns_3_io_update_repair_T_1 = s1_update_valid & _columns_3_io_update_repair_T; // @[predictor.scala:184:30] wire _columns_3_io_update_repair_T_2 = _columns_3_io_update_repair_T_1 & s1_update_bits_is_repair_update; // @[predictor.scala:184:30] wire [39:0] _io_f3_meta_T = {io_f3_meta_hi, io_f3_meta_lo}; // @[loop.scala:212:25] assign io_f3_meta_0 = {80'h0, _io_f3_meta_T}; // @[loop.scala:20:7, :212:{14,25}] always @(posedge clock) begin // @[loop.scala:20:7] s1_idx <= s0_idx; // @[frontend.scala:162:35] s2_idx <= s1_idx; // @[predictor.scala:163:29, :164:29] s3_idx <= s2_idx; // @[predictor.scala:164:29, :165:29] s1_valid <= io_f0_valid_0; // @[predictor.scala:168:25] s2_valid <= s1_valid; // @[predictor.scala:168:25, :169:25] s3_valid <= s2_valid; // @[predictor.scala:169:25, :170:25] s1_mask <= io_f0_mask_0; // @[predictor.scala:173:24] s2_mask <= s1_mask; // @[predictor.scala:173:24, :174:24] s3_mask <= s2_mask; // @[predictor.scala:174:24, :175:24] s1_pc <= io_f0_pc_0; // @[predictor.scala:178:22] s1_update_valid <= io_update_valid_0; // @[predictor.scala:184:30] s1_update_bits_is_mispredict_update <= io_update_bits_is_mispredict_update_0; // @[predictor.scala:184:30] s1_update_bits_is_repair_update <= io_update_bits_is_repair_update_0; // @[predictor.scala:184:30] s1_update_bits_btb_mispredicts <= io_update_bits_btb_mispredicts_0; // @[predictor.scala:184:30] s1_update_bits_pc <= io_update_bits_pc_0; // @[predictor.scala:184:30] s1_update_bits_br_mask <= io_update_bits_br_mask_0; // @[predictor.scala:184:30] s1_update_bits_cfi_idx_valid <= io_update_bits_cfi_idx_valid_0; // @[predictor.scala:184:30] s1_update_bits_cfi_idx_bits <= io_update_bits_cfi_idx_bits_0; // @[predictor.scala:184:30] s1_update_bits_cfi_taken <= io_update_bits_cfi_taken_0; // @[predictor.scala:184:30] s1_update_bits_cfi_mispredicted <= io_update_bits_cfi_mispredicted_0; // @[predictor.scala:184:30] s1_update_bits_cfi_is_br <= io_update_bits_cfi_is_br_0; // @[predictor.scala:184:30] s1_update_bits_cfi_is_jal <= io_update_bits_cfi_is_jal_0; // @[predictor.scala:184:30] s1_update_bits_cfi_is_jalr <= io_update_bits_cfi_is_jalr_0; // @[predictor.scala:184:30] s1_update_bits_ghist <= io_update_bits_ghist_0; // @[predictor.scala:184:30] s1_update_bits_lhist <= io_update_bits_lhist_0; // @[predictor.scala:184:30] s1_update_bits_target <= io_update_bits_target_0; // @[predictor.scala:184:30] s1_update_bits_meta <= io_update_bits_meta_0; // @[predictor.scala:184:30] s1_update_idx <= s0_update_idx; // @[frontend.scala:162:35] s1_update_valid_0 <= io_update_valid_0; // @[predictor.scala:186:32] columns_0_io_f3_req_fire_REG <= _columns_0_io_f3_req_fire_T_3; // @[loop.scala:193:{14,54}] columns_1_io_f3_req_fire_REG <= _columns_1_io_f3_req_fire_T_3; // @[loop.scala:193:{14,54}] columns_2_io_f3_req_fire_REG <= _columns_2_io_f3_req_fire_T_3; // @[loop.scala:193:{14,54}] columns_3_io_f3_req_fire_REG <= _columns_3_io_f3_req_fire_T_3; // @[loop.scala:193:{14,54}] always @(posedge) LoopBranchPredictorColumn columns_0 ( // @[loop.scala:182:45] .clock (clock), .reset (reset), .io_f2_req_valid (s2_valid), // @[predictor.scala:169:25] .io_f2_req_idx (s2_idx), // @[predictor.scala:164:29] .io_f3_req_fire (_columns_0_io_f3_req_fire_T_4), // @[loop.scala:192:72] .io_f3_pred_in (io_resp_in_0_f3_0_taken_0), // @[loop.scala:20:7] .io_f3_pred (io_resp_f3_0_taken_0), .io_f3_meta_s_cnt (f3_meta_0_s_cnt), .io_update_mispredict (_columns_0_io_update_mispredict_T_3), // @[loop.scala:200:82] .io_update_repair (_columns_0_io_update_repair_T_2), // @[loop.scala:203:72] .io_update_idx (s1_update_idx), // @[predictor.scala:185:30] .io_update_resolve_dir (s1_update_bits_cfi_taken), // @[predictor.scala:184:30] .io_update_meta_s_cnt (update_meta_0_s_cnt) // @[loop.scala:187:49] ); // @[loop.scala:182:45] LoopBranchPredictorColumn_1 columns_1 ( // @[loop.scala:182:45] .clock (clock), .reset (reset), .io_f2_req_valid (s2_valid), // @[predictor.scala:169:25] .io_f2_req_idx (s2_idx), // @[predictor.scala:164:29] .io_f3_req_fire (_columns_1_io_f3_req_fire_T_4), // @[loop.scala:192:72] .io_f3_pred_in (io_resp_in_0_f3_1_taken_0), // @[loop.scala:20:7] .io_f3_pred (io_resp_f3_1_taken_0), .io_f3_meta_s_cnt (f3_meta_1_s_cnt), .io_update_mispredict (_columns_1_io_update_mispredict_T_3), // @[loop.scala:200:82] .io_update_repair (_columns_1_io_update_repair_T_2), // @[loop.scala:203:72] .io_update_idx (s1_update_idx), // @[predictor.scala:185:30] .io_update_resolve_dir (s1_update_bits_cfi_taken), // @[predictor.scala:184:30] .io_update_meta_s_cnt (update_meta_1_s_cnt) // @[loop.scala:187:49] ); // @[loop.scala:182:45] LoopBranchPredictorColumn_2 columns_2 ( // @[loop.scala:182:45] .clock (clock), .reset (reset), .io_f2_req_valid (s2_valid), // @[predictor.scala:169:25] .io_f2_req_idx (s2_idx), // @[predictor.scala:164:29] .io_f3_req_fire (_columns_2_io_f3_req_fire_T_4), // @[loop.scala:192:72] .io_f3_pred_in (io_resp_in_0_f3_2_taken_0), // @[loop.scala:20:7] .io_f3_pred (io_resp_f3_2_taken_0), .io_f3_meta_s_cnt (f3_meta_2_s_cnt), .io_update_mispredict (_columns_2_io_update_mispredict_T_3), // @[loop.scala:200:82] .io_update_repair (_columns_2_io_update_repair_T_2), // @[loop.scala:203:72] .io_update_idx (s1_update_idx), // @[predictor.scala:185:30] .io_update_resolve_dir (s1_update_bits_cfi_taken), // @[predictor.scala:184:30] .io_update_meta_s_cnt (update_meta_2_s_cnt) // @[loop.scala:187:49] ); // @[loop.scala:182:45] LoopBranchPredictorColumn_3 columns_3 ( // @[loop.scala:182:45] .clock (clock), .reset (reset), .io_f2_req_valid (s2_valid), // @[predictor.scala:169:25] .io_f2_req_idx (s2_idx), // @[predictor.scala:164:29] .io_f3_req_fire (_columns_3_io_f3_req_fire_T_4), // @[loop.scala:192:72] .io_f3_pred_in (io_resp_in_0_f3_3_taken_0), // @[loop.scala:20:7] .io_f3_pred (io_resp_f3_3_taken_0), .io_f3_meta_s_cnt (f3_meta_3_s_cnt), .io_update_mispredict (_columns_3_io_update_mispredict_T_3), // @[loop.scala:200:82] .io_update_repair (_columns_3_io_update_repair_T_2), // @[loop.scala:203:72] .io_update_idx (s1_update_idx), // @[predictor.scala:185:30] .io_update_resolve_dir (s1_update_bits_cfi_taken), // @[predictor.scala:184:30] .io_update_meta_s_cnt (update_meta_3_s_cnt) // @[loop.scala:187:49] ); // @[loop.scala:182:45] assign io_resp_f1_0_taken = io_resp_f1_0_taken_0; // @[loop.scala:20:7] assign io_resp_f1_0_is_br = io_resp_f1_0_is_br_0; // @[loop.scala:20:7] assign io_resp_f1_0_is_jal = io_resp_f1_0_is_jal_0; // @[loop.scala:20:7] assign io_resp_f1_0_predicted_pc_valid = io_resp_f1_0_predicted_pc_valid_0; // @[loop.scala:20:7] assign io_resp_f1_0_predicted_pc_bits = io_resp_f1_0_predicted_pc_bits_0; // @[loop.scala:20:7] assign io_resp_f1_1_taken = io_resp_f1_1_taken_0; // @[loop.scala:20:7] assign io_resp_f1_1_is_br = io_resp_f1_1_is_br_0; // @[loop.scala:20:7] assign io_resp_f1_1_is_jal = io_resp_f1_1_is_jal_0; // @[loop.scala:20:7] assign io_resp_f1_1_predicted_pc_valid = io_resp_f1_1_predicted_pc_valid_0; // @[loop.scala:20:7] assign io_resp_f1_1_predicted_pc_bits = io_resp_f1_1_predicted_pc_bits_0; // @[loop.scala:20:7] assign io_resp_f1_2_taken = io_resp_f1_2_taken_0; // @[loop.scala:20:7] assign io_resp_f1_2_is_br = io_resp_f1_2_is_br_0; // @[loop.scala:20:7] assign io_resp_f1_2_is_jal = io_resp_f1_2_is_jal_0; // @[loop.scala:20:7] assign io_resp_f1_2_predicted_pc_valid = io_resp_f1_2_predicted_pc_valid_0; // @[loop.scala:20:7] assign io_resp_f1_2_predicted_pc_bits = io_resp_f1_2_predicted_pc_bits_0; // @[loop.scala:20:7] assign io_resp_f1_3_taken = io_resp_f1_3_taken_0; // @[loop.scala:20:7] assign io_resp_f1_3_is_br = io_resp_f1_3_is_br_0; // @[loop.scala:20:7] assign io_resp_f1_3_is_jal = io_resp_f1_3_is_jal_0; // @[loop.scala:20:7] assign io_resp_f1_3_predicted_pc_valid = io_resp_f1_3_predicted_pc_valid_0; // @[loop.scala:20:7] assign io_resp_f1_3_predicted_pc_bits = io_resp_f1_3_predicted_pc_bits_0; // @[loop.scala:20:7] assign io_resp_f2_0_taken = io_resp_f2_0_taken_0; // @[loop.scala:20:7] assign io_resp_f2_0_is_br = io_resp_f2_0_is_br_0; // @[loop.scala:20:7] assign io_resp_f2_0_is_jal = io_resp_f2_0_is_jal_0; // @[loop.scala:20:7] assign io_resp_f2_0_predicted_pc_valid = io_resp_f2_0_predicted_pc_valid_0; // @[loop.scala:20:7] assign io_resp_f2_0_predicted_pc_bits = io_resp_f2_0_predicted_pc_bits_0; // @[loop.scala:20:7] assign io_resp_f2_1_taken = io_resp_f2_1_taken_0; // @[loop.scala:20:7] assign io_resp_f2_1_is_br = io_resp_f2_1_is_br_0; // @[loop.scala:20:7] assign io_resp_f2_1_is_jal = io_resp_f2_1_is_jal_0; // @[loop.scala:20:7] assign io_resp_f2_1_predicted_pc_valid = io_resp_f2_1_predicted_pc_valid_0; // @[loop.scala:20:7] assign io_resp_f2_1_predicted_pc_bits = io_resp_f2_1_predicted_pc_bits_0; // @[loop.scala:20:7] assign io_resp_f2_2_taken = io_resp_f2_2_taken_0; // @[loop.scala:20:7] assign io_resp_f2_2_is_br = io_resp_f2_2_is_br_0; // @[loop.scala:20:7] assign io_resp_f2_2_is_jal = io_resp_f2_2_is_jal_0; // @[loop.scala:20:7] assign io_resp_f2_2_predicted_pc_valid = io_resp_f2_2_predicted_pc_valid_0; // @[loop.scala:20:7] assign io_resp_f2_2_predicted_pc_bits = io_resp_f2_2_predicted_pc_bits_0; // @[loop.scala:20:7] assign io_resp_f2_3_taken = io_resp_f2_3_taken_0; // @[loop.scala:20:7] assign io_resp_f2_3_is_br = io_resp_f2_3_is_br_0; // @[loop.scala:20:7] assign io_resp_f2_3_is_jal = io_resp_f2_3_is_jal_0; // @[loop.scala:20:7] assign io_resp_f2_3_predicted_pc_valid = io_resp_f2_3_predicted_pc_valid_0; // @[loop.scala:20:7] assign io_resp_f2_3_predicted_pc_bits = io_resp_f2_3_predicted_pc_bits_0; // @[loop.scala:20:7] assign io_resp_f3_0_taken = io_resp_f3_0_taken_0; // @[loop.scala:20:7] assign io_resp_f3_0_is_br = io_resp_f3_0_is_br_0; // @[loop.scala:20:7] assign io_resp_f3_0_is_jal = io_resp_f3_0_is_jal_0; // @[loop.scala:20:7] assign io_resp_f3_0_predicted_pc_valid = io_resp_f3_0_predicted_pc_valid_0; // @[loop.scala:20:7] assign io_resp_f3_0_predicted_pc_bits = io_resp_f3_0_predicted_pc_bits_0; // @[loop.scala:20:7] assign io_resp_f3_1_taken = io_resp_f3_1_taken_0; // @[loop.scala:20:7] assign io_resp_f3_1_is_br = io_resp_f3_1_is_br_0; // @[loop.scala:20:7] assign io_resp_f3_1_is_jal = io_resp_f3_1_is_jal_0; // @[loop.scala:20:7] assign io_resp_f3_1_predicted_pc_valid = io_resp_f3_1_predicted_pc_valid_0; // @[loop.scala:20:7] assign io_resp_f3_1_predicted_pc_bits = io_resp_f3_1_predicted_pc_bits_0; // @[loop.scala:20:7] assign io_resp_f3_2_taken = io_resp_f3_2_taken_0; // @[loop.scala:20:7] assign io_resp_f3_2_is_br = io_resp_f3_2_is_br_0; // @[loop.scala:20:7] assign io_resp_f3_2_is_jal = io_resp_f3_2_is_jal_0; // @[loop.scala:20:7] assign io_resp_f3_2_predicted_pc_valid = io_resp_f3_2_predicted_pc_valid_0; // @[loop.scala:20:7] assign io_resp_f3_2_predicted_pc_bits = io_resp_f3_2_predicted_pc_bits_0; // @[loop.scala:20:7] assign io_resp_f3_3_taken = io_resp_f3_3_taken_0; // @[loop.scala:20:7] assign io_resp_f3_3_is_br = io_resp_f3_3_is_br_0; // @[loop.scala:20:7] assign io_resp_f3_3_is_jal = io_resp_f3_3_is_jal_0; // @[loop.scala:20:7] assign io_resp_f3_3_predicted_pc_valid = io_resp_f3_3_predicted_pc_valid_0; // @[loop.scala:20:7] assign io_resp_f3_3_predicted_pc_bits = io_resp_f3_3_predicted_pc_bits_0; // @[loop.scala:20:7] assign io_f3_meta = io_f3_meta_0; // @[loop.scala:20:7] endmodule

Generate the Verilog code corresponding to the following Chisel files. File TilelinkAdapters.scala: package constellation.protocol import chisel3._ import chisel3.util._ import constellation.channel._ import constellation.noc._ import constellation.soc.{CanAttachToGlobalNoC} import org.chipsalliance.cde.config._ import freechips.rocketchip.diplomacy._ import freechips.rocketchip.util._ import freechips.rocketchip.tilelink._ import scala.collection.immutable.{ListMap} abstract class TLChannelToNoC[T <: TLChannel](gen: => T, edge: TLEdge, idToEgress: Int => Int)(implicit val p: Parameters) extends Module with TLFieldHelper { val flitWidth = minTLPayloadWidth(gen) val io = IO(new Bundle { val protocol = Flipped(Decoupled(gen)) val flit = Decoupled(new IngressFlit(flitWidth)) }) def unique(x: Vector[Boolean]): Bool = (x.filter(x=>x).size <= 1).B // convert decoupled to irrevocable val q = Module(new Queue(gen, 1, pipe=true, flow=true)) val protocol = q.io.deq val has_body = Wire(Bool()) val body_fields = getBodyFields(protocol.bits) val const_fields = getConstFields(protocol.bits) val head = edge.first(protocol.bits, protocol.fire) val tail = edge.last(protocol.bits, protocol.fire) def requestOH: Seq[Bool] val body = Cat( body_fields.filter(_.getWidth > 0).map(_.asUInt)) val const = Cat(const_fields.filter(_.getWidth > 0).map(_.asUInt)) val is_body = RegInit(false.B) io.flit.valid := protocol.valid protocol.ready := io.flit.ready && (is_body || !has_body) io.flit.bits.head := head && !is_body io.flit.bits.tail := tail && (is_body || !has_body) io.flit.bits.egress_id := Mux1H(requestOH.zipWithIndex.map { case (r, i) => r -> idToEgress(i).U }) io.flit.bits.payload := Mux(is_body, body, const) when (io.flit.fire && io.flit.bits.head) { is_body := true.B } when (io.flit.fire && io.flit.bits.tail) { is_body := false.B } } abstract class TLChannelFromNoC[T <: TLChannel](gen: => T)(implicit val p: Parameters) extends Module with TLFieldHelper { val flitWidth = minTLPayloadWidth(gen) val io = IO(new Bundle { val protocol = Decoupled(gen) val flit = Flipped(Decoupled(new EgressFlit(flitWidth))) }) // Handle size = 1 gracefully (Chisel3 empty range is broken) def trim(id: UInt, size: Int): UInt = if (size <= 1) 0.U else id(log2Ceil(size)-1, 0) val protocol = Wire(Decoupled(gen)) val body_fields = getBodyFields(protocol.bits) val const_fields = getConstFields(protocol.bits) val is_const = RegInit(true.B) val const_reg = Reg(UInt(const_fields.map(_.getWidth).sum.W)) val const = Mux(io.flit.bits.head, io.flit.bits.payload, const_reg) io.flit.ready := (is_const && !io.flit.bits.tail) || protocol.ready protocol.valid := (!is_const || io.flit.bits.tail) && io.flit.valid def assign(i: UInt, sigs: Seq[Data]) = { var t = i for (s <- sigs.reverse) { s := t.asTypeOf(s.cloneType) t = t >> s.getWidth } } assign(const, const_fields) assign(io.flit.bits.payload, body_fields) when (io.flit.fire && io.flit.bits.head) { is_const := false.B; const_reg := io.flit.bits.payload } when (io.flit.fire && io.flit.bits.tail) { is_const := true.B } } trait HasAddressDecoder { // Filter a list to only those elements selected def filter[T](data: Seq[T], mask: Seq[Boolean]) = (data zip mask).filter(_._2).map(_._1) val edgeIn: TLEdge val edgesOut: Seq[TLEdge] lazy val reacheableIO = edgesOut.map { mp => edgeIn.client.clients.exists { c => mp.manager.managers.exists { m => c.visibility.exists { ca => m.address.exists { ma => ca.overlaps(ma) }} }} }.toVector lazy val releaseIO = (edgesOut zip reacheableIO).map { case (mp, reachable) => reachable && edgeIn.client.anySupportProbe && mp.manager.anySupportAcquireB }.toVector def outputPortFn(connectIO: Seq[Boolean]) = { val port_addrs = edgesOut.map(_.manager.managers.flatMap(_.address)) val routingMask = AddressDecoder(filter(port_addrs, connectIO)) val route_addrs = port_addrs.map(seq => AddressSet.unify(seq.map(_.widen(~routingMask)).distinct)) route_addrs.map(seq => (addr: UInt) => seq.map(_.contains(addr)).reduce(_||_)) } } class TLAToNoC( val edgeIn: TLEdge, val edgesOut: Seq[TLEdge], bundle: TLBundleParameters, slaveToAEgress: Int => Int, sourceStart: Int )(implicit p: Parameters) extends TLChannelToNoC(new TLBundleA(bundle), edgeIn, slaveToAEgress)(p) with HasAddressDecoder { has_body := edgeIn.hasData(protocol.bits) || (~protocol.bits.mask =/= 0.U) lazy val connectAIO = reacheableIO lazy val requestOH = outputPortFn(connectAIO).zipWithIndex.map { case (o, j) => connectAIO(j).B && (unique(connectAIO) || o(protocol.bits.address)) } q.io.enq <> io.protocol q.io.enq.bits.source := io.protocol.bits.source | sourceStart.U } class TLAFromNoC(edgeOut: TLEdge, bundle: TLBundleParameters)(implicit p: Parameters) extends TLChannelFromNoC(new TLBundleA(bundle))(p) { io.protocol <> protocol when (io.flit.bits.head) { io.protocol.bits.mask := ~(0.U(io.protocol.bits.mask.getWidth.W)) } } class TLBToNoC( edgeOut: TLEdge, edgesIn: Seq[TLEdge], bundle: TLBundleParameters, masterToBIngress: Int => Int )(implicit p: Parameters) extends TLChannelToNoC(new TLBundleB(bundle), edgeOut, masterToBIngress)(p) { has_body := edgeOut.hasData(protocol.bits) || (~protocol.bits.mask =/= 0.U) lazy val inputIdRanges = TLXbar.mapInputIds(edgesIn.map(_.client)) lazy val requestOH = inputIdRanges.map { i => i.contains(protocol.bits.source) } q.io.enq <> io.protocol } class TLBFromNoC(edgeIn: TLEdge, bundle: TLBundleParameters, sourceSize: Int)(implicit p: Parameters) extends TLChannelFromNoC(new TLBundleB(bundle))(p) { io.protocol <> protocol io.protocol.bits.source := trim(protocol.bits.source, sourceSize) when (io.flit.bits.head) { io.protocol.bits.mask := ~(0.U(io.protocol.bits.mask.getWidth.W)) } } class TLCToNoC( val edgeIn: TLEdge, val edgesOut: Seq[TLEdge], bundle: TLBundleParameters, slaveToCEgress: Int => Int, sourceStart: Int )(implicit p: Parameters) extends TLChannelToNoC(new TLBundleC(bundle), edgeIn, slaveToCEgress)(p) with HasAddressDecoder { has_body := edgeIn.hasData(protocol.bits) lazy val connectCIO = releaseIO lazy val requestOH = outputPortFn(connectCIO).zipWithIndex.map { case (o, j) => connectCIO(j).B && (unique(connectCIO) || o(protocol.bits.address)) } q.io.enq <> io.protocol q.io.enq.bits.source := io.protocol.bits.source | sourceStart.U } class TLCFromNoC(edgeOut: TLEdge, bundle: TLBundleParameters)(implicit p: Parameters) extends TLChannelFromNoC(new TLBundleC(bundle))(p) { io.protocol <> protocol } class TLDToNoC( edgeOut: TLEdge, edgesIn: Seq[TLEdge], bundle: TLBundleParameters, masterToDIngress: Int => Int, sourceStart: Int )(implicit p: Parameters) extends TLChannelToNoC(new TLBundleD(bundle), edgeOut, masterToDIngress)(p) { has_body := edgeOut.hasData(protocol.bits) lazy val inputIdRanges = TLXbar.mapInputIds(edgesIn.map(_.client)) lazy val requestOH = inputIdRanges.map { i => i.contains(protocol.bits.source) } q.io.enq <> io.protocol q.io.enq.bits.sink := io.protocol.bits.sink | sourceStart.U } class TLDFromNoC(edgeIn: TLEdge, bundle: TLBundleParameters, sourceSize: Int)(implicit p: Parameters) extends TLChannelFromNoC(new TLBundleD(bundle))(p) { io.protocol <> protocol io.protocol.bits.source := trim(protocol.bits.source, sourceSize) } class TLEToNoC( val edgeIn: TLEdge, val edgesOut: Seq[TLEdge], bundle: TLBundleParameters, slaveToEEgress: Int => Int )(implicit p: Parameters) extends TLChannelToNoC(new TLBundleE(bundle), edgeIn, slaveToEEgress)(p) { has_body := edgeIn.hasData(protocol.bits) lazy val outputIdRanges = TLXbar.mapOutputIds(edgesOut.map(_.manager)) lazy val requestOH = outputIdRanges.map { o => o.contains(protocol.bits.sink) } q.io.enq <> io.protocol } class TLEFromNoC(edgeOut: TLEdge, bundle: TLBundleParameters, sourceSize: Int)(implicit p: Parameters) extends TLChannelFromNoC(new TLBundleE(bundle))(p) { io.protocol <> protocol io.protocol.bits.sink := trim(protocol.bits.sink, sourceSize) } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) || !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.ProbeAckData || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode | small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U || beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }

module TLCToNoC_5( // @[TilelinkAdapters.scala:151:7] input clock, // @[TilelinkAdapters.scala:151:7] input reset, // @[TilelinkAdapters.scala:151:7] output io_protocol_ready, // @[TilelinkAdapters.scala:19:14] input io_protocol_valid, // @[TilelinkAdapters.scala:19:14] input [2:0] io_protocol_bits_opcode, // @[TilelinkAdapters.scala:19:14] input [2:0] io_protocol_bits_param, // @[TilelinkAdapters.scala:19:14] input [3:0] io_protocol_bits_size, // @[TilelinkAdapters.scala:19:14] input [6:0] io_protocol_bits_source, // @[TilelinkAdapters.scala:19:14] input [31:0] io_protocol_bits_address, // @[TilelinkAdapters.scala:19:14] input [127:0] io_protocol_bits_data, // @[TilelinkAdapters.scala:19:14] input io_protocol_bits_corrupt, // @[TilelinkAdapters.scala:19:14] input io_flit_ready, // @[TilelinkAdapters.scala:19:14] output io_flit_valid, // @[TilelinkAdapters.scala:19:14] output io_flit_bits_head, // @[TilelinkAdapters.scala:19:14] output io_flit_bits_tail, // @[TilelinkAdapters.scala:19:14] output [128:0] io_flit_bits_payload, // @[TilelinkAdapters.scala:19:14] output [4:0] io_flit_bits_egress_id // @[TilelinkAdapters.scala:19:14] ); wire _q_io_deq_valid; // @[TilelinkAdapters.scala:26:17] wire [2:0] _q_io_deq_bits_opcode; // @[TilelinkAdapters.scala:26:17] wire [2:0] _q_io_deq_bits_param; // @[TilelinkAdapters.scala:26:17] wire [3:0] _q_io_deq_bits_size; // @[TilelinkAdapters.scala:26:17] wire [6:0] _q_io_deq_bits_source; // @[TilelinkAdapters.scala:26:17] wire [31:0] _q_io_deq_bits_address; // @[TilelinkAdapters.scala:26:17] wire [127:0] _q_io_deq_bits_data; // @[TilelinkAdapters.scala:26:17] wire _q_io_deq_bits_corrupt; // @[TilelinkAdapters.scala:26:17] wire [26:0] _tail_beats1_decode_T = 27'hFFF << _q_io_deq_bits_size; // @[package.scala:243:71] reg [7:0] head_counter; // @[Edges.scala:229:27] wire head = head_counter == 8'h0; // @[Edges.scala:229:27, :231:25] wire [7:0] tail_beats1 = _q_io_deq_bits_opcode[0] ? ~(_tail_beats1_decode_T[11:4]) : 8'h0; // @[package.scala:243:{46,71,76}] reg [7:0] tail_counter; // @[Edges.scala:229:27] reg is_body; // @[TilelinkAdapters.scala:39:24] wire q_io_deq_ready = io_flit_ready & (is_body | ~(_q_io_deq_bits_opcode[0])); // @[Edges.scala:102:36] wire io_flit_bits_head_0 = head & ~is_body; // @[Edges.scala:231:25] wire io_flit_bits_tail_0 = (tail_counter == 8'h1 | tail_beats1 == 8'h0) & (is_body | ~(_q_io_deq_bits_opcode[0])); // @[Edges.scala:102:36, :221:14, :229:27, :232:{25,33,43}] wire _GEN = io_flit_ready & _q_io_deq_valid; // @[Decoupled.scala:51:35] always @(posedge clock) begin // @[TilelinkAdapters.scala:151:7] if (reset) begin // @[TilelinkAdapters.scala:151:7] head_counter <= 8'h0; // @[Edges.scala:229:27] tail_counter <= 8'h0; // @[Edges.scala:229:27] is_body <= 1'h0; // @[TilelinkAdapters.scala:39:24, :151:7] end else begin // @[TilelinkAdapters.scala:151:7] if (q_io_deq_ready & _q_io_deq_valid) begin // @[Decoupled.scala:51:35] head_counter <= head ? (_q_io_deq_bits_opcode[0] ? ~(_tail_beats1_decode_T[11:4]) : 8'h0) : head_counter - 8'h1; // @[package.scala:243:{46,71,76}] tail_counter <= tail_counter == 8'h0 ? tail_beats1 : tail_counter - 8'h1; // @[Edges.scala:221:14, :229:27, :230:28, :231:25, :236:21] end is_body <= ~(_GEN & io_flit_bits_tail_0) & (_GEN & io_flit_bits_head_0 | is_body); // @[Decoupled.scala:51:35] end always @(posedge)

Generate the Verilog code corresponding to the following Chisel files. File DescribedSRAM.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3.{Data, SyncReadMem, Vec} import chisel3.util.log2Ceil object DescribedSRAM { def apply[T <: Data]( name: String, desc: String, size: BigInt, // depth data: T ): SyncReadMem[T] = { val mem = SyncReadMem(size, data) mem.suggestName(name) val granWidth = data match { case v: Vec[_] => v.head.getWidth case d => d.getWidth } val uid = 0 Annotated.srams( component = mem, name = name, address_width = log2Ceil(size), data_width = data.getWidth, depth = size, description = desc, write_mask_granularity = granWidth ) mem } }

module dataArrayB1Way_5( // @[DescribedSRAM.scala:17:26] input [7:0] RW0_addr, input RW0_en, input RW0_clk, input RW0_wmode, input [63:0] RW0_wdata, output [63:0] RW0_rdata ); dataArrayB0Way_0_ext dataArrayB0Way_0_ext ( // @[DescribedSRAM.scala:17:26] .RW0_addr (RW0_addr), .RW0_en (RW0_en), .RW0_clk (RW0_clk), .RW0_wmode (RW0_wmode), .RW0_wdata (RW0_wdata), .RW0_rdata (RW0_rdata) ); // @[DescribedSRAM.scala:17:26] endmodule

Generate the Verilog code corresponding to the following Chisel files. File ShiftReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ // Similar to the Chisel ShiftRegister but allows the user to suggest a // name to the registers that get instantiated, and // to provide a reset value. object ShiftRegInit { def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T = (0 until n).foldRight(in) { case (i, next) => { val r = RegNext(next, init) name.foreach { na => r.suggestName(s"${na}_${i}") } r } } } /** These wrap behavioral * shift registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * The different types vary in their reset behavior: * AsyncResetShiftReg -- Asynchronously reset register array * A W(width) x D(depth) sized array is constructed from D instantiations of a * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg, * but only used for timing applications */ abstract class AbstractPipelineReg(w: Int = 1) extends Module { val io = IO(new Bundle { val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) } ) } object AbstractPipelineReg { def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = { val chain = Module(gen) name.foreach{ chain.suggestName(_) } chain.io.d := in.asUInt chain.io.q.asTypeOf(in) } } class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) { require(depth > 0, "Depth must be greater than 0.") override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}" val chain = List.tabulate(depth) { i => Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}") } chain.last.io.d := io.d chain.last.io.en := true.B (chain.init zip chain.tail).foreach { case (sink, source) => sink.io.d := source.io.q sink.io.en := true.B } io.q := chain.head.io.q } object AsyncResetShiftReg { def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name) def apply [T <: Data](in: T, depth: Int, name: Option[String]): T = apply(in, depth, 0, name) def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T = apply(in, depth, init.litValue.toInt, name) def apply [T <: Data](in: T, depth: Int, init: T): T = apply (in, depth, init.litValue.toInt, None) } File AsyncQueue.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ case class AsyncQueueParams( depth: Int = 8, sync: Int = 3, safe: Boolean = true, // If safe is true, then effort is made to resynchronize the crossing indices when either side is reset. // This makes it safe/possible to reset one side of the crossing (but not the other) when the queue is empty. narrow: Boolean = false) // If narrow is true then the read mux is moved to the source side of the crossing. // This reduces the number of level shifters in the case where the clock crossing is also a voltage crossing, // at the expense of a combinational path from the sink to the source and back to the sink. { require (depth > 0 && isPow2(depth)) require (sync >= 2) val bits = log2Ceil(depth) val wires = if (narrow) 1 else depth } object AsyncQueueParams { // When there is only one entry, we don't need narrow. def singleton(sync: Int = 3, safe: Boolean = true) = AsyncQueueParams(1, sync, safe, false) } class AsyncBundleSafety extends Bundle { val ridx_valid = Input (Bool()) val widx_valid = Output(Bool()) val source_reset_n = Output(Bool()) val sink_reset_n = Input (Bool()) } class AsyncBundle[T <: Data](private val gen: T, val params: AsyncQueueParams = AsyncQueueParams()) extends Bundle { // Data-path synchronization val mem = Output(Vec(params.wires, gen)) val ridx = Input (UInt((params.bits+1).W)) val widx = Output(UInt((params.bits+1).W)) val index = params.narrow.option(Input(UInt(params.bits.W))) // Signals used to self-stabilize a safe AsyncQueue val safe = params.safe.option(new AsyncBundleSafety) } object GrayCounter { def apply(bits: Int, increment: Bool = true.B, clear: Bool = false.B, name: String = "binary"): UInt = { val incremented = Wire(UInt(bits.W)) val binary = RegNext(next=incremented, init=0.U).suggestName(name) incremented := Mux(clear, 0.U, binary + increment.asUInt) incremented ^ (incremented >> 1) } } class AsyncValidSync(sync: Int, desc: String) extends RawModule { val io = IO(new Bundle { val in = Input(Bool()) val out = Output(Bool()) }) val clock = IO(Input(Clock())) val reset = IO(Input(AsyncReset())) withClockAndReset(clock, reset){ io.out := AsyncResetSynchronizerShiftReg(io.in, sync, Some(desc)) } } class AsyncQueueSource[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module { override def desiredName = s"AsyncQueueSource_${gen.typeName}" val io = IO(new Bundle { // These come from the source domain val enq = Flipped(Decoupled(gen)) // These cross to the sink clock domain val async = new AsyncBundle(gen, params) }) val bits = params.bits val sink_ready = WireInit(true.B) val mem = Reg(Vec(params.depth, gen)) // This does NOT need to be reset at all. val widx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.enq.fire, !sink_ready, "widx_bin")) val ridx = AsyncResetSynchronizerShiftReg(io.async.ridx, params.sync, Some("ridx_gray")) val ready = sink_ready && widx =/= (ridx ^ (params.depth | params.depth >> 1).U) val index = if (bits == 0) 0.U else io.async.widx(bits-1, 0) ^ (io.async.widx(bits, bits) << (bits-1)) when (io.enq.fire) { mem(index) := io.enq.bits } val ready_reg = withReset(reset.asAsyncReset)(RegNext(next=ready, init=false.B).suggestName("ready_reg")) io.enq.ready := ready_reg && sink_ready val widx_reg = withReset(reset.asAsyncReset)(RegNext(next=widx, init=0.U).suggestName("widx_gray")) io.async.widx := widx_reg io.async.index match { case Some(index) => io.async.mem(0) := mem(index) case None => io.async.mem := mem } io.async.safe.foreach { sio => val source_valid_0 = Module(new AsyncValidSync(params.sync, "source_valid_0")) val source_valid_1 = Module(new AsyncValidSync(params.sync, "source_valid_1")) val sink_extend = Module(new AsyncValidSync(params.sync, "sink_extend")) val sink_valid = Module(new AsyncValidSync(params.sync, "sink_valid")) source_valid_0.reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset source_valid_1.reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset sink_extend .reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset sink_valid .reset := reset.asAsyncReset source_valid_0.clock := clock source_valid_1.clock := clock sink_extend .clock := clock sink_valid .clock := clock source_valid_0.io.in := true.B source_valid_1.io.in := source_valid_0.io.out sio.widx_valid := source_valid_1.io.out sink_extend.io.in := sio.ridx_valid sink_valid.io.in := sink_extend.io.out sink_ready := sink_valid.io.out sio.source_reset_n := !reset.asBool // Assert that if there is stuff in the queue, then reset cannot happen // Impossible to write because dequeue can occur on the receiving side, // then reset allowed to happen, but write side cannot know that dequeue // occurred. // TODO: write some sort of sanity check assertion for users // that denote don't reset when there is activity // assert (!(reset || !sio.sink_reset_n) || !io.enq.valid, "Enqueue while sink is reset and AsyncQueueSource is unprotected") // assert (!reset_rise || prev_idx_match.asBool, "Sink reset while AsyncQueueSource not empty") } } class AsyncQueueSink[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module { override def desiredName = s"AsyncQueueSink_${gen.typeName}" val io = IO(new Bundle { // These come from the sink domain val deq = Decoupled(gen) // These cross to the source clock domain val async = Flipped(new AsyncBundle(gen, params)) }) val bits = params.bits val source_ready = WireInit(true.B) val ridx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.deq.fire, !source_ready, "ridx_bin")) val widx = AsyncResetSynchronizerShiftReg(io.async.widx, params.sync, Some("widx_gray")) val valid = source_ready && ridx =/= widx // The mux is safe because timing analysis ensures ridx has reached the register // On an ASIC, changes to the unread location cannot affect the selected value // On an FPGA, only one input changes at a time => mem updates don't cause glitches // The register only latches when the selected valued is not being written val index = if (bits == 0) 0.U else ridx(bits-1, 0) ^ (ridx(bits, bits) << (bits-1)) io.async.index.foreach { _ := index } // This register does not NEED to be reset, as its contents will not // be considered unless the asynchronously reset deq valid register is set. // It is possible that bits latches when the source domain is reset / has power cut // This is safe, because isolation gates brought mem low before the zeroed widx reached us val deq_bits_nxt = io.async.mem(if (params.narrow) 0.U else index) io.deq.bits := ClockCrossingReg(deq_bits_nxt, en = valid, doInit = false, name = Some("deq_bits_reg")) val valid_reg = withReset(reset.asAsyncReset)(RegNext(next=valid, init=false.B).suggestName("valid_reg")) io.deq.valid := valid_reg && source_ready val ridx_reg = withReset(reset.asAsyncReset)(RegNext(next=ridx, init=0.U).suggestName("ridx_gray")) io.async.ridx := ridx_reg io.async.safe.foreach { sio => val sink_valid_0 = Module(new AsyncValidSync(params.sync, "sink_valid_0")) val sink_valid_1 = Module(new AsyncValidSync(params.sync, "sink_valid_1")) val source_extend = Module(new AsyncValidSync(params.sync, "source_extend")) val source_valid = Module(new AsyncValidSync(params.sync, "source_valid")) sink_valid_0 .reset := (reset.asBool || !sio.source_reset_n).asAsyncReset sink_valid_1 .reset := (reset.asBool || !sio.source_reset_n).asAsyncReset source_extend.reset := (reset.asBool || !sio.source_reset_n).asAsyncReset source_valid .reset := reset.asAsyncReset sink_valid_0 .clock := clock sink_valid_1 .clock := clock source_extend.clock := clock source_valid .clock := clock sink_valid_0.io.in := true.B sink_valid_1.io.in := sink_valid_0.io.out sio.ridx_valid := sink_valid_1.io.out source_extend.io.in := sio.widx_valid source_valid.io.in := source_extend.io.out source_ready := source_valid.io.out sio.sink_reset_n := !reset.asBool // TODO: write some sort of sanity check assertion for users // that denote don't reset when there is activity // // val reset_and_extend = !source_ready || !sio.source_reset_n || reset.asBool // val reset_and_extend_prev = RegNext(reset_and_extend, true.B) // val reset_rise = !reset_and_extend_prev && reset_and_extend // val prev_idx_match = AsyncResetReg(updateData=(io.async.widx===io.async.ridx), resetData=0) // assert (!reset_rise || prev_idx_match.asBool, "Source reset while AsyncQueueSink not empty") } } object FromAsyncBundle { // Sometimes it makes sense for the sink to have different sync than the source def apply[T <: Data](x: AsyncBundle[T]): DecoupledIO[T] = apply(x, x.params.sync) def apply[T <: Data](x: AsyncBundle[T], sync: Int): DecoupledIO[T] = { val sink = Module(new AsyncQueueSink(chiselTypeOf(x.mem(0)), x.params.copy(sync = sync))) sink.io.async <> x sink.io.deq } } object ToAsyncBundle { def apply[T <: Data](x: ReadyValidIO[T], params: AsyncQueueParams = AsyncQueueParams()): AsyncBundle[T] = { val source = Module(new AsyncQueueSource(chiselTypeOf(x.bits), params)) source.io.enq <> x source.io.async } } class AsyncQueue[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Crossing[T] { val io = IO(new CrossingIO(gen)) val source = withClockAndReset(io.enq_clock, io.enq_reset) { Module(new AsyncQueueSource(gen, params)) } val sink = withClockAndReset(io.deq_clock, io.deq_reset) { Module(new AsyncQueueSink (gen, params)) } source.io.enq <> io.enq io.deq <> sink.io.deq sink.io.async <> source.io.async }

module AsyncValidSync_32( // @[AsyncQueue.scala:58:7] output io_out, // @[AsyncQueue.scala:59:14] input clock, // @[AsyncQueue.scala:63:17] input reset // @[AsyncQueue.scala:64:17] ); wire io_in = 1'h1; // @[ShiftReg.scala:45:23] wire _io_out_WIRE; // @[ShiftReg.scala:48:24] wire io_out_0; // @[AsyncQueue.scala:58:7] assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24] AsyncResetSynchronizerShiftReg_w1_d3_i0_42 io_out_source_valid_0 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (reset), .io_q (_io_out_WIRE) ); // @[ShiftReg.scala:45:23] assign io_out = io_out_0; // @[AsyncQueue.scala:58:7] endmodule

Generate the Verilog code corresponding to the following Chisel files. File WidthWidget.scala: package constellation.channel import chisel3._ import chisel3.util._ import freechips.rocketchip.diplomacy._ import org.chipsalliance.cde.config.{Parameters} import freechips.rocketchip.util._ object WidthWidget { def split[T <: BaseFlit](in: IrrevocableIO[T], out: IrrevocableIO[T]) = { val inBits = in.bits.payload.getWidth val outBits = out.bits.payload.getWidth require(inBits > outBits && inBits % outBits == 0) val ratio = inBits / outBits val count = RegInit(0.U(log2Ceil(ratio).W)) val first = count === 0.U val last = count === (ratio - 1).U val stored = Reg(UInt((inBits - outBits).W)) out.valid := in.valid out.bits := in.bits out.bits.head := in.bits.head && first out.bits.tail := in.bits.tail && last out.bits.payload := Mux(first, in.bits.payload, stored) in.ready := last && out.ready when (out.fire) { count := Mux(last, 0.U, count + 1.U) stored := Mux(first, in.bits.payload, stored) >> outBits } } def merge[T <: BaseFlit](in: IrrevocableIO[T], out: IrrevocableIO[T]) = { val inBits = in.bits.payload.getWidth val outBits = out.bits.payload.getWidth require(outBits > inBits && outBits % inBits == 0) val ratio = outBits / inBits val count = RegInit(0.U(log2Ceil(ratio).W)) val first = count === 0.U val last = count === (ratio - 1).U val flit = Reg(out.bits.cloneType) val payload = Reg(Vec(ratio-1, UInt(inBits.W))) out.valid := in.valid && last out.bits := flit out.bits.tail := last && in.bits.tail out.bits.payload := Cat(in.bits.payload, payload.asUInt) in.ready := !last || out.ready when (in.fire) { count := Mux(last, 0.U, count + 1.U) payload(count) := in.bits.payload when (first) { flit := in.bits } } } def apply[T <: BaseFlit](in: IrrevocableIO[T], out: IrrevocableIO[T]) = { val inBits = in.bits.payload.getWidth val outBits = out.bits.payload.getWidth if (inBits == outBits) { out <> in } else if (inBits < outBits) { merge(in, out) } else { split(in, out) } } } class IngressWidthWidget(srcBits: Int)(implicit p: Parameters) extends LazyModule { val node = new IngressChannelAdapterNode( slaveFn = { s => s.copy(payloadBits=srcBits) } ) lazy val module = new LazyModuleImp(this) { (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => WidthWidget(in.flit, out.flit) } } } object IngressWidthWidget { def apply(destBits: Int, srcBits: Int)(implicit p: Parameters) = { if (destBits == srcBits) { val node = IngressChannelEphemeralNode() node } else { val ingress_width_widget = LazyModule(new IngressWidthWidget(srcBits)) ingress_width_widget.node } } } class EgressWidthWidget(srcBits: Int)(implicit p: Parameters) extends LazyModule { val node = new EgressChannelAdapterNode( slaveFn = { s => s.copy(payloadBits=srcBits) } ) lazy val module = new LazyModuleImp(this) { (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => WidthWidget(in.flit, out.flit) } } } object EgressWidthWidget { def apply(destBits: Int, srcBits: Int)(implicit p: Parameters) = { if (destBits == srcBits) { val node = EgressChannelEphemeralNode() node } else { val egress_width_widget = LazyModule(new EgressWidthWidget(srcBits)) egress_width_widget.node } } } class ChannelWidthWidget(srcBits: Int)(implicit p: Parameters) extends LazyModule { val node = new ChannelAdapterNode( slaveFn = { s => val destBits = s.payloadBits if (srcBits > destBits) { val ratio = srcBits / destBits val virtualChannelParams = s.virtualChannelParams.map { vP => require(vP.bufferSize >= ratio) vP.copy(bufferSize = vP.bufferSize / ratio) } s.copy(payloadBits=srcBits, virtualChannelParams=virtualChannelParams) } else { val ratio = destBits / srcBits val virtualChannelParams = s.virtualChannelParams.map { vP => vP.copy(bufferSize = vP.bufferSize * ratio) } s.copy(payloadBits=srcBits, virtualChannelParams=virtualChannelParams) } } ) lazy val module = new LazyModuleImp(this) { (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => val destBits = out.cParam.payloadBits in.vc_free := out.vc_free if (srcBits == destBits) { in.credit_return := out.credit_return out.flit <> in.flit } else if (srcBits > destBits) { require(srcBits % destBits == 0, s"$srcBits, $destBits") (in.flit zip out.flit) foreach { case (iF, oF) => val in_q = Module(new Queue(new Flit(in.cParam.payloadBits), in.cParam.virtualChannelParams.map(_.bufferSize).sum, pipe=true, flow=true)) in_q.io.enq.valid := iF.valid in_q.io.enq.bits := iF.bits assert(!(in_q.io.enq.valid && !in_q.io.enq.ready)) val in_flit = Wire(Irrevocable(new Flit(in.cParam.payloadBits))) in_flit.valid := in_q.io.deq.valid in_flit.bits := in_q.io.deq.bits in_q.io.deq.ready := in_flit.ready val out_flit = Wire(Irrevocable(new Flit(out.cParam.payloadBits))) oF.valid := out_flit.valid oF.bits := out_flit.bits out_flit.ready := true.B WidthWidget(in_flit, out_flit) } val ratio = srcBits / destBits val counts = RegInit(VecInit(Seq.fill(in.nVirtualChannels) { 0.U(log2Ceil(ratio).W) })) val in_credit_return = Wire(Vec(in.nVirtualChannels, Bool())) in.credit_return := in_credit_return.asUInt for (i <- 0 until in.nVirtualChannels) { in_credit_return(i) := false.B when (out.credit_return(i)) { val last = counts(i) === (ratio-1).U counts(i) := Mux(last, 0.U, counts(i) + 1.U) when (last) { in_credit_return(i) := true.B } } } } else { require(destBits % srcBits == 0) val in_flits = Wire(Vec(in.nVirtualChannels, Irrevocable(new Flit(in.cParam.payloadBits)))) val out_flits = Wire(Vec(in.nVirtualChannels, Irrevocable(new Flit(out.cParam.payloadBits)))) for (i <- 0 until in.nVirtualChannels) { val sel = in.flit.map(f => f.valid && f.bits.virt_channel_id === i.U) in_flits(i).valid := sel.orR in_flits(i).bits := Mux1H(sel, in.flit.map(_.bits)) out_flits(i).ready := sel.orR WidthWidget(in_flits(i), out_flits(i)) } for (i <- 0 until in.flit.size) { val sel = UIntToOH(in.flit(i).bits.virt_channel_id) out.flit(i).valid := Mux1H(sel, out_flits.map(_.valid)) out.flit(i).bits := Mux1H(sel, out_flits.map(_.bits)) } val ratio = destBits / srcBits val credits = RegInit(VecInit((0 until in.nVirtualChannels).map { i => 0.U(log2Ceil(ratio*in.cParam.virtualChannelParams(i).bufferSize).W) })) val in_credit_return = Wire(Vec(in.nVirtualChannels, Bool())) in.credit_return := in_credit_return.asUInt for (i <- 0 until in.nVirtualChannels) { when (out.credit_return(i)) { in_credit_return(i) := true.B credits(i) := credits(i) + (ratio - 1).U } .otherwise { val empty = credits(i) === 0.U in_credit_return(i) := !empty credits(i) := Mux(empty, 0.U, credits(i) - 1.U) } } } } } } object ChannelWidthWidget { def apply(destBits: Int, srcBits: Int)(implicit p: Parameters) = { if (destBits == srcBits) { val node = ChannelEphemeralNode() node } else { val channel_width_widget = LazyModule(new ChannelWidthWidget(srcBits)) channel_width_widget.node } } } File LazyModuleImp.scala: package org.chipsalliance.diplomacy.lazymodule import chisel3.{withClockAndReset, Module, RawModule, Reset, _} import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo} import firrtl.passes.InlineAnnotation import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.nodes.Dangle import scala.collection.immutable.SortedMap /** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]]. * * This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy. */ sealed trait LazyModuleImpLike extends RawModule { /** [[LazyModule]] that contains this instance. */ val wrapper: LazyModule /** IOs that will be automatically "punched" for this instance. */ val auto: AutoBundle /** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */ protected[diplomacy] val dangles: Seq[Dangle] // [[wrapper.module]] had better not be accessed while LazyModules are still being built! require( LazyModule.scope.isEmpty, s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}" ) /** Set module name. Defaults to the containing LazyModule's desiredName. */ override def desiredName: String = wrapper.desiredName suggestName(wrapper.suggestedName) /** [[Parameters]] for chisel [[Module]]s. */ implicit val p: Parameters = wrapper.p /** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and * submodules. */ protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = { // 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]], // 2. return [[Dangle]]s from each module. val childDangles = wrapper.children.reverse.flatMap { c => implicit val sourceInfo: SourceInfo = c.info c.cloneProto.map { cp => // If the child is a clone, then recursively set cloneProto of its children as well def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = { require(bases.size == clones.size) (bases.zip(clones)).map { case (l, r) => require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}") l.cloneProto = Some(r) assignCloneProtos(l.children, r.children) } } assignCloneProtos(c.children, cp.children) // Clone the child module as a record, and get its [[AutoBundle]] val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName) val clonedAuto = clone("auto").asInstanceOf[AutoBundle] // Get the empty [[Dangle]]'s of the cloned child val rawDangles = c.cloneDangles() require(rawDangles.size == clonedAuto.elements.size) // Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) } dangles }.getOrElse { // For non-clones, instantiate the child module val mod = try { Module(c.module) } catch { case e: ChiselException => { println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}") throw e } } mod.dangles } } // Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]]. // This will result in a sequence of [[Dangle]] from these [[BaseNode]]s. val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate()) // Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]] val allDangles = nodeDangles ++ childDangles // Group [[allDangles]] by their [[source]]. val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*) // For each [[source]] set of [[Dangle]]s of size 2, ensure that these // can be connected as a source-sink pair (have opposite flipped value). // Make the connection and mark them as [[done]]. val done = Set() ++ pairing.values.filter(_.size == 2).map { case Seq(a, b) => require(a.flipped != b.flipped) // @todo <> in chisel3 makes directionless connection. if (a.flipped) { a.data <> b.data } else { b.data <> a.data } a.source case _ => None } // Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module. val forward = allDangles.filter(d => !done(d.source)) // Generate [[AutoBundle]] IO from [[forward]]. val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*)) // Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]] val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) => if (d.flipped) { d.data <> io } else { io <> d.data } d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name) } // Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]]. wrapper.inModuleBody.reverse.foreach { _() } if (wrapper.shouldBeInlined) { chisel3.experimental.annotate(new ChiselAnnotation { def toFirrtl = InlineAnnotation(toNamed) }) } // Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]]. (auto, dangles) } } /** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike { /** Instantiate hardware of this `Module`. */ val (auto, dangles) = instantiate() } /** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike { // These wires are the default clock+reset for all LazyModule children. // It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the // [[LazyRawModuleImp]] children. // Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly. /** drive clock explicitly. */ val childClock: Clock = Wire(Clock()) /** drive reset explicitly. */ val childReset: Reset = Wire(Reset()) // the default is that these are disabled childClock := false.B.asClock childReset := chisel3.DontCare def provideImplicitClockToLazyChildren: Boolean = false val (auto, dangles) = if (provideImplicitClockToLazyChildren) { withClockAndReset(childClock, childReset) { instantiate() } } else { instantiate() } }

module EgressWidthWidget( // @[WidthWidget.scala:98:25] input clock, // @[WidthWidget.scala:98:25] input reset, // @[WidthWidget.scala:98:25] output auto_in_flit_ready, // @[LazyModuleImp.scala:107:25] input auto_in_flit_valid, // @[LazyModuleImp.scala:107:25] input auto_in_flit_bits_head, // @[LazyModuleImp.scala:107:25] input auto_in_flit_bits_tail, // @[LazyModuleImp.scala:107:25] input [36:0] auto_in_flit_bits_payload, // @[LazyModuleImp.scala:107:25] input auto_out_flit_ready, // @[LazyModuleImp.scala:107:25] output auto_out_flit_valid, // @[LazyModuleImp.scala:107:25] output auto_out_flit_bits_head, // @[LazyModuleImp.scala:107:25] output auto_out_flit_bits_tail, // @[LazyModuleImp.scala:107:25] output [73:0] auto_out_flit_bits_payload // @[LazyModuleImp.scala:107:25] ); reg last; // @[WidthWidget.scala:37:24] reg flit_head; // @[WidthWidget.scala:40:19] reg [36:0] payload_0; // @[WidthWidget.scala:41:22] wire nodeIn_flit_ready = ~last | auto_out_flit_ready; // @[WidthWidget.scala:37:24, :47:{17,23}] wire _GEN = nodeIn_flit_ready & auto_in_flit_valid; // @[Decoupled.scala:51:35] always @(posedge clock) begin // @[WidthWidget.scala:98:25] if (reset) // @[WidthWidget.scala:98:25] last <= 1'h0; // @[WidthWidget.scala:37:24] else if (_GEN) // @[Decoupled.scala:51:35] last <= ~last & last - 1'h1; // @[WidthWidget.scala:37:24, :49:{19,37}] if (_GEN & ~last) // @[Decoupled.scala:51:35] flit_head <= auto_in_flit_bits_head; // @[WidthWidget.scala:40:19] if (_GEN) // @[Decoupled.scala:51:35] payload_0 <= auto_in_flit_bits_payload; // @[WidthWidget.scala:41:22] always @(posedge)

Generate the Verilog code corresponding to the following Chisel files. File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /** Like Vec.apply(idx), but tolerates indices of mismatched width */ def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /** Any Data subtype that has a Bool member named valid. */ type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /** converts from camel case to to underscores, also removing all spaces */ def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /** converts spaces or underscores to hyphens, also lowering case */ def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y | (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y || y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /** Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation */ def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Nodes.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.nodes._ import freechips.rocketchip.util.{AsyncQueueParams,RationalDirection} case object TLMonitorBuilder extends Field[TLMonitorArgs => TLMonitorBase](args => new TLMonitor(args)) object TLImp extends NodeImp[TLMasterPortParameters, TLSlavePortParameters, TLEdgeOut, TLEdgeIn, TLBundle] { def edgeO(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeOut(pd, pu, p, sourceInfo) def edgeI(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeIn (pd, pu, p, sourceInfo) def bundleO(eo: TLEdgeOut) = TLBundle(eo.bundle) def bundleI(ei: TLEdgeIn) = TLBundle(ei.bundle) def render(ei: TLEdgeIn) = RenderedEdge(colour = "#000000" /* black */, label = (ei.manager.beatBytes * 8).toString) override def monitor(bundle: TLBundle, edge: TLEdgeIn): Unit = { val monitor = Module(edge.params(TLMonitorBuilder)(TLMonitorArgs(edge))) monitor.io.in := bundle } override def mixO(pd: TLMasterPortParameters, node: OutwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLMasterPortParameters = pd.v1copy(clients = pd.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }) override def mixI(pu: TLSlavePortParameters, node: InwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLSlavePortParameters = pu.v1copy(managers = pu.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }) } trait TLFormatNode extends FormatNode[TLEdgeIn, TLEdgeOut] case class TLClientNode(portParams: Seq[TLMasterPortParameters])(implicit valName: ValName) extends SourceNode(TLImp)(portParams) with TLFormatNode case class TLManagerNode(portParams: Seq[TLSlavePortParameters])(implicit valName: ValName) extends SinkNode(TLImp)(portParams) with TLFormatNode case class TLAdapterNode( clientFn: TLMasterPortParameters => TLMasterPortParameters = { s => s }, managerFn: TLSlavePortParameters => TLSlavePortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLImp)(clientFn, managerFn) with TLFormatNode case class TLJunctionNode( clientFn: Seq[TLMasterPortParameters] => Seq[TLMasterPortParameters], managerFn: Seq[TLSlavePortParameters] => Seq[TLSlavePortParameters])( implicit valName: ValName) extends JunctionNode(TLImp)(clientFn, managerFn) with TLFormatNode case class TLIdentityNode()(implicit valName: ValName) extends IdentityNode(TLImp)() with TLFormatNode object TLNameNode { def apply(name: ValName) = TLIdentityNode()(name) def apply(name: Option[String]): TLIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLIdentityNode = apply(Some(name)) } case class TLEphemeralNode()(implicit valName: ValName) extends EphemeralNode(TLImp)() object TLTempNode { def apply(): TLEphemeralNode = TLEphemeralNode()(ValName("temp")) } case class TLNexusNode( clientFn: Seq[TLMasterPortParameters] => TLMasterPortParameters, managerFn: Seq[TLSlavePortParameters] => TLSlavePortParameters)( implicit valName: ValName) extends NexusNode(TLImp)(clientFn, managerFn) with TLFormatNode abstract class TLCustomNode(implicit valName: ValName) extends CustomNode(TLImp) with TLFormatNode // Asynchronous crossings trait TLAsyncFormatNode extends FormatNode[TLAsyncEdgeParameters, TLAsyncEdgeParameters] object TLAsyncImp extends SimpleNodeImp[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncEdgeParameters, TLAsyncBundle] { def edge(pd: TLAsyncClientPortParameters, pu: TLAsyncManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLAsyncEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLAsyncEdgeParameters) = new TLAsyncBundle(e.bundle) def render(e: TLAsyncEdgeParameters) = RenderedEdge(colour = "#ff0000" /* red */, label = e.manager.async.depth.toString) override def mixO(pd: TLAsyncClientPortParameters, node: OutwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLAsyncManagerPortParameters, node: InwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLAsyncAdapterNode( clientFn: TLAsyncClientPortParameters => TLAsyncClientPortParameters = { s => s }, managerFn: TLAsyncManagerPortParameters => TLAsyncManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLAsyncImp)(clientFn, managerFn) with TLAsyncFormatNode case class TLAsyncIdentityNode()(implicit valName: ValName) extends IdentityNode(TLAsyncImp)() with TLAsyncFormatNode object TLAsyncNameNode { def apply(name: ValName) = TLAsyncIdentityNode()(name) def apply(name: Option[String]): TLAsyncIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLAsyncIdentityNode = apply(Some(name)) } case class TLAsyncSourceNode(sync: Option[Int])(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLAsyncImp)( dFn = { p => TLAsyncClientPortParameters(p) }, uFn = { p => p.base.v1copy(minLatency = p.base.minLatency + sync.getOrElse(p.async.sync)) }) with FormatNode[TLEdgeIn, TLAsyncEdgeParameters] // discard cycles in other clock domain case class TLAsyncSinkNode(async: AsyncQueueParams)(implicit valName: ValName) extends MixedAdapterNode(TLAsyncImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = p.base.minLatency + async.sync) }, uFn = { p => TLAsyncManagerPortParameters(async, p) }) with FormatNode[TLAsyncEdgeParameters, TLEdgeOut] // Rationally related crossings trait TLRationalFormatNode extends FormatNode[TLRationalEdgeParameters, TLRationalEdgeParameters] object TLRationalImp extends SimpleNodeImp[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalEdgeParameters, TLRationalBundle] { def edge(pd: TLRationalClientPortParameters, pu: TLRationalManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLRationalEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLRationalEdgeParameters) = new TLRationalBundle(e.bundle) def render(e: TLRationalEdgeParameters) = RenderedEdge(colour = "#00ff00" /* green */) override def mixO(pd: TLRationalClientPortParameters, node: OutwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLRationalManagerPortParameters, node: InwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLRationalAdapterNode( clientFn: TLRationalClientPortParameters => TLRationalClientPortParameters = { s => s }, managerFn: TLRationalManagerPortParameters => TLRationalManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLRationalImp)(clientFn, managerFn) with TLRationalFormatNode case class TLRationalIdentityNode()(implicit valName: ValName) extends IdentityNode(TLRationalImp)() with TLRationalFormatNode object TLRationalNameNode { def apply(name: ValName) = TLRationalIdentityNode()(name) def apply(name: Option[String]): TLRationalIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLRationalIdentityNode = apply(Some(name)) } case class TLRationalSourceNode()(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLRationalImp)( dFn = { p => TLRationalClientPortParameters(p) }, uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLRationalEdgeParameters] // discard cycles from other clock domain case class TLRationalSinkNode(direction: RationalDirection)(implicit valName: ValName) extends MixedAdapterNode(TLRationalImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = 1) }, uFn = { p => TLRationalManagerPortParameters(direction, p) }) with FormatNode[TLRationalEdgeParameters, TLEdgeOut] // Credited version of TileLink channels trait TLCreditedFormatNode extends FormatNode[TLCreditedEdgeParameters, TLCreditedEdgeParameters] object TLCreditedImp extends SimpleNodeImp[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedEdgeParameters, TLCreditedBundle] { def edge(pd: TLCreditedClientPortParameters, pu: TLCreditedManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLCreditedEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLCreditedEdgeParameters) = new TLCreditedBundle(e.bundle) def render(e: TLCreditedEdgeParameters) = RenderedEdge(colour = "#ffff00" /* yellow */, e.delay.toString) override def mixO(pd: TLCreditedClientPortParameters, node: OutwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLCreditedManagerPortParameters, node: InwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLCreditedAdapterNode( clientFn: TLCreditedClientPortParameters => TLCreditedClientPortParameters = { s => s }, managerFn: TLCreditedManagerPortParameters => TLCreditedManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLCreditedImp)(clientFn, managerFn) with TLCreditedFormatNode case class TLCreditedIdentityNode()(implicit valName: ValName) extends IdentityNode(TLCreditedImp)() with TLCreditedFormatNode object TLCreditedNameNode { def apply(name: ValName) = TLCreditedIdentityNode()(name) def apply(name: Option[String]): TLCreditedIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLCreditedIdentityNode = apply(Some(name)) } case class TLCreditedSourceNode(delay: TLCreditedDelay)(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLCreditedImp)( dFn = { p => TLCreditedClientPortParameters(delay, p) }, uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLCreditedEdgeParameters] // discard cycles from other clock domain case class TLCreditedSinkNode(delay: TLCreditedDelay)(implicit valName: ValName) extends MixedAdapterNode(TLCreditedImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = 1) }, uFn = { p => TLCreditedManagerPortParameters(delay, p) }) with FormatNode[TLCreditedEdgeParameters, TLEdgeOut] File Bundles.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import freechips.rocketchip.util._ import scala.collection.immutable.ListMap import chisel3.util.Decoupled import chisel3.util.DecoupledIO import chisel3.reflect.DataMirror abstract class TLBundleBase(val params: TLBundleParameters) extends Bundle // common combos in lazy policy: // Put + Acquire // Release + AccessAck object TLMessages { // A B C D E def PutFullData = 0.U // . . => AccessAck def PutPartialData = 1.U // . . => AccessAck def ArithmeticData = 2.U // . . => AccessAckData def LogicalData = 3.U // . . => AccessAckData def Get = 4.U // . . => AccessAckData def Hint = 5.U // . . => HintAck def AcquireBlock = 6.U // . => Grant[Data] def AcquirePerm = 7.U // . => Grant[Data] def Probe = 6.U // . => ProbeAck[Data] def AccessAck = 0.U // . . def AccessAckData = 1.U // . . def HintAck = 2.U // . . def ProbeAck = 4.U // . def ProbeAckData = 5.U // . def Release = 6.U // . => ReleaseAck def ReleaseData = 7.U // . => ReleaseAck def Grant = 4.U // . => GrantAck def GrantData = 5.U // . => GrantAck def ReleaseAck = 6.U // . def GrantAck = 0.U // . def isA(x: UInt) = x <= AcquirePerm def isB(x: UInt) = x <= Probe def isC(x: UInt) = x <= ReleaseData def isD(x: UInt) = x <= ReleaseAck def adResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, Grant, Grant) def bcResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, ProbeAck, ProbeAck) def a = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("AcquireBlock",TLPermissions.PermMsgGrow), ("AcquirePerm",TLPermissions.PermMsgGrow)) def b = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("Probe",TLPermissions.PermMsgCap)) def c = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("ProbeAck",TLPermissions.PermMsgReport), ("ProbeAckData",TLPermissions.PermMsgReport), ("Release",TLPermissions.PermMsgReport), ("ReleaseData",TLPermissions.PermMsgReport)) def d = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("Grant",TLPermissions.PermMsgCap), ("GrantData",TLPermissions.PermMsgCap), ("ReleaseAck",TLPermissions.PermMsgReserved)) } /** * The three primary TileLink permissions are: * (T)runk: the agent is (or is on inwards path to) the global point of serialization. * (B)ranch: the agent is on an outwards path to * (N)one: * These permissions are permuted by transfer operations in various ways. * Operations can cap permissions, request for them to be grown or shrunk, * or for a report on their current status. */ object TLPermissions { val aWidth = 2 val bdWidth = 2 val cWidth = 3 // Cap types (Grant = new permissions, Probe = permisions <= target) def toT = 0.U(bdWidth.W) def toB = 1.U(bdWidth.W) def toN = 2.U(bdWidth.W) def isCap(x: UInt) = x <= toN // Grow types (Acquire = permissions >= target) def NtoB = 0.U(aWidth.W) def NtoT = 1.U(aWidth.W) def BtoT = 2.U(aWidth.W) def isGrow(x: UInt) = x <= BtoT // Shrink types (ProbeAck, Release) def TtoB = 0.U(cWidth.W) def TtoN = 1.U(cWidth.W) def BtoN = 2.U(cWidth.W) def isShrink(x: UInt) = x <= BtoN // Report types (ProbeAck, Release) def TtoT = 3.U(cWidth.W) def BtoB = 4.U(cWidth.W) def NtoN = 5.U(cWidth.W) def isReport(x: UInt) = x <= NtoN def PermMsgGrow:Seq[String] = Seq("Grow NtoB", "Grow NtoT", "Grow BtoT") def PermMsgCap:Seq[String] = Seq("Cap toT", "Cap toB", "Cap toN") def PermMsgReport:Seq[String] = Seq("Shrink TtoB", "Shrink TtoN", "Shrink BtoN", "Report TotT", "Report BtoB", "Report NtoN") def PermMsgReserved:Seq[String] = Seq("Reserved") } object TLAtomics { val width = 3 // Arithmetic types def MIN = 0.U(width.W) def MAX = 1.U(width.W) def MINU = 2.U(width.W) def MAXU = 3.U(width.W) def ADD = 4.U(width.W) def isArithmetic(x: UInt) = x <= ADD // Logical types def XOR = 0.U(width.W) def OR = 1.U(width.W) def AND = 2.U(width.W) def SWAP = 3.U(width.W) def isLogical(x: UInt) = x <= SWAP def ArithMsg:Seq[String] = Seq("MIN", "MAX", "MINU", "MAXU", "ADD") def LogicMsg:Seq[String] = Seq("XOR", "OR", "AND", "SWAP") } object TLHints { val width = 1 def PREFETCH_READ = 0.U(width.W) def PREFETCH_WRITE = 1.U(width.W) def isHints(x: UInt) = x <= PREFETCH_WRITE def HintsMsg:Seq[String] = Seq("PrefetchRead", "PrefetchWrite") } sealed trait TLChannel extends TLBundleBase { val channelName: String } sealed trait TLDataChannel extends TLChannel sealed trait TLAddrChannel extends TLDataChannel final class TLBundleA(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleA_${params.shortName}" val channelName = "'A' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(List(TLAtomics.width, TLPermissions.aWidth, TLHints.width).max.W) // amo_opcode || grow perms || hint val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleB(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleB_${params.shortName}" val channelName = "'B' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val address = UInt(params.addressBits.W) // from // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleC(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleC_${params.shortName}" val channelName = "'C' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.cWidth.W) // shrink or report perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleD(params: TLBundleParameters) extends TLBundleBase(params) with TLDataChannel { override def typeName = s"TLBundleD_${params.shortName}" val channelName = "'D' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val sink = UInt(params.sinkBits.W) // from val denied = Bool() // implies corrupt iff *Data val user = BundleMap(params.responseFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleE(params: TLBundleParameters) extends TLBundleBase(params) with TLChannel { override def typeName = s"TLBundleE_${params.shortName}" val channelName = "'E' channel" val sink = UInt(params.sinkBits.W) // to } class TLBundle(val params: TLBundleParameters) extends Record { // Emulate a Bundle with elements abcde or ad depending on params.hasBCE private val optA = Some (Decoupled(new TLBundleA(params))) private val optB = params.hasBCE.option(Flipped(Decoupled(new TLBundleB(params)))) private val optC = params.hasBCE.option(Decoupled(new TLBundleC(params))) private val optD = Some (Flipped(Decoupled(new TLBundleD(params)))) private val optE = params.hasBCE.option(Decoupled(new TLBundleE(params))) def a: DecoupledIO[TLBundleA] = optA.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleA(params))))) def b: DecoupledIO[TLBundleB] = optB.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleB(params))))) def c: DecoupledIO[TLBundleC] = optC.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleC(params))))) def d: DecoupledIO[TLBundleD] = optD.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleD(params))))) def e: DecoupledIO[TLBundleE] = optE.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleE(params))))) val elements = if (params.hasBCE) ListMap("e" -> e, "d" -> d, "c" -> c, "b" -> b, "a" -> a) else ListMap("d" -> d, "a" -> a) def tieoff(): Unit = { DataMirror.specifiedDirectionOf(a.ready) match { case SpecifiedDirection.Input => a.ready := false.B c.ready := false.B e.ready := false.B b.valid := false.B d.valid := false.B case SpecifiedDirection.Output => a.valid := false.B c.valid := false.B e.valid := false.B b.ready := false.B d.ready := false.B case _ => } } } object TLBundle { def apply(params: TLBundleParameters) = new TLBundle(params) } class TLAsyncBundleBase(val params: TLAsyncBundleParameters) extends Bundle class TLAsyncBundle(params: TLAsyncBundleParameters) extends TLAsyncBundleBase(params) { val a = new AsyncBundle(new TLBundleA(params.base), params.async) val b = Flipped(new AsyncBundle(new TLBundleB(params.base), params.async)) val c = new AsyncBundle(new TLBundleC(params.base), params.async) val d = Flipped(new AsyncBundle(new TLBundleD(params.base), params.async)) val e = new AsyncBundle(new TLBundleE(params.base), params.async) } class TLRationalBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = RationalIO(new TLBundleA(params)) val b = Flipped(RationalIO(new TLBundleB(params))) val c = RationalIO(new TLBundleC(params)) val d = Flipped(RationalIO(new TLBundleD(params))) val e = RationalIO(new TLBundleE(params)) } class TLCreditedBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = CreditedIO(new TLBundleA(params)) val b = Flipped(CreditedIO(new TLBundleB(params))) val c = CreditedIO(new TLBundleC(params)) val d = Flipped(CreditedIO(new TLBundleD(params))) val e = CreditedIO(new TLBundleE(params)) } File LazyModuleImp.scala: package org.chipsalliance.diplomacy.lazymodule import chisel3.{withClockAndReset, Module, RawModule, Reset, _} import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo} import firrtl.passes.InlineAnnotation import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.nodes.Dangle import scala.collection.immutable.SortedMap /** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]]. * * This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy. */ sealed trait LazyModuleImpLike extends RawModule { /** [[LazyModule]] that contains this instance. */ val wrapper: LazyModule /** IOs that will be automatically "punched" for this instance. */ val auto: AutoBundle /** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */ protected[diplomacy] val dangles: Seq[Dangle] // [[wrapper.module]] had better not be accessed while LazyModules are still being built! require( LazyModule.scope.isEmpty, s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}" ) /** Set module name. Defaults to the containing LazyModule's desiredName. */ override def desiredName: String = wrapper.desiredName suggestName(wrapper.suggestedName) /** [[Parameters]] for chisel [[Module]]s. */ implicit val p: Parameters = wrapper.p /** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and * submodules. */ protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = { // 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]], // 2. return [[Dangle]]s from each module. val childDangles = wrapper.children.reverse.flatMap { c => implicit val sourceInfo: SourceInfo = c.info c.cloneProto.map { cp => // If the child is a clone, then recursively set cloneProto of its children as well def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = { require(bases.size == clones.size) (bases.zip(clones)).map { case (l, r) => require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}") l.cloneProto = Some(r) assignCloneProtos(l.children, r.children) } } assignCloneProtos(c.children, cp.children) // Clone the child module as a record, and get its [[AutoBundle]] val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName) val clonedAuto = clone("auto").asInstanceOf[AutoBundle] // Get the empty [[Dangle]]'s of the cloned child val rawDangles = c.cloneDangles() require(rawDangles.size == clonedAuto.elements.size) // Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) } dangles }.getOrElse { // For non-clones, instantiate the child module val mod = try { Module(c.module) } catch { case e: ChiselException => { println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}") throw e } } mod.dangles } } // Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]]. // This will result in a sequence of [[Dangle]] from these [[BaseNode]]s. val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate()) // Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]] val allDangles = nodeDangles ++ childDangles // Group [[allDangles]] by their [[source]]. val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*) // For each [[source]] set of [[Dangle]]s of size 2, ensure that these // can be connected as a source-sink pair (have opposite flipped value). // Make the connection and mark them as [[done]]. val done = Set() ++ pairing.values.filter(_.size == 2).map { case Seq(a, b) => require(a.flipped != b.flipped) // @todo <> in chisel3 makes directionless connection. if (a.flipped) { a.data <> b.data } else { b.data <> a.data } a.source case _ => None } // Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module. val forward = allDangles.filter(d => !done(d.source)) // Generate [[AutoBundle]] IO from [[forward]]. val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*)) // Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]] val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) => if (d.flipped) { d.data <> io } else { io <> d.data } d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name) } // Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]]. wrapper.inModuleBody.reverse.foreach { _() } if (wrapper.shouldBeInlined) { chisel3.experimental.annotate(new ChiselAnnotation { def toFirrtl = InlineAnnotation(toNamed) }) } // Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]]. (auto, dangles) } } /** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike { /** Instantiate hardware of this `Module`. */ val (auto, dangles) = instantiate() } /** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike { // These wires are the default clock+reset for all LazyModule children. // It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the // [[LazyRawModuleImp]] children. // Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly. /** drive clock explicitly. */ val childClock: Clock = Wire(Clock()) /** drive reset explicitly. */ val childReset: Reset = Wire(Reset()) // the default is that these are disabled childClock := false.B.asClock childReset := chisel3.DontCare def provideImplicitClockToLazyChildren: Boolean = false val (auto, dangles) = if (provideImplicitClockToLazyChildren) { withClockAndReset(childClock, childReset) { instantiate() } } else { instantiate() } } File TLSerdes.scala: package testchipip.serdes import chisel3._ import chisel3.util._ import freechips.rocketchip.diplomacy._ import org.chipsalliance.cde.config._ import freechips.rocketchip.util._ import freechips.rocketchip.tilelink._ object TLSerdesser { // This should be the standard bundle type for TLSerdesser val STANDARD_TLBUNDLE_PARAMS = TLBundleParameters( addressBits=64, dataBits=64, sourceBits=8, sinkBits=8, sizeBits=8, echoFields=Nil, requestFields=Nil, responseFields=Nil, hasBCE=true) } class SerdesDebugIO extends Bundle { val ser_busy = Output(Bool()) val des_busy = Output(Bool()) } class TLSerdesser( val flitWidth: Int, clientPortParams: Option[TLMasterPortParameters], managerPortParams: Option[TLSlavePortParameters], val bundleParams: TLBundleParameters = TLSerdesser.STANDARD_TLBUNDLE_PARAMS, nameSuffix: Option[String] = None ) (implicit p: Parameters) extends LazyModule { require (clientPortParams.isDefined || managerPortParams.isDefined) val clientNode = clientPortParams.map { c => TLClientNode(Seq(c)) } val managerNode = managerPortParams.map { m => TLManagerNode(Seq(m)) } override lazy val desiredName = (Seq("TLSerdesser") ++ nameSuffix).mkString("_") lazy val module = new Impl class Impl extends LazyModuleImp(this) { val io = IO(new Bundle { val ser = Vec(5, new DecoupledFlitIO(flitWidth)) val debug = new SerdesDebugIO }) val client_tl = clientNode.map(_.out(0)._1).getOrElse(0.U.asTypeOf(new TLBundle(bundleParams))) val client_edge = clientNode.map(_.out(0)._2) val manager_tl = managerNode.map(_.in(0)._1).getOrElse(0.U.asTypeOf(new TLBundle(bundleParams))) val manager_edge = managerNode.map(_.in(0)._2) val clientParams = client_edge.map(_.bundle).getOrElse(bundleParams) val managerParams = manager_edge.map(_.bundle).getOrElse(bundleParams) val mergedParams = clientParams.union(managerParams).union(bundleParams) require(mergedParams.echoFields.isEmpty, "TLSerdesser does not support TileLink with echo fields") require(mergedParams.requestFields.isEmpty, "TLSerdesser does not support TileLink with request fields") require(mergedParams.responseFields.isEmpty, "TLSerdesser does not support TileLink with response fields") require(mergedParams == bundleParams, s"TLSerdesser is misconfigured, the combined inwards/outwards parameters cannot be serialized using the provided bundle params\n$mergedParams > $bundleParams") val out_channels = Seq( (manager_tl.e, manager_edge.map(e => Module(new TLEToBeat(e, mergedParams, nameSuffix)))), (client_tl.d, client_edge.map (e => Module(new TLDToBeat(e, mergedParams, nameSuffix)))), (manager_tl.c, manager_edge.map(e => Module(new TLCToBeat(e, mergedParams, nameSuffix)))), (client_tl.b, client_edge.map (e => Module(new TLBToBeat(e, mergedParams, nameSuffix)))), (manager_tl.a, manager_edge.map(e => Module(new TLAToBeat(e, mergedParams, nameSuffix)))) ) io.ser.map(_.out.valid := false.B) io.ser.map(_.out.bits := DontCare) val out_sers = out_channels.zipWithIndex.map { case ((c,b),i) => b.map { b => b.io.protocol <> c val ser = Module(new GenericSerializer(b.io.beat.bits.cloneType, flitWidth)).suggestName(s"ser_$i") ser.io.in <> b.io.beat io.ser(i).out <> ser.io.out ser }}.flatten io.debug.ser_busy := out_sers.map(_.io.busy).orR val in_channels = Seq( (client_tl.e, Module(new TLEFromBeat(mergedParams, nameSuffix))), (manager_tl.d, Module(new TLDFromBeat(mergedParams, nameSuffix))), (client_tl.c, Module(new TLCFromBeat(mergedParams, nameSuffix))), (manager_tl.b, Module(new TLBFromBeat(mergedParams, nameSuffix))), (client_tl.a, Module(new TLAFromBeat(mergedParams, nameSuffix))) ) val in_desers = in_channels.zipWithIndex.map { case ((c,b),i) => c <> b.io.protocol val des = Module(new GenericDeserializer(b.io.beat.bits.cloneType, flitWidth)).suggestName(s"des_$i") des.io.in <> io.ser(i).in b.io.beat <> des.io.out des } io.debug.des_busy := in_desers.map(_.io.busy).orR } } File MixedNode.scala: package org.chipsalliance.diplomacy.nodes import chisel3.{Data, DontCare, Wire} import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.{Field, Parameters} import org.chipsalliance.diplomacy.ValName import org.chipsalliance.diplomacy.sourceLine /** One side metadata of a [[Dangle]]. * * Describes one side of an edge going into or out of a [[BaseNode]]. * * @param serial * the global [[BaseNode.serial]] number of the [[BaseNode]] that this [[HalfEdge]] connects to. * @param index * the `index` in the [[BaseNode]]'s input or output port list that this [[HalfEdge]] belongs to. */ case class HalfEdge(serial: Int, index: Int) extends Ordered[HalfEdge] { import scala.math.Ordered.orderingToOrdered def compare(that: HalfEdge): Int = HalfEdge.unapply(this).compare(HalfEdge.unapply(that)) } /** [[Dangle]] captures the `IO` information of a [[LazyModule]] and which two [[BaseNode]]s the [[Edges]]/[[Bundle]] * connects. * * [[Dangle]]s are generated by [[BaseNode.instantiate]] using [[MixedNode.danglesOut]] and [[MixedNode.danglesIn]] , * [[LazyModuleImp.instantiate]] connects those that go to internal or explicit IO connections in a [[LazyModule]]. * * @param source * the source [[HalfEdge]] of this [[Dangle]], which captures the source [[BaseNode]] and the port `index` within * that [[BaseNode]]. * @param sink * sink [[HalfEdge]] of this [[Dangle]], which captures the sink [[BaseNode]] and the port `index` within that * [[BaseNode]]. * @param flipped * flip or not in [[AutoBundle.makeElements]]. If true this corresponds to `danglesOut`, if false it corresponds to * `danglesIn`. * @param dataOpt * actual [[Data]] for the hardware connection. Can be empty if this belongs to a cloned module */ case class Dangle(source: HalfEdge, sink: HalfEdge, flipped: Boolean, name: String, dataOpt: Option[Data]) { def data = dataOpt.get } /** [[Edges]] is a collection of parameters describing the functionality and connection for an interface, which is often * derived from the interconnection protocol and can inform the parameterization of the hardware bundles that actually * implement the protocol. */ case class Edges[EI, EO](in: Seq[EI], out: Seq[EO]) /** A field available in [[Parameters]] used to determine whether [[InwardNodeImp.monitor]] will be called. */ case object MonitorsEnabled extends Field[Boolean](true) /** When rendering the edge in a graphical format, flip the order in which the edges' source and sink are presented. * * For example, when rendering graphML, yEd by default tries to put the source node vertically above the sink node, but * [[RenderFlipped]] inverts this relationship. When a particular [[LazyModule]] contains both source nodes and sink * nodes, flipping the rendering of one node's edge will usual produce a more concise visual layout for the * [[LazyModule]]. */ case object RenderFlipped extends Field[Boolean](false) /** The sealed node class in the package, all node are derived from it. * * @param inner * Sink interface implementation. * @param outer * Source interface implementation. * @param valName * val name of this node. * @tparam DI * Downward-flowing parameters received on the inner side of the node. It is usually a brunch of parameters * describing the protocol parameters from a source. For an [[InwardNode]], it is determined by the connected * [[OutwardNode]]. Since it can be connected to multiple sources, this parameter is always a Seq of source port * parameters. * @tparam UI * Upward-flowing parameters generated by the inner side of the node. It is usually a brunch of parameters describing * the protocol parameters of a sink. For an [[InwardNode]], it is determined itself. * @tparam EI * Edge Parameters describing a connection on the inner side of the node. It is usually a brunch of transfers * specified for a sink according to protocol. * @tparam BI * Bundle type used when connecting to the inner side of the node. It is a hardware interface of this sink interface. * It should extends from [[chisel3.Data]], which represents the real hardware. * @tparam DO * Downward-flowing parameters generated on the outer side of the node. It is usually a brunch of parameters * describing the protocol parameters of a source. For an [[OutwardNode]], it is determined itself. * @tparam UO * Upward-flowing parameters received by the outer side of the node. It is usually a brunch of parameters describing * the protocol parameters from a sink. For an [[OutwardNode]], it is determined by the connected [[InwardNode]]. * Since it can be connected to multiple sinks, this parameter is always a Seq of sink port parameters. * @tparam EO * Edge Parameters describing a connection on the outer side of the node. It is usually a brunch of transfers * specified for a source according to protocol. * @tparam BO * Bundle type used when connecting to the outer side of the node. It is a hardware interface of this source * interface. It should extends from [[chisel3.Data]], which represents the real hardware. * * @note * Call Graph of [[MixedNode]] * - line `─`: source is process by a function and generate pass to others * - Arrow `→`: target of arrow is generated by source * * {{{ * (from the other node) * ┌─────────────────────────────────────────────────────────[[InwardNode.uiParams]]─────────────┐ * ↓ │ * (binding node when elaboration) [[OutwardNode.uoParams]]────────────────────────[[MixedNode.mapParamsU]]→──────────┐ │ * [[InwardNode.accPI]] │ │ │ * │ │ (based on protocol) │ * │ │ [[MixedNode.inner.edgeI]] │ * │ │ ↓ │ * ↓ │ │ │ * (immobilize after elaboration) (inward port from [[OutwardNode]]) │ ↓ │ * [[InwardNode.iBindings]]──┐ [[MixedNode.iDirectPorts]]────────────────────→[[MixedNode.iPorts]] [[InwardNode.uiParams]] │ * │ │ ↑ │ │ │ * │ │ │ [[OutwardNode.doParams]] │ │ * │ │ │ (from the other node) │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * │ │ │ └────────┬──────────────┤ │ * │ │ │ │ │ │ * │ │ │ │ (based on protocol) │ * │ │ │ │ [[MixedNode.inner.edgeI]] │ * │ │ │ │ │ │ * │ │ (from the other node) │ ↓ │ * │ └───[[OutwardNode.oPortMapping]] [[OutwardNode.oStar]] │ [[MixedNode.edgesIn]]───┐ │ * │ ↑ ↑ │ │ ↓ │ * │ │ │ │ │ [[MixedNode.in]] │ * │ │ │ │ ↓ ↑ │ * │ (solve star connection) │ │ │ [[MixedNode.bundleIn]]──┘ │ * ├───[[MixedNode.resolveStar]]→─┼─────────────────────────────┤ └────────────────────────────────────┐ │ * │ │ │ [[MixedNode.bundleOut]]─┐ │ │ * │ │ │ ↑ ↓ │ │ * │ │ │ │ [[MixedNode.out]] │ │ * │ ↓ ↓ │ ↑ │ │ * │ ┌─────[[InwardNode.iPortMapping]] [[InwardNode.iStar]] [[MixedNode.edgesOut]]──┘ │ │ * │ │ (from the other node) ↑ │ │ * │ │ │ │ │ │ * │ │ │ [[MixedNode.outer.edgeO]] │ │ * │ │ │ (based on protocol) │ │ * │ │ │ │ │ │ * │ │ │ ┌────────────────────────────────────────┤ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * (immobilize after elaboration)│ ↓ │ │ │ │ * [[OutwardNode.oBindings]]─┘ [[MixedNode.oDirectPorts]]───→[[MixedNode.oPorts]] [[OutwardNode.doParams]] │ │ * ↑ (inward port from [[OutwardNode]]) │ │ │ │ * │ ┌─────────────────────────────────────────┤ │ │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * [[OutwardNode.accPO]] │ ↓ │ │ │ * (binding node when elaboration) │ [[InwardNode.diParams]]─────→[[MixedNode.mapParamsD]]────────────────────────────┘ │ │ * │ ↑ │ │ * │ └──────────────────────────────────────────────────────────────────────────────────────────┘ │ * └──────────────────────────────────────────────────────────────────────────────────────────────────────────┘ * }}} */ abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data]( val inner: InwardNodeImp[DI, UI, EI, BI], val outer: OutwardNodeImp[DO, UO, EO, BO] )( implicit valName: ValName) extends BaseNode with NodeHandle[DI, UI, EI, BI, DO, UO, EO, BO] with InwardNode[DI, UI, BI] with OutwardNode[DO, UO, BO] { // Generate a [[NodeHandle]] with inward and outward node are both this node. val inward = this val outward = this /** Debug info of nodes binding. */ def bindingInfo: String = s"""$iBindingInfo |$oBindingInfo |""".stripMargin /** Debug info of ports connecting. */ def connectedPortsInfo: String = s"""${oPorts.size} outward ports connected: [${oPorts.map(_._2.name).mkString(",")}] |${iPorts.size} inward ports connected: [${iPorts.map(_._2.name).mkString(",")}] |""".stripMargin /** Debug info of parameters propagations. */ def parametersInfo: String = s"""${doParams.size} downstream outward parameters: [${doParams.mkString(",")}] |${uoParams.size} upstream outward parameters: [${uoParams.mkString(",")}] |${diParams.size} downstream inward parameters: [${diParams.mkString(",")}] |${uiParams.size} upstream inward parameters: [${uiParams.mkString(",")}] |""".stripMargin /** For a given node, converts [[OutwardNode.accPO]] and [[InwardNode.accPI]] to [[MixedNode.oPortMapping]] and * [[MixedNode.iPortMapping]]. * * Given counts of known inward and outward binding and inward and outward star bindings, return the resolved inward * stars and outward stars. * * This method will also validate the arguments and throw a runtime error if the values are unsuitable for this type * of node. * * @param iKnown * Number of known-size ([[BIND_ONCE]]) input bindings. * @param oKnown * Number of known-size ([[BIND_ONCE]]) output bindings. * @param iStar * Number of unknown size ([[BIND_STAR]]) input bindings. * @param oStar * Number of unknown size ([[BIND_STAR]]) output bindings. * @return * A Tuple of the resolved number of input and output connections. */ protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStar: Int, oStar: Int): (Int, Int) /** Function to generate downward-flowing outward params from the downward-flowing input params and the current output * ports. * * @param n * The size of the output sequence to generate. * @param p * Sequence of downward-flowing input parameters of this node. * @return * A `n`-sized sequence of downward-flowing output edge parameters. */ protected[diplomacy] def mapParamsD(n: Int, p: Seq[DI]): Seq[DO] /** Function to generate upward-flowing input parameters from the upward-flowing output parameters [[uiParams]]. * * @param n * Size of the output sequence. * @param p * Upward-flowing output edge parameters. * @return * A n-sized sequence of upward-flowing input edge parameters. */ protected[diplomacy] def mapParamsU(n: Int, p: Seq[UO]): Seq[UI] /** @return * The sink cardinality of the node, the number of outputs bound with [[BIND_QUERY]] summed with inputs bound with * [[BIND_STAR]]. */ protected[diplomacy] lazy val sinkCard: Int = oBindings.count(_._3 == BIND_QUERY) + iBindings.count(_._3 == BIND_STAR) /** @return * The source cardinality of this node, the number of inputs bound with [[BIND_QUERY]] summed with the number of * output bindings bound with [[BIND_STAR]]. */ protected[diplomacy] lazy val sourceCard: Int = iBindings.count(_._3 == BIND_QUERY) + oBindings.count(_._3 == BIND_STAR) /** @return list of nodes involved in flex bindings with this node. */ protected[diplomacy] lazy val flexes: Seq[BaseNode] = oBindings.filter(_._3 == BIND_FLEX).map(_._2) ++ iBindings.filter(_._3 == BIND_FLEX).map(_._2) /** Resolves the flex to be either source or sink and returns the offset where the [[BIND_STAR]] operators begin * greedily taking up the remaining connections. * * @return * A value >= 0 if it is sink cardinality, a negative value for source cardinality. The magnitude of the return * value is not relevant. */ protected[diplomacy] lazy val flexOffset: Int = { /** Recursively performs a depth-first search of the [[flexes]], [[BaseNode]]s connected to this node with flex * operators. The algorithm bottoms out when we either get to a node we have already visited or when we get to a * connection that is not a flex and can set the direction for us. Otherwise, recurse by visiting the `flexes` of * each node in the current set and decide whether they should be added to the set or not. * * @return * the mapping of [[BaseNode]] indexed by their serial numbers. */ def DFS(v: BaseNode, visited: Map[Int, BaseNode]): Map[Int, BaseNode] = { if (visited.contains(v.serial) || !v.flexibleArityDirection) { visited } else { v.flexes.foldLeft(visited + (v.serial -> v))((sum, n) => DFS(n, sum)) } } /** Determine which [[BaseNode]] are involved in resolving the flex connections to/from this node. * * @example * {{{ * a :*=* b :*=* c * d :*=* b * e :*=* f * }}} * * `flexSet` for `a`, `b`, `c`, or `d` will be `Set(a, b, c, d)` `flexSet` for `e` or `f` will be `Set(e,f)` */ val flexSet = DFS(this, Map()).values /** The total number of :*= operators where we're on the left. */ val allSink = flexSet.map(_.sinkCard).sum /** The total number of :=* operators used when we're on the right. */ val allSource = flexSet.map(_.sourceCard).sum require( allSink == 0 || allSource == 0, s"The nodes ${flexSet.map(_.name)} which are inter-connected by :*=* have ${allSink} :*= operators and ${allSource} :=* operators connected to them, making it impossible to determine cardinality inference direction." ) allSink - allSource } /** @return A value >= 0 if it is sink cardinality, a negative value for source cardinality. */ protected[diplomacy] def edgeArityDirection(n: BaseNode): Int = { if (flexibleArityDirection) flexOffset else if (n.flexibleArityDirection) n.flexOffset else 0 } /** For a node which is connected between two nodes, select the one that will influence the direction of the flex * resolution. */ protected[diplomacy] def edgeAritySelect(n: BaseNode, l: => Int, r: => Int): Int = { val dir = edgeArityDirection(n) if (dir < 0) l else if (dir > 0) r else 1 } /** Ensure that the same node is not visited twice in resolving `:*=`, etc operators. */ private var starCycleGuard = false /** Resolve all the star operators into concrete indicies. As connections are being made, some may be "star" * connections which need to be resolved. In some way to determine how many actual edges they correspond to. We also * need to build up the ranges of edges which correspond to each binding operator, so that We can apply the correct * edge parameters and later build up correct bundle connections. * * [[oPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that oPort (binding * operator). [[iPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that iPort * (binding operator). [[oStar]]: `Int` the value to return for this node `N` for any `N :*= foo` or `N :*=* foo :*= * bar` [[iStar]]: `Int` the value to return for this node `N` for any `foo :=* N` or `bar :=* foo :*=* N` */ protected[diplomacy] lazy val ( oPortMapping: Seq[(Int, Int)], iPortMapping: Seq[(Int, Int)], oStar: Int, iStar: Int ) = { try { if (starCycleGuard) throw StarCycleException() starCycleGuard = true // For a given node N... // Number of foo :=* N // + Number of bar :=* foo :*=* N val oStars = oBindings.count { case (_, n, b, _, _) => b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) < 0) } // Number of N :*= foo // + Number of N :*=* foo :*= bar val iStars = iBindings.count { case (_, n, b, _, _) => b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) > 0) } // 1 for foo := N // + bar.iStar for bar :*= foo :*=* N // + foo.iStar for foo :*= N // + 0 for foo :=* N val oKnown = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, 0, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => 0 } }.sum // 1 for N := foo // + bar.oStar for N :*=* foo :=* bar // + foo.oStar for N :=* foo // + 0 for N :*= foo val iKnown = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, 0) case BIND_QUERY => n.oStar case BIND_STAR => 0 } }.sum // Resolve star depends on the node subclass to implement the algorithm for this. val (iStar, oStar) = resolveStar(iKnown, oKnown, iStars, oStars) // Cumulative list of resolved outward binding range starting points val oSum = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, oStar, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => oStar } }.scanLeft(0)(_ + _) // Cumulative list of resolved inward binding range starting points val iSum = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, iStar) case BIND_QUERY => n.oStar case BIND_STAR => iStar } }.scanLeft(0)(_ + _) // Create ranges for each binding based on the running sums and return // those along with resolved values for the star operations. (oSum.init.zip(oSum.tail), iSum.init.zip(iSum.tail), oStar, iStar) } catch { case c: StarCycleException => throw c.copy(loop = context +: c.loop) } } /** Sequence of inward ports. * * This should be called after all star bindings are resolved. * * Each element is: `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. * `n` Instance of inward node. `p` View of [[Parameters]] where this connection was made. `s` Source info where this * connection was made in the source code. */ protected[diplomacy] lazy val oDirectPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oBindings.flatMap { case (i, n, _, p, s) => // for each binding operator in this node, look at what it connects to val (start, end) = n.iPortMapping(i) (start until end).map { j => (j, n, p, s) } } /** Sequence of outward ports. * * This should be called after all star bindings are resolved. * * `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. `n` Instance of * outward node. `p` View of [[Parameters]] where this connection was made. `s` [[SourceInfo]] where this connection * was made in the source code. */ protected[diplomacy] lazy val iDirectPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iBindings.flatMap { case (i, n, _, p, s) => // query this port index range of this node in the other side of node. val (start, end) = n.oPortMapping(i) (start until end).map { j => (j, n, p, s) } } // Ephemeral nodes ( which have non-None iForward/oForward) have in_degree = out_degree // Thus, there must exist an Eulerian path and the below algorithms terminate @scala.annotation.tailrec private def oTrace( tuple: (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) ): (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.iForward(i) match { case None => (i, n, p, s) case Some((j, m)) => oTrace((j, m, p, s)) } } @scala.annotation.tailrec private def iTrace( tuple: (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) ): (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.oForward(i) match { case None => (i, n, p, s) case Some((j, m)) => iTrace((j, m, p, s)) } } /** Final output ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - Numeric index of this binding in the [[InwardNode]] on the other end. * - [[InwardNode]] on the other end of this binding. * - A view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. */ lazy val oPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oDirectPorts.map(oTrace) /** Final input ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - numeric index of this binding in [[OutwardNode]] on the other end. * - [[OutwardNode]] on the other end of this binding. * - a view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. */ lazy val iPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iDirectPorts.map(iTrace) private var oParamsCycleGuard = false protected[diplomacy] lazy val diParams: Seq[DI] = iPorts.map { case (i, n, _, _) => n.doParams(i) } protected[diplomacy] lazy val doParams: Seq[DO] = { try { if (oParamsCycleGuard) throw DownwardCycleException() oParamsCycleGuard = true val o = mapParamsD(oPorts.size, diParams) require( o.size == oPorts.size, s"""Diplomacy has detected a problem with your graph: |At the following node, the number of outward ports should equal the number of produced outward parameters. |$context |$connectedPortsInfo |Downstreamed inward parameters: [${diParams.mkString(",")}] |Produced outward parameters: [${o.mkString(",")}] |""".stripMargin ) o.map(outer.mixO(_, this)) } catch { case c: DownwardCycleException => throw c.copy(loop = context +: c.loop) } } private var iParamsCycleGuard = false protected[diplomacy] lazy val uoParams: Seq[UO] = oPorts.map { case (o, n, _, _) => n.uiParams(o) } protected[diplomacy] lazy val uiParams: Seq[UI] = { try { if (iParamsCycleGuard) throw UpwardCycleException() iParamsCycleGuard = true val i = mapParamsU(iPorts.size, uoParams) require( i.size == iPorts.size, s"""Diplomacy has detected a problem with your graph: |At the following node, the number of inward ports should equal the number of produced inward parameters. |$context |$connectedPortsInfo |Upstreamed outward parameters: [${uoParams.mkString(",")}] |Produced inward parameters: [${i.mkString(",")}] |""".stripMargin ) i.map(inner.mixI(_, this)) } catch { case c: UpwardCycleException => throw c.copy(loop = context +: c.loop) } } /** Outward edge parameters. */ protected[diplomacy] lazy val edgesOut: Seq[EO] = (oPorts.zip(doParams)).map { case ((i, n, p, s), o) => outer.edgeO(o, n.uiParams(i), p, s) } /** Inward edge parameters. */ protected[diplomacy] lazy val edgesIn: Seq[EI] = (iPorts.zip(uiParams)).map { case ((o, n, p, s), i) => inner.edgeI(n.doParams(o), i, p, s) } /** A tuple of the input edge parameters and output edge parameters for the edges bound to this node. * * If you need to access to the edges of a foreign Node, use this method (in/out create bundles). */ lazy val edges: Edges[EI, EO] = Edges(edgesIn, edgesOut) /** Create actual Wires corresponding to the Bundles parameterized by the outward edges of this node. */ protected[diplomacy] lazy val bundleOut: Seq[BO] = edgesOut.map { e => val x = Wire(outer.bundleO(e)).suggestName(s"${valName.value}Out") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } /** Create actual Wires corresponding to the Bundles parameterized by the inward edges of this node. */ protected[diplomacy] lazy val bundleIn: Seq[BI] = edgesIn.map { e => val x = Wire(inner.bundleI(e)).suggestName(s"${valName.value}In") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } private def emptyDanglesOut: Seq[Dangle] = oPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(serial, i), sink = HalfEdge(n.serial, j), flipped = false, name = wirePrefix + "out", dataOpt = None ) } private def emptyDanglesIn: Seq[Dangle] = iPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(n.serial, j), sink = HalfEdge(serial, i), flipped = true, name = wirePrefix + "in", dataOpt = None ) } /** Create the [[Dangle]]s which describe the connections from this node output to other nodes inputs. */ protected[diplomacy] def danglesOut: Seq[Dangle] = emptyDanglesOut.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleOut(i))) } /** Create the [[Dangle]]s which describe the connections from this node input from other nodes outputs. */ protected[diplomacy] def danglesIn: Seq[Dangle] = emptyDanglesIn.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleIn(i))) } private[diplomacy] var instantiated = false /** Gather Bundle and edge parameters of outward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. */ def out: Seq[(BO, EO)] = { require( instantiated, s"$name.out should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleOut.zip(edgesOut) } /** Gather Bundle and edge parameters of inward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. */ def in: Seq[(BI, EI)] = { require( instantiated, s"$name.in should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleIn.zip(edgesIn) } /** Actually instantiate this node during [[LazyModuleImp]] evaluation. Mark that it's safe to use the Bundle wires, * instantiate monitors on all input ports if appropriate, and return all the dangles of this node. */ protected[diplomacy] def instantiate(): Seq[Dangle] = { instantiated = true if (!circuitIdentity) { (iPorts.zip(in)).foreach { case ((_, _, p, _), (b, e)) => if (p(MonitorsEnabled)) inner.monitor(b, e) } } danglesOut ++ danglesIn } protected[diplomacy] def cloneDangles(): Seq[Dangle] = emptyDanglesOut ++ emptyDanglesIn /** Connects the outward part of a node with the inward part of this node. */ protected[diplomacy] def bind( h: OutwardNode[DI, UI, BI], binding: NodeBinding )( implicit p: Parameters, sourceInfo: SourceInfo ): Unit = { val x = this // x := y val y = h sourceLine(sourceInfo, " at ", "") val i = x.iPushed val o = y.oPushed y.oPush( i, x, binding match { case BIND_ONCE => BIND_ONCE case BIND_FLEX => BIND_FLEX case BIND_STAR => BIND_QUERY case BIND_QUERY => BIND_STAR } ) x.iPush(o, y, binding) } /* Metadata for printing the node graph. */ def inputs: Seq[(OutwardNode[DI, UI, BI], RenderedEdge)] = (iPorts.zip(edgesIn)).map { case ((_, n, p, _), e) => val re = inner.render(e) (n, re.copy(flipped = re.flipped != p(RenderFlipped))) } /** Metadata for printing the node graph */ def outputs: Seq[(InwardNode[DO, UO, BO], RenderedEdge)] = oPorts.map { case (i, n, _, _) => (n, n.inputs(i)._2) } }

module TLSerdesser_SerialRAM( // @[TLSerdes.scala:39:9] input clock, // @[TLSerdes.scala:39:9] input reset, // @[TLSerdes.scala:39:9] output auto_manager_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_manager_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_manager_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_manager_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_manager_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input auto_manager_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_manager_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_manager_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_manager_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_manager_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_manager_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_manager_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_manager_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_manager_in_d_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_manager_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output auto_manager_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output [3:0] auto_manager_in_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_manager_in_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [63:0] auto_manager_in_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_manager_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] output io_ser_0_in_ready, // @[TLSerdes.scala:40:16] input io_ser_0_in_valid, // @[TLSerdes.scala:40:16] input [31:0] io_ser_0_in_bits_flit, // @[TLSerdes.scala:40:16] input io_ser_0_out_ready, // @[TLSerdes.scala:40:16] output [31:0] io_ser_0_out_bits_flit, // @[TLSerdes.scala:40:16] output io_ser_1_in_ready, // @[TLSerdes.scala:40:16] input io_ser_1_in_valid, // @[TLSerdes.scala:40:16] input [31:0] io_ser_1_in_bits_flit, // @[TLSerdes.scala:40:16] output io_ser_2_in_ready, // @[TLSerdes.scala:40:16] input io_ser_2_in_valid, // @[TLSerdes.scala:40:16] input [31:0] io_ser_2_in_bits_flit, // @[TLSerdes.scala:40:16] input io_ser_2_out_ready, // @[TLSerdes.scala:40:16] output io_ser_2_out_valid, // @[TLSerdes.scala:40:16] output [31:0] io_ser_2_out_bits_flit, // @[TLSerdes.scala:40:16] output io_ser_3_in_ready, // @[TLSerdes.scala:40:16] input io_ser_3_in_valid, // @[TLSerdes.scala:40:16] input [31:0] io_ser_3_in_bits_flit, // @[TLSerdes.scala:40:16] output io_ser_4_in_ready, // @[TLSerdes.scala:40:16] input io_ser_4_in_valid, // @[TLSerdes.scala:40:16] input [31:0] io_ser_4_in_bits_flit, // @[TLSerdes.scala:40:16] input io_ser_4_out_ready, // @[TLSerdes.scala:40:16] output io_ser_4_out_valid, // @[TLSerdes.scala:40:16] output [31:0] io_ser_4_out_bits_flit // @[TLSerdes.scala:40:16] ); wire _des_4_io_out_valid; // @[TLSerdes.scala:86:23] wire [85:0] _des_4_io_out_bits_payload; // @[TLSerdes.scala:86:23] wire _des_4_io_out_bits_head; // @[TLSerdes.scala:86:23] wire _des_4_io_out_bits_tail; // @[TLSerdes.scala:86:23] wire _des_4_io_busy; // @[TLSerdes.scala:86:23] wire _des_3_io_out_valid; // @[TLSerdes.scala:86:23] wire [84:0] _des_3_io_out_bits_payload; // @[TLSerdes.scala:86:23] wire _des_3_io_out_bits_head; // @[TLSerdes.scala:86:23] wire _des_3_io_out_bits_tail; // @[TLSerdes.scala:86:23] wire _des_3_io_busy; // @[TLSerdes.scala:86:23] wire _des_2_io_out_valid; // @[TLSerdes.scala:86:23] wire [85:0] _des_2_io_out_bits_payload; // @[TLSerdes.scala:86:23] wire _des_2_io_out_bits_head; // @[TLSerdes.scala:86:23] wire _des_2_io_out_bits_tail; // @[TLSerdes.scala:86:23] wire _des_2_io_busy; // @[TLSerdes.scala:86:23] wire _des_1_io_out_valid; // @[TLSerdes.scala:86:23] wire [64:0] _des_1_io_out_bits_payload; // @[TLSerdes.scala:86:23] wire _des_1_io_out_bits_head; // @[TLSerdes.scala:86:23] wire _des_1_io_out_bits_tail; // @[TLSerdes.scala:86:23] wire _des_0_io_out_valid; // @[TLSerdes.scala:86:23] wire [7:0] _des_0_io_out_bits_payload; // @[TLSerdes.scala:86:23] wire _des_0_io_out_bits_head; // @[TLSerdes.scala:86:23] wire _des_0_io_out_bits_tail; // @[TLSerdes.scala:86:23] wire _in_channels_4_2_io_beat_ready; // @[TLSerdes.scala:82:28] wire [7:0] _in_channels_3_2_io_protocol_bits_size; // @[TLSerdes.scala:81:28] wire [7:0] _in_channels_3_2_io_protocol_bits_source; // @[TLSerdes.scala:81:28] wire [63:0] _in_channels_3_2_io_protocol_bits_address; // @[TLSerdes.scala:81:28] wire _in_channels_3_2_io_beat_ready; // @[TLSerdes.scala:81:28] wire _in_channels_2_2_io_beat_ready; // @[TLSerdes.scala:80:28] wire [7:0] _in_channels_1_2_io_protocol_bits_size; // @[TLSerdes.scala:79:28] wire [7:0] _in_channels_1_2_io_protocol_bits_source; // @[TLSerdes.scala:79:28] wire [7:0] _in_channels_1_2_io_protocol_bits_sink; // @[TLSerdes.scala:79:28] wire _in_channels_1_2_io_beat_ready; // @[TLSerdes.scala:79:28] wire _in_channels_0_2_io_beat_ready; // @[TLSerdes.scala:78:28] wire _ser_4_io_in_ready; // @[TLSerdes.scala:69:23] wire _ser_4_io_busy; // @[TLSerdes.scala:69:23] wire _ser_2_io_in_ready; // @[TLSerdes.scala:69:23] wire _ser_0_io_in_ready; // @[TLSerdes.scala:69:23] wire _out_channels_4_2_io_beat_valid; // @[TLSerdes.scala:63:50] wire [85:0] _out_channels_4_2_io_beat_bits_payload; // @[TLSerdes.scala:63:50] wire _out_channels_4_2_io_beat_bits_head; // @[TLSerdes.scala:63:50] wire _out_channels_4_2_io_beat_bits_tail; // @[TLSerdes.scala:63:50] wire _out_channels_2_2_io_beat_bits_head; // @[TLSerdes.scala:61:50] wire _out_channels_0_2_io_beat_bits_head; // @[TLSerdes.scala:59:50] wire auto_manager_in_a_valid_0 = auto_manager_in_a_valid; // @[TLSerdes.scala:39:9] wire [2:0] auto_manager_in_a_bits_opcode_0 = auto_manager_in_a_bits_opcode; // @[TLSerdes.scala:39:9] wire [2:0] auto_manager_in_a_bits_param_0 = auto_manager_in_a_bits_param; // @[TLSerdes.scala:39:9] wire [3:0] auto_manager_in_a_bits_size_0 = auto_manager_in_a_bits_size; // @[TLSerdes.scala:39:9] wire auto_manager_in_a_bits_source_0 = auto_manager_in_a_bits_source; // @[TLSerdes.scala:39:9] wire [31:0] auto_manager_in_a_bits_address_0 = auto_manager_in_a_bits_address; // @[TLSerdes.scala:39:9] wire [7:0] auto_manager_in_a_bits_mask_0 = auto_manager_in_a_bits_mask; // @[TLSerdes.scala:39:9] wire [63:0] auto_manager_in_a_bits_data_0 = auto_manager_in_a_bits_data; // @[TLSerdes.scala:39:9] wire auto_manager_in_a_bits_corrupt_0 = auto_manager_in_a_bits_corrupt; // @[TLSerdes.scala:39:9] wire auto_manager_in_d_ready_0 = auto_manager_in_d_ready; // @[TLSerdes.scala:39:9] wire io_ser_0_in_valid_0 = io_ser_0_in_valid; // @[TLSerdes.scala:39:9] wire [31:0] io_ser_0_in_bits_flit_0 = io_ser_0_in_bits_flit; // @[TLSerdes.scala:39:9] wire io_ser_0_out_ready_0 = io_ser_0_out_ready; // @[TLSerdes.scala:39:9] wire io_ser_1_in_valid_0 = io_ser_1_in_valid; // @[TLSerdes.scala:39:9] wire [31:0] io_ser_1_in_bits_flit_0 = io_ser_1_in_bits_flit; // @[TLSerdes.scala:39:9] wire io_ser_2_in_valid_0 = io_ser_2_in_valid; // @[TLSerdes.scala:39:9] wire [31:0] io_ser_2_in_bits_flit_0 = io_ser_2_in_bits_flit; // @[TLSerdes.scala:39:9] wire io_ser_2_out_ready_0 = io_ser_2_out_ready; // @[TLSerdes.scala:39:9] wire io_ser_3_in_valid_0 = io_ser_3_in_valid; // @[TLSerdes.scala:39:9] wire [31:0] io_ser_3_in_bits_flit_0 = io_ser_3_in_bits_flit; // @[TLSerdes.scala:39:9] wire io_ser_4_in_valid_0 = io_ser_4_in_valid; // @[TLSerdes.scala:39:9] wire [31:0] io_ser_4_in_bits_flit_0 = io_ser_4_in_bits_flit; // @[TLSerdes.scala:39:9] wire io_ser_4_out_ready_0 = io_ser_4_out_ready; // @[TLSerdes.scala:39:9] wire [2:0] client_tl_b_bits_opcode = 3'h0; // @[TLSerdes.scala:45:71] wire [2:0] client_tl_d_bits_opcode = 3'h0; // @[TLSerdes.scala:45:71] wire [2:0] _out_channels_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _out_channels_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] out_channels_2_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] out_channels_2_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _in_channels_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:264:74] wire [1:0] client_tl_b_bits_param = 2'h0; // @[TLSerdes.scala:45:71] wire [1:0] client_tl_d_bits_param = 2'h0; // @[TLSerdes.scala:45:71] wire [1:0] _in_channels_WIRE_bits_param = 2'h0; // @[Bundles.scala:264:74] wire [3:0] _out_channels_WIRE_bits_sink = 4'h0; // @[Bundles.scala:267:74] wire [3:0] out_channels_0_1_bits_sink = 4'h0; // @[Bundles.scala:267:61] wire [3:0] _out_channels_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] out_channels_2_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _in_channels_WIRE_bits_size = 4'h0; // @[Bundles.scala:264:74] wire [7:0] client_tl_b_bits_size = 8'h0; // @[TLSerdes.scala:45:71] wire [7:0] client_tl_b_bits_source = 8'h0; // @[TLSerdes.scala:45:71] wire [7:0] client_tl_b_bits_mask = 8'h0; // @[TLSerdes.scala:45:71] wire [7:0] client_tl_d_bits_size = 8'h0; // @[TLSerdes.scala:45:71] wire [7:0] client_tl_d_bits_source = 8'h0; // @[TLSerdes.scala:45:71] wire [7:0] client_tl_d_bits_sink = 8'h0; // @[TLSerdes.scala:45:71] wire [7:0] _in_channels_WIRE_bits_mask = 8'h0; // @[Bundles.scala:264:74] wire [63:0] client_tl_b_bits_address = 64'h0; // @[TLSerdes.scala:45:71] wire [63:0] client_tl_b_bits_data = 64'h0; // @[TLSerdes.scala:45:71] wire [63:0] client_tl_d_bits_data = 64'h0; // @[TLSerdes.scala:45:71] wire [63:0] _out_channels_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] out_channels_2_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _in_channels_WIRE_bits_data = 64'h0; // @[Bundles.scala:264:74] wire [31:0] io_ser_1_out_bits_flit = 32'h0; // @[TLSerdes.scala:39:9] wire [31:0] io_ser_3_out_bits_flit = 32'h0; // @[TLSerdes.scala:39:9] wire [31:0] _out_channels_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] out_channels_2_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _in_channels_WIRE_bits_address = 32'h0; // @[Bundles.scala:264:74] wire io_ser_1_out_ready = 1'h1; // @[TLSerdes.scala:39:9, :40:16, :59:50, :61:50] wire io_ser_3_out_ready = 1'h1; // @[TLSerdes.scala:39:9, :40:16, :59:50, :61:50] wire out_channels_0_1_ready = 1'h1; // @[TLSerdes.scala:39:9, :40:16, :59:50, :61:50] wire out_channels_2_1_ready = 1'h1; // @[TLSerdes.scala:39:9, :40:16, :59:50, :61:50] wire io_ser_0_out_valid = 1'h0; // @[TLSerdes.scala:39:9] wire io_ser_1_out_valid = 1'h0; // @[TLSerdes.scala:39:9] wire io_ser_3_out_valid = 1'h0; // @[TLSerdes.scala:39:9] wire managerNodeIn_a_ready; // @[MixedNode.scala:551:17] wire client_tl_a_ready = 1'h0; // @[TLSerdes.scala:45:71] wire client_tl_b_ready = 1'h0; // @[TLSerdes.scala:45:71] wire client_tl_b_valid = 1'h0; // @[TLSerdes.scala:45:71] wire client_tl_b_bits_corrupt = 1'h0; // @[TLSerdes.scala:45:71] wire client_tl_c_ready = 1'h0; // @[TLSerdes.scala:45:71] wire client_tl_d_ready = 1'h0; // @[TLSerdes.scala:45:71] wire client_tl_d_valid = 1'h0; // @[TLSerdes.scala:45:71] wire client_tl_d_bits_denied = 1'h0; // @[TLSerdes.scala:45:71] wire client_tl_d_bits_corrupt = 1'h0; // @[TLSerdes.scala:45:71] wire client_tl_e_ready = 1'h0; // @[TLSerdes.scala:45:71] wire _out_channels_WIRE_ready = 1'h0; // @[Bundles.scala:267:74] wire _out_channels_WIRE_valid = 1'h0; // @[Bundles.scala:267:74] wire out_channels_0_1_valid = 1'h0; // @[Bundles.scala:267:61] wire _out_channels_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:74] wire _out_channels_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:74] wire _out_channels_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _out_channels_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire out_channels_2_1_valid = 1'h0; // @[Bundles.scala:265:61] wire out_channels_2_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire out_channels_2_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _in_channels_WIRE_ready = 1'h0; // @[Bundles.scala:264:74] wire _in_channels_WIRE_valid = 1'h0; // @[Bundles.scala:264:74] wire _in_channels_WIRE_bits_source = 1'h0; // @[Bundles.scala:264:74] wire _in_channels_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:264:74] wire in_channels_3_1_ready = 1'h0; // @[Bundles.scala:264:61] wire managerNodeIn_a_valid = auto_manager_in_a_valid_0; // @[TLSerdes.scala:39:9] wire [2:0] managerNodeIn_a_bits_opcode = auto_manager_in_a_bits_opcode_0; // @[TLSerdes.scala:39:9] wire [2:0] managerNodeIn_a_bits_param = auto_manager_in_a_bits_param_0; // @[TLSerdes.scala:39:9] wire [3:0] managerNodeIn_a_bits_size = auto_manager_in_a_bits_size_0; // @[TLSerdes.scala:39:9] wire managerNodeIn_a_bits_source = auto_manager_in_a_bits_source_0; // @[TLSerdes.scala:39:9] wire [31:0] managerNodeIn_a_bits_address = auto_manager_in_a_bits_address_0; // @[TLSerdes.scala:39:9] wire [7:0] managerNodeIn_a_bits_mask = auto_manager_in_a_bits_mask_0; // @[TLSerdes.scala:39:9] wire [63:0] managerNodeIn_a_bits_data = auto_manager_in_a_bits_data_0; // @[TLSerdes.scala:39:9] wire managerNodeIn_a_bits_corrupt = auto_manager_in_a_bits_corrupt_0; // @[TLSerdes.scala:39:9] wire managerNodeIn_d_ready = auto_manager_in_d_ready_0; // @[TLSerdes.scala:39:9] wire managerNodeIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] managerNodeIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] managerNodeIn_d_bits_param; // @[MixedNode.scala:551:17] wire [3:0] managerNodeIn_d_bits_size; // @[MixedNode.scala:551:17] wire managerNodeIn_d_bits_source; // @[MixedNode.scala:551:17] wire [3:0] managerNodeIn_d_bits_sink; // @[MixedNode.scala:551:17] wire managerNodeIn_d_bits_denied; // @[MixedNode.scala:551:17] wire [63:0] managerNodeIn_d_bits_data; // @[MixedNode.scala:551:17] wire managerNodeIn_d_bits_corrupt; // @[MixedNode.scala:551:17] wire _io_debug_ser_busy_T_1; // @[package.scala:81:59] wire _io_debug_des_busy_T_3; // @[package.scala:81:59] wire auto_manager_in_a_ready_0; // @[TLSerdes.scala:39:9] wire [2:0] auto_manager_in_d_bits_opcode_0; // @[TLSerdes.scala:39:9] wire [1:0] auto_manager_in_d_bits_param_0; // @[TLSerdes.scala:39:9] wire [3:0] auto_manager_in_d_bits_size_0; // @[TLSerdes.scala:39:9] wire auto_manager_in_d_bits_source_0; // @[TLSerdes.scala:39:9] wire [3:0] auto_manager_in_d_bits_sink_0; // @[TLSerdes.scala:39:9] wire auto_manager_in_d_bits_denied_0; // @[TLSerdes.scala:39:9] wire [63:0] auto_manager_in_d_bits_data_0; // @[TLSerdes.scala:39:9] wire auto_manager_in_d_bits_corrupt_0; // @[TLSerdes.scala:39:9] wire auto_manager_in_d_valid_0; // @[TLSerdes.scala:39:9] wire io_ser_0_in_ready_0; // @[TLSerdes.scala:39:9] wire [31:0] io_ser_0_out_bits_flit_0; // @[TLSerdes.scala:39:9] wire io_ser_1_in_ready_0; // @[TLSerdes.scala:39:9] wire io_ser_2_in_ready_0; // @[TLSerdes.scala:39:9] wire [31:0] io_ser_2_out_bits_flit_0; // @[TLSerdes.scala:39:9] wire io_ser_2_out_valid_0; // @[TLSerdes.scala:39:9] wire io_ser_3_in_ready_0; // @[TLSerdes.scala:39:9] wire io_ser_4_in_ready_0; // @[TLSerdes.scala:39:9] wire [31:0] io_ser_4_out_bits_flit_0; // @[TLSerdes.scala:39:9] wire io_ser_4_out_valid_0; // @[TLSerdes.scala:39:9] wire io_debug_ser_busy; // @[TLSerdes.scala:39:9] wire io_debug_des_busy; // @[TLSerdes.scala:39:9] assign auto_manager_in_a_ready_0 = managerNodeIn_a_ready; // @[TLSerdes.scala:39:9] assign auto_manager_in_d_valid_0 = managerNodeIn_d_valid; // @[TLSerdes.scala:39:9] assign auto_manager_in_d_bits_opcode_0 = managerNodeIn_d_bits_opcode; // @[TLSerdes.scala:39:9] assign auto_manager_in_d_bits_param_0 = managerNodeIn_d_bits_param; // @[TLSerdes.scala:39:9] assign auto_manager_in_d_bits_size_0 = managerNodeIn_d_bits_size; // @[TLSerdes.scala:39:9] assign auto_manager_in_d_bits_source_0 = managerNodeIn_d_bits_source; // @[TLSerdes.scala:39:9] assign auto_manager_in_d_bits_sink_0 = managerNodeIn_d_bits_sink; // @[TLSerdes.scala:39:9] assign auto_manager_in_d_bits_denied_0 = managerNodeIn_d_bits_denied; // @[TLSerdes.scala:39:9] assign auto_manager_in_d_bits_data_0 = managerNodeIn_d_bits_data; // @[TLSerdes.scala:39:9] assign auto_manager_in_d_bits_corrupt_0 = managerNodeIn_d_bits_corrupt; // @[TLSerdes.scala:39:9] wire [2:0] client_tl_a_bits_opcode; // @[TLSerdes.scala:45:71] wire [2:0] client_tl_a_bits_param; // @[TLSerdes.scala:45:71] wire [7:0] client_tl_a_bits_size; // @[TLSerdes.scala:45:71] wire [7:0] client_tl_a_bits_source; // @[TLSerdes.scala:45:71] wire [63:0] client_tl_a_bits_address; // @[TLSerdes.scala:45:71] wire [7:0] client_tl_a_bits_mask; // @[TLSerdes.scala:45:71] wire [63:0] client_tl_a_bits_data; // @[TLSerdes.scala:45:71] wire client_tl_a_bits_corrupt; // @[TLSerdes.scala:45:71] wire client_tl_a_valid; // @[TLSerdes.scala:45:71] wire [2:0] client_tl_c_bits_opcode; // @[TLSerdes.scala:45:71] wire [2:0] client_tl_c_bits_param; // @[TLSerdes.scala:45:71] wire [7:0] client_tl_c_bits_size; // @[TLSerdes.scala:45:71] wire [7:0] client_tl_c_bits_source; // @[TLSerdes.scala:45:71] wire [63:0] client_tl_c_bits_address; // @[TLSerdes.scala:45:71] wire [63:0] client_tl_c_bits_data; // @[TLSerdes.scala:45:71] wire client_tl_c_bits_corrupt; // @[TLSerdes.scala:45:71] wire client_tl_c_valid; // @[TLSerdes.scala:45:71] wire [7:0] client_tl_e_bits_sink; // @[TLSerdes.scala:45:71] wire client_tl_e_valid; // @[TLSerdes.scala:45:71] wire _io_debug_ser_busy_T; // @[package.scala:81:59] assign _io_debug_ser_busy_T_1 = _io_debug_ser_busy_T | _ser_4_io_busy; // @[TLSerdes.scala:69:23] assign io_debug_ser_busy = _io_debug_ser_busy_T_1; // @[TLSerdes.scala:39:9] wire [2:0] in_channels_3_1_bits_opcode; // @[Bundles.scala:264:61] wire [1:0] in_channels_3_1_bits_param; // @[Bundles.scala:264:61] wire [3:0] in_channels_3_1_bits_size; // @[Bundles.scala:264:61] wire in_channels_3_1_bits_source; // @[Bundles.scala:264:61] wire [31:0] in_channels_3_1_bits_address; // @[Bundles.scala:264:61] wire [7:0] in_channels_3_1_bits_mask; // @[Bundles.scala:264:61] wire [63:0] in_channels_3_1_bits_data; // @[Bundles.scala:264:61] wire in_channels_3_1_bits_corrupt; // @[Bundles.scala:264:61] wire in_channels_3_1_valid; // @[Bundles.scala:264:61] assign managerNodeIn_d_bits_size = _in_channels_1_2_io_protocol_bits_size[3:0]; // @[TLSerdes.scala:79:28, :85:9] assign managerNodeIn_d_bits_source = _in_channels_1_2_io_protocol_bits_source[0]; // @[TLSerdes.scala:79:28, :85:9] assign managerNodeIn_d_bits_sink = _in_channels_1_2_io_protocol_bits_sink[3:0]; // @[TLSerdes.scala:79:28, :85:9] assign in_channels_3_1_bits_size = _in_channels_3_2_io_protocol_bits_size[3:0]; // @[TLSerdes.scala:81:28, :85:9] assign in_channels_3_1_bits_source = _in_channels_3_2_io_protocol_bits_source[0]; // @[TLSerdes.scala:81:28, :85:9] assign in_channels_3_1_bits_address = _in_channels_3_2_io_protocol_bits_address[31:0]; // @[TLSerdes.scala:81:28, :85:9] wire _io_debug_des_busy_T; // @[package.scala:81:59] wire _io_debug_des_busy_T_1 = _io_debug_des_busy_T | _des_2_io_busy; // @[TLSerdes.scala:86:23] wire _io_debug_des_busy_T_2 = _io_debug_des_busy_T_1 | _des_3_io_busy; // @[TLSerdes.scala:86:23] assign _io_debug_des_busy_T_3 = _io_debug_des_busy_T_2 | _des_4_io_busy; // @[TLSerdes.scala:86:23] assign io_debug_des_busy = _io_debug_des_busy_T_3; // @[TLSerdes.scala:39:9] TLMonitor_67 monitor ( // @[Nodes.scala:27:25] .clock (clock), .reset (reset), .io_in_a_ready (managerNodeIn_a_ready), // @[MixedNode.scala:551:17] .io_in_a_valid (managerNodeIn_a_valid), // @[MixedNode.scala:551:17] .io_in_a_bits_opcode (managerNodeIn_a_bits_opcode), // @[MixedNode.scala:551:17] .io_in_a_bits_param (managerNodeIn_a_bits_param), // @[MixedNode.scala:551:17] .io_in_a_bits_size (managerNodeIn_a_bits_size), // @[MixedNode.scala:551:17] .io_in_a_bits_source (managerNodeIn_a_bits_source), // @[MixedNode.scala:551:17] .io_in_a_bits_address (managerNodeIn_a_bits_address), // @[MixedNode.scala:551:17] .io_in_a_bits_mask (managerNodeIn_a_bits_mask), // @[MixedNode.scala:551:17] .io_in_a_bits_data (managerNodeIn_a_bits_data), // @[MixedNode.scala:551:17] .io_in_a_bits_corrupt (managerNodeIn_a_bits_corrupt), // @[MixedNode.scala:551:17] .io_in_d_ready (managerNodeIn_d_ready), // @[MixedNode.scala:551:17] .io_in_d_valid (managerNodeIn_d_valid), // @[MixedNode.scala:551:17] .io_in_d_bits_opcode (managerNodeIn_d_bits_opcode), // @[MixedNode.scala:551:17] .io_in_d_bits_param (managerNodeIn_d_bits_param), // @[MixedNode.scala:551:17] .io_in_d_bits_size (managerNodeIn_d_bits_size), // @[MixedNode.scala:551:17] .io_in_d_bits_source (managerNodeIn_d_bits_source), // @[MixedNode.scala:551:17] .io_in_d_bits_sink (managerNodeIn_d_bits_sink), // @[MixedNode.scala:551:17] .io_in_d_bits_denied (managerNodeIn_d_bits_denied), // @[MixedNode.scala:551:17] .io_in_d_bits_data (managerNodeIn_d_bits_data), // @[MixedNode.scala:551:17] .io_in_d_bits_corrupt (managerNodeIn_d_bits_corrupt) // @[MixedNode.scala:551:17] ); // @[Nodes.scala:27:25] TLEToBeat_SerialRAM_a64d64s8k8z8c out_channels_0_2 ( // @[TLSerdes.scala:59:50] .clock (clock), .reset (reset), .io_beat_ready (_ser_0_io_in_ready), // @[TLSerdes.scala:69:23] .io_beat_bits_head (_out_channels_0_2_io_beat_bits_head) ); // @[TLSerdes.scala:59:50] TLCToBeat_SerialRAM_a64d64s8k8z8c out_channels_2_2 ( // @[TLSerdes.scala:61:50] .clock (clock), .reset (reset), .io_beat_ready (_ser_2_io_in_ready), // @[TLSerdes.scala:69:23] .io_beat_bits_head (_out_channels_2_2_io_beat_bits_head) ); // @[TLSerdes.scala:61:50] TLAToBeat_SerialRAM_a64d64s8k8z8c out_channels_4_2 ( // @[TLSerdes.scala:63:50] .clock (clock), .reset (reset), .io_protocol_ready (managerNodeIn_a_ready), .io_protocol_valid (managerNodeIn_a_valid), // @[MixedNode.scala:551:17] .io_protocol_bits_opcode (managerNodeIn_a_bits_opcode), // @[MixedNode.scala:551:17] .io_protocol_bits_param (managerNodeIn_a_bits_param), // @[MixedNode.scala:551:17] .io_protocol_bits_size ({4'h0, managerNodeIn_a_bits_size}), // @[TLSerdes.scala:68:21] .io_protocol_bits_source ({7'h0, managerNodeIn_a_bits_source}), // @[TLSerdes.scala:68:21] .io_protocol_bits_address ({32'h0, managerNodeIn_a_bits_address}), // @[TLSerdes.scala:68:21] .io_protocol_bits_mask (managerNodeIn_a_bits_mask), // @[MixedNode.scala:551:17] .io_protocol_bits_data (managerNodeIn_a_bits_data), // @[MixedNode.scala:551:17] .io_protocol_bits_corrupt (managerNodeIn_a_bits_corrupt), // @[MixedNode.scala:551:17] .io_beat_ready (_ser_4_io_in_ready), // @[TLSerdes.scala:69:23] .io_beat_valid (_out_channels_4_2_io_beat_valid), .io_beat_bits_payload (_out_channels_4_2_io_beat_bits_payload), .io_beat_bits_head (_out_channels_4_2_io_beat_bits_head), .io_beat_bits_tail (_out_channels_4_2_io_beat_bits_tail) ); // @[TLSerdes.scala:63:50] GenericSerializer_TLBeatw10_f32 ser_0 ( // @[TLSerdes.scala:69:23] .clock (clock), .reset (reset), .io_in_ready (_ser_0_io_in_ready), .io_in_bits_head (_out_channels_0_2_io_beat_bits_head), // @[TLSerdes.scala:59:50] .io_out_ready (io_ser_0_out_ready_0), // @[TLSerdes.scala:39:9] .io_out_bits_flit (io_ser_0_out_bits_flit_0) ); // @[TLSerdes.scala:69:23] GenericSerializer_TLBeatw88_f32 ser_2 ( // @[TLSerdes.scala:69:23] .clock (clock), .reset (reset), .io_in_ready (_ser_2_io_in_ready), .io_in_bits_head (_out_channels_2_2_io_beat_bits_head), // @[TLSerdes.scala:61:50] .io_out_ready (io_ser_2_out_ready_0), // @[TLSerdes.scala:39:9] .io_out_valid (io_ser_2_out_valid_0), .io_out_bits_flit (io_ser_2_out_bits_flit_0), .io_busy (_io_debug_ser_busy_T) ); // @[TLSerdes.scala:69:23] GenericSerializer_TLBeatw88_f32_1 ser_4 ( // @[TLSerdes.scala:69:23] .clock (clock), .reset (reset), .io_in_ready (_ser_4_io_in_ready), .io_in_valid (_out_channels_4_2_io_beat_valid), // @[TLSerdes.scala:63:50] .io_in_bits_payload (_out_channels_4_2_io_beat_bits_payload), // @[TLSerdes.scala:63:50] .io_in_bits_head (_out_channels_4_2_io_beat_bits_head), // @[TLSerdes.scala:63:50] .io_in_bits_tail (_out_channels_4_2_io_beat_bits_tail), // @[TLSerdes.scala:63:50] .io_out_ready (io_ser_4_out_ready_0), // @[TLSerdes.scala:39:9] .io_out_valid (io_ser_4_out_valid_0), .io_out_bits_flit (io_ser_4_out_bits_flit_0), .io_busy (_ser_4_io_busy) ); // @[TLSerdes.scala:69:23] TLEFromBeat_SerialRAM_a64d64s8k8z8c in_channels_0_2 ( // @[TLSerdes.scala:78:28] .clock (clock), .reset (reset), .io_protocol_valid (client_tl_e_valid), .io_protocol_bits_sink (client_tl_e_bits_sink), .io_beat_ready (_in_channels_0_2_io_beat_ready), .io_beat_valid (_des_0_io_out_valid), // @[TLSerdes.scala:86:23] .io_beat_bits_payload (_des_0_io_out_bits_payload), // @[TLSerdes.scala:86:23] .io_beat_bits_head (_des_0_io_out_bits_head), // @[TLSerdes.scala:86:23] .io_beat_bits_tail (_des_0_io_out_bits_tail) // @[TLSerdes.scala:86:23] ); // @[TLSerdes.scala:78:28] TLDFromBeat_SerialRAM_a64d64s8k8z8c in_channels_1_2 ( // @[TLSerdes.scala:79:28] .clock (clock), .reset (reset), .io_protocol_ready (managerNodeIn_d_ready), // @[MixedNode.scala:551:17] .io_protocol_valid (managerNodeIn_d_valid), .io_protocol_bits_opcode (managerNodeIn_d_bits_opcode), .io_protocol_bits_param (managerNodeIn_d_bits_param), .io_protocol_bits_size (_in_channels_1_2_io_protocol_bits_size), .io_protocol_bits_source (_in_channels_1_2_io_protocol_bits_source), .io_protocol_bits_sink (_in_channels_1_2_io_protocol_bits_sink), .io_protocol_bits_denied (managerNodeIn_d_bits_denied), .io_protocol_bits_data (managerNodeIn_d_bits_data), .io_protocol_bits_corrupt (managerNodeIn_d_bits_corrupt), .io_beat_ready (_in_channels_1_2_io_beat_ready), .io_beat_valid (_des_1_io_out_valid), // @[TLSerdes.scala:86:23] .io_beat_bits_payload (_des_1_io_out_bits_payload), // @[TLSerdes.scala:86:23] .io_beat_bits_head (_des_1_io_out_bits_head), // @[TLSerdes.scala:86:23] .io_beat_bits_tail (_des_1_io_out_bits_tail) // @[TLSerdes.scala:86:23] ); // @[TLSerdes.scala:79:28] TLCFromBeat_SerialRAM_a64d64s8k8z8c in_channels_2_2 ( // @[TLSerdes.scala:80:28] .clock (clock), .reset (reset), .io_protocol_valid (client_tl_c_valid), .io_protocol_bits_opcode (client_tl_c_bits_opcode), .io_protocol_bits_param (client_tl_c_bits_param), .io_protocol_bits_size (client_tl_c_bits_size), .io_protocol_bits_source (client_tl_c_bits_source), .io_protocol_bits_address (client_tl_c_bits_address), .io_protocol_bits_data (client_tl_c_bits_data), .io_protocol_bits_corrupt (client_tl_c_bits_corrupt), .io_beat_ready (_in_channels_2_2_io_beat_ready), .io_beat_valid (_des_2_io_out_valid), // @[TLSerdes.scala:86:23] .io_beat_bits_payload (_des_2_io_out_bits_payload), // @[TLSerdes.scala:86:23] .io_beat_bits_head (_des_2_io_out_bits_head), // @[TLSerdes.scala:86:23] .io_beat_bits_tail (_des_2_io_out_bits_tail) // @[TLSerdes.scala:86:23] ); // @[TLSerdes.scala:80:28] TLBFromBeat_SerialRAM_a64d64s8k8z8c in_channels_3_2 ( // @[TLSerdes.scala:81:28] .clock (clock), .reset (reset), .io_protocol_valid (in_channels_3_1_valid), .io_protocol_bits_opcode (in_channels_3_1_bits_opcode), .io_protocol_bits_param (in_channels_3_1_bits_param), .io_protocol_bits_size (_in_channels_3_2_io_protocol_bits_size), .io_protocol_bits_source (_in_channels_3_2_io_protocol_bits_source), .io_protocol_bits_address (_in_channels_3_2_io_protocol_bits_address), .io_protocol_bits_mask (in_channels_3_1_bits_mask), .io_protocol_bits_data (in_channels_3_1_bits_data), .io_protocol_bits_corrupt (in_channels_3_1_bits_corrupt), .io_beat_ready (_in_channels_3_2_io_beat_ready), .io_beat_valid (_des_3_io_out_valid), // @[TLSerdes.scala:86:23] .io_beat_bits_payload (_des_3_io_out_bits_payload), // @[TLSerdes.scala:86:23] .io_beat_bits_head (_des_3_io_out_bits_head), // @[TLSerdes.scala:86:23] .io_beat_bits_tail (_des_3_io_out_bits_tail) // @[TLSerdes.scala:86:23] ); // @[TLSerdes.scala:81:28] TLAFromBeat_SerialRAM_a64d64s8k8z8c in_channels_4_2 ( // @[TLSerdes.scala:82:28] .clock (clock), .reset (reset), .io_protocol_valid (client_tl_a_valid), .io_protocol_bits_opcode (client_tl_a_bits_opcode), .io_protocol_bits_param (client_tl_a_bits_param), .io_protocol_bits_size (client_tl_a_bits_size), .io_protocol_bits_source (client_tl_a_bits_source), .io_protocol_bits_address (client_tl_a_bits_address), .io_protocol_bits_mask (client_tl_a_bits_mask), .io_protocol_bits_data (client_tl_a_bits_data), .io_protocol_bits_corrupt (client_tl_a_bits_corrupt), .io_beat_ready (_in_channels_4_2_io_beat_ready), .io_beat_valid (_des_4_io_out_valid), // @[TLSerdes.scala:86:23] .io_beat_bits_payload (_des_4_io_out_bits_payload), // @[TLSerdes.scala:86:23] .io_beat_bits_head (_des_4_io_out_bits_head), // @[TLSerdes.scala:86:23] .io_beat_bits_tail (_des_4_io_out_bits_tail) // @[TLSerdes.scala:86:23] ); // @[TLSerdes.scala:82:28] GenericDeserializer_TLBeatw10_f32_1 des_0 ( // @[TLSerdes.scala:86:23] .clock (clock), .reset (reset), .io_in_ready (io_ser_0_in_ready_0), .io_in_valid (io_ser_0_in_valid_0), // @[TLSerdes.scala:39:9] .io_in_bits_flit (io_ser_0_in_bits_flit_0), // @[TLSerdes.scala:39:9] .io_out_ready (_in_channels_0_2_io_beat_ready), // @[TLSerdes.scala:78:28] .io_out_valid (_des_0_io_out_valid), .io_out_bits_payload (_des_0_io_out_bits_payload), .io_out_bits_head (_des_0_io_out_bits_head), .io_out_bits_tail (_des_0_io_out_bits_tail) ); // @[TLSerdes.scala:86:23] GenericDeserializer_TLBeatw67_f32_1 des_1 ( // @[TLSerdes.scala:86:23] .clock (clock), .reset (reset), .io_in_ready (io_ser_1_in_ready_0), .io_in_valid (io_ser_1_in_valid_0), // @[TLSerdes.scala:39:9] .io_in_bits_flit (io_ser_1_in_bits_flit_0), // @[TLSerdes.scala:39:9] .io_out_ready (_in_channels_1_2_io_beat_ready), // @[TLSerdes.scala:79:28] .io_out_valid (_des_1_io_out_valid), .io_out_bits_payload (_des_1_io_out_bits_payload), .io_out_bits_head (_des_1_io_out_bits_head), .io_out_bits_tail (_des_1_io_out_bits_tail), .io_busy (_io_debug_des_busy_T) ); // @[TLSerdes.scala:86:23] GenericDeserializer_TLBeatw88_f32_2 des_2 ( // @[TLSerdes.scala:86:23] .clock (clock), .reset (reset), .io_in_ready (io_ser_2_in_ready_0), .io_in_valid (io_ser_2_in_valid_0), // @[TLSerdes.scala:39:9] .io_in_bits_flit (io_ser_2_in_bits_flit_0), // @[TLSerdes.scala:39:9] .io_out_ready (_in_channels_2_2_io_beat_ready), // @[TLSerdes.scala:80:28] .io_out_valid (_des_2_io_out_valid), .io_out_bits_payload (_des_2_io_out_bits_payload), .io_out_bits_head (_des_2_io_out_bits_head), .io_out_bits_tail (_des_2_io_out_bits_tail), .io_busy (_des_2_io_busy) ); // @[TLSerdes.scala:86:23] GenericDeserializer_TLBeatw87_f32_1 des_3 ( // @[TLSerdes.scala:86:23] .clock (clock), .reset (reset), .io_in_ready (io_ser_3_in_ready_0), .io_in_valid (io_ser_3_in_valid_0), // @[TLSerdes.scala:39:9] .io_in_bits_flit (io_ser_3_in_bits_flit_0), // @[TLSerdes.scala:39:9] .io_out_ready (_in_channels_3_2_io_beat_ready), // @[TLSerdes.scala:81:28] .io_out_valid (_des_3_io_out_valid), .io_out_bits_payload (_des_3_io_out_bits_payload), .io_out_bits_head (_des_3_io_out_bits_head), .io_out_bits_tail (_des_3_io_out_bits_tail), .io_busy (_des_3_io_busy) ); // @[TLSerdes.scala:86:23] GenericDeserializer_TLBeatw88_f32_3 des_4 ( // @[TLSerdes.scala:86:23] .clock (clock), .reset (reset), .io_in_ready (io_ser_4_in_ready_0), .io_in_valid (io_ser_4_in_valid_0), // @[TLSerdes.scala:39:9] .io_in_bits_flit (io_ser_4_in_bits_flit_0), // @[TLSerdes.scala:39:9] .io_out_ready (_in_channels_4_2_io_beat_ready), // @[TLSerdes.scala:82:28] .io_out_valid (_des_4_io_out_valid), .io_out_bits_payload (_des_4_io_out_bits_payload), .io_out_bits_head (_des_4_io_out_bits_head), .io_out_bits_tail (_des_4_io_out_bits_tail), .io_busy (_des_4_io_busy) ); // @[TLSerdes.scala:86:23] assign auto_manager_in_a_ready = auto_manager_in_a_ready_0; // @[TLSerdes.scala:39:9] assign auto_manager_in_d_valid = auto_manager_in_d_valid_0; // @[TLSerdes.scala:39:9] assign auto_manager_in_d_bits_opcode = auto_manager_in_d_bits_opcode_0; // @[TLSerdes.scala:39:9] assign auto_manager_in_d_bits_param = auto_manager_in_d_bits_param_0; // @[TLSerdes.scala:39:9] assign auto_manager_in_d_bits_size = auto_manager_in_d_bits_size_0; // @[TLSerdes.scala:39:9] assign auto_manager_in_d_bits_source = auto_manager_in_d_bits_source_0; // @[TLSerdes.scala:39:9] assign auto_manager_in_d_bits_sink = auto_manager_in_d_bits_sink_0; // @[TLSerdes.scala:39:9] assign auto_manager_in_d_bits_denied = auto_manager_in_d_bits_denied_0; // @[TLSerdes.scala:39:9] assign auto_manager_in_d_bits_data = auto_manager_in_d_bits_data_0; // @[TLSerdes.scala:39:9] assign auto_manager_in_d_bits_corrupt = auto_manager_in_d_bits_corrupt_0; // @[TLSerdes.scala:39:9] assign io_ser_0_in_ready = io_ser_0_in_ready_0; // @[TLSerdes.scala:39:9] assign io_ser_0_out_bits_flit = io_ser_0_out_bits_flit_0; // @[TLSerdes.scala:39:9] assign io_ser_1_in_ready = io_ser_1_in_ready_0; // @[TLSerdes.scala:39:9] assign io_ser_2_in_ready = io_ser_2_in_ready_0; // @[TLSerdes.scala:39:9] assign io_ser_2_out_valid = io_ser_2_out_valid_0; // @[TLSerdes.scala:39:9] assign io_ser_2_out_bits_flit = io_ser_2_out_bits_flit_0; // @[TLSerdes.scala:39:9] assign io_ser_3_in_ready = io_ser_3_in_ready_0; // @[TLSerdes.scala:39:9] assign io_ser_4_in_ready = io_ser_4_in_ready_0; // @[TLSerdes.scala:39:9] assign io_ser_4_out_valid = io_ser_4_out_valid_0; // @[TLSerdes.scala:39:9] assign io_ser_4_out_bits_flit = io_ser_4_out_bits_flit_0; // @[TLSerdes.scala:39:9] endmodule

Generate the Verilog code corresponding to the following Chisel files. File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /** Like Vec.apply(idx), but tolerates indices of mismatched width */ def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /** Any Data subtype that has a Bool member named valid. */ type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /** converts from camel case to to underscores, also removing all spaces */ def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /** converts spaces or underscores to hyphens, also lowering case */ def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y | (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y || y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /** Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation */ def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File dcache.scala: //****************************************************************************** // Ported from Rocket-Chip // See LICENSE.Berkeley and LICENSE.SiFive in Rocket-Chip for license details. //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ package boom.v3.lsu import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.diplomacy._ import freechips.rocketchip.tilelink._ import freechips.rocketchip.tile._ import freechips.rocketchip.util._ import freechips.rocketchip.rocket._ import boom.v3.common._ import boom.v3.exu.BrUpdateInfo import boom.v3.util.{IsKilledByBranch, GetNewBrMask, BranchKillableQueue, IsOlder, UpdateBrMask, AgePriorityEncoder, WrapInc, Transpose} class BoomWritebackUnit(implicit edge: TLEdgeOut, p: Parameters) extends L1HellaCacheModule()(p) { val io = IO(new Bundle { val req = Flipped(Decoupled(new WritebackReq(edge.bundle))) val meta_read = Decoupled(new L1MetaReadReq) val resp = Output(Bool()) val idx = Output(Valid(UInt())) val data_req = Decoupled(new L1DataReadReq) val data_resp = Input(UInt(encRowBits.W)) val mem_grant = Input(Bool()) val release = Decoupled(new TLBundleC(edge.bundle)) val lsu_release = Decoupled(new TLBundleC(edge.bundle)) }) val req = Reg(new WritebackReq(edge.bundle)) val s_invalid :: s_fill_buffer :: s_lsu_release :: s_active :: s_grant :: Nil = Enum(5) val state = RegInit(s_invalid) val r1_data_req_fired = RegInit(false.B) val r2_data_req_fired = RegInit(false.B) val r1_data_req_cnt = Reg(UInt(log2Up(refillCycles+1).W)) val r2_data_req_cnt = Reg(UInt(log2Up(refillCycles+1).W)) val data_req_cnt = RegInit(0.U(log2Up(refillCycles+1).W)) val (_, last_beat, all_beats_done, beat_count) = edge.count(io.release) val wb_buffer = Reg(Vec(refillCycles, UInt(encRowBits.W))) val acked = RegInit(false.B) io.idx.valid := state =/= s_invalid io.idx.bits := req.idx io.release.valid := false.B io.release.bits := DontCare io.req.ready := false.B io.meta_read.valid := false.B io.meta_read.bits := DontCare io.data_req.valid := false.B io.data_req.bits := DontCare io.resp := false.B io.lsu_release.valid := false.B io.lsu_release.bits := DontCare val r_address = Cat(req.tag, req.idx) << blockOffBits val id = cfg.nMSHRs val probeResponse = edge.ProbeAck( fromSource = id.U, toAddress = r_address, lgSize = lgCacheBlockBytes.U, reportPermissions = req.param, data = wb_buffer(data_req_cnt)) val voluntaryRelease = edge.Release( fromSource = id.U, toAddress = r_address, lgSize = lgCacheBlockBytes.U, shrinkPermissions = req.param, data = wb_buffer(data_req_cnt))._2 when (state === s_invalid) { io.req.ready := true.B when (io.req.fire) { state := s_fill_buffer data_req_cnt := 0.U req := io.req.bits acked := false.B } } .elsewhen (state === s_fill_buffer) { io.meta_read.valid := data_req_cnt < refillCycles.U io.meta_read.bits.idx := req.idx io.meta_read.bits.tag := req.tag io.data_req.valid := data_req_cnt < refillCycles.U io.data_req.bits.way_en := req.way_en io.data_req.bits.addr := (if(refillCycles > 1) Cat(req.idx, data_req_cnt(log2Up(refillCycles)-1,0)) else req.idx) << rowOffBits r1_data_req_fired := false.B r1_data_req_cnt := 0.U r2_data_req_fired := r1_data_req_fired r2_data_req_cnt := r1_data_req_cnt when (io.data_req.fire && io.meta_read.fire) { r1_data_req_fired := true.B r1_data_req_cnt := data_req_cnt data_req_cnt := data_req_cnt + 1.U } when (r2_data_req_fired) { wb_buffer(r2_data_req_cnt) := io.data_resp when (r2_data_req_cnt === (refillCycles-1).U) { io.resp := true.B state := s_lsu_release data_req_cnt := 0.U } } } .elsewhen (state === s_lsu_release) { io.lsu_release.valid := true.B io.lsu_release.bits := probeResponse when (io.lsu_release.fire) { state := s_active } } .elsewhen (state === s_active) { io.release.valid := data_req_cnt < refillCycles.U io.release.bits := Mux(req.voluntary, voluntaryRelease, probeResponse) when (io.mem_grant) { acked := true.B } when (io.release.fire) { data_req_cnt := data_req_cnt + 1.U } when ((data_req_cnt === (refillCycles-1).U) && io.release.fire) { state := Mux(req.voluntary, s_grant, s_invalid) } } .elsewhen (state === s_grant) { when (io.mem_grant) { acked := true.B } when (acked) { state := s_invalid } } } class BoomProbeUnit(implicit edge: TLEdgeOut, p: Parameters) extends L1HellaCacheModule()(p) { val io = IO(new Bundle { val req = Flipped(Decoupled(new TLBundleB(edge.bundle))) val rep = Decoupled(new TLBundleC(edge.bundle)) val meta_read = Decoupled(new L1MetaReadReq) val meta_write = Decoupled(new L1MetaWriteReq) val wb_req = Decoupled(new WritebackReq(edge.bundle)) val way_en = Input(UInt(nWays.W)) val wb_rdy = Input(Bool()) // Is writeback unit currently busy? If so need to retry meta read when its done val mshr_rdy = Input(Bool()) // Is MSHR ready for this request to proceed? val mshr_wb_rdy = Output(Bool()) // Should we block MSHR writebacks while we finish our own? val block_state = Input(new ClientMetadata()) val lsu_release = Decoupled(new TLBundleC(edge.bundle)) val state = Output(Valid(UInt(coreMaxAddrBits.W))) }) val (s_invalid :: s_meta_read :: s_meta_resp :: s_mshr_req :: s_mshr_resp :: s_lsu_release :: s_release :: s_writeback_req :: s_writeback_resp :: s_meta_write :: s_meta_write_resp :: Nil) = Enum(11) val state = RegInit(s_invalid) val req = Reg(new TLBundleB(edge.bundle)) val req_idx = req.address(idxMSB, idxLSB) val req_tag = req.address >> untagBits val way_en = Reg(UInt()) val tag_matches = way_en.orR val old_coh = Reg(new ClientMetadata) val miss_coh = ClientMetadata.onReset val reply_coh = Mux(tag_matches, old_coh, miss_coh) val (is_dirty, report_param, new_coh) = reply_coh.onProbe(req.param) io.state.valid := state =/= s_invalid io.state.bits := req.address io.req.ready := state === s_invalid io.rep.valid := state === s_release io.rep.bits := edge.ProbeAck(req, report_param) assert(!io.rep.valid || !edge.hasData(io.rep.bits), "ProbeUnit should not send ProbeAcks with data, WritebackUnit should handle it") io.meta_read.valid := state === s_meta_read io.meta_read.bits.idx := req_idx io.meta_read.bits.tag := req_tag io.meta_read.bits.way_en := ~(0.U(nWays.W)) io.meta_write.valid := state === s_meta_write io.meta_write.bits.way_en := way_en io.meta_write.bits.idx := req_idx io.meta_write.bits.tag := req_tag io.meta_write.bits.data.tag := req_tag io.meta_write.bits.data.coh := new_coh io.wb_req.valid := state === s_writeback_req io.wb_req.bits.source := req.source io.wb_req.bits.idx := req_idx io.wb_req.bits.tag := req_tag io.wb_req.bits.param := report_param io.wb_req.bits.way_en := way_en io.wb_req.bits.voluntary := false.B io.mshr_wb_rdy := !state.isOneOf(s_release, s_writeback_req, s_writeback_resp, s_meta_write, s_meta_write_resp) io.lsu_release.valid := state === s_lsu_release io.lsu_release.bits := edge.ProbeAck(req, report_param) // state === s_invalid when (state === s_invalid) { when (io.req.fire) { state := s_meta_read req := io.req.bits } } .elsewhen (state === s_meta_read) { when (io.meta_read.fire) { state := s_meta_resp } } .elsewhen (state === s_meta_resp) { // we need to wait one cycle for the metadata to be read from the array state := s_mshr_req } .elsewhen (state === s_mshr_req) { old_coh := io.block_state way_en := io.way_en // if the read didn't go through, we need to retry state := Mux(io.mshr_rdy && io.wb_rdy, s_mshr_resp, s_meta_read) } .elsewhen (state === s_mshr_resp) { state := Mux(tag_matches && is_dirty, s_writeback_req, s_lsu_release) } .elsewhen (state === s_lsu_release) { when (io.lsu_release.fire) { state := s_release } } .elsewhen (state === s_release) { when (io.rep.ready) { state := Mux(tag_matches, s_meta_write, s_invalid) } } .elsewhen (state === s_writeback_req) { when (io.wb_req.fire) { state := s_writeback_resp } } .elsewhen (state === s_writeback_resp) { // wait for the writeback request to finish before updating the metadata when (io.wb_req.ready) { state := s_meta_write } } .elsewhen (state === s_meta_write) { when (io.meta_write.fire) { state := s_meta_write_resp } } .elsewhen (state === s_meta_write_resp) { state := s_invalid } } class BoomL1MetaReadReq(implicit p: Parameters) extends BoomBundle()(p) { val req = Vec(memWidth, new L1MetaReadReq) } class BoomL1DataReadReq(implicit p: Parameters) extends BoomBundle()(p) { val req = Vec(memWidth, new L1DataReadReq) val valid = Vec(memWidth, Bool()) } abstract class AbstractBoomDataArray(implicit p: Parameters) extends BoomModule with HasL1HellaCacheParameters { val io = IO(new BoomBundle { val read = Input(Vec(memWidth, Valid(new L1DataReadReq))) val write = Input(Valid(new L1DataWriteReq)) val resp = Output(Vec(memWidth, Vec(nWays, Bits(encRowBits.W)))) val nacks = Output(Vec(memWidth, Bool())) }) def pipeMap[T <: Data](f: Int => T) = VecInit((0 until memWidth).map(f)) } class BoomDuplicatedDataArray(implicit p: Parameters) extends AbstractBoomDataArray { val waddr = io.write.bits.addr >> rowOffBits for (j <- 0 until memWidth) { val raddr = io.read(j).bits.addr >> rowOffBits for (w <- 0 until nWays) { val array = DescribedSRAM( name = s"array_${w}_${j}", desc = "Non-blocking DCache Data Array", size = nSets * refillCycles, data = Vec(rowWords, Bits(encDataBits.W)) ) when (io.write.bits.way_en(w) && io.write.valid) { val data = VecInit((0 until rowWords) map (i => io.write.bits.data(encDataBits*(i+1)-1,encDataBits*i))) array.write(waddr, data, io.write.bits.wmask.asBools) } io.resp(j)(w) := RegNext(array.read(raddr, io.read(j).bits.way_en(w) && io.read(j).valid).asUInt) } io.nacks(j) := false.B } } class BoomBankedDataArray(implicit p: Parameters) extends AbstractBoomDataArray { val nBanks = boomParams.numDCacheBanks val bankSize = nSets * refillCycles / nBanks require (nBanks >= memWidth) require (bankSize > 0) val bankBits = log2Ceil(nBanks) val bankOffBits = log2Ceil(rowWords) + log2Ceil(wordBytes) val bidxBits = log2Ceil(bankSize) val bidxOffBits = bankOffBits + bankBits //---------------------------------------------------------------------------------------------------- val s0_rbanks = if (nBanks > 1) VecInit(io.read.map(r => (r.bits.addr >> bankOffBits)(bankBits-1,0))) else VecInit(0.U) val s0_wbank = if (nBanks > 1) (io.write.bits.addr >> bankOffBits)(bankBits-1,0) else 0.U val s0_ridxs = VecInit(io.read.map(r => (r.bits.addr >> bidxOffBits)(bidxBits-1,0))) val s0_widx = (io.write.bits.addr >> bidxOffBits)(bidxBits-1,0) val s0_read_valids = VecInit(io.read.map(_.valid)) val s0_bank_conflicts = pipeMap(w => (0 until w).foldLeft(false.B)((c,i) => c || io.read(i).valid && s0_rbanks(i) === s0_rbanks(w))) val s0_do_bank_read = s0_read_valids zip s0_bank_conflicts map {case (v,c) => v && !c} val s0_bank_read_gnts = Transpose(VecInit(s0_rbanks zip s0_do_bank_read map {case (b,d) => VecInit((UIntToOH(b) & Fill(nBanks,d)).asBools)})) val s0_bank_write_gnt = (UIntToOH(s0_wbank) & Fill(nBanks, io.write.valid)).asBools //---------------------------------------------------------------------------------------------------- val s1_rbanks = RegNext(s0_rbanks) val s1_ridxs = RegNext(s0_ridxs) val s1_read_valids = RegNext(s0_read_valids) val s1_pipe_selection = pipeMap(i => VecInit(PriorityEncoderOH(pipeMap(j => if (j < i) s1_read_valids(j) && s1_rbanks(j) === s1_rbanks(i) else if (j == i) true.B else false.B)))) val s1_ridx_match = pipeMap(i => pipeMap(j => if (j < i) s1_ridxs(j) === s1_ridxs(i) else if (j == i) true.B else false.B)) val s1_nacks = pipeMap(w => s1_read_valids(w) && (s1_pipe_selection(w).asUInt & ~s1_ridx_match(w).asUInt).orR) val s1_bank_selection = pipeMap(w => Mux1H(s1_pipe_selection(w), s1_rbanks)) //---------------------------------------------------------------------------------------------------- val s2_bank_selection = RegNext(s1_bank_selection) val s2_nacks = RegNext(s1_nacks) for (w <- 0 until nWays) { val s2_bank_reads = Reg(Vec(nBanks, Bits(encRowBits.W))) for (b <- 0 until nBanks) { val array = DescribedSRAM( name = s"array_${w}_${b}", desc = "Non-blocking DCache Data Array", size = bankSize, data = Vec(rowWords, Bits(encDataBits.W)) ) val ridx = Mux1H(s0_bank_read_gnts(b), s0_ridxs) val way_en = Mux1H(s0_bank_read_gnts(b), io.read.map(_.bits.way_en)) s2_bank_reads(b) := array.read(ridx, way_en(w) && s0_bank_read_gnts(b).reduce(_||_)).asUInt when (io.write.bits.way_en(w) && s0_bank_write_gnt(b)) { val data = VecInit((0 until rowWords) map (i => io.write.bits.data(encDataBits*(i+1)-1,encDataBits*i))) array.write(s0_widx, data, io.write.bits.wmask.asBools) } } for (i <- 0 until memWidth) { io.resp(i)(w) := s2_bank_reads(s2_bank_selection(i)) } } io.nacks := s2_nacks } /** * Top level class wrapping a non-blocking dcache. * * @param hartid hardware thread for the cache */ class BoomNonBlockingDCache(staticIdForMetadataUseOnly: Int)(implicit p: Parameters) extends LazyModule { private val tileParams = p(TileKey) protected val cfg = tileParams.dcache.get protected def cacheClientParameters = cfg.scratch.map(x => Seq()).getOrElse(Seq(TLMasterParameters.v1( name = s"Core ${staticIdForMetadataUseOnly} DCache", sourceId = IdRange(0, 1 max (cfg.nMSHRs + 1)), supportsProbe = TransferSizes(cfg.blockBytes, cfg.blockBytes)))) protected def mmioClientParameters = Seq(TLMasterParameters.v1( name = s"Core ${staticIdForMetadataUseOnly} DCache MMIO", sourceId = IdRange(cfg.nMSHRs + 1, cfg.nMSHRs + 1 + cfg.nMMIOs), requestFifo = true)) val node = TLClientNode(Seq(TLMasterPortParameters.v1( cacheClientParameters ++ mmioClientParameters, minLatency = 1))) lazy val module = new BoomNonBlockingDCacheModule(this) def flushOnFenceI = cfg.scratch.isEmpty && !node.edges.out(0).manager.managers.forall(m => !m.supportsAcquireT || !m.executable || m.regionType >= RegionType.TRACKED || m.regionType <= RegionType.IDEMPOTENT) require(!tileParams.core.haveCFlush || cfg.scratch.isEmpty, "CFLUSH_D_L1 instruction requires a D$") } class BoomDCacheBundle(implicit p: Parameters, edge: TLEdgeOut) extends BoomBundle()(p) { val lsu = Flipped(new LSUDMemIO) } class BoomNonBlockingDCacheModule(outer: BoomNonBlockingDCache) extends LazyModuleImp(outer) with HasL1HellaCacheParameters with HasBoomCoreParameters { implicit val edge = outer.node.edges.out(0) val (tl_out, _) = outer.node.out(0) val io = IO(new BoomDCacheBundle) private val fifoManagers = edge.manager.managers.filter(TLFIFOFixer.allVolatile) fifoManagers.foreach { m => require (m.fifoId == fifoManagers.head.fifoId, s"IOMSHRs must be FIFO for all regions with effects, but HellaCache sees ${m.nodePath.map(_.name)}") } def widthMap[T <: Data](f: Int => T) = VecInit((0 until memWidth).map(f)) val t_replay :: t_probe :: t_wb :: t_mshr_meta_read :: t_lsu :: t_prefetch :: Nil = Enum(6) val wb = Module(new BoomWritebackUnit) val prober = Module(new BoomProbeUnit) val mshrs = Module(new BoomMSHRFile) mshrs.io.clear_all := io.lsu.force_order mshrs.io.brupdate := io.lsu.brupdate mshrs.io.exception := io.lsu.exception mshrs.io.rob_pnr_idx := io.lsu.rob_pnr_idx mshrs.io.rob_head_idx := io.lsu.rob_head_idx // tags def onReset = L1Metadata(0.U, ClientMetadata.onReset) val meta = Seq.fill(memWidth) { Module(new L1MetadataArray(onReset _)) } val metaWriteArb = Module(new Arbiter(new L1MetaWriteReq, 2)) // 0 goes to MSHR refills, 1 goes to prober val metaReadArb = Module(new Arbiter(new BoomL1MetaReadReq, 6)) // 0 goes to MSHR replays, 1 goes to prober, 2 goes to wb, 3 goes to MSHR meta read, // 4 goes to pipeline, 5 goes to prefetcher metaReadArb.io.in := DontCare for (w <- 0 until memWidth) { meta(w).io.write.valid := metaWriteArb.io.out.fire meta(w).io.write.bits := metaWriteArb.io.out.bits meta(w).io.read.valid := metaReadArb.io.out.valid meta(w).io.read.bits := metaReadArb.io.out.bits.req(w) } metaReadArb.io.out.ready := meta.map(_.io.read.ready).reduce(_||_) metaWriteArb.io.out.ready := meta.map(_.io.write.ready).reduce(_||_) // data val data = Module(if (boomParams.numDCacheBanks == 1) new BoomDuplicatedDataArray else new BoomBankedDataArray) val dataWriteArb = Module(new Arbiter(new L1DataWriteReq, 2)) // 0 goes to pipeline, 1 goes to MSHR refills val dataReadArb = Module(new Arbiter(new BoomL1DataReadReq, 3)) // 0 goes to MSHR replays, 1 goes to wb, 2 goes to pipeline dataReadArb.io.in := DontCare for (w <- 0 until memWidth) { data.io.read(w).valid := dataReadArb.io.out.bits.valid(w) && dataReadArb.io.out.valid data.io.read(w).bits := dataReadArb.io.out.bits.req(w) } dataReadArb.io.out.ready := true.B data.io.write.valid := dataWriteArb.io.out.fire data.io.write.bits := dataWriteArb.io.out.bits dataWriteArb.io.out.ready := true.B // ------------ // New requests io.lsu.req.ready := metaReadArb.io.in(4).ready && dataReadArb.io.in(2).ready metaReadArb.io.in(4).valid := io.lsu.req.valid dataReadArb.io.in(2).valid := io.lsu.req.valid for (w <- 0 until memWidth) { // Tag read for new requests metaReadArb.io.in(4).bits.req(w).idx := io.lsu.req.bits(w).bits.addr >> blockOffBits metaReadArb.io.in(4).bits.req(w).way_en := DontCare metaReadArb.io.in(4).bits.req(w).tag := DontCare // Data read for new requests dataReadArb.io.in(2).bits.valid(w) := io.lsu.req.bits(w).valid dataReadArb.io.in(2).bits.req(w).addr := io.lsu.req.bits(w).bits.addr dataReadArb.io.in(2).bits.req(w).way_en := ~0.U(nWays.W) } // ------------ // MSHR Replays val replay_req = Wire(Vec(memWidth, new BoomDCacheReq)) replay_req := DontCare replay_req(0).uop := mshrs.io.replay.bits.uop replay_req(0).addr := mshrs.io.replay.bits.addr replay_req(0).data := mshrs.io.replay.bits.data replay_req(0).is_hella := mshrs.io.replay.bits.is_hella mshrs.io.replay.ready := metaReadArb.io.in(0).ready && dataReadArb.io.in(0).ready // Tag read for MSHR replays // We don't actually need to read the metadata, for replays we already know our way metaReadArb.io.in(0).valid := mshrs.io.replay.valid metaReadArb.io.in(0).bits.req(0).idx := mshrs.io.replay.bits.addr >> blockOffBits metaReadArb.io.in(0).bits.req(0).way_en := DontCare metaReadArb.io.in(0).bits.req(0).tag := DontCare // Data read for MSHR replays dataReadArb.io.in(0).valid := mshrs.io.replay.valid dataReadArb.io.in(0).bits.req(0).addr := mshrs.io.replay.bits.addr dataReadArb.io.in(0).bits.req(0).way_en := mshrs.io.replay.bits.way_en dataReadArb.io.in(0).bits.valid := widthMap(w => (w == 0).B) // ----------- // MSHR Meta read val mshr_read_req = Wire(Vec(memWidth, new BoomDCacheReq)) mshr_read_req := DontCare mshr_read_req(0).uop := NullMicroOp mshr_read_req(0).addr := Cat(mshrs.io.meta_read.bits.tag, mshrs.io.meta_read.bits.idx) << blockOffBits mshr_read_req(0).data := DontCare mshr_read_req(0).is_hella := false.B metaReadArb.io.in(3).valid := mshrs.io.meta_read.valid metaReadArb.io.in(3).bits.req(0) := mshrs.io.meta_read.bits mshrs.io.meta_read.ready := metaReadArb.io.in(3).ready // ----------- // Write-backs val wb_fire = wb.io.meta_read.fire && wb.io.data_req.fire val wb_req = Wire(Vec(memWidth, new BoomDCacheReq)) wb_req := DontCare wb_req(0).uop := NullMicroOp wb_req(0).addr := Cat(wb.io.meta_read.bits.tag, wb.io.data_req.bits.addr) wb_req(0).data := DontCare wb_req(0).is_hella := false.B // Couple the two decoupled interfaces of the WBUnit's meta_read and data_read // Tag read for write-back metaReadArb.io.in(2).valid := wb.io.meta_read.valid metaReadArb.io.in(2).bits.req(0) := wb.io.meta_read.bits wb.io.meta_read.ready := metaReadArb.io.in(2).ready && dataReadArb.io.in(1).ready // Data read for write-back dataReadArb.io.in(1).valid := wb.io.data_req.valid dataReadArb.io.in(1).bits.req(0) := wb.io.data_req.bits dataReadArb.io.in(1).bits.valid := widthMap(w => (w == 0).B) wb.io.data_req.ready := metaReadArb.io.in(2).ready && dataReadArb.io.in(1).ready assert(!(wb.io.meta_read.fire ^ wb.io.data_req.fire)) // ------- // Prober val prober_fire = prober.io.meta_read.fire val prober_req = Wire(Vec(memWidth, new BoomDCacheReq)) prober_req := DontCare prober_req(0).uop := NullMicroOp prober_req(0).addr := Cat(prober.io.meta_read.bits.tag, prober.io.meta_read.bits.idx) << blockOffBits prober_req(0).data := DontCare prober_req(0).is_hella := false.B // Tag read for prober metaReadArb.io.in(1).valid := prober.io.meta_read.valid metaReadArb.io.in(1).bits.req(0) := prober.io.meta_read.bits prober.io.meta_read.ready := metaReadArb.io.in(1).ready // Prober does not need to read data array // ------- // Prefetcher val prefetch_fire = mshrs.io.prefetch.fire val prefetch_req = Wire(Vec(memWidth, new BoomDCacheReq)) prefetch_req := DontCare prefetch_req(0) := mshrs.io.prefetch.bits // Tag read for prefetch metaReadArb.io.in(5).valid := mshrs.io.prefetch.valid metaReadArb.io.in(5).bits.req(0).idx := mshrs.io.prefetch.bits.addr >> blockOffBits metaReadArb.io.in(5).bits.req(0).way_en := DontCare metaReadArb.io.in(5).bits.req(0).tag := DontCare mshrs.io.prefetch.ready := metaReadArb.io.in(5).ready // Prefetch does not need to read data array val s0_valid = Mux(io.lsu.req.fire, VecInit(io.lsu.req.bits.map(_.valid)), Mux(mshrs.io.replay.fire || wb_fire || prober_fire || prefetch_fire || mshrs.io.meta_read.fire, VecInit(1.U(memWidth.W).asBools), VecInit(0.U(memWidth.W).asBools))) val s0_req = Mux(io.lsu.req.fire , VecInit(io.lsu.req.bits.map(_.bits)), Mux(wb_fire , wb_req, Mux(prober_fire , prober_req, Mux(prefetch_fire , prefetch_req, Mux(mshrs.io.meta_read.fire, mshr_read_req , replay_req))))) val s0_type = Mux(io.lsu.req.fire , t_lsu, Mux(wb_fire , t_wb, Mux(prober_fire , t_probe, Mux(prefetch_fire , t_prefetch, Mux(mshrs.io.meta_read.fire, t_mshr_meta_read , t_replay))))) // Does this request need to send a response or nack val s0_send_resp_or_nack = Mux(io.lsu.req.fire, s0_valid, VecInit(Mux(mshrs.io.replay.fire && isRead(mshrs.io.replay.bits.uop.mem_cmd), 1.U(memWidth.W), 0.U(memWidth.W)).asBools)) val s1_req = RegNext(s0_req) for (w <- 0 until memWidth) s1_req(w).uop.br_mask := GetNewBrMask(io.lsu.brupdate, s0_req(w).uop) val s2_store_failed = Wire(Bool()) val s1_valid = widthMap(w => RegNext(s0_valid(w) && !IsKilledByBranch(io.lsu.brupdate, s0_req(w).uop) && !(io.lsu.exception && s0_req(w).uop.uses_ldq) && !(s2_store_failed && io.lsu.req.fire && s0_req(w).uop.uses_stq), init=false.B)) for (w <- 0 until memWidth) assert(!(io.lsu.s1_kill(w) && !RegNext(io.lsu.req.fire) && !RegNext(io.lsu.req.bits(w).valid))) val s1_addr = s1_req.map(_.addr) val s1_nack = s1_addr.map(a => a(idxMSB,idxLSB) === prober.io.meta_write.bits.idx && !prober.io.req.ready) val s1_send_resp_or_nack = RegNext(s0_send_resp_or_nack) val s1_type = RegNext(s0_type) val s1_mshr_meta_read_way_en = RegNext(mshrs.io.meta_read.bits.way_en) val s1_replay_way_en = RegNext(mshrs.io.replay.bits.way_en) // For replays, the metadata isn't written yet val s1_wb_way_en = RegNext(wb.io.data_req.bits.way_en) // tag check def wayMap[T <: Data](f: Int => T) = VecInit((0 until nWays).map(f)) val s1_tag_eq_way = widthMap(i => wayMap((w: Int) => meta(i).io.resp(w).tag === (s1_addr(i) >> untagBits)).asUInt) val s1_tag_match_way = widthMap(i => Mux(s1_type === t_replay, s1_replay_way_en, Mux(s1_type === t_wb, s1_wb_way_en, Mux(s1_type === t_mshr_meta_read, s1_mshr_meta_read_way_en, wayMap((w: Int) => s1_tag_eq_way(i)(w) && meta(i).io.resp(w).coh.isValid()).asUInt)))) val s1_wb_idx_matches = widthMap(i => (s1_addr(i)(untagBits-1,blockOffBits) === wb.io.idx.bits) && wb.io.idx.valid) val s2_req = RegNext(s1_req) val s2_type = RegNext(s1_type) val s2_valid = widthMap(w => RegNext(s1_valid(w) && !io.lsu.s1_kill(w) && !IsKilledByBranch(io.lsu.brupdate, s1_req(w).uop) && !(io.lsu.exception && s1_req(w).uop.uses_ldq) && !(s2_store_failed && (s1_type === t_lsu) && s1_req(w).uop.uses_stq))) for (w <- 0 until memWidth) s2_req(w).uop.br_mask := GetNewBrMask(io.lsu.brupdate, s1_req(w).uop) val s2_tag_match_way = RegNext(s1_tag_match_way) val s2_tag_match = s2_tag_match_way.map(_.orR) val s2_hit_state = widthMap(i => Mux1H(s2_tag_match_way(i), wayMap((w: Int) => RegNext(meta(i).io.resp(w).coh)))) val s2_has_permission = widthMap(w => s2_hit_state(w).onAccess(s2_req(w).uop.mem_cmd)._1) val s2_new_hit_state = widthMap(w => s2_hit_state(w).onAccess(s2_req(w).uop.mem_cmd)._3) val s2_hit = widthMap(w => (s2_tag_match(w) && s2_has_permission(w) && s2_hit_state(w) === s2_new_hit_state(w) && !mshrs.io.block_hit(w)) || s2_type.isOneOf(t_replay, t_wb)) val s2_nack = Wire(Vec(memWidth, Bool())) assert(!(s2_type === t_replay && !s2_hit(0)), "Replays should always hit") assert(!(s2_type === t_wb && !s2_hit(0)), "Writeback should always see data hit") val s2_wb_idx_matches = RegNext(s1_wb_idx_matches) // lr/sc val debug_sc_fail_addr = RegInit(0.U) val debug_sc_fail_cnt = RegInit(0.U(8.W)) val lrsc_count = RegInit(0.U(log2Ceil(lrscCycles).W)) val lrsc_valid = lrsc_count > lrscBackoff.U val lrsc_addr = Reg(UInt()) val s2_lr = s2_req(0).uop.mem_cmd === M_XLR && (!RegNext(s1_nack(0)) || s2_type === t_replay) val s2_sc = s2_req(0).uop.mem_cmd === M_XSC && (!RegNext(s1_nack(0)) || s2_type === t_replay) val s2_lrsc_addr_match = widthMap(w => lrsc_valid && lrsc_addr === (s2_req(w).addr >> blockOffBits)) val s2_sc_fail = s2_sc && !s2_lrsc_addr_match(0) when (lrsc_count > 0.U) { lrsc_count := lrsc_count - 1.U } when (s2_valid(0) && ((s2_type === t_lsu && s2_hit(0) && !s2_nack(0)) || (s2_type === t_replay && s2_req(0).uop.mem_cmd =/= M_FLUSH_ALL))) { when (s2_lr) { lrsc_count := (lrscCycles - 1).U lrsc_addr := s2_req(0).addr >> blockOffBits } when (lrsc_count > 0.U) { lrsc_count := 0.U } } for (w <- 0 until memWidth) { when (s2_valid(w) && s2_type === t_lsu && !s2_hit(w) && !(s2_has_permission(w) && s2_tag_match(w)) && s2_lrsc_addr_match(w) && !s2_nack(w)) { lrsc_count := 0.U } } when (s2_valid(0)) { when (s2_req(0).addr === debug_sc_fail_addr) { when (s2_sc_fail) { debug_sc_fail_cnt := debug_sc_fail_cnt + 1.U } .elsewhen (s2_sc) { debug_sc_fail_cnt := 0.U } } .otherwise { when (s2_sc_fail) { debug_sc_fail_addr := s2_req(0).addr debug_sc_fail_cnt := 1.U } } } assert(debug_sc_fail_cnt < 100.U, "L1DCache failed too many SCs in a row") val s2_data = Wire(Vec(memWidth, Vec(nWays, UInt(encRowBits.W)))) for (i <- 0 until memWidth) { for (w <- 0 until nWays) { s2_data(i)(w) := data.io.resp(i)(w) } } val s2_data_muxed = widthMap(w => Mux1H(s2_tag_match_way(w), s2_data(w))) val s2_word_idx = widthMap(w => if (rowWords == 1) 0.U else s2_req(w).addr(log2Up(rowWords*wordBytes)-1, log2Up(wordBytes))) // replacement policy val replacer = cacheParams.replacement val s1_replaced_way_en = UIntToOH(replacer.way) val s2_replaced_way_en = UIntToOH(RegNext(replacer.way)) val s2_repl_meta = widthMap(i => Mux1H(s2_replaced_way_en, wayMap((w: Int) => RegNext(meta(i).io.resp(w))).toSeq)) // nack because of incoming probe val s2_nack_hit = RegNext(VecInit(s1_nack)) // Nack when we hit something currently being evicted val s2_nack_victim = widthMap(w => s2_valid(w) && s2_hit(w) && mshrs.io.secondary_miss(w)) // MSHRs not ready for request val s2_nack_miss = widthMap(w => s2_valid(w) && !s2_hit(w) && !mshrs.io.req(w).ready) // Bank conflict on data arrays val s2_nack_data = widthMap(w => data.io.nacks(w)) // Can't allocate MSHR for same set currently being written back val s2_nack_wb = widthMap(w => s2_valid(w) && !s2_hit(w) && s2_wb_idx_matches(w)) s2_nack := widthMap(w => (s2_nack_miss(w) || s2_nack_hit(w) || s2_nack_victim(w) || s2_nack_data(w) || s2_nack_wb(w)) && s2_type =/= t_replay) val s2_send_resp = widthMap(w => (RegNext(s1_send_resp_or_nack(w)) && !s2_nack(w) && (s2_hit(w) || (mshrs.io.req(w).fire && isWrite(s2_req(w).uop.mem_cmd) && !isRead(s2_req(w).uop.mem_cmd))))) val s2_send_nack = widthMap(w => (RegNext(s1_send_resp_or_nack(w)) && s2_nack(w))) for (w <- 0 until memWidth) assert(!(s2_send_resp(w) && s2_send_nack(w))) // hits always send a response // If MSHR is not available, LSU has to replay this request later // If MSHR is available and this is only a store(not a amo), we don't need to wait for resp later s2_store_failed := s2_valid(0) && s2_nack(0) && s2_send_nack(0) && s2_req(0).uop.uses_stq // Miss handling for (w <- 0 until memWidth) { mshrs.io.req(w).valid := s2_valid(w) && !s2_hit(w) && !s2_nack_hit(w) && !s2_nack_victim(w) && !s2_nack_data(w) && !s2_nack_wb(w) && s2_type.isOneOf(t_lsu, t_prefetch) && !IsKilledByBranch(io.lsu.brupdate, s2_req(w).uop) && !(io.lsu.exception && s2_req(w).uop.uses_ldq) && (isPrefetch(s2_req(w).uop.mem_cmd) || isRead(s2_req(w).uop.mem_cmd) || isWrite(s2_req(w).uop.mem_cmd)) assert(!(mshrs.io.req(w).valid && s2_type === t_replay), "Replays should not need to go back into MSHRs") mshrs.io.req(w).bits := DontCare mshrs.io.req(w).bits.uop := s2_req(w).uop mshrs.io.req(w).bits.uop.br_mask := GetNewBrMask(io.lsu.brupdate, s2_req(w).uop) mshrs.io.req(w).bits.addr := s2_req(w).addr mshrs.io.req(w).bits.tag_match := s2_tag_match(w) mshrs.io.req(w).bits.old_meta := Mux(s2_tag_match(w), L1Metadata(s2_repl_meta(w).tag, s2_hit_state(w)), s2_repl_meta(w)) mshrs.io.req(w).bits.way_en := Mux(s2_tag_match(w), s2_tag_match_way(w), s2_replaced_way_en) mshrs.io.req(w).bits.data := s2_req(w).data mshrs.io.req(w).bits.is_hella := s2_req(w).is_hella mshrs.io.req_is_probe(w) := s2_type === t_probe && s2_valid(w) } mshrs.io.meta_resp.valid := !s2_nack_hit(0) || prober.io.mshr_wb_rdy mshrs.io.meta_resp.bits := Mux1H(s2_tag_match_way(0), RegNext(meta(0).io.resp)) when (mshrs.io.req.map(_.fire).reduce(_||_)) { replacer.miss } tl_out.a <> mshrs.io.mem_acquire // probes and releases prober.io.req.valid := tl_out.b.valid && !lrsc_valid tl_out.b.ready := prober.io.req.ready && !lrsc_valid prober.io.req.bits := tl_out.b.bits prober.io.way_en := s2_tag_match_way(0) prober.io.block_state := s2_hit_state(0) metaWriteArb.io.in(1) <> prober.io.meta_write prober.io.mshr_rdy := mshrs.io.probe_rdy prober.io.wb_rdy := (prober.io.meta_write.bits.idx =/= wb.io.idx.bits) || !wb.io.idx.valid mshrs.io.prober_state := prober.io.state // refills when (tl_out.d.bits.source === cfg.nMSHRs.U) { // This should be ReleaseAck tl_out.d.ready := true.B mshrs.io.mem_grant.valid := false.B mshrs.io.mem_grant.bits := DontCare } .otherwise { // This should be GrantData mshrs.io.mem_grant <> tl_out.d } dataWriteArb.io.in(1) <> mshrs.io.refill metaWriteArb.io.in(0) <> mshrs.io.meta_write tl_out.e <> mshrs.io.mem_finish // writebacks val wbArb = Module(new Arbiter(new WritebackReq(edge.bundle), 2)) // 0 goes to prober, 1 goes to MSHR evictions wbArb.io.in(0) <> prober.io.wb_req wbArb.io.in(1) <> mshrs.io.wb_req wb.io.req <> wbArb.io.out wb.io.data_resp := s2_data_muxed(0) mshrs.io.wb_resp := wb.io.resp wb.io.mem_grant := tl_out.d.fire && tl_out.d.bits.source === cfg.nMSHRs.U val lsu_release_arb = Module(new Arbiter(new TLBundleC(edge.bundle), 2)) io.lsu.release <> lsu_release_arb.io.out lsu_release_arb.io.in(0) <> wb.io.lsu_release lsu_release_arb.io.in(1) <> prober.io.lsu_release TLArbiter.lowest(edge, tl_out.c, wb.io.release, prober.io.rep) io.lsu.perf.release := edge.done(tl_out.c) io.lsu.perf.acquire := edge.done(tl_out.a) // load data gen val s2_data_word_prebypass = widthMap(w => s2_data_muxed(w) >> Cat(s2_word_idx(w), 0.U(log2Ceil(coreDataBits).W))) val s2_data_word = Wire(Vec(memWidth, UInt())) val loadgen = (0 until memWidth).map { w => new LoadGen(s2_req(w).uop.mem_size, s2_req(w).uop.mem_signed, s2_req(w).addr, s2_data_word(w), s2_sc && (w == 0).B, wordBytes) } // Mux between cache responses and uncache responses val cache_resp = Wire(Vec(memWidth, Valid(new BoomDCacheResp))) for (w <- 0 until memWidth) { cache_resp(w).valid := s2_valid(w) && s2_send_resp(w) cache_resp(w).bits.uop := s2_req(w).uop cache_resp(w).bits.data := loadgen(w).data | s2_sc_fail cache_resp(w).bits.is_hella := s2_req(w).is_hella } val uncache_resp = Wire(Valid(new BoomDCacheResp)) uncache_resp.bits := mshrs.io.resp.bits uncache_resp.valid := mshrs.io.resp.valid mshrs.io.resp.ready := !(cache_resp.map(_.valid).reduce(_&&_)) // We can backpressure the MSHRs, but not cache hits val resp = WireInit(cache_resp) var uncache_responding = false.B for (w <- 0 until memWidth) { val uncache_respond = !cache_resp(w).valid && !uncache_responding when (uncache_respond) { resp(w) := uncache_resp } uncache_responding = uncache_responding || uncache_respond } for (w <- 0 until memWidth) { io.lsu.resp(w).valid := resp(w).valid && !(io.lsu.exception && resp(w).bits.uop.uses_ldq) && !IsKilledByBranch(io.lsu.brupdate, resp(w).bits.uop) io.lsu.resp(w).bits := UpdateBrMask(io.lsu.brupdate, resp(w).bits) io.lsu.nack(w).valid := s2_valid(w) && s2_send_nack(w) && !(io.lsu.exception && s2_req(w).uop.uses_ldq) && !IsKilledByBranch(io.lsu.brupdate, s2_req(w).uop) io.lsu.nack(w).bits := UpdateBrMask(io.lsu.brupdate, s2_req(w)) assert(!(io.lsu.nack(w).valid && s2_type =/= t_lsu)) } // Store/amo hits val s3_req = RegNext(s2_req(0)) val s3_valid = RegNext(s2_valid(0) && s2_hit(0) && isWrite(s2_req(0).uop.mem_cmd) && !s2_sc_fail && !(s2_send_nack(0) && s2_nack(0))) for (w <- 1 until memWidth) { assert(!(s2_valid(w) && s2_hit(w) && isWrite(s2_req(w).uop.mem_cmd) && !s2_sc_fail && !(s2_send_nack(w) && s2_nack(w))), "Store must go through 0th pipe in L1D") } // For bypassing val s4_req = RegNext(s3_req) val s4_valid = RegNext(s3_valid) val s5_req = RegNext(s4_req) val s5_valid = RegNext(s4_valid) val s3_bypass = widthMap(w => s3_valid && ((s2_req(w).addr >> wordOffBits) === (s3_req.addr >> wordOffBits))) val s4_bypass = widthMap(w => s4_valid && ((s2_req(w).addr >> wordOffBits) === (s4_req.addr >> wordOffBits))) val s5_bypass = widthMap(w => s5_valid && ((s2_req(w).addr >> wordOffBits) === (s5_req.addr >> wordOffBits))) // Store -> Load bypassing for (w <- 0 until memWidth) { s2_data_word(w) := Mux(s3_bypass(w), s3_req.data, Mux(s4_bypass(w), s4_req.data, Mux(s5_bypass(w), s5_req.data, s2_data_word_prebypass(w)))) } val amoalu = Module(new AMOALU(xLen)) amoalu.io.mask := new StoreGen(s2_req(0).uop.mem_size, s2_req(0).addr, 0.U, xLen/8).mask amoalu.io.cmd := s2_req(0).uop.mem_cmd amoalu.io.lhs := s2_data_word(0) amoalu.io.rhs := s2_req(0).data s3_req.data := amoalu.io.out val s3_way = RegNext(s2_tag_match_way(0)) dataWriteArb.io.in(0).valid := s3_valid dataWriteArb.io.in(0).bits.addr := s3_req.addr dataWriteArb.io.in(0).bits.wmask := UIntToOH(s3_req.addr.extract(rowOffBits-1,offsetlsb)) dataWriteArb.io.in(0).bits.data := Fill(rowWords, s3_req.data) dataWriteArb.io.in(0).bits.way_en := s3_way io.lsu.ordered := mshrs.io.fence_rdy && !s1_valid.reduce(_||_) && !s2_valid.reduce(_||_) } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.nodes._ import freechips.rocketchip.diplomacy.{ AddressDecoder, AddressSet, BufferParams, DirectedBuffers, IdMap, IdMapEntry, IdRange, RegionType, TransferSizes } import freechips.rocketchip.resources.{Resource, ResourceAddress, ResourcePermissions} import freechips.rocketchip.util.{ AsyncQueueParams, BundleField, BundleFieldBase, BundleKeyBase, CreditedDelay, groupByIntoSeq, RationalDirection, SimpleProduct } import scala.math.max //These transfer sizes describe requests issued from masters on the A channel that will be responded by slaves on the D channel case class TLMasterToSlaveTransferSizes( // Supports both Acquire+Release of the following two sizes: acquireT: TransferSizes = TransferSizes.none, acquireB: TransferSizes = TransferSizes.none, arithmetic: TransferSizes = TransferSizes.none, logical: TransferSizes = TransferSizes.none, get: TransferSizes = TransferSizes.none, putFull: TransferSizes = TransferSizes.none, putPartial: TransferSizes = TransferSizes.none, hint: TransferSizes = TransferSizes.none) extends TLCommonTransferSizes { def intersect(rhs: TLMasterToSlaveTransferSizes) = TLMasterToSlaveTransferSizes( acquireT = acquireT .intersect(rhs.acquireT), acquireB = acquireB .intersect(rhs.acquireB), arithmetic = arithmetic.intersect(rhs.arithmetic), logical = logical .intersect(rhs.logical), get = get .intersect(rhs.get), putFull = putFull .intersect(rhs.putFull), putPartial = putPartial.intersect(rhs.putPartial), hint = hint .intersect(rhs.hint)) def mincover(rhs: TLMasterToSlaveTransferSizes) = TLMasterToSlaveTransferSizes( acquireT = acquireT .mincover(rhs.acquireT), acquireB = acquireB .mincover(rhs.acquireB), arithmetic = arithmetic.mincover(rhs.arithmetic), logical = logical .mincover(rhs.logical), get = get .mincover(rhs.get), putFull = putFull .mincover(rhs.putFull), putPartial = putPartial.mincover(rhs.putPartial), hint = hint .mincover(rhs.hint)) // Reduce rendering to a simple yes/no per field override def toString = { def str(x: TransferSizes, flag: String) = if (x.none) "" else flag def flags = Vector( str(acquireT, "T"), str(acquireB, "B"), str(arithmetic, "A"), str(logical, "L"), str(get, "G"), str(putFull, "F"), str(putPartial, "P"), str(hint, "H")) flags.mkString } // Prints out the actual information in a user readable way def infoString = { s"""acquireT = ${acquireT} |acquireB = ${acquireB} |arithmetic = ${arithmetic} |logical = ${logical} |get = ${get} |putFull = ${putFull} |putPartial = ${putPartial} |hint = ${hint} | |""".stripMargin } } object TLMasterToSlaveTransferSizes { def unknownEmits = TLMasterToSlaveTransferSizes( acquireT = TransferSizes(1, 4096), acquireB = TransferSizes(1, 4096), arithmetic = TransferSizes(1, 4096), logical = TransferSizes(1, 4096), get = TransferSizes(1, 4096), putFull = TransferSizes(1, 4096), putPartial = TransferSizes(1, 4096), hint = TransferSizes(1, 4096)) def unknownSupports = TLMasterToSlaveTransferSizes() } //These transfer sizes describe requests issued from slaves on the B channel that will be responded by masters on the C channel case class TLSlaveToMasterTransferSizes( probe: TransferSizes = TransferSizes.none, arithmetic: TransferSizes = TransferSizes.none, logical: TransferSizes = TransferSizes.none, get: TransferSizes = TransferSizes.none, putFull: TransferSizes = TransferSizes.none, putPartial: TransferSizes = TransferSizes.none, hint: TransferSizes = TransferSizes.none ) extends TLCommonTransferSizes { def intersect(rhs: TLSlaveToMasterTransferSizes) = TLSlaveToMasterTransferSizes( probe = probe .intersect(rhs.probe), arithmetic = arithmetic.intersect(rhs.arithmetic), logical = logical .intersect(rhs.logical), get = get .intersect(rhs.get), putFull = putFull .intersect(rhs.putFull), putPartial = putPartial.intersect(rhs.putPartial), hint = hint .intersect(rhs.hint) ) def mincover(rhs: TLSlaveToMasterTransferSizes) = TLSlaveToMasterTransferSizes( probe = probe .mincover(rhs.probe), arithmetic = arithmetic.mincover(rhs.arithmetic), logical = logical .mincover(rhs.logical), get = get .mincover(rhs.get), putFull = putFull .mincover(rhs.putFull), putPartial = putPartial.mincover(rhs.putPartial), hint = hint .mincover(rhs.hint) ) // Reduce rendering to a simple yes/no per field override def toString = { def str(x: TransferSizes, flag: String) = if (x.none) "" else flag def flags = Vector( str(probe, "P"), str(arithmetic, "A"), str(logical, "L"), str(get, "G"), str(putFull, "F"), str(putPartial, "P"), str(hint, "H")) flags.mkString } // Prints out the actual information in a user readable way def infoString = { s"""probe = ${probe} |arithmetic = ${arithmetic} |logical = ${logical} |get = ${get} |putFull = ${putFull} |putPartial = ${putPartial} |hint = ${hint} | |""".stripMargin } } object TLSlaveToMasterTransferSizes { def unknownEmits = TLSlaveToMasterTransferSizes( arithmetic = TransferSizes(1, 4096), logical = TransferSizes(1, 4096), get = TransferSizes(1, 4096), putFull = TransferSizes(1, 4096), putPartial = TransferSizes(1, 4096), hint = TransferSizes(1, 4096), probe = TransferSizes(1, 4096)) def unknownSupports = TLSlaveToMasterTransferSizes() } trait TLCommonTransferSizes { def arithmetic: TransferSizes def logical: TransferSizes def get: TransferSizes def putFull: TransferSizes def putPartial: TransferSizes def hint: TransferSizes } class TLSlaveParameters private( val nodePath: Seq[BaseNode], val resources: Seq[Resource], setName: Option[String], val address: Seq[AddressSet], val regionType: RegionType.T, val executable: Boolean, val fifoId: Option[Int], val supports: TLMasterToSlaveTransferSizes, val emits: TLSlaveToMasterTransferSizes, // By default, slaves are forbidden from issuing 'denied' responses (it prevents Fragmentation) val alwaysGrantsT: Boolean, // typically only true for CacheCork'd read-write devices; dual: neverReleaseData // If fifoId=Some, all accesses sent to the same fifoId are executed and ACK'd in FIFO order // Note: you can only rely on this FIFO behaviour if your TLMasterParameters include requestFifo val mayDenyGet: Boolean, // applies to: AccessAckData, GrantData val mayDenyPut: Boolean) // applies to: AccessAck, Grant, HintAck // ReleaseAck may NEVER be denied extends SimpleProduct { def sortedAddress = address.sorted override def canEqual(that: Any): Boolean = that.isInstanceOf[TLSlaveParameters] override def productPrefix = "TLSlaveParameters" // We intentionally omit nodePath for equality testing / formatting def productArity: Int = 11 def productElement(n: Int): Any = n match { case 0 => name case 1 => address case 2 => resources case 3 => regionType case 4 => executable case 5 => fifoId case 6 => supports case 7 => emits case 8 => alwaysGrantsT case 9 => mayDenyGet case 10 => mayDenyPut case _ => throw new IndexOutOfBoundsException(n.toString) } def supportsAcquireT: TransferSizes = supports.acquireT def supportsAcquireB: TransferSizes = supports.acquireB def supportsArithmetic: TransferSizes = supports.arithmetic def supportsLogical: TransferSizes = supports.logical def supportsGet: TransferSizes = supports.get def supportsPutFull: TransferSizes = supports.putFull def supportsPutPartial: TransferSizes = supports.putPartial def supportsHint: TransferSizes = supports.hint require (!address.isEmpty, "Address cannot be empty") address.foreach { a => require (a.finite, "Address must be finite") } address.combinations(2).foreach { case Seq(x,y) => require (!x.overlaps(y), s"$x and $y overlap.") } require (supportsPutFull.contains(supportsPutPartial), s"PutFull($supportsPutFull) < PutPartial($supportsPutPartial)") require (supportsPutFull.contains(supportsArithmetic), s"PutFull($supportsPutFull) < Arithmetic($supportsArithmetic)") require (supportsPutFull.contains(supportsLogical), s"PutFull($supportsPutFull) < Logical($supportsLogical)") require (supportsGet.contains(supportsArithmetic), s"Get($supportsGet) < Arithmetic($supportsArithmetic)") require (supportsGet.contains(supportsLogical), s"Get($supportsGet) < Logical($supportsLogical)") require (supportsAcquireB.contains(supportsAcquireT), s"AcquireB($supportsAcquireB) < AcquireT($supportsAcquireT)") require (!alwaysGrantsT || supportsAcquireT, s"Must supportAcquireT if promising to always grantT") // Make sure that the regionType agrees with the capabilities require (!supportsAcquireB || regionType >= RegionType.UNCACHED) // acquire -> uncached, tracked, cached require (regionType <= RegionType.UNCACHED || supportsAcquireB) // tracked, cached -> acquire require (regionType != RegionType.UNCACHED || supportsGet) // uncached -> supportsGet val name = setName.orElse(nodePath.lastOption.map(_.lazyModule.name)).getOrElse("disconnected") val maxTransfer = List( // Largest supported transfer of all types supportsAcquireT.max, supportsAcquireB.max, supportsArithmetic.max, supportsLogical.max, supportsGet.max, supportsPutFull.max, supportsPutPartial.max).max val maxAddress = address.map(_.max).max val minAlignment = address.map(_.alignment).min // The device had better not support a transfer larger than its alignment require (minAlignment >= maxTransfer, s"Bad $address: minAlignment ($minAlignment) must be >= maxTransfer ($maxTransfer)") def toResource: ResourceAddress = { ResourceAddress(address, ResourcePermissions( r = supportsAcquireB || supportsGet, w = supportsAcquireT || supportsPutFull, x = executable, c = supportsAcquireB, a = supportsArithmetic && supportsLogical)) } def findTreeViolation() = nodePath.find { case _: MixedAdapterNode[_, _, _, _, _, _, _, _] => false case _: SinkNode[_, _, _, _, _] => false case node => node.inputs.size != 1 } def isTree = findTreeViolation() == None def infoString = { s"""Slave Name = ${name} |Slave Address = ${address} |supports = ${supports.infoString} | |""".stripMargin } def v1copy( address: Seq[AddressSet] = address, resources: Seq[Resource] = resources, regionType: RegionType.T = regionType, executable: Boolean = executable, nodePath: Seq[BaseNode] = nodePath, supportsAcquireT: TransferSizes = supports.acquireT, supportsAcquireB: TransferSizes = supports.acquireB, supportsArithmetic: TransferSizes = supports.arithmetic, supportsLogical: TransferSizes = supports.logical, supportsGet: TransferSizes = supports.get, supportsPutFull: TransferSizes = supports.putFull, supportsPutPartial: TransferSizes = supports.putPartial, supportsHint: TransferSizes = supports.hint, mayDenyGet: Boolean = mayDenyGet, mayDenyPut: Boolean = mayDenyPut, alwaysGrantsT: Boolean = alwaysGrantsT, fifoId: Option[Int] = fifoId) = { new TLSlaveParameters( setName = setName, address = address, resources = resources, regionType = regionType, executable = executable, nodePath = nodePath, supports = TLMasterToSlaveTransferSizes( acquireT = supportsAcquireT, acquireB = supportsAcquireB, arithmetic = supportsArithmetic, logical = supportsLogical, get = supportsGet, putFull = supportsPutFull, putPartial = supportsPutPartial, hint = supportsHint), emits = emits, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut, alwaysGrantsT = alwaysGrantsT, fifoId = fifoId) } def v2copy( nodePath: Seq[BaseNode] = nodePath, resources: Seq[Resource] = resources, name: Option[String] = setName, address: Seq[AddressSet] = address, regionType: RegionType.T = regionType, executable: Boolean = executable, fifoId: Option[Int] = fifoId, supports: TLMasterToSlaveTransferSizes = supports, emits: TLSlaveToMasterTransferSizes = emits, alwaysGrantsT: Boolean = alwaysGrantsT, mayDenyGet: Boolean = mayDenyGet, mayDenyPut: Boolean = mayDenyPut) = { new TLSlaveParameters( nodePath = nodePath, resources = resources, setName = name, address = address, regionType = regionType, executable = executable, fifoId = fifoId, supports = supports, emits = emits, alwaysGrantsT = alwaysGrantsT, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut) } @deprecated("Use v1copy instead of copy","") def copy( address: Seq[AddressSet] = address, resources: Seq[Resource] = resources, regionType: RegionType.T = regionType, executable: Boolean = executable, nodePath: Seq[BaseNode] = nodePath, supportsAcquireT: TransferSizes = supports.acquireT, supportsAcquireB: TransferSizes = supports.acquireB, supportsArithmetic: TransferSizes = supports.arithmetic, supportsLogical: TransferSizes = supports.logical, supportsGet: TransferSizes = supports.get, supportsPutFull: TransferSizes = supports.putFull, supportsPutPartial: TransferSizes = supports.putPartial, supportsHint: TransferSizes = supports.hint, mayDenyGet: Boolean = mayDenyGet, mayDenyPut: Boolean = mayDenyPut, alwaysGrantsT: Boolean = alwaysGrantsT, fifoId: Option[Int] = fifoId) = { v1copy( address = address, resources = resources, regionType = regionType, executable = executable, nodePath = nodePath, supportsAcquireT = supportsAcquireT, supportsAcquireB = supportsAcquireB, supportsArithmetic = supportsArithmetic, supportsLogical = supportsLogical, supportsGet = supportsGet, supportsPutFull = supportsPutFull, supportsPutPartial = supportsPutPartial, supportsHint = supportsHint, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut, alwaysGrantsT = alwaysGrantsT, fifoId = fifoId) } } object TLSlaveParameters { def v1( address: Seq[AddressSet], resources: Seq[Resource] = Seq(), regionType: RegionType.T = RegionType.GET_EFFECTS, executable: Boolean = false, nodePath: Seq[BaseNode] = Seq(), supportsAcquireT: TransferSizes = TransferSizes.none, supportsAcquireB: TransferSizes = TransferSizes.none, supportsArithmetic: TransferSizes = TransferSizes.none, supportsLogical: TransferSizes = TransferSizes.none, supportsGet: TransferSizes = TransferSizes.none, supportsPutFull: TransferSizes = TransferSizes.none, supportsPutPartial: TransferSizes = TransferSizes.none, supportsHint: TransferSizes = TransferSizes.none, mayDenyGet: Boolean = false, mayDenyPut: Boolean = false, alwaysGrantsT: Boolean = false, fifoId: Option[Int] = None) = { new TLSlaveParameters( setName = None, address = address, resources = resources, regionType = regionType, executable = executable, nodePath = nodePath, supports = TLMasterToSlaveTransferSizes( acquireT = supportsAcquireT, acquireB = supportsAcquireB, arithmetic = supportsArithmetic, logical = supportsLogical, get = supportsGet, putFull = supportsPutFull, putPartial = supportsPutPartial, hint = supportsHint), emits = TLSlaveToMasterTransferSizes.unknownEmits, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut, alwaysGrantsT = alwaysGrantsT, fifoId = fifoId) } def v2( address: Seq[AddressSet], nodePath: Seq[BaseNode] = Seq(), resources: Seq[Resource] = Seq(), name: Option[String] = None, regionType: RegionType.T = RegionType.GET_EFFECTS, executable: Boolean = false, fifoId: Option[Int] = None, supports: TLMasterToSlaveTransferSizes = TLMasterToSlaveTransferSizes.unknownSupports, emits: TLSlaveToMasterTransferSizes = TLSlaveToMasterTransferSizes.unknownEmits, alwaysGrantsT: Boolean = false, mayDenyGet: Boolean = false, mayDenyPut: Boolean = false) = { new TLSlaveParameters( nodePath = nodePath, resources = resources, setName = name, address = address, regionType = regionType, executable = executable, fifoId = fifoId, supports = supports, emits = emits, alwaysGrantsT = alwaysGrantsT, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut) } } object TLManagerParameters { @deprecated("Use TLSlaveParameters.v1 instead of TLManagerParameters","") def apply( address: Seq[AddressSet], resources: Seq[Resource] = Seq(), regionType: RegionType.T = RegionType.GET_EFFECTS, executable: Boolean = false, nodePath: Seq[BaseNode] = Seq(), supportsAcquireT: TransferSizes = TransferSizes.none, supportsAcquireB: TransferSizes = TransferSizes.none, supportsArithmetic: TransferSizes = TransferSizes.none, supportsLogical: TransferSizes = TransferSizes.none, supportsGet: TransferSizes = TransferSizes.none, supportsPutFull: TransferSizes = TransferSizes.none, supportsPutPartial: TransferSizes = TransferSizes.none, supportsHint: TransferSizes = TransferSizes.none, mayDenyGet: Boolean = false, mayDenyPut: Boolean = false, alwaysGrantsT: Boolean = false, fifoId: Option[Int] = None) = TLSlaveParameters.v1( address, resources, regionType, executable, nodePath, supportsAcquireT, supportsAcquireB, supportsArithmetic, supportsLogical, supportsGet, supportsPutFull, supportsPutPartial, supportsHint, mayDenyGet, mayDenyPut, alwaysGrantsT, fifoId, ) } case class TLChannelBeatBytes(a: Option[Int], b: Option[Int], c: Option[Int], d: Option[Int]) { def members = Seq(a, b, c, d) members.collect { case Some(beatBytes) => require (isPow2(beatBytes), "Data channel width must be a power of 2") } } object TLChannelBeatBytes{ def apply(beatBytes: Int): TLChannelBeatBytes = TLChannelBeatBytes( Some(beatBytes), Some(beatBytes), Some(beatBytes), Some(beatBytes)) def apply(): TLChannelBeatBytes = TLChannelBeatBytes( None, None, None, None) } class TLSlavePortParameters private( val slaves: Seq[TLSlaveParameters], val channelBytes: TLChannelBeatBytes, val endSinkId: Int, val minLatency: Int, val responseFields: Seq[BundleFieldBase], val requestKeys: Seq[BundleKeyBase]) extends SimpleProduct { def sortedSlaves = slaves.sortBy(_.sortedAddress.head) override def canEqual(that: Any): Boolean = that.isInstanceOf[TLSlavePortParameters] override def productPrefix = "TLSlavePortParameters" def productArity: Int = 6 def productElement(n: Int): Any = n match { case 0 => slaves case 1 => channelBytes case 2 => endSinkId case 3 => minLatency case 4 => responseFields case 5 => requestKeys case _ => throw new IndexOutOfBoundsException(n.toString) } require (!slaves.isEmpty, "Slave ports must have slaves") require (endSinkId >= 0, "Sink ids cannot be negative") require (minLatency >= 0, "Minimum required latency cannot be negative") // Using this API implies you cannot handle mixed-width busses def beatBytes = { channelBytes.members.foreach { width => require (width.isDefined && width == channelBytes.a) } channelBytes.a.get } // TODO this should be deprecated def managers = slaves def requireFifo(policy: TLFIFOFixer.Policy = TLFIFOFixer.allFIFO) = { val relevant = slaves.filter(m => policy(m)) relevant.foreach { m => require(m.fifoId == relevant.head.fifoId, s"${m.name} had fifoId ${m.fifoId}, which was not homogeneous (${slaves.map(s => (s.name, s.fifoId))}) ") } } // Bounds on required sizes def maxAddress = slaves.map(_.maxAddress).max def maxTransfer = slaves.map(_.maxTransfer).max def mayDenyGet = slaves.exists(_.mayDenyGet) def mayDenyPut = slaves.exists(_.mayDenyPut) // Diplomatically determined operation sizes emitted by all outward Slaves // as opposed to emits* which generate circuitry to check which specific addresses val allEmitClaims = slaves.map(_.emits).reduce( _ intersect _) // Operation Emitted by at least one outward Slaves // as opposed to emits* which generate circuitry to check which specific addresses val anyEmitClaims = slaves.map(_.emits).reduce(_ mincover _) // Diplomatically determined operation sizes supported by all outward Slaves // as opposed to supports* which generate circuitry to check which specific addresses val allSupportClaims = slaves.map(_.supports).reduce( _ intersect _) val allSupportAcquireT = allSupportClaims.acquireT val allSupportAcquireB = allSupportClaims.acquireB val allSupportArithmetic = allSupportClaims.arithmetic val allSupportLogical = allSupportClaims.logical val allSupportGet = allSupportClaims.get val allSupportPutFull = allSupportClaims.putFull val allSupportPutPartial = allSupportClaims.putPartial val allSupportHint = allSupportClaims.hint // Operation supported by at least one outward Slaves // as opposed to supports* which generate circuitry to check which specific addresses val anySupportClaims = slaves.map(_.supports).reduce(_ mincover _) val anySupportAcquireT = !anySupportClaims.acquireT.none val anySupportAcquireB = !anySupportClaims.acquireB.none val anySupportArithmetic = !anySupportClaims.arithmetic.none val anySupportLogical = !anySupportClaims.logical.none val anySupportGet = !anySupportClaims.get.none val anySupportPutFull = !anySupportClaims.putFull.none val anySupportPutPartial = !anySupportClaims.putPartial.none val anySupportHint = !anySupportClaims.hint.none // Supporting Acquire means being routable for GrantAck require ((endSinkId == 0) == !anySupportAcquireB) // These return Option[TLSlaveParameters] for your convenience def find(address: BigInt) = slaves.find(_.address.exists(_.contains(address))) // The safe version will check the entire address def findSafe(address: UInt) = VecInit(sortedSlaves.map(_.address.map(_.contains(address)).reduce(_ || _))) // The fast version assumes the address is valid (you probably want fastProperty instead of this function) def findFast(address: UInt) = { val routingMask = AddressDecoder(slaves.map(_.address)) VecInit(sortedSlaves.map(_.address.map(_.widen(~routingMask)).distinct.map(_.contains(address)).reduce(_ || _))) } // Compute the simplest AddressSets that decide a key def fastPropertyGroup[K](p: TLSlaveParameters => K): Seq[(K, Seq[AddressSet])] = { val groups = groupByIntoSeq(sortedSlaves.map(m => (p(m), m.address)))( _._1).map { case (k, vs) => k -> vs.flatMap(_._2) } val reductionMask = AddressDecoder(groups.map(_._2)) groups.map { case (k, seq) => k -> AddressSet.unify(seq.map(_.widen(~reductionMask)).distinct) } } // Select a property def fastProperty[K, D <: Data](address: UInt, p: TLSlaveParameters => K, d: K => D): D = Mux1H(fastPropertyGroup(p).map { case (v, a) => (a.map(_.contains(address)).reduce(_||_), d(v)) }) // Note: returns the actual fifoId + 1 or 0 if None def findFifoIdFast(address: UInt) = fastProperty(address, _.fifoId.map(_+1).getOrElse(0), (i:Int) => i.U) def hasFifoIdFast(address: UInt) = fastProperty(address, _.fifoId.isDefined, (b:Boolean) => b.B) // Does this Port manage this ID/address? def containsSafe(address: UInt) = findSafe(address).reduce(_ || _) private def addressHelper( // setting safe to false indicates that all addresses are expected to be legal, which might reduce circuit complexity safe: Boolean, // member filters out the sizes being checked based on the opcode being emitted or supported member: TLSlaveParameters => TransferSizes, address: UInt, lgSize: UInt, // range provides a limit on the sizes that are expected to be evaluated, which might reduce circuit complexity range: Option[TransferSizes]): Bool = { // trim reduces circuit complexity by intersecting checked sizes with the range argument def trim(x: TransferSizes) = range.map(_.intersect(x)).getOrElse(x) // groupBy returns an unordered map, convert back to Seq and sort the result for determinism // groupByIntoSeq is turning slaves into trimmed membership sizes // We are grouping all the slaves by their transfer size where // if they support the trimmed size then // member is the type of transfer that you are looking for (What you are trying to filter on) // When you consider membership, you are trimming the sizes to only the ones that you care about // you are filtering the slaves based on both whether they support a particular opcode and the size // Grouping the slaves based on the actual transfer size range they support // intersecting the range and checking their membership // FOR SUPPORTCASES instead of returning the list of slaves, // you are returning a map from transfer size to the set of // address sets that are supported for that transfer size // find all the slaves that support a certain type of operation and then group their addresses by the supported size // for every size there could be multiple address ranges // safety is a trade off between checking between all possible addresses vs only the addresses // that are known to have supported sizes // the trade off is 'checking all addresses is a more expensive circuit but will always give you // the right answer even if you give it an illegal address' // the not safe version is a cheaper circuit but if you give it an illegal address then it might produce the wrong answer // fast presumes address legality // This groupByIntoSeq deterministically groups all address sets for which a given `member` transfer size applies. // In the resulting Map of cases, the keys are transfer sizes and the values are all address sets which emit or support that size. val supportCases = groupByIntoSeq(slaves)(m => trim(member(m))).map { case (k: TransferSizes, vs: Seq[TLSlaveParameters]) => k -> vs.flatMap(_.address) } // safe produces a circuit that compares against all possible addresses, // whereas fast presumes that the address is legal but uses an efficient address decoder val mask = if (safe) ~BigInt(0) else AddressDecoder(supportCases.map(_._2)) // Simplified creates the most concise possible representation of each cases' address sets based on the mask. val simplified = supportCases.map { case (k, seq) => k -> AddressSet.unify(seq.map(_.widen(~mask)).distinct) } simplified.map { case (s, a) => // s is a size, you are checking for this size either the size of the operation is in s // We return an or-reduction of all the cases, checking whether any contains both the dynamic size and dynamic address on the wire. ((Some(s) == range).B || s.containsLg(lgSize)) && a.map(_.contains(address)).reduce(_||_) }.foldLeft(false.B)(_||_) } def supportsAcquireTSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.acquireT, address, lgSize, range) def supportsAcquireBSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.acquireB, address, lgSize, range) def supportsArithmeticSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.arithmetic, address, lgSize, range) def supportsLogicalSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.logical, address, lgSize, range) def supportsGetSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.get, address, lgSize, range) def supportsPutFullSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.putFull, address, lgSize, range) def supportsPutPartialSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.putPartial, address, lgSize, range) def supportsHintSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.hint, address, lgSize, range) def supportsAcquireTFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.acquireT, address, lgSize, range) def supportsAcquireBFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.acquireB, address, lgSize, range) def supportsArithmeticFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.arithmetic, address, lgSize, range) def supportsLogicalFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.logical, address, lgSize, range) def supportsGetFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.get, address, lgSize, range) def supportsPutFullFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.putFull, address, lgSize, range) def supportsPutPartialFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.putPartial, address, lgSize, range) def supportsHintFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.hint, address, lgSize, range) def emitsProbeSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.probe, address, lgSize, range) def emitsArithmeticSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.arithmetic, address, lgSize, range) def emitsLogicalSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.logical, address, lgSize, range) def emitsGetSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.get, address, lgSize, range) def emitsPutFullSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.putFull, address, lgSize, range) def emitsPutPartialSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.putPartial, address, lgSize, range) def emitsHintSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.hint, address, lgSize, range) def findTreeViolation() = slaves.flatMap(_.findTreeViolation()).headOption def isTree = !slaves.exists(!_.isTree) def infoString = "Slave Port Beatbytes = " + beatBytes + "\n" + "Slave Port MinLatency = " + minLatency + "\n\n" + slaves.map(_.infoString).mkString def v1copy( managers: Seq[TLSlaveParameters] = slaves, beatBytes: Int = -1, endSinkId: Int = endSinkId, minLatency: Int = minLatency, responseFields: Seq[BundleFieldBase] = responseFields, requestKeys: Seq[BundleKeyBase] = requestKeys) = { new TLSlavePortParameters( slaves = managers, channelBytes = if (beatBytes != -1) TLChannelBeatBytes(beatBytes) else channelBytes, endSinkId = endSinkId, minLatency = minLatency, responseFields = responseFields, requestKeys = requestKeys) } def v2copy( slaves: Seq[TLSlaveParameters] = slaves, channelBytes: TLChannelBeatBytes = channelBytes, endSinkId: Int = endSinkId, minLatency: Int = minLatency, responseFields: Seq[BundleFieldBase] = responseFields, requestKeys: Seq[BundleKeyBase] = requestKeys) = { new TLSlavePortParameters( slaves = slaves, channelBytes = channelBytes, endSinkId = endSinkId, minLatency = minLatency, responseFields = responseFields, requestKeys = requestKeys) } @deprecated("Use v1copy instead of copy","") def copy( managers: Seq[TLSlaveParameters] = slaves, beatBytes: Int = -1, endSinkId: Int = endSinkId, minLatency: Int = minLatency, responseFields: Seq[BundleFieldBase] = responseFields, requestKeys: Seq[BundleKeyBase] = requestKeys) = { v1copy( managers, beatBytes, endSinkId, minLatency, responseFields, requestKeys) } } object TLSlavePortParameters { def v1( managers: Seq[TLSlaveParameters], beatBytes: Int, endSinkId: Int = 0, minLatency: Int = 0, responseFields: Seq[BundleFieldBase] = Nil, requestKeys: Seq[BundleKeyBase] = Nil) = { new TLSlavePortParameters( slaves = managers, channelBytes = TLChannelBeatBytes(beatBytes), endSinkId = endSinkId, minLatency = minLatency, responseFields = responseFields, requestKeys = requestKeys) } } object TLManagerPortParameters { @deprecated("Use TLSlavePortParameters.v1 instead of TLManagerPortParameters","") def apply( managers: Seq[TLSlaveParameters], beatBytes: Int, endSinkId: Int = 0, minLatency: Int = 0, responseFields: Seq[BundleFieldBase] = Nil, requestKeys: Seq[BundleKeyBase] = Nil) = { TLSlavePortParameters.v1( managers, beatBytes, endSinkId, minLatency, responseFields, requestKeys) } } class TLMasterParameters private( val nodePath: Seq[BaseNode], val resources: Seq[Resource], val name: String, val visibility: Seq[AddressSet], val unusedRegionTypes: Set[RegionType.T], val executesOnly: Boolean, val requestFifo: Boolean, // only a request, not a requirement. applies to A, not C. val supports: TLSlaveToMasterTransferSizes, val emits: TLMasterToSlaveTransferSizes, val neverReleasesData: Boolean, val sourceId: IdRange) extends SimpleProduct { override def canEqual(that: Any): Boolean = that.isInstanceOf[TLMasterParameters] override def productPrefix = "TLMasterParameters" // We intentionally omit nodePath for equality testing / formatting def productArity: Int = 10 def productElement(n: Int): Any = n match { case 0 => name case 1 => sourceId case 2 => resources case 3 => visibility case 4 => unusedRegionTypes case 5 => executesOnly case 6 => requestFifo case 7 => supports case 8 => emits case 9 => neverReleasesData case _ => throw new IndexOutOfBoundsException(n.toString) } require (!sourceId.isEmpty) require (!visibility.isEmpty) require (supports.putFull.contains(supports.putPartial)) // We only support these operations if we support Probe (ie: we're a cache) require (supports.probe.contains(supports.arithmetic)) require (supports.probe.contains(supports.logical)) require (supports.probe.contains(supports.get)) require (supports.probe.contains(supports.putFull)) require (supports.probe.contains(supports.putPartial)) require (supports.probe.contains(supports.hint)) visibility.combinations(2).foreach { case Seq(x,y) => require (!x.overlaps(y), s"$x and $y overlap.") } val maxTransfer = List( supports.probe.max, supports.arithmetic.max, supports.logical.max, supports.get.max, supports.putFull.max, supports.putPartial.max).max def infoString = { s"""Master Name = ${name} |visibility = ${visibility} |emits = ${emits.infoString} |sourceId = ${sourceId} | |""".stripMargin } def v1copy( name: String = name, sourceId: IdRange = sourceId, nodePath: Seq[BaseNode] = nodePath, requestFifo: Boolean = requestFifo, visibility: Seq[AddressSet] = visibility, supportsProbe: TransferSizes = supports.probe, supportsArithmetic: TransferSizes = supports.arithmetic, supportsLogical: TransferSizes = supports.logical, supportsGet: TransferSizes = supports.get, supportsPutFull: TransferSizes = supports.putFull, supportsPutPartial: TransferSizes = supports.putPartial, supportsHint: TransferSizes = supports.hint) = { new TLMasterParameters( nodePath = nodePath, resources = this.resources, name = name, visibility = visibility, unusedRegionTypes = this.unusedRegionTypes, executesOnly = this.executesOnly, requestFifo = requestFifo, supports = TLSlaveToMasterTransferSizes( probe = supportsProbe, arithmetic = supportsArithmetic, logical = supportsLogical, get = supportsGet, putFull = supportsPutFull, putPartial = supportsPutPartial, hint = supportsHint), emits = this.emits, neverReleasesData = this.neverReleasesData, sourceId = sourceId) } def v2copy( nodePath: Seq[BaseNode] = nodePath, resources: Seq[Resource] = resources, name: String = name, visibility: Seq[AddressSet] = visibility, unusedRegionTypes: Set[RegionType.T] = unusedRegionTypes, executesOnly: Boolean = executesOnly, requestFifo: Boolean = requestFifo, supports: TLSlaveToMasterTransferSizes = supports, emits: TLMasterToSlaveTransferSizes = emits, neverReleasesData: Boolean = neverReleasesData, sourceId: IdRange = sourceId) = { new TLMasterParameters( nodePath = nodePath, resources = resources, name = name, visibility = visibility, unusedRegionTypes = unusedRegionTypes, executesOnly = executesOnly, requestFifo = requestFifo, supports = supports, emits = emits, neverReleasesData = neverReleasesData, sourceId = sourceId) } @deprecated("Use v1copy instead of copy","") def copy( name: String = name, sourceId: IdRange = sourceId, nodePath: Seq[BaseNode] = nodePath, requestFifo: Boolean = requestFifo, visibility: Seq[AddressSet] = visibility, supportsProbe: TransferSizes = supports.probe, supportsArithmetic: TransferSizes = supports.arithmetic, supportsLogical: TransferSizes = supports.logical, supportsGet: TransferSizes = supports.get, supportsPutFull: TransferSizes = supports.putFull, supportsPutPartial: TransferSizes = supports.putPartial, supportsHint: TransferSizes = supports.hint) = { v1copy( name = name, sourceId = sourceId, nodePath = nodePath, requestFifo = requestFifo, visibility = visibility, supportsProbe = supportsProbe, supportsArithmetic = supportsArithmetic, supportsLogical = supportsLogical, supportsGet = supportsGet, supportsPutFull = supportsPutFull, supportsPutPartial = supportsPutPartial, supportsHint = supportsHint) } } object TLMasterParameters { def v1( name: String, sourceId: IdRange = IdRange(0,1), nodePath: Seq[BaseNode] = Seq(), requestFifo: Boolean = false, visibility: Seq[AddressSet] = Seq(AddressSet(0, ~0)), supportsProbe: TransferSizes = TransferSizes.none, supportsArithmetic: TransferSizes = TransferSizes.none, supportsLogical: TransferSizes = TransferSizes.none, supportsGet: TransferSizes = TransferSizes.none, supportsPutFull: TransferSizes = TransferSizes.none, supportsPutPartial: TransferSizes = TransferSizes.none, supportsHint: TransferSizes = TransferSizes.none) = { new TLMasterParameters( nodePath = nodePath, resources = Nil, name = name, visibility = visibility, unusedRegionTypes = Set(), executesOnly = false, requestFifo = requestFifo, supports = TLSlaveToMasterTransferSizes( probe = supportsProbe, arithmetic = supportsArithmetic, logical = supportsLogical, get = supportsGet, putFull = supportsPutFull, putPartial = supportsPutPartial, hint = supportsHint), emits = TLMasterToSlaveTransferSizes.unknownEmits, neverReleasesData = false, sourceId = sourceId) } def v2( nodePath: Seq[BaseNode] = Seq(), resources: Seq[Resource] = Nil, name: String, visibility: Seq[AddressSet] = Seq(AddressSet(0, ~0)), unusedRegionTypes: Set[RegionType.T] = Set(), executesOnly: Boolean = false, requestFifo: Boolean = false, supports: TLSlaveToMasterTransferSizes = TLSlaveToMasterTransferSizes.unknownSupports, emits: TLMasterToSlaveTransferSizes = TLMasterToSlaveTransferSizes.unknownEmits, neverReleasesData: Boolean = false, sourceId: IdRange = IdRange(0,1)) = { new TLMasterParameters( nodePath = nodePath, resources = resources, name = name, visibility = visibility, unusedRegionTypes = unusedRegionTypes, executesOnly = executesOnly, requestFifo = requestFifo, supports = supports, emits = emits, neverReleasesData = neverReleasesData, sourceId = sourceId) } } object TLClientParameters { @deprecated("Use TLMasterParameters.v1 instead of TLClientParameters","") def apply( name: String, sourceId: IdRange = IdRange(0,1), nodePath: Seq[BaseNode] = Seq(), requestFifo: Boolean = false, visibility: Seq[AddressSet] = Seq(AddressSet.everything), supportsProbe: TransferSizes = TransferSizes.none, supportsArithmetic: TransferSizes = TransferSizes.none, supportsLogical: TransferSizes = TransferSizes.none, supportsGet: TransferSizes = TransferSizes.none, supportsPutFull: TransferSizes = TransferSizes.none, supportsPutPartial: TransferSizes = TransferSizes.none, supportsHint: TransferSizes = TransferSizes.none) = { TLMasterParameters.v1( name = name, sourceId = sourceId, nodePath = nodePath, requestFifo = requestFifo, visibility = visibility, supportsProbe = supportsProbe, supportsArithmetic = supportsArithmetic, supportsLogical = supportsLogical, supportsGet = supportsGet, supportsPutFull = supportsPutFull, supportsPutPartial = supportsPutPartial, supportsHint = supportsHint) } } class TLMasterPortParameters private( val masters: Seq[TLMasterParameters], val channelBytes: TLChannelBeatBytes, val minLatency: Int, val echoFields: Seq[BundleFieldBase], val requestFields: Seq[BundleFieldBase], val responseKeys: Seq[BundleKeyBase]) extends SimpleProduct { override def canEqual(that: Any): Boolean = that.isInstanceOf[TLMasterPortParameters] override def productPrefix = "TLMasterPortParameters" def productArity: Int = 6 def productElement(n: Int): Any = n match { case 0 => masters case 1 => channelBytes case 2 => minLatency case 3 => echoFields case 4 => requestFields case 5 => responseKeys case _ => throw new IndexOutOfBoundsException(n.toString) } require (!masters.isEmpty) require (minLatency >= 0) def clients = masters // Require disjoint ranges for Ids IdRange.overlaps(masters.map(_.sourceId)).foreach { case (x, y) => require (!x.overlaps(y), s"TLClientParameters.sourceId ${x} overlaps ${y}") } // Bounds on required sizes def endSourceId = masters.map(_.sourceId.end).max def maxTransfer = masters.map(_.maxTransfer).max // The unused sources < endSourceId def unusedSources: Seq[Int] = { val usedSources = masters.map(_.sourceId).sortBy(_.start) ((Seq(0) ++ usedSources.map(_.end)) zip usedSources.map(_.start)) flatMap { case (end, start) => end until start } } // Diplomatically determined operation sizes emitted by all inward Masters // as opposed to emits* which generate circuitry to check which specific addresses val allEmitClaims = masters.map(_.emits).reduce( _ intersect _) // Diplomatically determined operation sizes Emitted by at least one inward Masters // as opposed to emits* which generate circuitry to check which specific addresses val anyEmitClaims = masters.map(_.emits).reduce(_ mincover _) // Diplomatically determined operation sizes supported by all inward Masters // as opposed to supports* which generate circuitry to check which specific addresses val allSupportProbe = masters.map(_.supports.probe) .reduce(_ intersect _) val allSupportArithmetic = masters.map(_.supports.arithmetic).reduce(_ intersect _) val allSupportLogical = masters.map(_.supports.logical) .reduce(_ intersect _) val allSupportGet = masters.map(_.supports.get) .reduce(_ intersect _) val allSupportPutFull = masters.map(_.supports.putFull) .reduce(_ intersect _) val allSupportPutPartial = masters.map(_.supports.putPartial).reduce(_ intersect _) val allSupportHint = masters.map(_.supports.hint) .reduce(_ intersect _) // Diplomatically determined operation sizes supported by at least one master // as opposed to supports* which generate circuitry to check which specific addresses val anySupportProbe = masters.map(!_.supports.probe.none) .reduce(_ || _) val anySupportArithmetic = masters.map(!_.supports.arithmetic.none).reduce(_ || _) val anySupportLogical = masters.map(!_.supports.logical.none) .reduce(_ || _) val anySupportGet = masters.map(!_.supports.get.none) .reduce(_ || _) val anySupportPutFull = masters.map(!_.supports.putFull.none) .reduce(_ || _) val anySupportPutPartial = masters.map(!_.supports.putPartial.none).reduce(_ || _) val anySupportHint = masters.map(!_.supports.hint.none) .reduce(_ || _) // These return Option[TLMasterParameters] for your convenience def find(id: Int) = masters.find(_.sourceId.contains(id)) // Synthesizable lookup methods def find(id: UInt) = VecInit(masters.map(_.sourceId.contains(id))) def contains(id: UInt) = find(id).reduce(_ || _) def requestFifo(id: UInt) = Mux1H(find(id), masters.map(c => c.requestFifo.B)) // Available during RTL runtime, checks to see if (id, size) is supported by the master's (client's) diplomatic parameters private def sourceIdHelper(member: TLMasterParameters => TransferSizes)(id: UInt, lgSize: UInt) = { val allSame = masters.map(member(_) == member(masters(0))).reduce(_ && _) // this if statement is a coarse generalization of the groupBy in the sourceIdHelper2 version; // the case where there is only one group. if (allSame) member(masters(0)).containsLg(lgSize) else { // Find the master associated with ID and returns whether that particular master is able to receive transaction of lgSize Mux1H(find(id), masters.map(member(_).containsLg(lgSize))) } } // Check for support of a given operation at a specific id val supportsProbe = sourceIdHelper(_.supports.probe) _ val supportsArithmetic = sourceIdHelper(_.supports.arithmetic) _ val supportsLogical = sourceIdHelper(_.supports.logical) _ val supportsGet = sourceIdHelper(_.supports.get) _ val supportsPutFull = sourceIdHelper(_.supports.putFull) _ val supportsPutPartial = sourceIdHelper(_.supports.putPartial) _ val supportsHint = sourceIdHelper(_.supports.hint) _ // TODO: Merge sourceIdHelper2 with sourceIdHelper private def sourceIdHelper2( member: TLMasterParameters => TransferSizes, sourceId: UInt, lgSize: UInt): Bool = { // Because sourceIds are uniquely owned by each master, we use them to group the // cases that have to be checked. val emitCases = groupByIntoSeq(masters)(m => member(m)).map { case (k, vs) => k -> vs.map(_.sourceId) } emitCases.map { case (s, a) => (s.containsLg(lgSize)) && a.map(_.contains(sourceId)).reduce(_||_) }.foldLeft(false.B)(_||_) } // Check for emit of a given operation at a specific id def emitsAcquireT (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.acquireT, sourceId, lgSize) def emitsAcquireB (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.acquireB, sourceId, lgSize) def emitsArithmetic(sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.arithmetic, sourceId, lgSize) def emitsLogical (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.logical, sourceId, lgSize) def emitsGet (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.get, sourceId, lgSize) def emitsPutFull (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.putFull, sourceId, lgSize) def emitsPutPartial(sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.putPartial, sourceId, lgSize) def emitsHint (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.hint, sourceId, lgSize) def infoString = masters.map(_.infoString).mkString def v1copy( clients: Seq[TLMasterParameters] = masters, minLatency: Int = minLatency, echoFields: Seq[BundleFieldBase] = echoFields, requestFields: Seq[BundleFieldBase] = requestFields, responseKeys: Seq[BundleKeyBase] = responseKeys) = { new TLMasterPortParameters( masters = clients, channelBytes = channelBytes, minLatency = minLatency, echoFields = echoFields, requestFields = requestFields, responseKeys = responseKeys) } def v2copy( masters: Seq[TLMasterParameters] = masters, channelBytes: TLChannelBeatBytes = channelBytes, minLatency: Int = minLatency, echoFields: Seq[BundleFieldBase] = echoFields, requestFields: Seq[BundleFieldBase] = requestFields, responseKeys: Seq[BundleKeyBase] = responseKeys) = { new TLMasterPortParameters( masters = masters, channelBytes = channelBytes, minLatency = minLatency, echoFields = echoFields, requestFields = requestFields, responseKeys = responseKeys) } @deprecated("Use v1copy instead of copy","") def copy( clients: Seq[TLMasterParameters] = masters, minLatency: Int = minLatency, echoFields: Seq[BundleFieldBase] = echoFields, requestFields: Seq[BundleFieldBase] = requestFields, responseKeys: Seq[BundleKeyBase] = responseKeys) = { v1copy( clients, minLatency, echoFields, requestFields, responseKeys) } } object TLClientPortParameters { @deprecated("Use TLMasterPortParameters.v1 instead of TLClientPortParameters","") def apply( clients: Seq[TLMasterParameters], minLatency: Int = 0, echoFields: Seq[BundleFieldBase] = Nil, requestFields: Seq[BundleFieldBase] = Nil, responseKeys: Seq[BundleKeyBase] = Nil) = { TLMasterPortParameters.v1( clients, minLatency, echoFields, requestFields, responseKeys) } } object TLMasterPortParameters { def v1( clients: Seq[TLMasterParameters], minLatency: Int = 0, echoFields: Seq[BundleFieldBase] = Nil, requestFields: Seq[BundleFieldBase] = Nil, responseKeys: Seq[BundleKeyBase] = Nil) = { new TLMasterPortParameters( masters = clients, channelBytes = TLChannelBeatBytes(), minLatency = minLatency, echoFields = echoFields, requestFields = requestFields, responseKeys = responseKeys) } def v2( masters: Seq[TLMasterParameters], channelBytes: TLChannelBeatBytes = TLChannelBeatBytes(), minLatency: Int = 0, echoFields: Seq[BundleFieldBase] = Nil, requestFields: Seq[BundleFieldBase] = Nil, responseKeys: Seq[BundleKeyBase] = Nil) = { new TLMasterPortParameters( masters = masters, channelBytes = channelBytes, minLatency = minLatency, echoFields = echoFields, requestFields = requestFields, responseKeys = responseKeys) } } case class TLBundleParameters( addressBits: Int, dataBits: Int, sourceBits: Int, sinkBits: Int, sizeBits: Int, echoFields: Seq[BundleFieldBase], requestFields: Seq[BundleFieldBase], responseFields: Seq[BundleFieldBase], hasBCE: Boolean) { // Chisel has issues with 0-width wires require (addressBits >= 1) require (dataBits >= 8) require (sourceBits >= 1) require (sinkBits >= 1) require (sizeBits >= 1) require (isPow2(dataBits)) echoFields.foreach { f => require (f.key.isControl, s"${f} is not a legal echo field") } val addrLoBits = log2Up(dataBits/8) // Used to uniquify bus IP names def shortName = s"a${addressBits}d${dataBits}s${sourceBits}k${sinkBits}z${sizeBits}" + (if (hasBCE) "c" else "u") def union(x: TLBundleParameters) = TLBundleParameters( max(addressBits, x.addressBits), max(dataBits, x.dataBits), max(sourceBits, x.sourceBits), max(sinkBits, x.sinkBits), max(sizeBits, x.sizeBits), echoFields = BundleField.union(echoFields ++ x.echoFields), requestFields = BundleField.union(requestFields ++ x.requestFields), responseFields = BundleField.union(responseFields ++ x.responseFields), hasBCE || x.hasBCE) } object TLBundleParameters { val emptyBundleParams = TLBundleParameters( addressBits = 1, dataBits = 8, sourceBits = 1, sinkBits = 1, sizeBits = 1, echoFields = Nil, requestFields = Nil, responseFields = Nil, hasBCE = false) def union(x: Seq[TLBundleParameters]) = x.foldLeft(emptyBundleParams)((x,y) => x.union(y)) def apply(master: TLMasterPortParameters, slave: TLSlavePortParameters) = new TLBundleParameters( addressBits = log2Up(slave.maxAddress + 1), dataBits = slave.beatBytes * 8, sourceBits = log2Up(master.endSourceId), sinkBits = log2Up(slave.endSinkId), sizeBits = log2Up(log2Ceil(max(master.maxTransfer, slave.maxTransfer))+1), echoFields = master.echoFields, requestFields = BundleField.accept(master.requestFields, slave.requestKeys), responseFields = BundleField.accept(slave.responseFields, master.responseKeys), hasBCE = master.anySupportProbe && slave.anySupportAcquireB) } case class TLEdgeParameters( master: TLMasterPortParameters, slave: TLSlavePortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge { // legacy names: def manager = slave def client = master val maxTransfer = max(master.maxTransfer, slave.maxTransfer) val maxLgSize = log2Ceil(maxTransfer) // Sanity check the link... require (maxTransfer >= slave.beatBytes, s"Link's max transfer (${maxTransfer}) < ${slave.slaves.map(_.name)}'s beatBytes (${slave.beatBytes})") def diplomaticClaimsMasterToSlave = master.anyEmitClaims.intersect(slave.anySupportClaims) val bundle = TLBundleParameters(master, slave) def formatEdge = master.infoString + "\n" + slave.infoString } case class TLCreditedDelay( a: CreditedDelay, b: CreditedDelay, c: CreditedDelay, d: CreditedDelay, e: CreditedDelay) { def + (that: TLCreditedDelay): TLCreditedDelay = TLCreditedDelay( a = a + that.a, b = b + that.b, c = c + that.c, d = d + that.d, e = e + that.e) override def toString = s"(${a}, ${b}, ${c}, ${d}, ${e})" } object TLCreditedDelay { def apply(delay: CreditedDelay): TLCreditedDelay = apply(delay, delay.flip, delay, delay.flip, delay) } case class TLCreditedManagerPortParameters(delay: TLCreditedDelay, base: TLSlavePortParameters) {def infoString = base.infoString} case class TLCreditedClientPortParameters(delay: TLCreditedDelay, base: TLMasterPortParameters) {def infoString = base.infoString} case class TLCreditedEdgeParameters(client: TLCreditedClientPortParameters, manager: TLCreditedManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge { val delay = client.delay + manager.delay val bundle = TLBundleParameters(client.base, manager.base) def formatEdge = client.infoString + "\n" + manager.infoString } case class TLAsyncManagerPortParameters(async: AsyncQueueParams, base: TLSlavePortParameters) {def infoString = base.infoString} case class TLAsyncClientPortParameters(base: TLMasterPortParameters) {def infoString = base.infoString} case class TLAsyncBundleParameters(async: AsyncQueueParams, base: TLBundleParameters) case class TLAsyncEdgeParameters(client: TLAsyncClientPortParameters, manager: TLAsyncManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge { val bundle = TLAsyncBundleParameters(manager.async, TLBundleParameters(client.base, manager.base)) def formatEdge = client.infoString + "\n" + manager.infoString } case class TLRationalManagerPortParameters(direction: RationalDirection, base: TLSlavePortParameters) {def infoString = base.infoString} case class TLRationalClientPortParameters(base: TLMasterPortParameters) {def infoString = base.infoString} case class TLRationalEdgeParameters(client: TLRationalClientPortParameters, manager: TLRationalManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge { val bundle = TLBundleParameters(client.base, manager.base) def formatEdge = client.infoString + "\n" + manager.infoString } // To be unified, devices must agree on all of these terms case class ManagerUnificationKey( resources: Seq[Resource], regionType: RegionType.T, executable: Boolean, supportsAcquireT: TransferSizes, supportsAcquireB: TransferSizes, supportsArithmetic: TransferSizes, supportsLogical: TransferSizes, supportsGet: TransferSizes, supportsPutFull: TransferSizes, supportsPutPartial: TransferSizes, supportsHint: TransferSizes) object ManagerUnificationKey { def apply(x: TLSlaveParameters): ManagerUnificationKey = ManagerUnificationKey( resources = x.resources, regionType = x.regionType, executable = x.executable, supportsAcquireT = x.supportsAcquireT, supportsAcquireB = x.supportsAcquireB, supportsArithmetic = x.supportsArithmetic, supportsLogical = x.supportsLogical, supportsGet = x.supportsGet, supportsPutFull = x.supportsPutFull, supportsPutPartial = x.supportsPutPartial, supportsHint = x.supportsHint) } object ManagerUnification { def apply(slaves: Seq[TLSlaveParameters]): List[TLSlaveParameters] = { slaves.groupBy(ManagerUnificationKey.apply).values.map { seq => val agree = seq.forall(_.fifoId == seq.head.fifoId) seq(0).v1copy( address = AddressSet.unify(seq.flatMap(_.address)), fifoId = if (agree) seq(0).fifoId else None) }.toList } } case class TLBufferParams( a: BufferParams = BufferParams.none, b: BufferParams = BufferParams.none, c: BufferParams = BufferParams.none, d: BufferParams = BufferParams.none, e: BufferParams = BufferParams.none ) extends DirectedBuffers[TLBufferParams] { def copyIn(x: BufferParams) = this.copy(b = x, d = x) def copyOut(x: BufferParams) = this.copy(a = x, c = x, e = x) def copyInOut(x: BufferParams) = this.copyIn(x).copyOut(x) } /** Pretty printing of TL source id maps */ class TLSourceIdMap(tl: TLMasterPortParameters) extends IdMap[TLSourceIdMapEntry] { private val tlDigits = String.valueOf(tl.endSourceId-1).length() protected val fmt = s"\t[%${tlDigits}d, %${tlDigits}d) %s%s%s" private val sorted = tl.masters.sortBy(_.sourceId) val mapping: Seq[TLSourceIdMapEntry] = sorted.map { case c => TLSourceIdMapEntry(c.sourceId, c.name, c.supports.probe, c.requestFifo) } } case class TLSourceIdMapEntry(tlId: IdRange, name: String, isCache: Boolean, requestFifo: Boolean) extends IdMapEntry { val from = tlId val to = tlId val maxTransactionsInFlight = Some(tlId.size) } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) || !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.ProbeAckData || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode | small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U || beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }

module BoomWritebackUnit( // @[dcache.scala:24:7] input clock, // @[dcache.scala:24:7] input reset, // @[dcache.scala:24:7] output io_req_ready, // @[dcache.scala:25:14] input io_req_valid, // @[dcache.scala:25:14] input [21:0] io_req_bits_tag, // @[dcache.scala:25:14] input [3:0] io_req_bits_idx, // @[dcache.scala:25:14] input [3:0] io_req_bits_source, // @[dcache.scala:25:14] input [2:0] io_req_bits_param, // @[dcache.scala:25:14] input [1:0] io_req_bits_way_en, // @[dcache.scala:25:14] input io_req_bits_voluntary, // @[dcache.scala:25:14] input io_meta_read_ready, // @[dcache.scala:25:14] output io_meta_read_valid, // @[dcache.scala:25:14] output [3:0] io_meta_read_bits_idx, // @[dcache.scala:25:14] output [21:0] io_meta_read_bits_tag, // @[dcache.scala:25:14] output io_resp, // @[dcache.scala:25:14] output io_idx_valid, // @[dcache.scala:25:14] output [3:0] io_idx_bits, // @[dcache.scala:25:14] input io_data_req_ready, // @[dcache.scala:25:14] output io_data_req_valid, // @[dcache.scala:25:14] output [1:0] io_data_req_bits_way_en, // @[dcache.scala:25:14] output [9:0] io_data_req_bits_addr, // @[dcache.scala:25:14] input [63:0] io_data_resp, // @[dcache.scala:25:14] input io_mem_grant, // @[dcache.scala:25:14] input io_release_ready, // @[dcache.scala:25:14] output io_release_valid, // @[dcache.scala:25:14] output [2:0] io_release_bits_opcode, // @[dcache.scala:25:14] output [2:0] io_release_bits_param, // @[dcache.scala:25:14] output [31:0] io_release_bits_address, // @[dcache.scala:25:14] output [63:0] io_release_bits_data, // @[dcache.scala:25:14] input io_lsu_release_ready, // @[dcache.scala:25:14] output io_lsu_release_valid, // @[dcache.scala:25:14] output [2:0] io_lsu_release_bits_param, // @[dcache.scala:25:14] output [31:0] io_lsu_release_bits_address, // @[dcache.scala:25:14] output [63:0] io_lsu_release_bits_data // @[dcache.scala:25:14] ); reg [2:0] state; // @[dcache.scala:39:22] wire io_req_valid_0 = io_req_valid; // @[dcache.scala:24:7] wire [21:0] io_req_bits_tag_0 = io_req_bits_tag; // @[dcache.scala:24:7] wire [3:0] io_req_bits_idx_0 = io_req_bits_idx; // @[dcache.scala:24:7] wire [3:0] io_req_bits_source_0 = io_req_bits_source; // @[dcache.scala:24:7] wire [2:0] io_req_bits_param_0 = io_req_bits_param; // @[dcache.scala:24:7] wire [1:0] io_req_bits_way_en_0 = io_req_bits_way_en; // @[dcache.scala:24:7] wire io_req_bits_voluntary_0 = io_req_bits_voluntary; // @[dcache.scala:24:7] wire io_meta_read_ready_0 = io_meta_read_ready; // @[dcache.scala:24:7] wire io_data_req_ready_0 = io_data_req_ready; // @[dcache.scala:24:7] wire [63:0] io_data_resp_0 = io_data_resp; // @[dcache.scala:24:7] wire io_mem_grant_0 = io_mem_grant; // @[dcache.scala:24:7] wire io_release_ready_0 = io_release_ready; // @[dcache.scala:24:7] wire io_lsu_release_ready_0 = io_lsu_release_ready; // @[dcache.scala:24:7] wire [26:0] _r_beats1_decode_T = 27'h3FFC0; // @[package.scala:243:71] wire [11:0] _r_beats1_decode_T_1 = 12'hFC0; // @[package.scala:243:76] wire [11:0] _r_beats1_decode_T_2 = 12'h3F; // @[package.scala:243:46] wire [8:0] r_beats1_decode = 9'h7; // @[Edges.scala:220:59] wire _voluntaryRelease_legal_T_7 = 1'h1; // @[Parameters.scala:91:44] wire _voluntaryRelease_legal_T_8 = 1'h1; // @[Parameters.scala:684:29] wire [2:0] voluntaryRelease_opcode = 3'h7; // @[Edges.scala:396:17] wire [2:0] io_lsu_release_bits_opcode = 3'h5; // @[dcache.scala:24:7] wire [2:0] probeResponse_opcode = 3'h5; // @[Edges.scala:433:17] wire io_release_bits_corrupt = 1'h0; // @[dcache.scala:24:7] wire io_lsu_release_bits_corrupt = 1'h0; // @[dcache.scala:24:7] wire probeResponse_corrupt = 1'h0; // @[Edges.scala:433:17] wire _voluntaryRelease_legal_T = 1'h0; // @[Parameters.scala:684:29] wire _voluntaryRelease_legal_T_6 = 1'h0; // @[Parameters.scala:684:54] wire _voluntaryRelease_legal_T_15 = 1'h0; // @[Parameters.scala:686:26] wire voluntaryRelease_corrupt = 1'h0; // @[Edges.scala:396:17] wire _io_release_bits_T_corrupt = 1'h0; // @[dcache.scala:124:27] wire [3:0] io_release_bits_source = 4'h8; // @[dcache.scala:24:7] wire [3:0] io_lsu_release_bits_source = 4'h8; // @[dcache.scala:24:7] wire [3:0] probeResponse_source = 4'h8; // @[Edges.scala:433:17] wire [3:0] voluntaryRelease_source = 4'h8; // @[Edges.scala:396:17] wire [3:0] _io_release_bits_T_source = 4'h8; // @[dcache.scala:124:27] wire [3:0] io_release_bits_size = 4'h6; // @[dcache.scala:24:7] wire [3:0] io_lsu_release_bits_size = 4'h6; // @[dcache.scala:24:7] wire [3:0] probeResponse_size = 4'h6; // @[Edges.scala:433:17] wire [3:0] voluntaryRelease_size = 4'h6; // @[Edges.scala:396:17] wire [3:0] _io_release_bits_T_size = 4'h6; // @[dcache.scala:124:27] wire [1:0] io_meta_read_bits_way_en = 2'h0; // @[dcache.scala:24:7] wire io_req_ready_0 = ~(|state); // @[dcache.scala:24:7, :39:22, :49:31, :80:15] wire _io_idx_valid_T; // @[dcache.scala:49:31] wire [9:0] _io_data_req_bits_addr_T_2; // @[dcache.scala:97:43] wire [2:0] _io_release_bits_T_opcode; // @[dcache.scala:124:27] wire [2:0] _io_release_bits_T_param; // @[dcache.scala:124:27] wire [31:0] _io_release_bits_T_address; // @[dcache.scala:124:27] wire [63:0] _io_release_bits_T_data; // @[dcache.scala:124:27] wire [2:0] probeResponse_param; // @[Edges.scala:433:17] wire [31:0] probeResponse_address; // @[Edges.scala:433:17] wire [63:0] probeResponse_data; // @[Edges.scala:433:17] wire [3:0] io_meta_read_bits_idx_0; // @[dcache.scala:24:7] wire [21:0] io_meta_read_bits_tag_0; // @[dcache.scala:24:7] wire io_meta_read_valid_0; // @[dcache.scala:24:7] wire io_idx_valid_0; // @[dcache.scala:24:7] wire [3:0] io_idx_bits_0; // @[dcache.scala:24:7] wire [1:0] io_data_req_bits_way_en_0; // @[dcache.scala:24:7] wire [9:0] io_data_req_bits_addr_0; // @[dcache.scala:24:7] wire io_data_req_valid_0; // @[dcache.scala:24:7] wire [2:0] io_release_bits_opcode_0; // @[dcache.scala:24:7] wire [2:0] io_release_bits_param_0; // @[dcache.scala:24:7] wire [31:0] io_release_bits_address_0; // @[dcache.scala:24:7] wire [63:0] io_release_bits_data_0; // @[dcache.scala:24:7] wire io_release_valid_0; // @[dcache.scala:24:7] wire [2:0] io_lsu_release_bits_param_0; // @[dcache.scala:24:7] wire [31:0] io_lsu_release_bits_address_0; // @[dcache.scala:24:7] wire [63:0] io_lsu_release_bits_data_0; // @[dcache.scala:24:7] wire io_lsu_release_valid_0; // @[dcache.scala:24:7] wire io_resp_0; // @[dcache.scala:24:7] reg [21:0] req_tag; // @[dcache.scala:37:16] assign io_meta_read_bits_tag_0 = req_tag; // @[dcache.scala:24:7, :37:16] reg [3:0] req_idx; // @[dcache.scala:37:16] assign io_meta_read_bits_idx_0 = req_idx; // @[dcache.scala:24:7, :37:16] assign io_idx_bits_0 = req_idx; // @[dcache.scala:24:7, :37:16] reg [3:0] req_source; // @[dcache.scala:37:16] reg [2:0] req_param; // @[dcache.scala:37:16] assign probeResponse_param = req_param; // @[Edges.scala:433:17] wire [2:0] voluntaryRelease_param = req_param; // @[Edges.scala:396:17] reg [1:0] req_way_en; // @[dcache.scala:37:16] assign io_data_req_bits_way_en_0 = req_way_en; // @[dcache.scala:24:7, :37:16] reg req_voluntary; // @[dcache.scala:37:16] reg r1_data_req_fired; // @[dcache.scala:40:34] reg r2_data_req_fired; // @[dcache.scala:41:34] reg [3:0] r1_data_req_cnt; // @[dcache.scala:42:28] reg [3:0] r2_data_req_cnt; // @[dcache.scala:43:28] reg [3:0] data_req_cnt; // @[dcache.scala:44:29] wire _T_14 = io_release_ready_0 & io_release_valid_0; // @[Decoupled.scala:51:35] wire r_beats1_opdata = io_release_bits_opcode_0[0]; // @[Edges.scala:102:36] wire [8:0] r_beats1 = r_beats1_opdata ? 9'h7 : 9'h0; // @[Edges.scala:102:36, :220:59, :221:14] reg [8:0] r_counter; // @[Edges.scala:229:27] wire [9:0] _r_counter1_T = {1'h0, r_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] r_counter1 = _r_counter1_T[8:0]; // @[Edges.scala:230:28] wire r_1 = r_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _r_last_T = r_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _r_last_T_1 = r_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire last_beat = _r_last_T | _r_last_T_1; // @[Edges.scala:232:{25,33,43}] wire all_beats_done = last_beat & _T_14; // @[Decoupled.scala:51:35] wire [8:0] _r_count_T = ~r_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] beat_count = r_beats1 & _r_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _r_counter_T = r_1 ? r_beats1 : r_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [63:0] wb_buffer_0; // @[dcache.scala:46:22] reg [63:0] wb_buffer_1; // @[dcache.scala:46:22] reg [63:0] wb_buffer_2; // @[dcache.scala:46:22] reg [63:0] wb_buffer_3; // @[dcache.scala:46:22] reg [63:0] wb_buffer_4; // @[dcache.scala:46:22] reg [63:0] wb_buffer_5; // @[dcache.scala:46:22] reg [63:0] wb_buffer_6; // @[dcache.scala:46:22] reg [63:0] wb_buffer_7; // @[dcache.scala:46:22] reg acked; // @[dcache.scala:47:22] assign _io_idx_valid_T = |state; // @[dcache.scala:39:22, :49:31] assign io_idx_valid_0 = _io_idx_valid_T; // @[dcache.scala:24:7, :49:31] wire [25:0] _r_address_T = {req_tag, req_idx}; // @[dcache.scala:37:16, :63:22] wire [31:0] r_address = {_r_address_T, 6'h0}; // @[dcache.scala:63:{22,41}] assign probeResponse_address = r_address; // @[Edges.scala:433:17] wire [31:0] _voluntaryRelease_legal_T_1 = r_address; // @[Parameters.scala:137:31] wire [31:0] voluntaryRelease_address = r_address; // @[Edges.scala:396:17] wire [2:0] _probeResponse_T = data_req_cnt[2:0]; // @[dcache.scala:44:29] wire [2:0] _voluntaryRelease_T = data_req_cnt[2:0]; // @[dcache.scala:44:29] wire [2:0] _io_data_req_bits_addr_T = data_req_cnt[2:0]; // @[dcache.scala:44:29, :96:56] assign io_lsu_release_bits_param_0 = probeResponse_param; // @[Edges.scala:433:17] assign io_lsu_release_bits_address_0 = probeResponse_address; // @[Edges.scala:433:17] assign io_lsu_release_bits_data_0 = probeResponse_data; // @[Edges.scala:433:17] wire [7:0][63:0] _GEN = {{wb_buffer_7}, {wb_buffer_6}, {wb_buffer_5}, {wb_buffer_4}, {wb_buffer_3}, {wb_buffer_2}, {wb_buffer_1}, {wb_buffer_0}}; // @[Edges.scala:441:15] assign probeResponse_data = _GEN[_probeResponse_T]; // @[Edges.scala:433:17, :441:15] wire [32:0] _voluntaryRelease_legal_T_2 = {1'h0, _voluntaryRelease_legal_T_1}; // @[Parameters.scala:137:{31,41}] wire [32:0] _voluntaryRelease_legal_T_3 = _voluntaryRelease_legal_T_2 & 33'h80000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _voluntaryRelease_legal_T_4 = _voluntaryRelease_legal_T_3; // @[Parameters.scala:137:46] wire _voluntaryRelease_legal_T_5 = _voluntaryRelease_legal_T_4 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] _voluntaryRelease_legal_T_9 = r_address ^ 32'h80000000; // @[Parameters.scala:137:31] wire [32:0] _voluntaryRelease_legal_T_10 = {1'h0, _voluntaryRelease_legal_T_9}; // @[Parameters.scala:137:{31,41}] wire [32:0] _voluntaryRelease_legal_T_11 = _voluntaryRelease_legal_T_10 & 33'h80000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _voluntaryRelease_legal_T_12 = _voluntaryRelease_legal_T_11; // @[Parameters.scala:137:46] wire _voluntaryRelease_legal_T_13 = _voluntaryRelease_legal_T_12 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _voluntaryRelease_legal_T_14 = _voluntaryRelease_legal_T_13; // @[Parameters.scala:684:54] wire voluntaryRelease_legal = _voluntaryRelease_legal_T_14; // @[Parameters.scala:684:54, :686:26] wire [63:0] voluntaryRelease_data; // @[Edges.scala:396:17] assign voluntaryRelease_data = _GEN[_voluntaryRelease_T]; // @[Edges.scala:396:17, :404:15, :441:15] wire _T_3 = state == 3'h1; // @[dcache.scala:39:22, :88:22] wire _io_meta_read_valid_T = ~(data_req_cnt[3]); // @[dcache.scala:44:29, :89:40] assign io_meta_read_valid_0 = (|state) & _T_3 & _io_meta_read_valid_T; // @[dcache.scala:24:7, :39:22, :49:31, :54:22, :80:30, :88:{22,41}, :89:{24,40}] wire _io_data_req_valid_T = ~(data_req_cnt[3]); // @[dcache.scala:44:29, :89:40, :93:39] assign io_data_req_valid_0 = (|state) & _T_3 & _io_data_req_valid_T; // @[dcache.scala:24:7, :39:22, :49:31, :56:22, :80:30, :88:{22,41}, :93:{23,39}] wire [6:0] _io_data_req_bits_addr_T_1 = {req_idx, _io_data_req_bits_addr_T}; // @[dcache.scala:37:16, :96:{34,56}] assign _io_data_req_bits_addr_T_2 = {_io_data_req_bits_addr_T_1, 3'h0}; // @[dcache.scala:96:34, :97:43] assign io_data_req_bits_addr_0 = _io_data_req_bits_addr_T_2; // @[dcache.scala:24:7, :97:43] wire [4:0] _GEN_0 = {1'h0, data_req_cnt} + 5'h1; // @[dcache.scala:44:29, :106:36] wire [4:0] _data_req_cnt_T; // @[dcache.scala:106:36] assign _data_req_cnt_T = _GEN_0; // @[dcache.scala:106:36] wire [4:0] _data_req_cnt_T_2; // @[dcache.scala:130:36] assign _data_req_cnt_T_2 = _GEN_0; // @[dcache.scala:106:36, :130:36] wire [3:0] _data_req_cnt_T_1 = _data_req_cnt_T[3:0]; // @[dcache.scala:106:36] wire _T_8 = r2_data_req_cnt == 4'h7; // @[dcache.scala:43:28, :110:29] assign io_resp_0 = (|state) & _T_3 & r2_data_req_fired & _T_8; // @[dcache.scala:24:7, :39:22, :41:34, :49:31, :58:22, :80:30, :88:{22,41}, :108:30, :110:{29,53}] wire _T_9 = state == 3'h2; // @[dcache.scala:39:22, :116:22] assign io_lsu_release_valid_0 = ~(~(|state) | _T_3) & _T_9; // @[dcache.scala:24:7, :39:22, :49:31, :59:24, :80:{15,30}, :88:{22,41}, :116:{22,41}] wire _T_11 = state == 3'h3; // @[dcache.scala:39:22, :122:22] wire _io_release_valid_T = ~(data_req_cnt[3]); // @[dcache.scala:44:29, :89:40, :123:38] wire _GEN_1 = _T_3 | _T_9; // @[dcache.scala:51:22, :88:{22,41}, :116:{22,41}, :122:36] assign io_release_valid_0 = ~(~(|state) | _GEN_1) & _T_11 & _io_release_valid_T; // @[dcache.scala:24:7, :39:22, :49:31, :51:22, :80:{15,30}, :88:41, :116:41, :122:{22,36}, :123:{22,38}] assign _io_release_bits_T_opcode = {1'h1, req_voluntary, 1'h1}; // @[dcache.scala:37:16, :124:27] assign _io_release_bits_T_param = req_voluntary ? voluntaryRelease_param : probeResponse_param; // @[Edges.scala:396:17, :433:17] assign _io_release_bits_T_address = req_voluntary ? voluntaryRelease_address : probeResponse_address; // @[Edges.scala:396:17, :433:17] assign _io_release_bits_T_data = req_voluntary ? voluntaryRelease_data : probeResponse_data; // @[Edges.scala:396:17, :433:17] assign io_release_bits_opcode_0 = _io_release_bits_T_opcode; // @[dcache.scala:24:7, :124:27] assign io_release_bits_param_0 = _io_release_bits_T_param; // @[dcache.scala:24:7, :124:27] assign io_release_bits_address_0 = _io_release_bits_T_address; // @[dcache.scala:24:7, :124:27] assign io_release_bits_data_0 = _io_release_bits_T_data; // @[dcache.scala:24:7, :124:27] wire [3:0] _data_req_cnt_T_3 = _data_req_cnt_T_2[3:0]; // @[dcache.scala:130:36] wire [2:0] _state_T = {req_voluntary, 2'h0}; // @[dcache.scala:37:16, :133:19] wire _T_16 = state == 3'h4; // @[dcache.scala:39:22, :135:22] wire _T_2 = io_req_ready_0 & io_req_valid_0; // @[Decoupled.scala:51:35] wire _GEN_2 = (|state) & _T_3; // @[dcache.scala:39:22, :41:34, :49:31, :80:30, :88:{22,41}] wire _T_6 = io_data_req_ready_0 & io_data_req_valid_0 & io_meta_read_ready_0 & io_meta_read_valid_0; // @[Decoupled.scala:51:35] always @(posedge clock) begin // @[dcache.scala:24:7] if (~(|state) & _T_2) begin // @[Decoupled.scala:51:35] req_tag <= io_req_bits_tag_0; // @[dcache.scala:24:7, :37:16] req_idx <= io_req_bits_idx_0; // @[dcache.scala:24:7, :37:16] req_source <= io_req_bits_source_0; // @[dcache.scala:24:7, :37:16] req_param <= io_req_bits_param_0; // @[dcache.scala:24:7, :37:16] req_way_en <= io_req_bits_way_en_0; // @[dcache.scala:24:7, :37:16] req_voluntary <= io_req_bits_voluntary_0; // @[dcache.scala:24:7, :37:16] end if (_GEN_2) begin // @[dcache.scala:41:34, :43:28, :80:30, :88:41] r1_data_req_cnt <= _T_6 ? data_req_cnt : 4'h0; // @[Decoupled.scala:51:35] r2_data_req_cnt <= r1_data_req_cnt; // @[dcache.scala:42:28, :43:28] end if ((|state) & _T_3 & r2_data_req_fired & r2_data_req_cnt[2:0] == 3'h0) // @[dcache.scala:39:22, :41:34, :43:28, :46:22, :49:31, :80:30, :88:{22,41}, :108:30, :109:34] wb_buffer_0 <= io_data_resp_0; // @[dcache.scala:24:7, :46:22] if ((|state) & _T_3 & r2_data_req_fired & r2_data_req_cnt[2:0] == 3'h1) // @[dcache.scala:39:22, :41:34, :43:28, :46:22, :49:31, :80:30, :88:{22,41}, :108:30, :109:34] wb_buffer_1 <= io_data_resp_0; // @[dcache.scala:24:7, :46:22] if ((|state) & _T_3 & r2_data_req_fired & r2_data_req_cnt[2:0] == 3'h2) // @[dcache.scala:39:22, :41:34, :43:28, :46:22, :49:31, :80:30, :88:{22,41}, :108:30, :109:34] wb_buffer_2 <= io_data_resp_0; // @[dcache.scala:24:7, :46:22] if ((|state) & _T_3 & r2_data_req_fired & r2_data_req_cnt[2:0] == 3'h3) // @[dcache.scala:39:22, :41:34, :43:28, :46:22, :49:31, :80:30, :88:{22,41}, :108:30, :109:34] wb_buffer_3 <= io_data_resp_0; // @[dcache.scala:24:7, :46:22] if ((|state) & _T_3 & r2_data_req_fired & r2_data_req_cnt[2:0] == 3'h4) // @[dcache.scala:39:22, :41:34, :43:28, :46:22, :49:31, :80:30, :88:{22,41}, :108:30, :109:34] wb_buffer_4 <= io_data_resp_0; // @[dcache.scala:24:7, :46:22] if ((|state) & _T_3 & r2_data_req_fired & r2_data_req_cnt[2:0] == 3'h5) // @[dcache.scala:39:22, :41:34, :43:28, :46:22, :49:31, :80:30, :88:{22,41}, :108:30, :109:34] wb_buffer_5 <= io_data_resp_0; // @[dcache.scala:24:7, :46:22] if ((|state) & _T_3 & r2_data_req_fired & r2_data_req_cnt[2:0] == 3'h6) // @[dcache.scala:39:22, :41:34, :43:28, :46:22, :49:31, :80:30, :88:{22,41}, :108:30, :109:34] wb_buffer_6 <= io_data_resp_0; // @[dcache.scala:24:7, :46:22] if ((|state) & _T_3 & r2_data_req_fired & (&(r2_data_req_cnt[2:0]))) // @[dcache.scala:39:22, :41:34, :43:28, :46:22, :49:31, :80:30, :88:{22,41}, :108:30, :109:34] wb_buffer_7 <= io_data_resp_0; // @[dcache.scala:24:7, :46:22] if (reset) begin // @[dcache.scala:24:7] state <= 3'h0; // @[dcache.scala:39:22] r1_data_req_fired <= 1'h0; // @[dcache.scala:40:34] r2_data_req_fired <= 1'h0; // @[dcache.scala:41:34] data_req_cnt <= 4'h0; // @[dcache.scala:44:29] r_counter <= 9'h0; // @[Edges.scala:229:27] acked <= 1'h0; // @[dcache.scala:47:22] end else begin // @[dcache.scala:24:7] if (|state) begin // @[dcache.scala:39:22, :49:31] if (_T_3) begin // @[dcache.scala:88:22] if (r2_data_req_fired & _T_8) begin // @[dcache.scala:39:22, :41:34, :108:30, :110:{29,53}, :112:15] state <= 3'h2; // @[dcache.scala:39:22] data_req_cnt <= 4'h0; // @[dcache.scala:44:29] end else if (_T_6) // @[Decoupled.scala:51:35] data_req_cnt <= _data_req_cnt_T_1; // @[dcache.scala:44:29, :106:36] end else begin // @[dcache.scala:88:22] if (_T_9) begin // @[dcache.scala:116:22] if (io_lsu_release_ready_0 & io_lsu_release_valid_0) // @[Decoupled.scala:51:35] state <= 3'h3; // @[dcache.scala:39:22] end else if (_T_11) begin // @[dcache.scala:122:22] if (data_req_cnt == 4'h7 & _T_14) // @[Decoupled.scala:51:35] state <= _state_T; // @[dcache.scala:39:22, :133:19] end else if (_T_16 & acked) // @[dcache.scala:39:22, :47:22, :135:{22,35}, :139:18, :140:13] state <= 3'h0; // @[dcache.scala:39:22] if (_T_9 | ~(_T_11 & _T_14)) begin // @[Decoupled.scala:51:35] end else // @[dcache.scala:44:29, :116:41, :122:36] data_req_cnt <= _data_req_cnt_T_3; // @[dcache.scala:44:29, :130:36] end if (~_GEN_1) // @[dcache.scala:51:22, :88:41, :116:41, :122:36] acked <= _T_11 ? io_mem_grant_0 | acked : _T_16 & io_mem_grant_0 | acked; // @[dcache.scala:24:7, :47:22, :122:{22,36}, :126:25, :127:13, :135:{22,35}, :136:25, :137:13] end else begin // @[dcache.scala:49:31] if (_T_2) begin // @[Decoupled.scala:51:35] state <= 3'h1; // @[dcache.scala:39:22] data_req_cnt <= 4'h0; // @[dcache.scala:44:29] end acked <= ~_T_2 & acked; // @[Decoupled.scala:51:35] end if (_GEN_2) begin // @[dcache.scala:41:34, :80:30, :88:41] r1_data_req_fired <= _T_6; // @[Decoupled.scala:51:35] r2_data_req_fired <= r1_data_req_fired; // @[dcache.scala:40:34, :41:34] end if (_T_14) // @[Decoupled.scala:51:35] r_counter <= _r_counter_T; // @[Edges.scala:229:27, :236:21] end always @(posedge) assign io_req_ready = io_req_ready_0; // @[dcache.scala:24:7] assign io_meta_read_valid = io_meta_read_valid_0; // @[dcache.scala:24:7] assign io_meta_read_bits_idx = io_meta_read_bits_idx_0; // @[dcache.scala:24:7] assign io_meta_read_bits_tag = io_meta_read_bits_tag_0; // @[dcache.scala:24:7] assign io_resp = io_resp_0; // @[dcache.scala:24:7] assign io_idx_valid = io_idx_valid_0; // @[dcache.scala:24:7] assign io_idx_bits = io_idx_bits_0; // @[dcache.scala:24:7] assign io_data_req_valid = io_data_req_valid_0; // @[dcache.scala:24:7] assign io_data_req_bits_way_en = io_data_req_bits_way_en_0; // @[dcache.scala:24:7] assign io_data_req_bits_addr = io_data_req_bits_addr_0; // @[dcache.scala:24:7] assign io_release_valid = io_release_valid_0; // @[dcache.scala:24:7] assign io_release_bits_opcode = io_release_bits_opcode_0; // @[dcache.scala:24:7] assign io_release_bits_param = io_release_bits_param_0; // @[dcache.scala:24:7] assign io_release_bits_address = io_release_bits_address_0; // @[dcache.scala:24:7] assign io_release_bits_data = io_release_bits_data_0; // @[dcache.scala:24:7] assign io_lsu_release_valid = io_lsu_release_valid_0; // @[dcache.scala:24:7] assign io_lsu_release_bits_param = io_lsu_release_bits_param_0; // @[dcache.scala:24:7] assign io_lsu_release_bits_address = io_lsu_release_bits_address_0; // @[dcache.scala:24:7] assign io_lsu_release_bits_data = io_lsu_release_bits_data_0; // @[dcache.scala:24:7] endmodule

Generate the Verilog code corresponding to the following Chisel files. File Monitor.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceLine import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import freechips.rocketchip.diplomacy.EnableMonitors import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode} import freechips.rocketchip.util.PlusArg case class TLMonitorArgs(edge: TLEdge) abstract class TLMonitorBase(args: TLMonitorArgs) extends Module { val io = IO(new Bundle { val in = Input(new TLBundle(args.edge.bundle)) }) def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit legalize(io.in, args.edge, reset) } object TLMonitor { def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = { if (enable) { EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) } } else { node } } } class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args) { require (args.edge.params(TLMonitorStrictMode) || (! args.edge.params(TestplanTestType).formal)) val cover_prop_class = PropertyClass.Default //Like assert but can flip to being an assumption for formal verification def monAssert(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir, cond, message, PropertyClass.Default) } def assume(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir.flip, cond, message, PropertyClass.Default) } def extra = { args.edge.sourceInfo match { case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)" case _ => "" } } def visible(address: UInt, source: UInt, edge: TLEdge) = edge.client.clients.map { c => !c.sourceId.contains(source) || c.visibility.map(_.contains(address)).reduce(_ || _) }.reduce(_ && _) def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = { //switch this flag to turn on diplomacy in error messages def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n" monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra) // Reuse these subexpressions to save some firrtl lines val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility") //The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B //TODO: check for acquireT? when (bundle.opcode === TLMessages.AcquireBlock) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra) } when (bundle.opcode === TLMessages.AcquirePerm) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra) monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra) monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra) monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra) } } def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = { monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra) monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility") // Reuse these subexpressions to save some firrtl lines val address_ok = edge.manager.containsSafe(edge.address(bundle)) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source when (bundle.opcode === TLMessages.Probe) { assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra) assume (address_ok, "'B' channel Probe carries unmanaged address" + extra) assume (legal_source, "'B' channel Probe carries source that is not first source" + extra) assume (is_aligned, "'B' channel Probe address not aligned to size" + extra) assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra) assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra) assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra) monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra) monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra) monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra) monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra) } } def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = { monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val address_ok = edge.manager.containsSafe(edge.address(bundle)) monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility") when (bundle.opcode === TLMessages.ProbeAck) { monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra) } when (bundle.opcode === TLMessages.ProbeAckData) { monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.Release) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra) monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra) } when (bundle.opcode === TLMessages.ReleaseData) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.AccessAck) { monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra) } when (bundle.opcode === TLMessages.HintAck) { monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra) } } def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = { assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val sink_ok = bundle.sink < edge.manager.endSinkId.U val deny_put_ok = edge.manager.mayDenyPut.B val deny_get_ok = edge.manager.mayDenyGet.B when (bundle.opcode === TLMessages.ReleaseAck) { assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra) assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra) assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra) } when (bundle.opcode === TLMessages.Grant) { assume (source_ok, "'D' channel Grant carries invalid source ID" + extra) assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra) assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel Grant is denied" + extra) } when (bundle.opcode === TLMessages.GrantData) { assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra) assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra) assume (!bundle.denied || bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra) assume (deny_get_ok || !bundle.denied, "'D' channel GrantData is denied" + extra) } when (bundle.opcode === TLMessages.AccessAck) { assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel AccessAck is denied" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra) assume (!bundle.denied || bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra) assume (deny_get_ok || !bundle.denied, "'D' channel AccessAckData is denied" + extra) } when (bundle.opcode === TLMessages.HintAck) { assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel HintAck is denied" + extra) } } def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = { val sink_ok = bundle.sink < edge.manager.endSinkId.U monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra) } def legalizeFormat(bundle: TLBundle, edge: TLEdge) = { when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) } when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) } when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) } when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) } } else { monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra) monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra) monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra) } } def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = { val a_first = edge.first(a.bits, a.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (a.valid && !a_first) { monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra) monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra) monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra) monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra) monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra) } when (a.fire && a_first) { opcode := a.bits.opcode param := a.bits.param size := a.bits.size source := a.bits.source address := a.bits.address } } def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = { val b_first = edge.first(b.bits, b.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (b.valid && !b_first) { monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra) monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra) monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra) monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra) monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra) } when (b.fire && b_first) { opcode := b.bits.opcode param := b.bits.param size := b.bits.size source := b.bits.source address := b.bits.address } } def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = { // Symbolic variable val sym_source = Wire(UInt(edge.client.endSourceId.W)) // TODO: Connect sym_source to a fixed value for simulation and to a // free wire in formal sym_source := 0.U // Type casting Int to UInt val maxSourceId = Wire(UInt(edge.client.endSourceId.W)) maxSourceId := edge.client.endSourceId.U // Delayed verison of sym_source val sym_source_d = Reg(UInt(edge.client.endSourceId.W)) sym_source_d := sym_source // These will be constraints for FV setup Property( MonitorDirection.Monitor, (sym_source === sym_source_d), "sym_source should remain stable", PropertyClass.Default) Property( MonitorDirection.Monitor, (sym_source <= maxSourceId), "sym_source should take legal value", PropertyClass.Default) val my_resp_pend = RegInit(false.B) val my_opcode = Reg(UInt()) val my_size = Reg(UInt()) val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire) val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire) val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source) val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source) val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat) val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend) when (my_set_resp_pend) { my_resp_pend := true.B } .elsewhen (my_clr_resp_pend) { my_resp_pend := false.B } when (my_a_first_beat) { my_opcode := bundle.a.bits.opcode my_size := bundle.a.bits.size } val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size) val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode) val my_resp_opcode_legal = Wire(Bool()) when ((my_resp_opcode === TLMessages.Get) || (my_resp_opcode === TLMessages.ArithmeticData) || (my_resp_opcode === TLMessages.LogicalData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData) } .elsewhen ((my_resp_opcode === TLMessages.PutFullData) || (my_resp_opcode === TLMessages.PutPartialData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck) } .otherwise { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck) } monAssert (IfThen(my_resp_pend, !my_a_first_beat), "Request message should not be sent with a source ID, for which a response message" + "is already pending (not received until current cycle) for a prior request message" + "with the same source ID" + extra) assume (IfThen(my_clr_resp_pend, (my_set_resp_pend || my_resp_pend)), "Response message should be accepted with a source ID only if a request message with the" + "same source ID has been accepted or is being accepted in the current cycle" + extra) assume (IfThen(my_d_first_beat, (my_a_first_beat || my_resp_pend)), "Response message should be sent with a source ID only if a request message with the" + "same source ID has been accepted or is being sent in the current cycle" + extra) assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)), "If d_valid is 1, then d_size should be same as a_size of the corresponding request" + "message" + extra) assume (IfThen(my_d_first_beat, my_resp_opcode_legal), "If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" + "request message" + extra) } def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = { val c_first = edge.first(c.bits, c.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (c.valid && !c_first) { monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra) monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra) monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra) monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra) monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra) } when (c.fire && c_first) { opcode := c.bits.opcode param := c.bits.param size := c.bits.size source := c.bits.source address := c.bits.address } } def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = { val d_first = edge.first(d.bits, d.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val sink = Reg(UInt()) val denied = Reg(Bool()) when (d.valid && !d_first) { assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra) assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra) assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra) assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra) assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra) assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra) } when (d.fire && d_first) { opcode := d.bits.opcode param := d.bits.param size := d.bits.size source := d.bits.source sink := d.bits.sink denied := d.bits.denied } } def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = { legalizeMultibeatA(bundle.a, edge) legalizeMultibeatD(bundle.d, edge) if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { legalizeMultibeatB(bundle.b, edge) legalizeMultibeatC(bundle.c, edge) } } //This is left in for almond which doesn't adhere to the tilelink protocol @deprecated("Use legalizeADSource instead if possible","") def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.client.endSourceId.W)) val a_first = edge.first(bundle.a.bits, bundle.a.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val a_set = WireInit(0.U(edge.client.endSourceId.W)) when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) assume((a_set | inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra) } if (edge.manager.minLatency > 0) { assume(a_set =/= d_clr || !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight | a_set) & ~d_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") assert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = { val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size) val log_a_size_bus_size = log2Ceil(a_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error inflight.suggestName("inflight") val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) inflight_opcodes.suggestName("inflight_opcodes") val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) inflight_sizes.suggestName("inflight_sizes") val a_first = edge.first(bundle.a.bits, bundle.a.fire) a_first.suggestName("a_first") val d_first = edge.first(bundle.d.bits, bundle.d.fire) d_first.suggestName("d_first") val a_set = WireInit(0.U(edge.client.endSourceId.W)) val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) a_set.suggestName("a_set") a_set_wo_ready.suggestName("a_set_wo_ready") val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) a_opcodes_set.suggestName("a_opcodes_set") val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) a_sizes_set.suggestName("a_sizes_set") val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W)) a_opcode_lookup.suggestName("a_opcode_lookup") a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W)) a_size_lookup.suggestName("a_size_lookup") a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant)) val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant)) val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W)) a_opcodes_set_interm.suggestName("a_opcodes_set_interm") val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W)) a_sizes_set_interm.suggestName("a_sizes_set_interm") when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) { a_set_wo_ready := UIntToOH(bundle.a.bits.source) } when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) | 1.U a_sizes_set_interm := (bundle.a.bits.size << 1.U) | 1.U a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U) a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U) monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) d_opcodes_clr.suggestName("d_opcodes_clr") val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) || (bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra) assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) || (bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra) assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) { assume((!bundle.d.ready) || bundle.a.ready, "ready check") } if (edge.manager.minLatency > 0) { assume(a_set_wo_ready =/= d_clr_wo_ready || !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight | a_set) & ~d_clr inflight_opcodes := (inflight_opcodes | a_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes | a_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = { val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size) val log_c_size_bus_size = log2Ceil(c_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) inflight.suggestName("inflight") inflight_opcodes.suggestName("inflight_opcodes") inflight_sizes.suggestName("inflight_sizes") val c_first = edge.first(bundle.c.bits, bundle.c.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) c_first.suggestName("c_first") d_first.suggestName("d_first") val c_set = WireInit(0.U(edge.client.endSourceId.W)) val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) c_set.suggestName("c_set") c_set_wo_ready.suggestName("c_set_wo_ready") c_opcodes_set.suggestName("c_opcodes_set") c_sizes_set.suggestName("c_sizes_set") val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W)) val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W)) c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U c_opcode_lookup.suggestName("c_opcode_lookup") c_size_lookup.suggestName("c_size_lookup") val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W)) val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W)) c_opcodes_set_interm.suggestName("c_opcodes_set_interm") c_sizes_set_interm.suggestName("c_sizes_set_interm") when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) { c_set_wo_ready := UIntToOH(bundle.c.bits.source) } when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) { c_set := UIntToOH(bundle.c.bits.source) c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) | 1.U c_sizes_set_interm := (bundle.c.bits.size << 1.U) | 1.U c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U) c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U) monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra) } val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck || bundle.c.bits.opcode === TLMessages.ProbeAckData val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") d_opcodes_clr.suggestName("d_opcodes_clr") d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) { assume((!bundle.d.ready) || bundle.c.ready, "ready check") } if (edge.manager.minLatency > 0) { when (c_set_wo_ready.orR) { assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra) } } inflight := (inflight | c_set) & ~d_clr inflight_opcodes := (inflight_opcodes | c_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes | c_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.c.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.manager.endSinkId.W)) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val e_first = true.B val d_set = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) { d_set := UIntToOH(bundle.d.bits.sink) assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra) } val e_clr = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) { e_clr := UIntToOH(bundle.e.bits.sink) monAssert((d_set | inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra) } // edge.client.minLatency applies to BC, not DE inflight := (inflight | d_set) & ~e_clr } def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = { val sourceBits = log2Ceil(edge.client.endSourceId) val tooBig = 14 // >16kB worth of flight information gets to be too much if (sourceBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked") } else { if (args.edge.params(TestplanTestType).simulation) { if (args.edge.params(TLMonitorStrictMode)) { legalizeADSource(bundle, edge) legalizeCDSource(bundle, edge) } else { legalizeADSourceOld(bundle, edge) } } if (args.edge.params(TestplanTestType).formal) { legalizeADSourceFormal(bundle, edge) } } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { // legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize... val sinkBits = log2Ceil(edge.manager.endSinkId) if (sinkBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked") } else { legalizeDESink(bundle, edge) } } } def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = { legalizeFormat (bundle, edge) legalizeMultibeat (bundle, edge) legalizeUnique (bundle, edge) } } File Misc.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import scala.math._ class ParameterizedBundle(implicit p: Parameters) extends Bundle trait Clocked extends Bundle { val clock = Clock() val reset = Bool() } object DecoupledHelper { def apply(rvs: Bool*) = new DecoupledHelper(rvs) } class DecoupledHelper(val rvs: Seq[Bool]) { def fire(exclude: Bool, includes: Bool*) = { require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!") (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _) } def fire() = { rvs.reduce(_ && _) } } object MuxT { def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2)) def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3)) def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4)) } /** Creates a cascade of n MuxTs to search for a key value. */ object MuxTLookup { def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } } object ValidMux { def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]*): ValidIO[T] = { apply(v1 +: v2.toSeq) } def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = { val out = Wire(Valid(valids.head.bits.cloneType)) out.valid := valids.map(_.valid).reduce(_ || _) out.bits := MuxCase(valids.head.bits, valids.map(v => (v.valid -> v.bits))) out } } object Str { def apply(s: String): UInt = { var i = BigInt(0) require(s.forall(validChar _)) for (c <- s) i = (i << 8) | c i.U((s.length*8).W) } def apply(x: Char): UInt = { require(validChar(x)) x.U(8.W) } def apply(x: UInt): UInt = apply(x, 10) def apply(x: UInt, radix: Int): UInt = { val rad = radix.U val w = x.getWidth require(w > 0) var q = x var s = digit(q % rad) for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s) } s } def apply(x: SInt): UInt = apply(x, 10) def apply(x: SInt, radix: Int): UInt = { val neg = x < 0.S val abs = x.abs.asUInt if (radix != 10) { Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix)) } else { val rad = radix.U val w = abs.getWidth require(w > 0) var q = abs var s = digit(q % rad) var needSign = neg for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad val placeSpace = q === 0.U val space = Mux(needSign, Str('-'), Str(' ')) needSign = needSign && !placeSpace s = Cat(Mux(placeSpace, space, digit(q % rad)), s) } Cat(Mux(needSign, Str('-'), Str(' ')), s) } } private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0) private def validChar(x: Char) = x == (x & 0xFF) } object Split { def apply(x: UInt, n0: Int) = { val w = x.getWidth (x.extract(w-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n2: Int, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } } object Random { def apply(mod: Int, random: UInt): UInt = { if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0) else PriorityEncoder(partition(apply(1 << log2Up(mod*8), random), mod)) } def apply(mod: Int): UInt = apply(mod, randomizer) def oneHot(mod: Int, random: UInt): UInt = { if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0)) else PriorityEncoderOH(partition(apply(1 << log2Up(mod*8), random), mod)).asUInt } def oneHot(mod: Int): UInt = oneHot(mod, randomizer) private def randomizer = LFSR(16) private def partition(value: UInt, slices: Int) = Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U) } object Majority { def apply(in: Set[Bool]): Bool = { val n = (in.size >> 1) + 1 val clauses = in.subsets(n).map(_.reduce(_ && _)) clauses.reduce(_ || _) } def apply(in: Seq[Bool]): Bool = apply(in.toSet) def apply(in: UInt): Bool = apply(in.asBools.toSet) } object PopCountAtLeast { private def two(x: UInt): (Bool, Bool) = x.getWidth match { case 1 => (x.asBool, false.B) case n => val half = x.getWidth / 2 val (leftOne, leftTwo) = two(x(half - 1, 0)) val (rightOne, rightTwo) = two(x(x.getWidth - 1, half)) (leftOne || rightOne, leftTwo || rightTwo || (leftOne && rightOne)) } def apply(x: UInt, n: Int): Bool = n match { case 0 => true.B case 1 => x.orR case 2 => two(x)._2 case 3 => PopCount(x) >= n.U } } // This gets used everywhere, so make the smallest circuit possible ... // Given an address and size, create a mask of beatBytes size // eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111 // groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01 object MaskGen { def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = { require (groupBy >= 1 && beatBytes >= groupBy) require (isPow2(beatBytes) && isPow2(groupBy)) val lgBytes = log2Ceil(beatBytes) val sizeOH = UIntToOH(lgSize | 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) | (groupBy*2 - 1).U def helper(i: Int): Seq[(Bool, Bool)] = { if (i == 0) { Seq((lgSize >= lgBytes.asUInt, true.B)) } else { val sub = helper(i-1) val size = sizeOH(lgBytes - i) val bit = addr_lo(lgBytes - i) val nbit = !bit Seq.tabulate (1 << i) { j => val (sub_acc, sub_eq) = sub(j/2) val eq = sub_eq && (if (j % 2 == 1) bit else nbit) val acc = sub_acc || (size && eq) (acc, eq) } } } if (groupBy == beatBytes) 1.U else Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse) } } File PlusArg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.experimental._ import chisel3.util.HasBlackBoxResource @deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05") case class PlusArgInfo(default: BigInt, docstring: String) /** Case class for PlusArg information * * @tparam A scala type of the PlusArg value * @param default optional default value * @param docstring text to include in the help * @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT) */ private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String) /** Typeclass for converting a type to a doctype string * @tparam A some type */ trait Doctypeable[A] { /** Return the doctype string for some option */ def toDoctype(a: Option[A]): String } /** Object containing implementations of the Doctypeable typeclass */ object Doctypes { /** Converts an Int => "INT" */ implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" } /** Converts a BigInt => "INT" */ implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" } /** Converts a String => "STRING" */ implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" } } class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map( "FORMAT" -> StringParam(format), "DEFAULT" -> IntParam(default), "WIDTH" -> IntParam(width) )) with HasBlackBoxResource { val io = IO(new Bundle { val out = Output(UInt(width.W)) }) addResource("/vsrc/plusarg_reader.v") } /* This wrapper class has no outputs, making it clear it is a simulation-only construct */ class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module { val io = IO(new Bundle { val count = Input(UInt(width.W)) }) val max = Module(new plusarg_reader(format, default, docstring, width)).io.out when (max > 0.U) { assert (io.count < max, s"Timeout exceeded: $docstring") } } import Doctypes._ object PlusArg { /** PlusArg("foo") will return 42.U if the simulation is run with +foo=42 * Do not use this as an initial register value. The value is set in an * initial block and thus accessing it from another initial is racey. * Add a docstring to document the arg, which can be dumped in an elaboration * pass. */ def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out } /** PlusArg.timeout(name, default, docstring)(count) will use chisel.assert * to kill the simulation when count exceeds the specified integer argument. * Default 0 will never assert. */ def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count } } object PlusArgArtefacts { private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty /* Add a new PlusArg */ @deprecated( "Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05" ) def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring) /** Add a new PlusArg * * @tparam A scala type of the PlusArg value * @param name name for the PlusArg * @param default optional default value * @param docstring text to include in the help */ def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit = artefacts = artefacts ++ Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default))) /* From plus args, generate help text */ private def serializeHelp_cHeader(tab: String = ""): String = artefacts .map{ case(arg, info) => s"""|$tab+$arg=${info.doctype}\\n\\ |$tab${" "*20}${info.docstring}\\n\\ |""".stripMargin ++ info.default.map{ case default => s"$tab${" "*22}(default=${default})\\n\\\n"}.getOrElse("") }.toSeq.mkString("\\n\\\n") ++ "\"" /* From plus args, generate a char array of their names */ private def serializeArray_cHeader(tab: String = ""): String = { val prettyTab = tab + " " * 44 // Length of 'static const ...' s"${tab}static const char * verilog_plusargs [] = {\\\n" ++ artefacts .map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" } .mkString("")++ s"${prettyTab}0};" } /* Generate C code to be included in emulator.cc that helps with * argument parsing based on available Verilog PlusArgs */ def serialize_cHeader(): String = s"""|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\ |${serializeHelp_cHeader(" "*7)} |${serializeArray_cHeader()} |""".stripMargin } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /** Like Vec.apply(idx), but tolerates indices of mismatched width */ def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /** Any Data subtype that has a Bool member named valid. */ type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /** converts from camel case to to underscores, also removing all spaces */ def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /** converts spaces or underscores to hyphens, also lowering case */ def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y | (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y || y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /** Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation */ def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Bundles.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import freechips.rocketchip.util._ import scala.collection.immutable.ListMap import chisel3.util.Decoupled import chisel3.util.DecoupledIO import chisel3.reflect.DataMirror abstract class TLBundleBase(val params: TLBundleParameters) extends Bundle // common combos in lazy policy: // Put + Acquire // Release + AccessAck object TLMessages { // A B C D E def PutFullData = 0.U // . . => AccessAck def PutPartialData = 1.U // . . => AccessAck def ArithmeticData = 2.U // . . => AccessAckData def LogicalData = 3.U // . . => AccessAckData def Get = 4.U // . . => AccessAckData def Hint = 5.U // . . => HintAck def AcquireBlock = 6.U // . => Grant[Data] def AcquirePerm = 7.U // . => Grant[Data] def Probe = 6.U // . => ProbeAck[Data] def AccessAck = 0.U // . . def AccessAckData = 1.U // . . def HintAck = 2.U // . . def ProbeAck = 4.U // . def ProbeAckData = 5.U // . def Release = 6.U // . => ReleaseAck def ReleaseData = 7.U // . => ReleaseAck def Grant = 4.U // . => GrantAck def GrantData = 5.U // . => GrantAck def ReleaseAck = 6.U // . def GrantAck = 0.U // . def isA(x: UInt) = x <= AcquirePerm def isB(x: UInt) = x <= Probe def isC(x: UInt) = x <= ReleaseData def isD(x: UInt) = x <= ReleaseAck def adResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, Grant, Grant) def bcResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, ProbeAck, ProbeAck) def a = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("AcquireBlock",TLPermissions.PermMsgGrow), ("AcquirePerm",TLPermissions.PermMsgGrow)) def b = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("Probe",TLPermissions.PermMsgCap)) def c = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("ProbeAck",TLPermissions.PermMsgReport), ("ProbeAckData",TLPermissions.PermMsgReport), ("Release",TLPermissions.PermMsgReport), ("ReleaseData",TLPermissions.PermMsgReport)) def d = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("Grant",TLPermissions.PermMsgCap), ("GrantData",TLPermissions.PermMsgCap), ("ReleaseAck",TLPermissions.PermMsgReserved)) } /** * The three primary TileLink permissions are: * (T)runk: the agent is (or is on inwards path to) the global point of serialization. * (B)ranch: the agent is on an outwards path to * (N)one: * These permissions are permuted by transfer operations in various ways. * Operations can cap permissions, request for them to be grown or shrunk, * or for a report on their current status. */ object TLPermissions { val aWidth = 2 val bdWidth = 2 val cWidth = 3 // Cap types (Grant = new permissions, Probe = permisions <= target) def toT = 0.U(bdWidth.W) def toB = 1.U(bdWidth.W) def toN = 2.U(bdWidth.W) def isCap(x: UInt) = x <= toN // Grow types (Acquire = permissions >= target) def NtoB = 0.U(aWidth.W) def NtoT = 1.U(aWidth.W) def BtoT = 2.U(aWidth.W) def isGrow(x: UInt) = x <= BtoT // Shrink types (ProbeAck, Release) def TtoB = 0.U(cWidth.W) def TtoN = 1.U(cWidth.W) def BtoN = 2.U(cWidth.W) def isShrink(x: UInt) = x <= BtoN // Report types (ProbeAck, Release) def TtoT = 3.U(cWidth.W) def BtoB = 4.U(cWidth.W) def NtoN = 5.U(cWidth.W) def isReport(x: UInt) = x <= NtoN def PermMsgGrow:Seq[String] = Seq("Grow NtoB", "Grow NtoT", "Grow BtoT") def PermMsgCap:Seq[String] = Seq("Cap toT", "Cap toB", "Cap toN") def PermMsgReport:Seq[String] = Seq("Shrink TtoB", "Shrink TtoN", "Shrink BtoN", "Report TotT", "Report BtoB", "Report NtoN") def PermMsgReserved:Seq[String] = Seq("Reserved") } object TLAtomics { val width = 3 // Arithmetic types def MIN = 0.U(width.W) def MAX = 1.U(width.W) def MINU = 2.U(width.W) def MAXU = 3.U(width.W) def ADD = 4.U(width.W) def isArithmetic(x: UInt) = x <= ADD // Logical types def XOR = 0.U(width.W) def OR = 1.U(width.W) def AND = 2.U(width.W) def SWAP = 3.U(width.W) def isLogical(x: UInt) = x <= SWAP def ArithMsg:Seq[String] = Seq("MIN", "MAX", "MINU", "MAXU", "ADD") def LogicMsg:Seq[String] = Seq("XOR", "OR", "AND", "SWAP") } object TLHints { val width = 1 def PREFETCH_READ = 0.U(width.W) def PREFETCH_WRITE = 1.U(width.W) def isHints(x: UInt) = x <= PREFETCH_WRITE def HintsMsg:Seq[String] = Seq("PrefetchRead", "PrefetchWrite") } sealed trait TLChannel extends TLBundleBase { val channelName: String } sealed trait TLDataChannel extends TLChannel sealed trait TLAddrChannel extends TLDataChannel final class TLBundleA(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleA_${params.shortName}" val channelName = "'A' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(List(TLAtomics.width, TLPermissions.aWidth, TLHints.width).max.W) // amo_opcode || grow perms || hint val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleB(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleB_${params.shortName}" val channelName = "'B' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val address = UInt(params.addressBits.W) // from // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleC(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleC_${params.shortName}" val channelName = "'C' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.cWidth.W) // shrink or report perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleD(params: TLBundleParameters) extends TLBundleBase(params) with TLDataChannel { override def typeName = s"TLBundleD_${params.shortName}" val channelName = "'D' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val sink = UInt(params.sinkBits.W) // from val denied = Bool() // implies corrupt iff *Data val user = BundleMap(params.responseFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleE(params: TLBundleParameters) extends TLBundleBase(params) with TLChannel { override def typeName = s"TLBundleE_${params.shortName}" val channelName = "'E' channel" val sink = UInt(params.sinkBits.W) // to } class TLBundle(val params: TLBundleParameters) extends Record { // Emulate a Bundle with elements abcde or ad depending on params.hasBCE private val optA = Some (Decoupled(new TLBundleA(params))) private val optB = params.hasBCE.option(Flipped(Decoupled(new TLBundleB(params)))) private val optC = params.hasBCE.option(Decoupled(new TLBundleC(params))) private val optD = Some (Flipped(Decoupled(new TLBundleD(params)))) private val optE = params.hasBCE.option(Decoupled(new TLBundleE(params))) def a: DecoupledIO[TLBundleA] = optA.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleA(params))))) def b: DecoupledIO[TLBundleB] = optB.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleB(params))))) def c: DecoupledIO[TLBundleC] = optC.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleC(params))))) def d: DecoupledIO[TLBundleD] = optD.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleD(params))))) def e: DecoupledIO[TLBundleE] = optE.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleE(params))))) val elements = if (params.hasBCE) ListMap("e" -> e, "d" -> d, "c" -> c, "b" -> b, "a" -> a) else ListMap("d" -> d, "a" -> a) def tieoff(): Unit = { DataMirror.specifiedDirectionOf(a.ready) match { case SpecifiedDirection.Input => a.ready := false.B c.ready := false.B e.ready := false.B b.valid := false.B d.valid := false.B case SpecifiedDirection.Output => a.valid := false.B c.valid := false.B e.valid := false.B b.ready := false.B d.ready := false.B case _ => } } } object TLBundle { def apply(params: TLBundleParameters) = new TLBundle(params) } class TLAsyncBundleBase(val params: TLAsyncBundleParameters) extends Bundle class TLAsyncBundle(params: TLAsyncBundleParameters) extends TLAsyncBundleBase(params) { val a = new AsyncBundle(new TLBundleA(params.base), params.async) val b = Flipped(new AsyncBundle(new TLBundleB(params.base), params.async)) val c = new AsyncBundle(new TLBundleC(params.base), params.async) val d = Flipped(new AsyncBundle(new TLBundleD(params.base), params.async)) val e = new AsyncBundle(new TLBundleE(params.base), params.async) } class TLRationalBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = RationalIO(new TLBundleA(params)) val b = Flipped(RationalIO(new TLBundleB(params))) val c = RationalIO(new TLBundleC(params)) val d = Flipped(RationalIO(new TLBundleD(params))) val e = RationalIO(new TLBundleE(params)) } class TLCreditedBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = CreditedIO(new TLBundleA(params)) val b = Flipped(CreditedIO(new TLBundleB(params))) val c = CreditedIO(new TLBundleC(params)) val d = Flipped(CreditedIO(new TLBundleD(params))) val e = CreditedIO(new TLBundleE(params)) } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.diplomacy import chisel3._ import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor} import freechips.rocketchip.util.ShiftQueue /** Options for describing the attributes of memory regions */ object RegionType { // Define the 'more relaxed than' ordering val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS) sealed trait T extends Ordered[T] { def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this) } case object CACHED extends T // an intermediate agent may have cached a copy of the region for you case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively } // A non-empty half-open range; [start, end) case class IdRange(start: Int, end: Int) extends Ordered[IdRange] { require (start >= 0, s"Ids cannot be negative, but got: $start.") require (start <= end, "Id ranges cannot be negative.") def compare(x: IdRange) = { val primary = (this.start - x.start).signum val secondary = (x.end - this.end).signum if (primary != 0) primary else secondary } def overlaps(x: IdRange) = start < x.end && x.start < end def contains(x: IdRange) = start <= x.start && x.end <= end def contains(x: Int) = start <= x && x < end def contains(x: UInt) = if (size == 0) { false.B } else if (size == 1) { // simple comparison x === start.U } else { // find index of largest different bit val largestDeltaBit = log2Floor(start ^ (end-1)) val smallestCommonBit = largestDeltaBit + 1 // may not exist in x val uncommonMask = (1 << smallestCommonBit) - 1 val uncommonBits = (x | 0.U(smallestCommonBit.W))(largestDeltaBit, 0) // the prefix must match exactly (note: may shift ALL bits away) (x >> smallestCommonBit) === (start >> smallestCommonBit).U && // firrtl constant prop range analysis can eliminate these two: (start & uncommonMask).U <= uncommonBits && uncommonBits <= ((end-1) & uncommonMask).U } def shift(x: Int) = IdRange(start+x, end+x) def size = end - start def isEmpty = end == start def range = start until end } object IdRange { def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else { val ranges = s.sorted (ranges.tail zip ranges.init) find { case (a, b) => a overlaps b } } } // An potentially empty inclusive range of 2-powers [min, max] (in bytes) case class TransferSizes(min: Int, max: Int) { def this(x: Int) = this(x, x) require (min <= max, s"Min transfer $min > max transfer $max") require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)") require (max == 0 || isPow2(max), s"TransferSizes must be a power of 2, got: $max") require (min == 0 || isPow2(min), s"TransferSizes must be a power of 2, got: $min") require (max == 0 || min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)") def none = min == 0 def contains(x: Int) = isPow2(x) && min <= x && x <= max def containsLg(x: Int) = contains(1 << x) def containsLg(x: UInt) = if (none) false.B else if (min == max) { log2Ceil(min).U === x } else { log2Ceil(min).U <= x && x <= log2Ceil(max).U } def contains(x: TransferSizes) = x.none || (min <= x.min && x.max <= max) def intersect(x: TransferSizes) = if (x.max < min || max < x.min) TransferSizes.none else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max)) // Not a union, because the result may contain sizes contained by neither term // NOT TO BE CONFUSED WITH COVERPOINTS def mincover(x: TransferSizes) = { if (none) { x } else if (x.none) { this } else { TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max)) } } override def toString() = "TransferSizes[%d, %d]".format(min, max) } object TransferSizes { def apply(x: Int) = new TransferSizes(x) val none = new TransferSizes(0) def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _) def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _) implicit def asBool(x: TransferSizes) = !x.none } // AddressSets specify the address space managed by the manager // Base is the base address, and mask are the bits consumed by the manager // e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff // e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ... case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet] { // Forbid misaligned base address (and empty sets) require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}") require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous // We do allow negative mask (=> ignore all high bits) def contains(x: BigInt) = ((x ^ base) & ~mask) == 0 def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S // turn x into an address contained in this set def legalize(x: UInt): UInt = base.U | (mask.U & x) // overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1) def overlaps(x: AddressSet) = (~(mask | x.mask) & (base ^ x.base)) == 0 // contains iff bitwise: x.mask => mask && contains(x.base) def contains(x: AddressSet) = ((x.mask | (base ^ x.base)) & ~mask) == 0 // The number of bytes to which the manager must be aligned def alignment = ((mask + 1) & ~mask) // Is this a contiguous memory range def contiguous = alignment == mask+1 def finite = mask >= 0 def max = { require (finite, "Max cannot be calculated on infinite mask"); base | mask } // Widen the match function to ignore all bits in imask def widen(imask: BigInt) = AddressSet(base & ~imask, mask | imask) // Return an AddressSet that only contains the addresses both sets contain def intersect(x: AddressSet): Option[AddressSet] = { if (!overlaps(x)) { None } else { val r_mask = mask & x.mask val r_base = base | x.base Some(AddressSet(r_base, r_mask)) } } def subtract(x: AddressSet): Seq[AddressSet] = { intersect(x) match { case None => Seq(this) case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit => val nmask = (mask & (bit-1)) | remove.mask val nbase = (remove.base ^ bit) & ~nmask AddressSet(nbase, nmask) } } } // AddressSets have one natural Ordering (the containment order, if contiguous) def compare(x: AddressSet) = { val primary = (this.base - x.base).signum // smallest address first val secondary = (x.mask - this.mask).signum // largest mask first if (primary != 0) primary else secondary } // We always want to see things in hex override def toString() = { if (mask >= 0) { "AddressSet(0x%x, 0x%x)".format(base, mask) } else { "AddressSet(0x%x, ~0x%x)".format(base, ~mask) } } def toRanges = { require (finite, "Ranges cannot be calculated on infinite mask") val size = alignment val fragments = mask & ~(size-1) val bits = bitIndexes(fragments) (BigInt(0) until (BigInt(1) << bits.size)).map { i => val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) } AddressRange(off, size) } } } object AddressSet { val everything = AddressSet(0, -1) def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = { if (size == 0) tail.reverse else { val maxBaseAlignment = base & (-base) // 0 for infinite (LSB) val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size val step = if (maxBaseAlignment == 0 || maxBaseAlignment > maxSizeAlignment) maxSizeAlignment else maxBaseAlignment misaligned(base+step, size-step, AddressSet(base, step-1) +: tail) } } def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = { // Pair terms up by ignoring 'bit' seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) => if (seq.size == 1) { seq.head // singleton -> unaffected } else { key.copy(mask = key.mask | bit) // pair - widen mask by bit } }.toList } def unify(seq: Seq[AddressSet]): Seq[AddressSet] = { val bits = seq.map(_.base).foldLeft(BigInt(0))(_ | _) AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted } def enumerateMask(mask: BigInt): Seq[BigInt] = { def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] = if (id == mask) (id +: tail).reverse else helper(((~mask | id) + 1) & mask, id +: tail) helper(0, Nil) } def enumerateBits(mask: BigInt): Seq[BigInt] = { def helper(x: BigInt): Seq[BigInt] = { if (x == 0) { Nil } else { val bit = x & (-x) bit +: helper(x & ~bit) } } helper(mask) } } case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean) { require (depth >= 0, "Buffer depth must be >= 0") def isDefined = depth > 0 def latency = if (isDefined && !flow) 1 else 0 def apply[T <: Data](x: DecoupledIO[T]) = if (isDefined) Queue(x, depth, flow=flow, pipe=pipe) else x def irrevocable[T <: Data](x: ReadyValidIO[T]) = if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe) else x def sq[T <: Data](x: DecoupledIO[T]) = if (!isDefined) x else { val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe)) sq.io.enq <> x sq.io.deq } override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "") } object BufferParams { implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false) val default = BufferParams(2) val none = BufferParams(0) val flow = BufferParams(1, true, false) val pipe = BufferParams(1, false, true) } case class TriStateValue(value: Boolean, set: Boolean) { def update(orig: Boolean) = if (set) value else orig } object TriStateValue { implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true) def unset = TriStateValue(false, false) } trait DirectedBuffers[T] { def copyIn(x: BufferParams): T def copyOut(x: BufferParams): T def copyInOut(x: BufferParams): T } trait IdMapEntry { def name: String def from: IdRange def to: IdRange def isCache: Boolean def requestFifo: Boolean def maxTransactionsInFlight: Option[Int] def pretty(fmt: String) = if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5 fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } else { fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } } abstract class IdMap[T <: IdMapEntry] { protected val fmt: String val mapping: Seq[T] def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n") } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) || !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.ProbeAckData || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode | small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U || beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }

module TLMonitor_59( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [1:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [8:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [27:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [8:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [1:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [8:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [27:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [8:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_sink = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_denied = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire _source_ok_T = 1'h0; // @[Parameters.scala:54:10] wire _source_ok_T_6 = 1'h0; // @[Parameters.scala:54:10] wire sink_ok = 1'h0; // @[Monitor.scala:309:31] wire a_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire a_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire a_first_count = 1'h0; // @[Edges.scala:234:25] wire d_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire d_first_count = 1'h0; // @[Edges.scala:234:25] wire a_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59] wire a_first_beats1_1 = 1'h0; // @[Edges.scala:221:14] wire a_first_count_1 = 1'h0; // @[Edges.scala:234:25] wire d_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1_1 = 1'h0; // @[Edges.scala:221:14] wire d_first_count_1 = 1'h0; // @[Edges.scala:234:25] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire c_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_first_count_T = 1'h0; // @[Edges.scala:234:27] wire c_first_count = 1'h0; // @[Edges.scala:234:25] wire _c_first_counter_T = 1'h0; // @[Edges.scala:236:21] wire d_first_beats1_decode_2 = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1_2 = 1'h0; // @[Edges.scala:221:14] wire d_first_count_2 = 1'h0; // @[Edges.scala:234:25] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire _source_ok_T_1 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:54:67] wire _source_ok_T_7 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_8 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:54:67] wire _a_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire a_first_last = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire d_first_last = 1'h1; // @[Edges.scala:232:33] wire _a_first_last_T_3 = 1'h1; // @[Edges.scala:232:43] wire a_first_last_1 = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_3 = 1'h1; // @[Edges.scala:232:43] wire d_first_last_1 = 1'h1; // @[Edges.scala:232:33] wire c_first_counter1 = 1'h1; // @[Edges.scala:230:28] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_5 = 1'h1; // @[Edges.scala:232:43] wire d_first_last_2 = 1'h1; // @[Edges.scala:232:33] wire [1:0] _c_first_counter1_T = 2'h3; // @[Edges.scala:230:28] wire [1:0] io_in_d_bits_param = 2'h0; // @[Monitor.scala:36:7] wire [1:0] _c_first_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_first_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_first_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_first_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_set_wo_ready_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_set_wo_ready_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_opcodes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_opcodes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_sizes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_sizes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_opcodes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_opcodes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_sizes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_sizes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_probe_ack_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_probe_ack_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_probe_ack_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_probe_ack_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_4_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_5_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [27:0] _c_first_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_first_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_first_WIRE_2_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_first_WIRE_3_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_set_wo_ready_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_set_wo_ready_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_set_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_set_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_opcodes_set_interm_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_opcodes_set_interm_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_sizes_set_interm_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_sizes_set_interm_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_opcodes_set_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_opcodes_set_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_sizes_set_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_sizes_set_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_probe_ack_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_probe_ack_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_probe_ack_WIRE_2_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_probe_ack_WIRE_3_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _same_cycle_resp_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _same_cycle_resp_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _same_cycle_resp_WIRE_2_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _same_cycle_resp_WIRE_3_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _same_cycle_resp_WIRE_4_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _same_cycle_resp_WIRE_5_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [8:0] _c_first_WIRE_bits_source = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _c_first_WIRE_1_bits_source = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _c_first_WIRE_2_bits_source = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _c_first_WIRE_3_bits_source = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _c_set_wo_ready_WIRE_bits_source = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _c_set_wo_ready_WIRE_1_bits_source = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _c_set_WIRE_bits_source = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _c_set_WIRE_1_bits_source = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _c_opcodes_set_interm_WIRE_bits_source = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _c_opcodes_set_interm_WIRE_1_bits_source = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _c_sizes_set_interm_WIRE_bits_source = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _c_sizes_set_interm_WIRE_1_bits_source = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _c_opcodes_set_WIRE_bits_source = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _c_opcodes_set_WIRE_1_bits_source = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _c_sizes_set_WIRE_bits_source = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _c_sizes_set_WIRE_1_bits_source = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _c_probe_ack_WIRE_bits_source = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _c_probe_ack_WIRE_1_bits_source = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _c_probe_ack_WIRE_2_bits_source = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _c_probe_ack_WIRE_3_bits_source = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _same_cycle_resp_WIRE_bits_source = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _same_cycle_resp_WIRE_1_bits_source = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _same_cycle_resp_WIRE_2_bits_source = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _same_cycle_resp_WIRE_3_bits_source = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _same_cycle_resp_WIRE_4_bits_source = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _same_cycle_resp_WIRE_5_bits_source = 9'h0; // @[Bundles.scala:265:61] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_beats1_decode_T_2 = 3'h0; // @[package.scala:243:46] wire [2:0] c_sizes_set_interm = 3'h0; // @[Monitor.scala:755:40] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_T = 3'h0; // @[Monitor.scala:766:51] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [4097:0] _c_sizes_set_T_1 = 4098'h0; // @[Monitor.scala:768:52] wire [11:0] _c_opcodes_set_T = 12'h0; // @[Monitor.scala:767:79] wire [11:0] _c_sizes_set_T = 12'h0; // @[Monitor.scala:768:77] wire [4098:0] _c_opcodes_set_T_1 = 4099'h0; // @[Monitor.scala:767:54] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] _c_sizes_set_interm_T_1 = 3'h1; // @[Monitor.scala:766:59] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [511:0] _c_set_wo_ready_T = 512'h1; // @[OneHot.scala:58:35] wire [511:0] _c_set_T = 512'h1; // @[OneHot.scala:58:35] wire [1279:0] c_opcodes_set = 1280'h0; // @[Monitor.scala:740:34] wire [1279:0] c_sizes_set = 1280'h0; // @[Monitor.scala:741:34] wire [319:0] c_set = 320'h0; // @[Monitor.scala:738:34] wire [319:0] c_set_wo_ready = 320'h0; // @[Monitor.scala:739:34] wire [2:0] _c_first_beats1_decode_T_1 = 3'h7; // @[package.scala:243:76] wire [5:0] _c_first_beats1_decode_T = 6'h7; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48] wire [8:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _source_ok_uncommonBits_T_1 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] source_ok_uncommonBits = _source_ok_uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_4 = source_ok_uncommonBits < 9'h140; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_5 = _source_ok_T_4; // @[Parameters.scala:56:48, :57:20] wire _source_ok_WIRE_0 = _source_ok_T_5; // @[Parameters.scala:1138:31] wire [5:0] _GEN = 6'h7 << io_in_a_bits_size_0; // @[package.scala:243:71] wire [5:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [5:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [5:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [2:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[2:0]; // @[package.scala:243:{71,76}] wire [2:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [27:0] _is_aligned_T = {25'h0, io_in_a_bits_address_0[2:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 28'h0; // @[Edges.scala:21:{16,24}] wire [2:0] _mask_sizeOH_T = {1'h0, io_in_a_bits_size_0}; // @[Misc.scala:202:34] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = &io_in_a_bits_size_0; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [8:0] uncommonBits = _uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire [8:0] uncommonBits_1 = _uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire [8:0] uncommonBits_2 = _uncommonBits_T_2; // @[Parameters.scala:52:{29,56}] wire [8:0] uncommonBits_3 = _uncommonBits_T_3; // @[Parameters.scala:52:{29,56}] wire [8:0] uncommonBits_4 = _uncommonBits_T_4; // @[Parameters.scala:52:{29,56}] wire [8:0] uncommonBits_5 = _uncommonBits_T_5; // @[Parameters.scala:52:{29,56}] wire [8:0] uncommonBits_6 = _uncommonBits_T_6; // @[Parameters.scala:52:{29,56}] wire [8:0] uncommonBits_7 = _uncommonBits_T_7; // @[Parameters.scala:52:{29,56}] wire [8:0] uncommonBits_8 = _uncommonBits_T_8; // @[Parameters.scala:52:{29,56}] wire [8:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_10 = source_ok_uncommonBits_1 < 9'h140; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_11 = _source_ok_T_10; // @[Parameters.scala:56:48, :57:20] wire _source_ok_WIRE_1_0 = _source_ok_T_11; // @[Parameters.scala:1138:31] wire _T_672 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_672; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_672; // @[Decoupled.scala:51:35] wire a_first_done = _a_first_T; // @[Decoupled.scala:51:35] wire [2:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] reg a_first_counter; // @[Edges.scala:229:27] wire _a_first_last_T = a_first_counter; // @[Edges.scala:229:27, :232:25] wire [1:0] _a_first_counter1_T = {1'h0, a_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28] wire a_first_counter1 = _a_first_counter1_T[0]; // @[Edges.scala:230:28] wire a_first = ~a_first_counter; // @[Edges.scala:229:27, :231:25] wire _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire _a_first_counter_T = ~a_first & a_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [1:0] size; // @[Monitor.scala:389:22] reg [8:0] source; // @[Monitor.scala:390:22] reg [27:0] address; // @[Monitor.scala:391:22] wire _T_745 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_745; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_745; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_745; // @[Decoupled.scala:51:35] wire d_first_done = _d_first_T; // @[Decoupled.scala:51:35] wire [5:0] _GEN_0 = 6'h7 << io_in_d_bits_size_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [2:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] reg d_first_counter; // @[Edges.scala:229:27] wire _d_first_last_T = d_first_counter; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T = {1'h0, d_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1 = _d_first_counter1_T[0]; // @[Edges.scala:230:28] wire d_first = ~d_first_counter; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T = ~d_first & d_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] size_1; // @[Monitor.scala:540:22] reg [8:0] source_1; // @[Monitor.scala:541:22] reg [319:0] inflight; // @[Monitor.scala:614:27] reg [1279:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [1279:0] inflight_sizes; // @[Monitor.scala:618:33] wire a_first_done_1 = _a_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] reg a_first_counter_1; // @[Edges.scala:229:27] wire _a_first_last_T_2 = a_first_counter_1; // @[Edges.scala:229:27, :232:25] wire [1:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28] wire a_first_counter1_1 = _a_first_counter1_T_1[0]; // @[Edges.scala:230:28] wire a_first_1 = ~a_first_counter_1; // @[Edges.scala:229:27, :231:25] wire _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire _a_first_counter_T_1 = ~a_first_1 & a_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21] wire d_first_done_1 = _d_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] reg d_first_counter_1; // @[Edges.scala:229:27] wire _d_first_last_T_2 = d_first_counter_1; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1_1 = _d_first_counter1_T_1[0]; // @[Edges.scala:230:28] wire d_first_1 = ~d_first_counter_1; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T_1 = ~d_first_1 & d_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21] wire [319:0] a_set; // @[Monitor.scala:626:34] wire [319:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [1279:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [1279:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [11:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [11:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [11:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :641:65] wire [11:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [11:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :681:99] wire [11:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [11:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :750:67] wire [11:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [11:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :791:99] wire [1279:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [1279:0] _a_opcode_lookup_T_6 = {1276'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [1279:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[1279:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [3:0] a_size_lookup; // @[Monitor.scala:639:33] wire [1279:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [1279:0] _a_size_lookup_T_6 = {1276'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}] wire [1279:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[1279:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [2:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [511:0] _GEN_2 = 512'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [511:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_2; // @[OneHot.scala:58:35] wire [511:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_2; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[319:0] : 320'h0; // @[OneHot.scala:58:35] wire _T_598 = _T_672 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_598 ? _a_set_T[319:0] : 320'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_598 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [2:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [2:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[2:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_598 ? _a_sizes_set_interm_T_1 : 3'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [11:0] _GEN_3 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [11:0] _a_opcodes_set_T; // @[Monitor.scala:659:79] assign _a_opcodes_set_T = _GEN_3; // @[Monitor.scala:659:79] wire [11:0] _a_sizes_set_T; // @[Monitor.scala:660:77] assign _a_sizes_set_T = _GEN_3; // @[Monitor.scala:659:79, :660:77] wire [4098:0] _a_opcodes_set_T_1 = {4095'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_598 ? _a_opcodes_set_T_1[1279:0] : 1280'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [4097:0] _a_sizes_set_T_1 = {4095'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_598 ? _a_sizes_set_T_1[1279:0] : 1280'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [319:0] d_clr; // @[Monitor.scala:664:34] wire [319:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [1279:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [1279:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46] wire _T_644 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [511:0] _GEN_5 = 512'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [511:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35] wire [511:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35] wire [511:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35] wire [511:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_644 & ~d_release_ack ? _d_clr_wo_ready_T[319:0] : 320'h0; // @[OneHot.scala:58:35] wire _T_613 = _T_745 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_613 ? _d_clr_T[319:0] : 320'h0; // @[OneHot.scala:58:35] wire [4110:0] _d_opcodes_clr_T_5 = 4111'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_613 ? _d_opcodes_clr_T_5[1279:0] : 1280'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [4110:0] _d_sizes_clr_T_5 = 4111'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_613 ? _d_sizes_clr_T_5[1279:0] : 1280'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [319:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [319:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [319:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [1279:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [1279:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [1279:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [1279:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [1279:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [1279:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [319:0] inflight_1; // @[Monitor.scala:726:35] wire [319:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [1279:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [1279:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [1279:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [1279:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire d_first_done_2 = _d_first_T_2; // @[Decoupled.scala:51:35] wire [2:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] reg d_first_counter_2; // @[Edges.scala:229:27] wire _d_first_last_T_4 = d_first_counter_2; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1_2 = _d_first_counter1_T_2[0]; // @[Edges.scala:230:28] wire d_first_2 = ~d_first_counter_2; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T_2 = ~d_first_2 & d_first_counter1_2; // @[Edges.scala:230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [3:0] c_size_lookup; // @[Monitor.scala:748:35] wire [1279:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [1279:0] _c_opcode_lookup_T_6 = {1276'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [1279:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[1279:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [1279:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [1279:0] _c_size_lookup_T_6 = {1276'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}] wire [1279:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[1279:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [319:0] d_clr_1; // @[Monitor.scala:774:34] wire [319:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [1279:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [1279:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_716 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_716 & d_release_ack_1 ? _d_clr_wo_ready_T_1[319:0] : 320'h0; // @[OneHot.scala:58:35] wire _T_698 = _T_745 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_698 ? _d_clr_T_1[319:0] : 320'h0; // @[OneHot.scala:58:35] wire [4110:0] _d_opcodes_clr_T_11 = 4111'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_698 ? _d_opcodes_clr_T_11[1279:0] : 1280'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [4110:0] _d_sizes_clr_T_11 = 4111'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_698 ? _d_sizes_clr_T_11[1279:0] : 1280'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 9'h0; // @[Monitor.scala:36:7, :795:113] wire [319:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [319:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [1279:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [1279:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [1279:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [1279:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]

Generate the Verilog code corresponding to the following Chisel files. File primitives.scala: /*============================================================================ This Chisel source file is part of a pre-release version of the HardFloat IEEE Floating-Point Arithmetic Package, by John R. Hauser (with some contributions from Yunsup Lee and Andrew Waterman, mainly concerning testing). Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the University of California. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions, and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions, and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the University nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. =============================================================================*/ package hardfloat import chisel3._ import chisel3.util._ //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- object lowMask { def apply(in: UInt, topBound: BigInt, bottomBound: BigInt): UInt = { require(topBound != bottomBound) val numInVals = BigInt(1)<<in.getWidth if (topBound < bottomBound) { lowMask(~in, numInVals - 1 - topBound, numInVals - 1 - bottomBound) } else if (numInVals > 64 /* Empirical */) { // For simulation performance, we should avoid generating // exteremely wide shifters, so we divide and conquer. // Empirically, this does not impact synthesis QoR. val mid = numInVals / 2 val msb = in(in.getWidth - 1) val lsbs = in(in.getWidth - 2, 0) if (mid < topBound) { if (mid <= bottomBound) { Mux(msb, lowMask(lsbs, topBound - mid, bottomBound - mid), 0.U ) } else { Mux(msb, lowMask(lsbs, topBound - mid, 0) ## ((BigInt(1)<<(mid - bottomBound).toInt) - 1).U, lowMask(lsbs, mid, bottomBound) ) } } else { ~Mux(msb, 0.U, ~lowMask(lsbs, topBound, bottomBound)) } } else { val shift = (BigInt(-1)<<numInVals.toInt).S>>in Reverse( shift( (numInVals - 1 - bottomBound).toInt, (numInVals - topBound).toInt ) ) } } } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- object countLeadingZeros { def apply(in: UInt): UInt = PriorityEncoder(in.asBools.reverse) } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- object orReduceBy2 { def apply(in: UInt): UInt = { val reducedWidth = (in.getWidth + 1)>>1 val reducedVec = Wire(Vec(reducedWidth, Bool())) for (ix <- 0 until reducedWidth - 1) { reducedVec(ix) := in(ix * 2 + 1, ix * 2).orR } reducedVec(reducedWidth - 1) := in(in.getWidth - 1, (reducedWidth - 1) * 2).orR reducedVec.asUInt } } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- object orReduceBy4 { def apply(in: UInt): UInt = { val reducedWidth = (in.getWidth + 3)>>2 val reducedVec = Wire(Vec(reducedWidth, Bool())) for (ix <- 0 until reducedWidth - 1) { reducedVec(ix) := in(ix * 4 + 3, ix * 4).orR } reducedVec(reducedWidth - 1) := in(in.getWidth - 1, (reducedWidth - 1) * 4).orR reducedVec.asUInt } } File RoundAnyRawFNToRecFN.scala: /*============================================================================ This Chisel source file is part of a pre-release version of the HardFloat IEEE Floating-Point Arithmetic Package, by John R. Hauser (with some contributions from Yunsup Lee and Andrew Waterman, mainly concerning testing). Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the University of California. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions, and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions, and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the University nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. =============================================================================*/ package hardfloat import chisel3._ import chisel3.util.Fill import consts._ //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- class RoundAnyRawFNToRecFN( inExpWidth: Int, inSigWidth: Int, outExpWidth: Int, outSigWidth: Int, options: Int ) extends RawModule { override def desiredName = s"RoundAnyRawFNToRecFN_ie${inExpWidth}_is${inSigWidth}_oe${outExpWidth}_os${outSigWidth}" val io = IO(new Bundle { val invalidExc = Input(Bool()) // overrides 'infiniteExc' and 'in' val infiniteExc = Input(Bool()) // overrides 'in' except for 'in.sign' val in = Input(new RawFloat(inExpWidth, inSigWidth)) // (allowed exponent range has limits) val roundingMode = Input(UInt(3.W)) val detectTininess = Input(UInt(1.W)) val out = Output(Bits((outExpWidth + outSigWidth + 1).W)) val exceptionFlags = Output(Bits(5.W)) }) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val sigMSBitAlwaysZero = ((options & flRoundOpt_sigMSBitAlwaysZero) != 0) val effectiveInSigWidth = if (sigMSBitAlwaysZero) inSigWidth else inSigWidth + 1 val neverUnderflows = ((options & (flRoundOpt_neverUnderflows | flRoundOpt_subnormsAlwaysExact) ) != 0) || (inExpWidth < outExpWidth) val neverOverflows = ((options & flRoundOpt_neverOverflows) != 0) || (inExpWidth < outExpWidth) val outNaNExp = BigInt(7)<<(outExpWidth - 2) val outInfExp = BigInt(6)<<(outExpWidth - 2) val outMaxFiniteExp = outInfExp - 1 val outMinNormExp = (BigInt(1)<<(outExpWidth - 1)) + 2 val outMinNonzeroExp = outMinNormExp - outSigWidth + 1 //------------------------------------------------------------------------ //------------------------------------------------------------------------ val roundingMode_near_even = (io.roundingMode === round_near_even) val roundingMode_minMag = (io.roundingMode === round_minMag) val roundingMode_min = (io.roundingMode === round_min) val roundingMode_max = (io.roundingMode === round_max) val roundingMode_near_maxMag = (io.roundingMode === round_near_maxMag) val roundingMode_odd = (io.roundingMode === round_odd) val roundMagUp = (roundingMode_min && io.in.sign) || (roundingMode_max && ! io.in.sign) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val sAdjustedExp = if (inExpWidth < outExpWidth) (io.in.sExp +& ((BigInt(1)<<outExpWidth) - (BigInt(1)<<inExpWidth)).S )(outExpWidth, 0).zext else if (inExpWidth == outExpWidth) io.in.sExp else io.in.sExp +& ((BigInt(1)<<outExpWidth) - (BigInt(1)<<inExpWidth)).S val adjustedSig = if (inSigWidth <= outSigWidth + 2) io.in.sig<<(outSigWidth - inSigWidth + 2) else (io.in.sig(inSigWidth, inSigWidth - outSigWidth - 1) ## io.in.sig(inSigWidth - outSigWidth - 2, 0).orR ) val doShiftSigDown1 = if (sigMSBitAlwaysZero) false.B else adjustedSig(outSigWidth + 2) val common_expOut = Wire(UInt((outExpWidth + 1).W)) val common_fractOut = Wire(UInt((outSigWidth - 1).W)) val common_overflow = Wire(Bool()) val common_totalUnderflow = Wire(Bool()) val common_underflow = Wire(Bool()) val common_inexact = Wire(Bool()) if ( neverOverflows && neverUnderflows && (effectiveInSigWidth <= outSigWidth) ) { //-------------------------------------------------------------------- //-------------------------------------------------------------------- common_expOut := sAdjustedExp(outExpWidth, 0) + doShiftSigDown1 common_fractOut := Mux(doShiftSigDown1, adjustedSig(outSigWidth + 1, 3), adjustedSig(outSigWidth, 2) ) common_overflow := false.B common_totalUnderflow := false.B common_underflow := false.B common_inexact := false.B } else { //-------------------------------------------------------------------- //-------------------------------------------------------------------- val roundMask = if (neverUnderflows) 0.U(outSigWidth.W) ## doShiftSigDown1 ## 3.U(2.W) else (lowMask( sAdjustedExp(outExpWidth, 0), outMinNormExp - outSigWidth - 1, outMinNormExp ) | doShiftSigDown1) ## 3.U(2.W) val shiftedRoundMask = 0.U(1.W) ## roundMask>>1 val roundPosMask = ~shiftedRoundMask & roundMask val roundPosBit = (adjustedSig & roundPosMask).orR val anyRoundExtra = (adjustedSig & shiftedRoundMask).orR val anyRound = roundPosBit || anyRoundExtra val roundIncr = ((roundingMode_near_even || roundingMode_near_maxMag) && roundPosBit) || (roundMagUp && anyRound) val roundedSig: Bits = Mux(roundIncr, (((adjustedSig | roundMask)>>2) +& 1.U) & ~Mux(roundingMode_near_even && roundPosBit && ! anyRoundExtra, roundMask>>1, 0.U((outSigWidth + 2).W) ), (adjustedSig & ~roundMask)>>2 | Mux(roundingMode_odd && anyRound, roundPosMask>>1, 0.U) ) //*** IF SIG WIDTH IS VERY NARROW, NEED TO ACCOUNT FOR ROUND-EVEN ZEROING //*** M.S. BIT OF SUBNORMAL SIG? val sRoundedExp = sAdjustedExp +& (roundedSig>>outSigWidth).asUInt.zext common_expOut := sRoundedExp(outExpWidth, 0) common_fractOut := Mux(doShiftSigDown1, roundedSig(outSigWidth - 1, 1), roundedSig(outSigWidth - 2, 0) ) common_overflow := (if (neverOverflows) false.B else //*** REWRITE BASED ON BEFORE-ROUNDING EXPONENT?: (sRoundedExp>>(outExpWidth - 1) >= 3.S)) common_totalUnderflow := (if (neverUnderflows) false.B else //*** WOULD BE GOOD ENOUGH TO USE EXPONENT BEFORE ROUNDING?: (sRoundedExp < outMinNonzeroExp.S)) val unboundedRange_roundPosBit = Mux(doShiftSigDown1, adjustedSig(2), adjustedSig(1)) val unboundedRange_anyRound = (doShiftSigDown1 && adjustedSig(2)) || adjustedSig(1, 0).orR val unboundedRange_roundIncr = ((roundingMode_near_even || roundingMode_near_maxMag) && unboundedRange_roundPosBit) || (roundMagUp && unboundedRange_anyRound) val roundCarry = Mux(doShiftSigDown1, roundedSig(outSigWidth + 1), roundedSig(outSigWidth) ) common_underflow := (if (neverUnderflows) false.B else common_totalUnderflow || //*** IF SIG WIDTH IS VERY NARROW, NEED TO ACCOUNT FOR ROUND-EVEN ZEROING //*** M.S. BIT OF SUBNORMAL SIG? (anyRound && ((sAdjustedExp>>outExpWidth) <= 0.S) && Mux(doShiftSigDown1, roundMask(3), roundMask(2)) && ! ((io.detectTininess === tininess_afterRounding) && ! Mux(doShiftSigDown1, roundMask(4), roundMask(3) ) && roundCarry && roundPosBit && unboundedRange_roundIncr))) common_inexact := common_totalUnderflow || anyRound } //------------------------------------------------------------------------ //------------------------------------------------------------------------ val isNaNOut = io.invalidExc || io.in.isNaN val notNaN_isSpecialInfOut = io.infiniteExc || io.in.isInf val commonCase = ! isNaNOut && ! notNaN_isSpecialInfOut && ! io.in.isZero val overflow = commonCase && common_overflow val underflow = commonCase && common_underflow val inexact = overflow || (commonCase && common_inexact) val overflow_roundMagUp = roundingMode_near_even || roundingMode_near_maxMag || roundMagUp val pegMinNonzeroMagOut = commonCase && common_totalUnderflow && (roundMagUp || roundingMode_odd) val pegMaxFiniteMagOut = overflow && ! overflow_roundMagUp val notNaN_isInfOut = notNaN_isSpecialInfOut || (overflow && overflow_roundMagUp) val signOut = Mux(isNaNOut, false.B, io.in.sign) val expOut = (common_expOut & ~Mux(io.in.isZero || common_totalUnderflow, (BigInt(7)<<(outExpWidth - 2)).U((outExpWidth + 1).W), 0.U ) & ~Mux(pegMinNonzeroMagOut, ~outMinNonzeroExp.U((outExpWidth + 1).W), 0.U ) & ~Mux(pegMaxFiniteMagOut, (BigInt(1)<<(outExpWidth - 1)).U((outExpWidth + 1).W), 0.U ) & ~Mux(notNaN_isInfOut, (BigInt(1)<<(outExpWidth - 2)).U((outExpWidth + 1).W), 0.U )) | Mux(pegMinNonzeroMagOut, outMinNonzeroExp.U((outExpWidth + 1).W), 0.U ) | Mux(pegMaxFiniteMagOut, outMaxFiniteExp.U((outExpWidth + 1).W), 0.U ) | Mux(notNaN_isInfOut, outInfExp.U((outExpWidth + 1).W), 0.U) | Mux(isNaNOut, outNaNExp.U((outExpWidth + 1).W), 0.U) val fractOut = Mux(isNaNOut || io.in.isZero || common_totalUnderflow, Mux(isNaNOut, (BigInt(1)<<(outSigWidth - 2)).U, 0.U), common_fractOut ) | Fill(outSigWidth - 1, pegMaxFiniteMagOut) io.out := signOut ## expOut ## fractOut io.exceptionFlags := io.invalidExc ## io.infiniteExc ## overflow ## underflow ## inexact } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- class RoundRawFNToRecFN(expWidth: Int, sigWidth: Int, options: Int) extends RawModule { override def desiredName = s"RoundRawFNToRecFN_e${expWidth}_s${sigWidth}" val io = IO(new Bundle { val invalidExc = Input(Bool()) // overrides 'infiniteExc' and 'in' val infiniteExc = Input(Bool()) // overrides 'in' except for 'in.sign' val in = Input(new RawFloat(expWidth, sigWidth + 2)) val roundingMode = Input(UInt(3.W)) val detectTininess = Input(UInt(1.W)) val out = Output(Bits((expWidth + sigWidth + 1).W)) val exceptionFlags = Output(Bits(5.W)) }) val roundAnyRawFNToRecFN = Module( new RoundAnyRawFNToRecFN( expWidth, sigWidth + 2, expWidth, sigWidth, options)) roundAnyRawFNToRecFN.io.invalidExc := io.invalidExc roundAnyRawFNToRecFN.io.infiniteExc := io.infiniteExc roundAnyRawFNToRecFN.io.in := io.in roundAnyRawFNToRecFN.io.roundingMode := io.roundingMode roundAnyRawFNToRecFN.io.detectTininess := io.detectTininess io.out := roundAnyRawFNToRecFN.io.out io.exceptionFlags := roundAnyRawFNToRecFN.io.exceptionFlags }

module RoundAnyRawFNToRecFN_ie8_is26_oe8_os24_75( // @[RoundAnyRawFNToRecFN.scala:48:5] input io_invalidExc, // @[RoundAnyRawFNToRecFN.scala:58:16] input io_in_isNaN, // @[RoundAnyRawFNToRecFN.scala:58:16] input io_in_isInf, // @[RoundAnyRawFNToRecFN.scala:58:16] input io_in_isZero, // @[RoundAnyRawFNToRecFN.scala:58:16] input io_in_sign, // @[RoundAnyRawFNToRecFN.scala:58:16] input [9:0] io_in_sExp, // @[RoundAnyRawFNToRecFN.scala:58:16] input [26:0] io_in_sig, // @[RoundAnyRawFNToRecFN.scala:58:16] output [32:0] io_out, // @[RoundAnyRawFNToRecFN.scala:58:16] output [4:0] io_exceptionFlags // @[RoundAnyRawFNToRecFN.scala:58:16] ); wire io_invalidExc_0 = io_invalidExc; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_isNaN_0 = io_in_isNaN; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_isInf_0 = io_in_isInf; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_isZero_0 = io_in_isZero; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_sign_0 = io_in_sign; // @[RoundAnyRawFNToRecFN.scala:48:5] wire [9:0] io_in_sExp_0 = io_in_sExp; // @[RoundAnyRawFNToRecFN.scala:48:5] wire [26:0] io_in_sig_0 = io_in_sig; // @[RoundAnyRawFNToRecFN.scala:48:5] wire [8:0] _expOut_T_4 = 9'h194; // @[RoundAnyRawFNToRecFN.scala:258:19] wire [15:0] _roundMask_T_5 = 16'hFF; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_4 = 16'hFF00; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_10 = 16'hFF00; // @[primitives.scala:77:20] wire [11:0] _roundMask_T_13 = 12'hFF; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_14 = 16'hFF0; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_15 = 16'hF0F; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_20 = 16'hF0F0; // @[primitives.scala:77:20] wire [13:0] _roundMask_T_23 = 14'hF0F; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_24 = 16'h3C3C; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_25 = 16'h3333; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_30 = 16'hCCCC; // @[primitives.scala:77:20] wire [14:0] _roundMask_T_33 = 15'h3333; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_34 = 16'h6666; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_35 = 16'h5555; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_40 = 16'hAAAA; // @[primitives.scala:77:20] wire [25:0] _roundedSig_T_15 = 26'h0; // @[RoundAnyRawFNToRecFN.scala:181:24] wire [8:0] _expOut_T_6 = 9'h1FF; // @[RoundAnyRawFNToRecFN.scala:257:14, :261:14] wire [8:0] _expOut_T_9 = 9'h1FF; // @[RoundAnyRawFNToRecFN.scala:257:14, :261:14] wire [8:0] _expOut_T_5 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:257:18] wire [8:0] _expOut_T_8 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:261:18] wire [8:0] _expOut_T_14 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:269:16] wire [8:0] _expOut_T_16 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:273:16] wire [22:0] _fractOut_T_4 = 23'h0; // @[RoundAnyRawFNToRecFN.scala:284:13] wire io_detectTininess = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5] wire roundingMode_near_even = 1'h1; // @[RoundAnyRawFNToRecFN.scala:90:53] wire _roundIncr_T = 1'h1; // @[RoundAnyRawFNToRecFN.scala:169:38] wire _unboundedRange_roundIncr_T = 1'h1; // @[RoundAnyRawFNToRecFN.scala:207:38] wire _common_underflow_T_7 = 1'h1; // @[RoundAnyRawFNToRecFN.scala:222:49] wire _overflow_roundMagUp_T = 1'h1; // @[RoundAnyRawFNToRecFN.scala:243:32] wire overflow_roundMagUp = 1'h1; // @[RoundAnyRawFNToRecFN.scala:243:60] wire [2:0] io_roundingMode = 3'h0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_infiniteExc = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire roundingMode_minMag = 1'h0; // @[RoundAnyRawFNToRecFN.scala:91:53] wire roundingMode_min = 1'h0; // @[RoundAnyRawFNToRecFN.scala:92:53] wire roundingMode_max = 1'h0; // @[RoundAnyRawFNToRecFN.scala:93:53] wire roundingMode_near_maxMag = 1'h0; // @[RoundAnyRawFNToRecFN.scala:94:53] wire roundingMode_odd = 1'h0; // @[RoundAnyRawFNToRecFN.scala:95:53] wire _roundMagUp_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:98:27] wire _roundMagUp_T_2 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:98:63] wire roundMagUp = 1'h0; // @[RoundAnyRawFNToRecFN.scala:98:42] wire _roundIncr_T_2 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:171:29] wire _roundedSig_T_13 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:181:42] wire _unboundedRange_roundIncr_T_2 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:209:29] wire _pegMinNonzeroMagOut_T_1 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:245:60] wire pegMinNonzeroMagOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:245:45] wire _pegMaxFiniteMagOut_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:246:42] wire pegMaxFiniteMagOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:246:39] wire notNaN_isSpecialInfOut = io_in_isInf_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :236:49] wire [26:0] adjustedSig = io_in_sig_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :114:22] wire [32:0] _io_out_T_1; // @[RoundAnyRawFNToRecFN.scala:286:33] wire [4:0] _io_exceptionFlags_T_3; // @[RoundAnyRawFNToRecFN.scala:288:66] wire [32:0] io_out_0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire [4:0] io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire _roundMagUp_T_1 = ~io_in_sign_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :98:66] wire doShiftSigDown1 = adjustedSig[26]; // @[RoundAnyRawFNToRecFN.scala:114:22, :120:57] wire [8:0] _common_expOut_T; // @[RoundAnyRawFNToRecFN.scala:187:37] wire [8:0] common_expOut; // @[RoundAnyRawFNToRecFN.scala:122:31] wire [22:0] _common_fractOut_T_2; // @[RoundAnyRawFNToRecFN.scala:189:16] wire [22:0] common_fractOut; // @[RoundAnyRawFNToRecFN.scala:123:31] wire _common_overflow_T_1; // @[RoundAnyRawFNToRecFN.scala:196:50] wire common_overflow; // @[RoundAnyRawFNToRecFN.scala:124:37] wire _common_totalUnderflow_T; // @[RoundAnyRawFNToRecFN.scala:200:31] wire common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:125:37] wire _common_underflow_T_18; // @[RoundAnyRawFNToRecFN.scala:217:40] wire common_underflow; // @[RoundAnyRawFNToRecFN.scala:126:37] wire _common_inexact_T; // @[RoundAnyRawFNToRecFN.scala:230:49] wire common_inexact; // @[RoundAnyRawFNToRecFN.scala:127:37] wire [8:0] _roundMask_T = io_in_sExp_0[8:0]; // @[RoundAnyRawFNToRecFN.scala:48:5, :156:37] wire [8:0] _roundMask_T_1 = ~_roundMask_T; // @[primitives.scala:52:21] wire roundMask_msb = _roundMask_T_1[8]; // @[primitives.scala:52:21, :58:25] wire [7:0] roundMask_lsbs = _roundMask_T_1[7:0]; // @[primitives.scala:52:21, :59:26] wire roundMask_msb_1 = roundMask_lsbs[7]; // @[primitives.scala:58:25, :59:26] wire [6:0] roundMask_lsbs_1 = roundMask_lsbs[6:0]; // @[primitives.scala:59:26] wire roundMask_msb_2 = roundMask_lsbs_1[6]; // @[primitives.scala:58:25, :59:26] wire roundMask_msb_3 = roundMask_lsbs_1[6]; // @[primitives.scala:58:25, :59:26] wire [5:0] roundMask_lsbs_2 = roundMask_lsbs_1[5:0]; // @[primitives.scala:59:26] wire [5:0] roundMask_lsbs_3 = roundMask_lsbs_1[5:0]; // @[primitives.scala:59:26] wire [64:0] roundMask_shift = $signed(65'sh10000000000000000 >>> roundMask_lsbs_2); // @[primitives.scala:59:26, :76:56] wire [21:0] _roundMask_T_2 = roundMask_shift[63:42]; // @[primitives.scala:76:56, :78:22] wire [15:0] _roundMask_T_3 = _roundMask_T_2[15:0]; // @[primitives.scala:77:20, :78:22] wire [7:0] _roundMask_T_6 = _roundMask_T_3[15:8]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_7 = {8'h0, _roundMask_T_6}; // @[primitives.scala:77:20] wire [7:0] _roundMask_T_8 = _roundMask_T_3[7:0]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_9 = {_roundMask_T_8, 8'h0}; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_11 = _roundMask_T_9 & 16'hFF00; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_12 = _roundMask_T_7 | _roundMask_T_11; // @[primitives.scala:77:20] wire [11:0] _roundMask_T_16 = _roundMask_T_12[15:4]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_17 = {4'h0, _roundMask_T_16 & 12'hF0F}; // @[primitives.scala:77:20] wire [11:0] _roundMask_T_18 = _roundMask_T_12[11:0]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_19 = {_roundMask_T_18, 4'h0}; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_21 = _roundMask_T_19 & 16'hF0F0; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_22 = _roundMask_T_17 | _roundMask_T_21; // @[primitives.scala:77:20] wire [13:0] _roundMask_T_26 = _roundMask_T_22[15:2]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_27 = {2'h0, _roundMask_T_26 & 14'h3333}; // @[primitives.scala:77:20] wire [13:0] _roundMask_T_28 = _roundMask_T_22[13:0]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_29 = {_roundMask_T_28, 2'h0}; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_31 = _roundMask_T_29 & 16'hCCCC; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_32 = _roundMask_T_27 | _roundMask_T_31; // @[primitives.scala:77:20] wire [14:0] _roundMask_T_36 = _roundMask_T_32[15:1]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_37 = {1'h0, _roundMask_T_36 & 15'h5555}; // @[primitives.scala:77:20] wire [14:0] _roundMask_T_38 = _roundMask_T_32[14:0]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_39 = {_roundMask_T_38, 1'h0}; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_41 = _roundMask_T_39 & 16'hAAAA; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_42 = _roundMask_T_37 | _roundMask_T_41; // @[primitives.scala:77:20] wire [5:0] _roundMask_T_43 = _roundMask_T_2[21:16]; // @[primitives.scala:77:20, :78:22] wire [3:0] _roundMask_T_44 = _roundMask_T_43[3:0]; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_45 = _roundMask_T_44[1:0]; // @[primitives.scala:77:20] wire _roundMask_T_46 = _roundMask_T_45[0]; // @[primitives.scala:77:20] wire _roundMask_T_47 = _roundMask_T_45[1]; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_48 = {_roundMask_T_46, _roundMask_T_47}; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_49 = _roundMask_T_44[3:2]; // @[primitives.scala:77:20] wire _roundMask_T_50 = _roundMask_T_49[0]; // @[primitives.scala:77:20] wire _roundMask_T_51 = _roundMask_T_49[1]; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_52 = {_roundMask_T_50, _roundMask_T_51}; // @[primitives.scala:77:20] wire [3:0] _roundMask_T_53 = {_roundMask_T_48, _roundMask_T_52}; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_54 = _roundMask_T_43[5:4]; // @[primitives.scala:77:20] wire _roundMask_T_55 = _roundMask_T_54[0]; // @[primitives.scala:77:20] wire _roundMask_T_56 = _roundMask_T_54[1]; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_57 = {_roundMask_T_55, _roundMask_T_56}; // @[primitives.scala:77:20] wire [5:0] _roundMask_T_58 = {_roundMask_T_53, _roundMask_T_57}; // @[primitives.scala:77:20] wire [21:0] _roundMask_T_59 = {_roundMask_T_42, _roundMask_T_58}; // @[primitives.scala:77:20] wire [21:0] _roundMask_T_60 = ~_roundMask_T_59; // @[primitives.scala:73:32, :77:20] wire [21:0] _roundMask_T_61 = roundMask_msb_2 ? 22'h0 : _roundMask_T_60; // @[primitives.scala:58:25, :73:{21,32}] wire [21:0] _roundMask_T_62 = ~_roundMask_T_61; // @[primitives.scala:73:{17,21}] wire [24:0] _roundMask_T_63 = {_roundMask_T_62, 3'h7}; // @[primitives.scala:68:58, :73:17] wire [64:0] roundMask_shift_1 = $signed(65'sh10000000000000000 >>> roundMask_lsbs_3); // @[primitives.scala:59:26, :76:56] wire [2:0] _roundMask_T_64 = roundMask_shift_1[2:0]; // @[primitives.scala:76:56, :78:22] wire [1:0] _roundMask_T_65 = _roundMask_T_64[1:0]; // @[primitives.scala:77:20, :78:22] wire _roundMask_T_66 = _roundMask_T_65[0]; // @[primitives.scala:77:20] wire _roundMask_T_67 = _roundMask_T_65[1]; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_68 = {_roundMask_T_66, _roundMask_T_67}; // @[primitives.scala:77:20] wire _roundMask_T_69 = _roundMask_T_64[2]; // @[primitives.scala:77:20, :78:22] wire [2:0] _roundMask_T_70 = {_roundMask_T_68, _roundMask_T_69}; // @[primitives.scala:77:20] wire [2:0] _roundMask_T_71 = roundMask_msb_3 ? _roundMask_T_70 : 3'h0; // @[primitives.scala:58:25, :62:24, :77:20] wire [24:0] _roundMask_T_72 = roundMask_msb_1 ? _roundMask_T_63 : {22'h0, _roundMask_T_71}; // @[primitives.scala:58:25, :62:24, :67:24, :68:58] wire [24:0] _roundMask_T_73 = roundMask_msb ? _roundMask_T_72 : 25'h0; // @[primitives.scala:58:25, :62:24, :67:24] wire [24:0] _roundMask_T_74 = {_roundMask_T_73[24:1], _roundMask_T_73[0] | doShiftSigDown1}; // @[primitives.scala:62:24] wire [26:0] roundMask = {_roundMask_T_74, 2'h3}; // @[RoundAnyRawFNToRecFN.scala:159:{23,42}] wire [27:0] _shiftedRoundMask_T = {1'h0, roundMask}; // @[RoundAnyRawFNToRecFN.scala:159:42, :162:41] wire [26:0] shiftedRoundMask = _shiftedRoundMask_T[27:1]; // @[RoundAnyRawFNToRecFN.scala:162:{41,53}] wire [26:0] _roundPosMask_T = ~shiftedRoundMask; // @[RoundAnyRawFNToRecFN.scala:162:53, :163:28] wire [26:0] roundPosMask = _roundPosMask_T & roundMask; // @[RoundAnyRawFNToRecFN.scala:159:42, :163:{28,46}] wire [26:0] _roundPosBit_T = adjustedSig & roundPosMask; // @[RoundAnyRawFNToRecFN.scala:114:22, :163:46, :164:40] wire roundPosBit = |_roundPosBit_T; // @[RoundAnyRawFNToRecFN.scala:164:{40,56}] wire _roundIncr_T_1 = roundPosBit; // @[RoundAnyRawFNToRecFN.scala:164:56, :169:67] wire _roundedSig_T_3 = roundPosBit; // @[RoundAnyRawFNToRecFN.scala:164:56, :175:49] wire [26:0] _anyRoundExtra_T = adjustedSig & shiftedRoundMask; // @[RoundAnyRawFNToRecFN.scala:114:22, :162:53, :165:42] wire anyRoundExtra = |_anyRoundExtra_T; // @[RoundAnyRawFNToRecFN.scala:165:{42,62}] wire anyRound = roundPosBit | anyRoundExtra; // @[RoundAnyRawFNToRecFN.scala:164:56, :165:62, :166:36] wire roundIncr = _roundIncr_T_1; // @[RoundAnyRawFNToRecFN.scala:169:67, :170:31] wire [26:0] _roundedSig_T = adjustedSig | roundMask; // @[RoundAnyRawFNToRecFN.scala:114:22, :159:42, :174:32] wire [24:0] _roundedSig_T_1 = _roundedSig_T[26:2]; // @[RoundAnyRawFNToRecFN.scala:174:{32,44}] wire [25:0] _roundedSig_T_2 = {1'h0, _roundedSig_T_1} + 26'h1; // @[RoundAnyRawFNToRecFN.scala:174:{44,49}] wire _roundedSig_T_4 = ~anyRoundExtra; // @[RoundAnyRawFNToRecFN.scala:165:62, :176:30] wire _roundedSig_T_5 = _roundedSig_T_3 & _roundedSig_T_4; // @[RoundAnyRawFNToRecFN.scala:175:{49,64}, :176:30] wire [25:0] _roundedSig_T_6 = roundMask[26:1]; // @[RoundAnyRawFNToRecFN.scala:159:42, :177:35] wire [25:0] _roundedSig_T_7 = _roundedSig_T_5 ? _roundedSig_T_6 : 26'h0; // @[RoundAnyRawFNToRecFN.scala:175:{25,64}, :177:35] wire [25:0] _roundedSig_T_8 = ~_roundedSig_T_7; // @[RoundAnyRawFNToRecFN.scala:175:{21,25}] wire [25:0] _roundedSig_T_9 = _roundedSig_T_2 & _roundedSig_T_8; // @[RoundAnyRawFNToRecFN.scala:174:{49,57}, :175:21] wire [26:0] _roundedSig_T_10 = ~roundMask; // @[RoundAnyRawFNToRecFN.scala:159:42, :180:32] wire [26:0] _roundedSig_T_11 = adjustedSig & _roundedSig_T_10; // @[RoundAnyRawFNToRecFN.scala:114:22, :180:{30,32}] wire [24:0] _roundedSig_T_12 = _roundedSig_T_11[26:2]; // @[RoundAnyRawFNToRecFN.scala:180:{30,43}] wire [25:0] _roundedSig_T_14 = roundPosMask[26:1]; // @[RoundAnyRawFNToRecFN.scala:163:46, :181:67] wire [25:0] _roundedSig_T_16 = {1'h0, _roundedSig_T_12}; // @[RoundAnyRawFNToRecFN.scala:180:{43,47}] wire [25:0] roundedSig = roundIncr ? _roundedSig_T_9 : _roundedSig_T_16; // @[RoundAnyRawFNToRecFN.scala:170:31, :173:16, :174:57, :180:47] wire [1:0] _sRoundedExp_T = roundedSig[25:24]; // @[RoundAnyRawFNToRecFN.scala:173:16, :185:54] wire [2:0] _sRoundedExp_T_1 = {1'h0, _sRoundedExp_T}; // @[RoundAnyRawFNToRecFN.scala:185:{54,76}] wire [10:0] sRoundedExp = {io_in_sExp_0[9], io_in_sExp_0} + {{8{_sRoundedExp_T_1[2]}}, _sRoundedExp_T_1}; // @[RoundAnyRawFNToRecFN.scala:48:5, :185:{40,76}] assign _common_expOut_T = sRoundedExp[8:0]; // @[RoundAnyRawFNToRecFN.scala:185:40, :187:37] assign common_expOut = _common_expOut_T; // @[RoundAnyRawFNToRecFN.scala:122:31, :187:37] wire [22:0] _common_fractOut_T = roundedSig[23:1]; // @[RoundAnyRawFNToRecFN.scala:173:16, :190:27] wire [22:0] _common_fractOut_T_1 = roundedSig[22:0]; // @[RoundAnyRawFNToRecFN.scala:173:16, :191:27] assign _common_fractOut_T_2 = doShiftSigDown1 ? _common_fractOut_T : _common_fractOut_T_1; // @[RoundAnyRawFNToRecFN.scala:120:57, :189:16, :190:27, :191:27] assign common_fractOut = _common_fractOut_T_2; // @[RoundAnyRawFNToRecFN.scala:123:31, :189:16] wire [3:0] _common_overflow_T = sRoundedExp[10:7]; // @[RoundAnyRawFNToRecFN.scala:185:40, :196:30] assign _common_overflow_T_1 = $signed(_common_overflow_T) > 4'sh2; // @[RoundAnyRawFNToRecFN.scala:196:{30,50}] assign common_overflow = _common_overflow_T_1; // @[RoundAnyRawFNToRecFN.scala:124:37, :196:50] assign _common_totalUnderflow_T = $signed(sRoundedExp) < 11'sh6B; // @[RoundAnyRawFNToRecFN.scala:185:40, :200:31] assign common_totalUnderflow = _common_totalUnderflow_T; // @[RoundAnyRawFNToRecFN.scala:125:37, :200:31] wire _unboundedRange_roundPosBit_T = adjustedSig[2]; // @[RoundAnyRawFNToRecFN.scala:114:22, :203:45] wire _unboundedRange_anyRound_T = adjustedSig[2]; // @[RoundAnyRawFNToRecFN.scala:114:22, :203:45, :205:44] wire _unboundedRange_roundPosBit_T_1 = adjustedSig[1]; // @[RoundAnyRawFNToRecFN.scala:114:22, :203:61] wire unboundedRange_roundPosBit = doShiftSigDown1 ? _unboundedRange_roundPosBit_T : _unboundedRange_roundPosBit_T_1; // @[RoundAnyRawFNToRecFN.scala:120:57, :203:{16,45,61}] wire _unboundedRange_roundIncr_T_1 = unboundedRange_roundPosBit; // @[RoundAnyRawFNToRecFN.scala:203:16, :207:67] wire _unboundedRange_anyRound_T_1 = doShiftSigDown1 & _unboundedRange_anyRound_T; // @[RoundAnyRawFNToRecFN.scala:120:57, :205:{30,44}] wire [1:0] _unboundedRange_anyRound_T_2 = adjustedSig[1:0]; // @[RoundAnyRawFNToRecFN.scala:114:22, :205:63] wire _unboundedRange_anyRound_T_3 = |_unboundedRange_anyRound_T_2; // @[RoundAnyRawFNToRecFN.scala:205:{63,70}] wire unboundedRange_anyRound = _unboundedRange_anyRound_T_1 | _unboundedRange_anyRound_T_3; // @[RoundAnyRawFNToRecFN.scala:205:{30,49,70}] wire unboundedRange_roundIncr = _unboundedRange_roundIncr_T_1; // @[RoundAnyRawFNToRecFN.scala:207:67, :208:46] wire _roundCarry_T = roundedSig[25]; // @[RoundAnyRawFNToRecFN.scala:173:16, :212:27] wire _roundCarry_T_1 = roundedSig[24]; // @[RoundAnyRawFNToRecFN.scala:173:16, :213:27] wire roundCarry = doShiftSigDown1 ? _roundCarry_T : _roundCarry_T_1; // @[RoundAnyRawFNToRecFN.scala:120:57, :211:16, :212:27, :213:27] wire [1:0] _common_underflow_T = io_in_sExp_0[9:8]; // @[RoundAnyRawFNToRecFN.scala:48:5, :220:49] wire _common_underflow_T_1 = _common_underflow_T != 2'h1; // @[RoundAnyRawFNToRecFN.scala:220:{49,64}] wire _common_underflow_T_2 = anyRound & _common_underflow_T_1; // @[RoundAnyRawFNToRecFN.scala:166:36, :220:{32,64}] wire _common_underflow_T_3 = roundMask[3]; // @[RoundAnyRawFNToRecFN.scala:159:42, :221:57] wire _common_underflow_T_9 = roundMask[3]; // @[RoundAnyRawFNToRecFN.scala:159:42, :221:57, :225:49] wire _common_underflow_T_4 = roundMask[2]; // @[RoundAnyRawFNToRecFN.scala:159:42, :221:71] wire _common_underflow_T_5 = doShiftSigDown1 ? _common_underflow_T_3 : _common_underflow_T_4; // @[RoundAnyRawFNToRecFN.scala:120:57, :221:{30,57,71}] wire _common_underflow_T_6 = _common_underflow_T_2 & _common_underflow_T_5; // @[RoundAnyRawFNToRecFN.scala:220:{32,72}, :221:30] wire _common_underflow_T_8 = roundMask[4]; // @[RoundAnyRawFNToRecFN.scala:159:42, :224:49] wire _common_underflow_T_10 = doShiftSigDown1 ? _common_underflow_T_8 : _common_underflow_T_9; // @[RoundAnyRawFNToRecFN.scala:120:57, :223:39, :224:49, :225:49] wire _common_underflow_T_11 = ~_common_underflow_T_10; // @[RoundAnyRawFNToRecFN.scala:223:{34,39}] wire _common_underflow_T_12 = _common_underflow_T_11; // @[RoundAnyRawFNToRecFN.scala:222:77, :223:34] wire _common_underflow_T_13 = _common_underflow_T_12 & roundCarry; // @[RoundAnyRawFNToRecFN.scala:211:16, :222:77, :226:38] wire _common_underflow_T_14 = _common_underflow_T_13 & roundPosBit; // @[RoundAnyRawFNToRecFN.scala:164:56, :226:38, :227:45] wire _common_underflow_T_15 = _common_underflow_T_14 & unboundedRange_roundIncr; // @[RoundAnyRawFNToRecFN.scala:208:46, :227:{45,60}] wire _common_underflow_T_16 = ~_common_underflow_T_15; // @[RoundAnyRawFNToRecFN.scala:222:27, :227:60] wire _common_underflow_T_17 = _common_underflow_T_6 & _common_underflow_T_16; // @[RoundAnyRawFNToRecFN.scala:220:72, :221:76, :222:27] assign _common_underflow_T_18 = common_totalUnderflow | _common_underflow_T_17; // @[RoundAnyRawFNToRecFN.scala:125:37, :217:40, :221:76] assign common_underflow = _common_underflow_T_18; // @[RoundAnyRawFNToRecFN.scala:126:37, :217:40] assign _common_inexact_T = common_totalUnderflow | anyRound; // @[RoundAnyRawFNToRecFN.scala:125:37, :166:36, :230:49] assign common_inexact = _common_inexact_T; // @[RoundAnyRawFNToRecFN.scala:127:37, :230:49] wire isNaNOut = io_invalidExc_0 | io_in_isNaN_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :235:34] wire _commonCase_T = ~isNaNOut; // @[RoundAnyRawFNToRecFN.scala:235:34, :237:22] wire _commonCase_T_1 = ~notNaN_isSpecialInfOut; // @[RoundAnyRawFNToRecFN.scala:236:49, :237:36] wire _commonCase_T_2 = _commonCase_T & _commonCase_T_1; // @[RoundAnyRawFNToRecFN.scala:237:{22,33,36}] wire _commonCase_T_3 = ~io_in_isZero_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :237:64] wire commonCase = _commonCase_T_2 & _commonCase_T_3; // @[RoundAnyRawFNToRecFN.scala:237:{33,61,64}] wire overflow = commonCase & common_overflow; // @[RoundAnyRawFNToRecFN.scala:124:37, :237:61, :238:32] wire _notNaN_isInfOut_T = overflow; // @[RoundAnyRawFNToRecFN.scala:238:32, :248:45] wire underflow = commonCase & common_underflow; // @[RoundAnyRawFNToRecFN.scala:126:37, :237:61, :239:32] wire _inexact_T = commonCase & common_inexact; // @[RoundAnyRawFNToRecFN.scala:127:37, :237:61, :240:43] wire inexact = overflow | _inexact_T; // @[RoundAnyRawFNToRecFN.scala:238:32, :240:{28,43}] wire _pegMinNonzeroMagOut_T = commonCase & common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:125:37, :237:61, :245:20] wire notNaN_isInfOut = notNaN_isSpecialInfOut | _notNaN_isInfOut_T; // @[RoundAnyRawFNToRecFN.scala:236:49, :248:{32,45}] wire signOut = ~isNaNOut & io_in_sign_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :235:34, :250:22] wire _expOut_T = io_in_isZero_0 | common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:48:5, :125:37, :253:32] wire [8:0] _expOut_T_1 = _expOut_T ? 9'h1C0 : 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:{18,32}] wire [8:0] _expOut_T_2 = ~_expOut_T_1; // @[RoundAnyRawFNToRecFN.scala:253:{14,18}] wire [8:0] _expOut_T_3 = common_expOut & _expOut_T_2; // @[RoundAnyRawFNToRecFN.scala:122:31, :252:24, :253:14] wire [8:0] _expOut_T_7 = _expOut_T_3; // @[RoundAnyRawFNToRecFN.scala:252:24, :256:17] wire [8:0] _expOut_T_10 = _expOut_T_7; // @[RoundAnyRawFNToRecFN.scala:256:17, :260:17] wire [8:0] _expOut_T_11 = {2'h0, notNaN_isInfOut, 6'h0}; // @[RoundAnyRawFNToRecFN.scala:248:32, :265:18] wire [8:0] _expOut_T_12 = ~_expOut_T_11; // @[RoundAnyRawFNToRecFN.scala:265:{14,18}] wire [8:0] _expOut_T_13 = _expOut_T_10 & _expOut_T_12; // @[RoundAnyRawFNToRecFN.scala:260:17, :264:17, :265:14] wire [8:0] _expOut_T_15 = _expOut_T_13; // @[RoundAnyRawFNToRecFN.scala:264:17, :268:18] wire [8:0] _expOut_T_17 = _expOut_T_15; // @[RoundAnyRawFNToRecFN.scala:268:18, :272:15] wire [8:0] _expOut_T_18 = notNaN_isInfOut ? 9'h180 : 9'h0; // @[RoundAnyRawFNToRecFN.scala:248:32, :277:16] wire [8:0] _expOut_T_19 = _expOut_T_17 | _expOut_T_18; // @[RoundAnyRawFNToRecFN.scala:272:15, :276:15, :277:16] wire [8:0] _expOut_T_20 = isNaNOut ? 9'h1C0 : 9'h0; // @[RoundAnyRawFNToRecFN.scala:235:34, :278:16] wire [8:0] expOut = _expOut_T_19 | _expOut_T_20; // @[RoundAnyRawFNToRecFN.scala:276:15, :277:73, :278:16] wire _fractOut_T = isNaNOut | io_in_isZero_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :235:34, :280:22] wire _fractOut_T_1 = _fractOut_T | common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:125:37, :280:{22,38}] wire [22:0] _fractOut_T_2 = {isNaNOut, 22'h0}; // @[RoundAnyRawFNToRecFN.scala:235:34, :281:16] wire [22:0] _fractOut_T_3 = _fractOut_T_1 ? _fractOut_T_2 : common_fractOut; // @[RoundAnyRawFNToRecFN.scala:123:31, :280:{12,38}, :281:16] wire [22:0] fractOut = _fractOut_T_3; // @[RoundAnyRawFNToRecFN.scala:280:12, :283:11] wire [9:0] _io_out_T = {signOut, expOut}; // @[RoundAnyRawFNToRecFN.scala:250:22, :277:73, :286:23] assign _io_out_T_1 = {_io_out_T, fractOut}; // @[RoundAnyRawFNToRecFN.scala:283:11, :286:{23,33}] assign io_out_0 = _io_out_T_1; // @[RoundAnyRawFNToRecFN.scala:48:5, :286:33] wire [1:0] _io_exceptionFlags_T = {io_invalidExc_0, 1'h0}; // @[RoundAnyRawFNToRecFN.scala:48:5, :288:23] wire [2:0] _io_exceptionFlags_T_1 = {_io_exceptionFlags_T, overflow}; // @[RoundAnyRawFNToRecFN.scala:238:32, :288:{23,41}] wire [3:0] _io_exceptionFlags_T_2 = {_io_exceptionFlags_T_1, underflow}; // @[RoundAnyRawFNToRecFN.scala:239:32, :288:{41,53}] assign _io_exceptionFlags_T_3 = {_io_exceptionFlags_T_2, inexact}; // @[RoundAnyRawFNToRecFN.scala:240:28, :288:{53,66}] assign io_exceptionFlags_0 = _io_exceptionFlags_T_3; // @[RoundAnyRawFNToRecFN.scala:48:5, :288:66] assign io_out = io_out_0; // @[RoundAnyRawFNToRecFN.scala:48:5] assign io_exceptionFlags = io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:48:5] endmodule

Generate the Verilog code corresponding to the following Chisel files. File Transposer.scala: package gemmini import chisel3._ import chisel3.util._ import Util._ trait Transposer[T <: Data] extends Module { def dim: Int def dataType: T val io = IO(new Bundle { val inRow = Flipped(Decoupled(Vec(dim, dataType))) val outCol = Decoupled(Vec(dim, dataType)) }) } class PipelinedTransposer[T <: Data](val dim: Int, val dataType: T) extends Transposer[T] { require(isPow2(dim)) val regArray = Seq.fill(dim, dim)(Reg(dataType)) val regArrayT = regArray.transpose val sMoveUp :: sMoveLeft :: Nil = Enum(2) val state = RegInit(sMoveUp) val leftCounter = RegInit(0.U(log2Ceil(dim+1).W)) //(io.inRow.fire && state === sMoveLeft, dim+1) val upCounter = RegInit(0.U(log2Ceil(dim+1).W)) //Counter(io.inRow.fire && state === sMoveUp, dim+1) io.outCol.valid := 0.U io.inRow.ready := 0.U switch(state) { is(sMoveUp) { io.inRow.ready := upCounter <= dim.U io.outCol.valid := leftCounter > 0.U when(io.inRow.fire) { upCounter := upCounter + 1.U } when(upCounter === (dim-1).U) { state := sMoveLeft leftCounter := 0.U } when(io.outCol.fire) { leftCounter := leftCounter - 1.U } } is(sMoveLeft) { io.inRow.ready := leftCounter <= dim.U // TODO: this is naive io.outCol.valid := upCounter > 0.U when(leftCounter === (dim-1).U) { state := sMoveUp } when(io.inRow.fire) { leftCounter := leftCounter + 1.U upCounter := 0.U } when(io.outCol.fire) { upCounter := upCounter - 1.U } } } // Propagate input from bottom row to top row systolically in the move up phase // TODO: need to iterate over columns to connect Chisel values of type T // Should be able to operate directly on the Vec, but Seq and Vec don't mix (try Array?) for (colIdx <- 0 until dim) { regArray.foldRight(io.inRow.bits(colIdx)) { case (regRow, prevReg) => when (state === sMoveUp) { regRow(colIdx) := prevReg } regRow(colIdx) } } // Propagate input from right side to left side systolically in the move left phase for (rowIdx <- 0 until dim) { regArrayT.foldRight(io.inRow.bits(rowIdx)) { case (regCol, prevReg) => when (state === sMoveLeft) { regCol(rowIdx) := prevReg } regCol(rowIdx) } } // Pull from the left side or the top side based on the state for (idx <- 0 until dim) { when (state === sMoveUp) { io.outCol.bits(idx) := regArray(0)(idx) }.elsewhen(state === sMoveLeft) { io.outCol.bits(idx) := regArrayT(0)(idx) }.otherwise { io.outCol.bits(idx) := DontCare } } } class AlwaysOutTransposer[T <: Data](val dim: Int, val dataType: T) extends Transposer[T] { require(isPow2(dim)) val LEFT_DIR = 0.U(1.W) val UP_DIR = 1.U(1.W) class PE extends Module { val io = IO(new Bundle { val inR = Input(dataType) val inD = Input(dataType) val outL = Output(dataType) val outU = Output(dataType) val dir = Input(UInt(1.W)) val en = Input(Bool()) }) val reg = RegEnable(Mux(io.dir === LEFT_DIR, io.inR, io.inD), io.en) io.outU := reg io.outL := reg } val pes = Seq.fill(dim,dim)(Module(new PE)) val counter = RegInit(0.U((log2Ceil(dim) max 1).W)) // TODO replace this with a standard Chisel counter val dir = RegInit(LEFT_DIR) // Wire up horizontal signals for (row <- 0 until dim; col <- 0 until dim) { val right_in = if (col == dim-1) io.inRow.bits(row) else pes(row)(col+1).io.outL pes(row)(col).io.inR := right_in } // Wire up vertical signals for (row <- 0 until dim; col <- 0 until dim) { val down_in = if (row == dim-1) io.inRow.bits(col) else pes(row+1)(col).io.outU pes(row)(col).io.inD := down_in } // Wire up global signals pes.flatten.foreach(_.io.dir := dir) pes.flatten.foreach(_.io.en := io.inRow.fire) io.outCol.valid := true.B io.inRow.ready := true.B val left_out = VecInit(pes.transpose.head.map(_.io.outL)) val up_out = VecInit(pes.head.map(_.io.outU)) io.outCol.bits := Mux(dir === LEFT_DIR, left_out, up_out) when (io.inRow.fire) { counter := wrappingAdd(counter, 1.U, dim) } when (counter === (dim-1).U && io.inRow.fire) { dir := ~dir } } class NaiveTransposer[T <: Data](val dim: Int, val dataType: T) extends Transposer[T] { val regArray = Seq.fill(dim, dim)(Reg(dataType)) val regArrayT = regArray.transpose // state = 0 => filling regArray row-wise, state = 1 => draining regArray column-wise val state = RegInit(0.U(1.W)) val countInc = io.inRow.fire || io.outCol.fire val (countValue, countWrap) = Counter(countInc, dim) io.inRow.ready := state === 0.U io.outCol.valid := state === 1.U for (i <- 0 until dim) { for (j <- 0 until dim) { when(countValue === i.U && io.inRow.fire) { regArray(i)(j) := io.inRow.bits(j) } } } for (i <- 0 until dim) { io.outCol.bits(i) := 0.U for (j <- 0 until dim) { when(countValue === j.U) { io.outCol.bits(i) := regArrayT(j)(i) } } } when (io.inRow.fire && countWrap) { state := 1.U } when (io.outCol.fire && countWrap) { state := 0.U } assert(!(state === 0.U) || !io.outCol.fire) assert(!(state === 1.U) || !io.inRow.fire) }

module PE_233( // @[Transposer.scala:100:9] input clock, // @[Transposer.scala:100:9] input reset, // @[Transposer.scala:100:9] input [7:0] io_inR, // @[Transposer.scala:101:16] input [7:0] io_inD, // @[Transposer.scala:101:16] output [7:0] io_outL, // @[Transposer.scala:101:16] output [7:0] io_outU, // @[Transposer.scala:101:16] input io_dir, // @[Transposer.scala:101:16] input io_en // @[Transposer.scala:101:16] ); wire [7:0] io_inR_0 = io_inR; // @[Transposer.scala:100:9] wire [7:0] io_inD_0 = io_inD; // @[Transposer.scala:100:9] wire io_dir_0 = io_dir; // @[Transposer.scala:100:9] wire io_en_0 = io_en; // @[Transposer.scala:100:9] wire [7:0] io_outL_0; // @[Transposer.scala:100:9] wire [7:0] io_outU_0; // @[Transposer.scala:100:9] wire _reg_T = ~io_dir_0; // @[Transposer.scala:100:9, :110:36] wire [7:0] _reg_T_1 = _reg_T ? io_inR_0 : io_inD_0; // @[Transposer.scala:100:9, :110:{28,36}] reg [7:0] reg_0; // @[Transposer.scala:110:24] assign io_outL_0 = reg_0; // @[Transposer.scala:100:9, :110:24] assign io_outU_0 = reg_0; // @[Transposer.scala:100:9, :110:24] always @(posedge clock) begin // @[Transposer.scala:100:9] if (io_en_0) // @[Transposer.scala:100:9] reg_0 <= _reg_T_1; // @[Transposer.scala:110:{24,28}] always @(posedge) assign io_outL = io_outL_0; // @[Transposer.scala:100:9] assign io_outU = io_outU_0; // @[Transposer.scala:100:9] endmodule

Generate the Verilog code corresponding to the following Chisel files. File Buffer.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.diplomacy.BufferParams class TLBufferNode ( a: BufferParams, b: BufferParams, c: BufferParams, d: BufferParams, e: BufferParams)(implicit valName: ValName) extends TLAdapterNode( clientFn = { p => p.v1copy(minLatency = p.minLatency + b.latency + c.latency) }, managerFn = { p => p.v1copy(minLatency = p.minLatency + a.latency + d.latency) } ) { override lazy val nodedebugstring = s"a:${a.toString}, b:${b.toString}, c:${c.toString}, d:${d.toString}, e:${e.toString}" override def circuitIdentity = List(a,b,c,d,e).forall(_ == BufferParams.none) } class TLBuffer( a: BufferParams, b: BufferParams, c: BufferParams, d: BufferParams, e: BufferParams)(implicit p: Parameters) extends LazyModule { def this(ace: BufferParams, bd: BufferParams)(implicit p: Parameters) = this(ace, bd, ace, bd, ace) def this(abcde: BufferParams)(implicit p: Parameters) = this(abcde, abcde) def this()(implicit p: Parameters) = this(BufferParams.default) val node = new TLBufferNode(a, b, c, d, e) lazy val module = new Impl class Impl extends LazyModuleImp(this) { def headBundle = node.out.head._2.bundle override def desiredName = (Seq("TLBuffer") ++ node.out.headOption.map(_._2.bundle.shortName)).mkString("_") (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out.a <> a(in .a) in .d <> d(out.d) if (edgeOut.manager.anySupportAcquireB && edgeOut.client.anySupportProbe) { in .b <> b(out.b) out.c <> c(in .c) out.e <> e(in .e) } else { in.b.valid := false.B in.c.ready := true.B in.e.ready := true.B out.b.ready := true.B out.c.valid := false.B out.e.valid := false.B } } } } object TLBuffer { def apply() (implicit p: Parameters): TLNode = apply(BufferParams.default) def apply(abcde: BufferParams) (implicit p: Parameters): TLNode = apply(abcde, abcde) def apply(ace: BufferParams, bd: BufferParams)(implicit p: Parameters): TLNode = apply(ace, bd, ace, bd, ace) def apply( a: BufferParams, b: BufferParams, c: BufferParams, d: BufferParams, e: BufferParams)(implicit p: Parameters): TLNode = { val buffer = LazyModule(new TLBuffer(a, b, c, d, e)) buffer.node } def chain(depth: Int, name: Option[String] = None)(implicit p: Parameters): Seq[TLNode] = { val buffers = Seq.fill(depth) { LazyModule(new TLBuffer()) } name.foreach { n => buffers.zipWithIndex.foreach { case (b, i) => b.suggestName(s"${n}_${i}") } } buffers.map(_.node) } def chainNode(depth: Int, name: Option[String] = None)(implicit p: Parameters): TLNode = { chain(depth, name) .reduceLeftOption(_ :*=* _) .getOrElse(TLNameNode("no_buffer")) } } File Nodes.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.nodes._ import freechips.rocketchip.util.{AsyncQueueParams,RationalDirection} case object TLMonitorBuilder extends Field[TLMonitorArgs => TLMonitorBase](args => new TLMonitor(args)) object TLImp extends NodeImp[TLMasterPortParameters, TLSlavePortParameters, TLEdgeOut, TLEdgeIn, TLBundle] { def edgeO(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeOut(pd, pu, p, sourceInfo) def edgeI(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeIn (pd, pu, p, sourceInfo) def bundleO(eo: TLEdgeOut) = TLBundle(eo.bundle) def bundleI(ei: TLEdgeIn) = TLBundle(ei.bundle) def render(ei: TLEdgeIn) = RenderedEdge(colour = "#000000" /* black */, label = (ei.manager.beatBytes * 8).toString) override def monitor(bundle: TLBundle, edge: TLEdgeIn): Unit = { val monitor = Module(edge.params(TLMonitorBuilder)(TLMonitorArgs(edge))) monitor.io.in := bundle } override def mixO(pd: TLMasterPortParameters, node: OutwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLMasterPortParameters = pd.v1copy(clients = pd.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }) override def mixI(pu: TLSlavePortParameters, node: InwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLSlavePortParameters = pu.v1copy(managers = pu.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }) } trait TLFormatNode extends FormatNode[TLEdgeIn, TLEdgeOut] case class TLClientNode(portParams: Seq[TLMasterPortParameters])(implicit valName: ValName) extends SourceNode(TLImp)(portParams) with TLFormatNode case class TLManagerNode(portParams: Seq[TLSlavePortParameters])(implicit valName: ValName) extends SinkNode(TLImp)(portParams) with TLFormatNode case class TLAdapterNode( clientFn: TLMasterPortParameters => TLMasterPortParameters = { s => s }, managerFn: TLSlavePortParameters => TLSlavePortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLImp)(clientFn, managerFn) with TLFormatNode case class TLJunctionNode( clientFn: Seq[TLMasterPortParameters] => Seq[TLMasterPortParameters], managerFn: Seq[TLSlavePortParameters] => Seq[TLSlavePortParameters])( implicit valName: ValName) extends JunctionNode(TLImp)(clientFn, managerFn) with TLFormatNode case class TLIdentityNode()(implicit valName: ValName) extends IdentityNode(TLImp)() with TLFormatNode object TLNameNode { def apply(name: ValName) = TLIdentityNode()(name) def apply(name: Option[String]): TLIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLIdentityNode = apply(Some(name)) } case class TLEphemeralNode()(implicit valName: ValName) extends EphemeralNode(TLImp)() object TLTempNode { def apply(): TLEphemeralNode = TLEphemeralNode()(ValName("temp")) } case class TLNexusNode( clientFn: Seq[TLMasterPortParameters] => TLMasterPortParameters, managerFn: Seq[TLSlavePortParameters] => TLSlavePortParameters)( implicit valName: ValName) extends NexusNode(TLImp)(clientFn, managerFn) with TLFormatNode abstract class TLCustomNode(implicit valName: ValName) extends CustomNode(TLImp) with TLFormatNode // Asynchronous crossings trait TLAsyncFormatNode extends FormatNode[TLAsyncEdgeParameters, TLAsyncEdgeParameters] object TLAsyncImp extends SimpleNodeImp[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncEdgeParameters, TLAsyncBundle] { def edge(pd: TLAsyncClientPortParameters, pu: TLAsyncManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLAsyncEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLAsyncEdgeParameters) = new TLAsyncBundle(e.bundle) def render(e: TLAsyncEdgeParameters) = RenderedEdge(colour = "#ff0000" /* red */, label = e.manager.async.depth.toString) override def mixO(pd: TLAsyncClientPortParameters, node: OutwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLAsyncManagerPortParameters, node: InwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLAsyncAdapterNode( clientFn: TLAsyncClientPortParameters => TLAsyncClientPortParameters = { s => s }, managerFn: TLAsyncManagerPortParameters => TLAsyncManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLAsyncImp)(clientFn, managerFn) with TLAsyncFormatNode case class TLAsyncIdentityNode()(implicit valName: ValName) extends IdentityNode(TLAsyncImp)() with TLAsyncFormatNode object TLAsyncNameNode { def apply(name: ValName) = TLAsyncIdentityNode()(name) def apply(name: Option[String]): TLAsyncIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLAsyncIdentityNode = apply(Some(name)) } case class TLAsyncSourceNode(sync: Option[Int])(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLAsyncImp)( dFn = { p => TLAsyncClientPortParameters(p) }, uFn = { p => p.base.v1copy(minLatency = p.base.minLatency + sync.getOrElse(p.async.sync)) }) with FormatNode[TLEdgeIn, TLAsyncEdgeParameters] // discard cycles in other clock domain case class TLAsyncSinkNode(async: AsyncQueueParams)(implicit valName: ValName) extends MixedAdapterNode(TLAsyncImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = p.base.minLatency + async.sync) }, uFn = { p => TLAsyncManagerPortParameters(async, p) }) with FormatNode[TLAsyncEdgeParameters, TLEdgeOut] // Rationally related crossings trait TLRationalFormatNode extends FormatNode[TLRationalEdgeParameters, TLRationalEdgeParameters] object TLRationalImp extends SimpleNodeImp[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalEdgeParameters, TLRationalBundle] { def edge(pd: TLRationalClientPortParameters, pu: TLRationalManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLRationalEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLRationalEdgeParameters) = new TLRationalBundle(e.bundle) def render(e: TLRationalEdgeParameters) = RenderedEdge(colour = "#00ff00" /* green */) override def mixO(pd: TLRationalClientPortParameters, node: OutwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLRationalManagerPortParameters, node: InwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLRationalAdapterNode( clientFn: TLRationalClientPortParameters => TLRationalClientPortParameters = { s => s }, managerFn: TLRationalManagerPortParameters => TLRationalManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLRationalImp)(clientFn, managerFn) with TLRationalFormatNode case class TLRationalIdentityNode()(implicit valName: ValName) extends IdentityNode(TLRationalImp)() with TLRationalFormatNode object TLRationalNameNode { def apply(name: ValName) = TLRationalIdentityNode()(name) def apply(name: Option[String]): TLRationalIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLRationalIdentityNode = apply(Some(name)) } case class TLRationalSourceNode()(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLRationalImp)( dFn = { p => TLRationalClientPortParameters(p) }, uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLRationalEdgeParameters] // discard cycles from other clock domain case class TLRationalSinkNode(direction: RationalDirection)(implicit valName: ValName) extends MixedAdapterNode(TLRationalImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = 1) }, uFn = { p => TLRationalManagerPortParameters(direction, p) }) with FormatNode[TLRationalEdgeParameters, TLEdgeOut] // Credited version of TileLink channels trait TLCreditedFormatNode extends FormatNode[TLCreditedEdgeParameters, TLCreditedEdgeParameters] object TLCreditedImp extends SimpleNodeImp[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedEdgeParameters, TLCreditedBundle] { def edge(pd: TLCreditedClientPortParameters, pu: TLCreditedManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLCreditedEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLCreditedEdgeParameters) = new TLCreditedBundle(e.bundle) def render(e: TLCreditedEdgeParameters) = RenderedEdge(colour = "#ffff00" /* yellow */, e.delay.toString) override def mixO(pd: TLCreditedClientPortParameters, node: OutwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLCreditedManagerPortParameters, node: InwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLCreditedAdapterNode( clientFn: TLCreditedClientPortParameters => TLCreditedClientPortParameters = { s => s }, managerFn: TLCreditedManagerPortParameters => TLCreditedManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLCreditedImp)(clientFn, managerFn) with TLCreditedFormatNode case class TLCreditedIdentityNode()(implicit valName: ValName) extends IdentityNode(TLCreditedImp)() with TLCreditedFormatNode object TLCreditedNameNode { def apply(name: ValName) = TLCreditedIdentityNode()(name) def apply(name: Option[String]): TLCreditedIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLCreditedIdentityNode = apply(Some(name)) } case class TLCreditedSourceNode(delay: TLCreditedDelay)(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLCreditedImp)( dFn = { p => TLCreditedClientPortParameters(delay, p) }, uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLCreditedEdgeParameters] // discard cycles from other clock domain case class TLCreditedSinkNode(delay: TLCreditedDelay)(implicit valName: ValName) extends MixedAdapterNode(TLCreditedImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = 1) }, uFn = { p => TLCreditedManagerPortParameters(delay, p) }) with FormatNode[TLCreditedEdgeParameters, TLEdgeOut] File LazyModuleImp.scala: package org.chipsalliance.diplomacy.lazymodule import chisel3.{withClockAndReset, Module, RawModule, Reset, _} import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo} import firrtl.passes.InlineAnnotation import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.nodes.Dangle import scala.collection.immutable.SortedMap /** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]]. * * This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy. */ sealed trait LazyModuleImpLike extends RawModule { /** [[LazyModule]] that contains this instance. */ val wrapper: LazyModule /** IOs that will be automatically "punched" for this instance. */ val auto: AutoBundle /** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */ protected[diplomacy] val dangles: Seq[Dangle] // [[wrapper.module]] had better not be accessed while LazyModules are still being built! require( LazyModule.scope.isEmpty, s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}" ) /** Set module name. Defaults to the containing LazyModule's desiredName. */ override def desiredName: String = wrapper.desiredName suggestName(wrapper.suggestedName) /** [[Parameters]] for chisel [[Module]]s. */ implicit val p: Parameters = wrapper.p /** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and * submodules. */ protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = { // 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]], // 2. return [[Dangle]]s from each module. val childDangles = wrapper.children.reverse.flatMap { c => implicit val sourceInfo: SourceInfo = c.info c.cloneProto.map { cp => // If the child is a clone, then recursively set cloneProto of its children as well def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = { require(bases.size == clones.size) (bases.zip(clones)).map { case (l, r) => require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}") l.cloneProto = Some(r) assignCloneProtos(l.children, r.children) } } assignCloneProtos(c.children, cp.children) // Clone the child module as a record, and get its [[AutoBundle]] val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName) val clonedAuto = clone("auto").asInstanceOf[AutoBundle] // Get the empty [[Dangle]]'s of the cloned child val rawDangles = c.cloneDangles() require(rawDangles.size == clonedAuto.elements.size) // Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) } dangles }.getOrElse { // For non-clones, instantiate the child module val mod = try { Module(c.module) } catch { case e: ChiselException => { println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}") throw e } } mod.dangles } } // Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]]. // This will result in a sequence of [[Dangle]] from these [[BaseNode]]s. val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate()) // Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]] val allDangles = nodeDangles ++ childDangles // Group [[allDangles]] by their [[source]]. val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*) // For each [[source]] set of [[Dangle]]s of size 2, ensure that these // can be connected as a source-sink pair (have opposite flipped value). // Make the connection and mark them as [[done]]. val done = Set() ++ pairing.values.filter(_.size == 2).map { case Seq(a, b) => require(a.flipped != b.flipped) // @todo <> in chisel3 makes directionless connection. if (a.flipped) { a.data <> b.data } else { b.data <> a.data } a.source case _ => None } // Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module. val forward = allDangles.filter(d => !done(d.source)) // Generate [[AutoBundle]] IO from [[forward]]. val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*)) // Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]] val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) => if (d.flipped) { d.data <> io } else { io <> d.data } d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name) } // Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]]. wrapper.inModuleBody.reverse.foreach { _() } if (wrapper.shouldBeInlined) { chisel3.experimental.annotate(new ChiselAnnotation { def toFirrtl = InlineAnnotation(toNamed) }) } // Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]]. (auto, dangles) } } /** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike { /** Instantiate hardware of this `Module`. */ val (auto, dangles) = instantiate() } /** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike { // These wires are the default clock+reset for all LazyModule children. // It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the // [[LazyRawModuleImp]] children. // Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly. /** drive clock explicitly. */ val childClock: Clock = Wire(Clock()) /** drive reset explicitly. */ val childReset: Reset = Wire(Reset()) // the default is that these are disabled childClock := false.B.asClock childReset := chisel3.DontCare def provideImplicitClockToLazyChildren: Boolean = false val (auto, dangles) = if (provideImplicitClockToLazyChildren) { withClockAndReset(childClock, childReset) { instantiate() } } else { instantiate() } } File MixedNode.scala: package org.chipsalliance.diplomacy.nodes import chisel3.{Data, DontCare, Wire} import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.{Field, Parameters} import org.chipsalliance.diplomacy.ValName import org.chipsalliance.diplomacy.sourceLine /** One side metadata of a [[Dangle]]. * * Describes one side of an edge going into or out of a [[BaseNode]]. * * @param serial * the global [[BaseNode.serial]] number of the [[BaseNode]] that this [[HalfEdge]] connects to. * @param index * the `index` in the [[BaseNode]]'s input or output port list that this [[HalfEdge]] belongs to. */ case class HalfEdge(serial: Int, index: Int) extends Ordered[HalfEdge] { import scala.math.Ordered.orderingToOrdered def compare(that: HalfEdge): Int = HalfEdge.unapply(this).compare(HalfEdge.unapply(that)) } /** [[Dangle]] captures the `IO` information of a [[LazyModule]] and which two [[BaseNode]]s the [[Edges]]/[[Bundle]] * connects. * * [[Dangle]]s are generated by [[BaseNode.instantiate]] using [[MixedNode.danglesOut]] and [[MixedNode.danglesIn]] , * [[LazyModuleImp.instantiate]] connects those that go to internal or explicit IO connections in a [[LazyModule]]. * * @param source * the source [[HalfEdge]] of this [[Dangle]], which captures the source [[BaseNode]] and the port `index` within * that [[BaseNode]]. * @param sink * sink [[HalfEdge]] of this [[Dangle]], which captures the sink [[BaseNode]] and the port `index` within that * [[BaseNode]]. * @param flipped * flip or not in [[AutoBundle.makeElements]]. If true this corresponds to `danglesOut`, if false it corresponds to * `danglesIn`. * @param dataOpt * actual [[Data]] for the hardware connection. Can be empty if this belongs to a cloned module */ case class Dangle(source: HalfEdge, sink: HalfEdge, flipped: Boolean, name: String, dataOpt: Option[Data]) { def data = dataOpt.get } /** [[Edges]] is a collection of parameters describing the functionality and connection for an interface, which is often * derived from the interconnection protocol and can inform the parameterization of the hardware bundles that actually * implement the protocol. */ case class Edges[EI, EO](in: Seq[EI], out: Seq[EO]) /** A field available in [[Parameters]] used to determine whether [[InwardNodeImp.monitor]] will be called. */ case object MonitorsEnabled extends Field[Boolean](true) /** When rendering the edge in a graphical format, flip the order in which the edges' source and sink are presented. * * For example, when rendering graphML, yEd by default tries to put the source node vertically above the sink node, but * [[RenderFlipped]] inverts this relationship. When a particular [[LazyModule]] contains both source nodes and sink * nodes, flipping the rendering of one node's edge will usual produce a more concise visual layout for the * [[LazyModule]]. */ case object RenderFlipped extends Field[Boolean](false) /** The sealed node class in the package, all node are derived from it. * * @param inner * Sink interface implementation. * @param outer * Source interface implementation. * @param valName * val name of this node. * @tparam DI * Downward-flowing parameters received on the inner side of the node. It is usually a brunch of parameters * describing the protocol parameters from a source. For an [[InwardNode]], it is determined by the connected * [[OutwardNode]]. Since it can be connected to multiple sources, this parameter is always a Seq of source port * parameters. * @tparam UI * Upward-flowing parameters generated by the inner side of the node. It is usually a brunch of parameters describing * the protocol parameters of a sink. For an [[InwardNode]], it is determined itself. * @tparam EI * Edge Parameters describing a connection on the inner side of the node. It is usually a brunch of transfers * specified for a sink according to protocol. * @tparam BI * Bundle type used when connecting to the inner side of the node. It is a hardware interface of this sink interface. * It should extends from [[chisel3.Data]], which represents the real hardware. * @tparam DO * Downward-flowing parameters generated on the outer side of the node. It is usually a brunch of parameters * describing the protocol parameters of a source. For an [[OutwardNode]], it is determined itself. * @tparam UO * Upward-flowing parameters received by the outer side of the node. It is usually a brunch of parameters describing * the protocol parameters from a sink. For an [[OutwardNode]], it is determined by the connected [[InwardNode]]. * Since it can be connected to multiple sinks, this parameter is always a Seq of sink port parameters. * @tparam EO * Edge Parameters describing a connection on the outer side of the node. It is usually a brunch of transfers * specified for a source according to protocol. * @tparam BO * Bundle type used when connecting to the outer side of the node. It is a hardware interface of this source * interface. It should extends from [[chisel3.Data]], which represents the real hardware. * * @note * Call Graph of [[MixedNode]] * - line `─`: source is process by a function and generate pass to others * - Arrow `→`: target of arrow is generated by source * * {{{ * (from the other node) * ┌─────────────────────────────────────────────────────────[[InwardNode.uiParams]]─────────────┐ * ↓ │ * (binding node when elaboration) [[OutwardNode.uoParams]]────────────────────────[[MixedNode.mapParamsU]]→──────────┐ │ * [[InwardNode.accPI]] │ │ │ * │ │ (based on protocol) │ * │ │ [[MixedNode.inner.edgeI]] │ * │ │ ↓ │ * ↓ │ │ │ * (immobilize after elaboration) (inward port from [[OutwardNode]]) │ ↓ │ * [[InwardNode.iBindings]]──┐ [[MixedNode.iDirectPorts]]────────────────────→[[MixedNode.iPorts]] [[InwardNode.uiParams]] │ * │ │ ↑ │ │ │ * │ │ │ [[OutwardNode.doParams]] │ │ * │ │ │ (from the other node) │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * │ │ │ └────────┬──────────────┤ │ * │ │ │ │ │ │ * │ │ │ │ (based on protocol) │ * │ │ │ │ [[MixedNode.inner.edgeI]] │ * │ │ │ │ │ │ * │ │ (from the other node) │ ↓ │ * │ └───[[OutwardNode.oPortMapping]] [[OutwardNode.oStar]] │ [[MixedNode.edgesIn]]───┐ │ * │ ↑ ↑ │ │ ↓ │ * │ │ │ │ │ [[MixedNode.in]] │ * │ │ │ │ ↓ ↑ │ * │ (solve star connection) │ │ │ [[MixedNode.bundleIn]]──┘ │ * ├───[[MixedNode.resolveStar]]→─┼─────────────────────────────┤ └────────────────────────────────────┐ │ * │ │ │ [[MixedNode.bundleOut]]─┐ │ │ * │ │ │ ↑ ↓ │ │ * │ │ │ │ [[MixedNode.out]] │ │ * │ ↓ ↓ │ ↑ │ │ * │ ┌─────[[InwardNode.iPortMapping]] [[InwardNode.iStar]] [[MixedNode.edgesOut]]──┘ │ │ * │ │ (from the other node) ↑ │ │ * │ │ │ │ │ │ * │ │ │ [[MixedNode.outer.edgeO]] │ │ * │ │ │ (based on protocol) │ │ * │ │ │ │ │ │ * │ │ │ ┌────────────────────────────────────────┤ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * (immobilize after elaboration)│ ↓ │ │ │ │ * [[OutwardNode.oBindings]]─┘ [[MixedNode.oDirectPorts]]───→[[MixedNode.oPorts]] [[OutwardNode.doParams]] │ │ * ↑ (inward port from [[OutwardNode]]) │ │ │ │ * │ ┌─────────────────────────────────────────┤ │ │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * [[OutwardNode.accPO]] │ ↓ │ │ │ * (binding node when elaboration) │ [[InwardNode.diParams]]─────→[[MixedNode.mapParamsD]]────────────────────────────┘ │ │ * │ ↑ │ │ * │ └──────────────────────────────────────────────────────────────────────────────────────────┘ │ * └──────────────────────────────────────────────────────────────────────────────────────────────────────────┘ * }}} */ abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data]( val inner: InwardNodeImp[DI, UI, EI, BI], val outer: OutwardNodeImp[DO, UO, EO, BO] )( implicit valName: ValName) extends BaseNode with NodeHandle[DI, UI, EI, BI, DO, UO, EO, BO] with InwardNode[DI, UI, BI] with OutwardNode[DO, UO, BO] { // Generate a [[NodeHandle]] with inward and outward node are both this node. val inward = this val outward = this /** Debug info of nodes binding. */ def bindingInfo: String = s"""$iBindingInfo |$oBindingInfo |""".stripMargin /** Debug info of ports connecting. */ def connectedPortsInfo: String = s"""${oPorts.size} outward ports connected: [${oPorts.map(_._2.name).mkString(",")}] |${iPorts.size} inward ports connected: [${iPorts.map(_._2.name).mkString(",")}] |""".stripMargin /** Debug info of parameters propagations. */ def parametersInfo: String = s"""${doParams.size} downstream outward parameters: [${doParams.mkString(",")}] |${uoParams.size} upstream outward parameters: [${uoParams.mkString(",")}] |${diParams.size} downstream inward parameters: [${diParams.mkString(",")}] |${uiParams.size} upstream inward parameters: [${uiParams.mkString(",")}] |""".stripMargin /** For a given node, converts [[OutwardNode.accPO]] and [[InwardNode.accPI]] to [[MixedNode.oPortMapping]] and * [[MixedNode.iPortMapping]]. * * Given counts of known inward and outward binding and inward and outward star bindings, return the resolved inward * stars and outward stars. * * This method will also validate the arguments and throw a runtime error if the values are unsuitable for this type * of node. * * @param iKnown * Number of known-size ([[BIND_ONCE]]) input bindings. * @param oKnown * Number of known-size ([[BIND_ONCE]]) output bindings. * @param iStar * Number of unknown size ([[BIND_STAR]]) input bindings. * @param oStar * Number of unknown size ([[BIND_STAR]]) output bindings. * @return * A Tuple of the resolved number of input and output connections. */ protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStar: Int, oStar: Int): (Int, Int) /** Function to generate downward-flowing outward params from the downward-flowing input params and the current output * ports. * * @param n * The size of the output sequence to generate. * @param p * Sequence of downward-flowing input parameters of this node. * @return * A `n`-sized sequence of downward-flowing output edge parameters. */ protected[diplomacy] def mapParamsD(n: Int, p: Seq[DI]): Seq[DO] /** Function to generate upward-flowing input parameters from the upward-flowing output parameters [[uiParams]]. * * @param n * Size of the output sequence. * @param p * Upward-flowing output edge parameters. * @return * A n-sized sequence of upward-flowing input edge parameters. */ protected[diplomacy] def mapParamsU(n: Int, p: Seq[UO]): Seq[UI] /** @return * The sink cardinality of the node, the number of outputs bound with [[BIND_QUERY]] summed with inputs bound with * [[BIND_STAR]]. */ protected[diplomacy] lazy val sinkCard: Int = oBindings.count(_._3 == BIND_QUERY) + iBindings.count(_._3 == BIND_STAR) /** @return * The source cardinality of this node, the number of inputs bound with [[BIND_QUERY]] summed with the number of * output bindings bound with [[BIND_STAR]]. */ protected[diplomacy] lazy val sourceCard: Int = iBindings.count(_._3 == BIND_QUERY) + oBindings.count(_._3 == BIND_STAR) /** @return list of nodes involved in flex bindings with this node. */ protected[diplomacy] lazy val flexes: Seq[BaseNode] = oBindings.filter(_._3 == BIND_FLEX).map(_._2) ++ iBindings.filter(_._3 == BIND_FLEX).map(_._2) /** Resolves the flex to be either source or sink and returns the offset where the [[BIND_STAR]] operators begin * greedily taking up the remaining connections. * * @return * A value >= 0 if it is sink cardinality, a negative value for source cardinality. The magnitude of the return * value is not relevant. */ protected[diplomacy] lazy val flexOffset: Int = { /** Recursively performs a depth-first search of the [[flexes]], [[BaseNode]]s connected to this node with flex * operators. The algorithm bottoms out when we either get to a node we have already visited or when we get to a * connection that is not a flex and can set the direction for us. Otherwise, recurse by visiting the `flexes` of * each node in the current set and decide whether they should be added to the set or not. * * @return * the mapping of [[BaseNode]] indexed by their serial numbers. */ def DFS(v: BaseNode, visited: Map[Int, BaseNode]): Map[Int, BaseNode] = { if (visited.contains(v.serial) || !v.flexibleArityDirection) { visited } else { v.flexes.foldLeft(visited + (v.serial -> v))((sum, n) => DFS(n, sum)) } } /** Determine which [[BaseNode]] are involved in resolving the flex connections to/from this node. * * @example * {{{ * a :*=* b :*=* c * d :*=* b * e :*=* f * }}} * * `flexSet` for `a`, `b`, `c`, or `d` will be `Set(a, b, c, d)` `flexSet` for `e` or `f` will be `Set(e,f)` */ val flexSet = DFS(this, Map()).values /** The total number of :*= operators where we're on the left. */ val allSink = flexSet.map(_.sinkCard).sum /** The total number of :=* operators used when we're on the right. */ val allSource = flexSet.map(_.sourceCard).sum require( allSink == 0 || allSource == 0, s"The nodes ${flexSet.map(_.name)} which are inter-connected by :*=* have ${allSink} :*= operators and ${allSource} :=* operators connected to them, making it impossible to determine cardinality inference direction." ) allSink - allSource } /** @return A value >= 0 if it is sink cardinality, a negative value for source cardinality. */ protected[diplomacy] def edgeArityDirection(n: BaseNode): Int = { if (flexibleArityDirection) flexOffset else if (n.flexibleArityDirection) n.flexOffset else 0 } /** For a node which is connected between two nodes, select the one that will influence the direction of the flex * resolution. */ protected[diplomacy] def edgeAritySelect(n: BaseNode, l: => Int, r: => Int): Int = { val dir = edgeArityDirection(n) if (dir < 0) l else if (dir > 0) r else 1 } /** Ensure that the same node is not visited twice in resolving `:*=`, etc operators. */ private var starCycleGuard = false /** Resolve all the star operators into concrete indicies. As connections are being made, some may be "star" * connections which need to be resolved. In some way to determine how many actual edges they correspond to. We also * need to build up the ranges of edges which correspond to each binding operator, so that We can apply the correct * edge parameters and later build up correct bundle connections. * * [[oPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that oPort (binding * operator). [[iPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that iPort * (binding operator). [[oStar]]: `Int` the value to return for this node `N` for any `N :*= foo` or `N :*=* foo :*= * bar` [[iStar]]: `Int` the value to return for this node `N` for any `foo :=* N` or `bar :=* foo :*=* N` */ protected[diplomacy] lazy val ( oPortMapping: Seq[(Int, Int)], iPortMapping: Seq[(Int, Int)], oStar: Int, iStar: Int ) = { try { if (starCycleGuard) throw StarCycleException() starCycleGuard = true // For a given node N... // Number of foo :=* N // + Number of bar :=* foo :*=* N val oStars = oBindings.count { case (_, n, b, _, _) => b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) < 0) } // Number of N :*= foo // + Number of N :*=* foo :*= bar val iStars = iBindings.count { case (_, n, b, _, _) => b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) > 0) } // 1 for foo := N // + bar.iStar for bar :*= foo :*=* N // + foo.iStar for foo :*= N // + 0 for foo :=* N val oKnown = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, 0, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => 0 } }.sum // 1 for N := foo // + bar.oStar for N :*=* foo :=* bar // + foo.oStar for N :=* foo // + 0 for N :*= foo val iKnown = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, 0) case BIND_QUERY => n.oStar case BIND_STAR => 0 } }.sum // Resolve star depends on the node subclass to implement the algorithm for this. val (iStar, oStar) = resolveStar(iKnown, oKnown, iStars, oStars) // Cumulative list of resolved outward binding range starting points val oSum = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, oStar, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => oStar } }.scanLeft(0)(_ + _) // Cumulative list of resolved inward binding range starting points val iSum = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, iStar) case BIND_QUERY => n.oStar case BIND_STAR => iStar } }.scanLeft(0)(_ + _) // Create ranges for each binding based on the running sums and return // those along with resolved values for the star operations. (oSum.init.zip(oSum.tail), iSum.init.zip(iSum.tail), oStar, iStar) } catch { case c: StarCycleException => throw c.copy(loop = context +: c.loop) } } /** Sequence of inward ports. * * This should be called after all star bindings are resolved. * * Each element is: `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. * `n` Instance of inward node. `p` View of [[Parameters]] where this connection was made. `s` Source info where this * connection was made in the source code. */ protected[diplomacy] lazy val oDirectPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oBindings.flatMap { case (i, n, _, p, s) => // for each binding operator in this node, look at what it connects to val (start, end) = n.iPortMapping(i) (start until end).map { j => (j, n, p, s) } } /** Sequence of outward ports. * * This should be called after all star bindings are resolved. * * `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. `n` Instance of * outward node. `p` View of [[Parameters]] where this connection was made. `s` [[SourceInfo]] where this connection * was made in the source code. */ protected[diplomacy] lazy val iDirectPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iBindings.flatMap { case (i, n, _, p, s) => // query this port index range of this node in the other side of node. val (start, end) = n.oPortMapping(i) (start until end).map { j => (j, n, p, s) } } // Ephemeral nodes ( which have non-None iForward/oForward) have in_degree = out_degree // Thus, there must exist an Eulerian path and the below algorithms terminate @scala.annotation.tailrec private def oTrace( tuple: (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) ): (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.iForward(i) match { case None => (i, n, p, s) case Some((j, m)) => oTrace((j, m, p, s)) } } @scala.annotation.tailrec private def iTrace( tuple: (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) ): (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.oForward(i) match { case None => (i, n, p, s) case Some((j, m)) => iTrace((j, m, p, s)) } } /** Final output ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - Numeric index of this binding in the [[InwardNode]] on the other end. * - [[InwardNode]] on the other end of this binding. * - A view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. */ lazy val oPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oDirectPorts.map(oTrace) /** Final input ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - numeric index of this binding in [[OutwardNode]] on the other end. * - [[OutwardNode]] on the other end of this binding. * - a view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. */ lazy val iPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iDirectPorts.map(iTrace) private var oParamsCycleGuard = false protected[diplomacy] lazy val diParams: Seq[DI] = iPorts.map { case (i, n, _, _) => n.doParams(i) } protected[diplomacy] lazy val doParams: Seq[DO] = { try { if (oParamsCycleGuard) throw DownwardCycleException() oParamsCycleGuard = true val o = mapParamsD(oPorts.size, diParams) require( o.size == oPorts.size, s"""Diplomacy has detected a problem with your graph: |At the following node, the number of outward ports should equal the number of produced outward parameters. |$context |$connectedPortsInfo |Downstreamed inward parameters: [${diParams.mkString(",")}] |Produced outward parameters: [${o.mkString(",")}] |""".stripMargin ) o.map(outer.mixO(_, this)) } catch { case c: DownwardCycleException => throw c.copy(loop = context +: c.loop) } } private var iParamsCycleGuard = false protected[diplomacy] lazy val uoParams: Seq[UO] = oPorts.map { case (o, n, _, _) => n.uiParams(o) } protected[diplomacy] lazy val uiParams: Seq[UI] = { try { if (iParamsCycleGuard) throw UpwardCycleException() iParamsCycleGuard = true val i = mapParamsU(iPorts.size, uoParams) require( i.size == iPorts.size, s"""Diplomacy has detected a problem with your graph: |At the following node, the number of inward ports should equal the number of produced inward parameters. |$context |$connectedPortsInfo |Upstreamed outward parameters: [${uoParams.mkString(",")}] |Produced inward parameters: [${i.mkString(",")}] |""".stripMargin ) i.map(inner.mixI(_, this)) } catch { case c: UpwardCycleException => throw c.copy(loop = context +: c.loop) } } /** Outward edge parameters. */ protected[diplomacy] lazy val edgesOut: Seq[EO] = (oPorts.zip(doParams)).map { case ((i, n, p, s), o) => outer.edgeO(o, n.uiParams(i), p, s) } /** Inward edge parameters. */ protected[diplomacy] lazy val edgesIn: Seq[EI] = (iPorts.zip(uiParams)).map { case ((o, n, p, s), i) => inner.edgeI(n.doParams(o), i, p, s) } /** A tuple of the input edge parameters and output edge parameters for the edges bound to this node. * * If you need to access to the edges of a foreign Node, use this method (in/out create bundles). */ lazy val edges: Edges[EI, EO] = Edges(edgesIn, edgesOut) /** Create actual Wires corresponding to the Bundles parameterized by the outward edges of this node. */ protected[diplomacy] lazy val bundleOut: Seq[BO] = edgesOut.map { e => val x = Wire(outer.bundleO(e)).suggestName(s"${valName.value}Out") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } /** Create actual Wires corresponding to the Bundles parameterized by the inward edges of this node. */ protected[diplomacy] lazy val bundleIn: Seq[BI] = edgesIn.map { e => val x = Wire(inner.bundleI(e)).suggestName(s"${valName.value}In") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } private def emptyDanglesOut: Seq[Dangle] = oPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(serial, i), sink = HalfEdge(n.serial, j), flipped = false, name = wirePrefix + "out", dataOpt = None ) } private def emptyDanglesIn: Seq[Dangle] = iPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(n.serial, j), sink = HalfEdge(serial, i), flipped = true, name = wirePrefix + "in", dataOpt = None ) } /** Create the [[Dangle]]s which describe the connections from this node output to other nodes inputs. */ protected[diplomacy] def danglesOut: Seq[Dangle] = emptyDanglesOut.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleOut(i))) } /** Create the [[Dangle]]s which describe the connections from this node input from other nodes outputs. */ protected[diplomacy] def danglesIn: Seq[Dangle] = emptyDanglesIn.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleIn(i))) } private[diplomacy] var instantiated = false /** Gather Bundle and edge parameters of outward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. */ def out: Seq[(BO, EO)] = { require( instantiated, s"$name.out should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleOut.zip(edgesOut) } /** Gather Bundle and edge parameters of inward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. */ def in: Seq[(BI, EI)] = { require( instantiated, s"$name.in should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleIn.zip(edgesIn) } /** Actually instantiate this node during [[LazyModuleImp]] evaluation. Mark that it's safe to use the Bundle wires, * instantiate monitors on all input ports if appropriate, and return all the dangles of this node. */ protected[diplomacy] def instantiate(): Seq[Dangle] = { instantiated = true if (!circuitIdentity) { (iPorts.zip(in)).foreach { case ((_, _, p, _), (b, e)) => if (p(MonitorsEnabled)) inner.monitor(b, e) } } danglesOut ++ danglesIn } protected[diplomacy] def cloneDangles(): Seq[Dangle] = emptyDanglesOut ++ emptyDanglesIn /** Connects the outward part of a node with the inward part of this node. */ protected[diplomacy] def bind( h: OutwardNode[DI, UI, BI], binding: NodeBinding )( implicit p: Parameters, sourceInfo: SourceInfo ): Unit = { val x = this // x := y val y = h sourceLine(sourceInfo, " at ", "") val i = x.iPushed val o = y.oPushed y.oPush( i, x, binding match { case BIND_ONCE => BIND_ONCE case BIND_FLEX => BIND_FLEX case BIND_STAR => BIND_QUERY case BIND_QUERY => BIND_STAR } ) x.iPush(o, y, binding) } /* Metadata for printing the node graph. */ def inputs: Seq[(OutwardNode[DI, UI, BI], RenderedEdge)] = (iPorts.zip(edgesIn)).map { case ((_, n, p, _), e) => val re = inner.render(e) (n, re.copy(flipped = re.flipped != p(RenderFlipped))) } /** Metadata for printing the node graph */ def outputs: Seq[(InwardNode[DO, UO, BO], RenderedEdge)] = oPorts.map { case (i, n, _, _) => (n, n.inputs(i)._2) } }

module TLBuffer_a32d128s2k4z4c_1( // @[Buffer.scala:40:9] input clock, // @[Buffer.scala:40:9] input reset, // @[Buffer.scala:40:9] output auto_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [1:0] auto_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [15:0] auto_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [127:0] auto_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_in_b_ready, // @[LazyModuleImp.scala:107:25] output auto_in_b_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_b_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_b_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_in_b_bits_size, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_b_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_in_b_bits_address, // @[LazyModuleImp.scala:107:25] output [15:0] auto_in_b_bits_mask, // @[LazyModuleImp.scala:107:25] output [127:0] auto_in_b_bits_data, // @[LazyModuleImp.scala:107:25] output auto_in_b_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_in_c_ready, // @[LazyModuleImp.scala:107:25] input auto_in_c_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_c_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_c_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_in_c_bits_size, // @[LazyModuleImp.scala:107:25] input [1:0] auto_in_c_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_in_c_bits_address, // @[LazyModuleImp.scala:107:25] input [127:0] auto_in_c_bits_data, // @[LazyModuleImp.scala:107:25] input auto_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_d_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output [3:0] auto_in_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [127:0] auto_in_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_in_e_ready, // @[LazyModuleImp.scala:107:25] input auto_in_e_valid, // @[LazyModuleImp.scala:107:25] input [3:0] auto_in_e_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [1:0] auto_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [15:0] auto_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [127:0] auto_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_out_b_ready, // @[LazyModuleImp.scala:107:25] input auto_out_b_valid, // @[LazyModuleImp.scala:107:25] input [1:0] auto_out_b_bits_param, // @[LazyModuleImp.scala:107:25] input [1:0] auto_out_b_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_out_b_bits_address, // @[LazyModuleImp.scala:107:25] input auto_out_c_ready, // @[LazyModuleImp.scala:107:25] output auto_out_c_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_c_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_c_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_c_bits_size, // @[LazyModuleImp.scala:107:25] output [1:0] auto_out_c_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_out_c_bits_address, // @[LazyModuleImp.scala:107:25] output [127:0] auto_out_c_bits_data, // @[LazyModuleImp.scala:107:25] output auto_out_c_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_out_d_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [1:0] auto_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input [3:0] auto_out_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_out_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [127:0] auto_out_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_out_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_out_e_ready, // @[LazyModuleImp.scala:107:25] output auto_out_e_valid, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_e_bits_sink // @[LazyModuleImp.scala:107:25] ); wire auto_in_a_valid_0 = auto_in_a_valid; // @[Buffer.scala:40:9] wire [2:0] auto_in_a_bits_opcode_0 = auto_in_a_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] auto_in_a_bits_param_0 = auto_in_a_bits_param; // @[Buffer.scala:40:9] wire [3:0] auto_in_a_bits_size_0 = auto_in_a_bits_size; // @[Buffer.scala:40:9] wire [1:0] auto_in_a_bits_source_0 = auto_in_a_bits_source; // @[Buffer.scala:40:9] wire [31:0] auto_in_a_bits_address_0 = auto_in_a_bits_address; // @[Buffer.scala:40:9] wire [15:0] auto_in_a_bits_mask_0 = auto_in_a_bits_mask; // @[Buffer.scala:40:9] wire [127:0] auto_in_a_bits_data_0 = auto_in_a_bits_data; // @[Buffer.scala:40:9] wire auto_in_b_ready_0 = auto_in_b_ready; // @[Buffer.scala:40:9] wire auto_in_c_valid_0 = auto_in_c_valid; // @[Buffer.scala:40:9] wire [2:0] auto_in_c_bits_opcode_0 = auto_in_c_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] auto_in_c_bits_param_0 = auto_in_c_bits_param; // @[Buffer.scala:40:9] wire [3:0] auto_in_c_bits_size_0 = auto_in_c_bits_size; // @[Buffer.scala:40:9] wire [1:0] auto_in_c_bits_source_0 = auto_in_c_bits_source; // @[Buffer.scala:40:9] wire [31:0] auto_in_c_bits_address_0 = auto_in_c_bits_address; // @[Buffer.scala:40:9] wire [127:0] auto_in_c_bits_data_0 = auto_in_c_bits_data; // @[Buffer.scala:40:9] wire auto_in_d_ready_0 = auto_in_d_ready; // @[Buffer.scala:40:9] wire auto_in_e_valid_0 = auto_in_e_valid; // @[Buffer.scala:40:9] wire [3:0] auto_in_e_bits_sink_0 = auto_in_e_bits_sink; // @[Buffer.scala:40:9] wire auto_out_a_ready_0 = auto_out_a_ready; // @[Buffer.scala:40:9] wire auto_out_b_valid_0 = auto_out_b_valid; // @[Buffer.scala:40:9] wire [1:0] auto_out_b_bits_param_0 = auto_out_b_bits_param; // @[Buffer.scala:40:9] wire [1:0] auto_out_b_bits_source_0 = auto_out_b_bits_source; // @[Buffer.scala:40:9] wire [31:0] auto_out_b_bits_address_0 = auto_out_b_bits_address; // @[Buffer.scala:40:9] wire auto_out_c_ready_0 = auto_out_c_ready; // @[Buffer.scala:40:9] wire auto_out_d_valid_0 = auto_out_d_valid; // @[Buffer.scala:40:9] wire [2:0] auto_out_d_bits_opcode_0 = auto_out_d_bits_opcode; // @[Buffer.scala:40:9] wire [1:0] auto_out_d_bits_param_0 = auto_out_d_bits_param; // @[Buffer.scala:40:9] wire [3:0] auto_out_d_bits_size_0 = auto_out_d_bits_size; // @[Buffer.scala:40:9] wire [1:0] auto_out_d_bits_source_0 = auto_out_d_bits_source; // @[Buffer.scala:40:9] wire [3:0] auto_out_d_bits_sink_0 = auto_out_d_bits_sink; // @[Buffer.scala:40:9] wire auto_out_d_bits_denied_0 = auto_out_d_bits_denied; // @[Buffer.scala:40:9] wire [127:0] auto_out_d_bits_data_0 = auto_out_d_bits_data; // @[Buffer.scala:40:9] wire auto_out_d_bits_corrupt_0 = auto_out_d_bits_corrupt; // @[Buffer.scala:40:9] wire auto_out_e_ready_0 = auto_out_e_ready; // @[Buffer.scala:40:9] wire [127:0] auto_out_b_bits_data = 128'h0; // @[Decoupled.scala:362:21] wire [127:0] nodeOut_b_bits_data = 128'h0; // @[Decoupled.scala:362:21] wire [15:0] auto_out_b_bits_mask = 16'hFFFF; // @[Decoupled.scala:362:21] wire [15:0] nodeOut_b_bits_mask = 16'hFFFF; // @[Decoupled.scala:362:21] wire [3:0] auto_out_b_bits_size = 4'h6; // @[Decoupled.scala:362:21] wire [3:0] nodeOut_b_bits_size = 4'h6; // @[Decoupled.scala:362:21] wire [2:0] auto_out_b_bits_opcode = 3'h6; // @[Decoupled.scala:362:21] wire [2:0] nodeOut_b_bits_opcode = 3'h6; // @[Decoupled.scala:362:21] wire auto_in_a_bits_corrupt = 1'h0; // @[Decoupled.scala:362:21] wire auto_in_c_bits_corrupt = 1'h0; // @[Decoupled.scala:362:21] wire auto_out_b_bits_corrupt = 1'h0; // @[Decoupled.scala:362:21] wire nodeIn_a_ready; // @[MixedNode.scala:551:17] wire nodeIn_a_bits_corrupt = 1'h0; // @[Decoupled.scala:362:21] wire nodeIn_c_bits_corrupt = 1'h0; // @[Decoupled.scala:362:21] wire nodeOut_b_bits_corrupt = 1'h0; // @[Decoupled.scala:362:21] wire nodeIn_a_valid = auto_in_a_valid_0; // @[Buffer.scala:40:9] wire [2:0] nodeIn_a_bits_opcode = auto_in_a_bits_opcode_0; // @[Buffer.scala:40:9] wire [2:0] nodeIn_a_bits_param = auto_in_a_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] nodeIn_a_bits_size = auto_in_a_bits_size_0; // @[Buffer.scala:40:9] wire [1:0] nodeIn_a_bits_source = auto_in_a_bits_source_0; // @[Buffer.scala:40:9] wire [31:0] nodeIn_a_bits_address = auto_in_a_bits_address_0; // @[Buffer.scala:40:9] wire [15:0] nodeIn_a_bits_mask = auto_in_a_bits_mask_0; // @[Buffer.scala:40:9] wire [127:0] nodeIn_a_bits_data = auto_in_a_bits_data_0; // @[Buffer.scala:40:9] wire nodeIn_b_ready = auto_in_b_ready_0; // @[Buffer.scala:40:9] wire nodeIn_b_valid; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_b_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] nodeIn_b_bits_param; // @[MixedNode.scala:551:17] wire [3:0] nodeIn_b_bits_size; // @[MixedNode.scala:551:17] wire [1:0] nodeIn_b_bits_source; // @[MixedNode.scala:551:17] wire [31:0] nodeIn_b_bits_address; // @[MixedNode.scala:551:17] wire [15:0] nodeIn_b_bits_mask; // @[MixedNode.scala:551:17] wire [127:0] nodeIn_b_bits_data; // @[MixedNode.scala:551:17] wire nodeIn_b_bits_corrupt; // @[MixedNode.scala:551:17] wire nodeIn_c_ready; // @[MixedNode.scala:551:17] wire nodeIn_c_valid = auto_in_c_valid_0; // @[Buffer.scala:40:9] wire [2:0] nodeIn_c_bits_opcode = auto_in_c_bits_opcode_0; // @[Buffer.scala:40:9] wire [2:0] nodeIn_c_bits_param = auto_in_c_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] nodeIn_c_bits_size = auto_in_c_bits_size_0; // @[Buffer.scala:40:9] wire [1:0] nodeIn_c_bits_source = auto_in_c_bits_source_0; // @[Buffer.scala:40:9] wire [31:0] nodeIn_c_bits_address = auto_in_c_bits_address_0; // @[Buffer.scala:40:9] wire [127:0] nodeIn_c_bits_data = auto_in_c_bits_data_0; // @[Buffer.scala:40:9] wire nodeIn_d_ready = auto_in_d_ready_0; // @[Buffer.scala:40:9] wire nodeIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] nodeIn_d_bits_param; // @[MixedNode.scala:551:17] wire [3:0] nodeIn_d_bits_size; // @[MixedNode.scala:551:17] wire [1:0] nodeIn_d_bits_source; // @[MixedNode.scala:551:17] wire [3:0] nodeIn_d_bits_sink; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_denied; // @[MixedNode.scala:551:17] wire [127:0] nodeIn_d_bits_data; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_corrupt; // @[MixedNode.scala:551:17] wire nodeIn_e_ready; // @[MixedNode.scala:551:17] wire nodeIn_e_valid = auto_in_e_valid_0; // @[Buffer.scala:40:9] wire [3:0] nodeIn_e_bits_sink = auto_in_e_bits_sink_0; // @[Buffer.scala:40:9] wire nodeOut_a_ready = auto_out_a_ready_0; // @[Buffer.scala:40:9] wire nodeOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_a_bits_param; // @[MixedNode.scala:542:17] wire [3:0] nodeOut_a_bits_size; // @[MixedNode.scala:542:17] wire [1:0] nodeOut_a_bits_source; // @[MixedNode.scala:542:17] wire [31:0] nodeOut_a_bits_address; // @[MixedNode.scala:542:17] wire [15:0] nodeOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [127:0] nodeOut_a_bits_data; // @[MixedNode.scala:542:17] wire nodeOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire nodeOut_b_ready; // @[MixedNode.scala:542:17] wire nodeOut_b_valid = auto_out_b_valid_0; // @[Buffer.scala:40:9] wire [1:0] nodeOut_b_bits_param = auto_out_b_bits_param_0; // @[Buffer.scala:40:9] wire [1:0] nodeOut_b_bits_source = auto_out_b_bits_source_0; // @[Buffer.scala:40:9] wire [31:0] nodeOut_b_bits_address = auto_out_b_bits_address_0; // @[Buffer.scala:40:9] wire nodeOut_c_ready = auto_out_c_ready_0; // @[Buffer.scala:40:9] wire nodeOut_c_valid; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_c_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_c_bits_param; // @[MixedNode.scala:542:17] wire [3:0] nodeOut_c_bits_size; // @[MixedNode.scala:542:17] wire [1:0] nodeOut_c_bits_source; // @[MixedNode.scala:542:17] wire [31:0] nodeOut_c_bits_address; // @[MixedNode.scala:542:17] wire [127:0] nodeOut_c_bits_data; // @[MixedNode.scala:542:17] wire nodeOut_c_bits_corrupt; // @[MixedNode.scala:542:17] wire nodeOut_d_ready; // @[MixedNode.scala:542:17] wire nodeOut_d_valid = auto_out_d_valid_0; // @[Buffer.scala:40:9] wire [2:0] nodeOut_d_bits_opcode = auto_out_d_bits_opcode_0; // @[Buffer.scala:40:9] wire [1:0] nodeOut_d_bits_param = auto_out_d_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] nodeOut_d_bits_size = auto_out_d_bits_size_0; // @[Buffer.scala:40:9] wire [1:0] nodeOut_d_bits_source = auto_out_d_bits_source_0; // @[Buffer.scala:40:9] wire [3:0] nodeOut_d_bits_sink = auto_out_d_bits_sink_0; // @[Buffer.scala:40:9] wire nodeOut_d_bits_denied = auto_out_d_bits_denied_0; // @[Buffer.scala:40:9] wire [127:0] nodeOut_d_bits_data = auto_out_d_bits_data_0; // @[Buffer.scala:40:9] wire nodeOut_d_bits_corrupt = auto_out_d_bits_corrupt_0; // @[Buffer.scala:40:9] wire nodeOut_e_ready = auto_out_e_ready_0; // @[Buffer.scala:40:9] wire nodeOut_e_valid; // @[MixedNode.scala:542:17] wire [3:0] nodeOut_e_bits_sink; // @[MixedNode.scala:542:17] wire auto_in_a_ready_0; // @[Buffer.scala:40:9] wire [2:0] auto_in_b_bits_opcode_0; // @[Buffer.scala:40:9] wire [1:0] auto_in_b_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] auto_in_b_bits_size_0; // @[Buffer.scala:40:9] wire [1:0] auto_in_b_bits_source_0; // @[Buffer.scala:40:9] wire [31:0] auto_in_b_bits_address_0; // @[Buffer.scala:40:9] wire [15:0] auto_in_b_bits_mask_0; // @[Buffer.scala:40:9] wire [127:0] auto_in_b_bits_data_0; // @[Buffer.scala:40:9] wire auto_in_b_bits_corrupt_0; // @[Buffer.scala:40:9] wire auto_in_b_valid_0; // @[Buffer.scala:40:9] wire auto_in_c_ready_0; // @[Buffer.scala:40:9] wire [2:0] auto_in_d_bits_opcode_0; // @[Buffer.scala:40:9] wire [1:0] auto_in_d_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] auto_in_d_bits_size_0; // @[Buffer.scala:40:9] wire [1:0] auto_in_d_bits_source_0; // @[Buffer.scala:40:9] wire [3:0] auto_in_d_bits_sink_0; // @[Buffer.scala:40:9] wire auto_in_d_bits_denied_0; // @[Buffer.scala:40:9] wire [127:0] auto_in_d_bits_data_0; // @[Buffer.scala:40:9] wire auto_in_d_bits_corrupt_0; // @[Buffer.scala:40:9] wire auto_in_d_valid_0; // @[Buffer.scala:40:9] wire auto_in_e_ready_0; // @[Buffer.scala:40:9] wire [2:0] auto_out_a_bits_opcode_0; // @[Buffer.scala:40:9] wire [2:0] auto_out_a_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] auto_out_a_bits_size_0; // @[Buffer.scala:40:9] wire [1:0] auto_out_a_bits_source_0; // @[Buffer.scala:40:9] wire [31:0] auto_out_a_bits_address_0; // @[Buffer.scala:40:9] wire [15:0] auto_out_a_bits_mask_0; // @[Buffer.scala:40:9] wire [127:0] auto_out_a_bits_data_0; // @[Buffer.scala:40:9] wire auto_out_a_bits_corrupt_0; // @[Buffer.scala:40:9] wire auto_out_a_valid_0; // @[Buffer.scala:40:9] wire auto_out_b_ready_0; // @[Buffer.scala:40:9] wire [2:0] auto_out_c_bits_opcode_0; // @[Buffer.scala:40:9] wire [2:0] auto_out_c_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] auto_out_c_bits_size_0; // @[Buffer.scala:40:9] wire [1:0] auto_out_c_bits_source_0; // @[Buffer.scala:40:9] wire [31:0] auto_out_c_bits_address_0; // @[Buffer.scala:40:9] wire [127:0] auto_out_c_bits_data_0; // @[Buffer.scala:40:9] wire auto_out_c_bits_corrupt_0; // @[Buffer.scala:40:9] wire auto_out_c_valid_0; // @[Buffer.scala:40:9] wire auto_out_d_ready_0; // @[Buffer.scala:40:9] wire [3:0] auto_out_e_bits_sink_0; // @[Buffer.scala:40:9] wire auto_out_e_valid_0; // @[Buffer.scala:40:9] assign auto_in_a_ready_0 = nodeIn_a_ready; // @[Buffer.scala:40:9] assign auto_in_b_valid_0 = nodeIn_b_valid; // @[Buffer.scala:40:9] assign auto_in_b_bits_opcode_0 = nodeIn_b_bits_opcode; // @[Buffer.scala:40:9] assign auto_in_b_bits_param_0 = nodeIn_b_bits_param; // @[Buffer.scala:40:9] assign auto_in_b_bits_size_0 = nodeIn_b_bits_size; // @[Buffer.scala:40:9] assign auto_in_b_bits_source_0 = nodeIn_b_bits_source; // @[Buffer.scala:40:9] assign auto_in_b_bits_address_0 = nodeIn_b_bits_address; // @[Buffer.scala:40:9] assign auto_in_b_bits_mask_0 = nodeIn_b_bits_mask; // @[Buffer.scala:40:9] assign auto_in_b_bits_data_0 = nodeIn_b_bits_data; // @[Buffer.scala:40:9] assign auto_in_b_bits_corrupt_0 = nodeIn_b_bits_corrupt; // @[Buffer.scala:40:9] assign auto_in_c_ready_0 = nodeIn_c_ready; // @[Buffer.scala:40:9] assign auto_in_d_valid_0 = nodeIn_d_valid; // @[Buffer.scala:40:9] assign auto_in_d_bits_opcode_0 = nodeIn_d_bits_opcode; // @[Buffer.scala:40:9] assign auto_in_d_bits_param_0 = nodeIn_d_bits_param; // @[Buffer.scala:40:9] assign auto_in_d_bits_size_0 = nodeIn_d_bits_size; // @[Buffer.scala:40:9] assign auto_in_d_bits_source_0 = nodeIn_d_bits_source; // @[Buffer.scala:40:9] assign auto_in_d_bits_sink_0 = nodeIn_d_bits_sink; // @[Buffer.scala:40:9] assign auto_in_d_bits_denied_0 = nodeIn_d_bits_denied; // @[Buffer.scala:40:9] assign auto_in_d_bits_data_0 = nodeIn_d_bits_data; // @[Buffer.scala:40:9] assign auto_in_d_bits_corrupt_0 = nodeIn_d_bits_corrupt; // @[Buffer.scala:40:9] assign auto_in_e_ready_0 = nodeIn_e_ready; // @[Buffer.scala:40:9] assign auto_out_a_valid_0 = nodeOut_a_valid; // @[Buffer.scala:40:9] assign auto_out_a_bits_opcode_0 = nodeOut_a_bits_opcode; // @[Buffer.scala:40:9] assign auto_out_a_bits_param_0 = nodeOut_a_bits_param; // @[Buffer.scala:40:9] assign auto_out_a_bits_size_0 = nodeOut_a_bits_size; // @[Buffer.scala:40:9] assign auto_out_a_bits_source_0 = nodeOut_a_bits_source; // @[Buffer.scala:40:9] assign auto_out_a_bits_address_0 = nodeOut_a_bits_address; // @[Buffer.scala:40:9] assign auto_out_a_bits_mask_0 = nodeOut_a_bits_mask; // @[Buffer.scala:40:9] assign auto_out_a_bits_data_0 = nodeOut_a_bits_data; // @[Buffer.scala:40:9] assign auto_out_a_bits_corrupt_0 = nodeOut_a_bits_corrupt; // @[Buffer.scala:40:9] assign auto_out_b_ready_0 = nodeOut_b_ready; // @[Buffer.scala:40:9] assign auto_out_c_valid_0 = nodeOut_c_valid; // @[Buffer.scala:40:9] assign auto_out_c_bits_opcode_0 = nodeOut_c_bits_opcode; // @[Buffer.scala:40:9] assign auto_out_c_bits_param_0 = nodeOut_c_bits_param; // @[Buffer.scala:40:9] assign auto_out_c_bits_size_0 = nodeOut_c_bits_size; // @[Buffer.scala:40:9] assign auto_out_c_bits_source_0 = nodeOut_c_bits_source; // @[Buffer.scala:40:9] assign auto_out_c_bits_address_0 = nodeOut_c_bits_address; // @[Buffer.scala:40:9] assign auto_out_c_bits_data_0 = nodeOut_c_bits_data; // @[Buffer.scala:40:9] assign auto_out_c_bits_corrupt_0 = nodeOut_c_bits_corrupt; // @[Buffer.scala:40:9] assign auto_out_d_ready_0 = nodeOut_d_ready; // @[Buffer.scala:40:9] assign auto_out_e_valid_0 = nodeOut_e_valid; // @[Buffer.scala:40:9] assign auto_out_e_bits_sink_0 = nodeOut_e_bits_sink; // @[Buffer.scala:40:9] TLMonitor_45 monitor ( // @[Nodes.scala:27:25] .clock (clock), .reset (reset), .io_in_a_ready (nodeIn_a_ready), // @[MixedNode.scala:551:17] .io_in_a_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17] .io_in_a_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17] .io_in_a_bits_param (nodeIn_a_bits_param), // @[MixedNode.scala:551:17] .io_in_a_bits_size (nodeIn_a_bits_size), // @[MixedNode.scala:551:17] .io_in_a_bits_source (nodeIn_a_bits_source), // @[MixedNode.scala:551:17] .io_in_a_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17] .io_in_a_bits_mask (nodeIn_a_bits_mask), // @[MixedNode.scala:551:17] .io_in_a_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17] .io_in_b_ready (nodeIn_b_ready), // @[MixedNode.scala:551:17] .io_in_b_valid (nodeIn_b_valid), // @[MixedNode.scala:551:17] .io_in_b_bits_opcode (nodeIn_b_bits_opcode), // @[MixedNode.scala:551:17] .io_in_b_bits_param (nodeIn_b_bits_param), // @[MixedNode.scala:551:17] .io_in_b_bits_size (nodeIn_b_bits_size), // @[MixedNode.scala:551:17] .io_in_b_bits_source (nodeIn_b_bits_source), // @[MixedNode.scala:551:17] .io_in_b_bits_address (nodeIn_b_bits_address), // @[MixedNode.scala:551:17] .io_in_b_bits_mask (nodeIn_b_bits_mask), // @[MixedNode.scala:551:17] .io_in_b_bits_data (nodeIn_b_bits_data), // @[MixedNode.scala:551:17] .io_in_b_bits_corrupt (nodeIn_b_bits_corrupt), // @[MixedNode.scala:551:17] .io_in_c_ready (nodeIn_c_ready), // @[MixedNode.scala:551:17] .io_in_c_valid (nodeIn_c_valid), // @[MixedNode.scala:551:17] .io_in_c_bits_opcode (nodeIn_c_bits_opcode), // @[MixedNode.scala:551:17] .io_in_c_bits_param (nodeIn_c_bits_param), // @[MixedNode.scala:551:17] .io_in_c_bits_size (nodeIn_c_bits_size), // @[MixedNode.scala:551:17] .io_in_c_bits_source (nodeIn_c_bits_source), // @[MixedNode.scala:551:17] .io_in_c_bits_address (nodeIn_c_bits_address), // @[MixedNode.scala:551:17] .io_in_c_bits_data (nodeIn_c_bits_data), // @[MixedNode.scala:551:17] .io_in_d_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17] .io_in_d_valid (nodeIn_d_valid), // @[MixedNode.scala:551:17] .io_in_d_bits_opcode (nodeIn_d_bits_opcode), // @[MixedNode.scala:551:17] .io_in_d_bits_param (nodeIn_d_bits_param), // @[MixedNode.scala:551:17] .io_in_d_bits_size (nodeIn_d_bits_size), // @[MixedNode.scala:551:17] .io_in_d_bits_source (nodeIn_d_bits_source), // @[MixedNode.scala:551:17] .io_in_d_bits_sink (nodeIn_d_bits_sink), // @[MixedNode.scala:551:17] .io_in_d_bits_denied (nodeIn_d_bits_denied), // @[MixedNode.scala:551:17] .io_in_d_bits_data (nodeIn_d_bits_data), // @[MixedNode.scala:551:17] .io_in_d_bits_corrupt (nodeIn_d_bits_corrupt), // @[MixedNode.scala:551:17] .io_in_e_ready (nodeIn_e_ready), // @[MixedNode.scala:551:17] .io_in_e_valid (nodeIn_e_valid), // @[MixedNode.scala:551:17] .io_in_e_bits_sink (nodeIn_e_bits_sink) // @[MixedNode.scala:551:17] ); // @[Nodes.scala:27:25] Queue2_TLBundleA_a32d128s2k4z4c nodeOut_a_q ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (nodeIn_a_ready), .io_enq_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17] .io_enq_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17] .io_enq_bits_param (nodeIn_a_bits_param), // @[MixedNode.scala:551:17] .io_enq_bits_size (nodeIn_a_bits_size), // @[MixedNode.scala:551:17] .io_enq_bits_source (nodeIn_a_bits_source), // @[MixedNode.scala:551:17] .io_enq_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17] .io_enq_bits_mask (nodeIn_a_bits_mask), // @[MixedNode.scala:551:17] .io_enq_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17] .io_deq_ready (nodeOut_a_ready), // @[MixedNode.scala:542:17] .io_deq_valid (nodeOut_a_valid), .io_deq_bits_opcode (nodeOut_a_bits_opcode), .io_deq_bits_param (nodeOut_a_bits_param), .io_deq_bits_size (nodeOut_a_bits_size), .io_deq_bits_source (nodeOut_a_bits_source), .io_deq_bits_address (nodeOut_a_bits_address), .io_deq_bits_mask (nodeOut_a_bits_mask), .io_deq_bits_data (nodeOut_a_bits_data), .io_deq_bits_corrupt (nodeOut_a_bits_corrupt) ); // @[Decoupled.scala:362:21] Queue2_TLBundleD_a32d128s2k4z4c nodeIn_d_q ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (nodeOut_d_ready), .io_enq_valid (nodeOut_d_valid), // @[MixedNode.scala:542:17] .io_enq_bits_opcode (nodeOut_d_bits_opcode), // @[MixedNode.scala:542:17] .io_enq_bits_param (nodeOut_d_bits_param), // @[MixedNode.scala:542:17] .io_enq_bits_size (nodeOut_d_bits_size), // @[MixedNode.scala:542:17] .io_enq_bits_source (nodeOut_d_bits_source), // @[MixedNode.scala:542:17] .io_enq_bits_sink (nodeOut_d_bits_sink), // @[MixedNode.scala:542:17] .io_enq_bits_denied (nodeOut_d_bits_denied), // @[MixedNode.scala:542:17] .io_enq_bits_data (nodeOut_d_bits_data), // @[MixedNode.scala:542:17] .io_enq_bits_corrupt (nodeOut_d_bits_corrupt), // @[MixedNode.scala:542:17] .io_deq_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17] .io_deq_valid (nodeIn_d_valid), .io_deq_bits_opcode (nodeIn_d_bits_opcode), .io_deq_bits_param (nodeIn_d_bits_param), .io_deq_bits_size (nodeIn_d_bits_size), .io_deq_bits_source (nodeIn_d_bits_source), .io_deq_bits_sink (nodeIn_d_bits_sink), .io_deq_bits_denied (nodeIn_d_bits_denied), .io_deq_bits_data (nodeIn_d_bits_data), .io_deq_bits_corrupt (nodeIn_d_bits_corrupt) ); // @[Decoupled.scala:362:21] Queue2_TLBundleB_a32d128s2k4z4c nodeIn_b_q ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (nodeOut_b_ready), .io_enq_valid (nodeOut_b_valid), // @[MixedNode.scala:542:17] .io_enq_bits_param (nodeOut_b_bits_param), // @[MixedNode.scala:542:17] .io_enq_bits_source (nodeOut_b_bits_source), // @[MixedNode.scala:542:17] .io_enq_bits_address (nodeOut_b_bits_address), // @[MixedNode.scala:542:17] .io_deq_ready (nodeIn_b_ready), // @[MixedNode.scala:551:17] .io_deq_valid (nodeIn_b_valid), .io_deq_bits_opcode (nodeIn_b_bits_opcode), .io_deq_bits_param (nodeIn_b_bits_param), .io_deq_bits_size (nodeIn_b_bits_size), .io_deq_bits_source (nodeIn_b_bits_source), .io_deq_bits_address (nodeIn_b_bits_address), .io_deq_bits_mask (nodeIn_b_bits_mask), .io_deq_bits_data (nodeIn_b_bits_data), .io_deq_bits_corrupt (nodeIn_b_bits_corrupt) ); // @[Decoupled.scala:362:21] Queue2_TLBundleC_a32d128s2k4z4c nodeOut_c_q ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (nodeIn_c_ready), .io_enq_valid (nodeIn_c_valid), // @[MixedNode.scala:551:17] .io_enq_bits_opcode (nodeIn_c_bits_opcode), // @[MixedNode.scala:551:17] .io_enq_bits_param (nodeIn_c_bits_param), // @[MixedNode.scala:551:17] .io_enq_bits_size (nodeIn_c_bits_size), // @[MixedNode.scala:551:17] .io_enq_bits_source (nodeIn_c_bits_source), // @[MixedNode.scala:551:17] .io_enq_bits_address (nodeIn_c_bits_address), // @[MixedNode.scala:551:17] .io_enq_bits_data (nodeIn_c_bits_data), // @[MixedNode.scala:551:17] .io_deq_ready (nodeOut_c_ready), // @[MixedNode.scala:542:17] .io_deq_valid (nodeOut_c_valid), .io_deq_bits_opcode (nodeOut_c_bits_opcode), .io_deq_bits_param (nodeOut_c_bits_param), .io_deq_bits_size (nodeOut_c_bits_size), .io_deq_bits_source (nodeOut_c_bits_source), .io_deq_bits_address (nodeOut_c_bits_address), .io_deq_bits_data (nodeOut_c_bits_data), .io_deq_bits_corrupt (nodeOut_c_bits_corrupt) ); // @[Decoupled.scala:362:21] Queue2_TLBundleE_a32d128s2k4z4c nodeOut_e_q ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (nodeIn_e_ready), .io_enq_valid (nodeIn_e_valid), // @[MixedNode.scala:551:17] .io_enq_bits_sink (nodeIn_e_bits_sink), // @[MixedNode.scala:551:17] .io_deq_ready (nodeOut_e_ready), // @[MixedNode.scala:542:17] .io_deq_valid (nodeOut_e_valid), .io_deq_bits_sink (nodeOut_e_bits_sink) ); // @[Decoupled.scala:362:21] assign auto_in_a_ready = auto_in_a_ready_0; // @[Buffer.scala:40:9] assign auto_in_b_valid = auto_in_b_valid_0; // @[Buffer.scala:40:9] assign auto_in_b_bits_opcode = auto_in_b_bits_opcode_0; // @[Buffer.scala:40:9] assign auto_in_b_bits_param = auto_in_b_bits_param_0; // @[Buffer.scala:40:9] assign auto_in_b_bits_size = auto_in_b_bits_size_0; // @[Buffer.scala:40:9] assign auto_in_b_bits_source = auto_in_b_bits_source_0; // @[Buffer.scala:40:9] assign auto_in_b_bits_address = auto_in_b_bits_address_0; // @[Buffer.scala:40:9] assign auto_in_b_bits_mask = auto_in_b_bits_mask_0; // @[Buffer.scala:40:9] assign auto_in_b_bits_data = auto_in_b_bits_data_0; // @[Buffer.scala:40:9] assign auto_in_b_bits_corrupt = auto_in_b_bits_corrupt_0; // @[Buffer.scala:40:9] assign auto_in_c_ready = auto_in_c_ready_0; // @[Buffer.scala:40:9] assign auto_in_d_valid = auto_in_d_valid_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_opcode = auto_in_d_bits_opcode_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_param = auto_in_d_bits_param_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_size = auto_in_d_bits_size_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_source = auto_in_d_bits_source_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_sink = auto_in_d_bits_sink_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_denied = auto_in_d_bits_denied_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_data = auto_in_d_bits_data_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_corrupt = auto_in_d_bits_corrupt_0; // @[Buffer.scala:40:9] assign auto_in_e_ready = auto_in_e_ready_0; // @[Buffer.scala:40:9] assign auto_out_a_valid = auto_out_a_valid_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_opcode = auto_out_a_bits_opcode_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_param = auto_out_a_bits_param_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_size = auto_out_a_bits_size_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_source = auto_out_a_bits_source_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_address = auto_out_a_bits_address_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_mask = auto_out_a_bits_mask_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_data = auto_out_a_bits_data_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_corrupt = auto_out_a_bits_corrupt_0; // @[Buffer.scala:40:9] assign auto_out_b_ready = auto_out_b_ready_0; // @[Buffer.scala:40:9] assign auto_out_c_valid = auto_out_c_valid_0; // @[Buffer.scala:40:9] assign auto_out_c_bits_opcode = auto_out_c_bits_opcode_0; // @[Buffer.scala:40:9] assign auto_out_c_bits_param = auto_out_c_bits_param_0; // @[Buffer.scala:40:9] assign auto_out_c_bits_size = auto_out_c_bits_size_0; // @[Buffer.scala:40:9] assign auto_out_c_bits_source = auto_out_c_bits_source_0; // @[Buffer.scala:40:9] assign auto_out_c_bits_address = auto_out_c_bits_address_0; // @[Buffer.scala:40:9] assign auto_out_c_bits_data = auto_out_c_bits_data_0; // @[Buffer.scala:40:9] assign auto_out_c_bits_corrupt = auto_out_c_bits_corrupt_0; // @[Buffer.scala:40:9] assign auto_out_d_ready = auto_out_d_ready_0; // @[Buffer.scala:40:9] assign auto_out_e_valid = auto_out_e_valid_0; // @[Buffer.scala:40:9] assign auto_out_e_bits_sink = auto_out_e_bits_sink_0; // @[Buffer.scala:40:9] endmodule

Generate the Verilog code corresponding to the following Chisel files. File Decode.scala: // See LICENSE.Berkeley for license details. package freechips.rocketchip.rocket import chisel3._ import chisel3.util.BitPat import chisel3.util.experimental.decode._ object DecodeLogic { // TODO This should be a method on BitPat private def hasDontCare(bp: BitPat): Boolean = bp.mask.bitCount != bp.width // Pads BitPats that are safe to pad (no don't cares), errors otherwise private def padBP(bp: BitPat, width: Int): BitPat = { if (bp.width == width) bp else { require(!hasDontCare(bp), s"Cannot pad '$bp' to '$width' bits because it has don't cares") val diff = width - bp.width require(diff > 0, s"Cannot pad '$bp' to '$width' because it is already '${bp.width}' bits wide!") BitPat(0.U(diff.W)) ## bp } } def apply(addr: UInt, default: BitPat, mapping: Iterable[(BitPat, BitPat)]): UInt = chisel3.util.experimental.decode.decoder(QMCMinimizer, addr, TruthTable(mapping, default)) def apply(addr: UInt, default: Seq[BitPat], mappingIn: Iterable[(BitPat, Seq[BitPat])]): Seq[UInt] = { val nElts = default.size require(mappingIn.forall(_._2.size == nElts), s"All Seq[BitPat] must be of the same length, got $nElts vs. ${mappingIn.find(_._2.size != nElts).get}" ) val elementsGrouped = mappingIn.map(_._2).transpose val elementWidths = elementsGrouped.zip(default).map { case (elts, default) => (default :: elts.toList).map(_.getWidth).max } val resultWidth = elementWidths.sum val elementIndices = elementWidths.scan(resultWidth - 1) { case (l, r) => l - r } // All BitPats that correspond to a given element in the result must have the same width in the // chisel3 decoder. We will zero pad any BitPats that are too small so long as they dont have // any don't cares. If there are don't cares, it is an error and the user needs to pad the // BitPat themselves val defaultsPadded = default.zip(elementWidths).map { case (bp, w) => padBP(bp, w) } val mappingInPadded = mappingIn.map { case (in, elts) => in -> elts.zip(elementWidths).map { case (bp, w) => padBP(bp, w) } } val decoded = apply(addr, defaultsPadded.reduce(_ ## _), mappingInPadded.map { case (in, out) => (in, out.reduce(_ ## _)) }) elementIndices.zip(elementIndices.tail).map { case (msb, lsb) => decoded(msb, lsb + 1) }.toList } def apply(addr: UInt, default: Seq[BitPat], mappingIn: List[(UInt, Seq[BitPat])]): Seq[UInt] = apply(addr, default, mappingIn.map(m => (BitPat(m._1), m._2)).asInstanceOf[Iterable[(BitPat, Seq[BitPat])]]) def apply(addr: UInt, trues: Iterable[UInt], falses: Iterable[UInt]): Bool = apply(addr, BitPat.dontCare(1), trues.map(BitPat(_) -> BitPat("b1")) ++ falses.map(BitPat(_) -> BitPat("b0"))).asBool } File Counters.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ // Produces 0-width value when counting to 1 class ZCounter(val n: Int) { val value = RegInit(0.U(log2Ceil(n).W)) def inc(): Bool = { if (n == 1) true.B else { val wrap = value === (n-1).U value := Mux(!isPow2(n).B && wrap, 0.U, value + 1.U) wrap } } } object ZCounter { def apply(n: Int) = new ZCounter(n) def apply(cond: Bool, n: Int): (UInt, Bool) = { val c = new ZCounter(n) var wrap: Bool = null when (cond) { wrap = c.inc() } (c.value, cond && wrap) } } object TwoWayCounter { def apply(up: Bool, down: Bool, max: Int): UInt = { val cnt = RegInit(0.U(log2Up(max + 1).W)) when (up && !down) { cnt := cnt + 1.U } when (down && !up) { cnt := cnt - 1.U } cnt } } // a counter that clock gates most of its MSBs using the LSB carry-out case class WideCounter(width: Int, inc: UInt = 1.U, reset: Boolean = true, inhibit: Bool = false.B) { private val isWide = width > (2 * inc.getWidth) private val smallWidth = if (isWide) inc.getWidth max log2Up(width) else width private val small = if (reset) RegInit(0.U(smallWidth.W)) else Reg(UInt(smallWidth.W)) private val nextSmall = small +& inc when (!inhibit) { small := nextSmall } private val large = if (isWide) { val r = if (reset) RegInit(0.U((width - smallWidth).W)) else Reg(UInt((width - smallWidth).W)) when (nextSmall(smallWidth) && !inhibit) { r := r + 1.U } r } else null val value = if (isWide) Cat(large, small) else small lazy val carryOut = { val lo = (small ^ nextSmall) >> 1 if (!isWide) lo else { val hi = Mux(nextSmall(smallWidth), large ^ (large +& 1.U), 0.U) >> 1 Cat(hi, lo) } } def := (x: UInt) = { small := x if (isWide) large := x >> smallWidth } } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /** Like Vec.apply(idx), but tolerates indices of mismatched width */ def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /** Any Data subtype that has a Bool member named valid. */ type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /** converts from camel case to to underscores, also removing all spaces */ def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /** converts spaces or underscores to hyphens, also lowering case */ def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y | (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y || y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /** Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation */ def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File PMP.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.rocket import chisel3._ import chisel3.util.{Cat, log2Ceil} import org.chipsalliance.cde.config._ import freechips.rocketchip.tile._ import freechips.rocketchip.util._ class PMPConfig extends Bundle { val l = Bool() val res = UInt(2.W) val a = UInt(2.W) val x = Bool() val w = Bool() val r = Bool() } object PMP { def lgAlign = 2 def apply(reg: PMPReg): PMP = { val pmp = Wire(new PMP()(reg.p)) pmp.cfg := reg.cfg pmp.addr := reg.addr pmp.mask := pmp.computeMask pmp } } class PMPReg(implicit p: Parameters) extends CoreBundle()(p) { val cfg = new PMPConfig val addr = UInt((paddrBits - PMP.lgAlign).W) def reset(): Unit = { cfg.a := 0.U cfg.l := 0.U } def readAddr = if (pmpGranularity.log2 == PMP.lgAlign) addr else { val mask = ((BigInt(1) << (pmpGranularity.log2 - PMP.lgAlign)) - 1).U Mux(napot, addr | (mask >> 1), ~(~addr | mask)) } def napot = cfg.a(1) def torNotNAPOT = cfg.a(0) def tor = !napot && torNotNAPOT def cfgLocked = cfg.l def addrLocked(next: PMPReg) = cfgLocked || next.cfgLocked && next.tor } class PMP(implicit p: Parameters) extends PMPReg { val mask = UInt(paddrBits.W) import PMP._ def computeMask = { val base = Cat(addr, cfg.a(0)) | ((pmpGranularity - 1).U >> lgAlign) Cat(base & ~(base + 1.U), ((1 << lgAlign) - 1).U) } private def comparand = ~(~(addr << lgAlign) | (pmpGranularity - 1).U) private def pow2Match(x: UInt, lgSize: UInt, lgMaxSize: Int) = { def eval(a: UInt, b: UInt, m: UInt) = ((a ^ b) & ~m) === 0.U if (lgMaxSize <= pmpGranularity.log2) { eval(x, comparand, mask) } else { // break up the circuit; the MSB part will be CSE'd val lsbMask = mask | UIntToOH1(lgSize, lgMaxSize) val msbMatch = eval(x >> lgMaxSize, comparand >> lgMaxSize, mask >> lgMaxSize) val lsbMatch = eval(x(lgMaxSize-1, 0), comparand(lgMaxSize-1, 0), lsbMask(lgMaxSize-1, 0)) msbMatch && lsbMatch } } private def boundMatch(x: UInt, lsbMask: UInt, lgMaxSize: Int) = { if (lgMaxSize <= pmpGranularity.log2) { x < comparand } else { // break up the circuit; the MSB part will be CSE'd val msbsLess = (x >> lgMaxSize) < (comparand >> lgMaxSize) val msbsEqual = ((x >> lgMaxSize) ^ (comparand >> lgMaxSize)) === 0.U val lsbsLess = (x(lgMaxSize-1, 0) | lsbMask) < comparand(lgMaxSize-1, 0) msbsLess || (msbsEqual && lsbsLess) } } private def lowerBoundMatch(x: UInt, lgSize: UInt, lgMaxSize: Int) = !boundMatch(x, UIntToOH1(lgSize, lgMaxSize), lgMaxSize) private def upperBoundMatch(x: UInt, lgMaxSize: Int) = boundMatch(x, 0.U, lgMaxSize) private def rangeMatch(x: UInt, lgSize: UInt, lgMaxSize: Int, prev: PMP) = prev.lowerBoundMatch(x, lgSize, lgMaxSize) && upperBoundMatch(x, lgMaxSize) private def pow2Homogeneous(x: UInt, pgLevel: UInt) = { val maskHomogeneous = pgLevelMap { idxBits => if (idxBits > paddrBits) false.B else mask(idxBits - 1) } (pgLevel) maskHomogeneous || (pgLevelMap { idxBits => ((x ^ comparand) >> idxBits) =/= 0.U } (pgLevel)) } private def pgLevelMap[T](f: Int => T) = (0 until pgLevels).map { i => f(pgIdxBits + (pgLevels - 1 - i) * pgLevelBits) } private def rangeHomogeneous(x: UInt, pgLevel: UInt, prev: PMP) = { val beginsAfterLower = !(x < prev.comparand) val beginsAfterUpper = !(x < comparand) val pgMask = pgLevelMap { idxBits => (((BigInt(1) << paddrBits) - (BigInt(1) << idxBits)) max 0).U } (pgLevel) val endsBeforeLower = (x & pgMask) < (prev.comparand & pgMask) val endsBeforeUpper = (x & pgMask) < (comparand & pgMask) endsBeforeLower || beginsAfterUpper || (beginsAfterLower && endsBeforeUpper) } // returns whether this PMP completely contains, or contains none of, a page def homogeneous(x: UInt, pgLevel: UInt, prev: PMP): Bool = Mux(napot, pow2Homogeneous(x, pgLevel), !torNotNAPOT || rangeHomogeneous(x, pgLevel, prev)) // returns whether this matching PMP fully contains the access def aligned(x: UInt, lgSize: UInt, lgMaxSize: Int, prev: PMP): Bool = if (lgMaxSize <= pmpGranularity.log2) true.B else { val lsbMask = UIntToOH1(lgSize, lgMaxSize) val straddlesLowerBound = ((x >> lgMaxSize) ^ (prev.comparand >> lgMaxSize)) === 0.U && (prev.comparand(lgMaxSize-1, 0) & ~x(lgMaxSize-1, 0)) =/= 0.U val straddlesUpperBound = ((x >> lgMaxSize) ^ (comparand >> lgMaxSize)) === 0.U && (comparand(lgMaxSize-1, 0) & (x(lgMaxSize-1, 0) | lsbMask)) =/= 0.U val rangeAligned = !(straddlesLowerBound || straddlesUpperBound) val pow2Aligned = (lsbMask & ~mask(lgMaxSize-1, 0)) === 0.U Mux(napot, pow2Aligned, rangeAligned) } // returns whether this PMP matches at least one byte of the access def hit(x: UInt, lgSize: UInt, lgMaxSize: Int, prev: PMP): Bool = Mux(napot, pow2Match(x, lgSize, lgMaxSize), torNotNAPOT && rangeMatch(x, lgSize, lgMaxSize, prev)) } class PMPHomogeneityChecker(pmps: Seq[PMP])(implicit p: Parameters) { def apply(addr: UInt, pgLevel: UInt): Bool = { pmps.foldLeft((true.B, 0.U.asTypeOf(new PMP))) { case ((h, prev), pmp) => (h && pmp.homogeneous(addr, pgLevel, prev), pmp) }._1 } } class PMPChecker(lgMaxSize: Int)(implicit val p: Parameters) extends Module with HasCoreParameters { override def desiredName = s"PMPChecker_s${lgMaxSize}" val io = IO(new Bundle { val prv = Input(UInt(PRV.SZ.W)) val pmp = Input(Vec(nPMPs, new PMP)) val addr = Input(UInt(paddrBits.W)) val size = Input(UInt(log2Ceil(lgMaxSize + 1).W)) val r = Output(Bool()) val w = Output(Bool()) val x = Output(Bool()) }) val default = if (io.pmp.isEmpty) true.B else io.prv > PRV.S.U val pmp0 = WireInit(0.U.asTypeOf(new PMP)) pmp0.cfg.r := default pmp0.cfg.w := default pmp0.cfg.x := default val res = (io.pmp zip (pmp0 +: io.pmp)).reverse.foldLeft(pmp0) { case (prev, (pmp, prevPMP)) => val hit = pmp.hit(io.addr, io.size, lgMaxSize, prevPMP) val ignore = default && !pmp.cfg.l val aligned = pmp.aligned(io.addr, io.size, lgMaxSize, prevPMP) for ((name, idx) <- Seq("no", "TOR", if (pmpGranularity <= 4) "NA4" else "", "NAPOT").zipWithIndex; if name.nonEmpty) property.cover(pmp.cfg.a === idx.U, s"The cfg access is set to ${name} access ", "Cover PMP access mode setting") property.cover(pmp.cfg.l === 0x1.U, s"The cfg lock is set to high ", "Cover PMP lock mode setting") // Not including Write and no Read permission as the combination is reserved for ((name, idx) <- Seq("no", "RO", "", "RW", "X", "RX", "", "RWX").zipWithIndex; if name.nonEmpty) property.cover((Cat(pmp.cfg.x, pmp.cfg.w, pmp.cfg.r) === idx.U), s"The permission is set to ${name} access ", "Cover PMP access permission setting") for ((name, idx) <- Seq("", "TOR", if (pmpGranularity <= 4) "NA4" else "", "NAPOT").zipWithIndex; if name.nonEmpty) { property.cover(!ignore && hit && aligned && pmp.cfg.a === idx.U, s"The access matches ${name} mode ", "Cover PMP access") property.cover(pmp.cfg.l && hit && aligned && pmp.cfg.a === idx.U, s"The access matches ${name} mode with lock bit high", "Cover PMP access with lock bit") } val cur = WireInit(pmp) cur.cfg.r := aligned && (pmp.cfg.r || ignore) cur.cfg.w := aligned && (pmp.cfg.w || ignore) cur.cfg.x := aligned && (pmp.cfg.x || ignore) Mux(hit, cur, prev) } io.r := res.cfg.r io.w := res.cfg.w io.x := res.cfg.x } File Events.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.rocket import chisel3._ import chisel3.util.log2Ceil import freechips.rocketchip.util._ import freechips.rocketchip.util.property class EventSet(val gate: (UInt, UInt) => Bool, val events: Seq[(String, () => Bool)]) { def size = events.size val hits = WireDefault(VecInit(Seq.fill(size)(false.B))) def check(mask: UInt) = { hits := events.map(_._2()) gate(mask, hits.asUInt) } def dump(): Unit = { for (((name, _), i) <- events.zipWithIndex) when (check(1.U << i)) { printf(s"Event $name\n") } } def withCovers: Unit = { events.zipWithIndex.foreach { case ((name, func), i) => property.cover(gate((1.U << i), (func() << i)), name) } } } class EventSets(val eventSets: Seq[EventSet]) { def maskEventSelector(eventSel: UInt): UInt = { // allow full associativity between counters and event sets (for now?) val setMask = (BigInt(1) << eventSetIdBits) - 1 val maskMask = ((BigInt(1) << eventSets.map(_.size).max) - 1) << maxEventSetIdBits eventSel & (setMask | maskMask).U } private def decode(counter: UInt): (UInt, UInt) = { require(eventSets.size <= (1 << maxEventSetIdBits)) require(eventSetIdBits > 0) (counter(eventSetIdBits-1, 0), counter >> maxEventSetIdBits) } def evaluate(eventSel: UInt): Bool = { val (set, mask) = decode(eventSel) val sets = for (e <- eventSets) yield { require(e.hits.getWidth <= mask.getWidth, s"too many events ${e.hits.getWidth} wider than mask ${mask.getWidth}") e check mask } sets(set) } def cover() = eventSets.foreach { _.withCovers } private def eventSetIdBits = log2Ceil(eventSets.size) private def maxEventSetIdBits = 8 require(eventSetIdBits <= maxEventSetIdBits) } class SuperscalarEventSets(val eventSets: Seq[(Seq[EventSet], (UInt, UInt) => UInt)]) { def evaluate(eventSel: UInt): UInt = { val (set, mask) = decode(eventSel) val sets = for ((sets, reducer) <- eventSets) yield { sets.map { set => require(set.hits.getWidth <= mask.getWidth, s"too many events ${set.hits.getWidth} wider than mask ${mask.getWidth}") set.check(mask) }.reduce(reducer) } val zeroPadded = sets.padTo(1 << eventSetIdBits, 0.U) zeroPadded(set) } def toScalarEventSets: EventSets = new EventSets(eventSets.map(_._1.head)) def cover(): Unit = { eventSets.foreach(_._1.foreach(_.withCovers)) } private def decode(counter: UInt): (UInt, UInt) = { require(eventSets.size <= (1 << maxEventSetIdBits)) require(eventSetIdBits > 0) (counter(eventSetIdBits-1, 0), counter >> maxEventSetIdBits) } private def eventSetIdBits = log2Ceil(eventSets.size) private def maxEventSetIdBits = 8 require(eventSets.forall(s => s._1.forall(_.size == s._1.head.size))) require(eventSetIdBits <= maxEventSetIdBits) } File CSR.scala: // See LICENSE.SiFive for license details. // See LICENSE.Berkeley for license details. package freechips.rocketchip.rocket import chisel3._ import chisel3.util.{BitPat, Cat, Fill, Mux1H, PopCount, PriorityMux, RegEnable, UIntToOH, Valid, log2Ceil, log2Up} import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.devices.debug.DebugModuleKey import freechips.rocketchip.tile._ import freechips.rocketchip.util._ import freechips.rocketchip.util.property import scala.collection.mutable.LinkedHashMap import Instructions._ import CustomInstructions._ class MStatus extends Bundle { // not truly part of mstatus, but convenient val debug = Bool() val cease = Bool() val wfi = Bool() val isa = UInt(32.W) val dprv = UInt(PRV.SZ.W) // effective prv for data accesses val dv = Bool() // effective v for data accesses val prv = UInt(PRV.SZ.W) val v = Bool() val sd = Bool() val zero2 = UInt(23.W) val mpv = Bool() val gva = Bool() val mbe = Bool() val sbe = Bool() val sxl = UInt(2.W) val uxl = UInt(2.W) val sd_rv32 = Bool() val zero1 = UInt(8.W) val tsr = Bool() val tw = Bool() val tvm = Bool() val mxr = Bool() val sum = Bool() val mprv = Bool() val xs = UInt(2.W) val fs = UInt(2.W) val mpp = UInt(2.W) val vs = UInt(2.W) val spp = UInt(1.W) val mpie = Bool() val ube = Bool() val spie = Bool() val upie = Bool() val mie = Bool() val hie = Bool() val sie = Bool() val uie = Bool() } class MNStatus extends Bundle { val mpp = UInt(2.W) val zero3 = UInt(3.W) val mpv = Bool() val zero2 = UInt(3.W) val mie = Bool() val zero1 = UInt(3.W) } class HStatus extends Bundle { val zero6 = UInt(30.W) val vsxl = UInt(2.W) val zero5 = UInt(9.W) val vtsr = Bool() val vtw = Bool() val vtvm = Bool() val zero3 = UInt(2.W) val vgein = UInt(6.W) val zero2 = UInt(2.W) val hu = Bool() val spvp = Bool() val spv = Bool() val gva = Bool() val vsbe = Bool() val zero1 = UInt(5.W) } class DCSR extends Bundle { val xdebugver = UInt(2.W) val zero4 = UInt(2.W) val zero3 = UInt(12.W) val ebreakm = Bool() val ebreakh = Bool() val ebreaks = Bool() val ebreaku = Bool() val zero2 = Bool() val stopcycle = Bool() val stoptime = Bool() val cause = UInt(3.W) val v = Bool() val zero1 = UInt(2.W) val step = Bool() val prv = UInt(PRV.SZ.W) } class MIP(implicit p: Parameters) extends CoreBundle()(p) with HasCoreParameters { val lip = Vec(coreParams.nLocalInterrupts, Bool()) val zero1 = Bool() val debug = Bool() // keep in sync with CSR.debugIntCause val rocc = Bool() val sgeip = Bool() val meip = Bool() val vseip = Bool() val seip = Bool() val ueip = Bool() val mtip = Bool() val vstip = Bool() val stip = Bool() val utip = Bool() val msip = Bool() val vssip = Bool() val ssip = Bool() val usip = Bool() } class Envcfg extends Bundle { val stce = Bool() // only for menvcfg/henvcfg val pbmte = Bool() // only for menvcfg/henvcfg val zero54 = UInt(54.W) val cbze = Bool() val cbcfe = Bool() val cbie = UInt(2.W) val zero3 = UInt(3.W) val fiom = Bool() def write(wdata: UInt) { val new_envcfg = wdata.asTypeOf(new Envcfg) fiom := new_envcfg.fiom // only FIOM is writable currently } } class PTBR(implicit p: Parameters) extends CoreBundle()(p) { def additionalPgLevels = mode.extract(log2Ceil(pgLevels-minPgLevels+1)-1, 0) def pgLevelsToMode(i: Int) = (xLen, i) match { case (32, 2) => 1 case (64, x) if x >= 3 && x <= 6 => x + 5 } val (modeBits, maxASIdBits) = xLen match { case 32 => (1, 9) case 64 => (4, 16) } require(modeBits + maxASIdBits + maxPAddrBits - pgIdxBits == xLen) val mode = UInt(modeBits.W) val asid = UInt(maxASIdBits.W) val ppn = UInt((maxPAddrBits - pgIdxBits).W) } object PRV { val SZ = 2 val U = 0 val S = 1 val H = 2 val M = 3 } object CSR { // commands val SZ = 3 def X = BitPat.dontCare(SZ) def N = 0.U(SZ.W) def R = 2.U(SZ.W) def I = 4.U(SZ.W) def W = 5.U(SZ.W) def S = 6.U(SZ.W) def C = 7.U(SZ.W) // mask a CSR cmd with a valid bit def maskCmd(valid: Bool, cmd: UInt): UInt = { // all commands less than CSR.I are treated by CSRFile as NOPs cmd & ~Mux(valid, 0.U, CSR.I) } val ADDRSZ = 12 def modeLSB: Int = 8 def mode(addr: Int): Int = (addr >> modeLSB) % (1 << PRV.SZ) def mode(addr: UInt): UInt = addr(modeLSB + PRV.SZ - 1, modeLSB) def busErrorIntCause = 128 def debugIntCause = 14 // keep in sync with MIP.debug def debugTriggerCause = { val res = debugIntCause require(!(Causes.all contains res)) res } def rnmiIntCause = 13 // NMI: Higher numbers = higher priority, must not reuse debugIntCause def rnmiBEUCause = 12 val firstCtr = CSRs.cycle val firstCtrH = CSRs.cycleh val firstHPC = CSRs.hpmcounter3 val firstHPCH = CSRs.hpmcounter3h val firstHPE = CSRs.mhpmevent3 val firstMHPC = CSRs.mhpmcounter3 val firstMHPCH = CSRs.mhpmcounter3h val firstHPM = 3 val nCtr = 32 val nHPM = nCtr - firstHPM val hpmWidth = 40 val maxPMPs = 16 } class PerfCounterIO(implicit p: Parameters) extends CoreBundle with HasCoreParameters { val eventSel = Output(UInt(xLen.W)) val inc = Input(UInt(log2Ceil(1+retireWidth).W)) } class TracedInstruction(implicit p: Parameters) extends CoreBundle { val valid = Bool() val iaddr = UInt(coreMaxAddrBits.W) val insn = UInt(iLen.W) val priv = UInt(3.W) val exception = Bool() val interrupt = Bool() val cause = UInt(xLen.W) val tval = UInt((coreMaxAddrBits max iLen).W) val wdata = Option.when(traceHasWdata)(UInt((vLen max xLen).W)) } class TraceAux extends Bundle { val enable = Bool() val stall = Bool() } class CSRDecodeIO(implicit p: Parameters) extends CoreBundle { val inst = Input(UInt(iLen.W)) def csr_addr = (inst >> 20)(CSR.ADDRSZ-1, 0) val fp_illegal = Output(Bool()) val vector_illegal = Output(Bool()) val fp_csr = Output(Bool()) val vector_csr = Output(Bool()) val rocc_illegal = Output(Bool()) val read_illegal = Output(Bool()) val write_illegal = Output(Bool()) val write_flush = Output(Bool()) val system_illegal = Output(Bool()) val virtual_access_illegal = Output(Bool()) val virtual_system_illegal = Output(Bool()) } class CSRFileIO(hasBeu: Boolean)(implicit p: Parameters) extends CoreBundle with HasCoreParameters { val ungated_clock = Input(Clock()) val interrupts = Input(new CoreInterrupts(hasBeu)) val hartid = Input(UInt(hartIdLen.W)) val rw = new Bundle { val addr = Input(UInt(CSR.ADDRSZ.W)) val cmd = Input(Bits(CSR.SZ.W)) val rdata = Output(Bits(xLen.W)) val wdata = Input(Bits(xLen.W)) } val decode = Vec(decodeWidth, new CSRDecodeIO) val csr_stall = Output(Bool()) // stall retire for wfi val rw_stall = Output(Bool()) // stall rw, rw will have no effect while rw_stall val eret = Output(Bool()) val singleStep = Output(Bool()) val status = Output(new MStatus()) val hstatus = Output(new HStatus()) val gstatus = Output(new MStatus()) val ptbr = Output(new PTBR()) val hgatp = Output(new PTBR()) val vsatp = Output(new PTBR()) val evec = Output(UInt(vaddrBitsExtended.W)) val exception = Input(Bool()) val retire = Input(UInt(log2Up(1+retireWidth).W)) val cause = Input(UInt(xLen.W)) val pc = Input(UInt(vaddrBitsExtended.W)) val tval = Input(UInt(vaddrBitsExtended.W)) val htval = Input(UInt(((maxSVAddrBits + 1) min xLen).W)) val mhtinst_read_pseudo = Input(Bool()) val gva = Input(Bool()) val time = Output(UInt(xLen.W)) val fcsr_rm = Output(Bits(FPConstants.RM_SZ.W)) val fcsr_flags = Flipped(Valid(Bits(FPConstants.FLAGS_SZ.W))) val set_fs_dirty = coreParams.haveFSDirty.option(Input(Bool())) val rocc_interrupt = Input(Bool()) val interrupt = Output(Bool()) val interrupt_cause = Output(UInt(xLen.W)) val bp = Output(Vec(nBreakpoints, new BP)) val pmp = Output(Vec(nPMPs, new PMP)) val counters = Vec(nPerfCounters, new PerfCounterIO) val csrw_counter = Output(UInt(CSR.nCtr.W)) val inhibit_cycle = Output(Bool()) val inst = Input(Vec(retireWidth, UInt(iLen.W))) val trace = Output(Vec(retireWidth, new TracedInstruction)) val mcontext = Output(UInt(coreParams.mcontextWidth.W)) val scontext = Output(UInt(coreParams.scontextWidth.W)) val fiom = Output(Bool()) val vector = usingVector.option(new Bundle { val vconfig = Output(new VConfig()) val vstart = Output(UInt(maxVLMax.log2.W)) val vxrm = Output(UInt(2.W)) val set_vs_dirty = Input(Bool()) val set_vconfig = Flipped(Valid(new VConfig)) val set_vstart = Flipped(Valid(vstart)) val set_vxsat = Input(Bool()) }) } class VConfig(implicit p: Parameters) extends CoreBundle { val vl = UInt((maxVLMax.log2 + 1).W) val vtype = new VType } object VType { def fromUInt(that: UInt, ignore_vill: Boolean = false)(implicit p: Parameters): VType = { val res = 0.U.asTypeOf(new VType) val in = that.asTypeOf(res) val vill = (in.max_vsew.U < in.vsew) || !in.lmul_ok || in.reserved =/= 0.U || in.vill when (!vill || ignore_vill.B) { res := in res.vsew := in.vsew(log2Ceil(1 + in.max_vsew) - 1, 0) } res.reserved := 0.U res.vill := vill res } def computeVL(avl: UInt, vtype: UInt, currentVL: UInt, useCurrentVL: Bool, useMax: Bool, useZero: Bool)(implicit p: Parameters): UInt = VType.fromUInt(vtype, true).vl(avl, currentVL, useCurrentVL, useMax, useZero) } class VType(implicit p: Parameters) extends CoreBundle { val vill = Bool() val reserved = UInt((xLen - 9).W) val vma = Bool() val vta = Bool() val vsew = UInt(3.W) val vlmul_sign = Bool() val vlmul_mag = UInt(2.W) def vlmul_signed: SInt = Cat(vlmul_sign, vlmul_mag).asSInt @deprecated("use vlmul_sign, vlmul_mag, or vlmul_signed", "RVV 0.9") def vlmul: UInt = vlmul_mag def max_vsew = log2Ceil(eLen/8) def max_vlmul = (1 << vlmul_mag.getWidth) - 1 def lmul_ok: Bool = Mux(this.vlmul_sign, this.vlmul_mag =/= 0.U && ~this.vlmul_mag < max_vsew.U - this.vsew, true.B) def minVLMax: Int = ((maxVLMax / eLen) >> ((1 << vlmul_mag.getWidth) - 1)) max 1 def vlMax: UInt = (maxVLMax.U >> (this.vsew +& Cat(this.vlmul_sign, ~this.vlmul_mag))).andNot((minVLMax-1).U) def vl(avl: UInt, currentVL: UInt, useCurrentVL: Bool, useMax: Bool, useZero: Bool): UInt = { val atLeastMaxVLMax = useMax || Mux(useCurrentVL, currentVL >= maxVLMax.U, avl >= maxVLMax.U) val avl_lsbs = Mux(useCurrentVL, currentVL, avl)(maxVLMax.log2 - 1, 0) val atLeastVLMax = atLeastMaxVLMax || (avl_lsbs & (-maxVLMax.S >> (this.vsew +& Cat(this.vlmul_sign, ~this.vlmul_mag))).asUInt.andNot((minVLMax-1).U)).orR val isZero = vill || useZero Mux(!isZero && atLeastVLMax, vlMax, 0.U) | Mux(!isZero && !atLeastVLMax, avl_lsbs, 0.U) } } class CSRFile( perfEventSets: EventSets = new EventSets(Seq()), customCSRs: Seq[CustomCSR] = Nil, roccCSRs: Seq[CustomCSR] = Nil, hasBeu: Boolean = false)(implicit p: Parameters) extends CoreModule()(p) with HasCoreParameters { val io = IO(new CSRFileIO(hasBeu) { val customCSRs = Vec(CSRFile.this.customCSRs.size, new CustomCSRIO) val roccCSRs = Vec(CSRFile.this.roccCSRs.size, new CustomCSRIO) }) io.rw_stall := false.B val reset_mstatus = WireDefault(0.U.asTypeOf(new MStatus())) reset_mstatus.mpp := PRV.M.U reset_mstatus.prv := PRV.M.U reset_mstatus.xs := (if (usingRoCC) 3.U else 0.U) val reg_mstatus = RegInit(reset_mstatus) val new_prv = WireDefault(reg_mstatus.prv) reg_mstatus.prv := legalizePrivilege(new_prv) val reset_dcsr = WireDefault(0.U.asTypeOf(new DCSR())) reset_dcsr.xdebugver := 1.U reset_dcsr.prv := PRV.M.U val reg_dcsr = RegInit(reset_dcsr) val (supported_interrupts, delegable_interrupts) = { val sup = Wire(new MIP) sup.usip := false.B sup.ssip := usingSupervisor.B sup.vssip := usingHypervisor.B sup.msip := true.B sup.utip := false.B sup.stip := usingSupervisor.B sup.vstip := usingHypervisor.B sup.mtip := true.B sup.ueip := false.B sup.seip := usingSupervisor.B sup.vseip := usingHypervisor.B sup.meip := true.B sup.sgeip := false.B sup.rocc := usingRoCC.B sup.debug := false.B sup.zero1 := false.B sup.lip foreach { _ := true.B } val supported_high_interrupts = if (io.interrupts.buserror.nonEmpty && !usingNMI) (BigInt(1) << CSR.busErrorIntCause).U else 0.U val del = WireDefault(sup) del.msip := false.B del.mtip := false.B del.meip := false.B (sup.asUInt | supported_high_interrupts, del.asUInt) } val delegable_base_exceptions = Seq( Causes.misaligned_fetch, Causes.fetch_page_fault, Causes.breakpoint, Causes.load_page_fault, Causes.store_page_fault, Causes.misaligned_load, Causes.misaligned_store, Causes.illegal_instruction, Causes.user_ecall, ) val delegable_hypervisor_exceptions = Seq( Causes.virtual_supervisor_ecall, Causes.fetch_guest_page_fault, Causes.load_guest_page_fault, Causes.virtual_instruction, Causes.store_guest_page_fault, ) val delegable_exceptions = ( delegable_base_exceptions ++ (if (usingHypervisor) delegable_hypervisor_exceptions else Seq()) ).map(1 << _).sum.U val hs_delegable_exceptions = Seq( Causes.misaligned_fetch, Causes.fetch_access, Causes.illegal_instruction, Causes.breakpoint, Causes.misaligned_load, Causes.load_access, Causes.misaligned_store, Causes.store_access, Causes.user_ecall, Causes.fetch_page_fault, Causes.load_page_fault, Causes.store_page_fault).map(1 << _).sum.U val (hs_delegable_interrupts, mideleg_always_hs) = { val always = WireDefault(0.U.asTypeOf(new MIP())) always.vssip := usingHypervisor.B always.vstip := usingHypervisor.B always.vseip := usingHypervisor.B val deleg = WireDefault(always) deleg.lip.foreach { _ := usingHypervisor.B } (deleg.asUInt, always.asUInt) } val reg_debug = RegInit(false.B) val reg_dpc = Reg(UInt(vaddrBitsExtended.W)) val reg_dscratch0 = Reg(UInt(xLen.W)) val reg_dscratch1 = (p(DebugModuleKey).map(_.nDscratch).getOrElse(1) > 1).option(Reg(UInt(xLen.W))) val reg_singleStepped = Reg(Bool()) val reg_mcontext = (coreParams.mcontextWidth > 0).option(RegInit(0.U(coreParams.mcontextWidth.W))) val reg_scontext = (coreParams.scontextWidth > 0).option(RegInit(0.U(coreParams.scontextWidth.W))) val reg_tselect = Reg(UInt(log2Up(nBreakpoints).W)) val reg_bp = Reg(Vec(1 << log2Up(nBreakpoints), new BP)) val reg_pmp = Reg(Vec(nPMPs, new PMPReg)) val reg_mie = Reg(UInt(xLen.W)) val (reg_mideleg, read_mideleg) = { val reg = Reg(UInt(xLen.W)) (reg, Mux(usingSupervisor.B, reg & delegable_interrupts | mideleg_always_hs, 0.U)) } val (reg_medeleg, read_medeleg) = { val reg = Reg(UInt(xLen.W)) (reg, Mux(usingSupervisor.B, reg & delegable_exceptions, 0.U)) } val reg_mip = Reg(new MIP) val reg_mepc = Reg(UInt(vaddrBitsExtended.W)) val reg_mcause = RegInit(0.U(xLen.W)) val reg_mtval = Reg(UInt(vaddrBitsExtended.W)) val reg_mtval2 = Reg(UInt(((maxSVAddrBits + 1) min xLen).W)) val reg_mscratch = Reg(Bits(xLen.W)) val mtvecWidth = paddrBits min xLen val reg_mtvec = mtvecInit match { case Some(addr) => RegInit(addr.U(mtvecWidth.W)) case None => Reg(UInt(mtvecWidth.W)) } val reset_mnstatus = WireDefault(0.U.asTypeOf(new MNStatus())) reset_mnstatus.mpp := PRV.M.U val reg_mnscratch = Reg(Bits(xLen.W)) val reg_mnepc = Reg(UInt(vaddrBitsExtended.W)) val reg_mncause = RegInit(0.U(xLen.W)) val reg_mnstatus = RegInit(reset_mnstatus) val reg_rnmie = RegInit(true.B) val nmie = reg_rnmie val reg_menvcfg = RegInit(0.U.asTypeOf(new Envcfg)) val reg_senvcfg = RegInit(0.U.asTypeOf(new Envcfg)) val reg_henvcfg = RegInit(0.U.asTypeOf(new Envcfg)) val delegable_counters = ((BigInt(1) << (nPerfCounters + CSR.firstHPM)) - 1).U val (reg_mcounteren, read_mcounteren) = { val reg = Reg(UInt(32.W)) (reg, Mux(usingUser.B, reg & delegable_counters, 0.U)) } val (reg_scounteren, read_scounteren) = { val reg = Reg(UInt(32.W)) (reg, Mux(usingSupervisor.B, reg & delegable_counters, 0.U)) } val (reg_hideleg, read_hideleg) = { val reg = Reg(UInt(xLen.W)) (reg, Mux(usingHypervisor.B, reg & hs_delegable_interrupts, 0.U)) } val (reg_hedeleg, read_hedeleg) = { val reg = Reg(UInt(xLen.W)) (reg, Mux(usingHypervisor.B, reg & hs_delegable_exceptions, 0.U)) } val hs_delegable_counters = delegable_counters val (reg_hcounteren, read_hcounteren) = { val reg = Reg(UInt(32.W)) (reg, Mux(usingHypervisor.B, reg & hs_delegable_counters, 0.U)) } val reg_hstatus = RegInit(0.U.asTypeOf(new HStatus)) val reg_hgatp = Reg(new PTBR) val reg_htval = Reg(reg_mtval2.cloneType) val read_hvip = reg_mip.asUInt & hs_delegable_interrupts val read_hie = reg_mie & hs_delegable_interrupts val (reg_vstvec, read_vstvec) = { val reg = Reg(UInt(vaddrBitsExtended.W)) (reg, formTVec(reg).sextTo(xLen)) } val reg_vsstatus = Reg(new MStatus) val reg_vsscratch = Reg(Bits(xLen.W)) val reg_vsepc = Reg(UInt(vaddrBitsExtended.W)) val reg_vscause = Reg(Bits(xLen.W)) val reg_vstval = Reg(UInt(vaddrBitsExtended.W)) val reg_vsatp = Reg(new PTBR) val reg_sepc = Reg(UInt(vaddrBitsExtended.W)) val reg_scause = Reg(Bits(xLen.W)) val reg_stval = Reg(UInt(vaddrBitsExtended.W)) val reg_sscratch = Reg(Bits(xLen.W)) val reg_stvec = Reg(UInt((if (usingHypervisor) vaddrBitsExtended else vaddrBits).W)) val reg_satp = Reg(new PTBR) val reg_wfi = withClock(io.ungated_clock) { RegInit(false.B) } val reg_fflags = Reg(UInt(5.W)) val reg_frm = Reg(UInt(3.W)) val reg_vconfig = usingVector.option(Reg(new VConfig)) val reg_vstart = usingVector.option(Reg(UInt(maxVLMax.log2.W))) val reg_vxsat = usingVector.option(Reg(Bool())) val reg_vxrm = usingVector.option(Reg(UInt(io.vector.get.vxrm.getWidth.W))) val reg_mtinst_read_pseudo = Reg(Bool()) val reg_htinst_read_pseudo = Reg(Bool()) // XLEN=32: 0x00002000 // XLEN=64: 0x00003000 val Seq(read_mtinst, read_htinst) = Seq(reg_mtinst_read_pseudo, reg_htinst_read_pseudo).map(r => Cat(r, (xLen == 32).option(0.U).getOrElse(r), 0.U(12.W))) val reg_mcountinhibit = RegInit(0.U((CSR.firstHPM + nPerfCounters).W)) io.inhibit_cycle := reg_mcountinhibit(0) val reg_instret = WideCounter(64, io.retire, inhibit = reg_mcountinhibit(2)) val reg_cycle = if (enableCommitLog) WideCounter(64, io.retire, inhibit = reg_mcountinhibit(0)) else withClock(io.ungated_clock) { WideCounter(64, !io.csr_stall, inhibit = reg_mcountinhibit(0)) } val reg_hpmevent = io.counters.map(c => RegInit(0.U(xLen.W))) (io.counters zip reg_hpmevent) foreach { case (c, e) => c.eventSel := e } val reg_hpmcounter = io.counters.zipWithIndex.map { case (c, i) => WideCounter(CSR.hpmWidth, c.inc, reset = false, inhibit = reg_mcountinhibit(CSR.firstHPM+i)) } val mip = WireDefault(reg_mip) mip.lip := (io.interrupts.lip: Seq[Bool]) mip.mtip := io.interrupts.mtip mip.msip := io.interrupts.msip mip.meip := io.interrupts.meip // seip is the OR of reg_mip.seip and the actual line from the PLIC io.interrupts.seip.foreach { mip.seip := reg_mip.seip || _ } // Simimlar sort of thing would apply if the PLIC had a VSEIP line: //io.interrupts.vseip.foreach { mip.vseip := reg_mip.vseip || _ } mip.rocc := io.rocc_interrupt val read_mip = mip.asUInt & supported_interrupts val read_hip = read_mip & hs_delegable_interrupts val high_interrupts = (if (usingNMI) 0.U else io.interrupts.buserror.map(_ << CSR.busErrorIntCause).getOrElse(0.U)) val pending_interrupts = high_interrupts | (read_mip & reg_mie) val d_interrupts = io.interrupts.debug << CSR.debugIntCause val (nmi_interrupts, nmiFlag) = io.interrupts.nmi.map(nmi => (((nmi.rnmi && reg_rnmie) << CSR.rnmiIntCause) | io.interrupts.buserror.map(_ << CSR.rnmiBEUCause).getOrElse(0.U), !io.interrupts.debug && nmi.rnmi && reg_rnmie)).getOrElse(0.U, false.B) val m_interrupts = Mux(nmie && (reg_mstatus.prv <= PRV.S.U || reg_mstatus.mie), ~(~pending_interrupts | read_mideleg), 0.U) val s_interrupts = Mux(nmie && (reg_mstatus.v || reg_mstatus.prv < PRV.S.U || (reg_mstatus.prv === PRV.S.U && reg_mstatus.sie)), pending_interrupts & read_mideleg & ~read_hideleg, 0.U) val vs_interrupts = Mux(nmie && (reg_mstatus.v && (reg_mstatus.prv < PRV.S.U || reg_mstatus.prv === PRV.S.U && reg_vsstatus.sie)), pending_interrupts & read_hideleg, 0.U) val (anyInterrupt, whichInterrupt) = chooseInterrupt(Seq(vs_interrupts, s_interrupts, m_interrupts, nmi_interrupts, d_interrupts)) val interruptMSB = BigInt(1) << (xLen-1) val interruptCause = interruptMSB.U + (nmiFlag << (xLen-2)) + whichInterrupt io.interrupt := (anyInterrupt && !io.singleStep || reg_singleStepped) && !(reg_debug || io.status.cease) io.interrupt_cause := interruptCause io.bp := reg_bp take nBreakpoints io.mcontext := reg_mcontext.getOrElse(0.U) io.scontext := reg_scontext.getOrElse(0.U) io.fiom := (reg_mstatus.prv < PRV.M.U && reg_menvcfg.fiom) || (reg_mstatus.prv < PRV.S.U && reg_senvcfg.fiom) || (reg_mstatus.v && reg_henvcfg.fiom) io.pmp := reg_pmp.map(PMP(_)) val isaMaskString = (if (usingMulDiv) "M" else "") + (if (usingAtomics) "A" else "") + (if (fLen >= 32) "F" else "") + (if (fLen >= 64) "D" else "") + (if (coreParams.hasV) "V" else "") + (if (usingCompressed) "C" else "") val isaString = (if (coreParams.useRVE) "E" else "I") + isaMaskString + (if (customIsaExt.isDefined || usingRoCC) "X" else "") + (if (usingSupervisor) "S" else "") + (if (usingHypervisor) "H" else "") + (if (usingUser) "U" else "") val isaMax = (BigInt(log2Ceil(xLen) - 4) << (xLen-2)) | isaStringToMask(isaString) val reg_misa = RegInit(isaMax.U) val read_mstatus = io.status.asUInt.extract(xLen-1,0) val read_mtvec = formTVec(reg_mtvec).padTo(xLen) val read_stvec = formTVec(reg_stvec).sextTo(xLen) val read_mapping = LinkedHashMap[Int,Bits]( CSRs.tselect -> reg_tselect, CSRs.tdata1 -> reg_bp(reg_tselect).control.asUInt, CSRs.tdata2 -> reg_bp(reg_tselect).address.sextTo(xLen), CSRs.tdata3 -> reg_bp(reg_tselect).textra.asUInt, CSRs.misa -> reg_misa, CSRs.mstatus -> read_mstatus, CSRs.mtvec -> read_mtvec, CSRs.mip -> read_mip, CSRs.mie -> reg_mie, CSRs.mscratch -> reg_mscratch, CSRs.mepc -> readEPC(reg_mepc).sextTo(xLen), CSRs.mtval -> reg_mtval.sextTo(xLen), CSRs.mcause -> reg_mcause, CSRs.mhartid -> io.hartid) val debug_csrs = if (!usingDebug) LinkedHashMap() else LinkedHashMap[Int,Bits]( CSRs.dcsr -> reg_dcsr.asUInt, CSRs.dpc -> readEPC(reg_dpc).sextTo(xLen), CSRs.dscratch0 -> reg_dscratch0.asUInt) ++ reg_dscratch1.map(r => CSRs.dscratch1 -> r) val read_mnstatus = WireInit(0.U.asTypeOf(new MNStatus())) read_mnstatus.mpp := reg_mnstatus.mpp read_mnstatus.mpv := reg_mnstatus.mpv read_mnstatus.mie := reg_rnmie val nmi_csrs = if (!usingNMI) LinkedHashMap() else LinkedHashMap[Int,Bits]( CustomCSRs.mnscratch -> reg_mnscratch, CustomCSRs.mnepc -> readEPC(reg_mnepc).sextTo(xLen), CustomCSRs.mncause -> reg_mncause, CustomCSRs.mnstatus -> read_mnstatus.asUInt) val context_csrs = LinkedHashMap[Int,Bits]() ++ reg_mcontext.map(r => CSRs.mcontext -> r) ++ reg_scontext.map(r => CSRs.scontext -> r) val read_fcsr = Cat(reg_frm, reg_fflags) val fp_csrs = LinkedHashMap[Int,Bits]() ++ usingFPU.option(CSRs.fflags -> reg_fflags) ++ usingFPU.option(CSRs.frm -> reg_frm) ++ (usingFPU || usingVector).option(CSRs.fcsr -> read_fcsr) val read_vcsr = Cat(reg_vxrm.getOrElse(0.U), reg_vxsat.getOrElse(0.U)) val vector_csrs = if (!usingVector) LinkedHashMap() else LinkedHashMap[Int,Bits]( CSRs.vxsat -> reg_vxsat.get, CSRs.vxrm -> reg_vxrm.get, CSRs.vcsr -> read_vcsr, CSRs.vstart -> reg_vstart.get, CSRs.vtype -> reg_vconfig.get.vtype.asUInt, CSRs.vl -> reg_vconfig.get.vl, CSRs.vlenb -> (vLen / 8).U) read_mapping ++= debug_csrs read_mapping ++= nmi_csrs read_mapping ++= context_csrs read_mapping ++= fp_csrs read_mapping ++= vector_csrs if (coreParams.haveBasicCounters) { read_mapping += CSRs.mcountinhibit -> reg_mcountinhibit read_mapping += CSRs.mcycle -> reg_cycle read_mapping += CSRs.minstret -> reg_instret for (((e, c), i) <- (reg_hpmevent.padTo(CSR.nHPM, 0.U) zip reg_hpmcounter.map(x => x: UInt).padTo(CSR.nHPM, 0.U)).zipWithIndex) { read_mapping += (i + CSR.firstHPE) -> e // mhpmeventN read_mapping += (i + CSR.firstMHPC) -> c // mhpmcounterN read_mapping += (i + CSR.firstHPC) -> c // hpmcounterN if (xLen == 32) { read_mapping += (i + CSR.firstMHPCH) -> (c >> 32) // mhpmcounterNh read_mapping += (i + CSR.firstHPCH) -> (c >> 32) // hpmcounterNh } } if (usingUser) { read_mapping += CSRs.mcounteren -> read_mcounteren } read_mapping += CSRs.cycle -> reg_cycle read_mapping += CSRs.instret -> reg_instret if (xLen == 32) { read_mapping += CSRs.mcycleh -> (reg_cycle >> 32) read_mapping += CSRs.minstreth -> (reg_instret >> 32) read_mapping += CSRs.cycleh -> (reg_cycle >> 32) read_mapping += CSRs.instreth -> (reg_instret >> 32) } } if (usingUser) { read_mapping += CSRs.menvcfg -> reg_menvcfg.asUInt if (xLen == 32) read_mapping += CSRs.menvcfgh -> (reg_menvcfg.asUInt >> 32) } val sie_mask = { val sgeip_mask = WireInit(0.U.asTypeOf(new MIP)) sgeip_mask.sgeip := true.B read_mideleg & ~(hs_delegable_interrupts | sgeip_mask.asUInt) } if (usingSupervisor) { val read_sie = reg_mie & sie_mask val read_sip = read_mip & sie_mask val read_sstatus = WireDefault(0.U.asTypeOf(new MStatus)) read_sstatus.sd := io.status.sd read_sstatus.uxl := io.status.uxl read_sstatus.sd_rv32 := io.status.sd_rv32 read_sstatus.mxr := io.status.mxr read_sstatus.sum := io.status.sum read_sstatus.xs := io.status.xs read_sstatus.fs := io.status.fs read_sstatus.vs := io.status.vs read_sstatus.spp := io.status.spp read_sstatus.spie := io.status.spie read_sstatus.sie := io.status.sie read_mapping += CSRs.sstatus -> (read_sstatus.asUInt)(xLen-1,0) read_mapping += CSRs.sip -> read_sip.asUInt read_mapping += CSRs.sie -> read_sie.asUInt read_mapping += CSRs.sscratch -> reg_sscratch read_mapping += CSRs.scause -> reg_scause read_mapping += CSRs.stval -> reg_stval.sextTo(xLen) read_mapping += CSRs.satp -> reg_satp.asUInt read_mapping += CSRs.sepc -> readEPC(reg_sepc).sextTo(xLen) read_mapping += CSRs.stvec -> read_stvec read_mapping += CSRs.scounteren -> read_scounteren read_mapping += CSRs.mideleg -> read_mideleg read_mapping += CSRs.medeleg -> read_medeleg read_mapping += CSRs.senvcfg -> reg_senvcfg.asUInt } val pmpCfgPerCSR = xLen / new PMPConfig().getWidth def pmpCfgIndex(i: Int) = (xLen / 32) * (i / pmpCfgPerCSR) if (reg_pmp.nonEmpty) { require(reg_pmp.size <= CSR.maxPMPs) val read_pmp = reg_pmp.padTo(CSR.maxPMPs, 0.U.asTypeOf(new PMP)) for (i <- 0 until read_pmp.size by pmpCfgPerCSR) read_mapping += (CSRs.pmpcfg0 + pmpCfgIndex(i)) -> read_pmp.map(_.cfg).slice(i, i + pmpCfgPerCSR).asUInt for ((pmp, i) <- read_pmp.zipWithIndex) read_mapping += (CSRs.pmpaddr0 + i) -> pmp.readAddr } // implementation-defined CSRs def generateCustomCSR(csr: CustomCSR, csr_io: CustomCSRIO) = { require(csr.mask >= 0 && csr.mask.bitLength <= xLen) require(!read_mapping.contains(csr.id)) val reg = csr.init.map(init => RegInit(init.U(xLen.W))).getOrElse(Reg(UInt(xLen.W))) val read = io.rw.cmd =/= CSR.N && io.rw.addr === csr.id.U csr_io.ren := read when (read && csr_io.stall) { io.rw_stall := true.B } read_mapping += csr.id -> reg reg } val reg_custom = customCSRs.zip(io.customCSRs).map(t => generateCustomCSR(t._1, t._2)) val reg_rocc = roccCSRs.zip(io.roccCSRs).map(t => generateCustomCSR(t._1, t._2)) if (usingHypervisor) { read_mapping += CSRs.mtinst -> read_mtinst read_mapping += CSRs.mtval2 -> reg_mtval2 val read_hstatus = io.hstatus.asUInt.extract(xLen-1,0) read_mapping += CSRs.hstatus -> read_hstatus read_mapping += CSRs.hedeleg -> read_hedeleg read_mapping += CSRs.hideleg -> read_hideleg read_mapping += CSRs.hcounteren-> read_hcounteren read_mapping += CSRs.hgatp -> reg_hgatp.asUInt read_mapping += CSRs.hip -> read_hip read_mapping += CSRs.hie -> read_hie read_mapping += CSRs.hvip -> read_hvip read_mapping += CSRs.hgeie -> 0.U read_mapping += CSRs.hgeip -> 0.U read_mapping += CSRs.htval -> reg_htval read_mapping += CSRs.htinst -> read_htinst read_mapping += CSRs.henvcfg -> reg_henvcfg.asUInt if (xLen == 32) read_mapping += CSRs.henvcfgh -> (reg_henvcfg.asUInt >> 32) val read_vsie = (read_hie & read_hideleg) >> 1 val read_vsip = (read_hip & read_hideleg) >> 1 val read_vsepc = readEPC(reg_vsepc).sextTo(xLen) val read_vstval = reg_vstval.sextTo(xLen) val read_vsstatus = io.gstatus.asUInt.extract(xLen-1,0) read_mapping += CSRs.vsstatus -> read_vsstatus read_mapping += CSRs.vsip -> read_vsip read_mapping += CSRs.vsie -> read_vsie read_mapping += CSRs.vsscratch -> reg_vsscratch read_mapping += CSRs.vscause -> reg_vscause read_mapping += CSRs.vstval -> read_vstval read_mapping += CSRs.vsatp -> reg_vsatp.asUInt read_mapping += CSRs.vsepc -> read_vsepc read_mapping += CSRs.vstvec -> read_vstvec } // mimpid, marchid, mvendorid, and mconfigptr are 0 unless overridden by customCSRs Seq(CSRs.mimpid, CSRs.marchid, CSRs.mvendorid, CSRs.mconfigptr).foreach(id => read_mapping.getOrElseUpdate(id, 0.U)) val decoded_addr = { val addr = Cat(io.status.v, io.rw.addr) val pats = for (((k, _), i) <- read_mapping.zipWithIndex) yield (BitPat(k.U), (0 until read_mapping.size).map(j => BitPat((i == j).B))) val decoded = DecodeLogic(addr, Seq.fill(read_mapping.size)(X), pats) val unvirtualized_mapping = (for (((k, _), v) <- read_mapping zip decoded) yield k -> v.asBool).toMap for ((k, v) <- unvirtualized_mapping) yield k -> { val alt: Option[Bool] = CSR.mode(k) match { // hcontext was assigned an unfortunate address; it lives where a // hypothetical vscontext will live. Exclude them from the S/VS remapping. // (on separate lines so scala-lint doesnt do something stupid) case _ if k == CSRs.scontext => None case _ if k == CSRs.hcontext => None // When V=1, if a corresponding VS CSR exists, access it instead... case PRV.H => unvirtualized_mapping.lift(k - (1 << CSR.modeLSB)) // ...and don't access the original S-mode version. case PRV.S => unvirtualized_mapping.contains(k + (1 << CSR.modeLSB)).option(false.B) case _ => None } alt.map(Mux(reg_mstatus.v, _, v)).getOrElse(v) } } val wdata = readModifyWriteCSR(io.rw.cmd, io.rw.rdata, io.rw.wdata) val system_insn = io.rw.cmd === CSR.I val hlsv = Seq(HLV_B, HLV_BU, HLV_H, HLV_HU, HLV_W, HLV_WU, HLV_D, HSV_B, HSV_H, HSV_W, HSV_D, HLVX_HU, HLVX_WU) val decode_table = Seq( ECALL-> List(Y,N,N,N,N,N,N,N,N), EBREAK-> List(N,Y,N,N,N,N,N,N,N), MRET-> List(N,N,Y,N,N,N,N,N,N), CEASE-> List(N,N,N,Y,N,N,N,N,N), WFI-> List(N,N,N,N,Y,N,N,N,N)) ++ usingDebug.option( DRET-> List(N,N,Y,N,N,N,N,N,N)) ++ usingNMI.option( MNRET-> List(N,N,Y,N,N,N,N,N,N)) ++ coreParams.haveCFlush.option(CFLUSH_D_L1-> List(N,N,N,N,N,N,N,N,N)) ++ usingSupervisor.option( SRET-> List(N,N,Y,N,N,N,N,N,N)) ++ usingVM.option( SFENCE_VMA-> List(N,N,N,N,N,Y,N,N,N)) ++ usingHypervisor.option( HFENCE_VVMA-> List(N,N,N,N,N,N,Y,N,N)) ++ usingHypervisor.option( HFENCE_GVMA-> List(N,N,N,N,N,N,N,Y,N)) ++ (if (usingHypervisor) hlsv.map(_-> List(N,N,N,N,N,N,N,N,Y)) else Seq()) val insn_call :: insn_break :: insn_ret :: insn_cease :: insn_wfi :: _ :: _ :: _ :: _ :: Nil = { val insn = ECALL.value.U | (io.rw.addr << 20) DecodeLogic(insn, decode_table(0)._2.map(x=>X), decode_table).map(system_insn && _.asBool) } for (io_dec <- io.decode) { val addr = io_dec.inst(31, 20) def decodeAny(m: LinkedHashMap[Int,Bits]): Bool = m.map { case(k: Int, _: Bits) => addr === k.U }.reduce(_||_) def decodeFast(s: Seq[Int]): Bool = DecodeLogic(addr, s.map(_.U), (read_mapping -- s).keys.toList.map(_.U)) val _ :: is_break :: is_ret :: _ :: is_wfi :: is_sfence :: is_hfence_vvma :: is_hfence_gvma :: is_hlsv :: Nil = DecodeLogic(io_dec.inst, decode_table(0)._2.map(x=>X), decode_table).map(_.asBool) val is_counter = (addr.inRange(CSR.firstCtr.U, (CSR.firstCtr + CSR.nCtr).U) || addr.inRange(CSR.firstCtrH.U, (CSR.firstCtrH + CSR.nCtr).U)) val allow_wfi = (!usingSupervisor).B || reg_mstatus.prv > PRV.S.U || !reg_mstatus.tw && (!reg_mstatus.v || !reg_hstatus.vtw) val allow_sfence_vma = (!usingVM).B || reg_mstatus.prv > PRV.S.U || !Mux(reg_mstatus.v, reg_hstatus.vtvm, reg_mstatus.tvm) val allow_hfence_vvma = (!usingHypervisor).B || !reg_mstatus.v && (reg_mstatus.prv >= PRV.S.U) val allow_hlsv = (!usingHypervisor).B || !reg_mstatus.v && (reg_mstatus.prv >= PRV.S.U || reg_hstatus.hu) val allow_sret = (!usingSupervisor).B || reg_mstatus.prv > PRV.S.U || !Mux(reg_mstatus.v, reg_hstatus.vtsr, reg_mstatus.tsr) val counter_addr = addr(log2Ceil(read_mcounteren.getWidth)-1, 0) val allow_counter = (reg_mstatus.prv > PRV.S.U || read_mcounteren(counter_addr)) && (!usingSupervisor.B || reg_mstatus.prv >= PRV.S.U || read_scounteren(counter_addr)) && (!usingHypervisor.B || !reg_mstatus.v || read_hcounteren(counter_addr)) io_dec.fp_illegal := io.status.fs === 0.U || reg_mstatus.v && reg_vsstatus.fs === 0.U || !reg_misa('f'-'a') io_dec.vector_illegal := io.status.vs === 0.U || reg_mstatus.v && reg_vsstatus.vs === 0.U || !reg_misa('v'-'a') io_dec.fp_csr := decodeFast(fp_csrs.keys.toList) io_dec.vector_csr := decodeFast(vector_csrs.keys.toList) io_dec.rocc_illegal := io.status.xs === 0.U || reg_mstatus.v && reg_vsstatus.xs === 0.U || !reg_misa('x'-'a') val csr_addr_legal = reg_mstatus.prv >= CSR.mode(addr) || usingHypervisor.B && !reg_mstatus.v && reg_mstatus.prv === PRV.S.U && CSR.mode(addr) === PRV.H.U val csr_exists = decodeAny(read_mapping) io_dec.read_illegal := !csr_addr_legal || !csr_exists || ((addr === CSRs.satp.U || addr === CSRs.hgatp.U) && !allow_sfence_vma) || is_counter && !allow_counter || decodeFast(debug_csrs.keys.toList) && !reg_debug || decodeFast(vector_csrs.keys.toList) && io_dec.vector_illegal || io_dec.fp_csr && io_dec.fp_illegal io_dec.write_illegal := addr(11,10).andR io_dec.write_flush := { val addr_m = addr | (PRV.M.U << CSR.modeLSB) !(addr_m >= CSRs.mscratch.U && addr_m <= CSRs.mtval.U) } io_dec.system_illegal := !csr_addr_legal && !is_hlsv || is_wfi && !allow_wfi || is_ret && !allow_sret || is_ret && addr(10) && addr(7) && !reg_debug || (is_sfence || is_hfence_gvma) && !allow_sfence_vma || is_hfence_vvma && !allow_hfence_vvma || is_hlsv && !allow_hlsv io_dec.virtual_access_illegal := reg_mstatus.v && csr_exists && ( CSR.mode(addr) === PRV.H.U || is_counter && read_mcounteren(counter_addr) && (!read_hcounteren(counter_addr) || !reg_mstatus.prv(0) && !read_scounteren(counter_addr)) || CSR.mode(addr) === PRV.S.U && !reg_mstatus.prv(0) || addr === CSRs.satp.U && reg_mstatus.prv(0) && reg_hstatus.vtvm) io_dec.virtual_system_illegal := reg_mstatus.v && ( is_hfence_vvma || is_hfence_gvma || is_hlsv || is_wfi && (!reg_mstatus.prv(0) || !reg_mstatus.tw && reg_hstatus.vtw) || is_ret && CSR.mode(addr) === PRV.S.U && (!reg_mstatus.prv(0) || reg_hstatus.vtsr) || is_sfence && (!reg_mstatus.prv(0) || reg_hstatus.vtvm)) } val cause = Mux(insn_call, Causes.user_ecall.U + Mux(reg_mstatus.prv(0) && reg_mstatus.v, PRV.H.U, reg_mstatus.prv), Mux[UInt](insn_break, Causes.breakpoint.U, io.cause)) val cause_lsbs = cause(log2Ceil(1 + CSR.busErrorIntCause)-1, 0) val cause_deleg_lsbs = cause(log2Ceil(xLen)-1,0) val causeIsDebugInt = cause(xLen-1) && cause_lsbs === CSR.debugIntCause.U val causeIsDebugTrigger = !cause(xLen-1) && cause_lsbs === CSR.debugTriggerCause.U val causeIsDebugBreak = !cause(xLen-1) && insn_break && Cat(reg_dcsr.ebreakm, reg_dcsr.ebreakh, reg_dcsr.ebreaks, reg_dcsr.ebreaku)(reg_mstatus.prv) val trapToDebug = usingDebug.B && (reg_singleStepped || causeIsDebugInt || causeIsDebugTrigger || causeIsDebugBreak || reg_debug) val debugEntry = p(DebugModuleKey).map(_.debugEntry).getOrElse(BigInt(0x800)) val debugException = p(DebugModuleKey).map(_.debugException).getOrElse(BigInt(0x808)) val debugTVec = Mux(reg_debug, Mux(insn_break, debugEntry.U, debugException.U), debugEntry.U) val delegate = usingSupervisor.B && reg_mstatus.prv <= PRV.S.U && Mux(cause(xLen-1), read_mideleg(cause_deleg_lsbs), read_medeleg(cause_deleg_lsbs)) val delegateVS = reg_mstatus.v && delegate && Mux(cause(xLen-1), read_hideleg(cause_deleg_lsbs), read_hedeleg(cause_deleg_lsbs)) def mtvecBaseAlign = 2 def mtvecInterruptAlign = { require(reg_mip.getWidth <= xLen) log2Ceil(xLen) } val notDebugTVec = { val base = Mux(delegate, Mux(delegateVS, read_vstvec, read_stvec), read_mtvec) val interruptOffset = cause(mtvecInterruptAlign-1, 0) << mtvecBaseAlign val interruptVec = Cat(base >> (mtvecInterruptAlign + mtvecBaseAlign), interruptOffset) val doVector = base(0) && cause(cause.getWidth-1) && (cause_lsbs >> mtvecInterruptAlign) === 0.U Mux(doVector, interruptVec, base >> mtvecBaseAlign << mtvecBaseAlign) } val causeIsRnmiInt = cause(xLen-1) && cause(xLen-2) && (cause_lsbs === CSR.rnmiIntCause.U || cause_lsbs === CSR.rnmiBEUCause.U) val causeIsRnmiBEU = cause(xLen-1) && cause(xLen-2) && cause_lsbs === CSR.rnmiBEUCause.U val causeIsNmi = causeIsRnmiInt val nmiTVecInt = io.interrupts.nmi.map(nmi => nmi.rnmi_interrupt_vector).getOrElse(0.U) val nmiTVecXcpt = io.interrupts.nmi.map(nmi => nmi.rnmi_exception_vector).getOrElse(0.U) val trapToNmiInt = usingNMI.B && causeIsNmi val trapToNmiXcpt = usingNMI.B && !nmie val trapToNmi = trapToNmiInt || trapToNmiXcpt val nmiTVec = (Mux(causeIsNmi, nmiTVecInt, nmiTVecXcpt)>>1)<<1 val tvec = Mux(trapToDebug, debugTVec, Mux(trapToNmi, nmiTVec, notDebugTVec)) io.evec := tvec io.ptbr := reg_satp io.hgatp := reg_hgatp io.vsatp := reg_vsatp io.eret := insn_call || insn_break || insn_ret io.singleStep := reg_dcsr.step && !reg_debug io.status := reg_mstatus io.status.sd := io.status.fs.andR || io.status.xs.andR || io.status.vs.andR io.status.debug := reg_debug io.status.isa := reg_misa io.status.uxl := (if (usingUser) log2Ceil(xLen) - 4 else 0).U io.status.sxl := (if (usingSupervisor) log2Ceil(xLen) - 4 else 0).U io.status.dprv := Mux(reg_mstatus.mprv && !reg_debug, reg_mstatus.mpp, reg_mstatus.prv) io.status.dv := reg_mstatus.v || Mux(reg_mstatus.mprv && !reg_debug, reg_mstatus.mpv, false.B) io.status.sd_rv32 := (xLen == 32).B && io.status.sd io.status.mpv := reg_mstatus.mpv io.status.gva := reg_mstatus.gva io.hstatus := reg_hstatus io.hstatus.vsxl := (if (usingSupervisor) log2Ceil(xLen) - 4 else 0).U io.gstatus := reg_vsstatus io.gstatus.sd := io.gstatus.fs.andR || io.gstatus.xs.andR || io.gstatus.vs.andR io.gstatus.uxl := (if (usingUser) log2Ceil(xLen) - 4 else 0).U io.gstatus.sd_rv32 := (xLen == 32).B && io.gstatus.sd val exception = insn_call || insn_break || io.exception assert(PopCount(insn_ret :: insn_call :: insn_break :: io.exception :: Nil) <= 1.U, "these conditions must be mutually exclusive") when (insn_wfi && !io.singleStep && !reg_debug) { reg_wfi := true.B } when (pending_interrupts.orR || io.interrupts.debug || exception) { reg_wfi := false.B } io.interrupts.nmi.map(nmi => when (nmi.rnmi) { reg_wfi := false.B } ) when (io.retire(0) || exception) { reg_singleStepped := true.B } when (!io.singleStep) { reg_singleStepped := false.B } assert(!io.singleStep || io.retire <= 1.U) assert(!reg_singleStepped || io.retire === 0.U) val epc = formEPC(io.pc) val tval = Mux(insn_break, epc, io.tval) when (exception) { when (trapToDebug) { when (!reg_debug) { reg_mstatus.v := false.B reg_debug := true.B reg_dpc := epc reg_dcsr.cause := Mux(reg_singleStepped, 4.U, Mux(causeIsDebugInt, 3.U, Mux[UInt](causeIsDebugTrigger, 2.U, 1.U))) reg_dcsr.prv := trimPrivilege(reg_mstatus.prv) reg_dcsr.v := reg_mstatus.v new_prv := PRV.M.U } }.elsewhen (trapToNmiInt) { when (reg_rnmie) { reg_mstatus.v := false.B reg_mnstatus.mpv := reg_mstatus.v reg_rnmie := false.B reg_mnepc := epc reg_mncause := (BigInt(1) << (xLen-1)).U | Mux(causeIsRnmiBEU, 3.U, 2.U) reg_mnstatus.mpp := trimPrivilege(reg_mstatus.prv) new_prv := PRV.M.U } }.elsewhen (delegateVS && nmie) { reg_mstatus.v := true.B reg_vsstatus.spp := reg_mstatus.prv reg_vsepc := epc reg_vscause := Mux(cause(xLen-1), Cat(cause(xLen-1, 2), 1.U(2.W)), cause) reg_vstval := tval reg_vsstatus.spie := reg_vsstatus.sie reg_vsstatus.sie := false.B new_prv := PRV.S.U }.elsewhen (delegate && nmie) { reg_mstatus.v := false.B reg_hstatus.spvp := Mux(reg_mstatus.v, reg_mstatus.prv(0),reg_hstatus.spvp) reg_hstatus.gva := io.gva reg_hstatus.spv := reg_mstatus.v reg_sepc := epc reg_scause := cause reg_stval := tval reg_htval := io.htval reg_htinst_read_pseudo := io.mhtinst_read_pseudo reg_mstatus.spie := reg_mstatus.sie reg_mstatus.spp := reg_mstatus.prv reg_mstatus.sie := false.B new_prv := PRV.S.U }.otherwise { reg_mstatus.v := false.B reg_mstatus.mpv := reg_mstatus.v reg_mstatus.gva := io.gva reg_mepc := epc reg_mcause := cause reg_mtval := tval reg_mtval2 := io.htval reg_mtinst_read_pseudo := io.mhtinst_read_pseudo reg_mstatus.mpie := reg_mstatus.mie reg_mstatus.mpp := trimPrivilege(reg_mstatus.prv) reg_mstatus.mie := false.B new_prv := PRV.M.U } } for (i <- 0 until supported_interrupts.getWidth) { val en = exception && (supported_interrupts & (BigInt(1) << i).U) =/= 0.U && cause === (BigInt(1) << (xLen - 1)).U + i.U val delegable = (delegable_interrupts & (BigInt(1) << i).U) =/= 0.U property.cover(en && !delegate, s"INTERRUPT_M_$i") property.cover(en && delegable && delegate, s"INTERRUPT_S_$i") } for (i <- 0 until xLen) { val supported_exceptions: BigInt = 0x8fe | (if (usingCompressed && !coreParams.misaWritable) 0 else 1) | (if (usingUser) 0x100 else 0) | (if (usingSupervisor) 0x200 else 0) | (if (usingVM) 0xb000 else 0) if (((supported_exceptions >> i) & 1) != 0) { val en = exception && cause === i.U val delegable = (delegable_exceptions & (BigInt(1) << i).U) =/= 0.U property.cover(en && !delegate, s"EXCEPTION_M_$i") property.cover(en && delegable && delegate, s"EXCEPTION_S_$i") } } when (insn_ret) { val ret_prv = WireInit(UInt(), DontCare) when (usingSupervisor.B && !io.rw.addr(9)) { when (!reg_mstatus.v) { reg_mstatus.sie := reg_mstatus.spie reg_mstatus.spie := true.B reg_mstatus.spp := PRV.U.U ret_prv := reg_mstatus.spp reg_mstatus.v := usingHypervisor.B && reg_hstatus.spv io.evec := readEPC(reg_sepc) reg_hstatus.spv := false.B }.otherwise { reg_vsstatus.sie := reg_vsstatus.spie reg_vsstatus.spie := true.B reg_vsstatus.spp := PRV.U.U ret_prv := reg_vsstatus.spp reg_mstatus.v := usingHypervisor.B io.evec := readEPC(reg_vsepc) } }.elsewhen (usingDebug.B && io.rw.addr(10) && io.rw.addr(7)) { ret_prv := reg_dcsr.prv reg_mstatus.v := usingHypervisor.B && reg_dcsr.v && reg_dcsr.prv <= PRV.S.U reg_debug := false.B io.evec := readEPC(reg_dpc) }.elsewhen (usingNMI.B && io.rw.addr(10) && !io.rw.addr(7)) { ret_prv := reg_mnstatus.mpp reg_mstatus.v := usingHypervisor.B && reg_mnstatus.mpv && reg_mnstatus.mpp <= PRV.S.U reg_rnmie := true.B io.evec := readEPC(reg_mnepc) }.otherwise { reg_mstatus.mie := reg_mstatus.mpie reg_mstatus.mpie := true.B reg_mstatus.mpp := legalizePrivilege(PRV.U.U) reg_mstatus.mpv := false.B ret_prv := reg_mstatus.mpp reg_mstatus.v := usingHypervisor.B && reg_mstatus.mpv && reg_mstatus.mpp <= PRV.S.U io.evec := readEPC(reg_mepc) } new_prv := ret_prv when (usingUser.B && ret_prv <= PRV.S.U) { reg_mstatus.mprv := false.B } } io.time := reg_cycle io.csr_stall := reg_wfi || io.status.cease io.status.cease := RegEnable(true.B, false.B, insn_cease) io.status.wfi := reg_wfi for ((io, reg) <- io.customCSRs zip reg_custom) { io.wen := false.B io.wdata := wdata io.value := reg } for ((io, reg) <- io.roccCSRs zip reg_rocc) { io.wen := false.B io.wdata := wdata io.value := reg } io.rw.rdata := Mux1H(for ((k, v) <- read_mapping) yield decoded_addr(k) -> v) // cover access to register val coverable_counters = read_mapping.filterNot { case (k, _) => k >= CSR.firstHPC + nPerfCounters && k < CSR.firstHPC + CSR.nHPM } coverable_counters.foreach( {case (k, v) => { when (!k.U(11,10).andR) { // Cover points for RW CSR registers property.cover(io.rw.cmd.isOneOf(CSR.W, CSR.S, CSR.C) && io.rw.addr===k.U, "CSR_access_"+k.toString, "Cover Accessing Core CSR field") } .otherwise { // Cover points for RO CSR registers property.cover(io.rw.cmd===CSR.R && io.rw.addr===k.U, "CSR_access_"+k.toString, "Cover Accessing Core CSR field") } }}) val set_vs_dirty = WireDefault(io.vector.map(_.set_vs_dirty).getOrElse(false.B)) io.vector.foreach { vio => when (set_vs_dirty) { assert(reg_mstatus.vs > 0.U) when (reg_mstatus.v) { reg_vsstatus.vs := 3.U } reg_mstatus.vs := 3.U } } val set_fs_dirty = WireDefault(io.set_fs_dirty.getOrElse(false.B)) if (coreParams.haveFSDirty) { when (set_fs_dirty) { assert(reg_mstatus.fs > 0.U) when (reg_mstatus.v) { reg_vsstatus.fs := 3.U } reg_mstatus.fs := 3.U } } io.fcsr_rm := reg_frm when (io.fcsr_flags.valid) { reg_fflags := reg_fflags | io.fcsr_flags.bits set_fs_dirty := true.B } io.vector.foreach { vio => when (vio.set_vxsat) { reg_vxsat.get := true.B set_vs_dirty := true.B } } val csr_wen = io.rw.cmd.isOneOf(CSR.S, CSR.C, CSR.W) && !io.rw_stall io.csrw_counter := Mux(coreParams.haveBasicCounters.B && csr_wen && (io.rw.addr.inRange(CSRs.mcycle.U, (CSRs.mcycle + CSR.nCtr).U) || io.rw.addr.inRange(CSRs.mcycleh.U, (CSRs.mcycleh + CSR.nCtr).U)), UIntToOH(io.rw.addr(log2Ceil(CSR.nCtr+nPerfCounters)-1, 0)), 0.U) when (csr_wen) { val scause_mask = ((BigInt(1) << (xLen-1)) + 31).U /* only implement 5 LSBs and MSB */ val satp_valid_modes = 0 +: (minPgLevels to pgLevels).map(new PTBR().pgLevelsToMode(_)) when (decoded_addr(CSRs.mstatus)) { val new_mstatus = wdata.asTypeOf(new MStatus()) reg_mstatus.mie := new_mstatus.mie reg_mstatus.mpie := new_mstatus.mpie if (usingUser) { reg_mstatus.mprv := new_mstatus.mprv reg_mstatus.mpp := legalizePrivilege(new_mstatus.mpp) if (usingSupervisor) { reg_mstatus.spp := new_mstatus.spp reg_mstatus.spie := new_mstatus.spie reg_mstatus.sie := new_mstatus.sie reg_mstatus.tw := new_mstatus.tw reg_mstatus.tsr := new_mstatus.tsr } if (usingVM) { reg_mstatus.mxr := new_mstatus.mxr reg_mstatus.sum := new_mstatus.sum reg_mstatus.tvm := new_mstatus.tvm } if (usingHypervisor) { reg_mstatus.mpv := new_mstatus.mpv reg_mstatus.gva := new_mstatus.gva } } if (usingSupervisor || usingFPU) reg_mstatus.fs := formFS(new_mstatus.fs) reg_mstatus.vs := formVS(new_mstatus.vs) } when (decoded_addr(CSRs.misa)) { val mask = isaStringToMask(isaMaskString).U(xLen.W) val f = wdata('f' - 'a') // suppress write if it would cause the next fetch to be misaligned when (!usingCompressed.B || !io.pc(1) || wdata('c' - 'a')) { if (coreParams.misaWritable) reg_misa := ~(~wdata | (!f << ('d' - 'a'))) & mask | reg_misa & ~mask } } when (decoded_addr(CSRs.mip)) { // MIP should be modified based on the value in reg_mip, not the value // in read_mip, since read_mip.seip is the OR of reg_mip.seip and // io.interrupts.seip. We don't want the value on the PLIC line to // inadvertently be OR'd into read_mip.seip. val new_mip = readModifyWriteCSR(io.rw.cmd, reg_mip.asUInt, io.rw.wdata).asTypeOf(new MIP) if (usingSupervisor) { reg_mip.ssip := new_mip.ssip reg_mip.stip := new_mip.stip reg_mip.seip := new_mip.seip } if (usingHypervisor) { reg_mip.vssip := new_mip.vssip } } when (decoded_addr(CSRs.mie)) { reg_mie := wdata & supported_interrupts } when (decoded_addr(CSRs.mepc)) { reg_mepc := formEPC(wdata) } when (decoded_addr(CSRs.mscratch)) { reg_mscratch := wdata } if (mtvecWritable) when (decoded_addr(CSRs.mtvec)) { reg_mtvec := wdata } when (decoded_addr(CSRs.mcause)) { reg_mcause := wdata & ((BigInt(1) << (xLen-1)) + (BigInt(1) << whichInterrupt.getWidth) - 1).U } when (decoded_addr(CSRs.mtval)) { reg_mtval := wdata } if (usingNMI) { val new_mnstatus = wdata.asTypeOf(new MNStatus()) when (decoded_addr(CustomCSRs.mnscratch)) { reg_mnscratch := wdata } when (decoded_addr(CustomCSRs.mnepc)) { reg_mnepc := formEPC(wdata) } when (decoded_addr(CustomCSRs.mncause)) { reg_mncause := wdata & ((BigInt(1) << (xLen-1)) + BigInt(3)).U } when (decoded_addr(CustomCSRs.mnstatus)) { reg_mnstatus.mpp := legalizePrivilege(new_mnstatus.mpp) reg_mnstatus.mpv := usingHypervisor.B && new_mnstatus.mpv reg_rnmie := reg_rnmie | new_mnstatus.mie // mnie bit settable but not clearable from software } } for (((e, c), i) <- (reg_hpmevent zip reg_hpmcounter).zipWithIndex) { writeCounter(i + CSR.firstMHPC, c, wdata) when (decoded_addr(i + CSR.firstHPE)) { e := perfEventSets.maskEventSelector(wdata) } } if (coreParams.haveBasicCounters) { when (decoded_addr(CSRs.mcountinhibit)) { reg_mcountinhibit := wdata & ~2.U(xLen.W) } // mcountinhibit bit [1] is tied zero writeCounter(CSRs.mcycle, reg_cycle, wdata) writeCounter(CSRs.minstret, reg_instret, wdata) } if (usingFPU) { when (decoded_addr(CSRs.fflags)) { set_fs_dirty := true.B; reg_fflags := wdata } when (decoded_addr(CSRs.frm)) { set_fs_dirty := true.B; reg_frm := wdata } when (decoded_addr(CSRs.fcsr)) { set_fs_dirty := true.B reg_fflags := wdata reg_frm := wdata >> reg_fflags.getWidth } } if (usingDebug) { when (decoded_addr(CSRs.dcsr)) { val new_dcsr = wdata.asTypeOf(new DCSR()) reg_dcsr.step := new_dcsr.step reg_dcsr.ebreakm := new_dcsr.ebreakm if (usingSupervisor) reg_dcsr.ebreaks := new_dcsr.ebreaks if (usingUser) reg_dcsr.ebreaku := new_dcsr.ebreaku if (usingUser) reg_dcsr.prv := legalizePrivilege(new_dcsr.prv) if (usingHypervisor) reg_dcsr.v := new_dcsr.v } when (decoded_addr(CSRs.dpc)) { reg_dpc := formEPC(wdata) } when (decoded_addr(CSRs.dscratch0)) { reg_dscratch0 := wdata } reg_dscratch1.foreach { r => when (decoded_addr(CSRs.dscratch1)) { r := wdata } } } if (usingSupervisor) { when (decoded_addr(CSRs.sstatus)) { val new_sstatus = wdata.asTypeOf(new MStatus()) reg_mstatus.sie := new_sstatus.sie reg_mstatus.spie := new_sstatus.spie reg_mstatus.spp := new_sstatus.spp reg_mstatus.fs := formFS(new_sstatus.fs) reg_mstatus.vs := formVS(new_sstatus.vs) if (usingVM) { reg_mstatus.mxr := new_sstatus.mxr reg_mstatus.sum := new_sstatus.sum } } when (decoded_addr(CSRs.sip)) { val new_sip = ((read_mip & ~read_mideleg) | (wdata & read_mideleg)).asTypeOf(new MIP()) reg_mip.ssip := new_sip.ssip } when (decoded_addr(CSRs.satp)) { if (usingVM) { val new_satp = wdata.asTypeOf(new PTBR()) when (new_satp.mode.isOneOf(satp_valid_modes.map(_.U))) { reg_satp.mode := new_satp.mode & satp_valid_modes.reduce(_|_).U reg_satp.ppn := new_satp.ppn(ppnBits-1,0) if (asIdBits > 0) reg_satp.asid := new_satp.asid(asIdBits-1,0) } } } when (decoded_addr(CSRs.sie)) { reg_mie := (reg_mie & ~sie_mask) | (wdata & sie_mask) } when (decoded_addr(CSRs.sscratch)) { reg_sscratch := wdata } when (decoded_addr(CSRs.sepc)) { reg_sepc := formEPC(wdata) } when (decoded_addr(CSRs.stvec)) { reg_stvec := wdata } when (decoded_addr(CSRs.scause)) { reg_scause := wdata & scause_mask } when (decoded_addr(CSRs.stval)) { reg_stval := wdata } when (decoded_addr(CSRs.mideleg)) { reg_mideleg := wdata } when (decoded_addr(CSRs.medeleg)) { reg_medeleg := wdata } when (decoded_addr(CSRs.scounteren)) { reg_scounteren := wdata } when (decoded_addr(CSRs.senvcfg)) { reg_senvcfg.write(wdata) } } if (usingHypervisor) { when (decoded_addr(CSRs.hstatus)) { val new_hstatus = wdata.asTypeOf(new HStatus()) reg_hstatus.gva := new_hstatus.gva reg_hstatus.spv := new_hstatus.spv reg_hstatus.spvp := new_hstatus.spvp reg_hstatus.hu := new_hstatus.hu reg_hstatus.vtvm := new_hstatus.vtvm reg_hstatus.vtw := new_hstatus.vtw reg_hstatus.vtsr := new_hstatus.vtsr reg_hstatus.vsxl := new_hstatus.vsxl } when (decoded_addr(CSRs.hideleg)) { reg_hideleg := wdata } when (decoded_addr(CSRs.hedeleg)) { reg_hedeleg := wdata } when (decoded_addr(CSRs.hgatp)) { val new_hgatp = wdata.asTypeOf(new PTBR()) val valid_modes = 0 +: (minPgLevels to pgLevels).map(new_hgatp.pgLevelsToMode(_)) when (new_hgatp.mode.isOneOf(valid_modes.map(_.U))) { reg_hgatp.mode := new_hgatp.mode & valid_modes.reduce(_|_).U } reg_hgatp.ppn := Cat(new_hgatp.ppn(ppnBits-1,2), 0.U(2.W)) if (vmIdBits > 0) reg_hgatp.asid := new_hgatp.asid(vmIdBits-1,0) } when (decoded_addr(CSRs.hip)) { val new_hip = ((read_mip & ~hs_delegable_interrupts) | (wdata & hs_delegable_interrupts)).asTypeOf(new MIP()) reg_mip.vssip := new_hip.vssip } when (decoded_addr(CSRs.hie)) { reg_mie := (reg_mie & ~hs_delegable_interrupts) | (wdata & hs_delegable_interrupts) } when (decoded_addr(CSRs.hvip)) { val new_sip = ((read_mip & ~hs_delegable_interrupts) | (wdata & hs_delegable_interrupts)).asTypeOf(new MIP()) reg_mip.vssip := new_sip.vssip reg_mip.vstip := new_sip.vstip reg_mip.vseip := new_sip.vseip } when (decoded_addr(CSRs.hcounteren)) { reg_hcounteren := wdata } when (decoded_addr(CSRs.htval)) { reg_htval := wdata } when (decoded_addr(CSRs.mtval2)) { reg_mtval2 := wdata } val write_mhtinst_read_pseudo = wdata(13) && (xLen == 32).option(true.B).getOrElse(wdata(12)) when(decoded_addr(CSRs.mtinst)) { reg_mtinst_read_pseudo := write_mhtinst_read_pseudo } when(decoded_addr(CSRs.htinst)) { reg_htinst_read_pseudo := write_mhtinst_read_pseudo } when (decoded_addr(CSRs.vsstatus)) { val new_vsstatus = wdata.asTypeOf(new MStatus()) reg_vsstatus.sie := new_vsstatus.sie reg_vsstatus.spie := new_vsstatus.spie reg_vsstatus.spp := new_vsstatus.spp reg_vsstatus.mxr := new_vsstatus.mxr reg_vsstatus.sum := new_vsstatus.sum reg_vsstatus.fs := formFS(new_vsstatus.fs) reg_vsstatus.vs := formVS(new_vsstatus.vs) } when (decoded_addr(CSRs.vsip)) { val new_vsip = ((read_hip & ~read_hideleg) | ((wdata << 1) & read_hideleg)).asTypeOf(new MIP()) reg_mip.vssip := new_vsip.vssip } when (decoded_addr(CSRs.vsatp)) { val new_vsatp = wdata.asTypeOf(new PTBR()) val mode_ok = new_vsatp.mode.isOneOf(satp_valid_modes.map(_.U)) when (mode_ok) { reg_vsatp.mode := new_vsatp.mode & satp_valid_modes.reduce(_|_).U } when (mode_ok || !reg_mstatus.v) { reg_vsatp.ppn := new_vsatp.ppn(vpnBits.min(new_vsatp.ppn.getWidth)-1,0) if (asIdBits > 0) reg_vsatp.asid := new_vsatp.asid(asIdBits-1,0) } } when (decoded_addr(CSRs.vsie)) { reg_mie := (reg_mie & ~read_hideleg) | ((wdata << 1) & read_hideleg) } when (decoded_addr(CSRs.vsscratch)) { reg_vsscratch := wdata } when (decoded_addr(CSRs.vsepc)) { reg_vsepc := formEPC(wdata) } when (decoded_addr(CSRs.vstvec)) { reg_vstvec := wdata } when (decoded_addr(CSRs.vscause)) { reg_vscause := wdata & scause_mask } when (decoded_addr(CSRs.vstval)) { reg_vstval := wdata } when (decoded_addr(CSRs.henvcfg)) { reg_henvcfg.write(wdata) } } if (usingUser) { when (decoded_addr(CSRs.mcounteren)) { reg_mcounteren := wdata } when (decoded_addr(CSRs.menvcfg)) { reg_menvcfg.write(wdata) } } if (nBreakpoints > 0) { when (decoded_addr(CSRs.tselect)) { reg_tselect := wdata } for ((bp, i) <- reg_bp.zipWithIndex) { when (i.U === reg_tselect && (!bp.control.dmode || reg_debug)) { when (decoded_addr(CSRs.tdata2)) { bp.address := wdata } when (decoded_addr(CSRs.tdata3)) { if (coreParams.mcontextWidth > 0) { bp.textra.mselect := wdata(bp.textra.mselectPos) bp.textra.mvalue := wdata >> bp.textra.mvaluePos } if (coreParams.scontextWidth > 0) { bp.textra.sselect := wdata(bp.textra.sselectPos) bp.textra.svalue := wdata >> bp.textra.svaluePos } } when (decoded_addr(CSRs.tdata1)) { bp.control := wdata.asTypeOf(bp.control) val prevChain = if (i == 0) false.B else reg_bp(i-1).control.chain val prevDMode = if (i == 0) false.B else reg_bp(i-1).control.dmode val nextChain = if (i >= nBreakpoints-1) true.B else reg_bp(i+1).control.chain val nextDMode = if (i >= nBreakpoints-1) true.B else reg_bp(i+1).control.dmode val newBPC = readModifyWriteCSR(io.rw.cmd, bp.control.asUInt, io.rw.wdata).asTypeOf(bp.control) val dMode = newBPC.dmode && reg_debug && (prevDMode || !prevChain) bp.control.dmode := dMode when (dMode || (newBPC.action > 1.U)) { bp.control.action := newBPC.action }.otherwise { bp.control.action := 0.U } bp.control.chain := newBPC.chain && !(prevChain || nextChain) && (dMode || !nextDMode) } } } } reg_mcontext.foreach { r => when (decoded_addr(CSRs.mcontext)) { r := wdata }} reg_scontext.foreach { r => when (decoded_addr(CSRs.scontext)) { r := wdata }} if (reg_pmp.nonEmpty) for (((pmp, next), i) <- (reg_pmp zip (reg_pmp.tail :+ reg_pmp.last)).zipWithIndex) { require(xLen % pmp.cfg.getWidth == 0) when (decoded_addr(CSRs.pmpcfg0 + pmpCfgIndex(i)) && !pmp.cfgLocked) { val newCfg = (wdata >> ((i * pmp.cfg.getWidth) % xLen)).asTypeOf(new PMPConfig()) pmp.cfg := newCfg // disallow unreadable but writable PMPs pmp.cfg.w := newCfg.w && newCfg.r // can't select a=NA4 with coarse-grained PMPs if (pmpGranularity.log2 > PMP.lgAlign) pmp.cfg.a := Cat(newCfg.a(1), newCfg.a.orR) } when (decoded_addr(CSRs.pmpaddr0 + i) && !pmp.addrLocked(next)) { pmp.addr := wdata } } def writeCustomCSR(io: CustomCSRIO, csr: CustomCSR, reg: UInt) = { val mask = csr.mask.U(xLen.W) when (decoded_addr(csr.id)) { reg := (wdata & mask) | (reg & ~mask) io.wen := true.B } } for ((io, csr, reg) <- (io.customCSRs, customCSRs, reg_custom).zipped) { writeCustomCSR(io, csr, reg) } for ((io, csr, reg) <- (io.roccCSRs, roccCSRs, reg_rocc).zipped) { writeCustomCSR(io, csr, reg) } if (usingVector) { when (decoded_addr(CSRs.vstart)) { set_vs_dirty := true.B; reg_vstart.get := wdata } when (decoded_addr(CSRs.vxrm)) { set_vs_dirty := true.B; reg_vxrm.get := wdata } when (decoded_addr(CSRs.vxsat)) { set_vs_dirty := true.B; reg_vxsat.get := wdata } when (decoded_addr(CSRs.vcsr)) { set_vs_dirty := true.B reg_vxsat.get := wdata reg_vxrm.get := wdata >> 1 } } } def setCustomCSR(io: CustomCSRIO, csr: CustomCSR, reg: UInt) = { val mask = csr.mask.U(xLen.W) when (io.set) { reg := (io.sdata & mask) | (reg & ~mask) } } for ((io, csr, reg) <- (io.customCSRs, customCSRs, reg_custom).zipped) { setCustomCSR(io, csr, reg) } for ((io, csr, reg) <- (io.roccCSRs, roccCSRs, reg_rocc).zipped) { setCustomCSR(io, csr, reg) } io.vector.map { vio => when (vio.set_vconfig.valid) { // user of CSRFile is responsible for set_vs_dirty in this case assert(vio.set_vconfig.bits.vl <= vio.set_vconfig.bits.vtype.vlMax) reg_vconfig.get := vio.set_vconfig.bits } when (vio.set_vstart.valid) { set_vs_dirty := true.B reg_vstart.get := vio.set_vstart.bits } vio.vstart := reg_vstart.get vio.vconfig := reg_vconfig.get vio.vxrm := reg_vxrm.get when (reset.asBool) { reg_vconfig.get.vl := 0.U reg_vconfig.get.vtype := 0.U.asTypeOf(new VType) reg_vconfig.get.vtype.vill := true.B } } when(reset.asBool) { reg_satp.mode := 0.U reg_vsatp.mode := 0.U reg_hgatp.mode := 0.U } if (!usingVM) { reg_satp.mode := 0.U reg_satp.ppn := 0.U reg_satp.asid := 0.U } if (!usingHypervisor) { reg_vsatp.mode := 0.U reg_vsatp.ppn := 0.U reg_vsatp.asid := 0.U reg_hgatp.mode := 0.U reg_hgatp.ppn := 0.U reg_hgatp.asid := 0.U } if (!(asIdBits > 0)) { reg_satp.asid := 0.U reg_vsatp.asid := 0.U } if (!(vmIdBits > 0)) { reg_hgatp.asid := 0.U } reg_vsstatus.xs := (if (usingRoCC) 3.U else 0.U) if (nBreakpoints <= 1) reg_tselect := 0.U for (bpc <- reg_bp map {_.control}) { bpc.ttype := bpc.tType.U bpc.maskmax := bpc.maskMax.U bpc.reserved := 0.U bpc.zero := 0.U bpc.h := false.B if (!usingSupervisor) bpc.s := false.B if (!usingUser) bpc.u := false.B if (!usingSupervisor && !usingUser) bpc.m := true.B when (reset.asBool) { bpc.action := 0.U bpc.dmode := false.B bpc.chain := false.B bpc.r := false.B bpc.w := false.B bpc.x := false.B } } for (bpx <- reg_bp map {_.textra}) { if (coreParams.mcontextWidth == 0) bpx.mselect := false.B if (coreParams.scontextWidth == 0) bpx.sselect := false.B } for (bp <- reg_bp drop nBreakpoints) bp := 0.U.asTypeOf(new BP()) for (pmp <- reg_pmp) { pmp.cfg.res := 0.U when (reset.asBool) { pmp.reset() } } for (((t, insn), i) <- (io.trace zip io.inst).zipWithIndex) { t.exception := io.retire >= i.U && exception t.valid := io.retire > i.U || t.exception t.insn := insn t.iaddr := io.pc t.priv := Cat(reg_debug, reg_mstatus.prv) t.cause := cause t.interrupt := cause(xLen-1) t.tval := io.tval t.wdata.foreach(_ := DontCare) } def chooseInterrupt(masksIn: Seq[UInt]): (Bool, UInt) = { val nonstandard = supported_interrupts.getWidth-1 to 12 by -1 // MEI, MSI, MTI, SEI, SSI, STI, VSEI, VSSI, VSTI, UEI, USI, UTI val standard = Seq(11, 3, 7, 9, 1, 5, 10, 2, 6, 8, 0, 4) val priority = nonstandard ++ standard val masks = masksIn.reverse val any = masks.flatMap(m => priority.filter(_ < m.getWidth).map(i => m(i))).reduce(_||_) val which = PriorityMux(masks.flatMap(m => priority.filter(_ < m.getWidth).map(i => (m(i), i.U)))) (any, which) } def readModifyWriteCSR(cmd: UInt, rdata: UInt, wdata: UInt) = { (Mux(cmd(1), rdata, 0.U) | wdata) & ~Mux(cmd(1,0).andR, wdata, 0.U) } def legalizePrivilege(priv: UInt): UInt = if (usingSupervisor) Mux(priv === PRV.H.U, PRV.U.U, priv) else if (usingUser) Fill(2, priv(0)) else PRV.M.U def trimPrivilege(priv: UInt): UInt = if (usingSupervisor) priv else legalizePrivilege(priv) def writeCounter(lo: Int, ctr: WideCounter, wdata: UInt) = { if (xLen == 32) { val hi = lo + CSRs.mcycleh - CSRs.mcycle when (decoded_addr(lo)) { ctr := Cat(ctr(ctr.getWidth-1, 32), wdata) } when (decoded_addr(hi)) { ctr := Cat(wdata(ctr.getWidth-33, 0), ctr(31, 0)) } } else { when (decoded_addr(lo)) { ctr := wdata(ctr.getWidth-1, 0) } } } def formEPC(x: UInt) = ~(~x | (if (usingCompressed) 1.U else 3.U)) def readEPC(x: UInt) = ~(~x | Mux(reg_misa('c' - 'a'), 1.U, 3.U)) def formTVec(x: UInt) = x andNot Mux(x(0), ((((BigInt(1) << mtvecInterruptAlign) - 1) << mtvecBaseAlign) | 2).U, 2.U) def isaStringToMask(s: String) = s.map(x => 1 << (x - 'A')).foldLeft(0)(_|_) def formFS(fs: UInt) = if (coreParams.haveFSDirty) fs else Fill(2, fs.orR) def formVS(vs: UInt) = if (usingVector) vs else 0.U }

module CSRFile_1( // @[CSR.scala:377:7] input clock, // @[CSR.scala:377:7] input reset, // @[CSR.scala:377:7] input io_ungated_clock, // @[CSR.scala:384:14] input io_interrupts_debug, // @[CSR.scala:384:14] input io_interrupts_mtip, // @[CSR.scala:384:14] input io_interrupts_msip, // @[CSR.scala:384:14] input io_interrupts_meip, // @[CSR.scala:384:14] input io_interrupts_seip, // @[CSR.scala:384:14] input io_hartid, // @[CSR.scala:384:14] input [11:0] io_rw_addr, // @[CSR.scala:384:14] input [2:0] io_rw_cmd, // @[CSR.scala:384:14] output [63:0] io_rw_rdata, // @[CSR.scala:384:14] input [63:0] io_rw_wdata, // @[CSR.scala:384:14] input [31:0] io_decode_0_inst, // @[CSR.scala:384:14] output io_decode_0_fp_illegal, // @[CSR.scala:384:14] output io_decode_0_fp_csr, // @[CSR.scala:384:14] output io_decode_0_read_illegal, // @[CSR.scala:384:14] output io_decode_0_write_illegal, // @[CSR.scala:384:14] output io_decode_0_write_flush, // @[CSR.scala:384:14] output io_decode_0_system_illegal, // @[CSR.scala:384:14] output io_decode_0_virtual_access_illegal, // @[CSR.scala:384:14] output io_decode_0_virtual_system_illegal, // @[CSR.scala:384:14] output io_csr_stall, // @[CSR.scala:384:14] output io_singleStep, // @[CSR.scala:384:14] output io_status_debug, // @[CSR.scala:384:14] output io_status_cease, // @[CSR.scala:384:14] output io_status_wfi, // @[CSR.scala:384:14] output [1:0] io_status_dprv, // @[CSR.scala:384:14] output io_status_dv, // @[CSR.scala:384:14] output [1:0] io_status_prv, // @[CSR.scala:384:14] output io_status_v, // @[CSR.scala:384:14] output io_status_sd, // @[CSR.scala:384:14] output io_status_mpv, // @[CSR.scala:384:14] output io_status_gva, // @[CSR.scala:384:14] output io_status_tsr, // @[CSR.scala:384:14] output io_status_tw, // @[CSR.scala:384:14] output io_status_tvm, // @[CSR.scala:384:14] output io_status_mxr, // @[CSR.scala:384:14] output io_status_sum, // @[CSR.scala:384:14] output io_status_mprv, // @[CSR.scala:384:14] output [1:0] io_status_fs, // @[CSR.scala:384:14] output [1:0] io_status_mpp, // @[CSR.scala:384:14] output io_status_spp, // @[CSR.scala:384:14] output io_status_mpie, // @[CSR.scala:384:14] output io_status_spie, // @[CSR.scala:384:14] output io_status_mie, // @[CSR.scala:384:14] output io_status_sie, // @[CSR.scala:384:14] output [3:0] io_ptbr_mode, // @[CSR.scala:384:14] output [43:0] io_ptbr_ppn, // @[CSR.scala:384:14] output [39:0] io_evec, // @[CSR.scala:384:14] input io_exception, // @[CSR.scala:384:14] input io_retire, // @[CSR.scala:384:14] input [63:0] io_cause, // @[CSR.scala:384:14] input [39:0] io_pc, // @[CSR.scala:384:14] input [39:0] io_tval, // @[CSR.scala:384:14] output [63:0] io_time, // @[CSR.scala:384:14] output [2:0] io_fcsr_rm, // @[CSR.scala:384:14] input io_fcsr_flags_valid, // @[CSR.scala:384:14] input [4:0] io_fcsr_flags_bits, // @[CSR.scala:384:14] input io_set_fs_dirty, // @[CSR.scala:384:14] output io_interrupt, // @[CSR.scala:384:14] output [63:0] io_interrupt_cause, // @[CSR.scala:384:14] output io_pmp_0_cfg_l, // @[CSR.scala:384:14] output [1:0] io_pmp_0_cfg_a, // @[CSR.scala:384:14] output io_pmp_0_cfg_x, // @[CSR.scala:384:14] output io_pmp_0_cfg_w, // @[CSR.scala:384:14] output io_pmp_0_cfg_r, // @[CSR.scala:384:14] output [29:0] io_pmp_0_addr, // @[CSR.scala:384:14] output [31:0] io_pmp_0_mask, // @[CSR.scala:384:14] output io_pmp_1_cfg_l, // @[CSR.scala:384:14] output [1:0] io_pmp_1_cfg_a, // @[CSR.scala:384:14] output io_pmp_1_cfg_x, // @[CSR.scala:384:14] output io_pmp_1_cfg_w, // @[CSR.scala:384:14] output io_pmp_1_cfg_r, // @[CSR.scala:384:14] output [29:0] io_pmp_1_addr, // @[CSR.scala:384:14] output [31:0] io_pmp_1_mask, // @[CSR.scala:384:14] output io_pmp_2_cfg_l, // @[CSR.scala:384:14] output [1:0] io_pmp_2_cfg_a, // @[CSR.scala:384:14] output io_pmp_2_cfg_x, // @[CSR.scala:384:14] output io_pmp_2_cfg_w, // @[CSR.scala:384:14] output io_pmp_2_cfg_r, // @[CSR.scala:384:14] output [29:0] io_pmp_2_addr, // @[CSR.scala:384:14] output [31:0] io_pmp_2_mask, // @[CSR.scala:384:14] output io_pmp_3_cfg_l, // @[CSR.scala:384:14] output [1:0] io_pmp_3_cfg_a, // @[CSR.scala:384:14] output io_pmp_3_cfg_x, // @[CSR.scala:384:14] output io_pmp_3_cfg_w, // @[CSR.scala:384:14] output io_pmp_3_cfg_r, // @[CSR.scala:384:14] output [29:0] io_pmp_3_addr, // @[CSR.scala:384:14] output [31:0] io_pmp_3_mask, // @[CSR.scala:384:14] output io_pmp_4_cfg_l, // @[CSR.scala:384:14] output [1:0] io_pmp_4_cfg_a, // @[CSR.scala:384:14] output io_pmp_4_cfg_x, // @[CSR.scala:384:14] output io_pmp_4_cfg_w, // @[CSR.scala:384:14] output io_pmp_4_cfg_r, // @[CSR.scala:384:14] output [29:0] io_pmp_4_addr, // @[CSR.scala:384:14] output [31:0] io_pmp_4_mask, // @[CSR.scala:384:14] output io_pmp_5_cfg_l, // @[CSR.scala:384:14] output [1:0] io_pmp_5_cfg_a, // @[CSR.scala:384:14] output io_pmp_5_cfg_x, // @[CSR.scala:384:14] output io_pmp_5_cfg_w, // @[CSR.scala:384:14] output io_pmp_5_cfg_r, // @[CSR.scala:384:14] output [29:0] io_pmp_5_addr, // @[CSR.scala:384:14] output [31:0] io_pmp_5_mask, // @[CSR.scala:384:14] output io_pmp_6_cfg_l, // @[CSR.scala:384:14] output [1:0] io_pmp_6_cfg_a, // @[CSR.scala:384:14] output io_pmp_6_cfg_x, // @[CSR.scala:384:14] output io_pmp_6_cfg_w, // @[CSR.scala:384:14] output io_pmp_6_cfg_r, // @[CSR.scala:384:14] output [29:0] io_pmp_6_addr, // @[CSR.scala:384:14] output [31:0] io_pmp_6_mask, // @[CSR.scala:384:14] output io_pmp_7_cfg_l, // @[CSR.scala:384:14] output [1:0] io_pmp_7_cfg_a, // @[CSR.scala:384:14] output io_pmp_7_cfg_x, // @[CSR.scala:384:14] output io_pmp_7_cfg_w, // @[CSR.scala:384:14] output io_pmp_7_cfg_r, // @[CSR.scala:384:14] output [29:0] io_pmp_7_addr, // @[CSR.scala:384:14] output [31:0] io_pmp_7_mask, // @[CSR.scala:384:14] output [63:0] io_counters_0_eventSel, // @[CSR.scala:384:14] input io_counters_0_inc, // @[CSR.scala:384:14] output [63:0] io_counters_1_eventSel, // @[CSR.scala:384:14] input io_counters_1_inc, // @[CSR.scala:384:14] output io_customCSRs_0_ren, // @[CSR.scala:384:14] output io_customCSRs_0_wen, // @[CSR.scala:384:14] output [63:0] io_customCSRs_0_wdata, // @[CSR.scala:384:14] output [63:0] io_customCSRs_0_value, // @[CSR.scala:384:14] output io_customCSRs_1_ren, // @[CSR.scala:384:14] output io_customCSRs_1_wen, // @[CSR.scala:384:14] output [63:0] io_customCSRs_1_wdata, // @[CSR.scala:384:14] output [63:0] io_customCSRs_1_value // @[CSR.scala:384:14] ); wire io_status_sie_0; // @[CSR.scala:377:7] wire io_status_spie_0; // @[CSR.scala:377:7] wire io_status_spp_0; // @[CSR.scala:377:7] wire [1:0] io_status_fs_0; // @[CSR.scala:377:7] wire io_status_sum_0; // @[CSR.scala:377:7] wire io_status_mxr_0; // @[CSR.scala:377:7] wire io_status_sd_0; // @[CSR.scala:377:7] wire io_ungated_clock_0 = io_ungated_clock; // @[CSR.scala:377:7] wire io_interrupts_debug_0 = io_interrupts_debug; // @[CSR.scala:377:7] wire io_interrupts_mtip_0 = io_interrupts_mtip; // @[CSR.scala:377:7] wire io_interrupts_msip_0 = io_interrupts_msip; // @[CSR.scala:377:7] wire io_interrupts_meip_0 = io_interrupts_meip; // @[CSR.scala:377:7] wire io_interrupts_seip_0 = io_interrupts_seip; // @[CSR.scala:377:7] wire io_hartid_0 = io_hartid; // @[CSR.scala:377:7] wire [11:0] io_rw_addr_0 = io_rw_addr; // @[CSR.scala:377:7] wire [2:0] io_rw_cmd_0 = io_rw_cmd; // @[CSR.scala:377:7] wire [63:0] io_rw_wdata_0 = io_rw_wdata; // @[CSR.scala:377:7] wire [31:0] io_decode_0_inst_0 = io_decode_0_inst; // @[CSR.scala:377:7] wire io_exception_0 = io_exception; // @[CSR.scala:377:7] wire io_retire_0 = io_retire; // @[CSR.scala:377:7] wire [63:0] io_cause_0 = io_cause; // @[CSR.scala:377:7] wire [39:0] io_pc_0 = io_pc; // @[CSR.scala:377:7] wire [39:0] io_tval_0 = io_tval; // @[CSR.scala:377:7] wire io_fcsr_flags_valid_0 = io_fcsr_flags_valid; // @[CSR.scala:377:7] wire [4:0] io_fcsr_flags_bits_0 = io_fcsr_flags_bits; // @[CSR.scala:377:7] wire io_set_fs_dirty_0 = io_set_fs_dirty; // @[CSR.scala:377:7] wire io_counters_0_inc_0 = io_counters_0_inc; // @[CSR.scala:377:7] wire io_counters_1_inc_0 = io_counters_1_inc; // @[CSR.scala:377:7] wire io_decode_0_vector_illegal = 1'h1; // @[CSR.scala:377:7] wire io_decode_0_rocc_illegal = 1'h1; // @[CSR.scala:377:7] wire io_gstatus_sd = 1'h1; // @[CSR.scala:377:7] wire sup_meip = 1'h1; // @[CSR.scala:406:19] wire sup_seip = 1'h1; // @[CSR.scala:406:19] wire sup_mtip = 1'h1; // @[CSR.scala:406:19] wire sup_stip = 1'h1; // @[CSR.scala:406:19] wire sup_msip = 1'h1; // @[CSR.scala:406:19] wire sup_ssip = 1'h1; // @[CSR.scala:406:19] wire del_seip = 1'h1; // @[CSR.scala:426:26] wire del_stip = 1'h1; // @[CSR.scala:426:26] wire del_ssip = 1'h1; // @[CSR.scala:426:26] wire _read_mapping_T_3 = 1'h1; // @[CSR.scala:1665:45] wire _debug_csrs_T_1 = 1'h1; // @[CSR.scala:1665:45] wire read_mnstatus_mie = 1'h1; // @[CSR.scala:675:31] wire sie_mask_sgeip_mask_sgeip = 1'h1; // @[CSR.scala:748:30] wire _allow_wfi_T_4 = 1'h1; // @[CSR.scala:906:112] wire _allow_wfi_T_5 = 1'h1; // @[CSR.scala:906:109] wire allow_hfence_vvma = 1'h1; // @[CSR.scala:908:50] wire allow_hlsv = 1'h1; // @[CSR.scala:909:43] wire _allow_counter_T_11 = 1'h1; // @[CSR.scala:914:8] wire _allow_counter_T_13 = 1'h1; // @[CSR.scala:914:27] wire _allow_counter_T_16 = 1'h1; // @[CSR.scala:914:45] wire _io_decode_0_fp_illegal_T_4 = 1'h1; // @[CSR.scala:915:103] wire _io_decode_0_vector_illegal_T = 1'h1; // @[CSR.scala:916:43] wire _io_decode_0_vector_illegal_T_1 = 1'h1; // @[CSR.scala:916:87] wire _io_decode_0_vector_illegal_T_3 = 1'h1; // @[CSR.scala:916:51] wire _io_decode_0_vector_illegal_T_5 = 1'h1; // @[CSR.scala:916:98] wire _io_decode_0_vector_illegal_T_6 = 1'h1; // @[CSR.scala:916:95] wire _io_decode_0_rocc_illegal_T = 1'h1; // @[CSR.scala:919:41] wire _io_decode_0_rocc_illegal_T_1 = 1'h1; // @[CSR.scala:919:85] wire _io_decode_0_rocc_illegal_T_3 = 1'h1; // @[CSR.scala:919:49] wire _io_decode_0_rocc_illegal_T_5 = 1'h1; // @[CSR.scala:919:96] wire _io_decode_0_rocc_illegal_T_6 = 1'h1; // @[CSR.scala:919:93] wire _io_gstatus_sd_T = 1'h1; // @[CSR.scala:1016:34] wire _io_gstatus_sd_T_2 = 1'h1; // @[CSR.scala:1016:39] wire _io_gstatus_sd_T_4 = 1'h1; // @[CSR.scala:1016:61] wire _en_T_7 = 1'h1; // @[CSR.scala:1096:71] wire delegable_1 = 1'h1; // @[CSR.scala:1097:65] wire _en_T_19 = 1'h1; // @[CSR.scala:1096:71] wire _en_T_31 = 1'h1; // @[CSR.scala:1096:71] wire delegable_5 = 1'h1; // @[CSR.scala:1097:65] wire _en_T_43 = 1'h1; // @[CSR.scala:1096:71] wire _en_T_55 = 1'h1; // @[CSR.scala:1096:71] wire delegable_9 = 1'h1; // @[CSR.scala:1097:65] wire _en_T_67 = 1'h1; // @[CSR.scala:1096:71] wire delegable_17 = 1'h1; // @[CSR.scala:1109:67] wire delegable_18 = 1'h1; // @[CSR.scala:1109:67] wire delegable_19 = 1'h1; // @[CSR.scala:1109:67] wire delegable_21 = 1'h1; // @[CSR.scala:1109:67] wire delegable_23 = 1'h1; // @[CSR.scala:1109:67] wire delegable_26 = 1'h1; // @[CSR.scala:1109:67] wire delegable_27 = 1'h1; // @[CSR.scala:1109:67] wire delegable_28 = 1'h1; // @[CSR.scala:1109:67] wire _io_evec_T_1 = 1'h1; // @[CSR.scala:1665:45] wire _io_evec_T_6 = 1'h1; // @[CSR.scala:1665:45] wire _io_evec_T_11 = 1'h1; // @[CSR.scala:1665:45] wire _io_evec_T_16 = 1'h1; // @[CSR.scala:1665:45] wire _io_evec_T_21 = 1'h1; // @[CSR.scala:1665:45] wire _csr_wen_T_5 = 1'h1; // @[CSR.scala:1222:59] wire _io_trace_0_exception_T = 1'h1; // @[CSR.scala:1620:30] wire [31:0] io_status_isa = 32'h14112D; // @[CSR.scala:377:7] wire [22:0] io_status_zero2 = 23'h0; // @[CSR.scala:377:7] wire [22:0] io_gstatus_zero2 = 23'h0; // @[CSR.scala:377:7] wire [22:0] _reset_mstatus_WIRE_zero2 = 23'h0; // @[CSR.scala:391:47] wire [22:0] reset_mstatus_zero2 = 23'h0; // @[CSR.scala:391:34] wire [22:0] _read_sstatus_WIRE_zero2 = 23'h0; // @[CSR.scala:755:48] wire [22:0] read_sstatus_zero2 = 23'h0; // @[CSR.scala:755:35] wire io_decode_0_vector_csr = 1'h0; // @[CSR.scala:377:7] wire io_rw_stall = 1'h0; // @[CSR.scala:377:7] wire io_status_mbe = 1'h0; // @[CSR.scala:377:7] wire io_status_sbe = 1'h0; // @[CSR.scala:377:7] wire io_status_sd_rv32 = 1'h0; // @[CSR.scala:377:7] wire io_status_ube = 1'h0; // @[CSR.scala:377:7] wire io_status_upie = 1'h0; // @[CSR.scala:377:7] wire io_status_hie = 1'h0; // @[CSR.scala:377:7] wire io_status_uie = 1'h0; // @[CSR.scala:377:7] wire io_hstatus_vtsr = 1'h0; // @[CSR.scala:377:7] wire io_hstatus_vtw = 1'h0; // @[CSR.scala:377:7] wire io_hstatus_vtvm = 1'h0; // @[CSR.scala:377:7] wire io_hstatus_hu = 1'h0; // @[CSR.scala:377:7] wire io_hstatus_vsbe = 1'h0; // @[CSR.scala:377:7] wire io_gstatus_debug = 1'h0; // @[CSR.scala:377:7] wire io_gstatus_cease = 1'h0; // @[CSR.scala:377:7] wire io_gstatus_wfi = 1'h0; // @[CSR.scala:377:7] wire io_gstatus_dv = 1'h0; // @[CSR.scala:377:7] wire io_gstatus_v = 1'h0; // @[CSR.scala:377:7] wire io_gstatus_mpv = 1'h0; // @[CSR.scala:377:7] wire io_gstatus_gva = 1'h0; // @[CSR.scala:377:7] wire io_gstatus_mbe = 1'h0; // @[CSR.scala:377:7] wire io_gstatus_sbe = 1'h0; // @[CSR.scala:377:7] wire io_gstatus_sd_rv32 = 1'h0; // @[CSR.scala:377:7] wire io_gstatus_tsr = 1'h0; // @[CSR.scala:377:7] wire io_gstatus_tw = 1'h0; // @[CSR.scala:377:7] wire io_gstatus_tvm = 1'h0; // @[CSR.scala:377:7] wire io_gstatus_mxr = 1'h0; // @[CSR.scala:377:7] wire io_gstatus_sum = 1'h0; // @[CSR.scala:377:7] wire io_gstatus_mprv = 1'h0; // @[CSR.scala:377:7] wire io_gstatus_mpie = 1'h0; // @[CSR.scala:377:7] wire io_gstatus_ube = 1'h0; // @[CSR.scala:377:7] wire io_gstatus_upie = 1'h0; // @[CSR.scala:377:7] wire io_gstatus_mie = 1'h0; // @[CSR.scala:377:7] wire io_gstatus_hie = 1'h0; // @[CSR.scala:377:7] wire io_gstatus_uie = 1'h0; // @[CSR.scala:377:7] wire io_mhtinst_read_pseudo = 1'h0; // @[CSR.scala:377:7] wire io_gva = 1'h0; // @[CSR.scala:377:7] wire io_rocc_interrupt = 1'h0; // @[CSR.scala:377:7] wire io_customCSRs_0_stall = 1'h0; // @[CSR.scala:377:7] wire io_customCSRs_0_set = 1'h0; // @[CSR.scala:377:7] wire io_customCSRs_1_stall = 1'h0; // @[CSR.scala:377:7] wire io_customCSRs_1_set = 1'h0; // @[CSR.scala:377:7] wire _reset_mstatus_WIRE_debug = 1'h0; // @[CSR.scala:391:47] wire _reset_mstatus_WIRE_cease = 1'h0; // @[CSR.scala:391:47] wire _reset_mstatus_WIRE_wfi = 1'h0; // @[CSR.scala:391:47] wire _reset_mstatus_WIRE_dv = 1'h0; // @[CSR.scala:391:47] wire _reset_mstatus_WIRE_v = 1'h0; // @[CSR.scala:391:47] wire _reset_mstatus_WIRE_sd = 1'h0; // @[CSR.scala:391:47] wire _reset_mstatus_WIRE_mpv = 1'h0; // @[CSR.scala:391:47] wire _reset_mstatus_WIRE_gva = 1'h0; // @[CSR.scala:391:47] wire _reset_mstatus_WIRE_mbe = 1'h0; // @[CSR.scala:391:47] wire _reset_mstatus_WIRE_sbe = 1'h0; // @[CSR.scala:391:47] wire _reset_mstatus_WIRE_sd_rv32 = 1'h0; // @[CSR.scala:391:47] wire _reset_mstatus_WIRE_tsr = 1'h0; // @[CSR.scala:391:47] wire _reset_mstatus_WIRE_tw = 1'h0; // @[CSR.scala:391:47] wire _reset_mstatus_WIRE_tvm = 1'h0; // @[CSR.scala:391:47] wire _reset_mstatus_WIRE_mxr = 1'h0; // @[CSR.scala:391:47] wire _reset_mstatus_WIRE_sum = 1'h0; // @[CSR.scala:391:47] wire _reset_mstatus_WIRE_mprv = 1'h0; // @[CSR.scala:391:47] wire _reset_mstatus_WIRE_spp = 1'h0; // @[CSR.scala:391:47] wire _reset_mstatus_WIRE_mpie = 1'h0; // @[CSR.scala:391:47] wire _reset_mstatus_WIRE_ube = 1'h0; // @[CSR.scala:391:47] wire _reset_mstatus_WIRE_spie = 1'h0; // @[CSR.scala:391:47] wire _reset_mstatus_WIRE_upie = 1'h0; // @[CSR.scala:391:47] wire _reset_mstatus_WIRE_mie = 1'h0; // @[CSR.scala:391:47] wire _reset_mstatus_WIRE_hie = 1'h0; // @[CSR.scala:391:47] wire _reset_mstatus_WIRE_sie = 1'h0; // @[CSR.scala:391:47] wire _reset_mstatus_WIRE_uie = 1'h0; // @[CSR.scala:391:47] wire reset_mstatus_debug = 1'h0; // @[CSR.scala:391:34] wire reset_mstatus_cease = 1'h0; // @[CSR.scala:391:34] wire reset_mstatus_wfi = 1'h0; // @[CSR.scala:391:34] wire reset_mstatus_dv = 1'h0; // @[CSR.scala:391:34] wire reset_mstatus_v = 1'h0; // @[CSR.scala:391:34] wire reset_mstatus_sd = 1'h0; // @[CSR.scala:391:34] wire reset_mstatus_mpv = 1'h0; // @[CSR.scala:391:34] wire reset_mstatus_gva = 1'h0; // @[CSR.scala:391:34] wire reset_mstatus_mbe = 1'h0; // @[CSR.scala:391:34] wire reset_mstatus_sbe = 1'h0; // @[CSR.scala:391:34] wire reset_mstatus_sd_rv32 = 1'h0; // @[CSR.scala:391:34] wire reset_mstatus_tsr = 1'h0; // @[CSR.scala:391:34] wire reset_mstatus_tw = 1'h0; // @[CSR.scala:391:34] wire reset_mstatus_tvm = 1'h0; // @[CSR.scala:391:34] wire reset_mstatus_mxr = 1'h0; // @[CSR.scala:391:34] wire reset_mstatus_sum = 1'h0; // @[CSR.scala:391:34] wire reset_mstatus_mprv = 1'h0; // @[CSR.scala:391:34] wire reset_mstatus_spp = 1'h0; // @[CSR.scala:391:34] wire reset_mstatus_mpie = 1'h0; // @[CSR.scala:391:34] wire reset_mstatus_ube = 1'h0; // @[CSR.scala:391:34] wire reset_mstatus_spie = 1'h0; // @[CSR.scala:391:34] wire reset_mstatus_upie = 1'h0; // @[CSR.scala:391:34] wire reset_mstatus_mie = 1'h0; // @[CSR.scala:391:34] wire reset_mstatus_hie = 1'h0; // @[CSR.scala:391:34] wire reset_mstatus_sie = 1'h0; // @[CSR.scala:391:34] wire reset_mstatus_uie = 1'h0; // @[CSR.scala:391:34] wire _reset_dcsr_WIRE_ebreakm = 1'h0; // @[CSR.scala:400:44] wire _reset_dcsr_WIRE_ebreakh = 1'h0; // @[CSR.scala:400:44] wire _reset_dcsr_WIRE_ebreaks = 1'h0; // @[CSR.scala:400:44] wire _reset_dcsr_WIRE_ebreaku = 1'h0; // @[CSR.scala:400:44] wire _reset_dcsr_WIRE_zero2 = 1'h0; // @[CSR.scala:400:44] wire _reset_dcsr_WIRE_stopcycle = 1'h0; // @[CSR.scala:400:44] wire _reset_dcsr_WIRE_stoptime = 1'h0; // @[CSR.scala:400:44] wire _reset_dcsr_WIRE_v = 1'h0; // @[CSR.scala:400:44] wire _reset_dcsr_WIRE_step = 1'h0; // @[CSR.scala:400:44] wire reset_dcsr_ebreakm = 1'h0; // @[CSR.scala:400:31] wire reset_dcsr_ebreakh = 1'h0; // @[CSR.scala:400:31] wire reset_dcsr_ebreaks = 1'h0; // @[CSR.scala:400:31] wire reset_dcsr_ebreaku = 1'h0; // @[CSR.scala:400:31] wire reset_dcsr_zero2 = 1'h0; // @[CSR.scala:400:31] wire reset_dcsr_stopcycle = 1'h0; // @[CSR.scala:400:31] wire reset_dcsr_stoptime = 1'h0; // @[CSR.scala:400:31] wire reset_dcsr_v = 1'h0; // @[CSR.scala:400:31] wire reset_dcsr_step = 1'h0; // @[CSR.scala:400:31] wire sup_zero1 = 1'h0; // @[CSR.scala:406:19] wire sup_debug = 1'h0; // @[CSR.scala:406:19] wire sup_rocc = 1'h0; // @[CSR.scala:406:19] wire sup_sgeip = 1'h0; // @[CSR.scala:406:19] wire sup_vseip = 1'h0; // @[CSR.scala:406:19] wire sup_ueip = 1'h0; // @[CSR.scala:406:19] wire sup_vstip = 1'h0; // @[CSR.scala:406:19] wire sup_utip = 1'h0; // @[CSR.scala:406:19] wire sup_vssip = 1'h0; // @[CSR.scala:406:19] wire sup_usip = 1'h0; // @[CSR.scala:406:19] wire del_zero1 = 1'h0; // @[CSR.scala:426:26] wire del_debug = 1'h0; // @[CSR.scala:426:26] wire del_rocc = 1'h0; // @[CSR.scala:426:26] wire del_sgeip = 1'h0; // @[CSR.scala:426:26] wire del_meip = 1'h0; // @[CSR.scala:426:26] wire del_vseip = 1'h0; // @[CSR.scala:426:26] wire del_ueip = 1'h0; // @[CSR.scala:426:26] wire del_mtip = 1'h0; // @[CSR.scala:426:26] wire del_vstip = 1'h0; // @[CSR.scala:426:26] wire del_utip = 1'h0; // @[CSR.scala:426:26] wire del_msip = 1'h0; // @[CSR.scala:426:26] wire del_vssip = 1'h0; // @[CSR.scala:426:26] wire del_usip = 1'h0; // @[CSR.scala:426:26] wire hi_hi_hi_hi = 1'h0; // @[CSR.scala:431:10] wire hi_hi_hi_hi_1 = 1'h0; // @[CSR.scala:431:50] wire _always_WIRE_zero1 = 1'h0; // @[CSR.scala:471:42] wire _always_WIRE_debug = 1'h0; // @[CSR.scala:471:42] wire _always_WIRE_rocc = 1'h0; // @[CSR.scala:471:42] wire _always_WIRE_sgeip = 1'h0; // @[CSR.scala:471:42] wire _always_WIRE_meip = 1'h0; // @[CSR.scala:471:42] wire _always_WIRE_vseip = 1'h0; // @[CSR.scala:471:42] wire _always_WIRE_seip = 1'h0; // @[CSR.scala:471:42] wire _always_WIRE_ueip = 1'h0; // @[CSR.scala:471:42] wire _always_WIRE_mtip = 1'h0; // @[CSR.scala:471:42] wire _always_WIRE_vstip = 1'h0; // @[CSR.scala:471:42] wire _always_WIRE_stip = 1'h0; // @[CSR.scala:471:42] wire _always_WIRE_utip = 1'h0; // @[CSR.scala:471:42] wire _always_WIRE_msip = 1'h0; // @[CSR.scala:471:42] wire _always_WIRE_vssip = 1'h0; // @[CSR.scala:471:42] wire _always_WIRE_ssip = 1'h0; // @[CSR.scala:471:42] wire _always_WIRE_usip = 1'h0; // @[CSR.scala:471:42] wire always_zero1 = 1'h0; // @[CSR.scala:471:29] wire always_debug = 1'h0; // @[CSR.scala:471:29] wire always_rocc = 1'h0; // @[CSR.scala:471:29] wire always_sgeip = 1'h0; // @[CSR.scala:471:29] wire always_meip = 1'h0; // @[CSR.scala:471:29] wire always_vseip = 1'h0; // @[CSR.scala:471:29] wire always_seip = 1'h0; // @[CSR.scala:471:29] wire always_ueip = 1'h0; // @[CSR.scala:471:29] wire always_mtip = 1'h0; // @[CSR.scala:471:29] wire always_vstip = 1'h0; // @[CSR.scala:471:29] wire always_stip = 1'h0; // @[CSR.scala:471:29] wire always_utip = 1'h0; // @[CSR.scala:471:29] wire always_msip = 1'h0; // @[CSR.scala:471:29] wire always_vssip = 1'h0; // @[CSR.scala:471:29] wire always_ssip = 1'h0; // @[CSR.scala:471:29] wire always_usip = 1'h0; // @[CSR.scala:471:29] wire deleg_zero1 = 1'h0; // @[CSR.scala:476:28] wire deleg_debug = 1'h0; // @[CSR.scala:476:28] wire deleg_rocc = 1'h0; // @[CSR.scala:476:28] wire deleg_sgeip = 1'h0; // @[CSR.scala:476:28] wire deleg_meip = 1'h0; // @[CSR.scala:476:28] wire deleg_vseip = 1'h0; // @[CSR.scala:476:28] wire deleg_seip = 1'h0; // @[CSR.scala:476:28] wire deleg_ueip = 1'h0; // @[CSR.scala:476:28] wire deleg_mtip = 1'h0; // @[CSR.scala:476:28] wire deleg_vstip = 1'h0; // @[CSR.scala:476:28] wire deleg_stip = 1'h0; // @[CSR.scala:476:28] wire deleg_utip = 1'h0; // @[CSR.scala:476:28] wire deleg_msip = 1'h0; // @[CSR.scala:476:28] wire deleg_vssip = 1'h0; // @[CSR.scala:476:28] wire deleg_ssip = 1'h0; // @[CSR.scala:476:28] wire deleg_usip = 1'h0; // @[CSR.scala:476:28] wire hi_hi_hi_hi_2 = 1'h0; // @[CSR.scala:479:12] wire hi_hi_hi_hi_3 = 1'h0; // @[CSR.scala:479:27] wire _reset_mnstatus_WIRE_mpv = 1'h0; // @[CSR.scala:516:48] wire _reset_mnstatus_WIRE_mie = 1'h0; // @[CSR.scala:516:48] wire reset_mnstatus_mpv = 1'h0; // @[CSR.scala:516:35] wire reset_mnstatus_mie = 1'h0; // @[CSR.scala:516:35] wire _reg_menvcfg_WIRE_stce = 1'h0; // @[CSR.scala:525:41] wire _reg_menvcfg_WIRE_pbmte = 1'h0; // @[CSR.scala:525:41] wire _reg_menvcfg_WIRE_cbze = 1'h0; // @[CSR.scala:525:41] wire _reg_menvcfg_WIRE_cbcfe = 1'h0; // @[CSR.scala:525:41] wire _reg_menvcfg_WIRE_fiom = 1'h0; // @[CSR.scala:525:41] wire _reg_senvcfg_WIRE_stce = 1'h0; // @[CSR.scala:526:41] wire _reg_senvcfg_WIRE_pbmte = 1'h0; // @[CSR.scala:526:41] wire _reg_senvcfg_WIRE_cbze = 1'h0; // @[CSR.scala:526:41] wire _reg_senvcfg_WIRE_cbcfe = 1'h0; // @[CSR.scala:526:41] wire _reg_senvcfg_WIRE_fiom = 1'h0; // @[CSR.scala:526:41] wire _reg_henvcfg_WIRE_stce = 1'h0; // @[CSR.scala:527:41] wire _reg_henvcfg_WIRE_pbmte = 1'h0; // @[CSR.scala:527:41] wire _reg_henvcfg_WIRE_cbze = 1'h0; // @[CSR.scala:527:41] wire _reg_henvcfg_WIRE_cbcfe = 1'h0; // @[CSR.scala:527:41] wire _reg_henvcfg_WIRE_fiom = 1'h0; // @[CSR.scala:527:41] wire _reg_hstatus_WIRE_vtsr = 1'h0; // @[CSR.scala:552:41] wire _reg_hstatus_WIRE_vtw = 1'h0; // @[CSR.scala:552:41] wire _reg_hstatus_WIRE_vtvm = 1'h0; // @[CSR.scala:552:41] wire _reg_hstatus_WIRE_hu = 1'h0; // @[CSR.scala:552:41] wire _reg_hstatus_WIRE_spvp = 1'h0; // @[CSR.scala:552:41] wire _reg_hstatus_WIRE_spv = 1'h0; // @[CSR.scala:552:41] wire _reg_hstatus_WIRE_gva = 1'h0; // @[CSR.scala:552:41] wire _reg_hstatus_WIRE_vsbe = 1'h0; // @[CSR.scala:552:41] wire read_hvip_hi_hi_hi_hi = 1'h0; // @[CSR.scala:555:27] wire mip_zero1 = 1'h0; // @[CSR.scala:600:24] wire mip_debug = 1'h0; // @[CSR.scala:600:24] wire mip_rocc = 1'h0; // @[CSR.scala:600:24] wire mip_sgeip = 1'h0; // @[CSR.scala:600:24] wire mip_vseip = 1'h0; // @[CSR.scala:600:24] wire mip_ueip = 1'h0; // @[CSR.scala:600:24] wire mip_vstip = 1'h0; // @[CSR.scala:600:24] wire mip_utip = 1'h0; // @[CSR.scala:600:24] wire mip_vssip = 1'h0; // @[CSR.scala:600:24] wire mip_usip = 1'h0; // @[CSR.scala:600:24] wire _any_T_47 = 1'h0; // @[CSR.scala:1637:76] wire _any_T_48 = 1'h0; // @[CSR.scala:1637:76] wire _any_T_49 = 1'h0; // @[CSR.scala:1637:76] wire _any_T_50 = 1'h0; // @[CSR.scala:1637:76] wire _any_T_51 = 1'h0; // @[CSR.scala:1637:76] wire _any_T_52 = 1'h0; // @[CSR.scala:1637:76] wire _any_T_53 = 1'h0; // @[CSR.scala:1637:76] wire _any_T_54 = 1'h0; // @[CSR.scala:1637:76] wire _any_T_55 = 1'h0; // @[CSR.scala:1637:76] wire _any_T_56 = 1'h0; // @[CSR.scala:1637:76] wire _any_T_57 = 1'h0; // @[CSR.scala:1637:76] wire _any_T_58 = 1'h0; // @[CSR.scala:1637:76] wire _any_T_59 = 1'h0; // @[CSR.scala:1637:76] wire _any_T_60 = 1'h0; // @[CSR.scala:1637:76] wire _any_T_61 = 1'h0; // @[CSR.scala:1637:76] wire _any_T_62 = 1'h0; // @[CSR.scala:1637:76] wire _which_T_47 = 1'h0; // @[CSR.scala:1638:91] wire _which_T_48 = 1'h0; // @[CSR.scala:1638:91] wire _which_T_49 = 1'h0; // @[CSR.scala:1638:91] wire _which_T_50 = 1'h0; // @[CSR.scala:1638:91] wire _which_T_51 = 1'h0; // @[CSR.scala:1638:91] wire _which_T_52 = 1'h0; // @[CSR.scala:1638:91] wire _which_T_53 = 1'h0; // @[CSR.scala:1638:91] wire _which_T_54 = 1'h0; // @[CSR.scala:1638:91] wire _which_T_55 = 1'h0; // @[CSR.scala:1638:91] wire _which_T_56 = 1'h0; // @[CSR.scala:1638:91] wire _which_T_57 = 1'h0; // @[CSR.scala:1638:91] wire _which_T_58 = 1'h0; // @[CSR.scala:1638:91] wire _which_T_59 = 1'h0; // @[CSR.scala:1638:91] wire _which_T_60 = 1'h0; // @[CSR.scala:1638:91] wire _which_T_61 = 1'h0; // @[CSR.scala:1638:91] wire _which_T_62 = 1'h0; // @[CSR.scala:1638:91] wire _io_fiom_T_5 = 1'h0; // @[CSR.scala:631:131] wire _pmp_mask_base_T_2 = 1'h0; // @[PMP.scala:57:62] wire _pmp_mask_base_T_5 = 1'h0; // @[PMP.scala:57:62] wire _pmp_mask_base_T_8 = 1'h0; // @[PMP.scala:57:62] wire _pmp_mask_base_T_11 = 1'h0; // @[PMP.scala:57:62] wire _pmp_mask_base_T_14 = 1'h0; // @[PMP.scala:57:62] wire _pmp_mask_base_T_17 = 1'h0; // @[PMP.scala:57:62] wire _pmp_mask_base_T_20 = 1'h0; // @[PMP.scala:57:62] wire _pmp_mask_base_T_23 = 1'h0; // @[PMP.scala:57:62] wire _read_mapping_T = 1'h0; // @[package.scala:132:38] wire read_mapping_lo_hi_1 = 1'h0; // @[CSR.scala:657:47] wire read_mapping_hi_hi_1 = 1'h0; // @[CSR.scala:657:47] wire _read_mnstatus_WIRE_mpv = 1'h0; // @[CSR.scala:675:44] wire _read_mnstatus_WIRE_mie = 1'h0; // @[CSR.scala:675:44] wire read_mnstatus_mpv = 1'h0; // @[CSR.scala:675:31] wire _sie_mask_sgeip_mask_WIRE_zero1 = 1'h0; // @[CSR.scala:748:43] wire _sie_mask_sgeip_mask_WIRE_debug = 1'h0; // @[CSR.scala:748:43] wire _sie_mask_sgeip_mask_WIRE_rocc = 1'h0; // @[CSR.scala:748:43] wire _sie_mask_sgeip_mask_WIRE_sgeip = 1'h0; // @[CSR.scala:748:43] wire _sie_mask_sgeip_mask_WIRE_meip = 1'h0; // @[CSR.scala:748:43] wire _sie_mask_sgeip_mask_WIRE_vseip = 1'h0; // @[CSR.scala:748:43] wire _sie_mask_sgeip_mask_WIRE_seip = 1'h0; // @[CSR.scala:748:43] wire _sie_mask_sgeip_mask_WIRE_ueip = 1'h0; // @[CSR.scala:748:43] wire _sie_mask_sgeip_mask_WIRE_mtip = 1'h0; // @[CSR.scala:748:43] wire _sie_mask_sgeip_mask_WIRE_vstip = 1'h0; // @[CSR.scala:748:43] wire _sie_mask_sgeip_mask_WIRE_stip = 1'h0; // @[CSR.scala:748:43] wire _sie_mask_sgeip_mask_WIRE_utip = 1'h0; // @[CSR.scala:748:43] wire _sie_mask_sgeip_mask_WIRE_msip = 1'h0; // @[CSR.scala:748:43] wire _sie_mask_sgeip_mask_WIRE_vssip = 1'h0; // @[CSR.scala:748:43] wire _sie_mask_sgeip_mask_WIRE_ssip = 1'h0; // @[CSR.scala:748:43] wire _sie_mask_sgeip_mask_WIRE_usip = 1'h0; // @[CSR.scala:748:43] wire sie_mask_sgeip_mask_zero1 = 1'h0; // @[CSR.scala:748:30] wire sie_mask_sgeip_mask_debug = 1'h0; // @[CSR.scala:748:30] wire sie_mask_sgeip_mask_rocc = 1'h0; // @[CSR.scala:748:30] wire sie_mask_sgeip_mask_meip = 1'h0; // @[CSR.scala:748:30] wire sie_mask_sgeip_mask_vseip = 1'h0; // @[CSR.scala:748:30] wire sie_mask_sgeip_mask_seip = 1'h0; // @[CSR.scala:748:30] wire sie_mask_sgeip_mask_ueip = 1'h0; // @[CSR.scala:748:30] wire sie_mask_sgeip_mask_mtip = 1'h0; // @[CSR.scala:748:30] wire sie_mask_sgeip_mask_vstip = 1'h0; // @[CSR.scala:748:30] wire sie_mask_sgeip_mask_stip = 1'h0; // @[CSR.scala:748:30] wire sie_mask_sgeip_mask_utip = 1'h0; // @[CSR.scala:748:30] wire sie_mask_sgeip_mask_msip = 1'h0; // @[CSR.scala:748:30] wire sie_mask_sgeip_mask_vssip = 1'h0; // @[CSR.scala:748:30] wire sie_mask_sgeip_mask_ssip = 1'h0; // @[CSR.scala:748:30] wire sie_mask_sgeip_mask_usip = 1'h0; // @[CSR.scala:748:30] wire sie_mask_hi_hi_hi_hi = 1'h0; // @[CSR.scala:750:59] wire _read_sstatus_WIRE_debug = 1'h0; // @[CSR.scala:755:48] wire _read_sstatus_WIRE_cease = 1'h0; // @[CSR.scala:755:48] wire _read_sstatus_WIRE_wfi = 1'h0; // @[CSR.scala:755:48] wire _read_sstatus_WIRE_dv = 1'h0; // @[CSR.scala:755:48] wire _read_sstatus_WIRE_v = 1'h0; // @[CSR.scala:755:48] wire _read_sstatus_WIRE_sd = 1'h0; // @[CSR.scala:755:48] wire _read_sstatus_WIRE_mpv = 1'h0; // @[CSR.scala:755:48] wire _read_sstatus_WIRE_gva = 1'h0; // @[CSR.scala:755:48] wire _read_sstatus_WIRE_mbe = 1'h0; // @[CSR.scala:755:48] wire _read_sstatus_WIRE_sbe = 1'h0; // @[CSR.scala:755:48] wire _read_sstatus_WIRE_sd_rv32 = 1'h0; // @[CSR.scala:755:48] wire _read_sstatus_WIRE_tsr = 1'h0; // @[CSR.scala:755:48] wire _read_sstatus_WIRE_tw = 1'h0; // @[CSR.scala:755:48] wire _read_sstatus_WIRE_tvm = 1'h0; // @[CSR.scala:755:48] wire _read_sstatus_WIRE_mxr = 1'h0; // @[CSR.scala:755:48] wire _read_sstatus_WIRE_sum = 1'h0; // @[CSR.scala:755:48] wire _read_sstatus_WIRE_mprv = 1'h0; // @[CSR.scala:755:48] wire _read_sstatus_WIRE_spp = 1'h0; // @[CSR.scala:755:48] wire _read_sstatus_WIRE_mpie = 1'h0; // @[CSR.scala:755:48] wire _read_sstatus_WIRE_ube = 1'h0; // @[CSR.scala:755:48] wire _read_sstatus_WIRE_spie = 1'h0; // @[CSR.scala:755:48] wire _read_sstatus_WIRE_upie = 1'h0; // @[CSR.scala:755:48] wire _read_sstatus_WIRE_mie = 1'h0; // @[CSR.scala:755:48] wire _read_sstatus_WIRE_hie = 1'h0; // @[CSR.scala:755:48] wire _read_sstatus_WIRE_sie = 1'h0; // @[CSR.scala:755:48] wire _read_sstatus_WIRE_uie = 1'h0; // @[CSR.scala:755:48] wire read_sstatus_debug = 1'h0; // @[CSR.scala:755:35] wire read_sstatus_cease = 1'h0; // @[CSR.scala:755:35] wire read_sstatus_wfi = 1'h0; // @[CSR.scala:755:35] wire read_sstatus_dv = 1'h0; // @[CSR.scala:755:35] wire read_sstatus_v = 1'h0; // @[CSR.scala:755:35] wire read_sstatus_mpv = 1'h0; // @[CSR.scala:755:35] wire read_sstatus_gva = 1'h0; // @[CSR.scala:755:35] wire read_sstatus_mbe = 1'h0; // @[CSR.scala:755:35] wire read_sstatus_sbe = 1'h0; // @[CSR.scala:755:35] wire read_sstatus_sd_rv32 = 1'h0; // @[CSR.scala:755:35] wire read_sstatus_tsr = 1'h0; // @[CSR.scala:755:35] wire read_sstatus_tw = 1'h0; // @[CSR.scala:755:35] wire read_sstatus_tvm = 1'h0; // @[CSR.scala:755:35] wire read_sstatus_mprv = 1'h0; // @[CSR.scala:755:35] wire read_sstatus_mpie = 1'h0; // @[CSR.scala:755:35] wire read_sstatus_ube = 1'h0; // @[CSR.scala:755:35] wire read_sstatus_upie = 1'h0; // @[CSR.scala:755:35] wire read_sstatus_mie = 1'h0; // @[CSR.scala:755:35] wire read_sstatus_hie = 1'h0; // @[CSR.scala:755:35] wire read_sstatus_uie = 1'h0; // @[CSR.scala:755:35] wire read_pmp_15_cfg_l = 1'h0; // @[CSR.scala:787:59] wire read_pmp_15_cfg_x = 1'h0; // @[CSR.scala:787:59] wire read_pmp_15_cfg_w = 1'h0; // @[CSR.scala:787:59] wire read_pmp_15_cfg_r = 1'h0; // @[CSR.scala:787:59] wire _reg_custom_T = 1'h0; // @[CSR.scala:801:16] wire _reg_custom_T_1 = 1'h0; // @[CSR.scala:801:16] wire _allow_counter_T_4 = 1'h0; // @[CSR.scala:913:8] wire _io_decode_0_fp_illegal_T_1 = 1'h0; // @[CSR.scala:915:83] wire _io_decode_0_fp_illegal_T_2 = 1'h0; // @[CSR.scala:915:64] wire _io_decode_0_fp_illegal_T_5 = 1'h0; // @[CSR.scala:915:94] wire _io_decode_0_vector_illegal_T_4 = 1'h0; // @[CSR.scala:916:107] wire io_decode_0_vector_csr_plaOutput = 1'h0; // @[pla.scala:81:23] wire _io_decode_0_vector_csr_T = 1'h0; // @[Decode.scala:55:116] wire _io_decode_0_rocc_illegal_T_4 = 1'h0; // @[CSR.scala:919:105] wire _csr_addr_legal_T_3 = 1'h0; // @[CSR.scala:921:25] wire _csr_addr_legal_T_5 = 1'h0; // @[CSR.scala:921:43] wire _csr_addr_legal_T_8 = 1'h0; // @[CSR.scala:921:74] wire io_decode_0_read_illegal_plaOutput_1 = 1'h0; // @[pla.scala:81:23] wire _io_decode_0_read_illegal_T_16 = 1'h0; // @[Decode.scala:55:116] wire _io_decode_0_read_illegal_T_17 = 1'h0; // @[CSR.scala:928:43] wire _io_decode_0_system_illegal_T_20 = 1'h0; // @[CSR.scala:940:25] wire _io_decode_0_system_illegal_T_21 = 1'h0; // @[CSR.scala:940:22] wire _io_decode_0_system_illegal_T_23 = 1'h0; // @[CSR.scala:941:18] wire _io_decode_0_system_illegal_T_24 = 1'h0; // @[CSR.scala:941:15] wire _io_decode_0_virtual_access_illegal_T_27 = 1'h0; // @[CSR.scala:947:50] wire _io_decode_0_virtual_system_illegal_T_5 = 1'h0; // @[CSR.scala:953:57] wire trapToNmiInt = 1'h0; // @[CSR.scala:990:33] wire _trapToNmiXcpt_T = 1'h0; // @[CSR.scala:991:37] wire trapToNmiXcpt = 1'h0; // @[CSR.scala:991:34] wire trapToNmi = 1'h0; // @[CSR.scala:992:32] wire _nmiTVec_T = 1'h0; // @[CSR.scala:993:21] wire _nmiTVec_T_1 = 1'h0; // @[CSR.scala:993:58] wire _io_status_sd_T_1 = 1'h0; // @[CSR.scala:1003:53] wire _io_status_sd_T_3 = 1'h0; // @[CSR.scala:1003:74] wire _io_status_sd_rv32_T = 1'h0; // @[CSR.scala:1010:39] wire _io_gstatus_sd_T_1 = 1'h0; // @[CSR.scala:1016:56] wire _io_gstatus_sd_rv32_T = 1'h0; // @[CSR.scala:1018:40] wire _en_T_1 = 1'h0; // @[CSR.scala:1096:71] wire _en_T_2 = 1'h0; // @[CSR.scala:1096:24] wire en = 1'h0; // @[CSR.scala:1096:79] wire delegable = 1'h0; // @[CSR.scala:1097:65] wire _en_T_13 = 1'h0; // @[CSR.scala:1096:71] wire _en_T_14 = 1'h0; // @[CSR.scala:1096:24] wire en_2 = 1'h0; // @[CSR.scala:1096:79] wire delegable_2 = 1'h0; // @[CSR.scala:1097:65] wire delegable_3 = 1'h0; // @[CSR.scala:1097:65] wire _en_T_25 = 1'h0; // @[CSR.scala:1096:71] wire _en_T_26 = 1'h0; // @[CSR.scala:1096:24] wire en_4 = 1'h0; // @[CSR.scala:1096:79] wire delegable_4 = 1'h0; // @[CSR.scala:1097:65] wire _en_T_37 = 1'h0; // @[CSR.scala:1096:71] wire _en_T_38 = 1'h0; // @[CSR.scala:1096:24] wire en_6 = 1'h0; // @[CSR.scala:1096:79] wire delegable_6 = 1'h0; // @[CSR.scala:1097:65] wire delegable_7 = 1'h0; // @[CSR.scala:1097:65] wire _en_T_49 = 1'h0; // @[CSR.scala:1096:71] wire _en_T_50 = 1'h0; // @[CSR.scala:1096:24] wire en_8 = 1'h0; // @[CSR.scala:1096:79] wire delegable_8 = 1'h0; // @[CSR.scala:1097:65] wire _en_T_61 = 1'h0; // @[CSR.scala:1096:71] wire _en_T_62 = 1'h0; // @[CSR.scala:1096:24] wire en_10 = 1'h0; // @[CSR.scala:1096:79] wire delegable_10 = 1'h0; // @[CSR.scala:1097:65] wire delegable_11 = 1'h0; // @[CSR.scala:1097:65] wire _en_T_73 = 1'h0; // @[CSR.scala:1096:71] wire _en_T_74 = 1'h0; // @[CSR.scala:1096:24] wire en_12 = 1'h0; // @[CSR.scala:1096:79] wire delegable_12 = 1'h0; // @[CSR.scala:1097:65] wire _en_T_79 = 1'h0; // @[CSR.scala:1096:71] wire _en_T_80 = 1'h0; // @[CSR.scala:1096:24] wire en_13 = 1'h0; // @[CSR.scala:1096:79] wire delegable_13 = 1'h0; // @[CSR.scala:1097:65] wire _en_T_85 = 1'h0; // @[CSR.scala:1096:71] wire _en_T_86 = 1'h0; // @[CSR.scala:1096:24] wire en_14 = 1'h0; // @[CSR.scala:1096:79] wire delegable_14 = 1'h0; // @[CSR.scala:1097:65] wire _en_T_91 = 1'h0; // @[CSR.scala:1096:71] wire _en_T_92 = 1'h0; // @[CSR.scala:1096:24] wire en_15 = 1'h0; // @[CSR.scala:1096:79] wire delegable_15 = 1'h0; // @[CSR.scala:1097:65] wire delegable_16 = 1'h0; // @[CSR.scala:1109:67] wire delegable_20 = 1'h0; // @[CSR.scala:1109:67] wire delegable_22 = 1'h0; // @[CSR.scala:1109:67] wire delegable_24 = 1'h0; // @[CSR.scala:1109:67] wire delegable_25 = 1'h0; // @[CSR.scala:1109:67] wire _reg_mstatus_v_T = 1'h0; // @[CSR.scala:1123:44] wire _reg_mstatus_v_T_1 = 1'h0; // @[CSR.scala:1136:42] wire _reg_mstatus_v_T_3 = 1'h0; // @[CSR.scala:1136:56] wire _reg_mstatus_v_T_4 = 1'h0; // @[CSR.scala:1141:42] wire _reg_mstatus_v_T_5 = 1'h0; // @[CSR.scala:1141:82] wire _reg_mstatus_v_T_6 = 1'h0; // @[CSR.scala:1141:62] wire _reg_mstatus_mpp_T = 1'h0; // @[CSR.scala:1647:35] wire _reg_mstatus_mpp_T_1 = 1'h0; // @[CSR.scala:1647:29] wire _reg_mstatus_v_T_7 = 1'h0; // @[CSR.scala:1150:42] wire _reg_mstatus_v_T_9 = 1'h0; // @[CSR.scala:1150:61] wire _io_rw_rdata_T = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_29 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_30 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_31 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_32 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_33 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_34 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_35 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_36 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_37 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_38 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_39 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_40 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_41 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_42 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_43 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_44 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_45 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_46 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_47 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_48 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_49 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_50 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_51 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_52 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_53 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_54 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_55 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_56 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_57 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_58 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_59 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_60 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_61 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_62 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_63 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_64 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_65 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_66 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_67 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_68 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_69 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_70 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_71 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_72 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_73 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_74 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_75 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_76 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_77 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_78 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_79 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_80 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_81 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_82 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_83 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_84 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_85 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_86 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_87 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_88 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_89 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_90 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_91 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_92 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_93 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_94 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_95 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_96 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_97 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_98 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_99 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_100 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_101 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_102 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_103 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_104 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_105 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_106 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_107 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_108 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_109 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_147 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_148 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_149 = 1'h0; // @[Mux.scala:30:73] wire set_vs_dirty = 1'h0; // @[CSR.scala:1191:33] wire new_mip_hi_hi_hi_hi = 1'h0; // @[CSR.scala:1271:59] wire _reg_bp_0_WIRE_control_dmode = 1'h0; // @[CSR.scala:1613:23] wire _reg_bp_0_WIRE_control_action = 1'h0; // @[CSR.scala:1613:23] wire _reg_bp_0_WIRE_control_chain = 1'h0; // @[CSR.scala:1613:23] wire _reg_bp_0_WIRE_control_m = 1'h0; // @[CSR.scala:1613:23] wire _reg_bp_0_WIRE_control_h = 1'h0; // @[CSR.scala:1613:23] wire _reg_bp_0_WIRE_control_s = 1'h0; // @[CSR.scala:1613:23] wire _reg_bp_0_WIRE_control_u = 1'h0; // @[CSR.scala:1613:23] wire _reg_bp_0_WIRE_control_x = 1'h0; // @[CSR.scala:1613:23] wire _reg_bp_0_WIRE_control_w = 1'h0; // @[CSR.scala:1613:23] wire _reg_bp_0_WIRE_control_r = 1'h0; // @[CSR.scala:1613:23] wire _reg_bp_0_WIRE_textra_mselect = 1'h0; // @[CSR.scala:1613:23] wire _reg_bp_0_WIRE_textra_pad1 = 1'h0; // @[CSR.scala:1613:23] wire _reg_bp_0_WIRE_textra_sselect = 1'h0; // @[CSR.scala:1613:23] wire _reg_bp_1_WIRE_control_dmode = 1'h0; // @[CSR.scala:1613:23] wire _reg_bp_1_WIRE_control_action = 1'h0; // @[CSR.scala:1613:23] wire _reg_bp_1_WIRE_control_chain = 1'h0; // @[CSR.scala:1613:23] wire _reg_bp_1_WIRE_control_m = 1'h0; // @[CSR.scala:1613:23] wire _reg_bp_1_WIRE_control_h = 1'h0; // @[CSR.scala:1613:23] wire _reg_bp_1_WIRE_control_s = 1'h0; // @[CSR.scala:1613:23] wire _reg_bp_1_WIRE_control_u = 1'h0; // @[CSR.scala:1613:23] wire _reg_bp_1_WIRE_control_x = 1'h0; // @[CSR.scala:1613:23] wire _reg_bp_1_WIRE_control_w = 1'h0; // @[CSR.scala:1613:23] wire _reg_bp_1_WIRE_control_r = 1'h0; // @[CSR.scala:1613:23] wire _reg_bp_1_WIRE_textra_mselect = 1'h0; // @[CSR.scala:1613:23] wire _reg_bp_1_WIRE_textra_pad1 = 1'h0; // @[CSR.scala:1613:23] wire _reg_bp_1_WIRE_textra_sselect = 1'h0; // @[CSR.scala:1613:23] wire [7:0] io_status_zero1 = 8'h0; // @[CSR.scala:377:7] wire [7:0] io_gstatus_zero1 = 8'h0; // @[CSR.scala:377:7] wire [7:0] _reset_mstatus_WIRE_zero1 = 8'h0; // @[CSR.scala:391:47] wire [7:0] reset_mstatus_zero1 = 8'h0; // @[CSR.scala:391:34] wire [7:0] lo_2 = 8'h0; // @[CSR.scala:479:12] wire [7:0] hi_2 = 8'h0; // @[CSR.scala:479:12] wire [7:0] lo_3 = 8'h0; // @[CSR.scala:479:27] wire [7:0] hi_3 = 8'h0; // @[CSR.scala:479:27] wire [7:0] sie_mask_lo = 8'h0; // @[CSR.scala:750:59] wire [7:0] _read_sstatus_WIRE_zero1 = 8'h0; // @[CSR.scala:755:48] wire [7:0] read_sstatus_zero1 = 8'h0; // @[CSR.scala:755:35] wire [1:0] io_status_xs = 2'h0; // @[CSR.scala:377:7] wire [1:0] io_status_vs = 2'h0; // @[CSR.scala:377:7] wire [1:0] io_hstatus_zero3 = 2'h0; // @[CSR.scala:377:7] wire [1:0] io_hstatus_zero2 = 2'h0; // @[CSR.scala:377:7] wire [1:0] io_gstatus_dprv = 2'h0; // @[CSR.scala:377:7] wire [1:0] io_gstatus_prv = 2'h0; // @[CSR.scala:377:7] wire [1:0] io_gstatus_sxl = 2'h0; // @[CSR.scala:377:7] wire [1:0] io_gstatus_xs = 2'h0; // @[CSR.scala:377:7] wire [1:0] io_gstatus_mpp = 2'h0; // @[CSR.scala:377:7] wire [1:0] io_gstatus_vs = 2'h0; // @[CSR.scala:377:7] wire [1:0] io_pmp_0_cfg_res = 2'h0; // @[CSR.scala:377:7] wire [1:0] io_pmp_1_cfg_res = 2'h0; // @[CSR.scala:377:7] wire [1:0] io_pmp_2_cfg_res = 2'h0; // @[CSR.scala:377:7] wire [1:0] io_pmp_3_cfg_res = 2'h0; // @[CSR.scala:377:7] wire [1:0] io_pmp_4_cfg_res = 2'h0; // @[CSR.scala:377:7] wire [1:0] io_pmp_5_cfg_res = 2'h0; // @[CSR.scala:377:7] wire [1:0] io_pmp_6_cfg_res = 2'h0; // @[CSR.scala:377:7] wire [1:0] io_pmp_7_cfg_res = 2'h0; // @[CSR.scala:377:7] wire [1:0] _reset_mstatus_WIRE_dprv = 2'h0; // @[CSR.scala:391:47] wire [1:0] _reset_mstatus_WIRE_prv = 2'h0; // @[CSR.scala:391:47] wire [1:0] _reset_mstatus_WIRE_sxl = 2'h0; // @[CSR.scala:391:47] wire [1:0] _reset_mstatus_WIRE_uxl = 2'h0; // @[CSR.scala:391:47] wire [1:0] _reset_mstatus_WIRE_xs = 2'h0; // @[CSR.scala:391:47] wire [1:0] _reset_mstatus_WIRE_fs = 2'h0; // @[CSR.scala:391:47] wire [1:0] _reset_mstatus_WIRE_mpp = 2'h0; // @[CSR.scala:391:47] wire [1:0] _reset_mstatus_WIRE_vs = 2'h0; // @[CSR.scala:391:47] wire [1:0] reset_mstatus_dprv = 2'h0; // @[CSR.scala:391:34] wire [1:0] reset_mstatus_sxl = 2'h0; // @[CSR.scala:391:34] wire [1:0] reset_mstatus_uxl = 2'h0; // @[CSR.scala:391:34] wire [1:0] reset_mstatus_xs = 2'h0; // @[CSR.scala:391:34] wire [1:0] reset_mstatus_fs = 2'h0; // @[CSR.scala:391:34] wire [1:0] reset_mstatus_vs = 2'h0; // @[CSR.scala:391:34] wire [1:0] _reset_dcsr_WIRE_xdebugver = 2'h0; // @[CSR.scala:400:44] wire [1:0] _reset_dcsr_WIRE_zero4 = 2'h0; // @[CSR.scala:400:44] wire [1:0] _reset_dcsr_WIRE_zero1 = 2'h0; // @[CSR.scala:400:44] wire [1:0] _reset_dcsr_WIRE_prv = 2'h0; // @[CSR.scala:400:44] wire [1:0] reset_dcsr_zero4 = 2'h0; // @[CSR.scala:400:31] wire [1:0] reset_dcsr_zero1 = 2'h0; // @[CSR.scala:400:31] wire [1:0] hi_hi_lo = 2'h0; // @[CSR.scala:431:10] wire [1:0] hi_hi_hi = 2'h0; // @[CSR.scala:431:10] wire [1:0] lo_lo_hi_1 = 2'h0; // @[CSR.scala:431:50] wire [1:0] lo_hi_hi_1 = 2'h0; // @[CSR.scala:431:50] wire [1:0] hi_lo_hi_1 = 2'h0; // @[CSR.scala:431:50] wire [1:0] hi_hi_lo_1 = 2'h0; // @[CSR.scala:431:50] wire [1:0] hi_hi_hi_1 = 2'h0; // @[CSR.scala:431:50] wire [1:0] lo_lo_lo_2 = 2'h0; // @[CSR.scala:479:12] wire [1:0] lo_lo_hi_2 = 2'h0; // @[CSR.scala:479:12] wire [1:0] lo_hi_lo_2 = 2'h0; // @[CSR.scala:479:12] wire [1:0] lo_hi_hi_2 = 2'h0; // @[CSR.scala:479:12] wire [1:0] hi_lo_lo_2 = 2'h0; // @[CSR.scala:479:12] wire [1:0] hi_lo_hi_2 = 2'h0; // @[CSR.scala:479:12] wire [1:0] hi_hi_lo_2 = 2'h0; // @[CSR.scala:479:12] wire [1:0] hi_hi_hi_2 = 2'h0; // @[CSR.scala:479:12] wire [1:0] lo_lo_lo_3 = 2'h0; // @[CSR.scala:479:27] wire [1:0] lo_lo_hi_3 = 2'h0; // @[CSR.scala:479:27] wire [1:0] lo_hi_lo_3 = 2'h0; // @[CSR.scala:479:27] wire [1:0] lo_hi_hi_3 = 2'h0; // @[CSR.scala:479:27] wire [1:0] hi_lo_lo_3 = 2'h0; // @[CSR.scala:479:27] wire [1:0] hi_lo_hi_3 = 2'h0; // @[CSR.scala:479:27] wire [1:0] hi_hi_lo_3 = 2'h0; // @[CSR.scala:479:27] wire [1:0] hi_hi_hi_3 = 2'h0; // @[CSR.scala:479:27] wire [1:0] _reset_mnstatus_WIRE_mpp = 2'h0; // @[CSR.scala:516:48] wire [1:0] _reg_menvcfg_WIRE_cbie = 2'h0; // @[CSR.scala:525:41] wire [1:0] _reg_senvcfg_WIRE_cbie = 2'h0; // @[CSR.scala:526:41] wire [1:0] _reg_henvcfg_WIRE_cbie = 2'h0; // @[CSR.scala:527:41] wire [1:0] _reg_hstatus_WIRE_vsxl = 2'h0; // @[CSR.scala:552:41] wire [1:0] _reg_hstatus_WIRE_zero3 = 2'h0; // @[CSR.scala:552:41] wire [1:0] _reg_hstatus_WIRE_zero2 = 2'h0; // @[CSR.scala:552:41] wire [1:0] read_hvip_lo_lo_hi = 2'h0; // @[CSR.scala:555:27] wire [1:0] read_hvip_lo_hi_hi = 2'h0; // @[CSR.scala:555:27] wire [1:0] read_hvip_hi_lo_hi = 2'h0; // @[CSR.scala:555:27] wire [1:0] read_hvip_hi_hi_lo = 2'h0; // @[CSR.scala:555:27] wire [1:0] pmp_cfg_res = 2'h0; // @[PMP.scala:24:19] wire [1:0] pmp_1_cfg_res = 2'h0; // @[PMP.scala:24:19] wire [1:0] pmp_2_cfg_res = 2'h0; // @[PMP.scala:24:19] wire [1:0] pmp_3_cfg_res = 2'h0; // @[PMP.scala:24:19] wire [1:0] pmp_4_cfg_res = 2'h0; // @[PMP.scala:24:19] wire [1:0] pmp_5_cfg_res = 2'h0; // @[PMP.scala:24:19] wire [1:0] pmp_6_cfg_res = 2'h0; // @[PMP.scala:24:19] wire [1:0] pmp_7_cfg_res = 2'h0; // @[PMP.scala:24:19] wire [1:0] read_mapping_lo_lo_hi = 2'h0; // @[CSR.scala:655:48] wire [1:0] read_mapping_lo_hi_lo = 2'h0; // @[CSR.scala:655:48] wire [1:0] read_mapping_lo_hi_hi = 2'h0; // @[CSR.scala:655:48] wire [1:0] read_mapping_hi_lo_hi = 2'h0; // @[CSR.scala:655:48] wire [1:0] read_mapping_lo_1 = 2'h0; // @[CSR.scala:657:47] wire [1:0] debug_csrs_lo_hi_hi = 2'h0; // @[CSR.scala:670:27] wire [1:0] _read_mnstatus_WIRE_mpp = 2'h0; // @[CSR.scala:675:44] wire [1:0] read_vcsr = 2'h0; // @[CSR.scala:695:22] wire [1:0] hi_hi_4 = 2'h0; // @[CSR.scala:742:49] wire [1:0] sie_mask_lo_lo_lo = 2'h0; // @[CSR.scala:750:59] wire [1:0] sie_mask_lo_lo_hi = 2'h0; // @[CSR.scala:750:59] wire [1:0] sie_mask_lo_hi_lo = 2'h0; // @[CSR.scala:750:59] wire [1:0] sie_mask_lo_hi_hi = 2'h0; // @[CSR.scala:750:59] wire [1:0] sie_mask_hi_lo_lo = 2'h0; // @[CSR.scala:750:59] wire [1:0] sie_mask_hi_lo_hi = 2'h0; // @[CSR.scala:750:59] wire [1:0] sie_mask_hi_hi_hi = 2'h0; // @[CSR.scala:750:59] wire [1:0] _read_sstatus_WIRE_dprv = 2'h0; // @[CSR.scala:755:48] wire [1:0] _read_sstatus_WIRE_prv = 2'h0; // @[CSR.scala:755:48] wire [1:0] _read_sstatus_WIRE_sxl = 2'h0; // @[CSR.scala:755:48] wire [1:0] _read_sstatus_WIRE_uxl = 2'h0; // @[CSR.scala:755:48] wire [1:0] _read_sstatus_WIRE_xs = 2'h0; // @[CSR.scala:755:48] wire [1:0] _read_sstatus_WIRE_fs = 2'h0; // @[CSR.scala:755:48] wire [1:0] _read_sstatus_WIRE_mpp = 2'h0; // @[CSR.scala:755:48] wire [1:0] _read_sstatus_WIRE_vs = 2'h0; // @[CSR.scala:755:48] wire [1:0] read_sstatus_dprv = 2'h0; // @[CSR.scala:755:35] wire [1:0] read_sstatus_prv = 2'h0; // @[CSR.scala:755:35] wire [1:0] read_sstatus_sxl = 2'h0; // @[CSR.scala:755:35] wire [1:0] read_sstatus_xs = 2'h0; // @[CSR.scala:755:35] wire [1:0] read_sstatus_mpp = 2'h0; // @[CSR.scala:755:35] wire [1:0] read_sstatus_vs = 2'h0; // @[CSR.scala:755:35] wire [1:0] lo_lo_lo_hi = 2'h0; // @[CSR.scala:768:51] wire [1:0] lo_hi_hi_hi_hi = 2'h0; // @[CSR.scala:768:51] wire [1:0] hi_lo_hi_hi_hi = 2'h0; // @[CSR.scala:768:51] wire [1:0] hi_hi_hi_hi_hi = 2'h0; // @[CSR.scala:768:51] wire [1:0] hi_hi_6 = 2'h0; // @[CSR.scala:780:49] wire [1:0] read_pmp_15_cfg_res = 2'h0; // @[CSR.scala:787:59] wire [1:0] read_pmp_15_cfg_a = 2'h0; // @[CSR.scala:787:59] wire [1:0] lo_hi_16 = 2'h0; // @[package.scala:45:36] wire [1:0] lo_hi_17 = 2'h0; // @[package.scala:45:36] wire [1:0] lo_hi_18 = 2'h0; // @[package.scala:45:36] wire [1:0] lo_hi_19 = 2'h0; // @[package.scala:45:36] wire [1:0] lo_hi_20 = 2'h0; // @[package.scala:45:36] wire [1:0] lo_hi_21 = 2'h0; // @[package.scala:45:36] wire [1:0] lo_hi_22 = 2'h0; // @[package.scala:45:36] wire [1:0] lo_hi_23 = 2'h0; // @[package.scala:45:36] wire [1:0] decoded_orMatrixOutputs_lo_lo = 2'h0; // @[pla.scala:102:36] wire [1:0] decoded_orMatrixOutputs_lo_lo_1 = 2'h0; // @[pla.scala:102:36] wire [1:0] nmiTVec = 2'h0; // @[CSR.scala:993:62] wire [1:0] new_mip_lo_lo_hi = 2'h0; // @[CSR.scala:1271:59] wire [1:0] new_mip_lo_hi_hi = 2'h0; // @[CSR.scala:1271:59] wire [1:0] new_mip_hi_lo_hi = 2'h0; // @[CSR.scala:1271:59] wire [1:0] new_mip_hi_hi_lo = 2'h0; // @[CSR.scala:1271:59] wire [1:0] _reg_bp_0_WIRE_control_zero = 2'h0; // @[CSR.scala:1613:23] wire [1:0] _reg_bp_0_WIRE_control_tmatch = 2'h0; // @[CSR.scala:1613:23] wire [1:0] _reg_bp_1_WIRE_control_zero = 2'h0; // @[CSR.scala:1613:23] wire [1:0] _reg_bp_1_WIRE_control_tmatch = 2'h0; // @[CSR.scala:1613:23] wire [15:0] io_ptbr_asid = 16'h0; // @[CSR.scala:377:7] wire [15:0] io_hgatp_asid = 16'h0; // @[CSR.scala:377:7] wire [15:0] io_vsatp_asid = 16'h0; // @[CSR.scala:377:7] wire [15:0] hs_delegable_interrupts = 16'h0; // @[CSR.scala:479:12] wire [15:0] mideleg_always_hs = 16'h0; // @[CSR.scala:479:27] wire [15:0] read_hvip = 16'h0; // @[CSR.scala:555:34] wire [15:0] read_hip = 16'h0; // @[CSR.scala:611:27] wire [15:0] lo_lo_8 = 16'h0; // @[package.scala:45:27] wire [15:0] lo_hi_24 = 16'h0; // @[package.scala:45:27] wire [15:0] hi_lo_8 = 16'h0; // @[package.scala:45:27] wire [15:0] hi_hi_24 = 16'h0; // @[package.scala:45:27] wire [15:0] _en_T = 16'h0; // @[CSR.scala:1096:49] wire [15:0] _delegable_T = 16'h0; // @[CSR.scala:1097:43] wire [15:0] _en_T_12 = 16'h0; // @[CSR.scala:1096:49] wire [15:0] _delegable_T_2 = 16'h0; // @[CSR.scala:1097:43] wire [15:0] _delegable_T_3 = 16'h0; // @[CSR.scala:1097:43] wire [15:0] _en_T_24 = 16'h0; // @[CSR.scala:1096:49] wire [15:0] _delegable_T_4 = 16'h0; // @[CSR.scala:1097:43] wire [15:0] _en_T_36 = 16'h0; // @[CSR.scala:1096:49] wire [15:0] _delegable_T_6 = 16'h0; // @[CSR.scala:1097:43] wire [15:0] _delegable_T_7 = 16'h0; // @[CSR.scala:1097:43] wire [15:0] _en_T_48 = 16'h0; // @[CSR.scala:1096:49] wire [15:0] _delegable_T_8 = 16'h0; // @[CSR.scala:1097:43] wire [15:0] _en_T_60 = 16'h0; // @[CSR.scala:1096:49] wire [15:0] _delegable_T_10 = 16'h0; // @[CSR.scala:1097:43] wire [15:0] _delegable_T_11 = 16'h0; // @[CSR.scala:1097:43] wire [15:0] _en_T_72 = 16'h0; // @[CSR.scala:1096:49] wire [15:0] _delegable_T_12 = 16'h0; // @[CSR.scala:1097:43] wire [15:0] _en_T_78 = 16'h0; // @[CSR.scala:1096:49] wire [15:0] _delegable_T_13 = 16'h0; // @[CSR.scala:1097:43] wire [15:0] _en_T_84 = 16'h0; // @[CSR.scala:1096:49] wire [15:0] _delegable_T_14 = 16'h0; // @[CSR.scala:1097:43] wire [15:0] _en_T_90 = 16'h0; // @[CSR.scala:1096:49] wire [15:0] _delegable_T_15 = 16'h0; // @[CSR.scala:1097:43] wire [15:0] _delegable_T_16 = 16'h0; // @[CSR.scala:1109:45] wire [15:0] _delegable_T_20 = 16'h0; // @[CSR.scala:1109:45] wire [15:0] _delegable_T_22 = 16'h0; // @[CSR.scala:1109:45] wire [15:0] _delegable_T_24 = 16'h0; // @[CSR.scala:1109:45] wire [15:0] _delegable_T_25 = 16'h0; // @[CSR.scala:1109:45] wire [5:0] io_hstatus_vgein = 6'h0; // @[CSR.scala:377:7] wire [5:0] _reg_hstatus_WIRE_vgein = 6'h0; // @[CSR.scala:552:41] wire [5:0] read_mapping_hi_lo = 6'h0; // @[CSR.scala:655:48] wire [5:0] hi_lo_hi_4 = 6'h0; // @[CSR.scala:768:51] wire [5:0] _reg_bp_0_WIRE_control_maskmax = 6'h0; // @[CSR.scala:1613:23] wire [5:0] _reg_bp_1_WIRE_control_maskmax = 6'h0; // @[CSR.scala:1613:23] wire [3:0] io_hgatp_mode = 4'h0; // @[CSR.scala:377:7] wire [3:0] io_vsatp_mode = 4'h0; // @[CSR.scala:377:7] wire [3:0] hi_hi = 4'h0; // @[CSR.scala:431:10] wire [3:0] hi_hi_1 = 4'h0; // @[CSR.scala:431:50] wire [3:0] lo_lo_2 = 4'h0; // @[CSR.scala:479:12] wire [3:0] lo_hi_2 = 4'h0; // @[CSR.scala:479:12] wire [3:0] hi_lo_2 = 4'h0; // @[CSR.scala:479:12] wire [3:0] hi_hi_2 = 4'h0; // @[CSR.scala:479:12] wire [3:0] lo_lo_3 = 4'h0; // @[CSR.scala:479:27] wire [3:0] lo_hi_3 = 4'h0; // @[CSR.scala:479:27] wire [3:0] hi_lo_3 = 4'h0; // @[CSR.scala:479:27] wire [3:0] hi_hi_3 = 4'h0; // @[CSR.scala:479:27] wire [3:0] read_mapping_lo_hi = 4'h0; // @[CSR.scala:655:48] wire [3:0] read_mapping_hi_lo_lo = 4'h0; // @[CSR.scala:655:48] wire [3:0] sie_mask_lo_lo = 4'h0; // @[CSR.scala:750:59] wire [3:0] sie_mask_lo_hi = 4'h0; // @[CSR.scala:750:59] wire [3:0] sie_mask_hi_lo = 4'h0; // @[CSR.scala:750:59] wire [3:0] lo_hi_lo_lo = 4'h0; // @[CSR.scala:768:51] wire [3:0] hi_hi_lo_hi = 4'h0; // @[CSR.scala:768:51] wire [3:0] _reg_bp_0_WIRE_control_ttype = 4'h0; // @[CSR.scala:1613:23] wire [3:0] _reg_bp_1_WIRE_control_ttype = 4'h0; // @[CSR.scala:1613:23] wire [63:0] io_customCSRs_0_sdata = 64'h0; // @[CSR.scala:377:7] wire [63:0] io_customCSRs_1_sdata = 64'h0; // @[CSR.scala:377:7] wire [63:0] read_hideleg = 64'h0; // @[CSR.scala:541:14] wire [63:0] read_hedeleg = 64'h0; // @[CSR.scala:545:14] wire [63:0] read_hie = 64'h0; // @[CSR.scala:556:26] wire [63:0] read_vstvec = 64'h0; // @[package.scala:132:15] wire [63:0] _vs_interrupts_T_6 = 64'h0; // @[CSR.scala:622:153] wire [63:0] vs_interrupts = 64'h0; // @[CSR.scala:622:26] wire [63:0] read_mapping_1_2 = 64'h0; // @[CSR.scala:655:48] wire [63:0] read_mapping_2_2 = 64'h0; // @[package.scala:132:15] wire [63:0] _io_rw_rdata_T_1 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_2 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_128 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_150 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_151 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_152 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _reg_custom_1_T = 64'h0; // @[CSR.scala:1506:23] wire [63:0] _reg_custom_0_T_4 = 64'h0; // @[CSR.scala:1531:24] wire [63:0] _reg_custom_1_T_4 = 64'h0; // @[CSR.scala:1531:24] wire [29:0] io_hstatus_zero6 = 30'h0; // @[CSR.scala:377:7] wire [29:0] _reg_hstatus_WIRE_zero6 = 30'h0; // @[CSR.scala:552:41] wire [29:0] read_pmp_15_addr = 30'h0; // @[CSR.scala:787:59] wire [29:0] _io_rw_rdata_T_137 = 30'h0; // @[Mux.scala:30:73] wire [29:0] _io_rw_rdata_T_138 = 30'h0; // @[Mux.scala:30:73] wire [29:0] _io_rw_rdata_T_139 = 30'h0; // @[Mux.scala:30:73] wire [29:0] _io_rw_rdata_T_140 = 30'h0; // @[Mux.scala:30:73] wire [29:0] _io_rw_rdata_T_141 = 30'h0; // @[Mux.scala:30:73] wire [29:0] _io_rw_rdata_T_142 = 30'h0; // @[Mux.scala:30:73] wire [29:0] _io_rw_rdata_T_143 = 30'h0; // @[Mux.scala:30:73] wire [29:0] _io_rw_rdata_T_144 = 30'h0; // @[Mux.scala:30:73] wire [50:0] read_mapping_hi_hi = 51'h0; // @[CSR.scala:655:48] wire [50:0] read_mapping_3_2 = 51'h0; // @[CSR.scala:657:47] wire [50:0] _io_rw_rdata_T_3 = 51'h0; // @[Mux.scala:30:73] wire [1:0] reset_dcsr_xdebugver = 2'h1; // @[CSR.scala:400:31] wire [1:0] _read_mapping_T_4 = 2'h1; // @[CSR.scala:1665:36] wire [1:0] _debug_csrs_T_2 = 2'h1; // @[CSR.scala:1665:36] wire [1:0] sie_mask_hi_hi_lo = 2'h1; // @[CSR.scala:750:59] wire [1:0] _io_evec_T_2 = 2'h1; // @[CSR.scala:1665:36] wire [1:0] _io_evec_T_7 = 2'h1; // @[CSR.scala:1665:36] wire [1:0] _io_evec_T_12 = 2'h1; // @[CSR.scala:1665:36] wire [1:0] _io_evec_T_17 = 2'h1; // @[CSR.scala:1665:36] wire [1:0] _io_evec_T_22 = 2'h1; // @[CSR.scala:1665:36] wire [4:0] io_hstatus_zero1 = 5'h0; // @[CSR.scala:377:7] wire [4:0] _reg_hstatus_WIRE_zero1 = 5'h0; // @[CSR.scala:552:41] wire [4:0] read_mapping_hi_hi_hi = 5'h0; // @[CSR.scala:655:48] wire [4:0] hi_19 = 5'h0; // @[package.scala:45:36] wire [4:0] hi_20 = 5'h0; // @[package.scala:45:36] wire [4:0] hi_21 = 5'h0; // @[package.scala:45:36] wire [4:0] hi_22 = 5'h0; // @[package.scala:45:36] wire [4:0] hi_23 = 5'h0; // @[package.scala:45:36] wire [4:0] hi_24 = 5'h0; // @[package.scala:45:36] wire [4:0] hi_25 = 5'h0; // @[package.scala:45:36] wire [4:0] hi_26 = 5'h0; // @[package.scala:45:36] wire [2:0] _reset_dcsr_WIRE_cause = 3'h0; // @[CSR.scala:400:44] wire [2:0] reset_dcsr_cause = 3'h0; // @[CSR.scala:400:31] wire [2:0] _reset_mnstatus_WIRE_zero3 = 3'h0; // @[CSR.scala:516:48] wire [2:0] _reset_mnstatus_WIRE_zero2 = 3'h0; // @[CSR.scala:516:48] wire [2:0] _reset_mnstatus_WIRE_zero1 = 3'h0; // @[CSR.scala:516:48] wire [2:0] reset_mnstatus_zero3 = 3'h0; // @[CSR.scala:516:35] wire [2:0] reset_mnstatus_zero2 = 3'h0; // @[CSR.scala:516:35] wire [2:0] reset_mnstatus_zero1 = 3'h0; // @[CSR.scala:516:35] wire [2:0] _reg_menvcfg_WIRE_zero3 = 3'h0; // @[CSR.scala:525:41] wire [2:0] _reg_senvcfg_WIRE_zero3 = 3'h0; // @[CSR.scala:526:41] wire [2:0] _reg_henvcfg_WIRE_zero3 = 3'h0; // @[CSR.scala:527:41] wire [2:0] read_mapping_lo_lo = 3'h0; // @[CSR.scala:655:48] wire [2:0] _read_mnstatus_WIRE_zero3 = 3'h0; // @[CSR.scala:675:44] wire [2:0] _read_mnstatus_WIRE_zero2 = 3'h0; // @[CSR.scala:675:44] wire [2:0] _read_mnstatus_WIRE_zero1 = 3'h0; // @[CSR.scala:675:44] wire [2:0] read_mnstatus_zero3 = 3'h0; // @[CSR.scala:675:31] wire [2:0] read_mnstatus_zero2 = 3'h0; // @[CSR.scala:675:31] wire [2:0] read_mnstatus_zero1 = 3'h0; // @[CSR.scala:675:31] wire [2:0] lo_hi_4 = 3'h0; // @[CSR.scala:742:49] wire [2:0] hi_lo_hi_lo = 3'h0; // @[CSR.scala:768:51] wire [2:0] hi_lo_hi_hi = 3'h0; // @[CSR.scala:768:51] wire [2:0] hi_hi_lo_hi_hi = 3'h0; // @[CSR.scala:768:51] wire [2:0] hi_hi_hi_hi_4 = 3'h0; // @[CSR.scala:768:51] wire [2:0] lo_hi_6 = 3'h0; // @[CSR.scala:780:49] wire [2:0] lo_16 = 3'h0; // @[package.scala:45:36] wire [2:0] hi_hi_16 = 3'h0; // @[package.scala:45:36] wire [2:0] lo_17 = 3'h0; // @[package.scala:45:36] wire [2:0] hi_hi_17 = 3'h0; // @[package.scala:45:36] wire [2:0] lo_18 = 3'h0; // @[package.scala:45:36] wire [2:0] hi_hi_18 = 3'h0; // @[package.scala:45:36] wire [2:0] lo_19 = 3'h0; // @[package.scala:45:36] wire [2:0] hi_hi_19 = 3'h0; // @[package.scala:45:36] wire [2:0] lo_20 = 3'h0; // @[package.scala:45:36] wire [2:0] hi_hi_20 = 3'h0; // @[package.scala:45:36] wire [2:0] lo_21 = 3'h0; // @[package.scala:45:36] wire [2:0] hi_hi_21 = 3'h0; // @[package.scala:45:36] wire [2:0] lo_22 = 3'h0; // @[package.scala:45:36] wire [2:0] hi_hi_22 = 3'h0; // @[package.scala:45:36] wire [2:0] lo_23 = 3'h0; // @[package.scala:45:36] wire [2:0] hi_hi_23 = 3'h0; // @[package.scala:45:36] wire [56:0] read_mapping_hi = 57'h0; // @[CSR.scala:655:48] wire [56:0] hi_6 = 57'h0; // @[CSR.scala:742:49] wire [56:0] hi_9 = 57'h0; // @[CSR.scala:780:49] wire [54:0] hi_lo_4 = 55'h0; // @[CSR.scala:742:49] wire [54:0] hi_lo_6 = 55'h0; // @[CSR.scala:780:49] wire [8:0] io_hstatus_zero5 = 9'h0; // @[CSR.scala:377:7] wire [8:0] _reg_hstatus_WIRE_zero5 = 9'h0; // @[CSR.scala:552:41] wire [8:0] hi_lo_lo_lo = 9'h0; // @[CSR.scala:768:51] wire [1:0] io_gstatus_fs = 2'h3; // @[CSR.scala:377:7] wire [1:0] reset_mstatus_prv = 2'h3; // @[CSR.scala:391:34] wire [1:0] reset_mstatus_mpp = 2'h3; // @[CSR.scala:391:34] wire [1:0] reset_dcsr_prv = 2'h3; // @[CSR.scala:400:31] wire [1:0] reset_mnstatus_mpp = 2'h3; // @[CSR.scala:516:35] wire [1:0] read_mnstatus_mpp = 2'h3; // @[CSR.scala:675:31] wire [3:0] _which_T_64 = 4'h4; // @[Mux.scala:50:70] wire [3:0] _which_T_65 = 4'h4; // @[Mux.scala:50:70] wire [3:0] _which_T_66 = 4'h4; // @[Mux.scala:50:70] wire [3:0] _which_T_67 = 4'h4; // @[Mux.scala:50:70] wire [3:0] _which_T_68 = 4'h4; // @[Mux.scala:50:70] wire [3:0] _which_T_69 = 4'h4; // @[Mux.scala:50:70] wire [3:0] _which_T_70 = 4'h4; // @[Mux.scala:50:70] wire [3:0] _which_T_71 = 4'h4; // @[Mux.scala:50:70] wire [3:0] _which_T_72 = 4'h4; // @[Mux.scala:50:70] wire [3:0] _which_T_73 = 4'h4; // @[Mux.scala:50:70] wire [3:0] _which_T_74 = 4'h4; // @[Mux.scala:50:70] wire [3:0] _which_T_75 = 4'h4; // @[Mux.scala:50:70] wire [3:0] _which_T_76 = 4'h4; // @[Mux.scala:50:70] wire [3:0] _which_T_77 = 4'h4; // @[Mux.scala:50:70] wire [3:0] _which_T_78 = 4'h4; // @[Mux.scala:50:70] wire [3:0] debug_csrs_hi_hi_hi = 4'h4; // @[CSR.scala:670:27] wire [48:0] read_mapping_hi_1 = 49'h0; // @[CSR.scala:657:47] wire [24:0] _read_mapping_T_1 = 25'h0; // @[package.scala:132:20] wire [45:0] read_mapping_hi_hi_lo = 46'h0; // @[CSR.scala:655:48] wire [6:0] read_mapping_lo = 7'h0; // @[CSR.scala:655:48] wire [2:0] read_mstatus_hi_lo_hi_lo = 3'h2; // @[CSR.scala:649:32] wire [43:0] io_hgatp_ppn = 44'h0; // @[CSR.scala:377:7] wire [43:0] io_vsatp_ppn = 44'h0; // @[CSR.scala:377:7] wire [47:0] _reg_bp_0_WIRE_textra_pad2 = 48'h0; // @[CSR.scala:1613:23] wire [47:0] _reg_bp_1_WIRE_textra_pad2 = 48'h0; // @[CSR.scala:1613:23] wire [38:0] _read_stvec_T_2 = 39'h0; // @[package.scala:174:46] wire [38:0] _reg_bp_0_WIRE_address = 39'h0; // @[CSR.scala:1613:23] wire [38:0] _reg_bp_1_WIRE_address = 39'h0; // @[CSR.scala:1613:23] wire [39:0] io_htval = 40'h0; // @[CSR.scala:377:7] wire [39:0] _reg_bp_0_WIRE_control_reserved = 40'h0; // @[CSR.scala:1613:23] wire [39:0] _reg_bp_1_WIRE_control_reserved = 40'h0; // @[CSR.scala:1613:23] wire [1:0] io_status_sxl = 2'h2; // @[CSR.scala:377:7] wire [1:0] io_status_uxl = 2'h2; // @[CSR.scala:377:7] wire [1:0] io_hstatus_vsxl = 2'h2; // @[CSR.scala:377:7] wire [1:0] io_gstatus_uxl = 2'h2; // @[CSR.scala:377:7] wire [1:0] lo_lo_lo = 2'h2; // @[CSR.scala:431:10] wire [1:0] lo_lo_hi = 2'h2; // @[CSR.scala:431:10] wire [1:0] lo_hi_lo = 2'h2; // @[CSR.scala:431:10] wire [1:0] lo_hi_hi = 2'h2; // @[CSR.scala:431:10] wire [1:0] hi_lo_lo = 2'h2; // @[CSR.scala:431:10] wire [1:0] hi_lo_hi = 2'h2; // @[CSR.scala:431:10] wire [1:0] lo_lo_lo_1 = 2'h2; // @[CSR.scala:431:50] wire [1:0] lo_hi_lo_1 = 2'h2; // @[CSR.scala:431:50] wire [1:0] hi_lo_lo_1 = 2'h2; // @[CSR.scala:431:50] wire [1:0] read_sstatus_uxl = 2'h2; // @[CSR.scala:755:35] wire [31:0] io_gstatus_isa = 32'h0; // @[CSR.scala:377:7] wire [31:0] io_inst_0 = 32'h0; // @[CSR.scala:377:7] wire [31:0] io_trace_0_insn = 32'h0; // @[CSR.scala:377:7] wire [31:0] _reset_mstatus_WIRE_isa = 32'h0; // @[CSR.scala:391:47] wire [31:0] reset_mstatus_isa = 32'h0; // @[CSR.scala:391:34] wire [31:0] read_hcounteren = 32'h0; // @[CSR.scala:550:14] wire [31:0] _read_mtvec_T_2 = 32'h0; // @[package.scala:174:46] wire [31:0] _read_sstatus_WIRE_isa = 32'h0; // @[CSR.scala:755:48] wire [31:0] read_sstatus_isa = 32'h0; // @[CSR.scala:755:35] wire [31:0] read_pmp_15_mask = 32'h0; // @[CSR.scala:787:59] wire [31:0] lo_24 = 32'h0; // @[package.scala:45:27] wire [31:0] hi_27 = 32'h0; // @[package.scala:45:27] wire [63:0] _s_interrupts_T_7 = 64'hFFFFFFFFFFFFFFFF; // @[CSR.scala:621:168] wire [63:0] _reg_custom_1_T_1 = 64'hFFFFFFFFFFFFFFFF; // @[CSR.scala:1506:40] wire [63:0] _reg_custom_1_T_5 = 64'hFFFFFFFFFFFFFFFF; // @[CSR.scala:1531:41] wire [63:0] _reg_custom_0_T_1 = 64'hFFFFFFFFFFFFFFF7; // @[CSR.scala:1506:40] wire [63:0] _reg_custom_0_T_5 = 64'hFFFFFFFFFFFFFFF7; // @[CSR.scala:1531:41] wire [63:0] _reg_mcountinhibit_T = 64'hFFFFFFFFFFFFFFFD; // @[CSR.scala:1306:78] wire [15:0] _sie_mask_T = 16'h1000; // @[CSR.scala:750:59] wire [15:0] _sie_mask_T_1 = 16'h1000; // @[CSR.scala:750:46] wire [15:0] _delegable_T_26 = 16'h1000; // @[CSR.scala:1109:45] wire [15:0] _en_T_18 = 16'h8; // @[CSR.scala:1096:49] wire [15:0] _delegable_T_18 = 16'h8; // @[CSR.scala:1109:45] wire [63:0] _en_T_94 = 64'h800000000000000F; // @[CSR.scala:1096:120] wire [63:0] _en_T_88 = 64'h800000000000000E; // @[CSR.scala:1096:120] wire [63:0] _en_T_82 = 64'h800000000000000D; // @[CSR.scala:1096:120] wire [63:0] _en_T_76 = 64'h800000000000000C; // @[CSR.scala:1096:120] wire [63:0] _en_T_70 = 64'h800000000000000B; // @[CSR.scala:1096:120] wire [15:0] _en_T_66 = 16'h800; // @[CSR.scala:1096:49] wire [63:0] _en_T_64 = 64'h800000000000000A; // @[CSR.scala:1096:120] wire [15:0] _en_T_54 = 16'h200; // @[CSR.scala:1096:49] wire [15:0] _delegable_T_9 = 16'h200; // @[CSR.scala:1097:43] wire [63:0] _en_T_58 = 64'h8000000000000009; // @[CSR.scala:1096:120] wire [63:0] _en_T_52 = 64'h8000000000000008; // @[CSR.scala:1096:120] wire [63:0] _en_T_46 = 64'h8000000000000007; // @[CSR.scala:1096:120] wire [15:0] _en_T_42 = 16'h80; // @[CSR.scala:1096:49] wire [63:0] _en_T_40 = 64'h8000000000000006; // @[CSR.scala:1096:120] wire [15:0] _en_T_30 = 16'h20; // @[CSR.scala:1096:49] wire [15:0] _delegable_T_5 = 16'h20; // @[CSR.scala:1097:43] wire [63:0] _en_T_34 = 64'h8000000000000005; // @[CSR.scala:1096:120] wire [63:0] _en_T_28 = 64'h8000000000000004; // @[CSR.scala:1096:120] wire [63:0] _en_T_22 = 64'h8000000000000003; // @[CSR.scala:1096:120] wire [63:0] _en_T_16 = 64'h8000000000000002; // @[CSR.scala:1096:120] wire [15:0] _en_T_6 = 16'h2; // @[CSR.scala:1096:49] wire [15:0] _delegable_T_1 = 16'h2; // @[CSR.scala:1097:43] wire [63:0] _en_T_10 = 64'h8000000000000001; // @[CSR.scala:1096:120] wire [63:0] _interruptCause_T_2 = 64'h8000000000000000; // @[CSR.scala:625:39] wire [63:0] _en_T_4 = 64'h8000000000000000; // @[CSR.scala:1096:120] wire [64:0] _interruptCause_T_1 = 65'h8000000000000000; // @[CSR.scala:625:39] wire [64:0] _en_T_3 = 65'h8000000000000000; // @[CSR.scala:1096:120] wire [9:0] _io_decode_0_write_flush_addr_m_T = 10'h300; // @[CSR.scala:932:36] wire [36:0] hi_hi_hi_4 = 37'h0; // @[CSR.scala:768:51] wire [33:0] hi_hi_hi_lo = 34'h0; // @[CSR.scala:768:51] wire [17:0] hi_lo_5 = 18'h800; // @[CSR.scala:768:51] wire [11:0] hi_lo_lo_4 = 12'h800; // @[CSR.scala:768:51] wire [2:0] _which_T_63 = 3'h4; // @[Mux.scala:50:70] wire [2:0] read_mstatus_hi_lo_lo_hi = 3'h4; // @[CSR.scala:649:32] wire [2:0] hi_lo_lo_hi = 3'h4; // @[CSR.scala:768:51] wire [15:0] _sie_mask_T_2 = 16'hEFFF; // @[CSR.scala:750:20] wire [7:0] sie_mask_hi = 8'h10; // @[CSR.scala:750:59] wire [3:0] sie_mask_hi_hi = 4'h1; // @[CSR.scala:750:59] wire [53:0] _reg_menvcfg_WIRE_zero54 = 54'h0; // @[CSR.scala:525:41] wire [53:0] _reg_senvcfg_WIRE_zero54 = 54'h0; // @[CSR.scala:526:41] wire [53:0] _reg_henvcfg_WIRE_zero54 = 54'h0; // @[CSR.scala:527:41] wire [15:0] delegable_interrupts = 16'h222; // @[CSR.scala:431:50] wire [7:0] hi_1 = 8'h2; // @[CSR.scala:431:50] wire [3:0] lo_lo_1 = 4'h2; // @[CSR.scala:431:50] wire [3:0] lo_hi_1 = 4'h2; // @[CSR.scala:431:50] wire [3:0] hi_lo_1 = 4'h2; // @[CSR.scala:431:50] wire [7:0] lo_1 = 8'h22; // @[CSR.scala:431:50] wire [15:0] supported_interrupts = 16'hAAA; // @[CSR.scala:431:17] wire [7:0] hi = 8'hA; // @[CSR.scala:431:10] wire [3:0] lo_lo = 4'hA; // @[CSR.scala:431:10] wire [3:0] lo_hi = 4'hA; // @[CSR.scala:431:10] wire [3:0] hi_lo = 4'hA; // @[CSR.scala:431:10] wire [7:0] lo = 8'hAA; // @[CSR.scala:431:10] wire [11:0] _reset_dcsr_WIRE_zero3 = 12'h0; // @[CSR.scala:400:44] wire [11:0] reset_dcsr_zero3 = 12'h0; // @[CSR.scala:400:31] wire [15:0] _delegable_T_27 = 16'h2000; // @[CSR.scala:1109:45] wire [15:0] _delegable_T_23 = 16'h100; // @[CSR.scala:1109:45] wire [15:0] _delegable_T_21 = 16'h40; // @[CSR.scala:1109:45] wire [15:0] _delegable_T_19 = 16'h10; // @[CSR.scala:1109:45] wire [15:0] _delegable_T_17 = 16'h4; // @[CSR.scala:1109:45] wire [64:0] _en_T_93 = 65'h800000000000000F; // @[CSR.scala:1096:120] wire [64:0] _en_T_87 = 65'h800000000000000E; // @[CSR.scala:1096:120] wire [64:0] _en_T_81 = 65'h800000000000000D; // @[CSR.scala:1096:120] wire [64:0] _en_T_75 = 65'h800000000000000C; // @[CSR.scala:1096:120] wire [64:0] _en_T_69 = 65'h800000000000000B; // @[CSR.scala:1096:120] wire [64:0] _en_T_63 = 65'h800000000000000A; // @[CSR.scala:1096:120] wire [64:0] _en_T_57 = 65'h8000000000000009; // @[CSR.scala:1096:120] wire [64:0] _en_T_51 = 65'h8000000000000008; // @[CSR.scala:1096:120] wire [64:0] _en_T_45 = 65'h8000000000000007; // @[CSR.scala:1096:120] wire [64:0] _en_T_39 = 65'h8000000000000006; // @[CSR.scala:1096:120] wire [64:0] _en_T_33 = 65'h8000000000000005; // @[CSR.scala:1096:120] wire [64:0] _en_T_27 = 65'h8000000000000004; // @[CSR.scala:1096:120] wire [64:0] _en_T_21 = 65'h8000000000000003; // @[CSR.scala:1096:120] wire [64:0] _en_T_15 = 65'h8000000000000002; // @[CSR.scala:1096:120] wire [64:0] _en_T_9 = 65'h8000000000000001; // @[CSR.scala:1096:120] wire [62:0] _interruptCause_T = 63'h0; // @[CSR.scala:625:50] wire [15:0] _delegable_T_28 = 16'h8000; // @[CSR.scala:1109:45] wire [39:0] _io_evec_T_15 = 40'hFFFFFFFFFF; // @[CSR.scala:1665:28] wire mip_mtip = io_interrupts_mtip_0; // @[CSR.scala:377:7, :600:24] wire mip_msip = io_interrupts_msip_0; // @[CSR.scala:377:7, :600:24] wire mip_meip = io_interrupts_meip_0; // @[CSR.scala:377:7, :600:24] wire [63:0] _io_rw_rdata_WIRE; // @[Mux.scala:30:73] wire [31:0] decoded_plaInput_1 = io_decode_0_inst_0; // @[pla.scala:77:22] wire _io_decode_0_fp_illegal_T_6; // @[CSR.scala:915:91] wire _io_decode_0_fp_csr_T; // @[Decode.scala:55:116] wire _io_decode_0_read_illegal_T_20; // @[CSR.scala:928:68] wire _io_decode_0_write_illegal_T_1; // @[CSR.scala:930:41] wire _io_decode_0_write_flush_T_3; // @[CSR.scala:933:7] wire _io_decode_0_system_illegal_T_25; // @[CSR.scala:940:44] wire _io_decode_0_virtual_access_illegal_T_29; // @[CSR.scala:943:66] wire _io_decode_0_virtual_system_illegal_T_22; // @[CSR.scala:949:52] wire _io_csr_stall_T; // @[CSR.scala:1161:27] wire _io_eret_T_1; // @[CSR.scala:1000:38] wire _io_singleStep_T_1; // @[CSR.scala:1001:34] wire [1:0] _io_status_dprv_T_2; // @[CSR.scala:1008:24] wire _io_status_dv_T_3; // @[CSR.scala:1009:33] wire _io_status_sd_T_4; // @[CSR.scala:1003:58] wire read_sstatus_sd = io_status_sd_0; // @[CSR.scala:377:7, :755:35] wire read_sstatus_mxr = io_status_mxr_0; // @[CSR.scala:377:7, :755:35] wire read_sstatus_sum = io_status_sum_0; // @[CSR.scala:377:7, :755:35] wire [1:0] read_sstatus_fs = io_status_fs_0; // @[CSR.scala:377:7, :755:35] wire read_sstatus_spp = io_status_spp_0; // @[CSR.scala:377:7, :755:35] wire read_sstatus_spie = io_status_spie_0; // @[CSR.scala:377:7, :755:35] wire read_sstatus_sie = io_status_sie_0; // @[CSR.scala:377:7, :755:35] wire _io_trace_0_valid_T = io_retire_0; // @[CSR.scala:377:7, :1621:26] wire [39:0] io_trace_0_iaddr = io_pc_0; // @[CSR.scala:377:7] wire [39:0] io_trace_0_tval = io_tval_0; // @[CSR.scala:377:7] wire [63:0] value_1; // @[Counters.scala:55:30] wire _io_interrupt_T_5; // @[CSR.scala:626:73] wire [63:0] interruptCause; // @[CSR.scala:625:63] wire pmp_cfg_l; // @[PMP.scala:24:19] wire [1:0] pmp_cfg_a; // @[PMP.scala:24:19] wire pmp_cfg_x; // @[PMP.scala:24:19] wire pmp_cfg_w; // @[PMP.scala:24:19] wire pmp_cfg_r; // @[PMP.scala:24:19] wire [29:0] pmp_addr; // @[PMP.scala:24:19] wire [31:0] pmp_mask; // @[PMP.scala:24:19] wire pmp_1_cfg_l; // @[PMP.scala:24:19] wire [1:0] pmp_1_cfg_a; // @[PMP.scala:24:19] wire pmp_1_cfg_x; // @[PMP.scala:24:19] wire pmp_1_cfg_w; // @[PMP.scala:24:19] wire pmp_1_cfg_r; // @[PMP.scala:24:19] wire [29:0] pmp_1_addr; // @[PMP.scala:24:19] wire [31:0] pmp_1_mask; // @[PMP.scala:24:19] wire pmp_2_cfg_l; // @[PMP.scala:24:19] wire [1:0] pmp_2_cfg_a; // @[PMP.scala:24:19] wire pmp_2_cfg_x; // @[PMP.scala:24:19] wire pmp_2_cfg_w; // @[PMP.scala:24:19] wire pmp_2_cfg_r; // @[PMP.scala:24:19] wire [29:0] pmp_2_addr; // @[PMP.scala:24:19] wire [31:0] pmp_2_mask; // @[PMP.scala:24:19] wire pmp_3_cfg_l; // @[PMP.scala:24:19] wire [1:0] pmp_3_cfg_a; // @[PMP.scala:24:19] wire pmp_3_cfg_x; // @[PMP.scala:24:19] wire pmp_3_cfg_w; // @[PMP.scala:24:19] wire pmp_3_cfg_r; // @[PMP.scala:24:19] wire [29:0] pmp_3_addr; // @[PMP.scala:24:19] wire [31:0] pmp_3_mask; // @[PMP.scala:24:19] wire pmp_4_cfg_l; // @[PMP.scala:24:19] wire [1:0] pmp_4_cfg_a; // @[PMP.scala:24:19] wire pmp_4_cfg_x; // @[PMP.scala:24:19] wire pmp_4_cfg_w; // @[PMP.scala:24:19] wire pmp_4_cfg_r; // @[PMP.scala:24:19] wire [29:0] pmp_4_addr; // @[PMP.scala:24:19] wire [31:0] pmp_4_mask; // @[PMP.scala:24:19] wire pmp_5_cfg_l; // @[PMP.scala:24:19] wire [1:0] pmp_5_cfg_a; // @[PMP.scala:24:19] wire pmp_5_cfg_x; // @[PMP.scala:24:19] wire pmp_5_cfg_w; // @[PMP.scala:24:19] wire pmp_5_cfg_r; // @[PMP.scala:24:19] wire [29:0] pmp_5_addr; // @[PMP.scala:24:19] wire [31:0] pmp_5_mask; // @[PMP.scala:24:19] wire pmp_6_cfg_l; // @[PMP.scala:24:19] wire [1:0] pmp_6_cfg_a; // @[PMP.scala:24:19] wire pmp_6_cfg_x; // @[PMP.scala:24:19] wire pmp_6_cfg_w; // @[PMP.scala:24:19] wire pmp_6_cfg_r; // @[PMP.scala:24:19] wire [29:0] pmp_6_addr; // @[PMP.scala:24:19] wire [31:0] pmp_6_mask; // @[PMP.scala:24:19] wire pmp_7_cfg_l; // @[PMP.scala:24:19] wire [1:0] pmp_7_cfg_a; // @[PMP.scala:24:19] wire pmp_7_cfg_x; // @[PMP.scala:24:19] wire pmp_7_cfg_w; // @[PMP.scala:24:19] wire pmp_7_cfg_r; // @[PMP.scala:24:19] wire [29:0] pmp_7_addr; // @[PMP.scala:24:19] wire [31:0] pmp_7_mask; // @[PMP.scala:24:19] wire _io_inhibit_cycle_T; // @[CSR.scala:591:40] wire _io_trace_0_valid_T_1; // @[CSR.scala:1621:32] wire [2:0] _io_trace_0_priv_T; // @[CSR.scala:1624:18] wire _io_trace_0_exception_T_1; // @[CSR.scala:1620:37] wire _io_trace_0_interrupt_T; // @[CSR.scala:1626:25] wire [63:0] cause; // @[CSR.scala:959:8] wire _io_fiom_T_6; // @[CSR.scala:631:113] wire reg_custom_read; // @[CSR.scala:799:36] wire [63:0] wdata; // @[CSR.scala:1643:39] wire reg_custom_read_1; // @[CSR.scala:799:36] wire [63:0] io_rw_rdata_0; // @[CSR.scala:377:7] wire io_decode_0_fp_illegal_0; // @[CSR.scala:377:7] wire io_decode_0_fp_csr_0; // @[CSR.scala:377:7] wire io_decode_0_read_illegal_0; // @[CSR.scala:377:7] wire io_decode_0_write_illegal_0; // @[CSR.scala:377:7] wire io_decode_0_write_flush_0; // @[CSR.scala:377:7] wire io_decode_0_system_illegal_0; // @[CSR.scala:377:7] wire io_decode_0_virtual_access_illegal_0; // @[CSR.scala:377:7] wire io_decode_0_virtual_system_illegal_0; // @[CSR.scala:377:7] wire io_status_debug_0; // @[CSR.scala:377:7] wire io_status_cease_0; // @[CSR.scala:377:7] wire io_status_wfi_0; // @[CSR.scala:377:7] wire [1:0] io_status_dprv_0; // @[CSR.scala:377:7] wire io_status_dv_0; // @[CSR.scala:377:7] wire [1:0] io_status_prv_0; // @[CSR.scala:377:7] wire io_status_v_0; // @[CSR.scala:377:7] wire io_status_mpv_0; // @[CSR.scala:377:7] wire io_status_gva_0; // @[CSR.scala:377:7] wire io_status_tsr_0; // @[CSR.scala:377:7] wire io_status_tw_0; // @[CSR.scala:377:7] wire io_status_tvm_0; // @[CSR.scala:377:7] wire io_status_mprv_0; // @[CSR.scala:377:7] wire [1:0] io_status_mpp_0; // @[CSR.scala:377:7] wire io_status_mpie_0; // @[CSR.scala:377:7] wire io_status_mie_0; // @[CSR.scala:377:7] wire io_hstatus_spvp; // @[CSR.scala:377:7] wire io_hstatus_spv; // @[CSR.scala:377:7] wire io_hstatus_gva; // @[CSR.scala:377:7] wire io_gstatus_spp; // @[CSR.scala:377:7] wire io_gstatus_spie; // @[CSR.scala:377:7] wire io_gstatus_sie; // @[CSR.scala:377:7] wire [3:0] io_ptbr_mode_0; // @[CSR.scala:377:7] wire [43:0] io_ptbr_ppn_0; // @[CSR.scala:377:7] wire io_pmp_0_cfg_l_0; // @[CSR.scala:377:7] wire [1:0] io_pmp_0_cfg_a_0; // @[CSR.scala:377:7] wire io_pmp_0_cfg_x_0; // @[CSR.scala:377:7] wire io_pmp_0_cfg_w_0; // @[CSR.scala:377:7] wire io_pmp_0_cfg_r_0; // @[CSR.scala:377:7] wire [29:0] io_pmp_0_addr_0; // @[CSR.scala:377:7] wire [31:0] io_pmp_0_mask_0; // @[CSR.scala:377:7] wire io_pmp_1_cfg_l_0; // @[CSR.scala:377:7] wire [1:0] io_pmp_1_cfg_a_0; // @[CSR.scala:377:7] wire io_pmp_1_cfg_x_0; // @[CSR.scala:377:7] wire io_pmp_1_cfg_w_0; // @[CSR.scala:377:7] wire io_pmp_1_cfg_r_0; // @[CSR.scala:377:7] wire [29:0] io_pmp_1_addr_0; // @[CSR.scala:377:7] wire [31:0] io_pmp_1_mask_0; // @[CSR.scala:377:7] wire io_pmp_2_cfg_l_0; // @[CSR.scala:377:7] wire [1:0] io_pmp_2_cfg_a_0; // @[CSR.scala:377:7] wire io_pmp_2_cfg_x_0; // @[CSR.scala:377:7] wire io_pmp_2_cfg_w_0; // @[CSR.scala:377:7] wire io_pmp_2_cfg_r_0; // @[CSR.scala:377:7] wire [29:0] io_pmp_2_addr_0; // @[CSR.scala:377:7] wire [31:0] io_pmp_2_mask_0; // @[CSR.scala:377:7] wire io_pmp_3_cfg_l_0; // @[CSR.scala:377:7] wire [1:0] io_pmp_3_cfg_a_0; // @[CSR.scala:377:7] wire io_pmp_3_cfg_x_0; // @[CSR.scala:377:7] wire io_pmp_3_cfg_w_0; // @[CSR.scala:377:7] wire io_pmp_3_cfg_r_0; // @[CSR.scala:377:7] wire [29:0] io_pmp_3_addr_0; // @[CSR.scala:377:7] wire [31:0] io_pmp_3_mask_0; // @[CSR.scala:377:7] wire io_pmp_4_cfg_l_0; // @[CSR.scala:377:7] wire [1:0] io_pmp_4_cfg_a_0; // @[CSR.scala:377:7] wire io_pmp_4_cfg_x_0; // @[CSR.scala:377:7] wire io_pmp_4_cfg_w_0; // @[CSR.scala:377:7] wire io_pmp_4_cfg_r_0; // @[CSR.scala:377:7] wire [29:0] io_pmp_4_addr_0; // @[CSR.scala:377:7] wire [31:0] io_pmp_4_mask_0; // @[CSR.scala:377:7] wire io_pmp_5_cfg_l_0; // @[CSR.scala:377:7] wire [1:0] io_pmp_5_cfg_a_0; // @[CSR.scala:377:7] wire io_pmp_5_cfg_x_0; // @[CSR.scala:377:7] wire io_pmp_5_cfg_w_0; // @[CSR.scala:377:7] wire io_pmp_5_cfg_r_0; // @[CSR.scala:377:7] wire [29:0] io_pmp_5_addr_0; // @[CSR.scala:377:7] wire [31:0] io_pmp_5_mask_0; // @[CSR.scala:377:7] wire io_pmp_6_cfg_l_0; // @[CSR.scala:377:7] wire [1:0] io_pmp_6_cfg_a_0; // @[CSR.scala:377:7] wire io_pmp_6_cfg_x_0; // @[CSR.scala:377:7] wire io_pmp_6_cfg_w_0; // @[CSR.scala:377:7] wire io_pmp_6_cfg_r_0; // @[CSR.scala:377:7] wire [29:0] io_pmp_6_addr_0; // @[CSR.scala:377:7] wire [31:0] io_pmp_6_mask_0; // @[CSR.scala:377:7] wire io_pmp_7_cfg_l_0; // @[CSR.scala:377:7] wire [1:0] io_pmp_7_cfg_a_0; // @[CSR.scala:377:7] wire io_pmp_7_cfg_x_0; // @[CSR.scala:377:7] wire io_pmp_7_cfg_w_0; // @[CSR.scala:377:7] wire io_pmp_7_cfg_r_0; // @[CSR.scala:377:7] wire [29:0] io_pmp_7_addr_0; // @[CSR.scala:377:7] wire [31:0] io_pmp_7_mask_0; // @[CSR.scala:377:7] wire [63:0] io_counters_0_eventSel_0; // @[CSR.scala:377:7] wire [63:0] io_counters_1_eventSel_0; // @[CSR.scala:377:7] wire io_trace_0_valid; // @[CSR.scala:377:7] wire [2:0] io_trace_0_priv; // @[CSR.scala:377:7] wire io_trace_0_exception; // @[CSR.scala:377:7] wire io_trace_0_interrupt; // @[CSR.scala:377:7] wire [63:0] io_trace_0_cause; // @[CSR.scala:377:7] wire io_customCSRs_0_ren_0; // @[CSR.scala:377:7] wire io_customCSRs_0_wen_0; // @[CSR.scala:377:7] wire [63:0] io_customCSRs_0_wdata_0; // @[CSR.scala:377:7] wire [63:0] io_customCSRs_0_value_0; // @[CSR.scala:377:7] wire io_customCSRs_1_ren_0; // @[CSR.scala:377:7] wire io_customCSRs_1_wen_0; // @[CSR.scala:377:7] wire [63:0] io_customCSRs_1_wdata_0; // @[CSR.scala:377:7] wire [63:0] io_customCSRs_1_value_0; // @[CSR.scala:377:7] wire io_csr_stall_0; // @[CSR.scala:377:7] wire io_eret; // @[CSR.scala:377:7] wire io_singleStep_0; // @[CSR.scala:377:7] wire [39:0] io_evec_0; // @[CSR.scala:377:7] wire [63:0] io_time_0; // @[CSR.scala:377:7] wire [2:0] io_fcsr_rm_0; // @[CSR.scala:377:7] wire io_interrupt_0; // @[CSR.scala:377:7] wire [63:0] io_interrupt_cause_0; // @[CSR.scala:377:7] wire [31:0] io_csrw_counter; // @[CSR.scala:377:7] wire io_inhibit_cycle; // @[CSR.scala:377:7] wire io_fiom; // @[CSR.scala:377:7] reg [1:0] reg_mstatus_prv; // @[CSR.scala:395:28] assign io_status_prv_0 = reg_mstatus_prv; // @[CSR.scala:377:7, :395:28] reg reg_mstatus_v; // @[CSR.scala:395:28] assign io_status_v_0 = reg_mstatus_v; // @[CSR.scala:377:7, :395:28] wire _io_decode_0_rocc_illegal_T_2 = reg_mstatus_v; // @[CSR.scala:395:28, :919:66] reg reg_mstatus_mpv; // @[CSR.scala:395:28] assign io_status_mpv_0 = reg_mstatus_mpv; // @[CSR.scala:377:7, :395:28] reg reg_mstatus_gva; // @[CSR.scala:395:28] assign io_status_gva_0 = reg_mstatus_gva; // @[CSR.scala:377:7, :395:28] reg reg_mstatus_tsr; // @[CSR.scala:395:28] assign io_status_tsr_0 = reg_mstatus_tsr; // @[CSR.scala:377:7, :395:28] reg reg_mstatus_tw; // @[CSR.scala:395:28] assign io_status_tw_0 = reg_mstatus_tw; // @[CSR.scala:377:7, :395:28] reg reg_mstatus_tvm; // @[CSR.scala:395:28] assign io_status_tvm_0 = reg_mstatus_tvm; // @[CSR.scala:377:7, :395:28] reg reg_mstatus_mxr; // @[CSR.scala:395:28] assign io_status_mxr_0 = reg_mstatus_mxr; // @[CSR.scala:377:7, :395:28] reg reg_mstatus_sum; // @[CSR.scala:395:28] assign io_status_sum_0 = reg_mstatus_sum; // @[CSR.scala:377:7, :395:28] reg reg_mstatus_mprv; // @[CSR.scala:395:28] assign io_status_mprv_0 = reg_mstatus_mprv; // @[CSR.scala:377:7, :395:28] reg [1:0] reg_mstatus_fs; // @[CSR.scala:395:28] assign io_status_fs_0 = reg_mstatus_fs; // @[CSR.scala:377:7, :395:28] reg [1:0] reg_mstatus_mpp; // @[CSR.scala:395:28] assign io_status_mpp_0 = reg_mstatus_mpp; // @[CSR.scala:377:7, :395:28] reg reg_mstatus_spp; // @[CSR.scala:395:28] assign io_status_spp_0 = reg_mstatus_spp; // @[CSR.scala:377:7, :395:28] reg reg_mstatus_mpie; // @[CSR.scala:395:28] assign io_status_mpie_0 = reg_mstatus_mpie; // @[CSR.scala:377:7, :395:28] reg reg_mstatus_spie; // @[CSR.scala:395:28] assign io_status_spie_0 = reg_mstatus_spie; // @[CSR.scala:377:7, :395:28] reg reg_mstatus_mie; // @[CSR.scala:395:28] assign io_status_mie_0 = reg_mstatus_mie; // @[CSR.scala:377:7, :395:28] reg reg_mstatus_sie; // @[CSR.scala:395:28] assign io_status_sie_0 = reg_mstatus_sie; // @[CSR.scala:377:7, :395:28] wire [1:0] new_prv; // @[CSR.scala:397:28] wire _reg_mstatus_prv_T = new_prv == 2'h2; // @[CSR.scala:397:28, :1647:35] wire [1:0] _reg_mstatus_prv_T_1 = _reg_mstatus_prv_T ? 2'h0 : new_prv; // @[CSR.scala:397:28, :1647:{29,35}] reg reg_dcsr_ebreakm; // @[CSR.scala:403:25] reg reg_dcsr_ebreaks; // @[CSR.scala:403:25] reg reg_dcsr_ebreaku; // @[CSR.scala:403:25] reg [2:0] reg_dcsr_cause; // @[CSR.scala:403:25] reg reg_dcsr_v; // @[CSR.scala:403:25] reg reg_dcsr_step; // @[CSR.scala:403:25] reg [1:0] reg_dcsr_prv; // @[CSR.scala:403:25] reg reg_debug; // @[CSR.scala:482:26] assign io_status_debug_0 = reg_debug; // @[CSR.scala:377:7, :482:26] reg [39:0] reg_dpc; // @[CSR.scala:483:20] reg [63:0] reg_dscratch0; // @[CSR.scala:484:26] reg reg_singleStepped; // @[CSR.scala:486:30] reg reg_pmp_0_cfg_l; // @[CSR.scala:493:20] assign pmp_cfg_l = reg_pmp_0_cfg_l; // @[PMP.scala:24:19] reg [1:0] reg_pmp_0_cfg_a; // @[CSR.scala:493:20] assign pmp_cfg_a = reg_pmp_0_cfg_a; // @[PMP.scala:24:19] reg reg_pmp_0_cfg_x; // @[CSR.scala:493:20] assign pmp_cfg_x = reg_pmp_0_cfg_x; // @[PMP.scala:24:19] reg reg_pmp_0_cfg_w; // @[CSR.scala:493:20] assign pmp_cfg_w = reg_pmp_0_cfg_w; // @[PMP.scala:24:19] reg reg_pmp_0_cfg_r; // @[CSR.scala:493:20] assign pmp_cfg_r = reg_pmp_0_cfg_r; // @[PMP.scala:24:19] reg [29:0] reg_pmp_0_addr; // @[CSR.scala:493:20] assign pmp_addr = reg_pmp_0_addr; // @[PMP.scala:24:19] reg reg_pmp_1_cfg_l; // @[CSR.scala:493:20] assign pmp_1_cfg_l = reg_pmp_1_cfg_l; // @[PMP.scala:24:19] reg [1:0] reg_pmp_1_cfg_a; // @[CSR.scala:493:20] assign pmp_1_cfg_a = reg_pmp_1_cfg_a; // @[PMP.scala:24:19] reg reg_pmp_1_cfg_x; // @[CSR.scala:493:20] assign pmp_1_cfg_x = reg_pmp_1_cfg_x; // @[PMP.scala:24:19] reg reg_pmp_1_cfg_w; // @[CSR.scala:493:20] assign pmp_1_cfg_w = reg_pmp_1_cfg_w; // @[PMP.scala:24:19] reg reg_pmp_1_cfg_r; // @[CSR.scala:493:20] assign pmp_1_cfg_r = reg_pmp_1_cfg_r; // @[PMP.scala:24:19] reg [29:0] reg_pmp_1_addr; // @[CSR.scala:493:20] assign pmp_1_addr = reg_pmp_1_addr; // @[PMP.scala:24:19] reg reg_pmp_2_cfg_l; // @[CSR.scala:493:20] assign pmp_2_cfg_l = reg_pmp_2_cfg_l; // @[PMP.scala:24:19] reg [1:0] reg_pmp_2_cfg_a; // @[CSR.scala:493:20] assign pmp_2_cfg_a = reg_pmp_2_cfg_a; // @[PMP.scala:24:19] reg reg_pmp_2_cfg_x; // @[CSR.scala:493:20] assign pmp_2_cfg_x = reg_pmp_2_cfg_x; // @[PMP.scala:24:19] reg reg_pmp_2_cfg_w; // @[CSR.scala:493:20] assign pmp_2_cfg_w = reg_pmp_2_cfg_w; // @[PMP.scala:24:19] reg reg_pmp_2_cfg_r; // @[CSR.scala:493:20] assign pmp_2_cfg_r = reg_pmp_2_cfg_r; // @[PMP.scala:24:19] reg [29:0] reg_pmp_2_addr; // @[CSR.scala:493:20] assign pmp_2_addr = reg_pmp_2_addr; // @[PMP.scala:24:19] reg reg_pmp_3_cfg_l; // @[CSR.scala:493:20] assign pmp_3_cfg_l = reg_pmp_3_cfg_l; // @[PMP.scala:24:19] reg [1:0] reg_pmp_3_cfg_a; // @[CSR.scala:493:20] assign pmp_3_cfg_a = reg_pmp_3_cfg_a; // @[PMP.scala:24:19] reg reg_pmp_3_cfg_x; // @[CSR.scala:493:20] assign pmp_3_cfg_x = reg_pmp_3_cfg_x; // @[PMP.scala:24:19] reg reg_pmp_3_cfg_w; // @[CSR.scala:493:20] assign pmp_3_cfg_w = reg_pmp_3_cfg_w; // @[PMP.scala:24:19] reg reg_pmp_3_cfg_r; // @[CSR.scala:493:20] assign pmp_3_cfg_r = reg_pmp_3_cfg_r; // @[PMP.scala:24:19] reg [29:0] reg_pmp_3_addr; // @[CSR.scala:493:20] assign pmp_3_addr = reg_pmp_3_addr; // @[PMP.scala:24:19] reg reg_pmp_4_cfg_l; // @[CSR.scala:493:20] assign pmp_4_cfg_l = reg_pmp_4_cfg_l; // @[PMP.scala:24:19] reg [1:0] reg_pmp_4_cfg_a; // @[CSR.scala:493:20] assign pmp_4_cfg_a = reg_pmp_4_cfg_a; // @[PMP.scala:24:19] reg reg_pmp_4_cfg_x; // @[CSR.scala:493:20] assign pmp_4_cfg_x = reg_pmp_4_cfg_x; // @[PMP.scala:24:19] reg reg_pmp_4_cfg_w; // @[CSR.scala:493:20] assign pmp_4_cfg_w = reg_pmp_4_cfg_w; // @[PMP.scala:24:19] reg reg_pmp_4_cfg_r; // @[CSR.scala:493:20] assign pmp_4_cfg_r = reg_pmp_4_cfg_r; // @[PMP.scala:24:19] reg [29:0] reg_pmp_4_addr; // @[CSR.scala:493:20] assign pmp_4_addr = reg_pmp_4_addr; // @[PMP.scala:24:19] reg reg_pmp_5_cfg_l; // @[CSR.scala:493:20] assign pmp_5_cfg_l = reg_pmp_5_cfg_l; // @[PMP.scala:24:19] reg [1:0] reg_pmp_5_cfg_a; // @[CSR.scala:493:20] assign pmp_5_cfg_a = reg_pmp_5_cfg_a; // @[PMP.scala:24:19] reg reg_pmp_5_cfg_x; // @[CSR.scala:493:20] assign pmp_5_cfg_x = reg_pmp_5_cfg_x; // @[PMP.scala:24:19] reg reg_pmp_5_cfg_w; // @[CSR.scala:493:20] assign pmp_5_cfg_w = reg_pmp_5_cfg_w; // @[PMP.scala:24:19] reg reg_pmp_5_cfg_r; // @[CSR.scala:493:20] assign pmp_5_cfg_r = reg_pmp_5_cfg_r; // @[PMP.scala:24:19] reg [29:0] reg_pmp_5_addr; // @[CSR.scala:493:20] assign pmp_5_addr = reg_pmp_5_addr; // @[PMP.scala:24:19] reg reg_pmp_6_cfg_l; // @[CSR.scala:493:20] assign pmp_6_cfg_l = reg_pmp_6_cfg_l; // @[PMP.scala:24:19] reg [1:0] reg_pmp_6_cfg_a; // @[CSR.scala:493:20] assign pmp_6_cfg_a = reg_pmp_6_cfg_a; // @[PMP.scala:24:19] reg reg_pmp_6_cfg_x; // @[CSR.scala:493:20] assign pmp_6_cfg_x = reg_pmp_6_cfg_x; // @[PMP.scala:24:19] reg reg_pmp_6_cfg_w; // @[CSR.scala:493:20] assign pmp_6_cfg_w = reg_pmp_6_cfg_w; // @[PMP.scala:24:19] reg reg_pmp_6_cfg_r; // @[CSR.scala:493:20] assign pmp_6_cfg_r = reg_pmp_6_cfg_r; // @[PMP.scala:24:19] reg [29:0] reg_pmp_6_addr; // @[CSR.scala:493:20] assign pmp_6_addr = reg_pmp_6_addr; // @[PMP.scala:24:19] reg reg_pmp_7_cfg_l; // @[CSR.scala:493:20] assign pmp_7_cfg_l = reg_pmp_7_cfg_l; // @[PMP.scala:24:19] reg [1:0] reg_pmp_7_cfg_a; // @[CSR.scala:493:20] assign pmp_7_cfg_a = reg_pmp_7_cfg_a; // @[PMP.scala:24:19] reg reg_pmp_7_cfg_x; // @[CSR.scala:493:20] assign pmp_7_cfg_x = reg_pmp_7_cfg_x; // @[PMP.scala:24:19] reg reg_pmp_7_cfg_w; // @[CSR.scala:493:20] assign pmp_7_cfg_w = reg_pmp_7_cfg_w; // @[PMP.scala:24:19] reg reg_pmp_7_cfg_r; // @[CSR.scala:493:20] assign pmp_7_cfg_r = reg_pmp_7_cfg_r; // @[PMP.scala:24:19] reg [29:0] reg_pmp_7_addr; // @[CSR.scala:493:20] assign pmp_7_addr = reg_pmp_7_addr; // @[PMP.scala:24:19] reg [63:0] reg_mie; // @[CSR.scala:495:20] reg [63:0] reg_mideleg; // @[CSR.scala:497:18] wire [63:0] read_mideleg = {54'h0, reg_mideleg[9:1] & 9'h111, 1'h0}; // @[CSR.scala:497:18, :498:{14,38,61}] reg [63:0] reg_medeleg; // @[CSR.scala:501:18] wire [63:0] read_medeleg = {48'h0, reg_medeleg[15:0] & 16'hB15D}; // @[CSR.scala:501:18, :502:{14,38}] reg reg_mip_seip; // @[CSR.scala:504:20] reg reg_mip_stip; // @[CSR.scala:504:20] wire mip_stip = reg_mip_stip; // @[CSR.scala:504:20, :600:24] reg reg_mip_ssip; // @[CSR.scala:504:20] wire mip_ssip = reg_mip_ssip; // @[CSR.scala:504:20, :600:24] reg [39:0] reg_mepc; // @[CSR.scala:505:21] reg [63:0] reg_mcause; // @[CSR.scala:506:27] reg [39:0] reg_mtval; // @[CSR.scala:507:22] reg [39:0] reg_mtval2; // @[CSR.scala:508:23] reg [63:0] reg_mscratch; // @[CSR.scala:509:25] reg [31:0] reg_mtvec; // @[CSR.scala:512:31] reg reg_menvcfg_fiom; // @[CSR.scala:525:28] reg reg_senvcfg_fiom; // @[CSR.scala:526:28] reg [31:0] reg_mcounteren; // @[CSR.scala:531:18] wire [31:0] read_mcounteren = {27'h0, reg_mcounteren[4:0]}; // @[CSR.scala:531:18, :532:{14,32}] reg [31:0] reg_scounteren; // @[CSR.scala:535:18] wire [31:0] read_scounteren = {27'h0, reg_scounteren[4:0]}; // @[CSR.scala:535:18, :536:{14,38}] reg reg_hstatus_spvp; // @[CSR.scala:552:28] assign io_hstatus_spvp = reg_hstatus_spvp; // @[CSR.scala:377:7, :552:28] reg reg_hstatus_spv; // @[CSR.scala:552:28] assign io_hstatus_spv = reg_hstatus_spv; // @[CSR.scala:377:7, :552:28] reg reg_hstatus_gva; // @[CSR.scala:552:28] assign io_hstatus_gva = reg_hstatus_gva; // @[CSR.scala:377:7, :552:28] reg [39:0] reg_htval; // @[CSR.scala:554:22] wire [1:0] _GEN = {reg_mip_ssip, 1'h0}; // @[CSR.scala:504:20, :555:27] wire [1:0] read_hvip_lo_lo_lo; // @[CSR.scala:555:27] assign read_hvip_lo_lo_lo = _GEN; // @[CSR.scala:555:27] wire [1:0] new_mip_lo_lo_lo; // @[CSR.scala:1271:59] assign new_mip_lo_lo_lo = _GEN; // @[CSR.scala:555:27, :1271:59] wire [3:0] read_hvip_lo_lo = {read_hvip_lo_lo_hi, read_hvip_lo_lo_lo}; // @[CSR.scala:555:27] wire [1:0] _GEN_0 = {reg_mip_stip, 1'h0}; // @[CSR.scala:504:20, :555:27] wire [1:0] read_hvip_lo_hi_lo; // @[CSR.scala:555:27] assign read_hvip_lo_hi_lo = _GEN_0; // @[CSR.scala:555:27] wire [1:0] new_mip_lo_hi_lo; // @[CSR.scala:1271:59] assign new_mip_lo_hi_lo = _GEN_0; // @[CSR.scala:555:27, :1271:59] wire [3:0] read_hvip_lo_hi = {read_hvip_lo_hi_hi, read_hvip_lo_hi_lo}; // @[CSR.scala:555:27] wire [7:0] read_hvip_lo = {read_hvip_lo_hi, read_hvip_lo_lo}; // @[CSR.scala:555:27] wire [1:0] _GEN_1 = {reg_mip_seip, 1'h0}; // @[CSR.scala:504:20, :555:27] wire [1:0] read_hvip_hi_lo_lo; // @[CSR.scala:555:27] assign read_hvip_hi_lo_lo = _GEN_1; // @[CSR.scala:555:27] wire [1:0] new_mip_hi_lo_lo; // @[CSR.scala:1271:59] assign new_mip_hi_lo_lo = _GEN_1; // @[CSR.scala:555:27, :1271:59] wire [3:0] read_hvip_hi_lo = {read_hvip_hi_lo_hi, read_hvip_hi_lo_lo}; // @[CSR.scala:555:27] wire [1:0] read_hvip_hi_hi_hi = {read_hvip_hi_hi_hi_hi, 1'h0}; // @[CSR.scala:555:27] wire [3:0] read_hvip_hi_hi = {read_hvip_hi_hi_hi, read_hvip_hi_hi_lo}; // @[CSR.scala:555:27] wire [7:0] read_hvip_hi = {read_hvip_hi_hi, read_hvip_hi_lo}; // @[CSR.scala:555:27] wire [15:0] _read_hvip_T = {read_hvip_hi, read_hvip_lo}; // @[CSR.scala:555:27] reg reg_vsstatus_spp; // @[CSR.scala:562:25] assign io_gstatus_spp = reg_vsstatus_spp; // @[CSR.scala:377:7, :562:25] reg reg_vsstatus_spie; // @[CSR.scala:562:25] assign io_gstatus_spie = reg_vsstatus_spie; // @[CSR.scala:377:7, :562:25] reg reg_vsstatus_sie; // @[CSR.scala:562:25] assign io_gstatus_sie = reg_vsstatus_sie; // @[CSR.scala:377:7, :562:25] reg [39:0] reg_vsepc; // @[CSR.scala:564:22] reg [63:0] reg_vscause; // @[CSR.scala:565:24] reg [39:0] reg_vstval; // @[CSR.scala:566:23] reg [39:0] reg_sepc; // @[CSR.scala:569:21] reg [63:0] reg_scause; // @[CSR.scala:570:23] reg [39:0] reg_stval; // @[CSR.scala:571:22] reg [63:0] reg_sscratch; // @[CSR.scala:572:25] reg [38:0] reg_stvec; // @[CSR.scala:573:22] reg [3:0] reg_satp_mode; // @[CSR.scala:574:21] assign io_ptbr_mode_0 = reg_satp_mode; // @[CSR.scala:377:7, :574:21] reg [43:0] reg_satp_ppn; // @[CSR.scala:574:21] assign io_ptbr_ppn_0 = reg_satp_ppn; // @[CSR.scala:377:7, :574:21] reg reg_wfi; // @[CSR.scala:575:54] assign io_status_wfi_0 = reg_wfi; // @[CSR.scala:377:7, :575:54] reg [4:0] reg_fflags; // @[CSR.scala:577:23] reg [2:0] reg_frm; // @[CSR.scala:578:20] assign io_fcsr_rm_0 = reg_frm; // @[CSR.scala:377:7, :578:20] reg reg_mtinst_read_pseudo; // @[CSR.scala:584:35] reg reg_htinst_read_pseudo; // @[CSR.scala:585:35] wire [1:0] hi_4 = {2{reg_mtinst_read_pseudo}}; // @[CSR.scala:584:35, :588:103] wire [13:0] read_mtinst = {hi_4, 12'h0}; // @[CSR.scala:588:103] wire [1:0] hi_5 = {2{reg_htinst_read_pseudo}}; // @[CSR.scala:585:35, :588:103] wire [13:0] read_htinst = {hi_5, 12'h0}; // @[CSR.scala:588:103] reg [4:0] reg_mcountinhibit; // @[CSR.scala:590:34] assign _io_inhibit_cycle_T = reg_mcountinhibit[0]; // @[CSR.scala:590:34, :591:40] wire x11 = reg_mcountinhibit[0]; // @[CSR.scala:590:34, :591:40, :594:98] assign io_inhibit_cycle = _io_inhibit_cycle_T; // @[CSR.scala:377:7, :591:40] wire x3 = reg_mcountinhibit[2]; // @[CSR.scala:590:34, :592:75] reg [5:0] small_0; // @[Counters.scala:45:41] wire [6:0] nextSmall = {1'h0, small_0} + {6'h0, io_retire_0}; // @[Counters.scala:45:41, :46:33] wire _large_T_1 = ~x3; // @[Counters.scala:47:9, :51:36] reg [57:0] large_0; // @[Counters.scala:50:31] wire _large_T = nextSmall[6]; // @[Counters.scala:46:33, :51:20] wire _large_T_2 = _large_T & _large_T_1; // @[Counters.scala:51:{20,33,36}] wire [58:0] _large_r_T = {1'h0, large_0} + 59'h1; // @[Counters.scala:50:31, :51:55] wire [57:0] _large_r_T_1 = _large_r_T[57:0]; // @[Counters.scala:51:55] wire [63:0] value = {large_0, small_0}; // @[Counters.scala:45:41, :50:31, :55:30] wire x10 = ~io_csr_stall_0; // @[CSR.scala:377:7, :594:56] reg [5:0] small_1; // @[Counters.scala:45:41] wire [6:0] nextSmall_1 = {1'h0, small_1} + {6'h0, x10}; // @[Counters.scala:45:41, :46:33] wire _large_T_4 = ~x11; // @[Counters.scala:47:9, :51:36] reg [57:0] large_1; // @[Counters.scala:50:31] wire _large_T_3 = nextSmall_1[6]; // @[Counters.scala:46:33, :51:20] wire _large_T_5 = _large_T_3 & _large_T_4; // @[Counters.scala:51:{20,33,36}] wire [58:0] _large_r_T_2 = {1'h0, large_1} + 59'h1; // @[Counters.scala:50:31, :51:55] wire [57:0] _large_r_T_3 = _large_r_T_2[57:0]; // @[Counters.scala:51:55] assign value_1 = {large_1, small_1}; // @[Counters.scala:45:41, :50:31, :55:30] assign io_time_0 = value_1; // @[Counters.scala:55:30] reg [63:0] reg_hpmevent_0; // @[CSR.scala:595:50] assign io_counters_0_eventSel_0 = reg_hpmevent_0; // @[CSR.scala:377:7, :595:50] reg [63:0] reg_hpmevent_1; // @[CSR.scala:595:50] assign io_counters_1_eventSel_0 = reg_hpmevent_1; // @[CSR.scala:377:7, :595:50] reg [5:0] small_2; // @[Counters.scala:45:69] wire [6:0] nextSmall_2 = {1'h0, small_2} + {6'h0, io_counters_0_inc_0}; // @[Counters.scala:45:69, :46:33] wire _large_T_7 = ~(reg_mcountinhibit[3]); // @[Counters.scala:47:9, :51:36] reg [33:0] large_2; // @[Counters.scala:50:69] wire _large_T_6 = nextSmall_2[6]; // @[Counters.scala:46:33, :51:20] wire _large_T_8 = _large_T_6 & _large_T_7; // @[Counters.scala:51:{20,33,36}] wire [34:0] _large_r_T_4 = {1'h0, large_2} + 35'h1; // @[Counters.scala:50:69, :51:55] wire [33:0] _large_r_T_5 = _large_r_T_4[33:0]; // @[Counters.scala:51:55] wire [39:0] value_2 = {large_2, small_2}; // @[Counters.scala:45:69, :50:69, :55:30] reg [5:0] small_3; // @[Counters.scala:45:69] wire [6:0] nextSmall_3 = {1'h0, small_3} + {6'h0, io_counters_1_inc_0}; // @[Counters.scala:45:69, :46:33] wire _large_T_10 = ~(reg_mcountinhibit[4]); // @[Counters.scala:47:9, :51:36] reg [33:0] large_3; // @[Counters.scala:50:69] wire _large_T_9 = nextSmall_3[6]; // @[Counters.scala:46:33, :51:20] wire _large_T_11 = _large_T_9 & _large_T_10; // @[Counters.scala:51:{20,33,36}] wire [34:0] _large_r_T_6 = {1'h0, large_3} + 35'h1; // @[Counters.scala:50:69, :51:55] wire [33:0] _large_r_T_7 = _large_r_T_6[33:0]; // @[Counters.scala:51:55] wire [39:0] value_3 = {large_3, small_3}; // @[Counters.scala:45:69, :50:69, :55:30] wire read_mip_hi_hi_hi_hi = mip_zero1; // @[CSR.scala:600:24, :610:22] wire _mip_seip_T; // @[CSR.scala:606:57] wire mip_seip; // @[CSR.scala:600:24] assign _mip_seip_T = reg_mip_seip | io_interrupts_seip_0; // @[CSR.scala:377:7, :504:20, :606:57] assign mip_seip = _mip_seip_T; // @[CSR.scala:600:24, :606:57] wire [1:0] read_mip_lo_lo_lo = {mip_ssip, mip_usip}; // @[CSR.scala:600:24, :610:22] wire [1:0] read_mip_lo_lo_hi = {mip_msip, mip_vssip}; // @[CSR.scala:600:24, :610:22] wire [3:0] read_mip_lo_lo = {read_mip_lo_lo_hi, read_mip_lo_lo_lo}; // @[CSR.scala:610:22] wire [1:0] read_mip_lo_hi_lo = {mip_stip, mip_utip}; // @[CSR.scala:600:24, :610:22] wire [1:0] read_mip_lo_hi_hi = {mip_mtip, mip_vstip}; // @[CSR.scala:600:24, :610:22] wire [3:0] read_mip_lo_hi = {read_mip_lo_hi_hi, read_mip_lo_hi_lo}; // @[CSR.scala:610:22] wire [7:0] read_mip_lo = {read_mip_lo_hi, read_mip_lo_lo}; // @[CSR.scala:610:22] wire [1:0] read_mip_hi_lo_lo = {mip_seip, mip_ueip}; // @[CSR.scala:600:24, :610:22] wire [1:0] read_mip_hi_lo_hi = {mip_meip, mip_vseip}; // @[CSR.scala:600:24, :610:22] wire [3:0] read_mip_hi_lo = {read_mip_hi_lo_hi, read_mip_hi_lo_lo}; // @[CSR.scala:610:22] wire [1:0] read_mip_hi_hi_lo = {1'h0, mip_sgeip}; // @[CSR.scala:600:24, :610:22] wire [1:0] read_mip_hi_hi_hi = {read_mip_hi_hi_hi_hi, mip_debug}; // @[CSR.scala:600:24, :610:22] wire [3:0] read_mip_hi_hi = {read_mip_hi_hi_hi, read_mip_hi_hi_lo}; // @[CSR.scala:610:22] wire [7:0] read_mip_hi = {read_mip_hi_hi, read_mip_hi_lo}; // @[CSR.scala:610:22] wire [15:0] _read_mip_T = {read_mip_hi, read_mip_lo}; // @[CSR.scala:610:22] wire [15:0] read_mip = _read_mip_T & 16'hAAA; // @[CSR.scala:610:{22,29}] wire [63:0] _pending_interrupts_T = {48'h0, reg_mie[15:0] & read_mip}; // @[CSR.scala:495:20, :610:29, :614:56] wire [63:0] pending_interrupts = _pending_interrupts_T; // @[CSR.scala:614:{44,56}] wire [14:0] d_interrupts = {io_interrupts_debug_0, 14'h0}; // @[CSR.scala:377:7, :615:42] wire _allow_wfi_T = reg_mstatus_prv[1]; // @[CSR.scala:395:28, :620:51, :906:61] wire _allow_sfence_vma_T = reg_mstatus_prv[1]; // @[CSR.scala:395:28, :620:51, :907:60] wire _allow_sret_T = reg_mstatus_prv[1]; // @[CSR.scala:395:28, :620:51, :910:62] wire _allow_counter_T = reg_mstatus_prv[1]; // @[CSR.scala:395:28, :620:51, :912:42] wire _m_interrupts_T = ~(reg_mstatus_prv[1]); // @[CSR.scala:395:28, :620:51] wire _m_interrupts_T_1 = _m_interrupts_T | reg_mstatus_mie; // @[CSR.scala:395:28, :620:{51,62}] wire _m_interrupts_T_2 = _m_interrupts_T_1; // @[CSR.scala:620:{31,62}] wire [63:0] _m_interrupts_T_3 = ~pending_interrupts; // @[CSR.scala:614:44, :620:85] wire [63:0] _m_interrupts_T_4 = _m_interrupts_T_3 | read_mideleg; // @[CSR.scala:498:14, :620:{85,105}] wire [63:0] _m_interrupts_T_5 = ~_m_interrupts_T_4; // @[CSR.scala:620:{83,105}] wire [63:0] m_interrupts = _m_interrupts_T_2 ? _m_interrupts_T_5 : 64'h0; // @[CSR.scala:620:{25,31,83}] wire _GEN_2 = reg_mstatus_prv == 2'h0; // @[CSR.scala:395:28, :621:68] wire _s_interrupts_T; // @[CSR.scala:621:68] assign _s_interrupts_T = _GEN_2; // @[CSR.scala:621:68] wire _vs_interrupts_T; // @[CSR.scala:622:70] assign _vs_interrupts_T = _GEN_2; // @[CSR.scala:621:68, :622:70] wire _io_fiom_T_2; // @[CSR.scala:631:82] assign _io_fiom_T_2 = _GEN_2; // @[CSR.scala:621:68, :631:82] wire _s_interrupts_T_1 = reg_mstatus_v | _s_interrupts_T; // @[CSR.scala:395:28, :621:{49,68}] wire _GEN_3 = reg_mstatus_prv == 2'h1; // @[CSR.scala:395:28, :621:98] wire _s_interrupts_T_2; // @[CSR.scala:621:98] assign _s_interrupts_T_2 = _GEN_3; // @[CSR.scala:621:98] wire _vs_interrupts_T_1; // @[CSR.scala:622:99] assign _vs_interrupts_T_1 = _GEN_3; // @[CSR.scala:621:98, :622:99] wire _csr_addr_legal_T_4; // @[CSR.scala:921:62] assign _csr_addr_legal_T_4 = _GEN_3; // @[CSR.scala:621:98, :921:62] wire _s_interrupts_T_3 = _s_interrupts_T_2 & reg_mstatus_sie; // @[CSR.scala:395:28, :621:{98,110}] wire _s_interrupts_T_4 = _s_interrupts_T_1 | _s_interrupts_T_3; // @[CSR.scala:621:{49,78,110}] wire _s_interrupts_T_5 = _s_interrupts_T_4; // @[CSR.scala:621:{31,78}] wire [63:0] _s_interrupts_T_6 = pending_interrupts & read_mideleg; // @[CSR.scala:498:14, :614:44, :621:151] wire [63:0] _s_interrupts_T_8 = _s_interrupts_T_6; // @[CSR.scala:621:{151,166}] wire [63:0] s_interrupts = _s_interrupts_T_5 ? _s_interrupts_T_8 : 64'h0; // @[CSR.scala:621:{25,31,166}] wire _vs_interrupts_T_2 = _vs_interrupts_T_1 & reg_vsstatus_sie; // @[CSR.scala:562:25, :622:{99,111}] wire _vs_interrupts_T_3 = _vs_interrupts_T | _vs_interrupts_T_2; // @[CSR.scala:622:{70,80,111}] wire _vs_interrupts_T_4 = reg_mstatus_v & _vs_interrupts_T_3; // @[CSR.scala:395:28, :622:{50,80}] wire _vs_interrupts_T_5 = _vs_interrupts_T_4; // @[CSR.scala:622:{32,50}] wire _any_T = d_interrupts[14]; // @[CSR.scala:615:42, :1637:76] wire _which_T = d_interrupts[14]; // @[CSR.scala:615:42, :1637:76, :1638:91] wire _any_T_1 = d_interrupts[13]; // @[CSR.scala:615:42, :1637:76] wire _which_T_1 = d_interrupts[13]; // @[CSR.scala:615:42, :1637:76, :1638:91] wire _any_T_2 = d_interrupts[12]; // @[CSR.scala:615:42, :1637:76] wire _which_T_2 = d_interrupts[12]; // @[CSR.scala:615:42, :1637:76, :1638:91] wire _any_T_3 = d_interrupts[11]; // @[CSR.scala:615:42, :1637:76] wire _which_T_3 = d_interrupts[11]; // @[CSR.scala:615:42, :1637:76, :1638:91] wire _any_T_4 = d_interrupts[3]; // @[CSR.scala:615:42, :1637:76] wire _which_T_4 = d_interrupts[3]; // @[CSR.scala:615:42, :1637:76, :1638:91] wire _any_T_5 = d_interrupts[7]; // @[CSR.scala:615:42, :1637:76] wire _which_T_5 = d_interrupts[7]; // @[CSR.scala:615:42, :1637:76, :1638:91] wire _any_T_6 = d_interrupts[9]; // @[CSR.scala:615:42, :1637:76] wire _which_T_6 = d_interrupts[9]; // @[CSR.scala:615:42, :1637:76, :1638:91] wire _any_T_7 = d_interrupts[1]; // @[CSR.scala:615:42, :1637:76] wire _which_T_7 = d_interrupts[1]; // @[CSR.scala:615:42, :1637:76, :1638:91] wire _any_T_8 = d_interrupts[5]; // @[CSR.scala:615:42, :1637:76] wire _which_T_8 = d_interrupts[5]; // @[CSR.scala:615:42, :1637:76, :1638:91] wire _any_T_9 = d_interrupts[10]; // @[CSR.scala:615:42, :1637:76] wire _which_T_9 = d_interrupts[10]; // @[CSR.scala:615:42, :1637:76, :1638:91] wire _any_T_10 = d_interrupts[2]; // @[CSR.scala:615:42, :1637:76] wire _which_T_10 = d_interrupts[2]; // @[CSR.scala:615:42, :1637:76, :1638:91] wire _any_T_11 = d_interrupts[6]; // @[CSR.scala:615:42, :1637:76] wire _which_T_11 = d_interrupts[6]; // @[CSR.scala:615:42, :1637:76, :1638:91] wire _any_T_12 = d_interrupts[8]; // @[CSR.scala:615:42, :1637:76] wire _which_T_12 = d_interrupts[8]; // @[CSR.scala:615:42, :1637:76, :1638:91] wire _any_T_13 = d_interrupts[0]; // @[CSR.scala:615:42, :1637:76] wire _which_T_13 = d_interrupts[0]; // @[CSR.scala:615:42, :1637:76, :1638:91] wire _any_T_14 = d_interrupts[4]; // @[CSR.scala:615:42, :1637:76] wire _which_T_14 = d_interrupts[4]; // @[CSR.scala:615:42, :1637:76, :1638:91] wire _any_T_15 = m_interrupts[15]; // @[CSR.scala:620:25, :1637:76] wire _which_T_15 = m_interrupts[15]; // @[CSR.scala:620:25, :1637:76, :1638:91] wire _any_T_16 = m_interrupts[14]; // @[CSR.scala:620:25, :1637:76] wire _which_T_16 = m_interrupts[14]; // @[CSR.scala:620:25, :1637:76, :1638:91] wire _any_T_17 = m_interrupts[13]; // @[CSR.scala:620:25, :1637:76] wire _which_T_17 = m_interrupts[13]; // @[CSR.scala:620:25, :1637:76, :1638:91] wire _any_T_18 = m_interrupts[12]; // @[CSR.scala:620:25, :1637:76] wire _which_T_18 = m_interrupts[12]; // @[CSR.scala:620:25, :1637:76, :1638:91] wire _any_T_19 = m_interrupts[11]; // @[CSR.scala:620:25, :1637:76] wire _which_T_19 = m_interrupts[11]; // @[CSR.scala:620:25, :1637:76, :1638:91] wire _any_T_20 = m_interrupts[3]; // @[CSR.scala:620:25, :1637:76] wire _which_T_20 = m_interrupts[3]; // @[CSR.scala:620:25, :1637:76, :1638:91] wire _any_T_21 = m_interrupts[7]; // @[CSR.scala:620:25, :1637:76] wire _which_T_21 = m_interrupts[7]; // @[CSR.scala:620:25, :1637:76, :1638:91] wire _any_T_22 = m_interrupts[9]; // @[CSR.scala:620:25, :1637:76] wire _which_T_22 = m_interrupts[9]; // @[CSR.scala:620:25, :1637:76, :1638:91] wire _any_T_23 = m_interrupts[1]; // @[CSR.scala:620:25, :1637:76] wire _which_T_23 = m_interrupts[1]; // @[CSR.scala:620:25, :1637:76, :1638:91] wire _any_T_24 = m_interrupts[5]; // @[CSR.scala:620:25, :1637:76] wire _which_T_24 = m_interrupts[5]; // @[CSR.scala:620:25, :1637:76, :1638:91] wire _any_T_25 = m_interrupts[10]; // @[CSR.scala:620:25, :1637:76] wire _which_T_25 = m_interrupts[10]; // @[CSR.scala:620:25, :1637:76, :1638:91] wire _any_T_26 = m_interrupts[2]; // @[CSR.scala:620:25, :1637:76] wire _which_T_26 = m_interrupts[2]; // @[CSR.scala:620:25, :1637:76, :1638:91] wire _any_T_27 = m_interrupts[6]; // @[CSR.scala:620:25, :1637:76] wire _which_T_27 = m_interrupts[6]; // @[CSR.scala:620:25, :1637:76, :1638:91] wire _any_T_28 = m_interrupts[8]; // @[CSR.scala:620:25, :1637:76] wire _which_T_28 = m_interrupts[8]; // @[CSR.scala:620:25, :1637:76, :1638:91] wire _any_T_29 = m_interrupts[0]; // @[CSR.scala:620:25, :1637:76] wire _which_T_29 = m_interrupts[0]; // @[CSR.scala:620:25, :1637:76, :1638:91] wire _any_T_30 = m_interrupts[4]; // @[CSR.scala:620:25, :1637:76] wire _which_T_30 = m_interrupts[4]; // @[CSR.scala:620:25, :1637:76, :1638:91] wire _any_T_31 = s_interrupts[15]; // @[CSR.scala:621:25, :1637:76] wire _which_T_31 = s_interrupts[15]; // @[CSR.scala:621:25, :1637:76, :1638:91] wire _any_T_32 = s_interrupts[14]; // @[CSR.scala:621:25, :1637:76] wire _which_T_32 = s_interrupts[14]; // @[CSR.scala:621:25, :1637:76, :1638:91] wire _any_T_33 = s_interrupts[13]; // @[CSR.scala:621:25, :1637:76] wire _which_T_33 = s_interrupts[13]; // @[CSR.scala:621:25, :1637:76, :1638:91] wire _any_T_34 = s_interrupts[12]; // @[CSR.scala:621:25, :1637:76] wire _which_T_34 = s_interrupts[12]; // @[CSR.scala:621:25, :1637:76, :1638:91] wire _any_T_35 = s_interrupts[11]; // @[CSR.scala:621:25, :1637:76] wire _which_T_35 = s_interrupts[11]; // @[CSR.scala:621:25, :1637:76, :1638:91] wire _any_T_36 = s_interrupts[3]; // @[CSR.scala:621:25, :1637:76] wire _which_T_36 = s_interrupts[3]; // @[CSR.scala:621:25, :1637:76, :1638:91] wire _any_T_37 = s_interrupts[7]; // @[CSR.scala:621:25, :1637:76] wire _which_T_37 = s_interrupts[7]; // @[CSR.scala:621:25, :1637:76, :1638:91] wire _any_T_38 = s_interrupts[9]; // @[CSR.scala:621:25, :1637:76] wire _which_T_38 = s_interrupts[9]; // @[CSR.scala:621:25, :1637:76, :1638:91] wire _any_T_39 = s_interrupts[1]; // @[CSR.scala:621:25, :1637:76] wire _which_T_39 = s_interrupts[1]; // @[CSR.scala:621:25, :1637:76, :1638:91] wire _any_T_40 = s_interrupts[5]; // @[CSR.scala:621:25, :1637:76] wire _which_T_40 = s_interrupts[5]; // @[CSR.scala:621:25, :1637:76, :1638:91] wire _any_T_41 = s_interrupts[10]; // @[CSR.scala:621:25, :1637:76] wire _which_T_41 = s_interrupts[10]; // @[CSR.scala:621:25, :1637:76, :1638:91] wire _any_T_42 = s_interrupts[2]; // @[CSR.scala:621:25, :1637:76] wire _which_T_42 = s_interrupts[2]; // @[CSR.scala:621:25, :1637:76, :1638:91] wire _any_T_43 = s_interrupts[6]; // @[CSR.scala:621:25, :1637:76] wire _which_T_43 = s_interrupts[6]; // @[CSR.scala:621:25, :1637:76, :1638:91] wire _any_T_44 = s_interrupts[8]; // @[CSR.scala:621:25, :1637:76] wire _which_T_44 = s_interrupts[8]; // @[CSR.scala:621:25, :1637:76, :1638:91] wire _any_T_45 = s_interrupts[0]; // @[CSR.scala:621:25, :1637:76] wire _which_T_45 = s_interrupts[0]; // @[CSR.scala:621:25, :1637:76, :1638:91] wire _any_T_46 = s_interrupts[4]; // @[CSR.scala:621:25, :1637:76] wire _which_T_46 = s_interrupts[4]; // @[CSR.scala:621:25, :1637:76, :1638:91] wire _any_T_63 = _any_T | _any_T_1; // @[CSR.scala:1637:{76,90}] wire _any_T_64 = _any_T_63 | _any_T_2; // @[CSR.scala:1637:{76,90}] wire _any_T_65 = _any_T_64 | _any_T_3; // @[CSR.scala:1637:{76,90}] wire _any_T_66 = _any_T_65 | _any_T_4; // @[CSR.scala:1637:{76,90}] wire _any_T_67 = _any_T_66 | _any_T_5; // @[CSR.scala:1637:{76,90}] wire _any_T_68 = _any_T_67 | _any_T_6; // @[CSR.scala:1637:{76,90}] wire _any_T_69 = _any_T_68 | _any_T_7; // @[CSR.scala:1637:{76,90}] wire _any_T_70 = _any_T_69 | _any_T_8; // @[CSR.scala:1637:{76,90}] wire _any_T_71 = _any_T_70 | _any_T_9; // @[CSR.scala:1637:{76,90}] wire _any_T_72 = _any_T_71 | _any_T_10; // @[CSR.scala:1637:{76,90}] wire _any_T_73 = _any_T_72 | _any_T_11; // @[CSR.scala:1637:{76,90}] wire _any_T_74 = _any_T_73 | _any_T_12; // @[CSR.scala:1637:{76,90}] wire _any_T_75 = _any_T_74 | _any_T_13; // @[CSR.scala:1637:{76,90}] wire _any_T_76 = _any_T_75 | _any_T_14; // @[CSR.scala:1637:{76,90}] wire _any_T_77 = _any_T_76; // @[CSR.scala:1637:90] wire _any_T_78 = _any_T_77 | _any_T_15; // @[CSR.scala:1637:{76,90}] wire _any_T_79 = _any_T_78 | _any_T_16; // @[CSR.scala:1637:{76,90}] wire _any_T_80 = _any_T_79 | _any_T_17; // @[CSR.scala:1637:{76,90}] wire _any_T_81 = _any_T_80 | _any_T_18; // @[CSR.scala:1637:{76,90}] wire _any_T_82 = _any_T_81 | _any_T_19; // @[CSR.scala:1637:{76,90}] wire _any_T_83 = _any_T_82 | _any_T_20; // @[CSR.scala:1637:{76,90}] wire _any_T_84 = _any_T_83 | _any_T_21; // @[CSR.scala:1637:{76,90}] wire _any_T_85 = _any_T_84 | _any_T_22; // @[CSR.scala:1637:{76,90}] wire _any_T_86 = _any_T_85 | _any_T_23; // @[CSR.scala:1637:{76,90}] wire _any_T_87 = _any_T_86 | _any_T_24; // @[CSR.scala:1637:{76,90}] wire _any_T_88 = _any_T_87 | _any_T_25; // @[CSR.scala:1637:{76,90}] wire _any_T_89 = _any_T_88 | _any_T_26; // @[CSR.scala:1637:{76,90}] wire _any_T_90 = _any_T_89 | _any_T_27; // @[CSR.scala:1637:{76,90}] wire _any_T_91 = _any_T_90 | _any_T_28; // @[CSR.scala:1637:{76,90}] wire _any_T_92 = _any_T_91 | _any_T_29; // @[CSR.scala:1637:{76,90}] wire _any_T_93 = _any_T_92 | _any_T_30; // @[CSR.scala:1637:{76,90}] wire _any_T_94 = _any_T_93 | _any_T_31; // @[CSR.scala:1637:{76,90}] wire _any_T_95 = _any_T_94 | _any_T_32; // @[CSR.scala:1637:{76,90}] wire _any_T_96 = _any_T_95 | _any_T_33; // @[CSR.scala:1637:{76,90}] wire _any_T_97 = _any_T_96 | _any_T_34; // @[CSR.scala:1637:{76,90}] wire _any_T_98 = _any_T_97 | _any_T_35; // @[CSR.scala:1637:{76,90}] wire _any_T_99 = _any_T_98 | _any_T_36; // @[CSR.scala:1637:{76,90}] wire _any_T_100 = _any_T_99 | _any_T_37; // @[CSR.scala:1637:{76,90}] wire _any_T_101 = _any_T_100 | _any_T_38; // @[CSR.scala:1637:{76,90}] wire _any_T_102 = _any_T_101 | _any_T_39; // @[CSR.scala:1637:{76,90}] wire _any_T_103 = _any_T_102 | _any_T_40; // @[CSR.scala:1637:{76,90}] wire _any_T_104 = _any_T_103 | _any_T_41; // @[CSR.scala:1637:{76,90}] wire _any_T_105 = _any_T_104 | _any_T_42; // @[CSR.scala:1637:{76,90}] wire _any_T_106 = _any_T_105 | _any_T_43; // @[CSR.scala:1637:{76,90}] wire _any_T_107 = _any_T_106 | _any_T_44; // @[CSR.scala:1637:{76,90}] wire _any_T_108 = _any_T_107 | _any_T_45; // @[CSR.scala:1637:{76,90}] wire _any_T_109 = _any_T_108 | _any_T_46; // @[CSR.scala:1637:{76,90}] wire _any_T_110 = _any_T_109; // @[CSR.scala:1637:90] wire _any_T_111 = _any_T_110; // @[CSR.scala:1637:90] wire _any_T_112 = _any_T_111; // @[CSR.scala:1637:90] wire _any_T_113 = _any_T_112; // @[CSR.scala:1637:90] wire _any_T_114 = _any_T_113; // @[CSR.scala:1637:90] wire _any_T_115 = _any_T_114; // @[CSR.scala:1637:90] wire _any_T_116 = _any_T_115; // @[CSR.scala:1637:90] wire _any_T_117 = _any_T_116; // @[CSR.scala:1637:90] wire _any_T_118 = _any_T_117; // @[CSR.scala:1637:90] wire _any_T_119 = _any_T_118; // @[CSR.scala:1637:90] wire _any_T_120 = _any_T_119; // @[CSR.scala:1637:90] wire _any_T_121 = _any_T_120; // @[CSR.scala:1637:90] wire _any_T_122 = _any_T_121; // @[CSR.scala:1637:90] wire _any_T_123 = _any_T_122; // @[CSR.scala:1637:90] wire _any_T_124 = _any_T_123; // @[CSR.scala:1637:90] wire anyInterrupt = _any_T_124; // @[CSR.scala:1637:90] wire [3:0] _which_T_79 = {1'h0, ~_which_T_45, 2'h0}; // @[Mux.scala:50:70] wire [3:0] _which_T_80 = _which_T_44 ? 4'h8 : _which_T_79; // @[Mux.scala:50:70] wire [3:0] _which_T_81 = _which_T_43 ? 4'h6 : _which_T_80; // @[Mux.scala:50:70] wire [3:0] _which_T_82 = _which_T_42 ? 4'h2 : _which_T_81; // @[Mux.scala:50:70] wire [3:0] _which_T_83 = _which_T_41 ? 4'hA : _which_T_82; // @[Mux.scala:50:70] wire [3:0] _which_T_84 = _which_T_40 ? 4'h5 : _which_T_83; // @[Mux.scala:50:70] wire [3:0] _which_T_85 = _which_T_39 ? 4'h1 : _which_T_84; // @[Mux.scala:50:70] wire [3:0] _which_T_86 = _which_T_38 ? 4'h9 : _which_T_85; // @[Mux.scala:50:70] wire [3:0] _which_T_87 = _which_T_37 ? 4'h7 : _which_T_86; // @[Mux.scala:50:70] wire [3:0] _which_T_88 = _which_T_36 ? 4'h3 : _which_T_87; // @[Mux.scala:50:70] wire [3:0] _which_T_89 = _which_T_35 ? 4'hB : _which_T_88; // @[Mux.scala:50:70] wire [3:0] _which_T_90 = _which_T_34 ? 4'hC : _which_T_89; // @[Mux.scala:50:70] wire [3:0] _which_T_91 = _which_T_33 ? 4'hD : _which_T_90; // @[Mux.scala:50:70] wire [3:0] _which_T_92 = _which_T_32 ? 4'hE : _which_T_91; // @[Mux.scala:50:70] wire [3:0] _which_T_93 = _which_T_31 ? 4'hF : _which_T_92; // @[Mux.scala:50:70] wire [3:0] _which_T_94 = _which_T_30 ? 4'h4 : _which_T_93; // @[Mux.scala:50:70] wire [3:0] _which_T_95 = _which_T_29 ? 4'h0 : _which_T_94; // @[Mux.scala:50:70] wire [3:0] _which_T_96 = _which_T_28 ? 4'h8 : _which_T_95; // @[Mux.scala:50:70] wire [3:0] _which_T_97 = _which_T_27 ? 4'h6 : _which_T_96; // @[Mux.scala:50:70] wire [3:0] _which_T_98 = _which_T_26 ? 4'h2 : _which_T_97; // @[Mux.scala:50:70] wire [3:0] _which_T_99 = _which_T_25 ? 4'hA : _which_T_98; // @[Mux.scala:50:70] wire [3:0] _which_T_100 = _which_T_24 ? 4'h5 : _which_T_99; // @[Mux.scala:50:70] wire [3:0] _which_T_101 = _which_T_23 ? 4'h1 : _which_T_100; // @[Mux.scala:50:70] wire [3:0] _which_T_102 = _which_T_22 ? 4'h9 : _which_T_101; // @[Mux.scala:50:70] wire [3:0] _which_T_103 = _which_T_21 ? 4'h7 : _which_T_102; // @[Mux.scala:50:70] wire [3:0] _which_T_104 = _which_T_20 ? 4'h3 : _which_T_103; // @[Mux.scala:50:70] wire [3:0] _which_T_105 = _which_T_19 ? 4'hB : _which_T_104; // @[Mux.scala:50:70] wire [3:0] _which_T_106 = _which_T_18 ? 4'hC : _which_T_105; // @[Mux.scala:50:70] wire [3:0] _which_T_107 = _which_T_17 ? 4'hD : _which_T_106; // @[Mux.scala:50:70] wire [3:0] _which_T_108 = _which_T_16 ? 4'hE : _which_T_107; // @[Mux.scala:50:70] wire [3:0] _which_T_109 = _which_T_15 ? 4'hF : _which_T_108; // @[Mux.scala:50:70] wire [3:0] _which_T_110 = _which_T_109; // @[Mux.scala:50:70] wire [3:0] _which_T_111 = _which_T_14 ? 4'h4 : _which_T_110; // @[Mux.scala:50:70] wire [3:0] _which_T_112 = _which_T_13 ? 4'h0 : _which_T_111; // @[Mux.scala:50:70] wire [3:0] _which_T_113 = _which_T_12 ? 4'h8 : _which_T_112; // @[Mux.scala:50:70] wire [3:0] _which_T_114 = _which_T_11 ? 4'h6 : _which_T_113; // @[Mux.scala:50:70] wire [3:0] _which_T_115 = _which_T_10 ? 4'h2 : _which_T_114; // @[Mux.scala:50:70] wire [3:0] _which_T_116 = _which_T_9 ? 4'hA : _which_T_115; // @[Mux.scala:50:70] wire [3:0] _which_T_117 = _which_T_8 ? 4'h5 : _which_T_116; // @[Mux.scala:50:70] wire [3:0] _which_T_118 = _which_T_7 ? 4'h1 : _which_T_117; // @[Mux.scala:50:70] wire [3:0] _which_T_119 = _which_T_6 ? 4'h9 : _which_T_118; // @[Mux.scala:50:70] wire [3:0] _which_T_120 = _which_T_5 ? 4'h7 : _which_T_119; // @[Mux.scala:50:70] wire [3:0] _which_T_121 = _which_T_4 ? 4'h3 : _which_T_120; // @[Mux.scala:50:70] wire [3:0] _which_T_122 = _which_T_3 ? 4'hB : _which_T_121; // @[Mux.scala:50:70] wire [3:0] _which_T_123 = _which_T_2 ? 4'hC : _which_T_122; // @[Mux.scala:50:70] wire [3:0] _which_T_124 = _which_T_1 ? 4'hD : _which_T_123; // @[Mux.scala:50:70] wire [3:0] whichInterrupt = _which_T ? 4'hE : _which_T_124; // @[Mux.scala:50:70] wire [64:0] _interruptCause_T_3 = {61'h0, whichInterrupt} + 65'h8000000000000000; // @[Mux.scala:50:70] assign interruptCause = _interruptCause_T_3[63:0]; // @[CSR.scala:625:63] assign io_interrupt_cause_0 = interruptCause; // @[CSR.scala:377:7, :625:63] wire _io_interrupt_T = ~io_singleStep_0; // @[CSR.scala:377:7, :626:36] wire _io_interrupt_T_1 = anyInterrupt & _io_interrupt_T; // @[CSR.scala:626:{33,36}, :1637:90] wire _io_interrupt_T_2 = _io_interrupt_T_1 | reg_singleStepped; // @[CSR.scala:486:30, :626:{33,51}] wire _io_interrupt_T_3 = reg_debug | io_status_cease_0; // @[CSR.scala:377:7, :482:26, :626:88] wire _io_interrupt_T_4 = ~_io_interrupt_T_3; // @[CSR.scala:626:{76,88}] assign _io_interrupt_T_5 = _io_interrupt_T_2 & _io_interrupt_T_4; // @[CSR.scala:626:{51,73,76}] assign io_interrupt_0 = _io_interrupt_T_5; // @[CSR.scala:377:7, :626:73] wire _io_fiom_T = reg_mstatus_prv != 2'h3; // @[CSR.scala:395:28, :631:31] wire _io_fiom_T_1 = _io_fiom_T & reg_menvcfg_fiom; // @[CSR.scala:525:28, :631:{31,41}] wire _io_fiom_T_3 = _io_fiom_T_2 & reg_senvcfg_fiom; // @[CSR.scala:526:28, :631:{82,92}] wire _io_fiom_T_4 = _io_fiom_T_1 | _io_fiom_T_3; // @[CSR.scala:631:{41,62,92}] assign _io_fiom_T_6 = _io_fiom_T_4; // @[CSR.scala:631:{62,113}] assign io_fiom = _io_fiom_T_6; // @[CSR.scala:377:7, :631:113] assign io_pmp_0_cfg_l_0 = pmp_cfg_l; // @[PMP.scala:24:19] assign io_pmp_0_cfg_a_0 = pmp_cfg_a; // @[PMP.scala:24:19] assign io_pmp_0_cfg_x_0 = pmp_cfg_x; // @[PMP.scala:24:19] assign io_pmp_0_cfg_w_0 = pmp_cfg_w; // @[PMP.scala:24:19] assign io_pmp_0_cfg_r_0 = pmp_cfg_r; // @[PMP.scala:24:19] assign io_pmp_0_addr_0 = pmp_addr; // @[PMP.scala:24:19] assign io_pmp_0_mask_0 = pmp_mask; // @[PMP.scala:24:19] wire _pmp_mask_base_T = pmp_cfg_a[0]; // @[PMP.scala:24:19, :57:31] wire [30:0] _pmp_mask_base_T_1 = {pmp_addr, _pmp_mask_base_T}; // @[PMP.scala:24:19, :57:{19,31}] wire [30:0] pmp_mask_base = _pmp_mask_base_T_1; // @[PMP.scala:57:{19,36}] wire [31:0] _pmp_mask_T = {1'h0, pmp_mask_base} + 32'h1; // @[PMP.scala:57:36, :58:23] wire [30:0] _pmp_mask_T_1 = _pmp_mask_T[30:0]; // @[PMP.scala:58:23] wire [30:0] _pmp_mask_T_2 = ~_pmp_mask_T_1; // @[PMP.scala:58:{16,23}] wire [30:0] _pmp_mask_T_3 = pmp_mask_base & _pmp_mask_T_2; // @[PMP.scala:57:36, :58:{14,16}] wire [32:0] _pmp_mask_T_4 = {_pmp_mask_T_3, 2'h3}; // @[PMP.scala:58:{8,14}] assign pmp_mask = _pmp_mask_T_4[31:0]; // @[PMP.scala:24:19, :27:14, :58:8] assign io_pmp_1_cfg_l_0 = pmp_1_cfg_l; // @[PMP.scala:24:19] assign io_pmp_1_cfg_a_0 = pmp_1_cfg_a; // @[PMP.scala:24:19] assign io_pmp_1_cfg_x_0 = pmp_1_cfg_x; // @[PMP.scala:24:19] assign io_pmp_1_cfg_w_0 = pmp_1_cfg_w; // @[PMP.scala:24:19] assign io_pmp_1_cfg_r_0 = pmp_1_cfg_r; // @[PMP.scala:24:19] assign io_pmp_1_addr_0 = pmp_1_addr; // @[PMP.scala:24:19] assign io_pmp_1_mask_0 = pmp_1_mask; // @[PMP.scala:24:19] wire _pmp_mask_base_T_3 = pmp_1_cfg_a[0]; // @[PMP.scala:24:19, :57:31] wire [30:0] _pmp_mask_base_T_4 = {pmp_1_addr, _pmp_mask_base_T_3}; // @[PMP.scala:24:19, :57:{19,31}] wire [30:0] pmp_mask_base_1 = _pmp_mask_base_T_4; // @[PMP.scala:57:{19,36}] wire [31:0] _pmp_mask_T_5 = {1'h0, pmp_mask_base_1} + 32'h1; // @[PMP.scala:57:36, :58:23] wire [30:0] _pmp_mask_T_6 = _pmp_mask_T_5[30:0]; // @[PMP.scala:58:23] wire [30:0] _pmp_mask_T_7 = ~_pmp_mask_T_6; // @[PMP.scala:58:{16,23}] wire [30:0] _pmp_mask_T_8 = pmp_mask_base_1 & _pmp_mask_T_7; // @[PMP.scala:57:36, :58:{14,16}] wire [32:0] _pmp_mask_T_9 = {_pmp_mask_T_8, 2'h3}; // @[PMP.scala:58:{8,14}] assign pmp_1_mask = _pmp_mask_T_9[31:0]; // @[PMP.scala:24:19, :27:14, :58:8] assign io_pmp_2_cfg_l_0 = pmp_2_cfg_l; // @[PMP.scala:24:19] assign io_pmp_2_cfg_a_0 = pmp_2_cfg_a; // @[PMP.scala:24:19] assign io_pmp_2_cfg_x_0 = pmp_2_cfg_x; // @[PMP.scala:24:19] assign io_pmp_2_cfg_w_0 = pmp_2_cfg_w; // @[PMP.scala:24:19] assign io_pmp_2_cfg_r_0 = pmp_2_cfg_r; // @[PMP.scala:24:19] assign io_pmp_2_addr_0 = pmp_2_addr; // @[PMP.scala:24:19] assign io_pmp_2_mask_0 = pmp_2_mask; // @[PMP.scala:24:19] wire _pmp_mask_base_T_6 = pmp_2_cfg_a[0]; // @[PMP.scala:24:19, :57:31] wire [30:0] _pmp_mask_base_T_7 = {pmp_2_addr, _pmp_mask_base_T_6}; // @[PMP.scala:24:19, :57:{19,31}] wire [30:0] pmp_mask_base_2 = _pmp_mask_base_T_7; // @[PMP.scala:57:{19,36}] wire [31:0] _pmp_mask_T_10 = {1'h0, pmp_mask_base_2} + 32'h1; // @[PMP.scala:57:36, :58:23] wire [30:0] _pmp_mask_T_11 = _pmp_mask_T_10[30:0]; // @[PMP.scala:58:23] wire [30:0] _pmp_mask_T_12 = ~_pmp_mask_T_11; // @[PMP.scala:58:{16,23}] wire [30:0] _pmp_mask_T_13 = pmp_mask_base_2 & _pmp_mask_T_12; // @[PMP.scala:57:36, :58:{14,16}] wire [32:0] _pmp_mask_T_14 = {_pmp_mask_T_13, 2'h3}; // @[PMP.scala:58:{8,14}] assign pmp_2_mask = _pmp_mask_T_14[31:0]; // @[PMP.scala:24:19, :27:14, :58:8] assign io_pmp_3_cfg_l_0 = pmp_3_cfg_l; // @[PMP.scala:24:19] assign io_pmp_3_cfg_a_0 = pmp_3_cfg_a; // @[PMP.scala:24:19] assign io_pmp_3_cfg_x_0 = pmp_3_cfg_x; // @[PMP.scala:24:19] assign io_pmp_3_cfg_w_0 = pmp_3_cfg_w; // @[PMP.scala:24:19] assign io_pmp_3_cfg_r_0 = pmp_3_cfg_r; // @[PMP.scala:24:19] assign io_pmp_3_addr_0 = pmp_3_addr; // @[PMP.scala:24:19] assign io_pmp_3_mask_0 = pmp_3_mask; // @[PMP.scala:24:19] wire _pmp_mask_base_T_9 = pmp_3_cfg_a[0]; // @[PMP.scala:24:19, :57:31] wire [30:0] _pmp_mask_base_T_10 = {pmp_3_addr, _pmp_mask_base_T_9}; // @[PMP.scala:24:19, :57:{19,31}] wire [30:0] pmp_mask_base_3 = _pmp_mask_base_T_10; // @[PMP.scala:57:{19,36}] wire [31:0] _pmp_mask_T_15 = {1'h0, pmp_mask_base_3} + 32'h1; // @[PMP.scala:57:36, :58:23] wire [30:0] _pmp_mask_T_16 = _pmp_mask_T_15[30:0]; // @[PMP.scala:58:23] wire [30:0] _pmp_mask_T_17 = ~_pmp_mask_T_16; // @[PMP.scala:58:{16,23}] wire [30:0] _pmp_mask_T_18 = pmp_mask_base_3 & _pmp_mask_T_17; // @[PMP.scala:57:36, :58:{14,16}] wire [32:0] _pmp_mask_T_19 = {_pmp_mask_T_18, 2'h3}; // @[PMP.scala:58:{8,14}] assign pmp_3_mask = _pmp_mask_T_19[31:0]; // @[PMP.scala:24:19, :27:14, :58:8] assign io_pmp_4_cfg_l_0 = pmp_4_cfg_l; // @[PMP.scala:24:19] assign io_pmp_4_cfg_a_0 = pmp_4_cfg_a; // @[PMP.scala:24:19] assign io_pmp_4_cfg_x_0 = pmp_4_cfg_x; // @[PMP.scala:24:19] assign io_pmp_4_cfg_w_0 = pmp_4_cfg_w; // @[PMP.scala:24:19] assign io_pmp_4_cfg_r_0 = pmp_4_cfg_r; // @[PMP.scala:24:19] assign io_pmp_4_addr_0 = pmp_4_addr; // @[PMP.scala:24:19] assign io_pmp_4_mask_0 = pmp_4_mask; // @[PMP.scala:24:19] wire _pmp_mask_base_T_12 = pmp_4_cfg_a[0]; // @[PMP.scala:24:19, :57:31] wire [30:0] _pmp_mask_base_T_13 = {pmp_4_addr, _pmp_mask_base_T_12}; // @[PMP.scala:24:19, :57:{19,31}] wire [30:0] pmp_mask_base_4 = _pmp_mask_base_T_13; // @[PMP.scala:57:{19,36}] wire [31:0] _pmp_mask_T_20 = {1'h0, pmp_mask_base_4} + 32'h1; // @[PMP.scala:57:36, :58:23] wire [30:0] _pmp_mask_T_21 = _pmp_mask_T_20[30:0]; // @[PMP.scala:58:23] wire [30:0] _pmp_mask_T_22 = ~_pmp_mask_T_21; // @[PMP.scala:58:{16,23}] wire [30:0] _pmp_mask_T_23 = pmp_mask_base_4 & _pmp_mask_T_22; // @[PMP.scala:57:36, :58:{14,16}] wire [32:0] _pmp_mask_T_24 = {_pmp_mask_T_23, 2'h3}; // @[PMP.scala:58:{8,14}] assign pmp_4_mask = _pmp_mask_T_24[31:0]; // @[PMP.scala:24:19, :27:14, :58:8] assign io_pmp_5_cfg_l_0 = pmp_5_cfg_l; // @[PMP.scala:24:19] assign io_pmp_5_cfg_a_0 = pmp_5_cfg_a; // @[PMP.scala:24:19] assign io_pmp_5_cfg_x_0 = pmp_5_cfg_x; // @[PMP.scala:24:19] assign io_pmp_5_cfg_w_0 = pmp_5_cfg_w; // @[PMP.scala:24:19] assign io_pmp_5_cfg_r_0 = pmp_5_cfg_r; // @[PMP.scala:24:19] assign io_pmp_5_addr_0 = pmp_5_addr; // @[PMP.scala:24:19] assign io_pmp_5_mask_0 = pmp_5_mask; // @[PMP.scala:24:19] wire _pmp_mask_base_T_15 = pmp_5_cfg_a[0]; // @[PMP.scala:24:19, :57:31] wire [30:0] _pmp_mask_base_T_16 = {pmp_5_addr, _pmp_mask_base_T_15}; // @[PMP.scala:24:19, :57:{19,31}] wire [30:0] pmp_mask_base_5 = _pmp_mask_base_T_16; // @[PMP.scala:57:{19,36}] wire [31:0] _pmp_mask_T_25 = {1'h0, pmp_mask_base_5} + 32'h1; // @[PMP.scala:57:36, :58:23] wire [30:0] _pmp_mask_T_26 = _pmp_mask_T_25[30:0]; // @[PMP.scala:58:23] wire [30:0] _pmp_mask_T_27 = ~_pmp_mask_T_26; // @[PMP.scala:58:{16,23}] wire [30:0] _pmp_mask_T_28 = pmp_mask_base_5 & _pmp_mask_T_27; // @[PMP.scala:57:36, :58:{14,16}] wire [32:0] _pmp_mask_T_29 = {_pmp_mask_T_28, 2'h3}; // @[PMP.scala:58:{8,14}] assign pmp_5_mask = _pmp_mask_T_29[31:0]; // @[PMP.scala:24:19, :27:14, :58:8] assign io_pmp_6_cfg_l_0 = pmp_6_cfg_l; // @[PMP.scala:24:19] assign io_pmp_6_cfg_a_0 = pmp_6_cfg_a; // @[PMP.scala:24:19] assign io_pmp_6_cfg_x_0 = pmp_6_cfg_x; // @[PMP.scala:24:19] assign io_pmp_6_cfg_w_0 = pmp_6_cfg_w; // @[PMP.scala:24:19] assign io_pmp_6_cfg_r_0 = pmp_6_cfg_r; // @[PMP.scala:24:19] assign io_pmp_6_addr_0 = pmp_6_addr; // @[PMP.scala:24:19] assign io_pmp_6_mask_0 = pmp_6_mask; // @[PMP.scala:24:19] wire _pmp_mask_base_T_18 = pmp_6_cfg_a[0]; // @[PMP.scala:24:19, :57:31] wire [30:0] _pmp_mask_base_T_19 = {pmp_6_addr, _pmp_mask_base_T_18}; // @[PMP.scala:24:19, :57:{19,31}] wire [30:0] pmp_mask_base_6 = _pmp_mask_base_T_19; // @[PMP.scala:57:{19,36}] wire [31:0] _pmp_mask_T_30 = {1'h0, pmp_mask_base_6} + 32'h1; // @[PMP.scala:57:36, :58:23] wire [30:0] _pmp_mask_T_31 = _pmp_mask_T_30[30:0]; // @[PMP.scala:58:23] wire [30:0] _pmp_mask_T_32 = ~_pmp_mask_T_31; // @[PMP.scala:58:{16,23}] wire [30:0] _pmp_mask_T_33 = pmp_mask_base_6 & _pmp_mask_T_32; // @[PMP.scala:57:36, :58:{14,16}] wire [32:0] _pmp_mask_T_34 = {_pmp_mask_T_33, 2'h3}; // @[PMP.scala:58:{8,14}] assign pmp_6_mask = _pmp_mask_T_34[31:0]; // @[PMP.scala:24:19, :27:14, :58:8] assign io_pmp_7_cfg_l_0 = pmp_7_cfg_l; // @[PMP.scala:24:19] assign io_pmp_7_cfg_a_0 = pmp_7_cfg_a; // @[PMP.scala:24:19] assign io_pmp_7_cfg_x_0 = pmp_7_cfg_x; // @[PMP.scala:24:19] assign io_pmp_7_cfg_w_0 = pmp_7_cfg_w; // @[PMP.scala:24:19] assign io_pmp_7_cfg_r_0 = pmp_7_cfg_r; // @[PMP.scala:24:19] assign io_pmp_7_addr_0 = pmp_7_addr; // @[PMP.scala:24:19] assign io_pmp_7_mask_0 = pmp_7_mask; // @[PMP.scala:24:19] wire _pmp_mask_base_T_21 = pmp_7_cfg_a[0]; // @[PMP.scala:24:19, :57:31] wire [30:0] _pmp_mask_base_T_22 = {pmp_7_addr, _pmp_mask_base_T_21}; // @[PMP.scala:24:19, :57:{19,31}] wire [30:0] pmp_mask_base_7 = _pmp_mask_base_T_22; // @[PMP.scala:57:{19,36}] wire [31:0] _pmp_mask_T_35 = {1'h0, pmp_mask_base_7} + 32'h1; // @[PMP.scala:57:36, :58:23] wire [30:0] _pmp_mask_T_36 = _pmp_mask_T_35[30:0]; // @[PMP.scala:58:23] wire [30:0] _pmp_mask_T_37 = ~_pmp_mask_T_36; // @[PMP.scala:58:{16,23}] wire [30:0] _pmp_mask_T_38 = pmp_mask_base_7 & _pmp_mask_T_37; // @[PMP.scala:57:36, :58:{14,16}] wire [32:0] _pmp_mask_T_39 = {_pmp_mask_T_38, 2'h3}; // @[PMP.scala:58:{8,14}] assign pmp_7_mask = _pmp_mask_T_39[31:0]; // @[PMP.scala:24:19, :27:14, :58:8] wire [1:0] read_mstatus_lo_lo_lo_lo = {io_status_sie_0, 1'h0}; // @[CSR.scala:377:7, :649:32] wire [1:0] read_mstatus_lo_lo_lo_hi = {io_status_mie_0, 1'h0}; // @[CSR.scala:377:7, :649:32] wire [3:0] read_mstatus_lo_lo_lo = {read_mstatus_lo_lo_lo_hi, read_mstatus_lo_lo_lo_lo}; // @[CSR.scala:649:32] wire [1:0] read_mstatus_lo_lo_hi_lo = {io_status_spie_0, 1'h0}; // @[CSR.scala:377:7, :649:32] wire [1:0] read_mstatus_lo_lo_hi_hi_hi = {io_status_spp_0, io_status_mpie_0}; // @[CSR.scala:377:7, :649:32] wire [2:0] read_mstatus_lo_lo_hi_hi = {read_mstatus_lo_lo_hi_hi_hi, 1'h0}; // @[CSR.scala:649:32] wire [4:0] read_mstatus_lo_lo_hi = {read_mstatus_lo_lo_hi_hi, read_mstatus_lo_lo_hi_lo}; // @[CSR.scala:649:32] wire [8:0] read_mstatus_lo_lo = {read_mstatus_lo_lo_hi, read_mstatus_lo_lo_lo}; // @[CSR.scala:649:32] wire [3:0] read_mstatus_lo_hi_lo_lo = {io_status_mpp_0, 2'h0}; // @[CSR.scala:377:7, :649:32] wire [3:0] read_mstatus_lo_hi_lo_hi = {2'h0, io_status_fs_0}; // @[CSR.scala:377:7, :649:32] wire [7:0] read_mstatus_lo_hi_lo = {read_mstatus_lo_hi_lo_hi, read_mstatus_lo_hi_lo_lo}; // @[CSR.scala:649:32] wire [1:0] read_mstatus_lo_hi_hi_lo = {io_status_sum_0, io_status_mprv_0}; // @[CSR.scala:377:7, :649:32] wire [1:0] read_mstatus_lo_hi_hi_hi_hi = {io_status_tw_0, io_status_tvm_0}; // @[CSR.scala:377:7, :649:32] wire [2:0] read_mstatus_lo_hi_hi_hi = {read_mstatus_lo_hi_hi_hi_hi, io_status_mxr_0}; // @[CSR.scala:377:7, :649:32] wire [4:0] read_mstatus_lo_hi_hi = {read_mstatus_lo_hi_hi_hi, read_mstatus_lo_hi_hi_lo}; // @[CSR.scala:649:32] wire [12:0] read_mstatus_lo_hi = {read_mstatus_lo_hi_hi, read_mstatus_lo_hi_lo}; // @[CSR.scala:649:32] wire [21:0] read_mstatus_lo = {read_mstatus_lo_hi, read_mstatus_lo_lo}; // @[CSR.scala:649:32] wire [8:0] read_mstatus_hi_lo_lo_lo = {8'h0, io_status_tsr_0}; // @[CSR.scala:377:7, :649:32] wire [11:0] read_mstatus_hi_lo_lo = {3'h4, read_mstatus_hi_lo_lo_lo}; // @[CSR.scala:649:32] wire [1:0] read_mstatus_hi_lo_hi_hi_hi = {io_status_mpv_0, io_status_gva_0}; // @[CSR.scala:377:7, :649:32] wire [2:0] read_mstatus_hi_lo_hi_hi = {read_mstatus_hi_lo_hi_hi_hi, 1'h0}; // @[CSR.scala:649:32] wire [5:0] read_mstatus_hi_lo_hi = {read_mstatus_hi_lo_hi_hi, 3'h2}; // @[CSR.scala:649:32] wire [17:0] read_mstatus_hi_lo = {read_mstatus_hi_lo_hi, read_mstatus_hi_lo_lo}; // @[CSR.scala:649:32] wire [23:0] read_mstatus_hi_hi_lo_lo = {io_status_sd_0, 23'h0}; // @[CSR.scala:377:7, :649:32] wire [2:0] read_mstatus_hi_hi_lo_hi_hi = {io_status_dv_0, io_status_prv_0}; // @[CSR.scala:377:7, :649:32] wire [3:0] read_mstatus_hi_hi_lo_hi = {read_mstatus_hi_hi_lo_hi_hi, io_status_v_0}; // @[CSR.scala:377:7, :649:32] wire [27:0] read_mstatus_hi_hi_lo = {read_mstatus_hi_hi_lo_hi, read_mstatus_hi_hi_lo_lo}; // @[CSR.scala:649:32] wire [33:0] read_mstatus_hi_hi_hi_lo = {32'h14112D, io_status_dprv_0}; // @[CSR.scala:377:7, :649:32] wire [1:0] read_mstatus_hi_hi_hi_hi_hi = {io_status_debug_0, io_status_cease_0}; // @[CSR.scala:377:7, :649:32] wire [2:0] read_mstatus_hi_hi_hi_hi = {read_mstatus_hi_hi_hi_hi_hi, io_status_wfi_0}; // @[CSR.scala:377:7, :649:32] wire [36:0] read_mstatus_hi_hi_hi = {read_mstatus_hi_hi_hi_hi, read_mstatus_hi_hi_hi_lo}; // @[CSR.scala:649:32] wire [64:0] read_mstatus_hi_hi = {read_mstatus_hi_hi_hi, read_mstatus_hi_hi_lo}; // @[CSR.scala:649:32] wire [82:0] read_mstatus_hi = {read_mstatus_hi_hi, read_mstatus_hi_lo}; // @[CSR.scala:649:32] wire [104:0] _read_mstatus_T = {read_mstatus_hi, read_mstatus_lo}; // @[CSR.scala:649:32] wire [63:0] read_mstatus = _read_mstatus_T[63:0]; // @[package.scala:163:13] wire _read_mtvec_T = reg_mtvec[0]; // @[CSR.scala:512:31, :1666:41] wire [7:0] _read_mtvec_T_1 = _read_mtvec_T ? 8'hFE : 8'h2; // @[CSR.scala:1666:{39,41}] wire [31:0] _read_mtvec_T_3 = {24'h0, _read_mtvec_T_1}; // @[package.scala:174:41] wire [31:0] _read_mtvec_T_4 = ~_read_mtvec_T_3; // @[package.scala:174:{37,41}] wire [31:0] _read_mtvec_T_5 = reg_mtvec & _read_mtvec_T_4; // @[package.scala:174:{35,37}] wire [63:0] read_mtvec = {32'h0, _read_mtvec_T_5}; // @[package.scala:138:15, :174:35] wire _read_stvec_T = reg_stvec[0]; // @[CSR.scala:573:22, :1666:41] wire [7:0] _read_stvec_T_1 = _read_stvec_T ? 8'hFE : 8'h2; // @[CSR.scala:1666:{39,41}] wire [38:0] _read_stvec_T_3 = {31'h0, _read_stvec_T_1}; // @[package.scala:174:41] wire [38:0] _read_stvec_T_4 = ~_read_stvec_T_3; // @[package.scala:174:{37,41}] wire [38:0] _read_stvec_T_5 = reg_stvec & _read_stvec_T_4; // @[package.scala:174:{35,37}] wire _read_stvec_T_6 = _read_stvec_T_5[38]; // @[package.scala:132:38, :174:35] wire [24:0] _read_stvec_T_7 = {25{_read_stvec_T_6}}; // @[package.scala:132:{20,38}] wire [63:0] read_stvec = {_read_stvec_T_7, _read_stvec_T_5}; // @[package.scala:132:{15,20}, :174:35] wire [39:0] _read_mapping_T_2 = ~reg_mepc; // @[CSR.scala:505:21, :1665:28] wire [39:0] _read_mapping_T_5 = {_read_mapping_T_2[39:2], _read_mapping_T_2[1:0] | 2'h1}; // @[CSR.scala:1665:{28,31}] wire [39:0] _read_mapping_T_6 = ~_read_mapping_T_5; // @[CSR.scala:1665:{26,31}] wire _read_mapping_T_7 = _read_mapping_T_6[39]; // @[package.scala:132:38] wire [23:0] _read_mapping_T_8 = {24{_read_mapping_T_7}}; // @[package.scala:132:{20,38}] wire [63:0] read_mapping_10_2 = {_read_mapping_T_8, _read_mapping_T_6}; // @[package.scala:132:{15,20}] wire _read_mapping_T_9 = reg_mtval[39]; // @[package.scala:132:38] wire [23:0] _read_mapping_T_10 = {24{_read_mapping_T_9}}; // @[package.scala:132:{20,38}] wire [63:0] read_mapping_11_2 = {_read_mapping_T_10, reg_mtval}; // @[package.scala:132:{15,20}] wire [2:0] debug_csrs_lo_lo_hi = {2'h0, reg_dcsr_step}; // @[CSR.scala:403:25, :670:27] wire [4:0] debug_csrs_lo_lo = {debug_csrs_lo_lo_hi, reg_dcsr_prv}; // @[CSR.scala:403:25, :670:27] wire [3:0] debug_csrs_lo_hi_lo = {reg_dcsr_cause, reg_dcsr_v}; // @[CSR.scala:403:25, :670:27] wire [5:0] debug_csrs_lo_hi = {2'h0, debug_csrs_lo_hi_lo}; // @[CSR.scala:670:27] wire [10:0] debug_csrs_lo = {debug_csrs_lo_hi, debug_csrs_lo_lo}; // @[CSR.scala:670:27] wire [1:0] debug_csrs_hi_lo_lo = {reg_dcsr_ebreaku, 1'h0}; // @[CSR.scala:403:25, :670:27] wire [1:0] debug_csrs_hi_lo_hi = {1'h0, reg_dcsr_ebreaks}; // @[CSR.scala:403:25, :670:27] wire [3:0] debug_csrs_hi_lo = {debug_csrs_hi_lo_hi, debug_csrs_hi_lo_lo}; // @[CSR.scala:670:27] wire [12:0] debug_csrs_hi_hi_lo = {12'h0, reg_dcsr_ebreakm}; // @[CSR.scala:403:25, :670:27] wire [16:0] debug_csrs_hi_hi = {4'h4, debug_csrs_hi_hi_lo}; // @[CSR.scala:670:27] wire [20:0] debug_csrs_hi = {debug_csrs_hi_hi, debug_csrs_hi_lo}; // @[CSR.scala:670:27] wire [31:0] debug_csrs_0_2 = {debug_csrs_hi, debug_csrs_lo}; // @[CSR.scala:670:27] wire [39:0] _debug_csrs_T = ~reg_dpc; // @[CSR.scala:483:20, :1665:28] wire [39:0] _debug_csrs_T_3 = {_debug_csrs_T[39:2], _debug_csrs_T[1:0] | 2'h1}; // @[CSR.scala:1665:{28,31}] wire [39:0] _debug_csrs_T_4 = ~_debug_csrs_T_3; // @[CSR.scala:1665:{26,31}] wire _debug_csrs_T_5 = _debug_csrs_T_4[39]; // @[package.scala:132:38] wire [23:0] _debug_csrs_T_6 = {24{_debug_csrs_T_5}}; // @[package.scala:132:{20,38}] wire [63:0] debug_csrs_1_2 = {_debug_csrs_T_6, _debug_csrs_T_4}; // @[package.scala:132:{15,20}] wire [7:0] read_fcsr = {reg_frm, reg_fflags}; // @[CSR.scala:577:23, :578:20, :689:22] wire [3:0] lo_lo_4 = {3'h0, reg_menvcfg_fiom}; // @[CSR.scala:525:28, :742:49] wire [6:0] lo_4 = {3'h0, lo_lo_4}; // @[CSR.scala:742:49] wire [63:0] sie_mask = {48'h0, read_mideleg[15:0] & 16'hEFFF}; // @[CSR.scala:498:14, :750:18] wire [63:0] read_sie = reg_mie & sie_mask; // @[CSR.scala:495:20, :750:18, :753:28] wire [63:0] read_sip = {48'h0, sie_mask[15:0] & read_mip}; // @[CSR.scala:610:29, :750:18, :754:29] wire [1:0] lo_lo_lo_lo = {read_sstatus_sie, 1'h0}; // @[CSR.scala:755:35, :768:51] wire [3:0] lo_lo_lo_4 = {2'h0, lo_lo_lo_lo}; // @[CSR.scala:768:51] wire [1:0] lo_lo_hi_lo = {read_sstatus_spie, 1'h0}; // @[CSR.scala:755:35, :768:51] wire [1:0] lo_lo_hi_hi_hi = {read_sstatus_spp, 1'h0}; // @[CSR.scala:755:35, :768:51] wire [2:0] lo_lo_hi_hi = {lo_lo_hi_hi_hi, 1'h0}; // @[CSR.scala:768:51] wire [4:0] lo_lo_hi_4 = {lo_lo_hi_hi, lo_lo_hi_lo}; // @[CSR.scala:768:51] wire [8:0] lo_lo_5 = {lo_lo_hi_4, lo_lo_lo_4}; // @[CSR.scala:768:51] wire [3:0] lo_hi_lo_hi = {2'h0, read_sstatus_fs}; // @[CSR.scala:755:35, :768:51] wire [7:0] lo_hi_lo_4 = {lo_hi_lo_hi, 4'h0}; // @[CSR.scala:768:51] wire [1:0] lo_hi_hi_lo = {read_sstatus_sum, 1'h0}; // @[CSR.scala:755:35, :768:51] wire [2:0] lo_hi_hi_hi = {2'h0, read_sstatus_mxr}; // @[CSR.scala:755:35, :768:51] wire [4:0] lo_hi_hi_4 = {lo_hi_hi_hi, lo_hi_hi_lo}; // @[CSR.scala:768:51] wire [12:0] lo_hi_5 = {lo_hi_hi_4, lo_hi_lo_4}; // @[CSR.scala:768:51] wire [21:0] lo_5 = {lo_hi_5, lo_lo_5}; // @[CSR.scala:768:51] wire [23:0] hi_hi_lo_lo = {read_sstatus_sd, 23'h0}; // @[CSR.scala:755:35, :768:51] wire [27:0] hi_hi_lo_4 = {4'h0, hi_hi_lo_lo}; // @[CSR.scala:768:51] wire [64:0] hi_hi_5 = {37'h0, hi_hi_lo_4}; // @[CSR.scala:768:51] wire [82:0] hi_7 = {hi_hi_5, 18'h800}; // @[CSR.scala:768:51] wire [19:0] hi_8 = {reg_satp_mode, 16'h0}; // @[CSR.scala:574:21, :774:43] wire [39:0] _io_evec_T = ~reg_sepc; // @[CSR.scala:569:21, :1665:28] wire [39:0] _T_34 = ~{_io_evec_T[39:2], _io_evec_T[1:0] | 2'h1}; // @[CSR.scala:1665:{26,28,31}] wire [3:0] lo_lo_6 = {3'h0, reg_senvcfg_fiom}; // @[CSR.scala:526:28, :780:49] wire [6:0] lo_6 = {3'h0, lo_lo_6}; // @[CSR.scala:780:49] wire [1:0] lo_hi_7 = {reg_pmp_0_cfg_x, reg_pmp_0_cfg_w}; // @[package.scala:45:36] wire [2:0] lo_7 = {lo_hi_7, reg_pmp_0_cfg_r}; // @[package.scala:45:36] wire [2:0] hi_hi_7 = {reg_pmp_0_cfg_l, 2'h0}; // @[package.scala:45:36] wire [4:0] hi_10 = {hi_hi_7, reg_pmp_0_cfg_a}; // @[package.scala:45:36] wire [1:0] lo_hi_8 = {reg_pmp_1_cfg_x, reg_pmp_1_cfg_w}; // @[package.scala:45:36] wire [2:0] lo_8 = {lo_hi_8, reg_pmp_1_cfg_r}; // @[package.scala:45:36] wire [2:0] hi_hi_8 = {reg_pmp_1_cfg_l, 2'h0}; // @[package.scala:45:36] wire [4:0] hi_11 = {hi_hi_8, reg_pmp_1_cfg_a}; // @[package.scala:45:36] wire [1:0] lo_hi_9 = {reg_pmp_2_cfg_x, reg_pmp_2_cfg_w}; // @[package.scala:45:36] wire [2:0] lo_9 = {lo_hi_9, reg_pmp_2_cfg_r}; // @[package.scala:45:36] wire [2:0] hi_hi_9 = {reg_pmp_2_cfg_l, 2'h0}; // @[package.scala:45:36] wire [4:0] hi_12 = {hi_hi_9, reg_pmp_2_cfg_a}; // @[package.scala:45:36] wire [1:0] lo_hi_10 = {reg_pmp_3_cfg_x, reg_pmp_3_cfg_w}; // @[package.scala:45:36] wire [2:0] lo_10 = {lo_hi_10, reg_pmp_3_cfg_r}; // @[package.scala:45:36] wire [2:0] hi_hi_10 = {reg_pmp_3_cfg_l, 2'h0}; // @[package.scala:45:36] wire [4:0] hi_13 = {hi_hi_10, reg_pmp_3_cfg_a}; // @[package.scala:45:36] wire [1:0] lo_hi_11 = {reg_pmp_4_cfg_x, reg_pmp_4_cfg_w}; // @[package.scala:45:36] wire [2:0] lo_11 = {lo_hi_11, reg_pmp_4_cfg_r}; // @[package.scala:45:36] wire [2:0] hi_hi_11 = {reg_pmp_4_cfg_l, 2'h0}; // @[package.scala:45:36] wire [4:0] hi_14 = {hi_hi_11, reg_pmp_4_cfg_a}; // @[package.scala:45:36] wire [1:0] lo_hi_12 = {reg_pmp_5_cfg_x, reg_pmp_5_cfg_w}; // @[package.scala:45:36] wire [2:0] lo_12 = {lo_hi_12, reg_pmp_5_cfg_r}; // @[package.scala:45:36] wire [2:0] hi_hi_12 = {reg_pmp_5_cfg_l, 2'h0}; // @[package.scala:45:36] wire [4:0] hi_15 = {hi_hi_12, reg_pmp_5_cfg_a}; // @[package.scala:45:36] wire [1:0] lo_hi_13 = {reg_pmp_6_cfg_x, reg_pmp_6_cfg_w}; // @[package.scala:45:36] wire [2:0] lo_13 = {lo_hi_13, reg_pmp_6_cfg_r}; // @[package.scala:45:36] wire [2:0] hi_hi_13 = {reg_pmp_6_cfg_l, 2'h0}; // @[package.scala:45:36] wire [4:0] hi_16 = {hi_hi_13, reg_pmp_6_cfg_a}; // @[package.scala:45:36] wire [1:0] lo_hi_14 = {reg_pmp_7_cfg_x, reg_pmp_7_cfg_w}; // @[package.scala:45:36] wire [2:0] lo_14 = {lo_hi_14, reg_pmp_7_cfg_r}; // @[package.scala:45:36] wire [2:0] hi_hi_14 = {reg_pmp_7_cfg_l, 2'h0}; // @[package.scala:45:36] wire [4:0] hi_17 = {hi_hi_14, reg_pmp_7_cfg_a}; // @[package.scala:45:36] wire [15:0] lo_lo_7 = {hi_11, lo_8, hi_10, lo_7}; // @[package.scala:45:{27,36}] wire [15:0] lo_hi_15 = {hi_13, lo_10, hi_12, lo_9}; // @[package.scala:45:{27,36}] wire [31:0] lo_15 = {lo_hi_15, lo_lo_7}; // @[package.scala:45:27] wire [15:0] hi_lo_7 = {hi_15, lo_12, hi_14, lo_11}; // @[package.scala:45:{27,36}] wire [15:0] hi_hi_15 = {hi_17, lo_14, hi_16, lo_13}; // @[package.scala:45:{27,36}] wire [31:0] hi_18 = {hi_hi_15, hi_lo_7}; // @[package.scala:45:27] reg [63:0] reg_custom_0; // @[CSR.scala:798:43] assign io_customCSRs_0_value_0 = reg_custom_0; // @[CSR.scala:377:7, :798:43] wire _reg_custom_read_T = |io_rw_cmd_0; // @[CSR.scala:377:7, :799:26] wire _reg_custom_read_T_1 = io_rw_addr_0 == 12'h7C1; // @[CSR.scala:377:7, :799:50] assign reg_custom_read = _reg_custom_read_T & _reg_custom_read_T_1; // @[CSR.scala:799:{26,36,50}] assign io_customCSRs_0_ren_0 = reg_custom_read; // @[CSR.scala:377:7, :799:36] reg [63:0] reg_custom_1; // @[CSR.scala:798:43] assign io_customCSRs_1_value_0 = reg_custom_1; // @[CSR.scala:377:7, :798:43] wire [63:0] _reg_custom_1_T_2 = reg_custom_1; // @[CSR.scala:798:43, :1506:38] wire [63:0] _reg_custom_1_T_6 = reg_custom_1; // @[CSR.scala:798:43, :1531:39] wire _reg_custom_read_T_2 = |io_rw_cmd_0; // @[CSR.scala:377:7, :799:26] wire _reg_custom_read_T_3 = io_rw_addr_0 == 12'hF12; // @[CSR.scala:377:7, :799:50] assign reg_custom_read_1 = _reg_custom_read_T_2 & _reg_custom_read_T_3; // @[CSR.scala:799:{26,36,50}] assign io_customCSRs_1_ren_0 = reg_custom_read_1; // @[CSR.scala:377:7, :799:36] wire [12:0] decoded_addr_addr = {io_status_v_0, io_rw_addr_0}; // @[CSR.scala:377:7, :851:19] wire [11:0] decoded_addr_decoded_decoded_plaInput; // @[pla.scala:77:22] wire [11:0] decoded_addr_decoded_decoded_invInputs = ~decoded_addr_decoded_decoded_plaInput; // @[pla.scala:77:22, :78:21] wire [149:0] decoded_addr_decoded_decoded_invMatrixOutputs; // @[pla.scala:120:37] wire [149:0] decoded_addr_decoded_decoded; // @[pla.scala:81:23] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_4 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_5 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_8 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_9 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_14 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_15 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_18 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_19 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_22 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_24 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_25 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_28 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_29 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_32 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_33 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_36 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_37 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_40 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_41 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_44 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_45 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_48 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_49 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_52 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_53 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_57 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_59 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_60 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_63 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_64 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_67 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_68 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_71 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_72 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_75 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_76 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_79 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_80 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_83 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_86 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_87 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_90 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_91 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_94 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_95 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_98 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_99 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_102 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_103 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_106 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_107 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_110 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_111 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_114 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_117 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_118 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_121 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_122 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_125 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_126 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_129 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_130 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_133 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_134 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_137 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_138 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_141 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_142 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_145 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_148 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_149 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_1 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_2 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_3 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_8 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_9 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_10 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_11 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_14 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_15 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_16 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_17 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_22 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_23 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_28 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_29 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_30 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_31 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_36 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_37 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_38 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_39 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_44 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_45 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_46 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_47 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_52 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_53 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_54 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_55 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_57 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_58 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_59 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_60 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_61 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_62 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_67 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_68 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_69 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_70 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_75 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_76 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_77 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_78 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_79 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_80 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_81 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_83 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_84 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_85 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_90 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_91 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_92 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_93 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_98 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_99 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_100 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_101 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_106 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_107 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_108 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_109 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_114 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_115 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_116 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_121 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_122 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_123 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_124 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_129 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_130 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_131 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_132 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_137 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_138 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_139 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_140 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_145 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_146 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_147 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_1 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_2 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_3 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_4 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_5 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_6 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_8 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_9 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_10 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_11 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_12 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_14 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_15 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_16 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_17 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_18 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_19 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_20 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_22 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_23 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_24 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_25 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_26 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_27 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_36 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_37 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_38 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_39 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_40 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_41 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_42 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_43 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_52 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_53 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_54 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_55 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_56 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_57 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_58 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_59 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_60 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_61 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_62 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_63 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_64 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_65 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_66 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_75 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_76 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_77 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_78 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_79 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_80 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_81 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_83 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_84 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_85 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_86 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_87 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_88 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_89 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_98 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_99 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_100 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_101 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_102 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_103 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_104 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_105 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_114 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_115 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_116 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_117 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_118 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_119 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_120 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_129 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_130 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_131 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_132 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_133 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_134 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_135 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_136 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_145 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_146 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_147 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_148 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_149 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_1 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_2 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_3 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_4 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_5 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_6 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_7 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_8 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_9 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_10 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_11 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_12 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_14 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_15 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_16 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_17 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_18 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_19 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_20 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_21 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_22 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_23 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_24 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_25 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_26 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_27 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_28 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_29 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_30 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_31 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_32 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_33 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_34 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_35 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_52 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_53 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_54 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_55 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_56 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_57 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_58 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_75 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_76 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_77 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_78 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_83 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_84 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_85 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_86 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_87 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_88 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_89 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_90 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_91 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_92 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_93 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_94 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_95 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_96 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_97 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_114 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_115 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_116 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_117 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_118 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_119 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_120 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_121 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_122 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_123 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_124 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_125 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_126 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_127 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_128 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_1 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_2 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_3 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_4 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_5 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_6 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_7 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_8 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_9 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_10 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_11 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_12 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_13 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_14 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_15 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_16 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_17 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_18 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_20 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_21 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_51 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_52 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_53 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_54 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_56 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_83 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_83 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_84 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_85 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_86 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_87 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_88 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_89 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_90 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_91 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_92 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_93 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_94 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_95 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_96 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_97 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_98 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_99 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_100 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_101 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_102 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_103 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_104 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_105 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_106 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_107 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_108 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_109 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_110 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_111 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_112 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_114 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_114 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_115 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_116 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_117 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_118 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_119 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_120 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_121 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_122 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_123 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_124 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_125 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_126 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_127 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_128 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_129 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_130 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_131 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_132 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_133 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_134 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_135 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_136 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_137 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_138 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_139 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_140 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_141 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_142 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_143 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_145 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_145 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_146 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_147 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_148 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_1 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_2 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_3 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_4 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_5 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_6 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_7 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_13 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_14 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_15 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_16 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_17 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_18 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_19 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_21 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_21 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_22 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_23 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_24 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_25 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_26 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_27 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_28 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_29 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_30 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_31 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_32 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_33 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_34 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_35 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_36 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_37 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_38 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_39 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_40 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_41 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_42 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_43 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_44 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_45 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_46 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_47 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_48 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_49 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_50 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_56 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_57 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_58 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_59 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_60 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_61 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_62 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_63 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_64 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_65 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_66 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_67 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_68 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_69 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_70 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_71 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_72 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_73 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_74 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_75 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_76 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_77 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_78 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_79 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_80 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_82 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_82 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_83 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_84 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_85 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_86 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_87 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_88 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_89 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_90 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_91 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_92 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_93 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_94 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_95 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_96 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_97 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_98 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_99 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_100 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_101 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_102 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_103 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_104 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_105 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_106 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_107 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_108 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_109 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_110 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_111 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_113 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_113 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_114 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_115 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_116 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_117 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_118 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_119 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_120 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_121 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_122 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_123 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_124 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_125 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_126 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_127 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_128 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_129 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_130 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_131 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_132 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_133 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_134 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_135 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_136 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_137 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_138 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_139 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_140 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_141 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_142 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_144 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_144 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_145 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_146 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_147 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_1 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_2 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_3 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_4 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_5 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_6 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_7 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_8 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_9 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_10 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_11 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_12 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_13 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_14 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_15 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_16 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_17 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_18 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_19 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_21 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_21 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_22 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_23 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_24 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_25 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_26 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_27 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_28 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_29 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_30 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_31 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_32 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_33 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_34 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_35 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_36 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_37 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_38 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_39 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_40 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_41 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_42 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_43 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_44 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_45 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_46 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_47 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_48 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_49 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_50 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_51 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_52 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_53 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_54 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_55 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_81 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_82 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_83 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_84 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_85 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_86 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_87 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_88 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_89 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_90 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_91 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_92 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_93 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_94 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_95 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_96 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_97 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_98 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_99 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_100 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_101 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_102 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_103 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_104 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_105 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_106 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_107 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_108 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_109 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_110 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_111 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_112 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_113 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_114 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_115 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_116 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_117 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_118 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_119 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_120 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_121 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_122 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_123 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_124 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_125 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_126 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_127 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_128 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_129 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_130 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_131 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_132 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_133 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_134 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_135 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_136 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_137 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_138 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_139 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_140 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_141 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_142 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_143 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_144 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_145 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_146 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_147 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_1 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_2 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_112 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_113 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_114 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_115 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_116 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_117 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_118 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_119 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_120 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_121 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_122 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_123 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_124 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_125 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_126 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_127 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_128 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_129 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_130 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_131 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_132 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_133 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_134 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_135 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_136 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_137 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_138 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_139 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_140 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_141 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_142 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_1 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_2 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_3 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_4 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_5 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_6 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_7 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_7 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_8 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_9 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_10 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_12 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_13 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_112 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_111 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_112 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_113 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_114 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_115 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_116 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_117 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_118 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_119 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_120 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_121 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_122 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_123 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_124 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_125 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_126 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_127 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_128 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_129 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_130 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_131 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_132 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_133 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_134 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_135 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_136 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_137 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_138 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_139 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_140 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_1 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_2 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_3 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_3 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_4 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_6 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_7 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_6 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_7 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_8 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_9 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_12 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_13 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_10 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_11 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_12 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_13 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_14 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_15 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_18 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_20 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_19 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_20 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_19 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_20 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_21 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_22 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_23 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_24 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_25 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_26 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_27 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_28 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_29 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_30 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_31 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_32 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_33 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_34 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_35 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_36 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_37 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_38 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_39 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_40 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_41 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_42 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_43 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_44 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_45 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_46 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_47 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_48 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_49 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_50 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_55 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_54 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_55 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_53 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_54 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_55 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_56 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_57 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_58 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_59 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_60 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_61 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_62 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_63 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_64 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_65 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_66 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_67 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_68 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_79 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_77 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_78 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_79 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_80 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_81 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_82 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_83 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_84 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_85 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_86 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_87 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_88 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_89 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_90 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_91 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_92 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_93 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_94 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_95 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_96 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_97 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_98 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_99 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_100 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_101 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_102 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_103 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_104 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_105 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_106 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_1 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_3 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_2 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_3 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_5 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_7 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_4 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_5 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_6 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_7 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_11 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_13 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_8 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_9 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_10 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_11 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_12 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_13 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_16 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_20 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_17 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_18 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_14 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_15 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_16 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_17 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_18 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_19 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_20 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_21 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_22 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_23 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_24 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_25 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_26 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_27 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_28 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_29 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_30 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_31 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_32 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_33 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_34 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_35 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_36 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_37 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_38 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_39 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_40 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_41 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_42 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_43 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_44 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_45 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_53 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_51 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_52 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_46 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_47 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_48 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_49 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_50 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_51 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_52 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_53 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_54 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_55 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_56 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_57 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_58 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_59 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_60 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_61 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_62 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_63 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_64 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_65 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_66 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_67 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_75 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_81 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8}; // @[pla.scala:91:29, :98:53] wire [4:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo}; // @[pla.scala:98:53] wire [10:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T = {decoded_addr_decoded_decoded_andMatrixOutputs_hi, decoded_addr_decoded_decoded_andMatrixOutputs_lo}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_138_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_132 = decoded_addr_decoded_decoded_andMatrixOutputs_138_2; // @[pla.scala:98:70, :114:36] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_1 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_4 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_8 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_10 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_14 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_16 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_18 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_24 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_26 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_28 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_30 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_32 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_34 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_36 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_38 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_40 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_42 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_44 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_46 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_48 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_50 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_52 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_54 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_59 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_61 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_63 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_65 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_67 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_69 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_71 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_73 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_75 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_77 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_79 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_84 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_86 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_88 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_90 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_92 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_94 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_96 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_98 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_100 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_102 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_104 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_106 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_108 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_110 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_112 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_115 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_117 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_119 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_121 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_123 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_125 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_127 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_129 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_131 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_133 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_135 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_137 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_139 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_141 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_143 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_146 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_148 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_1 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_2 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_6 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_10 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_11 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_16 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_17 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_20 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_23 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_26 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_27 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_30 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_31 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_34 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_35 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_38 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_39 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_42 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_43 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_46 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_47 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_50 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_51 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_54 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_55 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_58 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_61 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_62 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_65 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_66 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_69 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_70 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_73 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_74 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_77 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_78 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_81 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_84 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_85 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_88 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_89 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_92 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_93 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_96 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_97 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_100 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_101 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_104 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_105 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_108 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_109 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_112 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_113 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_115 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_116 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_119 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_120 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_123 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_124 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_127 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_128 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_131 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_132 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_135 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_136 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_139 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_140 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_143 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_144 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_146 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_147 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_1, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_1}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_1 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_1 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_1, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_1}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_1 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_1, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_1}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_1 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_1, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_1}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_1 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_1, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_1}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_1 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_1, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_1}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_1 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_1, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_1}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_1 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_1, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_1}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_1 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_1, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_1}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_1 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_1, decoded_addr_decoded_decoded_andMatrixOutputs_lo_1}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_134_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_1; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_131 = decoded_addr_decoded_decoded_andMatrixOutputs_134_2; // @[pla.scala:98:70, :114:36] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_2 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_5 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_9 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_11 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_15 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_17 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_19 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_25 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_27 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_29 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_31 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_33 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_35 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_37 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_39 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_41 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_43 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_45 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_47 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_49 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_51 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_53 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_55 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_60 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_62 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_64 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_66 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_68 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_70 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_72 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_74 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_76 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_78 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_80 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_85 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_87 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_89 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_91 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_93 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_95 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_97 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_99 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_101 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_103 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_105 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_107 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_109 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_111 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_113 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_116 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_118 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_120 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_122 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_124 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_126 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_128 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_130 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_132 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_134 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_136 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_138 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_140 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_142 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_144 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_147 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_149 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_1 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_2, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_2}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_2 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_1, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_1}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_2 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_2, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_2}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_2 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_2, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_2}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_2 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_2, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_2}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_2 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_2, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_2}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_2 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_2, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_2}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_2 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_2, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_2}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_2 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_2, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_2}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_2 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_2, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_2}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_2 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_2, decoded_addr_decoded_decoded_andMatrixOutputs_lo_2}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_41_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_2; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_130 = decoded_addr_decoded_decoded_andMatrixOutputs_41_2; // @[pla.scala:98:70, :114:36] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_3 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_4 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_5 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_6 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_7 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_8 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_9 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_10 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_11 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_12 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_13 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_13 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_14 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_15 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_16 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_17 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_18 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_19 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_20 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_21 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_22 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_23 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_24 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_25 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_26 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_27 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_28 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_29 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_30 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_31 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_32 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_33 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_34 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_35 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_36 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_37 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_38 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_39 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_40 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_41 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_42 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_43 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_44 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_45 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_46 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_47 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_48 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_49 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_50 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_51 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_52 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_53 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_54 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_55 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_56 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_57 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_58 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_59 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_60 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_61 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_62 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_63 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_64 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_65 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_66 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_67 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_68 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_69 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_70 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_71 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_72 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_73 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_74 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_75 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_76 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_77 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_78 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_79 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_80 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_82 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_81 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_82 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_83 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_84 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_85 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_86 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_87 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_88 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_89 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_90 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_91 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_92 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_93 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_94 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_95 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_96 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_97 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_98 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_99 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_100 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_101 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_102 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_103 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_104 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_105 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_106 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_107 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_108 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_109 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_110 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_111 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_143 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_144 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_145 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_146 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_147 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_3 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_3, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_3}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_3 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_3, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_3}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_3 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_3, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_3}; // @[pla.scala:91:29, :98:53] wire [4:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_3 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_3, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_3}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_3 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_3, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_3}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_3 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_3, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_3}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_3 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_3, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_3}; // @[pla.scala:91:29, :98:53] wire [4:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_3 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_3, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_3}; // @[pla.scala:98:53] wire [9:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_3 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_3, decoded_addr_decoded_decoded_andMatrixOutputs_lo_3}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_1_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_3; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_35 = decoded_addr_decoded_decoded_andMatrixOutputs_1_2; // @[pla.scala:98:70, :114:36] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_4 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_5 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_6 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_12 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_18 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_19 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_20 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_24 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_25 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_26 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_27 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_32 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_33 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_34 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_35 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_40 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_41 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_42 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_43 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_48 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_49 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_50 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_51 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_56 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_63 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_64 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_65 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_66 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_71 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_72 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_73 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_74 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_86 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_87 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_88 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_89 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_94 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_95 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_96 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_97 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_102 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_103 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_104 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_105 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_110 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_111 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_112 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_113 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_117 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_118 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_119 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_120 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_125 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_126 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_127 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_128 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_133 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_134 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_135 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_136 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_141 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_142 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_143 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_144 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_148 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_149 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_2 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_4, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_3}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_4 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_2, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_2}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_4 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_4, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_4}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_4 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_4, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_4}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_4 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_4, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_4}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_3 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_4, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_4}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_4 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_3, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_4}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_4 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_4, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_4}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_4 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_4, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_4}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_4 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_4, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_4}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_4 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_4, decoded_addr_decoded_decoded_andMatrixOutputs_lo_4}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_89_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_4; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_33 = decoded_addr_decoded_decoded_andMatrixOutputs_89_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_3 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_5, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_4}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_5 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_3, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_3}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_5 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_5, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_5}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_5 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_5, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_5}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_5 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_5, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_5}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_4 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_5, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_5}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_5 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_4, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_5}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_5 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_5, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_5}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_5 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_5, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_5}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_5 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_5, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_5}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_5 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_5, decoded_addr_decoded_decoded_andMatrixOutputs_lo_5}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_123_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_5; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_27 = decoded_addr_decoded_decoded_andMatrixOutputs_123_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_6 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_6, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_5}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_6 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_6, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_6}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_6 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_6, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_6}; // @[pla.scala:91:29, :98:53] wire [4:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_6 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_6, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_6}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_5 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_6, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_6}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_6 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_5, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_6}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_6 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_6, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_6}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_6 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_6, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_6}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_6 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_6, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_6}; // @[pla.scala:98:53] wire [10:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_6 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_6, decoded_addr_decoded_decoded_andMatrixOutputs_lo_6}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_27_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_6; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_26 = decoded_addr_decoded_decoded_andMatrixOutputs_27_2; // @[pla.scala:98:70, :114:36] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_7 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_21 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_28 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_29 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_30 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_31 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_32 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_33 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_34 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_35 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_44 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_45 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_46 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_47 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_48 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_49 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_50 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_51 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_67 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_68 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_69 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_70 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_71 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_72 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_73 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_74 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_90 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_91 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_92 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_93 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_94 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_95 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_96 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_97 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_106 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_107 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_108 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_109 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_110 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_111 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_112 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_113 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_121 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_122 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_123 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_124 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_125 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_126 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_127 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_128 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_137 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_138 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_139 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_140 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_141 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_142 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_143 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_144 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_7 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_7, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_7}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_7 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_7, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_7}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_7 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_7, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_7}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_7 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_7, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_7}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_7 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_7, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_7}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_7 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_7, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_7}; // @[pla.scala:91:29, :98:53] wire [4:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_7 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_7, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_7}; // @[pla.scala:98:53] wire [8:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_7 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_7, decoded_addr_decoded_decoded_andMatrixOutputs_lo_7}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_0_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_7; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_23 = decoded_addr_decoded_decoded_andMatrixOutputs_0_2; // @[pla.scala:98:70, :114:36] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_8 = decoded_addr_decoded_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_9 = decoded_addr_decoded_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_10 = decoded_addr_decoded_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_11 = decoded_addr_decoded_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_12 = decoded_addr_decoded_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_51 = decoded_addr_decoded_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_52 = decoded_addr_decoded_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_53 = decoded_addr_decoded_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_54 = decoded_addr_decoded_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_56 = decoded_addr_decoded_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_82 = decoded_addr_decoded_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_4 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_7, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_6}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_8 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_4, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_4}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_7 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_8, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_8}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_8 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_7, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_8}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_8 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_8, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_8}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_6 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_8, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_8}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_8 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_6, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_8}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_8 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_8, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_8}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_8 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_8, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_8}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_8 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_8, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_8}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_8 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_8, decoded_addr_decoded_decoded_andMatrixOutputs_lo_8}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_92_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_8; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_32 = decoded_addr_decoded_decoded_andMatrixOutputs_92_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_5 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_8, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_7}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_9 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_5, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_5}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_8 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_9, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_9}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_9 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_8, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_9}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_9 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_9, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_9}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_7 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_9, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_9}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_9 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_7, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_9}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_9 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_9, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_9}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_9 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_9, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_9}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_9 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_9, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_9}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_9 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_9, decoded_addr_decoded_decoded_andMatrixOutputs_lo_9}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_59_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_9; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_28 = decoded_addr_decoded_decoded_andMatrixOutputs_59_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_6 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_9, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_8}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_10 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_6, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_6}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_9 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_10, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_10}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_10 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_9, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_10}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_10 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_10, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_10}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_8 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_10, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_10}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_10 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_8, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_10}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_10 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_10, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_10}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_10 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_10, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_10}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_10 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_10, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_10}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_10 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_10, decoded_addr_decoded_decoded_andMatrixOutputs_lo_10}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_24_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_10; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_31 = decoded_addr_decoded_decoded_andMatrixOutputs_24_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_7 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_10, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_9}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_11 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_7, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_7}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_10 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_11, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_11}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_11 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_10, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_11}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_11 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_11, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_11}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_9 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_11, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_11}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_11 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_9, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_11}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_11 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_11, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_11}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_11 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_11, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_11}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_11 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_11, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_11}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_11 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_11, decoded_addr_decoded_decoded_andMatrixOutputs_lo_11}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_116_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_11; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_30 = decoded_addr_decoded_decoded_andMatrixOutputs_116_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_12 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_12, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_11}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_11 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_12, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_12}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_12 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_11, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_12}; // @[pla.scala:91:29, :98:53] wire [4:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_12 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_12, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_12}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_12 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_12, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_12}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_12 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_12, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_12}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_12 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_12, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_12}; // @[pla.scala:91:29, :98:53] wire [4:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_12 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_12, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_12}; // @[pla.scala:98:53] wire [9:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_12 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_12, decoded_addr_decoded_decoded_andMatrixOutputs_lo_12}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_121_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_12; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_34 = decoded_addr_decoded_decoded_andMatrixOutputs_121_2; // @[pla.scala:98:70, :114:36] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_13 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_56 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_57 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_58 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_59 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_60 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_61 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_62 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_63 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_64 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_65 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_66 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_67 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_68 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_69 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_70 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_71 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_72 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_73 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_74 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_75 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_76 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_77 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_78 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_79 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_80 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_82 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_13 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_13, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_13}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_13 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_13, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_13}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_13 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_13, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_13}; // @[pla.scala:91:29, :98:53] wire [4:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_13 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_13, decoded_addr_decoded_decoded_andMatrixOutputs_lo_13}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_74_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_13; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_29 = decoded_addr_decoded_decoded_andMatrixOutputs_74_2; // @[pla.scala:98:70, :114:36] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_12 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_13 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_14 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_15 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_16 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_17 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_19 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_20 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_21 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_22 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_21 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_22 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_23 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_24 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_25 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_26 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_27 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_28 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_29 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_30 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_31 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_32 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_33 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_34 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_35 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_36 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_37 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_38 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_39 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_40 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_41 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_42 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_43 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_44 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_45 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_46 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_47 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_48 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_49 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_50 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_51 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_52 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_55 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_56 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_57 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_56 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_57 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_58 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_59 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_60 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_61 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_62 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_63 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_64 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_65 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_66 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_67 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_68 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_69 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_70 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_71 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_72 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_73 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_74 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_75 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_76 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_77 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_80 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_82 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_81 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_80 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_81 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_82 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_83 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_84 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_85 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_86 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_87 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_88 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_89 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_90 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_91 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_92 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_93 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_94 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_95 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_96 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_97 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_98 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_99 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_100 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_101 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_102 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_103 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_104 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_105 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_106 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_107 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_108 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_109 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_143 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_142 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_143 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_144 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_145 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_8 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_12, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_10}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_13 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_8, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_8}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_12 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_13, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_13}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_13 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_12, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_13}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_14 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_13, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_13}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_10 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_14, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_14}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_13 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_10, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_13}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_13 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_14, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_14}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_14 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_13, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_14}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_14 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_14, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_13}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_14 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_14, decoded_addr_decoded_decoded_andMatrixOutputs_lo_14}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_114_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_14; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_144 = decoded_addr_decoded_decoded_andMatrixOutputs_114_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_9 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_13, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_11}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_14 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_9, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_9}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_13 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_14, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_14}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_14 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_13, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_14}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_15 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_14, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_14}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_11 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_15, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_15}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_14 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_11, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_14}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_14 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_15, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_15}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_15 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_14, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_15}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_15 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_15, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_14}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_15 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_15, decoded_addr_decoded_decoded_andMatrixOutputs_lo_15}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_104_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_15; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_145 = decoded_addr_decoded_decoded_andMatrixOutputs_104_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_10 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_14, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_12}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_15 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_10, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_10}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_14 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_15, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_15}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_15 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_14, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_15}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_16 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_15, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_15}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_12 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_16, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_16}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_15 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_12, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_15}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_15 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_16, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_16}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_16 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_15, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_16}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_16 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_16, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_15}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_16 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_16, decoded_addr_decoded_decoded_andMatrixOutputs_lo_16}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_82_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_16; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_24 = decoded_addr_decoded_decoded_andMatrixOutputs_82_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_11 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_15, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_13}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_16 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_11, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_11}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_15 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_16, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_16}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_16 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_15, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_16}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_17 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_16, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_16}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_13 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_17, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_17}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_16 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_13, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_16}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_16 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_17, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_17}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_17 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_16, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_17}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_17 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_17, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_16}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_17 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_17, decoded_addr_decoded_decoded_andMatrixOutputs_lo_17}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_28_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_17; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_25 = decoded_addr_decoded_decoded_andMatrixOutputs_28_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_12 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_16, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_14}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_17 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_12, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_12}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_16 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_17, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_17}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_17 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_16, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_17}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_18 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_17, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_17}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_14 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_18, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_18}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_17 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_14, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_17}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_17 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_18, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_18}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_18 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_17, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_18}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_18 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_18, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_17}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_18 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_18, decoded_addr_decoded_decoded_andMatrixOutputs_lo_18}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_91_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_18; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_141 = decoded_addr_decoded_decoded_andMatrixOutputs_91_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_13 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_17, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_15}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_18 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_13, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_13}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_17 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_18, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_18}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_18 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_17, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_18}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_19 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_18, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_18}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_15 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_19, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_19}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_18 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_15, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_18}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_18 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_19, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_19}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_19 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_18, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_19}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_19 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_19, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_18}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_19 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_19, decoded_addr_decoded_decoded_andMatrixOutputs_lo_19}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_68_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_19; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_143 = decoded_addr_decoded_decoded_andMatrixOutputs_68_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_19 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_18, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_16}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_18 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_19, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_19}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_19 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_18, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_19}; // @[pla.scala:90:45, :98:53] wire [4:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_20 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_19, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_19}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_16 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_20, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_20}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_19 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_16, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_19}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_19 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_20, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_20}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_20 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_19, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_20}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_20 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_20, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_19}; // @[pla.scala:98:53] wire [10:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_20 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_20, decoded_addr_decoded_decoded_andMatrixOutputs_lo_20}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_84_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_20; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_39 = decoded_addr_decoded_decoded_andMatrixOutputs_84_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_20 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_20, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_20}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_20 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_20, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_20}; // @[pla.scala:90:45, :98:53] wire [3:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_21 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_20, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_20}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_20 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_21, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_21}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_20 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_21, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_21}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_21 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_20, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_21}; // @[pla.scala:91:29, :98:53] wire [4:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_21 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_21, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_20}; // @[pla.scala:98:53] wire [8:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_21 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_21, decoded_addr_decoded_decoded_andMatrixOutputs_lo_21}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_40_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_21; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_36 = decoded_addr_decoded_decoded_andMatrixOutputs_40_2; // @[pla.scala:98:70, :114:36] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_22 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_23 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_23 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_24 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_25 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_26 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_27 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_28 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_29 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_30 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_31 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_32 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_33 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_34 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_35 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_36 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_37 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_38 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_39 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_40 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_41 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_42 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_43 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_44 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_45 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_46 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_47 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_48 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_49 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_50 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_57 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_58 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_58 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_59 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_60 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_61 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_62 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_63 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_64 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_65 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_66 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_67 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_68 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_69 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_70 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_71 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_72 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_73 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_74 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_75 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_76 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_77 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_78 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_79 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_81 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_21 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_19, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_17}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_19 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_21, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_21}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_21 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_19, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_21}; // @[pla.scala:90:45, :98:53] wire [4:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_22 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_21, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_21}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_17 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_22, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_22}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_21 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_17, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_21}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_21 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_22, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_22}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_22 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_21, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_22}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_22 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_22, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_21}; // @[pla.scala:98:53] wire [10:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_22 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_22, decoded_addr_decoded_decoded_andMatrixOutputs_lo_22}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_34_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_22; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_129 = decoded_addr_decoded_decoded_andMatrixOutputs_34_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_22 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_20, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_18}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_20 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_22, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_22}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_22 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_20, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_22}; // @[pla.scala:90:45, :98:53] wire [4:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_23 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_22, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_22}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_18 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_23, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_23}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_22 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_18, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_22}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_22 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_23, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_23}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_23 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_22, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_23}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_23 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_23, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_22}; // @[pla.scala:98:53] wire [10:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_23 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_23, decoded_addr_decoded_decoded_andMatrixOutputs_lo_23}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_136_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_23; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_126 = decoded_addr_decoded_decoded_andMatrixOutputs_136_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_14 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_21, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_19}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_23 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_14, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_14}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_21 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_23, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_23}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_23 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_21, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_23}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_24 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_23, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_23}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_19 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_24, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_24}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_23 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_19, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_23}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_23 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_24, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_24}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_24 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_23, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_24}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_24 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_24, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_23}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_24 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_24, decoded_addr_decoded_decoded_andMatrixOutputs_lo_24}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_55_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_24; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_123 = decoded_addr_decoded_decoded_andMatrixOutputs_55_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_15 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_22, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_20}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_24 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_15, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_15}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_22 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_24, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_24}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_24 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_22, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_24}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_25 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_24, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_24}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_20 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_25, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_25}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_24 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_20, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_24}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_24 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_25, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_25}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_25 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_24, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_25}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_25 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_25, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_24}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_25 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_25, decoded_addr_decoded_decoded_andMatrixOutputs_lo_25}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_105_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_25; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_120 = decoded_addr_decoded_decoded_andMatrixOutputs_105_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_16 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_23, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_21}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_25 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_16, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_16}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_23 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_25, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_25}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_25 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_23, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_25}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_26 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_25, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_25}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_21 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_26, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_26}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_25 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_21, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_25}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_25 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_26, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_26}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_26 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_25, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_26}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_26 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_26, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_25}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_26 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_26, decoded_addr_decoded_decoded_andMatrixOutputs_lo_26}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_109_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_26; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_117 = decoded_addr_decoded_decoded_andMatrixOutputs_109_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_17 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_24, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_22}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_26 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_17, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_17}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_24 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_26, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_26}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_26 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_24, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_26}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_27 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_26, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_26}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_22 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_27, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_27}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_26 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_22, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_26}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_26 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_27, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_27}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_27 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_26, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_27}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_27 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_27, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_26}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_27 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_27, decoded_addr_decoded_decoded_andMatrixOutputs_lo_27}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_7_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_27; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_114 = decoded_addr_decoded_decoded_andMatrixOutputs_7_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_18 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_25, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_23}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_27 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_18, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_18}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_25 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_27, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_27}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_27 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_25, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_27}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_28 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_27, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_27}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_23 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_28, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_28}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_27 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_23, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_27}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_27 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_28, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_28}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_28 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_27, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_28}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_28 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_28, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_27}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_28 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_28, decoded_addr_decoded_decoded_andMatrixOutputs_lo_28}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_47_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_28; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_111 = decoded_addr_decoded_decoded_andMatrixOutputs_47_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_19 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_26, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_24}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_28 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_19, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_19}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_26 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_28, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_28}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_28 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_26, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_28}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_29 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_28, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_28}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_24 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_29, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_29}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_28 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_24, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_28}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_28 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_29, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_29}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_29 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_28, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_29}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_29 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_29, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_28}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_29 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_29, decoded_addr_decoded_decoded_andMatrixOutputs_lo_29}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_141_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_29; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_108 = decoded_addr_decoded_decoded_andMatrixOutputs_141_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_20 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_27, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_25}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_29 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_20, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_20}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_27 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_29, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_29}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_29 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_27, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_29}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_30 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_29, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_29}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_25 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_30, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_30}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_29 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_25, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_29}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_29 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_30, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_30}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_30 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_29, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_30}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_30 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_30, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_29}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_30 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_30, decoded_addr_decoded_decoded_andMatrixOutputs_lo_30}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_11_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_30; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_105 = decoded_addr_decoded_decoded_andMatrixOutputs_11_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_21 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_28, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_26}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_30 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_21, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_21}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_28 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_30, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_30}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_30 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_28, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_30}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_31 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_30, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_30}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_26 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_31, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_31}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_30 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_26, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_30}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_30 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_31, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_31}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_31 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_30, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_31}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_31 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_31, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_30}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_31 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_31, decoded_addr_decoded_decoded_andMatrixOutputs_lo_31}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_118_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_31; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_102 = decoded_addr_decoded_decoded_andMatrixOutputs_118_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_22 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_29, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_27}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_31 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_22, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_22}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_29 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_31, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_31}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_31 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_29, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_31}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_32 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_31, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_31}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_27 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_32, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_32}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_31 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_27, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_31}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_31 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_32, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_32}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_32 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_31, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_32}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_32 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_32, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_31}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_32 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_32, decoded_addr_decoded_decoded_andMatrixOutputs_lo_32}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_120_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_32; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_99 = decoded_addr_decoded_decoded_andMatrixOutputs_120_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_23 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_30, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_28}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_32 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_23, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_23}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_30 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_32, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_32}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_32 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_30, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_32}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_33 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_32, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_32}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_28 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_33, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_33}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_32 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_28, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_32}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_32 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_33, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_33}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_33 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_32, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_33}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_33 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_33, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_32}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_33 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_33, decoded_addr_decoded_decoded_andMatrixOutputs_lo_33}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_139_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_33; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_96 = decoded_addr_decoded_decoded_andMatrixOutputs_139_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_24 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_31, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_29}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_33 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_24, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_24}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_31 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_33, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_33}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_33 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_31, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_33}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_34 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_33, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_33}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_29 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_34, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_34}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_33 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_29, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_33}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_33 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_34, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_34}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_34 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_33, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_34}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_34 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_34, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_33}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_34 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_34, decoded_addr_decoded_decoded_andMatrixOutputs_lo_34}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_86_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_34; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_93 = decoded_addr_decoded_decoded_andMatrixOutputs_86_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_25 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_32, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_30}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_34 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_25, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_25}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_32 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_34, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_34}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_34 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_32, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_34}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_35 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_34, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_34}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_30 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_35, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_35}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_34 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_30, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_34}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_34 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_35, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_35}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_35 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_34, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_35}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_35 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_35, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_34}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_35 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_35, decoded_addr_decoded_decoded_andMatrixOutputs_lo_35}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_8_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_35; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_90 = decoded_addr_decoded_decoded_andMatrixOutputs_8_2; // @[pla.scala:98:70, :114:36] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_36 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_37 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_38 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_39 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_40 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_41 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_42 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_43 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_44 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_45 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_46 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_47 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_48 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_49 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_50 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_51 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_59 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_60 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_61 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_62 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_63 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_64 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_65 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_66 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_67 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_68 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_69 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_70 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_71 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_72 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_73 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_74 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_79 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_80 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_81 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_98 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_99 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_100 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_101 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_102 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_103 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_104 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_105 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_106 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_107 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_108 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_109 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_110 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_111 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_112 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_113 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_129 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_130 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_131 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_132 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_133 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_134 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_135 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_136 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_137 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_138 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_139 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_140 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_141 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_142 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_143 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_144 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_145 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_146 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_147 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_148 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_149 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_26 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_33, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_31}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_35 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_26, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_26}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_33 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_35, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_35}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_35 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_33, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_35}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_36 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_35, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_35}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_31 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_36, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_36}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_35 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_31, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_35}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_35 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_36, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_36}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_36 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_35, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_36}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_36 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_36, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_35}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_36 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_36, decoded_addr_decoded_decoded_andMatrixOutputs_lo_36}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_61_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_36; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_87 = decoded_addr_decoded_decoded_andMatrixOutputs_61_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_27 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_34, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_32}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_36 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_27, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_27}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_34 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_36, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_36}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_36 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_34, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_36}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_37 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_36, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_36}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_32 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_37, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_37}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_36 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_32, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_36}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_36 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_37, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_37}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_37 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_36, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_37}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_37 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_37, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_36}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_37 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_37, decoded_addr_decoded_decoded_andMatrixOutputs_lo_37}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_83_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_37; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_84 = decoded_addr_decoded_decoded_andMatrixOutputs_83_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_28 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_35, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_33}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_37 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_28, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_28}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_35 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_37, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_37}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_37 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_35, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_37}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_38 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_37, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_37}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_33 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_38, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_38}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_37 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_33, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_37}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_37 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_38, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_38}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_38 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_37, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_38}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_38 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_38, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_37}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_38 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_38, decoded_addr_decoded_decoded_andMatrixOutputs_lo_38}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_129_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_38; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_81 = decoded_addr_decoded_decoded_andMatrixOutputs_129_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_29 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_36, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_34}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_38 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_29, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_29}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_36 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_38, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_38}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_38 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_36, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_38}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_39 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_38, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_38}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_34 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_39, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_39}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_38 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_34, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_38}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_38 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_39, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_39}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_39 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_38, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_39}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_39 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_39, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_38}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_39 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_39, decoded_addr_decoded_decoded_andMatrixOutputs_lo_39}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_17_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_39; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_78 = decoded_addr_decoded_decoded_andMatrixOutputs_17_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_30 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_37, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_35}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_39 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_30, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_30}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_37 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_39, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_39}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_39 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_37, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_39}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_40 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_39, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_39}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_35 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_40, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_40}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_39 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_35, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_39}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_39 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_40, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_40}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_40 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_39, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_40}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_40 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_40, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_39}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_40 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_40, decoded_addr_decoded_decoded_andMatrixOutputs_lo_40}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_87_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_40; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_75 = decoded_addr_decoded_decoded_andMatrixOutputs_87_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_31 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_38, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_36}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_40 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_31, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_31}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_38 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_40, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_40}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_40 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_38, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_40}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_41 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_40, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_40}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_36 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_41, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_41}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_40 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_36, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_40}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_40 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_41, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_41}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_41 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_40, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_41}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_41 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_41, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_40}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_41 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_41, decoded_addr_decoded_decoded_andMatrixOutputs_lo_41}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_133_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_41; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_72 = decoded_addr_decoded_decoded_andMatrixOutputs_133_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_32 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_39, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_37}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_41 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_32, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_32}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_39 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_41, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_41}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_41 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_39, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_41}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_42 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_41, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_41}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_37 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_42, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_42}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_41 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_37, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_41}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_41 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_42, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_42}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_42 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_41, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_42}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_42 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_42, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_41}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_42 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_42, decoded_addr_decoded_decoded_andMatrixOutputs_lo_42}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_142_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_42; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_69 = decoded_addr_decoded_decoded_andMatrixOutputs_142_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_33 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_40, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_38}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_42 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_33, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_33}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_40 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_42, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_42}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_42 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_40, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_42}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_43 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_42, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_42}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_38 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_43, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_43}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_42 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_38, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_42}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_42 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_43, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_43}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_43 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_42, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_43}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_43 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_43, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_42}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_43 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_43, decoded_addr_decoded_decoded_andMatrixOutputs_lo_43}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_22_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_43; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_66 = decoded_addr_decoded_decoded_andMatrixOutputs_22_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_34 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_41, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_39}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_43 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_34, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_34}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_41 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_43, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_43}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_43 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_41, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_43}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_44 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_43, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_43}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_39 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_44, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_44}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_43 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_39, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_43}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_43 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_44, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_44}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_44 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_43, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_44}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_44 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_44, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_43}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_44 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_44, decoded_addr_decoded_decoded_andMatrixOutputs_lo_44}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_94_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_44; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_63 = decoded_addr_decoded_decoded_andMatrixOutputs_94_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_35 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_42, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_40}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_44 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_35, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_35}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_42 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_44, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_44}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_44 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_42, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_44}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_45 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_44, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_44}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_40 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_45, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_45}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_44 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_40, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_44}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_44 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_45, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_45}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_45 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_44, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_45}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_45 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_45, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_44}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_45 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_45, decoded_addr_decoded_decoded_andMatrixOutputs_lo_45}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_65_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_45; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_60 = decoded_addr_decoded_decoded_andMatrixOutputs_65_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_36 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_43, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_41}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_45 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_36, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_36}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_43 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_45, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_45}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_45 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_43, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_45}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_46 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_45, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_45}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_41 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_46, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_46}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_45 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_41, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_45}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_45 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_46, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_46}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_46 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_45, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_46}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_46 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_46, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_45}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_46 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_46, decoded_addr_decoded_decoded_andMatrixOutputs_lo_46}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_36_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_46; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_57 = decoded_addr_decoded_decoded_andMatrixOutputs_36_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_37 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_44, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_42}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_46 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_37, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_37}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_44 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_46, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_46}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_46 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_44, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_46}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_47 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_46, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_46}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_42 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_47, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_47}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_46 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_42, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_46}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_46 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_47, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_47}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_47 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_46, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_47}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_47 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_47, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_46}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_47 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_47, decoded_addr_decoded_decoded_andMatrixOutputs_lo_47}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_33_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_47; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_54 = decoded_addr_decoded_decoded_andMatrixOutputs_33_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_38 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_45, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_43}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_47 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_38, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_38}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_45 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_47, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_47}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_47 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_45, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_47}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_48 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_47, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_47}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_43 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_48, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_48}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_47 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_43, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_47}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_47 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_48, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_48}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_48 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_47, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_48}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_48 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_48, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_47}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_48 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_48, decoded_addr_decoded_decoded_andMatrixOutputs_lo_48}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_63_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_48; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_51 = decoded_addr_decoded_decoded_andMatrixOutputs_63_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_39 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_46, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_44}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_48 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_39, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_39}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_46 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_48, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_48}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_48 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_46, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_48}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_49 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_48, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_48}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_44 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_49, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_49}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_48 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_44, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_48}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_48 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_49, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_49}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_49 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_48, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_49}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_49 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_49, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_48}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_49 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_49, decoded_addr_decoded_decoded_andMatrixOutputs_lo_49}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_39_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_49; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_48 = decoded_addr_decoded_decoded_andMatrixOutputs_39_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_40 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_47, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_45}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_49 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_40, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_40}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_47 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_49, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_49}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_49 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_47, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_49}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_50 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_49, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_49}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_45 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_50, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_50}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_49 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_45, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_49}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_49 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_50, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_50}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_50 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_49, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_50}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_50 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_50, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_49}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_50 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_50, decoded_addr_decoded_decoded_andMatrixOutputs_lo_50}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_32_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_50; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_45 = decoded_addr_decoded_decoded_andMatrixOutputs_32_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_41 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_48, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_46}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_50 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_41, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_41}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_48 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_50, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_50}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_50 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_48, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_50}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_51 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_50, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_50}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_46 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_51, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_51}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_50 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_46, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_50}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_50 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_51, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_51}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_51 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_50, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_51}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_51 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_51, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_50}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_51 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_51, decoded_addr_decoded_decoded_andMatrixOutputs_lo_51}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_144_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_51; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_42 = decoded_addr_decoded_decoded_andMatrixOutputs_144_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_42 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_49, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_47}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_51 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_42, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_42}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_49 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_51, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_51}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_51 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_49, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_51}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_52 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_51, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_51}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_47 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_52, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_52}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_51 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_47, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_51}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_51 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_52, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_52}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_52 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_51, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_52}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_52 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_52, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_51}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_52 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_52, decoded_addr_decoded_decoded_andMatrixOutputs_lo_52}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_66_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_52; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_140 = decoded_addr_decoded_decoded_andMatrixOutputs_66_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_43 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_50, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_48}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_52 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_43, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_43}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_50 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_52, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_52}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_52 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_50, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_52}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_53 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_52, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_52}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_48 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_53, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_53}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_52 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_48, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_52}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_52 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_53, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_53}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_53 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_52, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_53}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_53 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_53, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_52}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_53 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_53, decoded_addr_decoded_decoded_andMatrixOutputs_lo_53}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_106_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_53; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_139 = decoded_addr_decoded_decoded_andMatrixOutputs_106_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_44 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_51, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_49}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_53 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_44, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_44}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_51 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_53, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_53}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_53 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_51, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_53}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_54 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_53, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_53}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_49 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_54, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_54}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_53 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_49, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_53}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_53 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_54, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_54}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_54 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_53, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_54}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_54 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_54, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_53}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_54 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_54, decoded_addr_decoded_decoded_andMatrixOutputs_lo_54}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_80_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_54; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_137 = decoded_addr_decoded_decoded_andMatrixOutputs_80_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_45 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_52, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_50}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_54 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_45, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_45}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_52 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_54, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_54}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_54 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_52, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_54}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_55 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_54, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_54}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_50 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_55, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_55}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_54 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_50, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_54}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_54 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_55, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_55}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_55 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_54, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_55}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_55 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_55, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_54}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_55 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_55, decoded_addr_decoded_decoded_andMatrixOutputs_lo_55}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_122_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_55; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_138 = decoded_addr_decoded_decoded_andMatrixOutputs_122_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_55 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_55, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_53}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_53 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_55, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_55}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_55 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_53, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_55}; // @[pla.scala:90:45, :98:53] wire [4:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_56 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_55, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_55}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_55 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_56, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_56}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_55 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_56, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_56}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_56 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_55, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_56}; // @[pla.scala:91:29, :98:53] wire [4:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_56 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_56, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_55}; // @[pla.scala:98:53] wire [9:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_56 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_56, decoded_addr_decoded_decoded_andMatrixOutputs_lo_56}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_119_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_56; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_142 = decoded_addr_decoded_decoded_andMatrixOutputs_119_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_56 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_54, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_51}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_54 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_56, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_56}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_56 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_54, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_56}; // @[pla.scala:90:45, :98:53] wire [4:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_57 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_56, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_56}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_51 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_57, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_57}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_56 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_51, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_56}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_56 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_57, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_57}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_57 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_56, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_57}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_57 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_57, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_56}; // @[pla.scala:98:53] wire [10:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_57 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_57, decoded_addr_decoded_decoded_andMatrixOutputs_lo_57}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_67_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_57; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_22 = decoded_addr_decoded_decoded_andMatrixOutputs_67_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_57 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_55, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_52}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_55 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_57, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_57}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_57 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_55, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_57}; // @[pla.scala:90:45, :98:53] wire [4:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_58 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_57, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_57}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_52 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_58, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_58}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_57 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_52, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_57}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_57 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_58, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_58}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_58 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_57, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_58}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_58 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_58, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_57}; // @[pla.scala:98:53] wire [10:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_58 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_58, decoded_addr_decoded_decoded_andMatrixOutputs_lo_58}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_48_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_58; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_21 = decoded_addr_decoded_decoded_andMatrixOutputs_48_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_46 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_56, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_53}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_58 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_46, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_46}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_56 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_58, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_58}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_58 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_56, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_58}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_59 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_58, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_58}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_53 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_59, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_59}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_58 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_53, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_58}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_58 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_59, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_59}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_59 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_58, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_59}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_59 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_59, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_58}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_59 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_59, decoded_addr_decoded_decoded_andMatrixOutputs_lo_59}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_10_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_59; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_20 = decoded_addr_decoded_decoded_andMatrixOutputs_10_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_47 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_57, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_54}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_59 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_47, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_47}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_57 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_59, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_59}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_59 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_57, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_59}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_60 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_59, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_59}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_54 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_60, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_60}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_59 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_54, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_59}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_59 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_60, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_60}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_60 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_59, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_60}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_60 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_60, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_59}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_60 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_60, decoded_addr_decoded_decoded_andMatrixOutputs_lo_60}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_45_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_60; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_19 = decoded_addr_decoded_decoded_andMatrixOutputs_45_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_48 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_58, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_55}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_60 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_48, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_48}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_58 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_60, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_60}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_60 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_58, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_60}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_61 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_60, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_60}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_55 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_61, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_61}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_60 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_55, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_60}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_60 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_61, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_61}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_61 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_60, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_61}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_61 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_61, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_60}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_61 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_61, decoded_addr_decoded_decoded_andMatrixOutputs_lo_61}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_18_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_61; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_18 = decoded_addr_decoded_decoded_andMatrixOutputs_18_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_49 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_59, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_56}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_61 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_49, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_49}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_59 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_61, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_61}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_61 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_59, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_61}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_62 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_61, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_61}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_56 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_62, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_62}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_61 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_56, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_61}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_61 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_62, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_62}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_62 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_61, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_62}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_62 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_62, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_61}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_62 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_62, decoded_addr_decoded_decoded_andMatrixOutputs_lo_62}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_88_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_62; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_17 = decoded_addr_decoded_decoded_andMatrixOutputs_88_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_50 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_60, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_57}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_62 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_50, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_50}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_60 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_62, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_62}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_62 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_60, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_62}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_63 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_62, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_62}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_57 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_63, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_63}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_62 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_57, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_62}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_62 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_63, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_63}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_63 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_62, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_63}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_63 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_63, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_62}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_63 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_63, decoded_addr_decoded_decoded_andMatrixOutputs_lo_63}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_57_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_63; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_16 = decoded_addr_decoded_decoded_andMatrixOutputs_57_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_51 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_61, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_58}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_63 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_51, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_51}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_61 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_63, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_63}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_63 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_61, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_63}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_64 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_63, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_63}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_58 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_64, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_64}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_63 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_58, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_63}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_63 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_64, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_64}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_64 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_63, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_64}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_64 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_64, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_63}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_64 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_64, decoded_addr_decoded_decoded_andMatrixOutputs_lo_64}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_85_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_64; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_15 = decoded_addr_decoded_decoded_andMatrixOutputs_85_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_52 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_62, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_59}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_64 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_52, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_52}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_62 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_64, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_64}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_64 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_62, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_64}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_65 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_64, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_64}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_59 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_65, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_65}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_64 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_59, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_64}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_64 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_65, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_65}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_65 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_64, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_65}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_65 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_65, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_64}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_65 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_65, decoded_addr_decoded_decoded_andMatrixOutputs_lo_65}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_100_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_65; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_14 = decoded_addr_decoded_decoded_andMatrixOutputs_100_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_53 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_63, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_60}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_65 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_53, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_53}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_63 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_65, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_65}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_65 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_63, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_65}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_66 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_65, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_65}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_60 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_66, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_66}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_65 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_60, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_65}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_65 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_66, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_66}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_66 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_65, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_66}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_66 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_66, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_65}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_66 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_66, decoded_addr_decoded_decoded_andMatrixOutputs_lo_66}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_111_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_66; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_13 = decoded_addr_decoded_decoded_andMatrixOutputs_111_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_54 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_64, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_61}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_66 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_54, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_54}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_64 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_66, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_66}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_66 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_64, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_66}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_67 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_66, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_66}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_61 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_67, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_67}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_66 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_61, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_66}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_66 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_67, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_67}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_67 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_66, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_67}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_67 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_67, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_66}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_67 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_67, decoded_addr_decoded_decoded_andMatrixOutputs_lo_67}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_93_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_67; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_12 = decoded_addr_decoded_decoded_andMatrixOutputs_93_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_55 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_65, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_62}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_67 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_55, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_55}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_65 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_67, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_67}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_67 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_65, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_67}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_68 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_67, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_67}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_62 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_68, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_68}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_67 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_62, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_67}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_67 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_68, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_68}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_68 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_67, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_68}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_68 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_68, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_67}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_68 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_68, decoded_addr_decoded_decoded_andMatrixOutputs_lo_68}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_137_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_68; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_11 = decoded_addr_decoded_decoded_andMatrixOutputs_137_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_56 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_66, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_63}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_68 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_56, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_56}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_66 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_68, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_68}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_68 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_66, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_68}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_69 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_68, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_68}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_63 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_69, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_69}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_68 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_63, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_68}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_68 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_69, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_69}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_69 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_68, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_69}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_69 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_69, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_68}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_69 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_69, decoded_addr_decoded_decoded_andMatrixOutputs_lo_69}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_72_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_69; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_10 = decoded_addr_decoded_decoded_andMatrixOutputs_72_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_57 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_67, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_64}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_69 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_57, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_57}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_67 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_69, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_69}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_69 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_67, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_69}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_70 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_69, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_69}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_64 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_70, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_70}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_69 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_64, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_69}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_69 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_70, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_70}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_70 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_69, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_70}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_70 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_70, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_69}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_70 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_70, decoded_addr_decoded_decoded_andMatrixOutputs_lo_70}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_42_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_70; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_9 = decoded_addr_decoded_decoded_andMatrixOutputs_42_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_58 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_68, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_65}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_70 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_58, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_58}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_68 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_70, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_70}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_70 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_68, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_70}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_71 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_70, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_70}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_65 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_71, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_71}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_70 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_65, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_70}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_70 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_71, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_71}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_71 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_70, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_71}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_71 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_71, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_70}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_71 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_71, decoded_addr_decoded_decoded_andMatrixOutputs_lo_71}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_145_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_71; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_8 = decoded_addr_decoded_decoded_andMatrixOutputs_145_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_59 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_69, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_66}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_71 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_59, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_59}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_69 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_71, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_71}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_71 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_69, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_71}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_72 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_71, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_71}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_66 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_72, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_72}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_71 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_66, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_71}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_71 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_72, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_72}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_72 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_71, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_72}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_72 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_72, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_71}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_72 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_72, decoded_addr_decoded_decoded_andMatrixOutputs_lo_72}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_98_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_72; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_7 = decoded_addr_decoded_decoded_andMatrixOutputs_98_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_60 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_70, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_67}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_72 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_60, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_60}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_70 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_72, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_72}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_72 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_70, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_72}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_73 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_72, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_72}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_67 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_73, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_73}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_72 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_67, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_72}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_72 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_73, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_73}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_73 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_72, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_73}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_73 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_73, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_72}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_73 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_73, decoded_addr_decoded_decoded_andMatrixOutputs_lo_73}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_113_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_73; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_6 = decoded_addr_decoded_decoded_andMatrixOutputs_113_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_61 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_71, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_68}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_73 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_61, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_61}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_71 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_73, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_73}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_73 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_71, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_73}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_74 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_73, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_73}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_68 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_74, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_74}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_73 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_68, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_73}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_73 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_74, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_74}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_74 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_73, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_74}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_74 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_74, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_73}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_74 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_74, decoded_addr_decoded_decoded_andMatrixOutputs_lo_74}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_149_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_74; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_5 = decoded_addr_decoded_decoded_andMatrixOutputs_149_2; // @[pla.scala:98:70, :114:36] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_69 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_70 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_71 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_72 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_73 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_74 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_78 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_82 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_110 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_108 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_109 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_110 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_111 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_112 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_113 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_114 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_115 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_116 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_117 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_118 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_119 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_120 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_121 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_122 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_123 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_124 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_125 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_126 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_127 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_128 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_129 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_130 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_131 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_132 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_133 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_134 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_135 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_136 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_137 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_141 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_139 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_140 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_141 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_142 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_62 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_72, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_69}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_74 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_62, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_62}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_72 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_74, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_74}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_74 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_72, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_74}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_75 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_74, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_74}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_69 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_75, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_75}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_74 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_69, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_74}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_74 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_75, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_75}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_75 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_74, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_75}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_75 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_75, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_74}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_75 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_75, decoded_addr_decoded_decoded_andMatrixOutputs_lo_75}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_2_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_75; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_149 = decoded_addr_decoded_decoded_andMatrixOutputs_2_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_63 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_73, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_70}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_75 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_63, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_63}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_73 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_75, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_75}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_75 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_73, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_75}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_76 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_75, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_75}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_70 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_76, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_76}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_75 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_70, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_75}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_75 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_76, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_76}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_76 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_75, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_76}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_76 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_76, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_75}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_76 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_76, decoded_addr_decoded_decoded_andMatrixOutputs_lo_76}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_146_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_76; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_148 = decoded_addr_decoded_decoded_andMatrixOutputs_146_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_64 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_74, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_71}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_76 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_64, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_64}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_74 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_76, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_76}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_76 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_74, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_76}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_77 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_76, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_76}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_71 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_77, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_77}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_76 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_71, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_76}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_76 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_77, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_77}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_77 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_76, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_77}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_77 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_77, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_76}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_77 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_77, decoded_addr_decoded_decoded_andMatrixOutputs_lo_77}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_128_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_77; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_147 = decoded_addr_decoded_decoded_andMatrixOutputs_128_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_65 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_75, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_72}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_77 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_65, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_65}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_75 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_77, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_77}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_77 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_75, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_77}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_78 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_77, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_77}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_72 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_78, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_78}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_77 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_72, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_77}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_77 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_78, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_78}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_78 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_77, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_78}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_78 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_78, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_77}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_78 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_78, decoded_addr_decoded_decoded_andMatrixOutputs_lo_78}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_56_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_78; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_146 = decoded_addr_decoded_decoded_andMatrixOutputs_56_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_66 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_76, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_73}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_78 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_66, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_66}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_76 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_78, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_78}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_78 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_76, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_78}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_79 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_78, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_78}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_73 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_79, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_79}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_78 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_73, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_78}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_78 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_79, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_79}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_79 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_78, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_79}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_79 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_79, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_78}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_79 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_79, decoded_addr_decoded_decoded_andMatrixOutputs_lo_79}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_3_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_79; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_135 = decoded_addr_decoded_decoded_andMatrixOutputs_3_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_67 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_77, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_74}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_79 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_67, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_67}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_77 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_79, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_79}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_79 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_77, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_79}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_80 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_79, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_79}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_74 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_80, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_80}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_79 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_74, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_79}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_79 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_80, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_80}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_80 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_79, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_80}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_80 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_80, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_79}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_80 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_80, decoded_addr_decoded_decoded_andMatrixOutputs_lo_80}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_50_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_80; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_134 = decoded_addr_decoded_decoded_andMatrixOutputs_50_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_80 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_78, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_75}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_78 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_80, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_80}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_80 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_78, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_80}; // @[pla.scala:90:45, :98:53] wire [4:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_81 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_80, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_80}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_75 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_81, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_81}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_80 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_75, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_80}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_80 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_81, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_81}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_81 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_80, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_81}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_81 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_81, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_80}; // @[pla.scala:98:53] wire [10:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_81 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_81, decoded_addr_decoded_decoded_andMatrixOutputs_lo_81}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_23_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_81; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_133 = decoded_addr_decoded_decoded_andMatrixOutputs_23_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_81 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_82, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_82}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_82 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_81, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_81}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_82 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_82, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_82}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_82 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_82, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_82}; // @[pla.scala:90:45, :98:53] wire [5:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_82 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_82, decoded_addr_decoded_decoded_andMatrixOutputs_lo_82}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_12_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_82; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_4 = decoded_addr_decoded_decoded_andMatrixOutputs_12_2; // @[pla.scala:98:70, :114:36] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_76 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_68 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_69 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_70 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_71 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_72 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_73 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_74 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_75 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_76 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_77 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_78 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_79 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_80 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_81 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_82 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_83 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_84 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_85 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_86 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_87 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_88 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_89 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_90 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_91 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_92 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_93 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_94 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_95 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_96 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_97 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_107 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_98 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_99 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_100 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_101 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_102 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_103 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_104 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_105 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_106 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_107 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_108 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_109 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_110 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_111 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_112 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_113 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_114 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_115 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_116 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_117 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_118 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_119 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_120 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_121 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_122 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_123 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_124 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_125 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_126 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_127 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_138 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_128 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_129 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_130 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_131 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_81 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_79, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_76}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_79 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_81, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_81}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_82 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_79, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_81}; // @[pla.scala:90:45, :98:53] wire [4:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_83 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_82, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_81}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_76 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_83, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_83}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_81 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_76, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_82}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_81 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_83, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_83}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_83 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_81, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_83}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_83 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_83, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_81}; // @[pla.scala:98:53] wire [10:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_83 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_83, decoded_addr_decoded_decoded_andMatrixOutputs_lo_83}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_76_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_83; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_128 = decoded_addr_decoded_decoded_andMatrixOutputs_76_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_68 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_80, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_77}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_82 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_68, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_68}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_80 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_82, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_82}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_83 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_80, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_82}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_84 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_83, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_82}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_77 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_84, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_84}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_82 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_77, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_83}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_82 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_84, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_84}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_84 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_82, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_84}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_84 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_84, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_82}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_84 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_84, decoded_addr_decoded_decoded_andMatrixOutputs_lo_84}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_79_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_84; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_127 = decoded_addr_decoded_decoded_andMatrixOutputs_79_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_69 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_81, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_78}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_83 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_69, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_69}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_81 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_83, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_83}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_84 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_81, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_83}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_85 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_84, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_83}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_78 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_85, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_85}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_83 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_78, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_84}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_83 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_85, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_85}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_85 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_83, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_85}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_85 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_85, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_83}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_85 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_85, decoded_addr_decoded_decoded_andMatrixOutputs_lo_85}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_95_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_85; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_125 = decoded_addr_decoded_decoded_andMatrixOutputs_95_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_70 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_82, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_79}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_84 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_70, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_70}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_82 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_84, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_84}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_85 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_82, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_84}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_86 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_85, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_84}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_79 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_86, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_86}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_84 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_79, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_85}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_84 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_86, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_86}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_86 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_84, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_86}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_86 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_86, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_84}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_86 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_86, decoded_addr_decoded_decoded_andMatrixOutputs_lo_86}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_26_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_86; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_122 = decoded_addr_decoded_decoded_andMatrixOutputs_26_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_71 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_83, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_80}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_85 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_71, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_71}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_83 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_85, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_85}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_86 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_83, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_85}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_87 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_86, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_85}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_80 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_87, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_87}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_85 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_80, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_86}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_85 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_87, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_87}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_87 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_85, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_87}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_87 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_87, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_85}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_87 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_87, decoded_addr_decoded_decoded_andMatrixOutputs_lo_87}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_124_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_87; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_119 = decoded_addr_decoded_decoded_andMatrixOutputs_124_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_72 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_84, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_81}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_86 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_72, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_72}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_84 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_86, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_86}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_87 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_84, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_86}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_88 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_87, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_86}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_81 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_88, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_88}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_86 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_81, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_87}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_86 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_88, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_88}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_88 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_86, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_88}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_88 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_88, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_86}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_88 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_88, decoded_addr_decoded_decoded_andMatrixOutputs_lo_88}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_147_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_88; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_116 = decoded_addr_decoded_decoded_andMatrixOutputs_147_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_73 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_85, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_82}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_87 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_73, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_73}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_85 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_87, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_87}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_88 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_85, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_87}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_89 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_88, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_87}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_82 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_89, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_89}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_87 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_82, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_88}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_87 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_89, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_89}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_89 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_87, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_89}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_89 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_89, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_87}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_89 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_89, decoded_addr_decoded_decoded_andMatrixOutputs_lo_89}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_77_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_89; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_113 = decoded_addr_decoded_decoded_andMatrixOutputs_77_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_74 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_86, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_83}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_88 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_74, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_74}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_86 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_88, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_88}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_89 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_86, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_88}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_90 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_89, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_88}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_83 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_90, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_90}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_88 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_83, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_89}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_88 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_90, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_90}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_90 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_88, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_90}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_90 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_90, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_88}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_90 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_90, decoded_addr_decoded_decoded_andMatrixOutputs_lo_90}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_140_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_90; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_110 = decoded_addr_decoded_decoded_andMatrixOutputs_140_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_75 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_87, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_84}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_89 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_75, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_75}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_87 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_89, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_89}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_90 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_87, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_89}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_91 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_90, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_89}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_84 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_91, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_91}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_89 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_84, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_90}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_89 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_91, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_91}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_91 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_89, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_91}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_91 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_91, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_89}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_91 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_91, decoded_addr_decoded_decoded_andMatrixOutputs_lo_91}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_44_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_91; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_107 = decoded_addr_decoded_decoded_andMatrixOutputs_44_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_76 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_88, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_85}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_90 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_76, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_76}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_88 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_90, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_90}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_91 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_88, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_90}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_92 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_91, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_90}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_85 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_92, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_92}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_90 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_85, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_91}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_90 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_92, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_92}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_92 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_90, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_92}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_92 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_92, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_90}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_92 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_92, decoded_addr_decoded_decoded_andMatrixOutputs_lo_92}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_31_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_92; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_104 = decoded_addr_decoded_decoded_andMatrixOutputs_31_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_77 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_89, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_86}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_91 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_77, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_77}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_89 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_91, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_91}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_92 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_89, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_91}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_93 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_92, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_91}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_86 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_93, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_93}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_91 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_86, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_92}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_91 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_93, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_93}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_93 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_91, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_93}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_93 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_93, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_91}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_93 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_93, decoded_addr_decoded_decoded_andMatrixOutputs_lo_93}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_62_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_93; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_101 = decoded_addr_decoded_decoded_andMatrixOutputs_62_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_78 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_90, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_87}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_92 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_78, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_78}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_90 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_92, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_92}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_93 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_90, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_92}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_94 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_93, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_92}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_87 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_94, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_94}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_92 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_87, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_93}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_92 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_94, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_94}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_94 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_92, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_94}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_94 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_94, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_92}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_94 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_94, decoded_addr_decoded_decoded_andMatrixOutputs_lo_94}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_58_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_94; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_98 = decoded_addr_decoded_decoded_andMatrixOutputs_58_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_79 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_91, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_88}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_93 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_79, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_79}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_91 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_93, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_93}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_94 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_91, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_93}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_95 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_94, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_93}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_88 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_95, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_95}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_93 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_88, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_94}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_93 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_95, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_95}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_95 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_93, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_95}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_95 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_95, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_93}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_95 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_95, decoded_addr_decoded_decoded_andMatrixOutputs_lo_95}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_132_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_95; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_95 = decoded_addr_decoded_decoded_andMatrixOutputs_132_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_80 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_92, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_89}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_94 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_80, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_80}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_92 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_94, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_94}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_95 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_92, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_94}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_96 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_95, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_94}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_89 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_96, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_96}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_94 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_89, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_95}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_94 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_96, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_96}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_96 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_94, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_96}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_96 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_96, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_94}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_96 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_96, decoded_addr_decoded_decoded_andMatrixOutputs_lo_96}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_9_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_96; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_92 = decoded_addr_decoded_decoded_andMatrixOutputs_9_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_81 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_93, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_90}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_95 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_81, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_81}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_93 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_95, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_95}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_96 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_93, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_95}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_97 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_96, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_95}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_90 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_97, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_97}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_95 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_90, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_96}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_95 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_97, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_97}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_97 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_95, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_97}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_97 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_97, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_95}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_97 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_97, decoded_addr_decoded_decoded_andMatrixOutputs_lo_97}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_115_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_97; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_89 = decoded_addr_decoded_decoded_andMatrixOutputs_115_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_82 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_94, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_91}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_96 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_82, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_82}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_94 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_96, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_96}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_97 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_94, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_96}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_98 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_97, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_96}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_91 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_98, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_98}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_96 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_91, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_97}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_96 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_98, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_98}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_98 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_96, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_98}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_98 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_98, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_96}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_98 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_98, decoded_addr_decoded_decoded_andMatrixOutputs_lo_98}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_5_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_98; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_86 = decoded_addr_decoded_decoded_andMatrixOutputs_5_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_83 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_95, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_92}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_97 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_83, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_83}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_95 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_97, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_97}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_98 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_95, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_97}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_99 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_98, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_97}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_92 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_99, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_99}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_97 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_92, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_98}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_97 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_99, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_99}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_99 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_97, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_99}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_99 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_99, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_97}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_99 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_99, decoded_addr_decoded_decoded_andMatrixOutputs_lo_99}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_71_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_99; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_83 = decoded_addr_decoded_decoded_andMatrixOutputs_71_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_84 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_96, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_93}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_98 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_84, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_84}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_96 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_98, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_98}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_99 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_96, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_98}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_100 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_99, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_98}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_93 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_100, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_100}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_98 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_93, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_99}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_98 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_100, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_100}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_100 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_98, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_100}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_100 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_100, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_98}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_100 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_100, decoded_addr_decoded_decoded_andMatrixOutputs_lo_100}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_130_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_100; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_80 = decoded_addr_decoded_decoded_andMatrixOutputs_130_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_85 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_97, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_94}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_99 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_85, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_85}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_97 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_99, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_99}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_100 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_97, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_99}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_101 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_100, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_99}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_94 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_101, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_101}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_99 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_94, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_100}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_99 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_101, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_101}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_101 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_99, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_101}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_101 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_101, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_99}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_101 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_101, decoded_addr_decoded_decoded_andMatrixOutputs_lo_101}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_102_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_101; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_77 = decoded_addr_decoded_decoded_andMatrixOutputs_102_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_86 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_98, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_95}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_100 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_86, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_86}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_98 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_100, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_100}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_101 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_98, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_100}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_102 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_101, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_100}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_95 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_102, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_102}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_100 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_95, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_101}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_100 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_102, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_102}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_102 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_100, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_102}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_102 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_102, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_100}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_102 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_102, decoded_addr_decoded_decoded_andMatrixOutputs_lo_102}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_4_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_102; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_74 = decoded_addr_decoded_decoded_andMatrixOutputs_4_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_87 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_99, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_96}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_101 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_87, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_87}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_99 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_101, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_101}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_102 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_99, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_101}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_103 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_102, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_101}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_96 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_103, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_103}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_101 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_96, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_102}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_101 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_103, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_103}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_103 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_101, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_103}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_103 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_103, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_101}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_103 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_103, decoded_addr_decoded_decoded_andMatrixOutputs_lo_103}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_29_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_103; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_71 = decoded_addr_decoded_decoded_andMatrixOutputs_29_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_88 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_100, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_97}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_102 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_88, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_88}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_100 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_102, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_102}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_103 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_100, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_102}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_104 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_103, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_102}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_97 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_104, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_104}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_102 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_97, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_103}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_102 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_104, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_104}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_104 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_102, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_104}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_104 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_104, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_102}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_104 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_104, decoded_addr_decoded_decoded_andMatrixOutputs_lo_104}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_16_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_104; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_68 = decoded_addr_decoded_decoded_andMatrixOutputs_16_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_89 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_101, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_98}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_103 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_89, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_89}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_101 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_103, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_103}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_104 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_101, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_103}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_105 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_104, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_103}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_98 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_105, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_105}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_103 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_98, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_104}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_103 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_105, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_105}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_105 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_103, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_105}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_105 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_105, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_103}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_105 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_105, decoded_addr_decoded_decoded_andMatrixOutputs_lo_105}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_143_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_105; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_65 = decoded_addr_decoded_decoded_andMatrixOutputs_143_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_90 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_102, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_99}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_104 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_90, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_90}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_102 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_104, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_104}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_105 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_102, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_104}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_106 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_105, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_104}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_99 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_106, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_106}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_104 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_99, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_105}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_104 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_106, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_106}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_106 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_104, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_106}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_106 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_106, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_104}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_106 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_106, decoded_addr_decoded_decoded_andMatrixOutputs_lo_106}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_131_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_106; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_62 = decoded_addr_decoded_decoded_andMatrixOutputs_131_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_91 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_103, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_100}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_105 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_91, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_91}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_103 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_105, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_105}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_106 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_103, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_105}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_107 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_106, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_105}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_100 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_107, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_107}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_105 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_100, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_106}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_105 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_107, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_107}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_107 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_105, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_107}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_107 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_107, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_105}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_107 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_107, decoded_addr_decoded_decoded_andMatrixOutputs_lo_107}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_14_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_107; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_59 = decoded_addr_decoded_decoded_andMatrixOutputs_14_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_92 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_104, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_101}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_106 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_92, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_92}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_104 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_106, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_106}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_107 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_104, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_106}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_108 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_107, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_106}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_101 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_108, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_108}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_106 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_101, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_107}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_106 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_108, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_108}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_108 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_106, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_108}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_108 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_108, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_106}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_108 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_108, decoded_addr_decoded_decoded_andMatrixOutputs_lo_108}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_90_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_108; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_56 = decoded_addr_decoded_decoded_andMatrixOutputs_90_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_93 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_105, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_102}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_107 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_93, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_93}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_105 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_107, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_107}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_108 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_105, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_107}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_109 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_108, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_107}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_102 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_109, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_109}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_107 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_102, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_108}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_107 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_109, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_109}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_109 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_107, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_109}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_109 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_109, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_107}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_109 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_109, decoded_addr_decoded_decoded_andMatrixOutputs_lo_109}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_97_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_109; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_53 = decoded_addr_decoded_decoded_andMatrixOutputs_97_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_94 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_106, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_103}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_108 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_94, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_94}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_106 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_108, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_108}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_109 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_106, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_108}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_110 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_109, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_108}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_103 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_110, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_110}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_108 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_103, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_109}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_108 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_110, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_110}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_110 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_108, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_110}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_110 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_110, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_108}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_110 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_110, decoded_addr_decoded_decoded_andMatrixOutputs_lo_110}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_60_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_110; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_50 = decoded_addr_decoded_decoded_andMatrixOutputs_60_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_95 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_107, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_104}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_109 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_95, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_95}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_107 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_109, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_109}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_110 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_107, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_109}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_111 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_110, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_109}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_104 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_111, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_111}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_109 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_104, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_110}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_109 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_111, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_111}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_111 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_109, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_111}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_111 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_111, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_109}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_111 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_111, decoded_addr_decoded_decoded_andMatrixOutputs_lo_111}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_96_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_111; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_47 = decoded_addr_decoded_decoded_andMatrixOutputs_96_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_96 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_108, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_105}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_110 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_96, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_96}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_108 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_110, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_110}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_111 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_108, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_110}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_112 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_111, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_110}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_105 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_112, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_112}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_110 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_105, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_111}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_110 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_112, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_112}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_112 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_110, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_112}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_112 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_112, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_110}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_112 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_112, decoded_addr_decoded_decoded_andMatrixOutputs_lo_112}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_54_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_112; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_44 = decoded_addr_decoded_decoded_andMatrixOutputs_54_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_97 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_109, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_106}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_111 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_97, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_97}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_109 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_111, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_111}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_112 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_109, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_111}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_113 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_112, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_111}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_106 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_113, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_113}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_111 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_106, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_112}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_111 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_113, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_113}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_113 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_111, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_113}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_113 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_113, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_111}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_113 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_113, decoded_addr_decoded_decoded_andMatrixOutputs_lo_113}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_126_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_113; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_41 = decoded_addr_decoded_decoded_andMatrixOutputs_126_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_112 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_110, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_107}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_110 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_112, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_112}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_113 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_110, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_112}; // @[pla.scala:91:29, :98:53] wire [4:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_114 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_113, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_112}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_107 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_114, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_114}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_112 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_107, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_113}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_112 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_114, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_114}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_114 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_112, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_114}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_114 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_114, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_112}; // @[pla.scala:98:53] wire [10:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_114 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_114, decoded_addr_decoded_decoded_andMatrixOutputs_lo_114}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_49_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_114; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_38 = decoded_addr_decoded_decoded_andMatrixOutputs_49_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_98 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_111, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_108}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_113 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_98, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_98}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_111 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_113, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_113}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_114 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_111, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_113}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_115 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_114, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_113}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_108 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_115, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_115}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_113 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_108, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_114}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_113 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_115, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_115}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_115 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_113, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_115}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_115 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_115, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_113}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_115 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_115, decoded_addr_decoded_decoded_andMatrixOutputs_lo_115}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_52_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_115; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_37 = decoded_addr_decoded_decoded_andMatrixOutputs_52_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_99 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_112, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_109}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_114 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_99, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_99}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_112 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_114, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_114}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_115 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_112, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_114}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_116 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_115, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_114}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_109 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_116, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_116}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_114 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_109, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_115}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_114 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_116, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_116}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_116 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_114, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_116}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_116 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_116, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_114}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_116 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_116, decoded_addr_decoded_decoded_andMatrixOutputs_lo_116}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_20_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_116; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_124 = decoded_addr_decoded_decoded_andMatrixOutputs_20_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_100 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_113, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_110}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_115 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_100, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_100}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_113 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_115, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_115}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_116 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_113, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_115}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_117 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_116, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_115}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_110 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_117, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_117}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_115 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_110, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_116}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_115 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_117, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_117}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_117 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_115, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_117}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_117 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_117, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_115}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_117 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_117, decoded_addr_decoded_decoded_andMatrixOutputs_lo_117}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_107_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_117; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_121 = decoded_addr_decoded_decoded_andMatrixOutputs_107_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_101 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_114, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_111}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_116 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_101, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_101}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_114 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_116, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_116}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_117 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_114, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_116}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_118 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_117, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_116}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_111 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_118, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_118}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_116 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_111, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_117}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_116 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_118, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_118}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_118 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_116, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_118}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_118 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_118, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_116}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_118 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_118, decoded_addr_decoded_decoded_andMatrixOutputs_lo_118}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_6_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_118; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_118 = decoded_addr_decoded_decoded_andMatrixOutputs_6_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_102 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_115, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_112}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_117 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_102, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_102}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_115 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_117, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_117}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_118 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_115, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_117}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_119 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_118, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_117}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_112 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_119, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_119}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_117 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_112, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_118}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_117 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_119, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_119}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_119 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_117, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_119}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_119 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_119, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_117}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_119 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_119, decoded_addr_decoded_decoded_andMatrixOutputs_lo_119}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_21_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_119; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_115 = decoded_addr_decoded_decoded_andMatrixOutputs_21_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_103 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_116, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_113}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_118 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_103, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_103}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_116 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_118, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_118}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_119 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_116, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_118}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_120 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_119, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_118}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_113 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_120, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_120}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_118 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_113, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_119}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_118 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_120, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_120}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_120 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_118, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_120}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_120 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_120, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_118}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_120 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_120, decoded_addr_decoded_decoded_andMatrixOutputs_lo_120}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_30_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_120; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_112 = decoded_addr_decoded_decoded_andMatrixOutputs_30_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_104 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_117, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_114}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_119 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_104, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_104}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_117 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_119, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_119}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_120 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_117, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_119}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_121 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_120, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_119}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_114 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_121, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_121}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_119 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_114, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_120}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_119 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_121, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_121}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_121 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_119, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_121}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_121 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_121, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_119}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_121 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_121, decoded_addr_decoded_decoded_andMatrixOutputs_lo_121}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_127_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_121; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_109 = decoded_addr_decoded_decoded_andMatrixOutputs_127_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_105 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_118, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_115}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_120 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_105, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_105}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_118 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_120, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_120}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_121 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_118, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_120}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_122 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_121, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_120}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_115 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_122, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_122}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_120 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_115, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_121}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_120 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_122, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_122}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_122 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_120, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_122}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_122 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_122, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_120}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_122 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_122, decoded_addr_decoded_decoded_andMatrixOutputs_lo_122}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_35_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_122; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_106 = decoded_addr_decoded_decoded_andMatrixOutputs_35_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_106 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_119, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_116}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_121 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_106, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_106}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_119 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_121, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_121}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_122 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_119, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_121}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_123 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_122, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_121}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_116 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_123, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_123}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_121 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_116, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_122}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_121 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_123, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_123}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_123 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_121, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_123}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_123 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_123, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_121}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_123 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_123, decoded_addr_decoded_decoded_andMatrixOutputs_lo_123}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_73_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_123; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_103 = decoded_addr_decoded_decoded_andMatrixOutputs_73_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_107 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_120, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_117}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_122 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_107, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_107}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_120 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_122, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_122}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_123 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_120, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_122}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_124 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_123, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_122}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_117 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_124, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_124}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_122 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_117, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_123}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_122 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_124, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_124}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_124 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_122, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_124}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_124 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_124, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_122}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_124 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_124, decoded_addr_decoded_decoded_andMatrixOutputs_lo_124}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_53_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_124; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_100 = decoded_addr_decoded_decoded_andMatrixOutputs_53_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_108 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_121, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_118}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_123 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_108, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_108}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_121 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_123, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_123}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_124 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_121, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_123}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_125 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_124, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_123}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_118 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_125, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_125}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_123 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_118, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_124}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_123 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_125, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_125}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_125 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_123, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_125}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_125 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_125, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_123}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_125 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_125, decoded_addr_decoded_decoded_andMatrixOutputs_lo_125}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_135_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_125; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_97 = decoded_addr_decoded_decoded_andMatrixOutputs_135_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_109 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_122, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_119}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_124 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_109, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_109}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_122 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_124, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_124}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_125 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_122, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_124}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_126 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_125, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_124}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_119 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_126, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_126}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_124 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_119, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_125}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_124 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_126, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_126}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_126 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_124, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_126}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_126 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_126, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_124}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_126 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_126, decoded_addr_decoded_decoded_andMatrixOutputs_lo_126}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_37_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_126; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_94 = decoded_addr_decoded_decoded_andMatrixOutputs_37_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_110 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_123, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_120}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_125 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_110, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_110}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_123 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_125, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_125}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_126 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_123, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_125}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_127 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_126, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_125}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_120 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_127, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_127}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_125 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_120, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_126}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_125 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_127, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_127}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_127 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_125, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_127}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_127 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_127, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_125}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_127 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_127, decoded_addr_decoded_decoded_andMatrixOutputs_lo_127}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_25_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_127; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_91 = decoded_addr_decoded_decoded_andMatrixOutputs_25_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_111 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_124, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_121}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_126 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_111, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_111}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_124 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_126, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_126}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_127 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_124, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_126}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_128 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_127, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_126}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_121 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_128, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_128}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_126 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_121, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_127}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_126 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_128, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_128}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_128 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_126, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_128}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_128 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_128, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_126}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_128 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_128, decoded_addr_decoded_decoded_andMatrixOutputs_lo_128}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_64_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_128; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_88 = decoded_addr_decoded_decoded_andMatrixOutputs_64_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_112 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_125, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_122}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_127 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_112, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_112}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_125 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_127, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_127}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_128 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_125, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_127}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_129 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_128, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_127}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_122 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_129, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_129}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_127 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_122, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_128}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_127 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_129, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_129}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_129 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_127, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_129}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_129 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_129, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_127}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_129 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_129, decoded_addr_decoded_decoded_andMatrixOutputs_lo_129}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_19_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_129; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_85 = decoded_addr_decoded_decoded_andMatrixOutputs_19_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_113 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_126, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_123}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_128 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_113, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_113}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_126 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_128, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_128}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_129 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_126, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_128}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_130 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_129, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_128}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_123 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_130, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_130}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_128 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_123, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_129}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_128 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_130, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_130}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_130 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_128, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_130}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_130 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_130, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_128}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_130 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_130, decoded_addr_decoded_decoded_andMatrixOutputs_lo_130}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_112_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_130; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_82 = decoded_addr_decoded_decoded_andMatrixOutputs_112_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_114 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_127, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_124}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_129 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_114, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_114}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_127 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_129, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_129}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_130 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_127, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_129}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_131 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_130, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_129}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_124 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_131, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_131}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_129 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_124, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_130}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_129 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_131, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_131}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_131 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_129, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_131}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_131 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_131, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_129}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_131 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_131, decoded_addr_decoded_decoded_andMatrixOutputs_lo_131}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_108_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_131; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_79 = decoded_addr_decoded_decoded_andMatrixOutputs_108_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_115 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_128, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_125}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_130 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_115, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_115}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_128 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_130, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_130}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_131 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_128, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_130}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_132 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_131, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_130}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_125 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_132, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_132}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_130 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_125, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_131}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_130 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_132, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_132}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_132 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_130, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_132}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_132 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_132, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_130}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_132 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_132, decoded_addr_decoded_decoded_andMatrixOutputs_lo_132}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_148_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_132; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_76 = decoded_addr_decoded_decoded_andMatrixOutputs_148_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_116 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_129, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_126}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_131 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_116, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_116}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_129 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_131, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_131}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_132 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_129, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_131}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_133 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_132, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_131}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_126 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_133, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_133}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_131 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_126, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_132}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_131 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_133, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_133}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_133 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_131, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_133}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_133 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_133, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_131}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_133 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_133, decoded_addr_decoded_decoded_andMatrixOutputs_lo_133}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_69_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_133; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_73 = decoded_addr_decoded_decoded_andMatrixOutputs_69_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_117 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_130, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_127}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_132 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_117, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_117}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_130 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_132, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_132}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_133 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_130, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_132}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_134 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_133, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_132}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_127 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_134, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_134}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_132 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_127, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_133}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_132 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_134, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_134}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_134 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_132, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_134}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_134 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_134, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_132}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_134 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_134, decoded_addr_decoded_decoded_andMatrixOutputs_lo_134}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_103_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_134; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_70 = decoded_addr_decoded_decoded_andMatrixOutputs_103_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_118 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_131, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_128}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_133 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_118, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_118}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_131 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_133, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_133}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_134 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_131, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_133}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_135 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_134, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_133}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_128 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_135, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_135}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_133 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_128, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_134}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_133 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_135, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_135}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_135 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_133, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_135}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_135 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_135, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_133}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_135 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_135, decoded_addr_decoded_decoded_andMatrixOutputs_lo_135}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_99_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_135; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_67 = decoded_addr_decoded_decoded_andMatrixOutputs_99_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_119 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_132, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_129}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_134 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_119, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_119}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_132 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_134, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_134}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_135 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_132, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_134}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_136 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_135, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_134}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_129 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_136, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_136}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_134 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_129, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_135}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_134 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_136, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_136}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_136 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_134, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_136}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_136 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_136, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_134}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_136 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_136, decoded_addr_decoded_decoded_andMatrixOutputs_lo_136}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_125_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_136; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_64 = decoded_addr_decoded_decoded_andMatrixOutputs_125_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_120 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_133, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_130}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_135 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_120, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_120}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_133 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_135, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_135}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_136 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_133, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_135}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_137 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_136, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_135}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_130 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_137, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_137}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_135 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_130, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_136}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_135 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_137, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_137}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_137 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_135, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_137}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_137 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_137, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_135}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_137 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_137, decoded_addr_decoded_decoded_andMatrixOutputs_lo_137}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_117_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_137; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_61 = decoded_addr_decoded_decoded_andMatrixOutputs_117_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_121 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_134, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_131}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_136 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_121, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_121}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_134 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_136, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_136}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_137 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_134, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_136}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_138 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_137, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_136}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_131 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_138, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_138}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_136 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_131, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_137}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_136 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_138, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_138}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_138 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_136, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_138}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_138 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_138, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_136}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_138 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_138, decoded_addr_decoded_decoded_andMatrixOutputs_lo_138}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_46_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_138; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_58 = decoded_addr_decoded_decoded_andMatrixOutputs_46_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_122 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_135, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_132}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_137 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_122, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_122}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_135 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_137, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_137}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_138 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_135, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_137}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_139 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_138, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_137}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_132 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_139, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_139}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_137 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_132, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_138}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_137 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_139, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_139}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_139 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_137, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_139}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_139 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_139, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_137}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_139 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_139, decoded_addr_decoded_decoded_andMatrixOutputs_lo_139}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_15_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_139; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_55 = decoded_addr_decoded_decoded_andMatrixOutputs_15_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_123 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_136, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_133}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_138 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_123, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_123}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_136 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_138, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_138}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_139 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_136, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_138}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_140 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_139, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_138}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_133 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_140, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_140}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_138 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_133, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_139}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_138 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_140, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_140}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_140 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_138, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_140}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_140 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_140, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_138}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_140 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_140, decoded_addr_decoded_decoded_andMatrixOutputs_lo_140}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_51_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_140; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_52 = decoded_addr_decoded_decoded_andMatrixOutputs_51_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_124 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_137, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_134}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_139 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_124, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_124}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_137 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_139, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_139}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_140 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_137, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_139}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_141 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_140, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_139}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_134 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_141, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_141}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_139 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_134, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_140}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_139 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_141, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_141}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_141 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_139, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_141}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_141 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_141, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_139}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_141 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_141, decoded_addr_decoded_decoded_andMatrixOutputs_lo_141}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_43_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_141; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_49 = decoded_addr_decoded_decoded_andMatrixOutputs_43_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_125 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_138, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_135}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_140 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_125, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_125}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_138 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_140, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_140}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_141 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_138, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_140}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_142 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_141, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_140}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_135 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_142, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_142}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_140 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_135, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_141}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_140 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_142, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_142}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_142 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_140, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_142}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_142 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_142, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_140}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_142 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_142, decoded_addr_decoded_decoded_andMatrixOutputs_lo_142}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_70_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_142; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_46 = decoded_addr_decoded_decoded_andMatrixOutputs_70_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_126 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_139, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_136}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_141 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_126, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_126}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_139 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_141, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_141}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_142 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_139, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_141}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_143 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_142, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_141}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_136 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_143, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_143}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_141 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_136, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_142}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_141 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_143, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_143}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_143 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_141, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_143}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_143 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_143, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_141}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_143 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_143, decoded_addr_decoded_decoded_andMatrixOutputs_lo_143}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_78_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_143; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_43 = decoded_addr_decoded_decoded_andMatrixOutputs_78_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_127 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_140, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_137}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_142 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_127, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_127}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_140 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_142, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_142}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_143 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_140, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_142}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_144 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_143, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_142}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_137 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_144, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_144}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_142 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_137, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_143}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_142 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_144, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_144}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_144 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_142, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_144}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_144 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_144, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_142}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_144 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_144, decoded_addr_decoded_decoded_andMatrixOutputs_lo_144}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_110_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_144; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_40 = decoded_addr_decoded_decoded_andMatrixOutputs_110_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_143 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_141, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_138}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_141 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_143, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_143}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_144 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_141, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_143}; // @[pla.scala:90:45, :98:53] wire [4:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_145 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_144, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_143}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_138 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_145, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_145}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_143 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_138, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_144}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_143 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_145, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_145}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_145 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_143, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_145}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_145 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_145, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_143}; // @[pla.scala:98:53] wire [10:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_145 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_145, decoded_addr_decoded_decoded_andMatrixOutputs_lo_145}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_101_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_145; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_1 = decoded_addr_decoded_decoded_andMatrixOutputs_101_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_128 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_142, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_139}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_144 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_128, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_128}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_142 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_144, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_144}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_145 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_142, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_144}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_146 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_145, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_144}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_139 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_146, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_146}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_144 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_139, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_145}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_144 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_146, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_146}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_146 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_144, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_146}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_146 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_146, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_144}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_146 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_146, decoded_addr_decoded_decoded_andMatrixOutputs_lo_146}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_38_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_146; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_3 = decoded_addr_decoded_decoded_andMatrixOutputs_38_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_129 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_143, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_140}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_145 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_129, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_129}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_143 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_145, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_145}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_146 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_143, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_145}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_147 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_146, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_145}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_140 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_147, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_147}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_145 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_140, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_146}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_145 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_147, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_147}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_147 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_145, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_147}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_147 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_147, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_145}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_147 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_147, decoded_addr_decoded_decoded_andMatrixOutputs_lo_147}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_13_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_147; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_2 = decoded_addr_decoded_decoded_andMatrixOutputs_13_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_130 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_144, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_141}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_146 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_130, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_130}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_144 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_146, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_146}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_147 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_144, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_146}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_148 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_147, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_146}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_141 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_148, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_148}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_146 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_141, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_147}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_146 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_148, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_148}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_148 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_146, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_148}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_148 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_148, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_146}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_148 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_148, decoded_addr_decoded_decoded_andMatrixOutputs_lo_148}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_81_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_148; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_136 = decoded_addr_decoded_decoded_andMatrixOutputs_81_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_131 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_145, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_142}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_147 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_131, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_131}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_145 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_147, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_147}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_148 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_145, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_147}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_149 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_148, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_147}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_142 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_149, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_149}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_147 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_142, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_148}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_147 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_149, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_149}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_149 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_147, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_149}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_149 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_149, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_147}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_149 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_149, decoded_addr_decoded_decoded_andMatrixOutputs_lo_149}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_75_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_149; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T = decoded_addr_decoded_decoded_andMatrixOutputs_75_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo_lo_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_1, _decoded_addr_decoded_decoded_orMatrixOutputs_T}; // @[pla.scala:102:36, :114:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo_lo_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_3, _decoded_addr_decoded_decoded_orMatrixOutputs_T_2}; // @[pla.scala:102:36, :114:36] wire [3:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo_lo_lo}; // @[pla.scala:102:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo_hi_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_5, _decoded_addr_decoded_decoded_orMatrixOutputs_T_4}; // @[pla.scala:102:36, :114:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo_hi_hi_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_8, _decoded_addr_decoded_decoded_orMatrixOutputs_T_7}; // @[pla.scala:102:36, :114:36] wire [2:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_6}; // @[pla.scala:102:36, :114:36] wire [4:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo_hi_lo}; // @[pla.scala:102:36] wire [8:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo_lo}; // @[pla.scala:102:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi_lo_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_10, _decoded_addr_decoded_decoded_orMatrixOutputs_T_9}; // @[pla.scala:102:36, :114:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi_lo_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_12, _decoded_addr_decoded_decoded_orMatrixOutputs_T_11}; // @[pla.scala:102:36, :114:36] wire [3:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi_lo_lo}; // @[pla.scala:102:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi_hi_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_14, _decoded_addr_decoded_decoded_orMatrixOutputs_T_13}; // @[pla.scala:102:36, :114:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi_hi_hi_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_17, _decoded_addr_decoded_decoded_orMatrixOutputs_T_16}; // @[pla.scala:102:36, :114:36] wire [2:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_15}; // @[pla.scala:102:36, :114:36] wire [4:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi_hi_lo}; // @[pla.scala:102:36] wire [8:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi_lo}; // @[pla.scala:102:36] wire [17:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo}; // @[pla.scala:102:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo_lo_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_19, _decoded_addr_decoded_decoded_orMatrixOutputs_T_18}; // @[pla.scala:102:36, :114:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo_lo_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_21, _decoded_addr_decoded_decoded_orMatrixOutputs_T_20}; // @[pla.scala:102:36, :114:36] wire [3:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo_lo_lo}; // @[pla.scala:102:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo_hi_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_23, _decoded_addr_decoded_decoded_orMatrixOutputs_T_22}; // @[pla.scala:102:36, :114:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo_hi_hi_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_26, _decoded_addr_decoded_decoded_orMatrixOutputs_T_25}; // @[pla.scala:102:36, :114:36] wire [2:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_24}; // @[pla.scala:102:36, :114:36] wire [4:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo_hi_lo}; // @[pla.scala:102:36] wire [8:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo_lo}; // @[pla.scala:102:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_lo_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_28, _decoded_addr_decoded_decoded_orMatrixOutputs_T_27}; // @[pla.scala:102:36, :114:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_lo_hi_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_31, _decoded_addr_decoded_decoded_orMatrixOutputs_T_30}; // @[pla.scala:102:36, :114:36] wire [2:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_lo_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_lo_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_29}; // @[pla.scala:102:36, :114:36] wire [4:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_lo_lo}; // @[pla.scala:102:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_33, _decoded_addr_decoded_decoded_orMatrixOutputs_T_32}; // @[pla.scala:102:36, :114:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_hi_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_36, _decoded_addr_decoded_decoded_orMatrixOutputs_T_35}; // @[pla.scala:102:36, :114:36] wire [2:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_34}; // @[pla.scala:102:36, :114:36] wire [4:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_lo}; // @[pla.scala:102:36] wire [9:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_lo}; // @[pla.scala:102:36] wire [18:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo}; // @[pla.scala:102:36] wire [36:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo}; // @[pla.scala:102:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo_lo_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_38, _decoded_addr_decoded_decoded_orMatrixOutputs_T_37}; // @[pla.scala:102:36, :114:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo_lo_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_40, _decoded_addr_decoded_decoded_orMatrixOutputs_T_39}; // @[pla.scala:102:36, :114:36] wire [3:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo_lo_lo}; // @[pla.scala:102:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo_hi_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_42, _decoded_addr_decoded_decoded_orMatrixOutputs_T_41}; // @[pla.scala:102:36, :114:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo_hi_hi_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_45, _decoded_addr_decoded_decoded_orMatrixOutputs_T_44}; // @[pla.scala:102:36, :114:36] wire [2:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_43}; // @[pla.scala:102:36, :114:36] wire [4:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo_hi_lo}; // @[pla.scala:102:36] wire [8:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo_lo}; // @[pla.scala:102:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_lo_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_47, _decoded_addr_decoded_decoded_orMatrixOutputs_T_46}; // @[pla.scala:102:36, :114:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_lo_hi_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_50, _decoded_addr_decoded_decoded_orMatrixOutputs_T_49}; // @[pla.scala:102:36, :114:36] wire [2:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_lo_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_lo_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_48}; // @[pla.scala:102:36, :114:36] wire [4:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_lo_lo}; // @[pla.scala:102:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_52, _decoded_addr_decoded_decoded_orMatrixOutputs_T_51}; // @[pla.scala:102:36, :114:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_hi_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_55, _decoded_addr_decoded_decoded_orMatrixOutputs_T_54}; // @[pla.scala:102:36, :114:36] wire [2:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_53}; // @[pla.scala:102:36, :114:36] wire [4:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_lo}; // @[pla.scala:102:36] wire [9:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_lo}; // @[pla.scala:102:36] wire [18:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo}; // @[pla.scala:102:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo_lo_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_57, _decoded_addr_decoded_decoded_orMatrixOutputs_T_56}; // @[pla.scala:102:36, :114:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo_lo_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_59, _decoded_addr_decoded_decoded_orMatrixOutputs_T_58}; // @[pla.scala:102:36, :114:36] wire [3:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo_lo_lo}; // @[pla.scala:102:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo_hi_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_61, _decoded_addr_decoded_decoded_orMatrixOutputs_T_60}; // @[pla.scala:102:36, :114:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo_hi_hi_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_64, _decoded_addr_decoded_decoded_orMatrixOutputs_T_63}; // @[pla.scala:102:36, :114:36] wire [2:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_62}; // @[pla.scala:102:36, :114:36] wire [4:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo_hi_lo}; // @[pla.scala:102:36] wire [8:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo_lo}; // @[pla.scala:102:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_lo_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_66, _decoded_addr_decoded_decoded_orMatrixOutputs_T_65}; // @[pla.scala:102:36, :114:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_lo_hi_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_69, _decoded_addr_decoded_decoded_orMatrixOutputs_T_68}; // @[pla.scala:102:36, :114:36] wire [2:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_lo_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_lo_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_67}; // @[pla.scala:102:36, :114:36] wire [4:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_lo_lo}; // @[pla.scala:102:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_71, _decoded_addr_decoded_decoded_orMatrixOutputs_T_70}; // @[pla.scala:102:36, :114:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_hi_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_74, _decoded_addr_decoded_decoded_orMatrixOutputs_T_73}; // @[pla.scala:102:36, :114:36] wire [2:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_72}; // @[pla.scala:102:36, :114:36] wire [4:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_lo}; // @[pla.scala:102:36] wire [9:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_lo}; // @[pla.scala:102:36] wire [18:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo}; // @[pla.scala:102:36] wire [37:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo}; // @[pla.scala:102:36] wire [74:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo}; // @[pla.scala:102:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo_lo_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_76, _decoded_addr_decoded_decoded_orMatrixOutputs_T_75}; // @[pla.scala:102:36, :114:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo_lo_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_78, _decoded_addr_decoded_decoded_orMatrixOutputs_T_77}; // @[pla.scala:102:36, :114:36] wire [3:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo_lo_lo}; // @[pla.scala:102:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo_hi_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_80, _decoded_addr_decoded_decoded_orMatrixOutputs_T_79}; // @[pla.scala:102:36, :114:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo_hi_hi_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_83, _decoded_addr_decoded_decoded_orMatrixOutputs_T_82}; // @[pla.scala:102:36, :114:36] wire [2:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_81}; // @[pla.scala:102:36, :114:36] wire [4:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo_hi_lo}; // @[pla.scala:102:36] wire [8:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo_lo}; // @[pla.scala:102:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi_lo_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_85, _decoded_addr_decoded_decoded_orMatrixOutputs_T_84}; // @[pla.scala:102:36, :114:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi_lo_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_87, _decoded_addr_decoded_decoded_orMatrixOutputs_T_86}; // @[pla.scala:102:36, :114:36] wire [3:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi_lo_lo}; // @[pla.scala:102:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_89, _decoded_addr_decoded_decoded_orMatrixOutputs_T_88}; // @[pla.scala:102:36, :114:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_hi_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_92, _decoded_addr_decoded_decoded_orMatrixOutputs_T_91}; // @[pla.scala:102:36, :114:36] wire [2:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_90}; // @[pla.scala:102:36, :114:36] wire [4:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_lo}; // @[pla.scala:102:36] wire [8:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi_lo}; // @[pla.scala:102:36] wire [17:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo}; // @[pla.scala:102:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo_lo_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_94, _decoded_addr_decoded_decoded_orMatrixOutputs_T_93}; // @[pla.scala:102:36, :114:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo_lo_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_96, _decoded_addr_decoded_decoded_orMatrixOutputs_T_95}; // @[pla.scala:102:36, :114:36] wire [3:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo_lo_lo}; // @[pla.scala:102:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo_hi_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_98, _decoded_addr_decoded_decoded_orMatrixOutputs_T_97}; // @[pla.scala:102:36, :114:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo_hi_hi_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_101, _decoded_addr_decoded_decoded_orMatrixOutputs_T_100}; // @[pla.scala:102:36, :114:36] wire [2:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_99}; // @[pla.scala:102:36, :114:36] wire [4:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo_hi_lo}; // @[pla.scala:102:36] wire [8:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo_lo}; // @[pla.scala:102:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_lo_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_103, _decoded_addr_decoded_decoded_orMatrixOutputs_T_102}; // @[pla.scala:102:36, :114:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_lo_hi_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_106, _decoded_addr_decoded_decoded_orMatrixOutputs_T_105}; // @[pla.scala:102:36, :114:36] wire [2:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_lo_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_lo_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_104}; // @[pla.scala:102:36, :114:36] wire [4:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_lo_lo}; // @[pla.scala:102:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_108, _decoded_addr_decoded_decoded_orMatrixOutputs_T_107}; // @[pla.scala:102:36, :114:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_hi_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_111, _decoded_addr_decoded_decoded_orMatrixOutputs_T_110}; // @[pla.scala:102:36, :114:36] wire [2:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_109}; // @[pla.scala:102:36, :114:36] wire [4:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_lo}; // @[pla.scala:102:36] wire [9:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_lo}; // @[pla.scala:102:36] wire [18:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo}; // @[pla.scala:102:36] wire [36:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo}; // @[pla.scala:102:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo_lo_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_113, _decoded_addr_decoded_decoded_orMatrixOutputs_T_112}; // @[pla.scala:102:36, :114:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo_lo_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_115, _decoded_addr_decoded_decoded_orMatrixOutputs_T_114}; // @[pla.scala:102:36, :114:36] wire [3:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo_lo_lo}; // @[pla.scala:102:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo_hi_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_117, _decoded_addr_decoded_decoded_orMatrixOutputs_T_116}; // @[pla.scala:102:36, :114:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo_hi_hi_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_120, _decoded_addr_decoded_decoded_orMatrixOutputs_T_119}; // @[pla.scala:102:36, :114:36] wire [2:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_118}; // @[pla.scala:102:36, :114:36] wire [4:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo_hi_lo}; // @[pla.scala:102:36] wire [8:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo_lo}; // @[pla.scala:102:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_lo_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_122, _decoded_addr_decoded_decoded_orMatrixOutputs_T_121}; // @[pla.scala:102:36, :114:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_lo_hi_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_125, _decoded_addr_decoded_decoded_orMatrixOutputs_T_124}; // @[pla.scala:102:36, :114:36] wire [2:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_lo_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_lo_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_123}; // @[pla.scala:102:36, :114:36] wire [4:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_lo_lo}; // @[pla.scala:102:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_127, _decoded_addr_decoded_decoded_orMatrixOutputs_T_126}; // @[pla.scala:102:36, :114:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_hi_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_130, _decoded_addr_decoded_decoded_orMatrixOutputs_T_129}; // @[pla.scala:102:36, :114:36] wire [2:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_128}; // @[pla.scala:102:36, :114:36] wire [4:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_lo}; // @[pla.scala:102:36] wire [9:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_lo}; // @[pla.scala:102:36] wire [18:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo}; // @[pla.scala:102:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo_lo_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_132, _decoded_addr_decoded_decoded_orMatrixOutputs_T_131}; // @[pla.scala:102:36, :114:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo_lo_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_134, _decoded_addr_decoded_decoded_orMatrixOutputs_T_133}; // @[pla.scala:102:36, :114:36] wire [3:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo_lo_lo}; // @[pla.scala:102:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo_hi_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_136, _decoded_addr_decoded_decoded_orMatrixOutputs_T_135}; // @[pla.scala:102:36, :114:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo_hi_hi_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_139, _decoded_addr_decoded_decoded_orMatrixOutputs_T_138}; // @[pla.scala:102:36, :114:36] wire [2:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_137}; // @[pla.scala:102:36, :114:36] wire [4:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo_hi_lo}; // @[pla.scala:102:36] wire [8:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo_lo}; // @[pla.scala:102:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_lo_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_141, _decoded_addr_decoded_decoded_orMatrixOutputs_T_140}; // @[pla.scala:102:36, :114:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_lo_hi_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_144, _decoded_addr_decoded_decoded_orMatrixOutputs_T_143}; // @[pla.scala:102:36, :114:36] wire [2:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_lo_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_lo_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_142}; // @[pla.scala:102:36, :114:36] wire [4:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_lo_lo}; // @[pla.scala:102:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_146, _decoded_addr_decoded_decoded_orMatrixOutputs_T_145}; // @[pla.scala:102:36, :114:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_hi_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_149, _decoded_addr_decoded_decoded_orMatrixOutputs_T_148}; // @[pla.scala:102:36, :114:36] wire [2:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_147}; // @[pla.scala:102:36, :114:36] wire [4:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_lo}; // @[pla.scala:102:36] wire [9:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_lo}; // @[pla.scala:102:36] wire [18:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo}; // @[pla.scala:102:36] wire [37:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo}; // @[pla.scala:102:36] wire [74:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo}; // @[pla.scala:102:36] wire [149:0] decoded_addr_decoded_decoded_orMatrixOutputs = {decoded_addr_decoded_decoded_orMatrixOutputs_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo}; // @[pla.scala:102:36] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T = decoded_addr_decoded_decoded_orMatrixOutputs[0]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_1 = decoded_addr_decoded_decoded_orMatrixOutputs[1]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_2 = decoded_addr_decoded_decoded_orMatrixOutputs[2]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_3 = decoded_addr_decoded_decoded_orMatrixOutputs[3]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_4 = decoded_addr_decoded_decoded_orMatrixOutputs[4]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_5 = decoded_addr_decoded_decoded_orMatrixOutputs[5]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_6 = decoded_addr_decoded_decoded_orMatrixOutputs[6]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_7 = decoded_addr_decoded_decoded_orMatrixOutputs[7]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_8 = decoded_addr_decoded_decoded_orMatrixOutputs[8]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_9 = decoded_addr_decoded_decoded_orMatrixOutputs[9]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_10 = decoded_addr_decoded_decoded_orMatrixOutputs[10]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_11 = decoded_addr_decoded_decoded_orMatrixOutputs[11]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_12 = decoded_addr_decoded_decoded_orMatrixOutputs[12]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_13 = decoded_addr_decoded_decoded_orMatrixOutputs[13]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_14 = decoded_addr_decoded_decoded_orMatrixOutputs[14]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_15 = decoded_addr_decoded_decoded_orMatrixOutputs[15]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_16 = decoded_addr_decoded_decoded_orMatrixOutputs[16]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_17 = decoded_addr_decoded_decoded_orMatrixOutputs[17]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_18 = decoded_addr_decoded_decoded_orMatrixOutputs[18]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_19 = decoded_addr_decoded_decoded_orMatrixOutputs[19]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_20 = decoded_addr_decoded_decoded_orMatrixOutputs[20]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_21 = decoded_addr_decoded_decoded_orMatrixOutputs[21]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_22 = decoded_addr_decoded_decoded_orMatrixOutputs[22]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_23 = decoded_addr_decoded_decoded_orMatrixOutputs[23]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_24 = decoded_addr_decoded_decoded_orMatrixOutputs[24]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_25 = decoded_addr_decoded_decoded_orMatrixOutputs[25]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_26 = decoded_addr_decoded_decoded_orMatrixOutputs[26]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_27 = decoded_addr_decoded_decoded_orMatrixOutputs[27]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_28 = decoded_addr_decoded_decoded_orMatrixOutputs[28]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_29 = decoded_addr_decoded_decoded_orMatrixOutputs[29]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_30 = decoded_addr_decoded_decoded_orMatrixOutputs[30]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_31 = decoded_addr_decoded_decoded_orMatrixOutputs[31]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_32 = decoded_addr_decoded_decoded_orMatrixOutputs[32]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_33 = decoded_addr_decoded_decoded_orMatrixOutputs[33]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_34 = decoded_addr_decoded_decoded_orMatrixOutputs[34]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_35 = decoded_addr_decoded_decoded_orMatrixOutputs[35]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_36 = decoded_addr_decoded_decoded_orMatrixOutputs[36]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_37 = decoded_addr_decoded_decoded_orMatrixOutputs[37]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_38 = decoded_addr_decoded_decoded_orMatrixOutputs[38]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_39 = decoded_addr_decoded_decoded_orMatrixOutputs[39]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_40 = decoded_addr_decoded_decoded_orMatrixOutputs[40]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_41 = decoded_addr_decoded_decoded_orMatrixOutputs[41]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_42 = decoded_addr_decoded_decoded_orMatrixOutputs[42]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_43 = decoded_addr_decoded_decoded_orMatrixOutputs[43]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_44 = decoded_addr_decoded_decoded_orMatrixOutputs[44]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_45 = decoded_addr_decoded_decoded_orMatrixOutputs[45]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_46 = decoded_addr_decoded_decoded_orMatrixOutputs[46]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_47 = decoded_addr_decoded_decoded_orMatrixOutputs[47]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_48 = decoded_addr_decoded_decoded_orMatrixOutputs[48]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_49 = decoded_addr_decoded_decoded_orMatrixOutputs[49]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_50 = decoded_addr_decoded_decoded_orMatrixOutputs[50]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_51 = decoded_addr_decoded_decoded_orMatrixOutputs[51]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_52 = decoded_addr_decoded_decoded_orMatrixOutputs[52]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_53 = decoded_addr_decoded_decoded_orMatrixOutputs[53]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_54 = decoded_addr_decoded_decoded_orMatrixOutputs[54]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_55 = decoded_addr_decoded_decoded_orMatrixOutputs[55]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_56 = decoded_addr_decoded_decoded_orMatrixOutputs[56]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_57 = decoded_addr_decoded_decoded_orMatrixOutputs[57]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_58 = decoded_addr_decoded_decoded_orMatrixOutputs[58]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_59 = decoded_addr_decoded_decoded_orMatrixOutputs[59]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_60 = decoded_addr_decoded_decoded_orMatrixOutputs[60]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_61 = decoded_addr_decoded_decoded_orMatrixOutputs[61]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_62 = decoded_addr_decoded_decoded_orMatrixOutputs[62]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_63 = decoded_addr_decoded_decoded_orMatrixOutputs[63]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_64 = decoded_addr_decoded_decoded_orMatrixOutputs[64]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_65 = decoded_addr_decoded_decoded_orMatrixOutputs[65]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_66 = decoded_addr_decoded_decoded_orMatrixOutputs[66]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_67 = decoded_addr_decoded_decoded_orMatrixOutputs[67]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_68 = decoded_addr_decoded_decoded_orMatrixOutputs[68]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_69 = decoded_addr_decoded_decoded_orMatrixOutputs[69]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_70 = decoded_addr_decoded_decoded_orMatrixOutputs[70]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_71 = decoded_addr_decoded_decoded_orMatrixOutputs[71]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_72 = decoded_addr_decoded_decoded_orMatrixOutputs[72]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_73 = decoded_addr_decoded_decoded_orMatrixOutputs[73]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_74 = decoded_addr_decoded_decoded_orMatrixOutputs[74]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_75 = decoded_addr_decoded_decoded_orMatrixOutputs[75]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_76 = decoded_addr_decoded_decoded_orMatrixOutputs[76]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_77 = decoded_addr_decoded_decoded_orMatrixOutputs[77]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_78 = decoded_addr_decoded_decoded_orMatrixOutputs[78]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_79 = decoded_addr_decoded_decoded_orMatrixOutputs[79]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_80 = decoded_addr_decoded_decoded_orMatrixOutputs[80]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_81 = decoded_addr_decoded_decoded_orMatrixOutputs[81]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_82 = decoded_addr_decoded_decoded_orMatrixOutputs[82]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_83 = decoded_addr_decoded_decoded_orMatrixOutputs[83]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_84 = decoded_addr_decoded_decoded_orMatrixOutputs[84]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_85 = decoded_addr_decoded_decoded_orMatrixOutputs[85]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_86 = decoded_addr_decoded_decoded_orMatrixOutputs[86]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_87 = decoded_addr_decoded_decoded_orMatrixOutputs[87]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_88 = decoded_addr_decoded_decoded_orMatrixOutputs[88]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_89 = decoded_addr_decoded_decoded_orMatrixOutputs[89]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_90 = decoded_addr_decoded_decoded_orMatrixOutputs[90]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_91 = decoded_addr_decoded_decoded_orMatrixOutputs[91]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_92 = decoded_addr_decoded_decoded_orMatrixOutputs[92]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_93 = decoded_addr_decoded_decoded_orMatrixOutputs[93]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_94 = decoded_addr_decoded_decoded_orMatrixOutputs[94]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_95 = decoded_addr_decoded_decoded_orMatrixOutputs[95]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_96 = decoded_addr_decoded_decoded_orMatrixOutputs[96]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_97 = decoded_addr_decoded_decoded_orMatrixOutputs[97]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_98 = decoded_addr_decoded_decoded_orMatrixOutputs[98]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_99 = decoded_addr_decoded_decoded_orMatrixOutputs[99]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_100 = decoded_addr_decoded_decoded_orMatrixOutputs[100]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_101 = decoded_addr_decoded_decoded_orMatrixOutputs[101]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_102 = decoded_addr_decoded_decoded_orMatrixOutputs[102]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_103 = decoded_addr_decoded_decoded_orMatrixOutputs[103]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_104 = decoded_addr_decoded_decoded_orMatrixOutputs[104]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_105 = decoded_addr_decoded_decoded_orMatrixOutputs[105]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_106 = decoded_addr_decoded_decoded_orMatrixOutputs[106]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_107 = decoded_addr_decoded_decoded_orMatrixOutputs[107]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_108 = decoded_addr_decoded_decoded_orMatrixOutputs[108]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_109 = decoded_addr_decoded_decoded_orMatrixOutputs[109]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_110 = decoded_addr_decoded_decoded_orMatrixOutputs[110]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_111 = decoded_addr_decoded_decoded_orMatrixOutputs[111]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_112 = decoded_addr_decoded_decoded_orMatrixOutputs[112]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_113 = decoded_addr_decoded_decoded_orMatrixOutputs[113]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_114 = decoded_addr_decoded_decoded_orMatrixOutputs[114]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_115 = decoded_addr_decoded_decoded_orMatrixOutputs[115]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_116 = decoded_addr_decoded_decoded_orMatrixOutputs[116]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_117 = decoded_addr_decoded_decoded_orMatrixOutputs[117]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_118 = decoded_addr_decoded_decoded_orMatrixOutputs[118]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_119 = decoded_addr_decoded_decoded_orMatrixOutputs[119]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_120 = decoded_addr_decoded_decoded_orMatrixOutputs[120]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_121 = decoded_addr_decoded_decoded_orMatrixOutputs[121]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_122 = decoded_addr_decoded_decoded_orMatrixOutputs[122]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_123 = decoded_addr_decoded_decoded_orMatrixOutputs[123]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_124 = decoded_addr_decoded_decoded_orMatrixOutputs[124]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_125 = decoded_addr_decoded_decoded_orMatrixOutputs[125]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_126 = decoded_addr_decoded_decoded_orMatrixOutputs[126]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_127 = decoded_addr_decoded_decoded_orMatrixOutputs[127]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_128 = decoded_addr_decoded_decoded_orMatrixOutputs[128]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_129 = decoded_addr_decoded_decoded_orMatrixOutputs[129]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_130 = decoded_addr_decoded_decoded_orMatrixOutputs[130]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_131 = decoded_addr_decoded_decoded_orMatrixOutputs[131]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_132 = decoded_addr_decoded_decoded_orMatrixOutputs[132]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_133 = decoded_addr_decoded_decoded_orMatrixOutputs[133]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_134 = decoded_addr_decoded_decoded_orMatrixOutputs[134]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_135 = decoded_addr_decoded_decoded_orMatrixOutputs[135]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_136 = decoded_addr_decoded_decoded_orMatrixOutputs[136]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_137 = decoded_addr_decoded_decoded_orMatrixOutputs[137]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_138 = decoded_addr_decoded_decoded_orMatrixOutputs[138]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_139 = decoded_addr_decoded_decoded_orMatrixOutputs[139]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_140 = decoded_addr_decoded_decoded_orMatrixOutputs[140]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_141 = decoded_addr_decoded_decoded_orMatrixOutputs[141]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_142 = decoded_addr_decoded_decoded_orMatrixOutputs[142]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_143 = decoded_addr_decoded_decoded_orMatrixOutputs[143]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_144 = decoded_addr_decoded_decoded_orMatrixOutputs[144]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_145 = decoded_addr_decoded_decoded_orMatrixOutputs[145]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_146 = decoded_addr_decoded_decoded_orMatrixOutputs[146]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_147 = decoded_addr_decoded_decoded_orMatrixOutputs[147]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_148 = decoded_addr_decoded_decoded_orMatrixOutputs[148]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_149 = decoded_addr_decoded_decoded_orMatrixOutputs[149]; // @[pla.scala:102:36, :124:31] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo_lo_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_1, _decoded_addr_decoded_decoded_invMatrixOutputs_T}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo_lo_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_3, _decoded_addr_decoded_decoded_invMatrixOutputs_T_2}; // @[pla.scala:120:37, :124:31] wire [3:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo_lo_lo}; // @[pla.scala:120:37] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo_hi_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_5, _decoded_addr_decoded_decoded_invMatrixOutputs_T_4}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo_hi_hi_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_8, _decoded_addr_decoded_decoded_invMatrixOutputs_T_7}; // @[pla.scala:120:37, :124:31] wire [2:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_6}; // @[pla.scala:120:37, :124:31] wire [4:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo_hi_lo}; // @[pla.scala:120:37] wire [8:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo_lo}; // @[pla.scala:120:37] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi_lo_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_10, _decoded_addr_decoded_decoded_invMatrixOutputs_T_9}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi_lo_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_12, _decoded_addr_decoded_decoded_invMatrixOutputs_T_11}; // @[pla.scala:120:37, :124:31] wire [3:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi_lo_lo}; // @[pla.scala:120:37] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi_hi_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_14, _decoded_addr_decoded_decoded_invMatrixOutputs_T_13}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi_hi_hi_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_17, _decoded_addr_decoded_decoded_invMatrixOutputs_T_16}; // @[pla.scala:120:37, :124:31] wire [2:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_15}; // @[pla.scala:120:37, :124:31] wire [4:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi_hi_lo}; // @[pla.scala:120:37] wire [8:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi_lo}; // @[pla.scala:120:37] wire [17:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo}; // @[pla.scala:120:37] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo_lo_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_19, _decoded_addr_decoded_decoded_invMatrixOutputs_T_18}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo_lo_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_21, _decoded_addr_decoded_decoded_invMatrixOutputs_T_20}; // @[pla.scala:120:37, :124:31] wire [3:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo_lo_lo}; // @[pla.scala:120:37] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo_hi_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_23, _decoded_addr_decoded_decoded_invMatrixOutputs_T_22}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo_hi_hi_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_26, _decoded_addr_decoded_decoded_invMatrixOutputs_T_25}; // @[pla.scala:120:37, :124:31] wire [2:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_24}; // @[pla.scala:120:37, :124:31] wire [4:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo_hi_lo}; // @[pla.scala:120:37] wire [8:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo_lo}; // @[pla.scala:120:37] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_lo_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_28, _decoded_addr_decoded_decoded_invMatrixOutputs_T_27}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_lo_hi_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_31, _decoded_addr_decoded_decoded_invMatrixOutputs_T_30}; // @[pla.scala:120:37, :124:31] wire [2:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_lo_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_lo_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_29}; // @[pla.scala:120:37, :124:31] wire [4:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_lo_lo}; // @[pla.scala:120:37] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_hi_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_33, _decoded_addr_decoded_decoded_invMatrixOutputs_T_32}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_hi_hi_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_36, _decoded_addr_decoded_decoded_invMatrixOutputs_T_35}; // @[pla.scala:120:37, :124:31] wire [2:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_34}; // @[pla.scala:120:37, :124:31] wire [4:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_hi_lo}; // @[pla.scala:120:37] wire [9:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_lo}; // @[pla.scala:120:37] wire [18:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo}; // @[pla.scala:120:37] wire [36:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo}; // @[pla.scala:120:37] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo_lo_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_38, _decoded_addr_decoded_decoded_invMatrixOutputs_T_37}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo_lo_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_40, _decoded_addr_decoded_decoded_invMatrixOutputs_T_39}; // @[pla.scala:120:37, :124:31] wire [3:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo_lo_lo}; // @[pla.scala:120:37] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo_hi_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_42, _decoded_addr_decoded_decoded_invMatrixOutputs_T_41}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo_hi_hi_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_45, _decoded_addr_decoded_decoded_invMatrixOutputs_T_44}; // @[pla.scala:120:37, :124:31] wire [2:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_43}; // @[pla.scala:120:37, :124:31] wire [4:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo_hi_lo}; // @[pla.scala:120:37] wire [8:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo_lo}; // @[pla.scala:120:37] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_lo_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_47, _decoded_addr_decoded_decoded_invMatrixOutputs_T_46}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_lo_hi_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_50, _decoded_addr_decoded_decoded_invMatrixOutputs_T_49}; // @[pla.scala:120:37, :124:31] wire [2:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_lo_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_lo_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_48}; // @[pla.scala:120:37, :124:31] wire [4:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_lo_lo}; // @[pla.scala:120:37] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_hi_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_52, _decoded_addr_decoded_decoded_invMatrixOutputs_T_51}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_hi_hi_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_55, _decoded_addr_decoded_decoded_invMatrixOutputs_T_54}; // @[pla.scala:120:37, :124:31] wire [2:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_53}; // @[pla.scala:120:37, :124:31] wire [4:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_hi_lo}; // @[pla.scala:120:37] wire [9:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_lo}; // @[pla.scala:120:37] wire [18:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo}; // @[pla.scala:120:37] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo_lo_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_57, _decoded_addr_decoded_decoded_invMatrixOutputs_T_56}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo_lo_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_59, _decoded_addr_decoded_decoded_invMatrixOutputs_T_58}; // @[pla.scala:120:37, :124:31] wire [3:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo_lo_lo}; // @[pla.scala:120:37] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo_hi_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_61, _decoded_addr_decoded_decoded_invMatrixOutputs_T_60}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo_hi_hi_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_64, _decoded_addr_decoded_decoded_invMatrixOutputs_T_63}; // @[pla.scala:120:37, :124:31] wire [2:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_62}; // @[pla.scala:120:37, :124:31] wire [4:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo_hi_lo}; // @[pla.scala:120:37] wire [8:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo_lo}; // @[pla.scala:120:37] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_lo_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_66, _decoded_addr_decoded_decoded_invMatrixOutputs_T_65}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_lo_hi_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_69, _decoded_addr_decoded_decoded_invMatrixOutputs_T_68}; // @[pla.scala:120:37, :124:31] wire [2:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_lo_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_lo_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_67}; // @[pla.scala:120:37, :124:31] wire [4:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_lo_lo}; // @[pla.scala:120:37] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_hi_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_71, _decoded_addr_decoded_decoded_invMatrixOutputs_T_70}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_hi_hi_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_74, _decoded_addr_decoded_decoded_invMatrixOutputs_T_73}; // @[pla.scala:120:37, :124:31] wire [2:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_72}; // @[pla.scala:120:37, :124:31] wire [4:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_hi_lo}; // @[pla.scala:120:37] wire [9:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_lo}; // @[pla.scala:120:37] wire [18:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo}; // @[pla.scala:120:37] wire [37:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo}; // @[pla.scala:120:37] wire [74:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo}; // @[pla.scala:120:37] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo_lo_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_76, _decoded_addr_decoded_decoded_invMatrixOutputs_T_75}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo_lo_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_78, _decoded_addr_decoded_decoded_invMatrixOutputs_T_77}; // @[pla.scala:120:37, :124:31] wire [3:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo_lo_lo}; // @[pla.scala:120:37] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo_hi_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_80, _decoded_addr_decoded_decoded_invMatrixOutputs_T_79}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo_hi_hi_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_83, _decoded_addr_decoded_decoded_invMatrixOutputs_T_82}; // @[pla.scala:120:37, :124:31] wire [2:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_81}; // @[pla.scala:120:37, :124:31] wire [4:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo_hi_lo}; // @[pla.scala:120:37] wire [8:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo_lo}; // @[pla.scala:120:37] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi_lo_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_85, _decoded_addr_decoded_decoded_invMatrixOutputs_T_84}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi_lo_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_87, _decoded_addr_decoded_decoded_invMatrixOutputs_T_86}; // @[pla.scala:120:37, :124:31] wire [3:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi_lo_lo}; // @[pla.scala:120:37] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi_hi_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_89, _decoded_addr_decoded_decoded_invMatrixOutputs_T_88}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi_hi_hi_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_92, _decoded_addr_decoded_decoded_invMatrixOutputs_T_91}; // @[pla.scala:120:37, :124:31] wire [2:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_90}; // @[pla.scala:120:37, :124:31] wire [4:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi_hi_lo}; // @[pla.scala:120:37] wire [8:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi_lo}; // @[pla.scala:120:37] wire [17:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo}; // @[pla.scala:120:37] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo_lo_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_94, _decoded_addr_decoded_decoded_invMatrixOutputs_T_93}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo_lo_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_96, _decoded_addr_decoded_decoded_invMatrixOutputs_T_95}; // @[pla.scala:120:37, :124:31] wire [3:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo_lo_lo}; // @[pla.scala:120:37] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo_hi_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_98, _decoded_addr_decoded_decoded_invMatrixOutputs_T_97}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo_hi_hi_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_101, _decoded_addr_decoded_decoded_invMatrixOutputs_T_100}; // @[pla.scala:120:37, :124:31] wire [2:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_99}; // @[pla.scala:120:37, :124:31] wire [4:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo_hi_lo}; // @[pla.scala:120:37] wire [8:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo_lo}; // @[pla.scala:120:37] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_lo_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_103, _decoded_addr_decoded_decoded_invMatrixOutputs_T_102}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_lo_hi_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_106, _decoded_addr_decoded_decoded_invMatrixOutputs_T_105}; // @[pla.scala:120:37, :124:31] wire [2:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_lo_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_lo_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_104}; // @[pla.scala:120:37, :124:31] wire [4:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_lo_lo}; // @[pla.scala:120:37] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_hi_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_108, _decoded_addr_decoded_decoded_invMatrixOutputs_T_107}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_hi_hi_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_111, _decoded_addr_decoded_decoded_invMatrixOutputs_T_110}; // @[pla.scala:120:37, :124:31] wire [2:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_109}; // @[pla.scala:120:37, :124:31] wire [4:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_hi_lo}; // @[pla.scala:120:37] wire [9:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_lo}; // @[pla.scala:120:37] wire [18:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo}; // @[pla.scala:120:37] wire [36:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo}; // @[pla.scala:120:37] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo_lo_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_113, _decoded_addr_decoded_decoded_invMatrixOutputs_T_112}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo_lo_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_115, _decoded_addr_decoded_decoded_invMatrixOutputs_T_114}; // @[pla.scala:120:37, :124:31] wire [3:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo_lo_lo}; // @[pla.scala:120:37] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo_hi_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_117, _decoded_addr_decoded_decoded_invMatrixOutputs_T_116}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo_hi_hi_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_120, _decoded_addr_decoded_decoded_invMatrixOutputs_T_119}; // @[pla.scala:120:37, :124:31] wire [2:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_118}; // @[pla.scala:120:37, :124:31] wire [4:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo_hi_lo}; // @[pla.scala:120:37] wire [8:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo_lo}; // @[pla.scala:120:37] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_lo_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_122, _decoded_addr_decoded_decoded_invMatrixOutputs_T_121}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_lo_hi_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_125, _decoded_addr_decoded_decoded_invMatrixOutputs_T_124}; // @[pla.scala:120:37, :124:31] wire [2:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_lo_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_lo_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_123}; // @[pla.scala:120:37, :124:31] wire [4:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_lo_lo}; // @[pla.scala:120:37] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_hi_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_127, _decoded_addr_decoded_decoded_invMatrixOutputs_T_126}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_hi_hi_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_130, _decoded_addr_decoded_decoded_invMatrixOutputs_T_129}; // @[pla.scala:120:37, :124:31] wire [2:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_128}; // @[pla.scala:120:37, :124:31] wire [4:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_hi_lo}; // @[pla.scala:120:37] wire [9:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_lo}; // @[pla.scala:120:37] wire [18:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo}; // @[pla.scala:120:37] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo_lo_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_132, _decoded_addr_decoded_decoded_invMatrixOutputs_T_131}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo_lo_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_134, _decoded_addr_decoded_decoded_invMatrixOutputs_T_133}; // @[pla.scala:120:37, :124:31] wire [3:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo_lo_lo}; // @[pla.scala:120:37] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo_hi_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_136, _decoded_addr_decoded_decoded_invMatrixOutputs_T_135}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo_hi_hi_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_139, _decoded_addr_decoded_decoded_invMatrixOutputs_T_138}; // @[pla.scala:120:37, :124:31] wire [2:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_137}; // @[pla.scala:120:37, :124:31] wire [4:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo_hi_lo}; // @[pla.scala:120:37] wire [8:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo_lo}; // @[pla.scala:120:37] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_lo_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_141, _decoded_addr_decoded_decoded_invMatrixOutputs_T_140}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_lo_hi_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_144, _decoded_addr_decoded_decoded_invMatrixOutputs_T_143}; // @[pla.scala:120:37, :124:31] wire [2:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_lo_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_lo_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_142}; // @[pla.scala:120:37, :124:31] wire [4:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_lo_lo}; // @[pla.scala:120:37] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_hi_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_146, _decoded_addr_decoded_decoded_invMatrixOutputs_T_145}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_hi_hi_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_149, _decoded_addr_decoded_decoded_invMatrixOutputs_T_148}; // @[pla.scala:120:37, :124:31] wire [2:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_147}; // @[pla.scala:120:37, :124:31] wire [4:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_hi_lo}; // @[pla.scala:120:37] wire [9:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_lo}; // @[pla.scala:120:37] wire [18:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo}; // @[pla.scala:120:37] wire [37:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo}; // @[pla.scala:120:37] wire [74:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo}; // @[pla.scala:120:37] assign decoded_addr_decoded_decoded_invMatrixOutputs = {decoded_addr_decoded_decoded_invMatrixOutputs_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo}; // @[pla.scala:120:37] assign decoded_addr_decoded_decoded = decoded_addr_decoded_decoded_invMatrixOutputs; // @[pla.scala:81:23, :120:37] assign decoded_addr_decoded_decoded_plaInput = decoded_addr_addr[11:0]; // @[pla.scala:77:22] wire decoded_addr_decoded_0 = decoded_addr_decoded_decoded[149]; // @[pla.scala:81:23] wire decoded_addr_97_2 = decoded_addr_decoded_0; // @[Decode.scala:50:77] wire decoded_addr_decoded_1 = decoded_addr_decoded_decoded[148]; // @[pla.scala:81:23] wire decoded_addr_55_2 = decoded_addr_decoded_1; // @[Decode.scala:50:77] wire decoded_addr_decoded_2 = decoded_addr_decoded_decoded[147]; // @[pla.scala:81:23] wire decoded_addr_10_2 = decoded_addr_decoded_2; // @[Decode.scala:50:77] wire decoded_addr_decoded_3 = decoded_addr_decoded_decoded[146]; // @[pla.scala:81:23] wire decoded_addr_118_2 = decoded_addr_decoded_3; // @[Decode.scala:50:77] wire decoded_addr_decoded_4 = decoded_addr_decoded_decoded[145]; // @[pla.scala:81:23] wire decoded_addr_94_2 = decoded_addr_decoded_4; // @[Decode.scala:50:77] wire decoded_addr_decoded_5 = decoded_addr_decoded_decoded[144]; // @[pla.scala:81:23] wire decoded_addr_100_2 = decoded_addr_decoded_5; // @[Decode.scala:50:77] wire decoded_addr_decoded_6 = decoded_addr_decoded_decoded[143]; // @[pla.scala:81:23] wire decoded_addr_72_2 = decoded_addr_decoded_6; // @[Decode.scala:50:77] wire decoded_addr_decoded_7 = decoded_addr_decoded_decoded[142]; // @[pla.scala:81:23] wire decoded_addr_108_2 = decoded_addr_decoded_7; // @[Decode.scala:50:77] wire decoded_addr_decoded_8 = decoded_addr_decoded_decoded[141]; // @[pla.scala:81:23] wire decoded_addr_76_2 = decoded_addr_decoded_8; // @[Decode.scala:50:77] wire decoded_addr_decoded_9 = decoded_addr_decoded_decoded[140]; // @[pla.scala:81:23] wire decoded_addr_129_2 = decoded_addr_decoded_9; // @[Decode.scala:50:77] wire decoded_addr_decoded_10 = decoded_addr_decoded_decoded[139]; // @[pla.scala:81:23] wire decoded_addr_132_2 = decoded_addr_decoded_10; // @[Decode.scala:50:77] wire decoded_addr_decoded_11 = decoded_addr_decoded_decoded[138]; // @[pla.scala:81:23] wire decoded_addr_136_2 = decoded_addr_decoded_11; // @[Decode.scala:50:77] wire decoded_addr_decoded_12 = decoded_addr_decoded_decoded[137]; // @[pla.scala:81:23] wire decoded_addr_29_2 = decoded_addr_decoded_12; // @[Decode.scala:50:77] wire decoded_addr_decoded_13 = decoded_addr_decoded_decoded[136]; // @[pla.scala:81:23] wire decoded_addr_131_2 = decoded_addr_decoded_13; // @[Decode.scala:50:77] wire decoded_addr_decoded_14 = decoded_addr_decoded_decoded[135]; // @[pla.scala:81:23] wire decoded_addr_49_2 = decoded_addr_decoded_14; // @[Decode.scala:50:77] wire decoded_addr_decoded_15 = decoded_addr_decoded_decoded[134]; // @[pla.scala:81:23] wire decoded_addr_89_2 = decoded_addr_decoded_15; // @[Decode.scala:50:77] wire decoded_addr_decoded_16 = decoded_addr_decoded_decoded[133]; // @[pla.scala:81:23] wire decoded_addr_57_2 = decoded_addr_decoded_16; // @[Decode.scala:50:77] wire decoded_addr_decoded_17 = decoded_addr_decoded_decoded[132]; // @[pla.scala:81:23] wire decoded_addr_36_2 = decoded_addr_decoded_17; // @[Decode.scala:50:77] wire decoded_addr_decoded_18 = decoded_addr_decoded_decoded[131]; // @[pla.scala:81:23] wire decoded_addr_68_2 = decoded_addr_decoded_18; // @[Decode.scala:50:77] wire decoded_addr_decoded_19 = decoded_addr_decoded_decoded[130]; // @[pla.scala:81:23] wire decoded_addr_99_2 = decoded_addr_decoded_19; // @[Decode.scala:50:77] wire decoded_addr_decoded_20 = decoded_addr_decoded_decoded[129]; // @[pla.scala:81:23] wire decoded_addr_130_2 = decoded_addr_decoded_20; // @[Decode.scala:50:77] wire decoded_addr_decoded_21 = decoded_addr_decoded_decoded[128]; // @[pla.scala:81:23] wire decoded_addr_103_2 = decoded_addr_decoded_21; // @[Decode.scala:50:77] wire decoded_addr_decoded_22 = decoded_addr_decoded_decoded[127]; // @[pla.scala:81:23] wire decoded_addr_121_2 = decoded_addr_decoded_22; // @[Decode.scala:50:77] wire decoded_addr_decoded_23 = decoded_addr_decoded_decoded[126]; // @[pla.scala:81:23] wire decoded_addr_146_2 = decoded_addr_decoded_23; // @[Decode.scala:50:77] wire decoded_addr_decoded_24 = decoded_addr_decoded_decoded[125]; // @[pla.scala:81:23] wire decoded_addr_17_2 = decoded_addr_decoded_24; // @[Decode.scala:50:77] wire decoded_addr_decoded_25 = decoded_addr_decoded_decoded[124]; // @[pla.scala:81:23] wire decoded_addr_27_2 = decoded_addr_decoded_25; // @[Decode.scala:50:77] wire decoded_addr_decoded_26 = decoded_addr_decoded_decoded[123]; // @[pla.scala:81:23] wire decoded_addr_83_2 = decoded_addr_decoded_26; // @[Decode.scala:50:77] wire decoded_addr_decoded_27 = decoded_addr_decoded_decoded[122]; // @[pla.scala:81:23] wire decoded_addr_52_2 = decoded_addr_decoded_27; // @[Decode.scala:50:77] wire decoded_addr_decoded_28 = decoded_addr_decoded_decoded[121]; // @[pla.scala:81:23] wire decoded_addr_144_2 = decoded_addr_decoded_28; // @[Decode.scala:50:77] wire decoded_addr_decoded_29 = decoded_addr_decoded_decoded[120]; // @[pla.scala:81:23] wire decoded_addr_70_2 = decoded_addr_decoded_29; // @[Decode.scala:50:77] wire decoded_addr_decoded_30 = decoded_addr_decoded_decoded[119]; // @[pla.scala:81:23] wire decoded_addr_111_2 = decoded_addr_decoded_30; // @[Decode.scala:50:77] wire decoded_addr_decoded_31 = decoded_addr_decoded_decoded[118]; // @[pla.scala:81:23] wire decoded_addr_82_2 = decoded_addr_decoded_31; // @[Decode.scala:50:77] wire decoded_addr_decoded_32 = decoded_addr_decoded_decoded[117]; // @[pla.scala:81:23] wire decoded_addr_31_2 = decoded_addr_decoded_32; // @[Decode.scala:50:77] wire decoded_addr_decoded_33 = decoded_addr_decoded_decoded[116]; // @[pla.scala:81:23] wire decoded_addr_0_2 = decoded_addr_decoded_33; // @[Decode.scala:50:77] wire decoded_addr_decoded_34 = decoded_addr_decoded_decoded[115]; // @[pla.scala:81:23] wire decoded_addr_59_2 = decoded_addr_decoded_34; // @[Decode.scala:50:77] wire decoded_addr_decoded_35 = decoded_addr_decoded_decoded[114]; // @[pla.scala:81:23] wire decoded_addr_138_2 = decoded_addr_decoded_35; // @[Decode.scala:50:77] wire decoded_addr_decoded_36 = decoded_addr_decoded_decoded[113]; // @[pla.scala:81:23] wire decoded_addr_126_2 = decoded_addr_decoded_36; // @[Decode.scala:50:77] wire decoded_addr_decoded_37 = decoded_addr_decoded_decoded[112]; // @[pla.scala:81:23] wire decoded_addr_74_2 = decoded_addr_decoded_37; // @[Decode.scala:50:77] wire decoded_addr_decoded_38 = decoded_addr_decoded_decoded[111]; // @[pla.scala:81:23] wire decoded_addr_116_2 = decoded_addr_decoded_38; // @[Decode.scala:50:77] wire decoded_addr_decoded_39 = decoded_addr_decoded_decoded[110]; // @[pla.scala:81:23] wire decoded_addr_90_2 = decoded_addr_decoded_39; // @[Decode.scala:50:77] wire decoded_addr_decoded_40 = decoded_addr_decoded_decoded[109]; // @[pla.scala:81:23] wire decoded_addr_113_2 = decoded_addr_decoded_40; // @[Decode.scala:50:77] wire decoded_addr_decoded_41 = decoded_addr_decoded_decoded[108]; // @[pla.scala:81:23] wire decoded_addr_1_2 = decoded_addr_decoded_41; // @[Decode.scala:50:77] wire decoded_addr_decoded_42 = decoded_addr_decoded_decoded[107]; // @[pla.scala:81:23] wire decoded_addr_16_2 = decoded_addr_decoded_42; // @[Decode.scala:50:77] wire decoded_addr_decoded_43 = decoded_addr_decoded_decoded[106]; // @[pla.scala:81:23] wire decoded_addr_78_2 = decoded_addr_decoded_43; // @[Decode.scala:50:77] wire decoded_addr_decoded_44 = decoded_addr_decoded_decoded[105]; // @[pla.scala:81:23] wire decoded_addr_39_2 = decoded_addr_decoded_44; // @[Decode.scala:50:77] wire decoded_addr_decoded_45 = decoded_addr_decoded_decoded[104]; // @[pla.scala:81:23] wire decoded_addr_51_2 = decoded_addr_decoded_45; // @[Decode.scala:50:77] wire decoded_addr_decoded_46 = decoded_addr_decoded_decoded[103]; // @[pla.scala:81:23] wire decoded_addr_109_2 = decoded_addr_decoded_46; // @[Decode.scala:50:77] wire decoded_addr_decoded_47 = decoded_addr_decoded_decoded[102]; // @[pla.scala:81:23] wire decoded_addr_91_2 = decoded_addr_decoded_47; // @[Decode.scala:50:77] wire decoded_addr_decoded_48 = decoded_addr_decoded_decoded[101]; // @[pla.scala:81:23] wire decoded_addr_81_2 = decoded_addr_decoded_48; // @[Decode.scala:50:77] wire decoded_addr_decoded_49 = decoded_addr_decoded_decoded[100]; // @[pla.scala:81:23] wire decoded_addr_67_2 = decoded_addr_decoded_49; // @[Decode.scala:50:77] wire decoded_addr_decoded_50 = decoded_addr_decoded_decoded[99]; // @[pla.scala:81:23] wire decoded_addr_105_2 = decoded_addr_decoded_50; // @[Decode.scala:50:77] wire decoded_addr_decoded_51 = decoded_addr_decoded_decoded[98]; // @[pla.scala:81:23] wire decoded_addr_122_2 = decoded_addr_decoded_51; // @[Decode.scala:50:77] wire decoded_addr_decoded_52 = decoded_addr_decoded_decoded[97]; // @[pla.scala:81:23] wire decoded_addr_24_2 = decoded_addr_decoded_52; // @[Decode.scala:50:77] wire decoded_addr_decoded_53 = decoded_addr_decoded_decoded[96]; // @[pla.scala:81:23] wire decoded_addr_124_2 = decoded_addr_decoded_53; // @[Decode.scala:50:77] wire decoded_addr_decoded_54 = decoded_addr_decoded_decoded[95]; // @[pla.scala:81:23] wire decoded_addr_26_2 = decoded_addr_decoded_54; // @[Decode.scala:50:77] wire decoded_addr_decoded_55 = decoded_addr_decoded_decoded[94]; // @[pla.scala:81:23] wire decoded_addr_128_2 = decoded_addr_decoded_55; // @[Decode.scala:50:77] wire decoded_addr_decoded_56 = decoded_addr_decoded_decoded[93]; // @[pla.scala:81:23] wire decoded_addr_7_2 = decoded_addr_decoded_56; // @[Decode.scala:50:77] wire decoded_addr_decoded_57 = decoded_addr_decoded_decoded[92]; // @[pla.scala:81:23] wire decoded_addr_62_2 = decoded_addr_decoded_57; // @[Decode.scala:50:77] wire decoded_addr_decoded_58 = decoded_addr_decoded_decoded[91]; // @[pla.scala:81:23] wire decoded_addr_77_2 = decoded_addr_decoded_58; // @[Decode.scala:50:77] wire decoded_addr_decoded_59 = decoded_addr_decoded_decoded[90]; // @[pla.scala:81:23] wire decoded_addr_46_2 = decoded_addr_decoded_59; // @[Decode.scala:50:77] wire decoded_addr_decoded_60 = decoded_addr_decoded_decoded[89]; // @[pla.scala:81:23] wire decoded_addr_112_2 = decoded_addr_decoded_60; // @[Decode.scala:50:77] wire decoded_addr_decoded_61 = decoded_addr_decoded_decoded[88]; // @[pla.scala:81:23] wire decoded_addr_60_2 = decoded_addr_decoded_61; // @[Decode.scala:50:77] wire decoded_addr_decoded_62 = decoded_addr_decoded_decoded[87]; // @[pla.scala:81:23] wire decoded_addr_92_2 = decoded_addr_decoded_62; // @[Decode.scala:50:77] wire decoded_addr_decoded_63 = decoded_addr_decoded_decoded[86]; // @[pla.scala:81:23] wire decoded_addr_148_2 = decoded_addr_decoded_63; // @[Decode.scala:50:77] wire decoded_addr_decoded_64 = decoded_addr_decoded_decoded[85]; // @[pla.scala:81:23] wire decoded_addr_14_2 = decoded_addr_decoded_64; // @[Decode.scala:50:77] wire decoded_addr_decoded_65 = decoded_addr_decoded_decoded[84]; // @[pla.scala:81:23] wire decoded_addr_21_2 = decoded_addr_decoded_65; // @[Decode.scala:50:77] wire decoded_addr_decoded_66 = decoded_addr_decoded_decoded[83]; // @[pla.scala:81:23] wire decoded_addr_33_2 = decoded_addr_decoded_66; // @[Decode.scala:50:77] wire decoded_addr_decoded_67 = decoded_addr_decoded_decoded[82]; // @[pla.scala:81:23] wire decoded_addr_19_2 = decoded_addr_decoded_67; // @[Decode.scala:50:77] wire decoded_addr_decoded_68 = decoded_addr_decoded_decoded[81]; // @[pla.scala:81:23] wire decoded_addr_133_2 = decoded_addr_decoded_68; // @[Decode.scala:50:77] wire decoded_addr_decoded_69 = decoded_addr_decoded_decoded[80]; // @[pla.scala:81:23] wire decoded_addr_149_2 = decoded_addr_decoded_69; // @[Decode.scala:50:77] wire decoded_addr_decoded_70 = decoded_addr_decoded_decoded[79]; // @[pla.scala:81:23] wire decoded_addr_50_2 = decoded_addr_decoded_70; // @[Decode.scala:50:77] wire decoded_addr_decoded_71 = decoded_addr_decoded_decoded[78]; // @[pla.scala:81:23] wire decoded_addr_75_2 = decoded_addr_decoded_71; // @[Decode.scala:50:77] wire decoded_addr_decoded_72 = decoded_addr_decoded_decoded[77]; // @[pla.scala:81:23] wire decoded_addr_102_2 = decoded_addr_decoded_72; // @[Decode.scala:50:77] wire decoded_addr_decoded_73 = decoded_addr_decoded_decoded[76]; // @[pla.scala:81:23] wire decoded_addr_84_2 = decoded_addr_decoded_73; // @[Decode.scala:50:77] wire decoded_addr_decoded_74 = decoded_addr_decoded_decoded[75]; // @[pla.scala:81:23] wire decoded_addr_45_2 = decoded_addr_decoded_74; // @[Decode.scala:50:77] wire decoded_addr_decoded_75 = decoded_addr_decoded_decoded[74]; // @[pla.scala:81:23] wire decoded_addr_64_2 = decoded_addr_decoded_75; // @[Decode.scala:50:77] wire decoded_addr_decoded_76 = decoded_addr_decoded_decoded[73]; // @[pla.scala:81:23] wire decoded_addr_120_2 = decoded_addr_decoded_76; // @[Decode.scala:50:77] wire decoded_addr_decoded_77 = decoded_addr_decoded_decoded[72]; // @[pla.scala:81:23] wire decoded_addr_30_2 = decoded_addr_decoded_77; // @[Decode.scala:50:77] wire decoded_addr_decoded_78 = decoded_addr_decoded_decoded[71]; // @[pla.scala:81:23] wire decoded_addr_5_2 = decoded_addr_decoded_78; // @[Decode.scala:50:77] wire decoded_addr_decoded_79 = decoded_addr_decoded_decoded[70]; // @[pla.scala:81:23] wire decoded_addr_32_2 = decoded_addr_decoded_79; // @[Decode.scala:50:77] wire decoded_addr_decoded_80 = decoded_addr_decoded_decoded[69]; // @[pla.scala:81:23] wire decoded_addr_143_2 = decoded_addr_decoded_80; // @[Decode.scala:50:77] wire decoded_addr_decoded_81 = decoded_addr_decoded_decoded[68]; // @[pla.scala:81:23] wire decoded_addr_117_2 = decoded_addr_decoded_81; // @[Decode.scala:50:77] wire decoded_addr_decoded_82 = decoded_addr_decoded_decoded[67]; // @[pla.scala:81:23] wire decoded_addr_63_2 = decoded_addr_decoded_82; // @[Decode.scala:50:77] wire decoded_addr_decoded_83 = decoded_addr_decoded_decoded[66]; // @[pla.scala:81:23] wire decoded_addr_107_2 = decoded_addr_decoded_83; // @[Decode.scala:50:77] wire decoded_addr_decoded_84 = decoded_addr_decoded_decoded[65]; // @[pla.scala:81:23] wire decoded_addr_88_2 = decoded_addr_decoded_84; // @[Decode.scala:50:77] wire decoded_addr_decoded_85 = decoded_addr_decoded_decoded[64]; // @[pla.scala:81:23] wire decoded_addr_114_2 = decoded_addr_decoded_85; // @[Decode.scala:50:77] wire decoded_addr_decoded_86 = decoded_addr_decoded_decoded[63]; // @[pla.scala:81:23] wire decoded_addr_73_2 = decoded_addr_decoded_86; // @[Decode.scala:50:77] wire decoded_addr_decoded_87 = decoded_addr_decoded_decoded[62]; // @[pla.scala:81:23] wire decoded_addr_53_2 = decoded_addr_decoded_87; // @[Decode.scala:50:77] wire decoded_addr_decoded_88 = decoded_addr_decoded_decoded[61]; // @[pla.scala:81:23] wire decoded_addr_147_2 = decoded_addr_decoded_88; // @[Decode.scala:50:77] wire decoded_addr_decoded_89 = decoded_addr_decoded_decoded[60]; // @[pla.scala:81:23] wire decoded_addr_41_2 = decoded_addr_decoded_89; // @[Decode.scala:50:77] wire decoded_addr_decoded_90 = decoded_addr_decoded_decoded[59]; // @[pla.scala:81:23] wire decoded_addr_56_2 = decoded_addr_decoded_90; // @[Decode.scala:50:77] wire decoded_addr_decoded_91 = decoded_addr_decoded_decoded[58]; // @[pla.scala:81:23] wire decoded_addr_37_2 = decoded_addr_decoded_91; // @[Decode.scala:50:77] wire decoded_addr_decoded_92 = decoded_addr_decoded_decoded[57]; // @[pla.scala:81:23] wire decoded_addr_79_2 = decoded_addr_decoded_92; // @[Decode.scala:50:77] wire decoded_addr_decoded_93 = decoded_addr_decoded_decoded[56]; // @[pla.scala:81:23] wire decoded_addr_96_2 = decoded_addr_decoded_93; // @[Decode.scala:50:77] wire decoded_addr_decoded_94 = decoded_addr_decoded_decoded[55]; // @[pla.scala:81:23] wire decoded_addr_4_2 = decoded_addr_decoded_94; // @[Decode.scala:50:77] wire decoded_addr_decoded_95 = decoded_addr_decoded_decoded[54]; // @[pla.scala:81:23] wire decoded_addr_101_2 = decoded_addr_decoded_95; // @[Decode.scala:50:77] wire decoded_addr_decoded_96 = decoded_addr_decoded_decoded[53]; // @[pla.scala:81:23] wire decoded_addr_119_2 = decoded_addr_decoded_96; // @[Decode.scala:50:77] wire decoded_addr_decoded_97 = decoded_addr_decoded_decoded[52]; // @[pla.scala:81:23] wire decoded_addr_22_2 = decoded_addr_decoded_97; // @[Decode.scala:50:77] wire decoded_addr_decoded_98 = decoded_addr_decoded_decoded[51]; // @[pla.scala:81:23] wire decoded_addr_139_2 = decoded_addr_decoded_98; // @[Decode.scala:50:77] wire decoded_addr_decoded_99 = decoded_addr_decoded_decoded[50]; // @[pla.scala:81:23] wire decoded_addr_11_2 = decoded_addr_decoded_99; // @[Decode.scala:50:77] wire decoded_addr_decoded_100 = decoded_addr_decoded_decoded[49]; // @[pla.scala:81:23] wire decoded_addr_134_2 = decoded_addr_decoded_100; // @[Decode.scala:50:77] wire decoded_addr_decoded_101 = decoded_addr_decoded_decoded[48]; // @[pla.scala:81:23] wire decoded_addr_12_2 = decoded_addr_decoded_101; // @[Decode.scala:50:77] wire decoded_addr_decoded_102 = decoded_addr_decoded_decoded[47]; // @[pla.scala:81:23] wire decoded_addr_65_2 = decoded_addr_decoded_102; // @[Decode.scala:50:77] wire decoded_addr_decoded_103 = decoded_addr_decoded_decoded[46]; // @[pla.scala:81:23] wire decoded_addr_86_2 = decoded_addr_decoded_103; // @[Decode.scala:50:77] wire decoded_addr_decoded_104 = decoded_addr_decoded_decoded[45]; // @[pla.scala:81:23] wire decoded_addr_47_2 = decoded_addr_decoded_104; // @[Decode.scala:50:77] wire decoded_addr_decoded_105 = decoded_addr_decoded_decoded[44]; // @[pla.scala:81:23] wire decoded_addr_106_2 = decoded_addr_decoded_105; // @[Decode.scala:50:77] wire decoded_addr_decoded_106 = decoded_addr_decoded_decoded[43]; // @[pla.scala:81:23] wire decoded_addr_58_2 = decoded_addr_decoded_106; // @[Decode.scala:50:77] wire decoded_addr_decoded_107 = decoded_addr_decoded_decoded[42]; // @[pla.scala:81:23] wire decoded_addr_87_2 = decoded_addr_decoded_107; // @[Decode.scala:50:77] wire decoded_addr_decoded_108 = decoded_addr_decoded_decoded[41]; // @[pla.scala:81:23] wire decoded_addr_142_2 = decoded_addr_decoded_108; // @[Decode.scala:50:77] wire decoded_addr_decoded_109 = decoded_addr_decoded_decoded[40]; // @[pla.scala:81:23] wire decoded_addr_13_2 = decoded_addr_decoded_109; // @[Decode.scala:50:77] wire decoded_addr_decoded_110 = decoded_addr_decoded_decoded[39]; // @[pla.scala:81:23] wire decoded_addr_35_2 = decoded_addr_decoded_110; // @[Decode.scala:50:77] wire decoded_addr_decoded_111 = decoded_addr_decoded_decoded[38]; // @[pla.scala:81:23] wire decoded_addr_2_2 = decoded_addr_decoded_111; // @[Decode.scala:50:77] wire decoded_addr_decoded_112 = decoded_addr_decoded_decoded[37]; // @[pla.scala:81:23] wire decoded_addr_66_2 = decoded_addr_decoded_112; // @[Decode.scala:50:77] wire decoded_addr_decoded_113 = decoded_addr_decoded_decoded[36]; // @[pla.scala:81:23] wire decoded_addr_42_2 = decoded_addr_decoded_113; // @[Decode.scala:50:77] wire decoded_addr_decoded_114 = decoded_addr_decoded_decoded[35]; // @[pla.scala:81:23] wire decoded_addr_61_2 = decoded_addr_decoded_114; // @[Decode.scala:50:77] wire decoded_addr_decoded_115 = decoded_addr_decoded_decoded[34]; // @[pla.scala:81:23] wire decoded_addr_48_2 = decoded_addr_decoded_115; // @[Decode.scala:50:77] wire decoded_addr_decoded_116 = decoded_addr_decoded_decoded[33]; // @[pla.scala:81:23] wire decoded_addr_44_2 = decoded_addr_decoded_116; // @[Decode.scala:50:77] wire decoded_addr_decoded_117 = decoded_addr_decoded_decoded[32]; // @[pla.scala:81:23] wire decoded_addr_15_2 = decoded_addr_decoded_117; // @[Decode.scala:50:77] wire decoded_addr_decoded_118 = decoded_addr_decoded_decoded[31]; // @[pla.scala:81:23] wire decoded_addr_145_2 = decoded_addr_decoded_118; // @[Decode.scala:50:77] wire decoded_addr_decoded_119 = decoded_addr_decoded_decoded[30]; // @[pla.scala:81:23] wire decoded_addr_93_2 = decoded_addr_decoded_119; // @[Decode.scala:50:77] wire decoded_addr_decoded_120 = decoded_addr_decoded_decoded[29]; // @[pla.scala:81:23] wire decoded_addr_6_2 = decoded_addr_decoded_120; // @[Decode.scala:50:77] wire decoded_addr_decoded_121 = decoded_addr_decoded_decoded[28]; // @[pla.scala:81:23] wire decoded_addr_28_2 = decoded_addr_decoded_121; // @[Decode.scala:50:77] wire decoded_addr_decoded_122 = decoded_addr_decoded_decoded[27]; // @[pla.scala:81:23] wire decoded_addr_25_2 = decoded_addr_decoded_122; // @[Decode.scala:50:77] wire decoded_addr_decoded_123 = decoded_addr_decoded_decoded[26]; // @[pla.scala:81:23] wire decoded_addr_137_2 = decoded_addr_decoded_123; // @[Decode.scala:50:77] wire decoded_addr_decoded_124 = decoded_addr_decoded_decoded[25]; // @[pla.scala:81:23] wire decoded_addr_123_2 = decoded_addr_decoded_124; // @[Decode.scala:50:77] wire decoded_addr_decoded_125 = decoded_addr_decoded_decoded[24]; // @[pla.scala:81:23] wire decoded_addr_23_2 = decoded_addr_decoded_125; // @[Decode.scala:50:77] wire decoded_addr_decoded_126 = decoded_addr_decoded_decoded[23]; // @[pla.scala:81:23] wire decoded_addr_69_2 = decoded_addr_decoded_126; // @[Decode.scala:50:77] wire decoded_addr_decoded_127 = decoded_addr_decoded_decoded[22]; // @[pla.scala:81:23] wire decoded_addr_141_2 = decoded_addr_decoded_127; // @[Decode.scala:50:77] wire decoded_addr_decoded_128 = decoded_addr_decoded_decoded[21]; // @[pla.scala:81:23] wire decoded_addr_9_2 = decoded_addr_decoded_128; // @[Decode.scala:50:77] wire decoded_addr_decoded_129 = decoded_addr_decoded_decoded[20]; // @[pla.scala:81:23] wire decoded_addr_104_2 = decoded_addr_decoded_129; // @[Decode.scala:50:77] wire decoded_addr_decoded_130 = decoded_addr_decoded_decoded[19]; // @[pla.scala:81:23] wire decoded_addr_8_2 = decoded_addr_decoded_130; // @[Decode.scala:50:77] wire decoded_addr_decoded_131 = decoded_addr_decoded_decoded[18]; // @[pla.scala:81:23] wire decoded_addr_125_2 = decoded_addr_decoded_131; // @[Decode.scala:50:77] wire decoded_addr_decoded_132 = decoded_addr_decoded_decoded[17]; // @[pla.scala:81:23] wire decoded_addr_85_2 = decoded_addr_decoded_132; // @[Decode.scala:50:77] wire decoded_addr_decoded_133 = decoded_addr_decoded_decoded[16]; // @[pla.scala:81:23] wire decoded_addr_54_2 = decoded_addr_decoded_133; // @[Decode.scala:50:77] wire decoded_addr_decoded_134 = decoded_addr_decoded_decoded[15]; // @[pla.scala:81:23] wire decoded_addr_20_2 = decoded_addr_decoded_134; // @[Decode.scala:50:77] wire decoded_addr_decoded_135 = decoded_addr_decoded_decoded[14]; // @[pla.scala:81:23] wire decoded_addr_135_2 = decoded_addr_decoded_135; // @[Decode.scala:50:77] wire decoded_addr_decoded_136 = decoded_addr_decoded_decoded[13]; // @[pla.scala:81:23] wire decoded_addr_115_2 = decoded_addr_decoded_136; // @[Decode.scala:50:77] wire decoded_addr_decoded_137 = decoded_addr_decoded_decoded[12]; // @[pla.scala:81:23] wire decoded_addr_43_2 = decoded_addr_decoded_137; // @[Decode.scala:50:77] wire decoded_addr_decoded_138 = decoded_addr_decoded_decoded[11]; // @[pla.scala:81:23] wire decoded_addr_71_2 = decoded_addr_decoded_138; // @[Decode.scala:50:77] wire decoded_addr_decoded_139 = decoded_addr_decoded_decoded[10]; // @[pla.scala:81:23] wire decoded_addr_110_2 = decoded_addr_decoded_139; // @[Decode.scala:50:77] wire decoded_addr_decoded_140 = decoded_addr_decoded_decoded[9]; // @[pla.scala:81:23] wire decoded_addr_140_2 = decoded_addr_decoded_140; // @[Decode.scala:50:77] wire decoded_addr_decoded_141 = decoded_addr_decoded_decoded[8]; // @[pla.scala:81:23] wire decoded_addr_34_2 = decoded_addr_decoded_141; // @[Decode.scala:50:77] wire decoded_addr_decoded_142 = decoded_addr_decoded_decoded[7]; // @[pla.scala:81:23] wire decoded_addr_40_2 = decoded_addr_decoded_142; // @[Decode.scala:50:77] wire decoded_addr_decoded_143 = decoded_addr_decoded_decoded[6]; // @[pla.scala:81:23] wire decoded_addr_80_2 = decoded_addr_decoded_143; // @[Decode.scala:50:77] wire decoded_addr_decoded_144 = decoded_addr_decoded_decoded[5]; // @[pla.scala:81:23] wire decoded_addr_98_2 = decoded_addr_decoded_144; // @[Decode.scala:50:77] wire decoded_addr_decoded_145 = decoded_addr_decoded_decoded[4]; // @[pla.scala:81:23] wire decoded_addr_18_2 = decoded_addr_decoded_145; // @[Decode.scala:50:77] wire decoded_addr_decoded_146 = decoded_addr_decoded_decoded[3]; // @[pla.scala:81:23] wire decoded_addr_3_2 = decoded_addr_decoded_146; // @[Decode.scala:50:77] wire decoded_addr_decoded_147 = decoded_addr_decoded_decoded[2]; // @[pla.scala:81:23] wire decoded_addr_127_2 = decoded_addr_decoded_147; // @[Decode.scala:50:77] wire decoded_addr_decoded_148 = decoded_addr_decoded_decoded[1]; // @[pla.scala:81:23] wire decoded_addr_38_2 = decoded_addr_decoded_148; // @[Decode.scala:50:77] wire decoded_addr_decoded_149 = decoded_addr_decoded_decoded[0]; // @[pla.scala:81:23] wire decoded_addr_95_2 = decoded_addr_decoded_149; // @[Decode.scala:50:77] wire _wdata_T = io_rw_cmd_0[1]; // @[CSR.scala:377:7, :1643:13] wire _new_mip_T_1 = io_rw_cmd_0[1]; // @[CSR.scala:377:7, :1643:13] wire [63:0] _wdata_T_1 = _wdata_T ? io_rw_rdata_0 : 64'h0; // @[CSR.scala:377:7, :1643:{9,13}] wire [63:0] _wdata_T_2 = _wdata_T_1 | io_rw_wdata_0; // @[CSR.scala:377:7, :1643:{9,30}] wire [1:0] _wdata_T_3 = io_rw_cmd_0[1:0]; // @[CSR.scala:377:7, :1643:49] wire [1:0] _new_mip_T_4 = io_rw_cmd_0[1:0]; // @[CSR.scala:377:7, :1643:49] wire _wdata_T_4 = &_wdata_T_3; // @[CSR.scala:1643:{49,55}] wire [63:0] _wdata_T_5 = _wdata_T_4 ? io_rw_wdata_0 : 64'h0; // @[CSR.scala:377:7, :1643:{45,55}] wire [63:0] _wdata_T_6 = ~_wdata_T_5; // @[CSR.scala:1643:{41,45}] assign wdata = _wdata_T_2 & _wdata_T_6; // @[CSR.scala:1643:{30,39,41}] assign io_customCSRs_0_wdata_0 = wdata; // @[CSR.scala:377:7, :1643:39] assign io_customCSRs_1_wdata_0 = wdata; // @[CSR.scala:377:7, :1643:39] wire [63:0] _new_satp_WIRE = wdata; // @[CSR.scala:1355:40, :1643:39] wire [63:0] _new_envcfg_WIRE = wdata; // @[CSR.scala:137:36, :1643:39] wire [63:0] _new_envcfg_WIRE_1 = wdata; // @[CSR.scala:137:36, :1643:39] wire [63:0] _newCfg_T = wdata; // @[CSR.scala:1491:29, :1643:39] wire system_insn = io_rw_cmd_0 == 3'h4; // @[CSR.scala:377:7, :876:31] wire [31:0] _insn_T = {io_rw_addr_0, 20'h0}; // @[CSR.scala:377:7, :892:44] wire [31:0] insn = {_insn_T[31:7], _insn_T[6:0] | 7'h73}; // @[CSR.scala:892:{30,44}] wire [31:0] decoded_plaInput = insn; // @[pla.scala:77:22] wire [31:0] decoded_invInputs = ~decoded_plaInput; // @[pla.scala:77:22, :78:21] wire [8:0] decoded_invMatrixOutputs; // @[pla.scala:120:37] wire [8:0] decoded; // @[pla.scala:81:23] wire decoded_andMatrixOutputs_andMatrixInput_0 = decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_1 = decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_1_1 = decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_2 = decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_2_1 = decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_1_2 = decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_3 = decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_3_1 = decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_2_2 = decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_1_3 = decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_1_5 = decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_4 = decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_4_1 = decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_3_2 = decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_2_3 = decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_2_5 = decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_5 = decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_5_1 = decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_4_2 = decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_3_3 = decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_3_5 = decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_6 = decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_6_1 = decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_5_2 = decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_4_3 = decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_11_2 = decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_4_5 = decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_7 = decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_7_1 = decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_6_2 = decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_5_3 = decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_12 = decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_5_5 = decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_8 = decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_8_1 = decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_9 = decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_9_1 = decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_7_3 = decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_14 = decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_10 = decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_10_1 = decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_8_2 = decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_8_3 = decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_15 = decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_8_5 = decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_11 = decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_11_1 = decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_9_2 = decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_9_3 = decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_16 = decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_9_5 = decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_1_6 = decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire [1:0] decoded_andMatrixOutputs_lo_lo_hi = {decoded_andMatrixOutputs_andMatrixInput_9, decoded_andMatrixOutputs_andMatrixInput_10}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_andMatrixOutputs_lo_lo = {decoded_andMatrixOutputs_lo_lo_hi, decoded_andMatrixOutputs_andMatrixInput_11}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_andMatrixOutputs_lo_hi_hi = {decoded_andMatrixOutputs_andMatrixInput_6, decoded_andMatrixOutputs_andMatrixInput_7}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_andMatrixOutputs_lo_hi = {decoded_andMatrixOutputs_lo_hi_hi, decoded_andMatrixOutputs_andMatrixInput_8}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_andMatrixOutputs_lo = {decoded_andMatrixOutputs_lo_hi, decoded_andMatrixOutputs_lo_lo}; // @[pla.scala:98:53] wire [1:0] decoded_andMatrixOutputs_hi_lo_hi = {decoded_andMatrixOutputs_andMatrixInput_3, decoded_andMatrixOutputs_andMatrixInput_4}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_andMatrixOutputs_hi_lo = {decoded_andMatrixOutputs_hi_lo_hi, decoded_andMatrixOutputs_andMatrixInput_5}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_andMatrixOutputs_hi_hi_hi = {decoded_andMatrixOutputs_andMatrixInput_0, decoded_andMatrixOutputs_andMatrixInput_1}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_andMatrixOutputs_hi_hi = {decoded_andMatrixOutputs_hi_hi_hi, decoded_andMatrixOutputs_andMatrixInput_2}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_andMatrixOutputs_hi = {decoded_andMatrixOutputs_hi_hi, decoded_andMatrixOutputs_hi_lo}; // @[pla.scala:98:53] wire [11:0] _decoded_andMatrixOutputs_T = {decoded_andMatrixOutputs_hi, decoded_andMatrixOutputs_lo}; // @[pla.scala:98:53] wire decoded_andMatrixOutputs_6_2 = &_decoded_andMatrixOutputs_T; // @[pla.scala:98:{53,70}] wire _decoded_orMatrixOutputs_T_6 = decoded_andMatrixOutputs_6_2; // @[pla.scala:98:70, :114:36] wire decoded_andMatrixOutputs_andMatrixInput_0_1 = decoded_plaInput[20]; // @[pla.scala:77:22, :90:45] wire [1:0] decoded_andMatrixOutputs_lo_lo_hi_1 = {decoded_andMatrixOutputs_andMatrixInput_9_1, decoded_andMatrixOutputs_andMatrixInput_10_1}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_andMatrixOutputs_lo_lo_1 = {decoded_andMatrixOutputs_lo_lo_hi_1, decoded_andMatrixOutputs_andMatrixInput_11_1}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_andMatrixOutputs_lo_hi_hi_1 = {decoded_andMatrixOutputs_andMatrixInput_6_1, decoded_andMatrixOutputs_andMatrixInput_7_1}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_andMatrixOutputs_lo_hi_1 = {decoded_andMatrixOutputs_lo_hi_hi_1, decoded_andMatrixOutputs_andMatrixInput_8_1}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_andMatrixOutputs_lo_1 = {decoded_andMatrixOutputs_lo_hi_1, decoded_andMatrixOutputs_lo_lo_1}; // @[pla.scala:98:53] wire [1:0] decoded_andMatrixOutputs_hi_lo_hi_1 = {decoded_andMatrixOutputs_andMatrixInput_3_1, decoded_andMatrixOutputs_andMatrixInput_4_1}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_andMatrixOutputs_hi_lo_1 = {decoded_andMatrixOutputs_hi_lo_hi_1, decoded_andMatrixOutputs_andMatrixInput_5_1}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_andMatrixOutputs_hi_hi_hi_1 = {decoded_andMatrixOutputs_andMatrixInput_0_1, decoded_andMatrixOutputs_andMatrixInput_1_1}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_andMatrixOutputs_hi_hi_1 = {decoded_andMatrixOutputs_hi_hi_hi_1, decoded_andMatrixOutputs_andMatrixInput_2_1}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_andMatrixOutputs_hi_1 = {decoded_andMatrixOutputs_hi_hi_1, decoded_andMatrixOutputs_hi_lo_1}; // @[pla.scala:98:53] wire [11:0] _decoded_andMatrixOutputs_T_1 = {decoded_andMatrixOutputs_hi_1, decoded_andMatrixOutputs_lo_1}; // @[pla.scala:98:53] wire decoded_andMatrixOutputs_4_2 = &_decoded_andMatrixOutputs_T_1; // @[pla.scala:98:{53,70}] wire _decoded_orMatrixOutputs_T_5 = decoded_andMatrixOutputs_4_2; // @[pla.scala:98:70, :114:36] wire decoded_andMatrixOutputs_andMatrixInput_0_2 = decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_andMatrixOutputs_andMatrixInput_0_4 = decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_andMatrixOutputs_andMatrixInput_7_2 = decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire decoded_andMatrixOutputs_andMatrixInput_6_3 = decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire decoded_andMatrixOutputs_andMatrixInput_13 = decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire decoded_andMatrixOutputs_andMatrixInput_6_5 = decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire [1:0] decoded_andMatrixOutputs_lo_lo_2 = {decoded_andMatrixOutputs_andMatrixInput_8_2, decoded_andMatrixOutputs_andMatrixInput_9_2}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_andMatrixOutputs_lo_hi_hi_2 = {decoded_andMatrixOutputs_andMatrixInput_5_2, decoded_andMatrixOutputs_andMatrixInput_6_2}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_andMatrixOutputs_lo_hi_2 = {decoded_andMatrixOutputs_lo_hi_hi_2, decoded_andMatrixOutputs_andMatrixInput_7_2}; // @[pla.scala:90:45, :98:53] wire [4:0] decoded_andMatrixOutputs_lo_2 = {decoded_andMatrixOutputs_lo_hi_2, decoded_andMatrixOutputs_lo_lo_2}; // @[pla.scala:98:53] wire [1:0] decoded_andMatrixOutputs_hi_lo_2 = {decoded_andMatrixOutputs_andMatrixInput_3_2, decoded_andMatrixOutputs_andMatrixInput_4_2}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_andMatrixOutputs_hi_hi_hi_2 = {decoded_andMatrixOutputs_andMatrixInput_0_2, decoded_andMatrixOutputs_andMatrixInput_1_2}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_andMatrixOutputs_hi_hi_2 = {decoded_andMatrixOutputs_hi_hi_hi_2, decoded_andMatrixOutputs_andMatrixInput_2_2}; // @[pla.scala:91:29, :98:53] wire [4:0] decoded_andMatrixOutputs_hi_2 = {decoded_andMatrixOutputs_hi_hi_2, decoded_andMatrixOutputs_hi_lo_2}; // @[pla.scala:98:53] wire [9:0] _decoded_andMatrixOutputs_T_2 = {decoded_andMatrixOutputs_hi_2, decoded_andMatrixOutputs_lo_2}; // @[pla.scala:98:53] wire decoded_andMatrixOutputs_3_2 = &_decoded_andMatrixOutputs_T_2; // @[pla.scala:98:{53,70}] wire decoded_andMatrixOutputs_andMatrixInput_0_3 = decoded_plaInput[22]; // @[pla.scala:77:22, :90:45] wire decoded_andMatrixOutputs_andMatrixInput_0_5 = decoded_plaInput[22]; // @[pla.scala:77:22, :90:45] wire [1:0] decoded_andMatrixOutputs_lo_lo_3 = {decoded_andMatrixOutputs_andMatrixInput_8_3, decoded_andMatrixOutputs_andMatrixInput_9_3}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_andMatrixOutputs_lo_hi_hi_3 = {decoded_andMatrixOutputs_andMatrixInput_5_3, decoded_andMatrixOutputs_andMatrixInput_6_3}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_andMatrixOutputs_lo_hi_3 = {decoded_andMatrixOutputs_lo_hi_hi_3, decoded_andMatrixOutputs_andMatrixInput_7_3}; // @[pla.scala:91:29, :98:53] wire [4:0] decoded_andMatrixOutputs_lo_3 = {decoded_andMatrixOutputs_lo_hi_3, decoded_andMatrixOutputs_lo_lo_3}; // @[pla.scala:98:53] wire [1:0] decoded_andMatrixOutputs_hi_lo_3 = {decoded_andMatrixOutputs_andMatrixInput_3_3, decoded_andMatrixOutputs_andMatrixInput_4_3}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_andMatrixOutputs_hi_hi_hi_3 = {decoded_andMatrixOutputs_andMatrixInput_0_3, decoded_andMatrixOutputs_andMatrixInput_1_3}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_andMatrixOutputs_hi_hi_3 = {decoded_andMatrixOutputs_hi_hi_hi_3, decoded_andMatrixOutputs_andMatrixInput_2_3}; // @[pla.scala:91:29, :98:53] wire [4:0] decoded_andMatrixOutputs_hi_3 = {decoded_andMatrixOutputs_hi_hi_3, decoded_andMatrixOutputs_hi_lo_3}; // @[pla.scala:98:53] wire [9:0] _decoded_andMatrixOutputs_T_3 = {decoded_andMatrixOutputs_hi_3, decoded_andMatrixOutputs_lo_3}; // @[pla.scala:98:53] wire decoded_andMatrixOutputs_1_2 = &_decoded_andMatrixOutputs_T_3; // @[pla.scala:98:{53,70}] wire _decoded_orMatrixOutputs_T_1 = decoded_andMatrixOutputs_1_2; // @[pla.scala:98:70, :114:36] wire decoded_andMatrixOutputs_andMatrixInput_1_4 = decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_andMatrixOutputs_andMatrixInput_2_4 = decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_3_4 = decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_4_4 = decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_andMatrixOutputs_andMatrixInput_5_4 = decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_andMatrixOutputs_andMatrixInput_6_4 = decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire decoded_andMatrixOutputs_andMatrixInput_7_4 = decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_8_4 = decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_9_4 = decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_10_2 = decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire [1:0] decoded_andMatrixOutputs_lo_lo_lo = {decoded_andMatrixOutputs_andMatrixInput_15, decoded_andMatrixOutputs_andMatrixInput_16}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_andMatrixOutputs_lo_lo_hi_2 = {decoded_andMatrixOutputs_andMatrixInput_13, decoded_andMatrixOutputs_andMatrixInput_14}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoded_andMatrixOutputs_lo_lo_4 = {decoded_andMatrixOutputs_lo_lo_hi_2, decoded_andMatrixOutputs_lo_lo_lo}; // @[pla.scala:98:53] wire [1:0] decoded_andMatrixOutputs_lo_hi_lo = {decoded_andMatrixOutputs_andMatrixInput_11_2, decoded_andMatrixOutputs_andMatrixInput_12}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_andMatrixOutputs_lo_hi_hi_4 = {decoded_andMatrixOutputs_andMatrixInput_9_4, decoded_andMatrixOutputs_andMatrixInput_10_2}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoded_andMatrixOutputs_lo_hi_4 = {decoded_andMatrixOutputs_lo_hi_hi_4, decoded_andMatrixOutputs_lo_hi_lo}; // @[pla.scala:98:53] wire [7:0] decoded_andMatrixOutputs_lo_4 = {decoded_andMatrixOutputs_lo_hi_4, decoded_andMatrixOutputs_lo_lo_4}; // @[pla.scala:98:53] wire [1:0] decoded_andMatrixOutputs_hi_lo_lo = {decoded_andMatrixOutputs_andMatrixInput_7_4, decoded_andMatrixOutputs_andMatrixInput_8_4}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_andMatrixOutputs_hi_lo_hi_2 = {decoded_andMatrixOutputs_andMatrixInput_5_4, decoded_andMatrixOutputs_andMatrixInput_6_4}; // @[pla.scala:90:45, :98:53] wire [3:0] decoded_andMatrixOutputs_hi_lo_4 = {decoded_andMatrixOutputs_hi_lo_hi_2, decoded_andMatrixOutputs_hi_lo_lo}; // @[pla.scala:98:53] wire [1:0] decoded_andMatrixOutputs_hi_hi_lo = {decoded_andMatrixOutputs_andMatrixInput_3_4, decoded_andMatrixOutputs_andMatrixInput_4_4}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoded_andMatrixOutputs_hi_hi_hi_hi = {decoded_andMatrixOutputs_andMatrixInput_0_4, decoded_andMatrixOutputs_andMatrixInput_1_4}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_andMatrixOutputs_hi_hi_hi_4 = {decoded_andMatrixOutputs_hi_hi_hi_hi, decoded_andMatrixOutputs_andMatrixInput_2_4}; // @[pla.scala:91:29, :98:53] wire [4:0] decoded_andMatrixOutputs_hi_hi_4 = {decoded_andMatrixOutputs_hi_hi_hi_4, decoded_andMatrixOutputs_hi_hi_lo}; // @[pla.scala:98:53] wire [8:0] decoded_andMatrixOutputs_hi_4 = {decoded_andMatrixOutputs_hi_hi_4, decoded_andMatrixOutputs_hi_lo_4}; // @[pla.scala:98:53] wire [16:0] _decoded_andMatrixOutputs_T_4 = {decoded_andMatrixOutputs_hi_4, decoded_andMatrixOutputs_lo_4}; // @[pla.scala:98:53] wire decoded_andMatrixOutputs_0_2 = &_decoded_andMatrixOutputs_T_4; // @[pla.scala:98:{53,70}] wire _decoded_orMatrixOutputs_T = decoded_andMatrixOutputs_0_2; // @[pla.scala:98:70, :114:36] wire decoded_andMatrixOutputs_andMatrixInput_7_5 = decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire [1:0] decoded_andMatrixOutputs_lo_lo_5 = {decoded_andMatrixOutputs_andMatrixInput_8_5, decoded_andMatrixOutputs_andMatrixInput_9_5}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_andMatrixOutputs_lo_hi_hi_5 = {decoded_andMatrixOutputs_andMatrixInput_5_5, decoded_andMatrixOutputs_andMatrixInput_6_5}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_andMatrixOutputs_lo_hi_5 = {decoded_andMatrixOutputs_lo_hi_hi_5, decoded_andMatrixOutputs_andMatrixInput_7_5}; // @[pla.scala:90:45, :98:53] wire [4:0] decoded_andMatrixOutputs_lo_5 = {decoded_andMatrixOutputs_lo_hi_5, decoded_andMatrixOutputs_lo_lo_5}; // @[pla.scala:98:53] wire [1:0] decoded_andMatrixOutputs_hi_lo_5 = {decoded_andMatrixOutputs_andMatrixInput_3_5, decoded_andMatrixOutputs_andMatrixInput_4_5}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_andMatrixOutputs_hi_hi_hi_5 = {decoded_andMatrixOutputs_andMatrixInput_0_5, decoded_andMatrixOutputs_andMatrixInput_1_5}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_andMatrixOutputs_hi_hi_5 = {decoded_andMatrixOutputs_hi_hi_hi_5, decoded_andMatrixOutputs_andMatrixInput_2_5}; // @[pla.scala:91:29, :98:53] wire [4:0] decoded_andMatrixOutputs_hi_5 = {decoded_andMatrixOutputs_hi_hi_5, decoded_andMatrixOutputs_hi_lo_5}; // @[pla.scala:98:53] wire [9:0] _decoded_andMatrixOutputs_T_5 = {decoded_andMatrixOutputs_hi_5, decoded_andMatrixOutputs_lo_5}; // @[pla.scala:98:53] wire decoded_andMatrixOutputs_5_2 = &_decoded_andMatrixOutputs_T_5; // @[pla.scala:98:{53,70}] wire _decoded_orMatrixOutputs_T_2 = decoded_andMatrixOutputs_5_2; // @[pla.scala:98:70, :114:36] wire decoded_andMatrixOutputs_andMatrixInput_0_6 = decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire [1:0] _decoded_andMatrixOutputs_T_6 = {decoded_andMatrixOutputs_andMatrixInput_0_6, decoded_andMatrixOutputs_andMatrixInput_1_6}; // @[pla.scala:90:45, :91:29, :98:53] wire decoded_andMatrixOutputs_2_2 = &_decoded_andMatrixOutputs_T_6; // @[pla.scala:98:{53,70}] wire [1:0] _decoded_orMatrixOutputs_T_3 = {decoded_andMatrixOutputs_3_2, decoded_andMatrixOutputs_2_2}; // @[pla.scala:98:70, :114:19] wire _decoded_orMatrixOutputs_T_4 = |_decoded_orMatrixOutputs_T_3; // @[pla.scala:114:{19,36}] wire [1:0] decoded_orMatrixOutputs_lo_hi = {_decoded_orMatrixOutputs_T, 1'h0}; // @[pla.scala:102:36, :114:36] wire [3:0] decoded_orMatrixOutputs_lo = {decoded_orMatrixOutputs_lo_hi, 2'h0}; // @[pla.scala:102:36] wire [1:0] decoded_orMatrixOutputs_hi_lo = {_decoded_orMatrixOutputs_T_2, _decoded_orMatrixOutputs_T_1}; // @[pla.scala:102:36, :114:36] wire [1:0] decoded_orMatrixOutputs_hi_hi_hi = {_decoded_orMatrixOutputs_T_6, _decoded_orMatrixOutputs_T_5}; // @[pla.scala:102:36, :114:36] wire [2:0] decoded_orMatrixOutputs_hi_hi = {decoded_orMatrixOutputs_hi_hi_hi, _decoded_orMatrixOutputs_T_4}; // @[pla.scala:102:36, :114:36] wire [4:0] decoded_orMatrixOutputs_hi = {decoded_orMatrixOutputs_hi_hi, decoded_orMatrixOutputs_hi_lo}; // @[pla.scala:102:36] wire [8:0] decoded_orMatrixOutputs = {decoded_orMatrixOutputs_hi, decoded_orMatrixOutputs_lo}; // @[pla.scala:102:36] wire _decoded_invMatrixOutputs_T = decoded_orMatrixOutputs[0]; // @[pla.scala:102:36, :124:31] wire _decoded_invMatrixOutputs_T_1 = decoded_orMatrixOutputs[1]; // @[pla.scala:102:36, :124:31] wire _decoded_invMatrixOutputs_T_2 = decoded_orMatrixOutputs[2]; // @[pla.scala:102:36, :124:31] wire _decoded_invMatrixOutputs_T_3 = decoded_orMatrixOutputs[3]; // @[pla.scala:102:36, :124:31] wire _decoded_invMatrixOutputs_T_4 = decoded_orMatrixOutputs[4]; // @[pla.scala:102:36, :124:31] wire _decoded_invMatrixOutputs_T_5 = decoded_orMatrixOutputs[5]; // @[pla.scala:102:36, :124:31] wire _decoded_invMatrixOutputs_T_6 = decoded_orMatrixOutputs[6]; // @[pla.scala:102:36, :124:31] wire _decoded_invMatrixOutputs_T_7 = decoded_orMatrixOutputs[7]; // @[pla.scala:102:36, :124:31] wire _decoded_invMatrixOutputs_T_8 = decoded_orMatrixOutputs[8]; // @[pla.scala:102:36, :124:31] wire [1:0] decoded_invMatrixOutputs_lo_lo = {_decoded_invMatrixOutputs_T_1, _decoded_invMatrixOutputs_T}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_invMatrixOutputs_lo_hi = {_decoded_invMatrixOutputs_T_3, _decoded_invMatrixOutputs_T_2}; // @[pla.scala:120:37, :124:31] wire [3:0] decoded_invMatrixOutputs_lo = {decoded_invMatrixOutputs_lo_hi, decoded_invMatrixOutputs_lo_lo}; // @[pla.scala:120:37] wire [1:0] decoded_invMatrixOutputs_hi_lo = {_decoded_invMatrixOutputs_T_5, _decoded_invMatrixOutputs_T_4}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_invMatrixOutputs_hi_hi_hi = {_decoded_invMatrixOutputs_T_8, _decoded_invMatrixOutputs_T_7}; // @[pla.scala:120:37, :124:31] wire [2:0] decoded_invMatrixOutputs_hi_hi = {decoded_invMatrixOutputs_hi_hi_hi, _decoded_invMatrixOutputs_T_6}; // @[pla.scala:120:37, :124:31] wire [4:0] decoded_invMatrixOutputs_hi = {decoded_invMatrixOutputs_hi_hi, decoded_invMatrixOutputs_hi_lo}; // @[pla.scala:120:37] assign decoded_invMatrixOutputs = {decoded_invMatrixOutputs_hi, decoded_invMatrixOutputs_lo}; // @[pla.scala:120:37] assign decoded = decoded_invMatrixOutputs; // @[pla.scala:81:23, :120:37] wire insn_call = system_insn & decoded[8]; // @[pla.scala:81:23] wire insn_break = system_insn & decoded[7]; // @[pla.scala:81:23] wire insn_ret = system_insn & decoded[6]; // @[pla.scala:81:23] wire insn_cease = system_insn & decoded[5]; // @[pla.scala:81:23] wire insn_wfi = system_insn & decoded[4]; // @[pla.scala:81:23] wire [11:0] addr = io_decode_0_inst_0[31:20]; // @[CSR.scala:377:7, :897:27] wire [11:0] io_decode_0_fp_csr_plaInput = addr; // @[pla.scala:77:22] wire [11:0] io_decode_0_vector_csr_plaInput = addr; // @[pla.scala:77:22] wire [11:0] io_decode_0_read_illegal_plaInput = addr; // @[pla.scala:77:22] wire [11:0] io_decode_0_read_illegal_plaInput_1 = addr; // @[pla.scala:77:22] wire [31:0] decoded_invInputs_1 = ~decoded_plaInput_1; // @[pla.scala:77:22, :78:21] wire [8:0] decoded_invMatrixOutputs_1; // @[pla.scala:120:37] wire [8:0] decoded_1; // @[pla.scala:81:23] wire decoded_andMatrixOutputs_andMatrixInput_0_7 = decoded_invInputs_1[20]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_1_7 = decoded_invInputs_1[21]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_1_8 = decoded_invInputs_1[21]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_2_6 = decoded_invInputs_1[22]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_2_7 = decoded_invInputs_1[22]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_1_9 = decoded_invInputs_1[22]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_3_6 = decoded_invInputs_1[23]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_3_7 = decoded_invInputs_1[23]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_2_8 = decoded_invInputs_1[23]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_1_10 = decoded_invInputs_1[23]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_1_12 = decoded_invInputs_1[23]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_4_6 = decoded_invInputs_1[24]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_4_7 = decoded_invInputs_1[24]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_3_8 = decoded_invInputs_1[24]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_2_9 = decoded_invInputs_1[24]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_2_11 = decoded_invInputs_1[24]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_5_6 = decoded_invInputs_1[25]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_5_7 = decoded_invInputs_1[25]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_4_8 = decoded_invInputs_1[25]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_3_9 = decoded_invInputs_1[25]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_3_11 = decoded_invInputs_1[25]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_6_6 = decoded_invInputs_1[26]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_6_7 = decoded_invInputs_1[26]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_5_8 = decoded_invInputs_1[26]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_4_9 = decoded_invInputs_1[26]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_11_5 = decoded_invInputs_1[26]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_4_11 = decoded_invInputs_1[26]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_7_6 = decoded_invInputs_1[27]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_7_7 = decoded_invInputs_1[27]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_6_8 = decoded_invInputs_1[27]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_5_9 = decoded_invInputs_1[27]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_12_1 = decoded_invInputs_1[27]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_5_11 = decoded_invInputs_1[27]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_8_6 = decoded_invInputs_1[28]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_8_7 = decoded_invInputs_1[28]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_9_6 = decoded_invInputs_1[29]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_9_7 = decoded_invInputs_1[29]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_7_9 = decoded_invInputs_1[29]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_14_1 = decoded_invInputs_1[29]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_10_3 = decoded_invInputs_1[30]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_10_4 = decoded_invInputs_1[30]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_8_8 = decoded_invInputs_1[30]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_8_9 = decoded_invInputs_1[30]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_15_1 = decoded_invInputs_1[30]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_8_11 = decoded_invInputs_1[30]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_11_3 = decoded_invInputs_1[31]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_11_4 = decoded_invInputs_1[31]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_9_8 = decoded_invInputs_1[31]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_9_9 = decoded_invInputs_1[31]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_16_1 = decoded_invInputs_1[31]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_9_11 = decoded_invInputs_1[31]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_1_13 = decoded_invInputs_1[31]; // @[pla.scala:78:21, :91:29] wire [1:0] decoded_andMatrixOutputs_lo_lo_hi_3 = {decoded_andMatrixOutputs_andMatrixInput_9_6, decoded_andMatrixOutputs_andMatrixInput_10_3}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_andMatrixOutputs_lo_lo_6 = {decoded_andMatrixOutputs_lo_lo_hi_3, decoded_andMatrixOutputs_andMatrixInput_11_3}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_andMatrixOutputs_lo_hi_hi_6 = {decoded_andMatrixOutputs_andMatrixInput_6_6, decoded_andMatrixOutputs_andMatrixInput_7_6}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_andMatrixOutputs_lo_hi_6 = {decoded_andMatrixOutputs_lo_hi_hi_6, decoded_andMatrixOutputs_andMatrixInput_8_6}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_andMatrixOutputs_lo_6 = {decoded_andMatrixOutputs_lo_hi_6, decoded_andMatrixOutputs_lo_lo_6}; // @[pla.scala:98:53] wire [1:0] decoded_andMatrixOutputs_hi_lo_hi_3 = {decoded_andMatrixOutputs_andMatrixInput_3_6, decoded_andMatrixOutputs_andMatrixInput_4_6}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_andMatrixOutputs_hi_lo_6 = {decoded_andMatrixOutputs_hi_lo_hi_3, decoded_andMatrixOutputs_andMatrixInput_5_6}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_andMatrixOutputs_hi_hi_hi_6 = {decoded_andMatrixOutputs_andMatrixInput_0_7, decoded_andMatrixOutputs_andMatrixInput_1_7}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_andMatrixOutputs_hi_hi_6 = {decoded_andMatrixOutputs_hi_hi_hi_6, decoded_andMatrixOutputs_andMatrixInput_2_6}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_andMatrixOutputs_hi_6 = {decoded_andMatrixOutputs_hi_hi_6, decoded_andMatrixOutputs_hi_lo_6}; // @[pla.scala:98:53] wire [11:0] _decoded_andMatrixOutputs_T_7 = {decoded_andMatrixOutputs_hi_6, decoded_andMatrixOutputs_lo_6}; // @[pla.scala:98:53] wire decoded_andMatrixOutputs_6_2_1 = &_decoded_andMatrixOutputs_T_7; // @[pla.scala:98:{53,70}] wire _decoded_orMatrixOutputs_T_13 = decoded_andMatrixOutputs_6_2_1; // @[pla.scala:98:70, :114:36] wire decoded_andMatrixOutputs_andMatrixInput_0_8 = decoded_plaInput_1[20]; // @[pla.scala:77:22, :90:45] wire [1:0] decoded_andMatrixOutputs_lo_lo_hi_4 = {decoded_andMatrixOutputs_andMatrixInput_9_7, decoded_andMatrixOutputs_andMatrixInput_10_4}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_andMatrixOutputs_lo_lo_7 = {decoded_andMatrixOutputs_lo_lo_hi_4, decoded_andMatrixOutputs_andMatrixInput_11_4}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_andMatrixOutputs_lo_hi_hi_7 = {decoded_andMatrixOutputs_andMatrixInput_6_7, decoded_andMatrixOutputs_andMatrixInput_7_7}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_andMatrixOutputs_lo_hi_7 = {decoded_andMatrixOutputs_lo_hi_hi_7, decoded_andMatrixOutputs_andMatrixInput_8_7}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_andMatrixOutputs_lo_7 = {decoded_andMatrixOutputs_lo_hi_7, decoded_andMatrixOutputs_lo_lo_7}; // @[pla.scala:98:53] wire [1:0] decoded_andMatrixOutputs_hi_lo_hi_4 = {decoded_andMatrixOutputs_andMatrixInput_3_7, decoded_andMatrixOutputs_andMatrixInput_4_7}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_andMatrixOutputs_hi_lo_7 = {decoded_andMatrixOutputs_hi_lo_hi_4, decoded_andMatrixOutputs_andMatrixInput_5_7}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_andMatrixOutputs_hi_hi_hi_7 = {decoded_andMatrixOutputs_andMatrixInput_0_8, decoded_andMatrixOutputs_andMatrixInput_1_8}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_andMatrixOutputs_hi_hi_7 = {decoded_andMatrixOutputs_hi_hi_hi_7, decoded_andMatrixOutputs_andMatrixInput_2_7}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_andMatrixOutputs_hi_7 = {decoded_andMatrixOutputs_hi_hi_7, decoded_andMatrixOutputs_hi_lo_7}; // @[pla.scala:98:53] wire [11:0] _decoded_andMatrixOutputs_T_8 = {decoded_andMatrixOutputs_hi_7, decoded_andMatrixOutputs_lo_7}; // @[pla.scala:98:53] wire decoded_andMatrixOutputs_4_2_1 = &_decoded_andMatrixOutputs_T_8; // @[pla.scala:98:{53,70}] wire _decoded_orMatrixOutputs_T_12 = decoded_andMatrixOutputs_4_2_1; // @[pla.scala:98:70, :114:36] wire decoded_andMatrixOutputs_andMatrixInput_0_9 = decoded_plaInput_1[0]; // @[pla.scala:77:22, :90:45] wire decoded_andMatrixOutputs_andMatrixInput_0_11 = decoded_plaInput_1[0]; // @[pla.scala:77:22, :90:45] wire decoded_andMatrixOutputs_andMatrixInput_7_8 = decoded_plaInput_1[28]; // @[pla.scala:77:22, :90:45] wire decoded_andMatrixOutputs_andMatrixInput_6_9 = decoded_plaInput_1[28]; // @[pla.scala:77:22, :90:45] wire decoded_andMatrixOutputs_andMatrixInput_13_1 = decoded_plaInput_1[28]; // @[pla.scala:77:22, :90:45] wire decoded_andMatrixOutputs_andMatrixInput_6_11 = decoded_plaInput_1[28]; // @[pla.scala:77:22, :90:45] wire [1:0] decoded_andMatrixOutputs_lo_lo_8 = {decoded_andMatrixOutputs_andMatrixInput_8_8, decoded_andMatrixOutputs_andMatrixInput_9_8}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_andMatrixOutputs_lo_hi_hi_8 = {decoded_andMatrixOutputs_andMatrixInput_5_8, decoded_andMatrixOutputs_andMatrixInput_6_8}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_andMatrixOutputs_lo_hi_8 = {decoded_andMatrixOutputs_lo_hi_hi_8, decoded_andMatrixOutputs_andMatrixInput_7_8}; // @[pla.scala:90:45, :98:53] wire [4:0] decoded_andMatrixOutputs_lo_8 = {decoded_andMatrixOutputs_lo_hi_8, decoded_andMatrixOutputs_lo_lo_8}; // @[pla.scala:98:53] wire [1:0] decoded_andMatrixOutputs_hi_lo_8 = {decoded_andMatrixOutputs_andMatrixInput_3_8, decoded_andMatrixOutputs_andMatrixInput_4_8}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_andMatrixOutputs_hi_hi_hi_8 = {decoded_andMatrixOutputs_andMatrixInput_0_9, decoded_andMatrixOutputs_andMatrixInput_1_9}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_andMatrixOutputs_hi_hi_8 = {decoded_andMatrixOutputs_hi_hi_hi_8, decoded_andMatrixOutputs_andMatrixInput_2_8}; // @[pla.scala:91:29, :98:53] wire [4:0] decoded_andMatrixOutputs_hi_8 = {decoded_andMatrixOutputs_hi_hi_8, decoded_andMatrixOutputs_hi_lo_8}; // @[pla.scala:98:53] wire [9:0] _decoded_andMatrixOutputs_T_9 = {decoded_andMatrixOutputs_hi_8, decoded_andMatrixOutputs_lo_8}; // @[pla.scala:98:53] wire decoded_andMatrixOutputs_3_2_1 = &_decoded_andMatrixOutputs_T_9; // @[pla.scala:98:{53,70}] wire decoded_andMatrixOutputs_andMatrixInput_0_10 = decoded_plaInput_1[22]; // @[pla.scala:77:22, :90:45] wire decoded_andMatrixOutputs_andMatrixInput_0_12 = decoded_plaInput_1[22]; // @[pla.scala:77:22, :90:45] wire [1:0] decoded_andMatrixOutputs_lo_lo_9 = {decoded_andMatrixOutputs_andMatrixInput_8_9, decoded_andMatrixOutputs_andMatrixInput_9_9}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_andMatrixOutputs_lo_hi_hi_9 = {decoded_andMatrixOutputs_andMatrixInput_5_9, decoded_andMatrixOutputs_andMatrixInput_6_9}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_andMatrixOutputs_lo_hi_9 = {decoded_andMatrixOutputs_lo_hi_hi_9, decoded_andMatrixOutputs_andMatrixInput_7_9}; // @[pla.scala:91:29, :98:53] wire [4:0] decoded_andMatrixOutputs_lo_9 = {decoded_andMatrixOutputs_lo_hi_9, decoded_andMatrixOutputs_lo_lo_9}; // @[pla.scala:98:53] wire [1:0] decoded_andMatrixOutputs_hi_lo_9 = {decoded_andMatrixOutputs_andMatrixInput_3_9, decoded_andMatrixOutputs_andMatrixInput_4_9}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_andMatrixOutputs_hi_hi_hi_9 = {decoded_andMatrixOutputs_andMatrixInput_0_10, decoded_andMatrixOutputs_andMatrixInput_1_10}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_andMatrixOutputs_hi_hi_9 = {decoded_andMatrixOutputs_hi_hi_hi_9, decoded_andMatrixOutputs_andMatrixInput_2_9}; // @[pla.scala:91:29, :98:53] wire [4:0] decoded_andMatrixOutputs_hi_9 = {decoded_andMatrixOutputs_hi_hi_9, decoded_andMatrixOutputs_hi_lo_9}; // @[pla.scala:98:53] wire [9:0] _decoded_andMatrixOutputs_T_10 = {decoded_andMatrixOutputs_hi_9, decoded_andMatrixOutputs_lo_9}; // @[pla.scala:98:53] wire decoded_andMatrixOutputs_1_2_1 = &_decoded_andMatrixOutputs_T_10; // @[pla.scala:98:{53,70}] wire _decoded_orMatrixOutputs_T_8 = decoded_andMatrixOutputs_1_2_1; // @[pla.scala:98:70, :114:36] wire decoded_andMatrixOutputs_andMatrixInput_1_11 = decoded_plaInput_1[1]; // @[pla.scala:77:22, :90:45] wire decoded_andMatrixOutputs_andMatrixInput_2_10 = decoded_invInputs_1[2]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_3_10 = decoded_invInputs_1[3]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_4_10 = decoded_plaInput_1[4]; // @[pla.scala:77:22, :90:45] wire decoded_andMatrixOutputs_andMatrixInput_5_10 = decoded_plaInput_1[5]; // @[pla.scala:77:22, :90:45] wire decoded_andMatrixOutputs_andMatrixInput_6_10 = decoded_plaInput_1[6]; // @[pla.scala:77:22, :90:45] wire decoded_andMatrixOutputs_andMatrixInput_7_10 = decoded_invInputs_1[7]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_8_10 = decoded_invInputs_1[8]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_9_10 = decoded_invInputs_1[9]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_10_5 = decoded_plaInput_1[25]; // @[pla.scala:77:22, :90:45] wire [1:0] decoded_andMatrixOutputs_lo_lo_lo_1 = {decoded_andMatrixOutputs_andMatrixInput_15_1, decoded_andMatrixOutputs_andMatrixInput_16_1}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_andMatrixOutputs_lo_lo_hi_5 = {decoded_andMatrixOutputs_andMatrixInput_13_1, decoded_andMatrixOutputs_andMatrixInput_14_1}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoded_andMatrixOutputs_lo_lo_10 = {decoded_andMatrixOutputs_lo_lo_hi_5, decoded_andMatrixOutputs_lo_lo_lo_1}; // @[pla.scala:98:53] wire [1:0] decoded_andMatrixOutputs_lo_hi_lo_1 = {decoded_andMatrixOutputs_andMatrixInput_11_5, decoded_andMatrixOutputs_andMatrixInput_12_1}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_andMatrixOutputs_lo_hi_hi_10 = {decoded_andMatrixOutputs_andMatrixInput_9_10, decoded_andMatrixOutputs_andMatrixInput_10_5}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoded_andMatrixOutputs_lo_hi_10 = {decoded_andMatrixOutputs_lo_hi_hi_10, decoded_andMatrixOutputs_lo_hi_lo_1}; // @[pla.scala:98:53] wire [7:0] decoded_andMatrixOutputs_lo_10 = {decoded_andMatrixOutputs_lo_hi_10, decoded_andMatrixOutputs_lo_lo_10}; // @[pla.scala:98:53] wire [1:0] decoded_andMatrixOutputs_hi_lo_lo_1 = {decoded_andMatrixOutputs_andMatrixInput_7_10, decoded_andMatrixOutputs_andMatrixInput_8_10}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_andMatrixOutputs_hi_lo_hi_5 = {decoded_andMatrixOutputs_andMatrixInput_5_10, decoded_andMatrixOutputs_andMatrixInput_6_10}; // @[pla.scala:90:45, :98:53] wire [3:0] decoded_andMatrixOutputs_hi_lo_10 = {decoded_andMatrixOutputs_hi_lo_hi_5, decoded_andMatrixOutputs_hi_lo_lo_1}; // @[pla.scala:98:53] wire [1:0] decoded_andMatrixOutputs_hi_hi_lo_1 = {decoded_andMatrixOutputs_andMatrixInput_3_10, decoded_andMatrixOutputs_andMatrixInput_4_10}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoded_andMatrixOutputs_hi_hi_hi_hi_1 = {decoded_andMatrixOutputs_andMatrixInput_0_11, decoded_andMatrixOutputs_andMatrixInput_1_11}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_andMatrixOutputs_hi_hi_hi_10 = {decoded_andMatrixOutputs_hi_hi_hi_hi_1, decoded_andMatrixOutputs_andMatrixInput_2_10}; // @[pla.scala:91:29, :98:53] wire [4:0] decoded_andMatrixOutputs_hi_hi_10 = {decoded_andMatrixOutputs_hi_hi_hi_10, decoded_andMatrixOutputs_hi_hi_lo_1}; // @[pla.scala:98:53] wire [8:0] decoded_andMatrixOutputs_hi_10 = {decoded_andMatrixOutputs_hi_hi_10, decoded_andMatrixOutputs_hi_lo_10}; // @[pla.scala:98:53] wire [16:0] _decoded_andMatrixOutputs_T_11 = {decoded_andMatrixOutputs_hi_10, decoded_andMatrixOutputs_lo_10}; // @[pla.scala:98:53] wire decoded_andMatrixOutputs_0_2_1 = &_decoded_andMatrixOutputs_T_11; // @[pla.scala:98:{53,70}] wire _decoded_orMatrixOutputs_T_7 = decoded_andMatrixOutputs_0_2_1; // @[pla.scala:98:70, :114:36] wire decoded_andMatrixOutputs_andMatrixInput_7_11 = decoded_plaInput_1[29]; // @[pla.scala:77:22, :90:45] wire [1:0] decoded_andMatrixOutputs_lo_lo_11 = {decoded_andMatrixOutputs_andMatrixInput_8_11, decoded_andMatrixOutputs_andMatrixInput_9_11}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_andMatrixOutputs_lo_hi_hi_11 = {decoded_andMatrixOutputs_andMatrixInput_5_11, decoded_andMatrixOutputs_andMatrixInput_6_11}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_andMatrixOutputs_lo_hi_11 = {decoded_andMatrixOutputs_lo_hi_hi_11, decoded_andMatrixOutputs_andMatrixInput_7_11}; // @[pla.scala:90:45, :98:53] wire [4:0] decoded_andMatrixOutputs_lo_11 = {decoded_andMatrixOutputs_lo_hi_11, decoded_andMatrixOutputs_lo_lo_11}; // @[pla.scala:98:53] wire [1:0] decoded_andMatrixOutputs_hi_lo_11 = {decoded_andMatrixOutputs_andMatrixInput_3_11, decoded_andMatrixOutputs_andMatrixInput_4_11}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_andMatrixOutputs_hi_hi_hi_11 = {decoded_andMatrixOutputs_andMatrixInput_0_12, decoded_andMatrixOutputs_andMatrixInput_1_12}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_andMatrixOutputs_hi_hi_11 = {decoded_andMatrixOutputs_hi_hi_hi_11, decoded_andMatrixOutputs_andMatrixInput_2_11}; // @[pla.scala:91:29, :98:53] wire [4:0] decoded_andMatrixOutputs_hi_11 = {decoded_andMatrixOutputs_hi_hi_11, decoded_andMatrixOutputs_hi_lo_11}; // @[pla.scala:98:53] wire [9:0] _decoded_andMatrixOutputs_T_12 = {decoded_andMatrixOutputs_hi_11, decoded_andMatrixOutputs_lo_11}; // @[pla.scala:98:53] wire decoded_andMatrixOutputs_5_2_1 = &_decoded_andMatrixOutputs_T_12; // @[pla.scala:98:{53,70}] wire _decoded_orMatrixOutputs_T_9 = decoded_andMatrixOutputs_5_2_1; // @[pla.scala:98:70, :114:36] wire decoded_andMatrixOutputs_andMatrixInput_0_13 = decoded_plaInput_1[30]; // @[pla.scala:77:22, :90:45] wire [1:0] _decoded_andMatrixOutputs_T_13 = {decoded_andMatrixOutputs_andMatrixInput_0_13, decoded_andMatrixOutputs_andMatrixInput_1_13}; // @[pla.scala:90:45, :91:29, :98:53] wire decoded_andMatrixOutputs_2_2_1 = &_decoded_andMatrixOutputs_T_13; // @[pla.scala:98:{53,70}] wire [1:0] _decoded_orMatrixOutputs_T_10 = {decoded_andMatrixOutputs_3_2_1, decoded_andMatrixOutputs_2_2_1}; // @[pla.scala:98:70, :114:19] wire _decoded_orMatrixOutputs_T_11 = |_decoded_orMatrixOutputs_T_10; // @[pla.scala:114:{19,36}] wire [1:0] decoded_orMatrixOutputs_lo_hi_1 = {_decoded_orMatrixOutputs_T_7, 1'h0}; // @[pla.scala:102:36, :114:36] wire [3:0] decoded_orMatrixOutputs_lo_1 = {decoded_orMatrixOutputs_lo_hi_1, 2'h0}; // @[pla.scala:102:36] wire [1:0] decoded_orMatrixOutputs_hi_lo_1 = {_decoded_orMatrixOutputs_T_9, _decoded_orMatrixOutputs_T_8}; // @[pla.scala:102:36, :114:36] wire [1:0] decoded_orMatrixOutputs_hi_hi_hi_1 = {_decoded_orMatrixOutputs_T_13, _decoded_orMatrixOutputs_T_12}; // @[pla.scala:102:36, :114:36] wire [2:0] decoded_orMatrixOutputs_hi_hi_1 = {decoded_orMatrixOutputs_hi_hi_hi_1, _decoded_orMatrixOutputs_T_11}; // @[pla.scala:102:36, :114:36] wire [4:0] decoded_orMatrixOutputs_hi_1 = {decoded_orMatrixOutputs_hi_hi_1, decoded_orMatrixOutputs_hi_lo_1}; // @[pla.scala:102:36] wire [8:0] decoded_orMatrixOutputs_1 = {decoded_orMatrixOutputs_hi_1, decoded_orMatrixOutputs_lo_1}; // @[pla.scala:102:36] wire _decoded_invMatrixOutputs_T_9 = decoded_orMatrixOutputs_1[0]; // @[pla.scala:102:36, :124:31] wire _decoded_invMatrixOutputs_T_10 = decoded_orMatrixOutputs_1[1]; // @[pla.scala:102:36, :124:31] wire _decoded_invMatrixOutputs_T_11 = decoded_orMatrixOutputs_1[2]; // @[pla.scala:102:36, :124:31] wire _decoded_invMatrixOutputs_T_12 = decoded_orMatrixOutputs_1[3]; // @[pla.scala:102:36, :124:31] wire _decoded_invMatrixOutputs_T_13 = decoded_orMatrixOutputs_1[4]; // @[pla.scala:102:36, :124:31] wire _decoded_invMatrixOutputs_T_14 = decoded_orMatrixOutputs_1[5]; // @[pla.scala:102:36, :124:31] wire _decoded_invMatrixOutputs_T_15 = decoded_orMatrixOutputs_1[6]; // @[pla.scala:102:36, :124:31] wire _decoded_invMatrixOutputs_T_16 = decoded_orMatrixOutputs_1[7]; // @[pla.scala:102:36, :124:31] wire _decoded_invMatrixOutputs_T_17 = decoded_orMatrixOutputs_1[8]; // @[pla.scala:102:36, :124:31] wire [1:0] decoded_invMatrixOutputs_lo_lo_1 = {_decoded_invMatrixOutputs_T_10, _decoded_invMatrixOutputs_T_9}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_invMatrixOutputs_lo_hi_1 = {_decoded_invMatrixOutputs_T_12, _decoded_invMatrixOutputs_T_11}; // @[pla.scala:120:37, :124:31] wire [3:0] decoded_invMatrixOutputs_lo_1 = {decoded_invMatrixOutputs_lo_hi_1, decoded_invMatrixOutputs_lo_lo_1}; // @[pla.scala:120:37] wire [1:0] decoded_invMatrixOutputs_hi_lo_1 = {_decoded_invMatrixOutputs_T_14, _decoded_invMatrixOutputs_T_13}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_invMatrixOutputs_hi_hi_hi_1 = {_decoded_invMatrixOutputs_T_17, _decoded_invMatrixOutputs_T_16}; // @[pla.scala:120:37, :124:31] wire [2:0] decoded_invMatrixOutputs_hi_hi_1 = {decoded_invMatrixOutputs_hi_hi_hi_1, _decoded_invMatrixOutputs_T_15}; // @[pla.scala:120:37, :124:31] wire [4:0] decoded_invMatrixOutputs_hi_1 = {decoded_invMatrixOutputs_hi_hi_1, decoded_invMatrixOutputs_hi_lo_1}; // @[pla.scala:120:37] assign decoded_invMatrixOutputs_1 = {decoded_invMatrixOutputs_hi_1, decoded_invMatrixOutputs_lo_1}; // @[pla.scala:120:37] assign decoded_1 = decoded_invMatrixOutputs_1; // @[pla.scala:81:23, :120:37] wire is_break = decoded_1[7]; // @[pla.scala:81:23] wire is_ret = decoded_1[6]; // @[pla.scala:81:23] wire is_wfi = decoded_1[4]; // @[pla.scala:81:23] wire is_sfence = decoded_1[3]; // @[pla.scala:81:23] wire is_hfence_vvma = decoded_1[2]; // @[pla.scala:81:23] wire is_hfence_gvma = decoded_1[1]; // @[pla.scala:81:23] wire is_hlsv = decoded_1[0]; // @[pla.scala:81:23] wire _is_counter_T = addr > 12'hBFF; // @[package.scala:213:47] wire _is_counter_T_1 = addr < 12'hC20; // @[package.scala:213:60] wire _is_counter_T_2 = _is_counter_T & _is_counter_T_1; // @[package.scala:213:{47,55,60}] wire _is_counter_T_3 = addr > 12'hC7F; // @[package.scala:213:47] wire _is_counter_T_4 = addr < 12'hCA0; // @[package.scala:213:60] wire _is_counter_T_5 = _is_counter_T_3 & _is_counter_T_4; // @[package.scala:213:{47,55,60}] wire is_counter = _is_counter_T_2 | _is_counter_T_5; // @[package.scala:213:55] wire _allow_wfi_T_1 = _allow_wfi_T; // @[CSR.scala:906:{42,61}] wire _allow_wfi_T_2 = ~reg_mstatus_tw; // @[CSR.scala:395:28, :906:74] wire _allow_wfi_T_6 = _allow_wfi_T_2; // @[CSR.scala:906:{74,90}] wire _allow_wfi_T_3 = ~reg_mstatus_v; // @[CSR.scala:395:28, :906:94] wire allow_wfi = _allow_wfi_T_1 | _allow_wfi_T_6; // @[CSR.scala:906:{42,71,90}] wire _allow_sfence_vma_T_1 = _allow_sfence_vma_T; // @[CSR.scala:907:{41,60}] wire _allow_sfence_vma_T_2 = ~reg_mstatus_v & reg_mstatus_tvm; // @[CSR.scala:395:28, :907:77] wire _allow_sfence_vma_T_3 = ~_allow_sfence_vma_T_2; // @[CSR.scala:907:{73,77}] wire allow_sfence_vma = _allow_sfence_vma_T_1 | _allow_sfence_vma_T_3; // @[CSR.scala:907:{41,70,73}] wire _allow_hfence_vvma_T = ~reg_mstatus_v; // @[CSR.scala:395:28, :906:94, :908:53] wire _allow_hfence_vvma_T_1 = |reg_mstatus_prv; // @[CSR.scala:395:28, :908:88] wire _allow_hfence_vvma_T_2 = _allow_hfence_vvma_T & _allow_hfence_vvma_T_1; // @[CSR.scala:908:{53,68,88}] wire _allow_hlsv_T = ~reg_mstatus_v; // @[CSR.scala:395:28, :906:94, :909:46] wire _allow_hlsv_T_1 = |reg_mstatus_prv; // @[CSR.scala:395:28, :908:88, :909:81] wire _allow_hlsv_T_2 = _allow_hlsv_T_1; // @[CSR.scala:909:{81,92}] wire _allow_hlsv_T_3 = _allow_hlsv_T & _allow_hlsv_T_2; // @[CSR.scala:909:{46,61,92}] wire _allow_sret_T_1 = _allow_sret_T; // @[CSR.scala:910:{43,62}] wire _allow_sret_T_2 = ~reg_mstatus_v & reg_mstatus_tsr; // @[CSR.scala:395:28, :907:77, :910:79] wire _allow_sret_T_3 = ~_allow_sret_T_2; // @[CSR.scala:910:{75,79}] wire allow_sret = _allow_sret_T_1 | _allow_sret_T_3; // @[CSR.scala:910:{43,72,75}] wire [4:0] counter_addr = addr[4:0]; // @[CSR.scala:897:27, :911:28] wire [31:0] _GEN_4 = {27'h0, counter_addr}; // @[CSR.scala:911:28, :912:70] wire [31:0] _GEN_5 = read_mcounteren >> _GEN_4; // @[CSR.scala:532:14, :912:70] wire [31:0] _allow_counter_T_1; // @[CSR.scala:912:70] assign _allow_counter_T_1 = _GEN_5; // @[CSR.scala:912:70] wire [31:0] _io_decode_0_virtual_access_illegal_T_3; // @[CSR.scala:945:36] assign _io_decode_0_virtual_access_illegal_T_3 = _GEN_5; // @[CSR.scala:912:70, :945:36] wire _allow_counter_T_2 = _allow_counter_T_1[0]; // @[CSR.scala:912:70] wire _allow_counter_T_3 = _allow_counter_T | _allow_counter_T_2; // @[CSR.scala:912:{42,52,70}] wire _allow_counter_T_5 = |reg_mstatus_prv; // @[CSR.scala:395:28, :908:88, :913:46] wire _allow_counter_T_6 = _allow_counter_T_5; // @[CSR.scala:913:{27,46}] wire [31:0] _GEN_6 = read_scounteren >> _GEN_4; // @[CSR.scala:536:14, :912:70, :913:75] wire [31:0] _allow_counter_T_7; // @[CSR.scala:913:75] assign _allow_counter_T_7 = _GEN_6; // @[CSR.scala:913:75] wire [31:0] _io_decode_0_virtual_access_illegal_T_11; // @[CSR.scala:945:128] assign _io_decode_0_virtual_access_illegal_T_11 = _GEN_6; // @[CSR.scala:913:75, :945:128] wire _allow_counter_T_8 = _allow_counter_T_7[0]; // @[CSR.scala:913:75] wire _allow_counter_T_9 = _allow_counter_T_6 | _allow_counter_T_8; // @[CSR.scala:913:{27,57,75}] wire _allow_counter_T_10 = _allow_counter_T_3 & _allow_counter_T_9; // @[CSR.scala:912:{52,86}, :913:57] wire allow_counter = _allow_counter_T_10; // @[CSR.scala:912:86, :913:91] wire _allow_counter_T_12 = ~reg_mstatus_v; // @[CSR.scala:395:28, :906:94, :914:30] wire [31:0] _GEN_7 = 32'h0 >> _GEN_4; // @[CSR.scala:912:70, :914:63] wire [31:0] _allow_counter_T_14; // @[CSR.scala:914:63] assign _allow_counter_T_14 = _GEN_7; // @[CSR.scala:914:63] wire [31:0] _io_decode_0_virtual_access_illegal_T_6; // @[CSR.scala:945:71] assign _io_decode_0_virtual_access_illegal_T_6 = _GEN_7; // @[CSR.scala:914:63, :945:71] wire _allow_counter_T_15 = _allow_counter_T_14[0]; // @[CSR.scala:914:63] wire _io_decode_0_fp_illegal_T = io_status_fs_0 == 2'h0; // @[CSR.scala:377:7, :915:39] wire _io_decode_0_fp_illegal_T_3 = _io_decode_0_fp_illegal_T; // @[CSR.scala:915:{39,47}] assign _io_decode_0_fp_illegal_T_6 = _io_decode_0_fp_illegal_T_3; // @[CSR.scala:915:{47,91}] assign io_decode_0_fp_illegal_0 = _io_decode_0_fp_illegal_T_6; // @[CSR.scala:377:7, :915:91] wire _io_decode_0_vector_illegal_T_2 = reg_mstatus_v & _io_decode_0_vector_illegal_T_1; // @[CSR.scala:395:28, :916:{68,87}] wire [11:0] io_decode_0_fp_csr_invInputs = ~io_decode_0_fp_csr_plaInput; // @[pla.scala:77:22, :78:21] wire io_decode_0_fp_csr_invMatrixOutputs; // @[pla.scala:124:31] wire io_decode_0_fp_csr_plaOutput; // @[pla.scala:81:23] assign _io_decode_0_fp_csr_T = io_decode_0_fp_csr_plaOutput; // @[pla.scala:81:23] wire io_decode_0_fp_csr_andMatrixOutputs_andMatrixInput_0 = io_decode_0_fp_csr_invInputs[8]; // @[pla.scala:78:21, :91:29] wire io_decode_0_fp_csr_andMatrixOutputs_andMatrixInput_1 = io_decode_0_fp_csr_invInputs[9]; // @[pla.scala:78:21, :91:29] wire io_decode_0_fp_csr_andMatrixOutputs_andMatrixInput_2 = io_decode_0_fp_csr_invInputs[10]; // @[pla.scala:78:21, :91:29] wire io_decode_0_fp_csr_andMatrixOutputs_andMatrixInput_3 = io_decode_0_fp_csr_invInputs[11]; // @[pla.scala:78:21, :91:29] wire [1:0] io_decode_0_fp_csr_andMatrixOutputs_lo = {io_decode_0_fp_csr_andMatrixOutputs_andMatrixInput_2, io_decode_0_fp_csr_andMatrixOutputs_andMatrixInput_3}; // @[pla.scala:91:29, :98:53] wire [1:0] io_decode_0_fp_csr_andMatrixOutputs_hi = {io_decode_0_fp_csr_andMatrixOutputs_andMatrixInput_0, io_decode_0_fp_csr_andMatrixOutputs_andMatrixInput_1}; // @[pla.scala:91:29, :98:53] wire [3:0] _io_decode_0_fp_csr_andMatrixOutputs_T = {io_decode_0_fp_csr_andMatrixOutputs_hi, io_decode_0_fp_csr_andMatrixOutputs_lo}; // @[pla.scala:98:53] wire io_decode_0_fp_csr_andMatrixOutputs_0_2 = &_io_decode_0_fp_csr_andMatrixOutputs_T; // @[pla.scala:98:{53,70}] wire io_decode_0_fp_csr_orMatrixOutputs = io_decode_0_fp_csr_andMatrixOutputs_0_2; // @[pla.scala:98:70, :114:36] assign io_decode_0_fp_csr_invMatrixOutputs = io_decode_0_fp_csr_orMatrixOutputs; // @[pla.scala:114:36, :124:31] assign io_decode_0_fp_csr_plaOutput = io_decode_0_fp_csr_invMatrixOutputs; // @[pla.scala:81:23, :124:31] assign io_decode_0_fp_csr_0 = _io_decode_0_fp_csr_T; // @[Decode.scala:55:116] wire [11:0] io_decode_0_vector_csr_invInputs = ~io_decode_0_vector_csr_plaInput; // @[pla.scala:77:22, :78:21] wire [1:0] _csr_addr_legal_T = addr[9:8]; // @[CSR.scala:190:36, :897:27] wire [1:0] _csr_addr_legal_T_6 = addr[9:8]; // @[CSR.scala:190:36, :897:27] wire [1:0] _io_decode_0_virtual_access_illegal_T_1 = addr[9:8]; // @[CSR.scala:190:36, :897:27] wire [1:0] _io_decode_0_virtual_access_illegal_T_18 = addr[9:8]; // @[CSR.scala:190:36, :897:27] wire [1:0] _io_decode_0_virtual_system_illegal_T_9 = addr[9:8]; // @[CSR.scala:190:36, :897:27] wire _csr_addr_legal_T_1 = reg_mstatus_prv >= _csr_addr_legal_T; // @[CSR.scala:190:36, :395:28, :920:42] wire csr_addr_legal = _csr_addr_legal_T_1; // @[CSR.scala:920:{42,60}] wire _csr_addr_legal_T_2 = ~reg_mstatus_v; // @[CSR.scala:395:28, :906:94, :921:28] wire _csr_addr_legal_T_7 = _csr_addr_legal_T_6 == 2'h2; // @[CSR.scala:190:36, :921:92] wire _csr_exists_T = addr == 12'h7A0; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_1 = addr == 12'h7A1; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_2 = addr == 12'h7A2; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_3 = addr == 12'h7A3; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_4 = addr == 12'h301; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_5 = addr == 12'h300; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_6 = addr == 12'h305; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_7 = addr == 12'h344; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_8 = addr == 12'h304; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_9 = addr == 12'h340; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_10 = addr == 12'h341; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_11 = addr == 12'h343; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_12 = addr == 12'h342; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_13 = addr == 12'hF14; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_14 = addr == 12'h7B0; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_15 = addr == 12'h7B1; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_16 = addr == 12'h7B2; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_17 = addr == 12'h1; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_18 = addr == 12'h2; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_19 = addr == 12'h3; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_20 = addr == 12'h320; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_21 = addr == 12'hB00; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_22 = addr == 12'hB02; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_23 = addr == 12'h323; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_24 = addr == 12'hB03; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_25 = addr == 12'hC03; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_26 = addr == 12'h324; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_27 = addr == 12'hB04; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_28 = addr == 12'hC04; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_29 = addr == 12'h325; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_30 = addr == 12'hB05; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_31 = addr == 12'hC05; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_32 = addr == 12'h326; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_33 = addr == 12'hB06; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_34 = addr == 12'hC06; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_35 = addr == 12'h327; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_36 = addr == 12'hB07; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_37 = addr == 12'hC07; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_38 = addr == 12'h328; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_39 = addr == 12'hB08; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_40 = addr == 12'hC08; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_41 = addr == 12'h329; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_42 = addr == 12'hB09; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_43 = addr == 12'hC09; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_44 = addr == 12'h32A; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_45 = addr == 12'hB0A; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_46 = addr == 12'hC0A; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_47 = addr == 12'h32B; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_48 = addr == 12'hB0B; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_49 = addr == 12'hC0B; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_50 = addr == 12'h32C; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_51 = addr == 12'hB0C; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_52 = addr == 12'hC0C; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_53 = addr == 12'h32D; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_54 = addr == 12'hB0D; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_55 = addr == 12'hC0D; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_56 = addr == 12'h32E; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_57 = addr == 12'hB0E; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_58 = addr == 12'hC0E; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_59 = addr == 12'h32F; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_60 = addr == 12'hB0F; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_61 = addr == 12'hC0F; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_62 = addr == 12'h330; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_63 = addr == 12'hB10; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_64 = addr == 12'hC10; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_65 = addr == 12'h331; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_66 = addr == 12'hB11; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_67 = addr == 12'hC11; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_68 = addr == 12'h332; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_69 = addr == 12'hB12; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_70 = addr == 12'hC12; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_71 = addr == 12'h333; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_72 = addr == 12'hB13; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_73 = addr == 12'hC13; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_74 = addr == 12'h334; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_75 = addr == 12'hB14; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_76 = addr == 12'hC14; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_77 = addr == 12'h335; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_78 = addr == 12'hB15; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_79 = addr == 12'hC15; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_80 = addr == 12'h336; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_81 = addr == 12'hB16; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_82 = addr == 12'hC16; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_83 = addr == 12'h337; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_84 = addr == 12'hB17; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_85 = addr == 12'hC17; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_86 = addr == 12'h338; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_87 = addr == 12'hB18; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_88 = addr == 12'hC18; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_89 = addr == 12'h339; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_90 = addr == 12'hB19; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_91 = addr == 12'hC19; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_92 = addr == 12'h33A; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_93 = addr == 12'hB1A; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_94 = addr == 12'hC1A; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_95 = addr == 12'h33B; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_96 = addr == 12'hB1B; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_97 = addr == 12'hC1B; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_98 = addr == 12'h33C; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_99 = addr == 12'hB1C; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_100 = addr == 12'hC1C; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_101 = addr == 12'h33D; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_102 = addr == 12'hB1D; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_103 = addr == 12'hC1D; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_104 = addr == 12'h33E; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_105 = addr == 12'hB1E; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_106 = addr == 12'hC1E; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_107 = addr == 12'h33F; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_108 = addr == 12'hB1F; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_109 = addr == 12'hC1F; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_110 = addr == 12'h306; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_111 = addr == 12'hC00; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_112 = addr == 12'hC02; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_113 = addr == 12'h30A; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_114 = addr == 12'h100; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_115 = addr == 12'h144; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_116 = addr == 12'h104; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_117 = addr == 12'h140; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_118 = addr == 12'h142; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_119 = addr == 12'h143; // @[CSR.scala:897:27, :899:93] wire _GEN_8 = addr == 12'h180; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_120; // @[CSR.scala:899:93] assign _csr_exists_T_120 = _GEN_8; // @[CSR.scala:899:93] wire _io_decode_0_read_illegal_T_3; // @[CSR.scala:925:14] assign _io_decode_0_read_illegal_T_3 = _GEN_8; // @[CSR.scala:899:93, :925:14] wire _io_decode_0_virtual_access_illegal_T_24; // @[CSR.scala:947:12] assign _io_decode_0_virtual_access_illegal_T_24 = _GEN_8; // @[CSR.scala:899:93, :947:12] wire _csr_exists_T_121 = addr == 12'h141; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_122 = addr == 12'h105; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_123 = addr == 12'h106; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_124 = addr == 12'h303; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_125 = addr == 12'h302; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_126 = addr == 12'h10A; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_127 = addr == 12'h3A0; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_128 = addr == 12'h3A2; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_129 = addr == 12'h3B0; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_130 = addr == 12'h3B1; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_131 = addr == 12'h3B2; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_132 = addr == 12'h3B3; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_133 = addr == 12'h3B4; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_134 = addr == 12'h3B5; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_135 = addr == 12'h3B6; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_136 = addr == 12'h3B7; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_137 = addr == 12'h3B8; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_138 = addr == 12'h3B9; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_139 = addr == 12'h3BA; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_140 = addr == 12'h3BB; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_141 = addr == 12'h3BC; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_142 = addr == 12'h3BD; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_143 = addr == 12'h3BE; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_144 = addr == 12'h3BF; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_145 = addr == 12'h7C1; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_146 = addr == 12'hF12; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_147 = addr == 12'hF13; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_148 = addr == 12'hF11; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_149 = addr == 12'hF15; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_150 = _csr_exists_T | _csr_exists_T_1; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_151 = _csr_exists_T_150 | _csr_exists_T_2; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_152 = _csr_exists_T_151 | _csr_exists_T_3; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_153 = _csr_exists_T_152 | _csr_exists_T_4; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_154 = _csr_exists_T_153 | _csr_exists_T_5; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_155 = _csr_exists_T_154 | _csr_exists_T_6; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_156 = _csr_exists_T_155 | _csr_exists_T_7; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_157 = _csr_exists_T_156 | _csr_exists_T_8; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_158 = _csr_exists_T_157 | _csr_exists_T_9; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_159 = _csr_exists_T_158 | _csr_exists_T_10; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_160 = _csr_exists_T_159 | _csr_exists_T_11; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_161 = _csr_exists_T_160 | _csr_exists_T_12; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_162 = _csr_exists_T_161 | _csr_exists_T_13; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_163 = _csr_exists_T_162 | _csr_exists_T_14; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_164 = _csr_exists_T_163 | _csr_exists_T_15; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_165 = _csr_exists_T_164 | _csr_exists_T_16; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_166 = _csr_exists_T_165 | _csr_exists_T_17; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_167 = _csr_exists_T_166 | _csr_exists_T_18; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_168 = _csr_exists_T_167 | _csr_exists_T_19; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_169 = _csr_exists_T_168 | _csr_exists_T_20; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_170 = _csr_exists_T_169 | _csr_exists_T_21; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_171 = _csr_exists_T_170 | _csr_exists_T_22; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_172 = _csr_exists_T_171 | _csr_exists_T_23; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_173 = _csr_exists_T_172 | _csr_exists_T_24; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_174 = _csr_exists_T_173 | _csr_exists_T_25; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_175 = _csr_exists_T_174 | _csr_exists_T_26; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_176 = _csr_exists_T_175 | _csr_exists_T_27; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_177 = _csr_exists_T_176 | _csr_exists_T_28; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_178 = _csr_exists_T_177 | _csr_exists_T_29; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_179 = _csr_exists_T_178 | _csr_exists_T_30; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_180 = _csr_exists_T_179 | _csr_exists_T_31; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_181 = _csr_exists_T_180 | _csr_exists_T_32; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_182 = _csr_exists_T_181 | _csr_exists_T_33; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_183 = _csr_exists_T_182 | _csr_exists_T_34; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_184 = _csr_exists_T_183 | _csr_exists_T_35; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_185 = _csr_exists_T_184 | _csr_exists_T_36; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_186 = _csr_exists_T_185 | _csr_exists_T_37; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_187 = _csr_exists_T_186 | _csr_exists_T_38; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_188 = _csr_exists_T_187 | _csr_exists_T_39; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_189 = _csr_exists_T_188 | _csr_exists_T_40; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_190 = _csr_exists_T_189 | _csr_exists_T_41; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_191 = _csr_exists_T_190 | _csr_exists_T_42; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_192 = _csr_exists_T_191 | _csr_exists_T_43; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_193 = _csr_exists_T_192 | _csr_exists_T_44; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_194 = _csr_exists_T_193 | _csr_exists_T_45; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_195 = _csr_exists_T_194 | _csr_exists_T_46; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_196 = _csr_exists_T_195 | _csr_exists_T_47; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_197 = _csr_exists_T_196 | _csr_exists_T_48; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_198 = _csr_exists_T_197 | _csr_exists_T_49; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_199 = _csr_exists_T_198 | _csr_exists_T_50; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_200 = _csr_exists_T_199 | _csr_exists_T_51; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_201 = _csr_exists_T_200 | _csr_exists_T_52; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_202 = _csr_exists_T_201 | _csr_exists_T_53; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_203 = _csr_exists_T_202 | _csr_exists_T_54; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_204 = _csr_exists_T_203 | _csr_exists_T_55; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_205 = _csr_exists_T_204 | _csr_exists_T_56; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_206 = _csr_exists_T_205 | _csr_exists_T_57; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_207 = _csr_exists_T_206 | _csr_exists_T_58; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_208 = _csr_exists_T_207 | _csr_exists_T_59; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_209 = _csr_exists_T_208 | _csr_exists_T_60; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_210 = _csr_exists_T_209 | _csr_exists_T_61; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_211 = _csr_exists_T_210 | _csr_exists_T_62; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_212 = _csr_exists_T_211 | _csr_exists_T_63; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_213 = _csr_exists_T_212 | _csr_exists_T_64; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_214 = _csr_exists_T_213 | _csr_exists_T_65; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_215 = _csr_exists_T_214 | _csr_exists_T_66; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_216 = _csr_exists_T_215 | _csr_exists_T_67; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_217 = _csr_exists_T_216 | _csr_exists_T_68; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_218 = _csr_exists_T_217 | _csr_exists_T_69; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_219 = _csr_exists_T_218 | _csr_exists_T_70; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_220 = _csr_exists_T_219 | _csr_exists_T_71; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_221 = _csr_exists_T_220 | _csr_exists_T_72; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_222 = _csr_exists_T_221 | _csr_exists_T_73; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_223 = _csr_exists_T_222 | _csr_exists_T_74; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_224 = _csr_exists_T_223 | _csr_exists_T_75; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_225 = _csr_exists_T_224 | _csr_exists_T_76; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_226 = _csr_exists_T_225 | _csr_exists_T_77; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_227 = _csr_exists_T_226 | _csr_exists_T_78; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_228 = _csr_exists_T_227 | _csr_exists_T_79; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_229 = _csr_exists_T_228 | _csr_exists_T_80; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_230 = _csr_exists_T_229 | _csr_exists_T_81; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_231 = _csr_exists_T_230 | _csr_exists_T_82; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_232 = _csr_exists_T_231 | _csr_exists_T_83; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_233 = _csr_exists_T_232 | _csr_exists_T_84; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_234 = _csr_exists_T_233 | _csr_exists_T_85; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_235 = _csr_exists_T_234 | _csr_exists_T_86; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_236 = _csr_exists_T_235 | _csr_exists_T_87; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_237 = _csr_exists_T_236 | _csr_exists_T_88; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_238 = _csr_exists_T_237 | _csr_exists_T_89; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_239 = _csr_exists_T_238 | _csr_exists_T_90; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_240 = _csr_exists_T_239 | _csr_exists_T_91; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_241 = _csr_exists_T_240 | _csr_exists_T_92; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_242 = _csr_exists_T_241 | _csr_exists_T_93; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_243 = _csr_exists_T_242 | _csr_exists_T_94; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_244 = _csr_exists_T_243 | _csr_exists_T_95; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_245 = _csr_exists_T_244 | _csr_exists_T_96; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_246 = _csr_exists_T_245 | _csr_exists_T_97; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_247 = _csr_exists_T_246 | _csr_exists_T_98; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_248 = _csr_exists_T_247 | _csr_exists_T_99; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_249 = _csr_exists_T_248 | _csr_exists_T_100; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_250 = _csr_exists_T_249 | _csr_exists_T_101; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_251 = _csr_exists_T_250 | _csr_exists_T_102; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_252 = _csr_exists_T_251 | _csr_exists_T_103; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_253 = _csr_exists_T_252 | _csr_exists_T_104; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_254 = _csr_exists_T_253 | _csr_exists_T_105; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_255 = _csr_exists_T_254 | _csr_exists_T_106; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_256 = _csr_exists_T_255 | _csr_exists_T_107; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_257 = _csr_exists_T_256 | _csr_exists_T_108; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_258 = _csr_exists_T_257 | _csr_exists_T_109; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_259 = _csr_exists_T_258 | _csr_exists_T_110; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_260 = _csr_exists_T_259 | _csr_exists_T_111; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_261 = _csr_exists_T_260 | _csr_exists_T_112; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_262 = _csr_exists_T_261 | _csr_exists_T_113; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_263 = _csr_exists_T_262 | _csr_exists_T_114; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_264 = _csr_exists_T_263 | _csr_exists_T_115; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_265 = _csr_exists_T_264 | _csr_exists_T_116; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_266 = _csr_exists_T_265 | _csr_exists_T_117; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_267 = _csr_exists_T_266 | _csr_exists_T_118; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_268 = _csr_exists_T_267 | _csr_exists_T_119; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_269 = _csr_exists_T_268 | _csr_exists_T_120; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_270 = _csr_exists_T_269 | _csr_exists_T_121; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_271 = _csr_exists_T_270 | _csr_exists_T_122; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_272 = _csr_exists_T_271 | _csr_exists_T_123; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_273 = _csr_exists_T_272 | _csr_exists_T_124; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_274 = _csr_exists_T_273 | _csr_exists_T_125; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_275 = _csr_exists_T_274 | _csr_exists_T_126; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_276 = _csr_exists_T_275 | _csr_exists_T_127; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_277 = _csr_exists_T_276 | _csr_exists_T_128; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_278 = _csr_exists_T_277 | _csr_exists_T_129; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_279 = _csr_exists_T_278 | _csr_exists_T_130; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_280 = _csr_exists_T_279 | _csr_exists_T_131; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_281 = _csr_exists_T_280 | _csr_exists_T_132; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_282 = _csr_exists_T_281 | _csr_exists_T_133; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_283 = _csr_exists_T_282 | _csr_exists_T_134; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_284 = _csr_exists_T_283 | _csr_exists_T_135; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_285 = _csr_exists_T_284 | _csr_exists_T_136; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_286 = _csr_exists_T_285 | _csr_exists_T_137; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_287 = _csr_exists_T_286 | _csr_exists_T_138; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_288 = _csr_exists_T_287 | _csr_exists_T_139; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_289 = _csr_exists_T_288 | _csr_exists_T_140; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_290 = _csr_exists_T_289 | _csr_exists_T_141; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_291 = _csr_exists_T_290 | _csr_exists_T_142; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_292 = _csr_exists_T_291 | _csr_exists_T_143; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_293 = _csr_exists_T_292 | _csr_exists_T_144; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_294 = _csr_exists_T_293 | _csr_exists_T_145; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_295 = _csr_exists_T_294 | _csr_exists_T_146; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_296 = _csr_exists_T_295 | _csr_exists_T_147; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_297 = _csr_exists_T_296 | _csr_exists_T_148; // @[CSR.scala:899:{93,111}] wire csr_exists = _csr_exists_T_297 | _csr_exists_T_149; // @[CSR.scala:899:{93,111}] wire _io_decode_0_read_illegal_T = ~csr_addr_legal; // @[CSR.scala:920:60, :923:28] wire _io_decode_0_read_illegal_T_1 = ~csr_exists; // @[CSR.scala:899:111, :924:7] wire _io_decode_0_read_illegal_T_2 = _io_decode_0_read_illegal_T | _io_decode_0_read_illegal_T_1; // @[CSR.scala:923:{28,44}, :924:7] wire _io_decode_0_read_illegal_T_4 = addr == 12'h680; // @[CSR.scala:897:27, :925:38] wire _io_decode_0_read_illegal_T_5 = _io_decode_0_read_illegal_T_3 | _io_decode_0_read_illegal_T_4; // @[CSR.scala:925:{14,30,38}] wire _io_decode_0_read_illegal_T_6 = ~allow_sfence_vma; // @[CSR.scala:907:70, :925:59] wire _io_decode_0_read_illegal_T_7 = _io_decode_0_read_illegal_T_5 & _io_decode_0_read_illegal_T_6; // @[CSR.scala:925:{30,56,59}] wire _io_decode_0_read_illegal_T_8 = _io_decode_0_read_illegal_T_2 | _io_decode_0_read_illegal_T_7; // @[CSR.scala:923:44, :924:19, :925:56] wire _io_decode_0_read_illegal_T_9 = ~allow_counter; // @[CSR.scala:913:91, :926:21] wire _io_decode_0_read_illegal_T_10 = is_counter & _io_decode_0_read_illegal_T_9; // @[CSR.scala:904:81, :926:{18,21}] wire _io_decode_0_read_illegal_T_11 = _io_decode_0_read_illegal_T_8 | _io_decode_0_read_illegal_T_10; // @[CSR.scala:924:19, :925:78, :926:18] wire [11:0] io_decode_0_read_illegal_invInputs = ~io_decode_0_read_illegal_plaInput; // @[pla.scala:77:22, :78:21] wire io_decode_0_read_illegal_invMatrixOutputs; // @[pla.scala:124:31] wire io_decode_0_read_illegal_plaOutput; // @[pla.scala:81:23] wire _io_decode_0_read_illegal_T_12 = io_decode_0_read_illegal_plaOutput; // @[pla.scala:81:23] wire io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_0 = io_decode_0_read_illegal_plaInput[4]; // @[pla.scala:77:22, :90:45] wire io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_1 = io_decode_0_read_illegal_plaInput[5]; // @[pla.scala:77:22, :90:45] wire io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_2 = io_decode_0_read_illegal_invInputs[6]; // @[pla.scala:78:21, :91:29] wire io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_3 = io_decode_0_read_illegal_plaInput[7]; // @[pla.scala:77:22, :90:45] wire io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_4 = io_decode_0_read_illegal_plaInput[8]; // @[pla.scala:77:22, :90:45] wire io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_5 = io_decode_0_read_illegal_plaInput[9]; // @[pla.scala:77:22, :90:45] wire io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_6 = io_decode_0_read_illegal_plaInput[10]; // @[pla.scala:77:22, :90:45] wire io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_7 = io_decode_0_read_illegal_invInputs[11]; // @[pla.scala:78:21, :91:29] wire [1:0] io_decode_0_read_illegal_andMatrixOutputs_lo_lo = {io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_6, io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_7}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] io_decode_0_read_illegal_andMatrixOutputs_lo_hi = {io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_4, io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_5}; // @[pla.scala:90:45, :98:53] wire [3:0] io_decode_0_read_illegal_andMatrixOutputs_lo = {io_decode_0_read_illegal_andMatrixOutputs_lo_hi, io_decode_0_read_illegal_andMatrixOutputs_lo_lo}; // @[pla.scala:98:53] wire [1:0] io_decode_0_read_illegal_andMatrixOutputs_hi_lo = {io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_2, io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_3}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] io_decode_0_read_illegal_andMatrixOutputs_hi_hi = {io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_0, io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_1}; // @[pla.scala:90:45, :98:53] wire [3:0] io_decode_0_read_illegal_andMatrixOutputs_hi = {io_decode_0_read_illegal_andMatrixOutputs_hi_hi, io_decode_0_read_illegal_andMatrixOutputs_hi_lo}; // @[pla.scala:98:53] wire [7:0] _io_decode_0_read_illegal_andMatrixOutputs_T = {io_decode_0_read_illegal_andMatrixOutputs_hi, io_decode_0_read_illegal_andMatrixOutputs_lo}; // @[pla.scala:98:53] wire io_decode_0_read_illegal_andMatrixOutputs_0_2 = &_io_decode_0_read_illegal_andMatrixOutputs_T; // @[pla.scala:98:{53,70}] wire io_decode_0_read_illegal_orMatrixOutputs = io_decode_0_read_illegal_andMatrixOutputs_0_2; // @[pla.scala:98:70, :114:36] assign io_decode_0_read_illegal_invMatrixOutputs = io_decode_0_read_illegal_orMatrixOutputs; // @[pla.scala:114:36, :124:31] assign io_decode_0_read_illegal_plaOutput = io_decode_0_read_illegal_invMatrixOutputs; // @[pla.scala:81:23, :124:31] wire _io_decode_0_read_illegal_T_13 = ~reg_debug; // @[CSR.scala:482:26, :927:45] wire _io_decode_0_read_illegal_T_14 = _io_decode_0_read_illegal_T_12 & _io_decode_0_read_illegal_T_13; // @[Decode.scala:55:116] wire _io_decode_0_read_illegal_T_15 = _io_decode_0_read_illegal_T_11 | _io_decode_0_read_illegal_T_14; // @[CSR.scala:925:78, :926:36, :927:42] wire _io_decode_0_read_illegal_T_18 = _io_decode_0_read_illegal_T_15; // @[CSR.scala:926:36, :927:56] wire [11:0] io_decode_0_read_illegal_invInputs_1 = ~io_decode_0_read_illegal_plaInput_1; // @[pla.scala:77:22, :78:21] wire _io_decode_0_read_illegal_T_19 = io_decode_0_fp_csr_0 & io_decode_0_fp_illegal_0; // @[CSR.scala:377:7, :929:21] assign _io_decode_0_read_illegal_T_20 = _io_decode_0_read_illegal_T_18 | _io_decode_0_read_illegal_T_19; // @[CSR.scala:927:56, :928:68, :929:21] assign io_decode_0_read_illegal_0 = _io_decode_0_read_illegal_T_20; // @[CSR.scala:377:7, :928:68] wire [1:0] _io_decode_0_write_illegal_T = addr[11:10]; // @[CSR.scala:897:27, :930:33] assign _io_decode_0_write_illegal_T_1 = &_io_decode_0_write_illegal_T; // @[CSR.scala:930:{33,41}] assign io_decode_0_write_illegal_0 = _io_decode_0_write_illegal_T_1; // @[CSR.scala:377:7, :930:41] wire [11:0] io_decode_0_write_flush_addr_m = {_io_decode_0_write_illegal_T, addr[9:0] | 10'h300}; // @[CSR.scala:897:27, :930:33, :932:25] wire _io_decode_0_write_flush_T = io_decode_0_write_flush_addr_m > 12'h33F; // @[CSR.scala:932:25, :933:16] wire _io_decode_0_write_flush_T_1 = io_decode_0_write_flush_addr_m < 12'h344; // @[CSR.scala:932:25, :933:45] wire _io_decode_0_write_flush_T_2 = _io_decode_0_write_flush_T & _io_decode_0_write_flush_T_1; // @[CSR.scala:933:{16,35,45}] assign _io_decode_0_write_flush_T_3 = ~_io_decode_0_write_flush_T_2; // @[CSR.scala:933:{7,35}] assign io_decode_0_write_flush_0 = _io_decode_0_write_flush_T_3; // @[CSR.scala:377:7, :933:7] wire _io_decode_0_system_illegal_T = ~csr_addr_legal; // @[CSR.scala:920:60, :923:28, :935:30] wire _io_decode_0_system_illegal_T_1 = ~is_hlsv; // @[CSR.scala:903:82, :935:49] wire _io_decode_0_system_illegal_T_2 = _io_decode_0_system_illegal_T & _io_decode_0_system_illegal_T_1; // @[CSR.scala:935:{30,46,49}] wire _io_decode_0_system_illegal_T_3 = ~allow_wfi; // @[CSR.scala:906:71, :936:17] wire _io_decode_0_system_illegal_T_4 = is_wfi & _io_decode_0_system_illegal_T_3; // @[CSR.scala:903:82, :936:{14,17}] wire _io_decode_0_system_illegal_T_5 = _io_decode_0_system_illegal_T_2 | _io_decode_0_system_illegal_T_4; // @[CSR.scala:935:{46,58}, :936:14] wire _io_decode_0_system_illegal_T_6 = ~allow_sret; // @[CSR.scala:910:72, :937:17] wire _io_decode_0_system_illegal_T_7 = is_ret & _io_decode_0_system_illegal_T_6; // @[CSR.scala:903:82, :937:{14,17}] wire _io_decode_0_system_illegal_T_8 = _io_decode_0_system_illegal_T_5 | _io_decode_0_system_illegal_T_7; // @[CSR.scala:935:58, :936:28, :937:14] wire _io_decode_0_system_illegal_T_9 = addr[10]; // @[CSR.scala:897:27, :938:21] wire _io_decode_0_system_illegal_T_10 = is_ret & _io_decode_0_system_illegal_T_9; // @[CSR.scala:903:82, :938:{14,21}] wire _io_decode_0_system_illegal_T_11 = addr[7]; // @[CSR.scala:897:27, :938:33] wire _io_decode_0_system_illegal_T_12 = _io_decode_0_system_illegal_T_10 & _io_decode_0_system_illegal_T_11; // @[CSR.scala:938:{14,26,33}] wire _io_decode_0_system_illegal_T_13 = ~reg_debug; // @[CSR.scala:482:26, :927:45, :938:40] wire _io_decode_0_system_illegal_T_14 = _io_decode_0_system_illegal_T_12 & _io_decode_0_system_illegal_T_13; // @[CSR.scala:938:{26,37,40}] wire _io_decode_0_system_illegal_T_15 = _io_decode_0_system_illegal_T_8 | _io_decode_0_system_illegal_T_14; // @[CSR.scala:936:28, :937:29, :938:37] wire _io_decode_0_system_illegal_T_16 = is_sfence | is_hfence_gvma; // @[CSR.scala:903:82, :939:18] wire _io_decode_0_system_illegal_T_17 = ~allow_sfence_vma; // @[CSR.scala:907:70, :925:59, :939:40] wire _io_decode_0_system_illegal_T_18 = _io_decode_0_system_illegal_T_16 & _io_decode_0_system_illegal_T_17; // @[CSR.scala:939:{18,37,40}] wire _io_decode_0_system_illegal_T_19 = _io_decode_0_system_illegal_T_15 | _io_decode_0_system_illegal_T_18; // @[CSR.scala:937:29, :938:51, :939:37] wire _io_decode_0_system_illegal_T_22 = _io_decode_0_system_illegal_T_19; // @[CSR.scala:938:51, :939:58] assign _io_decode_0_system_illegal_T_25 = _io_decode_0_system_illegal_T_22; // @[CSR.scala:939:58, :940:44] assign io_decode_0_system_illegal_0 = _io_decode_0_system_illegal_T_25; // @[CSR.scala:377:7, :940:44] wire _io_decode_0_virtual_access_illegal_T = reg_mstatus_v & csr_exists; // @[CSR.scala:395:28, :899:111, :943:52] wire _io_decode_0_virtual_access_illegal_T_2 = _io_decode_0_virtual_access_illegal_T_1 == 2'h2; // @[CSR.scala:190:36, :944:22] wire _io_decode_0_virtual_access_illegal_T_4 = _io_decode_0_virtual_access_illegal_T_3[0]; // @[CSR.scala:945:36] wire _io_decode_0_virtual_access_illegal_T_5 = is_counter & _io_decode_0_virtual_access_illegal_T_4; // @[CSR.scala:904:81, :945:{18,36}] wire _io_decode_0_virtual_access_illegal_T_7 = _io_decode_0_virtual_access_illegal_T_6[0]; // @[CSR.scala:945:71] wire _io_decode_0_virtual_access_illegal_T_8 = ~_io_decode_0_virtual_access_illegal_T_7; // @[CSR.scala:945:{55,71}] wire _io_decode_0_virtual_access_illegal_T_9 = reg_mstatus_prv[0]; // @[CSR.scala:395:28, :945:105] wire _io_decode_0_virtual_access_illegal_T_20 = reg_mstatus_prv[0]; // @[CSR.scala:395:28, :945:105, :946:53] wire _io_decode_0_virtual_access_illegal_T_25 = reg_mstatus_prv[0]; // @[CSR.scala:395:28, :945:105, :947:46] wire _io_decode_0_virtual_system_illegal_T_2 = reg_mstatus_prv[0]; // @[CSR.scala:395:28, :945:105, :953:34] wire _io_decode_0_virtual_system_illegal_T_12 = reg_mstatus_prv[0]; // @[CSR.scala:395:28, :945:105, :954:64] wire _io_decode_0_virtual_system_illegal_T_17 = reg_mstatus_prv[0]; // @[CSR.scala:395:28, :945:105, :955:37] wire _cause_T = reg_mstatus_prv[0]; // @[CSR.scala:395:28, :945:105, :959:61] wire _reg_hstatus_spvp_T = reg_mstatus_prv[0]; // @[CSR.scala:395:28, :945:105, :1067:61] wire _io_decode_0_virtual_access_illegal_T_10 = ~_io_decode_0_virtual_access_illegal_T_9; // @[CSR.scala:945:{89,105}] wire _io_decode_0_virtual_access_illegal_T_12 = _io_decode_0_virtual_access_illegal_T_11[0]; // @[CSR.scala:945:128] wire _io_decode_0_virtual_access_illegal_T_13 = ~_io_decode_0_virtual_access_illegal_T_12; // @[CSR.scala:945:{112,128}] wire _io_decode_0_virtual_access_illegal_T_14 = _io_decode_0_virtual_access_illegal_T_10 & _io_decode_0_virtual_access_illegal_T_13; // @[CSR.scala:945:{89,109,112}] wire _io_decode_0_virtual_access_illegal_T_15 = _io_decode_0_virtual_access_illegal_T_8 | _io_decode_0_virtual_access_illegal_T_14; // @[CSR.scala:945:{55,86,109}] wire _io_decode_0_virtual_access_illegal_T_16 = _io_decode_0_virtual_access_illegal_T_5 & _io_decode_0_virtual_access_illegal_T_15; // @[CSR.scala:945:{18,51,86}] wire _io_decode_0_virtual_access_illegal_T_17 = _io_decode_0_virtual_access_illegal_T_2 | _io_decode_0_virtual_access_illegal_T_16; // @[CSR.scala:944:{22,34}, :945:51] wire _io_decode_0_virtual_access_illegal_T_19 = _io_decode_0_virtual_access_illegal_T_18 == 2'h1; // @[CSR.scala:190:36, :946:22] wire _io_decode_0_virtual_access_illegal_T_21 = ~_io_decode_0_virtual_access_illegal_T_20; // @[CSR.scala:946:{37,53}] wire _io_decode_0_virtual_access_illegal_T_22 = _io_decode_0_virtual_access_illegal_T_19 & _io_decode_0_virtual_access_illegal_T_21; // @[CSR.scala:946:{22,34,37}] wire _io_decode_0_virtual_access_illegal_T_23 = _io_decode_0_virtual_access_illegal_T_17 | _io_decode_0_virtual_access_illegal_T_22; // @[CSR.scala:944:34, :945:144, :946:34] wire _io_decode_0_virtual_access_illegal_T_28 = _io_decode_0_virtual_access_illegal_T_23; // @[CSR.scala:945:144, :946:57] wire _io_decode_0_virtual_access_illegal_T_26 = _io_decode_0_virtual_access_illegal_T_24 & _io_decode_0_virtual_access_illegal_T_25; // @[CSR.scala:947:{12,28,46}] assign _io_decode_0_virtual_access_illegal_T_29 = _io_decode_0_virtual_access_illegal_T & _io_decode_0_virtual_access_illegal_T_28; // @[CSR.scala:943:{52,66}, :946:57] assign io_decode_0_virtual_access_illegal_0 = _io_decode_0_virtual_access_illegal_T_29; // @[CSR.scala:377:7, :943:66] wire _io_decode_0_virtual_system_illegal_T = is_hfence_vvma | is_hfence_gvma; // @[CSR.scala:903:82, :950:22] wire _io_decode_0_virtual_system_illegal_T_1 = _io_decode_0_virtual_system_illegal_T | is_hlsv; // @[CSR.scala:903:82, :950:22, :951:22] wire _io_decode_0_virtual_system_illegal_T_3 = ~_io_decode_0_virtual_system_illegal_T_2; // @[CSR.scala:953:{18,34}] wire _io_decode_0_virtual_system_illegal_T_6 = _io_decode_0_virtual_system_illegal_T_3; // @[CSR.scala:953:{18,38}] wire _io_decode_0_virtual_system_illegal_T_4 = ~reg_mstatus_tw; // @[CSR.scala:395:28, :906:74, :953:41] wire _io_decode_0_virtual_system_illegal_T_7 = is_wfi & _io_decode_0_virtual_system_illegal_T_6; // @[CSR.scala:903:82, :953:{14,38}] wire _io_decode_0_virtual_system_illegal_T_8 = _io_decode_0_virtual_system_illegal_T_1 | _io_decode_0_virtual_system_illegal_T_7; // @[CSR.scala:951:22, :952:15, :953:14] wire _io_decode_0_virtual_system_illegal_T_10 = _io_decode_0_virtual_system_illegal_T_9 == 2'h1; // @[CSR.scala:190:36, :954:32] wire _io_decode_0_virtual_system_illegal_T_11 = is_ret & _io_decode_0_virtual_system_illegal_T_10; // @[CSR.scala:903:82, :954:{14,32}] wire _io_decode_0_virtual_system_illegal_T_13 = ~_io_decode_0_virtual_system_illegal_T_12; // @[CSR.scala:954:{48,64}] wire _io_decode_0_virtual_system_illegal_T_14 = _io_decode_0_virtual_system_illegal_T_13; // @[CSR.scala:954:{48,68}] wire _io_decode_0_virtual_system_illegal_T_15 = _io_decode_0_virtual_system_illegal_T_11 & _io_decode_0_virtual_system_illegal_T_14; // @[CSR.scala:954:{14,44,68}] wire _io_decode_0_virtual_system_illegal_T_16 = _io_decode_0_virtual_system_illegal_T_8 | _io_decode_0_virtual_system_illegal_T_15; // @[CSR.scala:952:15, :953:77, :954:44] wire _io_decode_0_virtual_system_illegal_T_18 = ~_io_decode_0_virtual_system_illegal_T_17; // @[CSR.scala:955:{21,37}] wire _io_decode_0_virtual_system_illegal_T_19 = _io_decode_0_virtual_system_illegal_T_18; // @[CSR.scala:955:{21,41}] wire _io_decode_0_virtual_system_illegal_T_20 = is_sfence & _io_decode_0_virtual_system_illegal_T_19; // @[CSR.scala:903:82, :955:{17,41}] wire _io_decode_0_virtual_system_illegal_T_21 = _io_decode_0_virtual_system_illegal_T_16 | _io_decode_0_virtual_system_illegal_T_20; // @[CSR.scala:953:77, :954:89, :955:17] assign _io_decode_0_virtual_system_illegal_T_22 = reg_mstatus_v & _io_decode_0_virtual_system_illegal_T_21; // @[CSR.scala:395:28, :949:52, :954:89] assign io_decode_0_virtual_system_illegal_0 = _io_decode_0_virtual_system_illegal_T_22; // @[CSR.scala:377:7, :949:52] wire _cause_T_1 = _cause_T & reg_mstatus_v; // @[CSR.scala:395:28, :959:{61,65}] wire [1:0] _cause_T_2 = _cause_T_1 ? 2'h2 : reg_mstatus_prv; // @[CSR.scala:395:28, :959:{45,65}] wire [4:0] _cause_T_3 = {3'h0, _cause_T_2} + 5'h8; // @[CSR.scala:959:{40,45}] wire [3:0] _cause_T_4 = _cause_T_3[3:0]; // @[CSR.scala:959:40] wire [63:0] _cause_T_5 = insn_break ? 64'h3 : io_cause_0; // @[CSR.scala:377:7, :893:83, :960:14] assign cause = insn_call ? {60'h0, _cause_T_4} : _cause_T_5; // @[CSR.scala:893:83, :959:{8,40}, :960:14] assign io_trace_0_cause = cause; // @[CSR.scala:377:7, :959:8] wire [7:0] cause_lsbs = cause[7:0]; // @[CSR.scala:959:8, :961:25] wire [5:0] cause_deleg_lsbs = cause[5:0]; // @[CSR.scala:959:8, :962:31] wire [5:0] _notDebugTVec_interruptOffset_T = cause[5:0]; // @[CSR.scala:959:8, :962:31, :979:32] wire _causeIsDebugInt_T = cause[63]; // @[CSR.scala:959:8, :963:30] wire _causeIsDebugTrigger_T = cause[63]; // @[CSR.scala:959:8, :963:30, :964:35] wire _causeIsDebugBreak_T = cause[63]; // @[CSR.scala:959:8, :963:30, :965:33] wire _delegate_T_2 = cause[63]; // @[CSR.scala:959:8, :963:30, :970:78] wire _delegateVS_T_1 = cause[63]; // @[CSR.scala:959:8, :963:30, :971:58] wire _notDebugTVec_doVector_T_1 = cause[63]; // @[CSR.scala:959:8, :963:30, :981:36] wire _causeIsRnmiInt_T = cause[63]; // @[CSR.scala:959:8, :963:30, :985:29] wire _causeIsRnmiBEU_T = cause[63]; // @[CSR.scala:959:8, :963:30, :986:29] wire _reg_vscause_T = cause[63]; // @[CSR.scala:959:8, :963:30, :1060:31] assign _io_trace_0_interrupt_T = cause[63]; // @[CSR.scala:959:8, :963:30, :1626:25] wire _GEN_9 = cause_lsbs == 8'hE; // @[CSR.scala:961:25, :963:53] wire _causeIsDebugInt_T_1; // @[CSR.scala:963:53] assign _causeIsDebugInt_T_1 = _GEN_9; // @[CSR.scala:963:53] wire _causeIsDebugTrigger_T_2; // @[CSR.scala:964:58] assign _causeIsDebugTrigger_T_2 = _GEN_9; // @[CSR.scala:963:53, :964:58] wire causeIsDebugInt = _causeIsDebugInt_T & _causeIsDebugInt_T_1; // @[CSR.scala:963:{30,39,53}] wire _causeIsDebugTrigger_T_1 = ~_causeIsDebugTrigger_T; // @[CSR.scala:964:{29,35}] wire causeIsDebugTrigger = _causeIsDebugTrigger_T_1 & _causeIsDebugTrigger_T_2; // @[CSR.scala:964:{29,44,58}] wire _causeIsDebugBreak_T_1 = ~_causeIsDebugBreak_T; // @[CSR.scala:965:{27,33}] wire _causeIsDebugBreak_T_2 = _causeIsDebugBreak_T_1 & insn_break; // @[CSR.scala:893:83, :965:{27,42}] wire [1:0] causeIsDebugBreak_lo = {reg_dcsr_ebreaks, reg_dcsr_ebreaku}; // @[CSR.scala:403:25, :965:62] wire [1:0] causeIsDebugBreak_hi = {reg_dcsr_ebreakm, 1'h0}; // @[CSR.scala:403:25, :965:62] wire [3:0] _causeIsDebugBreak_T_3 = {causeIsDebugBreak_hi, causeIsDebugBreak_lo}; // @[CSR.scala:965:62] wire [3:0] _causeIsDebugBreak_T_4 = _causeIsDebugBreak_T_3 >> reg_mstatus_prv; // @[CSR.scala:395:28, :965:{62,134}] wire _causeIsDebugBreak_T_5 = _causeIsDebugBreak_T_4[0]; // @[CSR.scala:965:134] wire causeIsDebugBreak = _causeIsDebugBreak_T_2 & _causeIsDebugBreak_T_5; // @[CSR.scala:965:{42,56,134}] wire _trapToDebug_T = reg_singleStepped | causeIsDebugInt; // @[CSR.scala:486:30, :963:39, :966:56] wire _trapToDebug_T_1 = _trapToDebug_T | causeIsDebugTrigger; // @[CSR.scala:964:44, :966:{56,75}] wire _trapToDebug_T_2 = _trapToDebug_T_1 | causeIsDebugBreak; // @[CSR.scala:965:56, :966:{75,98}] wire _trapToDebug_T_3 = _trapToDebug_T_2 | reg_debug; // @[CSR.scala:482:26, :966:{98,119}] wire trapToDebug = _trapToDebug_T_3; // @[CSR.scala:966:{34,119}] wire [11:0] _debugTVec_T = {8'h80, ~insn_break, 3'h0}; // @[CSR.scala:893:83, :969:37] wire [11:0] debugTVec = reg_debug ? _debugTVec_T : 12'h800; // @[CSR.scala:482:26, :969:{22,37}] wire _delegate_T = ~(reg_mstatus_prv[1]); // @[CSR.scala:395:28, :620:51, :970:55] wire _delegate_T_1 = _delegate_T; // @[CSR.scala:970:{36,55}] wire [63:0] _GEN_10 = {58'h0, cause_deleg_lsbs}; // @[CSR.scala:962:31, :970:100] wire [63:0] _delegate_T_3 = read_mideleg >> _GEN_10; // @[CSR.scala:498:14, :970:100] wire _delegate_T_4 = _delegate_T_3[0]; // @[CSR.scala:970:100] wire [63:0] _delegate_T_5 = read_medeleg >> _GEN_10; // @[CSR.scala:502:14, :970:{100,132}] wire _delegate_T_6 = _delegate_T_5[0]; // @[CSR.scala:970:132] wire _delegate_T_7 = _delegate_T_2 ? _delegate_T_4 : _delegate_T_6; // @[CSR.scala:970:{72,78,100,132}] wire delegate = _delegate_T_1 & _delegate_T_7; // @[CSR.scala:970:{36,66,72}] wire _delegateVS_T = reg_mstatus_v & delegate; // @[CSR.scala:395:28, :970:66, :971:34] wire [63:0] _GEN_11 = 64'h0 >> _GEN_10; // @[CSR.scala:970:100, :971:80] wire [63:0] _delegateVS_T_2; // @[CSR.scala:971:80] assign _delegateVS_T_2 = _GEN_11; // @[CSR.scala:971:80] wire [63:0] _delegateVS_T_4; // @[CSR.scala:971:112] assign _delegateVS_T_4 = _GEN_11; // @[CSR.scala:971:{80,112}] wire _delegateVS_T_3 = _delegateVS_T_2[0]; // @[CSR.scala:971:80] wire _delegateVS_T_5 = _delegateVS_T_4[0]; // @[CSR.scala:971:112] wire _delegateVS_T_6 = _delegateVS_T_1 ? _delegateVS_T_3 : _delegateVS_T_5; // @[CSR.scala:971:{52,58,80,112}] wire delegateVS = _delegateVS_T & _delegateVS_T_6; // @[CSR.scala:971:{34,46,52}] wire [63:0] _notDebugTVec_base_T = delegateVS ? read_vstvec : read_stvec; // @[package.scala:132:15] wire [63:0] notDebugTVec_base = delegate ? _notDebugTVec_base_T : read_mtvec; // @[package.scala:138:15] wire [7:0] notDebugTVec_interruptOffset = {_notDebugTVec_interruptOffset_T, 2'h0}; // @[CSR.scala:979:{32,59}] wire [55:0] _notDebugTVec_interruptVec_T = notDebugTVec_base[63:8]; // @[CSR.scala:978:19, :980:33] wire [63:0] notDebugTVec_interruptVec = {_notDebugTVec_interruptVec_T, notDebugTVec_interruptOffset}; // @[CSR.scala:979:59, :980:{27,33}] wire _notDebugTVec_doVector_T = notDebugTVec_base[0]; // @[CSR.scala:978:19, :981:24] wire _notDebugTVec_doVector_T_2 = _notDebugTVec_doVector_T & _notDebugTVec_doVector_T_1; // @[CSR.scala:981:{24,28,36}] wire [1:0] _notDebugTVec_doVector_T_3 = cause_lsbs[7:6]; // @[CSR.scala:961:25, :981:70] wire _notDebugTVec_doVector_T_4 = _notDebugTVec_doVector_T_3 == 2'h0; // @[CSR.scala:981:{70,94}] wire notDebugTVec_doVector = _notDebugTVec_doVector_T_2 & _notDebugTVec_doVector_T_4; // @[CSR.scala:981:{28,55,94}] wire [61:0] _notDebugTVec_T = notDebugTVec_base[63:2]; // @[CSR.scala:978:19, :982:38] wire [63:0] _notDebugTVec_T_1 = {_notDebugTVec_T, 2'h0}; // @[CSR.scala:982:{38,56}] wire [63:0] notDebugTVec = notDebugTVec_doVector ? notDebugTVec_interruptVec : _notDebugTVec_T_1; // @[CSR.scala:980:27, :981:55, :982:{8,56}] wire [63:0] _tvec_T = notDebugTVec; // @[CSR.scala:982:8, :995:45] wire _causeIsRnmiInt_T_1 = cause[62]; // @[CSR.scala:959:8, :985:46] wire _causeIsRnmiBEU_T_1 = cause[62]; // @[CSR.scala:959:8, :985:46, :986:46] wire _causeIsRnmiInt_T_2 = _causeIsRnmiInt_T & _causeIsRnmiInt_T_1; // @[CSR.scala:985:{29,38,46}] wire _causeIsRnmiInt_T_3 = cause_lsbs == 8'hD; // @[CSR.scala:961:25, :985:70] wire _GEN_12 = cause_lsbs == 8'hC; // @[CSR.scala:961:25, :985:107] wire _causeIsRnmiInt_T_4; // @[CSR.scala:985:107] assign _causeIsRnmiInt_T_4 = _GEN_12; // @[CSR.scala:985:107] wire _causeIsRnmiBEU_T_3; // @[CSR.scala:986:69] assign _causeIsRnmiBEU_T_3 = _GEN_12; // @[CSR.scala:985:107, :986:69] wire _causeIsRnmiInt_T_5 = _causeIsRnmiInt_T_3 | _causeIsRnmiInt_T_4; // @[CSR.scala:985:{70,93,107}] wire causeIsRnmiInt = _causeIsRnmiInt_T_2 & _causeIsRnmiInt_T_5; // @[CSR.scala:985:{38,55,93}] wire _causeIsRnmiBEU_T_2 = _causeIsRnmiBEU_T & _causeIsRnmiBEU_T_1; // @[CSR.scala:986:{29,38,46}] wire causeIsRnmiBEU = _causeIsRnmiBEU_T_2 & _causeIsRnmiBEU_T_3; // @[CSR.scala:986:{38,55,69}] wire [63:0] tvec = trapToDebug ? {52'h0, debugTVec} : _tvec_T; // @[CSR.scala:966:34, :969:22, :995:{17,45}] wire _GEN_13 = insn_call | insn_break; // @[CSR.scala:893:83, :1000:24] wire _io_eret_T; // @[CSR.scala:1000:24] assign _io_eret_T = _GEN_13; // @[CSR.scala:1000:24] wire _exception_T; // @[CSR.scala:1020:29] assign _exception_T = _GEN_13; // @[CSR.scala:1000:24, :1020:29] assign _io_eret_T_1 = _io_eret_T | insn_ret; // @[CSR.scala:893:83, :1000:{24,38}] assign io_eret = _io_eret_T_1; // @[CSR.scala:377:7, :1000:38] wire _io_singleStep_T = ~reg_debug; // @[CSR.scala:482:26, :927:45, :1001:37] assign _io_singleStep_T_1 = reg_dcsr_step & _io_singleStep_T; // @[CSR.scala:403:25, :1001:{34,37}] assign io_singleStep_0 = _io_singleStep_T_1; // @[CSR.scala:377:7, :1001:34] wire _io_status_sd_T = &io_status_fs_0; // @[CSR.scala:377:7, :1003:32] wire _io_status_sd_T_2 = _io_status_sd_T; // @[CSR.scala:1003:{32,37}] assign _io_status_sd_T_4 = _io_status_sd_T_2; // @[CSR.scala:1003:{37,58}] assign io_status_sd_0 = _io_status_sd_T_4; // @[CSR.scala:377:7, :1003:58] wire _io_status_dprv_T = ~reg_debug; // @[CSR.scala:482:26, :927:45, :1008:45] wire _io_status_dprv_T_1 = reg_mstatus_mprv & _io_status_dprv_T; // @[CSR.scala:395:28, :1008:{42,45}] assign _io_status_dprv_T_2 = _io_status_dprv_T_1 ? reg_mstatus_mpp : reg_mstatus_prv; // @[CSR.scala:395:28, :1008:{24,42}] assign io_status_dprv_0 = _io_status_dprv_T_2; // @[CSR.scala:377:7, :1008:24] wire _io_status_dv_T = ~reg_debug; // @[CSR.scala:482:26, :927:45, :1009:60] wire _io_status_dv_T_1 = reg_mstatus_mprv & _io_status_dv_T; // @[CSR.scala:395:28, :1009:{57,60}] wire _io_status_dv_T_2 = _io_status_dv_T_1 & reg_mstatus_mpv; // @[CSR.scala:395:28, :1009:{39,57}] assign _io_status_dv_T_3 = reg_mstatus_v | _io_status_dv_T_2; // @[CSR.scala:395:28, :1009:{33,39}] assign io_status_dv_0 = _io_status_dv_T_3; // @[CSR.scala:377:7, :1009:33] wire _io_gstatus_sd_T_3 = &io_gstatus_vs; // @[CSR.scala:377:7, :1016:78] wire exception = _exception_T | io_exception_0; // @[CSR.scala:377:7, :1020:{29,43}] wire _en_T_8 = exception; // @[CSR.scala:1020:43, :1096:24] wire _en_T_20 = exception; // @[CSR.scala:1020:43, :1096:24] wire _en_T_32 = exception; // @[CSR.scala:1020:43, :1096:24] wire _en_T_44 = exception; // @[CSR.scala:1020:43, :1096:24] wire _en_T_56 = exception; // @[CSR.scala:1020:43, :1096:24] wire _en_T_68 = exception; // @[CSR.scala:1020:43, :1096:24] assign _io_trace_0_exception_T_1 = exception; // @[CSR.scala:1020:43, :1620:37] wire [39:0] _epc_T = ~io_pc_0; // @[CSR.scala:377:7, :1664:28] wire [39:0] _epc_T_1 = {_epc_T[39:1], 1'h1}; // @[CSR.scala:1664:{28,31}] wire [39:0] epc = ~_epc_T_1; // @[CSR.scala:1664:{26,31}] wire [39:0] tval = insn_break ? epc : io_tval_0; // @[CSR.scala:377:7, :893:83, :1033:17, :1664:26] wire [1:0] _reg_dcsr_cause_T = causeIsDebugTrigger ? 2'h2 : 2'h1; // @[CSR.scala:964:44, :1041:90] wire [1:0] _reg_dcsr_cause_T_1 = causeIsDebugInt ? 2'h3 : _reg_dcsr_cause_T; // @[CSR.scala:963:39, :1041:{58,90}] wire [2:0] _reg_dcsr_cause_T_2 = reg_singleStepped ? 3'h4 : {1'h0, _reg_dcsr_cause_T_1}; // @[CSR.scala:486:30, :1041:{30,58}] wire [1:0] _reg_mncause_T = {1'h1, causeIsRnmiBEU}; // @[CSR.scala:986:55, :1052:55] wire [63:0] _reg_mncause_T_1 = {62'h2000000000000000, _reg_mncause_T}; // @[CSR.scala:1052:{50,55}] wire [61:0] _reg_vscause_T_1 = cause[63:2]; // @[CSR.scala:959:8, :1060:50] wire [63:0] _reg_vscause_T_2 = {_reg_vscause_T_1, 2'h1}; // @[CSR.scala:1060:{44,50}] wire [63:0] _reg_vscause_T_3 = _reg_vscause_T ? _reg_vscause_T_2 : cause; // @[CSR.scala:959:8, :1060:{25,31,44}] wire _reg_hstatus_spvp_T_1 = reg_mstatus_v ? _reg_hstatus_spvp_T : reg_hstatus_spvp; // @[CSR.scala:395:28, :552:28, :1067:{30,61}] wire _GEN_14 = delegateVS | delegate; // @[CSR.scala:395:28, :970:66, :971:46, :1056:37, :1065:35, :1081:23] wire _en_T_5 = cause == 64'h8000000000000000; // @[CSR.scala:959:8, :1096:88] wire _en_T_11 = cause == 64'h8000000000000001; // @[CSR.scala:959:8, :1096:88] wire en_1 = _en_T_8 & _en_T_11; // @[CSR.scala:1096:{24,79,88}] wire _en_T_17 = cause == 64'h8000000000000002; // @[CSR.scala:959:8, :1096:88] wire _en_T_23 = cause == 64'h8000000000000003; // @[CSR.scala:959:8, :1096:88] wire en_3 = _en_T_20 & _en_T_23; // @[CSR.scala:1096:{24,79,88}] wire _en_T_29 = cause == 64'h8000000000000004; // @[CSR.scala:959:8, :1096:88] wire _en_T_35 = cause == 64'h8000000000000005; // @[CSR.scala:959:8, :1096:88] wire en_5 = _en_T_32 & _en_T_35; // @[CSR.scala:1096:{24,79,88}] wire _en_T_41 = cause == 64'h8000000000000006; // @[CSR.scala:959:8, :1096:88] wire _en_T_47 = cause == 64'h8000000000000007; // @[CSR.scala:959:8, :1096:88] wire en_7 = _en_T_44 & _en_T_47; // @[CSR.scala:1096:{24,79,88}] wire _en_T_53 = cause == 64'h8000000000000008; // @[CSR.scala:959:8, :1096:88] wire _en_T_59 = cause == 64'h8000000000000009; // @[CSR.scala:959:8, :1096:88] wire en_9 = _en_T_56 & _en_T_59; // @[CSR.scala:1096:{24,79,88}] wire _en_T_65 = cause == 64'h800000000000000A; // @[CSR.scala:959:8, :1096:88] wire _en_T_71 = cause == 64'h800000000000000B; // @[CSR.scala:959:8, :1096:88] wire en_11 = _en_T_68 & _en_T_71; // @[CSR.scala:1096:{24,79,88}] wire _en_T_77 = cause == 64'h800000000000000C; // @[CSR.scala:959:8, :1096:88] wire _en_T_83 = cause == 64'h800000000000000D; // @[CSR.scala:959:8, :1096:88] wire _en_T_89 = cause == 64'h800000000000000E; // @[CSR.scala:959:8, :1096:88] wire _en_T_95 = cause == 64'h800000000000000F; // @[CSR.scala:959:8, :1096:88] wire _en_T_96 = cause == 64'h1; // @[CSR.scala:959:8, :1108:35] wire en_16 = exception & _en_T_96; // @[CSR.scala:1020:43, :1108:{26,35}] wire _en_T_97 = cause == 64'h2; // @[CSR.scala:959:8, :1108:35] wire en_17 = exception & _en_T_97; // @[CSR.scala:1020:43, :1108:{26,35}] wire _en_T_98 = cause == 64'h3; // @[CSR.scala:959:8, :1108:35] wire en_18 = exception & _en_T_98; // @[CSR.scala:1020:43, :1108:{26,35}] wire _en_T_99 = cause == 64'h4; // @[CSR.scala:959:8, :1108:35] wire en_19 = exception & _en_T_99; // @[CSR.scala:1020:43, :1108:{26,35}] wire _en_T_100 = cause == 64'h5; // @[CSR.scala:959:8, :1108:35] wire en_20 = exception & _en_T_100; // @[CSR.scala:1020:43, :1108:{26,35}] wire _en_T_101 = cause == 64'h6; // @[CSR.scala:959:8, :1108:35] wire en_21 = exception & _en_T_101; // @[CSR.scala:1020:43, :1108:{26,35}] wire _en_T_102 = cause == 64'h7; // @[CSR.scala:959:8, :1108:35] wire en_22 = exception & _en_T_102; // @[CSR.scala:1020:43, :1108:{26,35}] wire _en_T_103 = cause == 64'h8; // @[CSR.scala:959:8, :1108:35] wire en_23 = exception & _en_T_103; // @[CSR.scala:1020:43, :1108:{26,35}] wire _en_T_104 = cause == 64'h9; // @[CSR.scala:959:8, :1108:35] wire en_24 = exception & _en_T_104; // @[CSR.scala:1020:43, :1108:{26,35}] wire _en_T_105 = cause == 64'hB; // @[CSR.scala:959:8, :1108:35] wire en_25 = exception & _en_T_105; // @[CSR.scala:1020:43, :1108:{26,35}] wire _en_T_106 = cause == 64'hC; // @[CSR.scala:959:8, :1108:35] wire en_26 = exception & _en_T_106; // @[CSR.scala:1020:43, :1108:{26,35}] wire _en_T_107 = cause == 64'hD; // @[CSR.scala:959:8, :1108:35] wire en_27 = exception & _en_T_107; // @[CSR.scala:1020:43, :1108:{26,35}] wire _en_T_108 = cause == 64'hF; // @[CSR.scala:959:8, :1108:35] wire en_28 = exception & _en_T_108; // @[CSR.scala:1020:43, :1108:{26,35}] wire [1:0] ret_prv; // @[CSR.scala:1116:27] wire [39:0] _io_evec_T_3 = {_io_evec_T[39:2], _io_evec_T[1:0] | 2'h1}; // @[CSR.scala:1665:{28,31}] wire [39:0] _io_evec_T_4 = ~_io_evec_T_3; // @[CSR.scala:1665:{26,31}] wire [39:0] _io_evec_T_5 = ~reg_vsepc; // @[CSR.scala:564:22, :1665:28] wire [39:0] _io_evec_T_8 = {_io_evec_T_5[39:2], _io_evec_T_5[1:0] | 2'h1}; // @[CSR.scala:1665:{28,31}] wire [39:0] _io_evec_T_9 = ~_io_evec_T_8; // @[CSR.scala:1665:{26,31}] wire _T_248 = io_rw_addr_0[10] & io_rw_addr_0[7]; // @[CSR.scala:377:7, :1134:{43,48,61}] wire _reg_mstatus_v_T_2 = ~(reg_dcsr_prv[1]); // @[CSR.scala:403:25, :1136:72] wire [39:0] _io_evec_T_10 = ~reg_dpc; // @[CSR.scala:483:20, :1665:28] wire [39:0] _io_evec_T_13 = {_io_evec_T_10[39:2], _io_evec_T_10[1:0] | 2'h1}; // @[CSR.scala:1665:{28,31}] wire [39:0] _io_evec_T_14 = ~_io_evec_T_13; // @[CSR.scala:1665:{26,31}] wire [39:0] _io_evec_T_18 = {_io_evec_T_15[39:2], _io_evec_T_15[1:0] | 2'h1}; // @[CSR.scala:1665:{28,31}] wire [39:0] _io_evec_T_19 = ~_io_evec_T_18; // @[CSR.scala:1665:{26,31}] assign ret_prv = io_rw_addr_0[9] ? (_T_248 ? reg_dcsr_prv : reg_mstatus_mpp) : {1'h0, reg_mstatus_v ? reg_vsstatus_spp : reg_mstatus_spp}; // @[CSR.scala:377:7, :395:28, :403:25, :562:25, :1116:27, :1117:{43,48}, :1118:29, :1122:17, :1130:17, :1134:{48,66}, :1135:15, :1139:65] wire _reg_mstatus_v_T_8 = ~(reg_mstatus_mpp[1]); // @[CSR.scala:395:28, :1150:80] wire [39:0] _io_evec_T_20 = ~reg_mepc; // @[CSR.scala:505:21, :1665:28] wire [39:0] _io_evec_T_23 = {_io_evec_T_20[39:2], _io_evec_T_20[1:0] | 2'h1}; // @[CSR.scala:1665:{28,31}] wire [39:0] _io_evec_T_24 = ~_io_evec_T_23; // @[CSR.scala:1665:{26,31}] assign io_evec_0 = insn_ret ? (io_rw_addr_0[9] ? (_T_248 ? _io_evec_T_14 : _io_evec_T_24) : reg_mstatus_v ? _io_evec_T_9 : _io_evec_T_4) : tvec[39:0]; // @[CSR.scala:377:7, :395:28, :893:83, :995:17, :996:11, :1115:19, :1117:{43,48}, :1118:29, :1124:17, :1132:17, :1134:{48,66}, :1138:15, :1139:65, :1665:26] assign new_prv = insn_ret ? ret_prv : exception ? (trapToDebug ? (reg_debug ? reg_mstatus_prv : 2'h3) : {~_GEN_14, 1'h1}) : reg_mstatus_prv; // @[CSR.scala:395:28, :397:28, :482:26, :893:83, :966:34, :1020:43, :1035:20, :1036:24, :1037:25, :1044:17, :1046:31, :1056:37, :1064:15, :1065:35, :1078:15, :1081:23, :1091:15, :1115:19, :1116:27, :1154:13] assign _io_csr_stall_T = reg_wfi | io_status_cease_0; // @[CSR.scala:377:7, :575:54, :1161:27] assign io_csr_stall_0 = _io_csr_stall_T; // @[CSR.scala:377:7, :1161:27] reg io_status_cease_r; // @[CSR.scala:1162:31] assign io_status_cease_0 = io_status_cease_r; // @[CSR.scala:377:7, :1162:31] wire [63:0] _io_rw_rdata_T_4 = decoded_addr_94_2 ? 64'h800000000014112D : 64'h0; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_153 = _io_rw_rdata_T_4; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_5 = decoded_addr_100_2 ? read_mstatus : 64'h0; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_6 = decoded_addr_72_2 ? read_mtvec : 64'h0; // @[Mux.scala:30:73] wire [15:0] _io_rw_rdata_T_7 = decoded_addr_108_2 ? read_mip : 16'h0; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_8 = decoded_addr_76_2 ? reg_mie : 64'h0; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_9 = decoded_addr_129_2 ? reg_mscratch : 64'h0; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_10 = decoded_addr_132_2 ? read_mapping_10_2 : 64'h0; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_11 = decoded_addr_136_2 ? read_mapping_11_2 : 64'h0; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_12 = decoded_addr_29_2 ? reg_mcause : 64'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_13 = decoded_addr_131_2 & io_hartid_0; // @[Mux.scala:30:73] wire [31:0] _io_rw_rdata_T_14 = decoded_addr_49_2 ? debug_csrs_0_2 : 32'h0; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_15 = decoded_addr_89_2 ? debug_csrs_1_2 : 64'h0; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_16 = decoded_addr_57_2 ? reg_dscratch0 : 64'h0; // @[Mux.scala:30:73] wire [4:0] _io_rw_rdata_T_17 = decoded_addr_36_2 ? reg_fflags : 5'h0; // @[Mux.scala:30:73] wire [2:0] _io_rw_rdata_T_18 = decoded_addr_68_2 ? reg_frm : 3'h0; // @[Mux.scala:30:73] wire [7:0] _io_rw_rdata_T_19 = decoded_addr_99_2 ? read_fcsr : 8'h0; // @[Mux.scala:30:73] wire [4:0] _io_rw_rdata_T_20 = decoded_addr_130_2 ? reg_mcountinhibit : 5'h0; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_21 = decoded_addr_103_2 ? value_1 : 64'h0; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_22 = decoded_addr_121_2 ? value : 64'h0; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_23 = decoded_addr_146_2 ? reg_hpmevent_0 : 64'h0; // @[Mux.scala:30:73] wire [39:0] _io_rw_rdata_T_24 = decoded_addr_17_2 ? value_2 : 40'h0; // @[Mux.scala:30:73] wire [39:0] _io_rw_rdata_T_25 = decoded_addr_27_2 ? value_2 : 40'h0; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_26 = decoded_addr_83_2 ? reg_hpmevent_1 : 64'h0; // @[Mux.scala:30:73] wire [39:0] _io_rw_rdata_T_27 = decoded_addr_52_2 ? value_3 : 40'h0; // @[Mux.scala:30:73] wire [39:0] _io_rw_rdata_T_28 = decoded_addr_144_2 ? value_3 : 40'h0; // @[Mux.scala:30:73] wire [31:0] _io_rw_rdata_T_110 = decoded_addr_35_2 ? read_mcounteren : 32'h0; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_111 = decoded_addr_2_2 ? value_1 : 64'h0; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_112 = decoded_addr_66_2 ? value : 64'h0; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_113 = decoded_addr_42_2 ? {57'h0, lo_4} : 64'h0; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_114 = decoded_addr_61_2 ? {hi_7[41:0], lo_5} : 64'h0; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_115 = decoded_addr_48_2 ? read_sip : 64'h0; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_116 = decoded_addr_44_2 ? read_sie : 64'h0; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_117 = decoded_addr_15_2 ? reg_sscratch : 64'h0; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_118 = decoded_addr_145_2 ? reg_scause : 64'h0; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_119 = decoded_addr_93_2 ? {{24{reg_stval[39]}}, reg_stval} : 64'h0; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_120 = decoded_addr_6_2 ? {hi_8, reg_satp_ppn} : 64'h0; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_121 = decoded_addr_28_2 ? {{24{_T_34[39]}}, _T_34} : 64'h0; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_122 = decoded_addr_25_2 ? read_stvec : 64'h0; // @[Mux.scala:30:73] wire [31:0] _io_rw_rdata_T_123 = decoded_addr_137_2 ? read_scounteren : 32'h0; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_124 = decoded_addr_123_2 ? read_mideleg : 64'h0; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_125 = decoded_addr_23_2 ? read_medeleg : 64'h0; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_126 = decoded_addr_69_2 ? {57'h0, lo_6} : 64'h0; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_127 = decoded_addr_141_2 ? {hi_18, lo_15} : 64'h0; // @[Mux.scala:30:73] wire [29:0] _io_rw_rdata_T_129 = decoded_addr_104_2 ? reg_pmp_0_addr : 30'h0; // @[Mux.scala:30:73] wire [29:0] _io_rw_rdata_T_130 = decoded_addr_8_2 ? reg_pmp_1_addr : 30'h0; // @[Mux.scala:30:73] wire [29:0] _io_rw_rdata_T_131 = decoded_addr_125_2 ? reg_pmp_2_addr : 30'h0; // @[Mux.scala:30:73] wire [29:0] _io_rw_rdata_T_132 = decoded_addr_85_2 ? reg_pmp_3_addr : 30'h0; // @[Mux.scala:30:73] wire [29:0] _io_rw_rdata_T_133 = decoded_addr_54_2 ? reg_pmp_4_addr : 30'h0; // @[Mux.scala:30:73] wire [29:0] _io_rw_rdata_T_134 = decoded_addr_20_2 ? reg_pmp_5_addr : 30'h0; // @[Mux.scala:30:73] wire [29:0] _io_rw_rdata_T_135 = decoded_addr_135_2 ? reg_pmp_6_addr : 30'h0; // @[Mux.scala:30:73] wire [29:0] _io_rw_rdata_T_136 = decoded_addr_115_2 ? reg_pmp_7_addr : 30'h0; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_145 = decoded_addr_18_2 ? reg_custom_0 : 64'h0; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_146 = decoded_addr_3_2 ? reg_custom_1 : 64'h0; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_154 = _io_rw_rdata_T_153 | _io_rw_rdata_T_5; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_155 = _io_rw_rdata_T_154 | _io_rw_rdata_T_6; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_156 = {_io_rw_rdata_T_155[63:16], _io_rw_rdata_T_155[15:0] | _io_rw_rdata_T_7}; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_157 = _io_rw_rdata_T_156 | _io_rw_rdata_T_8; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_158 = _io_rw_rdata_T_157 | _io_rw_rdata_T_9; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_159 = _io_rw_rdata_T_158 | _io_rw_rdata_T_10; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_160 = _io_rw_rdata_T_159 | _io_rw_rdata_T_11; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_161 = _io_rw_rdata_T_160 | _io_rw_rdata_T_12; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_162 = {_io_rw_rdata_T_161[63:1], _io_rw_rdata_T_161[0] | _io_rw_rdata_T_13}; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_163 = {_io_rw_rdata_T_162[63:32], _io_rw_rdata_T_162[31:0] | _io_rw_rdata_T_14}; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_164 = _io_rw_rdata_T_163 | _io_rw_rdata_T_15; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_165 = _io_rw_rdata_T_164 | _io_rw_rdata_T_16; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_166 = {_io_rw_rdata_T_165[63:5], _io_rw_rdata_T_165[4:0] | _io_rw_rdata_T_17}; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_167 = {_io_rw_rdata_T_166[63:3], _io_rw_rdata_T_166[2:0] | _io_rw_rdata_T_18}; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_168 = {_io_rw_rdata_T_167[63:8], _io_rw_rdata_T_167[7:0] | _io_rw_rdata_T_19}; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_169 = {_io_rw_rdata_T_168[63:5], _io_rw_rdata_T_168[4:0] | _io_rw_rdata_T_20}; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_170 = _io_rw_rdata_T_169 | _io_rw_rdata_T_21; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_171 = _io_rw_rdata_T_170 | _io_rw_rdata_T_22; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_172 = _io_rw_rdata_T_171 | _io_rw_rdata_T_23; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_173 = {_io_rw_rdata_T_172[63:40], _io_rw_rdata_T_172[39:0] | _io_rw_rdata_T_24}; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_174 = {_io_rw_rdata_T_173[63:40], _io_rw_rdata_T_173[39:0] | _io_rw_rdata_T_25}; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_175 = _io_rw_rdata_T_174 | _io_rw_rdata_T_26; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_176 = {_io_rw_rdata_T_175[63:40], _io_rw_rdata_T_175[39:0] | _io_rw_rdata_T_27}; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_177 = {_io_rw_rdata_T_176[63:40], _io_rw_rdata_T_176[39:0] | _io_rw_rdata_T_28}; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_178 = _io_rw_rdata_T_177; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_179 = _io_rw_rdata_T_178; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_180 = _io_rw_rdata_T_179; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_181 = _io_rw_rdata_T_180; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_182 = _io_rw_rdata_T_181; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_183 = _io_rw_rdata_T_182; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_184 = _io_rw_rdata_T_183; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_185 = _io_rw_rdata_T_184; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_186 = _io_rw_rdata_T_185; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_187 = _io_rw_rdata_T_186; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_188 = _io_rw_rdata_T_187; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_189 = _io_rw_rdata_T_188; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_190 = _io_rw_rdata_T_189; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_191 = _io_rw_rdata_T_190; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_192 = _io_rw_rdata_T_191; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_193 = _io_rw_rdata_T_192; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_194 = _io_rw_rdata_T_193; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_195 = _io_rw_rdata_T_194; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_196 = _io_rw_rdata_T_195; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_197 = _io_rw_rdata_T_196; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_198 = _io_rw_rdata_T_197; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_199 = _io_rw_rdata_T_198; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_200 = _io_rw_rdata_T_199; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_201 = _io_rw_rdata_T_200; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_202 = _io_rw_rdata_T_201; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_203 = _io_rw_rdata_T_202; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_204 = _io_rw_rdata_T_203; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_205 = _io_rw_rdata_T_204; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_206 = _io_rw_rdata_T_205; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_207 = _io_rw_rdata_T_206; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_208 = _io_rw_rdata_T_207; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_209 = _io_rw_rdata_T_208; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_210 = _io_rw_rdata_T_209; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_211 = _io_rw_rdata_T_210; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_212 = _io_rw_rdata_T_211; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_213 = _io_rw_rdata_T_212; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_214 = _io_rw_rdata_T_213; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_215 = _io_rw_rdata_T_214; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_216 = _io_rw_rdata_T_215; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_217 = _io_rw_rdata_T_216; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_218 = _io_rw_rdata_T_217; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_219 = _io_rw_rdata_T_218; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_220 = _io_rw_rdata_T_219; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_221 = _io_rw_rdata_T_220; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_222 = _io_rw_rdata_T_221; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_223 = _io_rw_rdata_T_222; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_224 = _io_rw_rdata_T_223; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_225 = _io_rw_rdata_T_224; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_226 = _io_rw_rdata_T_225; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_227 = _io_rw_rdata_T_226; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_228 = _io_rw_rdata_T_227; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_229 = _io_rw_rdata_T_228; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_230 = _io_rw_rdata_T_229; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_231 = _io_rw_rdata_T_230; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_232 = _io_rw_rdata_T_231; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_233 = _io_rw_rdata_T_232; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_234 = _io_rw_rdata_T_233; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_235 = _io_rw_rdata_T_234; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_236 = _io_rw_rdata_T_235; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_237 = _io_rw_rdata_T_236; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_238 = _io_rw_rdata_T_237; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_239 = _io_rw_rdata_T_238; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_240 = _io_rw_rdata_T_239; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_241 = _io_rw_rdata_T_240; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_242 = _io_rw_rdata_T_241; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_243 = _io_rw_rdata_T_242; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_244 = _io_rw_rdata_T_243; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_245 = _io_rw_rdata_T_244; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_246 = _io_rw_rdata_T_245; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_247 = _io_rw_rdata_T_246; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_248 = _io_rw_rdata_T_247; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_249 = _io_rw_rdata_T_248; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_250 = _io_rw_rdata_T_249; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_251 = _io_rw_rdata_T_250; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_252 = _io_rw_rdata_T_251; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_253 = _io_rw_rdata_T_252; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_254 = _io_rw_rdata_T_253; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_255 = _io_rw_rdata_T_254; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_256 = _io_rw_rdata_T_255; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_257 = _io_rw_rdata_T_256; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_258 = _io_rw_rdata_T_257; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_259 = {_io_rw_rdata_T_258[63:32], _io_rw_rdata_T_258[31:0] | _io_rw_rdata_T_110}; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_260 = _io_rw_rdata_T_259 | _io_rw_rdata_T_111; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_261 = _io_rw_rdata_T_260 | _io_rw_rdata_T_112; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_262 = _io_rw_rdata_T_261 | _io_rw_rdata_T_113; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_263 = _io_rw_rdata_T_262 | _io_rw_rdata_T_114; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_264 = _io_rw_rdata_T_263 | _io_rw_rdata_T_115; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_265 = _io_rw_rdata_T_264 | _io_rw_rdata_T_116; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_266 = _io_rw_rdata_T_265 | _io_rw_rdata_T_117; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_267 = _io_rw_rdata_T_266 | _io_rw_rdata_T_118; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_268 = _io_rw_rdata_T_267 | _io_rw_rdata_T_119; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_269 = _io_rw_rdata_T_268 | _io_rw_rdata_T_120; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_270 = _io_rw_rdata_T_269 | _io_rw_rdata_T_121; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_271 = _io_rw_rdata_T_270 | _io_rw_rdata_T_122; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_272 = {_io_rw_rdata_T_271[63:32], _io_rw_rdata_T_271[31:0] | _io_rw_rdata_T_123}; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_273 = _io_rw_rdata_T_272 | _io_rw_rdata_T_124; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_274 = _io_rw_rdata_T_273 | _io_rw_rdata_T_125; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_275 = _io_rw_rdata_T_274 | _io_rw_rdata_T_126; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_276 = _io_rw_rdata_T_275 | _io_rw_rdata_T_127; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_277 = _io_rw_rdata_T_276; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_278 = {_io_rw_rdata_T_277[63:30], _io_rw_rdata_T_277[29:0] | _io_rw_rdata_T_129}; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_279 = {_io_rw_rdata_T_278[63:30], _io_rw_rdata_T_278[29:0] | _io_rw_rdata_T_130}; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_280 = {_io_rw_rdata_T_279[63:30], _io_rw_rdata_T_279[29:0] | _io_rw_rdata_T_131}; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_281 = {_io_rw_rdata_T_280[63:30], _io_rw_rdata_T_280[29:0] | _io_rw_rdata_T_132}; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_282 = {_io_rw_rdata_T_281[63:30], _io_rw_rdata_T_281[29:0] | _io_rw_rdata_T_133}; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_283 = {_io_rw_rdata_T_282[63:30], _io_rw_rdata_T_282[29:0] | _io_rw_rdata_T_134}; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_284 = {_io_rw_rdata_T_283[63:30], _io_rw_rdata_T_283[29:0] | _io_rw_rdata_T_135}; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_285 = {_io_rw_rdata_T_284[63:30], _io_rw_rdata_T_284[29:0] | _io_rw_rdata_T_136}; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_286 = _io_rw_rdata_T_285; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_287 = _io_rw_rdata_T_286; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_288 = _io_rw_rdata_T_287; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_289 = _io_rw_rdata_T_288; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_290 = _io_rw_rdata_T_289; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_291 = _io_rw_rdata_T_290; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_292 = _io_rw_rdata_T_291; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_293 = _io_rw_rdata_T_292; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_294 = _io_rw_rdata_T_293 | _io_rw_rdata_T_145; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_295 = _io_rw_rdata_T_294 | _io_rw_rdata_T_146; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_296 = _io_rw_rdata_T_295; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_297 = _io_rw_rdata_T_296; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_298 = _io_rw_rdata_T_297; // @[Mux.scala:30:73] assign _io_rw_rdata_WIRE = _io_rw_rdata_T_298; // @[Mux.scala:30:73] assign io_rw_rdata_0 = _io_rw_rdata_WIRE; // @[Mux.scala:30:73] wire set_fs_dirty; // @[CSR.scala:1200:33]

Generate the Verilog code corresponding to the following Chisel files. File Transposer.scala: package gemmini import chisel3._ import chisel3.util._ import Util._ trait Transposer[T <: Data] extends Module { def dim: Int def dataType: T val io = IO(new Bundle { val inRow = Flipped(Decoupled(Vec(dim, dataType))) val outCol = Decoupled(Vec(dim, dataType)) }) } class PipelinedTransposer[T <: Data](val dim: Int, val dataType: T) extends Transposer[T] { require(isPow2(dim)) val regArray = Seq.fill(dim, dim)(Reg(dataType)) val regArrayT = regArray.transpose val sMoveUp :: sMoveLeft :: Nil = Enum(2) val state = RegInit(sMoveUp) val leftCounter = RegInit(0.U(log2Ceil(dim+1).W)) //(io.inRow.fire && state === sMoveLeft, dim+1) val upCounter = RegInit(0.U(log2Ceil(dim+1).W)) //Counter(io.inRow.fire && state === sMoveUp, dim+1) io.outCol.valid := 0.U io.inRow.ready := 0.U switch(state) { is(sMoveUp) { io.inRow.ready := upCounter <= dim.U io.outCol.valid := leftCounter > 0.U when(io.inRow.fire) { upCounter := upCounter + 1.U } when(upCounter === (dim-1).U) { state := sMoveLeft leftCounter := 0.U } when(io.outCol.fire) { leftCounter := leftCounter - 1.U } } is(sMoveLeft) { io.inRow.ready := leftCounter <= dim.U // TODO: this is naive io.outCol.valid := upCounter > 0.U when(leftCounter === (dim-1).U) { state := sMoveUp } when(io.inRow.fire) { leftCounter := leftCounter + 1.U upCounter := 0.U } when(io.outCol.fire) { upCounter := upCounter - 1.U } } } // Propagate input from bottom row to top row systolically in the move up phase // TODO: need to iterate over columns to connect Chisel values of type T // Should be able to operate directly on the Vec, but Seq and Vec don't mix (try Array?) for (colIdx <- 0 until dim) { regArray.foldRight(io.inRow.bits(colIdx)) { case (regRow, prevReg) => when (state === sMoveUp) { regRow(colIdx) := prevReg } regRow(colIdx) } } // Propagate input from right side to left side systolically in the move left phase for (rowIdx <- 0 until dim) { regArrayT.foldRight(io.inRow.bits(rowIdx)) { case (regCol, prevReg) => when (state === sMoveLeft) { regCol(rowIdx) := prevReg } regCol(rowIdx) } } // Pull from the left side or the top side based on the state for (idx <- 0 until dim) { when (state === sMoveUp) { io.outCol.bits(idx) := regArray(0)(idx) }.elsewhen(state === sMoveLeft) { io.outCol.bits(idx) := regArrayT(0)(idx) }.otherwise { io.outCol.bits(idx) := DontCare } } } class AlwaysOutTransposer[T <: Data](val dim: Int, val dataType: T) extends Transposer[T] { require(isPow2(dim)) val LEFT_DIR = 0.U(1.W) val UP_DIR = 1.U(1.W) class PE extends Module { val io = IO(new Bundle { val inR = Input(dataType) val inD = Input(dataType) val outL = Output(dataType) val outU = Output(dataType) val dir = Input(UInt(1.W)) val en = Input(Bool()) }) val reg = RegEnable(Mux(io.dir === LEFT_DIR, io.inR, io.inD), io.en) io.outU := reg io.outL := reg } val pes = Seq.fill(dim,dim)(Module(new PE)) val counter = RegInit(0.U((log2Ceil(dim) max 1).W)) // TODO replace this with a standard Chisel counter val dir = RegInit(LEFT_DIR) // Wire up horizontal signals for (row <- 0 until dim; col <- 0 until dim) { val right_in = if (col == dim-1) io.inRow.bits(row) else pes(row)(col+1).io.outL pes(row)(col).io.inR := right_in } // Wire up vertical signals for (row <- 0 until dim; col <- 0 until dim) { val down_in = if (row == dim-1) io.inRow.bits(col) else pes(row+1)(col).io.outU pes(row)(col).io.inD := down_in } // Wire up global signals pes.flatten.foreach(_.io.dir := dir) pes.flatten.foreach(_.io.en := io.inRow.fire) io.outCol.valid := true.B io.inRow.ready := true.B val left_out = VecInit(pes.transpose.head.map(_.io.outL)) val up_out = VecInit(pes.head.map(_.io.outU)) io.outCol.bits := Mux(dir === LEFT_DIR, left_out, up_out) when (io.inRow.fire) { counter := wrappingAdd(counter, 1.U, dim) } when (counter === (dim-1).U && io.inRow.fire) { dir := ~dir } } class NaiveTransposer[T <: Data](val dim: Int, val dataType: T) extends Transposer[T] { val regArray = Seq.fill(dim, dim)(Reg(dataType)) val regArrayT = regArray.transpose // state = 0 => filling regArray row-wise, state = 1 => draining regArray column-wise val state = RegInit(0.U(1.W)) val countInc = io.inRow.fire || io.outCol.fire val (countValue, countWrap) = Counter(countInc, dim) io.inRow.ready := state === 0.U io.outCol.valid := state === 1.U for (i <- 0 until dim) { for (j <- 0 until dim) { when(countValue === i.U && io.inRow.fire) { regArray(i)(j) := io.inRow.bits(j) } } } for (i <- 0 until dim) { io.outCol.bits(i) := 0.U for (j <- 0 until dim) { when(countValue === j.U) { io.outCol.bits(i) := regArrayT(j)(i) } } } when (io.inRow.fire && countWrap) { state := 1.U } when (io.outCol.fire && countWrap) { state := 0.U } assert(!(state === 0.U) || !io.outCol.fire) assert(!(state === 1.U) || !io.inRow.fire) }

module PE_47( // @[Transposer.scala:100:9] input clock, // @[Transposer.scala:100:9] input reset, // @[Transposer.scala:100:9] input [7:0] io_inR, // @[Transposer.scala:101:16] input [7:0] io_inD, // @[Transposer.scala:101:16] output [7:0] io_outL, // @[Transposer.scala:101:16] output [7:0] io_outU, // @[Transposer.scala:101:16] input io_dir, // @[Transposer.scala:101:16] input io_en // @[Transposer.scala:101:16] ); wire [7:0] io_inR_0 = io_inR; // @[Transposer.scala:100:9] wire [7:0] io_inD_0 = io_inD; // @[Transposer.scala:100:9] wire io_dir_0 = io_dir; // @[Transposer.scala:100:9] wire io_en_0 = io_en; // @[Transposer.scala:100:9] wire [7:0] io_outL_0; // @[Transposer.scala:100:9] wire [7:0] io_outU_0; // @[Transposer.scala:100:9] wire _reg_T = ~io_dir_0; // @[Transposer.scala:100:9, :110:36] wire [7:0] _reg_T_1 = _reg_T ? io_inR_0 : io_inD_0; // @[Transposer.scala:100:9, :110:{28,36}] reg [7:0] reg_0; // @[Transposer.scala:110:24] assign io_outL_0 = reg_0; // @[Transposer.scala:100:9, :110:24] assign io_outU_0 = reg_0; // @[Transposer.scala:100:9, :110:24] always @(posedge clock) begin // @[Transposer.scala:100:9] if (io_en_0) // @[Transposer.scala:100:9] reg_0 <= _reg_T_1; // @[Transposer.scala:110:{24,28}] always @(posedge) assign io_outL = io_outL_0; // @[Transposer.scala:100:9] assign io_outU = io_outU_0; // @[Transposer.scala:100:9] endmodule

Generate the Verilog code corresponding to the following Chisel files. File Tilelink.scala: package constellation.protocol import chisel3._ import chisel3.util._ import constellation.channel._ import constellation.noc._ import constellation.soc.{CanAttachToGlobalNoC} import org.chipsalliance.cde.config._ import freechips.rocketchip.diplomacy._ import freechips.rocketchip.util._ import freechips.rocketchip.tilelink._ import scala.collection.immutable.{ListMap} trait TLFieldHelper { def getBodyFields(b: TLChannel): Seq[Data] = b match { case b: TLBundleA => Seq(b.mask, b.data, b.corrupt) case b: TLBundleB => Seq(b.mask, b.data, b.corrupt) case b: TLBundleC => Seq( b.data, b.corrupt) case b: TLBundleD => Seq( b.data, b.corrupt) case b: TLBundleE => Seq() } def getConstFields(b: TLChannel): Seq[Data] = b match { case b: TLBundleA => Seq(b.opcode, b.param, b.size, b.source, b.address, b.user, b.echo ) case b: TLBundleB => Seq(b.opcode, b.param, b.size, b.source, b.address ) case b: TLBundleC => Seq(b.opcode, b.param, b.size, b.source, b.address, b.user, b.echo ) case b: TLBundleD => Seq(b.opcode, b.param, b.size, b.source, b.user, b.echo, b.sink, b.denied) case b: TLBundleE => Seq( b.sink ) } def minTLPayloadWidth(b: TLChannel): Int = Seq(getBodyFields(b), getConstFields(b)).map(_.map(_.getWidth).sum).max def minTLPayloadWidth(bs: Seq[TLChannel]): Int = bs.map(b => minTLPayloadWidth(b)).max def minTLPayloadWidth(b: TLBundle): Int = minTLPayloadWidth(Seq(b.a, b.b, b.c, b.d, b.e).map(_.bits)) } class TLMasterToNoC( edgeIn: TLEdge, edgesOut: Seq[TLEdge], sourceStart: Int, sourceSize: Int, wideBundle: TLBundleParameters, slaveToEgressOffset: Int => Int, flitWidth: Int )(implicit p: Parameters) extends Module { val io = IO(new Bundle { val tilelink = Flipped(new TLBundle(wideBundle)) val flits = new Bundle { val a = Decoupled(new IngressFlit(flitWidth)) val b = Flipped(Decoupled(new EgressFlit(flitWidth))) val c = Decoupled(new IngressFlit(flitWidth)) val d = Flipped(Decoupled(new EgressFlit(flitWidth))) val e = Decoupled(new IngressFlit(flitWidth)) } }) val a = Module(new TLAToNoC(edgeIn, edgesOut, wideBundle, (i) => slaveToEgressOffset(i) + 0, sourceStart)) val b = Module(new TLBFromNoC(edgeIn, wideBundle, sourceSize)) val c = Module(new TLCToNoC(edgeIn, edgesOut, wideBundle, (i) => slaveToEgressOffset(i) + 1, sourceStart)) val d = Module(new TLDFromNoC(edgeIn, wideBundle, sourceSize)) val e = Module(new TLEToNoC(edgeIn, edgesOut, wideBundle, (i) => slaveToEgressOffset(i) + 2)) a.io.protocol <> io.tilelink.a io.tilelink.b <> b.io.protocol c.io.protocol <> io.tilelink.c io.tilelink.d <> d.io.protocol e.io.protocol <> io.tilelink.e io.flits.a <> a.io.flit b.io.flit <> io.flits.b io.flits.c <> c.io.flit d.io.flit <> io.flits.d io.flits.e <> e.io.flit } class TLMasterACDToNoC( edgeIn: TLEdge, edgesOut: Seq[TLEdge], sourceStart: Int, sourceSize: Int, wideBundle: TLBundleParameters, slaveToEgressOffset: Int => Int, flitWidth: Int )(implicit p: Parameters) extends Module { val io = IO(new Bundle { val tilelink = Flipped(new TLBundle(wideBundle)) val flits = new Bundle { val a = Decoupled(new IngressFlit(flitWidth)) val c = Decoupled(new IngressFlit(flitWidth)) val d = Flipped(Decoupled(new EgressFlit(flitWidth))) } }) io.tilelink := DontCare val a = Module(new TLAToNoC(edgeIn, edgesOut, wideBundle, (i) => slaveToEgressOffset(i) + 0, sourceStart)) val c = Module(new TLCToNoC(edgeIn, edgesOut, wideBundle, (i) => slaveToEgressOffset(i) + 1, sourceStart)) val d = Module(new TLDFromNoC(edgeIn, wideBundle, sourceSize)) a.io.protocol <> io.tilelink.a c.io.protocol <> io.tilelink.c io.tilelink.d <> d.io.protocol io.flits.a <> a.io.flit io.flits.c <> c.io.flit d.io.flit <> io.flits.d } class TLMasterBEToNoC( edgeIn: TLEdge, edgesOut: Seq[TLEdge], sourceStart: Int, sourceSize: Int, wideBundle: TLBundleParameters, slaveToEgressOffset: Int => Int, flitWidth: Int )(implicit p: Parameters) extends Module { val io = IO(new Bundle { val tilelink = Flipped(new TLBundle(wideBundle)) val flits = new Bundle { val b = Flipped(Decoupled(new EgressFlit(flitWidth))) val e = Decoupled(new IngressFlit(flitWidth)) } }) io.tilelink := DontCare val b = Module(new TLBFromNoC(edgeIn, wideBundle, sourceSize)) val e = Module(new TLEToNoC(edgeIn, edgesOut, wideBundle, (i) => slaveToEgressOffset(i) + 0)) io.tilelink.b <> b.io.protocol e.io.protocol <> io.tilelink.e b.io.flit <> io.flits.b io.flits.e <> e.io.flit } class TLSlaveToNoC( edgeOut: TLEdge, edgesIn: Seq[TLEdge], sourceStart: Int, sourceSize: Int, wideBundle: TLBundleParameters, masterToEgressOffset: Int => Int, flitWidth: Int )(implicit p: Parameters) extends Module { val io = IO(new Bundle { val tilelink = new TLBundle(wideBundle) val flits = new Bundle { val a = Flipped(Decoupled(new EgressFlit(flitWidth))) val b = Decoupled(new IngressFlit(flitWidth)) val c = Flipped(Decoupled(new EgressFlit(flitWidth))) val d = Decoupled(new IngressFlit(flitWidth)) val e = Flipped(Decoupled(new EgressFlit(flitWidth))) } }) val a = Module(new TLAFromNoC(edgeOut, wideBundle)) val b = Module(new TLBToNoC(edgeOut, edgesIn, wideBundle, (i) => masterToEgressOffset(i) + 0)) val c = Module(new TLCFromNoC(edgeOut, wideBundle)) val d = Module(new TLDToNoC(edgeOut, edgesIn, wideBundle, (i) => masterToEgressOffset(i) + 1, sourceStart)) val e = Module(new TLEFromNoC(edgeOut, wideBundle, sourceSize)) io.tilelink.a <> a.io.protocol b.io.protocol <> io.tilelink.b io.tilelink.c <> c.io.protocol d.io.protocol <> io.tilelink.d io.tilelink.e <> e.io.protocol a.io.flit <> io.flits.a io.flits.b <> b.io.flit c.io.flit <> io.flits.c io.flits.d <> d.io.flit e.io.flit <> io.flits.e } class TLSlaveACDToNoC( edgeOut: TLEdge, edgesIn: Seq[TLEdge], sourceStart: Int, sourceSize: Int, wideBundle: TLBundleParameters, masterToEgressOffset: Int => Int, flitWidth: Int )(implicit p: Parameters) extends Module { val io = IO(new Bundle { val tilelink = new TLBundle(wideBundle) val flits = new Bundle { val a = Flipped(Decoupled(new EgressFlit(flitWidth))) val c = Flipped(Decoupled(new EgressFlit(flitWidth))) val d = Decoupled(new IngressFlit(flitWidth)) } }) io.tilelink := DontCare val a = Module(new TLAFromNoC(edgeOut, wideBundle)) val c = Module(new TLCFromNoC(edgeOut, wideBundle)) val d = Module(new TLDToNoC(edgeOut, edgesIn, wideBundle, (i) => masterToEgressOffset(i) + 0, sourceStart)) io.tilelink.a <> a.io.protocol io.tilelink.c <> c.io.protocol d.io.protocol <> io.tilelink.d a.io.flit <> io.flits.a c.io.flit <> io.flits.c io.flits.d <> d.io.flit } class TLSlaveBEToNoC( edgeOut: TLEdge, edgesIn: Seq[TLEdge], sourceStart: Int, sourceSize: Int, wideBundle: TLBundleParameters, masterToEgressOffset: Int => Int, flitWidth: Int )(implicit p: Parameters) extends Module { val io = IO(new Bundle { val tilelink = new TLBundle(wideBundle) val flits = new Bundle { val b = Decoupled(new IngressFlit(flitWidth)) val e = Flipped(Decoupled(new EgressFlit(flitWidth))) } }) io.tilelink := DontCare val b = Module(new TLBToNoC(edgeOut, edgesIn, wideBundle, (i) => masterToEgressOffset(i) + 0)) val e = Module(new TLEFromNoC(edgeOut, wideBundle, sourceSize)) b.io.protocol <> io.tilelink.b io.tilelink.e <> e.io.protocol io.flits.b <> b.io.flit e.io.flit <> io.flits.e } class TileLinkInterconnectInterface(edgesIn: Seq[TLEdge], edgesOut: Seq[TLEdge])(implicit val p: Parameters) extends Bundle { val in = MixedVec(edgesIn.map { e => Flipped(new TLBundle(e.bundle)) }) val out = MixedVec(edgesOut.map { e => new TLBundle(e.bundle) }) } trait TileLinkProtocolParams extends ProtocolParams with TLFieldHelper { def edgesIn: Seq[TLEdge] def edgesOut: Seq[TLEdge] def edgeInNodes: Seq[Int] def edgeOutNodes: Seq[Int] require(edgesIn.size == edgeInNodes.size && edgesOut.size == edgeOutNodes.size) def wideBundle = TLBundleParameters.union(edgesIn.map(_.bundle) ++ edgesOut.map(_.bundle)) def genBundle = new TLBundle(wideBundle) def inputIdRanges = TLXbar.mapInputIds(edgesIn.map(_.client)) def outputIdRanges = TLXbar.mapOutputIds(edgesOut.map(_.manager)) val vNetBlocking = (blocker: Int, blockee: Int) => blocker < blockee def genIO()(implicit p: Parameters): Data = new TileLinkInterconnectInterface(edgesIn, edgesOut) } object TLConnect { def apply[T <: TLBundleBase](l: DecoupledIO[T], r: DecoupledIO[T]) = { l.valid := r.valid r.ready := l.ready l.bits.squeezeAll.waiveAll :<>= r.bits.squeezeAll.waiveAll } } // BEGIN: TileLinkProtocolParams case class TileLinkABCDEProtocolParams( edgesIn: Seq[TLEdge], edgesOut: Seq[TLEdge], edgeInNodes: Seq[Int], edgeOutNodes: Seq[Int] ) extends TileLinkProtocolParams { // END: TileLinkProtocolParams val minPayloadWidth = minTLPayloadWidth(new TLBundle(wideBundle)) val ingressNodes = (edgeInNodes.map(u => Seq.fill(3) (u)) ++ edgeOutNodes.map(u => Seq.fill (2) {u})).flatten val egressNodes = (edgeInNodes.map(u => Seq.fill(2) (u)) ++ edgeOutNodes.map(u => Seq.fill (3) {u})).flatten val nVirtualNetworks = 5 val flows = edgesIn.zipWithIndex.map { case (edgeIn, ii) => edgesOut.zipWithIndex.map { case (edgeOut, oi) => val reachable = edgeIn.client.clients.exists { c => edgeOut.manager.managers.exists { m => c.visibility.exists { ca => m.address.exists { ma => ca.overlaps(ma) }} }} val probe = edgeIn.client.anySupportProbe && edgeOut.manager.managers.exists(_.regionType >= RegionType.TRACKED) val release = edgeIn.client.anySupportProbe && edgeOut.manager.anySupportAcquireB ( (if (reachable) Some(FlowParams(ii * 3 + 0 , oi * 3 + 0 + edgesIn.size * 2, 4)) else None) ++ // A (if (probe ) Some(FlowParams(oi * 2 + 0 + edgesIn.size * 3, ii * 2 + 0 , 3)) else None) ++ // B (if (release ) Some(FlowParams(ii * 3 + 1 , oi * 3 + 1 + edgesIn.size * 2, 2)) else None) ++ // C (if (reachable) Some(FlowParams(oi * 2 + 1 + edgesIn.size * 3, ii * 2 + 1 , 1)) else None) ++ // D (if (release ) Some(FlowParams(ii * 3 + 2 , oi * 3 + 2 + edgesIn.size * 2, 0)) else None)) // E }}.flatten.flatten def interface(terminals: NoCTerminalIO, ingressOffset: Int, egressOffset: Int, protocol: Data)(implicit p: Parameters) = { val ingresses = terminals.ingress val egresses = terminals.egress protocol match { case protocol: TileLinkInterconnectInterface => { edgesIn.zipWithIndex.map { case (e,i) => val nif_master = Module(new TLMasterToNoC( e, edgesOut, inputIdRanges(i).start, inputIdRanges(i).size, wideBundle, (s) => s * 3 + edgesIn.size * 2 + egressOffset, minPayloadWidth )) nif_master.io.tilelink := DontCare nif_master.io.tilelink.a.valid := false.B nif_master.io.tilelink.c.valid := false.B nif_master.io.tilelink.e.valid := false.B TLConnect(nif_master.io.tilelink.a, protocol.in(i).a) TLConnect(protocol.in(i).d, nif_master.io.tilelink.d) if (protocol.in(i).params.hasBCE) { TLConnect(protocol.in(i).b, nif_master.io.tilelink.b) TLConnect(nif_master.io.tilelink.c, protocol.in(i).c) TLConnect(nif_master.io.tilelink.e, protocol.in(i).e) } ingresses(i * 3 + 0).flit <> nif_master.io.flits.a ingresses(i * 3 + 1).flit <> nif_master.io.flits.c ingresses(i * 3 + 2).flit <> nif_master.io.flits.e nif_master.io.flits.b <> egresses(i * 2 + 0).flit nif_master.io.flits.d <> egresses(i * 2 + 1).flit } edgesOut.zipWithIndex.map { case (e,i) => val nif_slave = Module(new TLSlaveToNoC( e, edgesIn, outputIdRanges(i).start, outputIdRanges(i).size, wideBundle, (s) => s * 2 + egressOffset, minPayloadWidth )) nif_slave.io.tilelink := DontCare nif_slave.io.tilelink.b.valid := false.B nif_slave.io.tilelink.d.valid := false.B TLConnect(protocol.out(i).a, nif_slave.io.tilelink.a) TLConnect(nif_slave.io.tilelink.d, protocol.out(i).d) if (protocol.out(i).params.hasBCE) { TLConnect(nif_slave.io.tilelink.b, protocol.out(i).b) TLConnect(protocol.out(i).c, nif_slave.io.tilelink.c) TLConnect(protocol.out(i).e, nif_slave.io.tilelink.e) } ingresses(i * 2 + 0 + edgesIn.size * 3).flit <> nif_slave.io.flits.b ingresses(i * 2 + 1 + edgesIn.size * 3).flit <> nif_slave.io.flits.d nif_slave.io.flits.a <> egresses(i * 3 + 0 + edgesIn.size * 2).flit nif_slave.io.flits.c <> egresses(i * 3 + 1 + edgesIn.size * 2).flit nif_slave.io.flits.e <> egresses(i * 3 + 2 + edgesIn.size * 2).flit } } } } } case class TileLinkACDProtocolParams( edgesIn: Seq[TLEdge], edgesOut: Seq[TLEdge], edgeInNodes: Seq[Int], edgeOutNodes: Seq[Int]) extends TileLinkProtocolParams { val minPayloadWidth = minTLPayloadWidth(Seq(genBundle.a, genBundle.c, genBundle.d).map(_.bits)) val ingressNodes = (edgeInNodes.map(u => Seq.fill(2) (u)) ++ edgeOutNodes.map(u => Seq.fill (1) {u})).flatten val egressNodes = (edgeInNodes.map(u => Seq.fill(1) (u)) ++ edgeOutNodes.map(u => Seq.fill (2) {u})).flatten val nVirtualNetworks = 3 val flows = edgesIn.zipWithIndex.map { case (edgeIn, ii) => edgesOut.zipWithIndex.map { case (edgeOut, oi) => val reachable = edgeIn.client.clients.exists { c => edgeOut.manager.managers.exists { m => c.visibility.exists { ca => m.address.exists { ma => ca.overlaps(ma) }} }} val release = edgeIn.client.anySupportProbe && edgeOut.manager.anySupportAcquireB ( (if (reachable) Some(FlowParams(ii * 2 + 0 , oi * 2 + 0 + edgesIn.size * 1, 2)) else None) ++ // A (if (release ) Some(FlowParams(ii * 2 + 1 , oi * 2 + 1 + edgesIn.size * 1, 1)) else None) ++ // C (if (reachable) Some(FlowParams(oi * 1 + 0 + edgesIn.size * 2, ii * 1 + 0 , 0)) else None)) // D }}.flatten.flatten def interface(terminals: NoCTerminalIO, ingressOffset: Int, egressOffset: Int, protocol: Data)(implicit p: Parameters) = { val ingresses = terminals.ingress val egresses = terminals.egress protocol match { case protocol: TileLinkInterconnectInterface => { protocol := DontCare edgesIn.zipWithIndex.map { case (e,i) => val nif_master_acd = Module(new TLMasterACDToNoC( e, edgesOut, inputIdRanges(i).start, inputIdRanges(i).size, wideBundle, (s) => s * 2 + edgesIn.size * 1 + egressOffset, minPayloadWidth )) nif_master_acd.io.tilelink := DontCare nif_master_acd.io.tilelink.a.valid := false.B nif_master_acd.io.tilelink.c.valid := false.B nif_master_acd.io.tilelink.e.valid := false.B TLConnect(nif_master_acd.io.tilelink.a, protocol.in(i).a) TLConnect(protocol.in(i).d, nif_master_acd.io.tilelink.d) if (protocol.in(i).params.hasBCE) { TLConnect(nif_master_acd.io.tilelink.c, protocol.in(i).c) } ingresses(i * 2 + 0).flit <> nif_master_acd.io.flits.a ingresses(i * 2 + 1).flit <> nif_master_acd.io.flits.c nif_master_acd.io.flits.d <> egresses(i * 1 + 0).flit } edgesOut.zipWithIndex.map { case (e,i) => val nif_slave_acd = Module(new TLSlaveACDToNoC( e, edgesIn, outputIdRanges(i).start, outputIdRanges(i).size, wideBundle, (s) => s * 1 + egressOffset, minPayloadWidth )) nif_slave_acd.io.tilelink := DontCare nif_slave_acd.io.tilelink.b.valid := false.B nif_slave_acd.io.tilelink.d.valid := false.B TLConnect(protocol.out(i).a, nif_slave_acd.io.tilelink.a) TLConnect(nif_slave_acd.io.tilelink.d, protocol.out(i).d) if (protocol.out(i).params.hasBCE) { TLConnect(protocol.out(i).c, nif_slave_acd.io.tilelink.c) } ingresses(i * 1 + 0 + edgesIn.size * 2).flit <> nif_slave_acd.io.flits.d nif_slave_acd.io.flits.a <> egresses(i * 2 + 0 + edgesIn.size * 1).flit nif_slave_acd.io.flits.c <> egresses(i * 2 + 1 + edgesIn.size * 1).flit } }} } } case class TileLinkBEProtocolParams( edgesIn: Seq[TLEdge], edgesOut: Seq[TLEdge], edgeInNodes: Seq[Int], edgeOutNodes: Seq[Int]) extends TileLinkProtocolParams { val minPayloadWidth = minTLPayloadWidth(Seq(genBundle.b, genBundle.e).map(_.bits)) val ingressNodes = (edgeInNodes.map(u => Seq.fill(1) (u)) ++ edgeOutNodes.map(u => Seq.fill (1) {u})).flatten val egressNodes = (edgeInNodes.map(u => Seq.fill(1) (u)) ++ edgeOutNodes.map(u => Seq.fill (1) {u})).flatten val nVirtualNetworks = 2 val flows = edgesIn.zipWithIndex.map { case (edgeIn, ii) => edgesOut.zipWithIndex.map { case (edgeOut, oi) => val probe = edgeIn.client.anySupportProbe && edgeOut.manager.managers.exists(_.regionType >= RegionType.TRACKED) val release = edgeIn.client.anySupportProbe && edgeOut.manager.anySupportAcquireB ( (if (probe ) Some(FlowParams(oi * 1 + 0 + edgesIn.size * 1, ii * 1 + 0 , 1)) else None) ++ // B (if (release ) Some(FlowParams(ii * 1 + 0 , oi * 1 + 0 + edgesIn.size * 1, 0)) else None)) // E }}.flatten.flatten def interface(terminals: NoCTerminalIO, ingressOffset: Int, egressOffset: Int, protocol: Data)(implicit p: Parameters) = { val ingresses = terminals.ingress val egresses = terminals.egress protocol match { case protocol: TileLinkInterconnectInterface => { protocol := DontCare edgesIn.zipWithIndex.map { case (e,i) => val nif_master_be = Module(new TLMasterBEToNoC( e, edgesOut, inputIdRanges(i).start, inputIdRanges(i).size, wideBundle, (s) => s * 1 + edgesIn.size * 1 + egressOffset, minPayloadWidth )) nif_master_be.io.tilelink := DontCare nif_master_be.io.tilelink.a.valid := false.B nif_master_be.io.tilelink.c.valid := false.B nif_master_be.io.tilelink.e.valid := false.B if (protocol.in(i).params.hasBCE) { TLConnect(protocol.in(i).b, nif_master_be.io.tilelink.b) TLConnect(nif_master_be.io.tilelink.e, protocol.in(i).e) } ingresses(i * 1 + 0).flit <> nif_master_be.io.flits.e nif_master_be.io.flits.b <> egresses(i * 1 + 0).flit } edgesOut.zipWithIndex.map { case (e,i) => val nif_slave_be = Module(new TLSlaveBEToNoC( e, edgesIn, outputIdRanges(i).start, outputIdRanges(i).size, wideBundle, (s) => s * 1 + egressOffset, minPayloadWidth )) nif_slave_be.io.tilelink := DontCare nif_slave_be.io.tilelink.b.valid := false.B nif_slave_be.io.tilelink.d.valid := false.B if (protocol.out(i).params.hasBCE) { TLConnect(protocol.out(i).e, nif_slave_be.io.tilelink.e) TLConnect(nif_slave_be.io.tilelink.b, protocol.out(i).b) } ingresses(i * 1 + 0 + edgesIn.size * 1).flit <> nif_slave_be.io.flits.b nif_slave_be.io.flits.e <> egresses(i * 1 + 0 + edgesIn.size * 1).flit } }} } } abstract class TLNoCLike(implicit p: Parameters) extends LazyModule { val node = new TLNexusNode( clientFn = { seq => seq(0).v1copy( echoFields = BundleField.union(seq.flatMap(_.echoFields)), requestFields = BundleField.union(seq.flatMap(_.requestFields)), responseKeys = seq.flatMap(_.responseKeys).distinct, minLatency = seq.map(_.minLatency).min, clients = (TLXbar.mapInputIds(seq) zip seq) flatMap { case (range, port) => port.clients map { client => client.v1copy( sourceId = client.sourceId.shift(range.start) )} } ) }, managerFn = { seq => val fifoIdFactory = TLXbar.relabeler() seq(0).v1copy( responseFields = BundleField.union(seq.flatMap(_.responseFields)), requestKeys = seq.flatMap(_.requestKeys).distinct, minLatency = seq.map(_.minLatency).min, endSinkId = TLXbar.mapOutputIds(seq).map(_.end).max, managers = seq.flatMap { port => require (port.beatBytes == seq(0).beatBytes, s"TLNoC (data widths don't match: ${port.managers.map(_.name)} has ${port.beatBytes}B vs ${seq(0).managers.map(_.name)} has ${seq(0).beatBytes}B") // TileLink NoC does not preserve FIFO-ness, masters to this NoC should instantiate FIFOFixers port.managers map { manager => manager.v1copy(fifoId = None) } } ) } ) } abstract class TLNoCModuleImp(outer: LazyModule) extends LazyModuleImp(outer) { val edgesIn: Seq[TLEdge] val edgesOut: Seq[TLEdge] val nodeMapping: DiplomaticNetworkNodeMapping val nocName: String lazy val inNames = nodeMapping.genUniqueName(edgesIn.map(_.master.masters.map(_.name))) lazy val outNames = nodeMapping.genUniqueName(edgesOut.map(_.slave.slaves.map(_.name))) lazy val edgeInNodes = nodeMapping.getNodesIn(inNames) lazy val edgeOutNodes = nodeMapping.getNodesOut(outNames) def printNodeMappings() { println(s"Constellation: TLNoC $nocName inwards mapping:") for ((n, i) <- inNames zip edgeInNodes) { val node = i.map(_.toString).getOrElse("X") println(s" $node <- $n") } println(s"Constellation: TLNoC $nocName outwards mapping:") for ((n, i) <- outNames zip edgeOutNodes) { val node = i.map(_.toString).getOrElse("X") println(s" $node <- $n") } } } trait TLNoCParams // Instantiates a private TLNoC. Replaces the TLXbar // BEGIN: TLNoCParams case class SimpleTLNoCParams( nodeMappings: DiplomaticNetworkNodeMapping, nocParams: NoCParams = NoCParams(), ) extends TLNoCParams class TLNoC(params: SimpleTLNoCParams, name: String = "test", inlineNoC: Boolean = false)(implicit p: Parameters) extends TLNoCLike { // END: TLNoCParams override def shouldBeInlined = inlineNoC lazy val module = new TLNoCModuleImp(this) { val (io_in, edgesIn) = node.in.unzip val (io_out, edgesOut) = node.out.unzip val nodeMapping = params.nodeMappings val nocName = name printNodeMappings() val protocolParams = TileLinkABCDEProtocolParams( edgesIn = edgesIn, edgesOut = edgesOut, edgeInNodes = edgeInNodes.flatten, edgeOutNodes = edgeOutNodes.flatten ) val noc = Module(new ProtocolNoC(ProtocolNoCParams( params.nocParams.copy(hasCtrl = false, nocName=name, inlineNoC = inlineNoC), Seq(protocolParams), inlineNoC = inlineNoC ))) noc.io.protocol(0) match { case protocol: TileLinkInterconnectInterface => { (protocol.in zip io_in).foreach { case (l,r) => l <> r } (io_out zip protocol.out).foreach { case (l,r) => l <> r } } } } } case class SplitACDxBETLNoCParams( nodeMappings: DiplomaticNetworkNodeMapping, acdNoCParams: NoCParams = NoCParams(), beNoCParams: NoCParams = NoCParams(), beDivision: Int = 2 ) extends TLNoCParams class TLSplitACDxBENoC(params: SplitACDxBETLNoCParams, name: String = "test", inlineNoC: Boolean = false)(implicit p: Parameters) extends TLNoCLike { override def shouldBeInlined = inlineNoC lazy val module = new TLNoCModuleImp(this) { val (io_in, edgesIn) = node.in.unzip val (io_out, edgesOut) = node.out.unzip val nodeMapping = params.nodeMappings val nocName = name printNodeMappings() val acdProtocolParams = TileLinkACDProtocolParams( edgesIn = edgesIn, edgesOut = edgesOut, edgeInNodes = edgeInNodes.flatten, edgeOutNodes = edgeOutNodes.flatten ) val beProtocolParams = TileLinkBEProtocolParams( edgesIn = edgesIn, edgesOut = edgesOut, edgeInNodes = edgeInNodes.flatten, edgeOutNodes = edgeOutNodes.flatten ) val acd_noc = Module(new ProtocolNoC(ProtocolNoCParams( params.acdNoCParams.copy(hasCtrl = false, nocName=s"${name}_acd", inlineNoC = inlineNoC), Seq(acdProtocolParams), inlineNoC = inlineNoC ))) val be_noc = Module(new ProtocolNoC(ProtocolNoCParams( params.beNoCParams.copy(hasCtrl = false, nocName=s"${name}_be", inlineNoC = inlineNoC), Seq(beProtocolParams), widthDivision = params.beDivision, inlineNoC = inlineNoC ))) acd_noc.io.protocol(0) match { case protocol: TileLinkInterconnectInterface => { (protocol.in zip io_in).foreach { case (l,r) => l := DontCare l.a <> r.a l.c <> r.c l.d <> r.d } (io_out zip protocol.out).foreach { case (l,r) => r := DontCare l.a <> r.a l.c <> r.c l.d <> r.d } }} be_noc.io.protocol(0) match { case protocol: TileLinkInterconnectInterface => { (protocol.in zip io_in).foreach { case (l,r) => l := DontCare l.b <> r.b l.e <> r.e } (io_out zip protocol.out).foreach { case (l,r) => r := DontCare l.b <> r.b l.e <> r.e } }} } } case class GlobalTLNoCParams( nodeMappings: DiplomaticNetworkNodeMapping ) extends TLNoCParams // Maps this interconnect onto a global NoC class TLGlobalNoC(params: GlobalTLNoCParams, name: String = "test")(implicit p: Parameters) extends TLNoCLike { lazy val module = new TLNoCModuleImp(this) with CanAttachToGlobalNoC { val (io_in, edgesIn) = node.in.unzip val (io_out, edgesOut) = node.out.unzip val nodeMapping = params.nodeMappings val nocName = name val protocolParams = TileLinkABCDEProtocolParams( edgesIn = edgesIn, edgesOut = edgesOut, edgeInNodes = edgeInNodes.flatten, edgeOutNodes = edgeOutNodes.flatten ) printNodeMappings() val io_global = IO(Flipped(protocolParams.genIO())) io_global match { case protocol: TileLinkInterconnectInterface => { (protocol.in zip io_in).foreach { case (l,r) => l <> r } (io_out zip protocol.out).foreach { case (l,r) => l <> r } } } } }

module TLMasterBEToNoC( // @[Tilelink.scala:100:7] input clock, // @[Tilelink.scala:100:7] input reset, // @[Tilelink.scala:100:7] output io_flits_b_ready, // @[Tilelink.scala:107:14] input io_flits_b_valid, // @[Tilelink.scala:107:14] input io_flits_b_bits_head, // @[Tilelink.scala:107:14] input io_flits_b_bits_tail, // @[Tilelink.scala:107:14] input io_flits_e_ready, // @[Tilelink.scala:107:14] output io_flits_e_valid, // @[Tilelink.scala:107:14] output io_flits_e_bits_head, // @[Tilelink.scala:107:14] output [144:0] io_flits_e_bits_payload, // @[Tilelink.scala:107:14] output [4:0] io_flits_e_bits_egress_id // @[Tilelink.scala:107:14] ); wire [5:0] _e_io_flit_bits_payload; // @[Tilelink.scala:116:17] TLBFromNoC b ( // @[Tilelink.scala:115:17] .clock (clock), .reset (reset), .io_flit_ready (io_flits_b_ready), .io_flit_valid (io_flits_b_valid), .io_flit_bits_head (io_flits_b_bits_head), .io_flit_bits_tail (io_flits_b_bits_tail) ); // @[Tilelink.scala:115:17] TLEToNoC e ( // @[Tilelink.scala:116:17] .clock (clock), .reset (reset), .io_protocol_ready (/* unused */), .io_protocol_valid (1'h0), // @[Tilelink.scala:107:14, :115:17, :116:17] .io_protocol_bits_sink (6'h0), // @[Tilelink.scala:107:14, :116:17] .io_flit_ready (io_flits_e_ready), .io_flit_valid (io_flits_e_valid), .io_flit_bits_head (io_flits_e_bits_head), .io_flit_bits_payload (_e_io_flit_bits_payload), .io_flit_bits_egress_id (io_flits_e_bits_egress_id) ); // @[Tilelink.scala:116:17] assign io_flits_e_bits_payload = {139'h0, _e_io_flit_bits_payload}; // @[Tilelink.scala:100:7, :116:17, :121:14] endmodule

Generate the Verilog code corresponding to the following Chisel files. File Tile.scala: // See README.md for license details. package gemmini import chisel3._ import chisel3.util._ import Util._ /** * A Tile is a purely combinational 2D array of passThrough PEs. * a, b, s, and in_propag are broadcast across the entire array and are passed through to the Tile's outputs * @param width The data width of each PE in bits * @param rows Number of PEs on each row * @param columns Number of PEs on each column */ class Tile[T <: Data](inputType: T, outputType: T, accType: T, df: Dataflow.Value, tree_reduction: Boolean, max_simultaneous_matmuls: Int, val rows: Int, val columns: Int)(implicit ev: Arithmetic[T]) extends Module { val io = IO(new Bundle { val in_a = Input(Vec(rows, inputType)) val in_b = Input(Vec(columns, outputType)) // This is the output of the tile next to it val in_d = Input(Vec(columns, outputType)) val in_control = Input(Vec(columns, new PEControl(accType))) val in_id = Input(Vec(columns, UInt(log2Up(max_simultaneous_matmuls).W))) val in_last = Input(Vec(columns, Bool())) val out_a = Output(Vec(rows, inputType)) val out_c = Output(Vec(columns, outputType)) val out_b = Output(Vec(columns, outputType)) val out_control = Output(Vec(columns, new PEControl(accType))) val out_id = Output(Vec(columns, UInt(log2Up(max_simultaneous_matmuls).W))) val out_last = Output(Vec(columns, Bool())) val in_valid = Input(Vec(columns, Bool())) val out_valid = Output(Vec(columns, Bool())) val bad_dataflow = Output(Bool()) }) import ev._ val tile = Seq.fill(rows, columns)(Module(new PE(inputType, outputType, accType, df, max_simultaneous_matmuls))) val tileT = tile.transpose // TODO: abstract hori/vert broadcast, all these connections look the same // Broadcast 'a' horizontally across the Tile for (r <- 0 until rows) { tile(r).foldLeft(io.in_a(r)) { case (in_a, pe) => pe.io.in_a := in_a pe.io.out_a } } // Broadcast 'b' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_b(c)) { case (in_b, pe) => pe.io.in_b := (if (tree_reduction) in_b.zero else in_b) pe.io.out_b } } // Broadcast 'd' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_d(c)) { case (in_d, pe) => pe.io.in_d := in_d pe.io.out_c } } // Broadcast 'control' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_control(c)) { case (in_ctrl, pe) => pe.io.in_control := in_ctrl pe.io.out_control } } // Broadcast 'garbage' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_valid(c)) { case (v, pe) => pe.io.in_valid := v pe.io.out_valid } } // Broadcast 'id' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_id(c)) { case (id, pe) => pe.io.in_id := id pe.io.out_id } } // Broadcast 'last' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_last(c)) { case (last, pe) => pe.io.in_last := last pe.io.out_last } } // Drive the Tile's bottom IO for (c <- 0 until columns) { io.out_c(c) := tile(rows-1)(c).io.out_c io.out_control(c) := tile(rows-1)(c).io.out_control io.out_id(c) := tile(rows-1)(c).io.out_id io.out_last(c) := tile(rows-1)(c).io.out_last io.out_valid(c) := tile(rows-1)(c).io.out_valid io.out_b(c) := { if (tree_reduction) { val prods = tileT(c).map(_.io.out_b) accumulateTree(prods :+ io.in_b(c)) } else { tile(rows - 1)(c).io.out_b } } } io.bad_dataflow := tile.map(_.map(_.io.bad_dataflow).reduce(_||_)).reduce(_||_) // Drive the Tile's right IO for (r <- 0 until rows) { io.out_a(r) := tile(r)(columns-1).io.out_a } }

module Tile_190( // @[Tile.scala:16:7] input clock, // @[Tile.scala:16:7] input reset, // @[Tile.scala:16:7] input [7:0] io_in_a_0, // @[Tile.scala:17:14] input [19:0] io_in_b_0, // @[Tile.scala:17:14] input [19:0] io_in_d_0, // @[Tile.scala:17:14] input io_in_control_0_dataflow, // @[Tile.scala:17:14] input io_in_control_0_propagate, // @[Tile.scala:17:14] input [4:0] io_in_control_0_shift, // @[Tile.scala:17:14] input [2:0] io_in_id_0, // @[Tile.scala:17:14] input io_in_last_0, // @[Tile.scala:17:14] output [7:0] io_out_a_0, // @[Tile.scala:17:14] output [19:0] io_out_c_0, // @[Tile.scala:17:14] output [19:0] io_out_b_0, // @[Tile.scala:17:14] output io_out_control_0_dataflow, // @[Tile.scala:17:14] output io_out_control_0_propagate, // @[Tile.scala:17:14] output [4:0] io_out_control_0_shift, // @[Tile.scala:17:14] output [2:0] io_out_id_0, // @[Tile.scala:17:14] output io_out_last_0, // @[Tile.scala:17:14] input io_in_valid_0, // @[Tile.scala:17:14] output io_out_valid_0, // @[Tile.scala:17:14] output io_bad_dataflow // @[Tile.scala:17:14] ); wire [7:0] io_in_a_0_0 = io_in_a_0; // @[Tile.scala:16:7] wire [19:0] io_in_b_0_0 = io_in_b_0; // @[Tile.scala:16:7] wire [19:0] io_in_d_0_0 = io_in_d_0; // @[Tile.scala:16:7] wire io_in_control_0_dataflow_0 = io_in_control_0_dataflow; // @[Tile.scala:16:7] wire io_in_control_0_propagate_0 = io_in_control_0_propagate; // @[Tile.scala:16:7] wire [4:0] io_in_control_0_shift_0 = io_in_control_0_shift; // @[Tile.scala:16:7] wire [2:0] io_in_id_0_0 = io_in_id_0; // @[Tile.scala:16:7] wire io_in_last_0_0 = io_in_last_0; // @[Tile.scala:16:7] wire io_in_valid_0_0 = io_in_valid_0; // @[Tile.scala:16:7] wire [7:0] io_out_a_0_0; // @[Tile.scala:16:7] wire [19:0] io_out_c_0_0; // @[Tile.scala:16:7] wire [19:0] io_out_b_0_0; // @[Tile.scala:16:7] wire io_out_control_0_dataflow_0; // @[Tile.scala:16:7] wire io_out_control_0_propagate_0; // @[Tile.scala:16:7] wire [4:0] io_out_control_0_shift_0; // @[Tile.scala:16:7] wire [2:0] io_out_id_0_0; // @[Tile.scala:16:7] wire io_out_last_0_0; // @[Tile.scala:16:7] wire io_out_valid_0_0; // @[Tile.scala:16:7] wire io_bad_dataflow_0; // @[Tile.scala:16:7] PE_446 tile_0_0 ( // @[Tile.scala:42:44] .clock (clock), .reset (reset), .io_in_a (io_in_a_0_0), // @[Tile.scala:16:7] .io_in_b (io_in_b_0_0), // @[Tile.scala:16:7] .io_in_d (io_in_d_0_0), // @[Tile.scala:16:7] .io_out_a (io_out_a_0_0), .io_out_b (io_out_b_0_0), .io_out_c (io_out_c_0_0), .io_in_control_dataflow (io_in_control_0_dataflow_0), // @[Tile.scala:16:7] .io_in_control_propagate (io_in_control_0_propagate_0), // @[Tile.scala:16:7] .io_in_control_shift (io_in_control_0_shift_0), // @[Tile.scala:16:7] .io_out_control_dataflow (io_out_control_0_dataflow_0), .io_out_control_propagate (io_out_control_0_propagate_0), .io_out_control_shift (io_out_control_0_shift_0), .io_in_id (io_in_id_0_0), // @[Tile.scala:16:7] .io_out_id (io_out_id_0_0), .io_in_last (io_in_last_0_0), // @[Tile.scala:16:7] .io_out_last (io_out_last_0_0), .io_in_valid (io_in_valid_0_0), // @[Tile.scala:16:7] .io_out_valid (io_out_valid_0_0), .io_bad_dataflow (io_bad_dataflow_0) ); // @[Tile.scala:42:44] assign io_out_a_0 = io_out_a_0_0; // @[Tile.scala:16:7] assign io_out_c_0 = io_out_c_0_0; // @[Tile.scala:16:7] assign io_out_b_0 = io_out_b_0_0; // @[Tile.scala:16:7] assign io_out_control_0_dataflow = io_out_control_0_dataflow_0; // @[Tile.scala:16:7] assign io_out_control_0_propagate = io_out_control_0_propagate_0; // @[Tile.scala:16:7] assign io_out_control_0_shift = io_out_control_0_shift_0; // @[Tile.scala:16:7] assign io_out_id_0 = io_out_id_0_0; // @[Tile.scala:16:7] assign io_out_last_0 = io_out_last_0_0; // @[Tile.scala:16:7] assign io_out_valid_0 = io_out_valid_0_0; // @[Tile.scala:16:7] assign io_bad_dataflow = io_bad_dataflow_0; // @[Tile.scala:16:7] endmodule

Generate the Verilog code corresponding to the following Chisel files. File ShiftReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ // Similar to the Chisel ShiftRegister but allows the user to suggest a // name to the registers that get instantiated, and // to provide a reset value. object ShiftRegInit { def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T = (0 until n).foldRight(in) { case (i, next) => { val r = RegNext(next, init) name.foreach { na => r.suggestName(s"${na}_${i}") } r } } } /** These wrap behavioral * shift registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * The different types vary in their reset behavior: * AsyncResetShiftReg -- Asynchronously reset register array * A W(width) x D(depth) sized array is constructed from D instantiations of a * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg, * but only used for timing applications */ abstract class AbstractPipelineReg(w: Int = 1) extends Module { val io = IO(new Bundle { val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) } ) } object AbstractPipelineReg { def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = { val chain = Module(gen) name.foreach{ chain.suggestName(_) } chain.io.d := in.asUInt chain.io.q.asTypeOf(in) } } class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) { require(depth > 0, "Depth must be greater than 0.") override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}" val chain = List.tabulate(depth) { i => Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}") } chain.last.io.d := io.d chain.last.io.en := true.B (chain.init zip chain.tail).foreach { case (sink, source) => sink.io.d := source.io.q sink.io.en := true.B } io.q := chain.head.io.q } object AsyncResetShiftReg { def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name) def apply [T <: Data](in: T, depth: Int, name: Option[String]): T = apply(in, depth, 0, name) def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T = apply(in, depth, init.litValue.toInt, name) def apply [T <: Data](in: T, depth: Int, init: T): T = apply (in, depth, init.litValue.toInt, None) } File SynchronizerReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util.{RegEnable, Cat} /** These wrap behavioral * shift and next registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * * These are built up of *ResetSynchronizerPrimitiveShiftReg, * intended to be replaced by the integrator's metastable flops chains or replaced * at this level if they have a multi-bit wide synchronizer primitive. * The different types vary in their reset behavior: * NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin * AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep * 1-bit-wide shift registers. * SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg * * [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference. * * ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross * Clock Domains. */ object SynchronizerResetType extends Enumeration { val NonSync, Inferred, Sync, Async = Value } // Note: this should not be used directly. // Use the companion object to generate this with the correct reset type mixin. private class SynchronizerPrimitiveShiftReg( sync: Int, init: Boolean, resetType: SynchronizerResetType.Value) extends AbstractPipelineReg(1) { val initInt = if (init) 1 else 0 val initPostfix = resetType match { case SynchronizerResetType.NonSync => "" case _ => s"_i${initInt}" } override def desiredName = s"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}" val chain = List.tabulate(sync) { i => val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B) reg.suggestName(s"sync_$i") } chain.last := io.d.asBool (chain.init zip chain.tail).foreach { case (sink, source) => sink := source } io.q := chain.head.asUInt } private object SynchronizerPrimitiveShiftReg { def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = { val gen: () => SynchronizerPrimitiveShiftReg = resetType match { case SynchronizerResetType.NonSync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) case SynchronizerResetType.Async => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset case SynchronizerResetType.Sync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset case SynchronizerResetType.Inferred => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) } AbstractPipelineReg(gen(), in) } } // Note: This module may end up with a non-AsyncReset type reset. // But the Primitives within will always have AsyncReset type. class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asAsyncReset){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async) } } io.q := Cat(output.reverse) } object AsyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } // Note: This module may end up with a non-Bool type reset. // But the Primitives within will always have Bool reset type. @deprecated("SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.", "rocket-chip 1.2") class SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asBool){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync) } } io.q := Cat(output.reverse) } object SyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred) } io.q := Cat(output.reverse) } object ResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}" val output = Seq.tabulate(w) { i => SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync) } io.q := Cat(output.reverse) } object SynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, None) def apply [T <: Data](in: T): T = apply (in, 3, None) } class ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module { override def desiredName = s"ClockCrossingReg_w${w}" val io = IO(new Bundle{ val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) val en = Input(Bool()) }) val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en) io.q := cdc_reg } object ClockCrossingReg { def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = { val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit)) name.foreach{ cdc_reg.suggestName(_) } cdc_reg.io.d := in.asUInt cdc_reg.io.en := en cdc_reg.io.q.asTypeOf(in) } }

module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_82( // @[SynchronizerReg.scala:68:19] input clock, // @[SynchronizerReg.scala:68:19] input reset, // @[SynchronizerReg.scala:68:19] input io_d, // @[ShiftReg.scala:36:14] output io_q // @[ShiftReg.scala:36:14] ); wire io_d_0 = io_d; // @[SynchronizerReg.scala:68:19] wire _sync_2_T = io_d_0; // @[SynchronizerReg.scala:54:22, :68:19] wire io_q_0; // @[SynchronizerReg.scala:68:19] reg sync_0; // @[SynchronizerReg.scala:51:87] assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19] reg sync_1; // @[SynchronizerReg.scala:51:87] reg sync_2; // @[SynchronizerReg.scala:51:87] always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19] if (reset) begin // @[SynchronizerReg.scala:68:19] sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87] end else begin // @[SynchronizerReg.scala:68:19] sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87] sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87] sync_2 <= _sync_2_T; // @[SynchronizerReg.scala:51:87, :54:22] end always @(posedge, posedge)

Generate the Verilog code corresponding to the following Chisel files. File Tile.scala: // See README.md for license details. package gemmini import chisel3._ import chisel3.util._ import Util._ /** * A Tile is a purely combinational 2D array of passThrough PEs. * a, b, s, and in_propag are broadcast across the entire array and are passed through to the Tile's outputs * @param width The data width of each PE in bits * @param rows Number of PEs on each row * @param columns Number of PEs on each column */ class Tile[T <: Data](inputType: T, outputType: T, accType: T, df: Dataflow.Value, tree_reduction: Boolean, max_simultaneous_matmuls: Int, val rows: Int, val columns: Int)(implicit ev: Arithmetic[T]) extends Module { val io = IO(new Bundle { val in_a = Input(Vec(rows, inputType)) val in_b = Input(Vec(columns, outputType)) // This is the output of the tile next to it val in_d = Input(Vec(columns, outputType)) val in_control = Input(Vec(columns, new PEControl(accType))) val in_id = Input(Vec(columns, UInt(log2Up(max_simultaneous_matmuls).W))) val in_last = Input(Vec(columns, Bool())) val out_a = Output(Vec(rows, inputType)) val out_c = Output(Vec(columns, outputType)) val out_b = Output(Vec(columns, outputType)) val out_control = Output(Vec(columns, new PEControl(accType))) val out_id = Output(Vec(columns, UInt(log2Up(max_simultaneous_matmuls).W))) val out_last = Output(Vec(columns, Bool())) val in_valid = Input(Vec(columns, Bool())) val out_valid = Output(Vec(columns, Bool())) val bad_dataflow = Output(Bool()) }) import ev._ val tile = Seq.fill(rows, columns)(Module(new PE(inputType, outputType, accType, df, max_simultaneous_matmuls))) val tileT = tile.transpose // TODO: abstract hori/vert broadcast, all these connections look the same // Broadcast 'a' horizontally across the Tile for (r <- 0 until rows) { tile(r).foldLeft(io.in_a(r)) { case (in_a, pe) => pe.io.in_a := in_a pe.io.out_a } } // Broadcast 'b' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_b(c)) { case (in_b, pe) => pe.io.in_b := (if (tree_reduction) in_b.zero else in_b) pe.io.out_b } } // Broadcast 'd' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_d(c)) { case (in_d, pe) => pe.io.in_d := in_d pe.io.out_c } } // Broadcast 'control' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_control(c)) { case (in_ctrl, pe) => pe.io.in_control := in_ctrl pe.io.out_control } } // Broadcast 'garbage' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_valid(c)) { case (v, pe) => pe.io.in_valid := v pe.io.out_valid } } // Broadcast 'id' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_id(c)) { case (id, pe) => pe.io.in_id := id pe.io.out_id } } // Broadcast 'last' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_last(c)) { case (last, pe) => pe.io.in_last := last pe.io.out_last } } // Drive the Tile's bottom IO for (c <- 0 until columns) { io.out_c(c) := tile(rows-1)(c).io.out_c io.out_control(c) := tile(rows-1)(c).io.out_control io.out_id(c) := tile(rows-1)(c).io.out_id io.out_last(c) := tile(rows-1)(c).io.out_last io.out_valid(c) := tile(rows-1)(c).io.out_valid io.out_b(c) := { if (tree_reduction) { val prods = tileT(c).map(_.io.out_b) accumulateTree(prods :+ io.in_b(c)) } else { tile(rows - 1)(c).io.out_b } } } io.bad_dataflow := tile.map(_.map(_.io.bad_dataflow).reduce(_||_)).reduce(_||_) // Drive the Tile's right IO for (r <- 0 until rows) { io.out_a(r) := tile(r)(columns-1).io.out_a } }

module Tile_232( // @[Tile.scala:16:7] input clock, // @[Tile.scala:16:7] input reset, // @[Tile.scala:16:7] input [7:0] io_in_a_0, // @[Tile.scala:17:14] input [19:0] io_in_b_0, // @[Tile.scala:17:14] input [19:0] io_in_d_0, // @[Tile.scala:17:14] input io_in_control_0_dataflow, // @[Tile.scala:17:14] input io_in_control_0_propagate, // @[Tile.scala:17:14] input [4:0] io_in_control_0_shift, // @[Tile.scala:17:14] input [2:0] io_in_id_0, // @[Tile.scala:17:14] input io_in_last_0, // @[Tile.scala:17:14] output [7:0] io_out_a_0, // @[Tile.scala:17:14] output [19:0] io_out_c_0, // @[Tile.scala:17:14] output [19:0] io_out_b_0, // @[Tile.scala:17:14] output io_out_control_0_dataflow, // @[Tile.scala:17:14] output io_out_control_0_propagate, // @[Tile.scala:17:14] output [4:0] io_out_control_0_shift, // @[Tile.scala:17:14] output [2:0] io_out_id_0, // @[Tile.scala:17:14] output io_out_last_0, // @[Tile.scala:17:14] input io_in_valid_0, // @[Tile.scala:17:14] output io_out_valid_0 // @[Tile.scala:17:14] ); wire [7:0] io_in_a_0_0 = io_in_a_0; // @[Tile.scala:16:7] wire [19:0] io_in_b_0_0 = io_in_b_0; // @[Tile.scala:16:7] wire [19:0] io_in_d_0_0 = io_in_d_0; // @[Tile.scala:16:7] wire io_in_control_0_dataflow_0 = io_in_control_0_dataflow; // @[Tile.scala:16:7] wire io_in_control_0_propagate_0 = io_in_control_0_propagate; // @[Tile.scala:16:7] wire [4:0] io_in_control_0_shift_0 = io_in_control_0_shift; // @[Tile.scala:16:7] wire [2:0] io_in_id_0_0 = io_in_id_0; // @[Tile.scala:16:7] wire io_in_last_0_0 = io_in_last_0; // @[Tile.scala:16:7] wire io_in_valid_0_0 = io_in_valid_0; // @[Tile.scala:16:7] wire io_bad_dataflow = 1'h0; // @[Tile.scala:16:7, :17:14, :42:44] wire [7:0] io_out_a_0_0; // @[Tile.scala:16:7] wire [19:0] io_out_c_0_0; // @[Tile.scala:16:7] wire [19:0] io_out_b_0_0; // @[Tile.scala:16:7] wire io_out_control_0_dataflow_0; // @[Tile.scala:16:7] wire io_out_control_0_propagate_0; // @[Tile.scala:16:7] wire [4:0] io_out_control_0_shift_0; // @[Tile.scala:16:7] wire [2:0] io_out_id_0_0; // @[Tile.scala:16:7] wire io_out_last_0_0; // @[Tile.scala:16:7] wire io_out_valid_0_0; // @[Tile.scala:16:7] PE_488 tile_0_0 ( // @[Tile.scala:42:44] .clock (clock), .reset (reset), .io_in_a (io_in_a_0_0), // @[Tile.scala:16:7] .io_in_b (io_in_b_0_0), // @[Tile.scala:16:7] .io_in_d (io_in_d_0_0), // @[Tile.scala:16:7] .io_out_a (io_out_a_0_0), .io_out_b (io_out_b_0_0), .io_out_c (io_out_c_0_0), .io_in_control_dataflow (io_in_control_0_dataflow_0), // @[Tile.scala:16:7] .io_in_control_propagate (io_in_control_0_propagate_0), // @[Tile.scala:16:7] .io_in_control_shift (io_in_control_0_shift_0), // @[Tile.scala:16:7] .io_out_control_dataflow (io_out_control_0_dataflow_0), .io_out_control_propagate (io_out_control_0_propagate_0), .io_out_control_shift (io_out_control_0_shift_0), .io_in_id (io_in_id_0_0), // @[Tile.scala:16:7] .io_out_id (io_out_id_0_0), .io_in_last (io_in_last_0_0), // @[Tile.scala:16:7] .io_out_last (io_out_last_0_0), .io_in_valid (io_in_valid_0_0), // @[Tile.scala:16:7] .io_out_valid (io_out_valid_0_0) ); // @[Tile.scala:42:44] assign io_out_a_0 = io_out_a_0_0; // @[Tile.scala:16:7] assign io_out_c_0 = io_out_c_0_0; // @[Tile.scala:16:7] assign io_out_b_0 = io_out_b_0_0; // @[Tile.scala:16:7] assign io_out_control_0_dataflow = io_out_control_0_dataflow_0; // @[Tile.scala:16:7] assign io_out_control_0_propagate = io_out_control_0_propagate_0; // @[Tile.scala:16:7] assign io_out_control_0_shift = io_out_control_0_shift_0; // @[Tile.scala:16:7] assign io_out_id_0 = io_out_id_0_0; // @[Tile.scala:16:7] assign io_out_last_0 = io_out_last_0_0; // @[Tile.scala:16:7] assign io_out_valid_0 = io_out_valid_0_0; // @[Tile.scala:16:7] endmodule

Generate the Verilog code corresponding to the following Chisel files. File SynchronizerReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util.{RegEnable, Cat} /** These wrap behavioral * shift and next registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * * These are built up of *ResetSynchronizerPrimitiveShiftReg, * intended to be replaced by the integrator's metastable flops chains or replaced * at this level if they have a multi-bit wide synchronizer primitive. * The different types vary in their reset behavior: * NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin * AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep * 1-bit-wide shift registers. * SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg * * [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference. * * ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross * Clock Domains. */ object SynchronizerResetType extends Enumeration { val NonSync, Inferred, Sync, Async = Value } // Note: this should not be used directly. // Use the companion object to generate this with the correct reset type mixin. private class SynchronizerPrimitiveShiftReg( sync: Int, init: Boolean, resetType: SynchronizerResetType.Value) extends AbstractPipelineReg(1) { val initInt = if (init) 1 else 0 val initPostfix = resetType match { case SynchronizerResetType.NonSync => "" case _ => s"_i${initInt}" } override def desiredName = s"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}" val chain = List.tabulate(sync) { i => val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B) reg.suggestName(s"sync_$i") } chain.last := io.d.asBool (chain.init zip chain.tail).foreach { case (sink, source) => sink := source } io.q := chain.head.asUInt } private object SynchronizerPrimitiveShiftReg { def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = { val gen: () => SynchronizerPrimitiveShiftReg = resetType match { case SynchronizerResetType.NonSync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) case SynchronizerResetType.Async => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset case SynchronizerResetType.Sync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset case SynchronizerResetType.Inferred => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) } AbstractPipelineReg(gen(), in) } } // Note: This module may end up with a non-AsyncReset type reset. // But the Primitives within will always have AsyncReset type. class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asAsyncReset){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async) } } io.q := Cat(output.reverse) } object AsyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } // Note: This module may end up with a non-Bool type reset. // But the Primitives within will always have Bool reset type. @deprecated("SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.", "rocket-chip 1.2") class SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asBool){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync) } } io.q := Cat(output.reverse) } object SyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred) } io.q := Cat(output.reverse) } object ResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}" val output = Seq.tabulate(w) { i => SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync) } io.q := Cat(output.reverse) } object SynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, None) def apply [T <: Data](in: T): T = apply (in, 3, None) } class ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module { override def desiredName = s"ClockCrossingReg_w${w}" val io = IO(new Bundle{ val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) val en = Input(Bool()) }) val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en) io.q := cdc_reg } object ClockCrossingReg { def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = { val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit)) name.foreach{ cdc_reg.suggestName(_) } cdc_reg.io.d := in.asUInt cdc_reg.io.en := en cdc_reg.io.q.asTypeOf(in) } }

module ClockCrossingReg_w17( // @[SynchronizerReg.scala:191:7] input clock, // @[SynchronizerReg.scala:191:7] input reset, // @[SynchronizerReg.scala:191:7] input [16:0] io_d, // @[SynchronizerReg.scala:195:14] output [16:0] io_q, // @[SynchronizerReg.scala:195:14] input io_en // @[SynchronizerReg.scala:195:14] ); wire [16:0] io_d_0 = io_d; // @[SynchronizerReg.scala:191:7] wire io_en_0 = io_en; // @[SynchronizerReg.scala:191:7] wire [16:0] io_q_0; // @[SynchronizerReg.scala:191:7] reg [16:0] cdc_reg; // @[SynchronizerReg.scala:201:76] assign io_q_0 = cdc_reg; // @[SynchronizerReg.scala:191:7, :201:76] always @(posedge clock) begin // @[SynchronizerReg.scala:191:7] if (io_en_0) // @[SynchronizerReg.scala:191:7] cdc_reg <= io_d_0; // @[SynchronizerReg.scala:191:7, :201:76] always @(posedge) assign io_q = io_q_0; // @[SynchronizerReg.scala:191:7] endmodule

Generate the Verilog code corresponding to the following Chisel files. File EgressUnit.scala: package constellation.router import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.{Field, Parameters} import freechips.rocketchip.util._ import constellation.channel._ import constellation.routing.{FlowRoutingBundle} class EgressUnit(coupleSAVA: Boolean, combineSAST: Boolean, inParams: Seq[ChannelParams], ingressParams: Seq[IngressChannelParams], cParam: EgressChannelParams) (implicit p: Parameters) extends AbstractOutputUnit(inParams, ingressParams, cParam)(p) { class EgressUnitIO extends AbstractOutputUnitIO(inParams, ingressParams, cParam) { val out = Decoupled(new EgressFlit(cParam.payloadBits)) } val io = IO(new EgressUnitIO) val channel_empty = RegInit(true.B) val flow = Reg(new FlowRoutingBundle) val q = Module(new Queue(new EgressFlit(cParam.payloadBits), 3 - (if (combineSAST) 1 else 0), flow=true)) q.io.enq.valid := io.in(0).valid q.io.enq.bits.head := io.in(0).bits.head q.io.enq.bits.tail := io.in(0).bits.tail val flows = cParam.possibleFlows.toSeq if (flows.size == 0) { q.io.enq.bits.ingress_id := 0.U(1.W) } else { q.io.enq.bits.ingress_id := Mux1H( flows.map(f => (f.ingressNode.U === io.in(0).bits.flow.ingress_node && f.ingressNodeId.U === io.in(0).bits.flow.ingress_node_id)), flows.map(f => f.ingressId.U(ingressIdBits.W)) ) } q.io.enq.bits.payload := io.in(0).bits.payload io.out <> q.io.deq assert(!(q.io.enq.valid && !q.io.enq.ready)) io.credit_available(0) := q.io.count === 0.U io.channel_status(0).occupied := !channel_empty io.channel_status(0).flow := flow when (io.credit_alloc(0).alloc && io.credit_alloc(0).tail) { channel_empty := true.B if (coupleSAVA) io.channel_status(0).occupied := false.B } when (io.allocs(0).alloc) { channel_empty := false.B flow := io.allocs(0).flow } }

module EgressUnit_3( // @[EgressUnit.scala:12:7] input clock, // @[EgressUnit.scala:12:7] input reset, // @[EgressUnit.scala:12:7] input io_in_0_valid, // @[EgressUnit.scala:18:14] input io_in_0_bits_head, // @[EgressUnit.scala:18:14] input io_in_0_bits_tail, // @[EgressUnit.scala:18:14] input [72:0] io_in_0_bits_payload, // @[EgressUnit.scala:18:14] input [3:0] io_in_0_bits_flow_ingress_node, // @[EgressUnit.scala:18:14] input [1:0] io_in_0_bits_flow_ingress_node_id, // @[EgressUnit.scala:18:14] output io_credit_available_0, // @[EgressUnit.scala:18:14] output io_channel_status_0_occupied, // @[EgressUnit.scala:18:14] input io_allocs_0_alloc, // @[EgressUnit.scala:18:14] input io_credit_alloc_0_alloc, // @[EgressUnit.scala:18:14] input io_credit_alloc_0_tail, // @[EgressUnit.scala:18:14] input io_out_ready, // @[EgressUnit.scala:18:14] output io_out_valid, // @[EgressUnit.scala:18:14] output io_out_bits_head, // @[EgressUnit.scala:18:14] output io_out_bits_tail, // @[EgressUnit.scala:18:14] output [72:0] io_out_bits_payload // @[EgressUnit.scala:18:14] ); wire _q_io_enq_ready; // @[EgressUnit.scala:22:17] wire [1:0] _q_io_count; // @[EgressUnit.scala:22:17] reg channel_empty; // @[EgressUnit.scala:20:30] wire _q_io_enq_bits_ingress_id_T_10 = io_in_0_bits_flow_ingress_node_id == 2'h0; // @[EgressUnit.scala:32:27]

Generate the Verilog code corresponding to the following Chisel files. File Monitor.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceLine import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import freechips.rocketchip.diplomacy.EnableMonitors import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode} import freechips.rocketchip.util.PlusArg case class TLMonitorArgs(edge: TLEdge) abstract class TLMonitorBase(args: TLMonitorArgs) extends Module { val io = IO(new Bundle { val in = Input(new TLBundle(args.edge.bundle)) }) def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit legalize(io.in, args.edge, reset) } object TLMonitor { def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = { if (enable) { EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) } } else { node } } } class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args) { require (args.edge.params(TLMonitorStrictMode) || (! args.edge.params(TestplanTestType).formal)) val cover_prop_class = PropertyClass.Default //Like assert but can flip to being an assumption for formal verification def monAssert(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir, cond, message, PropertyClass.Default) } def assume(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir.flip, cond, message, PropertyClass.Default) } def extra = { args.edge.sourceInfo match { case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)" case _ => "" } } def visible(address: UInt, source: UInt, edge: TLEdge) = edge.client.clients.map { c => !c.sourceId.contains(source) || c.visibility.map(_.contains(address)).reduce(_ || _) }.reduce(_ && _) def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = { //switch this flag to turn on diplomacy in error messages def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n" monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra) // Reuse these subexpressions to save some firrtl lines val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility") //The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B //TODO: check for acquireT? when (bundle.opcode === TLMessages.AcquireBlock) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra) } when (bundle.opcode === TLMessages.AcquirePerm) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra) monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra) monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra) monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra) } } def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = { monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra) monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility") // Reuse these subexpressions to save some firrtl lines val address_ok = edge.manager.containsSafe(edge.address(bundle)) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source when (bundle.opcode === TLMessages.Probe) { assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra) assume (address_ok, "'B' channel Probe carries unmanaged address" + extra) assume (legal_source, "'B' channel Probe carries source that is not first source" + extra) assume (is_aligned, "'B' channel Probe address not aligned to size" + extra) assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra) assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra) assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra) monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra) monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra) monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra) monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra) } } def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = { monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val address_ok = edge.manager.containsSafe(edge.address(bundle)) monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility") when (bundle.opcode === TLMessages.ProbeAck) { monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra) } when (bundle.opcode === TLMessages.ProbeAckData) { monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.Release) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra) monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra) } when (bundle.opcode === TLMessages.ReleaseData) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.AccessAck) { monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra) } when (bundle.opcode === TLMessages.HintAck) { monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra) } } def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = { assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val sink_ok = bundle.sink < edge.manager.endSinkId.U val deny_put_ok = edge.manager.mayDenyPut.B val deny_get_ok = edge.manager.mayDenyGet.B when (bundle.opcode === TLMessages.ReleaseAck) { assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra) assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra) assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra) } when (bundle.opcode === TLMessages.Grant) { assume (source_ok, "'D' channel Grant carries invalid source ID" + extra) assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra) assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel Grant is denied" + extra) } when (bundle.opcode === TLMessages.GrantData) { assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra) assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra) assume (!bundle.denied || bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra) assume (deny_get_ok || !bundle.denied, "'D' channel GrantData is denied" + extra) } when (bundle.opcode === TLMessages.AccessAck) { assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel AccessAck is denied" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra) assume (!bundle.denied || bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra) assume (deny_get_ok || !bundle.denied, "'D' channel AccessAckData is denied" + extra) } when (bundle.opcode === TLMessages.HintAck) { assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel HintAck is denied" + extra) } } def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = { val sink_ok = bundle.sink < edge.manager.endSinkId.U monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra) } def legalizeFormat(bundle: TLBundle, edge: TLEdge) = { when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) } when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) } when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) } when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) } } else { monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra) monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra) monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra) } } def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = { val a_first = edge.first(a.bits, a.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (a.valid && !a_first) { monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra) monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra) monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra) monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra) monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra) } when (a.fire && a_first) { opcode := a.bits.opcode param := a.bits.param size := a.bits.size source := a.bits.source address := a.bits.address } } def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = { val b_first = edge.first(b.bits, b.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (b.valid && !b_first) { monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra) monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra) monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra) monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra) monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra) } when (b.fire && b_first) { opcode := b.bits.opcode param := b.bits.param size := b.bits.size source := b.bits.source address := b.bits.address } } def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = { // Symbolic variable val sym_source = Wire(UInt(edge.client.endSourceId.W)) // TODO: Connect sym_source to a fixed value for simulation and to a // free wire in formal sym_source := 0.U // Type casting Int to UInt val maxSourceId = Wire(UInt(edge.client.endSourceId.W)) maxSourceId := edge.client.endSourceId.U // Delayed verison of sym_source val sym_source_d = Reg(UInt(edge.client.endSourceId.W)) sym_source_d := sym_source // These will be constraints for FV setup Property( MonitorDirection.Monitor, (sym_source === sym_source_d), "sym_source should remain stable", PropertyClass.Default) Property( MonitorDirection.Monitor, (sym_source <= maxSourceId), "sym_source should take legal value", PropertyClass.Default) val my_resp_pend = RegInit(false.B) val my_opcode = Reg(UInt()) val my_size = Reg(UInt()) val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire) val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire) val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source) val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source) val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat) val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend) when (my_set_resp_pend) { my_resp_pend := true.B } .elsewhen (my_clr_resp_pend) { my_resp_pend := false.B } when (my_a_first_beat) { my_opcode := bundle.a.bits.opcode my_size := bundle.a.bits.size } val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size) val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode) val my_resp_opcode_legal = Wire(Bool()) when ((my_resp_opcode === TLMessages.Get) || (my_resp_opcode === TLMessages.ArithmeticData) || (my_resp_opcode === TLMessages.LogicalData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData) } .elsewhen ((my_resp_opcode === TLMessages.PutFullData) || (my_resp_opcode === TLMessages.PutPartialData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck) } .otherwise { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck) } monAssert (IfThen(my_resp_pend, !my_a_first_beat), "Request message should not be sent with a source ID, for which a response message" + "is already pending (not received until current cycle) for a prior request message" + "with the same source ID" + extra) assume (IfThen(my_clr_resp_pend, (my_set_resp_pend || my_resp_pend)), "Response message should be accepted with a source ID only if a request message with the" + "same source ID has been accepted or is being accepted in the current cycle" + extra) assume (IfThen(my_d_first_beat, (my_a_first_beat || my_resp_pend)), "Response message should be sent with a source ID only if a request message with the" + "same source ID has been accepted or is being sent in the current cycle" + extra) assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)), "If d_valid is 1, then d_size should be same as a_size of the corresponding request" + "message" + extra) assume (IfThen(my_d_first_beat, my_resp_opcode_legal), "If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" + "request message" + extra) } def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = { val c_first = edge.first(c.bits, c.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (c.valid && !c_first) { monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra) monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra) monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra) monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra) monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra) } when (c.fire && c_first) { opcode := c.bits.opcode param := c.bits.param size := c.bits.size source := c.bits.source address := c.bits.address } } def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = { val d_first = edge.first(d.bits, d.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val sink = Reg(UInt()) val denied = Reg(Bool()) when (d.valid && !d_first) { assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra) assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra) assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra) assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra) assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra) assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra) } when (d.fire && d_first) { opcode := d.bits.opcode param := d.bits.param size := d.bits.size source := d.bits.source sink := d.bits.sink denied := d.bits.denied } } def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = { legalizeMultibeatA(bundle.a, edge) legalizeMultibeatD(bundle.d, edge) if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { legalizeMultibeatB(bundle.b, edge) legalizeMultibeatC(bundle.c, edge) } } //This is left in for almond which doesn't adhere to the tilelink protocol @deprecated("Use legalizeADSource instead if possible","") def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.client.endSourceId.W)) val a_first = edge.first(bundle.a.bits, bundle.a.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val a_set = WireInit(0.U(edge.client.endSourceId.W)) when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) assume((a_set | inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra) } if (edge.manager.minLatency > 0) { assume(a_set =/= d_clr || !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight | a_set) & ~d_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") assert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = { val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size) val log_a_size_bus_size = log2Ceil(a_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error inflight.suggestName("inflight") val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) inflight_opcodes.suggestName("inflight_opcodes") val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) inflight_sizes.suggestName("inflight_sizes") val a_first = edge.first(bundle.a.bits, bundle.a.fire) a_first.suggestName("a_first") val d_first = edge.first(bundle.d.bits, bundle.d.fire) d_first.suggestName("d_first") val a_set = WireInit(0.U(edge.client.endSourceId.W)) val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) a_set.suggestName("a_set") a_set_wo_ready.suggestName("a_set_wo_ready") val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) a_opcodes_set.suggestName("a_opcodes_set") val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) a_sizes_set.suggestName("a_sizes_set") val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W)) a_opcode_lookup.suggestName("a_opcode_lookup") a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W)) a_size_lookup.suggestName("a_size_lookup") a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant)) val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant)) val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W)) a_opcodes_set_interm.suggestName("a_opcodes_set_interm") val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W)) a_sizes_set_interm.suggestName("a_sizes_set_interm") when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) { a_set_wo_ready := UIntToOH(bundle.a.bits.source) } when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) | 1.U a_sizes_set_interm := (bundle.a.bits.size << 1.U) | 1.U a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U) a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U) monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) d_opcodes_clr.suggestName("d_opcodes_clr") val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) || (bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra) assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) || (bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra) assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) { assume((!bundle.d.ready) || bundle.a.ready, "ready check") } if (edge.manager.minLatency > 0) { assume(a_set_wo_ready =/= d_clr_wo_ready || !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight | a_set) & ~d_clr inflight_opcodes := (inflight_opcodes | a_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes | a_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = { val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size) val log_c_size_bus_size = log2Ceil(c_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) inflight.suggestName("inflight") inflight_opcodes.suggestName("inflight_opcodes") inflight_sizes.suggestName("inflight_sizes") val c_first = edge.first(bundle.c.bits, bundle.c.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) c_first.suggestName("c_first") d_first.suggestName("d_first") val c_set = WireInit(0.U(edge.client.endSourceId.W)) val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) c_set.suggestName("c_set") c_set_wo_ready.suggestName("c_set_wo_ready") c_opcodes_set.suggestName("c_opcodes_set") c_sizes_set.suggestName("c_sizes_set") val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W)) val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W)) c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U c_opcode_lookup.suggestName("c_opcode_lookup") c_size_lookup.suggestName("c_size_lookup") val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W)) val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W)) c_opcodes_set_interm.suggestName("c_opcodes_set_interm") c_sizes_set_interm.suggestName("c_sizes_set_interm") when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) { c_set_wo_ready := UIntToOH(bundle.c.bits.source) } when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) { c_set := UIntToOH(bundle.c.bits.source) c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) | 1.U c_sizes_set_interm := (bundle.c.bits.size << 1.U) | 1.U c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U) c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U) monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra) } val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck || bundle.c.bits.opcode === TLMessages.ProbeAckData val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") d_opcodes_clr.suggestName("d_opcodes_clr") d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) { assume((!bundle.d.ready) || bundle.c.ready, "ready check") } if (edge.manager.minLatency > 0) { when (c_set_wo_ready.orR) { assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra) } } inflight := (inflight | c_set) & ~d_clr inflight_opcodes := (inflight_opcodes | c_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes | c_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.c.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.manager.endSinkId.W)) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val e_first = true.B val d_set = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) { d_set := UIntToOH(bundle.d.bits.sink) assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra) } val e_clr = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) { e_clr := UIntToOH(bundle.e.bits.sink) monAssert((d_set | inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra) } // edge.client.minLatency applies to BC, not DE inflight := (inflight | d_set) & ~e_clr } def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = { val sourceBits = log2Ceil(edge.client.endSourceId) val tooBig = 14 // >16kB worth of flight information gets to be too much if (sourceBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked") } else { if (args.edge.params(TestplanTestType).simulation) { if (args.edge.params(TLMonitorStrictMode)) { legalizeADSource(bundle, edge) legalizeCDSource(bundle, edge) } else { legalizeADSourceOld(bundle, edge) } } if (args.edge.params(TestplanTestType).formal) { legalizeADSourceFormal(bundle, edge) } } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { // legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize... val sinkBits = log2Ceil(edge.manager.endSinkId) if (sinkBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked") } else { legalizeDESink(bundle, edge) } } } def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = { legalizeFormat (bundle, edge) legalizeMultibeat (bundle, edge) legalizeUnique (bundle, edge) } } File Misc.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import scala.math._ class ParameterizedBundle(implicit p: Parameters) extends Bundle trait Clocked extends Bundle { val clock = Clock() val reset = Bool() } object DecoupledHelper { def apply(rvs: Bool*) = new DecoupledHelper(rvs) } class DecoupledHelper(val rvs: Seq[Bool]) { def fire(exclude: Bool, includes: Bool*) = { require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!") (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _) } def fire() = { rvs.reduce(_ && _) } } object MuxT { def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2)) def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3)) def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4)) } /** Creates a cascade of n MuxTs to search for a key value. */ object MuxTLookup { def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } } object ValidMux { def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]*): ValidIO[T] = { apply(v1 +: v2.toSeq) } def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = { val out = Wire(Valid(valids.head.bits.cloneType)) out.valid := valids.map(_.valid).reduce(_ || _) out.bits := MuxCase(valids.head.bits, valids.map(v => (v.valid -> v.bits))) out } } object Str { def apply(s: String): UInt = { var i = BigInt(0) require(s.forall(validChar _)) for (c <- s) i = (i << 8) | c i.U((s.length*8).W) } def apply(x: Char): UInt = { require(validChar(x)) x.U(8.W) } def apply(x: UInt): UInt = apply(x, 10) def apply(x: UInt, radix: Int): UInt = { val rad = radix.U val w = x.getWidth require(w > 0) var q = x var s = digit(q % rad) for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s) } s } def apply(x: SInt): UInt = apply(x, 10) def apply(x: SInt, radix: Int): UInt = { val neg = x < 0.S val abs = x.abs.asUInt if (radix != 10) { Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix)) } else { val rad = radix.U val w = abs.getWidth require(w > 0) var q = abs var s = digit(q % rad) var needSign = neg for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad val placeSpace = q === 0.U val space = Mux(needSign, Str('-'), Str(' ')) needSign = needSign && !placeSpace s = Cat(Mux(placeSpace, space, digit(q % rad)), s) } Cat(Mux(needSign, Str('-'), Str(' ')), s) } } private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0) private def validChar(x: Char) = x == (x & 0xFF) } object Split { def apply(x: UInt, n0: Int) = { val w = x.getWidth (x.extract(w-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n2: Int, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } } object Random { def apply(mod: Int, random: UInt): UInt = { if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0) else PriorityEncoder(partition(apply(1 << log2Up(mod*8), random), mod)) } def apply(mod: Int): UInt = apply(mod, randomizer) def oneHot(mod: Int, random: UInt): UInt = { if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0)) else PriorityEncoderOH(partition(apply(1 << log2Up(mod*8), random), mod)).asUInt } def oneHot(mod: Int): UInt = oneHot(mod, randomizer) private def randomizer = LFSR(16) private def partition(value: UInt, slices: Int) = Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U) } object Majority { def apply(in: Set[Bool]): Bool = { val n = (in.size >> 1) + 1 val clauses = in.subsets(n).map(_.reduce(_ && _)) clauses.reduce(_ || _) } def apply(in: Seq[Bool]): Bool = apply(in.toSet) def apply(in: UInt): Bool = apply(in.asBools.toSet) } object PopCountAtLeast { private def two(x: UInt): (Bool, Bool) = x.getWidth match { case 1 => (x.asBool, false.B) case n => val half = x.getWidth / 2 val (leftOne, leftTwo) = two(x(half - 1, 0)) val (rightOne, rightTwo) = two(x(x.getWidth - 1, half)) (leftOne || rightOne, leftTwo || rightTwo || (leftOne && rightOne)) } def apply(x: UInt, n: Int): Bool = n match { case 0 => true.B case 1 => x.orR case 2 => two(x)._2 case 3 => PopCount(x) >= n.U } } // This gets used everywhere, so make the smallest circuit possible ... // Given an address and size, create a mask of beatBytes size // eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111 // groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01 object MaskGen { def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = { require (groupBy >= 1 && beatBytes >= groupBy) require (isPow2(beatBytes) && isPow2(groupBy)) val lgBytes = log2Ceil(beatBytes) val sizeOH = UIntToOH(lgSize | 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) | (groupBy*2 - 1).U def helper(i: Int): Seq[(Bool, Bool)] = { if (i == 0) { Seq((lgSize >= lgBytes.asUInt, true.B)) } else { val sub = helper(i-1) val size = sizeOH(lgBytes - i) val bit = addr_lo(lgBytes - i) val nbit = !bit Seq.tabulate (1 << i) { j => val (sub_acc, sub_eq) = sub(j/2) val eq = sub_eq && (if (j % 2 == 1) bit else nbit) val acc = sub_acc || (size && eq) (acc, eq) } } } if (groupBy == beatBytes) 1.U else Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse) } } File PlusArg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.experimental._ import chisel3.util.HasBlackBoxResource @deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05") case class PlusArgInfo(default: BigInt, docstring: String) /** Case class for PlusArg information * * @tparam A scala type of the PlusArg value * @param default optional default value * @param docstring text to include in the help * @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT) */ private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String) /** Typeclass for converting a type to a doctype string * @tparam A some type */ trait Doctypeable[A] { /** Return the doctype string for some option */ def toDoctype(a: Option[A]): String } /** Object containing implementations of the Doctypeable typeclass */ object Doctypes { /** Converts an Int => "INT" */ implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" } /** Converts a BigInt => "INT" */ implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" } /** Converts a String => "STRING" */ implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" } } class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map( "FORMAT" -> StringParam(format), "DEFAULT" -> IntParam(default), "WIDTH" -> IntParam(width) )) with HasBlackBoxResource { val io = IO(new Bundle { val out = Output(UInt(width.W)) }) addResource("/vsrc/plusarg_reader.v") } /* This wrapper class has no outputs, making it clear it is a simulation-only construct */ class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module { val io = IO(new Bundle { val count = Input(UInt(width.W)) }) val max = Module(new plusarg_reader(format, default, docstring, width)).io.out when (max > 0.U) { assert (io.count < max, s"Timeout exceeded: $docstring") } } import Doctypes._ object PlusArg { /** PlusArg("foo") will return 42.U if the simulation is run with +foo=42 * Do not use this as an initial register value. The value is set in an * initial block and thus accessing it from another initial is racey. * Add a docstring to document the arg, which can be dumped in an elaboration * pass. */ def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out } /** PlusArg.timeout(name, default, docstring)(count) will use chisel.assert * to kill the simulation when count exceeds the specified integer argument. * Default 0 will never assert. */ def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count } } object PlusArgArtefacts { private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty /* Add a new PlusArg */ @deprecated( "Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05" ) def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring) /** Add a new PlusArg * * @tparam A scala type of the PlusArg value * @param name name for the PlusArg * @param default optional default value * @param docstring text to include in the help */ def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit = artefacts = artefacts ++ Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default))) /* From plus args, generate help text */ private def serializeHelp_cHeader(tab: String = ""): String = artefacts .map{ case(arg, info) => s"""|$tab+$arg=${info.doctype}\\n\\ |$tab${" "*20}${info.docstring}\\n\\ |""".stripMargin ++ info.default.map{ case default => s"$tab${" "*22}(default=${default})\\n\\\n"}.getOrElse("") }.toSeq.mkString("\\n\\\n") ++ "\"" /* From plus args, generate a char array of their names */ private def serializeArray_cHeader(tab: String = ""): String = { val prettyTab = tab + " " * 44 // Length of 'static const ...' s"${tab}static const char * verilog_plusargs [] = {\\\n" ++ artefacts .map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" } .mkString("")++ s"${prettyTab}0};" } /* Generate C code to be included in emulator.cc that helps with * argument parsing based on available Verilog PlusArgs */ def serialize_cHeader(): String = s"""|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\ |${serializeHelp_cHeader(" "*7)} |${serializeArray_cHeader()} |""".stripMargin } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /** Like Vec.apply(idx), but tolerates indices of mismatched width */ def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /** Any Data subtype that has a Bool member named valid. */ type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /** converts from camel case to to underscores, also removing all spaces */ def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /** converts spaces or underscores to hyphens, also lowering case */ def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y | (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y || y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /** Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation */ def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.diplomacy import chisel3._ import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor} import freechips.rocketchip.util.ShiftQueue /** Options for describing the attributes of memory regions */ object RegionType { // Define the 'more relaxed than' ordering val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS) sealed trait T extends Ordered[T] { def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this) } case object CACHED extends T // an intermediate agent may have cached a copy of the region for you case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively } // A non-empty half-open range; [start, end) case class IdRange(start: Int, end: Int) extends Ordered[IdRange] { require (start >= 0, s"Ids cannot be negative, but got: $start.") require (start <= end, "Id ranges cannot be negative.") def compare(x: IdRange) = { val primary = (this.start - x.start).signum val secondary = (x.end - this.end).signum if (primary != 0) primary else secondary } def overlaps(x: IdRange) = start < x.end && x.start < end def contains(x: IdRange) = start <= x.start && x.end <= end def contains(x: Int) = start <= x && x < end def contains(x: UInt) = if (size == 0) { false.B } else if (size == 1) { // simple comparison x === start.U } else { // find index of largest different bit val largestDeltaBit = log2Floor(start ^ (end-1)) val smallestCommonBit = largestDeltaBit + 1 // may not exist in x val uncommonMask = (1 << smallestCommonBit) - 1 val uncommonBits = (x | 0.U(smallestCommonBit.W))(largestDeltaBit, 0) // the prefix must match exactly (note: may shift ALL bits away) (x >> smallestCommonBit) === (start >> smallestCommonBit).U && // firrtl constant prop range analysis can eliminate these two: (start & uncommonMask).U <= uncommonBits && uncommonBits <= ((end-1) & uncommonMask).U } def shift(x: Int) = IdRange(start+x, end+x) def size = end - start def isEmpty = end == start def range = start until end } object IdRange { def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else { val ranges = s.sorted (ranges.tail zip ranges.init) find { case (a, b) => a overlaps b } } } // An potentially empty inclusive range of 2-powers [min, max] (in bytes) case class TransferSizes(min: Int, max: Int) { def this(x: Int) = this(x, x) require (min <= max, s"Min transfer $min > max transfer $max") require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)") require (max == 0 || isPow2(max), s"TransferSizes must be a power of 2, got: $max") require (min == 0 || isPow2(min), s"TransferSizes must be a power of 2, got: $min") require (max == 0 || min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)") def none = min == 0 def contains(x: Int) = isPow2(x) && min <= x && x <= max def containsLg(x: Int) = contains(1 << x) def containsLg(x: UInt) = if (none) false.B else if (min == max) { log2Ceil(min).U === x } else { log2Ceil(min).U <= x && x <= log2Ceil(max).U } def contains(x: TransferSizes) = x.none || (min <= x.min && x.max <= max) def intersect(x: TransferSizes) = if (x.max < min || max < x.min) TransferSizes.none else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max)) // Not a union, because the result may contain sizes contained by neither term // NOT TO BE CONFUSED WITH COVERPOINTS def mincover(x: TransferSizes) = { if (none) { x } else if (x.none) { this } else { TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max)) } } override def toString() = "TransferSizes[%d, %d]".format(min, max) } object TransferSizes { def apply(x: Int) = new TransferSizes(x) val none = new TransferSizes(0) def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _) def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _) implicit def asBool(x: TransferSizes) = !x.none } // AddressSets specify the address space managed by the manager // Base is the base address, and mask are the bits consumed by the manager // e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff // e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ... case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet] { // Forbid misaligned base address (and empty sets) require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}") require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous // We do allow negative mask (=> ignore all high bits) def contains(x: BigInt) = ((x ^ base) & ~mask) == 0 def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S // turn x into an address contained in this set def legalize(x: UInt): UInt = base.U | (mask.U & x) // overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1) def overlaps(x: AddressSet) = (~(mask | x.mask) & (base ^ x.base)) == 0 // contains iff bitwise: x.mask => mask && contains(x.base) def contains(x: AddressSet) = ((x.mask | (base ^ x.base)) & ~mask) == 0 // The number of bytes to which the manager must be aligned def alignment = ((mask + 1) & ~mask) // Is this a contiguous memory range def contiguous = alignment == mask+1 def finite = mask >= 0 def max = { require (finite, "Max cannot be calculated on infinite mask"); base | mask } // Widen the match function to ignore all bits in imask def widen(imask: BigInt) = AddressSet(base & ~imask, mask | imask) // Return an AddressSet that only contains the addresses both sets contain def intersect(x: AddressSet): Option[AddressSet] = { if (!overlaps(x)) { None } else { val r_mask = mask & x.mask val r_base = base | x.base Some(AddressSet(r_base, r_mask)) } } def subtract(x: AddressSet): Seq[AddressSet] = { intersect(x) match { case None => Seq(this) case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit => val nmask = (mask & (bit-1)) | remove.mask val nbase = (remove.base ^ bit) & ~nmask AddressSet(nbase, nmask) } } } // AddressSets have one natural Ordering (the containment order, if contiguous) def compare(x: AddressSet) = { val primary = (this.base - x.base).signum // smallest address first val secondary = (x.mask - this.mask).signum // largest mask first if (primary != 0) primary else secondary } // We always want to see things in hex override def toString() = { if (mask >= 0) { "AddressSet(0x%x, 0x%x)".format(base, mask) } else { "AddressSet(0x%x, ~0x%x)".format(base, ~mask) } } def toRanges = { require (finite, "Ranges cannot be calculated on infinite mask") val size = alignment val fragments = mask & ~(size-1) val bits = bitIndexes(fragments) (BigInt(0) until (BigInt(1) << bits.size)).map { i => val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) } AddressRange(off, size) } } } object AddressSet { val everything = AddressSet(0, -1) def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = { if (size == 0) tail.reverse else { val maxBaseAlignment = base & (-base) // 0 for infinite (LSB) val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size val step = if (maxBaseAlignment == 0 || maxBaseAlignment > maxSizeAlignment) maxSizeAlignment else maxBaseAlignment misaligned(base+step, size-step, AddressSet(base, step-1) +: tail) } } def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = { // Pair terms up by ignoring 'bit' seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) => if (seq.size == 1) { seq.head // singleton -> unaffected } else { key.copy(mask = key.mask | bit) // pair - widen mask by bit } }.toList } def unify(seq: Seq[AddressSet]): Seq[AddressSet] = { val bits = seq.map(_.base).foldLeft(BigInt(0))(_ | _) AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted } def enumerateMask(mask: BigInt): Seq[BigInt] = { def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] = if (id == mask) (id +: tail).reverse else helper(((~mask | id) + 1) & mask, id +: tail) helper(0, Nil) } def enumerateBits(mask: BigInt): Seq[BigInt] = { def helper(x: BigInt): Seq[BigInt] = { if (x == 0) { Nil } else { val bit = x & (-x) bit +: helper(x & ~bit) } } helper(mask) } } case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean) { require (depth >= 0, "Buffer depth must be >= 0") def isDefined = depth > 0 def latency = if (isDefined && !flow) 1 else 0 def apply[T <: Data](x: DecoupledIO[T]) = if (isDefined) Queue(x, depth, flow=flow, pipe=pipe) else x def irrevocable[T <: Data](x: ReadyValidIO[T]) = if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe) else x def sq[T <: Data](x: DecoupledIO[T]) = if (!isDefined) x else { val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe)) sq.io.enq <> x sq.io.deq } override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "") } object BufferParams { implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false) val default = BufferParams(2) val none = BufferParams(0) val flow = BufferParams(1, true, false) val pipe = BufferParams(1, false, true) } case class TriStateValue(value: Boolean, set: Boolean) { def update(orig: Boolean) = if (set) value else orig } object TriStateValue { implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true) def unset = TriStateValue(false, false) } trait DirectedBuffers[T] { def copyIn(x: BufferParams): T def copyOut(x: BufferParams): T def copyInOut(x: BufferParams): T } trait IdMapEntry { def name: String def from: IdRange def to: IdRange def isCache: Boolean def requestFifo: Boolean def maxTransactionsInFlight: Option[Int] def pretty(fmt: String) = if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5 fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } else { fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } } abstract class IdMap[T <: IdMapEntry] { protected val fmt: String val mapping: Seq[T] def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n") } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) || !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.ProbeAckData || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode | small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U || beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }

module TLMonitor_9( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [1:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [10:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [12:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [10:0] io_in_d_bits_source // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire a_first_done = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala:51:35] reg a_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [1:0] size; // @[Monitor.scala:389:22] reg [10:0] source; // @[Monitor.scala:390:22] reg [12:0] address; // @[Monitor.scala:391:22] reg d_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] size_1; // @[Monitor.scala:540:22] reg [10:0] source_1; // @[Monitor.scala:541:22] reg [1039:0] inflight; // @[Monitor.scala:614:27] reg [4159:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [4159:0] inflight_sizes; // @[Monitor.scala:618:33] reg a_first_counter_1; // @[Edges.scala:229:27] reg d_first_counter_1; // @[Edges.scala:229:27] wire _GEN = a_first_done & ~a_first_counter_1; // @[Decoupled.scala:51:35] wire d_release_ack = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala:673:46] wire _GEN_0 = io_in_d_bits_opcode != 3'h6; // @[Monitor.scala:673:46, :674:74] reg [31:0] watchdog; // @[Monitor.scala:709:27] reg [1039:0] inflight_1; // @[Monitor.scala:726:35] reg [4159:0] inflight_sizes_1; // @[Monitor.scala:728:35] reg d_first_counter_2; // @[Edges.scala:229:27] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]

Generate the Verilog code corresponding to the following Chisel files. File InputUnit.scala: package constellation.router import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.{Field, Parameters} import freechips.rocketchip.util._ import constellation.channel._ import constellation.routing.{FlowRoutingBundle} import constellation.noc.{HasNoCParams} class AbstractInputUnitIO( val cParam: BaseChannelParams, val outParams: Seq[ChannelParams], val egressParams: Seq[EgressChannelParams], )(implicit val p: Parameters) extends Bundle with HasRouterOutputParams { val nodeId = cParam.destId val router_req = Decoupled(new RouteComputerReq) val router_resp = Input(new RouteComputerResp(outParams, egressParams)) val vcalloc_req = Decoupled(new VCAllocReq(cParam, outParams, egressParams)) val vcalloc_resp = Input(new VCAllocResp(outParams, egressParams)) val out_credit_available = Input(MixedVec(allOutParams.map { u => Vec(u.nVirtualChannels, Bool()) })) val salloc_req = Vec(cParam.destSpeedup, Decoupled(new SwitchAllocReq(outParams, egressParams))) val out = Vec(cParam.destSpeedup, Valid(new SwitchBundle(outParams, egressParams))) val debug = Output(new Bundle { val va_stall = UInt(log2Ceil(cParam.nVirtualChannels).W) val sa_stall = UInt(log2Ceil(cParam.nVirtualChannels).W) }) val block = Input(Bool()) } abstract class AbstractInputUnit( val cParam: BaseChannelParams, val outParams: Seq[ChannelParams], val egressParams: Seq[EgressChannelParams] )(implicit val p: Parameters) extends Module with HasRouterOutputParams with HasNoCParams { val nodeId = cParam.destId def io: AbstractInputUnitIO } class InputBuffer(cParam: ChannelParams)(implicit p: Parameters) extends Module { val nVirtualChannels = cParam.nVirtualChannels val io = IO(new Bundle { val enq = Flipped(Vec(cParam.srcSpeedup, Valid(new Flit(cParam.payloadBits)))) val deq = Vec(cParam.nVirtualChannels, Decoupled(new BaseFlit(cParam.payloadBits))) }) val useOutputQueues = cParam.useOutputQueues val delims = if (useOutputQueues) { cParam.virtualChannelParams.map(u => if (u.traversable) u.bufferSize else 0).scanLeft(0)(_+_) } else { // If no queuing, have to add an additional slot since head == tail implies empty // TODO this should be fixed, should use all slots available cParam.virtualChannelParams.map(u => if (u.traversable) u.bufferSize + 1 else 0).scanLeft(0)(_+_) } val starts = delims.dropRight(1).zipWithIndex.map { case (s,i) => if (cParam.virtualChannelParams(i).traversable) s else 0 } val ends = delims.tail.zipWithIndex.map { case (s,i) => if (cParam.virtualChannelParams(i).traversable) s else 0 } val fullSize = delims.last // Ugly case. Use multiple queues if ((cParam.srcSpeedup > 1 || cParam.destSpeedup > 1 || fullSize <= 1) || !cParam.unifiedBuffer) { require(useOutputQueues) val qs = cParam.virtualChannelParams.map(v => Module(new Queue(new BaseFlit(cParam.payloadBits), v.bufferSize))) qs.zipWithIndex.foreach { case (q,i) => val sel = io.enq.map(f => f.valid && f.bits.virt_channel_id === i.U) q.io.enq.valid := sel.orR q.io.enq.bits.head := Mux1H(sel, io.enq.map(_.bits.head)) q.io.enq.bits.tail := Mux1H(sel, io.enq.map(_.bits.tail)) q.io.enq.bits.payload := Mux1H(sel, io.enq.map(_.bits.payload)) io.deq(i) <> q.io.deq } } else { val mem = Mem(fullSize, new BaseFlit(cParam.payloadBits)) val heads = RegInit(VecInit(starts.map(_.U(log2Ceil(fullSize).W)))) val tails = RegInit(VecInit(starts.map(_.U(log2Ceil(fullSize).W)))) val empty = (heads zip tails).map(t => t._1 === t._2) val qs = Seq.fill(nVirtualChannels) { Module(new Queue(new BaseFlit(cParam.payloadBits), 1, pipe=true)) } qs.foreach(_.io.enq.valid := false.B) qs.foreach(_.io.enq.bits := DontCare) val vc_sel = UIntToOH(io.enq(0).bits.virt_channel_id) val flit = Wire(new BaseFlit(cParam.payloadBits)) val direct_to_q = (Mux1H(vc_sel, qs.map(_.io.enq.ready)) && Mux1H(vc_sel, empty)) && useOutputQueues.B flit.head := io.enq(0).bits.head flit.tail := io.enq(0).bits.tail flit.payload := io.enq(0).bits.payload when (io.enq(0).valid && !direct_to_q) { val tail = tails(io.enq(0).bits.virt_channel_id) mem.write(tail, flit) tails(io.enq(0).bits.virt_channel_id) := Mux( tail === Mux1H(vc_sel, ends.map(_ - 1).map(_ max 0).map(_.U)), Mux1H(vc_sel, starts.map(_.U)), tail + 1.U) } .elsewhen (io.enq(0).valid && direct_to_q) { for (i <- 0 until nVirtualChannels) { when (io.enq(0).bits.virt_channel_id === i.U) { qs(i).io.enq.valid := true.B qs(i).io.enq.bits := flit } } } if (useOutputQueues) { val can_to_q = (0 until nVirtualChannels).map { i => !empty(i) && qs(i).io.enq.ready } val to_q_oh = PriorityEncoderOH(can_to_q) val to_q = OHToUInt(to_q_oh) when (can_to_q.orR) { val head = Mux1H(to_q_oh, heads) heads(to_q) := Mux( head === Mux1H(to_q_oh, ends.map(_ - 1).map(_ max 0).map(_.U)), Mux1H(to_q_oh, starts.map(_.U)), head + 1.U) for (i <- 0 until nVirtualChannels) { when (to_q_oh(i)) { qs(i).io.enq.valid := true.B qs(i).io.enq.bits := mem.read(head) } } } for (i <- 0 until nVirtualChannels) { io.deq(i) <> qs(i).io.deq } } else { qs.map(_.io.deq.ready := false.B) val ready_sel = io.deq.map(_.ready) val fire = io.deq.map(_.fire) assert(PopCount(fire) <= 1.U) val head = Mux1H(fire, heads) when (fire.orR) { val fire_idx = OHToUInt(fire) heads(fire_idx) := Mux( head === Mux1H(fire, ends.map(_ - 1).map(_ max 0).map(_.U)), Mux1H(fire, starts.map(_.U)), head + 1.U) } val read_flit = mem.read(head) for (i <- 0 until nVirtualChannels) { io.deq(i).valid := !empty(i) io.deq(i).bits := read_flit } } } } class InputUnit(cParam: ChannelParams, outParams: Seq[ChannelParams], egressParams: Seq[EgressChannelParams], combineRCVA: Boolean, combineSAST: Boolean ) (implicit p: Parameters) extends AbstractInputUnit(cParam, outParams, egressParams)(p) { val nVirtualChannels = cParam.nVirtualChannels val virtualChannelParams = cParam.virtualChannelParams class InputUnitIO extends AbstractInputUnitIO(cParam, outParams, egressParams) { val in = Flipped(new Channel(cParam.asInstanceOf[ChannelParams])) } val io = IO(new InputUnitIO) val g_i :: g_r :: g_v :: g_a :: g_c :: Nil = Enum(5) class InputState extends Bundle { val g = UInt(3.W) val vc_sel = MixedVec(allOutParams.map { u => Vec(u.nVirtualChannels, Bool()) }) val flow = new FlowRoutingBundle val fifo_deps = UInt(nVirtualChannels.W) } val input_buffer = Module(new InputBuffer(cParam)) for (i <- 0 until cParam.srcSpeedup) { input_buffer.io.enq(i) := io.in.flit(i) } input_buffer.io.deq.foreach(_.ready := false.B) val route_arbiter = Module(new Arbiter( new RouteComputerReq, nVirtualChannels )) io.router_req <> route_arbiter.io.out val states = Reg(Vec(nVirtualChannels, new InputState)) val anyFifo = cParam.possibleFlows.map(_.fifo).reduce(_||_) val allFifo = cParam.possibleFlows.map(_.fifo).reduce(_&&_) if (anyFifo) { val idle_mask = VecInit(states.map(_.g === g_i)).asUInt for (s <- states) for (i <- 0 until nVirtualChannels) s.fifo_deps := s.fifo_deps & ~idle_mask } for (i <- 0 until cParam.srcSpeedup) { when (io.in.flit(i).fire && io.in.flit(i).bits.head) { val id = io.in.flit(i).bits.virt_channel_id assert(id < nVirtualChannels.U) assert(states(id).g === g_i) val at_dest = io.in.flit(i).bits.flow.egress_node === nodeId.U states(id).g := Mux(at_dest, g_v, g_r) states(id).vc_sel.foreach(_.foreach(_ := false.B)) for (o <- 0 until nEgress) { when (o.U === io.in.flit(i).bits.flow.egress_node_id) { states(id).vc_sel(o+nOutputs)(0) := true.B } } states(id).flow := io.in.flit(i).bits.flow if (anyFifo) { val fifo = cParam.possibleFlows.filter(_.fifo).map(_.isFlow(io.in.flit(i).bits.flow)).toSeq.orR states(id).fifo_deps := VecInit(states.zipWithIndex.map { case (s, j) => s.g =/= g_i && s.flow.asUInt === io.in.flit(i).bits.flow.asUInt && j.U =/= id }).asUInt } } } (route_arbiter.io.in zip states).zipWithIndex.map { case ((i,s),idx) => if (virtualChannelParams(idx).traversable) { i.valid := s.g === g_r i.bits.flow := s.flow i.bits.src_virt_id := idx.U when (i.fire) { s.g := g_v } } else { i.valid := false.B i.bits := DontCare } } when (io.router_req.fire) { val id = io.router_req.bits.src_virt_id assert(states(id).g === g_r) states(id).g := g_v for (i <- 0 until nVirtualChannels) { when (i.U === id) { states(i).vc_sel := io.router_resp.vc_sel } } } val mask = RegInit(0.U(nVirtualChannels.W)) val vcalloc_reqs = Wire(Vec(nVirtualChannels, new VCAllocReq(cParam, outParams, egressParams))) val vcalloc_vals = Wire(Vec(nVirtualChannels, Bool())) val vcalloc_filter = PriorityEncoderOH(Cat(vcalloc_vals.asUInt, vcalloc_vals.asUInt & ~mask)) val vcalloc_sel = vcalloc_filter(nVirtualChannels-1,0) | (vcalloc_filter >> nVirtualChannels) // Prioritize incoming packetes when (io.router_req.fire) { mask := (1.U << io.router_req.bits.src_virt_id) - 1.U } .elsewhen (vcalloc_vals.orR) { mask := Mux1H(vcalloc_sel, (0 until nVirtualChannels).map { w => ~(0.U((w+1).W)) }) } io.vcalloc_req.valid := vcalloc_vals.orR io.vcalloc_req.bits := Mux1H(vcalloc_sel, vcalloc_reqs) states.zipWithIndex.map { case (s,idx) => if (virtualChannelParams(idx).traversable) { vcalloc_vals(idx) := s.g === g_v && s.fifo_deps === 0.U vcalloc_reqs(idx).in_vc := idx.U vcalloc_reqs(idx).vc_sel := s.vc_sel vcalloc_reqs(idx).flow := s.flow when (vcalloc_vals(idx) && vcalloc_sel(idx) && io.vcalloc_req.ready) { s.g := g_a } if (combineRCVA) { when (route_arbiter.io.in(idx).fire) { vcalloc_vals(idx) := true.B vcalloc_reqs(idx).vc_sel := io.router_resp.vc_sel } } } else { vcalloc_vals(idx) := false.B vcalloc_reqs(idx) := DontCare } } io.debug.va_stall := PopCount(vcalloc_vals) - io.vcalloc_req.ready when (io.vcalloc_req.fire) { for (i <- 0 until nVirtualChannels) { when (vcalloc_sel(i)) { states(i).vc_sel := io.vcalloc_resp.vc_sel states(i).g := g_a if (!combineRCVA) { assert(states(i).g === g_v) } } } } val salloc_arb = Module(new SwitchArbiter( nVirtualChannels, cParam.destSpeedup, outParams, egressParams )) (states zip salloc_arb.io.in).zipWithIndex.map { case ((s,r),i) => if (virtualChannelParams(i).traversable) { val credit_available = (s.vc_sel.asUInt & io.out_credit_available.asUInt) =/= 0.U r.valid := s.g === g_a && credit_available && input_buffer.io.deq(i).valid r.bits.vc_sel := s.vc_sel val deq_tail = input_buffer.io.deq(i).bits.tail r.bits.tail := deq_tail when (r.fire && deq_tail) { s.g := g_i } input_buffer.io.deq(i).ready := r.ready } else { r.valid := false.B r.bits := DontCare } } io.debug.sa_stall := PopCount(salloc_arb.io.in.map(r => r.valid && !r.ready)) io.salloc_req <> salloc_arb.io.out when (io.block) { salloc_arb.io.out.foreach(_.ready := false.B) io.salloc_req.foreach(_.valid := false.B) } class OutBundle extends Bundle { val valid = Bool() val vid = UInt(virtualChannelBits.W) val out_vid = UInt(log2Up(allOutParams.map(_.nVirtualChannels).max).W) val flit = new Flit(cParam.payloadBits) } val salloc_outs = if (combineSAST) { Wire(Vec(cParam.destSpeedup, new OutBundle)) } else { Reg(Vec(cParam.destSpeedup, new OutBundle)) } io.in.credit_return := salloc_arb.io.out.zipWithIndex.map { case (o, i) => Mux(o.fire, salloc_arb.io.chosen_oh(i), 0.U) }.reduce(_|_) io.in.vc_free := salloc_arb.io.out.zipWithIndex.map { case (o, i) => Mux(o.fire && Mux1H(salloc_arb.io.chosen_oh(i), input_buffer.io.deq.map(_.bits.tail)), salloc_arb.io.chosen_oh(i), 0.U) }.reduce(_|_) for (i <- 0 until cParam.destSpeedup) { val salloc_out = salloc_outs(i) salloc_out.valid := salloc_arb.io.out(i).fire salloc_out.vid := OHToUInt(salloc_arb.io.chosen_oh(i)) val vc_sel = Mux1H(salloc_arb.io.chosen_oh(i), states.map(_.vc_sel)) val channel_oh = vc_sel.map(_.reduce(_||_)).toSeq val virt_channel = Mux1H(channel_oh, vc_sel.map(v => OHToUInt(v)).toSeq) when (salloc_arb.io.out(i).fire) { salloc_out.out_vid := virt_channel salloc_out.flit.payload := Mux1H(salloc_arb.io.chosen_oh(i), input_buffer.io.deq.map(_.bits.payload)) salloc_out.flit.head := Mux1H(salloc_arb.io.chosen_oh(i), input_buffer.io.deq.map(_.bits.head)) salloc_out.flit.tail := Mux1H(salloc_arb.io.chosen_oh(i), input_buffer.io.deq.map(_.bits.tail)) salloc_out.flit.flow := Mux1H(salloc_arb.io.chosen_oh(i), states.map(_.flow)) } .otherwise { salloc_out.out_vid := DontCare salloc_out.flit := DontCare } salloc_out.flit.virt_channel_id := DontCare // this gets set in the switch io.out(i).valid := salloc_out.valid io.out(i).bits.flit := salloc_out.flit io.out(i).bits.out_virt_channel := salloc_out.out_vid } def filterVCSel(sel: MixedVec[Vec[Bool]], srcV: Int) = { if (virtualChannelParams(srcV).traversable) { outParams.zipWithIndex.map { case (oP, oI) => (0 until oP.nVirtualChannels).map { oV => var allow = false virtualChannelParams(srcV).possibleFlows.foreach { pI => allow = allow || routingRelation( cParam.channelRoutingInfos(srcV), oP.channelRoutingInfos(oV), pI ) } if (!allow) sel(oI)(oV) := false.B } } } } (0 until nVirtualChannels).map { i => if (!virtualChannelParams(i).traversable) states(i) := DontCare filterVCSel(states(i).vc_sel, i) } when (reset.asBool) { states.foreach(_.g := g_i) } }

module InputUnit_73( // @[InputUnit.scala:158:7] input clock, // @[InputUnit.scala:158:7] input reset, // @[InputUnit.scala:158:7] input io_vcalloc_req_ready, // @[InputUnit.scala:170:14] output io_vcalloc_req_valid, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_3_0, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_2_0, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_1_0, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_3_0, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_2_0, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_1_0, // @[InputUnit.scala:170:14] input io_out_credit_available_3_0, // @[InputUnit.scala:170:14] input io_out_credit_available_2_0, // @[InputUnit.scala:170:14] input io_out_credit_available_1_0, // @[InputUnit.scala:170:14] input io_out_credit_available_0_1, // @[InputUnit.scala:170:14] input io_salloc_req_0_ready, // @[InputUnit.scala:170:14] output io_salloc_req_0_valid, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_3_0, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_2_0, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_1_0, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_tail, // @[InputUnit.scala:170:14] output io_out_0_valid, // @[InputUnit.scala:170:14] output io_out_0_bits_flit_head, // @[InputUnit.scala:170:14] output io_out_0_bits_flit_tail, // @[InputUnit.scala:170:14] output [72:0] io_out_0_bits_flit_payload, // @[InputUnit.scala:170:14] output [2:0] io_out_0_bits_flit_flow_vnet_id, // @[InputUnit.scala:170:14] output [4:0] io_out_0_bits_flit_flow_ingress_node, // @[InputUnit.scala:170:14] output [1:0] io_out_0_bits_flit_flow_ingress_node_id, // @[InputUnit.scala:170:14] output [4:0] io_out_0_bits_flit_flow_egress_node, // @[InputUnit.scala:170:14] output [1:0] io_out_0_bits_flit_flow_egress_node_id, // @[InputUnit.scala:170:14] output [2:0] io_debug_va_stall, // @[InputUnit.scala:170:14] output [2:0] io_debug_sa_stall, // @[InputUnit.scala:170:14] input io_in_flit_0_valid, // @[InputUnit.scala:170:14] input io_in_flit_0_bits_head, // @[InputUnit.scala:170:14] input io_in_flit_0_bits_tail, // @[InputUnit.scala:170:14] input [72:0] io_in_flit_0_bits_payload, // @[InputUnit.scala:170:14] input [2:0] io_in_flit_0_bits_flow_vnet_id, // @[InputUnit.scala:170:14] input [4:0] io_in_flit_0_bits_flow_ingress_node, // @[InputUnit.scala:170:14] input [1:0] io_in_flit_0_bits_flow_ingress_node_id, // @[InputUnit.scala:170:14] input [4:0] io_in_flit_0_bits_flow_egress_node, // @[InputUnit.scala:170:14] input [1:0] io_in_flit_0_bits_flow_egress_node_id, // @[InputUnit.scala:170:14] input [2:0] io_in_flit_0_bits_virt_channel_id, // @[InputUnit.scala:170:14] output [4:0] io_in_credit_return, // @[InputUnit.scala:170:14] output [4:0] io_in_vc_free // @[InputUnit.scala:170:14] ); wire vcalloc_vals_4; // @[InputUnit.scala:266:32] wire _salloc_arb_io_in_4_ready; // @[InputUnit.scala:296:26] wire _salloc_arb_io_out_0_valid; // @[InputUnit.scala:296:26] wire [4:0] _salloc_arb_io_chosen_oh_0; // @[InputUnit.scala:296:26] wire _route_arbiter_io_in_4_ready; // @[InputUnit.scala:187:29] wire _route_arbiter_io_out_valid; // @[InputUnit.scala:187:29] wire [2:0] _route_arbiter_io_out_bits_src_virt_id; // @[InputUnit.scala:187:29] wire _input_buffer_io_deq_0_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_0_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_0_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_1_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_1_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_1_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_2_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_2_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_2_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_3_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_3_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_3_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_4_valid; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_4_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_4_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_4_bits_payload; // @[InputUnit.scala:181:28] reg [2:0] states_4_g; // @[InputUnit.scala:192:19] reg states_4_vc_sel_3_0; // @[InputUnit.scala:192:19] reg states_4_vc_sel_2_0; // @[InputUnit.scala:192:19] reg states_4_vc_sel_1_0; // @[InputUnit.scala:192:19] reg [2:0] states_4_flow_vnet_id; // @[InputUnit.scala:192:19] reg [4:0] states_4_flow_ingress_node; // @[InputUnit.scala:192:19] reg [1:0] states_4_flow_ingress_node_id; // @[InputUnit.scala:192:19] reg [4:0] states_4_flow_egress_node; // @[InputUnit.scala:192:19] reg [1:0] states_4_flow_egress_node_id; // @[InputUnit.scala:192:19] wire _GEN = io_in_flit_0_valid & io_in_flit_0_bits_head; // @[InputUnit.scala:205:30] wire route_arbiter_io_in_4_valid = states_4_g == 3'h1; // @[InputUnit.scala:192:19, :229:22] reg [4:0] mask; // @[InputUnit.scala:250:21] wire [4:0] _vcalloc_filter_T_3 = {vcalloc_vals_4, 4'h0} & ~mask; // @[InputUnit.scala:158:7, :250:21, :253:{80,87,89}, :266:32] wire [9:0] vcalloc_filter = _vcalloc_filter_T_3[0] ? 10'h1 : _vcalloc_filter_T_3[1] ? 10'h2 : _vcalloc_filter_T_3[2] ? 10'h4 : _vcalloc_filter_T_3[3] ? 10'h8 : _vcalloc_filter_T_3[4] ? 10'h10 : {vcalloc_vals_4, 9'h0}; // @[OneHot.scala:85:71] wire [4:0] vcalloc_sel = vcalloc_filter[4:0] | vcalloc_filter[9:5]; // @[Mux.scala:50:70] assign vcalloc_vals_4 = states_4_g == 3'h2; // @[InputUnit.scala:192:19, :266:32] wire _GEN_0 = io_vcalloc_req_ready & vcalloc_vals_4; // @[Decoupled.scala:51:35] wire _GEN_1 = _GEN_0 & vcalloc_sel[4]; // @[Mux.scala:32:36]

Generate the Verilog code corresponding to the following Chisel files. File lsu.scala: //****************************************************************************** // Copyright (c) 2012 - 2018, The Regents of the University of California (Regents). // All Rights Reserved. See LICENSE and LICENSE.SiFive for license details. //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ // RISCV Out-of-Order Load/Store Unit //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ // // Load/Store Unit is made up of the Load Queue, the Store Queue (LDQ and STQ). // // Stores are sent to memory at (well, after) commit, loads are executed // optimstically ASAP. If a misspeculation was discovered, the pipeline is // cleared. Loads put to sleep are retried. If a LoadAddr and StoreAddr match, // the Load can receive its data by forwarding data out of the Store Queue. // // Currently, loads are sent to memory immediately, and in parallel do an // associative search of the STQ, on entering the LSU. If a hit on the STQ // search, the memory request is killed on the next cycle, and if the STQ entry // is valid, the store data is forwarded to the load (delayed to match the // load-use delay to delay with the write-port structural hazard). If the store // data is not present, or it's only a partial match (SB->LH), the load is put // to sleep in the LDQ. // // Memory ordering violations are detected by stores at their addr-gen time by // associatively searching the LDQ for newer loads that have been issued to // memory. // // The store queue contains both speculated and committed stores. // // Only one port to memory... loads and stores have to fight for it, West Side // Story style. // // TODO: // - Add predicting structure for ordering failures // - currently won't STD forward if DMEM is busy // - ability to turn off things if VM is disabled // - reconsider port count of the wakeup, retry stuff package boom.v3.lsu import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.rocket import freechips.rocketchip.tilelink._ import freechips.rocketchip.util.Str import boom.v3.common._ import boom.v3.exu.{BrUpdateInfo, Exception, FuncUnitResp, CommitSignals, ExeUnitResp} import boom.v3.util.{BoolToChar, AgePriorityEncoder, IsKilledByBranch, GetNewBrMask, WrapInc, IsOlder, UpdateBrMask} class LSUExeIO(implicit p: Parameters) extends BoomBundle()(p) { // The "resp" of the maddrcalc is really a "req" to the LSU val req = Flipped(new ValidIO(new FuncUnitResp(xLen))) // Send load data to regfiles val iresp = new DecoupledIO(new boom.v3.exu.ExeUnitResp(xLen)) val fresp = new DecoupledIO(new boom.v3.exu.ExeUnitResp(xLen+1)) // TODO: Should this be fLen? } class BoomDCacheReq(implicit p: Parameters) extends BoomBundle()(p) with HasBoomUOP { val addr = UInt(coreMaxAddrBits.W) val data = Bits(coreDataBits.W) val is_hella = Bool() // Is this the hellacache req? If so this is not tracked in LDQ or STQ } class BoomDCacheResp(implicit p: Parameters) extends BoomBundle()(p) with HasBoomUOP { val data = Bits(coreDataBits.W) val is_hella = Bool() } class LSUDMemIO(implicit p: Parameters, edge: TLEdgeOut) extends BoomBundle()(p) { // In LSU's dmem stage, send the request val req = new DecoupledIO(Vec(memWidth, Valid(new BoomDCacheReq))) // In LSU's LCAM search stage, kill if order fail (or forwarding possible) val s1_kill = Output(Vec(memWidth, Bool())) // Get a request any cycle val resp = Flipped(Vec(memWidth, new ValidIO(new BoomDCacheResp))) // In our response stage, if we get a nack, we need to reexecute val nack = Flipped(Vec(memWidth, new ValidIO(new BoomDCacheReq))) val brupdate = Output(new BrUpdateInfo) val exception = Output(Bool()) val rob_pnr_idx = Output(UInt(robAddrSz.W)) val rob_head_idx = Output(UInt(robAddrSz.W)) val release = Flipped(new DecoupledIO(new TLBundleC(edge.bundle))) // Clears prefetching MSHRs val force_order = Output(Bool()) val ordered = Input(Bool()) val perf = Input(new Bundle { val acquire = Bool() val release = Bool() }) } class LSUCoreIO(implicit p: Parameters) extends BoomBundle()(p) { val exe = Vec(memWidth, new LSUExeIO) val dis_uops = Flipped(Vec(coreWidth, Valid(new MicroOp))) val dis_ldq_idx = Output(Vec(coreWidth, UInt(ldqAddrSz.W))) val dis_stq_idx = Output(Vec(coreWidth, UInt(stqAddrSz.W))) val ldq_full = Output(Vec(coreWidth, Bool())) val stq_full = Output(Vec(coreWidth, Bool())) val fp_stdata = Flipped(Decoupled(new ExeUnitResp(fLen))) val commit = Input(new CommitSignals) val commit_load_at_rob_head = Input(Bool()) // Stores clear busy bit when stdata is received // memWidth for int, 1 for fp (to avoid back-pressure fpstdat) val clr_bsy = Output(Vec(memWidth + 1, Valid(UInt(robAddrSz.W)))) // Speculatively safe load (barring memory ordering failure) val clr_unsafe = Output(Vec(memWidth, Valid(UInt(robAddrSz.W)))) // Tell the DCache to clear prefetches/speculating misses val fence_dmem = Input(Bool()) // Speculatively tell the IQs that we'll get load data back next cycle val spec_ld_wakeup = Output(Vec(memWidth, Valid(UInt(maxPregSz.W)))) // Tell the IQs that the load we speculated last cycle was misspeculated val ld_miss = Output(Bool()) val brupdate = Input(new BrUpdateInfo) val rob_pnr_idx = Input(UInt(robAddrSz.W)) val rob_head_idx = Input(UInt(robAddrSz.W)) val exception = Input(Bool()) val fencei_rdy = Output(Bool()) val lxcpt = Output(Valid(new Exception)) val tsc_reg = Input(UInt()) val perf = Output(new Bundle { val acquire = Bool() val release = Bool() val tlbMiss = Bool() }) } class LSUIO(implicit p: Parameters, edge: TLEdgeOut) extends BoomBundle()(p) { val ptw = new rocket.TLBPTWIO val core = new LSUCoreIO val dmem = new LSUDMemIO val hellacache = Flipped(new freechips.rocketchip.rocket.HellaCacheIO) } class LDQEntry(implicit p: Parameters) extends BoomBundle()(p) with HasBoomUOP { val addr = Valid(UInt(coreMaxAddrBits.W)) val addr_is_virtual = Bool() // Virtual address, we got a TLB miss val addr_is_uncacheable = Bool() // Uncacheable, wait until head of ROB to execute val executed = Bool() // load sent to memory, reset by NACKs val succeeded = Bool() val order_fail = Bool() val observed = Bool() val st_dep_mask = UInt(numStqEntries.W) // list of stores older than us val youngest_stq_idx = UInt(stqAddrSz.W) // index of the oldest store younger than us val forward_std_val = Bool() val forward_stq_idx = UInt(stqAddrSz.W) // Which store did we get the store-load forward from? val debug_wb_data = UInt(xLen.W) } class STQEntry(implicit p: Parameters) extends BoomBundle()(p) with HasBoomUOP { val addr = Valid(UInt(coreMaxAddrBits.W)) val addr_is_virtual = Bool() // Virtual address, we got a TLB miss val data = Valid(UInt(xLen.W)) val committed = Bool() // committed by ROB val succeeded = Bool() // D$ has ack'd this, we don't need to maintain this anymore val debug_wb_data = UInt(xLen.W) } class LSU(implicit p: Parameters, edge: TLEdgeOut) extends BoomModule()(p) with rocket.HasL1HellaCacheParameters { val io = IO(new LSUIO) io.hellacache := DontCare val ldq = Reg(Vec(numLdqEntries, Valid(new LDQEntry))) val stq = Reg(Vec(numStqEntries, Valid(new STQEntry))) val ldq_head = Reg(UInt(ldqAddrSz.W)) val ldq_tail = Reg(UInt(ldqAddrSz.W)) val stq_head = Reg(UInt(stqAddrSz.W)) // point to next store to clear from STQ (i.e., send to memory) val stq_tail = Reg(UInt(stqAddrSz.W)) val stq_commit_head = Reg(UInt(stqAddrSz.W)) // point to next store to commit val stq_execute_head = Reg(UInt(stqAddrSz.W)) // point to next store to execute // If we got a mispredict, the tail will be misaligned for 1 extra cycle assert (io.core.brupdate.b2.mispredict || stq(stq_execute_head).valid || stq_head === stq_execute_head || stq_tail === stq_execute_head, "stq_execute_head got off track.") val h_ready :: h_s1 :: h_s2 :: h_s2_nack :: h_wait :: h_replay :: h_dead :: Nil = Enum(7) // s1 : do TLB, if success and not killed, fire request go to h_s2 // store s1_data to register // if tlb miss, go to s2_nack // if don't get TLB, go to s2_nack // store tlb xcpt // s2 : If kill, go to dead // If tlb xcpt, send tlb xcpt, go to dead // s2_nack : send nack, go to dead // wait : wait for response, if nack, go to replay // replay : refire request, use already translated address // dead : wait for response, ignore it val hella_state = RegInit(h_ready) val hella_req = Reg(new rocket.HellaCacheReq) val hella_data = Reg(new rocket.HellaCacheWriteData) val hella_paddr = Reg(UInt(paddrBits.W)) val hella_xcpt = Reg(new rocket.HellaCacheExceptions) val dtlb = Module(new NBDTLB( instruction = false, lgMaxSize = log2Ceil(coreDataBytes), rocket.TLBConfig(dcacheParams.nTLBSets, dcacheParams.nTLBWays))) io.ptw <> dtlb.io.ptw io.core.perf.tlbMiss := io.ptw.req.fire io.core.perf.acquire := io.dmem.perf.acquire io.core.perf.release := io.dmem.perf.release val clear_store = WireInit(false.B) val live_store_mask = RegInit(0.U(numStqEntries.W)) var next_live_store_mask = Mux(clear_store, live_store_mask & ~(1.U << stq_head), live_store_mask) def widthMap[T <: Data](f: Int => T) = VecInit((0 until memWidth).map(f)) //------------------------------------------------------------- //------------------------------------------------------------- // Enqueue new entries //------------------------------------------------------------- //------------------------------------------------------------- // This is a newer store than existing loads, so clear the bit in all the store dependency masks for (i <- 0 until numLdqEntries) { when (clear_store) { ldq(i).bits.st_dep_mask := ldq(i).bits.st_dep_mask & ~(1.U << stq_head) } } // Decode stage var ld_enq_idx = ldq_tail var st_enq_idx = stq_tail val stq_nonempty = (0 until numStqEntries).map{ i => stq(i).valid }.reduce(_||_) =/= 0.U var ldq_full = Bool() var stq_full = Bool() for (w <- 0 until coreWidth) { ldq_full = WrapInc(ld_enq_idx, numLdqEntries) === ldq_head io.core.ldq_full(w) := ldq_full io.core.dis_ldq_idx(w) := ld_enq_idx stq_full = WrapInc(st_enq_idx, numStqEntries) === stq_head io.core.stq_full(w) := stq_full io.core.dis_stq_idx(w) := st_enq_idx val dis_ld_val = io.core.dis_uops(w).valid && io.core.dis_uops(w).bits.uses_ldq && !io.core.dis_uops(w).bits.exception val dis_st_val = io.core.dis_uops(w).valid && io.core.dis_uops(w).bits.uses_stq && !io.core.dis_uops(w).bits.exception when (dis_ld_val) { ldq(ld_enq_idx).valid := true.B ldq(ld_enq_idx).bits.uop := io.core.dis_uops(w).bits ldq(ld_enq_idx).bits.youngest_stq_idx := st_enq_idx ldq(ld_enq_idx).bits.st_dep_mask := next_live_store_mask ldq(ld_enq_idx).bits.addr.valid := false.B ldq(ld_enq_idx).bits.executed := false.B ldq(ld_enq_idx).bits.succeeded := false.B ldq(ld_enq_idx).bits.order_fail := false.B ldq(ld_enq_idx).bits.observed := false.B ldq(ld_enq_idx).bits.forward_std_val := false.B assert (ld_enq_idx === io.core.dis_uops(w).bits.ldq_idx, "[lsu] mismatch enq load tag.") assert (!ldq(ld_enq_idx).valid, "[lsu] Enqueuing uop is overwriting ldq entries") } .elsewhen (dis_st_val) { stq(st_enq_idx).valid := true.B stq(st_enq_idx).bits.uop := io.core.dis_uops(w).bits stq(st_enq_idx).bits.addr.valid := false.B stq(st_enq_idx).bits.data.valid := false.B stq(st_enq_idx).bits.committed := false.B stq(st_enq_idx).bits.succeeded := false.B assert (st_enq_idx === io.core.dis_uops(w).bits.stq_idx, "[lsu] mismatch enq store tag.") assert (!stq(st_enq_idx).valid, "[lsu] Enqueuing uop is overwriting stq entries") } ld_enq_idx = Mux(dis_ld_val, WrapInc(ld_enq_idx, numLdqEntries), ld_enq_idx) next_live_store_mask = Mux(dis_st_val, next_live_store_mask | (1.U << st_enq_idx), next_live_store_mask) st_enq_idx = Mux(dis_st_val, WrapInc(st_enq_idx, numStqEntries), st_enq_idx) assert(!(dis_ld_val && dis_st_val), "A UOP is trying to go into both the LDQ and the STQ") } ldq_tail := ld_enq_idx stq_tail := st_enq_idx io.dmem.force_order := io.core.fence_dmem io.core.fencei_rdy := !stq_nonempty && io.dmem.ordered //------------------------------------------------------------- //------------------------------------------------------------- // Execute stage (access TLB, send requests to Memory) //------------------------------------------------------------- //------------------------------------------------------------- // We can only report 1 exception per cycle. // Just be sure to report the youngest one val mem_xcpt_valid = Wire(Bool()) val mem_xcpt_cause = Wire(UInt()) val mem_xcpt_uop = Wire(new MicroOp) val mem_xcpt_vaddr = Wire(UInt()) //--------------------------------------- // Can-fire logic and wakeup/retry select // // First we determine what operations are waiting to execute. // These are the "can_fire"/"will_fire" signals val will_fire_load_incoming = Wire(Vec(memWidth, Bool())) val will_fire_stad_incoming = Wire(Vec(memWidth, Bool())) val will_fire_sta_incoming = Wire(Vec(memWidth, Bool())) val will_fire_std_incoming = Wire(Vec(memWidth, Bool())) val will_fire_sfence = Wire(Vec(memWidth, Bool())) val will_fire_hella_incoming = Wire(Vec(memWidth, Bool())) val will_fire_hella_wakeup = Wire(Vec(memWidth, Bool())) val will_fire_release = Wire(Vec(memWidth, Bool())) val will_fire_load_retry = Wire(Vec(memWidth, Bool())) val will_fire_sta_retry = Wire(Vec(memWidth, Bool())) val will_fire_store_commit = Wire(Vec(memWidth, Bool())) val will_fire_load_wakeup = Wire(Vec(memWidth, Bool())) val exe_req = WireInit(VecInit(io.core.exe.map(_.req))) // Sfence goes through all pipes for (i <- 0 until memWidth) { when (io.core.exe(i).req.bits.sfence.valid) { exe_req := VecInit(Seq.fill(memWidth) { io.core.exe(i).req }) } } // ------------------------------- // Assorted signals for scheduling // Don't wakeup a load if we just sent it last cycle or two cycles ago // The block_load_mask may be wrong, but the executing_load mask must be accurate val block_load_mask = WireInit(VecInit((0 until numLdqEntries).map(x=>false.B))) val p1_block_load_mask = RegNext(block_load_mask) val p2_block_load_mask = RegNext(p1_block_load_mask) // Prioritize emptying the store queue when it is almost full val stq_almost_full = RegNext(WrapInc(WrapInc(st_enq_idx, numStqEntries), numStqEntries) === stq_head || WrapInc(st_enq_idx, numStqEntries) === stq_head) // The store at the commit head needs the DCache to appear ordered // Delay firing load wakeups and retries now val store_needs_order = WireInit(false.B) val ldq_incoming_idx = widthMap(i => exe_req(i).bits.uop.ldq_idx) val ldq_incoming_e = widthMap(i => ldq(ldq_incoming_idx(i))) val stq_incoming_idx = widthMap(i => exe_req(i).bits.uop.stq_idx) val stq_incoming_e = widthMap(i => stq(stq_incoming_idx(i))) val ldq_retry_idx = RegNext(AgePriorityEncoder((0 until numLdqEntries).map(i => { val e = ldq(i).bits val block = block_load_mask(i) || p1_block_load_mask(i) e.addr.valid && e.addr_is_virtual && !block }), ldq_head)) val ldq_retry_e = ldq(ldq_retry_idx) val stq_retry_idx = RegNext(AgePriorityEncoder((0 until numStqEntries).map(i => { val e = stq(i).bits e.addr.valid && e.addr_is_virtual }), stq_commit_head)) val stq_retry_e = stq(stq_retry_idx) val stq_commit_e = stq(stq_execute_head) val ldq_wakeup_idx = RegNext(AgePriorityEncoder((0 until numLdqEntries).map(i=> { val e = ldq(i).bits val block = block_load_mask(i) || p1_block_load_mask(i) e.addr.valid && !e.executed && !e.succeeded && !e.addr_is_virtual && !block }), ldq_head)) val ldq_wakeup_e = ldq(ldq_wakeup_idx) // ----------------------- // Determine what can fire // Can we fire a incoming load val can_fire_load_incoming = widthMap(w => exe_req(w).valid && exe_req(w).bits.uop.ctrl.is_load) // Can we fire an incoming store addrgen + store datagen val can_fire_stad_incoming = widthMap(w => exe_req(w).valid && exe_req(w).bits.uop.ctrl.is_sta && exe_req(w).bits.uop.ctrl.is_std) // Can we fire an incoming store addrgen val can_fire_sta_incoming = widthMap(w => exe_req(w).valid && exe_req(w).bits.uop.ctrl.is_sta && !exe_req(w).bits.uop.ctrl.is_std) // Can we fire an incoming store datagen val can_fire_std_incoming = widthMap(w => exe_req(w).valid && exe_req(w).bits.uop.ctrl.is_std && !exe_req(w).bits.uop.ctrl.is_sta) // Can we fire an incoming sfence val can_fire_sfence = widthMap(w => exe_req(w).valid && exe_req(w).bits.sfence.valid) // Can we fire a request from dcache to release a line // This needs to go through LDQ search to mark loads as dangerous val can_fire_release = widthMap(w => (w == memWidth-1).B && io.dmem.release.valid) io.dmem.release.ready := will_fire_release.reduce(_||_) // Can we retry a load that missed in the TLB val can_fire_load_retry = widthMap(w => ( ldq_retry_e.valid && ldq_retry_e.bits.addr.valid && ldq_retry_e.bits.addr_is_virtual && !p1_block_load_mask(ldq_retry_idx) && !p2_block_load_mask(ldq_retry_idx) && RegNext(dtlb.io.miss_rdy) && !store_needs_order && (w == memWidth-1).B && // TODO: Is this best scheduling? !ldq_retry_e.bits.order_fail)) // Can we retry a store addrgen that missed in the TLB // - Weird edge case when sta_retry and std_incoming for same entry in same cycle. Delay this val can_fire_sta_retry = widthMap(w => ( stq_retry_e.valid && stq_retry_e.bits.addr.valid && stq_retry_e.bits.addr_is_virtual && (w == memWidth-1).B && RegNext(dtlb.io.miss_rdy) && !(widthMap(i => (i != w).B && can_fire_std_incoming(i) && stq_incoming_idx(i) === stq_retry_idx).reduce(_||_)) )) // Can we commit a store val can_fire_store_commit = widthMap(w => ( stq_commit_e.valid && !stq_commit_e.bits.uop.is_fence && !mem_xcpt_valid && !stq_commit_e.bits.uop.exception && (w == 0).B && (stq_commit_e.bits.committed || ( stq_commit_e.bits.uop.is_amo && stq_commit_e.bits.addr.valid && !stq_commit_e.bits.addr_is_virtual && stq_commit_e.bits.data.valid)))) // Can we wakeup a load that was nack'd val block_load_wakeup = WireInit(false.B) val can_fire_load_wakeup = widthMap(w => ( ldq_wakeup_e.valid && ldq_wakeup_e.bits.addr.valid && !ldq_wakeup_e.bits.succeeded && !ldq_wakeup_e.bits.addr_is_virtual && !ldq_wakeup_e.bits.executed && !ldq_wakeup_e.bits.order_fail && !p1_block_load_mask(ldq_wakeup_idx) && !p2_block_load_mask(ldq_wakeup_idx) && !store_needs_order && !block_load_wakeup && (w == memWidth-1).B && (!ldq_wakeup_e.bits.addr_is_uncacheable || (io.core.commit_load_at_rob_head && ldq_head === ldq_wakeup_idx && ldq_wakeup_e.bits.st_dep_mask.asUInt === 0.U)))) // Can we fire an incoming hellacache request val can_fire_hella_incoming = WireInit(widthMap(w => false.B)) // This is assigned to in the hellashim ocntroller // Can we fire a hellacache request that the dcache nack'd val can_fire_hella_wakeup = WireInit(widthMap(w => false.B)) // This is assigned to in the hellashim controller //--------------------------------------------------------- // Controller logic. Arbitrate which request actually fires val exe_tlb_valid = Wire(Vec(memWidth, Bool())) for (w <- 0 until memWidth) { var tlb_avail = true.B var dc_avail = true.B var lcam_avail = true.B var rob_avail = true.B def lsu_sched(can_fire: Bool, uses_tlb:Boolean, uses_dc:Boolean, uses_lcam: Boolean, uses_rob:Boolean): Bool = { val will_fire = can_fire && !(uses_tlb.B && !tlb_avail) && !(uses_lcam.B && !lcam_avail) && !(uses_dc.B && !dc_avail) && !(uses_rob.B && !rob_avail) tlb_avail = tlb_avail && !(will_fire && uses_tlb.B) lcam_avail = lcam_avail && !(will_fire && uses_lcam.B) dc_avail = dc_avail && !(will_fire && uses_dc.B) rob_avail = rob_avail && !(will_fire && uses_rob.B) dontTouch(will_fire) // dontTouch these so we can inspect the will_fire signals will_fire } // The order of these statements is the priority // Some restrictions // - Incoming ops must get precedence, can't backpresure memaddrgen // - Incoming hellacache ops must get precedence over retrying ops (PTW must get precedence over retrying translation) // Notes on performance // - Prioritize releases, this speeds up cache line writebacks and refills // - Store commits are lowest priority, since they don't "block" younger instructions unless stq fills up will_fire_load_incoming (w) := lsu_sched(can_fire_load_incoming (w) , true , true , true , false) // TLB , DC , LCAM will_fire_stad_incoming (w) := lsu_sched(can_fire_stad_incoming (w) , true , false, true , true) // TLB , , LCAM , ROB will_fire_sta_incoming (w) := lsu_sched(can_fire_sta_incoming (w) , true , false, true , true) // TLB , , LCAM , ROB will_fire_std_incoming (w) := lsu_sched(can_fire_std_incoming (w) , false, false, false, true) // , ROB will_fire_sfence (w) := lsu_sched(can_fire_sfence (w) , true , false, false, true) // TLB , , , ROB will_fire_release (w) := lsu_sched(can_fire_release (w) , false, false, true , false) // LCAM will_fire_hella_incoming(w) := lsu_sched(can_fire_hella_incoming(w) , true , true , false, false) // TLB , DC will_fire_hella_wakeup (w) := lsu_sched(can_fire_hella_wakeup (w) , false, true , false, false) // , DC will_fire_load_retry (w) := lsu_sched(can_fire_load_retry (w) , true , true , true , false) // TLB , DC , LCAM will_fire_sta_retry (w) := lsu_sched(can_fire_sta_retry (w) , true , false, true , true) // TLB , , LCAM , ROB // TODO: This should be higher priority will_fire_load_wakeup (w) := lsu_sched(can_fire_load_wakeup (w) , false, true , true , false) // , DC , LCAM1 will_fire_store_commit (w) := lsu_sched(can_fire_store_commit (w) , false, true , false, false) // , DC assert(!(exe_req(w).valid && !(will_fire_load_incoming(w) || will_fire_stad_incoming(w) || will_fire_sta_incoming(w) || will_fire_std_incoming(w) || will_fire_sfence(w)))) when (will_fire_load_wakeup(w)) { block_load_mask(ldq_wakeup_idx) := true.B } .elsewhen (will_fire_load_incoming(w)) { block_load_mask(exe_req(w).bits.uop.ldq_idx) := true.B } .elsewhen (will_fire_load_retry(w)) { block_load_mask(ldq_retry_idx) := true.B } exe_tlb_valid(w) := !tlb_avail } assert((memWidth == 1).B || (!(will_fire_sfence.reduce(_||_) && !will_fire_sfence.reduce(_&&_)) && !will_fire_hella_incoming.reduce(_&&_) && !will_fire_hella_wakeup.reduce(_&&_) && !will_fire_load_retry.reduce(_&&_) && !will_fire_sta_retry.reduce(_&&_) && !will_fire_store_commit.reduce(_&&_) && !will_fire_load_wakeup.reduce(_&&_)), "Some operations is proceeding down multiple pipes") require(memWidth <= 2) //-------------------------------------------- // TLB Access assert(!(hella_state =/= h_ready && hella_req.cmd === rocket.M_SFENCE), "SFENCE through hella interface not supported") val exe_tlb_uop = widthMap(w => Mux(will_fire_load_incoming (w) || will_fire_stad_incoming (w) || will_fire_sta_incoming (w) || will_fire_sfence (w) , exe_req(w).bits.uop, Mux(will_fire_load_retry (w) , ldq_retry_e.bits.uop, Mux(will_fire_sta_retry (w) , stq_retry_e.bits.uop, Mux(will_fire_hella_incoming(w) , NullMicroOp, NullMicroOp))))) val exe_tlb_vaddr = widthMap(w => Mux(will_fire_load_incoming (w) || will_fire_stad_incoming (w) || will_fire_sta_incoming (w) , exe_req(w).bits.addr, Mux(will_fire_sfence (w) , exe_req(w).bits.sfence.bits.addr, Mux(will_fire_load_retry (w) , ldq_retry_e.bits.addr.bits, Mux(will_fire_sta_retry (w) , stq_retry_e.bits.addr.bits, Mux(will_fire_hella_incoming(w) , hella_req.addr, 0.U)))))) val exe_sfence = WireInit((0.U).asTypeOf(Valid(new rocket.SFenceReq))) for (w <- 0 until memWidth) { when (will_fire_sfence(w)) { exe_sfence := exe_req(w).bits.sfence } } val exe_size = widthMap(w => Mux(will_fire_load_incoming (w) || will_fire_stad_incoming (w) || will_fire_sta_incoming (w) || will_fire_sfence (w) || will_fire_load_retry (w) || will_fire_sta_retry (w) , exe_tlb_uop(w).mem_size, Mux(will_fire_hella_incoming(w) , hella_req.size, 0.U))) val exe_cmd = widthMap(w => Mux(will_fire_load_incoming (w) || will_fire_stad_incoming (w) || will_fire_sta_incoming (w) || will_fire_sfence (w) || will_fire_load_retry (w) || will_fire_sta_retry (w) , exe_tlb_uop(w).mem_cmd, Mux(will_fire_hella_incoming(w) , hella_req.cmd, 0.U))) val exe_passthr= widthMap(w => Mux(will_fire_hella_incoming(w) , hella_req.phys, false.B)) val exe_kill = widthMap(w => Mux(will_fire_hella_incoming(w) , io.hellacache.s1_kill, false.B)) for (w <- 0 until memWidth) { dtlb.io.req(w).valid := exe_tlb_valid(w) dtlb.io.req(w).bits.vaddr := exe_tlb_vaddr(w) dtlb.io.req(w).bits.size := exe_size(w) dtlb.io.req(w).bits.cmd := exe_cmd(w) dtlb.io.req(w).bits.passthrough := exe_passthr(w) dtlb.io.req(w).bits.v := io.ptw.status.v dtlb.io.req(w).bits.prv := io.ptw.status.prv } dtlb.io.kill := exe_kill.reduce(_||_) dtlb.io.sfence := exe_sfence // exceptions val ma_ld = widthMap(w => will_fire_load_incoming(w) && exe_req(w).bits.mxcpt.valid) // We get ma_ld in memaddrcalc val ma_st = widthMap(w => (will_fire_sta_incoming(w) || will_fire_stad_incoming(w)) && exe_req(w).bits.mxcpt.valid) // We get ma_ld in memaddrcalc val pf_ld = widthMap(w => dtlb.io.req(w).valid && dtlb.io.resp(w).pf.ld && exe_tlb_uop(w).uses_ldq) val pf_st = widthMap(w => dtlb.io.req(w).valid && dtlb.io.resp(w).pf.st && exe_tlb_uop(w).uses_stq) val ae_ld = widthMap(w => dtlb.io.req(w).valid && dtlb.io.resp(w).ae.ld && exe_tlb_uop(w).uses_ldq) val ae_st = widthMap(w => dtlb.io.req(w).valid && dtlb.io.resp(w).ae.st && exe_tlb_uop(w).uses_stq) // TODO check for xcpt_if and verify that never happens on non-speculative instructions. val mem_xcpt_valids = RegNext(widthMap(w => (pf_ld(w) || pf_st(w) || ae_ld(w) || ae_st(w) || ma_ld(w) || ma_st(w)) && !io.core.exception && !IsKilledByBranch(io.core.brupdate, exe_tlb_uop(w)))) val mem_xcpt_uops = RegNext(widthMap(w => UpdateBrMask(io.core.brupdate, exe_tlb_uop(w)))) val mem_xcpt_causes = RegNext(widthMap(w => Mux(ma_ld(w), rocket.Causes.misaligned_load.U, Mux(ma_st(w), rocket.Causes.misaligned_store.U, Mux(pf_ld(w), rocket.Causes.load_page_fault.U, Mux(pf_st(w), rocket.Causes.store_page_fault.U, Mux(ae_ld(w), rocket.Causes.load_access.U, rocket.Causes.store_access.U))))))) val mem_xcpt_vaddrs = RegNext(exe_tlb_vaddr) for (w <- 0 until memWidth) { assert (!(dtlb.io.req(w).valid && exe_tlb_uop(w).is_fence), "Fence is pretending to talk to the TLB") assert (!((will_fire_load_incoming(w) || will_fire_sta_incoming(w) || will_fire_stad_incoming(w)) && exe_req(w).bits.mxcpt.valid && dtlb.io.req(w).valid && !(exe_tlb_uop(w).ctrl.is_load || exe_tlb_uop(w).ctrl.is_sta)), "A uop that's not a load or store-address is throwing a memory exception.") } mem_xcpt_valid := mem_xcpt_valids.reduce(_||_) mem_xcpt_cause := mem_xcpt_causes(0) mem_xcpt_uop := mem_xcpt_uops(0) mem_xcpt_vaddr := mem_xcpt_vaddrs(0) var xcpt_found = mem_xcpt_valids(0) var oldest_xcpt_rob_idx = mem_xcpt_uops(0).rob_idx for (w <- 1 until memWidth) { val is_older = WireInit(false.B) when (mem_xcpt_valids(w) && (IsOlder(mem_xcpt_uops(w).rob_idx, oldest_xcpt_rob_idx, io.core.rob_head_idx) || !xcpt_found)) { is_older := true.B mem_xcpt_cause := mem_xcpt_causes(w) mem_xcpt_uop := mem_xcpt_uops(w) mem_xcpt_vaddr := mem_xcpt_vaddrs(w) } xcpt_found = xcpt_found || mem_xcpt_valids(w) oldest_xcpt_rob_idx = Mux(is_older, mem_xcpt_uops(w).rob_idx, oldest_xcpt_rob_idx) } val exe_tlb_miss = widthMap(w => dtlb.io.req(w).valid && (dtlb.io.resp(w).miss || !dtlb.io.req(w).ready)) val exe_tlb_paddr = widthMap(w => Cat(dtlb.io.resp(w).paddr(paddrBits-1,corePgIdxBits), exe_tlb_vaddr(w)(corePgIdxBits-1,0))) val exe_tlb_uncacheable = widthMap(w => !(dtlb.io.resp(w).cacheable)) for (w <- 0 until memWidth) { assert (exe_tlb_paddr(w) === dtlb.io.resp(w).paddr || exe_req(w).bits.sfence.valid, "[lsu] paddrs should match.") when (mem_xcpt_valids(w)) { assert(RegNext(will_fire_load_incoming(w) || will_fire_stad_incoming(w) || will_fire_sta_incoming(w) || will_fire_load_retry(w) || will_fire_sta_retry(w))) // Technically only faulting AMOs need this assert(mem_xcpt_uops(w).uses_ldq ^ mem_xcpt_uops(w).uses_stq) when (mem_xcpt_uops(w).uses_ldq) { ldq(mem_xcpt_uops(w).ldq_idx).bits.uop.exception := true.B } .otherwise { stq(mem_xcpt_uops(w).stq_idx).bits.uop.exception := true.B } } } //------------------------------ // Issue Someting to Memory // // A memory op can come from many different places // The address either was freshly translated, or we are // reading a physical address from the LDQ,STQ, or the HellaCache adapter // defaults io.dmem.brupdate := io.core.brupdate io.dmem.exception := io.core.exception io.dmem.rob_head_idx := io.core.rob_head_idx io.dmem.rob_pnr_idx := io.core.rob_pnr_idx val dmem_req = Wire(Vec(memWidth, Valid(new BoomDCacheReq))) io.dmem.req.valid := dmem_req.map(_.valid).reduce(_||_) io.dmem.req.bits := dmem_req val dmem_req_fire = widthMap(w => dmem_req(w).valid && io.dmem.req.fire) val s0_executing_loads = WireInit(VecInit((0 until numLdqEntries).map(x=>false.B))) for (w <- 0 until memWidth) { dmem_req(w).valid := false.B dmem_req(w).bits.uop := NullMicroOp dmem_req(w).bits.addr := 0.U dmem_req(w).bits.data := 0.U dmem_req(w).bits.is_hella := false.B io.dmem.s1_kill(w) := false.B when (will_fire_load_incoming(w)) { dmem_req(w).valid := !exe_tlb_miss(w) && !exe_tlb_uncacheable(w) dmem_req(w).bits.addr := exe_tlb_paddr(w) dmem_req(w).bits.uop := exe_tlb_uop(w) s0_executing_loads(ldq_incoming_idx(w)) := dmem_req_fire(w) assert(!ldq_incoming_e(w).bits.executed) } .elsewhen (will_fire_load_retry(w)) { dmem_req(w).valid := !exe_tlb_miss(w) && !exe_tlb_uncacheable(w) dmem_req(w).bits.addr := exe_tlb_paddr(w) dmem_req(w).bits.uop := exe_tlb_uop(w) s0_executing_loads(ldq_retry_idx) := dmem_req_fire(w) assert(!ldq_retry_e.bits.executed) } .elsewhen (will_fire_store_commit(w)) { dmem_req(w).valid := true.B dmem_req(w).bits.addr := stq_commit_e.bits.addr.bits dmem_req(w).bits.data := (new freechips.rocketchip.rocket.StoreGen( stq_commit_e.bits.uop.mem_size, 0.U, stq_commit_e.bits.data.bits, coreDataBytes)).data dmem_req(w).bits.uop := stq_commit_e.bits.uop stq_execute_head := Mux(dmem_req_fire(w), WrapInc(stq_execute_head, numStqEntries), stq_execute_head) stq(stq_execute_head).bits.succeeded := false.B } .elsewhen (will_fire_load_wakeup(w)) { dmem_req(w).valid := true.B dmem_req(w).bits.addr := ldq_wakeup_e.bits.addr.bits dmem_req(w).bits.uop := ldq_wakeup_e.bits.uop s0_executing_loads(ldq_wakeup_idx) := dmem_req_fire(w) assert(!ldq_wakeup_e.bits.executed && !ldq_wakeup_e.bits.addr_is_virtual) } .elsewhen (will_fire_hella_incoming(w)) { assert(hella_state === h_s1) dmem_req(w).valid := !io.hellacache.s1_kill && (!exe_tlb_miss(w) || hella_req.phys) dmem_req(w).bits.addr := exe_tlb_paddr(w) dmem_req(w).bits.data := (new freechips.rocketchip.rocket.StoreGen( hella_req.size, 0.U, io.hellacache.s1_data.data, coreDataBytes)).data dmem_req(w).bits.uop.mem_cmd := hella_req.cmd dmem_req(w).bits.uop.mem_size := hella_req.size dmem_req(w).bits.uop.mem_signed := hella_req.signed dmem_req(w).bits.is_hella := true.B hella_paddr := exe_tlb_paddr(w) } .elsewhen (will_fire_hella_wakeup(w)) { assert(hella_state === h_replay) dmem_req(w).valid := true.B dmem_req(w).bits.addr := hella_paddr dmem_req(w).bits.data := (new freechips.rocketchip.rocket.StoreGen( hella_req.size, 0.U, hella_data.data, coreDataBytes)).data dmem_req(w).bits.uop.mem_cmd := hella_req.cmd dmem_req(w).bits.uop.mem_size := hella_req.size dmem_req(w).bits.uop.mem_signed := hella_req.signed dmem_req(w).bits.is_hella := true.B } //------------------------------------------------------------- // Write Addr into the LAQ/SAQ when (will_fire_load_incoming(w) || will_fire_load_retry(w)) { val ldq_idx = Mux(will_fire_load_incoming(w), ldq_incoming_idx(w), ldq_retry_idx) ldq(ldq_idx).bits.addr.valid := true.B ldq(ldq_idx).bits.addr.bits := Mux(exe_tlb_miss(w), exe_tlb_vaddr(w), exe_tlb_paddr(w)) ldq(ldq_idx).bits.uop.pdst := exe_tlb_uop(w).pdst ldq(ldq_idx).bits.addr_is_virtual := exe_tlb_miss(w) ldq(ldq_idx).bits.addr_is_uncacheable := exe_tlb_uncacheable(w) && !exe_tlb_miss(w) assert(!(will_fire_load_incoming(w) && ldq_incoming_e(w).bits.addr.valid), "[lsu] Incoming load is overwriting a valid address") } when (will_fire_sta_incoming(w) || will_fire_stad_incoming(w) || will_fire_sta_retry(w)) { val stq_idx = Mux(will_fire_sta_incoming(w) || will_fire_stad_incoming(w), stq_incoming_idx(w), stq_retry_idx) stq(stq_idx).bits.addr.valid := !pf_st(w) // Prevent AMOs from executing! stq(stq_idx).bits.addr.bits := Mux(exe_tlb_miss(w), exe_tlb_vaddr(w), exe_tlb_paddr(w)) stq(stq_idx).bits.uop.pdst := exe_tlb_uop(w).pdst // Needed for AMOs stq(stq_idx).bits.addr_is_virtual := exe_tlb_miss(w) assert(!(will_fire_sta_incoming(w) && stq_incoming_e(w).bits.addr.valid), "[lsu] Incoming store is overwriting a valid address") } //------------------------------------------------------------- // Write data into the STQ if (w == 0) io.core.fp_stdata.ready := !will_fire_std_incoming(w) && !will_fire_stad_incoming(w) val fp_stdata_fire = io.core.fp_stdata.fire && (w == 0).B when (will_fire_std_incoming(w) || will_fire_stad_incoming(w) || fp_stdata_fire) { val sidx = Mux(will_fire_std_incoming(w) || will_fire_stad_incoming(w), stq_incoming_idx(w), io.core.fp_stdata.bits.uop.stq_idx) stq(sidx).bits.data.valid := true.B stq(sidx).bits.data.bits := Mux(will_fire_std_incoming(w) || will_fire_stad_incoming(w), exe_req(w).bits.data, io.core.fp_stdata.bits.data) assert(!(stq(sidx).bits.data.valid), "[lsu] Incoming store is overwriting a valid data entry") } } val will_fire_stdf_incoming = io.core.fp_stdata.fire require (xLen >= fLen) // for correct SDQ size //------------------------------------------------------------- //------------------------------------------------------------- // Cache Access Cycle (Mem) //------------------------------------------------------------- //------------------------------------------------------------- // Note the DCache may not have accepted our request val exe_req_killed = widthMap(w => IsKilledByBranch(io.core.brupdate, exe_req(w).bits.uop)) val stdf_killed = IsKilledByBranch(io.core.brupdate, io.core.fp_stdata.bits.uop) val fired_load_incoming = widthMap(w => RegNext(will_fire_load_incoming(w) && !exe_req_killed(w))) val fired_stad_incoming = widthMap(w => RegNext(will_fire_stad_incoming(w) && !exe_req_killed(w))) val fired_sta_incoming = widthMap(w => RegNext(will_fire_sta_incoming (w) && !exe_req_killed(w))) val fired_std_incoming = widthMap(w => RegNext(will_fire_std_incoming (w) && !exe_req_killed(w))) val fired_stdf_incoming = RegNext(will_fire_stdf_incoming && !stdf_killed) val fired_sfence = RegNext(will_fire_sfence) val fired_release = RegNext(will_fire_release) val fired_load_retry = widthMap(w => RegNext(will_fire_load_retry (w) && !IsKilledByBranch(io.core.brupdate, ldq_retry_e.bits.uop))) val fired_sta_retry = widthMap(w => RegNext(will_fire_sta_retry (w) && !IsKilledByBranch(io.core.brupdate, stq_retry_e.bits.uop))) val fired_store_commit = RegNext(will_fire_store_commit) val fired_load_wakeup = widthMap(w => RegNext(will_fire_load_wakeup (w) && !IsKilledByBranch(io.core.brupdate, ldq_wakeup_e.bits.uop))) val fired_hella_incoming = RegNext(will_fire_hella_incoming) val fired_hella_wakeup = RegNext(will_fire_hella_wakeup) val mem_incoming_uop = RegNext(widthMap(w => UpdateBrMask(io.core.brupdate, exe_req(w).bits.uop))) val mem_ldq_incoming_e = RegNext(widthMap(w => UpdateBrMask(io.core.brupdate, ldq_incoming_e(w)))) val mem_stq_incoming_e = RegNext(widthMap(w => UpdateBrMask(io.core.brupdate, stq_incoming_e(w)))) val mem_ldq_wakeup_e = RegNext(UpdateBrMask(io.core.brupdate, ldq_wakeup_e)) val mem_ldq_retry_e = RegNext(UpdateBrMask(io.core.brupdate, ldq_retry_e)) val mem_stq_retry_e = RegNext(UpdateBrMask(io.core.brupdate, stq_retry_e)) val mem_ldq_e = widthMap(w => Mux(fired_load_incoming(w), mem_ldq_incoming_e(w), Mux(fired_load_retry (w), mem_ldq_retry_e, Mux(fired_load_wakeup (w), mem_ldq_wakeup_e, (0.U).asTypeOf(Valid(new LDQEntry)))))) val mem_stq_e = widthMap(w => Mux(fired_stad_incoming(w) || fired_sta_incoming (w), mem_stq_incoming_e(w), Mux(fired_sta_retry (w), mem_stq_retry_e, (0.U).asTypeOf(Valid(new STQEntry))))) val mem_stdf_uop = RegNext(UpdateBrMask(io.core.brupdate, io.core.fp_stdata.bits.uop)) val mem_tlb_miss = RegNext(exe_tlb_miss) val mem_tlb_uncacheable = RegNext(exe_tlb_uncacheable) val mem_paddr = RegNext(widthMap(w => dmem_req(w).bits.addr)) // Task 1: Clr ROB busy bit val clr_bsy_valid = RegInit(widthMap(w => false.B)) val clr_bsy_rob_idx = Reg(Vec(memWidth, UInt(robAddrSz.W))) val clr_bsy_brmask = Reg(Vec(memWidth, UInt(maxBrCount.W))) for (w <- 0 until memWidth) { clr_bsy_valid (w) := false.B clr_bsy_rob_idx (w) := 0.U clr_bsy_brmask (w) := 0.U when (fired_stad_incoming(w)) { clr_bsy_valid (w) := mem_stq_incoming_e(w).valid && !mem_tlb_miss(w) && !mem_stq_incoming_e(w).bits.uop.is_amo && !IsKilledByBranch(io.core.brupdate, mem_stq_incoming_e(w).bits.uop) clr_bsy_rob_idx (w) := mem_stq_incoming_e(w).bits.uop.rob_idx clr_bsy_brmask (w) := GetNewBrMask(io.core.brupdate, mem_stq_incoming_e(w).bits.uop) } .elsewhen (fired_sta_incoming(w)) { clr_bsy_valid (w) := mem_stq_incoming_e(w).valid && mem_stq_incoming_e(w).bits.data.valid && !mem_tlb_miss(w) && !mem_stq_incoming_e(w).bits.uop.is_amo && !IsKilledByBranch(io.core.brupdate, mem_stq_incoming_e(w).bits.uop) clr_bsy_rob_idx (w) := mem_stq_incoming_e(w).bits.uop.rob_idx clr_bsy_brmask (w) := GetNewBrMask(io.core.brupdate, mem_stq_incoming_e(w).bits.uop) } .elsewhen (fired_std_incoming(w)) { clr_bsy_valid (w) := mem_stq_incoming_e(w).valid && mem_stq_incoming_e(w).bits.addr.valid && !mem_stq_incoming_e(w).bits.addr_is_virtual && !mem_stq_incoming_e(w).bits.uop.is_amo && !IsKilledByBranch(io.core.brupdate, mem_stq_incoming_e(w).bits.uop) clr_bsy_rob_idx (w) := mem_stq_incoming_e(w).bits.uop.rob_idx clr_bsy_brmask (w) := GetNewBrMask(io.core.brupdate, mem_stq_incoming_e(w).bits.uop) } .elsewhen (fired_sfence(w)) { clr_bsy_valid (w) := (w == 0).B // SFence proceeds down all paths, only allow one to clr the rob clr_bsy_rob_idx (w) := mem_incoming_uop(w).rob_idx clr_bsy_brmask (w) := GetNewBrMask(io.core.brupdate, mem_incoming_uop(w)) } .elsewhen (fired_sta_retry(w)) { clr_bsy_valid (w) := mem_stq_retry_e.valid && mem_stq_retry_e.bits.data.valid && !mem_tlb_miss(w) && !mem_stq_retry_e.bits.uop.is_amo && !IsKilledByBranch(io.core.brupdate, mem_stq_retry_e.bits.uop) clr_bsy_rob_idx (w) := mem_stq_retry_e.bits.uop.rob_idx clr_bsy_brmask (w) := GetNewBrMask(io.core.brupdate, mem_stq_retry_e.bits.uop) } io.core.clr_bsy(w).valid := clr_bsy_valid(w) && !IsKilledByBranch(io.core.brupdate, clr_bsy_brmask(w)) && !io.core.exception && !RegNext(io.core.exception) && !RegNext(RegNext(io.core.exception)) io.core.clr_bsy(w).bits := clr_bsy_rob_idx(w) } val stdf_clr_bsy_valid = RegInit(false.B) val stdf_clr_bsy_rob_idx = Reg(UInt(robAddrSz.W)) val stdf_clr_bsy_brmask = Reg(UInt(maxBrCount.W)) stdf_clr_bsy_valid := false.B stdf_clr_bsy_rob_idx := 0.U stdf_clr_bsy_brmask := 0.U when (fired_stdf_incoming) { val s_idx = mem_stdf_uop.stq_idx stdf_clr_bsy_valid := stq(s_idx).valid && stq(s_idx).bits.addr.valid && !stq(s_idx).bits.addr_is_virtual && !stq(s_idx).bits.uop.is_amo && !IsKilledByBranch(io.core.brupdate, mem_stdf_uop) stdf_clr_bsy_rob_idx := mem_stdf_uop.rob_idx stdf_clr_bsy_brmask := GetNewBrMask(io.core.brupdate, mem_stdf_uop) } io.core.clr_bsy(memWidth).valid := stdf_clr_bsy_valid && !IsKilledByBranch(io.core.brupdate, stdf_clr_bsy_brmask) && !io.core.exception && !RegNext(io.core.exception) && !RegNext(RegNext(io.core.exception)) io.core.clr_bsy(memWidth).bits := stdf_clr_bsy_rob_idx // Task 2: Do LD-LD. ST-LD searches for ordering failures // Do LD-ST search for forwarding opportunities // We have the opportunity to kill a request we sent last cycle. Use it wisely! // We translated a store last cycle val do_st_search = widthMap(w => (fired_stad_incoming(w) || fired_sta_incoming(w) || fired_sta_retry(w)) && !mem_tlb_miss(w)) // We translated a load last cycle val do_ld_search = widthMap(w => ((fired_load_incoming(w) || fired_load_retry(w)) && !mem_tlb_miss(w)) || fired_load_wakeup(w)) // We are making a local line visible to other harts val do_release_search = widthMap(w => fired_release(w)) // Store addrs don't go to memory yet, get it from the TLB response // Load wakeups don't go through TLB, get it through memory // Load incoming and load retries go through both val lcam_addr = widthMap(w => Mux(fired_stad_incoming(w) || fired_sta_incoming(w) || fired_sta_retry(w), RegNext(exe_tlb_paddr(w)), Mux(fired_release(w), RegNext(io.dmem.release.bits.address), mem_paddr(w)))) val lcam_uop = widthMap(w => Mux(do_st_search(w), mem_stq_e(w).bits.uop, Mux(do_ld_search(w), mem_ldq_e(w).bits.uop, NullMicroOp))) val lcam_mask = widthMap(w => GenByteMask(lcam_addr(w), lcam_uop(w).mem_size)) val lcam_st_dep_mask = widthMap(w => mem_ldq_e(w).bits.st_dep_mask) val lcam_is_release = widthMap(w => fired_release(w)) val lcam_ldq_idx = widthMap(w => Mux(fired_load_incoming(w), mem_incoming_uop(w).ldq_idx, Mux(fired_load_wakeup (w), RegNext(ldq_wakeup_idx), Mux(fired_load_retry (w), RegNext(ldq_retry_idx), 0.U)))) val lcam_stq_idx = widthMap(w => Mux(fired_stad_incoming(w) || fired_sta_incoming (w), mem_incoming_uop(w).stq_idx, Mux(fired_sta_retry (w), RegNext(stq_retry_idx), 0.U))) val can_forward = WireInit(widthMap(w => Mux(fired_load_incoming(w) || fired_load_retry(w), !mem_tlb_uncacheable(w), !ldq(lcam_ldq_idx(w)).bits.addr_is_uncacheable))) // Mask of stores which we conflict on address with val ldst_addr_matches = WireInit(widthMap(w => VecInit((0 until numStqEntries).map(x=>false.B)))) // Mask of stores which we can forward from val ldst_forward_matches = WireInit(widthMap(w => VecInit((0 until numStqEntries).map(x=>false.B)))) val failed_loads = WireInit(VecInit((0 until numLdqEntries).map(x=>false.B))) // Loads which we will report as failures (throws a mini-exception) val nacking_loads = WireInit(VecInit((0 until numLdqEntries).map(x=>false.B))) // Loads which are being nacked by dcache in the next stage val s1_executing_loads = RegNext(s0_executing_loads) val s1_set_execute = WireInit(s1_executing_loads) val mem_forward_valid = Wire(Vec(memWidth, Bool())) val mem_forward_ldq_idx = lcam_ldq_idx val mem_forward_ld_addr = lcam_addr val mem_forward_stq_idx = Wire(Vec(memWidth, UInt(log2Ceil(numStqEntries).W))) val wb_forward_valid = RegNext(mem_forward_valid) val wb_forward_ldq_idx = RegNext(mem_forward_ldq_idx) val wb_forward_ld_addr = RegNext(mem_forward_ld_addr) val wb_forward_stq_idx = RegNext(mem_forward_stq_idx) for (i <- 0 until numLdqEntries) { val l_valid = ldq(i).valid val l_bits = ldq(i).bits val l_addr = ldq(i).bits.addr.bits val l_mask = GenByteMask(l_addr, l_bits.uop.mem_size) val l_forwarders = widthMap(w => wb_forward_valid(w) && wb_forward_ldq_idx(w) === i.U) val l_is_forwarding = l_forwarders.reduce(_||_) val l_forward_stq_idx = Mux(l_is_forwarding, Mux1H(l_forwarders, wb_forward_stq_idx), l_bits.forward_stq_idx) val block_addr_matches = widthMap(w => lcam_addr(w) >> blockOffBits === l_addr >> blockOffBits) val dword_addr_matches = widthMap(w => block_addr_matches(w) && lcam_addr(w)(blockOffBits-1,3) === l_addr(blockOffBits-1,3)) val mask_match = widthMap(w => (l_mask & lcam_mask(w)) === l_mask) val mask_overlap = widthMap(w => (l_mask & lcam_mask(w)).orR) // Searcher is a store for (w <- 0 until memWidth) { when (do_release_search(w) && l_valid && l_bits.addr.valid && block_addr_matches(w)) { // This load has been observed, so if a younger load to the same address has not // executed yet, this load must be squashed ldq(i).bits.observed := true.B } .elsewhen (do_st_search(w) && l_valid && l_bits.addr.valid && (l_bits.executed || l_bits.succeeded || l_is_forwarding) && !l_bits.addr_is_virtual && l_bits.st_dep_mask(lcam_stq_idx(w)) && dword_addr_matches(w) && mask_overlap(w)) { val forwarded_is_older = IsOlder(l_forward_stq_idx, lcam_stq_idx(w), l_bits.youngest_stq_idx) // We are older than this load, which overlapped us. when (!l_bits.forward_std_val || // If the load wasn't forwarded, it definitely failed ((l_forward_stq_idx =/= lcam_stq_idx(w)) && forwarded_is_older)) { // If the load forwarded from us, we might be ok ldq(i).bits.order_fail := true.B failed_loads(i) := true.B } } .elsewhen (do_ld_search(w) && l_valid && l_bits.addr.valid && !l_bits.addr_is_virtual && dword_addr_matches(w) && mask_overlap(w)) { val searcher_is_older = IsOlder(lcam_ldq_idx(w), i.U, ldq_head) when (searcher_is_older) { when ((l_bits.executed || l_bits.succeeded || l_is_forwarding) && !s1_executing_loads(i) && // If the load is proceeding in parallel we don't need to kill it l_bits.observed) { // Its only a ordering failure if the cache line was observed between the younger load and us ldq(i).bits.order_fail := true.B failed_loads(i) := true.B } } .elsewhen (lcam_ldq_idx(w) =/= i.U) { // The load is older, and either it hasn't executed, it was nacked, or it is ignoring its response // we need to kill ourselves, and prevent forwarding val older_nacked = nacking_loads(i) || RegNext(nacking_loads(i)) when (!(l_bits.executed || l_bits.succeeded) || older_nacked) { s1_set_execute(lcam_ldq_idx(w)) := false.B io.dmem.s1_kill(w) := RegNext(dmem_req_fire(w)) can_forward(w) := false.B } } } } } for (i <- 0 until numStqEntries) { val s_addr = stq(i).bits.addr.bits val s_uop = stq(i).bits.uop val dword_addr_matches = widthMap(w => ( stq(i).bits.addr.valid && !stq(i).bits.addr_is_virtual && (s_addr(corePAddrBits-1,3) === lcam_addr(w)(corePAddrBits-1,3)))) val write_mask = GenByteMask(s_addr, s_uop.mem_size) for (w <- 0 until memWidth) { when (do_ld_search(w) && stq(i).valid && lcam_st_dep_mask(w)(i)) { when (((lcam_mask(w) & write_mask) === lcam_mask(w)) && !s_uop.is_fence && !s_uop.is_amo && dword_addr_matches(w) && can_forward(w)) { ldst_addr_matches(w)(i) := true.B ldst_forward_matches(w)(i) := true.B io.dmem.s1_kill(w) := RegNext(dmem_req_fire(w)) s1_set_execute(lcam_ldq_idx(w)) := false.B } .elsewhen (((lcam_mask(w) & write_mask) =/= 0.U) && dword_addr_matches(w)) { ldst_addr_matches(w)(i) := true.B io.dmem.s1_kill(w) := RegNext(dmem_req_fire(w)) s1_set_execute(lcam_ldq_idx(w)) := false.B } .elsewhen (s_uop.is_fence || s_uop.is_amo) { ldst_addr_matches(w)(i) := true.B io.dmem.s1_kill(w) := RegNext(dmem_req_fire(w)) s1_set_execute(lcam_ldq_idx(w)) := false.B } } } } // Set execute bit in LDQ for (i <- 0 until numLdqEntries) { when (s1_set_execute(i)) { ldq(i).bits.executed := true.B } } // Find the youngest store which the load is dependent on val forwarding_age_logic = Seq.fill(memWidth) { Module(new ForwardingAgeLogic(numStqEntries)) } for (w <- 0 until memWidth) { forwarding_age_logic(w).io.addr_matches := ldst_addr_matches(w).asUInt forwarding_age_logic(w).io.youngest_st_idx := lcam_uop(w).stq_idx } val forwarding_idx = widthMap(w => forwarding_age_logic(w).io.forwarding_idx) // Forward if st-ld forwarding is possible from the writemask and loadmask mem_forward_valid := widthMap(w => (ldst_forward_matches(w)(forwarding_idx(w)) && !IsKilledByBranch(io.core.brupdate, lcam_uop(w)) && !io.core.exception && !RegNext(io.core.exception))) mem_forward_stq_idx := forwarding_idx // Avoid deadlock with a 1-w LSU prioritizing load wakeups > store commits // On a 2W machine, load wakeups and store commits occupy separate pipelines, // so only add this logic for 1-w LSU if (memWidth == 1) { // Wakeups may repeatedly find a st->ld addr conflict and fail to forward, // repeated wakeups may block the store from ever committing // Disallow load wakeups 1 cycle after this happens to allow the stores to drain when (RegNext(ldst_addr_matches(0).reduce(_||_) && !mem_forward_valid(0))) { block_load_wakeup := true.B } // If stores remain blocked for 15 cycles, block load wakeups to get a store through val store_blocked_counter = Reg(UInt(4.W)) when (will_fire_store_commit(0) || !can_fire_store_commit(0)) { store_blocked_counter := 0.U } .elsewhen (can_fire_store_commit(0) && !will_fire_store_commit(0)) { store_blocked_counter := Mux(store_blocked_counter === 15.U, 15.U, store_blocked_counter + 1.U) } when (store_blocked_counter === 15.U) { block_load_wakeup := true.B } } // Task 3: Clr unsafe bit in ROB for succesful translations // Delay this a cycle to avoid going ahead of the exception broadcast // The unsafe bit is cleared on the first translation, so no need to fire for load wakeups for (w <- 0 until memWidth) { io.core.clr_unsafe(w).valid := RegNext((do_st_search(w) || do_ld_search(w)) && !fired_load_wakeup(w)) && false.B io.core.clr_unsafe(w).bits := RegNext(lcam_uop(w).rob_idx) } // detect which loads get marked as failures, but broadcast to the ROB the oldest failing load // TODO encapsulate this in an age-based priority-encoder // val l_idx = AgePriorityEncoder((Vec(Vec.tabulate(numLdqEntries)(i => failed_loads(i) && i.U >= laq_head) // ++ failed_loads)).asUInt) val temp_bits = (VecInit(VecInit.tabulate(numLdqEntries)(i => failed_loads(i) && i.U >= ldq_head) ++ failed_loads)).asUInt val l_idx = PriorityEncoder(temp_bits) // one exception port, but multiple causes! // - 1) the incoming store-address finds a faulting load (it is by definition younger) // - 2) the incoming load or store address is excepting. It must be older and thus takes precedent. val r_xcpt_valid = RegInit(false.B) val r_xcpt = Reg(new Exception) val ld_xcpt_valid = failed_loads.reduce(_|_) val ld_xcpt_uop = ldq(Mux(l_idx >= numLdqEntries.U, l_idx - numLdqEntries.U, l_idx)).bits.uop val use_mem_xcpt = (mem_xcpt_valid && IsOlder(mem_xcpt_uop.rob_idx, ld_xcpt_uop.rob_idx, io.core.rob_head_idx)) || !ld_xcpt_valid val xcpt_uop = Mux(use_mem_xcpt, mem_xcpt_uop, ld_xcpt_uop) r_xcpt_valid := (ld_xcpt_valid || mem_xcpt_valid) && !io.core.exception && !IsKilledByBranch(io.core.brupdate, xcpt_uop) r_xcpt.uop := xcpt_uop r_xcpt.uop.br_mask := GetNewBrMask(io.core.brupdate, xcpt_uop) r_xcpt.cause := Mux(use_mem_xcpt, mem_xcpt_cause, MINI_EXCEPTION_MEM_ORDERING) r_xcpt.badvaddr := mem_xcpt_vaddr // TODO is there another register we can use instead? io.core.lxcpt.valid := r_xcpt_valid && !io.core.exception && !IsKilledByBranch(io.core.brupdate, r_xcpt.uop) io.core.lxcpt.bits := r_xcpt // Task 4: Speculatively wakeup loads 1 cycle before they come back for (w <- 0 until memWidth) { io.core.spec_ld_wakeup(w).valid := enableFastLoadUse.B && fired_load_incoming(w) && !mem_incoming_uop(w).fp_val && mem_incoming_uop(w).pdst =/= 0.U io.core.spec_ld_wakeup(w).bits := mem_incoming_uop(w).pdst } //------------------------------------------------------------- //------------------------------------------------------------- // Writeback Cycle (St->Ld Forwarding Path) //------------------------------------------------------------- //------------------------------------------------------------- // Handle Memory Responses and nacks //---------------------------------- for (w <- 0 until memWidth) { io.core.exe(w).iresp.valid := false.B io.core.exe(w).iresp.bits := DontCare io.core.exe(w).fresp.valid := false.B io.core.exe(w).fresp.bits := DontCare } val dmem_resp_fired = WireInit(widthMap(w => false.B)) for (w <- 0 until memWidth) { // Handle nacks when (io.dmem.nack(w).valid) { // We have to re-execute this! when (io.dmem.nack(w).bits.is_hella) { assert(hella_state === h_wait || hella_state === h_dead) } .elsewhen (io.dmem.nack(w).bits.uop.uses_ldq) { assert(ldq(io.dmem.nack(w).bits.uop.ldq_idx).bits.executed) ldq(io.dmem.nack(w).bits.uop.ldq_idx).bits.executed := false.B nacking_loads(io.dmem.nack(w).bits.uop.ldq_idx) := true.B } .otherwise { assert(io.dmem.nack(w).bits.uop.uses_stq) when (IsOlder(io.dmem.nack(w).bits.uop.stq_idx, stq_execute_head, stq_head)) { stq_execute_head := io.dmem.nack(w).bits.uop.stq_idx } } } // Handle the response when (io.dmem.resp(w).valid) { when (io.dmem.resp(w).bits.uop.uses_ldq) { assert(!io.dmem.resp(w).bits.is_hella) val ldq_idx = io.dmem.resp(w).bits.uop.ldq_idx val send_iresp = ldq(ldq_idx).bits.uop.dst_rtype === RT_FIX val send_fresp = ldq(ldq_idx).bits.uop.dst_rtype === RT_FLT io.core.exe(w).iresp.bits.uop := ldq(ldq_idx).bits.uop io.core.exe(w).fresp.bits.uop := ldq(ldq_idx).bits.uop io.core.exe(w).iresp.valid := send_iresp io.core.exe(w).iresp.bits.data := io.dmem.resp(w).bits.data io.core.exe(w).fresp.valid := send_fresp io.core.exe(w).fresp.bits.data := io.dmem.resp(w).bits.data assert(send_iresp ^ send_fresp) dmem_resp_fired(w) := true.B ldq(ldq_idx).bits.succeeded := io.core.exe(w).iresp.valid || io.core.exe(w).fresp.valid ldq(ldq_idx).bits.debug_wb_data := io.dmem.resp(w).bits.data } .elsewhen (io.dmem.resp(w).bits.uop.uses_stq) { assert(!io.dmem.resp(w).bits.is_hella) stq(io.dmem.resp(w).bits.uop.stq_idx).bits.succeeded := true.B when (io.dmem.resp(w).bits.uop.is_amo) { dmem_resp_fired(w) := true.B io.core.exe(w).iresp.valid := true.B io.core.exe(w).iresp.bits.uop := stq(io.dmem.resp(w).bits.uop.stq_idx).bits.uop io.core.exe(w).iresp.bits.data := io.dmem.resp(w).bits.data stq(io.dmem.resp(w).bits.uop.stq_idx).bits.debug_wb_data := io.dmem.resp(w).bits.data } } } when (dmem_resp_fired(w) && wb_forward_valid(w)) { // Twiddle thumbs. Can't forward because dcache response takes precedence } .elsewhen (!dmem_resp_fired(w) && wb_forward_valid(w)) { val f_idx = wb_forward_ldq_idx(w) val forward_uop = ldq(f_idx).bits.uop val stq_e = stq(wb_forward_stq_idx(w)) val data_ready = stq_e.bits.data.valid val live = !IsKilledByBranch(io.core.brupdate, forward_uop) val storegen = new freechips.rocketchip.rocket.StoreGen( stq_e.bits.uop.mem_size, stq_e.bits.addr.bits, stq_e.bits.data.bits, coreDataBytes) val loadgen = new freechips.rocketchip.rocket.LoadGen( forward_uop.mem_size, forward_uop.mem_signed, wb_forward_ld_addr(w), storegen.data, false.B, coreDataBytes) io.core.exe(w).iresp.valid := (forward_uop.dst_rtype === RT_FIX) && data_ready && live io.core.exe(w).fresp.valid := (forward_uop.dst_rtype === RT_FLT) && data_ready && live io.core.exe(w).iresp.bits.uop := forward_uop io.core.exe(w).fresp.bits.uop := forward_uop io.core.exe(w).iresp.bits.data := loadgen.data io.core.exe(w).fresp.bits.data := loadgen.data when (data_ready && live) { ldq(f_idx).bits.succeeded := data_ready ldq(f_idx).bits.forward_std_val := true.B ldq(f_idx).bits.forward_stq_idx := wb_forward_stq_idx(w) ldq(f_idx).bits.debug_wb_data := loadgen.data } } } // Initially assume the speculative load wakeup failed io.core.ld_miss := RegNext(io.core.spec_ld_wakeup.map(_.valid).reduce(_||_)) val spec_ld_succeed = widthMap(w => !RegNext(io.core.spec_ld_wakeup(w).valid) || (io.core.exe(w).iresp.valid && io.core.exe(w).iresp.bits.uop.ldq_idx === RegNext(mem_incoming_uop(w).ldq_idx) ) ).reduce(_&&_) when (spec_ld_succeed) { io.core.ld_miss := false.B } //------------------------------------------------------------- // Kill speculated entries on branch mispredict //------------------------------------------------------------- //------------------------------------------------------------- // Kill stores val st_brkilled_mask = Wire(Vec(numStqEntries, Bool())) for (i <- 0 until numStqEntries) { st_brkilled_mask(i) := false.B when (stq(i).valid) { stq(i).bits.uop.br_mask := GetNewBrMask(io.core.brupdate, stq(i).bits.uop.br_mask) when (IsKilledByBranch(io.core.brupdate, stq(i).bits.uop)) { stq(i).valid := false.B stq(i).bits.addr.valid := false.B stq(i).bits.data.valid := false.B st_brkilled_mask(i) := true.B } } assert (!(IsKilledByBranch(io.core.brupdate, stq(i).bits.uop) && stq(i).valid && stq(i).bits.committed), "Branch is trying to clear a committed store.") } // Kill loads for (i <- 0 until numLdqEntries) { when (ldq(i).valid) { ldq(i).bits.uop.br_mask := GetNewBrMask(io.core.brupdate, ldq(i).bits.uop.br_mask) when (IsKilledByBranch(io.core.brupdate, ldq(i).bits.uop)) { ldq(i).valid := false.B ldq(i).bits.addr.valid := false.B } } } //------------------------------------------------------------- when (io.core.brupdate.b2.mispredict && !io.core.exception) { stq_tail := io.core.brupdate.b2.uop.stq_idx ldq_tail := io.core.brupdate.b2.uop.ldq_idx } //------------------------------------------------------------- //------------------------------------------------------------- // dequeue old entries on commit //------------------------------------------------------------- //------------------------------------------------------------- var temp_stq_commit_head = stq_commit_head var temp_ldq_head = ldq_head for (w <- 0 until coreWidth) { val commit_store = io.core.commit.valids(w) && io.core.commit.uops(w).uses_stq val commit_load = io.core.commit.valids(w) && io.core.commit.uops(w).uses_ldq val idx = Mux(commit_store, temp_stq_commit_head, temp_ldq_head) when (commit_store) { stq(idx).bits.committed := true.B } .elsewhen (commit_load) { assert (ldq(idx).valid, "[lsu] trying to commit an un-allocated load entry.") assert ((ldq(idx).bits.executed || ldq(idx).bits.forward_std_val) && ldq(idx).bits.succeeded , "[lsu] trying to commit an un-executed load entry.") ldq(idx).valid := false.B ldq(idx).bits.addr.valid := false.B ldq(idx).bits.executed := false.B ldq(idx).bits.succeeded := false.B ldq(idx).bits.order_fail := false.B ldq(idx).bits.forward_std_val := false.B } if (MEMTRACE_PRINTF) { when (commit_store || commit_load) { val uop = Mux(commit_store, stq(idx).bits.uop, ldq(idx).bits.uop) val addr = Mux(commit_store, stq(idx).bits.addr.bits, ldq(idx).bits.addr.bits) val stdata = Mux(commit_store, stq(idx).bits.data.bits, 0.U) val wbdata = Mux(commit_store, stq(idx).bits.debug_wb_data, ldq(idx).bits.debug_wb_data) printf("MT %x %x %x %x %x %x %x\n", io.core.tsc_reg, uop.uopc, uop.mem_cmd, uop.mem_size, addr, stdata, wbdata) } } temp_stq_commit_head = Mux(commit_store, WrapInc(temp_stq_commit_head, numStqEntries), temp_stq_commit_head) temp_ldq_head = Mux(commit_load, WrapInc(temp_ldq_head, numLdqEntries), temp_ldq_head) } stq_commit_head := temp_stq_commit_head ldq_head := temp_ldq_head // store has been committed AND successfully sent data to memory when (stq(stq_head).valid && stq(stq_head).bits.committed) { when (stq(stq_head).bits.uop.is_fence && !io.dmem.ordered) { io.dmem.force_order := true.B store_needs_order := true.B } clear_store := Mux(stq(stq_head).bits.uop.is_fence, io.dmem.ordered, stq(stq_head).bits.succeeded) } when (clear_store) { stq(stq_head).valid := false.B stq(stq_head).bits.addr.valid := false.B stq(stq_head).bits.data.valid := false.B stq(stq_head).bits.succeeded := false.B stq(stq_head).bits.committed := false.B stq_head := WrapInc(stq_head, numStqEntries) when (stq(stq_head).bits.uop.is_fence) { stq_execute_head := WrapInc(stq_execute_head, numStqEntries) } } // ----------------------- // Hellacache interface // We need to time things like a HellaCache would io.hellacache.req.ready := false.B io.hellacache.s2_nack := false.B io.hellacache.s2_xcpt := (0.U).asTypeOf(new rocket.HellaCacheExceptions) io.hellacache.resp.valid := false.B io.hellacache.store_pending := stq.map(_.valid).reduce(_||_) when (hella_state === h_ready) { io.hellacache.req.ready := true.B when (io.hellacache.req.fire) { hella_req := io.hellacache.req.bits hella_state := h_s1 } } .elsewhen (hella_state === h_s1) { can_fire_hella_incoming(memWidth-1) := true.B hella_data := io.hellacache.s1_data hella_xcpt := dtlb.io.resp(memWidth-1) when (io.hellacache.s1_kill) { when (will_fire_hella_incoming(memWidth-1) && dmem_req_fire(memWidth-1)) { hella_state := h_dead } .otherwise { hella_state := h_ready } } .elsewhen (will_fire_hella_incoming(memWidth-1) && dmem_req_fire(memWidth-1)) { hella_state := h_s2 } .otherwise { hella_state := h_s2_nack } } .elsewhen (hella_state === h_s2_nack) { io.hellacache.s2_nack := true.B hella_state := h_ready } .elsewhen (hella_state === h_s2) { io.hellacache.s2_xcpt := hella_xcpt when (io.hellacache.s2_kill || hella_xcpt.asUInt =/= 0.U) { hella_state := h_dead } .otherwise { hella_state := h_wait } } .elsewhen (hella_state === h_wait) { for (w <- 0 until memWidth) { when (io.dmem.resp(w).valid && io.dmem.resp(w).bits.is_hella) { hella_state := h_ready io.hellacache.resp.valid := true.B io.hellacache.resp.bits.addr := hella_req.addr io.hellacache.resp.bits.tag := hella_req.tag io.hellacache.resp.bits.cmd := hella_req.cmd io.hellacache.resp.bits.signed := hella_req.signed io.hellacache.resp.bits.size := hella_req.size io.hellacache.resp.bits.data := io.dmem.resp(w).bits.data } .elsewhen (io.dmem.nack(w).valid && io.dmem.nack(w).bits.is_hella) { hella_state := h_replay } } } .elsewhen (hella_state === h_replay) { can_fire_hella_wakeup(memWidth-1) := true.B when (will_fire_hella_wakeup(memWidth-1) && dmem_req_fire(memWidth-1)) { hella_state := h_wait } } .elsewhen (hella_state === h_dead) { for (w <- 0 until memWidth) { when (io.dmem.resp(w).valid && io.dmem.resp(w).bits.is_hella) { hella_state := h_ready } } } //------------------------------------------------------------- // Exception / Reset // for the live_store_mask, need to kill stores that haven't been committed val st_exc_killed_mask = WireInit(VecInit((0 until numStqEntries).map(x=>false.B))) when (reset.asBool || io.core.exception) { ldq_head := 0.U ldq_tail := 0.U when (reset.asBool) { stq_head := 0.U stq_tail := 0.U stq_commit_head := 0.U stq_execute_head := 0.U for (i <- 0 until numStqEntries) { stq(i).valid := false.B stq(i).bits.addr.valid := false.B stq(i).bits.data.valid := false.B stq(i).bits.uop := NullMicroOp } } .otherwise // exception { stq_tail := stq_commit_head for (i <- 0 until numStqEntries) { when (!stq(i).bits.committed && !stq(i).bits.succeeded) { stq(i).valid := false.B stq(i).bits.addr.valid := false.B stq(i).bits.data.valid := false.B st_exc_killed_mask(i) := true.B } } } for (i <- 0 until numLdqEntries) { ldq(i).valid := false.B ldq(i).bits.addr.valid := false.B ldq(i).bits.executed := false.B } } //------------------------------------------------------------- // Live Store Mask // track a bit-array of stores that are alive // (could maybe be re-produced from the stq_head/stq_tail, but need to know include spec_killed entries) // TODO is this the most efficient way to compute the live store mask? live_store_mask := next_live_store_mask & ~(st_brkilled_mask.asUInt) & ~(st_exc_killed_mask.asUInt) } /** * Object to take an address and generate an 8-bit mask of which bytes within a * double-word. */ object GenByteMask { def apply(addr: UInt, size: UInt): UInt = { val mask = Wire(UInt(8.W)) mask := MuxCase(255.U(8.W), Array( (size === 0.U) -> (1.U(8.W) << addr(2,0)), (size === 1.U) -> (3.U(8.W) << (addr(2,1) << 1.U)), (size === 2.U) -> Mux(addr(2), 240.U(8.W), 15.U(8.W)), (size === 3.U) -> 255.U(8.W))) mask } } /** * ... */ class ForwardingAgeLogic(num_entries: Int)(implicit p: Parameters) extends BoomModule()(p) { val io = IO(new Bundle { val addr_matches = Input(UInt(num_entries.W)) // bit vector of addresses that match // between the load and the SAQ val youngest_st_idx = Input(UInt(stqAddrSz.W)) // needed to get "age" val forwarding_val = Output(Bool()) val forwarding_idx = Output(UInt(stqAddrSz.W)) }) // generating mask that zeroes out anything younger than tail val age_mask = Wire(Vec(num_entries, Bool())) for (i <- 0 until num_entries) { age_mask(i) := true.B when (i.U >= io.youngest_st_idx) // currently the tail points PAST last store, so use >= { age_mask(i) := false.B } } // Priority encoder with moving tail: double length val matches = Wire(UInt((2*num_entries).W)) matches := Cat(io.addr_matches & age_mask.asUInt, io.addr_matches) val found_match = Wire(Bool()) found_match := false.B io.forwarding_idx := 0.U // look for youngest, approach from the oldest side, let the last one found stick for (i <- 0 until (2*num_entries)) { when (matches(i)) { found_match := true.B io.forwarding_idx := (i % num_entries).U } } io.forwarding_val := found_match } File util.scala: //****************************************************************************** // Copyright (c) 2015 - 2019, The Regents of the University of California (Regents). // All Rights Reserved. See LICENSE and LICENSE.SiFive for license details. //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ // Utility Functions //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ package boom.v3.util import chisel3._ import chisel3.util._ import freechips.rocketchip.rocket.Instructions._ import freechips.rocketchip.rocket._ import freechips.rocketchip.util.{Str} import org.chipsalliance.cde.config.{Parameters} import freechips.rocketchip.tile.{TileKey} import boom.v3.common.{MicroOp} import boom.v3.exu.{BrUpdateInfo} /** * Object to XOR fold a input register of fullLength into a compressedLength. */ object Fold { def apply(input: UInt, compressedLength: Int, fullLength: Int): UInt = { val clen = compressedLength val hlen = fullLength if (hlen <= clen) { input } else { var res = 0.U(clen.W) var remaining = input.asUInt for (i <- 0 to hlen-1 by clen) { val len = if (i + clen > hlen ) (hlen - i) else clen require(len > 0) res = res(clen-1,0) ^ remaining(len-1,0) remaining = remaining >> len.U } res } } } /** * Object to check if MicroOp was killed due to a branch mispredict. * Uses "Fast" branch masks */ object IsKilledByBranch { def apply(brupdate: BrUpdateInfo, uop: MicroOp): Bool = { return maskMatch(brupdate.b1.mispredict_mask, uop.br_mask) } def apply(brupdate: BrUpdateInfo, uop_mask: UInt): Bool = { return maskMatch(brupdate.b1.mispredict_mask, uop_mask) } } /** * Object to return new MicroOp with a new BR mask given a MicroOp mask * and old BR mask. */ object GetNewUopAndBrMask { def apply(uop: MicroOp, brupdate: BrUpdateInfo) (implicit p: Parameters): MicroOp = { val newuop = WireInit(uop) newuop.br_mask := uop.br_mask & ~brupdate.b1.resolve_mask newuop } } /** * Object to return a BR mask given a MicroOp mask and old BR mask. */ object GetNewBrMask { def apply(brupdate: BrUpdateInfo, uop: MicroOp): UInt = { return uop.br_mask & ~brupdate.b1.resolve_mask } def apply(brupdate: BrUpdateInfo, br_mask: UInt): UInt = { return br_mask & ~brupdate.b1.resolve_mask } } object UpdateBrMask { def apply(brupdate: BrUpdateInfo, uop: MicroOp): MicroOp = { val out = WireInit(uop) out.br_mask := GetNewBrMask(brupdate, uop) out } def apply[T <: boom.v3.common.HasBoomUOP](brupdate: BrUpdateInfo, bundle: T): T = { val out = WireInit(bundle) out.uop.br_mask := GetNewBrMask(brupdate, bundle.uop.br_mask) out } def apply[T <: boom.v3.common.HasBoomUOP](brupdate: BrUpdateInfo, bundle: Valid[T]): Valid[T] = { val out = WireInit(bundle) out.bits.uop.br_mask := GetNewBrMask(brupdate, bundle.bits.uop.br_mask) out.valid := bundle.valid && !IsKilledByBranch(brupdate, bundle.bits.uop.br_mask) out } } /** * Object to check if at least 1 bit matches in two masks */ object maskMatch { def apply(msk1: UInt, msk2: UInt): Bool = (msk1 & msk2) =/= 0.U } /** * Object to clear one bit in a mask given an index */ object clearMaskBit { def apply(msk: UInt, idx: UInt): UInt = (msk & ~(1.U << idx))(msk.getWidth-1, 0) } /** * Object to shift a register over by one bit and concat a new one */ object PerformShiftRegister { def apply(reg_val: UInt, new_bit: Bool): UInt = { reg_val := Cat(reg_val(reg_val.getWidth-1, 0).asUInt, new_bit.asUInt).asUInt reg_val } } /** * Object to shift a register over by one bit, wrapping the top bit around to the bottom * (XOR'ed with a new-bit), and evicting a bit at index HLEN. * This is used to simulate a longer HLEN-width shift register that is folded * down to a compressed CLEN. */ object PerformCircularShiftRegister { def apply(csr: UInt, new_bit: Bool, evict_bit: Bool, hlen: Int, clen: Int): UInt = { val carry = csr(clen-1) val newval = Cat(csr, new_bit ^ carry) ^ (evict_bit << (hlen % clen).U) newval } } /** * Object to increment an input value, wrapping it if * necessary. */ object WrapAdd { // "n" is the number of increments, so we wrap at n-1. def apply(value: UInt, amt: UInt, n: Int): UInt = { if (isPow2(n)) { (value + amt)(log2Ceil(n)-1,0) } else { val sum = Cat(0.U(1.W), value) + Cat(0.U(1.W), amt) Mux(sum >= n.U, sum - n.U, sum) } } } /** * Object to decrement an input value, wrapping it if * necessary. */ object WrapSub { // "n" is the number of increments, so we wrap to n-1. def apply(value: UInt, amt: Int, n: Int): UInt = { if (isPow2(n)) { (value - amt.U)(log2Ceil(n)-1,0) } else { val v = Cat(0.U(1.W), value) val b = Cat(0.U(1.W), amt.U) Mux(value >= amt.U, value - amt.U, n.U - amt.U + value) } } } /** * Object to increment an input value, wrapping it if * necessary. */ object WrapInc { // "n" is the number of increments, so we wrap at n-1. def apply(value: UInt, n: Int): UInt = { if (isPow2(n)) { (value + 1.U)(log2Ceil(n)-1,0) } else { val wrap = (value === (n-1).U) Mux(wrap, 0.U, value + 1.U) } } } /** * Object to decrement an input value, wrapping it if * necessary. */ object WrapDec { // "n" is the number of increments, so we wrap at n-1. def apply(value: UInt, n: Int): UInt = { if (isPow2(n)) { (value - 1.U)(log2Ceil(n)-1,0) } else { val wrap = (value === 0.U) Mux(wrap, (n-1).U, value - 1.U) } } } /** * Object to mask off lower bits of a PC to align to a "b" * Byte boundary. */ object AlignPCToBoundary { def apply(pc: UInt, b: Int): UInt = { // Invert for scenario where pc longer than b // (which would clear all bits above size(b)). ~(~pc | (b-1).U) } } /** * Object to rotate a signal left by one */ object RotateL1 { def apply(signal: UInt): UInt = { val w = signal.getWidth val out = Cat(signal(w-2,0), signal(w-1)) return out } } /** * Object to sext a value to a particular length. */ object Sext { def apply(x: UInt, length: Int): UInt = { if (x.getWidth == length) return x else return Cat(Fill(length-x.getWidth, x(x.getWidth-1)), x) } } /** * Object to translate from BOOM's special "packed immediate" to a 32b signed immediate * Asking for U-type gives it shifted up 12 bits. */ object ImmGen { import boom.v3.common.{LONGEST_IMM_SZ, IS_B, IS_I, IS_J, IS_S, IS_U} def apply(ip: UInt, isel: UInt): SInt = { val sign = ip(LONGEST_IMM_SZ-1).asSInt val i30_20 = Mux(isel === IS_U, ip(18,8).asSInt, sign) val i19_12 = Mux(isel === IS_U || isel === IS_J, ip(7,0).asSInt, sign) val i11 = Mux(isel === IS_U, 0.S, Mux(isel === IS_J || isel === IS_B, ip(8).asSInt, sign)) val i10_5 = Mux(isel === IS_U, 0.S, ip(18,14).asSInt) val i4_1 = Mux(isel === IS_U, 0.S, ip(13,9).asSInt) val i0 = Mux(isel === IS_S || isel === IS_I, ip(8).asSInt, 0.S) return Cat(sign, i30_20, i19_12, i11, i10_5, i4_1, i0).asSInt } } /** * Object to get the FP rounding mode out of a packed immediate. */ object ImmGenRm { def apply(ip: UInt): UInt = { return ip(2,0) } } /** * Object to get the FP function fype from a packed immediate. * Note: only works if !(IS_B or IS_S) */ object ImmGenTyp { def apply(ip: UInt): UInt = { return ip(9,8) } } /** * Object to see if an instruction is a JALR. */ object DebugIsJALR { def apply(inst: UInt): Bool = { // TODO Chisel not sure why this won't compile // val is_jalr = rocket.DecodeLogic(inst, List(Bool(false)), // Array( // JALR -> Bool(true))) inst(6,0) === "b1100111".U } } /** * Object to take an instruction and output its branch or jal target. Only used * for a debug assert (no where else would we jump straight from instruction * bits to a target). */ object DebugGetBJImm { def apply(inst: UInt): UInt = { // TODO Chisel not sure why this won't compile //val csignals = //rocket.DecodeLogic(inst, // List(Bool(false), Bool(false)), // Array( // BEQ -> List(Bool(true ), Bool(false)), // BNE -> List(Bool(true ), Bool(false)), // BGE -> List(Bool(true ), Bool(false)), // BGEU -> List(Bool(true ), Bool(false)), // BLT -> List(Bool(true ), Bool(false)), // BLTU -> List(Bool(true ), Bool(false)) // )) //val is_br :: nothing :: Nil = csignals val is_br = (inst(6,0) === "b1100011".U) val br_targ = Cat(Fill(12, inst(31)), Fill(8,inst(31)), inst(7), inst(30,25), inst(11,8), 0.U(1.W)) val jal_targ= Cat(Fill(12, inst(31)), inst(19,12), inst(20), inst(30,25), inst(24,21), 0.U(1.W)) Mux(is_br, br_targ, jal_targ) } } /** * Object to return the lowest bit position after the head. */ object AgePriorityEncoder { def apply(in: Seq[Bool], head: UInt): UInt = { val n = in.size val width = log2Ceil(in.size) val n_padded = 1 << width val temp_vec = (0 until n_padded).map(i => if (i < n) in(i) && i.U >= head else false.B) ++ in val idx = PriorityEncoder(temp_vec) idx(width-1, 0) //discard msb } } /** * Object to determine whether queue * index i0 is older than index i1. */ object IsOlder { def apply(i0: UInt, i1: UInt, head: UInt) = ((i0 < i1) ^ (i0 < head) ^ (i1 < head)) } /** * Set all bits at or below the highest order '1'. */ object MaskLower { def apply(in: UInt) = { val n = in.getWidth (0 until n).map(i => in >> i.U).reduce(_|_) } } /** * Set all bits at or above the lowest order '1'. */ object MaskUpper { def apply(in: UInt) = { val n = in.getWidth (0 until n).map(i => (in << i.U)(n-1,0)).reduce(_|_) } } /** * Transpose a matrix of Chisel Vecs. */ object Transpose { def apply[T <: chisel3.Data](in: Vec[Vec[T]]) = { val n = in(0).size VecInit((0 until n).map(i => VecInit(in.map(row => row(i))))) } } /** * N-wide one-hot priority encoder. */ object SelectFirstN { def apply(in: UInt, n: Int) = { val sels = Wire(Vec(n, UInt(in.getWidth.W))) var mask = in for (i <- 0 until n) { sels(i) := PriorityEncoderOH(mask) mask = mask & ~sels(i) } sels } } /** * Connect the first k of n valid input interfaces to k output interfaces. */ class Compactor[T <: chisel3.Data](n: Int, k: Int, gen: T) extends Module { require(n >= k) val io = IO(new Bundle { val in = Vec(n, Flipped(DecoupledIO(gen))) val out = Vec(k, DecoupledIO(gen)) }) if (n == k) { io.out <> io.in } else { val counts = io.in.map(_.valid).scanLeft(1.U(k.W)) ((c,e) => Mux(e, (c<<1)(k-1,0), c)) val sels = Transpose(VecInit(counts map (c => VecInit(c.asBools)))) map (col => (col zip io.in.map(_.valid)) map {case (c,v) => c && v}) val in_readys = counts map (row => (row.asBools zip io.out.map(_.ready)) map {case (c,r) => c && r} reduce (_||_)) val out_valids = sels map (col => col.reduce(_||_)) val out_data = sels map (s => Mux1H(s, io.in.map(_.bits))) in_readys zip io.in foreach {case (r,i) => i.ready := r} out_valids zip out_data zip io.out foreach {case ((v,d),o) => o.valid := v; o.bits := d} } } /** * Create a queue that can be killed with a branch kill signal. * Assumption: enq.valid only high if not killed by branch (so don't check IsKilled on io.enq). */ class BranchKillableQueue[T <: boom.v3.common.HasBoomUOP](gen: T, entries: Int, flush_fn: boom.v3.common.MicroOp => Bool = u => true.B, flow: Boolean = true) (implicit p: org.chipsalliance.cde.config.Parameters) extends boom.v3.common.BoomModule()(p) with boom.v3.common.HasBoomCoreParameters { val io = IO(new Bundle { val enq = Flipped(Decoupled(gen)) val deq = Decoupled(gen) val brupdate = Input(new BrUpdateInfo()) val flush = Input(Bool()) val empty = Output(Bool()) val count = Output(UInt(log2Ceil(entries).W)) }) val ram = Mem(entries, gen) val valids = RegInit(VecInit(Seq.fill(entries) {false.B})) val uops = Reg(Vec(entries, new MicroOp)) val enq_ptr = Counter(entries) val deq_ptr = Counter(entries) val maybe_full = RegInit(false.B) val ptr_match = enq_ptr.value === deq_ptr.value io.empty := ptr_match && !maybe_full val full = ptr_match && maybe_full val do_enq = WireInit(io.enq.fire) val do_deq = WireInit((io.deq.ready || !valids(deq_ptr.value)) && !io.empty) for (i <- 0 until entries) { val mask = uops(i).br_mask val uop = uops(i) valids(i) := valids(i) && !IsKilledByBranch(io.brupdate, mask) && !(io.flush && flush_fn(uop)) when (valids(i)) { uops(i).br_mask := GetNewBrMask(io.brupdate, mask) } } when (do_enq) { ram(enq_ptr.value) := io.enq.bits valids(enq_ptr.value) := true.B //!IsKilledByBranch(io.brupdate, io.enq.bits.uop) uops(enq_ptr.value) := io.enq.bits.uop uops(enq_ptr.value).br_mask := GetNewBrMask(io.brupdate, io.enq.bits.uop) enq_ptr.inc() } when (do_deq) { valids(deq_ptr.value) := false.B deq_ptr.inc() } when (do_enq =/= do_deq) { maybe_full := do_enq } io.enq.ready := !full val out = Wire(gen) out := ram(deq_ptr.value) out.uop := uops(deq_ptr.value) io.deq.valid := !io.empty && valids(deq_ptr.value) && !IsKilledByBranch(io.brupdate, out.uop) && !(io.flush && flush_fn(out.uop)) io.deq.bits := out io.deq.bits.uop.br_mask := GetNewBrMask(io.brupdate, out.uop) // For flow queue behavior. if (flow) { when (io.empty) { io.deq.valid := io.enq.valid //&& !IsKilledByBranch(io.brupdate, io.enq.bits.uop) io.deq.bits := io.enq.bits io.deq.bits.uop.br_mask := GetNewBrMask(io.brupdate, io.enq.bits.uop) do_deq := false.B when (io.deq.ready) { do_enq := false.B } } } private val ptr_diff = enq_ptr.value - deq_ptr.value if (isPow2(entries)) { io.count := Cat(maybe_full && ptr_match, ptr_diff) } else { io.count := Mux(ptr_match, Mux(maybe_full, entries.asUInt, 0.U), Mux(deq_ptr.value > enq_ptr.value, entries.asUInt + ptr_diff, ptr_diff)) } } // ------------------------------------------ // Printf helper functions // ------------------------------------------ object BoolToChar { /** * Take in a Chisel Bool and convert it into a Str * based on the Chars given * * @param c_bool Chisel Bool * @param trueChar Scala Char if bool is true * @param falseChar Scala Char if bool is false * @return UInt ASCII Char for "trueChar" or "falseChar" */ def apply(c_bool: Bool, trueChar: Char, falseChar: Char = '-'): UInt = { Mux(c_bool, Str(trueChar), Str(falseChar)) } } object CfiTypeToChars { /** * Get a Vec of Strs that can be used for printing * * @param cfi_type specific cfi type * @return Vec of Strs (must be indexed to get specific char) */ def apply(cfi_type: UInt) = { val strings = Seq("----", "BR ", "JAL ", "JALR") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(cfi_type) } } object BpdTypeToChars { /** * Get a Vec of Strs that can be used for printing * * @param bpd_type specific bpd type * @return Vec of Strs (must be indexed to get specific char) */ def apply(bpd_type: UInt) = { val strings = Seq("BR ", "JUMP", "----", "RET ", "----", "CALL", "----", "----") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(bpd_type) } } object RobTypeToChars { /** * Get a Vec of Strs that can be used for printing * * @param rob_type specific rob type * @return Vec of Strs (must be indexed to get specific char) */ def apply(rob_type: UInt) = { val strings = Seq("RST", "NML", "RBK", " WT") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(rob_type) } } object XRegToChars { /** * Get a Vec of Strs that can be used for printing * * @param xreg specific register number * @return Vec of Strs (must be indexed to get specific char) */ def apply(xreg: UInt) = { val strings = Seq(" x0", " ra", " sp", " gp", " tp", " t0", " t1", " t2", " s0", " s1", " a0", " a1", " a2", " a3", " a4", " a5", " a6", " a7", " s2", " s3", " s4", " s5", " s6", " s7", " s8", " s9", "s10", "s11", " t3", " t4", " t5", " t6") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(xreg) } } object FPRegToChars { /** * Get a Vec of Strs that can be used for printing * * @param fpreg specific register number * @return Vec of Strs (must be indexed to get specific char) */ def apply(fpreg: UInt) = { val strings = Seq(" ft0", " ft1", " ft2", " ft3", " ft4", " ft5", " ft6", " ft7", " fs0", " fs1", " fa0", " fa1", " fa2", " fa3", " fa4", " fa5", " fa6", " fa7", " fs2", " fs3", " fs4", " fs5", " fs6", " fs7", " fs8", " fs9", "fs10", "fs11", " ft8", " ft9", "ft10", "ft11") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(fpreg) } } object BoomCoreStringPrefix { /** * Add prefix to BOOM strings (currently only adds the hartId) * * @param strs list of strings * @return String combining the list with the prefix per line */ def apply(strs: String*)(implicit p: Parameters) = { val prefix = "[C" + s"${p(TileKey).tileId}" + "] " strs.map(str => prefix + str + "\n").mkString("") } } File consts.scala: //****************************************************************************** // Copyright (c) 2011 - 2018, The Regents of the University of California (Regents). // All Rights Reserved. See LICENSE and LICENSE.SiFive for license details. //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ // RISCV Processor Constants //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ package boom.v3.common.constants import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util.Str import freechips.rocketchip.rocket.RVCExpander /** * Mixin for issue queue types */ trait IQType { val IQT_SZ = 3 val IQT_INT = 1.U(IQT_SZ.W) val IQT_MEM = 2.U(IQT_SZ.W) val IQT_FP = 4.U(IQT_SZ.W) val IQT_MFP = 6.U(IQT_SZ.W) } /** * Mixin for scalar operation constants */ trait ScalarOpConstants { val X = BitPat("b?") val Y = BitPat("b1") val N = BitPat("b0") //************************************ // Extra Constants // Which branch predictor predicted us val BSRC_SZ = 2 val BSRC_1 = 0.U(BSRC_SZ.W) // 1-cycle branch pred val BSRC_2 = 1.U(BSRC_SZ.W) // 2-cycle branch pred val BSRC_3 = 2.U(BSRC_SZ.W) // 3-cycle branch pred val BSRC_C = 3.U(BSRC_SZ.W) // core branch resolution //************************************ // Control Signals // CFI types val CFI_SZ = 3 val CFI_X = 0.U(CFI_SZ.W) // Not a CFI instruction val CFI_BR = 1.U(CFI_SZ.W) // Branch val CFI_JAL = 2.U(CFI_SZ.W) // JAL val CFI_JALR = 3.U(CFI_SZ.W) // JALR // PC Select Signal val PC_PLUS4 = 0.U(2.W) // PC + 4 val PC_BRJMP = 1.U(2.W) // brjmp_target val PC_JALR = 2.U(2.W) // jump_reg_target // Branch Type val BR_N = 0.U(4.W) // Next val BR_NE = 1.U(4.W) // Branch on NotEqual val BR_EQ = 2.U(4.W) // Branch on Equal val BR_GE = 3.U(4.W) // Branch on Greater/Equal val BR_GEU = 4.U(4.W) // Branch on Greater/Equal Unsigned val BR_LT = 5.U(4.W) // Branch on Less Than val BR_LTU = 6.U(4.W) // Branch on Less Than Unsigned val BR_J = 7.U(4.W) // Jump val BR_JR = 8.U(4.W) // Jump Register // RS1 Operand Select Signal val OP1_RS1 = 0.U(2.W) // Register Source #1 val OP1_ZERO= 1.U(2.W) val OP1_PC = 2.U(2.W) val OP1_X = BitPat("b??") // RS2 Operand Select Signal val OP2_RS2 = 0.U(3.W) // Register Source #2 val OP2_IMM = 1.U(3.W) // immediate val OP2_ZERO= 2.U(3.W) // constant 0 val OP2_NEXT= 3.U(3.W) // constant 2/4 (for PC+2/4) val OP2_IMMC= 4.U(3.W) // for CSR imm found in RS1 val OP2_X = BitPat("b???") // Register File Write Enable Signal val REN_0 = false.B val REN_1 = true.B // Is 32b Word or 64b Doubldword? val SZ_DW = 1 val DW_X = true.B // Bool(xLen==64) val DW_32 = false.B val DW_64 = true.B val DW_XPR = true.B // Bool(xLen==64) // Memory Enable Signal val MEN_0 = false.B val MEN_1 = true.B val MEN_X = false.B // Immediate Extend Select val IS_I = 0.U(3.W) // I-Type (LD,ALU) val IS_S = 1.U(3.W) // S-Type (ST) val IS_B = 2.U(3.W) // SB-Type (BR) val IS_U = 3.U(3.W) // U-Type (LUI/AUIPC) val IS_J = 4.U(3.W) // UJ-Type (J/JAL) val IS_X = BitPat("b???") // Decode Stage Control Signals val RT_FIX = 0.U(2.W) val RT_FLT = 1.U(2.W) val RT_PAS = 3.U(2.W) // pass-through (prs1 := lrs1, etc) val RT_X = 2.U(2.W) // not-a-register (but shouldn't get a busy-bit, etc.) // TODO rename RT_NAR // Micro-op opcodes // TODO change micro-op opcodes into using enum val UOPC_SZ = 7 val uopX = BitPat.dontCare(UOPC_SZ) val uopNOP = 0.U(UOPC_SZ.W) val uopLD = 1.U(UOPC_SZ.W) val uopSTA = 2.U(UOPC_SZ.W) // store address generation val uopSTD = 3.U(UOPC_SZ.W) // store data generation val uopLUI = 4.U(UOPC_SZ.W) val uopADDI = 5.U(UOPC_SZ.W) val uopANDI = 6.U(UOPC_SZ.W) val uopORI = 7.U(UOPC_SZ.W) val uopXORI = 8.U(UOPC_SZ.W) val uopSLTI = 9.U(UOPC_SZ.W) val uopSLTIU= 10.U(UOPC_SZ.W) val uopSLLI = 11.U(UOPC_SZ.W) val uopSRAI = 12.U(UOPC_SZ.W) val uopSRLI = 13.U(UOPC_SZ.W) val uopSLL = 14.U(UOPC_SZ.W) val uopADD = 15.U(UOPC_SZ.W) val uopSUB = 16.U(UOPC_SZ.W) val uopSLT = 17.U(UOPC_SZ.W) val uopSLTU = 18.U(UOPC_SZ.W) val uopAND = 19.U(UOPC_SZ.W) val uopOR = 20.U(UOPC_SZ.W) val uopXOR = 21.U(UOPC_SZ.W) val uopSRA = 22.U(UOPC_SZ.W) val uopSRL = 23.U(UOPC_SZ.W) val uopBEQ = 24.U(UOPC_SZ.W) val uopBNE = 25.U(UOPC_SZ.W) val uopBGE = 26.U(UOPC_SZ.W) val uopBGEU = 27.U(UOPC_SZ.W) val uopBLT = 28.U(UOPC_SZ.W) val uopBLTU = 29.U(UOPC_SZ.W) val uopCSRRW= 30.U(UOPC_SZ.W) val uopCSRRS= 31.U(UOPC_SZ.W) val uopCSRRC= 32.U(UOPC_SZ.W) val uopCSRRWI=33.U(UOPC_SZ.W) val uopCSRRSI=34.U(UOPC_SZ.W) val uopCSRRCI=35.U(UOPC_SZ.W) val uopJ = 36.U(UOPC_SZ.W) val uopJAL = 37.U(UOPC_SZ.W) val uopJALR = 38.U(UOPC_SZ.W) val uopAUIPC= 39.U(UOPC_SZ.W) //val uopSRET = 40.U(UOPC_SZ.W) val uopCFLSH= 41.U(UOPC_SZ.W) val uopFENCE= 42.U(UOPC_SZ.W) val uopADDIW= 43.U(UOPC_SZ.W) val uopADDW = 44.U(UOPC_SZ.W) val uopSUBW = 45.U(UOPC_SZ.W) val uopSLLIW= 46.U(UOPC_SZ.W) val uopSLLW = 47.U(UOPC_SZ.W) val uopSRAIW= 48.U(UOPC_SZ.W) val uopSRAW = 49.U(UOPC_SZ.W) val uopSRLIW= 50.U(UOPC_SZ.W) val uopSRLW = 51.U(UOPC_SZ.W) val uopMUL = 52.U(UOPC_SZ.W) val uopMULH = 53.U(UOPC_SZ.W) val uopMULHU= 54.U(UOPC_SZ.W) val uopMULHSU=55.U(UOPC_SZ.W) val uopMULW = 56.U(UOPC_SZ.W) val uopDIV = 57.U(UOPC_SZ.W) val uopDIVU = 58.U(UOPC_SZ.W) val uopREM = 59.U(UOPC_SZ.W) val uopREMU = 60.U(UOPC_SZ.W) val uopDIVW = 61.U(UOPC_SZ.W) val uopDIVUW= 62.U(UOPC_SZ.W) val uopREMW = 63.U(UOPC_SZ.W) val uopREMUW= 64.U(UOPC_SZ.W) val uopFENCEI = 65.U(UOPC_SZ.W) // = 66.U(UOPC_SZ.W) val uopAMO_AG = 67.U(UOPC_SZ.W) // AMO-address gen (use normal STD for datagen) val uopFMV_W_X = 68.U(UOPC_SZ.W) val uopFMV_D_X = 69.U(UOPC_SZ.W) val uopFMV_X_W = 70.U(UOPC_SZ.W) val uopFMV_X_D = 71.U(UOPC_SZ.W) val uopFSGNJ_S = 72.U(UOPC_SZ.W) val uopFSGNJ_D = 73.U(UOPC_SZ.W) val uopFCVT_S_D = 74.U(UOPC_SZ.W) val uopFCVT_D_S = 75.U(UOPC_SZ.W) val uopFCVT_S_X = 76.U(UOPC_SZ.W) val uopFCVT_D_X = 77.U(UOPC_SZ.W) val uopFCVT_X_S = 78.U(UOPC_SZ.W) val uopFCVT_X_D = 79.U(UOPC_SZ.W) val uopCMPR_S = 80.U(UOPC_SZ.W) val uopCMPR_D = 81.U(UOPC_SZ.W) val uopFCLASS_S = 82.U(UOPC_SZ.W) val uopFCLASS_D = 83.U(UOPC_SZ.W) val uopFMINMAX_S = 84.U(UOPC_SZ.W) val uopFMINMAX_D = 85.U(UOPC_SZ.W) // = 86.U(UOPC_SZ.W) val uopFADD_S = 87.U(UOPC_SZ.W) val uopFSUB_S = 88.U(UOPC_SZ.W) val uopFMUL_S = 89.U(UOPC_SZ.W) val uopFADD_D = 90.U(UOPC_SZ.W) val uopFSUB_D = 91.U(UOPC_SZ.W) val uopFMUL_D = 92.U(UOPC_SZ.W) val uopFMADD_S = 93.U(UOPC_SZ.W) val uopFMSUB_S = 94.U(UOPC_SZ.W) val uopFNMADD_S = 95.U(UOPC_SZ.W) val uopFNMSUB_S = 96.U(UOPC_SZ.W) val uopFMADD_D = 97.U(UOPC_SZ.W) val uopFMSUB_D = 98.U(UOPC_SZ.W) val uopFNMADD_D = 99.U(UOPC_SZ.W) val uopFNMSUB_D = 100.U(UOPC_SZ.W) val uopFDIV_S = 101.U(UOPC_SZ.W) val uopFDIV_D = 102.U(UOPC_SZ.W) val uopFSQRT_S = 103.U(UOPC_SZ.W) val uopFSQRT_D = 104.U(UOPC_SZ.W) val uopWFI = 105.U(UOPC_SZ.W) // pass uop down the CSR pipeline val uopERET = 106.U(UOPC_SZ.W) // pass uop down the CSR pipeline, also is ERET val uopSFENCE = 107.U(UOPC_SZ.W) val uopROCC = 108.U(UOPC_SZ.W) val uopMOV = 109.U(UOPC_SZ.W) // conditional mov decoded from "add rd, x0, rs2" // The Bubble Instruction (Machine generated NOP) // Insert (XOR x0,x0,x0) which is different from software compiler // generated NOPs which are (ADDI x0, x0, 0). // Reasoning for this is to let visualizers and stat-trackers differentiate // between software NOPs and machine-generated Bubbles in the pipeline. val BUBBLE = (0x4033).U(32.W) def NullMicroOp()(implicit p: Parameters): boom.v3.common.MicroOp = { val uop = Wire(new boom.v3.common.MicroOp) uop := DontCare // Overridden in the following lines uop.uopc := uopNOP // maybe not required, but helps on asserts that try to catch spurious behavior uop.bypassable := false.B uop.fp_val := false.B uop.uses_stq := false.B uop.uses_ldq := false.B uop.pdst := 0.U uop.dst_rtype := RT_X val cs = Wire(new boom.v3.common.CtrlSignals()) cs := DontCare // Overridden in the following lines cs.br_type := BR_N cs.csr_cmd := freechips.rocketchip.rocket.CSR.N cs.is_load := false.B cs.is_sta := false.B cs.is_std := false.B uop.ctrl := cs uop } } /** * Mixin for RISCV constants */ trait RISCVConstants { // abstract out instruction decode magic numbers val RD_MSB = 11 val RD_LSB = 7 val RS1_MSB = 19 val RS1_LSB = 15 val RS2_MSB = 24 val RS2_LSB = 20 val RS3_MSB = 31 val RS3_LSB = 27 val CSR_ADDR_MSB = 31 val CSR_ADDR_LSB = 20 val CSR_ADDR_SZ = 12 // location of the fifth bit in the shamt (for checking for illegal ops for SRAIW,etc.) val SHAMT_5_BIT = 25 val LONGEST_IMM_SZ = 20 val X0 = 0.U val RA = 1.U // return address register // memory consistency model // The C/C++ atomics MCM requires that two loads to the same address maintain program order. // The Cortex A9 does NOT enforce load/load ordering (which leads to buggy behavior). val MCM_ORDER_DEPENDENT_LOADS = true val jal_opc = (0x6f).U val jalr_opc = (0x67).U def GetUop(inst: UInt): UInt = inst(6,0) def GetRd (inst: UInt): UInt = inst(RD_MSB,RD_LSB) def GetRs1(inst: UInt): UInt = inst(RS1_MSB,RS1_LSB) def ExpandRVC(inst: UInt)(implicit p: Parameters): UInt = { val rvc_exp = Module(new RVCExpander) rvc_exp.io.in := inst Mux(rvc_exp.io.rvc, rvc_exp.io.out.bits, inst) } // Note: Accepts only EXPANDED rvc instructions def ComputeBranchTarget(pc: UInt, inst: UInt, xlen: Int)(implicit p: Parameters): UInt = { val b_imm32 = Cat(Fill(20,inst(31)), inst(7), inst(30,25), inst(11,8), 0.U(1.W)) ((pc.asSInt + b_imm32.asSInt).asSInt & (-2).S).asUInt } // Note: Accepts only EXPANDED rvc instructions def ComputeJALTarget(pc: UInt, inst: UInt, xlen: Int)(implicit p: Parameters): UInt = { val j_imm32 = Cat(Fill(12,inst(31)), inst(19,12), inst(20), inst(30,25), inst(24,21), 0.U(1.W)) ((pc.asSInt + j_imm32.asSInt).asSInt & (-2).S).asUInt } // Note: Accepts only EXPANDED rvc instructions def GetCfiType(inst: UInt)(implicit p: Parameters): UInt = { val bdecode = Module(new boom.v3.exu.BranchDecode) bdecode.io.inst := inst bdecode.io.pc := 0.U bdecode.io.out.cfi_type } } /** * Mixin for exception cause constants */ trait ExcCauseConstants { // a memory disambigious misspeculation occurred val MINI_EXCEPTION_MEM_ORDERING = 16.U val MINI_EXCEPTION_CSR_REPLAY = 17.U require (!freechips.rocketchip.rocket.Causes.all.contains(16)) require (!freechips.rocketchip.rocket.Causes.all.contains(17)) } File AMOALU.scala: // See LICENSE.SiFive for license details. // See LICENSE.Berkeley for license details. package freechips.rocketchip.rocket import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.Parameters class StoreGen(typ: UInt, addr: UInt, dat: UInt, maxSize: Int) { val size = Wire(UInt(log2Up(log2Up(maxSize)+1).W)) size := typ val dat_padded = dat.pad(maxSize*8) def misaligned: Bool = (addr & ((1.U << size) - 1.U)(log2Up(maxSize)-1,0)).orR def mask = { var res = 1.U for (i <- 0 until log2Up(maxSize)) { val upper = Mux(addr(i), res, 0.U) | Mux(size >= (i+1).U, ((BigInt(1) << (1 << i))-1).U, 0.U) val lower = Mux(addr(i), 0.U, res) res = Cat(upper, lower) } res } protected def genData(i: Int): UInt = if (i >= log2Up(maxSize)) dat_padded else Mux(size === i.U, Fill(1 << (log2Up(maxSize)-i), dat_padded((8 << i)-1,0)), genData(i+1)) def data = genData(0) def wordData = genData(2) } class LoadGen(typ: UInt, signed: Bool, addr: UInt, dat: UInt, zero: Bool, maxSize: Int) { private val size = new StoreGen(typ, addr, dat, maxSize).size private def genData(logMinSize: Int): UInt = { var res = dat for (i <- log2Up(maxSize)-1 to logMinSize by -1) { val pos = 8 << i val shifted = Mux(addr(i), res(2*pos-1,pos), res(pos-1,0)) val doZero = (i == 0).B && zero val zeroed = Mux(doZero, 0.U, shifted) res = Cat(Mux(size === i.U || doZero, Fill(8*maxSize-pos, signed && zeroed(pos-1)), res(8*maxSize-1,pos)), zeroed) } res } def wordData = genData(2) def data = genData(0) } class AMOALU(operandBits: Int)(implicit p: Parameters) extends Module { val minXLen = 32 val widths = (0 to log2Ceil(operandBits / minXLen)).map(minXLen << _) val io = IO(new Bundle { val mask = Input(UInt((operandBits / 8).W)) val cmd = Input(UInt(M_SZ.W)) val lhs = Input(UInt(operandBits.W)) val rhs = Input(UInt(operandBits.W)) val out = Output(UInt(operandBits.W)) val out_unmasked = Output(UInt(operandBits.W)) }) val max = io.cmd === M_XA_MAX || io.cmd === M_XA_MAXU val min = io.cmd === M_XA_MIN || io.cmd === M_XA_MINU val add = io.cmd === M_XA_ADD val logic_and = io.cmd === M_XA_OR || io.cmd === M_XA_AND val logic_xor = io.cmd === M_XA_XOR || io.cmd === M_XA_OR val adder_out = { // partition the carry chain to support sub-xLen addition val mask = ~(0.U(operandBits.W) +: widths.init.map(w => !io.mask(w/8-1) << (w-1))).reduce(_|_) (io.lhs & mask) + (io.rhs & mask) } val less = { // break up the comparator so the lower parts will be CSE'd def isLessUnsigned(x: UInt, y: UInt, n: Int): Bool = { if (n == minXLen) x(n-1, 0) < y(n-1, 0) else x(n-1, n/2) < y(n-1, n/2) || x(n-1, n/2) === y(n-1, n/2) && isLessUnsigned(x, y, n/2) } def isLess(x: UInt, y: UInt, n: Int): Bool = { val signed = { val mask = M_XA_MIN ^ M_XA_MINU (io.cmd & mask) === (M_XA_MIN & mask) } Mux(x(n-1) === y(n-1), isLessUnsigned(x, y, n), Mux(signed, x(n-1), y(n-1))) } PriorityMux(widths.reverse.map(w => (io.mask(w/8/2), isLess(io.lhs, io.rhs, w)))) } val minmax = Mux(Mux(less, min, max), io.lhs, io.rhs) val logic = Mux(logic_and, io.lhs & io.rhs, 0.U) | Mux(logic_xor, io.lhs ^ io.rhs, 0.U) val out = Mux(add, adder_out, Mux(logic_and || logic_xor, logic, minmax)) val wmask = FillInterleaved(8, io.mask) io.out := wmask & out | ~wmask & io.lhs io.out_unmasked := out }

module LSU_1( // @[lsu.scala:201:7] input clock, // @[lsu.scala:201:7] input reset, // @[lsu.scala:201:7] input io_ptw_req_ready, // @[lsu.scala:204:14] output io_ptw_req_valid, // @[lsu.scala:204:14] output io_ptw_req_bits_valid, // @[lsu.scala:204:14] output [26:0] io_ptw_req_bits_bits_addr, // @[lsu.scala:204:14] input io_ptw_resp_valid, // @[lsu.scala:204:14] input io_ptw_resp_bits_ae_ptw, // @[lsu.scala:204:14] input io_ptw_resp_bits_ae_final, // @[lsu.scala:204:14] input io_ptw_resp_bits_pf, // @[lsu.scala:204:14] input io_ptw_resp_bits_gf, // @[lsu.scala:204:14] input io_ptw_resp_bits_hr, // @[lsu.scala:204:14] input io_ptw_resp_bits_hw, // @[lsu.scala:204:14] input io_ptw_resp_bits_hx, // @[lsu.scala:204:14] input [9:0] io_ptw_resp_bits_pte_reserved_for_future, // @[lsu.scala:204:14] input [43:0] io_ptw_resp_bits_pte_ppn, // @[lsu.scala:204:14] input [1:0] io_ptw_resp_bits_pte_reserved_for_software, // @[lsu.scala:204:14] input io_ptw_resp_bits_pte_d, // @[lsu.scala:204:14] input io_ptw_resp_bits_pte_a, // @[lsu.scala:204:14] input io_ptw_resp_bits_pte_g, // @[lsu.scala:204:14] input io_ptw_resp_bits_pte_u, // @[lsu.scala:204:14] input io_ptw_resp_bits_pte_x, // @[lsu.scala:204:14] input io_ptw_resp_bits_pte_w, // @[lsu.scala:204:14] input io_ptw_resp_bits_pte_r, // @[lsu.scala:204:14] input io_ptw_resp_bits_pte_v, // @[lsu.scala:204:14] input [1:0] io_ptw_resp_bits_level, // @[lsu.scala:204:14] input io_ptw_resp_bits_homogeneous, // @[lsu.scala:204:14] input io_ptw_resp_bits_gpa_valid, // @[lsu.scala:204:14] input [38:0] io_ptw_resp_bits_gpa_bits, // @[lsu.scala:204:14] input io_ptw_resp_bits_gpa_is_pte, // @[lsu.scala:204:14] input [3:0] io_ptw_ptbr_mode, // @[lsu.scala:204:14] input [43:0] io_ptw_ptbr_ppn, // @[lsu.scala:204:14] input io_ptw_status_debug, // @[lsu.scala:204:14] input io_ptw_status_cease, // @[lsu.scala:204:14] input io_ptw_status_wfi, // @[lsu.scala:204:14] input [1:0] io_ptw_status_dprv, // @[lsu.scala:204:14] input io_ptw_status_dv, // @[lsu.scala:204:14] input [1:0] io_ptw_status_prv, // @[lsu.scala:204:14] input io_ptw_status_v, // @[lsu.scala:204:14] input io_ptw_status_sd, // @[lsu.scala:204:14] input io_ptw_status_mpv, // @[lsu.scala:204:14] input io_ptw_status_gva, // @[lsu.scala:204:14] input io_ptw_status_tsr, // @[lsu.scala:204:14] input io_ptw_status_tw, // @[lsu.scala:204:14] input io_ptw_status_tvm, // @[lsu.scala:204:14] input io_ptw_status_mxr, // @[lsu.scala:204:14] input io_ptw_status_sum, // @[lsu.scala:204:14] input io_ptw_status_mprv, // @[lsu.scala:204:14] input [1:0] io_ptw_status_fs, // @[lsu.scala:204:14] input [1:0] io_ptw_status_mpp, // @[lsu.scala:204:14] input io_ptw_status_spp, // @[lsu.scala:204:14] input io_ptw_status_mpie, // @[lsu.scala:204:14] input io_ptw_status_spie, // @[lsu.scala:204:14] input io_ptw_status_mie, // @[lsu.scala:204:14] input io_ptw_status_sie, // @[lsu.scala:204:14] input io_ptw_pmp_0_cfg_l, // @[lsu.scala:204:14] input [1:0] io_ptw_pmp_0_cfg_a, // @[lsu.scala:204:14] input io_ptw_pmp_0_cfg_x, // @[lsu.scala:204:14] input io_ptw_pmp_0_cfg_w, // @[lsu.scala:204:14] input io_ptw_pmp_0_cfg_r, // @[lsu.scala:204:14] input [29:0] io_ptw_pmp_0_addr, // @[lsu.scala:204:14] input [31:0] io_ptw_pmp_0_mask, // @[lsu.scala:204:14] input io_ptw_pmp_1_cfg_l, // @[lsu.scala:204:14] input [1:0] io_ptw_pmp_1_cfg_a, // @[lsu.scala:204:14] input io_ptw_pmp_1_cfg_x, // @[lsu.scala:204:14] input io_ptw_pmp_1_cfg_w, // @[lsu.scala:204:14] input io_ptw_pmp_1_cfg_r, // @[lsu.scala:204:14] input [29:0] io_ptw_pmp_1_addr, // @[lsu.scala:204:14] input [31:0] io_ptw_pmp_1_mask, // @[lsu.scala:204:14] input io_ptw_pmp_2_cfg_l, // @[lsu.scala:204:14] input [1:0] io_ptw_pmp_2_cfg_a, // @[lsu.scala:204:14] input io_ptw_pmp_2_cfg_x, // @[lsu.scala:204:14] input io_ptw_pmp_2_cfg_w, // @[lsu.scala:204:14] input io_ptw_pmp_2_cfg_r, // @[lsu.scala:204:14] input [29:0] io_ptw_pmp_2_addr, // @[lsu.scala:204:14] input [31:0] io_ptw_pmp_2_mask, // @[lsu.scala:204:14] input io_ptw_pmp_3_cfg_l, // @[lsu.scala:204:14] input [1:0] io_ptw_pmp_3_cfg_a, // @[lsu.scala:204:14] input io_ptw_pmp_3_cfg_x, // @[lsu.scala:204:14] input io_ptw_pmp_3_cfg_w, // @[lsu.scala:204:14] input io_ptw_pmp_3_cfg_r, // @[lsu.scala:204:14] input [29:0] io_ptw_pmp_3_addr, // @[lsu.scala:204:14] input [31:0] io_ptw_pmp_3_mask, // @[lsu.scala:204:14] input io_ptw_pmp_4_cfg_l, // @[lsu.scala:204:14] input [1:0] io_ptw_pmp_4_cfg_a, // @[lsu.scala:204:14] input io_ptw_pmp_4_cfg_x, // @[lsu.scala:204:14] input io_ptw_pmp_4_cfg_w, // @[lsu.scala:204:14] input io_ptw_pmp_4_cfg_r, // @[lsu.scala:204:14] input [29:0] io_ptw_pmp_4_addr, // @[lsu.scala:204:14] input [31:0] io_ptw_pmp_4_mask, // @[lsu.scala:204:14] input io_ptw_pmp_5_cfg_l, // @[lsu.scala:204:14] input [1:0] io_ptw_pmp_5_cfg_a, // @[lsu.scala:204:14] input io_ptw_pmp_5_cfg_x, // @[lsu.scala:204:14] input io_ptw_pmp_5_cfg_w, // @[lsu.scala:204:14] input io_ptw_pmp_5_cfg_r, // @[lsu.scala:204:14] input [29:0] io_ptw_pmp_5_addr, // @[lsu.scala:204:14] input [31:0] io_ptw_pmp_5_mask, // @[lsu.scala:204:14] input io_ptw_pmp_6_cfg_l, // @[lsu.scala:204:14] input [1:0] io_ptw_pmp_6_cfg_a, // @[lsu.scala:204:14] input io_ptw_pmp_6_cfg_x, // @[lsu.scala:204:14] input io_ptw_pmp_6_cfg_w, // @[lsu.scala:204:14] input io_ptw_pmp_6_cfg_r, // @[lsu.scala:204:14] input [29:0] io_ptw_pmp_6_addr, // @[lsu.scala:204:14] input [31:0] io_ptw_pmp_6_mask, // @[lsu.scala:204:14] input io_ptw_pmp_7_cfg_l, // @[lsu.scala:204:14] input [1:0] io_ptw_pmp_7_cfg_a, // @[lsu.scala:204:14] input io_ptw_pmp_7_cfg_x, // @[lsu.scala:204:14] input io_ptw_pmp_7_cfg_w, // @[lsu.scala:204:14] input io_ptw_pmp_7_cfg_r, // @[lsu.scala:204:14] input [29:0] io_ptw_pmp_7_addr, // @[lsu.scala:204:14] input [31:0] io_ptw_pmp_7_mask, // @[lsu.scala:204:14] input io_core_exe_0_req_valid, // @[lsu.scala:204:14] input [6:0] io_core_exe_0_req_bits_uop_uopc, // @[lsu.scala:204:14] input [31:0] io_core_exe_0_req_bits_uop_inst, // @[lsu.scala:204:14] input [31:0] io_core_exe_0_req_bits_uop_debug_inst, // @[lsu.scala:204:14] input io_core_exe_0_req_bits_uop_is_rvc, // @[lsu.scala:204:14] input [39:0] io_core_exe_0_req_bits_uop_debug_pc, // @[lsu.scala:204:14] input [2:0] io_core_exe_0_req_bits_uop_iq_type, // @[lsu.scala:204:14] input [9:0] io_core_exe_0_req_bits_uop_fu_code, // @[lsu.scala:204:14] input [3:0] io_core_exe_0_req_bits_uop_ctrl_br_type, // @[lsu.scala:204:14] input [1:0] io_core_exe_0_req_bits_uop_ctrl_op1_sel, // @[lsu.scala:204:14] input [2:0] io_core_exe_0_req_bits_uop_ctrl_op2_sel, // @[lsu.scala:204:14] input [2:0] io_core_exe_0_req_bits_uop_ctrl_imm_sel, // @[lsu.scala:204:14] input [4:0] io_core_exe_0_req_bits_uop_ctrl_op_fcn, // @[lsu.scala:204:14] input io_core_exe_0_req_bits_uop_ctrl_fcn_dw, // @[lsu.scala:204:14] input [2:0] io_core_exe_0_req_bits_uop_ctrl_csr_cmd, // @[lsu.scala:204:14] input io_core_exe_0_req_bits_uop_ctrl_is_load, // @[lsu.scala:204:14] input io_core_exe_0_req_bits_uop_ctrl_is_sta, // @[lsu.scala:204:14] input io_core_exe_0_req_bits_uop_ctrl_is_std, // @[lsu.scala:204:14] input [1:0] io_core_exe_0_req_bits_uop_iw_state, // @[lsu.scala:204:14] input io_core_exe_0_req_bits_uop_iw_p1_poisoned, // @[lsu.scala:204:14] input io_core_exe_0_req_bits_uop_iw_p2_poisoned, // @[lsu.scala:204:14] input io_core_exe_0_req_bits_uop_is_br, // @[lsu.scala:204:14] input io_core_exe_0_req_bits_uop_is_jalr, // @[lsu.scala:204:14] input io_core_exe_0_req_bits_uop_is_jal, // @[lsu.scala:204:14] input io_core_exe_0_req_bits_uop_is_sfb, // @[lsu.scala:204:14] input [7:0] io_core_exe_0_req_bits_uop_br_mask, // @[lsu.scala:204:14] input [2:0] io_core_exe_0_req_bits_uop_br_tag, // @[lsu.scala:204:14] input [3:0] io_core_exe_0_req_bits_uop_ftq_idx, // @[lsu.scala:204:14] input io_core_exe_0_req_bits_uop_edge_inst, // @[lsu.scala:204:14] input [5:0] io_core_exe_0_req_bits_uop_pc_lob, // @[lsu.scala:204:14] input io_core_exe_0_req_bits_uop_taken, // @[lsu.scala:204:14] input [19:0] io_core_exe_0_req_bits_uop_imm_packed, // @[lsu.scala:204:14] input [11:0] io_core_exe_0_req_bits_uop_csr_addr, // @[lsu.scala:204:14] input [4:0] io_core_exe_0_req_bits_uop_rob_idx, // @[lsu.scala:204:14] input [2:0] io_core_exe_0_req_bits_uop_ldq_idx, // @[lsu.scala:204:14] input [2:0] io_core_exe_0_req_bits_uop_stq_idx, // @[lsu.scala:204:14] input [1:0] io_core_exe_0_req_bits_uop_rxq_idx, // @[lsu.scala:204:14] input [5:0] io_core_exe_0_req_bits_uop_pdst, // @[lsu.scala:204:14] input [5:0] io_core_exe_0_req_bits_uop_prs1, // @[lsu.scala:204:14] input [5:0] io_core_exe_0_req_bits_uop_prs2, // @[lsu.scala:204:14] input [5:0] io_core_exe_0_req_bits_uop_prs3, // @[lsu.scala:204:14] input [3:0] io_core_exe_0_req_bits_uop_ppred, // @[lsu.scala:204:14] input io_core_exe_0_req_bits_uop_prs1_busy, // @[lsu.scala:204:14] input io_core_exe_0_req_bits_uop_prs2_busy, // @[lsu.scala:204:14] input io_core_exe_0_req_bits_uop_prs3_busy, // @[lsu.scala:204:14] input io_core_exe_0_req_bits_uop_ppred_busy, // @[lsu.scala:204:14] input [5:0] io_core_exe_0_req_bits_uop_stale_pdst, // @[lsu.scala:204:14] input io_core_exe_0_req_bits_uop_exception, // @[lsu.scala:204:14] input [63:0] io_core_exe_0_req_bits_uop_exc_cause, // @[lsu.scala:204:14] input io_core_exe_0_req_bits_uop_bypassable, // @[lsu.scala:204:14] input [4:0] io_core_exe_0_req_bits_uop_mem_cmd, // @[lsu.scala:204:14] input [1:0] io_core_exe_0_req_bits_uop_mem_size, // @[lsu.scala:204:14] input io_core_exe_0_req_bits_uop_mem_signed, // @[lsu.scala:204:14] input io_core_exe_0_req_bits_uop_is_fence, // @[lsu.scala:204:14] input io_core_exe_0_req_bits_uop_is_fencei, // @[lsu.scala:204:14] input io_core_exe_0_req_bits_uop_is_amo, // @[lsu.scala:204:14] input io_core_exe_0_req_bits_uop_uses_ldq, // @[lsu.scala:204:14] input io_core_exe_0_req_bits_uop_uses_stq, // @[lsu.scala:204:14] input io_core_exe_0_req_bits_uop_is_sys_pc2epc, // @[lsu.scala:204:14] input io_core_exe_0_req_bits_uop_is_unique, // @[lsu.scala:204:14] input io_core_exe_0_req_bits_uop_flush_on_commit, // @[lsu.scala:204:14] input io_core_exe_0_req_bits_uop_ldst_is_rs1, // @[lsu.scala:204:14] input [5:0] io_core_exe_0_req_bits_uop_ldst, // @[lsu.scala:204:14] input [5:0] io_core_exe_0_req_bits_uop_lrs1, // @[lsu.scala:204:14] input [5:0] io_core_exe_0_req_bits_uop_lrs2, // @[lsu.scala:204:14] input [5:0] io_core_exe_0_req_bits_uop_lrs3, // @[lsu.scala:204:14] input io_core_exe_0_req_bits_uop_ldst_val, // @[lsu.scala:204:14] input [1:0] io_core_exe_0_req_bits_uop_dst_rtype, // @[lsu.scala:204:14] input [1:0] io_core_exe_0_req_bits_uop_lrs1_rtype, // @[lsu.scala:204:14] input [1:0] io_core_exe_0_req_bits_uop_lrs2_rtype, // @[lsu.scala:204:14] input io_core_exe_0_req_bits_uop_frs3_en, // @[lsu.scala:204:14] input io_core_exe_0_req_bits_uop_fp_val, // @[lsu.scala:204:14] input io_core_exe_0_req_bits_uop_fp_single, // @[lsu.scala:204:14] input io_core_exe_0_req_bits_uop_xcpt_pf_if, // @[lsu.scala:204:14] input io_core_exe_0_req_bits_uop_xcpt_ae_if, // @[lsu.scala:204:14] input io_core_exe_0_req_bits_uop_xcpt_ma_if, // @[lsu.scala:204:14] input io_core_exe_0_req_bits_uop_bp_debug_if, // @[lsu.scala:204:14] input io_core_exe_0_req_bits_uop_bp_xcpt_if, // @[lsu.scala:204:14] input [1:0] io_core_exe_0_req_bits_uop_debug_fsrc, // @[lsu.scala:204:14] input [1:0] io_core_exe_0_req_bits_uop_debug_tsrc, // @[lsu.scala:204:14] input [63:0] io_core_exe_0_req_bits_data, // @[lsu.scala:204:14] input [39:0] io_core_exe_0_req_bits_addr, // @[lsu.scala:204:14] input io_core_exe_0_req_bits_mxcpt_valid, // @[lsu.scala:204:14] input [24:0] io_core_exe_0_req_bits_mxcpt_bits, // @[lsu.scala:204:14] input io_core_exe_0_req_bits_sfence_valid, // @[lsu.scala:204:14] input io_core_exe_0_req_bits_sfence_bits_rs1, // @[lsu.scala:204:14] input io_core_exe_0_req_bits_sfence_bits_rs2, // @[lsu.scala:204:14] input [38:0] io_core_exe_0_req_bits_sfence_bits_addr, // @[lsu.scala:204:14] input io_core_exe_0_req_bits_sfence_bits_asid, // @[lsu.scala:204:14] output io_core_exe_0_iresp_valid, // @[lsu.scala:204:14] output [6:0] io_core_exe_0_iresp_bits_uop_uopc, // @[lsu.scala:204:14] output [31:0] io_core_exe_0_iresp_bits_uop_inst, // @[lsu.scala:204:14] output [31:0] io_core_exe_0_iresp_bits_uop_debug_inst, // @[lsu.scala:204:14] output io_core_exe_0_iresp_bits_uop_is_rvc, // @[lsu.scala:204:14] output [39:0] io_core_exe_0_iresp_bits_uop_debug_pc, // @[lsu.scala:204:14] output [2:0] io_core_exe_0_iresp_bits_uop_iq_type, // @[lsu.scala:204:14] output [9:0] io_core_exe_0_iresp_bits_uop_fu_code, // @[lsu.scala:204:14] output [3:0] io_core_exe_0_iresp_bits_uop_ctrl_br_type, // @[lsu.scala:204:14] output [1:0] io_core_exe_0_iresp_bits_uop_ctrl_op1_sel, // @[lsu.scala:204:14] output [2:0] io_core_exe_0_iresp_bits_uop_ctrl_op2_sel, // @[lsu.scala:204:14] output [2:0] io_core_exe_0_iresp_bits_uop_ctrl_imm_sel, // @[lsu.scala:204:14] output [4:0] io_core_exe_0_iresp_bits_uop_ctrl_op_fcn, // @[lsu.scala:204:14] output io_core_exe_0_iresp_bits_uop_ctrl_fcn_dw, // @[lsu.scala:204:14] output [2:0] io_core_exe_0_iresp_bits_uop_ctrl_csr_cmd, // @[lsu.scala:204:14] output io_core_exe_0_iresp_bits_uop_ctrl_is_load, // @[lsu.scala:204:14] output io_core_exe_0_iresp_bits_uop_ctrl_is_sta, // @[lsu.scala:204:14] output io_core_exe_0_iresp_bits_uop_ctrl_is_std, // @[lsu.scala:204:14] output [1:0] io_core_exe_0_iresp_bits_uop_iw_state, // @[lsu.scala:204:14] output io_core_exe_0_iresp_bits_uop_iw_p1_poisoned, // @[lsu.scala:204:14] output io_core_exe_0_iresp_bits_uop_iw_p2_poisoned, // @[lsu.scala:204:14] output io_core_exe_0_iresp_bits_uop_is_br, // @[lsu.scala:204:14] output io_core_exe_0_iresp_bits_uop_is_jalr, // @[lsu.scala:204:14] output io_core_exe_0_iresp_bits_uop_is_jal, // @[lsu.scala:204:14] output io_core_exe_0_iresp_bits_uop_is_sfb, // @[lsu.scala:204:14] output [7:0] io_core_exe_0_iresp_bits_uop_br_mask, // @[lsu.scala:204:14] output [2:0] io_core_exe_0_iresp_bits_uop_br_tag, // @[lsu.scala:204:14] output [3:0] io_core_exe_0_iresp_bits_uop_ftq_idx, // @[lsu.scala:204:14] output io_core_exe_0_iresp_bits_uop_edge_inst, // @[lsu.scala:204:14] output [5:0] io_core_exe_0_iresp_bits_uop_pc_lob, // @[lsu.scala:204:14] output io_core_exe_0_iresp_bits_uop_taken, // @[lsu.scala:204:14] output [19:0] io_core_exe_0_iresp_bits_uop_imm_packed, // @[lsu.scala:204:14] output [11:0] io_core_exe_0_iresp_bits_uop_csr_addr, // @[lsu.scala:204:14] output [4:0] io_core_exe_0_iresp_bits_uop_rob_idx, // @[lsu.scala:204:14] output [2:0] io_core_exe_0_iresp_bits_uop_ldq_idx, // @[lsu.scala:204:14] output [2:0] io_core_exe_0_iresp_bits_uop_stq_idx, // @[lsu.scala:204:14] output [1:0] io_core_exe_0_iresp_bits_uop_rxq_idx, // @[lsu.scala:204:14] output [5:0] io_core_exe_0_iresp_bits_uop_pdst, // @[lsu.scala:204:14] output [5:0] io_core_exe_0_iresp_bits_uop_prs1, // @[lsu.scala:204:14] output [5:0] io_core_exe_0_iresp_bits_uop_prs2, // @[lsu.scala:204:14] output [5:0] io_core_exe_0_iresp_bits_uop_prs3, // @[lsu.scala:204:14] output [3:0] io_core_exe_0_iresp_bits_uop_ppred, // @[lsu.scala:204:14] output io_core_exe_0_iresp_bits_uop_prs1_busy, // @[lsu.scala:204:14] output io_core_exe_0_iresp_bits_uop_prs2_busy, // @[lsu.scala:204:14] output io_core_exe_0_iresp_bits_uop_prs3_busy, // @[lsu.scala:204:14] output io_core_exe_0_iresp_bits_uop_ppred_busy, // @[lsu.scala:204:14] output [5:0] io_core_exe_0_iresp_bits_uop_stale_pdst, // @[lsu.scala:204:14] output io_core_exe_0_iresp_bits_uop_exception, // @[lsu.scala:204:14] output [63:0] io_core_exe_0_iresp_bits_uop_exc_cause, // @[lsu.scala:204:14] output io_core_exe_0_iresp_bits_uop_bypassable, // @[lsu.scala:204:14] output [4:0] io_core_exe_0_iresp_bits_uop_mem_cmd, // @[lsu.scala:204:14] output [1:0] io_core_exe_0_iresp_bits_uop_mem_size, // @[lsu.scala:204:14] output io_core_exe_0_iresp_bits_uop_mem_signed, // @[lsu.scala:204:14] output io_core_exe_0_iresp_bits_uop_is_fence, // @[lsu.scala:204:14] output io_core_exe_0_iresp_bits_uop_is_fencei, // @[lsu.scala:204:14] output io_core_exe_0_iresp_bits_uop_is_amo, // @[lsu.scala:204:14] output io_core_exe_0_iresp_bits_uop_uses_ldq, // @[lsu.scala:204:14] output io_core_exe_0_iresp_bits_uop_uses_stq, // @[lsu.scala:204:14] output io_core_exe_0_iresp_bits_uop_is_sys_pc2epc, // @[lsu.scala:204:14] output io_core_exe_0_iresp_bits_uop_is_unique, // @[lsu.scala:204:14] output io_core_exe_0_iresp_bits_uop_flush_on_commit, // @[lsu.scala:204:14] output io_core_exe_0_iresp_bits_uop_ldst_is_rs1, // @[lsu.scala:204:14] output [5:0] io_core_exe_0_iresp_bits_uop_ldst, // @[lsu.scala:204:14] output [5:0] io_core_exe_0_iresp_bits_uop_lrs1, // @[lsu.scala:204:14] output [5:0] io_core_exe_0_iresp_bits_uop_lrs2, // @[lsu.scala:204:14] output [5:0] io_core_exe_0_iresp_bits_uop_lrs3, // @[lsu.scala:204:14] output io_core_exe_0_iresp_bits_uop_ldst_val, // @[lsu.scala:204:14] output [1:0] io_core_exe_0_iresp_bits_uop_dst_rtype, // @[lsu.scala:204:14] output [1:0] io_core_exe_0_iresp_bits_uop_lrs1_rtype, // @[lsu.scala:204:14] output [1:0] io_core_exe_0_iresp_bits_uop_lrs2_rtype, // @[lsu.scala:204:14] output io_core_exe_0_iresp_bits_uop_frs3_en, // @[lsu.scala:204:14] output io_core_exe_0_iresp_bits_uop_fp_val, // @[lsu.scala:204:14] output io_core_exe_0_iresp_bits_uop_fp_single, // @[lsu.scala:204:14] output io_core_exe_0_iresp_bits_uop_xcpt_pf_if, // @[lsu.scala:204:14] output io_core_exe_0_iresp_bits_uop_xcpt_ae_if, // @[lsu.scala:204:14] output io_core_exe_0_iresp_bits_uop_xcpt_ma_if, // @[lsu.scala:204:14] output io_core_exe_0_iresp_bits_uop_bp_debug_if, // @[lsu.scala:204:14] output io_core_exe_0_iresp_bits_uop_bp_xcpt_if, // @[lsu.scala:204:14] output [1:0] io_core_exe_0_iresp_bits_uop_debug_fsrc, // @[lsu.scala:204:14] output [1:0] io_core_exe_0_iresp_bits_uop_debug_tsrc, // @[lsu.scala:204:14] output [63:0] io_core_exe_0_iresp_bits_data, // @[lsu.scala:204:14] output io_core_exe_0_fresp_valid, // @[lsu.scala:204:14] output [6:0] io_core_exe_0_fresp_bits_uop_uopc, // @[lsu.scala:204:14] output [31:0] io_core_exe_0_fresp_bits_uop_inst, // @[lsu.scala:204:14] output [31:0] io_core_exe_0_fresp_bits_uop_debug_inst, // @[lsu.scala:204:14] output io_core_exe_0_fresp_bits_uop_is_rvc, // @[lsu.scala:204:14] output [39:0] io_core_exe_0_fresp_bits_uop_debug_pc, // @[lsu.scala:204:14] output [2:0] io_core_exe_0_fresp_bits_uop_iq_type, // @[lsu.scala:204:14] output [9:0] io_core_exe_0_fresp_bits_uop_fu_code, // @[lsu.scala:204:14] output [3:0] io_core_exe_0_fresp_bits_uop_ctrl_br_type, // @[lsu.scala:204:14] output [1:0] io_core_exe_0_fresp_bits_uop_ctrl_op1_sel, // @[lsu.scala:204:14] output [2:0] io_core_exe_0_fresp_bits_uop_ctrl_op2_sel, // @[lsu.scala:204:14] output [2:0] io_core_exe_0_fresp_bits_uop_ctrl_imm_sel, // @[lsu.scala:204:14] output [4:0] io_core_exe_0_fresp_bits_uop_ctrl_op_fcn, // @[lsu.scala:204:14] output io_core_exe_0_fresp_bits_uop_ctrl_fcn_dw, // @[lsu.scala:204:14] output [2:0] io_core_exe_0_fresp_bits_uop_ctrl_csr_cmd, // @[lsu.scala:204:14] output io_core_exe_0_fresp_bits_uop_ctrl_is_load, // @[lsu.scala:204:14] output io_core_exe_0_fresp_bits_uop_ctrl_is_sta, // @[lsu.scala:204:14] output io_core_exe_0_fresp_bits_uop_ctrl_is_std, // @[lsu.scala:204:14] output [1:0] io_core_exe_0_fresp_bits_uop_iw_state, // @[lsu.scala:204:14] output io_core_exe_0_fresp_bits_uop_iw_p1_poisoned, // @[lsu.scala:204:14] output io_core_exe_0_fresp_bits_uop_iw_p2_poisoned, // @[lsu.scala:204:14] output io_core_exe_0_fresp_bits_uop_is_br, // @[lsu.scala:204:14] output io_core_exe_0_fresp_bits_uop_is_jalr, // @[lsu.scala:204:14] output io_core_exe_0_fresp_bits_uop_is_jal, // @[lsu.scala:204:14] output io_core_exe_0_fresp_bits_uop_is_sfb, // @[lsu.scala:204:14] output [7:0] io_core_exe_0_fresp_bits_uop_br_mask, // @[lsu.scala:204:14] output [2:0] io_core_exe_0_fresp_bits_uop_br_tag, // @[lsu.scala:204:14] output [3:0] io_core_exe_0_fresp_bits_uop_ftq_idx, // @[lsu.scala:204:14] output io_core_exe_0_fresp_bits_uop_edge_inst, // @[lsu.scala:204:14] output [5:0] io_core_exe_0_fresp_bits_uop_pc_lob, // @[lsu.scala:204:14] output io_core_exe_0_fresp_bits_uop_taken, // @[lsu.scala:204:14] output [19:0] io_core_exe_0_fresp_bits_uop_imm_packed, // @[lsu.scala:204:14] output [11:0] io_core_exe_0_fresp_bits_uop_csr_addr, // @[lsu.scala:204:14] output [4:0] io_core_exe_0_fresp_bits_uop_rob_idx, // @[lsu.scala:204:14] output [2:0] io_core_exe_0_fresp_bits_uop_ldq_idx, // @[lsu.scala:204:14] output [2:0] io_core_exe_0_fresp_bits_uop_stq_idx, // @[lsu.scala:204:14] output [1:0] io_core_exe_0_fresp_bits_uop_rxq_idx, // @[lsu.scala:204:14] output [5:0] io_core_exe_0_fresp_bits_uop_pdst, // @[lsu.scala:204:14] output [5:0] io_core_exe_0_fresp_bits_uop_prs1, // @[lsu.scala:204:14] output [5:0] io_core_exe_0_fresp_bits_uop_prs2, // @[lsu.scala:204:14] output [5:0] io_core_exe_0_fresp_bits_uop_prs3, // @[lsu.scala:204:14] output [3:0] io_core_exe_0_fresp_bits_uop_ppred, // @[lsu.scala:204:14] output io_core_exe_0_fresp_bits_uop_prs1_busy, // @[lsu.scala:204:14] output io_core_exe_0_fresp_bits_uop_prs2_busy, // @[lsu.scala:204:14] output io_core_exe_0_fresp_bits_uop_prs3_busy, // @[lsu.scala:204:14] output io_core_exe_0_fresp_bits_uop_ppred_busy, // @[lsu.scala:204:14] output [5:0] io_core_exe_0_fresp_bits_uop_stale_pdst, // @[lsu.scala:204:14] output io_core_exe_0_fresp_bits_uop_exception, // @[lsu.scala:204:14] output [63:0] io_core_exe_0_fresp_bits_uop_exc_cause, // @[lsu.scala:204:14] output io_core_exe_0_fresp_bits_uop_bypassable, // @[lsu.scala:204:14] output [4:0] io_core_exe_0_fresp_bits_uop_mem_cmd, // @[lsu.scala:204:14] output [1:0] io_core_exe_0_fresp_bits_uop_mem_size, // @[lsu.scala:204:14] output io_core_exe_0_fresp_bits_uop_mem_signed, // @[lsu.scala:204:14] output io_core_exe_0_fresp_bits_uop_is_fence, // @[lsu.scala:204:14] output io_core_exe_0_fresp_bits_uop_is_fencei, // @[lsu.scala:204:14] output io_core_exe_0_fresp_bits_uop_is_amo, // @[lsu.scala:204:14] output io_core_exe_0_fresp_bits_uop_uses_ldq, // @[lsu.scala:204:14] output io_core_exe_0_fresp_bits_uop_uses_stq, // @[lsu.scala:204:14] output io_core_exe_0_fresp_bits_uop_is_sys_pc2epc, // @[lsu.scala:204:14] output io_core_exe_0_fresp_bits_uop_is_unique, // @[lsu.scala:204:14] output io_core_exe_0_fresp_bits_uop_flush_on_commit, // @[lsu.scala:204:14] output io_core_exe_0_fresp_bits_uop_ldst_is_rs1, // @[lsu.scala:204:14] output [5:0] io_core_exe_0_fresp_bits_uop_ldst, // @[lsu.scala:204:14] output [5:0] io_core_exe_0_fresp_bits_uop_lrs1, // @[lsu.scala:204:14] output [5:0] io_core_exe_0_fresp_bits_uop_lrs2, // @[lsu.scala:204:14] output [5:0] io_core_exe_0_fresp_bits_uop_lrs3, // @[lsu.scala:204:14] output io_core_exe_0_fresp_bits_uop_ldst_val, // @[lsu.scala:204:14] output [1:0] io_core_exe_0_fresp_bits_uop_dst_rtype, // @[lsu.scala:204:14] output [1:0] io_core_exe_0_fresp_bits_uop_lrs1_rtype, // @[lsu.scala:204:14] output [1:0] io_core_exe_0_fresp_bits_uop_lrs2_rtype, // @[lsu.scala:204:14] output io_core_exe_0_fresp_bits_uop_frs3_en, // @[lsu.scala:204:14] output io_core_exe_0_fresp_bits_uop_fp_val, // @[lsu.scala:204:14] output io_core_exe_0_fresp_bits_uop_fp_single, // @[lsu.scala:204:14] output io_core_exe_0_fresp_bits_uop_xcpt_pf_if, // @[lsu.scala:204:14] output io_core_exe_0_fresp_bits_uop_xcpt_ae_if, // @[lsu.scala:204:14] output io_core_exe_0_fresp_bits_uop_xcpt_ma_if, // @[lsu.scala:204:14] output io_core_exe_0_fresp_bits_uop_bp_debug_if, // @[lsu.scala:204:14] output io_core_exe_0_fresp_bits_uop_bp_xcpt_if, // @[lsu.scala:204:14] output [1:0] io_core_exe_0_fresp_bits_uop_debug_fsrc, // @[lsu.scala:204:14] output [1:0] io_core_exe_0_fresp_bits_uop_debug_tsrc, // @[lsu.scala:204:14] output [64:0] io_core_exe_0_fresp_bits_data, // @[lsu.scala:204:14] input io_core_dis_uops_0_valid, // @[lsu.scala:204:14] input [6:0] io_core_dis_uops_0_bits_uopc, // @[lsu.scala:204:14] input [31:0] io_core_dis_uops_0_bits_inst, // @[lsu.scala:204:14] input [31:0] io_core_dis_uops_0_bits_debug_inst, // @[lsu.scala:204:14] input io_core_dis_uops_0_bits_is_rvc, // @[lsu.scala:204:14] input [39:0] io_core_dis_uops_0_bits_debug_pc, // @[lsu.scala:204:14] input [2:0] io_core_dis_uops_0_bits_iq_type, // @[lsu.scala:204:14] input [9:0] io_core_dis_uops_0_bits_fu_code, // @[lsu.scala:204:14] input [3:0] io_core_dis_uops_0_bits_ctrl_br_type, // @[lsu.scala:204:14] input [1:0] io_core_dis_uops_0_bits_ctrl_op1_sel, // @[lsu.scala:204:14] input [2:0] io_core_dis_uops_0_bits_ctrl_op2_sel, // @[lsu.scala:204:14] input [2:0] io_core_dis_uops_0_bits_ctrl_imm_sel, // @[lsu.scala:204:14] input [4:0] io_core_dis_uops_0_bits_ctrl_op_fcn, // @[lsu.scala:204:14] input io_core_dis_uops_0_bits_ctrl_fcn_dw, // @[lsu.scala:204:14] input [2:0] io_core_dis_uops_0_bits_ctrl_csr_cmd, // @[lsu.scala:204:14] input io_core_dis_uops_0_bits_ctrl_is_load, // @[lsu.scala:204:14] input io_core_dis_uops_0_bits_ctrl_is_sta, // @[lsu.scala:204:14] input io_core_dis_uops_0_bits_ctrl_is_std, // @[lsu.scala:204:14] input [1:0] io_core_dis_uops_0_bits_iw_state, // @[lsu.scala:204:14] input io_core_dis_uops_0_bits_iw_p1_poisoned, // @[lsu.scala:204:14] input io_core_dis_uops_0_bits_iw_p2_poisoned, // @[lsu.scala:204:14] input io_core_dis_uops_0_bits_is_br, // @[lsu.scala:204:14] input io_core_dis_uops_0_bits_is_jalr, // @[lsu.scala:204:14] input io_core_dis_uops_0_bits_is_jal, // @[lsu.scala:204:14] input io_core_dis_uops_0_bits_is_sfb, // @[lsu.scala:204:14] input [7:0] io_core_dis_uops_0_bits_br_mask, // @[lsu.scala:204:14] input [2:0] io_core_dis_uops_0_bits_br_tag, // @[lsu.scala:204:14] input [3:0] io_core_dis_uops_0_bits_ftq_idx, // @[lsu.scala:204:14] input io_core_dis_uops_0_bits_edge_inst, // @[lsu.scala:204:14] input [5:0] io_core_dis_uops_0_bits_pc_lob, // @[lsu.scala:204:14] input io_core_dis_uops_0_bits_taken, // @[lsu.scala:204:14] input [19:0] io_core_dis_uops_0_bits_imm_packed, // @[lsu.scala:204:14] input [11:0] io_core_dis_uops_0_bits_csr_addr, // @[lsu.scala:204:14] input [4:0] io_core_dis_uops_0_bits_rob_idx, // @[lsu.scala:204:14] input [2:0] io_core_dis_uops_0_bits_ldq_idx, // @[lsu.scala:204:14] input [2:0] io_core_dis_uops_0_bits_stq_idx, // @[lsu.scala:204:14] input [1:0] io_core_dis_uops_0_bits_rxq_idx, // @[lsu.scala:204:14] input [5:0] io_core_dis_uops_0_bits_pdst, // @[lsu.scala:204:14] input [5:0] io_core_dis_uops_0_bits_prs1, // @[lsu.scala:204:14] input [5:0] io_core_dis_uops_0_bits_prs2, // @[lsu.scala:204:14] input [5:0] io_core_dis_uops_0_bits_prs3, // @[lsu.scala:204:14] input io_core_dis_uops_0_bits_prs1_busy, // @[lsu.scala:204:14] input io_core_dis_uops_0_bits_prs2_busy, // @[lsu.scala:204:14] input io_core_dis_uops_0_bits_prs3_busy, // @[lsu.scala:204:14] input [5:0] io_core_dis_uops_0_bits_stale_pdst, // @[lsu.scala:204:14] input io_core_dis_uops_0_bits_exception, // @[lsu.scala:204:14] input [63:0] io_core_dis_uops_0_bits_exc_cause, // @[lsu.scala:204:14] input io_core_dis_uops_0_bits_bypassable, // @[lsu.scala:204:14] input [4:0] io_core_dis_uops_0_bits_mem_cmd, // @[lsu.scala:204:14] input [1:0] io_core_dis_uops_0_bits_mem_size, // @[lsu.scala:204:14] input io_core_dis_uops_0_bits_mem_signed, // @[lsu.scala:204:14] input io_core_dis_uops_0_bits_is_fence, // @[lsu.scala:204:14] input io_core_dis_uops_0_bits_is_fencei, // @[lsu.scala:204:14] input io_core_dis_uops_0_bits_is_amo, // @[lsu.scala:204:14] input io_core_dis_uops_0_bits_uses_ldq, // @[lsu.scala:204:14] input io_core_dis_uops_0_bits_uses_stq, // @[lsu.scala:204:14] input io_core_dis_uops_0_bits_is_sys_pc2epc, // @[lsu.scala:204:14] input io_core_dis_uops_0_bits_is_unique, // @[lsu.scala:204:14] input io_core_dis_uops_0_bits_flush_on_commit, // @[lsu.scala:204:14] input io_core_dis_uops_0_bits_ldst_is_rs1, // @[lsu.scala:204:14] input [5:0] io_core_dis_uops_0_bits_ldst, // @[lsu.scala:204:14] input [5:0] io_core_dis_uops_0_bits_lrs1, // @[lsu.scala:204:14] input [5:0] io_core_dis_uops_0_bits_lrs2, // @[lsu.scala:204:14] input [5:0] io_core_dis_uops_0_bits_lrs3, // @[lsu.scala:204:14] input io_core_dis_uops_0_bits_ldst_val, // @[lsu.scala:204:14] input [1:0] io_core_dis_uops_0_bits_dst_rtype, // @[lsu.scala:204:14] input [1:0] io_core_dis_uops_0_bits_lrs1_rtype, // @[lsu.scala:204:14] input [1:0] io_core_dis_uops_0_bits_lrs2_rtype, // @[lsu.scala:204:14] input io_core_dis_uops_0_bits_frs3_en, // @[lsu.scala:204:14] input io_core_dis_uops_0_bits_fp_val, // @[lsu.scala:204:14] input io_core_dis_uops_0_bits_fp_single, // @[lsu.scala:204:14] input io_core_dis_uops_0_bits_xcpt_pf_if, // @[lsu.scala:204:14] input io_core_dis_uops_0_bits_xcpt_ae_if, // @[lsu.scala:204:14] input io_core_dis_uops_0_bits_xcpt_ma_if, // @[lsu.scala:204:14] input io_core_dis_uops_0_bits_bp_debug_if, // @[lsu.scala:204:14] input io_core_dis_uops_0_bits_bp_xcpt_if, // @[lsu.scala:204:14] input [1:0] io_core_dis_uops_0_bits_debug_fsrc, // @[lsu.scala:204:14] input [1:0] io_core_dis_uops_0_bits_debug_tsrc, // @[lsu.scala:204:14] output [2:0] io_core_dis_ldq_idx_0, // @[lsu.scala:204:14] output [2:0] io_core_dis_stq_idx_0, // @[lsu.scala:204:14] output io_core_ldq_full_0, // @[lsu.scala:204:14] output io_core_stq_full_0, // @[lsu.scala:204:14] output io_core_fp_stdata_ready, // @[lsu.scala:204:14] input io_core_fp_stdata_valid, // @[lsu.scala:204:14] input [6:0] io_core_fp_stdata_bits_uop_uopc, // @[lsu.scala:204:14] input [31:0] io_core_fp_stdata_bits_uop_inst, // @[lsu.scala:204:14] input [31:0] io_core_fp_stdata_bits_uop_debug_inst, // @[lsu.scala:204:14] input io_core_fp_stdata_bits_uop_is_rvc, // @[lsu.scala:204:14] input [39:0] io_core_fp_stdata_bits_uop_debug_pc, // @[lsu.scala:204:14] input [2:0] io_core_fp_stdata_bits_uop_iq_type, // @[lsu.scala:204:14] input [9:0] io_core_fp_stdata_bits_uop_fu_code, // @[lsu.scala:204:14] input [3:0] io_core_fp_stdata_bits_uop_ctrl_br_type, // @[lsu.scala:204:14] input [1:0] io_core_fp_stdata_bits_uop_ctrl_op1_sel, // @[lsu.scala:204:14] input [2:0] io_core_fp_stdata_bits_uop_ctrl_op2_sel, // @[lsu.scala:204:14] input [2:0] io_core_fp_stdata_bits_uop_ctrl_imm_sel, // @[lsu.scala:204:14] input [4:0] io_core_fp_stdata_bits_uop_ctrl_op_fcn, // @[lsu.scala:204:14] input io_core_fp_stdata_bits_uop_ctrl_fcn_dw, // @[lsu.scala:204:14] input [2:0] io_core_fp_stdata_bits_uop_ctrl_csr_cmd, // @[lsu.scala:204:14] input io_core_fp_stdata_bits_uop_ctrl_is_load, // @[lsu.scala:204:14] input io_core_fp_stdata_bits_uop_ctrl_is_sta, // @[lsu.scala:204:14] input io_core_fp_stdata_bits_uop_ctrl_is_std, // @[lsu.scala:204:14] input [1:0] io_core_fp_stdata_bits_uop_iw_state, // @[lsu.scala:204:14] input io_core_fp_stdata_bits_uop_iw_p1_poisoned, // @[lsu.scala:204:14] input io_core_fp_stdata_bits_uop_iw_p2_poisoned, // @[lsu.scala:204:14] input io_core_fp_stdata_bits_uop_is_br, // @[lsu.scala:204:14] input io_core_fp_stdata_bits_uop_is_jalr, // @[lsu.scala:204:14] input io_core_fp_stdata_bits_uop_is_jal, // @[lsu.scala:204:14] input io_core_fp_stdata_bits_uop_is_sfb, // @[lsu.scala:204:14] input [7:0] io_core_fp_stdata_bits_uop_br_mask, // @[lsu.scala:204:14] input [2:0] io_core_fp_stdata_bits_uop_br_tag, // @[lsu.scala:204:14] input [3:0] io_core_fp_stdata_bits_uop_ftq_idx, // @[lsu.scala:204:14] input io_core_fp_stdata_bits_uop_edge_inst, // @[lsu.scala:204:14] input [5:0] io_core_fp_stdata_bits_uop_pc_lob, // @[lsu.scala:204:14] input io_core_fp_stdata_bits_uop_taken, // @[lsu.scala:204:14] input [19:0] io_core_fp_stdata_bits_uop_imm_packed, // @[lsu.scala:204:14] input [11:0] io_core_fp_stdata_bits_uop_csr_addr, // @[lsu.scala:204:14] input [4:0] io_core_fp_stdata_bits_uop_rob_idx, // @[lsu.scala:204:14] input [2:0] io_core_fp_stdata_bits_uop_ldq_idx, // @[lsu.scala:204:14] input [2:0] io_core_fp_stdata_bits_uop_stq_idx, // @[lsu.scala:204:14] input [1:0] io_core_fp_stdata_bits_uop_rxq_idx, // @[lsu.scala:204:14] input [5:0] io_core_fp_stdata_bits_uop_pdst, // @[lsu.scala:204:14] input [5:0] io_core_fp_stdata_bits_uop_prs1, // @[lsu.scala:204:14] input [5:0] io_core_fp_stdata_bits_uop_prs2, // @[lsu.scala:204:14] input [5:0] io_core_fp_stdata_bits_uop_prs3, // @[lsu.scala:204:14] input [3:0] io_core_fp_stdata_bits_uop_ppred, // @[lsu.scala:204:14] input io_core_fp_stdata_bits_uop_prs1_busy, // @[lsu.scala:204:14] input io_core_fp_stdata_bits_uop_prs2_busy, // @[lsu.scala:204:14] input io_core_fp_stdata_bits_uop_prs3_busy, // @[lsu.scala:204:14] input io_core_fp_stdata_bits_uop_ppred_busy, // @[lsu.scala:204:14] input [5:0] io_core_fp_stdata_bits_uop_stale_pdst, // @[lsu.scala:204:14] input io_core_fp_stdata_bits_uop_exception, // @[lsu.scala:204:14] input [63:0] io_core_fp_stdata_bits_uop_exc_cause, // @[lsu.scala:204:14] input io_core_fp_stdata_bits_uop_bypassable, // @[lsu.scala:204:14] input [4:0] io_core_fp_stdata_bits_uop_mem_cmd, // @[lsu.scala:204:14] input [1:0] io_core_fp_stdata_bits_uop_mem_size, // @[lsu.scala:204:14] input io_core_fp_stdata_bits_uop_mem_signed, // @[lsu.scala:204:14] input io_core_fp_stdata_bits_uop_is_fence, // @[lsu.scala:204:14] input io_core_fp_stdata_bits_uop_is_fencei, // @[lsu.scala:204:14] input io_core_fp_stdata_bits_uop_is_amo, // @[lsu.scala:204:14] input io_core_fp_stdata_bits_uop_uses_ldq, // @[lsu.scala:204:14] input io_core_fp_stdata_bits_uop_uses_stq, // @[lsu.scala:204:14] input io_core_fp_stdata_bits_uop_is_sys_pc2epc, // @[lsu.scala:204:14] input io_core_fp_stdata_bits_uop_is_unique, // @[lsu.scala:204:14] input io_core_fp_stdata_bits_uop_flush_on_commit, // @[lsu.scala:204:14] input io_core_fp_stdata_bits_uop_ldst_is_rs1, // @[lsu.scala:204:14] input [5:0] io_core_fp_stdata_bits_uop_ldst, // @[lsu.scala:204:14] input [5:0] io_core_fp_stdata_bits_uop_lrs1, // @[lsu.scala:204:14] input [5:0] io_core_fp_stdata_bits_uop_lrs2, // @[lsu.scala:204:14] input [5:0] io_core_fp_stdata_bits_uop_lrs3, // @[lsu.scala:204:14] input io_core_fp_stdata_bits_uop_ldst_val, // @[lsu.scala:204:14] input [1:0] io_core_fp_stdata_bits_uop_dst_rtype, // @[lsu.scala:204:14] input [1:0] io_core_fp_stdata_bits_uop_lrs1_rtype, // @[lsu.scala:204:14] input [1:0] io_core_fp_stdata_bits_uop_lrs2_rtype, // @[lsu.scala:204:14] input io_core_fp_stdata_bits_uop_frs3_en, // @[lsu.scala:204:14] input io_core_fp_stdata_bits_uop_fp_val, // @[lsu.scala:204:14] input io_core_fp_stdata_bits_uop_fp_single, // @[lsu.scala:204:14] input io_core_fp_stdata_bits_uop_xcpt_pf_if, // @[lsu.scala:204:14] input io_core_fp_stdata_bits_uop_xcpt_ae_if, // @[lsu.scala:204:14] input io_core_fp_stdata_bits_uop_xcpt_ma_if, // @[lsu.scala:204:14] input io_core_fp_stdata_bits_uop_bp_debug_if, // @[lsu.scala:204:14] input io_core_fp_stdata_bits_uop_bp_xcpt_if, // @[lsu.scala:204:14] input [1:0] io_core_fp_stdata_bits_uop_debug_fsrc, // @[lsu.scala:204:14] input [1:0] io_core_fp_stdata_bits_uop_debug_tsrc, // @[lsu.scala:204:14] input [63:0] io_core_fp_stdata_bits_data, // @[lsu.scala:204:14] input io_core_fp_stdata_bits_predicated, // @[lsu.scala:204:14] input io_core_fp_stdata_bits_fflags_valid, // @[lsu.scala:204:14] input [6:0] io_core_fp_stdata_bits_fflags_bits_uop_uopc, // @[lsu.scala:204:14] input [31:0] io_core_fp_stdata_bits_fflags_bits_uop_inst, // @[lsu.scala:204:14] input [31:0] io_core_fp_stdata_bits_fflags_bits_uop_debug_inst, // @[lsu.scala:204:14] input io_core_fp_stdata_bits_fflags_bits_uop_is_rvc, // @[lsu.scala:204:14] input [39:0] io_core_fp_stdata_bits_fflags_bits_uop_debug_pc, // @[lsu.scala:204:14] input [2:0] io_core_fp_stdata_bits_fflags_bits_uop_iq_type, // @[lsu.scala:204:14] input [9:0] io_core_fp_stdata_bits_fflags_bits_uop_fu_code, // @[lsu.scala:204:14] input [3:0] io_core_fp_stdata_bits_fflags_bits_uop_ctrl_br_type, // @[lsu.scala:204:14] input [1:0] io_core_fp_stdata_bits_fflags_bits_uop_ctrl_op1_sel, // @[lsu.scala:204:14] input [2:0] io_core_fp_stdata_bits_fflags_bits_uop_ctrl_op2_sel, // @[lsu.scala:204:14] input [2:0] io_core_fp_stdata_bits_fflags_bits_uop_ctrl_imm_sel, // @[lsu.scala:204:14] input [4:0] io_core_fp_stdata_bits_fflags_bits_uop_ctrl_op_fcn, // @[lsu.scala:204:14] input io_core_fp_stdata_bits_fflags_bits_uop_ctrl_fcn_dw, // @[lsu.scala:204:14] input [2:0] io_core_fp_stdata_bits_fflags_bits_uop_ctrl_csr_cmd, // @[lsu.scala:204:14] input io_core_fp_stdata_bits_fflags_bits_uop_ctrl_is_load, // @[lsu.scala:204:14] input io_core_fp_stdata_bits_fflags_bits_uop_ctrl_is_sta, // @[lsu.scala:204:14] input io_core_fp_stdata_bits_fflags_bits_uop_ctrl_is_std, // @[lsu.scala:204:14] input [1:0] io_core_fp_stdata_bits_fflags_bits_uop_iw_state, // @[lsu.scala:204:14] input io_core_fp_stdata_bits_fflags_bits_uop_iw_p1_poisoned, // @[lsu.scala:204:14] input io_core_fp_stdata_bits_fflags_bits_uop_iw_p2_poisoned, // @[lsu.scala:204:14] input io_core_fp_stdata_bits_fflags_bits_uop_is_br, // @[lsu.scala:204:14] input io_core_fp_stdata_bits_fflags_bits_uop_is_jalr, // @[lsu.scala:204:14] input io_core_fp_stdata_bits_fflags_bits_uop_is_jal, // @[lsu.scala:204:14] input io_core_fp_stdata_bits_fflags_bits_uop_is_sfb, // @[lsu.scala:204:14] input [7:0] io_core_fp_stdata_bits_fflags_bits_uop_br_mask, // @[lsu.scala:204:14] input [2:0] io_core_fp_stdata_bits_fflags_bits_uop_br_tag, // @[lsu.scala:204:14] input [3:0] io_core_fp_stdata_bits_fflags_bits_uop_ftq_idx, // @[lsu.scala:204:14] input io_core_fp_stdata_bits_fflags_bits_uop_edge_inst, // @[lsu.scala:204:14] input [5:0] io_core_fp_stdata_bits_fflags_bits_uop_pc_lob, // @[lsu.scala:204:14] input io_core_fp_stdata_bits_fflags_bits_uop_taken, // @[lsu.scala:204:14] input [19:0] io_core_fp_stdata_bits_fflags_bits_uop_imm_packed, // @[lsu.scala:204:14] input [11:0] io_core_fp_stdata_bits_fflags_bits_uop_csr_addr, // @[lsu.scala:204:14] input [4:0] io_core_fp_stdata_bits_fflags_bits_uop_rob_idx, // @[lsu.scala:204:14] input [2:0] io_core_fp_stdata_bits_fflags_bits_uop_ldq_idx, // @[lsu.scala:204:14] input [2:0] io_core_fp_stdata_bits_fflags_bits_uop_stq_idx, // @[lsu.scala:204:14] input [1:0] io_core_fp_stdata_bits_fflags_bits_uop_rxq_idx, // @[lsu.scala:204:14] input [5:0] io_core_fp_stdata_bits_fflags_bits_uop_pdst, // @[lsu.scala:204:14] input [5:0] io_core_fp_stdata_bits_fflags_bits_uop_prs1, // @[lsu.scala:204:14] input [5:0] io_core_fp_stdata_bits_fflags_bits_uop_prs2, // @[lsu.scala:204:14] input [5:0] io_core_fp_stdata_bits_fflags_bits_uop_prs3, // @[lsu.scala:204:14] input [3:0] io_core_fp_stdata_bits_fflags_bits_uop_ppred, // @[lsu.scala:204:14] input io_core_fp_stdata_bits_fflags_bits_uop_prs1_busy, // @[lsu.scala:204:14] input io_core_fp_stdata_bits_fflags_bits_uop_prs2_busy, // @[lsu.scala:204:14] input io_core_fp_stdata_bits_fflags_bits_uop_prs3_busy, // @[lsu.scala:204:14] input io_core_fp_stdata_bits_fflags_bits_uop_ppred_busy, // @[lsu.scala:204:14] input [5:0] io_core_fp_stdata_bits_fflags_bits_uop_stale_pdst, // @[lsu.scala:204:14] input io_core_fp_stdata_bits_fflags_bits_uop_exception, // @[lsu.scala:204:14] input [63:0] io_core_fp_stdata_bits_fflags_bits_uop_exc_cause, // @[lsu.scala:204:14] input io_core_fp_stdata_bits_fflags_bits_uop_bypassable, // @[lsu.scala:204:14] input [4:0] io_core_fp_stdata_bits_fflags_bits_uop_mem_cmd, // @[lsu.scala:204:14] input [1:0] io_core_fp_stdata_bits_fflags_bits_uop_mem_size, // @[lsu.scala:204:14] input io_core_fp_stdata_bits_fflags_bits_uop_mem_signed, // @[lsu.scala:204:14] input io_core_fp_stdata_bits_fflags_bits_uop_is_fence, // @[lsu.scala:204:14] input io_core_fp_stdata_bits_fflags_bits_uop_is_fencei, // @[lsu.scala:204:14] input io_core_fp_stdata_bits_fflags_bits_uop_is_amo, // @[lsu.scala:204:14] input io_core_fp_stdata_bits_fflags_bits_uop_uses_ldq, // @[lsu.scala:204:14] input io_core_fp_stdata_bits_fflags_bits_uop_uses_stq, // @[lsu.scala:204:14] input io_core_fp_stdata_bits_fflags_bits_uop_is_sys_pc2epc, // @[lsu.scala:204:14] input io_core_fp_stdata_bits_fflags_bits_uop_is_unique, // @[lsu.scala:204:14] input io_core_fp_stdata_bits_fflags_bits_uop_flush_on_commit, // @[lsu.scala:204:14] input io_core_fp_stdata_bits_fflags_bits_uop_ldst_is_rs1, // @[lsu.scala:204:14] input [5:0] io_core_fp_stdata_bits_fflags_bits_uop_ldst, // @[lsu.scala:204:14] input [5:0] io_core_fp_stdata_bits_fflags_bits_uop_lrs1, // @[lsu.scala:204:14] input [5:0] io_core_fp_stdata_bits_fflags_bits_uop_lrs2, // @[lsu.scala:204:14] input [5:0] io_core_fp_stdata_bits_fflags_bits_uop_lrs3, // @[lsu.scala:204:14] input io_core_fp_stdata_bits_fflags_bits_uop_ldst_val, // @[lsu.scala:204:14] input [1:0] io_core_fp_stdata_bits_fflags_bits_uop_dst_rtype, // @[lsu.scala:204:14] input [1:0] io_core_fp_stdata_bits_fflags_bits_uop_lrs1_rtype, // @[lsu.scala:204:14] input [1:0] io_core_fp_stdata_bits_fflags_bits_uop_lrs2_rtype, // @[lsu.scala:204:14] input io_core_fp_stdata_bits_fflags_bits_uop_frs3_en, // @[lsu.scala:204:14] input io_core_fp_stdata_bits_fflags_bits_uop_fp_val, // @[lsu.scala:204:14] input io_core_fp_stdata_bits_fflags_bits_uop_fp_single, // @[lsu.scala:204:14] input io_core_fp_stdata_bits_fflags_bits_uop_xcpt_pf_if, // @[lsu.scala:204:14] input io_core_fp_stdata_bits_fflags_bits_uop_xcpt_ae_if, // @[lsu.scala:204:14] input io_core_fp_stdata_bits_fflags_bits_uop_xcpt_ma_if, // @[lsu.scala:204:14] input io_core_fp_stdata_bits_fflags_bits_uop_bp_debug_if, // @[lsu.scala:204:14] input io_core_fp_stdata_bits_fflags_bits_uop_bp_xcpt_if, // @[lsu.scala:204:14] input [1:0] io_core_fp_stdata_bits_fflags_bits_uop_debug_fsrc, // @[lsu.scala:204:14] input [1:0] io_core_fp_stdata_bits_fflags_bits_uop_debug_tsrc, // @[lsu.scala:204:14] input [4:0] io_core_fp_stdata_bits_fflags_bits_flags, // @[lsu.scala:204:14] input io_core_commit_valids_0, // @[lsu.scala:204:14] input io_core_commit_arch_valids_0, // @[lsu.scala:204:14] input [6:0] io_core_commit_uops_0_uopc, // @[lsu.scala:204:14] input [31:0] io_core_commit_uops_0_inst, // @[lsu.scala:204:14] input [31:0] io_core_commit_uops_0_debug_inst, // @[lsu.scala:204:14] input io_core_commit_uops_0_is_rvc, // @[lsu.scala:204:14] input [39:0] io_core_commit_uops_0_debug_pc, // @[lsu.scala:204:14] input [2:0] io_core_commit_uops_0_iq_type, // @[lsu.scala:204:14] input [9:0] io_core_commit_uops_0_fu_code, // @[lsu.scala:204:14] input [3:0] io_core_commit_uops_0_ctrl_br_type, // @[lsu.scala:204:14] input [1:0] io_core_commit_uops_0_ctrl_op1_sel, // @[lsu.scala:204:14] input [2:0] io_core_commit_uops_0_ctrl_op2_sel, // @[lsu.scala:204:14] input [2:0] io_core_commit_uops_0_ctrl_imm_sel, // @[lsu.scala:204:14] input [4:0] io_core_commit_uops_0_ctrl_op_fcn, // @[lsu.scala:204:14] input io_core_commit_uops_0_ctrl_fcn_dw, // @[lsu.scala:204:14] input [2:0] io_core_commit_uops_0_ctrl_csr_cmd, // @[lsu.scala:204:14] input io_core_commit_uops_0_ctrl_is_load, // @[lsu.scala:204:14] input io_core_commit_uops_0_ctrl_is_sta, // @[lsu.scala:204:14] input io_core_commit_uops_0_ctrl_is_std, // @[lsu.scala:204:14] input [1:0] io_core_commit_uops_0_iw_state, // @[lsu.scala:204:14] input io_core_commit_uops_0_iw_p1_poisoned, // @[lsu.scala:204:14] input io_core_commit_uops_0_iw_p2_poisoned, // @[lsu.scala:204:14] input io_core_commit_uops_0_is_br, // @[lsu.scala:204:14] input io_core_commit_uops_0_is_jalr, // @[lsu.scala:204:14] input io_core_commit_uops_0_is_jal, // @[lsu.scala:204:14] input io_core_commit_uops_0_is_sfb, // @[lsu.scala:204:14] input [7:0] io_core_commit_uops_0_br_mask, // @[lsu.scala:204:14] input [2:0] io_core_commit_uops_0_br_tag, // @[lsu.scala:204:14] input [3:0] io_core_commit_uops_0_ftq_idx, // @[lsu.scala:204:14] input io_core_commit_uops_0_edge_inst, // @[lsu.scala:204:14] input [5:0] io_core_commit_uops_0_pc_lob, // @[lsu.scala:204:14] input io_core_commit_uops_0_taken, // @[lsu.scala:204:14] input [19:0] io_core_commit_uops_0_imm_packed, // @[lsu.scala:204:14] input [11:0] io_core_commit_uops_0_csr_addr, // @[lsu.scala:204:14] input [4:0] io_core_commit_uops_0_rob_idx, // @[lsu.scala:204:14] input [2:0] io_core_commit_uops_0_ldq_idx, // @[lsu.scala:204:14] input [2:0] io_core_commit_uops_0_stq_idx, // @[lsu.scala:204:14] input [1:0] io_core_commit_uops_0_rxq_idx, // @[lsu.scala:204:14] input [5:0] io_core_commit_uops_0_pdst, // @[lsu.scala:204:14] input [5:0] io_core_commit_uops_0_prs1, // @[lsu.scala:204:14] input [5:0] io_core_commit_uops_0_prs2, // @[lsu.scala:204:14] input [5:0] io_core_commit_uops_0_prs3, // @[lsu.scala:204:14] input [3:0] io_core_commit_uops_0_ppred, // @[lsu.scala:204:14] input io_core_commit_uops_0_prs1_busy, // @[lsu.scala:204:14] input io_core_commit_uops_0_prs2_busy, // @[lsu.scala:204:14] input io_core_commit_uops_0_prs3_busy, // @[lsu.scala:204:14] input io_core_commit_uops_0_ppred_busy, // @[lsu.scala:204:14] input [5:0] io_core_commit_uops_0_stale_pdst, // @[lsu.scala:204:14] input io_core_commit_uops_0_exception, // @[lsu.scala:204:14] input [63:0] io_core_commit_uops_0_exc_cause, // @[lsu.scala:204:14] input io_core_commit_uops_0_bypassable, // @[lsu.scala:204:14] input [4:0] io_core_commit_uops_0_mem_cmd, // @[lsu.scala:204:14] input [1:0] io_core_commit_uops_0_mem_size, // @[lsu.scala:204:14] input io_core_commit_uops_0_mem_signed, // @[lsu.scala:204:14] input io_core_commit_uops_0_is_fence, // @[lsu.scala:204:14] input io_core_commit_uops_0_is_fencei, // @[lsu.scala:204:14] input io_core_commit_uops_0_is_amo, // @[lsu.scala:204:14] input io_core_commit_uops_0_uses_ldq, // @[lsu.scala:204:14] input io_core_commit_uops_0_uses_stq, // @[lsu.scala:204:14] input io_core_commit_uops_0_is_sys_pc2epc, // @[lsu.scala:204:14] input io_core_commit_uops_0_is_unique, // @[lsu.scala:204:14] input io_core_commit_uops_0_flush_on_commit, // @[lsu.scala:204:14] input io_core_commit_uops_0_ldst_is_rs1, // @[lsu.scala:204:14] input [5:0] io_core_commit_uops_0_ldst, // @[lsu.scala:204:14] input [5:0] io_core_commit_uops_0_lrs1, // @[lsu.scala:204:14] input [5:0] io_core_commit_uops_0_lrs2, // @[lsu.scala:204:14] input [5:0] io_core_commit_uops_0_lrs3, // @[lsu.scala:204:14] input io_core_commit_uops_0_ldst_val, // @[lsu.scala:204:14] input [1:0] io_core_commit_uops_0_dst_rtype, // @[lsu.scala:204:14] input [1:0] io_core_commit_uops_0_lrs1_rtype, // @[lsu.scala:204:14] input [1:0] io_core_commit_uops_0_lrs2_rtype, // @[lsu.scala:204:14] input io_core_commit_uops_0_frs3_en, // @[lsu.scala:204:14] input io_core_commit_uops_0_fp_val, // @[lsu.scala:204:14] input io_core_commit_uops_0_fp_single, // @[lsu.scala:204:14] input io_core_commit_uops_0_xcpt_pf_if, // @[lsu.scala:204:14] input io_core_commit_uops_0_xcpt_ae_if, // @[lsu.scala:204:14] input io_core_commit_uops_0_xcpt_ma_if, // @[lsu.scala:204:14] input io_core_commit_uops_0_bp_debug_if, // @[lsu.scala:204:14] input io_core_commit_uops_0_bp_xcpt_if, // @[lsu.scala:204:14] input [1:0] io_core_commit_uops_0_debug_fsrc, // @[lsu.scala:204:14] input [1:0] io_core_commit_uops_0_debug_tsrc, // @[lsu.scala:204:14] input io_core_commit_fflags_valid, // @[lsu.scala:204:14] input [4:0] io_core_commit_fflags_bits, // @[lsu.scala:204:14] input [31:0] io_core_commit_debug_insts_0, // @[lsu.scala:204:14] input io_core_commit_rbk_valids_0, // @[lsu.scala:204:14] input io_core_commit_rollback, // @[lsu.scala:204:14] input [63:0] io_core_commit_debug_wdata_0, // @[lsu.scala:204:14] input io_core_commit_load_at_rob_head, // @[lsu.scala:204:14] output io_core_clr_bsy_0_valid, // @[lsu.scala:204:14] output [4:0] io_core_clr_bsy_0_bits, // @[lsu.scala:204:14] output io_core_clr_bsy_1_valid, // @[lsu.scala:204:14] output [4:0] io_core_clr_bsy_1_bits, // @[lsu.scala:204:14] output [4:0] io_core_clr_unsafe_0_bits, // @[lsu.scala:204:14] input io_core_fence_dmem, // @[lsu.scala:204:14] output io_core_spec_ld_wakeup_0_valid, // @[lsu.scala:204:14] output [5:0] io_core_spec_ld_wakeup_0_bits, // @[lsu.scala:204:14] output io_core_ld_miss, // @[lsu.scala:204:14] input [7:0] io_core_brupdate_b1_resolve_mask, // @[lsu.scala:204:14] input [7:0] io_core_brupdate_b1_mispredict_mask, // @[lsu.scala:204:14] input [6:0] io_core_brupdate_b2_uop_uopc, // @[lsu.scala:204:14] input [31:0] io_core_brupdate_b2_uop_inst, // @[lsu.scala:204:14] input [31:0] io_core_brupdate_b2_uop_debug_inst, // @[lsu.scala:204:14] input io_core_brupdate_b2_uop_is_rvc, // @[lsu.scala:204:14] input [39:0] io_core_brupdate_b2_uop_debug_pc, // @[lsu.scala:204:14] input [2:0] io_core_brupdate_b2_uop_iq_type, // @[lsu.scala:204:14] input [9:0] io_core_brupdate_b2_uop_fu_code, // @[lsu.scala:204:14] input [3:0] io_core_brupdate_b2_uop_ctrl_br_type, // @[lsu.scala:204:14] input [1:0] io_core_brupdate_b2_uop_ctrl_op1_sel, // @[lsu.scala:204:14] input [2:0] io_core_brupdate_b2_uop_ctrl_op2_sel, // @[lsu.scala:204:14] input [2:0] io_core_brupdate_b2_uop_ctrl_imm_sel, // @[lsu.scala:204:14] input [4:0] io_core_brupdate_b2_uop_ctrl_op_fcn, // @[lsu.scala:204:14] input io_core_brupdate_b2_uop_ctrl_fcn_dw, // @[lsu.scala:204:14] input [2:0] io_core_brupdate_b2_uop_ctrl_csr_cmd, // @[lsu.scala:204:14] input io_core_brupdate_b2_uop_ctrl_is_load, // @[lsu.scala:204:14] input io_core_brupdate_b2_uop_ctrl_is_sta, // @[lsu.scala:204:14] input io_core_brupdate_b2_uop_ctrl_is_std, // @[lsu.scala:204:14] input [1:0] io_core_brupdate_b2_uop_iw_state, // @[lsu.scala:204:14] input io_core_brupdate_b2_uop_iw_p1_poisoned, // @[lsu.scala:204:14] input io_core_brupdate_b2_uop_iw_p2_poisoned, // @[lsu.scala:204:14] input io_core_brupdate_b2_uop_is_br, // @[lsu.scala:204:14] input io_core_brupdate_b2_uop_is_jalr, // @[lsu.scala:204:14] input io_core_brupdate_b2_uop_is_jal, // @[lsu.scala:204:14] input io_core_brupdate_b2_uop_is_sfb, // @[lsu.scala:204:14] input [7:0] io_core_brupdate_b2_uop_br_mask, // @[lsu.scala:204:14] input [2:0] io_core_brupdate_b2_uop_br_tag, // @[lsu.scala:204:14] input [3:0] io_core_brupdate_b2_uop_ftq_idx, // @[lsu.scala:204:14] input io_core_brupdate_b2_uop_edge_inst, // @[lsu.scala:204:14] input [5:0] io_core_brupdate_b2_uop_pc_lob, // @[lsu.scala:204:14] input io_core_brupdate_b2_uop_taken, // @[lsu.scala:204:14] input [19:0] io_core_brupdate_b2_uop_imm_packed, // @[lsu.scala:204:14] input [11:0] io_core_brupdate_b2_uop_csr_addr, // @[lsu.scala:204:14] input [4:0] io_core_brupdate_b2_uop_rob_idx, // @[lsu.scala:204:14] input [2:0] io_core_brupdate_b2_uop_ldq_idx, // @[lsu.scala:204:14] input [2:0] io_core_brupdate_b2_uop_stq_idx, // @[lsu.scala:204:14] input [1:0] io_core_brupdate_b2_uop_rxq_idx, // @[lsu.scala:204:14] input [5:0] io_core_brupdate_b2_uop_pdst, // @[lsu.scala:204:14] input [5:0] io_core_brupdate_b2_uop_prs1, // @[lsu.scala:204:14] input [5:0] io_core_brupdate_b2_uop_prs2, // @[lsu.scala:204:14] input [5:0] io_core_brupdate_b2_uop_prs3, // @[lsu.scala:204:14] input [3:0] io_core_brupdate_b2_uop_ppred, // @[lsu.scala:204:14] input io_core_brupdate_b2_uop_prs1_busy, // @[lsu.scala:204:14] input io_core_brupdate_b2_uop_prs2_busy, // @[lsu.scala:204:14] input io_core_brupdate_b2_uop_prs3_busy, // @[lsu.scala:204:14] input io_core_brupdate_b2_uop_ppred_busy, // @[lsu.scala:204:14] input [5:0] io_core_brupdate_b2_uop_stale_pdst, // @[lsu.scala:204:14] input io_core_brupdate_b2_uop_exception, // @[lsu.scala:204:14] input [63:0] io_core_brupdate_b2_uop_exc_cause, // @[lsu.scala:204:14] input io_core_brupdate_b2_uop_bypassable, // @[lsu.scala:204:14] input [4:0] io_core_brupdate_b2_uop_mem_cmd, // @[lsu.scala:204:14] input [1:0] io_core_brupdate_b2_uop_mem_size, // @[lsu.scala:204:14] input io_core_brupdate_b2_uop_mem_signed, // @[lsu.scala:204:14] input io_core_brupdate_b2_uop_is_fence, // @[lsu.scala:204:14] input io_core_brupdate_b2_uop_is_fencei, // @[lsu.scala:204:14] input io_core_brupdate_b2_uop_is_amo, // @[lsu.scala:204:14] input io_core_brupdate_b2_uop_uses_ldq, // @[lsu.scala:204:14] input io_core_brupdate_b2_uop_uses_stq, // @[lsu.scala:204:14] input io_core_brupdate_b2_uop_is_sys_pc2epc, // @[lsu.scala:204:14] input io_core_brupdate_b2_uop_is_unique, // @[lsu.scala:204:14] input io_core_brupdate_b2_uop_flush_on_commit, // @[lsu.scala:204:14] input io_core_brupdate_b2_uop_ldst_is_rs1, // @[lsu.scala:204:14] input [5:0] io_core_brupdate_b2_uop_ldst, // @[lsu.scala:204:14] input [5:0] io_core_brupdate_b2_uop_lrs1, // @[lsu.scala:204:14] input [5:0] io_core_brupdate_b2_uop_lrs2, // @[lsu.scala:204:14] input [5:0] io_core_brupdate_b2_uop_lrs3, // @[lsu.scala:204:14] input io_core_brupdate_b2_uop_ldst_val, // @[lsu.scala:204:14] input [1:0] io_core_brupdate_b2_uop_dst_rtype, // @[lsu.scala:204:14] input [1:0] io_core_brupdate_b2_uop_lrs1_rtype, // @[lsu.scala:204:14] input [1:0] io_core_brupdate_b2_uop_lrs2_rtype, // @[lsu.scala:204:14] input io_core_brupdate_b2_uop_frs3_en, // @[lsu.scala:204:14] input io_core_brupdate_b2_uop_fp_val, // @[lsu.scala:204:14] input io_core_brupdate_b2_uop_fp_single, // @[lsu.scala:204:14] input io_core_brupdate_b2_uop_xcpt_pf_if, // @[lsu.scala:204:14] input io_core_brupdate_b2_uop_xcpt_ae_if, // @[lsu.scala:204:14] input io_core_brupdate_b2_uop_xcpt_ma_if, // @[lsu.scala:204:14] input io_core_brupdate_b2_uop_bp_debug_if, // @[lsu.scala:204:14] input io_core_brupdate_b2_uop_bp_xcpt_if, // @[lsu.scala:204:14] input [1:0] io_core_brupdate_b2_uop_debug_fsrc, // @[lsu.scala:204:14] input [1:0] io_core_brupdate_b2_uop_debug_tsrc, // @[lsu.scala:204:14] input io_core_brupdate_b2_valid, // @[lsu.scala:204:14] input io_core_brupdate_b2_mispredict, // @[lsu.scala:204:14] input io_core_brupdate_b2_taken, // @[lsu.scala:204:14] input [2:0] io_core_brupdate_b2_cfi_type, // @[lsu.scala:204:14] input [1:0] io_core_brupdate_b2_pc_sel, // @[lsu.scala:204:14] input [39:0] io_core_brupdate_b2_jalr_target, // @[lsu.scala:204:14] input [20:0] io_core_brupdate_b2_target_offset, // @[lsu.scala:204:14] input [4:0] io_core_rob_pnr_idx, // @[lsu.scala:204:14] input [4:0] io_core_rob_head_idx, // @[lsu.scala:204:14] input io_core_exception, // @[lsu.scala:204:14] output io_core_fencei_rdy, // @[lsu.scala:204:14] output io_core_lxcpt_valid, // @[lsu.scala:204:14] output [6:0] io_core_lxcpt_bits_uop_uopc, // @[lsu.scala:204:14] output [31:0] io_core_lxcpt_bits_uop_inst, // @[lsu.scala:204:14] output [31:0] io_core_lxcpt_bits_uop_debug_inst, // @[lsu.scala:204:14] output io_core_lxcpt_bits_uop_is_rvc, // @[lsu.scala:204:14] output [39:0] io_core_lxcpt_bits_uop_debug_pc, // @[lsu.scala:204:14] output [2:0] io_core_lxcpt_bits_uop_iq_type, // @[lsu.scala:204:14] output [9:0] io_core_lxcpt_bits_uop_fu_code, // @[lsu.scala:204:14] output [3:0] io_core_lxcpt_bits_uop_ctrl_br_type, // @[lsu.scala:204:14] output [1:0] io_core_lxcpt_bits_uop_ctrl_op1_sel, // @[lsu.scala:204:14] output [2:0] io_core_lxcpt_bits_uop_ctrl_op2_sel, // @[lsu.scala:204:14] output [2:0] io_core_lxcpt_bits_uop_ctrl_imm_sel, // @[lsu.scala:204:14] output [4:0] io_core_lxcpt_bits_uop_ctrl_op_fcn, // @[lsu.scala:204:14] output io_core_lxcpt_bits_uop_ctrl_fcn_dw, // @[lsu.scala:204:14] output [2:0] io_core_lxcpt_bits_uop_ctrl_csr_cmd, // @[lsu.scala:204:14] output io_core_lxcpt_bits_uop_ctrl_is_load, // @[lsu.scala:204:14] output io_core_lxcpt_bits_uop_ctrl_is_sta, // @[lsu.scala:204:14] output io_core_lxcpt_bits_uop_ctrl_is_std, // @[lsu.scala:204:14] output [1:0] io_core_lxcpt_bits_uop_iw_state, // @[lsu.scala:204:14] output io_core_lxcpt_bits_uop_iw_p1_poisoned, // @[lsu.scala:204:14] output io_core_lxcpt_bits_uop_iw_p2_poisoned, // @[lsu.scala:204:14] output io_core_lxcpt_bits_uop_is_br, // @[lsu.scala:204:14] output io_core_lxcpt_bits_uop_is_jalr, // @[lsu.scala:204:14] output io_core_lxcpt_bits_uop_is_jal, // @[lsu.scala:204:14] output io_core_lxcpt_bits_uop_is_sfb, // @[lsu.scala:204:14] output [7:0] io_core_lxcpt_bits_uop_br_mask, // @[lsu.scala:204:14] output [2:0] io_core_lxcpt_bits_uop_br_tag, // @[lsu.scala:204:14] output [3:0] io_core_lxcpt_bits_uop_ftq_idx, // @[lsu.scala:204:14] output io_core_lxcpt_bits_uop_edge_inst, // @[lsu.scala:204:14] output [5:0] io_core_lxcpt_bits_uop_pc_lob, // @[lsu.scala:204:14] output io_core_lxcpt_bits_uop_taken, // @[lsu.scala:204:14] output [19:0] io_core_lxcpt_bits_uop_imm_packed, // @[lsu.scala:204:14] output [11:0] io_core_lxcpt_bits_uop_csr_addr, // @[lsu.scala:204:14] output [4:0] io_core_lxcpt_bits_uop_rob_idx, // @[lsu.scala:204:14] output [2:0] io_core_lxcpt_bits_uop_ldq_idx, // @[lsu.scala:204:14] output [2:0] io_core_lxcpt_bits_uop_stq_idx, // @[lsu.scala:204:14] output [1:0] io_core_lxcpt_bits_uop_rxq_idx, // @[lsu.scala:204:14] output [5:0] io_core_lxcpt_bits_uop_pdst, // @[lsu.scala:204:14] output [5:0] io_core_lxcpt_bits_uop_prs1, // @[lsu.scala:204:14] output [5:0] io_core_lxcpt_bits_uop_prs2, // @[lsu.scala:204:14] output [5:0] io_core_lxcpt_bits_uop_prs3, // @[lsu.scala:204:14] output [3:0] io_core_lxcpt_bits_uop_ppred, // @[lsu.scala:204:14] output io_core_lxcpt_bits_uop_prs1_busy, // @[lsu.scala:204:14] output io_core_lxcpt_bits_uop_prs2_busy, // @[lsu.scala:204:14] output io_core_lxcpt_bits_uop_prs3_busy, // @[lsu.scala:204:14] output io_core_lxcpt_bits_uop_ppred_busy, // @[lsu.scala:204:14] output [5:0] io_core_lxcpt_bits_uop_stale_pdst, // @[lsu.scala:204:14] output io_core_lxcpt_bits_uop_exception, // @[lsu.scala:204:14] output [63:0] io_core_lxcpt_bits_uop_exc_cause, // @[lsu.scala:204:14] output io_core_lxcpt_bits_uop_bypassable, // @[lsu.scala:204:14] output [4:0] io_core_lxcpt_bits_uop_mem_cmd, // @[lsu.scala:204:14] output [1:0] io_core_lxcpt_bits_uop_mem_size, // @[lsu.scala:204:14] output io_core_lxcpt_bits_uop_mem_signed, // @[lsu.scala:204:14] output io_core_lxcpt_bits_uop_is_fence, // @[lsu.scala:204:14] output io_core_lxcpt_bits_uop_is_fencei, // @[lsu.scala:204:14] output io_core_lxcpt_bits_uop_is_amo, // @[lsu.scala:204:14] output io_core_lxcpt_bits_uop_uses_ldq, // @[lsu.scala:204:14] output io_core_lxcpt_bits_uop_uses_stq, // @[lsu.scala:204:14] output io_core_lxcpt_bits_uop_is_sys_pc2epc, // @[lsu.scala:204:14] output io_core_lxcpt_bits_uop_is_unique, // @[lsu.scala:204:14] output io_core_lxcpt_bits_uop_flush_on_commit, // @[lsu.scala:204:14] output io_core_lxcpt_bits_uop_ldst_is_rs1, // @[lsu.scala:204:14] output [5:0] io_core_lxcpt_bits_uop_ldst, // @[lsu.scala:204:14] output [5:0] io_core_lxcpt_bits_uop_lrs1, // @[lsu.scala:204:14] output [5:0] io_core_lxcpt_bits_uop_lrs2, // @[lsu.scala:204:14] output [5:0] io_core_lxcpt_bits_uop_lrs3, // @[lsu.scala:204:14] output io_core_lxcpt_bits_uop_ldst_val, // @[lsu.scala:204:14] output [1:0] io_core_lxcpt_bits_uop_dst_rtype, // @[lsu.scala:204:14] output [1:0] io_core_lxcpt_bits_uop_lrs1_rtype, // @[lsu.scala:204:14] output [1:0] io_core_lxcpt_bits_uop_lrs2_rtype, // @[lsu.scala:204:14] output io_core_lxcpt_bits_uop_frs3_en, // @[lsu.scala:204:14] output io_core_lxcpt_bits_uop_fp_val, // @[lsu.scala:204:14] output io_core_lxcpt_bits_uop_fp_single, // @[lsu.scala:204:14] output io_core_lxcpt_bits_uop_xcpt_pf_if, // @[lsu.scala:204:14] output io_core_lxcpt_bits_uop_xcpt_ae_if, // @[lsu.scala:204:14] output io_core_lxcpt_bits_uop_xcpt_ma_if, // @[lsu.scala:204:14] output io_core_lxcpt_bits_uop_bp_debug_if, // @[lsu.scala:204:14] output io_core_lxcpt_bits_uop_bp_xcpt_if, // @[lsu.scala:204:14] output [1:0] io_core_lxcpt_bits_uop_debug_fsrc, // @[lsu.scala:204:14] output [1:0] io_core_lxcpt_bits_uop_debug_tsrc, // @[lsu.scala:204:14] output [4:0] io_core_lxcpt_bits_cause, // @[lsu.scala:204:14] output [39:0] io_core_lxcpt_bits_badvaddr, // @[lsu.scala:204:14] input [63:0] io_core_tsc_reg, // @[lsu.scala:204:14] output io_core_perf_acquire, // @[lsu.scala:204:14] output io_core_perf_release, // @[lsu.scala:204:14] output io_core_perf_tlbMiss, // @[lsu.scala:204:14] input io_dmem_req_ready, // @[lsu.scala:204:14] output io_dmem_req_valid, // @[lsu.scala:204:14] output io_dmem_req_bits_0_valid, // @[lsu.scala:204:14] output [6:0] io_dmem_req_bits_0_bits_uop_uopc, // @[lsu.scala:204:14] output [31:0] io_dmem_req_bits_0_bits_uop_inst, // @[lsu.scala:204:14] output [31:0] io_dmem_req_bits_0_bits_uop_debug_inst, // @[lsu.scala:204:14] output io_dmem_req_bits_0_bits_uop_is_rvc, // @[lsu.scala:204:14] output [39:0] io_dmem_req_bits_0_bits_uop_debug_pc, // @[lsu.scala:204:14] output [2:0] io_dmem_req_bits_0_bits_uop_iq_type, // @[lsu.scala:204:14] output [9:0] io_dmem_req_bits_0_bits_uop_fu_code, // @[lsu.scala:204:14] output [3:0] io_dmem_req_bits_0_bits_uop_ctrl_br_type, // @[lsu.scala:204:14] output [1:0] io_dmem_req_bits_0_bits_uop_ctrl_op1_sel, // @[lsu.scala:204:14] output [2:0] io_dmem_req_bits_0_bits_uop_ctrl_op2_sel, // @[lsu.scala:204:14] output [2:0] io_dmem_req_bits_0_bits_uop_ctrl_imm_sel, // @[lsu.scala:204:14] output [4:0] io_dmem_req_bits_0_bits_uop_ctrl_op_fcn, // @[lsu.scala:204:14] output io_dmem_req_bits_0_bits_uop_ctrl_fcn_dw, // @[lsu.scala:204:14] output [2:0] io_dmem_req_bits_0_bits_uop_ctrl_csr_cmd, // @[lsu.scala:204:14] output io_dmem_req_bits_0_bits_uop_ctrl_is_load, // @[lsu.scala:204:14] output io_dmem_req_bits_0_bits_uop_ctrl_is_sta, // @[lsu.scala:204:14] output io_dmem_req_bits_0_bits_uop_ctrl_is_std, // @[lsu.scala:204:14] output [1:0] io_dmem_req_bits_0_bits_uop_iw_state, // @[lsu.scala:204:14] output io_dmem_req_bits_0_bits_uop_iw_p1_poisoned, // @[lsu.scala:204:14] output io_dmem_req_bits_0_bits_uop_iw_p2_poisoned, // @[lsu.scala:204:14] output io_dmem_req_bits_0_bits_uop_is_br, // @[lsu.scala:204:14] output io_dmem_req_bits_0_bits_uop_is_jalr, // @[lsu.scala:204:14] output io_dmem_req_bits_0_bits_uop_is_jal, // @[lsu.scala:204:14] output io_dmem_req_bits_0_bits_uop_is_sfb, // @[lsu.scala:204:14] output [7:0] io_dmem_req_bits_0_bits_uop_br_mask, // @[lsu.scala:204:14] output [2:0] io_dmem_req_bits_0_bits_uop_br_tag, // @[lsu.scala:204:14] output [3:0] io_dmem_req_bits_0_bits_uop_ftq_idx, // @[lsu.scala:204:14] output io_dmem_req_bits_0_bits_uop_edge_inst, // @[lsu.scala:204:14] output [5:0] io_dmem_req_bits_0_bits_uop_pc_lob, // @[lsu.scala:204:14] output io_dmem_req_bits_0_bits_uop_taken, // @[lsu.scala:204:14] output [19:0] io_dmem_req_bits_0_bits_uop_imm_packed, // @[lsu.scala:204:14] output [11:0] io_dmem_req_bits_0_bits_uop_csr_addr, // @[lsu.scala:204:14] output [4:0] io_dmem_req_bits_0_bits_uop_rob_idx, // @[lsu.scala:204:14] output [2:0] io_dmem_req_bits_0_bits_uop_ldq_idx, // @[lsu.scala:204:14] output [2:0] io_dmem_req_bits_0_bits_uop_stq_idx, // @[lsu.scala:204:14] output [1:0] io_dmem_req_bits_0_bits_uop_rxq_idx, // @[lsu.scala:204:14] output [5:0] io_dmem_req_bits_0_bits_uop_pdst, // @[lsu.scala:204:14] output [5:0] io_dmem_req_bits_0_bits_uop_prs1, // @[lsu.scala:204:14] output [5:0] io_dmem_req_bits_0_bits_uop_prs2, // @[lsu.scala:204:14] output [5:0] io_dmem_req_bits_0_bits_uop_prs3, // @[lsu.scala:204:14] output [3:0] io_dmem_req_bits_0_bits_uop_ppred, // @[lsu.scala:204:14] output io_dmem_req_bits_0_bits_uop_prs1_busy, // @[lsu.scala:204:14] output io_dmem_req_bits_0_bits_uop_prs2_busy, // @[lsu.scala:204:14] output io_dmem_req_bits_0_bits_uop_prs3_busy, // @[lsu.scala:204:14] output io_dmem_req_bits_0_bits_uop_ppred_busy, // @[lsu.scala:204:14] output [5:0] io_dmem_req_bits_0_bits_uop_stale_pdst, // @[lsu.scala:204:14] output io_dmem_req_bits_0_bits_uop_exception, // @[lsu.scala:204:14] output [63:0] io_dmem_req_bits_0_bits_uop_exc_cause, // @[lsu.scala:204:14] output io_dmem_req_bits_0_bits_uop_bypassable, // @[lsu.scala:204:14] output [4:0] io_dmem_req_bits_0_bits_uop_mem_cmd, // @[lsu.scala:204:14] output [1:0] io_dmem_req_bits_0_bits_uop_mem_size, // @[lsu.scala:204:14] output io_dmem_req_bits_0_bits_uop_mem_signed, // @[lsu.scala:204:14] output io_dmem_req_bits_0_bits_uop_is_fence, // @[lsu.scala:204:14] output io_dmem_req_bits_0_bits_uop_is_fencei, // @[lsu.scala:204:14] output io_dmem_req_bits_0_bits_uop_is_amo, // @[lsu.scala:204:14] output io_dmem_req_bits_0_bits_uop_uses_ldq, // @[lsu.scala:204:14] output io_dmem_req_bits_0_bits_uop_uses_stq, // @[lsu.scala:204:14] output io_dmem_req_bits_0_bits_uop_is_sys_pc2epc, // @[lsu.scala:204:14] output io_dmem_req_bits_0_bits_uop_is_unique, // @[lsu.scala:204:14] output io_dmem_req_bits_0_bits_uop_flush_on_commit, // @[lsu.scala:204:14] output io_dmem_req_bits_0_bits_uop_ldst_is_rs1, // @[lsu.scala:204:14] output [5:0] io_dmem_req_bits_0_bits_uop_ldst, // @[lsu.scala:204:14] output [5:0] io_dmem_req_bits_0_bits_uop_lrs1, // @[lsu.scala:204:14] output [5:0] io_dmem_req_bits_0_bits_uop_lrs2, // @[lsu.scala:204:14] output [5:0] io_dmem_req_bits_0_bits_uop_lrs3, // @[lsu.scala:204:14] output io_dmem_req_bits_0_bits_uop_ldst_val, // @[lsu.scala:204:14] output [1:0] io_dmem_req_bits_0_bits_uop_dst_rtype, // @[lsu.scala:204:14] output [1:0] io_dmem_req_bits_0_bits_uop_lrs1_rtype, // @[lsu.scala:204:14] output [1:0] io_dmem_req_bits_0_bits_uop_lrs2_rtype, // @[lsu.scala:204:14] output io_dmem_req_bits_0_bits_uop_frs3_en, // @[lsu.scala:204:14] output io_dmem_req_bits_0_bits_uop_fp_val, // @[lsu.scala:204:14] output io_dmem_req_bits_0_bits_uop_fp_single, // @[lsu.scala:204:14] output io_dmem_req_bits_0_bits_uop_xcpt_pf_if, // @[lsu.scala:204:14] output io_dmem_req_bits_0_bits_uop_xcpt_ae_if, // @[lsu.scala:204:14] output io_dmem_req_bits_0_bits_uop_xcpt_ma_if, // @[lsu.scala:204:14] output io_dmem_req_bits_0_bits_uop_bp_debug_if, // @[lsu.scala:204:14] output io_dmem_req_bits_0_bits_uop_bp_xcpt_if, // @[lsu.scala:204:14] output [1:0] io_dmem_req_bits_0_bits_uop_debug_fsrc, // @[lsu.scala:204:14] output [1:0] io_dmem_req_bits_0_bits_uop_debug_tsrc, // @[lsu.scala:204:14] output [39:0] io_dmem_req_bits_0_bits_addr, // @[lsu.scala:204:14] output [63:0] io_dmem_req_bits_0_bits_data, // @[lsu.scala:204:14] output io_dmem_req_bits_0_bits_is_hella, // @[lsu.scala:204:14] output io_dmem_s1_kill_0, // @[lsu.scala:204:14] input io_dmem_resp_0_valid, // @[lsu.scala:204:14] input [6:0] io_dmem_resp_0_bits_uop_uopc, // @[lsu.scala:204:14] input [31:0] io_dmem_resp_0_bits_uop_inst, // @[lsu.scala:204:14] input [31:0] io_dmem_resp_0_bits_uop_debug_inst, // @[lsu.scala:204:14] input io_dmem_resp_0_bits_uop_is_rvc, // @[lsu.scala:204:14] input [39:0] io_dmem_resp_0_bits_uop_debug_pc, // @[lsu.scala:204:14] input [2:0] io_dmem_resp_0_bits_uop_iq_type, // @[lsu.scala:204:14] input [9:0] io_dmem_resp_0_bits_uop_fu_code, // @[lsu.scala:204:14] input [3:0] io_dmem_resp_0_bits_uop_ctrl_br_type, // @[lsu.scala:204:14] input [1:0] io_dmem_resp_0_bits_uop_ctrl_op1_sel, // @[lsu.scala:204:14] input [2:0] io_dmem_resp_0_bits_uop_ctrl_op2_sel, // @[lsu.scala:204:14] input [2:0] io_dmem_resp_0_bits_uop_ctrl_imm_sel, // @[lsu.scala:204:14] input [4:0] io_dmem_resp_0_bits_uop_ctrl_op_fcn, // @[lsu.scala:204:14] input io_dmem_resp_0_bits_uop_ctrl_fcn_dw, // @[lsu.scala:204:14] input [2:0] io_dmem_resp_0_bits_uop_ctrl_csr_cmd, // @[lsu.scala:204:14] input io_dmem_resp_0_bits_uop_ctrl_is_load, // @[lsu.scala:204:14] input io_dmem_resp_0_bits_uop_ctrl_is_sta, // @[lsu.scala:204:14] input io_dmem_resp_0_bits_uop_ctrl_is_std, // @[lsu.scala:204:14] input [1:0] io_dmem_resp_0_bits_uop_iw_state, // @[lsu.scala:204:14] input io_dmem_resp_0_bits_uop_iw_p1_poisoned, // @[lsu.scala:204:14] input io_dmem_resp_0_bits_uop_iw_p2_poisoned, // @[lsu.scala:204:14] input io_dmem_resp_0_bits_uop_is_br, // @[lsu.scala:204:14] input io_dmem_resp_0_bits_uop_is_jalr, // @[lsu.scala:204:14] input io_dmem_resp_0_bits_uop_is_jal, // @[lsu.scala:204:14] input io_dmem_resp_0_bits_uop_is_sfb, // @[lsu.scala:204:14] input [7:0] io_dmem_resp_0_bits_uop_br_mask, // @[lsu.scala:204:14] input [2:0] io_dmem_resp_0_bits_uop_br_tag, // @[lsu.scala:204:14] input [3:0] io_dmem_resp_0_bits_uop_ftq_idx, // @[lsu.scala:204:14] input io_dmem_resp_0_bits_uop_edge_inst, // @[lsu.scala:204:14] input [5:0] io_dmem_resp_0_bits_uop_pc_lob, // @[lsu.scala:204:14] input io_dmem_resp_0_bits_uop_taken, // @[lsu.scala:204:14] input [19:0] io_dmem_resp_0_bits_uop_imm_packed, // @[lsu.scala:204:14] input [11:0] io_dmem_resp_0_bits_uop_csr_addr, // @[lsu.scala:204:14] input [4:0] io_dmem_resp_0_bits_uop_rob_idx, // @[lsu.scala:204:14] input [2:0] io_dmem_resp_0_bits_uop_ldq_idx, // @[lsu.scala:204:14] input [2:0] io_dmem_resp_0_bits_uop_stq_idx, // @[lsu.scala:204:14] input [1:0] io_dmem_resp_0_bits_uop_rxq_idx, // @[lsu.scala:204:14] input [5:0] io_dmem_resp_0_bits_uop_pdst, // @[lsu.scala:204:14] input [5:0] io_dmem_resp_0_bits_uop_prs1, // @[lsu.scala:204:14] input [5:0] io_dmem_resp_0_bits_uop_prs2, // @[lsu.scala:204:14] input [5:0] io_dmem_resp_0_bits_uop_prs3, // @[lsu.scala:204:14] input [3:0] io_dmem_resp_0_bits_uop_ppred, // @[lsu.scala:204:14] input io_dmem_resp_0_bits_uop_prs1_busy, // @[lsu.scala:204:14] input io_dmem_resp_0_bits_uop_prs2_busy, // @[lsu.scala:204:14] input io_dmem_resp_0_bits_uop_prs3_busy, // @[lsu.scala:204:14] input io_dmem_resp_0_bits_uop_ppred_busy, // @[lsu.scala:204:14] input [5:0] io_dmem_resp_0_bits_uop_stale_pdst, // @[lsu.scala:204:14] input io_dmem_resp_0_bits_uop_exception, // @[lsu.scala:204:14] input [63:0] io_dmem_resp_0_bits_uop_exc_cause, // @[lsu.scala:204:14] input io_dmem_resp_0_bits_uop_bypassable, // @[lsu.scala:204:14] input [4:0] io_dmem_resp_0_bits_uop_mem_cmd, // @[lsu.scala:204:14] input [1:0] io_dmem_resp_0_bits_uop_mem_size, // @[lsu.scala:204:14] input io_dmem_resp_0_bits_uop_mem_signed, // @[lsu.scala:204:14] input io_dmem_resp_0_bits_uop_is_fence, // @[lsu.scala:204:14] input io_dmem_resp_0_bits_uop_is_fencei, // @[lsu.scala:204:14] input io_dmem_resp_0_bits_uop_is_amo, // @[lsu.scala:204:14] input io_dmem_resp_0_bits_uop_uses_ldq, // @[lsu.scala:204:14] input io_dmem_resp_0_bits_uop_uses_stq, // @[lsu.scala:204:14] input io_dmem_resp_0_bits_uop_is_sys_pc2epc, // @[lsu.scala:204:14] input io_dmem_resp_0_bits_uop_is_unique, // @[lsu.scala:204:14] input io_dmem_resp_0_bits_uop_flush_on_commit, // @[lsu.scala:204:14] input io_dmem_resp_0_bits_uop_ldst_is_rs1, // @[lsu.scala:204:14] input [5:0] io_dmem_resp_0_bits_uop_ldst, // @[lsu.scala:204:14] input [5:0] io_dmem_resp_0_bits_uop_lrs1, // @[lsu.scala:204:14] input [5:0] io_dmem_resp_0_bits_uop_lrs2, // @[lsu.scala:204:14] input [5:0] io_dmem_resp_0_bits_uop_lrs3, // @[lsu.scala:204:14] input io_dmem_resp_0_bits_uop_ldst_val, // @[lsu.scala:204:14] input [1:0] io_dmem_resp_0_bits_uop_dst_rtype, // @[lsu.scala:204:14] input [1:0] io_dmem_resp_0_bits_uop_lrs1_rtype, // @[lsu.scala:204:14] input [1:0] io_dmem_resp_0_bits_uop_lrs2_rtype, // @[lsu.scala:204:14] input io_dmem_resp_0_bits_uop_frs3_en, // @[lsu.scala:204:14] input io_dmem_resp_0_bits_uop_fp_val, // @[lsu.scala:204:14] input io_dmem_resp_0_bits_uop_fp_single, // @[lsu.scala:204:14] input io_dmem_resp_0_bits_uop_xcpt_pf_if, // @[lsu.scala:204:14] input io_dmem_resp_0_bits_uop_xcpt_ae_if, // @[lsu.scala:204:14] input io_dmem_resp_0_bits_uop_xcpt_ma_if, // @[lsu.scala:204:14] input io_dmem_resp_0_bits_uop_bp_debug_if, // @[lsu.scala:204:14] input io_dmem_resp_0_bits_uop_bp_xcpt_if, // @[lsu.scala:204:14] input [1:0] io_dmem_resp_0_bits_uop_debug_fsrc, // @[lsu.scala:204:14] input [1:0] io_dmem_resp_0_bits_uop_debug_tsrc, // @[lsu.scala:204:14] input [63:0] io_dmem_resp_0_bits_data, // @[lsu.scala:204:14] input io_dmem_resp_0_bits_is_hella, // @[lsu.scala:204:14] input io_dmem_nack_0_valid, // @[lsu.scala:204:14] input [6:0] io_dmem_nack_0_bits_uop_uopc, // @[lsu.scala:204:14] input [31:0] io_dmem_nack_0_bits_uop_inst, // @[lsu.scala:204:14] input [31:0] io_dmem_nack_0_bits_uop_debug_inst, // @[lsu.scala:204:14] input io_dmem_nack_0_bits_uop_is_rvc, // @[lsu.scala:204:14] input [39:0] io_dmem_nack_0_bits_uop_debug_pc, // @[lsu.scala:204:14] input [2:0] io_dmem_nack_0_bits_uop_iq_type, // @[lsu.scala:204:14] input [9:0] io_dmem_nack_0_bits_uop_fu_code, // @[lsu.scala:204:14] input [3:0] io_dmem_nack_0_bits_uop_ctrl_br_type, // @[lsu.scala:204:14] input [1:0] io_dmem_nack_0_bits_uop_ctrl_op1_sel, // @[lsu.scala:204:14] input [2:0] io_dmem_nack_0_bits_uop_ctrl_op2_sel, // @[lsu.scala:204:14] input [2:0] io_dmem_nack_0_bits_uop_ctrl_imm_sel, // @[lsu.scala:204:14] input [4:0] io_dmem_nack_0_bits_uop_ctrl_op_fcn, // @[lsu.scala:204:14] input io_dmem_nack_0_bits_uop_ctrl_fcn_dw, // @[lsu.scala:204:14] input [2:0] io_dmem_nack_0_bits_uop_ctrl_csr_cmd, // @[lsu.scala:204:14] input io_dmem_nack_0_bits_uop_ctrl_is_load, // @[lsu.scala:204:14] input io_dmem_nack_0_bits_uop_ctrl_is_sta, // @[lsu.scala:204:14] input io_dmem_nack_0_bits_uop_ctrl_is_std, // @[lsu.scala:204:14] input [1:0] io_dmem_nack_0_bits_uop_iw_state, // @[lsu.scala:204:14] input io_dmem_nack_0_bits_uop_iw_p1_poisoned, // @[lsu.scala:204:14] input io_dmem_nack_0_bits_uop_iw_p2_poisoned, // @[lsu.scala:204:14] input io_dmem_nack_0_bits_uop_is_br, // @[lsu.scala:204:14] input io_dmem_nack_0_bits_uop_is_jalr, // @[lsu.scala:204:14] input io_dmem_nack_0_bits_uop_is_jal, // @[lsu.scala:204:14] input io_dmem_nack_0_bits_uop_is_sfb, // @[lsu.scala:204:14] input [7:0] io_dmem_nack_0_bits_uop_br_mask, // @[lsu.scala:204:14] input [2:0] io_dmem_nack_0_bits_uop_br_tag, // @[lsu.scala:204:14] input [3:0] io_dmem_nack_0_bits_uop_ftq_idx, // @[lsu.scala:204:14] input io_dmem_nack_0_bits_uop_edge_inst, // @[lsu.scala:204:14] input [5:0] io_dmem_nack_0_bits_uop_pc_lob, // @[lsu.scala:204:14] input io_dmem_nack_0_bits_uop_taken, // @[lsu.scala:204:14] input [19:0] io_dmem_nack_0_bits_uop_imm_packed, // @[lsu.scala:204:14] input [11:0] io_dmem_nack_0_bits_uop_csr_addr, // @[lsu.scala:204:14] input [4:0] io_dmem_nack_0_bits_uop_rob_idx, // @[lsu.scala:204:14] input [2:0] io_dmem_nack_0_bits_uop_ldq_idx, // @[lsu.scala:204:14] input [2:0] io_dmem_nack_0_bits_uop_stq_idx, // @[lsu.scala:204:14] input [1:0] io_dmem_nack_0_bits_uop_rxq_idx, // @[lsu.scala:204:14] input [5:0] io_dmem_nack_0_bits_uop_pdst, // @[lsu.scala:204:14] input [5:0] io_dmem_nack_0_bits_uop_prs1, // @[lsu.scala:204:14] input [5:0] io_dmem_nack_0_bits_uop_prs2, // @[lsu.scala:204:14] input [5:0] io_dmem_nack_0_bits_uop_prs3, // @[lsu.scala:204:14] input [3:0] io_dmem_nack_0_bits_uop_ppred, // @[lsu.scala:204:14] input io_dmem_nack_0_bits_uop_prs1_busy, // @[lsu.scala:204:14] input io_dmem_nack_0_bits_uop_prs2_busy, // @[lsu.scala:204:14] input io_dmem_nack_0_bits_uop_prs3_busy, // @[lsu.scala:204:14] input io_dmem_nack_0_bits_uop_ppred_busy, // @[lsu.scala:204:14] input [5:0] io_dmem_nack_0_bits_uop_stale_pdst, // @[lsu.scala:204:14] input io_dmem_nack_0_bits_uop_exception, // @[lsu.scala:204:14] input [63:0] io_dmem_nack_0_bits_uop_exc_cause, // @[lsu.scala:204:14] input io_dmem_nack_0_bits_uop_bypassable, // @[lsu.scala:204:14] input [4:0] io_dmem_nack_0_bits_uop_mem_cmd, // @[lsu.scala:204:14] input [1:0] io_dmem_nack_0_bits_uop_mem_size, // @[lsu.scala:204:14] input io_dmem_nack_0_bits_uop_mem_signed, // @[lsu.scala:204:14] input io_dmem_nack_0_bits_uop_is_fence, // @[lsu.scala:204:14] input io_dmem_nack_0_bits_uop_is_fencei, // @[lsu.scala:204:14] input io_dmem_nack_0_bits_uop_is_amo, // @[lsu.scala:204:14] input io_dmem_nack_0_bits_uop_uses_ldq, // @[lsu.scala:204:14] input io_dmem_nack_0_bits_uop_uses_stq, // @[lsu.scala:204:14] input io_dmem_nack_0_bits_uop_is_sys_pc2epc, // @[lsu.scala:204:14] input io_dmem_nack_0_bits_uop_is_unique, // @[lsu.scala:204:14] input io_dmem_nack_0_bits_uop_flush_on_commit, // @[lsu.scala:204:14] input io_dmem_nack_0_bits_uop_ldst_is_rs1, // @[lsu.scala:204:14] input [5:0] io_dmem_nack_0_bits_uop_ldst, // @[lsu.scala:204:14] input [5:0] io_dmem_nack_0_bits_uop_lrs1, // @[lsu.scala:204:14] input [5:0] io_dmem_nack_0_bits_uop_lrs2, // @[lsu.scala:204:14] input [5:0] io_dmem_nack_0_bits_uop_lrs3, // @[lsu.scala:204:14] input io_dmem_nack_0_bits_uop_ldst_val, // @[lsu.scala:204:14] input [1:0] io_dmem_nack_0_bits_uop_dst_rtype, // @[lsu.scala:204:14] input [1:0] io_dmem_nack_0_bits_uop_lrs1_rtype, // @[lsu.scala:204:14] input [1:0] io_dmem_nack_0_bits_uop_lrs2_rtype, // @[lsu.scala:204:14] input io_dmem_nack_0_bits_uop_frs3_en, // @[lsu.scala:204:14] input io_dmem_nack_0_bits_uop_fp_val, // @[lsu.scala:204:14] input io_dmem_nack_0_bits_uop_fp_single, // @[lsu.scala:204:14] input io_dmem_nack_0_bits_uop_xcpt_pf_if, // @[lsu.scala:204:14] input io_dmem_nack_0_bits_uop_xcpt_ae_if, // @[lsu.scala:204:14] input io_dmem_nack_0_bits_uop_xcpt_ma_if, // @[lsu.scala:204:14] input io_dmem_nack_0_bits_uop_bp_debug_if, // @[lsu.scala:204:14] input io_dmem_nack_0_bits_uop_bp_xcpt_if, // @[lsu.scala:204:14] input [1:0] io_dmem_nack_0_bits_uop_debug_fsrc, // @[lsu.scala:204:14] input [1:0] io_dmem_nack_0_bits_uop_debug_tsrc, // @[lsu.scala:204:14] input [39:0] io_dmem_nack_0_bits_addr, // @[lsu.scala:204:14] input [63:0] io_dmem_nack_0_bits_data, // @[lsu.scala:204:14] input io_dmem_nack_0_bits_is_hella, // @[lsu.scala:204:14] output [7:0] io_dmem_brupdate_b1_resolve_mask, // @[lsu.scala:204:14] output [7:0] io_dmem_brupdate_b1_mispredict_mask, // @[lsu.scala:204:14] output [6:0] io_dmem_brupdate_b2_uop_uopc, // @[lsu.scala:204:14] output [31:0] io_dmem_brupdate_b2_uop_inst, // @[lsu.scala:204:14] output [31:0] io_dmem_brupdate_b2_uop_debug_inst, // @[lsu.scala:204:14] output io_dmem_brupdate_b2_uop_is_rvc, // @[lsu.scala:204:14] output [39:0] io_dmem_brupdate_b2_uop_debug_pc, // @[lsu.scala:204:14] output [2:0] io_dmem_brupdate_b2_uop_iq_type, // @[lsu.scala:204:14] output [9:0] io_dmem_brupdate_b2_uop_fu_code, // @[lsu.scala:204:14] output [3:0] io_dmem_brupdate_b2_uop_ctrl_br_type, // @[lsu.scala:204:14] output [1:0] io_dmem_brupdate_b2_uop_ctrl_op1_sel, // @[lsu.scala:204:14] output [2:0] io_dmem_brupdate_b2_uop_ctrl_op2_sel, // @[lsu.scala:204:14] output [2:0] io_dmem_brupdate_b2_uop_ctrl_imm_sel, // @[lsu.scala:204:14] output [4:0] io_dmem_brupdate_b2_uop_ctrl_op_fcn, // @[lsu.scala:204:14] output io_dmem_brupdate_b2_uop_ctrl_fcn_dw, // @[lsu.scala:204:14] output [2:0] io_dmem_brupdate_b2_uop_ctrl_csr_cmd, // @[lsu.scala:204:14] output io_dmem_brupdate_b2_uop_ctrl_is_load, // @[lsu.scala:204:14] output io_dmem_brupdate_b2_uop_ctrl_is_sta, // @[lsu.scala:204:14] output io_dmem_brupdate_b2_uop_ctrl_is_std, // @[lsu.scala:204:14] output [1:0] io_dmem_brupdate_b2_uop_iw_state, // @[lsu.scala:204:14] output io_dmem_brupdate_b2_uop_iw_p1_poisoned, // @[lsu.scala:204:14] output io_dmem_brupdate_b2_uop_iw_p2_poisoned, // @[lsu.scala:204:14] output io_dmem_brupdate_b2_uop_is_br, // @[lsu.scala:204:14] output io_dmem_brupdate_b2_uop_is_jalr, // @[lsu.scala:204:14] output io_dmem_brupdate_b2_uop_is_jal, // @[lsu.scala:204:14] output io_dmem_brupdate_b2_uop_is_sfb, // @[lsu.scala:204:14] output [7:0] io_dmem_brupdate_b2_uop_br_mask, // @[lsu.scala:204:14] output [2:0] io_dmem_brupdate_b2_uop_br_tag, // @[lsu.scala:204:14] output [3:0] io_dmem_brupdate_b2_uop_ftq_idx, // @[lsu.scala:204:14] output io_dmem_brupdate_b2_uop_edge_inst, // @[lsu.scala:204:14] output [5:0] io_dmem_brupdate_b2_uop_pc_lob, // @[lsu.scala:204:14] output io_dmem_brupdate_b2_uop_taken, // @[lsu.scala:204:14] output [19:0] io_dmem_brupdate_b2_uop_imm_packed, // @[lsu.scala:204:14] output [11:0] io_dmem_brupdate_b2_uop_csr_addr, // @[lsu.scala:204:14] output [4:0] io_dmem_brupdate_b2_uop_rob_idx, // @[lsu.scala:204:14] output [2:0] io_dmem_brupdate_b2_uop_ldq_idx, // @[lsu.scala:204:14] output [2:0] io_dmem_brupdate_b2_uop_stq_idx, // @[lsu.scala:204:14] output [1:0] io_dmem_brupdate_b2_uop_rxq_idx, // @[lsu.scala:204:14] output [5:0] io_dmem_brupdate_b2_uop_pdst, // @[lsu.scala:204:14] output [5:0] io_dmem_brupdate_b2_uop_prs1, // @[lsu.scala:204:14] output [5:0] io_dmem_brupdate_b2_uop_prs2, // @[lsu.scala:204:14] output [5:0] io_dmem_brupdate_b2_uop_prs3, // @[lsu.scala:204:14] output [3:0] io_dmem_brupdate_b2_uop_ppred, // @[lsu.scala:204:14] output io_dmem_brupdate_b2_uop_prs1_busy, // @[lsu.scala:204:14] output io_dmem_brupdate_b2_uop_prs2_busy, // @[lsu.scala:204:14] output io_dmem_brupdate_b2_uop_prs3_busy, // @[lsu.scala:204:14] output io_dmem_brupdate_b2_uop_ppred_busy, // @[lsu.scala:204:14] output [5:0] io_dmem_brupdate_b2_uop_stale_pdst, // @[lsu.scala:204:14] output io_dmem_brupdate_b2_uop_exception, // @[lsu.scala:204:14] output [63:0] io_dmem_brupdate_b2_uop_exc_cause, // @[lsu.scala:204:14] output io_dmem_brupdate_b2_uop_bypassable, // @[lsu.scala:204:14] output [4:0] io_dmem_brupdate_b2_uop_mem_cmd, // @[lsu.scala:204:14] output [1:0] io_dmem_brupdate_b2_uop_mem_size, // @[lsu.scala:204:14] output io_dmem_brupdate_b2_uop_mem_signed, // @[lsu.scala:204:14] output io_dmem_brupdate_b2_uop_is_fence, // @[lsu.scala:204:14] output io_dmem_brupdate_b2_uop_is_fencei, // @[lsu.scala:204:14] output io_dmem_brupdate_b2_uop_is_amo, // @[lsu.scala:204:14] output io_dmem_brupdate_b2_uop_uses_ldq, // @[lsu.scala:204:14] output io_dmem_brupdate_b2_uop_uses_stq, // @[lsu.scala:204:14] output io_dmem_brupdate_b2_uop_is_sys_pc2epc, // @[lsu.scala:204:14] output io_dmem_brupdate_b2_uop_is_unique, // @[lsu.scala:204:14] output io_dmem_brupdate_b2_uop_flush_on_commit, // @[lsu.scala:204:14] output io_dmem_brupdate_b2_uop_ldst_is_rs1, // @[lsu.scala:204:14] output [5:0] io_dmem_brupdate_b2_uop_ldst, // @[lsu.scala:204:14] output [5:0] io_dmem_brupdate_b2_uop_lrs1, // @[lsu.scala:204:14] output [5:0] io_dmem_brupdate_b2_uop_lrs2, // @[lsu.scala:204:14] output [5:0] io_dmem_brupdate_b2_uop_lrs3, // @[lsu.scala:204:14] output io_dmem_brupdate_b2_uop_ldst_val, // @[lsu.scala:204:14] output [1:0] io_dmem_brupdate_b2_uop_dst_rtype, // @[lsu.scala:204:14] output [1:0] io_dmem_brupdate_b2_uop_lrs1_rtype, // @[lsu.scala:204:14] output [1:0] io_dmem_brupdate_b2_uop_lrs2_rtype, // @[lsu.scala:204:14] output io_dmem_brupdate_b2_uop_frs3_en, // @[lsu.scala:204:14] output io_dmem_brupdate_b2_uop_fp_val, // @[lsu.scala:204:14] output io_dmem_brupdate_b2_uop_fp_single, // @[lsu.scala:204:14] output io_dmem_brupdate_b2_uop_xcpt_pf_if, // @[lsu.scala:204:14] output io_dmem_brupdate_b2_uop_xcpt_ae_if, // @[lsu.scala:204:14] output io_dmem_brupdate_b2_uop_xcpt_ma_if, // @[lsu.scala:204:14] output io_dmem_brupdate_b2_uop_bp_debug_if, // @[lsu.scala:204:14] output io_dmem_brupdate_b2_uop_bp_xcpt_if, // @[lsu.scala:204:14] output [1:0] io_dmem_brupdate_b2_uop_debug_fsrc, // @[lsu.scala:204:14] output [1:0] io_dmem_brupdate_b2_uop_debug_tsrc, // @[lsu.scala:204:14] output io_dmem_brupdate_b2_valid, // @[lsu.scala:204:14] output io_dmem_brupdate_b2_mispredict, // @[lsu.scala:204:14] output io_dmem_brupdate_b2_taken, // @[lsu.scala:204:14] output [2:0] io_dmem_brupdate_b2_cfi_type, // @[lsu.scala:204:14] output [1:0] io_dmem_brupdate_b2_pc_sel, // @[lsu.scala:204:14] output [39:0] io_dmem_brupdate_b2_jalr_target, // @[lsu.scala:204:14] output [20:0] io_dmem_brupdate_b2_target_offset, // @[lsu.scala:204:14] output io_dmem_exception, // @[lsu.scala:204:14] output [4:0] io_dmem_rob_pnr_idx, // @[lsu.scala:204:14] output [4:0] io_dmem_rob_head_idx, // @[lsu.scala:204:14] output io_dmem_release_ready, // @[lsu.scala:204:14] input io_dmem_release_valid, // @[lsu.scala:204:14] input [2:0] io_dmem_release_bits_opcode, // @[lsu.scala:204:14] input [2:0] io_dmem_release_bits_param, // @[lsu.scala:204:14] input [3:0] io_dmem_release_bits_size, // @[lsu.scala:204:14] input [1:0] io_dmem_release_bits_source, // @[lsu.scala:204:14] input [31:0] io_dmem_release_bits_address, // @[lsu.scala:204:14] input [63:0] io_dmem_release_bits_data, // @[lsu.scala:204:14] output io_dmem_force_order, // @[lsu.scala:204:14] input io_dmem_ordered, // @[lsu.scala:204:14] input io_dmem_perf_acquire, // @[lsu.scala:204:14] input io_dmem_perf_release, // @[lsu.scala:204:14] output io_hellacache_req_ready, // @[lsu.scala:204:14] input io_hellacache_req_valid, // @[lsu.scala:204:14] input [39:0] io_hellacache_req_bits_addr, // @[lsu.scala:204:14] input io_hellacache_req_bits_dv, // @[lsu.scala:204:14] input io_hellacache_s1_kill, // @[lsu.scala:204:14] output io_hellacache_s2_nack, // @[lsu.scala:204:14] output io_hellacache_resp_valid, // @[lsu.scala:204:14] output [39:0] io_hellacache_resp_bits_addr, // @[lsu.scala:204:14] output [63:0] io_hellacache_resp_bits_data, // @[lsu.scala:204:14] output io_hellacache_s2_xcpt_ma_ld, // @[lsu.scala:204:14] output io_hellacache_s2_xcpt_ma_st, // @[lsu.scala:204:14] output io_hellacache_s2_xcpt_pf_ld, // @[lsu.scala:204:14] output io_hellacache_s2_xcpt_pf_st, // @[lsu.scala:204:14] output io_hellacache_s2_xcpt_gf_ld, // @[lsu.scala:204:14] output io_hellacache_s2_xcpt_gf_st, // @[lsu.scala:204:14] output io_hellacache_s2_xcpt_ae_ld, // @[lsu.scala:204:14] output io_hellacache_s2_xcpt_ae_st, // @[lsu.scala:204:14] output io_hellacache_store_pending // @[lsu.scala:204:14] ); wire failed_loads_6; // @[lsu.scala:1054:34] wire failed_loads_5; // @[lsu.scala:1054:34] wire failed_loads_4; // @[lsu.scala:1054:34] wire failed_loads_3; // @[lsu.scala:1054:34] wire failed_loads_2; // @[lsu.scala:1054:34] wire failed_loads_1; // @[lsu.scala:1054:34] wire failed_loads_0; // @[lsu.scala:1054:34] wire mem_stq_incoming_e_out_valid; // @[util.scala:106:23] wire [7:0] mem_stq_incoming_e_out_bits_uop_br_mask; // @[util.scala:106:23] wire mem_ldq_incoming_e_out_valid; // @[util.scala:106:23] wire [7:0] mem_ldq_incoming_e_out_bits_uop_br_mask; // @[util.scala:106:23] wire [7:0] mem_incoming_uop_out_br_mask; // @[util.scala:96:23] wire [7:0] mem_xcpt_uops_out_br_mask; // @[util.scala:96:23] wire [63:0] stq_incoming_e_0_bits_debug_wb_data; // @[lsu.scala:263:49] wire stq_incoming_e_0_bits_succeeded; // @[lsu.scala:263:49] wire stq_incoming_e_0_bits_committed; // @[lsu.scala:263:49] wire stq_incoming_e_0_bits_addr_is_virtual; // @[lsu.scala:263:49] wire [63:0] stq_incoming_e_0_bits_data_bits; // @[lsu.scala:263:49] wire stq_incoming_e_0_bits_data_valid; // @[lsu.scala:263:49] wire [39:0] stq_incoming_e_0_bits_addr_bits; // @[lsu.scala:263:49] wire stq_incoming_e_0_bits_addr_valid; // @[lsu.scala:263:49] wire [1:0] stq_incoming_e_0_bits_uop_debug_tsrc; // @[lsu.scala:263:49] wire [1:0] stq_incoming_e_0_bits_uop_debug_fsrc; // @[lsu.scala:263:49] wire stq_incoming_e_0_bits_uop_bp_xcpt_if; // @[lsu.scala:263:49] wire stq_incoming_e_0_bits_uop_bp_debug_if; // @[lsu.scala:263:49] wire stq_incoming_e_0_bits_uop_xcpt_ma_if; // @[lsu.scala:263:49] wire stq_incoming_e_0_bits_uop_xcpt_ae_if; // @[lsu.scala:263:49] wire stq_incoming_e_0_bits_uop_xcpt_pf_if; // @[lsu.scala:263:49] wire stq_incoming_e_0_bits_uop_fp_single; // @[lsu.scala:263:49] wire stq_incoming_e_0_bits_uop_fp_val; // @[lsu.scala:263:49] wire stq_incoming_e_0_bits_uop_frs3_en; // @[lsu.scala:263:49] wire [1:0] stq_incoming_e_0_bits_uop_lrs2_rtype; // @[lsu.scala:263:49] wire [1:0] stq_incoming_e_0_bits_uop_lrs1_rtype; // @[lsu.scala:263:49] wire [1:0] stq_incoming_e_0_bits_uop_dst_rtype; // @[lsu.scala:263:49] wire stq_incoming_e_0_bits_uop_ldst_val; // @[lsu.scala:263:49] wire [5:0] stq_incoming_e_0_bits_uop_lrs3; // @[lsu.scala:263:49] wire [5:0] stq_incoming_e_0_bits_uop_lrs2; // @[lsu.scala:263:49] wire [5:0] stq_incoming_e_0_bits_uop_lrs1; // @[lsu.scala:263:49] wire [5:0] stq_incoming_e_0_bits_uop_ldst; // @[lsu.scala:263:49] wire stq_incoming_e_0_bits_uop_ldst_is_rs1; // @[lsu.scala:263:49] wire stq_incoming_e_0_bits_uop_flush_on_commit; // @[lsu.scala:263:49] wire stq_incoming_e_0_bits_uop_is_unique; // @[lsu.scala:263:49] wire stq_incoming_e_0_bits_uop_is_sys_pc2epc; // @[lsu.scala:263:49] wire stq_incoming_e_0_bits_uop_uses_stq; // @[lsu.scala:263:49] wire stq_incoming_e_0_bits_uop_uses_ldq; // @[lsu.scala:263:49] wire stq_incoming_e_0_bits_uop_is_amo; // @[lsu.scala:263:49] wire stq_incoming_e_0_bits_uop_is_fencei; // @[lsu.scala:263:49] wire stq_incoming_e_0_bits_uop_is_fence; // @[lsu.scala:263:49] wire stq_incoming_e_0_bits_uop_mem_signed; // @[lsu.scala:263:49] wire [1:0] stq_incoming_e_0_bits_uop_mem_size; // @[lsu.scala:263:49] wire [4:0] stq_incoming_e_0_bits_uop_mem_cmd; // @[lsu.scala:263:49] wire stq_incoming_e_0_bits_uop_bypassable; // @[lsu.scala:263:49] wire [63:0] stq_incoming_e_0_bits_uop_exc_cause; // @[lsu.scala:263:49] wire stq_incoming_e_0_bits_uop_exception; // @[lsu.scala:263:49] wire [5:0] stq_incoming_e_0_bits_uop_stale_pdst; // @[lsu.scala:263:49] wire stq_incoming_e_0_bits_uop_ppred_busy; // @[lsu.scala:263:49] wire stq_incoming_e_0_bits_uop_prs3_busy; // @[lsu.scala:263:49] wire stq_incoming_e_0_bits_uop_prs2_busy; // @[lsu.scala:263:49] wire stq_incoming_e_0_bits_uop_prs1_busy; // @[lsu.scala:263:49] wire [3:0] stq_incoming_e_0_bits_uop_ppred; // @[lsu.scala:263:49] wire [5:0] stq_incoming_e_0_bits_uop_prs3; // @[lsu.scala:263:49] wire [5:0] stq_incoming_e_0_bits_uop_prs2; // @[lsu.scala:263:49] wire [5:0] stq_incoming_e_0_bits_uop_prs1; // @[lsu.scala:263:49] wire [5:0] stq_incoming_e_0_bits_uop_pdst; // @[lsu.scala:263:49] wire [1:0] stq_incoming_e_0_bits_uop_rxq_idx; // @[lsu.scala:263:49] wire [2:0] stq_incoming_e_0_bits_uop_stq_idx; // @[lsu.scala:263:49] wire [2:0] stq_incoming_e_0_bits_uop_ldq_idx; // @[lsu.scala:263:49] wire [4:0] stq_incoming_e_0_bits_uop_rob_idx; // @[lsu.scala:263:49] wire [11:0] stq_incoming_e_0_bits_uop_csr_addr; // @[lsu.scala:263:49] wire [19:0] stq_incoming_e_0_bits_uop_imm_packed; // @[lsu.scala:263:49] wire stq_incoming_e_0_bits_uop_taken; // @[lsu.scala:263:49] wire [5:0] stq_incoming_e_0_bits_uop_pc_lob; // @[lsu.scala:263:49] wire stq_incoming_e_0_bits_uop_edge_inst; // @[lsu.scala:263:49] wire [3:0] stq_incoming_e_0_bits_uop_ftq_idx; // @[lsu.scala:263:49] wire [2:0] stq_incoming_e_0_bits_uop_br_tag; // @[lsu.scala:263:49] wire stq_incoming_e_0_bits_uop_is_sfb; // @[lsu.scala:263:49] wire stq_incoming_e_0_bits_uop_is_jal; // @[lsu.scala:263:49] wire stq_incoming_e_0_bits_uop_is_jalr; // @[lsu.scala:263:49] wire stq_incoming_e_0_bits_uop_is_br; // @[lsu.scala:263:49] wire stq_incoming_e_0_bits_uop_iw_p2_poisoned; // @[lsu.scala:263:49] wire stq_incoming_e_0_bits_uop_iw_p1_poisoned; // @[lsu.scala:263:49] wire [1:0] stq_incoming_e_0_bits_uop_iw_state; // @[lsu.scala:263:49] wire [9:0] stq_incoming_e_0_bits_uop_fu_code; // @[lsu.scala:263:49] wire [2:0] stq_incoming_e_0_bits_uop_iq_type; // @[lsu.scala:263:49] wire [39:0] stq_incoming_e_0_bits_uop_debug_pc; // @[lsu.scala:263:49] wire stq_incoming_e_0_bits_uop_is_rvc; // @[lsu.scala:263:49] wire [31:0] stq_incoming_e_0_bits_uop_debug_inst; // @[lsu.scala:263:49] wire [31:0] stq_incoming_e_0_bits_uop_inst; // @[lsu.scala:263:49] wire [6:0] stq_incoming_e_0_bits_uop_uopc; // @[lsu.scala:263:49] wire stq_incoming_e_0_bits_uop_ctrl_is_std; // @[lsu.scala:263:49] wire stq_incoming_e_0_bits_uop_ctrl_is_sta; // @[lsu.scala:263:49] wire stq_incoming_e_0_bits_uop_ctrl_is_load; // @[lsu.scala:263:49] wire [2:0] stq_incoming_e_0_bits_uop_ctrl_csr_cmd; // @[lsu.scala:263:49] wire stq_incoming_e_0_bits_uop_ctrl_fcn_dw; // @[lsu.scala:263:49] wire [4:0] stq_incoming_e_0_bits_uop_ctrl_op_fcn; // @[lsu.scala:263:49] wire [2:0] stq_incoming_e_0_bits_uop_ctrl_imm_sel; // @[lsu.scala:263:49] wire [2:0] stq_incoming_e_0_bits_uop_ctrl_op2_sel; // @[lsu.scala:263:49] wire [1:0] stq_incoming_e_0_bits_uop_ctrl_op1_sel; // @[lsu.scala:263:49] wire [3:0] stq_incoming_e_0_bits_uop_ctrl_br_type; // @[lsu.scala:263:49] wire [63:0] ldq_incoming_e_0_bits_debug_wb_data; // @[lsu.scala:263:49] wire [2:0] ldq_incoming_e_0_bits_forward_stq_idx; // @[lsu.scala:263:49] wire ldq_incoming_e_0_bits_forward_std_val; // @[lsu.scala:263:49] wire [2:0] ldq_incoming_e_0_bits_youngest_stq_idx; // @[lsu.scala:263:49] wire [7:0] ldq_incoming_e_0_bits_st_dep_mask; // @[lsu.scala:263:49] wire ldq_incoming_e_0_bits_observed; // @[lsu.scala:263:49] wire ldq_incoming_e_0_bits_order_fail; // @[lsu.scala:263:49] wire ldq_incoming_e_0_bits_succeeded; // @[lsu.scala:263:49] wire ldq_incoming_e_0_bits_executed; // @[lsu.scala:263:49] wire ldq_incoming_e_0_bits_addr_is_uncacheable; // @[lsu.scala:263:49] wire ldq_incoming_e_0_bits_addr_is_virtual; // @[lsu.scala:263:49] wire [39:0] ldq_incoming_e_0_bits_addr_bits; // @[lsu.scala:263:49] wire ldq_incoming_e_0_bits_addr_valid; // @[lsu.scala:263:49] wire [1:0] ldq_incoming_e_0_bits_uop_debug_tsrc; // @[lsu.scala:263:49] wire [1:0] ldq_incoming_e_0_bits_uop_debug_fsrc; // @[lsu.scala:263:49] wire ldq_incoming_e_0_bits_uop_bp_xcpt_if; // @[lsu.scala:263:49] wire ldq_incoming_e_0_bits_uop_bp_debug_if; // @[lsu.scala:263:49] wire ldq_incoming_e_0_bits_uop_xcpt_ma_if; // @[lsu.scala:263:49] wire ldq_incoming_e_0_bits_uop_xcpt_ae_if; // @[lsu.scala:263:49] wire ldq_incoming_e_0_bits_uop_xcpt_pf_if; // @[lsu.scala:263:49] wire ldq_incoming_e_0_bits_uop_fp_single; // @[lsu.scala:263:49] wire ldq_incoming_e_0_bits_uop_fp_val; // @[lsu.scala:263:49] wire ldq_incoming_e_0_bits_uop_frs3_en; // @[lsu.scala:263:49] wire [1:0] ldq_incoming_e_0_bits_uop_lrs2_rtype; // @[lsu.scala:263:49] wire [1:0] ldq_incoming_e_0_bits_uop_lrs1_rtype; // @[lsu.scala:263:49] wire [1:0] ldq_incoming_e_0_bits_uop_dst_rtype; // @[lsu.scala:263:49] wire ldq_incoming_e_0_bits_uop_ldst_val; // @[lsu.scala:263:49] wire [5:0] ldq_incoming_e_0_bits_uop_lrs3; // @[lsu.scala:263:49] wire [5:0] ldq_incoming_e_0_bits_uop_lrs2; // @[lsu.scala:263:49] wire [5:0] ldq_incoming_e_0_bits_uop_lrs1; // @[lsu.scala:263:49] wire [5:0] ldq_incoming_e_0_bits_uop_ldst; // @[lsu.scala:263:49] wire ldq_incoming_e_0_bits_uop_ldst_is_rs1; // @[lsu.scala:263:49] wire ldq_incoming_e_0_bits_uop_flush_on_commit; // @[lsu.scala:263:49] wire ldq_incoming_e_0_bits_uop_is_unique; // @[lsu.scala:263:49] wire ldq_incoming_e_0_bits_uop_is_sys_pc2epc; // @[lsu.scala:263:49] wire ldq_incoming_e_0_bits_uop_uses_stq; // @[lsu.scala:263:49] wire ldq_incoming_e_0_bits_uop_uses_ldq; // @[lsu.scala:263:49] wire ldq_incoming_e_0_bits_uop_is_amo; // @[lsu.scala:263:49] wire ldq_incoming_e_0_bits_uop_is_fencei; // @[lsu.scala:263:49] wire ldq_incoming_e_0_bits_uop_is_fence; // @[lsu.scala:263:49] wire ldq_incoming_e_0_bits_uop_mem_signed; // @[lsu.scala:263:49] wire [1:0] ldq_incoming_e_0_bits_uop_mem_size; // @[lsu.scala:263:49] wire [4:0] ldq_incoming_e_0_bits_uop_mem_cmd; // @[lsu.scala:263:49] wire ldq_incoming_e_0_bits_uop_bypassable; // @[lsu.scala:263:49] wire [63:0] ldq_incoming_e_0_bits_uop_exc_cause; // @[lsu.scala:263:49] wire ldq_incoming_e_0_bits_uop_exception; // @[lsu.scala:263:49] wire [5:0] ldq_incoming_e_0_bits_uop_stale_pdst; // @[lsu.scala:263:49] wire ldq_incoming_e_0_bits_uop_prs3_busy; // @[lsu.scala:263:49] wire ldq_incoming_e_0_bits_uop_prs2_busy; // @[lsu.scala:263:49] wire ldq_incoming_e_0_bits_uop_prs1_busy; // @[lsu.scala:263:49] wire [5:0] ldq_incoming_e_0_bits_uop_prs3; // @[lsu.scala:263:49] wire [5:0] ldq_incoming_e_0_bits_uop_prs2; // @[lsu.scala:263:49] wire [5:0] ldq_incoming_e_0_bits_uop_prs1; // @[lsu.scala:263:49] wire [5:0] ldq_incoming_e_0_bits_uop_pdst; // @[lsu.scala:263:49] wire [1:0] ldq_incoming_e_0_bits_uop_rxq_idx; // @[lsu.scala:263:49] wire [2:0] ldq_incoming_e_0_bits_uop_stq_idx; // @[lsu.scala:263:49] wire [2:0] ldq_incoming_e_0_bits_uop_ldq_idx; // @[lsu.scala:263:49] wire [4:0] ldq_incoming_e_0_bits_uop_rob_idx; // @[lsu.scala:263:49] wire [11:0] ldq_incoming_e_0_bits_uop_csr_addr; // @[lsu.scala:263:49] wire [19:0] ldq_incoming_e_0_bits_uop_imm_packed; // @[lsu.scala:263:49] wire ldq_incoming_e_0_bits_uop_taken; // @[lsu.scala:263:49] wire [5:0] ldq_incoming_e_0_bits_uop_pc_lob; // @[lsu.scala:263:49] wire ldq_incoming_e_0_bits_uop_edge_inst; // @[lsu.scala:263:49] wire [3:0] ldq_incoming_e_0_bits_uop_ftq_idx; // @[lsu.scala:263:49] wire [2:0] ldq_incoming_e_0_bits_uop_br_tag; // @[lsu.scala:263:49] wire ldq_incoming_e_0_bits_uop_is_sfb; // @[lsu.scala:263:49] wire ldq_incoming_e_0_bits_uop_is_jal; // @[lsu.scala:263:49] wire ldq_incoming_e_0_bits_uop_is_jalr; // @[lsu.scala:263:49] wire ldq_incoming_e_0_bits_uop_is_br; // @[lsu.scala:263:49] wire ldq_incoming_e_0_bits_uop_iw_p2_poisoned; // @[lsu.scala:263:49] wire ldq_incoming_e_0_bits_uop_iw_p1_poisoned; // @[lsu.scala:263:49] wire [1:0] ldq_incoming_e_0_bits_uop_iw_state; // @[lsu.scala:263:49] wire [9:0] ldq_incoming_e_0_bits_uop_fu_code; // @[lsu.scala:263:49] wire [2:0] ldq_incoming_e_0_bits_uop_iq_type; // @[lsu.scala:263:49] wire [39:0] ldq_incoming_e_0_bits_uop_debug_pc; // @[lsu.scala:263:49] wire ldq_incoming_e_0_bits_uop_is_rvc; // @[lsu.scala:263:49] wire [31:0] ldq_incoming_e_0_bits_uop_debug_inst; // @[lsu.scala:263:49] wire [31:0] ldq_incoming_e_0_bits_uop_inst; // @[lsu.scala:263:49] wire [6:0] ldq_incoming_e_0_bits_uop_uopc; // @[lsu.scala:263:49] wire ldq_incoming_e_0_bits_uop_ctrl_is_std; // @[lsu.scala:263:49] wire ldq_incoming_e_0_bits_uop_ctrl_is_sta; // @[lsu.scala:263:49] wire ldq_incoming_e_0_bits_uop_ctrl_is_load; // @[lsu.scala:263:49] wire [2:0] ldq_incoming_e_0_bits_uop_ctrl_csr_cmd; // @[lsu.scala:263:49] wire ldq_incoming_e_0_bits_uop_ctrl_fcn_dw; // @[lsu.scala:263:49] wire [4:0] ldq_incoming_e_0_bits_uop_ctrl_op_fcn; // @[lsu.scala:263:49] wire [2:0] ldq_incoming_e_0_bits_uop_ctrl_imm_sel; // @[lsu.scala:263:49] wire [2:0] ldq_incoming_e_0_bits_uop_ctrl_op2_sel; // @[lsu.scala:263:49] wire [1:0] ldq_incoming_e_0_bits_uop_ctrl_op1_sel; // @[lsu.scala:263:49] wire [3:0] ldq_incoming_e_0_bits_uop_ctrl_br_type; // @[lsu.scala:263:49] wire [1:0] exe_req_0_bits_uop_debug_tsrc; // @[lsu.scala:383:25] wire [1:0] exe_req_0_bits_uop_debug_fsrc; // @[lsu.scala:383:25] wire exe_req_0_bits_uop_bp_xcpt_if; // @[lsu.scala:383:25] wire exe_req_0_bits_uop_bp_debug_if; // @[lsu.scala:383:25] wire exe_req_0_bits_uop_xcpt_ma_if; // @[lsu.scala:383:25] wire exe_req_0_bits_uop_xcpt_ae_if; // @[lsu.scala:383:25] wire exe_req_0_bits_uop_xcpt_pf_if; // @[lsu.scala:383:25] wire exe_req_0_bits_uop_fp_single; // @[lsu.scala:383:25] wire exe_req_0_bits_uop_fp_val; // @[lsu.scala:383:25] wire exe_req_0_bits_uop_frs3_en; // @[lsu.scala:383:25] wire [1:0] exe_req_0_bits_uop_lrs2_rtype; // @[lsu.scala:383:25] wire [1:0] exe_req_0_bits_uop_lrs1_rtype; // @[lsu.scala:383:25] wire [1:0] exe_req_0_bits_uop_dst_rtype; // @[lsu.scala:383:25] wire exe_req_0_bits_uop_ldst_val; // @[lsu.scala:383:25] wire [5:0] exe_req_0_bits_uop_lrs3; // @[lsu.scala:383:25] wire [5:0] exe_req_0_bits_uop_lrs2; // @[lsu.scala:383:25] wire [5:0] exe_req_0_bits_uop_lrs1; // @[lsu.scala:383:25] wire [5:0] exe_req_0_bits_uop_ldst; // @[lsu.scala:383:25] wire exe_req_0_bits_uop_ldst_is_rs1; // @[lsu.scala:383:25] wire exe_req_0_bits_uop_flush_on_commit; // @[lsu.scala:383:25] wire exe_req_0_bits_uop_is_unique; // @[lsu.scala:383:25] wire exe_req_0_bits_uop_is_sys_pc2epc; // @[lsu.scala:383:25] wire exe_req_0_bits_uop_uses_stq; // @[lsu.scala:383:25] wire exe_req_0_bits_uop_uses_ldq; // @[lsu.scala:383:25] wire exe_req_0_bits_uop_is_amo; // @[lsu.scala:383:25] wire exe_req_0_bits_uop_is_fencei; // @[lsu.scala:383:25] wire exe_req_0_bits_uop_is_fence; // @[lsu.scala:383:25] wire exe_req_0_bits_uop_mem_signed; // @[lsu.scala:383:25] wire [1:0] exe_req_0_bits_uop_mem_size; // @[lsu.scala:383:25] wire [4:0] exe_req_0_bits_uop_mem_cmd; // @[lsu.scala:383:25] wire exe_req_0_bits_uop_bypassable; // @[lsu.scala:383:25] wire [63:0] exe_req_0_bits_uop_exc_cause; // @[lsu.scala:383:25] wire exe_req_0_bits_uop_exception; // @[lsu.scala:383:25] wire [5:0] exe_req_0_bits_uop_stale_pdst; // @[lsu.scala:383:25] wire exe_req_0_bits_uop_ppred_busy; // @[lsu.scala:383:25] wire exe_req_0_bits_uop_prs3_busy; // @[lsu.scala:383:25] wire exe_req_0_bits_uop_prs2_busy; // @[lsu.scala:383:25] wire exe_req_0_bits_uop_prs1_busy; // @[lsu.scala:383:25] wire [3:0] exe_req_0_bits_uop_ppred; // @[lsu.scala:383:25] wire [5:0] exe_req_0_bits_uop_prs3; // @[lsu.scala:383:25] wire [5:0] exe_req_0_bits_uop_prs2; // @[lsu.scala:383:25] wire [5:0] exe_req_0_bits_uop_prs1; // @[lsu.scala:383:25] wire [5:0] exe_req_0_bits_uop_pdst; // @[lsu.scala:383:25] wire [1:0] exe_req_0_bits_uop_rxq_idx; // @[lsu.scala:383:25] wire [2:0] exe_req_0_bits_uop_stq_idx; // @[lsu.scala:383:25] wire [2:0] exe_req_0_bits_uop_ldq_idx; // @[lsu.scala:383:25] wire [4:0] exe_req_0_bits_uop_rob_idx; // @[lsu.scala:383:25] wire [11:0] exe_req_0_bits_uop_csr_addr; // @[lsu.scala:383:25] wire [19:0] exe_req_0_bits_uop_imm_packed; // @[lsu.scala:383:25] wire exe_req_0_bits_uop_taken; // @[lsu.scala:383:25] wire [5:0] exe_req_0_bits_uop_pc_lob; // @[lsu.scala:383:25] wire exe_req_0_bits_uop_edge_inst; // @[lsu.scala:383:25] wire [3:0] exe_req_0_bits_uop_ftq_idx; // @[lsu.scala:383:25] wire [2:0] exe_req_0_bits_uop_br_tag; // @[lsu.scala:383:25] wire exe_req_0_bits_uop_is_sfb; // @[lsu.scala:383:25] wire exe_req_0_bits_uop_is_jal; // @[lsu.scala:383:25] wire exe_req_0_bits_uop_is_jalr; // @[lsu.scala:383:25] wire exe_req_0_bits_uop_is_br; // @[lsu.scala:383:25] wire exe_req_0_bits_uop_iw_p2_poisoned; // @[lsu.scala:383:25] wire exe_req_0_bits_uop_iw_p1_poisoned; // @[lsu.scala:383:25] wire [1:0] exe_req_0_bits_uop_iw_state; // @[lsu.scala:383:25] wire [9:0] exe_req_0_bits_uop_fu_code; // @[lsu.scala:383:25] wire [2:0] exe_req_0_bits_uop_iq_type; // @[lsu.scala:383:25] wire [39:0] exe_req_0_bits_uop_debug_pc; // @[lsu.scala:383:25] wire exe_req_0_bits_uop_is_rvc; // @[lsu.scala:383:25] wire [31:0] exe_req_0_bits_uop_debug_inst; // @[lsu.scala:383:25] wire [31:0] exe_req_0_bits_uop_inst; // @[lsu.scala:383:25] wire [6:0] exe_req_0_bits_uop_uopc; // @[lsu.scala:383:25] wire exe_req_0_bits_uop_ctrl_is_std; // @[lsu.scala:383:25] wire exe_req_0_bits_uop_ctrl_is_sta; // @[lsu.scala:383:25] wire exe_req_0_bits_uop_ctrl_is_load; // @[lsu.scala:383:25] wire [2:0] exe_req_0_bits_uop_ctrl_csr_cmd; // @[lsu.scala:383:25] wire exe_req_0_bits_uop_ctrl_fcn_dw; // @[lsu.scala:383:25] wire [4:0] exe_req_0_bits_uop_ctrl_op_fcn; // @[lsu.scala:383:25] wire [2:0] exe_req_0_bits_uop_ctrl_imm_sel; // @[lsu.scala:383:25] wire [2:0] exe_req_0_bits_uop_ctrl_op2_sel; // @[lsu.scala:383:25] wire [1:0] exe_req_0_bits_uop_ctrl_op1_sel; // @[lsu.scala:383:25] wire [3:0] exe_req_0_bits_uop_ctrl_br_type; // @[lsu.scala:383:25] wire _dtlb_io_miss_rdy; // @[lsu.scala:247:20] wire [31:0] _dtlb_io_resp_0_paddr; // @[lsu.scala:247:20] wire _dtlb_io_resp_0_pf_ld; // @[lsu.scala:247:20] wire _dtlb_io_resp_0_pf_st; // @[lsu.scala:247:20] wire _dtlb_io_resp_0_ae_ld; // @[lsu.scala:247:20] wire _dtlb_io_resp_0_ae_st; // @[lsu.scala:247:20] wire _dtlb_io_resp_0_ma_ld; // @[lsu.scala:247:20] wire _dtlb_io_resp_0_ma_st; // @[lsu.scala:247:20] wire _dtlb_io_resp_0_cacheable; // @[lsu.scala:247:20] wire io_ptw_req_ready_0 = io_ptw_req_ready; // @[lsu.scala:201:7] wire io_ptw_resp_valid_0 = io_ptw_resp_valid; // @[lsu.scala:201:7] wire io_ptw_resp_bits_ae_ptw_0 = io_ptw_resp_bits_ae_ptw; // @[lsu.scala:201:7] wire io_ptw_resp_bits_ae_final_0 = io_ptw_resp_bits_ae_final; // @[lsu.scala:201:7] wire io_ptw_resp_bits_pf_0 = io_ptw_resp_bits_pf; // @[lsu.scala:201:7] wire io_ptw_resp_bits_gf_0 = io_ptw_resp_bits_gf; // @[lsu.scala:201:7] wire io_ptw_resp_bits_hr_0 = io_ptw_resp_bits_hr; // @[lsu.scala:201:7] wire io_ptw_resp_bits_hw_0 = io_ptw_resp_bits_hw; // @[lsu.scala:201:7] wire io_ptw_resp_bits_hx_0 = io_ptw_resp_bits_hx; // @[lsu.scala:201:7] wire [9:0] io_ptw_resp_bits_pte_reserved_for_future_0 = io_ptw_resp_bits_pte_reserved_for_future; // @[lsu.scala:201:7] wire [43:0] io_ptw_resp_bits_pte_ppn_0 = io_ptw_resp_bits_pte_ppn; // @[lsu.scala:201:7] wire [1:0] io_ptw_resp_bits_pte_reserved_for_software_0 = io_ptw_resp_bits_pte_reserved_for_software; // @[lsu.scala:201:7] wire io_ptw_resp_bits_pte_d_0 = io_ptw_resp_bits_pte_d; // @[lsu.scala:201:7] wire io_ptw_resp_bits_pte_a_0 = io_ptw_resp_bits_pte_a; // @[lsu.scala:201:7] wire io_ptw_resp_bits_pte_g_0 = io_ptw_resp_bits_pte_g; // @[lsu.scala:201:7] wire io_ptw_resp_bits_pte_u_0 = io_ptw_resp_bits_pte_u; // @[lsu.scala:201:7] wire io_ptw_resp_bits_pte_x_0 = io_ptw_resp_bits_pte_x; // @[lsu.scala:201:7] wire io_ptw_resp_bits_pte_w_0 = io_ptw_resp_bits_pte_w; // @[lsu.scala:201:7] wire io_ptw_resp_bits_pte_r_0 = io_ptw_resp_bits_pte_r; // @[lsu.scala:201:7] wire io_ptw_resp_bits_pte_v_0 = io_ptw_resp_bits_pte_v; // @[lsu.scala:201:7] wire [1:0] io_ptw_resp_bits_level_0 = io_ptw_resp_bits_level; // @[lsu.scala:201:7] wire io_ptw_resp_bits_homogeneous_0 = io_ptw_resp_bits_homogeneous; // @[lsu.scala:201:7] wire io_ptw_resp_bits_gpa_valid_0 = io_ptw_resp_bits_gpa_valid; // @[lsu.scala:201:7] wire [38:0] io_ptw_resp_bits_gpa_bits_0 = io_ptw_resp_bits_gpa_bits; // @[lsu.scala:201:7] wire io_ptw_resp_bits_gpa_is_pte_0 = io_ptw_resp_bits_gpa_is_pte; // @[lsu.scala:201:7] wire [3:0] io_ptw_ptbr_mode_0 = io_ptw_ptbr_mode; // @[lsu.scala:201:7] wire [43:0] io_ptw_ptbr_ppn_0 = io_ptw_ptbr_ppn; // @[lsu.scala:201:7] wire io_ptw_status_debug_0 = io_ptw_status_debug; // @[lsu.scala:201:7] wire io_ptw_status_cease_0 = io_ptw_status_cease; // @[lsu.scala:201:7] wire io_ptw_status_wfi_0 = io_ptw_status_wfi; // @[lsu.scala:201:7] wire [1:0] io_ptw_status_dprv_0 = io_ptw_status_dprv; // @[lsu.scala:201:7] wire io_ptw_status_dv_0 = io_ptw_status_dv; // @[lsu.scala:201:7] wire [1:0] io_ptw_status_prv_0 = io_ptw_status_prv; // @[lsu.scala:201:7] wire io_ptw_status_v_0 = io_ptw_status_v; // @[lsu.scala:201:7] wire io_ptw_status_sd_0 = io_ptw_status_sd; // @[lsu.scala:201:7] wire io_ptw_status_mpv_0 = io_ptw_status_mpv; // @[lsu.scala:201:7] wire io_ptw_status_gva_0 = io_ptw_status_gva; // @[lsu.scala:201:7] wire io_ptw_status_tsr_0 = io_ptw_status_tsr; // @[lsu.scala:201:7] wire io_ptw_status_tw_0 = io_ptw_status_tw; // @[lsu.scala:201:7] wire io_ptw_status_tvm_0 = io_ptw_status_tvm; // @[lsu.scala:201:7] wire io_ptw_status_mxr_0 = io_ptw_status_mxr; // @[lsu.scala:201:7] wire io_ptw_status_sum_0 = io_ptw_status_sum; // @[lsu.scala:201:7] wire io_ptw_status_mprv_0 = io_ptw_status_mprv; // @[lsu.scala:201:7] wire [1:0] io_ptw_status_fs_0 = io_ptw_status_fs; // @[lsu.scala:201:7] wire [1:0] io_ptw_status_mpp_0 = io_ptw_status_mpp; // @[lsu.scala:201:7] wire io_ptw_status_spp_0 = io_ptw_status_spp; // @[lsu.scala:201:7] wire io_ptw_status_mpie_0 = io_ptw_status_mpie; // @[lsu.scala:201:7] wire io_ptw_status_spie_0 = io_ptw_status_spie; // @[lsu.scala:201:7] wire io_ptw_status_mie_0 = io_ptw_status_mie; // @[lsu.scala:201:7] wire io_ptw_status_sie_0 = io_ptw_status_sie; // @[lsu.scala:201:7] wire io_ptw_pmp_0_cfg_l_0 = io_ptw_pmp_0_cfg_l; // @[lsu.scala:201:7] wire [1:0] io_ptw_pmp_0_cfg_a_0 = io_ptw_pmp_0_cfg_a; // @[lsu.scala:201:7] wire io_ptw_pmp_0_cfg_x_0 = io_ptw_pmp_0_cfg_x; // @[lsu.scala:201:7] wire io_ptw_pmp_0_cfg_w_0 = io_ptw_pmp_0_cfg_w; // @[lsu.scala:201:7] wire io_ptw_pmp_0_cfg_r_0 = io_ptw_pmp_0_cfg_r; // @[lsu.scala:201:7] wire [29:0] io_ptw_pmp_0_addr_0 = io_ptw_pmp_0_addr; // @[lsu.scala:201:7] wire [31:0] io_ptw_pmp_0_mask_0 = io_ptw_pmp_0_mask; // @[lsu.scala:201:7] wire io_ptw_pmp_1_cfg_l_0 = io_ptw_pmp_1_cfg_l; // @[lsu.scala:201:7] wire [1:0] io_ptw_pmp_1_cfg_a_0 = io_ptw_pmp_1_cfg_a; // @[lsu.scala:201:7] wire io_ptw_pmp_1_cfg_x_0 = io_ptw_pmp_1_cfg_x; // @[lsu.scala:201:7] wire io_ptw_pmp_1_cfg_w_0 = io_ptw_pmp_1_cfg_w; // @[lsu.scala:201:7] wire io_ptw_pmp_1_cfg_r_0 = io_ptw_pmp_1_cfg_r; // @[lsu.scala:201:7] wire [29:0] io_ptw_pmp_1_addr_0 = io_ptw_pmp_1_addr; // @[lsu.scala:201:7] wire [31:0] io_ptw_pmp_1_mask_0 = io_ptw_pmp_1_mask; // @[lsu.scala:201:7] wire io_ptw_pmp_2_cfg_l_0 = io_ptw_pmp_2_cfg_l; // @[lsu.scala:201:7] wire [1:0] io_ptw_pmp_2_cfg_a_0 = io_ptw_pmp_2_cfg_a; // @[lsu.scala:201:7] wire io_ptw_pmp_2_cfg_x_0 = io_ptw_pmp_2_cfg_x; // @[lsu.scala:201:7] wire io_ptw_pmp_2_cfg_w_0 = io_ptw_pmp_2_cfg_w; // @[lsu.scala:201:7] wire io_ptw_pmp_2_cfg_r_0 = io_ptw_pmp_2_cfg_r; // @[lsu.scala:201:7] wire [29:0] io_ptw_pmp_2_addr_0 = io_ptw_pmp_2_addr; // @[lsu.scala:201:7] wire [31:0] io_ptw_pmp_2_mask_0 = io_ptw_pmp_2_mask; // @[lsu.scala:201:7] wire io_ptw_pmp_3_cfg_l_0 = io_ptw_pmp_3_cfg_l; // @[lsu.scala:201:7] wire [1:0] io_ptw_pmp_3_cfg_a_0 = io_ptw_pmp_3_cfg_a; // @[lsu.scala:201:7] wire io_ptw_pmp_3_cfg_x_0 = io_ptw_pmp_3_cfg_x; // @[lsu.scala:201:7] wire io_ptw_pmp_3_cfg_w_0 = io_ptw_pmp_3_cfg_w; // @[lsu.scala:201:7] wire io_ptw_pmp_3_cfg_r_0 = io_ptw_pmp_3_cfg_r; // @[lsu.scala:201:7] wire [29:0] io_ptw_pmp_3_addr_0 = io_ptw_pmp_3_addr; // @[lsu.scala:201:7] wire [31:0] io_ptw_pmp_3_mask_0 = io_ptw_pmp_3_mask; // @[lsu.scala:201:7] wire io_ptw_pmp_4_cfg_l_0 = io_ptw_pmp_4_cfg_l; // @[lsu.scala:201:7] wire [1:0] io_ptw_pmp_4_cfg_a_0 = io_ptw_pmp_4_cfg_a; // @[lsu.scala:201:7] wire io_ptw_pmp_4_cfg_x_0 = io_ptw_pmp_4_cfg_x; // @[lsu.scala:201:7] wire io_ptw_pmp_4_cfg_w_0 = io_ptw_pmp_4_cfg_w; // @[lsu.scala:201:7] wire io_ptw_pmp_4_cfg_r_0 = io_ptw_pmp_4_cfg_r; // @[lsu.scala:201:7] wire [29:0] io_ptw_pmp_4_addr_0 = io_ptw_pmp_4_addr; // @[lsu.scala:201:7] wire [31:0] io_ptw_pmp_4_mask_0 = io_ptw_pmp_4_mask; // @[lsu.scala:201:7] wire io_ptw_pmp_5_cfg_l_0 = io_ptw_pmp_5_cfg_l; // @[lsu.scala:201:7] wire [1:0] io_ptw_pmp_5_cfg_a_0 = io_ptw_pmp_5_cfg_a; // @[lsu.scala:201:7] wire io_ptw_pmp_5_cfg_x_0 = io_ptw_pmp_5_cfg_x; // @[lsu.scala:201:7] wire io_ptw_pmp_5_cfg_w_0 = io_ptw_pmp_5_cfg_w; // @[lsu.scala:201:7] wire io_ptw_pmp_5_cfg_r_0 = io_ptw_pmp_5_cfg_r; // @[lsu.scala:201:7] wire [29:0] io_ptw_pmp_5_addr_0 = io_ptw_pmp_5_addr; // @[lsu.scala:201:7] wire [31:0] io_ptw_pmp_5_mask_0 = io_ptw_pmp_5_mask; // @[lsu.scala:201:7] wire io_ptw_pmp_6_cfg_l_0 = io_ptw_pmp_6_cfg_l; // @[lsu.scala:201:7] wire [1:0] io_ptw_pmp_6_cfg_a_0 = io_ptw_pmp_6_cfg_a; // @[lsu.scala:201:7] wire io_ptw_pmp_6_cfg_x_0 = io_ptw_pmp_6_cfg_x; // @[lsu.scala:201:7] wire io_ptw_pmp_6_cfg_w_0 = io_ptw_pmp_6_cfg_w; // @[lsu.scala:201:7] wire io_ptw_pmp_6_cfg_r_0 = io_ptw_pmp_6_cfg_r; // @[lsu.scala:201:7] wire [29:0] io_ptw_pmp_6_addr_0 = io_ptw_pmp_6_addr; // @[lsu.scala:201:7] wire [31:0] io_ptw_pmp_6_mask_0 = io_ptw_pmp_6_mask; // @[lsu.scala:201:7] wire io_ptw_pmp_7_cfg_l_0 = io_ptw_pmp_7_cfg_l; // @[lsu.scala:201:7] wire [1:0] io_ptw_pmp_7_cfg_a_0 = io_ptw_pmp_7_cfg_a; // @[lsu.scala:201:7] wire io_ptw_pmp_7_cfg_x_0 = io_ptw_pmp_7_cfg_x; // @[lsu.scala:201:7] wire io_ptw_pmp_7_cfg_w_0 = io_ptw_pmp_7_cfg_w; // @[lsu.scala:201:7] wire io_ptw_pmp_7_cfg_r_0 = io_ptw_pmp_7_cfg_r; // @[lsu.scala:201:7] wire [29:0] io_ptw_pmp_7_addr_0 = io_ptw_pmp_7_addr; // @[lsu.scala:201:7] wire [31:0] io_ptw_pmp_7_mask_0 = io_ptw_pmp_7_mask; // @[lsu.scala:201:7] wire io_core_exe_0_req_valid_0 = io_core_exe_0_req_valid; // @[lsu.scala:201:7] wire [6:0] io_core_exe_0_req_bits_uop_uopc_0 = io_core_exe_0_req_bits_uop_uopc; // @[lsu.scala:201:7] wire [31:0] io_core_exe_0_req_bits_uop_inst_0 = io_core_exe_0_req_bits_uop_inst; // @[lsu.scala:201:7] wire [31:0] io_core_exe_0_req_bits_uop_debug_inst_0 = io_core_exe_0_req_bits_uop_debug_inst; // @[lsu.scala:201:7] wire io_core_exe_0_req_bits_uop_is_rvc_0 = io_core_exe_0_req_bits_uop_is_rvc; // @[lsu.scala:201:7] wire [39:0] io_core_exe_0_req_bits_uop_debug_pc_0 = io_core_exe_0_req_bits_uop_debug_pc; // @[lsu.scala:201:7] wire [2:0] io_core_exe_0_req_bits_uop_iq_type_0 = io_core_exe_0_req_bits_uop_iq_type; // @[lsu.scala:201:7] wire [9:0] io_core_exe_0_req_bits_uop_fu_code_0 = io_core_exe_0_req_bits_uop_fu_code; // @[lsu.scala:201:7] wire [3:0] io_core_exe_0_req_bits_uop_ctrl_br_type_0 = io_core_exe_0_req_bits_uop_ctrl_br_type; // @[lsu.scala:201:7] wire [1:0] io_core_exe_0_req_bits_uop_ctrl_op1_sel_0 = io_core_exe_0_req_bits_uop_ctrl_op1_sel; // @[lsu.scala:201:7] wire [2:0] io_core_exe_0_req_bits_uop_ctrl_op2_sel_0 = io_core_exe_0_req_bits_uop_ctrl_op2_sel; // @[lsu.scala:201:7] wire [2:0] io_core_exe_0_req_bits_uop_ctrl_imm_sel_0 = io_core_exe_0_req_bits_uop_ctrl_imm_sel; // @[lsu.scala:201:7] wire [4:0] io_core_exe_0_req_bits_uop_ctrl_op_fcn_0 = io_core_exe_0_req_bits_uop_ctrl_op_fcn; // @[lsu.scala:201:7] wire io_core_exe_0_req_bits_uop_ctrl_fcn_dw_0 = io_core_exe_0_req_bits_uop_ctrl_fcn_dw; // @[lsu.scala:201:7] wire [2:0] io_core_exe_0_req_bits_uop_ctrl_csr_cmd_0 = io_core_exe_0_req_bits_uop_ctrl_csr_cmd; // @[lsu.scala:201:7] wire io_core_exe_0_req_bits_uop_ctrl_is_load_0 = io_core_exe_0_req_bits_uop_ctrl_is_load; // @[lsu.scala:201:7] wire io_core_exe_0_req_bits_uop_ctrl_is_sta_0 = io_core_exe_0_req_bits_uop_ctrl_is_sta; // @[lsu.scala:201:7] wire io_core_exe_0_req_bits_uop_ctrl_is_std_0 = io_core_exe_0_req_bits_uop_ctrl_is_std; // @[lsu.scala:201:7] wire [1:0] io_core_exe_0_req_bits_uop_iw_state_0 = io_core_exe_0_req_bits_uop_iw_state; // @[lsu.scala:201:7] wire io_core_exe_0_req_bits_uop_iw_p1_poisoned_0 = io_core_exe_0_req_bits_uop_iw_p1_poisoned; // @[lsu.scala:201:7] wire io_core_exe_0_req_bits_uop_iw_p2_poisoned_0 = io_core_exe_0_req_bits_uop_iw_p2_poisoned; // @[lsu.scala:201:7] wire io_core_exe_0_req_bits_uop_is_br_0 = io_core_exe_0_req_bits_uop_is_br; // @[lsu.scala:201:7] wire io_core_exe_0_req_bits_uop_is_jalr_0 = io_core_exe_0_req_bits_uop_is_jalr; // @[lsu.scala:201:7] wire io_core_exe_0_req_bits_uop_is_jal_0 = io_core_exe_0_req_bits_uop_is_jal; // @[lsu.scala:201:7] wire io_core_exe_0_req_bits_uop_is_sfb_0 = io_core_exe_0_req_bits_uop_is_sfb; // @[lsu.scala:201:7] wire [7:0] io_core_exe_0_req_bits_uop_br_mask_0 = io_core_exe_0_req_bits_uop_br_mask; // @[lsu.scala:201:7] wire [2:0] io_core_exe_0_req_bits_uop_br_tag_0 = io_core_exe_0_req_bits_uop_br_tag; // @[lsu.scala:201:7] wire [3:0] io_core_exe_0_req_bits_uop_ftq_idx_0 = io_core_exe_0_req_bits_uop_ftq_idx; // @[lsu.scala:201:7] wire io_core_exe_0_req_bits_uop_edge_inst_0 = io_core_exe_0_req_bits_uop_edge_inst; // @[lsu.scala:201:7] wire [5:0] io_core_exe_0_req_bits_uop_pc_lob_0 = io_core_exe_0_req_bits_uop_pc_lob; // @[lsu.scala:201:7] wire io_core_exe_0_req_bits_uop_taken_0 = io_core_exe_0_req_bits_uop_taken; // @[lsu.scala:201:7] wire [19:0] io_core_exe_0_req_bits_uop_imm_packed_0 = io_core_exe_0_req_bits_uop_imm_packed; // @[lsu.scala:201:7] wire [11:0] io_core_exe_0_req_bits_uop_csr_addr_0 = io_core_exe_0_req_bits_uop_csr_addr; // @[lsu.scala:201:7] wire [4:0] io_core_exe_0_req_bits_uop_rob_idx_0 = io_core_exe_0_req_bits_uop_rob_idx; // @[lsu.scala:201:7] wire [2:0] io_core_exe_0_req_bits_uop_ldq_idx_0 = io_core_exe_0_req_bits_uop_ldq_idx; // @[lsu.scala:201:7] wire [2:0] io_core_exe_0_req_bits_uop_stq_idx_0 = io_core_exe_0_req_bits_uop_stq_idx; // @[lsu.scala:201:7] wire [1:0] io_core_exe_0_req_bits_uop_rxq_idx_0 = io_core_exe_0_req_bits_uop_rxq_idx; // @[lsu.scala:201:7] wire [5:0] io_core_exe_0_req_bits_uop_pdst_0 = io_core_exe_0_req_bits_uop_pdst; // @[lsu.scala:201:7] wire [5:0] io_core_exe_0_req_bits_uop_prs1_0 = io_core_exe_0_req_bits_uop_prs1; // @[lsu.scala:201:7] wire [5:0] io_core_exe_0_req_bits_uop_prs2_0 = io_core_exe_0_req_bits_uop_prs2; // @[lsu.scala:201:7] wire [5:0] io_core_exe_0_req_bits_uop_prs3_0 = io_core_exe_0_req_bits_uop_prs3; // @[lsu.scala:201:7] wire [3:0] io_core_exe_0_req_bits_uop_ppred_0 = io_core_exe_0_req_bits_uop_ppred; // @[lsu.scala:201:7] wire io_core_exe_0_req_bits_uop_prs1_busy_0 = io_core_exe_0_req_bits_uop_prs1_busy; // @[lsu.scala:201:7] wire io_core_exe_0_req_bits_uop_prs2_busy_0 = io_core_exe_0_req_bits_uop_prs2_busy; // @[lsu.scala:201:7] wire io_core_exe_0_req_bits_uop_prs3_busy_0 = io_core_exe_0_req_bits_uop_prs3_busy; // @[lsu.scala:201:7] wire io_core_exe_0_req_bits_uop_ppred_busy_0 = io_core_exe_0_req_bits_uop_ppred_busy; // @[lsu.scala:201:7] wire [5:0] io_core_exe_0_req_bits_uop_stale_pdst_0 = io_core_exe_0_req_bits_uop_stale_pdst; // @[lsu.scala:201:7] wire io_core_exe_0_req_bits_uop_exception_0 = io_core_exe_0_req_bits_uop_exception; // @[lsu.scala:201:7] wire [63:0] io_core_exe_0_req_bits_uop_exc_cause_0 = io_core_exe_0_req_bits_uop_exc_cause; // @[lsu.scala:201:7] wire io_core_exe_0_req_bits_uop_bypassable_0 = io_core_exe_0_req_bits_uop_bypassable; // @[lsu.scala:201:7] wire [4:0] io_core_exe_0_req_bits_uop_mem_cmd_0 = io_core_exe_0_req_bits_uop_mem_cmd; // @[lsu.scala:201:7] wire [1:0] io_core_exe_0_req_bits_uop_mem_size_0 = io_core_exe_0_req_bits_uop_mem_size; // @[lsu.scala:201:7] wire io_core_exe_0_req_bits_uop_mem_signed_0 = io_core_exe_0_req_bits_uop_mem_signed; // @[lsu.scala:201:7] wire io_core_exe_0_req_bits_uop_is_fence_0 = io_core_exe_0_req_bits_uop_is_fence; // @[lsu.scala:201:7] wire io_core_exe_0_req_bits_uop_is_fencei_0 = io_core_exe_0_req_bits_uop_is_fencei; // @[lsu.scala:201:7] wire io_core_exe_0_req_bits_uop_is_amo_0 = io_core_exe_0_req_bits_uop_is_amo; // @[lsu.scala:201:7] wire io_core_exe_0_req_bits_uop_uses_ldq_0 = io_core_exe_0_req_bits_uop_uses_ldq; // @[lsu.scala:201:7] wire io_core_exe_0_req_bits_uop_uses_stq_0 = io_core_exe_0_req_bits_uop_uses_stq; // @[lsu.scala:201:7] wire io_core_exe_0_req_bits_uop_is_sys_pc2epc_0 = io_core_exe_0_req_bits_uop_is_sys_pc2epc; // @[lsu.scala:201:7] wire io_core_exe_0_req_bits_uop_is_unique_0 = io_core_exe_0_req_bits_uop_is_unique; // @[lsu.scala:201:7] wire io_core_exe_0_req_bits_uop_flush_on_commit_0 = io_core_exe_0_req_bits_uop_flush_on_commit; // @[lsu.scala:201:7] wire io_core_exe_0_req_bits_uop_ldst_is_rs1_0 = io_core_exe_0_req_bits_uop_ldst_is_rs1; // @[lsu.scala:201:7] wire [5:0] io_core_exe_0_req_bits_uop_ldst_0 = io_core_exe_0_req_bits_uop_ldst; // @[lsu.scala:201:7] wire [5:0] io_core_exe_0_req_bits_uop_lrs1_0 = io_core_exe_0_req_bits_uop_lrs1; // @[lsu.scala:201:7] wire [5:0] io_core_exe_0_req_bits_uop_lrs2_0 = io_core_exe_0_req_bits_uop_lrs2; // @[lsu.scala:201:7] wire [5:0] io_core_exe_0_req_bits_uop_lrs3_0 = io_core_exe_0_req_bits_uop_lrs3; // @[lsu.scala:201:7] wire io_core_exe_0_req_bits_uop_ldst_val_0 = io_core_exe_0_req_bits_uop_ldst_val; // @[lsu.scala:201:7] wire [1:0] io_core_exe_0_req_bits_uop_dst_rtype_0 = io_core_exe_0_req_bits_uop_dst_rtype; // @[lsu.scala:201:7] wire [1:0] io_core_exe_0_req_bits_uop_lrs1_rtype_0 = io_core_exe_0_req_bits_uop_lrs1_rtype; // @[lsu.scala:201:7] wire [1:0] io_core_exe_0_req_bits_uop_lrs2_rtype_0 = io_core_exe_0_req_bits_uop_lrs2_rtype; // @[lsu.scala:201:7] wire io_core_exe_0_req_bits_uop_frs3_en_0 = io_core_exe_0_req_bits_uop_frs3_en; // @[lsu.scala:201:7] wire io_core_exe_0_req_bits_uop_fp_val_0 = io_core_exe_0_req_bits_uop_fp_val; // @[lsu.scala:201:7] wire io_core_exe_0_req_bits_uop_fp_single_0 = io_core_exe_0_req_bits_uop_fp_single; // @[lsu.scala:201:7] wire io_core_exe_0_req_bits_uop_xcpt_pf_if_0 = io_core_exe_0_req_bits_uop_xcpt_pf_if; // @[lsu.scala:201:7] wire io_core_exe_0_req_bits_uop_xcpt_ae_if_0 = io_core_exe_0_req_bits_uop_xcpt_ae_if; // @[lsu.scala:201:7] wire io_core_exe_0_req_bits_uop_xcpt_ma_if_0 = io_core_exe_0_req_bits_uop_xcpt_ma_if; // @[lsu.scala:201:7] wire io_core_exe_0_req_bits_uop_bp_debug_if_0 = io_core_exe_0_req_bits_uop_bp_debug_if; // @[lsu.scala:201:7] wire io_core_exe_0_req_bits_uop_bp_xcpt_if_0 = io_core_exe_0_req_bits_uop_bp_xcpt_if; // @[lsu.scala:201:7] wire [1:0] io_core_exe_0_req_bits_uop_debug_fsrc_0 = io_core_exe_0_req_bits_uop_debug_fsrc; // @[lsu.scala:201:7] wire [1:0] io_core_exe_0_req_bits_uop_debug_tsrc_0 = io_core_exe_0_req_bits_uop_debug_tsrc; // @[lsu.scala:201:7] wire [63:0] io_core_exe_0_req_bits_data_0 = io_core_exe_0_req_bits_data; // @[lsu.scala:201:7] wire [39:0] io_core_exe_0_req_bits_addr_0 = io_core_exe_0_req_bits_addr; // @[lsu.scala:201:7] wire io_core_exe_0_req_bits_mxcpt_valid_0 = io_core_exe_0_req_bits_mxcpt_valid; // @[lsu.scala:201:7] wire [24:0] io_core_exe_0_req_bits_mxcpt_bits_0 = io_core_exe_0_req_bits_mxcpt_bits; // @[lsu.scala:201:7] wire io_core_exe_0_req_bits_sfence_valid_0 = io_core_exe_0_req_bits_sfence_valid; // @[lsu.scala:201:7] wire io_core_exe_0_req_bits_sfence_bits_rs1_0 = io_core_exe_0_req_bits_sfence_bits_rs1; // @[lsu.scala:201:7] wire io_core_exe_0_req_bits_sfence_bits_rs2_0 = io_core_exe_0_req_bits_sfence_bits_rs2; // @[lsu.scala:201:7] wire [38:0] io_core_exe_0_req_bits_sfence_bits_addr_0 = io_core_exe_0_req_bits_sfence_bits_addr; // @[lsu.scala:201:7] wire io_core_exe_0_req_bits_sfence_bits_asid_0 = io_core_exe_0_req_bits_sfence_bits_asid; // @[lsu.scala:201:7] wire io_core_dis_uops_0_valid_0 = io_core_dis_uops_0_valid; // @[lsu.scala:201:7] wire [6:0] io_core_dis_uops_0_bits_uopc_0 = io_core_dis_uops_0_bits_uopc; // @[lsu.scala:201:7] wire [31:0] io_core_dis_uops_0_bits_inst_0 = io_core_dis_uops_0_bits_inst; // @[lsu.scala:201:7] wire [31:0] io_core_dis_uops_0_bits_debug_inst_0 = io_core_dis_uops_0_bits_debug_inst; // @[lsu.scala:201:7] wire io_core_dis_uops_0_bits_is_rvc_0 = io_core_dis_uops_0_bits_is_rvc; // @[lsu.scala:201:7] wire [39:0] io_core_dis_uops_0_bits_debug_pc_0 = io_core_dis_uops_0_bits_debug_pc; // @[lsu.scala:201:7] wire [2:0] io_core_dis_uops_0_bits_iq_type_0 = io_core_dis_uops_0_bits_iq_type; // @[lsu.scala:201:7] wire [9:0] io_core_dis_uops_0_bits_fu_code_0 = io_core_dis_uops_0_bits_fu_code; // @[lsu.scala:201:7] wire [3:0] io_core_dis_uops_0_bits_ctrl_br_type_0 = io_core_dis_uops_0_bits_ctrl_br_type; // @[lsu.scala:201:7] wire [1:0] io_core_dis_uops_0_bits_ctrl_op1_sel_0 = io_core_dis_uops_0_bits_ctrl_op1_sel; // @[lsu.scala:201:7] wire [2:0] io_core_dis_uops_0_bits_ctrl_op2_sel_0 = io_core_dis_uops_0_bits_ctrl_op2_sel; // @[lsu.scala:201:7] wire [2:0] io_core_dis_uops_0_bits_ctrl_imm_sel_0 = io_core_dis_uops_0_bits_ctrl_imm_sel; // @[lsu.scala:201:7] wire [4:0] io_core_dis_uops_0_bits_ctrl_op_fcn_0 = io_core_dis_uops_0_bits_ctrl_op_fcn; // @[lsu.scala:201:7] wire io_core_dis_uops_0_bits_ctrl_fcn_dw_0 = io_core_dis_uops_0_bits_ctrl_fcn_dw; // @[lsu.scala:201:7] wire [2:0] io_core_dis_uops_0_bits_ctrl_csr_cmd_0 = io_core_dis_uops_0_bits_ctrl_csr_cmd; // @[lsu.scala:201:7] wire io_core_dis_uops_0_bits_ctrl_is_load_0 = io_core_dis_uops_0_bits_ctrl_is_load; // @[lsu.scala:201:7] wire io_core_dis_uops_0_bits_ctrl_is_sta_0 = io_core_dis_uops_0_bits_ctrl_is_sta; // @[lsu.scala:201:7] wire io_core_dis_uops_0_bits_ctrl_is_std_0 = io_core_dis_uops_0_bits_ctrl_is_std; // @[lsu.scala:201:7] wire [1:0] io_core_dis_uops_0_bits_iw_state_0 = io_core_dis_uops_0_bits_iw_state; // @[lsu.scala:201:7] wire io_core_dis_uops_0_bits_iw_p1_poisoned_0 = io_core_dis_uops_0_bits_iw_p1_poisoned; // @[lsu.scala:201:7] wire io_core_dis_uops_0_bits_iw_p2_poisoned_0 = io_core_dis_uops_0_bits_iw_p2_poisoned; // @[lsu.scala:201:7] wire io_core_dis_uops_0_bits_is_br_0 = io_core_dis_uops_0_bits_is_br; // @[lsu.scala:201:7] wire io_core_dis_uops_0_bits_is_jalr_0 = io_core_dis_uops_0_bits_is_jalr; // @[lsu.scala:201:7] wire io_core_dis_uops_0_bits_is_jal_0 = io_core_dis_uops_0_bits_is_jal; // @[lsu.scala:201:7] wire io_core_dis_uops_0_bits_is_sfb_0 = io_core_dis_uops_0_bits_is_sfb; // @[lsu.scala:201:7] wire [7:0] io_core_dis_uops_0_bits_br_mask_0 = io_core_dis_uops_0_bits_br_mask; // @[lsu.scala:201:7] wire [2:0] io_core_dis_uops_0_bits_br_tag_0 = io_core_dis_uops_0_bits_br_tag; // @[lsu.scala:201:7] wire [3:0] io_core_dis_uops_0_bits_ftq_idx_0 = io_core_dis_uops_0_bits_ftq_idx; // @[lsu.scala:201:7] wire io_core_dis_uops_0_bits_edge_inst_0 = io_core_dis_uops_0_bits_edge_inst; // @[lsu.scala:201:7] wire [5:0] io_core_dis_uops_0_bits_pc_lob_0 = io_core_dis_uops_0_bits_pc_lob; // @[lsu.scala:201:7] wire io_core_dis_uops_0_bits_taken_0 = io_core_dis_uops_0_bits_taken; // @[lsu.scala:201:7] wire [19:0] io_core_dis_uops_0_bits_imm_packed_0 = io_core_dis_uops_0_bits_imm_packed; // @[lsu.scala:201:7] wire [11:0] io_core_dis_uops_0_bits_csr_addr_0 = io_core_dis_uops_0_bits_csr_addr; // @[lsu.scala:201:7] wire [4:0] io_core_dis_uops_0_bits_rob_idx_0 = io_core_dis_uops_0_bits_rob_idx; // @[lsu.scala:201:7] wire [2:0] io_core_dis_uops_0_bits_ldq_idx_0 = io_core_dis_uops_0_bits_ldq_idx; // @[lsu.scala:201:7] wire [2:0] io_core_dis_uops_0_bits_stq_idx_0 = io_core_dis_uops_0_bits_stq_idx; // @[lsu.scala:201:7] wire [1:0] io_core_dis_uops_0_bits_rxq_idx_0 = io_core_dis_uops_0_bits_rxq_idx; // @[lsu.scala:201:7] wire [5:0] io_core_dis_uops_0_bits_pdst_0 = io_core_dis_uops_0_bits_pdst; // @[lsu.scala:201:7] wire [5:0] io_core_dis_uops_0_bits_prs1_0 = io_core_dis_uops_0_bits_prs1; // @[lsu.scala:201:7] wire [5:0] io_core_dis_uops_0_bits_prs2_0 = io_core_dis_uops_0_bits_prs2; // @[lsu.scala:201:7] wire [5:0] io_core_dis_uops_0_bits_prs3_0 = io_core_dis_uops_0_bits_prs3; // @[lsu.scala:201:7] wire io_core_dis_uops_0_bits_prs1_busy_0 = io_core_dis_uops_0_bits_prs1_busy; // @[lsu.scala:201:7] wire io_core_dis_uops_0_bits_prs2_busy_0 = io_core_dis_uops_0_bits_prs2_busy; // @[lsu.scala:201:7] wire io_core_dis_uops_0_bits_prs3_busy_0 = io_core_dis_uops_0_bits_prs3_busy; // @[lsu.scala:201:7] wire [5:0] io_core_dis_uops_0_bits_stale_pdst_0 = io_core_dis_uops_0_bits_stale_pdst; // @[lsu.scala:201:7] wire io_core_dis_uops_0_bits_exception_0 = io_core_dis_uops_0_bits_exception; // @[lsu.scala:201:7] wire [63:0] io_core_dis_uops_0_bits_exc_cause_0 = io_core_dis_uops_0_bits_exc_cause; // @[lsu.scala:201:7] wire io_core_dis_uops_0_bits_bypassable_0 = io_core_dis_uops_0_bits_bypassable; // @[lsu.scala:201:7] wire [4:0] io_core_dis_uops_0_bits_mem_cmd_0 = io_core_dis_uops_0_bits_mem_cmd; // @[lsu.scala:201:7] wire [1:0] io_core_dis_uops_0_bits_mem_size_0 = io_core_dis_uops_0_bits_mem_size; // @[lsu.scala:201:7] wire io_core_dis_uops_0_bits_mem_signed_0 = io_core_dis_uops_0_bits_mem_signed; // @[lsu.scala:201:7] wire io_core_dis_uops_0_bits_is_fence_0 = io_core_dis_uops_0_bits_is_fence; // @[lsu.scala:201:7] wire io_core_dis_uops_0_bits_is_fencei_0 = io_core_dis_uops_0_bits_is_fencei; // @[lsu.scala:201:7] wire io_core_dis_uops_0_bits_is_amo_0 = io_core_dis_uops_0_bits_is_amo; // @[lsu.scala:201:7] wire io_core_dis_uops_0_bits_uses_ldq_0 = io_core_dis_uops_0_bits_uses_ldq; // @[lsu.scala:201:7] wire io_core_dis_uops_0_bits_uses_stq_0 = io_core_dis_uops_0_bits_uses_stq; // @[lsu.scala:201:7] wire io_core_dis_uops_0_bits_is_sys_pc2epc_0 = io_core_dis_uops_0_bits_is_sys_pc2epc; // @[lsu.scala:201:7] wire io_core_dis_uops_0_bits_is_unique_0 = io_core_dis_uops_0_bits_is_unique; // @[lsu.scala:201:7] wire io_core_dis_uops_0_bits_flush_on_commit_0 = io_core_dis_uops_0_bits_flush_on_commit; // @[lsu.scala:201:7] wire io_core_dis_uops_0_bits_ldst_is_rs1_0 = io_core_dis_uops_0_bits_ldst_is_rs1; // @[lsu.scala:201:7] wire [5:0] io_core_dis_uops_0_bits_ldst_0 = io_core_dis_uops_0_bits_ldst; // @[lsu.scala:201:7] wire [5:0] io_core_dis_uops_0_bits_lrs1_0 = io_core_dis_uops_0_bits_lrs1; // @[lsu.scala:201:7] wire [5:0] io_core_dis_uops_0_bits_lrs2_0 = io_core_dis_uops_0_bits_lrs2; // @[lsu.scala:201:7] wire [5:0] io_core_dis_uops_0_bits_lrs3_0 = io_core_dis_uops_0_bits_lrs3; // @[lsu.scala:201:7] wire io_core_dis_uops_0_bits_ldst_val_0 = io_core_dis_uops_0_bits_ldst_val; // @[lsu.scala:201:7] wire [1:0] io_core_dis_uops_0_bits_dst_rtype_0 = io_core_dis_uops_0_bits_dst_rtype; // @[lsu.scala:201:7] wire [1:0] io_core_dis_uops_0_bits_lrs1_rtype_0 = io_core_dis_uops_0_bits_lrs1_rtype; // @[lsu.scala:201:7] wire [1:0] io_core_dis_uops_0_bits_lrs2_rtype_0 = io_core_dis_uops_0_bits_lrs2_rtype; // @[lsu.scala:201:7] wire io_core_dis_uops_0_bits_frs3_en_0 = io_core_dis_uops_0_bits_frs3_en; // @[lsu.scala:201:7] wire io_core_dis_uops_0_bits_fp_val_0 = io_core_dis_uops_0_bits_fp_val; // @[lsu.scala:201:7] wire io_core_dis_uops_0_bits_fp_single_0 = io_core_dis_uops_0_bits_fp_single; // @[lsu.scala:201:7] wire io_core_dis_uops_0_bits_xcpt_pf_if_0 = io_core_dis_uops_0_bits_xcpt_pf_if; // @[lsu.scala:201:7] wire io_core_dis_uops_0_bits_xcpt_ae_if_0 = io_core_dis_uops_0_bits_xcpt_ae_if; // @[lsu.scala:201:7] wire io_core_dis_uops_0_bits_xcpt_ma_if_0 = io_core_dis_uops_0_bits_xcpt_ma_if; // @[lsu.scala:201:7] wire io_core_dis_uops_0_bits_bp_debug_if_0 = io_core_dis_uops_0_bits_bp_debug_if; // @[lsu.scala:201:7] wire io_core_dis_uops_0_bits_bp_xcpt_if_0 = io_core_dis_uops_0_bits_bp_xcpt_if; // @[lsu.scala:201:7] wire [1:0] io_core_dis_uops_0_bits_debug_fsrc_0 = io_core_dis_uops_0_bits_debug_fsrc; // @[lsu.scala:201:7] wire [1:0] io_core_dis_uops_0_bits_debug_tsrc_0 = io_core_dis_uops_0_bits_debug_tsrc; // @[lsu.scala:201:7] wire io_core_fp_stdata_valid_0 = io_core_fp_stdata_valid; // @[lsu.scala:201:7] wire [6:0] io_core_fp_stdata_bits_uop_uopc_0 = io_core_fp_stdata_bits_uop_uopc; // @[lsu.scala:201:7] wire [31:0] io_core_fp_stdata_bits_uop_inst_0 = io_core_fp_stdata_bits_uop_inst; // @[lsu.scala:201:7] wire [31:0] io_core_fp_stdata_bits_uop_debug_inst_0 = io_core_fp_stdata_bits_uop_debug_inst; // @[lsu.scala:201:7] wire io_core_fp_stdata_bits_uop_is_rvc_0 = io_core_fp_stdata_bits_uop_is_rvc; // @[lsu.scala:201:7] wire [39:0] io_core_fp_stdata_bits_uop_debug_pc_0 = io_core_fp_stdata_bits_uop_debug_pc; // @[lsu.scala:201:7] wire [2:0] io_core_fp_stdata_bits_uop_iq_type_0 = io_core_fp_stdata_bits_uop_iq_type; // @[lsu.scala:201:7] wire [9:0] io_core_fp_stdata_bits_uop_fu_code_0 = io_core_fp_stdata_bits_uop_fu_code; // @[lsu.scala:201:7] wire [3:0] io_core_fp_stdata_bits_uop_ctrl_br_type_0 = io_core_fp_stdata_bits_uop_ctrl_br_type; // @[lsu.scala:201:7] wire [1:0] io_core_fp_stdata_bits_uop_ctrl_op1_sel_0 = io_core_fp_stdata_bits_uop_ctrl_op1_sel; // @[lsu.scala:201:7] wire [2:0] io_core_fp_stdata_bits_uop_ctrl_op2_sel_0 = io_core_fp_stdata_bits_uop_ctrl_op2_sel; // @[lsu.scala:201:7] wire [2:0] io_core_fp_stdata_bits_uop_ctrl_imm_sel_0 = io_core_fp_stdata_bits_uop_ctrl_imm_sel; // @[lsu.scala:201:7] wire [4:0] io_core_fp_stdata_bits_uop_ctrl_op_fcn_0 = io_core_fp_stdata_bits_uop_ctrl_op_fcn; // @[lsu.scala:201:7] wire io_core_fp_stdata_bits_uop_ctrl_fcn_dw_0 = io_core_fp_stdata_bits_uop_ctrl_fcn_dw; // @[lsu.scala:201:7] wire [2:0] io_core_fp_stdata_bits_uop_ctrl_csr_cmd_0 = io_core_fp_stdata_bits_uop_ctrl_csr_cmd; // @[lsu.scala:201:7] wire io_core_fp_stdata_bits_uop_ctrl_is_load_0 = io_core_fp_stdata_bits_uop_ctrl_is_load; // @[lsu.scala:201:7] wire io_core_fp_stdata_bits_uop_ctrl_is_sta_0 = io_core_fp_stdata_bits_uop_ctrl_is_sta; // @[lsu.scala:201:7] wire io_core_fp_stdata_bits_uop_ctrl_is_std_0 = io_core_fp_stdata_bits_uop_ctrl_is_std; // @[lsu.scala:201:7] wire [1:0] io_core_fp_stdata_bits_uop_iw_state_0 = io_core_fp_stdata_bits_uop_iw_state; // @[lsu.scala:201:7] wire io_core_fp_stdata_bits_uop_iw_p1_poisoned_0 = io_core_fp_stdata_bits_uop_iw_p1_poisoned; // @[lsu.scala:201:7] wire io_core_fp_stdata_bits_uop_iw_p2_poisoned_0 = io_core_fp_stdata_bits_uop_iw_p2_poisoned; // @[lsu.scala:201:7] wire io_core_fp_stdata_bits_uop_is_br_0 = io_core_fp_stdata_bits_uop_is_br; // @[lsu.scala:201:7] wire io_core_fp_stdata_bits_uop_is_jalr_0 = io_core_fp_stdata_bits_uop_is_jalr; // @[lsu.scala:201:7] wire io_core_fp_stdata_bits_uop_is_jal_0 = io_core_fp_stdata_bits_uop_is_jal; // @[lsu.scala:201:7] wire io_core_fp_stdata_bits_uop_is_sfb_0 = io_core_fp_stdata_bits_uop_is_sfb; // @[lsu.scala:201:7] wire [7:0] io_core_fp_stdata_bits_uop_br_mask_0 = io_core_fp_stdata_bits_uop_br_mask; // @[lsu.scala:201:7] wire [2:0] io_core_fp_stdata_bits_uop_br_tag_0 = io_core_fp_stdata_bits_uop_br_tag; // @[lsu.scala:201:7] wire [3:0] io_core_fp_stdata_bits_uop_ftq_idx_0 = io_core_fp_stdata_bits_uop_ftq_idx; // @[lsu.scala:201:7] wire io_core_fp_stdata_bits_uop_edge_inst_0 = io_core_fp_stdata_bits_uop_edge_inst; // @[lsu.scala:201:7] wire [5:0] io_core_fp_stdata_bits_uop_pc_lob_0 = io_core_fp_stdata_bits_uop_pc_lob; // @[lsu.scala:201:7] wire io_core_fp_stdata_bits_uop_taken_0 = io_core_fp_stdata_bits_uop_taken; // @[lsu.scala:201:7] wire [19:0] io_core_fp_stdata_bits_uop_imm_packed_0 = io_core_fp_stdata_bits_uop_imm_packed; // @[lsu.scala:201:7] wire [11:0] io_core_fp_stdata_bits_uop_csr_addr_0 = io_core_fp_stdata_bits_uop_csr_addr; // @[lsu.scala:201:7] wire [4:0] io_core_fp_stdata_bits_uop_rob_idx_0 = io_core_fp_stdata_bits_uop_rob_idx; // @[lsu.scala:201:7] wire [2:0] io_core_fp_stdata_bits_uop_ldq_idx_0 = io_core_fp_stdata_bits_uop_ldq_idx; // @[lsu.scala:201:7] wire [2:0] io_core_fp_stdata_bits_uop_stq_idx_0 = io_core_fp_stdata_bits_uop_stq_idx; // @[lsu.scala:201:7] wire [1:0] io_core_fp_stdata_bits_uop_rxq_idx_0 = io_core_fp_stdata_bits_uop_rxq_idx; // @[lsu.scala:201:7] wire [5:0] io_core_fp_stdata_bits_uop_pdst_0 = io_core_fp_stdata_bits_uop_pdst; // @[lsu.scala:201:7] wire [5:0] io_core_fp_stdata_bits_uop_prs1_0 = io_core_fp_stdata_bits_uop_prs1; // @[lsu.scala:201:7] wire [5:0] io_core_fp_stdata_bits_uop_prs2_0 = io_core_fp_stdata_bits_uop_prs2; // @[lsu.scala:201:7] wire [5:0] io_core_fp_stdata_bits_uop_prs3_0 = io_core_fp_stdata_bits_uop_prs3; // @[lsu.scala:201:7] wire [3:0] io_core_fp_stdata_bits_uop_ppred_0 = io_core_fp_stdata_bits_uop_ppred; // @[lsu.scala:201:7] wire io_core_fp_stdata_bits_uop_prs1_busy_0 = io_core_fp_stdata_bits_uop_prs1_busy; // @[lsu.scala:201:7] wire io_core_fp_stdata_bits_uop_prs2_busy_0 = io_core_fp_stdata_bits_uop_prs2_busy; // @[lsu.scala:201:7] wire io_core_fp_stdata_bits_uop_prs3_busy_0 = io_core_fp_stdata_bits_uop_prs3_busy; // @[lsu.scala:201:7] wire io_core_fp_stdata_bits_uop_ppred_busy_0 = io_core_fp_stdata_bits_uop_ppred_busy; // @[lsu.scala:201:7] wire [5:0] io_core_fp_stdata_bits_uop_stale_pdst_0 = io_core_fp_stdata_bits_uop_stale_pdst; // @[lsu.scala:201:7] wire io_core_fp_stdata_bits_uop_exception_0 = io_core_fp_stdata_bits_uop_exception; // @[lsu.scala:201:7] wire [63:0] io_core_fp_stdata_bits_uop_exc_cause_0 = io_core_fp_stdata_bits_uop_exc_cause; // @[lsu.scala:201:7] wire io_core_fp_stdata_bits_uop_bypassable_0 = io_core_fp_stdata_bits_uop_bypassable; // @[lsu.scala:201:7] wire [4:0] io_core_fp_stdata_bits_uop_mem_cmd_0 = io_core_fp_stdata_bits_uop_mem_cmd; // @[lsu.scala:201:7] wire [1:0] io_core_fp_stdata_bits_uop_mem_size_0 = io_core_fp_stdata_bits_uop_mem_size; // @[lsu.scala:201:7] wire io_core_fp_stdata_bits_uop_mem_signed_0 = io_core_fp_stdata_bits_uop_mem_signed; // @[lsu.scala:201:7] wire io_core_fp_stdata_bits_uop_is_fence_0 = io_core_fp_stdata_bits_uop_is_fence; // @[lsu.scala:201:7] wire io_core_fp_stdata_bits_uop_is_fencei_0 = io_core_fp_stdata_bits_uop_is_fencei; // @[lsu.scala:201:7] wire io_core_fp_stdata_bits_uop_is_amo_0 = io_core_fp_stdata_bits_uop_is_amo; // @[lsu.scala:201:7] wire io_core_fp_stdata_bits_uop_uses_ldq_0 = io_core_fp_stdata_bits_uop_uses_ldq; // @[lsu.scala:201:7] wire io_core_fp_stdata_bits_uop_uses_stq_0 = io_core_fp_stdata_bits_uop_uses_stq; // @[lsu.scala:201:7] wire io_core_fp_stdata_bits_uop_is_sys_pc2epc_0 = io_core_fp_stdata_bits_uop_is_sys_pc2epc; // @[lsu.scala:201:7] wire io_core_fp_stdata_bits_uop_is_unique_0 = io_core_fp_stdata_bits_uop_is_unique; // @[lsu.scala:201:7] wire io_core_fp_stdata_bits_uop_flush_on_commit_0 = io_core_fp_stdata_bits_uop_flush_on_commit; // @[lsu.scala:201:7] wire io_core_fp_stdata_bits_uop_ldst_is_rs1_0 = io_core_fp_stdata_bits_uop_ldst_is_rs1; // @[lsu.scala:201:7] wire [5:0] io_core_fp_stdata_bits_uop_ldst_0 = io_core_fp_stdata_bits_uop_ldst; // @[lsu.scala:201:7] wire [5:0] io_core_fp_stdata_bits_uop_lrs1_0 = io_core_fp_stdata_bits_uop_lrs1; // @[lsu.scala:201:7] wire [5:0] io_core_fp_stdata_bits_uop_lrs2_0 = io_core_fp_stdata_bits_uop_lrs2; // @[lsu.scala:201:7] wire [5:0] io_core_fp_stdata_bits_uop_lrs3_0 = io_core_fp_stdata_bits_uop_lrs3; // @[lsu.scala:201:7] wire io_core_fp_stdata_bits_uop_ldst_val_0 = io_core_fp_stdata_bits_uop_ldst_val; // @[lsu.scala:201:7] wire [1:0] io_core_fp_stdata_bits_uop_dst_rtype_0 = io_core_fp_stdata_bits_uop_dst_rtype; // @[lsu.scala:201:7] wire [1:0] io_core_fp_stdata_bits_uop_lrs1_rtype_0 = io_core_fp_stdata_bits_uop_lrs1_rtype; // @[lsu.scala:201:7] wire [1:0] io_core_fp_stdata_bits_uop_lrs2_rtype_0 = io_core_fp_stdata_bits_uop_lrs2_rtype; // @[lsu.scala:201:7] wire io_core_fp_stdata_bits_uop_frs3_en_0 = io_core_fp_stdata_bits_uop_frs3_en; // @[lsu.scala:201:7] wire io_core_fp_stdata_bits_uop_fp_val_0 = io_core_fp_stdata_bits_uop_fp_val; // @[lsu.scala:201:7] wire io_core_fp_stdata_bits_uop_fp_single_0 = io_core_fp_stdata_bits_uop_fp_single; // @[lsu.scala:201:7] wire io_core_fp_stdata_bits_uop_xcpt_pf_if_0 = io_core_fp_stdata_bits_uop_xcpt_pf_if; // @[lsu.scala:201:7] wire io_core_fp_stdata_bits_uop_xcpt_ae_if_0 = io_core_fp_stdata_bits_uop_xcpt_ae_if; // @[lsu.scala:201:7] wire io_core_fp_stdata_bits_uop_xcpt_ma_if_0 = io_core_fp_stdata_bits_uop_xcpt_ma_if; // @[lsu.scala:201:7] wire io_core_fp_stdata_bits_uop_bp_debug_if_0 = io_core_fp_stdata_bits_uop_bp_debug_if; // @[lsu.scala:201:7] wire io_core_fp_stdata_bits_uop_bp_xcpt_if_0 = io_core_fp_stdata_bits_uop_bp_xcpt_if; // @[lsu.scala:201:7] wire [1:0] io_core_fp_stdata_bits_uop_debug_fsrc_0 = io_core_fp_stdata_bits_uop_debug_fsrc; // @[lsu.scala:201:7] wire [1:0] io_core_fp_stdata_bits_uop_debug_tsrc_0 = io_core_fp_stdata_bits_uop_debug_tsrc; // @[lsu.scala:201:7] wire [63:0] io_core_fp_stdata_bits_data_0 = io_core_fp_stdata_bits_data; // @[lsu.scala:201:7] wire io_core_fp_stdata_bits_predicated_0 = io_core_fp_stdata_bits_predicated; // @[lsu.scala:201:7] wire io_core_fp_stdata_bits_fflags_valid_0 = io_core_fp_stdata_bits_fflags_valid; // @[lsu.scala:201:7] wire [6:0] io_core_fp_stdata_bits_fflags_bits_uop_uopc_0 = io_core_fp_stdata_bits_fflags_bits_uop_uopc; // @[lsu.scala:201:7] wire [31:0] io_core_fp_stdata_bits_fflags_bits_uop_inst_0 = io_core_fp_stdata_bits_fflags_bits_uop_inst; // @[lsu.scala:201:7] wire [31:0] io_core_fp_stdata_bits_fflags_bits_uop_debug_inst_0 = io_core_fp_stdata_bits_fflags_bits_uop_debug_inst; // @[lsu.scala:201:7] wire io_core_fp_stdata_bits_fflags_bits_uop_is_rvc_0 = io_core_fp_stdata_bits_fflags_bits_uop_is_rvc; // @[lsu.scala:201:7] wire [39:0] io_core_fp_stdata_bits_fflags_bits_uop_debug_pc_0 = io_core_fp_stdata_bits_fflags_bits_uop_debug_pc; // @[lsu.scala:201:7] wire [2:0] io_core_fp_stdata_bits_fflags_bits_uop_iq_type_0 = io_core_fp_stdata_bits_fflags_bits_uop_iq_type; // @[lsu.scala:201:7] wire [9:0] io_core_fp_stdata_bits_fflags_bits_uop_fu_code_0 = io_core_fp_stdata_bits_fflags_bits_uop_fu_code; // @[lsu.scala:201:7] wire [3:0] io_core_fp_stdata_bits_fflags_bits_uop_ctrl_br_type_0 = io_core_fp_stdata_bits_fflags_bits_uop_ctrl_br_type; // @[lsu.scala:201:7] wire [1:0] io_core_fp_stdata_bits_fflags_bits_uop_ctrl_op1_sel_0 = io_core_fp_stdata_bits_fflags_bits_uop_ctrl_op1_sel; // @[lsu.scala:201:7] wire [2:0] io_core_fp_stdata_bits_fflags_bits_uop_ctrl_op2_sel_0 = io_core_fp_stdata_bits_fflags_bits_uop_ctrl_op2_sel; // @[lsu.scala:201:7] wire [2:0] io_core_fp_stdata_bits_fflags_bits_uop_ctrl_imm_sel_0 = io_core_fp_stdata_bits_fflags_bits_uop_ctrl_imm_sel; // @[lsu.scala:201:7] wire [4:0] io_core_fp_stdata_bits_fflags_bits_uop_ctrl_op_fcn_0 = io_core_fp_stdata_bits_fflags_bits_uop_ctrl_op_fcn; // @[lsu.scala:201:7] wire io_core_fp_stdata_bits_fflags_bits_uop_ctrl_fcn_dw_0 = io_core_fp_stdata_bits_fflags_bits_uop_ctrl_fcn_dw; // @[lsu.scala:201:7] wire [2:0] io_core_fp_stdata_bits_fflags_bits_uop_ctrl_csr_cmd_0 = io_core_fp_stdata_bits_fflags_bits_uop_ctrl_csr_cmd; // @[lsu.scala:201:7] wire io_core_fp_stdata_bits_fflags_bits_uop_ctrl_is_load_0 = io_core_fp_stdata_bits_fflags_bits_uop_ctrl_is_load; // @[lsu.scala:201:7] wire io_core_fp_stdata_bits_fflags_bits_uop_ctrl_is_sta_0 = io_core_fp_stdata_bits_fflags_bits_uop_ctrl_is_sta; // @[lsu.scala:201:7] wire io_core_fp_stdata_bits_fflags_bits_uop_ctrl_is_std_0 = io_core_fp_stdata_bits_fflags_bits_uop_ctrl_is_std; // @[lsu.scala:201:7] wire [1:0] io_core_fp_stdata_bits_fflags_bits_uop_iw_state_0 = io_core_fp_stdata_bits_fflags_bits_uop_iw_state; // @[lsu.scala:201:7] wire io_core_fp_stdata_bits_fflags_bits_uop_iw_p1_poisoned_0 = io_core_fp_stdata_bits_fflags_bits_uop_iw_p1_poisoned; // @[lsu.scala:201:7] wire io_core_fp_stdata_bits_fflags_bits_uop_iw_p2_poisoned_0 = io_core_fp_stdata_bits_fflags_bits_uop_iw_p2_poisoned; // @[lsu.scala:201:7] wire io_core_fp_stdata_bits_fflags_bits_uop_is_br_0 = io_core_fp_stdata_bits_fflags_bits_uop_is_br; // @[lsu.scala:201:7] wire io_core_fp_stdata_bits_fflags_bits_uop_is_jalr_0 = io_core_fp_stdata_bits_fflags_bits_uop_is_jalr; // @[lsu.scala:201:7] wire io_core_fp_stdata_bits_fflags_bits_uop_is_jal_0 = io_core_fp_stdata_bits_fflags_bits_uop_is_jal; // @[lsu.scala:201:7] wire io_core_fp_stdata_bits_fflags_bits_uop_is_sfb_0 = io_core_fp_stdata_bits_fflags_bits_uop_is_sfb; // @[lsu.scala:201:7] wire [7:0] io_core_fp_stdata_bits_fflags_bits_uop_br_mask_0 = io_core_fp_stdata_bits_fflags_bits_uop_br_mask; // @[lsu.scala:201:7] wire [2:0] io_core_fp_stdata_bits_fflags_bits_uop_br_tag_0 = io_core_fp_stdata_bits_fflags_bits_uop_br_tag; // @[lsu.scala:201:7] wire [3:0] io_core_fp_stdata_bits_fflags_bits_uop_ftq_idx_0 = io_core_fp_stdata_bits_fflags_bits_uop_ftq_idx; // @[lsu.scala:201:7] wire io_core_fp_stdata_bits_fflags_bits_uop_edge_inst_0 = io_core_fp_stdata_bits_fflags_bits_uop_edge_inst; // @[lsu.scala:201:7] wire [5:0] io_core_fp_stdata_bits_fflags_bits_uop_pc_lob_0 = io_core_fp_stdata_bits_fflags_bits_uop_pc_lob; // @[lsu.scala:201:7] wire io_core_fp_stdata_bits_fflags_bits_uop_taken_0 = io_core_fp_stdata_bits_fflags_bits_uop_taken; // @[lsu.scala:201:7] wire [19:0] io_core_fp_stdata_bits_fflags_bits_uop_imm_packed_0 = io_core_fp_stdata_bits_fflags_bits_uop_imm_packed; // @[lsu.scala:201:7] wire [11:0] io_core_fp_stdata_bits_fflags_bits_uop_csr_addr_0 = io_core_fp_stdata_bits_fflags_bits_uop_csr_addr; // @[lsu.scala:201:7] wire [4:0] io_core_fp_stdata_bits_fflags_bits_uop_rob_idx_0 = io_core_fp_stdata_bits_fflags_bits_uop_rob_idx; // @[lsu.scala:201:7] wire [2:0] io_core_fp_stdata_bits_fflags_bits_uop_ldq_idx_0 = io_core_fp_stdata_bits_fflags_bits_uop_ldq_idx; // @[lsu.scala:201:7] wire [2:0] io_core_fp_stdata_bits_fflags_bits_uop_stq_idx_0 = io_core_fp_stdata_bits_fflags_bits_uop_stq_idx; // @[lsu.scala:201:7] wire [1:0] io_core_fp_stdata_bits_fflags_bits_uop_rxq_idx_0 = io_core_fp_stdata_bits_fflags_bits_uop_rxq_idx; // @[lsu.scala:201:7] wire [5:0] io_core_fp_stdata_bits_fflags_bits_uop_pdst_0 = io_core_fp_stdata_bits_fflags_bits_uop_pdst; // @[lsu.scala:201:7] wire [5:0] io_core_fp_stdata_bits_fflags_bits_uop_prs1_0 = io_core_fp_stdata_bits_fflags_bits_uop_prs1; // @[lsu.scala:201:7] wire [5:0] io_core_fp_stdata_bits_fflags_bits_uop_prs2_0 = io_core_fp_stdata_bits_fflags_bits_uop_prs2; // @[lsu.scala:201:7] wire [5:0] io_core_fp_stdata_bits_fflags_bits_uop_prs3_0 = io_core_fp_stdata_bits_fflags_bits_uop_prs3; // @[lsu.scala:201:7] wire [3:0] io_core_fp_stdata_bits_fflags_bits_uop_ppred_0 = io_core_fp_stdata_bits_fflags_bits_uop_ppred; // @[lsu.scala:201:7] wire io_core_fp_stdata_bits_fflags_bits_uop_prs1_busy_0 = io_core_fp_stdata_bits_fflags_bits_uop_prs1_busy; // @[lsu.scala:201:7] wire io_core_fp_stdata_bits_fflags_bits_uop_prs2_busy_0 = io_core_fp_stdata_bits_fflags_bits_uop_prs2_busy; // @[lsu.scala:201:7] wire io_core_fp_stdata_bits_fflags_bits_uop_prs3_busy_0 = io_core_fp_stdata_bits_fflags_bits_uop_prs3_busy; // @[lsu.scala:201:7] wire io_core_fp_stdata_bits_fflags_bits_uop_ppred_busy_0 = io_core_fp_stdata_bits_fflags_bits_uop_ppred_busy; // @[lsu.scala:201:7] wire [5:0] io_core_fp_stdata_bits_fflags_bits_uop_stale_pdst_0 = io_core_fp_stdata_bits_fflags_bits_uop_stale_pdst; // @[lsu.scala:201:7] wire io_core_fp_stdata_bits_fflags_bits_uop_exception_0 = io_core_fp_stdata_bits_fflags_bits_uop_exception; // @[lsu.scala:201:7] wire [63:0] io_core_fp_stdata_bits_fflags_bits_uop_exc_cause_0 = io_core_fp_stdata_bits_fflags_bits_uop_exc_cause; // @[lsu.scala:201:7] wire io_core_fp_stdata_bits_fflags_bits_uop_bypassable_0 = io_core_fp_stdata_bits_fflags_bits_uop_bypassable; // @[lsu.scala:201:7] wire [4:0] io_core_fp_stdata_bits_fflags_bits_uop_mem_cmd_0 = io_core_fp_stdata_bits_fflags_bits_uop_mem_cmd; // @[lsu.scala:201:7] wire [1:0] io_core_fp_stdata_bits_fflags_bits_uop_mem_size_0 = io_core_fp_stdata_bits_fflags_bits_uop_mem_size; // @[lsu.scala:201:7] wire io_core_fp_stdata_bits_fflags_bits_uop_mem_signed_0 = io_core_fp_stdata_bits_fflags_bits_uop_mem_signed; // @[lsu.scala:201:7] wire io_core_fp_stdata_bits_fflags_bits_uop_is_fence_0 = io_core_fp_stdata_bits_fflags_bits_uop_is_fence; // @[lsu.scala:201:7] wire io_core_fp_stdata_bits_fflags_bits_uop_is_fencei_0 = io_core_fp_stdata_bits_fflags_bits_uop_is_fencei; // @[lsu.scala:201:7] wire io_core_fp_stdata_bits_fflags_bits_uop_is_amo_0 = io_core_fp_stdata_bits_fflags_bits_uop_is_amo; // @[lsu.scala:201:7] wire io_core_fp_stdata_bits_fflags_bits_uop_uses_ldq_0 = io_core_fp_stdata_bits_fflags_bits_uop_uses_ldq; // @[lsu.scala:201:7] wire io_core_fp_stdata_bits_fflags_bits_uop_uses_stq_0 = io_core_fp_stdata_bits_fflags_bits_uop_uses_stq; // @[lsu.scala:201:7] wire io_core_fp_stdata_bits_fflags_bits_uop_is_sys_pc2epc_0 = io_core_fp_stdata_bits_fflags_bits_uop_is_sys_pc2epc; // @[lsu.scala:201:7] wire io_core_fp_stdata_bits_fflags_bits_uop_is_unique_0 = io_core_fp_stdata_bits_fflags_bits_uop_is_unique; // @[lsu.scala:201:7] wire io_core_fp_stdata_bits_fflags_bits_uop_flush_on_commit_0 = io_core_fp_stdata_bits_fflags_bits_uop_flush_on_commit; // @[lsu.scala:201:7] wire io_core_fp_stdata_bits_fflags_bits_uop_ldst_is_rs1_0 = io_core_fp_stdata_bits_fflags_bits_uop_ldst_is_rs1; // @[lsu.scala:201:7] wire [5:0] io_core_fp_stdata_bits_fflags_bits_uop_ldst_0 = io_core_fp_stdata_bits_fflags_bits_uop_ldst; // @[lsu.scala:201:7] wire [5:0] io_core_fp_stdata_bits_fflags_bits_uop_lrs1_0 = io_core_fp_stdata_bits_fflags_bits_uop_lrs1; // @[lsu.scala:201:7] wire [5:0] io_core_fp_stdata_bits_fflags_bits_uop_lrs2_0 = io_core_fp_stdata_bits_fflags_bits_uop_lrs2; // @[lsu.scala:201:7] wire [5:0] io_core_fp_stdata_bits_fflags_bits_uop_lrs3_0 = io_core_fp_stdata_bits_fflags_bits_uop_lrs3; // @[lsu.scala:201:7] wire io_core_fp_stdata_bits_fflags_bits_uop_ldst_val_0 = io_core_fp_stdata_bits_fflags_bits_uop_ldst_val; // @[lsu.scala:201:7] wire [1:0] io_core_fp_stdata_bits_fflags_bits_uop_dst_rtype_0 = io_core_fp_stdata_bits_fflags_bits_uop_dst_rtype; // @[lsu.scala:201:7] wire [1:0] io_core_fp_stdata_bits_fflags_bits_uop_lrs1_rtype_0 = io_core_fp_stdata_bits_fflags_bits_uop_lrs1_rtype; // @[lsu.scala:201:7] wire [1:0] io_core_fp_stdata_bits_fflags_bits_uop_lrs2_rtype_0 = io_core_fp_stdata_bits_fflags_bits_uop_lrs2_rtype; // @[lsu.scala:201:7] wire io_core_fp_stdata_bits_fflags_bits_uop_frs3_en_0 = io_core_fp_stdata_bits_fflags_bits_uop_frs3_en; // @[lsu.scala:201:7] wire io_core_fp_stdata_bits_fflags_bits_uop_fp_val_0 = io_core_fp_stdata_bits_fflags_bits_uop_fp_val; // @[lsu.scala:201:7] wire io_core_fp_stdata_bits_fflags_bits_uop_fp_single_0 = io_core_fp_stdata_bits_fflags_bits_uop_fp_single; // @[lsu.scala:201:7] wire io_core_fp_stdata_bits_fflags_bits_uop_xcpt_pf_if_0 = io_core_fp_stdata_bits_fflags_bits_uop_xcpt_pf_if; // @[lsu.scala:201:7] wire io_core_fp_stdata_bits_fflags_bits_uop_xcpt_ae_if_0 = io_core_fp_stdata_bits_fflags_bits_uop_xcpt_ae_if; // @[lsu.scala:201:7] wire io_core_fp_stdata_bits_fflags_bits_uop_xcpt_ma_if_0 = io_core_fp_stdata_bits_fflags_bits_uop_xcpt_ma_if; // @[lsu.scala:201:7] wire io_core_fp_stdata_bits_fflags_bits_uop_bp_debug_if_0 = io_core_fp_stdata_bits_fflags_bits_uop_bp_debug_if; // @[lsu.scala:201:7] wire io_core_fp_stdata_bits_fflags_bits_uop_bp_xcpt_if_0 = io_core_fp_stdata_bits_fflags_bits_uop_bp_xcpt_if; // @[lsu.scala:201:7] wire [1:0] io_core_fp_stdata_bits_fflags_bits_uop_debug_fsrc_0 = io_core_fp_stdata_bits_fflags_bits_uop_debug_fsrc; // @[lsu.scala:201:7] wire [1:0] io_core_fp_stdata_bits_fflags_bits_uop_debug_tsrc_0 = io_core_fp_stdata_bits_fflags_bits_uop_debug_tsrc; // @[lsu.scala:201:7] wire [4:0] io_core_fp_stdata_bits_fflags_bits_flags_0 = io_core_fp_stdata_bits_fflags_bits_flags; // @[lsu.scala:201:7] wire io_core_commit_valids_0_0 = io_core_commit_valids_0; // @[lsu.scala:201:7] wire io_core_commit_arch_valids_0_0 = io_core_commit_arch_valids_0; // @[lsu.scala:201:7] wire [6:0] io_core_commit_uops_0_uopc_0 = io_core_commit_uops_0_uopc; // @[lsu.scala:201:7] wire [31:0] io_core_commit_uops_0_inst_0 = io_core_commit_uops_0_inst; // @[lsu.scala:201:7] wire [31:0] io_core_commit_uops_0_debug_inst_0 = io_core_commit_uops_0_debug_inst; // @[lsu.scala:201:7] wire io_core_commit_uops_0_is_rvc_0 = io_core_commit_uops_0_is_rvc; // @[lsu.scala:201:7] wire [39:0] io_core_commit_uops_0_debug_pc_0 = io_core_commit_uops_0_debug_pc; // @[lsu.scala:201:7] wire [2:0] io_core_commit_uops_0_iq_type_0 = io_core_commit_uops_0_iq_type; // @[lsu.scala:201:7] wire [9:0] io_core_commit_uops_0_fu_code_0 = io_core_commit_uops_0_fu_code; // @[lsu.scala:201:7] wire [3:0] io_core_commit_uops_0_ctrl_br_type_0 = io_core_commit_uops_0_ctrl_br_type; // @[lsu.scala:201:7] wire [1:0] io_core_commit_uops_0_ctrl_op1_sel_0 = io_core_commit_uops_0_ctrl_op1_sel; // @[lsu.scala:201:7] wire [2:0] io_core_commit_uops_0_ctrl_op2_sel_0 = io_core_commit_uops_0_ctrl_op2_sel; // @[lsu.scala:201:7] wire [2:0] io_core_commit_uops_0_ctrl_imm_sel_0 = io_core_commit_uops_0_ctrl_imm_sel; // @[lsu.scala:201:7] wire [4:0] io_core_commit_uops_0_ctrl_op_fcn_0 = io_core_commit_uops_0_ctrl_op_fcn; // @[lsu.scala:201:7] wire io_core_commit_uops_0_ctrl_fcn_dw_0 = io_core_commit_uops_0_ctrl_fcn_dw; // @[lsu.scala:201:7] wire [2:0] io_core_commit_uops_0_ctrl_csr_cmd_0 = io_core_commit_uops_0_ctrl_csr_cmd; // @[lsu.scala:201:7] wire io_core_commit_uops_0_ctrl_is_load_0 = io_core_commit_uops_0_ctrl_is_load; // @[lsu.scala:201:7] wire io_core_commit_uops_0_ctrl_is_sta_0 = io_core_commit_uops_0_ctrl_is_sta; // @[lsu.scala:201:7] wire io_core_commit_uops_0_ctrl_is_std_0 = io_core_commit_uops_0_ctrl_is_std; // @[lsu.scala:201:7] wire [1:0] io_core_commit_uops_0_iw_state_0 = io_core_commit_uops_0_iw_state; // @[lsu.scala:201:7] wire io_core_commit_uops_0_iw_p1_poisoned_0 = io_core_commit_uops_0_iw_p1_poisoned; // @[lsu.scala:201:7] wire io_core_commit_uops_0_iw_p2_poisoned_0 = io_core_commit_uops_0_iw_p2_poisoned; // @[lsu.scala:201:7] wire io_core_commit_uops_0_is_br_0 = io_core_commit_uops_0_is_br; // @[lsu.scala:201:7] wire io_core_commit_uops_0_is_jalr_0 = io_core_commit_uops_0_is_jalr; // @[lsu.scala:201:7] wire io_core_commit_uops_0_is_jal_0 = io_core_commit_uops_0_is_jal; // @[lsu.scala:201:7] wire io_core_commit_uops_0_is_sfb_0 = io_core_commit_uops_0_is_sfb; // @[lsu.scala:201:7] wire [7:0] io_core_commit_uops_0_br_mask_0 = io_core_commit_uops_0_br_mask; // @[lsu.scala:201:7] wire [2:0] io_core_commit_uops_0_br_tag_0 = io_core_commit_uops_0_br_tag; // @[lsu.scala:201:7] wire [3:0] io_core_commit_uops_0_ftq_idx_0 = io_core_commit_uops_0_ftq_idx; // @[lsu.scala:201:7] wire io_core_commit_uops_0_edge_inst_0 = io_core_commit_uops_0_edge_inst; // @[lsu.scala:201:7] wire [5:0] io_core_commit_uops_0_pc_lob_0 = io_core_commit_uops_0_pc_lob; // @[lsu.scala:201:7] wire io_core_commit_uops_0_taken_0 = io_core_commit_uops_0_taken; // @[lsu.scala:201:7] wire [19:0] io_core_commit_uops_0_imm_packed_0 = io_core_commit_uops_0_imm_packed; // @[lsu.scala:201:7] wire [11:0] io_core_commit_uops_0_csr_addr_0 = io_core_commit_uops_0_csr_addr; // @[lsu.scala:201:7] wire [4:0] io_core_commit_uops_0_rob_idx_0 = io_core_commit_uops_0_rob_idx; // @[lsu.scala:201:7] wire [2:0] io_core_commit_uops_0_ldq_idx_0 = io_core_commit_uops_0_ldq_idx; // @[lsu.scala:201:7] wire [2:0] io_core_commit_uops_0_stq_idx_0 = io_core_commit_uops_0_stq_idx; // @[lsu.scala:201:7] wire [1:0] io_core_commit_uops_0_rxq_idx_0 = io_core_commit_uops_0_rxq_idx; // @[lsu.scala:201:7] wire [5:0] io_core_commit_uops_0_pdst_0 = io_core_commit_uops_0_pdst; // @[lsu.scala:201:7] wire [5:0] io_core_commit_uops_0_prs1_0 = io_core_commit_uops_0_prs1; // @[lsu.scala:201:7] wire [5:0] io_core_commit_uops_0_prs2_0 = io_core_commit_uops_0_prs2; // @[lsu.scala:201:7] wire [5:0] io_core_commit_uops_0_prs3_0 = io_core_commit_uops_0_prs3; // @[lsu.scala:201:7] wire [3:0] io_core_commit_uops_0_ppred_0 = io_core_commit_uops_0_ppred; // @[lsu.scala:201:7] wire io_core_commit_uops_0_prs1_busy_0 = io_core_commit_uops_0_prs1_busy; // @[lsu.scala:201:7] wire io_core_commit_uops_0_prs2_busy_0 = io_core_commit_uops_0_prs2_busy; // @[lsu.scala:201:7] wire io_core_commit_uops_0_prs3_busy_0 = io_core_commit_uops_0_prs3_busy; // @[lsu.scala:201:7] wire io_core_commit_uops_0_ppred_busy_0 = io_core_commit_uops_0_ppred_busy; // @[lsu.scala:201:7] wire [5:0] io_core_commit_uops_0_stale_pdst_0 = io_core_commit_uops_0_stale_pdst; // @[lsu.scala:201:7] wire io_core_commit_uops_0_exception_0 = io_core_commit_uops_0_exception; // @[lsu.scala:201:7] wire [63:0] io_core_commit_uops_0_exc_cause_0 = io_core_commit_uops_0_exc_cause; // @[lsu.scala:201:7] wire io_core_commit_uops_0_bypassable_0 = io_core_commit_uops_0_bypassable; // @[lsu.scala:201:7] wire [4:0] io_core_commit_uops_0_mem_cmd_0 = io_core_commit_uops_0_mem_cmd; // @[lsu.scala:201:7] wire [1:0] io_core_commit_uops_0_mem_size_0 = io_core_commit_uops_0_mem_size; // @[lsu.scala:201:7] wire io_core_commit_uops_0_mem_signed_0 = io_core_commit_uops_0_mem_signed; // @[lsu.scala:201:7] wire io_core_commit_uops_0_is_fence_0 = io_core_commit_uops_0_is_fence; // @[lsu.scala:201:7] wire io_core_commit_uops_0_is_fencei_0 = io_core_commit_uops_0_is_fencei; // @[lsu.scala:201:7] wire io_core_commit_uops_0_is_amo_0 = io_core_commit_uops_0_is_amo; // @[lsu.scala:201:7] wire io_core_commit_uops_0_uses_ldq_0 = io_core_commit_uops_0_uses_ldq; // @[lsu.scala:201:7] wire io_core_commit_uops_0_uses_stq_0 = io_core_commit_uops_0_uses_stq; // @[lsu.scala:201:7] wire io_core_commit_uops_0_is_sys_pc2epc_0 = io_core_commit_uops_0_is_sys_pc2epc; // @[lsu.scala:201:7] wire io_core_commit_uops_0_is_unique_0 = io_core_commit_uops_0_is_unique; // @[lsu.scala:201:7] wire io_core_commit_uops_0_flush_on_commit_0 = io_core_commit_uops_0_flush_on_commit; // @[lsu.scala:201:7] wire io_core_commit_uops_0_ldst_is_rs1_0 = io_core_commit_uops_0_ldst_is_rs1; // @[lsu.scala:201:7] wire [5:0] io_core_commit_uops_0_ldst_0 = io_core_commit_uops_0_ldst; // @[lsu.scala:201:7] wire [5:0] io_core_commit_uops_0_lrs1_0 = io_core_commit_uops_0_lrs1; // @[lsu.scala:201:7] wire [5:0] io_core_commit_uops_0_lrs2_0 = io_core_commit_uops_0_lrs2; // @[lsu.scala:201:7] wire [5:0] io_core_commit_uops_0_lrs3_0 = io_core_commit_uops_0_lrs3; // @[lsu.scala:201:7] wire io_core_commit_uops_0_ldst_val_0 = io_core_commit_uops_0_ldst_val; // @[lsu.scala:201:7] wire [1:0] io_core_commit_uops_0_dst_rtype_0 = io_core_commit_uops_0_dst_rtype; // @[lsu.scala:201:7] wire [1:0] io_core_commit_uops_0_lrs1_rtype_0 = io_core_commit_uops_0_lrs1_rtype; // @[lsu.scala:201:7] wire [1:0] io_core_commit_uops_0_lrs2_rtype_0 = io_core_commit_uops_0_lrs2_rtype; // @[lsu.scala:201:7] wire io_core_commit_uops_0_frs3_en_0 = io_core_commit_uops_0_frs3_en; // @[lsu.scala:201:7] wire io_core_commit_uops_0_fp_val_0 = io_core_commit_uops_0_fp_val; // @[lsu.scala:201:7] wire io_core_commit_uops_0_fp_single_0 = io_core_commit_uops_0_fp_single; // @[lsu.scala:201:7] wire io_core_commit_uops_0_xcpt_pf_if_0 = io_core_commit_uops_0_xcpt_pf_if; // @[lsu.scala:201:7] wire io_core_commit_uops_0_xcpt_ae_if_0 = io_core_commit_uops_0_xcpt_ae_if; // @[lsu.scala:201:7] wire io_core_commit_uops_0_xcpt_ma_if_0 = io_core_commit_uops_0_xcpt_ma_if; // @[lsu.scala:201:7] wire io_core_commit_uops_0_bp_debug_if_0 = io_core_commit_uops_0_bp_debug_if; // @[lsu.scala:201:7] wire io_core_commit_uops_0_bp_xcpt_if_0 = io_core_commit_uops_0_bp_xcpt_if; // @[lsu.scala:201:7] wire [1:0] io_core_commit_uops_0_debug_fsrc_0 = io_core_commit_uops_0_debug_fsrc; // @[lsu.scala:201:7] wire [1:0] io_core_commit_uops_0_debug_tsrc_0 = io_core_commit_uops_0_debug_tsrc; // @[lsu.scala:201:7] wire io_core_commit_fflags_valid_0 = io_core_commit_fflags_valid; // @[lsu.scala:201:7] wire [4:0] io_core_commit_fflags_bits_0 = io_core_commit_fflags_bits; // @[lsu.scala:201:7] wire [31:0] io_core_commit_debug_insts_0_0 = io_core_commit_debug_insts_0; // @[lsu.scala:201:7] wire io_core_commit_rbk_valids_0_0 = io_core_commit_rbk_valids_0; // @[lsu.scala:201:7] wire io_core_commit_rollback_0 = io_core_commit_rollback; // @[lsu.scala:201:7] wire [63:0] io_core_commit_debug_wdata_0_0 = io_core_commit_debug_wdata_0; // @[lsu.scala:201:7] wire io_core_commit_load_at_rob_head_0 = io_core_commit_load_at_rob_head; // @[lsu.scala:201:7] wire io_core_fence_dmem_0 = io_core_fence_dmem; // @[lsu.scala:201:7] wire [7:0] io_core_brupdate_b1_resolve_mask_0 = io_core_brupdate_b1_resolve_mask; // @[lsu.scala:201:7] wire [7:0] io_core_brupdate_b1_mispredict_mask_0 = io_core_brupdate_b1_mispredict_mask; // @[lsu.scala:201:7] wire [6:0] io_core_brupdate_b2_uop_uopc_0 = io_core_brupdate_b2_uop_uopc; // @[lsu.scala:201:7] wire [31:0] io_core_brupdate_b2_uop_inst_0 = io_core_brupdate_b2_uop_inst; // @[lsu.scala:201:7] wire [31:0] io_core_brupdate_b2_uop_debug_inst_0 = io_core_brupdate_b2_uop_debug_inst; // @[lsu.scala:201:7] wire io_core_brupdate_b2_uop_is_rvc_0 = io_core_brupdate_b2_uop_is_rvc; // @[lsu.scala:201:7] wire [39:0] io_core_brupdate_b2_uop_debug_pc_0 = io_core_brupdate_b2_uop_debug_pc; // @[lsu.scala:201:7] wire [2:0] io_core_brupdate_b2_uop_iq_type_0 = io_core_brupdate_b2_uop_iq_type; // @[lsu.scala:201:7] wire [9:0] io_core_brupdate_b2_uop_fu_code_0 = io_core_brupdate_b2_uop_fu_code; // @[lsu.scala:201:7] wire [3:0] io_core_brupdate_b2_uop_ctrl_br_type_0 = io_core_brupdate_b2_uop_ctrl_br_type; // @[lsu.scala:201:7] wire [1:0] io_core_brupdate_b2_uop_ctrl_op1_sel_0 = io_core_brupdate_b2_uop_ctrl_op1_sel; // @[lsu.scala:201:7] wire [2:0] io_core_brupdate_b2_uop_ctrl_op2_sel_0 = io_core_brupdate_b2_uop_ctrl_op2_sel; // @[lsu.scala:201:7] wire [2:0] io_core_brupdate_b2_uop_ctrl_imm_sel_0 = io_core_brupdate_b2_uop_ctrl_imm_sel; // @[lsu.scala:201:7] wire [4:0] io_core_brupdate_b2_uop_ctrl_op_fcn_0 = io_core_brupdate_b2_uop_ctrl_op_fcn; // @[lsu.scala:201:7] wire io_core_brupdate_b2_uop_ctrl_fcn_dw_0 = io_core_brupdate_b2_uop_ctrl_fcn_dw; // @[lsu.scala:201:7] wire [2:0] io_core_brupdate_b2_uop_ctrl_csr_cmd_0 = io_core_brupdate_b2_uop_ctrl_csr_cmd; // @[lsu.scala:201:7] wire io_core_brupdate_b2_uop_ctrl_is_load_0 = io_core_brupdate_b2_uop_ctrl_is_load; // @[lsu.scala:201:7] wire io_core_brupdate_b2_uop_ctrl_is_sta_0 = io_core_brupdate_b2_uop_ctrl_is_sta; // @[lsu.scala:201:7] wire io_core_brupdate_b2_uop_ctrl_is_std_0 = io_core_brupdate_b2_uop_ctrl_is_std; // @[lsu.scala:201:7] wire [1:0] io_core_brupdate_b2_uop_iw_state_0 = io_core_brupdate_b2_uop_iw_state; // @[lsu.scala:201:7] wire io_core_brupdate_b2_uop_iw_p1_poisoned_0 = io_core_brupdate_b2_uop_iw_p1_poisoned; // @[lsu.scala:201:7] wire io_core_brupdate_b2_uop_iw_p2_poisoned_0 = io_core_brupdate_b2_uop_iw_p2_poisoned; // @[lsu.scala:201:7] wire io_core_brupdate_b2_uop_is_br_0 = io_core_brupdate_b2_uop_is_br; // @[lsu.scala:201:7] wire io_core_brupdate_b2_uop_is_jalr_0 = io_core_brupdate_b2_uop_is_jalr; // @[lsu.scala:201:7] wire io_core_brupdate_b2_uop_is_jal_0 = io_core_brupdate_b2_uop_is_jal; // @[lsu.scala:201:7] wire io_core_brupdate_b2_uop_is_sfb_0 = io_core_brupdate_b2_uop_is_sfb; // @[lsu.scala:201:7] wire [7:0] io_core_brupdate_b2_uop_br_mask_0 = io_core_brupdate_b2_uop_br_mask; // @[lsu.scala:201:7] wire [2:0] io_core_brupdate_b2_uop_br_tag_0 = io_core_brupdate_b2_uop_br_tag; // @[lsu.scala:201:7] wire [3:0] io_core_brupdate_b2_uop_ftq_idx_0 = io_core_brupdate_b2_uop_ftq_idx; // @[lsu.scala:201:7] wire io_core_brupdate_b2_uop_edge_inst_0 = io_core_brupdate_b2_uop_edge_inst; // @[lsu.scala:201:7] wire [5:0] io_core_brupdate_b2_uop_pc_lob_0 = io_core_brupdate_b2_uop_pc_lob; // @[lsu.scala:201:7] wire io_core_brupdate_b2_uop_taken_0 = io_core_brupdate_b2_uop_taken; // @[lsu.scala:201:7] wire [19:0] io_core_brupdate_b2_uop_imm_packed_0 = io_core_brupdate_b2_uop_imm_packed; // @[lsu.scala:201:7] wire [11:0] io_core_brupdate_b2_uop_csr_addr_0 = io_core_brupdate_b2_uop_csr_addr; // @[lsu.scala:201:7] wire [4:0] io_core_brupdate_b2_uop_rob_idx_0 = io_core_brupdate_b2_uop_rob_idx; // @[lsu.scala:201:7] wire [2:0] io_core_brupdate_b2_uop_ldq_idx_0 = io_core_brupdate_b2_uop_ldq_idx; // @[lsu.scala:201:7] wire [2:0] io_core_brupdate_b2_uop_stq_idx_0 = io_core_brupdate_b2_uop_stq_idx; // @[lsu.scala:201:7] wire [1:0] io_core_brupdate_b2_uop_rxq_idx_0 = io_core_brupdate_b2_uop_rxq_idx; // @[lsu.scala:201:7] wire [5:0] io_core_brupdate_b2_uop_pdst_0 = io_core_brupdate_b2_uop_pdst; // @[lsu.scala:201:7] wire [5:0] io_core_brupdate_b2_uop_prs1_0 = io_core_brupdate_b2_uop_prs1; // @[lsu.scala:201:7] wire [5:0] io_core_brupdate_b2_uop_prs2_0 = io_core_brupdate_b2_uop_prs2; // @[lsu.scala:201:7] wire [5:0] io_core_brupdate_b2_uop_prs3_0 = io_core_brupdate_b2_uop_prs3; // @[lsu.scala:201:7] wire [3:0] io_core_brupdate_b2_uop_ppred_0 = io_core_brupdate_b2_uop_ppred; // @[lsu.scala:201:7] wire io_core_brupdate_b2_uop_prs1_busy_0 = io_core_brupdate_b2_uop_prs1_busy; // @[lsu.scala:201:7] wire io_core_brupdate_b2_uop_prs2_busy_0 = io_core_brupdate_b2_uop_prs2_busy; // @[lsu.scala:201:7] wire io_core_brupdate_b2_uop_prs3_busy_0 = io_core_brupdate_b2_uop_prs3_busy; // @[lsu.scala:201:7] wire io_core_brupdate_b2_uop_ppred_busy_0 = io_core_brupdate_b2_uop_ppred_busy; // @[lsu.scala:201:7] wire [5:0] io_core_brupdate_b2_uop_stale_pdst_0 = io_core_brupdate_b2_uop_stale_pdst; // @[lsu.scala:201:7] wire io_core_brupdate_b2_uop_exception_0 = io_core_brupdate_b2_uop_exception; // @[lsu.scala:201:7] wire [63:0] io_core_brupdate_b2_uop_exc_cause_0 = io_core_brupdate_b2_uop_exc_cause; // @[lsu.scala:201:7] wire io_core_brupdate_b2_uop_bypassable_0 = io_core_brupdate_b2_uop_bypassable; // @[lsu.scala:201:7] wire [4:0] io_core_brupdate_b2_uop_mem_cmd_0 = io_core_brupdate_b2_uop_mem_cmd; // @[lsu.scala:201:7] wire [1:0] io_core_brupdate_b2_uop_mem_size_0 = io_core_brupdate_b2_uop_mem_size; // @[lsu.scala:201:7] wire io_core_brupdate_b2_uop_mem_signed_0 = io_core_brupdate_b2_uop_mem_signed; // @[lsu.scala:201:7] wire io_core_brupdate_b2_uop_is_fence_0 = io_core_brupdate_b2_uop_is_fence; // @[lsu.scala:201:7] wire io_core_brupdate_b2_uop_is_fencei_0 = io_core_brupdate_b2_uop_is_fencei; // @[lsu.scala:201:7] wire io_core_brupdate_b2_uop_is_amo_0 = io_core_brupdate_b2_uop_is_amo; // @[lsu.scala:201:7] wire io_core_brupdate_b2_uop_uses_ldq_0 = io_core_brupdate_b2_uop_uses_ldq; // @[lsu.scala:201:7] wire io_core_brupdate_b2_uop_uses_stq_0 = io_core_brupdate_b2_uop_uses_stq; // @[lsu.scala:201:7] wire io_core_brupdate_b2_uop_is_sys_pc2epc_0 = io_core_brupdate_b2_uop_is_sys_pc2epc; // @[lsu.scala:201:7] wire io_core_brupdate_b2_uop_is_unique_0 = io_core_brupdate_b2_uop_is_unique; // @[lsu.scala:201:7] wire io_core_brupdate_b2_uop_flush_on_commit_0 = io_core_brupdate_b2_uop_flush_on_commit; // @[lsu.scala:201:7] wire io_core_brupdate_b2_uop_ldst_is_rs1_0 = io_core_brupdate_b2_uop_ldst_is_rs1; // @[lsu.scala:201:7] wire [5:0] io_core_brupdate_b2_uop_ldst_0 = io_core_brupdate_b2_uop_ldst; // @[lsu.scala:201:7] wire [5:0] io_core_brupdate_b2_uop_lrs1_0 = io_core_brupdate_b2_uop_lrs1; // @[lsu.scala:201:7] wire [5:0] io_core_brupdate_b2_uop_lrs2_0 = io_core_brupdate_b2_uop_lrs2; // @[lsu.scala:201:7] wire [5:0] io_core_brupdate_b2_uop_lrs3_0 = io_core_brupdate_b2_uop_lrs3; // @[lsu.scala:201:7] wire io_core_brupdate_b2_uop_ldst_val_0 = io_core_brupdate_b2_uop_ldst_val; // @[lsu.scala:201:7] wire [1:0] io_core_brupdate_b2_uop_dst_rtype_0 = io_core_brupdate_b2_uop_dst_rtype; // @[lsu.scala:201:7] wire [1:0] io_core_brupdate_b2_uop_lrs1_rtype_0 = io_core_brupdate_b2_uop_lrs1_rtype; // @[lsu.scala:201:7] wire [1:0] io_core_brupdate_b2_uop_lrs2_rtype_0 = io_core_brupdate_b2_uop_lrs2_rtype; // @[lsu.scala:201:7] wire io_core_brupdate_b2_uop_frs3_en_0 = io_core_brupdate_b2_uop_frs3_en; // @[lsu.scala:201:7] wire io_core_brupdate_b2_uop_fp_val_0 = io_core_brupdate_b2_uop_fp_val; // @[lsu.scala:201:7] wire io_core_brupdate_b2_uop_fp_single_0 = io_core_brupdate_b2_uop_fp_single; // @[lsu.scala:201:7] wire io_core_brupdate_b2_uop_xcpt_pf_if_0 = io_core_brupdate_b2_uop_xcpt_pf_if; // @[lsu.scala:201:7] wire io_core_brupdate_b2_uop_xcpt_ae_if_0 = io_core_brupdate_b2_uop_xcpt_ae_if; // @[lsu.scala:201:7] wire io_core_brupdate_b2_uop_xcpt_ma_if_0 = io_core_brupdate_b2_uop_xcpt_ma_if; // @[lsu.scala:201:7] wire io_core_brupdate_b2_uop_bp_debug_if_0 = io_core_brupdate_b2_uop_bp_debug_if; // @[lsu.scala:201:7] wire io_core_brupdate_b2_uop_bp_xcpt_if_0 = io_core_brupdate_b2_uop_bp_xcpt_if; // @[lsu.scala:201:7] wire [1:0] io_core_brupdate_b2_uop_debug_fsrc_0 = io_core_brupdate_b2_uop_debug_fsrc; // @[lsu.scala:201:7] wire [1:0] io_core_brupdate_b2_uop_debug_tsrc_0 = io_core_brupdate_b2_uop_debug_tsrc; // @[lsu.scala:201:7] wire io_core_brupdate_b2_valid_0 = io_core_brupdate_b2_valid; // @[lsu.scala:201:7] wire io_core_brupdate_b2_mispredict_0 = io_core_brupdate_b2_mispredict; // @[lsu.scala:201:7] wire io_core_brupdate_b2_taken_0 = io_core_brupdate_b2_taken; // @[lsu.scala:201:7] wire [2:0] io_core_brupdate_b2_cfi_type_0 = io_core_brupdate_b2_cfi_type; // @[lsu.scala:201:7] wire [1:0] io_core_brupdate_b2_pc_sel_0 = io_core_brupdate_b2_pc_sel; // @[lsu.scala:201:7] wire [39:0] io_core_brupdate_b2_jalr_target_0 = io_core_brupdate_b2_jalr_target; // @[lsu.scala:201:7] wire [20:0] io_core_brupdate_b2_target_offset_0 = io_core_brupdate_b2_target_offset; // @[lsu.scala:201:7] wire [4:0] io_core_rob_pnr_idx_0 = io_core_rob_pnr_idx; // @[lsu.scala:201:7] wire [4:0] io_core_rob_head_idx_0 = io_core_rob_head_idx; // @[lsu.scala:201:7] wire io_core_exception_0 = io_core_exception; // @[lsu.scala:201:7] wire [63:0] io_core_tsc_reg_0 = io_core_tsc_reg; // @[lsu.scala:201:7] wire io_dmem_req_ready_0 = io_dmem_req_ready; // @[lsu.scala:201:7] wire io_dmem_resp_0_valid_0 = io_dmem_resp_0_valid; // @[lsu.scala:201:7] wire [6:0] io_dmem_resp_0_bits_uop_uopc_0 = io_dmem_resp_0_bits_uop_uopc; // @[lsu.scala:201:7] wire [31:0] io_dmem_resp_0_bits_uop_inst_0 = io_dmem_resp_0_bits_uop_inst; // @[lsu.scala:201:7] wire [31:0] io_dmem_resp_0_bits_uop_debug_inst_0 = io_dmem_resp_0_bits_uop_debug_inst; // @[lsu.scala:201:7] wire io_dmem_resp_0_bits_uop_is_rvc_0 = io_dmem_resp_0_bits_uop_is_rvc; // @[lsu.scala:201:7] wire [39:0] io_dmem_resp_0_bits_uop_debug_pc_0 = io_dmem_resp_0_bits_uop_debug_pc; // @[lsu.scala:201:7] wire [2:0] io_dmem_resp_0_bits_uop_iq_type_0 = io_dmem_resp_0_bits_uop_iq_type; // @[lsu.scala:201:7] wire [9:0] io_dmem_resp_0_bits_uop_fu_code_0 = io_dmem_resp_0_bits_uop_fu_code; // @[lsu.scala:201:7] wire [3:0] io_dmem_resp_0_bits_uop_ctrl_br_type_0 = io_dmem_resp_0_bits_uop_ctrl_br_type; // @[lsu.scala:201:7] wire [1:0] io_dmem_resp_0_bits_uop_ctrl_op1_sel_0 = io_dmem_resp_0_bits_uop_ctrl_op1_sel; // @[lsu.scala:201:7] wire [2:0] io_dmem_resp_0_bits_uop_ctrl_op2_sel_0 = io_dmem_resp_0_bits_uop_ctrl_op2_sel; // @[lsu.scala:201:7] wire [2:0] io_dmem_resp_0_bits_uop_ctrl_imm_sel_0 = io_dmem_resp_0_bits_uop_ctrl_imm_sel; // @[lsu.scala:201:7] wire [4:0] io_dmem_resp_0_bits_uop_ctrl_op_fcn_0 = io_dmem_resp_0_bits_uop_ctrl_op_fcn; // @[lsu.scala:201:7] wire io_dmem_resp_0_bits_uop_ctrl_fcn_dw_0 = io_dmem_resp_0_bits_uop_ctrl_fcn_dw; // @[lsu.scala:201:7] wire [2:0] io_dmem_resp_0_bits_uop_ctrl_csr_cmd_0 = io_dmem_resp_0_bits_uop_ctrl_csr_cmd; // @[lsu.scala:201:7] wire io_dmem_resp_0_bits_uop_ctrl_is_load_0 = io_dmem_resp_0_bits_uop_ctrl_is_load; // @[lsu.scala:201:7] wire io_dmem_resp_0_bits_uop_ctrl_is_sta_0 = io_dmem_resp_0_bits_uop_ctrl_is_sta; // @[lsu.scala:201:7] wire io_dmem_resp_0_bits_uop_ctrl_is_std_0 = io_dmem_resp_0_bits_uop_ctrl_is_std; // @[lsu.scala:201:7] wire [1:0] io_dmem_resp_0_bits_uop_iw_state_0 = io_dmem_resp_0_bits_uop_iw_state; // @[lsu.scala:201:7] wire io_dmem_resp_0_bits_uop_iw_p1_poisoned_0 = io_dmem_resp_0_bits_uop_iw_p1_poisoned; // @[lsu.scala:201:7] wire io_dmem_resp_0_bits_uop_iw_p2_poisoned_0 = io_dmem_resp_0_bits_uop_iw_p2_poisoned; // @[lsu.scala:201:7] wire io_dmem_resp_0_bits_uop_is_br_0 = io_dmem_resp_0_bits_uop_is_br; // @[lsu.scala:201:7] wire io_dmem_resp_0_bits_uop_is_jalr_0 = io_dmem_resp_0_bits_uop_is_jalr; // @[lsu.scala:201:7] wire io_dmem_resp_0_bits_uop_is_jal_0 = io_dmem_resp_0_bits_uop_is_jal; // @[lsu.scala:201:7] wire io_dmem_resp_0_bits_uop_is_sfb_0 = io_dmem_resp_0_bits_uop_is_sfb; // @[lsu.scala:201:7] wire [7:0] io_dmem_resp_0_bits_uop_br_mask_0 = io_dmem_resp_0_bits_uop_br_mask; // @[lsu.scala:201:7] wire [2:0] io_dmem_resp_0_bits_uop_br_tag_0 = io_dmem_resp_0_bits_uop_br_tag; // @[lsu.scala:201:7] wire [3:0] io_dmem_resp_0_bits_uop_ftq_idx_0 = io_dmem_resp_0_bits_uop_ftq_idx; // @[lsu.scala:201:7] wire io_dmem_resp_0_bits_uop_edge_inst_0 = io_dmem_resp_0_bits_uop_edge_inst; // @[lsu.scala:201:7] wire [5:0] io_dmem_resp_0_bits_uop_pc_lob_0 = io_dmem_resp_0_bits_uop_pc_lob; // @[lsu.scala:201:7] wire io_dmem_resp_0_bits_uop_taken_0 = io_dmem_resp_0_bits_uop_taken; // @[lsu.scala:201:7] wire [19:0] io_dmem_resp_0_bits_uop_imm_packed_0 = io_dmem_resp_0_bits_uop_imm_packed; // @[lsu.scala:201:7] wire [11:0] io_dmem_resp_0_bits_uop_csr_addr_0 = io_dmem_resp_0_bits_uop_csr_addr; // @[lsu.scala:201:7] wire [4:0] io_dmem_resp_0_bits_uop_rob_idx_0 = io_dmem_resp_0_bits_uop_rob_idx; // @[lsu.scala:201:7] wire [2:0] io_dmem_resp_0_bits_uop_ldq_idx_0 = io_dmem_resp_0_bits_uop_ldq_idx; // @[lsu.scala:201:7] wire [2:0] io_dmem_resp_0_bits_uop_stq_idx_0 = io_dmem_resp_0_bits_uop_stq_idx; // @[lsu.scala:201:7] wire [1:0] io_dmem_resp_0_bits_uop_rxq_idx_0 = io_dmem_resp_0_bits_uop_rxq_idx; // @[lsu.scala:201:7] wire [5:0] io_dmem_resp_0_bits_uop_pdst_0 = io_dmem_resp_0_bits_uop_pdst; // @[lsu.scala:201:7] wire [5:0] io_dmem_resp_0_bits_uop_prs1_0 = io_dmem_resp_0_bits_uop_prs1; // @[lsu.scala:201:7] wire [5:0] io_dmem_resp_0_bits_uop_prs2_0 = io_dmem_resp_0_bits_uop_prs2; // @[lsu.scala:201:7] wire [5:0] io_dmem_resp_0_bits_uop_prs3_0 = io_dmem_resp_0_bits_uop_prs3; // @[lsu.scala:201:7] wire [3:0] io_dmem_resp_0_bits_uop_ppred_0 = io_dmem_resp_0_bits_uop_ppred; // @[lsu.scala:201:7] wire io_dmem_resp_0_bits_uop_prs1_busy_0 = io_dmem_resp_0_bits_uop_prs1_busy; // @[lsu.scala:201:7] wire io_dmem_resp_0_bits_uop_prs2_busy_0 = io_dmem_resp_0_bits_uop_prs2_busy; // @[lsu.scala:201:7] wire io_dmem_resp_0_bits_uop_prs3_busy_0 = io_dmem_resp_0_bits_uop_prs3_busy; // @[lsu.scala:201:7] wire io_dmem_resp_0_bits_uop_ppred_busy_0 = io_dmem_resp_0_bits_uop_ppred_busy; // @[lsu.scala:201:7] wire [5:0] io_dmem_resp_0_bits_uop_stale_pdst_0 = io_dmem_resp_0_bits_uop_stale_pdst; // @[lsu.scala:201:7] wire io_dmem_resp_0_bits_uop_exception_0 = io_dmem_resp_0_bits_uop_exception; // @[lsu.scala:201:7] wire [63:0] io_dmem_resp_0_bits_uop_exc_cause_0 = io_dmem_resp_0_bits_uop_exc_cause; // @[lsu.scala:201:7] wire io_dmem_resp_0_bits_uop_bypassable_0 = io_dmem_resp_0_bits_uop_bypassable; // @[lsu.scala:201:7] wire [4:0] io_dmem_resp_0_bits_uop_mem_cmd_0 = io_dmem_resp_0_bits_uop_mem_cmd; // @[lsu.scala:201:7] wire [1:0] io_dmem_resp_0_bits_uop_mem_size_0 = io_dmem_resp_0_bits_uop_mem_size; // @[lsu.scala:201:7] wire io_dmem_resp_0_bits_uop_mem_signed_0 = io_dmem_resp_0_bits_uop_mem_signed; // @[lsu.scala:201:7] wire io_dmem_resp_0_bits_uop_is_fence_0 = io_dmem_resp_0_bits_uop_is_fence; // @[lsu.scala:201:7] wire io_dmem_resp_0_bits_uop_is_fencei_0 = io_dmem_resp_0_bits_uop_is_fencei; // @[lsu.scala:201:7] wire io_dmem_resp_0_bits_uop_is_amo_0 = io_dmem_resp_0_bits_uop_is_amo; // @[lsu.scala:201:7] wire io_dmem_resp_0_bits_uop_uses_ldq_0 = io_dmem_resp_0_bits_uop_uses_ldq; // @[lsu.scala:201:7] wire io_dmem_resp_0_bits_uop_uses_stq_0 = io_dmem_resp_0_bits_uop_uses_stq; // @[lsu.scala:201:7] wire io_dmem_resp_0_bits_uop_is_sys_pc2epc_0 = io_dmem_resp_0_bits_uop_is_sys_pc2epc; // @[lsu.scala:201:7] wire io_dmem_resp_0_bits_uop_is_unique_0 = io_dmem_resp_0_bits_uop_is_unique; // @[lsu.scala:201:7] wire io_dmem_resp_0_bits_uop_flush_on_commit_0 = io_dmem_resp_0_bits_uop_flush_on_commit; // @[lsu.scala:201:7] wire io_dmem_resp_0_bits_uop_ldst_is_rs1_0 = io_dmem_resp_0_bits_uop_ldst_is_rs1; // @[lsu.scala:201:7] wire [5:0] io_dmem_resp_0_bits_uop_ldst_0 = io_dmem_resp_0_bits_uop_ldst; // @[lsu.scala:201:7] wire [5:0] io_dmem_resp_0_bits_uop_lrs1_0 = io_dmem_resp_0_bits_uop_lrs1; // @[lsu.scala:201:7] wire [5:0] io_dmem_resp_0_bits_uop_lrs2_0 = io_dmem_resp_0_bits_uop_lrs2; // @[lsu.scala:201:7] wire [5:0] io_dmem_resp_0_bits_uop_lrs3_0 = io_dmem_resp_0_bits_uop_lrs3; // @[lsu.scala:201:7] wire io_dmem_resp_0_bits_uop_ldst_val_0 = io_dmem_resp_0_bits_uop_ldst_val; // @[lsu.scala:201:7] wire [1:0] io_dmem_resp_0_bits_uop_dst_rtype_0 = io_dmem_resp_0_bits_uop_dst_rtype; // @[lsu.scala:201:7] wire [1:0] io_dmem_resp_0_bits_uop_lrs1_rtype_0 = io_dmem_resp_0_bits_uop_lrs1_rtype; // @[lsu.scala:201:7] wire [1:0] io_dmem_resp_0_bits_uop_lrs2_rtype_0 = io_dmem_resp_0_bits_uop_lrs2_rtype; // @[lsu.scala:201:7] wire io_dmem_resp_0_bits_uop_frs3_en_0 = io_dmem_resp_0_bits_uop_frs3_en; // @[lsu.scala:201:7] wire io_dmem_resp_0_bits_uop_fp_val_0 = io_dmem_resp_0_bits_uop_fp_val; // @[lsu.scala:201:7] wire io_dmem_resp_0_bits_uop_fp_single_0 = io_dmem_resp_0_bits_uop_fp_single; // @[lsu.scala:201:7] wire io_dmem_resp_0_bits_uop_xcpt_pf_if_0 = io_dmem_resp_0_bits_uop_xcpt_pf_if; // @[lsu.scala:201:7] wire io_dmem_resp_0_bits_uop_xcpt_ae_if_0 = io_dmem_resp_0_bits_uop_xcpt_ae_if; // @[lsu.scala:201:7] wire io_dmem_resp_0_bits_uop_xcpt_ma_if_0 = io_dmem_resp_0_bits_uop_xcpt_ma_if; // @[lsu.scala:201:7] wire io_dmem_resp_0_bits_uop_bp_debug_if_0 = io_dmem_resp_0_bits_uop_bp_debug_if; // @[lsu.scala:201:7] wire io_dmem_resp_0_bits_uop_bp_xcpt_if_0 = io_dmem_resp_0_bits_uop_bp_xcpt_if; // @[lsu.scala:201:7] wire [1:0] io_dmem_resp_0_bits_uop_debug_fsrc_0 = io_dmem_resp_0_bits_uop_debug_fsrc; // @[lsu.scala:201:7] wire [1:0] io_dmem_resp_0_bits_uop_debug_tsrc_0 = io_dmem_resp_0_bits_uop_debug_tsrc; // @[lsu.scala:201:7] wire [63:0] io_dmem_resp_0_bits_data_0 = io_dmem_resp_0_bits_data; // @[lsu.scala:201:7] wire io_dmem_resp_0_bits_is_hella_0 = io_dmem_resp_0_bits_is_hella; // @[lsu.scala:201:7] wire io_dmem_nack_0_valid_0 = io_dmem_nack_0_valid; // @[lsu.scala:201:7] wire [6:0] io_dmem_nack_0_bits_uop_uopc_0 = io_dmem_nack_0_bits_uop_uopc; // @[lsu.scala:201:7] wire [31:0] io_dmem_nack_0_bits_uop_inst_0 = io_dmem_nack_0_bits_uop_inst; // @[lsu.scala:201:7] wire [31:0] io_dmem_nack_0_bits_uop_debug_inst_0 = io_dmem_nack_0_bits_uop_debug_inst; // @[lsu.scala:201:7] wire io_dmem_nack_0_bits_uop_is_rvc_0 = io_dmem_nack_0_bits_uop_is_rvc; // @[lsu.scala:201:7] wire [39:0] io_dmem_nack_0_bits_uop_debug_pc_0 = io_dmem_nack_0_bits_uop_debug_pc; // @[lsu.scala:201:7] wire [2:0] io_dmem_nack_0_bits_uop_iq_type_0 = io_dmem_nack_0_bits_uop_iq_type; // @[lsu.scala:201:7] wire [9:0] io_dmem_nack_0_bits_uop_fu_code_0 = io_dmem_nack_0_bits_uop_fu_code; // @[lsu.scala:201:7] wire [3:0] io_dmem_nack_0_bits_uop_ctrl_br_type_0 = io_dmem_nack_0_bits_uop_ctrl_br_type; // @[lsu.scala:201:7] wire [1:0] io_dmem_nack_0_bits_uop_ctrl_op1_sel_0 = io_dmem_nack_0_bits_uop_ctrl_op1_sel; // @[lsu.scala:201:7] wire [2:0] io_dmem_nack_0_bits_uop_ctrl_op2_sel_0 = io_dmem_nack_0_bits_uop_ctrl_op2_sel; // @[lsu.scala:201:7] wire [2:0] io_dmem_nack_0_bits_uop_ctrl_imm_sel_0 = io_dmem_nack_0_bits_uop_ctrl_imm_sel; // @[lsu.scala:201:7] wire [4:0] io_dmem_nack_0_bits_uop_ctrl_op_fcn_0 = io_dmem_nack_0_bits_uop_ctrl_op_fcn; // @[lsu.scala:201:7] wire io_dmem_nack_0_bits_uop_ctrl_fcn_dw_0 = io_dmem_nack_0_bits_uop_ctrl_fcn_dw; // @[lsu.scala:201:7] wire [2:0] io_dmem_nack_0_bits_uop_ctrl_csr_cmd_0 = io_dmem_nack_0_bits_uop_ctrl_csr_cmd; // @[lsu.scala:201:7] wire io_dmem_nack_0_bits_uop_ctrl_is_load_0 = io_dmem_nack_0_bits_uop_ctrl_is_load; // @[lsu.scala:201:7] wire io_dmem_nack_0_bits_uop_ctrl_is_sta_0 = io_dmem_nack_0_bits_uop_ctrl_is_sta; // @[lsu.scala:201:7] wire io_dmem_nack_0_bits_uop_ctrl_is_std_0 = io_dmem_nack_0_bits_uop_ctrl_is_std; // @[lsu.scala:201:7] wire [1:0] io_dmem_nack_0_bits_uop_iw_state_0 = io_dmem_nack_0_bits_uop_iw_state; // @[lsu.scala:201:7] wire io_dmem_nack_0_bits_uop_iw_p1_poisoned_0 = io_dmem_nack_0_bits_uop_iw_p1_poisoned; // @[lsu.scala:201:7] wire io_dmem_nack_0_bits_uop_iw_p2_poisoned_0 = io_dmem_nack_0_bits_uop_iw_p2_poisoned; // @[lsu.scala:201:7] wire io_dmem_nack_0_bits_uop_is_br_0 = io_dmem_nack_0_bits_uop_is_br; // @[lsu.scala:201:7] wire io_dmem_nack_0_bits_uop_is_jalr_0 = io_dmem_nack_0_bits_uop_is_jalr; // @[lsu.scala:201:7] wire io_dmem_nack_0_bits_uop_is_jal_0 = io_dmem_nack_0_bits_uop_is_jal; // @[lsu.scala:201:7] wire io_dmem_nack_0_bits_uop_is_sfb_0 = io_dmem_nack_0_bits_uop_is_sfb; // @[lsu.scala:201:7] wire [7:0] io_dmem_nack_0_bits_uop_br_mask_0 = io_dmem_nack_0_bits_uop_br_mask; // @[lsu.scala:201:7] wire [2:0] io_dmem_nack_0_bits_uop_br_tag_0 = io_dmem_nack_0_bits_uop_br_tag; // @[lsu.scala:201:7] wire [3:0] io_dmem_nack_0_bits_uop_ftq_idx_0 = io_dmem_nack_0_bits_uop_ftq_idx; // @[lsu.scala:201:7] wire io_dmem_nack_0_bits_uop_edge_inst_0 = io_dmem_nack_0_bits_uop_edge_inst; // @[lsu.scala:201:7] wire [5:0] io_dmem_nack_0_bits_uop_pc_lob_0 = io_dmem_nack_0_bits_uop_pc_lob; // @[lsu.scala:201:7] wire io_dmem_nack_0_bits_uop_taken_0 = io_dmem_nack_0_bits_uop_taken; // @[lsu.scala:201:7] wire [19:0] io_dmem_nack_0_bits_uop_imm_packed_0 = io_dmem_nack_0_bits_uop_imm_packed; // @[lsu.scala:201:7] wire [11:0] io_dmem_nack_0_bits_uop_csr_addr_0 = io_dmem_nack_0_bits_uop_csr_addr; // @[lsu.scala:201:7] wire [4:0] io_dmem_nack_0_bits_uop_rob_idx_0 = io_dmem_nack_0_bits_uop_rob_idx; // @[lsu.scala:201:7] wire [2:0] io_dmem_nack_0_bits_uop_ldq_idx_0 = io_dmem_nack_0_bits_uop_ldq_idx; // @[lsu.scala:201:7] wire [2:0] io_dmem_nack_0_bits_uop_stq_idx_0 = io_dmem_nack_0_bits_uop_stq_idx; // @[lsu.scala:201:7] wire [1:0] io_dmem_nack_0_bits_uop_rxq_idx_0 = io_dmem_nack_0_bits_uop_rxq_idx; // @[lsu.scala:201:7] wire [5:0] io_dmem_nack_0_bits_uop_pdst_0 = io_dmem_nack_0_bits_uop_pdst; // @[lsu.scala:201:7] wire [5:0] io_dmem_nack_0_bits_uop_prs1_0 = io_dmem_nack_0_bits_uop_prs1; // @[lsu.scala:201:7] wire [5:0] io_dmem_nack_0_bits_uop_prs2_0 = io_dmem_nack_0_bits_uop_prs2; // @[lsu.scala:201:7] wire [5:0] io_dmem_nack_0_bits_uop_prs3_0 = io_dmem_nack_0_bits_uop_prs3; // @[lsu.scala:201:7] wire [3:0] io_dmem_nack_0_bits_uop_ppred_0 = io_dmem_nack_0_bits_uop_ppred; // @[lsu.scala:201:7] wire io_dmem_nack_0_bits_uop_prs1_busy_0 = io_dmem_nack_0_bits_uop_prs1_busy; // @[lsu.scala:201:7] wire io_dmem_nack_0_bits_uop_prs2_busy_0 = io_dmem_nack_0_bits_uop_prs2_busy; // @[lsu.scala:201:7] wire io_dmem_nack_0_bits_uop_prs3_busy_0 = io_dmem_nack_0_bits_uop_prs3_busy; // @[lsu.scala:201:7] wire io_dmem_nack_0_bits_uop_ppred_busy_0 = io_dmem_nack_0_bits_uop_ppred_busy; // @[lsu.scala:201:7] wire [5:0] io_dmem_nack_0_bits_uop_stale_pdst_0 = io_dmem_nack_0_bits_uop_stale_pdst; // @[lsu.scala:201:7] wire io_dmem_nack_0_bits_uop_exception_0 = io_dmem_nack_0_bits_uop_exception; // @[lsu.scala:201:7] wire [63:0] io_dmem_nack_0_bits_uop_exc_cause_0 = io_dmem_nack_0_bits_uop_exc_cause; // @[lsu.scala:201:7] wire io_dmem_nack_0_bits_uop_bypassable_0 = io_dmem_nack_0_bits_uop_bypassable; // @[lsu.scala:201:7] wire [4:0] io_dmem_nack_0_bits_uop_mem_cmd_0 = io_dmem_nack_0_bits_uop_mem_cmd; // @[lsu.scala:201:7] wire [1:0] io_dmem_nack_0_bits_uop_mem_size_0 = io_dmem_nack_0_bits_uop_mem_size; // @[lsu.scala:201:7] wire io_dmem_nack_0_bits_uop_mem_signed_0 = io_dmem_nack_0_bits_uop_mem_signed; // @[lsu.scala:201:7] wire io_dmem_nack_0_bits_uop_is_fence_0 = io_dmem_nack_0_bits_uop_is_fence; // @[lsu.scala:201:7] wire io_dmem_nack_0_bits_uop_is_fencei_0 = io_dmem_nack_0_bits_uop_is_fencei; // @[lsu.scala:201:7] wire io_dmem_nack_0_bits_uop_is_amo_0 = io_dmem_nack_0_bits_uop_is_amo; // @[lsu.scala:201:7] wire io_dmem_nack_0_bits_uop_uses_ldq_0 = io_dmem_nack_0_bits_uop_uses_ldq; // @[lsu.scala:201:7] wire io_dmem_nack_0_bits_uop_uses_stq_0 = io_dmem_nack_0_bits_uop_uses_stq; // @[lsu.scala:201:7] wire io_dmem_nack_0_bits_uop_is_sys_pc2epc_0 = io_dmem_nack_0_bits_uop_is_sys_pc2epc; // @[lsu.scala:201:7] wire io_dmem_nack_0_bits_uop_is_unique_0 = io_dmem_nack_0_bits_uop_is_unique; // @[lsu.scala:201:7] wire io_dmem_nack_0_bits_uop_flush_on_commit_0 = io_dmem_nack_0_bits_uop_flush_on_commit; // @[lsu.scala:201:7] wire io_dmem_nack_0_bits_uop_ldst_is_rs1_0 = io_dmem_nack_0_bits_uop_ldst_is_rs1; // @[lsu.scala:201:7] wire [5:0] io_dmem_nack_0_bits_uop_ldst_0 = io_dmem_nack_0_bits_uop_ldst; // @[lsu.scala:201:7] wire [5:0] io_dmem_nack_0_bits_uop_lrs1_0 = io_dmem_nack_0_bits_uop_lrs1; // @[lsu.scala:201:7] wire [5:0] io_dmem_nack_0_bits_uop_lrs2_0 = io_dmem_nack_0_bits_uop_lrs2; // @[lsu.scala:201:7] wire [5:0] io_dmem_nack_0_bits_uop_lrs3_0 = io_dmem_nack_0_bits_uop_lrs3; // @[lsu.scala:201:7] wire io_dmem_nack_0_bits_uop_ldst_val_0 = io_dmem_nack_0_bits_uop_ldst_val; // @[lsu.scala:201:7] wire [1:0] io_dmem_nack_0_bits_uop_dst_rtype_0 = io_dmem_nack_0_bits_uop_dst_rtype; // @[lsu.scala:201:7] wire [1:0] io_dmem_nack_0_bits_uop_lrs1_rtype_0 = io_dmem_nack_0_bits_uop_lrs1_rtype; // @[lsu.scala:201:7] wire [1:0] io_dmem_nack_0_bits_uop_lrs2_rtype_0 = io_dmem_nack_0_bits_uop_lrs2_rtype; // @[lsu.scala:201:7] wire io_dmem_nack_0_bits_uop_frs3_en_0 = io_dmem_nack_0_bits_uop_frs3_en; // @[lsu.scala:201:7] wire io_dmem_nack_0_bits_uop_fp_val_0 = io_dmem_nack_0_bits_uop_fp_val; // @[lsu.scala:201:7] wire io_dmem_nack_0_bits_uop_fp_single_0 = io_dmem_nack_0_bits_uop_fp_single; // @[lsu.scala:201:7] wire io_dmem_nack_0_bits_uop_xcpt_pf_if_0 = io_dmem_nack_0_bits_uop_xcpt_pf_if; // @[lsu.scala:201:7] wire io_dmem_nack_0_bits_uop_xcpt_ae_if_0 = io_dmem_nack_0_bits_uop_xcpt_ae_if; // @[lsu.scala:201:7] wire io_dmem_nack_0_bits_uop_xcpt_ma_if_0 = io_dmem_nack_0_bits_uop_xcpt_ma_if; // @[lsu.scala:201:7] wire io_dmem_nack_0_bits_uop_bp_debug_if_0 = io_dmem_nack_0_bits_uop_bp_debug_if; // @[lsu.scala:201:7] wire io_dmem_nack_0_bits_uop_bp_xcpt_if_0 = io_dmem_nack_0_bits_uop_bp_xcpt_if; // @[lsu.scala:201:7] wire [1:0] io_dmem_nack_0_bits_uop_debug_fsrc_0 = io_dmem_nack_0_bits_uop_debug_fsrc; // @[lsu.scala:201:7] wire [1:0] io_dmem_nack_0_bits_uop_debug_tsrc_0 = io_dmem_nack_0_bits_uop_debug_tsrc; // @[lsu.scala:201:7] wire [39:0] io_dmem_nack_0_bits_addr_0 = io_dmem_nack_0_bits_addr; // @[lsu.scala:201:7] wire [63:0] io_dmem_nack_0_bits_data_0 = io_dmem_nack_0_bits_data; // @[lsu.scala:201:7] wire io_dmem_nack_0_bits_is_hella_0 = io_dmem_nack_0_bits_is_hella; // @[lsu.scala:201:7] wire io_dmem_release_valid_0 = io_dmem_release_valid; // @[lsu.scala:201:7] wire [2:0] io_dmem_release_bits_opcode_0 = io_dmem_release_bits_opcode; // @[lsu.scala:201:7] wire [2:0] io_dmem_release_bits_param_0 = io_dmem_release_bits_param; // @[lsu.scala:201:7] wire [3:0] io_dmem_release_bits_size_0 = io_dmem_release_bits_size; // @[lsu.scala:201:7] wire [1:0] io_dmem_release_bits_source_0 = io_dmem_release_bits_source; // @[lsu.scala:201:7] wire [31:0] io_dmem_release_bits_address_0 = io_dmem_release_bits_address; // @[lsu.scala:201:7] wire [63:0] io_dmem_release_bits_data_0 = io_dmem_release_bits_data; // @[lsu.scala:201:7] wire io_dmem_ordered_0 = io_dmem_ordered; // @[lsu.scala:201:7] wire io_dmem_perf_acquire_0 = io_dmem_perf_acquire; // @[lsu.scala:201:7] wire io_dmem_perf_release_0 = io_dmem_perf_release; // @[lsu.scala:201:7] wire io_hellacache_req_valid_0 = io_hellacache_req_valid; // @[lsu.scala:201:7] wire [39:0] io_hellacache_req_bits_addr_0 = io_hellacache_req_bits_addr; // @[lsu.scala:201:7] wire io_hellacache_req_bits_dv_0 = io_hellacache_req_bits_dv; // @[lsu.scala:201:7] wire io_hellacache_s1_kill_0 = io_hellacache_s1_kill; // @[lsu.scala:201:7] wire [15:0] io_ptw_ptbr_asid = 16'h0; // @[lsu.scala:201:7] wire [15:0] io_ptw_hgatp_asid = 16'h0; // @[lsu.scala:201:7] wire [15:0] io_ptw_vsatp_asid = 16'h0; // @[lsu.scala:201:7] wire [15:0] _dmem_req_0_bits_data_T_17 = 16'h0; // @[AMOALU.scala:29:32] wire [15:0] _dmem_req_0_bits_data_T_21 = 16'h0; // @[AMOALU.scala:29:69] wire [31:0] io_ptw_status_isa = 32'h14112D; // @[lsu.scala:201:7] wire [22:0] io_ptw_status_zero2 = 23'h0; // @[lsu.scala:201:7] wire [22:0] io_ptw_gstatus_zero2 = 23'h0; // @[lsu.scala:201:7] wire io_ptw_req_bits_bits_need_gpa = 1'h0; // @[lsu.scala:201:7] wire io_ptw_req_bits_bits_vstage1 = 1'h0; // @[lsu.scala:201:7] wire io_ptw_req_bits_bits_stage2 = 1'h0; // @[lsu.scala:201:7] wire io_ptw_resp_bits_fragmented_superpage = 1'h0; // @[lsu.scala:201:7] wire io_ptw_status_mbe = 1'h0; // @[lsu.scala:201:7] wire io_ptw_status_sbe = 1'h0; // @[lsu.scala:201:7] wire io_ptw_status_sd_rv32 = 1'h0; // @[lsu.scala:201:7] wire io_ptw_status_ube = 1'h0; // @[lsu.scala:201:7] wire io_ptw_status_upie = 1'h0; // @[lsu.scala:201:7] wire io_ptw_status_hie = 1'h0; // @[lsu.scala:201:7] wire io_ptw_status_uie = 1'h0; // @[lsu.scala:201:7] wire io_ptw_hstatus_vtsr = 1'h0; // @[lsu.scala:201:7] wire io_ptw_hstatus_vtw = 1'h0; // @[lsu.scala:201:7] wire io_ptw_hstatus_vtvm = 1'h0; // @[lsu.scala:201:7] wire io_ptw_hstatus_hu = 1'h0; // @[lsu.scala:201:7] wire io_ptw_hstatus_spvp = 1'h0; // @[lsu.scala:201:7] wire io_ptw_hstatus_spv = 1'h0; // @[lsu.scala:201:7] wire io_ptw_hstatus_gva = 1'h0; // @[lsu.scala:201:7] wire io_ptw_hstatus_vsbe = 1'h0; // @[lsu.scala:201:7] wire io_ptw_gstatus_debug = 1'h0; // @[lsu.scala:201:7] wire io_ptw_gstatus_cease = 1'h0; // @[lsu.scala:201:7] wire io_ptw_gstatus_wfi = 1'h0; // @[lsu.scala:201:7] wire io_ptw_gstatus_dv = 1'h0; // @[lsu.scala:201:7] wire io_ptw_gstatus_v = 1'h0; // @[lsu.scala:201:7] wire io_ptw_gstatus_sd = 1'h0; // @[lsu.scala:201:7] wire io_ptw_gstatus_mpv = 1'h0; // @[lsu.scala:201:7] wire io_ptw_gstatus_gva = 1'h0; // @[lsu.scala:201:7] wire io_ptw_gstatus_mbe = 1'h0; // @[lsu.scala:201:7] wire io_ptw_gstatus_sbe = 1'h0; // @[lsu.scala:201:7] wire io_ptw_gstatus_sd_rv32 = 1'h0; // @[lsu.scala:201:7] wire io_ptw_gstatus_tsr = 1'h0; // @[lsu.scala:201:7] wire io_ptw_gstatus_tw = 1'h0; // @[lsu.scala:201:7] wire io_ptw_gstatus_tvm = 1'h0; // @[lsu.scala:201:7] wire io_ptw_gstatus_mxr = 1'h0; // @[lsu.scala:201:7] wire io_ptw_gstatus_sum = 1'h0; // @[lsu.scala:201:7] wire io_ptw_gstatus_mprv = 1'h0; // @[lsu.scala:201:7] wire io_ptw_gstatus_spp = 1'h0; // @[lsu.scala:201:7] wire io_ptw_gstatus_mpie = 1'h0; // @[lsu.scala:201:7] wire io_ptw_gstatus_ube = 1'h0; // @[lsu.scala:201:7] wire io_ptw_gstatus_spie = 1'h0; // @[lsu.scala:201:7] wire io_ptw_gstatus_upie = 1'h0; // @[lsu.scala:201:7] wire io_ptw_gstatus_mie = 1'h0; // @[lsu.scala:201:7] wire io_ptw_gstatus_hie = 1'h0; // @[lsu.scala:201:7] wire io_ptw_gstatus_sie = 1'h0; // @[lsu.scala:201:7] wire io_ptw_gstatus_uie = 1'h0; // @[lsu.scala:201:7] wire io_ptw_customCSRs_csrs_0_ren = 1'h0; // @[lsu.scala:201:7] wire io_ptw_customCSRs_csrs_0_wen = 1'h0; // @[lsu.scala:201:7] wire io_ptw_customCSRs_csrs_0_stall = 1'h0; // @[lsu.scala:201:7] wire io_ptw_customCSRs_csrs_0_set = 1'h0; // @[lsu.scala:201:7] wire io_ptw_customCSRs_csrs_1_ren = 1'h0; // @[lsu.scala:201:7] wire io_ptw_customCSRs_csrs_1_wen = 1'h0; // @[lsu.scala:201:7] wire io_ptw_customCSRs_csrs_1_stall = 1'h0; // @[lsu.scala:201:7] wire io_ptw_customCSRs_csrs_1_set = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_req_bits_predicated = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_req_bits_fflags_valid = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_req_bits_fflags_bits_uop_is_rvc = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_req_bits_fflags_bits_uop_ctrl_fcn_dw = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_req_bits_fflags_bits_uop_ctrl_is_load = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_req_bits_fflags_bits_uop_ctrl_is_sta = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_req_bits_fflags_bits_uop_ctrl_is_std = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_req_bits_fflags_bits_uop_iw_p1_poisoned = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_req_bits_fflags_bits_uop_iw_p2_poisoned = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_req_bits_fflags_bits_uop_is_br = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_req_bits_fflags_bits_uop_is_jalr = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_req_bits_fflags_bits_uop_is_jal = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_req_bits_fflags_bits_uop_is_sfb = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_req_bits_fflags_bits_uop_edge_inst = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_req_bits_fflags_bits_uop_taken = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_req_bits_fflags_bits_uop_prs1_busy = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_req_bits_fflags_bits_uop_prs2_busy = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_req_bits_fflags_bits_uop_prs3_busy = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_req_bits_fflags_bits_uop_ppred_busy = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_req_bits_fflags_bits_uop_exception = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_req_bits_fflags_bits_uop_bypassable = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_req_bits_fflags_bits_uop_mem_signed = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_req_bits_fflags_bits_uop_is_fence = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_req_bits_fflags_bits_uop_is_fencei = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_req_bits_fflags_bits_uop_is_amo = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_req_bits_fflags_bits_uop_uses_ldq = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_req_bits_fflags_bits_uop_uses_stq = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_req_bits_fflags_bits_uop_is_sys_pc2epc = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_req_bits_fflags_bits_uop_is_unique = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_req_bits_fflags_bits_uop_flush_on_commit = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_req_bits_fflags_bits_uop_ldst_is_rs1 = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_req_bits_fflags_bits_uop_ldst_val = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_req_bits_fflags_bits_uop_frs3_en = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_req_bits_fflags_bits_uop_fp_val = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_req_bits_fflags_bits_uop_fp_single = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_req_bits_fflags_bits_uop_xcpt_pf_if = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_req_bits_fflags_bits_uop_xcpt_ae_if = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_req_bits_fflags_bits_uop_xcpt_ma_if = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_req_bits_fflags_bits_uop_bp_debug_if = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_req_bits_fflags_bits_uop_bp_xcpt_if = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_req_bits_sfence_bits_hv = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_req_bits_sfence_bits_hg = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_iresp_bits_predicated = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_iresp_bits_fflags_valid = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_iresp_bits_fflags_bits_uop_is_rvc = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_iresp_bits_fflags_bits_uop_ctrl_fcn_dw = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_iresp_bits_fflags_bits_uop_ctrl_is_load = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_iresp_bits_fflags_bits_uop_ctrl_is_sta = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_iresp_bits_fflags_bits_uop_ctrl_is_std = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_iresp_bits_fflags_bits_uop_iw_p1_poisoned = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_iresp_bits_fflags_bits_uop_iw_p2_poisoned = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_iresp_bits_fflags_bits_uop_is_br = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_iresp_bits_fflags_bits_uop_is_jalr = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_iresp_bits_fflags_bits_uop_is_jal = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_iresp_bits_fflags_bits_uop_is_sfb = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_iresp_bits_fflags_bits_uop_edge_inst = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_iresp_bits_fflags_bits_uop_taken = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_iresp_bits_fflags_bits_uop_prs1_busy = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_iresp_bits_fflags_bits_uop_prs2_busy = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_iresp_bits_fflags_bits_uop_prs3_busy = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_iresp_bits_fflags_bits_uop_ppred_busy = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_iresp_bits_fflags_bits_uop_exception = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_iresp_bits_fflags_bits_uop_bypassable = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_iresp_bits_fflags_bits_uop_mem_signed = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_iresp_bits_fflags_bits_uop_is_fence = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_iresp_bits_fflags_bits_uop_is_fencei = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_iresp_bits_fflags_bits_uop_is_amo = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_iresp_bits_fflags_bits_uop_uses_ldq = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_iresp_bits_fflags_bits_uop_uses_stq = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_iresp_bits_fflags_bits_uop_is_sys_pc2epc = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_iresp_bits_fflags_bits_uop_is_unique = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_iresp_bits_fflags_bits_uop_flush_on_commit = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_iresp_bits_fflags_bits_uop_ldst_is_rs1 = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_iresp_bits_fflags_bits_uop_ldst_val = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_iresp_bits_fflags_bits_uop_frs3_en = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_iresp_bits_fflags_bits_uop_fp_val = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_iresp_bits_fflags_bits_uop_fp_single = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_iresp_bits_fflags_bits_uop_xcpt_pf_if = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_iresp_bits_fflags_bits_uop_xcpt_ae_if = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_iresp_bits_fflags_bits_uop_xcpt_ma_if = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_iresp_bits_fflags_bits_uop_bp_debug_if = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_iresp_bits_fflags_bits_uop_bp_xcpt_if = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_fresp_bits_uop_ppred_busy_0 = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_fresp_bits_predicated = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_fresp_bits_fflags_valid = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_fresp_bits_fflags_bits_uop_is_rvc = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_fresp_bits_fflags_bits_uop_ctrl_fcn_dw = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_fresp_bits_fflags_bits_uop_ctrl_is_load = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_fresp_bits_fflags_bits_uop_ctrl_is_sta = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_fresp_bits_fflags_bits_uop_ctrl_is_std = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_fresp_bits_fflags_bits_uop_iw_p1_poisoned = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_fresp_bits_fflags_bits_uop_iw_p2_poisoned = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_fresp_bits_fflags_bits_uop_is_br = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_fresp_bits_fflags_bits_uop_is_jalr = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_fresp_bits_fflags_bits_uop_is_jal = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_fresp_bits_fflags_bits_uop_is_sfb = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_fresp_bits_fflags_bits_uop_edge_inst = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_fresp_bits_fflags_bits_uop_taken = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_fresp_bits_fflags_bits_uop_prs1_busy = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_fresp_bits_fflags_bits_uop_prs2_busy = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_fresp_bits_fflags_bits_uop_prs3_busy = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_fresp_bits_fflags_bits_uop_ppred_busy = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_fresp_bits_fflags_bits_uop_exception = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_fresp_bits_fflags_bits_uop_bypassable = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_fresp_bits_fflags_bits_uop_mem_signed = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_fresp_bits_fflags_bits_uop_is_fence = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_fresp_bits_fflags_bits_uop_is_fencei = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_fresp_bits_fflags_bits_uop_is_amo = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_fresp_bits_fflags_bits_uop_uses_ldq = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_fresp_bits_fflags_bits_uop_uses_stq = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_fresp_bits_fflags_bits_uop_is_sys_pc2epc = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_fresp_bits_fflags_bits_uop_is_unique = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_fresp_bits_fflags_bits_uop_flush_on_commit = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_fresp_bits_fflags_bits_uop_ldst_is_rs1 = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_fresp_bits_fflags_bits_uop_ldst_val = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_fresp_bits_fflags_bits_uop_frs3_en = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_fresp_bits_fflags_bits_uop_fp_val = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_fresp_bits_fflags_bits_uop_fp_single = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_fresp_bits_fflags_bits_uop_xcpt_pf_if = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_fresp_bits_fflags_bits_uop_xcpt_ae_if = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_fresp_bits_fflags_bits_uop_xcpt_ma_if = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_fresp_bits_fflags_bits_uop_bp_debug_if = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_fresp_bits_fflags_bits_uop_bp_xcpt_if = 1'h0; // @[lsu.scala:201:7] wire io_core_dis_uops_0_bits_ppred_busy = 1'h0; // @[lsu.scala:201:7] wire io_core_clr_unsafe_0_valid = 1'h0; // @[lsu.scala:201:7] wire io_dmem_release_bits_corrupt = 1'h0; // @[lsu.scala:201:7] wire io_hellacache_req_bits_signed = 1'h0; // @[lsu.scala:201:7] wire io_hellacache_req_bits_no_resp = 1'h0; // @[lsu.scala:201:7] wire io_hellacache_req_bits_no_alloc = 1'h0; // @[lsu.scala:201:7] wire io_hellacache_req_bits_no_xcpt = 1'h0; // @[lsu.scala:201:7] wire io_hellacache_s2_nack_cause_raw = 1'h0; // @[lsu.scala:201:7] wire io_hellacache_s2_kill = 1'h0; // @[lsu.scala:201:7] wire io_hellacache_s2_uncached = 1'h0; // @[lsu.scala:201:7] wire io_hellacache_resp_bits_signed = 1'h0; // @[lsu.scala:201:7] wire io_hellacache_resp_bits_dv = 1'h0; // @[lsu.scala:201:7] wire io_hellacache_resp_bits_replay = 1'h0; // @[lsu.scala:201:7] wire io_hellacache_resp_bits_has_data = 1'h0; // @[lsu.scala:201:7] wire io_hellacache_replay_next = 1'h0; // @[lsu.scala:201:7] wire io_hellacache_s2_gpa_is_pte = 1'h0; // @[lsu.scala:201:7] wire io_hellacache_ordered = 1'h0; // @[lsu.scala:201:7] wire io_hellacache_perf_acquire = 1'h0; // @[lsu.scala:201:7] wire io_hellacache_perf_release = 1'h0; // @[lsu.scala:201:7] wire io_hellacache_perf_grant = 1'h0; // @[lsu.scala:201:7] wire io_hellacache_perf_tlbMiss = 1'h0; // @[lsu.scala:201:7] wire io_hellacache_perf_blocked = 1'h0; // @[lsu.scala:201:7] wire io_hellacache_perf_canAcceptStoreThenLoad = 1'h0; // @[lsu.scala:201:7] wire io_hellacache_perf_canAcceptStoreThenRMW = 1'h0; // @[lsu.scala:201:7] wire io_hellacache_perf_canAcceptLoadThenLoad = 1'h0; // @[lsu.scala:201:7] wire io_hellacache_perf_storeBufferEmptyAfterLoad = 1'h0; // @[lsu.scala:201:7] wire io_hellacache_perf_storeBufferEmptyAfterStore = 1'h0; // @[lsu.scala:201:7] wire io_hellacache_keep_clock_enabled = 1'h0; // @[lsu.scala:201:7] wire io_hellacache_clock_enabled = 1'h0; // @[lsu.scala:201:7] wire _exe_req_WIRE_0_bits_predicated = 1'h0; // @[lsu.scala:383:33] wire _exe_req_WIRE_0_bits_fflags_valid = 1'h0; // @[lsu.scala:383:33] wire _exe_req_WIRE_0_bits_fflags_bits_uop_is_rvc = 1'h0; // @[lsu.scala:383:33] wire _exe_req_WIRE_0_bits_fflags_bits_uop_ctrl_fcn_dw = 1'h0; // @[lsu.scala:383:33] wire _exe_req_WIRE_0_bits_fflags_bits_uop_ctrl_is_load = 1'h0; // @[lsu.scala:383:33] wire _exe_req_WIRE_0_bits_fflags_bits_uop_ctrl_is_sta = 1'h0; // @[lsu.scala:383:33] wire _exe_req_WIRE_0_bits_fflags_bits_uop_ctrl_is_std = 1'h0; // @[lsu.scala:383:33] wire _exe_req_WIRE_0_bits_fflags_bits_uop_iw_p1_poisoned = 1'h0; // @[lsu.scala:383:33] wire _exe_req_WIRE_0_bits_fflags_bits_uop_iw_p2_poisoned = 1'h0; // @[lsu.scala:383:33] wire _exe_req_WIRE_0_bits_fflags_bits_uop_is_br = 1'h0; // @[lsu.scala:383:33] wire _exe_req_WIRE_0_bits_fflags_bits_uop_is_jalr = 1'h0; // @[lsu.scala:383:33] wire _exe_req_WIRE_0_bits_fflags_bits_uop_is_jal = 1'h0; // @[lsu.scala:383:33] wire _exe_req_WIRE_0_bits_fflags_bits_uop_is_sfb = 1'h0; // @[lsu.scala:383:33] wire _exe_req_WIRE_0_bits_fflags_bits_uop_edge_inst = 1'h0; // @[lsu.scala:383:33] wire _exe_req_WIRE_0_bits_fflags_bits_uop_taken = 1'h0; // @[lsu.scala:383:33] wire _exe_req_WIRE_0_bits_fflags_bits_uop_prs1_busy = 1'h0; // @[lsu.scala:383:33] wire _exe_req_WIRE_0_bits_fflags_bits_uop_prs2_busy = 1'h0; // @[lsu.scala:383:33] wire _exe_req_WIRE_0_bits_fflags_bits_uop_prs3_busy = 1'h0; // @[lsu.scala:383:33] wire _exe_req_WIRE_0_bits_fflags_bits_uop_ppred_busy = 1'h0; // @[lsu.scala:383:33] wire _exe_req_WIRE_0_bits_fflags_bits_uop_exception = 1'h0; // @[lsu.scala:383:33] wire _exe_req_WIRE_0_bits_fflags_bits_uop_bypassable = 1'h0; // @[lsu.scala:383:33] wire _exe_req_WIRE_0_bits_fflags_bits_uop_mem_signed = 1'h0; // @[lsu.scala:383:33] wire _exe_req_WIRE_0_bits_fflags_bits_uop_is_fence = 1'h0; // @[lsu.scala:383:33] wire _exe_req_WIRE_0_bits_fflags_bits_uop_is_fencei = 1'h0; // @[lsu.scala:383:33] wire _exe_req_WIRE_0_bits_fflags_bits_uop_is_amo = 1'h0; // @[lsu.scala:383:33] wire _exe_req_WIRE_0_bits_fflags_bits_uop_uses_ldq = 1'h0; // @[lsu.scala:383:33] wire _exe_req_WIRE_0_bits_fflags_bits_uop_uses_stq = 1'h0; // @[lsu.scala:383:33] wire _exe_req_WIRE_0_bits_fflags_bits_uop_is_sys_pc2epc = 1'h0; // @[lsu.scala:383:33] wire _exe_req_WIRE_0_bits_fflags_bits_uop_is_unique = 1'h0; // @[lsu.scala:383:33] wire _exe_req_WIRE_0_bits_fflags_bits_uop_flush_on_commit = 1'h0; // @[lsu.scala:383:33] wire _exe_req_WIRE_0_bits_fflags_bits_uop_ldst_is_rs1 = 1'h0; // @[lsu.scala:383:33] wire _exe_req_WIRE_0_bits_fflags_bits_uop_ldst_val = 1'h0; // @[lsu.scala:383:33] wire _exe_req_WIRE_0_bits_fflags_bits_uop_frs3_en = 1'h0; // @[lsu.scala:383:33] wire _exe_req_WIRE_0_bits_fflags_bits_uop_fp_val = 1'h0; // @[lsu.scala:383:33] wire _exe_req_WIRE_0_bits_fflags_bits_uop_fp_single = 1'h0; // @[lsu.scala:383:33] wire _exe_req_WIRE_0_bits_fflags_bits_uop_xcpt_pf_if = 1'h0; // @[lsu.scala:383:33] wire _exe_req_WIRE_0_bits_fflags_bits_uop_xcpt_ae_if = 1'h0; // @[lsu.scala:383:33] wire _exe_req_WIRE_0_bits_fflags_bits_uop_xcpt_ma_if = 1'h0; // @[lsu.scala:383:33] wire _exe_req_WIRE_0_bits_fflags_bits_uop_bp_debug_if = 1'h0; // @[lsu.scala:383:33] wire _exe_req_WIRE_0_bits_fflags_bits_uop_bp_xcpt_if = 1'h0; // @[lsu.scala:383:33] wire _exe_req_WIRE_0_bits_sfence_bits_hv = 1'h0; // @[lsu.scala:383:33] wire _exe_req_WIRE_0_bits_sfence_bits_hg = 1'h0; // @[lsu.scala:383:33] wire exe_req_0_bits_predicated = 1'h0; // @[lsu.scala:383:25] wire exe_req_0_bits_fflags_valid = 1'h0; // @[lsu.scala:383:25] wire exe_req_0_bits_fflags_bits_uop_is_rvc = 1'h0; // @[lsu.scala:383:25] wire exe_req_0_bits_fflags_bits_uop_ctrl_fcn_dw = 1'h0; // @[lsu.scala:383:25] wire exe_req_0_bits_fflags_bits_uop_ctrl_is_load = 1'h0; // @[lsu.scala:383:25] wire exe_req_0_bits_fflags_bits_uop_ctrl_is_sta = 1'h0; // @[lsu.scala:383:25] wire exe_req_0_bits_fflags_bits_uop_ctrl_is_std = 1'h0; // @[lsu.scala:383:25] wire exe_req_0_bits_fflags_bits_uop_iw_p1_poisoned = 1'h0; // @[lsu.scala:383:25] wire exe_req_0_bits_fflags_bits_uop_iw_p2_poisoned = 1'h0; // @[lsu.scala:383:25] wire exe_req_0_bits_fflags_bits_uop_is_br = 1'h0; // @[lsu.scala:383:25] wire exe_req_0_bits_fflags_bits_uop_is_jalr = 1'h0; // @[lsu.scala:383:25] wire exe_req_0_bits_fflags_bits_uop_is_jal = 1'h0; // @[lsu.scala:383:25] wire exe_req_0_bits_fflags_bits_uop_is_sfb = 1'h0; // @[lsu.scala:383:25] wire exe_req_0_bits_fflags_bits_uop_edge_inst = 1'h0; // @[lsu.scala:383:25] wire exe_req_0_bits_fflags_bits_uop_taken = 1'h0; // @[lsu.scala:383:25] wire exe_req_0_bits_fflags_bits_uop_prs1_busy = 1'h0; // @[lsu.scala:383:25] wire exe_req_0_bits_fflags_bits_uop_prs2_busy = 1'h0; // @[lsu.scala:383:25] wire exe_req_0_bits_fflags_bits_uop_prs3_busy = 1'h0; // @[lsu.scala:383:25] wire exe_req_0_bits_fflags_bits_uop_ppred_busy = 1'h0; // @[lsu.scala:383:25] wire exe_req_0_bits_fflags_bits_uop_exception = 1'h0; // @[lsu.scala:383:25] wire exe_req_0_bits_fflags_bits_uop_bypassable = 1'h0; // @[lsu.scala:383:25] wire exe_req_0_bits_fflags_bits_uop_mem_signed = 1'h0; // @[lsu.scala:383:25] wire exe_req_0_bits_fflags_bits_uop_is_fence = 1'h0; // @[lsu.scala:383:25] wire exe_req_0_bits_fflags_bits_uop_is_fencei = 1'h0; // @[lsu.scala:383:25] wire exe_req_0_bits_fflags_bits_uop_is_amo = 1'h0; // @[lsu.scala:383:25] wire exe_req_0_bits_fflags_bits_uop_uses_ldq = 1'h0; // @[lsu.scala:383:25] wire exe_req_0_bits_fflags_bits_uop_uses_stq = 1'h0; // @[lsu.scala:383:25] wire exe_req_0_bits_fflags_bits_uop_is_sys_pc2epc = 1'h0; // @[lsu.scala:383:25] wire exe_req_0_bits_fflags_bits_uop_is_unique = 1'h0; // @[lsu.scala:383:25] wire exe_req_0_bits_fflags_bits_uop_flush_on_commit = 1'h0; // @[lsu.scala:383:25] wire exe_req_0_bits_fflags_bits_uop_ldst_is_rs1 = 1'h0; // @[lsu.scala:383:25] wire exe_req_0_bits_fflags_bits_uop_ldst_val = 1'h0; // @[lsu.scala:383:25] wire exe_req_0_bits_fflags_bits_uop_frs3_en = 1'h0; // @[lsu.scala:383:25] wire exe_req_0_bits_fflags_bits_uop_fp_val = 1'h0; // @[lsu.scala:383:25] wire exe_req_0_bits_fflags_bits_uop_fp_single = 1'h0; // @[lsu.scala:383:25] wire exe_req_0_bits_fflags_bits_uop_xcpt_pf_if = 1'h0; // @[lsu.scala:383:25] wire exe_req_0_bits_fflags_bits_uop_xcpt_ae_if = 1'h0; // @[lsu.scala:383:25] wire exe_req_0_bits_fflags_bits_uop_xcpt_ma_if = 1'h0; // @[lsu.scala:383:25] wire exe_req_0_bits_fflags_bits_uop_bp_debug_if = 1'h0; // @[lsu.scala:383:25] wire exe_req_0_bits_fflags_bits_uop_bp_xcpt_if = 1'h0; // @[lsu.scala:383:25] wire exe_req_0_bits_sfence_bits_hv = 1'h0; // @[lsu.scala:383:25] wire exe_req_0_bits_sfence_bits_hg = 1'h0; // @[lsu.scala:383:25] wire _block_load_mask_WIRE_0 = 1'h0; // @[lsu.scala:396:44] wire _block_load_mask_WIRE_1 = 1'h0; // @[lsu.scala:396:44] wire _block_load_mask_WIRE_2 = 1'h0; // @[lsu.scala:396:44] wire _block_load_mask_WIRE_3 = 1'h0; // @[lsu.scala:396:44] wire _block_load_mask_WIRE_4 = 1'h0; // @[lsu.scala:396:44] wire _block_load_mask_WIRE_5 = 1'h0; // @[lsu.scala:396:44] wire _block_load_mask_WIRE_6 = 1'h0; // @[lsu.scala:396:44] wire _block_load_mask_WIRE_7 = 1'h0; // @[lsu.scala:396:44] wire ldq_incoming_e_0_bits_uop_ppred_busy = 1'h0; // @[lsu.scala:263:49] wire _can_fire_sta_retry_T_4 = 1'h0; // @[lsu.scala:482:75] wire _can_fire_sta_retry_T_6 = 1'h0; // @[lsu.scala:483:75] wire _can_fire_sta_retry_WIRE_0 = 1'h0; // @[lsu.scala:263:49] wire _can_fire_hella_incoming_WIRE_0 = 1'h0; // @[lsu.scala:263:49] wire _can_fire_hella_wakeup_WIRE_0 = 1'h0; // @[lsu.scala:263:49] wire _will_fire_load_incoming_0_will_fire_T = 1'h0; // @[lsu.scala:533:51] wire _will_fire_load_incoming_0_will_fire_T_1 = 1'h0; // @[lsu.scala:533:48] wire _will_fire_load_incoming_0_will_fire_T_4 = 1'h0; // @[lsu.scala:534:52] wire _will_fire_load_incoming_0_will_fire_T_5 = 1'h0; // @[lsu.scala:534:49] wire _will_fire_load_incoming_0_will_fire_T_8 = 1'h0; // @[lsu.scala:535:50] wire _will_fire_load_incoming_0_will_fire_T_9 = 1'h0; // @[lsu.scala:535:47] wire _will_fire_load_incoming_0_will_fire_T_12 = 1'h0; // @[lsu.scala:536:51] wire _will_fire_load_incoming_0_will_fire_T_13 = 1'h0; // @[lsu.scala:536:48] wire _will_fire_load_incoming_0_T_9 = 1'h0; // @[lsu.scala:540:46] wire _will_fire_stad_incoming_0_will_fire_T_9 = 1'h0; // @[lsu.scala:535:47] wire _will_fire_stad_incoming_0_will_fire_T_12 = 1'h0; // @[lsu.scala:536:51] wire _will_fire_stad_incoming_0_will_fire_T_13 = 1'h0; // @[lsu.scala:536:48] wire _will_fire_stad_incoming_0_T_6 = 1'h0; // @[lsu.scala:539:46] wire _will_fire_sta_incoming_0_will_fire_T_9 = 1'h0; // @[lsu.scala:535:47] wire _will_fire_sta_incoming_0_T_6 = 1'h0; // @[lsu.scala:539:46] wire _will_fire_std_incoming_0_will_fire_T_1 = 1'h0; // @[lsu.scala:533:48] wire _will_fire_std_incoming_0_will_fire_T_5 = 1'h0; // @[lsu.scala:534:49] wire _will_fire_std_incoming_0_will_fire_T_9 = 1'h0; // @[lsu.scala:535:47] wire _will_fire_std_incoming_0_T = 1'h0; // @[lsu.scala:537:46] wire _will_fire_std_incoming_0_T_3 = 1'h0; // @[lsu.scala:538:46] wire _will_fire_std_incoming_0_T_6 = 1'h0; // @[lsu.scala:539:46] wire _will_fire_sfence_0_will_fire_T_5 = 1'h0; // @[lsu.scala:534:49] wire _will_fire_sfence_0_will_fire_T_9 = 1'h0; // @[lsu.scala:535:47] wire _will_fire_sfence_0_T_3 = 1'h0; // @[lsu.scala:538:46] wire _will_fire_sfence_0_T_6 = 1'h0; // @[lsu.scala:539:46] wire _will_fire_release_0_will_fire_T_1 = 1'h0; // @[lsu.scala:533:48] wire _will_fire_release_0_will_fire_T_9 = 1'h0; // @[lsu.scala:535:47] wire _will_fire_release_0_will_fire_T_13 = 1'h0; // @[lsu.scala:536:48] wire _will_fire_release_0_T = 1'h0; // @[lsu.scala:537:46] wire _will_fire_release_0_T_6 = 1'h0; // @[lsu.scala:539:46] wire _will_fire_release_0_T_9 = 1'h0; // @[lsu.scala:540:46] wire _will_fire_hella_incoming_0_will_fire_T_5 = 1'h0; // @[lsu.scala:534:49] wire _will_fire_hella_incoming_0_will_fire_T_13 = 1'h0; // @[lsu.scala:536:48] wire _will_fire_hella_incoming_0_T_3 = 1'h0; // @[lsu.scala:538:46] wire _will_fire_hella_incoming_0_T_9 = 1'h0; // @[lsu.scala:540:46] wire _will_fire_hella_wakeup_0_will_fire_T_1 = 1'h0; // @[lsu.scala:533:48] wire _will_fire_hella_wakeup_0_will_fire_T_5 = 1'h0; // @[lsu.scala:534:49] wire _will_fire_hella_wakeup_0_will_fire_T_13 = 1'h0; // @[lsu.scala:536:48] wire _will_fire_hella_wakeup_0_T = 1'h0; // @[lsu.scala:537:46] wire _will_fire_hella_wakeup_0_T_3 = 1'h0; // @[lsu.scala:538:46] wire _will_fire_hella_wakeup_0_T_9 = 1'h0; // @[lsu.scala:540:46] wire _will_fire_load_retry_0_will_fire_T_13 = 1'h0; // @[lsu.scala:536:48] wire _will_fire_load_retry_0_T_9 = 1'h0; // @[lsu.scala:540:46] wire _will_fire_sta_retry_0_will_fire_T_9 = 1'h0; // @[lsu.scala:535:47] wire _will_fire_sta_retry_0_T_6 = 1'h0; // @[lsu.scala:539:46] wire _will_fire_load_wakeup_0_will_fire_T_1 = 1'h0; // @[lsu.scala:533:48] wire _will_fire_load_wakeup_0_will_fire_T_13 = 1'h0; // @[lsu.scala:536:48] wire _will_fire_load_wakeup_0_T = 1'h0; // @[lsu.scala:537:46] wire _will_fire_load_wakeup_0_T_9 = 1'h0; // @[lsu.scala:540:46] wire _will_fire_store_commit_0_will_fire_T_1 = 1'h0; // @[lsu.scala:533:48] wire _will_fire_store_commit_0_will_fire_T_5 = 1'h0; // @[lsu.scala:534:49] wire _will_fire_store_commit_0_will_fire_T_13 = 1'h0; // @[lsu.scala:536:48] wire _will_fire_store_commit_0_T = 1'h0; // @[lsu.scala:537:46] wire _will_fire_store_commit_0_T_3 = 1'h0; // @[lsu.scala:538:46] wire _will_fire_store_commit_0_T_9 = 1'h0; // @[lsu.scala:540:46] wire exe_tlb_uop_uop_is_rvc = 1'h0; // @[consts.scala:269:19] wire exe_tlb_uop_uop_ctrl_fcn_dw = 1'h0; // @[consts.scala:269:19] wire exe_tlb_uop_uop_ctrl_is_load = 1'h0; // @[consts.scala:269:19] wire exe_tlb_uop_uop_ctrl_is_sta = 1'h0; // @[consts.scala:269:19] wire exe_tlb_uop_uop_ctrl_is_std = 1'h0; // @[consts.scala:269:19] wire exe_tlb_uop_uop_iw_p1_poisoned = 1'h0; // @[consts.scala:269:19] wire exe_tlb_uop_uop_iw_p2_poisoned = 1'h0; // @[consts.scala:269:19] wire exe_tlb_uop_uop_is_br = 1'h0; // @[consts.scala:269:19] wire exe_tlb_uop_uop_is_jalr = 1'h0; // @[consts.scala:269:19] wire exe_tlb_uop_uop_is_jal = 1'h0; // @[consts.scala:269:19] wire exe_tlb_uop_uop_is_sfb = 1'h0; // @[consts.scala:269:19] wire exe_tlb_uop_uop_edge_inst = 1'h0; // @[consts.scala:269:19] wire exe_tlb_uop_uop_taken = 1'h0; // @[consts.scala:269:19] wire exe_tlb_uop_uop_prs1_busy = 1'h0; // @[consts.scala:269:19] wire exe_tlb_uop_uop_prs2_busy = 1'h0; // @[consts.scala:269:19] wire exe_tlb_uop_uop_prs3_busy = 1'h0; // @[consts.scala:269:19] wire exe_tlb_uop_uop_ppred_busy = 1'h0; // @[consts.scala:269:19] wire exe_tlb_uop_uop_exception = 1'h0; // @[consts.scala:269:19] wire exe_tlb_uop_uop_bypassable = 1'h0; // @[consts.scala:269:19] wire exe_tlb_uop_uop_mem_signed = 1'h0; // @[consts.scala:269:19] wire exe_tlb_uop_uop_is_fence = 1'h0; // @[consts.scala:269:19] wire exe_tlb_uop_uop_is_fencei = 1'h0; // @[consts.scala:269:19] wire exe_tlb_uop_uop_is_amo = 1'h0; // @[consts.scala:269:19] wire exe_tlb_uop_uop_uses_ldq = 1'h0; // @[consts.scala:269:19] wire exe_tlb_uop_uop_uses_stq = 1'h0; // @[consts.scala:269:19] wire exe_tlb_uop_uop_is_sys_pc2epc = 1'h0; // @[consts.scala:269:19] wire exe_tlb_uop_uop_is_unique = 1'h0; // @[consts.scala:269:19] wire exe_tlb_uop_uop_flush_on_commit = 1'h0; // @[consts.scala:269:19] wire exe_tlb_uop_uop_ldst_is_rs1 = 1'h0; // @[consts.scala:269:19] wire exe_tlb_uop_uop_ldst_val = 1'h0; // @[consts.scala:269:19] wire exe_tlb_uop_uop_frs3_en = 1'h0; // @[consts.scala:269:19] wire exe_tlb_uop_uop_fp_val = 1'h0; // @[consts.scala:269:19] wire exe_tlb_uop_uop_fp_single = 1'h0; // @[consts.scala:269:19] wire exe_tlb_uop_uop_xcpt_pf_if = 1'h0; // @[consts.scala:269:19] wire exe_tlb_uop_uop_xcpt_ae_if = 1'h0; // @[consts.scala:269:19] wire exe_tlb_uop_uop_xcpt_ma_if = 1'h0; // @[consts.scala:269:19] wire exe_tlb_uop_uop_bp_debug_if = 1'h0; // @[consts.scala:269:19] wire exe_tlb_uop_uop_bp_xcpt_if = 1'h0; // @[consts.scala:269:19] wire exe_tlb_uop_cs_fcn_dw = 1'h0; // @[consts.scala:279:18] wire exe_tlb_uop_cs_is_load = 1'h0; // @[consts.scala:279:18] wire exe_tlb_uop_cs_is_sta = 1'h0; // @[consts.scala:279:18] wire exe_tlb_uop_cs_is_std = 1'h0; // @[consts.scala:279:18] wire exe_tlb_uop_uop_1_is_rvc = 1'h0; // @[consts.scala:269:19] wire exe_tlb_uop_uop_1_ctrl_fcn_dw = 1'h0; // @[consts.scala:269:19] wire exe_tlb_uop_uop_1_ctrl_is_load = 1'h0; // @[consts.scala:269:19] wire exe_tlb_uop_uop_1_ctrl_is_sta = 1'h0; // @[consts.scala:269:19] wire exe_tlb_uop_uop_1_ctrl_is_std = 1'h0; // @[consts.scala:269:19] wire exe_tlb_uop_uop_1_iw_p1_poisoned = 1'h0; // @[consts.scala:269:19] wire exe_tlb_uop_uop_1_iw_p2_poisoned = 1'h0; // @[consts.scala:269:19] wire exe_tlb_uop_uop_1_is_br = 1'h0; // @[consts.scala:269:19] wire exe_tlb_uop_uop_1_is_jalr = 1'h0; // @[consts.scala:269:19] wire exe_tlb_uop_uop_1_is_jal = 1'h0; // @[consts.scala:269:19] wire exe_tlb_uop_uop_1_is_sfb = 1'h0; // @[consts.scala:269:19] wire exe_tlb_uop_uop_1_edge_inst = 1'h0; // @[consts.scala:269:19] wire exe_tlb_uop_uop_1_taken = 1'h0; // @[consts.scala:269:19] wire exe_tlb_uop_uop_1_prs1_busy = 1'h0; // @[consts.scala:269:19] wire exe_tlb_uop_uop_1_prs2_busy = 1'h0; // @[consts.scala:269:19] wire exe_tlb_uop_uop_1_prs3_busy = 1'h0; // @[consts.scala:269:19] wire exe_tlb_uop_uop_1_ppred_busy = 1'h0; // @[consts.scala:269:19] wire exe_tlb_uop_uop_1_exception = 1'h0; // @[consts.scala:269:19] wire exe_tlb_uop_uop_1_bypassable = 1'h0; // @[consts.scala:269:19] wire exe_tlb_uop_uop_1_mem_signed = 1'h0; // @[consts.scala:269:19] wire exe_tlb_uop_uop_1_is_fence = 1'h0; // @[consts.scala:269:19] wire exe_tlb_uop_uop_1_is_fencei = 1'h0; // @[consts.scala:269:19] wire exe_tlb_uop_uop_1_is_amo = 1'h0; // @[consts.scala:269:19] wire exe_tlb_uop_uop_1_uses_ldq = 1'h0; // @[consts.scala:269:19] wire exe_tlb_uop_uop_1_uses_stq = 1'h0; // @[consts.scala:269:19] wire exe_tlb_uop_uop_1_is_sys_pc2epc = 1'h0; // @[consts.scala:269:19] wire exe_tlb_uop_uop_1_is_unique = 1'h0; // @[consts.scala:269:19] wire exe_tlb_uop_uop_1_flush_on_commit = 1'h0; // @[consts.scala:269:19] wire exe_tlb_uop_uop_1_ldst_is_rs1 = 1'h0; // @[consts.scala:269:19] wire exe_tlb_uop_uop_1_ldst_val = 1'h0; // @[consts.scala:269:19] wire exe_tlb_uop_uop_1_frs3_en = 1'h0; // @[consts.scala:269:19] wire exe_tlb_uop_uop_1_fp_val = 1'h0; // @[consts.scala:269:19] wire exe_tlb_uop_uop_1_fp_single = 1'h0; // @[consts.scala:269:19] wire exe_tlb_uop_uop_1_xcpt_pf_if = 1'h0; // @[consts.scala:269:19] wire exe_tlb_uop_uop_1_xcpt_ae_if = 1'h0; // @[consts.scala:269:19] wire exe_tlb_uop_uop_1_xcpt_ma_if = 1'h0; // @[consts.scala:269:19] wire exe_tlb_uop_uop_1_bp_debug_if = 1'h0; // @[consts.scala:269:19] wire exe_tlb_uop_uop_1_bp_xcpt_if = 1'h0; // @[consts.scala:269:19] wire exe_tlb_uop_cs_1_fcn_dw = 1'h0; // @[consts.scala:279:18] wire exe_tlb_uop_cs_1_is_load = 1'h0; // @[consts.scala:279:18] wire exe_tlb_uop_cs_1_is_sta = 1'h0; // @[consts.scala:279:18] wire exe_tlb_uop_cs_1_is_std = 1'h0; // @[consts.scala:279:18] wire _exe_tlb_uop_T_3_is_rvc = 1'h0; // @[lsu.scala:602:24] wire _exe_tlb_uop_T_3_ctrl_fcn_dw = 1'h0; // @[lsu.scala:602:24] wire _exe_tlb_uop_T_3_ctrl_is_load = 1'h0; // @[lsu.scala:602:24] wire _exe_tlb_uop_T_3_ctrl_is_sta = 1'h0; // @[lsu.scala:602:24] wire _exe_tlb_uop_T_3_ctrl_is_std = 1'h0; // @[lsu.scala:602:24] wire _exe_tlb_uop_T_3_iw_p1_poisoned = 1'h0; // @[lsu.scala:602:24] wire _exe_tlb_uop_T_3_iw_p2_poisoned = 1'h0; // @[lsu.scala:602:24] wire _exe_tlb_uop_T_3_is_br = 1'h0; // @[lsu.scala:602:24] wire _exe_tlb_uop_T_3_is_jalr = 1'h0; // @[lsu.scala:602:24] wire _exe_tlb_uop_T_3_is_jal = 1'h0; // @[lsu.scala:602:24] wire _exe_tlb_uop_T_3_is_sfb = 1'h0; // @[lsu.scala:602:24] wire _exe_tlb_uop_T_3_edge_inst = 1'h0; // @[lsu.scala:602:24] wire _exe_tlb_uop_T_3_taken = 1'h0; // @[lsu.scala:602:24] wire _exe_tlb_uop_T_3_prs1_busy = 1'h0; // @[lsu.scala:602:24] wire _exe_tlb_uop_T_3_prs2_busy = 1'h0; // @[lsu.scala:602:24] wire _exe_tlb_uop_T_3_prs3_busy = 1'h0; // @[lsu.scala:602:24] wire _exe_tlb_uop_T_3_ppred_busy = 1'h0; // @[lsu.scala:602:24] wire _exe_tlb_uop_T_3_exception = 1'h0; // @[lsu.scala:602:24] wire _exe_tlb_uop_T_3_bypassable = 1'h0; // @[lsu.scala:602:24] wire _exe_tlb_uop_T_3_mem_signed = 1'h0; // @[lsu.scala:602:24] wire _exe_tlb_uop_T_3_is_fence = 1'h0; // @[lsu.scala:602:24] wire _exe_tlb_uop_T_3_is_fencei = 1'h0; // @[lsu.scala:602:24] wire _exe_tlb_uop_T_3_is_amo = 1'h0; // @[lsu.scala:602:24] wire _exe_tlb_uop_T_3_uses_ldq = 1'h0; // @[lsu.scala:602:24] wire _exe_tlb_uop_T_3_uses_stq = 1'h0; // @[lsu.scala:602:24] wire _exe_tlb_uop_T_3_is_sys_pc2epc = 1'h0; // @[lsu.scala:602:24] wire _exe_tlb_uop_T_3_is_unique = 1'h0; // @[lsu.scala:602:24] wire _exe_tlb_uop_T_3_flush_on_commit = 1'h0; // @[lsu.scala:602:24] wire _exe_tlb_uop_T_3_ldst_is_rs1 = 1'h0; // @[lsu.scala:602:24] wire _exe_tlb_uop_T_3_ldst_val = 1'h0; // @[lsu.scala:602:24] wire _exe_tlb_uop_T_3_frs3_en = 1'h0; // @[lsu.scala:602:24] wire _exe_tlb_uop_T_3_fp_val = 1'h0; // @[lsu.scala:602:24] wire _exe_tlb_uop_T_3_fp_single = 1'h0; // @[lsu.scala:602:24] wire _exe_tlb_uop_T_3_xcpt_pf_if = 1'h0; // @[lsu.scala:602:24] wire _exe_tlb_uop_T_3_xcpt_ae_if = 1'h0; // @[lsu.scala:602:24] wire _exe_tlb_uop_T_3_xcpt_ma_if = 1'h0; // @[lsu.scala:602:24] wire _exe_tlb_uop_T_3_bp_debug_if = 1'h0; // @[lsu.scala:602:24] wire _exe_tlb_uop_T_3_bp_xcpt_if = 1'h0; // @[lsu.scala:602:24] wire _exe_sfence_WIRE_valid = 1'h0; // @[lsu.scala:615:43] wire _exe_sfence_WIRE_bits_rs1 = 1'h0; // @[lsu.scala:615:43] wire _exe_sfence_WIRE_bits_rs2 = 1'h0; // @[lsu.scala:615:43] wire _exe_sfence_WIRE_bits_asid = 1'h0; // @[lsu.scala:615:43] wire _exe_sfence_WIRE_bits_hv = 1'h0; // @[lsu.scala:615:43] wire _exe_sfence_WIRE_bits_hg = 1'h0; // @[lsu.scala:615:43] wire exe_sfence_bits_hv = 1'h0; // @[lsu.scala:615:28] wire exe_sfence_bits_hg = 1'h0; // @[lsu.scala:615:28] wire _exe_tlb_miss_T = 1'h0; // @[lsu.scala:709:86] wire _s0_executing_loads_WIRE_0 = 1'h0; // @[lsu.scala:755:44] wire _s0_executing_loads_WIRE_1 = 1'h0; // @[lsu.scala:755:44] wire _s0_executing_loads_WIRE_2 = 1'h0; // @[lsu.scala:755:44] wire _s0_executing_loads_WIRE_3 = 1'h0; // @[lsu.scala:755:44] wire _s0_executing_loads_WIRE_4 = 1'h0; // @[lsu.scala:755:44] wire _s0_executing_loads_WIRE_5 = 1'h0; // @[lsu.scala:755:44] wire _s0_executing_loads_WIRE_6 = 1'h0; // @[lsu.scala:755:44] wire _s0_executing_loads_WIRE_7 = 1'h0; // @[lsu.scala:755:44] wire dmem_req_0_bits_uop_uop_is_rvc = 1'h0; // @[consts.scala:269:19] wire dmem_req_0_bits_uop_uop_ctrl_fcn_dw = 1'h0; // @[consts.scala:269:19] wire dmem_req_0_bits_uop_uop_ctrl_is_load = 1'h0; // @[consts.scala:269:19] wire dmem_req_0_bits_uop_uop_ctrl_is_sta = 1'h0; // @[consts.scala:269:19] wire dmem_req_0_bits_uop_uop_ctrl_is_std = 1'h0; // @[consts.scala:269:19] wire dmem_req_0_bits_uop_uop_iw_p1_poisoned = 1'h0; // @[consts.scala:269:19] wire dmem_req_0_bits_uop_uop_iw_p2_poisoned = 1'h0; // @[consts.scala:269:19] wire dmem_req_0_bits_uop_uop_is_br = 1'h0; // @[consts.scala:269:19] wire dmem_req_0_bits_uop_uop_is_jalr = 1'h0; // @[consts.scala:269:19] wire dmem_req_0_bits_uop_uop_is_jal = 1'h0; // @[consts.scala:269:19] wire dmem_req_0_bits_uop_uop_is_sfb = 1'h0; // @[consts.scala:269:19] wire dmem_req_0_bits_uop_uop_edge_inst = 1'h0; // @[consts.scala:269:19] wire dmem_req_0_bits_uop_uop_taken = 1'h0; // @[consts.scala:269:19] wire dmem_req_0_bits_uop_uop_prs1_busy = 1'h0; // @[consts.scala:269:19] wire dmem_req_0_bits_uop_uop_prs2_busy = 1'h0; // @[consts.scala:269:19] wire dmem_req_0_bits_uop_uop_prs3_busy = 1'h0; // @[consts.scala:269:19] wire dmem_req_0_bits_uop_uop_ppred_busy = 1'h0; // @[consts.scala:269:19] wire dmem_req_0_bits_uop_uop_exception = 1'h0; // @[consts.scala:269:19] wire dmem_req_0_bits_uop_uop_bypassable = 1'h0; // @[consts.scala:269:19] wire dmem_req_0_bits_uop_uop_mem_signed = 1'h0; // @[consts.scala:269:19] wire dmem_req_0_bits_uop_uop_is_fence = 1'h0; // @[consts.scala:269:19] wire dmem_req_0_bits_uop_uop_is_fencei = 1'h0; // @[consts.scala:269:19] wire dmem_req_0_bits_uop_uop_is_amo = 1'h0; // @[consts.scala:269:19] wire dmem_req_0_bits_uop_uop_uses_ldq = 1'h0; // @[consts.scala:269:19] wire dmem_req_0_bits_uop_uop_uses_stq = 1'h0; // @[consts.scala:269:19] wire dmem_req_0_bits_uop_uop_is_sys_pc2epc = 1'h0; // @[consts.scala:269:19] wire dmem_req_0_bits_uop_uop_is_unique = 1'h0; // @[consts.scala:269:19] wire dmem_req_0_bits_uop_uop_flush_on_commit = 1'h0; // @[consts.scala:269:19] wire dmem_req_0_bits_uop_uop_ldst_is_rs1 = 1'h0; // @[consts.scala:269:19] wire dmem_req_0_bits_uop_uop_ldst_val = 1'h0; // @[consts.scala:269:19] wire dmem_req_0_bits_uop_uop_frs3_en = 1'h0; // @[consts.scala:269:19] wire dmem_req_0_bits_uop_uop_fp_val = 1'h0; // @[consts.scala:269:19] wire dmem_req_0_bits_uop_uop_fp_single = 1'h0; // @[consts.scala:269:19] wire dmem_req_0_bits_uop_uop_xcpt_pf_if = 1'h0; // @[consts.scala:269:19] wire dmem_req_0_bits_uop_uop_xcpt_ae_if = 1'h0; // @[consts.scala:269:19] wire dmem_req_0_bits_uop_uop_xcpt_ma_if = 1'h0; // @[consts.scala:269:19] wire dmem_req_0_bits_uop_uop_bp_debug_if = 1'h0; // @[consts.scala:269:19] wire dmem_req_0_bits_uop_uop_bp_xcpt_if = 1'h0; // @[consts.scala:269:19] wire dmem_req_0_bits_uop_cs_fcn_dw = 1'h0; // @[consts.scala:279:18] wire dmem_req_0_bits_uop_cs_is_load = 1'h0; // @[consts.scala:279:18] wire dmem_req_0_bits_uop_cs_is_sta = 1'h0; // @[consts.scala:279:18] wire dmem_req_0_bits_uop_cs_is_std = 1'h0; // @[consts.scala:279:18] wire _dmem_req_0_bits_data_T_15 = 1'h0; // @[AMOALU.scala:29:19] wire _dmem_req_0_bits_data_T_20 = 1'h0; // @[AMOALU.scala:29:19] wire _dmem_req_0_bits_data_T_24 = 1'h0; // @[AMOALU.scala:29:19] wire _dmem_req_0_bits_data_T_30 = 1'h0; // @[AMOALU.scala:29:19] wire _dmem_req_0_bits_data_T_35 = 1'h0; // @[AMOALU.scala:29:19] wire _dmem_req_0_bits_data_T_39 = 1'h0; // @[AMOALU.scala:29:19] wire mem_ldq_wakeup_e_out_bits_uop_ppred_busy = 1'h0; // @[util.scala:106:23] wire mem_ldq_retry_e_out_bits_uop_ppred_busy = 1'h0; // @[util.scala:106:23] wire _mem_ldq_e_WIRE_valid = 1'h0; // @[lsu.scala:918:90] wire _mem_ldq_e_WIRE_bits_uop_is_rvc = 1'h0; // @[lsu.scala:918:90] wire _mem_ldq_e_WIRE_bits_uop_ctrl_fcn_dw = 1'h0; // @[lsu.scala:918:90] wire _mem_ldq_e_WIRE_bits_uop_ctrl_is_load = 1'h0; // @[lsu.scala:918:90] wire _mem_ldq_e_WIRE_bits_uop_ctrl_is_sta = 1'h0; // @[lsu.scala:918:90] wire _mem_ldq_e_WIRE_bits_uop_ctrl_is_std = 1'h0; // @[lsu.scala:918:90] wire _mem_ldq_e_WIRE_bits_uop_iw_p1_poisoned = 1'h0; // @[lsu.scala:918:90] wire _mem_ldq_e_WIRE_bits_uop_iw_p2_poisoned = 1'h0; // @[lsu.scala:918:90] wire _mem_ldq_e_WIRE_bits_uop_is_br = 1'h0; // @[lsu.scala:918:90] wire _mem_ldq_e_WIRE_bits_uop_is_jalr = 1'h0; // @[lsu.scala:918:90] wire _mem_ldq_e_WIRE_bits_uop_is_jal = 1'h0; // @[lsu.scala:918:90] wire _mem_ldq_e_WIRE_bits_uop_is_sfb = 1'h0; // @[lsu.scala:918:90] wire _mem_ldq_e_WIRE_bits_uop_edge_inst = 1'h0; // @[lsu.scala:918:90] wire _mem_ldq_e_WIRE_bits_uop_taken = 1'h0; // @[lsu.scala:918:90] wire _mem_ldq_e_WIRE_bits_uop_prs1_busy = 1'h0; // @[lsu.scala:918:90] wire _mem_ldq_e_WIRE_bits_uop_prs2_busy = 1'h0; // @[lsu.scala:918:90] wire _mem_ldq_e_WIRE_bits_uop_prs3_busy = 1'h0; // @[lsu.scala:918:90] wire _mem_ldq_e_WIRE_bits_uop_ppred_busy = 1'h0; // @[lsu.scala:918:90] wire _mem_ldq_e_WIRE_bits_uop_exception = 1'h0; // @[lsu.scala:918:90] wire _mem_ldq_e_WIRE_bits_uop_bypassable = 1'h0; // @[lsu.scala:918:90] wire _mem_ldq_e_WIRE_bits_uop_mem_signed = 1'h0; // @[lsu.scala:918:90] wire _mem_ldq_e_WIRE_bits_uop_is_fence = 1'h0; // @[lsu.scala:918:90] wire _mem_ldq_e_WIRE_bits_uop_is_fencei = 1'h0; // @[lsu.scala:918:90] wire _mem_ldq_e_WIRE_bits_uop_is_amo = 1'h0; // @[lsu.scala:918:90] wire _mem_ldq_e_WIRE_bits_uop_uses_ldq = 1'h0; // @[lsu.scala:918:90] wire _mem_ldq_e_WIRE_bits_uop_uses_stq = 1'h0; // @[lsu.scala:918:90] wire _mem_ldq_e_WIRE_bits_uop_is_sys_pc2epc = 1'h0; // @[lsu.scala:918:90] wire _mem_ldq_e_WIRE_bits_uop_is_unique = 1'h0; // @[lsu.scala:918:90] wire _mem_ldq_e_WIRE_bits_uop_flush_on_commit = 1'h0; // @[lsu.scala:918:90] wire _mem_ldq_e_WIRE_bits_uop_ldst_is_rs1 = 1'h0; // @[lsu.scala:918:90] wire _mem_ldq_e_WIRE_bits_uop_ldst_val = 1'h0; // @[lsu.scala:918:90] wire _mem_ldq_e_WIRE_bits_uop_frs3_en = 1'h0; // @[lsu.scala:918:90] wire _mem_ldq_e_WIRE_bits_uop_fp_val = 1'h0; // @[lsu.scala:918:90] wire _mem_ldq_e_WIRE_bits_uop_fp_single = 1'h0; // @[lsu.scala:918:90] wire _mem_ldq_e_WIRE_bits_uop_xcpt_pf_if = 1'h0; // @[lsu.scala:918:90] wire _mem_ldq_e_WIRE_bits_uop_xcpt_ae_if = 1'h0; // @[lsu.scala:918:90] wire _mem_ldq_e_WIRE_bits_uop_xcpt_ma_if = 1'h0; // @[lsu.scala:918:90] wire _mem_ldq_e_WIRE_bits_uop_bp_debug_if = 1'h0; // @[lsu.scala:918:90] wire _mem_ldq_e_WIRE_bits_uop_bp_xcpt_if = 1'h0; // @[lsu.scala:918:90] wire _mem_ldq_e_WIRE_bits_addr_valid = 1'h0; // @[lsu.scala:918:90] wire _mem_ldq_e_WIRE_bits_addr_is_virtual = 1'h0; // @[lsu.scala:918:90] wire _mem_ldq_e_WIRE_bits_addr_is_uncacheable = 1'h0; // @[lsu.scala:918:90] wire _mem_ldq_e_WIRE_bits_executed = 1'h0; // @[lsu.scala:918:90] wire _mem_ldq_e_WIRE_bits_succeeded = 1'h0; // @[lsu.scala:918:90] wire _mem_ldq_e_WIRE_bits_order_fail = 1'h0; // @[lsu.scala:918:90] wire _mem_ldq_e_WIRE_bits_observed = 1'h0; // @[lsu.scala:918:90] wire _mem_ldq_e_WIRE_bits_forward_std_val = 1'h0; // @[lsu.scala:918:90] wire _mem_stq_e_WIRE_valid = 1'h0; // @[lsu.scala:922:89] wire _mem_stq_e_WIRE_bits_uop_is_rvc = 1'h0; // @[lsu.scala:922:89] wire _mem_stq_e_WIRE_bits_uop_ctrl_fcn_dw = 1'h0; // @[lsu.scala:922:89] wire _mem_stq_e_WIRE_bits_uop_ctrl_is_load = 1'h0; // @[lsu.scala:922:89] wire _mem_stq_e_WIRE_bits_uop_ctrl_is_sta = 1'h0; // @[lsu.scala:922:89] wire _mem_stq_e_WIRE_bits_uop_ctrl_is_std = 1'h0; // @[lsu.scala:922:89] wire _mem_stq_e_WIRE_bits_uop_iw_p1_poisoned = 1'h0; // @[lsu.scala:922:89] wire _mem_stq_e_WIRE_bits_uop_iw_p2_poisoned = 1'h0; // @[lsu.scala:922:89] wire _mem_stq_e_WIRE_bits_uop_is_br = 1'h0; // @[lsu.scala:922:89] wire _mem_stq_e_WIRE_bits_uop_is_jalr = 1'h0; // @[lsu.scala:922:89] wire _mem_stq_e_WIRE_bits_uop_is_jal = 1'h0; // @[lsu.scala:922:89] wire _mem_stq_e_WIRE_bits_uop_is_sfb = 1'h0; // @[lsu.scala:922:89] wire _mem_stq_e_WIRE_bits_uop_edge_inst = 1'h0; // @[lsu.scala:922:89] wire _mem_stq_e_WIRE_bits_uop_taken = 1'h0; // @[lsu.scala:922:89] wire _mem_stq_e_WIRE_bits_uop_prs1_busy = 1'h0; // @[lsu.scala:922:89] wire _mem_stq_e_WIRE_bits_uop_prs2_busy = 1'h0; // @[lsu.scala:922:89] wire _mem_stq_e_WIRE_bits_uop_prs3_busy = 1'h0; // @[lsu.scala:922:89] wire _mem_stq_e_WIRE_bits_uop_ppred_busy = 1'h0; // @[lsu.scala:922:89] wire _mem_stq_e_WIRE_bits_uop_exception = 1'h0; // @[lsu.scala:922:89] wire _mem_stq_e_WIRE_bits_uop_bypassable = 1'h0; // @[lsu.scala:922:89] wire _mem_stq_e_WIRE_bits_uop_mem_signed = 1'h0; // @[lsu.scala:922:89] wire _mem_stq_e_WIRE_bits_uop_is_fence = 1'h0; // @[lsu.scala:922:89] wire _mem_stq_e_WIRE_bits_uop_is_fencei = 1'h0; // @[lsu.scala:922:89] wire _mem_stq_e_WIRE_bits_uop_is_amo = 1'h0; // @[lsu.scala:922:89] wire _mem_stq_e_WIRE_bits_uop_uses_ldq = 1'h0; // @[lsu.scala:922:89] wire _mem_stq_e_WIRE_bits_uop_uses_stq = 1'h0; // @[lsu.scala:922:89] wire _mem_stq_e_WIRE_bits_uop_is_sys_pc2epc = 1'h0; // @[lsu.scala:922:89] wire _mem_stq_e_WIRE_bits_uop_is_unique = 1'h0; // @[lsu.scala:922:89] wire _mem_stq_e_WIRE_bits_uop_flush_on_commit = 1'h0; // @[lsu.scala:922:89] wire _mem_stq_e_WIRE_bits_uop_ldst_is_rs1 = 1'h0; // @[lsu.scala:922:89] wire _mem_stq_e_WIRE_bits_uop_ldst_val = 1'h0; // @[lsu.scala:922:89] wire _mem_stq_e_WIRE_bits_uop_frs3_en = 1'h0; // @[lsu.scala:922:89] wire _mem_stq_e_WIRE_bits_uop_fp_val = 1'h0; // @[lsu.scala:922:89] wire _mem_stq_e_WIRE_bits_uop_fp_single = 1'h0; // @[lsu.scala:922:89] wire _mem_stq_e_WIRE_bits_uop_xcpt_pf_if = 1'h0; // @[lsu.scala:922:89] wire _mem_stq_e_WIRE_bits_uop_xcpt_ae_if = 1'h0; // @[lsu.scala:922:89] wire _mem_stq_e_WIRE_bits_uop_xcpt_ma_if = 1'h0; // @[lsu.scala:922:89] wire _mem_stq_e_WIRE_bits_uop_bp_debug_if = 1'h0; // @[lsu.scala:922:89] wire _mem_stq_e_WIRE_bits_uop_bp_xcpt_if = 1'h0; // @[lsu.scala:922:89] wire _mem_stq_e_WIRE_bits_addr_valid = 1'h0; // @[lsu.scala:922:89] wire _mem_stq_e_WIRE_bits_addr_is_virtual = 1'h0; // @[lsu.scala:922:89] wire _mem_stq_e_WIRE_bits_data_valid = 1'h0; // @[lsu.scala:922:89] wire _mem_stq_e_WIRE_bits_committed = 1'h0; // @[lsu.scala:922:89] wire _mem_stq_e_WIRE_bits_succeeded = 1'h0; // @[lsu.scala:922:89] wire _clr_bsy_valid_WIRE_0 = 1'h0; // @[lsu.scala:263:49] wire lcam_uop_uop_is_rvc = 1'h0; // @[consts.scala:269:19] wire lcam_uop_uop_ctrl_fcn_dw = 1'h0; // @[consts.scala:269:19] wire lcam_uop_uop_ctrl_is_load = 1'h0; // @[consts.scala:269:19] wire lcam_uop_uop_ctrl_is_sta = 1'h0; // @[consts.scala:269:19] wire lcam_uop_uop_ctrl_is_std = 1'h0; // @[consts.scala:269:19] wire lcam_uop_uop_iw_p1_poisoned = 1'h0; // @[consts.scala:269:19] wire lcam_uop_uop_iw_p2_poisoned = 1'h0; // @[consts.scala:269:19] wire lcam_uop_uop_is_br = 1'h0; // @[consts.scala:269:19] wire lcam_uop_uop_is_jalr = 1'h0; // @[consts.scala:269:19] wire lcam_uop_uop_is_jal = 1'h0; // @[consts.scala:269:19] wire lcam_uop_uop_is_sfb = 1'h0; // @[consts.scala:269:19] wire lcam_uop_uop_edge_inst = 1'h0; // @[consts.scala:269:19] wire lcam_uop_uop_taken = 1'h0; // @[consts.scala:269:19] wire lcam_uop_uop_prs1_busy = 1'h0; // @[consts.scala:269:19] wire lcam_uop_uop_prs2_busy = 1'h0; // @[consts.scala:269:19] wire lcam_uop_uop_prs3_busy = 1'h0; // @[consts.scala:269:19] wire lcam_uop_uop_ppred_busy = 1'h0; // @[consts.scala:269:19] wire lcam_uop_uop_exception = 1'h0; // @[consts.scala:269:19] wire lcam_uop_uop_bypassable = 1'h0; // @[consts.scala:269:19] wire lcam_uop_uop_mem_signed = 1'h0; // @[consts.scala:269:19] wire lcam_uop_uop_is_fence = 1'h0; // @[consts.scala:269:19] wire lcam_uop_uop_is_fencei = 1'h0; // @[consts.scala:269:19] wire lcam_uop_uop_is_amo = 1'h0; // @[consts.scala:269:19] wire lcam_uop_uop_uses_ldq = 1'h0; // @[consts.scala:269:19] wire lcam_uop_uop_uses_stq = 1'h0; // @[consts.scala:269:19] wire lcam_uop_uop_is_sys_pc2epc = 1'h0; // @[consts.scala:269:19] wire lcam_uop_uop_is_unique = 1'h0; // @[consts.scala:269:19] wire lcam_uop_uop_flush_on_commit = 1'h0; // @[consts.scala:269:19] wire lcam_uop_uop_ldst_is_rs1 = 1'h0; // @[consts.scala:269:19] wire lcam_uop_uop_ldst_val = 1'h0; // @[consts.scala:269:19] wire lcam_uop_uop_frs3_en = 1'h0; // @[consts.scala:269:19] wire lcam_uop_uop_fp_val = 1'h0; // @[consts.scala:269:19] wire lcam_uop_uop_fp_single = 1'h0; // @[consts.scala:269:19] wire lcam_uop_uop_xcpt_pf_if = 1'h0; // @[consts.scala:269:19] wire lcam_uop_uop_xcpt_ae_if = 1'h0; // @[consts.scala:269:19] wire lcam_uop_uop_xcpt_ma_if = 1'h0; // @[consts.scala:269:19] wire lcam_uop_uop_bp_debug_if = 1'h0; // @[consts.scala:269:19] wire lcam_uop_uop_bp_xcpt_if = 1'h0; // @[consts.scala:269:19] wire lcam_uop_cs_fcn_dw = 1'h0; // @[consts.scala:279:18] wire lcam_uop_cs_is_load = 1'h0; // @[consts.scala:279:18] wire lcam_uop_cs_is_sta = 1'h0; // @[consts.scala:279:18] wire lcam_uop_cs_is_std = 1'h0; // @[consts.scala:279:18] wire _ldst_addr_matches_WIRE_0 = 1'h0; // @[lsu.scala:1050:60] wire _ldst_addr_matches_WIRE_1 = 1'h0; // @[lsu.scala:1050:60] wire _ldst_addr_matches_WIRE_2 = 1'h0; // @[lsu.scala:1050:60] wire _ldst_addr_matches_WIRE_3 = 1'h0; // @[lsu.scala:1050:60] wire _ldst_addr_matches_WIRE_4 = 1'h0; // @[lsu.scala:1050:60] wire _ldst_addr_matches_WIRE_5 = 1'h0; // @[lsu.scala:1050:60] wire _ldst_addr_matches_WIRE_6 = 1'h0; // @[lsu.scala:1050:60] wire _ldst_addr_matches_WIRE_7 = 1'h0; // @[lsu.scala:1050:60] wire _ldst_addr_matches_WIRE_1_0_0 = 1'h0; // @[lsu.scala:263:49] wire _ldst_addr_matches_WIRE_1_0_1 = 1'h0; // @[lsu.scala:263:49] wire _ldst_addr_matches_WIRE_1_0_2 = 1'h0; // @[lsu.scala:263:49] wire _ldst_addr_matches_WIRE_1_0_3 = 1'h0; // @[lsu.scala:263:49] wire _ldst_addr_matches_WIRE_1_0_4 = 1'h0; // @[lsu.scala:263:49] wire _ldst_addr_matches_WIRE_1_0_5 = 1'h0; // @[lsu.scala:263:49] wire _ldst_addr_matches_WIRE_1_0_6 = 1'h0; // @[lsu.scala:263:49] wire _ldst_addr_matches_WIRE_1_0_7 = 1'h0; // @[lsu.scala:263:49] wire _ldst_forward_matches_WIRE_0 = 1'h0; // @[lsu.scala:1052:60] wire _ldst_forward_matches_WIRE_1 = 1'h0; // @[lsu.scala:1052:60] wire _ldst_forward_matches_WIRE_2 = 1'h0; // @[lsu.scala:1052:60] wire _ldst_forward_matches_WIRE_3 = 1'h0; // @[lsu.scala:1052:60] wire _ldst_forward_matches_WIRE_4 = 1'h0; // @[lsu.scala:1052:60] wire _ldst_forward_matches_WIRE_5 = 1'h0; // @[lsu.scala:1052:60] wire _ldst_forward_matches_WIRE_6 = 1'h0; // @[lsu.scala:1052:60] wire _ldst_forward_matches_WIRE_7 = 1'h0; // @[lsu.scala:1052:60] wire _ldst_forward_matches_WIRE_1_0_0 = 1'h0; // @[lsu.scala:263:49] wire _ldst_forward_matches_WIRE_1_0_1 = 1'h0; // @[lsu.scala:263:49] wire _ldst_forward_matches_WIRE_1_0_2 = 1'h0; // @[lsu.scala:263:49] wire _ldst_forward_matches_WIRE_1_0_3 = 1'h0; // @[lsu.scala:263:49] wire _ldst_forward_matches_WIRE_1_0_4 = 1'h0; // @[lsu.scala:263:49] wire _ldst_forward_matches_WIRE_1_0_5 = 1'h0; // @[lsu.scala:263:49] wire _ldst_forward_matches_WIRE_1_0_6 = 1'h0; // @[lsu.scala:263:49] wire _ldst_forward_matches_WIRE_1_0_7 = 1'h0; // @[lsu.scala:263:49] wire _failed_loads_WIRE_0 = 1'h0; // @[lsu.scala:1054:42] wire _failed_loads_WIRE_1 = 1'h0; // @[lsu.scala:1054:42] wire _failed_loads_WIRE_2 = 1'h0; // @[lsu.scala:1054:42] wire _failed_loads_WIRE_3 = 1'h0; // @[lsu.scala:1054:42] wire _failed_loads_WIRE_4 = 1'h0; // @[lsu.scala:1054:42] wire _failed_loads_WIRE_5 = 1'h0; // @[lsu.scala:1054:42] wire _failed_loads_WIRE_6 = 1'h0; // @[lsu.scala:1054:42] wire _failed_loads_WIRE_7 = 1'h0; // @[lsu.scala:1054:42] wire _nacking_loads_WIRE_0 = 1'h0; // @[lsu.scala:1055:42] wire _nacking_loads_WIRE_1 = 1'h0; // @[lsu.scala:1055:42] wire _nacking_loads_WIRE_2 = 1'h0; // @[lsu.scala:1055:42] wire _nacking_loads_WIRE_3 = 1'h0; // @[lsu.scala:1055:42] wire _nacking_loads_WIRE_4 = 1'h0; // @[lsu.scala:1055:42] wire _nacking_loads_WIRE_5 = 1'h0; // @[lsu.scala:1055:42] wire _nacking_loads_WIRE_6 = 1'h0; // @[lsu.scala:1055:42] wire _nacking_loads_WIRE_7 = 1'h0; // @[lsu.scala:1055:42] wire _searcher_is_older_T = 1'h0; // @[util.scala:363:52] wire _searcher_is_older_T_31 = 1'h0; // @[util.scala:363:78] wire _io_core_clr_unsafe_0_valid_T_3 = 1'h0; // @[lsu.scala:1221:107] wire _dmem_resp_fired_WIRE_0 = 1'h0; // @[lsu.scala:263:49] wire io_core_exe_0_iresp_bits_data_doZero = 1'h0; // @[AMOALU.scala:43:31] wire io_core_exe_0_iresp_bits_data_doZero_1 = 1'h0; // @[AMOALU.scala:43:31] wire io_core_exe_0_iresp_bits_data_doZero_2 = 1'h0; // @[AMOALU.scala:43:31] wire io_core_exe_0_fresp_bits_data_doZero = 1'h0; // @[AMOALU.scala:43:31] wire io_core_exe_0_fresp_bits_data_doZero_1 = 1'h0; // @[AMOALU.scala:43:31] wire io_core_exe_0_fresp_bits_data_doZero_2 = 1'h0; // @[AMOALU.scala:43:31] wire ldq_bits_debug_wb_data_doZero = 1'h0; // @[AMOALU.scala:43:31] wire ldq_bits_debug_wb_data_doZero_1 = 1'h0; // @[AMOALU.scala:43:31] wire ldq_bits_debug_wb_data_doZero_2 = 1'h0; // @[AMOALU.scala:43:31] wire _io_hellacache_s2_xcpt_WIRE_ma_ld = 1'h0; // @[lsu.scala:1528:44] wire _io_hellacache_s2_xcpt_WIRE_ma_st = 1'h0; // @[lsu.scala:1528:44] wire _io_hellacache_s2_xcpt_WIRE_pf_ld = 1'h0; // @[lsu.scala:1528:44] wire _io_hellacache_s2_xcpt_WIRE_pf_st = 1'h0; // @[lsu.scala:1528:44] wire _io_hellacache_s2_xcpt_WIRE_gf_ld = 1'h0; // @[lsu.scala:1528:44] wire _io_hellacache_s2_xcpt_WIRE_gf_st = 1'h0; // @[lsu.scala:1528:44] wire _io_hellacache_s2_xcpt_WIRE_ae_ld = 1'h0; // @[lsu.scala:1528:44] wire _io_hellacache_s2_xcpt_WIRE_ae_st = 1'h0; // @[lsu.scala:1528:44] wire _st_exc_killed_mask_WIRE_0 = 1'h0; // @[lsu.scala:1598:44] wire _st_exc_killed_mask_WIRE_1 = 1'h0; // @[lsu.scala:1598:44] wire _st_exc_killed_mask_WIRE_2 = 1'h0; // @[lsu.scala:1598:44] wire _st_exc_killed_mask_WIRE_3 = 1'h0; // @[lsu.scala:1598:44] wire _st_exc_killed_mask_WIRE_4 = 1'h0; // @[lsu.scala:1598:44] wire _st_exc_killed_mask_WIRE_5 = 1'h0; // @[lsu.scala:1598:44] wire _st_exc_killed_mask_WIRE_6 = 1'h0; // @[lsu.scala:1598:44] wire _st_exc_killed_mask_WIRE_7 = 1'h0; // @[lsu.scala:1598:44] wire stq_0_bits_uop_uop_is_rvc = 1'h0; // @[consts.scala:269:19] wire stq_0_bits_uop_uop_ctrl_fcn_dw = 1'h0; // @[consts.scala:269:19] wire stq_0_bits_uop_uop_ctrl_is_load = 1'h0; // @[consts.scala:269:19] wire stq_0_bits_uop_uop_ctrl_is_sta = 1'h0; // @[consts.scala:269:19] wire stq_0_bits_uop_uop_ctrl_is_std = 1'h0; // @[consts.scala:269:19] wire stq_0_bits_uop_uop_iw_p1_poisoned = 1'h0; // @[consts.scala:269:19] wire stq_0_bits_uop_uop_iw_p2_poisoned = 1'h0; // @[consts.scala:269:19] wire stq_0_bits_uop_uop_is_br = 1'h0; // @[consts.scala:269:19] wire stq_0_bits_uop_uop_is_jalr = 1'h0; // @[consts.scala:269:19] wire stq_0_bits_uop_uop_is_jal = 1'h0; // @[consts.scala:269:19] wire stq_0_bits_uop_uop_is_sfb = 1'h0; // @[consts.scala:269:19] wire stq_0_bits_uop_uop_edge_inst = 1'h0; // @[consts.scala:269:19] wire stq_0_bits_uop_uop_taken = 1'h0; // @[consts.scala:269:19] wire stq_0_bits_uop_uop_prs1_busy = 1'h0; // @[consts.scala:269:19] wire stq_0_bits_uop_uop_prs2_busy = 1'h0; // @[consts.scala:269:19] wire stq_0_bits_uop_uop_prs3_busy = 1'h0; // @[consts.scala:269:19] wire stq_0_bits_uop_uop_ppred_busy = 1'h0; // @[consts.scala:269:19] wire stq_0_bits_uop_uop_exception = 1'h0; // @[consts.scala:269:19] wire stq_0_bits_uop_uop_bypassable = 1'h0; // @[consts.scala:269:19] wire stq_0_bits_uop_uop_mem_signed = 1'h0; // @[consts.scala:269:19] wire stq_0_bits_uop_uop_is_fence = 1'h0; // @[consts.scala:269:19] wire stq_0_bits_uop_uop_is_fencei = 1'h0; // @[consts.scala:269:19] wire stq_0_bits_uop_uop_is_amo = 1'h0; // @[consts.scala:269:19] wire stq_0_bits_uop_uop_uses_ldq = 1'h0; // @[consts.scala:269:19] wire stq_0_bits_uop_uop_uses_stq = 1'h0; // @[consts.scala:269:19] wire stq_0_bits_uop_uop_is_sys_pc2epc = 1'h0; // @[consts.scala:269:19] wire stq_0_bits_uop_uop_is_unique = 1'h0; // @[consts.scala:269:19] wire stq_0_bits_uop_uop_flush_on_commit = 1'h0; // @[consts.scala:269:19] wire stq_0_bits_uop_uop_ldst_is_rs1 = 1'h0; // @[consts.scala:269:19] wire stq_0_bits_uop_uop_ldst_val = 1'h0; // @[consts.scala:269:19] wire stq_0_bits_uop_uop_frs3_en = 1'h0; // @[consts.scala:269:19] wire stq_0_bits_uop_uop_fp_val = 1'h0; // @[consts.scala:269:19] wire stq_0_bits_uop_uop_fp_single = 1'h0; // @[consts.scala:269:19] wire stq_0_bits_uop_uop_xcpt_pf_if = 1'h0; // @[consts.scala:269:19] wire stq_0_bits_uop_uop_xcpt_ae_if = 1'h0; // @[consts.scala:269:19] wire stq_0_bits_uop_uop_xcpt_ma_if = 1'h0; // @[consts.scala:269:19] wire stq_0_bits_uop_uop_bp_debug_if = 1'h0; // @[consts.scala:269:19] wire stq_0_bits_uop_uop_bp_xcpt_if = 1'h0; // @[consts.scala:269:19] wire stq_0_bits_uop_cs_fcn_dw = 1'h0; // @[consts.scala:279:18] wire stq_0_bits_uop_cs_is_load = 1'h0; // @[consts.scala:279:18] wire stq_0_bits_uop_cs_is_sta = 1'h0; // @[consts.scala:279:18] wire stq_0_bits_uop_cs_is_std = 1'h0; // @[consts.scala:279:18] wire stq_1_bits_uop_uop_is_rvc = 1'h0; // @[consts.scala:269:19] wire stq_1_bits_uop_uop_ctrl_fcn_dw = 1'h0; // @[consts.scala:269:19] wire stq_1_bits_uop_uop_ctrl_is_load = 1'h0; // @[consts.scala:269:19] wire stq_1_bits_uop_uop_ctrl_is_sta = 1'h0; // @[consts.scala:269:19] wire stq_1_bits_uop_uop_ctrl_is_std = 1'h0; // @[consts.scala:269:19] wire stq_1_bits_uop_uop_iw_p1_poisoned = 1'h0; // @[consts.scala:269:19] wire stq_1_bits_uop_uop_iw_p2_poisoned = 1'h0; // @[consts.scala:269:19] wire stq_1_bits_uop_uop_is_br = 1'h0; // @[consts.scala:269:19] wire stq_1_bits_uop_uop_is_jalr = 1'h0; // @[consts.scala:269:19] wire stq_1_bits_uop_uop_is_jal = 1'h0; // @[consts.scala:269:19] wire stq_1_bits_uop_uop_is_sfb = 1'h0; // @[consts.scala:269:19] wire stq_1_bits_uop_uop_edge_inst = 1'h0; // @[consts.scala:269:19] wire stq_1_bits_uop_uop_taken = 1'h0; // @[consts.scala:269:19] wire stq_1_bits_uop_uop_prs1_busy = 1'h0; // @[consts.scala:269:19] wire stq_1_bits_uop_uop_prs2_busy = 1'h0; // @[consts.scala:269:19] wire stq_1_bits_uop_uop_prs3_busy = 1'h0; // @[consts.scala:269:19] wire stq_1_bits_uop_uop_ppred_busy = 1'h0; // @[consts.scala:269:19] wire stq_1_bits_uop_uop_exception = 1'h0; // @[consts.scala:269:19] wire stq_1_bits_uop_uop_bypassable = 1'h0; // @[consts.scala:269:19] wire stq_1_bits_uop_uop_mem_signed = 1'h0; // @[consts.scala:269:19] wire stq_1_bits_uop_uop_is_fence = 1'h0; // @[consts.scala:269:19] wire stq_1_bits_uop_uop_is_fencei = 1'h0; // @[consts.scala:269:19] wire stq_1_bits_uop_uop_is_amo = 1'h0; // @[consts.scala:269:19] wire stq_1_bits_uop_uop_uses_ldq = 1'h0; // @[consts.scala:269:19] wire stq_1_bits_uop_uop_uses_stq = 1'h0; // @[consts.scala:269:19] wire stq_1_bits_uop_uop_is_sys_pc2epc = 1'h0; // @[consts.scala:269:19] wire stq_1_bits_uop_uop_is_unique = 1'h0; // @[consts.scala:269:19] wire stq_1_bits_uop_uop_flush_on_commit = 1'h0; // @[consts.scala:269:19] wire stq_1_bits_uop_uop_ldst_is_rs1 = 1'h0; // @[consts.scala:269:19] wire stq_1_bits_uop_uop_ldst_val = 1'h0; // @[consts.scala:269:19] wire stq_1_bits_uop_uop_frs3_en = 1'h0; // @[consts.scala:269:19] wire stq_1_bits_uop_uop_fp_val = 1'h0; // @[consts.scala:269:19] wire stq_1_bits_uop_uop_fp_single = 1'h0; // @[consts.scala:269:19] wire stq_1_bits_uop_uop_xcpt_pf_if = 1'h0; // @[consts.scala:269:19] wire stq_1_bits_uop_uop_xcpt_ae_if = 1'h0; // @[consts.scala:269:19] wire stq_1_bits_uop_uop_xcpt_ma_if = 1'h0; // @[consts.scala:269:19] wire stq_1_bits_uop_uop_bp_debug_if = 1'h0; // @[consts.scala:269:19] wire stq_1_bits_uop_uop_bp_xcpt_if = 1'h0; // @[consts.scala:269:19] wire stq_1_bits_uop_cs_fcn_dw = 1'h0; // @[consts.scala:279:18] wire stq_1_bits_uop_cs_is_load = 1'h0; // @[consts.scala:279:18] wire stq_1_bits_uop_cs_is_sta = 1'h0; // @[consts.scala:279:18] wire stq_1_bits_uop_cs_is_std = 1'h0; // @[consts.scala:279:18] wire stq_2_bits_uop_uop_is_rvc = 1'h0; // @[consts.scala:269:19] wire stq_2_bits_uop_uop_ctrl_fcn_dw = 1'h0; // @[consts.scala:269:19] wire stq_2_bits_uop_uop_ctrl_is_load = 1'h0; // @[consts.scala:269:19] wire stq_2_bits_uop_uop_ctrl_is_sta = 1'h0; // @[consts.scala:269:19] wire stq_2_bits_uop_uop_ctrl_is_std = 1'h0; // @[consts.scala:269:19] wire stq_2_bits_uop_uop_iw_p1_poisoned = 1'h0; // @[consts.scala:269:19] wire stq_2_bits_uop_uop_iw_p2_poisoned = 1'h0; // @[consts.scala:269:19] wire stq_2_bits_uop_uop_is_br = 1'h0; // @[consts.scala:269:19] wire stq_2_bits_uop_uop_is_jalr = 1'h0; // @[consts.scala:269:19] wire stq_2_bits_uop_uop_is_jal = 1'h0; // @[consts.scala:269:19] wire stq_2_bits_uop_uop_is_sfb = 1'h0; // @[consts.scala:269:19] wire stq_2_bits_uop_uop_edge_inst = 1'h0; // @[consts.scala:269:19] wire stq_2_bits_uop_uop_taken = 1'h0; // @[consts.scala:269:19] wire stq_2_bits_uop_uop_prs1_busy = 1'h0; // @[consts.scala:269:19] wire stq_2_bits_uop_uop_prs2_busy = 1'h0; // @[consts.scala:269:19] wire stq_2_bits_uop_uop_prs3_busy = 1'h0; // @[consts.scala:269:19] wire stq_2_bits_uop_uop_ppred_busy = 1'h0; // @[consts.scala:269:19] wire stq_2_bits_uop_uop_exception = 1'h0; // @[consts.scala:269:19] wire stq_2_bits_uop_uop_bypassable = 1'h0; // @[consts.scala:269:19] wire stq_2_bits_uop_uop_mem_signed = 1'h0; // @[consts.scala:269:19] wire stq_2_bits_uop_uop_is_fence = 1'h0; // @[consts.scala:269:19] wire stq_2_bits_uop_uop_is_fencei = 1'h0; // @[consts.scala:269:19] wire stq_2_bits_uop_uop_is_amo = 1'h0; // @[consts.scala:269:19] wire stq_2_bits_uop_uop_uses_ldq = 1'h0; // @[consts.scala:269:19] wire stq_2_bits_uop_uop_uses_stq = 1'h0; // @[consts.scala:269:19] wire stq_2_bits_uop_uop_is_sys_pc2epc = 1'h0; // @[consts.scala:269:19] wire stq_2_bits_uop_uop_is_unique = 1'h0; // @[consts.scala:269:19] wire stq_2_bits_uop_uop_flush_on_commit = 1'h0; // @[consts.scala:269:19] wire stq_2_bits_uop_uop_ldst_is_rs1 = 1'h0; // @[consts.scala:269:19] wire stq_2_bits_uop_uop_ldst_val = 1'h0; // @[consts.scala:269:19] wire stq_2_bits_uop_uop_frs3_en = 1'h0; // @[consts.scala:269:19] wire stq_2_bits_uop_uop_fp_val = 1'h0; // @[consts.scala:269:19] wire stq_2_bits_uop_uop_fp_single = 1'h0; // @[consts.scala:269:19] wire stq_2_bits_uop_uop_xcpt_pf_if = 1'h0; // @[consts.scala:269:19] wire stq_2_bits_uop_uop_xcpt_ae_if = 1'h0; // @[consts.scala:269:19] wire stq_2_bits_uop_uop_xcpt_ma_if = 1'h0; // @[consts.scala:269:19] wire stq_2_bits_uop_uop_bp_debug_if = 1'h0; // @[consts.scala:269:19] wire stq_2_bits_uop_uop_bp_xcpt_if = 1'h0; // @[consts.scala:269:19] wire stq_2_bits_uop_cs_fcn_dw = 1'h0; // @[consts.scala:279:18] wire stq_2_bits_uop_cs_is_load = 1'h0; // @[consts.scala:279:18] wire stq_2_bits_uop_cs_is_sta = 1'h0; // @[consts.scala:279:18] wire stq_2_bits_uop_cs_is_std = 1'h0; // @[consts.scala:279:18] wire stq_3_bits_uop_uop_is_rvc = 1'h0; // @[consts.scala:269:19] wire stq_3_bits_uop_uop_ctrl_fcn_dw = 1'h0; // @[consts.scala:269:19] wire stq_3_bits_uop_uop_ctrl_is_load = 1'h0; // @[consts.scala:269:19] wire stq_3_bits_uop_uop_ctrl_is_sta = 1'h0; // @[consts.scala:269:19] wire stq_3_bits_uop_uop_ctrl_is_std = 1'h0; // @[consts.scala:269:19] wire stq_3_bits_uop_uop_iw_p1_poisoned = 1'h0; // @[consts.scala:269:19] wire stq_3_bits_uop_uop_iw_p2_poisoned = 1'h0; // @[consts.scala:269:19] wire stq_3_bits_uop_uop_is_br = 1'h0; // @[consts.scala:269:19] wire stq_3_bits_uop_uop_is_jalr = 1'h0; // @[consts.scala:269:19] wire stq_3_bits_uop_uop_is_jal = 1'h0; // @[consts.scala:269:19] wire stq_3_bits_uop_uop_is_sfb = 1'h0; // @[consts.scala:269:19] wire stq_3_bits_uop_uop_edge_inst = 1'h0; // @[consts.scala:269:19] wire stq_3_bits_uop_uop_taken = 1'h0; // @[consts.scala:269:19] wire stq_3_bits_uop_uop_prs1_busy = 1'h0; // @[consts.scala:269:19] wire stq_3_bits_uop_uop_prs2_busy = 1'h0; // @[consts.scala:269:19] wire stq_3_bits_uop_uop_prs3_busy = 1'h0; // @[consts.scala:269:19] wire stq_3_bits_uop_uop_ppred_busy = 1'h0; // @[consts.scala:269:19] wire stq_3_bits_uop_uop_exception = 1'h0; // @[consts.scala:269:19] wire stq_3_bits_uop_uop_bypassable = 1'h0; // @[consts.scala:269:19] wire stq_3_bits_uop_uop_mem_signed = 1'h0; // @[consts.scala:269:19] wire stq_3_bits_uop_uop_is_fence = 1'h0; // @[consts.scala:269:19] wire stq_3_bits_uop_uop_is_fencei = 1'h0; // @[consts.scala:269:19] wire stq_3_bits_uop_uop_is_amo = 1'h0; // @[consts.scala:269:19] wire stq_3_bits_uop_uop_uses_ldq = 1'h0; // @[consts.scala:269:19] wire stq_3_bits_uop_uop_uses_stq = 1'h0; // @[consts.scala:269:19] wire stq_3_bits_uop_uop_is_sys_pc2epc = 1'h0; // @[consts.scala:269:19] wire stq_3_bits_uop_uop_is_unique = 1'h0; // @[consts.scala:269:19] wire stq_3_bits_uop_uop_flush_on_commit = 1'h0; // @[consts.scala:269:19] wire stq_3_bits_uop_uop_ldst_is_rs1 = 1'h0; // @[consts.scala:269:19] wire stq_3_bits_uop_uop_ldst_val = 1'h0; // @[consts.scala:269:19] wire stq_3_bits_uop_uop_frs3_en = 1'h0; // @[consts.scala:269:19] wire stq_3_bits_uop_uop_fp_val = 1'h0; // @[consts.scala:269:19] wire stq_3_bits_uop_uop_fp_single = 1'h0; // @[consts.scala:269:19] wire stq_3_bits_uop_uop_xcpt_pf_if = 1'h0; // @[consts.scala:269:19] wire stq_3_bits_uop_uop_xcpt_ae_if = 1'h0; // @[consts.scala:269:19] wire stq_3_bits_uop_uop_xcpt_ma_if = 1'h0; // @[consts.scala:269:19] wire stq_3_bits_uop_uop_bp_debug_if = 1'h0; // @[consts.scala:269:19] wire stq_3_bits_uop_uop_bp_xcpt_if = 1'h0; // @[consts.scala:269:19] wire stq_3_bits_uop_cs_fcn_dw = 1'h0; // @[consts.scala:279:18] wire stq_3_bits_uop_cs_is_load = 1'h0; // @[consts.scala:279:18] wire stq_3_bits_uop_cs_is_sta = 1'h0; // @[consts.scala:279:18] wire stq_3_bits_uop_cs_is_std = 1'h0; // @[consts.scala:279:18] wire stq_4_bits_uop_uop_is_rvc = 1'h0; // @[consts.scala:269:19] wire stq_4_bits_uop_uop_ctrl_fcn_dw = 1'h0; // @[consts.scala:269:19] wire stq_4_bits_uop_uop_ctrl_is_load = 1'h0; // @[consts.scala:269:19] wire stq_4_bits_uop_uop_ctrl_is_sta = 1'h0; // @[consts.scala:269:19] wire stq_4_bits_uop_uop_ctrl_is_std = 1'h0; // @[consts.scala:269:19] wire stq_4_bits_uop_uop_iw_p1_poisoned = 1'h0; // @[consts.scala:269:19] wire stq_4_bits_uop_uop_iw_p2_poisoned = 1'h0; // @[consts.scala:269:19] wire stq_4_bits_uop_uop_is_br = 1'h0; // @[consts.scala:269:19] wire stq_4_bits_uop_uop_is_jalr = 1'h0; // @[consts.scala:269:19] wire stq_4_bits_uop_uop_is_jal = 1'h0; // @[consts.scala:269:19] wire stq_4_bits_uop_uop_is_sfb = 1'h0; // @[consts.scala:269:19] wire stq_4_bits_uop_uop_edge_inst = 1'h0; // @[consts.scala:269:19] wire stq_4_bits_uop_uop_taken = 1'h0; // @[consts.scala:269:19] wire stq_4_bits_uop_uop_prs1_busy = 1'h0; // @[consts.scala:269:19] wire stq_4_bits_uop_uop_prs2_busy = 1'h0; // @[consts.scala:269:19] wire stq_4_bits_uop_uop_prs3_busy = 1'h0; // @[consts.scala:269:19] wire stq_4_bits_uop_uop_ppred_busy = 1'h0; // @[consts.scala:269:19] wire stq_4_bits_uop_uop_exception = 1'h0; // @[consts.scala:269:19] wire stq_4_bits_uop_uop_bypassable = 1'h0; // @[consts.scala:269:19] wire stq_4_bits_uop_uop_mem_signed = 1'h0; // @[consts.scala:269:19] wire stq_4_bits_uop_uop_is_fence = 1'h0; // @[consts.scala:269:19] wire stq_4_bits_uop_uop_is_fencei = 1'h0; // @[consts.scala:269:19] wire stq_4_bits_uop_uop_is_amo = 1'h0; // @[consts.scala:269:19] wire stq_4_bits_uop_uop_uses_ldq = 1'h0; // @[consts.scala:269:19] wire stq_4_bits_uop_uop_uses_stq = 1'h0; // @[consts.scala:269:19] wire stq_4_bits_uop_uop_is_sys_pc2epc = 1'h0; // @[consts.scala:269:19] wire stq_4_bits_uop_uop_is_unique = 1'h0; // @[consts.scala:269:19] wire stq_4_bits_uop_uop_flush_on_commit = 1'h0; // @[consts.scala:269:19] wire stq_4_bits_uop_uop_ldst_is_rs1 = 1'h0; // @[consts.scala:269:19] wire stq_4_bits_uop_uop_ldst_val = 1'h0; // @[consts.scala:269:19] wire stq_4_bits_uop_uop_frs3_en = 1'h0; // @[consts.scala:269:19] wire stq_4_bits_uop_uop_fp_val = 1'h0; // @[consts.scala:269:19] wire stq_4_bits_uop_uop_fp_single = 1'h0; // @[consts.scala:269:19] wire stq_4_bits_uop_uop_xcpt_pf_if = 1'h0; // @[consts.scala:269:19] wire stq_4_bits_uop_uop_xcpt_ae_if = 1'h0; // @[consts.scala:269:19] wire stq_4_bits_uop_uop_xcpt_ma_if = 1'h0; // @[consts.scala:269:19] wire stq_4_bits_uop_uop_bp_debug_if = 1'h0; // @[consts.scala:269:19] wire stq_4_bits_uop_uop_bp_xcpt_if = 1'h0; // @[consts.scala:269:19] wire stq_4_bits_uop_cs_fcn_dw = 1'h0; // @[consts.scala:279:18] wire stq_4_bits_uop_cs_is_load = 1'h0; // @[consts.scala:279:18] wire stq_4_bits_uop_cs_is_sta = 1'h0; // @[consts.scala:279:18] wire stq_4_bits_uop_cs_is_std = 1'h0; // @[consts.scala:279:18] wire stq_5_bits_uop_uop_is_rvc = 1'h0; // @[consts.scala:269:19] wire stq_5_bits_uop_uop_ctrl_fcn_dw = 1'h0; // @[consts.scala:269:19] wire stq_5_bits_uop_uop_ctrl_is_load = 1'h0; // @[consts.scala:269:19] wire stq_5_bits_uop_uop_ctrl_is_sta = 1'h0; // @[consts.scala:269:19] wire stq_5_bits_uop_uop_ctrl_is_std = 1'h0; // @[consts.scala:269:19] wire stq_5_bits_uop_uop_iw_p1_poisoned = 1'h0; // @[consts.scala:269:19] wire stq_5_bits_uop_uop_iw_p2_poisoned = 1'h0; // @[consts.scala:269:19] wire stq_5_bits_uop_uop_is_br = 1'h0; // @[consts.scala:269:19] wire stq_5_bits_uop_uop_is_jalr = 1'h0; // @[consts.scala:269:19] wire stq_5_bits_uop_uop_is_jal = 1'h0; // @[consts.scala:269:19] wire stq_5_bits_uop_uop_is_sfb = 1'h0; // @[consts.scala:269:19] wire stq_5_bits_uop_uop_edge_inst = 1'h0; // @[consts.scala:269:19] wire stq_5_bits_uop_uop_taken = 1'h0; // @[consts.scala:269:19] wire stq_5_bits_uop_uop_prs1_busy = 1'h0; // @[consts.scala:269:19] wire stq_5_bits_uop_uop_prs2_busy = 1'h0; // @[consts.scala:269:19] wire stq_5_bits_uop_uop_prs3_busy = 1'h0; // @[consts.scala:269:19] wire stq_5_bits_uop_uop_ppred_busy = 1'h0; // @[consts.scala:269:19] wire stq_5_bits_uop_uop_exception = 1'h0; // @[consts.scala:269:19] wire stq_5_bits_uop_uop_bypassable = 1'h0; // @[consts.scala:269:19] wire stq_5_bits_uop_uop_mem_signed = 1'h0; // @[consts.scala:269:19] wire stq_5_bits_uop_uop_is_fence = 1'h0; // @[consts.scala:269:19] wire stq_5_bits_uop_uop_is_fencei = 1'h0; // @[consts.scala:269:19] wire stq_5_bits_uop_uop_is_amo = 1'h0; // @[consts.scala:269:19] wire stq_5_bits_uop_uop_uses_ldq = 1'h0; // @[consts.scala:269:19] wire stq_5_bits_uop_uop_uses_stq = 1'h0; // @[consts.scala:269:19] wire stq_5_bits_uop_uop_is_sys_pc2epc = 1'h0; // @[consts.scala:269:19] wire stq_5_bits_uop_uop_is_unique = 1'h0; // @[consts.scala:269:19] wire stq_5_bits_uop_uop_flush_on_commit = 1'h0; // @[consts.scala:269:19] wire stq_5_bits_uop_uop_ldst_is_rs1 = 1'h0; // @[consts.scala:269:19] wire stq_5_bits_uop_uop_ldst_val = 1'h0; // @[consts.scala:269:19] wire stq_5_bits_uop_uop_frs3_en = 1'h0; // @[consts.scala:269:19] wire stq_5_bits_uop_uop_fp_val = 1'h0; // @[consts.scala:269:19] wire stq_5_bits_uop_uop_fp_single = 1'h0; // @[consts.scala:269:19] wire stq_5_bits_uop_uop_xcpt_pf_if = 1'h0; // @[consts.scala:269:19] wire stq_5_bits_uop_uop_xcpt_ae_if = 1'h0; // @[consts.scala:269:19] wire stq_5_bits_uop_uop_xcpt_ma_if = 1'h0; // @[consts.scala:269:19] wire stq_5_bits_uop_uop_bp_debug_if = 1'h0; // @[consts.scala:269:19] wire stq_5_bits_uop_uop_bp_xcpt_if = 1'h0; // @[consts.scala:269:19] wire stq_5_bits_uop_cs_fcn_dw = 1'h0; // @[consts.scala:279:18] wire stq_5_bits_uop_cs_is_load = 1'h0; // @[consts.scala:279:18] wire stq_5_bits_uop_cs_is_sta = 1'h0; // @[consts.scala:279:18] wire stq_5_bits_uop_cs_is_std = 1'h0; // @[consts.scala:279:18] wire stq_6_bits_uop_uop_is_rvc = 1'h0; // @[consts.scala:269:19] wire stq_6_bits_uop_uop_ctrl_fcn_dw = 1'h0; // @[consts.scala:269:19] wire stq_6_bits_uop_uop_ctrl_is_load = 1'h0; // @[consts.scala:269:19] wire stq_6_bits_uop_uop_ctrl_is_sta = 1'h0; // @[consts.scala:269:19] wire stq_6_bits_uop_uop_ctrl_is_std = 1'h0; // @[consts.scala:269:19] wire stq_6_bits_uop_uop_iw_p1_poisoned = 1'h0; // @[consts.scala:269:19] wire stq_6_bits_uop_uop_iw_p2_poisoned = 1'h0; // @[consts.scala:269:19] wire stq_6_bits_uop_uop_is_br = 1'h0; // @[consts.scala:269:19] wire stq_6_bits_uop_uop_is_jalr = 1'h0; // @[consts.scala:269:19] wire stq_6_bits_uop_uop_is_jal = 1'h0; // @[consts.scala:269:19] wire stq_6_bits_uop_uop_is_sfb = 1'h0; // @[consts.scala:269:19] wire stq_6_bits_uop_uop_edge_inst = 1'h0; // @[consts.scala:269:19] wire stq_6_bits_uop_uop_taken = 1'h0; // @[consts.scala:269:19] wire stq_6_bits_uop_uop_prs1_busy = 1'h0; // @[consts.scala:269:19] wire stq_6_bits_uop_uop_prs2_busy = 1'h0; // @[consts.scala:269:19] wire stq_6_bits_uop_uop_prs3_busy = 1'h0; // @[consts.scala:269:19] wire stq_6_bits_uop_uop_ppred_busy = 1'h0; // @[consts.scala:269:19] wire stq_6_bits_uop_uop_exception = 1'h0; // @[consts.scala:269:19] wire stq_6_bits_uop_uop_bypassable = 1'h0; // @[consts.scala:269:19] wire stq_6_bits_uop_uop_mem_signed = 1'h0; // @[consts.scala:269:19] wire stq_6_bits_uop_uop_is_fence = 1'h0; // @[consts.scala:269:19] wire stq_6_bits_uop_uop_is_fencei = 1'h0; // @[consts.scala:269:19] wire stq_6_bits_uop_uop_is_amo = 1'h0; // @[consts.scala:269:19] wire stq_6_bits_uop_uop_uses_ldq = 1'h0; // @[consts.scala:269:19] wire stq_6_bits_uop_uop_uses_stq = 1'h0; // @[consts.scala:269:19] wire stq_6_bits_uop_uop_is_sys_pc2epc = 1'h0; // @[consts.scala:269:19] wire stq_6_bits_uop_uop_is_unique = 1'h0; // @[consts.scala:269:19] wire stq_6_bits_uop_uop_flush_on_commit = 1'h0; // @[consts.scala:269:19] wire stq_6_bits_uop_uop_ldst_is_rs1 = 1'h0; // @[consts.scala:269:19] wire stq_6_bits_uop_uop_ldst_val = 1'h0; // @[consts.scala:269:19] wire stq_6_bits_uop_uop_frs3_en = 1'h0; // @[consts.scala:269:19] wire stq_6_bits_uop_uop_fp_val = 1'h0; // @[consts.scala:269:19] wire stq_6_bits_uop_uop_fp_single = 1'h0; // @[consts.scala:269:19] wire stq_6_bits_uop_uop_xcpt_pf_if = 1'h0; // @[consts.scala:269:19] wire stq_6_bits_uop_uop_xcpt_ae_if = 1'h0; // @[consts.scala:269:19] wire stq_6_bits_uop_uop_xcpt_ma_if = 1'h0; // @[consts.scala:269:19] wire stq_6_bits_uop_uop_bp_debug_if = 1'h0; // @[consts.scala:269:19] wire stq_6_bits_uop_uop_bp_xcpt_if = 1'h0; // @[consts.scala:269:19] wire stq_6_bits_uop_cs_fcn_dw = 1'h0; // @[consts.scala:279:18] wire stq_6_bits_uop_cs_is_load = 1'h0; // @[consts.scala:279:18] wire stq_6_bits_uop_cs_is_sta = 1'h0; // @[consts.scala:279:18] wire stq_6_bits_uop_cs_is_std = 1'h0; // @[consts.scala:279:18] wire stq_7_bits_uop_uop_is_rvc = 1'h0; // @[consts.scala:269:19] wire stq_7_bits_uop_uop_ctrl_fcn_dw = 1'h0; // @[consts.scala:269:19] wire stq_7_bits_uop_uop_ctrl_is_load = 1'h0; // @[consts.scala:269:19] wire stq_7_bits_uop_uop_ctrl_is_sta = 1'h0; // @[consts.scala:269:19] wire stq_7_bits_uop_uop_ctrl_is_std = 1'h0; // @[consts.scala:269:19] wire stq_7_bits_uop_uop_iw_p1_poisoned = 1'h0; // @[consts.scala:269:19] wire stq_7_bits_uop_uop_iw_p2_poisoned = 1'h0; // @[consts.scala:269:19] wire stq_7_bits_uop_uop_is_br = 1'h0; // @[consts.scala:269:19] wire stq_7_bits_uop_uop_is_jalr = 1'h0; // @[consts.scala:269:19] wire stq_7_bits_uop_uop_is_jal = 1'h0; // @[consts.scala:269:19] wire stq_7_bits_uop_uop_is_sfb = 1'h0; // @[consts.scala:269:19] wire stq_7_bits_uop_uop_edge_inst = 1'h0; // @[consts.scala:269:19] wire stq_7_bits_uop_uop_taken = 1'h0; // @[consts.scala:269:19] wire stq_7_bits_uop_uop_prs1_busy = 1'h0; // @[consts.scala:269:19] wire stq_7_bits_uop_uop_prs2_busy = 1'h0; // @[consts.scala:269:19] wire stq_7_bits_uop_uop_prs3_busy = 1'h0; // @[consts.scala:269:19] wire stq_7_bits_uop_uop_ppred_busy = 1'h0; // @[consts.scala:269:19] wire stq_7_bits_uop_uop_exception = 1'h0; // @[consts.scala:269:19] wire stq_7_bits_uop_uop_bypassable = 1'h0; // @[consts.scala:269:19] wire stq_7_bits_uop_uop_mem_signed = 1'h0; // @[consts.scala:269:19] wire stq_7_bits_uop_uop_is_fence = 1'h0; // @[consts.scala:269:19] wire stq_7_bits_uop_uop_is_fencei = 1'h0; // @[consts.scala:269:19] wire stq_7_bits_uop_uop_is_amo = 1'h0; // @[consts.scala:269:19] wire stq_7_bits_uop_uop_uses_ldq = 1'h0; // @[consts.scala:269:19] wire stq_7_bits_uop_uop_uses_stq = 1'h0; // @[consts.scala:269:19] wire stq_7_bits_uop_uop_is_sys_pc2epc = 1'h0; // @[consts.scala:269:19] wire stq_7_bits_uop_uop_is_unique = 1'h0; // @[consts.scala:269:19] wire stq_7_bits_uop_uop_flush_on_commit = 1'h0; // @[consts.scala:269:19] wire stq_7_bits_uop_uop_ldst_is_rs1 = 1'h0; // @[consts.scala:269:19] wire stq_7_bits_uop_uop_ldst_val = 1'h0; // @[consts.scala:269:19] wire stq_7_bits_uop_uop_frs3_en = 1'h0; // @[consts.scala:269:19] wire stq_7_bits_uop_uop_fp_val = 1'h0; // @[consts.scala:269:19] wire stq_7_bits_uop_uop_fp_single = 1'h0; // @[consts.scala:269:19] wire stq_7_bits_uop_uop_xcpt_pf_if = 1'h0; // @[consts.scala:269:19] wire stq_7_bits_uop_uop_xcpt_ae_if = 1'h0; // @[consts.scala:269:19] wire stq_7_bits_uop_uop_xcpt_ma_if = 1'h0; // @[consts.scala:269:19] wire stq_7_bits_uop_uop_bp_debug_if = 1'h0; // @[consts.scala:269:19] wire stq_7_bits_uop_uop_bp_xcpt_if = 1'h0; // @[consts.scala:269:19] wire stq_7_bits_uop_cs_fcn_dw = 1'h0; // @[consts.scala:279:18] wire stq_7_bits_uop_cs_is_load = 1'h0; // @[consts.scala:279:18] wire stq_7_bits_uop_cs_is_sta = 1'h0; // @[consts.scala:279:18] wire stq_7_bits_uop_cs_is_std = 1'h0; // @[consts.scala:279:18] wire [7:0] io_ptw_status_zero1 = 8'h0; // @[lsu.scala:201:7] wire [7:0] io_ptw_gstatus_zero1 = 8'h0; // @[lsu.scala:201:7] wire [7:0] io_core_exe_0_req_bits_fflags_bits_uop_br_mask = 8'h0; // @[lsu.scala:201:7] wire [7:0] io_core_exe_0_iresp_bits_fflags_bits_uop_br_mask = 8'h0; // @[lsu.scala:201:7] wire [7:0] io_core_exe_0_fresp_bits_fflags_bits_uop_br_mask = 8'h0; // @[lsu.scala:201:7] wire [7:0] io_hellacache_req_bits_mask = 8'h0; // @[lsu.scala:201:7] wire [7:0] io_hellacache_s1_data_mask = 8'h0; // @[lsu.scala:201:7] wire [7:0] io_hellacache_resp_bits_mask = 8'h0; // @[lsu.scala:201:7] wire [7:0] _exe_req_WIRE_0_bits_fflags_bits_uop_br_mask = 8'h0; // @[lsu.scala:383:33] wire [7:0] exe_req_0_bits_fflags_bits_uop_br_mask = 8'h0; // @[lsu.scala:383:25] wire [7:0] exe_tlb_uop_uop_br_mask = 8'h0; // @[consts.scala:269:19] wire [7:0] exe_tlb_uop_uop_1_br_mask = 8'h0; // @[consts.scala:269:19] wire [7:0] _exe_tlb_uop_T_3_br_mask = 8'h0; // @[lsu.scala:602:24] wire [7:0] dmem_req_0_bits_uop_uop_br_mask = 8'h0; // @[consts.scala:269:19] wire [7:0] _dmem_req_0_bits_data_T_16 = 8'h0; // @[AMOALU.scala:29:69] wire [7:0] _mem_ldq_e_WIRE_bits_uop_br_mask = 8'h0; // @[lsu.scala:918:90] wire [7:0] _mem_ldq_e_WIRE_bits_st_dep_mask = 8'h0; // @[lsu.scala:918:90] wire [7:0] _mem_stq_e_WIRE_bits_uop_br_mask = 8'h0; // @[lsu.scala:922:89] wire [7:0] lcam_uop_uop_br_mask = 8'h0; // @[consts.scala:269:19] wire [7:0] stq_0_bits_uop_uop_br_mask = 8'h0; // @[consts.scala:269:19] wire [7:0] stq_1_bits_uop_uop_br_mask = 8'h0; // @[consts.scala:269:19] wire [7:0] stq_2_bits_uop_uop_br_mask = 8'h0; // @[consts.scala:269:19] wire [7:0] stq_3_bits_uop_uop_br_mask = 8'h0; // @[consts.scala:269:19] wire [7:0] stq_4_bits_uop_uop_br_mask = 8'h0; // @[consts.scala:269:19] wire [7:0] stq_5_bits_uop_uop_br_mask = 8'h0; // @[consts.scala:269:19] wire [7:0] stq_6_bits_uop_uop_br_mask = 8'h0; // @[consts.scala:269:19] wire [7:0] stq_7_bits_uop_uop_br_mask = 8'h0; // @[consts.scala:269:19] wire [1:0] io_ptw_status_xs = 2'h0; // @[lsu.scala:201:7] wire [1:0] io_ptw_status_vs = 2'h0; // @[lsu.scala:201:7] wire [1:0] io_ptw_hstatus_vsxl = 2'h0; // @[lsu.scala:201:7] wire [1:0] io_ptw_hstatus_zero3 = 2'h0; // @[lsu.scala:201:7] wire [1:0] io_ptw_hstatus_zero2 = 2'h0; // @[lsu.scala:201:7] wire [1:0] io_ptw_gstatus_dprv = 2'h0; // @[lsu.scala:201:7] wire [1:0] io_ptw_gstatus_prv = 2'h0; // @[lsu.scala:201:7] wire [1:0] io_ptw_gstatus_sxl = 2'h0; // @[lsu.scala:201:7] wire [1:0] io_ptw_gstatus_uxl = 2'h0; // @[lsu.scala:201:7] wire [1:0] io_ptw_gstatus_xs = 2'h0; // @[lsu.scala:201:7] wire [1:0] io_ptw_gstatus_fs = 2'h0; // @[lsu.scala:201:7] wire [1:0] io_ptw_gstatus_mpp = 2'h0; // @[lsu.scala:201:7] wire [1:0] io_ptw_gstatus_vs = 2'h0; // @[lsu.scala:201:7] wire [1:0] io_ptw_pmp_0_cfg_res = 2'h0; // @[lsu.scala:201:7] wire [1:0] io_ptw_pmp_1_cfg_res = 2'h0; // @[lsu.scala:201:7] wire [1:0] io_ptw_pmp_2_cfg_res = 2'h0; // @[lsu.scala:201:7] wire [1:0] io_ptw_pmp_3_cfg_res = 2'h0; // @[lsu.scala:201:7] wire [1:0] io_ptw_pmp_4_cfg_res = 2'h0; // @[lsu.scala:201:7] wire [1:0] io_ptw_pmp_5_cfg_res = 2'h0; // @[lsu.scala:201:7] wire [1:0] io_ptw_pmp_6_cfg_res = 2'h0; // @[lsu.scala:201:7] wire [1:0] io_ptw_pmp_7_cfg_res = 2'h0; // @[lsu.scala:201:7] wire [1:0] io_core_exe_0_req_bits_fflags_bits_uop_ctrl_op1_sel = 2'h0; // @[lsu.scala:201:7] wire [1:0] io_core_exe_0_req_bits_fflags_bits_uop_iw_state = 2'h0; // @[lsu.scala:201:7] wire [1:0] io_core_exe_0_req_bits_fflags_bits_uop_rxq_idx = 2'h0; // @[lsu.scala:201:7] wire [1:0] io_core_exe_0_req_bits_fflags_bits_uop_mem_size = 2'h0; // @[lsu.scala:201:7] wire [1:0] io_core_exe_0_req_bits_fflags_bits_uop_dst_rtype = 2'h0; // @[lsu.scala:201:7] wire [1:0] io_core_exe_0_req_bits_fflags_bits_uop_lrs1_rtype = 2'h0; // @[lsu.scala:201:7] wire [1:0] io_core_exe_0_req_bits_fflags_bits_uop_lrs2_rtype = 2'h0; // @[lsu.scala:201:7] wire [1:0] io_core_exe_0_req_bits_fflags_bits_uop_debug_fsrc = 2'h0; // @[lsu.scala:201:7] wire [1:0] io_core_exe_0_req_bits_fflags_bits_uop_debug_tsrc = 2'h0; // @[lsu.scala:201:7] wire [1:0] io_core_exe_0_iresp_bits_fflags_bits_uop_ctrl_op1_sel = 2'h0; // @[lsu.scala:201:7] wire [1:0] io_core_exe_0_iresp_bits_fflags_bits_uop_iw_state = 2'h0; // @[lsu.scala:201:7] wire [1:0] io_core_exe_0_iresp_bits_fflags_bits_uop_rxq_idx = 2'h0; // @[lsu.scala:201:7] wire [1:0] io_core_exe_0_iresp_bits_fflags_bits_uop_mem_size = 2'h0; // @[lsu.scala:201:7] wire [1:0] io_core_exe_0_iresp_bits_fflags_bits_uop_dst_rtype = 2'h0; // @[lsu.scala:201:7] wire [1:0] io_core_exe_0_iresp_bits_fflags_bits_uop_lrs1_rtype = 2'h0; // @[lsu.scala:201:7] wire [1:0] io_core_exe_0_iresp_bits_fflags_bits_uop_lrs2_rtype = 2'h0; // @[lsu.scala:201:7] wire [1:0] io_core_exe_0_iresp_bits_fflags_bits_uop_debug_fsrc = 2'h0; // @[lsu.scala:201:7] wire [1:0] io_core_exe_0_iresp_bits_fflags_bits_uop_debug_tsrc = 2'h0; // @[lsu.scala:201:7] wire [1:0] io_core_exe_0_fresp_bits_fflags_bits_uop_ctrl_op1_sel = 2'h0; // @[lsu.scala:201:7] wire [1:0] io_core_exe_0_fresp_bits_fflags_bits_uop_iw_state = 2'h0; // @[lsu.scala:201:7] wire [1:0] io_core_exe_0_fresp_bits_fflags_bits_uop_rxq_idx = 2'h0; // @[lsu.scala:201:7] wire [1:0] io_core_exe_0_fresp_bits_fflags_bits_uop_mem_size = 2'h0; // @[lsu.scala:201:7] wire [1:0] io_core_exe_0_fresp_bits_fflags_bits_uop_dst_rtype = 2'h0; // @[lsu.scala:201:7] wire [1:0] io_core_exe_0_fresp_bits_fflags_bits_uop_lrs1_rtype = 2'h0; // @[lsu.scala:201:7] wire [1:0] io_core_exe_0_fresp_bits_fflags_bits_uop_lrs2_rtype = 2'h0; // @[lsu.scala:201:7] wire [1:0] io_core_exe_0_fresp_bits_fflags_bits_uop_debug_fsrc = 2'h0; // @[lsu.scala:201:7] wire [1:0] io_core_exe_0_fresp_bits_fflags_bits_uop_debug_tsrc = 2'h0; // @[lsu.scala:201:7] wire [1:0] io_hellacache_resp_bits_dprv = 2'h0; // @[lsu.scala:201:7] wire [1:0] _exe_req_WIRE_0_bits_fflags_bits_uop_ctrl_op1_sel = 2'h0; // @[lsu.scala:383:33] wire [1:0] _exe_req_WIRE_0_bits_fflags_bits_uop_iw_state = 2'h0; // @[lsu.scala:383:33] wire [1:0] _exe_req_WIRE_0_bits_fflags_bits_uop_rxq_idx = 2'h0; // @[lsu.scala:383:33] wire [1:0] _exe_req_WIRE_0_bits_fflags_bits_uop_mem_size = 2'h0; // @[lsu.scala:383:33] wire [1:0] _exe_req_WIRE_0_bits_fflags_bits_uop_dst_rtype = 2'h0; // @[lsu.scala:383:33] wire [1:0] _exe_req_WIRE_0_bits_fflags_bits_uop_lrs1_rtype = 2'h0; // @[lsu.scala:383:33] wire [1:0] _exe_req_WIRE_0_bits_fflags_bits_uop_lrs2_rtype = 2'h0; // @[lsu.scala:383:33] wire [1:0] _exe_req_WIRE_0_bits_fflags_bits_uop_debug_fsrc = 2'h0; // @[lsu.scala:383:33] wire [1:0] _exe_req_WIRE_0_bits_fflags_bits_uop_debug_tsrc = 2'h0; // @[lsu.scala:383:33] wire [1:0] exe_req_0_bits_fflags_bits_uop_ctrl_op1_sel = 2'h0; // @[lsu.scala:383:25] wire [1:0] exe_req_0_bits_fflags_bits_uop_iw_state = 2'h0; // @[lsu.scala:383:25] wire [1:0] exe_req_0_bits_fflags_bits_uop_rxq_idx = 2'h0; // @[lsu.scala:383:25] wire [1:0] exe_req_0_bits_fflags_bits_uop_mem_size = 2'h0; // @[lsu.scala:383:25] wire [1:0] exe_req_0_bits_fflags_bits_uop_dst_rtype = 2'h0; // @[lsu.scala:383:25] wire [1:0] exe_req_0_bits_fflags_bits_uop_lrs1_rtype = 2'h0; // @[lsu.scala:383:25] wire [1:0] exe_req_0_bits_fflags_bits_uop_lrs2_rtype = 2'h0; // @[lsu.scala:383:25] wire [1:0] exe_req_0_bits_fflags_bits_uop_debug_fsrc = 2'h0; // @[lsu.scala:383:25] wire [1:0] exe_req_0_bits_fflags_bits_uop_debug_tsrc = 2'h0; // @[lsu.scala:383:25] wire [1:0] exe_tlb_uop_uop_ctrl_op1_sel = 2'h0; // @[consts.scala:269:19] wire [1:0] exe_tlb_uop_uop_iw_state = 2'h0; // @[consts.scala:269:19] wire [1:0] exe_tlb_uop_uop_rxq_idx = 2'h0; // @[consts.scala:269:19] wire [1:0] exe_tlb_uop_uop_mem_size = 2'h0; // @[consts.scala:269:19] wire [1:0] exe_tlb_uop_uop_lrs1_rtype = 2'h0; // @[consts.scala:269:19] wire [1:0] exe_tlb_uop_uop_lrs2_rtype = 2'h0; // @[consts.scala:269:19] wire [1:0] exe_tlb_uop_uop_debug_fsrc = 2'h0; // @[consts.scala:269:19] wire [1:0] exe_tlb_uop_uop_debug_tsrc = 2'h0; // @[consts.scala:269:19] wire [1:0] exe_tlb_uop_cs_op1_sel = 2'h0; // @[consts.scala:279:18] wire [1:0] exe_tlb_uop_uop_1_ctrl_op1_sel = 2'h0; // @[consts.scala:269:19] wire [1:0] exe_tlb_uop_uop_1_iw_state = 2'h0; // @[consts.scala:269:19] wire [1:0] exe_tlb_uop_uop_1_rxq_idx = 2'h0; // @[consts.scala:269:19] wire [1:0] exe_tlb_uop_uop_1_mem_size = 2'h0; // @[consts.scala:269:19] wire [1:0] exe_tlb_uop_uop_1_lrs1_rtype = 2'h0; // @[consts.scala:269:19] wire [1:0] exe_tlb_uop_uop_1_lrs2_rtype = 2'h0; // @[consts.scala:269:19] wire [1:0] exe_tlb_uop_uop_1_debug_fsrc = 2'h0; // @[consts.scala:269:19] wire [1:0] exe_tlb_uop_uop_1_debug_tsrc = 2'h0; // @[consts.scala:269:19] wire [1:0] exe_tlb_uop_cs_1_op1_sel = 2'h0; // @[consts.scala:279:18] wire [1:0] _exe_tlb_uop_T_3_ctrl_op1_sel = 2'h0; // @[lsu.scala:602:24] wire [1:0] _exe_tlb_uop_T_3_iw_state = 2'h0; // @[lsu.scala:602:24] wire [1:0] _exe_tlb_uop_T_3_rxq_idx = 2'h0; // @[lsu.scala:602:24] wire [1:0] _exe_tlb_uop_T_3_mem_size = 2'h0; // @[lsu.scala:602:24] wire [1:0] _exe_tlb_uop_T_3_lrs1_rtype = 2'h0; // @[lsu.scala:602:24] wire [1:0] _exe_tlb_uop_T_3_lrs2_rtype = 2'h0; // @[lsu.scala:602:24] wire [1:0] _exe_tlb_uop_T_3_debug_fsrc = 2'h0; // @[lsu.scala:602:24] wire [1:0] _exe_tlb_uop_T_3_debug_tsrc = 2'h0; // @[lsu.scala:602:24] wire [1:0] dmem_req_0_bits_uop_uop_ctrl_op1_sel = 2'h0; // @[consts.scala:269:19] wire [1:0] dmem_req_0_bits_uop_uop_iw_state = 2'h0; // @[consts.scala:269:19] wire [1:0] dmem_req_0_bits_uop_uop_rxq_idx = 2'h0; // @[consts.scala:269:19] wire [1:0] dmem_req_0_bits_uop_uop_mem_size = 2'h0; // @[consts.scala:269:19] wire [1:0] dmem_req_0_bits_uop_uop_lrs1_rtype = 2'h0; // @[consts.scala:269:19] wire [1:0] dmem_req_0_bits_uop_uop_lrs2_rtype = 2'h0; // @[consts.scala:269:19] wire [1:0] dmem_req_0_bits_uop_uop_debug_fsrc = 2'h0; // @[consts.scala:269:19] wire [1:0] dmem_req_0_bits_uop_uop_debug_tsrc = 2'h0; // @[consts.scala:269:19] wire [1:0] dmem_req_0_bits_uop_cs_op1_sel = 2'h0; // @[consts.scala:279:18] wire [1:0] _mem_ldq_e_WIRE_bits_uop_ctrl_op1_sel = 2'h0; // @[lsu.scala:918:90] wire [1:0] _mem_ldq_e_WIRE_bits_uop_iw_state = 2'h0; // @[lsu.scala:918:90] wire [1:0] _mem_ldq_e_WIRE_bits_uop_rxq_idx = 2'h0; // @[lsu.scala:918:90] wire [1:0] _mem_ldq_e_WIRE_bits_uop_mem_size = 2'h0; // @[lsu.scala:918:90] wire [1:0] _mem_ldq_e_WIRE_bits_uop_dst_rtype = 2'h0; // @[lsu.scala:918:90] wire [1:0] _mem_ldq_e_WIRE_bits_uop_lrs1_rtype = 2'h0; // @[lsu.scala:918:90] wire [1:0] _mem_ldq_e_WIRE_bits_uop_lrs2_rtype = 2'h0; // @[lsu.scala:918:90] wire [1:0] _mem_ldq_e_WIRE_bits_uop_debug_fsrc = 2'h0; // @[lsu.scala:918:90] wire [1:0] _mem_ldq_e_WIRE_bits_uop_debug_tsrc = 2'h0; // @[lsu.scala:918:90] wire [1:0] _mem_stq_e_WIRE_bits_uop_ctrl_op1_sel = 2'h0; // @[lsu.scala:922:89] wire [1:0] _mem_stq_e_WIRE_bits_uop_iw_state = 2'h0; // @[lsu.scala:922:89] wire [1:0] _mem_stq_e_WIRE_bits_uop_rxq_idx = 2'h0; // @[lsu.scala:922:89] wire [1:0] _mem_stq_e_WIRE_bits_uop_mem_size = 2'h0; // @[lsu.scala:922:89] wire [1:0] _mem_stq_e_WIRE_bits_uop_dst_rtype = 2'h0; // @[lsu.scala:922:89] wire [1:0] _mem_stq_e_WIRE_bits_uop_lrs1_rtype = 2'h0; // @[lsu.scala:922:89] wire [1:0] _mem_stq_e_WIRE_bits_uop_lrs2_rtype = 2'h0; // @[lsu.scala:922:89] wire [1:0] _mem_stq_e_WIRE_bits_uop_debug_fsrc = 2'h0; // @[lsu.scala:922:89] wire [1:0] _mem_stq_e_WIRE_bits_uop_debug_tsrc = 2'h0; // @[lsu.scala:922:89] wire [1:0] lcam_uop_uop_ctrl_op1_sel = 2'h0; // @[consts.scala:269:19] wire [1:0] lcam_uop_uop_iw_state = 2'h0; // @[consts.scala:269:19] wire [1:0] lcam_uop_uop_rxq_idx = 2'h0; // @[consts.scala:269:19] wire [1:0] lcam_uop_uop_mem_size = 2'h0; // @[consts.scala:269:19] wire [1:0] lcam_uop_uop_lrs1_rtype = 2'h0; // @[consts.scala:269:19] wire [1:0] lcam_uop_uop_lrs2_rtype = 2'h0; // @[consts.scala:269:19] wire [1:0] lcam_uop_uop_debug_fsrc = 2'h0; // @[consts.scala:269:19] wire [1:0] lcam_uop_uop_debug_tsrc = 2'h0; // @[consts.scala:269:19] wire [1:0] lcam_uop_cs_op1_sel = 2'h0; // @[consts.scala:279:18] wire [1:0] stq_0_bits_uop_uop_ctrl_op1_sel = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_0_bits_uop_uop_iw_state = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_0_bits_uop_uop_rxq_idx = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_0_bits_uop_uop_mem_size = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_0_bits_uop_uop_lrs1_rtype = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_0_bits_uop_uop_lrs2_rtype = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_0_bits_uop_uop_debug_fsrc = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_0_bits_uop_uop_debug_tsrc = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_0_bits_uop_cs_op1_sel = 2'h0; // @[consts.scala:279:18] wire [1:0] stq_1_bits_uop_uop_ctrl_op1_sel = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_1_bits_uop_uop_iw_state = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_1_bits_uop_uop_rxq_idx = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_1_bits_uop_uop_mem_size = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_1_bits_uop_uop_lrs1_rtype = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_1_bits_uop_uop_lrs2_rtype = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_1_bits_uop_uop_debug_fsrc = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_1_bits_uop_uop_debug_tsrc = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_1_bits_uop_cs_op1_sel = 2'h0; // @[consts.scala:279:18] wire [1:0] stq_2_bits_uop_uop_ctrl_op1_sel = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_2_bits_uop_uop_iw_state = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_2_bits_uop_uop_rxq_idx = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_2_bits_uop_uop_mem_size = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_2_bits_uop_uop_lrs1_rtype = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_2_bits_uop_uop_lrs2_rtype = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_2_bits_uop_uop_debug_fsrc = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_2_bits_uop_uop_debug_tsrc = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_2_bits_uop_cs_op1_sel = 2'h0; // @[consts.scala:279:18] wire [1:0] stq_3_bits_uop_uop_ctrl_op1_sel = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_3_bits_uop_uop_iw_state = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_3_bits_uop_uop_rxq_idx = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_3_bits_uop_uop_mem_size = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_3_bits_uop_uop_lrs1_rtype = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_3_bits_uop_uop_lrs2_rtype = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_3_bits_uop_uop_debug_fsrc = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_3_bits_uop_uop_debug_tsrc = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_3_bits_uop_cs_op1_sel = 2'h0; // @[consts.scala:279:18] wire [1:0] stq_4_bits_uop_uop_ctrl_op1_sel = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_4_bits_uop_uop_iw_state = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_4_bits_uop_uop_rxq_idx = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_4_bits_uop_uop_mem_size = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_4_bits_uop_uop_lrs1_rtype = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_4_bits_uop_uop_lrs2_rtype = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_4_bits_uop_uop_debug_fsrc = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_4_bits_uop_uop_debug_tsrc = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_4_bits_uop_cs_op1_sel = 2'h0; // @[consts.scala:279:18] wire [1:0] stq_5_bits_uop_uop_ctrl_op1_sel = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_5_bits_uop_uop_iw_state = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_5_bits_uop_uop_rxq_idx = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_5_bits_uop_uop_mem_size = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_5_bits_uop_uop_lrs1_rtype = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_5_bits_uop_uop_lrs2_rtype = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_5_bits_uop_uop_debug_fsrc = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_5_bits_uop_uop_debug_tsrc = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_5_bits_uop_cs_op1_sel = 2'h0; // @[consts.scala:279:18] wire [1:0] stq_6_bits_uop_uop_ctrl_op1_sel = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_6_bits_uop_uop_iw_state = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_6_bits_uop_uop_rxq_idx = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_6_bits_uop_uop_mem_size = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_6_bits_uop_uop_lrs1_rtype = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_6_bits_uop_uop_lrs2_rtype = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_6_bits_uop_uop_debug_fsrc = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_6_bits_uop_uop_debug_tsrc = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_6_bits_uop_cs_op1_sel = 2'h0; // @[consts.scala:279:18] wire [1:0] stq_7_bits_uop_uop_ctrl_op1_sel = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_7_bits_uop_uop_iw_state = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_7_bits_uop_uop_rxq_idx = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_7_bits_uop_uop_mem_size = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_7_bits_uop_uop_lrs1_rtype = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_7_bits_uop_uop_lrs2_rtype = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_7_bits_uop_uop_debug_fsrc = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_7_bits_uop_uop_debug_tsrc = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_7_bits_uop_cs_op1_sel = 2'h0; // @[consts.scala:279:18] wire [6:0] io_core_exe_0_req_bits_fflags_bits_uop_uopc = 7'h0; // @[lsu.scala:201:7] wire [6:0] io_core_exe_0_iresp_bits_fflags_bits_uop_uopc = 7'h0; // @[lsu.scala:201:7] wire [6:0] io_core_exe_0_fresp_bits_fflags_bits_uop_uopc = 7'h0; // @[lsu.scala:201:7] wire [6:0] io_hellacache_req_bits_tag = 7'h0; // @[lsu.scala:201:7] wire [6:0] io_hellacache_resp_bits_tag = 7'h0; // @[lsu.scala:201:7] wire [6:0] _exe_req_WIRE_0_bits_fflags_bits_uop_uopc = 7'h0; // @[lsu.scala:383:33] wire [6:0] exe_req_0_bits_fflags_bits_uop_uopc = 7'h0; // @[lsu.scala:383:25] wire [6:0] exe_tlb_uop_uop_uopc = 7'h0; // @[consts.scala:269:19] wire [6:0] exe_tlb_uop_uop_1_uopc = 7'h0; // @[consts.scala:269:19] wire [6:0] _exe_tlb_uop_T_3_uopc = 7'h0; // @[lsu.scala:602:24] wire [6:0] dmem_req_0_bits_uop_uop_uopc = 7'h0; // @[consts.scala:269:19] wire [6:0] _mem_ldq_e_WIRE_bits_uop_uopc = 7'h0; // @[lsu.scala:918:90] wire [6:0] _mem_stq_e_WIRE_bits_uop_uopc = 7'h0; // @[lsu.scala:922:89] wire [6:0] lcam_uop_uop_uopc = 7'h0; // @[consts.scala:269:19] wire [6:0] stq_0_bits_uop_uop_uopc = 7'h0; // @[consts.scala:269:19] wire [6:0] stq_1_bits_uop_uop_uopc = 7'h0; // @[consts.scala:269:19] wire [6:0] stq_2_bits_uop_uop_uopc = 7'h0; // @[consts.scala:269:19] wire [6:0] stq_3_bits_uop_uop_uopc = 7'h0; // @[consts.scala:269:19] wire [6:0] stq_4_bits_uop_uop_uopc = 7'h0; // @[consts.scala:269:19] wire [6:0] stq_5_bits_uop_uop_uopc = 7'h0; // @[consts.scala:269:19] wire [6:0] stq_6_bits_uop_uop_uopc = 7'h0; // @[consts.scala:269:19] wire [6:0] stq_7_bits_uop_uop_uopc = 7'h0; // @[consts.scala:269:19] wire [4:0] io_ptw_hstatus_zero1 = 5'h0; // @[lsu.scala:201:7] wire [4:0] io_core_exe_0_req_bits_fflags_bits_uop_ctrl_op_fcn = 5'h0; // @[lsu.scala:201:7] wire [4:0] io_core_exe_0_req_bits_fflags_bits_uop_rob_idx = 5'h0; // @[lsu.scala:201:7] wire [4:0] io_core_exe_0_req_bits_fflags_bits_uop_mem_cmd = 5'h0; // @[lsu.scala:201:7] wire [4:0] io_core_exe_0_req_bits_fflags_bits_flags = 5'h0; // @[lsu.scala:201:7] wire [4:0] io_core_exe_0_iresp_bits_fflags_bits_uop_ctrl_op_fcn = 5'h0; // @[lsu.scala:201:7] wire [4:0] io_core_exe_0_iresp_bits_fflags_bits_uop_rob_idx = 5'h0; // @[lsu.scala:201:7] wire [4:0] io_core_exe_0_iresp_bits_fflags_bits_uop_mem_cmd = 5'h0; // @[lsu.scala:201:7] wire [4:0] io_core_exe_0_iresp_bits_fflags_bits_flags = 5'h0; // @[lsu.scala:201:7] wire [4:0] io_core_exe_0_fresp_bits_fflags_bits_uop_ctrl_op_fcn = 5'h0; // @[lsu.scala:201:7] wire [4:0] io_core_exe_0_fresp_bits_fflags_bits_uop_rob_idx = 5'h0; // @[lsu.scala:201:7] wire [4:0] io_core_exe_0_fresp_bits_fflags_bits_uop_mem_cmd = 5'h0; // @[lsu.scala:201:7] wire [4:0] io_core_exe_0_fresp_bits_fflags_bits_flags = 5'h0; // @[lsu.scala:201:7] wire [4:0] io_hellacache_req_bits_cmd = 5'h0; // @[lsu.scala:201:7] wire [4:0] io_hellacache_resp_bits_cmd = 5'h0; // @[lsu.scala:201:7] wire [4:0] _exe_req_WIRE_0_bits_fflags_bits_uop_ctrl_op_fcn = 5'h0; // @[lsu.scala:383:33] wire [4:0] _exe_req_WIRE_0_bits_fflags_bits_uop_rob_idx = 5'h0; // @[lsu.scala:383:33] wire [4:0] _exe_req_WIRE_0_bits_fflags_bits_uop_mem_cmd = 5'h0; // @[lsu.scala:383:33] wire [4:0] _exe_req_WIRE_0_bits_fflags_bits_flags = 5'h0; // @[lsu.scala:383:33] wire [4:0] exe_req_0_bits_fflags_bits_uop_ctrl_op_fcn = 5'h0; // @[lsu.scala:383:25] wire [4:0] exe_req_0_bits_fflags_bits_uop_rob_idx = 5'h0; // @[lsu.scala:383:25] wire [4:0] exe_req_0_bits_fflags_bits_uop_mem_cmd = 5'h0; // @[lsu.scala:383:25] wire [4:0] exe_req_0_bits_fflags_bits_flags = 5'h0; // @[lsu.scala:383:25] wire [4:0] exe_tlb_uop_uop_ctrl_op_fcn = 5'h0; // @[consts.scala:269:19] wire [4:0] exe_tlb_uop_uop_rob_idx = 5'h0; // @[consts.scala:269:19] wire [4:0] exe_tlb_uop_uop_mem_cmd = 5'h0; // @[consts.scala:269:19] wire [4:0] exe_tlb_uop_cs_op_fcn = 5'h0; // @[consts.scala:279:18] wire [4:0] exe_tlb_uop_uop_1_ctrl_op_fcn = 5'h0; // @[consts.scala:269:19] wire [4:0] exe_tlb_uop_uop_1_rob_idx = 5'h0; // @[consts.scala:269:19] wire [4:0] exe_tlb_uop_uop_1_mem_cmd = 5'h0; // @[consts.scala:269:19] wire [4:0] exe_tlb_uop_cs_1_op_fcn = 5'h0; // @[consts.scala:279:18] wire [4:0] _exe_tlb_uop_T_3_ctrl_op_fcn = 5'h0; // @[lsu.scala:602:24] wire [4:0] _exe_tlb_uop_T_3_rob_idx = 5'h0; // @[lsu.scala:602:24] wire [4:0] _exe_tlb_uop_T_3_mem_cmd = 5'h0; // @[lsu.scala:602:24] wire [4:0] _exe_cmd_T_5 = 5'h0; // @[lsu.scala:638:23] wire [4:0] dmem_req_0_bits_uop_uop_ctrl_op_fcn = 5'h0; // @[consts.scala:269:19] wire [4:0] dmem_req_0_bits_uop_uop_rob_idx = 5'h0; // @[consts.scala:269:19] wire [4:0] dmem_req_0_bits_uop_uop_mem_cmd = 5'h0; // @[consts.scala:269:19] wire [4:0] dmem_req_0_bits_uop_cs_op_fcn = 5'h0; // @[consts.scala:279:18] wire [4:0] _mem_ldq_e_WIRE_bits_uop_ctrl_op_fcn = 5'h0; // @[lsu.scala:918:90] wire [4:0] _mem_ldq_e_WIRE_bits_uop_rob_idx = 5'h0; // @[lsu.scala:918:90] wire [4:0] _mem_ldq_e_WIRE_bits_uop_mem_cmd = 5'h0; // @[lsu.scala:918:90] wire [4:0] _mem_stq_e_WIRE_bits_uop_ctrl_op_fcn = 5'h0; // @[lsu.scala:922:89] wire [4:0] _mem_stq_e_WIRE_bits_uop_rob_idx = 5'h0; // @[lsu.scala:922:89] wire [4:0] _mem_stq_e_WIRE_bits_uop_mem_cmd = 5'h0; // @[lsu.scala:922:89] wire [4:0] lcam_uop_uop_ctrl_op_fcn = 5'h0; // @[consts.scala:269:19] wire [4:0] lcam_uop_uop_rob_idx = 5'h0; // @[consts.scala:269:19] wire [4:0] lcam_uop_uop_mem_cmd = 5'h0; // @[consts.scala:269:19] wire [4:0] lcam_uop_cs_op_fcn = 5'h0; // @[consts.scala:279:18] wire [4:0] stq_0_bits_uop_uop_ctrl_op_fcn = 5'h0; // @[consts.scala:269:19] wire [4:0] stq_0_bits_uop_uop_rob_idx = 5'h0; // @[consts.scala:269:19] wire [4:0] stq_0_bits_uop_uop_mem_cmd = 5'h0; // @[consts.scala:269:19] wire [4:0] stq_0_bits_uop_cs_op_fcn = 5'h0; // @[consts.scala:279:18] wire [4:0] stq_1_bits_uop_uop_ctrl_op_fcn = 5'h0; // @[consts.scala:269:19] wire [4:0] stq_1_bits_uop_uop_rob_idx = 5'h0; // @[consts.scala:269:19] wire [4:0] stq_1_bits_uop_uop_mem_cmd = 5'h0; // @[consts.scala:269:19] wire [4:0] stq_1_bits_uop_cs_op_fcn = 5'h0; // @[consts.scala:279:18] wire [4:0] stq_2_bits_uop_uop_ctrl_op_fcn = 5'h0; // @[consts.scala:269:19] wire [4:0] stq_2_bits_uop_uop_rob_idx = 5'h0; // @[consts.scala:269:19] wire [4:0] stq_2_bits_uop_uop_mem_cmd = 5'h0; // @[consts.scala:269:19] wire [4:0] stq_2_bits_uop_cs_op_fcn = 5'h0; // @[consts.scala:279:18] wire [4:0] stq_3_bits_uop_uop_ctrl_op_fcn = 5'h0; // @[consts.scala:269:19] wire [4:0] stq_3_bits_uop_uop_rob_idx = 5'h0; // @[consts.scala:269:19] wire [4:0] stq_3_bits_uop_uop_mem_cmd = 5'h0; // @[consts.scala:269:19] wire [4:0] stq_3_bits_uop_cs_op_fcn = 5'h0; // @[consts.scala:279:18] wire [4:0] stq_4_bits_uop_uop_ctrl_op_fcn = 5'h0; // @[consts.scala:269:19] wire [4:0] stq_4_bits_uop_uop_rob_idx = 5'h0; // @[consts.scala:269:19] wire [4:0] stq_4_bits_uop_uop_mem_cmd = 5'h0; // @[consts.scala:269:19] wire [4:0] stq_4_bits_uop_cs_op_fcn = 5'h0; // @[consts.scala:279:18] wire [4:0] stq_5_bits_uop_uop_ctrl_op_fcn = 5'h0; // @[consts.scala:269:19] wire [4:0] stq_5_bits_uop_uop_rob_idx = 5'h0; // @[consts.scala:269:19] wire [4:0] stq_5_bits_uop_uop_mem_cmd = 5'h0; // @[consts.scala:269:19] wire [4:0] stq_5_bits_uop_cs_op_fcn = 5'h0; // @[consts.scala:279:18] wire [4:0] stq_6_bits_uop_uop_ctrl_op_fcn = 5'h0; // @[consts.scala:269:19] wire [4:0] stq_6_bits_uop_uop_rob_idx = 5'h0; // @[consts.scala:269:19] wire [4:0] stq_6_bits_uop_uop_mem_cmd = 5'h0; // @[consts.scala:269:19] wire [4:0] stq_6_bits_uop_cs_op_fcn = 5'h0; // @[consts.scala:279:18] wire [4:0] stq_7_bits_uop_uop_ctrl_op_fcn = 5'h0; // @[consts.scala:269:19] wire [4:0] stq_7_bits_uop_uop_rob_idx = 5'h0; // @[consts.scala:269:19] wire [4:0] stq_7_bits_uop_uop_mem_cmd = 5'h0; // @[consts.scala:269:19] wire [4:0] stq_7_bits_uop_cs_op_fcn = 5'h0; // @[consts.scala:279:18] wire [1:0] io_hellacache_req_bits_size = 2'h3; // @[lsu.scala:201:7] wire [1:0] io_hellacache_resp_bits_size = 2'h3; // @[lsu.scala:201:7] wire [1:0] dmem_req_0_bits_data_size_1 = 2'h3; // @[AMOALU.scala:11:18] wire [1:0] dmem_req_0_bits_data_size_2 = 2'h3; // @[AMOALU.scala:11:18] wire io_core_exe_0_iresp_ready = 1'h1; // @[lsu.scala:201:7] wire io_core_exe_0_fresp_ready = 1'h1; // @[lsu.scala:201:7] wire io_hellacache_req_bits_phys = 1'h1; // @[lsu.scala:201:7] wire _ldq_retry_idx_temp_vec_T_7 = 1'h1; // @[util.scala:351:72] wire _stq_retry_idx_temp_vec_T_7 = 1'h1; // @[util.scala:351:72] wire _ldq_wakeup_idx_temp_vec_T_7 = 1'h1; // @[util.scala:351:72] wire _can_fire_sta_retry_T_7 = 1'h1; // @[lsu.scala:482:34] wire _will_fire_load_incoming_0_will_fire_T_2 = 1'h1; // @[lsu.scala:533:35] wire _will_fire_load_incoming_0_will_fire_T_6 = 1'h1; // @[lsu.scala:534:35] wire _will_fire_load_incoming_0_will_fire_T_10 = 1'h1; // @[lsu.scala:535:35] wire _will_fire_load_incoming_0_will_fire_T_14 = 1'h1; // @[lsu.scala:536:35] wire _will_fire_load_incoming_0_T_10 = 1'h1; // @[lsu.scala:540:34] wire _will_fire_load_incoming_0_T_11 = 1'h1; // @[lsu.scala:540:31] wire _will_fire_stad_incoming_0_will_fire_T_10 = 1'h1; // @[lsu.scala:535:35] wire _will_fire_stad_incoming_0_will_fire_T_14 = 1'h1; // @[lsu.scala:536:35] wire _will_fire_stad_incoming_0_T_7 = 1'h1; // @[lsu.scala:539:34] wire _will_fire_sta_incoming_0_will_fire_T_10 = 1'h1; // @[lsu.scala:535:35] wire _will_fire_sta_incoming_0_T_7 = 1'h1; // @[lsu.scala:539:34] wire _will_fire_std_incoming_0_will_fire_T_2 = 1'h1; // @[lsu.scala:533:35] wire _will_fire_std_incoming_0_will_fire_T_6 = 1'h1; // @[lsu.scala:534:35] wire _will_fire_std_incoming_0_will_fire_T_10 = 1'h1; // @[lsu.scala:535:35] wire _will_fire_std_incoming_0_T_1 = 1'h1; // @[lsu.scala:537:34] wire _will_fire_std_incoming_0_T_4 = 1'h1; // @[lsu.scala:538:34] wire _will_fire_std_incoming_0_T_7 = 1'h1; // @[lsu.scala:539:34] wire _will_fire_sfence_0_will_fire_T_6 = 1'h1; // @[lsu.scala:534:35] wire _will_fire_sfence_0_will_fire_T_10 = 1'h1; // @[lsu.scala:535:35] wire _will_fire_sfence_0_T_4 = 1'h1; // @[lsu.scala:538:34] wire _will_fire_sfence_0_T_7 = 1'h1; // @[lsu.scala:539:34] wire _will_fire_release_0_will_fire_T_2 = 1'h1; // @[lsu.scala:533:35] wire _will_fire_release_0_will_fire_T_10 = 1'h1; // @[lsu.scala:535:35] wire _will_fire_release_0_will_fire_T_14 = 1'h1; // @[lsu.scala:536:35] wire _will_fire_release_0_T_1 = 1'h1; // @[lsu.scala:537:34] wire _will_fire_release_0_T_7 = 1'h1; // @[lsu.scala:539:34] wire _will_fire_release_0_T_10 = 1'h1; // @[lsu.scala:540:34] wire _will_fire_hella_incoming_0_will_fire_T_6 = 1'h1; // @[lsu.scala:534:35] wire _will_fire_hella_incoming_0_will_fire_T_14 = 1'h1; // @[lsu.scala:536:35] wire _will_fire_hella_incoming_0_T_4 = 1'h1; // @[lsu.scala:538:34] wire _will_fire_hella_incoming_0_T_10 = 1'h1; // @[lsu.scala:540:34] wire _will_fire_hella_wakeup_0_will_fire_T_2 = 1'h1; // @[lsu.scala:533:35] wire _will_fire_hella_wakeup_0_will_fire_T_6 = 1'h1; // @[lsu.scala:534:35] wire _will_fire_hella_wakeup_0_will_fire_T_14 = 1'h1; // @[lsu.scala:536:35] wire _will_fire_hella_wakeup_0_T_1 = 1'h1; // @[lsu.scala:537:34] wire _will_fire_hella_wakeup_0_T_4 = 1'h1; // @[lsu.scala:538:34] wire _will_fire_hella_wakeup_0_T_10 = 1'h1; // @[lsu.scala:540:34] wire _will_fire_load_retry_0_will_fire_T_14 = 1'h1; // @[lsu.scala:536:35] wire _will_fire_load_retry_0_T_10 = 1'h1; // @[lsu.scala:540:34] wire _will_fire_sta_retry_0_will_fire_T_10 = 1'h1; // @[lsu.scala:535:35] wire _will_fire_sta_retry_0_T_7 = 1'h1; // @[lsu.scala:539:34] wire _will_fire_load_wakeup_0_will_fire_T_2 = 1'h1; // @[lsu.scala:533:35] wire _will_fire_load_wakeup_0_will_fire_T_14 = 1'h1; // @[lsu.scala:536:35] wire _will_fire_load_wakeup_0_T_1 = 1'h1; // @[lsu.scala:537:34] wire _will_fire_load_wakeup_0_T_10 = 1'h1; // @[lsu.scala:540:34] wire _will_fire_store_commit_0_will_fire_T_2 = 1'h1; // @[lsu.scala:533:35] wire _will_fire_store_commit_0_will_fire_T_6 = 1'h1; // @[lsu.scala:534:35] wire _will_fire_store_commit_0_will_fire_T_14 = 1'h1; // @[lsu.scala:536:35] wire _will_fire_store_commit_0_T_1 = 1'h1; // @[lsu.scala:537:34] wire _will_fire_store_commit_0_T_4 = 1'h1; // @[lsu.scala:538:34] wire _will_fire_store_commit_0_T_10 = 1'h1; // @[lsu.scala:540:34] wire _dmem_req_0_valid_T_8 = 1'h1; // @[lsu.scala:806:86] wire _temp_bits_T_14 = 1'h1; // @[lsu.scala:1230:28] wire [63:0] io_ptw_customCSRs_csrs_0_wdata = 64'h0; // @[lsu.scala:201:7] wire [63:0] io_ptw_customCSRs_csrs_0_value = 64'h0; // @[lsu.scala:201:7] wire [63:0] io_ptw_customCSRs_csrs_0_sdata = 64'h0; // @[lsu.scala:201:7] wire [63:0] io_ptw_customCSRs_csrs_1_wdata = 64'h0; // @[lsu.scala:201:7] wire [63:0] io_ptw_customCSRs_csrs_1_value = 64'h0; // @[lsu.scala:201:7] wire [63:0] io_ptw_customCSRs_csrs_1_sdata = 64'h0; // @[lsu.scala:201:7] wire [63:0] io_core_exe_0_req_bits_fflags_bits_uop_exc_cause = 64'h0; // @[lsu.scala:201:7] wire [63:0] io_core_exe_0_iresp_bits_fflags_bits_uop_exc_cause = 64'h0; // @[lsu.scala:201:7] wire [63:0] io_core_exe_0_fresp_bits_fflags_bits_uop_exc_cause = 64'h0; // @[lsu.scala:201:7] wire [63:0] io_hellacache_req_bits_data = 64'h0; // @[lsu.scala:201:7] wire [63:0] io_hellacache_s1_data_data = 64'h0; // @[lsu.scala:201:7] wire [63:0] io_hellacache_resp_bits_data_word_bypass = 64'h0; // @[lsu.scala:201:7] wire [63:0] io_hellacache_resp_bits_data_raw = 64'h0; // @[lsu.scala:201:7] wire [63:0] io_hellacache_resp_bits_store_data = 64'h0; // @[lsu.scala:201:7] wire [63:0] _exe_req_WIRE_0_bits_fflags_bits_uop_exc_cause = 64'h0; // @[lsu.scala:383:33] wire [63:0] exe_req_0_bits_fflags_bits_uop_exc_cause = 64'h0; // @[lsu.scala:383:25] wire [63:0] exe_tlb_uop_uop_exc_cause = 64'h0; // @[consts.scala:269:19] wire [63:0] exe_tlb_uop_uop_1_exc_cause = 64'h0; // @[consts.scala:269:19] wire [63:0] _exe_tlb_uop_T_3_exc_cause = 64'h0; // @[lsu.scala:602:24] wire [63:0] dmem_req_0_bits_uop_uop_exc_cause = 64'h0; // @[consts.scala:269:19] wire [63:0] _dmem_req_0_bits_data_T_19 = 64'h0; // @[AMOALU.scala:29:32] wire [63:0] _dmem_req_0_bits_data_T_23 = 64'h0; // @[AMOALU.scala:29:32] wire [63:0] _dmem_req_0_bits_data_T_26 = 64'h0; // @[AMOALU.scala:29:32] wire [63:0] _dmem_req_0_bits_data_T_27 = 64'h0; // @[AMOALU.scala:29:13] wire [63:0] _dmem_req_0_bits_data_T_28 = 64'h0; // @[AMOALU.scala:29:13] wire [63:0] _dmem_req_0_bits_data_T_29 = 64'h0; // @[AMOALU.scala:29:13] wire [63:0] _mem_ldq_e_WIRE_bits_uop_exc_cause = 64'h0; // @[lsu.scala:918:90] wire [63:0] _mem_ldq_e_WIRE_bits_debug_wb_data = 64'h0; // @[lsu.scala:918:90] wire [63:0] _mem_stq_e_WIRE_bits_uop_exc_cause = 64'h0; // @[lsu.scala:922:89] wire [63:0] _mem_stq_e_WIRE_bits_data_bits = 64'h0; // @[lsu.scala:922:89] wire [63:0] _mem_stq_e_WIRE_bits_debug_wb_data = 64'h0; // @[lsu.scala:922:89] wire [63:0] lcam_uop_uop_exc_cause = 64'h0; // @[consts.scala:269:19] wire [63:0] stq_0_bits_uop_uop_exc_cause = 64'h0; // @[consts.scala:269:19] wire [63:0] stq_1_bits_uop_uop_exc_cause = 64'h0; // @[consts.scala:269:19] wire [63:0] stq_2_bits_uop_uop_exc_cause = 64'h0; // @[consts.scala:269:19] wire [63:0] stq_3_bits_uop_uop_exc_cause = 64'h0; // @[consts.scala:269:19] wire [63:0] stq_4_bits_uop_uop_exc_cause = 64'h0; // @[consts.scala:269:19] wire [63:0] stq_5_bits_uop_uop_exc_cause = 64'h0; // @[consts.scala:269:19] wire [63:0] stq_6_bits_uop_uop_exc_cause = 64'h0; // @[consts.scala:269:19] wire [63:0] stq_7_bits_uop_uop_exc_cause = 64'h0; // @[consts.scala:269:19] wire [1:0] io_hellacache_req_bits_dprv = 2'h1; // @[lsu.scala:201:7] wire [3:0] io_ptw_hgatp_mode = 4'h0; // @[lsu.scala:201:7] wire [3:0] io_ptw_vsatp_mode = 4'h0; // @[lsu.scala:201:7] wire [3:0] io_core_exe_0_req_bits_fflags_bits_uop_ctrl_br_type = 4'h0; // @[lsu.scala:201:7] wire [3:0] io_core_exe_0_req_bits_fflags_bits_uop_ftq_idx = 4'h0; // @[lsu.scala:201:7] wire [3:0] io_core_exe_0_req_bits_fflags_bits_uop_ppred = 4'h0; // @[lsu.scala:201:7] wire [3:0] io_core_exe_0_iresp_bits_fflags_bits_uop_ctrl_br_type = 4'h0; // @[lsu.scala:201:7] wire [3:0] io_core_exe_0_iresp_bits_fflags_bits_uop_ftq_idx = 4'h0; // @[lsu.scala:201:7] wire [3:0] io_core_exe_0_iresp_bits_fflags_bits_uop_ppred = 4'h0; // @[lsu.scala:201:7] wire [3:0] io_core_exe_0_fresp_bits_uop_ppred_0 = 4'h0; // @[lsu.scala:201:7] wire [3:0] io_core_exe_0_fresp_bits_fflags_bits_uop_ctrl_br_type = 4'h0; // @[lsu.scala:201:7] wire [3:0] io_core_exe_0_fresp_bits_fflags_bits_uop_ftq_idx = 4'h0; // @[lsu.scala:201:7] wire [3:0] io_core_exe_0_fresp_bits_fflags_bits_uop_ppred = 4'h0; // @[lsu.scala:201:7] wire [3:0] io_core_dis_uops_0_bits_ppred = 4'h0; // @[lsu.scala:201:7] wire [3:0] _exe_req_WIRE_0_bits_fflags_bits_uop_ctrl_br_type = 4'h0; // @[lsu.scala:383:33] wire [3:0] _exe_req_WIRE_0_bits_fflags_bits_uop_ftq_idx = 4'h0; // @[lsu.scala:383:33] wire [3:0] _exe_req_WIRE_0_bits_fflags_bits_uop_ppred = 4'h0; // @[lsu.scala:383:33] wire [3:0] exe_req_0_bits_fflags_bits_uop_ctrl_br_type = 4'h0; // @[lsu.scala:383:25] wire [3:0] exe_req_0_bits_fflags_bits_uop_ftq_idx = 4'h0; // @[lsu.scala:383:25] wire [3:0] exe_req_0_bits_fflags_bits_uop_ppred = 4'h0; // @[lsu.scala:383:25] wire [3:0] ldq_incoming_e_0_bits_uop_ppred = 4'h0; // @[lsu.scala:263:49] wire [3:0] exe_tlb_uop_uop_ctrl_br_type = 4'h0; // @[consts.scala:269:19] wire [3:0] exe_tlb_uop_uop_ftq_idx = 4'h0; // @[consts.scala:269:19] wire [3:0] exe_tlb_uop_uop_ppred = 4'h0; // @[consts.scala:269:19] wire [3:0] exe_tlb_uop_cs_br_type = 4'h0; // @[consts.scala:279:18] wire [3:0] exe_tlb_uop_uop_1_ctrl_br_type = 4'h0; // @[consts.scala:269:19] wire [3:0] exe_tlb_uop_uop_1_ftq_idx = 4'h0; // @[consts.scala:269:19] wire [3:0] exe_tlb_uop_uop_1_ppred = 4'h0; // @[consts.scala:269:19] wire [3:0] exe_tlb_uop_cs_1_br_type = 4'h0; // @[consts.scala:279:18] wire [3:0] _exe_tlb_uop_T_3_ctrl_br_type = 4'h0; // @[lsu.scala:602:24] wire [3:0] _exe_tlb_uop_T_3_ftq_idx = 4'h0; // @[lsu.scala:602:24] wire [3:0] _exe_tlb_uop_T_3_ppred = 4'h0; // @[lsu.scala:602:24] wire [3:0] dmem_req_0_bits_uop_uop_ctrl_br_type = 4'h0; // @[consts.scala:269:19] wire [3:0] dmem_req_0_bits_uop_uop_ftq_idx = 4'h0; // @[consts.scala:269:19] wire [3:0] dmem_req_0_bits_uop_uop_ppred = 4'h0; // @[consts.scala:269:19] wire [3:0] dmem_req_0_bits_uop_cs_br_type = 4'h0; // @[consts.scala:279:18] wire [3:0] mem_ldq_wakeup_e_out_bits_uop_ppred = 4'h0; // @[util.scala:106:23] wire [3:0] mem_ldq_retry_e_out_bits_uop_ppred = 4'h0; // @[util.scala:106:23] wire [3:0] _mem_ldq_e_WIRE_bits_uop_ctrl_br_type = 4'h0; // @[lsu.scala:918:90] wire [3:0] _mem_ldq_e_WIRE_bits_uop_ftq_idx = 4'h0; // @[lsu.scala:918:90] wire [3:0] _mem_ldq_e_WIRE_bits_uop_ppred = 4'h0; // @[lsu.scala:918:90] wire [3:0] _mem_stq_e_WIRE_bits_uop_ctrl_br_type = 4'h0; // @[lsu.scala:922:89] wire [3:0] _mem_stq_e_WIRE_bits_uop_ftq_idx = 4'h0; // @[lsu.scala:922:89] wire [3:0] _mem_stq_e_WIRE_bits_uop_ppred = 4'h0; // @[lsu.scala:922:89] wire [3:0] lcam_uop_uop_ctrl_br_type = 4'h0; // @[consts.scala:269:19] wire [3:0] lcam_uop_uop_ftq_idx = 4'h0; // @[consts.scala:269:19] wire [3:0] lcam_uop_uop_ppred = 4'h0; // @[consts.scala:269:19] wire [3:0] lcam_uop_cs_br_type = 4'h0; // @[consts.scala:279:18] wire [3:0] stq_0_bits_uop_uop_ctrl_br_type = 4'h0; // @[consts.scala:269:19] wire [3:0] stq_0_bits_uop_uop_ftq_idx = 4'h0; // @[consts.scala:269:19] wire [3:0] stq_0_bits_uop_uop_ppred = 4'h0; // @[consts.scala:269:19] wire [3:0] stq_0_bits_uop_cs_br_type = 4'h0; // @[consts.scala:279:18] wire [3:0] stq_1_bits_uop_uop_ctrl_br_type = 4'h0; // @[consts.scala:269:19] wire [3:0] stq_1_bits_uop_uop_ftq_idx = 4'h0; // @[consts.scala:269:19] wire [3:0] stq_1_bits_uop_uop_ppred = 4'h0; // @[consts.scala:269:19] wire [3:0] stq_1_bits_uop_cs_br_type = 4'h0; // @[consts.scala:279:18] wire [3:0] stq_2_bits_uop_uop_ctrl_br_type = 4'h0; // @[consts.scala:269:19] wire [3:0] stq_2_bits_uop_uop_ftq_idx = 4'h0; // @[consts.scala:269:19] wire [3:0] stq_2_bits_uop_uop_ppred = 4'h0; // @[consts.scala:269:19] wire [3:0] stq_2_bits_uop_cs_br_type = 4'h0; // @[consts.scala:279:18] wire [3:0] stq_3_bits_uop_uop_ctrl_br_type = 4'h0; // @[consts.scala:269:19] wire [3:0] stq_3_bits_uop_uop_ftq_idx = 4'h0; // @[consts.scala:269:19] wire [3:0] stq_3_bits_uop_uop_ppred = 4'h0; // @[consts.scala:269:19] wire [3:0] stq_3_bits_uop_cs_br_type = 4'h0; // @[consts.scala:279:18] wire [3:0] stq_4_bits_uop_uop_ctrl_br_type = 4'h0; // @[consts.scala:269:19] wire [3:0] stq_4_bits_uop_uop_ftq_idx = 4'h0; // @[consts.scala:269:19] wire [3:0] stq_4_bits_uop_uop_ppred = 4'h0; // @[consts.scala:269:19] wire [3:0] stq_4_bits_uop_cs_br_type = 4'h0; // @[consts.scala:279:18] wire [3:0] stq_5_bits_uop_uop_ctrl_br_type = 4'h0; // @[consts.scala:269:19] wire [3:0] stq_5_bits_uop_uop_ftq_idx = 4'h0; // @[consts.scala:269:19] wire [3:0] stq_5_bits_uop_uop_ppred = 4'h0; // @[consts.scala:269:19] wire [3:0] stq_5_bits_uop_cs_br_type = 4'h0; // @[consts.scala:279:18] wire [3:0] stq_6_bits_uop_uop_ctrl_br_type = 4'h0; // @[consts.scala:269:19] wire [3:0] stq_6_bits_uop_uop_ftq_idx = 4'h0; // @[consts.scala:269:19] wire [3:0] stq_6_bits_uop_uop_ppred = 4'h0; // @[consts.scala:269:19] wire [3:0] stq_6_bits_uop_cs_br_type = 4'h0; // @[consts.scala:279:18] wire [3:0] stq_7_bits_uop_uop_ctrl_br_type = 4'h0; // @[consts.scala:269:19] wire [3:0] stq_7_bits_uop_uop_ftq_idx = 4'h0; // @[consts.scala:269:19] wire [3:0] stq_7_bits_uop_uop_ppred = 4'h0; // @[consts.scala:269:19] wire [3:0] stq_7_bits_uop_cs_br_type = 4'h0; // @[consts.scala:279:18] wire [43:0] io_ptw_hgatp_ppn = 44'h0; // @[lsu.scala:201:7] wire [43:0] io_ptw_vsatp_ppn = 44'h0; // @[lsu.scala:201:7] wire [1:0] io_ptw_status_sxl = 2'h2; // @[lsu.scala:201:7] wire [1:0] io_ptw_status_uxl = 2'h2; // @[lsu.scala:201:7] wire [1:0] exe_tlb_uop_uop_dst_rtype = 2'h2; // @[consts.scala:269:19] wire [1:0] exe_tlb_uop_uop_1_dst_rtype = 2'h2; // @[consts.scala:269:19] wire [1:0] _exe_tlb_uop_T_3_dst_rtype = 2'h2; // @[lsu.scala:602:24] wire [1:0] dmem_req_0_bits_uop_uop_dst_rtype = 2'h2; // @[consts.scala:269:19] wire [1:0] lcam_uop_uop_dst_rtype = 2'h2; // @[consts.scala:269:19] wire [1:0] stq_0_bits_uop_uop_dst_rtype = 2'h2; // @[consts.scala:269:19] wire [1:0] stq_1_bits_uop_uop_dst_rtype = 2'h2; // @[consts.scala:269:19] wire [1:0] stq_2_bits_uop_uop_dst_rtype = 2'h2; // @[consts.scala:269:19] wire [1:0] stq_3_bits_uop_uop_dst_rtype = 2'h2; // @[consts.scala:269:19] wire [1:0] stq_4_bits_uop_uop_dst_rtype = 2'h2; // @[consts.scala:269:19] wire [1:0] stq_5_bits_uop_uop_dst_rtype = 2'h2; // @[consts.scala:269:19] wire [1:0] stq_6_bits_uop_uop_dst_rtype = 2'h2; // @[consts.scala:269:19] wire [1:0] stq_7_bits_uop_uop_dst_rtype = 2'h2; // @[consts.scala:269:19] wire [29:0] io_ptw_hstatus_zero6 = 30'h0; // @[lsu.scala:201:7] wire [8:0] io_ptw_hstatus_zero5 = 9'h0; // @[lsu.scala:201:7] wire [5:0] io_ptw_hstatus_vgein = 6'h0; // @[lsu.scala:201:7] wire [5:0] io_core_exe_0_req_bits_fflags_bits_uop_pc_lob = 6'h0; // @[lsu.scala:201:7] wire [5:0] io_core_exe_0_req_bits_fflags_bits_uop_pdst = 6'h0; // @[lsu.scala:201:7] wire [5:0] io_core_exe_0_req_bits_fflags_bits_uop_prs1 = 6'h0; // @[lsu.scala:201:7] wire [5:0] io_core_exe_0_req_bits_fflags_bits_uop_prs2 = 6'h0; // @[lsu.scala:201:7] wire [5:0] io_core_exe_0_req_bits_fflags_bits_uop_prs3 = 6'h0; // @[lsu.scala:201:7] wire [5:0] io_core_exe_0_req_bits_fflags_bits_uop_stale_pdst = 6'h0; // @[lsu.scala:201:7] wire [5:0] io_core_exe_0_req_bits_fflags_bits_uop_ldst = 6'h0; // @[lsu.scala:201:7] wire [5:0] io_core_exe_0_req_bits_fflags_bits_uop_lrs1 = 6'h0; // @[lsu.scala:201:7] wire [5:0] io_core_exe_0_req_bits_fflags_bits_uop_lrs2 = 6'h0; // @[lsu.scala:201:7] wire [5:0] io_core_exe_0_req_bits_fflags_bits_uop_lrs3 = 6'h0; // @[lsu.scala:201:7] wire [5:0] io_core_exe_0_iresp_bits_fflags_bits_uop_pc_lob = 6'h0; // @[lsu.scala:201:7] wire [5:0] io_core_exe_0_iresp_bits_fflags_bits_uop_pdst = 6'h0; // @[lsu.scala:201:7] wire [5:0] io_core_exe_0_iresp_bits_fflags_bits_uop_prs1 = 6'h0; // @[lsu.scala:201:7] wire [5:0] io_core_exe_0_iresp_bits_fflags_bits_uop_prs2 = 6'h0; // @[lsu.scala:201:7] wire [5:0] io_core_exe_0_iresp_bits_fflags_bits_uop_prs3 = 6'h0; // @[lsu.scala:201:7] wire [5:0] io_core_exe_0_iresp_bits_fflags_bits_uop_stale_pdst = 6'h0; // @[lsu.scala:201:7] wire [5:0] io_core_exe_0_iresp_bits_fflags_bits_uop_ldst = 6'h0; // @[lsu.scala:201:7] wire [5:0] io_core_exe_0_iresp_bits_fflags_bits_uop_lrs1 = 6'h0; // @[lsu.scala:201:7] wire [5:0] io_core_exe_0_iresp_bits_fflags_bits_uop_lrs2 = 6'h0; // @[lsu.scala:201:7] wire [5:0] io_core_exe_0_iresp_bits_fflags_bits_uop_lrs3 = 6'h0; // @[lsu.scala:201:7] wire [5:0] io_core_exe_0_fresp_bits_fflags_bits_uop_pc_lob = 6'h0; // @[lsu.scala:201:7] wire [5:0] io_core_exe_0_fresp_bits_fflags_bits_uop_pdst = 6'h0; // @[lsu.scala:201:7] wire [5:0] io_core_exe_0_fresp_bits_fflags_bits_uop_prs1 = 6'h0; // @[lsu.scala:201:7] wire [5:0] io_core_exe_0_fresp_bits_fflags_bits_uop_prs2 = 6'h0; // @[lsu.scala:201:7] wire [5:0] io_core_exe_0_fresp_bits_fflags_bits_uop_prs3 = 6'h0; // @[lsu.scala:201:7] wire [5:0] io_core_exe_0_fresp_bits_fflags_bits_uop_stale_pdst = 6'h0; // @[lsu.scala:201:7] wire [5:0] io_core_exe_0_fresp_bits_fflags_bits_uop_ldst = 6'h0; // @[lsu.scala:201:7] wire [5:0] io_core_exe_0_fresp_bits_fflags_bits_uop_lrs1 = 6'h0; // @[lsu.scala:201:7] wire [5:0] io_core_exe_0_fresp_bits_fflags_bits_uop_lrs2 = 6'h0; // @[lsu.scala:201:7] wire [5:0] io_core_exe_0_fresp_bits_fflags_bits_uop_lrs3 = 6'h0; // @[lsu.scala:201:7] wire [5:0] _exe_req_WIRE_0_bits_fflags_bits_uop_pc_lob = 6'h0; // @[lsu.scala:383:33] wire [5:0] _exe_req_WIRE_0_bits_fflags_bits_uop_pdst = 6'h0; // @[lsu.scala:383:33] wire [5:0] _exe_req_WIRE_0_bits_fflags_bits_uop_prs1 = 6'h0; // @[lsu.scala:383:33] wire [5:0] _exe_req_WIRE_0_bits_fflags_bits_uop_prs2 = 6'h0; // @[lsu.scala:383:33] wire [5:0] _exe_req_WIRE_0_bits_fflags_bits_uop_prs3 = 6'h0; // @[lsu.scala:383:33] wire [5:0] _exe_req_WIRE_0_bits_fflags_bits_uop_stale_pdst = 6'h0; // @[lsu.scala:383:33] wire [5:0] _exe_req_WIRE_0_bits_fflags_bits_uop_ldst = 6'h0; // @[lsu.scala:383:33] wire [5:0] _exe_req_WIRE_0_bits_fflags_bits_uop_lrs1 = 6'h0; // @[lsu.scala:383:33] wire [5:0] _exe_req_WIRE_0_bits_fflags_bits_uop_lrs2 = 6'h0; // @[lsu.scala:383:33] wire [5:0] _exe_req_WIRE_0_bits_fflags_bits_uop_lrs3 = 6'h0; // @[lsu.scala:383:33] wire [5:0] exe_req_0_bits_fflags_bits_uop_pc_lob = 6'h0; // @[lsu.scala:383:25] wire [5:0] exe_req_0_bits_fflags_bits_uop_pdst = 6'h0; // @[lsu.scala:383:25] wire [5:0] exe_req_0_bits_fflags_bits_uop_prs1 = 6'h0; // @[lsu.scala:383:25] wire [5:0] exe_req_0_bits_fflags_bits_uop_prs2 = 6'h0; // @[lsu.scala:383:25] wire [5:0] exe_req_0_bits_fflags_bits_uop_prs3 = 6'h0; // @[lsu.scala:383:25] wire [5:0] exe_req_0_bits_fflags_bits_uop_stale_pdst = 6'h0; // @[lsu.scala:383:25] wire [5:0] exe_req_0_bits_fflags_bits_uop_ldst = 6'h0; // @[lsu.scala:383:25] wire [5:0] exe_req_0_bits_fflags_bits_uop_lrs1 = 6'h0; // @[lsu.scala:383:25] wire [5:0] exe_req_0_bits_fflags_bits_uop_lrs2 = 6'h0; // @[lsu.scala:383:25] wire [5:0] exe_req_0_bits_fflags_bits_uop_lrs3 = 6'h0; // @[lsu.scala:383:25] wire [5:0] exe_tlb_uop_uop_pc_lob = 6'h0; // @[consts.scala:269:19] wire [5:0] exe_tlb_uop_uop_pdst = 6'h0; // @[consts.scala:269:19] wire [5:0] exe_tlb_uop_uop_prs1 = 6'h0; // @[consts.scala:269:19] wire [5:0] exe_tlb_uop_uop_prs2 = 6'h0; // @[consts.scala:269:19] wire [5:0] exe_tlb_uop_uop_prs3 = 6'h0; // @[consts.scala:269:19] wire [5:0] exe_tlb_uop_uop_stale_pdst = 6'h0; // @[consts.scala:269:19] wire [5:0] exe_tlb_uop_uop_ldst = 6'h0; // @[consts.scala:269:19] wire [5:0] exe_tlb_uop_uop_lrs1 = 6'h0; // @[consts.scala:269:19] wire [5:0] exe_tlb_uop_uop_lrs2 = 6'h0; // @[consts.scala:269:19] wire [5:0] exe_tlb_uop_uop_lrs3 = 6'h0; // @[consts.scala:269:19] wire [5:0] exe_tlb_uop_uop_1_pc_lob = 6'h0; // @[consts.scala:269:19] wire [5:0] exe_tlb_uop_uop_1_pdst = 6'h0; // @[consts.scala:269:19] wire [5:0] exe_tlb_uop_uop_1_prs1 = 6'h0; // @[consts.scala:269:19] wire [5:0] exe_tlb_uop_uop_1_prs2 = 6'h0; // @[consts.scala:269:19] wire [5:0] exe_tlb_uop_uop_1_prs3 = 6'h0; // @[consts.scala:269:19] wire [5:0] exe_tlb_uop_uop_1_stale_pdst = 6'h0; // @[consts.scala:269:19] wire [5:0] exe_tlb_uop_uop_1_ldst = 6'h0; // @[consts.scala:269:19] wire [5:0] exe_tlb_uop_uop_1_lrs1 = 6'h0; // @[consts.scala:269:19] wire [5:0] exe_tlb_uop_uop_1_lrs2 = 6'h0; // @[consts.scala:269:19] wire [5:0] exe_tlb_uop_uop_1_lrs3 = 6'h0; // @[consts.scala:269:19] wire [5:0] _exe_tlb_uop_T_3_pc_lob = 6'h0; // @[lsu.scala:602:24] wire [5:0] _exe_tlb_uop_T_3_pdst = 6'h0; // @[lsu.scala:602:24] wire [5:0] _exe_tlb_uop_T_3_prs1 = 6'h0; // @[lsu.scala:602:24] wire [5:0] _exe_tlb_uop_T_3_prs2 = 6'h0; // @[lsu.scala:602:24] wire [5:0] _exe_tlb_uop_T_3_prs3 = 6'h0; // @[lsu.scala:602:24] wire [5:0] _exe_tlb_uop_T_3_stale_pdst = 6'h0; // @[lsu.scala:602:24] wire [5:0] _exe_tlb_uop_T_3_ldst = 6'h0; // @[lsu.scala:602:24] wire [5:0] _exe_tlb_uop_T_3_lrs1 = 6'h0; // @[lsu.scala:602:24] wire [5:0] _exe_tlb_uop_T_3_lrs2 = 6'h0; // @[lsu.scala:602:24] wire [5:0] _exe_tlb_uop_T_3_lrs3 = 6'h0; // @[lsu.scala:602:24] wire [5:0] dmem_req_0_bits_uop_uop_pc_lob = 6'h0; // @[consts.scala:269:19] wire [5:0] dmem_req_0_bits_uop_uop_pdst = 6'h0; // @[consts.scala:269:19] wire [5:0] dmem_req_0_bits_uop_uop_prs1 = 6'h0; // @[consts.scala:269:19] wire [5:0] dmem_req_0_bits_uop_uop_prs2 = 6'h0; // @[consts.scala:269:19] wire [5:0] dmem_req_0_bits_uop_uop_prs3 = 6'h0; // @[consts.scala:269:19] wire [5:0] dmem_req_0_bits_uop_uop_stale_pdst = 6'h0; // @[consts.scala:269:19] wire [5:0] dmem_req_0_bits_uop_uop_ldst = 6'h0; // @[consts.scala:269:19] wire [5:0] dmem_req_0_bits_uop_uop_lrs1 = 6'h0; // @[consts.scala:269:19] wire [5:0] dmem_req_0_bits_uop_uop_lrs2 = 6'h0; // @[consts.scala:269:19] wire [5:0] dmem_req_0_bits_uop_uop_lrs3 = 6'h0; // @[consts.scala:269:19] wire [5:0] _mem_ldq_e_WIRE_bits_uop_pc_lob = 6'h0; // @[lsu.scala:918:90] wire [5:0] _mem_ldq_e_WIRE_bits_uop_pdst = 6'h0; // @[lsu.scala:918:90] wire [5:0] _mem_ldq_e_WIRE_bits_uop_prs1 = 6'h0; // @[lsu.scala:918:90] wire [5:0] _mem_ldq_e_WIRE_bits_uop_prs2 = 6'h0; // @[lsu.scala:918:90] wire [5:0] _mem_ldq_e_WIRE_bits_uop_prs3 = 6'h0; // @[lsu.scala:918:90] wire [5:0] _mem_ldq_e_WIRE_bits_uop_stale_pdst = 6'h0; // @[lsu.scala:918:90] wire [5:0] _mem_ldq_e_WIRE_bits_uop_ldst = 6'h0; // @[lsu.scala:918:90] wire [5:0] _mem_ldq_e_WIRE_bits_uop_lrs1 = 6'h0; // @[lsu.scala:918:90] wire [5:0] _mem_ldq_e_WIRE_bits_uop_lrs2 = 6'h0; // @[lsu.scala:918:90] wire [5:0] _mem_ldq_e_WIRE_bits_uop_lrs3 = 6'h0; // @[lsu.scala:918:90] wire [5:0] _mem_stq_e_WIRE_bits_uop_pc_lob = 6'h0; // @[lsu.scala:922:89] wire [5:0] _mem_stq_e_WIRE_bits_uop_pdst = 6'h0; // @[lsu.scala:922:89] wire [5:0] _mem_stq_e_WIRE_bits_uop_prs1 = 6'h0; // @[lsu.scala:922:89] wire [5:0] _mem_stq_e_WIRE_bits_uop_prs2 = 6'h0; // @[lsu.scala:922:89] wire [5:0] _mem_stq_e_WIRE_bits_uop_prs3 = 6'h0; // @[lsu.scala:922:89] wire [5:0] _mem_stq_e_WIRE_bits_uop_stale_pdst = 6'h0; // @[lsu.scala:922:89] wire [5:0] _mem_stq_e_WIRE_bits_uop_ldst = 6'h0; // @[lsu.scala:922:89] wire [5:0] _mem_stq_e_WIRE_bits_uop_lrs1 = 6'h0; // @[lsu.scala:922:89] wire [5:0] _mem_stq_e_WIRE_bits_uop_lrs2 = 6'h0; // @[lsu.scala:922:89] wire [5:0] _mem_stq_e_WIRE_bits_uop_lrs3 = 6'h0; // @[lsu.scala:922:89] wire [5:0] lcam_uop_uop_pc_lob = 6'h0; // @[consts.scala:269:19] wire [5:0] lcam_uop_uop_pdst = 6'h0; // @[consts.scala:269:19] wire [5:0] lcam_uop_uop_prs1 = 6'h0; // @[consts.scala:269:19] wire [5:0] lcam_uop_uop_prs2 = 6'h0; // @[consts.scala:269:19] wire [5:0] lcam_uop_uop_prs3 = 6'h0; // @[consts.scala:269:19] wire [5:0] lcam_uop_uop_stale_pdst = 6'h0; // @[consts.scala:269:19] wire [5:0] lcam_uop_uop_ldst = 6'h0; // @[consts.scala:269:19] wire [5:0] lcam_uop_uop_lrs1 = 6'h0; // @[consts.scala:269:19] wire [5:0] lcam_uop_uop_lrs2 = 6'h0; // @[consts.scala:269:19] wire [5:0] lcam_uop_uop_lrs3 = 6'h0; // @[consts.scala:269:19] wire [5:0] stq_0_bits_uop_uop_pc_lob = 6'h0; // @[consts.scala:269:19] wire [5:0] stq_0_bits_uop_uop_pdst = 6'h0; // @[consts.scala:269:19] wire [5:0] stq_0_bits_uop_uop_prs1 = 6'h0; // @[consts.scala:269:19] wire [5:0] stq_0_bits_uop_uop_prs2 = 6'h0; // @[consts.scala:269:19] wire [5:0] stq_0_bits_uop_uop_prs3 = 6'h0; // @[consts.scala:269:19] wire [5:0] stq_0_bits_uop_uop_stale_pdst = 6'h0; // @[consts.scala:269:19] wire [5:0] stq_0_bits_uop_uop_ldst = 6'h0; // @[consts.scala:269:19] wire [5:0] stq_0_bits_uop_uop_lrs1 = 6'h0; // @[consts.scala:269:19] wire [5:0] stq_0_bits_uop_uop_lrs2 = 6'h0; // @[consts.scala:269:19] wire [5:0] stq_0_bits_uop_uop_lrs3 = 6'h0; // @[consts.scala:269:19] wire [5:0] stq_1_bits_uop_uop_pc_lob = 6'h0; // @[consts.scala:269:19] wire [5:0] stq_1_bits_uop_uop_pdst = 6'h0; // @[consts.scala:269:19] wire [5:0] stq_1_bits_uop_uop_prs1 = 6'h0; // @[consts.scala:269:19] wire [5:0] stq_1_bits_uop_uop_prs2 = 6'h0; // @[consts.scala:269:19] wire [5:0] stq_1_bits_uop_uop_prs3 = 6'h0; // @[consts.scala:269:19] wire [5:0] stq_1_bits_uop_uop_stale_pdst = 6'h0; // @[consts.scala:269:19] wire [5:0] stq_1_bits_uop_uop_ldst = 6'h0; // @[consts.scala:269:19] wire [5:0] stq_1_bits_uop_uop_lrs1 = 6'h0; // @[consts.scala:269:19] wire [5:0] stq_1_bits_uop_uop_lrs2 = 6'h0; // @[consts.scala:269:19] wire [5:0] stq_1_bits_uop_uop_lrs3 = 6'h0; // @[consts.scala:269:19] wire [5:0] stq_2_bits_uop_uop_pc_lob = 6'h0; // @[consts.scala:269:19] wire [5:0] stq_2_bits_uop_uop_pdst = 6'h0; // @[consts.scala:269:19] wire [5:0] stq_2_bits_uop_uop_prs1 = 6'h0; // @[consts.scala:269:19] wire [5:0] stq_2_bits_uop_uop_prs2 = 6'h0; // @[consts.scala:269:19] wire [5:0] stq_2_bits_uop_uop_prs3 = 6'h0; // @[consts.scala:269:19] wire [5:0] stq_2_bits_uop_uop_stale_pdst = 6'h0; // @[consts.scala:269:19] wire [5:0] stq_2_bits_uop_uop_ldst = 6'h0; // @[consts.scala:269:19] wire [5:0] stq_2_bits_uop_uop_lrs1 = 6'h0; // @[consts.scala:269:19] wire [5:0] stq_2_bits_uop_uop_lrs2 = 6'h0; // @[consts.scala:269:19] wire [5:0] stq_2_bits_uop_uop_lrs3 = 6'h0; // @[consts.scala:269:19] wire [5:0] stq_3_bits_uop_uop_pc_lob = 6'h0; // @[consts.scala:269:19] wire [5:0] stq_3_bits_uop_uop_pdst = 6'h0; // @[consts.scala:269:19] wire [5:0] stq_3_bits_uop_uop_prs1 = 6'h0; // @[consts.scala:269:19] wire [5:0] stq_3_bits_uop_uop_prs2 = 6'h0; // @[consts.scala:269:19] wire [5:0] stq_3_bits_uop_uop_prs3 = 6'h0; // @[consts.scala:269:19] wire [5:0] stq_3_bits_uop_uop_stale_pdst = 6'h0; // @[consts.scala:269:19] wire [5:0] stq_3_bits_uop_uop_ldst = 6'h0; // @[consts.scala:269:19] wire [5:0] stq_3_bits_uop_uop_lrs1 = 6'h0; // @[consts.scala:269:19] wire [5:0] stq_3_bits_uop_uop_lrs2 = 6'h0; // @[consts.scala:269:19] wire [5:0] stq_3_bits_uop_uop_lrs3 = 6'h0; // @[consts.scala:269:19] wire [5:0] stq_4_bits_uop_uop_pc_lob = 6'h0; // @[consts.scala:269:19] wire [5:0] stq_4_bits_uop_uop_pdst = 6'h0; // @[consts.scala:269:19] wire [5:0] stq_4_bits_uop_uop_prs1 = 6'h0; // @[consts.scala:269:19] wire [5:0] stq_4_bits_uop_uop_prs2 = 6'h0; // @[consts.scala:269:19] wire [5:0] stq_4_bits_uop_uop_prs3 = 6'h0; // @[consts.scala:269:19] wire [5:0] stq_4_bits_uop_uop_stale_pdst = 6'h0; // @[consts.scala:269:19] wire [5:0] stq_4_bits_uop_uop_ldst = 6'h0; // @[consts.scala:269:19] wire [5:0] stq_4_bits_uop_uop_lrs1 = 6'h0; // @[consts.scala:269:19] wire [5:0] stq_4_bits_uop_uop_lrs2 = 6'h0; // @[consts.scala:269:19] wire [5:0] stq_4_bits_uop_uop_lrs3 = 6'h0; // @[consts.scala:269:19] wire [5:0] stq_5_bits_uop_uop_pc_lob = 6'h0; // @[consts.scala:269:19] wire [5:0] stq_5_bits_uop_uop_pdst = 6'h0; // @[consts.scala:269:19] wire [5:0] stq_5_bits_uop_uop_prs1 = 6'h0; // @[consts.scala:269:19] wire [5:0] stq_5_bits_uop_uop_prs2 = 6'h0; // @[consts.scala:269:19] wire [5:0] stq_5_bits_uop_uop_prs3 = 6'h0; // @[consts.scala:269:19] wire [5:0] stq_5_bits_uop_uop_stale_pdst = 6'h0; // @[consts.scala:269:19] wire [5:0] stq_5_bits_uop_uop_ldst = 6'h0; // @[consts.scala:269:19] wire [5:0] stq_5_bits_uop_uop_lrs1 = 6'h0; // @[consts.scala:269:19] wire [5:0] stq_5_bits_uop_uop_lrs2 = 6'h0; // @[consts.scala:269:19] wire [5:0] stq_5_bits_uop_uop_lrs3 = 6'h0; // @[consts.scala:269:19] wire [5:0] stq_6_bits_uop_uop_pc_lob = 6'h0; // @[consts.scala:269:19] wire [5:0] stq_6_bits_uop_uop_pdst = 6'h0; // @[consts.scala:269:19] wire [5:0] stq_6_bits_uop_uop_prs1 = 6'h0; // @[consts.scala:269:19] wire [5:0] stq_6_bits_uop_uop_prs2 = 6'h0; // @[consts.scala:269:19] wire [5:0] stq_6_bits_uop_uop_prs3 = 6'h0; // @[consts.scala:269:19] wire [5:0] stq_6_bits_uop_uop_stale_pdst = 6'h0; // @[consts.scala:269:19] wire [5:0] stq_6_bits_uop_uop_ldst = 6'h0; // @[consts.scala:269:19] wire [5:0] stq_6_bits_uop_uop_lrs1 = 6'h0; // @[consts.scala:269:19] wire [5:0] stq_6_bits_uop_uop_lrs2 = 6'h0; // @[consts.scala:269:19] wire [5:0] stq_6_bits_uop_uop_lrs3 = 6'h0; // @[consts.scala:269:19] wire [5:0] stq_7_bits_uop_uop_pc_lob = 6'h0; // @[consts.scala:269:19] wire [5:0] stq_7_bits_uop_uop_pdst = 6'h0; // @[consts.scala:269:19] wire [5:0] stq_7_bits_uop_uop_prs1 = 6'h0; // @[consts.scala:269:19] wire [5:0] stq_7_bits_uop_uop_prs2 = 6'h0; // @[consts.scala:269:19] wire [5:0] stq_7_bits_uop_uop_prs3 = 6'h0; // @[consts.scala:269:19] wire [5:0] stq_7_bits_uop_uop_stale_pdst = 6'h0; // @[consts.scala:269:19] wire [5:0] stq_7_bits_uop_uop_ldst = 6'h0; // @[consts.scala:269:19] wire [5:0] stq_7_bits_uop_uop_lrs1 = 6'h0; // @[consts.scala:269:19] wire [5:0] stq_7_bits_uop_uop_lrs2 = 6'h0; // @[consts.scala:269:19] wire [5:0] stq_7_bits_uop_uop_lrs3 = 6'h0; // @[consts.scala:269:19] wire [31:0] io_ptw_gstatus_isa = 32'h0; // @[lsu.scala:201:7] wire [31:0] io_core_exe_0_req_bits_fflags_bits_uop_inst = 32'h0; // @[lsu.scala:201:7] wire [31:0] io_core_exe_0_req_bits_fflags_bits_uop_debug_inst = 32'h0; // @[lsu.scala:201:7] wire [31:0] io_core_exe_0_iresp_bits_fflags_bits_uop_inst = 32'h0; // @[lsu.scala:201:7] wire [31:0] io_core_exe_0_iresp_bits_fflags_bits_uop_debug_inst = 32'h0; // @[lsu.scala:201:7] wire [31:0] io_core_exe_0_fresp_bits_fflags_bits_uop_inst = 32'h0; // @[lsu.scala:201:7] wire [31:0] io_core_exe_0_fresp_bits_fflags_bits_uop_debug_inst = 32'h0; // @[lsu.scala:201:7] wire [31:0] io_hellacache_s2_paddr = 32'h0; // @[lsu.scala:201:7] wire [31:0] _exe_req_WIRE_0_bits_fflags_bits_uop_inst = 32'h0; // @[lsu.scala:383:33] wire [31:0] _exe_req_WIRE_0_bits_fflags_bits_uop_debug_inst = 32'h0; // @[lsu.scala:383:33] wire [31:0] exe_req_0_bits_fflags_bits_uop_inst = 32'h0; // @[lsu.scala:383:25] wire [31:0] exe_req_0_bits_fflags_bits_uop_debug_inst = 32'h0; // @[lsu.scala:383:25] wire [31:0] exe_tlb_uop_uop_inst = 32'h0; // @[consts.scala:269:19] wire [31:0] exe_tlb_uop_uop_debug_inst = 32'h0; // @[consts.scala:269:19] wire [31:0] exe_tlb_uop_uop_1_inst = 32'h0; // @[consts.scala:269:19] wire [31:0] exe_tlb_uop_uop_1_debug_inst = 32'h0; // @[consts.scala:269:19] wire [31:0] _exe_tlb_uop_T_3_inst = 32'h0; // @[lsu.scala:602:24] wire [31:0] _exe_tlb_uop_T_3_debug_inst = 32'h0; // @[lsu.scala:602:24] wire [31:0] dmem_req_0_bits_uop_uop_inst = 32'h0; // @[consts.scala:269:19] wire [31:0] dmem_req_0_bits_uop_uop_debug_inst = 32'h0; // @[consts.scala:269:19] wire [31:0] _dmem_req_0_bits_data_T_18 = 32'h0; // @[AMOALU.scala:29:32] wire [31:0] _dmem_req_0_bits_data_T_22 = 32'h0; // @[AMOALU.scala:29:32] wire [31:0] _dmem_req_0_bits_data_T_25 = 32'h0; // @[AMOALU.scala:29:69] wire [31:0] _mem_ldq_e_WIRE_bits_uop_inst = 32'h0; // @[lsu.scala:918:90] wire [31:0] _mem_ldq_e_WIRE_bits_uop_debug_inst = 32'h0; // @[lsu.scala:918:90] wire [31:0] _mem_stq_e_WIRE_bits_uop_inst = 32'h0; // @[lsu.scala:922:89] wire [31:0] _mem_stq_e_WIRE_bits_uop_debug_inst = 32'h0; // @[lsu.scala:922:89] wire [31:0] lcam_uop_uop_inst = 32'h0; // @[consts.scala:269:19] wire [31:0] lcam_uop_uop_debug_inst = 32'h0; // @[consts.scala:269:19] wire [31:0] stq_0_bits_uop_uop_inst = 32'h0; // @[consts.scala:269:19] wire [31:0] stq_0_bits_uop_uop_debug_inst = 32'h0; // @[consts.scala:269:19] wire [31:0] stq_1_bits_uop_uop_inst = 32'h0; // @[consts.scala:269:19] wire [31:0] stq_1_bits_uop_uop_debug_inst = 32'h0; // @[consts.scala:269:19] wire [31:0] stq_2_bits_uop_uop_inst = 32'h0; // @[consts.scala:269:19] wire [31:0] stq_2_bits_uop_uop_debug_inst = 32'h0; // @[consts.scala:269:19] wire [31:0] stq_3_bits_uop_uop_inst = 32'h0; // @[consts.scala:269:19] wire [31:0] stq_3_bits_uop_uop_debug_inst = 32'h0; // @[consts.scala:269:19] wire [31:0] stq_4_bits_uop_uop_inst = 32'h0; // @[consts.scala:269:19] wire [31:0] stq_4_bits_uop_uop_debug_inst = 32'h0; // @[consts.scala:269:19] wire [31:0] stq_5_bits_uop_uop_inst = 32'h0; // @[consts.scala:269:19] wire [31:0] stq_5_bits_uop_uop_debug_inst = 32'h0; // @[consts.scala:269:19] wire [31:0] stq_6_bits_uop_uop_inst = 32'h0; // @[consts.scala:269:19] wire [31:0] stq_6_bits_uop_uop_debug_inst = 32'h0; // @[consts.scala:269:19] wire [31:0] stq_7_bits_uop_uop_inst = 32'h0; // @[consts.scala:269:19] wire [31:0] stq_7_bits_uop_uop_debug_inst = 32'h0; // @[consts.scala:269:19] wire [39:0] io_core_exe_0_req_bits_fflags_bits_uop_debug_pc = 40'h0; // @[lsu.scala:201:7] wire [39:0] io_core_exe_0_iresp_bits_fflags_bits_uop_debug_pc = 40'h0; // @[lsu.scala:201:7] wire [39:0] io_core_exe_0_fresp_bits_fflags_bits_uop_debug_pc = 40'h0; // @[lsu.scala:201:7] wire [39:0] io_hellacache_s2_gpa = 40'h0; // @[lsu.scala:201:7] wire [39:0] _exe_req_WIRE_0_bits_fflags_bits_uop_debug_pc = 40'h0; // @[lsu.scala:383:33] wire [39:0] exe_req_0_bits_fflags_bits_uop_debug_pc = 40'h0; // @[lsu.scala:383:25] wire [39:0] exe_tlb_uop_uop_debug_pc = 40'h0; // @[consts.scala:269:19] wire [39:0] exe_tlb_uop_uop_1_debug_pc = 40'h0; // @[consts.scala:269:19] wire [39:0] _exe_tlb_uop_T_3_debug_pc = 40'h0; // @[lsu.scala:602:24] wire [39:0] dmem_req_0_bits_uop_uop_debug_pc = 40'h0; // @[consts.scala:269:19] wire [39:0] _mem_ldq_e_WIRE_bits_uop_debug_pc = 40'h0; // @[lsu.scala:918:90] wire [39:0] _mem_ldq_e_WIRE_bits_addr_bits = 40'h0; // @[lsu.scala:918:90] wire [39:0] _mem_stq_e_WIRE_bits_uop_debug_pc = 40'h0; // @[lsu.scala:922:89] wire [39:0] _mem_stq_e_WIRE_bits_addr_bits = 40'h0; // @[lsu.scala:922:89] wire [39:0] lcam_uop_uop_debug_pc = 40'h0; // @[consts.scala:269:19] wire [39:0] stq_0_bits_uop_uop_debug_pc = 40'h0; // @[consts.scala:269:19] wire [39:0] stq_1_bits_uop_uop_debug_pc = 40'h0; // @[consts.scala:269:19] wire [39:0] stq_2_bits_uop_uop_debug_pc = 40'h0; // @[consts.scala:269:19] wire [39:0] stq_3_bits_uop_uop_debug_pc = 40'h0; // @[consts.scala:269:19] wire [39:0] stq_4_bits_uop_uop_debug_pc = 40'h0; // @[consts.scala:269:19] wire [39:0] stq_5_bits_uop_uop_debug_pc = 40'h0; // @[consts.scala:269:19] wire [39:0] stq_6_bits_uop_uop_debug_pc = 40'h0; // @[consts.scala:269:19] wire [39:0] stq_7_bits_uop_uop_debug_pc = 40'h0; // @[consts.scala:269:19] wire [2:0] io_core_exe_0_req_bits_fflags_bits_uop_iq_type = 3'h0; // @[lsu.scala:201:7] wire [2:0] io_core_exe_0_req_bits_fflags_bits_uop_ctrl_op2_sel = 3'h0; // @[lsu.scala:201:7] wire [2:0] io_core_exe_0_req_bits_fflags_bits_uop_ctrl_imm_sel = 3'h0; // @[lsu.scala:201:7] wire [2:0] io_core_exe_0_req_bits_fflags_bits_uop_ctrl_csr_cmd = 3'h0; // @[lsu.scala:201:7] wire [2:0] io_core_exe_0_req_bits_fflags_bits_uop_br_tag = 3'h0; // @[lsu.scala:201:7] wire [2:0] io_core_exe_0_req_bits_fflags_bits_uop_ldq_idx = 3'h0; // @[lsu.scala:201:7] wire [2:0] io_core_exe_0_req_bits_fflags_bits_uop_stq_idx = 3'h0; // @[lsu.scala:201:7] wire [2:0] io_core_exe_0_iresp_bits_fflags_bits_uop_iq_type = 3'h0; // @[lsu.scala:201:7] wire [2:0] io_core_exe_0_iresp_bits_fflags_bits_uop_ctrl_op2_sel = 3'h0; // @[lsu.scala:201:7] wire [2:0] io_core_exe_0_iresp_bits_fflags_bits_uop_ctrl_imm_sel = 3'h0; // @[lsu.scala:201:7] wire [2:0] io_core_exe_0_iresp_bits_fflags_bits_uop_ctrl_csr_cmd = 3'h0; // @[lsu.scala:201:7] wire [2:0] io_core_exe_0_iresp_bits_fflags_bits_uop_br_tag = 3'h0; // @[lsu.scala:201:7] wire [2:0] io_core_exe_0_iresp_bits_fflags_bits_uop_ldq_idx = 3'h0; // @[lsu.scala:201:7] wire [2:0] io_core_exe_0_iresp_bits_fflags_bits_uop_stq_idx = 3'h0; // @[lsu.scala:201:7] wire [2:0] io_core_exe_0_fresp_bits_fflags_bits_uop_iq_type = 3'h0; // @[lsu.scala:201:7] wire [2:0] io_core_exe_0_fresp_bits_fflags_bits_uop_ctrl_op2_sel = 3'h0; // @[lsu.scala:201:7] wire [2:0] io_core_exe_0_fresp_bits_fflags_bits_uop_ctrl_imm_sel = 3'h0; // @[lsu.scala:201:7] wire [2:0] io_core_exe_0_fresp_bits_fflags_bits_uop_ctrl_csr_cmd = 3'h0; // @[lsu.scala:201:7] wire [2:0] io_core_exe_0_fresp_bits_fflags_bits_uop_br_tag = 3'h0; // @[lsu.scala:201:7] wire [2:0] io_core_exe_0_fresp_bits_fflags_bits_uop_ldq_idx = 3'h0; // @[lsu.scala:201:7] wire [2:0] io_core_exe_0_fresp_bits_fflags_bits_uop_stq_idx = 3'h0; // @[lsu.scala:201:7] wire [2:0] _exe_req_WIRE_0_bits_fflags_bits_uop_iq_type = 3'h0; // @[lsu.scala:383:33] wire [2:0] _exe_req_WIRE_0_bits_fflags_bits_uop_ctrl_op2_sel = 3'h0; // @[lsu.scala:383:33] wire [2:0] _exe_req_WIRE_0_bits_fflags_bits_uop_ctrl_imm_sel = 3'h0; // @[lsu.scala:383:33] wire [2:0] _exe_req_WIRE_0_bits_fflags_bits_uop_ctrl_csr_cmd = 3'h0; // @[lsu.scala:383:33] wire [2:0] _exe_req_WIRE_0_bits_fflags_bits_uop_br_tag = 3'h0; // @[lsu.scala:383:33] wire [2:0] _exe_req_WIRE_0_bits_fflags_bits_uop_ldq_idx = 3'h0; // @[lsu.scala:383:33] wire [2:0] _exe_req_WIRE_0_bits_fflags_bits_uop_stq_idx = 3'h0; // @[lsu.scala:383:33] wire [2:0] exe_req_0_bits_fflags_bits_uop_iq_type = 3'h0; // @[lsu.scala:383:25] wire [2:0] exe_req_0_bits_fflags_bits_uop_ctrl_op2_sel = 3'h0; // @[lsu.scala:383:25] wire [2:0] exe_req_0_bits_fflags_bits_uop_ctrl_imm_sel = 3'h0; // @[lsu.scala:383:25] wire [2:0] exe_req_0_bits_fflags_bits_uop_ctrl_csr_cmd = 3'h0; // @[lsu.scala:383:25] wire [2:0] exe_req_0_bits_fflags_bits_uop_br_tag = 3'h0; // @[lsu.scala:383:25] wire [2:0] exe_req_0_bits_fflags_bits_uop_ldq_idx = 3'h0; // @[lsu.scala:383:25] wire [2:0] exe_req_0_bits_fflags_bits_uop_stq_idx = 3'h0; // @[lsu.scala:383:25] wire [2:0] exe_tlb_uop_uop_iq_type = 3'h0; // @[consts.scala:269:19] wire [2:0] exe_tlb_uop_uop_ctrl_op2_sel = 3'h0; // @[consts.scala:269:19] wire [2:0] exe_tlb_uop_uop_ctrl_imm_sel = 3'h0; // @[consts.scala:269:19] wire [2:0] exe_tlb_uop_uop_ctrl_csr_cmd = 3'h0; // @[consts.scala:269:19] wire [2:0] exe_tlb_uop_uop_br_tag = 3'h0; // @[consts.scala:269:19] wire [2:0] exe_tlb_uop_uop_ldq_idx = 3'h0; // @[consts.scala:269:19] wire [2:0] exe_tlb_uop_uop_stq_idx = 3'h0; // @[consts.scala:269:19] wire [2:0] exe_tlb_uop_cs_op2_sel = 3'h0; // @[consts.scala:279:18] wire [2:0] exe_tlb_uop_cs_imm_sel = 3'h0; // @[consts.scala:279:18] wire [2:0] exe_tlb_uop_cs_csr_cmd = 3'h0; // @[consts.scala:279:18] wire [2:0] exe_tlb_uop_uop_1_iq_type = 3'h0; // @[consts.scala:269:19] wire [2:0] exe_tlb_uop_uop_1_ctrl_op2_sel = 3'h0; // @[consts.scala:269:19] wire [2:0] exe_tlb_uop_uop_1_ctrl_imm_sel = 3'h0; // @[consts.scala:269:19] wire [2:0] exe_tlb_uop_uop_1_ctrl_csr_cmd = 3'h0; // @[consts.scala:269:19] wire [2:0] exe_tlb_uop_uop_1_br_tag = 3'h0; // @[consts.scala:269:19] wire [2:0] exe_tlb_uop_uop_1_ldq_idx = 3'h0; // @[consts.scala:269:19] wire [2:0] exe_tlb_uop_uop_1_stq_idx = 3'h0; // @[consts.scala:269:19] wire [2:0] exe_tlb_uop_cs_1_op2_sel = 3'h0; // @[consts.scala:279:18] wire [2:0] exe_tlb_uop_cs_1_imm_sel = 3'h0; // @[consts.scala:279:18] wire [2:0] exe_tlb_uop_cs_1_csr_cmd = 3'h0; // @[consts.scala:279:18] wire [2:0] _exe_tlb_uop_T_3_iq_type = 3'h0; // @[lsu.scala:602:24] wire [2:0] _exe_tlb_uop_T_3_ctrl_op2_sel = 3'h0; // @[lsu.scala:602:24] wire [2:0] _exe_tlb_uop_T_3_ctrl_imm_sel = 3'h0; // @[lsu.scala:602:24] wire [2:0] _exe_tlb_uop_T_3_ctrl_csr_cmd = 3'h0; // @[lsu.scala:602:24] wire [2:0] _exe_tlb_uop_T_3_br_tag = 3'h0; // @[lsu.scala:602:24] wire [2:0] _exe_tlb_uop_T_3_ldq_idx = 3'h0; // @[lsu.scala:602:24] wire [2:0] _exe_tlb_uop_T_3_stq_idx = 3'h0; // @[lsu.scala:602:24] wire [2:0] dmem_req_0_bits_uop_uop_iq_type = 3'h0; // @[consts.scala:269:19] wire [2:0] dmem_req_0_bits_uop_uop_ctrl_op2_sel = 3'h0; // @[consts.scala:269:19] wire [2:0] dmem_req_0_bits_uop_uop_ctrl_imm_sel = 3'h0; // @[consts.scala:269:19] wire [2:0] dmem_req_0_bits_uop_uop_ctrl_csr_cmd = 3'h0; // @[consts.scala:269:19] wire [2:0] dmem_req_0_bits_uop_uop_br_tag = 3'h0; // @[consts.scala:269:19] wire [2:0] dmem_req_0_bits_uop_uop_ldq_idx = 3'h0; // @[consts.scala:269:19] wire [2:0] dmem_req_0_bits_uop_uop_stq_idx = 3'h0; // @[consts.scala:269:19] wire [2:0] dmem_req_0_bits_uop_cs_op2_sel = 3'h0; // @[consts.scala:279:18] wire [2:0] dmem_req_0_bits_uop_cs_imm_sel = 3'h0; // @[consts.scala:279:18] wire [2:0] dmem_req_0_bits_uop_cs_csr_cmd = 3'h0; // @[consts.scala:279:18] wire [2:0] _mem_ldq_e_WIRE_bits_uop_iq_type = 3'h0; // @[lsu.scala:918:90] wire [2:0] _mem_ldq_e_WIRE_bits_uop_ctrl_op2_sel = 3'h0; // @[lsu.scala:918:90] wire [2:0] _mem_ldq_e_WIRE_bits_uop_ctrl_imm_sel = 3'h0; // @[lsu.scala:918:90] wire [2:0] _mem_ldq_e_WIRE_bits_uop_ctrl_csr_cmd = 3'h0; // @[lsu.scala:918:90] wire [2:0] _mem_ldq_e_WIRE_bits_uop_br_tag = 3'h0; // @[lsu.scala:918:90] wire [2:0] _mem_ldq_e_WIRE_bits_uop_ldq_idx = 3'h0; // @[lsu.scala:918:90] wire [2:0] _mem_ldq_e_WIRE_bits_uop_stq_idx = 3'h0; // @[lsu.scala:918:90] wire [2:0] _mem_ldq_e_WIRE_bits_youngest_stq_idx = 3'h0; // @[lsu.scala:918:90] wire [2:0] _mem_ldq_e_WIRE_bits_forward_stq_idx = 3'h0; // @[lsu.scala:918:90] wire [2:0] _mem_stq_e_WIRE_bits_uop_iq_type = 3'h0; // @[lsu.scala:922:89] wire [2:0] _mem_stq_e_WIRE_bits_uop_ctrl_op2_sel = 3'h0; // @[lsu.scala:922:89] wire [2:0] _mem_stq_e_WIRE_bits_uop_ctrl_imm_sel = 3'h0; // @[lsu.scala:922:89] wire [2:0] _mem_stq_e_WIRE_bits_uop_ctrl_csr_cmd = 3'h0; // @[lsu.scala:922:89] wire [2:0] _mem_stq_e_WIRE_bits_uop_br_tag = 3'h0; // @[lsu.scala:922:89] wire [2:0] _mem_stq_e_WIRE_bits_uop_ldq_idx = 3'h0; // @[lsu.scala:922:89] wire [2:0] _mem_stq_e_WIRE_bits_uop_stq_idx = 3'h0; // @[lsu.scala:922:89] wire [2:0] lcam_uop_uop_iq_type = 3'h0; // @[consts.scala:269:19] wire [2:0] lcam_uop_uop_ctrl_op2_sel = 3'h0; // @[consts.scala:269:19] wire [2:0] lcam_uop_uop_ctrl_imm_sel = 3'h0; // @[consts.scala:269:19] wire [2:0] lcam_uop_uop_ctrl_csr_cmd = 3'h0; // @[consts.scala:269:19] wire [2:0] lcam_uop_uop_br_tag = 3'h0; // @[consts.scala:269:19] wire [2:0] lcam_uop_uop_ldq_idx = 3'h0; // @[consts.scala:269:19] wire [2:0] lcam_uop_uop_stq_idx = 3'h0; // @[consts.scala:269:19] wire [2:0] lcam_uop_cs_op2_sel = 3'h0; // @[consts.scala:279:18] wire [2:0] lcam_uop_cs_imm_sel = 3'h0; // @[consts.scala:279:18] wire [2:0] lcam_uop_cs_csr_cmd = 3'h0; // @[consts.scala:279:18] wire [2:0] stq_0_bits_uop_uop_iq_type = 3'h0; // @[consts.scala:269:19] wire [2:0] stq_0_bits_uop_uop_ctrl_op2_sel = 3'h0; // @[consts.scala:269:19] wire [2:0] stq_0_bits_uop_uop_ctrl_imm_sel = 3'h0; // @[consts.scala:269:19] wire [2:0] stq_0_bits_uop_uop_ctrl_csr_cmd = 3'h0; // @[consts.scala:269:19] wire [2:0] stq_0_bits_uop_uop_br_tag = 3'h0; // @[consts.scala:269:19] wire [2:0] stq_0_bits_uop_uop_ldq_idx = 3'h0; // @[consts.scala:269:19] wire [2:0] stq_0_bits_uop_uop_stq_idx = 3'h0; // @[consts.scala:269:19] wire [2:0] stq_0_bits_uop_cs_op2_sel = 3'h0; // @[consts.scala:279:18] wire [2:0] stq_0_bits_uop_cs_imm_sel = 3'h0; // @[consts.scala:279:18] wire [2:0] stq_0_bits_uop_cs_csr_cmd = 3'h0; // @[consts.scala:279:18] wire [2:0] stq_1_bits_uop_uop_iq_type = 3'h0; // @[consts.scala:269:19] wire [2:0] stq_1_bits_uop_uop_ctrl_op2_sel = 3'h0; // @[consts.scala:269:19] wire [2:0] stq_1_bits_uop_uop_ctrl_imm_sel = 3'h0; // @[consts.scala:269:19] wire [2:0] stq_1_bits_uop_uop_ctrl_csr_cmd = 3'h0; // @[consts.scala:269:19] wire [2:0] stq_1_bits_uop_uop_br_tag = 3'h0; // @[consts.scala:269:19] wire [2:0] stq_1_bits_uop_uop_ldq_idx = 3'h0; // @[consts.scala:269:19] wire [2:0] stq_1_bits_uop_uop_stq_idx = 3'h0; // @[consts.scala:269:19] wire [2:0] stq_1_bits_uop_cs_op2_sel = 3'h0; // @[consts.scala:279:18] wire [2:0] stq_1_bits_uop_cs_imm_sel = 3'h0; // @[consts.scala:279:18] wire [2:0] stq_1_bits_uop_cs_csr_cmd = 3'h0; // @[consts.scala:279:18] wire [2:0] stq_2_bits_uop_uop_iq_type = 3'h0; // @[consts.scala:269:19] wire [2:0] stq_2_bits_uop_uop_ctrl_op2_sel = 3'h0; // @[consts.scala:269:19] wire [2:0] stq_2_bits_uop_uop_ctrl_imm_sel = 3'h0; // @[consts.scala:269:19] wire [2:0] stq_2_bits_uop_uop_ctrl_csr_cmd = 3'h0; // @[consts.scala:269:19] wire [2:0] stq_2_bits_uop_uop_br_tag = 3'h0; // @[consts.scala:269:19] wire [2:0] stq_2_bits_uop_uop_ldq_idx = 3'h0; // @[consts.scala:269:19] wire [2:0] stq_2_bits_uop_uop_stq_idx = 3'h0; // @[consts.scala:269:19] wire [2:0] stq_2_bits_uop_cs_op2_sel = 3'h0; // @[consts.scala:279:18] wire [2:0] stq_2_bits_uop_cs_imm_sel = 3'h0; // @[consts.scala:279:18] wire [2:0] stq_2_bits_uop_cs_csr_cmd = 3'h0; // @[consts.scala:279:18] wire [2:0] stq_3_bits_uop_uop_iq_type = 3'h0; // @[consts.scala:269:19] wire [2:0] stq_3_bits_uop_uop_ctrl_op2_sel = 3'h0; // @[consts.scala:269:19] wire [2:0] stq_3_bits_uop_uop_ctrl_imm_sel = 3'h0; // @[consts.scala:269:19] wire [2:0] stq_3_bits_uop_uop_ctrl_csr_cmd = 3'h0; // @[consts.scala:269:19] wire [2:0] stq_3_bits_uop_uop_br_tag = 3'h0; // @[consts.scala:269:19] wire [2:0] stq_3_bits_uop_uop_ldq_idx = 3'h0; // @[consts.scala:269:19] wire [2:0] stq_3_bits_uop_uop_stq_idx = 3'h0; // @[consts.scala:269:19] wire [2:0] stq_3_bits_uop_cs_op2_sel = 3'h0; // @[consts.scala:279:18] wire [2:0] stq_3_bits_uop_cs_imm_sel = 3'h0; // @[consts.scala:279:18] wire [2:0] stq_3_bits_uop_cs_csr_cmd = 3'h0; // @[consts.scala:279:18] wire [2:0] stq_4_bits_uop_uop_iq_type = 3'h0; // @[consts.scala:269:19] wire [2:0] stq_4_bits_uop_uop_ctrl_op2_sel = 3'h0; // @[consts.scala:269:19] wire [2:0] stq_4_bits_uop_uop_ctrl_imm_sel = 3'h0; // @[consts.scala:269:19] wire [2:0] stq_4_bits_uop_uop_ctrl_csr_cmd = 3'h0; // @[consts.scala:269:19] wire [2:0] stq_4_bits_uop_uop_br_tag = 3'h0; // @[consts.scala:269:19] wire [2:0] stq_4_bits_uop_uop_ldq_idx = 3'h0; // @[consts.scala:269:19] wire [2:0] stq_4_bits_uop_uop_stq_idx = 3'h0; // @[consts.scala:269:19] wire [2:0] stq_4_bits_uop_cs_op2_sel = 3'h0; // @[consts.scala:279:18] wire [2:0] stq_4_bits_uop_cs_imm_sel = 3'h0; // @[consts.scala:279:18] wire [2:0] stq_4_bits_uop_cs_csr_cmd = 3'h0; // @[consts.scala:279:18] wire [2:0] stq_5_bits_uop_uop_iq_type = 3'h0; // @[consts.scala:269:19] wire [2:0] stq_5_bits_uop_uop_ctrl_op2_sel = 3'h0; // @[consts.scala:269:19] wire [2:0] stq_5_bits_uop_uop_ctrl_imm_sel = 3'h0; // @[consts.scala:269:19] wire [2:0] stq_5_bits_uop_uop_ctrl_csr_cmd = 3'h0; // @[consts.scala:269:19] wire [2:0] stq_5_bits_uop_uop_br_tag = 3'h0; // @[consts.scala:269:19] wire [2:0] stq_5_bits_uop_uop_ldq_idx = 3'h0; // @[consts.scala:269:19] wire [2:0] stq_5_bits_uop_uop_stq_idx = 3'h0; // @[consts.scala:269:19] wire [2:0] stq_5_bits_uop_cs_op2_sel = 3'h0; // @[consts.scala:279:18] wire [2:0] stq_5_bits_uop_cs_imm_sel = 3'h0; // @[consts.scala:279:18] wire [2:0] stq_5_bits_uop_cs_csr_cmd = 3'h0; // @[consts.scala:279:18] wire [2:0] stq_6_bits_uop_uop_iq_type = 3'h0; // @[consts.scala:269:19] wire [2:0] stq_6_bits_uop_uop_ctrl_op2_sel = 3'h0; // @[consts.scala:269:19] wire [2:0] stq_6_bits_uop_uop_ctrl_imm_sel = 3'h0; // @[consts.scala:269:19] wire [2:0] stq_6_bits_uop_uop_ctrl_csr_cmd = 3'h0; // @[consts.scala:269:19] wire [2:0] stq_6_bits_uop_uop_br_tag = 3'h0; // @[consts.scala:269:19] wire [2:0] stq_6_bits_uop_uop_ldq_idx = 3'h0; // @[consts.scala:269:19] wire [2:0] stq_6_bits_uop_uop_stq_idx = 3'h0; // @[consts.scala:269:19] wire [2:0] stq_6_bits_uop_cs_op2_sel = 3'h0; // @[consts.scala:279:18] wire [2:0] stq_6_bits_uop_cs_imm_sel = 3'h0; // @[consts.scala:279:18] wire [2:0] stq_6_bits_uop_cs_csr_cmd = 3'h0; // @[consts.scala:279:18] wire [2:0] stq_7_bits_uop_uop_iq_type = 3'h0; // @[consts.scala:269:19] wire [2:0] stq_7_bits_uop_uop_ctrl_op2_sel = 3'h0; // @[consts.scala:269:19] wire [2:0] stq_7_bits_uop_uop_ctrl_imm_sel = 3'h0; // @[consts.scala:269:19] wire [2:0] stq_7_bits_uop_uop_ctrl_csr_cmd = 3'h0; // @[consts.scala:269:19] wire [2:0] stq_7_bits_uop_uop_br_tag = 3'h0; // @[consts.scala:269:19] wire [2:0] stq_7_bits_uop_uop_ldq_idx = 3'h0; // @[consts.scala:269:19] wire [2:0] stq_7_bits_uop_uop_stq_idx = 3'h0; // @[consts.scala:269:19] wire [2:0] stq_7_bits_uop_cs_op2_sel = 3'h0; // @[consts.scala:279:18] wire [2:0] stq_7_bits_uop_cs_imm_sel = 3'h0; // @[consts.scala:279:18] wire [2:0] stq_7_bits_uop_cs_csr_cmd = 3'h0; // @[consts.scala:279:18] wire [9:0] io_core_exe_0_req_bits_fflags_bits_uop_fu_code = 10'h0; // @[lsu.scala:201:7] wire [9:0] io_core_exe_0_iresp_bits_fflags_bits_uop_fu_code = 10'h0; // @[lsu.scala:201:7] wire [9:0] io_core_exe_0_fresp_bits_fflags_bits_uop_fu_code = 10'h0; // @[lsu.scala:201:7] wire [9:0] _exe_req_WIRE_0_bits_fflags_bits_uop_fu_code = 10'h0; // @[lsu.scala:383:33] wire [9:0] exe_req_0_bits_fflags_bits_uop_fu_code = 10'h0; // @[lsu.scala:383:25] wire [9:0] exe_tlb_uop_uop_fu_code = 10'h0; // @[consts.scala:269:19] wire [9:0] exe_tlb_uop_uop_1_fu_code = 10'h0; // @[consts.scala:269:19] wire [9:0] _exe_tlb_uop_T_3_fu_code = 10'h0; // @[lsu.scala:602:24] wire [9:0] dmem_req_0_bits_uop_uop_fu_code = 10'h0; // @[consts.scala:269:19] wire [9:0] _mem_ldq_e_WIRE_bits_uop_fu_code = 10'h0; // @[lsu.scala:918:90] wire [9:0] _mem_stq_e_WIRE_bits_uop_fu_code = 10'h0; // @[lsu.scala:922:89] wire [9:0] lcam_uop_uop_fu_code = 10'h0; // @[consts.scala:269:19] wire [9:0] stq_0_bits_uop_uop_fu_code = 10'h0; // @[consts.scala:269:19] wire [9:0] stq_1_bits_uop_uop_fu_code = 10'h0; // @[consts.scala:269:19] wire [9:0] stq_2_bits_uop_uop_fu_code = 10'h0; // @[consts.scala:269:19] wire [9:0] stq_3_bits_uop_uop_fu_code = 10'h0; // @[consts.scala:269:19] wire [9:0] stq_4_bits_uop_uop_fu_code = 10'h0; // @[consts.scala:269:19] wire [9:0] stq_5_bits_uop_uop_fu_code = 10'h0; // @[consts.scala:269:19] wire [9:0] stq_6_bits_uop_uop_fu_code = 10'h0; // @[consts.scala:269:19] wire [9:0] stq_7_bits_uop_uop_fu_code = 10'h0; // @[consts.scala:269:19] wire [19:0] io_core_exe_0_req_bits_fflags_bits_uop_imm_packed = 20'h0; // @[lsu.scala:201:7] wire [19:0] io_core_exe_0_iresp_bits_fflags_bits_uop_imm_packed = 20'h0; // @[lsu.scala:201:7] wire [19:0] io_core_exe_0_fresp_bits_fflags_bits_uop_imm_packed = 20'h0; // @[lsu.scala:201:7] wire [19:0] _exe_req_WIRE_0_bits_fflags_bits_uop_imm_packed = 20'h0; // @[lsu.scala:383:33] wire [19:0] exe_req_0_bits_fflags_bits_uop_imm_packed = 20'h0; // @[lsu.scala:383:25] wire [19:0] exe_tlb_uop_uop_imm_packed = 20'h0; // @[consts.scala:269:19] wire [19:0] exe_tlb_uop_uop_1_imm_packed = 20'h0; // @[consts.scala:269:19] wire [19:0] _exe_tlb_uop_T_3_imm_packed = 20'h0; // @[lsu.scala:602:24] wire [19:0] dmem_req_0_bits_uop_uop_imm_packed = 20'h0; // @[consts.scala:269:19] wire [19:0] _mem_ldq_e_WIRE_bits_uop_imm_packed = 20'h0; // @[lsu.scala:918:90] wire [19:0] _mem_stq_e_WIRE_bits_uop_imm_packed = 20'h0; // @[lsu.scala:922:89] wire [19:0] lcam_uop_uop_imm_packed = 20'h0; // @[consts.scala:269:19] wire [19:0] stq_0_bits_uop_uop_imm_packed = 20'h0; // @[consts.scala:269:19] wire [19:0] stq_1_bits_uop_uop_imm_packed = 20'h0; // @[consts.scala:269:19] wire [19:0] stq_2_bits_uop_uop_imm_packed = 20'h0; // @[consts.scala:269:19] wire [19:0] stq_3_bits_uop_uop_imm_packed = 20'h0; // @[consts.scala:269:19] wire [19:0] stq_4_bits_uop_uop_imm_packed = 20'h0; // @[consts.scala:269:19] wire [19:0] stq_5_bits_uop_uop_imm_packed = 20'h0; // @[consts.scala:269:19] wire [19:0] stq_6_bits_uop_uop_imm_packed = 20'h0; // @[consts.scala:269:19] wire [19:0] stq_7_bits_uop_uop_imm_packed = 20'h0; // @[consts.scala:269:19] wire [11:0] io_core_exe_0_req_bits_fflags_bits_uop_csr_addr = 12'h0; // @[lsu.scala:201:7] wire [11:0] io_core_exe_0_iresp_bits_fflags_bits_uop_csr_addr = 12'h0; // @[lsu.scala:201:7] wire [11:0] io_core_exe_0_fresp_bits_fflags_bits_uop_csr_addr = 12'h0; // @[lsu.scala:201:7] wire [11:0] _exe_req_WIRE_0_bits_fflags_bits_uop_csr_addr = 12'h0; // @[lsu.scala:383:33] wire [11:0] exe_req_0_bits_fflags_bits_uop_csr_addr = 12'h0; // @[lsu.scala:383:25] wire [11:0] exe_tlb_uop_uop_csr_addr = 12'h0; // @[consts.scala:269:19] wire [11:0] exe_tlb_uop_uop_1_csr_addr = 12'h0; // @[consts.scala:269:19] wire [11:0] _exe_tlb_uop_T_3_csr_addr = 12'h0; // @[lsu.scala:602:24] wire [11:0] dmem_req_0_bits_uop_uop_csr_addr = 12'h0; // @[consts.scala:269:19] wire [11:0] _mem_ldq_e_WIRE_bits_uop_csr_addr = 12'h0; // @[lsu.scala:918:90] wire [11:0] _mem_stq_e_WIRE_bits_uop_csr_addr = 12'h0; // @[lsu.scala:922:89] wire [11:0] lcam_uop_uop_csr_addr = 12'h0; // @[consts.scala:269:19] wire [11:0] stq_0_bits_uop_uop_csr_addr = 12'h0; // @[consts.scala:269:19] wire [11:0] stq_1_bits_uop_uop_csr_addr = 12'h0; // @[consts.scala:269:19] wire [11:0] stq_2_bits_uop_uop_csr_addr = 12'h0; // @[consts.scala:269:19] wire [11:0] stq_3_bits_uop_uop_csr_addr = 12'h0; // @[consts.scala:269:19] wire [11:0] stq_4_bits_uop_uop_csr_addr = 12'h0; // @[consts.scala:269:19] wire [11:0] stq_5_bits_uop_uop_csr_addr = 12'h0; // @[consts.scala:269:19] wire [11:0] stq_6_bits_uop_uop_csr_addr = 12'h0; // @[consts.scala:269:19] wire [11:0] stq_7_bits_uop_uop_csr_addr = 12'h0; // @[consts.scala:269:19] wire [7:0] _lcam_mask_mask_T_11 = 8'hFF; // @[Mux.scala:126:16] wire [7:0] _l_mask_mask_T_11 = 8'hFF; // @[Mux.scala:126:16] wire [7:0] _l_mask_mask_T_26 = 8'hFF; // @[Mux.scala:126:16] wire [7:0] _l_mask_mask_T_41 = 8'hFF; // @[Mux.scala:126:16] wire [7:0] _l_mask_mask_T_56 = 8'hFF; // @[Mux.scala:126:16] wire [7:0] _l_mask_mask_T_71 = 8'hFF; // @[Mux.scala:126:16] wire [7:0] _l_mask_mask_T_86 = 8'hFF; // @[Mux.scala:126:16] wire [7:0] _l_mask_mask_T_101 = 8'hFF; // @[Mux.scala:126:16] wire [7:0] _l_mask_mask_T_116 = 8'hFF; // @[Mux.scala:126:16] wire [7:0] _write_mask_mask_T_11 = 8'hFF; // @[Mux.scala:126:16] wire [7:0] _write_mask_mask_T_26 = 8'hFF; // @[Mux.scala:126:16] wire [7:0] _write_mask_mask_T_41 = 8'hFF; // @[Mux.scala:126:16] wire [7:0] _write_mask_mask_T_56 = 8'hFF; // @[Mux.scala:126:16] wire [7:0] _write_mask_mask_T_71 = 8'hFF; // @[Mux.scala:126:16] wire [7:0] _write_mask_mask_T_86 = 8'hFF; // @[Mux.scala:126:16] wire [7:0] _write_mask_mask_T_101 = 8'hFF; // @[Mux.scala:126:16] wire [7:0] _write_mask_mask_T_116 = 8'hFF; // @[Mux.scala:126:16] wire [38:0] _exe_sfence_WIRE_bits_addr = 39'h0; // @[lsu.scala:615:43] wire _exe_req_WIRE_0_valid = io_core_exe_0_req_valid_0; // @[lsu.scala:201:7, :383:33] wire [6:0] _exe_req_WIRE_0_bits_uop_uopc = io_core_exe_0_req_bits_uop_uopc_0; // @[lsu.scala:201:7, :383:33] wire [31:0] _exe_req_WIRE_0_bits_uop_inst = io_core_exe_0_req_bits_uop_inst_0; // @[lsu.scala:201:7, :383:33] wire [31:0] _exe_req_WIRE_0_bits_uop_debug_inst = io_core_exe_0_req_bits_uop_debug_inst_0; // @[lsu.scala:201:7, :383:33] wire _exe_req_WIRE_0_bits_uop_is_rvc = io_core_exe_0_req_bits_uop_is_rvc_0; // @[lsu.scala:201:7, :383:33] wire [39:0] _exe_req_WIRE_0_bits_uop_debug_pc = io_core_exe_0_req_bits_uop_debug_pc_0; // @[lsu.scala:201:7, :383:33] wire [2:0] _exe_req_WIRE_0_bits_uop_iq_type = io_core_exe_0_req_bits_uop_iq_type_0; // @[lsu.scala:201:7, :383:33] wire [9:0] _exe_req_WIRE_0_bits_uop_fu_code = io_core_exe_0_req_bits_uop_fu_code_0; // @[lsu.scala:201:7, :383:33] wire [3:0] _exe_req_WIRE_0_bits_uop_ctrl_br_type = io_core_exe_0_req_bits_uop_ctrl_br_type_0; // @[lsu.scala:201:7, :383:33] wire [1:0] _exe_req_WIRE_0_bits_uop_ctrl_op1_sel = io_core_exe_0_req_bits_uop_ctrl_op1_sel_0; // @[lsu.scala:201:7, :383:33] wire [2:0] _exe_req_WIRE_0_bits_uop_ctrl_op2_sel = io_core_exe_0_req_bits_uop_ctrl_op2_sel_0; // @[lsu.scala:201:7, :383:33] wire [2:0] _exe_req_WIRE_0_bits_uop_ctrl_imm_sel = io_core_exe_0_req_bits_uop_ctrl_imm_sel_0; // @[lsu.scala:201:7, :383:33] wire [4:0] _exe_req_WIRE_0_bits_uop_ctrl_op_fcn = io_core_exe_0_req_bits_uop_ctrl_op_fcn_0; // @[lsu.scala:201:7, :383:33] wire _exe_req_WIRE_0_bits_uop_ctrl_fcn_dw = io_core_exe_0_req_bits_uop_ctrl_fcn_dw_0; // @[lsu.scala:201:7, :383:33] wire [2:0] _exe_req_WIRE_0_bits_uop_ctrl_csr_cmd = io_core_exe_0_req_bits_uop_ctrl_csr_cmd_0; // @[lsu.scala:201:7, :383:33] wire _exe_req_WIRE_0_bits_uop_ctrl_is_load = io_core_exe_0_req_bits_uop_ctrl_is_load_0; // @[lsu.scala:201:7, :383:33] wire _exe_req_WIRE_0_bits_uop_ctrl_is_sta = io_core_exe_0_req_bits_uop_ctrl_is_sta_0; // @[lsu.scala:201:7, :383:33] wire _exe_req_WIRE_0_bits_uop_ctrl_is_std = io_core_exe_0_req_bits_uop_ctrl_is_std_0; // @[lsu.scala:201:7, :383:33] wire [1:0] _exe_req_WIRE_0_bits_uop_iw_state = io_core_exe_0_req_bits_uop_iw_state_0; // @[lsu.scala:201:7, :383:33] wire _exe_req_WIRE_0_bits_uop_iw_p1_poisoned = io_core_exe_0_req_bits_uop_iw_p1_poisoned_0; // @[lsu.scala:201:7, :383:33] wire _exe_req_WIRE_0_bits_uop_iw_p2_poisoned = io_core_exe_0_req_bits_uop_iw_p2_poisoned_0; // @[lsu.scala:201:7, :383:33] wire _exe_req_WIRE_0_bits_uop_is_br = io_core_exe_0_req_bits_uop_is_br_0; // @[lsu.scala:201:7, :383:33] wire _exe_req_WIRE_0_bits_uop_is_jalr = io_core_exe_0_req_bits_uop_is_jalr_0; // @[lsu.scala:201:7, :383:33] wire _exe_req_WIRE_0_bits_uop_is_jal = io_core_exe_0_req_bits_uop_is_jal_0; // @[lsu.scala:201:7, :383:33] wire _exe_req_WIRE_0_bits_uop_is_sfb = io_core_exe_0_req_bits_uop_is_sfb_0; // @[lsu.scala:201:7, :383:33] wire [7:0] _exe_req_WIRE_0_bits_uop_br_mask = io_core_exe_0_req_bits_uop_br_mask_0; // @[lsu.scala:201:7, :383:33] wire [2:0] _exe_req_WIRE_0_bits_uop_br_tag = io_core_exe_0_req_bits_uop_br_tag_0; // @[lsu.scala:201:7, :383:33] wire [3:0] _exe_req_WIRE_0_bits_uop_ftq_idx = io_core_exe_0_req_bits_uop_ftq_idx_0; // @[lsu.scala:201:7, :383:33] wire _exe_req_WIRE_0_bits_uop_edge_inst = io_core_exe_0_req_bits_uop_edge_inst_0; // @[lsu.scala:201:7, :383:33] wire [5:0] _exe_req_WIRE_0_bits_uop_pc_lob = io_core_exe_0_req_bits_uop_pc_lob_0; // @[lsu.scala:201:7, :383:33] wire _exe_req_WIRE_0_bits_uop_taken = io_core_exe_0_req_bits_uop_taken_0; // @[lsu.scala:201:7, :383:33] wire [19:0] _exe_req_WIRE_0_bits_uop_imm_packed = io_core_exe_0_req_bits_uop_imm_packed_0; // @[lsu.scala:201:7, :383:33] wire [11:0] _exe_req_WIRE_0_bits_uop_csr_addr = io_core_exe_0_req_bits_uop_csr_addr_0; // @[lsu.scala:201:7, :383:33] wire [4:0] _exe_req_WIRE_0_bits_uop_rob_idx = io_core_exe_0_req_bits_uop_rob_idx_0; // @[lsu.scala:201:7, :383:33] wire [2:0] _exe_req_WIRE_0_bits_uop_ldq_idx = io_core_exe_0_req_bits_uop_ldq_idx_0; // @[lsu.scala:201:7, :383:33] wire [2:0] _exe_req_WIRE_0_bits_uop_stq_idx = io_core_exe_0_req_bits_uop_stq_idx_0; // @[lsu.scala:201:7, :383:33] wire [1:0] _exe_req_WIRE_0_bits_uop_rxq_idx = io_core_exe_0_req_bits_uop_rxq_idx_0; // @[lsu.scala:201:7, :383:33] wire [5:0] _exe_req_WIRE_0_bits_uop_pdst = io_core_exe_0_req_bits_uop_pdst_0; // @[lsu.scala:201:7, :383:33] wire [5:0] _exe_req_WIRE_0_bits_uop_prs1 = io_core_exe_0_req_bits_uop_prs1_0; // @[lsu.scala:201:7, :383:33] wire [5:0] _exe_req_WIRE_0_bits_uop_prs2 = io_core_exe_0_req_bits_uop_prs2_0; // @[lsu.scala:201:7, :383:33] wire [5:0] _exe_req_WIRE_0_bits_uop_prs3 = io_core_exe_0_req_bits_uop_prs3_0; // @[lsu.scala:201:7, :383:33] wire [3:0] _exe_req_WIRE_0_bits_uop_ppred = io_core_exe_0_req_bits_uop_ppred_0; // @[lsu.scala:201:7, :383:33] wire _exe_req_WIRE_0_bits_uop_prs1_busy = io_core_exe_0_req_bits_uop_prs1_busy_0; // @[lsu.scala:201:7, :383:33] wire _exe_req_WIRE_0_bits_uop_prs2_busy = io_core_exe_0_req_bits_uop_prs2_busy_0; // @[lsu.scala:201:7, :383:33] wire _exe_req_WIRE_0_bits_uop_prs3_busy = io_core_exe_0_req_bits_uop_prs3_busy_0; // @[lsu.scala:201:7, :383:33] wire _exe_req_WIRE_0_bits_uop_ppred_busy = io_core_exe_0_req_bits_uop_ppred_busy_0; // @[lsu.scala:201:7, :383:33] wire [5:0] _exe_req_WIRE_0_bits_uop_stale_pdst = io_core_exe_0_req_bits_uop_stale_pdst_0; // @[lsu.scala:201:7, :383:33] wire _exe_req_WIRE_0_bits_uop_exception = io_core_exe_0_req_bits_uop_exception_0; // @[lsu.scala:201:7, :383:33] wire [63:0] _exe_req_WIRE_0_bits_uop_exc_cause = io_core_exe_0_req_bits_uop_exc_cause_0; // @[lsu.scala:201:7, :383:33] wire _exe_req_WIRE_0_bits_uop_bypassable = io_core_exe_0_req_bits_uop_bypassable_0; // @[lsu.scala:201:7, :383:33] wire [4:0] _exe_req_WIRE_0_bits_uop_mem_cmd = io_core_exe_0_req_bits_uop_mem_cmd_0; // @[lsu.scala:201:7, :383:33] wire [1:0] _exe_req_WIRE_0_bits_uop_mem_size = io_core_exe_0_req_bits_uop_mem_size_0; // @[lsu.scala:201:7, :383:33] wire _exe_req_WIRE_0_bits_uop_mem_signed = io_core_exe_0_req_bits_uop_mem_signed_0; // @[lsu.scala:201:7, :383:33] wire _exe_req_WIRE_0_bits_uop_is_fence = io_core_exe_0_req_bits_uop_is_fence_0; // @[lsu.scala:201:7, :383:33] wire _exe_req_WIRE_0_bits_uop_is_fencei = io_core_exe_0_req_bits_uop_is_fencei_0; // @[lsu.scala:201:7, :383:33] wire _exe_req_WIRE_0_bits_uop_is_amo = io_core_exe_0_req_bits_uop_is_amo_0; // @[lsu.scala:201:7, :383:33] wire _exe_req_WIRE_0_bits_uop_uses_ldq = io_core_exe_0_req_bits_uop_uses_ldq_0; // @[lsu.scala:201:7, :383:33] wire _exe_req_WIRE_0_bits_uop_uses_stq = io_core_exe_0_req_bits_uop_uses_stq_0; // @[lsu.scala:201:7, :383:33] wire _exe_req_WIRE_0_bits_uop_is_sys_pc2epc = io_core_exe_0_req_bits_uop_is_sys_pc2epc_0; // @[lsu.scala:201:7, :383:33] wire _exe_req_WIRE_0_bits_uop_is_unique = io_core_exe_0_req_bits_uop_is_unique_0; // @[lsu.scala:201:7, :383:33] wire _exe_req_WIRE_0_bits_uop_flush_on_commit = io_core_exe_0_req_bits_uop_flush_on_commit_0; // @[lsu.scala:201:7, :383:33] wire _exe_req_WIRE_0_bits_uop_ldst_is_rs1 = io_core_exe_0_req_bits_uop_ldst_is_rs1_0; // @[lsu.scala:201:7, :383:33] wire [5:0] _exe_req_WIRE_0_bits_uop_ldst = io_core_exe_0_req_bits_uop_ldst_0; // @[lsu.scala:201:7, :383:33] wire [5:0] _exe_req_WIRE_0_bits_uop_lrs1 = io_core_exe_0_req_bits_uop_lrs1_0; // @[lsu.scala:201:7, :383:33] wire [5:0] _exe_req_WIRE_0_bits_uop_lrs2 = io_core_exe_0_req_bits_uop_lrs2_0; // @[lsu.scala:201:7, :383:33] wire [5:0] _exe_req_WIRE_0_bits_uop_lrs3 = io_core_exe_0_req_bits_uop_lrs3_0; // @[lsu.scala:201:7, :383:33] wire _exe_req_WIRE_0_bits_uop_ldst_val = io_core_exe_0_req_bits_uop_ldst_val_0; // @[lsu.scala:201:7, :383:33] wire [1:0] _exe_req_WIRE_0_bits_uop_dst_rtype = io_core_exe_0_req_bits_uop_dst_rtype_0; // @[lsu.scala:201:7, :383:33] wire [1:0] _exe_req_WIRE_0_bits_uop_lrs1_rtype = io_core_exe_0_req_bits_uop_lrs1_rtype_0; // @[lsu.scala:201:7, :383:33] wire [1:0] _exe_req_WIRE_0_bits_uop_lrs2_rtype = io_core_exe_0_req_bits_uop_lrs2_rtype_0; // @[lsu.scala:201:7, :383:33] wire _exe_req_WIRE_0_bits_uop_frs3_en = io_core_exe_0_req_bits_uop_frs3_en_0; // @[lsu.scala:201:7, :383:33] wire _exe_req_WIRE_0_bits_uop_fp_val = io_core_exe_0_req_bits_uop_fp_val_0; // @[lsu.scala:201:7, :383:33] wire _exe_req_WIRE_0_bits_uop_fp_single = io_core_exe_0_req_bits_uop_fp_single_0; // @[lsu.scala:201:7, :383:33] wire _exe_req_WIRE_0_bits_uop_xcpt_pf_if = io_core_exe_0_req_bits_uop_xcpt_pf_if_0; // @[lsu.scala:201:7, :383:33] wire _exe_req_WIRE_0_bits_uop_xcpt_ae_if = io_core_exe_0_req_bits_uop_xcpt_ae_if_0; // @[lsu.scala:201:7, :383:33] wire _exe_req_WIRE_0_bits_uop_xcpt_ma_if = io_core_exe_0_req_bits_uop_xcpt_ma_if_0; // @[lsu.scala:201:7, :383:33] wire _exe_req_WIRE_0_bits_uop_bp_debug_if = io_core_exe_0_req_bits_uop_bp_debug_if_0; // @[lsu.scala:201:7, :383:33] wire _exe_req_WIRE_0_bits_uop_bp_xcpt_if = io_core_exe_0_req_bits_uop_bp_xcpt_if_0; // @[lsu.scala:201:7, :383:33] wire [1:0] _exe_req_WIRE_0_bits_uop_debug_fsrc = io_core_exe_0_req_bits_uop_debug_fsrc_0; // @[lsu.scala:201:7, :383:33] wire [1:0] _exe_req_WIRE_0_bits_uop_debug_tsrc = io_core_exe_0_req_bits_uop_debug_tsrc_0; // @[lsu.scala:201:7, :383:33] wire [63:0] _exe_req_WIRE_0_bits_data = io_core_exe_0_req_bits_data_0; // @[lsu.scala:201:7, :383:33] wire [39:0] _exe_req_WIRE_0_bits_addr = io_core_exe_0_req_bits_addr_0; // @[lsu.scala:201:7, :383:33] wire _exe_req_WIRE_0_bits_mxcpt_valid = io_core_exe_0_req_bits_mxcpt_valid_0; // @[lsu.scala:201:7, :383:33] wire [24:0] _exe_req_WIRE_0_bits_mxcpt_bits = io_core_exe_0_req_bits_mxcpt_bits_0; // @[lsu.scala:201:7, :383:33] wire _exe_req_WIRE_0_bits_sfence_valid = io_core_exe_0_req_bits_sfence_valid_0; // @[lsu.scala:201:7, :383:33] wire _exe_req_WIRE_0_bits_sfence_bits_rs1 = io_core_exe_0_req_bits_sfence_bits_rs1_0; // @[lsu.scala:201:7, :383:33] wire _exe_req_WIRE_0_bits_sfence_bits_rs2 = io_core_exe_0_req_bits_sfence_bits_rs2_0; // @[lsu.scala:201:7, :383:33] wire [38:0] _exe_req_WIRE_0_bits_sfence_bits_addr = io_core_exe_0_req_bits_sfence_bits_addr_0; // @[lsu.scala:201:7, :383:33] wire _exe_req_WIRE_0_bits_sfence_bits_asid = io_core_exe_0_req_bits_sfence_bits_asid_0; // @[lsu.scala:201:7, :383:33] wire _io_core_fp_stdata_ready_T_2; // @[lsu.scala:867:61] wire [6:0] mem_stdf_uop_out_uopc = io_core_fp_stdata_bits_uop_uopc_0; // @[util.scala:96:23] wire [31:0] mem_stdf_uop_out_inst = io_core_fp_stdata_bits_uop_inst_0; // @[util.scala:96:23] wire [31:0] mem_stdf_uop_out_debug_inst = io_core_fp_stdata_bits_uop_debug_inst_0; // @[util.scala:96:23] wire mem_stdf_uop_out_is_rvc = io_core_fp_stdata_bits_uop_is_rvc_0; // @[util.scala:96:23] wire [39:0] mem_stdf_uop_out_debug_pc = io_core_fp_stdata_bits_uop_debug_pc_0; // @[util.scala:96:23] wire [2:0] mem_stdf_uop_out_iq_type = io_core_fp_stdata_bits_uop_iq_type_0; // @[util.scala:96:23] wire [9:0] mem_stdf_uop_out_fu_code = io_core_fp_stdata_bits_uop_fu_code_0; // @[util.scala:96:23] wire [3:0] mem_stdf_uop_out_ctrl_br_type = io_core_fp_stdata_bits_uop_ctrl_br_type_0; // @[util.scala:96:23] wire [1:0] mem_stdf_uop_out_ctrl_op1_sel = io_core_fp_stdata_bits_uop_ctrl_op1_sel_0; // @[util.scala:96:23] wire [2:0] mem_stdf_uop_out_ctrl_op2_sel = io_core_fp_stdata_bits_uop_ctrl_op2_sel_0; // @[util.scala:96:23] wire [2:0] mem_stdf_uop_out_ctrl_imm_sel = io_core_fp_stdata_bits_uop_ctrl_imm_sel_0; // @[util.scala:96:23] wire [4:0] mem_stdf_uop_out_ctrl_op_fcn = io_core_fp_stdata_bits_uop_ctrl_op_fcn_0; // @[util.scala:96:23] wire mem_stdf_uop_out_ctrl_fcn_dw = io_core_fp_stdata_bits_uop_ctrl_fcn_dw_0; // @[util.scala:96:23] wire [2:0] mem_stdf_uop_out_ctrl_csr_cmd = io_core_fp_stdata_bits_uop_ctrl_csr_cmd_0; // @[util.scala:96:23] wire mem_stdf_uop_out_ctrl_is_load = io_core_fp_stdata_bits_uop_ctrl_is_load_0; // @[util.scala:96:23] wire mem_stdf_uop_out_ctrl_is_sta = io_core_fp_stdata_bits_uop_ctrl_is_sta_0; // @[util.scala:96:23] wire mem_stdf_uop_out_ctrl_is_std = io_core_fp_stdata_bits_uop_ctrl_is_std_0; // @[util.scala:96:23] wire [1:0] mem_stdf_uop_out_iw_state = io_core_fp_stdata_bits_uop_iw_state_0; // @[util.scala:96:23] wire mem_stdf_uop_out_iw_p1_poisoned = io_core_fp_stdata_bits_uop_iw_p1_poisoned_0; // @[util.scala:96:23] wire mem_stdf_uop_out_iw_p2_poisoned = io_core_fp_stdata_bits_uop_iw_p2_poisoned_0; // @[util.scala:96:23] wire mem_stdf_uop_out_is_br = io_core_fp_stdata_bits_uop_is_br_0; // @[util.scala:96:23] wire mem_stdf_uop_out_is_jalr = io_core_fp_stdata_bits_uop_is_jalr_0; // @[util.scala:96:23] wire mem_stdf_uop_out_is_jal = io_core_fp_stdata_bits_uop_is_jal_0; // @[util.scala:96:23] wire mem_stdf_uop_out_is_sfb = io_core_fp_stdata_bits_uop_is_sfb_0; // @[util.scala:96:23] wire [2:0] mem_stdf_uop_out_br_tag = io_core_fp_stdata_bits_uop_br_tag_0; // @[util.scala:96:23] wire [3:0] mem_stdf_uop_out_ftq_idx = io_core_fp_stdata_bits_uop_ftq_idx_0; // @[util.scala:96:23] wire mem_stdf_uop_out_edge_inst = io_core_fp_stdata_bits_uop_edge_inst_0; // @[util.scala:96:23] wire [5:0] mem_stdf_uop_out_pc_lob = io_core_fp_stdata_bits_uop_pc_lob_0; // @[util.scala:96:23] wire mem_stdf_uop_out_taken = io_core_fp_stdata_bits_uop_taken_0; // @[util.scala:96:23] wire [19:0] mem_stdf_uop_out_imm_packed = io_core_fp_stdata_bits_uop_imm_packed_0; // @[util.scala:96:23] wire [11:0] mem_stdf_uop_out_csr_addr = io_core_fp_stdata_bits_uop_csr_addr_0; // @[util.scala:96:23] wire [4:0] mem_stdf_uop_out_rob_idx = io_core_fp_stdata_bits_uop_rob_idx_0; // @[util.scala:96:23] wire [2:0] mem_stdf_uop_out_ldq_idx = io_core_fp_stdata_bits_uop_ldq_idx_0; // @[util.scala:96:23] wire [2:0] mem_stdf_uop_out_stq_idx = io_core_fp_stdata_bits_uop_stq_idx_0; // @[util.scala:96:23] wire [1:0] mem_stdf_uop_out_rxq_idx = io_core_fp_stdata_bits_uop_rxq_idx_0; // @[util.scala:96:23] wire [5:0] mem_stdf_uop_out_pdst = io_core_fp_stdata_bits_uop_pdst_0; // @[util.scala:96:23] wire [5:0] mem_stdf_uop_out_prs1 = io_core_fp_stdata_bits_uop_prs1_0; // @[util.scala:96:23] wire [5:0] mem_stdf_uop_out_prs2 = io_core_fp_stdata_bits_uop_prs2_0; // @[util.scala:96:23] wire [5:0] mem_stdf_uop_out_prs3 = io_core_fp_stdata_bits_uop_prs3_0; // @[util.scala:96:23] wire [3:0] mem_stdf_uop_out_ppred = io_core_fp_stdata_bits_uop_ppred_0; // @[util.scala:96:23] wire mem_stdf_uop_out_prs1_busy = io_core_fp_stdata_bits_uop_prs1_busy_0; // @[util.scala:96:23] wire mem_stdf_uop_out_prs2_busy = io_core_fp_stdata_bits_uop_prs2_busy_0; // @[util.scala:96:23] wire mem_stdf_uop_out_prs3_busy = io_core_fp_stdata_bits_uop_prs3_busy_0; // @[util.scala:96:23] wire mem_stdf_uop_out_ppred_busy = io_core_fp_stdata_bits_uop_ppred_busy_0; // @[util.scala:96:23] wire [5:0] mem_stdf_uop_out_stale_pdst = io_core_fp_stdata_bits_uop_stale_pdst_0; // @[util.scala:96:23] wire mem_stdf_uop_out_exception = io_core_fp_stdata_bits_uop_exception_0; // @[util.scala:96:23] wire [63:0] mem_stdf_uop_out_exc_cause = io_core_fp_stdata_bits_uop_exc_cause_0; // @[util.scala:96:23] wire mem_stdf_uop_out_bypassable = io_core_fp_stdata_bits_uop_bypassable_0; // @[util.scala:96:23] wire [4:0] mem_stdf_uop_out_mem_cmd = io_core_fp_stdata_bits_uop_mem_cmd_0; // @[util.scala:96:23] wire [1:0] mem_stdf_uop_out_mem_size = io_core_fp_stdata_bits_uop_mem_size_0; // @[util.scala:96:23] wire mem_stdf_uop_out_mem_signed = io_core_fp_stdata_bits_uop_mem_signed_0; // @[util.scala:96:23] wire mem_stdf_uop_out_is_fence = io_core_fp_stdata_bits_uop_is_fence_0; // @[util.scala:96:23] wire mem_stdf_uop_out_is_fencei = io_core_fp_stdata_bits_uop_is_fencei_0; // @[util.scala:96:23] wire mem_stdf_uop_out_is_amo = io_core_fp_stdata_bits_uop_is_amo_0; // @[util.scala:96:23] wire mem_stdf_uop_out_uses_ldq = io_core_fp_stdata_bits_uop_uses_ldq_0; // @[util.scala:96:23] wire mem_stdf_uop_out_uses_stq = io_core_fp_stdata_bits_uop_uses_stq_0; // @[util.scala:96:23] wire mem_stdf_uop_out_is_sys_pc2epc = io_core_fp_stdata_bits_uop_is_sys_pc2epc_0; // @[util.scala:96:23] wire mem_stdf_uop_out_is_unique = io_core_fp_stdata_bits_uop_is_unique_0; // @[util.scala:96:23] wire mem_stdf_uop_out_flush_on_commit = io_core_fp_stdata_bits_uop_flush_on_commit_0; // @[util.scala:96:23] wire mem_stdf_uop_out_ldst_is_rs1 = io_core_fp_stdata_bits_uop_ldst_is_rs1_0; // @[util.scala:96:23] wire [5:0] mem_stdf_uop_out_ldst = io_core_fp_stdata_bits_uop_ldst_0; // @[util.scala:96:23] wire [5:0] mem_stdf_uop_out_lrs1 = io_core_fp_stdata_bits_uop_lrs1_0; // @[util.scala:96:23] wire [5:0] mem_stdf_uop_out_lrs2 = io_core_fp_stdata_bits_uop_lrs2_0; // @[util.scala:96:23] wire [5:0] mem_stdf_uop_out_lrs3 = io_core_fp_stdata_bits_uop_lrs3_0; // @[util.scala:96:23] wire mem_stdf_uop_out_ldst_val = io_core_fp_stdata_bits_uop_ldst_val_0; // @[util.scala:96:23] wire [1:0] mem_stdf_uop_out_dst_rtype = io_core_fp_stdata_bits_uop_dst_rtype_0; // @[util.scala:96:23] wire [1:0] mem_stdf_uop_out_lrs1_rtype = io_core_fp_stdata_bits_uop_lrs1_rtype_0; // @[util.scala:96:23] wire [1:0] mem_stdf_uop_out_lrs2_rtype = io_core_fp_stdata_bits_uop_lrs2_rtype_0; // @[util.scala:96:23] wire mem_stdf_uop_out_frs3_en = io_core_fp_stdata_bits_uop_frs3_en_0; // @[util.scala:96:23] wire mem_stdf_uop_out_fp_val = io_core_fp_stdata_bits_uop_fp_val_0; // @[util.scala:96:23] wire mem_stdf_uop_out_fp_single = io_core_fp_stdata_bits_uop_fp_single_0; // @[util.scala:96:23] wire mem_stdf_uop_out_xcpt_pf_if = io_core_fp_stdata_bits_uop_xcpt_pf_if_0; // @[util.scala:96:23] wire mem_stdf_uop_out_xcpt_ae_if = io_core_fp_stdata_bits_uop_xcpt_ae_if_0; // @[util.scala:96:23] wire mem_stdf_uop_out_xcpt_ma_if = io_core_fp_stdata_bits_uop_xcpt_ma_if_0; // @[util.scala:96:23] wire mem_stdf_uop_out_bp_debug_if = io_core_fp_stdata_bits_uop_bp_debug_if_0; // @[util.scala:96:23] wire mem_stdf_uop_out_bp_xcpt_if = io_core_fp_stdata_bits_uop_bp_xcpt_if_0; // @[util.scala:96:23] wire [1:0] mem_stdf_uop_out_debug_fsrc = io_core_fp_stdata_bits_uop_debug_fsrc_0; // @[util.scala:96:23] wire [1:0] mem_stdf_uop_out_debug_tsrc = io_core_fp_stdata_bits_uop_debug_tsrc_0; // @[util.scala:96:23] wire _io_core_clr_bsy_0_valid_T_9; // @[lsu.scala:980:82] wire _io_core_clr_bsy_1_valid_T_9; // @[lsu.scala:1005:87] wire _io_core_spec_ld_wakeup_0_valid_T_4; // @[lsu.scala:1261:69] wire [7:0] io_dmem_brupdate_b1_resolve_mask_0 = io_core_brupdate_b1_resolve_mask_0; // @[lsu.scala:201:7] wire [7:0] io_dmem_brupdate_b1_mispredict_mask_0 = io_core_brupdate_b1_mispredict_mask_0; // @[lsu.scala:201:7] wire [6:0] io_dmem_brupdate_b2_uop_uopc_0 = io_core_brupdate_b2_uop_uopc_0; // @[lsu.scala:201:7] wire [31:0] io_dmem_brupdate_b2_uop_inst_0 = io_core_brupdate_b2_uop_inst_0; // @[lsu.scala:201:7] wire [31:0] io_dmem_brupdate_b2_uop_debug_inst_0 = io_core_brupdate_b2_uop_debug_inst_0; // @[lsu.scala:201:7] wire io_dmem_brupdate_b2_uop_is_rvc_0 = io_core_brupdate_b2_uop_is_rvc_0; // @[lsu.scala:201:7] wire [39:0] io_dmem_brupdate_b2_uop_debug_pc_0 = io_core_brupdate_b2_uop_debug_pc_0; // @[lsu.scala:201:7] wire [2:0] io_dmem_brupdate_b2_uop_iq_type_0 = io_core_brupdate_b2_uop_iq_type_0; // @[lsu.scala:201:7] wire [9:0] io_dmem_brupdate_b2_uop_fu_code_0 = io_core_brupdate_b2_uop_fu_code_0; // @[lsu.scala:201:7] wire [3:0] io_dmem_brupdate_b2_uop_ctrl_br_type_0 = io_core_brupdate_b2_uop_ctrl_br_type_0; // @[lsu.scala:201:7] wire [1:0] io_dmem_brupdate_b2_uop_ctrl_op1_sel_0 = io_core_brupdate_b2_uop_ctrl_op1_sel_0; // @[lsu.scala:201:7] wire [2:0] io_dmem_brupdate_b2_uop_ctrl_op2_sel_0 = io_core_brupdate_b2_uop_ctrl_op2_sel_0; // @[lsu.scala:201:7] wire [2:0] io_dmem_brupdate_b2_uop_ctrl_imm_sel_0 = io_core_brupdate_b2_uop_ctrl_imm_sel_0; // @[lsu.scala:201:7] wire [4:0] io_dmem_brupdate_b2_uop_ctrl_op_fcn_0 = io_core_brupdate_b2_uop_ctrl_op_fcn_0; // @[lsu.scala:201:7] wire io_dmem_brupdate_b2_uop_ctrl_fcn_dw_0 = io_core_brupdate_b2_uop_ctrl_fcn_dw_0; // @[lsu.scala:201:7] wire [2:0] io_dmem_brupdate_b2_uop_ctrl_csr_cmd_0 = io_core_brupdate_b2_uop_ctrl_csr_cmd_0; // @[lsu.scala:201:7] wire io_dmem_brupdate_b2_uop_ctrl_is_load_0 = io_core_brupdate_b2_uop_ctrl_is_load_0; // @[lsu.scala:201:7] wire io_dmem_brupdate_b2_uop_ctrl_is_sta_0 = io_core_brupdate_b2_uop_ctrl_is_sta_0; // @[lsu.scala:201:7] wire io_dmem_brupdate_b2_uop_ctrl_is_std_0 = io_core_brupdate_b2_uop_ctrl_is_std_0; // @[lsu.scala:201:7] wire [1:0] io_dmem_brupdate_b2_uop_iw_state_0 = io_core_brupdate_b2_uop_iw_state_0; // @[lsu.scala:201:7] wire io_dmem_brupdate_b2_uop_iw_p1_poisoned_0 = io_core_brupdate_b2_uop_iw_p1_poisoned_0; // @[lsu.scala:201:7] wire io_dmem_brupdate_b2_uop_iw_p2_poisoned_0 = io_core_brupdate_b2_uop_iw_p2_poisoned_0; // @[lsu.scala:201:7] wire io_dmem_brupdate_b2_uop_is_br_0 = io_core_brupdate_b2_uop_is_br_0; // @[lsu.scala:201:7] wire io_dmem_brupdate_b2_uop_is_jalr_0 = io_core_brupdate_b2_uop_is_jalr_0; // @[lsu.scala:201:7] wire io_dmem_brupdate_b2_uop_is_jal_0 = io_core_brupdate_b2_uop_is_jal_0; // @[lsu.scala:201:7] wire io_dmem_brupdate_b2_uop_is_sfb_0 = io_core_brupdate_b2_uop_is_sfb_0; // @[lsu.scala:201:7] wire [7:0] io_dmem_brupdate_b2_uop_br_mask_0 = io_core_brupdate_b2_uop_br_mask_0; // @[lsu.scala:201:7] wire [2:0] io_dmem_brupdate_b2_uop_br_tag_0 = io_core_brupdate_b2_uop_br_tag_0; // @[lsu.scala:201:7] wire [3:0] io_dmem_brupdate_b2_uop_ftq_idx_0 = io_core_brupdate_b2_uop_ftq_idx_0; // @[lsu.scala:201:7] wire io_dmem_brupdate_b2_uop_edge_inst_0 = io_core_brupdate_b2_uop_edge_inst_0; // @[lsu.scala:201:7] wire [5:0] io_dmem_brupdate_b2_uop_pc_lob_0 = io_core_brupdate_b2_uop_pc_lob_0; // @[lsu.scala:201:7] wire io_dmem_brupdate_b2_uop_taken_0 = io_core_brupdate_b2_uop_taken_0; // @[lsu.scala:201:7] wire [19:0] io_dmem_brupdate_b2_uop_imm_packed_0 = io_core_brupdate_b2_uop_imm_packed_0; // @[lsu.scala:201:7] wire [11:0] io_dmem_brupdate_b2_uop_csr_addr_0 = io_core_brupdate_b2_uop_csr_addr_0; // @[lsu.scala:201:7] wire [4:0] io_dmem_brupdate_b2_uop_rob_idx_0 = io_core_brupdate_b2_uop_rob_idx_0; // @[lsu.scala:201:7] wire [2:0] io_dmem_brupdate_b2_uop_ldq_idx_0 = io_core_brupdate_b2_uop_ldq_idx_0; // @[lsu.scala:201:7] wire [2:0] io_dmem_brupdate_b2_uop_stq_idx_0 = io_core_brupdate_b2_uop_stq_idx_0; // @[lsu.scala:201:7] wire [1:0] io_dmem_brupdate_b2_uop_rxq_idx_0 = io_core_brupdate_b2_uop_rxq_idx_0; // @[lsu.scala:201:7] wire [5:0] io_dmem_brupdate_b2_uop_pdst_0 = io_core_brupdate_b2_uop_pdst_0; // @[lsu.scala:201:7] wire [5:0] io_dmem_brupdate_b2_uop_prs1_0 = io_core_brupdate_b2_uop_prs1_0; // @[lsu.scala:201:7] wire [5:0] io_dmem_brupdate_b2_uop_prs2_0 = io_core_brupdate_b2_uop_prs2_0; // @[lsu.scala:201:7] wire [5:0] io_dmem_brupdate_b2_uop_prs3_0 = io_core_brupdate_b2_uop_prs3_0; // @[lsu.scala:201:7] wire [3:0] io_dmem_brupdate_b2_uop_ppred_0 = io_core_brupdate_b2_uop_ppred_0; // @[lsu.scala:201:7] wire io_dmem_brupdate_b2_uop_prs1_busy_0 = io_core_brupdate_b2_uop_prs1_busy_0; // @[lsu.scala:201:7] wire io_dmem_brupdate_b2_uop_prs2_busy_0 = io_core_brupdate_b2_uop_prs2_busy_0; // @[lsu.scala:201:7] wire io_dmem_brupdate_b2_uop_prs3_busy_0 = io_core_brupdate_b2_uop_prs3_busy_0; // @[lsu.scala:201:7] wire io_dmem_brupdate_b2_uop_ppred_busy_0 = io_core_brupdate_b2_uop_ppred_busy_0; // @[lsu.scala:201:7] wire [5:0] io_dmem_brupdate_b2_uop_stale_pdst_0 = io_core_brupdate_b2_uop_stale_pdst_0; // @[lsu.scala:201:7] wire io_dmem_brupdate_b2_uop_exception_0 = io_core_brupdate_b2_uop_exception_0; // @[lsu.scala:201:7] wire [63:0] io_dmem_brupdate_b2_uop_exc_cause_0 = io_core_brupdate_b2_uop_exc_cause_0; // @[lsu.scala:201:7] wire io_dmem_brupdate_b2_uop_bypassable_0 = io_core_brupdate_b2_uop_bypassable_0; // @[lsu.scala:201:7] wire [4:0] io_dmem_brupdate_b2_uop_mem_cmd_0 = io_core_brupdate_b2_uop_mem_cmd_0; // @[lsu.scala:201:7] wire [1:0] io_dmem_brupdate_b2_uop_mem_size_0 = io_core_brupdate_b2_uop_mem_size_0; // @[lsu.scala:201:7] wire io_dmem_brupdate_b2_uop_mem_signed_0 = io_core_brupdate_b2_uop_mem_signed_0; // @[lsu.scala:201:7] wire io_dmem_brupdate_b2_uop_is_fence_0 = io_core_brupdate_b2_uop_is_fence_0; // @[lsu.scala:201:7] wire io_dmem_brupdate_b2_uop_is_fencei_0 = io_core_brupdate_b2_uop_is_fencei_0; // @[lsu.scala:201:7] wire io_dmem_brupdate_b2_uop_is_amo_0 = io_core_brupdate_b2_uop_is_amo_0; // @[lsu.scala:201:7] wire io_dmem_brupdate_b2_uop_uses_ldq_0 = io_core_brupdate_b2_uop_uses_ldq_0; // @[lsu.scala:201:7] wire io_dmem_brupdate_b2_uop_uses_stq_0 = io_core_brupdate_b2_uop_uses_stq_0; // @[lsu.scala:201:7] wire io_dmem_brupdate_b2_uop_is_sys_pc2epc_0 = io_core_brupdate_b2_uop_is_sys_pc2epc_0; // @[lsu.scala:201:7] wire io_dmem_brupdate_b2_uop_is_unique_0 = io_core_brupdate_b2_uop_is_unique_0; // @[lsu.scala:201:7] wire io_dmem_brupdate_b2_uop_flush_on_commit_0 = io_core_brupdate_b2_uop_flush_on_commit_0; // @[lsu.scala:201:7] wire io_dmem_brupdate_b2_uop_ldst_is_rs1_0 = io_core_brupdate_b2_uop_ldst_is_rs1_0; // @[lsu.scala:201:7] wire [5:0] io_dmem_brupdate_b2_uop_ldst_0 = io_core_brupdate_b2_uop_ldst_0; // @[lsu.scala:201:7] wire [5:0] io_dmem_brupdate_b2_uop_lrs1_0 = io_core_brupdate_b2_uop_lrs1_0; // @[lsu.scala:201:7] wire [5:0] io_dmem_brupdate_b2_uop_lrs2_0 = io_core_brupdate_b2_uop_lrs2_0; // @[lsu.scala:201:7] wire [5:0] io_dmem_brupdate_b2_uop_lrs3_0 = io_core_brupdate_b2_uop_lrs3_0; // @[lsu.scala:201:7] wire io_dmem_brupdate_b2_uop_ldst_val_0 = io_core_brupdate_b2_uop_ldst_val_0; // @[lsu.scala:201:7] wire [1:0] io_dmem_brupdate_b2_uop_dst_rtype_0 = io_core_brupdate_b2_uop_dst_rtype_0; // @[lsu.scala:201:7] wire [1:0] io_dmem_brupdate_b2_uop_lrs1_rtype_0 = io_core_brupdate_b2_uop_lrs1_rtype_0; // @[lsu.scala:201:7] wire [1:0] io_dmem_brupdate_b2_uop_lrs2_rtype_0 = io_core_brupdate_b2_uop_lrs2_rtype_0; // @[lsu.scala:201:7] wire io_dmem_brupdate_b2_uop_frs3_en_0 = io_core_brupdate_b2_uop_frs3_en_0; // @[lsu.scala:201:7] wire io_dmem_brupdate_b2_uop_fp_val_0 = io_core_brupdate_b2_uop_fp_val_0; // @[lsu.scala:201:7] wire io_dmem_brupdate_b2_uop_fp_single_0 = io_core_brupdate_b2_uop_fp_single_0; // @[lsu.scala:201:7] wire io_dmem_brupdate_b2_uop_xcpt_pf_if_0 = io_core_brupdate_b2_uop_xcpt_pf_if_0; // @[lsu.scala:201:7] wire io_dmem_brupdate_b2_uop_xcpt_ae_if_0 = io_core_brupdate_b2_uop_xcpt_ae_if_0; // @[lsu.scala:201:7] wire io_dmem_brupdate_b2_uop_xcpt_ma_if_0 = io_core_brupdate_b2_uop_xcpt_ma_if_0; // @[lsu.scala:201:7] wire io_dmem_brupdate_b2_uop_bp_debug_if_0 = io_core_brupdate_b2_uop_bp_debug_if_0; // @[lsu.scala:201:7] wire io_dmem_brupdate_b2_uop_bp_xcpt_if_0 = io_core_brupdate_b2_uop_bp_xcpt_if_0; // @[lsu.scala:201:7] wire [1:0] io_dmem_brupdate_b2_uop_debug_fsrc_0 = io_core_brupdate_b2_uop_debug_fsrc_0; // @[lsu.scala:201:7] wire [1:0] io_dmem_brupdate_b2_uop_debug_tsrc_0 = io_core_brupdate_b2_uop_debug_tsrc_0; // @[lsu.scala:201:7] wire io_dmem_brupdate_b2_valid_0 = io_core_brupdate_b2_valid_0; // @[lsu.scala:201:7] wire io_dmem_brupdate_b2_mispredict_0 = io_core_brupdate_b2_mispredict_0; // @[lsu.scala:201:7] wire io_dmem_brupdate_b2_taken_0 = io_core_brupdate_b2_taken_0; // @[lsu.scala:201:7] wire [2:0] io_dmem_brupdate_b2_cfi_type_0 = io_core_brupdate_b2_cfi_type_0; // @[lsu.scala:201:7] wire [1:0] io_dmem_brupdate_b2_pc_sel_0 = io_core_brupdate_b2_pc_sel_0; // @[lsu.scala:201:7] wire [39:0] io_dmem_brupdate_b2_jalr_target_0 = io_core_brupdate_b2_jalr_target_0; // @[lsu.scala:201:7] wire [20:0] io_dmem_brupdate_b2_target_offset_0 = io_core_brupdate_b2_target_offset_0; // @[lsu.scala:201:7] wire [4:0] io_dmem_rob_pnr_idx_0 = io_core_rob_pnr_idx_0; // @[lsu.scala:201:7] wire [4:0] io_dmem_rob_head_idx_0 = io_core_rob_head_idx_0; // @[lsu.scala:201:7] wire io_dmem_exception_0 = io_core_exception_0; // @[lsu.scala:201:7] wire _io_core_fencei_rdy_T_1; // @[lsu.scala:347:42] wire _io_core_lxcpt_valid_T_5; // @[lsu.scala:1254:61] wire _io_core_perf_tlbMiss_T; // @[Decoupled.scala:51:35] wire dmem_req_0_valid; // @[lsu.scala:750:22] wire [6:0] dmem_req_0_bits_uop_uopc; // @[lsu.scala:750:22] wire [31:0] dmem_req_0_bits_uop_inst; // @[lsu.scala:750:22] wire [31:0] dmem_req_0_bits_uop_debug_inst; // @[lsu.scala:750:22] wire dmem_req_0_bits_uop_is_rvc; // @[lsu.scala:750:22] wire [39:0] dmem_req_0_bits_uop_debug_pc; // @[lsu.scala:750:22] wire [2:0] dmem_req_0_bits_uop_iq_type; // @[lsu.scala:750:22] wire [9:0] dmem_req_0_bits_uop_fu_code; // @[lsu.scala:750:22] wire [3:0] dmem_req_0_bits_uop_ctrl_br_type; // @[lsu.scala:750:22] wire [1:0] dmem_req_0_bits_uop_ctrl_op1_sel; // @[lsu.scala:750:22] wire [2:0] dmem_req_0_bits_uop_ctrl_op2_sel; // @[lsu.scala:750:22] wire [2:0] dmem_req_0_bits_uop_ctrl_imm_sel; // @[lsu.scala:750:22] wire [4:0] dmem_req_0_bits_uop_ctrl_op_fcn; // @[lsu.scala:750:22] wire dmem_req_0_bits_uop_ctrl_fcn_dw; // @[lsu.scala:750:22] wire [2:0] dmem_req_0_bits_uop_ctrl_csr_cmd; // @[lsu.scala:750:22] wire dmem_req_0_bits_uop_ctrl_is_load; // @[lsu.scala:750:22] wire dmem_req_0_bits_uop_ctrl_is_sta; // @[lsu.scala:750:22] wire dmem_req_0_bits_uop_ctrl_is_std; // @[lsu.scala:750:22] wire [1:0] dmem_req_0_bits_uop_iw_state; // @[lsu.scala:750:22] wire dmem_req_0_bits_uop_iw_p1_poisoned; // @[lsu.scala:750:22] wire dmem_req_0_bits_uop_iw_p2_poisoned; // @[lsu.scala:750:22] wire dmem_req_0_bits_uop_is_br; // @[lsu.scala:750:22] wire dmem_req_0_bits_uop_is_jalr; // @[lsu.scala:750:22] wire dmem_req_0_bits_uop_is_jal; // @[lsu.scala:750:22] wire dmem_req_0_bits_uop_is_sfb; // @[lsu.scala:750:22] wire [7:0] dmem_req_0_bits_uop_br_mask; // @[lsu.scala:750:22] wire [2:0] dmem_req_0_bits_uop_br_tag; // @[lsu.scala:750:22] wire [3:0] dmem_req_0_bits_uop_ftq_idx; // @[lsu.scala:750:22] wire dmem_req_0_bits_uop_edge_inst; // @[lsu.scala:750:22] wire [5:0] dmem_req_0_bits_uop_pc_lob; // @[lsu.scala:750:22] wire dmem_req_0_bits_uop_taken; // @[lsu.scala:750:22] wire [19:0] dmem_req_0_bits_uop_imm_packed; // @[lsu.scala:750:22] wire [11:0] dmem_req_0_bits_uop_csr_addr; // @[lsu.scala:750:22] wire [4:0] dmem_req_0_bits_uop_rob_idx; // @[lsu.scala:750:22] wire [2:0] dmem_req_0_bits_uop_ldq_idx; // @[lsu.scala:750:22] wire [2:0] dmem_req_0_bits_uop_stq_idx; // @[lsu.scala:750:22] wire [1:0] dmem_req_0_bits_uop_rxq_idx; // @[lsu.scala:750:22] wire [5:0] dmem_req_0_bits_uop_pdst; // @[lsu.scala:750:22] wire [5:0] dmem_req_0_bits_uop_prs1; // @[lsu.scala:750:22] wire [5:0] dmem_req_0_bits_uop_prs2; // @[lsu.scala:750:22] wire [5:0] dmem_req_0_bits_uop_prs3; // @[lsu.scala:750:22] wire [3:0] dmem_req_0_bits_uop_ppred; // @[lsu.scala:750:22] wire dmem_req_0_bits_uop_prs1_busy; // @[lsu.scala:750:22] wire dmem_req_0_bits_uop_prs2_busy; // @[lsu.scala:750:22] wire dmem_req_0_bits_uop_prs3_busy; // @[lsu.scala:750:22] wire dmem_req_0_bits_uop_ppred_busy; // @[lsu.scala:750:22] wire [5:0] dmem_req_0_bits_uop_stale_pdst; // @[lsu.scala:750:22] wire dmem_req_0_bits_uop_exception; // @[lsu.scala:750:22] wire [63:0] dmem_req_0_bits_uop_exc_cause; // @[lsu.scala:750:22] wire dmem_req_0_bits_uop_bypassable; // @[lsu.scala:750:22] wire [4:0] dmem_req_0_bits_uop_mem_cmd; // @[lsu.scala:750:22] wire [1:0] dmem_req_0_bits_uop_mem_size; // @[lsu.scala:750:22] wire dmem_req_0_bits_uop_mem_signed; // @[lsu.scala:750:22] wire dmem_req_0_bits_uop_is_fence; // @[lsu.scala:750:22] wire dmem_req_0_bits_uop_is_fencei; // @[lsu.scala:750:22] wire dmem_req_0_bits_uop_is_amo; // @[lsu.scala:750:22] wire dmem_req_0_bits_uop_uses_ldq; // @[lsu.scala:750:22] wire dmem_req_0_bits_uop_uses_stq; // @[lsu.scala:750:22] wire dmem_req_0_bits_uop_is_sys_pc2epc; // @[lsu.scala:750:22] wire dmem_req_0_bits_uop_is_unique; // @[lsu.scala:750:22] wire dmem_req_0_bits_uop_flush_on_commit; // @[lsu.scala:750:22] wire dmem_req_0_bits_uop_ldst_is_rs1; // @[lsu.scala:750:22] wire [5:0] dmem_req_0_bits_uop_ldst; // @[lsu.scala:750:22] wire [5:0] dmem_req_0_bits_uop_lrs1; // @[lsu.scala:750:22] wire [5:0] dmem_req_0_bits_uop_lrs2; // @[lsu.scala:750:22] wire [5:0] dmem_req_0_bits_uop_lrs3; // @[lsu.scala:750:22] wire dmem_req_0_bits_uop_ldst_val; // @[lsu.scala:750:22] wire [1:0] dmem_req_0_bits_uop_dst_rtype; // @[lsu.scala:750:22] wire [1:0] dmem_req_0_bits_uop_lrs1_rtype; // @[lsu.scala:750:22] wire [1:0] dmem_req_0_bits_uop_lrs2_rtype; // @[lsu.scala:750:22] wire dmem_req_0_bits_uop_frs3_en; // @[lsu.scala:750:22] wire dmem_req_0_bits_uop_fp_val; // @[lsu.scala:750:22] wire dmem_req_0_bits_uop_fp_single; // @[lsu.scala:750:22] wire dmem_req_0_bits_uop_xcpt_pf_if; // @[lsu.scala:750:22] wire dmem_req_0_bits_uop_xcpt_ae_if; // @[lsu.scala:750:22] wire dmem_req_0_bits_uop_xcpt_ma_if; // @[lsu.scala:750:22] wire dmem_req_0_bits_uop_bp_debug_if; // @[lsu.scala:750:22] wire dmem_req_0_bits_uop_bp_xcpt_if; // @[lsu.scala:750:22] wire [1:0] dmem_req_0_bits_uop_debug_fsrc; // @[lsu.scala:750:22] wire [1:0] dmem_req_0_bits_uop_debug_tsrc; // @[lsu.scala:750:22] wire [39:0] dmem_req_0_bits_addr; // @[lsu.scala:750:22] wire [63:0] dmem_req_0_bits_data; // @[lsu.scala:750:22] wire dmem_req_0_bits_is_hella; // @[lsu.scala:750:22] wire [63:0] io_hellacache_resp_bits_data_0 = io_dmem_resp_0_bits_data_0; // @[lsu.scala:201:7] wire will_fire_release_0; // @[lsu.scala:377:38] wire _can_fire_release_T = io_dmem_release_valid_0; // @[lsu.scala:201:7, :459:66] wire io_core_perf_acquire_0 = io_dmem_perf_acquire_0; // @[lsu.scala:201:7] wire io_core_perf_release_0 = io_dmem_perf_release_0; // @[lsu.scala:201:7] wire _io_hellacache_store_pending_T_6; // @[lsu.scala:1530:59] wire [26:0] io_ptw_req_bits_bits_addr_0; // @[lsu.scala:201:7] wire io_ptw_req_bits_valid_0; // @[lsu.scala:201:7] wire io_ptw_req_valid_0; // @[lsu.scala:201:7] wire [3:0] io_core_exe_0_iresp_bits_uop_ctrl_br_type_0; // @[lsu.scala:201:7] wire [1:0] io_core_exe_0_iresp_bits_uop_ctrl_op1_sel_0; // @[lsu.scala:201:7] wire [2:0] io_core_exe_0_iresp_bits_uop_ctrl_op2_sel_0; // @[lsu.scala:201:7] wire [2:0] io_core_exe_0_iresp_bits_uop_ctrl_imm_sel_0; // @[lsu.scala:201:7] wire [4:0] io_core_exe_0_iresp_bits_uop_ctrl_op_fcn_0; // @[lsu.scala:201:7] wire io_core_exe_0_iresp_bits_uop_ctrl_fcn_dw_0; // @[lsu.scala:201:7] wire [2:0] io_core_exe_0_iresp_bits_uop_ctrl_csr_cmd_0; // @[lsu.scala:201:7] wire io_core_exe_0_iresp_bits_uop_ctrl_is_load_0; // @[lsu.scala:201:7] wire io_core_exe_0_iresp_bits_uop_ctrl_is_sta_0; // @[lsu.scala:201:7] wire io_core_exe_0_iresp_bits_uop_ctrl_is_std_0; // @[lsu.scala:201:7] wire [6:0] io_core_exe_0_iresp_bits_uop_uopc_0; // @[lsu.scala:201:7] wire [31:0] io_core_exe_0_iresp_bits_uop_inst_0; // @[lsu.scala:201:7] wire [31:0] io_core_exe_0_iresp_bits_uop_debug_inst_0; // @[lsu.scala:201:7] wire io_core_exe_0_iresp_bits_uop_is_rvc_0; // @[lsu.scala:201:7] wire [39:0] io_core_exe_0_iresp_bits_uop_debug_pc_0; // @[lsu.scala:201:7] wire [2:0] io_core_exe_0_iresp_bits_uop_iq_type_0; // @[lsu.scala:201:7] wire [9:0] io_core_exe_0_iresp_bits_uop_fu_code_0; // @[lsu.scala:201:7] wire [1:0] io_core_exe_0_iresp_bits_uop_iw_state_0; // @[lsu.scala:201:7] wire io_core_exe_0_iresp_bits_uop_iw_p1_poisoned_0; // @[lsu.scala:201:7] wire io_core_exe_0_iresp_bits_uop_iw_p2_poisoned_0; // @[lsu.scala:201:7] wire io_core_exe_0_iresp_bits_uop_is_br_0; // @[lsu.scala:201:7] wire io_core_exe_0_iresp_bits_uop_is_jalr_0; // @[lsu.scala:201:7] wire io_core_exe_0_iresp_bits_uop_is_jal_0; // @[lsu.scala:201:7] wire io_core_exe_0_iresp_bits_uop_is_sfb_0; // @[lsu.scala:201:7] wire [7:0] io_core_exe_0_iresp_bits_uop_br_mask_0; // @[lsu.scala:201:7] wire [2:0] io_core_exe_0_iresp_bits_uop_br_tag_0; // @[lsu.scala:201:7] wire [3:0] io_core_exe_0_iresp_bits_uop_ftq_idx_0; // @[lsu.scala:201:7] wire io_core_exe_0_iresp_bits_uop_edge_inst_0; // @[lsu.scala:201:7] wire [5:0] io_core_exe_0_iresp_bits_uop_pc_lob_0; // @[lsu.scala:201:7] wire io_core_exe_0_iresp_bits_uop_taken_0; // @[lsu.scala:201:7] wire [19:0] io_core_exe_0_iresp_bits_uop_imm_packed_0; // @[lsu.scala:201:7] wire [11:0] io_core_exe_0_iresp_bits_uop_csr_addr_0; // @[lsu.scala:201:7] wire [4:0] io_core_exe_0_iresp_bits_uop_rob_idx_0; // @[lsu.scala:201:7] wire [2:0] io_core_exe_0_iresp_bits_uop_ldq_idx_0; // @[lsu.scala:201:7] wire [2:0] io_core_exe_0_iresp_bits_uop_stq_idx_0; // @[lsu.scala:201:7] wire [1:0] io_core_exe_0_iresp_bits_uop_rxq_idx_0; // @[lsu.scala:201:7] wire [5:0] io_core_exe_0_iresp_bits_uop_pdst_0; // @[lsu.scala:201:7] wire [5:0] io_core_exe_0_iresp_bits_uop_prs1_0; // @[lsu.scala:201:7] wire [5:0] io_core_exe_0_iresp_bits_uop_prs2_0; // @[lsu.scala:201:7] wire [5:0] io_core_exe_0_iresp_bits_uop_prs3_0; // @[lsu.scala:201:7] wire [3:0] io_core_exe_0_iresp_bits_uop_ppred_0; // @[lsu.scala:201:7] wire io_core_exe_0_iresp_bits_uop_prs1_busy_0; // @[lsu.scala:201:7] wire io_core_exe_0_iresp_bits_uop_prs2_busy_0; // @[lsu.scala:201:7] wire io_core_exe_0_iresp_bits_uop_prs3_busy_0; // @[lsu.scala:201:7] wire io_core_exe_0_iresp_bits_uop_ppred_busy_0; // @[lsu.scala:201:7] wire [5:0] io_core_exe_0_iresp_bits_uop_stale_pdst_0; // @[lsu.scala:201:7] wire io_core_exe_0_iresp_bits_uop_exception_0; // @[lsu.scala:201:7] wire [63:0] io_core_exe_0_iresp_bits_uop_exc_cause_0; // @[lsu.scala:201:7] wire io_core_exe_0_iresp_bits_uop_bypassable_0; // @[lsu.scala:201:7] wire [4:0] io_core_exe_0_iresp_bits_uop_mem_cmd_0; // @[lsu.scala:201:7] wire [1:0] io_core_exe_0_iresp_bits_uop_mem_size_0; // @[lsu.scala:201:7] wire io_core_exe_0_iresp_bits_uop_mem_signed_0; // @[lsu.scala:201:7] wire io_core_exe_0_iresp_bits_uop_is_fence_0; // @[lsu.scala:201:7] wire io_core_exe_0_iresp_bits_uop_is_fencei_0; // @[lsu.scala:201:7] wire io_core_exe_0_iresp_bits_uop_is_amo_0; // @[lsu.scala:201:7] wire io_core_exe_0_iresp_bits_uop_uses_ldq_0; // @[lsu.scala:201:7] wire io_core_exe_0_iresp_bits_uop_uses_stq_0; // @[lsu.scala:201:7] wire io_core_exe_0_iresp_bits_uop_is_sys_pc2epc_0; // @[lsu.scala:201:7] wire io_core_exe_0_iresp_bits_uop_is_unique_0; // @[lsu.scala:201:7] wire io_core_exe_0_iresp_bits_uop_flush_on_commit_0; // @[lsu.scala:201:7] wire io_core_exe_0_iresp_bits_uop_ldst_is_rs1_0; // @[lsu.scala:201:7] wire [5:0] io_core_exe_0_iresp_bits_uop_ldst_0; // @[lsu.scala:201:7] wire [5:0] io_core_exe_0_iresp_bits_uop_lrs1_0; // @[lsu.scala:201:7] wire [5:0] io_core_exe_0_iresp_bits_uop_lrs2_0; // @[lsu.scala:201:7] wire [5:0] io_core_exe_0_iresp_bits_uop_lrs3_0; // @[lsu.scala:201:7] wire io_core_exe_0_iresp_bits_uop_ldst_val_0; // @[lsu.scala:201:7] wire [1:0] io_core_exe_0_iresp_bits_uop_dst_rtype_0; // @[lsu.scala:201:7] wire [1:0] io_core_exe_0_iresp_bits_uop_lrs1_rtype_0; // @[lsu.scala:201:7] wire [1:0] io_core_exe_0_iresp_bits_uop_lrs2_rtype_0; // @[lsu.scala:201:7] wire io_core_exe_0_iresp_bits_uop_frs3_en_0; // @[lsu.scala:201:7] wire io_core_exe_0_iresp_bits_uop_fp_val_0; // @[lsu.scala:201:7] wire io_core_exe_0_iresp_bits_uop_fp_single_0; // @[lsu.scala:201:7] wire io_core_exe_0_iresp_bits_uop_xcpt_pf_if_0; // @[lsu.scala:201:7] wire io_core_exe_0_iresp_bits_uop_xcpt_ae_if_0; // @[lsu.scala:201:7] wire io_core_exe_0_iresp_bits_uop_xcpt_ma_if_0; // @[lsu.scala:201:7] wire io_core_exe_0_iresp_bits_uop_bp_debug_if_0; // @[lsu.scala:201:7] wire io_core_exe_0_iresp_bits_uop_bp_xcpt_if_0; // @[lsu.scala:201:7] wire [1:0] io_core_exe_0_iresp_bits_uop_debug_fsrc_0; // @[lsu.scala:201:7] wire [1:0] io_core_exe_0_iresp_bits_uop_debug_tsrc_0; // @[lsu.scala:201:7] wire [63:0] io_core_exe_0_iresp_bits_data_0; // @[lsu.scala:201:7] wire io_core_exe_0_iresp_valid_0; // @[lsu.scala:201:7] wire [3:0] io_core_exe_0_fresp_bits_uop_ctrl_br_type_0; // @[lsu.scala:201:7] wire [1:0] io_core_exe_0_fresp_bits_uop_ctrl_op1_sel_0; // @[lsu.scala:201:7] wire [2:0] io_core_exe_0_fresp_bits_uop_ctrl_op2_sel_0; // @[lsu.scala:201:7] wire [2:0] io_core_exe_0_fresp_bits_uop_ctrl_imm_sel_0; // @[lsu.scala:201:7] wire [4:0] io_core_exe_0_fresp_bits_uop_ctrl_op_fcn_0; // @[lsu.scala:201:7] wire io_core_exe_0_fresp_bits_uop_ctrl_fcn_dw_0; // @[lsu.scala:201:7] wire [2:0] io_core_exe_0_fresp_bits_uop_ctrl_csr_cmd_0; // @[lsu.scala:201:7] wire io_core_exe_0_fresp_bits_uop_ctrl_is_load_0; // @[lsu.scala:201:7] wire io_core_exe_0_fresp_bits_uop_ctrl_is_sta_0; // @[lsu.scala:201:7] wire io_core_exe_0_fresp_bits_uop_ctrl_is_std_0; // @[lsu.scala:201:7] wire [6:0] io_core_exe_0_fresp_bits_uop_uopc_0; // @[lsu.scala:201:7] wire [31:0] io_core_exe_0_fresp_bits_uop_inst_0; // @[lsu.scala:201:7] wire [31:0] io_core_exe_0_fresp_bits_uop_debug_inst_0; // @[lsu.scala:201:7] wire io_core_exe_0_fresp_bits_uop_is_rvc_0; // @[lsu.scala:201:7] wire [39:0] io_core_exe_0_fresp_bits_uop_debug_pc_0; // @[lsu.scala:201:7] wire [2:0] io_core_exe_0_fresp_bits_uop_iq_type_0; // @[lsu.scala:201:7] wire [9:0] io_core_exe_0_fresp_bits_uop_fu_code_0; // @[lsu.scala:201:7] wire [1:0] io_core_exe_0_fresp_bits_uop_iw_state_0; // @[lsu.scala:201:7] wire io_core_exe_0_fresp_bits_uop_iw_p1_poisoned_0; // @[lsu.scala:201:7] wire io_core_exe_0_fresp_bits_uop_iw_p2_poisoned_0; // @[lsu.scala:201:7] wire io_core_exe_0_fresp_bits_uop_is_br_0; // @[lsu.scala:201:7] wire io_core_exe_0_fresp_bits_uop_is_jalr_0; // @[lsu.scala:201:7] wire io_core_exe_0_fresp_bits_uop_is_jal_0; // @[lsu.scala:201:7] wire io_core_exe_0_fresp_bits_uop_is_sfb_0; // @[lsu.scala:201:7] wire [7:0] io_core_exe_0_fresp_bits_uop_br_mask_0; // @[lsu.scala:201:7] wire [2:0] io_core_exe_0_fresp_bits_uop_br_tag_0; // @[lsu.scala:201:7] wire [3:0] io_core_exe_0_fresp_bits_uop_ftq_idx_0; // @[lsu.scala:201:7] wire io_core_exe_0_fresp_bits_uop_edge_inst_0; // @[lsu.scala:201:7] wire [5:0] io_core_exe_0_fresp_bits_uop_pc_lob_0; // @[lsu.scala:201:7] wire io_core_exe_0_fresp_bits_uop_taken_0; // @[lsu.scala:201:7] wire [19:0] io_core_exe_0_fresp_bits_uop_imm_packed_0; // @[lsu.scala:201:7] wire [11:0] io_core_exe_0_fresp_bits_uop_csr_addr_0; // @[lsu.scala:201:7] wire [4:0] io_core_exe_0_fresp_bits_uop_rob_idx_0; // @[lsu.scala:201:7] wire [2:0] io_core_exe_0_fresp_bits_uop_ldq_idx_0; // @[lsu.scala:201:7] wire [2:0] io_core_exe_0_fresp_bits_uop_stq_idx_0; // @[lsu.scala:201:7] wire [1:0] io_core_exe_0_fresp_bits_uop_rxq_idx_0; // @[lsu.scala:201:7] wire [5:0] io_core_exe_0_fresp_bits_uop_pdst_0; // @[lsu.scala:201:7] wire [5:0] io_core_exe_0_fresp_bits_uop_prs1_0; // @[lsu.scala:201:7] wire [5:0] io_core_exe_0_fresp_bits_uop_prs2_0; // @[lsu.scala:201:7] wire [5:0] io_core_exe_0_fresp_bits_uop_prs3_0; // @[lsu.scala:201:7] wire io_core_exe_0_fresp_bits_uop_prs1_busy_0; // @[lsu.scala:201:7] wire io_core_exe_0_fresp_bits_uop_prs2_busy_0; // @[lsu.scala:201:7] wire io_core_exe_0_fresp_bits_uop_prs3_busy_0; // @[lsu.scala:201:7] wire [5:0] io_core_exe_0_fresp_bits_uop_stale_pdst_0; // @[lsu.scala:201:7] wire io_core_exe_0_fresp_bits_uop_exception_0; // @[lsu.scala:201:7] wire [63:0] io_core_exe_0_fresp_bits_uop_exc_cause_0; // @[lsu.scala:201:7] wire io_core_exe_0_fresp_bits_uop_bypassable_0; // @[lsu.scala:201:7] wire [4:0] io_core_exe_0_fresp_bits_uop_mem_cmd_0; // @[lsu.scala:201:7] wire [1:0] io_core_exe_0_fresp_bits_uop_mem_size_0; // @[lsu.scala:201:7] wire io_core_exe_0_fresp_bits_uop_mem_signed_0; // @[lsu.scala:201:7] wire io_core_exe_0_fresp_bits_uop_is_fence_0; // @[lsu.scala:201:7] wire io_core_exe_0_fresp_bits_uop_is_fencei_0; // @[lsu.scala:201:7] wire io_core_exe_0_fresp_bits_uop_is_amo_0; // @[lsu.scala:201:7] wire io_core_exe_0_fresp_bits_uop_uses_ldq_0; // @[lsu.scala:201:7] wire io_core_exe_0_fresp_bits_uop_uses_stq_0; // @[lsu.scala:201:7] wire io_core_exe_0_fresp_bits_uop_is_sys_pc2epc_0; // @[lsu.scala:201:7] wire io_core_exe_0_fresp_bits_uop_is_unique_0; // @[lsu.scala:201:7] wire io_core_exe_0_fresp_bits_uop_flush_on_commit_0; // @[lsu.scala:201:7] wire io_core_exe_0_fresp_bits_uop_ldst_is_rs1_0; // @[lsu.scala:201:7] wire [5:0] io_core_exe_0_fresp_bits_uop_ldst_0; // @[lsu.scala:201:7] wire [5:0] io_core_exe_0_fresp_bits_uop_lrs1_0; // @[lsu.scala:201:7] wire [5:0] io_core_exe_0_fresp_bits_uop_lrs2_0; // @[lsu.scala:201:7] wire [5:0] io_core_exe_0_fresp_bits_uop_lrs3_0; // @[lsu.scala:201:7] wire io_core_exe_0_fresp_bits_uop_ldst_val_0; // @[lsu.scala:201:7] wire [1:0] io_core_exe_0_fresp_bits_uop_dst_rtype_0; // @[lsu.scala:201:7] wire [1:0] io_core_exe_0_fresp_bits_uop_lrs1_rtype_0; // @[lsu.scala:201:7] wire [1:0] io_core_exe_0_fresp_bits_uop_lrs2_rtype_0; // @[lsu.scala:201:7] wire io_core_exe_0_fresp_bits_uop_frs3_en_0; // @[lsu.scala:201:7] wire io_core_exe_0_fresp_bits_uop_fp_val_0; // @[lsu.scala:201:7] wire io_core_exe_0_fresp_bits_uop_fp_single_0; // @[lsu.scala:201:7] wire io_core_exe_0_fresp_bits_uop_xcpt_pf_if_0; // @[lsu.scala:201:7] wire io_core_exe_0_fresp_bits_uop_xcpt_ae_if_0; // @[lsu.scala:201:7] wire io_core_exe_0_fresp_bits_uop_xcpt_ma_if_0; // @[lsu.scala:201:7] wire io_core_exe_0_fresp_bits_uop_bp_debug_if_0; // @[lsu.scala:201:7] wire io_core_exe_0_fresp_bits_uop_bp_xcpt_if_0; // @[lsu.scala:201:7] wire [1:0] io_core_exe_0_fresp_bits_uop_debug_fsrc_0; // @[lsu.scala:201:7] wire [1:0] io_core_exe_0_fresp_bits_uop_debug_tsrc_0; // @[lsu.scala:201:7] wire [64:0] io_core_exe_0_fresp_bits_data_0; // @[lsu.scala:201:7] wire io_core_exe_0_fresp_valid_0; // @[lsu.scala:201:7] wire [2:0] io_core_dis_ldq_idx_0_0; // @[lsu.scala:201:7] wire [2:0] io_core_dis_stq_idx_0_0; // @[lsu.scala:201:7] wire io_core_ldq_full_0_0; // @[lsu.scala:201:7] wire io_core_stq_full_0_0; // @[lsu.scala:201:7] wire io_core_fp_stdata_ready_0; // @[lsu.scala:201:7] wire io_core_clr_bsy_0_valid_0; // @[lsu.scala:201:7] wire [4:0] io_core_clr_bsy_0_bits_0; // @[lsu.scala:201:7] wire io_core_clr_bsy_1_valid_0; // @[lsu.scala:201:7] wire [4:0] io_core_clr_bsy_1_bits_0; // @[lsu.scala:201:7] wire [4:0] io_core_clr_unsafe_0_bits_0; // @[lsu.scala:201:7] wire io_core_spec_ld_wakeup_0_valid_0; // @[lsu.scala:201:7] wire [5:0] io_core_spec_ld_wakeup_0_bits_0; // @[lsu.scala:201:7] wire [3:0] io_core_lxcpt_bits_uop_ctrl_br_type_0; // @[lsu.scala:201:7] wire [1:0] io_core_lxcpt_bits_uop_ctrl_op1_sel_0; // @[lsu.scala:201:7] wire [2:0] io_core_lxcpt_bits_uop_ctrl_op2_sel_0; // @[lsu.scala:201:7] wire [2:0] io_core_lxcpt_bits_uop_ctrl_imm_sel_0; // @[lsu.scala:201:7] wire [4:0] io_core_lxcpt_bits_uop_ctrl_op_fcn_0; // @[lsu.scala:201:7] wire io_core_lxcpt_bits_uop_ctrl_fcn_dw_0; // @[lsu.scala:201:7] wire [2:0] io_core_lxcpt_bits_uop_ctrl_csr_cmd_0; // @[lsu.scala:201:7] wire io_core_lxcpt_bits_uop_ctrl_is_load_0; // @[lsu.scala:201:7] wire io_core_lxcpt_bits_uop_ctrl_is_sta_0; // @[lsu.scala:201:7] wire io_core_lxcpt_bits_uop_ctrl_is_std_0; // @[lsu.scala:201:7] wire [6:0] io_core_lxcpt_bits_uop_uopc_0; // @[lsu.scala:201:7] wire [31:0] io_core_lxcpt_bits_uop_inst_0; // @[lsu.scala:201:7] wire [31:0] io_core_lxcpt_bits_uop_debug_inst_0; // @[lsu.scala:201:7] wire io_core_lxcpt_bits_uop_is_rvc_0; // @[lsu.scala:201:7] wire [39:0] io_core_lxcpt_bits_uop_debug_pc_0; // @[lsu.scala:201:7] wire [2:0] io_core_lxcpt_bits_uop_iq_type_0; // @[lsu.scala:201:7] wire [9:0] io_core_lxcpt_bits_uop_fu_code_0; // @[lsu.scala:201:7] wire [1:0] io_core_lxcpt_bits_uop_iw_state_0; // @[lsu.scala:201:7] wire io_core_lxcpt_bits_uop_iw_p1_poisoned_0; // @[lsu.scala:201:7] wire io_core_lxcpt_bits_uop_iw_p2_poisoned_0; // @[lsu.scala:201:7] wire io_core_lxcpt_bits_uop_is_br_0; // @[lsu.scala:201:7] wire io_core_lxcpt_bits_uop_is_jalr_0; // @[lsu.scala:201:7] wire io_core_lxcpt_bits_uop_is_jal_0; // @[lsu.scala:201:7] wire io_core_lxcpt_bits_uop_is_sfb_0; // @[lsu.scala:201:7] wire [7:0] io_core_lxcpt_bits_uop_br_mask_0; // @[lsu.scala:201:7] wire [2:0] io_core_lxcpt_bits_uop_br_tag_0; // @[lsu.scala:201:7] wire [3:0] io_core_lxcpt_bits_uop_ftq_idx_0; // @[lsu.scala:201:7] wire io_core_lxcpt_bits_uop_edge_inst_0; // @[lsu.scala:201:7] wire [5:0] io_core_lxcpt_bits_uop_pc_lob_0; // @[lsu.scala:201:7] wire io_core_lxcpt_bits_uop_taken_0; // @[lsu.scala:201:7] wire [19:0] io_core_lxcpt_bits_uop_imm_packed_0; // @[lsu.scala:201:7] wire [11:0] io_core_lxcpt_bits_uop_csr_addr_0; // @[lsu.scala:201:7] wire [4:0] io_core_lxcpt_bits_uop_rob_idx_0; // @[lsu.scala:201:7] wire [2:0] io_core_lxcpt_bits_uop_ldq_idx_0; // @[lsu.scala:201:7] wire [2:0] io_core_lxcpt_bits_uop_stq_idx_0; // @[lsu.scala:201:7] wire [1:0] io_core_lxcpt_bits_uop_rxq_idx_0; // @[lsu.scala:201:7] wire [5:0] io_core_lxcpt_bits_uop_pdst_0; // @[lsu.scala:201:7] wire [5:0] io_core_lxcpt_bits_uop_prs1_0; // @[lsu.scala:201:7] wire [5:0] io_core_lxcpt_bits_uop_prs2_0; // @[lsu.scala:201:7] wire [5:0] io_core_lxcpt_bits_uop_prs3_0; // @[lsu.scala:201:7] wire [3:0] io_core_lxcpt_bits_uop_ppred_0; // @[lsu.scala:201:7] wire io_core_lxcpt_bits_uop_prs1_busy_0; // @[lsu.scala:201:7] wire io_core_lxcpt_bits_uop_prs2_busy_0; // @[lsu.scala:201:7] wire io_core_lxcpt_bits_uop_prs3_busy_0; // @[lsu.scala:201:7] wire io_core_lxcpt_bits_uop_ppred_busy_0; // @[lsu.scala:201:7] wire [5:0] io_core_lxcpt_bits_uop_stale_pdst_0; // @[lsu.scala:201:7] wire io_core_lxcpt_bits_uop_exception_0; // @[lsu.scala:201:7] wire [63:0] io_core_lxcpt_bits_uop_exc_cause_0; // @[lsu.scala:201:7] wire io_core_lxcpt_bits_uop_bypassable_0; // @[lsu.scala:201:7] wire [4:0] io_core_lxcpt_bits_uop_mem_cmd_0; // @[lsu.scala:201:7] wire [1:0] io_core_lxcpt_bits_uop_mem_size_0; // @[lsu.scala:201:7] wire io_core_lxcpt_bits_uop_mem_signed_0; // @[lsu.scala:201:7] wire io_core_lxcpt_bits_uop_is_fence_0; // @[lsu.scala:201:7] wire io_core_lxcpt_bits_uop_is_fencei_0; // @[lsu.scala:201:7] wire io_core_lxcpt_bits_uop_is_amo_0; // @[lsu.scala:201:7] wire io_core_lxcpt_bits_uop_uses_ldq_0; // @[lsu.scala:201:7] wire io_core_lxcpt_bits_uop_uses_stq_0; // @[lsu.scala:201:7] wire io_core_lxcpt_bits_uop_is_sys_pc2epc_0; // @[lsu.scala:201:7] wire io_core_lxcpt_bits_uop_is_unique_0; // @[lsu.scala:201:7] wire io_core_lxcpt_bits_uop_flush_on_commit_0; // @[lsu.scala:201:7] wire io_core_lxcpt_bits_uop_ldst_is_rs1_0; // @[lsu.scala:201:7] wire [5:0] io_core_lxcpt_bits_uop_ldst_0; // @[lsu.scala:201:7] wire [5:0] io_core_lxcpt_bits_uop_lrs1_0; // @[lsu.scala:201:7] wire [5:0] io_core_lxcpt_bits_uop_lrs2_0; // @[lsu.scala:201:7] wire [5:0] io_core_lxcpt_bits_uop_lrs3_0; // @[lsu.scala:201:7] wire io_core_lxcpt_bits_uop_ldst_val_0; // @[lsu.scala:201:7] wire [1:0] io_core_lxcpt_bits_uop_dst_rtype_0; // @[lsu.scala:201:7] wire [1:0] io_core_lxcpt_bits_uop_lrs1_rtype_0; // @[lsu.scala:201:7] wire [1:0] io_core_lxcpt_bits_uop_lrs2_rtype_0; // @[lsu.scala:201:7] wire io_core_lxcpt_bits_uop_frs3_en_0; // @[lsu.scala:201:7] wire io_core_lxcpt_bits_uop_fp_val_0; // @[lsu.scala:201:7] wire io_core_lxcpt_bits_uop_fp_single_0; // @[lsu.scala:201:7] wire io_core_lxcpt_bits_uop_xcpt_pf_if_0; // @[lsu.scala:201:7] wire io_core_lxcpt_bits_uop_xcpt_ae_if_0; // @[lsu.scala:201:7] wire io_core_lxcpt_bits_uop_xcpt_ma_if_0; // @[lsu.scala:201:7] wire io_core_lxcpt_bits_uop_bp_debug_if_0; // @[lsu.scala:201:7] wire io_core_lxcpt_bits_uop_bp_xcpt_if_0; // @[lsu.scala:201:7] wire [1:0] io_core_lxcpt_bits_uop_debug_fsrc_0; // @[lsu.scala:201:7] wire [1:0] io_core_lxcpt_bits_uop_debug_tsrc_0; // @[lsu.scala:201:7] wire [4:0] io_core_lxcpt_bits_cause_0; // @[lsu.scala:201:7] wire [39:0] io_core_lxcpt_bits_badvaddr_0; // @[lsu.scala:201:7] wire io_core_lxcpt_valid_0; // @[lsu.scala:201:7] wire io_core_perf_tlbMiss_0; // @[lsu.scala:201:7] wire io_core_ld_miss_0; // @[lsu.scala:201:7] wire io_core_fencei_rdy_0; // @[lsu.scala:201:7] wire [3:0] io_dmem_req_bits_0_bits_uop_ctrl_br_type_0; // @[lsu.scala:201:7] wire [1:0] io_dmem_req_bits_0_bits_uop_ctrl_op1_sel_0; // @[lsu.scala:201:7] wire [2:0] io_dmem_req_bits_0_bits_uop_ctrl_op2_sel_0; // @[lsu.scala:201:7] wire [2:0] io_dmem_req_bits_0_bits_uop_ctrl_imm_sel_0; // @[lsu.scala:201:7] wire [4:0] io_dmem_req_bits_0_bits_uop_ctrl_op_fcn_0; // @[lsu.scala:201:7] wire io_dmem_req_bits_0_bits_uop_ctrl_fcn_dw_0; // @[lsu.scala:201:7] wire [2:0] io_dmem_req_bits_0_bits_uop_ctrl_csr_cmd_0; // @[lsu.scala:201:7] wire io_dmem_req_bits_0_bits_uop_ctrl_is_load_0; // @[lsu.scala:201:7] wire io_dmem_req_bits_0_bits_uop_ctrl_is_sta_0; // @[lsu.scala:201:7] wire io_dmem_req_bits_0_bits_uop_ctrl_is_std_0; // @[lsu.scala:201:7] wire [6:0] io_dmem_req_bits_0_bits_uop_uopc_0; // @[lsu.scala:201:7] wire [31:0] io_dmem_req_bits_0_bits_uop_inst_0; // @[lsu.scala:201:7] wire [31:0] io_dmem_req_bits_0_bits_uop_debug_inst_0; // @[lsu.scala:201:7] wire io_dmem_req_bits_0_bits_uop_is_rvc_0; // @[lsu.scala:201:7] wire [39:0] io_dmem_req_bits_0_bits_uop_debug_pc_0; // @[lsu.scala:201:7] wire [2:0] io_dmem_req_bits_0_bits_uop_iq_type_0; // @[lsu.scala:201:7] wire [9:0] io_dmem_req_bits_0_bits_uop_fu_code_0; // @[lsu.scala:201:7] wire [1:0] io_dmem_req_bits_0_bits_uop_iw_state_0; // @[lsu.scala:201:7] wire io_dmem_req_bits_0_bits_uop_iw_p1_poisoned_0; // @[lsu.scala:201:7] wire io_dmem_req_bits_0_bits_uop_iw_p2_poisoned_0; // @[lsu.scala:201:7] wire io_dmem_req_bits_0_bits_uop_is_br_0; // @[lsu.scala:201:7] wire io_dmem_req_bits_0_bits_uop_is_jalr_0; // @[lsu.scala:201:7] wire io_dmem_req_bits_0_bits_uop_is_jal_0; // @[lsu.scala:201:7] wire io_dmem_req_bits_0_bits_uop_is_sfb_0; // @[lsu.scala:201:7] wire [7:0] io_dmem_req_bits_0_bits_uop_br_mask_0; // @[lsu.scala:201:7] wire [2:0] io_dmem_req_bits_0_bits_uop_br_tag_0; // @[lsu.scala:201:7] wire [3:0] io_dmem_req_bits_0_bits_uop_ftq_idx_0; // @[lsu.scala:201:7] wire io_dmem_req_bits_0_bits_uop_edge_inst_0; // @[lsu.scala:201:7] wire [5:0] io_dmem_req_bits_0_bits_uop_pc_lob_0; // @[lsu.scala:201:7] wire io_dmem_req_bits_0_bits_uop_taken_0; // @[lsu.scala:201:7] wire [19:0] io_dmem_req_bits_0_bits_uop_imm_packed_0; // @[lsu.scala:201:7] wire [11:0] io_dmem_req_bits_0_bits_uop_csr_addr_0; // @[lsu.scala:201:7] wire [4:0] io_dmem_req_bits_0_bits_uop_rob_idx_0; // @[lsu.scala:201:7] wire [2:0] io_dmem_req_bits_0_bits_uop_ldq_idx_0; // @[lsu.scala:201:7] wire [2:0] io_dmem_req_bits_0_bits_uop_stq_idx_0; // @[lsu.scala:201:7] wire [1:0] io_dmem_req_bits_0_bits_uop_rxq_idx_0; // @[lsu.scala:201:7] wire [5:0] io_dmem_req_bits_0_bits_uop_pdst_0; // @[lsu.scala:201:7] wire [5:0] io_dmem_req_bits_0_bits_uop_prs1_0; // @[lsu.scala:201:7] wire [5:0] io_dmem_req_bits_0_bits_uop_prs2_0; // @[lsu.scala:201:7] wire [5:0] io_dmem_req_bits_0_bits_uop_prs3_0; // @[lsu.scala:201:7] wire [3:0] io_dmem_req_bits_0_bits_uop_ppred_0; // @[lsu.scala:201:7] wire io_dmem_req_bits_0_bits_uop_prs1_busy_0; // @[lsu.scala:201:7] wire io_dmem_req_bits_0_bits_uop_prs2_busy_0; // @[lsu.scala:201:7] wire io_dmem_req_bits_0_bits_uop_prs3_busy_0; // @[lsu.scala:201:7] wire io_dmem_req_bits_0_bits_uop_ppred_busy_0; // @[lsu.scala:201:7] wire [5:0] io_dmem_req_bits_0_bits_uop_stale_pdst_0; // @[lsu.scala:201:7] wire io_dmem_req_bits_0_bits_uop_exception_0; // @[lsu.scala:201:7] wire [63:0] io_dmem_req_bits_0_bits_uop_exc_cause_0; // @[lsu.scala:201:7] wire io_dmem_req_bits_0_bits_uop_bypassable_0; // @[lsu.scala:201:7] wire [4:0] io_dmem_req_bits_0_bits_uop_mem_cmd_0; // @[lsu.scala:201:7] wire [1:0] io_dmem_req_bits_0_bits_uop_mem_size_0; // @[lsu.scala:201:7] wire io_dmem_req_bits_0_bits_uop_mem_signed_0; // @[lsu.scala:201:7] wire io_dmem_req_bits_0_bits_uop_is_fence_0; // @[lsu.scala:201:7] wire io_dmem_req_bits_0_bits_uop_is_fencei_0; // @[lsu.scala:201:7] wire io_dmem_req_bits_0_bits_uop_is_amo_0; // @[lsu.scala:201:7] wire io_dmem_req_bits_0_bits_uop_uses_ldq_0; // @[lsu.scala:201:7] wire io_dmem_req_bits_0_bits_uop_uses_stq_0; // @[lsu.scala:201:7] wire io_dmem_req_bits_0_bits_uop_is_sys_pc2epc_0; // @[lsu.scala:201:7] wire io_dmem_req_bits_0_bits_uop_is_unique_0; // @[lsu.scala:201:7] wire io_dmem_req_bits_0_bits_uop_flush_on_commit_0; // @[lsu.scala:201:7] wire io_dmem_req_bits_0_bits_uop_ldst_is_rs1_0; // @[lsu.scala:201:7] wire [5:0] io_dmem_req_bits_0_bits_uop_ldst_0; // @[lsu.scala:201:7] wire [5:0] io_dmem_req_bits_0_bits_uop_lrs1_0; // @[lsu.scala:201:7] wire [5:0] io_dmem_req_bits_0_bits_uop_lrs2_0; // @[lsu.scala:201:7] wire [5:0] io_dmem_req_bits_0_bits_uop_lrs3_0; // @[lsu.scala:201:7] wire io_dmem_req_bits_0_bits_uop_ldst_val_0; // @[lsu.scala:201:7] wire [1:0] io_dmem_req_bits_0_bits_uop_dst_rtype_0; // @[lsu.scala:201:7] wire [1:0] io_dmem_req_bits_0_bits_uop_lrs1_rtype_0; // @[lsu.scala:201:7] wire [1:0] io_dmem_req_bits_0_bits_uop_lrs2_rtype_0; // @[lsu.scala:201:7] wire io_dmem_req_bits_0_bits_uop_frs3_en_0; // @[lsu.scala:201:7] wire io_dmem_req_bits_0_bits_uop_fp_val_0; // @[lsu.scala:201:7] wire io_dmem_req_bits_0_bits_uop_fp_single_0; // @[lsu.scala:201:7] wire io_dmem_req_bits_0_bits_uop_xcpt_pf_if_0; // @[lsu.scala:201:7] wire io_dmem_req_bits_0_bits_uop_xcpt_ae_if_0; // @[lsu.scala:201:7] wire io_dmem_req_bits_0_bits_uop_xcpt_ma_if_0; // @[lsu.scala:201:7] wire io_dmem_req_bits_0_bits_uop_bp_debug_if_0; // @[lsu.scala:201:7] wire io_dmem_req_bits_0_bits_uop_bp_xcpt_if_0; // @[lsu.scala:201:7] wire [1:0] io_dmem_req_bits_0_bits_uop_debug_fsrc_0; // @[lsu.scala:201:7] wire [1:0] io_dmem_req_bits_0_bits_uop_debug_tsrc_0; // @[lsu.scala:201:7] wire [39:0] io_dmem_req_bits_0_bits_addr_0; // @[lsu.scala:201:7] wire [63:0] io_dmem_req_bits_0_bits_data_0; // @[lsu.scala:201:7] wire io_dmem_req_bits_0_bits_is_hella_0; // @[lsu.scala:201:7] wire io_dmem_req_bits_0_valid_0; // @[lsu.scala:201:7] wire io_dmem_req_valid_0; // @[lsu.scala:201:7] wire io_dmem_s1_kill_0_0; // @[lsu.scala:201:7] wire io_dmem_release_ready_0; // @[lsu.scala:201:7] wire io_dmem_force_order_0; // @[lsu.scala:201:7] wire io_hellacache_req_ready_0; // @[lsu.scala:201:7] wire [39:0] io_hellacache_resp_bits_addr_0; // @[lsu.scala:201:7] wire io_hellacache_resp_valid_0; // @[lsu.scala:201:7] wire io_hellacache_s2_xcpt_ma_ld_0; // @[lsu.scala:201:7] wire io_hellacache_s2_xcpt_ma_st_0; // @[lsu.scala:201:7] wire io_hellacache_s2_xcpt_pf_ld_0; // @[lsu.scala:201:7] wire io_hellacache_s2_xcpt_pf_st_0; // @[lsu.scala:201:7] wire io_hellacache_s2_xcpt_gf_ld_0; // @[lsu.scala:201:7] wire io_hellacache_s2_xcpt_gf_st_0; // @[lsu.scala:201:7] wire io_hellacache_s2_xcpt_ae_ld_0; // @[lsu.scala:201:7] wire io_hellacache_s2_xcpt_ae_st_0; // @[lsu.scala:201:7] wire io_hellacache_s2_nack_0; // @[lsu.scala:201:7] wire io_hellacache_store_pending_0; // @[lsu.scala:201:7] reg ldq_0_valid; // @[lsu.scala:208:16] reg [6:0] ldq_0_bits_uop_uopc; // @[lsu.scala:208:16] reg [31:0] ldq_0_bits_uop_inst; // @[lsu.scala:208:16] reg [31:0] ldq_0_bits_uop_debug_inst; // @[lsu.scala:208:16] reg ldq_0_bits_uop_is_rvc; // @[lsu.scala:208:16] reg [39:0] ldq_0_bits_uop_debug_pc; // @[lsu.scala:208:16] reg [2:0] ldq_0_bits_uop_iq_type; // @[lsu.scala:208:16] reg [9:0] ldq_0_bits_uop_fu_code; // @[lsu.scala:208:16] reg [3:0] ldq_0_bits_uop_ctrl_br_type; // @[lsu.scala:208:16] reg [1:0] ldq_0_bits_uop_ctrl_op1_sel; // @[lsu.scala:208:16] reg [2:0] ldq_0_bits_uop_ctrl_op2_sel; // @[lsu.scala:208:16] reg [2:0] ldq_0_bits_uop_ctrl_imm_sel; // @[lsu.scala:208:16] reg [4:0] ldq_0_bits_uop_ctrl_op_fcn; // @[lsu.scala:208:16] reg ldq_0_bits_uop_ctrl_fcn_dw; // @[lsu.scala:208:16] reg [2:0] ldq_0_bits_uop_ctrl_csr_cmd; // @[lsu.scala:208:16] reg ldq_0_bits_uop_ctrl_is_load; // @[lsu.scala:208:16] reg ldq_0_bits_uop_ctrl_is_sta; // @[lsu.scala:208:16] reg ldq_0_bits_uop_ctrl_is_std; // @[lsu.scala:208:16] reg [1:0] ldq_0_bits_uop_iw_state; // @[lsu.scala:208:16] reg ldq_0_bits_uop_iw_p1_poisoned; // @[lsu.scala:208:16] reg ldq_0_bits_uop_iw_p2_poisoned; // @[lsu.scala:208:16] reg ldq_0_bits_uop_is_br; // @[lsu.scala:208:16] reg ldq_0_bits_uop_is_jalr; // @[lsu.scala:208:16] reg ldq_0_bits_uop_is_jal; // @[lsu.scala:208:16] reg ldq_0_bits_uop_is_sfb; // @[lsu.scala:208:16] reg [7:0] ldq_0_bits_uop_br_mask; // @[lsu.scala:208:16] reg [2:0] ldq_0_bits_uop_br_tag; // @[lsu.scala:208:16] reg [3:0] ldq_0_bits_uop_ftq_idx; // @[lsu.scala:208:16] reg ldq_0_bits_uop_edge_inst; // @[lsu.scala:208:16] reg [5:0] ldq_0_bits_uop_pc_lob; // @[lsu.scala:208:16] reg ldq_0_bits_uop_taken; // @[lsu.scala:208:16] reg [19:0] ldq_0_bits_uop_imm_packed; // @[lsu.scala:208:16] reg [11:0] ldq_0_bits_uop_csr_addr; // @[lsu.scala:208:16] reg [4:0] ldq_0_bits_uop_rob_idx; // @[lsu.scala:208:16] reg [2:0] ldq_0_bits_uop_ldq_idx; // @[lsu.scala:208:16] reg [2:0] ldq_0_bits_uop_stq_idx; // @[lsu.scala:208:16] reg [1:0] ldq_0_bits_uop_rxq_idx; // @[lsu.scala:208:16] reg [5:0] ldq_0_bits_uop_pdst; // @[lsu.scala:208:16] reg [5:0] ldq_0_bits_uop_prs1; // @[lsu.scala:208:16] reg [5:0] ldq_0_bits_uop_prs2; // @[lsu.scala:208:16] reg [5:0] ldq_0_bits_uop_prs3; // @[lsu.scala:208:16] reg ldq_0_bits_uop_prs1_busy; // @[lsu.scala:208:16] reg ldq_0_bits_uop_prs2_busy; // @[lsu.scala:208:16] reg ldq_0_bits_uop_prs3_busy; // @[lsu.scala:208:16] reg [5:0] ldq_0_bits_uop_stale_pdst; // @[lsu.scala:208:16] reg ldq_0_bits_uop_exception; // @[lsu.scala:208:16] reg [63:0] ldq_0_bits_uop_exc_cause; // @[lsu.scala:208:16] reg ldq_0_bits_uop_bypassable; // @[lsu.scala:208:16] reg [4:0] ldq_0_bits_uop_mem_cmd; // @[lsu.scala:208:16] reg [1:0] ldq_0_bits_uop_mem_size; // @[lsu.scala:208:16] reg ldq_0_bits_uop_mem_signed; // @[lsu.scala:208:16] reg ldq_0_bits_uop_is_fence; // @[lsu.scala:208:16] reg ldq_0_bits_uop_is_fencei; // @[lsu.scala:208:16] reg ldq_0_bits_uop_is_amo; // @[lsu.scala:208:16] reg ldq_0_bits_uop_uses_ldq; // @[lsu.scala:208:16] reg ldq_0_bits_uop_uses_stq; // @[lsu.scala:208:16] reg ldq_0_bits_uop_is_sys_pc2epc; // @[lsu.scala:208:16] reg ldq_0_bits_uop_is_unique; // @[lsu.scala:208:16] reg ldq_0_bits_uop_flush_on_commit; // @[lsu.scala:208:16] reg ldq_0_bits_uop_ldst_is_rs1; // @[lsu.scala:208:16] reg [5:0] ldq_0_bits_uop_ldst; // @[lsu.scala:208:16] reg [5:0] ldq_0_bits_uop_lrs1; // @[lsu.scala:208:16] reg [5:0] ldq_0_bits_uop_lrs2; // @[lsu.scala:208:16] reg [5:0] ldq_0_bits_uop_lrs3; // @[lsu.scala:208:16] reg ldq_0_bits_uop_ldst_val; // @[lsu.scala:208:16] reg [1:0] ldq_0_bits_uop_dst_rtype; // @[lsu.scala:208:16] reg [1:0] ldq_0_bits_uop_lrs1_rtype; // @[lsu.scala:208:16] reg [1:0] ldq_0_bits_uop_lrs2_rtype; // @[lsu.scala:208:16] reg ldq_0_bits_uop_frs3_en; // @[lsu.scala:208:16] reg ldq_0_bits_uop_fp_val; // @[lsu.scala:208:16] reg ldq_0_bits_uop_fp_single; // @[lsu.scala:208:16] reg ldq_0_bits_uop_xcpt_pf_if; // @[lsu.scala:208:16] reg ldq_0_bits_uop_xcpt_ae_if; // @[lsu.scala:208:16] reg ldq_0_bits_uop_xcpt_ma_if; // @[lsu.scala:208:16] reg ldq_0_bits_uop_bp_debug_if; // @[lsu.scala:208:16] reg ldq_0_bits_uop_bp_xcpt_if; // @[lsu.scala:208:16] reg [1:0] ldq_0_bits_uop_debug_fsrc; // @[lsu.scala:208:16] reg [1:0] ldq_0_bits_uop_debug_tsrc; // @[lsu.scala:208:16] reg ldq_0_bits_addr_valid; // @[lsu.scala:208:16] reg [39:0] ldq_0_bits_addr_bits; // @[lsu.scala:208:16] reg ldq_0_bits_addr_is_virtual; // @[lsu.scala:208:16] reg ldq_0_bits_addr_is_uncacheable; // @[lsu.scala:208:16] reg ldq_0_bits_executed; // @[lsu.scala:208:16] reg ldq_0_bits_succeeded; // @[lsu.scala:208:16] reg ldq_0_bits_order_fail; // @[lsu.scala:208:16] reg ldq_0_bits_observed; // @[lsu.scala:208:16] reg [7:0] ldq_0_bits_st_dep_mask; // @[lsu.scala:208:16] reg [2:0] ldq_0_bits_youngest_stq_idx; // @[lsu.scala:208:16] reg ldq_0_bits_forward_std_val; // @[lsu.scala:208:16] reg [2:0] ldq_0_bits_forward_stq_idx; // @[lsu.scala:208:16] reg [63:0] ldq_0_bits_debug_wb_data; // @[lsu.scala:208:16] reg ldq_1_valid; // @[lsu.scala:208:16] reg [6:0] ldq_1_bits_uop_uopc; // @[lsu.scala:208:16] reg [31:0] ldq_1_bits_uop_inst; // @[lsu.scala:208:16] reg [31:0] ldq_1_bits_uop_debug_inst; // @[lsu.scala:208:16] reg ldq_1_bits_uop_is_rvc; // @[lsu.scala:208:16] reg [39:0] ldq_1_bits_uop_debug_pc; // @[lsu.scala:208:16] reg [2:0] ldq_1_bits_uop_iq_type; // @[lsu.scala:208:16] reg [9:0] ldq_1_bits_uop_fu_code; // @[lsu.scala:208:16] reg [3:0] ldq_1_bits_uop_ctrl_br_type; // @[lsu.scala:208:16] reg [1:0] ldq_1_bits_uop_ctrl_op1_sel; // @[lsu.scala:208:16] reg [2:0] ldq_1_bits_uop_ctrl_op2_sel; // @[lsu.scala:208:16] reg [2:0] ldq_1_bits_uop_ctrl_imm_sel; // @[lsu.scala:208:16] reg [4:0] ldq_1_bits_uop_ctrl_op_fcn; // @[lsu.scala:208:16] reg ldq_1_bits_uop_ctrl_fcn_dw; // @[lsu.scala:208:16] reg [2:0] ldq_1_bits_uop_ctrl_csr_cmd; // @[lsu.scala:208:16] reg ldq_1_bits_uop_ctrl_is_load; // @[lsu.scala:208:16] reg ldq_1_bits_uop_ctrl_is_sta; // @[lsu.scala:208:16] reg ldq_1_bits_uop_ctrl_is_std; // @[lsu.scala:208:16] reg [1:0] ldq_1_bits_uop_iw_state; // @[lsu.scala:208:16] reg ldq_1_bits_uop_iw_p1_poisoned; // @[lsu.scala:208:16] reg ldq_1_bits_uop_iw_p2_poisoned; // @[lsu.scala:208:16] reg ldq_1_bits_uop_is_br; // @[lsu.scala:208:16] reg ldq_1_bits_uop_is_jalr; // @[lsu.scala:208:16] reg ldq_1_bits_uop_is_jal; // @[lsu.scala:208:16] reg ldq_1_bits_uop_is_sfb; // @[lsu.scala:208:16] reg [7:0] ldq_1_bits_uop_br_mask; // @[lsu.scala:208:16] reg [2:0] ldq_1_bits_uop_br_tag; // @[lsu.scala:208:16] reg [3:0] ldq_1_bits_uop_ftq_idx; // @[lsu.scala:208:16] reg ldq_1_bits_uop_edge_inst; // @[lsu.scala:208:16] reg [5:0] ldq_1_bits_uop_pc_lob; // @[lsu.scala:208:16] reg ldq_1_bits_uop_taken; // @[lsu.scala:208:16] reg [19:0] ldq_1_bits_uop_imm_packed; // @[lsu.scala:208:16] reg [11:0] ldq_1_bits_uop_csr_addr; // @[lsu.scala:208:16] reg [4:0] ldq_1_bits_uop_rob_idx; // @[lsu.scala:208:16] reg [2:0] ldq_1_bits_uop_ldq_idx; // @[lsu.scala:208:16] reg [2:0] ldq_1_bits_uop_stq_idx; // @[lsu.scala:208:16] reg [1:0] ldq_1_bits_uop_rxq_idx; // @[lsu.scala:208:16] reg [5:0] ldq_1_bits_uop_pdst; // @[lsu.scala:208:16] reg [5:0] ldq_1_bits_uop_prs1; // @[lsu.scala:208:16] reg [5:0] ldq_1_bits_uop_prs2; // @[lsu.scala:208:16] reg [5:0] ldq_1_bits_uop_prs3; // @[lsu.scala:208:16] reg ldq_1_bits_uop_prs1_busy; // @[lsu.scala:208:16] reg ldq_1_bits_uop_prs2_busy; // @[lsu.scala:208:16] reg ldq_1_bits_uop_prs3_busy; // @[lsu.scala:208:16] reg [5:0] ldq_1_bits_uop_stale_pdst; // @[lsu.scala:208:16] reg ldq_1_bits_uop_exception; // @[lsu.scala:208:16] reg [63:0] ldq_1_bits_uop_exc_cause; // @[lsu.scala:208:16] reg ldq_1_bits_uop_bypassable; // @[lsu.scala:208:16] reg [4:0] ldq_1_bits_uop_mem_cmd; // @[lsu.scala:208:16] reg [1:0] ldq_1_bits_uop_mem_size; // @[lsu.scala:208:16] reg ldq_1_bits_uop_mem_signed; // @[lsu.scala:208:16] reg ldq_1_bits_uop_is_fence; // @[lsu.scala:208:16] reg ldq_1_bits_uop_is_fencei; // @[lsu.scala:208:16] reg ldq_1_bits_uop_is_amo; // @[lsu.scala:208:16] reg ldq_1_bits_uop_uses_ldq; // @[lsu.scala:208:16] reg ldq_1_bits_uop_uses_stq; // @[lsu.scala:208:16] reg ldq_1_bits_uop_is_sys_pc2epc; // @[lsu.scala:208:16] reg ldq_1_bits_uop_is_unique; // @[lsu.scala:208:16] reg ldq_1_bits_uop_flush_on_commit; // @[lsu.scala:208:16] reg ldq_1_bits_uop_ldst_is_rs1; // @[lsu.scala:208:16] reg [5:0] ldq_1_bits_uop_ldst; // @[lsu.scala:208:16] reg [5:0] ldq_1_bits_uop_lrs1; // @[lsu.scala:208:16] reg [5:0] ldq_1_bits_uop_lrs2; // @[lsu.scala:208:16] reg [5:0] ldq_1_bits_uop_lrs3; // @[lsu.scala:208:16] reg ldq_1_bits_uop_ldst_val; // @[lsu.scala:208:16] reg [1:0] ldq_1_bits_uop_dst_rtype; // @[lsu.scala:208:16] reg [1:0] ldq_1_bits_uop_lrs1_rtype; // @[lsu.scala:208:16] reg [1:0] ldq_1_bits_uop_lrs2_rtype; // @[lsu.scala:208:16] reg ldq_1_bits_uop_frs3_en; // @[lsu.scala:208:16] reg ldq_1_bits_uop_fp_val; // @[lsu.scala:208:16] reg ldq_1_bits_uop_fp_single; // @[lsu.scala:208:16] reg ldq_1_bits_uop_xcpt_pf_if; // @[lsu.scala:208:16] reg ldq_1_bits_uop_xcpt_ae_if; // @[lsu.scala:208:16] reg ldq_1_bits_uop_xcpt_ma_if; // @[lsu.scala:208:16] reg ldq_1_bits_uop_bp_debug_if; // @[lsu.scala:208:16] reg ldq_1_bits_uop_bp_xcpt_if; // @[lsu.scala:208:16] reg [1:0] ldq_1_bits_uop_debug_fsrc; // @[lsu.scala:208:16] reg [1:0] ldq_1_bits_uop_debug_tsrc; // @[lsu.scala:208:16] reg ldq_1_bits_addr_valid; // @[lsu.scala:208:16] reg [39:0] ldq_1_bits_addr_bits; // @[lsu.scala:208:16] reg ldq_1_bits_addr_is_virtual; // @[lsu.scala:208:16] reg ldq_1_bits_addr_is_uncacheable; // @[lsu.scala:208:16] reg ldq_1_bits_executed; // @[lsu.scala:208:16] reg ldq_1_bits_succeeded; // @[lsu.scala:208:16] reg ldq_1_bits_order_fail; // @[lsu.scala:208:16] reg ldq_1_bits_observed; // @[lsu.scala:208:16] reg [7:0] ldq_1_bits_st_dep_mask; // @[lsu.scala:208:16] reg [2:0] ldq_1_bits_youngest_stq_idx; // @[lsu.scala:208:16] reg ldq_1_bits_forward_std_val; // @[lsu.scala:208:16] reg [2:0] ldq_1_bits_forward_stq_idx; // @[lsu.scala:208:16] reg [63:0] ldq_1_bits_debug_wb_data; // @[lsu.scala:208:16] reg ldq_2_valid; // @[lsu.scala:208:16] reg [6:0] ldq_2_bits_uop_uopc; // @[lsu.scala:208:16] reg [31:0] ldq_2_bits_uop_inst; // @[lsu.scala:208:16] reg [31:0] ldq_2_bits_uop_debug_inst; // @[lsu.scala:208:16] reg ldq_2_bits_uop_is_rvc; // @[lsu.scala:208:16] reg [39:0] ldq_2_bits_uop_debug_pc; // @[lsu.scala:208:16] reg [2:0] ldq_2_bits_uop_iq_type; // @[lsu.scala:208:16] reg [9:0] ldq_2_bits_uop_fu_code; // @[lsu.scala:208:16] reg [3:0] ldq_2_bits_uop_ctrl_br_type; // @[lsu.scala:208:16] reg [1:0] ldq_2_bits_uop_ctrl_op1_sel; // @[lsu.scala:208:16] reg [2:0] ldq_2_bits_uop_ctrl_op2_sel; // @[lsu.scala:208:16] reg [2:0] ldq_2_bits_uop_ctrl_imm_sel; // @[lsu.scala:208:16] reg [4:0] ldq_2_bits_uop_ctrl_op_fcn; // @[lsu.scala:208:16] reg ldq_2_bits_uop_ctrl_fcn_dw; // @[lsu.scala:208:16] reg [2:0] ldq_2_bits_uop_ctrl_csr_cmd; // @[lsu.scala:208:16] reg ldq_2_bits_uop_ctrl_is_load; // @[lsu.scala:208:16] reg ldq_2_bits_uop_ctrl_is_sta; // @[lsu.scala:208:16] reg ldq_2_bits_uop_ctrl_is_std; // @[lsu.scala:208:16] reg [1:0] ldq_2_bits_uop_iw_state; // @[lsu.scala:208:16] reg ldq_2_bits_uop_iw_p1_poisoned; // @[lsu.scala:208:16] reg ldq_2_bits_uop_iw_p2_poisoned; // @[lsu.scala:208:16] reg ldq_2_bits_uop_is_br; // @[lsu.scala:208:16] reg ldq_2_bits_uop_is_jalr; // @[lsu.scala:208:16] reg ldq_2_bits_uop_is_jal; // @[lsu.scala:208:16] reg ldq_2_bits_uop_is_sfb; // @[lsu.scala:208:16] reg [7:0] ldq_2_bits_uop_br_mask; // @[lsu.scala:208:16] reg [2:0] ldq_2_bits_uop_br_tag; // @[lsu.scala:208:16] reg [3:0] ldq_2_bits_uop_ftq_idx; // @[lsu.scala:208:16] reg ldq_2_bits_uop_edge_inst; // @[lsu.scala:208:16] reg [5:0] ldq_2_bits_uop_pc_lob; // @[lsu.scala:208:16] reg ldq_2_bits_uop_taken; // @[lsu.scala:208:16] reg [19:0] ldq_2_bits_uop_imm_packed; // @[lsu.scala:208:16] reg [11:0] ldq_2_bits_uop_csr_addr; // @[lsu.scala:208:16] reg [4:0] ldq_2_bits_uop_rob_idx; // @[lsu.scala:208:16] reg [2:0] ldq_2_bits_uop_ldq_idx; // @[lsu.scala:208:16] reg [2:0] ldq_2_bits_uop_stq_idx; // @[lsu.scala:208:16] reg [1:0] ldq_2_bits_uop_rxq_idx; // @[lsu.scala:208:16] reg [5:0] ldq_2_bits_uop_pdst; // @[lsu.scala:208:16] reg [5:0] ldq_2_bits_uop_prs1; // @[lsu.scala:208:16] reg [5:0] ldq_2_bits_uop_prs2; // @[lsu.scala:208:16] reg [5:0] ldq_2_bits_uop_prs3; // @[lsu.scala:208:16] reg ldq_2_bits_uop_prs1_busy; // @[lsu.scala:208:16] reg ldq_2_bits_uop_prs2_busy; // @[lsu.scala:208:16] reg ldq_2_bits_uop_prs3_busy; // @[lsu.scala:208:16] reg [5:0] ldq_2_bits_uop_stale_pdst; // @[lsu.scala:208:16] reg ldq_2_bits_uop_exception; // @[lsu.scala:208:16] reg [63:0] ldq_2_bits_uop_exc_cause; // @[lsu.scala:208:16] reg ldq_2_bits_uop_bypassable; // @[lsu.scala:208:16] reg [4:0] ldq_2_bits_uop_mem_cmd; // @[lsu.scala:208:16] reg [1:0] ldq_2_bits_uop_mem_size; // @[lsu.scala:208:16] reg ldq_2_bits_uop_mem_signed; // @[lsu.scala:208:16] reg ldq_2_bits_uop_is_fence; // @[lsu.scala:208:16] reg ldq_2_bits_uop_is_fencei; // @[lsu.scala:208:16] reg ldq_2_bits_uop_is_amo; // @[lsu.scala:208:16] reg ldq_2_bits_uop_uses_ldq; // @[lsu.scala:208:16] reg ldq_2_bits_uop_uses_stq; // @[lsu.scala:208:16] reg ldq_2_bits_uop_is_sys_pc2epc; // @[lsu.scala:208:16] reg ldq_2_bits_uop_is_unique; // @[lsu.scala:208:16] reg ldq_2_bits_uop_flush_on_commit; // @[lsu.scala:208:16] reg ldq_2_bits_uop_ldst_is_rs1; // @[lsu.scala:208:16] reg [5:0] ldq_2_bits_uop_ldst; // @[lsu.scala:208:16] reg [5:0] ldq_2_bits_uop_lrs1; // @[lsu.scala:208:16] reg [5:0] ldq_2_bits_uop_lrs2; // @[lsu.scala:208:16] reg [5:0] ldq_2_bits_uop_lrs3; // @[lsu.scala:208:16] reg ldq_2_bits_uop_ldst_val; // @[lsu.scala:208:16] reg [1:0] ldq_2_bits_uop_dst_rtype; // @[lsu.scala:208:16] reg [1:0] ldq_2_bits_uop_lrs1_rtype; // @[lsu.scala:208:16] reg [1:0] ldq_2_bits_uop_lrs2_rtype; // @[lsu.scala:208:16] reg ldq_2_bits_uop_frs3_en; // @[lsu.scala:208:16] reg ldq_2_bits_uop_fp_val; // @[lsu.scala:208:16] reg ldq_2_bits_uop_fp_single; // @[lsu.scala:208:16] reg ldq_2_bits_uop_xcpt_pf_if; // @[lsu.scala:208:16] reg ldq_2_bits_uop_xcpt_ae_if; // @[lsu.scala:208:16] reg ldq_2_bits_uop_xcpt_ma_if; // @[lsu.scala:208:16] reg ldq_2_bits_uop_bp_debug_if; // @[lsu.scala:208:16] reg ldq_2_bits_uop_bp_xcpt_if; // @[lsu.scala:208:16] reg [1:0] ldq_2_bits_uop_debug_fsrc; // @[lsu.scala:208:16] reg [1:0] ldq_2_bits_uop_debug_tsrc; // @[lsu.scala:208:16] reg ldq_2_bits_addr_valid; // @[lsu.scala:208:16] reg [39:0] ldq_2_bits_addr_bits; // @[lsu.scala:208:16] reg ldq_2_bits_addr_is_virtual; // @[lsu.scala:208:16] reg ldq_2_bits_addr_is_uncacheable; // @[lsu.scala:208:16] reg ldq_2_bits_executed; // @[lsu.scala:208:16] reg ldq_2_bits_succeeded; // @[lsu.scala:208:16] reg ldq_2_bits_order_fail; // @[lsu.scala:208:16] reg ldq_2_bits_observed; // @[lsu.scala:208:16] reg [7:0] ldq_2_bits_st_dep_mask; // @[lsu.scala:208:16] reg [2:0] ldq_2_bits_youngest_stq_idx; // @[lsu.scala:208:16] reg ldq_2_bits_forward_std_val; // @[lsu.scala:208:16] reg [2:0] ldq_2_bits_forward_stq_idx; // @[lsu.scala:208:16] reg [63:0] ldq_2_bits_debug_wb_data; // @[lsu.scala:208:16] reg ldq_3_valid; // @[lsu.scala:208:16] reg [6:0] ldq_3_bits_uop_uopc; // @[lsu.scala:208:16] reg [31:0] ldq_3_bits_uop_inst; // @[lsu.scala:208:16] reg [31:0] ldq_3_bits_uop_debug_inst; // @[lsu.scala:208:16] reg ldq_3_bits_uop_is_rvc; // @[lsu.scala:208:16] reg [39:0] ldq_3_bits_uop_debug_pc; // @[lsu.scala:208:16] reg [2:0] ldq_3_bits_uop_iq_type; // @[lsu.scala:208:16] reg [9:0] ldq_3_bits_uop_fu_code; // @[lsu.scala:208:16] reg [3:0] ldq_3_bits_uop_ctrl_br_type; // @[lsu.scala:208:16] reg [1:0] ldq_3_bits_uop_ctrl_op1_sel; // @[lsu.scala:208:16] reg [2:0] ldq_3_bits_uop_ctrl_op2_sel; // @[lsu.scala:208:16] reg [2:0] ldq_3_bits_uop_ctrl_imm_sel; // @[lsu.scala:208:16] reg [4:0] ldq_3_bits_uop_ctrl_op_fcn; // @[lsu.scala:208:16] reg ldq_3_bits_uop_ctrl_fcn_dw; // @[lsu.scala:208:16] reg [2:0] ldq_3_bits_uop_ctrl_csr_cmd; // @[lsu.scala:208:16] reg ldq_3_bits_uop_ctrl_is_load; // @[lsu.scala:208:16] reg ldq_3_bits_uop_ctrl_is_sta; // @[lsu.scala:208:16] reg ldq_3_bits_uop_ctrl_is_std; // @[lsu.scala:208:16] reg [1:0] ldq_3_bits_uop_iw_state; // @[lsu.scala:208:16] reg ldq_3_bits_uop_iw_p1_poisoned; // @[lsu.scala:208:16] reg ldq_3_bits_uop_iw_p2_poisoned; // @[lsu.scala:208:16] reg ldq_3_bits_uop_is_br; // @[lsu.scala:208:16] reg ldq_3_bits_uop_is_jalr; // @[lsu.scala:208:16] reg ldq_3_bits_uop_is_jal; // @[lsu.scala:208:16] reg ldq_3_bits_uop_is_sfb; // @[lsu.scala:208:16] reg [7:0] ldq_3_bits_uop_br_mask; // @[lsu.scala:208:16] reg [2:0] ldq_3_bits_uop_br_tag; // @[lsu.scala:208:16] reg [3:0] ldq_3_bits_uop_ftq_idx; // @[lsu.scala:208:16] reg ldq_3_bits_uop_edge_inst; // @[lsu.scala:208:16] reg [5:0] ldq_3_bits_uop_pc_lob; // @[lsu.scala:208:16] reg ldq_3_bits_uop_taken; // @[lsu.scala:208:16] reg [19:0] ldq_3_bits_uop_imm_packed; // @[lsu.scala:208:16] reg [11:0] ldq_3_bits_uop_csr_addr; // @[lsu.scala:208:16] reg [4:0] ldq_3_bits_uop_rob_idx; // @[lsu.scala:208:16] reg [2:0] ldq_3_bits_uop_ldq_idx; // @[lsu.scala:208:16] reg [2:0] ldq_3_bits_uop_stq_idx; // @[lsu.scala:208:16] reg [1:0] ldq_3_bits_uop_rxq_idx; // @[lsu.scala:208:16] reg [5:0] ldq_3_bits_uop_pdst; // @[lsu.scala:208:16] reg [5:0] ldq_3_bits_uop_prs1; // @[lsu.scala:208:16] reg [5:0] ldq_3_bits_uop_prs2; // @[lsu.scala:208:16] reg [5:0] ldq_3_bits_uop_prs3; // @[lsu.scala:208:16] reg ldq_3_bits_uop_prs1_busy; // @[lsu.scala:208:16] reg ldq_3_bits_uop_prs2_busy; // @[lsu.scala:208:16] reg ldq_3_bits_uop_prs3_busy; // @[lsu.scala:208:16] reg [5:0] ldq_3_bits_uop_stale_pdst; // @[lsu.scala:208:16] reg ldq_3_bits_uop_exception; // @[lsu.scala:208:16] reg [63:0] ldq_3_bits_uop_exc_cause; // @[lsu.scala:208:16] reg ldq_3_bits_uop_bypassable; // @[lsu.scala:208:16] reg [4:0] ldq_3_bits_uop_mem_cmd; // @[lsu.scala:208:16] reg [1:0] ldq_3_bits_uop_mem_size; // @[lsu.scala:208:16] reg ldq_3_bits_uop_mem_signed; // @[lsu.scala:208:16] reg ldq_3_bits_uop_is_fence; // @[lsu.scala:208:16] reg ldq_3_bits_uop_is_fencei; // @[lsu.scala:208:16] reg ldq_3_bits_uop_is_amo; // @[lsu.scala:208:16] reg ldq_3_bits_uop_uses_ldq; // @[lsu.scala:208:16] reg ldq_3_bits_uop_uses_stq; // @[lsu.scala:208:16] reg ldq_3_bits_uop_is_sys_pc2epc; // @[lsu.scala:208:16] reg ldq_3_bits_uop_is_unique; // @[lsu.scala:208:16] reg ldq_3_bits_uop_flush_on_commit; // @[lsu.scala:208:16] reg ldq_3_bits_uop_ldst_is_rs1; // @[lsu.scala:208:16] reg [5:0] ldq_3_bits_uop_ldst; // @[lsu.scala:208:16] reg [5:0] ldq_3_bits_uop_lrs1; // @[lsu.scala:208:16] reg [5:0] ldq_3_bits_uop_lrs2; // @[lsu.scala:208:16] reg [5:0] ldq_3_bits_uop_lrs3; // @[lsu.scala:208:16] reg ldq_3_bits_uop_ldst_val; // @[lsu.scala:208:16] reg [1:0] ldq_3_bits_uop_dst_rtype; // @[lsu.scala:208:16] reg [1:0] ldq_3_bits_uop_lrs1_rtype; // @[lsu.scala:208:16] reg [1:0] ldq_3_bits_uop_lrs2_rtype; // @[lsu.scala:208:16] reg ldq_3_bits_uop_frs3_en; // @[lsu.scala:208:16] reg ldq_3_bits_uop_fp_val; // @[lsu.scala:208:16] reg ldq_3_bits_uop_fp_single; // @[lsu.scala:208:16] reg ldq_3_bits_uop_xcpt_pf_if; // @[lsu.scala:208:16] reg ldq_3_bits_uop_xcpt_ae_if; // @[lsu.scala:208:16] reg ldq_3_bits_uop_xcpt_ma_if; // @[lsu.scala:208:16] reg ldq_3_bits_uop_bp_debug_if; // @[lsu.scala:208:16] reg ldq_3_bits_uop_bp_xcpt_if; // @[lsu.scala:208:16] reg [1:0] ldq_3_bits_uop_debug_fsrc; // @[lsu.scala:208:16] reg [1:0] ldq_3_bits_uop_debug_tsrc; // @[lsu.scala:208:16] reg ldq_3_bits_addr_valid; // @[lsu.scala:208:16] reg [39:0] ldq_3_bits_addr_bits; // @[lsu.scala:208:16] reg ldq_3_bits_addr_is_virtual; // @[lsu.scala:208:16] reg ldq_3_bits_addr_is_uncacheable; // @[lsu.scala:208:16] reg ldq_3_bits_executed; // @[lsu.scala:208:16] reg ldq_3_bits_succeeded; // @[lsu.scala:208:16] reg ldq_3_bits_order_fail; // @[lsu.scala:208:16] reg ldq_3_bits_observed; // @[lsu.scala:208:16] reg [7:0] ldq_3_bits_st_dep_mask; // @[lsu.scala:208:16] reg [2:0] ldq_3_bits_youngest_stq_idx; // @[lsu.scala:208:16] reg ldq_3_bits_forward_std_val; // @[lsu.scala:208:16] reg [2:0] ldq_3_bits_forward_stq_idx; // @[lsu.scala:208:16] reg [63:0] ldq_3_bits_debug_wb_data; // @[lsu.scala:208:16] reg ldq_4_valid; // @[lsu.scala:208:16] reg [6:0] ldq_4_bits_uop_uopc; // @[lsu.scala:208:16] reg [31:0] ldq_4_bits_uop_inst; // @[lsu.scala:208:16] reg [31:0] ldq_4_bits_uop_debug_inst; // @[lsu.scala:208:16] reg ldq_4_bits_uop_is_rvc; // @[lsu.scala:208:16] reg [39:0] ldq_4_bits_uop_debug_pc; // @[lsu.scala:208:16] reg [2:0] ldq_4_bits_uop_iq_type; // @[lsu.scala:208:16] reg [9:0] ldq_4_bits_uop_fu_code; // @[lsu.scala:208:16] reg [3:0] ldq_4_bits_uop_ctrl_br_type; // @[lsu.scala:208:16] reg [1:0] ldq_4_bits_uop_ctrl_op1_sel; // @[lsu.scala:208:16] reg [2:0] ldq_4_bits_uop_ctrl_op2_sel; // @[lsu.scala:208:16] reg [2:0] ldq_4_bits_uop_ctrl_imm_sel; // @[lsu.scala:208:16] reg [4:0] ldq_4_bits_uop_ctrl_op_fcn; // @[lsu.scala:208:16] reg ldq_4_bits_uop_ctrl_fcn_dw; // @[lsu.scala:208:16] reg [2:0] ldq_4_bits_uop_ctrl_csr_cmd; // @[lsu.scala:208:16] reg ldq_4_bits_uop_ctrl_is_load; // @[lsu.scala:208:16] reg ldq_4_bits_uop_ctrl_is_sta; // @[lsu.scala:208:16] reg ldq_4_bits_uop_ctrl_is_std; // @[lsu.scala:208:16] reg [1:0] ldq_4_bits_uop_iw_state; // @[lsu.scala:208:16] reg ldq_4_bits_uop_iw_p1_poisoned; // @[lsu.scala:208:16] reg ldq_4_bits_uop_iw_p2_poisoned; // @[lsu.scala:208:16] reg ldq_4_bits_uop_is_br; // @[lsu.scala:208:16] reg ldq_4_bits_uop_is_jalr; // @[lsu.scala:208:16] reg ldq_4_bits_uop_is_jal; // @[lsu.scala:208:16] reg ldq_4_bits_uop_is_sfb; // @[lsu.scala:208:16] reg [7:0] ldq_4_bits_uop_br_mask; // @[lsu.scala:208:16] reg [2:0] ldq_4_bits_uop_br_tag; // @[lsu.scala:208:16] reg [3:0] ldq_4_bits_uop_ftq_idx; // @[lsu.scala:208:16] reg ldq_4_bits_uop_edge_inst; // @[lsu.scala:208:16] reg [5:0] ldq_4_bits_uop_pc_lob; // @[lsu.scala:208:16] reg ldq_4_bits_uop_taken; // @[lsu.scala:208:16] reg [19:0] ldq_4_bits_uop_imm_packed; // @[lsu.scala:208:16] reg [11:0] ldq_4_bits_uop_csr_addr; // @[lsu.scala:208:16] reg [4:0] ldq_4_bits_uop_rob_idx; // @[lsu.scala:208:16] reg [2:0] ldq_4_bits_uop_ldq_idx; // @[lsu.scala:208:16] reg [2:0] ldq_4_bits_uop_stq_idx; // @[lsu.scala:208:16] reg [1:0] ldq_4_bits_uop_rxq_idx; // @[lsu.scala:208:16] reg [5:0] ldq_4_bits_uop_pdst; // @[lsu.scala:208:16] reg [5:0] ldq_4_bits_uop_prs1; // @[lsu.scala:208:16] reg [5:0] ldq_4_bits_uop_prs2; // @[lsu.scala:208:16] reg [5:0] ldq_4_bits_uop_prs3; // @[lsu.scala:208:16] reg ldq_4_bits_uop_prs1_busy; // @[lsu.scala:208:16] reg ldq_4_bits_uop_prs2_busy; // @[lsu.scala:208:16] reg ldq_4_bits_uop_prs3_busy; // @[lsu.scala:208:16] reg [5:0] ldq_4_bits_uop_stale_pdst; // @[lsu.scala:208:16] reg ldq_4_bits_uop_exception; // @[lsu.scala:208:16] reg [63:0] ldq_4_bits_uop_exc_cause; // @[lsu.scala:208:16] reg ldq_4_bits_uop_bypassable; // @[lsu.scala:208:16] reg [4:0] ldq_4_bits_uop_mem_cmd; // @[lsu.scala:208:16] reg [1:0] ldq_4_bits_uop_mem_size; // @[lsu.scala:208:16] reg ldq_4_bits_uop_mem_signed; // @[lsu.scala:208:16] reg ldq_4_bits_uop_is_fence; // @[lsu.scala:208:16] reg ldq_4_bits_uop_is_fencei; // @[lsu.scala:208:16] reg ldq_4_bits_uop_is_amo; // @[lsu.scala:208:16] reg ldq_4_bits_uop_uses_ldq; // @[lsu.scala:208:16] reg ldq_4_bits_uop_uses_stq; // @[lsu.scala:208:16] reg ldq_4_bits_uop_is_sys_pc2epc; // @[lsu.scala:208:16] reg ldq_4_bits_uop_is_unique; // @[lsu.scala:208:16] reg ldq_4_bits_uop_flush_on_commit; // @[lsu.scala:208:16] reg ldq_4_bits_uop_ldst_is_rs1; // @[lsu.scala:208:16] reg [5:0] ldq_4_bits_uop_ldst; // @[lsu.scala:208:16] reg [5:0] ldq_4_bits_uop_lrs1; // @[lsu.scala:208:16] reg [5:0] ldq_4_bits_uop_lrs2; // @[lsu.scala:208:16] reg [5:0] ldq_4_bits_uop_lrs3; // @[lsu.scala:208:16] reg ldq_4_bits_uop_ldst_val; // @[lsu.scala:208:16] reg [1:0] ldq_4_bits_uop_dst_rtype; // @[lsu.scala:208:16] reg [1:0] ldq_4_bits_uop_lrs1_rtype; // @[lsu.scala:208:16] reg [1:0] ldq_4_bits_uop_lrs2_rtype; // @[lsu.scala:208:16] reg ldq_4_bits_uop_frs3_en; // @[lsu.scala:208:16] reg ldq_4_bits_uop_fp_val; // @[lsu.scala:208:16] reg ldq_4_bits_uop_fp_single; // @[lsu.scala:208:16] reg ldq_4_bits_uop_xcpt_pf_if; // @[lsu.scala:208:16] reg ldq_4_bits_uop_xcpt_ae_if; // @[lsu.scala:208:16] reg ldq_4_bits_uop_xcpt_ma_if; // @[lsu.scala:208:16] reg ldq_4_bits_uop_bp_debug_if; // @[lsu.scala:208:16] reg ldq_4_bits_uop_bp_xcpt_if; // @[lsu.scala:208:16] reg [1:0] ldq_4_bits_uop_debug_fsrc; // @[lsu.scala:208:16] reg [1:0] ldq_4_bits_uop_debug_tsrc; // @[lsu.scala:208:16] reg ldq_4_bits_addr_valid; // @[lsu.scala:208:16] reg [39:0] ldq_4_bits_addr_bits; // @[lsu.scala:208:16] reg ldq_4_bits_addr_is_virtual; // @[lsu.scala:208:16] reg ldq_4_bits_addr_is_uncacheable; // @[lsu.scala:208:16] reg ldq_4_bits_executed; // @[lsu.scala:208:16] reg ldq_4_bits_succeeded; // @[lsu.scala:208:16] reg ldq_4_bits_order_fail; // @[lsu.scala:208:16] reg ldq_4_bits_observed; // @[lsu.scala:208:16] reg [7:0] ldq_4_bits_st_dep_mask; // @[lsu.scala:208:16] reg [2:0] ldq_4_bits_youngest_stq_idx; // @[lsu.scala:208:16] reg ldq_4_bits_forward_std_val; // @[lsu.scala:208:16] reg [2:0] ldq_4_bits_forward_stq_idx; // @[lsu.scala:208:16] reg [63:0] ldq_4_bits_debug_wb_data; // @[lsu.scala:208:16] reg ldq_5_valid; // @[lsu.scala:208:16] reg [6:0] ldq_5_bits_uop_uopc; // @[lsu.scala:208:16] reg [31:0] ldq_5_bits_uop_inst; // @[lsu.scala:208:16] reg [31:0] ldq_5_bits_uop_debug_inst; // @[lsu.scala:208:16] reg ldq_5_bits_uop_is_rvc; // @[lsu.scala:208:16] reg [39:0] ldq_5_bits_uop_debug_pc; // @[lsu.scala:208:16] reg [2:0] ldq_5_bits_uop_iq_type; // @[lsu.scala:208:16] reg [9:0] ldq_5_bits_uop_fu_code; // @[lsu.scala:208:16] reg [3:0] ldq_5_bits_uop_ctrl_br_type; // @[lsu.scala:208:16] reg [1:0] ldq_5_bits_uop_ctrl_op1_sel; // @[lsu.scala:208:16] reg [2:0] ldq_5_bits_uop_ctrl_op2_sel; // @[lsu.scala:208:16] reg [2:0] ldq_5_bits_uop_ctrl_imm_sel; // @[lsu.scala:208:16] reg [4:0] ldq_5_bits_uop_ctrl_op_fcn; // @[lsu.scala:208:16] reg ldq_5_bits_uop_ctrl_fcn_dw; // @[lsu.scala:208:16] reg [2:0] ldq_5_bits_uop_ctrl_csr_cmd; // @[lsu.scala:208:16] reg ldq_5_bits_uop_ctrl_is_load; // @[lsu.scala:208:16] reg ldq_5_bits_uop_ctrl_is_sta; // @[lsu.scala:208:16] reg ldq_5_bits_uop_ctrl_is_std; // @[lsu.scala:208:16] reg [1:0] ldq_5_bits_uop_iw_state; // @[lsu.scala:208:16] reg ldq_5_bits_uop_iw_p1_poisoned; // @[lsu.scala:208:16] reg ldq_5_bits_uop_iw_p2_poisoned; // @[lsu.scala:208:16] reg ldq_5_bits_uop_is_br; // @[lsu.scala:208:16] reg ldq_5_bits_uop_is_jalr; // @[lsu.scala:208:16] reg ldq_5_bits_uop_is_jal; // @[lsu.scala:208:16] reg ldq_5_bits_uop_is_sfb; // @[lsu.scala:208:16] reg [7:0] ldq_5_bits_uop_br_mask; // @[lsu.scala:208:16] reg [2:0] ldq_5_bits_uop_br_tag; // @[lsu.scala:208:16] reg [3:0] ldq_5_bits_uop_ftq_idx; // @[lsu.scala:208:16] reg ldq_5_bits_uop_edge_inst; // @[lsu.scala:208:16] reg [5:0] ldq_5_bits_uop_pc_lob; // @[lsu.scala:208:16] reg ldq_5_bits_uop_taken; // @[lsu.scala:208:16] reg [19:0] ldq_5_bits_uop_imm_packed; // @[lsu.scala:208:16] reg [11:0] ldq_5_bits_uop_csr_addr; // @[lsu.scala:208:16] reg [4:0] ldq_5_bits_uop_rob_idx; // @[lsu.scala:208:16] reg [2:0] ldq_5_bits_uop_ldq_idx; // @[lsu.scala:208:16] reg [2:0] ldq_5_bits_uop_stq_idx; // @[lsu.scala:208:16] reg [1:0] ldq_5_bits_uop_rxq_idx; // @[lsu.scala:208:16] reg [5:0] ldq_5_bits_uop_pdst; // @[lsu.scala:208:16] reg [5:0] ldq_5_bits_uop_prs1; // @[lsu.scala:208:16] reg [5:0] ldq_5_bits_uop_prs2; // @[lsu.scala:208:16] reg [5:0] ldq_5_bits_uop_prs3; // @[lsu.scala:208:16] reg ldq_5_bits_uop_prs1_busy; // @[lsu.scala:208:16] reg ldq_5_bits_uop_prs2_busy; // @[lsu.scala:208:16] reg ldq_5_bits_uop_prs3_busy; // @[lsu.scala:208:16] reg [5:0] ldq_5_bits_uop_stale_pdst; // @[lsu.scala:208:16] reg ldq_5_bits_uop_exception; // @[lsu.scala:208:16] reg [63:0] ldq_5_bits_uop_exc_cause; // @[lsu.scala:208:16] reg ldq_5_bits_uop_bypassable; // @[lsu.scala:208:16] reg [4:0] ldq_5_bits_uop_mem_cmd; // @[lsu.scala:208:16] reg [1:0] ldq_5_bits_uop_mem_size; // @[lsu.scala:208:16] reg ldq_5_bits_uop_mem_signed; // @[lsu.scala:208:16] reg ldq_5_bits_uop_is_fence; // @[lsu.scala:208:16] reg ldq_5_bits_uop_is_fencei; // @[lsu.scala:208:16] reg ldq_5_bits_uop_is_amo; // @[lsu.scala:208:16] reg ldq_5_bits_uop_uses_ldq; // @[lsu.scala:208:16] reg ldq_5_bits_uop_uses_stq; // @[lsu.scala:208:16] reg ldq_5_bits_uop_is_sys_pc2epc; // @[lsu.scala:208:16] reg ldq_5_bits_uop_is_unique; // @[lsu.scala:208:16] reg ldq_5_bits_uop_flush_on_commit; // @[lsu.scala:208:16] reg ldq_5_bits_uop_ldst_is_rs1; // @[lsu.scala:208:16] reg [5:0] ldq_5_bits_uop_ldst; // @[lsu.scala:208:16] reg [5:0] ldq_5_bits_uop_lrs1; // @[lsu.scala:208:16] reg [5:0] ldq_5_bits_uop_lrs2; // @[lsu.scala:208:16] reg [5:0] ldq_5_bits_uop_lrs3; // @[lsu.scala:208:16] reg ldq_5_bits_uop_ldst_val; // @[lsu.scala:208:16] reg [1:0] ldq_5_bits_uop_dst_rtype; // @[lsu.scala:208:16] reg [1:0] ldq_5_bits_uop_lrs1_rtype; // @[lsu.scala:208:16] reg [1:0] ldq_5_bits_uop_lrs2_rtype; // @[lsu.scala:208:16] reg ldq_5_bits_uop_frs3_en; // @[lsu.scala:208:16] reg ldq_5_bits_uop_fp_val; // @[lsu.scala:208:16] reg ldq_5_bits_uop_fp_single; // @[lsu.scala:208:16] reg ldq_5_bits_uop_xcpt_pf_if; // @[lsu.scala:208:16] reg ldq_5_bits_uop_xcpt_ae_if; // @[lsu.scala:208:16] reg ldq_5_bits_uop_xcpt_ma_if; // @[lsu.scala:208:16] reg ldq_5_bits_uop_bp_debug_if; // @[lsu.scala:208:16] reg ldq_5_bits_uop_bp_xcpt_if; // @[lsu.scala:208:16] reg [1:0] ldq_5_bits_uop_debug_fsrc; // @[lsu.scala:208:16] reg [1:0] ldq_5_bits_uop_debug_tsrc; // @[lsu.scala:208:16] reg ldq_5_bits_addr_valid; // @[lsu.scala:208:16] reg [39:0] ldq_5_bits_addr_bits; // @[lsu.scala:208:16] reg ldq_5_bits_addr_is_virtual; // @[lsu.scala:208:16] reg ldq_5_bits_addr_is_uncacheable; // @[lsu.scala:208:16] reg ldq_5_bits_executed; // @[lsu.scala:208:16] reg ldq_5_bits_succeeded; // @[lsu.scala:208:16] reg ldq_5_bits_order_fail; // @[lsu.scala:208:16] reg ldq_5_bits_observed; // @[lsu.scala:208:16] reg [7:0] ldq_5_bits_st_dep_mask; // @[lsu.scala:208:16] reg [2:0] ldq_5_bits_youngest_stq_idx; // @[lsu.scala:208:16] reg ldq_5_bits_forward_std_val; // @[lsu.scala:208:16] reg [2:0] ldq_5_bits_forward_stq_idx; // @[lsu.scala:208:16] reg [63:0] ldq_5_bits_debug_wb_data; // @[lsu.scala:208:16] reg ldq_6_valid; // @[lsu.scala:208:16] reg [6:0] ldq_6_bits_uop_uopc; // @[lsu.scala:208:16] reg [31:0] ldq_6_bits_uop_inst; // @[lsu.scala:208:16] reg [31:0] ldq_6_bits_uop_debug_inst; // @[lsu.scala:208:16] reg ldq_6_bits_uop_is_rvc; // @[lsu.scala:208:16] reg [39:0] ldq_6_bits_uop_debug_pc; // @[lsu.scala:208:16] reg [2:0] ldq_6_bits_uop_iq_type; // @[lsu.scala:208:16] reg [9:0] ldq_6_bits_uop_fu_code; // @[lsu.scala:208:16] reg [3:0] ldq_6_bits_uop_ctrl_br_type; // @[lsu.scala:208:16] reg [1:0] ldq_6_bits_uop_ctrl_op1_sel; // @[lsu.scala:208:16] reg [2:0] ldq_6_bits_uop_ctrl_op2_sel; // @[lsu.scala:208:16] reg [2:0] ldq_6_bits_uop_ctrl_imm_sel; // @[lsu.scala:208:16] reg [4:0] ldq_6_bits_uop_ctrl_op_fcn; // @[lsu.scala:208:16] reg ldq_6_bits_uop_ctrl_fcn_dw; // @[lsu.scala:208:16] reg [2:0] ldq_6_bits_uop_ctrl_csr_cmd; // @[lsu.scala:208:16] reg ldq_6_bits_uop_ctrl_is_load; // @[lsu.scala:208:16] reg ldq_6_bits_uop_ctrl_is_sta; // @[lsu.scala:208:16] reg ldq_6_bits_uop_ctrl_is_std; // @[lsu.scala:208:16] reg [1:0] ldq_6_bits_uop_iw_state; // @[lsu.scala:208:16] reg ldq_6_bits_uop_iw_p1_poisoned; // @[lsu.scala:208:16] reg ldq_6_bits_uop_iw_p2_poisoned; // @[lsu.scala:208:16] reg ldq_6_bits_uop_is_br; // @[lsu.scala:208:16] reg ldq_6_bits_uop_is_jalr; // @[lsu.scala:208:16] reg ldq_6_bits_uop_is_jal; // @[lsu.scala:208:16] reg ldq_6_bits_uop_is_sfb; // @[lsu.scala:208:16] reg [7:0] ldq_6_bits_uop_br_mask; // @[lsu.scala:208:16] reg [2:0] ldq_6_bits_uop_br_tag; // @[lsu.scala:208:16] reg [3:0] ldq_6_bits_uop_ftq_idx; // @[lsu.scala:208:16] reg ldq_6_bits_uop_edge_inst; // @[lsu.scala:208:16] reg [5:0] ldq_6_bits_uop_pc_lob; // @[lsu.scala:208:16] reg ldq_6_bits_uop_taken; // @[lsu.scala:208:16] reg [19:0] ldq_6_bits_uop_imm_packed; // @[lsu.scala:208:16] reg [11:0] ldq_6_bits_uop_csr_addr; // @[lsu.scala:208:16] reg [4:0] ldq_6_bits_uop_rob_idx; // @[lsu.scala:208:16] reg [2:0] ldq_6_bits_uop_ldq_idx; // @[lsu.scala:208:16] reg [2:0] ldq_6_bits_uop_stq_idx; // @[lsu.scala:208:16] reg [1:0] ldq_6_bits_uop_rxq_idx; // @[lsu.scala:208:16] reg [5:0] ldq_6_bits_uop_pdst; // @[lsu.scala:208:16] reg [5:0] ldq_6_bits_uop_prs1; // @[lsu.scala:208:16] reg [5:0] ldq_6_bits_uop_prs2; // @[lsu.scala:208:16] reg [5:0] ldq_6_bits_uop_prs3; // @[lsu.scala:208:16] reg ldq_6_bits_uop_prs1_busy; // @[lsu.scala:208:16] reg ldq_6_bits_uop_prs2_busy; // @[lsu.scala:208:16] reg ldq_6_bits_uop_prs3_busy; // @[lsu.scala:208:16] reg [5:0] ldq_6_bits_uop_stale_pdst; // @[lsu.scala:208:16] reg ldq_6_bits_uop_exception; // @[lsu.scala:208:16] reg [63:0] ldq_6_bits_uop_exc_cause; // @[lsu.scala:208:16] reg ldq_6_bits_uop_bypassable; // @[lsu.scala:208:16] reg [4:0] ldq_6_bits_uop_mem_cmd; // @[lsu.scala:208:16] reg [1:0] ldq_6_bits_uop_mem_size; // @[lsu.scala:208:16] reg ldq_6_bits_uop_mem_signed; // @[lsu.scala:208:16] reg ldq_6_bits_uop_is_fence; // @[lsu.scala:208:16] reg ldq_6_bits_uop_is_fencei; // @[lsu.scala:208:16] reg ldq_6_bits_uop_is_amo; // @[lsu.scala:208:16] reg ldq_6_bits_uop_uses_ldq; // @[lsu.scala:208:16] reg ldq_6_bits_uop_uses_stq; // @[lsu.scala:208:16] reg ldq_6_bits_uop_is_sys_pc2epc; // @[lsu.scala:208:16] reg ldq_6_bits_uop_is_unique; // @[lsu.scala:208:16] reg ldq_6_bits_uop_flush_on_commit; // @[lsu.scala:208:16] reg ldq_6_bits_uop_ldst_is_rs1; // @[lsu.scala:208:16] reg [5:0] ldq_6_bits_uop_ldst; // @[lsu.scala:208:16] reg [5:0] ldq_6_bits_uop_lrs1; // @[lsu.scala:208:16] reg [5:0] ldq_6_bits_uop_lrs2; // @[lsu.scala:208:16] reg [5:0] ldq_6_bits_uop_lrs3; // @[lsu.scala:208:16] reg ldq_6_bits_uop_ldst_val; // @[lsu.scala:208:16] reg [1:0] ldq_6_bits_uop_dst_rtype; // @[lsu.scala:208:16] reg [1:0] ldq_6_bits_uop_lrs1_rtype; // @[lsu.scala:208:16] reg [1:0] ldq_6_bits_uop_lrs2_rtype; // @[lsu.scala:208:16] reg ldq_6_bits_uop_frs3_en; // @[lsu.scala:208:16] reg ldq_6_bits_uop_fp_val; // @[lsu.scala:208:16] reg ldq_6_bits_uop_fp_single; // @[lsu.scala:208:16] reg ldq_6_bits_uop_xcpt_pf_if; // @[lsu.scala:208:16] reg ldq_6_bits_uop_xcpt_ae_if; // @[lsu.scala:208:16] reg ldq_6_bits_uop_xcpt_ma_if; // @[lsu.scala:208:16] reg ldq_6_bits_uop_bp_debug_if; // @[lsu.scala:208:16] reg ldq_6_bits_uop_bp_xcpt_if; // @[lsu.scala:208:16] reg [1:0] ldq_6_bits_uop_debug_fsrc; // @[lsu.scala:208:16] reg [1:0] ldq_6_bits_uop_debug_tsrc; // @[lsu.scala:208:16] reg ldq_6_bits_addr_valid; // @[lsu.scala:208:16] reg [39:0] ldq_6_bits_addr_bits; // @[lsu.scala:208:16] reg ldq_6_bits_addr_is_virtual; // @[lsu.scala:208:16] reg ldq_6_bits_addr_is_uncacheable; // @[lsu.scala:208:16] reg ldq_6_bits_executed; // @[lsu.scala:208:16] reg ldq_6_bits_succeeded; // @[lsu.scala:208:16] reg ldq_6_bits_order_fail; // @[lsu.scala:208:16] reg ldq_6_bits_observed; // @[lsu.scala:208:16] reg [7:0] ldq_6_bits_st_dep_mask; // @[lsu.scala:208:16] reg [2:0] ldq_6_bits_youngest_stq_idx; // @[lsu.scala:208:16] reg ldq_6_bits_forward_std_val; // @[lsu.scala:208:16] reg [2:0] ldq_6_bits_forward_stq_idx; // @[lsu.scala:208:16] reg [63:0] ldq_6_bits_debug_wb_data; // @[lsu.scala:208:16] reg ldq_7_valid; // @[lsu.scala:208:16] reg [6:0] ldq_7_bits_uop_uopc; // @[lsu.scala:208:16] reg [31:0] ldq_7_bits_uop_inst; // @[lsu.scala:208:16] reg [31:0] ldq_7_bits_uop_debug_inst; // @[lsu.scala:208:16] reg ldq_7_bits_uop_is_rvc; // @[lsu.scala:208:16] reg [39:0] ldq_7_bits_uop_debug_pc; // @[lsu.scala:208:16] reg [2:0] ldq_7_bits_uop_iq_type; // @[lsu.scala:208:16] reg [9:0] ldq_7_bits_uop_fu_code; // @[lsu.scala:208:16] reg [3:0] ldq_7_bits_uop_ctrl_br_type; // @[lsu.scala:208:16] reg [1:0] ldq_7_bits_uop_ctrl_op1_sel; // @[lsu.scala:208:16] reg [2:0] ldq_7_bits_uop_ctrl_op2_sel; // @[lsu.scala:208:16] reg [2:0] ldq_7_bits_uop_ctrl_imm_sel; // @[lsu.scala:208:16] reg [4:0] ldq_7_bits_uop_ctrl_op_fcn; // @[lsu.scala:208:16] reg ldq_7_bits_uop_ctrl_fcn_dw; // @[lsu.scala:208:16] reg [2:0] ldq_7_bits_uop_ctrl_csr_cmd; // @[lsu.scala:208:16] reg ldq_7_bits_uop_ctrl_is_load; // @[lsu.scala:208:16] reg ldq_7_bits_uop_ctrl_is_sta; // @[lsu.scala:208:16] reg ldq_7_bits_uop_ctrl_is_std; // @[lsu.scala:208:16] reg [1:0] ldq_7_bits_uop_iw_state; // @[lsu.scala:208:16] reg ldq_7_bits_uop_iw_p1_poisoned; // @[lsu.scala:208:16] reg ldq_7_bits_uop_iw_p2_poisoned; // @[lsu.scala:208:16] reg ldq_7_bits_uop_is_br; // @[lsu.scala:208:16] reg ldq_7_bits_uop_is_jalr; // @[lsu.scala:208:16] reg ldq_7_bits_uop_is_jal; // @[lsu.scala:208:16] reg ldq_7_bits_uop_is_sfb; // @[lsu.scala:208:16] reg [7:0] ldq_7_bits_uop_br_mask; // @[lsu.scala:208:16] reg [2:0] ldq_7_bits_uop_br_tag; // @[lsu.scala:208:16] reg [3:0] ldq_7_bits_uop_ftq_idx; // @[lsu.scala:208:16] reg ldq_7_bits_uop_edge_inst; // @[lsu.scala:208:16] reg [5:0] ldq_7_bits_uop_pc_lob; // @[lsu.scala:208:16] reg ldq_7_bits_uop_taken; // @[lsu.scala:208:16] reg [19:0] ldq_7_bits_uop_imm_packed; // @[lsu.scala:208:16] reg [11:0] ldq_7_bits_uop_csr_addr; // @[lsu.scala:208:16] reg [4:0] ldq_7_bits_uop_rob_idx; // @[lsu.scala:208:16] reg [2:0] ldq_7_bits_uop_ldq_idx; // @[lsu.scala:208:16] reg [2:0] ldq_7_bits_uop_stq_idx; // @[lsu.scala:208:16] reg [1:0] ldq_7_bits_uop_rxq_idx; // @[lsu.scala:208:16] reg [5:0] ldq_7_bits_uop_pdst; // @[lsu.scala:208:16] reg [5:0] ldq_7_bits_uop_prs1; // @[lsu.scala:208:16] reg [5:0] ldq_7_bits_uop_prs2; // @[lsu.scala:208:16] reg [5:0] ldq_7_bits_uop_prs3; // @[lsu.scala:208:16] reg ldq_7_bits_uop_prs1_busy; // @[lsu.scala:208:16] reg ldq_7_bits_uop_prs2_busy; // @[lsu.scala:208:16] reg ldq_7_bits_uop_prs3_busy; // @[lsu.scala:208:16] reg [5:0] ldq_7_bits_uop_stale_pdst; // @[lsu.scala:208:16] reg ldq_7_bits_uop_exception; // @[lsu.scala:208:16] reg [63:0] ldq_7_bits_uop_exc_cause; // @[lsu.scala:208:16] reg ldq_7_bits_uop_bypassable; // @[lsu.scala:208:16] reg [4:0] ldq_7_bits_uop_mem_cmd; // @[lsu.scala:208:16] reg [1:0] ldq_7_bits_uop_mem_size; // @[lsu.scala:208:16] reg ldq_7_bits_uop_mem_signed; // @[lsu.scala:208:16] reg ldq_7_bits_uop_is_fence; // @[lsu.scala:208:16] reg ldq_7_bits_uop_is_fencei; // @[lsu.scala:208:16] reg ldq_7_bits_uop_is_amo; // @[lsu.scala:208:16] reg ldq_7_bits_uop_uses_ldq; // @[lsu.scala:208:16] reg ldq_7_bits_uop_uses_stq; // @[lsu.scala:208:16] reg ldq_7_bits_uop_is_sys_pc2epc; // @[lsu.scala:208:16] reg ldq_7_bits_uop_is_unique; // @[lsu.scala:208:16] reg ldq_7_bits_uop_flush_on_commit; // @[lsu.scala:208:16] reg ldq_7_bits_uop_ldst_is_rs1; // @[lsu.scala:208:16] reg [5:0] ldq_7_bits_uop_ldst; // @[lsu.scala:208:16] reg [5:0] ldq_7_bits_uop_lrs1; // @[lsu.scala:208:16] reg [5:0] ldq_7_bits_uop_lrs2; // @[lsu.scala:208:16] reg [5:0] ldq_7_bits_uop_lrs3; // @[lsu.scala:208:16] reg ldq_7_bits_uop_ldst_val; // @[lsu.scala:208:16] reg [1:0] ldq_7_bits_uop_dst_rtype; // @[lsu.scala:208:16] reg [1:0] ldq_7_bits_uop_lrs1_rtype; // @[lsu.scala:208:16] reg [1:0] ldq_7_bits_uop_lrs2_rtype; // @[lsu.scala:208:16] reg ldq_7_bits_uop_frs3_en; // @[lsu.scala:208:16] reg ldq_7_bits_uop_fp_val; // @[lsu.scala:208:16] reg ldq_7_bits_uop_fp_single; // @[lsu.scala:208:16] reg ldq_7_bits_uop_xcpt_pf_if; // @[lsu.scala:208:16] reg ldq_7_bits_uop_xcpt_ae_if; // @[lsu.scala:208:16] reg ldq_7_bits_uop_xcpt_ma_if; // @[lsu.scala:208:16] reg ldq_7_bits_uop_bp_debug_if; // @[lsu.scala:208:16] reg ldq_7_bits_uop_bp_xcpt_if; // @[lsu.scala:208:16] reg [1:0] ldq_7_bits_uop_debug_fsrc; // @[lsu.scala:208:16] reg [1:0] ldq_7_bits_uop_debug_tsrc; // @[lsu.scala:208:16] reg ldq_7_bits_addr_valid; // @[lsu.scala:208:16] reg [39:0] ldq_7_bits_addr_bits; // @[lsu.scala:208:16] reg ldq_7_bits_addr_is_virtual; // @[lsu.scala:208:16] reg ldq_7_bits_addr_is_uncacheable; // @[lsu.scala:208:16] reg ldq_7_bits_executed; // @[lsu.scala:208:16] reg ldq_7_bits_succeeded; // @[lsu.scala:208:16] reg ldq_7_bits_order_fail; // @[lsu.scala:208:16] reg ldq_7_bits_observed; // @[lsu.scala:208:16] reg [7:0] ldq_7_bits_st_dep_mask; // @[lsu.scala:208:16] reg [2:0] ldq_7_bits_youngest_stq_idx; // @[lsu.scala:208:16] reg ldq_7_bits_forward_std_val; // @[lsu.scala:208:16] reg [2:0] ldq_7_bits_forward_stq_idx; // @[lsu.scala:208:16] reg [63:0] ldq_7_bits_debug_wb_data; // @[lsu.scala:208:16] reg stq_0_valid; // @[lsu.scala:209:16] reg [6:0] stq_0_bits_uop_uopc; // @[lsu.scala:209:16] reg [31:0] stq_0_bits_uop_inst; // @[lsu.scala:209:16] reg [31:0] stq_0_bits_uop_debug_inst; // @[lsu.scala:209:16] reg stq_0_bits_uop_is_rvc; // @[lsu.scala:209:16] reg [39:0] stq_0_bits_uop_debug_pc; // @[lsu.scala:209:16] reg [2:0] stq_0_bits_uop_iq_type; // @[lsu.scala:209:16] reg [9:0] stq_0_bits_uop_fu_code; // @[lsu.scala:209:16] reg [3:0] stq_0_bits_uop_ctrl_br_type; // @[lsu.scala:209:16] reg [1:0] stq_0_bits_uop_ctrl_op1_sel; // @[lsu.scala:209:16] reg [2:0] stq_0_bits_uop_ctrl_op2_sel; // @[lsu.scala:209:16] reg [2:0] stq_0_bits_uop_ctrl_imm_sel; // @[lsu.scala:209:16] reg [4:0] stq_0_bits_uop_ctrl_op_fcn; // @[lsu.scala:209:16] reg stq_0_bits_uop_ctrl_fcn_dw; // @[lsu.scala:209:16] reg [2:0] stq_0_bits_uop_ctrl_csr_cmd; // @[lsu.scala:209:16] reg stq_0_bits_uop_ctrl_is_load; // @[lsu.scala:209:16] reg stq_0_bits_uop_ctrl_is_sta; // @[lsu.scala:209:16] reg stq_0_bits_uop_ctrl_is_std; // @[lsu.scala:209:16] reg [1:0] stq_0_bits_uop_iw_state; // @[lsu.scala:209:16] reg stq_0_bits_uop_iw_p1_poisoned; // @[lsu.scala:209:16] reg stq_0_bits_uop_iw_p2_poisoned; // @[lsu.scala:209:16] reg stq_0_bits_uop_is_br; // @[lsu.scala:209:16] reg stq_0_bits_uop_is_jalr; // @[lsu.scala:209:16] reg stq_0_bits_uop_is_jal; // @[lsu.scala:209:16] reg stq_0_bits_uop_is_sfb; // @[lsu.scala:209:16] reg [7:0] stq_0_bits_uop_br_mask; // @[lsu.scala:209:16] reg [2:0] stq_0_bits_uop_br_tag; // @[lsu.scala:209:16] reg [3:0] stq_0_bits_uop_ftq_idx; // @[lsu.scala:209:16] reg stq_0_bits_uop_edge_inst; // @[lsu.scala:209:16] reg [5:0] stq_0_bits_uop_pc_lob; // @[lsu.scala:209:16] reg stq_0_bits_uop_taken; // @[lsu.scala:209:16] reg [19:0] stq_0_bits_uop_imm_packed; // @[lsu.scala:209:16] reg [11:0] stq_0_bits_uop_csr_addr; // @[lsu.scala:209:16] reg [4:0] stq_0_bits_uop_rob_idx; // @[lsu.scala:209:16] reg [2:0] stq_0_bits_uop_ldq_idx; // @[lsu.scala:209:16] reg [2:0] stq_0_bits_uop_stq_idx; // @[lsu.scala:209:16] reg [1:0] stq_0_bits_uop_rxq_idx; // @[lsu.scala:209:16] reg [5:0] stq_0_bits_uop_pdst; // @[lsu.scala:209:16] reg [5:0] stq_0_bits_uop_prs1; // @[lsu.scala:209:16] reg [5:0] stq_0_bits_uop_prs2; // @[lsu.scala:209:16] reg [5:0] stq_0_bits_uop_prs3; // @[lsu.scala:209:16] reg [3:0] stq_0_bits_uop_ppred; // @[lsu.scala:209:16] reg stq_0_bits_uop_prs1_busy; // @[lsu.scala:209:16] reg stq_0_bits_uop_prs2_busy; // @[lsu.scala:209:16] reg stq_0_bits_uop_prs3_busy; // @[lsu.scala:209:16] reg stq_0_bits_uop_ppred_busy; // @[lsu.scala:209:16] reg [5:0] stq_0_bits_uop_stale_pdst; // @[lsu.scala:209:16] reg stq_0_bits_uop_exception; // @[lsu.scala:209:16] reg [63:0] stq_0_bits_uop_exc_cause; // @[lsu.scala:209:16] reg stq_0_bits_uop_bypassable; // @[lsu.scala:209:16] reg [4:0] stq_0_bits_uop_mem_cmd; // @[lsu.scala:209:16] reg [1:0] stq_0_bits_uop_mem_size; // @[lsu.scala:209:16] reg stq_0_bits_uop_mem_signed; // @[lsu.scala:209:16] reg stq_0_bits_uop_is_fence; // @[lsu.scala:209:16] reg stq_0_bits_uop_is_fencei; // @[lsu.scala:209:16] reg stq_0_bits_uop_is_amo; // @[lsu.scala:209:16] reg stq_0_bits_uop_uses_ldq; // @[lsu.scala:209:16] reg stq_0_bits_uop_uses_stq; // @[lsu.scala:209:16] reg stq_0_bits_uop_is_sys_pc2epc; // @[lsu.scala:209:16] reg stq_0_bits_uop_is_unique; // @[lsu.scala:209:16] reg stq_0_bits_uop_flush_on_commit; // @[lsu.scala:209:16] reg stq_0_bits_uop_ldst_is_rs1; // @[lsu.scala:209:16] reg [5:0] stq_0_bits_uop_ldst; // @[lsu.scala:209:16] reg [5:0] stq_0_bits_uop_lrs1; // @[lsu.scala:209:16] reg [5:0] stq_0_bits_uop_lrs2; // @[lsu.scala:209:16] reg [5:0] stq_0_bits_uop_lrs3; // @[lsu.scala:209:16] reg stq_0_bits_uop_ldst_val; // @[lsu.scala:209:16] reg [1:0] stq_0_bits_uop_dst_rtype; // @[lsu.scala:209:16] reg [1:0] stq_0_bits_uop_lrs1_rtype; // @[lsu.scala:209:16] reg [1:0] stq_0_bits_uop_lrs2_rtype; // @[lsu.scala:209:16] reg stq_0_bits_uop_frs3_en; // @[lsu.scala:209:16] reg stq_0_bits_uop_fp_val; // @[lsu.scala:209:16] reg stq_0_bits_uop_fp_single; // @[lsu.scala:209:16] reg stq_0_bits_uop_xcpt_pf_if; // @[lsu.scala:209:16] reg stq_0_bits_uop_xcpt_ae_if; // @[lsu.scala:209:16] reg stq_0_bits_uop_xcpt_ma_if; // @[lsu.scala:209:16] reg stq_0_bits_uop_bp_debug_if; // @[lsu.scala:209:16] reg stq_0_bits_uop_bp_xcpt_if; // @[lsu.scala:209:16] reg [1:0] stq_0_bits_uop_debug_fsrc; // @[lsu.scala:209:16] reg [1:0] stq_0_bits_uop_debug_tsrc; // @[lsu.scala:209:16] reg stq_0_bits_addr_valid; // @[lsu.scala:209:16] reg [39:0] stq_0_bits_addr_bits; // @[lsu.scala:209:16] reg stq_0_bits_addr_is_virtual; // @[lsu.scala:209:16] reg stq_0_bits_data_valid; // @[lsu.scala:209:16] reg [63:0] stq_0_bits_data_bits; // @[lsu.scala:209:16] reg stq_0_bits_committed; // @[lsu.scala:209:16] reg stq_0_bits_succeeded; // @[lsu.scala:209:16] reg [63:0] stq_0_bits_debug_wb_data; // @[lsu.scala:209:16] reg stq_1_valid; // @[lsu.scala:209:16] reg [6:0] stq_1_bits_uop_uopc; // @[lsu.scala:209:16] reg [31:0] stq_1_bits_uop_inst; // @[lsu.scala:209:16] reg [31:0] stq_1_bits_uop_debug_inst; // @[lsu.scala:209:16] reg stq_1_bits_uop_is_rvc; // @[lsu.scala:209:16] reg [39:0] stq_1_bits_uop_debug_pc; // @[lsu.scala:209:16] reg [2:0] stq_1_bits_uop_iq_type; // @[lsu.scala:209:16] reg [9:0] stq_1_bits_uop_fu_code; // @[lsu.scala:209:16] reg [3:0] stq_1_bits_uop_ctrl_br_type; // @[lsu.scala:209:16] reg [1:0] stq_1_bits_uop_ctrl_op1_sel; // @[lsu.scala:209:16] reg [2:0] stq_1_bits_uop_ctrl_op2_sel; // @[lsu.scala:209:16] reg [2:0] stq_1_bits_uop_ctrl_imm_sel; // @[lsu.scala:209:16] reg [4:0] stq_1_bits_uop_ctrl_op_fcn; // @[lsu.scala:209:16] reg stq_1_bits_uop_ctrl_fcn_dw; // @[lsu.scala:209:16] reg [2:0] stq_1_bits_uop_ctrl_csr_cmd; // @[lsu.scala:209:16] reg stq_1_bits_uop_ctrl_is_load; // @[lsu.scala:209:16] reg stq_1_bits_uop_ctrl_is_sta; // @[lsu.scala:209:16] reg stq_1_bits_uop_ctrl_is_std; // @[lsu.scala:209:16] reg [1:0] stq_1_bits_uop_iw_state; // @[lsu.scala:209:16] reg stq_1_bits_uop_iw_p1_poisoned; // @[lsu.scala:209:16] reg stq_1_bits_uop_iw_p2_poisoned; // @[lsu.scala:209:16] reg stq_1_bits_uop_is_br; // @[lsu.scala:209:16] reg stq_1_bits_uop_is_jalr; // @[lsu.scala:209:16] reg stq_1_bits_uop_is_jal; // @[lsu.scala:209:16] reg stq_1_bits_uop_is_sfb; // @[lsu.scala:209:16] reg [7:0] stq_1_bits_uop_br_mask; // @[lsu.scala:209:16] reg [2:0] stq_1_bits_uop_br_tag; // @[lsu.scala:209:16] reg [3:0] stq_1_bits_uop_ftq_idx; // @[lsu.scala:209:16] reg stq_1_bits_uop_edge_inst; // @[lsu.scala:209:16] reg [5:0] stq_1_bits_uop_pc_lob; // @[lsu.scala:209:16] reg stq_1_bits_uop_taken; // @[lsu.scala:209:16] reg [19:0] stq_1_bits_uop_imm_packed; // @[lsu.scala:209:16] reg [11:0] stq_1_bits_uop_csr_addr; // @[lsu.scala:209:16] reg [4:0] stq_1_bits_uop_rob_idx; // @[lsu.scala:209:16] reg [2:0] stq_1_bits_uop_ldq_idx; // @[lsu.scala:209:16] reg [2:0] stq_1_bits_uop_stq_idx; // @[lsu.scala:209:16] reg [1:0] stq_1_bits_uop_rxq_idx; // @[lsu.scala:209:16] reg [5:0] stq_1_bits_uop_pdst; // @[lsu.scala:209:16] reg [5:0] stq_1_bits_uop_prs1; // @[lsu.scala:209:16] reg [5:0] stq_1_bits_uop_prs2; // @[lsu.scala:209:16] reg [5:0] stq_1_bits_uop_prs3; // @[lsu.scala:209:16] reg [3:0] stq_1_bits_uop_ppred; // @[lsu.scala:209:16] reg stq_1_bits_uop_prs1_busy; // @[lsu.scala:209:16] reg stq_1_bits_uop_prs2_busy; // @[lsu.scala:209:16] reg stq_1_bits_uop_prs3_busy; // @[lsu.scala:209:16] reg stq_1_bits_uop_ppred_busy; // @[lsu.scala:209:16] reg [5:0] stq_1_bits_uop_stale_pdst; // @[lsu.scala:209:16] reg stq_1_bits_uop_exception; // @[lsu.scala:209:16] reg [63:0] stq_1_bits_uop_exc_cause; // @[lsu.scala:209:16] reg stq_1_bits_uop_bypassable; // @[lsu.scala:209:16] reg [4:0] stq_1_bits_uop_mem_cmd; // @[lsu.scala:209:16] reg [1:0] stq_1_bits_uop_mem_size; // @[lsu.scala:209:16] reg stq_1_bits_uop_mem_signed; // @[lsu.scala:209:16] reg stq_1_bits_uop_is_fence; // @[lsu.scala:209:16] reg stq_1_bits_uop_is_fencei; // @[lsu.scala:209:16] reg stq_1_bits_uop_is_amo; // @[lsu.scala:209:16] reg stq_1_bits_uop_uses_ldq; // @[lsu.scala:209:16] reg stq_1_bits_uop_uses_stq; // @[lsu.scala:209:16] reg stq_1_bits_uop_is_sys_pc2epc; // @[lsu.scala:209:16] reg stq_1_bits_uop_is_unique; // @[lsu.scala:209:16] reg stq_1_bits_uop_flush_on_commit; // @[lsu.scala:209:16] reg stq_1_bits_uop_ldst_is_rs1; // @[lsu.scala:209:16] reg [5:0] stq_1_bits_uop_ldst; // @[lsu.scala:209:16] reg [5:0] stq_1_bits_uop_lrs1; // @[lsu.scala:209:16] reg [5:0] stq_1_bits_uop_lrs2; // @[lsu.scala:209:16] reg [5:0] stq_1_bits_uop_lrs3; // @[lsu.scala:209:16] reg stq_1_bits_uop_ldst_val; // @[lsu.scala:209:16] reg [1:0] stq_1_bits_uop_dst_rtype; // @[lsu.scala:209:16] reg [1:0] stq_1_bits_uop_lrs1_rtype; // @[lsu.scala:209:16] reg [1:0] stq_1_bits_uop_lrs2_rtype; // @[lsu.scala:209:16] reg stq_1_bits_uop_frs3_en; // @[lsu.scala:209:16] reg stq_1_bits_uop_fp_val; // @[lsu.scala:209:16] reg stq_1_bits_uop_fp_single; // @[lsu.scala:209:16] reg stq_1_bits_uop_xcpt_pf_if; // @[lsu.scala:209:16] reg stq_1_bits_uop_xcpt_ae_if; // @[lsu.scala:209:16] reg stq_1_bits_uop_xcpt_ma_if; // @[lsu.scala:209:16] reg stq_1_bits_uop_bp_debug_if; // @[lsu.scala:209:16] reg stq_1_bits_uop_bp_xcpt_if; // @[lsu.scala:209:16] reg [1:0] stq_1_bits_uop_debug_fsrc; // @[lsu.scala:209:16] reg [1:0] stq_1_bits_uop_debug_tsrc; // @[lsu.scala:209:16] reg stq_1_bits_addr_valid; // @[lsu.scala:209:16] reg [39:0] stq_1_bits_addr_bits; // @[lsu.scala:209:16] reg stq_1_bits_addr_is_virtual; // @[lsu.scala:209:16] reg stq_1_bits_data_valid; // @[lsu.scala:209:16] reg [63:0] stq_1_bits_data_bits; // @[lsu.scala:209:16] reg stq_1_bits_committed; // @[lsu.scala:209:16] reg stq_1_bits_succeeded; // @[lsu.scala:209:16] reg [63:0] stq_1_bits_debug_wb_data; // @[lsu.scala:209:16] reg stq_2_valid; // @[lsu.scala:209:16] reg [6:0] stq_2_bits_uop_uopc; // @[lsu.scala:209:16] reg [31:0] stq_2_bits_uop_inst; // @[lsu.scala:209:16] reg [31:0] stq_2_bits_uop_debug_inst; // @[lsu.scala:209:16] reg stq_2_bits_uop_is_rvc; // @[lsu.scala:209:16] reg [39:0] stq_2_bits_uop_debug_pc; // @[lsu.scala:209:16] reg [2:0] stq_2_bits_uop_iq_type; // @[lsu.scala:209:16] reg [9:0] stq_2_bits_uop_fu_code; // @[lsu.scala:209:16] reg [3:0] stq_2_bits_uop_ctrl_br_type; // @[lsu.scala:209:16] reg [1:0] stq_2_bits_uop_ctrl_op1_sel; // @[lsu.scala:209:16] reg [2:0] stq_2_bits_uop_ctrl_op2_sel; // @[lsu.scala:209:16] reg [2:0] stq_2_bits_uop_ctrl_imm_sel; // @[lsu.scala:209:16] reg [4:0] stq_2_bits_uop_ctrl_op_fcn; // @[lsu.scala:209:16] reg stq_2_bits_uop_ctrl_fcn_dw; // @[lsu.scala:209:16] reg [2:0] stq_2_bits_uop_ctrl_csr_cmd; // @[lsu.scala:209:16] reg stq_2_bits_uop_ctrl_is_load; // @[lsu.scala:209:16] reg stq_2_bits_uop_ctrl_is_sta; // @[lsu.scala:209:16] reg stq_2_bits_uop_ctrl_is_std; // @[lsu.scala:209:16] reg [1:0] stq_2_bits_uop_iw_state; // @[lsu.scala:209:16] reg stq_2_bits_uop_iw_p1_poisoned; // @[lsu.scala:209:16] reg stq_2_bits_uop_iw_p2_poisoned; // @[lsu.scala:209:16] reg stq_2_bits_uop_is_br; // @[lsu.scala:209:16] reg stq_2_bits_uop_is_jalr; // @[lsu.scala:209:16] reg stq_2_bits_uop_is_jal; // @[lsu.scala:209:16] reg stq_2_bits_uop_is_sfb; // @[lsu.scala:209:16] reg [7:0] stq_2_bits_uop_br_mask; // @[lsu.scala:209:16] reg [2:0] stq_2_bits_uop_br_tag; // @[lsu.scala:209:16] reg [3:0] stq_2_bits_uop_ftq_idx; // @[lsu.scala:209:16] reg stq_2_bits_uop_edge_inst; // @[lsu.scala:209:16] reg [5:0] stq_2_bits_uop_pc_lob; // @[lsu.scala:209:16] reg stq_2_bits_uop_taken; // @[lsu.scala:209:16] reg [19:0] stq_2_bits_uop_imm_packed; // @[lsu.scala:209:16] reg [11:0] stq_2_bits_uop_csr_addr; // @[lsu.scala:209:16] reg [4:0] stq_2_bits_uop_rob_idx; // @[lsu.scala:209:16] reg [2:0] stq_2_bits_uop_ldq_idx; // @[lsu.scala:209:16] reg [2:0] stq_2_bits_uop_stq_idx; // @[lsu.scala:209:16] reg [1:0] stq_2_bits_uop_rxq_idx; // @[lsu.scala:209:16] reg [5:0] stq_2_bits_uop_pdst; // @[lsu.scala:209:16] reg [5:0] stq_2_bits_uop_prs1; // @[lsu.scala:209:16] reg [5:0] stq_2_bits_uop_prs2; // @[lsu.scala:209:16] reg [5:0] stq_2_bits_uop_prs3; // @[lsu.scala:209:16] reg [3:0] stq_2_bits_uop_ppred; // @[lsu.scala:209:16] reg stq_2_bits_uop_prs1_busy; // @[lsu.scala:209:16] reg stq_2_bits_uop_prs2_busy; // @[lsu.scala:209:16] reg stq_2_bits_uop_prs3_busy; // @[lsu.scala:209:16] reg stq_2_bits_uop_ppred_busy; // @[lsu.scala:209:16] reg [5:0] stq_2_bits_uop_stale_pdst; // @[lsu.scala:209:16] reg stq_2_bits_uop_exception; // @[lsu.scala:209:16] reg [63:0] stq_2_bits_uop_exc_cause; // @[lsu.scala:209:16] reg stq_2_bits_uop_bypassable; // @[lsu.scala:209:16] reg [4:0] stq_2_bits_uop_mem_cmd; // @[lsu.scala:209:16] reg [1:0] stq_2_bits_uop_mem_size; // @[lsu.scala:209:16] reg stq_2_bits_uop_mem_signed; // @[lsu.scala:209:16] reg stq_2_bits_uop_is_fence; // @[lsu.scala:209:16] reg stq_2_bits_uop_is_fencei; // @[lsu.scala:209:16] reg stq_2_bits_uop_is_amo; // @[lsu.scala:209:16] reg stq_2_bits_uop_uses_ldq; // @[lsu.scala:209:16] reg stq_2_bits_uop_uses_stq; // @[lsu.scala:209:16] reg stq_2_bits_uop_is_sys_pc2epc; // @[lsu.scala:209:16] reg stq_2_bits_uop_is_unique; // @[lsu.scala:209:16] reg stq_2_bits_uop_flush_on_commit; // @[lsu.scala:209:16] reg stq_2_bits_uop_ldst_is_rs1; // @[lsu.scala:209:16] reg [5:0] stq_2_bits_uop_ldst; // @[lsu.scala:209:16] reg [5:0] stq_2_bits_uop_lrs1; // @[lsu.scala:209:16] reg [5:0] stq_2_bits_uop_lrs2; // @[lsu.scala:209:16] reg [5:0] stq_2_bits_uop_lrs3; // @[lsu.scala:209:16] reg stq_2_bits_uop_ldst_val; // @[lsu.scala:209:16] reg [1:0] stq_2_bits_uop_dst_rtype; // @[lsu.scala:209:16] reg [1:0] stq_2_bits_uop_lrs1_rtype; // @[lsu.scala:209:16] reg [1:0] stq_2_bits_uop_lrs2_rtype; // @[lsu.scala:209:16] reg stq_2_bits_uop_frs3_en; // @[lsu.scala:209:16] reg stq_2_bits_uop_fp_val; // @[lsu.scala:209:16] reg stq_2_bits_uop_fp_single; // @[lsu.scala:209:16] reg stq_2_bits_uop_xcpt_pf_if; // @[lsu.scala:209:16] reg stq_2_bits_uop_xcpt_ae_if; // @[lsu.scala:209:16] reg stq_2_bits_uop_xcpt_ma_if; // @[lsu.scala:209:16] reg stq_2_bits_uop_bp_debug_if; // @[lsu.scala:209:16] reg stq_2_bits_uop_bp_xcpt_if; // @[lsu.scala:209:16] reg [1:0] stq_2_bits_uop_debug_fsrc; // @[lsu.scala:209:16] reg [1:0] stq_2_bits_uop_debug_tsrc; // @[lsu.scala:209:16] reg stq_2_bits_addr_valid; // @[lsu.scala:209:16] reg [39:0] stq_2_bits_addr_bits; // @[lsu.scala:209:16] reg stq_2_bits_addr_is_virtual; // @[lsu.scala:209:16] reg stq_2_bits_data_valid; // @[lsu.scala:209:16] reg [63:0] stq_2_bits_data_bits; // @[lsu.scala:209:16] reg stq_2_bits_committed; // @[lsu.scala:209:16] reg stq_2_bits_succeeded; // @[lsu.scala:209:16] reg [63:0] stq_2_bits_debug_wb_data; // @[lsu.scala:209:16] reg stq_3_valid; // @[lsu.scala:209:16] reg [6:0] stq_3_bits_uop_uopc; // @[lsu.scala:209:16] reg [31:0] stq_3_bits_uop_inst; // @[lsu.scala:209:16] reg [31:0] stq_3_bits_uop_debug_inst; // @[lsu.scala:209:16] reg stq_3_bits_uop_is_rvc; // @[lsu.scala:209:16] reg [39:0] stq_3_bits_uop_debug_pc; // @[lsu.scala:209:16] reg [2:0] stq_3_bits_uop_iq_type; // @[lsu.scala:209:16] reg [9:0] stq_3_bits_uop_fu_code; // @[lsu.scala:209:16] reg [3:0] stq_3_bits_uop_ctrl_br_type; // @[lsu.scala:209:16] reg [1:0] stq_3_bits_uop_ctrl_op1_sel; // @[lsu.scala:209:16] reg [2:0] stq_3_bits_uop_ctrl_op2_sel; // @[lsu.scala:209:16] reg [2:0] stq_3_bits_uop_ctrl_imm_sel; // @[lsu.scala:209:16] reg [4:0] stq_3_bits_uop_ctrl_op_fcn; // @[lsu.scala:209:16] reg stq_3_bits_uop_ctrl_fcn_dw; // @[lsu.scala:209:16] reg [2:0] stq_3_bits_uop_ctrl_csr_cmd; // @[lsu.scala:209:16] reg stq_3_bits_uop_ctrl_is_load; // @[lsu.scala:209:16] reg stq_3_bits_uop_ctrl_is_sta; // @[lsu.scala:209:16] reg stq_3_bits_uop_ctrl_is_std; // @[lsu.scala:209:16] reg [1:0] stq_3_bits_uop_iw_state; // @[lsu.scala:209:16] reg stq_3_bits_uop_iw_p1_poisoned; // @[lsu.scala:209:16] reg stq_3_bits_uop_iw_p2_poisoned; // @[lsu.scala:209:16] reg stq_3_bits_uop_is_br; // @[lsu.scala:209:16] reg stq_3_bits_uop_is_jalr; // @[lsu.scala:209:16] reg stq_3_bits_uop_is_jal; // @[lsu.scala:209:16] reg stq_3_bits_uop_is_sfb; // @[lsu.scala:209:16] reg [7:0] stq_3_bits_uop_br_mask; // @[lsu.scala:209:16] reg [2:0] stq_3_bits_uop_br_tag; // @[lsu.scala:209:16] reg [3:0] stq_3_bits_uop_ftq_idx; // @[lsu.scala:209:16] reg stq_3_bits_uop_edge_inst; // @[lsu.scala:209:16] reg [5:0] stq_3_bits_uop_pc_lob; // @[lsu.scala:209:16] reg stq_3_bits_uop_taken; // @[lsu.scala:209:16] reg [19:0] stq_3_bits_uop_imm_packed; // @[lsu.scala:209:16] reg [11:0] stq_3_bits_uop_csr_addr; // @[lsu.scala:209:16] reg [4:0] stq_3_bits_uop_rob_idx; // @[lsu.scala:209:16] reg [2:0] stq_3_bits_uop_ldq_idx; // @[lsu.scala:209:16] reg [2:0] stq_3_bits_uop_stq_idx; // @[lsu.scala:209:16] reg [1:0] stq_3_bits_uop_rxq_idx; // @[lsu.scala:209:16] reg [5:0] stq_3_bits_uop_pdst; // @[lsu.scala:209:16] reg [5:0] stq_3_bits_uop_prs1; // @[lsu.scala:209:16] reg [5:0] stq_3_bits_uop_prs2; // @[lsu.scala:209:16] reg [5:0] stq_3_bits_uop_prs3; // @[lsu.scala:209:16] reg [3:0] stq_3_bits_uop_ppred; // @[lsu.scala:209:16] reg stq_3_bits_uop_prs1_busy; // @[lsu.scala:209:16] reg stq_3_bits_uop_prs2_busy; // @[lsu.scala:209:16] reg stq_3_bits_uop_prs3_busy; // @[lsu.scala:209:16] reg stq_3_bits_uop_ppred_busy; // @[lsu.scala:209:16] reg [5:0] stq_3_bits_uop_stale_pdst; // @[lsu.scala:209:16] reg stq_3_bits_uop_exception; // @[lsu.scala:209:16] reg [63:0] stq_3_bits_uop_exc_cause; // @[lsu.scala:209:16] reg stq_3_bits_uop_bypassable; // @[lsu.scala:209:16] reg [4:0] stq_3_bits_uop_mem_cmd; // @[lsu.scala:209:16] reg [1:0] stq_3_bits_uop_mem_size; // @[lsu.scala:209:16] reg stq_3_bits_uop_mem_signed; // @[lsu.scala:209:16] reg stq_3_bits_uop_is_fence; // @[lsu.scala:209:16] reg stq_3_bits_uop_is_fencei; // @[lsu.scala:209:16] reg stq_3_bits_uop_is_amo; // @[lsu.scala:209:16] reg stq_3_bits_uop_uses_ldq; // @[lsu.scala:209:16] reg stq_3_bits_uop_uses_stq; // @[lsu.scala:209:16] reg stq_3_bits_uop_is_sys_pc2epc; // @[lsu.scala:209:16] reg stq_3_bits_uop_is_unique; // @[lsu.scala:209:16] reg stq_3_bits_uop_flush_on_commit; // @[lsu.scala:209:16] reg stq_3_bits_uop_ldst_is_rs1; // @[lsu.scala:209:16] reg [5:0] stq_3_bits_uop_ldst; // @[lsu.scala:209:16] reg [5:0] stq_3_bits_uop_lrs1; // @[lsu.scala:209:16] reg [5:0] stq_3_bits_uop_lrs2; // @[lsu.scala:209:16] reg [5:0] stq_3_bits_uop_lrs3; // @[lsu.scala:209:16] reg stq_3_bits_uop_ldst_val; // @[lsu.scala:209:16] reg [1:0] stq_3_bits_uop_dst_rtype; // @[lsu.scala:209:16] reg [1:0] stq_3_bits_uop_lrs1_rtype; // @[lsu.scala:209:16] reg [1:0] stq_3_bits_uop_lrs2_rtype; // @[lsu.scala:209:16] reg stq_3_bits_uop_frs3_en; // @[lsu.scala:209:16] reg stq_3_bits_uop_fp_val; // @[lsu.scala:209:16] reg stq_3_bits_uop_fp_single; // @[lsu.scala:209:16] reg stq_3_bits_uop_xcpt_pf_if; // @[lsu.scala:209:16] reg stq_3_bits_uop_xcpt_ae_if; // @[lsu.scala:209:16] reg stq_3_bits_uop_xcpt_ma_if; // @[lsu.scala:209:16] reg stq_3_bits_uop_bp_debug_if; // @[lsu.scala:209:16] reg stq_3_bits_uop_bp_xcpt_if; // @[lsu.scala:209:16] reg [1:0] stq_3_bits_uop_debug_fsrc; // @[lsu.scala:209:16] reg [1:0] stq_3_bits_uop_debug_tsrc; // @[lsu.scala:209:16] reg stq_3_bits_addr_valid; // @[lsu.scala:209:16] reg [39:0] stq_3_bits_addr_bits; // @[lsu.scala:209:16] reg stq_3_bits_addr_is_virtual; // @[lsu.scala:209:16] reg stq_3_bits_data_valid; // @[lsu.scala:209:16] reg [63:0] stq_3_bits_data_bits; // @[lsu.scala:209:16] reg stq_3_bits_committed; // @[lsu.scala:209:16] reg stq_3_bits_succeeded; // @[lsu.scala:209:16] reg [63:0] stq_3_bits_debug_wb_data; // @[lsu.scala:209:16] reg stq_4_valid; // @[lsu.scala:209:16] reg [6:0] stq_4_bits_uop_uopc; // @[lsu.scala:209:16] reg [31:0] stq_4_bits_uop_inst; // @[lsu.scala:209:16] reg [31:0] stq_4_bits_uop_debug_inst; // @[lsu.scala:209:16] reg stq_4_bits_uop_is_rvc; // @[lsu.scala:209:16] reg [39:0] stq_4_bits_uop_debug_pc; // @[lsu.scala:209:16] reg [2:0] stq_4_bits_uop_iq_type; // @[lsu.scala:209:16] reg [9:0] stq_4_bits_uop_fu_code; // @[lsu.scala:209:16] reg [3:0] stq_4_bits_uop_ctrl_br_type; // @[lsu.scala:209:16] reg [1:0] stq_4_bits_uop_ctrl_op1_sel; // @[lsu.scala:209:16] reg [2:0] stq_4_bits_uop_ctrl_op2_sel; // @[lsu.scala:209:16] reg [2:0] stq_4_bits_uop_ctrl_imm_sel; // @[lsu.scala:209:16] reg [4:0] stq_4_bits_uop_ctrl_op_fcn; // @[lsu.scala:209:16] reg stq_4_bits_uop_ctrl_fcn_dw; // @[lsu.scala:209:16] reg [2:0] stq_4_bits_uop_ctrl_csr_cmd; // @[lsu.scala:209:16] reg stq_4_bits_uop_ctrl_is_load; // @[lsu.scala:209:16] reg stq_4_bits_uop_ctrl_is_sta; // @[lsu.scala:209:16] reg stq_4_bits_uop_ctrl_is_std; // @[lsu.scala:209:16] reg [1:0] stq_4_bits_uop_iw_state; // @[lsu.scala:209:16] reg stq_4_bits_uop_iw_p1_poisoned; // @[lsu.scala:209:16] reg stq_4_bits_uop_iw_p2_poisoned; // @[lsu.scala:209:16] reg stq_4_bits_uop_is_br; // @[lsu.scala:209:16] reg stq_4_bits_uop_is_jalr; // @[lsu.scala:209:16] reg stq_4_bits_uop_is_jal; // @[lsu.scala:209:16] reg stq_4_bits_uop_is_sfb; // @[lsu.scala:209:16] reg [7:0] stq_4_bits_uop_br_mask; // @[lsu.scala:209:16] reg [2:0] stq_4_bits_uop_br_tag; // @[lsu.scala:209:16] reg [3:0] stq_4_bits_uop_ftq_idx; // @[lsu.scala:209:16] reg stq_4_bits_uop_edge_inst; // @[lsu.scala:209:16] reg [5:0] stq_4_bits_uop_pc_lob; // @[lsu.scala:209:16] reg stq_4_bits_uop_taken; // @[lsu.scala:209:16] reg [19:0] stq_4_bits_uop_imm_packed; // @[lsu.scala:209:16] reg [11:0] stq_4_bits_uop_csr_addr; // @[lsu.scala:209:16] reg [4:0] stq_4_bits_uop_rob_idx; // @[lsu.scala:209:16] reg [2:0] stq_4_bits_uop_ldq_idx; // @[lsu.scala:209:16] reg [2:0] stq_4_bits_uop_stq_idx; // @[lsu.scala:209:16] reg [1:0] stq_4_bits_uop_rxq_idx; // @[lsu.scala:209:16] reg [5:0] stq_4_bits_uop_pdst; // @[lsu.scala:209:16] reg [5:0] stq_4_bits_uop_prs1; // @[lsu.scala:209:16] reg [5:0] stq_4_bits_uop_prs2; // @[lsu.scala:209:16] reg [5:0] stq_4_bits_uop_prs3; // @[lsu.scala:209:16] reg [3:0] stq_4_bits_uop_ppred; // @[lsu.scala:209:16] reg stq_4_bits_uop_prs1_busy; // @[lsu.scala:209:16] reg stq_4_bits_uop_prs2_busy; // @[lsu.scala:209:16] reg stq_4_bits_uop_prs3_busy; // @[lsu.scala:209:16] reg stq_4_bits_uop_ppred_busy; // @[lsu.scala:209:16] reg [5:0] stq_4_bits_uop_stale_pdst; // @[lsu.scala:209:16] reg stq_4_bits_uop_exception; // @[lsu.scala:209:16] reg [63:0] stq_4_bits_uop_exc_cause; // @[lsu.scala:209:16] reg stq_4_bits_uop_bypassable; // @[lsu.scala:209:16] reg [4:0] stq_4_bits_uop_mem_cmd; // @[lsu.scala:209:16] reg [1:0] stq_4_bits_uop_mem_size; // @[lsu.scala:209:16] reg stq_4_bits_uop_mem_signed; // @[lsu.scala:209:16] reg stq_4_bits_uop_is_fence; // @[lsu.scala:209:16] reg stq_4_bits_uop_is_fencei; // @[lsu.scala:209:16] reg stq_4_bits_uop_is_amo; // @[lsu.scala:209:16] reg stq_4_bits_uop_uses_ldq; // @[lsu.scala:209:16] reg stq_4_bits_uop_uses_stq; // @[lsu.scala:209:16] reg stq_4_bits_uop_is_sys_pc2epc; // @[lsu.scala:209:16] reg stq_4_bits_uop_is_unique; // @[lsu.scala:209:16] reg stq_4_bits_uop_flush_on_commit; // @[lsu.scala:209:16] reg stq_4_bits_uop_ldst_is_rs1; // @[lsu.scala:209:16] reg [5:0] stq_4_bits_uop_ldst; // @[lsu.scala:209:16] reg [5:0] stq_4_bits_uop_lrs1; // @[lsu.scala:209:16] reg [5:0] stq_4_bits_uop_lrs2; // @[lsu.scala:209:16] reg [5:0] stq_4_bits_uop_lrs3; // @[lsu.scala:209:16] reg stq_4_bits_uop_ldst_val; // @[lsu.scala:209:16] reg [1:0] stq_4_bits_uop_dst_rtype; // @[lsu.scala:209:16] reg [1:0] stq_4_bits_uop_lrs1_rtype; // @[lsu.scala:209:16] reg [1:0] stq_4_bits_uop_lrs2_rtype; // @[lsu.scala:209:16] reg stq_4_bits_uop_frs3_en; // @[lsu.scala:209:16] reg stq_4_bits_uop_fp_val; // @[lsu.scala:209:16] reg stq_4_bits_uop_fp_single; // @[lsu.scala:209:16] reg stq_4_bits_uop_xcpt_pf_if; // @[lsu.scala:209:16] reg stq_4_bits_uop_xcpt_ae_if; // @[lsu.scala:209:16] reg stq_4_bits_uop_xcpt_ma_if; // @[lsu.scala:209:16] reg stq_4_bits_uop_bp_debug_if; // @[lsu.scala:209:16] reg stq_4_bits_uop_bp_xcpt_if; // @[lsu.scala:209:16] reg [1:0] stq_4_bits_uop_debug_fsrc; // @[lsu.scala:209:16] reg [1:0] stq_4_bits_uop_debug_tsrc; // @[lsu.scala:209:16] reg stq_4_bits_addr_valid; // @[lsu.scala:209:16] reg [39:0] stq_4_bits_addr_bits; // @[lsu.scala:209:16] reg stq_4_bits_addr_is_virtual; // @[lsu.scala:209:16] reg stq_4_bits_data_valid; // @[lsu.scala:209:16] reg [63:0] stq_4_bits_data_bits; // @[lsu.scala:209:16] reg stq_4_bits_committed; // @[lsu.scala:209:16] reg stq_4_bits_succeeded; // @[lsu.scala:209:16] reg [63:0] stq_4_bits_debug_wb_data; // @[lsu.scala:209:16] reg stq_5_valid; // @[lsu.scala:209:16] reg [6:0] stq_5_bits_uop_uopc; // @[lsu.scala:209:16] reg [31:0] stq_5_bits_uop_inst; // @[lsu.scala:209:16] reg [31:0] stq_5_bits_uop_debug_inst; // @[lsu.scala:209:16] reg stq_5_bits_uop_is_rvc; // @[lsu.scala:209:16] reg [39:0] stq_5_bits_uop_debug_pc; // @[lsu.scala:209:16] reg [2:0] stq_5_bits_uop_iq_type; // @[lsu.scala:209:16] reg [9:0] stq_5_bits_uop_fu_code; // @[lsu.scala:209:16] reg [3:0] stq_5_bits_uop_ctrl_br_type; // @[lsu.scala:209:16] reg [1:0] stq_5_bits_uop_ctrl_op1_sel; // @[lsu.scala:209:16] reg [2:0] stq_5_bits_uop_ctrl_op2_sel; // @[lsu.scala:209:16] reg [2:0] stq_5_bits_uop_ctrl_imm_sel; // @[lsu.scala:209:16] reg [4:0] stq_5_bits_uop_ctrl_op_fcn; // @[lsu.scala:209:16] reg stq_5_bits_uop_ctrl_fcn_dw; // @[lsu.scala:209:16] reg [2:0] stq_5_bits_uop_ctrl_csr_cmd; // @[lsu.scala:209:16] reg stq_5_bits_uop_ctrl_is_load; // @[lsu.scala:209:16] reg stq_5_bits_uop_ctrl_is_sta; // @[lsu.scala:209:16] reg stq_5_bits_uop_ctrl_is_std; // @[lsu.scala:209:16] reg [1:0] stq_5_bits_uop_iw_state; // @[lsu.scala:209:16] reg stq_5_bits_uop_iw_p1_poisoned; // @[lsu.scala:209:16] reg stq_5_bits_uop_iw_p2_poisoned; // @[lsu.scala:209:16] reg stq_5_bits_uop_is_br; // @[lsu.scala:209:16] reg stq_5_bits_uop_is_jalr; // @[lsu.scala:209:16] reg stq_5_bits_uop_is_jal; // @[lsu.scala:209:16] reg stq_5_bits_uop_is_sfb; // @[lsu.scala:209:16] reg [7:0] stq_5_bits_uop_br_mask; // @[lsu.scala:209:16] reg [2:0] stq_5_bits_uop_br_tag; // @[lsu.scala:209:16] reg [3:0] stq_5_bits_uop_ftq_idx; // @[lsu.scala:209:16] reg stq_5_bits_uop_edge_inst; // @[lsu.scala:209:16] reg [5:0] stq_5_bits_uop_pc_lob; // @[lsu.scala:209:16] reg stq_5_bits_uop_taken; // @[lsu.scala:209:16] reg [19:0] stq_5_bits_uop_imm_packed; // @[lsu.scala:209:16] reg [11:0] stq_5_bits_uop_csr_addr; // @[lsu.scala:209:16] reg [4:0] stq_5_bits_uop_rob_idx; // @[lsu.scala:209:16] reg [2:0] stq_5_bits_uop_ldq_idx; // @[lsu.scala:209:16] reg [2:0] stq_5_bits_uop_stq_idx; // @[lsu.scala:209:16] reg [1:0] stq_5_bits_uop_rxq_idx; // @[lsu.scala:209:16] reg [5:0] stq_5_bits_uop_pdst; // @[lsu.scala:209:16] reg [5:0] stq_5_bits_uop_prs1; // @[lsu.scala:209:16] reg [5:0] stq_5_bits_uop_prs2; // @[lsu.scala:209:16] reg [5:0] stq_5_bits_uop_prs3; // @[lsu.scala:209:16] reg [3:0] stq_5_bits_uop_ppred; // @[lsu.scala:209:16] reg stq_5_bits_uop_prs1_busy; // @[lsu.scala:209:16] reg stq_5_bits_uop_prs2_busy; // @[lsu.scala:209:16] reg stq_5_bits_uop_prs3_busy; // @[lsu.scala:209:16] reg stq_5_bits_uop_ppred_busy; // @[lsu.scala:209:16] reg [5:0] stq_5_bits_uop_stale_pdst; // @[lsu.scala:209:16] reg stq_5_bits_uop_exception; // @[lsu.scala:209:16] reg [63:0] stq_5_bits_uop_exc_cause; // @[lsu.scala:209:16] reg stq_5_bits_uop_bypassable; // @[lsu.scala:209:16] reg [4:0] stq_5_bits_uop_mem_cmd; // @[lsu.scala:209:16] reg [1:0] stq_5_bits_uop_mem_size; // @[lsu.scala:209:16] reg stq_5_bits_uop_mem_signed; // @[lsu.scala:209:16] reg stq_5_bits_uop_is_fence; // @[lsu.scala:209:16] reg stq_5_bits_uop_is_fencei; // @[lsu.scala:209:16] reg stq_5_bits_uop_is_amo; // @[lsu.scala:209:16] reg stq_5_bits_uop_uses_ldq; // @[lsu.scala:209:16] reg stq_5_bits_uop_uses_stq; // @[lsu.scala:209:16] reg stq_5_bits_uop_is_sys_pc2epc; // @[lsu.scala:209:16] reg stq_5_bits_uop_is_unique; // @[lsu.scala:209:16] reg stq_5_bits_uop_flush_on_commit; // @[lsu.scala:209:16] reg stq_5_bits_uop_ldst_is_rs1; // @[lsu.scala:209:16] reg [5:0] stq_5_bits_uop_ldst; // @[lsu.scala:209:16] reg [5:0] stq_5_bits_uop_lrs1; // @[lsu.scala:209:16] reg [5:0] stq_5_bits_uop_lrs2; // @[lsu.scala:209:16] reg [5:0] stq_5_bits_uop_lrs3; // @[lsu.scala:209:16] reg stq_5_bits_uop_ldst_val; // @[lsu.scala:209:16] reg [1:0] stq_5_bits_uop_dst_rtype; // @[lsu.scala:209:16] reg [1:0] stq_5_bits_uop_lrs1_rtype; // @[lsu.scala:209:16] reg [1:0] stq_5_bits_uop_lrs2_rtype; // @[lsu.scala:209:16] reg stq_5_bits_uop_frs3_en; // @[lsu.scala:209:16] reg stq_5_bits_uop_fp_val; // @[lsu.scala:209:16] reg stq_5_bits_uop_fp_single; // @[lsu.scala:209:16] reg stq_5_bits_uop_xcpt_pf_if; // @[lsu.scala:209:16] reg stq_5_bits_uop_xcpt_ae_if; // @[lsu.scala:209:16] reg stq_5_bits_uop_xcpt_ma_if; // @[lsu.scala:209:16] reg stq_5_bits_uop_bp_debug_if; // @[lsu.scala:209:16] reg stq_5_bits_uop_bp_xcpt_if; // @[lsu.scala:209:16] reg [1:0] stq_5_bits_uop_debug_fsrc; // @[lsu.scala:209:16] reg [1:0] stq_5_bits_uop_debug_tsrc; // @[lsu.scala:209:16] reg stq_5_bits_addr_valid; // @[lsu.scala:209:16] reg [39:0] stq_5_bits_addr_bits; // @[lsu.scala:209:16] reg stq_5_bits_addr_is_virtual; // @[lsu.scala:209:16] reg stq_5_bits_data_valid; // @[lsu.scala:209:16] reg [63:0] stq_5_bits_data_bits; // @[lsu.scala:209:16] reg stq_5_bits_committed; // @[lsu.scala:209:16] reg stq_5_bits_succeeded; // @[lsu.scala:209:16] reg [63:0] stq_5_bits_debug_wb_data; // @[lsu.scala:209:16] reg stq_6_valid; // @[lsu.scala:209:16] reg [6:0] stq_6_bits_uop_uopc; // @[lsu.scala:209:16] reg [31:0] stq_6_bits_uop_inst; // @[lsu.scala:209:16] reg [31:0] stq_6_bits_uop_debug_inst; // @[lsu.scala:209:16] reg stq_6_bits_uop_is_rvc; // @[lsu.scala:209:16] reg [39:0] stq_6_bits_uop_debug_pc; // @[lsu.scala:209:16] reg [2:0] stq_6_bits_uop_iq_type; // @[lsu.scala:209:16] reg [9:0] stq_6_bits_uop_fu_code; // @[lsu.scala:209:16] reg [3:0] stq_6_bits_uop_ctrl_br_type; // @[lsu.scala:209:16] reg [1:0] stq_6_bits_uop_ctrl_op1_sel; // @[lsu.scala:209:16] reg [2:0] stq_6_bits_uop_ctrl_op2_sel; // @[lsu.scala:209:16] reg [2:0] stq_6_bits_uop_ctrl_imm_sel; // @[lsu.scala:209:16] reg [4:0] stq_6_bits_uop_ctrl_op_fcn; // @[lsu.scala:209:16] reg stq_6_bits_uop_ctrl_fcn_dw; // @[lsu.scala:209:16] reg [2:0] stq_6_bits_uop_ctrl_csr_cmd; // @[lsu.scala:209:16] reg stq_6_bits_uop_ctrl_is_load; // @[lsu.scala:209:16] reg stq_6_bits_uop_ctrl_is_sta; // @[lsu.scala:209:16] reg stq_6_bits_uop_ctrl_is_std; // @[lsu.scala:209:16] reg [1:0] stq_6_bits_uop_iw_state; // @[lsu.scala:209:16] reg stq_6_bits_uop_iw_p1_poisoned; // @[lsu.scala:209:16] reg stq_6_bits_uop_iw_p2_poisoned; // @[lsu.scala:209:16] reg stq_6_bits_uop_is_br; // @[lsu.scala:209:16] reg stq_6_bits_uop_is_jalr; // @[lsu.scala:209:16] reg stq_6_bits_uop_is_jal; // @[lsu.scala:209:16] reg stq_6_bits_uop_is_sfb; // @[lsu.scala:209:16] reg [7:0] stq_6_bits_uop_br_mask; // @[lsu.scala:209:16] reg [2:0] stq_6_bits_uop_br_tag; // @[lsu.scala:209:16] reg [3:0] stq_6_bits_uop_ftq_idx; // @[lsu.scala:209:16] reg stq_6_bits_uop_edge_inst; // @[lsu.scala:209:16] reg [5:0] stq_6_bits_uop_pc_lob; // @[lsu.scala:209:16] reg stq_6_bits_uop_taken; // @[lsu.scala:209:16] reg [19:0] stq_6_bits_uop_imm_packed; // @[lsu.scala:209:16] reg [11:0] stq_6_bits_uop_csr_addr; // @[lsu.scala:209:16] reg [4:0] stq_6_bits_uop_rob_idx; // @[lsu.scala:209:16] reg [2:0] stq_6_bits_uop_ldq_idx; // @[lsu.scala:209:16] reg [2:0] stq_6_bits_uop_stq_idx; // @[lsu.scala:209:16] reg [1:0] stq_6_bits_uop_rxq_idx; // @[lsu.scala:209:16] reg [5:0] stq_6_bits_uop_pdst; // @[lsu.scala:209:16] reg [5:0] stq_6_bits_uop_prs1; // @[lsu.scala:209:16] reg [5:0] stq_6_bits_uop_prs2; // @[lsu.scala:209:16] reg [5:0] stq_6_bits_uop_prs3; // @[lsu.scala:209:16] reg [3:0] stq_6_bits_uop_ppred; // @[lsu.scala:209:16] reg stq_6_bits_uop_prs1_busy; // @[lsu.scala:209:16] reg stq_6_bits_uop_prs2_busy; // @[lsu.scala:209:16] reg stq_6_bits_uop_prs3_busy; // @[lsu.scala:209:16] reg stq_6_bits_uop_ppred_busy; // @[lsu.scala:209:16] reg [5:0] stq_6_bits_uop_stale_pdst; // @[lsu.scala:209:16] reg stq_6_bits_uop_exception; // @[lsu.scala:209:16] reg [63:0] stq_6_bits_uop_exc_cause; // @[lsu.scala:209:16] reg stq_6_bits_uop_bypassable; // @[lsu.scala:209:16] reg [4:0] stq_6_bits_uop_mem_cmd; // @[lsu.scala:209:16] reg [1:0] stq_6_bits_uop_mem_size; // @[lsu.scala:209:16] reg stq_6_bits_uop_mem_signed; // @[lsu.scala:209:16] reg stq_6_bits_uop_is_fence; // @[lsu.scala:209:16] reg stq_6_bits_uop_is_fencei; // @[lsu.scala:209:16] reg stq_6_bits_uop_is_amo; // @[lsu.scala:209:16] reg stq_6_bits_uop_uses_ldq; // @[lsu.scala:209:16] reg stq_6_bits_uop_uses_stq; // @[lsu.scala:209:16] reg stq_6_bits_uop_is_sys_pc2epc; // @[lsu.scala:209:16] reg stq_6_bits_uop_is_unique; // @[lsu.scala:209:16] reg stq_6_bits_uop_flush_on_commit; // @[lsu.scala:209:16] reg stq_6_bits_uop_ldst_is_rs1; // @[lsu.scala:209:16] reg [5:0] stq_6_bits_uop_ldst; // @[lsu.scala:209:16] reg [5:0] stq_6_bits_uop_lrs1; // @[lsu.scala:209:16] reg [5:0] stq_6_bits_uop_lrs2; // @[lsu.scala:209:16] reg [5:0] stq_6_bits_uop_lrs3; // @[lsu.scala:209:16] reg stq_6_bits_uop_ldst_val; // @[lsu.scala:209:16] reg [1:0] stq_6_bits_uop_dst_rtype; // @[lsu.scala:209:16] reg [1:0] stq_6_bits_uop_lrs1_rtype; // @[lsu.scala:209:16] reg [1:0] stq_6_bits_uop_lrs2_rtype; // @[lsu.scala:209:16] reg stq_6_bits_uop_frs3_en; // @[lsu.scala:209:16] reg stq_6_bits_uop_fp_val; // @[lsu.scala:209:16] reg stq_6_bits_uop_fp_single; // @[lsu.scala:209:16] reg stq_6_bits_uop_xcpt_pf_if; // @[lsu.scala:209:16] reg stq_6_bits_uop_xcpt_ae_if; // @[lsu.scala:209:16] reg stq_6_bits_uop_xcpt_ma_if; // @[lsu.scala:209:16] reg stq_6_bits_uop_bp_debug_if; // @[lsu.scala:209:16] reg stq_6_bits_uop_bp_xcpt_if; // @[lsu.scala:209:16] reg [1:0] stq_6_bits_uop_debug_fsrc; // @[lsu.scala:209:16] reg [1:0] stq_6_bits_uop_debug_tsrc; // @[lsu.scala:209:16] reg stq_6_bits_addr_valid; // @[lsu.scala:209:16] reg [39:0] stq_6_bits_addr_bits; // @[lsu.scala:209:16] reg stq_6_bits_addr_is_virtual; // @[lsu.scala:209:16] reg stq_6_bits_data_valid; // @[lsu.scala:209:16] reg [63:0] stq_6_bits_data_bits; // @[lsu.scala:209:16] reg stq_6_bits_committed; // @[lsu.scala:209:16] reg stq_6_bits_succeeded; // @[lsu.scala:209:16] reg [63:0] stq_6_bits_debug_wb_data; // @[lsu.scala:209:16] reg stq_7_valid; // @[lsu.scala:209:16] reg [6:0] stq_7_bits_uop_uopc; // @[lsu.scala:209:16] reg [31:0] stq_7_bits_uop_inst; // @[lsu.scala:209:16] reg [31:0] stq_7_bits_uop_debug_inst; // @[lsu.scala:209:16] reg stq_7_bits_uop_is_rvc; // @[lsu.scala:209:16] reg [39:0] stq_7_bits_uop_debug_pc; // @[lsu.scala:209:16] reg [2:0] stq_7_bits_uop_iq_type; // @[lsu.scala:209:16] reg [9:0] stq_7_bits_uop_fu_code; // @[lsu.scala:209:16] reg [3:0] stq_7_bits_uop_ctrl_br_type; // @[lsu.scala:209:16] reg [1:0] stq_7_bits_uop_ctrl_op1_sel; // @[lsu.scala:209:16] reg [2:0] stq_7_bits_uop_ctrl_op2_sel; // @[lsu.scala:209:16] reg [2:0] stq_7_bits_uop_ctrl_imm_sel; // @[lsu.scala:209:16] reg [4:0] stq_7_bits_uop_ctrl_op_fcn; // @[lsu.scala:209:16] reg stq_7_bits_uop_ctrl_fcn_dw; // @[lsu.scala:209:16] reg [2:0] stq_7_bits_uop_ctrl_csr_cmd; // @[lsu.scala:209:16] reg stq_7_bits_uop_ctrl_is_load; // @[lsu.scala:209:16] reg stq_7_bits_uop_ctrl_is_sta; // @[lsu.scala:209:16] reg stq_7_bits_uop_ctrl_is_std; // @[lsu.scala:209:16] reg [1:0] stq_7_bits_uop_iw_state; // @[lsu.scala:209:16] reg stq_7_bits_uop_iw_p1_poisoned; // @[lsu.scala:209:16] reg stq_7_bits_uop_iw_p2_poisoned; // @[lsu.scala:209:16] reg stq_7_bits_uop_is_br; // @[lsu.scala:209:16] reg stq_7_bits_uop_is_jalr; // @[lsu.scala:209:16] reg stq_7_bits_uop_is_jal; // @[lsu.scala:209:16] reg stq_7_bits_uop_is_sfb; // @[lsu.scala:209:16] reg [7:0] stq_7_bits_uop_br_mask; // @[lsu.scala:209:16] reg [2:0] stq_7_bits_uop_br_tag; // @[lsu.scala:209:16] reg [3:0] stq_7_bits_uop_ftq_idx; // @[lsu.scala:209:16] reg stq_7_bits_uop_edge_inst; // @[lsu.scala:209:16] reg [5:0] stq_7_bits_uop_pc_lob; // @[lsu.scala:209:16] reg stq_7_bits_uop_taken; // @[lsu.scala:209:16] reg [19:0] stq_7_bits_uop_imm_packed; // @[lsu.scala:209:16] reg [11:0] stq_7_bits_uop_csr_addr; // @[lsu.scala:209:16] reg [4:0] stq_7_bits_uop_rob_idx; // @[lsu.scala:209:16] reg [2:0] stq_7_bits_uop_ldq_idx; // @[lsu.scala:209:16] reg [2:0] stq_7_bits_uop_stq_idx; // @[lsu.scala:209:16] reg [1:0] stq_7_bits_uop_rxq_idx; // @[lsu.scala:209:16] reg [5:0] stq_7_bits_uop_pdst; // @[lsu.scala:209:16] reg [5:0] stq_7_bits_uop_prs1; // @[lsu.scala:209:16] reg [5:0] stq_7_bits_uop_prs2; // @[lsu.scala:209:16] reg [5:0] stq_7_bits_uop_prs3; // @[lsu.scala:209:16] reg [3:0] stq_7_bits_uop_ppred; // @[lsu.scala:209:16] reg stq_7_bits_uop_prs1_busy; // @[lsu.scala:209:16] reg stq_7_bits_uop_prs2_busy; // @[lsu.scala:209:16] reg stq_7_bits_uop_prs3_busy; // @[lsu.scala:209:16] reg stq_7_bits_uop_ppred_busy; // @[lsu.scala:209:16] reg [5:0] stq_7_bits_uop_stale_pdst; // @[lsu.scala:209:16] reg stq_7_bits_uop_exception; // @[lsu.scala:209:16] reg [63:0] stq_7_bits_uop_exc_cause; // @[lsu.scala:209:16] reg stq_7_bits_uop_bypassable; // @[lsu.scala:209:16] reg [4:0] stq_7_bits_uop_mem_cmd; // @[lsu.scala:209:16] reg [1:0] stq_7_bits_uop_mem_size; // @[lsu.scala:209:16] reg stq_7_bits_uop_mem_signed; // @[lsu.scala:209:16] reg stq_7_bits_uop_is_fence; // @[lsu.scala:209:16] reg stq_7_bits_uop_is_fencei; // @[lsu.scala:209:16] reg stq_7_bits_uop_is_amo; // @[lsu.scala:209:16] reg stq_7_bits_uop_uses_ldq; // @[lsu.scala:209:16] reg stq_7_bits_uop_uses_stq; // @[lsu.scala:209:16] reg stq_7_bits_uop_is_sys_pc2epc; // @[lsu.scala:209:16] reg stq_7_bits_uop_is_unique; // @[lsu.scala:209:16] reg stq_7_bits_uop_flush_on_commit; // @[lsu.scala:209:16] reg stq_7_bits_uop_ldst_is_rs1; // @[lsu.scala:209:16] reg [5:0] stq_7_bits_uop_ldst; // @[lsu.scala:209:16] reg [5:0] stq_7_bits_uop_lrs1; // @[lsu.scala:209:16] reg [5:0] stq_7_bits_uop_lrs2; // @[lsu.scala:209:16] reg [5:0] stq_7_bits_uop_lrs3; // @[lsu.scala:209:16] reg stq_7_bits_uop_ldst_val; // @[lsu.scala:209:16] reg [1:0] stq_7_bits_uop_dst_rtype; // @[lsu.scala:209:16] reg [1:0] stq_7_bits_uop_lrs1_rtype; // @[lsu.scala:209:16] reg [1:0] stq_7_bits_uop_lrs2_rtype; // @[lsu.scala:209:16] reg stq_7_bits_uop_frs3_en; // @[lsu.scala:209:16] reg stq_7_bits_uop_fp_val; // @[lsu.scala:209:16] reg stq_7_bits_uop_fp_single; // @[lsu.scala:209:16] reg stq_7_bits_uop_xcpt_pf_if; // @[lsu.scala:209:16] reg stq_7_bits_uop_xcpt_ae_if; // @[lsu.scala:209:16] reg stq_7_bits_uop_xcpt_ma_if; // @[lsu.scala:209:16] reg stq_7_bits_uop_bp_debug_if; // @[lsu.scala:209:16] reg stq_7_bits_uop_bp_xcpt_if; // @[lsu.scala:209:16] reg [1:0] stq_7_bits_uop_debug_fsrc; // @[lsu.scala:209:16] reg [1:0] stq_7_bits_uop_debug_tsrc; // @[lsu.scala:209:16] reg stq_7_bits_addr_valid; // @[lsu.scala:209:16] reg [39:0] stq_7_bits_addr_bits; // @[lsu.scala:209:16] reg stq_7_bits_addr_is_virtual; // @[lsu.scala:209:16] reg stq_7_bits_data_valid; // @[lsu.scala:209:16] reg [63:0] stq_7_bits_data_bits; // @[lsu.scala:209:16] reg stq_7_bits_committed; // @[lsu.scala:209:16] reg stq_7_bits_succeeded; // @[lsu.scala:209:16] reg [63:0] stq_7_bits_debug_wb_data; // @[lsu.scala:209:16] reg [2:0] ldq_head; // @[lsu.scala:213:29] reg [2:0] ldq_tail; // @[lsu.scala:214:29] assign io_core_dis_ldq_idx_0_0 = ldq_tail; // @[lsu.scala:201:7, :214:29] reg [2:0] stq_head; // @[lsu.scala:215:29] reg [2:0] stq_tail; // @[lsu.scala:216:29] assign io_core_dis_stq_idx_0_0 = stq_tail; // @[lsu.scala:201:7, :216:29] reg [2:0] stq_commit_head; // @[lsu.scala:217:29] reg [2:0] stq_execute_head; // @[lsu.scala:218:29] wire [7:0] _GEN = {{stq_7_valid}, {stq_6_valid}, {stq_5_valid}, {stq_4_valid}, {stq_3_valid}, {stq_2_valid}, {stq_1_valid}, {stq_0_valid}}; // @[lsu.scala:209:16, :222:42] wire _GEN_0 = _GEN[stq_execute_head]; // @[lsu.scala:218:29, :222:42] wire [7:0][6:0] _GEN_1 = {{stq_7_bits_uop_uopc}, {stq_6_bits_uop_uopc}, {stq_5_bits_uop_uopc}, {stq_4_bits_uop_uopc}, {stq_3_bits_uop_uopc}, {stq_2_bits_uop_uopc}, {stq_1_bits_uop_uopc}, {stq_0_bits_uop_uopc}}; // @[lsu.scala:209:16, :222:42] wire [7:0][31:0] _GEN_2 = {{stq_7_bits_uop_inst}, {stq_6_bits_uop_inst}, {stq_5_bits_uop_inst}, {stq_4_bits_uop_inst}, {stq_3_bits_uop_inst}, {stq_2_bits_uop_inst}, {stq_1_bits_uop_inst}, {stq_0_bits_uop_inst}}; // @[lsu.scala:209:16, :222:42] wire [7:0][31:0] _GEN_3 = {{stq_7_bits_uop_debug_inst}, {stq_6_bits_uop_debug_inst}, {stq_5_bits_uop_debug_inst}, {stq_4_bits_uop_debug_inst}, {stq_3_bits_uop_debug_inst}, {stq_2_bits_uop_debug_inst}, {stq_1_bits_uop_debug_inst}, {stq_0_bits_uop_debug_inst}}; // @[lsu.scala:209:16, :222:42] wire [7:0] _GEN_4 = {{stq_7_bits_uop_is_rvc}, {stq_6_bits_uop_is_rvc}, {stq_5_bits_uop_is_rvc}, {stq_4_bits_uop_is_rvc}, {stq_3_bits_uop_is_rvc}, {stq_2_bits_uop_is_rvc}, {stq_1_bits_uop_is_rvc}, {stq_0_bits_uop_is_rvc}}; // @[lsu.scala:209:16, :222:42] wire [7:0][39:0] _GEN_5 = {{stq_7_bits_uop_debug_pc}, {stq_6_bits_uop_debug_pc}, {stq_5_bits_uop_debug_pc}, {stq_4_bits_uop_debug_pc}, {stq_3_bits_uop_debug_pc}, {stq_2_bits_uop_debug_pc}, {stq_1_bits_uop_debug_pc}, {stq_0_bits_uop_debug_pc}}; // @[lsu.scala:209:16, :222:42] wire [7:0][2:0] _GEN_6 = {{stq_7_bits_uop_iq_type}, {stq_6_bits_uop_iq_type}, {stq_5_bits_uop_iq_type}, {stq_4_bits_uop_iq_type}, {stq_3_bits_uop_iq_type}, {stq_2_bits_uop_iq_type}, {stq_1_bits_uop_iq_type}, {stq_0_bits_uop_iq_type}}; // @[lsu.scala:209:16, :222:42] wire [7:0][9:0] _GEN_7 = {{stq_7_bits_uop_fu_code}, {stq_6_bits_uop_fu_code}, {stq_5_bits_uop_fu_code}, {stq_4_bits_uop_fu_code}, {stq_3_bits_uop_fu_code}, {stq_2_bits_uop_fu_code}, {stq_1_bits_uop_fu_code}, {stq_0_bits_uop_fu_code}}; // @[lsu.scala:209:16, :222:42] wire [7:0][3:0] _GEN_8 = {{stq_7_bits_uop_ctrl_br_type}, {stq_6_bits_uop_ctrl_br_type}, {stq_5_bits_uop_ctrl_br_type}, {stq_4_bits_uop_ctrl_br_type}, {stq_3_bits_uop_ctrl_br_type}, {stq_2_bits_uop_ctrl_br_type}, {stq_1_bits_uop_ctrl_br_type}, {stq_0_bits_uop_ctrl_br_type}}; // @[lsu.scala:209:16, :222:42] wire [7:0][1:0] _GEN_9 = {{stq_7_bits_uop_ctrl_op1_sel}, {stq_6_bits_uop_ctrl_op1_sel}, {stq_5_bits_uop_ctrl_op1_sel}, {stq_4_bits_uop_ctrl_op1_sel}, {stq_3_bits_uop_ctrl_op1_sel}, {stq_2_bits_uop_ctrl_op1_sel}, {stq_1_bits_uop_ctrl_op1_sel}, {stq_0_bits_uop_ctrl_op1_sel}}; // @[lsu.scala:209:16, :222:42] wire [7:0][2:0] _GEN_10 = {{stq_7_bits_uop_ctrl_op2_sel}, {stq_6_bits_uop_ctrl_op2_sel}, {stq_5_bits_uop_ctrl_op2_sel}, {stq_4_bits_uop_ctrl_op2_sel}, {stq_3_bits_uop_ctrl_op2_sel}, {stq_2_bits_uop_ctrl_op2_sel}, {stq_1_bits_uop_ctrl_op2_sel}, {stq_0_bits_uop_ctrl_op2_sel}}; // @[lsu.scala:209:16, :222:42] wire [7:0][2:0] _GEN_11 = {{stq_7_bits_uop_ctrl_imm_sel}, {stq_6_bits_uop_ctrl_imm_sel}, {stq_5_bits_uop_ctrl_imm_sel}, {stq_4_bits_uop_ctrl_imm_sel}, {stq_3_bits_uop_ctrl_imm_sel}, {stq_2_bits_uop_ctrl_imm_sel}, {stq_1_bits_uop_ctrl_imm_sel}, {stq_0_bits_uop_ctrl_imm_sel}}; // @[lsu.scala:209:16, :222:42] wire [7:0][4:0] _GEN_12 = {{stq_7_bits_uop_ctrl_op_fcn}, {stq_6_bits_uop_ctrl_op_fcn}, {stq_5_bits_uop_ctrl_op_fcn}, {stq_4_bits_uop_ctrl_op_fcn}, {stq_3_bits_uop_ctrl_op_fcn}, {stq_2_bits_uop_ctrl_op_fcn}, {stq_1_bits_uop_ctrl_op_fcn}, {stq_0_bits_uop_ctrl_op_fcn}}; // @[lsu.scala:209:16, :222:42] wire [7:0] _GEN_13 = {{stq_7_bits_uop_ctrl_fcn_dw}, {stq_6_bits_uop_ctrl_fcn_dw}, {stq_5_bits_uop_ctrl_fcn_dw}, {stq_4_bits_uop_ctrl_fcn_dw}, {stq_3_bits_uop_ctrl_fcn_dw}, {stq_2_bits_uop_ctrl_fcn_dw}, {stq_1_bits_uop_ctrl_fcn_dw}, {stq_0_bits_uop_ctrl_fcn_dw}}; // @[lsu.scala:209:16, :222:42] wire [7:0][2:0] _GEN_14 = {{stq_7_bits_uop_ctrl_csr_cmd}, {stq_6_bits_uop_ctrl_csr_cmd}, {stq_5_bits_uop_ctrl_csr_cmd}, {stq_4_bits_uop_ctrl_csr_cmd}, {stq_3_bits_uop_ctrl_csr_cmd}, {stq_2_bits_uop_ctrl_csr_cmd}, {stq_1_bits_uop_ctrl_csr_cmd}, {stq_0_bits_uop_ctrl_csr_cmd}}; // @[lsu.scala:209:16, :222:42] wire [7:0] _GEN_15 = {{stq_7_bits_uop_ctrl_is_load}, {stq_6_bits_uop_ctrl_is_load}, {stq_5_bits_uop_ctrl_is_load}, {stq_4_bits_uop_ctrl_is_load}, {stq_3_bits_uop_ctrl_is_load}, {stq_2_bits_uop_ctrl_is_load}, {stq_1_bits_uop_ctrl_is_load}, {stq_0_bits_uop_ctrl_is_load}}; // @[lsu.scala:209:16, :222:42] wire [7:0] _GEN_16 = {{stq_7_bits_uop_ctrl_is_sta}, {stq_6_bits_uop_ctrl_is_sta}, {stq_5_bits_uop_ctrl_is_sta}, {stq_4_bits_uop_ctrl_is_sta}, {stq_3_bits_uop_ctrl_is_sta}, {stq_2_bits_uop_ctrl_is_sta}, {stq_1_bits_uop_ctrl_is_sta}, {stq_0_bits_uop_ctrl_is_sta}}; // @[lsu.scala:209:16, :222:42] wire [7:0] _GEN_17 = {{stq_7_bits_uop_ctrl_is_std}, {stq_6_bits_uop_ctrl_is_std}, {stq_5_bits_uop_ctrl_is_std}, {stq_4_bits_uop_ctrl_is_std}, {stq_3_bits_uop_ctrl_is_std}, {stq_2_bits_uop_ctrl_is_std}, {stq_1_bits_uop_ctrl_is_std}, {stq_0_bits_uop_ctrl_is_std}}; // @[lsu.scala:209:16, :222:42] wire [7:0][1:0] _GEN_18 = {{stq_7_bits_uop_iw_state}, {stq_6_bits_uop_iw_state}, {stq_5_bits_uop_iw_state}, {stq_4_bits_uop_iw_state}, {stq_3_bits_uop_iw_state}, {stq_2_bits_uop_iw_state}, {stq_1_bits_uop_iw_state}, {stq_0_bits_uop_iw_state}}; // @[lsu.scala:209:16, :222:42] wire [7:0] _GEN_19 = {{stq_7_bits_uop_iw_p1_poisoned}, {stq_6_bits_uop_iw_p1_poisoned}, {stq_5_bits_uop_iw_p1_poisoned}, {stq_4_bits_uop_iw_p1_poisoned}, {stq_3_bits_uop_iw_p1_poisoned}, {stq_2_bits_uop_iw_p1_poisoned}, {stq_1_bits_uop_iw_p1_poisoned}, {stq_0_bits_uop_iw_p1_poisoned}}; // @[lsu.scala:209:16, :222:42] wire [7:0] _GEN_20 = {{stq_7_bits_uop_iw_p2_poisoned}, {stq_6_bits_uop_iw_p2_poisoned}, {stq_5_bits_uop_iw_p2_poisoned}, {stq_4_bits_uop_iw_p2_poisoned}, {stq_3_bits_uop_iw_p2_poisoned}, {stq_2_bits_uop_iw_p2_poisoned}, {stq_1_bits_uop_iw_p2_poisoned}, {stq_0_bits_uop_iw_p2_poisoned}}; // @[lsu.scala:209:16, :222:42] wire [7:0] _GEN_21 = {{stq_7_bits_uop_is_br}, {stq_6_bits_uop_is_br}, {stq_5_bits_uop_is_br}, {stq_4_bits_uop_is_br}, {stq_3_bits_uop_is_br}, {stq_2_bits_uop_is_br}, {stq_1_bits_uop_is_br}, {stq_0_bits_uop_is_br}}; // @[lsu.scala:209:16, :222:42] wire [7:0] _GEN_22 = {{stq_7_bits_uop_is_jalr}, {stq_6_bits_uop_is_jalr}, {stq_5_bits_uop_is_jalr}, {stq_4_bits_uop_is_jalr}, {stq_3_bits_uop_is_jalr}, {stq_2_bits_uop_is_jalr}, {stq_1_bits_uop_is_jalr}, {stq_0_bits_uop_is_jalr}}; // @[lsu.scala:209:16, :222:42] wire [7:0] _GEN_23 = {{stq_7_bits_uop_is_jal}, {stq_6_bits_uop_is_jal}, {stq_5_bits_uop_is_jal}, {stq_4_bits_uop_is_jal}, {stq_3_bits_uop_is_jal}, {stq_2_bits_uop_is_jal}, {stq_1_bits_uop_is_jal}, {stq_0_bits_uop_is_jal}}; // @[lsu.scala:209:16, :222:42] wire [7:0] _GEN_24 = {{stq_7_bits_uop_is_sfb}, {stq_6_bits_uop_is_sfb}, {stq_5_bits_uop_is_sfb}, {stq_4_bits_uop_is_sfb}, {stq_3_bits_uop_is_sfb}, {stq_2_bits_uop_is_sfb}, {stq_1_bits_uop_is_sfb}, {stq_0_bits_uop_is_sfb}}; // @[lsu.scala:209:16, :222:42] wire [7:0][7:0] _GEN_25 = {{stq_7_bits_uop_br_mask}, {stq_6_bits_uop_br_mask}, {stq_5_bits_uop_br_mask}, {stq_4_bits_uop_br_mask}, {stq_3_bits_uop_br_mask}, {stq_2_bits_uop_br_mask}, {stq_1_bits_uop_br_mask}, {stq_0_bits_uop_br_mask}}; // @[lsu.scala:209:16, :222:42] wire [7:0][2:0] _GEN_26 = {{stq_7_bits_uop_br_tag}, {stq_6_bits_uop_br_tag}, {stq_5_bits_uop_br_tag}, {stq_4_bits_uop_br_tag}, {stq_3_bits_uop_br_tag}, {stq_2_bits_uop_br_tag}, {stq_1_bits_uop_br_tag}, {stq_0_bits_uop_br_tag}}; // @[lsu.scala:209:16, :222:42] wire [7:0][3:0] _GEN_27 = {{stq_7_bits_uop_ftq_idx}, {stq_6_bits_uop_ftq_idx}, {stq_5_bits_uop_ftq_idx}, {stq_4_bits_uop_ftq_idx}, {stq_3_bits_uop_ftq_idx}, {stq_2_bits_uop_ftq_idx}, {stq_1_bits_uop_ftq_idx}, {stq_0_bits_uop_ftq_idx}}; // @[lsu.scala:209:16, :222:42] wire [7:0] _GEN_28 = {{stq_7_bits_uop_edge_inst}, {stq_6_bits_uop_edge_inst}, {stq_5_bits_uop_edge_inst}, {stq_4_bits_uop_edge_inst}, {stq_3_bits_uop_edge_inst}, {stq_2_bits_uop_edge_inst}, {stq_1_bits_uop_edge_inst}, {stq_0_bits_uop_edge_inst}}; // @[lsu.scala:209:16, :222:42] wire [7:0][5:0] _GEN_29 = {{stq_7_bits_uop_pc_lob}, {stq_6_bits_uop_pc_lob}, {stq_5_bits_uop_pc_lob}, {stq_4_bits_uop_pc_lob}, {stq_3_bits_uop_pc_lob}, {stq_2_bits_uop_pc_lob}, {stq_1_bits_uop_pc_lob}, {stq_0_bits_uop_pc_lob}}; // @[lsu.scala:209:16, :222:42] wire [7:0] _GEN_30 = {{stq_7_bits_uop_taken}, {stq_6_bits_uop_taken}, {stq_5_bits_uop_taken}, {stq_4_bits_uop_taken}, {stq_3_bits_uop_taken}, {stq_2_bits_uop_taken}, {stq_1_bits_uop_taken}, {stq_0_bits_uop_taken}}; // @[lsu.scala:209:16, :222:42] wire [7:0][19:0] _GEN_31 = {{stq_7_bits_uop_imm_packed}, {stq_6_bits_uop_imm_packed}, {stq_5_bits_uop_imm_packed}, {stq_4_bits_uop_imm_packed}, {stq_3_bits_uop_imm_packed}, {stq_2_bits_uop_imm_packed}, {stq_1_bits_uop_imm_packed}, {stq_0_bits_uop_imm_packed}}; // @[lsu.scala:209:16, :222:42] wire [7:0][11:0] _GEN_32 = {{stq_7_bits_uop_csr_addr}, {stq_6_bits_uop_csr_addr}, {stq_5_bits_uop_csr_addr}, {stq_4_bits_uop_csr_addr}, {stq_3_bits_uop_csr_addr}, {stq_2_bits_uop_csr_addr}, {stq_1_bits_uop_csr_addr}, {stq_0_bits_uop_csr_addr}}; // @[lsu.scala:209:16, :222:42] wire [7:0][4:0] _GEN_33 = {{stq_7_bits_uop_rob_idx}, {stq_6_bits_uop_rob_idx}, {stq_5_bits_uop_rob_idx}, {stq_4_bits_uop_rob_idx}, {stq_3_bits_uop_rob_idx}, {stq_2_bits_uop_rob_idx}, {stq_1_bits_uop_rob_idx}, {stq_0_bits_uop_rob_idx}}; // @[lsu.scala:209:16, :222:42] wire [7:0][2:0] _GEN_34 = {{stq_7_bits_uop_ldq_idx}, {stq_6_bits_uop_ldq_idx}, {stq_5_bits_uop_ldq_idx}, {stq_4_bits_uop_ldq_idx}, {stq_3_bits_uop_ldq_idx}, {stq_2_bits_uop_ldq_idx}, {stq_1_bits_uop_ldq_idx}, {stq_0_bits_uop_ldq_idx}}; // @[lsu.scala:209:16, :222:42] wire [7:0][2:0] _GEN_35 = {{stq_7_bits_uop_stq_idx}, {stq_6_bits_uop_stq_idx}, {stq_5_bits_uop_stq_idx}, {stq_4_bits_uop_stq_idx}, {stq_3_bits_uop_stq_idx}, {stq_2_bits_uop_stq_idx}, {stq_1_bits_uop_stq_idx}, {stq_0_bits_uop_stq_idx}}; // @[lsu.scala:209:16, :222:42] wire [7:0][1:0] _GEN_36 = {{stq_7_bits_uop_rxq_idx}, {stq_6_bits_uop_rxq_idx}, {stq_5_bits_uop_rxq_idx}, {stq_4_bits_uop_rxq_idx}, {stq_3_bits_uop_rxq_idx}, {stq_2_bits_uop_rxq_idx}, {stq_1_bits_uop_rxq_idx}, {stq_0_bits_uop_rxq_idx}}; // @[lsu.scala:209:16, :222:42] wire [7:0][5:0] _GEN_37 = {{stq_7_bits_uop_pdst}, {stq_6_bits_uop_pdst}, {stq_5_bits_uop_pdst}, {stq_4_bits_uop_pdst}, {stq_3_bits_uop_pdst}, {stq_2_bits_uop_pdst}, {stq_1_bits_uop_pdst}, {stq_0_bits_uop_pdst}}; // @[lsu.scala:209:16, :222:42] wire [7:0][5:0] _GEN_38 = {{stq_7_bits_uop_prs1}, {stq_6_bits_uop_prs1}, {stq_5_bits_uop_prs1}, {stq_4_bits_uop_prs1}, {stq_3_bits_uop_prs1}, {stq_2_bits_uop_prs1}, {stq_1_bits_uop_prs1}, {stq_0_bits_uop_prs1}}; // @[lsu.scala:209:16, :222:42] wire [7:0][5:0] _GEN_39 = {{stq_7_bits_uop_prs2}, {stq_6_bits_uop_prs2}, {stq_5_bits_uop_prs2}, {stq_4_bits_uop_prs2}, {stq_3_bits_uop_prs2}, {stq_2_bits_uop_prs2}, {stq_1_bits_uop_prs2}, {stq_0_bits_uop_prs2}}; // @[lsu.scala:209:16, :222:42] wire [7:0][5:0] _GEN_40 = {{stq_7_bits_uop_prs3}, {stq_6_bits_uop_prs3}, {stq_5_bits_uop_prs3}, {stq_4_bits_uop_prs3}, {stq_3_bits_uop_prs3}, {stq_2_bits_uop_prs3}, {stq_1_bits_uop_prs3}, {stq_0_bits_uop_prs3}}; // @[lsu.scala:209:16, :222:42] wire [7:0][3:0] _GEN_41 = {{stq_7_bits_uop_ppred}, {stq_6_bits_uop_ppred}, {stq_5_bits_uop_ppred}, {stq_4_bits_uop_ppred}, {stq_3_bits_uop_ppred}, {stq_2_bits_uop_ppred}, {stq_1_bits_uop_ppred}, {stq_0_bits_uop_ppred}}; // @[lsu.scala:209:16, :222:42] wire [7:0] _GEN_42 = {{stq_7_bits_uop_prs1_busy}, {stq_6_bits_uop_prs1_busy}, {stq_5_bits_uop_prs1_busy}, {stq_4_bits_uop_prs1_busy}, {stq_3_bits_uop_prs1_busy}, {stq_2_bits_uop_prs1_busy}, {stq_1_bits_uop_prs1_busy}, {stq_0_bits_uop_prs1_busy}}; // @[lsu.scala:209:16, :222:42] wire [7:0] _GEN_43 = {{stq_7_bits_uop_prs2_busy}, {stq_6_bits_uop_prs2_busy}, {stq_5_bits_uop_prs2_busy}, {stq_4_bits_uop_prs2_busy}, {stq_3_bits_uop_prs2_busy}, {stq_2_bits_uop_prs2_busy}, {stq_1_bits_uop_prs2_busy}, {stq_0_bits_uop_prs2_busy}}; // @[lsu.scala:209:16, :222:42] wire [7:0] _GEN_44 = {{stq_7_bits_uop_prs3_busy}, {stq_6_bits_uop_prs3_busy}, {stq_5_bits_uop_prs3_busy}, {stq_4_bits_uop_prs3_busy}, {stq_3_bits_uop_prs3_busy}, {stq_2_bits_uop_prs3_busy}, {stq_1_bits_uop_prs3_busy}, {stq_0_bits_uop_prs3_busy}}; // @[lsu.scala:209:16, :222:42] wire [7:0] _GEN_45 = {{stq_7_bits_uop_ppred_busy}, {stq_6_bits_uop_ppred_busy}, {stq_5_bits_uop_ppred_busy}, {stq_4_bits_uop_ppred_busy}, {stq_3_bits_uop_ppred_busy}, {stq_2_bits_uop_ppred_busy}, {stq_1_bits_uop_ppred_busy}, {stq_0_bits_uop_ppred_busy}}; // @[lsu.scala:209:16, :222:42] wire [7:0][5:0] _GEN_46 = {{stq_7_bits_uop_stale_pdst}, {stq_6_bits_uop_stale_pdst}, {stq_5_bits_uop_stale_pdst}, {stq_4_bits_uop_stale_pdst}, {stq_3_bits_uop_stale_pdst}, {stq_2_bits_uop_stale_pdst}, {stq_1_bits_uop_stale_pdst}, {stq_0_bits_uop_stale_pdst}}; // @[lsu.scala:209:16, :222:42] wire [7:0] _GEN_47 = {{stq_7_bits_uop_exception}, {stq_6_bits_uop_exception}, {stq_5_bits_uop_exception}, {stq_4_bits_uop_exception}, {stq_3_bits_uop_exception}, {stq_2_bits_uop_exception}, {stq_1_bits_uop_exception}, {stq_0_bits_uop_exception}}; // @[lsu.scala:209:16, :222:42] wire _GEN_48 = _GEN_47[stq_execute_head]; // @[lsu.scala:218:29, :222:42] wire [7:0][63:0] _GEN_49 = {{stq_7_bits_uop_exc_cause}, {stq_6_bits_uop_exc_cause}, {stq_5_bits_uop_exc_cause}, {stq_4_bits_uop_exc_cause}, {stq_3_bits_uop_exc_cause}, {stq_2_bits_uop_exc_cause}, {stq_1_bits_uop_exc_cause}, {stq_0_bits_uop_exc_cause}}; // @[lsu.scala:209:16, :222:42] wire [7:0] _GEN_50 = {{stq_7_bits_uop_bypassable}, {stq_6_bits_uop_bypassable}, {stq_5_bits_uop_bypassable}, {stq_4_bits_uop_bypassable}, {stq_3_bits_uop_bypassable}, {stq_2_bits_uop_bypassable}, {stq_1_bits_uop_bypassable}, {stq_0_bits_uop_bypassable}}; // @[lsu.scala:209:16, :222:42] wire [7:0][4:0] _GEN_51 = {{stq_7_bits_uop_mem_cmd}, {stq_6_bits_uop_mem_cmd}, {stq_5_bits_uop_mem_cmd}, {stq_4_bits_uop_mem_cmd}, {stq_3_bits_uop_mem_cmd}, {stq_2_bits_uop_mem_cmd}, {stq_1_bits_uop_mem_cmd}, {stq_0_bits_uop_mem_cmd}}; // @[lsu.scala:209:16, :222:42] wire [7:0][1:0] _GEN_52 = {{stq_7_bits_uop_mem_size}, {stq_6_bits_uop_mem_size}, {stq_5_bits_uop_mem_size}, {stq_4_bits_uop_mem_size}, {stq_3_bits_uop_mem_size}, {stq_2_bits_uop_mem_size}, {stq_1_bits_uop_mem_size}, {stq_0_bits_uop_mem_size}}; // @[lsu.scala:209:16, :222:42] wire [1:0] dmem_req_0_bits_data_size = _GEN_52[stq_execute_head]; // @[AMOALU.scala:11:18] wire [7:0] _GEN_53 = {{stq_7_bits_uop_mem_signed}, {stq_6_bits_uop_mem_signed}, {stq_5_bits_uop_mem_signed}, {stq_4_bits_uop_mem_signed}, {stq_3_bits_uop_mem_signed}, {stq_2_bits_uop_mem_signed}, {stq_1_bits_uop_mem_signed}, {stq_0_bits_uop_mem_signed}}; // @[lsu.scala:209:16, :222:42] wire [7:0] _GEN_54 = {{stq_7_bits_uop_is_fence}, {stq_6_bits_uop_is_fence}, {stq_5_bits_uop_is_fence}, {stq_4_bits_uop_is_fence}, {stq_3_bits_uop_is_fence}, {stq_2_bits_uop_is_fence}, {stq_1_bits_uop_is_fence}, {stq_0_bits_uop_is_fence}}; // @[lsu.scala:209:16, :222:42] wire _GEN_55 = _GEN_54[stq_execute_head]; // @[lsu.scala:218:29, :222:42] wire [7:0] _GEN_56 = {{stq_7_bits_uop_is_fencei}, {stq_6_bits_uop_is_fencei}, {stq_5_bits_uop_is_fencei}, {stq_4_bits_uop_is_fencei}, {stq_3_bits_uop_is_fencei}, {stq_2_bits_uop_is_fencei}, {stq_1_bits_uop_is_fencei}, {stq_0_bits_uop_is_fencei}}; // @[lsu.scala:209:16, :222:42] wire [7:0] _GEN_57 = {{stq_7_bits_uop_is_amo}, {stq_6_bits_uop_is_amo}, {stq_5_bits_uop_is_amo}, {stq_4_bits_uop_is_amo}, {stq_3_bits_uop_is_amo}, {stq_2_bits_uop_is_amo}, {stq_1_bits_uop_is_amo}, {stq_0_bits_uop_is_amo}}; // @[lsu.scala:209:16, :222:42] wire _GEN_58 = _GEN_57[stq_execute_head]; // @[lsu.scala:218:29, :222:42] wire [7:0] _GEN_59 = {{stq_7_bits_uop_uses_ldq}, {stq_6_bits_uop_uses_ldq}, {stq_5_bits_uop_uses_ldq}, {stq_4_bits_uop_uses_ldq}, {stq_3_bits_uop_uses_ldq}, {stq_2_bits_uop_uses_ldq}, {stq_1_bits_uop_uses_ldq}, {stq_0_bits_uop_uses_ldq}}; // @[lsu.scala:209:16, :222:42] wire [7:0] _GEN_60 = {{stq_7_bits_uop_uses_stq}, {stq_6_bits_uop_uses_stq}, {stq_5_bits_uop_uses_stq}, {stq_4_bits_uop_uses_stq}, {stq_3_bits_uop_uses_stq}, {stq_2_bits_uop_uses_stq}, {stq_1_bits_uop_uses_stq}, {stq_0_bits_uop_uses_stq}}; // @[lsu.scala:209:16, :222:42] wire [7:0] _GEN_61 = {{stq_7_bits_uop_is_sys_pc2epc}, {stq_6_bits_uop_is_sys_pc2epc}, {stq_5_bits_uop_is_sys_pc2epc}, {stq_4_bits_uop_is_sys_pc2epc}, {stq_3_bits_uop_is_sys_pc2epc}, {stq_2_bits_uop_is_sys_pc2epc}, {stq_1_bits_uop_is_sys_pc2epc}, {stq_0_bits_uop_is_sys_pc2epc}}; // @[lsu.scala:209:16, :222:42] wire [7:0] _GEN_62 = {{stq_7_bits_uop_is_unique}, {stq_6_bits_uop_is_unique}, {stq_5_bits_uop_is_unique}, {stq_4_bits_uop_is_unique}, {stq_3_bits_uop_is_unique}, {stq_2_bits_uop_is_unique}, {stq_1_bits_uop_is_unique}, {stq_0_bits_uop_is_unique}}; // @[lsu.scala:209:16, :222:42] wire [7:0] _GEN_63 = {{stq_7_bits_uop_flush_on_commit}, {stq_6_bits_uop_flush_on_commit}, {stq_5_bits_uop_flush_on_commit}, {stq_4_bits_uop_flush_on_commit}, {stq_3_bits_uop_flush_on_commit}, {stq_2_bits_uop_flush_on_commit}, {stq_1_bits_uop_flush_on_commit}, {stq_0_bits_uop_flush_on_commit}}; // @[lsu.scala:209:16, :222:42] wire [7:0] _GEN_64 = {{stq_7_bits_uop_ldst_is_rs1}, {stq_6_bits_uop_ldst_is_rs1}, {stq_5_bits_uop_ldst_is_rs1}, {stq_4_bits_uop_ldst_is_rs1}, {stq_3_bits_uop_ldst_is_rs1}, {stq_2_bits_uop_ldst_is_rs1}, {stq_1_bits_uop_ldst_is_rs1}, {stq_0_bits_uop_ldst_is_rs1}}; // @[lsu.scala:209:16, :222:42] wire [7:0][5:0] _GEN_65 = {{stq_7_bits_uop_ldst}, {stq_6_bits_uop_ldst}, {stq_5_bits_uop_ldst}, {stq_4_bits_uop_ldst}, {stq_3_bits_uop_ldst}, {stq_2_bits_uop_ldst}, {stq_1_bits_uop_ldst}, {stq_0_bits_uop_ldst}}; // @[lsu.scala:209:16, :222:42] wire [7:0][5:0] _GEN_66 = {{stq_7_bits_uop_lrs1}, {stq_6_bits_uop_lrs1}, {stq_5_bits_uop_lrs1}, {stq_4_bits_uop_lrs1}, {stq_3_bits_uop_lrs1}, {stq_2_bits_uop_lrs1}, {stq_1_bits_uop_lrs1}, {stq_0_bits_uop_lrs1}}; // @[lsu.scala:209:16, :222:42] wire [7:0][5:0] _GEN_67 = {{stq_7_bits_uop_lrs2}, {stq_6_bits_uop_lrs2}, {stq_5_bits_uop_lrs2}, {stq_4_bits_uop_lrs2}, {stq_3_bits_uop_lrs2}, {stq_2_bits_uop_lrs2}, {stq_1_bits_uop_lrs2}, {stq_0_bits_uop_lrs2}}; // @[lsu.scala:209:16, :222:42] wire [7:0][5:0] _GEN_68 = {{stq_7_bits_uop_lrs3}, {stq_6_bits_uop_lrs3}, {stq_5_bits_uop_lrs3}, {stq_4_bits_uop_lrs3}, {stq_3_bits_uop_lrs3}, {stq_2_bits_uop_lrs3}, {stq_1_bits_uop_lrs3}, {stq_0_bits_uop_lrs3}}; // @[lsu.scala:209:16, :222:42] wire [7:0] _GEN_69 = {{stq_7_bits_uop_ldst_val}, {stq_6_bits_uop_ldst_val}, {stq_5_bits_uop_ldst_val}, {stq_4_bits_uop_ldst_val}, {stq_3_bits_uop_ldst_val}, {stq_2_bits_uop_ldst_val}, {stq_1_bits_uop_ldst_val}, {stq_0_bits_uop_ldst_val}}; // @[lsu.scala:209:16, :222:42] wire [7:0][1:0] _GEN_70 = {{stq_7_bits_uop_dst_rtype}, {stq_6_bits_uop_dst_rtype}, {stq_5_bits_uop_dst_rtype}, {stq_4_bits_uop_dst_rtype}, {stq_3_bits_uop_dst_rtype}, {stq_2_bits_uop_dst_rtype}, {stq_1_bits_uop_dst_rtype}, {stq_0_bits_uop_dst_rtype}}; // @[lsu.scala:209:16, :222:42] wire [7:0][1:0] _GEN_71 = {{stq_7_bits_uop_lrs1_rtype}, {stq_6_bits_uop_lrs1_rtype}, {stq_5_bits_uop_lrs1_rtype}, {stq_4_bits_uop_lrs1_rtype}, {stq_3_bits_uop_lrs1_rtype}, {stq_2_bits_uop_lrs1_rtype}, {stq_1_bits_uop_lrs1_rtype}, {stq_0_bits_uop_lrs1_rtype}}; // @[lsu.scala:209:16, :222:42] wire [7:0][1:0] _GEN_72 = {{stq_7_bits_uop_lrs2_rtype}, {stq_6_bits_uop_lrs2_rtype}, {stq_5_bits_uop_lrs2_rtype}, {stq_4_bits_uop_lrs2_rtype}, {stq_3_bits_uop_lrs2_rtype}, {stq_2_bits_uop_lrs2_rtype}, {stq_1_bits_uop_lrs2_rtype}, {stq_0_bits_uop_lrs2_rtype}}; // @[lsu.scala:209:16, :222:42] wire [7:0] _GEN_73 = {{stq_7_bits_uop_frs3_en}, {stq_6_bits_uop_frs3_en}, {stq_5_bits_uop_frs3_en}, {stq_4_bits_uop_frs3_en}, {stq_3_bits_uop_frs3_en}, {stq_2_bits_uop_frs3_en}, {stq_1_bits_uop_frs3_en}, {stq_0_bits_uop_frs3_en}}; // @[lsu.scala:209:16, :222:42] wire [7:0] _GEN_74 = {{stq_7_bits_uop_fp_val}, {stq_6_bits_uop_fp_val}, {stq_5_bits_uop_fp_val}, {stq_4_bits_uop_fp_val}, {stq_3_bits_uop_fp_val}, {stq_2_bits_uop_fp_val}, {stq_1_bits_uop_fp_val}, {stq_0_bits_uop_fp_val}}; // @[lsu.scala:209:16, :222:42] wire [7:0] _GEN_75 = {{stq_7_bits_uop_fp_single}, {stq_6_bits_uop_fp_single}, {stq_5_bits_uop_fp_single}, {stq_4_bits_uop_fp_single}, {stq_3_bits_uop_fp_single}, {stq_2_bits_uop_fp_single}, {stq_1_bits_uop_fp_single}, {stq_0_bits_uop_fp_single}}; // @[lsu.scala:209:16, :222:42] wire [7:0] _GEN_76 = {{stq_7_bits_uop_xcpt_pf_if}, {stq_6_bits_uop_xcpt_pf_if}, {stq_5_bits_uop_xcpt_pf_if}, {stq_4_bits_uop_xcpt_pf_if}, {stq_3_bits_uop_xcpt_pf_if}, {stq_2_bits_uop_xcpt_pf_if}, {stq_1_bits_uop_xcpt_pf_if}, {stq_0_bits_uop_xcpt_pf_if}}; // @[lsu.scala:209:16, :222:42] wire [7:0] _GEN_77 = {{stq_7_bits_uop_xcpt_ae_if}, {stq_6_bits_uop_xcpt_ae_if}, {stq_5_bits_uop_xcpt_ae_if}, {stq_4_bits_uop_xcpt_ae_if}, {stq_3_bits_uop_xcpt_ae_if}, {stq_2_bits_uop_xcpt_ae_if}, {stq_1_bits_uop_xcpt_ae_if}, {stq_0_bits_uop_xcpt_ae_if}}; // @[lsu.scala:209:16, :222:42] wire [7:0] _GEN_78 = {{stq_7_bits_uop_xcpt_ma_if}, {stq_6_bits_uop_xcpt_ma_if}, {stq_5_bits_uop_xcpt_ma_if}, {stq_4_bits_uop_xcpt_ma_if}, {stq_3_bits_uop_xcpt_ma_if}, {stq_2_bits_uop_xcpt_ma_if}, {stq_1_bits_uop_xcpt_ma_if}, {stq_0_bits_uop_xcpt_ma_if}}; // @[lsu.scala:209:16, :222:42] wire [7:0] _GEN_79 = {{stq_7_bits_uop_bp_debug_if}, {stq_6_bits_uop_bp_debug_if}, {stq_5_bits_uop_bp_debug_if}, {stq_4_bits_uop_bp_debug_if}, {stq_3_bits_uop_bp_debug_if}, {stq_2_bits_uop_bp_debug_if}, {stq_1_bits_uop_bp_debug_if}, {stq_0_bits_uop_bp_debug_if}}; // @[lsu.scala:209:16, :222:42] wire [7:0] _GEN_80 = {{stq_7_bits_uop_bp_xcpt_if}, {stq_6_bits_uop_bp_xcpt_if}, {stq_5_bits_uop_bp_xcpt_if}, {stq_4_bits_uop_bp_xcpt_if}, {stq_3_bits_uop_bp_xcpt_if}, {stq_2_bits_uop_bp_xcpt_if}, {stq_1_bits_uop_bp_xcpt_if}, {stq_0_bits_uop_bp_xcpt_if}}; // @[lsu.scala:209:16, :222:42] wire [7:0][1:0] _GEN_81 = {{stq_7_bits_uop_debug_fsrc}, {stq_6_bits_uop_debug_fsrc}, {stq_5_bits_uop_debug_fsrc}, {stq_4_bits_uop_debug_fsrc}, {stq_3_bits_uop_debug_fsrc}, {stq_2_bits_uop_debug_fsrc}, {stq_1_bits_uop_debug_fsrc}, {stq_0_bits_uop_debug_fsrc}}; // @[lsu.scala:209:16, :222:42] wire [7:0][1:0] _GEN_82 = {{stq_7_bits_uop_debug_tsrc}, {stq_6_bits_uop_debug_tsrc}, {stq_5_bits_uop_debug_tsrc}, {stq_4_bits_uop_debug_tsrc}, {stq_3_bits_uop_debug_tsrc}, {stq_2_bits_uop_debug_tsrc}, {stq_1_bits_uop_debug_tsrc}, {stq_0_bits_uop_debug_tsrc}}; // @[lsu.scala:209:16, :222:42] wire [7:0] _GEN_83 = {{stq_7_bits_addr_valid}, {stq_6_bits_addr_valid}, {stq_5_bits_addr_valid}, {stq_4_bits_addr_valid}, {stq_3_bits_addr_valid}, {stq_2_bits_addr_valid}, {stq_1_bits_addr_valid}, {stq_0_bits_addr_valid}}; // @[lsu.scala:209:16, :222:42] wire [7:0][39:0] _GEN_84 = {{stq_7_bits_addr_bits}, {stq_6_bits_addr_bits}, {stq_5_bits_addr_bits}, {stq_4_bits_addr_bits}, {stq_3_bits_addr_bits}, {stq_2_bits_addr_bits}, {stq_1_bits_addr_bits}, {stq_0_bits_addr_bits}}; // @[lsu.scala:209:16, :222:42] wire [7:0] _GEN_85 = {{stq_7_bits_addr_is_virtual}, {stq_6_bits_addr_is_virtual}, {stq_5_bits_addr_is_virtual}, {stq_4_bits_addr_is_virtual}, {stq_3_bits_addr_is_virtual}, {stq_2_bits_addr_is_virtual}, {stq_1_bits_addr_is_virtual}, {stq_0_bits_addr_is_virtual}}; // @[lsu.scala:209:16, :222:42] wire [7:0] _GEN_86 = {{stq_7_bits_data_valid}, {stq_6_bits_data_valid}, {stq_5_bits_data_valid}, {stq_4_bits_data_valid}, {stq_3_bits_data_valid}, {stq_2_bits_data_valid}, {stq_1_bits_data_valid}, {stq_0_bits_data_valid}}; // @[lsu.scala:209:16, :222:42] wire [7:0][63:0] _GEN_87 = {{stq_7_bits_data_bits}, {stq_6_bits_data_bits}, {stq_5_bits_data_bits}, {stq_4_bits_data_bits}, {stq_3_bits_data_bits}, {stq_2_bits_data_bits}, {stq_1_bits_data_bits}, {stq_0_bits_data_bits}}; // @[lsu.scala:209:16, :222:42] wire [63:0] _GEN_88 = _GEN_87[stq_execute_head]; // @[lsu.scala:218:29, :222:42] wire [7:0] _GEN_89 = {{stq_7_bits_committed}, {stq_6_bits_committed}, {stq_5_bits_committed}, {stq_4_bits_committed}, {stq_3_bits_committed}, {stq_2_bits_committed}, {stq_1_bits_committed}, {stq_0_bits_committed}}; // @[lsu.scala:209:16, :222:42] reg [2:0] hella_state; // @[lsu.scala:240:38] reg [39:0] hella_req_addr; // @[lsu.scala:241:34] assign io_hellacache_resp_bits_addr_0 = hella_req_addr; // @[lsu.scala:201:7, :241:34] reg hella_req_dv; // @[lsu.scala:241:34] reg [63:0] hella_data_data; // @[lsu.scala:242:34] wire [63:0] _dmem_req_0_bits_data_T_42 = hella_data_data; // @[AMOALU.scala:29:13] reg [7:0] hella_data_mask; // @[lsu.scala:242:34] reg [31:0] hella_paddr; // @[lsu.scala:243:34] reg hella_xcpt_ma_ld; // @[lsu.scala:244:34] reg hella_xcpt_ma_st; // @[lsu.scala:244:34] reg hella_xcpt_pf_ld; // @[lsu.scala:244:34] reg hella_xcpt_pf_st; // @[lsu.scala:244:34] reg hella_xcpt_gf_ld; // @[lsu.scala:244:34] reg hella_xcpt_gf_st; // @[lsu.scala:244:34] reg hella_xcpt_ae_ld; // @[lsu.scala:244:34] reg hella_xcpt_ae_st; // @[lsu.scala:244:34] assign _io_core_perf_tlbMiss_T = io_ptw_req_ready_0 & io_ptw_req_valid_0; // @[Decoupled.scala:51:35] assign io_core_perf_tlbMiss_0 = _io_core_perf_tlbMiss_T; // @[Decoupled.scala:51:35] wire clear_store; // @[lsu.scala:257:33] reg [7:0] live_store_mask; // @[lsu.scala:258:32] wire [7:0] _GEN_90 = 8'h1 << stq_head; // @[lsu.scala:215:29, :259:71] wire [7:0] _next_live_store_mask_T; // @[lsu.scala:259:71] assign _next_live_store_mask_T = _GEN_90; // @[lsu.scala:259:71] wire [7:0] _ldq_0_bits_st_dep_mask_T; // @[lsu.scala:277:66] assign _ldq_0_bits_st_dep_mask_T = _GEN_90; // @[lsu.scala:259:71, :277:66] wire [7:0] _ldq_1_bits_st_dep_mask_T; // @[lsu.scala:277:66] assign _ldq_1_bits_st_dep_mask_T = _GEN_90; // @[lsu.scala:259:71, :277:66] wire [7:0] _ldq_2_bits_st_dep_mask_T; // @[lsu.scala:277:66] assign _ldq_2_bits_st_dep_mask_T = _GEN_90; // @[lsu.scala:259:71, :277:66] wire [7:0] _ldq_3_bits_st_dep_mask_T; // @[lsu.scala:277:66] assign _ldq_3_bits_st_dep_mask_T = _GEN_90; // @[lsu.scala:259:71, :277:66] wire [7:0] _ldq_4_bits_st_dep_mask_T; // @[lsu.scala:277:66] assign _ldq_4_bits_st_dep_mask_T = _GEN_90; // @[lsu.scala:259:71, :277:66] wire [7:0] _ldq_5_bits_st_dep_mask_T; // @[lsu.scala:277:66] assign _ldq_5_bits_st_dep_mask_T = _GEN_90; // @[lsu.scala:259:71, :277:66] wire [7:0] _ldq_6_bits_st_dep_mask_T; // @[lsu.scala:277:66] assign _ldq_6_bits_st_dep_mask_T = _GEN_90; // @[lsu.scala:259:71, :277:66] wire [7:0] _ldq_7_bits_st_dep_mask_T; // @[lsu.scala:277:66] assign _ldq_7_bits_st_dep_mask_T = _GEN_90; // @[lsu.scala:259:71, :277:66] wire [7:0] _next_live_store_mask_T_1 = ~_next_live_store_mask_T; // @[lsu.scala:259:{65,71}] wire [7:0] _next_live_store_mask_T_2 = live_store_mask & _next_live_store_mask_T_1; // @[lsu.scala:258:32, :259:{63,65}] wire [7:0] next_live_store_mask = clear_store ? _next_live_store_mask_T_2 : live_store_mask; // @[lsu.scala:257:33, :258:32, :259:{33,63}] wire [7:0] _ldq_0_bits_st_dep_mask_T_1 = ~_ldq_0_bits_st_dep_mask_T; // @[lsu.scala:277:{60,66}] wire [7:0] _ldq_0_bits_st_dep_mask_T_2 = ldq_0_bits_st_dep_mask & _ldq_0_bits_st_dep_mask_T_1; // @[lsu.scala:208:16, :277:{58,60}] wire [7:0] _ldq_1_bits_st_dep_mask_T_1 = ~_ldq_1_bits_st_dep_mask_T; // @[lsu.scala:277:{60,66}] wire [7:0] _ldq_1_bits_st_dep_mask_T_2 = ldq_1_bits_st_dep_mask & _ldq_1_bits_st_dep_mask_T_1; // @[lsu.scala:208:16, :277:{58,60}] wire [7:0] _ldq_2_bits_st_dep_mask_T_1 = ~_ldq_2_bits_st_dep_mask_T; // @[lsu.scala:277:{60,66}] wire [7:0] _ldq_2_bits_st_dep_mask_T_2 = ldq_2_bits_st_dep_mask & _ldq_2_bits_st_dep_mask_T_1; // @[lsu.scala:208:16, :277:{58,60}] wire [7:0] _ldq_3_bits_st_dep_mask_T_1 = ~_ldq_3_bits_st_dep_mask_T; // @[lsu.scala:277:{60,66}] wire [7:0] _ldq_3_bits_st_dep_mask_T_2 = ldq_3_bits_st_dep_mask & _ldq_3_bits_st_dep_mask_T_1; // @[lsu.scala:208:16, :277:{58,60}] wire [7:0] _ldq_4_bits_st_dep_mask_T_1 = ~_ldq_4_bits_st_dep_mask_T; // @[lsu.scala:277:{60,66}] wire [7:0] _ldq_4_bits_st_dep_mask_T_2 = ldq_4_bits_st_dep_mask & _ldq_4_bits_st_dep_mask_T_1; // @[lsu.scala:208:16, :277:{58,60}] wire [7:0] _ldq_5_bits_st_dep_mask_T_1 = ~_ldq_5_bits_st_dep_mask_T; // @[lsu.scala:277:{60,66}] wire [7:0] _ldq_5_bits_st_dep_mask_T_2 = ldq_5_bits_st_dep_mask & _ldq_5_bits_st_dep_mask_T_1; // @[lsu.scala:208:16, :277:{58,60}] wire [7:0] _ldq_6_bits_st_dep_mask_T_1 = ~_ldq_6_bits_st_dep_mask_T; // @[lsu.scala:277:{60,66}] wire [7:0] _ldq_6_bits_st_dep_mask_T_2 = ldq_6_bits_st_dep_mask & _ldq_6_bits_st_dep_mask_T_1; // @[lsu.scala:208:16, :277:{58,60}] wire [7:0] _ldq_7_bits_st_dep_mask_T_1 = ~_ldq_7_bits_st_dep_mask_T; // @[lsu.scala:277:{60,66}] wire [7:0] _ldq_7_bits_st_dep_mask_T_2 = ldq_7_bits_st_dep_mask & _ldq_7_bits_st_dep_mask_T_1; // @[lsu.scala:208:16, :277:{58,60}] wire _GEN_91 = stq_0_valid | stq_1_valid; // @[lsu.scala:209:16, :285:79] wire _stq_nonempty_T; // @[lsu.scala:285:79] assign _stq_nonempty_T = _GEN_91; // @[lsu.scala:285:79] wire _io_hellacache_store_pending_T; // @[lsu.scala:1530:59] assign _io_hellacache_store_pending_T = _GEN_91; // @[lsu.scala:285:79, :1530:59] wire _stq_nonempty_T_1 = _stq_nonempty_T | stq_2_valid; // @[lsu.scala:209:16, :285:79] wire _stq_nonempty_T_2 = _stq_nonempty_T_1 | stq_3_valid; // @[lsu.scala:209:16, :285:79] wire _stq_nonempty_T_3 = _stq_nonempty_T_2 | stq_4_valid; // @[lsu.scala:209:16, :285:79] wire _stq_nonempty_T_4 = _stq_nonempty_T_3 | stq_5_valid; // @[lsu.scala:209:16, :285:79] wire _stq_nonempty_T_5 = _stq_nonempty_T_4 | stq_6_valid; // @[lsu.scala:209:16, :285:79] wire _stq_nonempty_T_6 = _stq_nonempty_T_5 | stq_7_valid; // @[lsu.scala:209:16, :285:79] wire stq_nonempty = _stq_nonempty_T_6; // @[lsu.scala:285:{79,84}] wire [2:0] _T_32 = ldq_tail + 3'h1; // @[util.scala:203:14] assign io_core_ldq_full_0_0 = _T_32 == ldq_head; // @[util.scala:203:14] wire [2:0] _T_39 = stq_tail + 3'h1; // @[util.scala:203:14] assign io_core_stq_full_0_0 = _T_39 == stq_head; // @[util.scala:203:14] wire _dis_ld_val_T = io_core_dis_uops_0_valid_0 & io_core_dis_uops_0_bits_uses_ldq_0; // @[lsu.scala:201:7, :300:48] wire _dis_ld_val_T_1 = ~io_core_dis_uops_0_bits_exception_0; // @[lsu.scala:201:7, :300:88] wire dis_ld_val = _dis_ld_val_T & _dis_ld_val_T_1; // @[lsu.scala:300:{48,85,88}] wire _dis_st_val_T = io_core_dis_uops_0_valid_0 & io_core_dis_uops_0_bits_uses_stq_0; // @[lsu.scala:201:7, :301:48] wire _dis_st_val_T_1 = ~io_core_dis_uops_0_bits_exception_0; // @[lsu.scala:201:7, :300:88, :301:88] wire dis_st_val = _dis_st_val_T & _dis_st_val_T_1; // @[lsu.scala:301:{48,85,88}] wire [7:0] _GEN_92 = {{ldq_7_valid}, {ldq_6_valid}, {ldq_5_valid}, {ldq_4_valid}, {ldq_3_valid}, {ldq_2_valid}, {ldq_1_valid}, {ldq_0_valid}}; // @[lsu.scala:208:16, :304:44] wire _io_core_fencei_rdy_T = ~stq_nonempty; // @[lsu.scala:285:84, :347:28] assign _io_core_fencei_rdy_T_1 = _io_core_fencei_rdy_T & io_dmem_ordered_0; // @[lsu.scala:201:7, :347:{28,42}] assign io_core_fencei_rdy_0 = _io_core_fencei_rdy_T_1; // @[lsu.scala:201:7, :347:42] wire mem_xcpt_valid; // @[lsu.scala:358:29] wire [3:0] mem_xcpt_cause; // @[lsu.scala:359:29] wire [3:0] mem_xcpt_uop_ctrl_br_type; // @[lsu.scala:360:29] wire [1:0] mem_xcpt_uop_ctrl_op1_sel; // @[lsu.scala:360:29] wire [2:0] mem_xcpt_uop_ctrl_op2_sel; // @[lsu.scala:360:29] wire [2:0] mem_xcpt_uop_ctrl_imm_sel; // @[lsu.scala:360:29] wire [4:0] mem_xcpt_uop_ctrl_op_fcn; // @[lsu.scala:360:29] wire mem_xcpt_uop_ctrl_fcn_dw; // @[lsu.scala:360:29] wire [2:0] mem_xcpt_uop_ctrl_csr_cmd; // @[lsu.scala:360:29] wire mem_xcpt_uop_ctrl_is_load; // @[lsu.scala:360:29] wire mem_xcpt_uop_ctrl_is_sta; // @[lsu.scala:360:29] wire mem_xcpt_uop_ctrl_is_std; // @[lsu.scala:360:29] wire [6:0] mem_xcpt_uop_uopc; // @[lsu.scala:360:29] wire [31:0] mem_xcpt_uop_inst; // @[lsu.scala:360:29] wire [31:0] mem_xcpt_uop_debug_inst; // @[lsu.scala:360:29] wire mem_xcpt_uop_is_rvc; // @[lsu.scala:360:29] wire [39:0] mem_xcpt_uop_debug_pc; // @[lsu.scala:360:29] wire [2:0] mem_xcpt_uop_iq_type; // @[lsu.scala:360:29] wire [9:0] mem_xcpt_uop_fu_code; // @[lsu.scala:360:29] wire [1:0] mem_xcpt_uop_iw_state; // @[lsu.scala:360:29] wire mem_xcpt_uop_iw_p1_poisoned; // @[lsu.scala:360:29] wire mem_xcpt_uop_iw_p2_poisoned; // @[lsu.scala:360:29] wire mem_xcpt_uop_is_br; // @[lsu.scala:360:29] wire mem_xcpt_uop_is_jalr; // @[lsu.scala:360:29] wire mem_xcpt_uop_is_jal; // @[lsu.scala:360:29] wire mem_xcpt_uop_is_sfb; // @[lsu.scala:360:29] wire [7:0] mem_xcpt_uop_br_mask; // @[lsu.scala:360:29] wire [2:0] mem_xcpt_uop_br_tag; // @[lsu.scala:360:29] wire [3:0] mem_xcpt_uop_ftq_idx; // @[lsu.scala:360:29] wire mem_xcpt_uop_edge_inst; // @[lsu.scala:360:29] wire [5:0] mem_xcpt_uop_pc_lob; // @[lsu.scala:360:29] wire mem_xcpt_uop_taken; // @[lsu.scala:360:29] wire [19:0] mem_xcpt_uop_imm_packed; // @[lsu.scala:360:29] wire [11:0] mem_xcpt_uop_csr_addr; // @[lsu.scala:360:29] wire [4:0] mem_xcpt_uop_rob_idx; // @[lsu.scala:360:29] wire [2:0] mem_xcpt_uop_ldq_idx; // @[lsu.scala:360:29] wire [2:0] mem_xcpt_uop_stq_idx; // @[lsu.scala:360:29] wire [1:0] mem_xcpt_uop_rxq_idx; // @[lsu.scala:360:29] wire [5:0] mem_xcpt_uop_pdst; // @[lsu.scala:360:29] wire [5:0] mem_xcpt_uop_prs1; // @[lsu.scala:360:29] wire [5:0] mem_xcpt_uop_prs2; // @[lsu.scala:360:29] wire [5:0] mem_xcpt_uop_prs3; // @[lsu.scala:360:29] wire [3:0] mem_xcpt_uop_ppred; // @[lsu.scala:360:29] wire mem_xcpt_uop_prs1_busy; // @[lsu.scala:360:29] wire mem_xcpt_uop_prs2_busy; // @[lsu.scala:360:29] wire mem_xcpt_uop_prs3_busy; // @[lsu.scala:360:29] wire mem_xcpt_uop_ppred_busy; // @[lsu.scala:360:29] wire [5:0] mem_xcpt_uop_stale_pdst; // @[lsu.scala:360:29] wire mem_xcpt_uop_exception; // @[lsu.scala:360:29] wire [63:0] mem_xcpt_uop_exc_cause; // @[lsu.scala:360:29] wire mem_xcpt_uop_bypassable; // @[lsu.scala:360:29] wire [4:0] mem_xcpt_uop_mem_cmd; // @[lsu.scala:360:29] wire [1:0] mem_xcpt_uop_mem_size; // @[lsu.scala:360:29] wire mem_xcpt_uop_mem_signed; // @[lsu.scala:360:29] wire mem_xcpt_uop_is_fence; // @[lsu.scala:360:29] wire mem_xcpt_uop_is_fencei; // @[lsu.scala:360:29] wire mem_xcpt_uop_is_amo; // @[lsu.scala:360:29] wire mem_xcpt_uop_uses_ldq; // @[lsu.scala:360:29] wire mem_xcpt_uop_uses_stq; // @[lsu.scala:360:29] wire mem_xcpt_uop_is_sys_pc2epc; // @[lsu.scala:360:29] wire mem_xcpt_uop_is_unique; // @[lsu.scala:360:29] wire mem_xcpt_uop_flush_on_commit; // @[lsu.scala:360:29] wire mem_xcpt_uop_ldst_is_rs1; // @[lsu.scala:360:29] wire [5:0] mem_xcpt_uop_ldst; // @[lsu.scala:360:29] wire [5:0] mem_xcpt_uop_lrs1; // @[lsu.scala:360:29] wire [5:0] mem_xcpt_uop_lrs2; // @[lsu.scala:360:29] wire [5:0] mem_xcpt_uop_lrs3; // @[lsu.scala:360:29] wire mem_xcpt_uop_ldst_val; // @[lsu.scala:360:29] wire [1:0] mem_xcpt_uop_dst_rtype; // @[lsu.scala:360:29] wire [1:0] mem_xcpt_uop_lrs1_rtype; // @[lsu.scala:360:29] wire [1:0] mem_xcpt_uop_lrs2_rtype; // @[lsu.scala:360:29] wire mem_xcpt_uop_frs3_en; // @[lsu.scala:360:29] wire mem_xcpt_uop_fp_val; // @[lsu.scala:360:29] wire mem_xcpt_uop_fp_single; // @[lsu.scala:360:29] wire mem_xcpt_uop_xcpt_pf_if; // @[lsu.scala:360:29] wire mem_xcpt_uop_xcpt_ae_if; // @[lsu.scala:360:29] wire mem_xcpt_uop_xcpt_ma_if; // @[lsu.scala:360:29] wire mem_xcpt_uop_bp_debug_if; // @[lsu.scala:360:29] wire mem_xcpt_uop_bp_xcpt_if; // @[lsu.scala:360:29] wire [1:0] mem_xcpt_uop_debug_fsrc; // @[lsu.scala:360:29] wire [1:0] mem_xcpt_uop_debug_tsrc; // @[lsu.scala:360:29] wire [39:0] mem_xcpt_vaddr; // @[lsu.scala:361:29] wire will_fire_load_incoming_0_will_fire; // @[lsu.scala:535:61] wire will_fire_load_incoming_0; // @[lsu.scala:370:38] wire will_fire_stad_incoming_0_will_fire; // @[lsu.scala:535:61] wire will_fire_stad_incoming_0; // @[lsu.scala:371:38] wire will_fire_sta_incoming_0_will_fire; // @[lsu.scala:535:61] wire will_fire_sta_incoming_0; // @[lsu.scala:372:38] wire will_fire_std_incoming_0_will_fire; // @[lsu.scala:535:61] wire will_fire_std_incoming_0; // @[lsu.scala:373:38] wire will_fire_sfence_0_will_fire; // @[lsu.scala:535:61] wire will_fire_sfence_0; // @[lsu.scala:374:38] wire will_fire_hella_incoming_0_will_fire; // @[lsu.scala:535:61] wire will_fire_hella_incoming_0; // @[lsu.scala:375:38] wire _exe_passthr_T = will_fire_hella_incoming_0; // @[lsu.scala:375:38, :642:23] wire will_fire_hella_wakeup_0_will_fire; // @[lsu.scala:535:61] wire will_fire_hella_wakeup_0; // @[lsu.scala:376:38] wire will_fire_release_0_will_fire; // @[lsu.scala:535:61] assign io_dmem_release_ready_0 = will_fire_release_0; // @[lsu.scala:201:7, :377:38] wire will_fire_load_retry_0_will_fire; // @[lsu.scala:535:61] wire will_fire_load_retry_0; // @[lsu.scala:378:38] wire will_fire_sta_retry_0_will_fire; // @[lsu.scala:535:61] wire will_fire_sta_retry_0; // @[lsu.scala:379:38] wire will_fire_store_commit_0_will_fire; // @[lsu.scala:535:61] wire will_fire_store_commit_0; // @[lsu.scala:380:38] wire will_fire_load_wakeup_0_will_fire; // @[lsu.scala:535:61] wire will_fire_load_wakeup_0; // @[lsu.scala:381:38] wire [6:0] mem_incoming_uop_out_uopc = exe_req_0_bits_uop_uopc; // @[util.scala:96:23] wire [31:0] mem_incoming_uop_out_inst = exe_req_0_bits_uop_inst; // @[util.scala:96:23] wire [31:0] mem_incoming_uop_out_debug_inst = exe_req_0_bits_uop_debug_inst; // @[util.scala:96:23] wire mem_incoming_uop_out_is_rvc = exe_req_0_bits_uop_is_rvc; // @[util.scala:96:23] wire [39:0] mem_incoming_uop_out_debug_pc = exe_req_0_bits_uop_debug_pc; // @[util.scala:96:23] wire [2:0] mem_incoming_uop_out_iq_type = exe_req_0_bits_uop_iq_type; // @[util.scala:96:23] wire [9:0] mem_incoming_uop_out_fu_code = exe_req_0_bits_uop_fu_code; // @[util.scala:96:23] wire [3:0] mem_incoming_uop_out_ctrl_br_type = exe_req_0_bits_uop_ctrl_br_type; // @[util.scala:96:23] wire [1:0] mem_incoming_uop_out_ctrl_op1_sel = exe_req_0_bits_uop_ctrl_op1_sel; // @[util.scala:96:23] wire [2:0] mem_incoming_uop_out_ctrl_op2_sel = exe_req_0_bits_uop_ctrl_op2_sel; // @[util.scala:96:23] wire [2:0] mem_incoming_uop_out_ctrl_imm_sel = exe_req_0_bits_uop_ctrl_imm_sel; // @[util.scala:96:23] wire [4:0] mem_incoming_uop_out_ctrl_op_fcn = exe_req_0_bits_uop_ctrl_op_fcn; // @[util.scala:96:23] wire mem_incoming_uop_out_ctrl_fcn_dw = exe_req_0_bits_uop_ctrl_fcn_dw; // @[util.scala:96:23] wire [2:0] mem_incoming_uop_out_ctrl_csr_cmd = exe_req_0_bits_uop_ctrl_csr_cmd; // @[util.scala:96:23] wire mem_incoming_uop_out_ctrl_is_load = exe_req_0_bits_uop_ctrl_is_load; // @[util.scala:96:23] wire mem_incoming_uop_out_ctrl_is_sta = exe_req_0_bits_uop_ctrl_is_sta; // @[util.scala:96:23] wire mem_incoming_uop_out_ctrl_is_std = exe_req_0_bits_uop_ctrl_is_std; // @[util.scala:96:23] wire [1:0] mem_incoming_uop_out_iw_state = exe_req_0_bits_uop_iw_state; // @[util.scala:96:23] wire mem_incoming_uop_out_iw_p1_poisoned = exe_req_0_bits_uop_iw_p1_poisoned; // @[util.scala:96:23] wire mem_incoming_uop_out_iw_p2_poisoned = exe_req_0_bits_uop_iw_p2_poisoned; // @[util.scala:96:23] wire mem_incoming_uop_out_is_br = exe_req_0_bits_uop_is_br; // @[util.scala:96:23] wire mem_incoming_uop_out_is_jalr = exe_req_0_bits_uop_is_jalr; // @[util.scala:96:23] wire mem_incoming_uop_out_is_jal = exe_req_0_bits_uop_is_jal; // @[util.scala:96:23] wire mem_incoming_uop_out_is_sfb = exe_req_0_bits_uop_is_sfb; // @[util.scala:96:23] wire [2:0] mem_incoming_uop_out_br_tag = exe_req_0_bits_uop_br_tag; // @[util.scala:96:23] wire [3:0] mem_incoming_uop_out_ftq_idx = exe_req_0_bits_uop_ftq_idx; // @[util.scala:96:23] wire mem_incoming_uop_out_edge_inst = exe_req_0_bits_uop_edge_inst; // @[util.scala:96:23] wire [5:0] mem_incoming_uop_out_pc_lob = exe_req_0_bits_uop_pc_lob; // @[util.scala:96:23] wire mem_incoming_uop_out_taken = exe_req_0_bits_uop_taken; // @[util.scala:96:23] wire [19:0] mem_incoming_uop_out_imm_packed = exe_req_0_bits_uop_imm_packed; // @[util.scala:96:23] wire [11:0] mem_incoming_uop_out_csr_addr = exe_req_0_bits_uop_csr_addr; // @[util.scala:96:23] wire [4:0] mem_incoming_uop_out_rob_idx = exe_req_0_bits_uop_rob_idx; // @[util.scala:96:23] wire [2:0] ldq_incoming_idx_0 = exe_req_0_bits_uop_ldq_idx; // @[lsu.scala:263:49, :383:25] wire [2:0] mem_incoming_uop_out_ldq_idx = exe_req_0_bits_uop_ldq_idx; // @[util.scala:96:23] wire [2:0] stq_incoming_idx_0 = exe_req_0_bits_uop_stq_idx; // @[lsu.scala:263:49, :383:25] wire [2:0] mem_incoming_uop_out_stq_idx = exe_req_0_bits_uop_stq_idx; // @[util.scala:96:23] wire [1:0] mem_incoming_uop_out_rxq_idx = exe_req_0_bits_uop_rxq_idx; // @[util.scala:96:23] wire [5:0] mem_incoming_uop_out_pdst = exe_req_0_bits_uop_pdst; // @[util.scala:96:23] wire [5:0] mem_incoming_uop_out_prs1 = exe_req_0_bits_uop_prs1; // @[util.scala:96:23] wire [5:0] mem_incoming_uop_out_prs2 = exe_req_0_bits_uop_prs2; // @[util.scala:96:23] wire [5:0] mem_incoming_uop_out_prs3 = exe_req_0_bits_uop_prs3; // @[util.scala:96:23] wire [3:0] mem_incoming_uop_out_ppred = exe_req_0_bits_uop_ppred; // @[util.scala:96:23] wire mem_incoming_uop_out_prs1_busy = exe_req_0_bits_uop_prs1_busy; // @[util.scala:96:23] wire mem_incoming_uop_out_prs2_busy = exe_req_0_bits_uop_prs2_busy; // @[util.scala:96:23] wire mem_incoming_uop_out_prs3_busy = exe_req_0_bits_uop_prs3_busy; // @[util.scala:96:23] wire mem_incoming_uop_out_ppred_busy = exe_req_0_bits_uop_ppred_busy; // @[util.scala:96:23] wire [5:0] mem_incoming_uop_out_stale_pdst = exe_req_0_bits_uop_stale_pdst; // @[util.scala:96:23] wire mem_incoming_uop_out_exception = exe_req_0_bits_uop_exception; // @[util.scala:96:23] wire [63:0] mem_incoming_uop_out_exc_cause = exe_req_0_bits_uop_exc_cause; // @[util.scala:96:23] wire mem_incoming_uop_out_bypassable = exe_req_0_bits_uop_bypassable; // @[util.scala:96:23] wire [4:0] mem_incoming_uop_out_mem_cmd = exe_req_0_bits_uop_mem_cmd; // @[util.scala:96:23] wire [1:0] mem_incoming_uop_out_mem_size = exe_req_0_bits_uop_mem_size; // @[util.scala:96:23] wire mem_incoming_uop_out_mem_signed = exe_req_0_bits_uop_mem_signed; // @[util.scala:96:23] wire mem_incoming_uop_out_is_fence = exe_req_0_bits_uop_is_fence; // @[util.scala:96:23] wire mem_incoming_uop_out_is_fencei = exe_req_0_bits_uop_is_fencei; // @[util.scala:96:23] wire mem_incoming_uop_out_is_amo = exe_req_0_bits_uop_is_amo; // @[util.scala:96:23] wire mem_incoming_uop_out_uses_ldq = exe_req_0_bits_uop_uses_ldq; // @[util.scala:96:23] wire mem_incoming_uop_out_uses_stq = exe_req_0_bits_uop_uses_stq; // @[util.scala:96:23] wire mem_incoming_uop_out_is_sys_pc2epc = exe_req_0_bits_uop_is_sys_pc2epc; // @[util.scala:96:23] wire mem_incoming_uop_out_is_unique = exe_req_0_bits_uop_is_unique; // @[util.scala:96:23] wire mem_incoming_uop_out_flush_on_commit = exe_req_0_bits_uop_flush_on_commit; // @[util.scala:96:23] wire mem_incoming_uop_out_ldst_is_rs1 = exe_req_0_bits_uop_ldst_is_rs1; // @[util.scala:96:23] wire [5:0] mem_incoming_uop_out_ldst = exe_req_0_bits_uop_ldst; // @[util.scala:96:23] wire [5:0] mem_incoming_uop_out_lrs1 = exe_req_0_bits_uop_lrs1; // @[util.scala:96:23] wire [5:0] mem_incoming_uop_out_lrs2 = exe_req_0_bits_uop_lrs2; // @[util.scala:96:23] wire [5:0] mem_incoming_uop_out_lrs3 = exe_req_0_bits_uop_lrs3; // @[util.scala:96:23] wire mem_incoming_uop_out_ldst_val = exe_req_0_bits_uop_ldst_val; // @[util.scala:96:23] wire [1:0] mem_incoming_uop_out_dst_rtype = exe_req_0_bits_uop_dst_rtype; // @[util.scala:96:23] wire [1:0] mem_incoming_uop_out_lrs1_rtype = exe_req_0_bits_uop_lrs1_rtype; // @[util.scala:96:23] wire [1:0] mem_incoming_uop_out_lrs2_rtype = exe_req_0_bits_uop_lrs2_rtype; // @[util.scala:96:23] wire mem_incoming_uop_out_frs3_en = exe_req_0_bits_uop_frs3_en; // @[util.scala:96:23] wire mem_incoming_uop_out_fp_val = exe_req_0_bits_uop_fp_val; // @[util.scala:96:23] wire mem_incoming_uop_out_fp_single = exe_req_0_bits_uop_fp_single; // @[util.scala:96:23] wire mem_incoming_uop_out_xcpt_pf_if = exe_req_0_bits_uop_xcpt_pf_if; // @[util.scala:96:23] wire mem_incoming_uop_out_xcpt_ae_if = exe_req_0_bits_uop_xcpt_ae_if; // @[util.scala:96:23] wire mem_incoming_uop_out_xcpt_ma_if = exe_req_0_bits_uop_xcpt_ma_if; // @[util.scala:96:23] wire mem_incoming_uop_out_bp_debug_if = exe_req_0_bits_uop_bp_debug_if; // @[util.scala:96:23] wire mem_incoming_uop_out_bp_xcpt_if = exe_req_0_bits_uop_bp_xcpt_if; // @[util.scala:96:23] wire [1:0] mem_incoming_uop_out_debug_fsrc = exe_req_0_bits_uop_debug_fsrc; // @[util.scala:96:23] wire [1:0] mem_incoming_uop_out_debug_tsrc = exe_req_0_bits_uop_debug_tsrc; // @[util.scala:96:23] wire [7:0] exe_req_0_bits_uop_br_mask; // @[lsu.scala:383:25] wire exe_req_0_bits_mxcpt_valid; // @[lsu.scala:383:25] wire [24:0] exe_req_0_bits_mxcpt_bits; // @[lsu.scala:383:25] wire exe_req_0_bits_sfence_bits_rs1; // @[lsu.scala:383:25] wire exe_req_0_bits_sfence_bits_rs2; // @[lsu.scala:383:25] wire [38:0] exe_req_0_bits_sfence_bits_addr; // @[lsu.scala:383:25] wire exe_req_0_bits_sfence_bits_asid; // @[lsu.scala:383:25] wire exe_req_0_bits_sfence_valid; // @[lsu.scala:383:25] wire [63:0] exe_req_0_bits_data; // @[lsu.scala:383:25] wire [39:0] exe_req_0_bits_addr; // @[lsu.scala:383:25] wire exe_req_0_valid; // @[lsu.scala:383:25] assign exe_req_0_bits_sfence_bits_asid = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_sfence_bits_asid_0 : _exe_req_WIRE_0_bits_sfence_bits_asid; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15] assign exe_req_0_bits_sfence_bits_addr = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_sfence_bits_addr_0 : _exe_req_WIRE_0_bits_sfence_bits_addr; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15] assign exe_req_0_bits_sfence_bits_rs2 = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_sfence_bits_rs2_0 : _exe_req_WIRE_0_bits_sfence_bits_rs2; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15] assign exe_req_0_bits_sfence_bits_rs1 = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_sfence_bits_rs1_0 : _exe_req_WIRE_0_bits_sfence_bits_rs1; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15] assign exe_req_0_bits_sfence_valid = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_sfence_valid_0 : _exe_req_WIRE_0_bits_sfence_valid; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15] assign exe_req_0_bits_mxcpt_bits = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_mxcpt_bits_0 : _exe_req_WIRE_0_bits_mxcpt_bits; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15] assign exe_req_0_bits_mxcpt_valid = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_mxcpt_valid_0 : _exe_req_WIRE_0_bits_mxcpt_valid; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15] assign exe_req_0_bits_addr = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_addr_0 : _exe_req_WIRE_0_bits_addr; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15] assign exe_req_0_bits_data = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_data_0 : _exe_req_WIRE_0_bits_data; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15] assign exe_req_0_bits_uop_debug_tsrc = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_uop_debug_tsrc_0 : _exe_req_WIRE_0_bits_uop_debug_tsrc; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15] assign exe_req_0_bits_uop_debug_fsrc = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_uop_debug_fsrc_0 : _exe_req_WIRE_0_bits_uop_debug_fsrc; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15] assign exe_req_0_bits_uop_bp_xcpt_if = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_uop_bp_xcpt_if_0 : _exe_req_WIRE_0_bits_uop_bp_xcpt_if; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15] assign exe_req_0_bits_uop_bp_debug_if = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_uop_bp_debug_if_0 : _exe_req_WIRE_0_bits_uop_bp_debug_if; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15] assign exe_req_0_bits_uop_xcpt_ma_if = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_uop_xcpt_ma_if_0 : _exe_req_WIRE_0_bits_uop_xcpt_ma_if; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15] assign exe_req_0_bits_uop_xcpt_ae_if = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_uop_xcpt_ae_if_0 : _exe_req_WIRE_0_bits_uop_xcpt_ae_if; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15] assign exe_req_0_bits_uop_xcpt_pf_if = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_uop_xcpt_pf_if_0 : _exe_req_WIRE_0_bits_uop_xcpt_pf_if; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15] assign exe_req_0_bits_uop_fp_single = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_uop_fp_single_0 : _exe_req_WIRE_0_bits_uop_fp_single; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15] assign exe_req_0_bits_uop_fp_val = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_uop_fp_val_0 : _exe_req_WIRE_0_bits_uop_fp_val; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15] assign exe_req_0_bits_uop_frs3_en = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_uop_frs3_en_0 : _exe_req_WIRE_0_bits_uop_frs3_en; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15] assign exe_req_0_bits_uop_lrs2_rtype = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_uop_lrs2_rtype_0 : _exe_req_WIRE_0_bits_uop_lrs2_rtype; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15] assign exe_req_0_bits_uop_lrs1_rtype = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_uop_lrs1_rtype_0 : _exe_req_WIRE_0_bits_uop_lrs1_rtype; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15] assign exe_req_0_bits_uop_dst_rtype = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_uop_dst_rtype_0 : _exe_req_WIRE_0_bits_uop_dst_rtype; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15] assign exe_req_0_bits_uop_ldst_val = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_uop_ldst_val_0 : _exe_req_WIRE_0_bits_uop_ldst_val; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15] assign exe_req_0_bits_uop_lrs3 = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_uop_lrs3_0 : _exe_req_WIRE_0_bits_uop_lrs3; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15] assign exe_req_0_bits_uop_lrs2 = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_uop_lrs2_0 : _exe_req_WIRE_0_bits_uop_lrs2; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15] assign exe_req_0_bits_uop_lrs1 = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_uop_lrs1_0 : _exe_req_WIRE_0_bits_uop_lrs1; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15] assign exe_req_0_bits_uop_ldst = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_uop_ldst_0 : _exe_req_WIRE_0_bits_uop_ldst; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15] assign exe_req_0_bits_uop_ldst_is_rs1 = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_uop_ldst_is_rs1_0 : _exe_req_WIRE_0_bits_uop_ldst_is_rs1; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15] assign exe_req_0_bits_uop_flush_on_commit = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_uop_flush_on_commit_0 : _exe_req_WIRE_0_bits_uop_flush_on_commit; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15] assign exe_req_0_bits_uop_is_unique = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_uop_is_unique_0 : _exe_req_WIRE_0_bits_uop_is_unique; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15] assign exe_req_0_bits_uop_is_sys_pc2epc = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_uop_is_sys_pc2epc_0 : _exe_req_WIRE_0_bits_uop_is_sys_pc2epc; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15] assign exe_req_0_bits_uop_uses_stq = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_uop_uses_stq_0 : _exe_req_WIRE_0_bits_uop_uses_stq; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15] assign exe_req_0_bits_uop_uses_ldq = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_uop_uses_ldq_0 : _exe_req_WIRE_0_bits_uop_uses_ldq; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15] assign exe_req_0_bits_uop_is_amo = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_uop_is_amo_0 : _exe_req_WIRE_0_bits_uop_is_amo; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15] assign exe_req_0_bits_uop_is_fencei = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_uop_is_fencei_0 : _exe_req_WIRE_0_bits_uop_is_fencei; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15] assign exe_req_0_bits_uop_is_fence = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_uop_is_fence_0 : _exe_req_WIRE_0_bits_uop_is_fence; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15] assign exe_req_0_bits_uop_mem_signed = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_uop_mem_signed_0 : _exe_req_WIRE_0_bits_uop_mem_signed; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15] assign exe_req_0_bits_uop_mem_size = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_uop_mem_size_0 : _exe_req_WIRE_0_bits_uop_mem_size; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15] assign exe_req_0_bits_uop_mem_cmd = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_uop_mem_cmd_0 : _exe_req_WIRE_0_bits_uop_mem_cmd; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15] assign exe_req_0_bits_uop_bypassable = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_uop_bypassable_0 : _exe_req_WIRE_0_bits_uop_bypassable; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15] assign exe_req_0_bits_uop_exc_cause = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_uop_exc_cause_0 : _exe_req_WIRE_0_bits_uop_exc_cause; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15] assign exe_req_0_bits_uop_exception = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_uop_exception_0 : _exe_req_WIRE_0_bits_uop_exception; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15] assign exe_req_0_bits_uop_stale_pdst = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_uop_stale_pdst_0 : _exe_req_WIRE_0_bits_uop_stale_pdst; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15] assign exe_req_0_bits_uop_ppred_busy = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_uop_ppred_busy_0 : _exe_req_WIRE_0_bits_uop_ppred_busy; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15] assign exe_req_0_bits_uop_prs3_busy = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_uop_prs3_busy_0 : _exe_req_WIRE_0_bits_uop_prs3_busy; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15] assign exe_req_0_bits_uop_prs2_busy = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_uop_prs2_busy_0 : _exe_req_WIRE_0_bits_uop_prs2_busy; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15] assign exe_req_0_bits_uop_prs1_busy = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_uop_prs1_busy_0 : _exe_req_WIRE_0_bits_uop_prs1_busy; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15] assign exe_req_0_bits_uop_ppred = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_uop_ppred_0 : _exe_req_WIRE_0_bits_uop_ppred; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15] assign exe_req_0_bits_uop_prs3 = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_uop_prs3_0 : _exe_req_WIRE_0_bits_uop_prs3; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15] assign exe_req_0_bits_uop_prs2 = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_uop_prs2_0 : _exe_req_WIRE_0_bits_uop_prs2; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15] assign exe_req_0_bits_uop_prs1 = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_uop_prs1_0 : _exe_req_WIRE_0_bits_uop_prs1; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15] assign exe_req_0_bits_uop_pdst = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_uop_pdst_0 : _exe_req_WIRE_0_bits_uop_pdst; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15] assign exe_req_0_bits_uop_rxq_idx = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_uop_rxq_idx_0 : _exe_req_WIRE_0_bits_uop_rxq_idx; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15] assign exe_req_0_bits_uop_stq_idx = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_uop_stq_idx_0 : _exe_req_WIRE_0_bits_uop_stq_idx; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15] assign exe_req_0_bits_uop_ldq_idx = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_uop_ldq_idx_0 : _exe_req_WIRE_0_bits_uop_ldq_idx; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15] assign exe_req_0_bits_uop_rob_idx = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_uop_rob_idx_0 : _exe_req_WIRE_0_bits_uop_rob_idx; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15] assign exe_req_0_bits_uop_csr_addr = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_uop_csr_addr_0 : _exe_req_WIRE_0_bits_uop_csr_addr; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15] assign exe_req_0_bits_uop_imm_packed = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_uop_imm_packed_0 : _exe_req_WIRE_0_bits_uop_imm_packed; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15] assign exe_req_0_bits_uop_taken = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_uop_taken_0 : _exe_req_WIRE_0_bits_uop_taken; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15] assign exe_req_0_bits_uop_pc_lob = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_uop_pc_lob_0 : _exe_req_WIRE_0_bits_uop_pc_lob; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15] assign exe_req_0_bits_uop_edge_inst = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_uop_edge_inst_0 : _exe_req_WIRE_0_bits_uop_edge_inst; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15] assign exe_req_0_bits_uop_ftq_idx = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_uop_ftq_idx_0 : _exe_req_WIRE_0_bits_uop_ftq_idx; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15] assign exe_req_0_bits_uop_br_tag = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_uop_br_tag_0 : _exe_req_WIRE_0_bits_uop_br_tag; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15] assign exe_req_0_bits_uop_br_mask = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_uop_br_mask_0 : _exe_req_WIRE_0_bits_uop_br_mask; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15] assign exe_req_0_bits_uop_is_sfb = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_uop_is_sfb_0 : _exe_req_WIRE_0_bits_uop_is_sfb; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15] assign exe_req_0_bits_uop_is_jal = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_uop_is_jal_0 : _exe_req_WIRE_0_bits_uop_is_jal; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15] assign exe_req_0_bits_uop_is_jalr = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_uop_is_jalr_0 : _exe_req_WIRE_0_bits_uop_is_jalr; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15] assign exe_req_0_bits_uop_is_br = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_uop_is_br_0 : _exe_req_WIRE_0_bits_uop_is_br; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15] assign exe_req_0_bits_uop_iw_p2_poisoned = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_uop_iw_p2_poisoned_0 : _exe_req_WIRE_0_bits_uop_iw_p2_poisoned; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15] assign exe_req_0_bits_uop_iw_p1_poisoned = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_uop_iw_p1_poisoned_0 : _exe_req_WIRE_0_bits_uop_iw_p1_poisoned; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15] assign exe_req_0_bits_uop_iw_state = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_uop_iw_state_0 : _exe_req_WIRE_0_bits_uop_iw_state; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15] assign exe_req_0_bits_uop_ctrl_is_std = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_uop_ctrl_is_std_0 : _exe_req_WIRE_0_bits_uop_ctrl_is_std; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15] assign exe_req_0_bits_uop_ctrl_is_sta = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_uop_ctrl_is_sta_0 : _exe_req_WIRE_0_bits_uop_ctrl_is_sta; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15] assign exe_req_0_bits_uop_ctrl_is_load = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_uop_ctrl_is_load_0 : _exe_req_WIRE_0_bits_uop_ctrl_is_load; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15] assign exe_req_0_bits_uop_ctrl_csr_cmd = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_uop_ctrl_csr_cmd_0 : _exe_req_WIRE_0_bits_uop_ctrl_csr_cmd; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15] assign exe_req_0_bits_uop_ctrl_fcn_dw = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_uop_ctrl_fcn_dw_0 : _exe_req_WIRE_0_bits_uop_ctrl_fcn_dw; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15] assign exe_req_0_bits_uop_ctrl_op_fcn = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_uop_ctrl_op_fcn_0 : _exe_req_WIRE_0_bits_uop_ctrl_op_fcn; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15] assign exe_req_0_bits_uop_ctrl_imm_sel = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_uop_ctrl_imm_sel_0 : _exe_req_WIRE_0_bits_uop_ctrl_imm_sel; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15] assign exe_req_0_bits_uop_ctrl_op2_sel = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_uop_ctrl_op2_sel_0 : _exe_req_WIRE_0_bits_uop_ctrl_op2_sel; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15] assign exe_req_0_bits_uop_ctrl_op1_sel = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_uop_ctrl_op1_sel_0 : _exe_req_WIRE_0_bits_uop_ctrl_op1_sel; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15] assign exe_req_0_bits_uop_ctrl_br_type = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_uop_ctrl_br_type_0 : _exe_req_WIRE_0_bits_uop_ctrl_br_type; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15] assign exe_req_0_bits_uop_fu_code = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_uop_fu_code_0 : _exe_req_WIRE_0_bits_uop_fu_code; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15] assign exe_req_0_bits_uop_iq_type = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_uop_iq_type_0 : _exe_req_WIRE_0_bits_uop_iq_type; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15] assign exe_req_0_bits_uop_debug_pc = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_uop_debug_pc_0 : _exe_req_WIRE_0_bits_uop_debug_pc; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15] assign exe_req_0_bits_uop_is_rvc = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_uop_is_rvc_0 : _exe_req_WIRE_0_bits_uop_is_rvc; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15] assign exe_req_0_bits_uop_debug_inst = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_uop_debug_inst_0 : _exe_req_WIRE_0_bits_uop_debug_inst; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15] assign exe_req_0_bits_uop_inst = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_uop_inst_0 : _exe_req_WIRE_0_bits_uop_inst; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15] assign exe_req_0_bits_uop_uopc = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_uop_uopc_0 : _exe_req_WIRE_0_bits_uop_uopc; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15] assign exe_req_0_valid = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_valid_0 : _exe_req_WIRE_0_valid; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15] wire block_load_mask_0; // @[lsu.scala:396:36] wire block_load_mask_1; // @[lsu.scala:396:36] wire block_load_mask_2; // @[lsu.scala:396:36] wire block_load_mask_3; // @[lsu.scala:396:36] wire block_load_mask_4; // @[lsu.scala:396:36] wire block_load_mask_5; // @[lsu.scala:396:36] wire block_load_mask_6; // @[lsu.scala:396:36] wire block_load_mask_7; // @[lsu.scala:396:36] reg p1_block_load_mask_0; // @[lsu.scala:397:35] reg p1_block_load_mask_1; // @[lsu.scala:397:35] reg p1_block_load_mask_2; // @[lsu.scala:397:35] reg p1_block_load_mask_3; // @[lsu.scala:397:35] reg p1_block_load_mask_4; // @[lsu.scala:397:35] reg p1_block_load_mask_5; // @[lsu.scala:397:35] reg p1_block_load_mask_6; // @[lsu.scala:397:35] reg p1_block_load_mask_7; // @[lsu.scala:397:35] reg p2_block_load_mask_0; // @[lsu.scala:398:35] reg p2_block_load_mask_1; // @[lsu.scala:398:35] reg p2_block_load_mask_2; // @[lsu.scala:398:35] reg p2_block_load_mask_3; // @[lsu.scala:398:35] reg p2_block_load_mask_4; // @[lsu.scala:398:35] reg p2_block_load_mask_5; // @[lsu.scala:398:35] reg p2_block_load_mask_6; // @[lsu.scala:398:35] reg p2_block_load_mask_7; // @[lsu.scala:398:35] wire [3:0] _GEN_93 = {1'h0, dis_st_val ? _T_39 : stq_tail} + 4'h1; // @[util.scala:203:14] wire [3:0] _stq_almost_full_T; // @[util.scala:203:14] assign _stq_almost_full_T = _GEN_93; // @[util.scala:203:14] wire [3:0] _stq_almost_full_T_7; // @[util.scala:203:14] assign _stq_almost_full_T_7 = _GEN_93; // @[util.scala:203:14] wire [2:0] _stq_almost_full_T_1 = _stq_almost_full_T[2:0]; // @[util.scala:203:14] wire [2:0] _stq_almost_full_T_2 = _stq_almost_full_T_1; // @[util.scala:203:{14,20}] wire [3:0] _stq_almost_full_T_3 = {1'h0, _stq_almost_full_T_2} + 4'h1; // @[util.scala:203:{14,20}] wire [2:0] _stq_almost_full_T_4 = _stq_almost_full_T_3[2:0]; // @[util.scala:203:14] wire [2:0] _stq_almost_full_T_5 = _stq_almost_full_T_4; // @[util.scala:203:{14,20}] wire _stq_almost_full_T_6 = _stq_almost_full_T_5 == stq_head; // @[util.scala:203:20] wire [2:0] _stq_almost_full_T_8 = _stq_almost_full_T_7[2:0]; // @[util.scala:203:14] wire [2:0] _stq_almost_full_T_9 = _stq_almost_full_T_8; // @[util.scala:203:{14,20}] wire _stq_almost_full_T_10 = _stq_almost_full_T_9 == stq_head; // @[util.scala:203:20] wire _stq_almost_full_T_11 = _stq_almost_full_T_6 | _stq_almost_full_T_10; // @[lsu.scala:401:{92,105}, :402:68] reg stq_almost_full; // @[lsu.scala:401:32] wire store_needs_order; // @[lsu.scala:406:35] wire [6:0] mem_ldq_incoming_e_out_bits_uop_uopc = ldq_incoming_e_0_bits_uop_uopc; // @[util.scala:106:23] wire [31:0] mem_ldq_incoming_e_out_bits_uop_inst = ldq_incoming_e_0_bits_uop_inst; // @[util.scala:106:23] wire [31:0] mem_ldq_incoming_e_out_bits_uop_debug_inst = ldq_incoming_e_0_bits_uop_debug_inst; // @[util.scala:106:23] wire mem_ldq_incoming_e_out_bits_uop_is_rvc = ldq_incoming_e_0_bits_uop_is_rvc; // @[util.scala:106:23] wire [39:0] mem_ldq_incoming_e_out_bits_uop_debug_pc = ldq_incoming_e_0_bits_uop_debug_pc; // @[util.scala:106:23] wire [2:0] mem_ldq_incoming_e_out_bits_uop_iq_type = ldq_incoming_e_0_bits_uop_iq_type; // @[util.scala:106:23] wire [9:0] mem_ldq_incoming_e_out_bits_uop_fu_code = ldq_incoming_e_0_bits_uop_fu_code; // @[util.scala:106:23] wire [3:0] mem_ldq_incoming_e_out_bits_uop_ctrl_br_type = ldq_incoming_e_0_bits_uop_ctrl_br_type; // @[util.scala:106:23] wire [1:0] mem_ldq_incoming_e_out_bits_uop_ctrl_op1_sel = ldq_incoming_e_0_bits_uop_ctrl_op1_sel; // @[util.scala:106:23] wire [2:0] mem_ldq_incoming_e_out_bits_uop_ctrl_op2_sel = ldq_incoming_e_0_bits_uop_ctrl_op2_sel; // @[util.scala:106:23] wire [2:0] mem_ldq_incoming_e_out_bits_uop_ctrl_imm_sel = ldq_incoming_e_0_bits_uop_ctrl_imm_sel; // @[util.scala:106:23] wire [4:0] mem_ldq_incoming_e_out_bits_uop_ctrl_op_fcn = ldq_incoming_e_0_bits_uop_ctrl_op_fcn; // @[util.scala:106:23] wire mem_ldq_incoming_e_out_bits_uop_ctrl_fcn_dw = ldq_incoming_e_0_bits_uop_ctrl_fcn_dw; // @[util.scala:106:23] wire [2:0] mem_ldq_incoming_e_out_bits_uop_ctrl_csr_cmd = ldq_incoming_e_0_bits_uop_ctrl_csr_cmd; // @[util.scala:106:23] wire mem_ldq_incoming_e_out_bits_uop_ctrl_is_load = ldq_incoming_e_0_bits_uop_ctrl_is_load; // @[util.scala:106:23] wire mem_ldq_incoming_e_out_bits_uop_ctrl_is_sta = ldq_incoming_e_0_bits_uop_ctrl_is_sta; // @[util.scala:106:23] wire mem_ldq_incoming_e_out_bits_uop_ctrl_is_std = ldq_incoming_e_0_bits_uop_ctrl_is_std; // @[util.scala:106:23] wire [1:0] mem_ldq_incoming_e_out_bits_uop_iw_state = ldq_incoming_e_0_bits_uop_iw_state; // @[util.scala:106:23] wire mem_ldq_incoming_e_out_bits_uop_iw_p1_poisoned = ldq_incoming_e_0_bits_uop_iw_p1_poisoned; // @[util.scala:106:23] wire mem_ldq_incoming_e_out_bits_uop_iw_p2_poisoned = ldq_incoming_e_0_bits_uop_iw_p2_poisoned; // @[util.scala:106:23] wire mem_ldq_incoming_e_out_bits_uop_is_br = ldq_incoming_e_0_bits_uop_is_br; // @[util.scala:106:23] wire mem_ldq_incoming_e_out_bits_uop_is_jalr = ldq_incoming_e_0_bits_uop_is_jalr; // @[util.scala:106:23] wire mem_ldq_incoming_e_out_bits_uop_is_jal = ldq_incoming_e_0_bits_uop_is_jal; // @[util.scala:106:23] wire mem_ldq_incoming_e_out_bits_uop_is_sfb = ldq_incoming_e_0_bits_uop_is_sfb; // @[util.scala:106:23] wire [2:0] mem_ldq_incoming_e_out_bits_uop_br_tag = ldq_incoming_e_0_bits_uop_br_tag; // @[util.scala:106:23] wire [3:0] mem_ldq_incoming_e_out_bits_uop_ftq_idx = ldq_incoming_e_0_bits_uop_ftq_idx; // @[util.scala:106:23] wire mem_ldq_incoming_e_out_bits_uop_edge_inst = ldq_incoming_e_0_bits_uop_edge_inst; // @[util.scala:106:23] wire [5:0] mem_ldq_incoming_e_out_bits_uop_pc_lob = ldq_incoming_e_0_bits_uop_pc_lob; // @[util.scala:106:23] wire mem_ldq_incoming_e_out_bits_uop_taken = ldq_incoming_e_0_bits_uop_taken; // @[util.scala:106:23] wire [19:0] mem_ldq_incoming_e_out_bits_uop_imm_packed = ldq_incoming_e_0_bits_uop_imm_packed; // @[util.scala:106:23] wire [11:0] mem_ldq_incoming_e_out_bits_uop_csr_addr = ldq_incoming_e_0_bits_uop_csr_addr; // @[util.scala:106:23] wire [4:0] mem_ldq_incoming_e_out_bits_uop_rob_idx = ldq_incoming_e_0_bits_uop_rob_idx; // @[util.scala:106:23] wire [2:0] mem_ldq_incoming_e_out_bits_uop_ldq_idx = ldq_incoming_e_0_bits_uop_ldq_idx; // @[util.scala:106:23] wire [2:0] mem_ldq_incoming_e_out_bits_uop_stq_idx = ldq_incoming_e_0_bits_uop_stq_idx; // @[util.scala:106:23] wire [1:0] mem_ldq_incoming_e_out_bits_uop_rxq_idx = ldq_incoming_e_0_bits_uop_rxq_idx; // @[util.scala:106:23] wire [5:0] mem_ldq_incoming_e_out_bits_uop_pdst = ldq_incoming_e_0_bits_uop_pdst; // @[util.scala:106:23] wire [5:0] mem_ldq_incoming_e_out_bits_uop_prs1 = ldq_incoming_e_0_bits_uop_prs1; // @[util.scala:106:23] wire [5:0] mem_ldq_incoming_e_out_bits_uop_prs2 = ldq_incoming_e_0_bits_uop_prs2; // @[util.scala:106:23] wire [5:0] mem_ldq_incoming_e_out_bits_uop_prs3 = ldq_incoming_e_0_bits_uop_prs3; // @[util.scala:106:23] wire [3:0] mem_ldq_incoming_e_out_bits_uop_ppred = ldq_incoming_e_0_bits_uop_ppred; // @[util.scala:106:23] wire mem_ldq_incoming_e_out_bits_uop_prs1_busy = ldq_incoming_e_0_bits_uop_prs1_busy; // @[util.scala:106:23] wire mem_ldq_incoming_e_out_bits_uop_prs2_busy = ldq_incoming_e_0_bits_uop_prs2_busy; // @[util.scala:106:23] wire mem_ldq_incoming_e_out_bits_uop_prs3_busy = ldq_incoming_e_0_bits_uop_prs3_busy; // @[util.scala:106:23] wire mem_ldq_incoming_e_out_bits_uop_ppred_busy = ldq_incoming_e_0_bits_uop_ppred_busy; // @[util.scala:106:23] wire [5:0] mem_ldq_incoming_e_out_bits_uop_stale_pdst = ldq_incoming_e_0_bits_uop_stale_pdst; // @[util.scala:106:23] wire mem_ldq_incoming_e_out_bits_uop_exception = ldq_incoming_e_0_bits_uop_exception; // @[util.scala:106:23] wire [63:0] mem_ldq_incoming_e_out_bits_uop_exc_cause = ldq_incoming_e_0_bits_uop_exc_cause; // @[util.scala:106:23] wire mem_ldq_incoming_e_out_bits_uop_bypassable = ldq_incoming_e_0_bits_uop_bypassable; // @[util.scala:106:23] wire [4:0] mem_ldq_incoming_e_out_bits_uop_mem_cmd = ldq_incoming_e_0_bits_uop_mem_cmd; // @[util.scala:106:23] wire [1:0] mem_ldq_incoming_e_out_bits_uop_mem_size = ldq_incoming_e_0_bits_uop_mem_size; // @[util.scala:106:23] wire mem_ldq_incoming_e_out_bits_uop_mem_signed = ldq_incoming_e_0_bits_uop_mem_signed; // @[util.scala:106:23] wire mem_ldq_incoming_e_out_bits_uop_is_fence = ldq_incoming_e_0_bits_uop_is_fence; // @[util.scala:106:23] wire mem_ldq_incoming_e_out_bits_uop_is_fencei = ldq_incoming_e_0_bits_uop_is_fencei; // @[util.scala:106:23] wire mem_ldq_incoming_e_out_bits_uop_is_amo = ldq_incoming_e_0_bits_uop_is_amo; // @[util.scala:106:23] wire mem_ldq_incoming_e_out_bits_uop_uses_ldq = ldq_incoming_e_0_bits_uop_uses_ldq; // @[util.scala:106:23] wire mem_ldq_incoming_e_out_bits_uop_uses_stq = ldq_incoming_e_0_bits_uop_uses_stq; // @[util.scala:106:23] wire mem_ldq_incoming_e_out_bits_uop_is_sys_pc2epc = ldq_incoming_e_0_bits_uop_is_sys_pc2epc; // @[util.scala:106:23] wire mem_ldq_incoming_e_out_bits_uop_is_unique = ldq_incoming_e_0_bits_uop_is_unique; // @[util.scala:106:23] wire mem_ldq_incoming_e_out_bits_uop_flush_on_commit = ldq_incoming_e_0_bits_uop_flush_on_commit; // @[util.scala:106:23] wire mem_ldq_incoming_e_out_bits_uop_ldst_is_rs1 = ldq_incoming_e_0_bits_uop_ldst_is_rs1; // @[util.scala:106:23] wire [5:0] mem_ldq_incoming_e_out_bits_uop_ldst = ldq_incoming_e_0_bits_uop_ldst; // @[util.scala:106:23] wire [5:0] mem_ldq_incoming_e_out_bits_uop_lrs1 = ldq_incoming_e_0_bits_uop_lrs1; // @[util.scala:106:23] wire [5:0] mem_ldq_incoming_e_out_bits_uop_lrs2 = ldq_incoming_e_0_bits_uop_lrs2; // @[util.scala:106:23] wire [5:0] mem_ldq_incoming_e_out_bits_uop_lrs3 = ldq_incoming_e_0_bits_uop_lrs3; // @[util.scala:106:23] wire mem_ldq_incoming_e_out_bits_uop_ldst_val = ldq_incoming_e_0_bits_uop_ldst_val; // @[util.scala:106:23] wire [1:0] mem_ldq_incoming_e_out_bits_uop_dst_rtype = ldq_incoming_e_0_bits_uop_dst_rtype; // @[util.scala:106:23] wire [1:0] mem_ldq_incoming_e_out_bits_uop_lrs1_rtype = ldq_incoming_e_0_bits_uop_lrs1_rtype; // @[util.scala:106:23] wire [1:0] mem_ldq_incoming_e_out_bits_uop_lrs2_rtype = ldq_incoming_e_0_bits_uop_lrs2_rtype; // @[util.scala:106:23] wire mem_ldq_incoming_e_out_bits_uop_frs3_en = ldq_incoming_e_0_bits_uop_frs3_en; // @[util.scala:106:23] wire mem_ldq_incoming_e_out_bits_uop_fp_val = ldq_incoming_e_0_bits_uop_fp_val; // @[util.scala:106:23] wire mem_ldq_incoming_e_out_bits_uop_fp_single = ldq_incoming_e_0_bits_uop_fp_single; // @[util.scala:106:23] wire mem_ldq_incoming_e_out_bits_uop_xcpt_pf_if = ldq_incoming_e_0_bits_uop_xcpt_pf_if; // @[util.scala:106:23] wire mem_ldq_incoming_e_out_bits_uop_xcpt_ae_if = ldq_incoming_e_0_bits_uop_xcpt_ae_if; // @[util.scala:106:23] wire mem_ldq_incoming_e_out_bits_uop_xcpt_ma_if = ldq_incoming_e_0_bits_uop_xcpt_ma_if; // @[util.scala:106:23] wire mem_ldq_incoming_e_out_bits_uop_bp_debug_if = ldq_incoming_e_0_bits_uop_bp_debug_if; // @[util.scala:106:23] wire mem_ldq_incoming_e_out_bits_uop_bp_xcpt_if = ldq_incoming_e_0_bits_uop_bp_xcpt_if; // @[util.scala:106:23] wire [1:0] mem_ldq_incoming_e_out_bits_uop_debug_fsrc = ldq_incoming_e_0_bits_uop_debug_fsrc; // @[util.scala:106:23] wire [1:0] mem_ldq_incoming_e_out_bits_uop_debug_tsrc = ldq_incoming_e_0_bits_uop_debug_tsrc; // @[util.scala:106:23] wire mem_ldq_incoming_e_out_bits_addr_valid = ldq_incoming_e_0_bits_addr_valid; // @[util.scala:106:23] wire [39:0] mem_ldq_incoming_e_out_bits_addr_bits = ldq_incoming_e_0_bits_addr_bits; // @[util.scala:106:23] wire mem_ldq_incoming_e_out_bits_addr_is_virtual = ldq_incoming_e_0_bits_addr_is_virtual; // @[util.scala:106:23] wire mem_ldq_incoming_e_out_bits_addr_is_uncacheable = ldq_incoming_e_0_bits_addr_is_uncacheable; // @[util.scala:106:23] wire mem_ldq_incoming_e_out_bits_executed = ldq_incoming_e_0_bits_executed; // @[util.scala:106:23] wire mem_ldq_incoming_e_out_bits_succeeded = ldq_incoming_e_0_bits_succeeded; // @[util.scala:106:23] wire mem_ldq_incoming_e_out_bits_order_fail = ldq_incoming_e_0_bits_order_fail; // @[util.scala:106:23] wire mem_ldq_incoming_e_out_bits_observed = ldq_incoming_e_0_bits_observed; // @[util.scala:106:23] wire [7:0] mem_ldq_incoming_e_out_bits_st_dep_mask = ldq_incoming_e_0_bits_st_dep_mask; // @[util.scala:106:23] wire [2:0] mem_ldq_incoming_e_out_bits_youngest_stq_idx = ldq_incoming_e_0_bits_youngest_stq_idx; // @[util.scala:106:23] wire mem_ldq_incoming_e_out_bits_forward_std_val = ldq_incoming_e_0_bits_forward_std_val; // @[util.scala:106:23] wire [2:0] mem_ldq_incoming_e_out_bits_forward_stq_idx = ldq_incoming_e_0_bits_forward_stq_idx; // @[util.scala:106:23] wire [63:0] mem_ldq_incoming_e_out_bits_debug_wb_data = ldq_incoming_e_0_bits_debug_wb_data; // @[util.scala:106:23] wire [7:0] ldq_incoming_e_0_bits_uop_br_mask; // @[lsu.scala:263:49] wire ldq_incoming_e_0_valid; // @[lsu.scala:263:49] assign ldq_incoming_e_0_valid = _GEN_92[ldq_incoming_idx_0]; // @[lsu.scala:263:49, :304:44] wire [7:0][6:0] _GEN_94 = {{ldq_7_bits_uop_uopc}, {ldq_6_bits_uop_uopc}, {ldq_5_bits_uop_uopc}, {ldq_4_bits_uop_uopc}, {ldq_3_bits_uop_uopc}, {ldq_2_bits_uop_uopc}, {ldq_1_bits_uop_uopc}, {ldq_0_bits_uop_uopc}}; // @[lsu.scala:208:16, :263:49] assign ldq_incoming_e_0_bits_uop_uopc = _GEN_94[ldq_incoming_idx_0]; // @[lsu.scala:263:49] wire [7:0][31:0] _GEN_95 = {{ldq_7_bits_uop_inst}, {ldq_6_bits_uop_inst}, {ldq_5_bits_uop_inst}, {ldq_4_bits_uop_inst}, {ldq_3_bits_uop_inst}, {ldq_2_bits_uop_inst}, {ldq_1_bits_uop_inst}, {ldq_0_bits_uop_inst}}; // @[lsu.scala:208:16, :263:49] assign ldq_incoming_e_0_bits_uop_inst = _GEN_95[ldq_incoming_idx_0]; // @[lsu.scala:263:49] wire [7:0][31:0] _GEN_96 = {{ldq_7_bits_uop_debug_inst}, {ldq_6_bits_uop_debug_inst}, {ldq_5_bits_uop_debug_inst}, {ldq_4_bits_uop_debug_inst}, {ldq_3_bits_uop_debug_inst}, {ldq_2_bits_uop_debug_inst}, {ldq_1_bits_uop_debug_inst}, {ldq_0_bits_uop_debug_inst}}; // @[lsu.scala:208:16, :263:49] assign ldq_incoming_e_0_bits_uop_debug_inst = _GEN_96[ldq_incoming_idx_0]; // @[lsu.scala:263:49] wire [7:0] _GEN_97 = {{ldq_7_bits_uop_is_rvc}, {ldq_6_bits_uop_is_rvc}, {ldq_5_bits_uop_is_rvc}, {ldq_4_bits_uop_is_rvc}, {ldq_3_bits_uop_is_rvc}, {ldq_2_bits_uop_is_rvc}, {ldq_1_bits_uop_is_rvc}, {ldq_0_bits_uop_is_rvc}}; // @[lsu.scala:208:16, :263:49] assign ldq_incoming_e_0_bits_uop_is_rvc = _GEN_97[ldq_incoming_idx_0]; // @[lsu.scala:263:49] wire [7:0][39:0] _GEN_98 = {{ldq_7_bits_uop_debug_pc}, {ldq_6_bits_uop_debug_pc}, {ldq_5_bits_uop_debug_pc}, {ldq_4_bits_uop_debug_pc}, {ldq_3_bits_uop_debug_pc}, {ldq_2_bits_uop_debug_pc}, {ldq_1_bits_uop_debug_pc}, {ldq_0_bits_uop_debug_pc}}; // @[lsu.scala:208:16, :263:49] assign ldq_incoming_e_0_bits_uop_debug_pc = _GEN_98[ldq_incoming_idx_0]; // @[lsu.scala:263:49] wire [7:0][2:0] _GEN_99 = {{ldq_7_bits_uop_iq_type}, {ldq_6_bits_uop_iq_type}, {ldq_5_bits_uop_iq_type}, {ldq_4_bits_uop_iq_type}, {ldq_3_bits_uop_iq_type}, {ldq_2_bits_uop_iq_type}, {ldq_1_bits_uop_iq_type}, {ldq_0_bits_uop_iq_type}}; // @[lsu.scala:208:16, :263:49] assign ldq_incoming_e_0_bits_uop_iq_type = _GEN_99[ldq_incoming_idx_0]; // @[lsu.scala:263:49] wire [7:0][9:0] _GEN_100 = {{ldq_7_bits_uop_fu_code}, {ldq_6_bits_uop_fu_code}, {ldq_5_bits_uop_fu_code}, {ldq_4_bits_uop_fu_code}, {ldq_3_bits_uop_fu_code}, {ldq_2_bits_uop_fu_code}, {ldq_1_bits_uop_fu_code}, {ldq_0_bits_uop_fu_code}}; // @[lsu.scala:208:16, :263:49] assign ldq_incoming_e_0_bits_uop_fu_code = _GEN_100[ldq_incoming_idx_0]; // @[lsu.scala:263:49] wire [7:0][3:0] _GEN_101 = {{ldq_7_bits_uop_ctrl_br_type}, {ldq_6_bits_uop_ctrl_br_type}, {ldq_5_bits_uop_ctrl_br_type}, {ldq_4_bits_uop_ctrl_br_type}, {ldq_3_bits_uop_ctrl_br_type}, {ldq_2_bits_uop_ctrl_br_type}, {ldq_1_bits_uop_ctrl_br_type}, {ldq_0_bits_uop_ctrl_br_type}}; // @[lsu.scala:208:16, :263:49] assign ldq_incoming_e_0_bits_uop_ctrl_br_type = _GEN_101[ldq_incoming_idx_0]; // @[lsu.scala:263:49] wire [7:0][1:0] _GEN_102 = {{ldq_7_bits_uop_ctrl_op1_sel}, {ldq_6_bits_uop_ctrl_op1_sel}, {ldq_5_bits_uop_ctrl_op1_sel}, {ldq_4_bits_uop_ctrl_op1_sel}, {ldq_3_bits_uop_ctrl_op1_sel}, {ldq_2_bits_uop_ctrl_op1_sel}, {ldq_1_bits_uop_ctrl_op1_sel}, {ldq_0_bits_uop_ctrl_op1_sel}}; // @[lsu.scala:208:16, :263:49] assign ldq_incoming_e_0_bits_uop_ctrl_op1_sel = _GEN_102[ldq_incoming_idx_0]; // @[lsu.scala:263:49] wire [7:0][2:0] _GEN_103 = {{ldq_7_bits_uop_ctrl_op2_sel}, {ldq_6_bits_uop_ctrl_op2_sel}, {ldq_5_bits_uop_ctrl_op2_sel}, {ldq_4_bits_uop_ctrl_op2_sel}, {ldq_3_bits_uop_ctrl_op2_sel}, {ldq_2_bits_uop_ctrl_op2_sel}, {ldq_1_bits_uop_ctrl_op2_sel}, {ldq_0_bits_uop_ctrl_op2_sel}}; // @[lsu.scala:208:16, :263:49] assign ldq_incoming_e_0_bits_uop_ctrl_op2_sel = _GEN_103[ldq_incoming_idx_0]; // @[lsu.scala:263:49] wire [7:0][2:0] _GEN_104 = {{ldq_7_bits_uop_ctrl_imm_sel}, {ldq_6_bits_uop_ctrl_imm_sel}, {ldq_5_bits_uop_ctrl_imm_sel}, {ldq_4_bits_uop_ctrl_imm_sel}, {ldq_3_bits_uop_ctrl_imm_sel}, {ldq_2_bits_uop_ctrl_imm_sel}, {ldq_1_bits_uop_ctrl_imm_sel}, {ldq_0_bits_uop_ctrl_imm_sel}}; // @[lsu.scala:208:16, :263:49] assign ldq_incoming_e_0_bits_uop_ctrl_imm_sel = _GEN_104[ldq_incoming_idx_0]; // @[lsu.scala:263:49] wire [7:0][4:0] _GEN_105 = {{ldq_7_bits_uop_ctrl_op_fcn}, {ldq_6_bits_uop_ctrl_op_fcn}, {ldq_5_bits_uop_ctrl_op_fcn}, {ldq_4_bits_uop_ctrl_op_fcn}, {ldq_3_bits_uop_ctrl_op_fcn}, {ldq_2_bits_uop_ctrl_op_fcn}, {ldq_1_bits_uop_ctrl_op_fcn}, {ldq_0_bits_uop_ctrl_op_fcn}}; // @[lsu.scala:208:16, :263:49] assign ldq_incoming_e_0_bits_uop_ctrl_op_fcn = _GEN_105[ldq_incoming_idx_0]; // @[lsu.scala:263:49] wire [7:0] _GEN_106 = {{ldq_7_bits_uop_ctrl_fcn_dw}, {ldq_6_bits_uop_ctrl_fcn_dw}, {ldq_5_bits_uop_ctrl_fcn_dw}, {ldq_4_bits_uop_ctrl_fcn_dw}, {ldq_3_bits_uop_ctrl_fcn_dw}, {ldq_2_bits_uop_ctrl_fcn_dw}, {ldq_1_bits_uop_ctrl_fcn_dw}, {ldq_0_bits_uop_ctrl_fcn_dw}}; // @[lsu.scala:208:16, :263:49] assign ldq_incoming_e_0_bits_uop_ctrl_fcn_dw = _GEN_106[ldq_incoming_idx_0]; // @[lsu.scala:263:49] wire [7:0][2:0] _GEN_107 = {{ldq_7_bits_uop_ctrl_csr_cmd}, {ldq_6_bits_uop_ctrl_csr_cmd}, {ldq_5_bits_uop_ctrl_csr_cmd}, {ldq_4_bits_uop_ctrl_csr_cmd}, {ldq_3_bits_uop_ctrl_csr_cmd}, {ldq_2_bits_uop_ctrl_csr_cmd}, {ldq_1_bits_uop_ctrl_csr_cmd}, {ldq_0_bits_uop_ctrl_csr_cmd}}; // @[lsu.scala:208:16, :263:49] assign ldq_incoming_e_0_bits_uop_ctrl_csr_cmd = _GEN_107[ldq_incoming_idx_0]; // @[lsu.scala:263:49] wire [7:0] _GEN_108 = {{ldq_7_bits_uop_ctrl_is_load}, {ldq_6_bits_uop_ctrl_is_load}, {ldq_5_bits_uop_ctrl_is_load}, {ldq_4_bits_uop_ctrl_is_load}, {ldq_3_bits_uop_ctrl_is_load}, {ldq_2_bits_uop_ctrl_is_load}, {ldq_1_bits_uop_ctrl_is_load}, {ldq_0_bits_uop_ctrl_is_load}}; // @[lsu.scala:208:16, :263:49] assign ldq_incoming_e_0_bits_uop_ctrl_is_load = _GEN_108[ldq_incoming_idx_0]; // @[lsu.scala:263:49] wire [7:0] _GEN_109 = {{ldq_7_bits_uop_ctrl_is_sta}, {ldq_6_bits_uop_ctrl_is_sta}, {ldq_5_bits_uop_ctrl_is_sta}, {ldq_4_bits_uop_ctrl_is_sta}, {ldq_3_bits_uop_ctrl_is_sta}, {ldq_2_bits_uop_ctrl_is_sta}, {ldq_1_bits_uop_ctrl_is_sta}, {ldq_0_bits_uop_ctrl_is_sta}}; // @[lsu.scala:208:16, :263:49] assign ldq_incoming_e_0_bits_uop_ctrl_is_sta = _GEN_109[ldq_incoming_idx_0]; // @[lsu.scala:263:49] wire [7:0] _GEN_110 = {{ldq_7_bits_uop_ctrl_is_std}, {ldq_6_bits_uop_ctrl_is_std}, {ldq_5_bits_uop_ctrl_is_std}, {ldq_4_bits_uop_ctrl_is_std}, {ldq_3_bits_uop_ctrl_is_std}, {ldq_2_bits_uop_ctrl_is_std}, {ldq_1_bits_uop_ctrl_is_std}, {ldq_0_bits_uop_ctrl_is_std}}; // @[lsu.scala:208:16, :263:49] assign ldq_incoming_e_0_bits_uop_ctrl_is_std = _GEN_110[ldq_incoming_idx_0]; // @[lsu.scala:263:49] wire [7:0][1:0] _GEN_111 = {{ldq_7_bits_uop_iw_state}, {ldq_6_bits_uop_iw_state}, {ldq_5_bits_uop_iw_state}, {ldq_4_bits_uop_iw_state}, {ldq_3_bits_uop_iw_state}, {ldq_2_bits_uop_iw_state}, {ldq_1_bits_uop_iw_state}, {ldq_0_bits_uop_iw_state}}; // @[lsu.scala:208:16, :263:49] assign ldq_incoming_e_0_bits_uop_iw_state = _GEN_111[ldq_incoming_idx_0]; // @[lsu.scala:263:49] wire [7:0] _GEN_112 = {{ldq_7_bits_uop_iw_p1_poisoned}, {ldq_6_bits_uop_iw_p1_poisoned}, {ldq_5_bits_uop_iw_p1_poisoned}, {ldq_4_bits_uop_iw_p1_poisoned}, {ldq_3_bits_uop_iw_p1_poisoned}, {ldq_2_bits_uop_iw_p1_poisoned}, {ldq_1_bits_uop_iw_p1_poisoned}, {ldq_0_bits_uop_iw_p1_poisoned}}; // @[lsu.scala:208:16, :263:49] assign ldq_incoming_e_0_bits_uop_iw_p1_poisoned = _GEN_112[ldq_incoming_idx_0]; // @[lsu.scala:263:49] wire [7:0] _GEN_113 = {{ldq_7_bits_uop_iw_p2_poisoned}, {ldq_6_bits_uop_iw_p2_poisoned}, {ldq_5_bits_uop_iw_p2_poisoned}, {ldq_4_bits_uop_iw_p2_poisoned}, {ldq_3_bits_uop_iw_p2_poisoned}, {ldq_2_bits_uop_iw_p2_poisoned}, {ldq_1_bits_uop_iw_p2_poisoned}, {ldq_0_bits_uop_iw_p2_poisoned}}; // @[lsu.scala:208:16, :263:49] assign ldq_incoming_e_0_bits_uop_iw_p2_poisoned = _GEN_113[ldq_incoming_idx_0]; // @[lsu.scala:263:49] wire [7:0] _GEN_114 = {{ldq_7_bits_uop_is_br}, {ldq_6_bits_uop_is_br}, {ldq_5_bits_uop_is_br}, {ldq_4_bits_uop_is_br}, {ldq_3_bits_uop_is_br}, {ldq_2_bits_uop_is_br}, {ldq_1_bits_uop_is_br}, {ldq_0_bits_uop_is_br}}; // @[lsu.scala:208:16, :263:49] assign ldq_incoming_e_0_bits_uop_is_br = _GEN_114[ldq_incoming_idx_0]; // @[lsu.scala:263:49] wire [7:0] _GEN_115 = {{ldq_7_bits_uop_is_jalr}, {ldq_6_bits_uop_is_jalr}, {ldq_5_bits_uop_is_jalr}, {ldq_4_bits_uop_is_jalr}, {ldq_3_bits_uop_is_jalr}, {ldq_2_bits_uop_is_jalr}, {ldq_1_bits_uop_is_jalr}, {ldq_0_bits_uop_is_jalr}}; // @[lsu.scala:208:16, :263:49] assign ldq_incoming_e_0_bits_uop_is_jalr = _GEN_115[ldq_incoming_idx_0]; // @[lsu.scala:263:49] wire [7:0] _GEN_116 = {{ldq_7_bits_uop_is_jal}, {ldq_6_bits_uop_is_jal}, {ldq_5_bits_uop_is_jal}, {ldq_4_bits_uop_is_jal}, {ldq_3_bits_uop_is_jal}, {ldq_2_bits_uop_is_jal}, {ldq_1_bits_uop_is_jal}, {ldq_0_bits_uop_is_jal}}; // @[lsu.scala:208:16, :263:49] assign ldq_incoming_e_0_bits_uop_is_jal = _GEN_116[ldq_incoming_idx_0]; // @[lsu.scala:263:49] wire [7:0] _GEN_117 = {{ldq_7_bits_uop_is_sfb}, {ldq_6_bits_uop_is_sfb}, {ldq_5_bits_uop_is_sfb}, {ldq_4_bits_uop_is_sfb}, {ldq_3_bits_uop_is_sfb}, {ldq_2_bits_uop_is_sfb}, {ldq_1_bits_uop_is_sfb}, {ldq_0_bits_uop_is_sfb}}; // @[lsu.scala:208:16, :263:49] assign ldq_incoming_e_0_bits_uop_is_sfb = _GEN_117[ldq_incoming_idx_0]; // @[lsu.scala:263:49] wire [7:0][7:0] _GEN_118 = {{ldq_7_bits_uop_br_mask}, {ldq_6_bits_uop_br_mask}, {ldq_5_bits_uop_br_mask}, {ldq_4_bits_uop_br_mask}, {ldq_3_bits_uop_br_mask}, {ldq_2_bits_uop_br_mask}, {ldq_1_bits_uop_br_mask}, {ldq_0_bits_uop_br_mask}}; // @[lsu.scala:208:16, :263:49] assign ldq_incoming_e_0_bits_uop_br_mask = _GEN_118[ldq_incoming_idx_0]; // @[lsu.scala:263:49] wire [7:0][2:0] _GEN_119 = {{ldq_7_bits_uop_br_tag}, {ldq_6_bits_uop_br_tag}, {ldq_5_bits_uop_br_tag}, {ldq_4_bits_uop_br_tag}, {ldq_3_bits_uop_br_tag}, {ldq_2_bits_uop_br_tag}, {ldq_1_bits_uop_br_tag}, {ldq_0_bits_uop_br_tag}}; // @[lsu.scala:208:16, :263:49] assign ldq_incoming_e_0_bits_uop_br_tag = _GEN_119[ldq_incoming_idx_0]; // @[lsu.scala:263:49] wire [7:0][3:0] _GEN_120 = {{ldq_7_bits_uop_ftq_idx}, {ldq_6_bits_uop_ftq_idx}, {ldq_5_bits_uop_ftq_idx}, {ldq_4_bits_uop_ftq_idx}, {ldq_3_bits_uop_ftq_idx}, {ldq_2_bits_uop_ftq_idx}, {ldq_1_bits_uop_ftq_idx}, {ldq_0_bits_uop_ftq_idx}}; // @[lsu.scala:208:16, :263:49] assign ldq_incoming_e_0_bits_uop_ftq_idx = _GEN_120[ldq_incoming_idx_0]; // @[lsu.scala:263:49] wire [7:0] _GEN_121 = {{ldq_7_bits_uop_edge_inst}, {ldq_6_bits_uop_edge_inst}, {ldq_5_bits_uop_edge_inst}, {ldq_4_bits_uop_edge_inst}, {ldq_3_bits_uop_edge_inst}, {ldq_2_bits_uop_edge_inst}, {ldq_1_bits_uop_edge_inst}, {ldq_0_bits_uop_edge_inst}}; // @[lsu.scala:208:16, :263:49] assign ldq_incoming_e_0_bits_uop_edge_inst = _GEN_121[ldq_incoming_idx_0]; // @[lsu.scala:263:49] wire [7:0][5:0] _GEN_122 = {{ldq_7_bits_uop_pc_lob}, {ldq_6_bits_uop_pc_lob}, {ldq_5_bits_uop_pc_lob}, {ldq_4_bits_uop_pc_lob}, {ldq_3_bits_uop_pc_lob}, {ldq_2_bits_uop_pc_lob}, {ldq_1_bits_uop_pc_lob}, {ldq_0_bits_uop_pc_lob}}; // @[lsu.scala:208:16, :263:49] assign ldq_incoming_e_0_bits_uop_pc_lob = _GEN_122[ldq_incoming_idx_0]; // @[lsu.scala:263:49] wire [7:0] _GEN_123 = {{ldq_7_bits_uop_taken}, {ldq_6_bits_uop_taken}, {ldq_5_bits_uop_taken}, {ldq_4_bits_uop_taken}, {ldq_3_bits_uop_taken}, {ldq_2_bits_uop_taken}, {ldq_1_bits_uop_taken}, {ldq_0_bits_uop_taken}}; // @[lsu.scala:208:16, :263:49] assign ldq_incoming_e_0_bits_uop_taken = _GEN_123[ldq_incoming_idx_0]; // @[lsu.scala:263:49] wire [7:0][19:0] _GEN_124 = {{ldq_7_bits_uop_imm_packed}, {ldq_6_bits_uop_imm_packed}, {ldq_5_bits_uop_imm_packed}, {ldq_4_bits_uop_imm_packed}, {ldq_3_bits_uop_imm_packed}, {ldq_2_bits_uop_imm_packed}, {ldq_1_bits_uop_imm_packed}, {ldq_0_bits_uop_imm_packed}}; // @[lsu.scala:208:16, :263:49] assign ldq_incoming_e_0_bits_uop_imm_packed = _GEN_124[ldq_incoming_idx_0]; // @[lsu.scala:263:49] wire [7:0][11:0] _GEN_125 = {{ldq_7_bits_uop_csr_addr}, {ldq_6_bits_uop_csr_addr}, {ldq_5_bits_uop_csr_addr}, {ldq_4_bits_uop_csr_addr}, {ldq_3_bits_uop_csr_addr}, {ldq_2_bits_uop_csr_addr}, {ldq_1_bits_uop_csr_addr}, {ldq_0_bits_uop_csr_addr}}; // @[lsu.scala:208:16, :263:49] assign ldq_incoming_e_0_bits_uop_csr_addr = _GEN_125[ldq_incoming_idx_0]; // @[lsu.scala:263:49] wire [7:0][4:0] _GEN_126 = {{ldq_7_bits_uop_rob_idx}, {ldq_6_bits_uop_rob_idx}, {ldq_5_bits_uop_rob_idx}, {ldq_4_bits_uop_rob_idx}, {ldq_3_bits_uop_rob_idx}, {ldq_2_bits_uop_rob_idx}, {ldq_1_bits_uop_rob_idx}, {ldq_0_bits_uop_rob_idx}}; // @[lsu.scala:208:16, :263:49] assign ldq_incoming_e_0_bits_uop_rob_idx = _GEN_126[ldq_incoming_idx_0]; // @[lsu.scala:263:49] wire [7:0][2:0] _GEN_127 = {{ldq_7_bits_uop_ldq_idx}, {ldq_6_bits_uop_ldq_idx}, {ldq_5_bits_uop_ldq_idx}, {ldq_4_bits_uop_ldq_idx}, {ldq_3_bits_uop_ldq_idx}, {ldq_2_bits_uop_ldq_idx}, {ldq_1_bits_uop_ldq_idx}, {ldq_0_bits_uop_ldq_idx}}; // @[lsu.scala:208:16, :263:49] assign ldq_incoming_e_0_bits_uop_ldq_idx = _GEN_127[ldq_incoming_idx_0]; // @[lsu.scala:263:49] wire [7:0][2:0] _GEN_128 = {{ldq_7_bits_uop_stq_idx}, {ldq_6_bits_uop_stq_idx}, {ldq_5_bits_uop_stq_idx}, {ldq_4_bits_uop_stq_idx}, {ldq_3_bits_uop_stq_idx}, {ldq_2_bits_uop_stq_idx}, {ldq_1_bits_uop_stq_idx}, {ldq_0_bits_uop_stq_idx}}; // @[lsu.scala:208:16, :263:49] assign ldq_incoming_e_0_bits_uop_stq_idx = _GEN_128[ldq_incoming_idx_0]; // @[lsu.scala:263:49] wire [7:0][1:0] _GEN_129 = {{ldq_7_bits_uop_rxq_idx}, {ldq_6_bits_uop_rxq_idx}, {ldq_5_bits_uop_rxq_idx}, {ldq_4_bits_uop_rxq_idx}, {ldq_3_bits_uop_rxq_idx}, {ldq_2_bits_uop_rxq_idx}, {ldq_1_bits_uop_rxq_idx}, {ldq_0_bits_uop_rxq_idx}}; // @[lsu.scala:208:16, :263:49] assign ldq_incoming_e_0_bits_uop_rxq_idx = _GEN_129[ldq_incoming_idx_0]; // @[lsu.scala:263:49] wire [7:0][5:0] _GEN_130 = {{ldq_7_bits_uop_pdst}, {ldq_6_bits_uop_pdst}, {ldq_5_bits_uop_pdst}, {ldq_4_bits_uop_pdst}, {ldq_3_bits_uop_pdst}, {ldq_2_bits_uop_pdst}, {ldq_1_bits_uop_pdst}, {ldq_0_bits_uop_pdst}}; // @[lsu.scala:208:16, :263:49] assign ldq_incoming_e_0_bits_uop_pdst = _GEN_130[ldq_incoming_idx_0]; // @[lsu.scala:263:49] wire [7:0][5:0] _GEN_131 = {{ldq_7_bits_uop_prs1}, {ldq_6_bits_uop_prs1}, {ldq_5_bits_uop_prs1}, {ldq_4_bits_uop_prs1}, {ldq_3_bits_uop_prs1}, {ldq_2_bits_uop_prs1}, {ldq_1_bits_uop_prs1}, {ldq_0_bits_uop_prs1}}; // @[lsu.scala:208:16, :263:49] assign ldq_incoming_e_0_bits_uop_prs1 = _GEN_131[ldq_incoming_idx_0]; // @[lsu.scala:263:49] wire [7:0][5:0] _GEN_132 = {{ldq_7_bits_uop_prs2}, {ldq_6_bits_uop_prs2}, {ldq_5_bits_uop_prs2}, {ldq_4_bits_uop_prs2}, {ldq_3_bits_uop_prs2}, {ldq_2_bits_uop_prs2}, {ldq_1_bits_uop_prs2}, {ldq_0_bits_uop_prs2}}; // @[lsu.scala:208:16, :263:49] assign ldq_incoming_e_0_bits_uop_prs2 = _GEN_132[ldq_incoming_idx_0]; // @[lsu.scala:263:49] wire [7:0][5:0] _GEN_133 = {{ldq_7_bits_uop_prs3}, {ldq_6_bits_uop_prs3}, {ldq_5_bits_uop_prs3}, {ldq_4_bits_uop_prs3}, {ldq_3_bits_uop_prs3}, {ldq_2_bits_uop_prs3}, {ldq_1_bits_uop_prs3}, {ldq_0_bits_uop_prs3}}; // @[lsu.scala:208:16, :263:49] assign ldq_incoming_e_0_bits_uop_prs3 = _GEN_133[ldq_incoming_idx_0]; // @[lsu.scala:263:49] wire [7:0] _GEN_134 = {{ldq_7_bits_uop_prs1_busy}, {ldq_6_bits_uop_prs1_busy}, {ldq_5_bits_uop_prs1_busy}, {ldq_4_bits_uop_prs1_busy}, {ldq_3_bits_uop_prs1_busy}, {ldq_2_bits_uop_prs1_busy}, {ldq_1_bits_uop_prs1_busy}, {ldq_0_bits_uop_prs1_busy}}; // @[lsu.scala:208:16, :263:49] assign ldq_incoming_e_0_bits_uop_prs1_busy = _GEN_134[ldq_incoming_idx_0]; // @[lsu.scala:263:49] wire [7:0] _GEN_135 = {{ldq_7_bits_uop_prs2_busy}, {ldq_6_bits_uop_prs2_busy}, {ldq_5_bits_uop_prs2_busy}, {ldq_4_bits_uop_prs2_busy}, {ldq_3_bits_uop_prs2_busy}, {ldq_2_bits_uop_prs2_busy}, {ldq_1_bits_uop_prs2_busy}, {ldq_0_bits_uop_prs2_busy}}; // @[lsu.scala:208:16, :263:49] assign ldq_incoming_e_0_bits_uop_prs2_busy = _GEN_135[ldq_incoming_idx_0]; // @[lsu.scala:263:49] wire [7:0] _GEN_136 = {{ldq_7_bits_uop_prs3_busy}, {ldq_6_bits_uop_prs3_busy}, {ldq_5_bits_uop_prs3_busy}, {ldq_4_bits_uop_prs3_busy}, {ldq_3_bits_uop_prs3_busy}, {ldq_2_bits_uop_prs3_busy}, {ldq_1_bits_uop_prs3_busy}, {ldq_0_bits_uop_prs3_busy}}; // @[lsu.scala:208:16, :263:49] assign ldq_incoming_e_0_bits_uop_prs3_busy = _GEN_136[ldq_incoming_idx_0]; // @[lsu.scala:263:49] wire [7:0][5:0] _GEN_137 = {{ldq_7_bits_uop_stale_pdst}, {ldq_6_bits_uop_stale_pdst}, {ldq_5_bits_uop_stale_pdst}, {ldq_4_bits_uop_stale_pdst}, {ldq_3_bits_uop_stale_pdst}, {ldq_2_bits_uop_stale_pdst}, {ldq_1_bits_uop_stale_pdst}, {ldq_0_bits_uop_stale_pdst}}; // @[lsu.scala:208:16, :263:49] assign ldq_incoming_e_0_bits_uop_stale_pdst = _GEN_137[ldq_incoming_idx_0]; // @[lsu.scala:263:49] wire [7:0] _GEN_138 = {{ldq_7_bits_uop_exception}, {ldq_6_bits_uop_exception}, {ldq_5_bits_uop_exception}, {ldq_4_bits_uop_exception}, {ldq_3_bits_uop_exception}, {ldq_2_bits_uop_exception}, {ldq_1_bits_uop_exception}, {ldq_0_bits_uop_exception}}; // @[lsu.scala:208:16, :263:49] assign ldq_incoming_e_0_bits_uop_exception = _GEN_138[ldq_incoming_idx_0]; // @[lsu.scala:263:49] wire [7:0][63:0] _GEN_139 = {{ldq_7_bits_uop_exc_cause}, {ldq_6_bits_uop_exc_cause}, {ldq_5_bits_uop_exc_cause}, {ldq_4_bits_uop_exc_cause}, {ldq_3_bits_uop_exc_cause}, {ldq_2_bits_uop_exc_cause}, {ldq_1_bits_uop_exc_cause}, {ldq_0_bits_uop_exc_cause}}; // @[lsu.scala:208:16, :263:49] assign ldq_incoming_e_0_bits_uop_exc_cause = _GEN_139[ldq_incoming_idx_0]; // @[lsu.scala:263:49] wire [7:0] _GEN_140 = {{ldq_7_bits_uop_bypassable}, {ldq_6_bits_uop_bypassable}, {ldq_5_bits_uop_bypassable}, {ldq_4_bits_uop_bypassable}, {ldq_3_bits_uop_bypassable}, {ldq_2_bits_uop_bypassable}, {ldq_1_bits_uop_bypassable}, {ldq_0_bits_uop_bypassable}}; // @[lsu.scala:208:16, :263:49] assign ldq_incoming_e_0_bits_uop_bypassable = _GEN_140[ldq_incoming_idx_0]; // @[lsu.scala:263:49] wire [7:0][4:0] _GEN_141 = {{ldq_7_bits_uop_mem_cmd}, {ldq_6_bits_uop_mem_cmd}, {ldq_5_bits_uop_mem_cmd}, {ldq_4_bits_uop_mem_cmd}, {ldq_3_bits_uop_mem_cmd}, {ldq_2_bits_uop_mem_cmd}, {ldq_1_bits_uop_mem_cmd}, {ldq_0_bits_uop_mem_cmd}}; // @[lsu.scala:208:16, :263:49] assign ldq_incoming_e_0_bits_uop_mem_cmd = _GEN_141[ldq_incoming_idx_0]; // @[lsu.scala:263:49] wire [7:0][1:0] _GEN_142 = {{ldq_7_bits_uop_mem_size}, {ldq_6_bits_uop_mem_size}, {ldq_5_bits_uop_mem_size}, {ldq_4_bits_uop_mem_size}, {ldq_3_bits_uop_mem_size}, {ldq_2_bits_uop_mem_size}, {ldq_1_bits_uop_mem_size}, {ldq_0_bits_uop_mem_size}}; // @[lsu.scala:208:16, :263:49] assign ldq_incoming_e_0_bits_uop_mem_size = _GEN_142[ldq_incoming_idx_0]; // @[lsu.scala:263:49] wire [7:0] _GEN_143 = {{ldq_7_bits_uop_mem_signed}, {ldq_6_bits_uop_mem_signed}, {ldq_5_bits_uop_mem_signed}, {ldq_4_bits_uop_mem_signed}, {ldq_3_bits_uop_mem_signed}, {ldq_2_bits_uop_mem_signed}, {ldq_1_bits_uop_mem_signed}, {ldq_0_bits_uop_mem_signed}}; // @[lsu.scala:208:16, :263:49] assign ldq_incoming_e_0_bits_uop_mem_signed = _GEN_143[ldq_incoming_idx_0]; // @[lsu.scala:263:49] wire [7:0] _GEN_144 = {{ldq_7_bits_uop_is_fence}, {ldq_6_bits_uop_is_fence}, {ldq_5_bits_uop_is_fence}, {ldq_4_bits_uop_is_fence}, {ldq_3_bits_uop_is_fence}, {ldq_2_bits_uop_is_fence}, {ldq_1_bits_uop_is_fence}, {ldq_0_bits_uop_is_fence}}; // @[lsu.scala:208:16, :263:49] assign ldq_incoming_e_0_bits_uop_is_fence = _GEN_144[ldq_incoming_idx_0]; // @[lsu.scala:263:49] wire [7:0] _GEN_145 = {{ldq_7_bits_uop_is_fencei}, {ldq_6_bits_uop_is_fencei}, {ldq_5_bits_uop_is_fencei}, {ldq_4_bits_uop_is_fencei}, {ldq_3_bits_uop_is_fencei}, {ldq_2_bits_uop_is_fencei}, {ldq_1_bits_uop_is_fencei}, {ldq_0_bits_uop_is_fencei}}; // @[lsu.scala:208:16, :263:49] assign ldq_incoming_e_0_bits_uop_is_fencei = _GEN_145[ldq_incoming_idx_0]; // @[lsu.scala:263:49] wire [7:0] _GEN_146 = {{ldq_7_bits_uop_is_amo}, {ldq_6_bits_uop_is_amo}, {ldq_5_bits_uop_is_amo}, {ldq_4_bits_uop_is_amo}, {ldq_3_bits_uop_is_amo}, {ldq_2_bits_uop_is_amo}, {ldq_1_bits_uop_is_amo}, {ldq_0_bits_uop_is_amo}}; // @[lsu.scala:208:16, :263:49] assign ldq_incoming_e_0_bits_uop_is_amo = _GEN_146[ldq_incoming_idx_0]; // @[lsu.scala:263:49] wire [7:0] _GEN_147 = {{ldq_7_bits_uop_uses_ldq}, {ldq_6_bits_uop_uses_ldq}, {ldq_5_bits_uop_uses_ldq}, {ldq_4_bits_uop_uses_ldq}, {ldq_3_bits_uop_uses_ldq}, {ldq_2_bits_uop_uses_ldq}, {ldq_1_bits_uop_uses_ldq}, {ldq_0_bits_uop_uses_ldq}}; // @[lsu.scala:208:16, :263:49] assign ldq_incoming_e_0_bits_uop_uses_ldq = _GEN_147[ldq_incoming_idx_0]; // @[lsu.scala:263:49] wire [7:0] _GEN_148 = {{ldq_7_bits_uop_uses_stq}, {ldq_6_bits_uop_uses_stq}, {ldq_5_bits_uop_uses_stq}, {ldq_4_bits_uop_uses_stq}, {ldq_3_bits_uop_uses_stq}, {ldq_2_bits_uop_uses_stq}, {ldq_1_bits_uop_uses_stq}, {ldq_0_bits_uop_uses_stq}}; // @[lsu.scala:208:16, :263:49] assign ldq_incoming_e_0_bits_uop_uses_stq = _GEN_148[ldq_incoming_idx_0]; // @[lsu.scala:263:49] wire [7:0] _GEN_149 = {{ldq_7_bits_uop_is_sys_pc2epc}, {ldq_6_bits_uop_is_sys_pc2epc}, {ldq_5_bits_uop_is_sys_pc2epc}, {ldq_4_bits_uop_is_sys_pc2epc}, {ldq_3_bits_uop_is_sys_pc2epc}, {ldq_2_bits_uop_is_sys_pc2epc}, {ldq_1_bits_uop_is_sys_pc2epc}, {ldq_0_bits_uop_is_sys_pc2epc}}; // @[lsu.scala:208:16, :263:49] assign ldq_incoming_e_0_bits_uop_is_sys_pc2epc = _GEN_149[ldq_incoming_idx_0]; // @[lsu.scala:263:49] wire [7:0] _GEN_150 = {{ldq_7_bits_uop_is_unique}, {ldq_6_bits_uop_is_unique}, {ldq_5_bits_uop_is_unique}, {ldq_4_bits_uop_is_unique}, {ldq_3_bits_uop_is_unique}, {ldq_2_bits_uop_is_unique}, {ldq_1_bits_uop_is_unique}, {ldq_0_bits_uop_is_unique}}; // @[lsu.scala:208:16, :263:49] assign ldq_incoming_e_0_bits_uop_is_unique = _GEN_150[ldq_incoming_idx_0]; // @[lsu.scala:263:49] wire [7:0] _GEN_151 = {{ldq_7_bits_uop_flush_on_commit}, {ldq_6_bits_uop_flush_on_commit}, {ldq_5_bits_uop_flush_on_commit}, {ldq_4_bits_uop_flush_on_commit}, {ldq_3_bits_uop_flush_on_commit}, {ldq_2_bits_uop_flush_on_commit}, {ldq_1_bits_uop_flush_on_commit}, {ldq_0_bits_uop_flush_on_commit}}; // @[lsu.scala:208:16, :263:49] assign ldq_incoming_e_0_bits_uop_flush_on_commit = _GEN_151[ldq_incoming_idx_0]; // @[lsu.scala:263:49] wire [7:0] _GEN_152 = {{ldq_7_bits_uop_ldst_is_rs1}, {ldq_6_bits_uop_ldst_is_rs1}, {ldq_5_bits_uop_ldst_is_rs1}, {ldq_4_bits_uop_ldst_is_rs1}, {ldq_3_bits_uop_ldst_is_rs1}, {ldq_2_bits_uop_ldst_is_rs1}, {ldq_1_bits_uop_ldst_is_rs1}, {ldq_0_bits_uop_ldst_is_rs1}}; // @[lsu.scala:208:16, :263:49] assign ldq_incoming_e_0_bits_uop_ldst_is_rs1 = _GEN_152[ldq_incoming_idx_0]; // @[lsu.scala:263:49] wire [7:0][5:0] _GEN_153 = {{ldq_7_bits_uop_ldst}, {ldq_6_bits_uop_ldst}, {ldq_5_bits_uop_ldst}, {ldq_4_bits_uop_ldst}, {ldq_3_bits_uop_ldst}, {ldq_2_bits_uop_ldst}, {ldq_1_bits_uop_ldst}, {ldq_0_bits_uop_ldst}}; // @[lsu.scala:208:16, :263:49] assign ldq_incoming_e_0_bits_uop_ldst = _GEN_153[ldq_incoming_idx_0]; // @[lsu.scala:263:49] wire [7:0][5:0] _GEN_154 = {{ldq_7_bits_uop_lrs1}, {ldq_6_bits_uop_lrs1}, {ldq_5_bits_uop_lrs1}, {ldq_4_bits_uop_lrs1}, {ldq_3_bits_uop_lrs1}, {ldq_2_bits_uop_lrs1}, {ldq_1_bits_uop_lrs1}, {ldq_0_bits_uop_lrs1}}; // @[lsu.scala:208:16, :263:49] assign ldq_incoming_e_0_bits_uop_lrs1 = _GEN_154[ldq_incoming_idx_0]; // @[lsu.scala:263:49] wire [7:0][5:0] _GEN_155 = {{ldq_7_bits_uop_lrs2}, {ldq_6_bits_uop_lrs2}, {ldq_5_bits_uop_lrs2}, {ldq_4_bits_uop_lrs2}, {ldq_3_bits_uop_lrs2}, {ldq_2_bits_uop_lrs2}, {ldq_1_bits_uop_lrs2}, {ldq_0_bits_uop_lrs2}}; // @[lsu.scala:208:16, :263:49] assign ldq_incoming_e_0_bits_uop_lrs2 = _GEN_155[ldq_incoming_idx_0]; // @[lsu.scala:263:49] wire [7:0][5:0] _GEN_156 = {{ldq_7_bits_uop_lrs3}, {ldq_6_bits_uop_lrs3}, {ldq_5_bits_uop_lrs3}, {ldq_4_bits_uop_lrs3}, {ldq_3_bits_uop_lrs3}, {ldq_2_bits_uop_lrs3}, {ldq_1_bits_uop_lrs3}, {ldq_0_bits_uop_lrs3}}; // @[lsu.scala:208:16, :263:49] assign ldq_incoming_e_0_bits_uop_lrs3 = _GEN_156[ldq_incoming_idx_0]; // @[lsu.scala:263:49] wire [7:0] _GEN_157 = {{ldq_7_bits_uop_ldst_val}, {ldq_6_bits_uop_ldst_val}, {ldq_5_bits_uop_ldst_val}, {ldq_4_bits_uop_ldst_val}, {ldq_3_bits_uop_ldst_val}, {ldq_2_bits_uop_ldst_val}, {ldq_1_bits_uop_ldst_val}, {ldq_0_bits_uop_ldst_val}}; // @[lsu.scala:208:16, :263:49] assign ldq_incoming_e_0_bits_uop_ldst_val = _GEN_157[ldq_incoming_idx_0]; // @[lsu.scala:263:49] wire [7:0][1:0] _GEN_158 = {{ldq_7_bits_uop_dst_rtype}, {ldq_6_bits_uop_dst_rtype}, {ldq_5_bits_uop_dst_rtype}, {ldq_4_bits_uop_dst_rtype}, {ldq_3_bits_uop_dst_rtype}, {ldq_2_bits_uop_dst_rtype}, {ldq_1_bits_uop_dst_rtype}, {ldq_0_bits_uop_dst_rtype}}; // @[lsu.scala:208:16, :263:49] assign ldq_incoming_e_0_bits_uop_dst_rtype = _GEN_158[ldq_incoming_idx_0]; // @[lsu.scala:263:49] wire [7:0][1:0] _GEN_159 = {{ldq_7_bits_uop_lrs1_rtype}, {ldq_6_bits_uop_lrs1_rtype}, {ldq_5_bits_uop_lrs1_rtype}, {ldq_4_bits_uop_lrs1_rtype}, {ldq_3_bits_uop_lrs1_rtype}, {ldq_2_bits_uop_lrs1_rtype}, {ldq_1_bits_uop_lrs1_rtype}, {ldq_0_bits_uop_lrs1_rtype}}; // @[lsu.scala:208:16, :263:49] assign ldq_incoming_e_0_bits_uop_lrs1_rtype = _GEN_159[ldq_incoming_idx_0]; // @[lsu.scala:263:49] wire [7:0][1:0] _GEN_160 = {{ldq_7_bits_uop_lrs2_rtype}, {ldq_6_bits_uop_lrs2_rtype}, {ldq_5_bits_uop_lrs2_rtype}, {ldq_4_bits_uop_lrs2_rtype}, {ldq_3_bits_uop_lrs2_rtype}, {ldq_2_bits_uop_lrs2_rtype}, {ldq_1_bits_uop_lrs2_rtype}, {ldq_0_bits_uop_lrs2_rtype}}; // @[lsu.scala:208:16, :263:49] assign ldq_incoming_e_0_bits_uop_lrs2_rtype = _GEN_160[ldq_incoming_idx_0]; // @[lsu.scala:263:49] wire [7:0] _GEN_161 = {{ldq_7_bits_uop_frs3_en}, {ldq_6_bits_uop_frs3_en}, {ldq_5_bits_uop_frs3_en}, {ldq_4_bits_uop_frs3_en}, {ldq_3_bits_uop_frs3_en}, {ldq_2_bits_uop_frs3_en}, {ldq_1_bits_uop_frs3_en}, {ldq_0_bits_uop_frs3_en}}; // @[lsu.scala:208:16, :263:49] assign ldq_incoming_e_0_bits_uop_frs3_en = _GEN_161[ldq_incoming_idx_0]; // @[lsu.scala:263:49] wire [7:0] _GEN_162 = {{ldq_7_bits_uop_fp_val}, {ldq_6_bits_uop_fp_val}, {ldq_5_bits_uop_fp_val}, {ldq_4_bits_uop_fp_val}, {ldq_3_bits_uop_fp_val}, {ldq_2_bits_uop_fp_val}, {ldq_1_bits_uop_fp_val}, {ldq_0_bits_uop_fp_val}}; // @[lsu.scala:208:16, :263:49] assign ldq_incoming_e_0_bits_uop_fp_val = _GEN_162[ldq_incoming_idx_0]; // @[lsu.scala:263:49] wire [7:0] _GEN_163 = {{ldq_7_bits_uop_fp_single}, {ldq_6_bits_uop_fp_single}, {ldq_5_bits_uop_fp_single}, {ldq_4_bits_uop_fp_single}, {ldq_3_bits_uop_fp_single}, {ldq_2_bits_uop_fp_single}, {ldq_1_bits_uop_fp_single}, {ldq_0_bits_uop_fp_single}}; // @[lsu.scala:208:16, :263:49] assign ldq_incoming_e_0_bits_uop_fp_single = _GEN_163[ldq_incoming_idx_0]; // @[lsu.scala:263:49] wire [7:0] _GEN_164 = {{ldq_7_bits_uop_xcpt_pf_if}, {ldq_6_bits_uop_xcpt_pf_if}, {ldq_5_bits_uop_xcpt_pf_if}, {ldq_4_bits_uop_xcpt_pf_if}, {ldq_3_bits_uop_xcpt_pf_if}, {ldq_2_bits_uop_xcpt_pf_if}, {ldq_1_bits_uop_xcpt_pf_if}, {ldq_0_bits_uop_xcpt_pf_if}}; // @[lsu.scala:208:16, :263:49] assign ldq_incoming_e_0_bits_uop_xcpt_pf_if = _GEN_164[ldq_incoming_idx_0]; // @[lsu.scala:263:49] wire [7:0] _GEN_165 = {{ldq_7_bits_uop_xcpt_ae_if}, {ldq_6_bits_uop_xcpt_ae_if}, {ldq_5_bits_uop_xcpt_ae_if}, {ldq_4_bits_uop_xcpt_ae_if}, {ldq_3_bits_uop_xcpt_ae_if}, {ldq_2_bits_uop_xcpt_ae_if}, {ldq_1_bits_uop_xcpt_ae_if}, {ldq_0_bits_uop_xcpt_ae_if}}; // @[lsu.scala:208:16, :263:49] assign ldq_incoming_e_0_bits_uop_xcpt_ae_if = _GEN_165[ldq_incoming_idx_0]; // @[lsu.scala:263:49] wire [7:0] _GEN_166 = {{ldq_7_bits_uop_xcpt_ma_if}, {ldq_6_bits_uop_xcpt_ma_if}, {ldq_5_bits_uop_xcpt_ma_if}, {ldq_4_bits_uop_xcpt_ma_if}, {ldq_3_bits_uop_xcpt_ma_if}, {ldq_2_bits_uop_xcpt_ma_if}, {ldq_1_bits_uop_xcpt_ma_if}, {ldq_0_bits_uop_xcpt_ma_if}}; // @[lsu.scala:208:16, :263:49] assign ldq_incoming_e_0_bits_uop_xcpt_ma_if = _GEN_166[ldq_incoming_idx_0]; // @[lsu.scala:263:49] wire [7:0] _GEN_167 = {{ldq_7_bits_uop_bp_debug_if}, {ldq_6_bits_uop_bp_debug_if}, {ldq_5_bits_uop_bp_debug_if}, {ldq_4_bits_uop_bp_debug_if}, {ldq_3_bits_uop_bp_debug_if}, {ldq_2_bits_uop_bp_debug_if}, {ldq_1_bits_uop_bp_debug_if}, {ldq_0_bits_uop_bp_debug_if}}; // @[lsu.scala:208:16, :263:49] assign ldq_incoming_e_0_bits_uop_bp_debug_if = _GEN_167[ldq_incoming_idx_0]; // @[lsu.scala:263:49] wire [7:0] _GEN_168 = {{ldq_7_bits_uop_bp_xcpt_if}, {ldq_6_bits_uop_bp_xcpt_if}, {ldq_5_bits_uop_bp_xcpt_if}, {ldq_4_bits_uop_bp_xcpt_if}, {ldq_3_bits_uop_bp_xcpt_if}, {ldq_2_bits_uop_bp_xcpt_if}, {ldq_1_bits_uop_bp_xcpt_if}, {ldq_0_bits_uop_bp_xcpt_if}}; // @[lsu.scala:208:16, :263:49] assign ldq_incoming_e_0_bits_uop_bp_xcpt_if = _GEN_168[ldq_incoming_idx_0]; // @[lsu.scala:263:49] wire [7:0][1:0] _GEN_169 = {{ldq_7_bits_uop_debug_fsrc}, {ldq_6_bits_uop_debug_fsrc}, {ldq_5_bits_uop_debug_fsrc}, {ldq_4_bits_uop_debug_fsrc}, {ldq_3_bits_uop_debug_fsrc}, {ldq_2_bits_uop_debug_fsrc}, {ldq_1_bits_uop_debug_fsrc}, {ldq_0_bits_uop_debug_fsrc}}; // @[lsu.scala:208:16, :263:49] assign ldq_incoming_e_0_bits_uop_debug_fsrc = _GEN_169[ldq_incoming_idx_0]; // @[lsu.scala:263:49] wire [7:0][1:0] _GEN_170 = {{ldq_7_bits_uop_debug_tsrc}, {ldq_6_bits_uop_debug_tsrc}, {ldq_5_bits_uop_debug_tsrc}, {ldq_4_bits_uop_debug_tsrc}, {ldq_3_bits_uop_debug_tsrc}, {ldq_2_bits_uop_debug_tsrc}, {ldq_1_bits_uop_debug_tsrc}, {ldq_0_bits_uop_debug_tsrc}}; // @[lsu.scala:208:16, :263:49] assign ldq_incoming_e_0_bits_uop_debug_tsrc = _GEN_170[ldq_incoming_idx_0]; // @[lsu.scala:263:49] wire [7:0] _GEN_171 = {{ldq_7_bits_addr_valid}, {ldq_6_bits_addr_valid}, {ldq_5_bits_addr_valid}, {ldq_4_bits_addr_valid}, {ldq_3_bits_addr_valid}, {ldq_2_bits_addr_valid}, {ldq_1_bits_addr_valid}, {ldq_0_bits_addr_valid}}; // @[lsu.scala:208:16, :263:49] assign ldq_incoming_e_0_bits_addr_valid = _GEN_171[ldq_incoming_idx_0]; // @[lsu.scala:263:49] wire [7:0][39:0] _GEN_172 = {{ldq_7_bits_addr_bits}, {ldq_6_bits_addr_bits}, {ldq_5_bits_addr_bits}, {ldq_4_bits_addr_bits}, {ldq_3_bits_addr_bits}, {ldq_2_bits_addr_bits}, {ldq_1_bits_addr_bits}, {ldq_0_bits_addr_bits}}; // @[lsu.scala:208:16, :263:49] assign ldq_incoming_e_0_bits_addr_bits = _GEN_172[ldq_incoming_idx_0]; // @[lsu.scala:263:49] wire [7:0] _GEN_173 = {{ldq_7_bits_addr_is_virtual}, {ldq_6_bits_addr_is_virtual}, {ldq_5_bits_addr_is_virtual}, {ldq_4_bits_addr_is_virtual}, {ldq_3_bits_addr_is_virtual}, {ldq_2_bits_addr_is_virtual}, {ldq_1_bits_addr_is_virtual}, {ldq_0_bits_addr_is_virtual}}; // @[lsu.scala:208:16, :263:49] assign ldq_incoming_e_0_bits_addr_is_virtual = _GEN_173[ldq_incoming_idx_0]; // @[lsu.scala:263:49] wire [7:0] _GEN_174 = {{ldq_7_bits_addr_is_uncacheable}, {ldq_6_bits_addr_is_uncacheable}, {ldq_5_bits_addr_is_uncacheable}, {ldq_4_bits_addr_is_uncacheable}, {ldq_3_bits_addr_is_uncacheable}, {ldq_2_bits_addr_is_uncacheable}, {ldq_1_bits_addr_is_uncacheable}, {ldq_0_bits_addr_is_uncacheable}}; // @[lsu.scala:208:16, :263:49] assign ldq_incoming_e_0_bits_addr_is_uncacheable = _GEN_174[ldq_incoming_idx_0]; // @[lsu.scala:263:49] wire [7:0] _GEN_175 = {{ldq_7_bits_executed}, {ldq_6_bits_executed}, {ldq_5_bits_executed}, {ldq_4_bits_executed}, {ldq_3_bits_executed}, {ldq_2_bits_executed}, {ldq_1_bits_executed}, {ldq_0_bits_executed}}; // @[lsu.scala:208:16, :263:49] assign ldq_incoming_e_0_bits_executed = _GEN_175[ldq_incoming_idx_0]; // @[lsu.scala:263:49] wire [7:0] _GEN_176 = {{ldq_7_bits_succeeded}, {ldq_6_bits_succeeded}, {ldq_5_bits_succeeded}, {ldq_4_bits_succeeded}, {ldq_3_bits_succeeded}, {ldq_2_bits_succeeded}, {ldq_1_bits_succeeded}, {ldq_0_bits_succeeded}}; // @[lsu.scala:208:16, :263:49] assign ldq_incoming_e_0_bits_succeeded = _GEN_176[ldq_incoming_idx_0]; // @[lsu.scala:263:49] wire [7:0] _GEN_177 = {{ldq_7_bits_order_fail}, {ldq_6_bits_order_fail}, {ldq_5_bits_order_fail}, {ldq_4_bits_order_fail}, {ldq_3_bits_order_fail}, {ldq_2_bits_order_fail}, {ldq_1_bits_order_fail}, {ldq_0_bits_order_fail}}; // @[lsu.scala:208:16, :263:49] assign ldq_incoming_e_0_bits_order_fail = _GEN_177[ldq_incoming_idx_0]; // @[lsu.scala:263:49] wire [7:0] _GEN_178 = {{ldq_7_bits_observed}, {ldq_6_bits_observed}, {ldq_5_bits_observed}, {ldq_4_bits_observed}, {ldq_3_bits_observed}, {ldq_2_bits_observed}, {ldq_1_bits_observed}, {ldq_0_bits_observed}}; // @[lsu.scala:208:16, :263:49] assign ldq_incoming_e_0_bits_observed = _GEN_178[ldq_incoming_idx_0]; // @[lsu.scala:263:49] wire [7:0][7:0] _GEN_179 = {{ldq_7_bits_st_dep_mask}, {ldq_6_bits_st_dep_mask}, {ldq_5_bits_st_dep_mask}, {ldq_4_bits_st_dep_mask}, {ldq_3_bits_st_dep_mask}, {ldq_2_bits_st_dep_mask}, {ldq_1_bits_st_dep_mask}, {ldq_0_bits_st_dep_mask}}; // @[lsu.scala:208:16, :263:49] assign ldq_incoming_e_0_bits_st_dep_mask = _GEN_179[ldq_incoming_idx_0]; // @[lsu.scala:263:49] wire [7:0][2:0] _GEN_180 = {{ldq_7_bits_youngest_stq_idx}, {ldq_6_bits_youngest_stq_idx}, {ldq_5_bits_youngest_stq_idx}, {ldq_4_bits_youngest_stq_idx}, {ldq_3_bits_youngest_stq_idx}, {ldq_2_bits_youngest_stq_idx}, {ldq_1_bits_youngest_stq_idx}, {ldq_0_bits_youngest_stq_idx}}; // @[lsu.scala:208:16, :263:49] assign ldq_incoming_e_0_bits_youngest_stq_idx = _GEN_180[ldq_incoming_idx_0]; // @[lsu.scala:263:49] wire [7:0] _GEN_181 = {{ldq_7_bits_forward_std_val}, {ldq_6_bits_forward_std_val}, {ldq_5_bits_forward_std_val}, {ldq_4_bits_forward_std_val}, {ldq_3_bits_forward_std_val}, {ldq_2_bits_forward_std_val}, {ldq_1_bits_forward_std_val}, {ldq_0_bits_forward_std_val}}; // @[lsu.scala:208:16, :263:49] assign ldq_incoming_e_0_bits_forward_std_val = _GEN_181[ldq_incoming_idx_0]; // @[lsu.scala:263:49] wire [7:0][2:0] _GEN_182 = {{ldq_7_bits_forward_stq_idx}, {ldq_6_bits_forward_stq_idx}, {ldq_5_bits_forward_stq_idx}, {ldq_4_bits_forward_stq_idx}, {ldq_3_bits_forward_stq_idx}, {ldq_2_bits_forward_stq_idx}, {ldq_1_bits_forward_stq_idx}, {ldq_0_bits_forward_stq_idx}}; // @[lsu.scala:208:16, :263:49] assign ldq_incoming_e_0_bits_forward_stq_idx = _GEN_182[ldq_incoming_idx_0]; // @[lsu.scala:263:49] wire [7:0][63:0] _GEN_183 = {{ldq_7_bits_debug_wb_data}, {ldq_6_bits_debug_wb_data}, {ldq_5_bits_debug_wb_data}, {ldq_4_bits_debug_wb_data}, {ldq_3_bits_debug_wb_data}, {ldq_2_bits_debug_wb_data}, {ldq_1_bits_debug_wb_data}, {ldq_0_bits_debug_wb_data}}; // @[lsu.scala:208:16, :263:49] assign ldq_incoming_e_0_bits_debug_wb_data = _GEN_183[ldq_incoming_idx_0]; // @[lsu.scala:263:49] wire [6:0] mem_stq_incoming_e_out_bits_uop_uopc = stq_incoming_e_0_bits_uop_uopc; // @[util.scala:106:23] wire [31:0] mem_stq_incoming_e_out_bits_uop_inst = stq_incoming_e_0_bits_uop_inst; // @[util.scala:106:23] wire [31:0] mem_stq_incoming_e_out_bits_uop_debug_inst = stq_incoming_e_0_bits_uop_debug_inst; // @[util.scala:106:23] wire mem_stq_incoming_e_out_bits_uop_is_rvc = stq_incoming_e_0_bits_uop_is_rvc; // @[util.scala:106:23] wire [39:0] mem_stq_incoming_e_out_bits_uop_debug_pc = stq_incoming_e_0_bits_uop_debug_pc; // @[util.scala:106:23] wire [2:0] mem_stq_incoming_e_out_bits_uop_iq_type = stq_incoming_e_0_bits_uop_iq_type; // @[util.scala:106:23] wire [9:0] mem_stq_incoming_e_out_bits_uop_fu_code = stq_incoming_e_0_bits_uop_fu_code; // @[util.scala:106:23] wire [3:0] mem_stq_incoming_e_out_bits_uop_ctrl_br_type = stq_incoming_e_0_bits_uop_ctrl_br_type; // @[util.scala:106:23] wire [1:0] mem_stq_incoming_e_out_bits_uop_ctrl_op1_sel = stq_incoming_e_0_bits_uop_ctrl_op1_sel; // @[util.scala:106:23] wire [2:0] mem_stq_incoming_e_out_bits_uop_ctrl_op2_sel = stq_incoming_e_0_bits_uop_ctrl_op2_sel; // @[util.scala:106:23] wire [2:0] mem_stq_incoming_e_out_bits_uop_ctrl_imm_sel = stq_incoming_e_0_bits_uop_ctrl_imm_sel; // @[util.scala:106:23] wire [4:0] mem_stq_incoming_e_out_bits_uop_ctrl_op_fcn = stq_incoming_e_0_bits_uop_ctrl_op_fcn; // @[util.scala:106:23] wire mem_stq_incoming_e_out_bits_uop_ctrl_fcn_dw = stq_incoming_e_0_bits_uop_ctrl_fcn_dw; // @[util.scala:106:23] wire [2:0] mem_stq_incoming_e_out_bits_uop_ctrl_csr_cmd = stq_incoming_e_0_bits_uop_ctrl_csr_cmd; // @[util.scala:106:23] wire mem_stq_incoming_e_out_bits_uop_ctrl_is_load = stq_incoming_e_0_bits_uop_ctrl_is_load; // @[util.scala:106:23] wire mem_stq_incoming_e_out_bits_uop_ctrl_is_sta = stq_incoming_e_0_bits_uop_ctrl_is_sta; // @[util.scala:106:23] wire mem_stq_incoming_e_out_bits_uop_ctrl_is_std = stq_incoming_e_0_bits_uop_ctrl_is_std; // @[util.scala:106:23] wire [1:0] mem_stq_incoming_e_out_bits_uop_iw_state = stq_incoming_e_0_bits_uop_iw_state; // @[util.scala:106:23] wire mem_stq_incoming_e_out_bits_uop_iw_p1_poisoned = stq_incoming_e_0_bits_uop_iw_p1_poisoned; // @[util.scala:106:23] wire mem_stq_incoming_e_out_bits_uop_iw_p2_poisoned = stq_incoming_e_0_bits_uop_iw_p2_poisoned; // @[util.scala:106:23] wire mem_stq_incoming_e_out_bits_uop_is_br = stq_incoming_e_0_bits_uop_is_br; // @[util.scala:106:23] wire mem_stq_incoming_e_out_bits_uop_is_jalr = stq_incoming_e_0_bits_uop_is_jalr; // @[util.scala:106:23] wire mem_stq_incoming_e_out_bits_uop_is_jal = stq_incoming_e_0_bits_uop_is_jal; // @[util.scala:106:23] wire mem_stq_incoming_e_out_bits_uop_is_sfb = stq_incoming_e_0_bits_uop_is_sfb; // @[util.scala:106:23] wire [2:0] mem_stq_incoming_e_out_bits_uop_br_tag = stq_incoming_e_0_bits_uop_br_tag; // @[util.scala:106:23] wire [3:0] mem_stq_incoming_e_out_bits_uop_ftq_idx = stq_incoming_e_0_bits_uop_ftq_idx; // @[util.scala:106:23] wire mem_stq_incoming_e_out_bits_uop_edge_inst = stq_incoming_e_0_bits_uop_edge_inst; // @[util.scala:106:23] wire [5:0] mem_stq_incoming_e_out_bits_uop_pc_lob = stq_incoming_e_0_bits_uop_pc_lob; // @[util.scala:106:23] wire mem_stq_incoming_e_out_bits_uop_taken = stq_incoming_e_0_bits_uop_taken; // @[util.scala:106:23] wire [19:0] mem_stq_incoming_e_out_bits_uop_imm_packed = stq_incoming_e_0_bits_uop_imm_packed; // @[util.scala:106:23] wire [11:0] mem_stq_incoming_e_out_bits_uop_csr_addr = stq_incoming_e_0_bits_uop_csr_addr; // @[util.scala:106:23] wire [4:0] mem_stq_incoming_e_out_bits_uop_rob_idx = stq_incoming_e_0_bits_uop_rob_idx; // @[util.scala:106:23] wire [2:0] mem_stq_incoming_e_out_bits_uop_ldq_idx = stq_incoming_e_0_bits_uop_ldq_idx; // @[util.scala:106:23] wire [2:0] mem_stq_incoming_e_out_bits_uop_stq_idx = stq_incoming_e_0_bits_uop_stq_idx; // @[util.scala:106:23] wire [1:0] mem_stq_incoming_e_out_bits_uop_rxq_idx = stq_incoming_e_0_bits_uop_rxq_idx; // @[util.scala:106:23] wire [5:0] mem_stq_incoming_e_out_bits_uop_pdst = stq_incoming_e_0_bits_uop_pdst; // @[util.scala:106:23] wire [5:0] mem_stq_incoming_e_out_bits_uop_prs1 = stq_incoming_e_0_bits_uop_prs1; // @[util.scala:106:23] wire [5:0] mem_stq_incoming_e_out_bits_uop_prs2 = stq_incoming_e_0_bits_uop_prs2; // @[util.scala:106:23] wire [5:0] mem_stq_incoming_e_out_bits_uop_prs3 = stq_incoming_e_0_bits_uop_prs3; // @[util.scala:106:23] wire [3:0] mem_stq_incoming_e_out_bits_uop_ppred = stq_incoming_e_0_bits_uop_ppred; // @[util.scala:106:23] wire mem_stq_incoming_e_out_bits_uop_prs1_busy = stq_incoming_e_0_bits_uop_prs1_busy; // @[util.scala:106:23] wire mem_stq_incoming_e_out_bits_uop_prs2_busy = stq_incoming_e_0_bits_uop_prs2_busy; // @[util.scala:106:23] wire mem_stq_incoming_e_out_bits_uop_prs3_busy = stq_incoming_e_0_bits_uop_prs3_busy; // @[util.scala:106:23] wire mem_stq_incoming_e_out_bits_uop_ppred_busy = stq_incoming_e_0_bits_uop_ppred_busy; // @[util.scala:106:23] wire [5:0] mem_stq_incoming_e_out_bits_uop_stale_pdst = stq_incoming_e_0_bits_uop_stale_pdst; // @[util.scala:106:23] wire mem_stq_incoming_e_out_bits_uop_exception = stq_incoming_e_0_bits_uop_exception; // @[util.scala:106:23] wire [63:0] mem_stq_incoming_e_out_bits_uop_exc_cause = stq_incoming_e_0_bits_uop_exc_cause; // @[util.scala:106:23] wire mem_stq_incoming_e_out_bits_uop_bypassable = stq_incoming_e_0_bits_uop_bypassable; // @[util.scala:106:23] wire [4:0] mem_stq_incoming_e_out_bits_uop_mem_cmd = stq_incoming_e_0_bits_uop_mem_cmd; // @[util.scala:106:23] wire [1:0] mem_stq_incoming_e_out_bits_uop_mem_size = stq_incoming_e_0_bits_uop_mem_size; // @[util.scala:106:23] wire mem_stq_incoming_e_out_bits_uop_mem_signed = stq_incoming_e_0_bits_uop_mem_signed; // @[util.scala:106:23] wire mem_stq_incoming_e_out_bits_uop_is_fence = stq_incoming_e_0_bits_uop_is_fence; // @[util.scala:106:23] wire mem_stq_incoming_e_out_bits_uop_is_fencei = stq_incoming_e_0_bits_uop_is_fencei; // @[util.scala:106:23] wire mem_stq_incoming_e_out_bits_uop_is_amo = stq_incoming_e_0_bits_uop_is_amo; // @[util.scala:106:23] wire mem_stq_incoming_e_out_bits_uop_uses_ldq = stq_incoming_e_0_bits_uop_uses_ldq; // @[util.scala:106:23] wire mem_stq_incoming_e_out_bits_uop_uses_stq = stq_incoming_e_0_bits_uop_uses_stq; // @[util.scala:106:23] wire mem_stq_incoming_e_out_bits_uop_is_sys_pc2epc = stq_incoming_e_0_bits_uop_is_sys_pc2epc; // @[util.scala:106:23] wire mem_stq_incoming_e_out_bits_uop_is_unique = stq_incoming_e_0_bits_uop_is_unique; // @[util.scala:106:23] wire mem_stq_incoming_e_out_bits_uop_flush_on_commit = stq_incoming_e_0_bits_uop_flush_on_commit; // @[util.scala:106:23] wire mem_stq_incoming_e_out_bits_uop_ldst_is_rs1 = stq_incoming_e_0_bits_uop_ldst_is_rs1; // @[util.scala:106:23] wire [5:0] mem_stq_incoming_e_out_bits_uop_ldst = stq_incoming_e_0_bits_uop_ldst; // @[util.scala:106:23] wire [5:0] mem_stq_incoming_e_out_bits_uop_lrs1 = stq_incoming_e_0_bits_uop_lrs1; // @[util.scala:106:23] wire [5:0] mem_stq_incoming_e_out_bits_uop_lrs2 = stq_incoming_e_0_bits_uop_lrs2; // @[util.scala:106:23] wire [5:0] mem_stq_incoming_e_out_bits_uop_lrs3 = stq_incoming_e_0_bits_uop_lrs3; // @[util.scala:106:23] wire mem_stq_incoming_e_out_bits_uop_ldst_val = stq_incoming_e_0_bits_uop_ldst_val; // @[util.scala:106:23] wire [1:0] mem_stq_incoming_e_out_bits_uop_dst_rtype = stq_incoming_e_0_bits_uop_dst_rtype; // @[util.scala:106:23] wire [1:0] mem_stq_incoming_e_out_bits_uop_lrs1_rtype = stq_incoming_e_0_bits_uop_lrs1_rtype; // @[util.scala:106:23] wire [1:0] mem_stq_incoming_e_out_bits_uop_lrs2_rtype = stq_incoming_e_0_bits_uop_lrs2_rtype; // @[util.scala:106:23] wire mem_stq_incoming_e_out_bits_uop_frs3_en = stq_incoming_e_0_bits_uop_frs3_en; // @[util.scala:106:23] wire mem_stq_incoming_e_out_bits_uop_fp_val = stq_incoming_e_0_bits_uop_fp_val; // @[util.scala:106:23] wire mem_stq_incoming_e_out_bits_uop_fp_single = stq_incoming_e_0_bits_uop_fp_single; // @[util.scala:106:23] wire mem_stq_incoming_e_out_bits_uop_xcpt_pf_if = stq_incoming_e_0_bits_uop_xcpt_pf_if; // @[util.scala:106:23] wire mem_stq_incoming_e_out_bits_uop_xcpt_ae_if = stq_incoming_e_0_bits_uop_xcpt_ae_if; // @[util.scala:106:23] wire mem_stq_incoming_e_out_bits_uop_xcpt_ma_if = stq_incoming_e_0_bits_uop_xcpt_ma_if; // @[util.scala:106:23] wire mem_stq_incoming_e_out_bits_uop_bp_debug_if = stq_incoming_e_0_bits_uop_bp_debug_if; // @[util.scala:106:23] wire mem_stq_incoming_e_out_bits_uop_bp_xcpt_if = stq_incoming_e_0_bits_uop_bp_xcpt_if; // @[util.scala:106:23] wire [1:0] mem_stq_incoming_e_out_bits_uop_debug_fsrc = stq_incoming_e_0_bits_uop_debug_fsrc; // @[util.scala:106:23] wire [1:0] mem_stq_incoming_e_out_bits_uop_debug_tsrc = stq_incoming_e_0_bits_uop_debug_tsrc; // @[util.scala:106:23] wire mem_stq_incoming_e_out_bits_addr_valid = stq_incoming_e_0_bits_addr_valid; // @[util.scala:106:23] wire [39:0] mem_stq_incoming_e_out_bits_addr_bits = stq_incoming_e_0_bits_addr_bits; // @[util.scala:106:23] wire mem_stq_incoming_e_out_bits_addr_is_virtual = stq_incoming_e_0_bits_addr_is_virtual; // @[util.scala:106:23] wire mem_stq_incoming_e_out_bits_data_valid = stq_incoming_e_0_bits_data_valid; // @[util.scala:106:23] wire [63:0] mem_stq_incoming_e_out_bits_data_bits = stq_incoming_e_0_bits_data_bits; // @[util.scala:106:23] wire mem_stq_incoming_e_out_bits_committed = stq_incoming_e_0_bits_committed; // @[util.scala:106:23] wire mem_stq_incoming_e_out_bits_succeeded = stq_incoming_e_0_bits_succeeded; // @[util.scala:106:23] wire [63:0] mem_stq_incoming_e_out_bits_debug_wb_data = stq_incoming_e_0_bits_debug_wb_data; // @[util.scala:106:23] wire [7:0] stq_incoming_e_0_bits_uop_br_mask; // @[lsu.scala:263:49] wire stq_incoming_e_0_valid; // @[lsu.scala:263:49] assign stq_incoming_e_0_valid = _GEN[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49] assign stq_incoming_e_0_bits_uop_uopc = _GEN_1[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49] assign stq_incoming_e_0_bits_uop_inst = _GEN_2[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49] assign stq_incoming_e_0_bits_uop_debug_inst = _GEN_3[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49] assign stq_incoming_e_0_bits_uop_is_rvc = _GEN_4[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49] assign stq_incoming_e_0_bits_uop_debug_pc = _GEN_5[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49] assign stq_incoming_e_0_bits_uop_iq_type = _GEN_6[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49] assign stq_incoming_e_0_bits_uop_fu_code = _GEN_7[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49] assign stq_incoming_e_0_bits_uop_ctrl_br_type = _GEN_8[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49] assign stq_incoming_e_0_bits_uop_ctrl_op1_sel = _GEN_9[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49] assign stq_incoming_e_0_bits_uop_ctrl_op2_sel = _GEN_10[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49] assign stq_incoming_e_0_bits_uop_ctrl_imm_sel = _GEN_11[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49] assign stq_incoming_e_0_bits_uop_ctrl_op_fcn = _GEN_12[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49] assign stq_incoming_e_0_bits_uop_ctrl_fcn_dw = _GEN_13[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49] assign stq_incoming_e_0_bits_uop_ctrl_csr_cmd = _GEN_14[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49] assign stq_incoming_e_0_bits_uop_ctrl_is_load = _GEN_15[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49] assign stq_incoming_e_0_bits_uop_ctrl_is_sta = _GEN_16[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49] assign stq_incoming_e_0_bits_uop_ctrl_is_std = _GEN_17[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49] assign stq_incoming_e_0_bits_uop_iw_state = _GEN_18[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49] assign stq_incoming_e_0_bits_uop_iw_p1_poisoned = _GEN_19[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49] assign stq_incoming_e_0_bits_uop_iw_p2_poisoned = _GEN_20[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49] assign stq_incoming_e_0_bits_uop_is_br = _GEN_21[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49] assign stq_incoming_e_0_bits_uop_is_jalr = _GEN_22[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49] assign stq_incoming_e_0_bits_uop_is_jal = _GEN_23[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49] assign stq_incoming_e_0_bits_uop_is_sfb = _GEN_24[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49] assign stq_incoming_e_0_bits_uop_br_mask = _GEN_25[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49] assign stq_incoming_e_0_bits_uop_br_tag = _GEN_26[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49] assign stq_incoming_e_0_bits_uop_ftq_idx = _GEN_27[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49] assign stq_incoming_e_0_bits_uop_edge_inst = _GEN_28[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49] assign stq_incoming_e_0_bits_uop_pc_lob = _GEN_29[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49] assign stq_incoming_e_0_bits_uop_taken = _GEN_30[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49] assign stq_incoming_e_0_bits_uop_imm_packed = _GEN_31[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49] assign stq_incoming_e_0_bits_uop_csr_addr = _GEN_32[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49] assign stq_incoming_e_0_bits_uop_rob_idx = _GEN_33[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49] assign stq_incoming_e_0_bits_uop_ldq_idx = _GEN_34[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49] assign stq_incoming_e_0_bits_uop_stq_idx = _GEN_35[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49] assign stq_incoming_e_0_bits_uop_rxq_idx = _GEN_36[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49] assign stq_incoming_e_0_bits_uop_pdst = _GEN_37[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49] assign stq_incoming_e_0_bits_uop_prs1 = _GEN_38[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49] assign stq_incoming_e_0_bits_uop_prs2 = _GEN_39[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49] assign stq_incoming_e_0_bits_uop_prs3 = _GEN_40[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49] assign stq_incoming_e_0_bits_uop_ppred = _GEN_41[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49] assign stq_incoming_e_0_bits_uop_prs1_busy = _GEN_42[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49] assign stq_incoming_e_0_bits_uop_prs2_busy = _GEN_43[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49] assign stq_incoming_e_0_bits_uop_prs3_busy = _GEN_44[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49] assign stq_incoming_e_0_bits_uop_ppred_busy = _GEN_45[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49] assign stq_incoming_e_0_bits_uop_stale_pdst = _GEN_46[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49] assign stq_incoming_e_0_bits_uop_exception = _GEN_47[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49] assign stq_incoming_e_0_bits_uop_exc_cause = _GEN_49[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49] assign stq_incoming_e_0_bits_uop_bypassable = _GEN_50[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49] assign stq_incoming_e_0_bits_uop_mem_cmd = _GEN_51[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49] assign stq_incoming_e_0_bits_uop_mem_size = _GEN_52[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49] assign stq_incoming_e_0_bits_uop_mem_signed = _GEN_53[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49] assign stq_incoming_e_0_bits_uop_is_fence = _GEN_54[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49] assign stq_incoming_e_0_bits_uop_is_fencei = _GEN_56[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49] assign stq_incoming_e_0_bits_uop_is_amo = _GEN_57[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49] assign stq_incoming_e_0_bits_uop_uses_ldq = _GEN_59[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49] assign stq_incoming_e_0_bits_uop_uses_stq = _GEN_60[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49] assign stq_incoming_e_0_bits_uop_is_sys_pc2epc = _GEN_61[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49] assign stq_incoming_e_0_bits_uop_is_unique = _GEN_62[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49] assign stq_incoming_e_0_bits_uop_flush_on_commit = _GEN_63[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49] assign stq_incoming_e_0_bits_uop_ldst_is_rs1 = _GEN_64[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49] assign stq_incoming_e_0_bits_uop_ldst = _GEN_65[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49] assign stq_incoming_e_0_bits_uop_lrs1 = _GEN_66[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49] assign stq_incoming_e_0_bits_uop_lrs2 = _GEN_67[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49] assign stq_incoming_e_0_bits_uop_lrs3 = _GEN_68[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49] assign stq_incoming_e_0_bits_uop_ldst_val = _GEN_69[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49] assign stq_incoming_e_0_bits_uop_dst_rtype = _GEN_70[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49] assign stq_incoming_e_0_bits_uop_lrs1_rtype = _GEN_71[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49] assign stq_incoming_e_0_bits_uop_lrs2_rtype = _GEN_72[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49] assign stq_incoming_e_0_bits_uop_frs3_en = _GEN_73[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49] assign stq_incoming_e_0_bits_uop_fp_val = _GEN_74[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49] assign stq_incoming_e_0_bits_uop_fp_single = _GEN_75[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49] assign stq_incoming_e_0_bits_uop_xcpt_pf_if = _GEN_76[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49] assign stq_incoming_e_0_bits_uop_xcpt_ae_if = _GEN_77[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49] assign stq_incoming_e_0_bits_uop_xcpt_ma_if = _GEN_78[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49] assign stq_incoming_e_0_bits_uop_bp_debug_if = _GEN_79[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49] assign stq_incoming_e_0_bits_uop_bp_xcpt_if = _GEN_80[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49] assign stq_incoming_e_0_bits_uop_debug_fsrc = _GEN_81[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49] assign stq_incoming_e_0_bits_uop_debug_tsrc = _GEN_82[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49] assign stq_incoming_e_0_bits_addr_valid = _GEN_83[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49] assign stq_incoming_e_0_bits_addr_bits = _GEN_84[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49] assign stq_incoming_e_0_bits_addr_is_virtual = _GEN_85[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49] assign stq_incoming_e_0_bits_data_valid = _GEN_86[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49] assign stq_incoming_e_0_bits_data_bits = _GEN_87[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49] assign stq_incoming_e_0_bits_committed = _GEN_89[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49] wire [7:0] _GEN_184 = {{stq_7_bits_succeeded}, {stq_6_bits_succeeded}, {stq_5_bits_succeeded}, {stq_4_bits_succeeded}, {stq_3_bits_succeeded}, {stq_2_bits_succeeded}, {stq_1_bits_succeeded}, {stq_0_bits_succeeded}}; // @[lsu.scala:209:16, :263:49] assign stq_incoming_e_0_bits_succeeded = _GEN_184[stq_incoming_idx_0]; // @[lsu.scala:263:49] wire [7:0][63:0] _GEN_185 = {{stq_7_bits_debug_wb_data}, {stq_6_bits_debug_wb_data}, {stq_5_bits_debug_wb_data}, {stq_4_bits_debug_wb_data}, {stq_3_bits_debug_wb_data}, {stq_2_bits_debug_wb_data}, {stq_1_bits_debug_wb_data}, {stq_0_bits_debug_wb_data}}; // @[lsu.scala:209:16, :263:49] assign stq_incoming_e_0_bits_debug_wb_data = _GEN_185[stq_incoming_idx_0]; // @[lsu.scala:263:49] wire _GEN_186 = block_load_mask_0 | p1_block_load_mask_0; // @[lsu.scala:396:36, :397:35, :416:36] wire ldq_retry_idx_block; // @[lsu.scala:416:36] assign ldq_retry_idx_block = _GEN_186; // @[lsu.scala:416:36] wire ldq_wakeup_idx_block; // @[lsu.scala:431:36] assign ldq_wakeup_idx_block = _GEN_186; // @[lsu.scala:416:36, :431:36] wire _ldq_retry_idx_T = ldq_0_bits_addr_valid & ldq_0_bits_addr_is_virtual; // @[lsu.scala:208:16, :417:18] wire _ldq_retry_idx_T_1 = ~ldq_retry_idx_block; // @[lsu.scala:416:36, :417:42] wire _ldq_retry_idx_T_2 = _ldq_retry_idx_T & _ldq_retry_idx_T_1; // @[lsu.scala:417:{18,39,42}] wire _GEN_187 = block_load_mask_1 | p1_block_load_mask_1; // @[lsu.scala:396:36, :397:35, :416:36] wire ldq_retry_idx_block_1; // @[lsu.scala:416:36] assign ldq_retry_idx_block_1 = _GEN_187; // @[lsu.scala:416:36] wire ldq_wakeup_idx_block_1; // @[lsu.scala:431:36] assign ldq_wakeup_idx_block_1 = _GEN_187; // @[lsu.scala:416:36, :431:36] wire _ldq_retry_idx_T_3 = ldq_1_bits_addr_valid & ldq_1_bits_addr_is_virtual; // @[lsu.scala:208:16, :417:18] wire _ldq_retry_idx_T_4 = ~ldq_retry_idx_block_1; // @[lsu.scala:416:36, :417:42] wire _ldq_retry_idx_T_5 = _ldq_retry_idx_T_3 & _ldq_retry_idx_T_4; // @[lsu.scala:417:{18,39,42}] wire _GEN_188 = block_load_mask_2 | p1_block_load_mask_2; // @[lsu.scala:396:36, :397:35, :416:36] wire ldq_retry_idx_block_2; // @[lsu.scala:416:36] assign ldq_retry_idx_block_2 = _GEN_188; // @[lsu.scala:416:36] wire ldq_wakeup_idx_block_2; // @[lsu.scala:431:36] assign ldq_wakeup_idx_block_2 = _GEN_188; // @[lsu.scala:416:36, :431:36] wire _ldq_retry_idx_T_6 = ldq_2_bits_addr_valid & ldq_2_bits_addr_is_virtual; // @[lsu.scala:208:16, :417:18] wire _ldq_retry_idx_T_7 = ~ldq_retry_idx_block_2; // @[lsu.scala:416:36, :417:42] wire _ldq_retry_idx_T_8 = _ldq_retry_idx_T_6 & _ldq_retry_idx_T_7; // @[lsu.scala:417:{18,39,42}] wire _GEN_189 = block_load_mask_3 | p1_block_load_mask_3; // @[lsu.scala:396:36, :397:35, :416:36] wire ldq_retry_idx_block_3; // @[lsu.scala:416:36] assign ldq_retry_idx_block_3 = _GEN_189; // @[lsu.scala:416:36] wire ldq_wakeup_idx_block_3; // @[lsu.scala:431:36] assign ldq_wakeup_idx_block_3 = _GEN_189; // @[lsu.scala:416:36, :431:36] wire _ldq_retry_idx_T_9 = ldq_3_bits_addr_valid & ldq_3_bits_addr_is_virtual; // @[lsu.scala:208:16, :417:18] wire _ldq_retry_idx_T_10 = ~ldq_retry_idx_block_3; // @[lsu.scala:416:36, :417:42] wire _ldq_retry_idx_T_11 = _ldq_retry_idx_T_9 & _ldq_retry_idx_T_10; // @[lsu.scala:417:{18,39,42}] wire _GEN_190 = block_load_mask_4 | p1_block_load_mask_4; // @[lsu.scala:396:36, :397:35, :416:36] wire ldq_retry_idx_block_4; // @[lsu.scala:416:36] assign ldq_retry_idx_block_4 = _GEN_190; // @[lsu.scala:416:36] wire ldq_wakeup_idx_block_4; // @[lsu.scala:431:36] assign ldq_wakeup_idx_block_4 = _GEN_190; // @[lsu.scala:416:36, :431:36] wire _ldq_retry_idx_T_12 = ldq_4_bits_addr_valid & ldq_4_bits_addr_is_virtual; // @[lsu.scala:208:16, :417:18] wire _ldq_retry_idx_T_13 = ~ldq_retry_idx_block_4; // @[lsu.scala:416:36, :417:42] wire _ldq_retry_idx_T_14 = _ldq_retry_idx_T_12 & _ldq_retry_idx_T_13; // @[lsu.scala:417:{18,39,42}] wire _GEN_191 = block_load_mask_5 | p1_block_load_mask_5; // @[lsu.scala:396:36, :397:35, :416:36] wire ldq_retry_idx_block_5; // @[lsu.scala:416:36] assign ldq_retry_idx_block_5 = _GEN_191; // @[lsu.scala:416:36] wire ldq_wakeup_idx_block_5; // @[lsu.scala:431:36] assign ldq_wakeup_idx_block_5 = _GEN_191; // @[lsu.scala:416:36, :431:36] wire _ldq_retry_idx_T_15 = ldq_5_bits_addr_valid & ldq_5_bits_addr_is_virtual; // @[lsu.scala:208:16, :417:18] wire _ldq_retry_idx_T_16 = ~ldq_retry_idx_block_5; // @[lsu.scala:416:36, :417:42] wire _ldq_retry_idx_T_17 = _ldq_retry_idx_T_15 & _ldq_retry_idx_T_16; // @[lsu.scala:417:{18,39,42}] wire _GEN_192 = block_load_mask_6 | p1_block_load_mask_6; // @[lsu.scala:396:36, :397:35, :416:36] wire ldq_retry_idx_block_6; // @[lsu.scala:416:36] assign ldq_retry_idx_block_6 = _GEN_192; // @[lsu.scala:416:36] wire ldq_wakeup_idx_block_6; // @[lsu.scala:431:36] assign ldq_wakeup_idx_block_6 = _GEN_192; // @[lsu.scala:416:36, :431:36] wire _ldq_retry_idx_T_18 = ldq_6_bits_addr_valid & ldq_6_bits_addr_is_virtual; // @[lsu.scala:208:16, :417:18] wire _ldq_retry_idx_T_19 = ~ldq_retry_idx_block_6; // @[lsu.scala:416:36, :417:42] wire _ldq_retry_idx_T_20 = _ldq_retry_idx_T_18 & _ldq_retry_idx_T_19; // @[lsu.scala:417:{18,39,42}] wire _GEN_193 = block_load_mask_7 | p1_block_load_mask_7; // @[lsu.scala:396:36, :397:35, :416:36] wire ldq_retry_idx_block_7; // @[lsu.scala:416:36] assign ldq_retry_idx_block_7 = _GEN_193; // @[lsu.scala:416:36] wire ldq_wakeup_idx_block_7; // @[lsu.scala:431:36] assign ldq_wakeup_idx_block_7 = _GEN_193; // @[lsu.scala:416:36, :431:36] wire _ldq_retry_idx_T_21 = ldq_7_bits_addr_valid & ldq_7_bits_addr_is_virtual; // @[lsu.scala:208:16, :417:18] wire _ldq_retry_idx_T_22 = ~ldq_retry_idx_block_7; // @[lsu.scala:416:36, :417:42] wire _ldq_retry_idx_T_23 = _ldq_retry_idx_T_21 & _ldq_retry_idx_T_22; // @[lsu.scala:417:{18,39,42}] wire ldq_retry_idx_temp_vec_7 = _ldq_retry_idx_T_23; // @[util.scala:351:65] wire _GEN_194 = ldq_head == 3'h0; // @[util.scala:351:72] wire _ldq_retry_idx_temp_vec_T; // @[util.scala:351:72] assign _ldq_retry_idx_temp_vec_T = _GEN_194; // @[util.scala:351:72] wire _ldq_wakeup_idx_temp_vec_T; // @[util.scala:351:72] assign _ldq_wakeup_idx_temp_vec_T = _GEN_194; // @[util.scala:351:72] wire _temp_bits_T; // @[lsu.scala:1230:28] assign _temp_bits_T = _GEN_194; // @[util.scala:351:72] wire ldq_retry_idx_temp_vec_0 = _ldq_retry_idx_T_2 & _ldq_retry_idx_temp_vec_T; // @[util.scala:351:{65,72}] wire _GEN_195 = ldq_head < 3'h2; // @[util.scala:351:72] wire _ldq_retry_idx_temp_vec_T_1; // @[util.scala:351:72] assign _ldq_retry_idx_temp_vec_T_1 = _GEN_195; // @[util.scala:351:72] wire _ldq_wakeup_idx_temp_vec_T_1; // @[util.scala:351:72] assign _ldq_wakeup_idx_temp_vec_T_1 = _GEN_195; // @[util.scala:351:72] wire _temp_bits_T_2; // @[lsu.scala:1230:28] assign _temp_bits_T_2 = _GEN_195; // @[util.scala:351:72] wire ldq_retry_idx_temp_vec_1 = _ldq_retry_idx_T_5 & _ldq_retry_idx_temp_vec_T_1; // @[util.scala:351:{65,72}] wire _GEN_196 = ldq_head < 3'h3; // @[util.scala:351:72] wire _ldq_retry_idx_temp_vec_T_2; // @[util.scala:351:72] assign _ldq_retry_idx_temp_vec_T_2 = _GEN_196; // @[util.scala:351:72] wire _ldq_wakeup_idx_temp_vec_T_2; // @[util.scala:351:72] assign _ldq_wakeup_idx_temp_vec_T_2 = _GEN_196; // @[util.scala:351:72] wire _temp_bits_T_4; // @[lsu.scala:1230:28] assign _temp_bits_T_4 = _GEN_196; // @[util.scala:351:72] wire ldq_retry_idx_temp_vec_2 = _ldq_retry_idx_T_8 & _ldq_retry_idx_temp_vec_T_2; // @[util.scala:351:{65,72}] wire _searcher_is_older_T_15 = ldq_head[2]; // @[util.scala:351:72, :363:78] wire _ldq_retry_idx_temp_vec_T_3 = ~_searcher_is_older_T_15; // @[util.scala:351:72, :363:78] wire ldq_retry_idx_temp_vec_3 = _ldq_retry_idx_T_11 & _ldq_retry_idx_temp_vec_T_3; // @[util.scala:351:{65,72}] wire _GEN_197 = ldq_head < 3'h5; // @[util.scala:351:72] wire _ldq_retry_idx_temp_vec_T_4; // @[util.scala:351:72] assign _ldq_retry_idx_temp_vec_T_4 = _GEN_197; // @[util.scala:351:72] wire _ldq_wakeup_idx_temp_vec_T_4; // @[util.scala:351:72] assign _ldq_wakeup_idx_temp_vec_T_4 = _GEN_197; // @[util.scala:351:72] wire _temp_bits_T_8; // @[lsu.scala:1230:28] assign _temp_bits_T_8 = _GEN_197; // @[util.scala:351:72] wire ldq_retry_idx_temp_vec_4 = _ldq_retry_idx_T_14 & _ldq_retry_idx_temp_vec_T_4; // @[util.scala:351:{65,72}] wire _GEN_198 = ldq_head[2:1] != 2'h3; // @[util.scala:351:72] wire _ldq_retry_idx_temp_vec_T_5; // @[util.scala:351:72] assign _ldq_retry_idx_temp_vec_T_5 = _GEN_198; // @[util.scala:351:72] wire _ldq_wakeup_idx_temp_vec_T_5; // @[util.scala:351:72] assign _ldq_wakeup_idx_temp_vec_T_5 = _GEN_198; // @[util.scala:351:72] wire _temp_bits_T_10; // @[lsu.scala:1230:28] assign _temp_bits_T_10 = _GEN_198; // @[util.scala:351:72] wire ldq_retry_idx_temp_vec_5 = _ldq_retry_idx_T_17 & _ldq_retry_idx_temp_vec_T_5; // @[util.scala:351:{65,72}] wire _GEN_199 = ldq_head != 3'h7; // @[util.scala:351:72] wire _ldq_retry_idx_temp_vec_T_6; // @[util.scala:351:72] assign _ldq_retry_idx_temp_vec_T_6 = _GEN_199; // @[util.scala:351:72] wire _ldq_wakeup_idx_temp_vec_T_6; // @[util.scala:351:72] assign _ldq_wakeup_idx_temp_vec_T_6 = _GEN_199; // @[util.scala:351:72] wire _temp_bits_T_12; // @[lsu.scala:1230:28] assign _temp_bits_T_12 = _GEN_199; // @[util.scala:351:72] wire ldq_retry_idx_temp_vec_6 = _ldq_retry_idx_T_20 & _ldq_retry_idx_temp_vec_T_6; // @[util.scala:351:{65,72}] wire [3:0] _ldq_retry_idx_idx_T = {3'h7, ~_ldq_retry_idx_T_20}; // @[Mux.scala:50:70] wire [3:0] _ldq_retry_idx_idx_T_1 = _ldq_retry_idx_T_17 ? 4'hD : _ldq_retry_idx_idx_T; // @[Mux.scala:50:70] wire [3:0] _ldq_retry_idx_idx_T_2 = _ldq_retry_idx_T_14 ? 4'hC : _ldq_retry_idx_idx_T_1; // @[Mux.scala:50:70] wire [3:0] _ldq_retry_idx_idx_T_3 = _ldq_retry_idx_T_11 ? 4'hB : _ldq_retry_idx_idx_T_2; // @[Mux.scala:50:70] wire [3:0] _ldq_retry_idx_idx_T_4 = _ldq_retry_idx_T_8 ? 4'hA : _ldq_retry_idx_idx_T_3; // @[Mux.scala:50:70] wire [3:0] _ldq_retry_idx_idx_T_5 = _ldq_retry_idx_T_5 ? 4'h9 : _ldq_retry_idx_idx_T_4; // @[Mux.scala:50:70] wire [3:0] _ldq_retry_idx_idx_T_6 = _ldq_retry_idx_T_2 ? 4'h8 : _ldq_retry_idx_idx_T_5; // @[Mux.scala:50:70] wire [3:0] _ldq_retry_idx_idx_T_7 = ldq_retry_idx_temp_vec_7 ? 4'h7 : _ldq_retry_idx_idx_T_6; // @[Mux.scala:50:70] wire [3:0] _ldq_retry_idx_idx_T_8 = ldq_retry_idx_temp_vec_6 ? 4'h6 : _ldq_retry_idx_idx_T_7; // @[Mux.scala:50:70] wire [3:0] _ldq_retry_idx_idx_T_9 = ldq_retry_idx_temp_vec_5 ? 4'h5 : _ldq_retry_idx_idx_T_8; // @[Mux.scala:50:70] wire [3:0] _ldq_retry_idx_idx_T_10 = ldq_retry_idx_temp_vec_4 ? 4'h4 : _ldq_retry_idx_idx_T_9; // @[Mux.scala:50:70] wire [3:0] _ldq_retry_idx_idx_T_11 = ldq_retry_idx_temp_vec_3 ? 4'h3 : _ldq_retry_idx_idx_T_10; // @[Mux.scala:50:70] wire [3:0] _ldq_retry_idx_idx_T_12 = ldq_retry_idx_temp_vec_2 ? 4'h2 : _ldq_retry_idx_idx_T_11; // @[Mux.scala:50:70] wire [3:0] _ldq_retry_idx_idx_T_13 = ldq_retry_idx_temp_vec_1 ? 4'h1 : _ldq_retry_idx_idx_T_12; // @[Mux.scala:50:70] wire [3:0] ldq_retry_idx_idx = ldq_retry_idx_temp_vec_0 ? 4'h0 : _ldq_retry_idx_idx_T_13; // @[Mux.scala:50:70] wire [2:0] _ldq_retry_idx_T_24 = ldq_retry_idx_idx[2:0]; // @[Mux.scala:50:70] reg [2:0] ldq_retry_idx; // @[lsu.scala:414:30] wire [2:0] _ldq_retry_e_T = ldq_retry_idx; // @[lsu.scala:414:30] wire [2:0] _can_fire_load_retry_T_2 = ldq_retry_idx; // @[lsu.scala:414:30] wire [2:0] _can_fire_load_retry_T_6 = ldq_retry_idx; // @[lsu.scala:414:30] wire [2:0] _ldq_retry_e_T_1 = _ldq_retry_e_T; wire _stq_retry_idx_T = stq_0_bits_addr_valid & stq_0_bits_addr_is_virtual; // @[lsu.scala:209:16, :423:18] wire _stq_retry_idx_T_1 = stq_1_bits_addr_valid & stq_1_bits_addr_is_virtual; // @[lsu.scala:209:16, :423:18] wire _stq_retry_idx_T_2 = stq_2_bits_addr_valid & stq_2_bits_addr_is_virtual; // @[lsu.scala:209:16, :423:18] wire _stq_retry_idx_T_3 = stq_3_bits_addr_valid & stq_3_bits_addr_is_virtual; // @[lsu.scala:209:16, :423:18] wire _stq_retry_idx_T_4 = stq_4_bits_addr_valid & stq_4_bits_addr_is_virtual; // @[lsu.scala:209:16, :423:18] wire _stq_retry_idx_T_5 = stq_5_bits_addr_valid & stq_5_bits_addr_is_virtual; // @[lsu.scala:209:16, :423:18] wire _stq_retry_idx_T_6 = stq_6_bits_addr_valid & stq_6_bits_addr_is_virtual; // @[lsu.scala:209:16, :423:18] wire _stq_retry_idx_T_7 = stq_7_bits_addr_valid & stq_7_bits_addr_is_virtual; // @[lsu.scala:209:16, :423:18] wire stq_retry_idx_temp_vec_7 = _stq_retry_idx_T_7; // @[util.scala:351:65] wire _stq_retry_idx_temp_vec_T = stq_commit_head == 3'h0; // @[util.scala:351:72] wire stq_retry_idx_temp_vec_0 = _stq_retry_idx_T & _stq_retry_idx_temp_vec_T; // @[util.scala:351:{65,72}] wire _stq_retry_idx_temp_vec_T_1 = stq_commit_head < 3'h2; // @[util.scala:351:72] wire stq_retry_idx_temp_vec_1 = _stq_retry_idx_T_1 & _stq_retry_idx_temp_vec_T_1; // @[util.scala:351:{65,72}] wire _stq_retry_idx_temp_vec_T_2 = stq_commit_head < 3'h3; // @[util.scala:351:72] wire stq_retry_idx_temp_vec_2 = _stq_retry_idx_T_2 & _stq_retry_idx_temp_vec_T_2; // @[util.scala:351:{65,72}] wire _stq_retry_idx_temp_vec_T_3 = ~(stq_commit_head[2]); // @[util.scala:351:72] wire stq_retry_idx_temp_vec_3 = _stq_retry_idx_T_3 & _stq_retry_idx_temp_vec_T_3; // @[util.scala:351:{65,72}] wire _stq_retry_idx_temp_vec_T_4 = stq_commit_head < 3'h5; // @[util.scala:351:72] wire stq_retry_idx_temp_vec_4 = _stq_retry_idx_T_4 & _stq_retry_idx_temp_vec_T_4; // @[util.scala:351:{65,72}] wire _stq_retry_idx_temp_vec_T_5 = stq_commit_head[2:1] != 2'h3; // @[util.scala:351:72] wire stq_retry_idx_temp_vec_5 = _stq_retry_idx_T_5 & _stq_retry_idx_temp_vec_T_5; // @[util.scala:351:{65,72}] wire _stq_retry_idx_temp_vec_T_6 = stq_commit_head != 3'h7; // @[util.scala:351:72] wire stq_retry_idx_temp_vec_6 = _stq_retry_idx_T_6 & _stq_retry_idx_temp_vec_T_6; // @[util.scala:351:{65,72}] wire [3:0] _stq_retry_idx_idx_T = {3'h7, ~_stq_retry_idx_T_6}; // @[Mux.scala:50:70] wire [3:0] _stq_retry_idx_idx_T_1 = _stq_retry_idx_T_5 ? 4'hD : _stq_retry_idx_idx_T; // @[Mux.scala:50:70] wire [3:0] _stq_retry_idx_idx_T_2 = _stq_retry_idx_T_4 ? 4'hC : _stq_retry_idx_idx_T_1; // @[Mux.scala:50:70] wire [3:0] _stq_retry_idx_idx_T_3 = _stq_retry_idx_T_3 ? 4'hB : _stq_retry_idx_idx_T_2; // @[Mux.scala:50:70] wire [3:0] _stq_retry_idx_idx_T_4 = _stq_retry_idx_T_2 ? 4'hA : _stq_retry_idx_idx_T_3; // @[Mux.scala:50:70] wire [3:0] _stq_retry_idx_idx_T_5 = _stq_retry_idx_T_1 ? 4'h9 : _stq_retry_idx_idx_T_4; // @[Mux.scala:50:70] wire [3:0] _stq_retry_idx_idx_T_6 = _stq_retry_idx_T ? 4'h8 : _stq_retry_idx_idx_T_5; // @[Mux.scala:50:70] wire [3:0] _stq_retry_idx_idx_T_7 = stq_retry_idx_temp_vec_7 ? 4'h7 : _stq_retry_idx_idx_T_6; // @[Mux.scala:50:70] wire [3:0] _stq_retry_idx_idx_T_8 = stq_retry_idx_temp_vec_6 ? 4'h6 : _stq_retry_idx_idx_T_7; // @[Mux.scala:50:70] wire [3:0] _stq_retry_idx_idx_T_9 = stq_retry_idx_temp_vec_5 ? 4'h5 : _stq_retry_idx_idx_T_8; // @[Mux.scala:50:70] wire [3:0] _stq_retry_idx_idx_T_10 = stq_retry_idx_temp_vec_4 ? 4'h4 : _stq_retry_idx_idx_T_9; // @[Mux.scala:50:70] wire [3:0] _stq_retry_idx_idx_T_11 = stq_retry_idx_temp_vec_3 ? 4'h3 : _stq_retry_idx_idx_T_10; // @[Mux.scala:50:70] wire [3:0] _stq_retry_idx_idx_T_12 = stq_retry_idx_temp_vec_2 ? 4'h2 : _stq_retry_idx_idx_T_11; // @[Mux.scala:50:70] wire [3:0] _stq_retry_idx_idx_T_13 = stq_retry_idx_temp_vec_1 ? 4'h1 : _stq_retry_idx_idx_T_12; // @[Mux.scala:50:70] wire [3:0] stq_retry_idx_idx = stq_retry_idx_temp_vec_0 ? 4'h0 : _stq_retry_idx_idx_T_13; // @[Mux.scala:50:70] wire [2:0] _stq_retry_idx_T_8 = stq_retry_idx_idx[2:0]; // @[Mux.scala:50:70] reg [2:0] stq_retry_idx; // @[lsu.scala:421:30] wire [2:0] _stq_retry_e_T = stq_retry_idx; // @[lsu.scala:421:30] wire [2:0] _stq_retry_e_T_1 = _stq_retry_e_T; wire _ldq_wakeup_idx_T = ~ldq_0_bits_executed; // @[lsu.scala:208:16, :432:21] wire _ldq_wakeup_idx_T_1 = ldq_0_bits_addr_valid & _ldq_wakeup_idx_T; // @[lsu.scala:208:16, :432:{18,21}] wire _ldq_wakeup_idx_T_2 = ~ldq_0_bits_succeeded; // @[lsu.scala:208:16, :432:36] wire _ldq_wakeup_idx_T_3 = _ldq_wakeup_idx_T_1 & _ldq_wakeup_idx_T_2; // @[lsu.scala:432:{18,33,36}] wire _ldq_wakeup_idx_T_4 = ~ldq_0_bits_addr_is_virtual; // @[lsu.scala:208:16, :432:52] wire _ldq_wakeup_idx_T_5 = _ldq_wakeup_idx_T_3 & _ldq_wakeup_idx_T_4; // @[lsu.scala:432:{33,49,52}] wire _ldq_wakeup_idx_T_6 = ~ldq_wakeup_idx_block; // @[lsu.scala:431:36, :432:74] wire _ldq_wakeup_idx_T_7 = _ldq_wakeup_idx_T_5 & _ldq_wakeup_idx_T_6; // @[lsu.scala:432:{49,71,74}] wire _ldq_wakeup_idx_T_8 = ~ldq_1_bits_executed; // @[lsu.scala:208:16, :432:21] wire _ldq_wakeup_idx_T_9 = ldq_1_bits_addr_valid & _ldq_wakeup_idx_T_8; // @[lsu.scala:208:16, :432:{18,21}] wire _ldq_wakeup_idx_T_10 = ~ldq_1_bits_succeeded; // @[lsu.scala:208:16, :432:36] wire _ldq_wakeup_idx_T_11 = _ldq_wakeup_idx_T_9 & _ldq_wakeup_idx_T_10; // @[lsu.scala:432:{18,33,36}] wire _ldq_wakeup_idx_T_12 = ~ldq_1_bits_addr_is_virtual; // @[lsu.scala:208:16, :432:52] wire _ldq_wakeup_idx_T_13 = _ldq_wakeup_idx_T_11 & _ldq_wakeup_idx_T_12; // @[lsu.scala:432:{33,49,52}] wire _ldq_wakeup_idx_T_14 = ~ldq_wakeup_idx_block_1; // @[lsu.scala:431:36, :432:74] wire _ldq_wakeup_idx_T_15 = _ldq_wakeup_idx_T_13 & _ldq_wakeup_idx_T_14; // @[lsu.scala:432:{49,71,74}] wire _ldq_wakeup_idx_T_16 = ~ldq_2_bits_executed; // @[lsu.scala:208:16, :432:21] wire _ldq_wakeup_idx_T_17 = ldq_2_bits_addr_valid & _ldq_wakeup_idx_T_16; // @[lsu.scala:208:16, :432:{18,21}] wire _ldq_wakeup_idx_T_18 = ~ldq_2_bits_succeeded; // @[lsu.scala:208:16, :432:36] wire _ldq_wakeup_idx_T_19 = _ldq_wakeup_idx_T_17 & _ldq_wakeup_idx_T_18; // @[lsu.scala:432:{18,33,36}] wire _ldq_wakeup_idx_T_20 = ~ldq_2_bits_addr_is_virtual; // @[lsu.scala:208:16, :432:52] wire _ldq_wakeup_idx_T_21 = _ldq_wakeup_idx_T_19 & _ldq_wakeup_idx_T_20; // @[lsu.scala:432:{33,49,52}] wire _ldq_wakeup_idx_T_22 = ~ldq_wakeup_idx_block_2; // @[lsu.scala:431:36, :432:74] wire _ldq_wakeup_idx_T_23 = _ldq_wakeup_idx_T_21 & _ldq_wakeup_idx_T_22; // @[lsu.scala:432:{49,71,74}] wire _ldq_wakeup_idx_T_24 = ~ldq_3_bits_executed; // @[lsu.scala:208:16, :432:21] wire _ldq_wakeup_idx_T_25 = ldq_3_bits_addr_valid & _ldq_wakeup_idx_T_24; // @[lsu.scala:208:16, :432:{18,21}] wire _ldq_wakeup_idx_T_26 = ~ldq_3_bits_succeeded; // @[lsu.scala:208:16, :432:36] wire _ldq_wakeup_idx_T_27 = _ldq_wakeup_idx_T_25 & _ldq_wakeup_idx_T_26; // @[lsu.scala:432:{18,33,36}] wire _ldq_wakeup_idx_T_28 = ~ldq_3_bits_addr_is_virtual; // @[lsu.scala:208:16, :432:52] wire _ldq_wakeup_idx_T_29 = _ldq_wakeup_idx_T_27 & _ldq_wakeup_idx_T_28; // @[lsu.scala:432:{33,49,52}] wire _ldq_wakeup_idx_T_30 = ~ldq_wakeup_idx_block_3; // @[lsu.scala:431:36, :432:74] wire _ldq_wakeup_idx_T_31 = _ldq_wakeup_idx_T_29 & _ldq_wakeup_idx_T_30; // @[lsu.scala:432:{49,71,74}] wire _ldq_wakeup_idx_T_32 = ~ldq_4_bits_executed; // @[lsu.scala:208:16, :432:21] wire _ldq_wakeup_idx_T_33 = ldq_4_bits_addr_valid & _ldq_wakeup_idx_T_32; // @[lsu.scala:208:16, :432:{18,21}] wire _ldq_wakeup_idx_T_34 = ~ldq_4_bits_succeeded; // @[lsu.scala:208:16, :432:36] wire _ldq_wakeup_idx_T_35 = _ldq_wakeup_idx_T_33 & _ldq_wakeup_idx_T_34; // @[lsu.scala:432:{18,33,36}] wire _ldq_wakeup_idx_T_36 = ~ldq_4_bits_addr_is_virtual; // @[lsu.scala:208:16, :432:52] wire _ldq_wakeup_idx_T_37 = _ldq_wakeup_idx_T_35 & _ldq_wakeup_idx_T_36; // @[lsu.scala:432:{33,49,52}] wire _ldq_wakeup_idx_T_38 = ~ldq_wakeup_idx_block_4; // @[lsu.scala:431:36, :432:74] wire _ldq_wakeup_idx_T_39 = _ldq_wakeup_idx_T_37 & _ldq_wakeup_idx_T_38; // @[lsu.scala:432:{49,71,74}] wire _ldq_wakeup_idx_T_40 = ~ldq_5_bits_executed; // @[lsu.scala:208:16, :432:21] wire _ldq_wakeup_idx_T_41 = ldq_5_bits_addr_valid & _ldq_wakeup_idx_T_40; // @[lsu.scala:208:16, :432:{18,21}] wire _ldq_wakeup_idx_T_42 = ~ldq_5_bits_succeeded; // @[lsu.scala:208:16, :432:36] wire _ldq_wakeup_idx_T_43 = _ldq_wakeup_idx_T_41 & _ldq_wakeup_idx_T_42; // @[lsu.scala:432:{18,33,36}] wire _ldq_wakeup_idx_T_44 = ~ldq_5_bits_addr_is_virtual; // @[lsu.scala:208:16, :432:52] wire _ldq_wakeup_idx_T_45 = _ldq_wakeup_idx_T_43 & _ldq_wakeup_idx_T_44; // @[lsu.scala:432:{33,49,52}] wire _ldq_wakeup_idx_T_46 = ~ldq_wakeup_idx_block_5; // @[lsu.scala:431:36, :432:74] wire _ldq_wakeup_idx_T_47 = _ldq_wakeup_idx_T_45 & _ldq_wakeup_idx_T_46; // @[lsu.scala:432:{49,71,74}] wire _ldq_wakeup_idx_T_48 = ~ldq_6_bits_executed; // @[lsu.scala:208:16, :432:21] wire _ldq_wakeup_idx_T_49 = ldq_6_bits_addr_valid & _ldq_wakeup_idx_T_48; // @[lsu.scala:208:16, :432:{18,21}] wire _ldq_wakeup_idx_T_50 = ~ldq_6_bits_succeeded; // @[lsu.scala:208:16, :432:36] wire _ldq_wakeup_idx_T_51 = _ldq_wakeup_idx_T_49 & _ldq_wakeup_idx_T_50; // @[lsu.scala:432:{18,33,36}] wire _ldq_wakeup_idx_T_52 = ~ldq_6_bits_addr_is_virtual; // @[lsu.scala:208:16, :432:52] wire _ldq_wakeup_idx_T_53 = _ldq_wakeup_idx_T_51 & _ldq_wakeup_idx_T_52; // @[lsu.scala:432:{33,49,52}] wire _ldq_wakeup_idx_T_54 = ~ldq_wakeup_idx_block_6; // @[lsu.scala:431:36, :432:74] wire _ldq_wakeup_idx_T_55 = _ldq_wakeup_idx_T_53 & _ldq_wakeup_idx_T_54; // @[lsu.scala:432:{49,71,74}] wire _ldq_wakeup_idx_T_56 = ~ldq_7_bits_executed; // @[lsu.scala:208:16, :432:21] wire _ldq_wakeup_idx_T_57 = ldq_7_bits_addr_valid & _ldq_wakeup_idx_T_56; // @[lsu.scala:208:16, :432:{18,21}] wire _ldq_wakeup_idx_T_58 = ~ldq_7_bits_succeeded; // @[lsu.scala:208:16, :432:36] wire _ldq_wakeup_idx_T_59 = _ldq_wakeup_idx_T_57 & _ldq_wakeup_idx_T_58; // @[lsu.scala:432:{18,33,36}] wire _ldq_wakeup_idx_T_60 = ~ldq_7_bits_addr_is_virtual; // @[lsu.scala:208:16, :432:52] wire _ldq_wakeup_idx_T_61 = _ldq_wakeup_idx_T_59 & _ldq_wakeup_idx_T_60; // @[lsu.scala:432:{33,49,52}] wire _ldq_wakeup_idx_T_62 = ~ldq_wakeup_idx_block_7; // @[lsu.scala:431:36, :432:74] wire _ldq_wakeup_idx_T_63 = _ldq_wakeup_idx_T_61 & _ldq_wakeup_idx_T_62; // @[lsu.scala:432:{49,71,74}] wire ldq_wakeup_idx_temp_vec_7 = _ldq_wakeup_idx_T_63; // @[util.scala:351:65] wire ldq_wakeup_idx_temp_vec_0 = _ldq_wakeup_idx_T_7 & _ldq_wakeup_idx_temp_vec_T; // @[util.scala:351:{65,72}] wire ldq_wakeup_idx_temp_vec_1 = _ldq_wakeup_idx_T_15 & _ldq_wakeup_idx_temp_vec_T_1; // @[util.scala:351:{65,72}] wire ldq_wakeup_idx_temp_vec_2 = _ldq_wakeup_idx_T_23 & _ldq_wakeup_idx_temp_vec_T_2; // @[util.scala:351:{65,72}] wire _ldq_wakeup_idx_temp_vec_T_3 = ~_searcher_is_older_T_15; // @[util.scala:351:72, :363:78] wire ldq_wakeup_idx_temp_vec_3 = _ldq_wakeup_idx_T_31 & _ldq_wakeup_idx_temp_vec_T_3; // @[util.scala:351:{65,72}] wire ldq_wakeup_idx_temp_vec_4 = _ldq_wakeup_idx_T_39 & _ldq_wakeup_idx_temp_vec_T_4; // @[util.scala:351:{65,72}] wire ldq_wakeup_idx_temp_vec_5 = _ldq_wakeup_idx_T_47 & _ldq_wakeup_idx_temp_vec_T_5; // @[util.scala:351:{65,72}] wire ldq_wakeup_idx_temp_vec_6 = _ldq_wakeup_idx_T_55 & _ldq_wakeup_idx_temp_vec_T_6; // @[util.scala:351:{65,72}] wire [3:0] _ldq_wakeup_idx_idx_T = {3'h7, ~_ldq_wakeup_idx_T_55}; // @[Mux.scala:50:70] wire [3:0] _ldq_wakeup_idx_idx_T_1 = _ldq_wakeup_idx_T_47 ? 4'hD : _ldq_wakeup_idx_idx_T; // @[Mux.scala:50:70] wire [3:0] _ldq_wakeup_idx_idx_T_2 = _ldq_wakeup_idx_T_39 ? 4'hC : _ldq_wakeup_idx_idx_T_1; // @[Mux.scala:50:70] wire [3:0] _ldq_wakeup_idx_idx_T_3 = _ldq_wakeup_idx_T_31 ? 4'hB : _ldq_wakeup_idx_idx_T_2; // @[Mux.scala:50:70] wire [3:0] _ldq_wakeup_idx_idx_T_4 = _ldq_wakeup_idx_T_23 ? 4'hA : _ldq_wakeup_idx_idx_T_3; // @[Mux.scala:50:70] wire [3:0] _ldq_wakeup_idx_idx_T_5 = _ldq_wakeup_idx_T_15 ? 4'h9 : _ldq_wakeup_idx_idx_T_4; // @[Mux.scala:50:70] wire [3:0] _ldq_wakeup_idx_idx_T_6 = _ldq_wakeup_idx_T_7 ? 4'h8 : _ldq_wakeup_idx_idx_T_5; // @[Mux.scala:50:70] wire [3:0] _ldq_wakeup_idx_idx_T_7 = ldq_wakeup_idx_temp_vec_7 ? 4'h7 : _ldq_wakeup_idx_idx_T_6; // @[Mux.scala:50:70] wire [3:0] _ldq_wakeup_idx_idx_T_8 = ldq_wakeup_idx_temp_vec_6 ? 4'h6 : _ldq_wakeup_idx_idx_T_7; // @[Mux.scala:50:70] wire [3:0] _ldq_wakeup_idx_idx_T_9 = ldq_wakeup_idx_temp_vec_5 ? 4'h5 : _ldq_wakeup_idx_idx_T_8; // @[Mux.scala:50:70] wire [3:0] _ldq_wakeup_idx_idx_T_10 = ldq_wakeup_idx_temp_vec_4 ? 4'h4 : _ldq_wakeup_idx_idx_T_9; // @[Mux.scala:50:70] wire [3:0] _ldq_wakeup_idx_idx_T_11 = ldq_wakeup_idx_temp_vec_3 ? 4'h3 : _ldq_wakeup_idx_idx_T_10; // @[Mux.scala:50:70] wire [3:0] _ldq_wakeup_idx_idx_T_12 = ldq_wakeup_idx_temp_vec_2 ? 4'h2 : _ldq_wakeup_idx_idx_T_11; // @[Mux.scala:50:70] wire [3:0] _ldq_wakeup_idx_idx_T_13 = ldq_wakeup_idx_temp_vec_1 ? 4'h1 : _ldq_wakeup_idx_idx_T_12; // @[Mux.scala:50:70] wire [3:0] ldq_wakeup_idx_idx = ldq_wakeup_idx_temp_vec_0 ? 4'h0 : _ldq_wakeup_idx_idx_T_13; // @[Mux.scala:50:70] wire [2:0] _ldq_wakeup_idx_T_64 = ldq_wakeup_idx_idx[2:0]; // @[Mux.scala:50:70] reg [2:0] ldq_wakeup_idx; // @[lsu.scala:429:31] wire [2:0] _ldq_wakeup_e_T = ldq_wakeup_idx; // @[lsu.scala:429:31] wire [2:0] _can_fire_load_wakeup_T_9 = ldq_wakeup_idx; // @[lsu.scala:429:31] wire [2:0] _can_fire_load_wakeup_T_13 = ldq_wakeup_idx; // @[lsu.scala:429:31] wire [2:0] _ldq_wakeup_e_T_1 = _ldq_wakeup_e_T; wire _can_fire_load_incoming_T = exe_req_0_valid & exe_req_0_bits_uop_ctrl_is_load; // @[lsu.scala:383:25, :440:63] wire can_fire_load_incoming_0 = _can_fire_load_incoming_T; // @[lsu.scala:263:49, :440:63] wire _will_fire_load_incoming_0_will_fire_T_3 = can_fire_load_incoming_0; // @[lsu.scala:263:49, :533:32] wire _GEN_200 = exe_req_0_valid & exe_req_0_bits_uop_ctrl_is_sta; // @[lsu.scala:383:25, :443:63] wire _can_fire_stad_incoming_T; // @[lsu.scala:443:63] assign _can_fire_stad_incoming_T = _GEN_200; // @[lsu.scala:443:63] wire _can_fire_sta_incoming_T; // @[lsu.scala:447:63] assign _can_fire_sta_incoming_T = _GEN_200; // @[lsu.scala:443:63, :447:63] wire _can_fire_stad_incoming_T_1 = _can_fire_stad_incoming_T & exe_req_0_bits_uop_ctrl_is_std; // @[lsu.scala:383:25, :443:63, :444:63] wire can_fire_stad_incoming_0 = _can_fire_stad_incoming_T_1; // @[lsu.scala:263:49, :444:63] wire _can_fire_sta_incoming_T_1 = ~exe_req_0_bits_uop_ctrl_is_std; // @[lsu.scala:383:25, :448:66] wire _can_fire_sta_incoming_T_2 = _can_fire_sta_incoming_T & _can_fire_sta_incoming_T_1; // @[lsu.scala:447:63, :448:{63,66}] wire can_fire_sta_incoming_0 = _can_fire_sta_incoming_T_2; // @[lsu.scala:263:49, :448:63] wire _can_fire_std_incoming_T = exe_req_0_valid & exe_req_0_bits_uop_ctrl_is_std; // @[lsu.scala:383:25, :451:63] wire _can_fire_std_incoming_T_1 = ~exe_req_0_bits_uop_ctrl_is_sta; // @[lsu.scala:383:25, :452:66] wire _can_fire_std_incoming_T_2 = _can_fire_std_incoming_T & _can_fire_std_incoming_T_1; // @[lsu.scala:451:63, :452:{63,66}] wire can_fire_std_incoming_0 = _can_fire_std_incoming_T_2; // @[lsu.scala:263:49, :452:63] wire _will_fire_std_incoming_0_will_fire_T_3 = can_fire_std_incoming_0; // @[lsu.scala:263:49, :533:32] wire _can_fire_sfence_T = exe_req_0_valid & exe_req_0_bits_sfence_valid; // @[lsu.scala:383:25, :455:63] wire can_fire_sfence_0 = _can_fire_sfence_T; // @[lsu.scala:263:49, :455:63] wire can_fire_release_0 = _can_fire_release_T; // @[lsu.scala:263:49, :459:66] wire _will_fire_release_0_will_fire_T_3 = can_fire_release_0; // @[lsu.scala:263:49, :533:32] wire [6:0] mem_ldq_retry_e_out_bits_uop_uopc = _GEN_94[_ldq_retry_e_T_1]; // @[util.scala:106:23] wire [31:0] mem_ldq_retry_e_out_bits_uop_inst = _GEN_95[_ldq_retry_e_T_1]; // @[util.scala:106:23] wire [31:0] mem_ldq_retry_e_out_bits_uop_debug_inst = _GEN_96[_ldq_retry_e_T_1]; // @[util.scala:106:23] wire mem_ldq_retry_e_out_bits_uop_is_rvc = _GEN_97[_ldq_retry_e_T_1]; // @[util.scala:106:23] wire [39:0] mem_ldq_retry_e_out_bits_uop_debug_pc = _GEN_98[_ldq_retry_e_T_1]; // @[util.scala:106:23] wire [2:0] mem_ldq_retry_e_out_bits_uop_iq_type = _GEN_99[_ldq_retry_e_T_1]; // @[util.scala:106:23] wire [9:0] mem_ldq_retry_e_out_bits_uop_fu_code = _GEN_100[_ldq_retry_e_T_1]; // @[util.scala:106:23] wire [3:0] mem_ldq_retry_e_out_bits_uop_ctrl_br_type = _GEN_101[_ldq_retry_e_T_1]; // @[util.scala:106:23] wire [1:0] mem_ldq_retry_e_out_bits_uop_ctrl_op1_sel = _GEN_102[_ldq_retry_e_T_1]; // @[util.scala:106:23] wire [2:0] mem_ldq_retry_e_out_bits_uop_ctrl_op2_sel = _GEN_103[_ldq_retry_e_T_1]; // @[util.scala:106:23] wire [2:0] mem_ldq_retry_e_out_bits_uop_ctrl_imm_sel = _GEN_104[_ldq_retry_e_T_1]; // @[util.scala:106:23] wire [4:0] mem_ldq_retry_e_out_bits_uop_ctrl_op_fcn = _GEN_105[_ldq_retry_e_T_1]; // @[util.scala:106:23] wire mem_ldq_retry_e_out_bits_uop_ctrl_fcn_dw = _GEN_106[_ldq_retry_e_T_1]; // @[util.scala:106:23] wire [2:0] mem_ldq_retry_e_out_bits_uop_ctrl_csr_cmd = _GEN_107[_ldq_retry_e_T_1]; // @[util.scala:106:23] wire mem_ldq_retry_e_out_bits_uop_ctrl_is_load = _GEN_108[_ldq_retry_e_T_1]; // @[util.scala:106:23] wire mem_ldq_retry_e_out_bits_uop_ctrl_is_sta = _GEN_109[_ldq_retry_e_T_1]; // @[util.scala:106:23] wire mem_ldq_retry_e_out_bits_uop_ctrl_is_std = _GEN_110[_ldq_retry_e_T_1]; // @[util.scala:106:23] wire [1:0] mem_ldq_retry_e_out_bits_uop_iw_state = _GEN_111[_ldq_retry_e_T_1]; // @[util.scala:106:23] wire mem_ldq_retry_e_out_bits_uop_iw_p1_poisoned = _GEN_112[_ldq_retry_e_T_1]; // @[util.scala:106:23] wire mem_ldq_retry_e_out_bits_uop_iw_p2_poisoned = _GEN_113[_ldq_retry_e_T_1]; // @[util.scala:106:23] wire mem_ldq_retry_e_out_bits_uop_is_br = _GEN_114[_ldq_retry_e_T_1]; // @[util.scala:106:23] wire mem_ldq_retry_e_out_bits_uop_is_jalr = _GEN_115[_ldq_retry_e_T_1]; // @[util.scala:106:23] wire mem_ldq_retry_e_out_bits_uop_is_jal = _GEN_116[_ldq_retry_e_T_1]; // @[util.scala:106:23] wire mem_ldq_retry_e_out_bits_uop_is_sfb = _GEN_117[_ldq_retry_e_T_1]; // @[util.scala:106:23] wire [2:0] mem_ldq_retry_e_out_bits_uop_br_tag = _GEN_119[_ldq_retry_e_T_1]; // @[util.scala:106:23] wire [3:0] mem_ldq_retry_e_out_bits_uop_ftq_idx = _GEN_120[_ldq_retry_e_T_1]; // @[util.scala:106:23] wire mem_ldq_retry_e_out_bits_uop_edge_inst = _GEN_121[_ldq_retry_e_T_1]; // @[util.scala:106:23] wire [5:0] mem_ldq_retry_e_out_bits_uop_pc_lob = _GEN_122[_ldq_retry_e_T_1]; // @[util.scala:106:23] wire mem_ldq_retry_e_out_bits_uop_taken = _GEN_123[_ldq_retry_e_T_1]; // @[util.scala:106:23] wire [19:0] mem_ldq_retry_e_out_bits_uop_imm_packed = _GEN_124[_ldq_retry_e_T_1]; // @[util.scala:106:23] wire [11:0] mem_ldq_retry_e_out_bits_uop_csr_addr = _GEN_125[_ldq_retry_e_T_1]; // @[util.scala:106:23] wire [4:0] mem_ldq_retry_e_out_bits_uop_rob_idx = _GEN_126[_ldq_retry_e_T_1]; // @[util.scala:106:23] wire [2:0] mem_ldq_retry_e_out_bits_uop_ldq_idx = _GEN_127[_ldq_retry_e_T_1]; // @[util.scala:106:23] wire [2:0] mem_ldq_retry_e_out_bits_uop_stq_idx = _GEN_128[_ldq_retry_e_T_1]; // @[util.scala:106:23] wire [1:0] mem_ldq_retry_e_out_bits_uop_rxq_idx = _GEN_129[_ldq_retry_e_T_1]; // @[util.scala:106:23] wire [5:0] mem_ldq_retry_e_out_bits_uop_pdst = _GEN_130[_ldq_retry_e_T_1]; // @[util.scala:106:23] wire [5:0] mem_ldq_retry_e_out_bits_uop_prs1 = _GEN_131[_ldq_retry_e_T_1]; // @[util.scala:106:23] wire [5:0] mem_ldq_retry_e_out_bits_uop_prs2 = _GEN_132[_ldq_retry_e_T_1]; // @[util.scala:106:23] wire [5:0] mem_ldq_retry_e_out_bits_uop_prs3 = _GEN_133[_ldq_retry_e_T_1]; // @[util.scala:106:23] wire mem_ldq_retry_e_out_bits_uop_prs1_busy = _GEN_134[_ldq_retry_e_T_1]; // @[util.scala:106:23] wire mem_ldq_retry_e_out_bits_uop_prs2_busy = _GEN_135[_ldq_retry_e_T_1]; // @[util.scala:106:23] wire mem_ldq_retry_e_out_bits_uop_prs3_busy = _GEN_136[_ldq_retry_e_T_1]; // @[util.scala:106:23] wire [5:0] mem_ldq_retry_e_out_bits_uop_stale_pdst = _GEN_137[_ldq_retry_e_T_1]; // @[util.scala:106:23] wire mem_ldq_retry_e_out_bits_uop_exception = _GEN_138[_ldq_retry_e_T_1]; // @[util.scala:106:23] wire [63:0] mem_ldq_retry_e_out_bits_uop_exc_cause = _GEN_139[_ldq_retry_e_T_1]; // @[util.scala:106:23] wire mem_ldq_retry_e_out_bits_uop_bypassable = _GEN_140[_ldq_retry_e_T_1]; // @[util.scala:106:23] wire [4:0] mem_ldq_retry_e_out_bits_uop_mem_cmd = _GEN_141[_ldq_retry_e_T_1]; // @[util.scala:106:23] wire [1:0] mem_ldq_retry_e_out_bits_uop_mem_size = _GEN_142[_ldq_retry_e_T_1]; // @[util.scala:106:23] wire mem_ldq_retry_e_out_bits_uop_mem_signed = _GEN_143[_ldq_retry_e_T_1]; // @[util.scala:106:23] wire mem_ldq_retry_e_out_bits_uop_is_fence = _GEN_144[_ldq_retry_e_T_1]; // @[util.scala:106:23] wire mem_ldq_retry_e_out_bits_uop_is_fencei = _GEN_145[_ldq_retry_e_T_1]; // @[util.scala:106:23] wire mem_ldq_retry_e_out_bits_uop_is_amo = _GEN_146[_ldq_retry_e_T_1]; // @[util.scala:106:23] wire mem_ldq_retry_e_out_bits_uop_uses_ldq = _GEN_147[_ldq_retry_e_T_1]; // @[util.scala:106:23] wire mem_ldq_retry_e_out_bits_uop_uses_stq = _GEN_148[_ldq_retry_e_T_1]; // @[util.scala:106:23] wire mem_ldq_retry_e_out_bits_uop_is_sys_pc2epc = _GEN_149[_ldq_retry_e_T_1]; // @[util.scala:106:23] wire mem_ldq_retry_e_out_bits_uop_is_unique = _GEN_150[_ldq_retry_e_T_1]; // @[util.scala:106:23] wire mem_ldq_retry_e_out_bits_uop_flush_on_commit = _GEN_151[_ldq_retry_e_T_1]; // @[util.scala:106:23] wire mem_ldq_retry_e_out_bits_uop_ldst_is_rs1 = _GEN_152[_ldq_retry_e_T_1]; // @[util.scala:106:23] wire [5:0] mem_ldq_retry_e_out_bits_uop_ldst = _GEN_153[_ldq_retry_e_T_1]; // @[util.scala:106:23] wire [5:0] mem_ldq_retry_e_out_bits_uop_lrs1 = _GEN_154[_ldq_retry_e_T_1]; // @[util.scala:106:23] wire [5:0] mem_ldq_retry_e_out_bits_uop_lrs2 = _GEN_155[_ldq_retry_e_T_1]; // @[util.scala:106:23] wire [5:0] mem_ldq_retry_e_out_bits_uop_lrs3 = _GEN_156[_ldq_retry_e_T_1]; // @[util.scala:106:23] wire mem_ldq_retry_e_out_bits_uop_ldst_val = _GEN_157[_ldq_retry_e_T_1]; // @[util.scala:106:23] wire [1:0] mem_ldq_retry_e_out_bits_uop_dst_rtype = _GEN_158[_ldq_retry_e_T_1]; // @[util.scala:106:23] wire [1:0] mem_ldq_retry_e_out_bits_uop_lrs1_rtype = _GEN_159[_ldq_retry_e_T_1]; // @[util.scala:106:23] wire [1:0] mem_ldq_retry_e_out_bits_uop_lrs2_rtype = _GEN_160[_ldq_retry_e_T_1]; // @[util.scala:106:23] wire mem_ldq_retry_e_out_bits_uop_frs3_en = _GEN_161[_ldq_retry_e_T_1]; // @[util.scala:106:23] wire mem_ldq_retry_e_out_bits_uop_fp_val = _GEN_162[_ldq_retry_e_T_1]; // @[util.scala:106:23] wire mem_ldq_retry_e_out_bits_uop_fp_single = _GEN_163[_ldq_retry_e_T_1]; // @[util.scala:106:23] wire mem_ldq_retry_e_out_bits_uop_xcpt_pf_if = _GEN_164[_ldq_retry_e_T_1]; // @[util.scala:106:23] wire mem_ldq_retry_e_out_bits_uop_xcpt_ae_if = _GEN_165[_ldq_retry_e_T_1]; // @[util.scala:106:23] wire mem_ldq_retry_e_out_bits_uop_xcpt_ma_if = _GEN_166[_ldq_retry_e_T_1]; // @[util.scala:106:23] wire mem_ldq_retry_e_out_bits_uop_bp_debug_if = _GEN_167[_ldq_retry_e_T_1]; // @[util.scala:106:23] wire mem_ldq_retry_e_out_bits_uop_bp_xcpt_if = _GEN_168[_ldq_retry_e_T_1]; // @[util.scala:106:23] wire [1:0] mem_ldq_retry_e_out_bits_uop_debug_fsrc = _GEN_169[_ldq_retry_e_T_1]; // @[util.scala:106:23] wire [1:0] mem_ldq_retry_e_out_bits_uop_debug_tsrc = _GEN_170[_ldq_retry_e_T_1]; // @[util.scala:106:23] wire mem_ldq_retry_e_out_bits_addr_valid = _GEN_171[_ldq_retry_e_T_1]; // @[util.scala:106:23] wire [39:0] mem_ldq_retry_e_out_bits_addr_bits = _GEN_172[_ldq_retry_e_T_1]; // @[util.scala:106:23] wire mem_ldq_retry_e_out_bits_addr_is_virtual = _GEN_173[_ldq_retry_e_T_1]; // @[util.scala:106:23] wire mem_ldq_retry_e_out_bits_addr_is_uncacheable = _GEN_174[_ldq_retry_e_T_1]; // @[util.scala:106:23] wire mem_ldq_retry_e_out_bits_executed = _GEN_175[_ldq_retry_e_T_1]; // @[util.scala:106:23] wire mem_ldq_retry_e_out_bits_succeeded = _GEN_176[_ldq_retry_e_T_1]; // @[util.scala:106:23] wire mem_ldq_retry_e_out_bits_order_fail = _GEN_177[_ldq_retry_e_T_1]; // @[util.scala:106:23] wire mem_ldq_retry_e_out_bits_observed = _GEN_178[_ldq_retry_e_T_1]; // @[util.scala:106:23] wire [7:0] mem_ldq_retry_e_out_bits_st_dep_mask = _GEN_179[_ldq_retry_e_T_1]; // @[util.scala:106:23] wire [2:0] mem_ldq_retry_e_out_bits_youngest_stq_idx = _GEN_180[_ldq_retry_e_T_1]; // @[util.scala:106:23] wire mem_ldq_retry_e_out_bits_forward_std_val = _GEN_181[_ldq_retry_e_T_1]; // @[util.scala:106:23] wire [2:0] mem_ldq_retry_e_out_bits_forward_stq_idx = _GEN_182[_ldq_retry_e_T_1]; // @[util.scala:106:23] wire [63:0] mem_ldq_retry_e_out_bits_debug_wb_data = _GEN_183[_ldq_retry_e_T_1]; // @[util.scala:106:23] wire _can_fire_load_retry_T = _GEN_92[_ldq_retry_e_T_1] & mem_ldq_retry_e_out_bits_addr_valid; // @[util.scala:106:23] wire _can_fire_load_retry_T_1 = _can_fire_load_retry_T & mem_ldq_retry_e_out_bits_addr_is_virtual; // @[util.scala:106:23] wire [2:0] _can_fire_load_retry_T_3 = _can_fire_load_retry_T_2; wire [7:0] _GEN_201 = {{p1_block_load_mask_7}, {p1_block_load_mask_6}, {p1_block_load_mask_5}, {p1_block_load_mask_4}, {p1_block_load_mask_3}, {p1_block_load_mask_2}, {p1_block_load_mask_1}, {p1_block_load_mask_0}}; // @[lsu.scala:397:35, :467:33] wire _can_fire_load_retry_T_4 = ~_GEN_201[_can_fire_load_retry_T_3]; // @[lsu.scala:467:33] wire _can_fire_load_retry_T_5 = _can_fire_load_retry_T_1 & _can_fire_load_retry_T_4; // @[lsu.scala:465:79, :466:79, :467:33] wire [2:0] _can_fire_load_retry_T_7 = _can_fire_load_retry_T_6; wire [7:0] _GEN_202 = {{p2_block_load_mask_7}, {p2_block_load_mask_6}, {p2_block_load_mask_5}, {p2_block_load_mask_4}, {p2_block_load_mask_3}, {p2_block_load_mask_2}, {p2_block_load_mask_1}, {p2_block_load_mask_0}}; // @[lsu.scala:398:35, :468:33] wire _can_fire_load_retry_T_8 = ~_GEN_202[_can_fire_load_retry_T_7]; // @[lsu.scala:468:33] wire _can_fire_load_retry_T_9 = _can_fire_load_retry_T_5 & _can_fire_load_retry_T_8; // @[lsu.scala:466:79, :467:79, :468:33] reg can_fire_load_retry_REG; // @[lsu.scala:469:40] wire _can_fire_load_retry_T_10 = _can_fire_load_retry_T_9 & can_fire_load_retry_REG; // @[lsu.scala:467:79, :468:79, :469:40] wire _can_fire_load_retry_T_11 = ~store_needs_order; // @[lsu.scala:406:35, :470:33] wire _can_fire_load_retry_T_12 = _can_fire_load_retry_T_10 & _can_fire_load_retry_T_11; // @[lsu.scala:468:79, :469:79, :470:33] wire _can_fire_load_retry_T_13 = _can_fire_load_retry_T_12; // @[lsu.scala:469:79, :470:79] wire _can_fire_load_retry_T_14 = ~mem_ldq_retry_e_out_bits_order_fail; // @[util.scala:106:23] wire _can_fire_load_retry_T_15 = _can_fire_load_retry_T_13 & _can_fire_load_retry_T_14; // @[lsu.scala:470:79, :471:79, :472:33] wire can_fire_load_retry_0 = _can_fire_load_retry_T_15; // @[lsu.scala:263:49, :471:79] wire [6:0] mem_stq_retry_e_out_bits_uop_uopc = _GEN_1[_stq_retry_e_T_1]; // @[util.scala:106:23] wire [31:0] mem_stq_retry_e_out_bits_uop_inst = _GEN_2[_stq_retry_e_T_1]; // @[util.scala:106:23] wire [31:0] mem_stq_retry_e_out_bits_uop_debug_inst = _GEN_3[_stq_retry_e_T_1]; // @[util.scala:106:23] wire mem_stq_retry_e_out_bits_uop_is_rvc = _GEN_4[_stq_retry_e_T_1]; // @[util.scala:106:23] wire [39:0] mem_stq_retry_e_out_bits_uop_debug_pc = _GEN_5[_stq_retry_e_T_1]; // @[util.scala:106:23] wire [2:0] mem_stq_retry_e_out_bits_uop_iq_type = _GEN_6[_stq_retry_e_T_1]; // @[util.scala:106:23] wire [9:0] mem_stq_retry_e_out_bits_uop_fu_code = _GEN_7[_stq_retry_e_T_1]; // @[util.scala:106:23] wire [3:0] mem_stq_retry_e_out_bits_uop_ctrl_br_type = _GEN_8[_stq_retry_e_T_1]; // @[util.scala:106:23] wire [1:0] mem_stq_retry_e_out_bits_uop_ctrl_op1_sel = _GEN_9[_stq_retry_e_T_1]; // @[util.scala:106:23] wire [2:0] mem_stq_retry_e_out_bits_uop_ctrl_op2_sel = _GEN_10[_stq_retry_e_T_1]; // @[util.scala:106:23] wire [2:0] mem_stq_retry_e_out_bits_uop_ctrl_imm_sel = _GEN_11[_stq_retry_e_T_1]; // @[util.scala:106:23] wire [4:0] mem_stq_retry_e_out_bits_uop_ctrl_op_fcn = _GEN_12[_stq_retry_e_T_1]; // @[util.scala:106:23] wire mem_stq_retry_e_out_bits_uop_ctrl_fcn_dw = _GEN_13[_stq_retry_e_T_1]; // @[util.scala:106:23] wire [2:0] mem_stq_retry_e_out_bits_uop_ctrl_csr_cmd = _GEN_14[_stq_retry_e_T_1]; // @[util.scala:106:23] wire mem_stq_retry_e_out_bits_uop_ctrl_is_load = _GEN_15[_stq_retry_e_T_1]; // @[util.scala:106:23] wire mem_stq_retry_e_out_bits_uop_ctrl_is_sta = _GEN_16[_stq_retry_e_T_1]; // @[util.scala:106:23] wire mem_stq_retry_e_out_bits_uop_ctrl_is_std = _GEN_17[_stq_retry_e_T_1]; // @[util.scala:106:23] wire [1:0] mem_stq_retry_e_out_bits_uop_iw_state = _GEN_18[_stq_retry_e_T_1]; // @[util.scala:106:23] wire mem_stq_retry_e_out_bits_uop_iw_p1_poisoned = _GEN_19[_stq_retry_e_T_1]; // @[util.scala:106:23] wire mem_stq_retry_e_out_bits_uop_iw_p2_poisoned = _GEN_20[_stq_retry_e_T_1]; // @[util.scala:106:23] wire mem_stq_retry_e_out_bits_uop_is_br = _GEN_21[_stq_retry_e_T_1]; // @[util.scala:106:23] wire mem_stq_retry_e_out_bits_uop_is_jalr = _GEN_22[_stq_retry_e_T_1]; // @[util.scala:106:23] wire mem_stq_retry_e_out_bits_uop_is_jal = _GEN_23[_stq_retry_e_T_1]; // @[util.scala:106:23] wire mem_stq_retry_e_out_bits_uop_is_sfb = _GEN_24[_stq_retry_e_T_1]; // @[util.scala:106:23] wire [2:0] mem_stq_retry_e_out_bits_uop_br_tag = _GEN_26[_stq_retry_e_T_1]; // @[util.scala:106:23] wire [3:0] mem_stq_retry_e_out_bits_uop_ftq_idx = _GEN_27[_stq_retry_e_T_1]; // @[util.scala:106:23] wire mem_stq_retry_e_out_bits_uop_edge_inst = _GEN_28[_stq_retry_e_T_1]; // @[util.scala:106:23] wire [5:0] mem_stq_retry_e_out_bits_uop_pc_lob = _GEN_29[_stq_retry_e_T_1]; // @[util.scala:106:23] wire mem_stq_retry_e_out_bits_uop_taken = _GEN_30[_stq_retry_e_T_1]; // @[util.scala:106:23] wire [19:0] mem_stq_retry_e_out_bits_uop_imm_packed = _GEN_31[_stq_retry_e_T_1]; // @[util.scala:106:23] wire [11:0] mem_stq_retry_e_out_bits_uop_csr_addr = _GEN_32[_stq_retry_e_T_1]; // @[util.scala:106:23] wire [4:0] mem_stq_retry_e_out_bits_uop_rob_idx = _GEN_33[_stq_retry_e_T_1]; // @[util.scala:106:23] wire [2:0] mem_stq_retry_e_out_bits_uop_ldq_idx = _GEN_34[_stq_retry_e_T_1]; // @[util.scala:106:23] wire [2:0] mem_stq_retry_e_out_bits_uop_stq_idx = _GEN_35[_stq_retry_e_T_1]; // @[util.scala:106:23] wire [1:0] mem_stq_retry_e_out_bits_uop_rxq_idx = _GEN_36[_stq_retry_e_T_1]; // @[util.scala:106:23] wire [5:0] mem_stq_retry_e_out_bits_uop_pdst = _GEN_37[_stq_retry_e_T_1]; // @[util.scala:106:23] wire [5:0] mem_stq_retry_e_out_bits_uop_prs1 = _GEN_38[_stq_retry_e_T_1]; // @[util.scala:106:23] wire [5:0] mem_stq_retry_e_out_bits_uop_prs2 = _GEN_39[_stq_retry_e_T_1]; // @[util.scala:106:23] wire [5:0] mem_stq_retry_e_out_bits_uop_prs3 = _GEN_40[_stq_retry_e_T_1]; // @[util.scala:106:23] wire [3:0] mem_stq_retry_e_out_bits_uop_ppred = _GEN_41[_stq_retry_e_T_1]; // @[util.scala:106:23] wire mem_stq_retry_e_out_bits_uop_prs1_busy = _GEN_42[_stq_retry_e_T_1]; // @[util.scala:106:23] wire mem_stq_retry_e_out_bits_uop_prs2_busy = _GEN_43[_stq_retry_e_T_1]; // @[util.scala:106:23] wire mem_stq_retry_e_out_bits_uop_prs3_busy = _GEN_44[_stq_retry_e_T_1]; // @[util.scala:106:23] wire mem_stq_retry_e_out_bits_uop_ppred_busy = _GEN_45[_stq_retry_e_T_1]; // @[util.scala:106:23] wire [5:0] mem_stq_retry_e_out_bits_uop_stale_pdst = _GEN_46[_stq_retry_e_T_1]; // @[util.scala:106:23] wire mem_stq_retry_e_out_bits_uop_exception = _GEN_47[_stq_retry_e_T_1]; // @[util.scala:106:23] wire [63:0] mem_stq_retry_e_out_bits_uop_exc_cause = _GEN_49[_stq_retry_e_T_1]; // @[util.scala:106:23] wire mem_stq_retry_e_out_bits_uop_bypassable = _GEN_50[_stq_retry_e_T_1]; // @[util.scala:106:23] wire [4:0] mem_stq_retry_e_out_bits_uop_mem_cmd = _GEN_51[_stq_retry_e_T_1]; // @[util.scala:106:23] wire [1:0] mem_stq_retry_e_out_bits_uop_mem_size = _GEN_52[_stq_retry_e_T_1]; // @[util.scala:106:23] wire mem_stq_retry_e_out_bits_uop_mem_signed = _GEN_53[_stq_retry_e_T_1]; // @[util.scala:106:23] wire mem_stq_retry_e_out_bits_uop_is_fence = _GEN_54[_stq_retry_e_T_1]; // @[util.scala:106:23] wire mem_stq_retry_e_out_bits_uop_is_fencei = _GEN_56[_stq_retry_e_T_1]; // @[util.scala:106:23] wire mem_stq_retry_e_out_bits_uop_is_amo = _GEN_57[_stq_retry_e_T_1]; // @[util.scala:106:23] wire mem_stq_retry_e_out_bits_uop_uses_ldq = _GEN_59[_stq_retry_e_T_1]; // @[util.scala:106:23] wire mem_stq_retry_e_out_bits_uop_uses_stq = _GEN_60[_stq_retry_e_T_1]; // @[util.scala:106:23] wire mem_stq_retry_e_out_bits_uop_is_sys_pc2epc = _GEN_61[_stq_retry_e_T_1]; // @[util.scala:106:23] wire mem_stq_retry_e_out_bits_uop_is_unique = _GEN_62[_stq_retry_e_T_1]; // @[util.scala:106:23] wire mem_stq_retry_e_out_bits_uop_flush_on_commit = _GEN_63[_stq_retry_e_T_1]; // @[util.scala:106:23] wire mem_stq_retry_e_out_bits_uop_ldst_is_rs1 = _GEN_64[_stq_retry_e_T_1]; // @[util.scala:106:23] wire [5:0] mem_stq_retry_e_out_bits_uop_ldst = _GEN_65[_stq_retry_e_T_1]; // @[util.scala:106:23] wire [5:0] mem_stq_retry_e_out_bits_uop_lrs1 = _GEN_66[_stq_retry_e_T_1]; // @[util.scala:106:23] wire [5:0] mem_stq_retry_e_out_bits_uop_lrs2 = _GEN_67[_stq_retry_e_T_1]; // @[util.scala:106:23] wire [5:0] mem_stq_retry_e_out_bits_uop_lrs3 = _GEN_68[_stq_retry_e_T_1]; // @[util.scala:106:23] wire mem_stq_retry_e_out_bits_uop_ldst_val = _GEN_69[_stq_retry_e_T_1]; // @[util.scala:106:23] wire [1:0] mem_stq_retry_e_out_bits_uop_dst_rtype = _GEN_70[_stq_retry_e_T_1]; // @[util.scala:106:23] wire [1:0] mem_stq_retry_e_out_bits_uop_lrs1_rtype = _GEN_71[_stq_retry_e_T_1]; // @[util.scala:106:23] wire [1:0] mem_stq_retry_e_out_bits_uop_lrs2_rtype = _GEN_72[_stq_retry_e_T_1]; // @[util.scala:106:23] wire mem_stq_retry_e_out_bits_uop_frs3_en = _GEN_73[_stq_retry_e_T_1]; // @[util.scala:106:23] wire mem_stq_retry_e_out_bits_uop_fp_val = _GEN_74[_stq_retry_e_T_1]; // @[util.scala:106:23] wire mem_stq_retry_e_out_bits_uop_fp_single = _GEN_75[_stq_retry_e_T_1]; // @[util.scala:106:23] wire mem_stq_retry_e_out_bits_uop_xcpt_pf_if = _GEN_76[_stq_retry_e_T_1]; // @[util.scala:106:23] wire mem_stq_retry_e_out_bits_uop_xcpt_ae_if = _GEN_77[_stq_retry_e_T_1]; // @[util.scala:106:23] wire mem_stq_retry_e_out_bits_uop_xcpt_ma_if = _GEN_78[_stq_retry_e_T_1]; // @[util.scala:106:23] wire mem_stq_retry_e_out_bits_uop_bp_debug_if = _GEN_79[_stq_retry_e_T_1]; // @[util.scala:106:23] wire mem_stq_retry_e_out_bits_uop_bp_xcpt_if = _GEN_80[_stq_retry_e_T_1]; // @[util.scala:106:23] wire [1:0] mem_stq_retry_e_out_bits_uop_debug_fsrc = _GEN_81[_stq_retry_e_T_1]; // @[util.scala:106:23] wire [1:0] mem_stq_retry_e_out_bits_uop_debug_tsrc = _GEN_82[_stq_retry_e_T_1]; // @[util.scala:106:23] wire mem_stq_retry_e_out_bits_addr_valid = _GEN_83[_stq_retry_e_T_1]; // @[util.scala:106:23] wire [39:0] mem_stq_retry_e_out_bits_addr_bits = _GEN_84[_stq_retry_e_T_1]; // @[util.scala:106:23] wire mem_stq_retry_e_out_bits_addr_is_virtual = _GEN_85[_stq_retry_e_T_1]; // @[util.scala:106:23] wire mem_stq_retry_e_out_bits_data_valid = _GEN_86[_stq_retry_e_T_1]; // @[util.scala:106:23] wire [63:0] mem_stq_retry_e_out_bits_data_bits = _GEN_87[_stq_retry_e_T_1]; // @[util.scala:106:23] wire mem_stq_retry_e_out_bits_committed = _GEN_89[_stq_retry_e_T_1]; // @[util.scala:106:23] wire mem_stq_retry_e_out_bits_succeeded = _GEN_184[_stq_retry_e_T_1]; // @[util.scala:106:23] wire [63:0] mem_stq_retry_e_out_bits_debug_wb_data = _GEN_185[_stq_retry_e_T_1]; // @[util.scala:106:23] wire _can_fire_sta_retry_T = _GEN[_stq_retry_e_T_1] & mem_stq_retry_e_out_bits_addr_valid; // @[util.scala:106:23] wire _can_fire_sta_retry_T_1 = _can_fire_sta_retry_T & mem_stq_retry_e_out_bits_addr_is_virtual; // @[util.scala:106:23] wire _can_fire_sta_retry_T_2 = _can_fire_sta_retry_T_1; // @[lsu.scala:478:79, :479:79] reg can_fire_sta_retry_REG; // @[lsu.scala:481:41] wire _can_fire_sta_retry_T_3 = _can_fire_sta_retry_T_2 & can_fire_sta_retry_REG; // @[lsu.scala:479:79, :480:79, :481:41] wire _can_fire_sta_retry_T_8 = _can_fire_sta_retry_T_3; // @[lsu.scala:480:79, :481:79] wire _can_fire_sta_retry_T_5 = stq_incoming_idx_0 == stq_retry_idx; // @[lsu.scala:263:49, :421:30, :484:70] wire can_fire_sta_retry_0 = _can_fire_sta_retry_T_8; // @[lsu.scala:263:49, :481:79] wire _can_fire_store_commit_T = ~_GEN_55; // @[lsu.scala:222:42, :489:33] wire _can_fire_store_commit_T_1 = _GEN_0 & _can_fire_store_commit_T; // @[lsu.scala:222:42, :488:79, :489:33] wire _can_fire_store_commit_T_2 = ~mem_xcpt_valid; // @[lsu.scala:358:29, :490:33] wire _can_fire_store_commit_T_3 = _can_fire_store_commit_T_1 & _can_fire_store_commit_T_2; // @[lsu.scala:488:79, :489:79, :490:33] wire _can_fire_store_commit_T_4 = ~_GEN_48; // @[lsu.scala:222:42, :491:33] wire _can_fire_store_commit_T_5 = _can_fire_store_commit_T_3 & _can_fire_store_commit_T_4; // @[lsu.scala:489:79, :490:79, :491:33] wire _can_fire_store_commit_T_6 = _can_fire_store_commit_T_5; // @[lsu.scala:490:79, :491:79] wire _can_fire_store_commit_T_7 = _GEN_58 & _GEN_83[stq_execute_head]; // @[lsu.scala:218:29, :222:42, :493:101] wire _can_fire_store_commit_T_8 = ~_GEN_85[stq_execute_head]; // @[lsu.scala:218:29, :222:42, :495:66] wire _can_fire_store_commit_T_9 = _can_fire_store_commit_T_7 & _can_fire_store_commit_T_8; // @[lsu.scala:493:101, :494:101, :495:66] wire _can_fire_store_commit_T_10 = _can_fire_store_commit_T_9 & _GEN_86[stq_execute_head]; // @[lsu.scala:218:29, :222:42, :494:101, :495:101] wire _can_fire_store_commit_T_11 = _GEN_89[stq_execute_head] | _can_fire_store_commit_T_10; // @[lsu.scala:218:29, :222:42, :493:62, :495:101] wire _can_fire_store_commit_T_12 = _can_fire_store_commit_T_6 & _can_fire_store_commit_T_11; // @[lsu.scala:491:79, :492:79, :493:62] wire can_fire_store_commit_0 = _can_fire_store_commit_T_12; // @[lsu.scala:263:49, :492:79] wire _will_fire_store_commit_0_will_fire_T_3 = can_fire_store_commit_0; // @[lsu.scala:263:49, :533:32] wire block_load_wakeup; // @[lsu.scala:499:35] wire [6:0] mem_ldq_wakeup_e_out_bits_uop_uopc = _GEN_94[_ldq_wakeup_e_T_1]; // @[util.scala:106:23] wire [31:0] mem_ldq_wakeup_e_out_bits_uop_inst = _GEN_95[_ldq_wakeup_e_T_1]; // @[util.scala:106:23] wire [31:0] mem_ldq_wakeup_e_out_bits_uop_debug_inst = _GEN_96[_ldq_wakeup_e_T_1]; // @[util.scala:106:23] wire mem_ldq_wakeup_e_out_bits_uop_is_rvc = _GEN_97[_ldq_wakeup_e_T_1]; // @[util.scala:106:23] wire [39:0] mem_ldq_wakeup_e_out_bits_uop_debug_pc = _GEN_98[_ldq_wakeup_e_T_1]; // @[util.scala:106:23] wire [2:0] mem_ldq_wakeup_e_out_bits_uop_iq_type = _GEN_99[_ldq_wakeup_e_T_1]; // @[util.scala:106:23] wire [9:0] mem_ldq_wakeup_e_out_bits_uop_fu_code = _GEN_100[_ldq_wakeup_e_T_1]; // @[util.scala:106:23] wire [3:0] mem_ldq_wakeup_e_out_bits_uop_ctrl_br_type = _GEN_101[_ldq_wakeup_e_T_1]; // @[util.scala:106:23] wire [1:0] mem_ldq_wakeup_e_out_bits_uop_ctrl_op1_sel = _GEN_102[_ldq_wakeup_e_T_1]; // @[util.scala:106:23] wire [2:0] mem_ldq_wakeup_e_out_bits_uop_ctrl_op2_sel = _GEN_103[_ldq_wakeup_e_T_1]; // @[util.scala:106:23] wire [2:0] mem_ldq_wakeup_e_out_bits_uop_ctrl_imm_sel = _GEN_104[_ldq_wakeup_e_T_1]; // @[util.scala:106:23] wire [4:0] mem_ldq_wakeup_e_out_bits_uop_ctrl_op_fcn = _GEN_105[_ldq_wakeup_e_T_1]; // @[util.scala:106:23] wire mem_ldq_wakeup_e_out_bits_uop_ctrl_fcn_dw = _GEN_106[_ldq_wakeup_e_T_1]; // @[util.scala:106:23] wire [2:0] mem_ldq_wakeup_e_out_bits_uop_ctrl_csr_cmd = _GEN_107[_ldq_wakeup_e_T_1]; // @[util.scala:106:23] wire mem_ldq_wakeup_e_out_bits_uop_ctrl_is_load = _GEN_108[_ldq_wakeup_e_T_1]; // @[util.scala:106:23] wire mem_ldq_wakeup_e_out_bits_uop_ctrl_is_sta = _GEN_109[_ldq_wakeup_e_T_1]; // @[util.scala:106:23] wire mem_ldq_wakeup_e_out_bits_uop_ctrl_is_std = _GEN_110[_ldq_wakeup_e_T_1]; // @[util.scala:106:23] wire [1:0] mem_ldq_wakeup_e_out_bits_uop_iw_state = _GEN_111[_ldq_wakeup_e_T_1]; // @[util.scala:106:23] wire mem_ldq_wakeup_e_out_bits_uop_iw_p1_poisoned = _GEN_112[_ldq_wakeup_e_T_1]; // @[util.scala:106:23] wire mem_ldq_wakeup_e_out_bits_uop_iw_p2_poisoned = _GEN_113[_ldq_wakeup_e_T_1]; // @[util.scala:106:23] wire mem_ldq_wakeup_e_out_bits_uop_is_br = _GEN_114[_ldq_wakeup_e_T_1]; // @[util.scala:106:23] wire mem_ldq_wakeup_e_out_bits_uop_is_jalr = _GEN_115[_ldq_wakeup_e_T_1]; // @[util.scala:106:23] wire mem_ldq_wakeup_e_out_bits_uop_is_jal = _GEN_116[_ldq_wakeup_e_T_1]; // @[util.scala:106:23] wire mem_ldq_wakeup_e_out_bits_uop_is_sfb = _GEN_117[_ldq_wakeup_e_T_1]; // @[util.scala:106:23] wire [2:0] mem_ldq_wakeup_e_out_bits_uop_br_tag = _GEN_119[_ldq_wakeup_e_T_1]; // @[util.scala:106:23] wire [3:0] mem_ldq_wakeup_e_out_bits_uop_ftq_idx = _GEN_120[_ldq_wakeup_e_T_1]; // @[util.scala:106:23] wire mem_ldq_wakeup_e_out_bits_uop_edge_inst = _GEN_121[_ldq_wakeup_e_T_1]; // @[util.scala:106:23] wire [5:0] mem_ldq_wakeup_e_out_bits_uop_pc_lob = _GEN_122[_ldq_wakeup_e_T_1]; // @[util.scala:106:23] wire mem_ldq_wakeup_e_out_bits_uop_taken = _GEN_123[_ldq_wakeup_e_T_1]; // @[util.scala:106:23] wire [19:0] mem_ldq_wakeup_e_out_bits_uop_imm_packed = _GEN_124[_ldq_wakeup_e_T_1]; // @[util.scala:106:23] wire [11:0] mem_ldq_wakeup_e_out_bits_uop_csr_addr = _GEN_125[_ldq_wakeup_e_T_1]; // @[util.scala:106:23] wire [4:0] mem_ldq_wakeup_e_out_bits_uop_rob_idx = _GEN_126[_ldq_wakeup_e_T_1]; // @[util.scala:106:23] wire [2:0] mem_ldq_wakeup_e_out_bits_uop_ldq_idx = _GEN_127[_ldq_wakeup_e_T_1]; // @[util.scala:106:23] wire [2:0] mem_ldq_wakeup_e_out_bits_uop_stq_idx = _GEN_128[_ldq_wakeup_e_T_1]; // @[util.scala:106:23] wire [1:0] mem_ldq_wakeup_e_out_bits_uop_rxq_idx = _GEN_129[_ldq_wakeup_e_T_1]; // @[util.scala:106:23] wire [5:0] mem_ldq_wakeup_e_out_bits_uop_pdst = _GEN_130[_ldq_wakeup_e_T_1]; // @[util.scala:106:23] wire [5:0] mem_ldq_wakeup_e_out_bits_uop_prs1 = _GEN_131[_ldq_wakeup_e_T_1]; // @[util.scala:106:23] wire [5:0] mem_ldq_wakeup_e_out_bits_uop_prs2 = _GEN_132[_ldq_wakeup_e_T_1]; // @[util.scala:106:23] wire [5:0] mem_ldq_wakeup_e_out_bits_uop_prs3 = _GEN_133[_ldq_wakeup_e_T_1]; // @[util.scala:106:23] wire mem_ldq_wakeup_e_out_bits_uop_prs1_busy = _GEN_134[_ldq_wakeup_e_T_1]; // @[util.scala:106:23] wire mem_ldq_wakeup_e_out_bits_uop_prs2_busy = _GEN_135[_ldq_wakeup_e_T_1]; // @[util.scala:106:23] wire mem_ldq_wakeup_e_out_bits_uop_prs3_busy = _GEN_136[_ldq_wakeup_e_T_1]; // @[util.scala:106:23] wire [5:0] mem_ldq_wakeup_e_out_bits_uop_stale_pdst = _GEN_137[_ldq_wakeup_e_T_1]; // @[util.scala:106:23] wire mem_ldq_wakeup_e_out_bits_uop_exception = _GEN_138[_ldq_wakeup_e_T_1]; // @[util.scala:106:23] wire [63:0] mem_ldq_wakeup_e_out_bits_uop_exc_cause = _GEN_139[_ldq_wakeup_e_T_1]; // @[util.scala:106:23] wire mem_ldq_wakeup_e_out_bits_uop_bypassable = _GEN_140[_ldq_wakeup_e_T_1]; // @[util.scala:106:23] wire [4:0] mem_ldq_wakeup_e_out_bits_uop_mem_cmd = _GEN_141[_ldq_wakeup_e_T_1]; // @[util.scala:106:23] wire [1:0] mem_ldq_wakeup_e_out_bits_uop_mem_size = _GEN_142[_ldq_wakeup_e_T_1]; // @[util.scala:106:23] wire mem_ldq_wakeup_e_out_bits_uop_mem_signed = _GEN_143[_ldq_wakeup_e_T_1]; // @[util.scala:106:23] wire mem_ldq_wakeup_e_out_bits_uop_is_fence = _GEN_144[_ldq_wakeup_e_T_1]; // @[util.scala:106:23] wire mem_ldq_wakeup_e_out_bits_uop_is_fencei = _GEN_145[_ldq_wakeup_e_T_1]; // @[util.scala:106:23] wire mem_ldq_wakeup_e_out_bits_uop_is_amo = _GEN_146[_ldq_wakeup_e_T_1]; // @[util.scala:106:23] wire mem_ldq_wakeup_e_out_bits_uop_uses_ldq = _GEN_147[_ldq_wakeup_e_T_1]; // @[util.scala:106:23] wire mem_ldq_wakeup_e_out_bits_uop_uses_stq = _GEN_148[_ldq_wakeup_e_T_1]; // @[util.scala:106:23] wire mem_ldq_wakeup_e_out_bits_uop_is_sys_pc2epc = _GEN_149[_ldq_wakeup_e_T_1]; // @[util.scala:106:23] wire mem_ldq_wakeup_e_out_bits_uop_is_unique = _GEN_150[_ldq_wakeup_e_T_1]; // @[util.scala:106:23] wire mem_ldq_wakeup_e_out_bits_uop_flush_on_commit = _GEN_151[_ldq_wakeup_e_T_1]; // @[util.scala:106:23] wire mem_ldq_wakeup_e_out_bits_uop_ldst_is_rs1 = _GEN_152[_ldq_wakeup_e_T_1]; // @[util.scala:106:23] wire [5:0] mem_ldq_wakeup_e_out_bits_uop_ldst = _GEN_153[_ldq_wakeup_e_T_1]; // @[util.scala:106:23] wire [5:0] mem_ldq_wakeup_e_out_bits_uop_lrs1 = _GEN_154[_ldq_wakeup_e_T_1]; // @[util.scala:106:23] wire [5:0] mem_ldq_wakeup_e_out_bits_uop_lrs2 = _GEN_155[_ldq_wakeup_e_T_1]; // @[util.scala:106:23] wire [5:0] mem_ldq_wakeup_e_out_bits_uop_lrs3 = _GEN_156[_ldq_wakeup_e_T_1]; // @[util.scala:106:23] wire mem_ldq_wakeup_e_out_bits_uop_ldst_val = _GEN_157[_ldq_wakeup_e_T_1]; // @[util.scala:106:23] wire [1:0] mem_ldq_wakeup_e_out_bits_uop_dst_rtype = _GEN_158[_ldq_wakeup_e_T_1]; // @[util.scala:106:23] wire [1:0] mem_ldq_wakeup_e_out_bits_uop_lrs1_rtype = _GEN_159[_ldq_wakeup_e_T_1]; // @[util.scala:106:23] wire [1:0] mem_ldq_wakeup_e_out_bits_uop_lrs2_rtype = _GEN_160[_ldq_wakeup_e_T_1]; // @[util.scala:106:23] wire mem_ldq_wakeup_e_out_bits_uop_frs3_en = _GEN_161[_ldq_wakeup_e_T_1]; // @[util.scala:106:23] wire mem_ldq_wakeup_e_out_bits_uop_fp_val = _GEN_162[_ldq_wakeup_e_T_1]; // @[util.scala:106:23] wire mem_ldq_wakeup_e_out_bits_uop_fp_single = _GEN_163[_ldq_wakeup_e_T_1]; // @[util.scala:106:23] wire mem_ldq_wakeup_e_out_bits_uop_xcpt_pf_if = _GEN_164[_ldq_wakeup_e_T_1]; // @[util.scala:106:23] wire mem_ldq_wakeup_e_out_bits_uop_xcpt_ae_if = _GEN_165[_ldq_wakeup_e_T_1]; // @[util.scala:106:23] wire mem_ldq_wakeup_e_out_bits_uop_xcpt_ma_if = _GEN_166[_ldq_wakeup_e_T_1]; // @[util.scala:106:23] wire mem_ldq_wakeup_e_out_bits_uop_bp_debug_if = _GEN_167[_ldq_wakeup_e_T_1]; // @[util.scala:106:23] wire mem_ldq_wakeup_e_out_bits_uop_bp_xcpt_if = _GEN_168[_ldq_wakeup_e_T_1]; // @[util.scala:106:23] wire [1:0] mem_ldq_wakeup_e_out_bits_uop_debug_fsrc = _GEN_169[_ldq_wakeup_e_T_1]; // @[util.scala:106:23] wire [1:0] mem_ldq_wakeup_e_out_bits_uop_debug_tsrc = _GEN_170[_ldq_wakeup_e_T_1]; // @[util.scala:106:23] wire mem_ldq_wakeup_e_out_bits_addr_valid = _GEN_171[_ldq_wakeup_e_T_1]; // @[util.scala:106:23] wire [39:0] mem_ldq_wakeup_e_out_bits_addr_bits = _GEN_172[_ldq_wakeup_e_T_1]; // @[util.scala:106:23] wire mem_ldq_wakeup_e_out_bits_addr_is_virtual = _GEN_173[_ldq_wakeup_e_T_1]; // @[util.scala:106:23] wire mem_ldq_wakeup_e_out_bits_addr_is_uncacheable = _GEN_174[_ldq_wakeup_e_T_1]; // @[util.scala:106:23] wire mem_ldq_wakeup_e_out_bits_executed = _GEN_175[_ldq_wakeup_e_T_1]; // @[util.scala:106:23] wire mem_ldq_wakeup_e_out_bits_succeeded = _GEN_176[_ldq_wakeup_e_T_1]; // @[util.scala:106:23] wire mem_ldq_wakeup_e_out_bits_order_fail = _GEN_177[_ldq_wakeup_e_T_1]; // @[util.scala:106:23] wire mem_ldq_wakeup_e_out_bits_observed = _GEN_178[_ldq_wakeup_e_T_1]; // @[util.scala:106:23] wire [7:0] mem_ldq_wakeup_e_out_bits_st_dep_mask = _GEN_179[_ldq_wakeup_e_T_1]; // @[util.scala:106:23] wire [2:0] mem_ldq_wakeup_e_out_bits_youngest_stq_idx = _GEN_180[_ldq_wakeup_e_T_1]; // @[util.scala:106:23] wire mem_ldq_wakeup_e_out_bits_forward_std_val = _GEN_181[_ldq_wakeup_e_T_1]; // @[util.scala:106:23] wire [2:0] mem_ldq_wakeup_e_out_bits_forward_stq_idx = _GEN_182[_ldq_wakeup_e_T_1]; // @[util.scala:106:23] wire [63:0] mem_ldq_wakeup_e_out_bits_debug_wb_data = _GEN_183[_ldq_wakeup_e_T_1]; // @[util.scala:106:23] wire _can_fire_load_wakeup_T = _GEN_92[_ldq_wakeup_e_T_1] & mem_ldq_wakeup_e_out_bits_addr_valid; // @[util.scala:106:23] wire _can_fire_load_wakeup_T_1 = ~mem_ldq_wakeup_e_out_bits_succeeded; // @[util.scala:106:23] wire _can_fire_load_wakeup_T_2 = _can_fire_load_wakeup_T & _can_fire_load_wakeup_T_1; // @[lsu.scala:501:88, :502:88, :503:31] wire _can_fire_load_wakeup_T_3 = ~mem_ldq_wakeup_e_out_bits_addr_is_virtual; // @[util.scala:106:23] wire _can_fire_load_wakeup_T_4 = _can_fire_load_wakeup_T_2 & _can_fire_load_wakeup_T_3; // @[lsu.scala:502:88, :503:88, :504:31] wire _can_fire_load_wakeup_T_5 = ~mem_ldq_wakeup_e_out_bits_executed; // @[util.scala:106:23] wire _can_fire_load_wakeup_T_6 = _can_fire_load_wakeup_T_4 & _can_fire_load_wakeup_T_5; // @[lsu.scala:503:88, :504:88, :505:31] wire _can_fire_load_wakeup_T_7 = ~mem_ldq_wakeup_e_out_bits_order_fail; // @[util.scala:106:23] wire _can_fire_load_wakeup_T_8 = _can_fire_load_wakeup_T_6 & _can_fire_load_wakeup_T_7; // @[lsu.scala:504:88, :505:88, :506:31] wire [2:0] _can_fire_load_wakeup_T_10 = _can_fire_load_wakeup_T_9; wire _can_fire_load_wakeup_T_11 = ~_GEN_201[_can_fire_load_wakeup_T_10]; // @[lsu.scala:467:33, :507:31] wire _can_fire_load_wakeup_T_12 = _can_fire_load_wakeup_T_8 & _can_fire_load_wakeup_T_11; // @[lsu.scala:505:88, :506:88, :507:31] wire [2:0] _can_fire_load_wakeup_T_14 = _can_fire_load_wakeup_T_13; wire _can_fire_load_wakeup_T_15 = ~_GEN_202[_can_fire_load_wakeup_T_14]; // @[lsu.scala:468:33, :508:31] wire _can_fire_load_wakeup_T_16 = _can_fire_load_wakeup_T_12 & _can_fire_load_wakeup_T_15; // @[lsu.scala:506:88, :507:88, :508:31] wire _can_fire_load_wakeup_T_17 = ~store_needs_order; // @[lsu.scala:406:35, :470:33, :509:31] wire _can_fire_load_wakeup_T_18 = _can_fire_load_wakeup_T_16 & _can_fire_load_wakeup_T_17; // @[lsu.scala:507:88, :508:88, :509:31] wire _can_fire_load_wakeup_T_19 = ~block_load_wakeup; // @[lsu.scala:499:35, :510:31] wire _can_fire_load_wakeup_T_20 = _can_fire_load_wakeup_T_18 & _can_fire_load_wakeup_T_19; // @[lsu.scala:508:88, :509:88, :510:31] wire _can_fire_load_wakeup_T_21 = _can_fire_load_wakeup_T_20; // @[lsu.scala:509:88, :510:88] wire _can_fire_load_wakeup_T_22 = ~mem_ldq_wakeup_e_out_bits_addr_is_uncacheable; // @[util.scala:106:23] wire _can_fire_load_wakeup_T_23 = ldq_head == ldq_wakeup_idx; // @[lsu.scala:213:29, :429:31, :513:84] wire _can_fire_load_wakeup_T_24 = io_core_commit_load_at_rob_head_0 & _can_fire_load_wakeup_T_23; // @[lsu.scala:201:7, :512:107, :513:84] wire _can_fire_load_wakeup_T_25 = mem_ldq_wakeup_e_out_bits_st_dep_mask == 8'h0; // @[util.scala:106:23] wire _can_fire_load_wakeup_T_26 = _can_fire_load_wakeup_T_24 & _can_fire_load_wakeup_T_25; // @[lsu.scala:512:107, :513:103, :514:112] wire _can_fire_load_wakeup_T_27 = _can_fire_load_wakeup_T_22 | _can_fire_load_wakeup_T_26; // @[lsu.scala:512:{32,71}, :513:103] wire _can_fire_load_wakeup_T_28 = _can_fire_load_wakeup_T_21 & _can_fire_load_wakeup_T_27; // @[lsu.scala:510:88, :511:88, :512:71] wire can_fire_load_wakeup_0 = _can_fire_load_wakeup_T_28; // @[lsu.scala:263:49, :511:88] wire _will_fire_load_wakeup_0_will_fire_T_3 = can_fire_load_wakeup_0; // @[lsu.scala:263:49, :533:32] wire can_fire_hella_incoming_0; // @[lsu.scala:517:42] wire can_fire_hella_wakeup_0; // @[lsu.scala:520:42] wire _will_fire_hella_wakeup_0_will_fire_T_3 = can_fire_hella_wakeup_0; // @[lsu.scala:520:42, :533:32] wire _exe_tlb_valid_0_T; // @[lsu.scala:575:25] wire exe_tlb_valid_0; // @[lsu.scala:525:27] wire _will_fire_load_incoming_0_will_fire_T_7 = _will_fire_load_incoming_0_will_fire_T_3; // @[lsu.scala:533:{32,63}] wire _will_fire_load_incoming_0_will_fire_T_11 = _will_fire_load_incoming_0_will_fire_T_7; // @[lsu.scala:533:63, :534:65] assign will_fire_load_incoming_0_will_fire = _will_fire_load_incoming_0_will_fire_T_11; // @[lsu.scala:534:65, :535:61] assign will_fire_load_incoming_0 = will_fire_load_incoming_0_will_fire; // @[lsu.scala:370:38, :535:61] wire _will_fire_load_incoming_0_T = will_fire_load_incoming_0_will_fire; // @[lsu.scala:535:61, :537:46] wire _will_fire_load_incoming_0_T_3 = will_fire_load_incoming_0_will_fire; // @[lsu.scala:535:61, :538:46] wire _will_fire_load_incoming_0_T_6 = will_fire_load_incoming_0_will_fire; // @[lsu.scala:535:61, :539:46] wire _will_fire_load_incoming_0_T_1 = ~_will_fire_load_incoming_0_T; // @[lsu.scala:537:{34,46}] wire _will_fire_load_incoming_0_T_2 = _will_fire_load_incoming_0_T_1; // @[lsu.scala:537:{31,34}] wire _will_fire_load_incoming_0_T_4 = ~_will_fire_load_incoming_0_T_3; // @[lsu.scala:538:{34,46}] wire _will_fire_load_incoming_0_T_5 = _will_fire_load_incoming_0_T_4; // @[lsu.scala:538:{31,34}] wire _will_fire_load_incoming_0_T_7 = ~_will_fire_load_incoming_0_T_6; // @[lsu.scala:539:{34,46}] wire _will_fire_load_incoming_0_T_8 = _will_fire_load_incoming_0_T_7; // @[lsu.scala:539:{31,34}] wire _will_fire_stad_incoming_0_T_8 = _will_fire_load_incoming_0_T_8; // @[lsu.scala:539:31] wire _will_fire_stad_incoming_0_will_fire_T = ~_will_fire_load_incoming_0_T_2; // @[lsu.scala:533:51, :537:31] wire _will_fire_stad_incoming_0_will_fire_T_1 = _will_fire_stad_incoming_0_will_fire_T; // @[lsu.scala:533:{48,51}] wire _will_fire_stad_incoming_0_will_fire_T_2 = ~_will_fire_stad_incoming_0_will_fire_T_1; // @[lsu.scala:533:{35,48}] wire _will_fire_stad_incoming_0_will_fire_T_3 = can_fire_stad_incoming_0 & _will_fire_stad_incoming_0_will_fire_T_2; // @[lsu.scala:263:49, :533:{32,35}] wire _will_fire_stad_incoming_0_will_fire_T_4 = ~_will_fire_load_incoming_0_T_5; // @[lsu.scala:534:52, :538:31] wire _will_fire_stad_incoming_0_will_fire_T_5 = _will_fire_stad_incoming_0_will_fire_T_4; // @[lsu.scala:534:{49,52}] wire _will_fire_stad_incoming_0_will_fire_T_6 = ~_will_fire_stad_incoming_0_will_fire_T_5; // @[lsu.scala:534:{35,49}] wire _will_fire_stad_incoming_0_will_fire_T_7 = _will_fire_stad_incoming_0_will_fire_T_3 & _will_fire_stad_incoming_0_will_fire_T_6; // @[lsu.scala:533:{32,63}, :534:35] wire _will_fire_stad_incoming_0_will_fire_T_11 = _will_fire_stad_incoming_0_will_fire_T_7; // @[lsu.scala:533:63, :534:65] wire _will_fire_stad_incoming_0_will_fire_T_8 = ~_will_fire_load_incoming_0_T_8; // @[lsu.scala:535:50, :539:31] assign will_fire_stad_incoming_0_will_fire = _will_fire_stad_incoming_0_will_fire_T_11; // @[lsu.scala:534:65, :535:61] assign will_fire_stad_incoming_0 = will_fire_stad_incoming_0_will_fire; // @[lsu.scala:371:38, :535:61] wire _will_fire_stad_incoming_0_T = will_fire_stad_incoming_0_will_fire; // @[lsu.scala:535:61, :537:46] wire _will_fire_stad_incoming_0_T_3 = will_fire_stad_incoming_0_will_fire; // @[lsu.scala:535:61, :538:46] wire _will_fire_stad_incoming_0_T_9 = will_fire_stad_incoming_0_will_fire; // @[lsu.scala:535:61, :540:46] wire _will_fire_stad_incoming_0_T_1 = ~_will_fire_stad_incoming_0_T; // @[lsu.scala:537:{34,46}] wire _will_fire_stad_incoming_0_T_2 = _will_fire_load_incoming_0_T_2 & _will_fire_stad_incoming_0_T_1; // @[lsu.scala:537:{31,34}] wire _will_fire_stad_incoming_0_T_4 = ~_will_fire_stad_incoming_0_T_3; // @[lsu.scala:538:{34,46}] wire _will_fire_stad_incoming_0_T_5 = _will_fire_load_incoming_0_T_5 & _will_fire_stad_incoming_0_T_4; // @[lsu.scala:538:{31,34}] wire _will_fire_sta_incoming_0_T_8 = _will_fire_stad_incoming_0_T_8; // @[lsu.scala:539:31] wire _will_fire_stad_incoming_0_T_10 = ~_will_fire_stad_incoming_0_T_9; // @[lsu.scala:540:{34,46}] wire _will_fire_stad_incoming_0_T_11 = _will_fire_stad_incoming_0_T_10; // @[lsu.scala:540:{31,34}] wire _will_fire_sta_incoming_0_will_fire_T = ~_will_fire_stad_incoming_0_T_2; // @[lsu.scala:533:51, :537:31] wire _will_fire_sta_incoming_0_will_fire_T_1 = _will_fire_sta_incoming_0_will_fire_T; // @[lsu.scala:533:{48,51}] wire _will_fire_sta_incoming_0_will_fire_T_2 = ~_will_fire_sta_incoming_0_will_fire_T_1; // @[lsu.scala:533:{35,48}] wire _will_fire_sta_incoming_0_will_fire_T_3 = can_fire_sta_incoming_0 & _will_fire_sta_incoming_0_will_fire_T_2; // @[lsu.scala:263:49, :533:{32,35}] wire _will_fire_sta_incoming_0_will_fire_T_4 = ~_will_fire_stad_incoming_0_T_5; // @[lsu.scala:534:52, :538:31] wire _will_fire_sta_incoming_0_will_fire_T_5 = _will_fire_sta_incoming_0_will_fire_T_4; // @[lsu.scala:534:{49,52}] wire _will_fire_sta_incoming_0_will_fire_T_6 = ~_will_fire_sta_incoming_0_will_fire_T_5; // @[lsu.scala:534:{35,49}] wire _will_fire_sta_incoming_0_will_fire_T_7 = _will_fire_sta_incoming_0_will_fire_T_3 & _will_fire_sta_incoming_0_will_fire_T_6; // @[lsu.scala:533:{32,63}, :534:35] wire _will_fire_sta_incoming_0_will_fire_T_11 = _will_fire_sta_incoming_0_will_fire_T_7; // @[lsu.scala:533:63, :534:65] wire _will_fire_sta_incoming_0_will_fire_T_8 = ~_will_fire_stad_incoming_0_T_8; // @[lsu.scala:535:50, :539:31] wire _will_fire_sta_incoming_0_will_fire_T_12 = ~_will_fire_stad_incoming_0_T_11; // @[lsu.scala:536:51, :540:31] wire _will_fire_sta_incoming_0_will_fire_T_13 = _will_fire_sta_incoming_0_will_fire_T_12; // @[lsu.scala:536:{48,51}] wire _will_fire_sta_incoming_0_will_fire_T_14 = ~_will_fire_sta_incoming_0_will_fire_T_13; // @[lsu.scala:536:{35,48}] assign will_fire_sta_incoming_0_will_fire = _will_fire_sta_incoming_0_will_fire_T_11 & _will_fire_sta_incoming_0_will_fire_T_14; // @[lsu.scala:534:65, :535:61, :536:35] assign will_fire_sta_incoming_0 = will_fire_sta_incoming_0_will_fire; // @[lsu.scala:372:38, :535:61] wire _will_fire_sta_incoming_0_T = will_fire_sta_incoming_0_will_fire; // @[lsu.scala:535:61, :537:46] wire _will_fire_sta_incoming_0_T_3 = will_fire_sta_incoming_0_will_fire; // @[lsu.scala:535:61, :538:46] wire _will_fire_sta_incoming_0_T_9 = will_fire_sta_incoming_0_will_fire; // @[lsu.scala:535:61, :540:46] wire _will_fire_sta_incoming_0_T_1 = ~_will_fire_sta_incoming_0_T; // @[lsu.scala:537:{34,46}] wire _will_fire_sta_incoming_0_T_2 = _will_fire_stad_incoming_0_T_2 & _will_fire_sta_incoming_0_T_1; // @[lsu.scala:537:{31,34}] wire _will_fire_std_incoming_0_T_2 = _will_fire_sta_incoming_0_T_2; // @[lsu.scala:537:31] wire _will_fire_sta_incoming_0_T_4 = ~_will_fire_sta_incoming_0_T_3; // @[lsu.scala:538:{34,46}] wire _will_fire_sta_incoming_0_T_5 = _will_fire_stad_incoming_0_T_5 & _will_fire_sta_incoming_0_T_4; // @[lsu.scala:538:{31,34}] wire _will_fire_std_incoming_0_T_5 = _will_fire_sta_incoming_0_T_5; // @[lsu.scala:538:31] wire _will_fire_std_incoming_0_T_8 = _will_fire_sta_incoming_0_T_8; // @[lsu.scala:539:31] wire _will_fire_sta_incoming_0_T_10 = ~_will_fire_sta_incoming_0_T_9; // @[lsu.scala:540:{34,46}] wire _will_fire_sta_incoming_0_T_11 = _will_fire_stad_incoming_0_T_11 & _will_fire_sta_incoming_0_T_10; // @[lsu.scala:540:{31,34}] wire _will_fire_std_incoming_0_will_fire_T = ~_will_fire_sta_incoming_0_T_2; // @[lsu.scala:533:51, :537:31] wire _will_fire_std_incoming_0_will_fire_T_7 = _will_fire_std_incoming_0_will_fire_T_3; // @[lsu.scala:533:{32,63}] wire _will_fire_std_incoming_0_will_fire_T_4 = ~_will_fire_sta_incoming_0_T_5; // @[lsu.scala:534:52, :538:31] wire _will_fire_std_incoming_0_will_fire_T_11 = _will_fire_std_incoming_0_will_fire_T_7; // @[lsu.scala:533:63, :534:65] wire _will_fire_std_incoming_0_will_fire_T_8 = ~_will_fire_sta_incoming_0_T_8; // @[lsu.scala:535:50, :539:31] wire _will_fire_std_incoming_0_will_fire_T_12 = ~_will_fire_sta_incoming_0_T_11; // @[lsu.scala:536:51, :540:31] wire _will_fire_std_incoming_0_will_fire_T_13 = _will_fire_std_incoming_0_will_fire_T_12; // @[lsu.scala:536:{48,51}] wire _will_fire_std_incoming_0_will_fire_T_14 = ~_will_fire_std_incoming_0_will_fire_T_13; // @[lsu.scala:536:{35,48}] assign will_fire_std_incoming_0_will_fire = _will_fire_std_incoming_0_will_fire_T_11 & _will_fire_std_incoming_0_will_fire_T_14; // @[lsu.scala:534:65, :535:61, :536:35] assign will_fire_std_incoming_0 = will_fire_std_incoming_0_will_fire; // @[lsu.scala:373:38, :535:61] wire _will_fire_std_incoming_0_T_9 = will_fire_std_incoming_0_will_fire; // @[lsu.scala:535:61, :540:46] wire _will_fire_sfence_0_T_5 = _will_fire_std_incoming_0_T_5; // @[lsu.scala:538:31] wire _will_fire_sfence_0_T_8 = _will_fire_std_incoming_0_T_8; // @[lsu.scala:539:31] wire _will_fire_std_incoming_0_T_10 = ~_will_fire_std_incoming_0_T_9; // @[lsu.scala:540:{34,46}] wire _will_fire_std_incoming_0_T_11 = _will_fire_sta_incoming_0_T_11 & _will_fire_std_incoming_0_T_10; // @[lsu.scala:540:{31,34}] wire _will_fire_sfence_0_will_fire_T = ~_will_fire_std_incoming_0_T_2; // @[lsu.scala:533:51, :537:31] wire _will_fire_sfence_0_will_fire_T_1 = _will_fire_sfence_0_will_fire_T; // @[lsu.scala:533:{48,51}] wire _will_fire_sfence_0_will_fire_T_2 = ~_will_fire_sfence_0_will_fire_T_1; // @[lsu.scala:533:{35,48}] wire _will_fire_sfence_0_will_fire_T_3 = can_fire_sfence_0 & _will_fire_sfence_0_will_fire_T_2; // @[lsu.scala:263:49, :533:{32,35}] wire _will_fire_sfence_0_will_fire_T_7 = _will_fire_sfence_0_will_fire_T_3; // @[lsu.scala:533:{32,63}] wire _will_fire_sfence_0_will_fire_T_4 = ~_will_fire_std_incoming_0_T_5; // @[lsu.scala:534:52, :538:31] wire _will_fire_sfence_0_will_fire_T_11 = _will_fire_sfence_0_will_fire_T_7; // @[lsu.scala:533:63, :534:65] wire _will_fire_sfence_0_will_fire_T_8 = ~_will_fire_std_incoming_0_T_8; // @[lsu.scala:535:50, :539:31] wire _will_fire_sfence_0_will_fire_T_12 = ~_will_fire_std_incoming_0_T_11; // @[lsu.scala:536:51, :540:31] wire _will_fire_sfence_0_will_fire_T_13 = _will_fire_sfence_0_will_fire_T_12; // @[lsu.scala:536:{48,51}] wire _will_fire_sfence_0_will_fire_T_14 = ~_will_fire_sfence_0_will_fire_T_13; // @[lsu.scala:536:{35,48}] assign will_fire_sfence_0_will_fire = _will_fire_sfence_0_will_fire_T_11 & _will_fire_sfence_0_will_fire_T_14; // @[lsu.scala:534:65, :535:61, :536:35] assign will_fire_sfence_0 = will_fire_sfence_0_will_fire; // @[lsu.scala:374:38, :535:61] wire _will_fire_sfence_0_T = will_fire_sfence_0_will_fire; // @[lsu.scala:535:61, :537:46] wire _will_fire_sfence_0_T_9 = will_fire_sfence_0_will_fire; // @[lsu.scala:535:61, :540:46] wire _will_fire_sfence_0_T_1 = ~_will_fire_sfence_0_T; // @[lsu.scala:537:{34,46}] wire _will_fire_sfence_0_T_2 = _will_fire_std_incoming_0_T_2 & _will_fire_sfence_0_T_1; // @[lsu.scala:537:{31,34}] wire _will_fire_release_0_T_2 = _will_fire_sfence_0_T_2; // @[lsu.scala:537:31] wire _will_fire_release_0_T_8 = _will_fire_sfence_0_T_8; // @[lsu.scala:539:31] wire _will_fire_sfence_0_T_10 = ~_will_fire_sfence_0_T_9; // @[lsu.scala:540:{34,46}] wire _will_fire_sfence_0_T_11 = _will_fire_std_incoming_0_T_11 & _will_fire_sfence_0_T_10; // @[lsu.scala:540:{31,34}] wire _will_fire_release_0_T_11 = _will_fire_sfence_0_T_11; // @[lsu.scala:540:31] wire _will_fire_release_0_will_fire_T = ~_will_fire_sfence_0_T_2; // @[lsu.scala:533:51, :537:31] wire _will_fire_release_0_will_fire_T_4 = ~_will_fire_sfence_0_T_5; // @[lsu.scala:534:52, :538:31] wire _will_fire_release_0_will_fire_T_5 = _will_fire_release_0_will_fire_T_4; // @[lsu.scala:534:{49,52}] wire _will_fire_release_0_will_fire_T_6 = ~_will_fire_release_0_will_fire_T_5; // @[lsu.scala:534:{35,49}] wire _will_fire_release_0_will_fire_T_7 = _will_fire_release_0_will_fire_T_3 & _will_fire_release_0_will_fire_T_6; // @[lsu.scala:533:{32,63}, :534:35] wire _will_fire_release_0_will_fire_T_11 = _will_fire_release_0_will_fire_T_7; // @[lsu.scala:533:63, :534:65] wire _will_fire_release_0_will_fire_T_8 = ~_will_fire_sfence_0_T_8; // @[lsu.scala:535:50, :539:31] assign will_fire_release_0_will_fire = _will_fire_release_0_will_fire_T_11; // @[lsu.scala:534:65, :535:61] wire _will_fire_release_0_will_fire_T_12 = ~_will_fire_sfence_0_T_11; // @[lsu.scala:536:51, :540:31] assign will_fire_release_0 = will_fire_release_0_will_fire; // @[lsu.scala:377:38, :535:61] wire _will_fire_release_0_T_3 = will_fire_release_0_will_fire; // @[lsu.scala:535:61, :538:46] wire _will_fire_release_0_T_4 = ~_will_fire_release_0_T_3; // @[lsu.scala:538:{34,46}] wire _will_fire_release_0_T_5 = _will_fire_sfence_0_T_5 & _will_fire_release_0_T_4; // @[lsu.scala:538:{31,34}] wire _will_fire_hella_incoming_0_T_5 = _will_fire_release_0_T_5; // @[lsu.scala:538:31] wire _will_fire_hella_incoming_0_T_11 = _will_fire_release_0_T_11; // @[lsu.scala:540:31] wire _will_fire_hella_incoming_0_will_fire_T = ~_will_fire_release_0_T_2; // @[lsu.scala:533:51, :537:31] wire _will_fire_hella_incoming_0_will_fire_T_1 = _will_fire_hella_incoming_0_will_fire_T; // @[lsu.scala:533:{48,51}] wire _will_fire_hella_incoming_0_will_fire_T_2 = ~_will_fire_hella_incoming_0_will_fire_T_1; // @[lsu.scala:533:{35,48}] wire _will_fire_hella_incoming_0_will_fire_T_3 = can_fire_hella_incoming_0 & _will_fire_hella_incoming_0_will_fire_T_2; // @[lsu.scala:517:42, :533:{32,35}] wire _will_fire_hella_incoming_0_will_fire_T_7 = _will_fire_hella_incoming_0_will_fire_T_3; // @[lsu.scala:533:{32,63}] wire _will_fire_hella_incoming_0_will_fire_T_4 = ~_will_fire_release_0_T_5; // @[lsu.scala:534:52, :538:31] wire _will_fire_hella_incoming_0_will_fire_T_8 = ~_will_fire_release_0_T_8; // @[lsu.scala:535:50, :539:31] wire _will_fire_hella_incoming_0_will_fire_T_9 = _will_fire_hella_incoming_0_will_fire_T_8; // @[lsu.scala:535:{47,50}] wire _will_fire_hella_incoming_0_will_fire_T_10 = ~_will_fire_hella_incoming_0_will_fire_T_9; // @[lsu.scala:535:{35,47}] wire _will_fire_hella_incoming_0_will_fire_T_11 = _will_fire_hella_incoming_0_will_fire_T_7 & _will_fire_hella_incoming_0_will_fire_T_10; // @[lsu.scala:533:63, :534:65, :535:35] assign will_fire_hella_incoming_0_will_fire = _will_fire_hella_incoming_0_will_fire_T_11; // @[lsu.scala:534:65, :535:61] wire _will_fire_hella_incoming_0_will_fire_T_12 = ~_will_fire_release_0_T_11; // @[lsu.scala:536:51, :540:31] assign will_fire_hella_incoming_0 = will_fire_hella_incoming_0_will_fire; // @[lsu.scala:375:38, :535:61] wire _will_fire_hella_incoming_0_T = will_fire_hella_incoming_0_will_fire; // @[lsu.scala:535:61, :537:46] wire _will_fire_hella_incoming_0_T_6 = will_fire_hella_incoming_0_will_fire; // @[lsu.scala:535:61, :539:46] wire _will_fire_hella_incoming_0_T_1 = ~_will_fire_hella_incoming_0_T; // @[lsu.scala:537:{34,46}] wire _will_fire_hella_incoming_0_T_2 = _will_fire_release_0_T_2 & _will_fire_hella_incoming_0_T_1; // @[lsu.scala:537:{31,34}] wire _will_fire_hella_wakeup_0_T_2 = _will_fire_hella_incoming_0_T_2; // @[lsu.scala:537:31] wire _will_fire_hella_wakeup_0_T_5 = _will_fire_hella_incoming_0_T_5; // @[lsu.scala:538:31] wire _will_fire_hella_incoming_0_T_7 = ~_will_fire_hella_incoming_0_T_6; // @[lsu.scala:539:{34,46}] wire _will_fire_hella_incoming_0_T_8 = _will_fire_release_0_T_8 & _will_fire_hella_incoming_0_T_7; // @[lsu.scala:539:{31,34}] wire _will_fire_hella_wakeup_0_T_11 = _will_fire_hella_incoming_0_T_11; // @[lsu.scala:540:31] wire _will_fire_hella_wakeup_0_will_fire_T = ~_will_fire_hella_incoming_0_T_2; // @[lsu.scala:533:51, :537:31] wire _will_fire_hella_wakeup_0_will_fire_T_7 = _will_fire_hella_wakeup_0_will_fire_T_3; // @[lsu.scala:533:{32,63}] wire _will_fire_hella_wakeup_0_will_fire_T_4 = ~_will_fire_hella_incoming_0_T_5; // @[lsu.scala:534:52, :538:31] wire _will_fire_hella_wakeup_0_will_fire_T_8 = ~_will_fire_hella_incoming_0_T_8; // @[lsu.scala:535:50, :539:31] wire _will_fire_hella_wakeup_0_will_fire_T_9 = _will_fire_hella_wakeup_0_will_fire_T_8; // @[lsu.scala:535:{47,50}] wire _will_fire_hella_wakeup_0_will_fire_T_10 = ~_will_fire_hella_wakeup_0_will_fire_T_9; // @[lsu.scala:535:{35,47}] wire _will_fire_hella_wakeup_0_will_fire_T_11 = _will_fire_hella_wakeup_0_will_fire_T_7 & _will_fire_hella_wakeup_0_will_fire_T_10; // @[lsu.scala:533:63, :534:65, :535:35] assign will_fire_hella_wakeup_0_will_fire = _will_fire_hella_wakeup_0_will_fire_T_11; // @[lsu.scala:534:65, :535:61] wire _will_fire_hella_wakeup_0_will_fire_T_12 = ~_will_fire_hella_incoming_0_T_11; // @[lsu.scala:536:51, :540:31] assign will_fire_hella_wakeup_0 = will_fire_hella_wakeup_0_will_fire; // @[lsu.scala:376:38, :535:61] wire _will_fire_hella_wakeup_0_T_6 = will_fire_hella_wakeup_0_will_fire; // @[lsu.scala:535:61, :539:46] wire _will_fire_hella_wakeup_0_T_7 = ~_will_fire_hella_wakeup_0_T_6; // @[lsu.scala:539:{34,46}] wire _will_fire_hella_wakeup_0_T_8 = _will_fire_hella_incoming_0_T_8 & _will_fire_hella_wakeup_0_T_7; // @[lsu.scala:539:{31,34}] wire _will_fire_load_retry_0_T_11 = _will_fire_hella_wakeup_0_T_11; // @[lsu.scala:540:31] wire _will_fire_load_retry_0_will_fire_T = ~_will_fire_hella_wakeup_0_T_2; // @[lsu.scala:533:51, :537:31] wire _will_fire_load_retry_0_will_fire_T_1 = _will_fire_load_retry_0_will_fire_T; // @[lsu.scala:533:{48,51}] wire _will_fire_load_retry_0_will_fire_T_2 = ~_will_fire_load_retry_0_will_fire_T_1; // @[lsu.scala:533:{35,48}] wire _will_fire_load_retry_0_will_fire_T_3 = can_fire_load_retry_0 & _will_fire_load_retry_0_will_fire_T_2; // @[lsu.scala:263:49, :533:{32,35}] wire _will_fire_load_retry_0_will_fire_T_4 = ~_will_fire_hella_wakeup_0_T_5; // @[lsu.scala:534:52, :538:31] wire _will_fire_load_retry_0_will_fire_T_5 = _will_fire_load_retry_0_will_fire_T_4; // @[lsu.scala:534:{49,52}] wire _will_fire_load_retry_0_will_fire_T_6 = ~_will_fire_load_retry_0_will_fire_T_5; // @[lsu.scala:534:{35,49}] wire _will_fire_load_retry_0_will_fire_T_7 = _will_fire_load_retry_0_will_fire_T_3 & _will_fire_load_retry_0_will_fire_T_6; // @[lsu.scala:533:{32,63}, :534:35] wire _will_fire_load_retry_0_will_fire_T_8 = ~_will_fire_hella_wakeup_0_T_8; // @[lsu.scala:535:50, :539:31] wire _will_fire_load_retry_0_will_fire_T_9 = _will_fire_load_retry_0_will_fire_T_8; // @[lsu.scala:535:{47,50}] wire _will_fire_load_retry_0_will_fire_T_10 = ~_will_fire_load_retry_0_will_fire_T_9; // @[lsu.scala:535:{35,47}] wire _will_fire_load_retry_0_will_fire_T_11 = _will_fire_load_retry_0_will_fire_T_7 & _will_fire_load_retry_0_will_fire_T_10; // @[lsu.scala:533:63, :534:65, :535:35] assign will_fire_load_retry_0_will_fire = _will_fire_load_retry_0_will_fire_T_11; // @[lsu.scala:534:65, :535:61] wire _will_fire_load_retry_0_will_fire_T_12 = ~_will_fire_hella_wakeup_0_T_11; // @[lsu.scala:536:51, :540:31] assign will_fire_load_retry_0 = will_fire_load_retry_0_will_fire; // @[lsu.scala:378:38, :535:61] wire _will_fire_load_retry_0_T = will_fire_load_retry_0_will_fire; // @[lsu.scala:535:61, :537:46] wire _will_fire_load_retry_0_T_3 = will_fire_load_retry_0_will_fire; // @[lsu.scala:535:61, :538:46] wire _will_fire_load_retry_0_T_6 = will_fire_load_retry_0_will_fire; // @[lsu.scala:535:61, :539:46] wire _will_fire_load_retry_0_T_1 = ~_will_fire_load_retry_0_T; // @[lsu.scala:537:{34,46}] wire _will_fire_load_retry_0_T_2 = _will_fire_hella_wakeup_0_T_2 & _will_fire_load_retry_0_T_1; // @[lsu.scala:537:{31,34}] wire _will_fire_load_retry_0_T_4 = ~_will_fire_load_retry_0_T_3; // @[lsu.scala:538:{34,46}] wire _will_fire_load_retry_0_T_5 = _will_fire_hella_wakeup_0_T_5 & _will_fire_load_retry_0_T_4; // @[lsu.scala:538:{31,34}] wire _will_fire_load_retry_0_T_7 = ~_will_fire_load_retry_0_T_6; // @[lsu.scala:539:{34,46}] wire _will_fire_load_retry_0_T_8 = _will_fire_hella_wakeup_0_T_8 & _will_fire_load_retry_0_T_7; // @[lsu.scala:539:{31,34}] wire _will_fire_sta_retry_0_T_8 = _will_fire_load_retry_0_T_8; // @[lsu.scala:539:31] wire _will_fire_sta_retry_0_will_fire_T = ~_will_fire_load_retry_0_T_2; // @[lsu.scala:533:51, :537:31] wire _will_fire_sta_retry_0_will_fire_T_1 = _will_fire_sta_retry_0_will_fire_T; // @[lsu.scala:533:{48,51}] wire _will_fire_sta_retry_0_will_fire_T_2 = ~_will_fire_sta_retry_0_will_fire_T_1; // @[lsu.scala:533:{35,48}] wire _will_fire_sta_retry_0_will_fire_T_3 = can_fire_sta_retry_0 & _will_fire_sta_retry_0_will_fire_T_2; // @[lsu.scala:263:49, :533:{32,35}] wire _will_fire_sta_retry_0_will_fire_T_4 = ~_will_fire_load_retry_0_T_5; // @[lsu.scala:534:52, :538:31] wire _will_fire_sta_retry_0_will_fire_T_5 = _will_fire_sta_retry_0_will_fire_T_4; // @[lsu.scala:534:{49,52}] wire _will_fire_sta_retry_0_will_fire_T_6 = ~_will_fire_sta_retry_0_will_fire_T_5; // @[lsu.scala:534:{35,49}] wire _will_fire_sta_retry_0_will_fire_T_7 = _will_fire_sta_retry_0_will_fire_T_3 & _will_fire_sta_retry_0_will_fire_T_6; // @[lsu.scala:533:{32,63}, :534:35] wire _will_fire_sta_retry_0_will_fire_T_11 = _will_fire_sta_retry_0_will_fire_T_7; // @[lsu.scala:533:63, :534:65] wire _will_fire_sta_retry_0_will_fire_T_8 = ~_will_fire_load_retry_0_T_8; // @[lsu.scala:535:50, :539:31] wire _will_fire_sta_retry_0_will_fire_T_12 = ~_will_fire_load_retry_0_T_11; // @[lsu.scala:536:51, :540:31] wire _will_fire_sta_retry_0_will_fire_T_13 = _will_fire_sta_retry_0_will_fire_T_12; // @[lsu.scala:536:{48,51}] wire _will_fire_sta_retry_0_will_fire_T_14 = ~_will_fire_sta_retry_0_will_fire_T_13; // @[lsu.scala:536:{35,48}] assign will_fire_sta_retry_0_will_fire = _will_fire_sta_retry_0_will_fire_T_11 & _will_fire_sta_retry_0_will_fire_T_14; // @[lsu.scala:534:65, :535:61, :536:35] assign will_fire_sta_retry_0 = will_fire_sta_retry_0_will_fire; // @[lsu.scala:379:38, :535:61] wire _will_fire_sta_retry_0_T = will_fire_sta_retry_0_will_fire; // @[lsu.scala:535:61, :537:46] wire _will_fire_sta_retry_0_T_3 = will_fire_sta_retry_0_will_fire; // @[lsu.scala:535:61, :538:46] wire _will_fire_sta_retry_0_T_9 = will_fire_sta_retry_0_will_fire; // @[lsu.scala:535:61, :540:46] wire _will_fire_sta_retry_0_T_1 = ~_will_fire_sta_retry_0_T; // @[lsu.scala:537:{34,46}] wire _will_fire_sta_retry_0_T_2 = _will_fire_load_retry_0_T_2 & _will_fire_sta_retry_0_T_1; // @[lsu.scala:537:{31,34}] wire _will_fire_load_wakeup_0_T_2 = _will_fire_sta_retry_0_T_2; // @[lsu.scala:537:31] wire _will_fire_sta_retry_0_T_4 = ~_will_fire_sta_retry_0_T_3; // @[lsu.scala:538:{34,46}] wire _will_fire_sta_retry_0_T_5 = _will_fire_load_retry_0_T_5 & _will_fire_sta_retry_0_T_4; // @[lsu.scala:538:{31,34}] wire _will_fire_sta_retry_0_T_10 = ~_will_fire_sta_retry_0_T_9; // @[lsu.scala:540:{34,46}] wire _will_fire_sta_retry_0_T_11 = _will_fire_load_retry_0_T_11 & _will_fire_sta_retry_0_T_10; // @[lsu.scala:540:{31,34}] wire _will_fire_load_wakeup_0_T_11 = _will_fire_sta_retry_0_T_11; // @[lsu.scala:540:31] wire _will_fire_load_wakeup_0_will_fire_T = ~_will_fire_sta_retry_0_T_2; // @[lsu.scala:533:51, :537:31] wire _will_fire_load_wakeup_0_will_fire_T_4 = ~_will_fire_sta_retry_0_T_5; // @[lsu.scala:534:52, :538:31] wire _will_fire_load_wakeup_0_will_fire_T_5 = _will_fire_load_wakeup_0_will_fire_T_4; // @[lsu.scala:534:{49,52}] wire _will_fire_load_wakeup_0_will_fire_T_6 = ~_will_fire_load_wakeup_0_will_fire_T_5; // @[lsu.scala:534:{35,49}] wire _will_fire_load_wakeup_0_will_fire_T_7 = _will_fire_load_wakeup_0_will_fire_T_3 & _will_fire_load_wakeup_0_will_fire_T_6; // @[lsu.scala:533:{32,63}, :534:35] wire _will_fire_load_wakeup_0_will_fire_T_8 = ~_will_fire_sta_retry_0_T_8; // @[lsu.scala:535:50, :539:31] wire _will_fire_load_wakeup_0_will_fire_T_9 = _will_fire_load_wakeup_0_will_fire_T_8; // @[lsu.scala:535:{47,50}] wire _will_fire_load_wakeup_0_will_fire_T_10 = ~_will_fire_load_wakeup_0_will_fire_T_9; // @[lsu.scala:535:{35,47}] wire _will_fire_load_wakeup_0_will_fire_T_11 = _will_fire_load_wakeup_0_will_fire_T_7 & _will_fire_load_wakeup_0_will_fire_T_10; // @[lsu.scala:533:63, :534:65, :535:35] assign will_fire_load_wakeup_0_will_fire = _will_fire_load_wakeup_0_will_fire_T_11; // @[lsu.scala:534:65, :535:61] wire _will_fire_load_wakeup_0_will_fire_T_12 = ~_will_fire_sta_retry_0_T_11; // @[lsu.scala:536:51, :540:31] assign will_fire_load_wakeup_0 = will_fire_load_wakeup_0_will_fire; // @[lsu.scala:381:38, :535:61] wire _will_fire_load_wakeup_0_T_3 = will_fire_load_wakeup_0_will_fire; // @[lsu.scala:535:61, :538:46] wire _will_fire_load_wakeup_0_T_6 = will_fire_load_wakeup_0_will_fire; // @[lsu.scala:535:61, :539:46] wire _will_fire_store_commit_0_T_2 = _will_fire_load_wakeup_0_T_2; // @[lsu.scala:537:31] wire _will_fire_load_wakeup_0_T_4 = ~_will_fire_load_wakeup_0_T_3; // @[lsu.scala:538:{34,46}] wire _will_fire_load_wakeup_0_T_5 = _will_fire_sta_retry_0_T_5 & _will_fire_load_wakeup_0_T_4; // @[lsu.scala:538:{31,34}] wire _will_fire_store_commit_0_T_5 = _will_fire_load_wakeup_0_T_5; // @[lsu.scala:538:31] wire _will_fire_load_wakeup_0_T_7 = ~_will_fire_load_wakeup_0_T_6; // @[lsu.scala:539:{34,46}] wire _will_fire_load_wakeup_0_T_8 = _will_fire_sta_retry_0_T_8 & _will_fire_load_wakeup_0_T_7; // @[lsu.scala:539:{31,34}] wire _will_fire_store_commit_0_T_11 = _will_fire_load_wakeup_0_T_11; // @[lsu.scala:540:31] wire _will_fire_store_commit_0_will_fire_T = ~_will_fire_load_wakeup_0_T_2; // @[lsu.scala:533:51, :537:31] wire _will_fire_store_commit_0_will_fire_T_7 = _will_fire_store_commit_0_will_fire_T_3; // @[lsu.scala:533:{32,63}] wire _will_fire_store_commit_0_will_fire_T_4 = ~_will_fire_load_wakeup_0_T_5; // @[lsu.scala:534:52, :538:31] wire _will_fire_store_commit_0_will_fire_T_8 = ~_will_fire_load_wakeup_0_T_8; // @[lsu.scala:535:50, :539:31] wire _will_fire_store_commit_0_will_fire_T_9 = _will_fire_store_commit_0_will_fire_T_8; // @[lsu.scala:535:{47,50}] wire _will_fire_store_commit_0_will_fire_T_10 = ~_will_fire_store_commit_0_will_fire_T_9; // @[lsu.scala:535:{35,47}] wire _will_fire_store_commit_0_will_fire_T_11 = _will_fire_store_commit_0_will_fire_T_7 & _will_fire_store_commit_0_will_fire_T_10; // @[lsu.scala:533:63, :534:65, :535:35] assign will_fire_store_commit_0_will_fire = _will_fire_store_commit_0_will_fire_T_11; // @[lsu.scala:534:65, :535:61] wire _will_fire_store_commit_0_will_fire_T_12 = ~_will_fire_load_wakeup_0_T_11; // @[lsu.scala:536:51, :540:31] assign will_fire_store_commit_0 = will_fire_store_commit_0_will_fire; // @[lsu.scala:380:38, :535:61] wire _will_fire_store_commit_0_T_6 = will_fire_store_commit_0_will_fire; // @[lsu.scala:535:61, :539:46] wire _will_fire_store_commit_0_T_7 = ~_will_fire_store_commit_0_T_6; // @[lsu.scala:539:{34,46}] wire _will_fire_store_commit_0_T_8 = _will_fire_load_wakeup_0_T_8 & _will_fire_store_commit_0_T_7; // @[lsu.scala:539:{31,34}] wire _T_109 = will_fire_load_incoming_0 | will_fire_stad_incoming_0; // @[lsu.scala:370:38, :371:38, :566:63] wire _exe_tlb_uop_T; // @[lsu.scala:596:53] assign _exe_tlb_uop_T = _T_109; // @[lsu.scala:566:63, :596:53] wire _exe_tlb_vaddr_T; // @[lsu.scala:606:53] assign _exe_tlb_vaddr_T = _T_109; // @[lsu.scala:566:63, :606:53] wire _exe_size_T; // @[lsu.scala:623:52] assign _exe_size_T = _T_109; // @[lsu.scala:566:63, :623:52] wire _exe_cmd_T; // @[lsu.scala:632:52] assign _exe_cmd_T = _T_109; // @[lsu.scala:566:63, :632:52] wire _GEN_203 = ldq_wakeup_idx == 3'h0; // @[lsu.scala:429:31, :569:49] wire _GEN_204 = ldq_wakeup_idx == 3'h1; // @[lsu.scala:429:31, :569:49] wire _GEN_205 = ldq_wakeup_idx == 3'h2; // @[lsu.scala:429:31, :569:49] wire _GEN_206 = ldq_wakeup_idx == 3'h3; // @[lsu.scala:429:31, :569:49] wire _GEN_207 = ldq_wakeup_idx == 3'h4; // @[lsu.scala:429:31, :569:49] wire _GEN_208 = ldq_wakeup_idx == 3'h5; // @[lsu.scala:429:31, :569:49] wire _GEN_209 = ldq_wakeup_idx == 3'h6; // @[lsu.scala:429:31, :569:49] wire _GEN_210 = ldq_retry_idx == 3'h0; // @[lsu.scala:414:30, :573:49] assign block_load_mask_0 = will_fire_load_wakeup_0 ? _GEN_203 : will_fire_load_incoming_0 ? exe_req_0_bits_uop_ldq_idx == 3'h0 : will_fire_load_retry_0 & _GEN_210; // @[lsu.scala:370:38, :378:38, :381:38, :383:25, :396:36, :568:37, :569:49, :570:46, :571:52, :572:43, :573:49] wire _GEN_211 = ldq_retry_idx == 3'h1; // @[lsu.scala:414:30, :573:49] assign block_load_mask_1 = will_fire_load_wakeup_0 ? _GEN_204 : will_fire_load_incoming_0 ? exe_req_0_bits_uop_ldq_idx == 3'h1 : will_fire_load_retry_0 & _GEN_211; // @[lsu.scala:370:38, :378:38, :381:38, :383:25, :396:36, :568:37, :569:49, :570:46, :571:52, :572:43, :573:49] wire _GEN_212 = ldq_retry_idx == 3'h2; // @[lsu.scala:414:30, :573:49] assign block_load_mask_2 = will_fire_load_wakeup_0 ? _GEN_205 : will_fire_load_incoming_0 ? exe_req_0_bits_uop_ldq_idx == 3'h2 : will_fire_load_retry_0 & _GEN_212; // @[lsu.scala:370:38, :378:38, :381:38, :383:25, :396:36, :568:37, :569:49, :570:46, :571:52, :572:43, :573:49] wire _GEN_213 = ldq_retry_idx == 3'h3; // @[lsu.scala:414:30, :573:49] assign block_load_mask_3 = will_fire_load_wakeup_0 ? _GEN_206 : will_fire_load_incoming_0 ? exe_req_0_bits_uop_ldq_idx == 3'h3 : will_fire_load_retry_0 & _GEN_213; // @[lsu.scala:370:38, :378:38, :381:38, :383:25, :396:36, :568:37, :569:49, :570:46, :571:52, :572:43, :573:49] wire _GEN_214 = ldq_retry_idx == 3'h4; // @[lsu.scala:414:30, :573:49] assign block_load_mask_4 = will_fire_load_wakeup_0 ? _GEN_207 : will_fire_load_incoming_0 ? exe_req_0_bits_uop_ldq_idx == 3'h4 : will_fire_load_retry_0 & _GEN_214; // @[lsu.scala:370:38, :378:38, :381:38, :383:25, :396:36, :568:37, :569:49, :570:46, :571:52, :572:43, :573:49] wire _GEN_215 = ldq_retry_idx == 3'h5; // @[lsu.scala:414:30, :573:49] assign block_load_mask_5 = will_fire_load_wakeup_0 ? _GEN_208 : will_fire_load_incoming_0 ? exe_req_0_bits_uop_ldq_idx == 3'h5 : will_fire_load_retry_0 & _GEN_215; // @[lsu.scala:370:38, :378:38, :381:38, :383:25, :396:36, :568:37, :569:49, :570:46, :571:52, :572:43, :573:49] wire _GEN_216 = ldq_retry_idx == 3'h6; // @[lsu.scala:414:30, :573:49] assign block_load_mask_6 = will_fire_load_wakeup_0 ? _GEN_209 : will_fire_load_incoming_0 ? exe_req_0_bits_uop_ldq_idx == 3'h6 : will_fire_load_retry_0 & _GEN_216; // @[lsu.scala:370:38, :378:38, :381:38, :383:25, :396:36, :568:37, :569:49, :570:46, :571:52, :572:43, :573:49] assign block_load_mask_7 = will_fire_load_wakeup_0 ? (&ldq_wakeup_idx) : will_fire_load_incoming_0 ? (&exe_req_0_bits_uop_ldq_idx) : will_fire_load_retry_0 & (&ldq_retry_idx); // @[lsu.scala:370:38, :378:38, :381:38, :383:25, :396:36, :414:30, :429:31, :568:37, :569:49, :570:46, :571:52, :572:43, :573:49] assign _exe_tlb_valid_0_T = ~_will_fire_store_commit_0_T_2; // @[lsu.scala:537:31, :575:25] assign exe_tlb_valid_0 = _exe_tlb_valid_0_T; // @[lsu.scala:525:27, :575:25] wire _exe_tlb_uop_T_1 = _exe_tlb_uop_T | will_fire_sta_incoming_0; // @[lsu.scala:372:38, :596:53, :597:53] wire _exe_tlb_uop_T_2 = _exe_tlb_uop_T_1 | will_fire_sfence_0; // @[lsu.scala:374:38, :597:53, :598:53] wire [6:0] _exe_tlb_uop_T_4_uopc = will_fire_sta_retry_0 ? mem_stq_retry_e_out_bits_uop_uopc : 7'h0; // @[util.scala:106:23] wire [31:0] _exe_tlb_uop_T_4_inst = will_fire_sta_retry_0 ? mem_stq_retry_e_out_bits_uop_inst : 32'h0; // @[util.scala:106:23] wire [31:0] _exe_tlb_uop_T_4_debug_inst = will_fire_sta_retry_0 ? mem_stq_retry_e_out_bits_uop_debug_inst : 32'h0; // @[util.scala:106:23] wire _exe_tlb_uop_T_4_is_rvc = will_fire_sta_retry_0 & mem_stq_retry_e_out_bits_uop_is_rvc; // @[util.scala:106:23] wire [39:0] _exe_tlb_uop_T_4_debug_pc = will_fire_sta_retry_0 ? mem_stq_retry_e_out_bits_uop_debug_pc : 40'h0; // @[util.scala:106:23] wire [2:0] _exe_tlb_uop_T_4_iq_type = will_fire_sta_retry_0 ? mem_stq_retry_e_out_bits_uop_iq_type : 3'h0; // @[util.scala:106:23] wire [9:0] _exe_tlb_uop_T_4_fu_code = will_fire_sta_retry_0 ? mem_stq_retry_e_out_bits_uop_fu_code : 10'h0; // @[util.scala:106:23] wire [3:0] _exe_tlb_uop_T_4_ctrl_br_type = will_fire_sta_retry_0 ? mem_stq_retry_e_out_bits_uop_ctrl_br_type : 4'h0; // @[util.scala:106:23] wire [1:0] _exe_tlb_uop_T_4_ctrl_op1_sel = will_fire_sta_retry_0 ? mem_stq_retry_e_out_bits_uop_ctrl_op1_sel : 2'h0; // @[util.scala:106:23] wire [2:0] _exe_tlb_uop_T_4_ctrl_op2_sel = will_fire_sta_retry_0 ? mem_stq_retry_e_out_bits_uop_ctrl_op2_sel : 3'h0; // @[util.scala:106:23] wire [2:0] _exe_tlb_uop_T_4_ctrl_imm_sel = will_fire_sta_retry_0 ? mem_stq_retry_e_out_bits_uop_ctrl_imm_sel : 3'h0; // @[util.scala:106:23] wire [4:0] _exe_tlb_uop_T_4_ctrl_op_fcn = will_fire_sta_retry_0 ? mem_stq_retry_e_out_bits_uop_ctrl_op_fcn : 5'h0; // @[util.scala:106:23] wire _exe_tlb_uop_T_4_ctrl_fcn_dw = will_fire_sta_retry_0 & mem_stq_retry_e_out_bits_uop_ctrl_fcn_dw; // @[util.scala:106:23] wire [2:0] _exe_tlb_uop_T_4_ctrl_csr_cmd = will_fire_sta_retry_0 ? mem_stq_retry_e_out_bits_uop_ctrl_csr_cmd : 3'h0; // @[util.scala:106:23] wire _exe_tlb_uop_T_4_ctrl_is_load = will_fire_sta_retry_0 & mem_stq_retry_e_out_bits_uop_ctrl_is_load; // @[util.scala:106:23] wire _exe_tlb_uop_T_4_ctrl_is_sta = will_fire_sta_retry_0 & mem_stq_retry_e_out_bits_uop_ctrl_is_sta; // @[util.scala:106:23] wire _exe_tlb_uop_T_4_ctrl_is_std = will_fire_sta_retry_0 & mem_stq_retry_e_out_bits_uop_ctrl_is_std; // @[util.scala:106:23] wire [1:0] _exe_tlb_uop_T_4_iw_state = will_fire_sta_retry_0 ? mem_stq_retry_e_out_bits_uop_iw_state : 2'h0; // @[util.scala:106:23] wire _exe_tlb_uop_T_4_iw_p1_poisoned = will_fire_sta_retry_0 & mem_stq_retry_e_out_bits_uop_iw_p1_poisoned; // @[util.scala:106:23] wire _exe_tlb_uop_T_4_iw_p2_poisoned = will_fire_sta_retry_0 & mem_stq_retry_e_out_bits_uop_iw_p2_poisoned; // @[util.scala:106:23] wire _exe_tlb_uop_T_4_is_br = will_fire_sta_retry_0 & mem_stq_retry_e_out_bits_uop_is_br; // @[util.scala:106:23] wire _exe_tlb_uop_T_4_is_jalr = will_fire_sta_retry_0 & mem_stq_retry_e_out_bits_uop_is_jalr; // @[util.scala:106:23] wire _exe_tlb_uop_T_4_is_jal = will_fire_sta_retry_0 & mem_stq_retry_e_out_bits_uop_is_jal; // @[util.scala:106:23] wire _exe_tlb_uop_T_4_is_sfb = will_fire_sta_retry_0 & mem_stq_retry_e_out_bits_uop_is_sfb; // @[util.scala:106:23] wire [7:0] _exe_tlb_uop_T_4_br_mask = will_fire_sta_retry_0 ? _GEN_25[_stq_retry_e_T_1] : 8'h0; // @[lsu.scala:222:42, :379:38, :477:79, :601:24] wire [2:0] _exe_tlb_uop_T_4_br_tag = will_fire_sta_retry_0 ? mem_stq_retry_e_out_bits_uop_br_tag : 3'h0; // @[util.scala:106:23] wire [3:0] _exe_tlb_uop_T_4_ftq_idx = will_fire_sta_retry_0 ? mem_stq_retry_e_out_bits_uop_ftq_idx : 4'h0; // @[util.scala:106:23] wire _exe_tlb_uop_T_4_edge_inst = will_fire_sta_retry_0 & mem_stq_retry_e_out_bits_uop_edge_inst; // @[util.scala:106:23] wire [5:0] _exe_tlb_uop_T_4_pc_lob = will_fire_sta_retry_0 ? mem_stq_retry_e_out_bits_uop_pc_lob : 6'h0; // @[util.scala:106:23] wire _exe_tlb_uop_T_4_taken = will_fire_sta_retry_0 & mem_stq_retry_e_out_bits_uop_taken; // @[util.scala:106:23] wire [19:0] _exe_tlb_uop_T_4_imm_packed = will_fire_sta_retry_0 ? mem_stq_retry_e_out_bits_uop_imm_packed : 20'h0; // @[util.scala:106:23] wire [11:0] _exe_tlb_uop_T_4_csr_addr = will_fire_sta_retry_0 ? mem_stq_retry_e_out_bits_uop_csr_addr : 12'h0; // @[util.scala:106:23] wire [4:0] _exe_tlb_uop_T_4_rob_idx = will_fire_sta_retry_0 ? mem_stq_retry_e_out_bits_uop_rob_idx : 5'h0; // @[util.scala:106:23] wire [2:0] _exe_tlb_uop_T_4_ldq_idx = will_fire_sta_retry_0 ? mem_stq_retry_e_out_bits_uop_ldq_idx : 3'h0; // @[util.scala:106:23] wire [2:0] _exe_tlb_uop_T_4_stq_idx = will_fire_sta_retry_0 ? mem_stq_retry_e_out_bits_uop_stq_idx : 3'h0; // @[util.scala:106:23] wire [1:0] _exe_tlb_uop_T_4_rxq_idx = will_fire_sta_retry_0 ? mem_stq_retry_e_out_bits_uop_rxq_idx : 2'h0; // @[util.scala:106:23] wire [5:0] _exe_tlb_uop_T_4_pdst = will_fire_sta_retry_0 ? mem_stq_retry_e_out_bits_uop_pdst : 6'h0; // @[util.scala:106:23] wire [5:0] _exe_tlb_uop_T_4_prs1 = will_fire_sta_retry_0 ? mem_stq_retry_e_out_bits_uop_prs1 : 6'h0; // @[util.scala:106:23] wire [5:0] _exe_tlb_uop_T_4_prs2 = will_fire_sta_retry_0 ? mem_stq_retry_e_out_bits_uop_prs2 : 6'h0; // @[util.scala:106:23] wire [5:0] _exe_tlb_uop_T_4_prs3 = will_fire_sta_retry_0 ? mem_stq_retry_e_out_bits_uop_prs3 : 6'h0; // @[util.scala:106:23] wire [3:0] _exe_tlb_uop_T_4_ppred = will_fire_sta_retry_0 ? mem_stq_retry_e_out_bits_uop_ppred : 4'h0; // @[util.scala:106:23] wire _exe_tlb_uop_T_4_prs1_busy = will_fire_sta_retry_0 & mem_stq_retry_e_out_bits_uop_prs1_busy; // @[util.scala:106:23] wire _exe_tlb_uop_T_4_prs2_busy = will_fire_sta_retry_0 & mem_stq_retry_e_out_bits_uop_prs2_busy; // @[util.scala:106:23] wire _exe_tlb_uop_T_4_prs3_busy = will_fire_sta_retry_0 & mem_stq_retry_e_out_bits_uop_prs3_busy; // @[util.scala:106:23] wire _exe_tlb_uop_T_4_ppred_busy = will_fire_sta_retry_0 & mem_stq_retry_e_out_bits_uop_ppred_busy; // @[util.scala:106:23] wire [5:0] _exe_tlb_uop_T_4_stale_pdst = will_fire_sta_retry_0 ? mem_stq_retry_e_out_bits_uop_stale_pdst : 6'h0; // @[util.scala:106:23] wire _exe_tlb_uop_T_4_exception = will_fire_sta_retry_0 & mem_stq_retry_e_out_bits_uop_exception; // @[util.scala:106:23] wire [63:0] _exe_tlb_uop_T_4_exc_cause = will_fire_sta_retry_0 ? mem_stq_retry_e_out_bits_uop_exc_cause : 64'h0; // @[util.scala:106:23] wire _exe_tlb_uop_T_4_bypassable = will_fire_sta_retry_0 & mem_stq_retry_e_out_bits_uop_bypassable; // @[util.scala:106:23] wire [4:0] _exe_tlb_uop_T_4_mem_cmd = will_fire_sta_retry_0 ? mem_stq_retry_e_out_bits_uop_mem_cmd : 5'h0; // @[util.scala:106:23] wire [1:0] _exe_tlb_uop_T_4_mem_size = will_fire_sta_retry_0 ? mem_stq_retry_e_out_bits_uop_mem_size : 2'h0; // @[util.scala:106:23] wire _exe_tlb_uop_T_4_mem_signed = will_fire_sta_retry_0 & mem_stq_retry_e_out_bits_uop_mem_signed; // @[util.scala:106:23] wire _exe_tlb_uop_T_4_is_fence = will_fire_sta_retry_0 & mem_stq_retry_e_out_bits_uop_is_fence; // @[util.scala:106:23] wire _exe_tlb_uop_T_4_is_fencei = will_fire_sta_retry_0 & mem_stq_retry_e_out_bits_uop_is_fencei; // @[util.scala:106:23] wire _exe_tlb_uop_T_4_is_amo = will_fire_sta_retry_0 & mem_stq_retry_e_out_bits_uop_is_amo; // @[util.scala:106:23] wire _exe_tlb_uop_T_4_uses_ldq = will_fire_sta_retry_0 & mem_stq_retry_e_out_bits_uop_uses_ldq; // @[util.scala:106:23] wire _exe_tlb_uop_T_4_uses_stq = will_fire_sta_retry_0 & mem_stq_retry_e_out_bits_uop_uses_stq; // @[util.scala:106:23] wire _exe_tlb_uop_T_4_is_sys_pc2epc = will_fire_sta_retry_0 & mem_stq_retry_e_out_bits_uop_is_sys_pc2epc; // @[util.scala:106:23] wire _exe_tlb_uop_T_4_is_unique = will_fire_sta_retry_0 & mem_stq_retry_e_out_bits_uop_is_unique; // @[util.scala:106:23] wire _exe_tlb_uop_T_4_flush_on_commit = will_fire_sta_retry_0 & mem_stq_retry_e_out_bits_uop_flush_on_commit; // @[util.scala:106:23] wire _exe_tlb_uop_T_4_ldst_is_rs1 = will_fire_sta_retry_0 & mem_stq_retry_e_out_bits_uop_ldst_is_rs1; // @[util.scala:106:23] wire [5:0] _exe_tlb_uop_T_4_ldst = will_fire_sta_retry_0 ? mem_stq_retry_e_out_bits_uop_ldst : 6'h0; // @[util.scala:106:23] wire [5:0] _exe_tlb_uop_T_4_lrs1 = will_fire_sta_retry_0 ? mem_stq_retry_e_out_bits_uop_lrs1 : 6'h0; // @[util.scala:106:23] wire [5:0] _exe_tlb_uop_T_4_lrs2 = will_fire_sta_retry_0 ? mem_stq_retry_e_out_bits_uop_lrs2 : 6'h0; // @[util.scala:106:23] wire [5:0] _exe_tlb_uop_T_4_lrs3 = will_fire_sta_retry_0 ? mem_stq_retry_e_out_bits_uop_lrs3 : 6'h0; // @[util.scala:106:23] wire _exe_tlb_uop_T_4_ldst_val = will_fire_sta_retry_0 & mem_stq_retry_e_out_bits_uop_ldst_val; // @[util.scala:106:23] wire [1:0] _exe_tlb_uop_T_4_dst_rtype = will_fire_sta_retry_0 ? mem_stq_retry_e_out_bits_uop_dst_rtype : 2'h2; // @[util.scala:106:23] wire [1:0] _exe_tlb_uop_T_4_lrs1_rtype = will_fire_sta_retry_0 ? mem_stq_retry_e_out_bits_uop_lrs1_rtype : 2'h0; // @[util.scala:106:23] wire [1:0] _exe_tlb_uop_T_4_lrs2_rtype = will_fire_sta_retry_0 ? mem_stq_retry_e_out_bits_uop_lrs2_rtype : 2'h0; // @[util.scala:106:23] wire _exe_tlb_uop_T_4_frs3_en = will_fire_sta_retry_0 & mem_stq_retry_e_out_bits_uop_frs3_en; // @[util.scala:106:23] wire _exe_tlb_uop_T_4_fp_val = will_fire_sta_retry_0 & mem_stq_retry_e_out_bits_uop_fp_val; // @[util.scala:106:23] wire _exe_tlb_uop_T_4_fp_single = will_fire_sta_retry_0 & mem_stq_retry_e_out_bits_uop_fp_single; // @[util.scala:106:23] wire _exe_tlb_uop_T_4_xcpt_pf_if = will_fire_sta_retry_0 & mem_stq_retry_e_out_bits_uop_xcpt_pf_if; // @[util.scala:106:23] wire _exe_tlb_uop_T_4_xcpt_ae_if = will_fire_sta_retry_0 & mem_stq_retry_e_out_bits_uop_xcpt_ae_if; // @[util.scala:106:23] wire _exe_tlb_uop_T_4_xcpt_ma_if = will_fire_sta_retry_0 & mem_stq_retry_e_out_bits_uop_xcpt_ma_if; // @[util.scala:106:23] wire _exe_tlb_uop_T_4_bp_debug_if = will_fire_sta_retry_0 & mem_stq_retry_e_out_bits_uop_bp_debug_if; // @[util.scala:106:23] wire _exe_tlb_uop_T_4_bp_xcpt_if = will_fire_sta_retry_0 & mem_stq_retry_e_out_bits_uop_bp_xcpt_if; // @[util.scala:106:23] wire [1:0] _exe_tlb_uop_T_4_debug_fsrc = will_fire_sta_retry_0 ? mem_stq_retry_e_out_bits_uop_debug_fsrc : 2'h0; // @[util.scala:106:23] wire [1:0] _exe_tlb_uop_T_4_debug_tsrc = will_fire_sta_retry_0 ? mem_stq_retry_e_out_bits_uop_debug_tsrc : 2'h0; // @[util.scala:106:23] wire [6:0] _exe_tlb_uop_T_5_uopc = will_fire_load_retry_0 ? mem_ldq_retry_e_out_bits_uop_uopc : _exe_tlb_uop_T_4_uopc; // @[util.scala:106:23] wire [31:0] _exe_tlb_uop_T_5_inst = will_fire_load_retry_0 ? mem_ldq_retry_e_out_bits_uop_inst : _exe_tlb_uop_T_4_inst; // @[util.scala:106:23] wire [31:0] _exe_tlb_uop_T_5_debug_inst = will_fire_load_retry_0 ? mem_ldq_retry_e_out_bits_uop_debug_inst : _exe_tlb_uop_T_4_debug_inst; // @[util.scala:106:23] wire _exe_tlb_uop_T_5_is_rvc = will_fire_load_retry_0 ? mem_ldq_retry_e_out_bits_uop_is_rvc : _exe_tlb_uop_T_4_is_rvc; // @[util.scala:106:23] wire [39:0] _exe_tlb_uop_T_5_debug_pc = will_fire_load_retry_0 ? mem_ldq_retry_e_out_bits_uop_debug_pc : _exe_tlb_uop_T_4_debug_pc; // @[util.scala:106:23] wire [2:0] _exe_tlb_uop_T_5_iq_type = will_fire_load_retry_0 ? mem_ldq_retry_e_out_bits_uop_iq_type : _exe_tlb_uop_T_4_iq_type; // @[util.scala:106:23] wire [9:0] _exe_tlb_uop_T_5_fu_code = will_fire_load_retry_0 ? mem_ldq_retry_e_out_bits_uop_fu_code : _exe_tlb_uop_T_4_fu_code; // @[util.scala:106:23] wire [3:0] _exe_tlb_uop_T_5_ctrl_br_type = will_fire_load_retry_0 ? mem_ldq_retry_e_out_bits_uop_ctrl_br_type : _exe_tlb_uop_T_4_ctrl_br_type; // @[util.scala:106:23] wire [1:0] _exe_tlb_uop_T_5_ctrl_op1_sel = will_fire_load_retry_0 ? mem_ldq_retry_e_out_bits_uop_ctrl_op1_sel : _exe_tlb_uop_T_4_ctrl_op1_sel; // @[util.scala:106:23] wire [2:0] _exe_tlb_uop_T_5_ctrl_op2_sel = will_fire_load_retry_0 ? mem_ldq_retry_e_out_bits_uop_ctrl_op2_sel : _exe_tlb_uop_T_4_ctrl_op2_sel; // @[util.scala:106:23] wire [2:0] _exe_tlb_uop_T_5_ctrl_imm_sel = will_fire_load_retry_0 ? mem_ldq_retry_e_out_bits_uop_ctrl_imm_sel : _exe_tlb_uop_T_4_ctrl_imm_sel; // @[util.scala:106:23] wire [4:0] _exe_tlb_uop_T_5_ctrl_op_fcn = will_fire_load_retry_0 ? mem_ldq_retry_e_out_bits_uop_ctrl_op_fcn : _exe_tlb_uop_T_4_ctrl_op_fcn; // @[util.scala:106:23] wire _exe_tlb_uop_T_5_ctrl_fcn_dw = will_fire_load_retry_0 ? mem_ldq_retry_e_out_bits_uop_ctrl_fcn_dw : _exe_tlb_uop_T_4_ctrl_fcn_dw; // @[util.scala:106:23] wire [2:0] _exe_tlb_uop_T_5_ctrl_csr_cmd = will_fire_load_retry_0 ? mem_ldq_retry_e_out_bits_uop_ctrl_csr_cmd : _exe_tlb_uop_T_4_ctrl_csr_cmd; // @[util.scala:106:23] wire _exe_tlb_uop_T_5_ctrl_is_load = will_fire_load_retry_0 ? mem_ldq_retry_e_out_bits_uop_ctrl_is_load : _exe_tlb_uop_T_4_ctrl_is_load; // @[util.scala:106:23] wire _exe_tlb_uop_T_5_ctrl_is_sta = will_fire_load_retry_0 ? mem_ldq_retry_e_out_bits_uop_ctrl_is_sta : _exe_tlb_uop_T_4_ctrl_is_sta; // @[util.scala:106:23] wire _exe_tlb_uop_T_5_ctrl_is_std = will_fire_load_retry_0 ? mem_ldq_retry_e_out_bits_uop_ctrl_is_std : _exe_tlb_uop_T_4_ctrl_is_std; // @[util.scala:106:23] wire [1:0] _exe_tlb_uop_T_5_iw_state = will_fire_load_retry_0 ? mem_ldq_retry_e_out_bits_uop_iw_state : _exe_tlb_uop_T_4_iw_state; // @[util.scala:106:23] wire _exe_tlb_uop_T_5_iw_p1_poisoned = will_fire_load_retry_0 ? mem_ldq_retry_e_out_bits_uop_iw_p1_poisoned : _exe_tlb_uop_T_4_iw_p1_poisoned; // @[util.scala:106:23] wire _exe_tlb_uop_T_5_iw_p2_poisoned = will_fire_load_retry_0 ? mem_ldq_retry_e_out_bits_uop_iw_p2_poisoned : _exe_tlb_uop_T_4_iw_p2_poisoned; // @[util.scala:106:23] wire _exe_tlb_uop_T_5_is_br = will_fire_load_retry_0 ? mem_ldq_retry_e_out_bits_uop_is_br : _exe_tlb_uop_T_4_is_br; // @[util.scala:106:23] wire _exe_tlb_uop_T_5_is_jalr = will_fire_load_retry_0 ? mem_ldq_retry_e_out_bits_uop_is_jalr : _exe_tlb_uop_T_4_is_jalr; // @[util.scala:106:23] wire _exe_tlb_uop_T_5_is_jal = will_fire_load_retry_0 ? mem_ldq_retry_e_out_bits_uop_is_jal : _exe_tlb_uop_T_4_is_jal; // @[util.scala:106:23] wire _exe_tlb_uop_T_5_is_sfb = will_fire_load_retry_0 ? mem_ldq_retry_e_out_bits_uop_is_sfb : _exe_tlb_uop_T_4_is_sfb; // @[util.scala:106:23] wire [7:0] _exe_tlb_uop_T_5_br_mask = will_fire_load_retry_0 ? _GEN_118[_ldq_retry_e_T_1] : _exe_tlb_uop_T_4_br_mask; // @[lsu.scala:263:49, :378:38, :464:79, :600:24, :601:24] wire [2:0] _exe_tlb_uop_T_5_br_tag = will_fire_load_retry_0 ? mem_ldq_retry_e_out_bits_uop_br_tag : _exe_tlb_uop_T_4_br_tag; // @[util.scala:106:23] wire [3:0] _exe_tlb_uop_T_5_ftq_idx = will_fire_load_retry_0 ? mem_ldq_retry_e_out_bits_uop_ftq_idx : _exe_tlb_uop_T_4_ftq_idx; // @[util.scala:106:23] wire _exe_tlb_uop_T_5_edge_inst = will_fire_load_retry_0 ? mem_ldq_retry_e_out_bits_uop_edge_inst : _exe_tlb_uop_T_4_edge_inst; // @[util.scala:106:23] wire [5:0] _exe_tlb_uop_T_5_pc_lob = will_fire_load_retry_0 ? mem_ldq_retry_e_out_bits_uop_pc_lob : _exe_tlb_uop_T_4_pc_lob; // @[util.scala:106:23] wire _exe_tlb_uop_T_5_taken = will_fire_load_retry_0 ? mem_ldq_retry_e_out_bits_uop_taken : _exe_tlb_uop_T_4_taken; // @[util.scala:106:23] wire [19:0] _exe_tlb_uop_T_5_imm_packed = will_fire_load_retry_0 ? mem_ldq_retry_e_out_bits_uop_imm_packed : _exe_tlb_uop_T_4_imm_packed; // @[util.scala:106:23] wire [11:0] _exe_tlb_uop_T_5_csr_addr = will_fire_load_retry_0 ? mem_ldq_retry_e_out_bits_uop_csr_addr : _exe_tlb_uop_T_4_csr_addr; // @[util.scala:106:23] wire [4:0] _exe_tlb_uop_T_5_rob_idx = will_fire_load_retry_0 ? mem_ldq_retry_e_out_bits_uop_rob_idx : _exe_tlb_uop_T_4_rob_idx; // @[util.scala:106:23] wire [2:0] _exe_tlb_uop_T_5_ldq_idx = will_fire_load_retry_0 ? mem_ldq_retry_e_out_bits_uop_ldq_idx : _exe_tlb_uop_T_4_ldq_idx; // @[util.scala:106:23] wire [2:0] _exe_tlb_uop_T_5_stq_idx = will_fire_load_retry_0 ? mem_ldq_retry_e_out_bits_uop_stq_idx : _exe_tlb_uop_T_4_stq_idx; // @[util.scala:106:23] wire [1:0] _exe_tlb_uop_T_5_rxq_idx = will_fire_load_retry_0 ? mem_ldq_retry_e_out_bits_uop_rxq_idx : _exe_tlb_uop_T_4_rxq_idx; // @[util.scala:106:23] wire [5:0] _exe_tlb_uop_T_5_pdst = will_fire_load_retry_0 ? mem_ldq_retry_e_out_bits_uop_pdst : _exe_tlb_uop_T_4_pdst; // @[util.scala:106:23] wire [5:0] _exe_tlb_uop_T_5_prs1 = will_fire_load_retry_0 ? mem_ldq_retry_e_out_bits_uop_prs1 : _exe_tlb_uop_T_4_prs1; // @[util.scala:106:23] wire [5:0] _exe_tlb_uop_T_5_prs2 = will_fire_load_retry_0 ? mem_ldq_retry_e_out_bits_uop_prs2 : _exe_tlb_uop_T_4_prs2; // @[util.scala:106:23] wire [5:0] _exe_tlb_uop_T_5_prs3 = will_fire_load_retry_0 ? mem_ldq_retry_e_out_bits_uop_prs3 : _exe_tlb_uop_T_4_prs3; // @[util.scala:106:23] wire [3:0] _exe_tlb_uop_T_5_ppred = will_fire_load_retry_0 ? 4'h0 : _exe_tlb_uop_T_4_ppred; // @[lsu.scala:378:38, :600:24, :601:24] wire _exe_tlb_uop_T_5_prs1_busy = will_fire_load_retry_0 ? mem_ldq_retry_e_out_bits_uop_prs1_busy : _exe_tlb_uop_T_4_prs1_busy; // @[util.scala:106:23] wire _exe_tlb_uop_T_5_prs2_busy = will_fire_load_retry_0 ? mem_ldq_retry_e_out_bits_uop_prs2_busy : _exe_tlb_uop_T_4_prs2_busy; // @[util.scala:106:23] wire _exe_tlb_uop_T_5_prs3_busy = will_fire_load_retry_0 ? mem_ldq_retry_e_out_bits_uop_prs3_busy : _exe_tlb_uop_T_4_prs3_busy; // @[util.scala:106:23] wire _exe_tlb_uop_T_5_ppred_busy = ~will_fire_load_retry_0 & _exe_tlb_uop_T_4_ppred_busy; // @[lsu.scala:378:38, :600:24, :601:24] wire [5:0] _exe_tlb_uop_T_5_stale_pdst = will_fire_load_retry_0 ? mem_ldq_retry_e_out_bits_uop_stale_pdst : _exe_tlb_uop_T_4_stale_pdst; // @[util.scala:106:23] wire _exe_tlb_uop_T_5_exception = will_fire_load_retry_0 ? mem_ldq_retry_e_out_bits_uop_exception : _exe_tlb_uop_T_4_exception; // @[util.scala:106:23] wire [63:0] _exe_tlb_uop_T_5_exc_cause = will_fire_load_retry_0 ? mem_ldq_retry_e_out_bits_uop_exc_cause : _exe_tlb_uop_T_4_exc_cause; // @[util.scala:106:23] wire _exe_tlb_uop_T_5_bypassable = will_fire_load_retry_0 ? mem_ldq_retry_e_out_bits_uop_bypassable : _exe_tlb_uop_T_4_bypassable; // @[util.scala:106:23] wire [4:0] _exe_tlb_uop_T_5_mem_cmd = will_fire_load_retry_0 ? mem_ldq_retry_e_out_bits_uop_mem_cmd : _exe_tlb_uop_T_4_mem_cmd; // @[util.scala:106:23] wire [1:0] _exe_tlb_uop_T_5_mem_size = will_fire_load_retry_0 ? mem_ldq_retry_e_out_bits_uop_mem_size : _exe_tlb_uop_T_4_mem_size; // @[util.scala:106:23] wire _exe_tlb_uop_T_5_mem_signed = will_fire_load_retry_0 ? mem_ldq_retry_e_out_bits_uop_mem_signed : _exe_tlb_uop_T_4_mem_signed; // @[util.scala:106:23] wire _exe_tlb_uop_T_5_is_fence = will_fire_load_retry_0 ? mem_ldq_retry_e_out_bits_uop_is_fence : _exe_tlb_uop_T_4_is_fence; // @[util.scala:106:23] wire _exe_tlb_uop_T_5_is_fencei = will_fire_load_retry_0 ? mem_ldq_retry_e_out_bits_uop_is_fencei : _exe_tlb_uop_T_4_is_fencei; // @[util.scala:106:23] wire _exe_tlb_uop_T_5_is_amo = will_fire_load_retry_0 ? mem_ldq_retry_e_out_bits_uop_is_amo : _exe_tlb_uop_T_4_is_amo; // @[util.scala:106:23] wire _exe_tlb_uop_T_5_uses_ldq = will_fire_load_retry_0 ? mem_ldq_retry_e_out_bits_uop_uses_ldq : _exe_tlb_uop_T_4_uses_ldq; // @[util.scala:106:23] wire _exe_tlb_uop_T_5_uses_stq = will_fire_load_retry_0 ? mem_ldq_retry_e_out_bits_uop_uses_stq : _exe_tlb_uop_T_4_uses_stq; // @[util.scala:106:23] wire _exe_tlb_uop_T_5_is_sys_pc2epc = will_fire_load_retry_0 ? mem_ldq_retry_e_out_bits_uop_is_sys_pc2epc : _exe_tlb_uop_T_4_is_sys_pc2epc; // @[util.scala:106:23] wire _exe_tlb_uop_T_5_is_unique = will_fire_load_retry_0 ? mem_ldq_retry_e_out_bits_uop_is_unique : _exe_tlb_uop_T_4_is_unique; // @[util.scala:106:23] wire _exe_tlb_uop_T_5_flush_on_commit = will_fire_load_retry_0 ? mem_ldq_retry_e_out_bits_uop_flush_on_commit : _exe_tlb_uop_T_4_flush_on_commit; // @[util.scala:106:23] wire _exe_tlb_uop_T_5_ldst_is_rs1 = will_fire_load_retry_0 ? mem_ldq_retry_e_out_bits_uop_ldst_is_rs1 : _exe_tlb_uop_T_4_ldst_is_rs1; // @[util.scala:106:23] wire [5:0] _exe_tlb_uop_T_5_ldst = will_fire_load_retry_0 ? mem_ldq_retry_e_out_bits_uop_ldst : _exe_tlb_uop_T_4_ldst; // @[util.scala:106:23] wire [5:0] _exe_tlb_uop_T_5_lrs1 = will_fire_load_retry_0 ? mem_ldq_retry_e_out_bits_uop_lrs1 : _exe_tlb_uop_T_4_lrs1; // @[util.scala:106:23] wire [5:0] _exe_tlb_uop_T_5_lrs2 = will_fire_load_retry_0 ? mem_ldq_retry_e_out_bits_uop_lrs2 : _exe_tlb_uop_T_4_lrs2; // @[util.scala:106:23] wire [5:0] _exe_tlb_uop_T_5_lrs3 = will_fire_load_retry_0 ? mem_ldq_retry_e_out_bits_uop_lrs3 : _exe_tlb_uop_T_4_lrs3; // @[util.scala:106:23] wire _exe_tlb_uop_T_5_ldst_val = will_fire_load_retry_0 ? mem_ldq_retry_e_out_bits_uop_ldst_val : _exe_tlb_uop_T_4_ldst_val; // @[util.scala:106:23] wire [1:0] _exe_tlb_uop_T_5_dst_rtype = will_fire_load_retry_0 ? mem_ldq_retry_e_out_bits_uop_dst_rtype : _exe_tlb_uop_T_4_dst_rtype; // @[util.scala:106:23] wire [1:0] _exe_tlb_uop_T_5_lrs1_rtype = will_fire_load_retry_0 ? mem_ldq_retry_e_out_bits_uop_lrs1_rtype : _exe_tlb_uop_T_4_lrs1_rtype; // @[util.scala:106:23] wire [1:0] _exe_tlb_uop_T_5_lrs2_rtype = will_fire_load_retry_0 ? mem_ldq_retry_e_out_bits_uop_lrs2_rtype : _exe_tlb_uop_T_4_lrs2_rtype; // @[util.scala:106:23] wire _exe_tlb_uop_T_5_frs3_en = will_fire_load_retry_0 ? mem_ldq_retry_e_out_bits_uop_frs3_en : _exe_tlb_uop_T_4_frs3_en; // @[util.scala:106:23] wire _exe_tlb_uop_T_5_fp_val = will_fire_load_retry_0 ? mem_ldq_retry_e_out_bits_uop_fp_val : _exe_tlb_uop_T_4_fp_val; // @[util.scala:106:23] wire _exe_tlb_uop_T_5_fp_single = will_fire_load_retry_0 ? mem_ldq_retry_e_out_bits_uop_fp_single : _exe_tlb_uop_T_4_fp_single; // @[util.scala:106:23] wire _exe_tlb_uop_T_5_xcpt_pf_if = will_fire_load_retry_0 ? mem_ldq_retry_e_out_bits_uop_xcpt_pf_if : _exe_tlb_uop_T_4_xcpt_pf_if; // @[util.scala:106:23] wire _exe_tlb_uop_T_5_xcpt_ae_if = will_fire_load_retry_0 ? mem_ldq_retry_e_out_bits_uop_xcpt_ae_if : _exe_tlb_uop_T_4_xcpt_ae_if; // @[util.scala:106:23] wire _exe_tlb_uop_T_5_xcpt_ma_if = will_fire_load_retry_0 ? mem_ldq_retry_e_out_bits_uop_xcpt_ma_if : _exe_tlb_uop_T_4_xcpt_ma_if; // @[util.scala:106:23] wire _exe_tlb_uop_T_5_bp_debug_if = will_fire_load_retry_0 ? mem_ldq_retry_e_out_bits_uop_bp_debug_if : _exe_tlb_uop_T_4_bp_debug_if; // @[util.scala:106:23] wire _exe_tlb_uop_T_5_bp_xcpt_if = will_fire_load_retry_0 ? mem_ldq_retry_e_out_bits_uop_bp_xcpt_if : _exe_tlb_uop_T_4_bp_xcpt_if; // @[util.scala:106:23] wire [1:0] _exe_tlb_uop_T_5_debug_fsrc = will_fire_load_retry_0 ? mem_ldq_retry_e_out_bits_uop_debug_fsrc : _exe_tlb_uop_T_4_debug_fsrc; // @[util.scala:106:23] wire [1:0] _exe_tlb_uop_T_5_debug_tsrc = will_fire_load_retry_0 ? mem_ldq_retry_e_out_bits_uop_debug_tsrc : _exe_tlb_uop_T_4_debug_tsrc; // @[util.scala:106:23] wire [6:0] _exe_tlb_uop_T_6_uopc = _exe_tlb_uop_T_2 ? exe_req_0_bits_uop_uopc : _exe_tlb_uop_T_5_uopc; // @[lsu.scala:383:25, :596:24, :598:53, :600:24] wire [31:0] _exe_tlb_uop_T_6_inst = _exe_tlb_uop_T_2 ? exe_req_0_bits_uop_inst : _exe_tlb_uop_T_5_inst; // @[lsu.scala:383:25, :596:24, :598:53, :600:24] wire [31:0] _exe_tlb_uop_T_6_debug_inst = _exe_tlb_uop_T_2 ? exe_req_0_bits_uop_debug_inst : _exe_tlb_uop_T_5_debug_inst; // @[lsu.scala:383:25, :596:24, :598:53, :600:24] wire _exe_tlb_uop_T_6_is_rvc = _exe_tlb_uop_T_2 ? exe_req_0_bits_uop_is_rvc : _exe_tlb_uop_T_5_is_rvc; // @[lsu.scala:383:25, :596:24, :598:53, :600:24] wire [39:0] _exe_tlb_uop_T_6_debug_pc = _exe_tlb_uop_T_2 ? exe_req_0_bits_uop_debug_pc : _exe_tlb_uop_T_5_debug_pc; // @[lsu.scala:383:25, :596:24, :598:53, :600:24] wire [2:0] _exe_tlb_uop_T_6_iq_type = _exe_tlb_uop_T_2 ? exe_req_0_bits_uop_iq_type : _exe_tlb_uop_T_5_iq_type; // @[lsu.scala:383:25, :596:24, :598:53, :600:24] wire [9:0] _exe_tlb_uop_T_6_fu_code = _exe_tlb_uop_T_2 ? exe_req_0_bits_uop_fu_code : _exe_tlb_uop_T_5_fu_code; // @[lsu.scala:383:25, :596:24, :598:53, :600:24] wire [3:0] _exe_tlb_uop_T_6_ctrl_br_type = _exe_tlb_uop_T_2 ? exe_req_0_bits_uop_ctrl_br_type : _exe_tlb_uop_T_5_ctrl_br_type; // @[lsu.scala:383:25, :596:24, :598:53, :600:24] wire [1:0] _exe_tlb_uop_T_6_ctrl_op1_sel = _exe_tlb_uop_T_2 ? exe_req_0_bits_uop_ctrl_op1_sel : _exe_tlb_uop_T_5_ctrl_op1_sel; // @[lsu.scala:383:25, :596:24, :598:53, :600:24] wire [2:0] _exe_tlb_uop_T_6_ctrl_op2_sel = _exe_tlb_uop_T_2 ? exe_req_0_bits_uop_ctrl_op2_sel : _exe_tlb_uop_T_5_ctrl_op2_sel; // @[lsu.scala:383:25, :596:24, :598:53, :600:24] wire [2:0] _exe_tlb_uop_T_6_ctrl_imm_sel = _exe_tlb_uop_T_2 ? exe_req_0_bits_uop_ctrl_imm_sel : _exe_tlb_uop_T_5_ctrl_imm_sel; // @[lsu.scala:383:25, :596:24, :598:53, :600:24] wire [4:0] _exe_tlb_uop_T_6_ctrl_op_fcn = _exe_tlb_uop_T_2 ? exe_req_0_bits_uop_ctrl_op_fcn : _exe_tlb_uop_T_5_ctrl_op_fcn; // @[lsu.scala:383:25, :596:24, :598:53, :600:24] wire _exe_tlb_uop_T_6_ctrl_fcn_dw = _exe_tlb_uop_T_2 ? exe_req_0_bits_uop_ctrl_fcn_dw : _exe_tlb_uop_T_5_ctrl_fcn_dw; // @[lsu.scala:383:25, :596:24, :598:53, :600:24] wire [2:0] _exe_tlb_uop_T_6_ctrl_csr_cmd = _exe_tlb_uop_T_2 ? exe_req_0_bits_uop_ctrl_csr_cmd : _exe_tlb_uop_T_5_ctrl_csr_cmd; // @[lsu.scala:383:25, :596:24, :598:53, :600:24] wire _exe_tlb_uop_T_6_ctrl_is_load = _exe_tlb_uop_T_2 ? exe_req_0_bits_uop_ctrl_is_load : _exe_tlb_uop_T_5_ctrl_is_load; // @[lsu.scala:383:25, :596:24, :598:53, :600:24] wire _exe_tlb_uop_T_6_ctrl_is_sta = _exe_tlb_uop_T_2 ? exe_req_0_bits_uop_ctrl_is_sta : _exe_tlb_uop_T_5_ctrl_is_sta; // @[lsu.scala:383:25, :596:24, :598:53, :600:24] wire _exe_tlb_uop_T_6_ctrl_is_std = _exe_tlb_uop_T_2 ? exe_req_0_bits_uop_ctrl_is_std : _exe_tlb_uop_T_5_ctrl_is_std; // @[lsu.scala:383:25, :596:24, :598:53, :600:24] wire [1:0] _exe_tlb_uop_T_6_iw_state = _exe_tlb_uop_T_2 ? exe_req_0_bits_uop_iw_state : _exe_tlb_uop_T_5_iw_state; // @[lsu.scala:383:25, :596:24, :598:53, :600:24] wire _exe_tlb_uop_T_6_iw_p1_poisoned = _exe_tlb_uop_T_2 ? exe_req_0_bits_uop_iw_p1_poisoned : _exe_tlb_uop_T_5_iw_p1_poisoned; // @[lsu.scala:383:25, :596:24, :598:53, :600:24] wire _exe_tlb_uop_T_6_iw_p2_poisoned = _exe_tlb_uop_T_2 ? exe_req_0_bits_uop_iw_p2_poisoned : _exe_tlb_uop_T_5_iw_p2_poisoned; // @[lsu.scala:383:25, :596:24, :598:53, :600:24] wire _exe_tlb_uop_T_6_is_br = _exe_tlb_uop_T_2 ? exe_req_0_bits_uop_is_br : _exe_tlb_uop_T_5_is_br; // @[lsu.scala:383:25, :596:24, :598:53, :600:24] wire _exe_tlb_uop_T_6_is_jalr = _exe_tlb_uop_T_2 ? exe_req_0_bits_uop_is_jalr : _exe_tlb_uop_T_5_is_jalr; // @[lsu.scala:383:25, :596:24, :598:53, :600:24] wire _exe_tlb_uop_T_6_is_jal = _exe_tlb_uop_T_2 ? exe_req_0_bits_uop_is_jal : _exe_tlb_uop_T_5_is_jal; // @[lsu.scala:383:25, :596:24, :598:53, :600:24] wire _exe_tlb_uop_T_6_is_sfb = _exe_tlb_uop_T_2 ? exe_req_0_bits_uop_is_sfb : _exe_tlb_uop_T_5_is_sfb; // @[lsu.scala:383:25, :596:24, :598:53, :600:24] wire [7:0] _exe_tlb_uop_T_6_br_mask = _exe_tlb_uop_T_2 ? exe_req_0_bits_uop_br_mask : _exe_tlb_uop_T_5_br_mask; // @[lsu.scala:383:25, :596:24, :598:53, :600:24] wire [2:0] _exe_tlb_uop_T_6_br_tag = _exe_tlb_uop_T_2 ? exe_req_0_bits_uop_br_tag : _exe_tlb_uop_T_5_br_tag; // @[lsu.scala:383:25, :596:24, :598:53, :600:24] wire [3:0] _exe_tlb_uop_T_6_ftq_idx = _exe_tlb_uop_T_2 ? exe_req_0_bits_uop_ftq_idx : _exe_tlb_uop_T_5_ftq_idx; // @[lsu.scala:383:25, :596:24, :598:53, :600:24] wire _exe_tlb_uop_T_6_edge_inst = _exe_tlb_uop_T_2 ? exe_req_0_bits_uop_edge_inst : _exe_tlb_uop_T_5_edge_inst; // @[lsu.scala:383:25, :596:24, :598:53, :600:24] wire [5:0] _exe_tlb_uop_T_6_pc_lob = _exe_tlb_uop_T_2 ? exe_req_0_bits_uop_pc_lob : _exe_tlb_uop_T_5_pc_lob; // @[lsu.scala:383:25, :596:24, :598:53, :600:24] wire _exe_tlb_uop_T_6_taken = _exe_tlb_uop_T_2 ? exe_req_0_bits_uop_taken : _exe_tlb_uop_T_5_taken; // @[lsu.scala:383:25, :596:24, :598:53, :600:24] wire [19:0] _exe_tlb_uop_T_6_imm_packed = _exe_tlb_uop_T_2 ? exe_req_0_bits_uop_imm_packed : _exe_tlb_uop_T_5_imm_packed; // @[lsu.scala:383:25, :596:24, :598:53, :600:24] wire [11:0] _exe_tlb_uop_T_6_csr_addr = _exe_tlb_uop_T_2 ? exe_req_0_bits_uop_csr_addr : _exe_tlb_uop_T_5_csr_addr; // @[lsu.scala:383:25, :596:24, :598:53, :600:24] wire [4:0] _exe_tlb_uop_T_6_rob_idx = _exe_tlb_uop_T_2 ? exe_req_0_bits_uop_rob_idx : _exe_tlb_uop_T_5_rob_idx; // @[lsu.scala:383:25, :596:24, :598:53, :600:24] wire [2:0] _exe_tlb_uop_T_6_ldq_idx = _exe_tlb_uop_T_2 ? exe_req_0_bits_uop_ldq_idx : _exe_tlb_uop_T_5_ldq_idx; // @[lsu.scala:383:25, :596:24, :598:53, :600:24] wire [2:0] _exe_tlb_uop_T_6_stq_idx = _exe_tlb_uop_T_2 ? exe_req_0_bits_uop_stq_idx : _exe_tlb_uop_T_5_stq_idx; // @[lsu.scala:383:25, :596:24, :598:53, :600:24] wire [1:0] _exe_tlb_uop_T_6_rxq_idx = _exe_tlb_uop_T_2 ? exe_req_0_bits_uop_rxq_idx : _exe_tlb_uop_T_5_rxq_idx; // @[lsu.scala:383:25, :596:24, :598:53, :600:24] wire [5:0] _exe_tlb_uop_T_6_pdst = _exe_tlb_uop_T_2 ? exe_req_0_bits_uop_pdst : _exe_tlb_uop_T_5_pdst; // @[lsu.scala:383:25, :596:24, :598:53, :600:24] wire [5:0] _exe_tlb_uop_T_6_prs1 = _exe_tlb_uop_T_2 ? exe_req_0_bits_uop_prs1 : _exe_tlb_uop_T_5_prs1; // @[lsu.scala:383:25, :596:24, :598:53, :600:24] wire [5:0] _exe_tlb_uop_T_6_prs2 = _exe_tlb_uop_T_2 ? exe_req_0_bits_uop_prs2 : _exe_tlb_uop_T_5_prs2; // @[lsu.scala:383:25, :596:24, :598:53, :600:24] wire [5:0] _exe_tlb_uop_T_6_prs3 = _exe_tlb_uop_T_2 ? exe_req_0_bits_uop_prs3 : _exe_tlb_uop_T_5_prs3; // @[lsu.scala:383:25, :596:24, :598:53, :600:24] wire [3:0] _exe_tlb_uop_T_6_ppred = _exe_tlb_uop_T_2 ? exe_req_0_bits_uop_ppred : _exe_tlb_uop_T_5_ppred; // @[lsu.scala:383:25, :596:24, :598:53, :600:24] wire _exe_tlb_uop_T_6_prs1_busy = _exe_tlb_uop_T_2 ? exe_req_0_bits_uop_prs1_busy : _exe_tlb_uop_T_5_prs1_busy; // @[lsu.scala:383:25, :596:24, :598:53, :600:24] wire _exe_tlb_uop_T_6_prs2_busy = _exe_tlb_uop_T_2 ? exe_req_0_bits_uop_prs2_busy : _exe_tlb_uop_T_5_prs2_busy; // @[lsu.scala:383:25, :596:24, :598:53, :600:24] wire _exe_tlb_uop_T_6_prs3_busy = _exe_tlb_uop_T_2 ? exe_req_0_bits_uop_prs3_busy : _exe_tlb_uop_T_5_prs3_busy; // @[lsu.scala:383:25, :596:24, :598:53, :600:24] wire _exe_tlb_uop_T_6_ppred_busy = _exe_tlb_uop_T_2 ? exe_req_0_bits_uop_ppred_busy : _exe_tlb_uop_T_5_ppred_busy; // @[lsu.scala:383:25, :596:24, :598:53, :600:24] wire [5:0] _exe_tlb_uop_T_6_stale_pdst = _exe_tlb_uop_T_2 ? exe_req_0_bits_uop_stale_pdst : _exe_tlb_uop_T_5_stale_pdst; // @[lsu.scala:383:25, :596:24, :598:53, :600:24] wire _exe_tlb_uop_T_6_exception = _exe_tlb_uop_T_2 ? exe_req_0_bits_uop_exception : _exe_tlb_uop_T_5_exception; // @[lsu.scala:383:25, :596:24, :598:53, :600:24] wire [63:0] _exe_tlb_uop_T_6_exc_cause = _exe_tlb_uop_T_2 ? exe_req_0_bits_uop_exc_cause : _exe_tlb_uop_T_5_exc_cause; // @[lsu.scala:383:25, :596:24, :598:53, :600:24] wire _exe_tlb_uop_T_6_bypassable = _exe_tlb_uop_T_2 ? exe_req_0_bits_uop_bypassable : _exe_tlb_uop_T_5_bypassable; // @[lsu.scala:383:25, :596:24, :598:53, :600:24] wire [4:0] _exe_tlb_uop_T_6_mem_cmd = _exe_tlb_uop_T_2 ? exe_req_0_bits_uop_mem_cmd : _exe_tlb_uop_T_5_mem_cmd; // @[lsu.scala:383:25, :596:24, :598:53, :600:24] wire [1:0] _exe_tlb_uop_T_6_mem_size = _exe_tlb_uop_T_2 ? exe_req_0_bits_uop_mem_size : _exe_tlb_uop_T_5_mem_size; // @[lsu.scala:383:25, :596:24, :598:53, :600:24] wire _exe_tlb_uop_T_6_mem_signed = _exe_tlb_uop_T_2 ? exe_req_0_bits_uop_mem_signed : _exe_tlb_uop_T_5_mem_signed; // @[lsu.scala:383:25, :596:24, :598:53, :600:24] wire _exe_tlb_uop_T_6_is_fence = _exe_tlb_uop_T_2 ? exe_req_0_bits_uop_is_fence : _exe_tlb_uop_T_5_is_fence; // @[lsu.scala:383:25, :596:24, :598:53, :600:24] wire _exe_tlb_uop_T_6_is_fencei = _exe_tlb_uop_T_2 ? exe_req_0_bits_uop_is_fencei : _exe_tlb_uop_T_5_is_fencei; // @[lsu.scala:383:25, :596:24, :598:53, :600:24] wire _exe_tlb_uop_T_6_is_amo = _exe_tlb_uop_T_2 ? exe_req_0_bits_uop_is_amo : _exe_tlb_uop_T_5_is_amo; // @[lsu.scala:383:25, :596:24, :598:53, :600:24] wire _exe_tlb_uop_T_6_uses_ldq = _exe_tlb_uop_T_2 ? exe_req_0_bits_uop_uses_ldq : _exe_tlb_uop_T_5_uses_ldq; // @[lsu.scala:383:25, :596:24, :598:53, :600:24] wire _exe_tlb_uop_T_6_uses_stq = _exe_tlb_uop_T_2 ? exe_req_0_bits_uop_uses_stq : _exe_tlb_uop_T_5_uses_stq; // @[lsu.scala:383:25, :596:24, :598:53, :600:24] wire _exe_tlb_uop_T_6_is_sys_pc2epc = _exe_tlb_uop_T_2 ? exe_req_0_bits_uop_is_sys_pc2epc : _exe_tlb_uop_T_5_is_sys_pc2epc; // @[lsu.scala:383:25, :596:24, :598:53, :600:24] wire _exe_tlb_uop_T_6_is_unique = _exe_tlb_uop_T_2 ? exe_req_0_bits_uop_is_unique : _exe_tlb_uop_T_5_is_unique; // @[lsu.scala:383:25, :596:24, :598:53, :600:24] wire _exe_tlb_uop_T_6_flush_on_commit = _exe_tlb_uop_T_2 ? exe_req_0_bits_uop_flush_on_commit : _exe_tlb_uop_T_5_flush_on_commit; // @[lsu.scala:383:25, :596:24, :598:53, :600:24] wire _exe_tlb_uop_T_6_ldst_is_rs1 = _exe_tlb_uop_T_2 ? exe_req_0_bits_uop_ldst_is_rs1 : _exe_tlb_uop_T_5_ldst_is_rs1; // @[lsu.scala:383:25, :596:24, :598:53, :600:24] wire [5:0] _exe_tlb_uop_T_6_ldst = _exe_tlb_uop_T_2 ? exe_req_0_bits_uop_ldst : _exe_tlb_uop_T_5_ldst; // @[lsu.scala:383:25, :596:24, :598:53, :600:24] wire [5:0] _exe_tlb_uop_T_6_lrs1 = _exe_tlb_uop_T_2 ? exe_req_0_bits_uop_lrs1 : _exe_tlb_uop_T_5_lrs1; // @[lsu.scala:383:25, :596:24, :598:53, :600:24] wire [5:0] _exe_tlb_uop_T_6_lrs2 = _exe_tlb_uop_T_2 ? exe_req_0_bits_uop_lrs2 : _exe_tlb_uop_T_5_lrs2; // @[lsu.scala:383:25, :596:24, :598:53, :600:24] wire [5:0] _exe_tlb_uop_T_6_lrs3 = _exe_tlb_uop_T_2 ? exe_req_0_bits_uop_lrs3 : _exe_tlb_uop_T_5_lrs3; // @[lsu.scala:383:25, :596:24, :598:53, :600:24] wire _exe_tlb_uop_T_6_ldst_val = _exe_tlb_uop_T_2 ? exe_req_0_bits_uop_ldst_val : _exe_tlb_uop_T_5_ldst_val; // @[lsu.scala:383:25, :596:24, :598:53, :600:24] wire [1:0] _exe_tlb_uop_T_6_dst_rtype = _exe_tlb_uop_T_2 ? exe_req_0_bits_uop_dst_rtype : _exe_tlb_uop_T_5_dst_rtype; // @[lsu.scala:383:25, :596:24, :598:53, :600:24] wire [1:0] _exe_tlb_uop_T_6_lrs1_rtype = _exe_tlb_uop_T_2 ? exe_req_0_bits_uop_lrs1_rtype : _exe_tlb_uop_T_5_lrs1_rtype; // @[lsu.scala:383:25, :596:24, :598:53, :600:24] wire [1:0] _exe_tlb_uop_T_6_lrs2_rtype = _exe_tlb_uop_T_2 ? exe_req_0_bits_uop_lrs2_rtype : _exe_tlb_uop_T_5_lrs2_rtype; // @[lsu.scala:383:25, :596:24, :598:53, :600:24] wire _exe_tlb_uop_T_6_frs3_en = _exe_tlb_uop_T_2 ? exe_req_0_bits_uop_frs3_en : _exe_tlb_uop_T_5_frs3_en; // @[lsu.scala:383:25, :596:24, :598:53, :600:24] wire _exe_tlb_uop_T_6_fp_val = _exe_tlb_uop_T_2 ? exe_req_0_bits_uop_fp_val : _exe_tlb_uop_T_5_fp_val; // @[lsu.scala:383:25, :596:24, :598:53, :600:24] wire _exe_tlb_uop_T_6_fp_single = _exe_tlb_uop_T_2 ? exe_req_0_bits_uop_fp_single : _exe_tlb_uop_T_5_fp_single; // @[lsu.scala:383:25, :596:24, :598:53, :600:24] wire _exe_tlb_uop_T_6_xcpt_pf_if = _exe_tlb_uop_T_2 ? exe_req_0_bits_uop_xcpt_pf_if : _exe_tlb_uop_T_5_xcpt_pf_if; // @[lsu.scala:383:25, :596:24, :598:53, :600:24] wire _exe_tlb_uop_T_6_xcpt_ae_if = _exe_tlb_uop_T_2 ? exe_req_0_bits_uop_xcpt_ae_if : _exe_tlb_uop_T_5_xcpt_ae_if; // @[lsu.scala:383:25, :596:24, :598:53, :600:24] wire _exe_tlb_uop_T_6_xcpt_ma_if = _exe_tlb_uop_T_2 ? exe_req_0_bits_uop_xcpt_ma_if : _exe_tlb_uop_T_5_xcpt_ma_if; // @[lsu.scala:383:25, :596:24, :598:53, :600:24] wire _exe_tlb_uop_T_6_bp_debug_if = _exe_tlb_uop_T_2 ? exe_req_0_bits_uop_bp_debug_if : _exe_tlb_uop_T_5_bp_debug_if; // @[lsu.scala:383:25, :596:24, :598:53, :600:24] wire _exe_tlb_uop_T_6_bp_xcpt_if = _exe_tlb_uop_T_2 ? exe_req_0_bits_uop_bp_xcpt_if : _exe_tlb_uop_T_5_bp_xcpt_if; // @[lsu.scala:383:25, :596:24, :598:53, :600:24] wire [1:0] _exe_tlb_uop_T_6_debug_fsrc = _exe_tlb_uop_T_2 ? exe_req_0_bits_uop_debug_fsrc : _exe_tlb_uop_T_5_debug_fsrc; // @[lsu.scala:383:25, :596:24, :598:53, :600:24] wire [1:0] _exe_tlb_uop_T_6_debug_tsrc = _exe_tlb_uop_T_2 ? exe_req_0_bits_uop_debug_tsrc : _exe_tlb_uop_T_5_debug_tsrc; // @[lsu.scala:383:25, :596:24, :598:53, :600:24] wire [6:0] exe_tlb_uop_0_uopc = _exe_tlb_uop_T_6_uopc; // @[lsu.scala:263:49, :596:24] wire [31:0] exe_tlb_uop_0_inst = _exe_tlb_uop_T_6_inst; // @[lsu.scala:263:49, :596:24] wire [31:0] exe_tlb_uop_0_debug_inst = _exe_tlb_uop_T_6_debug_inst; // @[lsu.scala:263:49, :596:24] wire exe_tlb_uop_0_is_rvc = _exe_tlb_uop_T_6_is_rvc; // @[lsu.scala:263:49, :596:24] wire [39:0] exe_tlb_uop_0_debug_pc = _exe_tlb_uop_T_6_debug_pc; // @[lsu.scala:263:49, :596:24] wire [2:0] exe_tlb_uop_0_iq_type = _exe_tlb_uop_T_6_iq_type; // @[lsu.scala:263:49, :596:24] wire [9:0] exe_tlb_uop_0_fu_code = _exe_tlb_uop_T_6_fu_code; // @[lsu.scala:263:49, :596:24] wire [3:0] exe_tlb_uop_0_ctrl_br_type = _exe_tlb_uop_T_6_ctrl_br_type; // @[lsu.scala:263:49, :596:24] wire [1:0] exe_tlb_uop_0_ctrl_op1_sel = _exe_tlb_uop_T_6_ctrl_op1_sel; // @[lsu.scala:263:49, :596:24] wire [2:0] exe_tlb_uop_0_ctrl_op2_sel = _exe_tlb_uop_T_6_ctrl_op2_sel; // @[lsu.scala:263:49, :596:24] wire [2:0] exe_tlb_uop_0_ctrl_imm_sel = _exe_tlb_uop_T_6_ctrl_imm_sel; // @[lsu.scala:263:49, :596:24] wire [4:0] exe_tlb_uop_0_ctrl_op_fcn = _exe_tlb_uop_T_6_ctrl_op_fcn; // @[lsu.scala:263:49, :596:24] wire exe_tlb_uop_0_ctrl_fcn_dw = _exe_tlb_uop_T_6_ctrl_fcn_dw; // @[lsu.scala:263:49, :596:24] wire [2:0] exe_tlb_uop_0_ctrl_csr_cmd = _exe_tlb_uop_T_6_ctrl_csr_cmd; // @[lsu.scala:263:49, :596:24] wire exe_tlb_uop_0_ctrl_is_load = _exe_tlb_uop_T_6_ctrl_is_load; // @[lsu.scala:263:49, :596:24] wire exe_tlb_uop_0_ctrl_is_sta = _exe_tlb_uop_T_6_ctrl_is_sta; // @[lsu.scala:263:49, :596:24] wire exe_tlb_uop_0_ctrl_is_std = _exe_tlb_uop_T_6_ctrl_is_std; // @[lsu.scala:263:49, :596:24] wire [1:0] exe_tlb_uop_0_iw_state = _exe_tlb_uop_T_6_iw_state; // @[lsu.scala:263:49, :596:24] wire exe_tlb_uop_0_iw_p1_poisoned = _exe_tlb_uop_T_6_iw_p1_poisoned; // @[lsu.scala:263:49, :596:24] wire exe_tlb_uop_0_iw_p2_poisoned = _exe_tlb_uop_T_6_iw_p2_poisoned; // @[lsu.scala:263:49, :596:24] wire exe_tlb_uop_0_is_br = _exe_tlb_uop_T_6_is_br; // @[lsu.scala:263:49, :596:24] wire exe_tlb_uop_0_is_jalr = _exe_tlb_uop_T_6_is_jalr; // @[lsu.scala:263:49, :596:24] wire exe_tlb_uop_0_is_jal = _exe_tlb_uop_T_6_is_jal; // @[lsu.scala:263:49, :596:24] wire exe_tlb_uop_0_is_sfb = _exe_tlb_uop_T_6_is_sfb; // @[lsu.scala:263:49, :596:24] wire [7:0] exe_tlb_uop_0_br_mask = _exe_tlb_uop_T_6_br_mask; // @[lsu.scala:263:49, :596:24] wire [2:0] exe_tlb_uop_0_br_tag = _exe_tlb_uop_T_6_br_tag; // @[lsu.scala:263:49, :596:24] wire [3:0] exe_tlb_uop_0_ftq_idx = _exe_tlb_uop_T_6_ftq_idx; // @[lsu.scala:263:49, :596:24] wire exe_tlb_uop_0_edge_inst = _exe_tlb_uop_T_6_edge_inst; // @[lsu.scala:263:49, :596:24] wire [5:0] exe_tlb_uop_0_pc_lob = _exe_tlb_uop_T_6_pc_lob; // @[lsu.scala:263:49, :596:24] wire exe_tlb_uop_0_taken = _exe_tlb_uop_T_6_taken; // @[lsu.scala:263:49, :596:24] wire [19:0] exe_tlb_uop_0_imm_packed = _exe_tlb_uop_T_6_imm_packed; // @[lsu.scala:263:49, :596:24] wire [11:0] exe_tlb_uop_0_csr_addr = _exe_tlb_uop_T_6_csr_addr; // @[lsu.scala:263:49, :596:24] wire [4:0] exe_tlb_uop_0_rob_idx = _exe_tlb_uop_T_6_rob_idx; // @[lsu.scala:263:49, :596:24] wire [2:0] exe_tlb_uop_0_ldq_idx = _exe_tlb_uop_T_6_ldq_idx; // @[lsu.scala:263:49, :596:24] wire [2:0] exe_tlb_uop_0_stq_idx = _exe_tlb_uop_T_6_stq_idx; // @[lsu.scala:263:49, :596:24] wire [1:0] exe_tlb_uop_0_rxq_idx = _exe_tlb_uop_T_6_rxq_idx; // @[lsu.scala:263:49, :596:24] wire [5:0] exe_tlb_uop_0_pdst = _exe_tlb_uop_T_6_pdst; // @[lsu.scala:263:49, :596:24] wire [5:0] exe_tlb_uop_0_prs1 = _exe_tlb_uop_T_6_prs1; // @[lsu.scala:263:49, :596:24] wire [5:0] exe_tlb_uop_0_prs2 = _exe_tlb_uop_T_6_prs2; // @[lsu.scala:263:49, :596:24] wire [5:0] exe_tlb_uop_0_prs3 = _exe_tlb_uop_T_6_prs3; // @[lsu.scala:263:49, :596:24] wire [3:0] exe_tlb_uop_0_ppred = _exe_tlb_uop_T_6_ppred; // @[lsu.scala:263:49, :596:24] wire exe_tlb_uop_0_prs1_busy = _exe_tlb_uop_T_6_prs1_busy; // @[lsu.scala:263:49, :596:24] wire exe_tlb_uop_0_prs2_busy = _exe_tlb_uop_T_6_prs2_busy; // @[lsu.scala:263:49, :596:24] wire exe_tlb_uop_0_prs3_busy = _exe_tlb_uop_T_6_prs3_busy; // @[lsu.scala:263:49, :596:24] wire exe_tlb_uop_0_ppred_busy = _exe_tlb_uop_T_6_ppred_busy; // @[lsu.scala:263:49, :596:24] wire [5:0] exe_tlb_uop_0_stale_pdst = _exe_tlb_uop_T_6_stale_pdst; // @[lsu.scala:263:49, :596:24] wire exe_tlb_uop_0_exception = _exe_tlb_uop_T_6_exception; // @[lsu.scala:263:49, :596:24] wire [63:0] exe_tlb_uop_0_exc_cause = _exe_tlb_uop_T_6_exc_cause; // @[lsu.scala:263:49, :596:24] wire exe_tlb_uop_0_bypassable = _exe_tlb_uop_T_6_bypassable; // @[lsu.scala:263:49, :596:24] wire [4:0] exe_tlb_uop_0_mem_cmd = _exe_tlb_uop_T_6_mem_cmd; // @[lsu.scala:263:49, :596:24] wire [1:0] exe_tlb_uop_0_mem_size = _exe_tlb_uop_T_6_mem_size; // @[lsu.scala:263:49, :596:24] wire exe_tlb_uop_0_mem_signed = _exe_tlb_uop_T_6_mem_signed; // @[lsu.scala:263:49, :596:24] wire exe_tlb_uop_0_is_fence = _exe_tlb_uop_T_6_is_fence; // @[lsu.scala:263:49, :596:24] wire exe_tlb_uop_0_is_fencei = _exe_tlb_uop_T_6_is_fencei; // @[lsu.scala:263:49, :596:24] wire exe_tlb_uop_0_is_amo = _exe_tlb_uop_T_6_is_amo; // @[lsu.scala:263:49, :596:24] wire exe_tlb_uop_0_uses_ldq = _exe_tlb_uop_T_6_uses_ldq; // @[lsu.scala:263:49, :596:24] wire exe_tlb_uop_0_uses_stq = _exe_tlb_uop_T_6_uses_stq; // @[lsu.scala:263:49, :596:24] wire exe_tlb_uop_0_is_sys_pc2epc = _exe_tlb_uop_T_6_is_sys_pc2epc; // @[lsu.scala:263:49, :596:24] wire exe_tlb_uop_0_is_unique = _exe_tlb_uop_T_6_is_unique; // @[lsu.scala:263:49, :596:24] wire exe_tlb_uop_0_flush_on_commit = _exe_tlb_uop_T_6_flush_on_commit; // @[lsu.scala:263:49, :596:24] wire exe_tlb_uop_0_ldst_is_rs1 = _exe_tlb_uop_T_6_ldst_is_rs1; // @[lsu.scala:263:49, :596:24] wire [5:0] exe_tlb_uop_0_ldst = _exe_tlb_uop_T_6_ldst; // @[lsu.scala:263:49, :596:24] wire [5:0] exe_tlb_uop_0_lrs1 = _exe_tlb_uop_T_6_lrs1; // @[lsu.scala:263:49, :596:24] wire [5:0] exe_tlb_uop_0_lrs2 = _exe_tlb_uop_T_6_lrs2; // @[lsu.scala:263:49, :596:24] wire [5:0] exe_tlb_uop_0_lrs3 = _exe_tlb_uop_T_6_lrs3; // @[lsu.scala:263:49, :596:24] wire exe_tlb_uop_0_ldst_val = _exe_tlb_uop_T_6_ldst_val; // @[lsu.scala:263:49, :596:24] wire [1:0] exe_tlb_uop_0_dst_rtype = _exe_tlb_uop_T_6_dst_rtype; // @[lsu.scala:263:49, :596:24] wire [1:0] exe_tlb_uop_0_lrs1_rtype = _exe_tlb_uop_T_6_lrs1_rtype; // @[lsu.scala:263:49, :596:24] wire [1:0] exe_tlb_uop_0_lrs2_rtype = _exe_tlb_uop_T_6_lrs2_rtype; // @[lsu.scala:263:49, :596:24] wire exe_tlb_uop_0_frs3_en = _exe_tlb_uop_T_6_frs3_en; // @[lsu.scala:263:49, :596:24] wire exe_tlb_uop_0_fp_val = _exe_tlb_uop_T_6_fp_val; // @[lsu.scala:263:49, :596:24] wire exe_tlb_uop_0_fp_single = _exe_tlb_uop_T_6_fp_single; // @[lsu.scala:263:49, :596:24] wire exe_tlb_uop_0_xcpt_pf_if = _exe_tlb_uop_T_6_xcpt_pf_if; // @[lsu.scala:263:49, :596:24] wire exe_tlb_uop_0_xcpt_ae_if = _exe_tlb_uop_T_6_xcpt_ae_if; // @[lsu.scala:263:49, :596:24] wire exe_tlb_uop_0_xcpt_ma_if = _exe_tlb_uop_T_6_xcpt_ma_if; // @[lsu.scala:263:49, :596:24] wire exe_tlb_uop_0_bp_debug_if = _exe_tlb_uop_T_6_bp_debug_if; // @[lsu.scala:263:49, :596:24] wire exe_tlb_uop_0_bp_xcpt_if = _exe_tlb_uop_T_6_bp_xcpt_if; // @[lsu.scala:263:49, :596:24] wire [1:0] exe_tlb_uop_0_debug_fsrc = _exe_tlb_uop_T_6_debug_fsrc; // @[lsu.scala:263:49, :596:24] wire [1:0] exe_tlb_uop_0_debug_tsrc = _exe_tlb_uop_T_6_debug_tsrc; // @[lsu.scala:263:49, :596:24] wire [6:0] mem_xcpt_uops_out_uopc = exe_tlb_uop_0_uopc; // @[util.scala:96:23] wire [31:0] mem_xcpt_uops_out_inst = exe_tlb_uop_0_inst; // @[util.scala:96:23] wire [31:0] mem_xcpt_uops_out_debug_inst = exe_tlb_uop_0_debug_inst; // @[util.scala:96:23] wire mem_xcpt_uops_out_is_rvc = exe_tlb_uop_0_is_rvc; // @[util.scala:96:23] wire [39:0] mem_xcpt_uops_out_debug_pc = exe_tlb_uop_0_debug_pc; // @[util.scala:96:23] wire [2:0] mem_xcpt_uops_out_iq_type = exe_tlb_uop_0_iq_type; // @[util.scala:96:23] wire [9:0] mem_xcpt_uops_out_fu_code = exe_tlb_uop_0_fu_code; // @[util.scala:96:23] wire [3:0] mem_xcpt_uops_out_ctrl_br_type = exe_tlb_uop_0_ctrl_br_type; // @[util.scala:96:23] wire [1:0] mem_xcpt_uops_out_ctrl_op1_sel = exe_tlb_uop_0_ctrl_op1_sel; // @[util.scala:96:23] wire [2:0] mem_xcpt_uops_out_ctrl_op2_sel = exe_tlb_uop_0_ctrl_op2_sel; // @[util.scala:96:23] wire [2:0] mem_xcpt_uops_out_ctrl_imm_sel = exe_tlb_uop_0_ctrl_imm_sel; // @[util.scala:96:23] wire [4:0] mem_xcpt_uops_out_ctrl_op_fcn = exe_tlb_uop_0_ctrl_op_fcn; // @[util.scala:96:23] wire mem_xcpt_uops_out_ctrl_fcn_dw = exe_tlb_uop_0_ctrl_fcn_dw; // @[util.scala:96:23] wire [2:0] mem_xcpt_uops_out_ctrl_csr_cmd = exe_tlb_uop_0_ctrl_csr_cmd; // @[util.scala:96:23] wire mem_xcpt_uops_out_ctrl_is_load = exe_tlb_uop_0_ctrl_is_load; // @[util.scala:96:23] wire mem_xcpt_uops_out_ctrl_is_sta = exe_tlb_uop_0_ctrl_is_sta; // @[util.scala:96:23] wire mem_xcpt_uops_out_ctrl_is_std = exe_tlb_uop_0_ctrl_is_std; // @[util.scala:96:23] wire [1:0] mem_xcpt_uops_out_iw_state = exe_tlb_uop_0_iw_state; // @[util.scala:96:23] wire mem_xcpt_uops_out_iw_p1_poisoned = exe_tlb_uop_0_iw_p1_poisoned; // @[util.scala:96:23] wire mem_xcpt_uops_out_iw_p2_poisoned = exe_tlb_uop_0_iw_p2_poisoned; // @[util.scala:96:23] wire mem_xcpt_uops_out_is_br = exe_tlb_uop_0_is_br; // @[util.scala:96:23] wire mem_xcpt_uops_out_is_jalr = exe_tlb_uop_0_is_jalr; // @[util.scala:96:23] wire mem_xcpt_uops_out_is_jal = exe_tlb_uop_0_is_jal; // @[util.scala:96:23] wire mem_xcpt_uops_out_is_sfb = exe_tlb_uop_0_is_sfb; // @[util.scala:96:23] wire [2:0] mem_xcpt_uops_out_br_tag = exe_tlb_uop_0_br_tag; // @[util.scala:96:23] wire [3:0] mem_xcpt_uops_out_ftq_idx = exe_tlb_uop_0_ftq_idx; // @[util.scala:96:23] wire mem_xcpt_uops_out_edge_inst = exe_tlb_uop_0_edge_inst; // @[util.scala:96:23] wire [5:0] mem_xcpt_uops_out_pc_lob = exe_tlb_uop_0_pc_lob; // @[util.scala:96:23] wire mem_xcpt_uops_out_taken = exe_tlb_uop_0_taken; // @[util.scala:96:23] wire [19:0] mem_xcpt_uops_out_imm_packed = exe_tlb_uop_0_imm_packed; // @[util.scala:96:23] wire [11:0] mem_xcpt_uops_out_csr_addr = exe_tlb_uop_0_csr_addr; // @[util.scala:96:23] wire [4:0] mem_xcpt_uops_out_rob_idx = exe_tlb_uop_0_rob_idx; // @[util.scala:96:23] wire [2:0] mem_xcpt_uops_out_ldq_idx = exe_tlb_uop_0_ldq_idx; // @[util.scala:96:23] wire [2:0] mem_xcpt_uops_out_stq_idx = exe_tlb_uop_0_stq_idx; // @[util.scala:96:23] wire [1:0] mem_xcpt_uops_out_rxq_idx = exe_tlb_uop_0_rxq_idx; // @[util.scala:96:23] wire [5:0] mem_xcpt_uops_out_pdst = exe_tlb_uop_0_pdst; // @[util.scala:96:23] wire [5:0] mem_xcpt_uops_out_prs1 = exe_tlb_uop_0_prs1; // @[util.scala:96:23] wire [5:0] mem_xcpt_uops_out_prs2 = exe_tlb_uop_0_prs2; // @[util.scala:96:23] wire [5:0] mem_xcpt_uops_out_prs3 = exe_tlb_uop_0_prs3; // @[util.scala:96:23] wire [3:0] mem_xcpt_uops_out_ppred = exe_tlb_uop_0_ppred; // @[util.scala:96:23] wire mem_xcpt_uops_out_prs1_busy = exe_tlb_uop_0_prs1_busy; // @[util.scala:96:23] wire mem_xcpt_uops_out_prs2_busy = exe_tlb_uop_0_prs2_busy; // @[util.scala:96:23] wire mem_xcpt_uops_out_prs3_busy = exe_tlb_uop_0_prs3_busy; // @[util.scala:96:23] wire mem_xcpt_uops_out_ppred_busy = exe_tlb_uop_0_ppred_busy; // @[util.scala:96:23] wire [5:0] mem_xcpt_uops_out_stale_pdst = exe_tlb_uop_0_stale_pdst; // @[util.scala:96:23] wire mem_xcpt_uops_out_exception = exe_tlb_uop_0_exception; // @[util.scala:96:23] wire [63:0] mem_xcpt_uops_out_exc_cause = exe_tlb_uop_0_exc_cause; // @[util.scala:96:23] wire mem_xcpt_uops_out_bypassable = exe_tlb_uop_0_bypassable; // @[util.scala:96:23] wire [4:0] mem_xcpt_uops_out_mem_cmd = exe_tlb_uop_0_mem_cmd; // @[util.scala:96:23] wire [1:0] mem_xcpt_uops_out_mem_size = exe_tlb_uop_0_mem_size; // @[util.scala:96:23] wire mem_xcpt_uops_out_mem_signed = exe_tlb_uop_0_mem_signed; // @[util.scala:96:23] wire mem_xcpt_uops_out_is_fence = exe_tlb_uop_0_is_fence; // @[util.scala:96:23] wire mem_xcpt_uops_out_is_fencei = exe_tlb_uop_0_is_fencei; // @[util.scala:96:23] wire mem_xcpt_uops_out_is_amo = exe_tlb_uop_0_is_amo; // @[util.scala:96:23] wire mem_xcpt_uops_out_uses_ldq = exe_tlb_uop_0_uses_ldq; // @[util.scala:96:23] wire mem_xcpt_uops_out_uses_stq = exe_tlb_uop_0_uses_stq; // @[util.scala:96:23] wire mem_xcpt_uops_out_is_sys_pc2epc = exe_tlb_uop_0_is_sys_pc2epc; // @[util.scala:96:23] wire mem_xcpt_uops_out_is_unique = exe_tlb_uop_0_is_unique; // @[util.scala:96:23] wire mem_xcpt_uops_out_flush_on_commit = exe_tlb_uop_0_flush_on_commit; // @[util.scala:96:23] wire mem_xcpt_uops_out_ldst_is_rs1 = exe_tlb_uop_0_ldst_is_rs1; // @[util.scala:96:23] wire [5:0] mem_xcpt_uops_out_ldst = exe_tlb_uop_0_ldst; // @[util.scala:96:23] wire [5:0] mem_xcpt_uops_out_lrs1 = exe_tlb_uop_0_lrs1; // @[util.scala:96:23] wire [5:0] mem_xcpt_uops_out_lrs2 = exe_tlb_uop_0_lrs2; // @[util.scala:96:23] wire [5:0] mem_xcpt_uops_out_lrs3 = exe_tlb_uop_0_lrs3; // @[util.scala:96:23] wire mem_xcpt_uops_out_ldst_val = exe_tlb_uop_0_ldst_val; // @[util.scala:96:23] wire [1:0] mem_xcpt_uops_out_dst_rtype = exe_tlb_uop_0_dst_rtype; // @[util.scala:96:23] wire [1:0] mem_xcpt_uops_out_lrs1_rtype = exe_tlb_uop_0_lrs1_rtype; // @[util.scala:96:23] wire [1:0] mem_xcpt_uops_out_lrs2_rtype = exe_tlb_uop_0_lrs2_rtype; // @[util.scala:96:23] wire mem_xcpt_uops_out_frs3_en = exe_tlb_uop_0_frs3_en; // @[util.scala:96:23] wire mem_xcpt_uops_out_fp_val = exe_tlb_uop_0_fp_val; // @[util.scala:96:23] wire mem_xcpt_uops_out_fp_single = exe_tlb_uop_0_fp_single; // @[util.scala:96:23] wire mem_xcpt_uops_out_xcpt_pf_if = exe_tlb_uop_0_xcpt_pf_if; // @[util.scala:96:23] wire mem_xcpt_uops_out_xcpt_ae_if = exe_tlb_uop_0_xcpt_ae_if; // @[util.scala:96:23] wire mem_xcpt_uops_out_xcpt_ma_if = exe_tlb_uop_0_xcpt_ma_if; // @[util.scala:96:23] wire mem_xcpt_uops_out_bp_debug_if = exe_tlb_uop_0_bp_debug_if; // @[util.scala:96:23] wire mem_xcpt_uops_out_bp_xcpt_if = exe_tlb_uop_0_bp_xcpt_if; // @[util.scala:96:23] wire [1:0] mem_xcpt_uops_out_debug_fsrc = exe_tlb_uop_0_debug_fsrc; // @[util.scala:96:23] wire [1:0] mem_xcpt_uops_out_debug_tsrc = exe_tlb_uop_0_debug_tsrc; // @[util.scala:96:23] wire _exe_tlb_vaddr_T_1 = _exe_tlb_vaddr_T | will_fire_sta_incoming_0; // @[lsu.scala:372:38, :606:53, :607:53] wire [39:0] _exe_tlb_vaddr_T_2 = will_fire_hella_incoming_0 ? hella_req_addr : 40'h0; // @[lsu.scala:241:34, :375:38, :612:24] wire [39:0] _exe_tlb_vaddr_T_3 = will_fire_sta_retry_0 ? mem_stq_retry_e_out_bits_addr_bits : _exe_tlb_vaddr_T_2; // @[util.scala:106:23] wire [39:0] _exe_tlb_vaddr_T_4 = will_fire_load_retry_0 ? mem_ldq_retry_e_out_bits_addr_bits : _exe_tlb_vaddr_T_3; // @[util.scala:106:23] wire [39:0] _exe_tlb_vaddr_T_5 = will_fire_sfence_0 ? {1'h0, exe_req_0_bits_sfence_bits_addr} : _exe_tlb_vaddr_T_4; // @[lsu.scala:374:38, :383:25, :609:24, :610:24] wire [39:0] _exe_tlb_vaddr_T_6 = _exe_tlb_vaddr_T_1 ? exe_req_0_bits_addr : _exe_tlb_vaddr_T_5; // @[lsu.scala:383:25, :606:24, :607:53, :609:24] wire [39:0] exe_tlb_vaddr_0 = _exe_tlb_vaddr_T_6; // @[lsu.scala:263:49, :606:24] wire exe_sfence_bits_rs1; // @[lsu.scala:615:28] wire exe_sfence_bits_rs2; // @[lsu.scala:615:28] wire [38:0] exe_sfence_bits_addr; // @[lsu.scala:615:28] wire exe_sfence_bits_asid; // @[lsu.scala:615:28] wire exe_sfence_valid; // @[lsu.scala:615:28] assign exe_sfence_valid = will_fire_sfence_0 & exe_req_0_bits_sfence_valid; // @[lsu.scala:374:38, :383:25, :615:28, :617:32, :618:18] assign exe_sfence_bits_rs1 = will_fire_sfence_0 & exe_req_0_bits_sfence_bits_rs1; // @[lsu.scala:374:38, :383:25, :615:28, :617:32, :618:18] assign exe_sfence_bits_rs2 = will_fire_sfence_0 & exe_req_0_bits_sfence_bits_rs2; // @[lsu.scala:374:38, :383:25, :615:28, :617:32, :618:18] assign exe_sfence_bits_addr = will_fire_sfence_0 ? exe_req_0_bits_sfence_bits_addr : 39'h0; // @[lsu.scala:374:38, :383:25, :615:28, :617:32, :618:18] assign exe_sfence_bits_asid = will_fire_sfence_0 & exe_req_0_bits_sfence_bits_asid; // @[lsu.scala:374:38, :383:25, :615:28, :617:32, :618:18] wire _exe_size_T_1 = _exe_size_T | will_fire_sta_incoming_0; // @[lsu.scala:372:38, :623:52, :624:52] wire _exe_size_T_2 = _exe_size_T_1 | will_fire_sfence_0; // @[lsu.scala:374:38, :624:52, :625:52] wire _exe_size_T_3 = _exe_size_T_2 | will_fire_load_retry_0; // @[lsu.scala:378:38, :625:52, :626:52] wire _exe_size_T_4 = _exe_size_T_3 | will_fire_sta_retry_0; // @[lsu.scala:379:38, :626:52, :627:52] wire [1:0] _exe_size_T_5 = {2{will_fire_hella_incoming_0}}; // @[lsu.scala:375:38, :629:23] wire [1:0] _exe_size_T_6 = _exe_size_T_4 ? exe_tlb_uop_0_mem_size : _exe_size_T_5; // @[lsu.scala:263:49, :623:23, :627:52, :629:23] wire [1:0] exe_size_0 = _exe_size_T_6; // @[lsu.scala:263:49, :623:23] wire _exe_cmd_T_1 = _exe_cmd_T | will_fire_sta_incoming_0; // @[lsu.scala:372:38, :632:52, :633:52] wire _exe_cmd_T_2 = _exe_cmd_T_1 | will_fire_sfence_0; // @[lsu.scala:374:38, :633:52, :634:52] wire _exe_cmd_T_3 = _exe_cmd_T_2 | will_fire_load_retry_0; // @[lsu.scala:378:38, :634:52, :635:52] wire _exe_cmd_T_4 = _exe_cmd_T_3 | will_fire_sta_retry_0; // @[lsu.scala:379:38, :635:52, :636:52] wire [4:0] _exe_cmd_T_6 = _exe_cmd_T_4 ? exe_tlb_uop_0_mem_cmd : 5'h0; // @[lsu.scala:263:49, :632:23, :636:52] wire [4:0] exe_cmd_0 = _exe_cmd_T_6; // @[lsu.scala:263:49, :632:23] wire exe_passthr_0 = _exe_passthr_T; // @[lsu.scala:263:49, :642:23] wire _exe_kill_T = will_fire_hella_incoming_0 & io_hellacache_s1_kill_0; // @[lsu.scala:201:7, :375:38, :645:23] wire exe_kill_0 = _exe_kill_T; // @[lsu.scala:263:49, :645:23] wire _ma_ld_T = will_fire_load_incoming_0 & exe_req_0_bits_mxcpt_valid; // @[lsu.scala:370:38, :383:25, :660:56] wire ma_ld_0 = _ma_ld_T; // @[lsu.scala:263:49, :660:56] wire _T_162 = will_fire_sta_incoming_0 | will_fire_stad_incoming_0; // @[lsu.scala:371:38, :372:38, :661:56] wire _ma_st_T; // @[lsu.scala:661:56] assign _ma_st_T = _T_162; // @[lsu.scala:661:56] wire _stq_idx_T; // @[lsu.scala:851:51] assign _stq_idx_T = _T_162; // @[lsu.scala:661:56, :851:51] wire _ma_st_T_1 = _ma_st_T & exe_req_0_bits_mxcpt_valid; // @[lsu.scala:383:25, :661:{56,87}] wire ma_st_0 = _ma_st_T_1; // @[lsu.scala:263:49, :661:87] wire _pf_ld_T = exe_tlb_valid_0 & _dtlb_io_resp_0_pf_ld; // @[lsu.scala:247:20, :525:27, :662:50] wire _pf_ld_T_1 = _pf_ld_T & exe_tlb_uop_0_uses_ldq; // @[lsu.scala:263:49, :662:{50,75}] wire pf_ld_0 = _pf_ld_T_1; // @[lsu.scala:263:49, :662:75] wire _pf_st_T = exe_tlb_valid_0 & _dtlb_io_resp_0_pf_st; // @[lsu.scala:247:20, :525:27, :663:50] wire _pf_st_T_1 = _pf_st_T & exe_tlb_uop_0_uses_stq; // @[lsu.scala:263:49, :663:{50,75}] wire pf_st_0 = _pf_st_T_1; // @[lsu.scala:263:49, :663:75] wire _ae_ld_T = exe_tlb_valid_0 & _dtlb_io_resp_0_ae_ld; // @[lsu.scala:247:20, :525:27, :664:50] wire _ae_ld_T_1 = _ae_ld_T & exe_tlb_uop_0_uses_ldq; // @[lsu.scala:263:49, :664:{50,75}] wire ae_ld_0 = _ae_ld_T_1; // @[lsu.scala:263:49, :664:75] wire _ae_st_T = exe_tlb_valid_0 & _dtlb_io_resp_0_ae_st; // @[lsu.scala:247:20, :525:27, :665:50] wire _ae_st_T_1 = _ae_st_T & exe_tlb_uop_0_uses_stq; // @[lsu.scala:263:49, :665:{50,75}] wire ae_st_0 = _ae_st_T_1; // @[lsu.scala:263:49, :665:75] wire _mem_xcpt_valids_T = pf_ld_0 | pf_st_0; // @[lsu.scala:263:49, :669:32] wire _mem_xcpt_valids_T_1 = _mem_xcpt_valids_T | ae_ld_0; // @[lsu.scala:263:49, :669:{32,44}] wire _mem_xcpt_valids_T_2 = _mem_xcpt_valids_T_1 | ae_st_0; // @[lsu.scala:263:49, :669:{44,56}] wire _mem_xcpt_valids_T_3 = _mem_xcpt_valids_T_2 | ma_ld_0; // @[lsu.scala:263:49, :669:{56,68}] wire _mem_xcpt_valids_T_4 = _mem_xcpt_valids_T_3 | ma_st_0; // @[lsu.scala:263:49, :669:{68,80}] wire _mem_xcpt_valids_T_5 = ~io_core_exception_0; // @[lsu.scala:201:7, :670:22] wire _mem_xcpt_valids_T_6 = _mem_xcpt_valids_T_4 & _mem_xcpt_valids_T_5; // @[lsu.scala:669:{80,93}, :670:22] wire [7:0] _mem_xcpt_valids_T_7 = io_core_brupdate_b1_mispredict_mask_0 & exe_tlb_uop_0_br_mask; // @[util.scala:118:51] wire _mem_xcpt_valids_T_8 = |_mem_xcpt_valids_T_7; // @[util.scala:118:{51,59}] wire _mem_xcpt_valids_T_9 = ~_mem_xcpt_valids_T_8; // @[util.scala:118:59] wire _mem_xcpt_valids_T_10 = _mem_xcpt_valids_T_6 & _mem_xcpt_valids_T_9; // @[lsu.scala:669:93, :670:41, :671:22] wire _mem_xcpt_valids_WIRE_0 = _mem_xcpt_valids_T_10; // @[lsu.scala:263:49, :670:41] reg mem_xcpt_valids_0; // @[lsu.scala:668:32] assign mem_xcpt_valid = mem_xcpt_valids_0; // @[lsu.scala:358:29, :668:32] wire [6:0] _mem_xcpt_uops_WIRE_0_uopc = mem_xcpt_uops_out_uopc; // @[util.scala:96:23] wire [31:0] _mem_xcpt_uops_WIRE_0_inst = mem_xcpt_uops_out_inst; // @[util.scala:96:23] wire [31:0] _mem_xcpt_uops_WIRE_0_debug_inst = mem_xcpt_uops_out_debug_inst; // @[util.scala:96:23] wire _mem_xcpt_uops_WIRE_0_is_rvc = mem_xcpt_uops_out_is_rvc; // @[util.scala:96:23] wire [39:0] _mem_xcpt_uops_WIRE_0_debug_pc = mem_xcpt_uops_out_debug_pc; // @[util.scala:96:23] wire [2:0] _mem_xcpt_uops_WIRE_0_iq_type = mem_xcpt_uops_out_iq_type; // @[util.scala:96:23] wire [9:0] _mem_xcpt_uops_WIRE_0_fu_code = mem_xcpt_uops_out_fu_code; // @[util.scala:96:23] wire [3:0] _mem_xcpt_uops_WIRE_0_ctrl_br_type = mem_xcpt_uops_out_ctrl_br_type; // @[util.scala:96:23] wire [1:0] _mem_xcpt_uops_WIRE_0_ctrl_op1_sel = mem_xcpt_uops_out_ctrl_op1_sel; // @[util.scala:96:23] wire [2:0] _mem_xcpt_uops_WIRE_0_ctrl_op2_sel = mem_xcpt_uops_out_ctrl_op2_sel; // @[util.scala:96:23] wire [2:0] _mem_xcpt_uops_WIRE_0_ctrl_imm_sel = mem_xcpt_uops_out_ctrl_imm_sel; // @[util.scala:96:23] wire [4:0] _mem_xcpt_uops_WIRE_0_ctrl_op_fcn = mem_xcpt_uops_out_ctrl_op_fcn; // @[util.scala:96:23] wire _mem_xcpt_uops_WIRE_0_ctrl_fcn_dw = mem_xcpt_uops_out_ctrl_fcn_dw; // @[util.scala:96:23] wire [2:0] _mem_xcpt_uops_WIRE_0_ctrl_csr_cmd = mem_xcpt_uops_out_ctrl_csr_cmd; // @[util.scala:96:23] wire _mem_xcpt_uops_WIRE_0_ctrl_is_load = mem_xcpt_uops_out_ctrl_is_load; // @[util.scala:96:23] wire _mem_xcpt_uops_WIRE_0_ctrl_is_sta = mem_xcpt_uops_out_ctrl_is_sta; // @[util.scala:96:23] wire _mem_xcpt_uops_WIRE_0_ctrl_is_std = mem_xcpt_uops_out_ctrl_is_std; // @[util.scala:96:23] wire [1:0] _mem_xcpt_uops_WIRE_0_iw_state = mem_xcpt_uops_out_iw_state; // @[util.scala:96:23] wire _mem_xcpt_uops_WIRE_0_iw_p1_poisoned = mem_xcpt_uops_out_iw_p1_poisoned; // @[util.scala:96:23] wire _mem_xcpt_uops_WIRE_0_iw_p2_poisoned = mem_xcpt_uops_out_iw_p2_poisoned; // @[util.scala:96:23] wire _mem_xcpt_uops_WIRE_0_is_br = mem_xcpt_uops_out_is_br; // @[util.scala:96:23] wire _mem_xcpt_uops_WIRE_0_is_jalr = mem_xcpt_uops_out_is_jalr; // @[util.scala:96:23] wire _mem_xcpt_uops_WIRE_0_is_jal = mem_xcpt_uops_out_is_jal; // @[util.scala:96:23] wire [7:0] _mem_xcpt_uops_out_br_mask_T_1; // @[util.scala:85:25] wire _mem_xcpt_uops_WIRE_0_is_sfb = mem_xcpt_uops_out_is_sfb; // @[util.scala:96:23] wire [7:0] _mem_xcpt_uops_WIRE_0_br_mask = mem_xcpt_uops_out_br_mask; // @[util.scala:96:23] wire [2:0] _mem_xcpt_uops_WIRE_0_br_tag = mem_xcpt_uops_out_br_tag; // @[util.scala:96:23] wire [3:0] _mem_xcpt_uops_WIRE_0_ftq_idx = mem_xcpt_uops_out_ftq_idx; // @[util.scala:96:23] wire _mem_xcpt_uops_WIRE_0_edge_inst = mem_xcpt_uops_out_edge_inst; // @[util.scala:96:23] wire [5:0] _mem_xcpt_uops_WIRE_0_pc_lob = mem_xcpt_uops_out_pc_lob; // @[util.scala:96:23] wire _mem_xcpt_uops_WIRE_0_taken = mem_xcpt_uops_out_taken; // @[util.scala:96:23] wire [19:0] _mem_xcpt_uops_WIRE_0_imm_packed = mem_xcpt_uops_out_imm_packed; // @[util.scala:96:23] wire [11:0] _mem_xcpt_uops_WIRE_0_csr_addr = mem_xcpt_uops_out_csr_addr; // @[util.scala:96:23] wire [4:0] _mem_xcpt_uops_WIRE_0_rob_idx = mem_xcpt_uops_out_rob_idx; // @[util.scala:96:23] wire [2:0] _mem_xcpt_uops_WIRE_0_ldq_idx = mem_xcpt_uops_out_ldq_idx; // @[util.scala:96:23] wire [2:0] _mem_xcpt_uops_WIRE_0_stq_idx = mem_xcpt_uops_out_stq_idx; // @[util.scala:96:23] wire [1:0] _mem_xcpt_uops_WIRE_0_rxq_idx = mem_xcpt_uops_out_rxq_idx; // @[util.scala:96:23] wire [5:0] _mem_xcpt_uops_WIRE_0_pdst = mem_xcpt_uops_out_pdst; // @[util.scala:96:23] wire [5:0] _mem_xcpt_uops_WIRE_0_prs1 = mem_xcpt_uops_out_prs1; // @[util.scala:96:23] wire [5:0] _mem_xcpt_uops_WIRE_0_prs2 = mem_xcpt_uops_out_prs2; // @[util.scala:96:23] wire [5:0] _mem_xcpt_uops_WIRE_0_prs3 = mem_xcpt_uops_out_prs3; // @[util.scala:96:23] wire [3:0] _mem_xcpt_uops_WIRE_0_ppred = mem_xcpt_uops_out_ppred; // @[util.scala:96:23] wire _mem_xcpt_uops_WIRE_0_prs1_busy = mem_xcpt_uops_out_prs1_busy; // @[util.scala:96:23] wire _mem_xcpt_uops_WIRE_0_prs2_busy = mem_xcpt_uops_out_prs2_busy; // @[util.scala:96:23] wire _mem_xcpt_uops_WIRE_0_prs3_busy = mem_xcpt_uops_out_prs3_busy; // @[util.scala:96:23] wire _mem_xcpt_uops_WIRE_0_ppred_busy = mem_xcpt_uops_out_ppred_busy; // @[util.scala:96:23] wire [5:0] _mem_xcpt_uops_WIRE_0_stale_pdst = mem_xcpt_uops_out_stale_pdst; // @[util.scala:96:23] wire _mem_xcpt_uops_WIRE_0_exception = mem_xcpt_uops_out_exception; // @[util.scala:96:23] wire [63:0] _mem_xcpt_uops_WIRE_0_exc_cause = mem_xcpt_uops_out_exc_cause; // @[util.scala:96:23] wire _mem_xcpt_uops_WIRE_0_bypassable = mem_xcpt_uops_out_bypassable; // @[util.scala:96:23] wire [4:0] _mem_xcpt_uops_WIRE_0_mem_cmd = mem_xcpt_uops_out_mem_cmd; // @[util.scala:96:23] wire [1:0] _mem_xcpt_uops_WIRE_0_mem_size = mem_xcpt_uops_out_mem_size; // @[util.scala:96:23] wire _mem_xcpt_uops_WIRE_0_mem_signed = mem_xcpt_uops_out_mem_signed; // @[util.scala:96:23] wire _mem_xcpt_uops_WIRE_0_is_fence = mem_xcpt_uops_out_is_fence; // @[util.scala:96:23] wire _mem_xcpt_uops_WIRE_0_is_fencei = mem_xcpt_uops_out_is_fencei; // @[util.scala:96:23] wire _mem_xcpt_uops_WIRE_0_is_amo = mem_xcpt_uops_out_is_amo; // @[util.scala:96:23] wire _mem_xcpt_uops_WIRE_0_uses_ldq = mem_xcpt_uops_out_uses_ldq; // @[util.scala:96:23] wire _mem_xcpt_uops_WIRE_0_uses_stq = mem_xcpt_uops_out_uses_stq; // @[util.scala:96:23] wire _mem_xcpt_uops_WIRE_0_is_sys_pc2epc = mem_xcpt_uops_out_is_sys_pc2epc; // @[util.scala:96:23] wire _mem_xcpt_uops_WIRE_0_is_unique = mem_xcpt_uops_out_is_unique; // @[util.scala:96:23] wire _mem_xcpt_uops_WIRE_0_flush_on_commit = mem_xcpt_uops_out_flush_on_commit; // @[util.scala:96:23] wire _mem_xcpt_uops_WIRE_0_ldst_is_rs1 = mem_xcpt_uops_out_ldst_is_rs1; // @[util.scala:96:23] wire [5:0] _mem_xcpt_uops_WIRE_0_ldst = mem_xcpt_uops_out_ldst; // @[util.scala:96:23] wire [5:0] _mem_xcpt_uops_WIRE_0_lrs1 = mem_xcpt_uops_out_lrs1; // @[util.scala:96:23] wire [5:0] _mem_xcpt_uops_WIRE_0_lrs2 = mem_xcpt_uops_out_lrs2; // @[util.scala:96:23] wire [5:0] _mem_xcpt_uops_WIRE_0_lrs3 = mem_xcpt_uops_out_lrs3; // @[util.scala:96:23] wire _mem_xcpt_uops_WIRE_0_ldst_val = mem_xcpt_uops_out_ldst_val; // @[util.scala:96:23] wire [1:0] _mem_xcpt_uops_WIRE_0_dst_rtype = mem_xcpt_uops_out_dst_rtype; // @[util.scala:96:23] wire [1:0] _mem_xcpt_uops_WIRE_0_lrs1_rtype = mem_xcpt_uops_out_lrs1_rtype; // @[util.scala:96:23] wire [1:0] _mem_xcpt_uops_WIRE_0_lrs2_rtype = mem_xcpt_uops_out_lrs2_rtype; // @[util.scala:96:23] wire _mem_xcpt_uops_WIRE_0_frs3_en = mem_xcpt_uops_out_frs3_en; // @[util.scala:96:23] wire _mem_xcpt_uops_WIRE_0_fp_val = mem_xcpt_uops_out_fp_val; // @[util.scala:96:23] wire _mem_xcpt_uops_WIRE_0_fp_single = mem_xcpt_uops_out_fp_single; // @[util.scala:96:23] wire _mem_xcpt_uops_WIRE_0_xcpt_pf_if = mem_xcpt_uops_out_xcpt_pf_if; // @[util.scala:96:23] wire _mem_xcpt_uops_WIRE_0_xcpt_ae_if = mem_xcpt_uops_out_xcpt_ae_if; // @[util.scala:96:23] wire _mem_xcpt_uops_WIRE_0_xcpt_ma_if = mem_xcpt_uops_out_xcpt_ma_if; // @[util.scala:96:23] wire _mem_xcpt_uops_WIRE_0_bp_debug_if = mem_xcpt_uops_out_bp_debug_if; // @[util.scala:96:23] wire _mem_xcpt_uops_WIRE_0_bp_xcpt_if = mem_xcpt_uops_out_bp_xcpt_if; // @[util.scala:96:23] wire [1:0] _mem_xcpt_uops_WIRE_0_debug_fsrc = mem_xcpt_uops_out_debug_fsrc; // @[util.scala:96:23] wire [1:0] _mem_xcpt_uops_WIRE_0_debug_tsrc = mem_xcpt_uops_out_debug_tsrc; // @[util.scala:96:23] wire [7:0] _mem_xcpt_uops_out_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:85:27] assign _mem_xcpt_uops_out_br_mask_T_1 = exe_tlb_uop_0_br_mask & _mem_xcpt_uops_out_br_mask_T; // @[util.scala:85:{25,27}] assign mem_xcpt_uops_out_br_mask = _mem_xcpt_uops_out_br_mask_T_1; // @[util.scala:85:25, :96:23] reg [6:0] mem_xcpt_uops_0_uopc; // @[lsu.scala:672:32] assign mem_xcpt_uop_uopc = mem_xcpt_uops_0_uopc; // @[lsu.scala:360:29, :672:32] reg [31:0] mem_xcpt_uops_0_inst; // @[lsu.scala:672:32] assign mem_xcpt_uop_inst = mem_xcpt_uops_0_inst; // @[lsu.scala:360:29, :672:32] reg [31:0] mem_xcpt_uops_0_debug_inst; // @[lsu.scala:672:32] assign mem_xcpt_uop_debug_inst = mem_xcpt_uops_0_debug_inst; // @[lsu.scala:360:29, :672:32] reg mem_xcpt_uops_0_is_rvc; // @[lsu.scala:672:32] assign mem_xcpt_uop_is_rvc = mem_xcpt_uops_0_is_rvc; // @[lsu.scala:360:29, :672:32] reg [39:0] mem_xcpt_uops_0_debug_pc; // @[lsu.scala:672:32] assign mem_xcpt_uop_debug_pc = mem_xcpt_uops_0_debug_pc; // @[lsu.scala:360:29, :672:32] reg [2:0] mem_xcpt_uops_0_iq_type; // @[lsu.scala:672:32] assign mem_xcpt_uop_iq_type = mem_xcpt_uops_0_iq_type; // @[lsu.scala:360:29, :672:32] reg [9:0] mem_xcpt_uops_0_fu_code; // @[lsu.scala:672:32] assign mem_xcpt_uop_fu_code = mem_xcpt_uops_0_fu_code; // @[lsu.scala:360:29, :672:32] reg [3:0] mem_xcpt_uops_0_ctrl_br_type; // @[lsu.scala:672:32] assign mem_xcpt_uop_ctrl_br_type = mem_xcpt_uops_0_ctrl_br_type; // @[lsu.scala:360:29, :672:32] reg [1:0] mem_xcpt_uops_0_ctrl_op1_sel; // @[lsu.scala:672:32] assign mem_xcpt_uop_ctrl_op1_sel = mem_xcpt_uops_0_ctrl_op1_sel; // @[lsu.scala:360:29, :672:32] reg [2:0] mem_xcpt_uops_0_ctrl_op2_sel; // @[lsu.scala:672:32] assign mem_xcpt_uop_ctrl_op2_sel = mem_xcpt_uops_0_ctrl_op2_sel; // @[lsu.scala:360:29, :672:32] reg [2:0] mem_xcpt_uops_0_ctrl_imm_sel; // @[lsu.scala:672:32] assign mem_xcpt_uop_ctrl_imm_sel = mem_xcpt_uops_0_ctrl_imm_sel; // @[lsu.scala:360:29, :672:32] reg [4:0] mem_xcpt_uops_0_ctrl_op_fcn; // @[lsu.scala:672:32] assign mem_xcpt_uop_ctrl_op_fcn = mem_xcpt_uops_0_ctrl_op_fcn; // @[lsu.scala:360:29, :672:32] reg mem_xcpt_uops_0_ctrl_fcn_dw; // @[lsu.scala:672:32] assign mem_xcpt_uop_ctrl_fcn_dw = mem_xcpt_uops_0_ctrl_fcn_dw; // @[lsu.scala:360:29, :672:32] reg [2:0] mem_xcpt_uops_0_ctrl_csr_cmd; // @[lsu.scala:672:32] assign mem_xcpt_uop_ctrl_csr_cmd = mem_xcpt_uops_0_ctrl_csr_cmd; // @[lsu.scala:360:29, :672:32] reg mem_xcpt_uops_0_ctrl_is_load; // @[lsu.scala:672:32] assign mem_xcpt_uop_ctrl_is_load = mem_xcpt_uops_0_ctrl_is_load; // @[lsu.scala:360:29, :672:32] reg mem_xcpt_uops_0_ctrl_is_sta; // @[lsu.scala:672:32] assign mem_xcpt_uop_ctrl_is_sta = mem_xcpt_uops_0_ctrl_is_sta; // @[lsu.scala:360:29, :672:32] reg mem_xcpt_uops_0_ctrl_is_std; // @[lsu.scala:672:32] assign mem_xcpt_uop_ctrl_is_std = mem_xcpt_uops_0_ctrl_is_std; // @[lsu.scala:360:29, :672:32] reg [1:0] mem_xcpt_uops_0_iw_state; // @[lsu.scala:672:32] assign mem_xcpt_uop_iw_state = mem_xcpt_uops_0_iw_state; // @[lsu.scala:360:29, :672:32] reg mem_xcpt_uops_0_iw_p1_poisoned; // @[lsu.scala:672:32] assign mem_xcpt_uop_iw_p1_poisoned = mem_xcpt_uops_0_iw_p1_poisoned; // @[lsu.scala:360:29, :672:32] reg mem_xcpt_uops_0_iw_p2_poisoned; // @[lsu.scala:672:32] assign mem_xcpt_uop_iw_p2_poisoned = mem_xcpt_uops_0_iw_p2_poisoned; // @[lsu.scala:360:29, :672:32] reg mem_xcpt_uops_0_is_br; // @[lsu.scala:672:32] assign mem_xcpt_uop_is_br = mem_xcpt_uops_0_is_br; // @[lsu.scala:360:29, :672:32] reg mem_xcpt_uops_0_is_jalr; // @[lsu.scala:672:32] assign mem_xcpt_uop_is_jalr = mem_xcpt_uops_0_is_jalr; // @[lsu.scala:360:29, :672:32] reg mem_xcpt_uops_0_is_jal; // @[lsu.scala:672:32] assign mem_xcpt_uop_is_jal = mem_xcpt_uops_0_is_jal; // @[lsu.scala:360:29, :672:32] reg mem_xcpt_uops_0_is_sfb; // @[lsu.scala:672:32] assign mem_xcpt_uop_is_sfb = mem_xcpt_uops_0_is_sfb; // @[lsu.scala:360:29, :672:32] reg [7:0] mem_xcpt_uops_0_br_mask; // @[lsu.scala:672:32] assign mem_xcpt_uop_br_mask = mem_xcpt_uops_0_br_mask; // @[lsu.scala:360:29, :672:32] reg [2:0] mem_xcpt_uops_0_br_tag; // @[lsu.scala:672:32] assign mem_xcpt_uop_br_tag = mem_xcpt_uops_0_br_tag; // @[lsu.scala:360:29, :672:32] reg [3:0] mem_xcpt_uops_0_ftq_idx; // @[lsu.scala:672:32] assign mem_xcpt_uop_ftq_idx = mem_xcpt_uops_0_ftq_idx; // @[lsu.scala:360:29, :672:32] reg mem_xcpt_uops_0_edge_inst; // @[lsu.scala:672:32] assign mem_xcpt_uop_edge_inst = mem_xcpt_uops_0_edge_inst; // @[lsu.scala:360:29, :672:32] reg [5:0] mem_xcpt_uops_0_pc_lob; // @[lsu.scala:672:32] assign mem_xcpt_uop_pc_lob = mem_xcpt_uops_0_pc_lob; // @[lsu.scala:360:29, :672:32] reg mem_xcpt_uops_0_taken; // @[lsu.scala:672:32] assign mem_xcpt_uop_taken = mem_xcpt_uops_0_taken; // @[lsu.scala:360:29, :672:32] reg [19:0] mem_xcpt_uops_0_imm_packed; // @[lsu.scala:672:32] assign mem_xcpt_uop_imm_packed = mem_xcpt_uops_0_imm_packed; // @[lsu.scala:360:29, :672:32] reg [11:0] mem_xcpt_uops_0_csr_addr; // @[lsu.scala:672:32] assign mem_xcpt_uop_csr_addr = mem_xcpt_uops_0_csr_addr; // @[lsu.scala:360:29, :672:32] reg [4:0] mem_xcpt_uops_0_rob_idx; // @[lsu.scala:672:32] assign mem_xcpt_uop_rob_idx = mem_xcpt_uops_0_rob_idx; // @[lsu.scala:360:29, :672:32] reg [2:0] mem_xcpt_uops_0_ldq_idx; // @[lsu.scala:672:32] assign mem_xcpt_uop_ldq_idx = mem_xcpt_uops_0_ldq_idx; // @[lsu.scala:360:29, :672:32] reg [2:0] mem_xcpt_uops_0_stq_idx; // @[lsu.scala:672:32] assign mem_xcpt_uop_stq_idx = mem_xcpt_uops_0_stq_idx; // @[lsu.scala:360:29, :672:32] reg [1:0] mem_xcpt_uops_0_rxq_idx; // @[lsu.scala:672:32] assign mem_xcpt_uop_rxq_idx = mem_xcpt_uops_0_rxq_idx; // @[lsu.scala:360:29, :672:32] reg [5:0] mem_xcpt_uops_0_pdst; // @[lsu.scala:672:32] assign mem_xcpt_uop_pdst = mem_xcpt_uops_0_pdst; // @[lsu.scala:360:29, :672:32] reg [5:0] mem_xcpt_uops_0_prs1; // @[lsu.scala:672:32] assign mem_xcpt_uop_prs1 = mem_xcpt_uops_0_prs1; // @[lsu.scala:360:29, :672:32] reg [5:0] mem_xcpt_uops_0_prs2; // @[lsu.scala:672:32] assign mem_xcpt_uop_prs2 = mem_xcpt_uops_0_prs2; // @[lsu.scala:360:29, :672:32] reg [5:0] mem_xcpt_uops_0_prs3; // @[lsu.scala:672:32] assign mem_xcpt_uop_prs3 = mem_xcpt_uops_0_prs3; // @[lsu.scala:360:29, :672:32] reg [3:0] mem_xcpt_uops_0_ppred; // @[lsu.scala:672:32] assign mem_xcpt_uop_ppred = mem_xcpt_uops_0_ppred; // @[lsu.scala:360:29, :672:32] reg mem_xcpt_uops_0_prs1_busy; // @[lsu.scala:672:32] assign mem_xcpt_uop_prs1_busy = mem_xcpt_uops_0_prs1_busy; // @[lsu.scala:360:29, :672:32] reg mem_xcpt_uops_0_prs2_busy; // @[lsu.scala:672:32] assign mem_xcpt_uop_prs2_busy = mem_xcpt_uops_0_prs2_busy; // @[lsu.scala:360:29, :672:32] reg mem_xcpt_uops_0_prs3_busy; // @[lsu.scala:672:32] assign mem_xcpt_uop_prs3_busy = mem_xcpt_uops_0_prs3_busy; // @[lsu.scala:360:29, :672:32] reg mem_xcpt_uops_0_ppred_busy; // @[lsu.scala:672:32] assign mem_xcpt_uop_ppred_busy = mem_xcpt_uops_0_ppred_busy; // @[lsu.scala:360:29, :672:32] reg [5:0] mem_xcpt_uops_0_stale_pdst; // @[lsu.scala:672:32] assign mem_xcpt_uop_stale_pdst = mem_xcpt_uops_0_stale_pdst; // @[lsu.scala:360:29, :672:32] reg mem_xcpt_uops_0_exception; // @[lsu.scala:672:32] assign mem_xcpt_uop_exception = mem_xcpt_uops_0_exception; // @[lsu.scala:360:29, :672:32] reg [63:0] mem_xcpt_uops_0_exc_cause; // @[lsu.scala:672:32] assign mem_xcpt_uop_exc_cause = mem_xcpt_uops_0_exc_cause; // @[lsu.scala:360:29, :672:32] reg mem_xcpt_uops_0_bypassable; // @[lsu.scala:672:32] assign mem_xcpt_uop_bypassable = mem_xcpt_uops_0_bypassable; // @[lsu.scala:360:29, :672:32] reg [4:0] mem_xcpt_uops_0_mem_cmd; // @[lsu.scala:672:32] assign mem_xcpt_uop_mem_cmd = mem_xcpt_uops_0_mem_cmd; // @[lsu.scala:360:29, :672:32] reg [1:0] mem_xcpt_uops_0_mem_size; // @[lsu.scala:672:32] assign mem_xcpt_uop_mem_size = mem_xcpt_uops_0_mem_size; // @[lsu.scala:360:29, :672:32] reg mem_xcpt_uops_0_mem_signed; // @[lsu.scala:672:32] assign mem_xcpt_uop_mem_signed = mem_xcpt_uops_0_mem_signed; // @[lsu.scala:360:29, :672:32] reg mem_xcpt_uops_0_is_fence; // @[lsu.scala:672:32] assign mem_xcpt_uop_is_fence = mem_xcpt_uops_0_is_fence; // @[lsu.scala:360:29, :672:32] reg mem_xcpt_uops_0_is_fencei; // @[lsu.scala:672:32] assign mem_xcpt_uop_is_fencei = mem_xcpt_uops_0_is_fencei; // @[lsu.scala:360:29, :672:32] reg mem_xcpt_uops_0_is_amo; // @[lsu.scala:672:32] assign mem_xcpt_uop_is_amo = mem_xcpt_uops_0_is_amo; // @[lsu.scala:360:29, :672:32] reg mem_xcpt_uops_0_uses_ldq; // @[lsu.scala:672:32] assign mem_xcpt_uop_uses_ldq = mem_xcpt_uops_0_uses_ldq; // @[lsu.scala:360:29, :672:32] reg mem_xcpt_uops_0_uses_stq; // @[lsu.scala:672:32] assign mem_xcpt_uop_uses_stq = mem_xcpt_uops_0_uses_stq; // @[lsu.scala:360:29, :672:32] reg mem_xcpt_uops_0_is_sys_pc2epc; // @[lsu.scala:672:32] assign mem_xcpt_uop_is_sys_pc2epc = mem_xcpt_uops_0_is_sys_pc2epc; // @[lsu.scala:360:29, :672:32] reg mem_xcpt_uops_0_is_unique; // @[lsu.scala:672:32] assign mem_xcpt_uop_is_unique = mem_xcpt_uops_0_is_unique; // @[lsu.scala:360:29, :672:32] reg mem_xcpt_uops_0_flush_on_commit; // @[lsu.scala:672:32] assign mem_xcpt_uop_flush_on_commit = mem_xcpt_uops_0_flush_on_commit; // @[lsu.scala:360:29, :672:32] reg mem_xcpt_uops_0_ldst_is_rs1; // @[lsu.scala:672:32] assign mem_xcpt_uop_ldst_is_rs1 = mem_xcpt_uops_0_ldst_is_rs1; // @[lsu.scala:360:29, :672:32] reg [5:0] mem_xcpt_uops_0_ldst; // @[lsu.scala:672:32] assign mem_xcpt_uop_ldst = mem_xcpt_uops_0_ldst; // @[lsu.scala:360:29, :672:32] reg [5:0] mem_xcpt_uops_0_lrs1; // @[lsu.scala:672:32] assign mem_xcpt_uop_lrs1 = mem_xcpt_uops_0_lrs1; // @[lsu.scala:360:29, :672:32] reg [5:0] mem_xcpt_uops_0_lrs2; // @[lsu.scala:672:32] assign mem_xcpt_uop_lrs2 = mem_xcpt_uops_0_lrs2; // @[lsu.scala:360:29, :672:32] reg [5:0] mem_xcpt_uops_0_lrs3; // @[lsu.scala:672:32] assign mem_xcpt_uop_lrs3 = mem_xcpt_uops_0_lrs3; // @[lsu.scala:360:29, :672:32] reg mem_xcpt_uops_0_ldst_val; // @[lsu.scala:672:32] assign mem_xcpt_uop_ldst_val = mem_xcpt_uops_0_ldst_val; // @[lsu.scala:360:29, :672:32] reg [1:0] mem_xcpt_uops_0_dst_rtype; // @[lsu.scala:672:32] assign mem_xcpt_uop_dst_rtype = mem_xcpt_uops_0_dst_rtype; // @[lsu.scala:360:29, :672:32] reg [1:0] mem_xcpt_uops_0_lrs1_rtype; // @[lsu.scala:672:32] assign mem_xcpt_uop_lrs1_rtype = mem_xcpt_uops_0_lrs1_rtype; // @[lsu.scala:360:29, :672:32] reg [1:0] mem_xcpt_uops_0_lrs2_rtype; // @[lsu.scala:672:32] assign mem_xcpt_uop_lrs2_rtype = mem_xcpt_uops_0_lrs2_rtype; // @[lsu.scala:360:29, :672:32] reg mem_xcpt_uops_0_frs3_en; // @[lsu.scala:672:32] assign mem_xcpt_uop_frs3_en = mem_xcpt_uops_0_frs3_en; // @[lsu.scala:360:29, :672:32] reg mem_xcpt_uops_0_fp_val; // @[lsu.scala:672:32] assign mem_xcpt_uop_fp_val = mem_xcpt_uops_0_fp_val; // @[lsu.scala:360:29, :672:32] reg mem_xcpt_uops_0_fp_single; // @[lsu.scala:672:32] assign mem_xcpt_uop_fp_single = mem_xcpt_uops_0_fp_single; // @[lsu.scala:360:29, :672:32] reg mem_xcpt_uops_0_xcpt_pf_if; // @[lsu.scala:672:32] assign mem_xcpt_uop_xcpt_pf_if = mem_xcpt_uops_0_xcpt_pf_if; // @[lsu.scala:360:29, :672:32] reg mem_xcpt_uops_0_xcpt_ae_if; // @[lsu.scala:672:32] assign mem_xcpt_uop_xcpt_ae_if = mem_xcpt_uops_0_xcpt_ae_if; // @[lsu.scala:360:29, :672:32] reg mem_xcpt_uops_0_xcpt_ma_if; // @[lsu.scala:672:32] assign mem_xcpt_uop_xcpt_ma_if = mem_xcpt_uops_0_xcpt_ma_if; // @[lsu.scala:360:29, :672:32] reg mem_xcpt_uops_0_bp_debug_if; // @[lsu.scala:672:32] assign mem_xcpt_uop_bp_debug_if = mem_xcpt_uops_0_bp_debug_if; // @[lsu.scala:360:29, :672:32] reg mem_xcpt_uops_0_bp_xcpt_if; // @[lsu.scala:672:32] assign mem_xcpt_uop_bp_xcpt_if = mem_xcpt_uops_0_bp_xcpt_if; // @[lsu.scala:360:29, :672:32] reg [1:0] mem_xcpt_uops_0_debug_fsrc; // @[lsu.scala:672:32] assign mem_xcpt_uop_debug_fsrc = mem_xcpt_uops_0_debug_fsrc; // @[lsu.scala:360:29, :672:32] reg [1:0] mem_xcpt_uops_0_debug_tsrc; // @[lsu.scala:672:32] assign mem_xcpt_uop_debug_tsrc = mem_xcpt_uops_0_debug_tsrc; // @[lsu.scala:360:29, :672:32] wire [2:0] _mem_xcpt_causes_T = {1'h1, ~ae_ld_0, 1'h1}; // @[lsu.scala:263:49, :678:8] wire [3:0] _mem_xcpt_causes_T_1 = pf_st_0 ? 4'hF : {1'h0, _mem_xcpt_causes_T}; // @[lsu.scala:263:49, :677:8, :678:8] wire [3:0] _mem_xcpt_causes_T_2 = pf_ld_0 ? 4'hD : _mem_xcpt_causes_T_1; // @[lsu.scala:263:49, :676:8, :677:8] wire [3:0] _mem_xcpt_causes_T_3 = ma_st_0 ? 4'h6 : _mem_xcpt_causes_T_2; // @[lsu.scala:263:49, :675:8, :676:8] wire [3:0] _mem_xcpt_causes_T_4 = ma_ld_0 ? 4'h4 : _mem_xcpt_causes_T_3; // @[lsu.scala:263:49, :674:8, :675:8] wire [3:0] _mem_xcpt_causes_WIRE_0 = _mem_xcpt_causes_T_4; // @[lsu.scala:263:49, :674:8] reg [3:0] mem_xcpt_causes_0; // @[lsu.scala:673:32] assign mem_xcpt_cause = mem_xcpt_causes_0; // @[lsu.scala:359:29, :673:32] reg [39:0] mem_xcpt_vaddrs_0; // @[lsu.scala:680:32] assign mem_xcpt_vaddr = mem_xcpt_vaddrs_0; // @[lsu.scala:361:29, :680:32] wire _exe_tlb_miss_T_1; // @[lsu.scala:709:83] wire _exe_tlb_miss_T_2 = exe_tlb_valid_0 & _exe_tlb_miss_T_1; // @[lsu.scala:525:27, :709:{58,83}] wire exe_tlb_miss_0 = _exe_tlb_miss_T_2; // @[lsu.scala:263:49, :709:58] wire [19:0] _exe_tlb_paddr_T = _dtlb_io_resp_0_paddr[31:12]; // @[lsu.scala:247:20, :710:62] wire [11:0] _exe_tlb_paddr_T_1 = exe_tlb_vaddr_0[11:0]; // @[lsu.scala:263:49, :711:57] wire [31:0] _exe_tlb_paddr_T_2 = {_exe_tlb_paddr_T, _exe_tlb_paddr_T_1}; // @[lsu.scala:710:{40,62}, :711:57] wire [31:0] exe_tlb_paddr_0 = _exe_tlb_paddr_T_2; // @[lsu.scala:263:49, :710:40] wire _exe_tlb_uncacheable_T = ~_dtlb_io_resp_0_cacheable; // @[lsu.scala:247:20, :712:43] wire exe_tlb_uncacheable_0 = _exe_tlb_uncacheable_T; // @[lsu.scala:263:49, :712:43] reg REG; // @[lsu.scala:719:21] assign io_dmem_req_valid_0 = dmem_req_0_valid; // @[lsu.scala:201:7, :750:22] assign io_dmem_req_bits_0_valid_0 = dmem_req_0_valid; // @[lsu.scala:201:7, :750:22] assign io_dmem_req_bits_0_bits_uop_uopc_0 = dmem_req_0_bits_uop_uopc; // @[lsu.scala:201:7, :750:22] assign io_dmem_req_bits_0_bits_uop_inst_0 = dmem_req_0_bits_uop_inst; // @[lsu.scala:201:7, :750:22] assign io_dmem_req_bits_0_bits_uop_debug_inst_0 = dmem_req_0_bits_uop_debug_inst; // @[lsu.scala:201:7, :750:22] assign io_dmem_req_bits_0_bits_uop_is_rvc_0 = dmem_req_0_bits_uop_is_rvc; // @[lsu.scala:201:7, :750:22] assign io_dmem_req_bits_0_bits_uop_debug_pc_0 = dmem_req_0_bits_uop_debug_pc; // @[lsu.scala:201:7, :750:22] assign io_dmem_req_bits_0_bits_uop_iq_type_0 = dmem_req_0_bits_uop_iq_type; // @[lsu.scala:201:7, :750:22] assign io_dmem_req_bits_0_bits_uop_fu_code_0 = dmem_req_0_bits_uop_fu_code; // @[lsu.scala:201:7, :750:22] assign io_dmem_req_bits_0_bits_uop_ctrl_br_type_0 = dmem_req_0_bits_uop_ctrl_br_type; // @[lsu.scala:201:7, :750:22] assign io_dmem_req_bits_0_bits_uop_ctrl_op1_sel_0 = dmem_req_0_bits_uop_ctrl_op1_sel; // @[lsu.scala:201:7, :750:22] assign io_dmem_req_bits_0_bits_uop_ctrl_op2_sel_0 = dmem_req_0_bits_uop_ctrl_op2_sel; // @[lsu.scala:201:7, :750:22] assign io_dmem_req_bits_0_bits_uop_ctrl_imm_sel_0 = dmem_req_0_bits_uop_ctrl_imm_sel; // @[lsu.scala:201:7, :750:22] assign io_dmem_req_bits_0_bits_uop_ctrl_op_fcn_0 = dmem_req_0_bits_uop_ctrl_op_fcn; // @[lsu.scala:201:7, :750:22] assign io_dmem_req_bits_0_bits_uop_ctrl_fcn_dw_0 = dmem_req_0_bits_uop_ctrl_fcn_dw; // @[lsu.scala:201:7, :750:22] assign io_dmem_req_bits_0_bits_uop_ctrl_csr_cmd_0 = dmem_req_0_bits_uop_ctrl_csr_cmd; // @[lsu.scala:201:7, :750:22] assign io_dmem_req_bits_0_bits_uop_ctrl_is_load_0 = dmem_req_0_bits_uop_ctrl_is_load; // @[lsu.scala:201:7, :750:22] assign io_dmem_req_bits_0_bits_uop_ctrl_is_sta_0 = dmem_req_0_bits_uop_ctrl_is_sta; // @[lsu.scala:201:7, :750:22] assign io_dmem_req_bits_0_bits_uop_ctrl_is_std_0 = dmem_req_0_bits_uop_ctrl_is_std; // @[lsu.scala:201:7, :750:22] assign io_dmem_req_bits_0_bits_uop_iw_state_0 = dmem_req_0_bits_uop_iw_state; // @[lsu.scala:201:7, :750:22] assign io_dmem_req_bits_0_bits_uop_iw_p1_poisoned_0 = dmem_req_0_bits_uop_iw_p1_poisoned; // @[lsu.scala:201:7, :750:22] assign io_dmem_req_bits_0_bits_uop_iw_p2_poisoned_0 = dmem_req_0_bits_uop_iw_p2_poisoned; // @[lsu.scala:201:7, :750:22] assign io_dmem_req_bits_0_bits_uop_is_br_0 = dmem_req_0_bits_uop_is_br; // @[lsu.scala:201:7, :750:22] assign io_dmem_req_bits_0_bits_uop_is_jalr_0 = dmem_req_0_bits_uop_is_jalr; // @[lsu.scala:201:7, :750:22] assign io_dmem_req_bits_0_bits_uop_is_jal_0 = dmem_req_0_bits_uop_is_jal; // @[lsu.scala:201:7, :750:22] assign io_dmem_req_bits_0_bits_uop_is_sfb_0 = dmem_req_0_bits_uop_is_sfb; // @[lsu.scala:201:7, :750:22] assign io_dmem_req_bits_0_bits_uop_br_mask_0 = dmem_req_0_bits_uop_br_mask; // @[lsu.scala:201:7, :750:22] assign io_dmem_req_bits_0_bits_uop_br_tag_0 = dmem_req_0_bits_uop_br_tag; // @[lsu.scala:201:7, :750:22] assign io_dmem_req_bits_0_bits_uop_ftq_idx_0 = dmem_req_0_bits_uop_ftq_idx; // @[lsu.scala:201:7, :750:22] assign io_dmem_req_bits_0_bits_uop_edge_inst_0 = dmem_req_0_bits_uop_edge_inst; // @[lsu.scala:201:7, :750:22] assign io_dmem_req_bits_0_bits_uop_pc_lob_0 = dmem_req_0_bits_uop_pc_lob; // @[lsu.scala:201:7, :750:22] assign io_dmem_req_bits_0_bits_uop_taken_0 = dmem_req_0_bits_uop_taken; // @[lsu.scala:201:7, :750:22] assign io_dmem_req_bits_0_bits_uop_imm_packed_0 = dmem_req_0_bits_uop_imm_packed; // @[lsu.scala:201:7, :750:22] assign io_dmem_req_bits_0_bits_uop_csr_addr_0 = dmem_req_0_bits_uop_csr_addr; // @[lsu.scala:201:7, :750:22] assign io_dmem_req_bits_0_bits_uop_rob_idx_0 = dmem_req_0_bits_uop_rob_idx; // @[lsu.scala:201:7, :750:22] assign io_dmem_req_bits_0_bits_uop_ldq_idx_0 = dmem_req_0_bits_uop_ldq_idx; // @[lsu.scala:201:7, :750:22] assign io_dmem_req_bits_0_bits_uop_stq_idx_0 = dmem_req_0_bits_uop_stq_idx; // @[lsu.scala:201:7, :750:22] assign io_dmem_req_bits_0_bits_uop_rxq_idx_0 = dmem_req_0_bits_uop_rxq_idx; // @[lsu.scala:201:7, :750:22] assign io_dmem_req_bits_0_bits_uop_pdst_0 = dmem_req_0_bits_uop_pdst; // @[lsu.scala:201:7, :750:22] assign io_dmem_req_bits_0_bits_uop_prs1_0 = dmem_req_0_bits_uop_prs1; // @[lsu.scala:201:7, :750:22] assign io_dmem_req_bits_0_bits_uop_prs2_0 = dmem_req_0_bits_uop_prs2; // @[lsu.scala:201:7, :750:22] assign io_dmem_req_bits_0_bits_uop_prs3_0 = dmem_req_0_bits_uop_prs3; // @[lsu.scala:201:7, :750:22] assign io_dmem_req_bits_0_bits_uop_ppred_0 = dmem_req_0_bits_uop_ppred; // @[lsu.scala:201:7, :750:22] assign io_dmem_req_bits_0_bits_uop_prs1_busy_0 = dmem_req_0_bits_uop_prs1_busy; // @[lsu.scala:201:7, :750:22] assign io_dmem_req_bits_0_bits_uop_prs2_busy_0 = dmem_req_0_bits_uop_prs2_busy; // @[lsu.scala:201:7, :750:22] assign io_dmem_req_bits_0_bits_uop_prs3_busy_0 = dmem_req_0_bits_uop_prs3_busy; // @[lsu.scala:201:7, :750:22] assign io_dmem_req_bits_0_bits_uop_ppred_busy_0 = dmem_req_0_bits_uop_ppred_busy; // @[lsu.scala:201:7, :750:22] assign io_dmem_req_bits_0_bits_uop_stale_pdst_0 = dmem_req_0_bits_uop_stale_pdst; // @[lsu.scala:201:7, :750:22] assign io_dmem_req_bits_0_bits_uop_exception_0 = dmem_req_0_bits_uop_exception; // @[lsu.scala:201:7, :750:22] assign io_dmem_req_bits_0_bits_uop_exc_cause_0 = dmem_req_0_bits_uop_exc_cause; // @[lsu.scala:201:7, :750:22] assign io_dmem_req_bits_0_bits_uop_bypassable_0 = dmem_req_0_bits_uop_bypassable; // @[lsu.scala:201:7, :750:22] assign io_dmem_req_bits_0_bits_uop_mem_cmd_0 = dmem_req_0_bits_uop_mem_cmd; // @[lsu.scala:201:7, :750:22] assign io_dmem_req_bits_0_bits_uop_mem_size_0 = dmem_req_0_bits_uop_mem_size; // @[lsu.scala:201:7, :750:22] assign io_dmem_req_bits_0_bits_uop_mem_signed_0 = dmem_req_0_bits_uop_mem_signed; // @[lsu.scala:201:7, :750:22] assign io_dmem_req_bits_0_bits_uop_is_fence_0 = dmem_req_0_bits_uop_is_fence; // @[lsu.scala:201:7, :750:22] assign io_dmem_req_bits_0_bits_uop_is_fencei_0 = dmem_req_0_bits_uop_is_fencei; // @[lsu.scala:201:7, :750:22] assign io_dmem_req_bits_0_bits_uop_is_amo_0 = dmem_req_0_bits_uop_is_amo; // @[lsu.scala:201:7, :750:22] assign io_dmem_req_bits_0_bits_uop_uses_ldq_0 = dmem_req_0_bits_uop_uses_ldq; // @[lsu.scala:201:7, :750:22] assign io_dmem_req_bits_0_bits_uop_uses_stq_0 = dmem_req_0_bits_uop_uses_stq; // @[lsu.scala:201:7, :750:22] assign io_dmem_req_bits_0_bits_uop_is_sys_pc2epc_0 = dmem_req_0_bits_uop_is_sys_pc2epc; // @[lsu.scala:201:7, :750:22] assign io_dmem_req_bits_0_bits_uop_is_unique_0 = dmem_req_0_bits_uop_is_unique; // @[lsu.scala:201:7, :750:22] assign io_dmem_req_bits_0_bits_uop_flush_on_commit_0 = dmem_req_0_bits_uop_flush_on_commit; // @[lsu.scala:201:7, :750:22] assign io_dmem_req_bits_0_bits_uop_ldst_is_rs1_0 = dmem_req_0_bits_uop_ldst_is_rs1; // @[lsu.scala:201:7, :750:22] assign io_dmem_req_bits_0_bits_uop_ldst_0 = dmem_req_0_bits_uop_ldst; // @[lsu.scala:201:7, :750:22] assign io_dmem_req_bits_0_bits_uop_lrs1_0 = dmem_req_0_bits_uop_lrs1; // @[lsu.scala:201:7, :750:22] assign io_dmem_req_bits_0_bits_uop_lrs2_0 = dmem_req_0_bits_uop_lrs2; // @[lsu.scala:201:7, :750:22] assign io_dmem_req_bits_0_bits_uop_lrs3_0 = dmem_req_0_bits_uop_lrs3; // @[lsu.scala:201:7, :750:22] assign io_dmem_req_bits_0_bits_uop_ldst_val_0 = dmem_req_0_bits_uop_ldst_val; // @[lsu.scala:201:7, :750:22] assign io_dmem_req_bits_0_bits_uop_dst_rtype_0 = dmem_req_0_bits_uop_dst_rtype; // @[lsu.scala:201:7, :750:22] assign io_dmem_req_bits_0_bits_uop_lrs1_rtype_0 = dmem_req_0_bits_uop_lrs1_rtype; // @[lsu.scala:201:7, :750:22] assign io_dmem_req_bits_0_bits_uop_lrs2_rtype_0 = dmem_req_0_bits_uop_lrs2_rtype; // @[lsu.scala:201:7, :750:22] assign io_dmem_req_bits_0_bits_uop_frs3_en_0 = dmem_req_0_bits_uop_frs3_en; // @[lsu.scala:201:7, :750:22] assign io_dmem_req_bits_0_bits_uop_fp_val_0 = dmem_req_0_bits_uop_fp_val; // @[lsu.scala:201:7, :750:22] assign io_dmem_req_bits_0_bits_uop_fp_single_0 = dmem_req_0_bits_uop_fp_single; // @[lsu.scala:201:7, :750:22] assign io_dmem_req_bits_0_bits_uop_xcpt_pf_if_0 = dmem_req_0_bits_uop_xcpt_pf_if; // @[lsu.scala:201:7, :750:22] assign io_dmem_req_bits_0_bits_uop_xcpt_ae_if_0 = dmem_req_0_bits_uop_xcpt_ae_if; // @[lsu.scala:201:7, :750:22] assign io_dmem_req_bits_0_bits_uop_xcpt_ma_if_0 = dmem_req_0_bits_uop_xcpt_ma_if; // @[lsu.scala:201:7, :750:22] assign io_dmem_req_bits_0_bits_uop_bp_debug_if_0 = dmem_req_0_bits_uop_bp_debug_if; // @[lsu.scala:201:7, :750:22] assign io_dmem_req_bits_0_bits_uop_bp_xcpt_if_0 = dmem_req_0_bits_uop_bp_xcpt_if; // @[lsu.scala:201:7, :750:22] assign io_dmem_req_bits_0_bits_uop_debug_fsrc_0 = dmem_req_0_bits_uop_debug_fsrc; // @[lsu.scala:201:7, :750:22] assign io_dmem_req_bits_0_bits_uop_debug_tsrc_0 = dmem_req_0_bits_uop_debug_tsrc; // @[lsu.scala:201:7, :750:22] assign io_dmem_req_bits_0_bits_addr_0 = dmem_req_0_bits_addr; // @[lsu.scala:201:7, :750:22] wire [39:0] _mem_paddr_WIRE_0 = dmem_req_0_bits_addr; // @[lsu.scala:263:49, :750:22] assign io_dmem_req_bits_0_bits_data_0 = dmem_req_0_bits_data; // @[lsu.scala:201:7, :750:22] assign io_dmem_req_bits_0_bits_is_hella_0 = dmem_req_0_bits_is_hella; // @[lsu.scala:201:7, :750:22] wire _dmem_req_fire_T = io_dmem_req_ready_0 & io_dmem_req_valid_0; // @[Decoupled.scala:51:35] wire _dmem_req_fire_T_1 = dmem_req_0_valid & _dmem_req_fire_T; // @[Decoupled.scala:51:35] wire dmem_req_fire_0 = _dmem_req_fire_T_1; // @[lsu.scala:263:49, :753:55] wire s0_executing_loads_0; // @[lsu.scala:755:36] wire s0_executing_loads_1; // @[lsu.scala:755:36] wire s0_executing_loads_2; // @[lsu.scala:755:36] wire s0_executing_loads_3; // @[lsu.scala:755:36] wire s0_executing_loads_4; // @[lsu.scala:755:36] wire s0_executing_loads_5; // @[lsu.scala:755:36] wire s0_executing_loads_6; // @[lsu.scala:755:36] wire s0_executing_loads_7; // @[lsu.scala:755:36] wire _dmem_req_0_valid_T = ~exe_tlb_miss_0; // @[lsu.scala:263:49, :768:33] wire _dmem_req_0_valid_T_1 = ~exe_tlb_uncacheable_0; // @[lsu.scala:263:49, :768:53] wire _dmem_req_0_valid_T_2 = _dmem_req_0_valid_T & _dmem_req_0_valid_T_1; // @[lsu.scala:768:{33,50,53}] wire [39:0] _GEN_217 = {8'h0, exe_tlb_paddr_0}; // @[lsu.scala:263:49, :769:30] wire _dmem_req_0_valid_T_3 = ~exe_tlb_miss_0; // @[lsu.scala:263:49, :768:33, :775:33] wire _dmem_req_0_valid_T_4 = ~exe_tlb_uncacheable_0; // @[lsu.scala:263:49, :768:53, :775:53] wire _dmem_req_0_valid_T_5 = _dmem_req_0_valid_T_3 & _dmem_req_0_valid_T_4; // @[lsu.scala:775:{33,50,53}] wire _dmem_req_0_bits_data_T = dmem_req_0_bits_data_size == 2'h0; // @[AMOALU.scala:11:18, :29:19] wire [7:0] _dmem_req_0_bits_data_T_1 = _GEN_88[7:0]; // @[AMOALU.scala:29:69] wire [15:0] _dmem_req_0_bits_data_T_2 = {2{_dmem_req_0_bits_data_T_1}}; // @[AMOALU.scala:29:{32,69}] wire [31:0] _dmem_req_0_bits_data_T_3 = {2{_dmem_req_0_bits_data_T_2}}; // @[AMOALU.scala:29:32] wire [63:0] _dmem_req_0_bits_data_T_4 = {2{_dmem_req_0_bits_data_T_3}}; // @[AMOALU.scala:29:32] wire _dmem_req_0_bits_data_T_5 = dmem_req_0_bits_data_size == 2'h1; // @[AMOALU.scala:11:18, :29:19] wire [15:0] _dmem_req_0_bits_data_T_6 = _GEN_88[15:0]; // @[AMOALU.scala:29:69] wire [31:0] _dmem_req_0_bits_data_T_7 = {2{_dmem_req_0_bits_data_T_6}}; // @[AMOALU.scala:29:{32,69}] wire [63:0] _dmem_req_0_bits_data_T_8 = {2{_dmem_req_0_bits_data_T_7}}; // @[AMOALU.scala:29:32] wire _dmem_req_0_bits_data_T_9 = dmem_req_0_bits_data_size == 2'h2; // @[AMOALU.scala:11:18, :29:19] wire [31:0] _dmem_req_0_bits_data_T_10 = _GEN_88[31:0]; // @[AMOALU.scala:29:69] wire [63:0] _dmem_req_0_bits_data_T_11 = {2{_dmem_req_0_bits_data_T_10}}; // @[AMOALU.scala:29:{32,69}] wire [63:0] _dmem_req_0_bits_data_T_12 = _dmem_req_0_bits_data_T_9 ? _dmem_req_0_bits_data_T_11 : _GEN_88; // @[AMOALU.scala:29:{13,19,32}] wire [63:0] _dmem_req_0_bits_data_T_13 = _dmem_req_0_bits_data_T_5 ? _dmem_req_0_bits_data_T_8 : _dmem_req_0_bits_data_T_12; // @[AMOALU.scala:29:{13,19,32}] wire [63:0] _dmem_req_0_bits_data_T_14 = _dmem_req_0_bits_data_T ? _dmem_req_0_bits_data_T_4 : _dmem_req_0_bits_data_T_13; // @[AMOALU.scala:29:{13,19,32}] wire [3:0] _GEN_218 = {1'h0, stq_execute_head} + 4'h1; // @[util.scala:203:14] wire [3:0] _stq_execute_head_T; // @[util.scala:203:14] assign _stq_execute_head_T = _GEN_218; // @[util.scala:203:14] wire [3:0] _stq_execute_head_T_4; // @[util.scala:203:14] assign _stq_execute_head_T_4 = _GEN_218; // @[util.scala:203:14] wire [2:0] _stq_execute_head_T_1 = _stq_execute_head_T[2:0]; // @[util.scala:203:14] wire [2:0] _stq_execute_head_T_2 = _stq_execute_head_T_1; // @[util.scala:203:{14,20}] wire [2:0] _stq_execute_head_T_3 = dmem_req_fire_0 ? _stq_execute_head_T_2 : stq_execute_head; // @[util.scala:203:20] wire _GEN_219 = will_fire_load_incoming_0 | will_fire_load_retry_0; // @[lsu.scala:218:29, :370:38, :378:38, :767:39, :774:43, :781:45] assign dmem_req_0_bits_uop_uopc = _GEN_219 ? exe_tlb_uop_0_uopc : will_fire_store_commit_0 ? _GEN_1[stq_execute_head] : will_fire_load_wakeup_0 ? mem_ldq_wakeup_e_out_bits_uop_uopc : 7'h0; // @[util.scala:106:23] assign dmem_req_0_bits_uop_inst = _GEN_219 ? exe_tlb_uop_0_inst : will_fire_store_commit_0 ? _GEN_2[stq_execute_head] : will_fire_load_wakeup_0 ? mem_ldq_wakeup_e_out_bits_uop_inst : 32'h0; // @[util.scala:106:23] assign dmem_req_0_bits_uop_debug_inst = _GEN_219 ? exe_tlb_uop_0_debug_inst : will_fire_store_commit_0 ? _GEN_3[stq_execute_head] : will_fire_load_wakeup_0 ? mem_ldq_wakeup_e_out_bits_uop_debug_inst : 32'h0; // @[util.scala:106:23] assign dmem_req_0_bits_uop_is_rvc = _GEN_219 ? exe_tlb_uop_0_is_rvc : will_fire_store_commit_0 ? _GEN_4[stq_execute_head] : will_fire_load_wakeup_0 & mem_ldq_wakeup_e_out_bits_uop_is_rvc; // @[util.scala:106:23] assign dmem_req_0_bits_uop_debug_pc = _GEN_219 ? exe_tlb_uop_0_debug_pc : will_fire_store_commit_0 ? _GEN_5[stq_execute_head] : will_fire_load_wakeup_0 ? mem_ldq_wakeup_e_out_bits_uop_debug_pc : 40'h0; // @[util.scala:106:23] assign dmem_req_0_bits_uop_iq_type = _GEN_219 ? exe_tlb_uop_0_iq_type : will_fire_store_commit_0 ? _GEN_6[stq_execute_head] : will_fire_load_wakeup_0 ? mem_ldq_wakeup_e_out_bits_uop_iq_type : 3'h0; // @[util.scala:106:23] assign dmem_req_0_bits_uop_fu_code = _GEN_219 ? exe_tlb_uop_0_fu_code : will_fire_store_commit_0 ? _GEN_7[stq_execute_head] : will_fire_load_wakeup_0 ? mem_ldq_wakeup_e_out_bits_uop_fu_code : 10'h0; // @[util.scala:106:23] assign dmem_req_0_bits_uop_ctrl_br_type = _GEN_219 ? exe_tlb_uop_0_ctrl_br_type : will_fire_store_commit_0 ? _GEN_8[stq_execute_head] : will_fire_load_wakeup_0 ? mem_ldq_wakeup_e_out_bits_uop_ctrl_br_type : 4'h0; // @[util.scala:106:23] assign dmem_req_0_bits_uop_ctrl_op1_sel = _GEN_219 ? exe_tlb_uop_0_ctrl_op1_sel : will_fire_store_commit_0 ? _GEN_9[stq_execute_head] : will_fire_load_wakeup_0 ? mem_ldq_wakeup_e_out_bits_uop_ctrl_op1_sel : 2'h0; // @[util.scala:106:23] assign dmem_req_0_bits_uop_ctrl_op2_sel = _GEN_219 ? exe_tlb_uop_0_ctrl_op2_sel : will_fire_store_commit_0 ? _GEN_10[stq_execute_head] : will_fire_load_wakeup_0 ? mem_ldq_wakeup_e_out_bits_uop_ctrl_op2_sel : 3'h0; // @[util.scala:106:23] assign dmem_req_0_bits_uop_ctrl_imm_sel = _GEN_219 ? exe_tlb_uop_0_ctrl_imm_sel : will_fire_store_commit_0 ? _GEN_11[stq_execute_head] : will_fire_load_wakeup_0 ? mem_ldq_wakeup_e_out_bits_uop_ctrl_imm_sel : 3'h0; // @[util.scala:106:23] assign dmem_req_0_bits_uop_ctrl_op_fcn = _GEN_219 ? exe_tlb_uop_0_ctrl_op_fcn : will_fire_store_commit_0 ? _GEN_12[stq_execute_head] : will_fire_load_wakeup_0 ? mem_ldq_wakeup_e_out_bits_uop_ctrl_op_fcn : 5'h0; // @[util.scala:106:23] assign dmem_req_0_bits_uop_ctrl_fcn_dw = _GEN_219 ? exe_tlb_uop_0_ctrl_fcn_dw : will_fire_store_commit_0 ? _GEN_13[stq_execute_head] : will_fire_load_wakeup_0 & mem_ldq_wakeup_e_out_bits_uop_ctrl_fcn_dw; // @[util.scala:106:23] assign dmem_req_0_bits_uop_ctrl_csr_cmd = _GEN_219 ? exe_tlb_uop_0_ctrl_csr_cmd : will_fire_store_commit_0 ? _GEN_14[stq_execute_head] : will_fire_load_wakeup_0 ? mem_ldq_wakeup_e_out_bits_uop_ctrl_csr_cmd : 3'h0; // @[util.scala:106:23] assign dmem_req_0_bits_uop_ctrl_is_load = _GEN_219 ? exe_tlb_uop_0_ctrl_is_load : will_fire_store_commit_0 ? _GEN_15[stq_execute_head] : will_fire_load_wakeup_0 & mem_ldq_wakeup_e_out_bits_uop_ctrl_is_load; // @[util.scala:106:23] assign dmem_req_0_bits_uop_ctrl_is_sta = _GEN_219 ? exe_tlb_uop_0_ctrl_is_sta : will_fire_store_commit_0 ? _GEN_16[stq_execute_head] : will_fire_load_wakeup_0 & mem_ldq_wakeup_e_out_bits_uop_ctrl_is_sta; // @[util.scala:106:23] assign dmem_req_0_bits_uop_ctrl_is_std = _GEN_219 ? exe_tlb_uop_0_ctrl_is_std : will_fire_store_commit_0 ? _GEN_17[stq_execute_head] : will_fire_load_wakeup_0 & mem_ldq_wakeup_e_out_bits_uop_ctrl_is_std; // @[util.scala:106:23] assign dmem_req_0_bits_uop_iw_state = _GEN_219 ? exe_tlb_uop_0_iw_state : will_fire_store_commit_0 ? _GEN_18[stq_execute_head] : will_fire_load_wakeup_0 ? mem_ldq_wakeup_e_out_bits_uop_iw_state : 2'h0; // @[util.scala:106:23] assign dmem_req_0_bits_uop_iw_p1_poisoned = _GEN_219 ? exe_tlb_uop_0_iw_p1_poisoned : will_fire_store_commit_0 ? _GEN_19[stq_execute_head] : will_fire_load_wakeup_0 & mem_ldq_wakeup_e_out_bits_uop_iw_p1_poisoned; // @[util.scala:106:23] assign dmem_req_0_bits_uop_iw_p2_poisoned = _GEN_219 ? exe_tlb_uop_0_iw_p2_poisoned : will_fire_store_commit_0 ? _GEN_20[stq_execute_head] : will_fire_load_wakeup_0 & mem_ldq_wakeup_e_out_bits_uop_iw_p2_poisoned; // @[util.scala:106:23] assign dmem_req_0_bits_uop_is_br = _GEN_219 ? exe_tlb_uop_0_is_br : will_fire_store_commit_0 ? _GEN_21[stq_execute_head] : will_fire_load_wakeup_0 & mem_ldq_wakeup_e_out_bits_uop_is_br; // @[util.scala:106:23] assign dmem_req_0_bits_uop_is_jalr = _GEN_219 ? exe_tlb_uop_0_is_jalr : will_fire_store_commit_0 ? _GEN_22[stq_execute_head] : will_fire_load_wakeup_0 & mem_ldq_wakeup_e_out_bits_uop_is_jalr; // @[util.scala:106:23] assign dmem_req_0_bits_uop_is_jal = _GEN_219 ? exe_tlb_uop_0_is_jal : will_fire_store_commit_0 ? _GEN_23[stq_execute_head] : will_fire_load_wakeup_0 & mem_ldq_wakeup_e_out_bits_uop_is_jal; // @[util.scala:106:23] assign dmem_req_0_bits_uop_is_sfb = _GEN_219 ? exe_tlb_uop_0_is_sfb : will_fire_store_commit_0 ? _GEN_24[stq_execute_head] : will_fire_load_wakeup_0 & mem_ldq_wakeup_e_out_bits_uop_is_sfb; // @[util.scala:106:23] assign dmem_req_0_bits_uop_br_mask = _GEN_219 ? exe_tlb_uop_0_br_mask : will_fire_store_commit_0 ? _GEN_25[stq_execute_head] : will_fire_load_wakeup_0 ? _GEN_118[_ldq_wakeup_e_T_1] : 8'h0; // @[lsu.scala:218:29, :222:42, :263:49, :380:38, :381:38, :501:88, :750:22, :760:28, :767:39, :770:30, :774:43, :777:30, :781:45, :788:33, :795:44, :798:30] assign dmem_req_0_bits_uop_br_tag = _GEN_219 ? exe_tlb_uop_0_br_tag : will_fire_store_commit_0 ? _GEN_26[stq_execute_head] : will_fire_load_wakeup_0 ? mem_ldq_wakeup_e_out_bits_uop_br_tag : 3'h0; // @[util.scala:106:23] assign dmem_req_0_bits_uop_ftq_idx = _GEN_219 ? exe_tlb_uop_0_ftq_idx : will_fire_store_commit_0 ? _GEN_27[stq_execute_head] : will_fire_load_wakeup_0 ? mem_ldq_wakeup_e_out_bits_uop_ftq_idx : 4'h0; // @[util.scala:106:23] assign dmem_req_0_bits_uop_edge_inst = _GEN_219 ? exe_tlb_uop_0_edge_inst : will_fire_store_commit_0 ? _GEN_28[stq_execute_head] : will_fire_load_wakeup_0 & mem_ldq_wakeup_e_out_bits_uop_edge_inst; // @[util.scala:106:23] assign dmem_req_0_bits_uop_pc_lob = _GEN_219 ? exe_tlb_uop_0_pc_lob : will_fire_store_commit_0 ? _GEN_29[stq_execute_head] : will_fire_load_wakeup_0 ? mem_ldq_wakeup_e_out_bits_uop_pc_lob : 6'h0; // @[util.scala:106:23] assign dmem_req_0_bits_uop_taken = _GEN_219 ? exe_tlb_uop_0_taken : will_fire_store_commit_0 ? _GEN_30[stq_execute_head] : will_fire_load_wakeup_0 & mem_ldq_wakeup_e_out_bits_uop_taken; // @[util.scala:106:23] assign dmem_req_0_bits_uop_imm_packed = _GEN_219 ? exe_tlb_uop_0_imm_packed : will_fire_store_commit_0 ? _GEN_31[stq_execute_head] : will_fire_load_wakeup_0 ? mem_ldq_wakeup_e_out_bits_uop_imm_packed : 20'h0; // @[util.scala:106:23] assign dmem_req_0_bits_uop_csr_addr = _GEN_219 ? exe_tlb_uop_0_csr_addr : will_fire_store_commit_0 ? _GEN_32[stq_execute_head] : will_fire_load_wakeup_0 ? mem_ldq_wakeup_e_out_bits_uop_csr_addr : 12'h0; // @[util.scala:106:23] assign dmem_req_0_bits_uop_rob_idx = _GEN_219 ? exe_tlb_uop_0_rob_idx : will_fire_store_commit_0 ? _GEN_33[stq_execute_head] : will_fire_load_wakeup_0 ? mem_ldq_wakeup_e_out_bits_uop_rob_idx : 5'h0; // @[util.scala:106:23] assign dmem_req_0_bits_uop_ldq_idx = _GEN_219 ? exe_tlb_uop_0_ldq_idx : will_fire_store_commit_0 ? _GEN_34[stq_execute_head] : will_fire_load_wakeup_0 ? mem_ldq_wakeup_e_out_bits_uop_ldq_idx : 3'h0; // @[util.scala:106:23] assign dmem_req_0_bits_uop_stq_idx = _GEN_219 ? exe_tlb_uop_0_stq_idx : will_fire_store_commit_0 ? _GEN_35[stq_execute_head] : will_fire_load_wakeup_0 ? mem_ldq_wakeup_e_out_bits_uop_stq_idx : 3'h0; // @[util.scala:106:23] assign dmem_req_0_bits_uop_rxq_idx = _GEN_219 ? exe_tlb_uop_0_rxq_idx : will_fire_store_commit_0 ? _GEN_36[stq_execute_head] : will_fire_load_wakeup_0 ? mem_ldq_wakeup_e_out_bits_uop_rxq_idx : 2'h0; // @[util.scala:106:23] assign dmem_req_0_bits_uop_pdst = _GEN_219 ? exe_tlb_uop_0_pdst : will_fire_store_commit_0 ? _GEN_37[stq_execute_head] : will_fire_load_wakeup_0 ? mem_ldq_wakeup_e_out_bits_uop_pdst : 6'h0; // @[util.scala:106:23] assign dmem_req_0_bits_uop_prs1 = _GEN_219 ? exe_tlb_uop_0_prs1 : will_fire_store_commit_0 ? _GEN_38[stq_execute_head] : will_fire_load_wakeup_0 ? mem_ldq_wakeup_e_out_bits_uop_prs1 : 6'h0; // @[util.scala:106:23] assign dmem_req_0_bits_uop_prs2 = _GEN_219 ? exe_tlb_uop_0_prs2 : will_fire_store_commit_0 ? _GEN_39[stq_execute_head] : will_fire_load_wakeup_0 ? mem_ldq_wakeup_e_out_bits_uop_prs2 : 6'h0; // @[util.scala:106:23] assign dmem_req_0_bits_uop_prs3 = _GEN_219 ? exe_tlb_uop_0_prs3 : will_fire_store_commit_0 ? _GEN_40[stq_execute_head] : will_fire_load_wakeup_0 ? mem_ldq_wakeup_e_out_bits_uop_prs3 : 6'h0; // @[util.scala:106:23] assign dmem_req_0_bits_uop_ppred = _GEN_219 ? exe_tlb_uop_0_ppred : will_fire_store_commit_0 ? _GEN_41[stq_execute_head] : 4'h0; // @[lsu.scala:218:29, :222:42, :263:49, :380:38, :750:22, :767:39, :770:30, :774:43, :777:30, :781:45, :788:33, :795:44] assign dmem_req_0_bits_uop_prs1_busy = _GEN_219 ? exe_tlb_uop_0_prs1_busy : will_fire_store_commit_0 ? _GEN_42[stq_execute_head] : will_fire_load_wakeup_0 & mem_ldq_wakeup_e_out_bits_uop_prs1_busy; // @[util.scala:106:23] assign dmem_req_0_bits_uop_prs2_busy = _GEN_219 ? exe_tlb_uop_0_prs2_busy : will_fire_store_commit_0 ? _GEN_43[stq_execute_head] : will_fire_load_wakeup_0 & mem_ldq_wakeup_e_out_bits_uop_prs2_busy; // @[util.scala:106:23] assign dmem_req_0_bits_uop_prs3_busy = _GEN_219 ? exe_tlb_uop_0_prs3_busy : will_fire_store_commit_0 ? _GEN_44[stq_execute_head] : will_fire_load_wakeup_0 & mem_ldq_wakeup_e_out_bits_uop_prs3_busy; // @[util.scala:106:23] assign dmem_req_0_bits_uop_ppred_busy = _GEN_219 ? exe_tlb_uop_0_ppred_busy : will_fire_store_commit_0 & _GEN_45[stq_execute_head]; // @[lsu.scala:218:29, :222:42, :263:49, :380:38, :750:22, :767:39, :770:30, :774:43, :777:30, :781:45, :788:33, :795:44] assign dmem_req_0_bits_uop_stale_pdst = _GEN_219 ? exe_tlb_uop_0_stale_pdst : will_fire_store_commit_0 ? _GEN_46[stq_execute_head] : will_fire_load_wakeup_0 ? mem_ldq_wakeup_e_out_bits_uop_stale_pdst : 6'h0; // @[util.scala:106:23] assign dmem_req_0_bits_uop_exception = _GEN_219 ? exe_tlb_uop_0_exception : will_fire_store_commit_0 ? _GEN_48 : will_fire_load_wakeup_0 & mem_ldq_wakeup_e_out_bits_uop_exception; // @[util.scala:106:23] assign dmem_req_0_bits_uop_exc_cause = _GEN_219 ? exe_tlb_uop_0_exc_cause : will_fire_store_commit_0 ? _GEN_49[stq_execute_head] : will_fire_load_wakeup_0 ? mem_ldq_wakeup_e_out_bits_uop_exc_cause : 64'h0; // @[util.scala:106:23] assign dmem_req_0_bits_uop_bypassable = _GEN_219 ? exe_tlb_uop_0_bypassable : will_fire_store_commit_0 ? _GEN_50[stq_execute_head] : will_fire_load_wakeup_0 & mem_ldq_wakeup_e_out_bits_uop_bypassable; // @[util.scala:106:23] assign dmem_req_0_bits_uop_is_fence = _GEN_219 ? exe_tlb_uop_0_is_fence : will_fire_store_commit_0 ? _GEN_55 : will_fire_load_wakeup_0 & mem_ldq_wakeup_e_out_bits_uop_is_fence; // @[util.scala:106:23] assign dmem_req_0_bits_uop_is_fencei = _GEN_219 ? exe_tlb_uop_0_is_fencei : will_fire_store_commit_0 ? _GEN_56[stq_execute_head] : will_fire_load_wakeup_0 & mem_ldq_wakeup_e_out_bits_uop_is_fencei; // @[util.scala:106:23] assign dmem_req_0_bits_uop_is_amo = _GEN_219 ? exe_tlb_uop_0_is_amo : will_fire_store_commit_0 ? _GEN_58 : will_fire_load_wakeup_0 & mem_ldq_wakeup_e_out_bits_uop_is_amo; // @[util.scala:106:23] assign dmem_req_0_bits_uop_uses_ldq = _GEN_219 ? exe_tlb_uop_0_uses_ldq : will_fire_store_commit_0 ? _GEN_59[stq_execute_head] : will_fire_load_wakeup_0 & mem_ldq_wakeup_e_out_bits_uop_uses_ldq; // @[util.scala:106:23] assign dmem_req_0_bits_uop_uses_stq = _GEN_219 ? exe_tlb_uop_0_uses_stq : will_fire_store_commit_0 ? _GEN_60[stq_execute_head] : will_fire_load_wakeup_0 & mem_ldq_wakeup_e_out_bits_uop_uses_stq; // @[util.scala:106:23] assign dmem_req_0_bits_uop_is_sys_pc2epc = _GEN_219 ? exe_tlb_uop_0_is_sys_pc2epc : will_fire_store_commit_0 ? _GEN_61[stq_execute_head] : will_fire_load_wakeup_0 & mem_ldq_wakeup_e_out_bits_uop_is_sys_pc2epc; // @[util.scala:106:23] assign dmem_req_0_bits_uop_is_unique = _GEN_219 ? exe_tlb_uop_0_is_unique : will_fire_store_commit_0 ? _GEN_62[stq_execute_head] : will_fire_load_wakeup_0 & mem_ldq_wakeup_e_out_bits_uop_is_unique; // @[util.scala:106:23] assign dmem_req_0_bits_uop_flush_on_commit = _GEN_219 ? exe_tlb_uop_0_flush_on_commit : will_fire_store_commit_0 ? _GEN_63[stq_execute_head] : will_fire_load_wakeup_0 & mem_ldq_wakeup_e_out_bits_uop_flush_on_commit; // @[util.scala:106:23] assign dmem_req_0_bits_uop_ldst_is_rs1 = _GEN_219 ? exe_tlb_uop_0_ldst_is_rs1 : will_fire_store_commit_0 ? _GEN_64[stq_execute_head] : will_fire_load_wakeup_0 & mem_ldq_wakeup_e_out_bits_uop_ldst_is_rs1; // @[util.scala:106:23] assign dmem_req_0_bits_uop_ldst = _GEN_219 ? exe_tlb_uop_0_ldst : will_fire_store_commit_0 ? _GEN_65[stq_execute_head] : will_fire_load_wakeup_0 ? mem_ldq_wakeup_e_out_bits_uop_ldst : 6'h0; // @[util.scala:106:23] assign dmem_req_0_bits_uop_lrs1 = _GEN_219 ? exe_tlb_uop_0_lrs1 : will_fire_store_commit_0 ? _GEN_66[stq_execute_head] : will_fire_load_wakeup_0 ? mem_ldq_wakeup_e_out_bits_uop_lrs1 : 6'h0; // @[util.scala:106:23] assign dmem_req_0_bits_uop_lrs2 = _GEN_219 ? exe_tlb_uop_0_lrs2 : will_fire_store_commit_0 ? _GEN_67[stq_execute_head] : will_fire_load_wakeup_0 ? mem_ldq_wakeup_e_out_bits_uop_lrs2 : 6'h0; // @[util.scala:106:23] assign dmem_req_0_bits_uop_lrs3 = _GEN_219 ? exe_tlb_uop_0_lrs3 : will_fire_store_commit_0 ? _GEN_68[stq_execute_head] : will_fire_load_wakeup_0 ? mem_ldq_wakeup_e_out_bits_uop_lrs3 : 6'h0; // @[util.scala:106:23] assign dmem_req_0_bits_uop_ldst_val = _GEN_219 ? exe_tlb_uop_0_ldst_val : will_fire_store_commit_0 ? _GEN_69[stq_execute_head] : will_fire_load_wakeup_0 & mem_ldq_wakeup_e_out_bits_uop_ldst_val; // @[util.scala:106:23] assign dmem_req_0_bits_uop_dst_rtype = _GEN_219 ? exe_tlb_uop_0_dst_rtype : will_fire_store_commit_0 ? _GEN_70[stq_execute_head] : will_fire_load_wakeup_0 ? mem_ldq_wakeup_e_out_bits_uop_dst_rtype : 2'h2; // @[util.scala:106:23] assign dmem_req_0_bits_uop_lrs1_rtype = _GEN_219 ? exe_tlb_uop_0_lrs1_rtype : will_fire_store_commit_0 ? _GEN_71[stq_execute_head] : will_fire_load_wakeup_0 ? mem_ldq_wakeup_e_out_bits_uop_lrs1_rtype : 2'h0; // @[util.scala:106:23] assign dmem_req_0_bits_uop_lrs2_rtype = _GEN_219 ? exe_tlb_uop_0_lrs2_rtype : will_fire_store_commit_0 ? _GEN_72[stq_execute_head] : will_fire_load_wakeup_0 ? mem_ldq_wakeup_e_out_bits_uop_lrs2_rtype : 2'h0; // @[util.scala:106:23] assign dmem_req_0_bits_uop_frs3_en = _GEN_219 ? exe_tlb_uop_0_frs3_en : will_fire_store_commit_0 ? _GEN_73[stq_execute_head] : will_fire_load_wakeup_0 & mem_ldq_wakeup_e_out_bits_uop_frs3_en; // @[util.scala:106:23] assign dmem_req_0_bits_uop_fp_val = _GEN_219 ? exe_tlb_uop_0_fp_val : will_fire_store_commit_0 ? _GEN_74[stq_execute_head] : will_fire_load_wakeup_0 & mem_ldq_wakeup_e_out_bits_uop_fp_val; // @[util.scala:106:23] assign dmem_req_0_bits_uop_fp_single = _GEN_219 ? exe_tlb_uop_0_fp_single : will_fire_store_commit_0 ? _GEN_75[stq_execute_head] : will_fire_load_wakeup_0 & mem_ldq_wakeup_e_out_bits_uop_fp_single; // @[util.scala:106:23] assign dmem_req_0_bits_uop_xcpt_pf_if = _GEN_219 ? exe_tlb_uop_0_xcpt_pf_if : will_fire_store_commit_0 ? _GEN_76[stq_execute_head] : will_fire_load_wakeup_0 & mem_ldq_wakeup_e_out_bits_uop_xcpt_pf_if; // @[util.scala:106:23] assign dmem_req_0_bits_uop_xcpt_ae_if = _GEN_219 ? exe_tlb_uop_0_xcpt_ae_if : will_fire_store_commit_0 ? _GEN_77[stq_execute_head] : will_fire_load_wakeup_0 & mem_ldq_wakeup_e_out_bits_uop_xcpt_ae_if; // @[util.scala:106:23] assign dmem_req_0_bits_uop_xcpt_ma_if = _GEN_219 ? exe_tlb_uop_0_xcpt_ma_if : will_fire_store_commit_0 ? _GEN_78[stq_execute_head] : will_fire_load_wakeup_0 & mem_ldq_wakeup_e_out_bits_uop_xcpt_ma_if; // @[util.scala:106:23] assign dmem_req_0_bits_uop_bp_debug_if = _GEN_219 ? exe_tlb_uop_0_bp_debug_if : will_fire_store_commit_0 ? _GEN_79[stq_execute_head] : will_fire_load_wakeup_0 & mem_ldq_wakeup_e_out_bits_uop_bp_debug_if; // @[util.scala:106:23] assign dmem_req_0_bits_uop_bp_xcpt_if = _GEN_219 ? exe_tlb_uop_0_bp_xcpt_if : will_fire_store_commit_0 ? _GEN_80[stq_execute_head] : will_fire_load_wakeup_0 & mem_ldq_wakeup_e_out_bits_uop_bp_xcpt_if; // @[util.scala:106:23] assign dmem_req_0_bits_uop_debug_fsrc = _GEN_219 ? exe_tlb_uop_0_debug_fsrc : will_fire_store_commit_0 ? _GEN_81[stq_execute_head] : will_fire_load_wakeup_0 ? mem_ldq_wakeup_e_out_bits_uop_debug_fsrc : 2'h0; // @[util.scala:106:23] assign dmem_req_0_bits_uop_debug_tsrc = _GEN_219 ? exe_tlb_uop_0_debug_tsrc : will_fire_store_commit_0 ? _GEN_82[stq_execute_head] : will_fire_load_wakeup_0 ? mem_ldq_wakeup_e_out_bits_uop_debug_tsrc : 2'h0; // @[util.scala:106:23] assign s0_executing_loads_0 = will_fire_load_incoming_0 ? ldq_incoming_idx_0 == 3'h0 & dmem_req_fire_0 : will_fire_load_retry_0 ? _GEN_210 & dmem_req_fire_0 : ~will_fire_store_commit_0 & will_fire_load_wakeup_0 & _GEN_203 & dmem_req_fire_0; // @[lsu.scala:218:29, :263:49, :370:38, :378:38, :380:38, :381:38, :569:49, :573:49, :755:36, :767:39, :772:47, :774:43, :779:41, :781:45, :795:44, :800:42] assign s0_executing_loads_1 = will_fire_load_incoming_0 ? ldq_incoming_idx_0 == 3'h1 & dmem_req_fire_0 : will_fire_load_retry_0 ? _GEN_211 & dmem_req_fire_0 : ~will_fire_store_commit_0 & will_fire_load_wakeup_0 & _GEN_204 & dmem_req_fire_0; // @[lsu.scala:218:29, :263:49, :370:38, :378:38, :380:38, :381:38, :569:49, :573:49, :755:36, :767:39, :772:47, :774:43, :779:41, :781:45, :795:44, :800:42] assign s0_executing_loads_2 = will_fire_load_incoming_0 ? ldq_incoming_idx_0 == 3'h2 & dmem_req_fire_0 : will_fire_load_retry_0 ? _GEN_212 & dmem_req_fire_0 : ~will_fire_store_commit_0 & will_fire_load_wakeup_0 & _GEN_205 & dmem_req_fire_0; // @[lsu.scala:218:29, :263:49, :370:38, :378:38, :380:38, :381:38, :569:49, :573:49, :755:36, :767:39, :772:47, :774:43, :779:41, :781:45, :795:44, :800:42] assign s0_executing_loads_3 = will_fire_load_incoming_0 ? ldq_incoming_idx_0 == 3'h3 & dmem_req_fire_0 : will_fire_load_retry_0 ? _GEN_213 & dmem_req_fire_0 : ~will_fire_store_commit_0 & will_fire_load_wakeup_0 & _GEN_206 & dmem_req_fire_0; // @[lsu.scala:218:29, :263:49, :370:38, :378:38, :380:38, :381:38, :569:49, :573:49, :755:36, :767:39, :772:47, :774:43, :779:41, :781:45, :795:44, :800:42] assign s0_executing_loads_4 = will_fire_load_incoming_0 ? ldq_incoming_idx_0 == 3'h4 & dmem_req_fire_0 : will_fire_load_retry_0 ? _GEN_214 & dmem_req_fire_0 : ~will_fire_store_commit_0 & will_fire_load_wakeup_0 & _GEN_207 & dmem_req_fire_0; // @[lsu.scala:218:29, :263:49, :370:38, :378:38, :380:38, :381:38, :569:49, :573:49, :755:36, :767:39, :772:47, :774:43, :779:41, :781:45, :795:44, :800:42] assign s0_executing_loads_5 = will_fire_load_incoming_0 ? ldq_incoming_idx_0 == 3'h5 & dmem_req_fire_0 : will_fire_load_retry_0 ? _GEN_215 & dmem_req_fire_0 : ~will_fire_store_commit_0 & will_fire_load_wakeup_0 & _GEN_208 & dmem_req_fire_0; // @[lsu.scala:218:29, :263:49, :370:38, :378:38, :380:38, :381:38, :569:49, :573:49, :755:36, :767:39, :772:47, :774:43, :779:41, :781:45, :795:44, :800:42] assign s0_executing_loads_6 = will_fire_load_incoming_0 ? ldq_incoming_idx_0 == 3'h6 & dmem_req_fire_0 : will_fire_load_retry_0 ? _GEN_216 & dmem_req_fire_0 : ~will_fire_store_commit_0 & will_fire_load_wakeup_0 & _GEN_209 & dmem_req_fire_0; // @[lsu.scala:218:29, :263:49, :370:38, :378:38, :380:38, :381:38, :569:49, :573:49, :755:36, :767:39, :772:47, :774:43, :779:41, :781:45, :795:44, :800:42] assign s0_executing_loads_7 = will_fire_load_incoming_0 ? (&ldq_incoming_idx_0) & dmem_req_fire_0 : will_fire_load_retry_0 ? (&ldq_retry_idx) & dmem_req_fire_0 : ~will_fire_store_commit_0 & will_fire_load_wakeup_0 & (&ldq_wakeup_idx) & dmem_req_fire_0; // @[lsu.scala:218:29, :263:49, :370:38, :378:38, :380:38, :381:38, :414:30, :429:31, :569:49, :573:49, :755:36, :767:39, :772:47, :774:43, :779:41, :781:45, :795:44, :800:42] wire _dmem_req_0_valid_T_6 = ~io_hellacache_s1_kill_0; // @[lsu.scala:201:7, :806:42] wire _dmem_req_0_valid_T_9 = _dmem_req_0_valid_T_6; // @[lsu.scala:806:{42,65}] wire _dmem_req_0_valid_T_7 = ~exe_tlb_miss_0; // @[lsu.scala:263:49, :768:33, :806:69] wire _GEN_220 = will_fire_store_commit_0 | will_fire_load_wakeup_0; // @[lsu.scala:243:34, :380:38, :381:38, :781:45, :795:44, :803:47] assign dmem_req_0_valid = will_fire_load_incoming_0 ? _dmem_req_0_valid_T_2 : will_fire_load_retry_0 ? _dmem_req_0_valid_T_5 : _GEN_220 | (will_fire_hella_incoming_0 ? _dmem_req_0_valid_T_9 : will_fire_hella_wakeup_0); // @[lsu.scala:243:34, :370:38, :375:38, :376:38, :378:38, :750:22, :767:39, :768:{30,50}, :774:43, :775:{30,50}, :781:45, :782:33, :795:44, :796:30, :803:47, :806:{39,65}, :820:5] assign dmem_req_0_bits_addr = will_fire_load_incoming_0 | will_fire_load_retry_0 ? _GEN_217 : will_fire_store_commit_0 ? _GEN_84[stq_execute_head] : will_fire_load_wakeup_0 ? mem_ldq_wakeup_e_out_bits_addr_bits : will_fire_hella_incoming_0 ? _GEN_217 : will_fire_hella_wakeup_0 ? {8'h0, hella_paddr} : 40'h0; // @[util.scala:106:23] wire [7:0] _dmem_req_0_bits_data_T_31 = hella_data_data[7:0]; // @[AMOALU.scala:29:69] wire [15:0] _dmem_req_0_bits_data_T_32 = {2{_dmem_req_0_bits_data_T_31}}; // @[AMOALU.scala:29:{32,69}] wire [31:0] _dmem_req_0_bits_data_T_33 = {2{_dmem_req_0_bits_data_T_32}}; // @[AMOALU.scala:29:32] wire [63:0] _dmem_req_0_bits_data_T_34 = {2{_dmem_req_0_bits_data_T_33}}; // @[AMOALU.scala:29:32] wire [15:0] _dmem_req_0_bits_data_T_36 = hella_data_data[15:0]; // @[AMOALU.scala:29:69] wire [31:0] _dmem_req_0_bits_data_T_37 = {2{_dmem_req_0_bits_data_T_36}}; // @[AMOALU.scala:29:{32,69}] wire [63:0] _dmem_req_0_bits_data_T_38 = {2{_dmem_req_0_bits_data_T_37}}; // @[AMOALU.scala:29:32] wire [31:0] _dmem_req_0_bits_data_T_40 = hella_data_data[31:0]; // @[AMOALU.scala:29:69] wire [63:0] _dmem_req_0_bits_data_T_41 = {2{_dmem_req_0_bits_data_T_40}}; // @[AMOALU.scala:29:{32,69}] wire [63:0] _dmem_req_0_bits_data_T_43 = _dmem_req_0_bits_data_T_42; // @[AMOALU.scala:29:13] wire [63:0] _dmem_req_0_bits_data_T_44 = _dmem_req_0_bits_data_T_43; // @[AMOALU.scala:29:13] assign dmem_req_0_bits_data = _GEN_219 ? 64'h0 : will_fire_store_commit_0 ? _dmem_req_0_bits_data_T_14 : will_fire_load_wakeup_0 | will_fire_hella_incoming_0 | ~will_fire_hella_wakeup_0 ? 64'h0 : _dmem_req_0_bits_data_T_44; // @[AMOALU.scala:29:13] assign dmem_req_0_bits_uop_mem_cmd = _GEN_219 ? exe_tlb_uop_0_mem_cmd : will_fire_store_commit_0 ? _GEN_51[stq_execute_head] : will_fire_load_wakeup_0 ? mem_ldq_wakeup_e_out_bits_uop_mem_cmd : 5'h0; // @[util.scala:106:23] assign dmem_req_0_bits_uop_mem_size = _GEN_219 ? exe_tlb_uop_0_mem_size : will_fire_store_commit_0 ? dmem_req_0_bits_data_size : will_fire_load_wakeup_0 ? mem_ldq_wakeup_e_out_bits_uop_mem_size : {2{will_fire_hella_incoming_0 | will_fire_hella_wakeup_0}}; // @[AMOALU.scala:11:18] assign dmem_req_0_bits_uop_mem_signed = _GEN_219 ? exe_tlb_uop_0_mem_signed : will_fire_store_commit_0 ? _GEN_53[stq_execute_head] : will_fire_load_wakeup_0 & mem_ldq_wakeup_e_out_bits_uop_mem_signed; // @[util.scala:106:23] assign dmem_req_0_bits_is_hella = ~(_GEN_219 | will_fire_store_commit_0 | will_fire_load_wakeup_0) & (will_fire_hella_incoming_0 | will_fire_hella_wakeup_0); // @[lsu.scala:218:29, :375:38, :376:38, :380:38, :381:38, :750:22, :763:31, :767:39, :774:43, :781:45, :795:44, :803:47, :815:39, :820:5] wire _T_146 = will_fire_load_incoming_0 | will_fire_load_retry_0; // @[lsu.scala:370:38, :378:38, :836:38] wire [2:0] ldq_idx = will_fire_load_incoming_0 ? ldq_incoming_idx_0 : ldq_retry_idx; // @[lsu.scala:263:49, :370:38, :414:30, :838:24] wire [39:0] _GEN_221 = exe_tlb_miss_0 ? exe_tlb_vaddr_0 : _GEN_217; // @[lsu.scala:263:49, :769:30, :840:51] wire [39:0] _ldq_bits_addr_bits_T; // @[lsu.scala:840:51] assign _ldq_bits_addr_bits_T = _GEN_221; // @[lsu.scala:840:51] wire [39:0] _stq_bits_addr_bits_T; // @[lsu.scala:855:42] assign _stq_bits_addr_bits_T = _GEN_221; // @[lsu.scala:840:51, :855:42] wire _ldq_bits_addr_is_uncacheable_T = ~exe_tlb_miss_0; // @[lsu.scala:263:49, :768:33, :843:74] wire _ldq_bits_addr_is_uncacheable_T_1 = exe_tlb_uncacheable_0 & _ldq_bits_addr_is_uncacheable_T; // @[lsu.scala:263:49, :843:{71,74}] wire _T_163 = _T_162 | will_fire_sta_retry_0; // @[lsu.scala:379:38, :661:56, :849:67] wire [2:0] stq_idx = _stq_idx_T ? stq_incoming_idx_0 : stq_retry_idx; // @[lsu.scala:263:49, :421:30, :851:{24,51}] wire _stq_bits_addr_valid_T = ~pf_st_0; // @[lsu.scala:263:49, :854:39] wire _io_core_fp_stdata_ready_T = ~will_fire_std_incoming_0; // @[lsu.scala:373:38, :867:34] wire _io_core_fp_stdata_ready_T_1 = ~will_fire_stad_incoming_0; // @[lsu.scala:371:38, :867:64] assign _io_core_fp_stdata_ready_T_2 = _io_core_fp_stdata_ready_T & _io_core_fp_stdata_ready_T_1; // @[lsu.scala:867:{34,61,64}] assign io_core_fp_stdata_ready_0 = _io_core_fp_stdata_ready_T_2; // @[lsu.scala:201:7, :867:61] wire _GEN_222 = io_core_fp_stdata_ready_0 & io_core_fp_stdata_valid_0; // @[Decoupled.scala:51:35] wire _fp_stdata_fire_T; // @[Decoupled.scala:51:35] assign _fp_stdata_fire_T = _GEN_222; // @[Decoupled.scala:51:35] wire will_fire_stdf_incoming; // @[Decoupled.scala:51:35] assign will_fire_stdf_incoming = _GEN_222; // @[Decoupled.scala:51:35] wire fp_stdata_fire = _fp_stdata_fire_T; // @[Decoupled.scala:51:35] wire _T_177 = will_fire_std_incoming_0 | will_fire_stad_incoming_0; // @[lsu.scala:371:38, :373:38, :869:37] wire _sidx_T; // @[lsu.scala:871:48] assign _sidx_T = _T_177; // @[lsu.scala:869:37, :871:48] wire _stq_bits_data_bits_T; // @[lsu.scala:875:66] assign _stq_bits_data_bits_T = _T_177; // @[lsu.scala:869:37, :875:66] wire _T_178 = _T_177 | fp_stdata_fire; // @[lsu.scala:868:49, :869:{37,67}] wire [2:0] sidx = _sidx_T ? stq_incoming_idx_0 : io_core_fp_stdata_bits_uop_stq_idx_0; // @[lsu.scala:201:7, :263:49, :871:{21,48}] wire [63:0] _stq_bits_data_bits_T_1 = _stq_bits_data_bits_T ? exe_req_0_bits_data : io_core_fp_stdata_bits_data_0; // @[lsu.scala:201:7, :383:25, :875:{39,66}] wire [7:0] _exe_req_killed_T = io_core_brupdate_b1_mispredict_mask_0 & exe_req_0_bits_uop_br_mask; // @[util.scala:118:51] wire _exe_req_killed_T_1 = |_exe_req_killed_T; // @[util.scala:118:{51,59}] wire exe_req_killed_0 = _exe_req_killed_T_1; // @[util.scala:118:59] wire [7:0] _stdf_killed_T = io_core_brupdate_b1_mispredict_mask_0 & io_core_fp_stdata_bits_uop_br_mask_0; // @[util.scala:118:51] wire stdf_killed = |_stdf_killed_T; // @[util.scala:118:{51,59}] wire _fired_load_incoming_T = ~exe_req_killed_0; // @[lsu.scala:263:49, :895:82] wire _fired_load_incoming_T_1 = will_fire_load_incoming_0 & _fired_load_incoming_T; // @[lsu.scala:370:38, :895:{79,82}] reg fired_load_incoming_REG; // @[lsu.scala:895:51] wire fired_load_incoming_0 = fired_load_incoming_REG; // @[lsu.scala:263:49, :895:51] wire _io_core_spec_ld_wakeup_0_valid_T = fired_load_incoming_0; // @[lsu.scala:263:49, :1259:69] wire _fired_stad_incoming_T = ~exe_req_killed_0; // @[lsu.scala:263:49, :895:82, :896:82] wire _fired_stad_incoming_T_1 = will_fire_stad_incoming_0 & _fired_stad_incoming_T; // @[lsu.scala:371:38, :896:{79,82}] reg fired_stad_incoming_REG; // @[lsu.scala:896:51] wire fired_stad_incoming_0 = fired_stad_incoming_REG; // @[lsu.scala:263:49, :896:51] wire _fired_sta_incoming_T = ~exe_req_killed_0; // @[lsu.scala:263:49, :895:82, :897:82] wire _fired_sta_incoming_T_1 = will_fire_sta_incoming_0 & _fired_sta_incoming_T; // @[lsu.scala:372:38, :897:{79,82}] reg fired_sta_incoming_REG; // @[lsu.scala:897:51] wire fired_sta_incoming_0 = fired_sta_incoming_REG; // @[lsu.scala:263:49, :897:51] wire _fired_std_incoming_T = ~exe_req_killed_0; // @[lsu.scala:263:49, :895:82, :898:82] wire _fired_std_incoming_T_1 = will_fire_std_incoming_0 & _fired_std_incoming_T; // @[lsu.scala:373:38, :898:{79,82}] reg fired_std_incoming_REG; // @[lsu.scala:898:51] wire fired_std_incoming_0 = fired_std_incoming_REG; // @[lsu.scala:263:49, :898:51] wire _fired_stdf_incoming_T = ~stdf_killed; // @[util.scala:118:59] wire _fired_stdf_incoming_T_1 = will_fire_stdf_incoming & _fired_stdf_incoming_T; // @[Decoupled.scala:51:35] reg fired_stdf_incoming; // @[lsu.scala:899:37] reg fired_sfence_0; // @[lsu.scala:900:37] reg fired_release_0; // @[lsu.scala:901:37] wire do_release_search_0 = fired_release_0; // @[lsu.scala:263:49, :901:37] wire lcam_is_release_0 = fired_release_0; // @[lsu.scala:263:49, :901:37] wire [7:0] _GEN_223 = io_core_brupdate_b1_mispredict_mask_0 & _GEN_118[_ldq_retry_e_T_1]; // @[util.scala:118:51] wire [7:0] _fired_load_retry_T; // @[util.scala:118:51] assign _fired_load_retry_T = _GEN_223; // @[util.scala:118:51] wire [7:0] _mem_ldq_retry_e_out_valid_T; // @[util.scala:118:51] assign _mem_ldq_retry_e_out_valid_T = _GEN_223; // @[util.scala:118:51] wire _fired_load_retry_T_1 = |_fired_load_retry_T; // @[util.scala:118:{51,59}] wire _fired_load_retry_T_2 = ~_fired_load_retry_T_1; // @[util.scala:118:59] wire _fired_load_retry_T_3 = will_fire_load_retry_0 & _fired_load_retry_T_2; // @[lsu.scala:378:38, :902:{79,82}] reg fired_load_retry_REG; // @[lsu.scala:902:51] wire fired_load_retry_0 = fired_load_retry_REG; // @[lsu.scala:263:49, :902:51] wire [7:0] _GEN_224 = io_core_brupdate_b1_mispredict_mask_0 & _GEN_25[_stq_retry_e_T_1]; // @[util.scala:118:51] wire [7:0] _fired_sta_retry_T; // @[util.scala:118:51] assign _fired_sta_retry_T = _GEN_224; // @[util.scala:118:51] wire [7:0] _mem_stq_retry_e_out_valid_T; // @[util.scala:118:51] assign _mem_stq_retry_e_out_valid_T = _GEN_224; // @[util.scala:118:51] wire _fired_sta_retry_T_1 = |_fired_sta_retry_T; // @[util.scala:118:{51,59}] wire _fired_sta_retry_T_2 = ~_fired_sta_retry_T_1; // @[util.scala:118:59] wire _fired_sta_retry_T_3 = will_fire_sta_retry_0 & _fired_sta_retry_T_2; // @[lsu.scala:379:38, :903:{79,82}] reg fired_sta_retry_REG; // @[lsu.scala:903:51] wire fired_sta_retry_0 = fired_sta_retry_REG; // @[lsu.scala:263:49, :903:51] reg fired_store_commit_0; // @[lsu.scala:904:37] wire [7:0] _GEN_225 = io_core_brupdate_b1_mispredict_mask_0 & _GEN_118[_ldq_wakeup_e_T_1]; // @[util.scala:118:51] wire [7:0] _fired_load_wakeup_T; // @[util.scala:118:51] assign _fired_load_wakeup_T = _GEN_225; // @[util.scala:118:51] wire [7:0] _mem_ldq_wakeup_e_out_valid_T; // @[util.scala:118:51] assign _mem_ldq_wakeup_e_out_valid_T = _GEN_225; // @[util.scala:118:51] wire _fired_load_wakeup_T_1 = |_fired_load_wakeup_T; // @[util.scala:118:{51,59}] wire _fired_load_wakeup_T_2 = ~_fired_load_wakeup_T_1; // @[util.scala:118:59] wire _fired_load_wakeup_T_3 = will_fire_load_wakeup_0 & _fired_load_wakeup_T_2; // @[lsu.scala:381:38, :905:{79,82}] reg fired_load_wakeup_REG; // @[lsu.scala:905:51] wire fired_load_wakeup_0 = fired_load_wakeup_REG; // @[lsu.scala:263:49, :905:51] reg fired_hella_incoming_0; // @[lsu.scala:906:37] reg fired_hella_wakeup_0; // @[lsu.scala:907:37] wire [6:0] _mem_incoming_uop_WIRE_0_uopc = mem_incoming_uop_out_uopc; // @[util.scala:96:23] wire [31:0] _mem_incoming_uop_WIRE_0_inst = mem_incoming_uop_out_inst; // @[util.scala:96:23] wire [31:0] _mem_incoming_uop_WIRE_0_debug_inst = mem_incoming_uop_out_debug_inst; // @[util.scala:96:23] wire _mem_incoming_uop_WIRE_0_is_rvc = mem_incoming_uop_out_is_rvc; // @[util.scala:96:23] wire [39:0] _mem_incoming_uop_WIRE_0_debug_pc = mem_incoming_uop_out_debug_pc; // @[util.scala:96:23] wire [2:0] _mem_incoming_uop_WIRE_0_iq_type = mem_incoming_uop_out_iq_type; // @[util.scala:96:23] wire [9:0] _mem_incoming_uop_WIRE_0_fu_code = mem_incoming_uop_out_fu_code; // @[util.scala:96:23] wire [3:0] _mem_incoming_uop_WIRE_0_ctrl_br_type = mem_incoming_uop_out_ctrl_br_type; // @[util.scala:96:23] wire [1:0] _mem_incoming_uop_WIRE_0_ctrl_op1_sel = mem_incoming_uop_out_ctrl_op1_sel; // @[util.scala:96:23] wire [2:0] _mem_incoming_uop_WIRE_0_ctrl_op2_sel = mem_incoming_uop_out_ctrl_op2_sel; // @[util.scala:96:23] wire [2:0] _mem_incoming_uop_WIRE_0_ctrl_imm_sel = mem_incoming_uop_out_ctrl_imm_sel; // @[util.scala:96:23] wire [4:0] _mem_incoming_uop_WIRE_0_ctrl_op_fcn = mem_incoming_uop_out_ctrl_op_fcn; // @[util.scala:96:23] wire _mem_incoming_uop_WIRE_0_ctrl_fcn_dw = mem_incoming_uop_out_ctrl_fcn_dw; // @[util.scala:96:23] wire [2:0] _mem_incoming_uop_WIRE_0_ctrl_csr_cmd = mem_incoming_uop_out_ctrl_csr_cmd; // @[util.scala:96:23] wire _mem_incoming_uop_WIRE_0_ctrl_is_load = mem_incoming_uop_out_ctrl_is_load; // @[util.scala:96:23] wire _mem_incoming_uop_WIRE_0_ctrl_is_sta = mem_incoming_uop_out_ctrl_is_sta; // @[util.scala:96:23] wire _mem_incoming_uop_WIRE_0_ctrl_is_std = mem_incoming_uop_out_ctrl_is_std; // @[util.scala:96:23] wire [1:0] _mem_incoming_uop_WIRE_0_iw_state = mem_incoming_uop_out_iw_state; // @[util.scala:96:23] wire _mem_incoming_uop_WIRE_0_iw_p1_poisoned = mem_incoming_uop_out_iw_p1_poisoned; // @[util.scala:96:23] wire _mem_incoming_uop_WIRE_0_iw_p2_poisoned = mem_incoming_uop_out_iw_p2_poisoned; // @[util.scala:96:23] wire _mem_incoming_uop_WIRE_0_is_br = mem_incoming_uop_out_is_br; // @[util.scala:96:23] wire _mem_incoming_uop_WIRE_0_is_jalr = mem_incoming_uop_out_is_jalr; // @[util.scala:96:23] wire _mem_incoming_uop_WIRE_0_is_jal = mem_incoming_uop_out_is_jal; // @[util.scala:96:23] wire [7:0] _mem_incoming_uop_out_br_mask_T_1; // @[util.scala:85:25] wire _mem_incoming_uop_WIRE_0_is_sfb = mem_incoming_uop_out_is_sfb; // @[util.scala:96:23] wire [7:0] _mem_incoming_uop_WIRE_0_br_mask = mem_incoming_uop_out_br_mask; // @[util.scala:96:23] wire [2:0] _mem_incoming_uop_WIRE_0_br_tag = mem_incoming_uop_out_br_tag; // @[util.scala:96:23] wire [3:0] _mem_incoming_uop_WIRE_0_ftq_idx = mem_incoming_uop_out_ftq_idx; // @[util.scala:96:23] wire _mem_incoming_uop_WIRE_0_edge_inst = mem_incoming_uop_out_edge_inst; // @[util.scala:96:23] wire [5:0] _mem_incoming_uop_WIRE_0_pc_lob = mem_incoming_uop_out_pc_lob; // @[util.scala:96:23] wire _mem_incoming_uop_WIRE_0_taken = mem_incoming_uop_out_taken; // @[util.scala:96:23] wire [19:0] _mem_incoming_uop_WIRE_0_imm_packed = mem_incoming_uop_out_imm_packed; // @[util.scala:96:23] wire [11:0] _mem_incoming_uop_WIRE_0_csr_addr = mem_incoming_uop_out_csr_addr; // @[util.scala:96:23] wire [4:0] _mem_incoming_uop_WIRE_0_rob_idx = mem_incoming_uop_out_rob_idx; // @[util.scala:96:23] wire [2:0] _mem_incoming_uop_WIRE_0_ldq_idx = mem_incoming_uop_out_ldq_idx; // @[util.scala:96:23] wire [2:0] _mem_incoming_uop_WIRE_0_stq_idx = mem_incoming_uop_out_stq_idx; // @[util.scala:96:23] wire [1:0] _mem_incoming_uop_WIRE_0_rxq_idx = mem_incoming_uop_out_rxq_idx; // @[util.scala:96:23] wire [5:0] _mem_incoming_uop_WIRE_0_pdst = mem_incoming_uop_out_pdst; // @[util.scala:96:23] wire [5:0] _mem_incoming_uop_WIRE_0_prs1 = mem_incoming_uop_out_prs1; // @[util.scala:96:23] wire [5:0] _mem_incoming_uop_WIRE_0_prs2 = mem_incoming_uop_out_prs2; // @[util.scala:96:23] wire [5:0] _mem_incoming_uop_WIRE_0_prs3 = mem_incoming_uop_out_prs3; // @[util.scala:96:23] wire [3:0] _mem_incoming_uop_WIRE_0_ppred = mem_incoming_uop_out_ppred; // @[util.scala:96:23] wire _mem_incoming_uop_WIRE_0_prs1_busy = mem_incoming_uop_out_prs1_busy; // @[util.scala:96:23] wire _mem_incoming_uop_WIRE_0_prs2_busy = mem_incoming_uop_out_prs2_busy; // @[util.scala:96:23] wire _mem_incoming_uop_WIRE_0_prs3_busy = mem_incoming_uop_out_prs3_busy; // @[util.scala:96:23] wire _mem_incoming_uop_WIRE_0_ppred_busy = mem_incoming_uop_out_ppred_busy; // @[util.scala:96:23] wire [5:0] _mem_incoming_uop_WIRE_0_stale_pdst = mem_incoming_uop_out_stale_pdst; // @[util.scala:96:23] wire _mem_incoming_uop_WIRE_0_exception = mem_incoming_uop_out_exception; // @[util.scala:96:23] wire [63:0] _mem_incoming_uop_WIRE_0_exc_cause = mem_incoming_uop_out_exc_cause; // @[util.scala:96:23] wire _mem_incoming_uop_WIRE_0_bypassable = mem_incoming_uop_out_bypassable; // @[util.scala:96:23] wire [4:0] _mem_incoming_uop_WIRE_0_mem_cmd = mem_incoming_uop_out_mem_cmd; // @[util.scala:96:23] wire [1:0] _mem_incoming_uop_WIRE_0_mem_size = mem_incoming_uop_out_mem_size; // @[util.scala:96:23] wire _mem_incoming_uop_WIRE_0_mem_signed = mem_incoming_uop_out_mem_signed; // @[util.scala:96:23] wire _mem_incoming_uop_WIRE_0_is_fence = mem_incoming_uop_out_is_fence; // @[util.scala:96:23] wire _mem_incoming_uop_WIRE_0_is_fencei = mem_incoming_uop_out_is_fencei; // @[util.scala:96:23] wire _mem_incoming_uop_WIRE_0_is_amo = mem_incoming_uop_out_is_amo; // @[util.scala:96:23] wire _mem_incoming_uop_WIRE_0_uses_ldq = mem_incoming_uop_out_uses_ldq; // @[util.scala:96:23] wire _mem_incoming_uop_WIRE_0_uses_stq = mem_incoming_uop_out_uses_stq; // @[util.scala:96:23] wire _mem_incoming_uop_WIRE_0_is_sys_pc2epc = mem_incoming_uop_out_is_sys_pc2epc; // @[util.scala:96:23] wire _mem_incoming_uop_WIRE_0_is_unique = mem_incoming_uop_out_is_unique; // @[util.scala:96:23] wire _mem_incoming_uop_WIRE_0_flush_on_commit = mem_incoming_uop_out_flush_on_commit; // @[util.scala:96:23] wire _mem_incoming_uop_WIRE_0_ldst_is_rs1 = mem_incoming_uop_out_ldst_is_rs1; // @[util.scala:96:23] wire [5:0] _mem_incoming_uop_WIRE_0_ldst = mem_incoming_uop_out_ldst; // @[util.scala:96:23] wire [5:0] _mem_incoming_uop_WIRE_0_lrs1 = mem_incoming_uop_out_lrs1; // @[util.scala:96:23] wire [5:0] _mem_incoming_uop_WIRE_0_lrs2 = mem_incoming_uop_out_lrs2; // @[util.scala:96:23] wire [5:0] _mem_incoming_uop_WIRE_0_lrs3 = mem_incoming_uop_out_lrs3; // @[util.scala:96:23] wire _mem_incoming_uop_WIRE_0_ldst_val = mem_incoming_uop_out_ldst_val; // @[util.scala:96:23] wire [1:0] _mem_incoming_uop_WIRE_0_dst_rtype = mem_incoming_uop_out_dst_rtype; // @[util.scala:96:23] wire [1:0] _mem_incoming_uop_WIRE_0_lrs1_rtype = mem_incoming_uop_out_lrs1_rtype; // @[util.scala:96:23] wire [1:0] _mem_incoming_uop_WIRE_0_lrs2_rtype = mem_incoming_uop_out_lrs2_rtype; // @[util.scala:96:23] wire _mem_incoming_uop_WIRE_0_frs3_en = mem_incoming_uop_out_frs3_en; // @[util.scala:96:23] wire _mem_incoming_uop_WIRE_0_fp_val = mem_incoming_uop_out_fp_val; // @[util.scala:96:23] wire _mem_incoming_uop_WIRE_0_fp_single = mem_incoming_uop_out_fp_single; // @[util.scala:96:23] wire _mem_incoming_uop_WIRE_0_xcpt_pf_if = mem_incoming_uop_out_xcpt_pf_if; // @[util.scala:96:23] wire _mem_incoming_uop_WIRE_0_xcpt_ae_if = mem_incoming_uop_out_xcpt_ae_if; // @[util.scala:96:23] wire _mem_incoming_uop_WIRE_0_xcpt_ma_if = mem_incoming_uop_out_xcpt_ma_if; // @[util.scala:96:23] wire _mem_incoming_uop_WIRE_0_bp_debug_if = mem_incoming_uop_out_bp_debug_if; // @[util.scala:96:23] wire _mem_incoming_uop_WIRE_0_bp_xcpt_if = mem_incoming_uop_out_bp_xcpt_if; // @[util.scala:96:23] wire [1:0] _mem_incoming_uop_WIRE_0_debug_fsrc = mem_incoming_uop_out_debug_fsrc; // @[util.scala:96:23] wire [1:0] _mem_incoming_uop_WIRE_0_debug_tsrc = mem_incoming_uop_out_debug_tsrc; // @[util.scala:96:23] wire [7:0] _mem_incoming_uop_out_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:85:27] assign _mem_incoming_uop_out_br_mask_T_1 = exe_req_0_bits_uop_br_mask & _mem_incoming_uop_out_br_mask_T; // @[util.scala:85:{25,27}] assign mem_incoming_uop_out_br_mask = _mem_incoming_uop_out_br_mask_T_1; // @[util.scala:85:25, :96:23] reg [6:0] mem_incoming_uop_0_uopc; // @[lsu.scala:909:37] reg [31:0] mem_incoming_uop_0_inst; // @[lsu.scala:909:37] reg [31:0] mem_incoming_uop_0_debug_inst; // @[lsu.scala:909:37] reg mem_incoming_uop_0_is_rvc; // @[lsu.scala:909:37] reg [39:0] mem_incoming_uop_0_debug_pc; // @[lsu.scala:909:37] reg [2:0] mem_incoming_uop_0_iq_type; // @[lsu.scala:909:37] reg [9:0] mem_incoming_uop_0_fu_code; // @[lsu.scala:909:37] reg [3:0] mem_incoming_uop_0_ctrl_br_type; // @[lsu.scala:909:37] reg [1:0] mem_incoming_uop_0_ctrl_op1_sel; // @[lsu.scala:909:37] reg [2:0] mem_incoming_uop_0_ctrl_op2_sel; // @[lsu.scala:909:37] reg [2:0] mem_incoming_uop_0_ctrl_imm_sel; // @[lsu.scala:909:37] reg [4:0] mem_incoming_uop_0_ctrl_op_fcn; // @[lsu.scala:909:37] reg mem_incoming_uop_0_ctrl_fcn_dw; // @[lsu.scala:909:37] reg [2:0] mem_incoming_uop_0_ctrl_csr_cmd; // @[lsu.scala:909:37] reg mem_incoming_uop_0_ctrl_is_load; // @[lsu.scala:909:37] reg mem_incoming_uop_0_ctrl_is_sta; // @[lsu.scala:909:37] reg mem_incoming_uop_0_ctrl_is_std; // @[lsu.scala:909:37] reg [1:0] mem_incoming_uop_0_iw_state; // @[lsu.scala:909:37] reg mem_incoming_uop_0_iw_p1_poisoned; // @[lsu.scala:909:37] reg mem_incoming_uop_0_iw_p2_poisoned; // @[lsu.scala:909:37] reg mem_incoming_uop_0_is_br; // @[lsu.scala:909:37] reg mem_incoming_uop_0_is_jalr; // @[lsu.scala:909:37] reg mem_incoming_uop_0_is_jal; // @[lsu.scala:909:37] reg mem_incoming_uop_0_is_sfb; // @[lsu.scala:909:37] reg [7:0] mem_incoming_uop_0_br_mask; // @[lsu.scala:909:37] reg [2:0] mem_incoming_uop_0_br_tag; // @[lsu.scala:909:37] reg [3:0] mem_incoming_uop_0_ftq_idx; // @[lsu.scala:909:37] reg mem_incoming_uop_0_edge_inst; // @[lsu.scala:909:37] reg [5:0] mem_incoming_uop_0_pc_lob; // @[lsu.scala:909:37] reg mem_incoming_uop_0_taken; // @[lsu.scala:909:37] reg [19:0] mem_incoming_uop_0_imm_packed; // @[lsu.scala:909:37] reg [11:0] mem_incoming_uop_0_csr_addr; // @[lsu.scala:909:37] reg [4:0] mem_incoming_uop_0_rob_idx; // @[lsu.scala:909:37] reg [2:0] mem_incoming_uop_0_ldq_idx; // @[lsu.scala:909:37] reg [2:0] mem_incoming_uop_0_stq_idx; // @[lsu.scala:909:37] reg [1:0] mem_incoming_uop_0_rxq_idx; // @[lsu.scala:909:37] reg [5:0] mem_incoming_uop_0_pdst; // @[lsu.scala:909:37] assign io_core_spec_ld_wakeup_0_bits_0 = mem_incoming_uop_0_pdst; // @[lsu.scala:201:7, :909:37] reg [5:0] mem_incoming_uop_0_prs1; // @[lsu.scala:909:37] reg [5:0] mem_incoming_uop_0_prs2; // @[lsu.scala:909:37] reg [5:0] mem_incoming_uop_0_prs3; // @[lsu.scala:909:37] reg [3:0] mem_incoming_uop_0_ppred; // @[lsu.scala:909:37] reg mem_incoming_uop_0_prs1_busy; // @[lsu.scala:909:37] reg mem_incoming_uop_0_prs2_busy; // @[lsu.scala:909:37] reg mem_incoming_uop_0_prs3_busy; // @[lsu.scala:909:37] reg mem_incoming_uop_0_ppred_busy; // @[lsu.scala:909:37] reg [5:0] mem_incoming_uop_0_stale_pdst; // @[lsu.scala:909:37] reg mem_incoming_uop_0_exception; // @[lsu.scala:909:37] reg [63:0] mem_incoming_uop_0_exc_cause; // @[lsu.scala:909:37] reg mem_incoming_uop_0_bypassable; // @[lsu.scala:909:37] reg [4:0] mem_incoming_uop_0_mem_cmd; // @[lsu.scala:909:37] reg [1:0] mem_incoming_uop_0_mem_size; // @[lsu.scala:909:37] reg mem_incoming_uop_0_mem_signed; // @[lsu.scala:909:37] reg mem_incoming_uop_0_is_fence; // @[lsu.scala:909:37] reg mem_incoming_uop_0_is_fencei; // @[lsu.scala:909:37] reg mem_incoming_uop_0_is_amo; // @[lsu.scala:909:37] reg mem_incoming_uop_0_uses_ldq; // @[lsu.scala:909:37] reg mem_incoming_uop_0_uses_stq; // @[lsu.scala:909:37] reg mem_incoming_uop_0_is_sys_pc2epc; // @[lsu.scala:909:37] reg mem_incoming_uop_0_is_unique; // @[lsu.scala:909:37] reg mem_incoming_uop_0_flush_on_commit; // @[lsu.scala:909:37] reg mem_incoming_uop_0_ldst_is_rs1; // @[lsu.scala:909:37] reg [5:0] mem_incoming_uop_0_ldst; // @[lsu.scala:909:37] reg [5:0] mem_incoming_uop_0_lrs1; // @[lsu.scala:909:37] reg [5:0] mem_incoming_uop_0_lrs2; // @[lsu.scala:909:37] reg [5:0] mem_incoming_uop_0_lrs3; // @[lsu.scala:909:37] reg mem_incoming_uop_0_ldst_val; // @[lsu.scala:909:37] reg [1:0] mem_incoming_uop_0_dst_rtype; // @[lsu.scala:909:37] reg [1:0] mem_incoming_uop_0_lrs1_rtype; // @[lsu.scala:909:37] reg [1:0] mem_incoming_uop_0_lrs2_rtype; // @[lsu.scala:909:37] reg mem_incoming_uop_0_frs3_en; // @[lsu.scala:909:37] reg mem_incoming_uop_0_fp_val; // @[lsu.scala:909:37] reg mem_incoming_uop_0_fp_single; // @[lsu.scala:909:37] reg mem_incoming_uop_0_xcpt_pf_if; // @[lsu.scala:909:37] reg mem_incoming_uop_0_xcpt_ae_if; // @[lsu.scala:909:37] reg mem_incoming_uop_0_xcpt_ma_if; // @[lsu.scala:909:37] reg mem_incoming_uop_0_bp_debug_if; // @[lsu.scala:909:37] reg mem_incoming_uop_0_bp_xcpt_if; // @[lsu.scala:909:37] reg [1:0] mem_incoming_uop_0_debug_fsrc; // @[lsu.scala:909:37] reg [1:0] mem_incoming_uop_0_debug_tsrc; // @[lsu.scala:909:37] wire _mem_ldq_incoming_e_out_valid_T_3; // @[util.scala:108:31] wire _mem_ldq_incoming_e_WIRE_0_valid = mem_ldq_incoming_e_out_valid; // @[util.scala:106:23] wire [6:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_uopc = mem_ldq_incoming_e_out_bits_uop_uopc; // @[util.scala:106:23] wire [31:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_inst = mem_ldq_incoming_e_out_bits_uop_inst; // @[util.scala:106:23] wire [31:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_debug_inst = mem_ldq_incoming_e_out_bits_uop_debug_inst; // @[util.scala:106:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_is_rvc = mem_ldq_incoming_e_out_bits_uop_is_rvc; // @[util.scala:106:23] wire [39:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_debug_pc = mem_ldq_incoming_e_out_bits_uop_debug_pc; // @[util.scala:106:23] wire [2:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_iq_type = mem_ldq_incoming_e_out_bits_uop_iq_type; // @[util.scala:106:23] wire [9:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_fu_code = mem_ldq_incoming_e_out_bits_uop_fu_code; // @[util.scala:106:23] wire [3:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_ctrl_br_type = mem_ldq_incoming_e_out_bits_uop_ctrl_br_type; // @[util.scala:106:23] wire [1:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_ctrl_op1_sel = mem_ldq_incoming_e_out_bits_uop_ctrl_op1_sel; // @[util.scala:106:23] wire [2:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_ctrl_op2_sel = mem_ldq_incoming_e_out_bits_uop_ctrl_op2_sel; // @[util.scala:106:23] wire [2:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_ctrl_imm_sel = mem_ldq_incoming_e_out_bits_uop_ctrl_imm_sel; // @[util.scala:106:23] wire [4:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_ctrl_op_fcn = mem_ldq_incoming_e_out_bits_uop_ctrl_op_fcn; // @[util.scala:106:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_ctrl_fcn_dw = mem_ldq_incoming_e_out_bits_uop_ctrl_fcn_dw; // @[util.scala:106:23] wire [2:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_ctrl_csr_cmd = mem_ldq_incoming_e_out_bits_uop_ctrl_csr_cmd; // @[util.scala:106:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_ctrl_is_load = mem_ldq_incoming_e_out_bits_uop_ctrl_is_load; // @[util.scala:106:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_ctrl_is_sta = mem_ldq_incoming_e_out_bits_uop_ctrl_is_sta; // @[util.scala:106:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_ctrl_is_std = mem_ldq_incoming_e_out_bits_uop_ctrl_is_std; // @[util.scala:106:23] wire [1:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_iw_state = mem_ldq_incoming_e_out_bits_uop_iw_state; // @[util.scala:106:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_iw_p1_poisoned = mem_ldq_incoming_e_out_bits_uop_iw_p1_poisoned; // @[util.scala:106:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_iw_p2_poisoned = mem_ldq_incoming_e_out_bits_uop_iw_p2_poisoned; // @[util.scala:106:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_is_br = mem_ldq_incoming_e_out_bits_uop_is_br; // @[util.scala:106:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_is_jalr = mem_ldq_incoming_e_out_bits_uop_is_jalr; // @[util.scala:106:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_is_jal = mem_ldq_incoming_e_out_bits_uop_is_jal; // @[util.scala:106:23] wire [7:0] _mem_ldq_incoming_e_out_bits_uop_br_mask_T_1; // @[util.scala:89:21] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_is_sfb = mem_ldq_incoming_e_out_bits_uop_is_sfb; // @[util.scala:106:23] wire [7:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_br_mask = mem_ldq_incoming_e_out_bits_uop_br_mask; // @[util.scala:106:23] wire [2:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_br_tag = mem_ldq_incoming_e_out_bits_uop_br_tag; // @[util.scala:106:23] wire [3:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_ftq_idx = mem_ldq_incoming_e_out_bits_uop_ftq_idx; // @[util.scala:106:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_edge_inst = mem_ldq_incoming_e_out_bits_uop_edge_inst; // @[util.scala:106:23] wire [5:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_pc_lob = mem_ldq_incoming_e_out_bits_uop_pc_lob; // @[util.scala:106:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_taken = mem_ldq_incoming_e_out_bits_uop_taken; // @[util.scala:106:23] wire [19:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_imm_packed = mem_ldq_incoming_e_out_bits_uop_imm_packed; // @[util.scala:106:23] wire [11:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_csr_addr = mem_ldq_incoming_e_out_bits_uop_csr_addr; // @[util.scala:106:23] wire [4:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_rob_idx = mem_ldq_incoming_e_out_bits_uop_rob_idx; // @[util.scala:106:23] wire [2:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_ldq_idx = mem_ldq_incoming_e_out_bits_uop_ldq_idx; // @[util.scala:106:23] wire [2:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_stq_idx = mem_ldq_incoming_e_out_bits_uop_stq_idx; // @[util.scala:106:23] wire [1:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_rxq_idx = mem_ldq_incoming_e_out_bits_uop_rxq_idx; // @[util.scala:106:23] wire [5:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_pdst = mem_ldq_incoming_e_out_bits_uop_pdst; // @[util.scala:106:23] wire [5:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_prs1 = mem_ldq_incoming_e_out_bits_uop_prs1; // @[util.scala:106:23] wire [5:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_prs2 = mem_ldq_incoming_e_out_bits_uop_prs2; // @[util.scala:106:23] wire [5:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_prs3 = mem_ldq_incoming_e_out_bits_uop_prs3; // @[util.scala:106:23] wire [3:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_ppred = mem_ldq_incoming_e_out_bits_uop_ppred; // @[util.scala:106:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_prs1_busy = mem_ldq_incoming_e_out_bits_uop_prs1_busy; // @[util.scala:106:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_prs2_busy = mem_ldq_incoming_e_out_bits_uop_prs2_busy; // @[util.scala:106:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_prs3_busy = mem_ldq_incoming_e_out_bits_uop_prs3_busy; // @[util.scala:106:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_ppred_busy = mem_ldq_incoming_e_out_bits_uop_ppred_busy; // @[util.scala:106:23] wire [5:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_stale_pdst = mem_ldq_incoming_e_out_bits_uop_stale_pdst; // @[util.scala:106:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_exception = mem_ldq_incoming_e_out_bits_uop_exception; // @[util.scala:106:23] wire [63:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_exc_cause = mem_ldq_incoming_e_out_bits_uop_exc_cause; // @[util.scala:106:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_bypassable = mem_ldq_incoming_e_out_bits_uop_bypassable; // @[util.scala:106:23] wire [4:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_mem_cmd = mem_ldq_incoming_e_out_bits_uop_mem_cmd; // @[util.scala:106:23] wire [1:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_mem_size = mem_ldq_incoming_e_out_bits_uop_mem_size; // @[util.scala:106:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_mem_signed = mem_ldq_incoming_e_out_bits_uop_mem_signed; // @[util.scala:106:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_is_fence = mem_ldq_incoming_e_out_bits_uop_is_fence; // @[util.scala:106:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_is_fencei = mem_ldq_incoming_e_out_bits_uop_is_fencei; // @[util.scala:106:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_is_amo = mem_ldq_incoming_e_out_bits_uop_is_amo; // @[util.scala:106:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_uses_ldq = mem_ldq_incoming_e_out_bits_uop_uses_ldq; // @[util.scala:106:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_uses_stq = mem_ldq_incoming_e_out_bits_uop_uses_stq; // @[util.scala:106:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_is_sys_pc2epc = mem_ldq_incoming_e_out_bits_uop_is_sys_pc2epc; // @[util.scala:106:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_is_unique = mem_ldq_incoming_e_out_bits_uop_is_unique; // @[util.scala:106:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_flush_on_commit = mem_ldq_incoming_e_out_bits_uop_flush_on_commit; // @[util.scala:106:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_ldst_is_rs1 = mem_ldq_incoming_e_out_bits_uop_ldst_is_rs1; // @[util.scala:106:23] wire [5:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_ldst = mem_ldq_incoming_e_out_bits_uop_ldst; // @[util.scala:106:23] wire [5:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_lrs1 = mem_ldq_incoming_e_out_bits_uop_lrs1; // @[util.scala:106:23] wire [5:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_lrs2 = mem_ldq_incoming_e_out_bits_uop_lrs2; // @[util.scala:106:23] wire [5:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_lrs3 = mem_ldq_incoming_e_out_bits_uop_lrs3; // @[util.scala:106:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_ldst_val = mem_ldq_incoming_e_out_bits_uop_ldst_val; // @[util.scala:106:23] wire [1:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_dst_rtype = mem_ldq_incoming_e_out_bits_uop_dst_rtype; // @[util.scala:106:23] wire [1:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_lrs1_rtype = mem_ldq_incoming_e_out_bits_uop_lrs1_rtype; // @[util.scala:106:23] wire [1:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_lrs2_rtype = mem_ldq_incoming_e_out_bits_uop_lrs2_rtype; // @[util.scala:106:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_frs3_en = mem_ldq_incoming_e_out_bits_uop_frs3_en; // @[util.scala:106:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_fp_val = mem_ldq_incoming_e_out_bits_uop_fp_val; // @[util.scala:106:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_fp_single = mem_ldq_incoming_e_out_bits_uop_fp_single; // @[util.scala:106:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_xcpt_pf_if = mem_ldq_incoming_e_out_bits_uop_xcpt_pf_if; // @[util.scala:106:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_xcpt_ae_if = mem_ldq_incoming_e_out_bits_uop_xcpt_ae_if; // @[util.scala:106:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_xcpt_ma_if = mem_ldq_incoming_e_out_bits_uop_xcpt_ma_if; // @[util.scala:106:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_bp_debug_if = mem_ldq_incoming_e_out_bits_uop_bp_debug_if; // @[util.scala:106:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_bp_xcpt_if = mem_ldq_incoming_e_out_bits_uop_bp_xcpt_if; // @[util.scala:106:23] wire [1:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_debug_fsrc = mem_ldq_incoming_e_out_bits_uop_debug_fsrc; // @[util.scala:106:23] wire [1:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_debug_tsrc = mem_ldq_incoming_e_out_bits_uop_debug_tsrc; // @[util.scala:106:23] wire _mem_ldq_incoming_e_WIRE_0_bits_addr_valid = mem_ldq_incoming_e_out_bits_addr_valid; // @[util.scala:106:23] wire [39:0] _mem_ldq_incoming_e_WIRE_0_bits_addr_bits = mem_ldq_incoming_e_out_bits_addr_bits; // @[util.scala:106:23] wire _mem_ldq_incoming_e_WIRE_0_bits_addr_is_virtual = mem_ldq_incoming_e_out_bits_addr_is_virtual; // @[util.scala:106:23] wire _mem_ldq_incoming_e_WIRE_0_bits_addr_is_uncacheable = mem_ldq_incoming_e_out_bits_addr_is_uncacheable; // @[util.scala:106:23] wire _mem_ldq_incoming_e_WIRE_0_bits_executed = mem_ldq_incoming_e_out_bits_executed; // @[util.scala:106:23] wire _mem_ldq_incoming_e_WIRE_0_bits_succeeded = mem_ldq_incoming_e_out_bits_succeeded; // @[util.scala:106:23] wire _mem_ldq_incoming_e_WIRE_0_bits_order_fail = mem_ldq_incoming_e_out_bits_order_fail; // @[util.scala:106:23] wire _mem_ldq_incoming_e_WIRE_0_bits_observed = mem_ldq_incoming_e_out_bits_observed; // @[util.scala:106:23] wire [7:0] _mem_ldq_incoming_e_WIRE_0_bits_st_dep_mask = mem_ldq_incoming_e_out_bits_st_dep_mask; // @[util.scala:106:23] wire [2:0] _mem_ldq_incoming_e_WIRE_0_bits_youngest_stq_idx = mem_ldq_incoming_e_out_bits_youngest_stq_idx; // @[util.scala:106:23] wire _mem_ldq_incoming_e_WIRE_0_bits_forward_std_val = mem_ldq_incoming_e_out_bits_forward_std_val; // @[util.scala:106:23] wire [2:0] _mem_ldq_incoming_e_WIRE_0_bits_forward_stq_idx = mem_ldq_incoming_e_out_bits_forward_stq_idx; // @[util.scala:106:23] wire [63:0] _mem_ldq_incoming_e_WIRE_0_bits_debug_wb_data = mem_ldq_incoming_e_out_bits_debug_wb_data; // @[util.scala:106:23] wire [7:0] _mem_ldq_incoming_e_out_bits_uop_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:85:27, :89:23] assign _mem_ldq_incoming_e_out_bits_uop_br_mask_T_1 = ldq_incoming_e_0_bits_uop_br_mask & _mem_ldq_incoming_e_out_bits_uop_br_mask_T; // @[util.scala:89:{21,23}] assign mem_ldq_incoming_e_out_bits_uop_br_mask = _mem_ldq_incoming_e_out_bits_uop_br_mask_T_1; // @[util.scala:89:21, :106:23] wire [7:0] _mem_ldq_incoming_e_out_valid_T = io_core_brupdate_b1_mispredict_mask_0 & ldq_incoming_e_0_bits_uop_br_mask; // @[util.scala:118:51] wire _mem_ldq_incoming_e_out_valid_T_1 = |_mem_ldq_incoming_e_out_valid_T; // @[util.scala:118:{51,59}] wire _mem_ldq_incoming_e_out_valid_T_2 = ~_mem_ldq_incoming_e_out_valid_T_1; // @[util.scala:108:34, :118:59] assign _mem_ldq_incoming_e_out_valid_T_3 = ldq_incoming_e_0_valid & _mem_ldq_incoming_e_out_valid_T_2; // @[util.scala:108:{31,34}] assign mem_ldq_incoming_e_out_valid = _mem_ldq_incoming_e_out_valid_T_3; // @[util.scala:106:23, :108:31] reg mem_ldq_incoming_e_0_valid; // @[lsu.scala:910:37] reg [6:0] mem_ldq_incoming_e_0_bits_uop_uopc; // @[lsu.scala:910:37] reg [31:0] mem_ldq_incoming_e_0_bits_uop_inst; // @[lsu.scala:910:37] reg [31:0] mem_ldq_incoming_e_0_bits_uop_debug_inst; // @[lsu.scala:910:37] reg mem_ldq_incoming_e_0_bits_uop_is_rvc; // @[lsu.scala:910:37] reg [39:0] mem_ldq_incoming_e_0_bits_uop_debug_pc; // @[lsu.scala:910:37] reg [2:0] mem_ldq_incoming_e_0_bits_uop_iq_type; // @[lsu.scala:910:37] reg [9:0] mem_ldq_incoming_e_0_bits_uop_fu_code; // @[lsu.scala:910:37] reg [3:0] mem_ldq_incoming_e_0_bits_uop_ctrl_br_type; // @[lsu.scala:910:37] reg [1:0] mem_ldq_incoming_e_0_bits_uop_ctrl_op1_sel; // @[lsu.scala:910:37] reg [2:0] mem_ldq_incoming_e_0_bits_uop_ctrl_op2_sel; // @[lsu.scala:910:37] reg [2:0] mem_ldq_incoming_e_0_bits_uop_ctrl_imm_sel; // @[lsu.scala:910:37] reg [4:0] mem_ldq_incoming_e_0_bits_uop_ctrl_op_fcn; // @[lsu.scala:910:37] reg mem_ldq_incoming_e_0_bits_uop_ctrl_fcn_dw; // @[lsu.scala:910:37] reg [2:0] mem_ldq_incoming_e_0_bits_uop_ctrl_csr_cmd; // @[lsu.scala:910:37] reg mem_ldq_incoming_e_0_bits_uop_ctrl_is_load; // @[lsu.scala:910:37] reg mem_ldq_incoming_e_0_bits_uop_ctrl_is_sta; // @[lsu.scala:910:37] reg mem_ldq_incoming_e_0_bits_uop_ctrl_is_std; // @[lsu.scala:910:37] reg [1:0] mem_ldq_incoming_e_0_bits_uop_iw_state; // @[lsu.scala:910:37] reg mem_ldq_incoming_e_0_bits_uop_iw_p1_poisoned; // @[lsu.scala:910:37] reg mem_ldq_incoming_e_0_bits_uop_iw_p2_poisoned; // @[lsu.scala:910:37] reg mem_ldq_incoming_e_0_bits_uop_is_br; // @[lsu.scala:910:37] reg mem_ldq_incoming_e_0_bits_uop_is_jalr; // @[lsu.scala:910:37] reg mem_ldq_incoming_e_0_bits_uop_is_jal; // @[lsu.scala:910:37] reg mem_ldq_incoming_e_0_bits_uop_is_sfb; // @[lsu.scala:910:37] reg [7:0] mem_ldq_incoming_e_0_bits_uop_br_mask; // @[lsu.scala:910:37] reg [2:0] mem_ldq_incoming_e_0_bits_uop_br_tag; // @[lsu.scala:910:37] reg [3:0] mem_ldq_incoming_e_0_bits_uop_ftq_idx; // @[lsu.scala:910:37] reg mem_ldq_incoming_e_0_bits_uop_edge_inst; // @[lsu.scala:910:37] reg [5:0] mem_ldq_incoming_e_0_bits_uop_pc_lob; // @[lsu.scala:910:37] reg mem_ldq_incoming_e_0_bits_uop_taken; // @[lsu.scala:910:37] reg [19:0] mem_ldq_incoming_e_0_bits_uop_imm_packed; // @[lsu.scala:910:37] reg [11:0] mem_ldq_incoming_e_0_bits_uop_csr_addr; // @[lsu.scala:910:37] reg [4:0] mem_ldq_incoming_e_0_bits_uop_rob_idx; // @[lsu.scala:910:37] reg [2:0] mem_ldq_incoming_e_0_bits_uop_ldq_idx; // @[lsu.scala:910:37] reg [2:0] mem_ldq_incoming_e_0_bits_uop_stq_idx; // @[lsu.scala:910:37] reg [1:0] mem_ldq_incoming_e_0_bits_uop_rxq_idx; // @[lsu.scala:910:37] reg [5:0] mem_ldq_incoming_e_0_bits_uop_pdst; // @[lsu.scala:910:37] reg [5:0] mem_ldq_incoming_e_0_bits_uop_prs1; // @[lsu.scala:910:37] reg [5:0] mem_ldq_incoming_e_0_bits_uop_prs2; // @[lsu.scala:910:37] reg [5:0] mem_ldq_incoming_e_0_bits_uop_prs3; // @[lsu.scala:910:37] reg [3:0] mem_ldq_incoming_e_0_bits_uop_ppred; // @[lsu.scala:910:37] reg mem_ldq_incoming_e_0_bits_uop_prs1_busy; // @[lsu.scala:910:37] reg mem_ldq_incoming_e_0_bits_uop_prs2_busy; // @[lsu.scala:910:37] reg mem_ldq_incoming_e_0_bits_uop_prs3_busy; // @[lsu.scala:910:37] reg mem_ldq_incoming_e_0_bits_uop_ppred_busy; // @[lsu.scala:910:37] reg [5:0] mem_ldq_incoming_e_0_bits_uop_stale_pdst; // @[lsu.scala:910:37] reg mem_ldq_incoming_e_0_bits_uop_exception; // @[lsu.scala:910:37] reg [63:0] mem_ldq_incoming_e_0_bits_uop_exc_cause; // @[lsu.scala:910:37] reg mem_ldq_incoming_e_0_bits_uop_bypassable; // @[lsu.scala:910:37] reg [4:0] mem_ldq_incoming_e_0_bits_uop_mem_cmd; // @[lsu.scala:910:37] reg [1:0] mem_ldq_incoming_e_0_bits_uop_mem_size; // @[lsu.scala:910:37] reg mem_ldq_incoming_e_0_bits_uop_mem_signed; // @[lsu.scala:910:37] reg mem_ldq_incoming_e_0_bits_uop_is_fence; // @[lsu.scala:910:37] reg mem_ldq_incoming_e_0_bits_uop_is_fencei; // @[lsu.scala:910:37] reg mem_ldq_incoming_e_0_bits_uop_is_amo; // @[lsu.scala:910:37] reg mem_ldq_incoming_e_0_bits_uop_uses_ldq; // @[lsu.scala:910:37] reg mem_ldq_incoming_e_0_bits_uop_uses_stq; // @[lsu.scala:910:37] reg mem_ldq_incoming_e_0_bits_uop_is_sys_pc2epc; // @[lsu.scala:910:37] reg mem_ldq_incoming_e_0_bits_uop_is_unique; // @[lsu.scala:910:37] reg mem_ldq_incoming_e_0_bits_uop_flush_on_commit; // @[lsu.scala:910:37] reg mem_ldq_incoming_e_0_bits_uop_ldst_is_rs1; // @[lsu.scala:910:37] reg [5:0] mem_ldq_incoming_e_0_bits_uop_ldst; // @[lsu.scala:910:37] reg [5:0] mem_ldq_incoming_e_0_bits_uop_lrs1; // @[lsu.scala:910:37] reg [5:0] mem_ldq_incoming_e_0_bits_uop_lrs2; // @[lsu.scala:910:37] reg [5:0] mem_ldq_incoming_e_0_bits_uop_lrs3; // @[lsu.scala:910:37] reg mem_ldq_incoming_e_0_bits_uop_ldst_val; // @[lsu.scala:910:37] reg [1:0] mem_ldq_incoming_e_0_bits_uop_dst_rtype; // @[lsu.scala:910:37] reg [1:0] mem_ldq_incoming_e_0_bits_uop_lrs1_rtype; // @[lsu.scala:910:37] reg [1:0] mem_ldq_incoming_e_0_bits_uop_lrs2_rtype; // @[lsu.scala:910:37] reg mem_ldq_incoming_e_0_bits_uop_frs3_en; // @[lsu.scala:910:37] reg mem_ldq_incoming_e_0_bits_uop_fp_val; // @[lsu.scala:910:37] reg mem_ldq_incoming_e_0_bits_uop_fp_single; // @[lsu.scala:910:37] reg mem_ldq_incoming_e_0_bits_uop_xcpt_pf_if; // @[lsu.scala:910:37] reg mem_ldq_incoming_e_0_bits_uop_xcpt_ae_if; // @[lsu.scala:910:37] reg mem_ldq_incoming_e_0_bits_uop_xcpt_ma_if; // @[lsu.scala:910:37] reg mem_ldq_incoming_e_0_bits_uop_bp_debug_if; // @[lsu.scala:910:37] reg mem_ldq_incoming_e_0_bits_uop_bp_xcpt_if; // @[lsu.scala:910:37] reg [1:0] mem_ldq_incoming_e_0_bits_uop_debug_fsrc; // @[lsu.scala:910:37] reg [1:0] mem_ldq_incoming_e_0_bits_uop_debug_tsrc; // @[lsu.scala:910:37] reg mem_ldq_incoming_e_0_bits_addr_valid; // @[lsu.scala:910:37] reg [39:0] mem_ldq_incoming_e_0_bits_addr_bits; // @[lsu.scala:910:37] reg mem_ldq_incoming_e_0_bits_addr_is_virtual; // @[lsu.scala:910:37] reg mem_ldq_incoming_e_0_bits_addr_is_uncacheable; // @[lsu.scala:910:37] reg mem_ldq_incoming_e_0_bits_executed; // @[lsu.scala:910:37] reg mem_ldq_incoming_e_0_bits_succeeded; // @[lsu.scala:910:37] reg mem_ldq_incoming_e_0_bits_order_fail; // @[lsu.scala:910:37] reg mem_ldq_incoming_e_0_bits_observed; // @[lsu.scala:910:37] reg [7:0] mem_ldq_incoming_e_0_bits_st_dep_mask; // @[lsu.scala:910:37] reg [2:0] mem_ldq_incoming_e_0_bits_youngest_stq_idx; // @[lsu.scala:910:37] reg mem_ldq_incoming_e_0_bits_forward_std_val; // @[lsu.scala:910:37] reg [2:0] mem_ldq_incoming_e_0_bits_forward_stq_idx; // @[lsu.scala:910:37] reg [63:0] mem_ldq_incoming_e_0_bits_debug_wb_data; // @[lsu.scala:910:37] wire _mem_stq_incoming_e_out_valid_T_3; // @[util.scala:108:31] wire _mem_stq_incoming_e_WIRE_0_valid = mem_stq_incoming_e_out_valid; // @[util.scala:106:23] wire [6:0] _mem_stq_incoming_e_WIRE_0_bits_uop_uopc = mem_stq_incoming_e_out_bits_uop_uopc; // @[util.scala:106:23] wire [31:0] _mem_stq_incoming_e_WIRE_0_bits_uop_inst = mem_stq_incoming_e_out_bits_uop_inst; // @[util.scala:106:23] wire [31:0] _mem_stq_incoming_e_WIRE_0_bits_uop_debug_inst = mem_stq_incoming_e_out_bits_uop_debug_inst; // @[util.scala:106:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_is_rvc = mem_stq_incoming_e_out_bits_uop_is_rvc; // @[util.scala:106:23] wire [39:0] _mem_stq_incoming_e_WIRE_0_bits_uop_debug_pc = mem_stq_incoming_e_out_bits_uop_debug_pc; // @[util.scala:106:23] wire [2:0] _mem_stq_incoming_e_WIRE_0_bits_uop_iq_type = mem_stq_incoming_e_out_bits_uop_iq_type; // @[util.scala:106:23] wire [9:0] _mem_stq_incoming_e_WIRE_0_bits_uop_fu_code = mem_stq_incoming_e_out_bits_uop_fu_code; // @[util.scala:106:23] wire [3:0] _mem_stq_incoming_e_WIRE_0_bits_uop_ctrl_br_type = mem_stq_incoming_e_out_bits_uop_ctrl_br_type; // @[util.scala:106:23] wire [1:0] _mem_stq_incoming_e_WIRE_0_bits_uop_ctrl_op1_sel = mem_stq_incoming_e_out_bits_uop_ctrl_op1_sel; // @[util.scala:106:23] wire [2:0] _mem_stq_incoming_e_WIRE_0_bits_uop_ctrl_op2_sel = mem_stq_incoming_e_out_bits_uop_ctrl_op2_sel; // @[util.scala:106:23] wire [2:0] _mem_stq_incoming_e_WIRE_0_bits_uop_ctrl_imm_sel = mem_stq_incoming_e_out_bits_uop_ctrl_imm_sel; // @[util.scala:106:23] wire [4:0] _mem_stq_incoming_e_WIRE_0_bits_uop_ctrl_op_fcn = mem_stq_incoming_e_out_bits_uop_ctrl_op_fcn; // @[util.scala:106:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_ctrl_fcn_dw = mem_stq_incoming_e_out_bits_uop_ctrl_fcn_dw; // @[util.scala:106:23] wire [2:0] _mem_stq_incoming_e_WIRE_0_bits_uop_ctrl_csr_cmd = mem_stq_incoming_e_out_bits_uop_ctrl_csr_cmd; // @[util.scala:106:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_ctrl_is_load = mem_stq_incoming_e_out_bits_uop_ctrl_is_load; // @[util.scala:106:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_ctrl_is_sta = mem_stq_incoming_e_out_bits_uop_ctrl_is_sta; // @[util.scala:106:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_ctrl_is_std = mem_stq_incoming_e_out_bits_uop_ctrl_is_std; // @[util.scala:106:23] wire [1:0] _mem_stq_incoming_e_WIRE_0_bits_uop_iw_state = mem_stq_incoming_e_out_bits_uop_iw_state; // @[util.scala:106:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_iw_p1_poisoned = mem_stq_incoming_e_out_bits_uop_iw_p1_poisoned; // @[util.scala:106:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_iw_p2_poisoned = mem_stq_incoming_e_out_bits_uop_iw_p2_poisoned; // @[util.scala:106:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_is_br = mem_stq_incoming_e_out_bits_uop_is_br; // @[util.scala:106:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_is_jalr = mem_stq_incoming_e_out_bits_uop_is_jalr; // @[util.scala:106:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_is_jal = mem_stq_incoming_e_out_bits_uop_is_jal; // @[util.scala:106:23] wire [7:0] _mem_stq_incoming_e_out_bits_uop_br_mask_T_1; // @[util.scala:89:21] wire _mem_stq_incoming_e_WIRE_0_bits_uop_is_sfb = mem_stq_incoming_e_out_bits_uop_is_sfb; // @[util.scala:106:23] wire [7:0] _mem_stq_incoming_e_WIRE_0_bits_uop_br_mask = mem_stq_incoming_e_out_bits_uop_br_mask; // @[util.scala:106:23] wire [2:0] _mem_stq_incoming_e_WIRE_0_bits_uop_br_tag = mem_stq_incoming_e_out_bits_uop_br_tag; // @[util.scala:106:23] wire [3:0] _mem_stq_incoming_e_WIRE_0_bits_uop_ftq_idx = mem_stq_incoming_e_out_bits_uop_ftq_idx; // @[util.scala:106:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_edge_inst = mem_stq_incoming_e_out_bits_uop_edge_inst; // @[util.scala:106:23] wire [5:0] _mem_stq_incoming_e_WIRE_0_bits_uop_pc_lob = mem_stq_incoming_e_out_bits_uop_pc_lob; // @[util.scala:106:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_taken = mem_stq_incoming_e_out_bits_uop_taken; // @[util.scala:106:23] wire [19:0] _mem_stq_incoming_e_WIRE_0_bits_uop_imm_packed = mem_stq_incoming_e_out_bits_uop_imm_packed; // @[util.scala:106:23] wire [11:0] _mem_stq_incoming_e_WIRE_0_bits_uop_csr_addr = mem_stq_incoming_e_out_bits_uop_csr_addr; // @[util.scala:106:23] wire [4:0] _mem_stq_incoming_e_WIRE_0_bits_uop_rob_idx = mem_stq_incoming_e_out_bits_uop_rob_idx; // @[util.scala:106:23] wire [2:0] _mem_stq_incoming_e_WIRE_0_bits_uop_ldq_idx = mem_stq_incoming_e_out_bits_uop_ldq_idx; // @[util.scala:106:23] wire [2:0] _mem_stq_incoming_e_WIRE_0_bits_uop_stq_idx = mem_stq_incoming_e_out_bits_uop_stq_idx; // @[util.scala:106:23] wire [1:0] _mem_stq_incoming_e_WIRE_0_bits_uop_rxq_idx = mem_stq_incoming_e_out_bits_uop_rxq_idx; // @[util.scala:106:23] wire [5:0] _mem_stq_incoming_e_WIRE_0_bits_uop_pdst = mem_stq_incoming_e_out_bits_uop_pdst; // @[util.scala:106:23] wire [5:0] _mem_stq_incoming_e_WIRE_0_bits_uop_prs1 = mem_stq_incoming_e_out_bits_uop_prs1; // @[util.scala:106:23] wire [5:0] _mem_stq_incoming_e_WIRE_0_bits_uop_prs2 = mem_stq_incoming_e_out_bits_uop_prs2; // @[util.scala:106:23] wire [5:0] _mem_stq_incoming_e_WIRE_0_bits_uop_prs3 = mem_stq_incoming_e_out_bits_uop_prs3; // @[util.scala:106:23] wire [3:0] _mem_stq_incoming_e_WIRE_0_bits_uop_ppred = mem_stq_incoming_e_out_bits_uop_ppred; // @[util.scala:106:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_prs1_busy = mem_stq_incoming_e_out_bits_uop_prs1_busy; // @[util.scala:106:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_prs2_busy = mem_stq_incoming_e_out_bits_uop_prs2_busy; // @[util.scala:106:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_prs3_busy = mem_stq_incoming_e_out_bits_uop_prs3_busy; // @[util.scala:106:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_ppred_busy = mem_stq_incoming_e_out_bits_uop_ppred_busy; // @[util.scala:106:23] wire [5:0] _mem_stq_incoming_e_WIRE_0_bits_uop_stale_pdst = mem_stq_incoming_e_out_bits_uop_stale_pdst; // @[util.scala:106:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_exception = mem_stq_incoming_e_out_bits_uop_exception; // @[util.scala:106:23] wire [63:0] _mem_stq_incoming_e_WIRE_0_bits_uop_exc_cause = mem_stq_incoming_e_out_bits_uop_exc_cause; // @[util.scala:106:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_bypassable = mem_stq_incoming_e_out_bits_uop_bypassable; // @[util.scala:106:23] wire [4:0] _mem_stq_incoming_e_WIRE_0_bits_uop_mem_cmd = mem_stq_incoming_e_out_bits_uop_mem_cmd; // @[util.scala:106:23] wire [1:0] _mem_stq_incoming_e_WIRE_0_bits_uop_mem_size = mem_stq_incoming_e_out_bits_uop_mem_size; // @[util.scala:106:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_mem_signed = mem_stq_incoming_e_out_bits_uop_mem_signed; // @[util.scala:106:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_is_fence = mem_stq_incoming_e_out_bits_uop_is_fence; // @[util.scala:106:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_is_fencei = mem_stq_incoming_e_out_bits_uop_is_fencei; // @[util.scala:106:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_is_amo = mem_stq_incoming_e_out_bits_uop_is_amo; // @[util.scala:106:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_uses_ldq = mem_stq_incoming_e_out_bits_uop_uses_ldq; // @[util.scala:106:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_uses_stq = mem_stq_incoming_e_out_bits_uop_uses_stq; // @[util.scala:106:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_is_sys_pc2epc = mem_stq_incoming_e_out_bits_uop_is_sys_pc2epc; // @[util.scala:106:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_is_unique = mem_stq_incoming_e_out_bits_uop_is_unique; // @[util.scala:106:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_flush_on_commit = mem_stq_incoming_e_out_bits_uop_flush_on_commit; // @[util.scala:106:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_ldst_is_rs1 = mem_stq_incoming_e_out_bits_uop_ldst_is_rs1; // @[util.scala:106:23] wire [5:0] _mem_stq_incoming_e_WIRE_0_bits_uop_ldst = mem_stq_incoming_e_out_bits_uop_ldst; // @[util.scala:106:23] wire [5:0] _mem_stq_incoming_e_WIRE_0_bits_uop_lrs1 = mem_stq_incoming_e_out_bits_uop_lrs1; // @[util.scala:106:23] wire [5:0] _mem_stq_incoming_e_WIRE_0_bits_uop_lrs2 = mem_stq_incoming_e_out_bits_uop_lrs2; // @[util.scala:106:23] wire [5:0] _mem_stq_incoming_e_WIRE_0_bits_uop_lrs3 = mem_stq_incoming_e_out_bits_uop_lrs3; // @[util.scala:106:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_ldst_val = mem_stq_incoming_e_out_bits_uop_ldst_val; // @[util.scala:106:23] wire [1:0] _mem_stq_incoming_e_WIRE_0_bits_uop_dst_rtype = mem_stq_incoming_e_out_bits_uop_dst_rtype; // @[util.scala:106:23] wire [1:0] _mem_stq_incoming_e_WIRE_0_bits_uop_lrs1_rtype = mem_stq_incoming_e_out_bits_uop_lrs1_rtype; // @[util.scala:106:23] wire [1:0] _mem_stq_incoming_e_WIRE_0_bits_uop_lrs2_rtype = mem_stq_incoming_e_out_bits_uop_lrs2_rtype; // @[util.scala:106:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_frs3_en = mem_stq_incoming_e_out_bits_uop_frs3_en; // @[util.scala:106:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_fp_val = mem_stq_incoming_e_out_bits_uop_fp_val; // @[util.scala:106:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_fp_single = mem_stq_incoming_e_out_bits_uop_fp_single; // @[util.scala:106:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_xcpt_pf_if = mem_stq_incoming_e_out_bits_uop_xcpt_pf_if; // @[util.scala:106:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_xcpt_ae_if = mem_stq_incoming_e_out_bits_uop_xcpt_ae_if; // @[util.scala:106:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_xcpt_ma_if = mem_stq_incoming_e_out_bits_uop_xcpt_ma_if; // @[util.scala:106:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_bp_debug_if = mem_stq_incoming_e_out_bits_uop_bp_debug_if; // @[util.scala:106:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_bp_xcpt_if = mem_stq_incoming_e_out_bits_uop_bp_xcpt_if; // @[util.scala:106:23] wire [1:0] _mem_stq_incoming_e_WIRE_0_bits_uop_debug_fsrc = mem_stq_incoming_e_out_bits_uop_debug_fsrc; // @[util.scala:106:23] wire [1:0] _mem_stq_incoming_e_WIRE_0_bits_uop_debug_tsrc = mem_stq_incoming_e_out_bits_uop_debug_tsrc; // @[util.scala:106:23] wire _mem_stq_incoming_e_WIRE_0_bits_addr_valid = mem_stq_incoming_e_out_bits_addr_valid; // @[util.scala:106:23] wire [39:0] _mem_stq_incoming_e_WIRE_0_bits_addr_bits = mem_stq_incoming_e_out_bits_addr_bits; // @[util.scala:106:23] wire _mem_stq_incoming_e_WIRE_0_bits_addr_is_virtual = mem_stq_incoming_e_out_bits_addr_is_virtual; // @[util.scala:106:23] wire _mem_stq_incoming_e_WIRE_0_bits_data_valid = mem_stq_incoming_e_out_bits_data_valid; // @[util.scala:106:23] wire [63:0] _mem_stq_incoming_e_WIRE_0_bits_data_bits = mem_stq_incoming_e_out_bits_data_bits; // @[util.scala:106:23] wire _mem_stq_incoming_e_WIRE_0_bits_committed = mem_stq_incoming_e_out_bits_committed; // @[util.scala:106:23] wire _mem_stq_incoming_e_WIRE_0_bits_succeeded = mem_stq_incoming_e_out_bits_succeeded; // @[util.scala:106:23] wire [63:0] _mem_stq_incoming_e_WIRE_0_bits_debug_wb_data = mem_stq_incoming_e_out_bits_debug_wb_data; // @[util.scala:106:23] wire [7:0] _mem_stq_incoming_e_out_bits_uop_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:85:27, :89:23] assign _mem_stq_incoming_e_out_bits_uop_br_mask_T_1 = stq_incoming_e_0_bits_uop_br_mask & _mem_stq_incoming_e_out_bits_uop_br_mask_T; // @[util.scala:89:{21,23}] assign mem_stq_incoming_e_out_bits_uop_br_mask = _mem_stq_incoming_e_out_bits_uop_br_mask_T_1; // @[util.scala:89:21, :106:23] wire [7:0] _mem_stq_incoming_e_out_valid_T = io_core_brupdate_b1_mispredict_mask_0 & stq_incoming_e_0_bits_uop_br_mask; // @[util.scala:118:51] wire _mem_stq_incoming_e_out_valid_T_1 = |_mem_stq_incoming_e_out_valid_T; // @[util.scala:118:{51,59}] wire _mem_stq_incoming_e_out_valid_T_2 = ~_mem_stq_incoming_e_out_valid_T_1; // @[util.scala:108:34, :118:59] assign _mem_stq_incoming_e_out_valid_T_3 = stq_incoming_e_0_valid & _mem_stq_incoming_e_out_valid_T_2; // @[util.scala:108:{31,34}] assign mem_stq_incoming_e_out_valid = _mem_stq_incoming_e_out_valid_T_3; // @[util.scala:106:23, :108:31] reg mem_stq_incoming_e_0_valid; // @[lsu.scala:911:37] reg [6:0] mem_stq_incoming_e_0_bits_uop_uopc; // @[lsu.scala:911:37] reg [31:0] mem_stq_incoming_e_0_bits_uop_inst; // @[lsu.scala:911:37] reg [31:0] mem_stq_incoming_e_0_bits_uop_debug_inst; // @[lsu.scala:911:37] reg mem_stq_incoming_e_0_bits_uop_is_rvc; // @[lsu.scala:911:37] reg [39:0] mem_stq_incoming_e_0_bits_uop_debug_pc; // @[lsu.scala:911:37] reg [2:0] mem_stq_incoming_e_0_bits_uop_iq_type; // @[lsu.scala:911:37] reg [9:0] mem_stq_incoming_e_0_bits_uop_fu_code; // @[lsu.scala:911:37] reg [3:0] mem_stq_incoming_e_0_bits_uop_ctrl_br_type; // @[lsu.scala:911:37] reg [1:0] mem_stq_incoming_e_0_bits_uop_ctrl_op1_sel; // @[lsu.scala:911:37] reg [2:0] mem_stq_incoming_e_0_bits_uop_ctrl_op2_sel; // @[lsu.scala:911:37] reg [2:0] mem_stq_incoming_e_0_bits_uop_ctrl_imm_sel; // @[lsu.scala:911:37] reg [4:0] mem_stq_incoming_e_0_bits_uop_ctrl_op_fcn; // @[lsu.scala:911:37] reg mem_stq_incoming_e_0_bits_uop_ctrl_fcn_dw; // @[lsu.scala:911:37] reg [2:0] mem_stq_incoming_e_0_bits_uop_ctrl_csr_cmd; // @[lsu.scala:911:37] reg mem_stq_incoming_e_0_bits_uop_ctrl_is_load; // @[lsu.scala:911:37] reg mem_stq_incoming_e_0_bits_uop_ctrl_is_sta; // @[lsu.scala:911:37] reg mem_stq_incoming_e_0_bits_uop_ctrl_is_std; // @[lsu.scala:911:37] reg [1:0] mem_stq_incoming_e_0_bits_uop_iw_state; // @[lsu.scala:911:37] reg mem_stq_incoming_e_0_bits_uop_iw_p1_poisoned; // @[lsu.scala:911:37] reg mem_stq_incoming_e_0_bits_uop_iw_p2_poisoned; // @[lsu.scala:911:37] reg mem_stq_incoming_e_0_bits_uop_is_br; // @[lsu.scala:911:37] reg mem_stq_incoming_e_0_bits_uop_is_jalr; // @[lsu.scala:911:37] reg mem_stq_incoming_e_0_bits_uop_is_jal; // @[lsu.scala:911:37] reg mem_stq_incoming_e_0_bits_uop_is_sfb; // @[lsu.scala:911:37] reg [7:0] mem_stq_incoming_e_0_bits_uop_br_mask; // @[lsu.scala:911:37] reg [2:0] mem_stq_incoming_e_0_bits_uop_br_tag; // @[lsu.scala:911:37] reg [3:0] mem_stq_incoming_e_0_bits_uop_ftq_idx; // @[lsu.scala:911:37] reg mem_stq_incoming_e_0_bits_uop_edge_inst; // @[lsu.scala:911:37] reg [5:0] mem_stq_incoming_e_0_bits_uop_pc_lob; // @[lsu.scala:911:37] reg mem_stq_incoming_e_0_bits_uop_taken; // @[lsu.scala:911:37] reg [19:0] mem_stq_incoming_e_0_bits_uop_imm_packed; // @[lsu.scala:911:37] reg [11:0] mem_stq_incoming_e_0_bits_uop_csr_addr; // @[lsu.scala:911:37] reg [4:0] mem_stq_incoming_e_0_bits_uop_rob_idx; // @[lsu.scala:911:37] reg [2:0] mem_stq_incoming_e_0_bits_uop_ldq_idx; // @[lsu.scala:911:37] reg [2:0] mem_stq_incoming_e_0_bits_uop_stq_idx; // @[lsu.scala:911:37] reg [1:0] mem_stq_incoming_e_0_bits_uop_rxq_idx; // @[lsu.scala:911:37] reg [5:0] mem_stq_incoming_e_0_bits_uop_pdst; // @[lsu.scala:911:37] reg [5:0] mem_stq_incoming_e_0_bits_uop_prs1; // @[lsu.scala:911:37] reg [5:0] mem_stq_incoming_e_0_bits_uop_prs2; // @[lsu.scala:911:37] reg [5:0] mem_stq_incoming_e_0_bits_uop_prs3; // @[lsu.scala:911:37] reg [3:0] mem_stq_incoming_e_0_bits_uop_ppred; // @[lsu.scala:911:37] reg mem_stq_incoming_e_0_bits_uop_prs1_busy; // @[lsu.scala:911:37] reg mem_stq_incoming_e_0_bits_uop_prs2_busy; // @[lsu.scala:911:37] reg mem_stq_incoming_e_0_bits_uop_prs3_busy; // @[lsu.scala:911:37] reg mem_stq_incoming_e_0_bits_uop_ppred_busy; // @[lsu.scala:911:37] reg [5:0] mem_stq_incoming_e_0_bits_uop_stale_pdst; // @[lsu.scala:911:37] reg mem_stq_incoming_e_0_bits_uop_exception; // @[lsu.scala:911:37] reg [63:0] mem_stq_incoming_e_0_bits_uop_exc_cause; // @[lsu.scala:911:37] reg mem_stq_incoming_e_0_bits_uop_bypassable; // @[lsu.scala:911:37] reg [4:0] mem_stq_incoming_e_0_bits_uop_mem_cmd; // @[lsu.scala:911:37] reg [1:0] mem_stq_incoming_e_0_bits_uop_mem_size; // @[lsu.scala:911:37] reg mem_stq_incoming_e_0_bits_uop_mem_signed; // @[lsu.scala:911:37] reg mem_stq_incoming_e_0_bits_uop_is_fence; // @[lsu.scala:911:37] reg mem_stq_incoming_e_0_bits_uop_is_fencei; // @[lsu.scala:911:37] reg mem_stq_incoming_e_0_bits_uop_is_amo; // @[lsu.scala:911:37] reg mem_stq_incoming_e_0_bits_uop_uses_ldq; // @[lsu.scala:911:37] reg mem_stq_incoming_e_0_bits_uop_uses_stq; // @[lsu.scala:911:37] reg mem_stq_incoming_e_0_bits_uop_is_sys_pc2epc; // @[lsu.scala:911:37] reg mem_stq_incoming_e_0_bits_uop_is_unique; // @[lsu.scala:911:37] reg mem_stq_incoming_e_0_bits_uop_flush_on_commit; // @[lsu.scala:911:37] reg mem_stq_incoming_e_0_bits_uop_ldst_is_rs1; // @[lsu.scala:911:37] reg [5:0] mem_stq_incoming_e_0_bits_uop_ldst; // @[lsu.scala:911:37] reg [5:0] mem_stq_incoming_e_0_bits_uop_lrs1; // @[lsu.scala:911:37] reg [5:0] mem_stq_incoming_e_0_bits_uop_lrs2; // @[lsu.scala:911:37] reg [5:0] mem_stq_incoming_e_0_bits_uop_lrs3; // @[lsu.scala:911:37] reg mem_stq_incoming_e_0_bits_uop_ldst_val; // @[lsu.scala:911:37] reg [1:0] mem_stq_incoming_e_0_bits_uop_dst_rtype; // @[lsu.scala:911:37] reg [1:0] mem_stq_incoming_e_0_bits_uop_lrs1_rtype; // @[lsu.scala:911:37] reg [1:0] mem_stq_incoming_e_0_bits_uop_lrs2_rtype; // @[lsu.scala:911:37] reg mem_stq_incoming_e_0_bits_uop_frs3_en; // @[lsu.scala:911:37] reg mem_stq_incoming_e_0_bits_uop_fp_val; // @[lsu.scala:911:37] reg mem_stq_incoming_e_0_bits_uop_fp_single; // @[lsu.scala:911:37] reg mem_stq_incoming_e_0_bits_uop_xcpt_pf_if; // @[lsu.scala:911:37] reg mem_stq_incoming_e_0_bits_uop_xcpt_ae_if; // @[lsu.scala:911:37] reg mem_stq_incoming_e_0_bits_uop_xcpt_ma_if; // @[lsu.scala:911:37] reg mem_stq_incoming_e_0_bits_uop_bp_debug_if; // @[lsu.scala:911:37] reg mem_stq_incoming_e_0_bits_uop_bp_xcpt_if; // @[lsu.scala:911:37] reg [1:0] mem_stq_incoming_e_0_bits_uop_debug_fsrc; // @[lsu.scala:911:37] reg [1:0] mem_stq_incoming_e_0_bits_uop_debug_tsrc; // @[lsu.scala:911:37] reg mem_stq_incoming_e_0_bits_addr_valid; // @[lsu.scala:911:37] reg [39:0] mem_stq_incoming_e_0_bits_addr_bits; // @[lsu.scala:911:37] reg mem_stq_incoming_e_0_bits_addr_is_virtual; // @[lsu.scala:911:37] reg mem_stq_incoming_e_0_bits_data_valid; // @[lsu.scala:911:37] reg [63:0] mem_stq_incoming_e_0_bits_data_bits; // @[lsu.scala:911:37] reg mem_stq_incoming_e_0_bits_committed; // @[lsu.scala:911:37] reg mem_stq_incoming_e_0_bits_succeeded; // @[lsu.scala:911:37] reg [63:0] mem_stq_incoming_e_0_bits_debug_wb_data; // @[lsu.scala:911:37] wire _mem_ldq_wakeup_e_out_valid_T_3; // @[util.scala:108:31] wire [7:0] _mem_ldq_wakeup_e_out_bits_uop_br_mask_T_1; // @[util.scala:89:21] wire [7:0] mem_ldq_wakeup_e_out_bits_uop_br_mask; // @[util.scala:106:23] wire mem_ldq_wakeup_e_out_valid; // @[util.scala:106:23] wire [7:0] _mem_ldq_wakeup_e_out_bits_uop_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:85:27, :89:23] assign _mem_ldq_wakeup_e_out_bits_uop_br_mask_T_1 = _GEN_118[_ldq_wakeup_e_T_1] & _mem_ldq_wakeup_e_out_bits_uop_br_mask_T; // @[util.scala:89:{21,23}] assign mem_ldq_wakeup_e_out_bits_uop_br_mask = _mem_ldq_wakeup_e_out_bits_uop_br_mask_T_1; // @[util.scala:89:21, :106:23] wire _mem_ldq_wakeup_e_out_valid_T_1 = |_mem_ldq_wakeup_e_out_valid_T; // @[util.scala:118:{51,59}] wire _mem_ldq_wakeup_e_out_valid_T_2 = ~_mem_ldq_wakeup_e_out_valid_T_1; // @[util.scala:108:34, :118:59] assign _mem_ldq_wakeup_e_out_valid_T_3 = _GEN_92[_ldq_wakeup_e_T_1] & _mem_ldq_wakeup_e_out_valid_T_2; // @[util.scala:108:{31,34}] assign mem_ldq_wakeup_e_out_valid = _mem_ldq_wakeup_e_out_valid_T_3; // @[util.scala:106:23, :108:31] reg mem_ldq_wakeup_e_valid; // @[lsu.scala:912:37] reg [6:0] mem_ldq_wakeup_e_bits_uop_uopc; // @[lsu.scala:912:37] reg [31:0] mem_ldq_wakeup_e_bits_uop_inst; // @[lsu.scala:912:37] reg [31:0] mem_ldq_wakeup_e_bits_uop_debug_inst; // @[lsu.scala:912:37] reg mem_ldq_wakeup_e_bits_uop_is_rvc; // @[lsu.scala:912:37] reg [39:0] mem_ldq_wakeup_e_bits_uop_debug_pc; // @[lsu.scala:912:37] reg [2:0] mem_ldq_wakeup_e_bits_uop_iq_type; // @[lsu.scala:912:37] reg [9:0] mem_ldq_wakeup_e_bits_uop_fu_code; // @[lsu.scala:912:37] reg [3:0] mem_ldq_wakeup_e_bits_uop_ctrl_br_type; // @[lsu.scala:912:37] reg [1:0] mem_ldq_wakeup_e_bits_uop_ctrl_op1_sel; // @[lsu.scala:912:37] reg [2:0] mem_ldq_wakeup_e_bits_uop_ctrl_op2_sel; // @[lsu.scala:912:37] reg [2:0] mem_ldq_wakeup_e_bits_uop_ctrl_imm_sel; // @[lsu.scala:912:37] reg [4:0] mem_ldq_wakeup_e_bits_uop_ctrl_op_fcn; // @[lsu.scala:912:37] reg mem_ldq_wakeup_e_bits_uop_ctrl_fcn_dw; // @[lsu.scala:912:37] reg [2:0] mem_ldq_wakeup_e_bits_uop_ctrl_csr_cmd; // @[lsu.scala:912:37] reg mem_ldq_wakeup_e_bits_uop_ctrl_is_load; // @[lsu.scala:912:37] reg mem_ldq_wakeup_e_bits_uop_ctrl_is_sta; // @[lsu.scala:912:37] reg mem_ldq_wakeup_e_bits_uop_ctrl_is_std; // @[lsu.scala:912:37] reg [1:0] mem_ldq_wakeup_e_bits_uop_iw_state; // @[lsu.scala:912:37] reg mem_ldq_wakeup_e_bits_uop_iw_p1_poisoned; // @[lsu.scala:912:37] reg mem_ldq_wakeup_e_bits_uop_iw_p2_poisoned; // @[lsu.scala:912:37] reg mem_ldq_wakeup_e_bits_uop_is_br; // @[lsu.scala:912:37] reg mem_ldq_wakeup_e_bits_uop_is_jalr; // @[lsu.scala:912:37] reg mem_ldq_wakeup_e_bits_uop_is_jal; // @[lsu.scala:912:37] reg mem_ldq_wakeup_e_bits_uop_is_sfb; // @[lsu.scala:912:37] reg [7:0] mem_ldq_wakeup_e_bits_uop_br_mask; // @[lsu.scala:912:37] reg [2:0] mem_ldq_wakeup_e_bits_uop_br_tag; // @[lsu.scala:912:37] reg [3:0] mem_ldq_wakeup_e_bits_uop_ftq_idx; // @[lsu.scala:912:37] reg mem_ldq_wakeup_e_bits_uop_edge_inst; // @[lsu.scala:912:37] reg [5:0] mem_ldq_wakeup_e_bits_uop_pc_lob; // @[lsu.scala:912:37] reg mem_ldq_wakeup_e_bits_uop_taken; // @[lsu.scala:912:37] reg [19:0] mem_ldq_wakeup_e_bits_uop_imm_packed; // @[lsu.scala:912:37] reg [11:0] mem_ldq_wakeup_e_bits_uop_csr_addr; // @[lsu.scala:912:37] reg [4:0] mem_ldq_wakeup_e_bits_uop_rob_idx; // @[lsu.scala:912:37] reg [2:0] mem_ldq_wakeup_e_bits_uop_ldq_idx; // @[lsu.scala:912:37] reg [2:0] mem_ldq_wakeup_e_bits_uop_stq_idx; // @[lsu.scala:912:37] reg [1:0] mem_ldq_wakeup_e_bits_uop_rxq_idx; // @[lsu.scala:912:37] reg [5:0] mem_ldq_wakeup_e_bits_uop_pdst; // @[lsu.scala:912:37] reg [5:0] mem_ldq_wakeup_e_bits_uop_prs1; // @[lsu.scala:912:37] reg [5:0] mem_ldq_wakeup_e_bits_uop_prs2; // @[lsu.scala:912:37] reg [5:0] mem_ldq_wakeup_e_bits_uop_prs3; // @[lsu.scala:912:37] reg [3:0] mem_ldq_wakeup_e_bits_uop_ppred; // @[lsu.scala:912:37] reg mem_ldq_wakeup_e_bits_uop_prs1_busy; // @[lsu.scala:912:37] reg mem_ldq_wakeup_e_bits_uop_prs2_busy; // @[lsu.scala:912:37] reg mem_ldq_wakeup_e_bits_uop_prs3_busy; // @[lsu.scala:912:37] reg mem_ldq_wakeup_e_bits_uop_ppred_busy; // @[lsu.scala:912:37] reg [5:0] mem_ldq_wakeup_e_bits_uop_stale_pdst; // @[lsu.scala:912:37] reg mem_ldq_wakeup_e_bits_uop_exception; // @[lsu.scala:912:37] reg [63:0] mem_ldq_wakeup_e_bits_uop_exc_cause; // @[lsu.scala:912:37] reg mem_ldq_wakeup_e_bits_uop_bypassable; // @[lsu.scala:912:37] reg [4:0] mem_ldq_wakeup_e_bits_uop_mem_cmd; // @[lsu.scala:912:37] reg [1:0] mem_ldq_wakeup_e_bits_uop_mem_size; // @[lsu.scala:912:37] reg mem_ldq_wakeup_e_bits_uop_mem_signed; // @[lsu.scala:912:37] reg mem_ldq_wakeup_e_bits_uop_is_fence; // @[lsu.scala:912:37] reg mem_ldq_wakeup_e_bits_uop_is_fencei; // @[lsu.scala:912:37] reg mem_ldq_wakeup_e_bits_uop_is_amo; // @[lsu.scala:912:37] reg mem_ldq_wakeup_e_bits_uop_uses_ldq; // @[lsu.scala:912:37] reg mem_ldq_wakeup_e_bits_uop_uses_stq; // @[lsu.scala:912:37] reg mem_ldq_wakeup_e_bits_uop_is_sys_pc2epc; // @[lsu.scala:912:37] reg mem_ldq_wakeup_e_bits_uop_is_unique; // @[lsu.scala:912:37] reg mem_ldq_wakeup_e_bits_uop_flush_on_commit; // @[lsu.scala:912:37] reg mem_ldq_wakeup_e_bits_uop_ldst_is_rs1; // @[lsu.scala:912:37] reg [5:0] mem_ldq_wakeup_e_bits_uop_ldst; // @[lsu.scala:912:37] reg [5:0] mem_ldq_wakeup_e_bits_uop_lrs1; // @[lsu.scala:912:37] reg [5:0] mem_ldq_wakeup_e_bits_uop_lrs2; // @[lsu.scala:912:37] reg [5:0] mem_ldq_wakeup_e_bits_uop_lrs3; // @[lsu.scala:912:37] reg mem_ldq_wakeup_e_bits_uop_ldst_val; // @[lsu.scala:912:37] reg [1:0] mem_ldq_wakeup_e_bits_uop_dst_rtype; // @[lsu.scala:912:37] reg [1:0] mem_ldq_wakeup_e_bits_uop_lrs1_rtype; // @[lsu.scala:912:37] reg [1:0] mem_ldq_wakeup_e_bits_uop_lrs2_rtype; // @[lsu.scala:912:37] reg mem_ldq_wakeup_e_bits_uop_frs3_en; // @[lsu.scala:912:37] reg mem_ldq_wakeup_e_bits_uop_fp_val; // @[lsu.scala:912:37] reg mem_ldq_wakeup_e_bits_uop_fp_single; // @[lsu.scala:912:37] reg mem_ldq_wakeup_e_bits_uop_xcpt_pf_if; // @[lsu.scala:912:37] reg mem_ldq_wakeup_e_bits_uop_xcpt_ae_if; // @[lsu.scala:912:37] reg mem_ldq_wakeup_e_bits_uop_xcpt_ma_if; // @[lsu.scala:912:37] reg mem_ldq_wakeup_e_bits_uop_bp_debug_if; // @[lsu.scala:912:37] reg mem_ldq_wakeup_e_bits_uop_bp_xcpt_if; // @[lsu.scala:912:37] reg [1:0] mem_ldq_wakeup_e_bits_uop_debug_fsrc; // @[lsu.scala:912:37] reg [1:0] mem_ldq_wakeup_e_bits_uop_debug_tsrc; // @[lsu.scala:912:37] reg mem_ldq_wakeup_e_bits_addr_valid; // @[lsu.scala:912:37] reg [39:0] mem_ldq_wakeup_e_bits_addr_bits; // @[lsu.scala:912:37] reg mem_ldq_wakeup_e_bits_addr_is_virtual; // @[lsu.scala:912:37] reg mem_ldq_wakeup_e_bits_addr_is_uncacheable; // @[lsu.scala:912:37] reg mem_ldq_wakeup_e_bits_executed; // @[lsu.scala:912:37] reg mem_ldq_wakeup_e_bits_succeeded; // @[lsu.scala:912:37] reg mem_ldq_wakeup_e_bits_order_fail; // @[lsu.scala:912:37] reg mem_ldq_wakeup_e_bits_observed; // @[lsu.scala:912:37] reg [7:0] mem_ldq_wakeup_e_bits_st_dep_mask; // @[lsu.scala:912:37] reg [2:0] mem_ldq_wakeup_e_bits_youngest_stq_idx; // @[lsu.scala:912:37] reg mem_ldq_wakeup_e_bits_forward_std_val; // @[lsu.scala:912:37] reg [2:0] mem_ldq_wakeup_e_bits_forward_stq_idx; // @[lsu.scala:912:37] reg [63:0] mem_ldq_wakeup_e_bits_debug_wb_data; // @[lsu.scala:912:37] wire _mem_ldq_retry_e_out_valid_T_3; // @[util.scala:108:31] wire [7:0] _mem_ldq_retry_e_out_bits_uop_br_mask_T_1; // @[util.scala:89:21] wire [7:0] mem_ldq_retry_e_out_bits_uop_br_mask; // @[util.scala:106:23] wire mem_ldq_retry_e_out_valid; // @[util.scala:106:23] wire [7:0] _mem_ldq_retry_e_out_bits_uop_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:85:27, :89:23] assign _mem_ldq_retry_e_out_bits_uop_br_mask_T_1 = _GEN_118[_ldq_retry_e_T_1] & _mem_ldq_retry_e_out_bits_uop_br_mask_T; // @[util.scala:89:{21,23}] assign mem_ldq_retry_e_out_bits_uop_br_mask = _mem_ldq_retry_e_out_bits_uop_br_mask_T_1; // @[util.scala:89:21, :106:23] wire _mem_ldq_retry_e_out_valid_T_1 = |_mem_ldq_retry_e_out_valid_T; // @[util.scala:118:{51,59}] wire _mem_ldq_retry_e_out_valid_T_2 = ~_mem_ldq_retry_e_out_valid_T_1; // @[util.scala:108:34, :118:59] assign _mem_ldq_retry_e_out_valid_T_3 = _GEN_92[_ldq_retry_e_T_1] & _mem_ldq_retry_e_out_valid_T_2; // @[util.scala:108:{31,34}] assign mem_ldq_retry_e_out_valid = _mem_ldq_retry_e_out_valid_T_3; // @[util.scala:106:23, :108:31] reg mem_ldq_retry_e_valid; // @[lsu.scala:913:37] reg [6:0] mem_ldq_retry_e_bits_uop_uopc; // @[lsu.scala:913:37] reg [31:0] mem_ldq_retry_e_bits_uop_inst; // @[lsu.scala:913:37] reg [31:0] mem_ldq_retry_e_bits_uop_debug_inst; // @[lsu.scala:913:37] reg mem_ldq_retry_e_bits_uop_is_rvc; // @[lsu.scala:913:37] reg [39:0] mem_ldq_retry_e_bits_uop_debug_pc; // @[lsu.scala:913:37] reg [2:0] mem_ldq_retry_e_bits_uop_iq_type; // @[lsu.scala:913:37] reg [9:0] mem_ldq_retry_e_bits_uop_fu_code; // @[lsu.scala:913:37] reg [3:0] mem_ldq_retry_e_bits_uop_ctrl_br_type; // @[lsu.scala:913:37] reg [1:0] mem_ldq_retry_e_bits_uop_ctrl_op1_sel; // @[lsu.scala:913:37] reg [2:0] mem_ldq_retry_e_bits_uop_ctrl_op2_sel; // @[lsu.scala:913:37] reg [2:0] mem_ldq_retry_e_bits_uop_ctrl_imm_sel; // @[lsu.scala:913:37] reg [4:0] mem_ldq_retry_e_bits_uop_ctrl_op_fcn; // @[lsu.scala:913:37] reg mem_ldq_retry_e_bits_uop_ctrl_fcn_dw; // @[lsu.scala:913:37] reg [2:0] mem_ldq_retry_e_bits_uop_ctrl_csr_cmd; // @[lsu.scala:913:37] reg mem_ldq_retry_e_bits_uop_ctrl_is_load; // @[lsu.scala:913:37] reg mem_ldq_retry_e_bits_uop_ctrl_is_sta; // @[lsu.scala:913:37] reg mem_ldq_retry_e_bits_uop_ctrl_is_std; // @[lsu.scala:913:37] reg [1:0] mem_ldq_retry_e_bits_uop_iw_state; // @[lsu.scala:913:37] reg mem_ldq_retry_e_bits_uop_iw_p1_poisoned; // @[lsu.scala:913:37] reg mem_ldq_retry_e_bits_uop_iw_p2_poisoned; // @[lsu.scala:913:37] reg mem_ldq_retry_e_bits_uop_is_br; // @[lsu.scala:913:37] reg mem_ldq_retry_e_bits_uop_is_jalr; // @[lsu.scala:913:37] reg mem_ldq_retry_e_bits_uop_is_jal; // @[lsu.scala:913:37] reg mem_ldq_retry_e_bits_uop_is_sfb; // @[lsu.scala:913:37] reg [7:0] mem_ldq_retry_e_bits_uop_br_mask; // @[lsu.scala:913:37] reg [2:0] mem_ldq_retry_e_bits_uop_br_tag; // @[lsu.scala:913:37] reg [3:0] mem_ldq_retry_e_bits_uop_ftq_idx; // @[lsu.scala:913:37] reg mem_ldq_retry_e_bits_uop_edge_inst; // @[lsu.scala:913:37] reg [5:0] mem_ldq_retry_e_bits_uop_pc_lob; // @[lsu.scala:913:37] reg mem_ldq_retry_e_bits_uop_taken; // @[lsu.scala:913:37] reg [19:0] mem_ldq_retry_e_bits_uop_imm_packed; // @[lsu.scala:913:37] reg [11:0] mem_ldq_retry_e_bits_uop_csr_addr; // @[lsu.scala:913:37] reg [4:0] mem_ldq_retry_e_bits_uop_rob_idx; // @[lsu.scala:913:37] reg [2:0] mem_ldq_retry_e_bits_uop_ldq_idx; // @[lsu.scala:913:37] reg [2:0] mem_ldq_retry_e_bits_uop_stq_idx; // @[lsu.scala:913:37] reg [1:0] mem_ldq_retry_e_bits_uop_rxq_idx; // @[lsu.scala:913:37] reg [5:0] mem_ldq_retry_e_bits_uop_pdst; // @[lsu.scala:913:37] reg [5:0] mem_ldq_retry_e_bits_uop_prs1; // @[lsu.scala:913:37] reg [5:0] mem_ldq_retry_e_bits_uop_prs2; // @[lsu.scala:913:37] reg [5:0] mem_ldq_retry_e_bits_uop_prs3; // @[lsu.scala:913:37] reg [3:0] mem_ldq_retry_e_bits_uop_ppred; // @[lsu.scala:913:37] reg mem_ldq_retry_e_bits_uop_prs1_busy; // @[lsu.scala:913:37] reg mem_ldq_retry_e_bits_uop_prs2_busy; // @[lsu.scala:913:37] reg mem_ldq_retry_e_bits_uop_prs3_busy; // @[lsu.scala:913:37] reg mem_ldq_retry_e_bits_uop_ppred_busy; // @[lsu.scala:913:37] reg [5:0] mem_ldq_retry_e_bits_uop_stale_pdst; // @[lsu.scala:913:37] reg mem_ldq_retry_e_bits_uop_exception; // @[lsu.scala:913:37] reg [63:0] mem_ldq_retry_e_bits_uop_exc_cause; // @[lsu.scala:913:37] reg mem_ldq_retry_e_bits_uop_bypassable; // @[lsu.scala:913:37] reg [4:0] mem_ldq_retry_e_bits_uop_mem_cmd; // @[lsu.scala:913:37] reg [1:0] mem_ldq_retry_e_bits_uop_mem_size; // @[lsu.scala:913:37] reg mem_ldq_retry_e_bits_uop_mem_signed; // @[lsu.scala:913:37] reg mem_ldq_retry_e_bits_uop_is_fence; // @[lsu.scala:913:37] reg mem_ldq_retry_e_bits_uop_is_fencei; // @[lsu.scala:913:37] reg mem_ldq_retry_e_bits_uop_is_amo; // @[lsu.scala:913:37] reg mem_ldq_retry_e_bits_uop_uses_ldq; // @[lsu.scala:913:37] reg mem_ldq_retry_e_bits_uop_uses_stq; // @[lsu.scala:913:37] reg mem_ldq_retry_e_bits_uop_is_sys_pc2epc; // @[lsu.scala:913:37] reg mem_ldq_retry_e_bits_uop_is_unique; // @[lsu.scala:913:37] reg mem_ldq_retry_e_bits_uop_flush_on_commit; // @[lsu.scala:913:37] reg mem_ldq_retry_e_bits_uop_ldst_is_rs1; // @[lsu.scala:913:37] reg [5:0] mem_ldq_retry_e_bits_uop_ldst; // @[lsu.scala:913:37] reg [5:0] mem_ldq_retry_e_bits_uop_lrs1; // @[lsu.scala:913:37] reg [5:0] mem_ldq_retry_e_bits_uop_lrs2; // @[lsu.scala:913:37] reg [5:0] mem_ldq_retry_e_bits_uop_lrs3; // @[lsu.scala:913:37] reg mem_ldq_retry_e_bits_uop_ldst_val; // @[lsu.scala:913:37] reg [1:0] mem_ldq_retry_e_bits_uop_dst_rtype; // @[lsu.scala:913:37] reg [1:0] mem_ldq_retry_e_bits_uop_lrs1_rtype; // @[lsu.scala:913:37] reg [1:0] mem_ldq_retry_e_bits_uop_lrs2_rtype; // @[lsu.scala:913:37] reg mem_ldq_retry_e_bits_uop_frs3_en; // @[lsu.scala:913:37] reg mem_ldq_retry_e_bits_uop_fp_val; // @[lsu.scala:913:37] reg mem_ldq_retry_e_bits_uop_fp_single; // @[lsu.scala:913:37] reg mem_ldq_retry_e_bits_uop_xcpt_pf_if; // @[lsu.scala:913:37] reg mem_ldq_retry_e_bits_uop_xcpt_ae_if; // @[lsu.scala:913:37] reg mem_ldq_retry_e_bits_uop_xcpt_ma_if; // @[lsu.scala:913:37] reg mem_ldq_retry_e_bits_uop_bp_debug_if; // @[lsu.scala:913:37] reg mem_ldq_retry_e_bits_uop_bp_xcpt_if; // @[lsu.scala:913:37] reg [1:0] mem_ldq_retry_e_bits_uop_debug_fsrc; // @[lsu.scala:913:37] reg [1:0] mem_ldq_retry_e_bits_uop_debug_tsrc; // @[lsu.scala:913:37] reg mem_ldq_retry_e_bits_addr_valid; // @[lsu.scala:913:37] reg [39:0] mem_ldq_retry_e_bits_addr_bits; // @[lsu.scala:913:37] reg mem_ldq_retry_e_bits_addr_is_virtual; // @[lsu.scala:913:37] reg mem_ldq_retry_e_bits_addr_is_uncacheable; // @[lsu.scala:913:37] reg mem_ldq_retry_e_bits_executed; // @[lsu.scala:913:37] reg mem_ldq_retry_e_bits_succeeded; // @[lsu.scala:913:37] reg mem_ldq_retry_e_bits_order_fail; // @[lsu.scala:913:37] reg mem_ldq_retry_e_bits_observed; // @[lsu.scala:913:37] reg [7:0] mem_ldq_retry_e_bits_st_dep_mask; // @[lsu.scala:913:37] reg [2:0] mem_ldq_retry_e_bits_youngest_stq_idx; // @[lsu.scala:913:37] reg mem_ldq_retry_e_bits_forward_std_val; // @[lsu.scala:913:37] reg [2:0] mem_ldq_retry_e_bits_forward_stq_idx; // @[lsu.scala:913:37] reg [63:0] mem_ldq_retry_e_bits_debug_wb_data; // @[lsu.scala:913:37] wire _mem_stq_retry_e_out_valid_T_3; // @[util.scala:108:31] wire [7:0] _mem_stq_retry_e_out_bits_uop_br_mask_T_1; // @[util.scala:89:21] wire [7:0] mem_stq_retry_e_out_bits_uop_br_mask; // @[util.scala:106:23] wire mem_stq_retry_e_out_valid; // @[util.scala:106:23] wire [7:0] _mem_stq_retry_e_out_bits_uop_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:85:27, :89:23] assign _mem_stq_retry_e_out_bits_uop_br_mask_T_1 = _GEN_25[_stq_retry_e_T_1] & _mem_stq_retry_e_out_bits_uop_br_mask_T; // @[util.scala:89:{21,23}] assign mem_stq_retry_e_out_bits_uop_br_mask = _mem_stq_retry_e_out_bits_uop_br_mask_T_1; // @[util.scala:89:21, :106:23] wire _mem_stq_retry_e_out_valid_T_1 = |_mem_stq_retry_e_out_valid_T; // @[util.scala:118:{51,59}] wire _mem_stq_retry_e_out_valid_T_2 = ~_mem_stq_retry_e_out_valid_T_1; // @[util.scala:108:34, :118:59] assign _mem_stq_retry_e_out_valid_T_3 = _GEN[_stq_retry_e_T_1] & _mem_stq_retry_e_out_valid_T_2; // @[util.scala:108:{31,34}] assign mem_stq_retry_e_out_valid = _mem_stq_retry_e_out_valid_T_3; // @[util.scala:106:23, :108:31] reg mem_stq_retry_e_valid; // @[lsu.scala:914:37] reg [6:0] mem_stq_retry_e_bits_uop_uopc; // @[lsu.scala:914:37] reg [31:0] mem_stq_retry_e_bits_uop_inst; // @[lsu.scala:914:37] reg [31:0] mem_stq_retry_e_bits_uop_debug_inst; // @[lsu.scala:914:37] reg mem_stq_retry_e_bits_uop_is_rvc; // @[lsu.scala:914:37] reg [39:0] mem_stq_retry_e_bits_uop_debug_pc; // @[lsu.scala:914:37] reg [2:0] mem_stq_retry_e_bits_uop_iq_type; // @[lsu.scala:914:37] reg [9:0] mem_stq_retry_e_bits_uop_fu_code; // @[lsu.scala:914:37] reg [3:0] mem_stq_retry_e_bits_uop_ctrl_br_type; // @[lsu.scala:914:37] reg [1:0] mem_stq_retry_e_bits_uop_ctrl_op1_sel; // @[lsu.scala:914:37] reg [2:0] mem_stq_retry_e_bits_uop_ctrl_op2_sel; // @[lsu.scala:914:37] reg [2:0] mem_stq_retry_e_bits_uop_ctrl_imm_sel; // @[lsu.scala:914:37] reg [4:0] mem_stq_retry_e_bits_uop_ctrl_op_fcn; // @[lsu.scala:914:37] reg mem_stq_retry_e_bits_uop_ctrl_fcn_dw; // @[lsu.scala:914:37] reg [2:0] mem_stq_retry_e_bits_uop_ctrl_csr_cmd; // @[lsu.scala:914:37] reg mem_stq_retry_e_bits_uop_ctrl_is_load; // @[lsu.scala:914:37] reg mem_stq_retry_e_bits_uop_ctrl_is_sta; // @[lsu.scala:914:37] reg mem_stq_retry_e_bits_uop_ctrl_is_std; // @[lsu.scala:914:37] reg [1:0] mem_stq_retry_e_bits_uop_iw_state; // @[lsu.scala:914:37] reg mem_stq_retry_e_bits_uop_iw_p1_poisoned; // @[lsu.scala:914:37] reg mem_stq_retry_e_bits_uop_iw_p2_poisoned; // @[lsu.scala:914:37] reg mem_stq_retry_e_bits_uop_is_br; // @[lsu.scala:914:37] reg mem_stq_retry_e_bits_uop_is_jalr; // @[lsu.scala:914:37] reg mem_stq_retry_e_bits_uop_is_jal; // @[lsu.scala:914:37] reg mem_stq_retry_e_bits_uop_is_sfb; // @[lsu.scala:914:37] reg [7:0] mem_stq_retry_e_bits_uop_br_mask; // @[lsu.scala:914:37] reg [2:0] mem_stq_retry_e_bits_uop_br_tag; // @[lsu.scala:914:37] reg [3:0] mem_stq_retry_e_bits_uop_ftq_idx; // @[lsu.scala:914:37] reg mem_stq_retry_e_bits_uop_edge_inst; // @[lsu.scala:914:37] reg [5:0] mem_stq_retry_e_bits_uop_pc_lob; // @[lsu.scala:914:37] reg mem_stq_retry_e_bits_uop_taken; // @[lsu.scala:914:37] reg [19:0] mem_stq_retry_e_bits_uop_imm_packed; // @[lsu.scala:914:37] reg [11:0] mem_stq_retry_e_bits_uop_csr_addr; // @[lsu.scala:914:37] reg [4:0] mem_stq_retry_e_bits_uop_rob_idx; // @[lsu.scala:914:37] reg [2:0] mem_stq_retry_e_bits_uop_ldq_idx; // @[lsu.scala:914:37] reg [2:0] mem_stq_retry_e_bits_uop_stq_idx; // @[lsu.scala:914:37] reg [1:0] mem_stq_retry_e_bits_uop_rxq_idx; // @[lsu.scala:914:37] reg [5:0] mem_stq_retry_e_bits_uop_pdst; // @[lsu.scala:914:37] reg [5:0] mem_stq_retry_e_bits_uop_prs1; // @[lsu.scala:914:37] reg [5:0] mem_stq_retry_e_bits_uop_prs2; // @[lsu.scala:914:37] reg [5:0] mem_stq_retry_e_bits_uop_prs3; // @[lsu.scala:914:37] reg [3:0] mem_stq_retry_e_bits_uop_ppred; // @[lsu.scala:914:37] reg mem_stq_retry_e_bits_uop_prs1_busy; // @[lsu.scala:914:37] reg mem_stq_retry_e_bits_uop_prs2_busy; // @[lsu.scala:914:37] reg mem_stq_retry_e_bits_uop_prs3_busy; // @[lsu.scala:914:37] reg mem_stq_retry_e_bits_uop_ppred_busy; // @[lsu.scala:914:37] reg [5:0] mem_stq_retry_e_bits_uop_stale_pdst; // @[lsu.scala:914:37] reg mem_stq_retry_e_bits_uop_exception; // @[lsu.scala:914:37] reg [63:0] mem_stq_retry_e_bits_uop_exc_cause; // @[lsu.scala:914:37] reg mem_stq_retry_e_bits_uop_bypassable; // @[lsu.scala:914:37] reg [4:0] mem_stq_retry_e_bits_uop_mem_cmd; // @[lsu.scala:914:37] reg [1:0] mem_stq_retry_e_bits_uop_mem_size; // @[lsu.scala:914:37] reg mem_stq_retry_e_bits_uop_mem_signed; // @[lsu.scala:914:37] reg mem_stq_retry_e_bits_uop_is_fence; // @[lsu.scala:914:37] reg mem_stq_retry_e_bits_uop_is_fencei; // @[lsu.scala:914:37] reg mem_stq_retry_e_bits_uop_is_amo; // @[lsu.scala:914:37] reg mem_stq_retry_e_bits_uop_uses_ldq; // @[lsu.scala:914:37] reg mem_stq_retry_e_bits_uop_uses_stq; // @[lsu.scala:914:37] reg mem_stq_retry_e_bits_uop_is_sys_pc2epc; // @[lsu.scala:914:37] reg mem_stq_retry_e_bits_uop_is_unique; // @[lsu.scala:914:37] reg mem_stq_retry_e_bits_uop_flush_on_commit; // @[lsu.scala:914:37] reg mem_stq_retry_e_bits_uop_ldst_is_rs1; // @[lsu.scala:914:37] reg [5:0] mem_stq_retry_e_bits_uop_ldst; // @[lsu.scala:914:37] reg [5:0] mem_stq_retry_e_bits_uop_lrs1; // @[lsu.scala:914:37] reg [5:0] mem_stq_retry_e_bits_uop_lrs2; // @[lsu.scala:914:37] reg [5:0] mem_stq_retry_e_bits_uop_lrs3; // @[lsu.scala:914:37] reg mem_stq_retry_e_bits_uop_ldst_val; // @[lsu.scala:914:37] reg [1:0] mem_stq_retry_e_bits_uop_dst_rtype; // @[lsu.scala:914:37] reg [1:0] mem_stq_retry_e_bits_uop_lrs1_rtype; // @[lsu.scala:914:37] reg [1:0] mem_stq_retry_e_bits_uop_lrs2_rtype; // @[lsu.scala:914:37] reg mem_stq_retry_e_bits_uop_frs3_en; // @[lsu.scala:914:37] reg mem_stq_retry_e_bits_uop_fp_val; // @[lsu.scala:914:37] reg mem_stq_retry_e_bits_uop_fp_single; // @[lsu.scala:914:37] reg mem_stq_retry_e_bits_uop_xcpt_pf_if; // @[lsu.scala:914:37] reg mem_stq_retry_e_bits_uop_xcpt_ae_if; // @[lsu.scala:914:37] reg mem_stq_retry_e_bits_uop_xcpt_ma_if; // @[lsu.scala:914:37] reg mem_stq_retry_e_bits_uop_bp_debug_if; // @[lsu.scala:914:37] reg mem_stq_retry_e_bits_uop_bp_xcpt_if; // @[lsu.scala:914:37] reg [1:0] mem_stq_retry_e_bits_uop_debug_fsrc; // @[lsu.scala:914:37] reg [1:0] mem_stq_retry_e_bits_uop_debug_tsrc; // @[lsu.scala:914:37] reg mem_stq_retry_e_bits_addr_valid; // @[lsu.scala:914:37] reg [39:0] mem_stq_retry_e_bits_addr_bits; // @[lsu.scala:914:37] reg mem_stq_retry_e_bits_addr_is_virtual; // @[lsu.scala:914:37] reg mem_stq_retry_e_bits_data_valid; // @[lsu.scala:914:37] reg [63:0] mem_stq_retry_e_bits_data_bits; // @[lsu.scala:914:37] reg mem_stq_retry_e_bits_committed; // @[lsu.scala:914:37] reg mem_stq_retry_e_bits_succeeded; // @[lsu.scala:914:37] reg [63:0] mem_stq_retry_e_bits_debug_wb_data; // @[lsu.scala:914:37] wire _mem_ldq_e_T_valid = fired_load_wakeup_0 & mem_ldq_wakeup_e_valid; // @[lsu.scala:263:49, :912:37, :918:33] wire [6:0] _mem_ldq_e_T_bits_uop_uopc = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_uopc : 7'h0; // @[lsu.scala:263:49, :912:37, :918:33] wire [31:0] _mem_ldq_e_T_bits_uop_inst = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_inst : 32'h0; // @[lsu.scala:263:49, :912:37, :918:33] wire [31:0] _mem_ldq_e_T_bits_uop_debug_inst = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_debug_inst : 32'h0; // @[lsu.scala:263:49, :912:37, :918:33] wire _mem_ldq_e_T_bits_uop_is_rvc = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_is_rvc; // @[lsu.scala:263:49, :912:37, :918:33] wire [39:0] _mem_ldq_e_T_bits_uop_debug_pc = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_debug_pc : 40'h0; // @[lsu.scala:263:49, :912:37, :918:33] wire [2:0] _mem_ldq_e_T_bits_uop_iq_type = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_iq_type : 3'h0; // @[lsu.scala:263:49, :912:37, :918:33] wire [9:0] _mem_ldq_e_T_bits_uop_fu_code = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_fu_code : 10'h0; // @[lsu.scala:263:49, :912:37, :918:33] wire [3:0] _mem_ldq_e_T_bits_uop_ctrl_br_type = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_ctrl_br_type : 4'h0; // @[lsu.scala:263:49, :912:37, :918:33] wire [1:0] _mem_ldq_e_T_bits_uop_ctrl_op1_sel = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_ctrl_op1_sel : 2'h0; // @[lsu.scala:263:49, :912:37, :918:33] wire [2:0] _mem_ldq_e_T_bits_uop_ctrl_op2_sel = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_ctrl_op2_sel : 3'h0; // @[lsu.scala:263:49, :912:37, :918:33] wire [2:0] _mem_ldq_e_T_bits_uop_ctrl_imm_sel = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_ctrl_imm_sel : 3'h0; // @[lsu.scala:263:49, :912:37, :918:33] wire [4:0] _mem_ldq_e_T_bits_uop_ctrl_op_fcn = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_ctrl_op_fcn : 5'h0; // @[lsu.scala:263:49, :912:37, :918:33] wire _mem_ldq_e_T_bits_uop_ctrl_fcn_dw = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_ctrl_fcn_dw; // @[lsu.scala:263:49, :912:37, :918:33] wire [2:0] _mem_ldq_e_T_bits_uop_ctrl_csr_cmd = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_ctrl_csr_cmd : 3'h0; // @[lsu.scala:263:49, :912:37, :918:33] wire _mem_ldq_e_T_bits_uop_ctrl_is_load = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_ctrl_is_load; // @[lsu.scala:263:49, :912:37, :918:33] wire _mem_ldq_e_T_bits_uop_ctrl_is_sta = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_ctrl_is_sta; // @[lsu.scala:263:49, :912:37, :918:33] wire _mem_ldq_e_T_bits_uop_ctrl_is_std = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_ctrl_is_std; // @[lsu.scala:263:49, :912:37, :918:33] wire [1:0] _mem_ldq_e_T_bits_uop_iw_state = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_iw_state : 2'h0; // @[lsu.scala:263:49, :912:37, :918:33] wire _mem_ldq_e_T_bits_uop_iw_p1_poisoned = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_iw_p1_poisoned; // @[lsu.scala:263:49, :912:37, :918:33] wire _mem_ldq_e_T_bits_uop_iw_p2_poisoned = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_iw_p2_poisoned; // @[lsu.scala:263:49, :912:37, :918:33] wire _mem_ldq_e_T_bits_uop_is_br = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_is_br; // @[lsu.scala:263:49, :912:37, :918:33] wire _mem_ldq_e_T_bits_uop_is_jalr = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_is_jalr; // @[lsu.scala:263:49, :912:37, :918:33] wire _mem_ldq_e_T_bits_uop_is_jal = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_is_jal; // @[lsu.scala:263:49, :912:37, :918:33] wire _mem_ldq_e_T_bits_uop_is_sfb = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_is_sfb; // @[lsu.scala:263:49, :912:37, :918:33] wire [7:0] _mem_ldq_e_T_bits_uop_br_mask = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_br_mask : 8'h0; // @[lsu.scala:263:49, :912:37, :918:33] wire [2:0] _mem_ldq_e_T_bits_uop_br_tag = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_br_tag : 3'h0; // @[lsu.scala:263:49, :912:37, :918:33] wire [3:0] _mem_ldq_e_T_bits_uop_ftq_idx = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_ftq_idx : 4'h0; // @[lsu.scala:263:49, :912:37, :918:33] wire _mem_ldq_e_T_bits_uop_edge_inst = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_edge_inst; // @[lsu.scala:263:49, :912:37, :918:33] wire [5:0] _mem_ldq_e_T_bits_uop_pc_lob = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_pc_lob : 6'h0; // @[lsu.scala:263:49, :912:37, :918:33] wire _mem_ldq_e_T_bits_uop_taken = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_taken; // @[lsu.scala:263:49, :912:37, :918:33] wire [19:0] _mem_ldq_e_T_bits_uop_imm_packed = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_imm_packed : 20'h0; // @[lsu.scala:263:49, :912:37, :918:33] wire [11:0] _mem_ldq_e_T_bits_uop_csr_addr = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_csr_addr : 12'h0; // @[lsu.scala:263:49, :912:37, :918:33] wire [4:0] _mem_ldq_e_T_bits_uop_rob_idx = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_rob_idx : 5'h0; // @[lsu.scala:263:49, :912:37, :918:33] wire [2:0] _mem_ldq_e_T_bits_uop_ldq_idx = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_ldq_idx : 3'h0; // @[lsu.scala:263:49, :912:37, :918:33] wire [2:0] _mem_ldq_e_T_bits_uop_stq_idx = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_stq_idx : 3'h0; // @[lsu.scala:263:49, :912:37, :918:33] wire [1:0] _mem_ldq_e_T_bits_uop_rxq_idx = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_rxq_idx : 2'h0; // @[lsu.scala:263:49, :912:37, :918:33] wire [5:0] _mem_ldq_e_T_bits_uop_pdst = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_pdst : 6'h0; // @[lsu.scala:263:49, :912:37, :918:33] wire [5:0] _mem_ldq_e_T_bits_uop_prs1 = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_prs1 : 6'h0; // @[lsu.scala:263:49, :912:37, :918:33] wire [5:0] _mem_ldq_e_T_bits_uop_prs2 = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_prs2 : 6'h0; // @[lsu.scala:263:49, :912:37, :918:33] wire [5:0] _mem_ldq_e_T_bits_uop_prs3 = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_prs3 : 6'h0; // @[lsu.scala:263:49, :912:37, :918:33] wire [3:0] _mem_ldq_e_T_bits_uop_ppred = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_ppred : 4'h0; // @[lsu.scala:263:49, :912:37, :918:33] wire _mem_ldq_e_T_bits_uop_prs1_busy = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_prs1_busy; // @[lsu.scala:263:49, :912:37, :918:33] wire _mem_ldq_e_T_bits_uop_prs2_busy = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_prs2_busy; // @[lsu.scala:263:49, :912:37, :918:33] wire _mem_ldq_e_T_bits_uop_prs3_busy = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_prs3_busy; // @[lsu.scala:263:49, :912:37, :918:33] wire _mem_ldq_e_T_bits_uop_ppred_busy = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_ppred_busy; // @[lsu.scala:263:49, :912:37, :918:33] wire [5:0] _mem_ldq_e_T_bits_uop_stale_pdst = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_stale_pdst : 6'h0; // @[lsu.scala:263:49, :912:37, :918:33] wire _mem_ldq_e_T_bits_uop_exception = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_exception; // @[lsu.scala:263:49, :912:37, :918:33] wire [63:0] _mem_ldq_e_T_bits_uop_exc_cause = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_exc_cause : 64'h0; // @[lsu.scala:263:49, :912:37, :918:33] wire _mem_ldq_e_T_bits_uop_bypassable = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_bypassable; // @[lsu.scala:263:49, :912:37, :918:33] wire [4:0] _mem_ldq_e_T_bits_uop_mem_cmd = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_mem_cmd : 5'h0; // @[lsu.scala:263:49, :912:37, :918:33] wire [1:0] _mem_ldq_e_T_bits_uop_mem_size = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_mem_size : 2'h0; // @[lsu.scala:263:49, :912:37, :918:33] wire _mem_ldq_e_T_bits_uop_mem_signed = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_mem_signed; // @[lsu.scala:263:49, :912:37, :918:33] wire _mem_ldq_e_T_bits_uop_is_fence = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_is_fence; // @[lsu.scala:263:49, :912:37, :918:33] wire _mem_ldq_e_T_bits_uop_is_fencei = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_is_fencei; // @[lsu.scala:263:49, :912:37, :918:33] wire _mem_ldq_e_T_bits_uop_is_amo = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_is_amo; // @[lsu.scala:263:49, :912:37, :918:33] wire _mem_ldq_e_T_bits_uop_uses_ldq = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_uses_ldq; // @[lsu.scala:263:49, :912:37, :918:33] wire _mem_ldq_e_T_bits_uop_uses_stq = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_uses_stq; // @[lsu.scala:263:49, :912:37, :918:33] wire _mem_ldq_e_T_bits_uop_is_sys_pc2epc = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_is_sys_pc2epc; // @[lsu.scala:263:49, :912:37, :918:33] wire _mem_ldq_e_T_bits_uop_is_unique = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_is_unique; // @[lsu.scala:263:49, :912:37, :918:33] wire _mem_ldq_e_T_bits_uop_flush_on_commit = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_flush_on_commit; // @[lsu.scala:263:49, :912:37, :918:33] wire _mem_ldq_e_T_bits_uop_ldst_is_rs1 = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_ldst_is_rs1; // @[lsu.scala:263:49, :912:37, :918:33] wire [5:0] _mem_ldq_e_T_bits_uop_ldst = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_ldst : 6'h0; // @[lsu.scala:263:49, :912:37, :918:33] wire [5:0] _mem_ldq_e_T_bits_uop_lrs1 = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_lrs1 : 6'h0; // @[lsu.scala:263:49, :912:37, :918:33] wire [5:0] _mem_ldq_e_T_bits_uop_lrs2 = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_lrs2 : 6'h0; // @[lsu.scala:263:49, :912:37, :918:33] wire [5:0] _mem_ldq_e_T_bits_uop_lrs3 = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_lrs3 : 6'h0; // @[lsu.scala:263:49, :912:37, :918:33] wire _mem_ldq_e_T_bits_uop_ldst_val = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_ldst_val; // @[lsu.scala:263:49, :912:37, :918:33] wire [1:0] _mem_ldq_e_T_bits_uop_dst_rtype = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_dst_rtype : 2'h0; // @[lsu.scala:263:49, :912:37, :918:33] wire [1:0] _mem_ldq_e_T_bits_uop_lrs1_rtype = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_lrs1_rtype : 2'h0; // @[lsu.scala:263:49, :912:37, :918:33] wire [1:0] _mem_ldq_e_T_bits_uop_lrs2_rtype = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_lrs2_rtype : 2'h0; // @[lsu.scala:263:49, :912:37, :918:33] wire _mem_ldq_e_T_bits_uop_frs3_en = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_frs3_en; // @[lsu.scala:263:49, :912:37, :918:33] wire _mem_ldq_e_T_bits_uop_fp_val = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_fp_val; // @[lsu.scala:263:49, :912:37, :918:33] wire _mem_ldq_e_T_bits_uop_fp_single = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_fp_single; // @[lsu.scala:263:49, :912:37, :918:33] wire _mem_ldq_e_T_bits_uop_xcpt_pf_if = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_xcpt_pf_if; // @[lsu.scala:263:49, :912:37, :918:33] wire _mem_ldq_e_T_bits_uop_xcpt_ae_if = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_xcpt_ae_if; // @[lsu.scala:263:49, :912:37, :918:33] wire _mem_ldq_e_T_bits_uop_xcpt_ma_if = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_xcpt_ma_if; // @[lsu.scala:263:49, :912:37, :918:33] wire _mem_ldq_e_T_bits_uop_bp_debug_if = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_bp_debug_if; // @[lsu.scala:263:49, :912:37, :918:33] wire _mem_ldq_e_T_bits_uop_bp_xcpt_if = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_bp_xcpt_if; // @[lsu.scala:263:49, :912:37, :918:33] wire [1:0] _mem_ldq_e_T_bits_uop_debug_fsrc = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_debug_fsrc : 2'h0; // @[lsu.scala:263:49, :912:37, :918:33] wire [1:0] _mem_ldq_e_T_bits_uop_debug_tsrc = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_debug_tsrc : 2'h0; // @[lsu.scala:263:49, :912:37, :918:33] wire _mem_ldq_e_T_bits_addr_valid = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_addr_valid; // @[lsu.scala:263:49, :912:37, :918:33] wire [39:0] _mem_ldq_e_T_bits_addr_bits = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_addr_bits : 40'h0; // @[lsu.scala:263:49, :912:37, :918:33] wire _mem_ldq_e_T_bits_addr_is_virtual = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_addr_is_virtual; // @[lsu.scala:263:49, :912:37, :918:33] wire _mem_ldq_e_T_bits_addr_is_uncacheable = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_addr_is_uncacheable; // @[lsu.scala:263:49, :912:37, :918:33] wire _mem_ldq_e_T_bits_executed = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_executed; // @[lsu.scala:263:49, :912:37, :918:33] wire _mem_ldq_e_T_bits_succeeded = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_succeeded; // @[lsu.scala:263:49, :912:37, :918:33] wire _mem_ldq_e_T_bits_order_fail = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_order_fail; // @[lsu.scala:263:49, :912:37, :918:33] wire _mem_ldq_e_T_bits_observed = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_observed; // @[lsu.scala:263:49, :912:37, :918:33] wire [7:0] _mem_ldq_e_T_bits_st_dep_mask = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_st_dep_mask : 8'h0; // @[lsu.scala:263:49, :912:37, :918:33] wire [2:0] _mem_ldq_e_T_bits_youngest_stq_idx = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_youngest_stq_idx : 3'h0; // @[lsu.scala:263:49, :912:37, :918:33] wire _mem_ldq_e_T_bits_forward_std_val = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_forward_std_val; // @[lsu.scala:263:49, :912:37, :918:33] wire [2:0] _mem_ldq_e_T_bits_forward_stq_idx = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_forward_stq_idx : 3'h0; // @[lsu.scala:263:49, :912:37, :918:33] wire [63:0] _mem_ldq_e_T_bits_debug_wb_data = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_debug_wb_data : 64'h0; // @[lsu.scala:263:49, :912:37, :918:33] wire _mem_ldq_e_T_1_valid = fired_load_retry_0 ? mem_ldq_retry_e_valid : _mem_ldq_e_T_valid; // @[lsu.scala:263:49, :913:37, :917:33, :918:33] wire [6:0] _mem_ldq_e_T_1_bits_uop_uopc = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_uopc : _mem_ldq_e_T_bits_uop_uopc; // @[lsu.scala:263:49, :913:37, :917:33, :918:33] wire [31:0] _mem_ldq_e_T_1_bits_uop_inst = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_inst : _mem_ldq_e_T_bits_uop_inst; // @[lsu.scala:263:49, :913:37, :917:33, :918:33] wire [31:0] _mem_ldq_e_T_1_bits_uop_debug_inst = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_debug_inst : _mem_ldq_e_T_bits_uop_debug_inst; // @[lsu.scala:263:49, :913:37, :917:33, :918:33] wire _mem_ldq_e_T_1_bits_uop_is_rvc = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_is_rvc : _mem_ldq_e_T_bits_uop_is_rvc; // @[lsu.scala:263:49, :913:37, :917:33, :918:33] wire [39:0] _mem_ldq_e_T_1_bits_uop_debug_pc = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_debug_pc : _mem_ldq_e_T_bits_uop_debug_pc; // @[lsu.scala:263:49, :913:37, :917:33, :918:33] wire [2:0] _mem_ldq_e_T_1_bits_uop_iq_type = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_iq_type : _mem_ldq_e_T_bits_uop_iq_type; // @[lsu.scala:263:49, :913:37, :917:33, :918:33] wire [9:0] _mem_ldq_e_T_1_bits_uop_fu_code = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_fu_code : _mem_ldq_e_T_bits_uop_fu_code; // @[lsu.scala:263:49, :913:37, :917:33, :918:33] wire [3:0] _mem_ldq_e_T_1_bits_uop_ctrl_br_type = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_ctrl_br_type : _mem_ldq_e_T_bits_uop_ctrl_br_type; // @[lsu.scala:263:49, :913:37, :917:33, :918:33] wire [1:0] _mem_ldq_e_T_1_bits_uop_ctrl_op1_sel = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_ctrl_op1_sel : _mem_ldq_e_T_bits_uop_ctrl_op1_sel; // @[lsu.scala:263:49, :913:37, :917:33, :918:33] wire [2:0] _mem_ldq_e_T_1_bits_uop_ctrl_op2_sel = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_ctrl_op2_sel : _mem_ldq_e_T_bits_uop_ctrl_op2_sel; // @[lsu.scala:263:49, :913:37, :917:33, :918:33] wire [2:0] _mem_ldq_e_T_1_bits_uop_ctrl_imm_sel = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_ctrl_imm_sel : _mem_ldq_e_T_bits_uop_ctrl_imm_sel; // @[lsu.scala:263:49, :913:37, :917:33, :918:33] wire [4:0] _mem_ldq_e_T_1_bits_uop_ctrl_op_fcn = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_ctrl_op_fcn : _mem_ldq_e_T_bits_uop_ctrl_op_fcn; // @[lsu.scala:263:49, :913:37, :917:33, :918:33] wire _mem_ldq_e_T_1_bits_uop_ctrl_fcn_dw = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_ctrl_fcn_dw : _mem_ldq_e_T_bits_uop_ctrl_fcn_dw; // @[lsu.scala:263:49, :913:37, :917:33, :918:33] wire [2:0] _mem_ldq_e_T_1_bits_uop_ctrl_csr_cmd = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_ctrl_csr_cmd : _mem_ldq_e_T_bits_uop_ctrl_csr_cmd; // @[lsu.scala:263:49, :913:37, :917:33, :918:33] wire _mem_ldq_e_T_1_bits_uop_ctrl_is_load = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_ctrl_is_load : _mem_ldq_e_T_bits_uop_ctrl_is_load; // @[lsu.scala:263:49, :913:37, :917:33, :918:33] wire _mem_ldq_e_T_1_bits_uop_ctrl_is_sta = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_ctrl_is_sta : _mem_ldq_e_T_bits_uop_ctrl_is_sta; // @[lsu.scala:263:49, :913:37, :917:33, :918:33] wire _mem_ldq_e_T_1_bits_uop_ctrl_is_std = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_ctrl_is_std : _mem_ldq_e_T_bits_uop_ctrl_is_std; // @[lsu.scala:263:49, :913:37, :917:33, :918:33] wire [1:0] _mem_ldq_e_T_1_bits_uop_iw_state = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_iw_state : _mem_ldq_e_T_bits_uop_iw_state; // @[lsu.scala:263:49, :913:37, :917:33, :918:33] wire _mem_ldq_e_T_1_bits_uop_iw_p1_poisoned = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_iw_p1_poisoned : _mem_ldq_e_T_bits_uop_iw_p1_poisoned; // @[lsu.scala:263:49, :913:37, :917:33, :918:33] wire _mem_ldq_e_T_1_bits_uop_iw_p2_poisoned = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_iw_p2_poisoned : _mem_ldq_e_T_bits_uop_iw_p2_poisoned; // @[lsu.scala:263:49, :913:37, :917:33, :918:33] wire _mem_ldq_e_T_1_bits_uop_is_br = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_is_br : _mem_ldq_e_T_bits_uop_is_br; // @[lsu.scala:263:49, :913:37, :917:33, :918:33] wire _mem_ldq_e_T_1_bits_uop_is_jalr = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_is_jalr : _mem_ldq_e_T_bits_uop_is_jalr; // @[lsu.scala:263:49, :913:37, :917:33, :918:33] wire _mem_ldq_e_T_1_bits_uop_is_jal = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_is_jal : _mem_ldq_e_T_bits_uop_is_jal; // @[lsu.scala:263:49, :913:37, :917:33, :918:33] wire _mem_ldq_e_T_1_bits_uop_is_sfb = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_is_sfb : _mem_ldq_e_T_bits_uop_is_sfb; // @[lsu.scala:263:49, :913:37, :917:33, :918:33] wire [7:0] _mem_ldq_e_T_1_bits_uop_br_mask = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_br_mask : _mem_ldq_e_T_bits_uop_br_mask; // @[lsu.scala:263:49, :913:37, :917:33, :918:33] wire [2:0] _mem_ldq_e_T_1_bits_uop_br_tag = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_br_tag : _mem_ldq_e_T_bits_uop_br_tag; // @[lsu.scala:263:49, :913:37, :917:33, :918:33] wire [3:0] _mem_ldq_e_T_1_bits_uop_ftq_idx = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_ftq_idx : _mem_ldq_e_T_bits_uop_ftq_idx; // @[lsu.scala:263:49, :913:37, :917:33, :918:33] wire _mem_ldq_e_T_1_bits_uop_edge_inst = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_edge_inst : _mem_ldq_e_T_bits_uop_edge_inst; // @[lsu.scala:263:49, :913:37, :917:33, :918:33] wire [5:0] _mem_ldq_e_T_1_bits_uop_pc_lob = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_pc_lob : _mem_ldq_e_T_bits_uop_pc_lob; // @[lsu.scala:263:49, :913:37, :917:33, :918:33] wire _mem_ldq_e_T_1_bits_uop_taken = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_taken : _mem_ldq_e_T_bits_uop_taken; // @[lsu.scala:263:49, :913:37, :917:33, :918:33] wire [19:0] _mem_ldq_e_T_1_bits_uop_imm_packed = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_imm_packed : _mem_ldq_e_T_bits_uop_imm_packed; // @[lsu.scala:263:49, :913:37, :917:33, :918:33] wire [11:0] _mem_ldq_e_T_1_bits_uop_csr_addr = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_csr_addr : _mem_ldq_e_T_bits_uop_csr_addr; // @[lsu.scala:263:49, :913:37, :917:33, :918:33] wire [4:0] _mem_ldq_e_T_1_bits_uop_rob_idx = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_rob_idx : _mem_ldq_e_T_bits_uop_rob_idx; // @[lsu.scala:263:49, :913:37, :917:33, :918:33] wire [2:0] _mem_ldq_e_T_1_bits_uop_ldq_idx = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_ldq_idx : _mem_ldq_e_T_bits_uop_ldq_idx; // @[lsu.scala:263:49, :913:37, :917:33, :918:33] wire [2:0] _mem_ldq_e_T_1_bits_uop_stq_idx = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_stq_idx : _mem_ldq_e_T_bits_uop_stq_idx; // @[lsu.scala:263:49, :913:37, :917:33, :918:33] wire [1:0] _mem_ldq_e_T_1_bits_uop_rxq_idx = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_rxq_idx : _mem_ldq_e_T_bits_uop_rxq_idx; // @[lsu.scala:263:49, :913:37, :917:33, :918:33] wire [5:0] _mem_ldq_e_T_1_bits_uop_pdst = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_pdst : _mem_ldq_e_T_bits_uop_pdst; // @[lsu.scala:263:49, :913:37, :917:33, :918:33] wire [5:0] _mem_ldq_e_T_1_bits_uop_prs1 = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_prs1 : _mem_ldq_e_T_bits_uop_prs1; // @[lsu.scala:263:49, :913:37, :917:33, :918:33] wire [5:0] _mem_ldq_e_T_1_bits_uop_prs2 = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_prs2 : _mem_ldq_e_T_bits_uop_prs2; // @[lsu.scala:263:49, :913:37, :917:33, :918:33] wire [5:0] _mem_ldq_e_T_1_bits_uop_prs3 = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_prs3 : _mem_ldq_e_T_bits_uop_prs3; // @[lsu.scala:263:49, :913:37, :917:33, :918:33] wire [3:0] _mem_ldq_e_T_1_bits_uop_ppred = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_ppred : _mem_ldq_e_T_bits_uop_ppred; // @[lsu.scala:263:49, :913:37, :917:33, :918:33] wire _mem_ldq_e_T_1_bits_uop_prs1_busy = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_prs1_busy : _mem_ldq_e_T_bits_uop_prs1_busy; // @[lsu.scala:263:49, :913:37, :917:33, :918:33] wire _mem_ldq_e_T_1_bits_uop_prs2_busy = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_prs2_busy : _mem_ldq_e_T_bits_uop_prs2_busy; // @[lsu.scala:263:49, :913:37, :917:33, :918:33] wire _mem_ldq_e_T_1_bits_uop_prs3_busy = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_prs3_busy : _mem_ldq_e_T_bits_uop_prs3_busy; // @[lsu.scala:263:49, :913:37, :917:33, :918:33] wire _mem_ldq_e_T_1_bits_uop_ppred_busy = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_ppred_busy : _mem_ldq_e_T_bits_uop_ppred_busy; // @[lsu.scala:263:49, :913:37, :917:33, :918:33] wire [5:0] _mem_ldq_e_T_1_bits_uop_stale_pdst = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_stale_pdst : _mem_ldq_e_T_bits_uop_stale_pdst; // @[lsu.scala:263:49, :913:37, :917:33, :918:33] wire _mem_ldq_e_T_1_bits_uop_exception = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_exception : _mem_ldq_e_T_bits_uop_exception; // @[lsu.scala:263:49, :913:37, :917:33, :918:33] wire [63:0] _mem_ldq_e_T_1_bits_uop_exc_cause = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_exc_cause : _mem_ldq_e_T_bits_uop_exc_cause; // @[lsu.scala:263:49, :913:37, :917:33, :918:33] wire _mem_ldq_e_T_1_bits_uop_bypassable = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_bypassable : _mem_ldq_e_T_bits_uop_bypassable; // @[lsu.scala:263:49, :913:37, :917:33, :918:33] wire [4:0] _mem_ldq_e_T_1_bits_uop_mem_cmd = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_mem_cmd : _mem_ldq_e_T_bits_uop_mem_cmd; // @[lsu.scala:263:49, :913:37, :917:33, :918:33] wire [1:0] _mem_ldq_e_T_1_bits_uop_mem_size = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_mem_size : _mem_ldq_e_T_bits_uop_mem_size; // @[lsu.scala:263:49, :913:37, :917:33, :918:33] wire _mem_ldq_e_T_1_bits_uop_mem_signed = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_mem_signed : _mem_ldq_e_T_bits_uop_mem_signed; // @[lsu.scala:263:49, :913:37, :917:33, :918:33] wire _mem_ldq_e_T_1_bits_uop_is_fence = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_is_fence : _mem_ldq_e_T_bits_uop_is_fence; // @[lsu.scala:263:49, :913:37, :917:33, :918:33] wire _mem_ldq_e_T_1_bits_uop_is_fencei = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_is_fencei : _mem_ldq_e_T_bits_uop_is_fencei; // @[lsu.scala:263:49, :913:37, :917:33, :918:33] wire _mem_ldq_e_T_1_bits_uop_is_amo = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_is_amo : _mem_ldq_e_T_bits_uop_is_amo; // @[lsu.scala:263:49, :913:37, :917:33, :918:33] wire _mem_ldq_e_T_1_bits_uop_uses_ldq = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_uses_ldq : _mem_ldq_e_T_bits_uop_uses_ldq; // @[lsu.scala:263:49, :913:37, :917:33, :918:33] wire _mem_ldq_e_T_1_bits_uop_uses_stq = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_uses_stq : _mem_ldq_e_T_bits_uop_uses_stq; // @[lsu.scala:263:49, :913:37, :917:33, :918:33] wire _mem_ldq_e_T_1_bits_uop_is_sys_pc2epc = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_is_sys_pc2epc : _mem_ldq_e_T_bits_uop_is_sys_pc2epc; // @[lsu.scala:263:49, :913:37, :917:33, :918:33] wire _mem_ldq_e_T_1_bits_uop_is_unique = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_is_unique : _mem_ldq_e_T_bits_uop_is_unique; // @[lsu.scala:263:49, :913:37, :917:33, :918:33] wire _mem_ldq_e_T_1_bits_uop_flush_on_commit = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_flush_on_commit : _mem_ldq_e_T_bits_uop_flush_on_commit; // @[lsu.scala:263:49, :913:37, :917:33, :918:33] wire _mem_ldq_e_T_1_bits_uop_ldst_is_rs1 = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_ldst_is_rs1 : _mem_ldq_e_T_bits_uop_ldst_is_rs1; // @[lsu.scala:263:49, :913:37, :917:33, :918:33] wire [5:0] _mem_ldq_e_T_1_bits_uop_ldst = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_ldst : _mem_ldq_e_T_bits_uop_ldst; // @[lsu.scala:263:49, :913:37, :917:33, :918:33] wire [5:0] _mem_ldq_e_T_1_bits_uop_lrs1 = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_lrs1 : _mem_ldq_e_T_bits_uop_lrs1; // @[lsu.scala:263:49, :913:37, :917:33, :918:33] wire [5:0] _mem_ldq_e_T_1_bits_uop_lrs2 = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_lrs2 : _mem_ldq_e_T_bits_uop_lrs2; // @[lsu.scala:263:49, :913:37, :917:33, :918:33] wire [5:0] _mem_ldq_e_T_1_bits_uop_lrs3 = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_lrs3 : _mem_ldq_e_T_bits_uop_lrs3; // @[lsu.scala:263:49, :913:37, :917:33, :918:33] wire _mem_ldq_e_T_1_bits_uop_ldst_val = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_ldst_val : _mem_ldq_e_T_bits_uop_ldst_val; // @[lsu.scala:263:49, :913:37, :917:33, :918:33] wire [1:0] _mem_ldq_e_T_1_bits_uop_dst_rtype = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_dst_rtype : _mem_ldq_e_T_bits_uop_dst_rtype; // @[lsu.scala:263:49, :913:37, :917:33, :918:33] wire [1:0] _mem_ldq_e_T_1_bits_uop_lrs1_rtype = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_lrs1_rtype : _mem_ldq_e_T_bits_uop_lrs1_rtype; // @[lsu.scala:263:49, :913:37, :917:33, :918:33] wire [1:0] _mem_ldq_e_T_1_bits_uop_lrs2_rtype = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_lrs2_rtype : _mem_ldq_e_T_bits_uop_lrs2_rtype; // @[lsu.scala:263:49, :913:37, :917:33, :918:33] wire _mem_ldq_e_T_1_bits_uop_frs3_en = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_frs3_en : _mem_ldq_e_T_bits_uop_frs3_en; // @[lsu.scala:263:49, :913:37, :917:33, :918:33] wire _mem_ldq_e_T_1_bits_uop_fp_val = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_fp_val : _mem_ldq_e_T_bits_uop_fp_val; // @[lsu.scala:263:49, :913:37, :917:33, :918:33] wire _mem_ldq_e_T_1_bits_uop_fp_single = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_fp_single : _mem_ldq_e_T_bits_uop_fp_single; // @[lsu.scala:263:49, :913:37, :917:33, :918:33] wire _mem_ldq_e_T_1_bits_uop_xcpt_pf_if = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_xcpt_pf_if : _mem_ldq_e_T_bits_uop_xcpt_pf_if; // @[lsu.scala:263:49, :913:37, :917:33, :918:33] wire _mem_ldq_e_T_1_bits_uop_xcpt_ae_if = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_xcpt_ae_if : _mem_ldq_e_T_bits_uop_xcpt_ae_if; // @[lsu.scala:263:49, :913:37, :917:33, :918:33] wire _mem_ldq_e_T_1_bits_uop_xcpt_ma_if = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_xcpt_ma_if : _mem_ldq_e_T_bits_uop_xcpt_ma_if; // @[lsu.scala:263:49, :913:37, :917:33, :918:33] wire _mem_ldq_e_T_1_bits_uop_bp_debug_if = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_bp_debug_if : _mem_ldq_e_T_bits_uop_bp_debug_if; // @[lsu.scala:263:49, :913:37, :917:33, :918:33] wire _mem_ldq_e_T_1_bits_uop_bp_xcpt_if = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_bp_xcpt_if : _mem_ldq_e_T_bits_uop_bp_xcpt_if; // @[lsu.scala:263:49, :913:37, :917:33, :918:33] wire [1:0] _mem_ldq_e_T_1_bits_uop_debug_fsrc = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_debug_fsrc : _mem_ldq_e_T_bits_uop_debug_fsrc; // @[lsu.scala:263:49, :913:37, :917:33, :918:33] wire [1:0] _mem_ldq_e_T_1_bits_uop_debug_tsrc = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_debug_tsrc : _mem_ldq_e_T_bits_uop_debug_tsrc; // @[lsu.scala:263:49, :913:37, :917:33, :918:33] wire _mem_ldq_e_T_1_bits_addr_valid = fired_load_retry_0 ? mem_ldq_retry_e_bits_addr_valid : _mem_ldq_e_T_bits_addr_valid; // @[lsu.scala:263:49, :913:37, :917:33, :918:33] wire [39:0] _mem_ldq_e_T_1_bits_addr_bits = fired_load_retry_0 ? mem_ldq_retry_e_bits_addr_bits : _mem_ldq_e_T_bits_addr_bits; // @[lsu.scala:263:49, :913:37, :917:33, :918:33] wire _mem_ldq_e_T_1_bits_addr_is_virtual = fired_load_retry_0 ? mem_ldq_retry_e_bits_addr_is_virtual : _mem_ldq_e_T_bits_addr_is_virtual; // @[lsu.scala:263:49, :913:37, :917:33, :918:33] wire _mem_ldq_e_T_1_bits_addr_is_uncacheable = fired_load_retry_0 ? mem_ldq_retry_e_bits_addr_is_uncacheable : _mem_ldq_e_T_bits_addr_is_uncacheable; // @[lsu.scala:263:49, :913:37, :917:33, :918:33] wire _mem_ldq_e_T_1_bits_executed = fired_load_retry_0 ? mem_ldq_retry_e_bits_executed : _mem_ldq_e_T_bits_executed; // @[lsu.scala:263:49, :913:37, :917:33, :918:33] wire _mem_ldq_e_T_1_bits_succeeded = fired_load_retry_0 ? mem_ldq_retry_e_bits_succeeded : _mem_ldq_e_T_bits_succeeded; // @[lsu.scala:263:49, :913:37, :917:33, :918:33] wire _mem_ldq_e_T_1_bits_order_fail = fired_load_retry_0 ? mem_ldq_retry_e_bits_order_fail : _mem_ldq_e_T_bits_order_fail; // @[lsu.scala:263:49, :913:37, :917:33, :918:33] wire _mem_ldq_e_T_1_bits_observed = fired_load_retry_0 ? mem_ldq_retry_e_bits_observed : _mem_ldq_e_T_bits_observed; // @[lsu.scala:263:49, :913:37, :917:33, :918:33] wire [7:0] _mem_ldq_e_T_1_bits_st_dep_mask = fired_load_retry_0 ? mem_ldq_retry_e_bits_st_dep_mask : _mem_ldq_e_T_bits_st_dep_mask; // @[lsu.scala:263:49, :913:37, :917:33, :918:33] wire [2:0] _mem_ldq_e_T_1_bits_youngest_stq_idx = fired_load_retry_0 ? mem_ldq_retry_e_bits_youngest_stq_idx : _mem_ldq_e_T_bits_youngest_stq_idx; // @[lsu.scala:263:49, :913:37, :917:33, :918:33] wire _mem_ldq_e_T_1_bits_forward_std_val = fired_load_retry_0 ? mem_ldq_retry_e_bits_forward_std_val : _mem_ldq_e_T_bits_forward_std_val; // @[lsu.scala:263:49, :913:37, :917:33, :918:33] wire [2:0] _mem_ldq_e_T_1_bits_forward_stq_idx = fired_load_retry_0 ? mem_ldq_retry_e_bits_forward_stq_idx : _mem_ldq_e_T_bits_forward_stq_idx; // @[lsu.scala:263:49, :913:37, :917:33, :918:33] wire [63:0] _mem_ldq_e_T_1_bits_debug_wb_data = fired_load_retry_0 ? mem_ldq_retry_e_bits_debug_wb_data : _mem_ldq_e_T_bits_debug_wb_data; // @[lsu.scala:263:49, :913:37, :917:33, :918:33] wire _mem_ldq_e_T_2_valid = fired_load_incoming_0 ? mem_ldq_incoming_e_0_valid : _mem_ldq_e_T_1_valid; // @[lsu.scala:263:49, :910:37, :916:33, :917:33] wire [6:0] _mem_ldq_e_T_2_bits_uop_uopc = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_uop_uopc : _mem_ldq_e_T_1_bits_uop_uopc; // @[lsu.scala:263:49, :910:37, :916:33, :917:33] wire [31:0] _mem_ldq_e_T_2_bits_uop_inst = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_uop_inst : _mem_ldq_e_T_1_bits_uop_inst; // @[lsu.scala:263:49, :910:37, :916:33, :917:33] wire [31:0] _mem_ldq_e_T_2_bits_uop_debug_inst = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_uop_debug_inst : _mem_ldq_e_T_1_bits_uop_debug_inst; // @[lsu.scala:263:49, :910:37, :916:33, :917:33] wire _mem_ldq_e_T_2_bits_uop_is_rvc = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_uop_is_rvc : _mem_ldq_e_T_1_bits_uop_is_rvc; // @[lsu.scala:263:49, :910:37, :916:33, :917:33] wire [39:0] _mem_ldq_e_T_2_bits_uop_debug_pc = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_uop_debug_pc : _mem_ldq_e_T_1_bits_uop_debug_pc; // @[lsu.scala:263:49, :910:37, :916:33, :917:33] wire [2:0] _mem_ldq_e_T_2_bits_uop_iq_type = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_uop_iq_type : _mem_ldq_e_T_1_bits_uop_iq_type; // @[lsu.scala:263:49, :910:37, :916:33, :917:33] wire [9:0] _mem_ldq_e_T_2_bits_uop_fu_code = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_uop_fu_code : _mem_ldq_e_T_1_bits_uop_fu_code; // @[lsu.scala:263:49, :910:37, :916:33, :917:33] wire [3:0] _mem_ldq_e_T_2_bits_uop_ctrl_br_type = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_uop_ctrl_br_type : _mem_ldq_e_T_1_bits_uop_ctrl_br_type; // @[lsu.scala:263:49, :910:37, :916:33, :917:33] wire [1:0] _mem_ldq_e_T_2_bits_uop_ctrl_op1_sel = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_uop_ctrl_op1_sel : _mem_ldq_e_T_1_bits_uop_ctrl_op1_sel; // @[lsu.scala:263:49, :910:37, :916:33, :917:33] wire [2:0] _mem_ldq_e_T_2_bits_uop_ctrl_op2_sel = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_uop_ctrl_op2_sel : _mem_ldq_e_T_1_bits_uop_ctrl_op2_sel; // @[lsu.scala:263:49, :910:37, :916:33, :917:33] wire [2:0] _mem_ldq_e_T_2_bits_uop_ctrl_imm_sel = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_uop_ctrl_imm_sel : _mem_ldq_e_T_1_bits_uop_ctrl_imm_sel; // @[lsu.scala:263:49, :910:37, :916:33, :917:33] wire [4:0] _mem_ldq_e_T_2_bits_uop_ctrl_op_fcn = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_uop_ctrl_op_fcn : _mem_ldq_e_T_1_bits_uop_ctrl_op_fcn; // @[lsu.scala:263:49, :910:37, :916:33, :917:33] wire _mem_ldq_e_T_2_bits_uop_ctrl_fcn_dw = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_uop_ctrl_fcn_dw : _mem_ldq_e_T_1_bits_uop_ctrl_fcn_dw; // @[lsu.scala:263:49, :910:37, :916:33, :917:33] wire [2:0] _mem_ldq_e_T_2_bits_uop_ctrl_csr_cmd = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_uop_ctrl_csr_cmd : _mem_ldq_e_T_1_bits_uop_ctrl_csr_cmd; // @[lsu.scala:263:49, :910:37, :916:33, :917:33] wire _mem_ldq_e_T_2_bits_uop_ctrl_is_load = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_uop_ctrl_is_load : _mem_ldq_e_T_1_bits_uop_ctrl_is_load; // @[lsu.scala:263:49, :910:37, :916:33, :917:33] wire _mem_ldq_e_T_2_bits_uop_ctrl_is_sta = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_uop_ctrl_is_sta : _mem_ldq_e_T_1_bits_uop_ctrl_is_sta; // @[lsu.scala:263:49, :910:37, :916:33, :917:33] wire _mem_ldq_e_T_2_bits_uop_ctrl_is_std = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_uop_ctrl_is_std : _mem_ldq_e_T_1_bits_uop_ctrl_is_std; // @[lsu.scala:263:49, :910:37, :916:33, :917:33] wire [1:0] _mem_ldq_e_T_2_bits_uop_iw_state = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_uop_iw_state : _mem_ldq_e_T_1_bits_uop_iw_state; // @[lsu.scala:263:49, :910:37, :916:33, :917:33] wire _mem_ldq_e_T_2_bits_uop_iw_p1_poisoned = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_uop_iw_p1_poisoned : _mem_ldq_e_T_1_bits_uop_iw_p1_poisoned; // @[lsu.scala:263:49, :910:37, :916:33, :917:33] wire _mem_ldq_e_T_2_bits_uop_iw_p2_poisoned = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_uop_iw_p2_poisoned : _mem_ldq_e_T_1_bits_uop_iw_p2_poisoned; // @[lsu.scala:263:49, :910:37, :916:33, :917:33] wire _mem_ldq_e_T_2_bits_uop_is_br = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_uop_is_br : _mem_ldq_e_T_1_bits_uop_is_br; // @[lsu.scala:263:49, :910:37, :916:33, :917:33] wire _mem_ldq_e_T_2_bits_uop_is_jalr = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_uop_is_jalr : _mem_ldq_e_T_1_bits_uop_is_jalr; // @[lsu.scala:263:49, :910:37, :916:33, :917:33] wire _mem_ldq_e_T_2_bits_uop_is_jal = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_uop_is_jal : _mem_ldq_e_T_1_bits_uop_is_jal; // @[lsu.scala:263:49, :910:37, :916:33, :917:33] wire _mem_ldq_e_T_2_bits_uop_is_sfb = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_uop_is_sfb : _mem_ldq_e_T_1_bits_uop_is_sfb; // @[lsu.scala:263:49, :910:37, :916:33, :917:33] wire [7:0] _mem_ldq_e_T_2_bits_uop_br_mask = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_uop_br_mask : _mem_ldq_e_T_1_bits_uop_br_mask; // @[lsu.scala:263:49, :910:37, :916:33, :917:33] wire [2:0] _mem_ldq_e_T_2_bits_uop_br_tag = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_uop_br_tag : _mem_ldq_e_T_1_bits_uop_br_tag; // @[lsu.scala:263:49, :910:37, :916:33, :917:33] wire [3:0] _mem_ldq_e_T_2_bits_uop_ftq_idx = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_uop_ftq_idx : _mem_ldq_e_T_1_bits_uop_ftq_idx; // @[lsu.scala:263:49, :910:37, :916:33, :917:33] wire _mem_ldq_e_T_2_bits_uop_edge_inst = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_uop_edge_inst : _mem_ldq_e_T_1_bits_uop_edge_inst; // @[lsu.scala:263:49, :910:37, :916:33, :917:33] wire [5:0] _mem_ldq_e_T_2_bits_uop_pc_lob = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_uop_pc_lob : _mem_ldq_e_T_1_bits_uop_pc_lob; // @[lsu.scala:263:49, :910:37, :916:33, :917:33] wire _mem_ldq_e_T_2_bits_uop_taken = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_uop_taken : _mem_ldq_e_T_1_bits_uop_taken; // @[lsu.scala:263:49, :910:37, :916:33, :917:33] wire [19:0] _mem_ldq_e_T_2_bits_uop_imm_packed = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_uop_imm_packed : _mem_ldq_e_T_1_bits_uop_imm_packed; // @[lsu.scala:263:49, :910:37, :916:33, :917:33] wire [11:0] _mem_ldq_e_T_2_bits_uop_csr_addr = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_uop_csr_addr : _mem_ldq_e_T_1_bits_uop_csr_addr; // @[lsu.scala:263:49, :910:37, :916:33, :917:33] wire [4:0] _mem_ldq_e_T_2_bits_uop_rob_idx = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_uop_rob_idx : _mem_ldq_e_T_1_bits_uop_rob_idx; // @[lsu.scala:263:49, :910:37, :916:33, :917:33] wire [2:0] _mem_ldq_e_T_2_bits_uop_ldq_idx = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_uop_ldq_idx : _mem_ldq_e_T_1_bits_uop_ldq_idx; // @[lsu.scala:263:49, :910:37, :916:33, :917:33] wire [2:0] _mem_ldq_e_T_2_bits_uop_stq_idx = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_uop_stq_idx : _mem_ldq_e_T_1_bits_uop_stq_idx; // @[lsu.scala:263:49, :910:37, :916:33, :917:33] wire [1:0] _mem_ldq_e_T_2_bits_uop_rxq_idx = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_uop_rxq_idx : _mem_ldq_e_T_1_bits_uop_rxq_idx; // @[lsu.scala:263:49, :910:37, :916:33, :917:33] wire [5:0] _mem_ldq_e_T_2_bits_uop_pdst = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_uop_pdst : _mem_ldq_e_T_1_bits_uop_pdst; // @[lsu.scala:263:49, :910:37, :916:33, :917:33] wire [5:0] _mem_ldq_e_T_2_bits_uop_prs1 = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_uop_prs1 : _mem_ldq_e_T_1_bits_uop_prs1; // @[lsu.scala:263:49, :910:37, :916:33, :917:33] wire [5:0] _mem_ldq_e_T_2_bits_uop_prs2 = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_uop_prs2 : _mem_ldq_e_T_1_bits_uop_prs2; // @[lsu.scala:263:49, :910:37, :916:33, :917:33] wire [5:0] _mem_ldq_e_T_2_bits_uop_prs3 = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_uop_prs3 : _mem_ldq_e_T_1_bits_uop_prs3; // @[lsu.scala:263:49, :910:37, :916:33, :917:33] wire [3:0] _mem_ldq_e_T_2_bits_uop_ppred = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_uop_ppred : _mem_ldq_e_T_1_bits_uop_ppred; // @[lsu.scala:263:49, :910:37, :916:33, :917:33] wire _mem_ldq_e_T_2_bits_uop_prs1_busy = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_uop_prs1_busy : _mem_ldq_e_T_1_bits_uop_prs1_busy; // @[lsu.scala:263:49, :910:37, :916:33, :917:33] wire _mem_ldq_e_T_2_bits_uop_prs2_busy = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_uop_prs2_busy : _mem_ldq_e_T_1_bits_uop_prs2_busy; // @[lsu.scala:263:49, :910:37, :916:33, :917:33] wire _mem_ldq_e_T_2_bits_uop_prs3_busy = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_uop_prs3_busy : _mem_ldq_e_T_1_bits_uop_prs3_busy; // @[lsu.scala:263:49, :910:37, :916:33, :917:33] wire _mem_ldq_e_T_2_bits_uop_ppred_busy = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_uop_ppred_busy : _mem_ldq_e_T_1_bits_uop_ppred_busy; // @[lsu.scala:263:49, :910:37, :916:33, :917:33] wire [5:0] _mem_ldq_e_T_2_bits_uop_stale_pdst = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_uop_stale_pdst : _mem_ldq_e_T_1_bits_uop_stale_pdst; // @[lsu.scala:263:49, :910:37, :916:33, :917:33] wire _mem_ldq_e_T_2_bits_uop_exception = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_uop_exception : _mem_ldq_e_T_1_bits_uop_exception; // @[lsu.scala:263:49, :910:37, :916:33, :917:33] wire [63:0] _mem_ldq_e_T_2_bits_uop_exc_cause = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_uop_exc_cause : _mem_ldq_e_T_1_bits_uop_exc_cause; // @[lsu.scala:263:49, :910:37, :916:33, :917:33] wire _mem_ldq_e_T_2_bits_uop_bypassable = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_uop_bypassable : _mem_ldq_e_T_1_bits_uop_bypassable; // @[lsu.scala:263:49, :910:37, :916:33, :917:33] wire [4:0] _mem_ldq_e_T_2_bits_uop_mem_cmd = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_uop_mem_cmd : _mem_ldq_e_T_1_bits_uop_mem_cmd; // @[lsu.scala:263:49, :910:37, :916:33, :917:33] wire [1:0] _mem_ldq_e_T_2_bits_uop_mem_size = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_uop_mem_size : _mem_ldq_e_T_1_bits_uop_mem_size; // @[lsu.scala:263:49, :910:37, :916:33, :917:33] wire _mem_ldq_e_T_2_bits_uop_mem_signed = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_uop_mem_signed : _mem_ldq_e_T_1_bits_uop_mem_signed; // @[lsu.scala:263:49, :910:37, :916:33, :917:33] wire _mem_ldq_e_T_2_bits_uop_is_fence = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_uop_is_fence : _mem_ldq_e_T_1_bits_uop_is_fence; // @[lsu.scala:263:49, :910:37, :916:33, :917:33] wire _mem_ldq_e_T_2_bits_uop_is_fencei = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_uop_is_fencei : _mem_ldq_e_T_1_bits_uop_is_fencei; // @[lsu.scala:263:49, :910:37, :916:33, :917:33] wire _mem_ldq_e_T_2_bits_uop_is_amo = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_uop_is_amo : _mem_ldq_e_T_1_bits_uop_is_amo; // @[lsu.scala:263:49, :910:37, :916:33, :917:33] wire _mem_ldq_e_T_2_bits_uop_uses_ldq = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_uop_uses_ldq : _mem_ldq_e_T_1_bits_uop_uses_ldq; // @[lsu.scala:263:49, :910:37, :916:33, :917:33] wire _mem_ldq_e_T_2_bits_uop_uses_stq = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_uop_uses_stq : _mem_ldq_e_T_1_bits_uop_uses_stq; // @[lsu.scala:263:49, :910:37, :916:33, :917:33] wire _mem_ldq_e_T_2_bits_uop_is_sys_pc2epc = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_uop_is_sys_pc2epc : _mem_ldq_e_T_1_bits_uop_is_sys_pc2epc; // @[lsu.scala:263:49, :910:37, :916:33, :917:33] wire _mem_ldq_e_T_2_bits_uop_is_unique = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_uop_is_unique : _mem_ldq_e_T_1_bits_uop_is_unique; // @[lsu.scala:263:49, :910:37, :916:33, :917:33] wire _mem_ldq_e_T_2_bits_uop_flush_on_commit = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_uop_flush_on_commit : _mem_ldq_e_T_1_bits_uop_flush_on_commit; // @[lsu.scala:263:49, :910:37, :916:33, :917:33] wire _mem_ldq_e_T_2_bits_uop_ldst_is_rs1 = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_uop_ldst_is_rs1 : _mem_ldq_e_T_1_bits_uop_ldst_is_rs1; // @[lsu.scala:263:49, :910:37, :916:33, :917:33] wire [5:0] _mem_ldq_e_T_2_bits_uop_ldst = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_uop_ldst : _mem_ldq_e_T_1_bits_uop_ldst; // @[lsu.scala:263:49, :910:37, :916:33, :917:33] wire [5:0] _mem_ldq_e_T_2_bits_uop_lrs1 = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_uop_lrs1 : _mem_ldq_e_T_1_bits_uop_lrs1; // @[lsu.scala:263:49, :910:37, :916:33, :917:33] wire [5:0] _mem_ldq_e_T_2_bits_uop_lrs2 = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_uop_lrs2 : _mem_ldq_e_T_1_bits_uop_lrs2; // @[lsu.scala:263:49, :910:37, :916:33, :917:33] wire [5:0] _mem_ldq_e_T_2_bits_uop_lrs3 = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_uop_lrs3 : _mem_ldq_e_T_1_bits_uop_lrs3; // @[lsu.scala:263:49, :910:37, :916:33, :917:33] wire _mem_ldq_e_T_2_bits_uop_ldst_val = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_uop_ldst_val : _mem_ldq_e_T_1_bits_uop_ldst_val; // @[lsu.scala:263:49, :910:37, :916:33, :917:33] wire [1:0] _mem_ldq_e_T_2_bits_uop_dst_rtype = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_uop_dst_rtype : _mem_ldq_e_T_1_bits_uop_dst_rtype; // @[lsu.scala:263:49, :910:37, :916:33, :917:33] wire [1:0] _mem_ldq_e_T_2_bits_uop_lrs1_rtype = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_uop_lrs1_rtype : _mem_ldq_e_T_1_bits_uop_lrs1_rtype; // @[lsu.scala:263:49, :910:37, :916:33, :917:33] wire [1:0] _mem_ldq_e_T_2_bits_uop_lrs2_rtype = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_uop_lrs2_rtype : _mem_ldq_e_T_1_bits_uop_lrs2_rtype; // @[lsu.scala:263:49, :910:37, :916:33, :917:33] wire _mem_ldq_e_T_2_bits_uop_frs3_en = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_uop_frs3_en : _mem_ldq_e_T_1_bits_uop_frs3_en; // @[lsu.scala:263:49, :910:37, :916:33, :917:33] wire _mem_ldq_e_T_2_bits_uop_fp_val = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_uop_fp_val : _mem_ldq_e_T_1_bits_uop_fp_val; // @[lsu.scala:263:49, :910:37, :916:33, :917:33] wire _mem_ldq_e_T_2_bits_uop_fp_single = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_uop_fp_single : _mem_ldq_e_T_1_bits_uop_fp_single; // @[lsu.scala:263:49, :910:37, :916:33, :917:33] wire _mem_ldq_e_T_2_bits_uop_xcpt_pf_if = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_uop_xcpt_pf_if : _mem_ldq_e_T_1_bits_uop_xcpt_pf_if; // @[lsu.scala:263:49, :910:37, :916:33, :917:33] wire _mem_ldq_e_T_2_bits_uop_xcpt_ae_if = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_uop_xcpt_ae_if : _mem_ldq_e_T_1_bits_uop_xcpt_ae_if; // @[lsu.scala:263:49, :910:37, :916:33, :917:33] wire _mem_ldq_e_T_2_bits_uop_xcpt_ma_if = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_uop_xcpt_ma_if : _mem_ldq_e_T_1_bits_uop_xcpt_ma_if; // @[lsu.scala:263:49, :910:37, :916:33, :917:33] wire _mem_ldq_e_T_2_bits_uop_bp_debug_if = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_uop_bp_debug_if : _mem_ldq_e_T_1_bits_uop_bp_debug_if; // @[lsu.scala:263:49, :910:37, :916:33, :917:33] wire _mem_ldq_e_T_2_bits_uop_bp_xcpt_if = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_uop_bp_xcpt_if : _mem_ldq_e_T_1_bits_uop_bp_xcpt_if; // @[lsu.scala:263:49, :910:37, :916:33, :917:33] wire [1:0] _mem_ldq_e_T_2_bits_uop_debug_fsrc = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_uop_debug_fsrc : _mem_ldq_e_T_1_bits_uop_debug_fsrc; // @[lsu.scala:263:49, :910:37, :916:33, :917:33] wire [1:0] _mem_ldq_e_T_2_bits_uop_debug_tsrc = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_uop_debug_tsrc : _mem_ldq_e_T_1_bits_uop_debug_tsrc; // @[lsu.scala:263:49, :910:37, :916:33, :917:33] wire _mem_ldq_e_T_2_bits_addr_valid = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_addr_valid : _mem_ldq_e_T_1_bits_addr_valid; // @[lsu.scala:263:49, :910:37, :916:33, :917:33] wire [39:0] _mem_ldq_e_T_2_bits_addr_bits = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_addr_bits : _mem_ldq_e_T_1_bits_addr_bits; // @[lsu.scala:263:49, :910:37, :916:33, :917:33] wire _mem_ldq_e_T_2_bits_addr_is_virtual = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_addr_is_virtual : _mem_ldq_e_T_1_bits_addr_is_virtual; // @[lsu.scala:263:49, :910:37, :916:33, :917:33] wire _mem_ldq_e_T_2_bits_addr_is_uncacheable = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_addr_is_uncacheable : _mem_ldq_e_T_1_bits_addr_is_uncacheable; // @[lsu.scala:263:49, :910:37, :916:33, :917:33] wire _mem_ldq_e_T_2_bits_executed = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_executed : _mem_ldq_e_T_1_bits_executed; // @[lsu.scala:263:49, :910:37, :916:33, :917:33] wire _mem_ldq_e_T_2_bits_succeeded = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_succeeded : _mem_ldq_e_T_1_bits_succeeded; // @[lsu.scala:263:49, :910:37, :916:33, :917:33] wire _mem_ldq_e_T_2_bits_order_fail = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_order_fail : _mem_ldq_e_T_1_bits_order_fail; // @[lsu.scala:263:49, :910:37, :916:33, :917:33] wire _mem_ldq_e_T_2_bits_observed = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_observed : _mem_ldq_e_T_1_bits_observed; // @[lsu.scala:263:49, :910:37, :916:33, :917:33] wire [7:0] _mem_ldq_e_T_2_bits_st_dep_mask = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_st_dep_mask : _mem_ldq_e_T_1_bits_st_dep_mask; // @[lsu.scala:263:49, :910:37, :916:33, :917:33] wire [2:0] _mem_ldq_e_T_2_bits_youngest_stq_idx = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_youngest_stq_idx : _mem_ldq_e_T_1_bits_youngest_stq_idx; // @[lsu.scala:263:49, :910:37, :916:33, :917:33] wire _mem_ldq_e_T_2_bits_forward_std_val = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_forward_std_val : _mem_ldq_e_T_1_bits_forward_std_val; // @[lsu.scala:263:49, :910:37, :916:33, :917:33] wire [2:0] _mem_ldq_e_T_2_bits_forward_stq_idx = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_forward_stq_idx : _mem_ldq_e_T_1_bits_forward_stq_idx; // @[lsu.scala:263:49, :910:37, :916:33, :917:33] wire [63:0] _mem_ldq_e_T_2_bits_debug_wb_data = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_debug_wb_data : _mem_ldq_e_T_1_bits_debug_wb_data; // @[lsu.scala:263:49, :910:37, :916:33, :917:33] wire mem_ldq_e_0_valid = _mem_ldq_e_T_2_valid; // @[lsu.scala:263:49, :916:33] wire [6:0] mem_ldq_e_0_bits_uop_uopc = _mem_ldq_e_T_2_bits_uop_uopc; // @[lsu.scala:263:49, :916:33] wire [31:0] mem_ldq_e_0_bits_uop_inst = _mem_ldq_e_T_2_bits_uop_inst; // @[lsu.scala:263:49, :916:33] wire [31:0] mem_ldq_e_0_bits_uop_debug_inst = _mem_ldq_e_T_2_bits_uop_debug_inst; // @[lsu.scala:263:49, :916:33] wire mem_ldq_e_0_bits_uop_is_rvc = _mem_ldq_e_T_2_bits_uop_is_rvc; // @[lsu.scala:263:49, :916:33] wire [39:0] mem_ldq_e_0_bits_uop_debug_pc = _mem_ldq_e_T_2_bits_uop_debug_pc; // @[lsu.scala:263:49, :916:33] wire [2:0] mem_ldq_e_0_bits_uop_iq_type = _mem_ldq_e_T_2_bits_uop_iq_type; // @[lsu.scala:263:49, :916:33] wire [9:0] mem_ldq_e_0_bits_uop_fu_code = _mem_ldq_e_T_2_bits_uop_fu_code; // @[lsu.scala:263:49, :916:33] wire [3:0] mem_ldq_e_0_bits_uop_ctrl_br_type = _mem_ldq_e_T_2_bits_uop_ctrl_br_type; // @[lsu.scala:263:49, :916:33] wire [1:0] mem_ldq_e_0_bits_uop_ctrl_op1_sel = _mem_ldq_e_T_2_bits_uop_ctrl_op1_sel; // @[lsu.scala:263:49, :916:33] wire [2:0] mem_ldq_e_0_bits_uop_ctrl_op2_sel = _mem_ldq_e_T_2_bits_uop_ctrl_op2_sel; // @[lsu.scala:263:49, :916:33] wire [2:0] mem_ldq_e_0_bits_uop_ctrl_imm_sel = _mem_ldq_e_T_2_bits_uop_ctrl_imm_sel; // @[lsu.scala:263:49, :916:33] wire [4:0] mem_ldq_e_0_bits_uop_ctrl_op_fcn = _mem_ldq_e_T_2_bits_uop_ctrl_op_fcn; // @[lsu.scala:263:49, :916:33] wire mem_ldq_e_0_bits_uop_ctrl_fcn_dw = _mem_ldq_e_T_2_bits_uop_ctrl_fcn_dw; // @[lsu.scala:263:49, :916:33] wire [2:0] mem_ldq_e_0_bits_uop_ctrl_csr_cmd = _mem_ldq_e_T_2_bits_uop_ctrl_csr_cmd; // @[lsu.scala:263:49, :916:33] wire mem_ldq_e_0_bits_uop_ctrl_is_load = _mem_ldq_e_T_2_bits_uop_ctrl_is_load; // @[lsu.scala:263:49, :916:33] wire mem_ldq_e_0_bits_uop_ctrl_is_sta = _mem_ldq_e_T_2_bits_uop_ctrl_is_sta; // @[lsu.scala:263:49, :916:33] wire mem_ldq_e_0_bits_uop_ctrl_is_std = _mem_ldq_e_T_2_bits_uop_ctrl_is_std; // @[lsu.scala:263:49, :916:33] wire [1:0] mem_ldq_e_0_bits_uop_iw_state = _mem_ldq_e_T_2_bits_uop_iw_state; // @[lsu.scala:263:49, :916:33] wire mem_ldq_e_0_bits_uop_iw_p1_poisoned = _mem_ldq_e_T_2_bits_uop_iw_p1_poisoned; // @[lsu.scala:263:49, :916:33] wire mem_ldq_e_0_bits_uop_iw_p2_poisoned = _mem_ldq_e_T_2_bits_uop_iw_p2_poisoned; // @[lsu.scala:263:49, :916:33] wire mem_ldq_e_0_bits_uop_is_br = _mem_ldq_e_T_2_bits_uop_is_br; // @[lsu.scala:263:49, :916:33] wire mem_ldq_e_0_bits_uop_is_jalr = _mem_ldq_e_T_2_bits_uop_is_jalr; // @[lsu.scala:263:49, :916:33] wire mem_ldq_e_0_bits_uop_is_jal = _mem_ldq_e_T_2_bits_uop_is_jal; // @[lsu.scala:263:49, :916:33] wire mem_ldq_e_0_bits_uop_is_sfb = _mem_ldq_e_T_2_bits_uop_is_sfb; // @[lsu.scala:263:49, :916:33] wire [7:0] mem_ldq_e_0_bits_uop_br_mask = _mem_ldq_e_T_2_bits_uop_br_mask; // @[lsu.scala:263:49, :916:33] wire [2:0] mem_ldq_e_0_bits_uop_br_tag = _mem_ldq_e_T_2_bits_uop_br_tag; // @[lsu.scala:263:49, :916:33] wire [3:0] mem_ldq_e_0_bits_uop_ftq_idx = _mem_ldq_e_T_2_bits_uop_ftq_idx; // @[lsu.scala:263:49, :916:33] wire mem_ldq_e_0_bits_uop_edge_inst = _mem_ldq_e_T_2_bits_uop_edge_inst; // @[lsu.scala:263:49, :916:33] wire [5:0] mem_ldq_e_0_bits_uop_pc_lob = _mem_ldq_e_T_2_bits_uop_pc_lob; // @[lsu.scala:263:49, :916:33] wire mem_ldq_e_0_bits_uop_taken = _mem_ldq_e_T_2_bits_uop_taken; // @[lsu.scala:263:49, :916:33] wire [19:0] mem_ldq_e_0_bits_uop_imm_packed = _mem_ldq_e_T_2_bits_uop_imm_packed; // @[lsu.scala:263:49, :916:33] wire [11:0] mem_ldq_e_0_bits_uop_csr_addr = _mem_ldq_e_T_2_bits_uop_csr_addr; // @[lsu.scala:263:49, :916:33] wire [4:0] mem_ldq_e_0_bits_uop_rob_idx = _mem_ldq_e_T_2_bits_uop_rob_idx; // @[lsu.scala:263:49, :916:33] wire [2:0] mem_ldq_e_0_bits_uop_ldq_idx = _mem_ldq_e_T_2_bits_uop_ldq_idx; // @[lsu.scala:263:49, :916:33] wire [2:0] mem_ldq_e_0_bits_uop_stq_idx = _mem_ldq_e_T_2_bits_uop_stq_idx; // @[lsu.scala:263:49, :916:33] wire [1:0] mem_ldq_e_0_bits_uop_rxq_idx = _mem_ldq_e_T_2_bits_uop_rxq_idx; // @[lsu.scala:263:49, :916:33] wire [5:0] mem_ldq_e_0_bits_uop_pdst = _mem_ldq_e_T_2_bits_uop_pdst; // @[lsu.scala:263:49, :916:33] wire [5:0] mem_ldq_e_0_bits_uop_prs1 = _mem_ldq_e_T_2_bits_uop_prs1; // @[lsu.scala:263:49, :916:33] wire [5:0] mem_ldq_e_0_bits_uop_prs2 = _mem_ldq_e_T_2_bits_uop_prs2; // @[lsu.scala:263:49, :916:33] wire [5:0] mem_ldq_e_0_bits_uop_prs3 = _mem_ldq_e_T_2_bits_uop_prs3; // @[lsu.scala:263:49, :916:33] wire [3:0] mem_ldq_e_0_bits_uop_ppred = _mem_ldq_e_T_2_bits_uop_ppred; // @[lsu.scala:263:49, :916:33] wire mem_ldq_e_0_bits_uop_prs1_busy = _mem_ldq_e_T_2_bits_uop_prs1_busy; // @[lsu.scala:263:49, :916:33] wire mem_ldq_e_0_bits_uop_prs2_busy = _mem_ldq_e_T_2_bits_uop_prs2_busy; // @[lsu.scala:263:49, :916:33] wire mem_ldq_e_0_bits_uop_prs3_busy = _mem_ldq_e_T_2_bits_uop_prs3_busy; // @[lsu.scala:263:49, :916:33] wire mem_ldq_e_0_bits_uop_ppred_busy = _mem_ldq_e_T_2_bits_uop_ppred_busy; // @[lsu.scala:263:49, :916:33] wire [5:0] mem_ldq_e_0_bits_uop_stale_pdst = _mem_ldq_e_T_2_bits_uop_stale_pdst; // @[lsu.scala:263:49, :916:33] wire mem_ldq_e_0_bits_uop_exception = _mem_ldq_e_T_2_bits_uop_exception; // @[lsu.scala:263:49, :916:33] wire [63:0] mem_ldq_e_0_bits_uop_exc_cause = _mem_ldq_e_T_2_bits_uop_exc_cause; // @[lsu.scala:263:49, :916:33] wire mem_ldq_e_0_bits_uop_bypassable = _mem_ldq_e_T_2_bits_uop_bypassable; // @[lsu.scala:263:49, :916:33] wire [4:0] mem_ldq_e_0_bits_uop_mem_cmd = _mem_ldq_e_T_2_bits_uop_mem_cmd; // @[lsu.scala:263:49, :916:33] wire [1:0] mem_ldq_e_0_bits_uop_mem_size = _mem_ldq_e_T_2_bits_uop_mem_size; // @[lsu.scala:263:49, :916:33] wire mem_ldq_e_0_bits_uop_mem_signed = _mem_ldq_e_T_2_bits_uop_mem_signed; // @[lsu.scala:263:49, :916:33] wire mem_ldq_e_0_bits_uop_is_fence = _mem_ldq_e_T_2_bits_uop_is_fence; // @[lsu.scala:263:49, :916:33] wire mem_ldq_e_0_bits_uop_is_fencei = _mem_ldq_e_T_2_bits_uop_is_fencei; // @[lsu.scala:263:49, :916:33] wire mem_ldq_e_0_bits_uop_is_amo = _mem_ldq_e_T_2_bits_uop_is_amo; // @[lsu.scala:263:49, :916:33] wire mem_ldq_e_0_bits_uop_uses_ldq = _mem_ldq_e_T_2_bits_uop_uses_ldq; // @[lsu.scala:263:49, :916:33] wire mem_ldq_e_0_bits_uop_uses_stq = _mem_ldq_e_T_2_bits_uop_uses_stq; // @[lsu.scala:263:49, :916:33] wire mem_ldq_e_0_bits_uop_is_sys_pc2epc = _mem_ldq_e_T_2_bits_uop_is_sys_pc2epc; // @[lsu.scala:263:49, :916:33] wire mem_ldq_e_0_bits_uop_is_unique = _mem_ldq_e_T_2_bits_uop_is_unique; // @[lsu.scala:263:49, :916:33] wire mem_ldq_e_0_bits_uop_flush_on_commit = _mem_ldq_e_T_2_bits_uop_flush_on_commit; // @[lsu.scala:263:49, :916:33] wire mem_ldq_e_0_bits_uop_ldst_is_rs1 = _mem_ldq_e_T_2_bits_uop_ldst_is_rs1; // @[lsu.scala:263:49, :916:33] wire [5:0] mem_ldq_e_0_bits_uop_ldst = _mem_ldq_e_T_2_bits_uop_ldst; // @[lsu.scala:263:49, :916:33] wire [5:0] mem_ldq_e_0_bits_uop_lrs1 = _mem_ldq_e_T_2_bits_uop_lrs1; // @[lsu.scala:263:49, :916:33] wire [5:0] mem_ldq_e_0_bits_uop_lrs2 = _mem_ldq_e_T_2_bits_uop_lrs2; // @[lsu.scala:263:49, :916:33] wire [5:0] mem_ldq_e_0_bits_uop_lrs3 = _mem_ldq_e_T_2_bits_uop_lrs3; // @[lsu.scala:263:49, :916:33] wire mem_ldq_e_0_bits_uop_ldst_val = _mem_ldq_e_T_2_bits_uop_ldst_val; // @[lsu.scala:263:49, :916:33] wire [1:0] mem_ldq_e_0_bits_uop_dst_rtype = _mem_ldq_e_T_2_bits_uop_dst_rtype; // @[lsu.scala:263:49, :916:33] wire [1:0] mem_ldq_e_0_bits_uop_lrs1_rtype = _mem_ldq_e_T_2_bits_uop_lrs1_rtype; // @[lsu.scala:263:49, :916:33] wire [1:0] mem_ldq_e_0_bits_uop_lrs2_rtype = _mem_ldq_e_T_2_bits_uop_lrs2_rtype; // @[lsu.scala:263:49, :916:33] wire mem_ldq_e_0_bits_uop_frs3_en = _mem_ldq_e_T_2_bits_uop_frs3_en; // @[lsu.scala:263:49, :916:33] wire mem_ldq_e_0_bits_uop_fp_val = _mem_ldq_e_T_2_bits_uop_fp_val; // @[lsu.scala:263:49, :916:33] wire mem_ldq_e_0_bits_uop_fp_single = _mem_ldq_e_T_2_bits_uop_fp_single; // @[lsu.scala:263:49, :916:33] wire mem_ldq_e_0_bits_uop_xcpt_pf_if = _mem_ldq_e_T_2_bits_uop_xcpt_pf_if; // @[lsu.scala:263:49, :916:33] wire mem_ldq_e_0_bits_uop_xcpt_ae_if = _mem_ldq_e_T_2_bits_uop_xcpt_ae_if; // @[lsu.scala:263:49, :916:33] wire mem_ldq_e_0_bits_uop_xcpt_ma_if = _mem_ldq_e_T_2_bits_uop_xcpt_ma_if; // @[lsu.scala:263:49, :916:33] wire mem_ldq_e_0_bits_uop_bp_debug_if = _mem_ldq_e_T_2_bits_uop_bp_debug_if; // @[lsu.scala:263:49, :916:33] wire mem_ldq_e_0_bits_uop_bp_xcpt_if = _mem_ldq_e_T_2_bits_uop_bp_xcpt_if; // @[lsu.scala:263:49, :916:33] wire [1:0] mem_ldq_e_0_bits_uop_debug_fsrc = _mem_ldq_e_T_2_bits_uop_debug_fsrc; // @[lsu.scala:263:49, :916:33] wire [1:0] mem_ldq_e_0_bits_uop_debug_tsrc = _mem_ldq_e_T_2_bits_uop_debug_tsrc; // @[lsu.scala:263:49, :916:33] wire mem_ldq_e_0_bits_addr_valid = _mem_ldq_e_T_2_bits_addr_valid; // @[lsu.scala:263:49, :916:33] wire [39:0] mem_ldq_e_0_bits_addr_bits = _mem_ldq_e_T_2_bits_addr_bits; // @[lsu.scala:263:49, :916:33] wire mem_ldq_e_0_bits_addr_is_virtual = _mem_ldq_e_T_2_bits_addr_is_virtual; // @[lsu.scala:263:49, :916:33] wire mem_ldq_e_0_bits_addr_is_uncacheable = _mem_ldq_e_T_2_bits_addr_is_uncacheable; // @[lsu.scala:263:49, :916:33] wire mem_ldq_e_0_bits_executed = _mem_ldq_e_T_2_bits_executed; // @[lsu.scala:263:49, :916:33] wire mem_ldq_e_0_bits_succeeded = _mem_ldq_e_T_2_bits_succeeded; // @[lsu.scala:263:49, :916:33] wire mem_ldq_e_0_bits_order_fail = _mem_ldq_e_T_2_bits_order_fail; // @[lsu.scala:263:49, :916:33] wire mem_ldq_e_0_bits_observed = _mem_ldq_e_T_2_bits_observed; // @[lsu.scala:263:49, :916:33] wire [7:0] mem_ldq_e_0_bits_st_dep_mask = _mem_ldq_e_T_2_bits_st_dep_mask; // @[lsu.scala:263:49, :916:33] wire [2:0] mem_ldq_e_0_bits_youngest_stq_idx = _mem_ldq_e_T_2_bits_youngest_stq_idx; // @[lsu.scala:263:49, :916:33] wire mem_ldq_e_0_bits_forward_std_val = _mem_ldq_e_T_2_bits_forward_std_val; // @[lsu.scala:263:49, :916:33] wire [2:0] mem_ldq_e_0_bits_forward_stq_idx = _mem_ldq_e_T_2_bits_forward_stq_idx; // @[lsu.scala:263:49, :916:33] wire [63:0] mem_ldq_e_0_bits_debug_wb_data = _mem_ldq_e_T_2_bits_debug_wb_data; // @[lsu.scala:263:49, :916:33] wire [7:0] lcam_st_dep_mask_0 = mem_ldq_e_0_bits_st_dep_mask; // @[lsu.scala:263:49] wire _GEN_226 = fired_stad_incoming_0 | fired_sta_incoming_0; // @[lsu.scala:263:49, :920:57] wire _mem_stq_e_T; // @[lsu.scala:920:57] assign _mem_stq_e_T = _GEN_226; // @[lsu.scala:920:57] wire _do_st_search_T; // @[lsu.scala:1015:60] assign _do_st_search_T = _GEN_226; // @[lsu.scala:920:57, :1015:60] wire _lcam_addr_T; // @[lsu.scala:1026:61] assign _lcam_addr_T = _GEN_226; // @[lsu.scala:920:57, :1026:61] wire _lcam_stq_idx_T; // @[lsu.scala:1041:50] assign _lcam_stq_idx_T = _GEN_226; // @[lsu.scala:920:57, :1041:50] wire _mem_stq_e_T_1_valid = fired_sta_retry_0 & mem_stq_retry_e_valid; // @[lsu.scala:263:49, :914:37, :922:33] wire [6:0] _mem_stq_e_T_1_bits_uop_uopc = fired_sta_retry_0 ? mem_stq_retry_e_bits_uop_uopc : 7'h0; // @[lsu.scala:263:49, :914:37, :922:33] wire [31:0] _mem_stq_e_T_1_bits_uop_inst = fired_sta_retry_0 ? mem_stq_retry_e_bits_uop_inst : 32'h0; // @[lsu.scala:263:49, :914:37, :922:33] wire [31:0] _mem_stq_e_T_1_bits_uop_debug_inst = fired_sta_retry_0 ? mem_stq_retry_e_bits_uop_debug_inst : 32'h0; // @[lsu.scala:263:49, :914:37, :922:33] wire _mem_stq_e_T_1_bits_uop_is_rvc = fired_sta_retry_0 & mem_stq_retry_e_bits_uop_is_rvc; // @[lsu.scala:263:49, :914:37, :922:33] wire [39:0] _mem_stq_e_T_1_bits_uop_debug_pc = fired_sta_retry_0 ? mem_stq_retry_e_bits_uop_debug_pc : 40'h0; // @[lsu.scala:263:49, :914:37, :922:33] wire [2:0] _mem_stq_e_T_1_bits_uop_iq_type = fired_sta_retry_0 ? mem_stq_retry_e_bits_uop_iq_type : 3'h0; // @[lsu.scala:263:49, :914:37, :922:33] wire [9:0] _mem_stq_e_T_1_bits_uop_fu_code = fired_sta_retry_0 ? mem_stq_retry_e_bits_uop_fu_code : 10'h0; // @[lsu.scala:263:49, :914:37, :922:33] wire [3:0] _mem_stq_e_T_1_bits_uop_ctrl_br_type = fired_sta_retry_0 ? mem_stq_retry_e_bits_uop_ctrl_br_type : 4'h0; // @[lsu.scala:263:49, :914:37, :922:33] wire [1:0] _mem_stq_e_T_1_bits_uop_ctrl_op1_sel = fired_sta_retry_0 ? mem_stq_retry_e_bits_uop_ctrl_op1_sel : 2'h0; // @[lsu.scala:263:49, :914:37, :922:33] wire [2:0] _mem_stq_e_T_1_bits_uop_ctrl_op2_sel = fired_sta_retry_0 ? mem_stq_retry_e_bits_uop_ctrl_op2_sel : 3'h0; // @[lsu.scala:263:49, :914:37, :922:33] wire [2:0] _mem_stq_e_T_1_bits_uop_ctrl_imm_sel = fired_sta_retry_0 ? mem_stq_retry_e_bits_uop_ctrl_imm_sel : 3'h0; // @[lsu.scala:263:49, :914:37, :922:33] wire [4:0] _mem_stq_e_T_1_bits_uop_ctrl_op_fcn = fired_sta_retry_0 ? mem_stq_retry_e_bits_uop_ctrl_op_fcn : 5'h0; // @[lsu.scala:263:49, :914:37, :922:33] wire _mem_stq_e_T_1_bits_uop_ctrl_fcn_dw = fired_sta_retry_0 & mem_stq_retry_e_bits_uop_ctrl_fcn_dw; // @[lsu.scala:263:49, :914:37, :922:33] wire [2:0] _mem_stq_e_T_1_bits_uop_ctrl_csr_cmd = fired_sta_retry_0 ? mem_stq_retry_e_bits_uop_ctrl_csr_cmd : 3'h0; // @[lsu.scala:263:49, :914:37, :922:33] wire _mem_stq_e_T_1_bits_uop_ctrl_is_load = fired_sta_retry_0 & mem_stq_retry_e_bits_uop_ctrl_is_load; // @[lsu.scala:263:49, :914:37, :922:33] wire _mem_stq_e_T_1_bits_uop_ctrl_is_sta = fired_sta_retry_0 & mem_stq_retry_e_bits_uop_ctrl_is_sta; // @[lsu.scala:263:49, :914:37, :922:33] wire _mem_stq_e_T_1_bits_uop_ctrl_is_std = fired_sta_retry_0 & mem_stq_retry_e_bits_uop_ctrl_is_std; // @[lsu.scala:263:49, :914:37, :922:33] wire [1:0] _mem_stq_e_T_1_bits_uop_iw_state = fired_sta_retry_0 ? mem_stq_retry_e_bits_uop_iw_state : 2'h0; // @[lsu.scala:263:49, :914:37, :922:33] wire _mem_stq_e_T_1_bits_uop_iw_p1_poisoned = fired_sta_retry_0 & mem_stq_retry_e_bits_uop_iw_p1_poisoned; // @[lsu.scala:263:49, :914:37, :922:33] wire _mem_stq_e_T_1_bits_uop_iw_p2_poisoned = fired_sta_retry_0 & mem_stq_retry_e_bits_uop_iw_p2_poisoned; // @[lsu.scala:263:49, :914:37, :922:33] wire _mem_stq_e_T_1_bits_uop_is_br = fired_sta_retry_0 & mem_stq_retry_e_bits_uop_is_br; // @[lsu.scala:263:49, :914:37, :922:33] wire _mem_stq_e_T_1_bits_uop_is_jalr = fired_sta_retry_0 & mem_stq_retry_e_bits_uop_is_jalr; // @[lsu.scala:263:49, :914:37, :922:33] wire _mem_stq_e_T_1_bits_uop_is_jal = fired_sta_retry_0 & mem_stq_retry_e_bits_uop_is_jal; // @[lsu.scala:263:49, :914:37, :922:33] wire _mem_stq_e_T_1_bits_uop_is_sfb = fired_sta_retry_0 & mem_stq_retry_e_bits_uop_is_sfb; // @[lsu.scala:263:49, :914:37, :922:33] wire [7:0] _mem_stq_e_T_1_bits_uop_br_mask = fired_sta_retry_0 ? mem_stq_retry_e_bits_uop_br_mask : 8'h0; // @[lsu.scala:263:49, :914:37, :922:33] wire [2:0] _mem_stq_e_T_1_bits_uop_br_tag = fired_sta_retry_0 ? mem_stq_retry_e_bits_uop_br_tag : 3'h0; // @[lsu.scala:263:49, :914:37, :922:33] wire [3:0] _mem_stq_e_T_1_bits_uop_ftq_idx = fired_sta_retry_0 ? mem_stq_retry_e_bits_uop_ftq_idx : 4'h0; // @[lsu.scala:263:49, :914:37, :922:33] wire _mem_stq_e_T_1_bits_uop_edge_inst = fired_sta_retry_0 & mem_stq_retry_e_bits_uop_edge_inst; // @[lsu.scala:263:49, :914:37, :922:33] wire [5:0] _mem_stq_e_T_1_bits_uop_pc_lob = fired_sta_retry_0 ? mem_stq_retry_e_bits_uop_pc_lob : 6'h0; // @[lsu.scala:263:49, :914:37, :922:33] wire _mem_stq_e_T_1_bits_uop_taken = fired_sta_retry_0 & mem_stq_retry_e_bits_uop_taken; // @[lsu.scala:263:49, :914:37, :922:33] wire [19:0] _mem_stq_e_T_1_bits_uop_imm_packed = fired_sta_retry_0 ? mem_stq_retry_e_bits_uop_imm_packed : 20'h0; // @[lsu.scala:263:49, :914:37, :922:33] wire [11:0] _mem_stq_e_T_1_bits_uop_csr_addr = fired_sta_retry_0 ? mem_stq_retry_e_bits_uop_csr_addr : 12'h0; // @[lsu.scala:263:49, :914:37, :922:33] wire [4:0] _mem_stq_e_T_1_bits_uop_rob_idx = fired_sta_retry_0 ? mem_stq_retry_e_bits_uop_rob_idx : 5'h0; // @[lsu.scala:263:49, :914:37, :922:33] wire [2:0] _mem_stq_e_T_1_bits_uop_ldq_idx = fired_sta_retry_0 ? mem_stq_retry_e_bits_uop_ldq_idx : 3'h0; // @[lsu.scala:263:49, :914:37, :922:33] wire [2:0] _mem_stq_e_T_1_bits_uop_stq_idx = fired_sta_retry_0 ? mem_stq_retry_e_bits_uop_stq_idx : 3'h0; // @[lsu.scala:263:49, :914:37, :922:33] wire [1:0] _mem_stq_e_T_1_bits_uop_rxq_idx = fired_sta_retry_0 ? mem_stq_retry_e_bits_uop_rxq_idx : 2'h0; // @[lsu.scala:263:49, :914:37, :922:33] wire [5:0] _mem_stq_e_T_1_bits_uop_pdst = fired_sta_retry_0 ? mem_stq_retry_e_bits_uop_pdst : 6'h0; // @[lsu.scala:263:49, :914:37, :922:33] wire [5:0] _mem_stq_e_T_1_bits_uop_prs1 = fired_sta_retry_0 ? mem_stq_retry_e_bits_uop_prs1 : 6'h0; // @[lsu.scala:263:49, :914:37, :922:33] wire [5:0] _mem_stq_e_T_1_bits_uop_prs2 = fired_sta_retry_0 ? mem_stq_retry_e_bits_uop_prs2 : 6'h0; // @[lsu.scala:263:49, :914:37, :922:33] wire [5:0] _mem_stq_e_T_1_bits_uop_prs3 = fired_sta_retry_0 ? mem_stq_retry_e_bits_uop_prs3 : 6'h0; // @[lsu.scala:263:49, :914:37, :922:33] wire [3:0] _mem_stq_e_T_1_bits_uop_ppred = fired_sta_retry_0 ? mem_stq_retry_e_bits_uop_ppred : 4'h0; // @[lsu.scala:263:49, :914:37, :922:33] wire _mem_stq_e_T_1_bits_uop_prs1_busy = fired_sta_retry_0 & mem_stq_retry_e_bits_uop_prs1_busy; // @[lsu.scala:263:49, :914:37, :922:33] wire _mem_stq_e_T_1_bits_uop_prs2_busy = fired_sta_retry_0 & mem_stq_retry_e_bits_uop_prs2_busy; // @[lsu.scala:263:49, :914:37, :922:33] wire _mem_stq_e_T_1_bits_uop_prs3_busy = fired_sta_retry_0 & mem_stq_retry_e_bits_uop_prs3_busy; // @[lsu.scala:263:49, :914:37, :922:33] wire _mem_stq_e_T_1_bits_uop_ppred_busy = fired_sta_retry_0 & mem_stq_retry_e_bits_uop_ppred_busy; // @[lsu.scala:263:49, :914:37, :922:33] wire [5:0] _mem_stq_e_T_1_bits_uop_stale_pdst = fired_sta_retry_0 ? mem_stq_retry_e_bits_uop_stale_pdst : 6'h0; // @[lsu.scala:263:49, :914:37, :922:33] wire _mem_stq_e_T_1_bits_uop_exception = fired_sta_retry_0 & mem_stq_retry_e_bits_uop_exception; // @[lsu.scala:263:49, :914:37, :922:33] wire [63:0] _mem_stq_e_T_1_bits_uop_exc_cause = fired_sta_retry_0 ? mem_stq_retry_e_bits_uop_exc_cause : 64'h0; // @[lsu.scala:263:49, :914:37, :922:33] wire _mem_stq_e_T_1_bits_uop_bypassable = fired_sta_retry_0 & mem_stq_retry_e_bits_uop_bypassable; // @[lsu.scala:263:49, :914:37, :922:33] wire [4:0] _mem_stq_e_T_1_bits_uop_mem_cmd = fired_sta_retry_0 ? mem_stq_retry_e_bits_uop_mem_cmd : 5'h0; // @[lsu.scala:263:49, :914:37, :922:33] wire [1:0] _mem_stq_e_T_1_bits_uop_mem_size = fired_sta_retry_0 ? mem_stq_retry_e_bits_uop_mem_size : 2'h0; // @[lsu.scala:263:49, :914:37, :922:33] wire _mem_stq_e_T_1_bits_uop_mem_signed = fired_sta_retry_0 & mem_stq_retry_e_bits_uop_mem_signed; // @[lsu.scala:263:49, :914:37, :922:33] wire _mem_stq_e_T_1_bits_uop_is_fence = fired_sta_retry_0 & mem_stq_retry_e_bits_uop_is_fence; // @[lsu.scala:263:49, :914:37, :922:33] wire _mem_stq_e_T_1_bits_uop_is_fencei = fired_sta_retry_0 & mem_stq_retry_e_bits_uop_is_fencei; // @[lsu.scala:263:49, :914:37, :922:33] wire _mem_stq_e_T_1_bits_uop_is_amo = fired_sta_retry_0 & mem_stq_retry_e_bits_uop_is_amo; // @[lsu.scala:263:49, :914:37, :922:33] wire _mem_stq_e_T_1_bits_uop_uses_ldq = fired_sta_retry_0 & mem_stq_retry_e_bits_uop_uses_ldq; // @[lsu.scala:263:49, :914:37, :922:33] wire _mem_stq_e_T_1_bits_uop_uses_stq = fired_sta_retry_0 & mem_stq_retry_e_bits_uop_uses_stq; // @[lsu.scala:263:49, :914:37, :922:33] wire _mem_stq_e_T_1_bits_uop_is_sys_pc2epc = fired_sta_retry_0 & mem_stq_retry_e_bits_uop_is_sys_pc2epc; // @[lsu.scala:263:49, :914:37, :922:33] wire _mem_stq_e_T_1_bits_uop_is_unique = fired_sta_retry_0 & mem_stq_retry_e_bits_uop_is_unique; // @[lsu.scala:263:49, :914:37, :922:33] wire _mem_stq_e_T_1_bits_uop_flush_on_commit = fired_sta_retry_0 & mem_stq_retry_e_bits_uop_flush_on_commit; // @[lsu.scala:263:49, :914:37, :922:33] wire _mem_stq_e_T_1_bits_uop_ldst_is_rs1 = fired_sta_retry_0 & mem_stq_retry_e_bits_uop_ldst_is_rs1; // @[lsu.scala:263:49, :914:37, :922:33] wire [5:0] _mem_stq_e_T_1_bits_uop_ldst = fired_sta_retry_0 ? mem_stq_retry_e_bits_uop_ldst : 6'h0; // @[lsu.scala:263:49, :914:37, :922:33] wire [5:0] _mem_stq_e_T_1_bits_uop_lrs1 = fired_sta_retry_0 ? mem_stq_retry_e_bits_uop_lrs1 : 6'h0; // @[lsu.scala:263:49, :914:37, :922:33] wire [5:0] _mem_stq_e_T_1_bits_uop_lrs2 = fired_sta_retry_0 ? mem_stq_retry_e_bits_uop_lrs2 : 6'h0; // @[lsu.scala:263:49, :914:37, :922:33] wire [5:0] _mem_stq_e_T_1_bits_uop_lrs3 = fired_sta_retry_0 ? mem_stq_retry_e_bits_uop_lrs3 : 6'h0; // @[lsu.scala:263:49, :914:37, :922:33] wire _mem_stq_e_T_1_bits_uop_ldst_val = fired_sta_retry_0 & mem_stq_retry_e_bits_uop_ldst_val; // @[lsu.scala:263:49, :914:37, :922:33] wire [1:0] _mem_stq_e_T_1_bits_uop_dst_rtype = fired_sta_retry_0 ? mem_stq_retry_e_bits_uop_dst_rtype : 2'h0; // @[lsu.scala:263:49, :914:37, :922:33] wire [1:0] _mem_stq_e_T_1_bits_uop_lrs1_rtype = fired_sta_retry_0 ? mem_stq_retry_e_bits_uop_lrs1_rtype : 2'h0; // @[lsu.scala:263:49, :914:37, :922:33] wire [1:0] _mem_stq_e_T_1_bits_uop_lrs2_rtype = fired_sta_retry_0 ? mem_stq_retry_e_bits_uop_lrs2_rtype : 2'h0; // @[lsu.scala:263:49, :914:37, :922:33] wire _mem_stq_e_T_1_bits_uop_frs3_en = fired_sta_retry_0 & mem_stq_retry_e_bits_uop_frs3_en; // @[lsu.scala:263:49, :914:37, :922:33] wire _mem_stq_e_T_1_bits_uop_fp_val = fired_sta_retry_0 & mem_stq_retry_e_bits_uop_fp_val; // @[lsu.scala:263:49, :914:37, :922:33] wire _mem_stq_e_T_1_bits_uop_fp_single = fired_sta_retry_0 & mem_stq_retry_e_bits_uop_fp_single; // @[lsu.scala:263:49, :914:37, :922:33] wire _mem_stq_e_T_1_bits_uop_xcpt_pf_if = fired_sta_retry_0 & mem_stq_retry_e_bits_uop_xcpt_pf_if; // @[lsu.scala:263:49, :914:37, :922:33] wire _mem_stq_e_T_1_bits_uop_xcpt_ae_if = fired_sta_retry_0 & mem_stq_retry_e_bits_uop_xcpt_ae_if; // @[lsu.scala:263:49, :914:37, :922:33] wire _mem_stq_e_T_1_bits_uop_xcpt_ma_if = fired_sta_retry_0 & mem_stq_retry_e_bits_uop_xcpt_ma_if; // @[lsu.scala:263:49, :914:37, :922:33] wire _mem_stq_e_T_1_bits_uop_bp_debug_if = fired_sta_retry_0 & mem_stq_retry_e_bits_uop_bp_debug_if; // @[lsu.scala:263:49, :914:37, :922:33] wire _mem_stq_e_T_1_bits_uop_bp_xcpt_if = fired_sta_retry_0 & mem_stq_retry_e_bits_uop_bp_xcpt_if; // @[lsu.scala:263:49, :914:37, :922:33] wire [1:0] _mem_stq_e_T_1_bits_uop_debug_fsrc = fired_sta_retry_0 ? mem_stq_retry_e_bits_uop_debug_fsrc : 2'h0; // @[lsu.scala:263:49, :914:37, :922:33] wire [1:0] _mem_stq_e_T_1_bits_uop_debug_tsrc = fired_sta_retry_0 ? mem_stq_retry_e_bits_uop_debug_tsrc : 2'h0; // @[lsu.scala:263:49, :914:37, :922:33] wire _mem_stq_e_T_1_bits_addr_valid = fired_sta_retry_0 & mem_stq_retry_e_bits_addr_valid; // @[lsu.scala:263:49, :914:37, :922:33] wire [39:0] _mem_stq_e_T_1_bits_addr_bits = fired_sta_retry_0 ? mem_stq_retry_e_bits_addr_bits : 40'h0; // @[lsu.scala:263:49, :914:37, :922:33] wire _mem_stq_e_T_1_bits_addr_is_virtual = fired_sta_retry_0 & mem_stq_retry_e_bits_addr_is_virtual; // @[lsu.scala:263:49, :914:37, :922:33] wire _mem_stq_e_T_1_bits_data_valid = fired_sta_retry_0 & mem_stq_retry_e_bits_data_valid; // @[lsu.scala:263:49, :914:37, :922:33] wire [63:0] _mem_stq_e_T_1_bits_data_bits = fired_sta_retry_0 ? mem_stq_retry_e_bits_data_bits : 64'h0; // @[lsu.scala:263:49, :914:37, :922:33] wire _mem_stq_e_T_1_bits_committed = fired_sta_retry_0 & mem_stq_retry_e_bits_committed; // @[lsu.scala:263:49, :914:37, :922:33] wire _mem_stq_e_T_1_bits_succeeded = fired_sta_retry_0 & mem_stq_retry_e_bits_succeeded; // @[lsu.scala:263:49, :914:37, :922:33] wire [63:0] _mem_stq_e_T_1_bits_debug_wb_data = fired_sta_retry_0 ? mem_stq_retry_e_bits_debug_wb_data : 64'h0; // @[lsu.scala:263:49, :914:37, :922:33] wire _mem_stq_e_T_2_valid = _mem_stq_e_T ? mem_stq_incoming_e_0_valid : _mem_stq_e_T_1_valid; // @[lsu.scala:911:37, :920:{33,57}, :922:33] wire [6:0] _mem_stq_e_T_2_bits_uop_uopc = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_uop_uopc : _mem_stq_e_T_1_bits_uop_uopc; // @[lsu.scala:911:37, :920:{33,57}, :922:33] wire [31:0] _mem_stq_e_T_2_bits_uop_inst = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_uop_inst : _mem_stq_e_T_1_bits_uop_inst; // @[lsu.scala:911:37, :920:{33,57}, :922:33] wire [31:0] _mem_stq_e_T_2_bits_uop_debug_inst = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_uop_debug_inst : _mem_stq_e_T_1_bits_uop_debug_inst; // @[lsu.scala:911:37, :920:{33,57}, :922:33] wire _mem_stq_e_T_2_bits_uop_is_rvc = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_uop_is_rvc : _mem_stq_e_T_1_bits_uop_is_rvc; // @[lsu.scala:911:37, :920:{33,57}, :922:33] wire [39:0] _mem_stq_e_T_2_bits_uop_debug_pc = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_uop_debug_pc : _mem_stq_e_T_1_bits_uop_debug_pc; // @[lsu.scala:911:37, :920:{33,57}, :922:33] wire [2:0] _mem_stq_e_T_2_bits_uop_iq_type = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_uop_iq_type : _mem_stq_e_T_1_bits_uop_iq_type; // @[lsu.scala:911:37, :920:{33,57}, :922:33] wire [9:0] _mem_stq_e_T_2_bits_uop_fu_code = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_uop_fu_code : _mem_stq_e_T_1_bits_uop_fu_code; // @[lsu.scala:911:37, :920:{33,57}, :922:33] wire [3:0] _mem_stq_e_T_2_bits_uop_ctrl_br_type = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_uop_ctrl_br_type : _mem_stq_e_T_1_bits_uop_ctrl_br_type; // @[lsu.scala:911:37, :920:{33,57}, :922:33] wire [1:0] _mem_stq_e_T_2_bits_uop_ctrl_op1_sel = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_uop_ctrl_op1_sel : _mem_stq_e_T_1_bits_uop_ctrl_op1_sel; // @[lsu.scala:911:37, :920:{33,57}, :922:33] wire [2:0] _mem_stq_e_T_2_bits_uop_ctrl_op2_sel = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_uop_ctrl_op2_sel : _mem_stq_e_T_1_bits_uop_ctrl_op2_sel; // @[lsu.scala:911:37, :920:{33,57}, :922:33] wire [2:0] _mem_stq_e_T_2_bits_uop_ctrl_imm_sel = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_uop_ctrl_imm_sel : _mem_stq_e_T_1_bits_uop_ctrl_imm_sel; // @[lsu.scala:911:37, :920:{33,57}, :922:33] wire [4:0] _mem_stq_e_T_2_bits_uop_ctrl_op_fcn = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_uop_ctrl_op_fcn : _mem_stq_e_T_1_bits_uop_ctrl_op_fcn; // @[lsu.scala:911:37, :920:{33,57}, :922:33] wire _mem_stq_e_T_2_bits_uop_ctrl_fcn_dw = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_uop_ctrl_fcn_dw : _mem_stq_e_T_1_bits_uop_ctrl_fcn_dw; // @[lsu.scala:911:37, :920:{33,57}, :922:33] wire [2:0] _mem_stq_e_T_2_bits_uop_ctrl_csr_cmd = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_uop_ctrl_csr_cmd : _mem_stq_e_T_1_bits_uop_ctrl_csr_cmd; // @[lsu.scala:911:37, :920:{33,57}, :922:33] wire _mem_stq_e_T_2_bits_uop_ctrl_is_load = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_uop_ctrl_is_load : _mem_stq_e_T_1_bits_uop_ctrl_is_load; // @[lsu.scala:911:37, :920:{33,57}, :922:33] wire _mem_stq_e_T_2_bits_uop_ctrl_is_sta = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_uop_ctrl_is_sta : _mem_stq_e_T_1_bits_uop_ctrl_is_sta; // @[lsu.scala:911:37, :920:{33,57}, :922:33] wire _mem_stq_e_T_2_bits_uop_ctrl_is_std = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_uop_ctrl_is_std : _mem_stq_e_T_1_bits_uop_ctrl_is_std; // @[lsu.scala:911:37, :920:{33,57}, :922:33] wire [1:0] _mem_stq_e_T_2_bits_uop_iw_state = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_uop_iw_state : _mem_stq_e_T_1_bits_uop_iw_state; // @[lsu.scala:911:37, :920:{33,57}, :922:33] wire _mem_stq_e_T_2_bits_uop_iw_p1_poisoned = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_uop_iw_p1_poisoned : _mem_stq_e_T_1_bits_uop_iw_p1_poisoned; // @[lsu.scala:911:37, :920:{33,57}, :922:33] wire _mem_stq_e_T_2_bits_uop_iw_p2_poisoned = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_uop_iw_p2_poisoned : _mem_stq_e_T_1_bits_uop_iw_p2_poisoned; // @[lsu.scala:911:37, :920:{33,57}, :922:33] wire _mem_stq_e_T_2_bits_uop_is_br = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_uop_is_br : _mem_stq_e_T_1_bits_uop_is_br; // @[lsu.scala:911:37, :920:{33,57}, :922:33] wire _mem_stq_e_T_2_bits_uop_is_jalr = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_uop_is_jalr : _mem_stq_e_T_1_bits_uop_is_jalr; // @[lsu.scala:911:37, :920:{33,57}, :922:33] wire _mem_stq_e_T_2_bits_uop_is_jal = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_uop_is_jal : _mem_stq_e_T_1_bits_uop_is_jal; // @[lsu.scala:911:37, :920:{33,57}, :922:33] wire _mem_stq_e_T_2_bits_uop_is_sfb = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_uop_is_sfb : _mem_stq_e_T_1_bits_uop_is_sfb; // @[lsu.scala:911:37, :920:{33,57}, :922:33] wire [7:0] _mem_stq_e_T_2_bits_uop_br_mask = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_uop_br_mask : _mem_stq_e_T_1_bits_uop_br_mask; // @[lsu.scala:911:37, :920:{33,57}, :922:33] wire [2:0] _mem_stq_e_T_2_bits_uop_br_tag = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_uop_br_tag : _mem_stq_e_T_1_bits_uop_br_tag; // @[lsu.scala:911:37, :920:{33,57}, :922:33] wire [3:0] _mem_stq_e_T_2_bits_uop_ftq_idx = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_uop_ftq_idx : _mem_stq_e_T_1_bits_uop_ftq_idx; // @[lsu.scala:911:37, :920:{33,57}, :922:33] wire _mem_stq_e_T_2_bits_uop_edge_inst = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_uop_edge_inst : _mem_stq_e_T_1_bits_uop_edge_inst; // @[lsu.scala:911:37, :920:{33,57}, :922:33] wire [5:0] _mem_stq_e_T_2_bits_uop_pc_lob = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_uop_pc_lob : _mem_stq_e_T_1_bits_uop_pc_lob; // @[lsu.scala:911:37, :920:{33,57}, :922:33] wire _mem_stq_e_T_2_bits_uop_taken = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_uop_taken : _mem_stq_e_T_1_bits_uop_taken; // @[lsu.scala:911:37, :920:{33,57}, :922:33] wire [19:0] _mem_stq_e_T_2_bits_uop_imm_packed = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_uop_imm_packed : _mem_stq_e_T_1_bits_uop_imm_packed; // @[lsu.scala:911:37, :920:{33,57}, :922:33] wire [11:0] _mem_stq_e_T_2_bits_uop_csr_addr = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_uop_csr_addr : _mem_stq_e_T_1_bits_uop_csr_addr; // @[lsu.scala:911:37, :920:{33,57}, :922:33] wire [4:0] _mem_stq_e_T_2_bits_uop_rob_idx = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_uop_rob_idx : _mem_stq_e_T_1_bits_uop_rob_idx; // @[lsu.scala:911:37, :920:{33,57}, :922:33] wire [2:0] _mem_stq_e_T_2_bits_uop_ldq_idx = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_uop_ldq_idx : _mem_stq_e_T_1_bits_uop_ldq_idx; // @[lsu.scala:911:37, :920:{33,57}, :922:33] wire [2:0] _mem_stq_e_T_2_bits_uop_stq_idx = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_uop_stq_idx : _mem_stq_e_T_1_bits_uop_stq_idx; // @[lsu.scala:911:37, :920:{33,57}, :922:33] wire [1:0] _mem_stq_e_T_2_bits_uop_rxq_idx = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_uop_rxq_idx : _mem_stq_e_T_1_bits_uop_rxq_idx; // @[lsu.scala:911:37, :920:{33,57}, :922:33] wire [5:0] _mem_stq_e_T_2_bits_uop_pdst = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_uop_pdst : _mem_stq_e_T_1_bits_uop_pdst; // @[lsu.scala:911:37, :920:{33,57}, :922:33] wire [5:0] _mem_stq_e_T_2_bits_uop_prs1 = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_uop_prs1 : _mem_stq_e_T_1_bits_uop_prs1; // @[lsu.scala:911:37, :920:{33,57}, :922:33] wire [5:0] _mem_stq_e_T_2_bits_uop_prs2 = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_uop_prs2 : _mem_stq_e_T_1_bits_uop_prs2; // @[lsu.scala:911:37, :920:{33,57}, :922:33] wire [5:0] _mem_stq_e_T_2_bits_uop_prs3 = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_uop_prs3 : _mem_stq_e_T_1_bits_uop_prs3; // @[lsu.scala:911:37, :920:{33,57}, :922:33] wire [3:0] _mem_stq_e_T_2_bits_uop_ppred = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_uop_ppred : _mem_stq_e_T_1_bits_uop_ppred; // @[lsu.scala:911:37, :920:{33,57}, :922:33] wire _mem_stq_e_T_2_bits_uop_prs1_busy = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_uop_prs1_busy : _mem_stq_e_T_1_bits_uop_prs1_busy; // @[lsu.scala:911:37, :920:{33,57}, :922:33] wire _mem_stq_e_T_2_bits_uop_prs2_busy = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_uop_prs2_busy : _mem_stq_e_T_1_bits_uop_prs2_busy; // @[lsu.scala:911:37, :920:{33,57}, :922:33] wire _mem_stq_e_T_2_bits_uop_prs3_busy = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_uop_prs3_busy : _mem_stq_e_T_1_bits_uop_prs3_busy; // @[lsu.scala:911:37, :920:{33,57}, :922:33] wire _mem_stq_e_T_2_bits_uop_ppred_busy = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_uop_ppred_busy : _mem_stq_e_T_1_bits_uop_ppred_busy; // @[lsu.scala:911:37, :920:{33,57}, :922:33] wire [5:0] _mem_stq_e_T_2_bits_uop_stale_pdst = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_uop_stale_pdst : _mem_stq_e_T_1_bits_uop_stale_pdst; // @[lsu.scala:911:37, :920:{33,57}, :922:33] wire _mem_stq_e_T_2_bits_uop_exception = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_uop_exception : _mem_stq_e_T_1_bits_uop_exception; // @[lsu.scala:911:37, :920:{33,57}, :922:33] wire [63:0] _mem_stq_e_T_2_bits_uop_exc_cause = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_uop_exc_cause : _mem_stq_e_T_1_bits_uop_exc_cause; // @[lsu.scala:911:37, :920:{33,57}, :922:33] wire _mem_stq_e_T_2_bits_uop_bypassable = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_uop_bypassable : _mem_stq_e_T_1_bits_uop_bypassable; // @[lsu.scala:911:37, :920:{33,57}, :922:33] wire [4:0] _mem_stq_e_T_2_bits_uop_mem_cmd = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_uop_mem_cmd : _mem_stq_e_T_1_bits_uop_mem_cmd; // @[lsu.scala:911:37, :920:{33,57}, :922:33] wire [1:0] _mem_stq_e_T_2_bits_uop_mem_size = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_uop_mem_size : _mem_stq_e_T_1_bits_uop_mem_size; // @[lsu.scala:911:37, :920:{33,57}, :922:33] wire _mem_stq_e_T_2_bits_uop_mem_signed = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_uop_mem_signed : _mem_stq_e_T_1_bits_uop_mem_signed; // @[lsu.scala:911:37, :920:{33,57}, :922:33] wire _mem_stq_e_T_2_bits_uop_is_fence = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_uop_is_fence : _mem_stq_e_T_1_bits_uop_is_fence; // @[lsu.scala:911:37, :920:{33,57}, :922:33] wire _mem_stq_e_T_2_bits_uop_is_fencei = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_uop_is_fencei : _mem_stq_e_T_1_bits_uop_is_fencei; // @[lsu.scala:911:37, :920:{33,57}, :922:33] wire _mem_stq_e_T_2_bits_uop_is_amo = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_uop_is_amo : _mem_stq_e_T_1_bits_uop_is_amo; // @[lsu.scala:911:37, :920:{33,57}, :922:33] wire _mem_stq_e_T_2_bits_uop_uses_ldq = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_uop_uses_ldq : _mem_stq_e_T_1_bits_uop_uses_ldq; // @[lsu.scala:911:37, :920:{33,57}, :922:33] wire _mem_stq_e_T_2_bits_uop_uses_stq = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_uop_uses_stq : _mem_stq_e_T_1_bits_uop_uses_stq; // @[lsu.scala:911:37, :920:{33,57}, :922:33] wire _mem_stq_e_T_2_bits_uop_is_sys_pc2epc = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_uop_is_sys_pc2epc : _mem_stq_e_T_1_bits_uop_is_sys_pc2epc; // @[lsu.scala:911:37, :920:{33,57}, :922:33] wire _mem_stq_e_T_2_bits_uop_is_unique = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_uop_is_unique : _mem_stq_e_T_1_bits_uop_is_unique; // @[lsu.scala:911:37, :920:{33,57}, :922:33] wire _mem_stq_e_T_2_bits_uop_flush_on_commit = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_uop_flush_on_commit : _mem_stq_e_T_1_bits_uop_flush_on_commit; // @[lsu.scala:911:37, :920:{33,57}, :922:33] wire _mem_stq_e_T_2_bits_uop_ldst_is_rs1 = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_uop_ldst_is_rs1 : _mem_stq_e_T_1_bits_uop_ldst_is_rs1; // @[lsu.scala:911:37, :920:{33,57}, :922:33] wire [5:0] _mem_stq_e_T_2_bits_uop_ldst = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_uop_ldst : _mem_stq_e_T_1_bits_uop_ldst; // @[lsu.scala:911:37, :920:{33,57}, :922:33] wire [5:0] _mem_stq_e_T_2_bits_uop_lrs1 = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_uop_lrs1 : _mem_stq_e_T_1_bits_uop_lrs1; // @[lsu.scala:911:37, :920:{33,57}, :922:33] wire [5:0] _mem_stq_e_T_2_bits_uop_lrs2 = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_uop_lrs2 : _mem_stq_e_T_1_bits_uop_lrs2; // @[lsu.scala:911:37, :920:{33,57}, :922:33] wire [5:0] _mem_stq_e_T_2_bits_uop_lrs3 = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_uop_lrs3 : _mem_stq_e_T_1_bits_uop_lrs3; // @[lsu.scala:911:37, :920:{33,57}, :922:33] wire _mem_stq_e_T_2_bits_uop_ldst_val = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_uop_ldst_val : _mem_stq_e_T_1_bits_uop_ldst_val; // @[lsu.scala:911:37, :920:{33,57}, :922:33] wire [1:0] _mem_stq_e_T_2_bits_uop_dst_rtype = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_uop_dst_rtype : _mem_stq_e_T_1_bits_uop_dst_rtype; // @[lsu.scala:911:37, :920:{33,57}, :922:33] wire [1:0] _mem_stq_e_T_2_bits_uop_lrs1_rtype = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_uop_lrs1_rtype : _mem_stq_e_T_1_bits_uop_lrs1_rtype; // @[lsu.scala:911:37, :920:{33,57}, :922:33] wire [1:0] _mem_stq_e_T_2_bits_uop_lrs2_rtype = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_uop_lrs2_rtype : _mem_stq_e_T_1_bits_uop_lrs2_rtype; // @[lsu.scala:911:37, :920:{33,57}, :922:33] wire _mem_stq_e_T_2_bits_uop_frs3_en = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_uop_frs3_en : _mem_stq_e_T_1_bits_uop_frs3_en; // @[lsu.scala:911:37, :920:{33,57}, :922:33] wire _mem_stq_e_T_2_bits_uop_fp_val = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_uop_fp_val : _mem_stq_e_T_1_bits_uop_fp_val; // @[lsu.scala:911:37, :920:{33,57}, :922:33] wire _mem_stq_e_T_2_bits_uop_fp_single = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_uop_fp_single : _mem_stq_e_T_1_bits_uop_fp_single; // @[lsu.scala:911:37, :920:{33,57}, :922:33] wire _mem_stq_e_T_2_bits_uop_xcpt_pf_if = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_uop_xcpt_pf_if : _mem_stq_e_T_1_bits_uop_xcpt_pf_if; // @[lsu.scala:911:37, :920:{33,57}, :922:33] wire _mem_stq_e_T_2_bits_uop_xcpt_ae_if = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_uop_xcpt_ae_if : _mem_stq_e_T_1_bits_uop_xcpt_ae_if; // @[lsu.scala:911:37, :920:{33,57}, :922:33] wire _mem_stq_e_T_2_bits_uop_xcpt_ma_if = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_uop_xcpt_ma_if : _mem_stq_e_T_1_bits_uop_xcpt_ma_if; // @[lsu.scala:911:37, :920:{33,57}, :922:33] wire _mem_stq_e_T_2_bits_uop_bp_debug_if = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_uop_bp_debug_if : _mem_stq_e_T_1_bits_uop_bp_debug_if; // @[lsu.scala:911:37, :920:{33,57}, :922:33] wire _mem_stq_e_T_2_bits_uop_bp_xcpt_if = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_uop_bp_xcpt_if : _mem_stq_e_T_1_bits_uop_bp_xcpt_if; // @[lsu.scala:911:37, :920:{33,57}, :922:33] wire [1:0] _mem_stq_e_T_2_bits_uop_debug_fsrc = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_uop_debug_fsrc : _mem_stq_e_T_1_bits_uop_debug_fsrc; // @[lsu.scala:911:37, :920:{33,57}, :922:33] wire [1:0] _mem_stq_e_T_2_bits_uop_debug_tsrc = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_uop_debug_tsrc : _mem_stq_e_T_1_bits_uop_debug_tsrc; // @[lsu.scala:911:37, :920:{33,57}, :922:33] wire _mem_stq_e_T_2_bits_addr_valid = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_addr_valid : _mem_stq_e_T_1_bits_addr_valid; // @[lsu.scala:911:37, :920:{33,57}, :922:33] wire [39:0] _mem_stq_e_T_2_bits_addr_bits = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_addr_bits : _mem_stq_e_T_1_bits_addr_bits; // @[lsu.scala:911:37, :920:{33,57}, :922:33] wire _mem_stq_e_T_2_bits_addr_is_virtual = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_addr_is_virtual : _mem_stq_e_T_1_bits_addr_is_virtual; // @[lsu.scala:911:37, :920:{33,57}, :922:33] wire _mem_stq_e_T_2_bits_data_valid = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_data_valid : _mem_stq_e_T_1_bits_data_valid; // @[lsu.scala:911:37, :920:{33,57}, :922:33] wire [63:0] _mem_stq_e_T_2_bits_data_bits = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_data_bits : _mem_stq_e_T_1_bits_data_bits; // @[lsu.scala:911:37, :920:{33,57}, :922:33] wire _mem_stq_e_T_2_bits_committed = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_committed : _mem_stq_e_T_1_bits_committed; // @[lsu.scala:911:37, :920:{33,57}, :922:33] wire _mem_stq_e_T_2_bits_succeeded = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_succeeded : _mem_stq_e_T_1_bits_succeeded; // @[lsu.scala:911:37, :920:{33,57}, :922:33] wire [63:0] _mem_stq_e_T_2_bits_debug_wb_data = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_debug_wb_data : _mem_stq_e_T_1_bits_debug_wb_data; // @[lsu.scala:911:37, :920:{33,57}, :922:33] wire mem_stq_e_0_valid = _mem_stq_e_T_2_valid; // @[lsu.scala:263:49, :920:33] wire [6:0] mem_stq_e_0_bits_uop_uopc = _mem_stq_e_T_2_bits_uop_uopc; // @[lsu.scala:263:49, :920:33] wire [31:0] mem_stq_e_0_bits_uop_inst = _mem_stq_e_T_2_bits_uop_inst; // @[lsu.scala:263:49, :920:33] wire [31:0] mem_stq_e_0_bits_uop_debug_inst = _mem_stq_e_T_2_bits_uop_debug_inst; // @[lsu.scala:263:49, :920:33] wire mem_stq_e_0_bits_uop_is_rvc = _mem_stq_e_T_2_bits_uop_is_rvc; // @[lsu.scala:263:49, :920:33] wire [39:0] mem_stq_e_0_bits_uop_debug_pc = _mem_stq_e_T_2_bits_uop_debug_pc; // @[lsu.scala:263:49, :920:33] wire [2:0] mem_stq_e_0_bits_uop_iq_type = _mem_stq_e_T_2_bits_uop_iq_type; // @[lsu.scala:263:49, :920:33] wire [9:0] mem_stq_e_0_bits_uop_fu_code = _mem_stq_e_T_2_bits_uop_fu_code; // @[lsu.scala:263:49, :920:33] wire [3:0] mem_stq_e_0_bits_uop_ctrl_br_type = _mem_stq_e_T_2_bits_uop_ctrl_br_type; // @[lsu.scala:263:49, :920:33] wire [1:0] mem_stq_e_0_bits_uop_ctrl_op1_sel = _mem_stq_e_T_2_bits_uop_ctrl_op1_sel; // @[lsu.scala:263:49, :920:33] wire [2:0] mem_stq_e_0_bits_uop_ctrl_op2_sel = _mem_stq_e_T_2_bits_uop_ctrl_op2_sel; // @[lsu.scala:263:49, :920:33] wire [2:0] mem_stq_e_0_bits_uop_ctrl_imm_sel = _mem_stq_e_T_2_bits_uop_ctrl_imm_sel; // @[lsu.scala:263:49, :920:33] wire [4:0] mem_stq_e_0_bits_uop_ctrl_op_fcn = _mem_stq_e_T_2_bits_uop_ctrl_op_fcn; // @[lsu.scala:263:49, :920:33] wire mem_stq_e_0_bits_uop_ctrl_fcn_dw = _mem_stq_e_T_2_bits_uop_ctrl_fcn_dw; // @[lsu.scala:263:49, :920:33] wire [2:0] mem_stq_e_0_bits_uop_ctrl_csr_cmd = _mem_stq_e_T_2_bits_uop_ctrl_csr_cmd; // @[lsu.scala:263:49, :920:33] wire mem_stq_e_0_bits_uop_ctrl_is_load = _mem_stq_e_T_2_bits_uop_ctrl_is_load; // @[lsu.scala:263:49, :920:33] wire mem_stq_e_0_bits_uop_ctrl_is_sta = _mem_stq_e_T_2_bits_uop_ctrl_is_sta; // @[lsu.scala:263:49, :920:33] wire mem_stq_e_0_bits_uop_ctrl_is_std = _mem_stq_e_T_2_bits_uop_ctrl_is_std; // @[lsu.scala:263:49, :920:33] wire [1:0] mem_stq_e_0_bits_uop_iw_state = _mem_stq_e_T_2_bits_uop_iw_state; // @[lsu.scala:263:49, :920:33] wire mem_stq_e_0_bits_uop_iw_p1_poisoned = _mem_stq_e_T_2_bits_uop_iw_p1_poisoned; // @[lsu.scala:263:49, :920:33] wire mem_stq_e_0_bits_uop_iw_p2_poisoned = _mem_stq_e_T_2_bits_uop_iw_p2_poisoned; // @[lsu.scala:263:49, :920:33] wire mem_stq_e_0_bits_uop_is_br = _mem_stq_e_T_2_bits_uop_is_br; // @[lsu.scala:263:49, :920:33] wire mem_stq_e_0_bits_uop_is_jalr = _mem_stq_e_T_2_bits_uop_is_jalr; // @[lsu.scala:263:49, :920:33] wire mem_stq_e_0_bits_uop_is_jal = _mem_stq_e_T_2_bits_uop_is_jal; // @[lsu.scala:263:49, :920:33] wire mem_stq_e_0_bits_uop_is_sfb = _mem_stq_e_T_2_bits_uop_is_sfb; // @[lsu.scala:263:49, :920:33] wire [7:0] mem_stq_e_0_bits_uop_br_mask = _mem_stq_e_T_2_bits_uop_br_mask; // @[lsu.scala:263:49, :920:33] wire [2:0] mem_stq_e_0_bits_uop_br_tag = _mem_stq_e_T_2_bits_uop_br_tag; // @[lsu.scala:263:49, :920:33] wire [3:0] mem_stq_e_0_bits_uop_ftq_idx = _mem_stq_e_T_2_bits_uop_ftq_idx; // @[lsu.scala:263:49, :920:33] wire mem_stq_e_0_bits_uop_edge_inst = _mem_stq_e_T_2_bits_uop_edge_inst; // @[lsu.scala:263:49, :920:33] wire [5:0] mem_stq_e_0_bits_uop_pc_lob = _mem_stq_e_T_2_bits_uop_pc_lob; // @[lsu.scala:263:49, :920:33] wire mem_stq_e_0_bits_uop_taken = _mem_stq_e_T_2_bits_uop_taken; // @[lsu.scala:263:49, :920:33] wire [19:0] mem_stq_e_0_bits_uop_imm_packed = _mem_stq_e_T_2_bits_uop_imm_packed; // @[lsu.scala:263:49, :920:33] wire [11:0] mem_stq_e_0_bits_uop_csr_addr = _mem_stq_e_T_2_bits_uop_csr_addr; // @[lsu.scala:263:49, :920:33] wire [4:0] mem_stq_e_0_bits_uop_rob_idx = _mem_stq_e_T_2_bits_uop_rob_idx; // @[lsu.scala:263:49, :920:33] wire [2:0] mem_stq_e_0_bits_uop_ldq_idx = _mem_stq_e_T_2_bits_uop_ldq_idx; // @[lsu.scala:263:49, :920:33] wire [2:0] mem_stq_e_0_bits_uop_stq_idx = _mem_stq_e_T_2_bits_uop_stq_idx; // @[lsu.scala:263:49, :920:33] wire [1:0] mem_stq_e_0_bits_uop_rxq_idx = _mem_stq_e_T_2_bits_uop_rxq_idx; // @[lsu.scala:263:49, :920:33] wire [5:0] mem_stq_e_0_bits_uop_pdst = _mem_stq_e_T_2_bits_uop_pdst; // @[lsu.scala:263:49, :920:33] wire [5:0] mem_stq_e_0_bits_uop_prs1 = _mem_stq_e_T_2_bits_uop_prs1; // @[lsu.scala:263:49, :920:33] wire [5:0] mem_stq_e_0_bits_uop_prs2 = _mem_stq_e_T_2_bits_uop_prs2; // @[lsu.scala:263:49, :920:33] wire [5:0] mem_stq_e_0_bits_uop_prs3 = _mem_stq_e_T_2_bits_uop_prs3; // @[lsu.scala:263:49, :920:33] wire [3:0] mem_stq_e_0_bits_uop_ppred = _mem_stq_e_T_2_bits_uop_ppred; // @[lsu.scala:263:49, :920:33] wire mem_stq_e_0_bits_uop_prs1_busy = _mem_stq_e_T_2_bits_uop_prs1_busy; // @[lsu.scala:263:49, :920:33] wire mem_stq_e_0_bits_uop_prs2_busy = _mem_stq_e_T_2_bits_uop_prs2_busy; // @[lsu.scala:263:49, :920:33] wire mem_stq_e_0_bits_uop_prs3_busy = _mem_stq_e_T_2_bits_uop_prs3_busy; // @[lsu.scala:263:49, :920:33] wire mem_stq_e_0_bits_uop_ppred_busy = _mem_stq_e_T_2_bits_uop_ppred_busy; // @[lsu.scala:263:49, :920:33] wire [5:0] mem_stq_e_0_bits_uop_stale_pdst = _mem_stq_e_T_2_bits_uop_stale_pdst; // @[lsu.scala:263:49, :920:33] wire mem_stq_e_0_bits_uop_exception = _mem_stq_e_T_2_bits_uop_exception; // @[lsu.scala:263:49, :920:33] wire [63:0] mem_stq_e_0_bits_uop_exc_cause = _mem_stq_e_T_2_bits_uop_exc_cause; // @[lsu.scala:263:49, :920:33] wire mem_stq_e_0_bits_uop_bypassable = _mem_stq_e_T_2_bits_uop_bypassable; // @[lsu.scala:263:49, :920:33] wire [4:0] mem_stq_e_0_bits_uop_mem_cmd = _mem_stq_e_T_2_bits_uop_mem_cmd; // @[lsu.scala:263:49, :920:33] wire [1:0] mem_stq_e_0_bits_uop_mem_size = _mem_stq_e_T_2_bits_uop_mem_size; // @[lsu.scala:263:49, :920:33] wire mem_stq_e_0_bits_uop_mem_signed = _mem_stq_e_T_2_bits_uop_mem_signed; // @[lsu.scala:263:49, :920:33] wire mem_stq_e_0_bits_uop_is_fence = _mem_stq_e_T_2_bits_uop_is_fence; // @[lsu.scala:263:49, :920:33] wire mem_stq_e_0_bits_uop_is_fencei = _mem_stq_e_T_2_bits_uop_is_fencei; // @[lsu.scala:263:49, :920:33] wire mem_stq_e_0_bits_uop_is_amo = _mem_stq_e_T_2_bits_uop_is_amo; // @[lsu.scala:263:49, :920:33] wire mem_stq_e_0_bits_uop_uses_ldq = _mem_stq_e_T_2_bits_uop_uses_ldq; // @[lsu.scala:263:49, :920:33] wire mem_stq_e_0_bits_uop_uses_stq = _mem_stq_e_T_2_bits_uop_uses_stq; // @[lsu.scala:263:49, :920:33] wire mem_stq_e_0_bits_uop_is_sys_pc2epc = _mem_stq_e_T_2_bits_uop_is_sys_pc2epc; // @[lsu.scala:263:49, :920:33] wire mem_stq_e_0_bits_uop_is_unique = _mem_stq_e_T_2_bits_uop_is_unique; // @[lsu.scala:263:49, :920:33] wire mem_stq_e_0_bits_uop_flush_on_commit = _mem_stq_e_T_2_bits_uop_flush_on_commit; // @[lsu.scala:263:49, :920:33] wire mem_stq_e_0_bits_uop_ldst_is_rs1 = _mem_stq_e_T_2_bits_uop_ldst_is_rs1; // @[lsu.scala:263:49, :920:33] wire [5:0] mem_stq_e_0_bits_uop_ldst = _mem_stq_e_T_2_bits_uop_ldst; // @[lsu.scala:263:49, :920:33] wire [5:0] mem_stq_e_0_bits_uop_lrs1 = _mem_stq_e_T_2_bits_uop_lrs1; // @[lsu.scala:263:49, :920:33] wire [5:0] mem_stq_e_0_bits_uop_lrs2 = _mem_stq_e_T_2_bits_uop_lrs2; // @[lsu.scala:263:49, :920:33] wire [5:0] mem_stq_e_0_bits_uop_lrs3 = _mem_stq_e_T_2_bits_uop_lrs3; // @[lsu.scala:263:49, :920:33] wire mem_stq_e_0_bits_uop_ldst_val = _mem_stq_e_T_2_bits_uop_ldst_val; // @[lsu.scala:263:49, :920:33] wire [1:0] mem_stq_e_0_bits_uop_dst_rtype = _mem_stq_e_T_2_bits_uop_dst_rtype; // @[lsu.scala:263:49, :920:33] wire [1:0] mem_stq_e_0_bits_uop_lrs1_rtype = _mem_stq_e_T_2_bits_uop_lrs1_rtype; // @[lsu.scala:263:49, :920:33] wire [1:0] mem_stq_e_0_bits_uop_lrs2_rtype = _mem_stq_e_T_2_bits_uop_lrs2_rtype; // @[lsu.scala:263:49, :920:33] wire mem_stq_e_0_bits_uop_frs3_en = _mem_stq_e_T_2_bits_uop_frs3_en; // @[lsu.scala:263:49, :920:33] wire mem_stq_e_0_bits_uop_fp_val = _mem_stq_e_T_2_bits_uop_fp_val; // @[lsu.scala:263:49, :920:33] wire mem_stq_e_0_bits_uop_fp_single = _mem_stq_e_T_2_bits_uop_fp_single; // @[lsu.scala:263:49, :920:33] wire mem_stq_e_0_bits_uop_xcpt_pf_if = _mem_stq_e_T_2_bits_uop_xcpt_pf_if; // @[lsu.scala:263:49, :920:33] wire mem_stq_e_0_bits_uop_xcpt_ae_if = _mem_stq_e_T_2_bits_uop_xcpt_ae_if; // @[lsu.scala:263:49, :920:33] wire mem_stq_e_0_bits_uop_xcpt_ma_if = _mem_stq_e_T_2_bits_uop_xcpt_ma_if; // @[lsu.scala:263:49, :920:33] wire mem_stq_e_0_bits_uop_bp_debug_if = _mem_stq_e_T_2_bits_uop_bp_debug_if; // @[lsu.scala:263:49, :920:33] wire mem_stq_e_0_bits_uop_bp_xcpt_if = _mem_stq_e_T_2_bits_uop_bp_xcpt_if; // @[lsu.scala:263:49, :920:33] wire [1:0] mem_stq_e_0_bits_uop_debug_fsrc = _mem_stq_e_T_2_bits_uop_debug_fsrc; // @[lsu.scala:263:49, :920:33] wire [1:0] mem_stq_e_0_bits_uop_debug_tsrc = _mem_stq_e_T_2_bits_uop_debug_tsrc; // @[lsu.scala:263:49, :920:33] wire mem_stq_e_0_bits_addr_valid = _mem_stq_e_T_2_bits_addr_valid; // @[lsu.scala:263:49, :920:33] wire [39:0] mem_stq_e_0_bits_addr_bits = _mem_stq_e_T_2_bits_addr_bits; // @[lsu.scala:263:49, :920:33] wire mem_stq_e_0_bits_addr_is_virtual = _mem_stq_e_T_2_bits_addr_is_virtual; // @[lsu.scala:263:49, :920:33] wire mem_stq_e_0_bits_data_valid = _mem_stq_e_T_2_bits_data_valid; // @[lsu.scala:263:49, :920:33] wire [63:0] mem_stq_e_0_bits_data_bits = _mem_stq_e_T_2_bits_data_bits; // @[lsu.scala:263:49, :920:33] wire mem_stq_e_0_bits_committed = _mem_stq_e_T_2_bits_committed; // @[lsu.scala:263:49, :920:33] wire mem_stq_e_0_bits_succeeded = _mem_stq_e_T_2_bits_succeeded; // @[lsu.scala:263:49, :920:33] wire [63:0] mem_stq_e_0_bits_debug_wb_data = _mem_stq_e_T_2_bits_debug_wb_data; // @[lsu.scala:263:49, :920:33] wire [7:0] _mem_stdf_uop_out_br_mask_T_1; // @[util.scala:85:25] wire [7:0] mem_stdf_uop_out_br_mask; // @[util.scala:96:23] wire [7:0] _mem_stdf_uop_out_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:85:27] assign _mem_stdf_uop_out_br_mask_T_1 = io_core_fp_stdata_bits_uop_br_mask_0 & _mem_stdf_uop_out_br_mask_T; // @[util.scala:85:{25,27}] assign mem_stdf_uop_out_br_mask = _mem_stdf_uop_out_br_mask_T_1; // @[util.scala:85:25, :96:23] reg [6:0] mem_stdf_uop_uopc; // @[lsu.scala:923:37] reg [31:0] mem_stdf_uop_inst; // @[lsu.scala:923:37] reg [31:0] mem_stdf_uop_debug_inst; // @[lsu.scala:923:37] reg mem_stdf_uop_is_rvc; // @[lsu.scala:923:37] reg [39:0] mem_stdf_uop_debug_pc; // @[lsu.scala:923:37] reg [2:0] mem_stdf_uop_iq_type; // @[lsu.scala:923:37] reg [9:0] mem_stdf_uop_fu_code; // @[lsu.scala:923:37] reg [3:0] mem_stdf_uop_ctrl_br_type; // @[lsu.scala:923:37] reg [1:0] mem_stdf_uop_ctrl_op1_sel; // @[lsu.scala:923:37] reg [2:0] mem_stdf_uop_ctrl_op2_sel; // @[lsu.scala:923:37] reg [2:0] mem_stdf_uop_ctrl_imm_sel; // @[lsu.scala:923:37] reg [4:0] mem_stdf_uop_ctrl_op_fcn; // @[lsu.scala:923:37] reg mem_stdf_uop_ctrl_fcn_dw; // @[lsu.scala:923:37] reg [2:0] mem_stdf_uop_ctrl_csr_cmd; // @[lsu.scala:923:37] reg mem_stdf_uop_ctrl_is_load; // @[lsu.scala:923:37] reg mem_stdf_uop_ctrl_is_sta; // @[lsu.scala:923:37] reg mem_stdf_uop_ctrl_is_std; // @[lsu.scala:923:37] reg [1:0] mem_stdf_uop_iw_state; // @[lsu.scala:923:37] reg mem_stdf_uop_iw_p1_poisoned; // @[lsu.scala:923:37] reg mem_stdf_uop_iw_p2_poisoned; // @[lsu.scala:923:37] reg mem_stdf_uop_is_br; // @[lsu.scala:923:37] reg mem_stdf_uop_is_jalr; // @[lsu.scala:923:37] reg mem_stdf_uop_is_jal; // @[lsu.scala:923:37] reg mem_stdf_uop_is_sfb; // @[lsu.scala:923:37] reg [7:0] mem_stdf_uop_br_mask; // @[lsu.scala:923:37] reg [2:0] mem_stdf_uop_br_tag; // @[lsu.scala:923:37] reg [3:0] mem_stdf_uop_ftq_idx; // @[lsu.scala:923:37] reg mem_stdf_uop_edge_inst; // @[lsu.scala:923:37] reg [5:0] mem_stdf_uop_pc_lob; // @[lsu.scala:923:37] reg mem_stdf_uop_taken; // @[lsu.scala:923:37] reg [19:0] mem_stdf_uop_imm_packed; // @[lsu.scala:923:37] reg [11:0] mem_stdf_uop_csr_addr; // @[lsu.scala:923:37] reg [4:0] mem_stdf_uop_rob_idx; // @[lsu.scala:923:37] reg [2:0] mem_stdf_uop_ldq_idx; // @[lsu.scala:923:37] reg [2:0] mem_stdf_uop_stq_idx; // @[lsu.scala:923:37] reg [1:0] mem_stdf_uop_rxq_idx; // @[lsu.scala:923:37] reg [5:0] mem_stdf_uop_pdst; // @[lsu.scala:923:37] reg [5:0] mem_stdf_uop_prs1; // @[lsu.scala:923:37] reg [5:0] mem_stdf_uop_prs2; // @[lsu.scala:923:37] reg [5:0] mem_stdf_uop_prs3; // @[lsu.scala:923:37] reg [3:0] mem_stdf_uop_ppred; // @[lsu.scala:923:37] reg mem_stdf_uop_prs1_busy; // @[lsu.scala:923:37] reg mem_stdf_uop_prs2_busy; // @[lsu.scala:923:37] reg mem_stdf_uop_prs3_busy; // @[lsu.scala:923:37] reg mem_stdf_uop_ppred_busy; // @[lsu.scala:923:37] reg [5:0] mem_stdf_uop_stale_pdst; // @[lsu.scala:923:37] reg mem_stdf_uop_exception; // @[lsu.scala:923:37] reg [63:0] mem_stdf_uop_exc_cause; // @[lsu.scala:923:37] reg mem_stdf_uop_bypassable; // @[lsu.scala:923:37] reg [4:0] mem_stdf_uop_mem_cmd; // @[lsu.scala:923:37] reg [1:0] mem_stdf_uop_mem_size; // @[lsu.scala:923:37] reg mem_stdf_uop_mem_signed; // @[lsu.scala:923:37] reg mem_stdf_uop_is_fence; // @[lsu.scala:923:37] reg mem_stdf_uop_is_fencei; // @[lsu.scala:923:37] reg mem_stdf_uop_is_amo; // @[lsu.scala:923:37] reg mem_stdf_uop_uses_ldq; // @[lsu.scala:923:37] reg mem_stdf_uop_uses_stq; // @[lsu.scala:923:37] reg mem_stdf_uop_is_sys_pc2epc; // @[lsu.scala:923:37] reg mem_stdf_uop_is_unique; // @[lsu.scala:923:37] reg mem_stdf_uop_flush_on_commit; // @[lsu.scala:923:37] reg mem_stdf_uop_ldst_is_rs1; // @[lsu.scala:923:37] reg [5:0] mem_stdf_uop_ldst; // @[lsu.scala:923:37] reg [5:0] mem_stdf_uop_lrs1; // @[lsu.scala:923:37] reg [5:0] mem_stdf_uop_lrs2; // @[lsu.scala:923:37] reg [5:0] mem_stdf_uop_lrs3; // @[lsu.scala:923:37] reg mem_stdf_uop_ldst_val; // @[lsu.scala:923:37] reg [1:0] mem_stdf_uop_dst_rtype; // @[lsu.scala:923:37] reg [1:0] mem_stdf_uop_lrs1_rtype; // @[lsu.scala:923:37] reg [1:0] mem_stdf_uop_lrs2_rtype; // @[lsu.scala:923:37] reg mem_stdf_uop_frs3_en; // @[lsu.scala:923:37] reg mem_stdf_uop_fp_val; // @[lsu.scala:923:37] reg mem_stdf_uop_fp_single; // @[lsu.scala:923:37] reg mem_stdf_uop_xcpt_pf_if; // @[lsu.scala:923:37] reg mem_stdf_uop_xcpt_ae_if; // @[lsu.scala:923:37] reg mem_stdf_uop_xcpt_ma_if; // @[lsu.scala:923:37] reg mem_stdf_uop_bp_debug_if; // @[lsu.scala:923:37] reg mem_stdf_uop_bp_xcpt_if; // @[lsu.scala:923:37] reg [1:0] mem_stdf_uop_debug_fsrc; // @[lsu.scala:923:37] reg [1:0] mem_stdf_uop_debug_tsrc; // @[lsu.scala:923:37] reg mem_tlb_miss_0; // @[lsu.scala:926:41] reg mem_tlb_uncacheable_0; // @[lsu.scala:927:41] reg [39:0] mem_paddr_0; // @[lsu.scala:928:41] reg clr_bsy_valid_0; // @[lsu.scala:931:32] reg [4:0] clr_bsy_rob_idx_0; // @[lsu.scala:932:28] assign io_core_clr_bsy_0_bits_0 = clr_bsy_rob_idx_0; // @[lsu.scala:201:7, :932:28] reg [7:0] clr_bsy_brmask_0; // @[lsu.scala:933:28] wire _clr_bsy_valid_0_T = ~mem_tlb_miss_0; // @[lsu.scala:926:41, :943:29] wire _clr_bsy_valid_0_T_1 = mem_stq_incoming_e_0_valid & _clr_bsy_valid_0_T; // @[lsu.scala:911:37, :942:68, :943:29] wire _clr_bsy_valid_0_T_2 = ~mem_stq_incoming_e_0_bits_uop_is_amo; // @[lsu.scala:911:37, :944:29] wire _clr_bsy_valid_0_T_3 = _clr_bsy_valid_0_T_1 & _clr_bsy_valid_0_T_2; // @[lsu.scala:942:68, :943:68, :944:29] wire [7:0] _GEN_227 = io_core_brupdate_b1_mispredict_mask_0 & mem_stq_incoming_e_0_bits_uop_br_mask; // @[util.scala:118:51] wire [7:0] _clr_bsy_valid_0_T_4; // @[util.scala:118:51] assign _clr_bsy_valid_0_T_4 = _GEN_227; // @[util.scala:118:51] wire [7:0] _clr_bsy_valid_0_T_13; // @[util.scala:118:51] assign _clr_bsy_valid_0_T_13 = _GEN_227; // @[util.scala:118:51] wire [7:0] _clr_bsy_valid_0_T_22; // @[util.scala:118:51] assign _clr_bsy_valid_0_T_22 = _GEN_227; // @[util.scala:118:51] wire _clr_bsy_valid_0_T_5 = |_clr_bsy_valid_0_T_4; // @[util.scala:118:{51,59}] wire _clr_bsy_valid_0_T_6 = ~_clr_bsy_valid_0_T_5; // @[util.scala:118:59] wire _clr_bsy_valid_0_T_7 = _clr_bsy_valid_0_T_3 & _clr_bsy_valid_0_T_6; // @[lsu.scala:943:68, :944:68, :945:29] wire [7:0] _clr_bsy_brmask_0_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:85:27] wire [7:0] _clr_bsy_brmask_0_T_1 = mem_stq_incoming_e_0_bits_uop_br_mask & _clr_bsy_brmask_0_T; // @[util.scala:85:{25,27}] wire _clr_bsy_valid_0_T_8 = mem_stq_incoming_e_0_valid & mem_stq_incoming_e_0_bits_data_valid; // @[lsu.scala:911:37, :949:69] wire _clr_bsy_valid_0_T_9 = ~mem_tlb_miss_0; // @[lsu.scala:926:41, :943:29, :951:29] wire _clr_bsy_valid_0_T_10 = _clr_bsy_valid_0_T_8 & _clr_bsy_valid_0_T_9; // @[lsu.scala:949:69, :950:69, :951:29] wire _clr_bsy_valid_0_T_11 = ~mem_stq_incoming_e_0_bits_uop_is_amo; // @[lsu.scala:911:37, :944:29, :952:29] wire _clr_bsy_valid_0_T_12 = _clr_bsy_valid_0_T_10 & _clr_bsy_valid_0_T_11; // @[lsu.scala:950:69, :951:69, :952:29] wire _clr_bsy_valid_0_T_14 = |_clr_bsy_valid_0_T_13; // @[util.scala:118:{51,59}] wire _clr_bsy_valid_0_T_15 = ~_clr_bsy_valid_0_T_14; // @[util.scala:118:59] wire _clr_bsy_valid_0_T_16 = _clr_bsy_valid_0_T_12 & _clr_bsy_valid_0_T_15; // @[lsu.scala:951:69, :952:69, :953:29] wire [7:0] _clr_bsy_brmask_0_T_2 = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:85:27] wire [7:0] _clr_bsy_brmask_0_T_3 = mem_stq_incoming_e_0_bits_uop_br_mask & _clr_bsy_brmask_0_T_2; // @[util.scala:85:{25,27}] wire _clr_bsy_valid_0_T_17 = mem_stq_incoming_e_0_valid & mem_stq_incoming_e_0_bits_addr_valid; // @[lsu.scala:911:37, :957:74] wire _clr_bsy_valid_0_T_18 = ~mem_stq_incoming_e_0_bits_addr_is_virtual; // @[lsu.scala:911:37, :959:29] wire _clr_bsy_valid_0_T_19 = _clr_bsy_valid_0_T_17 & _clr_bsy_valid_0_T_18; // @[lsu.scala:957:74, :958:74, :959:29] wire _clr_bsy_valid_0_T_20 = ~mem_stq_incoming_e_0_bits_uop_is_amo; // @[lsu.scala:911:37, :944:29, :960:29] wire _clr_bsy_valid_0_T_21 = _clr_bsy_valid_0_T_19 & _clr_bsy_valid_0_T_20; // @[lsu.scala:958:74, :959:74, :960:29] wire _clr_bsy_valid_0_T_23 = |_clr_bsy_valid_0_T_22; // @[util.scala:118:{51,59}] wire _clr_bsy_valid_0_T_24 = ~_clr_bsy_valid_0_T_23; // @[util.scala:118:59] wire _clr_bsy_valid_0_T_25 = _clr_bsy_valid_0_T_21 & _clr_bsy_valid_0_T_24; // @[lsu.scala:959:74, :960:74, :961:29] wire [7:0] _clr_bsy_brmask_0_T_4 = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:85:27] wire [7:0] _clr_bsy_brmask_0_T_5 = mem_stq_incoming_e_0_bits_uop_br_mask & _clr_bsy_brmask_0_T_4; // @[util.scala:85:{25,27}] wire [7:0] _clr_bsy_brmask_0_T_6 = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:85:27] wire [7:0] _clr_bsy_brmask_0_T_7 = mem_incoming_uop_0_br_mask & _clr_bsy_brmask_0_T_6; // @[util.scala:85:{25,27}] wire _clr_bsy_valid_0_T_26 = mem_stq_retry_e_valid & mem_stq_retry_e_bits_data_valid; // @[lsu.scala:914:37, :969:63] wire _clr_bsy_valid_0_T_27 = ~mem_tlb_miss_0; // @[lsu.scala:926:41, :943:29, :971:29] wire _clr_bsy_valid_0_T_28 = _clr_bsy_valid_0_T_26 & _clr_bsy_valid_0_T_27; // @[lsu.scala:969:63, :970:63, :971:29] wire _clr_bsy_valid_0_T_29 = ~mem_stq_retry_e_bits_uop_is_amo; // @[lsu.scala:914:37, :972:29] wire _clr_bsy_valid_0_T_30 = _clr_bsy_valid_0_T_28 & _clr_bsy_valid_0_T_29; // @[lsu.scala:970:63, :971:63, :972:29] wire [7:0] _clr_bsy_valid_0_T_31 = io_core_brupdate_b1_mispredict_mask_0 & mem_stq_retry_e_bits_uop_br_mask; // @[util.scala:118:51] wire _clr_bsy_valid_0_T_32 = |_clr_bsy_valid_0_T_31; // @[util.scala:118:{51,59}] wire _clr_bsy_valid_0_T_33 = ~_clr_bsy_valid_0_T_32; // @[util.scala:118:59] wire _clr_bsy_valid_0_T_34 = _clr_bsy_valid_0_T_30 & _clr_bsy_valid_0_T_33; // @[lsu.scala:971:63, :972:63, :973:29] wire [7:0] _clr_bsy_brmask_0_T_8 = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:85:27] wire [7:0] _clr_bsy_brmask_0_T_9 = mem_stq_retry_e_bits_uop_br_mask & _clr_bsy_brmask_0_T_8; // @[util.scala:85:{25,27}] wire [7:0] _io_core_clr_bsy_0_valid_T = io_core_brupdate_b1_mispredict_mask_0 & clr_bsy_brmask_0; // @[util.scala:118:51] wire _io_core_clr_bsy_0_valid_T_1 = |_io_core_clr_bsy_0_valid_T; // @[util.scala:118:{51,59}] wire _io_core_clr_bsy_0_valid_T_2 = ~_io_core_clr_bsy_0_valid_T_1; // @[util.scala:118:59] wire _io_core_clr_bsy_0_valid_T_3 = clr_bsy_valid_0 & _io_core_clr_bsy_0_valid_T_2; // @[lsu.scala:931:32, :978:50, :979:32] wire _io_core_clr_bsy_0_valid_T_4 = ~io_core_exception_0; // @[lsu.scala:201:7, :670:22, :980:32] wire _io_core_clr_bsy_0_valid_T_5 = _io_core_clr_bsy_0_valid_T_3 & _io_core_clr_bsy_0_valid_T_4; // @[lsu.scala:978:50, :979:87, :980:32] reg io_core_clr_bsy_0_valid_REG; // @[lsu.scala:980:62] wire _io_core_clr_bsy_0_valid_T_6 = ~io_core_clr_bsy_0_valid_REG; // @[lsu.scala:980:{54,62}] wire _io_core_clr_bsy_0_valid_T_7 = _io_core_clr_bsy_0_valid_T_5 & _io_core_clr_bsy_0_valid_T_6; // @[lsu.scala:979:87, :980:{51,54}] reg io_core_clr_bsy_0_valid_REG_1; // @[lsu.scala:980:101] reg io_core_clr_bsy_0_valid_REG_2; // @[lsu.scala:980:93] wire _io_core_clr_bsy_0_valid_T_8 = ~io_core_clr_bsy_0_valid_REG_2; // @[lsu.scala:980:{85,93}] assign _io_core_clr_bsy_0_valid_T_9 = _io_core_clr_bsy_0_valid_T_7 & _io_core_clr_bsy_0_valid_T_8; // @[lsu.scala:980:{51,82,85}] assign io_core_clr_bsy_0_valid_0 = _io_core_clr_bsy_0_valid_T_9; // @[lsu.scala:201:7, :980:82] reg stdf_clr_bsy_valid; // @[lsu.scala:984:37] reg [4:0] stdf_clr_bsy_rob_idx; // @[lsu.scala:985:33] assign io_core_clr_bsy_1_bits_0 = stdf_clr_bsy_rob_idx; // @[lsu.scala:201:7, :985:33] reg [7:0] stdf_clr_bsy_brmask; // @[lsu.scala:986:33] wire _stdf_clr_bsy_valid_T = _GEN[mem_stdf_uop_stq_idx] & _GEN_83[mem_stdf_uop_stq_idx]; // @[lsu.scala:222:42, :923:37, :992:62] wire _stdf_clr_bsy_valid_T_1 = ~_GEN_85[mem_stdf_uop_stq_idx]; // @[lsu.scala:222:42, :923:37, :992:62, :994:29] wire _stdf_clr_bsy_valid_T_2 = _stdf_clr_bsy_valid_T & _stdf_clr_bsy_valid_T_1; // @[lsu.scala:992:62, :993:62, :994:29] wire _stdf_clr_bsy_valid_T_3 = ~_GEN_57[mem_stdf_uop_stq_idx]; // @[lsu.scala:222:42, :923:37, :992:62, :995:29] wire _stdf_clr_bsy_valid_T_4 = _stdf_clr_bsy_valid_T_2 & _stdf_clr_bsy_valid_T_3; // @[lsu.scala:993:62, :994:62, :995:29] wire [7:0] _stdf_clr_bsy_valid_T_5 = io_core_brupdate_b1_mispredict_mask_0 & mem_stdf_uop_br_mask; // @[util.scala:118:51] wire _stdf_clr_bsy_valid_T_6 = |_stdf_clr_bsy_valid_T_5; // @[util.scala:118:{51,59}] wire _stdf_clr_bsy_valid_T_7 = ~_stdf_clr_bsy_valid_T_6; // @[util.scala:118:59] wire _stdf_clr_bsy_valid_T_8 = _stdf_clr_bsy_valid_T_4 & _stdf_clr_bsy_valid_T_7; // @[lsu.scala:994:62, :995:62, :996:29] wire [7:0] _stdf_clr_bsy_brmask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:85:27] wire [7:0] _stdf_clr_bsy_brmask_T_1 = mem_stdf_uop_br_mask & _stdf_clr_bsy_brmask_T; // @[util.scala:85:{25,27}] wire [7:0] _io_core_clr_bsy_1_valid_T = io_core_brupdate_b1_mispredict_mask_0 & stdf_clr_bsy_brmask; // @[util.scala:118:51] wire _io_core_clr_bsy_1_valid_T_1 = |_io_core_clr_bsy_1_valid_T; // @[util.scala:118:{51,59}] wire _io_core_clr_bsy_1_valid_T_2 = ~_io_core_clr_bsy_1_valid_T_1; // @[util.scala:118:59] wire _io_core_clr_bsy_1_valid_T_3 = stdf_clr_bsy_valid & _io_core_clr_bsy_1_valid_T_2; // @[lsu.scala:984:37, :1003:57, :1004:37] wire _io_core_clr_bsy_1_valid_T_4 = ~io_core_exception_0; // @[lsu.scala:201:7, :670:22, :1005:37] wire _io_core_clr_bsy_1_valid_T_5 = _io_core_clr_bsy_1_valid_T_3 & _io_core_clr_bsy_1_valid_T_4; // @[lsu.scala:1003:57, :1004:94, :1005:37] reg io_core_clr_bsy_1_valid_REG; // @[lsu.scala:1005:67] wire _io_core_clr_bsy_1_valid_T_6 = ~io_core_clr_bsy_1_valid_REG; // @[lsu.scala:1005:{59,67}] wire _io_core_clr_bsy_1_valid_T_7 = _io_core_clr_bsy_1_valid_T_5 & _io_core_clr_bsy_1_valid_T_6; // @[lsu.scala:1004:94, :1005:{56,59}] reg io_core_clr_bsy_1_valid_REG_1; // @[lsu.scala:1005:106] reg io_core_clr_bsy_1_valid_REG_2; // @[lsu.scala:1005:98] wire _io_core_clr_bsy_1_valid_T_8 = ~io_core_clr_bsy_1_valid_REG_2; // @[lsu.scala:1005:{90,98}] assign _io_core_clr_bsy_1_valid_T_9 = _io_core_clr_bsy_1_valid_T_7 & _io_core_clr_bsy_1_valid_T_8; // @[lsu.scala:1005:{56,87,90}] assign io_core_clr_bsy_1_valid_0 = _io_core_clr_bsy_1_valid_T_9; // @[lsu.scala:201:7, :1005:87] wire _do_st_search_T_1 = _do_st_search_T | fired_sta_retry_0; // @[lsu.scala:263:49, :1015:{60,85}] wire _do_st_search_T_2 = ~mem_tlb_miss_0; // @[lsu.scala:926:41, :943:29, :1015:111] wire _do_st_search_T_3 = _do_st_search_T_1 & _do_st_search_T_2; // @[lsu.scala:1015:{85,108,111}] wire do_st_search_0 = _do_st_search_T_3; // @[lsu.scala:263:49, :1015:108] wire _GEN_228 = fired_load_incoming_0 | fired_load_retry_0; // @[lsu.scala:263:49, :1017:61] wire _do_ld_search_T; // @[lsu.scala:1017:61] assign _do_ld_search_T = _GEN_228; // @[lsu.scala:1017:61] wire _can_forward_T; // @[lsu.scala:1046:32] assign _can_forward_T = _GEN_228; // @[lsu.scala:1017:61, :1046:32] wire _do_ld_search_T_1 = ~mem_tlb_miss_0; // @[lsu.scala:926:41, :943:29, :1017:88] wire _do_ld_search_T_2 = _do_ld_search_T & _do_ld_search_T_1; // @[lsu.scala:1017:{61,85,88}] wire _do_ld_search_T_3 = _do_ld_search_T_2 | fired_load_wakeup_0; // @[lsu.scala:263:49, :1017:{85,106}] wire do_ld_search_0 = _do_ld_search_T_3; // @[lsu.scala:263:49, :1017:106] wire _lcam_addr_T_1 = _lcam_addr_T | fired_sta_retry_0; // @[lsu.scala:263:49, :1026:{61,86}] reg [31:0] lcam_addr_REG; // @[lsu.scala:1027:45] reg [31:0] lcam_addr_REG_1; // @[lsu.scala:1028:67] wire [39:0] _lcam_addr_T_2 = fired_release_0 ? {8'h0, lcam_addr_REG_1} : mem_paddr_0; // @[lsu.scala:901:37, :928:41, :1028:{41,67}] wire [39:0] _lcam_addr_T_3 = _lcam_addr_T_1 ? {8'h0, lcam_addr_REG} : _lcam_addr_T_2; // @[lsu.scala:1026:{37,86}, :1027:45, :1028:41] wire [39:0] lcam_addr_0 = _lcam_addr_T_3; // @[lsu.scala:263:49, :1026:37] wire [6:0] _lcam_uop_T_uopc = do_ld_search_0 ? mem_ldq_e_0_bits_uop_uopc : 7'h0; // @[lsu.scala:263:49, :1031:37] wire [31:0] _lcam_uop_T_inst = do_ld_search_0 ? mem_ldq_e_0_bits_uop_inst : 32'h0; // @[lsu.scala:263:49, :1031:37] wire [31:0] _lcam_uop_T_debug_inst = do_ld_search_0 ? mem_ldq_e_0_bits_uop_debug_inst : 32'h0; // @[lsu.scala:263:49, :1031:37] wire _lcam_uop_T_is_rvc = do_ld_search_0 & mem_ldq_e_0_bits_uop_is_rvc; // @[lsu.scala:263:49, :1031:37] wire [39:0] _lcam_uop_T_debug_pc = do_ld_search_0 ? mem_ldq_e_0_bits_uop_debug_pc : 40'h0; // @[lsu.scala:263:49, :1031:37] wire [2:0] _lcam_uop_T_iq_type = do_ld_search_0 ? mem_ldq_e_0_bits_uop_iq_type : 3'h0; // @[lsu.scala:263:49, :1031:37] wire [9:0] _lcam_uop_T_fu_code = do_ld_search_0 ? mem_ldq_e_0_bits_uop_fu_code : 10'h0; // @[lsu.scala:263:49, :1031:37] wire [3:0] _lcam_uop_T_ctrl_br_type = do_ld_search_0 ? mem_ldq_e_0_bits_uop_ctrl_br_type : 4'h0; // @[lsu.scala:263:49, :1031:37] wire [1:0] _lcam_uop_T_ctrl_op1_sel = do_ld_search_0 ? mem_ldq_e_0_bits_uop_ctrl_op1_sel : 2'h0; // @[lsu.scala:263:49, :1031:37] wire [2:0] _lcam_uop_T_ctrl_op2_sel = do_ld_search_0 ? mem_ldq_e_0_bits_uop_ctrl_op2_sel : 3'h0; // @[lsu.scala:263:49, :1031:37] wire [2:0] _lcam_uop_T_ctrl_imm_sel = do_ld_search_0 ? mem_ldq_e_0_bits_uop_ctrl_imm_sel : 3'h0; // @[lsu.scala:263:49, :1031:37] wire [4:0] _lcam_uop_T_ctrl_op_fcn = do_ld_search_0 ? mem_ldq_e_0_bits_uop_ctrl_op_fcn : 5'h0; // @[lsu.scala:263:49, :1031:37] wire _lcam_uop_T_ctrl_fcn_dw = do_ld_search_0 & mem_ldq_e_0_bits_uop_ctrl_fcn_dw; // @[lsu.scala:263:49, :1031:37] wire [2:0] _lcam_uop_T_ctrl_csr_cmd = do_ld_search_0 ? mem_ldq_e_0_bits_uop_ctrl_csr_cmd : 3'h0; // @[lsu.scala:263:49, :1031:37] wire _lcam_uop_T_ctrl_is_load = do_ld_search_0 & mem_ldq_e_0_bits_uop_ctrl_is_load; // @[lsu.scala:263:49, :1031:37] wire _lcam_uop_T_ctrl_is_sta = do_ld_search_0 & mem_ldq_e_0_bits_uop_ctrl_is_sta; // @[lsu.scala:263:49, :1031:37] wire _lcam_uop_T_ctrl_is_std = do_ld_search_0 & mem_ldq_e_0_bits_uop_ctrl_is_std; // @[lsu.scala:263:49, :1031:37] wire [1:0] _lcam_uop_T_iw_state = do_ld_search_0 ? mem_ldq_e_0_bits_uop_iw_state : 2'h0; // @[lsu.scala:263:49, :1031:37] wire _lcam_uop_T_iw_p1_poisoned = do_ld_search_0 & mem_ldq_e_0_bits_uop_iw_p1_poisoned; // @[lsu.scala:263:49, :1031:37] wire _lcam_uop_T_iw_p2_poisoned = do_ld_search_0 & mem_ldq_e_0_bits_uop_iw_p2_poisoned; // @[lsu.scala:263:49, :1031:37] wire _lcam_uop_T_is_br = do_ld_search_0 & mem_ldq_e_0_bits_uop_is_br; // @[lsu.scala:263:49, :1031:37] wire _lcam_uop_T_is_jalr = do_ld_search_0 & mem_ldq_e_0_bits_uop_is_jalr; // @[lsu.scala:263:49, :1031:37] wire _lcam_uop_T_is_jal = do_ld_search_0 & mem_ldq_e_0_bits_uop_is_jal; // @[lsu.scala:263:49, :1031:37] wire _lcam_uop_T_is_sfb = do_ld_search_0 & mem_ldq_e_0_bits_uop_is_sfb; // @[lsu.scala:263:49, :1031:37] wire [7:0] _lcam_uop_T_br_mask = do_ld_search_0 ? mem_ldq_e_0_bits_uop_br_mask : 8'h0; // @[lsu.scala:263:49, :1031:37] wire [2:0] _lcam_uop_T_br_tag = do_ld_search_0 ? mem_ldq_e_0_bits_uop_br_tag : 3'h0; // @[lsu.scala:263:49, :1031:37] wire [3:0] _lcam_uop_T_ftq_idx = do_ld_search_0 ? mem_ldq_e_0_bits_uop_ftq_idx : 4'h0; // @[lsu.scala:263:49, :1031:37] wire _lcam_uop_T_edge_inst = do_ld_search_0 & mem_ldq_e_0_bits_uop_edge_inst; // @[lsu.scala:263:49, :1031:37] wire [5:0] _lcam_uop_T_pc_lob = do_ld_search_0 ? mem_ldq_e_0_bits_uop_pc_lob : 6'h0; // @[lsu.scala:263:49, :1031:37] wire _lcam_uop_T_taken = do_ld_search_0 & mem_ldq_e_0_bits_uop_taken; // @[lsu.scala:263:49, :1031:37] wire [19:0] _lcam_uop_T_imm_packed = do_ld_search_0 ? mem_ldq_e_0_bits_uop_imm_packed : 20'h0; // @[lsu.scala:263:49, :1031:37] wire [11:0] _lcam_uop_T_csr_addr = do_ld_search_0 ? mem_ldq_e_0_bits_uop_csr_addr : 12'h0; // @[lsu.scala:263:49, :1031:37] wire [4:0] _lcam_uop_T_rob_idx = do_ld_search_0 ? mem_ldq_e_0_bits_uop_rob_idx : 5'h0; // @[lsu.scala:263:49, :1031:37] wire [2:0] _lcam_uop_T_ldq_idx = do_ld_search_0 ? mem_ldq_e_0_bits_uop_ldq_idx : 3'h0; // @[lsu.scala:263:49, :1031:37] wire [2:0] _lcam_uop_T_stq_idx = do_ld_search_0 ? mem_ldq_e_0_bits_uop_stq_idx : 3'h0; // @[lsu.scala:263:49, :1031:37] wire [1:0] _lcam_uop_T_rxq_idx = do_ld_search_0 ? mem_ldq_e_0_bits_uop_rxq_idx : 2'h0; // @[lsu.scala:263:49, :1031:37] wire [5:0] _lcam_uop_T_pdst = do_ld_search_0 ? mem_ldq_e_0_bits_uop_pdst : 6'h0; // @[lsu.scala:263:49, :1031:37] wire [5:0] _lcam_uop_T_prs1 = do_ld_search_0 ? mem_ldq_e_0_bits_uop_prs1 : 6'h0; // @[lsu.scala:263:49, :1031:37] wire [5:0] _lcam_uop_T_prs2 = do_ld_search_0 ? mem_ldq_e_0_bits_uop_prs2 : 6'h0; // @[lsu.scala:263:49, :1031:37] wire [5:0] _lcam_uop_T_prs3 = do_ld_search_0 ? mem_ldq_e_0_bits_uop_prs3 : 6'h0; // @[lsu.scala:263:49, :1031:37] wire [3:0] _lcam_uop_T_ppred = do_ld_search_0 ? mem_ldq_e_0_bits_uop_ppred : 4'h0; // @[lsu.scala:263:49, :1031:37] wire _lcam_uop_T_prs1_busy = do_ld_search_0 & mem_ldq_e_0_bits_uop_prs1_busy; // @[lsu.scala:263:49, :1031:37] wire _lcam_uop_T_prs2_busy = do_ld_search_0 & mem_ldq_e_0_bits_uop_prs2_busy; // @[lsu.scala:263:49, :1031:37] wire _lcam_uop_T_prs3_busy = do_ld_search_0 & mem_ldq_e_0_bits_uop_prs3_busy; // @[lsu.scala:263:49, :1031:37] wire _lcam_uop_T_ppred_busy = do_ld_search_0 & mem_ldq_e_0_bits_uop_ppred_busy; // @[lsu.scala:263:49, :1031:37] wire [5:0] _lcam_uop_T_stale_pdst = do_ld_search_0 ? mem_ldq_e_0_bits_uop_stale_pdst : 6'h0; // @[lsu.scala:263:49, :1031:37] wire _lcam_uop_T_exception = do_ld_search_0 & mem_ldq_e_0_bits_uop_exception; // @[lsu.scala:263:49, :1031:37] wire [63:0] _lcam_uop_T_exc_cause = do_ld_search_0 ? mem_ldq_e_0_bits_uop_exc_cause : 64'h0; // @[lsu.scala:263:49, :1031:37] wire _lcam_uop_T_bypassable = do_ld_search_0 & mem_ldq_e_0_bits_uop_bypassable; // @[lsu.scala:263:49, :1031:37] wire [4:0] _lcam_uop_T_mem_cmd = do_ld_search_0 ? mem_ldq_e_0_bits_uop_mem_cmd : 5'h0; // @[lsu.scala:263:49, :1031:37] wire [1:0] _lcam_uop_T_mem_size = do_ld_search_0 ? mem_ldq_e_0_bits_uop_mem_size : 2'h0; // @[lsu.scala:263:49, :1031:37] wire _lcam_uop_T_mem_signed = do_ld_search_0 & mem_ldq_e_0_bits_uop_mem_signed; // @[lsu.scala:263:49, :1031:37] wire _lcam_uop_T_is_fence = do_ld_search_0 & mem_ldq_e_0_bits_uop_is_fence; // @[lsu.scala:263:49, :1031:37] wire _lcam_uop_T_is_fencei = do_ld_search_0 & mem_ldq_e_0_bits_uop_is_fencei; // @[lsu.scala:263:49, :1031:37] wire _lcam_uop_T_is_amo = do_ld_search_0 & mem_ldq_e_0_bits_uop_is_amo; // @[lsu.scala:263:49, :1031:37] wire _lcam_uop_T_uses_ldq = do_ld_search_0 & mem_ldq_e_0_bits_uop_uses_ldq; // @[lsu.scala:263:49, :1031:37] wire _lcam_uop_T_uses_stq = do_ld_search_0 & mem_ldq_e_0_bits_uop_uses_stq; // @[lsu.scala:263:49, :1031:37] wire _lcam_uop_T_is_sys_pc2epc = do_ld_search_0 & mem_ldq_e_0_bits_uop_is_sys_pc2epc; // @[lsu.scala:263:49, :1031:37] wire _lcam_uop_T_is_unique = do_ld_search_0 & mem_ldq_e_0_bits_uop_is_unique; // @[lsu.scala:263:49, :1031:37] wire _lcam_uop_T_flush_on_commit = do_ld_search_0 & mem_ldq_e_0_bits_uop_flush_on_commit; // @[lsu.scala:263:49, :1031:37] wire _lcam_uop_T_ldst_is_rs1 = do_ld_search_0 & mem_ldq_e_0_bits_uop_ldst_is_rs1; // @[lsu.scala:263:49, :1031:37] wire [5:0] _lcam_uop_T_ldst = do_ld_search_0 ? mem_ldq_e_0_bits_uop_ldst : 6'h0; // @[lsu.scala:263:49, :1031:37] wire [5:0] _lcam_uop_T_lrs1 = do_ld_search_0 ? mem_ldq_e_0_bits_uop_lrs1 : 6'h0; // @[lsu.scala:263:49, :1031:37] wire [5:0] _lcam_uop_T_lrs2 = do_ld_search_0 ? mem_ldq_e_0_bits_uop_lrs2 : 6'h0; // @[lsu.scala:263:49, :1031:37] wire [5:0] _lcam_uop_T_lrs3 = do_ld_search_0 ? mem_ldq_e_0_bits_uop_lrs3 : 6'h0; // @[lsu.scala:263:49, :1031:37] wire _lcam_uop_T_ldst_val = do_ld_search_0 & mem_ldq_e_0_bits_uop_ldst_val; // @[lsu.scala:263:49, :1031:37] wire [1:0] _lcam_uop_T_dst_rtype = do_ld_search_0 ? mem_ldq_e_0_bits_uop_dst_rtype : 2'h2; // @[lsu.scala:263:49, :1031:37] wire [1:0] _lcam_uop_T_lrs1_rtype = do_ld_search_0 ? mem_ldq_e_0_bits_uop_lrs1_rtype : 2'h0; // @[lsu.scala:263:49, :1031:37] wire [1:0] _lcam_uop_T_lrs2_rtype = do_ld_search_0 ? mem_ldq_e_0_bits_uop_lrs2_rtype : 2'h0; // @[lsu.scala:263:49, :1031:37] wire _lcam_uop_T_frs3_en = do_ld_search_0 & mem_ldq_e_0_bits_uop_frs3_en; // @[lsu.scala:263:49, :1031:37] wire _lcam_uop_T_fp_val = do_ld_search_0 & mem_ldq_e_0_bits_uop_fp_val; // @[lsu.scala:263:49, :1031:37] wire _lcam_uop_T_fp_single = do_ld_search_0 & mem_ldq_e_0_bits_uop_fp_single; // @[lsu.scala:263:49, :1031:37] wire _lcam_uop_T_xcpt_pf_if = do_ld_search_0 & mem_ldq_e_0_bits_uop_xcpt_pf_if; // @[lsu.scala:263:49, :1031:37] wire _lcam_uop_T_xcpt_ae_if = do_ld_search_0 & mem_ldq_e_0_bits_uop_xcpt_ae_if; // @[lsu.scala:263:49, :1031:37] wire _lcam_uop_T_xcpt_ma_if = do_ld_search_0 & mem_ldq_e_0_bits_uop_xcpt_ma_if; // @[lsu.scala:263:49, :1031:37] wire _lcam_uop_T_bp_debug_if = do_ld_search_0 & mem_ldq_e_0_bits_uop_bp_debug_if; // @[lsu.scala:263:49, :1031:37] wire _lcam_uop_T_bp_xcpt_if = do_ld_search_0 & mem_ldq_e_0_bits_uop_bp_xcpt_if; // @[lsu.scala:263:49, :1031:37] wire [1:0] _lcam_uop_T_debug_fsrc = do_ld_search_0 ? mem_ldq_e_0_bits_uop_debug_fsrc : 2'h0; // @[lsu.scala:263:49, :1031:37] wire [1:0] _lcam_uop_T_debug_tsrc = do_ld_search_0 ? mem_ldq_e_0_bits_uop_debug_tsrc : 2'h0; // @[lsu.scala:263:49, :1031:37] wire [6:0] _lcam_uop_T_1_uopc = do_st_search_0 ? mem_stq_e_0_bits_uop_uopc : _lcam_uop_T_uopc; // @[lsu.scala:263:49, :1030:37, :1031:37] wire [31:0] _lcam_uop_T_1_inst = do_st_search_0 ? mem_stq_e_0_bits_uop_inst : _lcam_uop_T_inst; // @[lsu.scala:263:49, :1030:37, :1031:37] wire [31:0] _lcam_uop_T_1_debug_inst = do_st_search_0 ? mem_stq_e_0_bits_uop_debug_inst : _lcam_uop_T_debug_inst; // @[lsu.scala:263:49, :1030:37, :1031:37] wire _lcam_uop_T_1_is_rvc = do_st_search_0 ? mem_stq_e_0_bits_uop_is_rvc : _lcam_uop_T_is_rvc; // @[lsu.scala:263:49, :1030:37, :1031:37] wire [39:0] _lcam_uop_T_1_debug_pc = do_st_search_0 ? mem_stq_e_0_bits_uop_debug_pc : _lcam_uop_T_debug_pc; // @[lsu.scala:263:49, :1030:37, :1031:37] wire [2:0] _lcam_uop_T_1_iq_type = do_st_search_0 ? mem_stq_e_0_bits_uop_iq_type : _lcam_uop_T_iq_type; // @[lsu.scala:263:49, :1030:37, :1031:37] wire [9:0] _lcam_uop_T_1_fu_code = do_st_search_0 ? mem_stq_e_0_bits_uop_fu_code : _lcam_uop_T_fu_code; // @[lsu.scala:263:49, :1030:37, :1031:37] wire [3:0] _lcam_uop_T_1_ctrl_br_type = do_st_search_0 ? mem_stq_e_0_bits_uop_ctrl_br_type : _lcam_uop_T_ctrl_br_type; // @[lsu.scala:263:49, :1030:37, :1031:37] wire [1:0] _lcam_uop_T_1_ctrl_op1_sel = do_st_search_0 ? mem_stq_e_0_bits_uop_ctrl_op1_sel : _lcam_uop_T_ctrl_op1_sel; // @[lsu.scala:263:49, :1030:37, :1031:37] wire [2:0] _lcam_uop_T_1_ctrl_op2_sel = do_st_search_0 ? mem_stq_e_0_bits_uop_ctrl_op2_sel : _lcam_uop_T_ctrl_op2_sel; // @[lsu.scala:263:49, :1030:37, :1031:37] wire [2:0] _lcam_uop_T_1_ctrl_imm_sel = do_st_search_0 ? mem_stq_e_0_bits_uop_ctrl_imm_sel : _lcam_uop_T_ctrl_imm_sel; // @[lsu.scala:263:49, :1030:37, :1031:37] wire [4:0] _lcam_uop_T_1_ctrl_op_fcn = do_st_search_0 ? mem_stq_e_0_bits_uop_ctrl_op_fcn : _lcam_uop_T_ctrl_op_fcn; // @[lsu.scala:263:49, :1030:37, :1031:37] wire _lcam_uop_T_1_ctrl_fcn_dw = do_st_search_0 ? mem_stq_e_0_bits_uop_ctrl_fcn_dw : _lcam_uop_T_ctrl_fcn_dw; // @[lsu.scala:263:49, :1030:37, :1031:37] wire [2:0] _lcam_uop_T_1_ctrl_csr_cmd = do_st_search_0 ? mem_stq_e_0_bits_uop_ctrl_csr_cmd : _lcam_uop_T_ctrl_csr_cmd; // @[lsu.scala:263:49, :1030:37, :1031:37] wire _lcam_uop_T_1_ctrl_is_load = do_st_search_0 ? mem_stq_e_0_bits_uop_ctrl_is_load : _lcam_uop_T_ctrl_is_load; // @[lsu.scala:263:49, :1030:37, :1031:37] wire _lcam_uop_T_1_ctrl_is_sta = do_st_search_0 ? mem_stq_e_0_bits_uop_ctrl_is_sta : _lcam_uop_T_ctrl_is_sta; // @[lsu.scala:263:49, :1030:37, :1031:37] wire _lcam_uop_T_1_ctrl_is_std = do_st_search_0 ? mem_stq_e_0_bits_uop_ctrl_is_std : _lcam_uop_T_ctrl_is_std; // @[lsu.scala:263:49, :1030:37, :1031:37] wire [1:0] _lcam_uop_T_1_iw_state = do_st_search_0 ? mem_stq_e_0_bits_uop_iw_state : _lcam_uop_T_iw_state; // @[lsu.scala:263:49, :1030:37, :1031:37] wire _lcam_uop_T_1_iw_p1_poisoned = do_st_search_0 ? mem_stq_e_0_bits_uop_iw_p1_poisoned : _lcam_uop_T_iw_p1_poisoned; // @[lsu.scala:263:49, :1030:37, :1031:37] wire _lcam_uop_T_1_iw_p2_poisoned = do_st_search_0 ? mem_stq_e_0_bits_uop_iw_p2_poisoned : _lcam_uop_T_iw_p2_poisoned; // @[lsu.scala:263:49, :1030:37, :1031:37] wire _lcam_uop_T_1_is_br = do_st_search_0 ? mem_stq_e_0_bits_uop_is_br : _lcam_uop_T_is_br; // @[lsu.scala:263:49, :1030:37, :1031:37] wire _lcam_uop_T_1_is_jalr = do_st_search_0 ? mem_stq_e_0_bits_uop_is_jalr : _lcam_uop_T_is_jalr; // @[lsu.scala:263:49, :1030:37, :1031:37] wire _lcam_uop_T_1_is_jal = do_st_search_0 ? mem_stq_e_0_bits_uop_is_jal : _lcam_uop_T_is_jal; // @[lsu.scala:263:49, :1030:37, :1031:37] wire _lcam_uop_T_1_is_sfb = do_st_search_0 ? mem_stq_e_0_bits_uop_is_sfb : _lcam_uop_T_is_sfb; // @[lsu.scala:263:49, :1030:37, :1031:37] wire [7:0] _lcam_uop_T_1_br_mask = do_st_search_0 ? mem_stq_e_0_bits_uop_br_mask : _lcam_uop_T_br_mask; // @[lsu.scala:263:49, :1030:37, :1031:37] wire [2:0] _lcam_uop_T_1_br_tag = do_st_search_0 ? mem_stq_e_0_bits_uop_br_tag : _lcam_uop_T_br_tag; // @[lsu.scala:263:49, :1030:37, :1031:37] wire [3:0] _lcam_uop_T_1_ftq_idx = do_st_search_0 ? mem_stq_e_0_bits_uop_ftq_idx : _lcam_uop_T_ftq_idx; // @[lsu.scala:263:49, :1030:37, :1031:37] wire _lcam_uop_T_1_edge_inst = do_st_search_0 ? mem_stq_e_0_bits_uop_edge_inst : _lcam_uop_T_edge_inst; // @[lsu.scala:263:49, :1030:37, :1031:37] wire [5:0] _lcam_uop_T_1_pc_lob = do_st_search_0 ? mem_stq_e_0_bits_uop_pc_lob : _lcam_uop_T_pc_lob; // @[lsu.scala:263:49, :1030:37, :1031:37] wire _lcam_uop_T_1_taken = do_st_search_0 ? mem_stq_e_0_bits_uop_taken : _lcam_uop_T_taken; // @[lsu.scala:263:49, :1030:37, :1031:37] wire [19:0] _lcam_uop_T_1_imm_packed = do_st_search_0 ? mem_stq_e_0_bits_uop_imm_packed : _lcam_uop_T_imm_packed; // @[lsu.scala:263:49, :1030:37, :1031:37] wire [11:0] _lcam_uop_T_1_csr_addr = do_st_search_0 ? mem_stq_e_0_bits_uop_csr_addr : _lcam_uop_T_csr_addr; // @[lsu.scala:263:49, :1030:37, :1031:37] wire [4:0] _lcam_uop_T_1_rob_idx = do_st_search_0 ? mem_stq_e_0_bits_uop_rob_idx : _lcam_uop_T_rob_idx; // @[lsu.scala:263:49, :1030:37, :1031:37] wire [2:0] _lcam_uop_T_1_ldq_idx = do_st_search_0 ? mem_stq_e_0_bits_uop_ldq_idx : _lcam_uop_T_ldq_idx; // @[lsu.scala:263:49, :1030:37, :1031:37] wire [2:0] _lcam_uop_T_1_stq_idx = do_st_search_0 ? mem_stq_e_0_bits_uop_stq_idx : _lcam_uop_T_stq_idx; // @[lsu.scala:263:49, :1030:37, :1031:37] wire [1:0] _lcam_uop_T_1_rxq_idx = do_st_search_0 ? mem_stq_e_0_bits_uop_rxq_idx : _lcam_uop_T_rxq_idx; // @[lsu.scala:263:49, :1030:37, :1031:37] wire [5:0] _lcam_uop_T_1_pdst = do_st_search_0 ? mem_stq_e_0_bits_uop_pdst : _lcam_uop_T_pdst; // @[lsu.scala:263:49, :1030:37, :1031:37] wire [5:0] _lcam_uop_T_1_prs1 = do_st_search_0 ? mem_stq_e_0_bits_uop_prs1 : _lcam_uop_T_prs1; // @[lsu.scala:263:49, :1030:37, :1031:37] wire [5:0] _lcam_uop_T_1_prs2 = do_st_search_0 ? mem_stq_e_0_bits_uop_prs2 : _lcam_uop_T_prs2; // @[lsu.scala:263:49, :1030:37, :1031:37] wire [5:0] _lcam_uop_T_1_prs3 = do_st_search_0 ? mem_stq_e_0_bits_uop_prs3 : _lcam_uop_T_prs3; // @[lsu.scala:263:49, :1030:37, :1031:37] wire [3:0] _lcam_uop_T_1_ppred = do_st_search_0 ? mem_stq_e_0_bits_uop_ppred : _lcam_uop_T_ppred; // @[lsu.scala:263:49, :1030:37, :1031:37] wire _lcam_uop_T_1_prs1_busy = do_st_search_0 ? mem_stq_e_0_bits_uop_prs1_busy : _lcam_uop_T_prs1_busy; // @[lsu.scala:263:49, :1030:37, :1031:37] wire _lcam_uop_T_1_prs2_busy = do_st_search_0 ? mem_stq_e_0_bits_uop_prs2_busy : _lcam_uop_T_prs2_busy; // @[lsu.scala:263:49, :1030:37, :1031:37] wire _lcam_uop_T_1_prs3_busy = do_st_search_0 ? mem_stq_e_0_bits_uop_prs3_busy : _lcam_uop_T_prs3_busy; // @[lsu.scala:263:49, :1030:37, :1031:37] wire _lcam_uop_T_1_ppred_busy = do_st_search_0 ? mem_stq_e_0_bits_uop_ppred_busy : _lcam_uop_T_ppred_busy; // @[lsu.scala:263:49, :1030:37, :1031:37] wire [5:0] _lcam_uop_T_1_stale_pdst = do_st_search_0 ? mem_stq_e_0_bits_uop_stale_pdst : _lcam_uop_T_stale_pdst; // @[lsu.scala:263:49, :1030:37, :1031:37] wire _lcam_uop_T_1_exception = do_st_search_0 ? mem_stq_e_0_bits_uop_exception : _lcam_uop_T_exception; // @[lsu.scala:263:49, :1030:37, :1031:37] wire [63:0] _lcam_uop_T_1_exc_cause = do_st_search_0 ? mem_stq_e_0_bits_uop_exc_cause : _lcam_uop_T_exc_cause; // @[lsu.scala:263:49, :1030:37, :1031:37] wire _lcam_uop_T_1_bypassable = do_st_search_0 ? mem_stq_e_0_bits_uop_bypassable : _lcam_uop_T_bypassable; // @[lsu.scala:263:49, :1030:37, :1031:37] wire [4:0] _lcam_uop_T_1_mem_cmd = do_st_search_0 ? mem_stq_e_0_bits_uop_mem_cmd : _lcam_uop_T_mem_cmd; // @[lsu.scala:263:49, :1030:37, :1031:37] wire [1:0] _lcam_uop_T_1_mem_size = do_st_search_0 ? mem_stq_e_0_bits_uop_mem_size : _lcam_uop_T_mem_size; // @[lsu.scala:263:49, :1030:37, :1031:37] wire _lcam_uop_T_1_mem_signed = do_st_search_0 ? mem_stq_e_0_bits_uop_mem_signed : _lcam_uop_T_mem_signed; // @[lsu.scala:263:49, :1030:37, :1031:37] wire _lcam_uop_T_1_is_fence = do_st_search_0 ? mem_stq_e_0_bits_uop_is_fence : _lcam_uop_T_is_fence; // @[lsu.scala:263:49, :1030:37, :1031:37] wire _lcam_uop_T_1_is_fencei = do_st_search_0 ? mem_stq_e_0_bits_uop_is_fencei : _lcam_uop_T_is_fencei; // @[lsu.scala:263:49, :1030:37, :1031:37] wire _lcam_uop_T_1_is_amo = do_st_search_0 ? mem_stq_e_0_bits_uop_is_amo : _lcam_uop_T_is_amo; // @[lsu.scala:263:49, :1030:37, :1031:37] wire _lcam_uop_T_1_uses_ldq = do_st_search_0 ? mem_stq_e_0_bits_uop_uses_ldq : _lcam_uop_T_uses_ldq; // @[lsu.scala:263:49, :1030:37, :1031:37] wire _lcam_uop_T_1_uses_stq = do_st_search_0 ? mem_stq_e_0_bits_uop_uses_stq : _lcam_uop_T_uses_stq; // @[lsu.scala:263:49, :1030:37, :1031:37] wire _lcam_uop_T_1_is_sys_pc2epc = do_st_search_0 ? mem_stq_e_0_bits_uop_is_sys_pc2epc : _lcam_uop_T_is_sys_pc2epc; // @[lsu.scala:263:49, :1030:37, :1031:37] wire _lcam_uop_T_1_is_unique = do_st_search_0 ? mem_stq_e_0_bits_uop_is_unique : _lcam_uop_T_is_unique; // @[lsu.scala:263:49, :1030:37, :1031:37] wire _lcam_uop_T_1_flush_on_commit = do_st_search_0 ? mem_stq_e_0_bits_uop_flush_on_commit : _lcam_uop_T_flush_on_commit; // @[lsu.scala:263:49, :1030:37, :1031:37] wire _lcam_uop_T_1_ldst_is_rs1 = do_st_search_0 ? mem_stq_e_0_bits_uop_ldst_is_rs1 : _lcam_uop_T_ldst_is_rs1; // @[lsu.scala:263:49, :1030:37, :1031:37] wire [5:0] _lcam_uop_T_1_ldst = do_st_search_0 ? mem_stq_e_0_bits_uop_ldst : _lcam_uop_T_ldst; // @[lsu.scala:263:49, :1030:37, :1031:37] wire [5:0] _lcam_uop_T_1_lrs1 = do_st_search_0 ? mem_stq_e_0_bits_uop_lrs1 : _lcam_uop_T_lrs1; // @[lsu.scala:263:49, :1030:37, :1031:37] wire [5:0] _lcam_uop_T_1_lrs2 = do_st_search_0 ? mem_stq_e_0_bits_uop_lrs2 : _lcam_uop_T_lrs2; // @[lsu.scala:263:49, :1030:37, :1031:37] wire [5:0] _lcam_uop_T_1_lrs3 = do_st_search_0 ? mem_stq_e_0_bits_uop_lrs3 : _lcam_uop_T_lrs3; // @[lsu.scala:263:49, :1030:37, :1031:37] wire _lcam_uop_T_1_ldst_val = do_st_search_0 ? mem_stq_e_0_bits_uop_ldst_val : _lcam_uop_T_ldst_val; // @[lsu.scala:263:49, :1030:37, :1031:37] wire [1:0] _lcam_uop_T_1_dst_rtype = do_st_search_0 ? mem_stq_e_0_bits_uop_dst_rtype : _lcam_uop_T_dst_rtype; // @[lsu.scala:263:49, :1030:37, :1031:37] wire [1:0] _lcam_uop_T_1_lrs1_rtype = do_st_search_0 ? mem_stq_e_0_bits_uop_lrs1_rtype : _lcam_uop_T_lrs1_rtype; // @[lsu.scala:263:49, :1030:37, :1031:37] wire [1:0] _lcam_uop_T_1_lrs2_rtype = do_st_search_0 ? mem_stq_e_0_bits_uop_lrs2_rtype : _lcam_uop_T_lrs2_rtype; // @[lsu.scala:263:49, :1030:37, :1031:37] wire _lcam_uop_T_1_frs3_en = do_st_search_0 ? mem_stq_e_0_bits_uop_frs3_en : _lcam_uop_T_frs3_en; // @[lsu.scala:263:49, :1030:37, :1031:37] wire _lcam_uop_T_1_fp_val = do_st_search_0 ? mem_stq_e_0_bits_uop_fp_val : _lcam_uop_T_fp_val; // @[lsu.scala:263:49, :1030:37, :1031:37] wire _lcam_uop_T_1_fp_single = do_st_search_0 ? mem_stq_e_0_bits_uop_fp_single : _lcam_uop_T_fp_single; // @[lsu.scala:263:49, :1030:37, :1031:37] wire _lcam_uop_T_1_xcpt_pf_if = do_st_search_0 ? mem_stq_e_0_bits_uop_xcpt_pf_if : _lcam_uop_T_xcpt_pf_if; // @[lsu.scala:263:49, :1030:37, :1031:37] wire _lcam_uop_T_1_xcpt_ae_if = do_st_search_0 ? mem_stq_e_0_bits_uop_xcpt_ae_if : _lcam_uop_T_xcpt_ae_if; // @[lsu.scala:263:49, :1030:37, :1031:37] wire _lcam_uop_T_1_xcpt_ma_if = do_st_search_0 ? mem_stq_e_0_bits_uop_xcpt_ma_if : _lcam_uop_T_xcpt_ma_if; // @[lsu.scala:263:49, :1030:37, :1031:37] wire _lcam_uop_T_1_bp_debug_if = do_st_search_0 ? mem_stq_e_0_bits_uop_bp_debug_if : _lcam_uop_T_bp_debug_if; // @[lsu.scala:263:49, :1030:37, :1031:37] wire _lcam_uop_T_1_bp_xcpt_if = do_st_search_0 ? mem_stq_e_0_bits_uop_bp_xcpt_if : _lcam_uop_T_bp_xcpt_if; // @[lsu.scala:263:49, :1030:37, :1031:37] wire [1:0] _lcam_uop_T_1_debug_fsrc = do_st_search_0 ? mem_stq_e_0_bits_uop_debug_fsrc : _lcam_uop_T_debug_fsrc; // @[lsu.scala:263:49, :1030:37, :1031:37] wire [1:0] _lcam_uop_T_1_debug_tsrc = do_st_search_0 ? mem_stq_e_0_bits_uop_debug_tsrc : _lcam_uop_T_debug_tsrc; // @[lsu.scala:263:49, :1030:37, :1031:37] wire [6:0] lcam_uop_0_uopc = _lcam_uop_T_1_uopc; // @[lsu.scala:263:49, :1030:37] wire [31:0] lcam_uop_0_inst = _lcam_uop_T_1_inst; // @[lsu.scala:263:49, :1030:37] wire [31:0] lcam_uop_0_debug_inst = _lcam_uop_T_1_debug_inst; // @[lsu.scala:263:49, :1030:37] wire lcam_uop_0_is_rvc = _lcam_uop_T_1_is_rvc; // @[lsu.scala:263:49, :1030:37] wire [39:0] lcam_uop_0_debug_pc = _lcam_uop_T_1_debug_pc; // @[lsu.scala:263:49, :1030:37] wire [2:0] lcam_uop_0_iq_type = _lcam_uop_T_1_iq_type; // @[lsu.scala:263:49, :1030:37] wire [9:0] lcam_uop_0_fu_code = _lcam_uop_T_1_fu_code; // @[lsu.scala:263:49, :1030:37] wire [3:0] lcam_uop_0_ctrl_br_type = _lcam_uop_T_1_ctrl_br_type; // @[lsu.scala:263:49, :1030:37] wire [1:0] lcam_uop_0_ctrl_op1_sel = _lcam_uop_T_1_ctrl_op1_sel; // @[lsu.scala:263:49, :1030:37] wire [2:0] lcam_uop_0_ctrl_op2_sel = _lcam_uop_T_1_ctrl_op2_sel; // @[lsu.scala:263:49, :1030:37] wire [2:0] lcam_uop_0_ctrl_imm_sel = _lcam_uop_T_1_ctrl_imm_sel; // @[lsu.scala:263:49, :1030:37] wire [4:0] lcam_uop_0_ctrl_op_fcn = _lcam_uop_T_1_ctrl_op_fcn; // @[lsu.scala:263:49, :1030:37] wire lcam_uop_0_ctrl_fcn_dw = _lcam_uop_T_1_ctrl_fcn_dw; // @[lsu.scala:263:49, :1030:37] wire [2:0] lcam_uop_0_ctrl_csr_cmd = _lcam_uop_T_1_ctrl_csr_cmd; // @[lsu.scala:263:49, :1030:37] wire lcam_uop_0_ctrl_is_load = _lcam_uop_T_1_ctrl_is_load; // @[lsu.scala:263:49, :1030:37] wire lcam_uop_0_ctrl_is_sta = _lcam_uop_T_1_ctrl_is_sta; // @[lsu.scala:263:49, :1030:37] wire lcam_uop_0_ctrl_is_std = _lcam_uop_T_1_ctrl_is_std; // @[lsu.scala:263:49, :1030:37] wire [1:0] lcam_uop_0_iw_state = _lcam_uop_T_1_iw_state; // @[lsu.scala:263:49, :1030:37] wire lcam_uop_0_iw_p1_poisoned = _lcam_uop_T_1_iw_p1_poisoned; // @[lsu.scala:263:49, :1030:37] wire lcam_uop_0_iw_p2_poisoned = _lcam_uop_T_1_iw_p2_poisoned; // @[lsu.scala:263:49, :1030:37] wire lcam_uop_0_is_br = _lcam_uop_T_1_is_br; // @[lsu.scala:263:49, :1030:37] wire lcam_uop_0_is_jalr = _lcam_uop_T_1_is_jalr; // @[lsu.scala:263:49, :1030:37] wire lcam_uop_0_is_jal = _lcam_uop_T_1_is_jal; // @[lsu.scala:263:49, :1030:37] wire lcam_uop_0_is_sfb = _lcam_uop_T_1_is_sfb; // @[lsu.scala:263:49, :1030:37] wire [7:0] lcam_uop_0_br_mask = _lcam_uop_T_1_br_mask; // @[lsu.scala:263:49, :1030:37] wire [2:0] lcam_uop_0_br_tag = _lcam_uop_T_1_br_tag; // @[lsu.scala:263:49, :1030:37] wire [3:0] lcam_uop_0_ftq_idx = _lcam_uop_T_1_ftq_idx; // @[lsu.scala:263:49, :1030:37] wire lcam_uop_0_edge_inst = _lcam_uop_T_1_edge_inst; // @[lsu.scala:263:49, :1030:37] wire [5:0] lcam_uop_0_pc_lob = _lcam_uop_T_1_pc_lob; // @[lsu.scala:263:49, :1030:37] wire lcam_uop_0_taken = _lcam_uop_T_1_taken; // @[lsu.scala:263:49, :1030:37] wire [19:0] lcam_uop_0_imm_packed = _lcam_uop_T_1_imm_packed; // @[lsu.scala:263:49, :1030:37] wire [11:0] lcam_uop_0_csr_addr = _lcam_uop_T_1_csr_addr; // @[lsu.scala:263:49, :1030:37] wire [4:0] lcam_uop_0_rob_idx = _lcam_uop_T_1_rob_idx; // @[lsu.scala:263:49, :1030:37] wire [2:0] lcam_uop_0_ldq_idx = _lcam_uop_T_1_ldq_idx; // @[lsu.scala:263:49, :1030:37] wire [2:0] lcam_uop_0_stq_idx = _lcam_uop_T_1_stq_idx; // @[lsu.scala:263:49, :1030:37] wire [1:0] lcam_uop_0_rxq_idx = _lcam_uop_T_1_rxq_idx; // @[lsu.scala:263:49, :1030:37] wire [5:0] lcam_uop_0_pdst = _lcam_uop_T_1_pdst; // @[lsu.scala:263:49, :1030:37] wire [5:0] lcam_uop_0_prs1 = _lcam_uop_T_1_prs1; // @[lsu.scala:263:49, :1030:37] wire [5:0] lcam_uop_0_prs2 = _lcam_uop_T_1_prs2; // @[lsu.scala:263:49, :1030:37] wire [5:0] lcam_uop_0_prs3 = _lcam_uop_T_1_prs3; // @[lsu.scala:263:49, :1030:37] wire [3:0] lcam_uop_0_ppred = _lcam_uop_T_1_ppred; // @[lsu.scala:263:49, :1030:37] wire lcam_uop_0_prs1_busy = _lcam_uop_T_1_prs1_busy; // @[lsu.scala:263:49, :1030:37] wire lcam_uop_0_prs2_busy = _lcam_uop_T_1_prs2_busy; // @[lsu.scala:263:49, :1030:37] wire lcam_uop_0_prs3_busy = _lcam_uop_T_1_prs3_busy; // @[lsu.scala:263:49, :1030:37] wire lcam_uop_0_ppred_busy = _lcam_uop_T_1_ppred_busy; // @[lsu.scala:263:49, :1030:37] wire [5:0] lcam_uop_0_stale_pdst = _lcam_uop_T_1_stale_pdst; // @[lsu.scala:263:49, :1030:37] wire lcam_uop_0_exception = _lcam_uop_T_1_exception; // @[lsu.scala:263:49, :1030:37] wire [63:0] lcam_uop_0_exc_cause = _lcam_uop_T_1_exc_cause; // @[lsu.scala:263:49, :1030:37] wire lcam_uop_0_bypassable = _lcam_uop_T_1_bypassable; // @[lsu.scala:263:49, :1030:37] wire [4:0] lcam_uop_0_mem_cmd = _lcam_uop_T_1_mem_cmd; // @[lsu.scala:263:49, :1030:37] wire [1:0] lcam_uop_0_mem_size = _lcam_uop_T_1_mem_size; // @[lsu.scala:263:49, :1030:37] wire lcam_uop_0_mem_signed = _lcam_uop_T_1_mem_signed; // @[lsu.scala:263:49, :1030:37] wire lcam_uop_0_is_fence = _lcam_uop_T_1_is_fence; // @[lsu.scala:263:49, :1030:37] wire lcam_uop_0_is_fencei = _lcam_uop_T_1_is_fencei; // @[lsu.scala:263:49, :1030:37] wire lcam_uop_0_is_amo = _lcam_uop_T_1_is_amo; // @[lsu.scala:263:49, :1030:37] wire lcam_uop_0_uses_ldq = _lcam_uop_T_1_uses_ldq; // @[lsu.scala:263:49, :1030:37] wire lcam_uop_0_uses_stq = _lcam_uop_T_1_uses_stq; // @[lsu.scala:263:49, :1030:37] wire lcam_uop_0_is_sys_pc2epc = _lcam_uop_T_1_is_sys_pc2epc; // @[lsu.scala:263:49, :1030:37] wire lcam_uop_0_is_unique = _lcam_uop_T_1_is_unique; // @[lsu.scala:263:49, :1030:37] wire lcam_uop_0_flush_on_commit = _lcam_uop_T_1_flush_on_commit; // @[lsu.scala:263:49, :1030:37] wire lcam_uop_0_ldst_is_rs1 = _lcam_uop_T_1_ldst_is_rs1; // @[lsu.scala:263:49, :1030:37] wire [5:0] lcam_uop_0_ldst = _lcam_uop_T_1_ldst; // @[lsu.scala:263:49, :1030:37] wire [5:0] lcam_uop_0_lrs1 = _lcam_uop_T_1_lrs1; // @[lsu.scala:263:49, :1030:37] wire [5:0] lcam_uop_0_lrs2 = _lcam_uop_T_1_lrs2; // @[lsu.scala:263:49, :1030:37] wire [5:0] lcam_uop_0_lrs3 = _lcam_uop_T_1_lrs3; // @[lsu.scala:263:49, :1030:37] wire lcam_uop_0_ldst_val = _lcam_uop_T_1_ldst_val; // @[lsu.scala:263:49, :1030:37] wire [1:0] lcam_uop_0_dst_rtype = _lcam_uop_T_1_dst_rtype; // @[lsu.scala:263:49, :1030:37] wire [1:0] lcam_uop_0_lrs1_rtype = _lcam_uop_T_1_lrs1_rtype; // @[lsu.scala:263:49, :1030:37] wire [1:0] lcam_uop_0_lrs2_rtype = _lcam_uop_T_1_lrs2_rtype; // @[lsu.scala:263:49, :1030:37] wire lcam_uop_0_frs3_en = _lcam_uop_T_1_frs3_en; // @[lsu.scala:263:49, :1030:37] wire lcam_uop_0_fp_val = _lcam_uop_T_1_fp_val; // @[lsu.scala:263:49, :1030:37] wire lcam_uop_0_fp_single = _lcam_uop_T_1_fp_single; // @[lsu.scala:263:49, :1030:37] wire lcam_uop_0_xcpt_pf_if = _lcam_uop_T_1_xcpt_pf_if; // @[lsu.scala:263:49, :1030:37] wire lcam_uop_0_xcpt_ae_if = _lcam_uop_T_1_xcpt_ae_if; // @[lsu.scala:263:49, :1030:37] wire lcam_uop_0_xcpt_ma_if = _lcam_uop_T_1_xcpt_ma_if; // @[lsu.scala:263:49, :1030:37] wire lcam_uop_0_bp_debug_if = _lcam_uop_T_1_bp_debug_if; // @[lsu.scala:263:49, :1030:37] wire lcam_uop_0_bp_xcpt_if = _lcam_uop_T_1_bp_xcpt_if; // @[lsu.scala:263:49, :1030:37] wire [1:0] lcam_uop_0_debug_fsrc = _lcam_uop_T_1_debug_fsrc; // @[lsu.scala:263:49, :1030:37] wire [1:0] lcam_uop_0_debug_tsrc = _lcam_uop_T_1_debug_tsrc; // @[lsu.scala:263:49, :1030:37] wire [7:0] lcam_mask_mask; // @[lsu.scala:1665:22] wire [7:0] lcam_mask_0 = lcam_mask_mask; // @[lsu.scala:263:49, :1665:22] wire _lcam_mask_mask_T = lcam_uop_0_mem_size == 2'h0; // @[lsu.scala:263:49, :1667:26] wire [2:0] _lcam_mask_mask_T_1 = lcam_addr_0[2:0]; // @[lsu.scala:263:49, :1667:55] wire [14:0] _lcam_mask_mask_T_2 = 15'h1 << _lcam_mask_mask_T_1; // @[lsu.scala:1667:{48,55}] wire _lcam_mask_mask_T_3 = lcam_uop_0_mem_size == 2'h1; // @[lsu.scala:263:49, :1668:26] wire [1:0] _lcam_mask_mask_T_4 = lcam_addr_0[2:1]; // @[lsu.scala:263:49, :1668:56] wire [2:0] _lcam_mask_mask_T_5 = {_lcam_mask_mask_T_4, 1'h0}; // @[lsu.scala:1668:{56,62}] wire [14:0] _lcam_mask_mask_T_6 = 15'h3 << _lcam_mask_mask_T_5; // @[lsu.scala:1668:{48,62}] wire _lcam_mask_mask_T_7 = lcam_uop_0_mem_size == 2'h2; // @[lsu.scala:263:49, :1669:26] wire _lcam_mask_mask_T_8 = lcam_addr_0[2]; // @[lsu.scala:263:49, :1669:46] wire [7:0] _lcam_mask_mask_T_9 = _lcam_mask_mask_T_8 ? 8'hF0 : 8'hF; // @[lsu.scala:1669:{41,46}] wire _lcam_mask_mask_T_10 = &lcam_uop_0_mem_size; // @[lsu.scala:263:49, :1670:26] wire [7:0] _lcam_mask_mask_T_12 = _lcam_mask_mask_T_7 ? _lcam_mask_mask_T_9 : 8'hFF; // @[Mux.scala:126:16] wire [14:0] _lcam_mask_mask_T_13 = _lcam_mask_mask_T_3 ? _lcam_mask_mask_T_6 : {7'h0, _lcam_mask_mask_T_12}; // @[Mux.scala:126:16] wire [14:0] _lcam_mask_mask_T_14 = _lcam_mask_mask_T ? _lcam_mask_mask_T_2 : _lcam_mask_mask_T_13; // @[Mux.scala:126:16] assign lcam_mask_mask = _lcam_mask_mask_T_14[7:0]; // @[Mux.scala:126:16] reg [2:0] lcam_ldq_idx_REG; // @[lsu.scala:1038:58] reg [2:0] lcam_ldq_idx_REG_1; // @[lsu.scala:1039:58] wire [2:0] _lcam_ldq_idx_T = fired_load_retry_0 ? lcam_ldq_idx_REG_1 : 3'h0; // @[lsu.scala:263:49, :1039:{26,58}] wire [2:0] _lcam_ldq_idx_T_1 = fired_load_wakeup_0 ? lcam_ldq_idx_REG : _lcam_ldq_idx_T; // @[lsu.scala:263:49, :1038:{26,58}, :1039:26] wire [2:0] _lcam_ldq_idx_T_2 = fired_load_incoming_0 ? mem_incoming_uop_0_ldq_idx : _lcam_ldq_idx_T_1; // @[lsu.scala:263:49, :909:37, :1037:26, :1038:26] wire [2:0] lcam_ldq_idx_0 = _lcam_ldq_idx_T_2; // @[lsu.scala:263:49, :1037:26] wire [2:0] _can_forward_T_2 = lcam_ldq_idx_0; // @[lsu.scala:263:49] reg [2:0] lcam_stq_idx_REG; // @[lsu.scala:1043:58] wire [2:0] _lcam_stq_idx_T_1 = fired_sta_retry_0 ? lcam_stq_idx_REG : 3'h0; // @[lsu.scala:263:49, :1043:{26,58}] wire [2:0] _lcam_stq_idx_T_2 = _lcam_stq_idx_T ? mem_incoming_uop_0_stq_idx : _lcam_stq_idx_T_1; // @[lsu.scala:909:37, :1041:{26,50}, :1043:26] wire [2:0] lcam_stq_idx_0 = _lcam_stq_idx_T_2; // @[lsu.scala:263:49, :1041:26] wire _can_forward_T_1 = ~mem_tlb_uncacheable_0; // @[lsu.scala:927:41, :1046:56] wire [2:0] _can_forward_T_3 = _can_forward_T_2; wire _can_forward_T_4 = ~_GEN_174[_can_forward_T_3]; // @[lsu.scala:263:49, :1047:7] wire _can_forward_T_5 = _can_forward_T ? _can_forward_T_1 : _can_forward_T_4; // @[lsu.scala:1046:{8,32,56}, :1047:7] wire _can_forward_WIRE_0 = _can_forward_T_5; // @[lsu.scala:263:49, :1046:8] wire can_forward_0; // @[lsu.scala:1045:29] wire ldst_addr_matches_0_0; // @[lsu.scala:1050:38] wire ldst_addr_matches_0_1; // @[lsu.scala:1050:38] wire ldst_addr_matches_0_2; // @[lsu.scala:1050:38] wire ldst_addr_matches_0_3; // @[lsu.scala:1050:38] wire ldst_addr_matches_0_4; // @[lsu.scala:1050:38] wire ldst_addr_matches_0_5; // @[lsu.scala:1050:38] wire ldst_addr_matches_0_6; // @[lsu.scala:1050:38] wire ldst_addr_matches_0_7; // @[lsu.scala:1050:38] wire ldst_forward_matches_0_0; // @[lsu.scala:1052:38] wire ldst_forward_matches_0_1; // @[lsu.scala:1052:38] wire ldst_forward_matches_0_2; // @[lsu.scala:1052:38] wire ldst_forward_matches_0_3; // @[lsu.scala:1052:38] wire ldst_forward_matches_0_4; // @[lsu.scala:1052:38] wire ldst_forward_matches_0_5; // @[lsu.scala:1052:38] wire ldst_forward_matches_0_6; // @[lsu.scala:1052:38] wire ldst_forward_matches_0_7; // @[lsu.scala:1052:38] wire _temp_bits_WIRE_1_8 = failed_loads_0; // @[lsu.scala:1054:34, :1229:27] wire _temp_bits_WIRE_1_9 = failed_loads_1; // @[lsu.scala:1054:34, :1229:27] wire _temp_bits_WIRE_1_10 = failed_loads_2; // @[lsu.scala:1054:34, :1229:27] wire _temp_bits_WIRE_1_11 = failed_loads_3; // @[lsu.scala:1054:34, :1229:27] wire _temp_bits_WIRE_1_12 = failed_loads_4; // @[lsu.scala:1054:34, :1229:27] wire _temp_bits_WIRE_1_13 = failed_loads_5; // @[lsu.scala:1054:34, :1229:27] wire _temp_bits_WIRE_1_14 = failed_loads_6; // @[lsu.scala:1054:34, :1229:27] wire failed_loads_7; // @[lsu.scala:1054:34] wire _temp_bits_T_15 = failed_loads_7; // @[lsu.scala:1054:34, :1230:21] wire _temp_bits_WIRE_1_15 = failed_loads_7; // @[lsu.scala:1054:34, :1229:27] wire nacking_loads_0; // @[lsu.scala:1055:34] wire nacking_loads_1; // @[lsu.scala:1055:34] wire nacking_loads_2; // @[lsu.scala:1055:34] wire nacking_loads_3; // @[lsu.scala:1055:34] wire nacking_loads_4; // @[lsu.scala:1055:34] wire nacking_loads_5; // @[lsu.scala:1055:34] wire nacking_loads_6; // @[lsu.scala:1055:34] wire nacking_loads_7; // @[lsu.scala:1055:34] reg s1_executing_loads_0; // @[lsu.scala:1057:35] reg s1_executing_loads_1; // @[lsu.scala:1057:35] reg s1_executing_loads_2; // @[lsu.scala:1057:35] reg s1_executing_loads_3; // @[lsu.scala:1057:35] reg s1_executing_loads_4; // @[lsu.scala:1057:35] reg s1_executing_loads_5; // @[lsu.scala:1057:35] reg s1_executing_loads_6; // @[lsu.scala:1057:35] reg s1_executing_loads_7; // @[lsu.scala:1057:35] wire s1_set_execute_0; // @[lsu.scala:1058:36] wire s1_set_execute_1; // @[lsu.scala:1058:36] wire s1_set_execute_2; // @[lsu.scala:1058:36] wire s1_set_execute_3; // @[lsu.scala:1058:36] wire s1_set_execute_4; // @[lsu.scala:1058:36] wire s1_set_execute_5; // @[lsu.scala:1058:36] wire s1_set_execute_6; // @[lsu.scala:1058:36] wire s1_set_execute_7; // @[lsu.scala:1058:36] wire mem_forward_valid_0; // @[lsu.scala:1060:33] wire [2:0] forwarding_idx_0; // @[lsu.scala:263:49] wire [2:0] mem_forward_stq_idx_0; // @[lsu.scala:1063:33] reg wb_forward_valid_0; // @[lsu.scala:1065:36] reg [2:0] wb_forward_ldq_idx_0; // @[lsu.scala:1066:36] wire [2:0] _forward_uop_T = wb_forward_ldq_idx_0; // @[lsu.scala:1066:36] reg [39:0] wb_forward_ld_addr_0; // @[lsu.scala:1067:36] reg [2:0] wb_forward_stq_idx_0; // @[lsu.scala:1068:36] wire [7:0] l_mask; // @[lsu.scala:1665:22] wire _l_mask_mask_T = ldq_0_bits_uop_mem_size == 2'h0; // @[lsu.scala:208:16, :1667:26] wire [2:0] _l_mask_mask_T_1 = ldq_0_bits_addr_bits[2:0]; // @[lsu.scala:208:16, :1667:55] wire [14:0] _l_mask_mask_T_2 = 15'h1 << _l_mask_mask_T_1; // @[lsu.scala:1667:{48,55}] wire _l_mask_mask_T_3 = ldq_0_bits_uop_mem_size == 2'h1; // @[lsu.scala:208:16, :1668:26] wire [1:0] _l_mask_mask_T_4 = ldq_0_bits_addr_bits[2:1]; // @[lsu.scala:208:16, :1668:56] wire [2:0] _l_mask_mask_T_5 = {_l_mask_mask_T_4, 1'h0}; // @[lsu.scala:1668:{56,62}] wire [14:0] _l_mask_mask_T_6 = 15'h3 << _l_mask_mask_T_5; // @[lsu.scala:1668:{48,62}] wire _l_mask_mask_T_7 = ldq_0_bits_uop_mem_size == 2'h2; // @[lsu.scala:208:16, :1669:26] wire _l_mask_mask_T_8 = ldq_0_bits_addr_bits[2]; // @[lsu.scala:208:16, :1669:46] wire [7:0] _l_mask_mask_T_9 = _l_mask_mask_T_8 ? 8'hF0 : 8'hF; // @[lsu.scala:1669:{41,46}] wire _l_mask_mask_T_10 = &ldq_0_bits_uop_mem_size; // @[lsu.scala:208:16, :1670:26] wire [7:0] _l_mask_mask_T_12 = _l_mask_mask_T_7 ? _l_mask_mask_T_9 : 8'hFF; // @[Mux.scala:126:16] wire [14:0] _l_mask_mask_T_13 = _l_mask_mask_T_3 ? _l_mask_mask_T_6 : {7'h0, _l_mask_mask_T_12}; // @[Mux.scala:126:16] wire [14:0] _l_mask_mask_T_14 = _l_mask_mask_T ? _l_mask_mask_T_2 : _l_mask_mask_T_13; // @[Mux.scala:126:16] assign l_mask = _l_mask_mask_T_14[7:0]; // @[Mux.scala:126:16] wire _l_forwarders_T = wb_forward_ldq_idx_0 == 3'h0; // @[lsu.scala:1066:36, :1076:88] wire _l_forwarders_T_1 = wb_forward_valid_0 & _l_forwarders_T; // @[lsu.scala:1065:36, :1076:{63,88}] wire l_forwarders_0 = _l_forwarders_T_1; // @[lsu.scala:263:49, :1076:63] wire [2:0] l_forward_stq_idx = l_forwarders_0 ? wb_forward_stq_idx_0 : ldq_0_bits_forward_stq_idx; // @[lsu.scala:208:16, :263:49, :1068:36, :1078:32] wire [33:0] _block_addr_matches_T = lcam_addr_0[39:6]; // @[lsu.scala:263:49, :1081:57] wire [33:0] _block_addr_matches_T_3 = lcam_addr_0[39:6]; // @[lsu.scala:263:49, :1081:57] wire [33:0] _block_addr_matches_T_6 = lcam_addr_0[39:6]; // @[lsu.scala:263:49, :1081:57] wire [33:0] _block_addr_matches_T_9 = lcam_addr_0[39:6]; // @[lsu.scala:263:49, :1081:57] wire [33:0] _block_addr_matches_T_12 = lcam_addr_0[39:6]; // @[lsu.scala:263:49, :1081:57] wire [33:0] _block_addr_matches_T_15 = lcam_addr_0[39:6]; // @[lsu.scala:263:49, :1081:57] wire [33:0] _block_addr_matches_T_18 = lcam_addr_0[39:6]; // @[lsu.scala:263:49, :1081:57] wire [33:0] _block_addr_matches_T_21 = lcam_addr_0[39:6]; // @[lsu.scala:263:49, :1081:57] wire [33:0] _block_addr_matches_T_1 = ldq_0_bits_addr_bits[39:6]; // @[lsu.scala:208:16, :1081:84] wire _block_addr_matches_T_2 = _block_addr_matches_T == _block_addr_matches_T_1; // @[lsu.scala:1081:{57,73,84}] wire block_addr_matches_0 = _block_addr_matches_T_2; // @[lsu.scala:263:49, :1081:73] wire [2:0] _dword_addr_matches_T = lcam_addr_0[5:3]; // @[lsu.scala:263:49, :1082:81] wire [2:0] _dword_addr_matches_T_4 = lcam_addr_0[5:3]; // @[lsu.scala:263:49, :1082:81] wire [2:0] _dword_addr_matches_T_8 = lcam_addr_0[5:3]; // @[lsu.scala:263:49, :1082:81] wire [2:0] _dword_addr_matches_T_12 = lcam_addr_0[5:3]; // @[lsu.scala:263:49, :1082:81] wire [2:0] _dword_addr_matches_T_16 = lcam_addr_0[5:3]; // @[lsu.scala:263:49, :1082:81] wire [2:0] _dword_addr_matches_T_20 = lcam_addr_0[5:3]; // @[lsu.scala:263:49, :1082:81] wire [2:0] _dword_addr_matches_T_24 = lcam_addr_0[5:3]; // @[lsu.scala:263:49, :1082:81] wire [2:0] _dword_addr_matches_T_28 = lcam_addr_0[5:3]; // @[lsu.scala:263:49, :1082:81] wire [2:0] _dword_addr_matches_T_1 = ldq_0_bits_addr_bits[5:3]; // @[lsu.scala:208:16, :1082:110] wire _dword_addr_matches_T_2 = _dword_addr_matches_T == _dword_addr_matches_T_1; // @[lsu.scala:1082:{81,100,110}] wire _dword_addr_matches_T_3 = block_addr_matches_0 & _dword_addr_matches_T_2; // @[lsu.scala:263:49, :1082:{66,100}] wire dword_addr_matches_0 = _dword_addr_matches_T_3; // @[lsu.scala:263:49, :1082:66] wire [7:0] _GEN_229 = l_mask & lcam_mask_0; // @[lsu.scala:263:49, :1083:46, :1665:22] wire [7:0] _mask_match_T; // @[lsu.scala:1083:46] assign _mask_match_T = _GEN_229; // @[lsu.scala:1083:46] wire [7:0] _mask_overlap_T; // @[lsu.scala:1084:46] assign _mask_overlap_T = _GEN_229; // @[lsu.scala:1083:46, :1084:46] wire _mask_match_T_1 = _mask_match_T == l_mask; // @[lsu.scala:1083:{46,62}, :1665:22] wire mask_match_0 = _mask_match_T_1; // @[lsu.scala:263:49, :1083:62] wire _mask_overlap_T_1 = |_mask_overlap_T; // @[lsu.scala:1084:{46,62}] wire mask_overlap_0 = _mask_overlap_T_1; // @[lsu.scala:263:49, :1084:62] wire _T_185 = do_release_search_0 & ldq_0_valid & ldq_0_bits_addr_valid & block_addr_matches_0; // @[lsu.scala:208:16, :263:49, :1089:34, :1090:34, :1091:34] wire _T_214 = ldq_0_bits_executed | ldq_0_bits_succeeded; // @[lsu.scala:208:16, :1099:37] wire [7:0] _GEN_230 = {5'h0, lcam_stq_idx_0}; // @[lsu.scala:263:49, :1101:38] wire [7:0] _T_193 = ldq_0_bits_st_dep_mask >> _GEN_230; // @[lsu.scala:208:16, :1101:38] wire _T_197 = do_st_search_0 & ldq_0_valid & ldq_0_bits_addr_valid & (_T_214 | l_forwarders_0) & ~ldq_0_bits_addr_is_virtual & _T_193[0] & dword_addr_matches_0 & mask_overlap_0; // @[lsu.scala:208:16, :263:49, :432:52, :1096:131, :1097:131, :1098:131, :1099:{37,57,131}, :1100:131, :1101:{38,131}, :1102:131] wire _forwarded_is_older_T = l_forward_stq_idx < lcam_stq_idx_0; // @[util.scala:363:52] wire _forwarded_is_older_T_1 = l_forward_stq_idx < ldq_0_bits_youngest_stq_idx; // @[util.scala:363:64] wire _forwarded_is_older_T_2 = _forwarded_is_older_T ^ _forwarded_is_older_T_1; // @[util.scala:363:{52,58,64}] wire _forwarded_is_older_T_3 = lcam_stq_idx_0 < ldq_0_bits_youngest_stq_idx; // @[util.scala:363:78] wire forwarded_is_older = _forwarded_is_older_T_2 ^ _forwarded_is_older_T_3; // @[util.scala:363:{58,72,78}] wire _T_201 = ~ldq_0_bits_forward_std_val | l_forward_stq_idx != lcam_stq_idx_0 & forwarded_is_older; // @[util.scala:363:72] wire _T_207 = do_ld_search_0 & ldq_0_valid & ldq_0_bits_addr_valid & ~ldq_0_bits_addr_is_virtual & dword_addr_matches_0 & mask_overlap_0; // @[lsu.scala:208:16, :263:49, :432:52, :1112:47, :1113:47, :1114:47, :1115:47, :1116:47] wire _GEN_231 = lcam_ldq_idx_0 < ldq_head; // @[util.scala:363:64] wire _searcher_is_older_T_1; // @[util.scala:363:64] assign _searcher_is_older_T_1 = _GEN_231; // @[util.scala:363:64] wire _searcher_is_older_T_5; // @[util.scala:363:64] assign _searcher_is_older_T_5 = _GEN_231; // @[util.scala:363:64] wire _searcher_is_older_T_9; // @[util.scala:363:64] assign _searcher_is_older_T_9 = _GEN_231; // @[util.scala:363:64] wire _searcher_is_older_T_13; // @[util.scala:363:64] assign _searcher_is_older_T_13 = _GEN_231; // @[util.scala:363:64] wire _searcher_is_older_T_17; // @[util.scala:363:64] assign _searcher_is_older_T_17 = _GEN_231; // @[util.scala:363:64] wire _searcher_is_older_T_21; // @[util.scala:363:64] assign _searcher_is_older_T_21 = _GEN_231; // @[util.scala:363:64] wire _searcher_is_older_T_25; // @[util.scala:363:64] assign _searcher_is_older_T_25 = _GEN_231; // @[util.scala:363:64] wire _searcher_is_older_T_29; // @[util.scala:363:64] assign _searcher_is_older_T_29 = _GEN_231; // @[util.scala:363:64] wire _searcher_is_older_T_2 = _searcher_is_older_T_1; // @[util.scala:363:{58,64}] wire _searcher_is_older_T_3 = |ldq_head; // @[util.scala:363:78] wire searcher_is_older = _searcher_is_older_T_2 ^ _searcher_is_older_T_3; // @[util.scala:363:{58,72,78}] wire _GEN_232 = _T_207 & searcher_is_older & (_T_214 | l_forwarders_0) & ~s1_executing_loads_0 & ldq_0_bits_observed; // @[util.scala:363:72] assign failed_loads_0 = ~_T_185 & (_T_197 ? _T_201 : _GEN_232); // @[lsu.scala:303:5, :1054:34, :1089:34, :1090:34, :1091:34, :1092:36, :1096:131, :1097:131, :1098:131, :1099:131, :1100:131, :1101:131, :1102:131, :1103:37, :1107:39, :1108:76, :1117:37, :1119:34, :1120:74, :1121:40, :1122:34, :1123:36] reg older_nacked_REG; // @[lsu.scala:1129:57] wire older_nacked = nacking_loads_0 | older_nacked_REG; // @[lsu.scala:1055:34, :1129:{47,57}] wire _T_216 = ~_T_214 | older_nacked; // @[lsu.scala:1099:37, :1129:47, :1130:{17,56}] wire _searcher_is_older_T_4 = lcam_ldq_idx_0 == 3'h0; // @[util.scala:363:52] wire _GEN_233 = _T_185 | _T_197; // @[lsu.scala:1058:36, :1089:34, :1090:34, :1091:34, :1092:36, :1096:131, :1097:131, :1098:131, :1099:131, :1100:131, :1101:131, :1102:131, :1103:37, :1117:37] wire _GEN_234 = lcam_ldq_idx_0 == 3'h1; // @[lsu.scala:263:49, :1131:48] wire _GEN_235 = lcam_ldq_idx_0 == 3'h2; // @[lsu.scala:263:49, :1131:48] wire _GEN_236 = lcam_ldq_idx_0 == 3'h3; // @[lsu.scala:263:49, :1131:48] wire _GEN_237 = lcam_ldq_idx_0 == 3'h4; // @[lsu.scala:263:49, :1131:48] wire _GEN_238 = lcam_ldq_idx_0 == 3'h5; // @[lsu.scala:263:49, :1131:48] wire _GEN_239 = lcam_ldq_idx_0 == 3'h6; // @[lsu.scala:263:49, :1131:48] reg io_dmem_s1_kill_0_REG; // @[lsu.scala:1132:58] wire _GEN_240 = (|lcam_ldq_idx_0) & _T_216; // @[lsu.scala:263:49, :765:24, :1126:{38,47}, :1130:{56,73}, :1132:48] wire [7:0] l_mask_1; // @[lsu.scala:1665:22] wire _l_mask_mask_T_15 = ldq_1_bits_uop_mem_size == 2'h0; // @[lsu.scala:208:16, :1667:26] wire [2:0] _l_mask_mask_T_16 = ldq_1_bits_addr_bits[2:0]; // @[lsu.scala:208:16, :1667:55] wire [14:0] _l_mask_mask_T_17 = 15'h1 << _l_mask_mask_T_16; // @[lsu.scala:1667:{48,55}] wire _l_mask_mask_T_18 = ldq_1_bits_uop_mem_size == 2'h1; // @[lsu.scala:208:16, :1668:26] wire [1:0] _l_mask_mask_T_19 = ldq_1_bits_addr_bits[2:1]; // @[lsu.scala:208:16, :1668:56] wire [2:0] _l_mask_mask_T_20 = {_l_mask_mask_T_19, 1'h0}; // @[lsu.scala:1668:{56,62}] wire [14:0] _l_mask_mask_T_21 = 15'h3 << _l_mask_mask_T_20; // @[lsu.scala:1668:{48,62}] wire _l_mask_mask_T_22 = ldq_1_bits_uop_mem_size == 2'h2; // @[lsu.scala:208:16, :1669:26] wire _l_mask_mask_T_23 = ldq_1_bits_addr_bits[2]; // @[lsu.scala:208:16, :1669:46] wire [7:0] _l_mask_mask_T_24 = _l_mask_mask_T_23 ? 8'hF0 : 8'hF; // @[lsu.scala:1669:{41,46}] wire _l_mask_mask_T_25 = &ldq_1_bits_uop_mem_size; // @[lsu.scala:208:16, :1670:26] wire [7:0] _l_mask_mask_T_27 = _l_mask_mask_T_22 ? _l_mask_mask_T_24 : 8'hFF; // @[Mux.scala:126:16] wire [14:0] _l_mask_mask_T_28 = _l_mask_mask_T_18 ? _l_mask_mask_T_21 : {7'h0, _l_mask_mask_T_27}; // @[Mux.scala:126:16] wire [14:0] _l_mask_mask_T_29 = _l_mask_mask_T_15 ? _l_mask_mask_T_17 : _l_mask_mask_T_28; // @[Mux.scala:126:16] assign l_mask_1 = _l_mask_mask_T_29[7:0]; // @[Mux.scala:126:16] wire _l_forwarders_T_2 = wb_forward_ldq_idx_0 == 3'h1; // @[lsu.scala:1066:36, :1076:88] wire _l_forwarders_T_3 = wb_forward_valid_0 & _l_forwarders_T_2; // @[lsu.scala:1065:36, :1076:{63,88}] wire l_forwarders_1_0 = _l_forwarders_T_3; // @[lsu.scala:263:49, :1076:63] wire [2:0] l_forward_stq_idx_1 = l_forwarders_1_0 ? wb_forward_stq_idx_0 : ldq_1_bits_forward_stq_idx; // @[lsu.scala:208:16, :263:49, :1068:36, :1078:32] wire [33:0] _block_addr_matches_T_4 = ldq_1_bits_addr_bits[39:6]; // @[lsu.scala:208:16, :1081:84] wire _block_addr_matches_T_5 = _block_addr_matches_T_3 == _block_addr_matches_T_4; // @[lsu.scala:1081:{57,73,84}] wire block_addr_matches_1_0 = _block_addr_matches_T_5; // @[lsu.scala:263:49, :1081:73] wire [2:0] _dword_addr_matches_T_5 = ldq_1_bits_addr_bits[5:3]; // @[lsu.scala:208:16, :1082:110] wire _dword_addr_matches_T_6 = _dword_addr_matches_T_4 == _dword_addr_matches_T_5; // @[lsu.scala:1082:{81,100,110}] wire _dword_addr_matches_T_7 = block_addr_matches_1_0 & _dword_addr_matches_T_6; // @[lsu.scala:263:49, :1082:{66,100}] wire dword_addr_matches_1_0 = _dword_addr_matches_T_7; // @[lsu.scala:263:49, :1082:66] wire [7:0] _GEN_241 = l_mask_1 & lcam_mask_0; // @[lsu.scala:263:49, :1083:46, :1665:22] wire [7:0] _mask_match_T_2; // @[lsu.scala:1083:46] assign _mask_match_T_2 = _GEN_241; // @[lsu.scala:1083:46] wire [7:0] _mask_overlap_T_2; // @[lsu.scala:1084:46] assign _mask_overlap_T_2 = _GEN_241; // @[lsu.scala:1083:46, :1084:46] wire _mask_match_T_3 = _mask_match_T_2 == l_mask_1; // @[lsu.scala:1083:{46,62}, :1665:22] wire mask_match_1_0 = _mask_match_T_3; // @[lsu.scala:263:49, :1083:62] wire _mask_overlap_T_3 = |_mask_overlap_T_2; // @[lsu.scala:1084:{46,62}] wire mask_overlap_1_0 = _mask_overlap_T_3; // @[lsu.scala:263:49, :1084:62] wire _T_221 = do_release_search_0 & ldq_1_valid & ldq_1_bits_addr_valid & block_addr_matches_1_0; // @[lsu.scala:208:16, :263:49, :1089:34, :1090:34, :1091:34] wire _T_250 = ldq_1_bits_executed | ldq_1_bits_succeeded; // @[lsu.scala:208:16, :1099:37] wire [7:0] _T_229 = ldq_1_bits_st_dep_mask >> _GEN_230; // @[lsu.scala:208:16, :1101:38] wire _T_233 = do_st_search_0 & ldq_1_valid & ldq_1_bits_addr_valid & (_T_250 | l_forwarders_1_0) & ~ldq_1_bits_addr_is_virtual & _T_229[0] & dword_addr_matches_1_0 & mask_overlap_1_0; // @[lsu.scala:208:16, :263:49, :432:52, :1096:131, :1097:131, :1098:131, :1099:{37,57,131}, :1100:131, :1101:{38,131}, :1102:131] wire _forwarded_is_older_T_4 = l_forward_stq_idx_1 < lcam_stq_idx_0; // @[util.scala:363:52] wire _forwarded_is_older_T_5 = l_forward_stq_idx_1 < ldq_1_bits_youngest_stq_idx; // @[util.scala:363:64] wire _forwarded_is_older_T_6 = _forwarded_is_older_T_4 ^ _forwarded_is_older_T_5; // @[util.scala:363:{52,58,64}] wire _forwarded_is_older_T_7 = lcam_stq_idx_0 < ldq_1_bits_youngest_stq_idx; // @[util.scala:363:78] wire forwarded_is_older_1 = _forwarded_is_older_T_6 ^ _forwarded_is_older_T_7; // @[util.scala:363:{58,72,78}] wire _T_237 = ~ldq_1_bits_forward_std_val | l_forward_stq_idx_1 != lcam_stq_idx_0 & forwarded_is_older_1; // @[util.scala:363:72] wire _T_243 = do_ld_search_0 & ldq_1_valid & ldq_1_bits_addr_valid & ~ldq_1_bits_addr_is_virtual & dword_addr_matches_1_0 & mask_overlap_1_0; // @[lsu.scala:208:16, :263:49, :432:52, :1112:47, :1113:47, :1114:47, :1115:47, :1116:47] wire _searcher_is_older_T_6 = _searcher_is_older_T_4 ^ _searcher_is_older_T_5; // @[util.scala:363:{52,58,64}] wire _searcher_is_older_T_7 = |(ldq_head[2:1]); // @[util.scala:351:72, :363:78] wire searcher_is_older_1 = _searcher_is_older_T_6 ^ _searcher_is_older_T_7; // @[util.scala:363:{58,72,78}] wire _GEN_242 = _T_243 & searcher_is_older_1 & (_T_250 | l_forwarders_1_0) & ~s1_executing_loads_1 & ldq_1_bits_observed; // @[util.scala:363:72] assign failed_loads_1 = ~_T_221 & (_T_233 ? _T_237 : _GEN_242); // @[lsu.scala:303:5, :1054:34, :1089:34, :1090:34, :1091:34, :1092:36, :1096:131, :1097:131, :1098:131, :1099:131, :1100:131, :1101:131, :1102:131, :1103:37, :1107:39, :1108:76, :1117:37, :1119:34, :1120:74, :1121:40, :1122:34, :1123:36] reg older_nacked_REG_1; // @[lsu.scala:1129:57] wire older_nacked_1 = nacking_loads_1 | older_nacked_REG_1; // @[lsu.scala:1055:34, :1129:{47,57}] wire _T_252 = ~_T_250 | older_nacked_1; // @[lsu.scala:1099:37, :1129:47, :1130:{17,56}] wire _GEN_243 = searcher_is_older_1 | _GEN_234; // @[util.scala:363:72] wire _GEN_244 = _T_221 | _T_233; // @[lsu.scala:1089:34, :1090:34, :1091:34, :1092:36, :1096:131, :1097:131, :1098:131, :1099:131, :1100:131, :1101:131, :1102:131, :1103:37, :1117:37] reg io_dmem_s1_kill_0_REG_1; // @[lsu.scala:1132:58] wire _GEN_245 = _GEN_244 | ~_T_243 | _GEN_243 | ~_T_252; // @[lsu.scala:1092:36, :1103:37, :1112:47, :1113:47, :1114:47, :1115:47, :1116:47, :1117:37, :1119:34, :1126:{38,47}, :1130:{56,73}] wire [7:0] l_mask_2; // @[lsu.scala:1665:22] wire _l_mask_mask_T_30 = ldq_2_bits_uop_mem_size == 2'h0; // @[lsu.scala:208:16, :1667:26] wire [2:0] _l_mask_mask_T_31 = ldq_2_bits_addr_bits[2:0]; // @[lsu.scala:208:16, :1667:55] wire [14:0] _l_mask_mask_T_32 = 15'h1 << _l_mask_mask_T_31; // @[lsu.scala:1667:{48,55}] wire _l_mask_mask_T_33 = ldq_2_bits_uop_mem_size == 2'h1; // @[lsu.scala:208:16, :1668:26] wire [1:0] _l_mask_mask_T_34 = ldq_2_bits_addr_bits[2:1]; // @[lsu.scala:208:16, :1668:56] wire [2:0] _l_mask_mask_T_35 = {_l_mask_mask_T_34, 1'h0}; // @[lsu.scala:1668:{56,62}] wire [14:0] _l_mask_mask_T_36 = 15'h3 << _l_mask_mask_T_35; // @[lsu.scala:1668:{48,62}] wire _l_mask_mask_T_37 = ldq_2_bits_uop_mem_size == 2'h2; // @[lsu.scala:208:16, :1669:26] wire _l_mask_mask_T_38 = ldq_2_bits_addr_bits[2]; // @[lsu.scala:208:16, :1669:46] wire [7:0] _l_mask_mask_T_39 = _l_mask_mask_T_38 ? 8'hF0 : 8'hF; // @[lsu.scala:1669:{41,46}] wire _l_mask_mask_T_40 = &ldq_2_bits_uop_mem_size; // @[lsu.scala:208:16, :1670:26] wire [7:0] _l_mask_mask_T_42 = _l_mask_mask_T_37 ? _l_mask_mask_T_39 : 8'hFF; // @[Mux.scala:126:16] wire [14:0] _l_mask_mask_T_43 = _l_mask_mask_T_33 ? _l_mask_mask_T_36 : {7'h0, _l_mask_mask_T_42}; // @[Mux.scala:126:16] wire [14:0] _l_mask_mask_T_44 = _l_mask_mask_T_30 ? _l_mask_mask_T_32 : _l_mask_mask_T_43; // @[Mux.scala:126:16] assign l_mask_2 = _l_mask_mask_T_44[7:0]; // @[Mux.scala:126:16] wire _l_forwarders_T_4 = wb_forward_ldq_idx_0 == 3'h2; // @[lsu.scala:1066:36, :1076:88] wire _l_forwarders_T_5 = wb_forward_valid_0 & _l_forwarders_T_4; // @[lsu.scala:1065:36, :1076:{63,88}] wire l_forwarders_2_0 = _l_forwarders_T_5; // @[lsu.scala:263:49, :1076:63] wire [2:0] l_forward_stq_idx_2 = l_forwarders_2_0 ? wb_forward_stq_idx_0 : ldq_2_bits_forward_stq_idx; // @[lsu.scala:208:16, :263:49, :1068:36, :1078:32] wire [33:0] _block_addr_matches_T_7 = ldq_2_bits_addr_bits[39:6]; // @[lsu.scala:208:16, :1081:84] wire _block_addr_matches_T_8 = _block_addr_matches_T_6 == _block_addr_matches_T_7; // @[lsu.scala:1081:{57,73,84}] wire block_addr_matches_2_0 = _block_addr_matches_T_8; // @[lsu.scala:263:49, :1081:73] wire [2:0] _dword_addr_matches_T_9 = ldq_2_bits_addr_bits[5:3]; // @[lsu.scala:208:16, :1082:110] wire _dword_addr_matches_T_10 = _dword_addr_matches_T_8 == _dword_addr_matches_T_9; // @[lsu.scala:1082:{81,100,110}] wire _dword_addr_matches_T_11 = block_addr_matches_2_0 & _dword_addr_matches_T_10; // @[lsu.scala:263:49, :1082:{66,100}] wire dword_addr_matches_2_0 = _dword_addr_matches_T_11; // @[lsu.scala:263:49, :1082:66] wire [7:0] _GEN_246 = l_mask_2 & lcam_mask_0; // @[lsu.scala:263:49, :1083:46, :1665:22] wire [7:0] _mask_match_T_4; // @[lsu.scala:1083:46] assign _mask_match_T_4 = _GEN_246; // @[lsu.scala:1083:46] wire [7:0] _mask_overlap_T_4; // @[lsu.scala:1084:46] assign _mask_overlap_T_4 = _GEN_246; // @[lsu.scala:1083:46, :1084:46] wire _mask_match_T_5 = _mask_match_T_4 == l_mask_2; // @[lsu.scala:1083:{46,62}, :1665:22] wire mask_match_2_0 = _mask_match_T_5; // @[lsu.scala:263:49, :1083:62] wire _mask_overlap_T_5 = |_mask_overlap_T_4; // @[lsu.scala:1084:{46,62}] wire mask_overlap_2_0 = _mask_overlap_T_5; // @[lsu.scala:263:49, :1084:62] wire _T_257 = do_release_search_0 & ldq_2_valid & ldq_2_bits_addr_valid & block_addr_matches_2_0; // @[lsu.scala:208:16, :263:49, :1089:34, :1090:34, :1091:34] wire _T_286 = ldq_2_bits_executed | ldq_2_bits_succeeded; // @[lsu.scala:208:16, :1099:37] wire [7:0] _T_265 = ldq_2_bits_st_dep_mask >> _GEN_230; // @[lsu.scala:208:16, :1101:38] wire _T_269 = do_st_search_0 & ldq_2_valid & ldq_2_bits_addr_valid & (_T_286 | l_forwarders_2_0) & ~ldq_2_bits_addr_is_virtual & _T_265[0] & dword_addr_matches_2_0 & mask_overlap_2_0; // @[lsu.scala:208:16, :263:49, :432:52, :1096:131, :1097:131, :1098:131, :1099:{37,57,131}, :1100:131, :1101:{38,131}, :1102:131] wire _forwarded_is_older_T_8 = l_forward_stq_idx_2 < lcam_stq_idx_0; // @[util.scala:363:52] wire _forwarded_is_older_T_9 = l_forward_stq_idx_2 < ldq_2_bits_youngest_stq_idx; // @[util.scala:363:64] wire _forwarded_is_older_T_10 = _forwarded_is_older_T_8 ^ _forwarded_is_older_T_9; // @[util.scala:363:{52,58,64}] wire _forwarded_is_older_T_11 = lcam_stq_idx_0 < ldq_2_bits_youngest_stq_idx; // @[util.scala:363:78] wire forwarded_is_older_2 = _forwarded_is_older_T_10 ^ _forwarded_is_older_T_11; // @[util.scala:363:{58,72,78}] wire _T_273 = ~ldq_2_bits_forward_std_val | l_forward_stq_idx_2 != lcam_stq_idx_0 & forwarded_is_older_2; // @[util.scala:363:72] wire _T_279 = do_ld_search_0 & ldq_2_valid & ldq_2_bits_addr_valid & ~ldq_2_bits_addr_is_virtual & dword_addr_matches_2_0 & mask_overlap_2_0; // @[lsu.scala:208:16, :263:49, :432:52, :1112:47, :1113:47, :1114:47, :1115:47, :1116:47] wire _searcher_is_older_T_8 = lcam_ldq_idx_0 < 3'h2; // @[util.scala:363:52] wire _searcher_is_older_T_10 = _searcher_is_older_T_8 ^ _searcher_is_older_T_9; // @[util.scala:363:{52,58,64}] wire _searcher_is_older_T_11 = ldq_head > 3'h2; // @[util.scala:363:78] wire searcher_is_older_2 = _searcher_is_older_T_10 ^ _searcher_is_older_T_11; // @[util.scala:363:{58,72,78}] wire _GEN_247 = _T_279 & searcher_is_older_2 & (_T_286 | l_forwarders_2_0) & ~s1_executing_loads_2 & ldq_2_bits_observed; // @[util.scala:363:72] assign failed_loads_2 = ~_T_257 & (_T_269 ? _T_273 : _GEN_247); // @[lsu.scala:303:5, :1054:34, :1089:34, :1090:34, :1091:34, :1092:36, :1096:131, :1097:131, :1098:131, :1099:131, :1100:131, :1101:131, :1102:131, :1103:37, :1107:39, :1108:76, :1117:37, :1119:34, :1120:74, :1121:40, :1122:34, :1123:36] reg older_nacked_REG_2; // @[lsu.scala:1129:57] wire older_nacked_2 = nacking_loads_2 | older_nacked_REG_2; // @[lsu.scala:1055:34, :1129:{47,57}] wire _T_288 = ~_T_286 | older_nacked_2; // @[lsu.scala:1099:37, :1129:47, :1130:{17,56}] wire _GEN_248 = searcher_is_older_2 | _GEN_235; // @[util.scala:363:72] wire _GEN_249 = _T_257 | _T_269; // @[lsu.scala:1089:34, :1090:34, :1091:34, :1092:36, :1096:131, :1097:131, :1098:131, :1099:131, :1100:131, :1101:131, :1102:131, :1103:37, :1117:37] reg io_dmem_s1_kill_0_REG_2; // @[lsu.scala:1132:58] wire _GEN_250 = _GEN_249 | ~_T_279 | _GEN_248 | ~_T_288; // @[lsu.scala:1092:36, :1103:37, :1112:47, :1113:47, :1114:47, :1115:47, :1116:47, :1117:37, :1119:34, :1126:{38,47}, :1130:{56,73}] wire [7:0] l_mask_3; // @[lsu.scala:1665:22] wire _l_mask_mask_T_45 = ldq_3_bits_uop_mem_size == 2'h0; // @[lsu.scala:208:16, :1667:26] wire [2:0] _l_mask_mask_T_46 = ldq_3_bits_addr_bits[2:0]; // @[lsu.scala:208:16, :1667:55] wire [14:0] _l_mask_mask_T_47 = 15'h1 << _l_mask_mask_T_46; // @[lsu.scala:1667:{48,55}] wire _l_mask_mask_T_48 = ldq_3_bits_uop_mem_size == 2'h1; // @[lsu.scala:208:16, :1668:26] wire [1:0] _l_mask_mask_T_49 = ldq_3_bits_addr_bits[2:1]; // @[lsu.scala:208:16, :1668:56] wire [2:0] _l_mask_mask_T_50 = {_l_mask_mask_T_49, 1'h0}; // @[lsu.scala:1668:{56,62}] wire [14:0] _l_mask_mask_T_51 = 15'h3 << _l_mask_mask_T_50; // @[lsu.scala:1668:{48,62}] wire _l_mask_mask_T_52 = ldq_3_bits_uop_mem_size == 2'h2; // @[lsu.scala:208:16, :1669:26] wire _l_mask_mask_T_53 = ldq_3_bits_addr_bits[2]; // @[lsu.scala:208:16, :1669:46] wire [7:0] _l_mask_mask_T_54 = _l_mask_mask_T_53 ? 8'hF0 : 8'hF; // @[lsu.scala:1669:{41,46}] wire _l_mask_mask_T_55 = &ldq_3_bits_uop_mem_size; // @[lsu.scala:208:16, :1670:26] wire [7:0] _l_mask_mask_T_57 = _l_mask_mask_T_52 ? _l_mask_mask_T_54 : 8'hFF; // @[Mux.scala:126:16] wire [14:0] _l_mask_mask_T_58 = _l_mask_mask_T_48 ? _l_mask_mask_T_51 : {7'h0, _l_mask_mask_T_57}; // @[Mux.scala:126:16] wire [14:0] _l_mask_mask_T_59 = _l_mask_mask_T_45 ? _l_mask_mask_T_47 : _l_mask_mask_T_58; // @[Mux.scala:126:16] assign l_mask_3 = _l_mask_mask_T_59[7:0]; // @[Mux.scala:126:16] wire _l_forwarders_T_6 = wb_forward_ldq_idx_0 == 3'h3; // @[lsu.scala:1066:36, :1076:88] wire _l_forwarders_T_7 = wb_forward_valid_0 & _l_forwarders_T_6; // @[lsu.scala:1065:36, :1076:{63,88}] wire l_forwarders_3_0 = _l_forwarders_T_7; // @[lsu.scala:263:49, :1076:63] wire [2:0] l_forward_stq_idx_3 = l_forwarders_3_0 ? wb_forward_stq_idx_0 : ldq_3_bits_forward_stq_idx; // @[lsu.scala:208:16, :263:49, :1068:36, :1078:32] wire [33:0] _block_addr_matches_T_10 = ldq_3_bits_addr_bits[39:6]; // @[lsu.scala:208:16, :1081:84] wire _block_addr_matches_T_11 = _block_addr_matches_T_9 == _block_addr_matches_T_10; // @[lsu.scala:1081:{57,73,84}] wire block_addr_matches_3_0 = _block_addr_matches_T_11; // @[lsu.scala:263:49, :1081:73] wire [2:0] _dword_addr_matches_T_13 = ldq_3_bits_addr_bits[5:3]; // @[lsu.scala:208:16, :1082:110] wire _dword_addr_matches_T_14 = _dword_addr_matches_T_12 == _dword_addr_matches_T_13; // @[lsu.scala:1082:{81,100,110}] wire _dword_addr_matches_T_15 = block_addr_matches_3_0 & _dword_addr_matches_T_14; // @[lsu.scala:263:49, :1082:{66,100}] wire dword_addr_matches_3_0 = _dword_addr_matches_T_15; // @[lsu.scala:263:49, :1082:66] wire [7:0] _GEN_251 = l_mask_3 & lcam_mask_0; // @[lsu.scala:263:49, :1083:46, :1665:22] wire [7:0] _mask_match_T_6; // @[lsu.scala:1083:46] assign _mask_match_T_6 = _GEN_251; // @[lsu.scala:1083:46] wire [7:0] _mask_overlap_T_6; // @[lsu.scala:1084:46] assign _mask_overlap_T_6 = _GEN_251; // @[lsu.scala:1083:46, :1084:46] wire _mask_match_T_7 = _mask_match_T_6 == l_mask_3; // @[lsu.scala:1083:{46,62}, :1665:22] wire mask_match_3_0 = _mask_match_T_7; // @[lsu.scala:263:49, :1083:62] wire _mask_overlap_T_7 = |_mask_overlap_T_6; // @[lsu.scala:1084:{46,62}] wire mask_overlap_3_0 = _mask_overlap_T_7; // @[lsu.scala:263:49, :1084:62] wire _T_293 = do_release_search_0 & ldq_3_valid & ldq_3_bits_addr_valid & block_addr_matches_3_0; // @[lsu.scala:208:16, :263:49, :1089:34, :1090:34, :1091:34] wire _T_322 = ldq_3_bits_executed | ldq_3_bits_succeeded; // @[lsu.scala:208:16, :1099:37] wire [7:0] _T_301 = ldq_3_bits_st_dep_mask >> _GEN_230; // @[lsu.scala:208:16, :1101:38] wire _T_305 = do_st_search_0 & ldq_3_valid & ldq_3_bits_addr_valid & (_T_322 | l_forwarders_3_0) & ~ldq_3_bits_addr_is_virtual & _T_301[0] & dword_addr_matches_3_0 & mask_overlap_3_0; // @[lsu.scala:208:16, :263:49, :432:52, :1096:131, :1097:131, :1098:131, :1099:{37,57,131}, :1100:131, :1101:{38,131}, :1102:131] wire _forwarded_is_older_T_12 = l_forward_stq_idx_3 < lcam_stq_idx_0; // @[util.scala:363:52] wire _forwarded_is_older_T_13 = l_forward_stq_idx_3 < ldq_3_bits_youngest_stq_idx; // @[util.scala:363:64] wire _forwarded_is_older_T_14 = _forwarded_is_older_T_12 ^ _forwarded_is_older_T_13; // @[util.scala:363:{52,58,64}] wire _forwarded_is_older_T_15 = lcam_stq_idx_0 < ldq_3_bits_youngest_stq_idx; // @[util.scala:363:78] wire forwarded_is_older_3 = _forwarded_is_older_T_14 ^ _forwarded_is_older_T_15; // @[util.scala:363:{58,72,78}] wire _T_309 = ~ldq_3_bits_forward_std_val | l_forward_stq_idx_3 != lcam_stq_idx_0 & forwarded_is_older_3; // @[util.scala:363:72] wire _T_315 = do_ld_search_0 & ldq_3_valid & ldq_3_bits_addr_valid & ~ldq_3_bits_addr_is_virtual & dword_addr_matches_3_0 & mask_overlap_3_0; // @[lsu.scala:208:16, :263:49, :432:52, :1112:47, :1113:47, :1114:47, :1115:47, :1116:47] wire _searcher_is_older_T_12 = lcam_ldq_idx_0 < 3'h3; // @[util.scala:363:52] wire _searcher_is_older_T_14 = _searcher_is_older_T_12 ^ _searcher_is_older_T_13; // @[util.scala:363:{52,58,64}] wire searcher_is_older_3 = _searcher_is_older_T_14 ^ _searcher_is_older_T_15; // @[util.scala:363:{58,72,78}] wire _GEN_252 = _T_315 & searcher_is_older_3 & (_T_322 | l_forwarders_3_0) & ~s1_executing_loads_3 & ldq_3_bits_observed; // @[util.scala:363:72] assign failed_loads_3 = ~_T_293 & (_T_305 ? _T_309 : _GEN_252); // @[lsu.scala:303:5, :1054:34, :1089:34, :1090:34, :1091:34, :1092:36, :1096:131, :1097:131, :1098:131, :1099:131, :1100:131, :1101:131, :1102:131, :1103:37, :1107:39, :1108:76, :1117:37, :1119:34, :1120:74, :1121:40, :1122:34, :1123:36] reg older_nacked_REG_3; // @[lsu.scala:1129:57] wire older_nacked_3 = nacking_loads_3 | older_nacked_REG_3; // @[lsu.scala:1055:34, :1129:{47,57}] wire _T_324 = ~_T_322 | older_nacked_3; // @[lsu.scala:1099:37, :1129:47, :1130:{17,56}] wire _GEN_253 = searcher_is_older_3 | _GEN_236; // @[util.scala:363:72] wire _GEN_254 = _T_293 | _T_305; // @[lsu.scala:1089:34, :1090:34, :1091:34, :1092:36, :1096:131, :1097:131, :1098:131, :1099:131, :1100:131, :1101:131, :1102:131, :1103:37, :1117:37] reg io_dmem_s1_kill_0_REG_3; // @[lsu.scala:1132:58] wire _GEN_255 = _GEN_254 | ~_T_315 | _GEN_253 | ~_T_324; // @[lsu.scala:1092:36, :1103:37, :1112:47, :1113:47, :1114:47, :1115:47, :1116:47, :1117:37, :1119:34, :1126:{38,47}, :1130:{56,73}] wire [7:0] l_mask_4; // @[lsu.scala:1665:22] wire _l_mask_mask_T_60 = ldq_4_bits_uop_mem_size == 2'h0; // @[lsu.scala:208:16, :1667:26] wire [2:0] _l_mask_mask_T_61 = ldq_4_bits_addr_bits[2:0]; // @[lsu.scala:208:16, :1667:55] wire [14:0] _l_mask_mask_T_62 = 15'h1 << _l_mask_mask_T_61; // @[lsu.scala:1667:{48,55}] wire _l_mask_mask_T_63 = ldq_4_bits_uop_mem_size == 2'h1; // @[lsu.scala:208:16, :1668:26] wire [1:0] _l_mask_mask_T_64 = ldq_4_bits_addr_bits[2:1]; // @[lsu.scala:208:16, :1668:56] wire [2:0] _l_mask_mask_T_65 = {_l_mask_mask_T_64, 1'h0}; // @[lsu.scala:1668:{56,62}] wire [14:0] _l_mask_mask_T_66 = 15'h3 << _l_mask_mask_T_65; // @[lsu.scala:1668:{48,62}] wire _l_mask_mask_T_67 = ldq_4_bits_uop_mem_size == 2'h2; // @[lsu.scala:208:16, :1669:26] wire _l_mask_mask_T_68 = ldq_4_bits_addr_bits[2]; // @[lsu.scala:208:16, :1669:46] wire [7:0] _l_mask_mask_T_69 = _l_mask_mask_T_68 ? 8'hF0 : 8'hF; // @[lsu.scala:1669:{41,46}] wire _l_mask_mask_T_70 = &ldq_4_bits_uop_mem_size; // @[lsu.scala:208:16, :1670:26] wire [7:0] _l_mask_mask_T_72 = _l_mask_mask_T_67 ? _l_mask_mask_T_69 : 8'hFF; // @[Mux.scala:126:16] wire [14:0] _l_mask_mask_T_73 = _l_mask_mask_T_63 ? _l_mask_mask_T_66 : {7'h0, _l_mask_mask_T_72}; // @[Mux.scala:126:16] wire [14:0] _l_mask_mask_T_74 = _l_mask_mask_T_60 ? _l_mask_mask_T_62 : _l_mask_mask_T_73; // @[Mux.scala:126:16] assign l_mask_4 = _l_mask_mask_T_74[7:0]; // @[Mux.scala:126:16] wire _l_forwarders_T_8 = wb_forward_ldq_idx_0 == 3'h4; // @[lsu.scala:1066:36, :1076:88] wire _l_forwarders_T_9 = wb_forward_valid_0 & _l_forwarders_T_8; // @[lsu.scala:1065:36, :1076:{63,88}] wire l_forwarders_4_0 = _l_forwarders_T_9; // @[lsu.scala:263:49, :1076:63] wire [2:0] l_forward_stq_idx_4 = l_forwarders_4_0 ? wb_forward_stq_idx_0 : ldq_4_bits_forward_stq_idx; // @[lsu.scala:208:16, :263:49, :1068:36, :1078:32] wire [33:0] _block_addr_matches_T_13 = ldq_4_bits_addr_bits[39:6]; // @[lsu.scala:208:16, :1081:84] wire _block_addr_matches_T_14 = _block_addr_matches_T_12 == _block_addr_matches_T_13; // @[lsu.scala:1081:{57,73,84}] wire block_addr_matches_4_0 = _block_addr_matches_T_14; // @[lsu.scala:263:49, :1081:73] wire [2:0] _dword_addr_matches_T_17 = ldq_4_bits_addr_bits[5:3]; // @[lsu.scala:208:16, :1082:110] wire _dword_addr_matches_T_18 = _dword_addr_matches_T_16 == _dword_addr_matches_T_17; // @[lsu.scala:1082:{81,100,110}] wire _dword_addr_matches_T_19 = block_addr_matches_4_0 & _dword_addr_matches_T_18; // @[lsu.scala:263:49, :1082:{66,100}] wire dword_addr_matches_4_0 = _dword_addr_matches_T_19; // @[lsu.scala:263:49, :1082:66] wire [7:0] _GEN_256 = l_mask_4 & lcam_mask_0; // @[lsu.scala:263:49, :1083:46, :1665:22] wire [7:0] _mask_match_T_8; // @[lsu.scala:1083:46] assign _mask_match_T_8 = _GEN_256; // @[lsu.scala:1083:46] wire [7:0] _mask_overlap_T_8; // @[lsu.scala:1084:46] assign _mask_overlap_T_8 = _GEN_256; // @[lsu.scala:1083:46, :1084:46] wire _mask_match_T_9 = _mask_match_T_8 == l_mask_4; // @[lsu.scala:1083:{46,62}, :1665:22] wire mask_match_4_0 = _mask_match_T_9; // @[lsu.scala:263:49, :1083:62] wire _mask_overlap_T_9 = |_mask_overlap_T_8; // @[lsu.scala:1084:{46,62}] wire mask_overlap_4_0 = _mask_overlap_T_9; // @[lsu.scala:263:49, :1084:62] wire _T_329 = do_release_search_0 & ldq_4_valid & ldq_4_bits_addr_valid & block_addr_matches_4_0; // @[lsu.scala:208:16, :263:49, :1089:34, :1090:34, :1091:34] wire _T_358 = ldq_4_bits_executed | ldq_4_bits_succeeded; // @[lsu.scala:208:16, :1099:37] wire [7:0] _T_337 = ldq_4_bits_st_dep_mask >> _GEN_230; // @[lsu.scala:208:16, :1101:38] wire _T_341 = do_st_search_0 & ldq_4_valid & ldq_4_bits_addr_valid & (_T_358 | l_forwarders_4_0) & ~ldq_4_bits_addr_is_virtual & _T_337[0] & dword_addr_matches_4_0 & mask_overlap_4_0; // @[lsu.scala:208:16, :263:49, :432:52, :1096:131, :1097:131, :1098:131, :1099:{37,57,131}, :1100:131, :1101:{38,131}, :1102:131] wire _forwarded_is_older_T_16 = l_forward_stq_idx_4 < lcam_stq_idx_0; // @[util.scala:363:52] wire _forwarded_is_older_T_17 = l_forward_stq_idx_4 < ldq_4_bits_youngest_stq_idx; // @[util.scala:363:64] wire _forwarded_is_older_T_18 = _forwarded_is_older_T_16 ^ _forwarded_is_older_T_17; // @[util.scala:363:{52,58,64}] wire _forwarded_is_older_T_19 = lcam_stq_idx_0 < ldq_4_bits_youngest_stq_idx; // @[util.scala:363:78] wire forwarded_is_older_4 = _forwarded_is_older_T_18 ^ _forwarded_is_older_T_19; // @[util.scala:363:{58,72,78}] wire _T_345 = ~ldq_4_bits_forward_std_val | l_forward_stq_idx_4 != lcam_stq_idx_0 & forwarded_is_older_4; // @[util.scala:363:72] wire _T_351 = do_ld_search_0 & ldq_4_valid & ldq_4_bits_addr_valid & ~ldq_4_bits_addr_is_virtual & dword_addr_matches_4_0 & mask_overlap_4_0; // @[lsu.scala:208:16, :263:49, :432:52, :1112:47, :1113:47, :1114:47, :1115:47, :1116:47] wire _searcher_is_older_T_16 = ~(lcam_ldq_idx_0[2]); // @[util.scala:363:52] wire _searcher_is_older_T_18 = _searcher_is_older_T_16 ^ _searcher_is_older_T_17; // @[util.scala:363:{52,58,64}] wire _searcher_is_older_T_19 = ldq_head > 3'h4; // @[util.scala:363:78] wire searcher_is_older_4 = _searcher_is_older_T_18 ^ _searcher_is_older_T_19; // @[util.scala:363:{58,72,78}] wire _GEN_257 = _T_351 & searcher_is_older_4 & (_T_358 | l_forwarders_4_0) & ~s1_executing_loads_4 & ldq_4_bits_observed; // @[util.scala:363:72] assign failed_loads_4 = ~_T_329 & (_T_341 ? _T_345 : _GEN_257); // @[lsu.scala:303:5, :1054:34, :1089:34, :1090:34, :1091:34, :1092:36, :1096:131, :1097:131, :1098:131, :1099:131, :1100:131, :1101:131, :1102:131, :1103:37, :1107:39, :1108:76, :1117:37, :1119:34, :1120:74, :1121:40, :1122:34, :1123:36] reg older_nacked_REG_4; // @[lsu.scala:1129:57] wire older_nacked_4 = nacking_loads_4 | older_nacked_REG_4; // @[lsu.scala:1055:34, :1129:{47,57}] wire _T_360 = ~_T_358 | older_nacked_4; // @[lsu.scala:1099:37, :1129:47, :1130:{17,56}] wire _GEN_258 = searcher_is_older_4 | _GEN_237; // @[util.scala:363:72] wire _GEN_259 = _T_329 | _T_341; // @[lsu.scala:1089:34, :1090:34, :1091:34, :1092:36, :1096:131, :1097:131, :1098:131, :1099:131, :1100:131, :1101:131, :1102:131, :1103:37, :1117:37] reg io_dmem_s1_kill_0_REG_4; // @[lsu.scala:1132:58] wire _GEN_260 = _GEN_259 | ~_T_351 | _GEN_258 | ~_T_360; // @[lsu.scala:1092:36, :1103:37, :1112:47, :1113:47, :1114:47, :1115:47, :1116:47, :1117:37, :1119:34, :1126:{38,47}, :1130:{56,73}] wire [7:0] l_mask_5; // @[lsu.scala:1665:22] wire _l_mask_mask_T_75 = ldq_5_bits_uop_mem_size == 2'h0; // @[lsu.scala:208:16, :1667:26] wire [2:0] _l_mask_mask_T_76 = ldq_5_bits_addr_bits[2:0]; // @[lsu.scala:208:16, :1667:55] wire [14:0] _l_mask_mask_T_77 = 15'h1 << _l_mask_mask_T_76; // @[lsu.scala:1667:{48,55}] wire _l_mask_mask_T_78 = ldq_5_bits_uop_mem_size == 2'h1; // @[lsu.scala:208:16, :1668:26] wire [1:0] _l_mask_mask_T_79 = ldq_5_bits_addr_bits[2:1]; // @[lsu.scala:208:16, :1668:56] wire [2:0] _l_mask_mask_T_80 = {_l_mask_mask_T_79, 1'h0}; // @[lsu.scala:1668:{56,62}] wire [14:0] _l_mask_mask_T_81 = 15'h3 << _l_mask_mask_T_80; // @[lsu.scala:1668:{48,62}] wire _l_mask_mask_T_82 = ldq_5_bits_uop_mem_size == 2'h2; // @[lsu.scala:208:16, :1669:26] wire _l_mask_mask_T_83 = ldq_5_bits_addr_bits[2]; // @[lsu.scala:208:16, :1669:46] wire [7:0] _l_mask_mask_T_84 = _l_mask_mask_T_83 ? 8'hF0 : 8'hF; // @[lsu.scala:1669:{41,46}] wire _l_mask_mask_T_85 = &ldq_5_bits_uop_mem_size; // @[lsu.scala:208:16, :1670:26] wire [7:0] _l_mask_mask_T_87 = _l_mask_mask_T_82 ? _l_mask_mask_T_84 : 8'hFF; // @[Mux.scala:126:16] wire [14:0] _l_mask_mask_T_88 = _l_mask_mask_T_78 ? _l_mask_mask_T_81 : {7'h0, _l_mask_mask_T_87}; // @[Mux.scala:126:16] wire [14:0] _l_mask_mask_T_89 = _l_mask_mask_T_75 ? _l_mask_mask_T_77 : _l_mask_mask_T_88; // @[Mux.scala:126:16] assign l_mask_5 = _l_mask_mask_T_89[7:0]; // @[Mux.scala:126:16] wire _l_forwarders_T_10 = wb_forward_ldq_idx_0 == 3'h5; // @[lsu.scala:1066:36, :1076:88] wire _l_forwarders_T_11 = wb_forward_valid_0 & _l_forwarders_T_10; // @[lsu.scala:1065:36, :1076:{63,88}] wire l_forwarders_5_0 = _l_forwarders_T_11; // @[lsu.scala:263:49, :1076:63] wire [2:0] l_forward_stq_idx_5 = l_forwarders_5_0 ? wb_forward_stq_idx_0 : ldq_5_bits_forward_stq_idx; // @[lsu.scala:208:16, :263:49, :1068:36, :1078:32] wire [33:0] _block_addr_matches_T_16 = ldq_5_bits_addr_bits[39:6]; // @[lsu.scala:208:16, :1081:84] wire _block_addr_matches_T_17 = _block_addr_matches_T_15 == _block_addr_matches_T_16; // @[lsu.scala:1081:{57,73,84}] wire block_addr_matches_5_0 = _block_addr_matches_T_17; // @[lsu.scala:263:49, :1081:73] wire [2:0] _dword_addr_matches_T_21 = ldq_5_bits_addr_bits[5:3]; // @[lsu.scala:208:16, :1082:110] wire _dword_addr_matches_T_22 = _dword_addr_matches_T_20 == _dword_addr_matches_T_21; // @[lsu.scala:1082:{81,100,110}] wire _dword_addr_matches_T_23 = block_addr_matches_5_0 & _dword_addr_matches_T_22; // @[lsu.scala:263:49, :1082:{66,100}] wire dword_addr_matches_5_0 = _dword_addr_matches_T_23; // @[lsu.scala:263:49, :1082:66] wire [7:0] _GEN_261 = l_mask_5 & lcam_mask_0; // @[lsu.scala:263:49, :1083:46, :1665:22] wire [7:0] _mask_match_T_10; // @[lsu.scala:1083:46] assign _mask_match_T_10 = _GEN_261; // @[lsu.scala:1083:46] wire [7:0] _mask_overlap_T_10; // @[lsu.scala:1084:46] assign _mask_overlap_T_10 = _GEN_261; // @[lsu.scala:1083:46, :1084:46] wire _mask_match_T_11 = _mask_match_T_10 == l_mask_5; // @[lsu.scala:1083:{46,62}, :1665:22] wire mask_match_5_0 = _mask_match_T_11; // @[lsu.scala:263:49, :1083:62] wire _mask_overlap_T_11 = |_mask_overlap_T_10; // @[lsu.scala:1084:{46,62}] wire mask_overlap_5_0 = _mask_overlap_T_11; // @[lsu.scala:263:49, :1084:62] wire _T_365 = do_release_search_0 & ldq_5_valid & ldq_5_bits_addr_valid & block_addr_matches_5_0; // @[lsu.scala:208:16, :263:49, :1089:34, :1090:34, :1091:34] wire _T_394 = ldq_5_bits_executed | ldq_5_bits_succeeded; // @[lsu.scala:208:16, :1099:37] wire [7:0] _T_373 = ldq_5_bits_st_dep_mask >> _GEN_230; // @[lsu.scala:208:16, :1101:38] wire _T_377 = do_st_search_0 & ldq_5_valid & ldq_5_bits_addr_valid & (_T_394 | l_forwarders_5_0) & ~ldq_5_bits_addr_is_virtual & _T_373[0] & dword_addr_matches_5_0 & mask_overlap_5_0; // @[lsu.scala:208:16, :263:49, :432:52, :1096:131, :1097:131, :1098:131, :1099:{37,57,131}, :1100:131, :1101:{38,131}, :1102:131] wire _forwarded_is_older_T_20 = l_forward_stq_idx_5 < lcam_stq_idx_0; // @[util.scala:363:52] wire _forwarded_is_older_T_21 = l_forward_stq_idx_5 < ldq_5_bits_youngest_stq_idx; // @[util.scala:363:64] wire _forwarded_is_older_T_22 = _forwarded_is_older_T_20 ^ _forwarded_is_older_T_21; // @[util.scala:363:{52,58,64}] wire _forwarded_is_older_T_23 = lcam_stq_idx_0 < ldq_5_bits_youngest_stq_idx; // @[util.scala:363:78] wire forwarded_is_older_5 = _forwarded_is_older_T_22 ^ _forwarded_is_older_T_23; // @[util.scala:363:{58,72,78}] wire _T_381 = ~ldq_5_bits_forward_std_val | l_forward_stq_idx_5 != lcam_stq_idx_0 & forwarded_is_older_5; // @[util.scala:363:72] wire _T_387 = do_ld_search_0 & ldq_5_valid & ldq_5_bits_addr_valid & ~ldq_5_bits_addr_is_virtual & dword_addr_matches_5_0 & mask_overlap_5_0; // @[lsu.scala:208:16, :263:49, :432:52, :1112:47, :1113:47, :1114:47, :1115:47, :1116:47] wire _searcher_is_older_T_20 = lcam_ldq_idx_0 < 3'h5; // @[util.scala:363:52] wire _searcher_is_older_T_22 = _searcher_is_older_T_20 ^ _searcher_is_older_T_21; // @[util.scala:363:{52,58,64}] wire _searcher_is_older_T_23 = ldq_head > 3'h5; // @[util.scala:363:78] wire searcher_is_older_5 = _searcher_is_older_T_22 ^ _searcher_is_older_T_23; // @[util.scala:363:{58,72,78}] wire _GEN_262 = _T_387 & searcher_is_older_5 & (_T_394 | l_forwarders_5_0) & ~s1_executing_loads_5 & ldq_5_bits_observed; // @[util.scala:363:72] assign failed_loads_5 = ~_T_365 & (_T_377 ? _T_381 : _GEN_262); // @[lsu.scala:303:5, :1054:34, :1089:34, :1090:34, :1091:34, :1092:36, :1096:131, :1097:131, :1098:131, :1099:131, :1100:131, :1101:131, :1102:131, :1103:37, :1107:39, :1108:76, :1117:37, :1119:34, :1120:74, :1121:40, :1122:34, :1123:36] reg older_nacked_REG_5; // @[lsu.scala:1129:57] wire older_nacked_5 = nacking_loads_5 | older_nacked_REG_5; // @[lsu.scala:1055:34, :1129:{47,57}] wire _T_396 = ~_T_394 | older_nacked_5; // @[lsu.scala:1099:37, :1129:47, :1130:{17,56}] wire _GEN_263 = searcher_is_older_5 | _GEN_238; // @[util.scala:363:72] wire _GEN_264 = _T_365 | _T_377; // @[lsu.scala:1089:34, :1090:34, :1091:34, :1092:36, :1096:131, :1097:131, :1098:131, :1099:131, :1100:131, :1101:131, :1102:131, :1103:37, :1117:37] reg io_dmem_s1_kill_0_REG_5; // @[lsu.scala:1132:58] wire _GEN_265 = _GEN_264 | ~_T_387 | _GEN_263 | ~_T_396; // @[lsu.scala:1092:36, :1103:37, :1112:47, :1113:47, :1114:47, :1115:47, :1116:47, :1117:37, :1119:34, :1126:{38,47}, :1130:{56,73}] wire [7:0] l_mask_6; // @[lsu.scala:1665:22] wire _l_mask_mask_T_90 = ldq_6_bits_uop_mem_size == 2'h0; // @[lsu.scala:208:16, :1667:26] wire [2:0] _l_mask_mask_T_91 = ldq_6_bits_addr_bits[2:0]; // @[lsu.scala:208:16, :1667:55] wire [14:0] _l_mask_mask_T_92 = 15'h1 << _l_mask_mask_T_91; // @[lsu.scala:1667:{48,55}] wire _l_mask_mask_T_93 = ldq_6_bits_uop_mem_size == 2'h1; // @[lsu.scala:208:16, :1668:26] wire [1:0] _l_mask_mask_T_94 = ldq_6_bits_addr_bits[2:1]; // @[lsu.scala:208:16, :1668:56] wire [2:0] _l_mask_mask_T_95 = {_l_mask_mask_T_94, 1'h0}; // @[lsu.scala:1668:{56,62}] wire [14:0] _l_mask_mask_T_96 = 15'h3 << _l_mask_mask_T_95; // @[lsu.scala:1668:{48,62}] wire _l_mask_mask_T_97 = ldq_6_bits_uop_mem_size == 2'h2; // @[lsu.scala:208:16, :1669:26] wire _l_mask_mask_T_98 = ldq_6_bits_addr_bits[2]; // @[lsu.scala:208:16, :1669:46] wire [7:0] _l_mask_mask_T_99 = _l_mask_mask_T_98 ? 8'hF0 : 8'hF; // @[lsu.scala:1669:{41,46}] wire _l_mask_mask_T_100 = &ldq_6_bits_uop_mem_size; // @[lsu.scala:208:16, :1670:26] wire [7:0] _l_mask_mask_T_102 = _l_mask_mask_T_97 ? _l_mask_mask_T_99 : 8'hFF; // @[Mux.scala:126:16] wire [14:0] _l_mask_mask_T_103 = _l_mask_mask_T_93 ? _l_mask_mask_T_96 : {7'h0, _l_mask_mask_T_102}; // @[Mux.scala:126:16] wire [14:0] _l_mask_mask_T_104 = _l_mask_mask_T_90 ? _l_mask_mask_T_92 : _l_mask_mask_T_103; // @[Mux.scala:126:16] assign l_mask_6 = _l_mask_mask_T_104[7:0]; // @[Mux.scala:126:16] wire _l_forwarders_T_12 = wb_forward_ldq_idx_0 == 3'h6; // @[lsu.scala:1066:36, :1076:88] wire _l_forwarders_T_13 = wb_forward_valid_0 & _l_forwarders_T_12; // @[lsu.scala:1065:36, :1076:{63,88}] wire l_forwarders_6_0 = _l_forwarders_T_13; // @[lsu.scala:263:49, :1076:63] wire [2:0] l_forward_stq_idx_6 = l_forwarders_6_0 ? wb_forward_stq_idx_0 : ldq_6_bits_forward_stq_idx; // @[lsu.scala:208:16, :263:49, :1068:36, :1078:32] wire [33:0] _block_addr_matches_T_19 = ldq_6_bits_addr_bits[39:6]; // @[lsu.scala:208:16, :1081:84] wire _block_addr_matches_T_20 = _block_addr_matches_T_18 == _block_addr_matches_T_19; // @[lsu.scala:1081:{57,73,84}] wire block_addr_matches_6_0 = _block_addr_matches_T_20; // @[lsu.scala:263:49, :1081:73] wire [2:0] _dword_addr_matches_T_25 = ldq_6_bits_addr_bits[5:3]; // @[lsu.scala:208:16, :1082:110] wire _dword_addr_matches_T_26 = _dword_addr_matches_T_24 == _dword_addr_matches_T_25; // @[lsu.scala:1082:{81,100,110}] wire _dword_addr_matches_T_27 = block_addr_matches_6_0 & _dword_addr_matches_T_26; // @[lsu.scala:263:49, :1082:{66,100}] wire dword_addr_matches_6_0 = _dword_addr_matches_T_27; // @[lsu.scala:263:49, :1082:66] wire [7:0] _GEN_266 = l_mask_6 & lcam_mask_0; // @[lsu.scala:263:49, :1083:46, :1665:22] wire [7:0] _mask_match_T_12; // @[lsu.scala:1083:46] assign _mask_match_T_12 = _GEN_266; // @[lsu.scala:1083:46] wire [7:0] _mask_overlap_T_12; // @[lsu.scala:1084:46] assign _mask_overlap_T_12 = _GEN_266; // @[lsu.scala:1083:46, :1084:46] wire _mask_match_T_13 = _mask_match_T_12 == l_mask_6; // @[lsu.scala:1083:{46,62}, :1665:22] wire mask_match_6_0 = _mask_match_T_13; // @[lsu.scala:263:49, :1083:62] wire _mask_overlap_T_13 = |_mask_overlap_T_12; // @[lsu.scala:1084:{46,62}] wire mask_overlap_6_0 = _mask_overlap_T_13; // @[lsu.scala:263:49, :1084:62] wire _T_401 = do_release_search_0 & ldq_6_valid & ldq_6_bits_addr_valid & block_addr_matches_6_0; // @[lsu.scala:208:16, :263:49, :1089:34, :1090:34, :1091:34] wire _T_430 = ldq_6_bits_executed | ldq_6_bits_succeeded; // @[lsu.scala:208:16, :1099:37] wire [7:0] _T_409 = ldq_6_bits_st_dep_mask >> _GEN_230; // @[lsu.scala:208:16, :1101:38] wire _T_413 = do_st_search_0 & ldq_6_valid & ldq_6_bits_addr_valid & (_T_430 | l_forwarders_6_0) & ~ldq_6_bits_addr_is_virtual & _T_409[0] & dword_addr_matches_6_0 & mask_overlap_6_0; // @[lsu.scala:208:16, :263:49, :432:52, :1096:131, :1097:131, :1098:131, :1099:{37,57,131}, :1100:131, :1101:{38,131}, :1102:131] wire _forwarded_is_older_T_24 = l_forward_stq_idx_6 < lcam_stq_idx_0; // @[util.scala:363:52] wire _forwarded_is_older_T_25 = l_forward_stq_idx_6 < ldq_6_bits_youngest_stq_idx; // @[util.scala:363:64] wire _forwarded_is_older_T_26 = _forwarded_is_older_T_24 ^ _forwarded_is_older_T_25; // @[util.scala:363:{52,58,64}] wire _forwarded_is_older_T_27 = lcam_stq_idx_0 < ldq_6_bits_youngest_stq_idx; // @[util.scala:363:78] wire forwarded_is_older_6 = _forwarded_is_older_T_26 ^ _forwarded_is_older_T_27; // @[util.scala:363:{58,72,78}] wire _T_417 = ~ldq_6_bits_forward_std_val | l_forward_stq_idx_6 != lcam_stq_idx_0 & forwarded_is_older_6; // @[util.scala:363:72] wire _T_423 = do_ld_search_0 & ldq_6_valid & ldq_6_bits_addr_valid & ~ldq_6_bits_addr_is_virtual & dword_addr_matches_6_0 & mask_overlap_6_0; // @[lsu.scala:208:16, :263:49, :432:52, :1112:47, :1113:47, :1114:47, :1115:47, :1116:47] wire _searcher_is_older_T_24 = lcam_ldq_idx_0[2:1] != 2'h3; // @[util.scala:363:52] wire _searcher_is_older_T_26 = _searcher_is_older_T_24 ^ _searcher_is_older_T_25; // @[util.scala:363:{52,58,64}] wire _searcher_is_older_T_27 = &ldq_head; // @[util.scala:363:78] wire searcher_is_older_6 = _searcher_is_older_T_26 ^ _searcher_is_older_T_27; // @[util.scala:363:{58,72,78}] wire _GEN_267 = _T_423 & searcher_is_older_6 & (_T_430 | l_forwarders_6_0) & ~s1_executing_loads_6 & ldq_6_bits_observed; // @[util.scala:363:72] assign failed_loads_6 = ~_T_401 & (_T_413 ? _T_417 : _GEN_267); // @[lsu.scala:303:5, :1054:34, :1089:34, :1090:34, :1091:34, :1092:36, :1096:131, :1097:131, :1098:131, :1099:131, :1100:131, :1101:131, :1102:131, :1103:37, :1107:39, :1108:76, :1117:37, :1119:34, :1120:74, :1121:40, :1122:34, :1123:36] reg older_nacked_REG_6; // @[lsu.scala:1129:57] wire older_nacked_6 = nacking_loads_6 | older_nacked_REG_6; // @[lsu.scala:1055:34, :1129:{47,57}] wire _T_432 = ~_T_430 | older_nacked_6; // @[lsu.scala:1099:37, :1129:47, :1130:{17,56}] wire _GEN_268 = searcher_is_older_6 | _GEN_239; // @[util.scala:363:72] wire _GEN_269 = _T_401 | _T_413; // @[lsu.scala:1089:34, :1090:34, :1091:34, :1092:36, :1096:131, :1097:131, :1098:131, :1099:131, :1100:131, :1101:131, :1102:131, :1103:37, :1117:37] wire _GEN_270 = (_GEN_269 | ~_T_423 | _GEN_268 | ~(_T_432 & (&lcam_ldq_idx_0))) & (_GEN_264 | ~_T_387 | _GEN_263 | ~(_T_396 & (&lcam_ldq_idx_0))) & (_GEN_259 | ~_T_351 | _GEN_258 | ~(_T_360 & (&lcam_ldq_idx_0))) & (_GEN_254 | ~_T_315 | _GEN_253 | ~(_T_324 & (&lcam_ldq_idx_0))) & (_GEN_249 | ~_T_279 | _GEN_248 | ~(_T_288 & (&lcam_ldq_idx_0))) & (_GEN_244 | ~_T_243 | _GEN_243 | ~(_T_252 & (&lcam_ldq_idx_0))) & (_GEN_233 | ~_T_207 | searcher_is_older | ~((|lcam_ldq_idx_0) & _T_216 & (&lcam_ldq_idx_0))) & s1_executing_loads_7; // @[util.scala:363:72] reg io_dmem_s1_kill_0_REG_6; // @[lsu.scala:1132:58] wire _GEN_271 = _GEN_269 | ~_T_423 | _GEN_268 | ~_T_432; // @[lsu.scala:1092:36, :1103:37, :1112:47, :1113:47, :1114:47, :1115:47, :1116:47, :1117:37, :1119:34, :1126:{38,47}, :1130:{56,73}] wire [7:0] l_mask_7; // @[lsu.scala:1665:22] wire _l_mask_mask_T_105 = ldq_7_bits_uop_mem_size == 2'h0; // @[lsu.scala:208:16, :1667:26] wire [2:0] _l_mask_mask_T_106 = ldq_7_bits_addr_bits[2:0]; // @[lsu.scala:208:16, :1667:55] wire [14:0] _l_mask_mask_T_107 = 15'h1 << _l_mask_mask_T_106; // @[lsu.scala:1667:{48,55}] wire _l_mask_mask_T_108 = ldq_7_bits_uop_mem_size == 2'h1; // @[lsu.scala:208:16, :1668:26] wire [1:0] _l_mask_mask_T_109 = ldq_7_bits_addr_bits[2:1]; // @[lsu.scala:208:16, :1668:56] wire [2:0] _l_mask_mask_T_110 = {_l_mask_mask_T_109, 1'h0}; // @[lsu.scala:1668:{56,62}] wire [14:0] _l_mask_mask_T_111 = 15'h3 << _l_mask_mask_T_110; // @[lsu.scala:1668:{48,62}] wire _l_mask_mask_T_112 = ldq_7_bits_uop_mem_size == 2'h2; // @[lsu.scala:208:16, :1669:26] wire _l_mask_mask_T_113 = ldq_7_bits_addr_bits[2]; // @[lsu.scala:208:16, :1669:46] wire [7:0] _l_mask_mask_T_114 = _l_mask_mask_T_113 ? 8'hF0 : 8'hF; // @[lsu.scala:1669:{41,46}] wire _l_mask_mask_T_115 = &ldq_7_bits_uop_mem_size; // @[lsu.scala:208:16, :1670:26] wire [7:0] _l_mask_mask_T_117 = _l_mask_mask_T_112 ? _l_mask_mask_T_114 : 8'hFF; // @[Mux.scala:126:16] wire [14:0] _l_mask_mask_T_118 = _l_mask_mask_T_108 ? _l_mask_mask_T_111 : {7'h0, _l_mask_mask_T_117}; // @[Mux.scala:126:16] wire [14:0] _l_mask_mask_T_119 = _l_mask_mask_T_105 ? _l_mask_mask_T_107 : _l_mask_mask_T_118; // @[Mux.scala:126:16] assign l_mask_7 = _l_mask_mask_T_119[7:0]; // @[Mux.scala:126:16] wire _l_forwarders_T_14 = &wb_forward_ldq_idx_0; // @[lsu.scala:1066:36, :1076:88] wire _l_forwarders_T_15 = wb_forward_valid_0 & _l_forwarders_T_14; // @[lsu.scala:1065:36, :1076:{63,88}] wire l_forwarders_7_0 = _l_forwarders_T_15; // @[lsu.scala:263:49, :1076:63] wire [2:0] l_forward_stq_idx_7 = l_forwarders_7_0 ? wb_forward_stq_idx_0 : ldq_7_bits_forward_stq_idx; // @[lsu.scala:208:16, :263:49, :1068:36, :1078:32] wire [33:0] _block_addr_matches_T_22 = ldq_7_bits_addr_bits[39:6]; // @[lsu.scala:208:16, :1081:84] wire _block_addr_matches_T_23 = _block_addr_matches_T_21 == _block_addr_matches_T_22; // @[lsu.scala:1081:{57,73,84}] wire block_addr_matches_7_0 = _block_addr_matches_T_23; // @[lsu.scala:263:49, :1081:73] wire [2:0] _dword_addr_matches_T_29 = ldq_7_bits_addr_bits[5:3]; // @[lsu.scala:208:16, :1082:110] wire _dword_addr_matches_T_30 = _dword_addr_matches_T_28 == _dword_addr_matches_T_29; // @[lsu.scala:1082:{81,100,110}] wire _dword_addr_matches_T_31 = block_addr_matches_7_0 & _dword_addr_matches_T_30; // @[lsu.scala:263:49, :1082:{66,100}] wire dword_addr_matches_7_0 = _dword_addr_matches_T_31; // @[lsu.scala:263:49, :1082:66] wire [7:0] _GEN_272 = l_mask_7 & lcam_mask_0; // @[lsu.scala:263:49, :1083:46, :1665:22] wire [7:0] _mask_match_T_14; // @[lsu.scala:1083:46] assign _mask_match_T_14 = _GEN_272; // @[lsu.scala:1083:46] wire [7:0] _mask_overlap_T_14; // @[lsu.scala:1084:46] assign _mask_overlap_T_14 = _GEN_272; // @[lsu.scala:1083:46, :1084:46] wire _mask_match_T_15 = _mask_match_T_14 == l_mask_7; // @[lsu.scala:1083:{46,62}, :1665:22] wire mask_match_7_0 = _mask_match_T_15; // @[lsu.scala:263:49, :1083:62] wire _mask_overlap_T_15 = |_mask_overlap_T_14; // @[lsu.scala:1084:{46,62}] wire mask_overlap_7_0 = _mask_overlap_T_15; // @[lsu.scala:263:49, :1084:62] wire _T_437 = do_release_search_0 & ldq_7_valid & ldq_7_bits_addr_valid & block_addr_matches_7_0; // @[lsu.scala:208:16, :263:49, :1089:34, :1090:34, :1091:34] wire _T_466 = ldq_7_bits_executed | ldq_7_bits_succeeded; // @[lsu.scala:208:16, :1099:37] wire [7:0] _T_445 = ldq_7_bits_st_dep_mask >> _GEN_230; // @[lsu.scala:208:16, :1101:38] wire _T_449 = do_st_search_0 & ldq_7_valid & ldq_7_bits_addr_valid & (_T_466 | l_forwarders_7_0) & ~ldq_7_bits_addr_is_virtual & _T_445[0] & dword_addr_matches_7_0 & mask_overlap_7_0; // @[lsu.scala:208:16, :263:49, :432:52, :1096:131, :1097:131, :1098:131, :1099:{37,57,131}, :1100:131, :1101:{38,131}, :1102:131] wire _forwarded_is_older_T_28 = l_forward_stq_idx_7 < lcam_stq_idx_0; // @[util.scala:363:52] wire _forwarded_is_older_T_29 = l_forward_stq_idx_7 < ldq_7_bits_youngest_stq_idx; // @[util.scala:363:64] wire _forwarded_is_older_T_30 = _forwarded_is_older_T_28 ^ _forwarded_is_older_T_29; // @[util.scala:363:{52,58,64}] wire _forwarded_is_older_T_31 = lcam_stq_idx_0 < ldq_7_bits_youngest_stq_idx; // @[util.scala:363:78] wire forwarded_is_older_7 = _forwarded_is_older_T_30 ^ _forwarded_is_older_T_31; // @[util.scala:363:{58,72,78}] wire _T_453 = ~ldq_7_bits_forward_std_val | l_forward_stq_idx_7 != lcam_stq_idx_0 & forwarded_is_older_7; // @[util.scala:363:72] wire _T_459 = do_ld_search_0 & ldq_7_valid & ldq_7_bits_addr_valid & ~ldq_7_bits_addr_is_virtual & dword_addr_matches_7_0 & mask_overlap_7_0; // @[lsu.scala:208:16, :263:49, :432:52, :1112:47, :1113:47, :1114:47, :1115:47, :1116:47] wire _searcher_is_older_T_28 = lcam_ldq_idx_0 != 3'h7; // @[util.scala:363:52] wire _searcher_is_older_T_30 = _searcher_is_older_T_28 ^ _searcher_is_older_T_29; // @[util.scala:363:{52,58,64}] wire searcher_is_older_7 = _searcher_is_older_T_30; // @[util.scala:363:{58,72}] wire _GEN_273 = _T_459 & searcher_is_older_7 & (_T_466 | l_forwarders_7_0) & ~s1_executing_loads_7 & ldq_7_bits_observed; // @[util.scala:363:72] assign failed_loads_7 = ~_T_437 & (_T_449 ? _T_453 : _GEN_273); // @[lsu.scala:303:5, :1054:34, :1089:34, :1090:34, :1091:34, :1092:36, :1096:131, :1097:131, :1098:131, :1099:131, :1100:131, :1101:131, :1102:131, :1103:37, :1107:39, :1108:76, :1117:37, :1119:34, :1120:74, :1121:40, :1122:34, :1123:36] reg older_nacked_REG_7; // @[lsu.scala:1129:57] wire older_nacked_7 = nacking_loads_7 | older_nacked_REG_7; // @[lsu.scala:1055:34, :1129:{47,57}] wire _T_468 = ~_T_466 | older_nacked_7; // @[lsu.scala:1099:37, :1129:47, :1130:{17,56}] wire _GEN_274 = _T_437 | _T_449; // @[lsu.scala:1089:34, :1090:34, :1091:34, :1092:36, :1096:131, :1097:131, :1098:131, :1099:131, :1100:131, :1101:131, :1102:131, :1103:37, :1117:37] wire _GEN_275 = (_GEN_274 | ~_T_459 | searcher_is_older_7 | ~(~(&lcam_ldq_idx_0) & _T_468 & _searcher_is_older_T_4)) & (_GEN_269 | ~_T_423 | _GEN_268 | ~(_T_432 & _searcher_is_older_T_4)) & (_GEN_264 | ~_T_387 | _GEN_263 | ~(_T_396 & _searcher_is_older_T_4)) & (_GEN_259 | ~_T_351 | _GEN_258 | ~(_T_360 & _searcher_is_older_T_4)) & (_GEN_254 | ~_T_315 | _GEN_253 | ~(_T_324 & _searcher_is_older_T_4)) & (_GEN_249 | ~_T_279 | _GEN_248 | ~(_T_288 & _searcher_is_older_T_4)) & (_GEN_244 | ~_T_243 | _GEN_243 | ~(_T_252 & _searcher_is_older_T_4)) & s1_executing_loads_0; // @[util.scala:363:{52,72}] wire _GEN_276 = (_GEN_274 | ~_T_459 | searcher_is_older_7 | ~(~(&lcam_ldq_idx_0) & _T_468 & _GEN_234)) & (_GEN_269 | ~_T_423 | _GEN_268 | ~(_T_432 & _GEN_234)) & (_GEN_264 | ~_T_387 | _GEN_263 | ~(_T_396 & _GEN_234)) & (_GEN_259 | ~_T_351 | _GEN_258 | ~(_T_360 & _GEN_234)) & (_GEN_254 | ~_T_315 | _GEN_253 | ~(_T_324 & _GEN_234)) & (_GEN_249 | ~_T_279 | _GEN_248 | ~(_T_288 & _GEN_234)) & (_GEN_244 | ~_T_243 | _GEN_243 | ~(_T_252 & _GEN_234)) & (_GEN_233 | ~_T_207 | searcher_is_older | ~((|lcam_ldq_idx_0) & _T_216 & _GEN_234)) & s1_executing_loads_1; // @[util.scala:363:72] wire _GEN_277 = (_GEN_274 | ~_T_459 | searcher_is_older_7 | ~(~(&lcam_ldq_idx_0) & _T_468 & _GEN_235)) & (_GEN_269 | ~_T_423 | _GEN_268 | ~(_T_432 & _GEN_235)) & (_GEN_264 | ~_T_387 | _GEN_263 | ~(_T_396 & _GEN_235)) & (_GEN_259 | ~_T_351 | _GEN_258 | ~(_T_360 & _GEN_235)) & (_GEN_254 | ~_T_315 | _GEN_253 | ~(_T_324 & _GEN_235)) & (_GEN_249 | ~_T_279 | _GEN_248 | ~(_T_288 & _GEN_235)) & (_GEN_244 | ~_T_243 | _GEN_243 | ~(_T_252 & _GEN_235)) & (_GEN_233 | ~_T_207 | searcher_is_older | ~((|lcam_ldq_idx_0) & _T_216 & _GEN_235)) & s1_executing_loads_2; // @[util.scala:363:72] wire _GEN_278 = (_GEN_274 | ~_T_459 | searcher_is_older_7 | ~(~(&lcam_ldq_idx_0) & _T_468 & _GEN_236)) & (_GEN_269 | ~_T_423 | _GEN_268 | ~(_T_432 & _GEN_236)) & (_GEN_264 | ~_T_387 | _GEN_263 | ~(_T_396 & _GEN_236)) & (_GEN_259 | ~_T_351 | _GEN_258 | ~(_T_360 & _GEN_236)) & (_GEN_254 | ~_T_315 | _GEN_253 | ~(_T_324 & _GEN_236)) & (_GEN_249 | ~_T_279 | _GEN_248 | ~(_T_288 & _GEN_236)) & (_GEN_244 | ~_T_243 | _GEN_243 | ~(_T_252 & _GEN_236)) & (_GEN_233 | ~_T_207 | searcher_is_older | ~((|lcam_ldq_idx_0) & _T_216 & _GEN_236)) & s1_executing_loads_3; // @[util.scala:363:72] wire _GEN_279 = (_GEN_274 | ~_T_459 | searcher_is_older_7 | ~(~(&lcam_ldq_idx_0) & _T_468 & _GEN_237)) & (_GEN_269 | ~_T_423 | _GEN_268 | ~(_T_432 & _GEN_237)) & (_GEN_264 | ~_T_387 | _GEN_263 | ~(_T_396 & _GEN_237)) & (_GEN_259 | ~_T_351 | _GEN_258 | ~(_T_360 & _GEN_237)) & (_GEN_254 | ~_T_315 | _GEN_253 | ~(_T_324 & _GEN_237)) & (_GEN_249 | ~_T_279 | _GEN_248 | ~(_T_288 & _GEN_237)) & (_GEN_244 | ~_T_243 | _GEN_243 | ~(_T_252 & _GEN_237)) & (_GEN_233 | ~_T_207 | searcher_is_older | ~((|lcam_ldq_idx_0) & _T_216 & _GEN_237)) & s1_executing_loads_4; // @[util.scala:363:72] wire _GEN_280 = (_GEN_274 | ~_T_459 | searcher_is_older_7 | ~(~(&lcam_ldq_idx_0) & _T_468 & _GEN_238)) & (_GEN_269 | ~_T_423 | _GEN_268 | ~(_T_432 & _GEN_238)) & (_GEN_264 | ~_T_387 | _GEN_263 | ~(_T_396 & _GEN_238)) & (_GEN_259 | ~_T_351 | _GEN_258 | ~(_T_360 & _GEN_238)) & (_GEN_254 | ~_T_315 | _GEN_253 | ~(_T_324 & _GEN_238)) & (_GEN_249 | ~_T_279 | _GEN_248 | ~(_T_288 & _GEN_238)) & (_GEN_244 | ~_T_243 | _GEN_243 | ~(_T_252 & _GEN_238)) & (_GEN_233 | ~_T_207 | searcher_is_older | ~((|lcam_ldq_idx_0) & _T_216 & _GEN_238)) & s1_executing_loads_5; // @[util.scala:363:72] wire _GEN_281 = (_GEN_274 | ~_T_459 | searcher_is_older_7 | ~(~(&lcam_ldq_idx_0) & _T_468 & _GEN_239)) & (_GEN_269 | ~_T_423 | _GEN_268 | ~(_T_432 & _GEN_239)) & (_GEN_264 | ~_T_387 | _GEN_263 | ~(_T_396 & _GEN_239)) & (_GEN_259 | ~_T_351 | _GEN_258 | ~(_T_360 & _GEN_239)) & (_GEN_254 | ~_T_315 | _GEN_253 | ~(_T_324 & _GEN_239)) & (_GEN_249 | ~_T_279 | _GEN_248 | ~(_T_288 & _GEN_239)) & (_GEN_244 | ~_T_243 | _GEN_243 | ~(_T_252 & _GEN_239)) & (_GEN_233 | ~_T_207 | searcher_is_older | ~((|lcam_ldq_idx_0) & _T_216 & _GEN_239)) & s1_executing_loads_6; // @[util.scala:363:72] reg io_dmem_s1_kill_0_REG_7; // @[lsu.scala:1132:58] wire _GEN_282 = _GEN_274 | ~_T_459 | searcher_is_older_7 | ~(~(&lcam_ldq_idx_0) & _T_468); // @[util.scala:363:72] wire _GEN_283 = _GEN_282 ? (_GEN_271 ? (_GEN_265 ? (_GEN_260 ? (_GEN_255 ? (_GEN_250 ? (_GEN_245 ? ~_GEN_233 & _T_207 & ~searcher_is_older & _GEN_240 & io_dmem_s1_kill_0_REG : io_dmem_s1_kill_0_REG_1) : io_dmem_s1_kill_0_REG_2) : io_dmem_s1_kill_0_REG_3) : io_dmem_s1_kill_0_REG_4) : io_dmem_s1_kill_0_REG_5) : io_dmem_s1_kill_0_REG_6) : io_dmem_s1_kill_0_REG_7; // @[util.scala:363:72] assign can_forward_0 = _GEN_282 & _GEN_271 & _GEN_265 & _GEN_260 & _GEN_255 & _GEN_250 & _GEN_245 & (_GEN_233 | ~_T_207 | searcher_is_older | ~_GEN_240) & _can_forward_WIRE_0; // @[util.scala:363:72] wire _dword_addr_matches_T_32 = ~stq_0_bits_addr_is_virtual; // @[lsu.scala:209:16, :1145:31] wire _dword_addr_matches_T_33 = stq_0_bits_addr_valid & _dword_addr_matches_T_32; // @[lsu.scala:209:16, :1144:60, :1145:31] wire [28:0] _dword_addr_matches_T_34 = stq_0_bits_addr_bits[31:3]; // @[lsu.scala:209:16, :1146:38] wire [28:0] _dword_addr_matches_T_35 = lcam_addr_0[31:3]; // @[lsu.scala:263:49, :1146:74] wire [28:0] _dword_addr_matches_T_41 = lcam_addr_0[31:3]; // @[lsu.scala:263:49, :1146:74] wire [28:0] _dword_addr_matches_T_47 = lcam_addr_0[31:3]; // @[lsu.scala:263:49, :1146:74] wire [28:0] _dword_addr_matches_T_53 = lcam_addr_0[31:3]; // @[lsu.scala:263:49, :1146:74] wire [28:0] _dword_addr_matches_T_59 = lcam_addr_0[31:3]; // @[lsu.scala:263:49, :1146:74] wire [28:0] _dword_addr_matches_T_65 = lcam_addr_0[31:3]; // @[lsu.scala:263:49, :1146:74] wire [28:0] _dword_addr_matches_T_71 = lcam_addr_0[31:3]; // @[lsu.scala:263:49, :1146:74] wire [28:0] _dword_addr_matches_T_77 = lcam_addr_0[31:3]; // @[lsu.scala:263:49, :1146:74] wire _dword_addr_matches_T_36 = _dword_addr_matches_T_34 == _dword_addr_matches_T_35; // @[lsu.scala:1146:{38,58,74}] wire _dword_addr_matches_T_37 = _dword_addr_matches_T_33 & _dword_addr_matches_T_36; // @[lsu.scala:1144:60, :1145:60, :1146:58] wire dword_addr_matches_8_0 = _dword_addr_matches_T_37; // @[lsu.scala:263:49, :1145:60] wire [7:0] write_mask; // @[lsu.scala:1665:22] wire _write_mask_mask_T = stq_0_bits_uop_mem_size == 2'h0; // @[lsu.scala:209:16, :1667:26] wire [2:0] _write_mask_mask_T_1 = stq_0_bits_addr_bits[2:0]; // @[lsu.scala:209:16, :1667:55] wire [14:0] _write_mask_mask_T_2 = 15'h1 << _write_mask_mask_T_1; // @[lsu.scala:1667:{48,55}] wire _write_mask_mask_T_3 = stq_0_bits_uop_mem_size == 2'h1; // @[lsu.scala:209:16, :1668:26] wire [1:0] _write_mask_mask_T_4 = stq_0_bits_addr_bits[2:1]; // @[lsu.scala:209:16, :1668:56] wire [2:0] _write_mask_mask_T_5 = {_write_mask_mask_T_4, 1'h0}; // @[lsu.scala:1668:{56,62}] wire [14:0] _write_mask_mask_T_6 = 15'h3 << _write_mask_mask_T_5; // @[lsu.scala:1668:{48,62}] wire _write_mask_mask_T_7 = stq_0_bits_uop_mem_size == 2'h2; // @[lsu.scala:209:16, :1669:26] wire _write_mask_mask_T_8 = stq_0_bits_addr_bits[2]; // @[lsu.scala:209:16, :1669:46] wire [7:0] _write_mask_mask_T_9 = _write_mask_mask_T_8 ? 8'hF0 : 8'hF; // @[lsu.scala:1669:{41,46}] wire _write_mask_mask_T_10 = &stq_0_bits_uop_mem_size; // @[lsu.scala:209:16, :1670:26] wire [7:0] _write_mask_mask_T_12 = _write_mask_mask_T_7 ? _write_mask_mask_T_9 : 8'hFF; // @[Mux.scala:126:16] wire [14:0] _write_mask_mask_T_13 = _write_mask_mask_T_3 ? _write_mask_mask_T_6 : {7'h0, _write_mask_mask_T_12}; // @[Mux.scala:126:16] wire [14:0] _write_mask_mask_T_14 = _write_mask_mask_T ? _write_mask_mask_T_2 : _write_mask_mask_T_13; // @[Mux.scala:126:16] assign write_mask = _write_mask_mask_T_14[7:0]; // @[Mux.scala:126:16] wire _T_473 = do_ld_search_0 & stq_0_valid & lcam_st_dep_mask_0[0]; // @[lsu.scala:209:16, :263:49, :1149:{29,45,67}] wire [7:0] _T_484 = lcam_mask_0 & write_mask; // @[lsu.scala:263:49, :1150:30, :1665:22] wire _T_481 = _T_484 == lcam_mask_0 & ~stq_0_bits_uop_is_fence & ~stq_0_bits_uop_is_amo & dword_addr_matches_8_0 & can_forward_0; // @[lsu.scala:209:16, :263:49, :1045:29, :1150:{30,44,62,65,81,84,98,123}] assign ldst_forward_matches_0_0 = _T_473 & _T_481; // @[lsu.scala:1052:38, :1149:{29,45,72}, :1150:{62,81,98,123}, :1151:9, :1153:46] reg io_dmem_s1_kill_0_REG_8; // @[lsu.scala:1154:56] wire _T_486 = (|_T_484) & dword_addr_matches_8_0; // @[lsu.scala:263:49, :1150:30, :1157:{51,60}] reg io_dmem_s1_kill_0_REG_9; // @[lsu.scala:1160:56] wire _T_489 = stq_0_bits_uop_is_fence | stq_0_bits_uop_is_amo; // @[lsu.scala:209:16, :1163:37] assign ldst_addr_matches_0_0 = _T_473 & (_T_481 | _T_486 | _T_489); // @[lsu.scala:1050:38, :1149:{29,45,72}, :1150:{62,81,98,123}, :1151:9, :1152:46, :1157:60, :1158:9, :1159:46, :1163:37, :1164:9, :1165:46] reg io_dmem_s1_kill_0_REG_10; // @[lsu.scala:1166:56] wire _GEN_284 = _T_473 ? (_T_481 ? io_dmem_s1_kill_0_REG_8 : _T_486 ? io_dmem_s1_kill_0_REG_9 : _T_489 ? io_dmem_s1_kill_0_REG_10 : _GEN_283) : _GEN_283; // @[lsu.scala:1092:36, :1103:37, :1117:37, :1149:{29,45,72}, :1150:{62,81,98,123}, :1151:9, :1154:{46,56}, :1157:60, :1158:9, :1160:{46,56}, :1163:37, :1164:9, :1166:{46,56}] wire _GEN_285 = _T_481 | _T_486; // @[lsu.scala:1150:{62,81,98,123}, :1151:9, :1155:46, :1157:60, :1158:9] wire _GEN_286 = _T_473 ? (_GEN_285 ? ~_searcher_is_older_T_4 & _GEN_275 : ~(_T_489 & _searcher_is_older_T_4) & _GEN_275) : _GEN_275; // @[util.scala:363:52] wire _GEN_287 = _T_473 ? (_GEN_285 ? ~_GEN_234 & _GEN_276 : ~(_T_489 & _GEN_234) & _GEN_276) : _GEN_276; // @[lsu.scala:1058:36, :1092:36, :1103:37, :1117:37, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_288 = _T_473 ? (_GEN_285 ? ~_GEN_235 & _GEN_277 : ~(_T_489 & _GEN_235) & _GEN_277) : _GEN_277; // @[lsu.scala:1058:36, :1092:36, :1103:37, :1117:37, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_289 = _T_473 ? (_GEN_285 ? ~_GEN_236 & _GEN_278 : ~(_T_489 & _GEN_236) & _GEN_278) : _GEN_278; // @[lsu.scala:1058:36, :1092:36, :1103:37, :1117:37, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_290 = _T_473 ? (_GEN_285 ? ~_GEN_237 & _GEN_279 : ~(_T_489 & _GEN_237) & _GEN_279) : _GEN_279; // @[lsu.scala:1058:36, :1092:36, :1103:37, :1117:37, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_291 = _T_473 ? (_GEN_285 ? ~_GEN_238 & _GEN_280 : ~(_T_489 & _GEN_238) & _GEN_280) : _GEN_280; // @[lsu.scala:1058:36, :1092:36, :1103:37, :1117:37, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_292 = _T_473 ? (_GEN_285 ? ~_GEN_239 & _GEN_281 : ~(_T_489 & _GEN_239) & _GEN_281) : _GEN_281; // @[lsu.scala:1058:36, :1092:36, :1103:37, :1117:37, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_293 = _T_473 ? (_GEN_285 ? ~(&lcam_ldq_idx_0) & _GEN_270 : ~(_T_489 & (&lcam_ldq_idx_0)) & _GEN_270) : _GEN_270; // @[lsu.scala:263:49, :1058:36, :1092:36, :1103:37, :1117:37, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _dword_addr_matches_T_38 = ~stq_1_bits_addr_is_virtual; // @[lsu.scala:209:16, :1145:31] wire _dword_addr_matches_T_39 = stq_1_bits_addr_valid & _dword_addr_matches_T_38; // @[lsu.scala:209:16, :1144:60, :1145:31] wire [28:0] _dword_addr_matches_T_40 = stq_1_bits_addr_bits[31:3]; // @[lsu.scala:209:16, :1146:38] wire _dword_addr_matches_T_42 = _dword_addr_matches_T_40 == _dword_addr_matches_T_41; // @[lsu.scala:1146:{38,58,74}] wire _dword_addr_matches_T_43 = _dword_addr_matches_T_39 & _dword_addr_matches_T_42; // @[lsu.scala:1144:60, :1145:60, :1146:58] wire dword_addr_matches_9_0 = _dword_addr_matches_T_43; // @[lsu.scala:263:49, :1145:60] wire [7:0] write_mask_1; // @[lsu.scala:1665:22] wire _write_mask_mask_T_15 = stq_1_bits_uop_mem_size == 2'h0; // @[lsu.scala:209:16, :1667:26] wire [2:0] _write_mask_mask_T_16 = stq_1_bits_addr_bits[2:0]; // @[lsu.scala:209:16, :1667:55] wire [14:0] _write_mask_mask_T_17 = 15'h1 << _write_mask_mask_T_16; // @[lsu.scala:1667:{48,55}] wire _write_mask_mask_T_18 = stq_1_bits_uop_mem_size == 2'h1; // @[lsu.scala:209:16, :1668:26] wire [1:0] _write_mask_mask_T_19 = stq_1_bits_addr_bits[2:1]; // @[lsu.scala:209:16, :1668:56] wire [2:0] _write_mask_mask_T_20 = {_write_mask_mask_T_19, 1'h0}; // @[lsu.scala:1668:{56,62}] wire [14:0] _write_mask_mask_T_21 = 15'h3 << _write_mask_mask_T_20; // @[lsu.scala:1668:{48,62}] wire _write_mask_mask_T_22 = stq_1_bits_uop_mem_size == 2'h2; // @[lsu.scala:209:16, :1669:26] wire _write_mask_mask_T_23 = stq_1_bits_addr_bits[2]; // @[lsu.scala:209:16, :1669:46] wire [7:0] _write_mask_mask_T_24 = _write_mask_mask_T_23 ? 8'hF0 : 8'hF; // @[lsu.scala:1669:{41,46}] wire _write_mask_mask_T_25 = &stq_1_bits_uop_mem_size; // @[lsu.scala:209:16, :1670:26] wire [7:0] _write_mask_mask_T_27 = _write_mask_mask_T_22 ? _write_mask_mask_T_24 : 8'hFF; // @[Mux.scala:126:16] wire [14:0] _write_mask_mask_T_28 = _write_mask_mask_T_18 ? _write_mask_mask_T_21 : {7'h0, _write_mask_mask_T_27}; // @[Mux.scala:126:16] wire [14:0] _write_mask_mask_T_29 = _write_mask_mask_T_15 ? _write_mask_mask_T_17 : _write_mask_mask_T_28; // @[Mux.scala:126:16] assign write_mask_1 = _write_mask_mask_T_29[7:0]; // @[Mux.scala:126:16] wire _T_494 = do_ld_search_0 & stq_1_valid & lcam_st_dep_mask_0[1]; // @[lsu.scala:209:16, :263:49, :1149:{29,45,67}] wire [7:0] _T_505 = lcam_mask_0 & write_mask_1; // @[lsu.scala:263:49, :1150:30, :1665:22] wire _T_502 = _T_505 == lcam_mask_0 & ~stq_1_bits_uop_is_fence & ~stq_1_bits_uop_is_amo & dword_addr_matches_9_0 & can_forward_0; // @[lsu.scala:209:16, :263:49, :1045:29, :1150:{30,44,62,65,81,84,98,123}] assign ldst_forward_matches_0_1 = _T_494 & _T_502; // @[lsu.scala:1052:38, :1149:{29,45,72}, :1150:{62,81,98,123}, :1151:9, :1153:46] reg io_dmem_s1_kill_0_REG_11; // @[lsu.scala:1154:56] wire _T_507 = (|_T_505) & dword_addr_matches_9_0; // @[lsu.scala:263:49, :1150:30, :1157:{51,60}] reg io_dmem_s1_kill_0_REG_12; // @[lsu.scala:1160:56] wire _T_510 = stq_1_bits_uop_is_fence | stq_1_bits_uop_is_amo; // @[lsu.scala:209:16, :1163:37] assign ldst_addr_matches_0_1 = _T_494 & (_T_502 | _T_507 | _T_510); // @[lsu.scala:1050:38, :1149:{29,45,72}, :1150:{62,81,98,123}, :1151:9, :1152:46, :1157:60, :1158:9, :1159:46, :1163:37, :1164:9, :1165:46] reg io_dmem_s1_kill_0_REG_13; // @[lsu.scala:1166:56] wire _GEN_294 = _T_494 ? (_T_502 ? io_dmem_s1_kill_0_REG_11 : _T_507 ? io_dmem_s1_kill_0_REG_12 : _T_510 ? io_dmem_s1_kill_0_REG_13 : _GEN_284) : _GEN_284; // @[lsu.scala:1092:36, :1149:{29,45,72}, :1150:{62,81,98,123}, :1151:9, :1154:{46,56}, :1157:60, :1158:9, :1160:{46,56}, :1163:37, :1164:9, :1166:{46,56}] wire _GEN_295 = _T_502 | _T_507; // @[lsu.scala:1150:{62,81,98,123}, :1151:9, :1155:46, :1157:60, :1158:9] wire _GEN_296 = _T_494 ? (_GEN_295 ? ~_searcher_is_older_T_4 & _GEN_286 : ~(_T_510 & _searcher_is_older_T_4) & _GEN_286) : _GEN_286; // @[util.scala:363:52] wire _GEN_297 = _T_494 ? (_GEN_295 ? ~_GEN_234 & _GEN_287 : ~(_T_510 & _GEN_234) & _GEN_287) : _GEN_287; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_298 = _T_494 ? (_GEN_295 ? ~_GEN_235 & _GEN_288 : ~(_T_510 & _GEN_235) & _GEN_288) : _GEN_288; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_299 = _T_494 ? (_GEN_295 ? ~_GEN_236 & _GEN_289 : ~(_T_510 & _GEN_236) & _GEN_289) : _GEN_289; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_300 = _T_494 ? (_GEN_295 ? ~_GEN_237 & _GEN_290 : ~(_T_510 & _GEN_237) & _GEN_290) : _GEN_290; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_301 = _T_494 ? (_GEN_295 ? ~_GEN_238 & _GEN_291 : ~(_T_510 & _GEN_238) & _GEN_291) : _GEN_291; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_302 = _T_494 ? (_GEN_295 ? ~_GEN_239 & _GEN_292 : ~(_T_510 & _GEN_239) & _GEN_292) : _GEN_292; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_303 = _T_494 ? (_GEN_295 ? ~(&lcam_ldq_idx_0) & _GEN_293 : ~(_T_510 & (&lcam_ldq_idx_0)) & _GEN_293) : _GEN_293; // @[lsu.scala:263:49, :1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _dword_addr_matches_T_44 = ~stq_2_bits_addr_is_virtual; // @[lsu.scala:209:16, :1145:31] wire _dword_addr_matches_T_45 = stq_2_bits_addr_valid & _dword_addr_matches_T_44; // @[lsu.scala:209:16, :1144:60, :1145:31] wire [28:0] _dword_addr_matches_T_46 = stq_2_bits_addr_bits[31:3]; // @[lsu.scala:209:16, :1146:38] wire _dword_addr_matches_T_48 = _dword_addr_matches_T_46 == _dword_addr_matches_T_47; // @[lsu.scala:1146:{38,58,74}] wire _dword_addr_matches_T_49 = _dword_addr_matches_T_45 & _dword_addr_matches_T_48; // @[lsu.scala:1144:60, :1145:60, :1146:58] wire dword_addr_matches_10_0 = _dword_addr_matches_T_49; // @[lsu.scala:263:49, :1145:60] wire [7:0] write_mask_2; // @[lsu.scala:1665:22] wire _write_mask_mask_T_30 = stq_2_bits_uop_mem_size == 2'h0; // @[lsu.scala:209:16, :1667:26] wire [2:0] _write_mask_mask_T_31 = stq_2_bits_addr_bits[2:0]; // @[lsu.scala:209:16, :1667:55] wire [14:0] _write_mask_mask_T_32 = 15'h1 << _write_mask_mask_T_31; // @[lsu.scala:1667:{48,55}] wire _write_mask_mask_T_33 = stq_2_bits_uop_mem_size == 2'h1; // @[lsu.scala:209:16, :1668:26] wire [1:0] _write_mask_mask_T_34 = stq_2_bits_addr_bits[2:1]; // @[lsu.scala:209:16, :1668:56] wire [2:0] _write_mask_mask_T_35 = {_write_mask_mask_T_34, 1'h0}; // @[lsu.scala:1668:{56,62}] wire [14:0] _write_mask_mask_T_36 = 15'h3 << _write_mask_mask_T_35; // @[lsu.scala:1668:{48,62}] wire _write_mask_mask_T_37 = stq_2_bits_uop_mem_size == 2'h2; // @[lsu.scala:209:16, :1669:26] wire _write_mask_mask_T_38 = stq_2_bits_addr_bits[2]; // @[lsu.scala:209:16, :1669:46] wire [7:0] _write_mask_mask_T_39 = _write_mask_mask_T_38 ? 8'hF0 : 8'hF; // @[lsu.scala:1669:{41,46}] wire _write_mask_mask_T_40 = &stq_2_bits_uop_mem_size; // @[lsu.scala:209:16, :1670:26] wire [7:0] _write_mask_mask_T_42 = _write_mask_mask_T_37 ? _write_mask_mask_T_39 : 8'hFF; // @[Mux.scala:126:16] wire [14:0] _write_mask_mask_T_43 = _write_mask_mask_T_33 ? _write_mask_mask_T_36 : {7'h0, _write_mask_mask_T_42}; // @[Mux.scala:126:16] wire [14:0] _write_mask_mask_T_44 = _write_mask_mask_T_30 ? _write_mask_mask_T_32 : _write_mask_mask_T_43; // @[Mux.scala:126:16] assign write_mask_2 = _write_mask_mask_T_44[7:0]; // @[Mux.scala:126:16] wire _T_515 = do_ld_search_0 & stq_2_valid & lcam_st_dep_mask_0[2]; // @[lsu.scala:209:16, :263:49, :1149:{29,45,67}] wire [7:0] _T_526 = lcam_mask_0 & write_mask_2; // @[lsu.scala:263:49, :1150:30, :1665:22] wire _T_523 = _T_526 == lcam_mask_0 & ~stq_2_bits_uop_is_fence & ~stq_2_bits_uop_is_amo & dword_addr_matches_10_0 & can_forward_0; // @[lsu.scala:209:16, :263:49, :1045:29, :1150:{30,44,62,65,81,84,98,123}] assign ldst_forward_matches_0_2 = _T_515 & _T_523; // @[lsu.scala:1052:38, :1149:{29,45,72}, :1150:{62,81,98,123}, :1151:9, :1153:46] reg io_dmem_s1_kill_0_REG_14; // @[lsu.scala:1154:56] wire _T_528 = (|_T_526) & dword_addr_matches_10_0; // @[lsu.scala:263:49, :1150:30, :1157:{51,60}] reg io_dmem_s1_kill_0_REG_15; // @[lsu.scala:1160:56] wire _T_531 = stq_2_bits_uop_is_fence | stq_2_bits_uop_is_amo; // @[lsu.scala:209:16, :1163:37] assign ldst_addr_matches_0_2 = _T_515 & (_T_523 | _T_528 | _T_531); // @[lsu.scala:1050:38, :1149:{29,45,72}, :1150:{62,81,98,123}, :1151:9, :1152:46, :1157:60, :1158:9, :1159:46, :1163:37, :1164:9, :1165:46] reg io_dmem_s1_kill_0_REG_16; // @[lsu.scala:1166:56] wire _GEN_304 = _T_515 ? (_T_523 ? io_dmem_s1_kill_0_REG_14 : _T_528 ? io_dmem_s1_kill_0_REG_15 : _T_531 ? io_dmem_s1_kill_0_REG_16 : _GEN_294) : _GEN_294; // @[lsu.scala:1149:{29,45,72}, :1150:{62,81,98,123}, :1151:9, :1154:{46,56}, :1157:60, :1158:9, :1160:{46,56}, :1163:37, :1164:9, :1166:{46,56}] wire _GEN_305 = _T_523 | _T_528; // @[lsu.scala:1150:{62,81,98,123}, :1151:9, :1155:46, :1157:60, :1158:9] wire _GEN_306 = _T_515 ? (_GEN_305 ? ~_searcher_is_older_T_4 & _GEN_296 : ~(_T_531 & _searcher_is_older_T_4) & _GEN_296) : _GEN_296; // @[util.scala:363:52] wire _GEN_307 = _T_515 ? (_GEN_305 ? ~_GEN_234 & _GEN_297 : ~(_T_531 & _GEN_234) & _GEN_297) : _GEN_297; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_308 = _T_515 ? (_GEN_305 ? ~_GEN_235 & _GEN_298 : ~(_T_531 & _GEN_235) & _GEN_298) : _GEN_298; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_309 = _T_515 ? (_GEN_305 ? ~_GEN_236 & _GEN_299 : ~(_T_531 & _GEN_236) & _GEN_299) : _GEN_299; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_310 = _T_515 ? (_GEN_305 ? ~_GEN_237 & _GEN_300 : ~(_T_531 & _GEN_237) & _GEN_300) : _GEN_300; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_311 = _T_515 ? (_GEN_305 ? ~_GEN_238 & _GEN_301 : ~(_T_531 & _GEN_238) & _GEN_301) : _GEN_301; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_312 = _T_515 ? (_GEN_305 ? ~_GEN_239 & _GEN_302 : ~(_T_531 & _GEN_239) & _GEN_302) : _GEN_302; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_313 = _T_515 ? (_GEN_305 ? ~(&lcam_ldq_idx_0) & _GEN_303 : ~(_T_531 & (&lcam_ldq_idx_0)) & _GEN_303) : _GEN_303; // @[lsu.scala:263:49, :1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _dword_addr_matches_T_50 = ~stq_3_bits_addr_is_virtual; // @[lsu.scala:209:16, :1145:31] wire _dword_addr_matches_T_51 = stq_3_bits_addr_valid & _dword_addr_matches_T_50; // @[lsu.scala:209:16, :1144:60, :1145:31] wire [28:0] _dword_addr_matches_T_52 = stq_3_bits_addr_bits[31:3]; // @[lsu.scala:209:16, :1146:38] wire _dword_addr_matches_T_54 = _dword_addr_matches_T_52 == _dword_addr_matches_T_53; // @[lsu.scala:1146:{38,58,74}] wire _dword_addr_matches_T_55 = _dword_addr_matches_T_51 & _dword_addr_matches_T_54; // @[lsu.scala:1144:60, :1145:60, :1146:58] wire dword_addr_matches_11_0 = _dword_addr_matches_T_55; // @[lsu.scala:263:49, :1145:60] wire [7:0] write_mask_3; // @[lsu.scala:1665:22] wire _write_mask_mask_T_45 = stq_3_bits_uop_mem_size == 2'h0; // @[lsu.scala:209:16, :1667:26] wire [2:0] _write_mask_mask_T_46 = stq_3_bits_addr_bits[2:0]; // @[lsu.scala:209:16, :1667:55] wire [14:0] _write_mask_mask_T_47 = 15'h1 << _write_mask_mask_T_46; // @[lsu.scala:1667:{48,55}] wire _write_mask_mask_T_48 = stq_3_bits_uop_mem_size == 2'h1; // @[lsu.scala:209:16, :1668:26] wire [1:0] _write_mask_mask_T_49 = stq_3_bits_addr_bits[2:1]; // @[lsu.scala:209:16, :1668:56] wire [2:0] _write_mask_mask_T_50 = {_write_mask_mask_T_49, 1'h0}; // @[lsu.scala:1668:{56,62}] wire [14:0] _write_mask_mask_T_51 = 15'h3 << _write_mask_mask_T_50; // @[lsu.scala:1668:{48,62}] wire _write_mask_mask_T_52 = stq_3_bits_uop_mem_size == 2'h2; // @[lsu.scala:209:16, :1669:26] wire _write_mask_mask_T_53 = stq_3_bits_addr_bits[2]; // @[lsu.scala:209:16, :1669:46] wire [7:0] _write_mask_mask_T_54 = _write_mask_mask_T_53 ? 8'hF0 : 8'hF; // @[lsu.scala:1669:{41,46}] wire _write_mask_mask_T_55 = &stq_3_bits_uop_mem_size; // @[lsu.scala:209:16, :1670:26] wire [7:0] _write_mask_mask_T_57 = _write_mask_mask_T_52 ? _write_mask_mask_T_54 : 8'hFF; // @[Mux.scala:126:16] wire [14:0] _write_mask_mask_T_58 = _write_mask_mask_T_48 ? _write_mask_mask_T_51 : {7'h0, _write_mask_mask_T_57}; // @[Mux.scala:126:16] wire [14:0] _write_mask_mask_T_59 = _write_mask_mask_T_45 ? _write_mask_mask_T_47 : _write_mask_mask_T_58; // @[Mux.scala:126:16] assign write_mask_3 = _write_mask_mask_T_59[7:0]; // @[Mux.scala:126:16] wire _T_536 = do_ld_search_0 & stq_3_valid & lcam_st_dep_mask_0[3]; // @[lsu.scala:209:16, :263:49, :1149:{29,45,67}] wire [7:0] _T_547 = lcam_mask_0 & write_mask_3; // @[lsu.scala:263:49, :1150:30, :1665:22] wire _T_544 = _T_547 == lcam_mask_0 & ~stq_3_bits_uop_is_fence & ~stq_3_bits_uop_is_amo & dword_addr_matches_11_0 & can_forward_0; // @[lsu.scala:209:16, :263:49, :1045:29, :1150:{30,44,62,65,81,84,98,123}] assign ldst_forward_matches_0_3 = _T_536 & _T_544; // @[lsu.scala:1052:38, :1149:{29,45,72}, :1150:{62,81,98,123}, :1151:9, :1153:46] reg io_dmem_s1_kill_0_REG_17; // @[lsu.scala:1154:56] wire _T_549 = (|_T_547) & dword_addr_matches_11_0; // @[lsu.scala:263:49, :1150:30, :1157:{51,60}] reg io_dmem_s1_kill_0_REG_18; // @[lsu.scala:1160:56] wire _T_552 = stq_3_bits_uop_is_fence | stq_3_bits_uop_is_amo; // @[lsu.scala:209:16, :1163:37] assign ldst_addr_matches_0_3 = _T_536 & (_T_544 | _T_549 | _T_552); // @[lsu.scala:1050:38, :1149:{29,45,72}, :1150:{62,81,98,123}, :1151:9, :1152:46, :1157:60, :1158:9, :1159:46, :1163:37, :1164:9, :1165:46] reg io_dmem_s1_kill_0_REG_19; // @[lsu.scala:1166:56] wire _GEN_314 = _T_536 ? (_T_544 ? io_dmem_s1_kill_0_REG_17 : _T_549 ? io_dmem_s1_kill_0_REG_18 : _T_552 ? io_dmem_s1_kill_0_REG_19 : _GEN_304) : _GEN_304; // @[lsu.scala:1149:{29,45,72}, :1150:{62,81,98,123}, :1151:9, :1154:{46,56}, :1157:60, :1158:9, :1160:{46,56}, :1163:37, :1164:9, :1166:{46,56}] wire _GEN_315 = _T_544 | _T_549; // @[lsu.scala:1150:{62,81,98,123}, :1151:9, :1155:46, :1157:60, :1158:9] wire _GEN_316 = _T_536 ? (_GEN_315 ? ~_searcher_is_older_T_4 & _GEN_306 : ~(_T_552 & _searcher_is_older_T_4) & _GEN_306) : _GEN_306; // @[util.scala:363:52] wire _GEN_317 = _T_536 ? (_GEN_315 ? ~_GEN_234 & _GEN_307 : ~(_T_552 & _GEN_234) & _GEN_307) : _GEN_307; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_318 = _T_536 ? (_GEN_315 ? ~_GEN_235 & _GEN_308 : ~(_T_552 & _GEN_235) & _GEN_308) : _GEN_308; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_319 = _T_536 ? (_GEN_315 ? ~_GEN_236 & _GEN_309 : ~(_T_552 & _GEN_236) & _GEN_309) : _GEN_309; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_320 = _T_536 ? (_GEN_315 ? ~_GEN_237 & _GEN_310 : ~(_T_552 & _GEN_237) & _GEN_310) : _GEN_310; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_321 = _T_536 ? (_GEN_315 ? ~_GEN_238 & _GEN_311 : ~(_T_552 & _GEN_238) & _GEN_311) : _GEN_311; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_322 = _T_536 ? (_GEN_315 ? ~_GEN_239 & _GEN_312 : ~(_T_552 & _GEN_239) & _GEN_312) : _GEN_312; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_323 = _T_536 ? (_GEN_315 ? ~(&lcam_ldq_idx_0) & _GEN_313 : ~(_T_552 & (&lcam_ldq_idx_0)) & _GEN_313) : _GEN_313; // @[lsu.scala:263:49, :1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _dword_addr_matches_T_56 = ~stq_4_bits_addr_is_virtual; // @[lsu.scala:209:16, :1145:31] wire _dword_addr_matches_T_57 = stq_4_bits_addr_valid & _dword_addr_matches_T_56; // @[lsu.scala:209:16, :1144:60, :1145:31] wire [28:0] _dword_addr_matches_T_58 = stq_4_bits_addr_bits[31:3]; // @[lsu.scala:209:16, :1146:38] wire _dword_addr_matches_T_60 = _dword_addr_matches_T_58 == _dword_addr_matches_T_59; // @[lsu.scala:1146:{38,58,74}] wire _dword_addr_matches_T_61 = _dword_addr_matches_T_57 & _dword_addr_matches_T_60; // @[lsu.scala:1144:60, :1145:60, :1146:58] wire dword_addr_matches_12_0 = _dword_addr_matches_T_61; // @[lsu.scala:263:49, :1145:60] wire [7:0] write_mask_4; // @[lsu.scala:1665:22] wire _write_mask_mask_T_60 = stq_4_bits_uop_mem_size == 2'h0; // @[lsu.scala:209:16, :1667:26] wire [2:0] _write_mask_mask_T_61 = stq_4_bits_addr_bits[2:0]; // @[lsu.scala:209:16, :1667:55] wire [14:0] _write_mask_mask_T_62 = 15'h1 << _write_mask_mask_T_61; // @[lsu.scala:1667:{48,55}] wire _write_mask_mask_T_63 = stq_4_bits_uop_mem_size == 2'h1; // @[lsu.scala:209:16, :1668:26] wire [1:0] _write_mask_mask_T_64 = stq_4_bits_addr_bits[2:1]; // @[lsu.scala:209:16, :1668:56] wire [2:0] _write_mask_mask_T_65 = {_write_mask_mask_T_64, 1'h0}; // @[lsu.scala:1668:{56,62}] wire [14:0] _write_mask_mask_T_66 = 15'h3 << _write_mask_mask_T_65; // @[lsu.scala:1668:{48,62}] wire _write_mask_mask_T_67 = stq_4_bits_uop_mem_size == 2'h2; // @[lsu.scala:209:16, :1669:26] wire _write_mask_mask_T_68 = stq_4_bits_addr_bits[2]; // @[lsu.scala:209:16, :1669:46] wire [7:0] _write_mask_mask_T_69 = _write_mask_mask_T_68 ? 8'hF0 : 8'hF; // @[lsu.scala:1669:{41,46}] wire _write_mask_mask_T_70 = &stq_4_bits_uop_mem_size; // @[lsu.scala:209:16, :1670:26] wire [7:0] _write_mask_mask_T_72 = _write_mask_mask_T_67 ? _write_mask_mask_T_69 : 8'hFF; // @[Mux.scala:126:16] wire [14:0] _write_mask_mask_T_73 = _write_mask_mask_T_63 ? _write_mask_mask_T_66 : {7'h0, _write_mask_mask_T_72}; // @[Mux.scala:126:16] wire [14:0] _write_mask_mask_T_74 = _write_mask_mask_T_60 ? _write_mask_mask_T_62 : _write_mask_mask_T_73; // @[Mux.scala:126:16] assign write_mask_4 = _write_mask_mask_T_74[7:0]; // @[Mux.scala:126:16] wire _T_557 = do_ld_search_0 & stq_4_valid & lcam_st_dep_mask_0[4]; // @[lsu.scala:209:16, :263:49, :1149:{29,45,67}] wire [7:0] _T_568 = lcam_mask_0 & write_mask_4; // @[lsu.scala:263:49, :1150:30, :1665:22] wire _T_565 = _T_568 == lcam_mask_0 & ~stq_4_bits_uop_is_fence & ~stq_4_bits_uop_is_amo & dword_addr_matches_12_0 & can_forward_0; // @[lsu.scala:209:16, :263:49, :1045:29, :1150:{30,44,62,65,81,84,98,123}] assign ldst_forward_matches_0_4 = _T_557 & _T_565; // @[lsu.scala:1052:38, :1149:{29,45,72}, :1150:{62,81,98,123}, :1151:9, :1153:46] reg io_dmem_s1_kill_0_REG_20; // @[lsu.scala:1154:56] wire _T_570 = (|_T_568) & dword_addr_matches_12_0; // @[lsu.scala:263:49, :1150:30, :1157:{51,60}] reg io_dmem_s1_kill_0_REG_21; // @[lsu.scala:1160:56] wire _T_573 = stq_4_bits_uop_is_fence | stq_4_bits_uop_is_amo; // @[lsu.scala:209:16, :1163:37] assign ldst_addr_matches_0_4 = _T_557 & (_T_565 | _T_570 | _T_573); // @[lsu.scala:1050:38, :1149:{29,45,72}, :1150:{62,81,98,123}, :1151:9, :1152:46, :1157:60, :1158:9, :1159:46, :1163:37, :1164:9, :1165:46] reg io_dmem_s1_kill_0_REG_22; // @[lsu.scala:1166:56] wire _GEN_324 = _T_557 ? (_T_565 ? io_dmem_s1_kill_0_REG_20 : _T_570 ? io_dmem_s1_kill_0_REG_21 : _T_573 ? io_dmem_s1_kill_0_REG_22 : _GEN_314) : _GEN_314; // @[lsu.scala:1149:{29,45,72}, :1150:{62,81,98,123}, :1151:9, :1154:{46,56}, :1157:60, :1158:9, :1160:{46,56}, :1163:37, :1164:9, :1166:{46,56}] wire _GEN_325 = _T_565 | _T_570; // @[lsu.scala:1150:{62,81,98,123}, :1151:9, :1155:46, :1157:60, :1158:9] wire _GEN_326 = _T_557 ? (_GEN_325 ? ~_searcher_is_older_T_4 & _GEN_316 : ~(_T_573 & _searcher_is_older_T_4) & _GEN_316) : _GEN_316; // @[util.scala:363:52] wire _GEN_327 = _T_557 ? (_GEN_325 ? ~_GEN_234 & _GEN_317 : ~(_T_573 & _GEN_234) & _GEN_317) : _GEN_317; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_328 = _T_557 ? (_GEN_325 ? ~_GEN_235 & _GEN_318 : ~(_T_573 & _GEN_235) & _GEN_318) : _GEN_318; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_329 = _T_557 ? (_GEN_325 ? ~_GEN_236 & _GEN_319 : ~(_T_573 & _GEN_236) & _GEN_319) : _GEN_319; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_330 = _T_557 ? (_GEN_325 ? ~_GEN_237 & _GEN_320 : ~(_T_573 & _GEN_237) & _GEN_320) : _GEN_320; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_331 = _T_557 ? (_GEN_325 ? ~_GEN_238 & _GEN_321 : ~(_T_573 & _GEN_238) & _GEN_321) : _GEN_321; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_332 = _T_557 ? (_GEN_325 ? ~_GEN_239 & _GEN_322 : ~(_T_573 & _GEN_239) & _GEN_322) : _GEN_322; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_333 = _T_557 ? (_GEN_325 ? ~(&lcam_ldq_idx_0) & _GEN_323 : ~(_T_573 & (&lcam_ldq_idx_0)) & _GEN_323) : _GEN_323; // @[lsu.scala:263:49, :1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _dword_addr_matches_T_62 = ~stq_5_bits_addr_is_virtual; // @[lsu.scala:209:16, :1145:31] wire _dword_addr_matches_T_63 = stq_5_bits_addr_valid & _dword_addr_matches_T_62; // @[lsu.scala:209:16, :1144:60, :1145:31] wire [28:0] _dword_addr_matches_T_64 = stq_5_bits_addr_bits[31:3]; // @[lsu.scala:209:16, :1146:38] wire _dword_addr_matches_T_66 = _dword_addr_matches_T_64 == _dword_addr_matches_T_65; // @[lsu.scala:1146:{38,58,74}] wire _dword_addr_matches_T_67 = _dword_addr_matches_T_63 & _dword_addr_matches_T_66; // @[lsu.scala:1144:60, :1145:60, :1146:58] wire dword_addr_matches_13_0 = _dword_addr_matches_T_67; // @[lsu.scala:263:49, :1145:60] wire [7:0] write_mask_5; // @[lsu.scala:1665:22] wire _write_mask_mask_T_75 = stq_5_bits_uop_mem_size == 2'h0; // @[lsu.scala:209:16, :1667:26] wire [2:0] _write_mask_mask_T_76 = stq_5_bits_addr_bits[2:0]; // @[lsu.scala:209:16, :1667:55] wire [14:0] _write_mask_mask_T_77 = 15'h1 << _write_mask_mask_T_76; // @[lsu.scala:1667:{48,55}] wire _write_mask_mask_T_78 = stq_5_bits_uop_mem_size == 2'h1; // @[lsu.scala:209:16, :1668:26] wire [1:0] _write_mask_mask_T_79 = stq_5_bits_addr_bits[2:1]; // @[lsu.scala:209:16, :1668:56] wire [2:0] _write_mask_mask_T_80 = {_write_mask_mask_T_79, 1'h0}; // @[lsu.scala:1668:{56,62}] wire [14:0] _write_mask_mask_T_81 = 15'h3 << _write_mask_mask_T_80; // @[lsu.scala:1668:{48,62}] wire _write_mask_mask_T_82 = stq_5_bits_uop_mem_size == 2'h2; // @[lsu.scala:209:16, :1669:26] wire _write_mask_mask_T_83 = stq_5_bits_addr_bits[2]; // @[lsu.scala:209:16, :1669:46] wire [7:0] _write_mask_mask_T_84 = _write_mask_mask_T_83 ? 8'hF0 : 8'hF; // @[lsu.scala:1669:{41,46}] wire _write_mask_mask_T_85 = &stq_5_bits_uop_mem_size; // @[lsu.scala:209:16, :1670:26] wire [7:0] _write_mask_mask_T_87 = _write_mask_mask_T_82 ? _write_mask_mask_T_84 : 8'hFF; // @[Mux.scala:126:16] wire [14:0] _write_mask_mask_T_88 = _write_mask_mask_T_78 ? _write_mask_mask_T_81 : {7'h0, _write_mask_mask_T_87}; // @[Mux.scala:126:16] wire [14:0] _write_mask_mask_T_89 = _write_mask_mask_T_75 ? _write_mask_mask_T_77 : _write_mask_mask_T_88; // @[Mux.scala:126:16] assign write_mask_5 = _write_mask_mask_T_89[7:0]; // @[Mux.scala:126:16] wire _T_578 = do_ld_search_0 & stq_5_valid & lcam_st_dep_mask_0[5]; // @[lsu.scala:209:16, :263:49, :1149:{29,45,67}] wire [7:0] _T_589 = lcam_mask_0 & write_mask_5; // @[lsu.scala:263:49, :1150:30, :1665:22] wire _T_586 = _T_589 == lcam_mask_0 & ~stq_5_bits_uop_is_fence & ~stq_5_bits_uop_is_amo & dword_addr_matches_13_0 & can_forward_0; // @[lsu.scala:209:16, :263:49, :1045:29, :1150:{30,44,62,65,81,84,98,123}] assign ldst_forward_matches_0_5 = _T_578 & _T_586; // @[lsu.scala:1052:38, :1149:{29,45,72}, :1150:{62,81,98,123}, :1151:9, :1153:46] reg io_dmem_s1_kill_0_REG_23; // @[lsu.scala:1154:56] wire _T_591 = (|_T_589) & dword_addr_matches_13_0; // @[lsu.scala:263:49, :1150:30, :1157:{51,60}] reg io_dmem_s1_kill_0_REG_24; // @[lsu.scala:1160:56] wire _T_594 = stq_5_bits_uop_is_fence | stq_5_bits_uop_is_amo; // @[lsu.scala:209:16, :1163:37] assign ldst_addr_matches_0_5 = _T_578 & (_T_586 | _T_591 | _T_594); // @[lsu.scala:1050:38, :1149:{29,45,72}, :1150:{62,81,98,123}, :1151:9, :1152:46, :1157:60, :1158:9, :1159:46, :1163:37, :1164:9, :1165:46] reg io_dmem_s1_kill_0_REG_25; // @[lsu.scala:1166:56] wire _GEN_334 = _T_578 ? (_T_586 ? io_dmem_s1_kill_0_REG_23 : _T_591 ? io_dmem_s1_kill_0_REG_24 : _T_594 ? io_dmem_s1_kill_0_REG_25 : _GEN_324) : _GEN_324; // @[lsu.scala:1149:{29,45,72}, :1150:{62,81,98,123}, :1151:9, :1154:{46,56}, :1157:60, :1158:9, :1160:{46,56}, :1163:37, :1164:9, :1166:{46,56}] wire _GEN_335 = _T_586 | _T_591; // @[lsu.scala:1150:{62,81,98,123}, :1151:9, :1155:46, :1157:60, :1158:9] wire _GEN_336 = _T_578 ? (_GEN_335 ? ~_searcher_is_older_T_4 & _GEN_326 : ~(_T_594 & _searcher_is_older_T_4) & _GEN_326) : _GEN_326; // @[util.scala:363:52] wire _GEN_337 = _T_578 ? (_GEN_335 ? ~_GEN_234 & _GEN_327 : ~(_T_594 & _GEN_234) & _GEN_327) : _GEN_327; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_338 = _T_578 ? (_GEN_335 ? ~_GEN_235 & _GEN_328 : ~(_T_594 & _GEN_235) & _GEN_328) : _GEN_328; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_339 = _T_578 ? (_GEN_335 ? ~_GEN_236 & _GEN_329 : ~(_T_594 & _GEN_236) & _GEN_329) : _GEN_329; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_340 = _T_578 ? (_GEN_335 ? ~_GEN_237 & _GEN_330 : ~(_T_594 & _GEN_237) & _GEN_330) : _GEN_330; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_341 = _T_578 ? (_GEN_335 ? ~_GEN_238 & _GEN_331 : ~(_T_594 & _GEN_238) & _GEN_331) : _GEN_331; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_342 = _T_578 ? (_GEN_335 ? ~_GEN_239 & _GEN_332 : ~(_T_594 & _GEN_239) & _GEN_332) : _GEN_332; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_343 = _T_578 ? (_GEN_335 ? ~(&lcam_ldq_idx_0) & _GEN_333 : ~(_T_594 & (&lcam_ldq_idx_0)) & _GEN_333) : _GEN_333; // @[lsu.scala:263:49, :1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _dword_addr_matches_T_68 = ~stq_6_bits_addr_is_virtual; // @[lsu.scala:209:16, :1145:31] wire _dword_addr_matches_T_69 = stq_6_bits_addr_valid & _dword_addr_matches_T_68; // @[lsu.scala:209:16, :1144:60, :1145:31] wire [28:0] _dword_addr_matches_T_70 = stq_6_bits_addr_bits[31:3]; // @[lsu.scala:209:16, :1146:38] wire _dword_addr_matches_T_72 = _dword_addr_matches_T_70 == _dword_addr_matches_T_71; // @[lsu.scala:1146:{38,58,74}] wire _dword_addr_matches_T_73 = _dword_addr_matches_T_69 & _dword_addr_matches_T_72; // @[lsu.scala:1144:60, :1145:60, :1146:58] wire dword_addr_matches_14_0 = _dword_addr_matches_T_73; // @[lsu.scala:263:49, :1145:60] wire [7:0] write_mask_6; // @[lsu.scala:1665:22] wire _write_mask_mask_T_90 = stq_6_bits_uop_mem_size == 2'h0; // @[lsu.scala:209:16, :1667:26] wire [2:0] _write_mask_mask_T_91 = stq_6_bits_addr_bits[2:0]; // @[lsu.scala:209:16, :1667:55] wire [14:0] _write_mask_mask_T_92 = 15'h1 << _write_mask_mask_T_91; // @[lsu.scala:1667:{48,55}] wire _write_mask_mask_T_93 = stq_6_bits_uop_mem_size == 2'h1; // @[lsu.scala:209:16, :1668:26] wire [1:0] _write_mask_mask_T_94 = stq_6_bits_addr_bits[2:1]; // @[lsu.scala:209:16, :1668:56] wire [2:0] _write_mask_mask_T_95 = {_write_mask_mask_T_94, 1'h0}; // @[lsu.scala:1668:{56,62}] wire [14:0] _write_mask_mask_T_96 = 15'h3 << _write_mask_mask_T_95; // @[lsu.scala:1668:{48,62}] wire _write_mask_mask_T_97 = stq_6_bits_uop_mem_size == 2'h2; // @[lsu.scala:209:16, :1669:26] wire _write_mask_mask_T_98 = stq_6_bits_addr_bits[2]; // @[lsu.scala:209:16, :1669:46] wire [7:0] _write_mask_mask_T_99 = _write_mask_mask_T_98 ? 8'hF0 : 8'hF; // @[lsu.scala:1669:{41,46}] wire _write_mask_mask_T_100 = &stq_6_bits_uop_mem_size; // @[lsu.scala:209:16, :1670:26] wire [7:0] _write_mask_mask_T_102 = _write_mask_mask_T_97 ? _write_mask_mask_T_99 : 8'hFF; // @[Mux.scala:126:16] wire [14:0] _write_mask_mask_T_103 = _write_mask_mask_T_93 ? _write_mask_mask_T_96 : {7'h0, _write_mask_mask_T_102}; // @[Mux.scala:126:16] wire [14:0] _write_mask_mask_T_104 = _write_mask_mask_T_90 ? _write_mask_mask_T_92 : _write_mask_mask_T_103; // @[Mux.scala:126:16] assign write_mask_6 = _write_mask_mask_T_104[7:0]; // @[Mux.scala:126:16] wire _T_599 = do_ld_search_0 & stq_6_valid & lcam_st_dep_mask_0[6]; // @[lsu.scala:209:16, :263:49, :1149:{29,45,67}] wire [7:0] _T_610 = lcam_mask_0 & write_mask_6; // @[lsu.scala:263:49, :1150:30, :1665:22] wire _T_607 = _T_610 == lcam_mask_0 & ~stq_6_bits_uop_is_fence & ~stq_6_bits_uop_is_amo & dword_addr_matches_14_0 & can_forward_0; // @[lsu.scala:209:16, :263:49, :1045:29, :1150:{30,44,62,65,81,84,98,123}] assign ldst_forward_matches_0_6 = _T_599 & _T_607; // @[lsu.scala:1052:38, :1149:{29,45,72}, :1150:{62,81,98,123}, :1151:9, :1153:46] reg io_dmem_s1_kill_0_REG_26; // @[lsu.scala:1154:56] wire _T_612 = (|_T_610) & dword_addr_matches_14_0; // @[lsu.scala:263:49, :1150:30, :1157:{51,60}] reg io_dmem_s1_kill_0_REG_27; // @[lsu.scala:1160:56] wire _T_615 = stq_6_bits_uop_is_fence | stq_6_bits_uop_is_amo; // @[lsu.scala:209:16, :1163:37] assign ldst_addr_matches_0_6 = _T_599 & (_T_607 | _T_612 | _T_615); // @[lsu.scala:1050:38, :1149:{29,45,72}, :1150:{62,81,98,123}, :1151:9, :1152:46, :1157:60, :1158:9, :1159:46, :1163:37, :1164:9, :1165:46] reg io_dmem_s1_kill_0_REG_28; // @[lsu.scala:1166:56] wire _GEN_344 = _T_599 ? (_T_607 ? io_dmem_s1_kill_0_REG_26 : _T_612 ? io_dmem_s1_kill_0_REG_27 : _T_615 ? io_dmem_s1_kill_0_REG_28 : _GEN_334) : _GEN_334; // @[lsu.scala:1149:{29,45,72}, :1150:{62,81,98,123}, :1151:9, :1154:{46,56}, :1157:60, :1158:9, :1160:{46,56}, :1163:37, :1164:9, :1166:{46,56}] wire _GEN_345 = _T_607 | _T_612; // @[lsu.scala:1150:{62,81,98,123}, :1151:9, :1155:46, :1157:60, :1158:9] wire _GEN_346 = _T_599 ? (_GEN_345 ? ~_searcher_is_older_T_4 & _GEN_336 : ~(_T_615 & _searcher_is_older_T_4) & _GEN_336) : _GEN_336; // @[util.scala:363:52] wire _GEN_347 = _T_599 ? (_GEN_345 ? ~_GEN_234 & _GEN_337 : ~(_T_615 & _GEN_234) & _GEN_337) : _GEN_337; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_348 = _T_599 ? (_GEN_345 ? ~_GEN_235 & _GEN_338 : ~(_T_615 & _GEN_235) & _GEN_338) : _GEN_338; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_349 = _T_599 ? (_GEN_345 ? ~_GEN_236 & _GEN_339 : ~(_T_615 & _GEN_236) & _GEN_339) : _GEN_339; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_350 = _T_599 ? (_GEN_345 ? ~_GEN_237 & _GEN_340 : ~(_T_615 & _GEN_237) & _GEN_340) : _GEN_340; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_351 = _T_599 ? (_GEN_345 ? ~_GEN_238 & _GEN_341 : ~(_T_615 & _GEN_238) & _GEN_341) : _GEN_341; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_352 = _T_599 ? (_GEN_345 ? ~_GEN_239 & _GEN_342 : ~(_T_615 & _GEN_239) & _GEN_342) : _GEN_342; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_353 = _T_599 ? (_GEN_345 ? ~(&lcam_ldq_idx_0) & _GEN_343 : ~(_T_615 & (&lcam_ldq_idx_0)) & _GEN_343) : _GEN_343; // @[lsu.scala:263:49, :1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _dword_addr_matches_T_74 = ~stq_7_bits_addr_is_virtual; // @[lsu.scala:209:16, :1145:31] wire _dword_addr_matches_T_75 = stq_7_bits_addr_valid & _dword_addr_matches_T_74; // @[lsu.scala:209:16, :1144:60, :1145:31] wire [28:0] _dword_addr_matches_T_76 = stq_7_bits_addr_bits[31:3]; // @[lsu.scala:209:16, :1146:38] wire _dword_addr_matches_T_78 = _dword_addr_matches_T_76 == _dword_addr_matches_T_77; // @[lsu.scala:1146:{38,58,74}] wire _dword_addr_matches_T_79 = _dword_addr_matches_T_75 & _dword_addr_matches_T_78; // @[lsu.scala:1144:60, :1145:60, :1146:58] wire dword_addr_matches_15_0 = _dword_addr_matches_T_79; // @[lsu.scala:263:49, :1145:60] wire [7:0] write_mask_7; // @[lsu.scala:1665:22] wire _write_mask_mask_T_105 = stq_7_bits_uop_mem_size == 2'h0; // @[lsu.scala:209:16, :1667:26] wire [2:0] _write_mask_mask_T_106 = stq_7_bits_addr_bits[2:0]; // @[lsu.scala:209:16, :1667:55] wire [14:0] _write_mask_mask_T_107 = 15'h1 << _write_mask_mask_T_106; // @[lsu.scala:1667:{48,55}] wire _write_mask_mask_T_108 = stq_7_bits_uop_mem_size == 2'h1; // @[lsu.scala:209:16, :1668:26] wire [1:0] _write_mask_mask_T_109 = stq_7_bits_addr_bits[2:1]; // @[lsu.scala:209:16, :1668:56] wire [2:0] _write_mask_mask_T_110 = {_write_mask_mask_T_109, 1'h0}; // @[lsu.scala:1668:{56,62}] wire [14:0] _write_mask_mask_T_111 = 15'h3 << _write_mask_mask_T_110; // @[lsu.scala:1668:{48,62}] wire _write_mask_mask_T_112 = stq_7_bits_uop_mem_size == 2'h2; // @[lsu.scala:209:16, :1669:26] wire _write_mask_mask_T_113 = stq_7_bits_addr_bits[2]; // @[lsu.scala:209:16, :1669:46] wire [7:0] _write_mask_mask_T_114 = _write_mask_mask_T_113 ? 8'hF0 : 8'hF; // @[lsu.scala:1669:{41,46}] wire _write_mask_mask_T_115 = &stq_7_bits_uop_mem_size; // @[lsu.scala:209:16, :1670:26] wire [7:0] _write_mask_mask_T_117 = _write_mask_mask_T_112 ? _write_mask_mask_T_114 : 8'hFF; // @[Mux.scala:126:16] wire [14:0] _write_mask_mask_T_118 = _write_mask_mask_T_108 ? _write_mask_mask_T_111 : {7'h0, _write_mask_mask_T_117}; // @[Mux.scala:126:16] wire [14:0] _write_mask_mask_T_119 = _write_mask_mask_T_105 ? _write_mask_mask_T_107 : _write_mask_mask_T_118; // @[Mux.scala:126:16] assign write_mask_7 = _write_mask_mask_T_119[7:0]; // @[Mux.scala:126:16] wire _T_620 = do_ld_search_0 & stq_7_valid & lcam_st_dep_mask_0[7]; // @[lsu.scala:209:16, :263:49, :1149:{29,45,67}] wire [7:0] _T_631 = lcam_mask_0 & write_mask_7; // @[lsu.scala:263:49, :1150:30, :1665:22] wire _T_628 = _T_631 == lcam_mask_0 & ~stq_7_bits_uop_is_fence & ~stq_7_bits_uop_is_amo & dword_addr_matches_15_0 & can_forward_0; // @[lsu.scala:209:16, :263:49, :1045:29, :1150:{30,44,62,65,81,84,98,123}] assign ldst_forward_matches_0_7 = _T_620 & _T_628; // @[lsu.scala:1052:38, :1149:{29,45,72}, :1150:{62,81,98,123}, :1151:9, :1153:46] reg io_dmem_s1_kill_0_REG_29; // @[lsu.scala:1154:56] wire _T_633 = (|_T_631) & dword_addr_matches_15_0; // @[lsu.scala:263:49, :1150:30, :1157:{51,60}] reg io_dmem_s1_kill_0_REG_30; // @[lsu.scala:1160:56] wire _T_636 = stq_7_bits_uop_is_fence | stq_7_bits_uop_is_amo; // @[lsu.scala:209:16, :1163:37] assign ldst_addr_matches_0_7 = _T_620 & (_T_628 | _T_633 | _T_636); // @[lsu.scala:1050:38, :1149:{29,45,72}, :1150:{62,81,98,123}, :1151:9, :1152:46, :1157:60, :1158:9, :1159:46, :1163:37, :1164:9, :1165:46] reg io_dmem_s1_kill_0_REG_31; // @[lsu.scala:1166:56] assign io_dmem_s1_kill_0_0 = _T_620 ? (_T_628 ? io_dmem_s1_kill_0_REG_29 : _T_633 ? io_dmem_s1_kill_0_REG_30 : _T_636 ? io_dmem_s1_kill_0_REG_31 : _GEN_344) : _GEN_344; // @[lsu.scala:201:7, :1149:{29,45,72}, :1150:{62,81,98,123}, :1151:9, :1154:{46,56}, :1157:60, :1158:9, :1160:{46,56}, :1163:37, :1164:9, :1166:{46,56}] wire _GEN_354 = _T_628 | _T_633; // @[lsu.scala:1150:{62,81,98,123}, :1151:9, :1155:46, :1157:60, :1158:9] assign s1_set_execute_0 = _T_620 ? (_GEN_354 ? ~_searcher_is_older_T_4 & _GEN_346 : ~(_T_636 & _searcher_is_older_T_4) & _GEN_346) : _GEN_346; // @[util.scala:363:52] assign s1_set_execute_1 = _T_620 ? (_GEN_354 ? ~_GEN_234 & _GEN_347 : ~(_T_636 & _GEN_234) & _GEN_347) : _GEN_347; // @[lsu.scala:1058:36, :1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] assign s1_set_execute_2 = _T_620 ? (_GEN_354 ? ~_GEN_235 & _GEN_348 : ~(_T_636 & _GEN_235) & _GEN_348) : _GEN_348; // @[lsu.scala:1058:36, :1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] assign s1_set_execute_3 = _T_620 ? (_GEN_354 ? ~_GEN_236 & _GEN_349 : ~(_T_636 & _GEN_236) & _GEN_349) : _GEN_349; // @[lsu.scala:1058:36, :1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] assign s1_set_execute_4 = _T_620 ? (_GEN_354 ? ~_GEN_237 & _GEN_350 : ~(_T_636 & _GEN_237) & _GEN_350) : _GEN_350; // @[lsu.scala:1058:36, :1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] assign s1_set_execute_5 = _T_620 ? (_GEN_354 ? ~_GEN_238 & _GEN_351 : ~(_T_636 & _GEN_238) & _GEN_351) : _GEN_351; // @[lsu.scala:1058:36, :1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] assign s1_set_execute_6 = _T_620 ? (_GEN_354 ? ~_GEN_239 & _GEN_352 : ~(_T_636 & _GEN_239) & _GEN_352) : _GEN_352; // @[lsu.scala:1058:36, :1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] assign s1_set_execute_7 = _T_620 ? (_GEN_354 ? ~(&lcam_ldq_idx_0) & _GEN_353 : ~(_T_636 & (&lcam_ldq_idx_0)) & _GEN_353) : _GEN_353; // @[lsu.scala:263:49, :1058:36, :1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire [1:0] forwarding_age_logic_0_io_addr_matches_lo_lo = {ldst_addr_matches_0_1, ldst_addr_matches_0_0}; // @[lsu.scala:1050:38, :1181:72] wire [1:0] forwarding_age_logic_0_io_addr_matches_lo_hi = {ldst_addr_matches_0_3, ldst_addr_matches_0_2}; // @[lsu.scala:1050:38, :1181:72] wire [3:0] forwarding_age_logic_0_io_addr_matches_lo = {forwarding_age_logic_0_io_addr_matches_lo_hi, forwarding_age_logic_0_io_addr_matches_lo_lo}; // @[lsu.scala:1181:72] wire [1:0] forwarding_age_logic_0_io_addr_matches_hi_lo = {ldst_addr_matches_0_5, ldst_addr_matches_0_4}; // @[lsu.scala:1050:38, :1181:72] wire [1:0] forwarding_age_logic_0_io_addr_matches_hi_hi = {ldst_addr_matches_0_7, ldst_addr_matches_0_6}; // @[lsu.scala:1050:38, :1181:72] wire [3:0] forwarding_age_logic_0_io_addr_matches_hi = {forwarding_age_logic_0_io_addr_matches_hi_hi, forwarding_age_logic_0_io_addr_matches_hi_lo}; // @[lsu.scala:1181:72] wire [7:0] _forwarding_age_logic_0_io_addr_matches_T = {forwarding_age_logic_0_io_addr_matches_hi, forwarding_age_logic_0_io_addr_matches_lo}; // @[lsu.scala:1181:72] assign mem_forward_stq_idx_0 = forwarding_idx_0; // @[lsu.scala:263:49, :1063:33] wire [7:0] _GEN_355 = {{ldst_forward_matches_0_7}, {ldst_forward_matches_0_6}, {ldst_forward_matches_0_5}, {ldst_forward_matches_0_4}, {ldst_forward_matches_0_3}, {ldst_forward_matches_0_2}, {ldst_forward_matches_0_1}, {ldst_forward_matches_0_0}}; // @[lsu.scala:1052:38, :1188:86] reg REG_1; // @[lsu.scala:1190:64] assign mem_forward_valid_0 = _GEN_355[forwarding_idx_0] & (io_core_brupdate_b1_mispredict_mask_0 & lcam_uop_0_br_mask) == 8'h0 & ~io_core_exception_0 & ~REG_1; // @[util.scala:118:{51,59}] reg REG_2; // @[lsu.scala:1200:18] reg [3:0] store_blocked_counter; // @[lsu.scala:1205:36] wire _store_blocked_counter_T = &store_blocked_counter; // @[lsu.scala:1205:36, :1209:58] wire [4:0] _store_blocked_counter_T_1 = {1'h0, store_blocked_counter} + 5'h1; // @[lsu.scala:1205:36, :1209:96] wire [3:0] _store_blocked_counter_T_2 = _store_blocked_counter_T_1[3:0]; // @[lsu.scala:1209:96] wire [3:0] _store_blocked_counter_T_3 = _store_blocked_counter_T ? 4'hF : _store_blocked_counter_T_2; // @[lsu.scala:1209:{35,58,96}] assign block_load_wakeup = (&store_blocked_counter) | REG_2; // @[lsu.scala:499:35, :1200:{18,80}, :1205:36, :1211:{33,43}, :1212:25] wire _io_core_clr_unsafe_0_valid_T = do_st_search_0 | do_ld_search_0; // @[lsu.scala:263:49, :1221:61] wire _io_core_clr_unsafe_0_valid_T_1 = ~fired_load_wakeup_0; // @[lsu.scala:263:49, :1221:84] wire _io_core_clr_unsafe_0_valid_T_2 = _io_core_clr_unsafe_0_valid_T & _io_core_clr_unsafe_0_valid_T_1; // @[lsu.scala:1221:{61,81,84}] reg io_core_clr_unsafe_0_valid_REG; // @[lsu.scala:1221:43] reg [4:0] io_core_clr_unsafe_0_bits_REG; // @[lsu.scala:1222:43] assign io_core_clr_unsafe_0_bits_0 = io_core_clr_unsafe_0_bits_REG; // @[lsu.scala:201:7, :1222:43] wire _temp_bits_T_1 = failed_loads_0 & _temp_bits_T; // @[lsu.scala:1054:34, :1230:{21,28}] wire _temp_bits_WIRE_0 = _temp_bits_T_1; // @[lsu.scala:1229:59, :1230:21] wire _temp_bits_T_3 = failed_loads_1 & _temp_bits_T_2; // @[lsu.scala:1054:34, :1230:{21,28}] wire _temp_bits_WIRE_1 = _temp_bits_T_3; // @[lsu.scala:1229:59, :1230:21] wire _temp_bits_T_5 = failed_loads_2 & _temp_bits_T_4; // @[lsu.scala:1054:34, :1230:{21,28}] wire _temp_bits_WIRE_2 = _temp_bits_T_5; // @[lsu.scala:1229:59, :1230:21] wire _temp_bits_T_6 = ~_searcher_is_older_T_15; // @[util.scala:351:72, :363:78] wire _temp_bits_T_7 = failed_loads_3 & _temp_bits_T_6; // @[lsu.scala:1054:34, :1230:{21,28}] wire _temp_bits_WIRE_3 = _temp_bits_T_7; // @[lsu.scala:1229:59, :1230:21] wire _temp_bits_T_9 = failed_loads_4 & _temp_bits_T_8; // @[lsu.scala:1054:34, :1230:{21,28}] wire _temp_bits_WIRE_4 = _temp_bits_T_9; // @[lsu.scala:1229:59, :1230:21] wire _temp_bits_T_11 = failed_loads_5 & _temp_bits_T_10; // @[lsu.scala:1054:34, :1230:{21,28}] wire _temp_bits_WIRE_5 = _temp_bits_T_11; // @[lsu.scala:1229:59, :1230:21] wire _temp_bits_T_13 = failed_loads_6 & _temp_bits_T_12; // @[lsu.scala:1054:34, :1230:{21,28}] wire _temp_bits_WIRE_6 = _temp_bits_T_13; // @[lsu.scala:1229:59, :1230:21] wire _temp_bits_WIRE_7 = _temp_bits_T_15; // @[lsu.scala:1229:59, :1230:21] wire _temp_bits_WIRE_1_0 = _temp_bits_WIRE_0; // @[lsu.scala:1229:{27,59}] wire _temp_bits_WIRE_1_1 = _temp_bits_WIRE_1; // @[lsu.scala:1229:{27,59}] wire _temp_bits_WIRE_1_2 = _temp_bits_WIRE_2; // @[lsu.scala:1229:{27,59}] wire _temp_bits_WIRE_1_3 = _temp_bits_WIRE_3; // @[lsu.scala:1229:{27,59}] wire _temp_bits_WIRE_1_4 = _temp_bits_WIRE_4; // @[lsu.scala:1229:{27,59}] wire _temp_bits_WIRE_1_5 = _temp_bits_WIRE_5; // @[lsu.scala:1229:{27,59}] wire _temp_bits_WIRE_1_6 = _temp_bits_WIRE_6; // @[lsu.scala:1229:{27,59}] wire _temp_bits_WIRE_1_7 = _temp_bits_WIRE_7; // @[lsu.scala:1229:{27,59}] wire [1:0] temp_bits_lo_lo_lo = {_temp_bits_WIRE_1_1, _temp_bits_WIRE_1_0}; // @[lsu.scala:1229:27, :1230:59] wire [1:0] temp_bits_lo_lo_hi = {_temp_bits_WIRE_1_3, _temp_bits_WIRE_1_2}; // @[lsu.scala:1229:27, :1230:59] wire [3:0] temp_bits_lo_lo = {temp_bits_lo_lo_hi, temp_bits_lo_lo_lo}; // @[lsu.scala:1230:59] wire [1:0] temp_bits_lo_hi_lo = {_temp_bits_WIRE_1_5, _temp_bits_WIRE_1_4}; // @[lsu.scala:1229:27, :1230:59] wire [1:0] temp_bits_lo_hi_hi = {_temp_bits_WIRE_1_7, _temp_bits_WIRE_1_6}; // @[lsu.scala:1229:27, :1230:59] wire [3:0] temp_bits_lo_hi = {temp_bits_lo_hi_hi, temp_bits_lo_hi_lo}; // @[lsu.scala:1230:59] wire [7:0] temp_bits_lo = {temp_bits_lo_hi, temp_bits_lo_lo}; // @[lsu.scala:1230:59] wire [1:0] temp_bits_hi_lo_lo = {_temp_bits_WIRE_1_9, _temp_bits_WIRE_1_8}; // @[lsu.scala:1229:27, :1230:59] wire [1:0] temp_bits_hi_lo_hi = {_temp_bits_WIRE_1_11, _temp_bits_WIRE_1_10}; // @[lsu.scala:1229:27, :1230:59] wire [3:0] temp_bits_hi_lo = {temp_bits_hi_lo_hi, temp_bits_hi_lo_lo}; // @[lsu.scala:1230:59] wire [1:0] temp_bits_hi_hi_lo = {_temp_bits_WIRE_1_13, _temp_bits_WIRE_1_12}; // @[lsu.scala:1229:27, :1230:59] wire [1:0] temp_bits_hi_hi_hi = {_temp_bits_WIRE_1_15, _temp_bits_WIRE_1_14}; // @[lsu.scala:1229:27, :1230:59] wire [3:0] temp_bits_hi_hi = {temp_bits_hi_hi_hi, temp_bits_hi_hi_lo}; // @[lsu.scala:1230:59] wire [7:0] temp_bits_hi = {temp_bits_hi_hi, temp_bits_hi_lo}; // @[lsu.scala:1230:59] wire [15:0] temp_bits = {temp_bits_hi, temp_bits_lo}; // @[lsu.scala:1230:59] wire _l_idx_T = temp_bits[0]; // @[OneHot.scala:48:45] wire _l_idx_T_1 = temp_bits[1]; // @[OneHot.scala:48:45] wire _l_idx_T_2 = temp_bits[2]; // @[OneHot.scala:48:45] wire _l_idx_T_3 = temp_bits[3]; // @[OneHot.scala:48:45] wire _l_idx_T_4 = temp_bits[4]; // @[OneHot.scala:48:45] wire _l_idx_T_5 = temp_bits[5]; // @[OneHot.scala:48:45] wire _l_idx_T_6 = temp_bits[6]; // @[OneHot.scala:48:45] wire _l_idx_T_7 = temp_bits[7]; // @[OneHot.scala:48:45] wire _l_idx_T_8 = temp_bits[8]; // @[OneHot.scala:48:45] wire _l_idx_T_9 = temp_bits[9]; // @[OneHot.scala:48:45] wire _l_idx_T_10 = temp_bits[10]; // @[OneHot.scala:48:45] wire _l_idx_T_11 = temp_bits[11]; // @[OneHot.scala:48:45] wire _l_idx_T_12 = temp_bits[12]; // @[OneHot.scala:48:45] wire _l_idx_T_13 = temp_bits[13]; // @[OneHot.scala:48:45] wire _l_idx_T_14 = temp_bits[14]; // @[OneHot.scala:48:45] wire _l_idx_T_15 = temp_bits[15]; // @[OneHot.scala:48:45] wire [3:0] _l_idx_T_16 = {3'h7, ~_l_idx_T_14}; // @[OneHot.scala:48:45] wire [3:0] _l_idx_T_17 = _l_idx_T_13 ? 4'hD : _l_idx_T_16; // @[OneHot.scala:48:45] wire [3:0] _l_idx_T_18 = _l_idx_T_12 ? 4'hC : _l_idx_T_17; // @[OneHot.scala:48:45] wire [3:0] _l_idx_T_19 = _l_idx_T_11 ? 4'hB : _l_idx_T_18; // @[OneHot.scala:48:45] wire [3:0] _l_idx_T_20 = _l_idx_T_10 ? 4'hA : _l_idx_T_19; // @[OneHot.scala:48:45] wire [3:0] _l_idx_T_21 = _l_idx_T_9 ? 4'h9 : _l_idx_T_20; // @[OneHot.scala:48:45] wire [3:0] _l_idx_T_22 = _l_idx_T_8 ? 4'h8 : _l_idx_T_21; // @[OneHot.scala:48:45] wire [3:0] _l_idx_T_23 = _l_idx_T_7 ? 4'h7 : _l_idx_T_22; // @[OneHot.scala:48:45] wire [3:0] _l_idx_T_24 = _l_idx_T_6 ? 4'h6 : _l_idx_T_23; // @[OneHot.scala:48:45] wire [3:0] _l_idx_T_25 = _l_idx_T_5 ? 4'h5 : _l_idx_T_24; // @[OneHot.scala:48:45] wire [3:0] _l_idx_T_26 = _l_idx_T_4 ? 4'h4 : _l_idx_T_25; // @[OneHot.scala:48:45] wire [3:0] _l_idx_T_27 = _l_idx_T_3 ? 4'h3 : _l_idx_T_26; // @[OneHot.scala:48:45] wire [3:0] _l_idx_T_28 = _l_idx_T_2 ? 4'h2 : _l_idx_T_27; // @[OneHot.scala:48:45] wire [3:0] _l_idx_T_29 = _l_idx_T_1 ? 4'h1 : _l_idx_T_28; // @[OneHot.scala:48:45] wire [3:0] l_idx = _l_idx_T ? 4'h0 : _l_idx_T_29; // @[OneHot.scala:48:45] reg r_xcpt_valid; // @[lsu.scala:1236:29] reg [6:0] r_xcpt_uop_uopc; // @[lsu.scala:1237:25] assign io_core_lxcpt_bits_uop_uopc_0 = r_xcpt_uop_uopc; // @[lsu.scala:201:7, :1237:25] reg [31:0] r_xcpt_uop_inst; // @[lsu.scala:1237:25] assign io_core_lxcpt_bits_uop_inst_0 = r_xcpt_uop_inst; // @[lsu.scala:201:7, :1237:25] reg [31:0] r_xcpt_uop_debug_inst; // @[lsu.scala:1237:25] assign io_core_lxcpt_bits_uop_debug_inst_0 = r_xcpt_uop_debug_inst; // @[lsu.scala:201:7, :1237:25] reg r_xcpt_uop_is_rvc; // @[lsu.scala:1237:25] assign io_core_lxcpt_bits_uop_is_rvc_0 = r_xcpt_uop_is_rvc; // @[lsu.scala:201:7, :1237:25] reg [39:0] r_xcpt_uop_debug_pc; // @[lsu.scala:1237:25] assign io_core_lxcpt_bits_uop_debug_pc_0 = r_xcpt_uop_debug_pc; // @[lsu.scala:201:7, :1237:25] reg [2:0] r_xcpt_uop_iq_type; // @[lsu.scala:1237:25] assign io_core_lxcpt_bits_uop_iq_type_0 = r_xcpt_uop_iq_type; // @[lsu.scala:201:7, :1237:25] reg [9:0] r_xcpt_uop_fu_code; // @[lsu.scala:1237:25] assign io_core_lxcpt_bits_uop_fu_code_0 = r_xcpt_uop_fu_code; // @[lsu.scala:201:7, :1237:25] reg [3:0] r_xcpt_uop_ctrl_br_type; // @[lsu.scala:1237:25] assign io_core_lxcpt_bits_uop_ctrl_br_type_0 = r_xcpt_uop_ctrl_br_type; // @[lsu.scala:201:7, :1237:25] reg [1:0] r_xcpt_uop_ctrl_op1_sel; // @[lsu.scala:1237:25] assign io_core_lxcpt_bits_uop_ctrl_op1_sel_0 = r_xcpt_uop_ctrl_op1_sel; // @[lsu.scala:201:7, :1237:25] reg [2:0] r_xcpt_uop_ctrl_op2_sel; // @[lsu.scala:1237:25] assign io_core_lxcpt_bits_uop_ctrl_op2_sel_0 = r_xcpt_uop_ctrl_op2_sel; // @[lsu.scala:201:7, :1237:25] reg [2:0] r_xcpt_uop_ctrl_imm_sel; // @[lsu.scala:1237:25] assign io_core_lxcpt_bits_uop_ctrl_imm_sel_0 = r_xcpt_uop_ctrl_imm_sel; // @[lsu.scala:201:7, :1237:25] reg [4:0] r_xcpt_uop_ctrl_op_fcn; // @[lsu.scala:1237:25] assign io_core_lxcpt_bits_uop_ctrl_op_fcn_0 = r_xcpt_uop_ctrl_op_fcn; // @[lsu.scala:201:7, :1237:25] reg r_xcpt_uop_ctrl_fcn_dw; // @[lsu.scala:1237:25] assign io_core_lxcpt_bits_uop_ctrl_fcn_dw_0 = r_xcpt_uop_ctrl_fcn_dw; // @[lsu.scala:201:7, :1237:25] reg [2:0] r_xcpt_uop_ctrl_csr_cmd; // @[lsu.scala:1237:25] assign io_core_lxcpt_bits_uop_ctrl_csr_cmd_0 = r_xcpt_uop_ctrl_csr_cmd; // @[lsu.scala:201:7, :1237:25] reg r_xcpt_uop_ctrl_is_load; // @[lsu.scala:1237:25] assign io_core_lxcpt_bits_uop_ctrl_is_load_0 = r_xcpt_uop_ctrl_is_load; // @[lsu.scala:201:7, :1237:25] reg r_xcpt_uop_ctrl_is_sta; // @[lsu.scala:1237:25] assign io_core_lxcpt_bits_uop_ctrl_is_sta_0 = r_xcpt_uop_ctrl_is_sta; // @[lsu.scala:201:7, :1237:25] reg r_xcpt_uop_ctrl_is_std; // @[lsu.scala:1237:25] assign io_core_lxcpt_bits_uop_ctrl_is_std_0 = r_xcpt_uop_ctrl_is_std; // @[lsu.scala:201:7, :1237:25] reg [1:0] r_xcpt_uop_iw_state; // @[lsu.scala:1237:25] assign io_core_lxcpt_bits_uop_iw_state_0 = r_xcpt_uop_iw_state; // @[lsu.scala:201:7, :1237:25] reg r_xcpt_uop_iw_p1_poisoned; // @[lsu.scala:1237:25] assign io_core_lxcpt_bits_uop_iw_p1_poisoned_0 = r_xcpt_uop_iw_p1_poisoned; // @[lsu.scala:201:7, :1237:25] reg r_xcpt_uop_iw_p2_poisoned; // @[lsu.scala:1237:25] assign io_core_lxcpt_bits_uop_iw_p2_poisoned_0 = r_xcpt_uop_iw_p2_poisoned; // @[lsu.scala:201:7, :1237:25] reg r_xcpt_uop_is_br; // @[lsu.scala:1237:25] assign io_core_lxcpt_bits_uop_is_br_0 = r_xcpt_uop_is_br; // @[lsu.scala:201:7, :1237:25] reg r_xcpt_uop_is_jalr; // @[lsu.scala:1237:25] assign io_core_lxcpt_bits_uop_is_jalr_0 = r_xcpt_uop_is_jalr; // @[lsu.scala:201:7, :1237:25] reg r_xcpt_uop_is_jal; // @[lsu.scala:1237:25] assign io_core_lxcpt_bits_uop_is_jal_0 = r_xcpt_uop_is_jal; // @[lsu.scala:201:7, :1237:25] reg r_xcpt_uop_is_sfb; // @[lsu.scala:1237:25] assign io_core_lxcpt_bits_uop_is_sfb_0 = r_xcpt_uop_is_sfb; // @[lsu.scala:201:7, :1237:25] reg [7:0] r_xcpt_uop_br_mask; // @[lsu.scala:1237:25] assign io_core_lxcpt_bits_uop_br_mask_0 = r_xcpt_uop_br_mask; // @[lsu.scala:201:7, :1237:25] reg [2:0] r_xcpt_uop_br_tag; // @[lsu.scala:1237:25] assign io_core_lxcpt_bits_uop_br_tag_0 = r_xcpt_uop_br_tag; // @[lsu.scala:201:7, :1237:25] reg [3:0] r_xcpt_uop_ftq_idx; // @[lsu.scala:1237:25] assign io_core_lxcpt_bits_uop_ftq_idx_0 = r_xcpt_uop_ftq_idx; // @[lsu.scala:201:7, :1237:25] reg r_xcpt_uop_edge_inst; // @[lsu.scala:1237:25] assign io_core_lxcpt_bits_uop_edge_inst_0 = r_xcpt_uop_edge_inst; // @[lsu.scala:201:7, :1237:25] reg [5:0] r_xcpt_uop_pc_lob; // @[lsu.scala:1237:25] assign io_core_lxcpt_bits_uop_pc_lob_0 = r_xcpt_uop_pc_lob; // @[lsu.scala:201:7, :1237:25] reg r_xcpt_uop_taken; // @[lsu.scala:1237:25] assign io_core_lxcpt_bits_uop_taken_0 = r_xcpt_uop_taken; // @[lsu.scala:201:7, :1237:25] reg [19:0] r_xcpt_uop_imm_packed; // @[lsu.scala:1237:25] assign io_core_lxcpt_bits_uop_imm_packed_0 = r_xcpt_uop_imm_packed; // @[lsu.scala:201:7, :1237:25] reg [11:0] r_xcpt_uop_csr_addr; // @[lsu.scala:1237:25] assign io_core_lxcpt_bits_uop_csr_addr_0 = r_xcpt_uop_csr_addr; // @[lsu.scala:201:7, :1237:25] reg [4:0] r_xcpt_uop_rob_idx; // @[lsu.scala:1237:25] assign io_core_lxcpt_bits_uop_rob_idx_0 = r_xcpt_uop_rob_idx; // @[lsu.scala:201:7, :1237:25] reg [2:0] r_xcpt_uop_ldq_idx; // @[lsu.scala:1237:25] assign io_core_lxcpt_bits_uop_ldq_idx_0 = r_xcpt_uop_ldq_idx; // @[lsu.scala:201:7, :1237:25] reg [2:0] r_xcpt_uop_stq_idx; // @[lsu.scala:1237:25] assign io_core_lxcpt_bits_uop_stq_idx_0 = r_xcpt_uop_stq_idx; // @[lsu.scala:201:7, :1237:25] reg [1:0] r_xcpt_uop_rxq_idx; // @[lsu.scala:1237:25] assign io_core_lxcpt_bits_uop_rxq_idx_0 = r_xcpt_uop_rxq_idx; // @[lsu.scala:201:7, :1237:25] reg [5:0] r_xcpt_uop_pdst; // @[lsu.scala:1237:25] assign io_core_lxcpt_bits_uop_pdst_0 = r_xcpt_uop_pdst; // @[lsu.scala:201:7, :1237:25] reg [5:0] r_xcpt_uop_prs1; // @[lsu.scala:1237:25] assign io_core_lxcpt_bits_uop_prs1_0 = r_xcpt_uop_prs1; // @[lsu.scala:201:7, :1237:25] reg [5:0] r_xcpt_uop_prs2; // @[lsu.scala:1237:25] assign io_core_lxcpt_bits_uop_prs2_0 = r_xcpt_uop_prs2; // @[lsu.scala:201:7, :1237:25] reg [5:0] r_xcpt_uop_prs3; // @[lsu.scala:1237:25] assign io_core_lxcpt_bits_uop_prs3_0 = r_xcpt_uop_prs3; // @[lsu.scala:201:7, :1237:25] reg [3:0] r_xcpt_uop_ppred; // @[lsu.scala:1237:25] assign io_core_lxcpt_bits_uop_ppred_0 = r_xcpt_uop_ppred; // @[lsu.scala:201:7, :1237:25] reg r_xcpt_uop_prs1_busy; // @[lsu.scala:1237:25] assign io_core_lxcpt_bits_uop_prs1_busy_0 = r_xcpt_uop_prs1_busy; // @[lsu.scala:201:7, :1237:25] reg r_xcpt_uop_prs2_busy; // @[lsu.scala:1237:25] assign io_core_lxcpt_bits_uop_prs2_busy_0 = r_xcpt_uop_prs2_busy; // @[lsu.scala:201:7, :1237:25] reg r_xcpt_uop_prs3_busy; // @[lsu.scala:1237:25] assign io_core_lxcpt_bits_uop_prs3_busy_0 = r_xcpt_uop_prs3_busy; // @[lsu.scala:201:7, :1237:25] reg r_xcpt_uop_ppred_busy; // @[lsu.scala:1237:25] assign io_core_lxcpt_bits_uop_ppred_busy_0 = r_xcpt_uop_ppred_busy; // @[lsu.scala:201:7, :1237:25] reg [5:0] r_xcpt_uop_stale_pdst; // @[lsu.scala:1237:25] assign io_core_lxcpt_bits_uop_stale_pdst_0 = r_xcpt_uop_stale_pdst; // @[lsu.scala:201:7, :1237:25] reg r_xcpt_uop_exception; // @[lsu.scala:1237:25] assign io_core_lxcpt_bits_uop_exception_0 = r_xcpt_uop_exception; // @[lsu.scala:201:7, :1237:25] reg [63:0] r_xcpt_uop_exc_cause; // @[lsu.scala:1237:25] assign io_core_lxcpt_bits_uop_exc_cause_0 = r_xcpt_uop_exc_cause; // @[lsu.scala:201:7, :1237:25] reg r_xcpt_uop_bypassable; // @[lsu.scala:1237:25] assign io_core_lxcpt_bits_uop_bypassable_0 = r_xcpt_uop_bypassable; // @[lsu.scala:201:7, :1237:25] reg [4:0] r_xcpt_uop_mem_cmd; // @[lsu.scala:1237:25] assign io_core_lxcpt_bits_uop_mem_cmd_0 = r_xcpt_uop_mem_cmd; // @[lsu.scala:201:7, :1237:25] reg [1:0] r_xcpt_uop_mem_size; // @[lsu.scala:1237:25] assign io_core_lxcpt_bits_uop_mem_size_0 = r_xcpt_uop_mem_size; // @[lsu.scala:201:7, :1237:25] reg r_xcpt_uop_mem_signed; // @[lsu.scala:1237:25] assign io_core_lxcpt_bits_uop_mem_signed_0 = r_xcpt_uop_mem_signed; // @[lsu.scala:201:7, :1237:25] reg r_xcpt_uop_is_fence; // @[lsu.scala:1237:25] assign io_core_lxcpt_bits_uop_is_fence_0 = r_xcpt_uop_is_fence; // @[lsu.scala:201:7, :1237:25] reg r_xcpt_uop_is_fencei; // @[lsu.scala:1237:25] assign io_core_lxcpt_bits_uop_is_fencei_0 = r_xcpt_uop_is_fencei; // @[lsu.scala:201:7, :1237:25] reg r_xcpt_uop_is_amo; // @[lsu.scala:1237:25] assign io_core_lxcpt_bits_uop_is_amo_0 = r_xcpt_uop_is_amo; // @[lsu.scala:201:7, :1237:25] reg r_xcpt_uop_uses_ldq; // @[lsu.scala:1237:25] assign io_core_lxcpt_bits_uop_uses_ldq_0 = r_xcpt_uop_uses_ldq; // @[lsu.scala:201:7, :1237:25] reg r_xcpt_uop_uses_stq; // @[lsu.scala:1237:25] assign io_core_lxcpt_bits_uop_uses_stq_0 = r_xcpt_uop_uses_stq; // @[lsu.scala:201:7, :1237:25] reg r_xcpt_uop_is_sys_pc2epc; // @[lsu.scala:1237:25] assign io_core_lxcpt_bits_uop_is_sys_pc2epc_0 = r_xcpt_uop_is_sys_pc2epc; // @[lsu.scala:201:7, :1237:25] reg r_xcpt_uop_is_unique; // @[lsu.scala:1237:25] assign io_core_lxcpt_bits_uop_is_unique_0 = r_xcpt_uop_is_unique; // @[lsu.scala:201:7, :1237:25] reg r_xcpt_uop_flush_on_commit; // @[lsu.scala:1237:25] assign io_core_lxcpt_bits_uop_flush_on_commit_0 = r_xcpt_uop_flush_on_commit; // @[lsu.scala:201:7, :1237:25] reg r_xcpt_uop_ldst_is_rs1; // @[lsu.scala:1237:25] assign io_core_lxcpt_bits_uop_ldst_is_rs1_0 = r_xcpt_uop_ldst_is_rs1; // @[lsu.scala:201:7, :1237:25] reg [5:0] r_xcpt_uop_ldst; // @[lsu.scala:1237:25] assign io_core_lxcpt_bits_uop_ldst_0 = r_xcpt_uop_ldst; // @[lsu.scala:201:7, :1237:25] reg [5:0] r_xcpt_uop_lrs1; // @[lsu.scala:1237:25] assign io_core_lxcpt_bits_uop_lrs1_0 = r_xcpt_uop_lrs1; // @[lsu.scala:201:7, :1237:25] reg [5:0] r_xcpt_uop_lrs2; // @[lsu.scala:1237:25] assign io_core_lxcpt_bits_uop_lrs2_0 = r_xcpt_uop_lrs2; // @[lsu.scala:201:7, :1237:25] reg [5:0] r_xcpt_uop_lrs3; // @[lsu.scala:1237:25] assign io_core_lxcpt_bits_uop_lrs3_0 = r_xcpt_uop_lrs3; // @[lsu.scala:201:7, :1237:25] reg r_xcpt_uop_ldst_val; // @[lsu.scala:1237:25] assign io_core_lxcpt_bits_uop_ldst_val_0 = r_xcpt_uop_ldst_val; // @[lsu.scala:201:7, :1237:25] reg [1:0] r_xcpt_uop_dst_rtype; // @[lsu.scala:1237:25] assign io_core_lxcpt_bits_uop_dst_rtype_0 = r_xcpt_uop_dst_rtype; // @[lsu.scala:201:7, :1237:25] reg [1:0] r_xcpt_uop_lrs1_rtype; // @[lsu.scala:1237:25] assign io_core_lxcpt_bits_uop_lrs1_rtype_0 = r_xcpt_uop_lrs1_rtype; // @[lsu.scala:201:7, :1237:25] reg [1:0] r_xcpt_uop_lrs2_rtype; // @[lsu.scala:1237:25] assign io_core_lxcpt_bits_uop_lrs2_rtype_0 = r_xcpt_uop_lrs2_rtype; // @[lsu.scala:201:7, :1237:25] reg r_xcpt_uop_frs3_en; // @[lsu.scala:1237:25] assign io_core_lxcpt_bits_uop_frs3_en_0 = r_xcpt_uop_frs3_en; // @[lsu.scala:201:7, :1237:25] reg r_xcpt_uop_fp_val; // @[lsu.scala:1237:25] assign io_core_lxcpt_bits_uop_fp_val_0 = r_xcpt_uop_fp_val; // @[lsu.scala:201:7, :1237:25] reg r_xcpt_uop_fp_single; // @[lsu.scala:1237:25] assign io_core_lxcpt_bits_uop_fp_single_0 = r_xcpt_uop_fp_single; // @[lsu.scala:201:7, :1237:25] reg r_xcpt_uop_xcpt_pf_if; // @[lsu.scala:1237:25] assign io_core_lxcpt_bits_uop_xcpt_pf_if_0 = r_xcpt_uop_xcpt_pf_if; // @[lsu.scala:201:7, :1237:25] reg r_xcpt_uop_xcpt_ae_if; // @[lsu.scala:1237:25] assign io_core_lxcpt_bits_uop_xcpt_ae_if_0 = r_xcpt_uop_xcpt_ae_if; // @[lsu.scala:201:7, :1237:25] reg r_xcpt_uop_xcpt_ma_if; // @[lsu.scala:1237:25] assign io_core_lxcpt_bits_uop_xcpt_ma_if_0 = r_xcpt_uop_xcpt_ma_if; // @[lsu.scala:201:7, :1237:25] reg r_xcpt_uop_bp_debug_if; // @[lsu.scala:1237:25] assign io_core_lxcpt_bits_uop_bp_debug_if_0 = r_xcpt_uop_bp_debug_if; // @[lsu.scala:201:7, :1237:25] reg r_xcpt_uop_bp_xcpt_if; // @[lsu.scala:1237:25] assign io_core_lxcpt_bits_uop_bp_xcpt_if_0 = r_xcpt_uop_bp_xcpt_if; // @[lsu.scala:201:7, :1237:25] reg [1:0] r_xcpt_uop_debug_fsrc; // @[lsu.scala:1237:25] assign io_core_lxcpt_bits_uop_debug_fsrc_0 = r_xcpt_uop_debug_fsrc; // @[lsu.scala:201:7, :1237:25] reg [1:0] r_xcpt_uop_debug_tsrc; // @[lsu.scala:1237:25] assign io_core_lxcpt_bits_uop_debug_tsrc_0 = r_xcpt_uop_debug_tsrc; // @[lsu.scala:201:7, :1237:25] reg [4:0] r_xcpt_cause; // @[lsu.scala:1237:25] assign io_core_lxcpt_bits_cause_0 = r_xcpt_cause; // @[lsu.scala:201:7, :1237:25] reg [39:0] r_xcpt_badvaddr; // @[lsu.scala:1237:25] assign io_core_lxcpt_bits_badvaddr_0 = r_xcpt_badvaddr; // @[lsu.scala:201:7, :1237:25] wire _ld_xcpt_valid_T = failed_loads_0 | failed_loads_1; // @[lsu.scala:1054:34, :1239:44] wire _ld_xcpt_valid_T_1 = _ld_xcpt_valid_T | failed_loads_2; // @[lsu.scala:1054:34, :1239:44] wire _ld_xcpt_valid_T_2 = _ld_xcpt_valid_T_1 | failed_loads_3; // @[lsu.scala:1054:34, :1239:44] wire _ld_xcpt_valid_T_3 = _ld_xcpt_valid_T_2 | failed_loads_4; // @[lsu.scala:1054:34, :1239:44] wire _ld_xcpt_valid_T_4 = _ld_xcpt_valid_T_3 | failed_loads_5; // @[lsu.scala:1054:34, :1239:44] wire _ld_xcpt_valid_T_5 = _ld_xcpt_valid_T_4 | failed_loads_6; // @[lsu.scala:1054:34, :1239:44] wire ld_xcpt_valid = _ld_xcpt_valid_T_5 | failed_loads_7; // @[lsu.scala:1054:34, :1239:44] wire _ld_xcpt_uop_T = l_idx[3]; // @[Mux.scala:50:70] wire [4:0] _ld_xcpt_uop_T_1 = {1'h0, l_idx} - 5'h8; // @[Mux.scala:50:70] wire [3:0] _ld_xcpt_uop_T_2 = _ld_xcpt_uop_T_1[3:0]; // @[lsu.scala:1240:63] wire [3:0] _ld_xcpt_uop_T_3 = _ld_xcpt_uop_T ? _ld_xcpt_uop_T_2 : l_idx; // @[Mux.scala:50:70] wire [2:0] _ld_xcpt_uop_T_4 = _ld_xcpt_uop_T_3[2:0]; // @[lsu.scala:1240:30] wire _use_mem_xcpt_T = mem_xcpt_uop_rob_idx < _GEN_126[_ld_xcpt_uop_T_4]; // @[util.scala:363:52] wire _use_mem_xcpt_T_1 = mem_xcpt_uop_rob_idx < io_core_rob_head_idx_0; // @[util.scala:363:64] wire _use_mem_xcpt_T_2 = _use_mem_xcpt_T ^ _use_mem_xcpt_T_1; // @[util.scala:363:{52,58,64}] wire _use_mem_xcpt_T_3 = _GEN_126[_ld_xcpt_uop_T_4] < io_core_rob_head_idx_0; // @[util.scala:363:{52,78}] wire _use_mem_xcpt_T_4 = _use_mem_xcpt_T_2 ^ _use_mem_xcpt_T_3; // @[util.scala:363:{58,72,78}] wire _use_mem_xcpt_T_5 = mem_xcpt_valid & _use_mem_xcpt_T_4; // @[util.scala:363:72] wire _use_mem_xcpt_T_6 = ~ld_xcpt_valid; // @[lsu.scala:1239:44, :1242:118] wire use_mem_xcpt = _use_mem_xcpt_T_5 | _use_mem_xcpt_T_6; // @[lsu.scala:1242:{38,115,118}] wire [6:0] xcpt_uop_uopc = use_mem_xcpt ? mem_xcpt_uop_uopc : _GEN_94[_ld_xcpt_uop_T_4]; // @[util.scala:363:52] wire [31:0] xcpt_uop_inst = use_mem_xcpt ? mem_xcpt_uop_inst : _GEN_95[_ld_xcpt_uop_T_4]; // @[util.scala:363:52] wire [31:0] xcpt_uop_debug_inst = use_mem_xcpt ? mem_xcpt_uop_debug_inst : _GEN_96[_ld_xcpt_uop_T_4]; // @[util.scala:363:52] wire xcpt_uop_is_rvc = use_mem_xcpt ? mem_xcpt_uop_is_rvc : _GEN_97[_ld_xcpt_uop_T_4]; // @[util.scala:363:52] wire [39:0] xcpt_uop_debug_pc = use_mem_xcpt ? mem_xcpt_uop_debug_pc : _GEN_98[_ld_xcpt_uop_T_4]; // @[util.scala:363:52] wire [2:0] xcpt_uop_iq_type = use_mem_xcpt ? mem_xcpt_uop_iq_type : _GEN_99[_ld_xcpt_uop_T_4]; // @[util.scala:363:52] wire [9:0] xcpt_uop_fu_code = use_mem_xcpt ? mem_xcpt_uop_fu_code : _GEN_100[_ld_xcpt_uop_T_4]; // @[util.scala:363:52] wire [3:0] xcpt_uop_ctrl_br_type = use_mem_xcpt ? mem_xcpt_uop_ctrl_br_type : _GEN_101[_ld_xcpt_uop_T_4]; // @[util.scala:363:52] wire [1:0] xcpt_uop_ctrl_op1_sel = use_mem_xcpt ? mem_xcpt_uop_ctrl_op1_sel : _GEN_102[_ld_xcpt_uop_T_4]; // @[util.scala:363:52] wire [2:0] xcpt_uop_ctrl_op2_sel = use_mem_xcpt ? mem_xcpt_uop_ctrl_op2_sel : _GEN_103[_ld_xcpt_uop_T_4]; // @[util.scala:363:52] wire [2:0] xcpt_uop_ctrl_imm_sel = use_mem_xcpt ? mem_xcpt_uop_ctrl_imm_sel : _GEN_104[_ld_xcpt_uop_T_4]; // @[util.scala:363:52] wire [4:0] xcpt_uop_ctrl_op_fcn = use_mem_xcpt ? mem_xcpt_uop_ctrl_op_fcn : _GEN_105[_ld_xcpt_uop_T_4]; // @[util.scala:363:52] wire xcpt_uop_ctrl_fcn_dw = use_mem_xcpt ? mem_xcpt_uop_ctrl_fcn_dw : _GEN_106[_ld_xcpt_uop_T_4]; // @[util.scala:363:52] wire [2:0] xcpt_uop_ctrl_csr_cmd = use_mem_xcpt ? mem_xcpt_uop_ctrl_csr_cmd : _GEN_107[_ld_xcpt_uop_T_4]; // @[util.scala:363:52] wire xcpt_uop_ctrl_is_load = use_mem_xcpt ? mem_xcpt_uop_ctrl_is_load : _GEN_108[_ld_xcpt_uop_T_4]; // @[util.scala:363:52] wire xcpt_uop_ctrl_is_sta = use_mem_xcpt ? mem_xcpt_uop_ctrl_is_sta : _GEN_109[_ld_xcpt_uop_T_4]; // @[util.scala:363:52] wire xcpt_uop_ctrl_is_std = use_mem_xcpt ? mem_xcpt_uop_ctrl_is_std : _GEN_110[_ld_xcpt_uop_T_4]; // @[util.scala:363:52] wire [1:0] xcpt_uop_iw_state = use_mem_xcpt ? mem_xcpt_uop_iw_state : _GEN_111[_ld_xcpt_uop_T_4]; // @[util.scala:363:52] wire xcpt_uop_iw_p1_poisoned = use_mem_xcpt ? mem_xcpt_uop_iw_p1_poisoned : _GEN_112[_ld_xcpt_uop_T_4]; // @[util.scala:363:52] wire xcpt_uop_iw_p2_poisoned = use_mem_xcpt ? mem_xcpt_uop_iw_p2_poisoned : _GEN_113[_ld_xcpt_uop_T_4]; // @[util.scala:363:52] wire xcpt_uop_is_br = use_mem_xcpt ? mem_xcpt_uop_is_br : _GEN_114[_ld_xcpt_uop_T_4]; // @[util.scala:363:52] wire xcpt_uop_is_jalr = use_mem_xcpt ? mem_xcpt_uop_is_jalr : _GEN_115[_ld_xcpt_uop_T_4]; // @[util.scala:363:52] wire xcpt_uop_is_jal = use_mem_xcpt ? mem_xcpt_uop_is_jal : _GEN_116[_ld_xcpt_uop_T_4]; // @[util.scala:363:52] wire xcpt_uop_is_sfb = use_mem_xcpt ? mem_xcpt_uop_is_sfb : _GEN_117[_ld_xcpt_uop_T_4]; // @[util.scala:363:52] wire [7:0] xcpt_uop_br_mask = use_mem_xcpt ? mem_xcpt_uop_br_mask : _GEN_118[_ld_xcpt_uop_T_4]; // @[util.scala:363:52] wire [2:0] xcpt_uop_br_tag = use_mem_xcpt ? mem_xcpt_uop_br_tag : _GEN_119[_ld_xcpt_uop_T_4]; // @[util.scala:363:52] wire [3:0] xcpt_uop_ftq_idx = use_mem_xcpt ? mem_xcpt_uop_ftq_idx : _GEN_120[_ld_xcpt_uop_T_4]; // @[util.scala:363:52] wire xcpt_uop_edge_inst = use_mem_xcpt ? mem_xcpt_uop_edge_inst : _GEN_121[_ld_xcpt_uop_T_4]; // @[util.scala:363:52] wire [5:0] xcpt_uop_pc_lob = use_mem_xcpt ? mem_xcpt_uop_pc_lob : _GEN_122[_ld_xcpt_uop_T_4]; // @[util.scala:363:52] wire xcpt_uop_taken = use_mem_xcpt ? mem_xcpt_uop_taken : _GEN_123[_ld_xcpt_uop_T_4]; // @[util.scala:363:52] wire [19:0] xcpt_uop_imm_packed = use_mem_xcpt ? mem_xcpt_uop_imm_packed : _GEN_124[_ld_xcpt_uop_T_4]; // @[util.scala:363:52] wire [11:0] xcpt_uop_csr_addr = use_mem_xcpt ? mem_xcpt_uop_csr_addr : _GEN_125[_ld_xcpt_uop_T_4]; // @[util.scala:363:52] wire [4:0] xcpt_uop_rob_idx = use_mem_xcpt ? mem_xcpt_uop_rob_idx : _GEN_126[_ld_xcpt_uop_T_4]; // @[util.scala:363:52] wire [2:0] xcpt_uop_ldq_idx = use_mem_xcpt ? mem_xcpt_uop_ldq_idx : _GEN_127[_ld_xcpt_uop_T_4]; // @[util.scala:363:52] wire [2:0] xcpt_uop_stq_idx = use_mem_xcpt ? mem_xcpt_uop_stq_idx : _GEN_128[_ld_xcpt_uop_T_4]; // @[util.scala:363:52] wire [1:0] xcpt_uop_rxq_idx = use_mem_xcpt ? mem_xcpt_uop_rxq_idx : _GEN_129[_ld_xcpt_uop_T_4]; // @[util.scala:363:52] wire [5:0] xcpt_uop_pdst = use_mem_xcpt ? mem_xcpt_uop_pdst : _GEN_130[_ld_xcpt_uop_T_4]; // @[util.scala:363:52] wire [5:0] xcpt_uop_prs1 = use_mem_xcpt ? mem_xcpt_uop_prs1 : _GEN_131[_ld_xcpt_uop_T_4]; // @[util.scala:363:52] wire [5:0] xcpt_uop_prs2 = use_mem_xcpt ? mem_xcpt_uop_prs2 : _GEN_132[_ld_xcpt_uop_T_4]; // @[util.scala:363:52] wire [5:0] xcpt_uop_prs3 = use_mem_xcpt ? mem_xcpt_uop_prs3 : _GEN_133[_ld_xcpt_uop_T_4]; // @[util.scala:363:52] wire [3:0] xcpt_uop_ppred = use_mem_xcpt ? mem_xcpt_uop_ppred : 4'h0; // @[lsu.scala:360:29, :1242:115, :1244:21] wire xcpt_uop_prs1_busy = use_mem_xcpt ? mem_xcpt_uop_prs1_busy : _GEN_134[_ld_xcpt_uop_T_4]; // @[util.scala:363:52] wire xcpt_uop_prs2_busy = use_mem_xcpt ? mem_xcpt_uop_prs2_busy : _GEN_135[_ld_xcpt_uop_T_4]; // @[util.scala:363:52] wire xcpt_uop_prs3_busy = use_mem_xcpt ? mem_xcpt_uop_prs3_busy : _GEN_136[_ld_xcpt_uop_T_4]; // @[util.scala:363:52] wire xcpt_uop_ppred_busy = use_mem_xcpt & mem_xcpt_uop_ppred_busy; // @[lsu.scala:360:29, :1242:115, :1244:21] wire [5:0] xcpt_uop_stale_pdst = use_mem_xcpt ? mem_xcpt_uop_stale_pdst : _GEN_137[_ld_xcpt_uop_T_4]; // @[util.scala:363:52] wire xcpt_uop_exception = use_mem_xcpt ? mem_xcpt_uop_exception : _GEN_138[_ld_xcpt_uop_T_4]; // @[util.scala:363:52] wire [63:0] xcpt_uop_exc_cause = use_mem_xcpt ? mem_xcpt_uop_exc_cause : _GEN_139[_ld_xcpt_uop_T_4]; // @[util.scala:363:52] wire xcpt_uop_bypassable = use_mem_xcpt ? mem_xcpt_uop_bypassable : _GEN_140[_ld_xcpt_uop_T_4]; // @[util.scala:363:52] wire [4:0] xcpt_uop_mem_cmd = use_mem_xcpt ? mem_xcpt_uop_mem_cmd : _GEN_141[_ld_xcpt_uop_T_4]; // @[util.scala:363:52] wire [1:0] xcpt_uop_mem_size = use_mem_xcpt ? mem_xcpt_uop_mem_size : _GEN_142[_ld_xcpt_uop_T_4]; // @[util.scala:363:52] wire xcpt_uop_mem_signed = use_mem_xcpt ? mem_xcpt_uop_mem_signed : _GEN_143[_ld_xcpt_uop_T_4]; // @[util.scala:363:52] wire xcpt_uop_is_fence = use_mem_xcpt ? mem_xcpt_uop_is_fence : _GEN_144[_ld_xcpt_uop_T_4]; // @[util.scala:363:52] wire xcpt_uop_is_fencei = use_mem_xcpt ? mem_xcpt_uop_is_fencei : _GEN_145[_ld_xcpt_uop_T_4]; // @[util.scala:363:52] wire xcpt_uop_is_amo = use_mem_xcpt ? mem_xcpt_uop_is_amo : _GEN_146[_ld_xcpt_uop_T_4]; // @[util.scala:363:52] wire xcpt_uop_uses_ldq = use_mem_xcpt ? mem_xcpt_uop_uses_ldq : _GEN_147[_ld_xcpt_uop_T_4]; // @[util.scala:363:52] wire xcpt_uop_uses_stq = use_mem_xcpt ? mem_xcpt_uop_uses_stq : _GEN_148[_ld_xcpt_uop_T_4]; // @[util.scala:363:52] wire xcpt_uop_is_sys_pc2epc = use_mem_xcpt ? mem_xcpt_uop_is_sys_pc2epc : _GEN_149[_ld_xcpt_uop_T_4]; // @[util.scala:363:52] wire xcpt_uop_is_unique = use_mem_xcpt ? mem_xcpt_uop_is_unique : _GEN_150[_ld_xcpt_uop_T_4]; // @[util.scala:363:52] wire xcpt_uop_flush_on_commit = use_mem_xcpt ? mem_xcpt_uop_flush_on_commit : _GEN_151[_ld_xcpt_uop_T_4]; // @[util.scala:363:52] wire xcpt_uop_ldst_is_rs1 = use_mem_xcpt ? mem_xcpt_uop_ldst_is_rs1 : _GEN_152[_ld_xcpt_uop_T_4]; // @[util.scala:363:52] wire [5:0] xcpt_uop_ldst = use_mem_xcpt ? mem_xcpt_uop_ldst : _GEN_153[_ld_xcpt_uop_T_4]; // @[util.scala:363:52] wire [5:0] xcpt_uop_lrs1 = use_mem_xcpt ? mem_xcpt_uop_lrs1 : _GEN_154[_ld_xcpt_uop_T_4]; // @[util.scala:363:52] wire [5:0] xcpt_uop_lrs2 = use_mem_xcpt ? mem_xcpt_uop_lrs2 : _GEN_155[_ld_xcpt_uop_T_4]; // @[util.scala:363:52] wire [5:0] xcpt_uop_lrs3 = use_mem_xcpt ? mem_xcpt_uop_lrs3 : _GEN_156[_ld_xcpt_uop_T_4]; // @[util.scala:363:52] wire xcpt_uop_ldst_val = use_mem_xcpt ? mem_xcpt_uop_ldst_val : _GEN_157[_ld_xcpt_uop_T_4]; // @[util.scala:363:52] wire [1:0] xcpt_uop_dst_rtype = use_mem_xcpt ? mem_xcpt_uop_dst_rtype : _GEN_158[_ld_xcpt_uop_T_4]; // @[util.scala:363:52] wire [1:0] xcpt_uop_lrs1_rtype = use_mem_xcpt ? mem_xcpt_uop_lrs1_rtype : _GEN_159[_ld_xcpt_uop_T_4]; // @[util.scala:363:52] wire [1:0] xcpt_uop_lrs2_rtype = use_mem_xcpt ? mem_xcpt_uop_lrs2_rtype : _GEN_160[_ld_xcpt_uop_T_4]; // @[util.scala:363:52] wire xcpt_uop_frs3_en = use_mem_xcpt ? mem_xcpt_uop_frs3_en : _GEN_161[_ld_xcpt_uop_T_4]; // @[util.scala:363:52] wire xcpt_uop_fp_val = use_mem_xcpt ? mem_xcpt_uop_fp_val : _GEN_162[_ld_xcpt_uop_T_4]; // @[util.scala:363:52] wire xcpt_uop_fp_single = use_mem_xcpt ? mem_xcpt_uop_fp_single : _GEN_163[_ld_xcpt_uop_T_4]; // @[util.scala:363:52] wire xcpt_uop_xcpt_pf_if = use_mem_xcpt ? mem_xcpt_uop_xcpt_pf_if : _GEN_164[_ld_xcpt_uop_T_4]; // @[util.scala:363:52] wire xcpt_uop_xcpt_ae_if = use_mem_xcpt ? mem_xcpt_uop_xcpt_ae_if : _GEN_165[_ld_xcpt_uop_T_4]; // @[util.scala:363:52] wire xcpt_uop_xcpt_ma_if = use_mem_xcpt ? mem_xcpt_uop_xcpt_ma_if : _GEN_166[_ld_xcpt_uop_T_4]; // @[util.scala:363:52] wire xcpt_uop_bp_debug_if = use_mem_xcpt ? mem_xcpt_uop_bp_debug_if : _GEN_167[_ld_xcpt_uop_T_4]; // @[util.scala:363:52] wire xcpt_uop_bp_xcpt_if = use_mem_xcpt ? mem_xcpt_uop_bp_xcpt_if : _GEN_168[_ld_xcpt_uop_T_4]; // @[util.scala:363:52] wire [1:0] xcpt_uop_debug_fsrc = use_mem_xcpt ? mem_xcpt_uop_debug_fsrc : _GEN_169[_ld_xcpt_uop_T_4]; // @[util.scala:363:52] wire [1:0] xcpt_uop_debug_tsrc = use_mem_xcpt ? mem_xcpt_uop_debug_tsrc : _GEN_170[_ld_xcpt_uop_T_4]; // @[util.scala:363:52] wire _r_xcpt_valid_T = ld_xcpt_valid | mem_xcpt_valid; // @[lsu.scala:358:29, :1239:44, :1246:34] wire _r_xcpt_valid_T_1 = ~io_core_exception_0; // @[lsu.scala:201:7, :670:22, :1247:20] wire _r_xcpt_valid_T_2 = _r_xcpt_valid_T & _r_xcpt_valid_T_1; // @[lsu.scala:1246:{34,53}, :1247:20] wire [7:0] _r_xcpt_valid_T_3 = io_core_brupdate_b1_mispredict_mask_0 & xcpt_uop_br_mask; // @[util.scala:118:51] wire _r_xcpt_valid_T_4 = |_r_xcpt_valid_T_3; // @[util.scala:118:{51,59}] wire _r_xcpt_valid_T_5 = ~_r_xcpt_valid_T_4; // @[util.scala:118:59] wire _r_xcpt_valid_T_6 = _r_xcpt_valid_T_2 & _r_xcpt_valid_T_5; // @[lsu.scala:1246:53, :1247:39, :1248:20] wire [7:0] _r_xcpt_uop_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:85:27] wire [7:0] _r_xcpt_uop_br_mask_T_1 = xcpt_uop_br_mask & _r_xcpt_uop_br_mask_T; // @[util.scala:85:{25,27}] wire [4:0] _r_xcpt_cause_T = use_mem_xcpt ? {1'h0, mem_xcpt_cause} : 5'h10; // @[lsu.scala:359:29, :1242:115, :1251:28] wire _io_core_lxcpt_valid_T = ~io_core_exception_0; // @[lsu.scala:201:7, :670:22, :1254:42] wire _io_core_lxcpt_valid_T_1 = r_xcpt_valid & _io_core_lxcpt_valid_T; // @[lsu.scala:1236:29, :1254:{39,42}] wire [7:0] _io_core_lxcpt_valid_T_2 = io_core_brupdate_b1_mispredict_mask_0 & r_xcpt_uop_br_mask; // @[util.scala:118:51] wire _io_core_lxcpt_valid_T_3 = |_io_core_lxcpt_valid_T_2; // @[util.scala:118:{51,59}] wire _io_core_lxcpt_valid_T_4 = ~_io_core_lxcpt_valid_T_3; // @[util.scala:118:59] assign _io_core_lxcpt_valid_T_5 = _io_core_lxcpt_valid_T_1 & _io_core_lxcpt_valid_T_4; // @[lsu.scala:1254:{39,61,64}] assign io_core_lxcpt_valid_0 = _io_core_lxcpt_valid_T_5; // @[lsu.scala:201:7, :1254:61] wire _io_core_spec_ld_wakeup_0_valid_T_1 = ~mem_incoming_uop_0_fp_val; // @[lsu.scala:909:37, :1261:40] wire _io_core_spec_ld_wakeup_0_valid_T_2 = _io_core_spec_ld_wakeup_0_valid_T & _io_core_spec_ld_wakeup_0_valid_T_1; // @[lsu.scala:1259:69, :1260:69, :1261:40] wire _io_core_spec_ld_wakeup_0_valid_T_3 = |mem_incoming_uop_0_pdst; // @[lsu.scala:909:37, :1262:65] assign _io_core_spec_ld_wakeup_0_valid_T_4 = _io_core_spec_ld_wakeup_0_valid_T_2 & _io_core_spec_ld_wakeup_0_valid_T_3; // @[lsu.scala:1260:69, :1261:69, :1262:65] assign io_core_spec_ld_wakeup_0_valid_0 = _io_core_spec_ld_wakeup_0_valid_T_4; // @[lsu.scala:201:7, :1261:69] wire dmem_resp_fired_0; // @[lsu.scala:1282:33] wire _GEN_356 = io_dmem_nack_0_valid_0 & ~io_dmem_nack_0_bits_is_hella_0; // @[lsu.scala:201:7, :1290:7] wire _GEN_357 = _GEN_356 & io_dmem_nack_0_bits_uop_uses_ldq_0 & ~reset; // @[lsu.scala:201:7, :1290:7, :1294:7, :1295:15] wire _GEN_358 = io_dmem_nack_0_bits_uop_uses_ldq_0 & io_dmem_nack_0_bits_uop_ldq_idx_0 == 3'h0; // @[lsu.scala:201:7, :1175:30, :1294:7, :1296:62] wire _GEN_359 = io_dmem_nack_0_bits_uop_uses_ldq_0 & io_dmem_nack_0_bits_uop_ldq_idx_0 == 3'h1; // @[lsu.scala:201:7, :1175:30, :1294:7, :1296:62] wire _GEN_360 = io_dmem_nack_0_bits_uop_uses_ldq_0 & io_dmem_nack_0_bits_uop_ldq_idx_0 == 3'h2; // @[lsu.scala:201:7, :1175:30, :1294:7, :1296:62] wire _GEN_361 = io_dmem_nack_0_bits_uop_uses_ldq_0 & io_dmem_nack_0_bits_uop_ldq_idx_0 == 3'h3; // @[lsu.scala:201:7, :1175:30, :1294:7, :1296:62] wire _GEN_362 = io_dmem_nack_0_bits_uop_uses_ldq_0 & io_dmem_nack_0_bits_uop_ldq_idx_0 == 3'h4; // @[lsu.scala:201:7, :1175:30, :1294:7, :1296:62] wire _GEN_363 = io_dmem_nack_0_bits_uop_uses_ldq_0 & io_dmem_nack_0_bits_uop_ldq_idx_0 == 3'h5; // @[lsu.scala:201:7, :1175:30, :1294:7, :1296:62] wire _GEN_364 = io_dmem_nack_0_bits_uop_uses_ldq_0 & io_dmem_nack_0_bits_uop_ldq_idx_0 == 3'h6; // @[lsu.scala:201:7, :1175:30, :1294:7, :1296:62] wire _GEN_365 = io_dmem_nack_0_bits_uop_uses_ldq_0 & (&io_dmem_nack_0_bits_uop_ldq_idx_0); // @[lsu.scala:201:7, :1175:30, :1294:7, :1296:62] assign nacking_loads_0 = io_dmem_nack_0_valid_0 & ~io_dmem_nack_0_bits_is_hella_0 & _GEN_358; // @[lsu.scala:201:7, :1055:34, :1175:30, :1287:5, :1290:7, :1294:7, :1296:62] assign nacking_loads_1 = io_dmem_nack_0_valid_0 & ~io_dmem_nack_0_bits_is_hella_0 & _GEN_359; // @[lsu.scala:201:7, :1055:34, :1175:30, :1287:5, :1290:7, :1294:7, :1296:62] assign nacking_loads_2 = io_dmem_nack_0_valid_0 & ~io_dmem_nack_0_bits_is_hella_0 & _GEN_360; // @[lsu.scala:201:7, :1055:34, :1175:30, :1287:5, :1290:7, :1294:7, :1296:62] assign nacking_loads_3 = io_dmem_nack_0_valid_0 & ~io_dmem_nack_0_bits_is_hella_0 & _GEN_361; // @[lsu.scala:201:7, :1055:34, :1175:30, :1287:5, :1290:7, :1294:7, :1296:62] assign nacking_loads_4 = io_dmem_nack_0_valid_0 & ~io_dmem_nack_0_bits_is_hella_0 & _GEN_362; // @[lsu.scala:201:7, :1055:34, :1175:30, :1287:5, :1290:7, :1294:7, :1296:62] assign nacking_loads_5 = io_dmem_nack_0_valid_0 & ~io_dmem_nack_0_bits_is_hella_0 & _GEN_363; // @[lsu.scala:201:7, :1055:34, :1175:30, :1287:5, :1290:7, :1294:7, :1296:62] assign nacking_loads_6 = io_dmem_nack_0_valid_0 & ~io_dmem_nack_0_bits_is_hella_0 & _GEN_364; // @[lsu.scala:201:7, :1055:34, :1175:30, :1287:5, :1290:7, :1294:7, :1296:62] assign nacking_loads_7 = io_dmem_nack_0_valid_0 & ~io_dmem_nack_0_bits_is_hella_0 & _GEN_365; // @[lsu.scala:201:7, :1055:34, :1175:30, :1287:5, :1290:7, :1294:7, :1296:62] wire _GEN_366 = io_dmem_resp_0_valid_0 & io_dmem_resp_0_bits_uop_uses_ldq_0; // @[lsu.scala:201:7, :1311:7] wire send_iresp = _GEN_158[io_dmem_resp_0_bits_uop_ldq_idx_0] == 2'h0; // @[lsu.scala:201:7, :263:49, :1314:58] wire send_fresp = _GEN_158[io_dmem_resp_0_bits_uop_ldq_idx_0] == 2'h1; // @[lsu.scala:201:7, :263:49, :1314:58, :1315:58] wire _ldq_bits_succeeded_T = io_core_exe_0_iresp_valid_0 | io_core_exe_0_fresp_valid_0; // @[lsu.scala:201:7, :1327:72] assign dmem_resp_fired_0 = io_dmem_resp_0_valid_0 & (io_dmem_resp_0_bits_uop_uses_ldq_0 | io_dmem_resp_0_bits_uop_uses_stq_0 & io_dmem_resp_0_bits_uop_is_amo_0); // @[lsu.scala:201:7, :1282:33, :1309:5, :1311:7, :1325:28, :1331:7, :1334:48, :1335:30] wire _T_690 = dmem_resp_fired_0 & wb_forward_valid_0; // @[lsu.scala:1065:36, :1282:33, :1346:30] wire _T_692 = ~dmem_resp_fired_0 & wb_forward_valid_0; // @[lsu.scala:1065:36, :1282:33, :1350:{18,38}] wire [2:0] _forward_uop_T_1 = _forward_uop_T; wire [1:0] size_1 = _GEN_142[_forward_uop_T_1]; // @[AMOALU.scala:11:18] wire [7:0] _live_T = io_core_brupdate_b1_mispredict_mask_0 & _GEN_118[_forward_uop_T_1]; // @[util.scala:118:51] wire _live_T_1 = |_live_T; // @[util.scala:118:{51,59}] wire live = ~_live_T_1; // @[util.scala:118:59] wire [1:0] size; // @[AMOALU.scala:11:18] assign size = _GEN_52[wb_forward_stq_idx_0]; // @[AMOALU.scala:11:18, :12:8] wire _GEN_367 = _GEN_86[wb_forward_stq_idx_0]; // @[AMOALU.scala:12:8] wire [63:0] _GEN_368 = _GEN_87[wb_forward_stq_idx_0]; // @[AMOALU.scala:12:8] wire [3:0][63:0] _GEN_369 = {{_GEN_368}, {{2{_GEN_368[31:0]}}}, {{2{{2{_GEN_368[15:0]}}}}}, {{2{{2{{2{_GEN_368[7:0]}}}}}}}}; // @[AMOALU.scala:12:8, :29:{13,19,32,69}] wire _io_core_exe_0_iresp_valid_T = _GEN_158[_forward_uop_T_1] == 2'h0; // @[util.scala:118:51] wire _io_core_exe_0_iresp_valid_T_1 = _io_core_exe_0_iresp_valid_T & _GEN_367; // @[AMOALU.scala:12:8] wire _io_core_exe_0_iresp_valid_T_2 = _io_core_exe_0_iresp_valid_T_1 & live; // @[lsu.scala:1356:25, :1365:{72,86}] wire _GEN_370 = _T_690 | ~_T_692; // @[lsu.scala:1309:5, :1346:30, :1347:5, :1350:38, :1351:5] assign io_core_exe_0_iresp_valid_0 = _GEN_370 ? io_dmem_resp_0_valid_0 & (io_dmem_resp_0_bits_uop_uses_ldq_0 ? send_iresp : io_dmem_resp_0_bits_uop_uses_stq_0 & io_dmem_resp_0_bits_uop_is_amo_0) : _io_core_exe_0_iresp_valid_T_2; // @[lsu.scala:201:7, :1276:32, :1309:5, :1311:7, :1314:58, :1319:40, :1331:7, :1334:48, :1347:5, :1351:5, :1365:86] wire _io_core_exe_0_fresp_valid_T = _GEN_158[_forward_uop_T_1] == 2'h1; // @[util.scala:118:51] wire _io_core_exe_0_fresp_valid_T_1 = _io_core_exe_0_fresp_valid_T & _GEN_367; // @[AMOALU.scala:12:8] wire _io_core_exe_0_fresp_valid_T_2 = _io_core_exe_0_fresp_valid_T_1 & live; // @[lsu.scala:1356:25, :1366:{72,86}] assign io_core_exe_0_fresp_valid_0 = _GEN_370 ? _GEN_366 & send_fresp : _io_core_exe_0_fresp_valid_T_2; // @[lsu.scala:201:7, :1278:32, :1309:5, :1311:7, :1315:58, :1321:40, :1347:5, :1351:5, :1366:86] assign io_core_exe_0_iresp_bits_uop_uopc_0 = _GEN_370 ? (io_dmem_resp_0_bits_uop_uses_ldq_0 ? _GEN_94[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_1[io_dmem_resp_0_bits_uop_stq_idx_0]) : _GEN_94[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_iresp_bits_uop_inst_0 = _GEN_370 ? (io_dmem_resp_0_bits_uop_uses_ldq_0 ? _GEN_95[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_2[io_dmem_resp_0_bits_uop_stq_idx_0]) : _GEN_95[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_iresp_bits_uop_debug_inst_0 = _GEN_370 ? (io_dmem_resp_0_bits_uop_uses_ldq_0 ? _GEN_96[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_3[io_dmem_resp_0_bits_uop_stq_idx_0]) : _GEN_96[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_iresp_bits_uop_is_rvc_0 = _GEN_370 ? (io_dmem_resp_0_bits_uop_uses_ldq_0 ? _GEN_97[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_4[io_dmem_resp_0_bits_uop_stq_idx_0]) : _GEN_97[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_iresp_bits_uop_debug_pc_0 = _GEN_370 ? (io_dmem_resp_0_bits_uop_uses_ldq_0 ? _GEN_98[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_5[io_dmem_resp_0_bits_uop_stq_idx_0]) : _GEN_98[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_iresp_bits_uop_iq_type_0 = _GEN_370 ? (io_dmem_resp_0_bits_uop_uses_ldq_0 ? _GEN_99[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_6[io_dmem_resp_0_bits_uop_stq_idx_0]) : _GEN_99[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_iresp_bits_uop_fu_code_0 = _GEN_370 ? (io_dmem_resp_0_bits_uop_uses_ldq_0 ? _GEN_100[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_7[io_dmem_resp_0_bits_uop_stq_idx_0]) : _GEN_100[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_iresp_bits_uop_ctrl_br_type_0 = _GEN_370 ? (io_dmem_resp_0_bits_uop_uses_ldq_0 ? _GEN_101[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_8[io_dmem_resp_0_bits_uop_stq_idx_0]) : _GEN_101[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_iresp_bits_uop_ctrl_op1_sel_0 = _GEN_370 ? (io_dmem_resp_0_bits_uop_uses_ldq_0 ? _GEN_102[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_9[io_dmem_resp_0_bits_uop_stq_idx_0]) : _GEN_102[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_iresp_bits_uop_ctrl_op2_sel_0 = _GEN_370 ? (io_dmem_resp_0_bits_uop_uses_ldq_0 ? _GEN_103[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_10[io_dmem_resp_0_bits_uop_stq_idx_0]) : _GEN_103[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_iresp_bits_uop_ctrl_imm_sel_0 = _GEN_370 ? (io_dmem_resp_0_bits_uop_uses_ldq_0 ? _GEN_104[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_11[io_dmem_resp_0_bits_uop_stq_idx_0]) : _GEN_104[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_iresp_bits_uop_ctrl_op_fcn_0 = _GEN_370 ? (io_dmem_resp_0_bits_uop_uses_ldq_0 ? _GEN_105[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_12[io_dmem_resp_0_bits_uop_stq_idx_0]) : _GEN_105[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_iresp_bits_uop_ctrl_fcn_dw_0 = _GEN_370 ? (io_dmem_resp_0_bits_uop_uses_ldq_0 ? _GEN_106[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_13[io_dmem_resp_0_bits_uop_stq_idx_0]) : _GEN_106[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_iresp_bits_uop_ctrl_csr_cmd_0 = _GEN_370 ? (io_dmem_resp_0_bits_uop_uses_ldq_0 ? _GEN_107[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_14[io_dmem_resp_0_bits_uop_stq_idx_0]) : _GEN_107[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_iresp_bits_uop_ctrl_is_load_0 = _GEN_370 ? (io_dmem_resp_0_bits_uop_uses_ldq_0 ? _GEN_108[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_15[io_dmem_resp_0_bits_uop_stq_idx_0]) : _GEN_108[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_iresp_bits_uop_ctrl_is_sta_0 = _GEN_370 ? (io_dmem_resp_0_bits_uop_uses_ldq_0 ? _GEN_109[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_16[io_dmem_resp_0_bits_uop_stq_idx_0]) : _GEN_109[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_iresp_bits_uop_ctrl_is_std_0 = _GEN_370 ? (io_dmem_resp_0_bits_uop_uses_ldq_0 ? _GEN_110[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_17[io_dmem_resp_0_bits_uop_stq_idx_0]) : _GEN_110[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_iresp_bits_uop_iw_state_0 = _GEN_370 ? (io_dmem_resp_0_bits_uop_uses_ldq_0 ? _GEN_111[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_18[io_dmem_resp_0_bits_uop_stq_idx_0]) : _GEN_111[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_iresp_bits_uop_iw_p1_poisoned_0 = _GEN_370 ? (io_dmem_resp_0_bits_uop_uses_ldq_0 ? _GEN_112[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_19[io_dmem_resp_0_bits_uop_stq_idx_0]) : _GEN_112[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_iresp_bits_uop_iw_p2_poisoned_0 = _GEN_370 ? (io_dmem_resp_0_bits_uop_uses_ldq_0 ? _GEN_113[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_20[io_dmem_resp_0_bits_uop_stq_idx_0]) : _GEN_113[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_iresp_bits_uop_is_br_0 = _GEN_370 ? (io_dmem_resp_0_bits_uop_uses_ldq_0 ? _GEN_114[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_21[io_dmem_resp_0_bits_uop_stq_idx_0]) : _GEN_114[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_iresp_bits_uop_is_jalr_0 = _GEN_370 ? (io_dmem_resp_0_bits_uop_uses_ldq_0 ? _GEN_115[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_22[io_dmem_resp_0_bits_uop_stq_idx_0]) : _GEN_115[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_iresp_bits_uop_is_jal_0 = _GEN_370 ? (io_dmem_resp_0_bits_uop_uses_ldq_0 ? _GEN_116[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_23[io_dmem_resp_0_bits_uop_stq_idx_0]) : _GEN_116[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_iresp_bits_uop_is_sfb_0 = _GEN_370 ? (io_dmem_resp_0_bits_uop_uses_ldq_0 ? _GEN_117[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_24[io_dmem_resp_0_bits_uop_stq_idx_0]) : _GEN_117[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_iresp_bits_uop_br_mask_0 = _GEN_370 ? (io_dmem_resp_0_bits_uop_uses_ldq_0 ? _GEN_118[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_25[io_dmem_resp_0_bits_uop_stq_idx_0]) : _GEN_118[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_iresp_bits_uop_br_tag_0 = _GEN_370 ? (io_dmem_resp_0_bits_uop_uses_ldq_0 ? _GEN_119[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_26[io_dmem_resp_0_bits_uop_stq_idx_0]) : _GEN_119[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_iresp_bits_uop_ftq_idx_0 = _GEN_370 ? (io_dmem_resp_0_bits_uop_uses_ldq_0 ? _GEN_120[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_27[io_dmem_resp_0_bits_uop_stq_idx_0]) : _GEN_120[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_iresp_bits_uop_edge_inst_0 = _GEN_370 ? (io_dmem_resp_0_bits_uop_uses_ldq_0 ? _GEN_121[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_28[io_dmem_resp_0_bits_uop_stq_idx_0]) : _GEN_121[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_iresp_bits_uop_pc_lob_0 = _GEN_370 ? (io_dmem_resp_0_bits_uop_uses_ldq_0 ? _GEN_122[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_29[io_dmem_resp_0_bits_uop_stq_idx_0]) : _GEN_122[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_iresp_bits_uop_taken_0 = _GEN_370 ? (io_dmem_resp_0_bits_uop_uses_ldq_0 ? _GEN_123[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_30[io_dmem_resp_0_bits_uop_stq_idx_0]) : _GEN_123[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_iresp_bits_uop_imm_packed_0 = _GEN_370 ? (io_dmem_resp_0_bits_uop_uses_ldq_0 ? _GEN_124[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_31[io_dmem_resp_0_bits_uop_stq_idx_0]) : _GEN_124[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_iresp_bits_uop_csr_addr_0 = _GEN_370 ? (io_dmem_resp_0_bits_uop_uses_ldq_0 ? _GEN_125[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_32[io_dmem_resp_0_bits_uop_stq_idx_0]) : _GEN_125[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_iresp_bits_uop_rob_idx_0 = _GEN_370 ? (io_dmem_resp_0_bits_uop_uses_ldq_0 ? _GEN_126[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_33[io_dmem_resp_0_bits_uop_stq_idx_0]) : _GEN_126[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_iresp_bits_uop_ldq_idx_0 = _GEN_370 ? (io_dmem_resp_0_bits_uop_uses_ldq_0 ? _GEN_127[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_34[io_dmem_resp_0_bits_uop_stq_idx_0]) : _GEN_127[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_iresp_bits_uop_stq_idx_0 = _GEN_370 ? (io_dmem_resp_0_bits_uop_uses_ldq_0 ? _GEN_128[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_35[io_dmem_resp_0_bits_uop_stq_idx_0]) : _GEN_128[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_iresp_bits_uop_rxq_idx_0 = _GEN_370 ? (io_dmem_resp_0_bits_uop_uses_ldq_0 ? _GEN_129[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_36[io_dmem_resp_0_bits_uop_stq_idx_0]) : _GEN_129[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_iresp_bits_uop_pdst_0 = _GEN_370 ? (io_dmem_resp_0_bits_uop_uses_ldq_0 ? _GEN_130[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_37[io_dmem_resp_0_bits_uop_stq_idx_0]) : _GEN_130[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_iresp_bits_uop_prs1_0 = _GEN_370 ? (io_dmem_resp_0_bits_uop_uses_ldq_0 ? _GEN_131[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_38[io_dmem_resp_0_bits_uop_stq_idx_0]) : _GEN_131[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_iresp_bits_uop_prs2_0 = _GEN_370 ? (io_dmem_resp_0_bits_uop_uses_ldq_0 ? _GEN_132[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_39[io_dmem_resp_0_bits_uop_stq_idx_0]) : _GEN_132[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_iresp_bits_uop_prs3_0 = _GEN_370 ? (io_dmem_resp_0_bits_uop_uses_ldq_0 ? _GEN_133[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_40[io_dmem_resp_0_bits_uop_stq_idx_0]) : _GEN_133[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_iresp_bits_uop_ppred_0 = ~_GEN_370 | io_dmem_resp_0_bits_uop_uses_ldq_0 ? 4'h0 : _GEN_41[io_dmem_resp_0_bits_uop_stq_idx_0]; // @[lsu.scala:201:7, :222:42, :1309:5, :1333:62, :1347:5, :1351:5] assign io_core_exe_0_iresp_bits_uop_prs1_busy_0 = _GEN_370 ? (io_dmem_resp_0_bits_uop_uses_ldq_0 ? _GEN_134[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_42[io_dmem_resp_0_bits_uop_stq_idx_0]) : _GEN_134[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_iresp_bits_uop_prs2_busy_0 = _GEN_370 ? (io_dmem_resp_0_bits_uop_uses_ldq_0 ? _GEN_135[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_43[io_dmem_resp_0_bits_uop_stq_idx_0]) : _GEN_135[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_iresp_bits_uop_prs3_busy_0 = _GEN_370 ? (io_dmem_resp_0_bits_uop_uses_ldq_0 ? _GEN_136[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_44[io_dmem_resp_0_bits_uop_stq_idx_0]) : _GEN_136[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_iresp_bits_uop_ppred_busy_0 = _GEN_370 & ~io_dmem_resp_0_bits_uop_uses_ldq_0 & _GEN_45[io_dmem_resp_0_bits_uop_stq_idx_0]; // @[lsu.scala:201:7, :222:42, :767:39, :1309:5, :1311:7, :1317:40, :1331:7, :1333:62, :1347:5, :1351:5] assign io_core_exe_0_iresp_bits_uop_stale_pdst_0 = _GEN_370 ? (io_dmem_resp_0_bits_uop_uses_ldq_0 ? _GEN_137[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_46[io_dmem_resp_0_bits_uop_stq_idx_0]) : _GEN_137[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_iresp_bits_uop_exception_0 = _GEN_370 ? (io_dmem_resp_0_bits_uop_uses_ldq_0 ? _GEN_138[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_47[io_dmem_resp_0_bits_uop_stq_idx_0]) : _GEN_138[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_iresp_bits_uop_exc_cause_0 = _GEN_370 ? (io_dmem_resp_0_bits_uop_uses_ldq_0 ? _GEN_139[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_49[io_dmem_resp_0_bits_uop_stq_idx_0]) : _GEN_139[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_iresp_bits_uop_bypassable_0 = _GEN_370 ? (io_dmem_resp_0_bits_uop_uses_ldq_0 ? _GEN_140[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_50[io_dmem_resp_0_bits_uop_stq_idx_0]) : _GEN_140[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_iresp_bits_uop_mem_cmd_0 = _GEN_370 ? (io_dmem_resp_0_bits_uop_uses_ldq_0 ? _GEN_141[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_51[io_dmem_resp_0_bits_uop_stq_idx_0]) : _GEN_141[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_iresp_bits_uop_mem_size_0 = _GEN_370 ? (io_dmem_resp_0_bits_uop_uses_ldq_0 ? _GEN_142[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_52[io_dmem_resp_0_bits_uop_stq_idx_0]) : size_1; // @[AMOALU.scala:11:18] assign io_core_exe_0_iresp_bits_uop_mem_signed_0 = _GEN_370 ? (io_dmem_resp_0_bits_uop_uses_ldq_0 ? _GEN_143[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_53[io_dmem_resp_0_bits_uop_stq_idx_0]) : _GEN_143[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_iresp_bits_uop_is_fence_0 = _GEN_370 ? (io_dmem_resp_0_bits_uop_uses_ldq_0 ? _GEN_144[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_54[io_dmem_resp_0_bits_uop_stq_idx_0]) : _GEN_144[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_iresp_bits_uop_is_fencei_0 = _GEN_370 ? (io_dmem_resp_0_bits_uop_uses_ldq_0 ? _GEN_145[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_56[io_dmem_resp_0_bits_uop_stq_idx_0]) : _GEN_145[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_iresp_bits_uop_is_amo_0 = _GEN_370 ? (io_dmem_resp_0_bits_uop_uses_ldq_0 ? _GEN_146[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_57[io_dmem_resp_0_bits_uop_stq_idx_0]) : _GEN_146[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_iresp_bits_uop_uses_ldq_0 = _GEN_370 ? (io_dmem_resp_0_bits_uop_uses_ldq_0 ? _GEN_147[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_59[io_dmem_resp_0_bits_uop_stq_idx_0]) : _GEN_147[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_iresp_bits_uop_uses_stq_0 = _GEN_370 ? (io_dmem_resp_0_bits_uop_uses_ldq_0 ? _GEN_148[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_60[io_dmem_resp_0_bits_uop_stq_idx_0]) : _GEN_148[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_iresp_bits_uop_is_sys_pc2epc_0 = _GEN_370 ? (io_dmem_resp_0_bits_uop_uses_ldq_0 ? _GEN_149[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_61[io_dmem_resp_0_bits_uop_stq_idx_0]) : _GEN_149[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_iresp_bits_uop_is_unique_0 = _GEN_370 ? (io_dmem_resp_0_bits_uop_uses_ldq_0 ? _GEN_150[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_62[io_dmem_resp_0_bits_uop_stq_idx_0]) : _GEN_150[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_iresp_bits_uop_flush_on_commit_0 = _GEN_370 ? (io_dmem_resp_0_bits_uop_uses_ldq_0 ? _GEN_151[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_63[io_dmem_resp_0_bits_uop_stq_idx_0]) : _GEN_151[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_iresp_bits_uop_ldst_is_rs1_0 = _GEN_370 ? (io_dmem_resp_0_bits_uop_uses_ldq_0 ? _GEN_152[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_64[io_dmem_resp_0_bits_uop_stq_idx_0]) : _GEN_152[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_iresp_bits_uop_ldst_0 = _GEN_370 ? (io_dmem_resp_0_bits_uop_uses_ldq_0 ? _GEN_153[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_65[io_dmem_resp_0_bits_uop_stq_idx_0]) : _GEN_153[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_iresp_bits_uop_lrs1_0 = _GEN_370 ? (io_dmem_resp_0_bits_uop_uses_ldq_0 ? _GEN_154[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_66[io_dmem_resp_0_bits_uop_stq_idx_0]) : _GEN_154[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_iresp_bits_uop_lrs2_0 = _GEN_370 ? (io_dmem_resp_0_bits_uop_uses_ldq_0 ? _GEN_155[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_67[io_dmem_resp_0_bits_uop_stq_idx_0]) : _GEN_155[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_iresp_bits_uop_lrs3_0 = _GEN_370 ? (io_dmem_resp_0_bits_uop_uses_ldq_0 ? _GEN_156[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_68[io_dmem_resp_0_bits_uop_stq_idx_0]) : _GEN_156[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_iresp_bits_uop_ldst_val_0 = _GEN_370 ? (io_dmem_resp_0_bits_uop_uses_ldq_0 ? _GEN_157[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_69[io_dmem_resp_0_bits_uop_stq_idx_0]) : _GEN_157[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_iresp_bits_uop_dst_rtype_0 = _GEN_370 ? (io_dmem_resp_0_bits_uop_uses_ldq_0 ? _GEN_158[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_70[io_dmem_resp_0_bits_uop_stq_idx_0]) : _GEN_158[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_iresp_bits_uop_lrs1_rtype_0 = _GEN_370 ? (io_dmem_resp_0_bits_uop_uses_ldq_0 ? _GEN_159[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_71[io_dmem_resp_0_bits_uop_stq_idx_0]) : _GEN_159[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_iresp_bits_uop_lrs2_rtype_0 = _GEN_370 ? (io_dmem_resp_0_bits_uop_uses_ldq_0 ? _GEN_160[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_72[io_dmem_resp_0_bits_uop_stq_idx_0]) : _GEN_160[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_iresp_bits_uop_frs3_en_0 = _GEN_370 ? (io_dmem_resp_0_bits_uop_uses_ldq_0 ? _GEN_161[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_73[io_dmem_resp_0_bits_uop_stq_idx_0]) : _GEN_161[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_iresp_bits_uop_fp_val_0 = _GEN_370 ? (io_dmem_resp_0_bits_uop_uses_ldq_0 ? _GEN_162[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_74[io_dmem_resp_0_bits_uop_stq_idx_0]) : _GEN_162[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_iresp_bits_uop_fp_single_0 = _GEN_370 ? (io_dmem_resp_0_bits_uop_uses_ldq_0 ? _GEN_163[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_75[io_dmem_resp_0_bits_uop_stq_idx_0]) : _GEN_163[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_iresp_bits_uop_xcpt_pf_if_0 = _GEN_370 ? (io_dmem_resp_0_bits_uop_uses_ldq_0 ? _GEN_164[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_76[io_dmem_resp_0_bits_uop_stq_idx_0]) : _GEN_164[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_iresp_bits_uop_xcpt_ae_if_0 = _GEN_370 ? (io_dmem_resp_0_bits_uop_uses_ldq_0 ? _GEN_165[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_77[io_dmem_resp_0_bits_uop_stq_idx_0]) : _GEN_165[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_iresp_bits_uop_xcpt_ma_if_0 = _GEN_370 ? (io_dmem_resp_0_bits_uop_uses_ldq_0 ? _GEN_166[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_78[io_dmem_resp_0_bits_uop_stq_idx_0]) : _GEN_166[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_iresp_bits_uop_bp_debug_if_0 = _GEN_370 ? (io_dmem_resp_0_bits_uop_uses_ldq_0 ? _GEN_167[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_79[io_dmem_resp_0_bits_uop_stq_idx_0]) : _GEN_167[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_iresp_bits_uop_bp_xcpt_if_0 = _GEN_370 ? (io_dmem_resp_0_bits_uop_uses_ldq_0 ? _GEN_168[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_80[io_dmem_resp_0_bits_uop_stq_idx_0]) : _GEN_168[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_iresp_bits_uop_debug_fsrc_0 = _GEN_370 ? (io_dmem_resp_0_bits_uop_uses_ldq_0 ? _GEN_169[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_81[io_dmem_resp_0_bits_uop_stq_idx_0]) : _GEN_169[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_iresp_bits_uop_debug_tsrc_0 = _GEN_370 ? (io_dmem_resp_0_bits_uop_uses_ldq_0 ? _GEN_170[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_82[io_dmem_resp_0_bits_uop_stq_idx_0]) : _GEN_170[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_fresp_bits_uop_uopc_0 = _GEN_370 ? _GEN_94[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_94[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_fresp_bits_uop_inst_0 = _GEN_370 ? _GEN_95[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_95[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_fresp_bits_uop_debug_inst_0 = _GEN_370 ? _GEN_96[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_96[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_fresp_bits_uop_is_rvc_0 = _GEN_370 ? _GEN_97[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_97[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_fresp_bits_uop_debug_pc_0 = _GEN_370 ? _GEN_98[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_98[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_fresp_bits_uop_iq_type_0 = _GEN_370 ? _GEN_99[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_99[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_fresp_bits_uop_fu_code_0 = _GEN_370 ? _GEN_100[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_100[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_fresp_bits_uop_ctrl_br_type_0 = _GEN_370 ? _GEN_101[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_101[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_fresp_bits_uop_ctrl_op1_sel_0 = _GEN_370 ? _GEN_102[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_102[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_fresp_bits_uop_ctrl_op2_sel_0 = _GEN_370 ? _GEN_103[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_103[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_fresp_bits_uop_ctrl_imm_sel_0 = _GEN_370 ? _GEN_104[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_104[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_fresp_bits_uop_ctrl_op_fcn_0 = _GEN_370 ? _GEN_105[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_105[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_fresp_bits_uop_ctrl_fcn_dw_0 = _GEN_370 ? _GEN_106[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_106[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_fresp_bits_uop_ctrl_csr_cmd_0 = _GEN_370 ? _GEN_107[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_107[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_fresp_bits_uop_ctrl_is_load_0 = _GEN_370 ? _GEN_108[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_108[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_fresp_bits_uop_ctrl_is_sta_0 = _GEN_370 ? _GEN_109[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_109[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_fresp_bits_uop_ctrl_is_std_0 = _GEN_370 ? _GEN_110[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_110[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_fresp_bits_uop_iw_state_0 = _GEN_370 ? _GEN_111[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_111[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_fresp_bits_uop_iw_p1_poisoned_0 = _GEN_370 ? _GEN_112[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_112[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_fresp_bits_uop_iw_p2_poisoned_0 = _GEN_370 ? _GEN_113[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_113[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_fresp_bits_uop_is_br_0 = _GEN_370 ? _GEN_114[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_114[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_fresp_bits_uop_is_jalr_0 = _GEN_370 ? _GEN_115[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_115[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_fresp_bits_uop_is_jal_0 = _GEN_370 ? _GEN_116[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_116[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_fresp_bits_uop_is_sfb_0 = _GEN_370 ? _GEN_117[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_117[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_fresp_bits_uop_br_mask_0 = _GEN_370 ? _GEN_118[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_118[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_fresp_bits_uop_br_tag_0 = _GEN_370 ? _GEN_119[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_119[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_fresp_bits_uop_ftq_idx_0 = _GEN_370 ? _GEN_120[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_120[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_fresp_bits_uop_edge_inst_0 = _GEN_370 ? _GEN_121[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_121[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_fresp_bits_uop_pc_lob_0 = _GEN_370 ? _GEN_122[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_122[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_fresp_bits_uop_taken_0 = _GEN_370 ? _GEN_123[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_123[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_fresp_bits_uop_imm_packed_0 = _GEN_370 ? _GEN_124[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_124[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_fresp_bits_uop_csr_addr_0 = _GEN_370 ? _GEN_125[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_125[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_fresp_bits_uop_rob_idx_0 = _GEN_370 ? _GEN_126[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_126[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_fresp_bits_uop_ldq_idx_0 = _GEN_370 ? _GEN_127[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_127[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_fresp_bits_uop_stq_idx_0 = _GEN_370 ? _GEN_128[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_128[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_fresp_bits_uop_rxq_idx_0 = _GEN_370 ? _GEN_129[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_129[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_fresp_bits_uop_pdst_0 = _GEN_370 ? _GEN_130[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_130[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_fresp_bits_uop_prs1_0 = _GEN_370 ? _GEN_131[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_131[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_fresp_bits_uop_prs2_0 = _GEN_370 ? _GEN_132[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_132[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_fresp_bits_uop_prs3_0 = _GEN_370 ? _GEN_133[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_133[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_fresp_bits_uop_prs1_busy_0 = _GEN_370 ? _GEN_134[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_134[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_fresp_bits_uop_prs2_busy_0 = _GEN_370 ? _GEN_135[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_135[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_fresp_bits_uop_prs3_busy_0 = _GEN_370 ? _GEN_136[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_136[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_fresp_bits_uop_stale_pdst_0 = _GEN_370 ? _GEN_137[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_137[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_fresp_bits_uop_exception_0 = _GEN_370 ? _GEN_138[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_138[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_fresp_bits_uop_exc_cause_0 = _GEN_370 ? _GEN_139[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_139[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_fresp_bits_uop_bypassable_0 = _GEN_370 ? _GEN_140[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_140[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_fresp_bits_uop_mem_cmd_0 = _GEN_370 ? _GEN_141[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_141[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_fresp_bits_uop_mem_size_0 = _GEN_370 ? _GEN_142[io_dmem_resp_0_bits_uop_ldq_idx_0] : size_1; // @[AMOALU.scala:11:18] assign io_core_exe_0_fresp_bits_uop_mem_signed_0 = _GEN_370 ? _GEN_143[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_143[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_fresp_bits_uop_is_fence_0 = _GEN_370 ? _GEN_144[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_144[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_fresp_bits_uop_is_fencei_0 = _GEN_370 ? _GEN_145[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_145[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_fresp_bits_uop_is_amo_0 = _GEN_370 ? _GEN_146[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_146[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_fresp_bits_uop_uses_ldq_0 = _GEN_370 ? _GEN_147[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_147[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_fresp_bits_uop_uses_stq_0 = _GEN_370 ? _GEN_148[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_148[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_fresp_bits_uop_is_sys_pc2epc_0 = _GEN_370 ? _GEN_149[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_149[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_fresp_bits_uop_is_unique_0 = _GEN_370 ? _GEN_150[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_150[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_fresp_bits_uop_flush_on_commit_0 = _GEN_370 ? _GEN_151[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_151[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_fresp_bits_uop_ldst_is_rs1_0 = _GEN_370 ? _GEN_152[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_152[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_fresp_bits_uop_ldst_0 = _GEN_370 ? _GEN_153[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_153[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_fresp_bits_uop_lrs1_0 = _GEN_370 ? _GEN_154[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_154[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_fresp_bits_uop_lrs2_0 = _GEN_370 ? _GEN_155[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_155[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_fresp_bits_uop_lrs3_0 = _GEN_370 ? _GEN_156[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_156[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_fresp_bits_uop_ldst_val_0 = _GEN_370 ? _GEN_157[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_157[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_fresp_bits_uop_dst_rtype_0 = _GEN_370 ? _GEN_158[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_158[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_fresp_bits_uop_lrs1_rtype_0 = _GEN_370 ? _GEN_159[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_159[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_fresp_bits_uop_lrs2_rtype_0 = _GEN_370 ? _GEN_160[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_160[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_fresp_bits_uop_frs3_en_0 = _GEN_370 ? _GEN_161[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_161[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_fresp_bits_uop_fp_val_0 = _GEN_370 ? _GEN_162[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_162[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_fresp_bits_uop_fp_single_0 = _GEN_370 ? _GEN_163[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_163[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_fresp_bits_uop_xcpt_pf_if_0 = _GEN_370 ? _GEN_164[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_164[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_fresp_bits_uop_xcpt_ae_if_0 = _GEN_370 ? _GEN_165[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_165[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_fresp_bits_uop_xcpt_ma_if_0 = _GEN_370 ? _GEN_166[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_166[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_fresp_bits_uop_bp_debug_if_0 = _GEN_370 ? _GEN_167[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_167[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_fresp_bits_uop_bp_xcpt_if_0 = _GEN_370 ? _GEN_168[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_168[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_fresp_bits_uop_debug_fsrc_0 = _GEN_370 ? _GEN_169[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_169[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_fresp_bits_uop_debug_tsrc_0 = _GEN_370 ? _GEN_170[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_170[_forward_uop_T_1]; // @[util.scala:118:51] wire _io_core_exe_0_iresp_bits_data_shifted_T = wb_forward_ld_addr_0[2]; // @[AMOALU.scala:42:29] wire _io_core_exe_0_fresp_bits_data_shifted_T = wb_forward_ld_addr_0[2]; // @[AMOALU.scala:42:29] wire _ldq_bits_debug_wb_data_shifted_T = wb_forward_ld_addr_0[2]; // @[AMOALU.scala:42:29] wire [31:0] _io_core_exe_0_iresp_bits_data_shifted_T_1 = _GEN_369[size][63:32]; // @[AMOALU.scala:11:18, :29:{13,19}, :42:37] wire [31:0] _io_core_exe_0_iresp_bits_data_T_5 = _GEN_369[size][63:32]; // @[AMOALU.scala:11:18, :29:{13,19}, :42:37, :45:94] wire [31:0] _io_core_exe_0_fresp_bits_data_shifted_T_1 = _GEN_369[size][63:32]; // @[AMOALU.scala:11:18, :29:{13,19}, :42:37] wire [31:0] _io_core_exe_0_fresp_bits_data_T_5 = _GEN_369[size][63:32]; // @[AMOALU.scala:11:18, :29:{13,19}, :42:37, :45:94] wire [31:0] _ldq_bits_debug_wb_data_shifted_T_1 = _GEN_369[size][63:32]; // @[AMOALU.scala:11:18, :29:{13,19}, :42:37] wire [31:0] _ldq_bits_debug_wb_data_T_5 = _GEN_369[size][63:32]; // @[AMOALU.scala:11:18, :29:{13,19}, :42:37, :45:94] wire [31:0] _io_core_exe_0_iresp_bits_data_shifted_T_2 = _GEN_369[size][31:0]; // @[AMOALU.scala:11:18, :29:{13,19}, :42:55] wire [31:0] _io_core_exe_0_fresp_bits_data_shifted_T_2 = _GEN_369[size][31:0]; // @[AMOALU.scala:11:18, :29:{13,19}, :42:55] wire [31:0] _ldq_bits_debug_wb_data_shifted_T_2 = _GEN_369[size][31:0]; // @[AMOALU.scala:11:18, :29:{13,19}, :42:55] wire [31:0] io_core_exe_0_iresp_bits_data_shifted = _io_core_exe_0_iresp_bits_data_shifted_T ? _io_core_exe_0_iresp_bits_data_shifted_T_1 : _io_core_exe_0_iresp_bits_data_shifted_T_2; // @[AMOALU.scala:42:{24,29,37,55}] wire [31:0] io_core_exe_0_iresp_bits_data_zeroed = io_core_exe_0_iresp_bits_data_shifted; // @[AMOALU.scala:42:24, :44:23] wire _GEN_371 = size_1 == 2'h2; // @[AMOALU.scala:11:18, :45:26] wire _io_core_exe_0_iresp_bits_data_T; // @[AMOALU.scala:45:26] assign _io_core_exe_0_iresp_bits_data_T = _GEN_371; // @[AMOALU.scala:45:26] wire _io_core_exe_0_fresp_bits_data_T; // @[AMOALU.scala:45:26] assign _io_core_exe_0_fresp_bits_data_T = _GEN_371; // @[AMOALU.scala:45:26] wire _ldq_bits_debug_wb_data_T; // @[AMOALU.scala:45:26] assign _ldq_bits_debug_wb_data_T = _GEN_371; // @[AMOALU.scala:45:26] wire _io_core_exe_0_iresp_bits_data_T_1 = _io_core_exe_0_iresp_bits_data_T; // @[AMOALU.scala:45:{26,34}] wire _io_core_exe_0_iresp_bits_data_T_2 = io_core_exe_0_iresp_bits_data_zeroed[31]; // @[AMOALU.scala:44:23, :45:81] wire _io_core_exe_0_iresp_bits_data_T_3 = _GEN_143[_forward_uop_T_1] & _io_core_exe_0_iresp_bits_data_T_2; // @[AMOALU.scala:45:{72,81}] wire [31:0] _io_core_exe_0_iresp_bits_data_T_4 = {32{_io_core_exe_0_iresp_bits_data_T_3}}; // @[AMOALU.scala:45:{49,72}] wire [31:0] _io_core_exe_0_iresp_bits_data_T_6 = _io_core_exe_0_iresp_bits_data_T_1 ? _io_core_exe_0_iresp_bits_data_T_4 : _io_core_exe_0_iresp_bits_data_T_5; // @[AMOALU.scala:45:{20,34,49,94}] wire [63:0] _io_core_exe_0_iresp_bits_data_T_7 = {_io_core_exe_0_iresp_bits_data_T_6, io_core_exe_0_iresp_bits_data_zeroed}; // @[AMOALU.scala:44:23, :45:{16,20}] wire _io_core_exe_0_iresp_bits_data_shifted_T_3 = wb_forward_ld_addr_0[1]; // @[AMOALU.scala:42:29] wire _io_core_exe_0_fresp_bits_data_shifted_T_3 = wb_forward_ld_addr_0[1]; // @[AMOALU.scala:42:29] wire _ldq_bits_debug_wb_data_shifted_T_3 = wb_forward_ld_addr_0[1]; // @[AMOALU.scala:42:29] wire [15:0] _io_core_exe_0_iresp_bits_data_shifted_T_4 = _io_core_exe_0_iresp_bits_data_T_7[31:16]; // @[AMOALU.scala:42:37, :45:16] wire [15:0] _io_core_exe_0_iresp_bits_data_shifted_T_5 = _io_core_exe_0_iresp_bits_data_T_7[15:0]; // @[AMOALU.scala:42:55, :45:16] wire [15:0] io_core_exe_0_iresp_bits_data_shifted_1 = _io_core_exe_0_iresp_bits_data_shifted_T_3 ? _io_core_exe_0_iresp_bits_data_shifted_T_4 : _io_core_exe_0_iresp_bits_data_shifted_T_5; // @[AMOALU.scala:42:{24,29,37,55}] wire [15:0] io_core_exe_0_iresp_bits_data_zeroed_1 = io_core_exe_0_iresp_bits_data_shifted_1; // @[AMOALU.scala:42:24, :44:23] wire _GEN_372 = size_1 == 2'h1; // @[AMOALU.scala:11:18, :45:26] wire _io_core_exe_0_iresp_bits_data_T_8; // @[AMOALU.scala:45:26] assign _io_core_exe_0_iresp_bits_data_T_8 = _GEN_372; // @[AMOALU.scala:45:26] wire _io_core_exe_0_fresp_bits_data_T_8; // @[AMOALU.scala:45:26] assign _io_core_exe_0_fresp_bits_data_T_8 = _GEN_372; // @[AMOALU.scala:45:26] wire _ldq_bits_debug_wb_data_T_8; // @[AMOALU.scala:45:26] assign _ldq_bits_debug_wb_data_T_8 = _GEN_372; // @[AMOALU.scala:45:26] wire _io_core_exe_0_iresp_bits_data_T_9 = _io_core_exe_0_iresp_bits_data_T_8; // @[AMOALU.scala:45:{26,34}] wire _io_core_exe_0_iresp_bits_data_T_10 = io_core_exe_0_iresp_bits_data_zeroed_1[15]; // @[AMOALU.scala:44:23, :45:81] wire _io_core_exe_0_iresp_bits_data_T_11 = _GEN_143[_forward_uop_T_1] & _io_core_exe_0_iresp_bits_data_T_10; // @[AMOALU.scala:45:{72,81}] wire [47:0] _io_core_exe_0_iresp_bits_data_T_12 = {48{_io_core_exe_0_iresp_bits_data_T_11}}; // @[AMOALU.scala:45:{49,72}] wire [47:0] _io_core_exe_0_iresp_bits_data_T_13 = _io_core_exe_0_iresp_bits_data_T_7[63:16]; // @[AMOALU.scala:45:{16,94}] wire [47:0] _io_core_exe_0_iresp_bits_data_T_14 = _io_core_exe_0_iresp_bits_data_T_9 ? _io_core_exe_0_iresp_bits_data_T_12 : _io_core_exe_0_iresp_bits_data_T_13; // @[AMOALU.scala:45:{20,34,49,94}] wire [63:0] _io_core_exe_0_iresp_bits_data_T_15 = {_io_core_exe_0_iresp_bits_data_T_14, io_core_exe_0_iresp_bits_data_zeroed_1}; // @[AMOALU.scala:44:23, :45:{16,20}] wire _io_core_exe_0_iresp_bits_data_shifted_T_6 = wb_forward_ld_addr_0[0]; // @[AMOALU.scala:42:29] wire _io_core_exe_0_fresp_bits_data_shifted_T_6 = wb_forward_ld_addr_0[0]; // @[AMOALU.scala:42:29] wire _ldq_bits_debug_wb_data_shifted_T_6 = wb_forward_ld_addr_0[0]; // @[AMOALU.scala:42:29] wire [7:0] _io_core_exe_0_iresp_bits_data_shifted_T_7 = _io_core_exe_0_iresp_bits_data_T_15[15:8]; // @[AMOALU.scala:42:37, :45:16] wire [7:0] _io_core_exe_0_iresp_bits_data_shifted_T_8 = _io_core_exe_0_iresp_bits_data_T_15[7:0]; // @[AMOALU.scala:42:55, :45:16] wire [7:0] io_core_exe_0_iresp_bits_data_shifted_2 = _io_core_exe_0_iresp_bits_data_shifted_T_6 ? _io_core_exe_0_iresp_bits_data_shifted_T_7 : _io_core_exe_0_iresp_bits_data_shifted_T_8; // @[AMOALU.scala:42:{24,29,37,55}] wire [7:0] io_core_exe_0_iresp_bits_data_zeroed_2 = io_core_exe_0_iresp_bits_data_shifted_2; // @[AMOALU.scala:42:24, :44:23] wire _GEN_373 = size_1 == 2'h0; // @[AMOALU.scala:11:18, :45:26] wire _io_core_exe_0_iresp_bits_data_T_16; // @[AMOALU.scala:45:26] assign _io_core_exe_0_iresp_bits_data_T_16 = _GEN_373; // @[AMOALU.scala:45:26] wire _io_core_exe_0_fresp_bits_data_T_16; // @[AMOALU.scala:45:26] assign _io_core_exe_0_fresp_bits_data_T_16 = _GEN_373; // @[AMOALU.scala:45:26] wire _ldq_bits_debug_wb_data_T_16; // @[AMOALU.scala:45:26] assign _ldq_bits_debug_wb_data_T_16 = _GEN_373; // @[AMOALU.scala:45:26] wire _io_core_exe_0_iresp_bits_data_T_17 = _io_core_exe_0_iresp_bits_data_T_16; // @[AMOALU.scala:45:{26,34}] wire _io_core_exe_0_iresp_bits_data_T_18 = io_core_exe_0_iresp_bits_data_zeroed_2[7]; // @[AMOALU.scala:44:23, :45:81] wire _io_core_exe_0_iresp_bits_data_T_19 = _GEN_143[_forward_uop_T_1] & _io_core_exe_0_iresp_bits_data_T_18; // @[AMOALU.scala:45:{72,81}] wire [55:0] _io_core_exe_0_iresp_bits_data_T_20 = {56{_io_core_exe_0_iresp_bits_data_T_19}}; // @[AMOALU.scala:45:{49,72}] wire [55:0] _io_core_exe_0_iresp_bits_data_T_21 = _io_core_exe_0_iresp_bits_data_T_15[63:8]; // @[AMOALU.scala:45:{16,94}] wire [55:0] _io_core_exe_0_iresp_bits_data_T_22 = _io_core_exe_0_iresp_bits_data_T_17 ? _io_core_exe_0_iresp_bits_data_T_20 : _io_core_exe_0_iresp_bits_data_T_21; // @[AMOALU.scala:45:{20,34,49,94}] wire [63:0] _io_core_exe_0_iresp_bits_data_T_23 = {_io_core_exe_0_iresp_bits_data_T_22, io_core_exe_0_iresp_bits_data_zeroed_2}; // @[AMOALU.scala:44:23, :45:{16,20}] assign io_core_exe_0_iresp_bits_data_0 = _GEN_370 ? io_dmem_resp_0_bits_data_0 : _io_core_exe_0_iresp_bits_data_T_23; // @[AMOALU.scala:45:16] wire [31:0] io_core_exe_0_fresp_bits_data_shifted = _io_core_exe_0_fresp_bits_data_shifted_T ? _io_core_exe_0_fresp_bits_data_shifted_T_1 : _io_core_exe_0_fresp_bits_data_shifted_T_2; // @[AMOALU.scala:42:{24,29,37,55}] wire [31:0] io_core_exe_0_fresp_bits_data_zeroed = io_core_exe_0_fresp_bits_data_shifted; // @[AMOALU.scala:42:24, :44:23] wire _io_core_exe_0_fresp_bits_data_T_1 = _io_core_exe_0_fresp_bits_data_T; // @[AMOALU.scala:45:{26,34}] wire _io_core_exe_0_fresp_bits_data_T_2 = io_core_exe_0_fresp_bits_data_zeroed[31]; // @[AMOALU.scala:44:23, :45:81] wire _io_core_exe_0_fresp_bits_data_T_3 = _GEN_143[_forward_uop_T_1] & _io_core_exe_0_fresp_bits_data_T_2; // @[AMOALU.scala:45:{72,81}] wire [31:0] _io_core_exe_0_fresp_bits_data_T_4 = {32{_io_core_exe_0_fresp_bits_data_T_3}}; // @[AMOALU.scala:45:{49,72}] wire [31:0] _io_core_exe_0_fresp_bits_data_T_6 = _io_core_exe_0_fresp_bits_data_T_1 ? _io_core_exe_0_fresp_bits_data_T_4 : _io_core_exe_0_fresp_bits_data_T_5; // @[AMOALU.scala:45:{20,34,49,94}] wire [63:0] _io_core_exe_0_fresp_bits_data_T_7 = {_io_core_exe_0_fresp_bits_data_T_6, io_core_exe_0_fresp_bits_data_zeroed}; // @[AMOALU.scala:44:23, :45:{16,20}] wire [15:0] _io_core_exe_0_fresp_bits_data_shifted_T_4 = _io_core_exe_0_fresp_bits_data_T_7[31:16]; // @[AMOALU.scala:42:37, :45:16] wire [15:0] _io_core_exe_0_fresp_bits_data_shifted_T_5 = _io_core_exe_0_fresp_bits_data_T_7[15:0]; // @[AMOALU.scala:42:55, :45:16] wire [15:0] io_core_exe_0_fresp_bits_data_shifted_1 = _io_core_exe_0_fresp_bits_data_shifted_T_3 ? _io_core_exe_0_fresp_bits_data_shifted_T_4 : _io_core_exe_0_fresp_bits_data_shifted_T_5; // @[AMOALU.scala:42:{24,29,37,55}] wire [15:0] io_core_exe_0_fresp_bits_data_zeroed_1 = io_core_exe_0_fresp_bits_data_shifted_1; // @[AMOALU.scala:42:24, :44:23] wire _io_core_exe_0_fresp_bits_data_T_9 = _io_core_exe_0_fresp_bits_data_T_8; // @[AMOALU.scala:45:{26,34}] wire _io_core_exe_0_fresp_bits_data_T_10 = io_core_exe_0_fresp_bits_data_zeroed_1[15]; // @[AMOALU.scala:44:23, :45:81] wire _io_core_exe_0_fresp_bits_data_T_11 = _GEN_143[_forward_uop_T_1] & _io_core_exe_0_fresp_bits_data_T_10; // @[AMOALU.scala:45:{72,81}] wire [47:0] _io_core_exe_0_fresp_bits_data_T_12 = {48{_io_core_exe_0_fresp_bits_data_T_11}}; // @[AMOALU.scala:45:{49,72}] wire [47:0] _io_core_exe_0_fresp_bits_data_T_13 = _io_core_exe_0_fresp_bits_data_T_7[63:16]; // @[AMOALU.scala:45:{16,94}] wire [47:0] _io_core_exe_0_fresp_bits_data_T_14 = _io_core_exe_0_fresp_bits_data_T_9 ? _io_core_exe_0_fresp_bits_data_T_12 : _io_core_exe_0_fresp_bits_data_T_13; // @[AMOALU.scala:45:{20,34,49,94}] wire [63:0] _io_core_exe_0_fresp_bits_data_T_15 = {_io_core_exe_0_fresp_bits_data_T_14, io_core_exe_0_fresp_bits_data_zeroed_1}; // @[AMOALU.scala:44:23, :45:{16,20}] wire [7:0] _io_core_exe_0_fresp_bits_data_shifted_T_7 = _io_core_exe_0_fresp_bits_data_T_15[15:8]; // @[AMOALU.scala:42:37, :45:16] wire [7:0] _io_core_exe_0_fresp_bits_data_shifted_T_8 = _io_core_exe_0_fresp_bits_data_T_15[7:0]; // @[AMOALU.scala:42:55, :45:16] wire [7:0] io_core_exe_0_fresp_bits_data_shifted_2 = _io_core_exe_0_fresp_bits_data_shifted_T_6 ? _io_core_exe_0_fresp_bits_data_shifted_T_7 : _io_core_exe_0_fresp_bits_data_shifted_T_8; // @[AMOALU.scala:42:{24,29,37,55}] wire [7:0] io_core_exe_0_fresp_bits_data_zeroed_2 = io_core_exe_0_fresp_bits_data_shifted_2; // @[AMOALU.scala:42:24, :44:23] wire _io_core_exe_0_fresp_bits_data_T_17 = _io_core_exe_0_fresp_bits_data_T_16; // @[AMOALU.scala:45:{26,34}] wire _io_core_exe_0_fresp_bits_data_T_18 = io_core_exe_0_fresp_bits_data_zeroed_2[7]; // @[AMOALU.scala:44:23, :45:81] wire _io_core_exe_0_fresp_bits_data_T_19 = _GEN_143[_forward_uop_T_1] & _io_core_exe_0_fresp_bits_data_T_18; // @[AMOALU.scala:45:{72,81}] wire [55:0] _io_core_exe_0_fresp_bits_data_T_20 = {56{_io_core_exe_0_fresp_bits_data_T_19}}; // @[AMOALU.scala:45:{49,72}] wire [55:0] _io_core_exe_0_fresp_bits_data_T_21 = _io_core_exe_0_fresp_bits_data_T_15[63:8]; // @[AMOALU.scala:45:{16,94}] wire [55:0] _io_core_exe_0_fresp_bits_data_T_22 = _io_core_exe_0_fresp_bits_data_T_17 ? _io_core_exe_0_fresp_bits_data_T_20 : _io_core_exe_0_fresp_bits_data_T_21; // @[AMOALU.scala:45:{20,34,49,94}] wire [63:0] _io_core_exe_0_fresp_bits_data_T_23 = {_io_core_exe_0_fresp_bits_data_T_22, io_core_exe_0_fresp_bits_data_zeroed_2}; // @[AMOALU.scala:44:23, :45:{16,20}] assign io_core_exe_0_fresp_bits_data_0 = {1'h0, _GEN_370 ? io_dmem_resp_0_bits_data_0 : _io_core_exe_0_fresp_bits_data_T_23}; // @[AMOALU.scala:45:16] wire [31:0] ldq_bits_debug_wb_data_shifted = _ldq_bits_debug_wb_data_shifted_T ? _ldq_bits_debug_wb_data_shifted_T_1 : _ldq_bits_debug_wb_data_shifted_T_2; // @[AMOALU.scala:42:{24,29,37,55}] wire [31:0] ldq_bits_debug_wb_data_zeroed = ldq_bits_debug_wb_data_shifted; // @[AMOALU.scala:42:24, :44:23] wire _ldq_bits_debug_wb_data_T_1 = _ldq_bits_debug_wb_data_T; // @[AMOALU.scala:45:{26,34}] wire _ldq_bits_debug_wb_data_T_2 = ldq_bits_debug_wb_data_zeroed[31]; // @[AMOALU.scala:44:23, :45:81] wire _ldq_bits_debug_wb_data_T_3 = _GEN_143[_forward_uop_T_1] & _ldq_bits_debug_wb_data_T_2; // @[AMOALU.scala:45:{72,81}] wire [31:0] _ldq_bits_debug_wb_data_T_4 = {32{_ldq_bits_debug_wb_data_T_3}}; // @[AMOALU.scala:45:{49,72}] wire [31:0] _ldq_bits_debug_wb_data_T_6 = _ldq_bits_debug_wb_data_T_1 ? _ldq_bits_debug_wb_data_T_4 : _ldq_bits_debug_wb_data_T_5; // @[AMOALU.scala:45:{20,34,49,94}] wire [63:0] _ldq_bits_debug_wb_data_T_7 = {_ldq_bits_debug_wb_data_T_6, ldq_bits_debug_wb_data_zeroed}; // @[AMOALU.scala:44:23, :45:{16,20}] wire [15:0] _ldq_bits_debug_wb_data_shifted_T_4 = _ldq_bits_debug_wb_data_T_7[31:16]; // @[AMOALU.scala:42:37, :45:16] wire [15:0] _ldq_bits_debug_wb_data_shifted_T_5 = _ldq_bits_debug_wb_data_T_7[15:0]; // @[AMOALU.scala:42:55, :45:16] wire [15:0] ldq_bits_debug_wb_data_shifted_1 = _ldq_bits_debug_wb_data_shifted_T_3 ? _ldq_bits_debug_wb_data_shifted_T_4 : _ldq_bits_debug_wb_data_shifted_T_5; // @[AMOALU.scala:42:{24,29,37,55}] wire [15:0] ldq_bits_debug_wb_data_zeroed_1 = ldq_bits_debug_wb_data_shifted_1; // @[AMOALU.scala:42:24, :44:23] wire _ldq_bits_debug_wb_data_T_9 = _ldq_bits_debug_wb_data_T_8; // @[AMOALU.scala:45:{26,34}] wire _ldq_bits_debug_wb_data_T_10 = ldq_bits_debug_wb_data_zeroed_1[15]; // @[AMOALU.scala:44:23, :45:81] wire _ldq_bits_debug_wb_data_T_11 = _GEN_143[_forward_uop_T_1] & _ldq_bits_debug_wb_data_T_10; // @[AMOALU.scala:45:{72,81}] wire [47:0] _ldq_bits_debug_wb_data_T_12 = {48{_ldq_bits_debug_wb_data_T_11}}; // @[AMOALU.scala:45:{49,72}] wire [47:0] _ldq_bits_debug_wb_data_T_13 = _ldq_bits_debug_wb_data_T_7[63:16]; // @[AMOALU.scala:45:{16,94}] wire [47:0] _ldq_bits_debug_wb_data_T_14 = _ldq_bits_debug_wb_data_T_9 ? _ldq_bits_debug_wb_data_T_12 : _ldq_bits_debug_wb_data_T_13; // @[AMOALU.scala:45:{20,34,49,94}] wire [63:0] _ldq_bits_debug_wb_data_T_15 = {_ldq_bits_debug_wb_data_T_14, ldq_bits_debug_wb_data_zeroed_1}; // @[AMOALU.scala:44:23, :45:{16,20}] wire [7:0] _ldq_bits_debug_wb_data_shifted_T_7 = _ldq_bits_debug_wb_data_T_15[15:8]; // @[AMOALU.scala:42:37, :45:16] wire [7:0] _ldq_bits_debug_wb_data_shifted_T_8 = _ldq_bits_debug_wb_data_T_15[7:0]; // @[AMOALU.scala:42:55, :45:16] wire [7:0] ldq_bits_debug_wb_data_shifted_2 = _ldq_bits_debug_wb_data_shifted_T_6 ? _ldq_bits_debug_wb_data_shifted_T_7 : _ldq_bits_debug_wb_data_shifted_T_8; // @[AMOALU.scala:42:{24,29,37,55}] wire [7:0] ldq_bits_debug_wb_data_zeroed_2 = ldq_bits_debug_wb_data_shifted_2; // @[AMOALU.scala:42:24, :44:23] wire _ldq_bits_debug_wb_data_T_17 = _ldq_bits_debug_wb_data_T_16; // @[AMOALU.scala:45:{26,34}] wire _ldq_bits_debug_wb_data_T_18 = ldq_bits_debug_wb_data_zeroed_2[7]; // @[AMOALU.scala:44:23, :45:81] wire _ldq_bits_debug_wb_data_T_19 = _GEN_143[_forward_uop_T_1] & _ldq_bits_debug_wb_data_T_18; // @[AMOALU.scala:45:{72,81}] wire [55:0] _ldq_bits_debug_wb_data_T_20 = {56{_ldq_bits_debug_wb_data_T_19}}; // @[AMOALU.scala:45:{49,72}] wire [55:0] _ldq_bits_debug_wb_data_T_21 = _ldq_bits_debug_wb_data_T_15[63:8]; // @[AMOALU.scala:45:{16,94}] wire [55:0] _ldq_bits_debug_wb_data_T_22 = _ldq_bits_debug_wb_data_T_17 ? _ldq_bits_debug_wb_data_T_20 : _ldq_bits_debug_wb_data_T_21; // @[AMOALU.scala:45:{20,34,49,94}] wire [63:0] _ldq_bits_debug_wb_data_T_23 = {_ldq_bits_debug_wb_data_T_22, ldq_bits_debug_wb_data_zeroed_2}; // @[AMOALU.scala:44:23, :45:{16,20}] reg io_core_ld_miss_REG; // @[lsu.scala:1383:37] reg spec_ld_succeed_REG; // @[lsu.scala:1385:13] wire _spec_ld_succeed_T = ~spec_ld_succeed_REG; // @[lsu.scala:1385:{5,13}] reg [2:0] spec_ld_succeed_REG_1; // @[lsu.scala:1387:56] wire _spec_ld_succeed_T_1 = io_core_exe_0_iresp_bits_uop_ldq_idx_0 == spec_ld_succeed_REG_1; // @[lsu.scala:201:7, :1387:{45,56}] wire _spec_ld_succeed_T_2 = io_core_exe_0_iresp_valid_0 & _spec_ld_succeed_T_1; // @[lsu.scala:201:7, :1386:33, :1387:45] wire _spec_ld_succeed_T_3 = _spec_ld_succeed_T | _spec_ld_succeed_T_2; // @[lsu.scala:1385:{5,47}, :1386:33] wire _spec_ld_succeed_WIRE_0 = _spec_ld_succeed_T_3; // @[lsu.scala:263:49, :1385:47] assign io_core_ld_miss_0 = ~_spec_ld_succeed_WIRE_0 & io_core_ld_miss_REG; // @[lsu.scala:201:7, :263:49, :1383:{27,37}, :1390:26, :1391:21] wire st_brkilled_mask_0; // @[lsu.scala:1401:30] wire st_brkilled_mask_1; // @[lsu.scala:1401:30] wire st_brkilled_mask_2; // @[lsu.scala:1401:30] wire st_brkilled_mask_3; // @[lsu.scala:1401:30] wire st_brkilled_mask_4; // @[lsu.scala:1401:30] wire st_brkilled_mask_5; // @[lsu.scala:1401:30] wire st_brkilled_mask_6; // @[lsu.scala:1401:30] wire st_brkilled_mask_7; // @[lsu.scala:1401:30] wire [7:0] _stq_0_bits_uop_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:85:27, :89:23] wire [7:0] _stq_0_bits_uop_br_mask_T_1 = stq_0_bits_uop_br_mask & _stq_0_bits_uop_br_mask_T; // @[util.scala:89:{21,23}] wire [7:0] _T_717 = io_core_brupdate_b1_mispredict_mask_0 & stq_0_bits_uop_br_mask; // @[util.scala:118:51] assign st_brkilled_mask_0 = stq_0_valid & (|_T_717); // @[util.scala:118:{51,59}] wire [7:0] _stq_1_bits_uop_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:85:27, :89:23] wire [7:0] _stq_1_bits_uop_br_mask_T_1 = stq_1_bits_uop_br_mask & _stq_1_bits_uop_br_mask_T; // @[util.scala:89:{21,23}] wire [7:0] _T_727 = io_core_brupdate_b1_mispredict_mask_0 & stq_1_bits_uop_br_mask; // @[util.scala:118:51] assign st_brkilled_mask_1 = stq_1_valid & (|_T_727); // @[util.scala:118:{51,59}] wire [7:0] _stq_2_bits_uop_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:85:27, :89:23] wire [7:0] _stq_2_bits_uop_br_mask_T_1 = stq_2_bits_uop_br_mask & _stq_2_bits_uop_br_mask_T; // @[util.scala:89:{21,23}] wire [7:0] _T_737 = io_core_brupdate_b1_mispredict_mask_0 & stq_2_bits_uop_br_mask; // @[util.scala:118:51] assign st_brkilled_mask_2 = stq_2_valid & (|_T_737); // @[util.scala:118:{51,59}] wire [7:0] _stq_3_bits_uop_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:85:27, :89:23] wire [7:0] _stq_3_bits_uop_br_mask_T_1 = stq_3_bits_uop_br_mask & _stq_3_bits_uop_br_mask_T; // @[util.scala:89:{21,23}] wire [7:0] _T_747 = io_core_brupdate_b1_mispredict_mask_0 & stq_3_bits_uop_br_mask; // @[util.scala:118:51] assign st_brkilled_mask_3 = stq_3_valid & (|_T_747); // @[util.scala:118:{51,59}] wire [7:0] _stq_4_bits_uop_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:85:27, :89:23] wire [7:0] _stq_4_bits_uop_br_mask_T_1 = stq_4_bits_uop_br_mask & _stq_4_bits_uop_br_mask_T; // @[util.scala:89:{21,23}] wire [7:0] _T_757 = io_core_brupdate_b1_mispredict_mask_0 & stq_4_bits_uop_br_mask; // @[util.scala:118:51] assign st_brkilled_mask_4 = stq_4_valid & (|_T_757); // @[util.scala:118:{51,59}] wire [7:0] _stq_5_bits_uop_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:85:27, :89:23] wire [7:0] _stq_5_bits_uop_br_mask_T_1 = stq_5_bits_uop_br_mask & _stq_5_bits_uop_br_mask_T; // @[util.scala:89:{21,23}] wire [7:0] _T_767 = io_core_brupdate_b1_mispredict_mask_0 & stq_5_bits_uop_br_mask; // @[util.scala:118:51] assign st_brkilled_mask_5 = stq_5_valid & (|_T_767); // @[util.scala:118:{51,59}] wire [7:0] _stq_6_bits_uop_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:85:27, :89:23] wire [7:0] _stq_6_bits_uop_br_mask_T_1 = stq_6_bits_uop_br_mask & _stq_6_bits_uop_br_mask_T; // @[util.scala:89:{21,23}] wire [7:0] _T_777 = io_core_brupdate_b1_mispredict_mask_0 & stq_6_bits_uop_br_mask; // @[util.scala:118:51] assign st_brkilled_mask_6 = stq_6_valid & (|_T_777); // @[util.scala:118:{51,59}] wire [7:0] _stq_7_bits_uop_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:85:27, :89:23] wire [7:0] _stq_7_bits_uop_br_mask_T_1 = stq_7_bits_uop_br_mask & _stq_7_bits_uop_br_mask_T; // @[util.scala:89:{21,23}] wire [7:0] _T_787 = io_core_brupdate_b1_mispredict_mask_0 & stq_7_bits_uop_br_mask; // @[util.scala:118:51] assign st_brkilled_mask_7 = stq_7_valid & (|_T_787); // @[util.scala:118:{51,59}] wire [7:0] _ldq_0_bits_uop_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:85:27, :89:23] wire [7:0] _ldq_0_bits_uop_br_mask_T_1 = ldq_0_bits_uop_br_mask & _ldq_0_bits_uop_br_mask_T; // @[util.scala:89:{21,23}] wire [7:0] _ldq_1_bits_uop_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:85:27, :89:23] wire [7:0] _ldq_1_bits_uop_br_mask_T_1 = ldq_1_bits_uop_br_mask & _ldq_1_bits_uop_br_mask_T; // @[util.scala:89:{21,23}] wire [7:0] _ldq_2_bits_uop_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:85:27, :89:23] wire [7:0] _ldq_2_bits_uop_br_mask_T_1 = ldq_2_bits_uop_br_mask & _ldq_2_bits_uop_br_mask_T; // @[util.scala:89:{21,23}] wire [7:0] _ldq_3_bits_uop_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:85:27, :89:23] wire [7:0] _ldq_3_bits_uop_br_mask_T_1 = ldq_3_bits_uop_br_mask & _ldq_3_bits_uop_br_mask_T; // @[util.scala:89:{21,23}] wire [7:0] _ldq_4_bits_uop_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:85:27, :89:23] wire [7:0] _ldq_4_bits_uop_br_mask_T_1 = ldq_4_bits_uop_br_mask & _ldq_4_bits_uop_br_mask_T; // @[util.scala:89:{21,23}] wire [7:0] _ldq_5_bits_uop_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:85:27, :89:23] wire [7:0] _ldq_5_bits_uop_br_mask_T_1 = ldq_5_bits_uop_br_mask & _ldq_5_bits_uop_br_mask_T; // @[util.scala:89:{21,23}] wire [7:0] _ldq_6_bits_uop_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:85:27, :89:23] wire [7:0] _ldq_6_bits_uop_br_mask_T_1 = ldq_6_bits_uop_br_mask & _ldq_6_bits_uop_br_mask_T; // @[util.scala:89:{21,23}] wire [7:0] _ldq_7_bits_uop_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:85:27, :89:23] wire [7:0] _ldq_7_bits_uop_br_mask_T_1 = ldq_7_bits_uop_br_mask & _ldq_7_bits_uop_br_mask_T; // @[util.scala:89:{21,23}] wire commit_store = io_core_commit_valids_0_0 & io_core_commit_uops_0_uses_stq_0; // @[lsu.scala:201:7, :1454:49] wire commit_load = io_core_commit_valids_0_0 & io_core_commit_uops_0_uses_ldq_0; // @[lsu.scala:201:7, :1455:49] wire [2:0] idx = commit_store ? stq_commit_head : ldq_head; // @[lsu.scala:213:29, :217:29, :1454:49, :1456:18] wire _GEN_374 = ~commit_store & commit_load; // @[lsu.scala:1454:49, :1455:49, :1458:5, :1460:31] wire _GEN_375 = _GEN_374 & ~reset; // @[lsu.scala:1460:31, :1461:14]

Generate the Verilog code corresponding to the following Chisel files. File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /** Like Vec.apply(idx), but tolerates indices of mismatched width */ def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /** Any Data subtype that has a Bool member named valid. */ type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /** converts from camel case to to underscores, also removing all spaces */ def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /** converts spaces or underscores to hyphens, also lowering case */ def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y | (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y || y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /** Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation */ def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File PMP.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.rocket import chisel3._ import chisel3.util.{Cat, log2Ceil} import org.chipsalliance.cde.config._ import freechips.rocketchip.tile._ import freechips.rocketchip.util._ class PMPConfig extends Bundle { val l = Bool() val res = UInt(2.W) val a = UInt(2.W) val x = Bool() val w = Bool() val r = Bool() } object PMP { def lgAlign = 2 def apply(reg: PMPReg): PMP = { val pmp = Wire(new PMP()(reg.p)) pmp.cfg := reg.cfg pmp.addr := reg.addr pmp.mask := pmp.computeMask pmp } } class PMPReg(implicit p: Parameters) extends CoreBundle()(p) { val cfg = new PMPConfig val addr = UInt((paddrBits - PMP.lgAlign).W) def reset(): Unit = { cfg.a := 0.U cfg.l := 0.U } def readAddr = if (pmpGranularity.log2 == PMP.lgAlign) addr else { val mask = ((BigInt(1) << (pmpGranularity.log2 - PMP.lgAlign)) - 1).U Mux(napot, addr | (mask >> 1), ~(~addr | mask)) } def napot = cfg.a(1) def torNotNAPOT = cfg.a(0) def tor = !napot && torNotNAPOT def cfgLocked = cfg.l def addrLocked(next: PMPReg) = cfgLocked || next.cfgLocked && next.tor } class PMP(implicit p: Parameters) extends PMPReg { val mask = UInt(paddrBits.W) import PMP._ def computeMask = { val base = Cat(addr, cfg.a(0)) | ((pmpGranularity - 1).U >> lgAlign) Cat(base & ~(base + 1.U), ((1 << lgAlign) - 1).U) } private def comparand = ~(~(addr << lgAlign) | (pmpGranularity - 1).U) private def pow2Match(x: UInt, lgSize: UInt, lgMaxSize: Int) = { def eval(a: UInt, b: UInt, m: UInt) = ((a ^ b) & ~m) === 0.U if (lgMaxSize <= pmpGranularity.log2) { eval(x, comparand, mask) } else { // break up the circuit; the MSB part will be CSE'd val lsbMask = mask | UIntToOH1(lgSize, lgMaxSize) val msbMatch = eval(x >> lgMaxSize, comparand >> lgMaxSize, mask >> lgMaxSize) val lsbMatch = eval(x(lgMaxSize-1, 0), comparand(lgMaxSize-1, 0), lsbMask(lgMaxSize-1, 0)) msbMatch && lsbMatch } } private def boundMatch(x: UInt, lsbMask: UInt, lgMaxSize: Int) = { if (lgMaxSize <= pmpGranularity.log2) { x < comparand } else { // break up the circuit; the MSB part will be CSE'd val msbsLess = (x >> lgMaxSize) < (comparand >> lgMaxSize) val msbsEqual = ((x >> lgMaxSize) ^ (comparand >> lgMaxSize)) === 0.U val lsbsLess = (x(lgMaxSize-1, 0) | lsbMask) < comparand(lgMaxSize-1, 0) msbsLess || (msbsEqual && lsbsLess) } } private def lowerBoundMatch(x: UInt, lgSize: UInt, lgMaxSize: Int) = !boundMatch(x, UIntToOH1(lgSize, lgMaxSize), lgMaxSize) private def upperBoundMatch(x: UInt, lgMaxSize: Int) = boundMatch(x, 0.U, lgMaxSize) private def rangeMatch(x: UInt, lgSize: UInt, lgMaxSize: Int, prev: PMP) = prev.lowerBoundMatch(x, lgSize, lgMaxSize) && upperBoundMatch(x, lgMaxSize) private def pow2Homogeneous(x: UInt, pgLevel: UInt) = { val maskHomogeneous = pgLevelMap { idxBits => if (idxBits > paddrBits) false.B else mask(idxBits - 1) } (pgLevel) maskHomogeneous || (pgLevelMap { idxBits => ((x ^ comparand) >> idxBits) =/= 0.U } (pgLevel)) } private def pgLevelMap[T](f: Int => T) = (0 until pgLevels).map { i => f(pgIdxBits + (pgLevels - 1 - i) * pgLevelBits) } private def rangeHomogeneous(x: UInt, pgLevel: UInt, prev: PMP) = { val beginsAfterLower = !(x < prev.comparand) val beginsAfterUpper = !(x < comparand) val pgMask = pgLevelMap { idxBits => (((BigInt(1) << paddrBits) - (BigInt(1) << idxBits)) max 0).U } (pgLevel) val endsBeforeLower = (x & pgMask) < (prev.comparand & pgMask) val endsBeforeUpper = (x & pgMask) < (comparand & pgMask) endsBeforeLower || beginsAfterUpper || (beginsAfterLower && endsBeforeUpper) } // returns whether this PMP completely contains, or contains none of, a page def homogeneous(x: UInt, pgLevel: UInt, prev: PMP): Bool = Mux(napot, pow2Homogeneous(x, pgLevel), !torNotNAPOT || rangeHomogeneous(x, pgLevel, prev)) // returns whether this matching PMP fully contains the access def aligned(x: UInt, lgSize: UInt, lgMaxSize: Int, prev: PMP): Bool = if (lgMaxSize <= pmpGranularity.log2) true.B else { val lsbMask = UIntToOH1(lgSize, lgMaxSize) val straddlesLowerBound = ((x >> lgMaxSize) ^ (prev.comparand >> lgMaxSize)) === 0.U && (prev.comparand(lgMaxSize-1, 0) & ~x(lgMaxSize-1, 0)) =/= 0.U val straddlesUpperBound = ((x >> lgMaxSize) ^ (comparand >> lgMaxSize)) === 0.U && (comparand(lgMaxSize-1, 0) & (x(lgMaxSize-1, 0) | lsbMask)) =/= 0.U val rangeAligned = !(straddlesLowerBound || straddlesUpperBound) val pow2Aligned = (lsbMask & ~mask(lgMaxSize-1, 0)) === 0.U Mux(napot, pow2Aligned, rangeAligned) } // returns whether this PMP matches at least one byte of the access def hit(x: UInt, lgSize: UInt, lgMaxSize: Int, prev: PMP): Bool = Mux(napot, pow2Match(x, lgSize, lgMaxSize), torNotNAPOT && rangeMatch(x, lgSize, lgMaxSize, prev)) } class PMPHomogeneityChecker(pmps: Seq[PMP])(implicit p: Parameters) { def apply(addr: UInt, pgLevel: UInt): Bool = { pmps.foldLeft((true.B, 0.U.asTypeOf(new PMP))) { case ((h, prev), pmp) => (h && pmp.homogeneous(addr, pgLevel, prev), pmp) }._1 } } class PMPChecker(lgMaxSize: Int)(implicit val p: Parameters) extends Module with HasCoreParameters { override def desiredName = s"PMPChecker_s${lgMaxSize}" val io = IO(new Bundle { val prv = Input(UInt(PRV.SZ.W)) val pmp = Input(Vec(nPMPs, new PMP)) val addr = Input(UInt(paddrBits.W)) val size = Input(UInt(log2Ceil(lgMaxSize + 1).W)) val r = Output(Bool()) val w = Output(Bool()) val x = Output(Bool()) }) val default = if (io.pmp.isEmpty) true.B else io.prv > PRV.S.U val pmp0 = WireInit(0.U.asTypeOf(new PMP)) pmp0.cfg.r := default pmp0.cfg.w := default pmp0.cfg.x := default val res = (io.pmp zip (pmp0 +: io.pmp)).reverse.foldLeft(pmp0) { case (prev, (pmp, prevPMP)) => val hit = pmp.hit(io.addr, io.size, lgMaxSize, prevPMP) val ignore = default && !pmp.cfg.l val aligned = pmp.aligned(io.addr, io.size, lgMaxSize, prevPMP) for ((name, idx) <- Seq("no", "TOR", if (pmpGranularity <= 4) "NA4" else "", "NAPOT").zipWithIndex; if name.nonEmpty) property.cover(pmp.cfg.a === idx.U, s"The cfg access is set to ${name} access ", "Cover PMP access mode setting") property.cover(pmp.cfg.l === 0x1.U, s"The cfg lock is set to high ", "Cover PMP lock mode setting") // Not including Write and no Read permission as the combination is reserved for ((name, idx) <- Seq("no", "RO", "", "RW", "X", "RX", "", "RWX").zipWithIndex; if name.nonEmpty) property.cover((Cat(pmp.cfg.x, pmp.cfg.w, pmp.cfg.r) === idx.U), s"The permission is set to ${name} access ", "Cover PMP access permission setting") for ((name, idx) <- Seq("", "TOR", if (pmpGranularity <= 4) "NA4" else "", "NAPOT").zipWithIndex; if name.nonEmpty) { property.cover(!ignore && hit && aligned && pmp.cfg.a === idx.U, s"The access matches ${name} mode ", "Cover PMP access") property.cover(pmp.cfg.l && hit && aligned && pmp.cfg.a === idx.U, s"The access matches ${name} mode with lock bit high", "Cover PMP access with lock bit") } val cur = WireInit(pmp) cur.cfg.r := aligned && (pmp.cfg.r || ignore) cur.cfg.w := aligned && (pmp.cfg.w || ignore) cur.cfg.x := aligned && (pmp.cfg.x || ignore) Mux(hit, cur, prev) } io.r := res.cfg.r io.w := res.cfg.w io.x := res.cfg.x }

module PMPChecker_s6( // @[PMP.scala:143:7] input clock, // @[PMP.scala:143:7] input reset, // @[PMP.scala:143:7] input [1:0] io_prv, // @[PMP.scala:146:14] input io_pmp_0_cfg_l, // @[PMP.scala:146:14] input [1:0] io_pmp_0_cfg_a, // @[PMP.scala:146:14] input io_pmp_0_cfg_x, // @[PMP.scala:146:14] input io_pmp_0_cfg_w, // @[PMP.scala:146:14] input io_pmp_0_cfg_r, // @[PMP.scala:146:14] input [29:0] io_pmp_0_addr, // @[PMP.scala:146:14] input [31:0] io_pmp_0_mask, // @[PMP.scala:146:14] input io_pmp_1_cfg_l, // @[PMP.scala:146:14] input [1:0] io_pmp_1_cfg_a, // @[PMP.scala:146:14] input io_pmp_1_cfg_x, // @[PMP.scala:146:14] input io_pmp_1_cfg_w, // @[PMP.scala:146:14] input io_pmp_1_cfg_r, // @[PMP.scala:146:14] input [29:0] io_pmp_1_addr, // @[PMP.scala:146:14] input [31:0] io_pmp_1_mask, // @[PMP.scala:146:14] input io_pmp_2_cfg_l, // @[PMP.scala:146:14] input [1:0] io_pmp_2_cfg_a, // @[PMP.scala:146:14] input io_pmp_2_cfg_x, // @[PMP.scala:146:14] input io_pmp_2_cfg_w, // @[PMP.scala:146:14] input io_pmp_2_cfg_r, // @[PMP.scala:146:14] input [29:0] io_pmp_2_addr, // @[PMP.scala:146:14] input [31:0] io_pmp_2_mask, // @[PMP.scala:146:14] input io_pmp_3_cfg_l, // @[PMP.scala:146:14] input [1:0] io_pmp_3_cfg_a, // @[PMP.scala:146:14] input io_pmp_3_cfg_x, // @[PMP.scala:146:14] input io_pmp_3_cfg_w, // @[PMP.scala:146:14] input io_pmp_3_cfg_r, // @[PMP.scala:146:14] input [29:0] io_pmp_3_addr, // @[PMP.scala:146:14] input [31:0] io_pmp_3_mask, // @[PMP.scala:146:14] input io_pmp_4_cfg_l, // @[PMP.scala:146:14] input [1:0] io_pmp_4_cfg_a, // @[PMP.scala:146:14] input io_pmp_4_cfg_x, // @[PMP.scala:146:14] input io_pmp_4_cfg_w, // @[PMP.scala:146:14] input io_pmp_4_cfg_r, // @[PMP.scala:146:14] input [29:0] io_pmp_4_addr, // @[PMP.scala:146:14] input [31:0] io_pmp_4_mask, // @[PMP.scala:146:14] input io_pmp_5_cfg_l, // @[PMP.scala:146:14] input [1:0] io_pmp_5_cfg_a, // @[PMP.scala:146:14] input io_pmp_5_cfg_x, // @[PMP.scala:146:14] input io_pmp_5_cfg_w, // @[PMP.scala:146:14] input io_pmp_5_cfg_r, // @[PMP.scala:146:14] input [29:0] io_pmp_5_addr, // @[PMP.scala:146:14] input [31:0] io_pmp_5_mask, // @[PMP.scala:146:14] input io_pmp_6_cfg_l, // @[PMP.scala:146:14] input [1:0] io_pmp_6_cfg_a, // @[PMP.scala:146:14] input io_pmp_6_cfg_x, // @[PMP.scala:146:14] input io_pmp_6_cfg_w, // @[PMP.scala:146:14] input io_pmp_6_cfg_r, // @[PMP.scala:146:14] input [29:0] io_pmp_6_addr, // @[PMP.scala:146:14] input [31:0] io_pmp_6_mask, // @[PMP.scala:146:14] input io_pmp_7_cfg_l, // @[PMP.scala:146:14] input [1:0] io_pmp_7_cfg_a, // @[PMP.scala:146:14] input io_pmp_7_cfg_x, // @[PMP.scala:146:14] input io_pmp_7_cfg_w, // @[PMP.scala:146:14] input io_pmp_7_cfg_r, // @[PMP.scala:146:14] input [29:0] io_pmp_7_addr, // @[PMP.scala:146:14] input [31:0] io_pmp_7_mask, // @[PMP.scala:146:14] input [31:0] io_addr, // @[PMP.scala:146:14] output io_r, // @[PMP.scala:146:14] output io_w, // @[PMP.scala:146:14] output io_x // @[PMP.scala:146:14] ); wire [1:0] io_prv_0 = io_prv; // @[PMP.scala:143:7] wire io_pmp_0_cfg_l_0 = io_pmp_0_cfg_l; // @[PMP.scala:143:7] wire [1:0] io_pmp_0_cfg_a_0 = io_pmp_0_cfg_a; // @[PMP.scala:143:7] wire io_pmp_0_cfg_x_0 = io_pmp_0_cfg_x; // @[PMP.scala:143:7] wire io_pmp_0_cfg_w_0 = io_pmp_0_cfg_w; // @[PMP.scala:143:7] wire io_pmp_0_cfg_r_0 = io_pmp_0_cfg_r; // @[PMP.scala:143:7] wire [29:0] io_pmp_0_addr_0 = io_pmp_0_addr; // @[PMP.scala:143:7] wire [31:0] io_pmp_0_mask_0 = io_pmp_0_mask; // @[PMP.scala:143:7] wire io_pmp_1_cfg_l_0 = io_pmp_1_cfg_l; // @[PMP.scala:143:7] wire [1:0] io_pmp_1_cfg_a_0 = io_pmp_1_cfg_a; // @[PMP.scala:143:7] wire io_pmp_1_cfg_x_0 = io_pmp_1_cfg_x; // @[PMP.scala:143:7] wire io_pmp_1_cfg_w_0 = io_pmp_1_cfg_w; // @[PMP.scala:143:7] wire io_pmp_1_cfg_r_0 = io_pmp_1_cfg_r; // @[PMP.scala:143:7] wire [29:0] io_pmp_1_addr_0 = io_pmp_1_addr; // @[PMP.scala:143:7] wire [31:0] io_pmp_1_mask_0 = io_pmp_1_mask; // @[PMP.scala:143:7] wire io_pmp_2_cfg_l_0 = io_pmp_2_cfg_l; // @[PMP.scala:143:7] wire [1:0] io_pmp_2_cfg_a_0 = io_pmp_2_cfg_a; // @[PMP.scala:143:7] wire io_pmp_2_cfg_x_0 = io_pmp_2_cfg_x; // @[PMP.scala:143:7] wire io_pmp_2_cfg_w_0 = io_pmp_2_cfg_w; // @[PMP.scala:143:7] wire io_pmp_2_cfg_r_0 = io_pmp_2_cfg_r; // @[PMP.scala:143:7] wire [29:0] io_pmp_2_addr_0 = io_pmp_2_addr; // @[PMP.scala:143:7] wire [31:0] io_pmp_2_mask_0 = io_pmp_2_mask; // @[PMP.scala:143:7] wire io_pmp_3_cfg_l_0 = io_pmp_3_cfg_l; // @[PMP.scala:143:7] wire [1:0] io_pmp_3_cfg_a_0 = io_pmp_3_cfg_a; // @[PMP.scala:143:7] wire io_pmp_3_cfg_x_0 = io_pmp_3_cfg_x; // @[PMP.scala:143:7] wire io_pmp_3_cfg_w_0 = io_pmp_3_cfg_w; // @[PMP.scala:143:7] wire io_pmp_3_cfg_r_0 = io_pmp_3_cfg_r; // @[PMP.scala:143:7] wire [29:0] io_pmp_3_addr_0 = io_pmp_3_addr; // @[PMP.scala:143:7] wire [31:0] io_pmp_3_mask_0 = io_pmp_3_mask; // @[PMP.scala:143:7] wire io_pmp_4_cfg_l_0 = io_pmp_4_cfg_l; // @[PMP.scala:143:7] wire [1:0] io_pmp_4_cfg_a_0 = io_pmp_4_cfg_a; // @[PMP.scala:143:7] wire io_pmp_4_cfg_x_0 = io_pmp_4_cfg_x; // @[PMP.scala:143:7] wire io_pmp_4_cfg_w_0 = io_pmp_4_cfg_w; // @[PMP.scala:143:7] wire io_pmp_4_cfg_r_0 = io_pmp_4_cfg_r; // @[PMP.scala:143:7] wire [29:0] io_pmp_4_addr_0 = io_pmp_4_addr; // @[PMP.scala:143:7] wire [31:0] io_pmp_4_mask_0 = io_pmp_4_mask; // @[PMP.scala:143:7] wire io_pmp_5_cfg_l_0 = io_pmp_5_cfg_l; // @[PMP.scala:143:7] wire [1:0] io_pmp_5_cfg_a_0 = io_pmp_5_cfg_a; // @[PMP.scala:143:7] wire io_pmp_5_cfg_x_0 = io_pmp_5_cfg_x; // @[PMP.scala:143:7] wire io_pmp_5_cfg_w_0 = io_pmp_5_cfg_w; // @[PMP.scala:143:7] wire io_pmp_5_cfg_r_0 = io_pmp_5_cfg_r; // @[PMP.scala:143:7] wire [29:0] io_pmp_5_addr_0 = io_pmp_5_addr; // @[PMP.scala:143:7] wire [31:0] io_pmp_5_mask_0 = io_pmp_5_mask; // @[PMP.scala:143:7] wire io_pmp_6_cfg_l_0 = io_pmp_6_cfg_l; // @[PMP.scala:143:7] wire [1:0] io_pmp_6_cfg_a_0 = io_pmp_6_cfg_a; // @[PMP.scala:143:7] wire io_pmp_6_cfg_x_0 = io_pmp_6_cfg_x; // @[PMP.scala:143:7] wire io_pmp_6_cfg_w_0 = io_pmp_6_cfg_w; // @[PMP.scala:143:7] wire io_pmp_6_cfg_r_0 = io_pmp_6_cfg_r; // @[PMP.scala:143:7] wire [29:0] io_pmp_6_addr_0 = io_pmp_6_addr; // @[PMP.scala:143:7] wire [31:0] io_pmp_6_mask_0 = io_pmp_6_mask; // @[PMP.scala:143:7] wire io_pmp_7_cfg_l_0 = io_pmp_7_cfg_l; // @[PMP.scala:143:7] wire [1:0] io_pmp_7_cfg_a_0 = io_pmp_7_cfg_a; // @[PMP.scala:143:7] wire io_pmp_7_cfg_x_0 = io_pmp_7_cfg_x; // @[PMP.scala:143:7] wire io_pmp_7_cfg_w_0 = io_pmp_7_cfg_w; // @[PMP.scala:143:7] wire io_pmp_7_cfg_r_0 = io_pmp_7_cfg_r; // @[PMP.scala:143:7] wire [29:0] io_pmp_7_addr_0 = io_pmp_7_addr; // @[PMP.scala:143:7] wire [31:0] io_pmp_7_mask_0 = io_pmp_7_mask; // @[PMP.scala:143:7] wire [31:0] io_addr_0 = io_addr; // @[PMP.scala:143:7] wire [29:0] _pmp0_WIRE_addr = 30'h0; // @[PMP.scala:157:35] wire [29:0] pmp0_addr = 30'h0; // @[PMP.scala:157:22] wire [25:0] _res_hit_msbsLess_T_89 = 26'h0; // @[PMP.scala:80:52, :81:54, :123:67] wire [25:0] _res_hit_msbsEqual_T_103 = 26'h0; // @[PMP.scala:80:52, :81:54, :123:67] wire [25:0] _res_aligned_straddlesLowerBound_T_124 = 26'h0; // @[PMP.scala:80:52, :81:54, :123:67] wire [31:0] _res_hit_msbsLess_T_86 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsLess_T_87 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsEqual_T_100 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsEqual_T_101 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbsLess_T_101 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbsLess_T_102 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesLowerBound_T_121 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesLowerBound_T_122 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesLowerBound_T_128 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesLowerBound_T_129 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}] wire [31:0] _pmp0_WIRE_mask = 32'h0; // @[PMP.scala:157:35] wire [31:0] pmp0_mask = 32'h0; // @[PMP.scala:157:22] wire [31:0] _res_hit_msbsLess_T_85 = 32'h0; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsLess_T_88 = 32'h0; // @[PMP.scala:60:27] wire [31:0] _res_hit_msbsEqual_T_99 = 32'h0; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsEqual_T_102 = 32'h0; // @[PMP.scala:60:27] wire [31:0] _res_hit_lsbsLess_T_100 = 32'h0; // @[PMP.scala:60:36] wire [31:0] _res_hit_lsbsLess_T_103 = 32'h0; // @[PMP.scala:60:27] wire [31:0] _res_aligned_straddlesLowerBound_T_120 = 32'h0; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesLowerBound_T_123 = 32'h0; // @[PMP.scala:60:27] wire [31:0] _res_aligned_straddlesLowerBound_T_127 = 32'h0; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesLowerBound_T_130 = 32'h0; // @[PMP.scala:60:27] wire _pmp0_WIRE_cfg_l = 1'h0; // @[PMP.scala:157:35] wire _pmp0_WIRE_cfg_x = 1'h0; // @[PMP.scala:157:35] wire _pmp0_WIRE_cfg_w = 1'h0; // @[PMP.scala:157:35] wire _pmp0_WIRE_cfg_r = 1'h0; // @[PMP.scala:157:35] wire pmp0_cfg_l = 1'h0; // @[PMP.scala:157:22] wire res_hit_msbsLess_14 = 1'h0; // @[PMP.scala:80:39] wire res_hit_lsbsLess_14 = 1'h0; // @[PMP.scala:82:53] wire _res_hit_T_97 = 1'h0; // @[PMP.scala:83:30] wire _res_hit_T_98 = 1'h0; // @[PMP.scala:83:16] wire _res_aligned_straddlesLowerBound_T_135 = 1'h0; // @[PMP.scala:123:147] wire res_aligned_straddlesLowerBound_7 = 1'h0; // @[PMP.scala:123:90] wire [12:0] _res_hit_lsbMask_T = 13'h3F; // @[package.scala:243:71] wire [12:0] _res_hit_T_3 = 13'h3F; // @[package.scala:243:71] wire [12:0] _res_aligned_lsbMask_T = 13'h3F; // @[package.scala:243:71] wire [12:0] _res_hit_lsbMask_T_3 = 13'h3F; // @[package.scala:243:71] wire [12:0] _res_hit_T_16 = 13'h3F; // @[package.scala:243:71] wire [12:0] _res_aligned_lsbMask_T_2 = 13'h3F; // @[package.scala:243:71] wire [12:0] _res_hit_lsbMask_T_6 = 13'h3F; // @[package.scala:243:71] wire [12:0] _res_hit_T_29 = 13'h3F; // @[package.scala:243:71] wire [12:0] _res_aligned_lsbMask_T_4 = 13'h3F; // @[package.scala:243:71] wire [12:0] _res_hit_lsbMask_T_9 = 13'h3F; // @[package.scala:243:71] wire [12:0] _res_hit_T_42 = 13'h3F; // @[package.scala:243:71] wire [12:0] _res_aligned_lsbMask_T_6 = 13'h3F; // @[package.scala:243:71] wire [12:0] _res_hit_lsbMask_T_12 = 13'h3F; // @[package.scala:243:71] wire [12:0] _res_hit_T_55 = 13'h3F; // @[package.scala:243:71] wire [12:0] _res_aligned_lsbMask_T_8 = 13'h3F; // @[package.scala:243:71] wire [12:0] _res_hit_lsbMask_T_15 = 13'h3F; // @[package.scala:243:71] wire [12:0] _res_hit_T_68 = 13'h3F; // @[package.scala:243:71] wire [12:0] _res_aligned_lsbMask_T_10 = 13'h3F; // @[package.scala:243:71] wire [12:0] _res_hit_lsbMask_T_18 = 13'h3F; // @[package.scala:243:71] wire [12:0] _res_hit_T_81 = 13'h3F; // @[package.scala:243:71] wire [12:0] _res_aligned_lsbMask_T_12 = 13'h3F; // @[package.scala:243:71] wire [12:0] _res_hit_lsbMask_T_21 = 13'h3F; // @[package.scala:243:71] wire [12:0] _res_hit_T_94 = 13'h3F; // @[package.scala:243:71] wire [12:0] _res_aligned_lsbMask_T_14 = 13'h3F; // @[package.scala:243:71] wire [5:0] _res_hit_lsbMask_T_1 = 6'h3F; // @[package.scala:243:76] wire [5:0] _res_hit_T_4 = 6'h3F; // @[package.scala:243:76] wire [5:0] _res_aligned_lsbMask_T_1 = 6'h3F; // @[package.scala:243:76] wire [5:0] _res_hit_lsbMask_T_4 = 6'h3F; // @[package.scala:243:76] wire [5:0] _res_hit_T_17 = 6'h3F; // @[package.scala:243:76] wire [5:0] _res_aligned_lsbMask_T_3 = 6'h3F; // @[package.scala:243:76] wire [5:0] _res_hit_lsbMask_T_7 = 6'h3F; // @[package.scala:243:76] wire [5:0] _res_hit_T_30 = 6'h3F; // @[package.scala:243:76] wire [5:0] _res_aligned_lsbMask_T_5 = 6'h3F; // @[package.scala:243:76] wire [5:0] _res_hit_lsbMask_T_10 = 6'h3F; // @[package.scala:243:76] wire [5:0] _res_hit_T_43 = 6'h3F; // @[package.scala:243:76] wire [5:0] _res_aligned_lsbMask_T_7 = 6'h3F; // @[package.scala:243:76] wire [5:0] _res_hit_lsbMask_T_13 = 6'h3F; // @[package.scala:243:76] wire [5:0] _res_hit_T_56 = 6'h3F; // @[package.scala:243:76] wire [5:0] _res_aligned_lsbMask_T_9 = 6'h3F; // @[package.scala:243:76] wire [5:0] _res_hit_lsbMask_T_16 = 6'h3F; // @[package.scala:243:76] wire [5:0] _res_hit_T_69 = 6'h3F; // @[package.scala:243:76] wire [5:0] _res_aligned_lsbMask_T_11 = 6'h3F; // @[package.scala:243:76] wire [5:0] _res_hit_lsbMask_T_19 = 6'h3F; // @[package.scala:243:76] wire [5:0] _res_hit_T_82 = 6'h3F; // @[package.scala:243:76] wire [5:0] _res_aligned_lsbMask_T_13 = 6'h3F; // @[package.scala:243:76] wire [5:0] _res_hit_lsbMask_T_22 = 6'h3F; // @[package.scala:243:76] wire [5:0] _res_hit_T_95 = 6'h3F; // @[package.scala:243:76] wire [5:0] _res_aligned_lsbMask_T_15 = 6'h3F; // @[package.scala:243:76] wire [5:0] _res_hit_lsbMask_T_2 = 6'h0; // @[package.scala:243:46] wire [5:0] _res_hit_T_5 = 6'h0; // @[package.scala:243:46] wire [5:0] res_aligned_lsbMask = 6'h0; // @[package.scala:243:46] wire [5:0] _res_aligned_pow2Aligned_T_2 = 6'h0; // @[PMP.scala:126:32] wire [5:0] _res_hit_lsbMask_T_5 = 6'h0; // @[package.scala:243:46] wire [5:0] _res_hit_T_18 = 6'h0; // @[package.scala:243:46] wire [5:0] res_aligned_lsbMask_1 = 6'h0; // @[package.scala:243:46] wire [5:0] _res_aligned_pow2Aligned_T_5 = 6'h0; // @[PMP.scala:126:32] wire [5:0] _res_hit_lsbMask_T_8 = 6'h0; // @[package.scala:243:46] wire [5:0] _res_hit_T_31 = 6'h0; // @[package.scala:243:46] wire [5:0] res_aligned_lsbMask_2 = 6'h0; // @[package.scala:243:46] wire [5:0] _res_aligned_pow2Aligned_T_8 = 6'h0; // @[PMP.scala:126:32] wire [5:0] _res_hit_lsbMask_T_11 = 6'h0; // @[package.scala:243:46] wire [5:0] _res_hit_T_44 = 6'h0; // @[package.scala:243:46] wire [5:0] res_aligned_lsbMask_3 = 6'h0; // @[package.scala:243:46] wire [5:0] _res_aligned_pow2Aligned_T_11 = 6'h0; // @[PMP.scala:126:32] wire [5:0] _res_hit_lsbMask_T_14 = 6'h0; // @[package.scala:243:46] wire [5:0] _res_hit_T_57 = 6'h0; // @[package.scala:243:46] wire [5:0] res_aligned_lsbMask_4 = 6'h0; // @[package.scala:243:46] wire [5:0] _res_aligned_pow2Aligned_T_14 = 6'h0; // @[PMP.scala:126:32] wire [5:0] _res_hit_lsbMask_T_17 = 6'h0; // @[package.scala:243:46] wire [5:0] _res_hit_T_70 = 6'h0; // @[package.scala:243:46] wire [5:0] res_aligned_lsbMask_5 = 6'h0; // @[package.scala:243:46] wire [5:0] _res_aligned_pow2Aligned_T_17 = 6'h0; // @[PMP.scala:126:32] wire [5:0] _res_hit_lsbMask_T_20 = 6'h0; // @[package.scala:243:46] wire [5:0] _res_hit_T_83 = 6'h0; // @[package.scala:243:46] wire [5:0] res_aligned_lsbMask_6 = 6'h0; // @[package.scala:243:46] wire [5:0] _res_aligned_pow2Aligned_T_20 = 6'h0; // @[PMP.scala:126:32] wire [5:0] _res_hit_lsbMask_T_23 = 6'h0; // @[package.scala:243:46] wire [5:0] _res_hit_T_96 = 6'h0; // @[package.scala:243:46] wire [5:0] _res_hit_lsbsLess_T_104 = 6'h0; // @[PMP.scala:82:64] wire [5:0] res_aligned_lsbMask_7 = 6'h0; // @[package.scala:243:46] wire [5:0] _res_aligned_straddlesLowerBound_T_131 = 6'h0; // @[PMP.scala:123:108] wire [5:0] _res_aligned_straddlesLowerBound_T_134 = 6'h0; // @[PMP.scala:123:125] wire [5:0] _res_aligned_pow2Aligned_T_23 = 6'h0; // @[PMP.scala:126:32] wire res_aligned_pow2Aligned = 1'h1; // @[PMP.scala:126:57] wire res_aligned_pow2Aligned_1 = 1'h1; // @[PMP.scala:126:57] wire res_aligned_pow2Aligned_2 = 1'h1; // @[PMP.scala:126:57] wire res_aligned_pow2Aligned_3 = 1'h1; // @[PMP.scala:126:57] wire res_aligned_pow2Aligned_4 = 1'h1; // @[PMP.scala:126:57] wire res_aligned_pow2Aligned_5 = 1'h1; // @[PMP.scala:126:57] wire res_aligned_pow2Aligned_6 = 1'h1; // @[PMP.scala:126:57] wire _res_hit_T_99 = 1'h1; // @[PMP.scala:88:5] wire res_aligned_pow2Aligned_7 = 1'h1; // @[PMP.scala:126:57] wire [2:0] io_size = 3'h0; // @[PMP.scala:143:7, :146:14] wire [1:0] io_pmp_0_cfg_res = 2'h0; // @[PMP.scala:143:7] wire [1:0] io_pmp_1_cfg_res = 2'h0; // @[PMP.scala:143:7] wire [1:0] io_pmp_2_cfg_res = 2'h0; // @[PMP.scala:143:7] wire [1:0] io_pmp_3_cfg_res = 2'h0; // @[PMP.scala:143:7] wire [1:0] io_pmp_4_cfg_res = 2'h0; // @[PMP.scala:143:7] wire [1:0] io_pmp_5_cfg_res = 2'h0; // @[PMP.scala:143:7] wire [1:0] io_pmp_6_cfg_res = 2'h0; // @[PMP.scala:143:7] wire [1:0] io_pmp_7_cfg_res = 2'h0; // @[PMP.scala:143:7] wire [1:0] _pmp0_WIRE_cfg_res = 2'h0; // @[PMP.scala:157:35] wire [1:0] _pmp0_WIRE_cfg_a = 2'h0; // @[PMP.scala:157:35] wire [1:0] pmp0_cfg_res = 2'h0; // @[PMP.scala:157:22] wire [1:0] pmp0_cfg_a = 2'h0; // @[PMP.scala:157:22] wire [1:0] res_cur_cfg_res = 2'h0; // @[PMP.scala:181:23] wire [1:0] _res_T_44_cfg_res = 2'h0; // @[PMP.scala:185:8] wire [1:0] res_cur_1_cfg_res = 2'h0; // @[PMP.scala:181:23] wire [1:0] _res_T_89_cfg_res = 2'h0; // @[PMP.scala:185:8] wire [1:0] res_cur_2_cfg_res = 2'h0; // @[PMP.scala:181:23] wire [1:0] _res_T_134_cfg_res = 2'h0; // @[PMP.scala:185:8] wire [1:0] res_cur_3_cfg_res = 2'h0; // @[PMP.scala:181:23] wire [1:0] _res_T_179_cfg_res = 2'h0; // @[PMP.scala:185:8] wire [1:0] res_cur_4_cfg_res = 2'h0; // @[PMP.scala:181:23] wire [1:0] _res_T_224_cfg_res = 2'h0; // @[PMP.scala:185:8] wire [1:0] res_cur_5_cfg_res = 2'h0; // @[PMP.scala:181:23] wire [1:0] _res_T_269_cfg_res = 2'h0; // @[PMP.scala:185:8] wire [1:0] res_cur_6_cfg_res = 2'h0; // @[PMP.scala:181:23] wire [1:0] _res_T_314_cfg_res = 2'h0; // @[PMP.scala:185:8] wire [1:0] res_cur_7_cfg_res = 2'h0; // @[PMP.scala:181:23] wire [1:0] res_cfg_res = 2'h0; // @[PMP.scala:185:8] wire _res_T_319 = io_pmp_0_cfg_l_0; // @[PMP.scala:143:7, :170:30] wire res_cur_7_cfg_l = io_pmp_0_cfg_l_0; // @[PMP.scala:143:7, :181:23] wire [1:0] res_cur_7_cfg_a = io_pmp_0_cfg_a_0; // @[PMP.scala:143:7, :181:23] wire [29:0] res_cur_7_addr = io_pmp_0_addr_0; // @[PMP.scala:143:7, :181:23] wire [31:0] res_hit_lsbMask_7 = io_pmp_0_mask_0; // @[PMP.scala:68:26, :143:7] wire [31:0] res_cur_7_mask = io_pmp_0_mask_0; // @[PMP.scala:143:7, :181:23] wire _res_T_274 = io_pmp_1_cfg_l_0; // @[PMP.scala:143:7, :170:30] wire res_cur_6_cfg_l = io_pmp_1_cfg_l_0; // @[PMP.scala:143:7, :181:23] wire [1:0] res_cur_6_cfg_a = io_pmp_1_cfg_a_0; // @[PMP.scala:143:7, :181:23] wire [29:0] res_cur_6_addr = io_pmp_1_addr_0; // @[PMP.scala:143:7, :181:23] wire [31:0] res_hit_lsbMask_6 = io_pmp_1_mask_0; // @[PMP.scala:68:26, :143:7] wire [31:0] res_cur_6_mask = io_pmp_1_mask_0; // @[PMP.scala:143:7, :181:23] wire _res_T_229 = io_pmp_2_cfg_l_0; // @[PMP.scala:143:7, :170:30] wire res_cur_5_cfg_l = io_pmp_2_cfg_l_0; // @[PMP.scala:143:7, :181:23] wire [1:0] res_cur_5_cfg_a = io_pmp_2_cfg_a_0; // @[PMP.scala:143:7, :181:23] wire [29:0] res_cur_5_addr = io_pmp_2_addr_0; // @[PMP.scala:143:7, :181:23] wire [31:0] res_hit_lsbMask_5 = io_pmp_2_mask_0; // @[PMP.scala:68:26, :143:7] wire [31:0] res_cur_5_mask = io_pmp_2_mask_0; // @[PMP.scala:143:7, :181:23] wire _res_T_184 = io_pmp_3_cfg_l_0; // @[PMP.scala:143:7, :170:30] wire res_cur_4_cfg_l = io_pmp_3_cfg_l_0; // @[PMP.scala:143:7, :181:23] wire [1:0] res_cur_4_cfg_a = io_pmp_3_cfg_a_0; // @[PMP.scala:143:7, :181:23] wire [29:0] res_cur_4_addr = io_pmp_3_addr_0; // @[PMP.scala:143:7, :181:23] wire [31:0] res_hit_lsbMask_4 = io_pmp_3_mask_0; // @[PMP.scala:68:26, :143:7] wire [31:0] res_cur_4_mask = io_pmp_3_mask_0; // @[PMP.scala:143:7, :181:23] wire _res_T_139 = io_pmp_4_cfg_l_0; // @[PMP.scala:143:7, :170:30] wire res_cur_3_cfg_l = io_pmp_4_cfg_l_0; // @[PMP.scala:143:7, :181:23] wire [1:0] res_cur_3_cfg_a = io_pmp_4_cfg_a_0; // @[PMP.scala:143:7, :181:23] wire [29:0] res_cur_3_addr = io_pmp_4_addr_0; // @[PMP.scala:143:7, :181:23] wire [31:0] res_hit_lsbMask_3 = io_pmp_4_mask_0; // @[PMP.scala:68:26, :143:7] wire [31:0] res_cur_3_mask = io_pmp_4_mask_0; // @[PMP.scala:143:7, :181:23] wire _res_T_94 = io_pmp_5_cfg_l_0; // @[PMP.scala:143:7, :170:30] wire res_cur_2_cfg_l = io_pmp_5_cfg_l_0; // @[PMP.scala:143:7, :181:23] wire [1:0] res_cur_2_cfg_a = io_pmp_5_cfg_a_0; // @[PMP.scala:143:7, :181:23] wire [29:0] res_cur_2_addr = io_pmp_5_addr_0; // @[PMP.scala:143:7, :181:23] wire [31:0] res_hit_lsbMask_2 = io_pmp_5_mask_0; // @[PMP.scala:68:26, :143:7] wire [31:0] res_cur_2_mask = io_pmp_5_mask_0; // @[PMP.scala:143:7, :181:23] wire _res_T_49 = io_pmp_6_cfg_l_0; // @[PMP.scala:143:7, :170:30] wire res_cur_1_cfg_l = io_pmp_6_cfg_l_0; // @[PMP.scala:143:7, :181:23] wire [1:0] res_cur_1_cfg_a = io_pmp_6_cfg_a_0; // @[PMP.scala:143:7, :181:23] wire [29:0] res_cur_1_addr = io_pmp_6_addr_0; // @[PMP.scala:143:7, :181:23] wire [31:0] res_hit_lsbMask_1 = io_pmp_6_mask_0; // @[PMP.scala:68:26, :143:7] wire [31:0] res_cur_1_mask = io_pmp_6_mask_0; // @[PMP.scala:143:7, :181:23] wire _res_T_4 = io_pmp_7_cfg_l_0; // @[PMP.scala:143:7, :170:30] wire res_cur_cfg_l = io_pmp_7_cfg_l_0; // @[PMP.scala:143:7, :181:23] wire [1:0] res_cur_cfg_a = io_pmp_7_cfg_a_0; // @[PMP.scala:143:7, :181:23] wire [29:0] res_cur_addr = io_pmp_7_addr_0; // @[PMP.scala:143:7, :181:23] wire [31:0] res_hit_lsbMask = io_pmp_7_mask_0; // @[PMP.scala:68:26, :143:7] wire [31:0] res_cur_mask = io_pmp_7_mask_0; // @[PMP.scala:143:7, :181:23] wire res_cfg_r; // @[PMP.scala:185:8] wire res_cfg_w; // @[PMP.scala:185:8] wire res_cfg_x; // @[PMP.scala:185:8] wire io_r_0; // @[PMP.scala:143:7] wire io_w_0; // @[PMP.scala:143:7] wire io_x_0; // @[PMP.scala:143:7] wire default_0 = io_prv_0[1]; // @[PMP.scala:143:7, :156:56] wire pmp0_cfg_x = default_0; // @[PMP.scala:156:56, :157:22] wire pmp0_cfg_w = default_0; // @[PMP.scala:156:56, :157:22] wire pmp0_cfg_r = default_0; // @[PMP.scala:156:56, :157:22] wire _res_hit_T = io_pmp_7_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7] wire _res_aligned_T = io_pmp_7_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7] wire [25:0] _res_hit_msbMatch_T_6 = io_pmp_7_mask_0[31:6]; // @[PMP.scala:68:26, :69:72, :143:7] wire [5:0] _res_aligned_pow2Aligned_T = io_pmp_7_mask_0[5:0]; // @[PMP.scala:68:26, :126:39, :143:7] wire [25:0] _res_hit_msbMatch_T = io_addr_0[31:6]; // @[PMP.scala:69:29, :143:7] wire [25:0] _res_hit_msbsLess_T = io_addr_0[31:6]; // @[PMP.scala:69:29, :80:25, :143:7] wire [25:0] _res_hit_msbsEqual_T = io_addr_0[31:6]; // @[PMP.scala:69:29, :81:27, :143:7] wire [25:0] _res_hit_msbsLess_T_6 = io_addr_0[31:6]; // @[PMP.scala:69:29, :80:25, :143:7] wire [25:0] _res_hit_msbsEqual_T_7 = io_addr_0[31:6]; // @[PMP.scala:69:29, :81:27, :143:7] wire [25:0] _res_aligned_straddlesLowerBound_T = io_addr_0[31:6]; // @[PMP.scala:69:29, :123:35, :143:7] wire [25:0] _res_aligned_straddlesUpperBound_T = io_addr_0[31:6]; // @[PMP.scala:69:29, :124:35, :143:7] wire [25:0] _res_hit_msbMatch_T_10 = io_addr_0[31:6]; // @[PMP.scala:69:29, :143:7] wire [25:0] _res_hit_msbsLess_T_12 = io_addr_0[31:6]; // @[PMP.scala:69:29, :80:25, :143:7] wire [25:0] _res_hit_msbsEqual_T_14 = io_addr_0[31:6]; // @[PMP.scala:69:29, :81:27, :143:7] wire [25:0] _res_hit_msbsLess_T_18 = io_addr_0[31:6]; // @[PMP.scala:69:29, :80:25, :143:7] wire [25:0] _res_hit_msbsEqual_T_21 = io_addr_0[31:6]; // @[PMP.scala:69:29, :81:27, :143:7] wire [25:0] _res_aligned_straddlesLowerBound_T_17 = io_addr_0[31:6]; // @[PMP.scala:69:29, :123:35, :143:7] wire [25:0] _res_aligned_straddlesUpperBound_T_17 = io_addr_0[31:6]; // @[PMP.scala:69:29, :124:35, :143:7] wire [25:0] _res_hit_msbMatch_T_20 = io_addr_0[31:6]; // @[PMP.scala:69:29, :143:7] wire [25:0] _res_hit_msbsLess_T_24 = io_addr_0[31:6]; // @[PMP.scala:69:29, :80:25, :143:7] wire [25:0] _res_hit_msbsEqual_T_28 = io_addr_0[31:6]; // @[PMP.scala:69:29, :81:27, :143:7] wire [25:0] _res_hit_msbsLess_T_30 = io_addr_0[31:6]; // @[PMP.scala:69:29, :80:25, :143:7] wire [25:0] _res_hit_msbsEqual_T_35 = io_addr_0[31:6]; // @[PMP.scala:69:29, :81:27, :143:7] wire [25:0] _res_aligned_straddlesLowerBound_T_34 = io_addr_0[31:6]; // @[PMP.scala:69:29, :123:35, :143:7] wire [25:0] _res_aligned_straddlesUpperBound_T_34 = io_addr_0[31:6]; // @[PMP.scala:69:29, :124:35, :143:7] wire [25:0] _res_hit_msbMatch_T_30 = io_addr_0[31:6]; // @[PMP.scala:69:29, :143:7] wire [25:0] _res_hit_msbsLess_T_36 = io_addr_0[31:6]; // @[PMP.scala:69:29, :80:25, :143:7] wire [25:0] _res_hit_msbsEqual_T_42 = io_addr_0[31:6]; // @[PMP.scala:69:29, :81:27, :143:7] wire [25:0] _res_hit_msbsLess_T_42 = io_addr_0[31:6]; // @[PMP.scala:69:29, :80:25, :143:7] wire [25:0] _res_hit_msbsEqual_T_49 = io_addr_0[31:6]; // @[PMP.scala:69:29, :81:27, :143:7] wire [25:0] _res_aligned_straddlesLowerBound_T_51 = io_addr_0[31:6]; // @[PMP.scala:69:29, :123:35, :143:7] wire [25:0] _res_aligned_straddlesUpperBound_T_51 = io_addr_0[31:6]; // @[PMP.scala:69:29, :124:35, :143:7] wire [25:0] _res_hit_msbMatch_T_40 = io_addr_0[31:6]; // @[PMP.scala:69:29, :143:7] wire [25:0] _res_hit_msbsLess_T_48 = io_addr_0[31:6]; // @[PMP.scala:69:29, :80:25, :143:7] wire [25:0] _res_hit_msbsEqual_T_56 = io_addr_0[31:6]; // @[PMP.scala:69:29, :81:27, :143:7] wire [25:0] _res_hit_msbsLess_T_54 = io_addr_0[31:6]; // @[PMP.scala:69:29, :80:25, :143:7] wire [25:0] _res_hit_msbsEqual_T_63 = io_addr_0[31:6]; // @[PMP.scala:69:29, :81:27, :143:7] wire [25:0] _res_aligned_straddlesLowerBound_T_68 = io_addr_0[31:6]; // @[PMP.scala:69:29, :123:35, :143:7] wire [25:0] _res_aligned_straddlesUpperBound_T_68 = io_addr_0[31:6]; // @[PMP.scala:69:29, :124:35, :143:7] wire [25:0] _res_hit_msbMatch_T_50 = io_addr_0[31:6]; // @[PMP.scala:69:29, :143:7] wire [25:0] _res_hit_msbsLess_T_60 = io_addr_0[31:6]; // @[PMP.scala:69:29, :80:25, :143:7] wire [25:0] _res_hit_msbsEqual_T_70 = io_addr_0[31:6]; // @[PMP.scala:69:29, :81:27, :143:7] wire [25:0] _res_hit_msbsLess_T_66 = io_addr_0[31:6]; // @[PMP.scala:69:29, :80:25, :143:7] wire [25:0] _res_hit_msbsEqual_T_77 = io_addr_0[31:6]; // @[PMP.scala:69:29, :81:27, :143:7] wire [25:0] _res_aligned_straddlesLowerBound_T_85 = io_addr_0[31:6]; // @[PMP.scala:69:29, :123:35, :143:7] wire [25:0] _res_aligned_straddlesUpperBound_T_85 = io_addr_0[31:6]; // @[PMP.scala:69:29, :124:35, :143:7] wire [25:0] _res_hit_msbMatch_T_60 = io_addr_0[31:6]; // @[PMP.scala:69:29, :143:7] wire [25:0] _res_hit_msbsLess_T_72 = io_addr_0[31:6]; // @[PMP.scala:69:29, :80:25, :143:7] wire [25:0] _res_hit_msbsEqual_T_84 = io_addr_0[31:6]; // @[PMP.scala:69:29, :81:27, :143:7] wire [25:0] _res_hit_msbsLess_T_78 = io_addr_0[31:6]; // @[PMP.scala:69:29, :80:25, :143:7] wire [25:0] _res_hit_msbsEqual_T_91 = io_addr_0[31:6]; // @[PMP.scala:69:29, :81:27, :143:7] wire [25:0] _res_aligned_straddlesLowerBound_T_102 = io_addr_0[31:6]; // @[PMP.scala:69:29, :123:35, :143:7] wire [25:0] _res_aligned_straddlesUpperBound_T_102 = io_addr_0[31:6]; // @[PMP.scala:69:29, :124:35, :143:7] wire [25:0] _res_hit_msbMatch_T_70 = io_addr_0[31:6]; // @[PMP.scala:69:29, :143:7] wire [25:0] _res_hit_msbsLess_T_84 = io_addr_0[31:6]; // @[PMP.scala:69:29, :80:25, :143:7] wire [25:0] _res_hit_msbsEqual_T_98 = io_addr_0[31:6]; // @[PMP.scala:69:29, :81:27, :143:7] wire [25:0] _res_hit_msbsLess_T_90 = io_addr_0[31:6]; // @[PMP.scala:69:29, :80:25, :143:7] wire [25:0] _res_hit_msbsEqual_T_105 = io_addr_0[31:6]; // @[PMP.scala:69:29, :81:27, :143:7] wire [25:0] _res_aligned_straddlesLowerBound_T_119 = io_addr_0[31:6]; // @[PMP.scala:69:29, :123:35, :143:7] wire [25:0] _res_aligned_straddlesUpperBound_T_119 = io_addr_0[31:6]; // @[PMP.scala:69:29, :124:35, :143:7] wire [31:0] _GEN = {io_pmp_7_addr_0, 2'h0}; // @[PMP.scala:60:36, :143:7] wire [31:0] _res_hit_msbMatch_T_1; // @[PMP.scala:60:36] assign _res_hit_msbMatch_T_1 = _GEN; // @[PMP.scala:60:36] wire [31:0] _res_hit_lsbMatch_T_1; // @[PMP.scala:60:36] assign _res_hit_lsbMatch_T_1 = _GEN; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsLess_T_7; // @[PMP.scala:60:36] assign _res_hit_msbsLess_T_7 = _GEN; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsEqual_T_8; // @[PMP.scala:60:36] assign _res_hit_msbsEqual_T_8 = _GEN; // @[PMP.scala:60:36] wire [31:0] _res_hit_lsbsLess_T_9; // @[PMP.scala:60:36] assign _res_hit_lsbsLess_T_9 = _GEN; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesUpperBound_T_1; // @[PMP.scala:60:36] assign _res_aligned_straddlesUpperBound_T_1 = _GEN; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesUpperBound_T_8; // @[PMP.scala:60:36] assign _res_aligned_straddlesUpperBound_T_8 = _GEN; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbMatch_T_2 = ~_res_hit_msbMatch_T_1; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbMatch_T_3 = {_res_hit_msbMatch_T_2[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbMatch_T_4 = ~_res_hit_msbMatch_T_3; // @[PMP.scala:60:{27,48}] wire [25:0] _res_hit_msbMatch_T_5 = _res_hit_msbMatch_T_4[31:6]; // @[PMP.scala:60:27, :69:53] wire [25:0] _res_hit_msbMatch_T_7 = _res_hit_msbMatch_T ^ _res_hit_msbMatch_T_5; // @[PMP.scala:63:47, :69:{29,53}] wire [25:0] _res_hit_msbMatch_T_8 = ~_res_hit_msbMatch_T_6; // @[PMP.scala:63:54, :69:72] wire [25:0] _res_hit_msbMatch_T_9 = _res_hit_msbMatch_T_7 & _res_hit_msbMatch_T_8; // @[PMP.scala:63:{47,52,54}] wire res_hit_msbMatch = _res_hit_msbMatch_T_9 == 26'h0; // @[PMP.scala:63:{52,58}, :80:52, :81:54, :123:67] wire [5:0] _res_hit_lsbMatch_T = io_addr_0[5:0]; // @[PMP.scala:70:28, :143:7] wire [5:0] _res_hit_lsbsLess_T = io_addr_0[5:0]; // @[PMP.scala:70:28, :82:25, :143:7] wire [5:0] _res_hit_lsbsLess_T_7 = io_addr_0[5:0]; // @[PMP.scala:70:28, :82:25, :143:7] wire [5:0] _res_aligned_straddlesLowerBound_T_13 = io_addr_0[5:0]; // @[PMP.scala:70:28, :123:129, :143:7] wire [5:0] _res_aligned_straddlesUpperBound_T_13 = io_addr_0[5:0]; // @[PMP.scala:70:28, :124:119, :143:7] wire [5:0] _res_hit_lsbMatch_T_10 = io_addr_0[5:0]; // @[PMP.scala:70:28, :143:7] wire [5:0] _res_hit_lsbsLess_T_14 = io_addr_0[5:0]; // @[PMP.scala:70:28, :82:25, :143:7] wire [5:0] _res_hit_lsbsLess_T_21 = io_addr_0[5:0]; // @[PMP.scala:70:28, :82:25, :143:7] wire [5:0] _res_aligned_straddlesLowerBound_T_30 = io_addr_0[5:0]; // @[PMP.scala:70:28, :123:129, :143:7] wire [5:0] _res_aligned_straddlesUpperBound_T_30 = io_addr_0[5:0]; // @[PMP.scala:70:28, :124:119, :143:7] wire [5:0] _res_hit_lsbMatch_T_20 = io_addr_0[5:0]; // @[PMP.scala:70:28, :143:7] wire [5:0] _res_hit_lsbsLess_T_28 = io_addr_0[5:0]; // @[PMP.scala:70:28, :82:25, :143:7] wire [5:0] _res_hit_lsbsLess_T_35 = io_addr_0[5:0]; // @[PMP.scala:70:28, :82:25, :143:7] wire [5:0] _res_aligned_straddlesLowerBound_T_47 = io_addr_0[5:0]; // @[PMP.scala:70:28, :123:129, :143:7] wire [5:0] _res_aligned_straddlesUpperBound_T_47 = io_addr_0[5:0]; // @[PMP.scala:70:28, :124:119, :143:7] wire [5:0] _res_hit_lsbMatch_T_30 = io_addr_0[5:0]; // @[PMP.scala:70:28, :143:7] wire [5:0] _res_hit_lsbsLess_T_42 = io_addr_0[5:0]; // @[PMP.scala:70:28, :82:25, :143:7] wire [5:0] _res_hit_lsbsLess_T_49 = io_addr_0[5:0]; // @[PMP.scala:70:28, :82:25, :143:7] wire [5:0] _res_aligned_straddlesLowerBound_T_64 = io_addr_0[5:0]; // @[PMP.scala:70:28, :123:129, :143:7] wire [5:0] _res_aligned_straddlesUpperBound_T_64 = io_addr_0[5:0]; // @[PMP.scala:70:28, :124:119, :143:7] wire [5:0] _res_hit_lsbMatch_T_40 = io_addr_0[5:0]; // @[PMP.scala:70:28, :143:7] wire [5:0] _res_hit_lsbsLess_T_56 = io_addr_0[5:0]; // @[PMP.scala:70:28, :82:25, :143:7] wire [5:0] _res_hit_lsbsLess_T_63 = io_addr_0[5:0]; // @[PMP.scala:70:28, :82:25, :143:7] wire [5:0] _res_aligned_straddlesLowerBound_T_81 = io_addr_0[5:0]; // @[PMP.scala:70:28, :123:129, :143:7] wire [5:0] _res_aligned_straddlesUpperBound_T_81 = io_addr_0[5:0]; // @[PMP.scala:70:28, :124:119, :143:7] wire [5:0] _res_hit_lsbMatch_T_50 = io_addr_0[5:0]; // @[PMP.scala:70:28, :143:7] wire [5:0] _res_hit_lsbsLess_T_70 = io_addr_0[5:0]; // @[PMP.scala:70:28, :82:25, :143:7] wire [5:0] _res_hit_lsbsLess_T_77 = io_addr_0[5:0]; // @[PMP.scala:70:28, :82:25, :143:7] wire [5:0] _res_aligned_straddlesLowerBound_T_98 = io_addr_0[5:0]; // @[PMP.scala:70:28, :123:129, :143:7] wire [5:0] _res_aligned_straddlesUpperBound_T_98 = io_addr_0[5:0]; // @[PMP.scala:70:28, :124:119, :143:7] wire [5:0] _res_hit_lsbMatch_T_60 = io_addr_0[5:0]; // @[PMP.scala:70:28, :143:7] wire [5:0] _res_hit_lsbsLess_T_84 = io_addr_0[5:0]; // @[PMP.scala:70:28, :82:25, :143:7] wire [5:0] _res_hit_lsbsLess_T_91 = io_addr_0[5:0]; // @[PMP.scala:70:28, :82:25, :143:7] wire [5:0] _res_aligned_straddlesLowerBound_T_115 = io_addr_0[5:0]; // @[PMP.scala:70:28, :123:129, :143:7] wire [5:0] _res_aligned_straddlesUpperBound_T_115 = io_addr_0[5:0]; // @[PMP.scala:70:28, :124:119, :143:7] wire [5:0] _res_hit_lsbMatch_T_70 = io_addr_0[5:0]; // @[PMP.scala:70:28, :143:7] wire [5:0] _res_hit_lsbsLess_T_98 = io_addr_0[5:0]; // @[PMP.scala:70:28, :82:25, :143:7] wire [5:0] _res_hit_lsbsLess_T_105 = io_addr_0[5:0]; // @[PMP.scala:70:28, :82:25, :143:7] wire [5:0] _res_aligned_straddlesLowerBound_T_132 = io_addr_0[5:0]; // @[PMP.scala:70:28, :123:129, :143:7] wire [5:0] _res_aligned_straddlesUpperBound_T_132 = io_addr_0[5:0]; // @[PMP.scala:70:28, :124:119, :143:7] wire [31:0] _res_hit_lsbMatch_T_2 = ~_res_hit_lsbMatch_T_1; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_lsbMatch_T_3 = {_res_hit_lsbMatch_T_2[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbMatch_T_4 = ~_res_hit_lsbMatch_T_3; // @[PMP.scala:60:{27,48}] wire [5:0] _res_hit_lsbMatch_T_5 = _res_hit_lsbMatch_T_4[5:0]; // @[PMP.scala:60:27, :70:55] wire [5:0] _res_hit_lsbMatch_T_6 = res_hit_lsbMask[5:0]; // @[PMP.scala:68:26, :70:80] wire [5:0] _res_hit_lsbMatch_T_7 = _res_hit_lsbMatch_T ^ _res_hit_lsbMatch_T_5; // @[PMP.scala:63:47, :70:{28,55}] wire [5:0] _res_hit_lsbMatch_T_8 = ~_res_hit_lsbMatch_T_6; // @[PMP.scala:63:54, :70:80] wire [5:0] _res_hit_lsbMatch_T_9 = _res_hit_lsbMatch_T_7 & _res_hit_lsbMatch_T_8; // @[PMP.scala:63:{47,52,54}] wire res_hit_lsbMatch = _res_hit_lsbMatch_T_9 == 6'h0; // @[PMP.scala:63:{52,58}] wire _res_hit_T_1 = res_hit_msbMatch & res_hit_lsbMatch; // @[PMP.scala:63:58, :71:16] wire _res_hit_T_2 = io_pmp_7_cfg_a_0[0]; // @[PMP.scala:46:26, :143:7] wire [31:0] _GEN_0 = {io_pmp_6_addr_0, 2'h0}; // @[PMP.scala:60:36, :143:7] wire [31:0] _res_hit_msbsLess_T_1; // @[PMP.scala:60:36] assign _res_hit_msbsLess_T_1 = _GEN_0; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsEqual_T_1; // @[PMP.scala:60:36] assign _res_hit_msbsEqual_T_1 = _GEN_0; // @[PMP.scala:60:36] wire [31:0] _res_hit_lsbsLess_T_2; // @[PMP.scala:60:36] assign _res_hit_lsbsLess_T_2 = _GEN_0; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesLowerBound_T_1; // @[PMP.scala:60:36] assign _res_aligned_straddlesLowerBound_T_1 = _GEN_0; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesLowerBound_T_8; // @[PMP.scala:60:36] assign _res_aligned_straddlesLowerBound_T_8 = _GEN_0; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbMatch_T_11; // @[PMP.scala:60:36] assign _res_hit_msbMatch_T_11 = _GEN_0; // @[PMP.scala:60:36] wire [31:0] _res_hit_lsbMatch_T_11; // @[PMP.scala:60:36] assign _res_hit_lsbMatch_T_11 = _GEN_0; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsLess_T_19; // @[PMP.scala:60:36] assign _res_hit_msbsLess_T_19 = _GEN_0; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsEqual_T_22; // @[PMP.scala:60:36] assign _res_hit_msbsEqual_T_22 = _GEN_0; // @[PMP.scala:60:36] wire [31:0] _res_hit_lsbsLess_T_23; // @[PMP.scala:60:36] assign _res_hit_lsbsLess_T_23 = _GEN_0; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesUpperBound_T_18; // @[PMP.scala:60:36] assign _res_aligned_straddlesUpperBound_T_18 = _GEN_0; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesUpperBound_T_25; // @[PMP.scala:60:36] assign _res_aligned_straddlesUpperBound_T_25 = _GEN_0; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsLess_T_2 = ~_res_hit_msbsLess_T_1; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsLess_T_3 = {_res_hit_msbsLess_T_2[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsLess_T_4 = ~_res_hit_msbsLess_T_3; // @[PMP.scala:60:{27,48}] wire [25:0] _res_hit_msbsLess_T_5 = _res_hit_msbsLess_T_4[31:6]; // @[PMP.scala:60:27, :80:52] wire res_hit_msbsLess = _res_hit_msbsLess_T < _res_hit_msbsLess_T_5; // @[PMP.scala:80:{25,39,52}] wire [31:0] _res_hit_msbsEqual_T_2 = ~_res_hit_msbsEqual_T_1; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsEqual_T_3 = {_res_hit_msbsEqual_T_2[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsEqual_T_4 = ~_res_hit_msbsEqual_T_3; // @[PMP.scala:60:{27,48}] wire [25:0] _res_hit_msbsEqual_T_5 = _res_hit_msbsEqual_T_4[31:6]; // @[PMP.scala:60:27, :81:54] wire [25:0] _res_hit_msbsEqual_T_6 = _res_hit_msbsEqual_T ^ _res_hit_msbsEqual_T_5; // @[PMP.scala:81:{27,41,54}] wire res_hit_msbsEqual = _res_hit_msbsEqual_T_6 == 26'h0; // @[PMP.scala:80:52, :81:{41,54,69}, :123:67] wire [5:0] _res_hit_lsbsLess_T_1 = _res_hit_lsbsLess_T; // @[PMP.scala:82:{25,42}] wire [31:0] _res_hit_lsbsLess_T_3 = ~_res_hit_lsbsLess_T_2; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_lsbsLess_T_4 = {_res_hit_lsbsLess_T_3[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbsLess_T_5 = ~_res_hit_lsbsLess_T_4; // @[PMP.scala:60:{27,48}] wire [5:0] _res_hit_lsbsLess_T_6 = _res_hit_lsbsLess_T_5[5:0]; // @[PMP.scala:60:27, :82:64] wire res_hit_lsbsLess = _res_hit_lsbsLess_T_1 < _res_hit_lsbsLess_T_6; // @[PMP.scala:82:{42,53,64}] wire _res_hit_T_6 = res_hit_msbsEqual & res_hit_lsbsLess; // @[PMP.scala:81:69, :82:53, :83:30] wire _res_hit_T_7 = res_hit_msbsLess | _res_hit_T_6; // @[PMP.scala:80:39, :83:{16,30}] wire _res_hit_T_8 = ~_res_hit_T_7; // @[PMP.scala:83:16, :88:5] wire [31:0] _res_hit_msbsLess_T_8 = ~_res_hit_msbsLess_T_7; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsLess_T_9 = {_res_hit_msbsLess_T_8[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsLess_T_10 = ~_res_hit_msbsLess_T_9; // @[PMP.scala:60:{27,48}] wire [25:0] _res_hit_msbsLess_T_11 = _res_hit_msbsLess_T_10[31:6]; // @[PMP.scala:60:27, :80:52] wire res_hit_msbsLess_1 = _res_hit_msbsLess_T_6 < _res_hit_msbsLess_T_11; // @[PMP.scala:80:{25,39,52}] wire [31:0] _res_hit_msbsEqual_T_9 = ~_res_hit_msbsEqual_T_8; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsEqual_T_10 = {_res_hit_msbsEqual_T_9[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsEqual_T_11 = ~_res_hit_msbsEqual_T_10; // @[PMP.scala:60:{27,48}] wire [25:0] _res_hit_msbsEqual_T_12 = _res_hit_msbsEqual_T_11[31:6]; // @[PMP.scala:60:27, :81:54] wire [25:0] _res_hit_msbsEqual_T_13 = _res_hit_msbsEqual_T_7 ^ _res_hit_msbsEqual_T_12; // @[PMP.scala:81:{27,41,54}] wire res_hit_msbsEqual_1 = _res_hit_msbsEqual_T_13 == 26'h0; // @[PMP.scala:80:52, :81:{41,54,69}, :123:67] wire [5:0] _res_hit_lsbsLess_T_8 = _res_hit_lsbsLess_T_7; // @[PMP.scala:82:{25,42}] wire [31:0] _res_hit_lsbsLess_T_10 = ~_res_hit_lsbsLess_T_9; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_lsbsLess_T_11 = {_res_hit_lsbsLess_T_10[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbsLess_T_12 = ~_res_hit_lsbsLess_T_11; // @[PMP.scala:60:{27,48}] wire [5:0] _res_hit_lsbsLess_T_13 = _res_hit_lsbsLess_T_12[5:0]; // @[PMP.scala:60:27, :82:64] wire res_hit_lsbsLess_1 = _res_hit_lsbsLess_T_8 < _res_hit_lsbsLess_T_13; // @[PMP.scala:82:{42,53,64}] wire _res_hit_T_9 = res_hit_msbsEqual_1 & res_hit_lsbsLess_1; // @[PMP.scala:81:69, :82:53, :83:30] wire _res_hit_T_10 = res_hit_msbsLess_1 | _res_hit_T_9; // @[PMP.scala:80:39, :83:{16,30}] wire _res_hit_T_11 = _res_hit_T_8 & _res_hit_T_10; // @[PMP.scala:83:16, :88:5, :94:48] wire _res_hit_T_12 = _res_hit_T_2 & _res_hit_T_11; // @[PMP.scala:46:26, :94:48, :132:61] wire res_hit = _res_hit_T ? _res_hit_T_1 : _res_hit_T_12; // @[PMP.scala:45:20, :71:16, :132:{8,61}] wire _res_ignore_T = ~io_pmp_7_cfg_l_0; // @[PMP.scala:143:7, :164:29] wire res_ignore = default_0 & _res_ignore_T; // @[PMP.scala:156:56, :164:{26,29}] wire [31:0] _res_aligned_straddlesLowerBound_T_2 = ~_res_aligned_straddlesLowerBound_T_1; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesLowerBound_T_3 = {_res_aligned_straddlesLowerBound_T_2[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesLowerBound_T_4 = ~_res_aligned_straddlesLowerBound_T_3; // @[PMP.scala:60:{27,48}] wire [25:0] _res_aligned_straddlesLowerBound_T_5 = _res_aligned_straddlesLowerBound_T_4[31:6]; // @[PMP.scala:60:27, :123:67] wire [25:0] _res_aligned_straddlesLowerBound_T_6 = _res_aligned_straddlesLowerBound_T ^ _res_aligned_straddlesLowerBound_T_5; // @[PMP.scala:123:{35,49,67}] wire _res_aligned_straddlesLowerBound_T_7 = _res_aligned_straddlesLowerBound_T_6 == 26'h0; // @[PMP.scala:80:52, :81:54, :123:{49,67,82}] wire [31:0] _res_aligned_straddlesLowerBound_T_9 = ~_res_aligned_straddlesLowerBound_T_8; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesLowerBound_T_10 = {_res_aligned_straddlesLowerBound_T_9[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesLowerBound_T_11 = ~_res_aligned_straddlesLowerBound_T_10; // @[PMP.scala:60:{27,48}] wire [5:0] _res_aligned_straddlesLowerBound_T_12 = _res_aligned_straddlesLowerBound_T_11[5:0]; // @[PMP.scala:60:27, :123:108] wire [5:0] _res_aligned_straddlesLowerBound_T_14 = ~_res_aligned_straddlesLowerBound_T_13; // @[PMP.scala:123:{127,129}] wire [5:0] _res_aligned_straddlesLowerBound_T_15 = _res_aligned_straddlesLowerBound_T_12 & _res_aligned_straddlesLowerBound_T_14; // @[PMP.scala:123:{108,125,127}] wire _res_aligned_straddlesLowerBound_T_16 = |_res_aligned_straddlesLowerBound_T_15; // @[PMP.scala:123:{125,147}] wire res_aligned_straddlesLowerBound = _res_aligned_straddlesLowerBound_T_7 & _res_aligned_straddlesLowerBound_T_16; // @[PMP.scala:123:{82,90,147}] wire [31:0] _res_aligned_straddlesUpperBound_T_2 = ~_res_aligned_straddlesUpperBound_T_1; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesUpperBound_T_3 = {_res_aligned_straddlesUpperBound_T_2[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesUpperBound_T_4 = ~_res_aligned_straddlesUpperBound_T_3; // @[PMP.scala:60:{27,48}] wire [25:0] _res_aligned_straddlesUpperBound_T_5 = _res_aligned_straddlesUpperBound_T_4[31:6]; // @[PMP.scala:60:27, :124:62] wire [25:0] _res_aligned_straddlesUpperBound_T_6 = _res_aligned_straddlesUpperBound_T ^ _res_aligned_straddlesUpperBound_T_5; // @[PMP.scala:124:{35,49,62}] wire _res_aligned_straddlesUpperBound_T_7 = _res_aligned_straddlesUpperBound_T_6 == 26'h0; // @[PMP.scala:80:52, :81:54, :123:67, :124:{49,77}] wire [31:0] _res_aligned_straddlesUpperBound_T_9 = ~_res_aligned_straddlesUpperBound_T_8; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesUpperBound_T_10 = {_res_aligned_straddlesUpperBound_T_9[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesUpperBound_T_11 = ~_res_aligned_straddlesUpperBound_T_10; // @[PMP.scala:60:{27,48}] wire [5:0] _res_aligned_straddlesUpperBound_T_12 = _res_aligned_straddlesUpperBound_T_11[5:0]; // @[PMP.scala:60:27, :124:98] wire [5:0] _res_aligned_straddlesUpperBound_T_14 = _res_aligned_straddlesUpperBound_T_13; // @[PMP.scala:124:{119,136}] wire [5:0] _res_aligned_straddlesUpperBound_T_15 = _res_aligned_straddlesUpperBound_T_12 & _res_aligned_straddlesUpperBound_T_14; // @[PMP.scala:124:{98,115,136}] wire _res_aligned_straddlesUpperBound_T_16 = |_res_aligned_straddlesUpperBound_T_15; // @[PMP.scala:124:{115,148}] wire res_aligned_straddlesUpperBound = _res_aligned_straddlesUpperBound_T_7 & _res_aligned_straddlesUpperBound_T_16; // @[PMP.scala:124:{77,85,148}] wire _res_aligned_rangeAligned_T = res_aligned_straddlesLowerBound | res_aligned_straddlesUpperBound; // @[PMP.scala:123:90, :124:85, :125:46] wire res_aligned_rangeAligned = ~_res_aligned_rangeAligned_T; // @[PMP.scala:125:{24,46}] wire [5:0] _res_aligned_pow2Aligned_T_1 = ~_res_aligned_pow2Aligned_T; // @[PMP.scala:126:{34,39}] wire res_aligned = _res_aligned_T | res_aligned_rangeAligned; // @[PMP.scala:45:20, :125:24, :127:8] wire _res_T = io_pmp_7_cfg_a_0 == 2'h0; // @[PMP.scala:143:7, :168:32] wire _GEN_1 = io_pmp_7_cfg_a_0 == 2'h1; // @[PMP.scala:143:7, :168:32] wire _res_T_1; // @[PMP.scala:168:32] assign _res_T_1 = _GEN_1; // @[PMP.scala:168:32] wire _res_T_20; // @[PMP.scala:177:61] assign _res_T_20 = _GEN_1; // @[PMP.scala:168:32, :177:61] wire _res_T_24; // @[PMP.scala:178:63] assign _res_T_24 = _GEN_1; // @[PMP.scala:168:32, :178:63] wire _GEN_2 = io_pmp_7_cfg_a_0 == 2'h2; // @[PMP.scala:143:7, :168:32] wire _res_T_2; // @[PMP.scala:168:32] assign _res_T_2 = _GEN_2; // @[PMP.scala:168:32] wire _res_T_29; // @[PMP.scala:177:61] assign _res_T_29 = _GEN_2; // @[PMP.scala:168:32, :177:61] wire _res_T_33; // @[PMP.scala:178:63] assign _res_T_33 = _GEN_2; // @[PMP.scala:168:32, :178:63] wire _res_T_3 = &io_pmp_7_cfg_a_0; // @[PMP.scala:143:7, :168:32] wire [1:0] _GEN_3 = {io_pmp_7_cfg_x_0, io_pmp_7_cfg_w_0}; // @[PMP.scala:143:7, :174:26] wire [1:0] res_hi; // @[PMP.scala:174:26] assign res_hi = _GEN_3; // @[PMP.scala:174:26] wire [1:0] res_hi_1; // @[PMP.scala:174:26] assign res_hi_1 = _GEN_3; // @[PMP.scala:174:26] wire [1:0] res_hi_2; // @[PMP.scala:174:26] assign res_hi_2 = _GEN_3; // @[PMP.scala:174:26] wire [1:0] res_hi_3; // @[PMP.scala:174:26] assign res_hi_3 = _GEN_3; // @[PMP.scala:174:26] wire [1:0] res_hi_4; // @[PMP.scala:174:26] assign res_hi_4 = _GEN_3; // @[PMP.scala:174:26] wire [1:0] res_hi_5; // @[PMP.scala:174:26] assign res_hi_5 = _GEN_3; // @[PMP.scala:174:26] wire [2:0] _res_T_5 = {res_hi, io_pmp_7_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_6 = _res_T_5 == 3'h0; // @[PMP.scala:143:7, :146:14, :174:{26,60}] wire [2:0] _res_T_7 = {res_hi_1, io_pmp_7_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_8 = _res_T_7 == 3'h1; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_9 = {res_hi_2, io_pmp_7_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_10 = _res_T_9 == 3'h3; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_11 = {res_hi_3, io_pmp_7_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_12 = _res_T_11 == 3'h4; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_13 = {res_hi_4, io_pmp_7_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_14 = _res_T_13 == 3'h5; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_15 = {res_hi_5, io_pmp_7_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_16 = &_res_T_15; // @[PMP.scala:174:{26,60}] wire _res_T_17 = ~res_ignore; // @[PMP.scala:164:26, :177:22] wire _res_T_18 = _res_T_17 & res_hit; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_19 = _res_T_18 & res_aligned; // @[PMP.scala:127:8, :177:{30,37}] wire _res_T_21 = _res_T_19 & _res_T_20; // @[PMP.scala:177:{37,48,61}] wire _GEN_4 = io_pmp_7_cfg_l_0 & res_hit; // @[PMP.scala:132:8, :143:7, :178:32] wire _res_T_22; // @[PMP.scala:178:32] assign _res_T_22 = _GEN_4; // @[PMP.scala:178:32] wire _res_T_31; // @[PMP.scala:178:32] assign _res_T_31 = _GEN_4; // @[PMP.scala:178:32] wire _res_T_40; // @[PMP.scala:178:32] assign _res_T_40 = _GEN_4; // @[PMP.scala:178:32] wire _res_T_23 = _res_T_22 & res_aligned; // @[PMP.scala:127:8, :178:{32,39}] wire _res_T_25 = _res_T_23 & _res_T_24; // @[PMP.scala:178:{39,50,63}] wire _res_T_26 = ~res_ignore; // @[PMP.scala:164:26, :177:22] wire _res_T_27 = _res_T_26 & res_hit; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_28 = _res_T_27 & res_aligned; // @[PMP.scala:127:8, :177:{30,37}] wire _res_T_30 = _res_T_28 & _res_T_29; // @[PMP.scala:177:{37,48,61}] wire _res_T_32 = _res_T_31 & res_aligned; // @[PMP.scala:127:8, :178:{32,39}] wire _res_T_34 = _res_T_32 & _res_T_33; // @[PMP.scala:178:{39,50,63}] wire _res_T_35 = ~res_ignore; // @[PMP.scala:164:26, :177:22] wire _res_T_36 = _res_T_35 & res_hit; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_37 = _res_T_36 & res_aligned; // @[PMP.scala:127:8, :177:{30,37}] wire _res_T_38 = &io_pmp_7_cfg_a_0; // @[PMP.scala:143:7, :168:32, :177:61] wire _res_T_39 = _res_T_37 & _res_T_38; // @[PMP.scala:177:{37,48,61}] wire _res_T_41 = _res_T_40 & res_aligned; // @[PMP.scala:127:8, :178:{32,39}] wire _res_T_42 = &io_pmp_7_cfg_a_0; // @[PMP.scala:143:7, :168:32, :178:63] wire _res_T_43 = _res_T_41 & _res_T_42; // @[PMP.scala:178:{39,50,63}] wire _res_cur_cfg_x_T_1; // @[PMP.scala:184:26] wire _res_cur_cfg_w_T_1; // @[PMP.scala:183:26] wire _res_cur_cfg_r_T_1; // @[PMP.scala:182:26] wire res_cur_cfg_x; // @[PMP.scala:181:23] wire res_cur_cfg_w; // @[PMP.scala:181:23] wire res_cur_cfg_r; // @[PMP.scala:181:23] wire _res_cur_cfg_r_T = io_pmp_7_cfg_r_0 | res_ignore; // @[PMP.scala:143:7, :164:26, :182:40] assign _res_cur_cfg_r_T_1 = res_aligned & _res_cur_cfg_r_T; // @[PMP.scala:127:8, :182:{26,40}] assign res_cur_cfg_r = _res_cur_cfg_r_T_1; // @[PMP.scala:181:23, :182:26] wire _res_cur_cfg_w_T = io_pmp_7_cfg_w_0 | res_ignore; // @[PMP.scala:143:7, :164:26, :183:40] assign _res_cur_cfg_w_T_1 = res_aligned & _res_cur_cfg_w_T; // @[PMP.scala:127:8, :183:{26,40}] assign res_cur_cfg_w = _res_cur_cfg_w_T_1; // @[PMP.scala:181:23, :183:26] wire _res_cur_cfg_x_T = io_pmp_7_cfg_x_0 | res_ignore; // @[PMP.scala:143:7, :164:26, :184:40] assign _res_cur_cfg_x_T_1 = res_aligned & _res_cur_cfg_x_T; // @[PMP.scala:127:8, :184:{26,40}] assign res_cur_cfg_x = _res_cur_cfg_x_T_1; // @[PMP.scala:181:23, :184:26] wire _res_T_44_cfg_l = res_hit & res_cur_cfg_l; // @[PMP.scala:132:8, :181:23, :185:8] wire [1:0] _res_T_44_cfg_a = res_hit ? res_cur_cfg_a : 2'h0; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_T_44_cfg_x = res_hit ? res_cur_cfg_x : pmp0_cfg_x; // @[PMP.scala:132:8, :157:22, :181:23, :185:8] wire _res_T_44_cfg_w = res_hit ? res_cur_cfg_w : pmp0_cfg_w; // @[PMP.scala:132:8, :157:22, :181:23, :185:8] wire _res_T_44_cfg_r = res_hit ? res_cur_cfg_r : pmp0_cfg_r; // @[PMP.scala:132:8, :157:22, :181:23, :185:8] wire [29:0] _res_T_44_addr = res_hit ? res_cur_addr : 30'h0; // @[PMP.scala:132:8, :181:23, :185:8] wire [31:0] _res_T_44_mask = res_hit ? res_cur_mask : 32'h0; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_hit_T_13 = io_pmp_6_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7] wire _res_aligned_T_1 = io_pmp_6_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7] wire [25:0] _res_hit_msbMatch_T_16 = io_pmp_6_mask_0[31:6]; // @[PMP.scala:68:26, :69:72, :143:7] wire [5:0] _res_aligned_pow2Aligned_T_3 = io_pmp_6_mask_0[5:0]; // @[PMP.scala:68:26, :126:39, :143:7] wire [31:0] _res_hit_msbMatch_T_12 = ~_res_hit_msbMatch_T_11; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbMatch_T_13 = {_res_hit_msbMatch_T_12[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbMatch_T_14 = ~_res_hit_msbMatch_T_13; // @[PMP.scala:60:{27,48}] wire [25:0] _res_hit_msbMatch_T_15 = _res_hit_msbMatch_T_14[31:6]; // @[PMP.scala:60:27, :69:53] wire [25:0] _res_hit_msbMatch_T_17 = _res_hit_msbMatch_T_10 ^ _res_hit_msbMatch_T_15; // @[PMP.scala:63:47, :69:{29,53}] wire [25:0] _res_hit_msbMatch_T_18 = ~_res_hit_msbMatch_T_16; // @[PMP.scala:63:54, :69:72] wire [25:0] _res_hit_msbMatch_T_19 = _res_hit_msbMatch_T_17 & _res_hit_msbMatch_T_18; // @[PMP.scala:63:{47,52,54}] wire res_hit_msbMatch_1 = _res_hit_msbMatch_T_19 == 26'h0; // @[PMP.scala:63:{52,58}, :80:52, :81:54, :123:67] wire [31:0] _res_hit_lsbMatch_T_12 = ~_res_hit_lsbMatch_T_11; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_lsbMatch_T_13 = {_res_hit_lsbMatch_T_12[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbMatch_T_14 = ~_res_hit_lsbMatch_T_13; // @[PMP.scala:60:{27,48}] wire [5:0] _res_hit_lsbMatch_T_15 = _res_hit_lsbMatch_T_14[5:0]; // @[PMP.scala:60:27, :70:55] wire [5:0] _res_hit_lsbMatch_T_16 = res_hit_lsbMask_1[5:0]; // @[PMP.scala:68:26, :70:80] wire [5:0] _res_hit_lsbMatch_T_17 = _res_hit_lsbMatch_T_10 ^ _res_hit_lsbMatch_T_15; // @[PMP.scala:63:47, :70:{28,55}] wire [5:0] _res_hit_lsbMatch_T_18 = ~_res_hit_lsbMatch_T_16; // @[PMP.scala:63:54, :70:80] wire [5:0] _res_hit_lsbMatch_T_19 = _res_hit_lsbMatch_T_17 & _res_hit_lsbMatch_T_18; // @[PMP.scala:63:{47,52,54}] wire res_hit_lsbMatch_1 = _res_hit_lsbMatch_T_19 == 6'h0; // @[PMP.scala:63:{52,58}] wire _res_hit_T_14 = res_hit_msbMatch_1 & res_hit_lsbMatch_1; // @[PMP.scala:63:58, :71:16] wire _res_hit_T_15 = io_pmp_6_cfg_a_0[0]; // @[PMP.scala:46:26, :143:7] wire [31:0] _GEN_5 = {io_pmp_5_addr_0, 2'h0}; // @[PMP.scala:60:36, :143:7] wire [31:0] _res_hit_msbsLess_T_13; // @[PMP.scala:60:36] assign _res_hit_msbsLess_T_13 = _GEN_5; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsEqual_T_15; // @[PMP.scala:60:36] assign _res_hit_msbsEqual_T_15 = _GEN_5; // @[PMP.scala:60:36] wire [31:0] _res_hit_lsbsLess_T_16; // @[PMP.scala:60:36] assign _res_hit_lsbsLess_T_16 = _GEN_5; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesLowerBound_T_18; // @[PMP.scala:60:36] assign _res_aligned_straddlesLowerBound_T_18 = _GEN_5; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesLowerBound_T_25; // @[PMP.scala:60:36] assign _res_aligned_straddlesLowerBound_T_25 = _GEN_5; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbMatch_T_21; // @[PMP.scala:60:36] assign _res_hit_msbMatch_T_21 = _GEN_5; // @[PMP.scala:60:36] wire [31:0] _res_hit_lsbMatch_T_21; // @[PMP.scala:60:36] assign _res_hit_lsbMatch_T_21 = _GEN_5; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsLess_T_31; // @[PMP.scala:60:36] assign _res_hit_msbsLess_T_31 = _GEN_5; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsEqual_T_36; // @[PMP.scala:60:36] assign _res_hit_msbsEqual_T_36 = _GEN_5; // @[PMP.scala:60:36] wire [31:0] _res_hit_lsbsLess_T_37; // @[PMP.scala:60:36] assign _res_hit_lsbsLess_T_37 = _GEN_5; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesUpperBound_T_35; // @[PMP.scala:60:36] assign _res_aligned_straddlesUpperBound_T_35 = _GEN_5; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesUpperBound_T_42; // @[PMP.scala:60:36] assign _res_aligned_straddlesUpperBound_T_42 = _GEN_5; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsLess_T_14 = ~_res_hit_msbsLess_T_13; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsLess_T_15 = {_res_hit_msbsLess_T_14[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsLess_T_16 = ~_res_hit_msbsLess_T_15; // @[PMP.scala:60:{27,48}] wire [25:0] _res_hit_msbsLess_T_17 = _res_hit_msbsLess_T_16[31:6]; // @[PMP.scala:60:27, :80:52] wire res_hit_msbsLess_2 = _res_hit_msbsLess_T_12 < _res_hit_msbsLess_T_17; // @[PMP.scala:80:{25,39,52}] wire [31:0] _res_hit_msbsEqual_T_16 = ~_res_hit_msbsEqual_T_15; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsEqual_T_17 = {_res_hit_msbsEqual_T_16[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsEqual_T_18 = ~_res_hit_msbsEqual_T_17; // @[PMP.scala:60:{27,48}] wire [25:0] _res_hit_msbsEqual_T_19 = _res_hit_msbsEqual_T_18[31:6]; // @[PMP.scala:60:27, :81:54] wire [25:0] _res_hit_msbsEqual_T_20 = _res_hit_msbsEqual_T_14 ^ _res_hit_msbsEqual_T_19; // @[PMP.scala:81:{27,41,54}] wire res_hit_msbsEqual_2 = _res_hit_msbsEqual_T_20 == 26'h0; // @[PMP.scala:80:52, :81:{41,54,69}, :123:67] wire [5:0] _res_hit_lsbsLess_T_15 = _res_hit_lsbsLess_T_14; // @[PMP.scala:82:{25,42}] wire [31:0] _res_hit_lsbsLess_T_17 = ~_res_hit_lsbsLess_T_16; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_lsbsLess_T_18 = {_res_hit_lsbsLess_T_17[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbsLess_T_19 = ~_res_hit_lsbsLess_T_18; // @[PMP.scala:60:{27,48}] wire [5:0] _res_hit_lsbsLess_T_20 = _res_hit_lsbsLess_T_19[5:0]; // @[PMP.scala:60:27, :82:64] wire res_hit_lsbsLess_2 = _res_hit_lsbsLess_T_15 < _res_hit_lsbsLess_T_20; // @[PMP.scala:82:{42,53,64}] wire _res_hit_T_19 = res_hit_msbsEqual_2 & res_hit_lsbsLess_2; // @[PMP.scala:81:69, :82:53, :83:30] wire _res_hit_T_20 = res_hit_msbsLess_2 | _res_hit_T_19; // @[PMP.scala:80:39, :83:{16,30}] wire _res_hit_T_21 = ~_res_hit_T_20; // @[PMP.scala:83:16, :88:5] wire [31:0] _res_hit_msbsLess_T_20 = ~_res_hit_msbsLess_T_19; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsLess_T_21 = {_res_hit_msbsLess_T_20[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsLess_T_22 = ~_res_hit_msbsLess_T_21; // @[PMP.scala:60:{27,48}] wire [25:0] _res_hit_msbsLess_T_23 = _res_hit_msbsLess_T_22[31:6]; // @[PMP.scala:60:27, :80:52] wire res_hit_msbsLess_3 = _res_hit_msbsLess_T_18 < _res_hit_msbsLess_T_23; // @[PMP.scala:80:{25,39,52}] wire [31:0] _res_hit_msbsEqual_T_23 = ~_res_hit_msbsEqual_T_22; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsEqual_T_24 = {_res_hit_msbsEqual_T_23[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsEqual_T_25 = ~_res_hit_msbsEqual_T_24; // @[PMP.scala:60:{27,48}] wire [25:0] _res_hit_msbsEqual_T_26 = _res_hit_msbsEqual_T_25[31:6]; // @[PMP.scala:60:27, :81:54] wire [25:0] _res_hit_msbsEqual_T_27 = _res_hit_msbsEqual_T_21 ^ _res_hit_msbsEqual_T_26; // @[PMP.scala:81:{27,41,54}] wire res_hit_msbsEqual_3 = _res_hit_msbsEqual_T_27 == 26'h0; // @[PMP.scala:80:52, :81:{41,54,69}, :123:67] wire [5:0] _res_hit_lsbsLess_T_22 = _res_hit_lsbsLess_T_21; // @[PMP.scala:82:{25,42}] wire [31:0] _res_hit_lsbsLess_T_24 = ~_res_hit_lsbsLess_T_23; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_lsbsLess_T_25 = {_res_hit_lsbsLess_T_24[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbsLess_T_26 = ~_res_hit_lsbsLess_T_25; // @[PMP.scala:60:{27,48}] wire [5:0] _res_hit_lsbsLess_T_27 = _res_hit_lsbsLess_T_26[5:0]; // @[PMP.scala:60:27, :82:64] wire res_hit_lsbsLess_3 = _res_hit_lsbsLess_T_22 < _res_hit_lsbsLess_T_27; // @[PMP.scala:82:{42,53,64}] wire _res_hit_T_22 = res_hit_msbsEqual_3 & res_hit_lsbsLess_3; // @[PMP.scala:81:69, :82:53, :83:30] wire _res_hit_T_23 = res_hit_msbsLess_3 | _res_hit_T_22; // @[PMP.scala:80:39, :83:{16,30}] wire _res_hit_T_24 = _res_hit_T_21 & _res_hit_T_23; // @[PMP.scala:83:16, :88:5, :94:48] wire _res_hit_T_25 = _res_hit_T_15 & _res_hit_T_24; // @[PMP.scala:46:26, :94:48, :132:61] wire res_hit_1 = _res_hit_T_13 ? _res_hit_T_14 : _res_hit_T_25; // @[PMP.scala:45:20, :71:16, :132:{8,61}] wire _res_ignore_T_1 = ~io_pmp_6_cfg_l_0; // @[PMP.scala:143:7, :164:29] wire res_ignore_1 = default_0 & _res_ignore_T_1; // @[PMP.scala:156:56, :164:{26,29}] wire [31:0] _res_aligned_straddlesLowerBound_T_19 = ~_res_aligned_straddlesLowerBound_T_18; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesLowerBound_T_20 = {_res_aligned_straddlesLowerBound_T_19[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesLowerBound_T_21 = ~_res_aligned_straddlesLowerBound_T_20; // @[PMP.scala:60:{27,48}] wire [25:0] _res_aligned_straddlesLowerBound_T_22 = _res_aligned_straddlesLowerBound_T_21[31:6]; // @[PMP.scala:60:27, :123:67] wire [25:0] _res_aligned_straddlesLowerBound_T_23 = _res_aligned_straddlesLowerBound_T_17 ^ _res_aligned_straddlesLowerBound_T_22; // @[PMP.scala:123:{35,49,67}] wire _res_aligned_straddlesLowerBound_T_24 = _res_aligned_straddlesLowerBound_T_23 == 26'h0; // @[PMP.scala:80:52, :81:54, :123:{49,67,82}] wire [31:0] _res_aligned_straddlesLowerBound_T_26 = ~_res_aligned_straddlesLowerBound_T_25; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesLowerBound_T_27 = {_res_aligned_straddlesLowerBound_T_26[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesLowerBound_T_28 = ~_res_aligned_straddlesLowerBound_T_27; // @[PMP.scala:60:{27,48}] wire [5:0] _res_aligned_straddlesLowerBound_T_29 = _res_aligned_straddlesLowerBound_T_28[5:0]; // @[PMP.scala:60:27, :123:108] wire [5:0] _res_aligned_straddlesLowerBound_T_31 = ~_res_aligned_straddlesLowerBound_T_30; // @[PMP.scala:123:{127,129}] wire [5:0] _res_aligned_straddlesLowerBound_T_32 = _res_aligned_straddlesLowerBound_T_29 & _res_aligned_straddlesLowerBound_T_31; // @[PMP.scala:123:{108,125,127}] wire _res_aligned_straddlesLowerBound_T_33 = |_res_aligned_straddlesLowerBound_T_32; // @[PMP.scala:123:{125,147}] wire res_aligned_straddlesLowerBound_1 = _res_aligned_straddlesLowerBound_T_24 & _res_aligned_straddlesLowerBound_T_33; // @[PMP.scala:123:{82,90,147}] wire [31:0] _res_aligned_straddlesUpperBound_T_19 = ~_res_aligned_straddlesUpperBound_T_18; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesUpperBound_T_20 = {_res_aligned_straddlesUpperBound_T_19[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesUpperBound_T_21 = ~_res_aligned_straddlesUpperBound_T_20; // @[PMP.scala:60:{27,48}] wire [25:0] _res_aligned_straddlesUpperBound_T_22 = _res_aligned_straddlesUpperBound_T_21[31:6]; // @[PMP.scala:60:27, :124:62] wire [25:0] _res_aligned_straddlesUpperBound_T_23 = _res_aligned_straddlesUpperBound_T_17 ^ _res_aligned_straddlesUpperBound_T_22; // @[PMP.scala:124:{35,49,62}] wire _res_aligned_straddlesUpperBound_T_24 = _res_aligned_straddlesUpperBound_T_23 == 26'h0; // @[PMP.scala:80:52, :81:54, :123:67, :124:{49,77}] wire [31:0] _res_aligned_straddlesUpperBound_T_26 = ~_res_aligned_straddlesUpperBound_T_25; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesUpperBound_T_27 = {_res_aligned_straddlesUpperBound_T_26[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesUpperBound_T_28 = ~_res_aligned_straddlesUpperBound_T_27; // @[PMP.scala:60:{27,48}] wire [5:0] _res_aligned_straddlesUpperBound_T_29 = _res_aligned_straddlesUpperBound_T_28[5:0]; // @[PMP.scala:60:27, :124:98] wire [5:0] _res_aligned_straddlesUpperBound_T_31 = _res_aligned_straddlesUpperBound_T_30; // @[PMP.scala:124:{119,136}] wire [5:0] _res_aligned_straddlesUpperBound_T_32 = _res_aligned_straddlesUpperBound_T_29 & _res_aligned_straddlesUpperBound_T_31; // @[PMP.scala:124:{98,115,136}] wire _res_aligned_straddlesUpperBound_T_33 = |_res_aligned_straddlesUpperBound_T_32; // @[PMP.scala:124:{115,148}] wire res_aligned_straddlesUpperBound_1 = _res_aligned_straddlesUpperBound_T_24 & _res_aligned_straddlesUpperBound_T_33; // @[PMP.scala:124:{77,85,148}] wire _res_aligned_rangeAligned_T_1 = res_aligned_straddlesLowerBound_1 | res_aligned_straddlesUpperBound_1; // @[PMP.scala:123:90, :124:85, :125:46] wire res_aligned_rangeAligned_1 = ~_res_aligned_rangeAligned_T_1; // @[PMP.scala:125:{24,46}] wire [5:0] _res_aligned_pow2Aligned_T_4 = ~_res_aligned_pow2Aligned_T_3; // @[PMP.scala:126:{34,39}] wire res_aligned_1 = _res_aligned_T_1 | res_aligned_rangeAligned_1; // @[PMP.scala:45:20, :125:24, :127:8] wire _res_T_45 = io_pmp_6_cfg_a_0 == 2'h0; // @[PMP.scala:143:7, :168:32] wire _GEN_6 = io_pmp_6_cfg_a_0 == 2'h1; // @[PMP.scala:143:7, :168:32] wire _res_T_46; // @[PMP.scala:168:32] assign _res_T_46 = _GEN_6; // @[PMP.scala:168:32] wire _res_T_65; // @[PMP.scala:177:61] assign _res_T_65 = _GEN_6; // @[PMP.scala:168:32, :177:61] wire _res_T_69; // @[PMP.scala:178:63] assign _res_T_69 = _GEN_6; // @[PMP.scala:168:32, :178:63] wire _GEN_7 = io_pmp_6_cfg_a_0 == 2'h2; // @[PMP.scala:143:7, :168:32] wire _res_T_47; // @[PMP.scala:168:32] assign _res_T_47 = _GEN_7; // @[PMP.scala:168:32] wire _res_T_74; // @[PMP.scala:177:61] assign _res_T_74 = _GEN_7; // @[PMP.scala:168:32, :177:61] wire _res_T_78; // @[PMP.scala:178:63] assign _res_T_78 = _GEN_7; // @[PMP.scala:168:32, :178:63] wire _res_T_48 = &io_pmp_6_cfg_a_0; // @[PMP.scala:143:7, :168:32] wire [1:0] _GEN_8 = {io_pmp_6_cfg_x_0, io_pmp_6_cfg_w_0}; // @[PMP.scala:143:7, :174:26] wire [1:0] res_hi_6; // @[PMP.scala:174:26] assign res_hi_6 = _GEN_8; // @[PMP.scala:174:26] wire [1:0] res_hi_7; // @[PMP.scala:174:26] assign res_hi_7 = _GEN_8; // @[PMP.scala:174:26] wire [1:0] res_hi_8; // @[PMP.scala:174:26] assign res_hi_8 = _GEN_8; // @[PMP.scala:174:26] wire [1:0] res_hi_9; // @[PMP.scala:174:26] assign res_hi_9 = _GEN_8; // @[PMP.scala:174:26] wire [1:0] res_hi_10; // @[PMP.scala:174:26] assign res_hi_10 = _GEN_8; // @[PMP.scala:174:26] wire [1:0] res_hi_11; // @[PMP.scala:174:26] assign res_hi_11 = _GEN_8; // @[PMP.scala:174:26] wire [2:0] _res_T_50 = {res_hi_6, io_pmp_6_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_51 = _res_T_50 == 3'h0; // @[PMP.scala:143:7, :146:14, :174:{26,60}] wire [2:0] _res_T_52 = {res_hi_7, io_pmp_6_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_53 = _res_T_52 == 3'h1; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_54 = {res_hi_8, io_pmp_6_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_55 = _res_T_54 == 3'h3; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_56 = {res_hi_9, io_pmp_6_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_57 = _res_T_56 == 3'h4; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_58 = {res_hi_10, io_pmp_6_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_59 = _res_T_58 == 3'h5; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_60 = {res_hi_11, io_pmp_6_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_61 = &_res_T_60; // @[PMP.scala:174:{26,60}] wire _res_T_62 = ~res_ignore_1; // @[PMP.scala:164:26, :177:22] wire _res_T_63 = _res_T_62 & res_hit_1; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_64 = _res_T_63 & res_aligned_1; // @[PMP.scala:127:8, :177:{30,37}] wire _res_T_66 = _res_T_64 & _res_T_65; // @[PMP.scala:177:{37,48,61}] wire _GEN_9 = io_pmp_6_cfg_l_0 & res_hit_1; // @[PMP.scala:132:8, :143:7, :178:32] wire _res_T_67; // @[PMP.scala:178:32] assign _res_T_67 = _GEN_9; // @[PMP.scala:178:32] wire _res_T_76; // @[PMP.scala:178:32] assign _res_T_76 = _GEN_9; // @[PMP.scala:178:32] wire _res_T_85; // @[PMP.scala:178:32] assign _res_T_85 = _GEN_9; // @[PMP.scala:178:32] wire _res_T_68 = _res_T_67 & res_aligned_1; // @[PMP.scala:127:8, :178:{32,39}] wire _res_T_70 = _res_T_68 & _res_T_69; // @[PMP.scala:178:{39,50,63}] wire _res_T_71 = ~res_ignore_1; // @[PMP.scala:164:26, :177:22] wire _res_T_72 = _res_T_71 & res_hit_1; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_73 = _res_T_72 & res_aligned_1; // @[PMP.scala:127:8, :177:{30,37}] wire _res_T_75 = _res_T_73 & _res_T_74; // @[PMP.scala:177:{37,48,61}] wire _res_T_77 = _res_T_76 & res_aligned_1; // @[PMP.scala:127:8, :178:{32,39}] wire _res_T_79 = _res_T_77 & _res_T_78; // @[PMP.scala:178:{39,50,63}] wire _res_T_80 = ~res_ignore_1; // @[PMP.scala:164:26, :177:22] wire _res_T_81 = _res_T_80 & res_hit_1; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_82 = _res_T_81 & res_aligned_1; // @[PMP.scala:127:8, :177:{30,37}] wire _res_T_83 = &io_pmp_6_cfg_a_0; // @[PMP.scala:143:7, :168:32, :177:61] wire _res_T_84 = _res_T_82 & _res_T_83; // @[PMP.scala:177:{37,48,61}] wire _res_T_86 = _res_T_85 & res_aligned_1; // @[PMP.scala:127:8, :178:{32,39}] wire _res_T_87 = &io_pmp_6_cfg_a_0; // @[PMP.scala:143:7, :168:32, :178:63] wire _res_T_88 = _res_T_86 & _res_T_87; // @[PMP.scala:178:{39,50,63}] wire _res_cur_cfg_x_T_3; // @[PMP.scala:184:26] wire _res_cur_cfg_w_T_3; // @[PMP.scala:183:26] wire _res_cur_cfg_r_T_3; // @[PMP.scala:182:26] wire res_cur_1_cfg_x; // @[PMP.scala:181:23] wire res_cur_1_cfg_w; // @[PMP.scala:181:23] wire res_cur_1_cfg_r; // @[PMP.scala:181:23] wire _res_cur_cfg_r_T_2 = io_pmp_6_cfg_r_0 | res_ignore_1; // @[PMP.scala:143:7, :164:26, :182:40] assign _res_cur_cfg_r_T_3 = res_aligned_1 & _res_cur_cfg_r_T_2; // @[PMP.scala:127:8, :182:{26,40}] assign res_cur_1_cfg_r = _res_cur_cfg_r_T_3; // @[PMP.scala:181:23, :182:26] wire _res_cur_cfg_w_T_2 = io_pmp_6_cfg_w_0 | res_ignore_1; // @[PMP.scala:143:7, :164:26, :183:40] assign _res_cur_cfg_w_T_3 = res_aligned_1 & _res_cur_cfg_w_T_2; // @[PMP.scala:127:8, :183:{26,40}] assign res_cur_1_cfg_w = _res_cur_cfg_w_T_3; // @[PMP.scala:181:23, :183:26] wire _res_cur_cfg_x_T_2 = io_pmp_6_cfg_x_0 | res_ignore_1; // @[PMP.scala:143:7, :164:26, :184:40] assign _res_cur_cfg_x_T_3 = res_aligned_1 & _res_cur_cfg_x_T_2; // @[PMP.scala:127:8, :184:{26,40}] assign res_cur_1_cfg_x = _res_cur_cfg_x_T_3; // @[PMP.scala:181:23, :184:26] wire _res_T_89_cfg_l = res_hit_1 ? res_cur_1_cfg_l : _res_T_44_cfg_l; // @[PMP.scala:132:8, :181:23, :185:8] wire [1:0] _res_T_89_cfg_a = res_hit_1 ? res_cur_1_cfg_a : _res_T_44_cfg_a; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_T_89_cfg_x = res_hit_1 ? res_cur_1_cfg_x : _res_T_44_cfg_x; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_T_89_cfg_w = res_hit_1 ? res_cur_1_cfg_w : _res_T_44_cfg_w; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_T_89_cfg_r = res_hit_1 ? res_cur_1_cfg_r : _res_T_44_cfg_r; // @[PMP.scala:132:8, :181:23, :185:8] wire [29:0] _res_T_89_addr = res_hit_1 ? res_cur_1_addr : _res_T_44_addr; // @[PMP.scala:132:8, :181:23, :185:8] wire [31:0] _res_T_89_mask = res_hit_1 ? res_cur_1_mask : _res_T_44_mask; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_hit_T_26 = io_pmp_5_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7] wire _res_aligned_T_2 = io_pmp_5_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7] wire [25:0] _res_hit_msbMatch_T_26 = io_pmp_5_mask_0[31:6]; // @[PMP.scala:68:26, :69:72, :143:7] wire [5:0] _res_aligned_pow2Aligned_T_6 = io_pmp_5_mask_0[5:0]; // @[PMP.scala:68:26, :126:39, :143:7] wire [31:0] _res_hit_msbMatch_T_22 = ~_res_hit_msbMatch_T_21; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbMatch_T_23 = {_res_hit_msbMatch_T_22[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbMatch_T_24 = ~_res_hit_msbMatch_T_23; // @[PMP.scala:60:{27,48}] wire [25:0] _res_hit_msbMatch_T_25 = _res_hit_msbMatch_T_24[31:6]; // @[PMP.scala:60:27, :69:53] wire [25:0] _res_hit_msbMatch_T_27 = _res_hit_msbMatch_T_20 ^ _res_hit_msbMatch_T_25; // @[PMP.scala:63:47, :69:{29,53}] wire [25:0] _res_hit_msbMatch_T_28 = ~_res_hit_msbMatch_T_26; // @[PMP.scala:63:54, :69:72] wire [25:0] _res_hit_msbMatch_T_29 = _res_hit_msbMatch_T_27 & _res_hit_msbMatch_T_28; // @[PMP.scala:63:{47,52,54}] wire res_hit_msbMatch_2 = _res_hit_msbMatch_T_29 == 26'h0; // @[PMP.scala:63:{52,58}, :80:52, :81:54, :123:67] wire [31:0] _res_hit_lsbMatch_T_22 = ~_res_hit_lsbMatch_T_21; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_lsbMatch_T_23 = {_res_hit_lsbMatch_T_22[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbMatch_T_24 = ~_res_hit_lsbMatch_T_23; // @[PMP.scala:60:{27,48}] wire [5:0] _res_hit_lsbMatch_T_25 = _res_hit_lsbMatch_T_24[5:0]; // @[PMP.scala:60:27, :70:55] wire [5:0] _res_hit_lsbMatch_T_26 = res_hit_lsbMask_2[5:0]; // @[PMP.scala:68:26, :70:80] wire [5:0] _res_hit_lsbMatch_T_27 = _res_hit_lsbMatch_T_20 ^ _res_hit_lsbMatch_T_25; // @[PMP.scala:63:47, :70:{28,55}] wire [5:0] _res_hit_lsbMatch_T_28 = ~_res_hit_lsbMatch_T_26; // @[PMP.scala:63:54, :70:80] wire [5:0] _res_hit_lsbMatch_T_29 = _res_hit_lsbMatch_T_27 & _res_hit_lsbMatch_T_28; // @[PMP.scala:63:{47,52,54}] wire res_hit_lsbMatch_2 = _res_hit_lsbMatch_T_29 == 6'h0; // @[PMP.scala:63:{52,58}] wire _res_hit_T_27 = res_hit_msbMatch_2 & res_hit_lsbMatch_2; // @[PMP.scala:63:58, :71:16] wire _res_hit_T_28 = io_pmp_5_cfg_a_0[0]; // @[PMP.scala:46:26, :143:7] wire [31:0] _GEN_10 = {io_pmp_4_addr_0, 2'h0}; // @[PMP.scala:60:36, :143:7] wire [31:0] _res_hit_msbsLess_T_25; // @[PMP.scala:60:36] assign _res_hit_msbsLess_T_25 = _GEN_10; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsEqual_T_29; // @[PMP.scala:60:36] assign _res_hit_msbsEqual_T_29 = _GEN_10; // @[PMP.scala:60:36] wire [31:0] _res_hit_lsbsLess_T_30; // @[PMP.scala:60:36] assign _res_hit_lsbsLess_T_30 = _GEN_10; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesLowerBound_T_35; // @[PMP.scala:60:36] assign _res_aligned_straddlesLowerBound_T_35 = _GEN_10; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesLowerBound_T_42; // @[PMP.scala:60:36] assign _res_aligned_straddlesLowerBound_T_42 = _GEN_10; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbMatch_T_31; // @[PMP.scala:60:36] assign _res_hit_msbMatch_T_31 = _GEN_10; // @[PMP.scala:60:36] wire [31:0] _res_hit_lsbMatch_T_31; // @[PMP.scala:60:36] assign _res_hit_lsbMatch_T_31 = _GEN_10; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsLess_T_43; // @[PMP.scala:60:36] assign _res_hit_msbsLess_T_43 = _GEN_10; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsEqual_T_50; // @[PMP.scala:60:36] assign _res_hit_msbsEqual_T_50 = _GEN_10; // @[PMP.scala:60:36] wire [31:0] _res_hit_lsbsLess_T_51; // @[PMP.scala:60:36] assign _res_hit_lsbsLess_T_51 = _GEN_10; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesUpperBound_T_52; // @[PMP.scala:60:36] assign _res_aligned_straddlesUpperBound_T_52 = _GEN_10; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesUpperBound_T_59; // @[PMP.scala:60:36] assign _res_aligned_straddlesUpperBound_T_59 = _GEN_10; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsLess_T_26 = ~_res_hit_msbsLess_T_25; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsLess_T_27 = {_res_hit_msbsLess_T_26[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsLess_T_28 = ~_res_hit_msbsLess_T_27; // @[PMP.scala:60:{27,48}] wire [25:0] _res_hit_msbsLess_T_29 = _res_hit_msbsLess_T_28[31:6]; // @[PMP.scala:60:27, :80:52] wire res_hit_msbsLess_4 = _res_hit_msbsLess_T_24 < _res_hit_msbsLess_T_29; // @[PMP.scala:80:{25,39,52}] wire [31:0] _res_hit_msbsEqual_T_30 = ~_res_hit_msbsEqual_T_29; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsEqual_T_31 = {_res_hit_msbsEqual_T_30[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsEqual_T_32 = ~_res_hit_msbsEqual_T_31; // @[PMP.scala:60:{27,48}] wire [25:0] _res_hit_msbsEqual_T_33 = _res_hit_msbsEqual_T_32[31:6]; // @[PMP.scala:60:27, :81:54] wire [25:0] _res_hit_msbsEqual_T_34 = _res_hit_msbsEqual_T_28 ^ _res_hit_msbsEqual_T_33; // @[PMP.scala:81:{27,41,54}] wire res_hit_msbsEqual_4 = _res_hit_msbsEqual_T_34 == 26'h0; // @[PMP.scala:80:52, :81:{41,54,69}, :123:67] wire [5:0] _res_hit_lsbsLess_T_29 = _res_hit_lsbsLess_T_28; // @[PMP.scala:82:{25,42}] wire [31:0] _res_hit_lsbsLess_T_31 = ~_res_hit_lsbsLess_T_30; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_lsbsLess_T_32 = {_res_hit_lsbsLess_T_31[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbsLess_T_33 = ~_res_hit_lsbsLess_T_32; // @[PMP.scala:60:{27,48}] wire [5:0] _res_hit_lsbsLess_T_34 = _res_hit_lsbsLess_T_33[5:0]; // @[PMP.scala:60:27, :82:64] wire res_hit_lsbsLess_4 = _res_hit_lsbsLess_T_29 < _res_hit_lsbsLess_T_34; // @[PMP.scala:82:{42,53,64}] wire _res_hit_T_32 = res_hit_msbsEqual_4 & res_hit_lsbsLess_4; // @[PMP.scala:81:69, :82:53, :83:30] wire _res_hit_T_33 = res_hit_msbsLess_4 | _res_hit_T_32; // @[PMP.scala:80:39, :83:{16,30}] wire _res_hit_T_34 = ~_res_hit_T_33; // @[PMP.scala:83:16, :88:5] wire [31:0] _res_hit_msbsLess_T_32 = ~_res_hit_msbsLess_T_31; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsLess_T_33 = {_res_hit_msbsLess_T_32[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsLess_T_34 = ~_res_hit_msbsLess_T_33; // @[PMP.scala:60:{27,48}] wire [25:0] _res_hit_msbsLess_T_35 = _res_hit_msbsLess_T_34[31:6]; // @[PMP.scala:60:27, :80:52] wire res_hit_msbsLess_5 = _res_hit_msbsLess_T_30 < _res_hit_msbsLess_T_35; // @[PMP.scala:80:{25,39,52}] wire [31:0] _res_hit_msbsEqual_T_37 = ~_res_hit_msbsEqual_T_36; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsEqual_T_38 = {_res_hit_msbsEqual_T_37[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsEqual_T_39 = ~_res_hit_msbsEqual_T_38; // @[PMP.scala:60:{27,48}] wire [25:0] _res_hit_msbsEqual_T_40 = _res_hit_msbsEqual_T_39[31:6]; // @[PMP.scala:60:27, :81:54] wire [25:0] _res_hit_msbsEqual_T_41 = _res_hit_msbsEqual_T_35 ^ _res_hit_msbsEqual_T_40; // @[PMP.scala:81:{27,41,54}] wire res_hit_msbsEqual_5 = _res_hit_msbsEqual_T_41 == 26'h0; // @[PMP.scala:80:52, :81:{41,54,69}, :123:67] wire [5:0] _res_hit_lsbsLess_T_36 = _res_hit_lsbsLess_T_35; // @[PMP.scala:82:{25,42}] wire [31:0] _res_hit_lsbsLess_T_38 = ~_res_hit_lsbsLess_T_37; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_lsbsLess_T_39 = {_res_hit_lsbsLess_T_38[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbsLess_T_40 = ~_res_hit_lsbsLess_T_39; // @[PMP.scala:60:{27,48}] wire [5:0] _res_hit_lsbsLess_T_41 = _res_hit_lsbsLess_T_40[5:0]; // @[PMP.scala:60:27, :82:64] wire res_hit_lsbsLess_5 = _res_hit_lsbsLess_T_36 < _res_hit_lsbsLess_T_41; // @[PMP.scala:82:{42,53,64}] wire _res_hit_T_35 = res_hit_msbsEqual_5 & res_hit_lsbsLess_5; // @[PMP.scala:81:69, :82:53, :83:30] wire _res_hit_T_36 = res_hit_msbsLess_5 | _res_hit_T_35; // @[PMP.scala:80:39, :83:{16,30}] wire _res_hit_T_37 = _res_hit_T_34 & _res_hit_T_36; // @[PMP.scala:83:16, :88:5, :94:48] wire _res_hit_T_38 = _res_hit_T_28 & _res_hit_T_37; // @[PMP.scala:46:26, :94:48, :132:61] wire res_hit_2 = _res_hit_T_26 ? _res_hit_T_27 : _res_hit_T_38; // @[PMP.scala:45:20, :71:16, :132:{8,61}] wire _res_ignore_T_2 = ~io_pmp_5_cfg_l_0; // @[PMP.scala:143:7, :164:29] wire res_ignore_2 = default_0 & _res_ignore_T_2; // @[PMP.scala:156:56, :164:{26,29}] wire [31:0] _res_aligned_straddlesLowerBound_T_36 = ~_res_aligned_straddlesLowerBound_T_35; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesLowerBound_T_37 = {_res_aligned_straddlesLowerBound_T_36[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesLowerBound_T_38 = ~_res_aligned_straddlesLowerBound_T_37; // @[PMP.scala:60:{27,48}] wire [25:0] _res_aligned_straddlesLowerBound_T_39 = _res_aligned_straddlesLowerBound_T_38[31:6]; // @[PMP.scala:60:27, :123:67] wire [25:0] _res_aligned_straddlesLowerBound_T_40 = _res_aligned_straddlesLowerBound_T_34 ^ _res_aligned_straddlesLowerBound_T_39; // @[PMP.scala:123:{35,49,67}] wire _res_aligned_straddlesLowerBound_T_41 = _res_aligned_straddlesLowerBound_T_40 == 26'h0; // @[PMP.scala:80:52, :81:54, :123:{49,67,82}] wire [31:0] _res_aligned_straddlesLowerBound_T_43 = ~_res_aligned_straddlesLowerBound_T_42; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesLowerBound_T_44 = {_res_aligned_straddlesLowerBound_T_43[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesLowerBound_T_45 = ~_res_aligned_straddlesLowerBound_T_44; // @[PMP.scala:60:{27,48}] wire [5:0] _res_aligned_straddlesLowerBound_T_46 = _res_aligned_straddlesLowerBound_T_45[5:0]; // @[PMP.scala:60:27, :123:108] wire [5:0] _res_aligned_straddlesLowerBound_T_48 = ~_res_aligned_straddlesLowerBound_T_47; // @[PMP.scala:123:{127,129}] wire [5:0] _res_aligned_straddlesLowerBound_T_49 = _res_aligned_straddlesLowerBound_T_46 & _res_aligned_straddlesLowerBound_T_48; // @[PMP.scala:123:{108,125,127}] wire _res_aligned_straddlesLowerBound_T_50 = |_res_aligned_straddlesLowerBound_T_49; // @[PMP.scala:123:{125,147}] wire res_aligned_straddlesLowerBound_2 = _res_aligned_straddlesLowerBound_T_41 & _res_aligned_straddlesLowerBound_T_50; // @[PMP.scala:123:{82,90,147}] wire [31:0] _res_aligned_straddlesUpperBound_T_36 = ~_res_aligned_straddlesUpperBound_T_35; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesUpperBound_T_37 = {_res_aligned_straddlesUpperBound_T_36[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesUpperBound_T_38 = ~_res_aligned_straddlesUpperBound_T_37; // @[PMP.scala:60:{27,48}] wire [25:0] _res_aligned_straddlesUpperBound_T_39 = _res_aligned_straddlesUpperBound_T_38[31:6]; // @[PMP.scala:60:27, :124:62] wire [25:0] _res_aligned_straddlesUpperBound_T_40 = _res_aligned_straddlesUpperBound_T_34 ^ _res_aligned_straddlesUpperBound_T_39; // @[PMP.scala:124:{35,49,62}] wire _res_aligned_straddlesUpperBound_T_41 = _res_aligned_straddlesUpperBound_T_40 == 26'h0; // @[PMP.scala:80:52, :81:54, :123:67, :124:{49,77}] wire [31:0] _res_aligned_straddlesUpperBound_T_43 = ~_res_aligned_straddlesUpperBound_T_42; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesUpperBound_T_44 = {_res_aligned_straddlesUpperBound_T_43[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesUpperBound_T_45 = ~_res_aligned_straddlesUpperBound_T_44; // @[PMP.scala:60:{27,48}] wire [5:0] _res_aligned_straddlesUpperBound_T_46 = _res_aligned_straddlesUpperBound_T_45[5:0]; // @[PMP.scala:60:27, :124:98] wire [5:0] _res_aligned_straddlesUpperBound_T_48 = _res_aligned_straddlesUpperBound_T_47; // @[PMP.scala:124:{119,136}] wire [5:0] _res_aligned_straddlesUpperBound_T_49 = _res_aligned_straddlesUpperBound_T_46 & _res_aligned_straddlesUpperBound_T_48; // @[PMP.scala:124:{98,115,136}] wire _res_aligned_straddlesUpperBound_T_50 = |_res_aligned_straddlesUpperBound_T_49; // @[PMP.scala:124:{115,148}] wire res_aligned_straddlesUpperBound_2 = _res_aligned_straddlesUpperBound_T_41 & _res_aligned_straddlesUpperBound_T_50; // @[PMP.scala:124:{77,85,148}] wire _res_aligned_rangeAligned_T_2 = res_aligned_straddlesLowerBound_2 | res_aligned_straddlesUpperBound_2; // @[PMP.scala:123:90, :124:85, :125:46] wire res_aligned_rangeAligned_2 = ~_res_aligned_rangeAligned_T_2; // @[PMP.scala:125:{24,46}] wire [5:0] _res_aligned_pow2Aligned_T_7 = ~_res_aligned_pow2Aligned_T_6; // @[PMP.scala:126:{34,39}] wire res_aligned_2 = _res_aligned_T_2 | res_aligned_rangeAligned_2; // @[PMP.scala:45:20, :125:24, :127:8] wire _res_T_90 = io_pmp_5_cfg_a_0 == 2'h0; // @[PMP.scala:143:7, :168:32] wire _GEN_11 = io_pmp_5_cfg_a_0 == 2'h1; // @[PMP.scala:143:7, :168:32] wire _res_T_91; // @[PMP.scala:168:32] assign _res_T_91 = _GEN_11; // @[PMP.scala:168:32] wire _res_T_110; // @[PMP.scala:177:61] assign _res_T_110 = _GEN_11; // @[PMP.scala:168:32, :177:61] wire _res_T_114; // @[PMP.scala:178:63] assign _res_T_114 = _GEN_11; // @[PMP.scala:168:32, :178:63] wire _GEN_12 = io_pmp_5_cfg_a_0 == 2'h2; // @[PMP.scala:143:7, :168:32] wire _res_T_92; // @[PMP.scala:168:32] assign _res_T_92 = _GEN_12; // @[PMP.scala:168:32] wire _res_T_119; // @[PMP.scala:177:61] assign _res_T_119 = _GEN_12; // @[PMP.scala:168:32, :177:61] wire _res_T_123; // @[PMP.scala:178:63] assign _res_T_123 = _GEN_12; // @[PMP.scala:168:32, :178:63] wire _res_T_93 = &io_pmp_5_cfg_a_0; // @[PMP.scala:143:7, :168:32] wire [1:0] _GEN_13 = {io_pmp_5_cfg_x_0, io_pmp_5_cfg_w_0}; // @[PMP.scala:143:7, :174:26] wire [1:0] res_hi_12; // @[PMP.scala:174:26] assign res_hi_12 = _GEN_13; // @[PMP.scala:174:26] wire [1:0] res_hi_13; // @[PMP.scala:174:26] assign res_hi_13 = _GEN_13; // @[PMP.scala:174:26] wire [1:0] res_hi_14; // @[PMP.scala:174:26] assign res_hi_14 = _GEN_13; // @[PMP.scala:174:26] wire [1:0] res_hi_15; // @[PMP.scala:174:26] assign res_hi_15 = _GEN_13; // @[PMP.scala:174:26] wire [1:0] res_hi_16; // @[PMP.scala:174:26] assign res_hi_16 = _GEN_13; // @[PMP.scala:174:26] wire [1:0] res_hi_17; // @[PMP.scala:174:26] assign res_hi_17 = _GEN_13; // @[PMP.scala:174:26] wire [2:0] _res_T_95 = {res_hi_12, io_pmp_5_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_96 = _res_T_95 == 3'h0; // @[PMP.scala:143:7, :146:14, :174:{26,60}] wire [2:0] _res_T_97 = {res_hi_13, io_pmp_5_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_98 = _res_T_97 == 3'h1; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_99 = {res_hi_14, io_pmp_5_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_100 = _res_T_99 == 3'h3; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_101 = {res_hi_15, io_pmp_5_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_102 = _res_T_101 == 3'h4; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_103 = {res_hi_16, io_pmp_5_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_104 = _res_T_103 == 3'h5; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_105 = {res_hi_17, io_pmp_5_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_106 = &_res_T_105; // @[PMP.scala:174:{26,60}] wire _res_T_107 = ~res_ignore_2; // @[PMP.scala:164:26, :177:22] wire _res_T_108 = _res_T_107 & res_hit_2; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_109 = _res_T_108 & res_aligned_2; // @[PMP.scala:127:8, :177:{30,37}] wire _res_T_111 = _res_T_109 & _res_T_110; // @[PMP.scala:177:{37,48,61}] wire _GEN_14 = io_pmp_5_cfg_l_0 & res_hit_2; // @[PMP.scala:132:8, :143:7, :178:32] wire _res_T_112; // @[PMP.scala:178:32] assign _res_T_112 = _GEN_14; // @[PMP.scala:178:32] wire _res_T_121; // @[PMP.scala:178:32] assign _res_T_121 = _GEN_14; // @[PMP.scala:178:32] wire _res_T_130; // @[PMP.scala:178:32] assign _res_T_130 = _GEN_14; // @[PMP.scala:178:32] wire _res_T_113 = _res_T_112 & res_aligned_2; // @[PMP.scala:127:8, :178:{32,39}] wire _res_T_115 = _res_T_113 & _res_T_114; // @[PMP.scala:178:{39,50,63}] wire _res_T_116 = ~res_ignore_2; // @[PMP.scala:164:26, :177:22] wire _res_T_117 = _res_T_116 & res_hit_2; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_118 = _res_T_117 & res_aligned_2; // @[PMP.scala:127:8, :177:{30,37}] wire _res_T_120 = _res_T_118 & _res_T_119; // @[PMP.scala:177:{37,48,61}] wire _res_T_122 = _res_T_121 & res_aligned_2; // @[PMP.scala:127:8, :178:{32,39}] wire _res_T_124 = _res_T_122 & _res_T_123; // @[PMP.scala:178:{39,50,63}] wire _res_T_125 = ~res_ignore_2; // @[PMP.scala:164:26, :177:22] wire _res_T_126 = _res_T_125 & res_hit_2; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_127 = _res_T_126 & res_aligned_2; // @[PMP.scala:127:8, :177:{30,37}] wire _res_T_128 = &io_pmp_5_cfg_a_0; // @[PMP.scala:143:7, :168:32, :177:61] wire _res_T_129 = _res_T_127 & _res_T_128; // @[PMP.scala:177:{37,48,61}] wire _res_T_131 = _res_T_130 & res_aligned_2; // @[PMP.scala:127:8, :178:{32,39}] wire _res_T_132 = &io_pmp_5_cfg_a_0; // @[PMP.scala:143:7, :168:32, :178:63] wire _res_T_133 = _res_T_131 & _res_T_132; // @[PMP.scala:178:{39,50,63}] wire _res_cur_cfg_x_T_5; // @[PMP.scala:184:26] wire _res_cur_cfg_w_T_5; // @[PMP.scala:183:26] wire _res_cur_cfg_r_T_5; // @[PMP.scala:182:26] wire res_cur_2_cfg_x; // @[PMP.scala:181:23] wire res_cur_2_cfg_w; // @[PMP.scala:181:23] wire res_cur_2_cfg_r; // @[PMP.scala:181:23] wire _res_cur_cfg_r_T_4 = io_pmp_5_cfg_r_0 | res_ignore_2; // @[PMP.scala:143:7, :164:26, :182:40] assign _res_cur_cfg_r_T_5 = res_aligned_2 & _res_cur_cfg_r_T_4; // @[PMP.scala:127:8, :182:{26,40}] assign res_cur_2_cfg_r = _res_cur_cfg_r_T_5; // @[PMP.scala:181:23, :182:26] wire _res_cur_cfg_w_T_4 = io_pmp_5_cfg_w_0 | res_ignore_2; // @[PMP.scala:143:7, :164:26, :183:40] assign _res_cur_cfg_w_T_5 = res_aligned_2 & _res_cur_cfg_w_T_4; // @[PMP.scala:127:8, :183:{26,40}] assign res_cur_2_cfg_w = _res_cur_cfg_w_T_5; // @[PMP.scala:181:23, :183:26] wire _res_cur_cfg_x_T_4 = io_pmp_5_cfg_x_0 | res_ignore_2; // @[PMP.scala:143:7, :164:26, :184:40] assign _res_cur_cfg_x_T_5 = res_aligned_2 & _res_cur_cfg_x_T_4; // @[PMP.scala:127:8, :184:{26,40}] assign res_cur_2_cfg_x = _res_cur_cfg_x_T_5; // @[PMP.scala:181:23, :184:26] wire _res_T_134_cfg_l = res_hit_2 ? res_cur_2_cfg_l : _res_T_89_cfg_l; // @[PMP.scala:132:8, :181:23, :185:8] wire [1:0] _res_T_134_cfg_a = res_hit_2 ? res_cur_2_cfg_a : _res_T_89_cfg_a; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_T_134_cfg_x = res_hit_2 ? res_cur_2_cfg_x : _res_T_89_cfg_x; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_T_134_cfg_w = res_hit_2 ? res_cur_2_cfg_w : _res_T_89_cfg_w; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_T_134_cfg_r = res_hit_2 ? res_cur_2_cfg_r : _res_T_89_cfg_r; // @[PMP.scala:132:8, :181:23, :185:8] wire [29:0] _res_T_134_addr = res_hit_2 ? res_cur_2_addr : _res_T_89_addr; // @[PMP.scala:132:8, :181:23, :185:8] wire [31:0] _res_T_134_mask = res_hit_2 ? res_cur_2_mask : _res_T_89_mask; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_hit_T_39 = io_pmp_4_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7] wire _res_aligned_T_3 = io_pmp_4_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7] wire [25:0] _res_hit_msbMatch_T_36 = io_pmp_4_mask_0[31:6]; // @[PMP.scala:68:26, :69:72, :143:7] wire [5:0] _res_aligned_pow2Aligned_T_9 = io_pmp_4_mask_0[5:0]; // @[PMP.scala:68:26, :126:39, :143:7] wire [31:0] _res_hit_msbMatch_T_32 = ~_res_hit_msbMatch_T_31; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbMatch_T_33 = {_res_hit_msbMatch_T_32[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbMatch_T_34 = ~_res_hit_msbMatch_T_33; // @[PMP.scala:60:{27,48}] wire [25:0] _res_hit_msbMatch_T_35 = _res_hit_msbMatch_T_34[31:6]; // @[PMP.scala:60:27, :69:53] wire [25:0] _res_hit_msbMatch_T_37 = _res_hit_msbMatch_T_30 ^ _res_hit_msbMatch_T_35; // @[PMP.scala:63:47, :69:{29,53}] wire [25:0] _res_hit_msbMatch_T_38 = ~_res_hit_msbMatch_T_36; // @[PMP.scala:63:54, :69:72] wire [25:0] _res_hit_msbMatch_T_39 = _res_hit_msbMatch_T_37 & _res_hit_msbMatch_T_38; // @[PMP.scala:63:{47,52,54}] wire res_hit_msbMatch_3 = _res_hit_msbMatch_T_39 == 26'h0; // @[PMP.scala:63:{52,58}, :80:52, :81:54, :123:67] wire [31:0] _res_hit_lsbMatch_T_32 = ~_res_hit_lsbMatch_T_31; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_lsbMatch_T_33 = {_res_hit_lsbMatch_T_32[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbMatch_T_34 = ~_res_hit_lsbMatch_T_33; // @[PMP.scala:60:{27,48}] wire [5:0] _res_hit_lsbMatch_T_35 = _res_hit_lsbMatch_T_34[5:0]; // @[PMP.scala:60:27, :70:55] wire [5:0] _res_hit_lsbMatch_T_36 = res_hit_lsbMask_3[5:0]; // @[PMP.scala:68:26, :70:80] wire [5:0] _res_hit_lsbMatch_T_37 = _res_hit_lsbMatch_T_30 ^ _res_hit_lsbMatch_T_35; // @[PMP.scala:63:47, :70:{28,55}] wire [5:0] _res_hit_lsbMatch_T_38 = ~_res_hit_lsbMatch_T_36; // @[PMP.scala:63:54, :70:80] wire [5:0] _res_hit_lsbMatch_T_39 = _res_hit_lsbMatch_T_37 & _res_hit_lsbMatch_T_38; // @[PMP.scala:63:{47,52,54}] wire res_hit_lsbMatch_3 = _res_hit_lsbMatch_T_39 == 6'h0; // @[PMP.scala:63:{52,58}] wire _res_hit_T_40 = res_hit_msbMatch_3 & res_hit_lsbMatch_3; // @[PMP.scala:63:58, :71:16] wire _res_hit_T_41 = io_pmp_4_cfg_a_0[0]; // @[PMP.scala:46:26, :143:7] wire [31:0] _GEN_15 = {io_pmp_3_addr_0, 2'h0}; // @[PMP.scala:60:36, :143:7] wire [31:0] _res_hit_msbsLess_T_37; // @[PMP.scala:60:36] assign _res_hit_msbsLess_T_37 = _GEN_15; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsEqual_T_43; // @[PMP.scala:60:36] assign _res_hit_msbsEqual_T_43 = _GEN_15; // @[PMP.scala:60:36] wire [31:0] _res_hit_lsbsLess_T_44; // @[PMP.scala:60:36] assign _res_hit_lsbsLess_T_44 = _GEN_15; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesLowerBound_T_52; // @[PMP.scala:60:36] assign _res_aligned_straddlesLowerBound_T_52 = _GEN_15; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesLowerBound_T_59; // @[PMP.scala:60:36] assign _res_aligned_straddlesLowerBound_T_59 = _GEN_15; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbMatch_T_41; // @[PMP.scala:60:36] assign _res_hit_msbMatch_T_41 = _GEN_15; // @[PMP.scala:60:36] wire [31:0] _res_hit_lsbMatch_T_41; // @[PMP.scala:60:36] assign _res_hit_lsbMatch_T_41 = _GEN_15; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsLess_T_55; // @[PMP.scala:60:36] assign _res_hit_msbsLess_T_55 = _GEN_15; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsEqual_T_64; // @[PMP.scala:60:36] assign _res_hit_msbsEqual_T_64 = _GEN_15; // @[PMP.scala:60:36] wire [31:0] _res_hit_lsbsLess_T_65; // @[PMP.scala:60:36] assign _res_hit_lsbsLess_T_65 = _GEN_15; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesUpperBound_T_69; // @[PMP.scala:60:36] assign _res_aligned_straddlesUpperBound_T_69 = _GEN_15; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesUpperBound_T_76; // @[PMP.scala:60:36] assign _res_aligned_straddlesUpperBound_T_76 = _GEN_15; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsLess_T_38 = ~_res_hit_msbsLess_T_37; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsLess_T_39 = {_res_hit_msbsLess_T_38[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsLess_T_40 = ~_res_hit_msbsLess_T_39; // @[PMP.scala:60:{27,48}] wire [25:0] _res_hit_msbsLess_T_41 = _res_hit_msbsLess_T_40[31:6]; // @[PMP.scala:60:27, :80:52] wire res_hit_msbsLess_6 = _res_hit_msbsLess_T_36 < _res_hit_msbsLess_T_41; // @[PMP.scala:80:{25,39,52}] wire [31:0] _res_hit_msbsEqual_T_44 = ~_res_hit_msbsEqual_T_43; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsEqual_T_45 = {_res_hit_msbsEqual_T_44[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsEqual_T_46 = ~_res_hit_msbsEqual_T_45; // @[PMP.scala:60:{27,48}] wire [25:0] _res_hit_msbsEqual_T_47 = _res_hit_msbsEqual_T_46[31:6]; // @[PMP.scala:60:27, :81:54] wire [25:0] _res_hit_msbsEqual_T_48 = _res_hit_msbsEqual_T_42 ^ _res_hit_msbsEqual_T_47; // @[PMP.scala:81:{27,41,54}] wire res_hit_msbsEqual_6 = _res_hit_msbsEqual_T_48 == 26'h0; // @[PMP.scala:80:52, :81:{41,54,69}, :123:67] wire [5:0] _res_hit_lsbsLess_T_43 = _res_hit_lsbsLess_T_42; // @[PMP.scala:82:{25,42}] wire [31:0] _res_hit_lsbsLess_T_45 = ~_res_hit_lsbsLess_T_44; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_lsbsLess_T_46 = {_res_hit_lsbsLess_T_45[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbsLess_T_47 = ~_res_hit_lsbsLess_T_46; // @[PMP.scala:60:{27,48}] wire [5:0] _res_hit_lsbsLess_T_48 = _res_hit_lsbsLess_T_47[5:0]; // @[PMP.scala:60:27, :82:64] wire res_hit_lsbsLess_6 = _res_hit_lsbsLess_T_43 < _res_hit_lsbsLess_T_48; // @[PMP.scala:82:{42,53,64}] wire _res_hit_T_45 = res_hit_msbsEqual_6 & res_hit_lsbsLess_6; // @[PMP.scala:81:69, :82:53, :83:30] wire _res_hit_T_46 = res_hit_msbsLess_6 | _res_hit_T_45; // @[PMP.scala:80:39, :83:{16,30}] wire _res_hit_T_47 = ~_res_hit_T_46; // @[PMP.scala:83:16, :88:5] wire [31:0] _res_hit_msbsLess_T_44 = ~_res_hit_msbsLess_T_43; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsLess_T_45 = {_res_hit_msbsLess_T_44[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsLess_T_46 = ~_res_hit_msbsLess_T_45; // @[PMP.scala:60:{27,48}] wire [25:0] _res_hit_msbsLess_T_47 = _res_hit_msbsLess_T_46[31:6]; // @[PMP.scala:60:27, :80:52] wire res_hit_msbsLess_7 = _res_hit_msbsLess_T_42 < _res_hit_msbsLess_T_47; // @[PMP.scala:80:{25,39,52}] wire [31:0] _res_hit_msbsEqual_T_51 = ~_res_hit_msbsEqual_T_50; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsEqual_T_52 = {_res_hit_msbsEqual_T_51[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsEqual_T_53 = ~_res_hit_msbsEqual_T_52; // @[PMP.scala:60:{27,48}] wire [25:0] _res_hit_msbsEqual_T_54 = _res_hit_msbsEqual_T_53[31:6]; // @[PMP.scala:60:27, :81:54] wire [25:0] _res_hit_msbsEqual_T_55 = _res_hit_msbsEqual_T_49 ^ _res_hit_msbsEqual_T_54; // @[PMP.scala:81:{27,41,54}] wire res_hit_msbsEqual_7 = _res_hit_msbsEqual_T_55 == 26'h0; // @[PMP.scala:80:52, :81:{41,54,69}, :123:67] wire [5:0] _res_hit_lsbsLess_T_50 = _res_hit_lsbsLess_T_49; // @[PMP.scala:82:{25,42}] wire [31:0] _res_hit_lsbsLess_T_52 = ~_res_hit_lsbsLess_T_51; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_lsbsLess_T_53 = {_res_hit_lsbsLess_T_52[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbsLess_T_54 = ~_res_hit_lsbsLess_T_53; // @[PMP.scala:60:{27,48}] wire [5:0] _res_hit_lsbsLess_T_55 = _res_hit_lsbsLess_T_54[5:0]; // @[PMP.scala:60:27, :82:64] wire res_hit_lsbsLess_7 = _res_hit_lsbsLess_T_50 < _res_hit_lsbsLess_T_55; // @[PMP.scala:82:{42,53,64}] wire _res_hit_T_48 = res_hit_msbsEqual_7 & res_hit_lsbsLess_7; // @[PMP.scala:81:69, :82:53, :83:30] wire _res_hit_T_49 = res_hit_msbsLess_7 | _res_hit_T_48; // @[PMP.scala:80:39, :83:{16,30}] wire _res_hit_T_50 = _res_hit_T_47 & _res_hit_T_49; // @[PMP.scala:83:16, :88:5, :94:48] wire _res_hit_T_51 = _res_hit_T_41 & _res_hit_T_50; // @[PMP.scala:46:26, :94:48, :132:61] wire res_hit_3 = _res_hit_T_39 ? _res_hit_T_40 : _res_hit_T_51; // @[PMP.scala:45:20, :71:16, :132:{8,61}] wire _res_ignore_T_3 = ~io_pmp_4_cfg_l_0; // @[PMP.scala:143:7, :164:29] wire res_ignore_3 = default_0 & _res_ignore_T_3; // @[PMP.scala:156:56, :164:{26,29}] wire [31:0] _res_aligned_straddlesLowerBound_T_53 = ~_res_aligned_straddlesLowerBound_T_52; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesLowerBound_T_54 = {_res_aligned_straddlesLowerBound_T_53[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesLowerBound_T_55 = ~_res_aligned_straddlesLowerBound_T_54; // @[PMP.scala:60:{27,48}] wire [25:0] _res_aligned_straddlesLowerBound_T_56 = _res_aligned_straddlesLowerBound_T_55[31:6]; // @[PMP.scala:60:27, :123:67] wire [25:0] _res_aligned_straddlesLowerBound_T_57 = _res_aligned_straddlesLowerBound_T_51 ^ _res_aligned_straddlesLowerBound_T_56; // @[PMP.scala:123:{35,49,67}] wire _res_aligned_straddlesLowerBound_T_58 = _res_aligned_straddlesLowerBound_T_57 == 26'h0; // @[PMP.scala:80:52, :81:54, :123:{49,67,82}] wire [31:0] _res_aligned_straddlesLowerBound_T_60 = ~_res_aligned_straddlesLowerBound_T_59; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesLowerBound_T_61 = {_res_aligned_straddlesLowerBound_T_60[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesLowerBound_T_62 = ~_res_aligned_straddlesLowerBound_T_61; // @[PMP.scala:60:{27,48}] wire [5:0] _res_aligned_straddlesLowerBound_T_63 = _res_aligned_straddlesLowerBound_T_62[5:0]; // @[PMP.scala:60:27, :123:108] wire [5:0] _res_aligned_straddlesLowerBound_T_65 = ~_res_aligned_straddlesLowerBound_T_64; // @[PMP.scala:123:{127,129}] wire [5:0] _res_aligned_straddlesLowerBound_T_66 = _res_aligned_straddlesLowerBound_T_63 & _res_aligned_straddlesLowerBound_T_65; // @[PMP.scala:123:{108,125,127}] wire _res_aligned_straddlesLowerBound_T_67 = |_res_aligned_straddlesLowerBound_T_66; // @[PMP.scala:123:{125,147}] wire res_aligned_straddlesLowerBound_3 = _res_aligned_straddlesLowerBound_T_58 & _res_aligned_straddlesLowerBound_T_67; // @[PMP.scala:123:{82,90,147}] wire [31:0] _res_aligned_straddlesUpperBound_T_53 = ~_res_aligned_straddlesUpperBound_T_52; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesUpperBound_T_54 = {_res_aligned_straddlesUpperBound_T_53[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesUpperBound_T_55 = ~_res_aligned_straddlesUpperBound_T_54; // @[PMP.scala:60:{27,48}] wire [25:0] _res_aligned_straddlesUpperBound_T_56 = _res_aligned_straddlesUpperBound_T_55[31:6]; // @[PMP.scala:60:27, :124:62] wire [25:0] _res_aligned_straddlesUpperBound_T_57 = _res_aligned_straddlesUpperBound_T_51 ^ _res_aligned_straddlesUpperBound_T_56; // @[PMP.scala:124:{35,49,62}] wire _res_aligned_straddlesUpperBound_T_58 = _res_aligned_straddlesUpperBound_T_57 == 26'h0; // @[PMP.scala:80:52, :81:54, :123:67, :124:{49,77}] wire [31:0] _res_aligned_straddlesUpperBound_T_60 = ~_res_aligned_straddlesUpperBound_T_59; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesUpperBound_T_61 = {_res_aligned_straddlesUpperBound_T_60[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesUpperBound_T_62 = ~_res_aligned_straddlesUpperBound_T_61; // @[PMP.scala:60:{27,48}] wire [5:0] _res_aligned_straddlesUpperBound_T_63 = _res_aligned_straddlesUpperBound_T_62[5:0]; // @[PMP.scala:60:27, :124:98] wire [5:0] _res_aligned_straddlesUpperBound_T_65 = _res_aligned_straddlesUpperBound_T_64; // @[PMP.scala:124:{119,136}] wire [5:0] _res_aligned_straddlesUpperBound_T_66 = _res_aligned_straddlesUpperBound_T_63 & _res_aligned_straddlesUpperBound_T_65; // @[PMP.scala:124:{98,115,136}] wire _res_aligned_straddlesUpperBound_T_67 = |_res_aligned_straddlesUpperBound_T_66; // @[PMP.scala:124:{115,148}] wire res_aligned_straddlesUpperBound_3 = _res_aligned_straddlesUpperBound_T_58 & _res_aligned_straddlesUpperBound_T_67; // @[PMP.scala:124:{77,85,148}] wire _res_aligned_rangeAligned_T_3 = res_aligned_straddlesLowerBound_3 | res_aligned_straddlesUpperBound_3; // @[PMP.scala:123:90, :124:85, :125:46] wire res_aligned_rangeAligned_3 = ~_res_aligned_rangeAligned_T_3; // @[PMP.scala:125:{24,46}] wire [5:0] _res_aligned_pow2Aligned_T_10 = ~_res_aligned_pow2Aligned_T_9; // @[PMP.scala:126:{34,39}] wire res_aligned_3 = _res_aligned_T_3 | res_aligned_rangeAligned_3; // @[PMP.scala:45:20, :125:24, :127:8] wire _res_T_135 = io_pmp_4_cfg_a_0 == 2'h0; // @[PMP.scala:143:7, :168:32] wire _GEN_16 = io_pmp_4_cfg_a_0 == 2'h1; // @[PMP.scala:143:7, :168:32] wire _res_T_136; // @[PMP.scala:168:32] assign _res_T_136 = _GEN_16; // @[PMP.scala:168:32] wire _res_T_155; // @[PMP.scala:177:61] assign _res_T_155 = _GEN_16; // @[PMP.scala:168:32, :177:61] wire _res_T_159; // @[PMP.scala:178:63] assign _res_T_159 = _GEN_16; // @[PMP.scala:168:32, :178:63] wire _GEN_17 = io_pmp_4_cfg_a_0 == 2'h2; // @[PMP.scala:143:7, :168:32] wire _res_T_137; // @[PMP.scala:168:32] assign _res_T_137 = _GEN_17; // @[PMP.scala:168:32] wire _res_T_164; // @[PMP.scala:177:61] assign _res_T_164 = _GEN_17; // @[PMP.scala:168:32, :177:61] wire _res_T_168; // @[PMP.scala:178:63] assign _res_T_168 = _GEN_17; // @[PMP.scala:168:32, :178:63] wire _res_T_138 = &io_pmp_4_cfg_a_0; // @[PMP.scala:143:7, :168:32] wire [1:0] _GEN_18 = {io_pmp_4_cfg_x_0, io_pmp_4_cfg_w_0}; // @[PMP.scala:143:7, :174:26] wire [1:0] res_hi_18; // @[PMP.scala:174:26] assign res_hi_18 = _GEN_18; // @[PMP.scala:174:26] wire [1:0] res_hi_19; // @[PMP.scala:174:26] assign res_hi_19 = _GEN_18; // @[PMP.scala:174:26] wire [1:0] res_hi_20; // @[PMP.scala:174:26] assign res_hi_20 = _GEN_18; // @[PMP.scala:174:26] wire [1:0] res_hi_21; // @[PMP.scala:174:26] assign res_hi_21 = _GEN_18; // @[PMP.scala:174:26] wire [1:0] res_hi_22; // @[PMP.scala:174:26] assign res_hi_22 = _GEN_18; // @[PMP.scala:174:26] wire [1:0] res_hi_23; // @[PMP.scala:174:26] assign res_hi_23 = _GEN_18; // @[PMP.scala:174:26] wire [2:0] _res_T_140 = {res_hi_18, io_pmp_4_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_141 = _res_T_140 == 3'h0; // @[PMP.scala:143:7, :146:14, :174:{26,60}] wire [2:0] _res_T_142 = {res_hi_19, io_pmp_4_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_143 = _res_T_142 == 3'h1; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_144 = {res_hi_20, io_pmp_4_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_145 = _res_T_144 == 3'h3; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_146 = {res_hi_21, io_pmp_4_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_147 = _res_T_146 == 3'h4; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_148 = {res_hi_22, io_pmp_4_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_149 = _res_T_148 == 3'h5; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_150 = {res_hi_23, io_pmp_4_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_151 = &_res_T_150; // @[PMP.scala:174:{26,60}] wire _res_T_152 = ~res_ignore_3; // @[PMP.scala:164:26, :177:22] wire _res_T_153 = _res_T_152 & res_hit_3; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_154 = _res_T_153 & res_aligned_3; // @[PMP.scala:127:8, :177:{30,37}] wire _res_T_156 = _res_T_154 & _res_T_155; // @[PMP.scala:177:{37,48,61}] wire _GEN_19 = io_pmp_4_cfg_l_0 & res_hit_3; // @[PMP.scala:132:8, :143:7, :178:32] wire _res_T_157; // @[PMP.scala:178:32] assign _res_T_157 = _GEN_19; // @[PMP.scala:178:32] wire _res_T_166; // @[PMP.scala:178:32] assign _res_T_166 = _GEN_19; // @[PMP.scala:178:32] wire _res_T_175; // @[PMP.scala:178:32] assign _res_T_175 = _GEN_19; // @[PMP.scala:178:32] wire _res_T_158 = _res_T_157 & res_aligned_3; // @[PMP.scala:127:8, :178:{32,39}] wire _res_T_160 = _res_T_158 & _res_T_159; // @[PMP.scala:178:{39,50,63}] wire _res_T_161 = ~res_ignore_3; // @[PMP.scala:164:26, :177:22] wire _res_T_162 = _res_T_161 & res_hit_3; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_163 = _res_T_162 & res_aligned_3; // @[PMP.scala:127:8, :177:{30,37}] wire _res_T_165 = _res_T_163 & _res_T_164; // @[PMP.scala:177:{37,48,61}] wire _res_T_167 = _res_T_166 & res_aligned_3; // @[PMP.scala:127:8, :178:{32,39}] wire _res_T_169 = _res_T_167 & _res_T_168; // @[PMP.scala:178:{39,50,63}] wire _res_T_170 = ~res_ignore_3; // @[PMP.scala:164:26, :177:22] wire _res_T_171 = _res_T_170 & res_hit_3; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_172 = _res_T_171 & res_aligned_3; // @[PMP.scala:127:8, :177:{30,37}] wire _res_T_173 = &io_pmp_4_cfg_a_0; // @[PMP.scala:143:7, :168:32, :177:61] wire _res_T_174 = _res_T_172 & _res_T_173; // @[PMP.scala:177:{37,48,61}] wire _res_T_176 = _res_T_175 & res_aligned_3; // @[PMP.scala:127:8, :178:{32,39}] wire _res_T_177 = &io_pmp_4_cfg_a_0; // @[PMP.scala:143:7, :168:32, :178:63] wire _res_T_178 = _res_T_176 & _res_T_177; // @[PMP.scala:178:{39,50,63}] wire _res_cur_cfg_x_T_7; // @[PMP.scala:184:26] wire _res_cur_cfg_w_T_7; // @[PMP.scala:183:26] wire _res_cur_cfg_r_T_7; // @[PMP.scala:182:26] wire res_cur_3_cfg_x; // @[PMP.scala:181:23] wire res_cur_3_cfg_w; // @[PMP.scala:181:23] wire res_cur_3_cfg_r; // @[PMP.scala:181:23] wire _res_cur_cfg_r_T_6 = io_pmp_4_cfg_r_0 | res_ignore_3; // @[PMP.scala:143:7, :164:26, :182:40] assign _res_cur_cfg_r_T_7 = res_aligned_3 & _res_cur_cfg_r_T_6; // @[PMP.scala:127:8, :182:{26,40}] assign res_cur_3_cfg_r = _res_cur_cfg_r_T_7; // @[PMP.scala:181:23, :182:26] wire _res_cur_cfg_w_T_6 = io_pmp_4_cfg_w_0 | res_ignore_3; // @[PMP.scala:143:7, :164:26, :183:40] assign _res_cur_cfg_w_T_7 = res_aligned_3 & _res_cur_cfg_w_T_6; // @[PMP.scala:127:8, :183:{26,40}] assign res_cur_3_cfg_w = _res_cur_cfg_w_T_7; // @[PMP.scala:181:23, :183:26] wire _res_cur_cfg_x_T_6 = io_pmp_4_cfg_x_0 | res_ignore_3; // @[PMP.scala:143:7, :164:26, :184:40] assign _res_cur_cfg_x_T_7 = res_aligned_3 & _res_cur_cfg_x_T_6; // @[PMP.scala:127:8, :184:{26,40}] assign res_cur_3_cfg_x = _res_cur_cfg_x_T_7; // @[PMP.scala:181:23, :184:26] wire _res_T_179_cfg_l = res_hit_3 ? res_cur_3_cfg_l : _res_T_134_cfg_l; // @[PMP.scala:132:8, :181:23, :185:8] wire [1:0] _res_T_179_cfg_a = res_hit_3 ? res_cur_3_cfg_a : _res_T_134_cfg_a; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_T_179_cfg_x = res_hit_3 ? res_cur_3_cfg_x : _res_T_134_cfg_x; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_T_179_cfg_w = res_hit_3 ? res_cur_3_cfg_w : _res_T_134_cfg_w; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_T_179_cfg_r = res_hit_3 ? res_cur_3_cfg_r : _res_T_134_cfg_r; // @[PMP.scala:132:8, :181:23, :185:8] wire [29:0] _res_T_179_addr = res_hit_3 ? res_cur_3_addr : _res_T_134_addr; // @[PMP.scala:132:8, :181:23, :185:8] wire [31:0] _res_T_179_mask = res_hit_3 ? res_cur_3_mask : _res_T_134_mask; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_hit_T_52 = io_pmp_3_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7] wire _res_aligned_T_4 = io_pmp_3_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7] wire [25:0] _res_hit_msbMatch_T_46 = io_pmp_3_mask_0[31:6]; // @[PMP.scala:68:26, :69:72, :143:7] wire [5:0] _res_aligned_pow2Aligned_T_12 = io_pmp_3_mask_0[5:0]; // @[PMP.scala:68:26, :126:39, :143:7] wire [31:0] _res_hit_msbMatch_T_42 = ~_res_hit_msbMatch_T_41; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbMatch_T_43 = {_res_hit_msbMatch_T_42[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbMatch_T_44 = ~_res_hit_msbMatch_T_43; // @[PMP.scala:60:{27,48}] wire [25:0] _res_hit_msbMatch_T_45 = _res_hit_msbMatch_T_44[31:6]; // @[PMP.scala:60:27, :69:53] wire [25:0] _res_hit_msbMatch_T_47 = _res_hit_msbMatch_T_40 ^ _res_hit_msbMatch_T_45; // @[PMP.scala:63:47, :69:{29,53}] wire [25:0] _res_hit_msbMatch_T_48 = ~_res_hit_msbMatch_T_46; // @[PMP.scala:63:54, :69:72] wire [25:0] _res_hit_msbMatch_T_49 = _res_hit_msbMatch_T_47 & _res_hit_msbMatch_T_48; // @[PMP.scala:63:{47,52,54}] wire res_hit_msbMatch_4 = _res_hit_msbMatch_T_49 == 26'h0; // @[PMP.scala:63:{52,58}, :80:52, :81:54, :123:67] wire [31:0] _res_hit_lsbMatch_T_42 = ~_res_hit_lsbMatch_T_41; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_lsbMatch_T_43 = {_res_hit_lsbMatch_T_42[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbMatch_T_44 = ~_res_hit_lsbMatch_T_43; // @[PMP.scala:60:{27,48}] wire [5:0] _res_hit_lsbMatch_T_45 = _res_hit_lsbMatch_T_44[5:0]; // @[PMP.scala:60:27, :70:55] wire [5:0] _res_hit_lsbMatch_T_46 = res_hit_lsbMask_4[5:0]; // @[PMP.scala:68:26, :70:80] wire [5:0] _res_hit_lsbMatch_T_47 = _res_hit_lsbMatch_T_40 ^ _res_hit_lsbMatch_T_45; // @[PMP.scala:63:47, :70:{28,55}] wire [5:0] _res_hit_lsbMatch_T_48 = ~_res_hit_lsbMatch_T_46; // @[PMP.scala:63:54, :70:80] wire [5:0] _res_hit_lsbMatch_T_49 = _res_hit_lsbMatch_T_47 & _res_hit_lsbMatch_T_48; // @[PMP.scala:63:{47,52,54}] wire res_hit_lsbMatch_4 = _res_hit_lsbMatch_T_49 == 6'h0; // @[PMP.scala:63:{52,58}] wire _res_hit_T_53 = res_hit_msbMatch_4 & res_hit_lsbMatch_4; // @[PMP.scala:63:58, :71:16] wire _res_hit_T_54 = io_pmp_3_cfg_a_0[0]; // @[PMP.scala:46:26, :143:7] wire [31:0] _GEN_20 = {io_pmp_2_addr_0, 2'h0}; // @[PMP.scala:60:36, :143:7] wire [31:0] _res_hit_msbsLess_T_49; // @[PMP.scala:60:36] assign _res_hit_msbsLess_T_49 = _GEN_20; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsEqual_T_57; // @[PMP.scala:60:36] assign _res_hit_msbsEqual_T_57 = _GEN_20; // @[PMP.scala:60:36] wire [31:0] _res_hit_lsbsLess_T_58; // @[PMP.scala:60:36] assign _res_hit_lsbsLess_T_58 = _GEN_20; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesLowerBound_T_69; // @[PMP.scala:60:36] assign _res_aligned_straddlesLowerBound_T_69 = _GEN_20; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesLowerBound_T_76; // @[PMP.scala:60:36] assign _res_aligned_straddlesLowerBound_T_76 = _GEN_20; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbMatch_T_51; // @[PMP.scala:60:36] assign _res_hit_msbMatch_T_51 = _GEN_20; // @[PMP.scala:60:36] wire [31:0] _res_hit_lsbMatch_T_51; // @[PMP.scala:60:36] assign _res_hit_lsbMatch_T_51 = _GEN_20; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsLess_T_67; // @[PMP.scala:60:36] assign _res_hit_msbsLess_T_67 = _GEN_20; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsEqual_T_78; // @[PMP.scala:60:36] assign _res_hit_msbsEqual_T_78 = _GEN_20; // @[PMP.scala:60:36] wire [31:0] _res_hit_lsbsLess_T_79; // @[PMP.scala:60:36] assign _res_hit_lsbsLess_T_79 = _GEN_20; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesUpperBound_T_86; // @[PMP.scala:60:36] assign _res_aligned_straddlesUpperBound_T_86 = _GEN_20; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesUpperBound_T_93; // @[PMP.scala:60:36] assign _res_aligned_straddlesUpperBound_T_93 = _GEN_20; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsLess_T_50 = ~_res_hit_msbsLess_T_49; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsLess_T_51 = {_res_hit_msbsLess_T_50[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsLess_T_52 = ~_res_hit_msbsLess_T_51; // @[PMP.scala:60:{27,48}] wire [25:0] _res_hit_msbsLess_T_53 = _res_hit_msbsLess_T_52[31:6]; // @[PMP.scala:60:27, :80:52] wire res_hit_msbsLess_8 = _res_hit_msbsLess_T_48 < _res_hit_msbsLess_T_53; // @[PMP.scala:80:{25,39,52}] wire [31:0] _res_hit_msbsEqual_T_58 = ~_res_hit_msbsEqual_T_57; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsEqual_T_59 = {_res_hit_msbsEqual_T_58[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsEqual_T_60 = ~_res_hit_msbsEqual_T_59; // @[PMP.scala:60:{27,48}] wire [25:0] _res_hit_msbsEqual_T_61 = _res_hit_msbsEqual_T_60[31:6]; // @[PMP.scala:60:27, :81:54] wire [25:0] _res_hit_msbsEqual_T_62 = _res_hit_msbsEqual_T_56 ^ _res_hit_msbsEqual_T_61; // @[PMP.scala:81:{27,41,54}] wire res_hit_msbsEqual_8 = _res_hit_msbsEqual_T_62 == 26'h0; // @[PMP.scala:80:52, :81:{41,54,69}, :123:67] wire [5:0] _res_hit_lsbsLess_T_57 = _res_hit_lsbsLess_T_56; // @[PMP.scala:82:{25,42}] wire [31:0] _res_hit_lsbsLess_T_59 = ~_res_hit_lsbsLess_T_58; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_lsbsLess_T_60 = {_res_hit_lsbsLess_T_59[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbsLess_T_61 = ~_res_hit_lsbsLess_T_60; // @[PMP.scala:60:{27,48}] wire [5:0] _res_hit_lsbsLess_T_62 = _res_hit_lsbsLess_T_61[5:0]; // @[PMP.scala:60:27, :82:64] wire res_hit_lsbsLess_8 = _res_hit_lsbsLess_T_57 < _res_hit_lsbsLess_T_62; // @[PMP.scala:82:{42,53,64}] wire _res_hit_T_58 = res_hit_msbsEqual_8 & res_hit_lsbsLess_8; // @[PMP.scala:81:69, :82:53, :83:30] wire _res_hit_T_59 = res_hit_msbsLess_8 | _res_hit_T_58; // @[PMP.scala:80:39, :83:{16,30}] wire _res_hit_T_60 = ~_res_hit_T_59; // @[PMP.scala:83:16, :88:5] wire [31:0] _res_hit_msbsLess_T_56 = ~_res_hit_msbsLess_T_55; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsLess_T_57 = {_res_hit_msbsLess_T_56[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsLess_T_58 = ~_res_hit_msbsLess_T_57; // @[PMP.scala:60:{27,48}] wire [25:0] _res_hit_msbsLess_T_59 = _res_hit_msbsLess_T_58[31:6]; // @[PMP.scala:60:27, :80:52] wire res_hit_msbsLess_9 = _res_hit_msbsLess_T_54 < _res_hit_msbsLess_T_59; // @[PMP.scala:80:{25,39,52}] wire [31:0] _res_hit_msbsEqual_T_65 = ~_res_hit_msbsEqual_T_64; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsEqual_T_66 = {_res_hit_msbsEqual_T_65[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsEqual_T_67 = ~_res_hit_msbsEqual_T_66; // @[PMP.scala:60:{27,48}] wire [25:0] _res_hit_msbsEqual_T_68 = _res_hit_msbsEqual_T_67[31:6]; // @[PMP.scala:60:27, :81:54] wire [25:0] _res_hit_msbsEqual_T_69 = _res_hit_msbsEqual_T_63 ^ _res_hit_msbsEqual_T_68; // @[PMP.scala:81:{27,41,54}] wire res_hit_msbsEqual_9 = _res_hit_msbsEqual_T_69 == 26'h0; // @[PMP.scala:80:52, :81:{41,54,69}, :123:67] wire [5:0] _res_hit_lsbsLess_T_64 = _res_hit_lsbsLess_T_63; // @[PMP.scala:82:{25,42}] wire [31:0] _res_hit_lsbsLess_T_66 = ~_res_hit_lsbsLess_T_65; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_lsbsLess_T_67 = {_res_hit_lsbsLess_T_66[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbsLess_T_68 = ~_res_hit_lsbsLess_T_67; // @[PMP.scala:60:{27,48}] wire [5:0] _res_hit_lsbsLess_T_69 = _res_hit_lsbsLess_T_68[5:0]; // @[PMP.scala:60:27, :82:64] wire res_hit_lsbsLess_9 = _res_hit_lsbsLess_T_64 < _res_hit_lsbsLess_T_69; // @[PMP.scala:82:{42,53,64}] wire _res_hit_T_61 = res_hit_msbsEqual_9 & res_hit_lsbsLess_9; // @[PMP.scala:81:69, :82:53, :83:30] wire _res_hit_T_62 = res_hit_msbsLess_9 | _res_hit_T_61; // @[PMP.scala:80:39, :83:{16,30}] wire _res_hit_T_63 = _res_hit_T_60 & _res_hit_T_62; // @[PMP.scala:83:16, :88:5, :94:48] wire _res_hit_T_64 = _res_hit_T_54 & _res_hit_T_63; // @[PMP.scala:46:26, :94:48, :132:61] wire res_hit_4 = _res_hit_T_52 ? _res_hit_T_53 : _res_hit_T_64; // @[PMP.scala:45:20, :71:16, :132:{8,61}] wire _res_ignore_T_4 = ~io_pmp_3_cfg_l_0; // @[PMP.scala:143:7, :164:29] wire res_ignore_4 = default_0 & _res_ignore_T_4; // @[PMP.scala:156:56, :164:{26,29}] wire [31:0] _res_aligned_straddlesLowerBound_T_70 = ~_res_aligned_straddlesLowerBound_T_69; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesLowerBound_T_71 = {_res_aligned_straddlesLowerBound_T_70[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesLowerBound_T_72 = ~_res_aligned_straddlesLowerBound_T_71; // @[PMP.scala:60:{27,48}] wire [25:0] _res_aligned_straddlesLowerBound_T_73 = _res_aligned_straddlesLowerBound_T_72[31:6]; // @[PMP.scala:60:27, :123:67] wire [25:0] _res_aligned_straddlesLowerBound_T_74 = _res_aligned_straddlesLowerBound_T_68 ^ _res_aligned_straddlesLowerBound_T_73; // @[PMP.scala:123:{35,49,67}] wire _res_aligned_straddlesLowerBound_T_75 = _res_aligned_straddlesLowerBound_T_74 == 26'h0; // @[PMP.scala:80:52, :81:54, :123:{49,67,82}] wire [31:0] _res_aligned_straddlesLowerBound_T_77 = ~_res_aligned_straddlesLowerBound_T_76; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesLowerBound_T_78 = {_res_aligned_straddlesLowerBound_T_77[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesLowerBound_T_79 = ~_res_aligned_straddlesLowerBound_T_78; // @[PMP.scala:60:{27,48}] wire [5:0] _res_aligned_straddlesLowerBound_T_80 = _res_aligned_straddlesLowerBound_T_79[5:0]; // @[PMP.scala:60:27, :123:108] wire [5:0] _res_aligned_straddlesLowerBound_T_82 = ~_res_aligned_straddlesLowerBound_T_81; // @[PMP.scala:123:{127,129}] wire [5:0] _res_aligned_straddlesLowerBound_T_83 = _res_aligned_straddlesLowerBound_T_80 & _res_aligned_straddlesLowerBound_T_82; // @[PMP.scala:123:{108,125,127}] wire _res_aligned_straddlesLowerBound_T_84 = |_res_aligned_straddlesLowerBound_T_83; // @[PMP.scala:123:{125,147}] wire res_aligned_straddlesLowerBound_4 = _res_aligned_straddlesLowerBound_T_75 & _res_aligned_straddlesLowerBound_T_84; // @[PMP.scala:123:{82,90,147}] wire [31:0] _res_aligned_straddlesUpperBound_T_70 = ~_res_aligned_straddlesUpperBound_T_69; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesUpperBound_T_71 = {_res_aligned_straddlesUpperBound_T_70[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesUpperBound_T_72 = ~_res_aligned_straddlesUpperBound_T_71; // @[PMP.scala:60:{27,48}] wire [25:0] _res_aligned_straddlesUpperBound_T_73 = _res_aligned_straddlesUpperBound_T_72[31:6]; // @[PMP.scala:60:27, :124:62] wire [25:0] _res_aligned_straddlesUpperBound_T_74 = _res_aligned_straddlesUpperBound_T_68 ^ _res_aligned_straddlesUpperBound_T_73; // @[PMP.scala:124:{35,49,62}] wire _res_aligned_straddlesUpperBound_T_75 = _res_aligned_straddlesUpperBound_T_74 == 26'h0; // @[PMP.scala:80:52, :81:54, :123:67, :124:{49,77}] wire [31:0] _res_aligned_straddlesUpperBound_T_77 = ~_res_aligned_straddlesUpperBound_T_76; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesUpperBound_T_78 = {_res_aligned_straddlesUpperBound_T_77[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesUpperBound_T_79 = ~_res_aligned_straddlesUpperBound_T_78; // @[PMP.scala:60:{27,48}] wire [5:0] _res_aligned_straddlesUpperBound_T_80 = _res_aligned_straddlesUpperBound_T_79[5:0]; // @[PMP.scala:60:27, :124:98] wire [5:0] _res_aligned_straddlesUpperBound_T_82 = _res_aligned_straddlesUpperBound_T_81; // @[PMP.scala:124:{119,136}] wire [5:0] _res_aligned_straddlesUpperBound_T_83 = _res_aligned_straddlesUpperBound_T_80 & _res_aligned_straddlesUpperBound_T_82; // @[PMP.scala:124:{98,115,136}] wire _res_aligned_straddlesUpperBound_T_84 = |_res_aligned_straddlesUpperBound_T_83; // @[PMP.scala:124:{115,148}] wire res_aligned_straddlesUpperBound_4 = _res_aligned_straddlesUpperBound_T_75 & _res_aligned_straddlesUpperBound_T_84; // @[PMP.scala:124:{77,85,148}] wire _res_aligned_rangeAligned_T_4 = res_aligned_straddlesLowerBound_4 | res_aligned_straddlesUpperBound_4; // @[PMP.scala:123:90, :124:85, :125:46] wire res_aligned_rangeAligned_4 = ~_res_aligned_rangeAligned_T_4; // @[PMP.scala:125:{24,46}] wire [5:0] _res_aligned_pow2Aligned_T_13 = ~_res_aligned_pow2Aligned_T_12; // @[PMP.scala:126:{34,39}] wire res_aligned_4 = _res_aligned_T_4 | res_aligned_rangeAligned_4; // @[PMP.scala:45:20, :125:24, :127:8] wire _res_T_180 = io_pmp_3_cfg_a_0 == 2'h0; // @[PMP.scala:143:7, :168:32] wire _GEN_21 = io_pmp_3_cfg_a_0 == 2'h1; // @[PMP.scala:143:7, :168:32] wire _res_T_181; // @[PMP.scala:168:32] assign _res_T_181 = _GEN_21; // @[PMP.scala:168:32] wire _res_T_200; // @[PMP.scala:177:61] assign _res_T_200 = _GEN_21; // @[PMP.scala:168:32, :177:61] wire _res_T_204; // @[PMP.scala:178:63] assign _res_T_204 = _GEN_21; // @[PMP.scala:168:32, :178:63] wire _GEN_22 = io_pmp_3_cfg_a_0 == 2'h2; // @[PMP.scala:143:7, :168:32] wire _res_T_182; // @[PMP.scala:168:32] assign _res_T_182 = _GEN_22; // @[PMP.scala:168:32] wire _res_T_209; // @[PMP.scala:177:61] assign _res_T_209 = _GEN_22; // @[PMP.scala:168:32, :177:61] wire _res_T_213; // @[PMP.scala:178:63] assign _res_T_213 = _GEN_22; // @[PMP.scala:168:32, :178:63] wire _res_T_183 = &io_pmp_3_cfg_a_0; // @[PMP.scala:143:7, :168:32] wire [1:0] _GEN_23 = {io_pmp_3_cfg_x_0, io_pmp_3_cfg_w_0}; // @[PMP.scala:143:7, :174:26] wire [1:0] res_hi_24; // @[PMP.scala:174:26] assign res_hi_24 = _GEN_23; // @[PMP.scala:174:26] wire [1:0] res_hi_25; // @[PMP.scala:174:26] assign res_hi_25 = _GEN_23; // @[PMP.scala:174:26] wire [1:0] res_hi_26; // @[PMP.scala:174:26] assign res_hi_26 = _GEN_23; // @[PMP.scala:174:26] wire [1:0] res_hi_27; // @[PMP.scala:174:26] assign res_hi_27 = _GEN_23; // @[PMP.scala:174:26] wire [1:0] res_hi_28; // @[PMP.scala:174:26] assign res_hi_28 = _GEN_23; // @[PMP.scala:174:26] wire [1:0] res_hi_29; // @[PMP.scala:174:26] assign res_hi_29 = _GEN_23; // @[PMP.scala:174:26] wire [2:0] _res_T_185 = {res_hi_24, io_pmp_3_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_186 = _res_T_185 == 3'h0; // @[PMP.scala:143:7, :146:14, :174:{26,60}] wire [2:0] _res_T_187 = {res_hi_25, io_pmp_3_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_188 = _res_T_187 == 3'h1; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_189 = {res_hi_26, io_pmp_3_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_190 = _res_T_189 == 3'h3; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_191 = {res_hi_27, io_pmp_3_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_192 = _res_T_191 == 3'h4; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_193 = {res_hi_28, io_pmp_3_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_194 = _res_T_193 == 3'h5; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_195 = {res_hi_29, io_pmp_3_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_196 = &_res_T_195; // @[PMP.scala:174:{26,60}] wire _res_T_197 = ~res_ignore_4; // @[PMP.scala:164:26, :177:22] wire _res_T_198 = _res_T_197 & res_hit_4; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_199 = _res_T_198 & res_aligned_4; // @[PMP.scala:127:8, :177:{30,37}] wire _res_T_201 = _res_T_199 & _res_T_200; // @[PMP.scala:177:{37,48,61}] wire _GEN_24 = io_pmp_3_cfg_l_0 & res_hit_4; // @[PMP.scala:132:8, :143:7, :178:32] wire _res_T_202; // @[PMP.scala:178:32] assign _res_T_202 = _GEN_24; // @[PMP.scala:178:32] wire _res_T_211; // @[PMP.scala:178:32] assign _res_T_211 = _GEN_24; // @[PMP.scala:178:32] wire _res_T_220; // @[PMP.scala:178:32] assign _res_T_220 = _GEN_24; // @[PMP.scala:178:32] wire _res_T_203 = _res_T_202 & res_aligned_4; // @[PMP.scala:127:8, :178:{32,39}] wire _res_T_205 = _res_T_203 & _res_T_204; // @[PMP.scala:178:{39,50,63}] wire _res_T_206 = ~res_ignore_4; // @[PMP.scala:164:26, :177:22] wire _res_T_207 = _res_T_206 & res_hit_4; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_208 = _res_T_207 & res_aligned_4; // @[PMP.scala:127:8, :177:{30,37}] wire _res_T_210 = _res_T_208 & _res_T_209; // @[PMP.scala:177:{37,48,61}] wire _res_T_212 = _res_T_211 & res_aligned_4; // @[PMP.scala:127:8, :178:{32,39}] wire _res_T_214 = _res_T_212 & _res_T_213; // @[PMP.scala:178:{39,50,63}] wire _res_T_215 = ~res_ignore_4; // @[PMP.scala:164:26, :177:22] wire _res_T_216 = _res_T_215 & res_hit_4; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_217 = _res_T_216 & res_aligned_4; // @[PMP.scala:127:8, :177:{30,37}] wire _res_T_218 = &io_pmp_3_cfg_a_0; // @[PMP.scala:143:7, :168:32, :177:61] wire _res_T_219 = _res_T_217 & _res_T_218; // @[PMP.scala:177:{37,48,61}] wire _res_T_221 = _res_T_220 & res_aligned_4; // @[PMP.scala:127:8, :178:{32,39}] wire _res_T_222 = &io_pmp_3_cfg_a_0; // @[PMP.scala:143:7, :168:32, :178:63] wire _res_T_223 = _res_T_221 & _res_T_222; // @[PMP.scala:178:{39,50,63}] wire _res_cur_cfg_x_T_9; // @[PMP.scala:184:26] wire _res_cur_cfg_w_T_9; // @[PMP.scala:183:26] wire _res_cur_cfg_r_T_9; // @[PMP.scala:182:26] wire res_cur_4_cfg_x; // @[PMP.scala:181:23] wire res_cur_4_cfg_w; // @[PMP.scala:181:23] wire res_cur_4_cfg_r; // @[PMP.scala:181:23] wire _res_cur_cfg_r_T_8 = io_pmp_3_cfg_r_0 | res_ignore_4; // @[PMP.scala:143:7, :164:26, :182:40] assign _res_cur_cfg_r_T_9 = res_aligned_4 & _res_cur_cfg_r_T_8; // @[PMP.scala:127:8, :182:{26,40}] assign res_cur_4_cfg_r = _res_cur_cfg_r_T_9; // @[PMP.scala:181:23, :182:26] wire _res_cur_cfg_w_T_8 = io_pmp_3_cfg_w_0 | res_ignore_4; // @[PMP.scala:143:7, :164:26, :183:40] assign _res_cur_cfg_w_T_9 = res_aligned_4 & _res_cur_cfg_w_T_8; // @[PMP.scala:127:8, :183:{26,40}] assign res_cur_4_cfg_w = _res_cur_cfg_w_T_9; // @[PMP.scala:181:23, :183:26] wire _res_cur_cfg_x_T_8 = io_pmp_3_cfg_x_0 | res_ignore_4; // @[PMP.scala:143:7, :164:26, :184:40] assign _res_cur_cfg_x_T_9 = res_aligned_4 & _res_cur_cfg_x_T_8; // @[PMP.scala:127:8, :184:{26,40}] assign res_cur_4_cfg_x = _res_cur_cfg_x_T_9; // @[PMP.scala:181:23, :184:26] wire _res_T_224_cfg_l = res_hit_4 ? res_cur_4_cfg_l : _res_T_179_cfg_l; // @[PMP.scala:132:8, :181:23, :185:8] wire [1:0] _res_T_224_cfg_a = res_hit_4 ? res_cur_4_cfg_a : _res_T_179_cfg_a; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_T_224_cfg_x = res_hit_4 ? res_cur_4_cfg_x : _res_T_179_cfg_x; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_T_224_cfg_w = res_hit_4 ? res_cur_4_cfg_w : _res_T_179_cfg_w; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_T_224_cfg_r = res_hit_4 ? res_cur_4_cfg_r : _res_T_179_cfg_r; // @[PMP.scala:132:8, :181:23, :185:8] wire [29:0] _res_T_224_addr = res_hit_4 ? res_cur_4_addr : _res_T_179_addr; // @[PMP.scala:132:8, :181:23, :185:8] wire [31:0] _res_T_224_mask = res_hit_4 ? res_cur_4_mask : _res_T_179_mask; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_hit_T_65 = io_pmp_2_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7] wire _res_aligned_T_5 = io_pmp_2_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7] wire [25:0] _res_hit_msbMatch_T_56 = io_pmp_2_mask_0[31:6]; // @[PMP.scala:68:26, :69:72, :143:7] wire [5:0] _res_aligned_pow2Aligned_T_15 = io_pmp_2_mask_0[5:0]; // @[PMP.scala:68:26, :126:39, :143:7] wire [31:0] _res_hit_msbMatch_T_52 = ~_res_hit_msbMatch_T_51; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbMatch_T_53 = {_res_hit_msbMatch_T_52[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbMatch_T_54 = ~_res_hit_msbMatch_T_53; // @[PMP.scala:60:{27,48}] wire [25:0] _res_hit_msbMatch_T_55 = _res_hit_msbMatch_T_54[31:6]; // @[PMP.scala:60:27, :69:53] wire [25:0] _res_hit_msbMatch_T_57 = _res_hit_msbMatch_T_50 ^ _res_hit_msbMatch_T_55; // @[PMP.scala:63:47, :69:{29,53}] wire [25:0] _res_hit_msbMatch_T_58 = ~_res_hit_msbMatch_T_56; // @[PMP.scala:63:54, :69:72] wire [25:0] _res_hit_msbMatch_T_59 = _res_hit_msbMatch_T_57 & _res_hit_msbMatch_T_58; // @[PMP.scala:63:{47,52,54}] wire res_hit_msbMatch_5 = _res_hit_msbMatch_T_59 == 26'h0; // @[PMP.scala:63:{52,58}, :80:52, :81:54, :123:67] wire [31:0] _res_hit_lsbMatch_T_52 = ~_res_hit_lsbMatch_T_51; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_lsbMatch_T_53 = {_res_hit_lsbMatch_T_52[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbMatch_T_54 = ~_res_hit_lsbMatch_T_53; // @[PMP.scala:60:{27,48}] wire [5:0] _res_hit_lsbMatch_T_55 = _res_hit_lsbMatch_T_54[5:0]; // @[PMP.scala:60:27, :70:55] wire [5:0] _res_hit_lsbMatch_T_56 = res_hit_lsbMask_5[5:0]; // @[PMP.scala:68:26, :70:80] wire [5:0] _res_hit_lsbMatch_T_57 = _res_hit_lsbMatch_T_50 ^ _res_hit_lsbMatch_T_55; // @[PMP.scala:63:47, :70:{28,55}] wire [5:0] _res_hit_lsbMatch_T_58 = ~_res_hit_lsbMatch_T_56; // @[PMP.scala:63:54, :70:80] wire [5:0] _res_hit_lsbMatch_T_59 = _res_hit_lsbMatch_T_57 & _res_hit_lsbMatch_T_58; // @[PMP.scala:63:{47,52,54}] wire res_hit_lsbMatch_5 = _res_hit_lsbMatch_T_59 == 6'h0; // @[PMP.scala:63:{52,58}] wire _res_hit_T_66 = res_hit_msbMatch_5 & res_hit_lsbMatch_5; // @[PMP.scala:63:58, :71:16] wire _res_hit_T_67 = io_pmp_2_cfg_a_0[0]; // @[PMP.scala:46:26, :143:7] wire [31:0] _GEN_25 = {io_pmp_1_addr_0, 2'h0}; // @[PMP.scala:60:36, :143:7] wire [31:0] _res_hit_msbsLess_T_61; // @[PMP.scala:60:36] assign _res_hit_msbsLess_T_61 = _GEN_25; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsEqual_T_71; // @[PMP.scala:60:36] assign _res_hit_msbsEqual_T_71 = _GEN_25; // @[PMP.scala:60:36] wire [31:0] _res_hit_lsbsLess_T_72; // @[PMP.scala:60:36] assign _res_hit_lsbsLess_T_72 = _GEN_25; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesLowerBound_T_86; // @[PMP.scala:60:36] assign _res_aligned_straddlesLowerBound_T_86 = _GEN_25; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesLowerBound_T_93; // @[PMP.scala:60:36] assign _res_aligned_straddlesLowerBound_T_93 = _GEN_25; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbMatch_T_61; // @[PMP.scala:60:36] assign _res_hit_msbMatch_T_61 = _GEN_25; // @[PMP.scala:60:36] wire [31:0] _res_hit_lsbMatch_T_61; // @[PMP.scala:60:36] assign _res_hit_lsbMatch_T_61 = _GEN_25; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsLess_T_79; // @[PMP.scala:60:36] assign _res_hit_msbsLess_T_79 = _GEN_25; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsEqual_T_92; // @[PMP.scala:60:36] assign _res_hit_msbsEqual_T_92 = _GEN_25; // @[PMP.scala:60:36] wire [31:0] _res_hit_lsbsLess_T_93; // @[PMP.scala:60:36] assign _res_hit_lsbsLess_T_93 = _GEN_25; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesUpperBound_T_103; // @[PMP.scala:60:36] assign _res_aligned_straddlesUpperBound_T_103 = _GEN_25; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesUpperBound_T_110; // @[PMP.scala:60:36] assign _res_aligned_straddlesUpperBound_T_110 = _GEN_25; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsLess_T_62 = ~_res_hit_msbsLess_T_61; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsLess_T_63 = {_res_hit_msbsLess_T_62[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsLess_T_64 = ~_res_hit_msbsLess_T_63; // @[PMP.scala:60:{27,48}] wire [25:0] _res_hit_msbsLess_T_65 = _res_hit_msbsLess_T_64[31:6]; // @[PMP.scala:60:27, :80:52] wire res_hit_msbsLess_10 = _res_hit_msbsLess_T_60 < _res_hit_msbsLess_T_65; // @[PMP.scala:80:{25,39,52}] wire [31:0] _res_hit_msbsEqual_T_72 = ~_res_hit_msbsEqual_T_71; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsEqual_T_73 = {_res_hit_msbsEqual_T_72[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsEqual_T_74 = ~_res_hit_msbsEqual_T_73; // @[PMP.scala:60:{27,48}] wire [25:0] _res_hit_msbsEqual_T_75 = _res_hit_msbsEqual_T_74[31:6]; // @[PMP.scala:60:27, :81:54] wire [25:0] _res_hit_msbsEqual_T_76 = _res_hit_msbsEqual_T_70 ^ _res_hit_msbsEqual_T_75; // @[PMP.scala:81:{27,41,54}] wire res_hit_msbsEqual_10 = _res_hit_msbsEqual_T_76 == 26'h0; // @[PMP.scala:80:52, :81:{41,54,69}, :123:67] wire [5:0] _res_hit_lsbsLess_T_71 = _res_hit_lsbsLess_T_70; // @[PMP.scala:82:{25,42}] wire [31:0] _res_hit_lsbsLess_T_73 = ~_res_hit_lsbsLess_T_72; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_lsbsLess_T_74 = {_res_hit_lsbsLess_T_73[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbsLess_T_75 = ~_res_hit_lsbsLess_T_74; // @[PMP.scala:60:{27,48}] wire [5:0] _res_hit_lsbsLess_T_76 = _res_hit_lsbsLess_T_75[5:0]; // @[PMP.scala:60:27, :82:64] wire res_hit_lsbsLess_10 = _res_hit_lsbsLess_T_71 < _res_hit_lsbsLess_T_76; // @[PMP.scala:82:{42,53,64}] wire _res_hit_T_71 = res_hit_msbsEqual_10 & res_hit_lsbsLess_10; // @[PMP.scala:81:69, :82:53, :83:30] wire _res_hit_T_72 = res_hit_msbsLess_10 | _res_hit_T_71; // @[PMP.scala:80:39, :83:{16,30}] wire _res_hit_T_73 = ~_res_hit_T_72; // @[PMP.scala:83:16, :88:5] wire [31:0] _res_hit_msbsLess_T_68 = ~_res_hit_msbsLess_T_67; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsLess_T_69 = {_res_hit_msbsLess_T_68[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsLess_T_70 = ~_res_hit_msbsLess_T_69; // @[PMP.scala:60:{27,48}] wire [25:0] _res_hit_msbsLess_T_71 = _res_hit_msbsLess_T_70[31:6]; // @[PMP.scala:60:27, :80:52] wire res_hit_msbsLess_11 = _res_hit_msbsLess_T_66 < _res_hit_msbsLess_T_71; // @[PMP.scala:80:{25,39,52}] wire [31:0] _res_hit_msbsEqual_T_79 = ~_res_hit_msbsEqual_T_78; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsEqual_T_80 = {_res_hit_msbsEqual_T_79[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsEqual_T_81 = ~_res_hit_msbsEqual_T_80; // @[PMP.scala:60:{27,48}] wire [25:0] _res_hit_msbsEqual_T_82 = _res_hit_msbsEqual_T_81[31:6]; // @[PMP.scala:60:27, :81:54] wire [25:0] _res_hit_msbsEqual_T_83 = _res_hit_msbsEqual_T_77 ^ _res_hit_msbsEqual_T_82; // @[PMP.scala:81:{27,41,54}] wire res_hit_msbsEqual_11 = _res_hit_msbsEqual_T_83 == 26'h0; // @[PMP.scala:80:52, :81:{41,54,69}, :123:67] wire [5:0] _res_hit_lsbsLess_T_78 = _res_hit_lsbsLess_T_77; // @[PMP.scala:82:{25,42}] wire [31:0] _res_hit_lsbsLess_T_80 = ~_res_hit_lsbsLess_T_79; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_lsbsLess_T_81 = {_res_hit_lsbsLess_T_80[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbsLess_T_82 = ~_res_hit_lsbsLess_T_81; // @[PMP.scala:60:{27,48}] wire [5:0] _res_hit_lsbsLess_T_83 = _res_hit_lsbsLess_T_82[5:0]; // @[PMP.scala:60:27, :82:64] wire res_hit_lsbsLess_11 = _res_hit_lsbsLess_T_78 < _res_hit_lsbsLess_T_83; // @[PMP.scala:82:{42,53,64}] wire _res_hit_T_74 = res_hit_msbsEqual_11 & res_hit_lsbsLess_11; // @[PMP.scala:81:69, :82:53, :83:30] wire _res_hit_T_75 = res_hit_msbsLess_11 | _res_hit_T_74; // @[PMP.scala:80:39, :83:{16,30}] wire _res_hit_T_76 = _res_hit_T_73 & _res_hit_T_75; // @[PMP.scala:83:16, :88:5, :94:48] wire _res_hit_T_77 = _res_hit_T_67 & _res_hit_T_76; // @[PMP.scala:46:26, :94:48, :132:61] wire res_hit_5 = _res_hit_T_65 ? _res_hit_T_66 : _res_hit_T_77; // @[PMP.scala:45:20, :71:16, :132:{8,61}] wire _res_ignore_T_5 = ~io_pmp_2_cfg_l_0; // @[PMP.scala:143:7, :164:29] wire res_ignore_5 = default_0 & _res_ignore_T_5; // @[PMP.scala:156:56, :164:{26,29}] wire [31:0] _res_aligned_straddlesLowerBound_T_87 = ~_res_aligned_straddlesLowerBound_T_86; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesLowerBound_T_88 = {_res_aligned_straddlesLowerBound_T_87[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesLowerBound_T_89 = ~_res_aligned_straddlesLowerBound_T_88; // @[PMP.scala:60:{27,48}] wire [25:0] _res_aligned_straddlesLowerBound_T_90 = _res_aligned_straddlesLowerBound_T_89[31:6]; // @[PMP.scala:60:27, :123:67] wire [25:0] _res_aligned_straddlesLowerBound_T_91 = _res_aligned_straddlesLowerBound_T_85 ^ _res_aligned_straddlesLowerBound_T_90; // @[PMP.scala:123:{35,49,67}] wire _res_aligned_straddlesLowerBound_T_92 = _res_aligned_straddlesLowerBound_T_91 == 26'h0; // @[PMP.scala:80:52, :81:54, :123:{49,67,82}] wire [31:0] _res_aligned_straddlesLowerBound_T_94 = ~_res_aligned_straddlesLowerBound_T_93; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesLowerBound_T_95 = {_res_aligned_straddlesLowerBound_T_94[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesLowerBound_T_96 = ~_res_aligned_straddlesLowerBound_T_95; // @[PMP.scala:60:{27,48}] wire [5:0] _res_aligned_straddlesLowerBound_T_97 = _res_aligned_straddlesLowerBound_T_96[5:0]; // @[PMP.scala:60:27, :123:108] wire [5:0] _res_aligned_straddlesLowerBound_T_99 = ~_res_aligned_straddlesLowerBound_T_98; // @[PMP.scala:123:{127,129}] wire [5:0] _res_aligned_straddlesLowerBound_T_100 = _res_aligned_straddlesLowerBound_T_97 & _res_aligned_straddlesLowerBound_T_99; // @[PMP.scala:123:{108,125,127}] wire _res_aligned_straddlesLowerBound_T_101 = |_res_aligned_straddlesLowerBound_T_100; // @[PMP.scala:123:{125,147}] wire res_aligned_straddlesLowerBound_5 = _res_aligned_straddlesLowerBound_T_92 & _res_aligned_straddlesLowerBound_T_101; // @[PMP.scala:123:{82,90,147}] wire [31:0] _res_aligned_straddlesUpperBound_T_87 = ~_res_aligned_straddlesUpperBound_T_86; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesUpperBound_T_88 = {_res_aligned_straddlesUpperBound_T_87[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesUpperBound_T_89 = ~_res_aligned_straddlesUpperBound_T_88; // @[PMP.scala:60:{27,48}] wire [25:0] _res_aligned_straddlesUpperBound_T_90 = _res_aligned_straddlesUpperBound_T_89[31:6]; // @[PMP.scala:60:27, :124:62] wire [25:0] _res_aligned_straddlesUpperBound_T_91 = _res_aligned_straddlesUpperBound_T_85 ^ _res_aligned_straddlesUpperBound_T_90; // @[PMP.scala:124:{35,49,62}] wire _res_aligned_straddlesUpperBound_T_92 = _res_aligned_straddlesUpperBound_T_91 == 26'h0; // @[PMP.scala:80:52, :81:54, :123:67, :124:{49,77}] wire [31:0] _res_aligned_straddlesUpperBound_T_94 = ~_res_aligned_straddlesUpperBound_T_93; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesUpperBound_T_95 = {_res_aligned_straddlesUpperBound_T_94[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesUpperBound_T_96 = ~_res_aligned_straddlesUpperBound_T_95; // @[PMP.scala:60:{27,48}] wire [5:0] _res_aligned_straddlesUpperBound_T_97 = _res_aligned_straddlesUpperBound_T_96[5:0]; // @[PMP.scala:60:27, :124:98] wire [5:0] _res_aligned_straddlesUpperBound_T_99 = _res_aligned_straddlesUpperBound_T_98; // @[PMP.scala:124:{119,136}] wire [5:0] _res_aligned_straddlesUpperBound_T_100 = _res_aligned_straddlesUpperBound_T_97 & _res_aligned_straddlesUpperBound_T_99; // @[PMP.scala:124:{98,115,136}] wire _res_aligned_straddlesUpperBound_T_101 = |_res_aligned_straddlesUpperBound_T_100; // @[PMP.scala:124:{115,148}] wire res_aligned_straddlesUpperBound_5 = _res_aligned_straddlesUpperBound_T_92 & _res_aligned_straddlesUpperBound_T_101; // @[PMP.scala:124:{77,85,148}] wire _res_aligned_rangeAligned_T_5 = res_aligned_straddlesLowerBound_5 | res_aligned_straddlesUpperBound_5; // @[PMP.scala:123:90, :124:85, :125:46] wire res_aligned_rangeAligned_5 = ~_res_aligned_rangeAligned_T_5; // @[PMP.scala:125:{24,46}] wire [5:0] _res_aligned_pow2Aligned_T_16 = ~_res_aligned_pow2Aligned_T_15; // @[PMP.scala:126:{34,39}] wire res_aligned_5 = _res_aligned_T_5 | res_aligned_rangeAligned_5; // @[PMP.scala:45:20, :125:24, :127:8] wire _res_T_225 = io_pmp_2_cfg_a_0 == 2'h0; // @[PMP.scala:143:7, :168:32] wire _GEN_26 = io_pmp_2_cfg_a_0 == 2'h1; // @[PMP.scala:143:7, :168:32] wire _res_T_226; // @[PMP.scala:168:32] assign _res_T_226 = _GEN_26; // @[PMP.scala:168:32] wire _res_T_245; // @[PMP.scala:177:61] assign _res_T_245 = _GEN_26; // @[PMP.scala:168:32, :177:61] wire _res_T_249; // @[PMP.scala:178:63] assign _res_T_249 = _GEN_26; // @[PMP.scala:168:32, :178:63] wire _GEN_27 = io_pmp_2_cfg_a_0 == 2'h2; // @[PMP.scala:143:7, :168:32] wire _res_T_227; // @[PMP.scala:168:32] assign _res_T_227 = _GEN_27; // @[PMP.scala:168:32] wire _res_T_254; // @[PMP.scala:177:61] assign _res_T_254 = _GEN_27; // @[PMP.scala:168:32, :177:61] wire _res_T_258; // @[PMP.scala:178:63] assign _res_T_258 = _GEN_27; // @[PMP.scala:168:32, :178:63] wire _res_T_228 = &io_pmp_2_cfg_a_0; // @[PMP.scala:143:7, :168:32] wire [1:0] _GEN_28 = {io_pmp_2_cfg_x_0, io_pmp_2_cfg_w_0}; // @[PMP.scala:143:7, :174:26] wire [1:0] res_hi_30; // @[PMP.scala:174:26] assign res_hi_30 = _GEN_28; // @[PMP.scala:174:26] wire [1:0] res_hi_31; // @[PMP.scala:174:26] assign res_hi_31 = _GEN_28; // @[PMP.scala:174:26] wire [1:0] res_hi_32; // @[PMP.scala:174:26] assign res_hi_32 = _GEN_28; // @[PMP.scala:174:26] wire [1:0] res_hi_33; // @[PMP.scala:174:26] assign res_hi_33 = _GEN_28; // @[PMP.scala:174:26] wire [1:0] res_hi_34; // @[PMP.scala:174:26] assign res_hi_34 = _GEN_28; // @[PMP.scala:174:26] wire [1:0] res_hi_35; // @[PMP.scala:174:26] assign res_hi_35 = _GEN_28; // @[PMP.scala:174:26] wire [2:0] _res_T_230 = {res_hi_30, io_pmp_2_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_231 = _res_T_230 == 3'h0; // @[PMP.scala:143:7, :146:14, :174:{26,60}] wire [2:0] _res_T_232 = {res_hi_31, io_pmp_2_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_233 = _res_T_232 == 3'h1; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_234 = {res_hi_32, io_pmp_2_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_235 = _res_T_234 == 3'h3; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_236 = {res_hi_33, io_pmp_2_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_237 = _res_T_236 == 3'h4; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_238 = {res_hi_34, io_pmp_2_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_239 = _res_T_238 == 3'h5; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_240 = {res_hi_35, io_pmp_2_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_241 = &_res_T_240; // @[PMP.scala:174:{26,60}] wire _res_T_242 = ~res_ignore_5; // @[PMP.scala:164:26, :177:22] wire _res_T_243 = _res_T_242 & res_hit_5; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_244 = _res_T_243 & res_aligned_5; // @[PMP.scala:127:8, :177:{30,37}] wire _res_T_246 = _res_T_244 & _res_T_245; // @[PMP.scala:177:{37,48,61}] wire _GEN_29 = io_pmp_2_cfg_l_0 & res_hit_5; // @[PMP.scala:132:8, :143:7, :178:32] wire _res_T_247; // @[PMP.scala:178:32] assign _res_T_247 = _GEN_29; // @[PMP.scala:178:32] wire _res_T_256; // @[PMP.scala:178:32] assign _res_T_256 = _GEN_29; // @[PMP.scala:178:32] wire _res_T_265; // @[PMP.scala:178:32] assign _res_T_265 = _GEN_29; // @[PMP.scala:178:32] wire _res_T_248 = _res_T_247 & res_aligned_5; // @[PMP.scala:127:8, :178:{32,39}] wire _res_T_250 = _res_T_248 & _res_T_249; // @[PMP.scala:178:{39,50,63}] wire _res_T_251 = ~res_ignore_5; // @[PMP.scala:164:26, :177:22] wire _res_T_252 = _res_T_251 & res_hit_5; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_253 = _res_T_252 & res_aligned_5; // @[PMP.scala:127:8, :177:{30,37}] wire _res_T_255 = _res_T_253 & _res_T_254; // @[PMP.scala:177:{37,48,61}] wire _res_T_257 = _res_T_256 & res_aligned_5; // @[PMP.scala:127:8, :178:{32,39}] wire _res_T_259 = _res_T_257 & _res_T_258; // @[PMP.scala:178:{39,50,63}] wire _res_T_260 = ~res_ignore_5; // @[PMP.scala:164:26, :177:22] wire _res_T_261 = _res_T_260 & res_hit_5; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_262 = _res_T_261 & res_aligned_5; // @[PMP.scala:127:8, :177:{30,37}] wire _res_T_263 = &io_pmp_2_cfg_a_0; // @[PMP.scala:143:7, :168:32, :177:61] wire _res_T_264 = _res_T_262 & _res_T_263; // @[PMP.scala:177:{37,48,61}] wire _res_T_266 = _res_T_265 & res_aligned_5; // @[PMP.scala:127:8, :178:{32,39}] wire _res_T_267 = &io_pmp_2_cfg_a_0; // @[PMP.scala:143:7, :168:32, :178:63] wire _res_T_268 = _res_T_266 & _res_T_267; // @[PMP.scala:178:{39,50,63}] wire _res_cur_cfg_x_T_11; // @[PMP.scala:184:26] wire _res_cur_cfg_w_T_11; // @[PMP.scala:183:26] wire _res_cur_cfg_r_T_11; // @[PMP.scala:182:26] wire res_cur_5_cfg_x; // @[PMP.scala:181:23] wire res_cur_5_cfg_w; // @[PMP.scala:181:23] wire res_cur_5_cfg_r; // @[PMP.scala:181:23] wire _res_cur_cfg_r_T_10 = io_pmp_2_cfg_r_0 | res_ignore_5; // @[PMP.scala:143:7, :164:26, :182:40] assign _res_cur_cfg_r_T_11 = res_aligned_5 & _res_cur_cfg_r_T_10; // @[PMP.scala:127:8, :182:{26,40}] assign res_cur_5_cfg_r = _res_cur_cfg_r_T_11; // @[PMP.scala:181:23, :182:26] wire _res_cur_cfg_w_T_10 = io_pmp_2_cfg_w_0 | res_ignore_5; // @[PMP.scala:143:7, :164:26, :183:40] assign _res_cur_cfg_w_T_11 = res_aligned_5 & _res_cur_cfg_w_T_10; // @[PMP.scala:127:8, :183:{26,40}] assign res_cur_5_cfg_w = _res_cur_cfg_w_T_11; // @[PMP.scala:181:23, :183:26] wire _res_cur_cfg_x_T_10 = io_pmp_2_cfg_x_0 | res_ignore_5; // @[PMP.scala:143:7, :164:26, :184:40] assign _res_cur_cfg_x_T_11 = res_aligned_5 & _res_cur_cfg_x_T_10; // @[PMP.scala:127:8, :184:{26,40}] assign res_cur_5_cfg_x = _res_cur_cfg_x_T_11; // @[PMP.scala:181:23, :184:26] wire _res_T_269_cfg_l = res_hit_5 ? res_cur_5_cfg_l : _res_T_224_cfg_l; // @[PMP.scala:132:8, :181:23, :185:8] wire [1:0] _res_T_269_cfg_a = res_hit_5 ? res_cur_5_cfg_a : _res_T_224_cfg_a; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_T_269_cfg_x = res_hit_5 ? res_cur_5_cfg_x : _res_T_224_cfg_x; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_T_269_cfg_w = res_hit_5 ? res_cur_5_cfg_w : _res_T_224_cfg_w; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_T_269_cfg_r = res_hit_5 ? res_cur_5_cfg_r : _res_T_224_cfg_r; // @[PMP.scala:132:8, :181:23, :185:8] wire [29:0] _res_T_269_addr = res_hit_5 ? res_cur_5_addr : _res_T_224_addr; // @[PMP.scala:132:8, :181:23, :185:8] wire [31:0] _res_T_269_mask = res_hit_5 ? res_cur_5_mask : _res_T_224_mask; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_hit_T_78 = io_pmp_1_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7] wire _res_aligned_T_6 = io_pmp_1_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7] wire [25:0] _res_hit_msbMatch_T_66 = io_pmp_1_mask_0[31:6]; // @[PMP.scala:68:26, :69:72, :143:7] wire [5:0] _res_aligned_pow2Aligned_T_18 = io_pmp_1_mask_0[5:0]; // @[PMP.scala:68:26, :126:39, :143:7] wire [31:0] _res_hit_msbMatch_T_62 = ~_res_hit_msbMatch_T_61; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbMatch_T_63 = {_res_hit_msbMatch_T_62[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbMatch_T_64 = ~_res_hit_msbMatch_T_63; // @[PMP.scala:60:{27,48}] wire [25:0] _res_hit_msbMatch_T_65 = _res_hit_msbMatch_T_64[31:6]; // @[PMP.scala:60:27, :69:53] wire [25:0] _res_hit_msbMatch_T_67 = _res_hit_msbMatch_T_60 ^ _res_hit_msbMatch_T_65; // @[PMP.scala:63:47, :69:{29,53}] wire [25:0] _res_hit_msbMatch_T_68 = ~_res_hit_msbMatch_T_66; // @[PMP.scala:63:54, :69:72] wire [25:0] _res_hit_msbMatch_T_69 = _res_hit_msbMatch_T_67 & _res_hit_msbMatch_T_68; // @[PMP.scala:63:{47,52,54}] wire res_hit_msbMatch_6 = _res_hit_msbMatch_T_69 == 26'h0; // @[PMP.scala:63:{52,58}, :80:52, :81:54, :123:67] wire [31:0] _res_hit_lsbMatch_T_62 = ~_res_hit_lsbMatch_T_61; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_lsbMatch_T_63 = {_res_hit_lsbMatch_T_62[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbMatch_T_64 = ~_res_hit_lsbMatch_T_63; // @[PMP.scala:60:{27,48}] wire [5:0] _res_hit_lsbMatch_T_65 = _res_hit_lsbMatch_T_64[5:0]; // @[PMP.scala:60:27, :70:55] wire [5:0] _res_hit_lsbMatch_T_66 = res_hit_lsbMask_6[5:0]; // @[PMP.scala:68:26, :70:80] wire [5:0] _res_hit_lsbMatch_T_67 = _res_hit_lsbMatch_T_60 ^ _res_hit_lsbMatch_T_65; // @[PMP.scala:63:47, :70:{28,55}] wire [5:0] _res_hit_lsbMatch_T_68 = ~_res_hit_lsbMatch_T_66; // @[PMP.scala:63:54, :70:80] wire [5:0] _res_hit_lsbMatch_T_69 = _res_hit_lsbMatch_T_67 & _res_hit_lsbMatch_T_68; // @[PMP.scala:63:{47,52,54}] wire res_hit_lsbMatch_6 = _res_hit_lsbMatch_T_69 == 6'h0; // @[PMP.scala:63:{52,58}] wire _res_hit_T_79 = res_hit_msbMatch_6 & res_hit_lsbMatch_6; // @[PMP.scala:63:58, :71:16] wire _res_hit_T_80 = io_pmp_1_cfg_a_0[0]; // @[PMP.scala:46:26, :143:7] wire [31:0] _GEN_30 = {io_pmp_0_addr_0, 2'h0}; // @[PMP.scala:60:36, :143:7] wire [31:0] _res_hit_msbsLess_T_73; // @[PMP.scala:60:36] assign _res_hit_msbsLess_T_73 = _GEN_30; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsEqual_T_85; // @[PMP.scala:60:36] assign _res_hit_msbsEqual_T_85 = _GEN_30; // @[PMP.scala:60:36] wire [31:0] _res_hit_lsbsLess_T_86; // @[PMP.scala:60:36] assign _res_hit_lsbsLess_T_86 = _GEN_30; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesLowerBound_T_103; // @[PMP.scala:60:36] assign _res_aligned_straddlesLowerBound_T_103 = _GEN_30; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesLowerBound_T_110; // @[PMP.scala:60:36] assign _res_aligned_straddlesLowerBound_T_110 = _GEN_30; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbMatch_T_71; // @[PMP.scala:60:36] assign _res_hit_msbMatch_T_71 = _GEN_30; // @[PMP.scala:60:36] wire [31:0] _res_hit_lsbMatch_T_71; // @[PMP.scala:60:36] assign _res_hit_lsbMatch_T_71 = _GEN_30; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsLess_T_91; // @[PMP.scala:60:36] assign _res_hit_msbsLess_T_91 = _GEN_30; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsEqual_T_106; // @[PMP.scala:60:36] assign _res_hit_msbsEqual_T_106 = _GEN_30; // @[PMP.scala:60:36] wire [31:0] _res_hit_lsbsLess_T_107; // @[PMP.scala:60:36] assign _res_hit_lsbsLess_T_107 = _GEN_30; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesUpperBound_T_120; // @[PMP.scala:60:36] assign _res_aligned_straddlesUpperBound_T_120 = _GEN_30; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesUpperBound_T_127; // @[PMP.scala:60:36] assign _res_aligned_straddlesUpperBound_T_127 = _GEN_30; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsLess_T_74 = ~_res_hit_msbsLess_T_73; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsLess_T_75 = {_res_hit_msbsLess_T_74[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsLess_T_76 = ~_res_hit_msbsLess_T_75; // @[PMP.scala:60:{27,48}] wire [25:0] _res_hit_msbsLess_T_77 = _res_hit_msbsLess_T_76[31:6]; // @[PMP.scala:60:27, :80:52] wire res_hit_msbsLess_12 = _res_hit_msbsLess_T_72 < _res_hit_msbsLess_T_77; // @[PMP.scala:80:{25,39,52}] wire [31:0] _res_hit_msbsEqual_T_86 = ~_res_hit_msbsEqual_T_85; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsEqual_T_87 = {_res_hit_msbsEqual_T_86[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsEqual_T_88 = ~_res_hit_msbsEqual_T_87; // @[PMP.scala:60:{27,48}] wire [25:0] _res_hit_msbsEqual_T_89 = _res_hit_msbsEqual_T_88[31:6]; // @[PMP.scala:60:27, :81:54] wire [25:0] _res_hit_msbsEqual_T_90 = _res_hit_msbsEqual_T_84 ^ _res_hit_msbsEqual_T_89; // @[PMP.scala:81:{27,41,54}] wire res_hit_msbsEqual_12 = _res_hit_msbsEqual_T_90 == 26'h0; // @[PMP.scala:80:52, :81:{41,54,69}, :123:67] wire [5:0] _res_hit_lsbsLess_T_85 = _res_hit_lsbsLess_T_84; // @[PMP.scala:82:{25,42}] wire [31:0] _res_hit_lsbsLess_T_87 = ~_res_hit_lsbsLess_T_86; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_lsbsLess_T_88 = {_res_hit_lsbsLess_T_87[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbsLess_T_89 = ~_res_hit_lsbsLess_T_88; // @[PMP.scala:60:{27,48}] wire [5:0] _res_hit_lsbsLess_T_90 = _res_hit_lsbsLess_T_89[5:0]; // @[PMP.scala:60:27, :82:64] wire res_hit_lsbsLess_12 = _res_hit_lsbsLess_T_85 < _res_hit_lsbsLess_T_90; // @[PMP.scala:82:{42,53,64}] wire _res_hit_T_84 = res_hit_msbsEqual_12 & res_hit_lsbsLess_12; // @[PMP.scala:81:69, :82:53, :83:30] wire _res_hit_T_85 = res_hit_msbsLess_12 | _res_hit_T_84; // @[PMP.scala:80:39, :83:{16,30}] wire _res_hit_T_86 = ~_res_hit_T_85; // @[PMP.scala:83:16, :88:5] wire [31:0] _res_hit_msbsLess_T_80 = ~_res_hit_msbsLess_T_79; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsLess_T_81 = {_res_hit_msbsLess_T_80[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsLess_T_82 = ~_res_hit_msbsLess_T_81; // @[PMP.scala:60:{27,48}] wire [25:0] _res_hit_msbsLess_T_83 = _res_hit_msbsLess_T_82[31:6]; // @[PMP.scala:60:27, :80:52] wire res_hit_msbsLess_13 = _res_hit_msbsLess_T_78 < _res_hit_msbsLess_T_83; // @[PMP.scala:80:{25,39,52}] wire [31:0] _res_hit_msbsEqual_T_93 = ~_res_hit_msbsEqual_T_92; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsEqual_T_94 = {_res_hit_msbsEqual_T_93[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsEqual_T_95 = ~_res_hit_msbsEqual_T_94; // @[PMP.scala:60:{27,48}] wire [25:0] _res_hit_msbsEqual_T_96 = _res_hit_msbsEqual_T_95[31:6]; // @[PMP.scala:60:27, :81:54] wire [25:0] _res_hit_msbsEqual_T_97 = _res_hit_msbsEqual_T_91 ^ _res_hit_msbsEqual_T_96; // @[PMP.scala:81:{27,41,54}] wire res_hit_msbsEqual_13 = _res_hit_msbsEqual_T_97 == 26'h0; // @[PMP.scala:80:52, :81:{41,54,69}, :123:67] wire [5:0] _res_hit_lsbsLess_T_92 = _res_hit_lsbsLess_T_91; // @[PMP.scala:82:{25,42}] wire [31:0] _res_hit_lsbsLess_T_94 = ~_res_hit_lsbsLess_T_93; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_lsbsLess_T_95 = {_res_hit_lsbsLess_T_94[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbsLess_T_96 = ~_res_hit_lsbsLess_T_95; // @[PMP.scala:60:{27,48}] wire [5:0] _res_hit_lsbsLess_T_97 = _res_hit_lsbsLess_T_96[5:0]; // @[PMP.scala:60:27, :82:64] wire res_hit_lsbsLess_13 = _res_hit_lsbsLess_T_92 < _res_hit_lsbsLess_T_97; // @[PMP.scala:82:{42,53,64}] wire _res_hit_T_87 = res_hit_msbsEqual_13 & res_hit_lsbsLess_13; // @[PMP.scala:81:69, :82:53, :83:30] wire _res_hit_T_88 = res_hit_msbsLess_13 | _res_hit_T_87; // @[PMP.scala:80:39, :83:{16,30}] wire _res_hit_T_89 = _res_hit_T_86 & _res_hit_T_88; // @[PMP.scala:83:16, :88:5, :94:48] wire _res_hit_T_90 = _res_hit_T_80 & _res_hit_T_89; // @[PMP.scala:46:26, :94:48, :132:61] wire res_hit_6 = _res_hit_T_78 ? _res_hit_T_79 : _res_hit_T_90; // @[PMP.scala:45:20, :71:16, :132:{8,61}] wire _res_ignore_T_6 = ~io_pmp_1_cfg_l_0; // @[PMP.scala:143:7, :164:29] wire res_ignore_6 = default_0 & _res_ignore_T_6; // @[PMP.scala:156:56, :164:{26,29}] wire [31:0] _res_aligned_straddlesLowerBound_T_104 = ~_res_aligned_straddlesLowerBound_T_103; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesLowerBound_T_105 = {_res_aligned_straddlesLowerBound_T_104[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesLowerBound_T_106 = ~_res_aligned_straddlesLowerBound_T_105; // @[PMP.scala:60:{27,48}] wire [25:0] _res_aligned_straddlesLowerBound_T_107 = _res_aligned_straddlesLowerBound_T_106[31:6]; // @[PMP.scala:60:27, :123:67] wire [25:0] _res_aligned_straddlesLowerBound_T_108 = _res_aligned_straddlesLowerBound_T_102 ^ _res_aligned_straddlesLowerBound_T_107; // @[PMP.scala:123:{35,49,67}] wire _res_aligned_straddlesLowerBound_T_109 = _res_aligned_straddlesLowerBound_T_108 == 26'h0; // @[PMP.scala:80:52, :81:54, :123:{49,67,82}] wire [31:0] _res_aligned_straddlesLowerBound_T_111 = ~_res_aligned_straddlesLowerBound_T_110; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesLowerBound_T_112 = {_res_aligned_straddlesLowerBound_T_111[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesLowerBound_T_113 = ~_res_aligned_straddlesLowerBound_T_112; // @[PMP.scala:60:{27,48}] wire [5:0] _res_aligned_straddlesLowerBound_T_114 = _res_aligned_straddlesLowerBound_T_113[5:0]; // @[PMP.scala:60:27, :123:108] wire [5:0] _res_aligned_straddlesLowerBound_T_116 = ~_res_aligned_straddlesLowerBound_T_115; // @[PMP.scala:123:{127,129}] wire [5:0] _res_aligned_straddlesLowerBound_T_117 = _res_aligned_straddlesLowerBound_T_114 & _res_aligned_straddlesLowerBound_T_116; // @[PMP.scala:123:{108,125,127}] wire _res_aligned_straddlesLowerBound_T_118 = |_res_aligned_straddlesLowerBound_T_117; // @[PMP.scala:123:{125,147}] wire res_aligned_straddlesLowerBound_6 = _res_aligned_straddlesLowerBound_T_109 & _res_aligned_straddlesLowerBound_T_118; // @[PMP.scala:123:{82,90,147}] wire [31:0] _res_aligned_straddlesUpperBound_T_104 = ~_res_aligned_straddlesUpperBound_T_103; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesUpperBound_T_105 = {_res_aligned_straddlesUpperBound_T_104[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesUpperBound_T_106 = ~_res_aligned_straddlesUpperBound_T_105; // @[PMP.scala:60:{27,48}] wire [25:0] _res_aligned_straddlesUpperBound_T_107 = _res_aligned_straddlesUpperBound_T_106[31:6]; // @[PMP.scala:60:27, :124:62] wire [25:0] _res_aligned_straddlesUpperBound_T_108 = _res_aligned_straddlesUpperBound_T_102 ^ _res_aligned_straddlesUpperBound_T_107; // @[PMP.scala:124:{35,49,62}] wire _res_aligned_straddlesUpperBound_T_109 = _res_aligned_straddlesUpperBound_T_108 == 26'h0; // @[PMP.scala:80:52, :81:54, :123:67, :124:{49,77}] wire [31:0] _res_aligned_straddlesUpperBound_T_111 = ~_res_aligned_straddlesUpperBound_T_110; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesUpperBound_T_112 = {_res_aligned_straddlesUpperBound_T_111[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesUpperBound_T_113 = ~_res_aligned_straddlesUpperBound_T_112; // @[PMP.scala:60:{27,48}] wire [5:0] _res_aligned_straddlesUpperBound_T_114 = _res_aligned_straddlesUpperBound_T_113[5:0]; // @[PMP.scala:60:27, :124:98] wire [5:0] _res_aligned_straddlesUpperBound_T_116 = _res_aligned_straddlesUpperBound_T_115; // @[PMP.scala:124:{119,136}] wire [5:0] _res_aligned_straddlesUpperBound_T_117 = _res_aligned_straddlesUpperBound_T_114 & _res_aligned_straddlesUpperBound_T_116; // @[PMP.scala:124:{98,115,136}] wire _res_aligned_straddlesUpperBound_T_118 = |_res_aligned_straddlesUpperBound_T_117; // @[PMP.scala:124:{115,148}] wire res_aligned_straddlesUpperBound_6 = _res_aligned_straddlesUpperBound_T_109 & _res_aligned_straddlesUpperBound_T_118; // @[PMP.scala:124:{77,85,148}] wire _res_aligned_rangeAligned_T_6 = res_aligned_straddlesLowerBound_6 | res_aligned_straddlesUpperBound_6; // @[PMP.scala:123:90, :124:85, :125:46] wire res_aligned_rangeAligned_6 = ~_res_aligned_rangeAligned_T_6; // @[PMP.scala:125:{24,46}] wire [5:0] _res_aligned_pow2Aligned_T_19 = ~_res_aligned_pow2Aligned_T_18; // @[PMP.scala:126:{34,39}] wire res_aligned_6 = _res_aligned_T_6 | res_aligned_rangeAligned_6; // @[PMP.scala:45:20, :125:24, :127:8] wire _res_T_270 = io_pmp_1_cfg_a_0 == 2'h0; // @[PMP.scala:143:7, :168:32] wire _GEN_31 = io_pmp_1_cfg_a_0 == 2'h1; // @[PMP.scala:143:7, :168:32] wire _res_T_271; // @[PMP.scala:168:32] assign _res_T_271 = _GEN_31; // @[PMP.scala:168:32] wire _res_T_290; // @[PMP.scala:177:61] assign _res_T_290 = _GEN_31; // @[PMP.scala:168:32, :177:61] wire _res_T_294; // @[PMP.scala:178:63] assign _res_T_294 = _GEN_31; // @[PMP.scala:168:32, :178:63] wire _GEN_32 = io_pmp_1_cfg_a_0 == 2'h2; // @[PMP.scala:143:7, :168:32] wire _res_T_272; // @[PMP.scala:168:32] assign _res_T_272 = _GEN_32; // @[PMP.scala:168:32] wire _res_T_299; // @[PMP.scala:177:61] assign _res_T_299 = _GEN_32; // @[PMP.scala:168:32, :177:61] wire _res_T_303; // @[PMP.scala:178:63] assign _res_T_303 = _GEN_32; // @[PMP.scala:168:32, :178:63] wire _res_T_273 = &io_pmp_1_cfg_a_0; // @[PMP.scala:143:7, :168:32] wire [1:0] _GEN_33 = {io_pmp_1_cfg_x_0, io_pmp_1_cfg_w_0}; // @[PMP.scala:143:7, :174:26] wire [1:0] res_hi_36; // @[PMP.scala:174:26] assign res_hi_36 = _GEN_33; // @[PMP.scala:174:26] wire [1:0] res_hi_37; // @[PMP.scala:174:26] assign res_hi_37 = _GEN_33; // @[PMP.scala:174:26] wire [1:0] res_hi_38; // @[PMP.scala:174:26] assign res_hi_38 = _GEN_33; // @[PMP.scala:174:26] wire [1:0] res_hi_39; // @[PMP.scala:174:26] assign res_hi_39 = _GEN_33; // @[PMP.scala:174:26] wire [1:0] res_hi_40; // @[PMP.scala:174:26] assign res_hi_40 = _GEN_33; // @[PMP.scala:174:26] wire [1:0] res_hi_41; // @[PMP.scala:174:26] assign res_hi_41 = _GEN_33; // @[PMP.scala:174:26] wire [2:0] _res_T_275 = {res_hi_36, io_pmp_1_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_276 = _res_T_275 == 3'h0; // @[PMP.scala:143:7, :146:14, :174:{26,60}] wire [2:0] _res_T_277 = {res_hi_37, io_pmp_1_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_278 = _res_T_277 == 3'h1; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_279 = {res_hi_38, io_pmp_1_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_280 = _res_T_279 == 3'h3; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_281 = {res_hi_39, io_pmp_1_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_282 = _res_T_281 == 3'h4; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_283 = {res_hi_40, io_pmp_1_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_284 = _res_T_283 == 3'h5; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_285 = {res_hi_41, io_pmp_1_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_286 = &_res_T_285; // @[PMP.scala:174:{26,60}] wire _res_T_287 = ~res_ignore_6; // @[PMP.scala:164:26, :177:22] wire _res_T_288 = _res_T_287 & res_hit_6; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_289 = _res_T_288 & res_aligned_6; // @[PMP.scala:127:8, :177:{30,37}] wire _res_T_291 = _res_T_289 & _res_T_290; // @[PMP.scala:177:{37,48,61}] wire _GEN_34 = io_pmp_1_cfg_l_0 & res_hit_6; // @[PMP.scala:132:8, :143:7, :178:32] wire _res_T_292; // @[PMP.scala:178:32] assign _res_T_292 = _GEN_34; // @[PMP.scala:178:32] wire _res_T_301; // @[PMP.scala:178:32] assign _res_T_301 = _GEN_34; // @[PMP.scala:178:32] wire _res_T_310; // @[PMP.scala:178:32] assign _res_T_310 = _GEN_34; // @[PMP.scala:178:32] wire _res_T_293 = _res_T_292 & res_aligned_6; // @[PMP.scala:127:8, :178:{32,39}] wire _res_T_295 = _res_T_293 & _res_T_294; // @[PMP.scala:178:{39,50,63}] wire _res_T_296 = ~res_ignore_6; // @[PMP.scala:164:26, :177:22] wire _res_T_297 = _res_T_296 & res_hit_6; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_298 = _res_T_297 & res_aligned_6; // @[PMP.scala:127:8, :177:{30,37}] wire _res_T_300 = _res_T_298 & _res_T_299; // @[PMP.scala:177:{37,48,61}] wire _res_T_302 = _res_T_301 & res_aligned_6; // @[PMP.scala:127:8, :178:{32,39}] wire _res_T_304 = _res_T_302 & _res_T_303; // @[PMP.scala:178:{39,50,63}] wire _res_T_305 = ~res_ignore_6; // @[PMP.scala:164:26, :177:22] wire _res_T_306 = _res_T_305 & res_hit_6; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_307 = _res_T_306 & res_aligned_6; // @[PMP.scala:127:8, :177:{30,37}] wire _res_T_308 = &io_pmp_1_cfg_a_0; // @[PMP.scala:143:7, :168:32, :177:61] wire _res_T_309 = _res_T_307 & _res_T_308; // @[PMP.scala:177:{37,48,61}] wire _res_T_311 = _res_T_310 & res_aligned_6; // @[PMP.scala:127:8, :178:{32,39}] wire _res_T_312 = &io_pmp_1_cfg_a_0; // @[PMP.scala:143:7, :168:32, :178:63] wire _res_T_313 = _res_T_311 & _res_T_312; // @[PMP.scala:178:{39,50,63}] wire _res_cur_cfg_x_T_13; // @[PMP.scala:184:26] wire _res_cur_cfg_w_T_13; // @[PMP.scala:183:26] wire _res_cur_cfg_r_T_13; // @[PMP.scala:182:26] wire res_cur_6_cfg_x; // @[PMP.scala:181:23] wire res_cur_6_cfg_w; // @[PMP.scala:181:23] wire res_cur_6_cfg_r; // @[PMP.scala:181:23] wire _res_cur_cfg_r_T_12 = io_pmp_1_cfg_r_0 | res_ignore_6; // @[PMP.scala:143:7, :164:26, :182:40] assign _res_cur_cfg_r_T_13 = res_aligned_6 & _res_cur_cfg_r_T_12; // @[PMP.scala:127:8, :182:{26,40}] assign res_cur_6_cfg_r = _res_cur_cfg_r_T_13; // @[PMP.scala:181:23, :182:26] wire _res_cur_cfg_w_T_12 = io_pmp_1_cfg_w_0 | res_ignore_6; // @[PMP.scala:143:7, :164:26, :183:40] assign _res_cur_cfg_w_T_13 = res_aligned_6 & _res_cur_cfg_w_T_12; // @[PMP.scala:127:8, :183:{26,40}] assign res_cur_6_cfg_w = _res_cur_cfg_w_T_13; // @[PMP.scala:181:23, :183:26] wire _res_cur_cfg_x_T_12 = io_pmp_1_cfg_x_0 | res_ignore_6; // @[PMP.scala:143:7, :164:26, :184:40] assign _res_cur_cfg_x_T_13 = res_aligned_6 & _res_cur_cfg_x_T_12; // @[PMP.scala:127:8, :184:{26,40}] assign res_cur_6_cfg_x = _res_cur_cfg_x_T_13; // @[PMP.scala:181:23, :184:26] wire _res_T_314_cfg_l = res_hit_6 ? res_cur_6_cfg_l : _res_T_269_cfg_l; // @[PMP.scala:132:8, :181:23, :185:8] wire [1:0] _res_T_314_cfg_a = res_hit_6 ? res_cur_6_cfg_a : _res_T_269_cfg_a; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_T_314_cfg_x = res_hit_6 ? res_cur_6_cfg_x : _res_T_269_cfg_x; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_T_314_cfg_w = res_hit_6 ? res_cur_6_cfg_w : _res_T_269_cfg_w; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_T_314_cfg_r = res_hit_6 ? res_cur_6_cfg_r : _res_T_269_cfg_r; // @[PMP.scala:132:8, :181:23, :185:8] wire [29:0] _res_T_314_addr = res_hit_6 ? res_cur_6_addr : _res_T_269_addr; // @[PMP.scala:132:8, :181:23, :185:8] wire [31:0] _res_T_314_mask = res_hit_6 ? res_cur_6_mask : _res_T_269_mask; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_hit_T_91 = io_pmp_0_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7] wire _res_aligned_T_7 = io_pmp_0_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7] wire [25:0] _res_hit_msbMatch_T_76 = io_pmp_0_mask_0[31:6]; // @[PMP.scala:68:26, :69:72, :143:7] wire [5:0] _res_aligned_pow2Aligned_T_21 = io_pmp_0_mask_0[5:0]; // @[PMP.scala:68:26, :126:39, :143:7] wire [31:0] _res_hit_msbMatch_T_72 = ~_res_hit_msbMatch_T_71; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbMatch_T_73 = {_res_hit_msbMatch_T_72[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbMatch_T_74 = ~_res_hit_msbMatch_T_73; // @[PMP.scala:60:{27,48}] wire [25:0] _res_hit_msbMatch_T_75 = _res_hit_msbMatch_T_74[31:6]; // @[PMP.scala:60:27, :69:53] wire [25:0] _res_hit_msbMatch_T_77 = _res_hit_msbMatch_T_70 ^ _res_hit_msbMatch_T_75; // @[PMP.scala:63:47, :69:{29,53}] wire [25:0] _res_hit_msbMatch_T_78 = ~_res_hit_msbMatch_T_76; // @[PMP.scala:63:54, :69:72] wire [25:0] _res_hit_msbMatch_T_79 = _res_hit_msbMatch_T_77 & _res_hit_msbMatch_T_78; // @[PMP.scala:63:{47,52,54}] wire res_hit_msbMatch_7 = _res_hit_msbMatch_T_79 == 26'h0; // @[PMP.scala:63:{52,58}, :80:52, :81:54, :123:67] wire [31:0] _res_hit_lsbMatch_T_72 = ~_res_hit_lsbMatch_T_71; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_lsbMatch_T_73 = {_res_hit_lsbMatch_T_72[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbMatch_T_74 = ~_res_hit_lsbMatch_T_73; // @[PMP.scala:60:{27,48}] wire [5:0] _res_hit_lsbMatch_T_75 = _res_hit_lsbMatch_T_74[5:0]; // @[PMP.scala:60:27, :70:55] wire [5:0] _res_hit_lsbMatch_T_76 = res_hit_lsbMask_7[5:0]; // @[PMP.scala:68:26, :70:80] wire [5:0] _res_hit_lsbMatch_T_77 = _res_hit_lsbMatch_T_70 ^ _res_hit_lsbMatch_T_75; // @[PMP.scala:63:47, :70:{28,55}] wire [5:0] _res_hit_lsbMatch_T_78 = ~_res_hit_lsbMatch_T_76; // @[PMP.scala:63:54, :70:80] wire [5:0] _res_hit_lsbMatch_T_79 = _res_hit_lsbMatch_T_77 & _res_hit_lsbMatch_T_78; // @[PMP.scala:63:{47,52,54}] wire res_hit_lsbMatch_7 = _res_hit_lsbMatch_T_79 == 6'h0; // @[PMP.scala:63:{52,58}] wire _res_hit_T_92 = res_hit_msbMatch_7 & res_hit_lsbMatch_7; // @[PMP.scala:63:58, :71:16] wire _res_hit_T_93 = io_pmp_0_cfg_a_0[0]; // @[PMP.scala:46:26, :143:7] wire [25:0] _res_hit_msbsEqual_T_104 = _res_hit_msbsEqual_T_98; // @[PMP.scala:81:{27,41}] wire res_hit_msbsEqual_14 = _res_hit_msbsEqual_T_104 == 26'h0; // @[PMP.scala:80:52, :81:{41,54,69}, :123:67] wire [5:0] _res_hit_lsbsLess_T_99 = _res_hit_lsbsLess_T_98; // @[PMP.scala:82:{25,42}] wire [31:0] _res_hit_msbsLess_T_92 = ~_res_hit_msbsLess_T_91; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsLess_T_93 = {_res_hit_msbsLess_T_92[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsLess_T_94 = ~_res_hit_msbsLess_T_93; // @[PMP.scala:60:{27,48}] wire [25:0] _res_hit_msbsLess_T_95 = _res_hit_msbsLess_T_94[31:6]; // @[PMP.scala:60:27, :80:52] wire res_hit_msbsLess_15 = _res_hit_msbsLess_T_90 < _res_hit_msbsLess_T_95; // @[PMP.scala:80:{25,39,52}] wire [31:0] _res_hit_msbsEqual_T_107 = ~_res_hit_msbsEqual_T_106; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsEqual_T_108 = {_res_hit_msbsEqual_T_107[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsEqual_T_109 = ~_res_hit_msbsEqual_T_108; // @[PMP.scala:60:{27,48}] wire [25:0] _res_hit_msbsEqual_T_110 = _res_hit_msbsEqual_T_109[31:6]; // @[PMP.scala:60:27, :81:54] wire [25:0] _res_hit_msbsEqual_T_111 = _res_hit_msbsEqual_T_105 ^ _res_hit_msbsEqual_T_110; // @[PMP.scala:81:{27,41,54}] wire res_hit_msbsEqual_15 = _res_hit_msbsEqual_T_111 == 26'h0; // @[PMP.scala:80:52, :81:{41,54,69}, :123:67] wire [5:0] _res_hit_lsbsLess_T_106 = _res_hit_lsbsLess_T_105; // @[PMP.scala:82:{25,42}] wire [31:0] _res_hit_lsbsLess_T_108 = ~_res_hit_lsbsLess_T_107; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_lsbsLess_T_109 = {_res_hit_lsbsLess_T_108[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbsLess_T_110 = ~_res_hit_lsbsLess_T_109; // @[PMP.scala:60:{27,48}] wire [5:0] _res_hit_lsbsLess_T_111 = _res_hit_lsbsLess_T_110[5:0]; // @[PMP.scala:60:27, :82:64] wire res_hit_lsbsLess_15 = _res_hit_lsbsLess_T_106 < _res_hit_lsbsLess_T_111; // @[PMP.scala:82:{42,53,64}] wire _res_hit_T_100 = res_hit_msbsEqual_15 & res_hit_lsbsLess_15; // @[PMP.scala:81:69, :82:53, :83:30] wire _res_hit_T_101 = res_hit_msbsLess_15 | _res_hit_T_100; // @[PMP.scala:80:39, :83:{16,30}] wire _res_hit_T_102 = _res_hit_T_101; // @[PMP.scala:83:16, :94:48] wire _res_hit_T_103 = _res_hit_T_93 & _res_hit_T_102; // @[PMP.scala:46:26, :94:48, :132:61] wire res_hit_7 = _res_hit_T_91 ? _res_hit_T_92 : _res_hit_T_103; // @[PMP.scala:45:20, :71:16, :132:{8,61}] wire _res_ignore_T_7 = ~io_pmp_0_cfg_l_0; // @[PMP.scala:143:7, :164:29] wire res_ignore_7 = default_0 & _res_ignore_T_7; // @[PMP.scala:156:56, :164:{26,29}] wire [25:0] _res_aligned_straddlesLowerBound_T_125 = _res_aligned_straddlesLowerBound_T_119; // @[PMP.scala:123:{35,49}] wire _res_aligned_straddlesLowerBound_T_126 = _res_aligned_straddlesLowerBound_T_125 == 26'h0; // @[PMP.scala:80:52, :81:54, :123:{49,67,82}] wire [5:0] _res_aligned_straddlesLowerBound_T_133 = ~_res_aligned_straddlesLowerBound_T_132; // @[PMP.scala:123:{127,129}] wire [31:0] _res_aligned_straddlesUpperBound_T_121 = ~_res_aligned_straddlesUpperBound_T_120; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesUpperBound_T_122 = {_res_aligned_straddlesUpperBound_T_121[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesUpperBound_T_123 = ~_res_aligned_straddlesUpperBound_T_122; // @[PMP.scala:60:{27,48}] wire [25:0] _res_aligned_straddlesUpperBound_T_124 = _res_aligned_straddlesUpperBound_T_123[31:6]; // @[PMP.scala:60:27, :124:62] wire [25:0] _res_aligned_straddlesUpperBound_T_125 = _res_aligned_straddlesUpperBound_T_119 ^ _res_aligned_straddlesUpperBound_T_124; // @[PMP.scala:124:{35,49,62}] wire _res_aligned_straddlesUpperBound_T_126 = _res_aligned_straddlesUpperBound_T_125 == 26'h0; // @[PMP.scala:80:52, :81:54, :123:67, :124:{49,77}] wire [31:0] _res_aligned_straddlesUpperBound_T_128 = ~_res_aligned_straddlesUpperBound_T_127; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesUpperBound_T_129 = {_res_aligned_straddlesUpperBound_T_128[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesUpperBound_T_130 = ~_res_aligned_straddlesUpperBound_T_129; // @[PMP.scala:60:{27,48}] wire [5:0] _res_aligned_straddlesUpperBound_T_131 = _res_aligned_straddlesUpperBound_T_130[5:0]; // @[PMP.scala:60:27, :124:98] wire [5:0] _res_aligned_straddlesUpperBound_T_133 = _res_aligned_straddlesUpperBound_T_132; // @[PMP.scala:124:{119,136}] wire [5:0] _res_aligned_straddlesUpperBound_T_134 = _res_aligned_straddlesUpperBound_T_131 & _res_aligned_straddlesUpperBound_T_133; // @[PMP.scala:124:{98,115,136}] wire _res_aligned_straddlesUpperBound_T_135 = |_res_aligned_straddlesUpperBound_T_134; // @[PMP.scala:124:{115,148}] wire res_aligned_straddlesUpperBound_7 = _res_aligned_straddlesUpperBound_T_126 & _res_aligned_straddlesUpperBound_T_135; // @[PMP.scala:124:{77,85,148}] wire _res_aligned_rangeAligned_T_7 = res_aligned_straddlesUpperBound_7; // @[PMP.scala:124:85, :125:46] wire res_aligned_rangeAligned_7 = ~_res_aligned_rangeAligned_T_7; // @[PMP.scala:125:{24,46}] wire [5:0] _res_aligned_pow2Aligned_T_22 = ~_res_aligned_pow2Aligned_T_21; // @[PMP.scala:126:{34,39}] wire res_aligned_7 = _res_aligned_T_7 | res_aligned_rangeAligned_7; // @[PMP.scala:45:20, :125:24, :127:8] wire _res_T_315 = io_pmp_0_cfg_a_0 == 2'h0; // @[PMP.scala:143:7, :168:32] wire _GEN_35 = io_pmp_0_cfg_a_0 == 2'h1; // @[PMP.scala:143:7, :168:32] wire _res_T_316; // @[PMP.scala:168:32] assign _res_T_316 = _GEN_35; // @[PMP.scala:168:32] wire _res_T_335; // @[PMP.scala:177:61] assign _res_T_335 = _GEN_35; // @[PMP.scala:168:32, :177:61] wire _res_T_339; // @[PMP.scala:178:63] assign _res_T_339 = _GEN_35; // @[PMP.scala:168:32, :178:63] wire _GEN_36 = io_pmp_0_cfg_a_0 == 2'h2; // @[PMP.scala:143:7, :168:32] wire _res_T_317; // @[PMP.scala:168:32] assign _res_T_317 = _GEN_36; // @[PMP.scala:168:32] wire _res_T_344; // @[PMP.scala:177:61] assign _res_T_344 = _GEN_36; // @[PMP.scala:168:32, :177:61] wire _res_T_348; // @[PMP.scala:178:63] assign _res_T_348 = _GEN_36; // @[PMP.scala:168:32, :178:63] wire _res_T_318 = &io_pmp_0_cfg_a_0; // @[PMP.scala:143:7, :168:32] wire [1:0] _GEN_37 = {io_pmp_0_cfg_x_0, io_pmp_0_cfg_w_0}; // @[PMP.scala:143:7, :174:26] wire [1:0] res_hi_42; // @[PMP.scala:174:26] assign res_hi_42 = _GEN_37; // @[PMP.scala:174:26] wire [1:0] res_hi_43; // @[PMP.scala:174:26] assign res_hi_43 = _GEN_37; // @[PMP.scala:174:26] wire [1:0] res_hi_44; // @[PMP.scala:174:26] assign res_hi_44 = _GEN_37; // @[PMP.scala:174:26] wire [1:0] res_hi_45; // @[PMP.scala:174:26] assign res_hi_45 = _GEN_37; // @[PMP.scala:174:26] wire [1:0] res_hi_46; // @[PMP.scala:174:26] assign res_hi_46 = _GEN_37; // @[PMP.scala:174:26] wire [1:0] res_hi_47; // @[PMP.scala:174:26] assign res_hi_47 = _GEN_37; // @[PMP.scala:174:26] wire [2:0] _res_T_320 = {res_hi_42, io_pmp_0_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_321 = _res_T_320 == 3'h0; // @[PMP.scala:143:7, :146:14, :174:{26,60}] wire [2:0] _res_T_322 = {res_hi_43, io_pmp_0_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_323 = _res_T_322 == 3'h1; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_324 = {res_hi_44, io_pmp_0_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_325 = _res_T_324 == 3'h3; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_326 = {res_hi_45, io_pmp_0_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_327 = _res_T_326 == 3'h4; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_328 = {res_hi_46, io_pmp_0_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_329 = _res_T_328 == 3'h5; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_330 = {res_hi_47, io_pmp_0_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_331 = &_res_T_330; // @[PMP.scala:174:{26,60}] wire _res_T_332 = ~res_ignore_7; // @[PMP.scala:164:26, :177:22] wire _res_T_333 = _res_T_332 & res_hit_7; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_334 = _res_T_333 & res_aligned_7; // @[PMP.scala:127:8, :177:{30,37}] wire _res_T_336 = _res_T_334 & _res_T_335; // @[PMP.scala:177:{37,48,61}] wire _GEN_38 = io_pmp_0_cfg_l_0 & res_hit_7; // @[PMP.scala:132:8, :143:7, :178:32] wire _res_T_337; // @[PMP.scala:178:32] assign _res_T_337 = _GEN_38; // @[PMP.scala:178:32] wire _res_T_346; // @[PMP.scala:178:32] assign _res_T_346 = _GEN_38; // @[PMP.scala:178:32] wire _res_T_355; // @[PMP.scala:178:32] assign _res_T_355 = _GEN_38; // @[PMP.scala:178:32] wire _res_T_338 = _res_T_337 & res_aligned_7; // @[PMP.scala:127:8, :178:{32,39}] wire _res_T_340 = _res_T_338 & _res_T_339; // @[PMP.scala:178:{39,50,63}] wire _res_T_341 = ~res_ignore_7; // @[PMP.scala:164:26, :177:22] wire _res_T_342 = _res_T_341 & res_hit_7; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_343 = _res_T_342 & res_aligned_7; // @[PMP.scala:127:8, :177:{30,37}] wire _res_T_345 = _res_T_343 & _res_T_344; // @[PMP.scala:177:{37,48,61}] wire _res_T_347 = _res_T_346 & res_aligned_7; // @[PMP.scala:127:8, :178:{32,39}] wire _res_T_349 = _res_T_347 & _res_T_348; // @[PMP.scala:178:{39,50,63}] wire _res_T_350 = ~res_ignore_7; // @[PMP.scala:164:26, :177:22] wire _res_T_351 = _res_T_350 & res_hit_7; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_352 = _res_T_351 & res_aligned_7; // @[PMP.scala:127:8, :177:{30,37}] wire _res_T_353 = &io_pmp_0_cfg_a_0; // @[PMP.scala:143:7, :168:32, :177:61] wire _res_T_354 = _res_T_352 & _res_T_353; // @[PMP.scala:177:{37,48,61}] wire _res_T_356 = _res_T_355 & res_aligned_7; // @[PMP.scala:127:8, :178:{32,39}] wire _res_T_357 = &io_pmp_0_cfg_a_0; // @[PMP.scala:143:7, :168:32, :178:63] wire _res_T_358 = _res_T_356 & _res_T_357; // @[PMP.scala:178:{39,50,63}] wire _res_cur_cfg_x_T_15; // @[PMP.scala:184:26] wire _res_cur_cfg_w_T_15; // @[PMP.scala:183:26] wire _res_cur_cfg_r_T_15; // @[PMP.scala:182:26] wire res_cur_7_cfg_x; // @[PMP.scala:181:23] wire res_cur_7_cfg_w; // @[PMP.scala:181:23] wire res_cur_7_cfg_r; // @[PMP.scala:181:23] wire _res_cur_cfg_r_T_14 = io_pmp_0_cfg_r_0 | res_ignore_7; // @[PMP.scala:143:7, :164:26, :182:40] assign _res_cur_cfg_r_T_15 = res_aligned_7 & _res_cur_cfg_r_T_14; // @[PMP.scala:127:8, :182:{26,40}] assign res_cur_7_cfg_r = _res_cur_cfg_r_T_15; // @[PMP.scala:181:23, :182:26] wire _res_cur_cfg_w_T_14 = io_pmp_0_cfg_w_0 | res_ignore_7; // @[PMP.scala:143:7, :164:26, :183:40] assign _res_cur_cfg_w_T_15 = res_aligned_7 & _res_cur_cfg_w_T_14; // @[PMP.scala:127:8, :183:{26,40}] assign res_cur_7_cfg_w = _res_cur_cfg_w_T_15; // @[PMP.scala:181:23, :183:26] wire _res_cur_cfg_x_T_14 = io_pmp_0_cfg_x_0 | res_ignore_7; // @[PMP.scala:143:7, :164:26, :184:40] assign _res_cur_cfg_x_T_15 = res_aligned_7 & _res_cur_cfg_x_T_14; // @[PMP.scala:127:8, :184:{26,40}] assign res_cur_7_cfg_x = _res_cur_cfg_x_T_15; // @[PMP.scala:181:23, :184:26] wire res_cfg_l = res_hit_7 ? res_cur_7_cfg_l : _res_T_314_cfg_l; // @[PMP.scala:132:8, :181:23, :185:8] wire [1:0] res_cfg_a = res_hit_7 ? res_cur_7_cfg_a : _res_T_314_cfg_a; // @[PMP.scala:132:8, :181:23, :185:8] assign res_cfg_x = res_hit_7 ? res_cur_7_cfg_x : _res_T_314_cfg_x; // @[PMP.scala:132:8, :181:23, :185:8] assign res_cfg_w = res_hit_7 ? res_cur_7_cfg_w : _res_T_314_cfg_w; // @[PMP.scala:132:8, :181:23, :185:8] assign res_cfg_r = res_hit_7 ? res_cur_7_cfg_r : _res_T_314_cfg_r; // @[PMP.scala:132:8, :181:23, :185:8] wire [29:0] res_addr = res_hit_7 ? res_cur_7_addr : _res_T_314_addr; // @[PMP.scala:132:8, :181:23, :185:8] wire [31:0] res_mask = res_hit_7 ? res_cur_7_mask : _res_T_314_mask; // @[PMP.scala:132:8, :181:23, :185:8] assign io_x_0 = res_cfg_x; // @[PMP.scala:143:7, :185:8] assign io_w_0 = res_cfg_w; // @[PMP.scala:143:7, :185:8] assign io_r_0 = res_cfg_r; // @[PMP.scala:143:7, :185:8] assign io_r = io_r_0; // @[PMP.scala:143:7] assign io_w = io_w_0; // @[PMP.scala:143:7] assign io_x = io_x_0; // @[PMP.scala:143:7] endmodule

Generate the Verilog code corresponding to the following Chisel files. File CompareRecFN.scala: /*============================================================================ This Chisel source file is part of a pre-release version of the HardFloat IEEE Floating-Point Arithmetic Package, by John R. Hauser (with some contributions from Yunsup Lee and Andrew Waterman, mainly concerning testing). Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of California. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions, and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions, and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the University nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. =============================================================================*/ package hardfloat import chisel3._ class CompareRecFN(expWidth: Int, sigWidth: Int) extends RawModule { val io = IO(new Bundle { val a = Input(Bits((expWidth + sigWidth + 1).W)) val b = Input(Bits((expWidth + sigWidth + 1).W)) val signaling = Input(Bool()) val lt = Output(Bool()) val eq = Output(Bool()) val gt = Output(Bool()) val exceptionFlags = Output(Bits(5.W)) }) val rawA = rawFloatFromRecFN(expWidth, sigWidth, io.a) val rawB = rawFloatFromRecFN(expWidth, sigWidth, io.b) val ordered = ! rawA.isNaN && ! rawB.isNaN val bothInfs = rawA.isInf && rawB.isInf val bothZeros = rawA.isZero && rawB.isZero val eqExps = (rawA.sExp === rawB.sExp) val common_ltMags = (rawA.sExp < rawB.sExp) || (eqExps && (rawA.sig < rawB.sig)) val common_eqMags = eqExps && (rawA.sig === rawB.sig) val ordered_lt = ! bothZeros && ((rawA.sign && ! rawB.sign) || (! bothInfs && ((rawA.sign && ! common_ltMags && ! common_eqMags) || (! rawB.sign && common_ltMags)))) val ordered_eq = bothZeros || ((rawA.sign === rawB.sign) && (bothInfs || common_eqMags)) val invalid = isSigNaNRawFloat(rawA) || isSigNaNRawFloat(rawB) || (io.signaling && ! ordered) io.lt := ordered && ordered_lt io.eq := ordered && ordered_eq io.gt := ordered && ! ordered_lt && ! ordered_eq io.exceptionFlags := invalid ## 0.U(4.W) } File rawFloatFromRecFN.scala: /*============================================================================ This Chisel source file is part of a pre-release version of the HardFloat IEEE Floating-Point Arithmetic Package, by John R. Hauser (with some contributions from Yunsup Lee and Andrew Waterman, mainly concerning testing). Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of California. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions, and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions, and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the University nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. =============================================================================*/ package hardfloat import chisel3._ import chisel3.util._ /*---------------------------------------------------------------------------- | In the result, no more than one of 'isNaN', 'isInf', and 'isZero' will be | set. *----------------------------------------------------------------------------*/ object rawFloatFromRecFN { def apply(expWidth: Int, sigWidth: Int, in: Bits): RawFloat = { val exp = in(expWidth + sigWidth - 1, sigWidth - 1) val isZero = exp(expWidth, expWidth - 2) === 0.U val isSpecial = exp(expWidth, expWidth - 1) === 3.U val out = Wire(new RawFloat(expWidth, sigWidth)) out.isNaN := isSpecial && exp(expWidth - 2) out.isInf := isSpecial && ! exp(expWidth - 2) out.isZero := isZero out.sign := in(expWidth + sigWidth) out.sExp := exp.zext out.sig := 0.U(1.W) ## ! isZero ## in(sigWidth - 2, 0) out } }

module CompareRecFN_5( // @[CompareRecFN.scala:42:7] input [64:0] io_a, // @[CompareRecFN.scala:44:16] input [64:0] io_b, // @[CompareRecFN.scala:44:16] input io_signaling, // @[CompareRecFN.scala:44:16] output io_lt, // @[CompareRecFN.scala:44:16] output io_eq, // @[CompareRecFN.scala:44:16] output [4:0] io_exceptionFlags // @[CompareRecFN.scala:44:16] ); wire [64:0] io_a_0 = io_a; // @[CompareRecFN.scala:42:7] wire [64:0] io_b_0 = io_b; // @[CompareRecFN.scala:42:7] wire io_signaling_0 = io_signaling; // @[CompareRecFN.scala:42:7] wire _io_lt_T; // @[CompareRecFN.scala:78:22] wire _io_eq_T; // @[CompareRecFN.scala:79:22] wire _io_gt_T_3; // @[CompareRecFN.scala:80:38] wire [4:0] _io_exceptionFlags_T; // @[CompareRecFN.scala:81:34] wire io_lt_0; // @[CompareRecFN.scala:42:7] wire io_eq_0; // @[CompareRecFN.scala:42:7] wire io_gt; // @[CompareRecFN.scala:42:7] wire [4:0] io_exceptionFlags_0; // @[CompareRecFN.scala:42:7] wire [11:0] rawA_exp = io_a_0[63:52]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _rawA_isZero_T = rawA_exp[11:9]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire rawA_isZero = _rawA_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire rawA_isZero_0 = rawA_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _rawA_isSpecial_T = rawA_exp[11:10]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire rawA_isSpecial = &_rawA_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _rawA_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33] wire _rawA_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33] wire _rawA_out_sign_T; // @[rawFloatFromRecFN.scala:59:25] wire [12:0] _rawA_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27] wire [53:0] _rawA_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44] wire rawA_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire rawA_isInf; // @[rawFloatFromRecFN.scala:55:23] wire rawA_sign; // @[rawFloatFromRecFN.scala:55:23] wire [12:0] rawA_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [53:0] rawA_sig; // @[rawFloatFromRecFN.scala:55:23] wire _rawA_out_isNaN_T = rawA_exp[9]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _rawA_out_isInf_T = rawA_exp[9]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _rawA_out_isNaN_T_1 = rawA_isSpecial & _rawA_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign rawA_isNaN = _rawA_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _rawA_out_isInf_T_1 = ~_rawA_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _rawA_out_isInf_T_2 = rawA_isSpecial & _rawA_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign rawA_isInf = _rawA_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _rawA_out_sign_T = io_a_0[64]; // @[rawFloatFromRecFN.scala:59:25] assign rawA_sign = _rawA_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _rawA_out_sExp_T = {1'h0, rawA_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign rawA_sExp = _rawA_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _rawA_out_sig_T = ~rawA_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _rawA_out_sig_T_1 = {1'h0, _rawA_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [51:0] _rawA_out_sig_T_2 = io_a_0[51:0]; // @[rawFloatFromRecFN.scala:61:49] assign _rawA_out_sig_T_3 = {_rawA_out_sig_T_1, _rawA_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign rawA_sig = _rawA_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire [11:0] rawB_exp = io_b_0[63:52]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _rawB_isZero_T = rawB_exp[11:9]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire rawB_isZero = _rawB_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire rawB_isZero_0 = rawB_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _rawB_isSpecial_T = rawB_exp[11:10]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire rawB_isSpecial = &_rawB_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _rawB_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33] wire _rawB_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33] wire _rawB_out_sign_T; // @[rawFloatFromRecFN.scala:59:25] wire [12:0] _rawB_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27] wire [53:0] _rawB_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44] wire rawB_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire rawB_isInf; // @[rawFloatFromRecFN.scala:55:23] wire rawB_sign; // @[rawFloatFromRecFN.scala:55:23] wire [12:0] rawB_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [53:0] rawB_sig; // @[rawFloatFromRecFN.scala:55:23] wire _rawB_out_isNaN_T = rawB_exp[9]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _rawB_out_isInf_T = rawB_exp[9]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _rawB_out_isNaN_T_1 = rawB_isSpecial & _rawB_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign rawB_isNaN = _rawB_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _rawB_out_isInf_T_1 = ~_rawB_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _rawB_out_isInf_T_2 = rawB_isSpecial & _rawB_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign rawB_isInf = _rawB_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _rawB_out_sign_T = io_b_0[64]; // @[rawFloatFromRecFN.scala:59:25] assign rawB_sign = _rawB_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _rawB_out_sExp_T = {1'h0, rawB_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign rawB_sExp = _rawB_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _rawB_out_sig_T = ~rawB_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _rawB_out_sig_T_1 = {1'h0, _rawB_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [51:0] _rawB_out_sig_T_2 = io_b_0[51:0]; // @[rawFloatFromRecFN.scala:61:49] assign _rawB_out_sig_T_3 = {_rawB_out_sig_T_1, _rawB_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign rawB_sig = _rawB_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire _ordered_T = ~rawA_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire _ordered_T_1 = ~rawB_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire ordered = _ordered_T & _ordered_T_1; // @[CompareRecFN.scala:57:{19,32,35}] wire bothInfs = rawA_isInf & rawB_isInf; // @[rawFloatFromRecFN.scala:55:23] wire bothZeros = rawA_isZero_0 & rawB_isZero_0; // @[rawFloatFromRecFN.scala:55:23] wire eqExps = rawA_sExp == rawB_sExp; // @[rawFloatFromRecFN.scala:55:23] wire _common_ltMags_T = $signed(rawA_sExp) < $signed(rawB_sExp); // @[rawFloatFromRecFN.scala:55:23] wire _common_ltMags_T_1 = rawA_sig < rawB_sig; // @[rawFloatFromRecFN.scala:55:23] wire _common_ltMags_T_2 = eqExps & _common_ltMags_T_1; // @[CompareRecFN.scala:60:29, :62:{44,57}] wire common_ltMags = _common_ltMags_T | _common_ltMags_T_2; // @[CompareRecFN.scala:62:{20,33,44}] wire _common_eqMags_T = rawA_sig == rawB_sig; // @[rawFloatFromRecFN.scala:55:23] wire common_eqMags = eqExps & _common_eqMags_T; // @[CompareRecFN.scala:60:29, :63:{32,45}] wire _ordered_lt_T = ~bothZeros; // @[CompareRecFN.scala:59:33, :66:9] wire _ordered_lt_T_1 = ~rawB_sign; // @[rawFloatFromRecFN.scala:55:23] wire _ordered_lt_T_2 = rawA_sign & _ordered_lt_T_1; // @[rawFloatFromRecFN.scala:55:23] wire _ordered_lt_T_3 = ~bothInfs; // @[CompareRecFN.scala:58:33, :68:19] wire _ordered_lt_T_4 = ~common_ltMags; // @[CompareRecFN.scala:62:33, :69:38] wire _ordered_lt_T_5 = rawA_sign & _ordered_lt_T_4; // @[rawFloatFromRecFN.scala:55:23] wire _ordered_lt_T_6 = ~common_eqMags; // @[CompareRecFN.scala:63:32, :69:57] wire _ordered_lt_T_7 = _ordered_lt_T_5 & _ordered_lt_T_6; // @[CompareRecFN.scala:69:{35,54,57}] wire _ordered_lt_T_8 = ~rawB_sign; // @[rawFloatFromRecFN.scala:55:23] wire _ordered_lt_T_9 = _ordered_lt_T_8 & common_ltMags; // @[CompareRecFN.scala:62:33, :70:{29,41}] wire _ordered_lt_T_10 = _ordered_lt_T_7 | _ordered_lt_T_9; // @[CompareRecFN.scala:69:{54,74}, :70:41] wire _ordered_lt_T_11 = _ordered_lt_T_3 & _ordered_lt_T_10; // @[CompareRecFN.scala:68:{19,30}, :69:74] wire _ordered_lt_T_12 = _ordered_lt_T_2 | _ordered_lt_T_11; // @[CompareRecFN.scala:67:{25,41}, :68:30] wire ordered_lt = _ordered_lt_T & _ordered_lt_T_12; // @[CompareRecFN.scala:66:{9,21}, :67:41] wire _ordered_eq_T = rawA_sign == rawB_sign; // @[rawFloatFromRecFN.scala:55:23] wire _ordered_eq_T_1 = bothInfs | common_eqMags; // @[CompareRecFN.scala:58:33, :63:32, :72:62] wire _ordered_eq_T_2 = _ordered_eq_T & _ordered_eq_T_1; // @[CompareRecFN.scala:72:{34,49,62}] wire ordered_eq = bothZeros | _ordered_eq_T_2; // @[CompareRecFN.scala:59:33, :72:{19,49}] wire _invalid_T = rawA_sig[51]; // @[rawFloatFromRecFN.scala:55:23] wire _invalid_T_1 = ~_invalid_T; // @[common.scala:82:{49,56}] wire _invalid_T_2 = rawA_isNaN & _invalid_T_1; // @[rawFloatFromRecFN.scala:55:23] wire _invalid_T_3 = rawB_sig[51]; // @[rawFloatFromRecFN.scala:55:23] wire _invalid_T_4 = ~_invalid_T_3; // @[common.scala:82:{49,56}] wire _invalid_T_5 = rawB_isNaN & _invalid_T_4; // @[rawFloatFromRecFN.scala:55:23] wire _invalid_T_6 = _invalid_T_2 | _invalid_T_5; // @[common.scala:82:46] wire _invalid_T_7 = ~ordered; // @[CompareRecFN.scala:57:32, :76:30] wire _invalid_T_8 = io_signaling_0 & _invalid_T_7; // @[CompareRecFN.scala:42:7, :76:{27,30}] wire invalid = _invalid_T_6 | _invalid_T_8; // @[CompareRecFN.scala:75:{32,58}, :76:27] assign _io_lt_T = ordered & ordered_lt; // @[CompareRecFN.scala:57:32, :66:21, :78:22] assign io_lt_0 = _io_lt_T; // @[CompareRecFN.scala:42:7, :78:22] assign _io_eq_T = ordered & ordered_eq; // @[CompareRecFN.scala:57:32, :72:19, :79:22] assign io_eq_0 = _io_eq_T; // @[CompareRecFN.scala:42:7, :79:22] wire _io_gt_T = ~ordered_lt; // @[CompareRecFN.scala:66:21, :80:25] wire _io_gt_T_1 = ordered & _io_gt_T; // @[CompareRecFN.scala:57:32, :80:{22,25}] wire _io_gt_T_2 = ~ordered_eq; // @[CompareRecFN.scala:72:19, :80:41] assign _io_gt_T_3 = _io_gt_T_1 & _io_gt_T_2; // @[CompareRecFN.scala:80:{22,38,41}] assign io_gt = _io_gt_T_3; // @[CompareRecFN.scala:42:7, :80:38] assign _io_exceptionFlags_T = {invalid, 4'h0}; // @[CompareRecFN.scala:75:58, :81:34] assign io_exceptionFlags_0 = _io_exceptionFlags_T; // @[CompareRecFN.scala:42:7, :81:34] assign io_lt = io_lt_0; // @[CompareRecFN.scala:42:7] assign io_eq = io_eq_0; // @[CompareRecFN.scala:42:7] assign io_exceptionFlags = io_exceptionFlags_0; // @[CompareRecFN.scala:42:7] endmodule

Generate the Verilog code corresponding to the following Chisel files. File Monitor.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceLine import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import freechips.rocketchip.diplomacy.EnableMonitors import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode} import freechips.rocketchip.util.PlusArg case class TLMonitorArgs(edge: TLEdge) abstract class TLMonitorBase(args: TLMonitorArgs) extends Module { val io = IO(new Bundle { val in = Input(new TLBundle(args.edge.bundle)) }) def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit legalize(io.in, args.edge, reset) } object TLMonitor { def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = { if (enable) { EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) } } else { node } } } class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args) { require (args.edge.params(TLMonitorStrictMode) || (! args.edge.params(TestplanTestType).formal)) val cover_prop_class = PropertyClass.Default //Like assert but can flip to being an assumption for formal verification def monAssert(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir, cond, message, PropertyClass.Default) } def assume(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir.flip, cond, message, PropertyClass.Default) } def extra = { args.edge.sourceInfo match { case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)" case _ => "" } } def visible(address: UInt, source: UInt, edge: TLEdge) = edge.client.clients.map { c => !c.sourceId.contains(source) || c.visibility.map(_.contains(address)).reduce(_ || _) }.reduce(_ && _) def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = { //switch this flag to turn on diplomacy in error messages def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n" monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra) // Reuse these subexpressions to save some firrtl lines val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility") //The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B //TODO: check for acquireT? when (bundle.opcode === TLMessages.AcquireBlock) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra) } when (bundle.opcode === TLMessages.AcquirePerm) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra) monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra) monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra) monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra) } } def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = { monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra) monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility") // Reuse these subexpressions to save some firrtl lines val address_ok = edge.manager.containsSafe(edge.address(bundle)) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source when (bundle.opcode === TLMessages.Probe) { assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra) assume (address_ok, "'B' channel Probe carries unmanaged address" + extra) assume (legal_source, "'B' channel Probe carries source that is not first source" + extra) assume (is_aligned, "'B' channel Probe address not aligned to size" + extra) assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra) assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra) assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra) monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra) monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra) monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra) monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra) } } def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = { monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val address_ok = edge.manager.containsSafe(edge.address(bundle)) monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility") when (bundle.opcode === TLMessages.ProbeAck) { monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra) } when (bundle.opcode === TLMessages.ProbeAckData) { monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.Release) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra) monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra) } when (bundle.opcode === TLMessages.ReleaseData) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.AccessAck) { monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra) } when (bundle.opcode === TLMessages.HintAck) { monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra) } } def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = { assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val sink_ok = bundle.sink < edge.manager.endSinkId.U val deny_put_ok = edge.manager.mayDenyPut.B val deny_get_ok = edge.manager.mayDenyGet.B when (bundle.opcode === TLMessages.ReleaseAck) { assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra) assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra) assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra) } when (bundle.opcode === TLMessages.Grant) { assume (source_ok, "'D' channel Grant carries invalid source ID" + extra) assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra) assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel Grant is denied" + extra) } when (bundle.opcode === TLMessages.GrantData) { assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra) assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra) assume (!bundle.denied || bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra) assume (deny_get_ok || !bundle.denied, "'D' channel GrantData is denied" + extra) } when (bundle.opcode === TLMessages.AccessAck) { assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel AccessAck is denied" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra) assume (!bundle.denied || bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra) assume (deny_get_ok || !bundle.denied, "'D' channel AccessAckData is denied" + extra) } when (bundle.opcode === TLMessages.HintAck) { assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel HintAck is denied" + extra) } } def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = { val sink_ok = bundle.sink < edge.manager.endSinkId.U monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra) } def legalizeFormat(bundle: TLBundle, edge: TLEdge) = { when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) } when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) } when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) } when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) } } else { monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra) monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra) monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra) } } def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = { val a_first = edge.first(a.bits, a.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (a.valid && !a_first) { monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra) monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra) monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra) monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra) monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra) } when (a.fire && a_first) { opcode := a.bits.opcode param := a.bits.param size := a.bits.size source := a.bits.source address := a.bits.address } } def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = { val b_first = edge.first(b.bits, b.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (b.valid && !b_first) { monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra) monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra) monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra) monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra) monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra) } when (b.fire && b_first) { opcode := b.bits.opcode param := b.bits.param size := b.bits.size source := b.bits.source address := b.bits.address } } def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = { // Symbolic variable val sym_source = Wire(UInt(edge.client.endSourceId.W)) // TODO: Connect sym_source to a fixed value for simulation and to a // free wire in formal sym_source := 0.U // Type casting Int to UInt val maxSourceId = Wire(UInt(edge.client.endSourceId.W)) maxSourceId := edge.client.endSourceId.U // Delayed verison of sym_source val sym_source_d = Reg(UInt(edge.client.endSourceId.W)) sym_source_d := sym_source // These will be constraints for FV setup Property( MonitorDirection.Monitor, (sym_source === sym_source_d), "sym_source should remain stable", PropertyClass.Default) Property( MonitorDirection.Monitor, (sym_source <= maxSourceId), "sym_source should take legal value", PropertyClass.Default) val my_resp_pend = RegInit(false.B) val my_opcode = Reg(UInt()) val my_size = Reg(UInt()) val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire) val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire) val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source) val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source) val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat) val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend) when (my_set_resp_pend) { my_resp_pend := true.B } .elsewhen (my_clr_resp_pend) { my_resp_pend := false.B } when (my_a_first_beat) { my_opcode := bundle.a.bits.opcode my_size := bundle.a.bits.size } val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size) val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode) val my_resp_opcode_legal = Wire(Bool()) when ((my_resp_opcode === TLMessages.Get) || (my_resp_opcode === TLMessages.ArithmeticData) || (my_resp_opcode === TLMessages.LogicalData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData) } .elsewhen ((my_resp_opcode === TLMessages.PutFullData) || (my_resp_opcode === TLMessages.PutPartialData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck) } .otherwise { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck) } monAssert (IfThen(my_resp_pend, !my_a_first_beat), "Request message should not be sent with a source ID, for which a response message" + "is already pending (not received until current cycle) for a prior request message" + "with the same source ID" + extra) assume (IfThen(my_clr_resp_pend, (my_set_resp_pend || my_resp_pend)), "Response message should be accepted with a source ID only if a request message with the" + "same source ID has been accepted or is being accepted in the current cycle" + extra) assume (IfThen(my_d_first_beat, (my_a_first_beat || my_resp_pend)), "Response message should be sent with a source ID only if a request message with the" + "same source ID has been accepted or is being sent in the current cycle" + extra) assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)), "If d_valid is 1, then d_size should be same as a_size of the corresponding request" + "message" + extra) assume (IfThen(my_d_first_beat, my_resp_opcode_legal), "If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" + "request message" + extra) } def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = { val c_first = edge.first(c.bits, c.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (c.valid && !c_first) { monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra) monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra) monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra) monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra) monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra) } when (c.fire && c_first) { opcode := c.bits.opcode param := c.bits.param size := c.bits.size source := c.bits.source address := c.bits.address } } def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = { val d_first = edge.first(d.bits, d.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val sink = Reg(UInt()) val denied = Reg(Bool()) when (d.valid && !d_first) { assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra) assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra) assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra) assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra) assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra) assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra) } when (d.fire && d_first) { opcode := d.bits.opcode param := d.bits.param size := d.bits.size source := d.bits.source sink := d.bits.sink denied := d.bits.denied } } def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = { legalizeMultibeatA(bundle.a, edge) legalizeMultibeatD(bundle.d, edge) if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { legalizeMultibeatB(bundle.b, edge) legalizeMultibeatC(bundle.c, edge) } } //This is left in for almond which doesn't adhere to the tilelink protocol @deprecated("Use legalizeADSource instead if possible","") def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.client.endSourceId.W)) val a_first = edge.first(bundle.a.bits, bundle.a.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val a_set = WireInit(0.U(edge.client.endSourceId.W)) when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) assume((a_set | inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra) } if (edge.manager.minLatency > 0) { assume(a_set =/= d_clr || !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight | a_set) & ~d_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") assert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = { val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size) val log_a_size_bus_size = log2Ceil(a_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error inflight.suggestName("inflight") val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) inflight_opcodes.suggestName("inflight_opcodes") val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) inflight_sizes.suggestName("inflight_sizes") val a_first = edge.first(bundle.a.bits, bundle.a.fire) a_first.suggestName("a_first") val d_first = edge.first(bundle.d.bits, bundle.d.fire) d_first.suggestName("d_first") val a_set = WireInit(0.U(edge.client.endSourceId.W)) val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) a_set.suggestName("a_set") a_set_wo_ready.suggestName("a_set_wo_ready") val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) a_opcodes_set.suggestName("a_opcodes_set") val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) a_sizes_set.suggestName("a_sizes_set") val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W)) a_opcode_lookup.suggestName("a_opcode_lookup") a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W)) a_size_lookup.suggestName("a_size_lookup") a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant)) val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant)) val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W)) a_opcodes_set_interm.suggestName("a_opcodes_set_interm") val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W)) a_sizes_set_interm.suggestName("a_sizes_set_interm") when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) { a_set_wo_ready := UIntToOH(bundle.a.bits.source) } when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) | 1.U a_sizes_set_interm := (bundle.a.bits.size << 1.U) | 1.U a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U) a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U) monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) d_opcodes_clr.suggestName("d_opcodes_clr") val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) || (bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra) assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) || (bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra) assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) { assume((!bundle.d.ready) || bundle.a.ready, "ready check") } if (edge.manager.minLatency > 0) { assume(a_set_wo_ready =/= d_clr_wo_ready || !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight | a_set) & ~d_clr inflight_opcodes := (inflight_opcodes | a_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes | a_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = { val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size) val log_c_size_bus_size = log2Ceil(c_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) inflight.suggestName("inflight") inflight_opcodes.suggestName("inflight_opcodes") inflight_sizes.suggestName("inflight_sizes") val c_first = edge.first(bundle.c.bits, bundle.c.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) c_first.suggestName("c_first") d_first.suggestName("d_first") val c_set = WireInit(0.U(edge.client.endSourceId.W)) val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) c_set.suggestName("c_set") c_set_wo_ready.suggestName("c_set_wo_ready") c_opcodes_set.suggestName("c_opcodes_set") c_sizes_set.suggestName("c_sizes_set") val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W)) val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W)) c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U c_opcode_lookup.suggestName("c_opcode_lookup") c_size_lookup.suggestName("c_size_lookup") val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W)) val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W)) c_opcodes_set_interm.suggestName("c_opcodes_set_interm") c_sizes_set_interm.suggestName("c_sizes_set_interm") when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) { c_set_wo_ready := UIntToOH(bundle.c.bits.source) } when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) { c_set := UIntToOH(bundle.c.bits.source) c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) | 1.U c_sizes_set_interm := (bundle.c.bits.size << 1.U) | 1.U c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U) c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U) monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra) } val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck || bundle.c.bits.opcode === TLMessages.ProbeAckData val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") d_opcodes_clr.suggestName("d_opcodes_clr") d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) { assume((!bundle.d.ready) || bundle.c.ready, "ready check") } if (edge.manager.minLatency > 0) { when (c_set_wo_ready.orR) { assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra) } } inflight := (inflight | c_set) & ~d_clr inflight_opcodes := (inflight_opcodes | c_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes | c_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.c.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.manager.endSinkId.W)) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val e_first = true.B val d_set = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) { d_set := UIntToOH(bundle.d.bits.sink) assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra) } val e_clr = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) { e_clr := UIntToOH(bundle.e.bits.sink) monAssert((d_set | inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra) } // edge.client.minLatency applies to BC, not DE inflight := (inflight | d_set) & ~e_clr } def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = { val sourceBits = log2Ceil(edge.client.endSourceId) val tooBig = 14 // >16kB worth of flight information gets to be too much if (sourceBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked") } else { if (args.edge.params(TestplanTestType).simulation) { if (args.edge.params(TLMonitorStrictMode)) { legalizeADSource(bundle, edge) legalizeCDSource(bundle, edge) } else { legalizeADSourceOld(bundle, edge) } } if (args.edge.params(TestplanTestType).formal) { legalizeADSourceFormal(bundle, edge) } } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { // legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize... val sinkBits = log2Ceil(edge.manager.endSinkId) if (sinkBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked") } else { legalizeDESink(bundle, edge) } } } def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = { legalizeFormat (bundle, edge) legalizeMultibeat (bundle, edge) legalizeUnique (bundle, edge) } } File Misc.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import scala.math._ class ParameterizedBundle(implicit p: Parameters) extends Bundle trait Clocked extends Bundle { val clock = Clock() val reset = Bool() } object DecoupledHelper { def apply(rvs: Bool*) = new DecoupledHelper(rvs) } class DecoupledHelper(val rvs: Seq[Bool]) { def fire(exclude: Bool, includes: Bool*) = { require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!") (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _) } def fire() = { rvs.reduce(_ && _) } } object MuxT { def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2)) def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3)) def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4)) } /** Creates a cascade of n MuxTs to search for a key value. */ object MuxTLookup { def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } } object ValidMux { def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]*): ValidIO[T] = { apply(v1 +: v2.toSeq) } def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = { val out = Wire(Valid(valids.head.bits.cloneType)) out.valid := valids.map(_.valid).reduce(_ || _) out.bits := MuxCase(valids.head.bits, valids.map(v => (v.valid -> v.bits))) out } } object Str { def apply(s: String): UInt = { var i = BigInt(0) require(s.forall(validChar _)) for (c <- s) i = (i << 8) | c i.U((s.length*8).W) } def apply(x: Char): UInt = { require(validChar(x)) x.U(8.W) } def apply(x: UInt): UInt = apply(x, 10) def apply(x: UInt, radix: Int): UInt = { val rad = radix.U val w = x.getWidth require(w > 0) var q = x var s = digit(q % rad) for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s) } s } def apply(x: SInt): UInt = apply(x, 10) def apply(x: SInt, radix: Int): UInt = { val neg = x < 0.S val abs = x.abs.asUInt if (radix != 10) { Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix)) } else { val rad = radix.U val w = abs.getWidth require(w > 0) var q = abs var s = digit(q % rad) var needSign = neg for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad val placeSpace = q === 0.U val space = Mux(needSign, Str('-'), Str(' ')) needSign = needSign && !placeSpace s = Cat(Mux(placeSpace, space, digit(q % rad)), s) } Cat(Mux(needSign, Str('-'), Str(' ')), s) } } private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0) private def validChar(x: Char) = x == (x & 0xFF) } object Split { def apply(x: UInt, n0: Int) = { val w = x.getWidth (x.extract(w-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n2: Int, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } } object Random { def apply(mod: Int, random: UInt): UInt = { if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0) else PriorityEncoder(partition(apply(1 << log2Up(mod*8), random), mod)) } def apply(mod: Int): UInt = apply(mod, randomizer) def oneHot(mod: Int, random: UInt): UInt = { if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0)) else PriorityEncoderOH(partition(apply(1 << log2Up(mod*8), random), mod)).asUInt } def oneHot(mod: Int): UInt = oneHot(mod, randomizer) private def randomizer = LFSR(16) private def partition(value: UInt, slices: Int) = Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U) } object Majority { def apply(in: Set[Bool]): Bool = { val n = (in.size >> 1) + 1 val clauses = in.subsets(n).map(_.reduce(_ && _)) clauses.reduce(_ || _) } def apply(in: Seq[Bool]): Bool = apply(in.toSet) def apply(in: UInt): Bool = apply(in.asBools.toSet) } object PopCountAtLeast { private def two(x: UInt): (Bool, Bool) = x.getWidth match { case 1 => (x.asBool, false.B) case n => val half = x.getWidth / 2 val (leftOne, leftTwo) = two(x(half - 1, 0)) val (rightOne, rightTwo) = two(x(x.getWidth - 1, half)) (leftOne || rightOne, leftTwo || rightTwo || (leftOne && rightOne)) } def apply(x: UInt, n: Int): Bool = n match { case 0 => true.B case 1 => x.orR case 2 => two(x)._2 case 3 => PopCount(x) >= n.U } } // This gets used everywhere, so make the smallest circuit possible ... // Given an address and size, create a mask of beatBytes size // eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111 // groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01 object MaskGen { def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = { require (groupBy >= 1 && beatBytes >= groupBy) require (isPow2(beatBytes) && isPow2(groupBy)) val lgBytes = log2Ceil(beatBytes) val sizeOH = UIntToOH(lgSize | 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) | (groupBy*2 - 1).U def helper(i: Int): Seq[(Bool, Bool)] = { if (i == 0) { Seq((lgSize >= lgBytes.asUInt, true.B)) } else { val sub = helper(i-1) val size = sizeOH(lgBytes - i) val bit = addr_lo(lgBytes - i) val nbit = !bit Seq.tabulate (1 << i) { j => val (sub_acc, sub_eq) = sub(j/2) val eq = sub_eq && (if (j % 2 == 1) bit else nbit) val acc = sub_acc || (size && eq) (acc, eq) } } } if (groupBy == beatBytes) 1.U else Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse) } } File PlusArg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.experimental._ import chisel3.util.HasBlackBoxResource @deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05") case class PlusArgInfo(default: BigInt, docstring: String) /** Case class for PlusArg information * * @tparam A scala type of the PlusArg value * @param default optional default value * @param docstring text to include in the help * @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT) */ private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String) /** Typeclass for converting a type to a doctype string * @tparam A some type */ trait Doctypeable[A] { /** Return the doctype string for some option */ def toDoctype(a: Option[A]): String } /** Object containing implementations of the Doctypeable typeclass */ object Doctypes { /** Converts an Int => "INT" */ implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" } /** Converts a BigInt => "INT" */ implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" } /** Converts a String => "STRING" */ implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" } } class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map( "FORMAT" -> StringParam(format), "DEFAULT" -> IntParam(default), "WIDTH" -> IntParam(width) )) with HasBlackBoxResource { val io = IO(new Bundle { val out = Output(UInt(width.W)) }) addResource("/vsrc/plusarg_reader.v") } /* This wrapper class has no outputs, making it clear it is a simulation-only construct */ class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module { val io = IO(new Bundle { val count = Input(UInt(width.W)) }) val max = Module(new plusarg_reader(format, default, docstring, width)).io.out when (max > 0.U) { assert (io.count < max, s"Timeout exceeded: $docstring") } } import Doctypes._ object PlusArg { /** PlusArg("foo") will return 42.U if the simulation is run with +foo=42 * Do not use this as an initial register value. The value is set in an * initial block and thus accessing it from another initial is racey. * Add a docstring to document the arg, which can be dumped in an elaboration * pass. */ def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out } /** PlusArg.timeout(name, default, docstring)(count) will use chisel.assert * to kill the simulation when count exceeds the specified integer argument. * Default 0 will never assert. */ def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count } } object PlusArgArtefacts { private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty /* Add a new PlusArg */ @deprecated( "Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05" ) def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring) /** Add a new PlusArg * * @tparam A scala type of the PlusArg value * @param name name for the PlusArg * @param default optional default value * @param docstring text to include in the help */ def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit = artefacts = artefacts ++ Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default))) /* From plus args, generate help text */ private def serializeHelp_cHeader(tab: String = ""): String = artefacts .map{ case(arg, info) => s"""|$tab+$arg=${info.doctype}\\n\\ |$tab${" "*20}${info.docstring}\\n\\ |""".stripMargin ++ info.default.map{ case default => s"$tab${" "*22}(default=${default})\\n\\\n"}.getOrElse("") }.toSeq.mkString("\\n\\\n") ++ "\"" /* From plus args, generate a char array of their names */ private def serializeArray_cHeader(tab: String = ""): String = { val prettyTab = tab + " " * 44 // Length of 'static const ...' s"${tab}static const char * verilog_plusargs [] = {\\\n" ++ artefacts .map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" } .mkString("")++ s"${prettyTab}0};" } /* Generate C code to be included in emulator.cc that helps with * argument parsing based on available Verilog PlusArgs */ def serialize_cHeader(): String = s"""|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\ |${serializeHelp_cHeader(" "*7)} |${serializeArray_cHeader()} |""".stripMargin } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /** Like Vec.apply(idx), but tolerates indices of mismatched width */ def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /** Any Data subtype that has a Bool member named valid. */ type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /** converts from camel case to to underscores, also removing all spaces */ def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /** converts spaces or underscores to hyphens, also lowering case */ def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y | (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y || y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /** Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation */ def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Bundles.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import freechips.rocketchip.util._ import scala.collection.immutable.ListMap import chisel3.util.Decoupled import chisel3.util.DecoupledIO import chisel3.reflect.DataMirror abstract class TLBundleBase(val params: TLBundleParameters) extends Bundle // common combos in lazy policy: // Put + Acquire // Release + AccessAck object TLMessages { // A B C D E def PutFullData = 0.U // . . => AccessAck def PutPartialData = 1.U // . . => AccessAck def ArithmeticData = 2.U // . . => AccessAckData def LogicalData = 3.U // . . => AccessAckData def Get = 4.U // . . => AccessAckData def Hint = 5.U // . . => HintAck def AcquireBlock = 6.U // . => Grant[Data] def AcquirePerm = 7.U // . => Grant[Data] def Probe = 6.U // . => ProbeAck[Data] def AccessAck = 0.U // . . def AccessAckData = 1.U // . . def HintAck = 2.U // . . def ProbeAck = 4.U // . def ProbeAckData = 5.U // . def Release = 6.U // . => ReleaseAck def ReleaseData = 7.U // . => ReleaseAck def Grant = 4.U // . => GrantAck def GrantData = 5.U // . => GrantAck def ReleaseAck = 6.U // . def GrantAck = 0.U // . def isA(x: UInt) = x <= AcquirePerm def isB(x: UInt) = x <= Probe def isC(x: UInt) = x <= ReleaseData def isD(x: UInt) = x <= ReleaseAck def adResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, Grant, Grant) def bcResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, ProbeAck, ProbeAck) def a = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("AcquireBlock",TLPermissions.PermMsgGrow), ("AcquirePerm",TLPermissions.PermMsgGrow)) def b = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("Probe",TLPermissions.PermMsgCap)) def c = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("ProbeAck",TLPermissions.PermMsgReport), ("ProbeAckData",TLPermissions.PermMsgReport), ("Release",TLPermissions.PermMsgReport), ("ReleaseData",TLPermissions.PermMsgReport)) def d = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("Grant",TLPermissions.PermMsgCap), ("GrantData",TLPermissions.PermMsgCap), ("ReleaseAck",TLPermissions.PermMsgReserved)) } /** * The three primary TileLink permissions are: * (T)runk: the agent is (or is on inwards path to) the global point of serialization. * (B)ranch: the agent is on an outwards path to * (N)one: * These permissions are permuted by transfer operations in various ways. * Operations can cap permissions, request for them to be grown or shrunk, * or for a report on their current status. */ object TLPermissions { val aWidth = 2 val bdWidth = 2 val cWidth = 3 // Cap types (Grant = new permissions, Probe = permisions <= target) def toT = 0.U(bdWidth.W) def toB = 1.U(bdWidth.W) def toN = 2.U(bdWidth.W) def isCap(x: UInt) = x <= toN // Grow types (Acquire = permissions >= target) def NtoB = 0.U(aWidth.W) def NtoT = 1.U(aWidth.W) def BtoT = 2.U(aWidth.W) def isGrow(x: UInt) = x <= BtoT // Shrink types (ProbeAck, Release) def TtoB = 0.U(cWidth.W) def TtoN = 1.U(cWidth.W) def BtoN = 2.U(cWidth.W) def isShrink(x: UInt) = x <= BtoN // Report types (ProbeAck, Release) def TtoT = 3.U(cWidth.W) def BtoB = 4.U(cWidth.W) def NtoN = 5.U(cWidth.W) def isReport(x: UInt) = x <= NtoN def PermMsgGrow:Seq[String] = Seq("Grow NtoB", "Grow NtoT", "Grow BtoT") def PermMsgCap:Seq[String] = Seq("Cap toT", "Cap toB", "Cap toN") def PermMsgReport:Seq[String] = Seq("Shrink TtoB", "Shrink TtoN", "Shrink BtoN", "Report TotT", "Report BtoB", "Report NtoN") def PermMsgReserved:Seq[String] = Seq("Reserved") } object TLAtomics { val width = 3 // Arithmetic types def MIN = 0.U(width.W) def MAX = 1.U(width.W) def MINU = 2.U(width.W) def MAXU = 3.U(width.W) def ADD = 4.U(width.W) def isArithmetic(x: UInt) = x <= ADD // Logical types def XOR = 0.U(width.W) def OR = 1.U(width.W) def AND = 2.U(width.W) def SWAP = 3.U(width.W) def isLogical(x: UInt) = x <= SWAP def ArithMsg:Seq[String] = Seq("MIN", "MAX", "MINU", "MAXU", "ADD") def LogicMsg:Seq[String] = Seq("XOR", "OR", "AND", "SWAP") } object TLHints { val width = 1 def PREFETCH_READ = 0.U(width.W) def PREFETCH_WRITE = 1.U(width.W) def isHints(x: UInt) = x <= PREFETCH_WRITE def HintsMsg:Seq[String] = Seq("PrefetchRead", "PrefetchWrite") } sealed trait TLChannel extends TLBundleBase { val channelName: String } sealed trait TLDataChannel extends TLChannel sealed trait TLAddrChannel extends TLDataChannel final class TLBundleA(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleA_${params.shortName}" val channelName = "'A' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(List(TLAtomics.width, TLPermissions.aWidth, TLHints.width).max.W) // amo_opcode || grow perms || hint val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleB(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleB_${params.shortName}" val channelName = "'B' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val address = UInt(params.addressBits.W) // from // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleC(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleC_${params.shortName}" val channelName = "'C' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.cWidth.W) // shrink or report perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleD(params: TLBundleParameters) extends TLBundleBase(params) with TLDataChannel { override def typeName = s"TLBundleD_${params.shortName}" val channelName = "'D' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val sink = UInt(params.sinkBits.W) // from val denied = Bool() // implies corrupt iff *Data val user = BundleMap(params.responseFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleE(params: TLBundleParameters) extends TLBundleBase(params) with TLChannel { override def typeName = s"TLBundleE_${params.shortName}" val channelName = "'E' channel" val sink = UInt(params.sinkBits.W) // to } class TLBundle(val params: TLBundleParameters) extends Record { // Emulate a Bundle with elements abcde or ad depending on params.hasBCE private val optA = Some (Decoupled(new TLBundleA(params))) private val optB = params.hasBCE.option(Flipped(Decoupled(new TLBundleB(params)))) private val optC = params.hasBCE.option(Decoupled(new TLBundleC(params))) private val optD = Some (Flipped(Decoupled(new TLBundleD(params)))) private val optE = params.hasBCE.option(Decoupled(new TLBundleE(params))) def a: DecoupledIO[TLBundleA] = optA.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleA(params))))) def b: DecoupledIO[TLBundleB] = optB.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleB(params))))) def c: DecoupledIO[TLBundleC] = optC.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleC(params))))) def d: DecoupledIO[TLBundleD] = optD.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleD(params))))) def e: DecoupledIO[TLBundleE] = optE.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleE(params))))) val elements = if (params.hasBCE) ListMap("e" -> e, "d" -> d, "c" -> c, "b" -> b, "a" -> a) else ListMap("d" -> d, "a" -> a) def tieoff(): Unit = { DataMirror.specifiedDirectionOf(a.ready) match { case SpecifiedDirection.Input => a.ready := false.B c.ready := false.B e.ready := false.B b.valid := false.B d.valid := false.B case SpecifiedDirection.Output => a.valid := false.B c.valid := false.B e.valid := false.B b.ready := false.B d.ready := false.B case _ => } } } object TLBundle { def apply(params: TLBundleParameters) = new TLBundle(params) } class TLAsyncBundleBase(val params: TLAsyncBundleParameters) extends Bundle class TLAsyncBundle(params: TLAsyncBundleParameters) extends TLAsyncBundleBase(params) { val a = new AsyncBundle(new TLBundleA(params.base), params.async) val b = Flipped(new AsyncBundle(new TLBundleB(params.base), params.async)) val c = new AsyncBundle(new TLBundleC(params.base), params.async) val d = Flipped(new AsyncBundle(new TLBundleD(params.base), params.async)) val e = new AsyncBundle(new TLBundleE(params.base), params.async) } class TLRationalBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = RationalIO(new TLBundleA(params)) val b = Flipped(RationalIO(new TLBundleB(params))) val c = RationalIO(new TLBundleC(params)) val d = Flipped(RationalIO(new TLBundleD(params))) val e = RationalIO(new TLBundleE(params)) } class TLCreditedBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = CreditedIO(new TLBundleA(params)) val b = Flipped(CreditedIO(new TLBundleB(params))) val c = CreditedIO(new TLBundleC(params)) val d = Flipped(CreditedIO(new TLBundleD(params))) val e = CreditedIO(new TLBundleE(params)) } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.nodes._ import freechips.rocketchip.diplomacy.{ AddressDecoder, AddressSet, BufferParams, DirectedBuffers, IdMap, IdMapEntry, IdRange, RegionType, TransferSizes } import freechips.rocketchip.resources.{Resource, ResourceAddress, ResourcePermissions} import freechips.rocketchip.util.{ AsyncQueueParams, BundleField, BundleFieldBase, BundleKeyBase, CreditedDelay, groupByIntoSeq, RationalDirection, SimpleProduct } import scala.math.max //These transfer sizes describe requests issued from masters on the A channel that will be responded by slaves on the D channel case class TLMasterToSlaveTransferSizes( // Supports both Acquire+Release of the following two sizes: acquireT: TransferSizes = TransferSizes.none, acquireB: TransferSizes = TransferSizes.none, arithmetic: TransferSizes = TransferSizes.none, logical: TransferSizes = TransferSizes.none, get: TransferSizes = TransferSizes.none, putFull: TransferSizes = TransferSizes.none, putPartial: TransferSizes = TransferSizes.none, hint: TransferSizes = TransferSizes.none) extends TLCommonTransferSizes { def intersect(rhs: TLMasterToSlaveTransferSizes) = TLMasterToSlaveTransferSizes( acquireT = acquireT .intersect(rhs.acquireT), acquireB = acquireB .intersect(rhs.acquireB), arithmetic = arithmetic.intersect(rhs.arithmetic), logical = logical .intersect(rhs.logical), get = get .intersect(rhs.get), putFull = putFull .intersect(rhs.putFull), putPartial = putPartial.intersect(rhs.putPartial), hint = hint .intersect(rhs.hint)) def mincover(rhs: TLMasterToSlaveTransferSizes) = TLMasterToSlaveTransferSizes( acquireT = acquireT .mincover(rhs.acquireT), acquireB = acquireB .mincover(rhs.acquireB), arithmetic = arithmetic.mincover(rhs.arithmetic), logical = logical .mincover(rhs.logical), get = get .mincover(rhs.get), putFull = putFull .mincover(rhs.putFull), putPartial = putPartial.mincover(rhs.putPartial), hint = hint .mincover(rhs.hint)) // Reduce rendering to a simple yes/no per field override def toString = { def str(x: TransferSizes, flag: String) = if (x.none) "" else flag def flags = Vector( str(acquireT, "T"), str(acquireB, "B"), str(arithmetic, "A"), str(logical, "L"), str(get, "G"), str(putFull, "F"), str(putPartial, "P"), str(hint, "H")) flags.mkString } // Prints out the actual information in a user readable way def infoString = { s"""acquireT = ${acquireT} |acquireB = ${acquireB} |arithmetic = ${arithmetic} |logical = ${logical} |get = ${get} |putFull = ${putFull} |putPartial = ${putPartial} |hint = ${hint} | |""".stripMargin } } object TLMasterToSlaveTransferSizes { def unknownEmits = TLMasterToSlaveTransferSizes( acquireT = TransferSizes(1, 4096), acquireB = TransferSizes(1, 4096), arithmetic = TransferSizes(1, 4096), logical = TransferSizes(1, 4096), get = TransferSizes(1, 4096), putFull = TransferSizes(1, 4096), putPartial = TransferSizes(1, 4096), hint = TransferSizes(1, 4096)) def unknownSupports = TLMasterToSlaveTransferSizes() } //These transfer sizes describe requests issued from slaves on the B channel that will be responded by masters on the C channel case class TLSlaveToMasterTransferSizes( probe: TransferSizes = TransferSizes.none, arithmetic: TransferSizes = TransferSizes.none, logical: TransferSizes = TransferSizes.none, get: TransferSizes = TransferSizes.none, putFull: TransferSizes = TransferSizes.none, putPartial: TransferSizes = TransferSizes.none, hint: TransferSizes = TransferSizes.none ) extends TLCommonTransferSizes { def intersect(rhs: TLSlaveToMasterTransferSizes) = TLSlaveToMasterTransferSizes( probe = probe .intersect(rhs.probe), arithmetic = arithmetic.intersect(rhs.arithmetic), logical = logical .intersect(rhs.logical), get = get .intersect(rhs.get), putFull = putFull .intersect(rhs.putFull), putPartial = putPartial.intersect(rhs.putPartial), hint = hint .intersect(rhs.hint) ) def mincover(rhs: TLSlaveToMasterTransferSizes) = TLSlaveToMasterTransferSizes( probe = probe .mincover(rhs.probe), arithmetic = arithmetic.mincover(rhs.arithmetic), logical = logical .mincover(rhs.logical), get = get .mincover(rhs.get), putFull = putFull .mincover(rhs.putFull), putPartial = putPartial.mincover(rhs.putPartial), hint = hint .mincover(rhs.hint) ) // Reduce rendering to a simple yes/no per field override def toString = { def str(x: TransferSizes, flag: String) = if (x.none) "" else flag def flags = Vector( str(probe, "P"), str(arithmetic, "A"), str(logical, "L"), str(get, "G"), str(putFull, "F"), str(putPartial, "P"), str(hint, "H")) flags.mkString } // Prints out the actual information in a user readable way def infoString = { s"""probe = ${probe} |arithmetic = ${arithmetic} |logical = ${logical} |get = ${get} |putFull = ${putFull} |putPartial = ${putPartial} |hint = ${hint} | |""".stripMargin } } object TLSlaveToMasterTransferSizes { def unknownEmits = TLSlaveToMasterTransferSizes( arithmetic = TransferSizes(1, 4096), logical = TransferSizes(1, 4096), get = TransferSizes(1, 4096), putFull = TransferSizes(1, 4096), putPartial = TransferSizes(1, 4096), hint = TransferSizes(1, 4096), probe = TransferSizes(1, 4096)) def unknownSupports = TLSlaveToMasterTransferSizes() } trait TLCommonTransferSizes { def arithmetic: TransferSizes def logical: TransferSizes def get: TransferSizes def putFull: TransferSizes def putPartial: TransferSizes def hint: TransferSizes } class TLSlaveParameters private( val nodePath: Seq[BaseNode], val resources: Seq[Resource], setName: Option[String], val address: Seq[AddressSet], val regionType: RegionType.T, val executable: Boolean, val fifoId: Option[Int], val supports: TLMasterToSlaveTransferSizes, val emits: TLSlaveToMasterTransferSizes, // By default, slaves are forbidden from issuing 'denied' responses (it prevents Fragmentation) val alwaysGrantsT: Boolean, // typically only true for CacheCork'd read-write devices; dual: neverReleaseData // If fifoId=Some, all accesses sent to the same fifoId are executed and ACK'd in FIFO order // Note: you can only rely on this FIFO behaviour if your TLMasterParameters include requestFifo val mayDenyGet: Boolean, // applies to: AccessAckData, GrantData val mayDenyPut: Boolean) // applies to: AccessAck, Grant, HintAck // ReleaseAck may NEVER be denied extends SimpleProduct { def sortedAddress = address.sorted override def canEqual(that: Any): Boolean = that.isInstanceOf[TLSlaveParameters] override def productPrefix = "TLSlaveParameters" // We intentionally omit nodePath for equality testing / formatting def productArity: Int = 11 def productElement(n: Int): Any = n match { case 0 => name case 1 => address case 2 => resources case 3 => regionType case 4 => executable case 5 => fifoId case 6 => supports case 7 => emits case 8 => alwaysGrantsT case 9 => mayDenyGet case 10 => mayDenyPut case _ => throw new IndexOutOfBoundsException(n.toString) } def supportsAcquireT: TransferSizes = supports.acquireT def supportsAcquireB: TransferSizes = supports.acquireB def supportsArithmetic: TransferSizes = supports.arithmetic def supportsLogical: TransferSizes = supports.logical def supportsGet: TransferSizes = supports.get def supportsPutFull: TransferSizes = supports.putFull def supportsPutPartial: TransferSizes = supports.putPartial def supportsHint: TransferSizes = supports.hint require (!address.isEmpty, "Address cannot be empty") address.foreach { a => require (a.finite, "Address must be finite") } address.combinations(2).foreach { case Seq(x,y) => require (!x.overlaps(y), s"$x and $y overlap.") } require (supportsPutFull.contains(supportsPutPartial), s"PutFull($supportsPutFull) < PutPartial($supportsPutPartial)") require (supportsPutFull.contains(supportsArithmetic), s"PutFull($supportsPutFull) < Arithmetic($supportsArithmetic)") require (supportsPutFull.contains(supportsLogical), s"PutFull($supportsPutFull) < Logical($supportsLogical)") require (supportsGet.contains(supportsArithmetic), s"Get($supportsGet) < Arithmetic($supportsArithmetic)") require (supportsGet.contains(supportsLogical), s"Get($supportsGet) < Logical($supportsLogical)") require (supportsAcquireB.contains(supportsAcquireT), s"AcquireB($supportsAcquireB) < AcquireT($supportsAcquireT)") require (!alwaysGrantsT || supportsAcquireT, s"Must supportAcquireT if promising to always grantT") // Make sure that the regionType agrees with the capabilities require (!supportsAcquireB || regionType >= RegionType.UNCACHED) // acquire -> uncached, tracked, cached require (regionType <= RegionType.UNCACHED || supportsAcquireB) // tracked, cached -> acquire require (regionType != RegionType.UNCACHED || supportsGet) // uncached -> supportsGet val name = setName.orElse(nodePath.lastOption.map(_.lazyModule.name)).getOrElse("disconnected") val maxTransfer = List( // Largest supported transfer of all types supportsAcquireT.max, supportsAcquireB.max, supportsArithmetic.max, supportsLogical.max, supportsGet.max, supportsPutFull.max, supportsPutPartial.max).max val maxAddress = address.map(_.max).max val minAlignment = address.map(_.alignment).min // The device had better not support a transfer larger than its alignment require (minAlignment >= maxTransfer, s"Bad $address: minAlignment ($minAlignment) must be >= maxTransfer ($maxTransfer)") def toResource: ResourceAddress = { ResourceAddress(address, ResourcePermissions( r = supportsAcquireB || supportsGet, w = supportsAcquireT || supportsPutFull, x = executable, c = supportsAcquireB, a = supportsArithmetic && supportsLogical)) } def findTreeViolation() = nodePath.find { case _: MixedAdapterNode[_, _, _, _, _, _, _, _] => false case _: SinkNode[_, _, _, _, _] => false case node => node.inputs.size != 1 } def isTree = findTreeViolation() == None def infoString = { s"""Slave Name = ${name} |Slave Address = ${address} |supports = ${supports.infoString} | |""".stripMargin } def v1copy( address: Seq[AddressSet] = address, resources: Seq[Resource] = resources, regionType: RegionType.T = regionType, executable: Boolean = executable, nodePath: Seq[BaseNode] = nodePath, supportsAcquireT: TransferSizes = supports.acquireT, supportsAcquireB: TransferSizes = supports.acquireB, supportsArithmetic: TransferSizes = supports.arithmetic, supportsLogical: TransferSizes = supports.logical, supportsGet: TransferSizes = supports.get, supportsPutFull: TransferSizes = supports.putFull, supportsPutPartial: TransferSizes = supports.putPartial, supportsHint: TransferSizes = supports.hint, mayDenyGet: Boolean = mayDenyGet, mayDenyPut: Boolean = mayDenyPut, alwaysGrantsT: Boolean = alwaysGrantsT, fifoId: Option[Int] = fifoId) = { new TLSlaveParameters( setName = setName, address = address, resources = resources, regionType = regionType, executable = executable, nodePath = nodePath, supports = TLMasterToSlaveTransferSizes( acquireT = supportsAcquireT, acquireB = supportsAcquireB, arithmetic = supportsArithmetic, logical = supportsLogical, get = supportsGet, putFull = supportsPutFull, putPartial = supportsPutPartial, hint = supportsHint), emits = emits, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut, alwaysGrantsT = alwaysGrantsT, fifoId = fifoId) } def v2copy( nodePath: Seq[BaseNode] = nodePath, resources: Seq[Resource] = resources, name: Option[String] = setName, address: Seq[AddressSet] = address, regionType: RegionType.T = regionType, executable: Boolean = executable, fifoId: Option[Int] = fifoId, supports: TLMasterToSlaveTransferSizes = supports, emits: TLSlaveToMasterTransferSizes = emits, alwaysGrantsT: Boolean = alwaysGrantsT, mayDenyGet: Boolean = mayDenyGet, mayDenyPut: Boolean = mayDenyPut) = { new TLSlaveParameters( nodePath = nodePath, resources = resources, setName = name, address = address, regionType = regionType, executable = executable, fifoId = fifoId, supports = supports, emits = emits, alwaysGrantsT = alwaysGrantsT, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut) } @deprecated("Use v1copy instead of copy","") def copy( address: Seq[AddressSet] = address, resources: Seq[Resource] = resources, regionType: RegionType.T = regionType, executable: Boolean = executable, nodePath: Seq[BaseNode] = nodePath, supportsAcquireT: TransferSizes = supports.acquireT, supportsAcquireB: TransferSizes = supports.acquireB, supportsArithmetic: TransferSizes = supports.arithmetic, supportsLogical: TransferSizes = supports.logical, supportsGet: TransferSizes = supports.get, supportsPutFull: TransferSizes = supports.putFull, supportsPutPartial: TransferSizes = supports.putPartial, supportsHint: TransferSizes = supports.hint, mayDenyGet: Boolean = mayDenyGet, mayDenyPut: Boolean = mayDenyPut, alwaysGrantsT: Boolean = alwaysGrantsT, fifoId: Option[Int] = fifoId) = { v1copy( address = address, resources = resources, regionType = regionType, executable = executable, nodePath = nodePath, supportsAcquireT = supportsAcquireT, supportsAcquireB = supportsAcquireB, supportsArithmetic = supportsArithmetic, supportsLogical = supportsLogical, supportsGet = supportsGet, supportsPutFull = supportsPutFull, supportsPutPartial = supportsPutPartial, supportsHint = supportsHint, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut, alwaysGrantsT = alwaysGrantsT, fifoId = fifoId) } } object TLSlaveParameters { def v1( address: Seq[AddressSet], resources: Seq[Resource] = Seq(), regionType: RegionType.T = RegionType.GET_EFFECTS, executable: Boolean = false, nodePath: Seq[BaseNode] = Seq(), supportsAcquireT: TransferSizes = TransferSizes.none, supportsAcquireB: TransferSizes = TransferSizes.none, supportsArithmetic: TransferSizes = TransferSizes.none, supportsLogical: TransferSizes = TransferSizes.none, supportsGet: TransferSizes = TransferSizes.none, supportsPutFull: TransferSizes = TransferSizes.none, supportsPutPartial: TransferSizes = TransferSizes.none, supportsHint: TransferSizes = TransferSizes.none, mayDenyGet: Boolean = false, mayDenyPut: Boolean = false, alwaysGrantsT: Boolean = false, fifoId: Option[Int] = None) = { new TLSlaveParameters( setName = None, address = address, resources = resources, regionType = regionType, executable = executable, nodePath = nodePath, supports = TLMasterToSlaveTransferSizes( acquireT = supportsAcquireT, acquireB = supportsAcquireB, arithmetic = supportsArithmetic, logical = supportsLogical, get = supportsGet, putFull = supportsPutFull, putPartial = supportsPutPartial, hint = supportsHint), emits = TLSlaveToMasterTransferSizes.unknownEmits, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut, alwaysGrantsT = alwaysGrantsT, fifoId = fifoId) } def v2( address: Seq[AddressSet], nodePath: Seq[BaseNode] = Seq(), resources: Seq[Resource] = Seq(), name: Option[String] = None, regionType: RegionType.T = RegionType.GET_EFFECTS, executable: Boolean = false, fifoId: Option[Int] = None, supports: TLMasterToSlaveTransferSizes = TLMasterToSlaveTransferSizes.unknownSupports, emits: TLSlaveToMasterTransferSizes = TLSlaveToMasterTransferSizes.unknownEmits, alwaysGrantsT: Boolean = false, mayDenyGet: Boolean = false, mayDenyPut: Boolean = false) = { new TLSlaveParameters( nodePath = nodePath, resources = resources, setName = name, address = address, regionType = regionType, executable = executable, fifoId = fifoId, supports = supports, emits = emits, alwaysGrantsT = alwaysGrantsT, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut) } } object TLManagerParameters { @deprecated("Use TLSlaveParameters.v1 instead of TLManagerParameters","") def apply( address: Seq[AddressSet], resources: Seq[Resource] = Seq(), regionType: RegionType.T = RegionType.GET_EFFECTS, executable: Boolean = false, nodePath: Seq[BaseNode] = Seq(), supportsAcquireT: TransferSizes = TransferSizes.none, supportsAcquireB: TransferSizes = TransferSizes.none, supportsArithmetic: TransferSizes = TransferSizes.none, supportsLogical: TransferSizes = TransferSizes.none, supportsGet: TransferSizes = TransferSizes.none, supportsPutFull: TransferSizes = TransferSizes.none, supportsPutPartial: TransferSizes = TransferSizes.none, supportsHint: TransferSizes = TransferSizes.none, mayDenyGet: Boolean = false, mayDenyPut: Boolean = false, alwaysGrantsT: Boolean = false, fifoId: Option[Int] = None) = TLSlaveParameters.v1( address, resources, regionType, executable, nodePath, supportsAcquireT, supportsAcquireB, supportsArithmetic, supportsLogical, supportsGet, supportsPutFull, supportsPutPartial, supportsHint, mayDenyGet, mayDenyPut, alwaysGrantsT, fifoId, ) } case class TLChannelBeatBytes(a: Option[Int], b: Option[Int], c: Option[Int], d: Option[Int]) { def members = Seq(a, b, c, d) members.collect { case Some(beatBytes) => require (isPow2(beatBytes), "Data channel width must be a power of 2") } } object TLChannelBeatBytes{ def apply(beatBytes: Int): TLChannelBeatBytes = TLChannelBeatBytes( Some(beatBytes), Some(beatBytes), Some(beatBytes), Some(beatBytes)) def apply(): TLChannelBeatBytes = TLChannelBeatBytes( None, None, None, None) } class TLSlavePortParameters private( val slaves: Seq[TLSlaveParameters], val channelBytes: TLChannelBeatBytes, val endSinkId: Int, val minLatency: Int, val responseFields: Seq[BundleFieldBase], val requestKeys: Seq[BundleKeyBase]) extends SimpleProduct { def sortedSlaves = slaves.sortBy(_.sortedAddress.head) override def canEqual(that: Any): Boolean = that.isInstanceOf[TLSlavePortParameters] override def productPrefix = "TLSlavePortParameters" def productArity: Int = 6 def productElement(n: Int): Any = n match { case 0 => slaves case 1 => channelBytes case 2 => endSinkId case 3 => minLatency case 4 => responseFields case 5 => requestKeys case _ => throw new IndexOutOfBoundsException(n.toString) } require (!slaves.isEmpty, "Slave ports must have slaves") require (endSinkId >= 0, "Sink ids cannot be negative") require (minLatency >= 0, "Minimum required latency cannot be negative") // Using this API implies you cannot handle mixed-width busses def beatBytes = { channelBytes.members.foreach { width => require (width.isDefined && width == channelBytes.a) } channelBytes.a.get } // TODO this should be deprecated def managers = slaves def requireFifo(policy: TLFIFOFixer.Policy = TLFIFOFixer.allFIFO) = { val relevant = slaves.filter(m => policy(m)) relevant.foreach { m => require(m.fifoId == relevant.head.fifoId, s"${m.name} had fifoId ${m.fifoId}, which was not homogeneous (${slaves.map(s => (s.name, s.fifoId))}) ") } } // Bounds on required sizes def maxAddress = slaves.map(_.maxAddress).max def maxTransfer = slaves.map(_.maxTransfer).max def mayDenyGet = slaves.exists(_.mayDenyGet) def mayDenyPut = slaves.exists(_.mayDenyPut) // Diplomatically determined operation sizes emitted by all outward Slaves // as opposed to emits* which generate circuitry to check which specific addresses val allEmitClaims = slaves.map(_.emits).reduce( _ intersect _) // Operation Emitted by at least one outward Slaves // as opposed to emits* which generate circuitry to check which specific addresses val anyEmitClaims = slaves.map(_.emits).reduce(_ mincover _) // Diplomatically determined operation sizes supported by all outward Slaves // as opposed to supports* which generate circuitry to check which specific addresses val allSupportClaims = slaves.map(_.supports).reduce( _ intersect _) val allSupportAcquireT = allSupportClaims.acquireT val allSupportAcquireB = allSupportClaims.acquireB val allSupportArithmetic = allSupportClaims.arithmetic val allSupportLogical = allSupportClaims.logical val allSupportGet = allSupportClaims.get val allSupportPutFull = allSupportClaims.putFull val allSupportPutPartial = allSupportClaims.putPartial val allSupportHint = allSupportClaims.hint // Operation supported by at least one outward Slaves // as opposed to supports* which generate circuitry to check which specific addresses val anySupportClaims = slaves.map(_.supports).reduce(_ mincover _) val anySupportAcquireT = !anySupportClaims.acquireT.none val anySupportAcquireB = !anySupportClaims.acquireB.none val anySupportArithmetic = !anySupportClaims.arithmetic.none val anySupportLogical = !anySupportClaims.logical.none val anySupportGet = !anySupportClaims.get.none val anySupportPutFull = !anySupportClaims.putFull.none val anySupportPutPartial = !anySupportClaims.putPartial.none val anySupportHint = !anySupportClaims.hint.none // Supporting Acquire means being routable for GrantAck require ((endSinkId == 0) == !anySupportAcquireB) // These return Option[TLSlaveParameters] for your convenience def find(address: BigInt) = slaves.find(_.address.exists(_.contains(address))) // The safe version will check the entire address def findSafe(address: UInt) = VecInit(sortedSlaves.map(_.address.map(_.contains(address)).reduce(_ || _))) // The fast version assumes the address is valid (you probably want fastProperty instead of this function) def findFast(address: UInt) = { val routingMask = AddressDecoder(slaves.map(_.address)) VecInit(sortedSlaves.map(_.address.map(_.widen(~routingMask)).distinct.map(_.contains(address)).reduce(_ || _))) } // Compute the simplest AddressSets that decide a key def fastPropertyGroup[K](p: TLSlaveParameters => K): Seq[(K, Seq[AddressSet])] = { val groups = groupByIntoSeq(sortedSlaves.map(m => (p(m), m.address)))( _._1).map { case (k, vs) => k -> vs.flatMap(_._2) } val reductionMask = AddressDecoder(groups.map(_._2)) groups.map { case (k, seq) => k -> AddressSet.unify(seq.map(_.widen(~reductionMask)).distinct) } } // Select a property def fastProperty[K, D <: Data](address: UInt, p: TLSlaveParameters => K, d: K => D): D = Mux1H(fastPropertyGroup(p).map { case (v, a) => (a.map(_.contains(address)).reduce(_||_), d(v)) }) // Note: returns the actual fifoId + 1 or 0 if None def findFifoIdFast(address: UInt) = fastProperty(address, _.fifoId.map(_+1).getOrElse(0), (i:Int) => i.U) def hasFifoIdFast(address: UInt) = fastProperty(address, _.fifoId.isDefined, (b:Boolean) => b.B) // Does this Port manage this ID/address? def containsSafe(address: UInt) = findSafe(address).reduce(_ || _) private def addressHelper( // setting safe to false indicates that all addresses are expected to be legal, which might reduce circuit complexity safe: Boolean, // member filters out the sizes being checked based on the opcode being emitted or supported member: TLSlaveParameters => TransferSizes, address: UInt, lgSize: UInt, // range provides a limit on the sizes that are expected to be evaluated, which might reduce circuit complexity range: Option[TransferSizes]): Bool = { // trim reduces circuit complexity by intersecting checked sizes with the range argument def trim(x: TransferSizes) = range.map(_.intersect(x)).getOrElse(x) // groupBy returns an unordered map, convert back to Seq and sort the result for determinism // groupByIntoSeq is turning slaves into trimmed membership sizes // We are grouping all the slaves by their transfer size where // if they support the trimmed size then // member is the type of transfer that you are looking for (What you are trying to filter on) // When you consider membership, you are trimming the sizes to only the ones that you care about // you are filtering the slaves based on both whether they support a particular opcode and the size // Grouping the slaves based on the actual transfer size range they support // intersecting the range and checking their membership // FOR SUPPORTCASES instead of returning the list of slaves, // you are returning a map from transfer size to the set of // address sets that are supported for that transfer size // find all the slaves that support a certain type of operation and then group their addresses by the supported size // for every size there could be multiple address ranges // safety is a trade off between checking between all possible addresses vs only the addresses // that are known to have supported sizes // the trade off is 'checking all addresses is a more expensive circuit but will always give you // the right answer even if you give it an illegal address' // the not safe version is a cheaper circuit but if you give it an illegal address then it might produce the wrong answer // fast presumes address legality // This groupByIntoSeq deterministically groups all address sets for which a given `member` transfer size applies. // In the resulting Map of cases, the keys are transfer sizes and the values are all address sets which emit or support that size. val supportCases = groupByIntoSeq(slaves)(m => trim(member(m))).map { case (k: TransferSizes, vs: Seq[TLSlaveParameters]) => k -> vs.flatMap(_.address) } // safe produces a circuit that compares against all possible addresses, // whereas fast presumes that the address is legal but uses an efficient address decoder val mask = if (safe) ~BigInt(0) else AddressDecoder(supportCases.map(_._2)) // Simplified creates the most concise possible representation of each cases' address sets based on the mask. val simplified = supportCases.map { case (k, seq) => k -> AddressSet.unify(seq.map(_.widen(~mask)).distinct) } simplified.map { case (s, a) => // s is a size, you are checking for this size either the size of the operation is in s // We return an or-reduction of all the cases, checking whether any contains both the dynamic size and dynamic address on the wire. ((Some(s) == range).B || s.containsLg(lgSize)) && a.map(_.contains(address)).reduce(_||_) }.foldLeft(false.B)(_||_) } def supportsAcquireTSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.acquireT, address, lgSize, range) def supportsAcquireBSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.acquireB, address, lgSize, range) def supportsArithmeticSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.arithmetic, address, lgSize, range) def supportsLogicalSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.logical, address, lgSize, range) def supportsGetSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.get, address, lgSize, range) def supportsPutFullSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.putFull, address, lgSize, range) def supportsPutPartialSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.putPartial, address, lgSize, range) def supportsHintSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.hint, address, lgSize, range) def supportsAcquireTFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.acquireT, address, lgSize, range) def supportsAcquireBFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.acquireB, address, lgSize, range) def supportsArithmeticFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.arithmetic, address, lgSize, range) def supportsLogicalFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.logical, address, lgSize, range) def supportsGetFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.get, address, lgSize, range) def supportsPutFullFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.putFull, address, lgSize, range) def supportsPutPartialFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.putPartial, address, lgSize, range) def supportsHintFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.hint, address, lgSize, range) def emitsProbeSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.probe, address, lgSize, range) def emitsArithmeticSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.arithmetic, address, lgSize, range) def emitsLogicalSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.logical, address, lgSize, range) def emitsGetSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.get, address, lgSize, range) def emitsPutFullSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.putFull, address, lgSize, range) def emitsPutPartialSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.putPartial, address, lgSize, range) def emitsHintSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.hint, address, lgSize, range) def findTreeViolation() = slaves.flatMap(_.findTreeViolation()).headOption def isTree = !slaves.exists(!_.isTree) def infoString = "Slave Port Beatbytes = " + beatBytes + "\n" + "Slave Port MinLatency = " + minLatency + "\n\n" + slaves.map(_.infoString).mkString def v1copy( managers: Seq[TLSlaveParameters] = slaves, beatBytes: Int = -1, endSinkId: Int = endSinkId, minLatency: Int = minLatency, responseFields: Seq[BundleFieldBase] = responseFields, requestKeys: Seq[BundleKeyBase] = requestKeys) = { new TLSlavePortParameters( slaves = managers, channelBytes = if (beatBytes != -1) TLChannelBeatBytes(beatBytes) else channelBytes, endSinkId = endSinkId, minLatency = minLatency, responseFields = responseFields, requestKeys = requestKeys) } def v2copy( slaves: Seq[TLSlaveParameters] = slaves, channelBytes: TLChannelBeatBytes = channelBytes, endSinkId: Int = endSinkId, minLatency: Int = minLatency, responseFields: Seq[BundleFieldBase] = responseFields, requestKeys: Seq[BundleKeyBase] = requestKeys) = { new TLSlavePortParameters( slaves = slaves, channelBytes = channelBytes, endSinkId = endSinkId, minLatency = minLatency, responseFields = responseFields, requestKeys = requestKeys) } @deprecated("Use v1copy instead of copy","") def copy( managers: Seq[TLSlaveParameters] = slaves, beatBytes: Int = -1, endSinkId: Int = endSinkId, minLatency: Int = minLatency, responseFields: Seq[BundleFieldBase] = responseFields, requestKeys: Seq[BundleKeyBase] = requestKeys) = { v1copy( managers, beatBytes, endSinkId, minLatency, responseFields, requestKeys) } } object TLSlavePortParameters { def v1( managers: Seq[TLSlaveParameters], beatBytes: Int, endSinkId: Int = 0, minLatency: Int = 0, responseFields: Seq[BundleFieldBase] = Nil, requestKeys: Seq[BundleKeyBase] = Nil) = { new TLSlavePortParameters( slaves = managers, channelBytes = TLChannelBeatBytes(beatBytes), endSinkId = endSinkId, minLatency = minLatency, responseFields = responseFields, requestKeys = requestKeys) } } object TLManagerPortParameters { @deprecated("Use TLSlavePortParameters.v1 instead of TLManagerPortParameters","") def apply( managers: Seq[TLSlaveParameters], beatBytes: Int, endSinkId: Int = 0, minLatency: Int = 0, responseFields: Seq[BundleFieldBase] = Nil, requestKeys: Seq[BundleKeyBase] = Nil) = { TLSlavePortParameters.v1( managers, beatBytes, endSinkId, minLatency, responseFields, requestKeys) } } class TLMasterParameters private( val nodePath: Seq[BaseNode], val resources: Seq[Resource], val name: String, val visibility: Seq[AddressSet], val unusedRegionTypes: Set[RegionType.T], val executesOnly: Boolean, val requestFifo: Boolean, // only a request, not a requirement. applies to A, not C. val supports: TLSlaveToMasterTransferSizes, val emits: TLMasterToSlaveTransferSizes, val neverReleasesData: Boolean, val sourceId: IdRange) extends SimpleProduct { override def canEqual(that: Any): Boolean = that.isInstanceOf[TLMasterParameters] override def productPrefix = "TLMasterParameters" // We intentionally omit nodePath for equality testing / formatting def productArity: Int = 10 def productElement(n: Int): Any = n match { case 0 => name case 1 => sourceId case 2 => resources case 3 => visibility case 4 => unusedRegionTypes case 5 => executesOnly case 6 => requestFifo case 7 => supports case 8 => emits case 9 => neverReleasesData case _ => throw new IndexOutOfBoundsException(n.toString) } require (!sourceId.isEmpty) require (!visibility.isEmpty) require (supports.putFull.contains(supports.putPartial)) // We only support these operations if we support Probe (ie: we're a cache) require (supports.probe.contains(supports.arithmetic)) require (supports.probe.contains(supports.logical)) require (supports.probe.contains(supports.get)) require (supports.probe.contains(supports.putFull)) require (supports.probe.contains(supports.putPartial)) require (supports.probe.contains(supports.hint)) visibility.combinations(2).foreach { case Seq(x,y) => require (!x.overlaps(y), s"$x and $y overlap.") } val maxTransfer = List( supports.probe.max, supports.arithmetic.max, supports.logical.max, supports.get.max, supports.putFull.max, supports.putPartial.max).max def infoString = { s"""Master Name = ${name} |visibility = ${visibility} |emits = ${emits.infoString} |sourceId = ${sourceId} | |""".stripMargin } def v1copy( name: String = name, sourceId: IdRange = sourceId, nodePath: Seq[BaseNode] = nodePath, requestFifo: Boolean = requestFifo, visibility: Seq[AddressSet] = visibility, supportsProbe: TransferSizes = supports.probe, supportsArithmetic: TransferSizes = supports.arithmetic, supportsLogical: TransferSizes = supports.logical, supportsGet: TransferSizes = supports.get, supportsPutFull: TransferSizes = supports.putFull, supportsPutPartial: TransferSizes = supports.putPartial, supportsHint: TransferSizes = supports.hint) = { new TLMasterParameters( nodePath = nodePath, resources = this.resources, name = name, visibility = visibility, unusedRegionTypes = this.unusedRegionTypes, executesOnly = this.executesOnly, requestFifo = requestFifo, supports = TLSlaveToMasterTransferSizes( probe = supportsProbe, arithmetic = supportsArithmetic, logical = supportsLogical, get = supportsGet, putFull = supportsPutFull, putPartial = supportsPutPartial, hint = supportsHint), emits = this.emits, neverReleasesData = this.neverReleasesData, sourceId = sourceId) } def v2copy( nodePath: Seq[BaseNode] = nodePath, resources: Seq[Resource] = resources, name: String = name, visibility: Seq[AddressSet] = visibility, unusedRegionTypes: Set[RegionType.T] = unusedRegionTypes, executesOnly: Boolean = executesOnly, requestFifo: Boolean = requestFifo, supports: TLSlaveToMasterTransferSizes = supports, emits: TLMasterToSlaveTransferSizes = emits, neverReleasesData: Boolean = neverReleasesData, sourceId: IdRange = sourceId) = { new TLMasterParameters( nodePath = nodePath, resources = resources, name = name, visibility = visibility, unusedRegionTypes = unusedRegionTypes, executesOnly = executesOnly, requestFifo = requestFifo, supports = supports, emits = emits, neverReleasesData = neverReleasesData, sourceId = sourceId) } @deprecated("Use v1copy instead of copy","") def copy( name: String = name, sourceId: IdRange = sourceId, nodePath: Seq[BaseNode] = nodePath, requestFifo: Boolean = requestFifo, visibility: Seq[AddressSet] = visibility, supportsProbe: TransferSizes = supports.probe, supportsArithmetic: TransferSizes = supports.arithmetic, supportsLogical: TransferSizes = supports.logical, supportsGet: TransferSizes = supports.get, supportsPutFull: TransferSizes = supports.putFull, supportsPutPartial: TransferSizes = supports.putPartial, supportsHint: TransferSizes = supports.hint) = { v1copy( name = name, sourceId = sourceId, nodePath = nodePath, requestFifo = requestFifo, visibility = visibility, supportsProbe = supportsProbe, supportsArithmetic = supportsArithmetic, supportsLogical = supportsLogical, supportsGet = supportsGet, supportsPutFull = supportsPutFull, supportsPutPartial = supportsPutPartial, supportsHint = supportsHint) } } object TLMasterParameters { def v1( name: String, sourceId: IdRange = IdRange(0,1), nodePath: Seq[BaseNode] = Seq(), requestFifo: Boolean = false, visibility: Seq[AddressSet] = Seq(AddressSet(0, ~0)), supportsProbe: TransferSizes = TransferSizes.none, supportsArithmetic: TransferSizes = TransferSizes.none, supportsLogical: TransferSizes = TransferSizes.none, supportsGet: TransferSizes = TransferSizes.none, supportsPutFull: TransferSizes = TransferSizes.none, supportsPutPartial: TransferSizes = TransferSizes.none, supportsHint: TransferSizes = TransferSizes.none) = { new TLMasterParameters( nodePath = nodePath, resources = Nil, name = name, visibility = visibility, unusedRegionTypes = Set(), executesOnly = false, requestFifo = requestFifo, supports = TLSlaveToMasterTransferSizes( probe = supportsProbe, arithmetic = supportsArithmetic, logical = supportsLogical, get = supportsGet, putFull = supportsPutFull, putPartial = supportsPutPartial, hint = supportsHint), emits = TLMasterToSlaveTransferSizes.unknownEmits, neverReleasesData = false, sourceId = sourceId) } def v2( nodePath: Seq[BaseNode] = Seq(), resources: Seq[Resource] = Nil, name: String, visibility: Seq[AddressSet] = Seq(AddressSet(0, ~0)), unusedRegionTypes: Set[RegionType.T] = Set(), executesOnly: Boolean = false, requestFifo: Boolean = false, supports: TLSlaveToMasterTransferSizes = TLSlaveToMasterTransferSizes.unknownSupports, emits: TLMasterToSlaveTransferSizes = TLMasterToSlaveTransferSizes.unknownEmits, neverReleasesData: Boolean = false, sourceId: IdRange = IdRange(0,1)) = { new TLMasterParameters( nodePath = nodePath, resources = resources, name = name, visibility = visibility, unusedRegionTypes = unusedRegionTypes, executesOnly = executesOnly, requestFifo = requestFifo, supports = supports, emits = emits, neverReleasesData = neverReleasesData, sourceId = sourceId) } } object TLClientParameters { @deprecated("Use TLMasterParameters.v1 instead of TLClientParameters","") def apply( name: String, sourceId: IdRange = IdRange(0,1), nodePath: Seq[BaseNode] = Seq(), requestFifo: Boolean = false, visibility: Seq[AddressSet] = Seq(AddressSet.everything), supportsProbe: TransferSizes = TransferSizes.none, supportsArithmetic: TransferSizes = TransferSizes.none, supportsLogical: TransferSizes = TransferSizes.none, supportsGet: TransferSizes = TransferSizes.none, supportsPutFull: TransferSizes = TransferSizes.none, supportsPutPartial: TransferSizes = TransferSizes.none, supportsHint: TransferSizes = TransferSizes.none) = { TLMasterParameters.v1( name = name, sourceId = sourceId, nodePath = nodePath, requestFifo = requestFifo, visibility = visibility, supportsProbe = supportsProbe, supportsArithmetic = supportsArithmetic, supportsLogical = supportsLogical, supportsGet = supportsGet, supportsPutFull = supportsPutFull, supportsPutPartial = supportsPutPartial, supportsHint = supportsHint) } } class TLMasterPortParameters private( val masters: Seq[TLMasterParameters], val channelBytes: TLChannelBeatBytes, val minLatency: Int, val echoFields: Seq[BundleFieldBase], val requestFields: Seq[BundleFieldBase], val responseKeys: Seq[BundleKeyBase]) extends SimpleProduct { override def canEqual(that: Any): Boolean = that.isInstanceOf[TLMasterPortParameters] override def productPrefix = "TLMasterPortParameters" def productArity: Int = 6 def productElement(n: Int): Any = n match { case 0 => masters case 1 => channelBytes case 2 => minLatency case 3 => echoFields case 4 => requestFields case 5 => responseKeys case _ => throw new IndexOutOfBoundsException(n.toString) } require (!masters.isEmpty) require (minLatency >= 0) def clients = masters // Require disjoint ranges for Ids IdRange.overlaps(masters.map(_.sourceId)).foreach { case (x, y) => require (!x.overlaps(y), s"TLClientParameters.sourceId ${x} overlaps ${y}") } // Bounds on required sizes def endSourceId = masters.map(_.sourceId.end).max def maxTransfer = masters.map(_.maxTransfer).max // The unused sources < endSourceId def unusedSources: Seq[Int] = { val usedSources = masters.map(_.sourceId).sortBy(_.start) ((Seq(0) ++ usedSources.map(_.end)) zip usedSources.map(_.start)) flatMap { case (end, start) => end until start } } // Diplomatically determined operation sizes emitted by all inward Masters // as opposed to emits* which generate circuitry to check which specific addresses val allEmitClaims = masters.map(_.emits).reduce( _ intersect _) // Diplomatically determined operation sizes Emitted by at least one inward Masters // as opposed to emits* which generate circuitry to check which specific addresses val anyEmitClaims = masters.map(_.emits).reduce(_ mincover _) // Diplomatically determined operation sizes supported by all inward Masters // as opposed to supports* which generate circuitry to check which specific addresses val allSupportProbe = masters.map(_.supports.probe) .reduce(_ intersect _) val allSupportArithmetic = masters.map(_.supports.arithmetic).reduce(_ intersect _) val allSupportLogical = masters.map(_.supports.logical) .reduce(_ intersect _) val allSupportGet = masters.map(_.supports.get) .reduce(_ intersect _) val allSupportPutFull = masters.map(_.supports.putFull) .reduce(_ intersect _) val allSupportPutPartial = masters.map(_.supports.putPartial).reduce(_ intersect _) val allSupportHint = masters.map(_.supports.hint) .reduce(_ intersect _) // Diplomatically determined operation sizes supported by at least one master // as opposed to supports* which generate circuitry to check which specific addresses val anySupportProbe = masters.map(!_.supports.probe.none) .reduce(_ || _) val anySupportArithmetic = masters.map(!_.supports.arithmetic.none).reduce(_ || _) val anySupportLogical = masters.map(!_.supports.logical.none) .reduce(_ || _) val anySupportGet = masters.map(!_.supports.get.none) .reduce(_ || _) val anySupportPutFull = masters.map(!_.supports.putFull.none) .reduce(_ || _) val anySupportPutPartial = masters.map(!_.supports.putPartial.none).reduce(_ || _) val anySupportHint = masters.map(!_.supports.hint.none) .reduce(_ || _) // These return Option[TLMasterParameters] for your convenience def find(id: Int) = masters.find(_.sourceId.contains(id)) // Synthesizable lookup methods def find(id: UInt) = VecInit(masters.map(_.sourceId.contains(id))) def contains(id: UInt) = find(id).reduce(_ || _) def requestFifo(id: UInt) = Mux1H(find(id), masters.map(c => c.requestFifo.B)) // Available during RTL runtime, checks to see if (id, size) is supported by the master's (client's) diplomatic parameters private def sourceIdHelper(member: TLMasterParameters => TransferSizes)(id: UInt, lgSize: UInt) = { val allSame = masters.map(member(_) == member(masters(0))).reduce(_ && _) // this if statement is a coarse generalization of the groupBy in the sourceIdHelper2 version; // the case where there is only one group. if (allSame) member(masters(0)).containsLg(lgSize) else { // Find the master associated with ID and returns whether that particular master is able to receive transaction of lgSize Mux1H(find(id), masters.map(member(_).containsLg(lgSize))) } } // Check for support of a given operation at a specific id val supportsProbe = sourceIdHelper(_.supports.probe) _ val supportsArithmetic = sourceIdHelper(_.supports.arithmetic) _ val supportsLogical = sourceIdHelper(_.supports.logical) _ val supportsGet = sourceIdHelper(_.supports.get) _ val supportsPutFull = sourceIdHelper(_.supports.putFull) _ val supportsPutPartial = sourceIdHelper(_.supports.putPartial) _ val supportsHint = sourceIdHelper(_.supports.hint) _ // TODO: Merge sourceIdHelper2 with sourceIdHelper private def sourceIdHelper2( member: TLMasterParameters => TransferSizes, sourceId: UInt, lgSize: UInt): Bool = { // Because sourceIds are uniquely owned by each master, we use them to group the // cases that have to be checked. val emitCases = groupByIntoSeq(masters)(m => member(m)).map { case (k, vs) => k -> vs.map(_.sourceId) } emitCases.map { case (s, a) => (s.containsLg(lgSize)) && a.map(_.contains(sourceId)).reduce(_||_) }.foldLeft(false.B)(_||_) } // Check for emit of a given operation at a specific id def emitsAcquireT (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.acquireT, sourceId, lgSize) def emitsAcquireB (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.acquireB, sourceId, lgSize) def emitsArithmetic(sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.arithmetic, sourceId, lgSize) def emitsLogical (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.logical, sourceId, lgSize) def emitsGet (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.get, sourceId, lgSize) def emitsPutFull (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.putFull, sourceId, lgSize) def emitsPutPartial(sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.putPartial, sourceId, lgSize) def emitsHint (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.hint, sourceId, lgSize) def infoString = masters.map(_.infoString).mkString def v1copy( clients: Seq[TLMasterParameters] = masters, minLatency: Int = minLatency, echoFields: Seq[BundleFieldBase] = echoFields, requestFields: Seq[BundleFieldBase] = requestFields, responseKeys: Seq[BundleKeyBase] = responseKeys) = { new TLMasterPortParameters( masters = clients, channelBytes = channelBytes, minLatency = minLatency, echoFields = echoFields, requestFields = requestFields, responseKeys = responseKeys) } def v2copy( masters: Seq[TLMasterParameters] = masters, channelBytes: TLChannelBeatBytes = channelBytes, minLatency: Int = minLatency, echoFields: Seq[BundleFieldBase] = echoFields, requestFields: Seq[BundleFieldBase] = requestFields, responseKeys: Seq[BundleKeyBase] = responseKeys) = { new TLMasterPortParameters( masters = masters, channelBytes = channelBytes, minLatency = minLatency, echoFields = echoFields, requestFields = requestFields, responseKeys = responseKeys) } @deprecated("Use v1copy instead of copy","") def copy( clients: Seq[TLMasterParameters] = masters, minLatency: Int = minLatency, echoFields: Seq[BundleFieldBase] = echoFields, requestFields: Seq[BundleFieldBase] = requestFields, responseKeys: Seq[BundleKeyBase] = responseKeys) = { v1copy( clients, minLatency, echoFields, requestFields, responseKeys) } } object TLClientPortParameters { @deprecated("Use TLMasterPortParameters.v1 instead of TLClientPortParameters","") def apply( clients: Seq[TLMasterParameters], minLatency: Int = 0, echoFields: Seq[BundleFieldBase] = Nil, requestFields: Seq[BundleFieldBase] = Nil, responseKeys: Seq[BundleKeyBase] = Nil) = { TLMasterPortParameters.v1( clients, minLatency, echoFields, requestFields, responseKeys) } } object TLMasterPortParameters { def v1( clients: Seq[TLMasterParameters], minLatency: Int = 0, echoFields: Seq[BundleFieldBase] = Nil, requestFields: Seq[BundleFieldBase] = Nil, responseKeys: Seq[BundleKeyBase] = Nil) = { new TLMasterPortParameters( masters = clients, channelBytes = TLChannelBeatBytes(), minLatency = minLatency, echoFields = echoFields, requestFields = requestFields, responseKeys = responseKeys) } def v2( masters: Seq[TLMasterParameters], channelBytes: TLChannelBeatBytes = TLChannelBeatBytes(), minLatency: Int = 0, echoFields: Seq[BundleFieldBase] = Nil, requestFields: Seq[BundleFieldBase] = Nil, responseKeys: Seq[BundleKeyBase] = Nil) = { new TLMasterPortParameters( masters = masters, channelBytes = channelBytes, minLatency = minLatency, echoFields = echoFields, requestFields = requestFields, responseKeys = responseKeys) } } case class TLBundleParameters( addressBits: Int, dataBits: Int, sourceBits: Int, sinkBits: Int, sizeBits: Int, echoFields: Seq[BundleFieldBase], requestFields: Seq[BundleFieldBase], responseFields: Seq[BundleFieldBase], hasBCE: Boolean) { // Chisel has issues with 0-width wires require (addressBits >= 1) require (dataBits >= 8) require (sourceBits >= 1) require (sinkBits >= 1) require (sizeBits >= 1) require (isPow2(dataBits)) echoFields.foreach { f => require (f.key.isControl, s"${f} is not a legal echo field") } val addrLoBits = log2Up(dataBits/8) // Used to uniquify bus IP names def shortName = s"a${addressBits}d${dataBits}s${sourceBits}k${sinkBits}z${sizeBits}" + (if (hasBCE) "c" else "u") def union(x: TLBundleParameters) = TLBundleParameters( max(addressBits, x.addressBits), max(dataBits, x.dataBits), max(sourceBits, x.sourceBits), max(sinkBits, x.sinkBits), max(sizeBits, x.sizeBits), echoFields = BundleField.union(echoFields ++ x.echoFields), requestFields = BundleField.union(requestFields ++ x.requestFields), responseFields = BundleField.union(responseFields ++ x.responseFields), hasBCE || x.hasBCE) } object TLBundleParameters { val emptyBundleParams = TLBundleParameters( addressBits = 1, dataBits = 8, sourceBits = 1, sinkBits = 1, sizeBits = 1, echoFields = Nil, requestFields = Nil, responseFields = Nil, hasBCE = false) def union(x: Seq[TLBundleParameters]) = x.foldLeft(emptyBundleParams)((x,y) => x.union(y)) def apply(master: TLMasterPortParameters, slave: TLSlavePortParameters) = new TLBundleParameters( addressBits = log2Up(slave.maxAddress + 1), dataBits = slave.beatBytes * 8, sourceBits = log2Up(master.endSourceId), sinkBits = log2Up(slave.endSinkId), sizeBits = log2Up(log2Ceil(max(master.maxTransfer, slave.maxTransfer))+1), echoFields = master.echoFields, requestFields = BundleField.accept(master.requestFields, slave.requestKeys), responseFields = BundleField.accept(slave.responseFields, master.responseKeys), hasBCE = master.anySupportProbe && slave.anySupportAcquireB) } case class TLEdgeParameters( master: TLMasterPortParameters, slave: TLSlavePortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge { // legacy names: def manager = slave def client = master val maxTransfer = max(master.maxTransfer, slave.maxTransfer) val maxLgSize = log2Ceil(maxTransfer) // Sanity check the link... require (maxTransfer >= slave.beatBytes, s"Link's max transfer (${maxTransfer}) < ${slave.slaves.map(_.name)}'s beatBytes (${slave.beatBytes})") def diplomaticClaimsMasterToSlave = master.anyEmitClaims.intersect(slave.anySupportClaims) val bundle = TLBundleParameters(master, slave) def formatEdge = master.infoString + "\n" + slave.infoString } case class TLCreditedDelay( a: CreditedDelay, b: CreditedDelay, c: CreditedDelay, d: CreditedDelay, e: CreditedDelay) { def + (that: TLCreditedDelay): TLCreditedDelay = TLCreditedDelay( a = a + that.a, b = b + that.b, c = c + that.c, d = d + that.d, e = e + that.e) override def toString = s"(${a}, ${b}, ${c}, ${d}, ${e})" } object TLCreditedDelay { def apply(delay: CreditedDelay): TLCreditedDelay = apply(delay, delay.flip, delay, delay.flip, delay) } case class TLCreditedManagerPortParameters(delay: TLCreditedDelay, base: TLSlavePortParameters) {def infoString = base.infoString} case class TLCreditedClientPortParameters(delay: TLCreditedDelay, base: TLMasterPortParameters) {def infoString = base.infoString} case class TLCreditedEdgeParameters(client: TLCreditedClientPortParameters, manager: TLCreditedManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge { val delay = client.delay + manager.delay val bundle = TLBundleParameters(client.base, manager.base) def formatEdge = client.infoString + "\n" + manager.infoString } case class TLAsyncManagerPortParameters(async: AsyncQueueParams, base: TLSlavePortParameters) {def infoString = base.infoString} case class TLAsyncClientPortParameters(base: TLMasterPortParameters) {def infoString = base.infoString} case class TLAsyncBundleParameters(async: AsyncQueueParams, base: TLBundleParameters) case class TLAsyncEdgeParameters(client: TLAsyncClientPortParameters, manager: TLAsyncManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge { val bundle = TLAsyncBundleParameters(manager.async, TLBundleParameters(client.base, manager.base)) def formatEdge = client.infoString + "\n" + manager.infoString } case class TLRationalManagerPortParameters(direction: RationalDirection, base: TLSlavePortParameters) {def infoString = base.infoString} case class TLRationalClientPortParameters(base: TLMasterPortParameters) {def infoString = base.infoString} case class TLRationalEdgeParameters(client: TLRationalClientPortParameters, manager: TLRationalManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge { val bundle = TLBundleParameters(client.base, manager.base) def formatEdge = client.infoString + "\n" + manager.infoString } // To be unified, devices must agree on all of these terms case class ManagerUnificationKey( resources: Seq[Resource], regionType: RegionType.T, executable: Boolean, supportsAcquireT: TransferSizes, supportsAcquireB: TransferSizes, supportsArithmetic: TransferSizes, supportsLogical: TransferSizes, supportsGet: TransferSizes, supportsPutFull: TransferSizes, supportsPutPartial: TransferSizes, supportsHint: TransferSizes) object ManagerUnificationKey { def apply(x: TLSlaveParameters): ManagerUnificationKey = ManagerUnificationKey( resources = x.resources, regionType = x.regionType, executable = x.executable, supportsAcquireT = x.supportsAcquireT, supportsAcquireB = x.supportsAcquireB, supportsArithmetic = x.supportsArithmetic, supportsLogical = x.supportsLogical, supportsGet = x.supportsGet, supportsPutFull = x.supportsPutFull, supportsPutPartial = x.supportsPutPartial, supportsHint = x.supportsHint) } object ManagerUnification { def apply(slaves: Seq[TLSlaveParameters]): List[TLSlaveParameters] = { slaves.groupBy(ManagerUnificationKey.apply).values.map { seq => val agree = seq.forall(_.fifoId == seq.head.fifoId) seq(0).v1copy( address = AddressSet.unify(seq.flatMap(_.address)), fifoId = if (agree) seq(0).fifoId else None) }.toList } } case class TLBufferParams( a: BufferParams = BufferParams.none, b: BufferParams = BufferParams.none, c: BufferParams = BufferParams.none, d: BufferParams = BufferParams.none, e: BufferParams = BufferParams.none ) extends DirectedBuffers[TLBufferParams] { def copyIn(x: BufferParams) = this.copy(b = x, d = x) def copyOut(x: BufferParams) = this.copy(a = x, c = x, e = x) def copyInOut(x: BufferParams) = this.copyIn(x).copyOut(x) } /** Pretty printing of TL source id maps */ class TLSourceIdMap(tl: TLMasterPortParameters) extends IdMap[TLSourceIdMapEntry] { private val tlDigits = String.valueOf(tl.endSourceId-1).length() protected val fmt = s"\t[%${tlDigits}d, %${tlDigits}d) %s%s%s" private val sorted = tl.masters.sortBy(_.sourceId) val mapping: Seq[TLSourceIdMapEntry] = sorted.map { case c => TLSourceIdMapEntry(c.sourceId, c.name, c.supports.probe, c.requestFifo) } } case class TLSourceIdMapEntry(tlId: IdRange, name: String, isCache: Boolean, requestFifo: Boolean) extends IdMapEntry { val from = tlId val to = tlId val maxTransactionsInFlight = Some(tlId.size) } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) || !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.ProbeAckData || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode | small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U || beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }

module TLMonitor_11( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [3:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [31:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7] wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_a_bits_source = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_source = 1'h0; // @[Monitor.scala:36:7] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire c_set = 1'h0; // @[Monitor.scala:738:34] wire c_set_wo_ready = 1'h0; // @[Monitor.scala:739:34] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire _source_ok_T = 1'h1; // @[Parameters.scala:46:9] wire _source_ok_WIRE_0 = 1'h1; // @[Parameters.scala:1138:31] wire _source_ok_T_1 = 1'h1; // @[Parameters.scala:46:9] wire _source_ok_WIRE_1_0 = 1'h1; // @[Parameters.scala:1138:31] wire sink_ok = 1'h1; // @[Monitor.scala:309:31] wire _same_cycle_resp_T_2 = 1'h1; // @[Monitor.scala:684:113] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire _same_cycle_resp_T_8 = 1'h1; // @[Monitor.scala:795:113] wire [8:0] c_first_beats1_decode = 9'h0; // @[Edges.scala:220:59] wire [8:0] c_first_beats1 = 9'h0; // @[Edges.scala:221:14] wire [8:0] _c_first_count_T = 9'h0; // @[Edges.scala:234:27] wire [8:0] c_first_count = 9'h0; // @[Edges.scala:234:25] wire [8:0] _c_first_counter_T = 9'h0; // @[Edges.scala:236:21] wire [8:0] c_first_counter1 = 9'h1FF; // @[Edges.scala:230:28] wire [9:0] _c_first_counter1_T = 10'h3FF; // @[Edges.scala:230:28] wire [2:0] io_in_a_bits_param = 3'h0; // @[Monitor.scala:36:7] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [31:0] _c_first_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_first_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_wo_ready_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_wo_ready_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_4_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_5_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [3:0] _a_opcode_lookup_T = 4'h0; // @[Monitor.scala:637:69] wire [3:0] _a_size_lookup_T = 4'h0; // @[Monitor.scala:641:65] wire [3:0] _a_opcodes_set_T = 4'h0; // @[Monitor.scala:659:79] wire [3:0] _a_sizes_set_T = 4'h0; // @[Monitor.scala:660:77] wire [3:0] _d_opcodes_clr_T_4 = 4'h0; // @[Monitor.scala:680:101] wire [3:0] _d_sizes_clr_T_4 = 4'h0; // @[Monitor.scala:681:99] wire [3:0] _c_first_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] c_opcodes_set = 4'h0; // @[Monitor.scala:740:34] wire [3:0] _c_opcode_lookup_T = 4'h0; // @[Monitor.scala:749:69] wire [3:0] _c_size_lookup_T = 4'h0; // @[Monitor.scala:750:67] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] _c_set_wo_ready_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_wo_ready_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_sizes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_T = 4'h0; // @[Monitor.scala:767:79] wire [3:0] _c_sizes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_sizes_set_T = 4'h0; // @[Monitor.scala:768:77] wire [3:0] _c_probe_ack_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _d_opcodes_clr_T_10 = 4'h0; // @[Monitor.scala:790:101] wire [3:0] _d_sizes_clr_T_10 = 4'h0; // @[Monitor.scala:791:99] wire [3:0] _same_cycle_resp_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_4_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_5_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [30:0] _d_sizes_clr_T_5 = 31'hFF; // @[Monitor.scala:681:74] wire [30:0] _d_sizes_clr_T_11 = 31'hFF; // @[Monitor.scala:791:74] wire [15:0] _a_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _c_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hFF; // @[Monitor.scala:724:57] wire [16:0] _a_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _c_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hFF; // @[Monitor.scala:724:57] wire [15:0] _a_size_lookup_T_3 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _c_size_lookup_T_3 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h100; // @[Monitor.scala:724:51] wire [30:0] _d_opcodes_clr_T_5 = 31'hF; // @[Monitor.scala:680:76] wire [30:0] _d_opcodes_clr_T_11 = 31'hF; // @[Monitor.scala:790:76] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [1:0] _a_set_wo_ready_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _a_set_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _d_clr_wo_ready_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _d_clr_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _c_set_wo_ready_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _c_set_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _d_clr_wo_ready_T_1 = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _d_clr_T_1 = 2'h1; // @[OneHot.scala:58:35] wire [19:0] _c_sizes_set_T_1 = 20'h0; // @[Monitor.scala:768:52] wire [18:0] _c_opcodes_set_T_1 = 19'h0; // @[Monitor.scala:767:54] wire [4:0] _c_sizes_set_interm_T_1 = 5'h1; // @[Monitor.scala:766:59] wire [4:0] c_sizes_set_interm = 5'h0; // @[Monitor.scala:755:40] wire [4:0] _c_sizes_set_interm_T = 5'h0; // @[Monitor.scala:766:51] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [7:0] c_sizes_set = 8'h0; // @[Monitor.scala:741:34] wire [11:0] _c_first_beats1_decode_T_2 = 12'h0; // @[package.scala:243:46] wire [11:0] _c_first_beats1_decode_T_1 = 12'hFFF; // @[package.scala:243:76] wire [26:0] _c_first_beats1_decode_T = 27'hFFF; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [3:0] _a_size_lookup_T_2 = 4'h8; // @[Monitor.scala:641:117] wire [3:0] _d_sizes_clr_T = 4'h8; // @[Monitor.scala:681:48] wire [3:0] _c_size_lookup_T_2 = 4'h8; // @[Monitor.scala:750:119] wire [3:0] _d_sizes_clr_T_6 = 4'h8; // @[Monitor.scala:791:48] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire [26:0] _GEN = 27'hFFF << io_in_a_bits_size_0; // @[package.scala:243:71] wire [26:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [11:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [31:0] _is_aligned_T = {20'h0, io_in_a_bits_address_0[11:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 32'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 4'h2; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire _T_1222 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_1222; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_1222; // @[Decoupled.scala:51:35] wire [11:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [8:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [8:0] a_first_counter; // @[Edges.scala:229:27] wire [9:0] _a_first_counter1_T = {1'h0, a_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] a_first_counter1 = _a_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [8:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [3:0] size; // @[Monitor.scala:389:22] reg [31:0] address; // @[Monitor.scala:391:22] wire _T_1295 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_1295; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_1295; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_1295; // @[Decoupled.scala:51:35] wire [26:0] _GEN_0 = 27'hFFF << io_in_d_bits_size_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [11:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [8:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T = {1'h0, d_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1 = _d_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [3:0] size_1; // @[Monitor.scala:540:22] reg [2:0] sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] reg [1:0] inflight; // @[Monitor.scala:614:27] reg [3:0] inflight_opcodes; // @[Monitor.scala:616:35] wire [3:0] _a_opcode_lookup_T_1 = inflight_opcodes; // @[Monitor.scala:616:35, :637:44] reg [7:0] inflight_sizes; // @[Monitor.scala:618:33] wire [7:0] _a_size_lookup_T_1 = inflight_sizes; // @[Monitor.scala:618:33, :641:40] wire [11:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [8:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [8:0] a_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] a_first_counter1_1 = _a_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [11:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_1 = _d_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire a_set; // @[Monitor.scala:626:34] wire a_set_wo_ready; // @[Monitor.scala:627:34] wire [3:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [7:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [15:0] _a_opcode_lookup_T_6 = {12'h0, _a_opcode_lookup_T_1}; // @[Monitor.scala:637:{44,97}] wire [15:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [7:0] a_size_lookup; // @[Monitor.scala:639:33] wire [15:0] _a_size_lookup_T_6 = {8'h0, _a_size_lookup_T_1}; // @[Monitor.scala:641:{40,91}] wire [15:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[15:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[7:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [4:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _T_1145 = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26] assign a_set_wo_ready = _T_1145; // @[Monitor.scala:627:34, :651:26] wire _same_cycle_resp_T; // @[Monitor.scala:684:44] assign _same_cycle_resp_T = _T_1145; // @[Monitor.scala:651:26, :684:44] assign a_set = _T_1222 & a_first_1; // @[Decoupled.scala:51:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = a_set ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:626:34, :646:40, :655:70, :657:{28,61}] wire [4:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [4:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = a_set ? _a_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:626:34, :648:38, :655:70, :658:{28,59}] wire [18:0] _a_opcodes_set_T_1 = {15'h0, a_opcodes_set_interm}; // @[Monitor.scala:646:40, :659:54] assign a_opcodes_set = a_set ? _a_opcodes_set_T_1[3:0] : 4'h0; // @[Monitor.scala:626:34, :630:33, :655:70, :659:{28,54}] wire [19:0] _a_sizes_set_T_1 = {15'h0, a_sizes_set_interm}; // @[Monitor.scala:648:38, :660:52] assign a_sizes_set = a_set ? _a_sizes_set_T_1[7:0] : 8'h0; // @[Monitor.scala:626:34, :632:31, :655:70, :660:{28,52}] wire d_clr; // @[Monitor.scala:664:34] wire d_clr_wo_ready; // @[Monitor.scala:665:34] wire [3:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [7:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_1 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_1; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_1; // @[Monitor.scala:673:46, :783:46] wire _T_1194 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] assign d_clr_wo_ready = _T_1194 & ~d_release_ack; // @[Monitor.scala:665:34, :673:46, :674:{26,71,74}] assign d_clr = _T_1295 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_opcodes_clr = {4{d_clr}}; // @[Monitor.scala:664:34, :668:33, :678:89, :680:21] assign d_sizes_clr = {8{d_clr}}; // @[Monitor.scala:664:34, :670:31, :678:89, :681:21] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire same_cycle_resp = _same_cycle_resp_T_1; // @[Monitor.scala:684:{55,88}] wire [1:0] _inflight_T = {inflight[1], inflight[0] | a_set}; // @[Monitor.scala:614:27, :626:34, :705:27] wire _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [1:0] _inflight_T_2 = {1'h0, _inflight_T[0] & _inflight_T_1}; // @[Monitor.scala:705:{27,36,38}] wire [3:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [3:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [3:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [7:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [7:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [7:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [1:0] inflight_1; // @[Monitor.scala:726:35] wire [1:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [3:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [3:0] _c_opcode_lookup_T_1 = inflight_opcodes_1; // @[Monitor.scala:727:35, :749:44] wire [3:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [7:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [7:0] _c_size_lookup_T_1 = inflight_sizes_1; // @[Monitor.scala:728:35, :750:42] wire [7:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire [11:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_2; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_2 = _d_first_counter1_T_2[8:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [7:0] c_size_lookup; // @[Monitor.scala:748:35] wire [15:0] _c_opcode_lookup_T_6 = {12'h0, _c_opcode_lookup_T_1}; // @[Monitor.scala:749:{44,97}] wire [15:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [15:0] _c_size_lookup_T_6 = {8'h0, _c_size_lookup_T_1}; // @[Monitor.scala:750:{42,93}] wire [15:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[15:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[7:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire d_clr_1; // @[Monitor.scala:774:34] wire d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [3:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [7:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_1266 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_1266 & d_release_ack_1; // @[Monitor.scala:775:34, :783:46, :784:{26,71}] assign d_clr_1 = _T_1295 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_opcodes_clr_1 = {4{d_clr_1}}; // @[Monitor.scala:774:34, :776:34, :788:88, :790:21] assign d_sizes_clr_1 = {8{d_clr_1}}; // @[Monitor.scala:774:34, :777:34, :788:88, :791:21] wire _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [1:0] _inflight_T_5 = {1'h0, _inflight_T_3[0] & _inflight_T_4}; // @[Monitor.scala:814:{35,44,46}] wire [3:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [3:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [7:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [7:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]

Generate the Verilog code corresponding to the following Chisel files. File Monitor.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceLine import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import freechips.rocketchip.diplomacy.EnableMonitors import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode} import freechips.rocketchip.util.PlusArg case class TLMonitorArgs(edge: TLEdge) abstract class TLMonitorBase(args: TLMonitorArgs) extends Module { val io = IO(new Bundle { val in = Input(new TLBundle(args.edge.bundle)) }) def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit legalize(io.in, args.edge, reset) } object TLMonitor { def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = { if (enable) { EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) } } else { node } } } class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args) { require (args.edge.params(TLMonitorStrictMode) || (! args.edge.params(TestplanTestType).formal)) val cover_prop_class = PropertyClass.Default //Like assert but can flip to being an assumption for formal verification def monAssert(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir, cond, message, PropertyClass.Default) } def assume(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir.flip, cond, message, PropertyClass.Default) } def extra = { args.edge.sourceInfo match { case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)" case _ => "" } } def visible(address: UInt, source: UInt, edge: TLEdge) = edge.client.clients.map { c => !c.sourceId.contains(source) || c.visibility.map(_.contains(address)).reduce(_ || _) }.reduce(_ && _) def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = { //switch this flag to turn on diplomacy in error messages def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n" monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra) // Reuse these subexpressions to save some firrtl lines val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility") //The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B //TODO: check for acquireT? when (bundle.opcode === TLMessages.AcquireBlock) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra) } when (bundle.opcode === TLMessages.AcquirePerm) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra) monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra) monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra) monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra) } } def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = { monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra) monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility") // Reuse these subexpressions to save some firrtl lines val address_ok = edge.manager.containsSafe(edge.address(bundle)) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source when (bundle.opcode === TLMessages.Probe) { assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra) assume (address_ok, "'B' channel Probe carries unmanaged address" + extra) assume (legal_source, "'B' channel Probe carries source that is not first source" + extra) assume (is_aligned, "'B' channel Probe address not aligned to size" + extra) assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra) assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra) assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra) monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra) monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra) monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra) monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra) } } def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = { monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val address_ok = edge.manager.containsSafe(edge.address(bundle)) monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility") when (bundle.opcode === TLMessages.ProbeAck) { monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra) } when (bundle.opcode === TLMessages.ProbeAckData) { monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.Release) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra) monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra) } when (bundle.opcode === TLMessages.ReleaseData) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.AccessAck) { monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra) } when (bundle.opcode === TLMessages.HintAck) { monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra) } } def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = { assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val sink_ok = bundle.sink < edge.manager.endSinkId.U val deny_put_ok = edge.manager.mayDenyPut.B val deny_get_ok = edge.manager.mayDenyGet.B when (bundle.opcode === TLMessages.ReleaseAck) { assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra) assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra) assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra) } when (bundle.opcode === TLMessages.Grant) { assume (source_ok, "'D' channel Grant carries invalid source ID" + extra) assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra) assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel Grant is denied" + extra) } when (bundle.opcode === TLMessages.GrantData) { assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra) assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra) assume (!bundle.denied || bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra) assume (deny_get_ok || !bundle.denied, "'D' channel GrantData is denied" + extra) } when (bundle.opcode === TLMessages.AccessAck) { assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel AccessAck is denied" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra) assume (!bundle.denied || bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra) assume (deny_get_ok || !bundle.denied, "'D' channel AccessAckData is denied" + extra) } when (bundle.opcode === TLMessages.HintAck) { assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel HintAck is denied" + extra) } } def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = { val sink_ok = bundle.sink < edge.manager.endSinkId.U monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra) } def legalizeFormat(bundle: TLBundle, edge: TLEdge) = { when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) } when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) } when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) } when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) } } else { monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra) monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra) monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra) } } def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = { val a_first = edge.first(a.bits, a.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (a.valid && !a_first) { monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra) monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra) monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra) monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra) monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra) } when (a.fire && a_first) { opcode := a.bits.opcode param := a.bits.param size := a.bits.size source := a.bits.source address := a.bits.address } } def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = { val b_first = edge.first(b.bits, b.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (b.valid && !b_first) { monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra) monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra) monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra) monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra) monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra) } when (b.fire && b_first) { opcode := b.bits.opcode param := b.bits.param size := b.bits.size source := b.bits.source address := b.bits.address } } def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = { // Symbolic variable val sym_source = Wire(UInt(edge.client.endSourceId.W)) // TODO: Connect sym_source to a fixed value for simulation and to a // free wire in formal sym_source := 0.U // Type casting Int to UInt val maxSourceId = Wire(UInt(edge.client.endSourceId.W)) maxSourceId := edge.client.endSourceId.U // Delayed verison of sym_source val sym_source_d = Reg(UInt(edge.client.endSourceId.W)) sym_source_d := sym_source // These will be constraints for FV setup Property( MonitorDirection.Monitor, (sym_source === sym_source_d), "sym_source should remain stable", PropertyClass.Default) Property( MonitorDirection.Monitor, (sym_source <= maxSourceId), "sym_source should take legal value", PropertyClass.Default) val my_resp_pend = RegInit(false.B) val my_opcode = Reg(UInt()) val my_size = Reg(UInt()) val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire) val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire) val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source) val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source) val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat) val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend) when (my_set_resp_pend) { my_resp_pend := true.B } .elsewhen (my_clr_resp_pend) { my_resp_pend := false.B } when (my_a_first_beat) { my_opcode := bundle.a.bits.opcode my_size := bundle.a.bits.size } val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size) val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode) val my_resp_opcode_legal = Wire(Bool()) when ((my_resp_opcode === TLMessages.Get) || (my_resp_opcode === TLMessages.ArithmeticData) || (my_resp_opcode === TLMessages.LogicalData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData) } .elsewhen ((my_resp_opcode === TLMessages.PutFullData) || (my_resp_opcode === TLMessages.PutPartialData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck) } .otherwise { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck) } monAssert (IfThen(my_resp_pend, !my_a_first_beat), "Request message should not be sent with a source ID, for which a response message" + "is already pending (not received until current cycle) for a prior request message" + "with the same source ID" + extra) assume (IfThen(my_clr_resp_pend, (my_set_resp_pend || my_resp_pend)), "Response message should be accepted with a source ID only if a request message with the" + "same source ID has been accepted or is being accepted in the current cycle" + extra) assume (IfThen(my_d_first_beat, (my_a_first_beat || my_resp_pend)), "Response message should be sent with a source ID only if a request message with the" + "same source ID has been accepted or is being sent in the current cycle" + extra) assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)), "If d_valid is 1, then d_size should be same as a_size of the corresponding request" + "message" + extra) assume (IfThen(my_d_first_beat, my_resp_opcode_legal), "If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" + "request message" + extra) } def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = { val c_first = edge.first(c.bits, c.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (c.valid && !c_first) { monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra) monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra) monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra) monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra) monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra) } when (c.fire && c_first) { opcode := c.bits.opcode param := c.bits.param size := c.bits.size source := c.bits.source address := c.bits.address } } def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = { val d_first = edge.first(d.bits, d.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val sink = Reg(UInt()) val denied = Reg(Bool()) when (d.valid && !d_first) { assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra) assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra) assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra) assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra) assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra) assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra) } when (d.fire && d_first) { opcode := d.bits.opcode param := d.bits.param size := d.bits.size source := d.bits.source sink := d.bits.sink denied := d.bits.denied } } def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = { legalizeMultibeatA(bundle.a, edge) legalizeMultibeatD(bundle.d, edge) if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { legalizeMultibeatB(bundle.b, edge) legalizeMultibeatC(bundle.c, edge) } } //This is left in for almond which doesn't adhere to the tilelink protocol @deprecated("Use legalizeADSource instead if possible","") def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.client.endSourceId.W)) val a_first = edge.first(bundle.a.bits, bundle.a.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val a_set = WireInit(0.U(edge.client.endSourceId.W)) when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) assume((a_set | inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra) } if (edge.manager.minLatency > 0) { assume(a_set =/= d_clr || !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight | a_set) & ~d_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") assert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = { val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size) val log_a_size_bus_size = log2Ceil(a_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error inflight.suggestName("inflight") val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) inflight_opcodes.suggestName("inflight_opcodes") val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) inflight_sizes.suggestName("inflight_sizes") val a_first = edge.first(bundle.a.bits, bundle.a.fire) a_first.suggestName("a_first") val d_first = edge.first(bundle.d.bits, bundle.d.fire) d_first.suggestName("d_first") val a_set = WireInit(0.U(edge.client.endSourceId.W)) val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) a_set.suggestName("a_set") a_set_wo_ready.suggestName("a_set_wo_ready") val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) a_opcodes_set.suggestName("a_opcodes_set") val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) a_sizes_set.suggestName("a_sizes_set") val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W)) a_opcode_lookup.suggestName("a_opcode_lookup") a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W)) a_size_lookup.suggestName("a_size_lookup") a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant)) val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant)) val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W)) a_opcodes_set_interm.suggestName("a_opcodes_set_interm") val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W)) a_sizes_set_interm.suggestName("a_sizes_set_interm") when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) { a_set_wo_ready := UIntToOH(bundle.a.bits.source) } when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) | 1.U a_sizes_set_interm := (bundle.a.bits.size << 1.U) | 1.U a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U) a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U) monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) d_opcodes_clr.suggestName("d_opcodes_clr") val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) || (bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra) assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) || (bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra) assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) { assume((!bundle.d.ready) || bundle.a.ready, "ready check") } if (edge.manager.minLatency > 0) { assume(a_set_wo_ready =/= d_clr_wo_ready || !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight | a_set) & ~d_clr inflight_opcodes := (inflight_opcodes | a_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes | a_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = { val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size) val log_c_size_bus_size = log2Ceil(c_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) inflight.suggestName("inflight") inflight_opcodes.suggestName("inflight_opcodes") inflight_sizes.suggestName("inflight_sizes") val c_first = edge.first(bundle.c.bits, bundle.c.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) c_first.suggestName("c_first") d_first.suggestName("d_first") val c_set = WireInit(0.U(edge.client.endSourceId.W)) val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) c_set.suggestName("c_set") c_set_wo_ready.suggestName("c_set_wo_ready") c_opcodes_set.suggestName("c_opcodes_set") c_sizes_set.suggestName("c_sizes_set") val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W)) val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W)) c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U c_opcode_lookup.suggestName("c_opcode_lookup") c_size_lookup.suggestName("c_size_lookup") val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W)) val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W)) c_opcodes_set_interm.suggestName("c_opcodes_set_interm") c_sizes_set_interm.suggestName("c_sizes_set_interm") when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) { c_set_wo_ready := UIntToOH(bundle.c.bits.source) } when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) { c_set := UIntToOH(bundle.c.bits.source) c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) | 1.U c_sizes_set_interm := (bundle.c.bits.size << 1.U) | 1.U c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U) c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U) monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra) } val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck || bundle.c.bits.opcode === TLMessages.ProbeAckData val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") d_opcodes_clr.suggestName("d_opcodes_clr") d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) { assume((!bundle.d.ready) || bundle.c.ready, "ready check") } if (edge.manager.minLatency > 0) { when (c_set_wo_ready.orR) { assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra) } } inflight := (inflight | c_set) & ~d_clr inflight_opcodes := (inflight_opcodes | c_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes | c_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.c.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.manager.endSinkId.W)) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val e_first = true.B val d_set = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) { d_set := UIntToOH(bundle.d.bits.sink) assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra) } val e_clr = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) { e_clr := UIntToOH(bundle.e.bits.sink) monAssert((d_set | inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra) } // edge.client.minLatency applies to BC, not DE inflight := (inflight | d_set) & ~e_clr } def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = { val sourceBits = log2Ceil(edge.client.endSourceId) val tooBig = 14 // >16kB worth of flight information gets to be too much if (sourceBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked") } else { if (args.edge.params(TestplanTestType).simulation) { if (args.edge.params(TLMonitorStrictMode)) { legalizeADSource(bundle, edge) legalizeCDSource(bundle, edge) } else { legalizeADSourceOld(bundle, edge) } } if (args.edge.params(TestplanTestType).formal) { legalizeADSourceFormal(bundle, edge) } } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { // legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize... val sinkBits = log2Ceil(edge.manager.endSinkId) if (sinkBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked") } else { legalizeDESink(bundle, edge) } } } def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = { legalizeFormat (bundle, edge) legalizeMultibeat (bundle, edge) legalizeUnique (bundle, edge) } } File Misc.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import scala.math._ class ParameterizedBundle(implicit p: Parameters) extends Bundle trait Clocked extends Bundle { val clock = Clock() val reset = Bool() } object DecoupledHelper { def apply(rvs: Bool*) = new DecoupledHelper(rvs) } class DecoupledHelper(val rvs: Seq[Bool]) { def fire(exclude: Bool, includes: Bool*) = { require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!") (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _) } def fire() = { rvs.reduce(_ && _) } } object MuxT { def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2)) def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3)) def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4)) } /** Creates a cascade of n MuxTs to search for a key value. */ object MuxTLookup { def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } } object ValidMux { def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]*): ValidIO[T] = { apply(v1 +: v2.toSeq) } def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = { val out = Wire(Valid(valids.head.bits.cloneType)) out.valid := valids.map(_.valid).reduce(_ || _) out.bits := MuxCase(valids.head.bits, valids.map(v => (v.valid -> v.bits))) out } } object Str { def apply(s: String): UInt = { var i = BigInt(0) require(s.forall(validChar _)) for (c <- s) i = (i << 8) | c i.U((s.length*8).W) } def apply(x: Char): UInt = { require(validChar(x)) x.U(8.W) } def apply(x: UInt): UInt = apply(x, 10) def apply(x: UInt, radix: Int): UInt = { val rad = radix.U val w = x.getWidth require(w > 0) var q = x var s = digit(q % rad) for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s) } s } def apply(x: SInt): UInt = apply(x, 10) def apply(x: SInt, radix: Int): UInt = { val neg = x < 0.S val abs = x.abs.asUInt if (radix != 10) { Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix)) } else { val rad = radix.U val w = abs.getWidth require(w > 0) var q = abs var s = digit(q % rad) var needSign = neg for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad val placeSpace = q === 0.U val space = Mux(needSign, Str('-'), Str(' ')) needSign = needSign && !placeSpace s = Cat(Mux(placeSpace, space, digit(q % rad)), s) } Cat(Mux(needSign, Str('-'), Str(' ')), s) } } private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0) private def validChar(x: Char) = x == (x & 0xFF) } object Split { def apply(x: UInt, n0: Int) = { val w = x.getWidth (x.extract(w-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n2: Int, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } } object Random { def apply(mod: Int, random: UInt): UInt = { if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0) else PriorityEncoder(partition(apply(1 << log2Up(mod*8), random), mod)) } def apply(mod: Int): UInt = apply(mod, randomizer) def oneHot(mod: Int, random: UInt): UInt = { if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0)) else PriorityEncoderOH(partition(apply(1 << log2Up(mod*8), random), mod)).asUInt } def oneHot(mod: Int): UInt = oneHot(mod, randomizer) private def randomizer = LFSR(16) private def partition(value: UInt, slices: Int) = Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U) } object Majority { def apply(in: Set[Bool]): Bool = { val n = (in.size >> 1) + 1 val clauses = in.subsets(n).map(_.reduce(_ && _)) clauses.reduce(_ || _) } def apply(in: Seq[Bool]): Bool = apply(in.toSet) def apply(in: UInt): Bool = apply(in.asBools.toSet) } object PopCountAtLeast { private def two(x: UInt): (Bool, Bool) = x.getWidth match { case 1 => (x.asBool, false.B) case n => val half = x.getWidth / 2 val (leftOne, leftTwo) = two(x(half - 1, 0)) val (rightOne, rightTwo) = two(x(x.getWidth - 1, half)) (leftOne || rightOne, leftTwo || rightTwo || (leftOne && rightOne)) } def apply(x: UInt, n: Int): Bool = n match { case 0 => true.B case 1 => x.orR case 2 => two(x)._2 case 3 => PopCount(x) >= n.U } } // This gets used everywhere, so make the smallest circuit possible ... // Given an address and size, create a mask of beatBytes size // eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111 // groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01 object MaskGen { def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = { require (groupBy >= 1 && beatBytes >= groupBy) require (isPow2(beatBytes) && isPow2(groupBy)) val lgBytes = log2Ceil(beatBytes) val sizeOH = UIntToOH(lgSize | 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) | (groupBy*2 - 1).U def helper(i: Int): Seq[(Bool, Bool)] = { if (i == 0) { Seq((lgSize >= lgBytes.asUInt, true.B)) } else { val sub = helper(i-1) val size = sizeOH(lgBytes - i) val bit = addr_lo(lgBytes - i) val nbit = !bit Seq.tabulate (1 << i) { j => val (sub_acc, sub_eq) = sub(j/2) val eq = sub_eq && (if (j % 2 == 1) bit else nbit) val acc = sub_acc || (size && eq) (acc, eq) } } } if (groupBy == beatBytes) 1.U else Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse) } } File PlusArg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.experimental._ import chisel3.util.HasBlackBoxResource @deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05") case class PlusArgInfo(default: BigInt, docstring: String) /** Case class for PlusArg information * * @tparam A scala type of the PlusArg value * @param default optional default value * @param docstring text to include in the help * @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT) */ private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String) /** Typeclass for converting a type to a doctype string * @tparam A some type */ trait Doctypeable[A] { /** Return the doctype string for some option */ def toDoctype(a: Option[A]): String } /** Object containing implementations of the Doctypeable typeclass */ object Doctypes { /** Converts an Int => "INT" */ implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" } /** Converts a BigInt => "INT" */ implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" } /** Converts a String => "STRING" */ implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" } } class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map( "FORMAT" -> StringParam(format), "DEFAULT" -> IntParam(default), "WIDTH" -> IntParam(width) )) with HasBlackBoxResource { val io = IO(new Bundle { val out = Output(UInt(width.W)) }) addResource("/vsrc/plusarg_reader.v") } /* This wrapper class has no outputs, making it clear it is a simulation-only construct */ class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module { val io = IO(new Bundle { val count = Input(UInt(width.W)) }) val max = Module(new plusarg_reader(format, default, docstring, width)).io.out when (max > 0.U) { assert (io.count < max, s"Timeout exceeded: $docstring") } } import Doctypes._ object PlusArg { /** PlusArg("foo") will return 42.U if the simulation is run with +foo=42 * Do not use this as an initial register value. The value is set in an * initial block and thus accessing it from another initial is racey. * Add a docstring to document the arg, which can be dumped in an elaboration * pass. */ def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out } /** PlusArg.timeout(name, default, docstring)(count) will use chisel.assert * to kill the simulation when count exceeds the specified integer argument. * Default 0 will never assert. */ def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count } } object PlusArgArtefacts { private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty /* Add a new PlusArg */ @deprecated( "Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05" ) def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring) /** Add a new PlusArg * * @tparam A scala type of the PlusArg value * @param name name for the PlusArg * @param default optional default value * @param docstring text to include in the help */ def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit = artefacts = artefacts ++ Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default))) /* From plus args, generate help text */ private def serializeHelp_cHeader(tab: String = ""): String = artefacts .map{ case(arg, info) => s"""|$tab+$arg=${info.doctype}\\n\\ |$tab${" "*20}${info.docstring}\\n\\ |""".stripMargin ++ info.default.map{ case default => s"$tab${" "*22}(default=${default})\\n\\\n"}.getOrElse("") }.toSeq.mkString("\\n\\\n") ++ "\"" /* From plus args, generate a char array of their names */ private def serializeArray_cHeader(tab: String = ""): String = { val prettyTab = tab + " " * 44 // Length of 'static const ...' s"${tab}static const char * verilog_plusargs [] = {\\\n" ++ artefacts .map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" } .mkString("")++ s"${prettyTab}0};" } /* Generate C code to be included in emulator.cc that helps with * argument parsing based on available Verilog PlusArgs */ def serialize_cHeader(): String = s"""|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\ |${serializeHelp_cHeader(" "*7)} |${serializeArray_cHeader()} |""".stripMargin } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /** Like Vec.apply(idx), but tolerates indices of mismatched width */ def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /** Any Data subtype that has a Bool member named valid. */ type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /** converts from camel case to to underscores, also removing all spaces */ def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /** converts spaces or underscores to hyphens, also lowering case */ def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y | (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y || y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /** Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation */ def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Bundles.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import freechips.rocketchip.util._ import scala.collection.immutable.ListMap import chisel3.util.Decoupled import chisel3.util.DecoupledIO import chisel3.reflect.DataMirror abstract class TLBundleBase(val params: TLBundleParameters) extends Bundle // common combos in lazy policy: // Put + Acquire // Release + AccessAck object TLMessages { // A B C D E def PutFullData = 0.U // . . => AccessAck def PutPartialData = 1.U // . . => AccessAck def ArithmeticData = 2.U // . . => AccessAckData def LogicalData = 3.U // . . => AccessAckData def Get = 4.U // . . => AccessAckData def Hint = 5.U // . . => HintAck def AcquireBlock = 6.U // . => Grant[Data] def AcquirePerm = 7.U // . => Grant[Data] def Probe = 6.U // . => ProbeAck[Data] def AccessAck = 0.U // . . def AccessAckData = 1.U // . . def HintAck = 2.U // . . def ProbeAck = 4.U // . def ProbeAckData = 5.U // . def Release = 6.U // . => ReleaseAck def ReleaseData = 7.U // . => ReleaseAck def Grant = 4.U // . => GrantAck def GrantData = 5.U // . => GrantAck def ReleaseAck = 6.U // . def GrantAck = 0.U // . def isA(x: UInt) = x <= AcquirePerm def isB(x: UInt) = x <= Probe def isC(x: UInt) = x <= ReleaseData def isD(x: UInt) = x <= ReleaseAck def adResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, Grant, Grant) def bcResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, ProbeAck, ProbeAck) def a = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("AcquireBlock",TLPermissions.PermMsgGrow), ("AcquirePerm",TLPermissions.PermMsgGrow)) def b = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("Probe",TLPermissions.PermMsgCap)) def c = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("ProbeAck",TLPermissions.PermMsgReport), ("ProbeAckData",TLPermissions.PermMsgReport), ("Release",TLPermissions.PermMsgReport), ("ReleaseData",TLPermissions.PermMsgReport)) def d = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("Grant",TLPermissions.PermMsgCap), ("GrantData",TLPermissions.PermMsgCap), ("ReleaseAck",TLPermissions.PermMsgReserved)) } /** * The three primary TileLink permissions are: * (T)runk: the agent is (or is on inwards path to) the global point of serialization. * (B)ranch: the agent is on an outwards path to * (N)one: * These permissions are permuted by transfer operations in various ways. * Operations can cap permissions, request for them to be grown or shrunk, * or for a report on their current status. */ object TLPermissions { val aWidth = 2 val bdWidth = 2 val cWidth = 3 // Cap types (Grant = new permissions, Probe = permisions <= target) def toT = 0.U(bdWidth.W) def toB = 1.U(bdWidth.W) def toN = 2.U(bdWidth.W) def isCap(x: UInt) = x <= toN // Grow types (Acquire = permissions >= target) def NtoB = 0.U(aWidth.W) def NtoT = 1.U(aWidth.W) def BtoT = 2.U(aWidth.W) def isGrow(x: UInt) = x <= BtoT // Shrink types (ProbeAck, Release) def TtoB = 0.U(cWidth.W) def TtoN = 1.U(cWidth.W) def BtoN = 2.U(cWidth.W) def isShrink(x: UInt) = x <= BtoN // Report types (ProbeAck, Release) def TtoT = 3.U(cWidth.W) def BtoB = 4.U(cWidth.W) def NtoN = 5.U(cWidth.W) def isReport(x: UInt) = x <= NtoN def PermMsgGrow:Seq[String] = Seq("Grow NtoB", "Grow NtoT", "Grow BtoT") def PermMsgCap:Seq[String] = Seq("Cap toT", "Cap toB", "Cap toN") def PermMsgReport:Seq[String] = Seq("Shrink TtoB", "Shrink TtoN", "Shrink BtoN", "Report TotT", "Report BtoB", "Report NtoN") def PermMsgReserved:Seq[String] = Seq("Reserved") } object TLAtomics { val width = 3 // Arithmetic types def MIN = 0.U(width.W) def MAX = 1.U(width.W) def MINU = 2.U(width.W) def MAXU = 3.U(width.W) def ADD = 4.U(width.W) def isArithmetic(x: UInt) = x <= ADD // Logical types def XOR = 0.U(width.W) def OR = 1.U(width.W) def AND = 2.U(width.W) def SWAP = 3.U(width.W) def isLogical(x: UInt) = x <= SWAP def ArithMsg:Seq[String] = Seq("MIN", "MAX", "MINU", "MAXU", "ADD") def LogicMsg:Seq[String] = Seq("XOR", "OR", "AND", "SWAP") } object TLHints { val width = 1 def PREFETCH_READ = 0.U(width.W) def PREFETCH_WRITE = 1.U(width.W) def isHints(x: UInt) = x <= PREFETCH_WRITE def HintsMsg:Seq[String] = Seq("PrefetchRead", "PrefetchWrite") } sealed trait TLChannel extends TLBundleBase { val channelName: String } sealed trait TLDataChannel extends TLChannel sealed trait TLAddrChannel extends TLDataChannel final class TLBundleA(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleA_${params.shortName}" val channelName = "'A' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(List(TLAtomics.width, TLPermissions.aWidth, TLHints.width).max.W) // amo_opcode || grow perms || hint val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleB(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleB_${params.shortName}" val channelName = "'B' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val address = UInt(params.addressBits.W) // from // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleC(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleC_${params.shortName}" val channelName = "'C' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.cWidth.W) // shrink or report perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleD(params: TLBundleParameters) extends TLBundleBase(params) with TLDataChannel { override def typeName = s"TLBundleD_${params.shortName}" val channelName = "'D' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val sink = UInt(params.sinkBits.W) // from val denied = Bool() // implies corrupt iff *Data val user = BundleMap(params.responseFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleE(params: TLBundleParameters) extends TLBundleBase(params) with TLChannel { override def typeName = s"TLBundleE_${params.shortName}" val channelName = "'E' channel" val sink = UInt(params.sinkBits.W) // to } class TLBundle(val params: TLBundleParameters) extends Record { // Emulate a Bundle with elements abcde or ad depending on params.hasBCE private val optA = Some (Decoupled(new TLBundleA(params))) private val optB = params.hasBCE.option(Flipped(Decoupled(new TLBundleB(params)))) private val optC = params.hasBCE.option(Decoupled(new TLBundleC(params))) private val optD = Some (Flipped(Decoupled(new TLBundleD(params)))) private val optE = params.hasBCE.option(Decoupled(new TLBundleE(params))) def a: DecoupledIO[TLBundleA] = optA.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleA(params))))) def b: DecoupledIO[TLBundleB] = optB.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleB(params))))) def c: DecoupledIO[TLBundleC] = optC.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleC(params))))) def d: DecoupledIO[TLBundleD] = optD.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleD(params))))) def e: DecoupledIO[TLBundleE] = optE.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleE(params))))) val elements = if (params.hasBCE) ListMap("e" -> e, "d" -> d, "c" -> c, "b" -> b, "a" -> a) else ListMap("d" -> d, "a" -> a) def tieoff(): Unit = { DataMirror.specifiedDirectionOf(a.ready) match { case SpecifiedDirection.Input => a.ready := false.B c.ready := false.B e.ready := false.B b.valid := false.B d.valid := false.B case SpecifiedDirection.Output => a.valid := false.B c.valid := false.B e.valid := false.B b.ready := false.B d.ready := false.B case _ => } } } object TLBundle { def apply(params: TLBundleParameters) = new TLBundle(params) } class TLAsyncBundleBase(val params: TLAsyncBundleParameters) extends Bundle class TLAsyncBundle(params: TLAsyncBundleParameters) extends TLAsyncBundleBase(params) { val a = new AsyncBundle(new TLBundleA(params.base), params.async) val b = Flipped(new AsyncBundle(new TLBundleB(params.base), params.async)) val c = new AsyncBundle(new TLBundleC(params.base), params.async) val d = Flipped(new AsyncBundle(new TLBundleD(params.base), params.async)) val e = new AsyncBundle(new TLBundleE(params.base), params.async) } class TLRationalBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = RationalIO(new TLBundleA(params)) val b = Flipped(RationalIO(new TLBundleB(params))) val c = RationalIO(new TLBundleC(params)) val d = Flipped(RationalIO(new TLBundleD(params))) val e = RationalIO(new TLBundleE(params)) } class TLCreditedBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = CreditedIO(new TLBundleA(params)) val b = Flipped(CreditedIO(new TLBundleB(params))) val c = CreditedIO(new TLBundleC(params)) val d = Flipped(CreditedIO(new TLBundleD(params))) val e = CreditedIO(new TLBundleE(params)) } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.nodes._ import freechips.rocketchip.diplomacy.{ AddressDecoder, AddressSet, BufferParams, DirectedBuffers, IdMap, IdMapEntry, IdRange, RegionType, TransferSizes } import freechips.rocketchip.resources.{Resource, ResourceAddress, ResourcePermissions} import freechips.rocketchip.util.{ AsyncQueueParams, BundleField, BundleFieldBase, BundleKeyBase, CreditedDelay, groupByIntoSeq, RationalDirection, SimpleProduct } import scala.math.max //These transfer sizes describe requests issued from masters on the A channel that will be responded by slaves on the D channel case class TLMasterToSlaveTransferSizes( // Supports both Acquire+Release of the following two sizes: acquireT: TransferSizes = TransferSizes.none, acquireB: TransferSizes = TransferSizes.none, arithmetic: TransferSizes = TransferSizes.none, logical: TransferSizes = TransferSizes.none, get: TransferSizes = TransferSizes.none, putFull: TransferSizes = TransferSizes.none, putPartial: TransferSizes = TransferSizes.none, hint: TransferSizes = TransferSizes.none) extends TLCommonTransferSizes { def intersect(rhs: TLMasterToSlaveTransferSizes) = TLMasterToSlaveTransferSizes( acquireT = acquireT .intersect(rhs.acquireT), acquireB = acquireB .intersect(rhs.acquireB), arithmetic = arithmetic.intersect(rhs.arithmetic), logical = logical .intersect(rhs.logical), get = get .intersect(rhs.get), putFull = putFull .intersect(rhs.putFull), putPartial = putPartial.intersect(rhs.putPartial), hint = hint .intersect(rhs.hint)) def mincover(rhs: TLMasterToSlaveTransferSizes) = TLMasterToSlaveTransferSizes( acquireT = acquireT .mincover(rhs.acquireT), acquireB = acquireB .mincover(rhs.acquireB), arithmetic = arithmetic.mincover(rhs.arithmetic), logical = logical .mincover(rhs.logical), get = get .mincover(rhs.get), putFull = putFull .mincover(rhs.putFull), putPartial = putPartial.mincover(rhs.putPartial), hint = hint .mincover(rhs.hint)) // Reduce rendering to a simple yes/no per field override def toString = { def str(x: TransferSizes, flag: String) = if (x.none) "" else flag def flags = Vector( str(acquireT, "T"), str(acquireB, "B"), str(arithmetic, "A"), str(logical, "L"), str(get, "G"), str(putFull, "F"), str(putPartial, "P"), str(hint, "H")) flags.mkString } // Prints out the actual information in a user readable way def infoString = { s"""acquireT = ${acquireT} |acquireB = ${acquireB} |arithmetic = ${arithmetic} |logical = ${logical} |get = ${get} |putFull = ${putFull} |putPartial = ${putPartial} |hint = ${hint} | |""".stripMargin } } object TLMasterToSlaveTransferSizes { def unknownEmits = TLMasterToSlaveTransferSizes( acquireT = TransferSizes(1, 4096), acquireB = TransferSizes(1, 4096), arithmetic = TransferSizes(1, 4096), logical = TransferSizes(1, 4096), get = TransferSizes(1, 4096), putFull = TransferSizes(1, 4096), putPartial = TransferSizes(1, 4096), hint = TransferSizes(1, 4096)) def unknownSupports = TLMasterToSlaveTransferSizes() } //These transfer sizes describe requests issued from slaves on the B channel that will be responded by masters on the C channel case class TLSlaveToMasterTransferSizes( probe: TransferSizes = TransferSizes.none, arithmetic: TransferSizes = TransferSizes.none, logical: TransferSizes = TransferSizes.none, get: TransferSizes = TransferSizes.none, putFull: TransferSizes = TransferSizes.none, putPartial: TransferSizes = TransferSizes.none, hint: TransferSizes = TransferSizes.none ) extends TLCommonTransferSizes { def intersect(rhs: TLSlaveToMasterTransferSizes) = TLSlaveToMasterTransferSizes( probe = probe .intersect(rhs.probe), arithmetic = arithmetic.intersect(rhs.arithmetic), logical = logical .intersect(rhs.logical), get = get .intersect(rhs.get), putFull = putFull .intersect(rhs.putFull), putPartial = putPartial.intersect(rhs.putPartial), hint = hint .intersect(rhs.hint) ) def mincover(rhs: TLSlaveToMasterTransferSizes) = TLSlaveToMasterTransferSizes( probe = probe .mincover(rhs.probe), arithmetic = arithmetic.mincover(rhs.arithmetic), logical = logical .mincover(rhs.logical), get = get .mincover(rhs.get), putFull = putFull .mincover(rhs.putFull), putPartial = putPartial.mincover(rhs.putPartial), hint = hint .mincover(rhs.hint) ) // Reduce rendering to a simple yes/no per field override def toString = { def str(x: TransferSizes, flag: String) = if (x.none) "" else flag def flags = Vector( str(probe, "P"), str(arithmetic, "A"), str(logical, "L"), str(get, "G"), str(putFull, "F"), str(putPartial, "P"), str(hint, "H")) flags.mkString } // Prints out the actual information in a user readable way def infoString = { s"""probe = ${probe} |arithmetic = ${arithmetic} |logical = ${logical} |get = ${get} |putFull = ${putFull} |putPartial = ${putPartial} |hint = ${hint} | |""".stripMargin } } object TLSlaveToMasterTransferSizes { def unknownEmits = TLSlaveToMasterTransferSizes( arithmetic = TransferSizes(1, 4096), logical = TransferSizes(1, 4096), get = TransferSizes(1, 4096), putFull = TransferSizes(1, 4096), putPartial = TransferSizes(1, 4096), hint = TransferSizes(1, 4096), probe = TransferSizes(1, 4096)) def unknownSupports = TLSlaveToMasterTransferSizes() } trait TLCommonTransferSizes { def arithmetic: TransferSizes def logical: TransferSizes def get: TransferSizes def putFull: TransferSizes def putPartial: TransferSizes def hint: TransferSizes } class TLSlaveParameters private( val nodePath: Seq[BaseNode], val resources: Seq[Resource], setName: Option[String], val address: Seq[AddressSet], val regionType: RegionType.T, val executable: Boolean, val fifoId: Option[Int], val supports: TLMasterToSlaveTransferSizes, val emits: TLSlaveToMasterTransferSizes, // By default, slaves are forbidden from issuing 'denied' responses (it prevents Fragmentation) val alwaysGrantsT: Boolean, // typically only true for CacheCork'd read-write devices; dual: neverReleaseData // If fifoId=Some, all accesses sent to the same fifoId are executed and ACK'd in FIFO order // Note: you can only rely on this FIFO behaviour if your TLMasterParameters include requestFifo val mayDenyGet: Boolean, // applies to: AccessAckData, GrantData val mayDenyPut: Boolean) // applies to: AccessAck, Grant, HintAck // ReleaseAck may NEVER be denied extends SimpleProduct { def sortedAddress = address.sorted override def canEqual(that: Any): Boolean = that.isInstanceOf[TLSlaveParameters] override def productPrefix = "TLSlaveParameters" // We intentionally omit nodePath for equality testing / formatting def productArity: Int = 11 def productElement(n: Int): Any = n match { case 0 => name case 1 => address case 2 => resources case 3 => regionType case 4 => executable case 5 => fifoId case 6 => supports case 7 => emits case 8 => alwaysGrantsT case 9 => mayDenyGet case 10 => mayDenyPut case _ => throw new IndexOutOfBoundsException(n.toString) } def supportsAcquireT: TransferSizes = supports.acquireT def supportsAcquireB: TransferSizes = supports.acquireB def supportsArithmetic: TransferSizes = supports.arithmetic def supportsLogical: TransferSizes = supports.logical def supportsGet: TransferSizes = supports.get def supportsPutFull: TransferSizes = supports.putFull def supportsPutPartial: TransferSizes = supports.putPartial def supportsHint: TransferSizes = supports.hint require (!address.isEmpty, "Address cannot be empty") address.foreach { a => require (a.finite, "Address must be finite") } address.combinations(2).foreach { case Seq(x,y) => require (!x.overlaps(y), s"$x and $y overlap.") } require (supportsPutFull.contains(supportsPutPartial), s"PutFull($supportsPutFull) < PutPartial($supportsPutPartial)") require (supportsPutFull.contains(supportsArithmetic), s"PutFull($supportsPutFull) < Arithmetic($supportsArithmetic)") require (supportsPutFull.contains(supportsLogical), s"PutFull($supportsPutFull) < Logical($supportsLogical)") require (supportsGet.contains(supportsArithmetic), s"Get($supportsGet) < Arithmetic($supportsArithmetic)") require (supportsGet.contains(supportsLogical), s"Get($supportsGet) < Logical($supportsLogical)") require (supportsAcquireB.contains(supportsAcquireT), s"AcquireB($supportsAcquireB) < AcquireT($supportsAcquireT)") require (!alwaysGrantsT || supportsAcquireT, s"Must supportAcquireT if promising to always grantT") // Make sure that the regionType agrees with the capabilities require (!supportsAcquireB || regionType >= RegionType.UNCACHED) // acquire -> uncached, tracked, cached require (regionType <= RegionType.UNCACHED || supportsAcquireB) // tracked, cached -> acquire require (regionType != RegionType.UNCACHED || supportsGet) // uncached -> supportsGet val name = setName.orElse(nodePath.lastOption.map(_.lazyModule.name)).getOrElse("disconnected") val maxTransfer = List( // Largest supported transfer of all types supportsAcquireT.max, supportsAcquireB.max, supportsArithmetic.max, supportsLogical.max, supportsGet.max, supportsPutFull.max, supportsPutPartial.max).max val maxAddress = address.map(_.max).max val minAlignment = address.map(_.alignment).min // The device had better not support a transfer larger than its alignment require (minAlignment >= maxTransfer, s"Bad $address: minAlignment ($minAlignment) must be >= maxTransfer ($maxTransfer)") def toResource: ResourceAddress = { ResourceAddress(address, ResourcePermissions( r = supportsAcquireB || supportsGet, w = supportsAcquireT || supportsPutFull, x = executable, c = supportsAcquireB, a = supportsArithmetic && supportsLogical)) } def findTreeViolation() = nodePath.find { case _: MixedAdapterNode[_, _, _, _, _, _, _, _] => false case _: SinkNode[_, _, _, _, _] => false case node => node.inputs.size != 1 } def isTree = findTreeViolation() == None def infoString = { s"""Slave Name = ${name} |Slave Address = ${address} |supports = ${supports.infoString} | |""".stripMargin } def v1copy( address: Seq[AddressSet] = address, resources: Seq[Resource] = resources, regionType: RegionType.T = regionType, executable: Boolean = executable, nodePath: Seq[BaseNode] = nodePath, supportsAcquireT: TransferSizes = supports.acquireT, supportsAcquireB: TransferSizes = supports.acquireB, supportsArithmetic: TransferSizes = supports.arithmetic, supportsLogical: TransferSizes = supports.logical, supportsGet: TransferSizes = supports.get, supportsPutFull: TransferSizes = supports.putFull, supportsPutPartial: TransferSizes = supports.putPartial, supportsHint: TransferSizes = supports.hint, mayDenyGet: Boolean = mayDenyGet, mayDenyPut: Boolean = mayDenyPut, alwaysGrantsT: Boolean = alwaysGrantsT, fifoId: Option[Int] = fifoId) = { new TLSlaveParameters( setName = setName, address = address, resources = resources, regionType = regionType, executable = executable, nodePath = nodePath, supports = TLMasterToSlaveTransferSizes( acquireT = supportsAcquireT, acquireB = supportsAcquireB, arithmetic = supportsArithmetic, logical = supportsLogical, get = supportsGet, putFull = supportsPutFull, putPartial = supportsPutPartial, hint = supportsHint), emits = emits, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut, alwaysGrantsT = alwaysGrantsT, fifoId = fifoId) } def v2copy( nodePath: Seq[BaseNode] = nodePath, resources: Seq[Resource] = resources, name: Option[String] = setName, address: Seq[AddressSet] = address, regionType: RegionType.T = regionType, executable: Boolean = executable, fifoId: Option[Int] = fifoId, supports: TLMasterToSlaveTransferSizes = supports, emits: TLSlaveToMasterTransferSizes = emits, alwaysGrantsT: Boolean = alwaysGrantsT, mayDenyGet: Boolean = mayDenyGet, mayDenyPut: Boolean = mayDenyPut) = { new TLSlaveParameters( nodePath = nodePath, resources = resources, setName = name, address = address, regionType = regionType, executable = executable, fifoId = fifoId, supports = supports, emits = emits, alwaysGrantsT = alwaysGrantsT, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut) } @deprecated("Use v1copy instead of copy","") def copy( address: Seq[AddressSet] = address, resources: Seq[Resource] = resources, regionType: RegionType.T = regionType, executable: Boolean = executable, nodePath: Seq[BaseNode] = nodePath, supportsAcquireT: TransferSizes = supports.acquireT, supportsAcquireB: TransferSizes = supports.acquireB, supportsArithmetic: TransferSizes = supports.arithmetic, supportsLogical: TransferSizes = supports.logical, supportsGet: TransferSizes = supports.get, supportsPutFull: TransferSizes = supports.putFull, supportsPutPartial: TransferSizes = supports.putPartial, supportsHint: TransferSizes = supports.hint, mayDenyGet: Boolean = mayDenyGet, mayDenyPut: Boolean = mayDenyPut, alwaysGrantsT: Boolean = alwaysGrantsT, fifoId: Option[Int] = fifoId) = { v1copy( address = address, resources = resources, regionType = regionType, executable = executable, nodePath = nodePath, supportsAcquireT = supportsAcquireT, supportsAcquireB = supportsAcquireB, supportsArithmetic = supportsArithmetic, supportsLogical = supportsLogical, supportsGet = supportsGet, supportsPutFull = supportsPutFull, supportsPutPartial = supportsPutPartial, supportsHint = supportsHint, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut, alwaysGrantsT = alwaysGrantsT, fifoId = fifoId) } } object TLSlaveParameters { def v1( address: Seq[AddressSet], resources: Seq[Resource] = Seq(), regionType: RegionType.T = RegionType.GET_EFFECTS, executable: Boolean = false, nodePath: Seq[BaseNode] = Seq(), supportsAcquireT: TransferSizes = TransferSizes.none, supportsAcquireB: TransferSizes = TransferSizes.none, supportsArithmetic: TransferSizes = TransferSizes.none, supportsLogical: TransferSizes = TransferSizes.none, supportsGet: TransferSizes = TransferSizes.none, supportsPutFull: TransferSizes = TransferSizes.none, supportsPutPartial: TransferSizes = TransferSizes.none, supportsHint: TransferSizes = TransferSizes.none, mayDenyGet: Boolean = false, mayDenyPut: Boolean = false, alwaysGrantsT: Boolean = false, fifoId: Option[Int] = None) = { new TLSlaveParameters( setName = None, address = address, resources = resources, regionType = regionType, executable = executable, nodePath = nodePath, supports = TLMasterToSlaveTransferSizes( acquireT = supportsAcquireT, acquireB = supportsAcquireB, arithmetic = supportsArithmetic, logical = supportsLogical, get = supportsGet, putFull = supportsPutFull, putPartial = supportsPutPartial, hint = supportsHint), emits = TLSlaveToMasterTransferSizes.unknownEmits, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut, alwaysGrantsT = alwaysGrantsT, fifoId = fifoId) } def v2( address: Seq[AddressSet], nodePath: Seq[BaseNode] = Seq(), resources: Seq[Resource] = Seq(), name: Option[String] = None, regionType: RegionType.T = RegionType.GET_EFFECTS, executable: Boolean = false, fifoId: Option[Int] = None, supports: TLMasterToSlaveTransferSizes = TLMasterToSlaveTransferSizes.unknownSupports, emits: TLSlaveToMasterTransferSizes = TLSlaveToMasterTransferSizes.unknownEmits, alwaysGrantsT: Boolean = false, mayDenyGet: Boolean = false, mayDenyPut: Boolean = false) = { new TLSlaveParameters( nodePath = nodePath, resources = resources, setName = name, address = address, regionType = regionType, executable = executable, fifoId = fifoId, supports = supports, emits = emits, alwaysGrantsT = alwaysGrantsT, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut) } } object TLManagerParameters { @deprecated("Use TLSlaveParameters.v1 instead of TLManagerParameters","") def apply( address: Seq[AddressSet], resources: Seq[Resource] = Seq(), regionType: RegionType.T = RegionType.GET_EFFECTS, executable: Boolean = false, nodePath: Seq[BaseNode] = Seq(), supportsAcquireT: TransferSizes = TransferSizes.none, supportsAcquireB: TransferSizes = TransferSizes.none, supportsArithmetic: TransferSizes = TransferSizes.none, supportsLogical: TransferSizes = TransferSizes.none, supportsGet: TransferSizes = TransferSizes.none, supportsPutFull: TransferSizes = TransferSizes.none, supportsPutPartial: TransferSizes = TransferSizes.none, supportsHint: TransferSizes = TransferSizes.none, mayDenyGet: Boolean = false, mayDenyPut: Boolean = false, alwaysGrantsT: Boolean = false, fifoId: Option[Int] = None) = TLSlaveParameters.v1( address, resources, regionType, executable, nodePath, supportsAcquireT, supportsAcquireB, supportsArithmetic, supportsLogical, supportsGet, supportsPutFull, supportsPutPartial, supportsHint, mayDenyGet, mayDenyPut, alwaysGrantsT, fifoId, ) } case class TLChannelBeatBytes(a: Option[Int], b: Option[Int], c: Option[Int], d: Option[Int]) { def members = Seq(a, b, c, d) members.collect { case Some(beatBytes) => require (isPow2(beatBytes), "Data channel width must be a power of 2") } } object TLChannelBeatBytes{ def apply(beatBytes: Int): TLChannelBeatBytes = TLChannelBeatBytes( Some(beatBytes), Some(beatBytes), Some(beatBytes), Some(beatBytes)) def apply(): TLChannelBeatBytes = TLChannelBeatBytes( None, None, None, None) } class TLSlavePortParameters private( val slaves: Seq[TLSlaveParameters], val channelBytes: TLChannelBeatBytes, val endSinkId: Int, val minLatency: Int, val responseFields: Seq[BundleFieldBase], val requestKeys: Seq[BundleKeyBase]) extends SimpleProduct { def sortedSlaves = slaves.sortBy(_.sortedAddress.head) override def canEqual(that: Any): Boolean = that.isInstanceOf[TLSlavePortParameters] override def productPrefix = "TLSlavePortParameters" def productArity: Int = 6 def productElement(n: Int): Any = n match { case 0 => slaves case 1 => channelBytes case 2 => endSinkId case 3 => minLatency case 4 => responseFields case 5 => requestKeys case _ => throw new IndexOutOfBoundsException(n.toString) } require (!slaves.isEmpty, "Slave ports must have slaves") require (endSinkId >= 0, "Sink ids cannot be negative") require (minLatency >= 0, "Minimum required latency cannot be negative") // Using this API implies you cannot handle mixed-width busses def beatBytes = { channelBytes.members.foreach { width => require (width.isDefined && width == channelBytes.a) } channelBytes.a.get } // TODO this should be deprecated def managers = slaves def requireFifo(policy: TLFIFOFixer.Policy = TLFIFOFixer.allFIFO) = { val relevant = slaves.filter(m => policy(m)) relevant.foreach { m => require(m.fifoId == relevant.head.fifoId, s"${m.name} had fifoId ${m.fifoId}, which was not homogeneous (${slaves.map(s => (s.name, s.fifoId))}) ") } } // Bounds on required sizes def maxAddress = slaves.map(_.maxAddress).max def maxTransfer = slaves.map(_.maxTransfer).max def mayDenyGet = slaves.exists(_.mayDenyGet) def mayDenyPut = slaves.exists(_.mayDenyPut) // Diplomatically determined operation sizes emitted by all outward Slaves // as opposed to emits* which generate circuitry to check which specific addresses val allEmitClaims = slaves.map(_.emits).reduce( _ intersect _) // Operation Emitted by at least one outward Slaves // as opposed to emits* which generate circuitry to check which specific addresses val anyEmitClaims = slaves.map(_.emits).reduce(_ mincover _) // Diplomatically determined operation sizes supported by all outward Slaves // as opposed to supports* which generate circuitry to check which specific addresses val allSupportClaims = slaves.map(_.supports).reduce( _ intersect _) val allSupportAcquireT = allSupportClaims.acquireT val allSupportAcquireB = allSupportClaims.acquireB val allSupportArithmetic = allSupportClaims.arithmetic val allSupportLogical = allSupportClaims.logical val allSupportGet = allSupportClaims.get val allSupportPutFull = allSupportClaims.putFull val allSupportPutPartial = allSupportClaims.putPartial val allSupportHint = allSupportClaims.hint // Operation supported by at least one outward Slaves // as opposed to supports* which generate circuitry to check which specific addresses val anySupportClaims = slaves.map(_.supports).reduce(_ mincover _) val anySupportAcquireT = !anySupportClaims.acquireT.none val anySupportAcquireB = !anySupportClaims.acquireB.none val anySupportArithmetic = !anySupportClaims.arithmetic.none val anySupportLogical = !anySupportClaims.logical.none val anySupportGet = !anySupportClaims.get.none val anySupportPutFull = !anySupportClaims.putFull.none val anySupportPutPartial = !anySupportClaims.putPartial.none val anySupportHint = !anySupportClaims.hint.none // Supporting Acquire means being routable for GrantAck require ((endSinkId == 0) == !anySupportAcquireB) // These return Option[TLSlaveParameters] for your convenience def find(address: BigInt) = slaves.find(_.address.exists(_.contains(address))) // The safe version will check the entire address def findSafe(address: UInt) = VecInit(sortedSlaves.map(_.address.map(_.contains(address)).reduce(_ || _))) // The fast version assumes the address is valid (you probably want fastProperty instead of this function) def findFast(address: UInt) = { val routingMask = AddressDecoder(slaves.map(_.address)) VecInit(sortedSlaves.map(_.address.map(_.widen(~routingMask)).distinct.map(_.contains(address)).reduce(_ || _))) } // Compute the simplest AddressSets that decide a key def fastPropertyGroup[K](p: TLSlaveParameters => K): Seq[(K, Seq[AddressSet])] = { val groups = groupByIntoSeq(sortedSlaves.map(m => (p(m), m.address)))( _._1).map { case (k, vs) => k -> vs.flatMap(_._2) } val reductionMask = AddressDecoder(groups.map(_._2)) groups.map { case (k, seq) => k -> AddressSet.unify(seq.map(_.widen(~reductionMask)).distinct) } } // Select a property def fastProperty[K, D <: Data](address: UInt, p: TLSlaveParameters => K, d: K => D): D = Mux1H(fastPropertyGroup(p).map { case (v, a) => (a.map(_.contains(address)).reduce(_||_), d(v)) }) // Note: returns the actual fifoId + 1 or 0 if None def findFifoIdFast(address: UInt) = fastProperty(address, _.fifoId.map(_+1).getOrElse(0), (i:Int) => i.U) def hasFifoIdFast(address: UInt) = fastProperty(address, _.fifoId.isDefined, (b:Boolean) => b.B) // Does this Port manage this ID/address? def containsSafe(address: UInt) = findSafe(address).reduce(_ || _) private def addressHelper( // setting safe to false indicates that all addresses are expected to be legal, which might reduce circuit complexity safe: Boolean, // member filters out the sizes being checked based on the opcode being emitted or supported member: TLSlaveParameters => TransferSizes, address: UInt, lgSize: UInt, // range provides a limit on the sizes that are expected to be evaluated, which might reduce circuit complexity range: Option[TransferSizes]): Bool = { // trim reduces circuit complexity by intersecting checked sizes with the range argument def trim(x: TransferSizes) = range.map(_.intersect(x)).getOrElse(x) // groupBy returns an unordered map, convert back to Seq and sort the result for determinism // groupByIntoSeq is turning slaves into trimmed membership sizes // We are grouping all the slaves by their transfer size where // if they support the trimmed size then // member is the type of transfer that you are looking for (What you are trying to filter on) // When you consider membership, you are trimming the sizes to only the ones that you care about // you are filtering the slaves based on both whether they support a particular opcode and the size // Grouping the slaves based on the actual transfer size range they support // intersecting the range and checking their membership // FOR SUPPORTCASES instead of returning the list of slaves, // you are returning a map from transfer size to the set of // address sets that are supported for that transfer size // find all the slaves that support a certain type of operation and then group their addresses by the supported size // for every size there could be multiple address ranges // safety is a trade off between checking between all possible addresses vs only the addresses // that are known to have supported sizes // the trade off is 'checking all addresses is a more expensive circuit but will always give you // the right answer even if you give it an illegal address' // the not safe version is a cheaper circuit but if you give it an illegal address then it might produce the wrong answer // fast presumes address legality // This groupByIntoSeq deterministically groups all address sets for which a given `member` transfer size applies. // In the resulting Map of cases, the keys are transfer sizes and the values are all address sets which emit or support that size. val supportCases = groupByIntoSeq(slaves)(m => trim(member(m))).map { case (k: TransferSizes, vs: Seq[TLSlaveParameters]) => k -> vs.flatMap(_.address) } // safe produces a circuit that compares against all possible addresses, // whereas fast presumes that the address is legal but uses an efficient address decoder val mask = if (safe) ~BigInt(0) else AddressDecoder(supportCases.map(_._2)) // Simplified creates the most concise possible representation of each cases' address sets based on the mask. val simplified = supportCases.map { case (k, seq) => k -> AddressSet.unify(seq.map(_.widen(~mask)).distinct) } simplified.map { case (s, a) => // s is a size, you are checking for this size either the size of the operation is in s // We return an or-reduction of all the cases, checking whether any contains both the dynamic size and dynamic address on the wire. ((Some(s) == range).B || s.containsLg(lgSize)) && a.map(_.contains(address)).reduce(_||_) }.foldLeft(false.B)(_||_) } def supportsAcquireTSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.acquireT, address, lgSize, range) def supportsAcquireBSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.acquireB, address, lgSize, range) def supportsArithmeticSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.arithmetic, address, lgSize, range) def supportsLogicalSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.logical, address, lgSize, range) def supportsGetSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.get, address, lgSize, range) def supportsPutFullSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.putFull, address, lgSize, range) def supportsPutPartialSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.putPartial, address, lgSize, range) def supportsHintSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.hint, address, lgSize, range) def supportsAcquireTFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.acquireT, address, lgSize, range) def supportsAcquireBFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.acquireB, address, lgSize, range) def supportsArithmeticFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.arithmetic, address, lgSize, range) def supportsLogicalFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.logical, address, lgSize, range) def supportsGetFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.get, address, lgSize, range) def supportsPutFullFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.putFull, address, lgSize, range) def supportsPutPartialFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.putPartial, address, lgSize, range) def supportsHintFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.hint, address, lgSize, range) def emitsProbeSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.probe, address, lgSize, range) def emitsArithmeticSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.arithmetic, address, lgSize, range) def emitsLogicalSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.logical, address, lgSize, range) def emitsGetSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.get, address, lgSize, range) def emitsPutFullSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.putFull, address, lgSize, range) def emitsPutPartialSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.putPartial, address, lgSize, range) def emitsHintSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.hint, address, lgSize, range) def findTreeViolation() = slaves.flatMap(_.findTreeViolation()).headOption def isTree = !slaves.exists(!_.isTree) def infoString = "Slave Port Beatbytes = " + beatBytes + "\n" + "Slave Port MinLatency = " + minLatency + "\n\n" + slaves.map(_.infoString).mkString def v1copy( managers: Seq[TLSlaveParameters] = slaves, beatBytes: Int = -1, endSinkId: Int = endSinkId, minLatency: Int = minLatency, responseFields: Seq[BundleFieldBase] = responseFields, requestKeys: Seq[BundleKeyBase] = requestKeys) = { new TLSlavePortParameters( slaves = managers, channelBytes = if (beatBytes != -1) TLChannelBeatBytes(beatBytes) else channelBytes, endSinkId = endSinkId, minLatency = minLatency, responseFields = responseFields, requestKeys = requestKeys) } def v2copy( slaves: Seq[TLSlaveParameters] = slaves, channelBytes: TLChannelBeatBytes = channelBytes, endSinkId: Int = endSinkId, minLatency: Int = minLatency, responseFields: Seq[BundleFieldBase] = responseFields, requestKeys: Seq[BundleKeyBase] = requestKeys) = { new TLSlavePortParameters( slaves = slaves, channelBytes = channelBytes, endSinkId = endSinkId, minLatency = minLatency, responseFields = responseFields, requestKeys = requestKeys) } @deprecated("Use v1copy instead of copy","") def copy( managers: Seq[TLSlaveParameters] = slaves, beatBytes: Int = -1, endSinkId: Int = endSinkId, minLatency: Int = minLatency, responseFields: Seq[BundleFieldBase] = responseFields, requestKeys: Seq[BundleKeyBase] = requestKeys) = { v1copy( managers, beatBytes, endSinkId, minLatency, responseFields, requestKeys) } } object TLSlavePortParameters { def v1( managers: Seq[TLSlaveParameters], beatBytes: Int, endSinkId: Int = 0, minLatency: Int = 0, responseFields: Seq[BundleFieldBase] = Nil, requestKeys: Seq[BundleKeyBase] = Nil) = { new TLSlavePortParameters( slaves = managers, channelBytes = TLChannelBeatBytes(beatBytes), endSinkId = endSinkId, minLatency = minLatency, responseFields = responseFields, requestKeys = requestKeys) } } object TLManagerPortParameters { @deprecated("Use TLSlavePortParameters.v1 instead of TLManagerPortParameters","") def apply( managers: Seq[TLSlaveParameters], beatBytes: Int, endSinkId: Int = 0, minLatency: Int = 0, responseFields: Seq[BundleFieldBase] = Nil, requestKeys: Seq[BundleKeyBase] = Nil) = { TLSlavePortParameters.v1( managers, beatBytes, endSinkId, minLatency, responseFields, requestKeys) } } class TLMasterParameters private( val nodePath: Seq[BaseNode], val resources: Seq[Resource], val name: String, val visibility: Seq[AddressSet], val unusedRegionTypes: Set[RegionType.T], val executesOnly: Boolean, val requestFifo: Boolean, // only a request, not a requirement. applies to A, not C. val supports: TLSlaveToMasterTransferSizes, val emits: TLMasterToSlaveTransferSizes, val neverReleasesData: Boolean, val sourceId: IdRange) extends SimpleProduct { override def canEqual(that: Any): Boolean = that.isInstanceOf[TLMasterParameters] override def productPrefix = "TLMasterParameters" // We intentionally omit nodePath for equality testing / formatting def productArity: Int = 10 def productElement(n: Int): Any = n match { case 0 => name case 1 => sourceId case 2 => resources case 3 => visibility case 4 => unusedRegionTypes case 5 => executesOnly case 6 => requestFifo case 7 => supports case 8 => emits case 9 => neverReleasesData case _ => throw new IndexOutOfBoundsException(n.toString) } require (!sourceId.isEmpty) require (!visibility.isEmpty) require (supports.putFull.contains(supports.putPartial)) // We only support these operations if we support Probe (ie: we're a cache) require (supports.probe.contains(supports.arithmetic)) require (supports.probe.contains(supports.logical)) require (supports.probe.contains(supports.get)) require (supports.probe.contains(supports.putFull)) require (supports.probe.contains(supports.putPartial)) require (supports.probe.contains(supports.hint)) visibility.combinations(2).foreach { case Seq(x,y) => require (!x.overlaps(y), s"$x and $y overlap.") } val maxTransfer = List( supports.probe.max, supports.arithmetic.max, supports.logical.max, supports.get.max, supports.putFull.max, supports.putPartial.max).max def infoString = { s"""Master Name = ${name} |visibility = ${visibility} |emits = ${emits.infoString} |sourceId = ${sourceId} | |""".stripMargin } def v1copy( name: String = name, sourceId: IdRange = sourceId, nodePath: Seq[BaseNode] = nodePath, requestFifo: Boolean = requestFifo, visibility: Seq[AddressSet] = visibility, supportsProbe: TransferSizes = supports.probe, supportsArithmetic: TransferSizes = supports.arithmetic, supportsLogical: TransferSizes = supports.logical, supportsGet: TransferSizes = supports.get, supportsPutFull: TransferSizes = supports.putFull, supportsPutPartial: TransferSizes = supports.putPartial, supportsHint: TransferSizes = supports.hint) = { new TLMasterParameters( nodePath = nodePath, resources = this.resources, name = name, visibility = visibility, unusedRegionTypes = this.unusedRegionTypes, executesOnly = this.executesOnly, requestFifo = requestFifo, supports = TLSlaveToMasterTransferSizes( probe = supportsProbe, arithmetic = supportsArithmetic, logical = supportsLogical, get = supportsGet, putFull = supportsPutFull, putPartial = supportsPutPartial, hint = supportsHint), emits = this.emits, neverReleasesData = this.neverReleasesData, sourceId = sourceId) } def v2copy( nodePath: Seq[BaseNode] = nodePath, resources: Seq[Resource] = resources, name: String = name, visibility: Seq[AddressSet] = visibility, unusedRegionTypes: Set[RegionType.T] = unusedRegionTypes, executesOnly: Boolean = executesOnly, requestFifo: Boolean = requestFifo, supports: TLSlaveToMasterTransferSizes = supports, emits: TLMasterToSlaveTransferSizes = emits, neverReleasesData: Boolean = neverReleasesData, sourceId: IdRange = sourceId) = { new TLMasterParameters( nodePath = nodePath, resources = resources, name = name, visibility = visibility, unusedRegionTypes = unusedRegionTypes, executesOnly = executesOnly, requestFifo = requestFifo, supports = supports, emits = emits, neverReleasesData = neverReleasesData, sourceId = sourceId) } @deprecated("Use v1copy instead of copy","") def copy( name: String = name, sourceId: IdRange = sourceId, nodePath: Seq[BaseNode] = nodePath, requestFifo: Boolean = requestFifo, visibility: Seq[AddressSet] = visibility, supportsProbe: TransferSizes = supports.probe, supportsArithmetic: TransferSizes = supports.arithmetic, supportsLogical: TransferSizes = supports.logical, supportsGet: TransferSizes = supports.get, supportsPutFull: TransferSizes = supports.putFull, supportsPutPartial: TransferSizes = supports.putPartial, supportsHint: TransferSizes = supports.hint) = { v1copy( name = name, sourceId = sourceId, nodePath = nodePath, requestFifo = requestFifo, visibility = visibility, supportsProbe = supportsProbe, supportsArithmetic = supportsArithmetic, supportsLogical = supportsLogical, supportsGet = supportsGet, supportsPutFull = supportsPutFull, supportsPutPartial = supportsPutPartial, supportsHint = supportsHint) } } object TLMasterParameters { def v1( name: String, sourceId: IdRange = IdRange(0,1), nodePath: Seq[BaseNode] = Seq(), requestFifo: Boolean = false, visibility: Seq[AddressSet] = Seq(AddressSet(0, ~0)), supportsProbe: TransferSizes = TransferSizes.none, supportsArithmetic: TransferSizes = TransferSizes.none, supportsLogical: TransferSizes = TransferSizes.none, supportsGet: TransferSizes = TransferSizes.none, supportsPutFull: TransferSizes = TransferSizes.none, supportsPutPartial: TransferSizes = TransferSizes.none, supportsHint: TransferSizes = TransferSizes.none) = { new TLMasterParameters( nodePath = nodePath, resources = Nil, name = name, visibility = visibility, unusedRegionTypes = Set(), executesOnly = false, requestFifo = requestFifo, supports = TLSlaveToMasterTransferSizes( probe = supportsProbe, arithmetic = supportsArithmetic, logical = supportsLogical, get = supportsGet, putFull = supportsPutFull, putPartial = supportsPutPartial, hint = supportsHint), emits = TLMasterToSlaveTransferSizes.unknownEmits, neverReleasesData = false, sourceId = sourceId) } def v2( nodePath: Seq[BaseNode] = Seq(), resources: Seq[Resource] = Nil, name: String, visibility: Seq[AddressSet] = Seq(AddressSet(0, ~0)), unusedRegionTypes: Set[RegionType.T] = Set(), executesOnly: Boolean = false, requestFifo: Boolean = false, supports: TLSlaveToMasterTransferSizes = TLSlaveToMasterTransferSizes.unknownSupports, emits: TLMasterToSlaveTransferSizes = TLMasterToSlaveTransferSizes.unknownEmits, neverReleasesData: Boolean = false, sourceId: IdRange = IdRange(0,1)) = { new TLMasterParameters( nodePath = nodePath, resources = resources, name = name, visibility = visibility, unusedRegionTypes = unusedRegionTypes, executesOnly = executesOnly, requestFifo = requestFifo, supports = supports, emits = emits, neverReleasesData = neverReleasesData, sourceId = sourceId) } } object TLClientParameters { @deprecated("Use TLMasterParameters.v1 instead of TLClientParameters","") def apply( name: String, sourceId: IdRange = IdRange(0,1), nodePath: Seq[BaseNode] = Seq(), requestFifo: Boolean = false, visibility: Seq[AddressSet] = Seq(AddressSet.everything), supportsProbe: TransferSizes = TransferSizes.none, supportsArithmetic: TransferSizes = TransferSizes.none, supportsLogical: TransferSizes = TransferSizes.none, supportsGet: TransferSizes = TransferSizes.none, supportsPutFull: TransferSizes = TransferSizes.none, supportsPutPartial: TransferSizes = TransferSizes.none, supportsHint: TransferSizes = TransferSizes.none) = { TLMasterParameters.v1( name = name, sourceId = sourceId, nodePath = nodePath, requestFifo = requestFifo, visibility = visibility, supportsProbe = supportsProbe, supportsArithmetic = supportsArithmetic, supportsLogical = supportsLogical, supportsGet = supportsGet, supportsPutFull = supportsPutFull, supportsPutPartial = supportsPutPartial, supportsHint = supportsHint) } } class TLMasterPortParameters private( val masters: Seq[TLMasterParameters], val channelBytes: TLChannelBeatBytes, val minLatency: Int, val echoFields: Seq[BundleFieldBase], val requestFields: Seq[BundleFieldBase], val responseKeys: Seq[BundleKeyBase]) extends SimpleProduct { override def canEqual(that: Any): Boolean = that.isInstanceOf[TLMasterPortParameters] override def productPrefix = "TLMasterPortParameters" def productArity: Int = 6 def productElement(n: Int): Any = n match { case 0 => masters case 1 => channelBytes case 2 => minLatency case 3 => echoFields case 4 => requestFields case 5 => responseKeys case _ => throw new IndexOutOfBoundsException(n.toString) } require (!masters.isEmpty) require (minLatency >= 0) def clients = masters // Require disjoint ranges for Ids IdRange.overlaps(masters.map(_.sourceId)).foreach { case (x, y) => require (!x.overlaps(y), s"TLClientParameters.sourceId ${x} overlaps ${y}") } // Bounds on required sizes def endSourceId = masters.map(_.sourceId.end).max def maxTransfer = masters.map(_.maxTransfer).max // The unused sources < endSourceId def unusedSources: Seq[Int] = { val usedSources = masters.map(_.sourceId).sortBy(_.start) ((Seq(0) ++ usedSources.map(_.end)) zip usedSources.map(_.start)) flatMap { case (end, start) => end until start } } // Diplomatically determined operation sizes emitted by all inward Masters // as opposed to emits* which generate circuitry to check which specific addresses val allEmitClaims = masters.map(_.emits).reduce( _ intersect _) // Diplomatically determined operation sizes Emitted by at least one inward Masters // as opposed to emits* which generate circuitry to check which specific addresses val anyEmitClaims = masters.map(_.emits).reduce(_ mincover _) // Diplomatically determined operation sizes supported by all inward Masters // as opposed to supports* which generate circuitry to check which specific addresses val allSupportProbe = masters.map(_.supports.probe) .reduce(_ intersect _) val allSupportArithmetic = masters.map(_.supports.arithmetic).reduce(_ intersect _) val allSupportLogical = masters.map(_.supports.logical) .reduce(_ intersect _) val allSupportGet = masters.map(_.supports.get) .reduce(_ intersect _) val allSupportPutFull = masters.map(_.supports.putFull) .reduce(_ intersect _) val allSupportPutPartial = masters.map(_.supports.putPartial).reduce(_ intersect _) val allSupportHint = masters.map(_.supports.hint) .reduce(_ intersect _) // Diplomatically determined operation sizes supported by at least one master // as opposed to supports* which generate circuitry to check which specific addresses val anySupportProbe = masters.map(!_.supports.probe.none) .reduce(_ || _) val anySupportArithmetic = masters.map(!_.supports.arithmetic.none).reduce(_ || _) val anySupportLogical = masters.map(!_.supports.logical.none) .reduce(_ || _) val anySupportGet = masters.map(!_.supports.get.none) .reduce(_ || _) val anySupportPutFull = masters.map(!_.supports.putFull.none) .reduce(_ || _) val anySupportPutPartial = masters.map(!_.supports.putPartial.none).reduce(_ || _) val anySupportHint = masters.map(!_.supports.hint.none) .reduce(_ || _) // These return Option[TLMasterParameters] for your convenience def find(id: Int) = masters.find(_.sourceId.contains(id)) // Synthesizable lookup methods def find(id: UInt) = VecInit(masters.map(_.sourceId.contains(id))) def contains(id: UInt) = find(id).reduce(_ || _) def requestFifo(id: UInt) = Mux1H(find(id), masters.map(c => c.requestFifo.B)) // Available during RTL runtime, checks to see if (id, size) is supported by the master's (client's) diplomatic parameters private def sourceIdHelper(member: TLMasterParameters => TransferSizes)(id: UInt, lgSize: UInt) = { val allSame = masters.map(member(_) == member(masters(0))).reduce(_ && _) // this if statement is a coarse generalization of the groupBy in the sourceIdHelper2 version; // the case where there is only one group. if (allSame) member(masters(0)).containsLg(lgSize) else { // Find the master associated with ID and returns whether that particular master is able to receive transaction of lgSize Mux1H(find(id), masters.map(member(_).containsLg(lgSize))) } } // Check for support of a given operation at a specific id val supportsProbe = sourceIdHelper(_.supports.probe) _ val supportsArithmetic = sourceIdHelper(_.supports.arithmetic) _ val supportsLogical = sourceIdHelper(_.supports.logical) _ val supportsGet = sourceIdHelper(_.supports.get) _ val supportsPutFull = sourceIdHelper(_.supports.putFull) _ val supportsPutPartial = sourceIdHelper(_.supports.putPartial) _ val supportsHint = sourceIdHelper(_.supports.hint) _ // TODO: Merge sourceIdHelper2 with sourceIdHelper private def sourceIdHelper2( member: TLMasterParameters => TransferSizes, sourceId: UInt, lgSize: UInt): Bool = { // Because sourceIds are uniquely owned by each master, we use them to group the // cases that have to be checked. val emitCases = groupByIntoSeq(masters)(m => member(m)).map { case (k, vs) => k -> vs.map(_.sourceId) } emitCases.map { case (s, a) => (s.containsLg(lgSize)) && a.map(_.contains(sourceId)).reduce(_||_) }.foldLeft(false.B)(_||_) } // Check for emit of a given operation at a specific id def emitsAcquireT (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.acquireT, sourceId, lgSize) def emitsAcquireB (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.acquireB, sourceId, lgSize) def emitsArithmetic(sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.arithmetic, sourceId, lgSize) def emitsLogical (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.logical, sourceId, lgSize) def emitsGet (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.get, sourceId, lgSize) def emitsPutFull (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.putFull, sourceId, lgSize) def emitsPutPartial(sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.putPartial, sourceId, lgSize) def emitsHint (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.hint, sourceId, lgSize) def infoString = masters.map(_.infoString).mkString def v1copy( clients: Seq[TLMasterParameters] = masters, minLatency: Int = minLatency, echoFields: Seq[BundleFieldBase] = echoFields, requestFields: Seq[BundleFieldBase] = requestFields, responseKeys: Seq[BundleKeyBase] = responseKeys) = { new TLMasterPortParameters( masters = clients, channelBytes = channelBytes, minLatency = minLatency, echoFields = echoFields, requestFields = requestFields, responseKeys = responseKeys) } def v2copy( masters: Seq[TLMasterParameters] = masters, channelBytes: TLChannelBeatBytes = channelBytes, minLatency: Int = minLatency, echoFields: Seq[BundleFieldBase] = echoFields, requestFields: Seq[BundleFieldBase] = requestFields, responseKeys: Seq[BundleKeyBase] = responseKeys) = { new TLMasterPortParameters( masters = masters, channelBytes = channelBytes, minLatency = minLatency, echoFields = echoFields, requestFields = requestFields, responseKeys = responseKeys) } @deprecated("Use v1copy instead of copy","") def copy( clients: Seq[TLMasterParameters] = masters, minLatency: Int = minLatency, echoFields: Seq[BundleFieldBase] = echoFields, requestFields: Seq[BundleFieldBase] = requestFields, responseKeys: Seq[BundleKeyBase] = responseKeys) = { v1copy( clients, minLatency, echoFields, requestFields, responseKeys) } } object TLClientPortParameters { @deprecated("Use TLMasterPortParameters.v1 instead of TLClientPortParameters","") def apply( clients: Seq[TLMasterParameters], minLatency: Int = 0, echoFields: Seq[BundleFieldBase] = Nil, requestFields: Seq[BundleFieldBase] = Nil, responseKeys: Seq[BundleKeyBase] = Nil) = { TLMasterPortParameters.v1( clients, minLatency, echoFields, requestFields, responseKeys) } } object TLMasterPortParameters { def v1( clients: Seq[TLMasterParameters], minLatency: Int = 0, echoFields: Seq[BundleFieldBase] = Nil, requestFields: Seq[BundleFieldBase] = Nil, responseKeys: Seq[BundleKeyBase] = Nil) = { new TLMasterPortParameters( masters = clients, channelBytes = TLChannelBeatBytes(), minLatency = minLatency, echoFields = echoFields, requestFields = requestFields, responseKeys = responseKeys) } def v2( masters: Seq[TLMasterParameters], channelBytes: TLChannelBeatBytes = TLChannelBeatBytes(), minLatency: Int = 0, echoFields: Seq[BundleFieldBase] = Nil, requestFields: Seq[BundleFieldBase] = Nil, responseKeys: Seq[BundleKeyBase] = Nil) = { new TLMasterPortParameters( masters = masters, channelBytes = channelBytes, minLatency = minLatency, echoFields = echoFields, requestFields = requestFields, responseKeys = responseKeys) } } case class TLBundleParameters( addressBits: Int, dataBits: Int, sourceBits: Int, sinkBits: Int, sizeBits: Int, echoFields: Seq[BundleFieldBase], requestFields: Seq[BundleFieldBase], responseFields: Seq[BundleFieldBase], hasBCE: Boolean) { // Chisel has issues with 0-width wires require (addressBits >= 1) require (dataBits >= 8) require (sourceBits >= 1) require (sinkBits >= 1) require (sizeBits >= 1) require (isPow2(dataBits)) echoFields.foreach { f => require (f.key.isControl, s"${f} is not a legal echo field") } val addrLoBits = log2Up(dataBits/8) // Used to uniquify bus IP names def shortName = s"a${addressBits}d${dataBits}s${sourceBits}k${sinkBits}z${sizeBits}" + (if (hasBCE) "c" else "u") def union(x: TLBundleParameters) = TLBundleParameters( max(addressBits, x.addressBits), max(dataBits, x.dataBits), max(sourceBits, x.sourceBits), max(sinkBits, x.sinkBits), max(sizeBits, x.sizeBits), echoFields = BundleField.union(echoFields ++ x.echoFields), requestFields = BundleField.union(requestFields ++ x.requestFields), responseFields = BundleField.union(responseFields ++ x.responseFields), hasBCE || x.hasBCE) } object TLBundleParameters { val emptyBundleParams = TLBundleParameters( addressBits = 1, dataBits = 8, sourceBits = 1, sinkBits = 1, sizeBits = 1, echoFields = Nil, requestFields = Nil, responseFields = Nil, hasBCE = false) def union(x: Seq[TLBundleParameters]) = x.foldLeft(emptyBundleParams)((x,y) => x.union(y)) def apply(master: TLMasterPortParameters, slave: TLSlavePortParameters) = new TLBundleParameters( addressBits = log2Up(slave.maxAddress + 1), dataBits = slave.beatBytes * 8, sourceBits = log2Up(master.endSourceId), sinkBits = log2Up(slave.endSinkId), sizeBits = log2Up(log2Ceil(max(master.maxTransfer, slave.maxTransfer))+1), echoFields = master.echoFields, requestFields = BundleField.accept(master.requestFields, slave.requestKeys), responseFields = BundleField.accept(slave.responseFields, master.responseKeys), hasBCE = master.anySupportProbe && slave.anySupportAcquireB) } case class TLEdgeParameters( master: TLMasterPortParameters, slave: TLSlavePortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge { // legacy names: def manager = slave def client = master val maxTransfer = max(master.maxTransfer, slave.maxTransfer) val maxLgSize = log2Ceil(maxTransfer) // Sanity check the link... require (maxTransfer >= slave.beatBytes, s"Link's max transfer (${maxTransfer}) < ${slave.slaves.map(_.name)}'s beatBytes (${slave.beatBytes})") def diplomaticClaimsMasterToSlave = master.anyEmitClaims.intersect(slave.anySupportClaims) val bundle = TLBundleParameters(master, slave) def formatEdge = master.infoString + "\n" + slave.infoString } case class TLCreditedDelay( a: CreditedDelay, b: CreditedDelay, c: CreditedDelay, d: CreditedDelay, e: CreditedDelay) { def + (that: TLCreditedDelay): TLCreditedDelay = TLCreditedDelay( a = a + that.a, b = b + that.b, c = c + that.c, d = d + that.d, e = e + that.e) override def toString = s"(${a}, ${b}, ${c}, ${d}, ${e})" } object TLCreditedDelay { def apply(delay: CreditedDelay): TLCreditedDelay = apply(delay, delay.flip, delay, delay.flip, delay) } case class TLCreditedManagerPortParameters(delay: TLCreditedDelay, base: TLSlavePortParameters) {def infoString = base.infoString} case class TLCreditedClientPortParameters(delay: TLCreditedDelay, base: TLMasterPortParameters) {def infoString = base.infoString} case class TLCreditedEdgeParameters(client: TLCreditedClientPortParameters, manager: TLCreditedManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge { val delay = client.delay + manager.delay val bundle = TLBundleParameters(client.base, manager.base) def formatEdge = client.infoString + "\n" + manager.infoString } case class TLAsyncManagerPortParameters(async: AsyncQueueParams, base: TLSlavePortParameters) {def infoString = base.infoString} case class TLAsyncClientPortParameters(base: TLMasterPortParameters) {def infoString = base.infoString} case class TLAsyncBundleParameters(async: AsyncQueueParams, base: TLBundleParameters) case class TLAsyncEdgeParameters(client: TLAsyncClientPortParameters, manager: TLAsyncManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge { val bundle = TLAsyncBundleParameters(manager.async, TLBundleParameters(client.base, manager.base)) def formatEdge = client.infoString + "\n" + manager.infoString } case class TLRationalManagerPortParameters(direction: RationalDirection, base: TLSlavePortParameters) {def infoString = base.infoString} case class TLRationalClientPortParameters(base: TLMasterPortParameters) {def infoString = base.infoString} case class TLRationalEdgeParameters(client: TLRationalClientPortParameters, manager: TLRationalManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge { val bundle = TLBundleParameters(client.base, manager.base) def formatEdge = client.infoString + "\n" + manager.infoString } // To be unified, devices must agree on all of these terms case class ManagerUnificationKey( resources: Seq[Resource], regionType: RegionType.T, executable: Boolean, supportsAcquireT: TransferSizes, supportsAcquireB: TransferSizes, supportsArithmetic: TransferSizes, supportsLogical: TransferSizes, supportsGet: TransferSizes, supportsPutFull: TransferSizes, supportsPutPartial: TransferSizes, supportsHint: TransferSizes) object ManagerUnificationKey { def apply(x: TLSlaveParameters): ManagerUnificationKey = ManagerUnificationKey( resources = x.resources, regionType = x.regionType, executable = x.executable, supportsAcquireT = x.supportsAcquireT, supportsAcquireB = x.supportsAcquireB, supportsArithmetic = x.supportsArithmetic, supportsLogical = x.supportsLogical, supportsGet = x.supportsGet, supportsPutFull = x.supportsPutFull, supportsPutPartial = x.supportsPutPartial, supportsHint = x.supportsHint) } object ManagerUnification { def apply(slaves: Seq[TLSlaveParameters]): List[TLSlaveParameters] = { slaves.groupBy(ManagerUnificationKey.apply).values.map { seq => val agree = seq.forall(_.fifoId == seq.head.fifoId) seq(0).v1copy( address = AddressSet.unify(seq.flatMap(_.address)), fifoId = if (agree) seq(0).fifoId else None) }.toList } } case class TLBufferParams( a: BufferParams = BufferParams.none, b: BufferParams = BufferParams.none, c: BufferParams = BufferParams.none, d: BufferParams = BufferParams.none, e: BufferParams = BufferParams.none ) extends DirectedBuffers[TLBufferParams] { def copyIn(x: BufferParams) = this.copy(b = x, d = x) def copyOut(x: BufferParams) = this.copy(a = x, c = x, e = x) def copyInOut(x: BufferParams) = this.copyIn(x).copyOut(x) } /** Pretty printing of TL source id maps */ class TLSourceIdMap(tl: TLMasterPortParameters) extends IdMap[TLSourceIdMapEntry] { private val tlDigits = String.valueOf(tl.endSourceId-1).length() protected val fmt = s"\t[%${tlDigits}d, %${tlDigits}d) %s%s%s" private val sorted = tl.masters.sortBy(_.sourceId) val mapping: Seq[TLSourceIdMapEntry] = sorted.map { case c => TLSourceIdMapEntry(c.sourceId, c.name, c.supports.probe, c.requestFifo) } } case class TLSourceIdMapEntry(tlId: IdRange, name: String, isCache: Boolean, requestFifo: Boolean) extends IdMapEntry { val from = tlId val to = tlId val maxTransactionsInFlight = Some(tlId.size) } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) || !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.ProbeAckData || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode | small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U || beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }

module TLMonitor_42( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input io_in_a_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [511:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input [511:0] io_in_d_bits_data, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [31:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [511:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7] wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7] wire [511:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_bits_source = 1'h0; // @[Monitor.scala:36:7] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire c_set = 1'h0; // @[Monitor.scala:738:34] wire c_set_wo_ready = 1'h0; // @[Monitor.scala:739:34] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire _source_ok_T_1 = 1'h1; // @[Parameters.scala:46:9] wire _source_ok_WIRE_1_0 = 1'h1; // @[Parameters.scala:1138:31] wire sink_ok = 1'h1; // @[Monitor.scala:309:31] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire _same_cycle_resp_T_8 = 1'h1; // @[Monitor.scala:795:113] wire [5:0] c_first_beats1_decode = 6'h0; // @[Edges.scala:220:59] wire [5:0] c_first_beats1 = 6'h0; // @[Edges.scala:221:14] wire [5:0] _c_first_count_T = 6'h0; // @[Edges.scala:234:27] wire [5:0] c_first_count = 6'h0; // @[Edges.scala:234:25] wire [5:0] _c_first_counter_T = 6'h0; // @[Edges.scala:236:21] wire [5:0] c_first_counter1 = 6'h3F; // @[Edges.scala:230:28] wire [6:0] _c_first_counter1_T = 7'h7F; // @[Edges.scala:230:28] wire [511:0] _c_first_WIRE_bits_data = 512'h0; // @[Bundles.scala:265:74] wire [511:0] _c_first_WIRE_1_bits_data = 512'h0; // @[Bundles.scala:265:61] wire [511:0] _c_first_WIRE_2_bits_data = 512'h0; // @[Bundles.scala:265:74] wire [511:0] _c_first_WIRE_3_bits_data = 512'h0; // @[Bundles.scala:265:61] wire [511:0] _c_set_wo_ready_WIRE_bits_data = 512'h0; // @[Bundles.scala:265:74] wire [511:0] _c_set_wo_ready_WIRE_1_bits_data = 512'h0; // @[Bundles.scala:265:61] wire [511:0] _c_set_WIRE_bits_data = 512'h0; // @[Bundles.scala:265:74] wire [511:0] _c_set_WIRE_1_bits_data = 512'h0; // @[Bundles.scala:265:61] wire [511:0] _c_opcodes_set_interm_WIRE_bits_data = 512'h0; // @[Bundles.scala:265:74] wire [511:0] _c_opcodes_set_interm_WIRE_1_bits_data = 512'h0; // @[Bundles.scala:265:61] wire [511:0] _c_sizes_set_interm_WIRE_bits_data = 512'h0; // @[Bundles.scala:265:74] wire [511:0] _c_sizes_set_interm_WIRE_1_bits_data = 512'h0; // @[Bundles.scala:265:61] wire [511:0] _c_opcodes_set_WIRE_bits_data = 512'h0; // @[Bundles.scala:265:74] wire [511:0] _c_opcodes_set_WIRE_1_bits_data = 512'h0; // @[Bundles.scala:265:61] wire [511:0] _c_sizes_set_WIRE_bits_data = 512'h0; // @[Bundles.scala:265:74] wire [511:0] _c_sizes_set_WIRE_1_bits_data = 512'h0; // @[Bundles.scala:265:61] wire [511:0] _c_probe_ack_WIRE_bits_data = 512'h0; // @[Bundles.scala:265:74] wire [511:0] _c_probe_ack_WIRE_1_bits_data = 512'h0; // @[Bundles.scala:265:61] wire [511:0] _c_probe_ack_WIRE_2_bits_data = 512'h0; // @[Bundles.scala:265:74] wire [511:0] _c_probe_ack_WIRE_3_bits_data = 512'h0; // @[Bundles.scala:265:61] wire [511:0] _same_cycle_resp_WIRE_bits_data = 512'h0; // @[Bundles.scala:265:74] wire [511:0] _same_cycle_resp_WIRE_1_bits_data = 512'h0; // @[Bundles.scala:265:61] wire [511:0] _same_cycle_resp_WIRE_2_bits_data = 512'h0; // @[Bundles.scala:265:74] wire [511:0] _same_cycle_resp_WIRE_3_bits_data = 512'h0; // @[Bundles.scala:265:61] wire [511:0] _same_cycle_resp_WIRE_4_bits_data = 512'h0; // @[Bundles.scala:265:74] wire [511:0] _same_cycle_resp_WIRE_5_bits_data = 512'h0; // @[Bundles.scala:265:61] wire [31:0] _c_first_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_first_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_wo_ready_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_wo_ready_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_4_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_5_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [3:0] _a_opcode_lookup_T = 4'h0; // @[Monitor.scala:637:69] wire [3:0] _a_size_lookup_T = 4'h0; // @[Monitor.scala:641:65] wire [3:0] _d_opcodes_clr_T_4 = 4'h0; // @[Monitor.scala:680:101] wire [3:0] _d_sizes_clr_T_4 = 4'h0; // @[Monitor.scala:681:99] wire [3:0] _c_first_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] c_opcodes_set = 4'h0; // @[Monitor.scala:740:34] wire [3:0] _c_opcode_lookup_T = 4'h0; // @[Monitor.scala:749:69] wire [3:0] _c_size_lookup_T = 4'h0; // @[Monitor.scala:750:67] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] _c_set_wo_ready_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_wo_ready_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_sizes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_T = 4'h0; // @[Monitor.scala:767:79] wire [3:0] _c_sizes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_sizes_set_T = 4'h0; // @[Monitor.scala:768:77] wire [3:0] _c_probe_ack_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _d_opcodes_clr_T_10 = 4'h0; // @[Monitor.scala:790:101] wire [3:0] _d_sizes_clr_T_10 = 4'h0; // @[Monitor.scala:791:99] wire [3:0] _same_cycle_resp_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_4_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_5_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [30:0] _d_sizes_clr_T_5 = 31'hFF; // @[Monitor.scala:681:74] wire [30:0] _d_sizes_clr_T_11 = 31'hFF; // @[Monitor.scala:791:74] wire [15:0] _a_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _c_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hFF; // @[Monitor.scala:724:57] wire [16:0] _a_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _c_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hFF; // @[Monitor.scala:724:57] wire [15:0] _a_size_lookup_T_3 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _c_size_lookup_T_3 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h100; // @[Monitor.scala:724:51] wire [30:0] _d_opcodes_clr_T_5 = 31'hF; // @[Monitor.scala:680:76] wire [30:0] _d_opcodes_clr_T_11 = 31'hF; // @[Monitor.scala:790:76] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [1:0] _d_clr_wo_ready_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _d_clr_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _c_set_wo_ready_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _c_set_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _d_clr_wo_ready_T_1 = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _d_clr_T_1 = 2'h1; // @[OneHot.scala:58:35] wire [19:0] _c_sizes_set_T_1 = 20'h0; // @[Monitor.scala:768:52] wire [18:0] _c_opcodes_set_T_1 = 19'h0; // @[Monitor.scala:767:54] wire [4:0] _c_sizes_set_interm_T_1 = 5'h1; // @[Monitor.scala:766:59] wire [4:0] c_sizes_set_interm = 5'h0; // @[Monitor.scala:755:40] wire [4:0] _c_sizes_set_interm_T = 5'h0; // @[Monitor.scala:766:51] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [7:0] c_sizes_set = 8'h0; // @[Monitor.scala:741:34] wire [11:0] _c_first_beats1_decode_T_2 = 12'h0; // @[package.scala:243:46] wire [11:0] _c_first_beats1_decode_T_1 = 12'hFFF; // @[package.scala:243:76] wire [26:0] _c_first_beats1_decode_T = 27'hFFF; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [3:0] _a_size_lookup_T_2 = 4'h8; // @[Monitor.scala:641:117] wire [3:0] _d_sizes_clr_T = 4'h8; // @[Monitor.scala:681:48] wire [3:0] _c_size_lookup_T_2 = 4'h8; // @[Monitor.scala:750:119] wire [3:0] _d_sizes_clr_T_6 = 4'h8; // @[Monitor.scala:791:48] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire _source_ok_T = ~io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31] wire [26:0] _GEN = 27'hFFF << io_in_a_bits_size_0; // @[package.scala:243:71] wire [26:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [11:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [31:0] _is_aligned_T = {20'h0, io_in_a_bits_address_0[11:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 32'h0; // @[Edges.scala:21:{16,24}] wire [5:0] _mask_sizeOH_T = {2'h0, io_in_a_bits_size_0}; // @[Misc.scala:202:34] wire [2:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[2:0]; // @[OneHot.scala:64:49] wire [7:0] _mask_sizeOH_T_1 = 8'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [5:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[5:0]; // @[OneHot.scala:65:{12,27}] wire [5:0] mask_sizeOH = {_mask_sizeOH_T_2[5:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 4'h5; // @[Misc.scala:206:21] wire mask_sub_sub_sub_sub_sub_size = mask_sizeOH[5]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_sub_sub_sub_bit = io_in_a_bits_address_0[5]; // @[Misc.scala:210:26] wire mask_sub_sub_sub_sub_sub_1_2 = mask_sub_sub_sub_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_sub_sub_sub_nbit = ~mask_sub_sub_sub_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_sub_sub_sub_0_2 = mask_sub_sub_sub_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_sub_sub_sub_acc_T = mask_sub_sub_sub_sub_sub_size & mask_sub_sub_sub_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_sub_sub_sub_0_1 = mask_sub_sub_sub_sub_sub_sub_0_1 | _mask_sub_sub_sub_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_sub_sub_sub_acc_T_1 = mask_sub_sub_sub_sub_sub_size & mask_sub_sub_sub_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_sub_sub_sub_1_1 = mask_sub_sub_sub_sub_sub_sub_0_1 | _mask_sub_sub_sub_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_sub_sub_sub_size = mask_sizeOH[4]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_sub_sub_bit = io_in_a_bits_address_0[4]; // @[Misc.scala:210:26] wire mask_sub_sub_sub_sub_nbit = ~mask_sub_sub_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_sub_sub_0_2 = mask_sub_sub_sub_sub_sub_0_2 & mask_sub_sub_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_sub_sub_acc_T = mask_sub_sub_sub_sub_size & mask_sub_sub_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_sub_sub_0_1 = mask_sub_sub_sub_sub_sub_0_1 | _mask_sub_sub_sub_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_sub_sub_1_2 = mask_sub_sub_sub_sub_sub_0_2 & mask_sub_sub_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_sub_sub_sub_acc_T_1 = mask_sub_sub_sub_sub_size & mask_sub_sub_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_sub_sub_1_1 = mask_sub_sub_sub_sub_sub_0_1 | _mask_sub_sub_sub_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_sub_sub_2_2 = mask_sub_sub_sub_sub_sub_1_2 & mask_sub_sub_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_sub_sub_acc_T_2 = mask_sub_sub_sub_sub_size & mask_sub_sub_sub_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_sub_sub_2_1 = mask_sub_sub_sub_sub_sub_1_1 | _mask_sub_sub_sub_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_sub_sub_3_2 = mask_sub_sub_sub_sub_sub_1_2 & mask_sub_sub_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_sub_sub_sub_acc_T_3 = mask_sub_sub_sub_sub_size & mask_sub_sub_sub_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_sub_sub_3_1 = mask_sub_sub_sub_sub_sub_1_1 | _mask_sub_sub_sub_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_sub_size = mask_sizeOH[3]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_sub_bit = io_in_a_bits_address_0[3]; // @[Misc.scala:210:26] wire mask_sub_sub_sub_nbit = ~mask_sub_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_sub_0_2 = mask_sub_sub_sub_sub_0_2 & mask_sub_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_sub_acc_T = mask_sub_sub_sub_size & mask_sub_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_sub_0_1 = mask_sub_sub_sub_sub_0_1 | _mask_sub_sub_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_sub_1_2 = mask_sub_sub_sub_sub_0_2 & mask_sub_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_sub_sub_acc_T_1 = mask_sub_sub_sub_size & mask_sub_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_sub_1_1 = mask_sub_sub_sub_sub_0_1 | _mask_sub_sub_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_sub_2_2 = mask_sub_sub_sub_sub_1_2 & mask_sub_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_sub_acc_T_2 = mask_sub_sub_sub_size & mask_sub_sub_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_sub_2_1 = mask_sub_sub_sub_sub_1_1 | _mask_sub_sub_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_sub_3_2 = mask_sub_sub_sub_sub_1_2 & mask_sub_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_sub_sub_acc_T_3 = mask_sub_sub_sub_size & mask_sub_sub_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_sub_3_1 = mask_sub_sub_sub_sub_1_1 | _mask_sub_sub_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_sub_4_2 = mask_sub_sub_sub_sub_2_2 & mask_sub_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_sub_acc_T_4 = mask_sub_sub_sub_size & mask_sub_sub_sub_4_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_sub_4_1 = mask_sub_sub_sub_sub_2_1 | _mask_sub_sub_sub_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_sub_5_2 = mask_sub_sub_sub_sub_2_2 & mask_sub_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_sub_sub_acc_T_5 = mask_sub_sub_sub_size & mask_sub_sub_sub_5_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_sub_5_1 = mask_sub_sub_sub_sub_2_1 | _mask_sub_sub_sub_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_sub_6_2 = mask_sub_sub_sub_sub_3_2 & mask_sub_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_sub_acc_T_6 = mask_sub_sub_sub_size & mask_sub_sub_sub_6_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_sub_6_1 = mask_sub_sub_sub_sub_3_1 | _mask_sub_sub_sub_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_sub_7_2 = mask_sub_sub_sub_sub_3_2 & mask_sub_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_sub_sub_acc_T_7 = mask_sub_sub_sub_size & mask_sub_sub_sub_7_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_sub_7_1 = mask_sub_sub_sub_sub_3_1 | _mask_sub_sub_sub_acc_T_7; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_sub_0_2 & mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_1_2 = mask_sub_sub_sub_0_2 & mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_2_2 = mask_sub_sub_sub_1_2 & mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T_2 = mask_sub_sub_size & mask_sub_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_2_1 = mask_sub_sub_sub_1_1 | _mask_sub_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_3_2 = mask_sub_sub_sub_1_2 & mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_sub_acc_T_3 = mask_sub_sub_size & mask_sub_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_3_1 = mask_sub_sub_sub_1_1 | _mask_sub_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_4_2 = mask_sub_sub_sub_2_2 & mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T_4 = mask_sub_sub_size & mask_sub_sub_4_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_4_1 = mask_sub_sub_sub_2_1 | _mask_sub_sub_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_5_2 = mask_sub_sub_sub_2_2 & mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_sub_acc_T_5 = mask_sub_sub_size & mask_sub_sub_5_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_5_1 = mask_sub_sub_sub_2_1 | _mask_sub_sub_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_6_2 = mask_sub_sub_sub_3_2 & mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T_6 = mask_sub_sub_size & mask_sub_sub_6_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_6_1 = mask_sub_sub_sub_3_1 | _mask_sub_sub_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_7_2 = mask_sub_sub_sub_3_2 & mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_sub_acc_T_7 = mask_sub_sub_size & mask_sub_sub_7_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_7_1 = mask_sub_sub_sub_3_1 | _mask_sub_sub_acc_T_7; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_8_2 = mask_sub_sub_sub_4_2 & mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T_8 = mask_sub_sub_size & mask_sub_sub_8_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_8_1 = mask_sub_sub_sub_4_1 | _mask_sub_sub_acc_T_8; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_9_2 = mask_sub_sub_sub_4_2 & mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_sub_acc_T_9 = mask_sub_sub_size & mask_sub_sub_9_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_9_1 = mask_sub_sub_sub_4_1 | _mask_sub_sub_acc_T_9; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_10_2 = mask_sub_sub_sub_5_2 & mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T_10 = mask_sub_sub_size & mask_sub_sub_10_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_10_1 = mask_sub_sub_sub_5_1 | _mask_sub_sub_acc_T_10; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_11_2 = mask_sub_sub_sub_5_2 & mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_sub_acc_T_11 = mask_sub_sub_size & mask_sub_sub_11_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_11_1 = mask_sub_sub_sub_5_1 | _mask_sub_sub_acc_T_11; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_12_2 = mask_sub_sub_sub_6_2 & mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T_12 = mask_sub_sub_size & mask_sub_sub_12_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_12_1 = mask_sub_sub_sub_6_1 | _mask_sub_sub_acc_T_12; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_13_2 = mask_sub_sub_sub_6_2 & mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_sub_acc_T_13 = mask_sub_sub_size & mask_sub_sub_13_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_13_1 = mask_sub_sub_sub_6_1 | _mask_sub_sub_acc_T_13; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_14_2 = mask_sub_sub_sub_7_2 & mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T_14 = mask_sub_sub_size & mask_sub_sub_14_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_14_1 = mask_sub_sub_sub_7_1 | _mask_sub_sub_acc_T_14; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_15_2 = mask_sub_sub_sub_7_2 & mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_sub_acc_T_15 = mask_sub_sub_size & mask_sub_sub_15_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_15_1 = mask_sub_sub_sub_7_1 | _mask_sub_sub_acc_T_15; // @[Misc.scala:215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_sub_4_2 = mask_sub_sub_2_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_4 = mask_sub_size & mask_sub_4_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_4_1 = mask_sub_sub_2_1 | _mask_sub_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_sub_5_2 = mask_sub_sub_2_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_5 = mask_sub_size & mask_sub_5_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_5_1 = mask_sub_sub_2_1 | _mask_sub_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_sub_6_2 = mask_sub_sub_3_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_6 = mask_sub_size & mask_sub_6_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_6_1 = mask_sub_sub_3_1 | _mask_sub_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_sub_7_2 = mask_sub_sub_3_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_7 = mask_sub_size & mask_sub_7_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_7_1 = mask_sub_sub_3_1 | _mask_sub_acc_T_7; // @[Misc.scala:215:{29,38}] wire mask_sub_8_2 = mask_sub_sub_4_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_8 = mask_sub_size & mask_sub_8_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_8_1 = mask_sub_sub_4_1 | _mask_sub_acc_T_8; // @[Misc.scala:215:{29,38}] wire mask_sub_9_2 = mask_sub_sub_4_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_9 = mask_sub_size & mask_sub_9_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_9_1 = mask_sub_sub_4_1 | _mask_sub_acc_T_9; // @[Misc.scala:215:{29,38}] wire mask_sub_10_2 = mask_sub_sub_5_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_10 = mask_sub_size & mask_sub_10_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_10_1 = mask_sub_sub_5_1 | _mask_sub_acc_T_10; // @[Misc.scala:215:{29,38}] wire mask_sub_11_2 = mask_sub_sub_5_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_11 = mask_sub_size & mask_sub_11_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_11_1 = mask_sub_sub_5_1 | _mask_sub_acc_T_11; // @[Misc.scala:215:{29,38}] wire mask_sub_12_2 = mask_sub_sub_6_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_12 = mask_sub_size & mask_sub_12_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_12_1 = mask_sub_sub_6_1 | _mask_sub_acc_T_12; // @[Misc.scala:215:{29,38}] wire mask_sub_13_2 = mask_sub_sub_6_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_13 = mask_sub_size & mask_sub_13_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_13_1 = mask_sub_sub_6_1 | _mask_sub_acc_T_13; // @[Misc.scala:215:{29,38}] wire mask_sub_14_2 = mask_sub_sub_7_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_14 = mask_sub_size & mask_sub_14_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_14_1 = mask_sub_sub_7_1 | _mask_sub_acc_T_14; // @[Misc.scala:215:{29,38}] wire mask_sub_15_2 = mask_sub_sub_7_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_15 = mask_sub_size & mask_sub_15_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_15_1 = mask_sub_sub_7_1 | _mask_sub_acc_T_15; // @[Misc.scala:215:{29,38}] wire mask_sub_16_2 = mask_sub_sub_8_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_16 = mask_sub_size & mask_sub_16_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_16_1 = mask_sub_sub_8_1 | _mask_sub_acc_T_16; // @[Misc.scala:215:{29,38}] wire mask_sub_17_2 = mask_sub_sub_8_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_17 = mask_sub_size & mask_sub_17_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_17_1 = mask_sub_sub_8_1 | _mask_sub_acc_T_17; // @[Misc.scala:215:{29,38}] wire mask_sub_18_2 = mask_sub_sub_9_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_18 = mask_sub_size & mask_sub_18_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_18_1 = mask_sub_sub_9_1 | _mask_sub_acc_T_18; // @[Misc.scala:215:{29,38}] wire mask_sub_19_2 = mask_sub_sub_9_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_19 = mask_sub_size & mask_sub_19_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_19_1 = mask_sub_sub_9_1 | _mask_sub_acc_T_19; // @[Misc.scala:215:{29,38}] wire mask_sub_20_2 = mask_sub_sub_10_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_20 = mask_sub_size & mask_sub_20_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_20_1 = mask_sub_sub_10_1 | _mask_sub_acc_T_20; // @[Misc.scala:215:{29,38}] wire mask_sub_21_2 = mask_sub_sub_10_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_21 = mask_sub_size & mask_sub_21_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_21_1 = mask_sub_sub_10_1 | _mask_sub_acc_T_21; // @[Misc.scala:215:{29,38}] wire mask_sub_22_2 = mask_sub_sub_11_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_22 = mask_sub_size & mask_sub_22_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_22_1 = mask_sub_sub_11_1 | _mask_sub_acc_T_22; // @[Misc.scala:215:{29,38}] wire mask_sub_23_2 = mask_sub_sub_11_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_23 = mask_sub_size & mask_sub_23_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_23_1 = mask_sub_sub_11_1 | _mask_sub_acc_T_23; // @[Misc.scala:215:{29,38}] wire mask_sub_24_2 = mask_sub_sub_12_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_24 = mask_sub_size & mask_sub_24_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_24_1 = mask_sub_sub_12_1 | _mask_sub_acc_T_24; // @[Misc.scala:215:{29,38}] wire mask_sub_25_2 = mask_sub_sub_12_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_25 = mask_sub_size & mask_sub_25_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_25_1 = mask_sub_sub_12_1 | _mask_sub_acc_T_25; // @[Misc.scala:215:{29,38}] wire mask_sub_26_2 = mask_sub_sub_13_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_26 = mask_sub_size & mask_sub_26_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_26_1 = mask_sub_sub_13_1 | _mask_sub_acc_T_26; // @[Misc.scala:215:{29,38}] wire mask_sub_27_2 = mask_sub_sub_13_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_27 = mask_sub_size & mask_sub_27_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_27_1 = mask_sub_sub_13_1 | _mask_sub_acc_T_27; // @[Misc.scala:215:{29,38}] wire mask_sub_28_2 = mask_sub_sub_14_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_28 = mask_sub_size & mask_sub_28_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_28_1 = mask_sub_sub_14_1 | _mask_sub_acc_T_28; // @[Misc.scala:215:{29,38}] wire mask_sub_29_2 = mask_sub_sub_14_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_29 = mask_sub_size & mask_sub_29_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_29_1 = mask_sub_sub_14_1 | _mask_sub_acc_T_29; // @[Misc.scala:215:{29,38}] wire mask_sub_30_2 = mask_sub_sub_15_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_30 = mask_sub_size & mask_sub_30_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_30_1 = mask_sub_sub_15_1 | _mask_sub_acc_T_30; // @[Misc.scala:215:{29,38}] wire mask_sub_31_2 = mask_sub_sub_15_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_31 = mask_sub_size & mask_sub_31_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_31_1 = mask_sub_sub_15_1 | _mask_sub_acc_T_31; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire mask_eq_8 = mask_sub_4_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_8 = mask_size & mask_eq_8; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_8 = mask_sub_4_1 | _mask_acc_T_8; // @[Misc.scala:215:{29,38}] wire mask_eq_9 = mask_sub_4_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_9 = mask_size & mask_eq_9; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_9 = mask_sub_4_1 | _mask_acc_T_9; // @[Misc.scala:215:{29,38}] wire mask_eq_10 = mask_sub_5_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_10 = mask_size & mask_eq_10; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_10 = mask_sub_5_1 | _mask_acc_T_10; // @[Misc.scala:215:{29,38}] wire mask_eq_11 = mask_sub_5_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_11 = mask_size & mask_eq_11; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_11 = mask_sub_5_1 | _mask_acc_T_11; // @[Misc.scala:215:{29,38}] wire mask_eq_12 = mask_sub_6_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_12 = mask_size & mask_eq_12; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_12 = mask_sub_6_1 | _mask_acc_T_12; // @[Misc.scala:215:{29,38}] wire mask_eq_13 = mask_sub_6_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_13 = mask_size & mask_eq_13; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_13 = mask_sub_6_1 | _mask_acc_T_13; // @[Misc.scala:215:{29,38}] wire mask_eq_14 = mask_sub_7_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_14 = mask_size & mask_eq_14; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_14 = mask_sub_7_1 | _mask_acc_T_14; // @[Misc.scala:215:{29,38}] wire mask_eq_15 = mask_sub_7_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_15 = mask_size & mask_eq_15; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_15 = mask_sub_7_1 | _mask_acc_T_15; // @[Misc.scala:215:{29,38}] wire mask_eq_16 = mask_sub_8_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_16 = mask_size & mask_eq_16; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_16 = mask_sub_8_1 | _mask_acc_T_16; // @[Misc.scala:215:{29,38}] wire mask_eq_17 = mask_sub_8_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_17 = mask_size & mask_eq_17; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_17 = mask_sub_8_1 | _mask_acc_T_17; // @[Misc.scala:215:{29,38}] wire mask_eq_18 = mask_sub_9_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_18 = mask_size & mask_eq_18; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_18 = mask_sub_9_1 | _mask_acc_T_18; // @[Misc.scala:215:{29,38}] wire mask_eq_19 = mask_sub_9_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_19 = mask_size & mask_eq_19; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_19 = mask_sub_9_1 | _mask_acc_T_19; // @[Misc.scala:215:{29,38}] wire mask_eq_20 = mask_sub_10_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_20 = mask_size & mask_eq_20; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_20 = mask_sub_10_1 | _mask_acc_T_20; // @[Misc.scala:215:{29,38}] wire mask_eq_21 = mask_sub_10_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_21 = mask_size & mask_eq_21; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_21 = mask_sub_10_1 | _mask_acc_T_21; // @[Misc.scala:215:{29,38}] wire mask_eq_22 = mask_sub_11_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_22 = mask_size & mask_eq_22; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_22 = mask_sub_11_1 | _mask_acc_T_22; // @[Misc.scala:215:{29,38}] wire mask_eq_23 = mask_sub_11_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_23 = mask_size & mask_eq_23; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_23 = mask_sub_11_1 | _mask_acc_T_23; // @[Misc.scala:215:{29,38}] wire mask_eq_24 = mask_sub_12_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_24 = mask_size & mask_eq_24; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_24 = mask_sub_12_1 | _mask_acc_T_24; // @[Misc.scala:215:{29,38}] wire mask_eq_25 = mask_sub_12_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_25 = mask_size & mask_eq_25; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_25 = mask_sub_12_1 | _mask_acc_T_25; // @[Misc.scala:215:{29,38}] wire mask_eq_26 = mask_sub_13_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_26 = mask_size & mask_eq_26; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_26 = mask_sub_13_1 | _mask_acc_T_26; // @[Misc.scala:215:{29,38}] wire mask_eq_27 = mask_sub_13_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_27 = mask_size & mask_eq_27; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_27 = mask_sub_13_1 | _mask_acc_T_27; // @[Misc.scala:215:{29,38}] wire mask_eq_28 = mask_sub_14_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_28 = mask_size & mask_eq_28; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_28 = mask_sub_14_1 | _mask_acc_T_28; // @[Misc.scala:215:{29,38}] wire mask_eq_29 = mask_sub_14_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_29 = mask_size & mask_eq_29; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_29 = mask_sub_14_1 | _mask_acc_T_29; // @[Misc.scala:215:{29,38}] wire mask_eq_30 = mask_sub_15_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_30 = mask_size & mask_eq_30; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_30 = mask_sub_15_1 | _mask_acc_T_30; // @[Misc.scala:215:{29,38}] wire mask_eq_31 = mask_sub_15_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_31 = mask_size & mask_eq_31; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_31 = mask_sub_15_1 | _mask_acc_T_31; // @[Misc.scala:215:{29,38}] wire mask_eq_32 = mask_sub_16_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_32 = mask_size & mask_eq_32; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_32 = mask_sub_16_1 | _mask_acc_T_32; // @[Misc.scala:215:{29,38}] wire mask_eq_33 = mask_sub_16_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_33 = mask_size & mask_eq_33; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_33 = mask_sub_16_1 | _mask_acc_T_33; // @[Misc.scala:215:{29,38}] wire mask_eq_34 = mask_sub_17_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_34 = mask_size & mask_eq_34; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_34 = mask_sub_17_1 | _mask_acc_T_34; // @[Misc.scala:215:{29,38}] wire mask_eq_35 = mask_sub_17_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_35 = mask_size & mask_eq_35; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_35 = mask_sub_17_1 | _mask_acc_T_35; // @[Misc.scala:215:{29,38}] wire mask_eq_36 = mask_sub_18_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_36 = mask_size & mask_eq_36; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_36 = mask_sub_18_1 | _mask_acc_T_36; // @[Misc.scala:215:{29,38}] wire mask_eq_37 = mask_sub_18_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_37 = mask_size & mask_eq_37; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_37 = mask_sub_18_1 | _mask_acc_T_37; // @[Misc.scala:215:{29,38}] wire mask_eq_38 = mask_sub_19_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_38 = mask_size & mask_eq_38; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_38 = mask_sub_19_1 | _mask_acc_T_38; // @[Misc.scala:215:{29,38}] wire mask_eq_39 = mask_sub_19_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_39 = mask_size & mask_eq_39; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_39 = mask_sub_19_1 | _mask_acc_T_39; // @[Misc.scala:215:{29,38}] wire mask_eq_40 = mask_sub_20_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_40 = mask_size & mask_eq_40; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_40 = mask_sub_20_1 | _mask_acc_T_40; // @[Misc.scala:215:{29,38}] wire mask_eq_41 = mask_sub_20_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_41 = mask_size & mask_eq_41; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_41 = mask_sub_20_1 | _mask_acc_T_41; // @[Misc.scala:215:{29,38}] wire mask_eq_42 = mask_sub_21_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_42 = mask_size & mask_eq_42; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_42 = mask_sub_21_1 | _mask_acc_T_42; // @[Misc.scala:215:{29,38}] wire mask_eq_43 = mask_sub_21_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_43 = mask_size & mask_eq_43; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_43 = mask_sub_21_1 | _mask_acc_T_43; // @[Misc.scala:215:{29,38}] wire mask_eq_44 = mask_sub_22_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_44 = mask_size & mask_eq_44; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_44 = mask_sub_22_1 | _mask_acc_T_44; // @[Misc.scala:215:{29,38}] wire mask_eq_45 = mask_sub_22_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_45 = mask_size & mask_eq_45; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_45 = mask_sub_22_1 | _mask_acc_T_45; // @[Misc.scala:215:{29,38}] wire mask_eq_46 = mask_sub_23_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_46 = mask_size & mask_eq_46; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_46 = mask_sub_23_1 | _mask_acc_T_46; // @[Misc.scala:215:{29,38}] wire mask_eq_47 = mask_sub_23_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_47 = mask_size & mask_eq_47; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_47 = mask_sub_23_1 | _mask_acc_T_47; // @[Misc.scala:215:{29,38}] wire mask_eq_48 = mask_sub_24_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_48 = mask_size & mask_eq_48; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_48 = mask_sub_24_1 | _mask_acc_T_48; // @[Misc.scala:215:{29,38}] wire mask_eq_49 = mask_sub_24_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_49 = mask_size & mask_eq_49; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_49 = mask_sub_24_1 | _mask_acc_T_49; // @[Misc.scala:215:{29,38}] wire mask_eq_50 = mask_sub_25_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_50 = mask_size & mask_eq_50; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_50 = mask_sub_25_1 | _mask_acc_T_50; // @[Misc.scala:215:{29,38}] wire mask_eq_51 = mask_sub_25_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_51 = mask_size & mask_eq_51; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_51 = mask_sub_25_1 | _mask_acc_T_51; // @[Misc.scala:215:{29,38}] wire mask_eq_52 = mask_sub_26_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_52 = mask_size & mask_eq_52; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_52 = mask_sub_26_1 | _mask_acc_T_52; // @[Misc.scala:215:{29,38}] wire mask_eq_53 = mask_sub_26_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_53 = mask_size & mask_eq_53; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_53 = mask_sub_26_1 | _mask_acc_T_53; // @[Misc.scala:215:{29,38}] wire mask_eq_54 = mask_sub_27_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_54 = mask_size & mask_eq_54; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_54 = mask_sub_27_1 | _mask_acc_T_54; // @[Misc.scala:215:{29,38}] wire mask_eq_55 = mask_sub_27_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_55 = mask_size & mask_eq_55; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_55 = mask_sub_27_1 | _mask_acc_T_55; // @[Misc.scala:215:{29,38}] wire mask_eq_56 = mask_sub_28_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_56 = mask_size & mask_eq_56; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_56 = mask_sub_28_1 | _mask_acc_T_56; // @[Misc.scala:215:{29,38}] wire mask_eq_57 = mask_sub_28_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_57 = mask_size & mask_eq_57; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_57 = mask_sub_28_1 | _mask_acc_T_57; // @[Misc.scala:215:{29,38}] wire mask_eq_58 = mask_sub_29_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_58 = mask_size & mask_eq_58; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_58 = mask_sub_29_1 | _mask_acc_T_58; // @[Misc.scala:215:{29,38}] wire mask_eq_59 = mask_sub_29_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_59 = mask_size & mask_eq_59; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_59 = mask_sub_29_1 | _mask_acc_T_59; // @[Misc.scala:215:{29,38}] wire mask_eq_60 = mask_sub_30_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_60 = mask_size & mask_eq_60; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_60 = mask_sub_30_1 | _mask_acc_T_60; // @[Misc.scala:215:{29,38}] wire mask_eq_61 = mask_sub_30_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_61 = mask_size & mask_eq_61; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_61 = mask_sub_30_1 | _mask_acc_T_61; // @[Misc.scala:215:{29,38}] wire mask_eq_62 = mask_sub_31_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_62 = mask_size & mask_eq_62; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_62 = mask_sub_31_1 | _mask_acc_T_62; // @[Misc.scala:215:{29,38}] wire mask_eq_63 = mask_sub_31_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_63 = mask_size & mask_eq_63; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_63 = mask_sub_31_1 | _mask_acc_T_63; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo_lo_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_lo_lo_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo_lo_lo_lo = {mask_lo_lo_lo_lo_hi, mask_lo_lo_lo_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_lo_lo_lo_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_lo_lo_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo_lo_lo_hi = {mask_lo_lo_lo_hi_hi, mask_lo_lo_lo_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask_lo_lo_lo = {mask_lo_lo_lo_hi, mask_lo_lo_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_lo_lo_hi_lo_lo = {mask_acc_9, mask_acc_8}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_lo_hi_lo_hi = {mask_acc_11, mask_acc_10}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo_lo_hi_lo = {mask_lo_lo_hi_lo_hi, mask_lo_lo_hi_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_lo_lo_hi_hi_lo = {mask_acc_13, mask_acc_12}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_lo_hi_hi_hi = {mask_acc_15, mask_acc_14}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo_lo_hi_hi = {mask_lo_lo_hi_hi_hi, mask_lo_lo_hi_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask_lo_lo_hi = {mask_lo_lo_hi_hi, mask_lo_lo_hi_lo}; // @[Misc.scala:222:10] wire [15:0] mask_lo_lo = {mask_lo_lo_hi, mask_lo_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_lo_hi_lo_lo_lo = {mask_acc_17, mask_acc_16}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi_lo_lo_hi = {mask_acc_19, mask_acc_18}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo_hi_lo_lo = {mask_lo_hi_lo_lo_hi, mask_lo_hi_lo_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_lo_hi_lo_hi_lo = {mask_acc_21, mask_acc_20}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi_lo_hi_hi = {mask_acc_23, mask_acc_22}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo_hi_lo_hi = {mask_lo_hi_lo_hi_hi, mask_lo_hi_lo_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask_lo_hi_lo = {mask_lo_hi_lo_hi, mask_lo_hi_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_lo_hi_hi_lo_lo = {mask_acc_25, mask_acc_24}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi_hi_lo_hi = {mask_acc_27, mask_acc_26}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo_hi_hi_lo = {mask_lo_hi_hi_lo_hi, mask_lo_hi_hi_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_lo_hi_hi_hi_lo = {mask_acc_29, mask_acc_28}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi_hi_hi_hi = {mask_acc_31, mask_acc_30}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo_hi_hi_hi = {mask_lo_hi_hi_hi_hi, mask_lo_hi_hi_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask_lo_hi_hi = {mask_lo_hi_hi_hi, mask_lo_hi_hi_lo}; // @[Misc.scala:222:10] wire [15:0] mask_lo_hi = {mask_lo_hi_hi, mask_lo_hi_lo}; // @[Misc.scala:222:10] wire [31:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo_lo_lo_lo = {mask_acc_33, mask_acc_32}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_lo_lo_lo_hi = {mask_acc_35, mask_acc_34}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi_lo_lo_lo = {mask_hi_lo_lo_lo_hi, mask_hi_lo_lo_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo_lo_hi_lo = {mask_acc_37, mask_acc_36}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_lo_lo_hi_hi = {mask_acc_39, mask_acc_38}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi_lo_lo_hi = {mask_hi_lo_lo_hi_hi, mask_hi_lo_lo_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask_hi_lo_lo = {mask_hi_lo_lo_hi, mask_hi_lo_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo_hi_lo_lo = {mask_acc_41, mask_acc_40}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_lo_hi_lo_hi = {mask_acc_43, mask_acc_42}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi_lo_hi_lo = {mask_hi_lo_hi_lo_hi, mask_hi_lo_hi_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo_hi_hi_lo = {mask_acc_45, mask_acc_44}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_lo_hi_hi_hi = {mask_acc_47, mask_acc_46}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi_lo_hi_hi = {mask_hi_lo_hi_hi_hi, mask_hi_lo_hi_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask_hi_lo_hi = {mask_hi_lo_hi_hi, mask_hi_lo_hi_lo}; // @[Misc.scala:222:10] wire [15:0] mask_hi_lo = {mask_hi_lo_hi, mask_hi_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_hi_lo_lo_lo = {mask_acc_49, mask_acc_48}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi_lo_lo_hi = {mask_acc_51, mask_acc_50}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi_hi_lo_lo = {mask_hi_hi_lo_lo_hi, mask_hi_hi_lo_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_hi_lo_hi_lo = {mask_acc_53, mask_acc_52}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi_lo_hi_hi = {mask_acc_55, mask_acc_54}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi_hi_lo_hi = {mask_hi_hi_lo_hi_hi, mask_hi_hi_lo_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask_hi_hi_lo = {mask_hi_hi_lo_hi, mask_hi_hi_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_hi_hi_lo_lo = {mask_acc_57, mask_acc_56}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi_hi_lo_hi = {mask_acc_59, mask_acc_58}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi_hi_hi_lo = {mask_hi_hi_hi_lo_hi, mask_hi_hi_hi_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_hi_hi_hi_lo = {mask_acc_61, mask_acc_60}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi_hi_hi_hi = {mask_acc_63, mask_acc_62}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi_hi_hi_hi = {mask_hi_hi_hi_hi_hi, mask_hi_hi_hi_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask_hi_hi_hi = {mask_hi_hi_hi_hi, mask_hi_hi_hi_lo}; // @[Misc.scala:222:10] wire [15:0] mask_hi_hi = {mask_hi_hi_hi, mask_hi_hi_lo}; // @[Misc.scala:222:10] wire [31:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [63:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire _T_1212 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_1212; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_1212; // @[Decoupled.scala:51:35] wire [11:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [5:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[11:6]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [5:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 6'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [5:0] a_first_counter; // @[Edges.scala:229:27] wire [6:0] _a_first_counter1_T = {1'h0, a_first_counter} - 7'h1; // @[Edges.scala:229:27, :230:28] wire [5:0] a_first_counter1 = _a_first_counter1_T[5:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 6'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 6'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 6'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [5:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [5:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [5:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [3:0] size; // @[Monitor.scala:389:22] reg source; // @[Monitor.scala:390:22] reg [31:0] address; // @[Monitor.scala:391:22] wire _T_1285 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_1285; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_1285; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_1285; // @[Decoupled.scala:51:35] wire [26:0] _GEN_0 = 27'hFFF << io_in_d_bits_size_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [11:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [5:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[11:6]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [5:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 6'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [5:0] d_first_counter; // @[Edges.scala:229:27] wire [6:0] _d_first_counter1_T = {1'h0, d_first_counter} - 7'h1; // @[Edges.scala:229:27, :230:28] wire [5:0] d_first_counter1 = _d_first_counter1_T[5:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 6'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 6'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 6'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [5:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [5:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [5:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [3:0] size_1; // @[Monitor.scala:540:22] reg [2:0] sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] reg [1:0] inflight; // @[Monitor.scala:614:27] reg [3:0] inflight_opcodes; // @[Monitor.scala:616:35] wire [3:0] _a_opcode_lookup_T_1 = inflight_opcodes; // @[Monitor.scala:616:35, :637:44] reg [7:0] inflight_sizes; // @[Monitor.scala:618:33] wire [7:0] _a_size_lookup_T_1 = inflight_sizes; // @[Monitor.scala:618:33, :641:40] wire [11:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [5:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[11:6]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [5:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 6'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [5:0] a_first_counter_1; // @[Edges.scala:229:27] wire [6:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 7'h1; // @[Edges.scala:229:27, :230:28] wire [5:0] a_first_counter1_1 = _a_first_counter1_T_1[5:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 6'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 6'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 6'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [5:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [5:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [5:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [11:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [5:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[11:6]; // @[package.scala:243:46] wire [5:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 6'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [5:0] d_first_counter_1; // @[Edges.scala:229:27] wire [6:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 7'h1; // @[Edges.scala:229:27, :230:28] wire [5:0] d_first_counter1_1 = _d_first_counter1_T_1[5:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 6'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 6'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 6'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [5:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [5:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [5:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire a_set; // @[Monitor.scala:626:34] wire a_set_wo_ready; // @[Monitor.scala:627:34] wire [3:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [7:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [15:0] _a_opcode_lookup_T_6 = {12'h0, _a_opcode_lookup_T_1}; // @[Monitor.scala:637:{44,97}] wire [15:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [7:0] a_size_lookup; // @[Monitor.scala:639:33] wire [15:0] _a_size_lookup_T_6 = {8'h0, _a_size_lookup_T_1}; // @[Monitor.scala:641:{40,91}] wire [15:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[15:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[7:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [4:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [1:0] _GEN_1 = {1'h0, io_in_a_bits_source_0}; // @[OneHot.scala:58:35] wire [1:0] _GEN_2 = 2'h1 << _GEN_1; // @[OneHot.scala:58:35] wire [1:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_2; // @[OneHot.scala:58:35] wire [1:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_2; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T & _a_set_wo_ready_T[0]; // @[OneHot.scala:58:35] wire _T_1138 = _T_1212 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_1138 & _a_set_T[0]; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_1138 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [4:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [4:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_1138 ? _a_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [3:0] _a_opcodes_set_T = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [18:0] _a_opcodes_set_T_1 = {15'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_1138 ? _a_opcodes_set_T_1[3:0] : 4'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [3:0] _a_sizes_set_T = {io_in_a_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :660:77] wire [19:0] _a_sizes_set_T_1 = {15'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :660:{52,77}] assign a_sizes_set = _T_1138 ? _a_sizes_set_T_1[7:0] : 8'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire d_clr; // @[Monitor.scala:664:34] wire d_clr_wo_ready; // @[Monitor.scala:665:34] wire [3:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [7:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_3 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_3; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_3; // @[Monitor.scala:673:46, :783:46] wire _T_1184 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] assign d_clr_wo_ready = _T_1184 & ~d_release_ack; // @[Monitor.scala:665:34, :673:46, :674:{26,71,74}] assign d_clr = _T_1285 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_opcodes_clr = {4{d_clr}}; // @[Monitor.scala:664:34, :668:33, :678:89, :680:21] assign d_sizes_clr = {8{d_clr}}; // @[Monitor.scala:664:34, :670:31, :678:89, :681:21] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = ~io_in_a_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [1:0] _inflight_T = {inflight[1], inflight[0] | a_set}; // @[Monitor.scala:614:27, :626:34, :705:27] wire _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [1:0] _inflight_T_2 = {1'h0, _inflight_T[0] & _inflight_T_1}; // @[Monitor.scala:705:{27,36,38}] wire [3:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [3:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [3:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [7:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [7:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [7:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [1:0] inflight_1; // @[Monitor.scala:726:35] wire [1:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [3:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [3:0] _c_opcode_lookup_T_1 = inflight_opcodes_1; // @[Monitor.scala:727:35, :749:44] wire [3:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [7:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [7:0] _c_size_lookup_T_1 = inflight_sizes_1; // @[Monitor.scala:728:35, :750:42] wire [7:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire [11:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [5:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[11:6]; // @[package.scala:243:46] wire [5:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 6'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [5:0] d_first_counter_2; // @[Edges.scala:229:27] wire [6:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 7'h1; // @[Edges.scala:229:27, :230:28] wire [5:0] d_first_counter1_2 = _d_first_counter1_T_2[5:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 6'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 6'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 6'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [5:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [5:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [5:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [7:0] c_size_lookup; // @[Monitor.scala:748:35] wire [15:0] _c_opcode_lookup_T_6 = {12'h0, _c_opcode_lookup_T_1}; // @[Monitor.scala:749:{44,97}] wire [15:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [15:0] _c_size_lookup_T_6 = {8'h0, _c_size_lookup_T_1}; // @[Monitor.scala:750:{42,93}] wire [15:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[15:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[7:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire d_clr_1; // @[Monitor.scala:774:34] wire d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [3:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [7:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_1256 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_1256 & d_release_ack_1; // @[Monitor.scala:775:34, :783:46, :784:{26,71}] assign d_clr_1 = _T_1285 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_opcodes_clr_1 = {4{d_clr_1}}; // @[Monitor.scala:774:34, :776:34, :788:88, :790:21] assign d_sizes_clr_1 = {8{d_clr_1}}; // @[Monitor.scala:774:34, :777:34, :788:88, :791:21] wire _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [1:0] _inflight_T_5 = {1'h0, _inflight_T_3[0] & _inflight_T_4}; // @[Monitor.scala:814:{35,44,46}] wire [3:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [3:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [7:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [7:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]

Generate the Verilog code corresponding to the following Chisel files. File PE.scala: // See README.md for license details. package gemmini import chisel3._ import chisel3.util._ class PEControl[T <: Data : Arithmetic](accType: T) extends Bundle { val dataflow = UInt(1.W) // TODO make this an Enum val propagate = UInt(1.W) // Which register should be propagated (and which should be accumulated)? val shift = UInt(log2Up(accType.getWidth).W) // TODO this isn't correct for Floats } class MacUnit[T <: Data](inputType: T, cType: T, dType: T) (implicit ev: Arithmetic[T]) extends Module { import ev._ val io = IO(new Bundle { val in_a = Input(inputType) val in_b = Input(inputType) val in_c = Input(cType) val out_d = Output(dType) }) io.out_d := io.in_c.mac(io.in_a, io.in_b) } // TODO update documentation /** * A PE implementing a MAC operation. Configured as fully combinational when integrated into a Mesh. * @param width Data width of operands */ class PE[T <: Data](inputType: T, outputType: T, accType: T, df: Dataflow.Value, max_simultaneous_matmuls: Int) (implicit ev: Arithmetic[T]) extends Module { // Debugging variables import ev._ val io = IO(new Bundle { val in_a = Input(inputType) val in_b = Input(outputType) val in_d = Input(outputType) val out_a = Output(inputType) val out_b = Output(outputType) val out_c = Output(outputType) val in_control = Input(new PEControl(accType)) val out_control = Output(new PEControl(accType)) val in_id = Input(UInt(log2Up(max_simultaneous_matmuls).W)) val out_id = Output(UInt(log2Up(max_simultaneous_matmuls).W)) val in_last = Input(Bool()) val out_last = Output(Bool()) val in_valid = Input(Bool()) val out_valid = Output(Bool()) val bad_dataflow = Output(Bool()) }) val cType = if (df == Dataflow.WS) inputType else accType // When creating PEs that support multiple dataflows, the // elaboration/synthesis tools often fail to consolidate and de-duplicate // MAC units. To force mac circuitry to be re-used, we create a "mac_unit" // module here which just performs a single MAC operation val mac_unit = Module(new MacUnit(inputType, if (df == Dataflow.WS) outputType else accType, outputType)) val a = io.in_a val b = io.in_b val d = io.in_d val c1 = Reg(cType) val c2 = Reg(cType) val dataflow = io.in_control.dataflow val prop = io.in_control.propagate val shift = io.in_control.shift val id = io.in_id val last = io.in_last val valid = io.in_valid io.out_a := a io.out_control.dataflow := dataflow io.out_control.propagate := prop io.out_control.shift := shift io.out_id := id io.out_last := last io.out_valid := valid mac_unit.io.in_a := a val last_s = RegEnable(prop, valid) val flip = last_s =/= prop val shift_offset = Mux(flip, shift, 0.U) // Which dataflow are we using? val OUTPUT_STATIONARY = Dataflow.OS.id.U(1.W) val WEIGHT_STATIONARY = Dataflow.WS.id.U(1.W) // Is c1 being computed on, or propagated forward (in the output-stationary dataflow)? val COMPUTE = 0.U(1.W) val PROPAGATE = 1.U(1.W) io.bad_dataflow := false.B when ((df == Dataflow.OS).B || ((df == Dataflow.BOTH).B && dataflow === OUTPUT_STATIONARY)) { when(prop === PROPAGATE) { io.out_c := (c1 >> shift_offset).clippedToWidthOf(outputType) io.out_b := b mac_unit.io.in_b := b.asTypeOf(inputType) mac_unit.io.in_c := c2 c2 := mac_unit.io.out_d c1 := d.withWidthOf(cType) }.otherwise { io.out_c := (c2 >> shift_offset).clippedToWidthOf(outputType) io.out_b := b mac_unit.io.in_b := b.asTypeOf(inputType) mac_unit.io.in_c := c1 c1 := mac_unit.io.out_d c2 := d.withWidthOf(cType) } }.elsewhen ((df == Dataflow.WS).B || ((df == Dataflow.BOTH).B && dataflow === WEIGHT_STATIONARY)) { when(prop === PROPAGATE) { io.out_c := c1 mac_unit.io.in_b := c2.asTypeOf(inputType) mac_unit.io.in_c := b io.out_b := mac_unit.io.out_d c1 := d }.otherwise { io.out_c := c2 mac_unit.io.in_b := c1.asTypeOf(inputType) mac_unit.io.in_c := b io.out_b := mac_unit.io.out_d c2 := d } }.otherwise { io.bad_dataflow := true.B //assert(false.B, "unknown dataflow") io.out_c := DontCare io.out_b := DontCare mac_unit.io.in_b := b.asTypeOf(inputType) mac_unit.io.in_c := c2 } when (!valid) { c1 := c1 c2 := c2 mac_unit.io.in_b := DontCare mac_unit.io.in_c := DontCare } } File Arithmetic.scala: // A simple type class for Chisel datatypes that can add and multiply. To add your own type, simply create your own: // implicit MyTypeArithmetic extends Arithmetic[MyType] { ... } package gemmini import chisel3._ import chisel3.util._ import hardfloat._ // Bundles that represent the raw bits of custom datatypes case class Float(expWidth: Int, sigWidth: Int) extends Bundle { val bits = UInt((expWidth + sigWidth).W) val bias: Int = (1 << (expWidth-1)) - 1 } case class DummySInt(w: Int) extends Bundle { val bits = UInt(w.W) def dontCare: DummySInt = { val o = Wire(new DummySInt(w)) o.bits := 0.U o } } // The Arithmetic typeclass which implements various arithmetic operations on custom datatypes abstract class Arithmetic[T <: Data] { implicit def cast(t: T): ArithmeticOps[T] } abstract class ArithmeticOps[T <: Data](self: T) { def *(t: T): T def mac(m1: T, m2: T): T // Returns (m1 * m2 + self) def +(t: T): T def -(t: T): T def >>(u: UInt): T // This is a rounding shift! Rounds away from 0 def >(t: T): Bool def identity: T def withWidthOf(t: T): T def clippedToWidthOf(t: T): T // Like "withWidthOf", except that it saturates def relu: T def zero: T def minimum: T // Optional parameters, which only need to be defined if you want to enable various optimizations for transformers def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[T])] = None def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[T])] = None def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = None def mult_with_reciprocal[U <: Data](reciprocal: U) = self } object Arithmetic { implicit object UIntArithmetic extends Arithmetic[UInt] { override implicit def cast(self: UInt) = new ArithmeticOps(self) { override def *(t: UInt) = self * t override def mac(m1: UInt, m2: UInt) = m1 * m2 + self override def +(t: UInt) = self + t override def -(t: UInt) = self - t override def >>(u: UInt) = { // The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm // TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here? val point_five = Mux(u === 0.U, 0.U, self(u - 1.U)) val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U val ones_digit = self(u) val r = point_five & (zeros | ones_digit) (self >> u).asUInt + r } override def >(t: UInt): Bool = self > t override def withWidthOf(t: UInt) = self.asTypeOf(t) override def clippedToWidthOf(t: UInt) = { val sat = ((1 << (t.getWidth-1))-1).U Mux(self > sat, sat, self)(t.getWidth-1, 0) } override def relu: UInt = self override def zero: UInt = 0.U override def identity: UInt = 1.U override def minimum: UInt = 0.U } } implicit object SIntArithmetic extends Arithmetic[SInt] { override implicit def cast(self: SInt) = new ArithmeticOps(self) { override def *(t: SInt) = self * t override def mac(m1: SInt, m2: SInt) = m1 * m2 + self override def +(t: SInt) = self + t override def -(t: SInt) = self - t override def >>(u: UInt) = { // The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm // TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here? val point_five = Mux(u === 0.U, 0.U, self(u - 1.U)) val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U val ones_digit = self(u) val r = (point_five & (zeros | ones_digit)).asBool (self >> u).asSInt + Mux(r, 1.S, 0.S) } override def >(t: SInt): Bool = self > t override def withWidthOf(t: SInt) = { if (self.getWidth >= t.getWidth) self(t.getWidth-1, 0).asSInt else { val sign_bits = t.getWidth - self.getWidth val sign = self(self.getWidth-1) Cat(Cat(Seq.fill(sign_bits)(sign)), self).asTypeOf(t) } } override def clippedToWidthOf(t: SInt): SInt = { val maxsat = ((1 << (t.getWidth-1))-1).S val minsat = (-(1 << (t.getWidth-1))).S MuxCase(self, Seq((self > maxsat) -> maxsat, (self < minsat) -> minsat))(t.getWidth-1, 0).asSInt } override def relu: SInt = Mux(self >= 0.S, self, 0.S) override def zero: SInt = 0.S override def identity: SInt = 1.S override def minimum: SInt = (-(1 << (self.getWidth-1))).S override def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = { // TODO this uses a floating point divider, but we should use an integer divider instead val input = Wire(Decoupled(denom_t.cloneType)) val output = Wire(Decoupled(self.cloneType)) // We translate our integer to floating-point form so that we can use the hardfloat divider val expWidth = log2Up(self.getWidth) + 1 val sigWidth = self.getWidth def sin_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def uin_to_float(x: UInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := false.B in_to_rec_fn.io.in := x in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def float_to_in(x: UInt) = { val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth)) rec_fn_to_in.io.signedOut := true.B rec_fn_to_in.io.in := x rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag rec_fn_to_in.io.out.asSInt } val self_rec = sin_to_float(self) val denom_rec = uin_to_float(input.bits) // Instantiate the hardloat divider val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options)) input.ready := divider.io.inReady divider.io.inValid := input.valid divider.io.sqrtOp := false.B divider.io.a := self_rec divider.io.b := denom_rec divider.io.roundingMode := consts.round_minMag divider.io.detectTininess := consts.tininess_afterRounding output.valid := divider.io.outValid_div output.bits := float_to_in(divider.io.out) assert(!output.valid || output.ready) Some((input, output)) } override def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = { // TODO this uses a floating point divider, but we should use an integer divider instead val input = Wire(Decoupled(UInt(0.W))) val output = Wire(Decoupled(self.cloneType)) input.bits := DontCare // We translate our integer to floating-point form so that we can use the hardfloat divider val expWidth = log2Up(self.getWidth) + 1 val sigWidth = self.getWidth def in_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def float_to_in(x: UInt) = { val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth)) rec_fn_to_in.io.signedOut := true.B rec_fn_to_in.io.in := x rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag rec_fn_to_in.io.out.asSInt } val self_rec = in_to_float(self) // Instantiate the hardloat sqrt val sqrter = Module(new DivSqrtRecFN_small(expWidth, sigWidth, 0)) input.ready := sqrter.io.inReady sqrter.io.inValid := input.valid sqrter.io.sqrtOp := true.B sqrter.io.a := self_rec sqrter.io.b := DontCare sqrter.io.roundingMode := consts.round_minMag sqrter.io.detectTininess := consts.tininess_afterRounding output.valid := sqrter.io.outValid_sqrt output.bits := float_to_in(sqrter.io.out) assert(!output.valid || output.ready) Some((input, output)) } override def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = u match { case Float(expWidth, sigWidth) => val input = Wire(Decoupled(UInt(0.W))) val output = Wire(Decoupled(u.cloneType)) input.bits := DontCare // We translate our integer to floating-point form so that we can use the hardfloat divider def in_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } val self_rec = in_to_float(self) val one_rec = in_to_float(1.S) // Instantiate the hardloat divider val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options)) input.ready := divider.io.inReady divider.io.inValid := input.valid divider.io.sqrtOp := false.B divider.io.a := one_rec divider.io.b := self_rec divider.io.roundingMode := consts.round_near_even divider.io.detectTininess := consts.tininess_afterRounding output.valid := divider.io.outValid_div output.bits := fNFromRecFN(expWidth, sigWidth, divider.io.out).asTypeOf(u) assert(!output.valid || output.ready) Some((input, output)) case _ => None } override def mult_with_reciprocal[U <: Data](reciprocal: U): SInt = reciprocal match { case recip @ Float(expWidth, sigWidth) => def in_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def float_to_in(x: UInt) = { val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth)) rec_fn_to_in.io.signedOut := true.B rec_fn_to_in.io.in := x rec_fn_to_in.io.roundingMode := consts.round_minMag rec_fn_to_in.io.out.asSInt } val self_rec = in_to_float(self) val reciprocal_rec = recFNFromFN(expWidth, sigWidth, recip.bits) // Instantiate the hardloat divider val muladder = Module(new MulRecFN(expWidth, sigWidth)) muladder.io.roundingMode := consts.round_near_even muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := self_rec muladder.io.b := reciprocal_rec float_to_in(muladder.io.out) case _ => self } } } implicit object FloatArithmetic extends Arithmetic[Float] { // TODO Floating point arithmetic currently switches between recoded and standard formats for every operation. However, it should stay in the recoded format as it travels through the systolic array override implicit def cast(self: Float): ArithmeticOps[Float] = new ArithmeticOps(self) { override def *(t: Float): Float = { val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth)) t_resizer.io.in := t_rec t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag t_resizer.io.detectTininess := consts.tininess_afterRounding val t_rec_resized = t_resizer.io.out val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth)) muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := self_rec muladder.io.b := t_rec_resized val out = Wire(Float(self.expWidth, self.sigWidth)) out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) out } override def mac(m1: Float, m2: Float): Float = { // Recode all operands val m1_rec = recFNFromFN(m1.expWidth, m1.sigWidth, m1.bits) val m2_rec = recFNFromFN(m2.expWidth, m2.sigWidth, m2.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Resize m1 to self's width val m1_resizer = Module(new RecFNToRecFN(m1.expWidth, m1.sigWidth, self.expWidth, self.sigWidth)) m1_resizer.io.in := m1_rec m1_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag m1_resizer.io.detectTininess := consts.tininess_afterRounding val m1_rec_resized = m1_resizer.io.out // Resize m2 to self's width val m2_resizer = Module(new RecFNToRecFN(m2.expWidth, m2.sigWidth, self.expWidth, self.sigWidth)) m2_resizer.io.in := m2_rec m2_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag m2_resizer.io.detectTininess := consts.tininess_afterRounding val m2_rec_resized = m2_resizer.io.out // Perform multiply-add val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth)) muladder.io.op := 0.U muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := m1_rec_resized muladder.io.b := m2_rec_resized muladder.io.c := self_rec // Convert result to standard format // TODO remove these intermediate recodings val out = Wire(Float(self.expWidth, self.sigWidth)) out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) out } override def +(t: Float): Float = { require(self.getWidth >= t.getWidth) // This just makes it easier to write the resizing code // Recode all operands val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Generate 1 as a float val in_to_rec_fn = Module(new INToRecFN(1, self.expWidth, self.sigWidth)) in_to_rec_fn.io.signedIn := false.B in_to_rec_fn.io.in := 1.U in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding val one_rec = in_to_rec_fn.io.out // Resize t val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth)) t_resizer.io.in := t_rec t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag t_resizer.io.detectTininess := consts.tininess_afterRounding val t_rec_resized = t_resizer.io.out // Perform addition val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth)) muladder.io.op := 0.U muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := t_rec_resized muladder.io.b := one_rec muladder.io.c := self_rec val result = Wire(Float(self.expWidth, self.sigWidth)) result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) result } override def -(t: Float): Float = { val t_sgn = t.bits(t.getWidth-1) val neg_t = Cat(~t_sgn, t.bits(t.getWidth-2,0)).asTypeOf(t) self + neg_t } override def >>(u: UInt): Float = { // Recode self val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Get 2^(-u) as a recoded float val shift_exp = Wire(UInt(self.expWidth.W)) shift_exp := self.bias.U - u val shift_fn = Cat(0.U(1.W), shift_exp, 0.U((self.sigWidth-1).W)) val shift_rec = recFNFromFN(self.expWidth, self.sigWidth, shift_fn) assert(shift_exp =/= 0.U, "scaling by denormalized numbers is not currently supported") // Multiply self and 2^(-u) val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth)) muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := self_rec muladder.io.b := shift_rec val result = Wire(Float(self.expWidth, self.sigWidth)) result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) result } override def >(t: Float): Bool = { // Recode all operands val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Resize t to self's width val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth)) t_resizer.io.in := t_rec t_resizer.io.roundingMode := consts.round_near_even t_resizer.io.detectTininess := consts.tininess_afterRounding val t_rec_resized = t_resizer.io.out val comparator = Module(new CompareRecFN(self.expWidth, self.sigWidth)) comparator.io.a := self_rec comparator.io.b := t_rec_resized comparator.io.signaling := false.B comparator.io.gt } override def withWidthOf(t: Float): Float = { val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth)) resizer.io.in := self_rec resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag resizer.io.detectTininess := consts.tininess_afterRounding val result = Wire(Float(t.expWidth, t.sigWidth)) result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out) result } override def clippedToWidthOf(t: Float): Float = { // TODO check for overflow. Right now, we just assume that overflow doesn't happen val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth)) resizer.io.in := self_rec resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag resizer.io.detectTininess := consts.tininess_afterRounding val result = Wire(Float(t.expWidth, t.sigWidth)) result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out) result } override def relu: Float = { val raw = rawFloatFromFN(self.expWidth, self.sigWidth, self.bits) val result = Wire(Float(self.expWidth, self.sigWidth)) result.bits := Mux(!raw.isZero && raw.sign, 0.U, self.bits) result } override def zero: Float = 0.U.asTypeOf(self) override def identity: Float = Cat(0.U(2.W), ~(0.U((self.expWidth-1).W)), 0.U((self.sigWidth-1).W)).asTypeOf(self) override def minimum: Float = Cat(1.U, ~(0.U(self.expWidth.W)), 0.U((self.sigWidth-1).W)).asTypeOf(self) } } implicit object DummySIntArithmetic extends Arithmetic[DummySInt] { override implicit def cast(self: DummySInt) = new ArithmeticOps(self) { override def *(t: DummySInt) = self.dontCare override def mac(m1: DummySInt, m2: DummySInt) = self.dontCare override def +(t: DummySInt) = self.dontCare override def -(t: DummySInt) = self.dontCare override def >>(t: UInt) = self.dontCare override def >(t: DummySInt): Bool = false.B override def identity = self.dontCare override def withWidthOf(t: DummySInt) = self.dontCare override def clippedToWidthOf(t: DummySInt) = self.dontCare override def relu = self.dontCare override def zero = self.dontCare override def minimum: DummySInt = self.dontCare } } }

module PE_272( // @[PE.scala:31:7] input clock, // @[PE.scala:31:7] input reset, // @[PE.scala:31:7] input [7:0] io_in_a, // @[PE.scala:35:14] input [19:0] io_in_b, // @[PE.scala:35:14] input [19:0] io_in_d, // @[PE.scala:35:14] output [7:0] io_out_a, // @[PE.scala:35:14] output [19:0] io_out_b, // @[PE.scala:35:14] output [19:0] io_out_c, // @[PE.scala:35:14] input io_in_control_dataflow, // @[PE.scala:35:14] input io_in_control_propagate, // @[PE.scala:35:14] input [4:0] io_in_control_shift, // @[PE.scala:35:14] output io_out_control_dataflow, // @[PE.scala:35:14] output io_out_control_propagate, // @[PE.scala:35:14] output [4:0] io_out_control_shift, // @[PE.scala:35:14] input [2:0] io_in_id, // @[PE.scala:35:14] output [2:0] io_out_id, // @[PE.scala:35:14] input io_in_last, // @[PE.scala:35:14] output io_out_last, // @[PE.scala:35:14] input io_in_valid, // @[PE.scala:35:14] output io_out_valid // @[PE.scala:35:14] ); wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:31:7] wire [19:0] io_in_b_0 = io_in_b; // @[PE.scala:31:7] wire [19:0] io_in_d_0 = io_in_d; // @[PE.scala:31:7] wire io_in_control_dataflow_0 = io_in_control_dataflow; // @[PE.scala:31:7] wire io_in_control_propagate_0 = io_in_control_propagate; // @[PE.scala:31:7] wire [4:0] io_in_control_shift_0 = io_in_control_shift; // @[PE.scala:31:7] wire [2:0] io_in_id_0 = io_in_id; // @[PE.scala:31:7] wire io_in_last_0 = io_in_last; // @[PE.scala:31:7] wire io_in_valid_0 = io_in_valid; // @[PE.scala:31:7] wire io_bad_dataflow = 1'h0; // @[PE.scala:31:7] wire _io_out_c_T_5 = 1'h0; // @[Arithmetic.scala:125:33] wire _io_out_c_T_6 = 1'h0; // @[Arithmetic.scala:125:60] wire _io_out_c_T_16 = 1'h0; // @[Arithmetic.scala:125:33] wire _io_out_c_T_17 = 1'h0; // @[Arithmetic.scala:125:60] wire [7:0] io_out_a_0 = io_in_a_0; // @[PE.scala:31:7] wire [19:0] _mac_unit_io_in_b_T = io_in_b_0; // @[PE.scala:31:7, :106:37] wire [19:0] _mac_unit_io_in_b_T_2 = io_in_b_0; // @[PE.scala:31:7, :113:37] wire [19:0] _mac_unit_io_in_b_T_8 = io_in_b_0; // @[PE.scala:31:7, :137:35] wire io_out_control_dataflow_0 = io_in_control_dataflow_0; // @[PE.scala:31:7] wire io_out_control_propagate_0 = io_in_control_propagate_0; // @[PE.scala:31:7] wire [4:0] io_out_control_shift_0 = io_in_control_shift_0; // @[PE.scala:31:7] wire [2:0] io_out_id_0 = io_in_id_0; // @[PE.scala:31:7] wire io_out_last_0 = io_in_last_0; // @[PE.scala:31:7] wire io_out_valid_0 = io_in_valid_0; // @[PE.scala:31:7] wire [19:0] io_out_b_0; // @[PE.scala:31:7] wire [19:0] io_out_c_0; // @[PE.scala:31:7] reg [7:0] c1; // @[PE.scala:70:15] wire [7:0] _io_out_c_zeros_T_1 = c1; // @[PE.scala:70:15] wire [7:0] _mac_unit_io_in_b_T_6 = c1; // @[PE.scala:70:15, :127:38] reg [7:0] c2; // @[PE.scala:71:15] wire [7:0] _io_out_c_zeros_T_10 = c2; // @[PE.scala:71:15] wire [7:0] _mac_unit_io_in_b_T_4 = c2; // @[PE.scala:71:15, :121:38] reg last_s; // @[PE.scala:89:25] wire flip = last_s != io_in_control_propagate_0; // @[PE.scala:31:7, :89:25, :90:21] wire [4:0] shift_offset = flip ? io_in_control_shift_0 : 5'h0; // @[PE.scala:31:7, :90:21, :91:25] wire _GEN = shift_offset == 5'h0; // @[PE.scala:91:25] wire _io_out_c_point_five_T; // @[Arithmetic.scala:101:32] assign _io_out_c_point_five_T = _GEN; // @[Arithmetic.scala:101:32] wire _io_out_c_point_five_T_5; // @[Arithmetic.scala:101:32] assign _io_out_c_point_five_T_5 = _GEN; // @[Arithmetic.scala:101:32] wire [5:0] _GEN_0 = {1'h0, shift_offset} - 6'h1; // @[PE.scala:91:25] wire [5:0] _io_out_c_point_five_T_1; // @[Arithmetic.scala:101:53] assign _io_out_c_point_five_T_1 = _GEN_0; // @[Arithmetic.scala:101:53] wire [5:0] _io_out_c_zeros_T_2; // @[Arithmetic.scala:102:66] assign _io_out_c_zeros_T_2 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66] wire [5:0] _io_out_c_point_five_T_6; // @[Arithmetic.scala:101:53] assign _io_out_c_point_five_T_6 = _GEN_0; // @[Arithmetic.scala:101:53] wire [5:0] _io_out_c_zeros_T_11; // @[Arithmetic.scala:102:66] assign _io_out_c_zeros_T_11 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66] wire [4:0] _io_out_c_point_five_T_2 = _io_out_c_point_five_T_1[4:0]; // @[Arithmetic.scala:101:53] wire [7:0] _io_out_c_point_five_T_3 = $signed($signed(c1) >>> _io_out_c_point_five_T_2); // @[PE.scala:70:15] wire _io_out_c_point_five_T_4 = _io_out_c_point_five_T_3[0]; // @[Arithmetic.scala:101:50] wire io_out_c_point_five = ~_io_out_c_point_five_T & _io_out_c_point_five_T_4; // @[Arithmetic.scala:101:{29,32,50}] wire _GEN_1 = shift_offset < 5'h2; // @[PE.scala:91:25] wire _io_out_c_zeros_T; // @[Arithmetic.scala:102:27] assign _io_out_c_zeros_T = _GEN_1; // @[Arithmetic.scala:102:27] wire _io_out_c_zeros_T_9; // @[Arithmetic.scala:102:27] assign _io_out_c_zeros_T_9 = _GEN_1; // @[Arithmetic.scala:102:27] wire [4:0] _io_out_c_zeros_T_3 = _io_out_c_zeros_T_2[4:0]; // @[Arithmetic.scala:102:66] wire [31:0] _io_out_c_zeros_T_4 = 32'h1 << _io_out_c_zeros_T_3; // @[Arithmetic.scala:102:{60,66}] wire [32:0] _io_out_c_zeros_T_5 = {1'h0, _io_out_c_zeros_T_4} - 33'h1; // @[Arithmetic.scala:102:{60,81}] wire [31:0] _io_out_c_zeros_T_6 = _io_out_c_zeros_T_5[31:0]; // @[Arithmetic.scala:102:81] wire [31:0] _io_out_c_zeros_T_7 = {24'h0, _io_out_c_zeros_T_6[7:0] & _io_out_c_zeros_T_1}; // @[Arithmetic.scala:102:{45,52,81}] wire [31:0] _io_out_c_zeros_T_8 = _io_out_c_zeros_T ? 32'h0 : _io_out_c_zeros_T_7; // @[Arithmetic.scala:102:{24,27,52}] wire io_out_c_zeros = |_io_out_c_zeros_T_8; // @[Arithmetic.scala:102:{24,89}] wire [7:0] _GEN_2 = {3'h0, shift_offset}; // @[PE.scala:91:25] wire [7:0] _GEN_3 = $signed($signed(c1) >>> _GEN_2); // @[PE.scala:70:15] wire [7:0] _io_out_c_ones_digit_T; // @[Arithmetic.scala:103:30] assign _io_out_c_ones_digit_T = _GEN_3; // @[Arithmetic.scala:103:30] wire [7:0] _io_out_c_T; // @[Arithmetic.scala:107:15] assign _io_out_c_T = _GEN_3; // @[Arithmetic.scala:103:30, :107:15] wire io_out_c_ones_digit = _io_out_c_ones_digit_T[0]; // @[Arithmetic.scala:103:30] wire _io_out_c_r_T = io_out_c_zeros | io_out_c_ones_digit; // @[Arithmetic.scala:102:89, :103:30, :105:38] wire _io_out_c_r_T_1 = io_out_c_point_five & _io_out_c_r_T; // @[Arithmetic.scala:101:29, :105:{29,38}] wire io_out_c_r = _io_out_c_r_T_1; // @[Arithmetic.scala:105:{29,53}] wire [1:0] _io_out_c_T_1 = {1'h0, io_out_c_r}; // @[Arithmetic.scala:105:53, :107:33] wire [8:0] _io_out_c_T_2 = {_io_out_c_T[7], _io_out_c_T} + {{7{_io_out_c_T_1[1]}}, _io_out_c_T_1}; // @[Arithmetic.scala:107:{15,28,33}] wire [7:0] _io_out_c_T_3 = _io_out_c_T_2[7:0]; // @[Arithmetic.scala:107:28] wire [7:0] _io_out_c_T_4 = _io_out_c_T_3; // @[Arithmetic.scala:107:28] wire [19:0] _io_out_c_T_7 = {{12{_io_out_c_T_4[7]}}, _io_out_c_T_4}; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_8 = _io_out_c_T_7; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_9 = _io_out_c_T_8; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_10 = _io_out_c_T_9; // @[Arithmetic.scala:125:{81,99}] wire [19:0] _mac_unit_io_in_b_T_1 = _mac_unit_io_in_b_T; // @[PE.scala:106:37] wire [7:0] _mac_unit_io_in_b_WIRE = _mac_unit_io_in_b_T_1[7:0]; // @[PE.scala:106:37] wire [7:0] _c1_T = io_in_d_0[7:0]; // @[PE.scala:31:7] wire [7:0] _c2_T = io_in_d_0[7:0]; // @[PE.scala:31:7] wire [7:0] _c1_T_1 = _c1_T; // @[Arithmetic.scala:114:{15,33}] wire [4:0] _io_out_c_point_five_T_7 = _io_out_c_point_five_T_6[4:0]; // @[Arithmetic.scala:101:53] wire [7:0] _io_out_c_point_five_T_8 = $signed($signed(c2) >>> _io_out_c_point_five_T_7); // @[PE.scala:71:15] wire _io_out_c_point_five_T_9 = _io_out_c_point_five_T_8[0]; // @[Arithmetic.scala:101:50] wire io_out_c_point_five_1 = ~_io_out_c_point_five_T_5 & _io_out_c_point_five_T_9; // @[Arithmetic.scala:101:{29,32,50}] wire [4:0] _io_out_c_zeros_T_12 = _io_out_c_zeros_T_11[4:0]; // @[Arithmetic.scala:102:66] wire [31:0] _io_out_c_zeros_T_13 = 32'h1 << _io_out_c_zeros_T_12; // @[Arithmetic.scala:102:{60,66}] wire [32:0] _io_out_c_zeros_T_14 = {1'h0, _io_out_c_zeros_T_13} - 33'h1; // @[Arithmetic.scala:102:{60,81}] wire [31:0] _io_out_c_zeros_T_15 = _io_out_c_zeros_T_14[31:0]; // @[Arithmetic.scala:102:81] wire [31:0] _io_out_c_zeros_T_16 = {24'h0, _io_out_c_zeros_T_15[7:0] & _io_out_c_zeros_T_10}; // @[Arithmetic.scala:102:{45,52,81}] wire [31:0] _io_out_c_zeros_T_17 = _io_out_c_zeros_T_9 ? 32'h0 : _io_out_c_zeros_T_16; // @[Arithmetic.scala:102:{24,27,52}] wire io_out_c_zeros_1 = |_io_out_c_zeros_T_17; // @[Arithmetic.scala:102:{24,89}] wire [7:0] _GEN_4 = $signed($signed(c2) >>> _GEN_2); // @[PE.scala:71:15] wire [7:0] _io_out_c_ones_digit_T_1; // @[Arithmetic.scala:103:30] assign _io_out_c_ones_digit_T_1 = _GEN_4; // @[Arithmetic.scala:103:30] wire [7:0] _io_out_c_T_11; // @[Arithmetic.scala:107:15] assign _io_out_c_T_11 = _GEN_4; // @[Arithmetic.scala:103:30, :107:15] wire io_out_c_ones_digit_1 = _io_out_c_ones_digit_T_1[0]; // @[Arithmetic.scala:103:30] wire _io_out_c_r_T_2 = io_out_c_zeros_1 | io_out_c_ones_digit_1; // @[Arithmetic.scala:102:89, :103:30, :105:38] wire _io_out_c_r_T_3 = io_out_c_point_five_1 & _io_out_c_r_T_2; // @[Arithmetic.scala:101:29, :105:{29,38}] wire io_out_c_r_1 = _io_out_c_r_T_3; // @[Arithmetic.scala:105:{29,53}] wire [1:0] _io_out_c_T_12 = {1'h0, io_out_c_r_1}; // @[Arithmetic.scala:105:53, :107:33] wire [8:0] _io_out_c_T_13 = {_io_out_c_T_11[7], _io_out_c_T_11} + {{7{_io_out_c_T_12[1]}}, _io_out_c_T_12}; // @[Arithmetic.scala:107:{15,28,33}] wire [7:0] _io_out_c_T_14 = _io_out_c_T_13[7:0]; // @[Arithmetic.scala:107:28] wire [7:0] _io_out_c_T_15 = _io_out_c_T_14; // @[Arithmetic.scala:107:28] wire [19:0] _io_out_c_T_18 = {{12{_io_out_c_T_15[7]}}, _io_out_c_T_15}; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_19 = _io_out_c_T_18; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_20 = _io_out_c_T_19; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_21 = _io_out_c_T_20; // @[Arithmetic.scala:125:{81,99}] wire [19:0] _mac_unit_io_in_b_T_3 = _mac_unit_io_in_b_T_2; // @[PE.scala:113:37] wire [7:0] _mac_unit_io_in_b_WIRE_1 = _mac_unit_io_in_b_T_3[7:0]; // @[PE.scala:113:37] wire [7:0] _c2_T_1 = _c2_T; // @[Arithmetic.scala:114:{15,33}] wire [7:0] _mac_unit_io_in_b_T_5; // @[PE.scala:121:38] assign _mac_unit_io_in_b_T_5 = _mac_unit_io_in_b_T_4; // @[PE.scala:121:38] wire [7:0] _mac_unit_io_in_b_WIRE_2 = _mac_unit_io_in_b_T_5; // @[PE.scala:121:38] assign io_out_c_0 = io_in_control_propagate_0 ? {{12{c1[7]}}, c1} : {{12{c2[7]}}, c2}; // @[PE.scala:31:7, :70:15, :71:15, :119:30, :120:16, :126:16] wire [7:0] _mac_unit_io_in_b_T_7; // @[PE.scala:127:38] assign _mac_unit_io_in_b_T_7 = _mac_unit_io_in_b_T_6; // @[PE.scala:127:38] wire [7:0] _mac_unit_io_in_b_WIRE_3 = _mac_unit_io_in_b_T_7; // @[PE.scala:127:38] wire [19:0] _mac_unit_io_in_b_T_9 = _mac_unit_io_in_b_T_8; // @[PE.scala:137:35] wire [7:0] _mac_unit_io_in_b_WIRE_4 = _mac_unit_io_in_b_T_9[7:0]; // @[PE.scala:137:35] always @(posedge clock) begin // @[PE.scala:31:7] if (io_in_valid_0 & io_in_control_propagate_0) // @[PE.scala:31:7, :102:95, :141:17, :142:8] c1 <= io_in_d_0[7:0]; // @[PE.scala:31:7, :70:15] if (~(~io_in_valid_0 | io_in_control_propagate_0)) // @[PE.scala:31:7, :71:15, :102:95, :119:30, :130:10, :141:{9,17}, :143:8] c2 <= io_in_d_0[7:0]; // @[PE.scala:31:7, :71:15] if (io_in_valid_0) // @[PE.scala:31:7] last_s <= io_in_control_propagate_0; // @[PE.scala:31:7, :89:25] always @(posedge) MacUnit_16 mac_unit ( // @[PE.scala:64:24] .clock (clock), .reset (reset), .io_in_a (io_in_a_0), // @[PE.scala:31:7] .io_in_b (io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE_2 : _mac_unit_io_in_b_WIRE_3), // @[PE.scala:31:7, :119:30, :121:{24,38}, :127:{24,38}] .io_in_c (io_in_b_0), // @[PE.scala:31:7] .io_out_d (io_out_b_0) ); // @[PE.scala:64:24] assign io_out_a = io_out_a_0; // @[PE.scala:31:7] assign io_out_b = io_out_b_0; // @[PE.scala:31:7] assign io_out_c = io_out_c_0; // @[PE.scala:31:7] assign io_out_control_dataflow = io_out_control_dataflow_0; // @[PE.scala:31:7] assign io_out_control_propagate = io_out_control_propagate_0; // @[PE.scala:31:7] assign io_out_control_shift = io_out_control_shift_0; // @[PE.scala:31:7] assign io_out_id = io_out_id_0; // @[PE.scala:31:7] assign io_out_last = io_out_last_0; // @[PE.scala:31:7] assign io_out_valid = io_out_valid_0; // @[PE.scala:31:7] endmodule

Generate the Verilog code corresponding to the following Chisel files. File ShiftReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ // Similar to the Chisel ShiftRegister but allows the user to suggest a // name to the registers that get instantiated, and // to provide a reset value. object ShiftRegInit { def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T = (0 until n).foldRight(in) { case (i, next) => { val r = RegNext(next, init) name.foreach { na => r.suggestName(s"${na}_${i}") } r } } } /** These wrap behavioral * shift registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * The different types vary in their reset behavior: * AsyncResetShiftReg -- Asynchronously reset register array * A W(width) x D(depth) sized array is constructed from D instantiations of a * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg, * but only used for timing applications */ abstract class AbstractPipelineReg(w: Int = 1) extends Module { val io = IO(new Bundle { val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) } ) } object AbstractPipelineReg { def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = { val chain = Module(gen) name.foreach{ chain.suggestName(_) } chain.io.d := in.asUInt chain.io.q.asTypeOf(in) } } class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) { require(depth > 0, "Depth must be greater than 0.") override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}" val chain = List.tabulate(depth) { i => Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}") } chain.last.io.d := io.d chain.last.io.en := true.B (chain.init zip chain.tail).foreach { case (sink, source) => sink.io.d := source.io.q sink.io.en := true.B } io.q := chain.head.io.q } object AsyncResetShiftReg { def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name) def apply [T <: Data](in: T, depth: Int, name: Option[String]): T = apply(in, depth, 0, name) def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T = apply(in, depth, init.litValue.toInt, name) def apply [T <: Data](in: T, depth: Int, init: T): T = apply (in, depth, init.litValue.toInt, None) } File SynchronizerReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util.{RegEnable, Cat} /** These wrap behavioral * shift and next registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * * These are built up of *ResetSynchronizerPrimitiveShiftReg, * intended to be replaced by the integrator's metastable flops chains or replaced * at this level if they have a multi-bit wide synchronizer primitive. * The different types vary in their reset behavior: * NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin * AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep * 1-bit-wide shift registers. * SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg * * [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference. * * ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross * Clock Domains. */ object SynchronizerResetType extends Enumeration { val NonSync, Inferred, Sync, Async = Value } // Note: this should not be used directly. // Use the companion object to generate this with the correct reset type mixin. private class SynchronizerPrimitiveShiftReg( sync: Int, init: Boolean, resetType: SynchronizerResetType.Value) extends AbstractPipelineReg(1) { val initInt = if (init) 1 else 0 val initPostfix = resetType match { case SynchronizerResetType.NonSync => "" case _ => s"_i${initInt}" } override def desiredName = s"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}" val chain = List.tabulate(sync) { i => val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B) reg.suggestName(s"sync_$i") } chain.last := io.d.asBool (chain.init zip chain.tail).foreach { case (sink, source) => sink := source } io.q := chain.head.asUInt } private object SynchronizerPrimitiveShiftReg { def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = { val gen: () => SynchronizerPrimitiveShiftReg = resetType match { case SynchronizerResetType.NonSync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) case SynchronizerResetType.Async => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset case SynchronizerResetType.Sync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset case SynchronizerResetType.Inferred => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) } AbstractPipelineReg(gen(), in) } } // Note: This module may end up with a non-AsyncReset type reset. // But the Primitives within will always have AsyncReset type. class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asAsyncReset){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async) } } io.q := Cat(output.reverse) } object AsyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } // Note: This module may end up with a non-Bool type reset. // But the Primitives within will always have Bool reset type. @deprecated("SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.", "rocket-chip 1.2") class SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asBool){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync) } } io.q := Cat(output.reverse) } object SyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred) } io.q := Cat(output.reverse) } object ResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}" val output = Seq.tabulate(w) { i => SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync) } io.q := Cat(output.reverse) } object SynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, None) def apply [T <: Data](in: T): T = apply (in, 3, None) } class ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module { override def desiredName = s"ClockCrossingReg_w${w}" val io = IO(new Bundle{ val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) val en = Input(Bool()) }) val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en) io.q := cdc_reg } object ClockCrossingReg { def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = { val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit)) name.foreach{ cdc_reg.suggestName(_) } cdc_reg.io.d := in.asUInt cdc_reg.io.en := en cdc_reg.io.q.asTypeOf(in) } }

module AsyncResetSynchronizerShiftReg_w1_d3_i0_75( // @[SynchronizerReg.scala:80:7] input clock, // @[SynchronizerReg.scala:80:7] input reset, // @[SynchronizerReg.scala:80:7] output io_q // @[ShiftReg.scala:36:14] ); wire _output_T = reset; // @[SynchronizerReg.scala:86:21] wire io_d = 1'h1; // @[SynchronizerReg.scala:80:7, :87:41] wire _output_T_1 = 1'h1; // @[SynchronizerReg.scala:80:7, :87:41] wire output_0; // @[ShiftReg.scala:48:24] wire io_q_0; // @[SynchronizerReg.scala:80:7] assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_119 output_chain ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T), // @[SynchronizerReg.scala:86:21] .io_q (output_0) ); // @[ShiftReg.scala:45:23] assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7] endmodule

Generate the Verilog code corresponding to the following Chisel files. File ShiftReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ // Similar to the Chisel ShiftRegister but allows the user to suggest a // name to the registers that get instantiated, and // to provide a reset value. object ShiftRegInit { def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T = (0 until n).foldRight(in) { case (i, next) => { val r = RegNext(next, init) name.foreach { na => r.suggestName(s"${na}_${i}") } r } } } /** These wrap behavioral * shift registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * The different types vary in their reset behavior: * AsyncResetShiftReg -- Asynchronously reset register array * A W(width) x D(depth) sized array is constructed from D instantiations of a * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg, * but only used for timing applications */ abstract class AbstractPipelineReg(w: Int = 1) extends Module { val io = IO(new Bundle { val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) } ) } object AbstractPipelineReg { def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = { val chain = Module(gen) name.foreach{ chain.suggestName(_) } chain.io.d := in.asUInt chain.io.q.asTypeOf(in) } } class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) { require(depth > 0, "Depth must be greater than 0.") override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}" val chain = List.tabulate(depth) { i => Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}") } chain.last.io.d := io.d chain.last.io.en := true.B (chain.init zip chain.tail).foreach { case (sink, source) => sink.io.d := source.io.q sink.io.en := true.B } io.q := chain.head.io.q } object AsyncResetShiftReg { def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name) def apply [T <: Data](in: T, depth: Int, name: Option[String]): T = apply(in, depth, 0, name) def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T = apply(in, depth, init.litValue.toInt, name) def apply [T <: Data](in: T, depth: Int, init: T): T = apply (in, depth, init.litValue.toInt, None) } File AsyncQueue.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ case class AsyncQueueParams( depth: Int = 8, sync: Int = 3, safe: Boolean = true, // If safe is true, then effort is made to resynchronize the crossing indices when either side is reset. // This makes it safe/possible to reset one side of the crossing (but not the other) when the queue is empty. narrow: Boolean = false) // If narrow is true then the read mux is moved to the source side of the crossing. // This reduces the number of level shifters in the case where the clock crossing is also a voltage crossing, // at the expense of a combinational path from the sink to the source and back to the sink. { require (depth > 0 && isPow2(depth)) require (sync >= 2) val bits = log2Ceil(depth) val wires = if (narrow) 1 else depth } object AsyncQueueParams { // When there is only one entry, we don't need narrow. def singleton(sync: Int = 3, safe: Boolean = true) = AsyncQueueParams(1, sync, safe, false) } class AsyncBundleSafety extends Bundle { val ridx_valid = Input (Bool()) val widx_valid = Output(Bool()) val source_reset_n = Output(Bool()) val sink_reset_n = Input (Bool()) } class AsyncBundle[T <: Data](private val gen: T, val params: AsyncQueueParams = AsyncQueueParams()) extends Bundle { // Data-path synchronization val mem = Output(Vec(params.wires, gen)) val ridx = Input (UInt((params.bits+1).W)) val widx = Output(UInt((params.bits+1).W)) val index = params.narrow.option(Input(UInt(params.bits.W))) // Signals used to self-stabilize a safe AsyncQueue val safe = params.safe.option(new AsyncBundleSafety) } object GrayCounter { def apply(bits: Int, increment: Bool = true.B, clear: Bool = false.B, name: String = "binary"): UInt = { val incremented = Wire(UInt(bits.W)) val binary = RegNext(next=incremented, init=0.U).suggestName(name) incremented := Mux(clear, 0.U, binary + increment.asUInt) incremented ^ (incremented >> 1) } } class AsyncValidSync(sync: Int, desc: String) extends RawModule { val io = IO(new Bundle { val in = Input(Bool()) val out = Output(Bool()) }) val clock = IO(Input(Clock())) val reset = IO(Input(AsyncReset())) withClockAndReset(clock, reset){ io.out := AsyncResetSynchronizerShiftReg(io.in, sync, Some(desc)) } } class AsyncQueueSource[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module { override def desiredName = s"AsyncQueueSource_${gen.typeName}" val io = IO(new Bundle { // These come from the source domain val enq = Flipped(Decoupled(gen)) // These cross to the sink clock domain val async = new AsyncBundle(gen, params) }) val bits = params.bits val sink_ready = WireInit(true.B) val mem = Reg(Vec(params.depth, gen)) // This does NOT need to be reset at all. val widx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.enq.fire, !sink_ready, "widx_bin")) val ridx = AsyncResetSynchronizerShiftReg(io.async.ridx, params.sync, Some("ridx_gray")) val ready = sink_ready && widx =/= (ridx ^ (params.depth | params.depth >> 1).U) val index = if (bits == 0) 0.U else io.async.widx(bits-1, 0) ^ (io.async.widx(bits, bits) << (bits-1)) when (io.enq.fire) { mem(index) := io.enq.bits } val ready_reg = withReset(reset.asAsyncReset)(RegNext(next=ready, init=false.B).suggestName("ready_reg")) io.enq.ready := ready_reg && sink_ready val widx_reg = withReset(reset.asAsyncReset)(RegNext(next=widx, init=0.U).suggestName("widx_gray")) io.async.widx := widx_reg io.async.index match { case Some(index) => io.async.mem(0) := mem(index) case None => io.async.mem := mem } io.async.safe.foreach { sio => val source_valid_0 = Module(new AsyncValidSync(params.sync, "source_valid_0")) val source_valid_1 = Module(new AsyncValidSync(params.sync, "source_valid_1")) val sink_extend = Module(new AsyncValidSync(params.sync, "sink_extend")) val sink_valid = Module(new AsyncValidSync(params.sync, "sink_valid")) source_valid_0.reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset source_valid_1.reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset sink_extend .reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset sink_valid .reset := reset.asAsyncReset source_valid_0.clock := clock source_valid_1.clock := clock sink_extend .clock := clock sink_valid .clock := clock source_valid_0.io.in := true.B source_valid_1.io.in := source_valid_0.io.out sio.widx_valid := source_valid_1.io.out sink_extend.io.in := sio.ridx_valid sink_valid.io.in := sink_extend.io.out sink_ready := sink_valid.io.out sio.source_reset_n := !reset.asBool // Assert that if there is stuff in the queue, then reset cannot happen // Impossible to write because dequeue can occur on the receiving side, // then reset allowed to happen, but write side cannot know that dequeue // occurred. // TODO: write some sort of sanity check assertion for users // that denote don't reset when there is activity // assert (!(reset || !sio.sink_reset_n) || !io.enq.valid, "Enqueue while sink is reset and AsyncQueueSource is unprotected") // assert (!reset_rise || prev_idx_match.asBool, "Sink reset while AsyncQueueSource not empty") } } class AsyncQueueSink[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module { override def desiredName = s"AsyncQueueSink_${gen.typeName}" val io = IO(new Bundle { // These come from the sink domain val deq = Decoupled(gen) // These cross to the source clock domain val async = Flipped(new AsyncBundle(gen, params)) }) val bits = params.bits val source_ready = WireInit(true.B) val ridx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.deq.fire, !source_ready, "ridx_bin")) val widx = AsyncResetSynchronizerShiftReg(io.async.widx, params.sync, Some("widx_gray")) val valid = source_ready && ridx =/= widx // The mux is safe because timing analysis ensures ridx has reached the register // On an ASIC, changes to the unread location cannot affect the selected value // On an FPGA, only one input changes at a time => mem updates don't cause glitches // The register only latches when the selected valued is not being written val index = if (bits == 0) 0.U else ridx(bits-1, 0) ^ (ridx(bits, bits) << (bits-1)) io.async.index.foreach { _ := index } // This register does not NEED to be reset, as its contents will not // be considered unless the asynchronously reset deq valid register is set. // It is possible that bits latches when the source domain is reset / has power cut // This is safe, because isolation gates brought mem low before the zeroed widx reached us val deq_bits_nxt = io.async.mem(if (params.narrow) 0.U else index) io.deq.bits := ClockCrossingReg(deq_bits_nxt, en = valid, doInit = false, name = Some("deq_bits_reg")) val valid_reg = withReset(reset.asAsyncReset)(RegNext(next=valid, init=false.B).suggestName("valid_reg")) io.deq.valid := valid_reg && source_ready val ridx_reg = withReset(reset.asAsyncReset)(RegNext(next=ridx, init=0.U).suggestName("ridx_gray")) io.async.ridx := ridx_reg io.async.safe.foreach { sio => val sink_valid_0 = Module(new AsyncValidSync(params.sync, "sink_valid_0")) val sink_valid_1 = Module(new AsyncValidSync(params.sync, "sink_valid_1")) val source_extend = Module(new AsyncValidSync(params.sync, "source_extend")) val source_valid = Module(new AsyncValidSync(params.sync, "source_valid")) sink_valid_0 .reset := (reset.asBool || !sio.source_reset_n).asAsyncReset sink_valid_1 .reset := (reset.asBool || !sio.source_reset_n).asAsyncReset source_extend.reset := (reset.asBool || !sio.source_reset_n).asAsyncReset source_valid .reset := reset.asAsyncReset sink_valid_0 .clock := clock sink_valid_1 .clock := clock source_extend.clock := clock source_valid .clock := clock sink_valid_0.io.in := true.B sink_valid_1.io.in := sink_valid_0.io.out sio.ridx_valid := sink_valid_1.io.out source_extend.io.in := sio.widx_valid source_valid.io.in := source_extend.io.out source_ready := source_valid.io.out sio.sink_reset_n := !reset.asBool // TODO: write some sort of sanity check assertion for users // that denote don't reset when there is activity // // val reset_and_extend = !source_ready || !sio.source_reset_n || reset.asBool // val reset_and_extend_prev = RegNext(reset_and_extend, true.B) // val reset_rise = !reset_and_extend_prev && reset_and_extend // val prev_idx_match = AsyncResetReg(updateData=(io.async.widx===io.async.ridx), resetData=0) // assert (!reset_rise || prev_idx_match.asBool, "Source reset while AsyncQueueSink not empty") } } object FromAsyncBundle { // Sometimes it makes sense for the sink to have different sync than the source def apply[T <: Data](x: AsyncBundle[T]): DecoupledIO[T] = apply(x, x.params.sync) def apply[T <: Data](x: AsyncBundle[T], sync: Int): DecoupledIO[T] = { val sink = Module(new AsyncQueueSink(chiselTypeOf(x.mem(0)), x.params.copy(sync = sync))) sink.io.async <> x sink.io.deq } } object ToAsyncBundle { def apply[T <: Data](x: ReadyValidIO[T], params: AsyncQueueParams = AsyncQueueParams()): AsyncBundle[T] = { val source = Module(new AsyncQueueSource(chiselTypeOf(x.bits), params)) source.io.enq <> x source.io.async } } class AsyncQueue[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Crossing[T] { val io = IO(new CrossingIO(gen)) val source = withClockAndReset(io.enq_clock, io.enq_reset) { Module(new AsyncQueueSource(gen, params)) } val sink = withClockAndReset(io.deq_clock, io.deq_reset) { Module(new AsyncQueueSink (gen, params)) } source.io.enq <> io.enq io.deq <> sink.io.deq sink.io.async <> source.io.async }

module AsyncValidSync_166( // @[AsyncQueue.scala:58:7] input io_in, // @[AsyncQueue.scala:59:14] output io_out, // @[AsyncQueue.scala:59:14] input clock, // @[AsyncQueue.scala:63:17] input reset // @[AsyncQueue.scala:64:17] ); wire io_in_0 = io_in; // @[AsyncQueue.scala:58:7] wire _io_out_WIRE; // @[ShiftReg.scala:48:24] wire io_out_0; // @[AsyncQueue.scala:58:7] assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24] AsyncResetSynchronizerShiftReg_w1_d3_i0_183 io_out_source_extend ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (reset), .io_d (io_in_0), // @[AsyncQueue.scala:58:7] .io_q (_io_out_WIRE) ); // @[ShiftReg.scala:45:23] assign io_out = io_out_0; // @[AsyncQueue.scala:58:7] endmodule

Generate the Verilog code corresponding to the following Chisel files. File ShiftReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ // Similar to the Chisel ShiftRegister but allows the user to suggest a // name to the registers that get instantiated, and // to provide a reset value. object ShiftRegInit { def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T = (0 until n).foldRight(in) { case (i, next) => { val r = RegNext(next, init) name.foreach { na => r.suggestName(s"${na}_${i}") } r } } } /** These wrap behavioral * shift registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * The different types vary in their reset behavior: * AsyncResetShiftReg -- Asynchronously reset register array * A W(width) x D(depth) sized array is constructed from D instantiations of a * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg, * but only used for timing applications */ abstract class AbstractPipelineReg(w: Int = 1) extends Module { val io = IO(new Bundle { val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) } ) } object AbstractPipelineReg { def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = { val chain = Module(gen) name.foreach{ chain.suggestName(_) } chain.io.d := in.asUInt chain.io.q.asTypeOf(in) } } class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) { require(depth > 0, "Depth must be greater than 0.") override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}" val chain = List.tabulate(depth) { i => Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}") } chain.last.io.d := io.d chain.last.io.en := true.B (chain.init zip chain.tail).foreach { case (sink, source) => sink.io.d := source.io.q sink.io.en := true.B } io.q := chain.head.io.q } object AsyncResetShiftReg { def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name) def apply [T <: Data](in: T, depth: Int, name: Option[String]): T = apply(in, depth, 0, name) def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T = apply(in, depth, init.litValue.toInt, name) def apply [T <: Data](in: T, depth: Int, init: T): T = apply (in, depth, init.litValue.toInt, None) } File SynchronizerReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util.{RegEnable, Cat} /** These wrap behavioral * shift and next registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * * These are built up of *ResetSynchronizerPrimitiveShiftReg, * intended to be replaced by the integrator's metastable flops chains or replaced * at this level if they have a multi-bit wide synchronizer primitive. * The different types vary in their reset behavior: * NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin * AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep * 1-bit-wide shift registers. * SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg * * [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference. * * ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross * Clock Domains. */ object SynchronizerResetType extends Enumeration { val NonSync, Inferred, Sync, Async = Value } // Note: this should not be used directly. // Use the companion object to generate this with the correct reset type mixin. private class SynchronizerPrimitiveShiftReg( sync: Int, init: Boolean, resetType: SynchronizerResetType.Value) extends AbstractPipelineReg(1) { val initInt = if (init) 1 else 0 val initPostfix = resetType match { case SynchronizerResetType.NonSync => "" case _ => s"_i${initInt}" } override def desiredName = s"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}" val chain = List.tabulate(sync) { i => val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B) reg.suggestName(s"sync_$i") } chain.last := io.d.asBool (chain.init zip chain.tail).foreach { case (sink, source) => sink := source } io.q := chain.head.asUInt } private object SynchronizerPrimitiveShiftReg { def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = { val gen: () => SynchronizerPrimitiveShiftReg = resetType match { case SynchronizerResetType.NonSync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) case SynchronizerResetType.Async => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset case SynchronizerResetType.Sync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset case SynchronizerResetType.Inferred => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) } AbstractPipelineReg(gen(), in) } } // Note: This module may end up with a non-AsyncReset type reset. // But the Primitives within will always have AsyncReset type. class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asAsyncReset){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async) } } io.q := Cat(output.reverse) } object AsyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } // Note: This module may end up with a non-Bool type reset. // But the Primitives within will always have Bool reset type. @deprecated("SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.", "rocket-chip 1.2") class SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asBool){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync) } } io.q := Cat(output.reverse) } object SyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred) } io.q := Cat(output.reverse) } object ResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}" val output = Seq.tabulate(w) { i => SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync) } io.q := Cat(output.reverse) } object SynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, None) def apply [T <: Data](in: T): T = apply (in, 3, None) } class ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module { override def desiredName = s"ClockCrossingReg_w${w}" val io = IO(new Bundle{ val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) val en = Input(Bool()) }) val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en) io.q := cdc_reg } object ClockCrossingReg { def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = { val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit)) name.foreach{ cdc_reg.suggestName(_) } cdc_reg.io.d := in.asUInt cdc_reg.io.en := en cdc_reg.io.q.asTypeOf(in) } }

module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_482( // @[SynchronizerReg.scala:68:19] input clock, // @[SynchronizerReg.scala:68:19] input reset, // @[SynchronizerReg.scala:68:19] input io_d, // @[ShiftReg.scala:36:14] output io_q // @[ShiftReg.scala:36:14] ); wire io_d_0 = io_d; // @[SynchronizerReg.scala:68:19] wire _sync_2_T = io_d_0; // @[SynchronizerReg.scala:54:22, :68:19] wire io_q_0; // @[SynchronizerReg.scala:68:19] reg sync_0; // @[SynchronizerReg.scala:51:87] assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19] reg sync_1; // @[SynchronizerReg.scala:51:87] reg sync_2; // @[SynchronizerReg.scala:51:87] always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19] if (reset) begin // @[SynchronizerReg.scala:68:19] sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87] end else begin // @[SynchronizerReg.scala:68:19] sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87] sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87] sync_2 <= _sync_2_T; // @[SynchronizerReg.scala:51:87, :54:22] end always @(posedge, posedge)

Generate the Verilog code corresponding to the following Chisel files. File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /** Like Vec.apply(idx), but tolerates indices of mismatched width */ def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /** Any Data subtype that has a Bool member named valid. */ type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /** converts from camel case to to underscores, also removing all spaces */ def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /** converts spaces or underscores to hyphens, also lowering case */ def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y | (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y || y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /** Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation */ def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag }

module OptimizationBarrier_TLBEntryData_283( // @[package.scala:267:30] input clock, // @[package.scala:267:30] input reset, // @[package.scala:267:30] input [19:0] io_x_ppn, // @[package.scala:268:18] input io_x_u, // @[package.scala:268:18] input io_x_g, // @[package.scala:268:18] input io_x_ae_ptw, // @[package.scala:268:18] input io_x_ae_final, // @[package.scala:268:18] input io_x_ae_stage2, // @[package.scala:268:18] input io_x_pf, // @[package.scala:268:18] input io_x_gf, // @[package.scala:268:18] input io_x_sw, // @[package.scala:268:18] input io_x_sx, // @[package.scala:268:18] input io_x_sr, // @[package.scala:268:18] input io_x_hw, // @[package.scala:268:18] input io_x_hx, // @[package.scala:268:18] input io_x_hr, // @[package.scala:268:18] input io_x_pw, // @[package.scala:268:18] input io_x_px, // @[package.scala:268:18] input io_x_pr, // @[package.scala:268:18] input io_x_ppp, // @[package.scala:268:18] input io_x_pal, // @[package.scala:268:18] input io_x_paa, // @[package.scala:268:18] input io_x_eff, // @[package.scala:268:18] input io_x_c, // @[package.scala:268:18] input io_x_fragmented_superpage, // @[package.scala:268:18] output [19:0] io_y_ppn, // @[package.scala:268:18] output io_y_u, // @[package.scala:268:18] output io_y_ae_ptw, // @[package.scala:268:18] output io_y_ae_final, // @[package.scala:268:18] output io_y_ae_stage2, // @[package.scala:268:18] output io_y_pf, // @[package.scala:268:18] output io_y_gf, // @[package.scala:268:18] output io_y_sw, // @[package.scala:268:18] output io_y_sx, // @[package.scala:268:18] output io_y_sr, // @[package.scala:268:18] output io_y_hw, // @[package.scala:268:18] output io_y_hx, // @[package.scala:268:18] output io_y_hr, // @[package.scala:268:18] output io_y_pw, // @[package.scala:268:18] output io_y_px, // @[package.scala:268:18] output io_y_pr, // @[package.scala:268:18] output io_y_ppp, // @[package.scala:268:18] output io_y_pal, // @[package.scala:268:18] output io_y_paa, // @[package.scala:268:18] output io_y_eff, // @[package.scala:268:18] output io_y_c // @[package.scala:268:18] ); wire [19:0] io_x_ppn_0 = io_x_ppn; // @[package.scala:267:30] wire io_x_u_0 = io_x_u; // @[package.scala:267:30] wire io_x_g_0 = io_x_g; // @[package.scala:267:30] wire io_x_ae_ptw_0 = io_x_ae_ptw; // @[package.scala:267:30] wire io_x_ae_final_0 = io_x_ae_final; // @[package.scala:267:30] wire io_x_ae_stage2_0 = io_x_ae_stage2; // @[package.scala:267:30] wire io_x_pf_0 = io_x_pf; // @[package.scala:267:30] wire io_x_gf_0 = io_x_gf; // @[package.scala:267:30] wire io_x_sw_0 = io_x_sw; // @[package.scala:267:30] wire io_x_sx_0 = io_x_sx; // @[package.scala:267:30] wire io_x_sr_0 = io_x_sr; // @[package.scala:267:30] wire io_x_hw_0 = io_x_hw; // @[package.scala:267:30] wire io_x_hx_0 = io_x_hx; // @[package.scala:267:30] wire io_x_hr_0 = io_x_hr; // @[package.scala:267:30] wire io_x_pw_0 = io_x_pw; // @[package.scala:267:30] wire io_x_px_0 = io_x_px; // @[package.scala:267:30] wire io_x_pr_0 = io_x_pr; // @[package.scala:267:30] wire io_x_ppp_0 = io_x_ppp; // @[package.scala:267:30] wire io_x_pal_0 = io_x_pal; // @[package.scala:267:30] wire io_x_paa_0 = io_x_paa; // @[package.scala:267:30] wire io_x_eff_0 = io_x_eff; // @[package.scala:267:30] wire io_x_c_0 = io_x_c; // @[package.scala:267:30] wire io_x_fragmented_superpage_0 = io_x_fragmented_superpage; // @[package.scala:267:30] wire [19:0] io_y_ppn_0 = io_x_ppn_0; // @[package.scala:267:30] wire io_y_u_0 = io_x_u_0; // @[package.scala:267:30] wire io_y_g = io_x_g_0; // @[package.scala:267:30] wire io_y_ae_ptw_0 = io_x_ae_ptw_0; // @[package.scala:267:30] wire io_y_ae_final_0 = io_x_ae_final_0; // @[package.scala:267:30] wire io_y_ae_stage2_0 = io_x_ae_stage2_0; // @[package.scala:267:30] wire io_y_pf_0 = io_x_pf_0; // @[package.scala:267:30] wire io_y_gf_0 = io_x_gf_0; // @[package.scala:267:30] wire io_y_sw_0 = io_x_sw_0; // @[package.scala:267:30] wire io_y_sx_0 = io_x_sx_0; // @[package.scala:267:30] wire io_y_sr_0 = io_x_sr_0; // @[package.scala:267:30] wire io_y_hw_0 = io_x_hw_0; // @[package.scala:267:30] wire io_y_hx_0 = io_x_hx_0; // @[package.scala:267:30] wire io_y_hr_0 = io_x_hr_0; // @[package.scala:267:30] wire io_y_pw_0 = io_x_pw_0; // @[package.scala:267:30] wire io_y_px_0 = io_x_px_0; // @[package.scala:267:30] wire io_y_pr_0 = io_x_pr_0; // @[package.scala:267:30] wire io_y_ppp_0 = io_x_ppp_0; // @[package.scala:267:30] wire io_y_pal_0 = io_x_pal_0; // @[package.scala:267:30] wire io_y_paa_0 = io_x_paa_0; // @[package.scala:267:30] wire io_y_eff_0 = io_x_eff_0; // @[package.scala:267:30] wire io_y_c_0 = io_x_c_0; // @[package.scala:267:30] wire io_y_fragmented_superpage = io_x_fragmented_superpage_0; // @[package.scala:267:30] assign io_y_ppn = io_y_ppn_0; // @[package.scala:267:30] assign io_y_u = io_y_u_0; // @[package.scala:267:30] assign io_y_ae_ptw = io_y_ae_ptw_0; // @[package.scala:267:30] assign io_y_ae_final = io_y_ae_final_0; // @[package.scala:267:30] assign io_y_ae_stage2 = io_y_ae_stage2_0; // @[package.scala:267:30] assign io_y_pf = io_y_pf_0; // @[package.scala:267:30] assign io_y_gf = io_y_gf_0; // @[package.scala:267:30] assign io_y_sw = io_y_sw_0; // @[package.scala:267:30] assign io_y_sx = io_y_sx_0; // @[package.scala:267:30] assign io_y_sr = io_y_sr_0; // @[package.scala:267:30] assign io_y_hw = io_y_hw_0; // @[package.scala:267:30] assign io_y_hx = io_y_hx_0; // @[package.scala:267:30] assign io_y_hr = io_y_hr_0; // @[package.scala:267:30] assign io_y_pw = io_y_pw_0; // @[package.scala:267:30] assign io_y_px = io_y_px_0; // @[package.scala:267:30] assign io_y_pr = io_y_pr_0; // @[package.scala:267:30] assign io_y_ppp = io_y_ppp_0; // @[package.scala:267:30] assign io_y_pal = io_y_pal_0; // @[package.scala:267:30] assign io_y_paa = io_y_paa_0; // @[package.scala:267:30] assign io_y_eff = io_y_eff_0; // @[package.scala:267:30] assign io_y_c = io_y_c_0; // @[package.scala:267:30] endmodule

Generate the Verilog code corresponding to the following Chisel files. File Misc.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import scala.math._ class ParameterizedBundle(implicit p: Parameters) extends Bundle trait Clocked extends Bundle { val clock = Clock() val reset = Bool() } object DecoupledHelper { def apply(rvs: Bool*) = new DecoupledHelper(rvs) } class DecoupledHelper(val rvs: Seq[Bool]) { def fire(exclude: Bool, includes: Bool*) = { require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!") (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _) } def fire() = { rvs.reduce(_ && _) } } object MuxT { def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2)) def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3)) def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4)) } /** Creates a cascade of n MuxTs to search for a key value. */ object MuxTLookup { def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } } object ValidMux { def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]*): ValidIO[T] = { apply(v1 +: v2.toSeq) } def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = { val out = Wire(Valid(valids.head.bits.cloneType)) out.valid := valids.map(_.valid).reduce(_ || _) out.bits := MuxCase(valids.head.bits, valids.map(v => (v.valid -> v.bits))) out } } object Str { def apply(s: String): UInt = { var i = BigInt(0) require(s.forall(validChar _)) for (c <- s) i = (i << 8) | c i.U((s.length*8).W) } def apply(x: Char): UInt = { require(validChar(x)) x.U(8.W) } def apply(x: UInt): UInt = apply(x, 10) def apply(x: UInt, radix: Int): UInt = { val rad = radix.U val w = x.getWidth require(w > 0) var q = x var s = digit(q % rad) for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s) } s } def apply(x: SInt): UInt = apply(x, 10) def apply(x: SInt, radix: Int): UInt = { val neg = x < 0.S val abs = x.abs.asUInt if (radix != 10) { Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix)) } else { val rad = radix.U val w = abs.getWidth require(w > 0) var q = abs var s = digit(q % rad) var needSign = neg for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad val placeSpace = q === 0.U val space = Mux(needSign, Str('-'), Str(' ')) needSign = needSign && !placeSpace s = Cat(Mux(placeSpace, space, digit(q % rad)), s) } Cat(Mux(needSign, Str('-'), Str(' ')), s) } } private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0) private def validChar(x: Char) = x == (x & 0xFF) } object Split { def apply(x: UInt, n0: Int) = { val w = x.getWidth (x.extract(w-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n2: Int, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } } object Random { def apply(mod: Int, random: UInt): UInt = { if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0) else PriorityEncoder(partition(apply(1 << log2Up(mod*8), random), mod)) } def apply(mod: Int): UInt = apply(mod, randomizer) def oneHot(mod: Int, random: UInt): UInt = { if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0)) else PriorityEncoderOH(partition(apply(1 << log2Up(mod*8), random), mod)).asUInt } def oneHot(mod: Int): UInt = oneHot(mod, randomizer) private def randomizer = LFSR(16) private def partition(value: UInt, slices: Int) = Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U) } object Majority { def apply(in: Set[Bool]): Bool = { val n = (in.size >> 1) + 1 val clauses = in.subsets(n).map(_.reduce(_ && _)) clauses.reduce(_ || _) } def apply(in: Seq[Bool]): Bool = apply(in.toSet) def apply(in: UInt): Bool = apply(in.asBools.toSet) } object PopCountAtLeast { private def two(x: UInt): (Bool, Bool) = x.getWidth match { case 1 => (x.asBool, false.B) case n => val half = x.getWidth / 2 val (leftOne, leftTwo) = two(x(half - 1, 0)) val (rightOne, rightTwo) = two(x(x.getWidth - 1, half)) (leftOne || rightOne, leftTwo || rightTwo || (leftOne && rightOne)) } def apply(x: UInt, n: Int): Bool = n match { case 0 => true.B case 1 => x.orR case 2 => two(x)._2 case 3 => PopCount(x) >= n.U } } // This gets used everywhere, so make the smallest circuit possible ... // Given an address and size, create a mask of beatBytes size // eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111 // groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01 object MaskGen { def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = { require (groupBy >= 1 && beatBytes >= groupBy) require (isPow2(beatBytes) && isPow2(groupBy)) val lgBytes = log2Ceil(beatBytes) val sizeOH = UIntToOH(lgSize | 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) | (groupBy*2 - 1).U def helper(i: Int): Seq[(Bool, Bool)] = { if (i == 0) { Seq((lgSize >= lgBytes.asUInt, true.B)) } else { val sub = helper(i-1) val size = sizeOH(lgBytes - i) val bit = addr_lo(lgBytes - i) val nbit = !bit Seq.tabulate (1 << i) { j => val (sub_acc, sub_eq) = sub(j/2) val eq = sub_eq && (if (j % 2 == 1) bit else nbit) val acc = sub_acc || (size && eq) (acc, eq) } } } if (groupBy == beatBytes) 1.U else Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse) } } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /** Like Vec.apply(idx), but tolerates indices of mismatched width */ def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /** Any Data subtype that has a Bool member named valid. */ type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /** converts from camel case to to underscores, also removing all spaces */ def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /** converts spaces or underscores to hyphens, also lowering case */ def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y | (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y || y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /** Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation */ def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Replacement.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import freechips.rocketchip.util.property.cover abstract class ReplacementPolicy { def nBits: Int def perSet: Boolean def way: UInt def miss: Unit def hit: Unit def access(touch_way: UInt): Unit def access(touch_ways: Seq[Valid[UInt]]): Unit def state_read: UInt def get_next_state(state: UInt, touch_way: UInt): UInt def get_next_state(state: UInt, touch_ways: Seq[Valid[UInt]]): UInt = { touch_ways.foldLeft(state)((prev, touch_way) => Mux(touch_way.valid, get_next_state(prev, touch_way.bits), prev)) } def get_replace_way(state: UInt): UInt } object ReplacementPolicy { def fromString(s: String, n_ways: Int): ReplacementPolicy = s.toLowerCase match { case "random" => new RandomReplacement(n_ways) case "lru" => new TrueLRU(n_ways) case "plru" => new PseudoLRU(n_ways) case t => throw new IllegalArgumentException(s"unknown Replacement Policy type $t") } } class RandomReplacement(n_ways: Int) extends ReplacementPolicy { private val replace = Wire(Bool()) replace := false.B def nBits = 16 def perSet = false private val lfsr = LFSR(nBits, replace) def state_read = WireDefault(lfsr) def way = Random(n_ways, lfsr) def miss = replace := true.B def hit = {} def access(touch_way: UInt) = {} def access(touch_ways: Seq[Valid[UInt]]) = {} def get_next_state(state: UInt, touch_way: UInt) = 0.U //DontCare def get_replace_way(state: UInt) = way } abstract class SeqReplacementPolicy { def access(set: UInt): Unit def update(valid: Bool, hit: Bool, set: UInt, way: UInt): Unit def way: UInt } abstract class SetAssocReplacementPolicy { def access(set: UInt, touch_way: UInt): Unit def access(sets: Seq[UInt], touch_ways: Seq[Valid[UInt]]): Unit def way(set: UInt): UInt } class SeqRandom(n_ways: Int) extends SeqReplacementPolicy { val logic = new RandomReplacement(n_ways) def access(set: UInt) = { } def update(valid: Bool, hit: Bool, set: UInt, way: UInt) = { when (valid && !hit) { logic.miss } } def way = logic.way } class TrueLRU(n_ways: Int) extends ReplacementPolicy { // True LRU replacement policy, using a triangular matrix to track which sets are more recently used than others. // The matrix is packed into a single UInt (or Bits). Example 4-way (6-bits): // [5] - 3 more recent than 2 // [4] - 3 more recent than 1 // [3] - 2 more recent than 1 // [2] - 3 more recent than 0 // [1] - 2 more recent than 0 // [0] - 1 more recent than 0 def nBits = (n_ways * (n_ways-1)) / 2 def perSet = true private val state_reg = RegInit(0.U(nBits.W)) def state_read = WireDefault(state_reg) private def extractMRUVec(state: UInt): Seq[UInt] = { // Extract per-way information about which higher-indexed ways are more recently used val moreRecentVec = Wire(Vec(n_ways-1, UInt(n_ways.W))) var lsb = 0 for (i <- 0 until n_ways-1) { moreRecentVec(i) := Cat(state(lsb+n_ways-i-2,lsb), 0.U((i+1).W)) lsb = lsb + (n_ways - i - 1) } moreRecentVec } def get_next_state(state: UInt, touch_way: UInt): UInt = { val nextState = Wire(Vec(n_ways-1, UInt(n_ways.W))) val moreRecentVec = extractMRUVec(state) // reconstruct lower triangular matrix val wayDec = UIntToOH(touch_way, n_ways) // Compute next value of triangular matrix // set the touched way as more recent than every other way nextState.zipWithIndex.map { case (e, i) => e := Mux(i.U === touch_way, 0.U(n_ways.W), moreRecentVec(i) | wayDec) } nextState.zipWithIndex.tail.foldLeft((nextState.head.apply(n_ways-1,1),0)) { case ((pe,pi),(ce,ci)) => (Cat(ce.apply(n_ways-1,ci+1), pe), ci) }._1 } def access(touch_way: UInt): Unit = { state_reg := get_next_state(state_reg, touch_way) } def access(touch_ways: Seq[Valid[UInt]]): Unit = { when (touch_ways.map(_.valid).orR) { state_reg := get_next_state(state_reg, touch_ways) } for (i <- 1 until touch_ways.size) { cover(PopCount(touch_ways.map(_.valid)) === i.U, s"LRU_UpdateCount$i", s"LRU Update $i simultaneous") } } def get_replace_way(state: UInt): UInt = { val moreRecentVec = extractMRUVec(state) // reconstruct lower triangular matrix // For each way, determine if all other ways are more recent val mruWayDec = (0 until n_ways).map { i => val upperMoreRecent = (if (i == n_ways-1) true.B else moreRecentVec(i).apply(n_ways-1,i+1).andR) val lowerMoreRecent = (if (i == 0) true.B else moreRecentVec.map(e => !e(i)).reduce(_ && _)) upperMoreRecent && lowerMoreRecent } OHToUInt(mruWayDec) } def way = get_replace_way(state_reg) def miss = access(way) def hit = {} @deprecated("replace 'replace' with 'way' from abstract class ReplacementPolicy","Rocket Chip 2020.05") def replace: UInt = way } class PseudoLRU(n_ways: Int) extends ReplacementPolicy { // Pseudo-LRU tree algorithm: https://en.wikipedia.org/wiki/Pseudo-LRU#Tree-PLRU // // // - bits storage example for 4-way PLRU binary tree: // bit[2]: ways 3+2 older than ways 1+0 // / \ // bit[1]: way 3 older than way 2 bit[0]: way 1 older than way 0 // // // - bits storage example for 3-way PLRU binary tree: // bit[1]: way 2 older than ways 1+0 // \ // bit[0]: way 1 older than way 0 // // // - bits storage example for 8-way PLRU binary tree: // bit[6]: ways 7-4 older than ways 3-0 // / \ // bit[5]: ways 7+6 > 5+4 bit[2]: ways 3+2 > 1+0 // / \ / \ // bit[4]: way 7>6 bit[3]: way 5>4 bit[1]: way 3>2 bit[0]: way 1>0 def nBits = n_ways - 1 def perSet = true private val state_reg = if (nBits == 0) Reg(UInt(0.W)) else RegInit(0.U(nBits.W)) def state_read = WireDefault(state_reg) def access(touch_way: UInt): Unit = { state_reg := get_next_state(state_reg, touch_way) } def access(touch_ways: Seq[Valid[UInt]]): Unit = { when (touch_ways.map(_.valid).orR) { state_reg := get_next_state(state_reg, touch_ways) } for (i <- 1 until touch_ways.size) { cover(PopCount(touch_ways.map(_.valid)) === i.U, s"PLRU_UpdateCount$i", s"PLRU Update $i simultaneous") } } /** @param state state_reg bits for this sub-tree * @param touch_way touched way encoded value bits for this sub-tree * @param tree_nways number of ways in this sub-tree */ def get_next_state(state: UInt, touch_way: UInt, tree_nways: Int): UInt = { require(state.getWidth == (tree_nways-1), s"wrong state bits width ${state.getWidth} for $tree_nways ways") require(touch_way.getWidth == (log2Ceil(tree_nways) max 1), s"wrong encoded way width ${touch_way.getWidth} for $tree_nways ways") if (tree_nways > 2) { // we are at a branching node in the tree, so recurse val right_nways: Int = 1 << (log2Ceil(tree_nways) - 1) // number of ways in the right sub-tree val left_nways: Int = tree_nways - right_nways // number of ways in the left sub-tree val set_left_older = !touch_way(log2Ceil(tree_nways)-1) val left_subtree_state = state.extract(tree_nways-3, right_nways-1) val right_subtree_state = state(right_nways-2, 0) if (left_nways > 1) { // we are at a branching node in the tree with both left and right sub-trees, so recurse both sub-trees Cat(set_left_older, Mux(set_left_older, left_subtree_state, // if setting left sub-tree as older, do NOT recurse into left sub-tree get_next_state(left_subtree_state, touch_way.extract(log2Ceil(left_nways)-1,0), left_nways)), // recurse left if newer Mux(set_left_older, get_next_state(right_subtree_state, touch_way(log2Ceil(right_nways)-1,0), right_nways), // recurse right if newer right_subtree_state)) // if setting right sub-tree as older, do NOT recurse into right sub-tree } else { // we are at a branching node in the tree with only a right sub-tree, so recurse only right sub-tree Cat(set_left_older, Mux(set_left_older, get_next_state(right_subtree_state, touch_way(log2Ceil(right_nways)-1,0), right_nways), // recurse right if newer right_subtree_state)) // if setting right sub-tree as older, do NOT recurse into right sub-tree } } else if (tree_nways == 2) { // we are at a leaf node at the end of the tree, so set the single state bit opposite of the lsb of the touched way encoded value !touch_way(0) } else { // tree_nways <= 1 // we are at an empty node in an empty tree for 1 way, so return single zero bit for Chisel (no zero-width wires) 0.U(1.W) } } def get_next_state(state: UInt, touch_way: UInt): UInt = { val touch_way_sized = if (touch_way.getWidth < log2Ceil(n_ways)) touch_way.padTo (log2Ceil(n_ways)) else touch_way.extract(log2Ceil(n_ways)-1,0) get_next_state(state, touch_way_sized, n_ways) } /** @param state state_reg bits for this sub-tree * @param tree_nways number of ways in this sub-tree */ def get_replace_way(state: UInt, tree_nways: Int): UInt = { require(state.getWidth == (tree_nways-1), s"wrong state bits width ${state.getWidth} for $tree_nways ways") // this algorithm recursively descends the binary tree, filling in the way-to-replace encoded value from msb to lsb if (tree_nways > 2) { // we are at a branching node in the tree, so recurse val right_nways: Int = 1 << (log2Ceil(tree_nways) - 1) // number of ways in the right sub-tree val left_nways: Int = tree_nways - right_nways // number of ways in the left sub-tree val left_subtree_older = state(tree_nways-2) val left_subtree_state = state.extract(tree_nways-3, right_nways-1) val right_subtree_state = state(right_nways-2, 0) if (left_nways > 1) { // we are at a branching node in the tree with both left and right sub-trees, so recurse both sub-trees Cat(left_subtree_older, // return the top state bit (current tree node) as msb of the way-to-replace encoded value Mux(left_subtree_older, // if left sub-tree is older, recurse left, else recurse right get_replace_way(left_subtree_state, left_nways), // recurse left get_replace_way(right_subtree_state, right_nways))) // recurse right } else { // we are at a branching node in the tree with only a right sub-tree, so recurse only right sub-tree Cat(left_subtree_older, // return the top state bit (current tree node) as msb of the way-to-replace encoded value Mux(left_subtree_older, // if left sub-tree is older, return and do not recurse right 0.U(1.W), get_replace_way(right_subtree_state, right_nways))) // recurse right } } else if (tree_nways == 2) { // we are at a leaf node at the end of the tree, so just return the single state bit as lsb of the way-to-replace encoded value state(0) } else { // tree_nways <= 1 // we are at an empty node in an unbalanced tree for non-power-of-2 ways, so return single zero bit as lsb of the way-to-replace encoded value 0.U(1.W) } } def get_replace_way(state: UInt): UInt = get_replace_way(state, n_ways) def way = get_replace_way(state_reg) def miss = access(way) def hit = {} } class SeqPLRU(n_sets: Int, n_ways: Int) extends SeqReplacementPolicy { val logic = new PseudoLRU(n_ways) val state = SyncReadMem(n_sets, UInt(logic.nBits.W)) val current_state = Wire(UInt(logic.nBits.W)) val next_state = Wire(UInt(logic.nBits.W)) val plru_way = logic.get_replace_way(current_state) def access(set: UInt) = { current_state := state.read(set) } def update(valid: Bool, hit: Bool, set: UInt, way: UInt) = { val update_way = Mux(hit, way, plru_way) next_state := logic.get_next_state(current_state, update_way) when (valid) { state.write(set, next_state) } } def way = plru_way } class SetAssocLRU(n_sets: Int, n_ways: Int, policy: String) extends SetAssocReplacementPolicy { val logic = policy.toLowerCase match { case "plru" => new PseudoLRU(n_ways) case "lru" => new TrueLRU(n_ways) case t => throw new IllegalArgumentException(s"unknown Replacement Policy type $t") } val state_vec = if (logic.nBits == 0) Reg(Vec(n_sets, UInt(logic.nBits.W))) // Work around elaboration error on following line else RegInit(VecInit(Seq.fill(n_sets)(0.U(logic.nBits.W)))) def access(set: UInt, touch_way: UInt) = { state_vec(set) := logic.get_next_state(state_vec(set), touch_way) } def access(sets: Seq[UInt], touch_ways: Seq[Valid[UInt]]) = { require(sets.size == touch_ways.size, "internal consistency check: should be same number of simultaneous updates for sets and touch_ways") for (set <- 0 until n_sets) { val set_touch_ways = (sets zip touch_ways).map { case (touch_set, touch_way) => Pipe(touch_way.valid && (touch_set === set.U), touch_way.bits, 0)} when (set_touch_ways.map(_.valid).orR) { state_vec(set) := logic.get_next_state(state_vec(set), set_touch_ways) } } } def way(set: UInt) = logic.get_replace_way(state_vec(set)) } // Synthesizable unit tests import freechips.rocketchip.unittest._ class PLRUTest(n_ways: Int, timeout: Int = 500) extends UnitTest(timeout) { val plru = new PseudoLRU(n_ways) // step io.finished := RegNext(true.B, false.B) val get_replace_ways = (0 until (1 << (n_ways-1))).map(state => plru.get_replace_way(state = state.U((n_ways-1).W))) val get_next_states = (0 until (1 << (n_ways-1))).map(state => (0 until n_ways).map(way => plru.get_next_state (state = state.U((n_ways-1).W), touch_way = way.U(log2Ceil(n_ways).W)))) n_ways match { case 2 => { assert(get_replace_ways(0) === 0.U(log2Ceil(n_ways).W), s"get_replace_way state=0: expected=0 actual=%d", get_replace_ways(0)) assert(get_replace_ways(1) === 1.U(log2Ceil(n_ways).W), s"get_replace_way state=1: expected=1 actual=%d", get_replace_ways(1)) assert(get_next_states(0)(0) === 1.U(plru.nBits.W), s"get_next_state state=0 way=0: expected=1 actual=%d", get_next_states(0)(0)) assert(get_next_states(0)(1) === 0.U(plru.nBits.W), s"get_next_state state=0 way=1: expected=0 actual=%d", get_next_states(0)(1)) assert(get_next_states(1)(0) === 1.U(plru.nBits.W), s"get_next_state state=1 way=0: expected=1 actual=%d", get_next_states(1)(0)) assert(get_next_states(1)(1) === 0.U(plru.nBits.W), s"get_next_state state=1 way=1: expected=0 actual=%d", get_next_states(1)(1)) } case 3 => { assert(get_replace_ways(0) === 0.U(log2Ceil(n_ways).W), s"get_replace_way state=0: expected=0 actual=%d", get_replace_ways(0)) assert(get_replace_ways(1) === 1.U(log2Ceil(n_ways).W), s"get_replace_way state=1: expected=1 actual=%d", get_replace_ways(1)) assert(get_replace_ways(2) === 2.U(log2Ceil(n_ways).W), s"get_replace_way state=2: expected=2 actual=%d", get_replace_ways(2)) assert(get_replace_ways(3) === 2.U(log2Ceil(n_ways).W), s"get_replace_way state=3: expected=2 actual=%d", get_replace_ways(3)) assert(get_next_states(0)(0) === 3.U(plru.nBits.W), s"get_next_state state=0 way=0: expected=3 actual=%d", get_next_states(0)(0)) assert(get_next_states(0)(1) === 2.U(plru.nBits.W), s"get_next_state state=0 way=1: expected=2 actual=%d", get_next_states(0)(1)) assert(get_next_states(0)(2) === 0.U(plru.nBits.W), s"get_next_state state=0 way=2: expected=0 actual=%d", get_next_states(0)(2)) assert(get_next_states(1)(0) === 3.U(plru.nBits.W), s"get_next_state state=1 way=0: expected=3 actual=%d", get_next_states(1)(0)) assert(get_next_states(1)(1) === 2.U(plru.nBits.W), s"get_next_state state=1 way=1: expected=2 actual=%d", get_next_states(1)(1)) assert(get_next_states(1)(2) === 1.U(plru.nBits.W), s"get_next_state state=1 way=2: expected=1 actual=%d", get_next_states(1)(2)) assert(get_next_states(2)(0) === 3.U(plru.nBits.W), s"get_next_state state=2 way=0: expected=3 actual=%d", get_next_states(2)(0)) assert(get_next_states(2)(1) === 2.U(plru.nBits.W), s"get_next_state state=2 way=1: expected=2 actual=%d", get_next_states(2)(1)) assert(get_next_states(2)(2) === 0.U(plru.nBits.W), s"get_next_state state=2 way=2: expected=0 actual=%d", get_next_states(2)(2)) assert(get_next_states(3)(0) === 3.U(plru.nBits.W), s"get_next_state state=3 way=0: expected=3 actual=%d", get_next_states(3)(0)) assert(get_next_states(3)(1) === 2.U(plru.nBits.W), s"get_next_state state=3 way=1: expected=2 actual=%d", get_next_states(3)(1)) assert(get_next_states(3)(2) === 1.U(plru.nBits.W), s"get_next_state state=3 way=2: expected=1 actual=%d", get_next_states(3)(2)) } case 4 => { assert(get_replace_ways(0) === 0.U(log2Ceil(n_ways).W), s"get_replace_way state=0: expected=0 actual=%d", get_replace_ways(0)) assert(get_replace_ways(1) === 1.U(log2Ceil(n_ways).W), s"get_replace_way state=1: expected=1 actual=%d", get_replace_ways(1)) assert(get_replace_ways(2) === 0.U(log2Ceil(n_ways).W), s"get_replace_way state=2: expected=0 actual=%d", get_replace_ways(2)) assert(get_replace_ways(3) === 1.U(log2Ceil(n_ways).W), s"get_replace_way state=3: expected=1 actual=%d", get_replace_ways(3)) assert(get_replace_ways(4) === 2.U(log2Ceil(n_ways).W), s"get_replace_way state=4: expected=2 actual=%d", get_replace_ways(4)) assert(get_replace_ways(5) === 2.U(log2Ceil(n_ways).W), s"get_replace_way state=5: expected=2 actual=%d", get_replace_ways(5)) assert(get_replace_ways(6) === 3.U(log2Ceil(n_ways).W), s"get_replace_way state=6: expected=3 actual=%d", get_replace_ways(6)) assert(get_replace_ways(7) === 3.U(log2Ceil(n_ways).W), s"get_replace_way state=7: expected=3 actual=%d", get_replace_ways(7)) assert(get_next_states(0)(0) === 5.U(plru.nBits.W), s"get_next_state state=0 way=0: expected=5 actual=%d", get_next_states(0)(0)) assert(get_next_states(0)(1) === 4.U(plru.nBits.W), s"get_next_state state=0 way=1: expected=4 actual=%d", get_next_states(0)(1)) assert(get_next_states(0)(2) === 2.U(plru.nBits.W), s"get_next_state state=0 way=2: expected=2 actual=%d", get_next_states(0)(2)) assert(get_next_states(0)(3) === 0.U(plru.nBits.W), s"get_next_state state=0 way=3: expected=0 actual=%d", get_next_states(0)(3)) assert(get_next_states(1)(0) === 5.U(plru.nBits.W), s"get_next_state state=1 way=0: expected=5 actual=%d", get_next_states(1)(0)) assert(get_next_states(1)(1) === 4.U(plru.nBits.W), s"get_next_state state=1 way=1: expected=4 actual=%d", get_next_states(1)(1)) assert(get_next_states(1)(2) === 3.U(plru.nBits.W), s"get_next_state state=1 way=2: expected=3 actual=%d", get_next_states(1)(2)) assert(get_next_states(1)(3) === 1.U(plru.nBits.W), s"get_next_state state=1 way=3: expected=1 actual=%d", get_next_states(1)(3)) assert(get_next_states(2)(0) === 7.U(plru.nBits.W), s"get_next_state state=2 way=0: expected=7 actual=%d", get_next_states(2)(0)) assert(get_next_states(2)(1) === 6.U(plru.nBits.W), s"get_next_state state=2 way=1: expected=6 actual=%d", get_next_states(2)(1)) assert(get_next_states(2)(2) === 2.U(plru.nBits.W), s"get_next_state state=2 way=2: expected=2 actual=%d", get_next_states(2)(2)) assert(get_next_states(2)(3) === 0.U(plru.nBits.W), s"get_next_state state=2 way=3: expected=0 actual=%d", get_next_states(2)(3)) assert(get_next_states(3)(0) === 7.U(plru.nBits.W), s"get_next_state state=3 way=0: expected=7 actual=%d", get_next_states(3)(0)) assert(get_next_states(3)(1) === 6.U(plru.nBits.W), s"get_next_state state=3 way=1: expected=6 actual=%d", get_next_states(3)(1)) assert(get_next_states(3)(2) === 3.U(plru.nBits.W), s"get_next_state state=3 way=2: expected=3 actual=%d", get_next_states(3)(2)) assert(get_next_states(3)(3) === 1.U(plru.nBits.W), s"get_next_state state=3 way=3: expected=1 actual=%d", get_next_states(3)(3)) assert(get_next_states(4)(0) === 5.U(plru.nBits.W), s"get_next_state state=4 way=0: expected=5 actual=%d", get_next_states(4)(0)) assert(get_next_states(4)(1) === 4.U(plru.nBits.W), s"get_next_state state=4 way=1: expected=4 actual=%d", get_next_states(4)(1)) assert(get_next_states(4)(2) === 2.U(plru.nBits.W), s"get_next_state state=4 way=2: expected=2 actual=%d", get_next_states(4)(2)) assert(get_next_states(4)(3) === 0.U(plru.nBits.W), s"get_next_state state=4 way=3: expected=0 actual=%d", get_next_states(4)(3)) assert(get_next_states(5)(0) === 5.U(plru.nBits.W), s"get_next_state state=5 way=0: expected=5 actual=%d", get_next_states(5)(0)) assert(get_next_states(5)(1) === 4.U(plru.nBits.W), s"get_next_state state=5 way=1: expected=4 actual=%d", get_next_states(5)(1)) assert(get_next_states(5)(2) === 3.U(plru.nBits.W), s"get_next_state state=5 way=2: expected=3 actual=%d", get_next_states(5)(2)) assert(get_next_states(5)(3) === 1.U(plru.nBits.W), s"get_next_state state=5 way=3: expected=1 actual=%d", get_next_states(5)(3)) assert(get_next_states(6)(0) === 7.U(plru.nBits.W), s"get_next_state state=6 way=0: expected=7 actual=%d", get_next_states(6)(0)) assert(get_next_states(6)(1) === 6.U(plru.nBits.W), s"get_next_state state=6 way=1: expected=6 actual=%d", get_next_states(6)(1)) assert(get_next_states(6)(2) === 2.U(plru.nBits.W), s"get_next_state state=6 way=2: expected=2 actual=%d", get_next_states(6)(2)) assert(get_next_states(6)(3) === 0.U(plru.nBits.W), s"get_next_state state=6 way=3: expected=0 actual=%d", get_next_states(6)(3)) assert(get_next_states(7)(0) === 7.U(plru.nBits.W), s"get_next_state state=7 way=0: expected=7 actual=%d", get_next_states(7)(0)) assert(get_next_states(7)(1) === 6.U(plru.nBits.W), s"get_next_state state=7 way=5: expected=6 actual=%d", get_next_states(7)(1)) assert(get_next_states(7)(2) === 3.U(plru.nBits.W), s"get_next_state state=7 way=2: expected=3 actual=%d", get_next_states(7)(2)) assert(get_next_states(7)(3) === 1.U(plru.nBits.W), s"get_next_state state=7 way=3: expected=1 actual=%d", get_next_states(7)(3)) } case 5 => { assert(get_replace_ways( 0) === 0.U(log2Ceil(n_ways).W), s"get_replace_way state=00: expected=0 actual=%d", get_replace_ways( 0)) assert(get_replace_ways( 1) === 1.U(log2Ceil(n_ways).W), s"get_replace_way state=01: expected=1 actual=%d", get_replace_ways( 1)) assert(get_replace_ways( 2) === 0.U(log2Ceil(n_ways).W), s"get_replace_way state=02: expected=0 actual=%d", get_replace_ways( 2)) assert(get_replace_ways( 3) === 1.U(log2Ceil(n_ways).W), s"get_replace_way state=03: expected=1 actual=%d", get_replace_ways( 3)) assert(get_replace_ways( 4) === 2.U(log2Ceil(n_ways).W), s"get_replace_way state=04: expected=2 actual=%d", get_replace_ways( 4)) assert(get_replace_ways( 5) === 2.U(log2Ceil(n_ways).W), s"get_replace_way state=05: expected=2 actual=%d", get_replace_ways( 5)) assert(get_replace_ways( 6) === 3.U(log2Ceil(n_ways).W), s"get_replace_way state=06: expected=3 actual=%d", get_replace_ways( 6)) assert(get_replace_ways( 7) === 3.U(log2Ceil(n_ways).W), s"get_replace_way state=07: expected=3 actual=%d", get_replace_ways( 7)) assert(get_replace_ways( 8) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=08: expected=4 actual=%d", get_replace_ways( 8)) assert(get_replace_ways( 9) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=09: expected=4 actual=%d", get_replace_ways( 9)) assert(get_replace_ways(10) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=10: expected=4 actual=%d", get_replace_ways(10)) assert(get_replace_ways(11) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=11: expected=4 actual=%d", get_replace_ways(11)) assert(get_replace_ways(12) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=12: expected=4 actual=%d", get_replace_ways(12)) assert(get_replace_ways(13) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=13: expected=4 actual=%d", get_replace_ways(13)) assert(get_replace_ways(14) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=14: expected=4 actual=%d", get_replace_ways(14)) assert(get_replace_ways(15) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=15: expected=4 actual=%d", get_replace_ways(15)) assert(get_next_states( 0)(0) === 13.U(plru.nBits.W), s"get_next_state state=00 way=0: expected=13 actual=%d", get_next_states( 0)(0)) assert(get_next_states( 0)(1) === 12.U(plru.nBits.W), s"get_next_state state=00 way=1: expected=12 actual=%d", get_next_states( 0)(1)) assert(get_next_states( 0)(2) === 10.U(plru.nBits.W), s"get_next_state state=00 way=2: expected=10 actual=%d", get_next_states( 0)(2)) assert(get_next_states( 0)(3) === 8.U(plru.nBits.W), s"get_next_state state=00 way=3: expected=08 actual=%d", get_next_states( 0)(3)) assert(get_next_states( 0)(4) === 0.U(plru.nBits.W), s"get_next_state state=00 way=4: expected=00 actual=%d", get_next_states( 0)(4)) assert(get_next_states( 1)(0) === 13.U(plru.nBits.W), s"get_next_state state=01 way=0: expected=13 actual=%d", get_next_states( 1)(0)) assert(get_next_states( 1)(1) === 12.U(plru.nBits.W), s"get_next_state state=01 way=1: expected=12 actual=%d", get_next_states( 1)(1)) assert(get_next_states( 1)(2) === 11.U(plru.nBits.W), s"get_next_state state=01 way=2: expected=11 actual=%d", get_next_states( 1)(2)) assert(get_next_states( 1)(3) === 9.U(plru.nBits.W), s"get_next_state state=01 way=3: expected=09 actual=%d", get_next_states( 1)(3)) assert(get_next_states( 1)(4) === 1.U(plru.nBits.W), s"get_next_state state=01 way=4: expected=01 actual=%d", get_next_states( 1)(4)) assert(get_next_states( 2)(0) === 15.U(plru.nBits.W), s"get_next_state state=02 way=0: expected=15 actual=%d", get_next_states( 2)(0)) assert(get_next_states( 2)(1) === 14.U(plru.nBits.W), s"get_next_state state=02 way=1: expected=14 actual=%d", get_next_states( 2)(1)) assert(get_next_states( 2)(2) === 10.U(plru.nBits.W), s"get_next_state state=02 way=2: expected=10 actual=%d", get_next_states( 2)(2)) assert(get_next_states( 2)(3) === 8.U(plru.nBits.W), s"get_next_state state=02 way=3: expected=08 actual=%d", get_next_states( 2)(3)) assert(get_next_states( 2)(4) === 2.U(plru.nBits.W), s"get_next_state state=02 way=4: expected=02 actual=%d", get_next_states( 2)(4)) assert(get_next_states( 3)(0) === 15.U(plru.nBits.W), s"get_next_state state=03 way=0: expected=15 actual=%d", get_next_states( 3)(0)) assert(get_next_states( 3)(1) === 14.U(plru.nBits.W), s"get_next_state state=03 way=1: expected=14 actual=%d", get_next_states( 3)(1)) assert(get_next_states( 3)(2) === 11.U(plru.nBits.W), s"get_next_state state=03 way=2: expected=11 actual=%d", get_next_states( 3)(2)) assert(get_next_states( 3)(3) === 9.U(plru.nBits.W), s"get_next_state state=03 way=3: expected=09 actual=%d", get_next_states( 3)(3)) assert(get_next_states( 3)(4) === 3.U(plru.nBits.W), s"get_next_state state=03 way=4: expected=03 actual=%d", get_next_states( 3)(4)) assert(get_next_states( 4)(0) === 13.U(plru.nBits.W), s"get_next_state state=04 way=0: expected=13 actual=%d", get_next_states( 4)(0)) assert(get_next_states( 4)(1) === 12.U(plru.nBits.W), s"get_next_state state=04 way=1: expected=12 actual=%d", get_next_states( 4)(1)) assert(get_next_states( 4)(2) === 10.U(plru.nBits.W), s"get_next_state state=04 way=2: expected=10 actual=%d", get_next_states( 4)(2)) assert(get_next_states( 4)(3) === 8.U(plru.nBits.W), s"get_next_state state=04 way=3: expected=08 actual=%d", get_next_states( 4)(3)) assert(get_next_states( 4)(4) === 4.U(plru.nBits.W), s"get_next_state state=04 way=4: expected=04 actual=%d", get_next_states( 4)(4)) assert(get_next_states( 5)(0) === 13.U(plru.nBits.W), s"get_next_state state=05 way=0: expected=13 actual=%d", get_next_states( 5)(0)) assert(get_next_states( 5)(1) === 12.U(plru.nBits.W), s"get_next_state state=05 way=1: expected=12 actual=%d", get_next_states( 5)(1)) assert(get_next_states( 5)(2) === 11.U(plru.nBits.W), s"get_next_state state=05 way=2: expected=11 actual=%d", get_next_states( 5)(2)) assert(get_next_states( 5)(3) === 9.U(plru.nBits.W), s"get_next_state state=05 way=3: expected=09 actual=%d", get_next_states( 5)(3)) assert(get_next_states( 5)(4) === 5.U(plru.nBits.W), s"get_next_state state=05 way=4: expected=05 actual=%d", get_next_states( 5)(4)) assert(get_next_states( 6)(0) === 15.U(plru.nBits.W), s"get_next_state state=06 way=0: expected=15 actual=%d", get_next_states( 6)(0)) assert(get_next_states( 6)(1) === 14.U(plru.nBits.W), s"get_next_state state=06 way=1: expected=14 actual=%d", get_next_states( 6)(1)) assert(get_next_states( 6)(2) === 10.U(plru.nBits.W), s"get_next_state state=06 way=2: expected=10 actual=%d", get_next_states( 6)(2)) assert(get_next_states( 6)(3) === 8.U(plru.nBits.W), s"get_next_state state=06 way=3: expected=08 actual=%d", get_next_states( 6)(3)) assert(get_next_states( 6)(4) === 6.U(plru.nBits.W), s"get_next_state state=06 way=4: expected=06 actual=%d", get_next_states( 6)(4)) assert(get_next_states( 7)(0) === 15.U(plru.nBits.W), s"get_next_state state=07 way=0: expected=15 actual=%d", get_next_states( 7)(0)) assert(get_next_states( 7)(1) === 14.U(plru.nBits.W), s"get_next_state state=07 way=5: expected=14 actual=%d", get_next_states( 7)(1)) assert(get_next_states( 7)(2) === 11.U(plru.nBits.W), s"get_next_state state=07 way=2: expected=11 actual=%d", get_next_states( 7)(2)) assert(get_next_states( 7)(3) === 9.U(plru.nBits.W), s"get_next_state state=07 way=3: expected=09 actual=%d", get_next_states( 7)(3)) assert(get_next_states( 7)(4) === 7.U(plru.nBits.W), s"get_next_state state=07 way=4: expected=07 actual=%d", get_next_states( 7)(4)) assert(get_next_states( 8)(0) === 13.U(plru.nBits.W), s"get_next_state state=08 way=0: expected=13 actual=%d", get_next_states( 8)(0)) assert(get_next_states( 8)(1) === 12.U(plru.nBits.W), s"get_next_state state=08 way=1: expected=12 actual=%d", get_next_states( 8)(1)) assert(get_next_states( 8)(2) === 10.U(plru.nBits.W), s"get_next_state state=08 way=2: expected=10 actual=%d", get_next_states( 8)(2)) assert(get_next_states( 8)(3) === 8.U(plru.nBits.W), s"get_next_state state=08 way=3: expected=08 actual=%d", get_next_states( 8)(3)) assert(get_next_states( 8)(4) === 0.U(plru.nBits.W), s"get_next_state state=08 way=4: expected=00 actual=%d", get_next_states( 8)(4)) assert(get_next_states( 9)(0) === 13.U(plru.nBits.W), s"get_next_state state=09 way=0: expected=13 actual=%d", get_next_states( 9)(0)) assert(get_next_states( 9)(1) === 12.U(plru.nBits.W), s"get_next_state state=09 way=1: expected=12 actual=%d", get_next_states( 9)(1)) assert(get_next_states( 9)(2) === 11.U(plru.nBits.W), s"get_next_state state=09 way=2: expected=11 actual=%d", get_next_states( 9)(2)) assert(get_next_states( 9)(3) === 9.U(plru.nBits.W), s"get_next_state state=09 way=3: expected=09 actual=%d", get_next_states( 9)(3)) assert(get_next_states( 9)(4) === 1.U(plru.nBits.W), s"get_next_state state=09 way=4: expected=01 actual=%d", get_next_states( 9)(4)) assert(get_next_states(10)(0) === 15.U(plru.nBits.W), s"get_next_state state=10 way=0: expected=15 actual=%d", get_next_states(10)(0)) assert(get_next_states(10)(1) === 14.U(plru.nBits.W), s"get_next_state state=10 way=1: expected=14 actual=%d", get_next_states(10)(1)) assert(get_next_states(10)(2) === 10.U(plru.nBits.W), s"get_next_state state=10 way=2: expected=10 actual=%d", get_next_states(10)(2)) assert(get_next_states(10)(3) === 8.U(plru.nBits.W), s"get_next_state state=10 way=3: expected=08 actual=%d", get_next_states(10)(3)) assert(get_next_states(10)(4) === 2.U(plru.nBits.W), s"get_next_state state=10 way=4: expected=02 actual=%d", get_next_states(10)(4)) assert(get_next_states(11)(0) === 15.U(plru.nBits.W), s"get_next_state state=11 way=0: expected=15 actual=%d", get_next_states(11)(0)) assert(get_next_states(11)(1) === 14.U(plru.nBits.W), s"get_next_state state=11 way=1: expected=14 actual=%d", get_next_states(11)(1)) assert(get_next_states(11)(2) === 11.U(plru.nBits.W), s"get_next_state state=11 way=2: expected=11 actual=%d", get_next_states(11)(2)) assert(get_next_states(11)(3) === 9.U(plru.nBits.W), s"get_next_state state=11 way=3: expected=09 actual=%d", get_next_states(11)(3)) assert(get_next_states(11)(4) === 3.U(plru.nBits.W), s"get_next_state state=11 way=4: expected=03 actual=%d", get_next_states(11)(4)) assert(get_next_states(12)(0) === 13.U(plru.nBits.W), s"get_next_state state=12 way=0: expected=13 actual=%d", get_next_states(12)(0)) assert(get_next_states(12)(1) === 12.U(plru.nBits.W), s"get_next_state state=12 way=1: expected=12 actual=%d", get_next_states(12)(1)) assert(get_next_states(12)(2) === 10.U(plru.nBits.W), s"get_next_state state=12 way=2: expected=10 actual=%d", get_next_states(12)(2)) assert(get_next_states(12)(3) === 8.U(plru.nBits.W), s"get_next_state state=12 way=3: expected=08 actual=%d", get_next_states(12)(3)) assert(get_next_states(12)(4) === 4.U(plru.nBits.W), s"get_next_state state=12 way=4: expected=04 actual=%d", get_next_states(12)(4)) assert(get_next_states(13)(0) === 13.U(plru.nBits.W), s"get_next_state state=13 way=0: expected=13 actual=%d", get_next_states(13)(0)) assert(get_next_states(13)(1) === 12.U(plru.nBits.W), s"get_next_state state=13 way=1: expected=12 actual=%d", get_next_states(13)(1)) assert(get_next_states(13)(2) === 11.U(plru.nBits.W), s"get_next_state state=13 way=2: expected=11 actual=%d", get_next_states(13)(2)) assert(get_next_states(13)(3) === 9.U(plru.nBits.W), s"get_next_state state=13 way=3: expected=09 actual=%d", get_next_states(13)(3)) assert(get_next_states(13)(4) === 5.U(plru.nBits.W), s"get_next_state state=13 way=4: expected=05 actual=%d", get_next_states(13)(4)) assert(get_next_states(14)(0) === 15.U(plru.nBits.W), s"get_next_state state=14 way=0: expected=15 actual=%d", get_next_states(14)(0)) assert(get_next_states(14)(1) === 14.U(plru.nBits.W), s"get_next_state state=14 way=1: expected=14 actual=%d", get_next_states(14)(1)) assert(get_next_states(14)(2) === 10.U(plru.nBits.W), s"get_next_state state=14 way=2: expected=10 actual=%d", get_next_states(14)(2)) assert(get_next_states(14)(3) === 8.U(plru.nBits.W), s"get_next_state state=14 way=3: expected=08 actual=%d", get_next_states(14)(3)) assert(get_next_states(14)(4) === 6.U(plru.nBits.W), s"get_next_state state=14 way=4: expected=06 actual=%d", get_next_states(14)(4)) assert(get_next_states(15)(0) === 15.U(plru.nBits.W), s"get_next_state state=15 way=0: expected=15 actual=%d", get_next_states(15)(0)) assert(get_next_states(15)(1) === 14.U(plru.nBits.W), s"get_next_state state=15 way=5: expected=14 actual=%d", get_next_states(15)(1)) assert(get_next_states(15)(2) === 11.U(plru.nBits.W), s"get_next_state state=15 way=2: expected=11 actual=%d", get_next_states(15)(2)) assert(get_next_states(15)(3) === 9.U(plru.nBits.W), s"get_next_state state=15 way=3: expected=09 actual=%d", get_next_states(15)(3)) assert(get_next_states(15)(4) === 7.U(plru.nBits.W), s"get_next_state state=15 way=4: expected=07 actual=%d", get_next_states(15)(4)) } case 6 => { assert(get_replace_ways( 0) === 0.U(log2Ceil(n_ways).W), s"get_replace_way state=00: expected=0 actual=%d", get_replace_ways( 0)) assert(get_replace_ways( 1) === 1.U(log2Ceil(n_ways).W), s"get_replace_way state=01: expected=1 actual=%d", get_replace_ways( 1)) assert(get_replace_ways( 2) === 0.U(log2Ceil(n_ways).W), s"get_replace_way state=02: expected=0 actual=%d", get_replace_ways( 2)) assert(get_replace_ways( 3) === 1.U(log2Ceil(n_ways).W), s"get_replace_way state=03: expected=1 actual=%d", get_replace_ways( 3)) assert(get_replace_ways( 4) === 2.U(log2Ceil(n_ways).W), s"get_replace_way state=04: expected=2 actual=%d", get_replace_ways( 4)) assert(get_replace_ways( 5) === 2.U(log2Ceil(n_ways).W), s"get_replace_way state=05: expected=2 actual=%d", get_replace_ways( 5)) assert(get_replace_ways( 6) === 3.U(log2Ceil(n_ways).W), s"get_replace_way state=06: expected=3 actual=%d", get_replace_ways( 6)) assert(get_replace_ways( 7) === 3.U(log2Ceil(n_ways).W), s"get_replace_way state=07: expected=3 actual=%d", get_replace_ways( 7)) assert(get_replace_ways( 8) === 0.U(log2Ceil(n_ways).W), s"get_replace_way state=08: expected=0 actual=%d", get_replace_ways( 8)) assert(get_replace_ways( 9) === 1.U(log2Ceil(n_ways).W), s"get_replace_way state=09: expected=1 actual=%d", get_replace_ways( 9)) assert(get_replace_ways(10) === 0.U(log2Ceil(n_ways).W), s"get_replace_way state=10: expected=0 actual=%d", get_replace_ways(10)) assert(get_replace_ways(11) === 1.U(log2Ceil(n_ways).W), s"get_replace_way state=11: expected=1 actual=%d", get_replace_ways(11)) assert(get_replace_ways(12) === 2.U(log2Ceil(n_ways).W), s"get_replace_way state=12: expected=2 actual=%d", get_replace_ways(12)) assert(get_replace_ways(13) === 2.U(log2Ceil(n_ways).W), s"get_replace_way state=13: expected=2 actual=%d", get_replace_ways(13)) assert(get_replace_ways(14) === 3.U(log2Ceil(n_ways).W), s"get_replace_way state=14: expected=3 actual=%d", get_replace_ways(14)) assert(get_replace_ways(15) === 3.U(log2Ceil(n_ways).W), s"get_replace_way state=15: expected=3 actual=%d", get_replace_ways(15)) assert(get_replace_ways(16) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=16: expected=4 actual=%d", get_replace_ways(16)) assert(get_replace_ways(17) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=17: expected=4 actual=%d", get_replace_ways(17)) assert(get_replace_ways(18) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=18: expected=4 actual=%d", get_replace_ways(18)) assert(get_replace_ways(19) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=19: expected=4 actual=%d", get_replace_ways(19)) assert(get_replace_ways(20) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=20: expected=4 actual=%d", get_replace_ways(20)) assert(get_replace_ways(21) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=21: expected=4 actual=%d", get_replace_ways(21)) assert(get_replace_ways(22) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=22: expected=4 actual=%d", get_replace_ways(22)) assert(get_replace_ways(23) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=23: expected=4 actual=%d", get_replace_ways(23)) assert(get_replace_ways(24) === 5.U(log2Ceil(n_ways).W), s"get_replace_way state=24: expected=5 actual=%d", get_replace_ways(24)) assert(get_replace_ways(25) === 5.U(log2Ceil(n_ways).W), s"get_replace_way state=25: expected=5 actual=%d", get_replace_ways(25)) assert(get_replace_ways(26) === 5.U(log2Ceil(n_ways).W), s"get_replace_way state=26: expected=5 actual=%d", get_replace_ways(26)) assert(get_replace_ways(27) === 5.U(log2Ceil(n_ways).W), s"get_replace_way state=27: expected=5 actual=%d", get_replace_ways(27)) assert(get_replace_ways(28) === 5.U(log2Ceil(n_ways).W), s"get_replace_way state=28: expected=5 actual=%d", get_replace_ways(28)) assert(get_replace_ways(29) === 5.U(log2Ceil(n_ways).W), s"get_replace_way state=29: expected=5 actual=%d", get_replace_ways(29)) assert(get_replace_ways(30) === 5.U(log2Ceil(n_ways).W), s"get_replace_way state=30: expected=5 actual=%d", get_replace_ways(30)) assert(get_replace_ways(31) === 5.U(log2Ceil(n_ways).W), s"get_replace_way state=31: expected=5 actual=%d", get_replace_ways(31)) } case _ => throw new IllegalArgumentException(s"no test pattern found for n_ways=$n_ways") } } File Consts.scala: // See LICENSE.Berkeley for license details. package freechips.rocketchip.rocket.constants import chisel3._ import chisel3.util._ import freechips.rocketchip.util._ trait ScalarOpConstants { val SZ_BR = 3 def BR_X = BitPat("b???") def BR_EQ = 0.U(3.W) def BR_NE = 1.U(3.W) def BR_J = 2.U(3.W) def BR_N = 3.U(3.W) def BR_LT = 4.U(3.W) def BR_GE = 5.U(3.W) def BR_LTU = 6.U(3.W) def BR_GEU = 7.U(3.W) def A1_X = BitPat("b??") def A1_ZERO = 0.U(2.W) def A1_RS1 = 1.U(2.W) def A1_PC = 2.U(2.W) def A1_RS1SHL = 3.U(2.W) def IMM_X = BitPat("b???") def IMM_S = 0.U(3.W) def IMM_SB = 1.U(3.W) def IMM_U = 2.U(3.W) def IMM_UJ = 3.U(3.W) def IMM_I = 4.U(3.W) def IMM_Z = 5.U(3.W) def A2_X = BitPat("b???") def A2_ZERO = 0.U(3.W) def A2_SIZE = 1.U(3.W) def A2_RS2 = 2.U(3.W) def A2_IMM = 3.U(3.W) def A2_RS2OH = 4.U(3.W) def A2_IMMOH = 5.U(3.W) def X = BitPat("b?") def N = BitPat("b0") def Y = BitPat("b1") val SZ_DW = 1 def DW_X = X def DW_32 = false.B def DW_64 = true.B def DW_XPR = DW_64 } trait MemoryOpConstants { val NUM_XA_OPS = 9 val M_SZ = 5 def M_X = BitPat("b?????"); def M_XRD = "b00000".U; // int load def M_XWR = "b00001".U; // int store def M_PFR = "b00010".U; // prefetch with intent to read def M_PFW = "b00011".U; // prefetch with intent to write def M_XA_SWAP = "b00100".U def M_FLUSH_ALL = "b00101".U // flush all lines def M_XLR = "b00110".U def M_XSC = "b00111".U def M_XA_ADD = "b01000".U def M_XA_XOR = "b01001".U def M_XA_OR = "b01010".U def M_XA_AND = "b01011".U def M_XA_MIN = "b01100".U def M_XA_MAX = "b01101".U def M_XA_MINU = "b01110".U def M_XA_MAXU = "b01111".U def M_FLUSH = "b10000".U // write back dirty data and cede R/W permissions def M_PWR = "b10001".U // partial (masked) store def M_PRODUCE = "b10010".U // write back dirty data and cede W permissions def M_CLEAN = "b10011".U // write back dirty data and retain R/W permissions def M_SFENCE = "b10100".U // SFENCE.VMA def M_HFENCEV = "b10101".U // HFENCE.VVMA def M_HFENCEG = "b10110".U // HFENCE.GVMA def M_WOK = "b10111".U // check write permissions but don't perform a write def M_HLVX = "b10000".U // HLVX instruction def isAMOLogical(cmd: UInt) = cmd.isOneOf(M_XA_SWAP, M_XA_XOR, M_XA_OR, M_XA_AND) def isAMOArithmetic(cmd: UInt) = cmd.isOneOf(M_XA_ADD, M_XA_MIN, M_XA_MAX, M_XA_MINU, M_XA_MAXU) def isAMO(cmd: UInt) = isAMOLogical(cmd) || isAMOArithmetic(cmd) def isPrefetch(cmd: UInt) = cmd === M_PFR || cmd === M_PFW def isRead(cmd: UInt) = cmd.isOneOf(M_XRD, M_HLVX, M_XLR, M_XSC) || isAMO(cmd) def isWrite(cmd: UInt) = cmd === M_XWR || cmd === M_PWR || cmd === M_XSC || isAMO(cmd) def isWriteIntent(cmd: UInt) = isWrite(cmd) || cmd === M_PFW || cmd === M_XLR } File TLB.scala: // See LICENSE.SiFive for license details. // See LICENSE.Berkeley for license details. package freechips.rocketchip.rocket import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config._ import freechips.rocketchip.devices.debug.DebugModuleKey import freechips.rocketchip.diplomacy.RegionType import freechips.rocketchip.subsystem.CacheBlockBytes import freechips.rocketchip.tile.{CoreModule, CoreBundle} import freechips.rocketchip.tilelink._ import freechips.rocketchip.util.{OptimizationBarrier, SetAssocLRU, PseudoLRU, PopCountAtLeast, property} import freechips.rocketchip.util.BooleanToAugmentedBoolean import freechips.rocketchip.util.IntToAugmentedInt import freechips.rocketchip.util.UIntToAugmentedUInt import freechips.rocketchip.util.UIntIsOneOf import freechips.rocketchip.util.SeqToAugmentedSeq import freechips.rocketchip.util.SeqBoolBitwiseOps case object ASIdBits extends Field[Int](0) case object VMIdBits extends Field[Int](0) /** =SFENCE= * rs1 rs2 * {{{ * 0 0 -> flush All * 0 1 -> flush by ASID * 1 1 -> flush by ADDR * 1 0 -> flush by ADDR and ASID * }}} * {{{ * If rs1=x0 and rs2=x0, the fence orders all reads and writes made to any level of the page tables, for all address spaces. * If rs1=x0 and rs2!=x0, the fence orders all reads and writes made to any level of the page tables, but only for the address space identified by integer register rs2. Accesses to global mappings (see Section 4.3.1) are not ordered. * If rs1!=x0 and rs2=x0, the fence orders only reads and writes made to the leaf page table entry corresponding to the virtual address in rs1, for all address spaces. * If rs1!=x0 and rs2!=x0, the fence orders only reads and writes made to the leaf page table entry corresponding to the virtual address in rs1, for the address space identified by integer register rs2. Accesses to global mappings are not ordered. * }}} */ class SFenceReq(implicit p: Parameters) extends CoreBundle()(p) { val rs1 = Bool() val rs2 = Bool() val addr = UInt(vaddrBits.W) val asid = UInt((asIdBits max 1).W) // TODO zero-width val hv = Bool() val hg = Bool() } class TLBReq(lgMaxSize: Int)(implicit p: Parameters) extends CoreBundle()(p) { /** request address from CPU. */ val vaddr = UInt(vaddrBitsExtended.W) /** don't lookup TLB, bypass vaddr as paddr */ val passthrough = Bool() /** granularity */ val size = UInt(log2Ceil(lgMaxSize + 1).W) /** memory command. */ val cmd = Bits(M_SZ.W) val prv = UInt(PRV.SZ.W) /** virtualization mode */ val v = Bool() } class TLBExceptions extends Bundle { val ld = Bool() val st = Bool() val inst = Bool() } class TLBResp(lgMaxSize: Int = 3)(implicit p: Parameters) extends CoreBundle()(p) { // lookup responses val miss = Bool() /** physical address */ val paddr = UInt(paddrBits.W) val gpa = UInt(vaddrBitsExtended.W) val gpa_is_pte = Bool() /** page fault exception */ val pf = new TLBExceptions /** guest page fault exception */ val gf = new TLBExceptions /** access exception */ val ae = new TLBExceptions /** misaligned access exception */ val ma = new TLBExceptions /** if this address is cacheable */ val cacheable = Bool() /** if caches must allocate this address */ val must_alloc = Bool() /** if this address is prefetchable for caches*/ val prefetchable = Bool() /** size/cmd of request that generated this response*/ val size = UInt(log2Ceil(lgMaxSize + 1).W) val cmd = UInt(M_SZ.W) } class TLBEntryData(implicit p: Parameters) extends CoreBundle()(p) { val ppn = UInt(ppnBits.W) /** pte.u user */ val u = Bool() /** pte.g global */ val g = Bool() /** access exception. * D$ -> PTW -> TLB AE * Alignment failed. */ val ae_ptw = Bool() val ae_final = Bool() val ae_stage2 = Bool() /** page fault */ val pf = Bool() /** guest page fault */ val gf = Bool() /** supervisor write */ val sw = Bool() /** supervisor execute */ val sx = Bool() /** supervisor read */ val sr = Bool() /** hypervisor write */ val hw = Bool() /** hypervisor excute */ val hx = Bool() /** hypervisor read */ val hr = Bool() /** prot_w */ val pw = Bool() /** prot_x */ val px = Bool() /** prot_r */ val pr = Bool() /** PutPartial */ val ppp = Bool() /** AMO logical */ val pal = Bool() /** AMO arithmetic */ val paa = Bool() /** get/put effects */ val eff = Bool() /** cacheable */ val c = Bool() /** fragmented_superpage support */ val fragmented_superpage = Bool() } /** basic cell for TLB data */ class TLBEntry(val nSectors: Int, val superpage: Boolean, val superpageOnly: Boolean)(implicit p: Parameters) extends CoreBundle()(p) { require(nSectors == 1 || !superpage) require(!superpageOnly || superpage) val level = UInt(log2Ceil(pgLevels).W) /** use vpn as tag */ val tag_vpn = UInt(vpnBits.W) /** tag in vitualization mode */ val tag_v = Bool() /** entry data */ val data = Vec(nSectors, UInt(new TLBEntryData().getWidth.W)) /** valid bit */ val valid = Vec(nSectors, Bool()) /** returns all entry data in this entry */ def entry_data = data.map(_.asTypeOf(new TLBEntryData)) /** returns the index of sector */ private def sectorIdx(vpn: UInt) = vpn.extract(nSectors.log2-1, 0) /** returns the entry data matched with this vpn*/ def getData(vpn: UInt) = OptimizationBarrier(data(sectorIdx(vpn)).asTypeOf(new TLBEntryData)) /** returns whether a sector hits */ def sectorHit(vpn: UInt, virtual: Bool) = valid.orR && sectorTagMatch(vpn, virtual) /** returns whether tag matches vpn */ def sectorTagMatch(vpn: UInt, virtual: Bool) = (((tag_vpn ^ vpn) >> nSectors.log2) === 0.U) && (tag_v === virtual) /** returns hit signal */ def hit(vpn: UInt, virtual: Bool): Bool = { if (superpage && usingVM) { var tagMatch = valid.head && (tag_v === virtual) for (j <- 0 until pgLevels) { val base = (pgLevels - 1 - j) * pgLevelBits val n = pgLevelBits + (if (j == 0) hypervisorExtraAddrBits else 0) val ignore = level < j.U || (superpageOnly && j == pgLevels - 1).B tagMatch = tagMatch && (ignore || (tag_vpn ^ vpn)(base + n - 1, base) === 0.U) } tagMatch } else { val idx = sectorIdx(vpn) valid(idx) && sectorTagMatch(vpn, virtual) } } /** returns the ppn of the input TLBEntryData */ def ppn(vpn: UInt, data: TLBEntryData) = { val supervisorVPNBits = pgLevels * pgLevelBits if (superpage && usingVM) { var res = data.ppn >> pgLevelBits*(pgLevels - 1) for (j <- 1 until pgLevels) { val ignore = level < j.U || (superpageOnly && j == pgLevels - 1).B res = Cat(res, (Mux(ignore, vpn, 0.U) | data.ppn)(supervisorVPNBits - j*pgLevelBits - 1, supervisorVPNBits - (j + 1)*pgLevelBits)) } res } else { data.ppn } } /** does the refill * * find the target entry with vpn tag * and replace the target entry with the input entry data */ def insert(vpn: UInt, virtual: Bool, level: UInt, entry: TLBEntryData): Unit = { this.tag_vpn := vpn this.tag_v := virtual this.level := level.extract(log2Ceil(pgLevels - superpageOnly.toInt)-1, 0) val idx = sectorIdx(vpn) valid(idx) := true.B data(idx) := entry.asUInt } def invalidate(): Unit = { valid.foreach(_ := false.B) } def invalidate(virtual: Bool): Unit = { for ((v, e) <- valid zip entry_data) when (tag_v === virtual) { v := false.B } } def invalidateVPN(vpn: UInt, virtual: Bool): Unit = { if (superpage) { when (hit(vpn, virtual)) { invalidate() } } else { when (sectorTagMatch(vpn, virtual)) { for (((v, e), i) <- (valid zip entry_data).zipWithIndex) when (tag_v === virtual && i.U === sectorIdx(vpn)) { v := false.B } } } // For fragmented superpage mappings, we assume the worst (largest) // case, and zap entries whose most-significant VPNs match when (((tag_vpn ^ vpn) >> (pgLevelBits * (pgLevels - 1))) === 0.U) { for ((v, e) <- valid zip entry_data) when (tag_v === virtual && e.fragmented_superpage) { v := false.B } } } def invalidateNonGlobal(virtual: Bool): Unit = { for ((v, e) <- valid zip entry_data) when (tag_v === virtual && !e.g) { v := false.B } } } /** TLB config * * @param nSets the number of sets of PTE, follow [[ICacheParams.nSets]] * @param nWays the total number of wayss of PTE, follow [[ICacheParams.nWays]] * @param nSectors the number of ways in a single PTE TLBEntry * @param nSuperpageEntries the number of SuperpageEntries */ case class TLBConfig( nSets: Int, nWays: Int, nSectors: Int = 4, nSuperpageEntries: Int = 4) /** =Overview= * [[TLB]] is a TLB template which contains PMA logic and PMP checker. * * TLB caches PTE and accelerates the address translation process. * When tlb miss happens, ask PTW(L2TLB) for Page Table Walk. * Perform PMP and PMA check during the translation and throw exception if there were any. * * ==Cache Structure== * - Sectored Entry (PTE) * - set-associative or direct-mapped * - nsets = [[TLBConfig.nSets]] * - nways = [[TLBConfig.nWays]] / [[TLBConfig.nSectors]] * - PTEEntry( sectors = [[TLBConfig.nSectors]] ) * - LRU(if set-associative) * * - Superpage Entry(superpage PTE) * - fully associative * - nsets = [[TLBConfig.nSuperpageEntries]] * - PTEEntry(sectors = 1) * - PseudoLRU * * - Special Entry(PTE across PMP) * - nsets = 1 * - PTEEntry(sectors = 1) * * ==Address structure== * {{{ * |vaddr | * |ppn/vpn | pgIndex | * | | | * | |nSets |nSector | |}}} * * ==State Machine== * {{{ * s_ready: ready to accept request from CPU. * s_request: when L1TLB(this) miss, send request to PTW(L2TLB), . * s_wait: wait for PTW to refill L1TLB. * s_wait_invalidate: L1TLB is waiting for respond from PTW, but L1TLB will invalidate respond from PTW.}}} * * ==PMP== * pmp check * - special_entry: always check * - other entry: check on refill * * ==Note== * PMA consume diplomacy parameter generate physical memory address checking logic * * Boom use Rocket ITLB, and its own DTLB. * * Accelerators:{{{ * sha3: DTLB * gemmini: DTLB * hwacha: DTLB*2+ITLB}}} * @param instruction true for ITLB, false for DTLB * @param lgMaxSize @todo seems granularity * @param cfg [[TLBConfig]] * @param edge collect SoC metadata. */ class TLB(instruction: Boolean, lgMaxSize: Int, cfg: TLBConfig)(implicit edge: TLEdgeOut, p: Parameters) extends CoreModule()(p) { override def desiredName = if (instruction) "ITLB" else "DTLB" val io = IO(new Bundle { /** request from Core */ val req = Flipped(Decoupled(new TLBReq(lgMaxSize))) /** response to Core */ val resp = Output(new TLBResp(lgMaxSize)) /** SFence Input */ val sfence = Flipped(Valid(new SFenceReq)) /** IO to PTW */ val ptw = new TLBPTWIO /** suppress a TLB refill, one cycle after a miss */ val kill = Input(Bool()) }) io.ptw.customCSRs := DontCare val pageGranularityPMPs = pmpGranularity >= (1 << pgIdxBits) val vpn = io.req.bits.vaddr(vaddrBits-1, pgIdxBits) /** index for sectored_Entry */ val memIdx = vpn.extract(cfg.nSectors.log2 + cfg.nSets.log2 - 1, cfg.nSectors.log2) /** TLB Entry */ val sectored_entries = Reg(Vec(cfg.nSets, Vec(cfg.nWays / cfg.nSectors, new TLBEntry(cfg.nSectors, false, false)))) /** Superpage Entry */ val superpage_entries = Reg(Vec(cfg.nSuperpageEntries, new TLBEntry(1, true, true))) /** Special Entry * * If PMP granularity is less than page size, thus need additional "special" entry manage PMP. */ val special_entry = (!pageGranularityPMPs).option(Reg(new TLBEntry(1, true, false))) def ordinary_entries = sectored_entries(memIdx) ++ superpage_entries def all_entries = ordinary_entries ++ special_entry def all_real_entries = sectored_entries.flatten ++ superpage_entries ++ special_entry val s_ready :: s_request :: s_wait :: s_wait_invalidate :: Nil = Enum(4) val state = RegInit(s_ready) // use vpn as refill_tag val r_refill_tag = Reg(UInt(vpnBits.W)) val r_superpage_repl_addr = Reg(UInt(log2Ceil(superpage_entries.size).W)) val r_sectored_repl_addr = Reg(UInt(log2Ceil(sectored_entries.head.size).W)) val r_sectored_hit = Reg(Valid(UInt(log2Ceil(sectored_entries.head.size).W))) val r_superpage_hit = Reg(Valid(UInt(log2Ceil(superpage_entries.size).W))) val r_vstage1_en = Reg(Bool()) val r_stage2_en = Reg(Bool()) val r_need_gpa = Reg(Bool()) val r_gpa_valid = Reg(Bool()) val r_gpa = Reg(UInt(vaddrBits.W)) val r_gpa_vpn = Reg(UInt(vpnBits.W)) val r_gpa_is_pte = Reg(Bool()) /** privilege mode */ val priv = io.req.bits.prv val priv_v = usingHypervisor.B && io.req.bits.v val priv_s = priv(0) // user mode and supervisor mode val priv_uses_vm = priv <= PRV.S.U val satp = Mux(priv_v, io.ptw.vsatp, io.ptw.ptbr) val stage1_en = usingVM.B && satp.mode(satp.mode.getWidth-1) /** VS-stage translation enable */ val vstage1_en = usingHypervisor.B && priv_v && io.ptw.vsatp.mode(io.ptw.vsatp.mode.getWidth-1) /** G-stage translation enable */ val stage2_en = usingHypervisor.B && priv_v && io.ptw.hgatp.mode(io.ptw.hgatp.mode.getWidth-1) /** Enable Virtual Memory when: * 1. statically configured * 1. satp highest bits enabled * i. RV32: * - 0 -> Bare * - 1 -> SV32 * i. RV64: * - 0000 -> Bare * - 1000 -> SV39 * - 1001 -> SV48 * - 1010 -> SV57 * - 1011 -> SV64 * 1. In virtualization mode, vsatp highest bits enabled * 1. priv mode in U and S. * 1. in H & M mode, disable VM. * 1. no passthrough(micro-arch defined.) * * @see RV-priv spec 4.1.11 Supervisor Address Translation and Protection (satp) Register * @see RV-priv spec 8.2.18 Virtual Supervisor Address Translation and Protection Register (vsatp) */ val vm_enabled = (stage1_en || stage2_en) && priv_uses_vm && !io.req.bits.passthrough // flush guest entries on vsatp.MODE Bare <-> SvXX transitions val v_entries_use_stage1 = RegInit(false.B) val vsatp_mode_mismatch = priv_v && (vstage1_en =/= v_entries_use_stage1) && !io.req.bits.passthrough // share a single physical memory attribute checker (unshare if critical path) val refill_ppn = io.ptw.resp.bits.pte.ppn(ppnBits-1, 0) /** refill signal */ val do_refill = usingVM.B && io.ptw.resp.valid /** sfence invalidate refill */ val invalidate_refill = state.isOneOf(s_request /* don't care */, s_wait_invalidate) || io.sfence.valid // PMP val mpu_ppn = Mux(do_refill, refill_ppn, Mux(vm_enabled && special_entry.nonEmpty.B, special_entry.map(e => e.ppn(vpn, e.getData(vpn))).getOrElse(0.U), io.req.bits.vaddr >> pgIdxBits)) val mpu_physaddr = Cat(mpu_ppn, io.req.bits.vaddr(pgIdxBits-1, 0)) val mpu_priv = Mux[UInt](usingVM.B && (do_refill || io.req.bits.passthrough /* PTW */), PRV.S.U, Cat(io.ptw.status.debug, priv)) val pmp = Module(new PMPChecker(lgMaxSize)) pmp.io.addr := mpu_physaddr pmp.io.size := io.req.bits.size pmp.io.pmp := (io.ptw.pmp: Seq[PMP]) pmp.io.prv := mpu_priv val pma = Module(new PMAChecker(edge.manager)(p)) pma.io.paddr := mpu_physaddr // todo: using DataScratchpad doesn't support cacheable. val cacheable = pma.io.resp.cacheable && (instruction || !usingDataScratchpad).B val homogeneous = TLBPageLookup(edge.manager.managers, xLen, p(CacheBlockBytes), BigInt(1) << pgIdxBits, 1 << lgMaxSize)(mpu_physaddr).homogeneous // In M mode, if access DM address(debug module program buffer) val deny_access_to_debug = mpu_priv <= PRV.M.U && p(DebugModuleKey).map(dmp => dmp.address.contains(mpu_physaddr)).getOrElse(false.B) val prot_r = pma.io.resp.r && !deny_access_to_debug && pmp.io.r val prot_w = pma.io.resp.w && !deny_access_to_debug && pmp.io.w val prot_pp = pma.io.resp.pp val prot_al = pma.io.resp.al val prot_aa = pma.io.resp.aa val prot_x = pma.io.resp.x && !deny_access_to_debug && pmp.io.x val prot_eff = pma.io.resp.eff // hit check val sector_hits = sectored_entries(memIdx).map(_.sectorHit(vpn, priv_v)) val superpage_hits = superpage_entries.map(_.hit(vpn, priv_v)) val hitsVec = all_entries.map(vm_enabled && _.hit(vpn, priv_v)) val real_hits = hitsVec.asUInt val hits = Cat(!vm_enabled, real_hits) // use ptw response to refill // permission bit arrays when (do_refill) { val pte = io.ptw.resp.bits.pte val refill_v = r_vstage1_en || r_stage2_en val newEntry = Wire(new TLBEntryData) newEntry.ppn := pte.ppn newEntry.c := cacheable newEntry.u := pte.u newEntry.g := pte.g && pte.v newEntry.ae_ptw := io.ptw.resp.bits.ae_ptw newEntry.ae_final := io.ptw.resp.bits.ae_final newEntry.ae_stage2 := io.ptw.resp.bits.ae_final && io.ptw.resp.bits.gpa_is_pte && r_stage2_en newEntry.pf := io.ptw.resp.bits.pf newEntry.gf := io.ptw.resp.bits.gf newEntry.hr := io.ptw.resp.bits.hr newEntry.hw := io.ptw.resp.bits.hw newEntry.hx := io.ptw.resp.bits.hx newEntry.sr := pte.sr() newEntry.sw := pte.sw() newEntry.sx := pte.sx() newEntry.pr := prot_r newEntry.pw := prot_w newEntry.px := prot_x newEntry.ppp := prot_pp newEntry.pal := prot_al newEntry.paa := prot_aa newEntry.eff := prot_eff newEntry.fragmented_superpage := io.ptw.resp.bits.fragmented_superpage // refill special_entry when (special_entry.nonEmpty.B && !io.ptw.resp.bits.homogeneous) { special_entry.foreach(_.insert(r_refill_tag, refill_v, io.ptw.resp.bits.level, newEntry)) }.elsewhen (io.ptw.resp.bits.level < (pgLevels-1).U) { val waddr = Mux(r_superpage_hit.valid && usingHypervisor.B, r_superpage_hit.bits, r_superpage_repl_addr) for ((e, i) <- superpage_entries.zipWithIndex) when (r_superpage_repl_addr === i.U) { e.insert(r_refill_tag, refill_v, io.ptw.resp.bits.level, newEntry) when (invalidate_refill) { e.invalidate() } } // refill sectored_hit }.otherwise { val r_memIdx = r_refill_tag.extract(cfg.nSectors.log2 + cfg.nSets.log2 - 1, cfg.nSectors.log2) val waddr = Mux(r_sectored_hit.valid, r_sectored_hit.bits, r_sectored_repl_addr) for ((e, i) <- sectored_entries(r_memIdx).zipWithIndex) when (waddr === i.U) { when (!r_sectored_hit.valid) { e.invalidate() } e.insert(r_refill_tag, refill_v, 0.U, newEntry) when (invalidate_refill) { e.invalidate() } } } r_gpa_valid := io.ptw.resp.bits.gpa.valid r_gpa := io.ptw.resp.bits.gpa.bits r_gpa_is_pte := io.ptw.resp.bits.gpa_is_pte } // get all entries data. val entries = all_entries.map(_.getData(vpn)) val normal_entries = entries.take(ordinary_entries.size) // parallel query PPN from [[all_entries]], if VM not enabled return VPN instead val ppn = Mux1H(hitsVec :+ !vm_enabled, (all_entries zip entries).map{ case (entry, data) => entry.ppn(vpn, data) } :+ vpn(ppnBits-1, 0)) val nPhysicalEntries = 1 + special_entry.size // generally PTW misaligned load exception. val ptw_ae_array = Cat(false.B, entries.map(_.ae_ptw).asUInt) val final_ae_array = Cat(false.B, entries.map(_.ae_final).asUInt) val ptw_pf_array = Cat(false.B, entries.map(_.pf).asUInt) val ptw_gf_array = Cat(false.B, entries.map(_.gf).asUInt) val sum = Mux(priv_v, io.ptw.gstatus.sum, io.ptw.status.sum) // if in hypervisor/machine mode, cannot read/write user entries. // if in superviosr/user mode, "If the SUM bit in the sstatus register is set, supervisor mode software may also access pages with U=1.(from spec)" val priv_rw_ok = Mux(!priv_s || sum, entries.map(_.u).asUInt, 0.U) | Mux(priv_s, ~entries.map(_.u).asUInt, 0.U) // if in hypervisor/machine mode, other than user pages, all pages are executable. // if in superviosr/user mode, only user page can execute. val priv_x_ok = Mux(priv_s, ~entries.map(_.u).asUInt, entries.map(_.u).asUInt) val stage1_bypass = Fill(entries.size, usingHypervisor.B) & (Fill(entries.size, !stage1_en) | entries.map(_.ae_stage2).asUInt) val mxr = io.ptw.status.mxr | Mux(priv_v, io.ptw.gstatus.mxr, false.B) // "The vsstatus field MXR, which makes execute-only pages readable, only overrides VS-stage page protection.(from spec)" val r_array = Cat(true.B, (priv_rw_ok & (entries.map(_.sr).asUInt | Mux(mxr, entries.map(_.sx).asUInt, 0.U))) | stage1_bypass) val w_array = Cat(true.B, (priv_rw_ok & entries.map(_.sw).asUInt) | stage1_bypass) val x_array = Cat(true.B, (priv_x_ok & entries.map(_.sx).asUInt) | stage1_bypass) val stage2_bypass = Fill(entries.size, !stage2_en) val hr_array = Cat(true.B, entries.map(_.hr).asUInt | Mux(io.ptw.status.mxr, entries.map(_.hx).asUInt, 0.U) | stage2_bypass) val hw_array = Cat(true.B, entries.map(_.hw).asUInt | stage2_bypass) val hx_array = Cat(true.B, entries.map(_.hx).asUInt | stage2_bypass) // These array is for each TLB entries. // user mode can read: PMA OK, TLB OK, AE OK val pr_array = Cat(Fill(nPhysicalEntries, prot_r), normal_entries.map(_.pr).asUInt) & ~(ptw_ae_array | final_ae_array) // user mode can write: PMA OK, TLB OK, AE OK val pw_array = Cat(Fill(nPhysicalEntries, prot_w), normal_entries.map(_.pw).asUInt) & ~(ptw_ae_array | final_ae_array) // user mode can write: PMA OK, TLB OK, AE OK val px_array = Cat(Fill(nPhysicalEntries, prot_x), normal_entries.map(_.px).asUInt) & ~(ptw_ae_array | final_ae_array) // put effect val eff_array = Cat(Fill(nPhysicalEntries, prot_eff), normal_entries.map(_.eff).asUInt) // cacheable val c_array = Cat(Fill(nPhysicalEntries, cacheable), normal_entries.map(_.c).asUInt) // put partial val ppp_array = Cat(Fill(nPhysicalEntries, prot_pp), normal_entries.map(_.ppp).asUInt) // atomic arithmetic val paa_array = Cat(Fill(nPhysicalEntries, prot_aa), normal_entries.map(_.paa).asUInt) // atomic logic val pal_array = Cat(Fill(nPhysicalEntries, prot_al), normal_entries.map(_.pal).asUInt) val ppp_array_if_cached = ppp_array | c_array val paa_array_if_cached = paa_array | (if(usingAtomicsInCache) c_array else 0.U) val pal_array_if_cached = pal_array | (if(usingAtomicsInCache) c_array else 0.U) val prefetchable_array = Cat((cacheable && homogeneous) << (nPhysicalEntries-1), normal_entries.map(_.c).asUInt) // vaddr misaligned: vaddr[1:0]=b00 val misaligned = (io.req.bits.vaddr & (UIntToOH(io.req.bits.size) - 1.U)).orR def badVA(guestPA: Boolean): Bool = { val additionalPgLevels = (if (guestPA) io.ptw.hgatp else satp).additionalPgLevels val extraBits = if (guestPA) hypervisorExtraAddrBits else 0 val signed = !guestPA val nPgLevelChoices = pgLevels - minPgLevels + 1 val minVAddrBits = pgIdxBits + minPgLevels * pgLevelBits + extraBits (for (i <- 0 until nPgLevelChoices) yield { val mask = ((BigInt(1) << vaddrBitsExtended) - (BigInt(1) << (minVAddrBits + i * pgLevelBits - signed.toInt))).U val maskedVAddr = io.req.bits.vaddr & mask additionalPgLevels === i.U && !(maskedVAddr === 0.U || signed.B && maskedVAddr === mask) }).orR } val bad_gpa = if (!usingHypervisor) false.B else vm_enabled && !stage1_en && badVA(true) val bad_va = if (!usingVM || (minPgLevels == pgLevels && vaddrBits == vaddrBitsExtended)) false.B else vm_enabled && stage1_en && badVA(false) val cmd_lrsc = usingAtomics.B && io.req.bits.cmd.isOneOf(M_XLR, M_XSC) val cmd_amo_logical = usingAtomics.B && isAMOLogical(io.req.bits.cmd) val cmd_amo_arithmetic = usingAtomics.B && isAMOArithmetic(io.req.bits.cmd) val cmd_put_partial = io.req.bits.cmd === M_PWR val cmd_read = isRead(io.req.bits.cmd) val cmd_readx = usingHypervisor.B && io.req.bits.cmd === M_HLVX val cmd_write = isWrite(io.req.bits.cmd) val cmd_write_perms = cmd_write || io.req.bits.cmd.isOneOf(M_FLUSH_ALL, M_WOK) // not a write, but needs write permissions val lrscAllowed = Mux((usingDataScratchpad || usingAtomicsOnlyForIO).B, 0.U, c_array) val ae_array = Mux(misaligned, eff_array, 0.U) | Mux(cmd_lrsc, ~lrscAllowed, 0.U) // access exception needs SoC information from PMA val ae_ld_array = Mux(cmd_read, ae_array | ~pr_array, 0.U) val ae_st_array = Mux(cmd_write_perms, ae_array | ~pw_array, 0.U) | Mux(cmd_put_partial, ~ppp_array_if_cached, 0.U) | Mux(cmd_amo_logical, ~pal_array_if_cached, 0.U) | Mux(cmd_amo_arithmetic, ~paa_array_if_cached, 0.U) val must_alloc_array = Mux(cmd_put_partial, ~ppp_array, 0.U) | Mux(cmd_amo_logical, ~pal_array, 0.U) | Mux(cmd_amo_arithmetic, ~paa_array, 0.U) | Mux(cmd_lrsc, ~0.U(pal_array.getWidth.W), 0.U) val pf_ld_array = Mux(cmd_read, ((~Mux(cmd_readx, x_array, r_array) & ~ptw_ae_array) | ptw_pf_array) & ~ptw_gf_array, 0.U) val pf_st_array = Mux(cmd_write_perms, ((~w_array & ~ptw_ae_array) | ptw_pf_array) & ~ptw_gf_array, 0.U) val pf_inst_array = ((~x_array & ~ptw_ae_array) | ptw_pf_array) & ~ptw_gf_array val gf_ld_array = Mux(priv_v && cmd_read, (~Mux(cmd_readx, hx_array, hr_array) | ptw_gf_array) & ~ptw_ae_array, 0.U) val gf_st_array = Mux(priv_v && cmd_write_perms, (~hw_array | ptw_gf_array) & ~ptw_ae_array, 0.U) val gf_inst_array = Mux(priv_v, (~hx_array | ptw_gf_array) & ~ptw_ae_array, 0.U) val gpa_hits = { val need_gpa_mask = if (instruction) gf_inst_array else gf_ld_array | gf_st_array val hit_mask = Fill(ordinary_entries.size, r_gpa_valid && r_gpa_vpn === vpn) | Fill(all_entries.size, !vstage1_en) hit_mask | ~need_gpa_mask(all_entries.size-1, 0) } val tlb_hit_if_not_gpa_miss = real_hits.orR val tlb_hit = (real_hits & gpa_hits).orR // leads to s_request val tlb_miss = vm_enabled && !vsatp_mode_mismatch && !bad_va && !tlb_hit val sectored_plru = new SetAssocLRU(cfg.nSets, sectored_entries.head.size, "plru") val superpage_plru = new PseudoLRU(superpage_entries.size) when (io.req.valid && vm_enabled) { // replace when (sector_hits.orR) { sectored_plru.access(memIdx, OHToUInt(sector_hits)) } when (superpage_hits.orR) { superpage_plru.access(OHToUInt(superpage_hits)) } } // Superpages create the possibility that two entries in the TLB may match. // This corresponds to a software bug, but we can't return complete garbage; // we must return either the old translation or the new translation. This // isn't compatible with the Mux1H approach. So, flush the TLB and report // a miss on duplicate entries. val multipleHits = PopCountAtLeast(real_hits, 2) // only pull up req.ready when this is s_ready state. io.req.ready := state === s_ready // page fault io.resp.pf.ld := (bad_va && cmd_read) || (pf_ld_array & hits).orR io.resp.pf.st := (bad_va && cmd_write_perms) || (pf_st_array & hits).orR io.resp.pf.inst := bad_va || (pf_inst_array & hits).orR // guest page fault io.resp.gf.ld := (bad_gpa && cmd_read) || (gf_ld_array & hits).orR io.resp.gf.st := (bad_gpa && cmd_write_perms) || (gf_st_array & hits).orR io.resp.gf.inst := bad_gpa || (gf_inst_array & hits).orR // access exception io.resp.ae.ld := (ae_ld_array & hits).orR io.resp.ae.st := (ae_st_array & hits).orR io.resp.ae.inst := (~px_array & hits).orR // misaligned io.resp.ma.ld := misaligned && cmd_read io.resp.ma.st := misaligned && cmd_write io.resp.ma.inst := false.B // this is up to the pipeline to figure out io.resp.cacheable := (c_array & hits).orR io.resp.must_alloc := (must_alloc_array & hits).orR io.resp.prefetchable := (prefetchable_array & hits).orR && edge.manager.managers.forall(m => !m.supportsAcquireB || m.supportsHint).B io.resp.miss := do_refill || vsatp_mode_mismatch || tlb_miss || multipleHits io.resp.paddr := Cat(ppn, io.req.bits.vaddr(pgIdxBits-1, 0)) io.resp.size := io.req.bits.size io.resp.cmd := io.req.bits.cmd io.resp.gpa_is_pte := vstage1_en && r_gpa_is_pte io.resp.gpa := { val page = Mux(!vstage1_en, Cat(bad_gpa, vpn), r_gpa >> pgIdxBits) val offset = Mux(io.resp.gpa_is_pte, r_gpa(pgIdxBits-1, 0), io.req.bits.vaddr(pgIdxBits-1, 0)) Cat(page, offset) } io.ptw.req.valid := state === s_request io.ptw.req.bits.valid := !io.kill io.ptw.req.bits.bits.addr := r_refill_tag io.ptw.req.bits.bits.vstage1 := r_vstage1_en io.ptw.req.bits.bits.stage2 := r_stage2_en io.ptw.req.bits.bits.need_gpa := r_need_gpa if (usingVM) { when(io.ptw.req.fire && io.ptw.req.bits.valid) { r_gpa_valid := false.B r_gpa_vpn := r_refill_tag } val sfence = io.sfence.valid // this is [[s_ready]] // handle miss/hit at the first cycle. // if miss, request PTW(L2TLB). when (io.req.fire && tlb_miss) { state := s_request r_refill_tag := vpn r_need_gpa := tlb_hit_if_not_gpa_miss r_vstage1_en := vstage1_en r_stage2_en := stage2_en r_superpage_repl_addr := replacementEntry(superpage_entries, superpage_plru.way) r_sectored_repl_addr := replacementEntry(sectored_entries(memIdx), sectored_plru.way(memIdx)) r_sectored_hit.valid := sector_hits.orR r_sectored_hit.bits := OHToUInt(sector_hits) r_superpage_hit.valid := superpage_hits.orR r_superpage_hit.bits := OHToUInt(superpage_hits) } // Handle SFENCE.VMA when send request to PTW. // SFENCE.VMA io.ptw.req.ready kill // ? ? 1 // 0 0 0 // 0 1 0 -> s_wait // 1 0 0 -> s_wait_invalidate // 1 0 0 -> s_ready when (state === s_request) { // SFENCE.VMA will kill TLB entries based on rs1 and rs2. It will take 1 cycle. when (sfence) { state := s_ready } // here should be io.ptw.req.fire, but assert(io.ptw.req.ready === true.B) // fire -> s_wait when (io.ptw.req.ready) { state := Mux(sfence, s_wait_invalidate, s_wait) } // If CPU kills request(frontend.s2_redirect) when (io.kill) { state := s_ready } } // sfence in refill will results in invalidate when (state === s_wait && sfence) { state := s_wait_invalidate } // after CPU acquire response, go back to s_ready. when (io.ptw.resp.valid) { state := s_ready } // SFENCE processing logic. when (sfence) { assert(!io.sfence.bits.rs1 || (io.sfence.bits.addr >> pgIdxBits) === vpn) for (e <- all_real_entries) { val hv = usingHypervisor.B && io.sfence.bits.hv val hg = usingHypervisor.B && io.sfence.bits.hg when (!hg && io.sfence.bits.rs1) { e.invalidateVPN(vpn, hv) } .elsewhen (!hg && io.sfence.bits.rs2) { e.invalidateNonGlobal(hv) } .otherwise { e.invalidate(hv || hg) } } } when(io.req.fire && vsatp_mode_mismatch) { all_real_entries.foreach(_.invalidate(true.B)) v_entries_use_stage1 := vstage1_en } when (multipleHits || reset.asBool) { all_real_entries.foreach(_.invalidate()) } ccover(io.ptw.req.fire, "MISS", "TLB miss") ccover(io.ptw.req.valid && !io.ptw.req.ready, "PTW_STALL", "TLB miss, but PTW busy") ccover(state === s_wait_invalidate, "SFENCE_DURING_REFILL", "flush TLB during TLB refill") ccover(sfence && !io.sfence.bits.rs1 && !io.sfence.bits.rs2, "SFENCE_ALL", "flush TLB") ccover(sfence && !io.sfence.bits.rs1 && io.sfence.bits.rs2, "SFENCE_ASID", "flush TLB ASID") ccover(sfence && io.sfence.bits.rs1 && !io.sfence.bits.rs2, "SFENCE_LINE", "flush TLB line") ccover(sfence && io.sfence.bits.rs1 && io.sfence.bits.rs2, "SFENCE_LINE_ASID", "flush TLB line/ASID") ccover(multipleHits, "MULTIPLE_HITS", "Two matching translations in TLB") } def ccover(cond: Bool, label: String, desc: String)(implicit sourceInfo: SourceInfo) = property.cover(cond, s"${if (instruction) "I" else "D"}TLB_$label", "MemorySystem;;" + desc) /** Decides which entry to be replaced * * If there is a invalid entry, replace it with priorityencoder; * if not, replace the alt entry * * @return mask for TLBEntry replacement */ def replacementEntry(set: Seq[TLBEntry], alt: UInt) = { val valids = set.map(_.valid.orR).asUInt Mux(valids.andR, alt, PriorityEncoder(~valids)) } } File TLBPermissions.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.rocket import chisel3._ import chisel3.util._ import freechips.rocketchip.diplomacy.{AddressSet, TransferSizes, RegionType, AddressDecoder} import freechips.rocketchip.tilelink.TLManagerParameters case class TLBPermissions( homogeneous: Bool, // if false, the below are undefined r: Bool, // readable w: Bool, // writeable x: Bool, // executable c: Bool, // cacheable a: Bool, // arithmetic ops l: Bool) // logical ops object TLBPageLookup { private case class TLBFixedPermissions( e: Boolean, // get-/put-effects r: Boolean, // readable w: Boolean, // writeable x: Boolean, // executable c: Boolean, // cacheable a: Boolean, // arithmetic ops l: Boolean) { // logical ops val useful = r || w || x || c || a || l } private def groupRegions(managers: Seq[TLManagerParameters]): Map[TLBFixedPermissions, Seq[AddressSet]] = { val permissions = managers.map { m => (m.address, TLBFixedPermissions( e = Seq(RegionType.PUT_EFFECTS, RegionType.GET_EFFECTS) contains m.regionType, r = m.supportsGet || m.supportsAcquireB, // if cached, never uses Get w = m.supportsPutFull || m.supportsAcquireT, // if cached, never uses Put x = m.executable, c = m.supportsAcquireB, a = m.supportsArithmetic, l = m.supportsLogical)) } permissions .filter(_._2.useful) // get rid of no-permission devices .groupBy(_._2) // group by permission type .mapValues(seq => AddressSet.unify(seq.flatMap(_._1))) // coalesce same-permission regions .toMap } // Unmapped memory is considered to be inhomogeneous def apply(managers: Seq[TLManagerParameters], xLen: Int, cacheBlockBytes: Int, pageSize: BigInt, maxRequestBytes: Int): UInt => TLBPermissions = { require (isPow2(xLen) && xLen >= 8) require (isPow2(cacheBlockBytes) && cacheBlockBytes >= xLen/8) require (isPow2(pageSize) && pageSize >= cacheBlockBytes) val xferSizes = TransferSizes(cacheBlockBytes, cacheBlockBytes) val allSizes = TransferSizes(1, maxRequestBytes) val amoSizes = TransferSizes(4, xLen/8) val permissions = managers.foreach { m => require (!m.supportsGet || m.supportsGet .contains(allSizes), s"Memory region '${m.name}' at ${m.address} only supports ${m.supportsGet} Get, but must support ${allSizes}") require (!m.supportsPutFull || m.supportsPutFull .contains(allSizes), s"Memory region '${m.name}' at ${m.address} only supports ${m.supportsPutFull} PutFull, but must support ${allSizes}") require (!m.supportsPutPartial || m.supportsPutPartial.contains(allSizes), s"Memory region '${m.name}' at ${m.address} only supports ${m.supportsPutPartial} PutPartial, but must support ${allSizes}") require (!m.supportsAcquireB || m.supportsAcquireB .contains(xferSizes), s"Memory region '${m.name}' at ${m.address} only supports ${m.supportsAcquireB} AcquireB, but must support ${xferSizes}") require (!m.supportsAcquireT || m.supportsAcquireT .contains(xferSizes), s"Memory region '${m.name}' at ${m.address} only supports ${m.supportsAcquireT} AcquireT, but must support ${xferSizes}") require (!m.supportsLogical || m.supportsLogical .contains(amoSizes), s"Memory region '${m.name}' at ${m.address} only supports ${m.supportsLogical} Logical, but must support ${amoSizes}") require (!m.supportsArithmetic || m.supportsArithmetic.contains(amoSizes), s"Memory region '${m.name}' at ${m.address} only supports ${m.supportsArithmetic} Arithmetic, but must support ${amoSizes}") require (!(m.supportsAcquireB && m.supportsPutFull && !m.supportsAcquireT), s"Memory region '${m.name}' supports AcquireB (cached read) and PutFull (un-cached write) but not AcquireT (cached write)") } val grouped = groupRegions(managers) .mapValues(_.filter(_.alignment >= pageSize)) // discard any region that's not big enough def lowCostProperty(prop: TLBFixedPermissions => Boolean): UInt => Bool = { val (yesm, nom) = grouped.partition { case (k, eq) => prop(k) } val (yes, no) = (yesm.values.flatten.toList, nom.values.flatten.toList) // Find the minimal bits needed to distinguish between yes and no val decisionMask = AddressDecoder(Seq(yes, no)) def simplify(x: Seq[AddressSet]) = AddressSet.unify(x.map(_.widen(~decisionMask)).distinct) val (yesf, nof) = (simplify(yes), simplify(no)) if (yesf.size < no.size) { (x: UInt) => yesf.map(_.contains(x)).foldLeft(false.B)(_ || _) } else { (x: UInt) => !nof.map(_.contains(x)).foldLeft(false.B)(_ || _) } } // Derive simplified property circuits (don't care when !homo) val rfn = lowCostProperty(_.r) val wfn = lowCostProperty(_.w) val xfn = lowCostProperty(_.x) val cfn = lowCostProperty(_.c) val afn = lowCostProperty(_.a) val lfn = lowCostProperty(_.l) val homo = AddressSet.unify(grouped.values.flatten.toList) (x: UInt) => TLBPermissions( homogeneous = homo.map(_.contains(x)).foldLeft(false.B)(_ || _), r = rfn(x), w = wfn(x), x = xfn(x), c = cfn(x), a = afn(x), l = lfn(x)) } // Are all pageSize intervals of mapped regions homogeneous? def homogeneous(managers: Seq[TLManagerParameters], pageSize: BigInt): Boolean = { groupRegions(managers).values.forall(_.forall(_.alignment >= pageSize)) } } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.diplomacy import chisel3._ import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor} import freechips.rocketchip.util.ShiftQueue /** Options for describing the attributes of memory regions */ object RegionType { // Define the 'more relaxed than' ordering val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS) sealed trait T extends Ordered[T] { def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this) } case object CACHED extends T // an intermediate agent may have cached a copy of the region for you case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively } // A non-empty half-open range; [start, end) case class IdRange(start: Int, end: Int) extends Ordered[IdRange] { require (start >= 0, s"Ids cannot be negative, but got: $start.") require (start <= end, "Id ranges cannot be negative.") def compare(x: IdRange) = { val primary = (this.start - x.start).signum val secondary = (x.end - this.end).signum if (primary != 0) primary else secondary } def overlaps(x: IdRange) = start < x.end && x.start < end def contains(x: IdRange) = start <= x.start && x.end <= end def contains(x: Int) = start <= x && x < end def contains(x: UInt) = if (size == 0) { false.B } else if (size == 1) { // simple comparison x === start.U } else { // find index of largest different bit val largestDeltaBit = log2Floor(start ^ (end-1)) val smallestCommonBit = largestDeltaBit + 1 // may not exist in x val uncommonMask = (1 << smallestCommonBit) - 1 val uncommonBits = (x | 0.U(smallestCommonBit.W))(largestDeltaBit, 0) // the prefix must match exactly (note: may shift ALL bits away) (x >> smallestCommonBit) === (start >> smallestCommonBit).U && // firrtl constant prop range analysis can eliminate these two: (start & uncommonMask).U <= uncommonBits && uncommonBits <= ((end-1) & uncommonMask).U } def shift(x: Int) = IdRange(start+x, end+x) def size = end - start def isEmpty = end == start def range = start until end } object IdRange { def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else { val ranges = s.sorted (ranges.tail zip ranges.init) find { case (a, b) => a overlaps b } } } // An potentially empty inclusive range of 2-powers [min, max] (in bytes) case class TransferSizes(min: Int, max: Int) { def this(x: Int) = this(x, x) require (min <= max, s"Min transfer $min > max transfer $max") require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)") require (max == 0 || isPow2(max), s"TransferSizes must be a power of 2, got: $max") require (min == 0 || isPow2(min), s"TransferSizes must be a power of 2, got: $min") require (max == 0 || min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)") def none = min == 0 def contains(x: Int) = isPow2(x) && min <= x && x <= max def containsLg(x: Int) = contains(1 << x) def containsLg(x: UInt) = if (none) false.B else if (min == max) { log2Ceil(min).U === x } else { log2Ceil(min).U <= x && x <= log2Ceil(max).U } def contains(x: TransferSizes) = x.none || (min <= x.min && x.max <= max) def intersect(x: TransferSizes) = if (x.max < min || max < x.min) TransferSizes.none else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max)) // Not a union, because the result may contain sizes contained by neither term // NOT TO BE CONFUSED WITH COVERPOINTS def mincover(x: TransferSizes) = { if (none) { x } else if (x.none) { this } else { TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max)) } } override def toString() = "TransferSizes[%d, %d]".format(min, max) } object TransferSizes { def apply(x: Int) = new TransferSizes(x) val none = new TransferSizes(0) def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _) def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _) implicit def asBool(x: TransferSizes) = !x.none } // AddressSets specify the address space managed by the manager // Base is the base address, and mask are the bits consumed by the manager // e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff // e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ... case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet] { // Forbid misaligned base address (and empty sets) require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}") require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous // We do allow negative mask (=> ignore all high bits) def contains(x: BigInt) = ((x ^ base) & ~mask) == 0 def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S // turn x into an address contained in this set def legalize(x: UInt): UInt = base.U | (mask.U & x) // overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1) def overlaps(x: AddressSet) = (~(mask | x.mask) & (base ^ x.base)) == 0 // contains iff bitwise: x.mask => mask && contains(x.base) def contains(x: AddressSet) = ((x.mask | (base ^ x.base)) & ~mask) == 0 // The number of bytes to which the manager must be aligned def alignment = ((mask + 1) & ~mask) // Is this a contiguous memory range def contiguous = alignment == mask+1 def finite = mask >= 0 def max = { require (finite, "Max cannot be calculated on infinite mask"); base | mask } // Widen the match function to ignore all bits in imask def widen(imask: BigInt) = AddressSet(base & ~imask, mask | imask) // Return an AddressSet that only contains the addresses both sets contain def intersect(x: AddressSet): Option[AddressSet] = { if (!overlaps(x)) { None } else { val r_mask = mask & x.mask val r_base = base | x.base Some(AddressSet(r_base, r_mask)) } } def subtract(x: AddressSet): Seq[AddressSet] = { intersect(x) match { case None => Seq(this) case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit => val nmask = (mask & (bit-1)) | remove.mask val nbase = (remove.base ^ bit) & ~nmask AddressSet(nbase, nmask) } } } // AddressSets have one natural Ordering (the containment order, if contiguous) def compare(x: AddressSet) = { val primary = (this.base - x.base).signum // smallest address first val secondary = (x.mask - this.mask).signum // largest mask first if (primary != 0) primary else secondary } // We always want to see things in hex override def toString() = { if (mask >= 0) { "AddressSet(0x%x, 0x%x)".format(base, mask) } else { "AddressSet(0x%x, ~0x%x)".format(base, ~mask) } } def toRanges = { require (finite, "Ranges cannot be calculated on infinite mask") val size = alignment val fragments = mask & ~(size-1) val bits = bitIndexes(fragments) (BigInt(0) until (BigInt(1) << bits.size)).map { i => val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) } AddressRange(off, size) } } } object AddressSet { val everything = AddressSet(0, -1) def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = { if (size == 0) tail.reverse else { val maxBaseAlignment = base & (-base) // 0 for infinite (LSB) val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size val step = if (maxBaseAlignment == 0 || maxBaseAlignment > maxSizeAlignment) maxSizeAlignment else maxBaseAlignment misaligned(base+step, size-step, AddressSet(base, step-1) +: tail) } } def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = { // Pair terms up by ignoring 'bit' seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) => if (seq.size == 1) { seq.head // singleton -> unaffected } else { key.copy(mask = key.mask | bit) // pair - widen mask by bit } }.toList } def unify(seq: Seq[AddressSet]): Seq[AddressSet] = { val bits = seq.map(_.base).foldLeft(BigInt(0))(_ | _) AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted } def enumerateMask(mask: BigInt): Seq[BigInt] = { def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] = if (id == mask) (id +: tail).reverse else helper(((~mask | id) + 1) & mask, id +: tail) helper(0, Nil) } def enumerateBits(mask: BigInt): Seq[BigInt] = { def helper(x: BigInt): Seq[BigInt] = { if (x == 0) { Nil } else { val bit = x & (-x) bit +: helper(x & ~bit) } } helper(mask) } } case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean) { require (depth >= 0, "Buffer depth must be >= 0") def isDefined = depth > 0 def latency = if (isDefined && !flow) 1 else 0 def apply[T <: Data](x: DecoupledIO[T]) = if (isDefined) Queue(x, depth, flow=flow, pipe=pipe) else x def irrevocable[T <: Data](x: ReadyValidIO[T]) = if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe) else x def sq[T <: Data](x: DecoupledIO[T]) = if (!isDefined) x else { val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe)) sq.io.enq <> x sq.io.deq } override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "") } object BufferParams { implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false) val default = BufferParams(2) val none = BufferParams(0) val flow = BufferParams(1, true, false) val pipe = BufferParams(1, false, true) } case class TriStateValue(value: Boolean, set: Boolean) { def update(orig: Boolean) = if (set) value else orig } object TriStateValue { implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true) def unset = TriStateValue(false, false) } trait DirectedBuffers[T] { def copyIn(x: BufferParams): T def copyOut(x: BufferParams): T def copyInOut(x: BufferParams): T } trait IdMapEntry { def name: String def from: IdRange def to: IdRange def isCache: Boolean def requestFifo: Boolean def maxTransactionsInFlight: Option[Int] def pretty(fmt: String) = if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5 fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } else { fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } } abstract class IdMap[T <: IdMapEntry] { protected val fmt: String val mapping: Seq[T] def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n") } File PTW.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.rocket import chisel3._ import chisel3.util.{Arbiter, Cat, Decoupled, Enum, Mux1H, OHToUInt, PopCount, PriorityEncoder, PriorityEncoderOH, RegEnable, UIntToOH, Valid, is, isPow2, log2Ceil, switch} import chisel3.withClock import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.subsystem.CacheBlockBytes import freechips.rocketchip.tile._ import freechips.rocketchip.tilelink._ import freechips.rocketchip.util._ import freechips.rocketchip.util.property import scala.collection.mutable.ListBuffer /** PTE request from TLB to PTW * * TLB send a PTE request to PTW when L1TLB miss */ class PTWReq(implicit p: Parameters) extends CoreBundle()(p) { val addr = UInt(vpnBits.W) val need_gpa = Bool() val vstage1 = Bool() val stage2 = Bool() } /** PTE info from L2TLB to TLB * * containing: target PTE, exceptions, two-satge tanslation info */ class PTWResp(implicit p: Parameters) extends CoreBundle()(p) { /** ptw access exception */ val ae_ptw = Bool() /** final access exception */ val ae_final = Bool() /** page fault */ val pf = Bool() /** guest page fault */ val gf = Bool() /** hypervisor read */ val hr = Bool() /** hypervisor write */ val hw = Bool() /** hypervisor execute */ val hx = Bool() /** PTE to refill L1TLB * * source: L2TLB */ val pte = new PTE /** pte pglevel */ val level = UInt(log2Ceil(pgLevels).W) /** fragmented_superpage support */ val fragmented_superpage = Bool() /** homogeneous for both pma and pmp */ val homogeneous = Bool() val gpa = Valid(UInt(vaddrBits.W)) val gpa_is_pte = Bool() } /** IO between TLB and PTW * * PTW receives : * - PTE request * - CSRs info * - pmp results from PMP(in TLB) */ class TLBPTWIO(implicit p: Parameters) extends CoreBundle()(p) with HasCoreParameters { val req = Decoupled(Valid(new PTWReq)) val resp = Flipped(Valid(new PTWResp)) val ptbr = Input(new PTBR()) val hgatp = Input(new PTBR()) val vsatp = Input(new PTBR()) val status = Input(new MStatus()) val hstatus = Input(new HStatus()) val gstatus = Input(new MStatus()) val pmp = Input(Vec(nPMPs, new PMP)) val customCSRs = Flipped(coreParams.customCSRs) } /** PTW performance statistics */ class PTWPerfEvents extends Bundle { val l2miss = Bool() val l2hit = Bool() val pte_miss = Bool() val pte_hit = Bool() } /** Datapath IO between PTW and Core * * PTW receives CSRs info, pmp checks, sfence instruction info * * PTW sends its performance statistics to core */ class DatapathPTWIO(implicit p: Parameters) extends CoreBundle()(p) with HasCoreParameters { val ptbr = Input(new PTBR()) val hgatp = Input(new PTBR()) val vsatp = Input(new PTBR()) val sfence = Flipped(Valid(new SFenceReq)) val status = Input(new MStatus()) val hstatus = Input(new HStatus()) val gstatus = Input(new MStatus()) val pmp = Input(Vec(nPMPs, new PMP)) val perf = Output(new PTWPerfEvents()) val customCSRs = Flipped(coreParams.customCSRs) /** enable clock generated by ptw */ val clock_enabled = Output(Bool()) } /** PTE template for transmission * * contains useful methods to check PTE attributes * @see RV-priv spec 4.3.1 for pgae table entry format */ class PTE(implicit p: Parameters) extends CoreBundle()(p) { val reserved_for_future = UInt(10.W) val ppn = UInt(44.W) val reserved_for_software = Bits(2.W) /** dirty bit */ val d = Bool() /** access bit */ val a = Bool() /** global mapping */ val g = Bool() /** user mode accessible */ val u = Bool() /** whether the page is executable */ val x = Bool() /** whether the page is writable */ val w = Bool() /** whether the page is readable */ val r = Bool() /** valid bit */ val v = Bool() /** return true if find a pointer to next level page table */ def table(dummy: Int = 0) = v && !r && !w && !x && !d && !a && !u && reserved_for_future === 0.U /** return true if find a leaf PTE */ def leaf(dummy: Int = 0) = v && (r || (x && !w)) && a /** user read */ def ur(dummy: Int = 0) = sr() && u /** user write*/ def uw(dummy: Int = 0) = sw() && u /** user execute */ def ux(dummy: Int = 0) = sx() && u /** supervisor read */ def sr(dummy: Int = 0) = leaf() && r /** supervisor write */ def sw(dummy: Int = 0) = leaf() && w && d /** supervisor execute */ def sx(dummy: Int = 0) = leaf() && x /** full permission: writable and executable in user mode */ def isFullPerm(dummy: Int = 0) = uw() && ux() } /** L2TLB PTE template * * contains tag bits * @param nSets number of sets in L2TLB * @see RV-priv spec 4.3.1 for page table entry format */ class L2TLBEntry(nSets: Int)(implicit p: Parameters) extends CoreBundle()(p) with HasCoreParameters { val idxBits = log2Ceil(nSets) val tagBits = maxSVAddrBits - pgIdxBits - idxBits + (if (usingHypervisor) 1 else 0) val tag = UInt(tagBits.W) val ppn = UInt(ppnBits.W) /** dirty bit */ val d = Bool() /** access bit */ val a = Bool() /** user mode accessible */ val u = Bool() /** whether the page is executable */ val x = Bool() /** whether the page is writable */ val w = Bool() /** whether the page is readable */ val r = Bool() } /** PTW contains L2TLB, and performs page table walk for high level TLB, and cache queries from L1 TLBs(I$, D$, RoCC) * * It performs hierarchy page table query to mem for the desired leaf PTE and cache them in l2tlb. * Besides leaf PTEs, it also caches non-leaf PTEs in pte_cache to accerlerate the process. * * ==Structure== * - l2tlb : for leaf PTEs * - set-associative (configurable with [[CoreParams.nL2TLBEntries]]and [[CoreParams.nL2TLBWays]])) * - PLRU * - pte_cache: for non-leaf PTEs * - set-associative * - LRU * - s2_pte_cache: for non-leaf PTEs in 2-stage translation * - set-associative * - PLRU * * l2tlb Pipeline: 3 stage * {{{ * stage 0 : read * stage 1 : decode * stage 2 : hit check * }}} * ==State Machine== * s_ready: ready to reveive request from TLB * s_req: request mem; pte_cache hit judge * s_wait1: deal with l2tlb error * s_wait2: final hit judge * s_wait3: receive mem response * s_fragment_superpage: for superpage PTE * * @note l2tlb hit happens in s_req or s_wait1 * @see RV-priv spec 4.3-4.6 for Virtual-Memory System * @see RV-priv spec 8.5 for Two-Stage Address Translation * @todo details in two-stage translation */ class PTW(n: Int)(implicit edge: TLEdgeOut, p: Parameters) extends CoreModule()(p) { val io = IO(new Bundle { /** to n TLB */ val requestor = Flipped(Vec(n, new TLBPTWIO)) /** to HellaCache */ val mem = new HellaCacheIO /** to Core * * contains CSRs info and performance statistics */ val dpath = new DatapathPTWIO }) val s_ready :: s_req :: s_wait1 :: s_dummy1 :: s_wait2 :: s_wait3 :: s_dummy2 :: s_fragment_superpage :: Nil = Enum(8) val state = RegInit(s_ready) val l2_refill_wire = Wire(Bool()) /** Arbiter to arbite request from n TLB */ val arb = Module(new Arbiter(Valid(new PTWReq), n)) // use TLB req as arbitor's input arb.io.in <> io.requestor.map(_.req) // receive req only when s_ready and not in refill arb.io.out.ready := (state === s_ready) && !l2_refill_wire val resp_valid = RegNext(VecInit(Seq.fill(io.requestor.size)(false.B))) val clock_en = state =/= s_ready || l2_refill_wire || arb.io.out.valid || io.dpath.sfence.valid || io.dpath.customCSRs.disableDCacheClockGate io.dpath.clock_enabled := usingVM.B && clock_en val gated_clock = if (!usingVM || !tileParams.dcache.get.clockGate) clock else ClockGate(clock, clock_en, "ptw_clock_gate") withClock (gated_clock) { // entering gated-clock domain val invalidated = Reg(Bool()) /** current PTE level * {{{ * 0 <= count <= pgLevel-1 * count = pgLevel - 1 : leaf PTE * count < pgLevel - 1 : non-leaf PTE * }}} */ val count = Reg(UInt(log2Ceil(pgLevels).W)) val resp_ae_ptw = Reg(Bool()) val resp_ae_final = Reg(Bool()) val resp_pf = Reg(Bool()) val resp_gf = Reg(Bool()) val resp_hr = Reg(Bool()) val resp_hw = Reg(Bool()) val resp_hx = Reg(Bool()) val resp_fragmented_superpage = Reg(Bool()) /** tlb request */ val r_req = Reg(new PTWReq) /** current selected way in arbitor */ val r_req_dest = Reg(Bits()) // to respond to L1TLB : l2_hit // to construct mem.req.addr val r_pte = Reg(new PTE) val r_hgatp = Reg(new PTBR) // 2-stage pageLevel val aux_count = Reg(UInt(log2Ceil(pgLevels).W)) /** pte for 2-stage translation */ val aux_pte = Reg(new PTE) val gpa_pgoff = Reg(UInt(pgIdxBits.W)) // only valid in resp_gf case val stage2 = Reg(Bool()) val stage2_final = Reg(Bool()) val satp = Mux(arb.io.out.bits.bits.vstage1, io.dpath.vsatp, io.dpath.ptbr) val r_hgatp_initial_count = pgLevels.U - minPgLevels.U - r_hgatp.additionalPgLevels /** 2-stage translation both enable */ val do_both_stages = r_req.vstage1 && r_req.stage2 val max_count = count max aux_count val vpn = Mux(r_req.vstage1 && stage2, aux_pte.ppn, r_req.addr) val mem_resp_valid = RegNext(io.mem.resp.valid) val mem_resp_data = RegNext(io.mem.resp.bits.data) io.mem.uncached_resp.map { resp => assert(!(resp.valid && io.mem.resp.valid)) resp.ready := true.B when (resp.valid) { mem_resp_valid := true.B mem_resp_data := resp.bits.data } } // construct pte from mem.resp val (pte, invalid_paddr, invalid_gpa) = { val tmp = mem_resp_data.asTypeOf(new PTE()) val res = WireDefault(tmp) res.ppn := Mux(do_both_stages && !stage2, tmp.ppn(vpnBits.min(tmp.ppn.getWidth)-1, 0), tmp.ppn(ppnBits-1, 0)) when (tmp.r || tmp.w || tmp.x) { // for superpage mappings, make sure PPN LSBs are zero for (i <- 0 until pgLevels-1) when (count <= i.U && tmp.ppn((pgLevels-1-i)*pgLevelBits-1, (pgLevels-2-i)*pgLevelBits) =/= 0.U) { res.v := false.B } } (res, Mux(do_both_stages && !stage2, (tmp.ppn >> vpnBits) =/= 0.U, (tmp.ppn >> ppnBits) =/= 0.U), do_both_stages && !stage2 && checkInvalidHypervisorGPA(r_hgatp, tmp.ppn)) } // find non-leaf PTE, need traverse val traverse = pte.table() && !invalid_paddr && !invalid_gpa && count < (pgLevels-1).U /** address send to mem for enquerry */ val pte_addr = if (!usingVM) 0.U else { val vpn_idxs = (0 until pgLevels).map { i => val width = pgLevelBits + (if (i <= pgLevels - minPgLevels) hypervisorExtraAddrBits else 0) (vpn >> (pgLevels - i - 1) * pgLevelBits)(width - 1, 0) } val mask = Mux(stage2 && count === r_hgatp_initial_count, ((1 << (hypervisorExtraAddrBits + pgLevelBits)) - 1).U, ((1 << pgLevelBits) - 1).U) val vpn_idx = vpn_idxs(count) & mask val raw_pte_addr = ((r_pte.ppn << pgLevelBits) | vpn_idx) << log2Ceil(xLen / 8) val size = if (usingHypervisor) vaddrBits else paddrBits //use r_pte.ppn as page table base address //use vpn slice as offset raw_pte_addr.apply(size.min(raw_pte_addr.getWidth) - 1, 0) } /** stage2_pte_cache input addr */ val stage2_pte_cache_addr = if (!usingHypervisor) 0.U else { val vpn_idxs = (0 until pgLevels - 1).map { i => (r_req.addr >> (pgLevels - i - 1) * pgLevelBits)(pgLevelBits - 1, 0) } val vpn_idx = vpn_idxs(aux_count) val raw_s2_pte_cache_addr = Cat(aux_pte.ppn, vpn_idx) << log2Ceil(xLen / 8) raw_s2_pte_cache_addr(vaddrBits.min(raw_s2_pte_cache_addr.getWidth) - 1, 0) } def makeFragmentedSuperpagePPN(ppn: UInt): Seq[UInt] = { (pgLevels-1 until 0 by -1).map(i => Cat(ppn >> (pgLevelBits*i), r_req.addr(((pgLevelBits*i) min vpnBits)-1, 0).padTo(pgLevelBits*i))) } /** PTECache caches non-leaf PTE * @param s2 true: 2-stage address translation */ def makePTECache(s2: Boolean): (Bool, UInt) = if (coreParams.nPTECacheEntries == 0) { (false.B, 0.U) } else { val plru = new PseudoLRU(coreParams.nPTECacheEntries) val valid = RegInit(0.U(coreParams.nPTECacheEntries.W)) val tags = Reg(Vec(coreParams.nPTECacheEntries, UInt((if (usingHypervisor) 1 + vaddrBits else paddrBits).W))) // not include full pte, only ppn val data = Reg(Vec(coreParams.nPTECacheEntries, UInt((if (usingHypervisor && s2) vpnBits else ppnBits).W))) val can_hit = if (s2) count === r_hgatp_initial_count && aux_count < (pgLevels-1).U && r_req.vstage1 && stage2 && !stage2_final else count < (pgLevels-1).U && Mux(r_req.vstage1, stage2, !r_req.stage2) val can_refill = if (s2) do_both_stages && !stage2 && !stage2_final else can_hit val tag = if (s2) Cat(true.B, stage2_pte_cache_addr.padTo(vaddrBits)) else Cat(r_req.vstage1, pte_addr.padTo(if (usingHypervisor) vaddrBits else paddrBits)) val hits = tags.map(_ === tag).asUInt & valid val hit = hits.orR && can_hit // refill with mem response when (mem_resp_valid && traverse && can_refill && !hits.orR && !invalidated) { val r = Mux(valid.andR, plru.way, PriorityEncoder(~valid)) valid := valid | UIntToOH(r) tags(r) := tag data(r) := pte.ppn plru.access(r) } // replace when (hit && state === s_req) { plru.access(OHToUInt(hits)) } when (io.dpath.sfence.valid && (!io.dpath.sfence.bits.rs1 || usingHypervisor.B && io.dpath.sfence.bits.hg)) { valid := 0.U } val lcount = if (s2) aux_count else count for (i <- 0 until pgLevels-1) { ccover(hit && state === s_req && lcount === i.U, s"PTE_CACHE_HIT_L$i", s"PTE cache hit, level $i") } (hit, Mux1H(hits, data)) } // generate pte_cache val (pte_cache_hit, pte_cache_data) = makePTECache(false) // generate pte_cache with 2-stage translation val (stage2_pte_cache_hit, stage2_pte_cache_data) = makePTECache(true) // pte_cache hit or 2-stage pte_cache hit val pte_hit = RegNext(false.B) io.dpath.perf.pte_miss := false.B io.dpath.perf.pte_hit := pte_hit && (state === s_req) && !io.dpath.perf.l2hit assert(!(io.dpath.perf.l2hit && (io.dpath.perf.pte_miss || io.dpath.perf.pte_hit)), "PTE Cache Hit/Miss Performance Monitor Events are lower priority than L2TLB Hit event") // l2_refill happens when find the leaf pte val l2_refill = RegNext(false.B) l2_refill_wire := l2_refill io.dpath.perf.l2miss := false.B io.dpath.perf.l2hit := false.B // l2tlb val (l2_hit, l2_error, l2_pte, l2_tlb_ram) = if (coreParams.nL2TLBEntries == 0) (false.B, false.B, WireDefault(0.U.asTypeOf(new PTE)), None) else { val code = new ParityCode require(isPow2(coreParams.nL2TLBEntries)) require(isPow2(coreParams.nL2TLBWays)) require(coreParams.nL2TLBEntries >= coreParams.nL2TLBWays) val nL2TLBSets = coreParams.nL2TLBEntries / coreParams.nL2TLBWays require(isPow2(nL2TLBSets)) val idxBits = log2Ceil(nL2TLBSets) val l2_plru = new SetAssocLRU(nL2TLBSets, coreParams.nL2TLBWays, "plru") val ram = DescribedSRAM( name = "l2_tlb_ram", desc = "L2 TLB", size = nL2TLBSets, data = Vec(coreParams.nL2TLBWays, UInt(code.width(new L2TLBEntry(nL2TLBSets).getWidth).W)) ) val g = Reg(Vec(coreParams.nL2TLBWays, UInt(nL2TLBSets.W))) val valid = RegInit(VecInit(Seq.fill(coreParams.nL2TLBWays)(0.U(nL2TLBSets.W)))) // use r_req to construct tag val (r_tag, r_idx) = Split(Cat(r_req.vstage1, r_req.addr(maxSVAddrBits-pgIdxBits-1, 0)), idxBits) /** the valid vec for the selected set(including n ways) */ val r_valid_vec = valid.map(_(r_idx)).asUInt val r_valid_vec_q = Reg(UInt(coreParams.nL2TLBWays.W)) val r_l2_plru_way = Reg(UInt(log2Ceil(coreParams.nL2TLBWays max 1).W)) r_valid_vec_q := r_valid_vec // replacement way r_l2_plru_way := (if (coreParams.nL2TLBWays > 1) l2_plru.way(r_idx) else 0.U) // refill with r_pte(leaf pte) when (l2_refill && !invalidated) { val entry = Wire(new L2TLBEntry(nL2TLBSets)) entry.ppn := r_pte.ppn entry.d := r_pte.d entry.a := r_pte.a entry.u := r_pte.u entry.x := r_pte.x entry.w := r_pte.w entry.r := r_pte.r entry.tag := r_tag // if all the way are valid, use plru to select one way to be replaced, // otherwise use PriorityEncoderOH to select one val wmask = if (coreParams.nL2TLBWays > 1) Mux(r_valid_vec_q.andR, UIntToOH(r_l2_plru_way, coreParams.nL2TLBWays), PriorityEncoderOH(~r_valid_vec_q)) else 1.U(1.W) ram.write(r_idx, VecInit(Seq.fill(coreParams.nL2TLBWays)(code.encode(entry.asUInt))), wmask.asBools) val mask = UIntToOH(r_idx) for (way <- 0 until coreParams.nL2TLBWays) { when (wmask(way)) { valid(way) := valid(way) | mask g(way) := Mux(r_pte.g, g(way) | mask, g(way) & ~mask) } } } // sfence happens when (io.dpath.sfence.valid) { val hg = usingHypervisor.B && io.dpath.sfence.bits.hg for (way <- 0 until coreParams.nL2TLBWays) { valid(way) := Mux(!hg && io.dpath.sfence.bits.rs1, valid(way) & ~UIntToOH(io.dpath.sfence.bits.addr(idxBits+pgIdxBits-1, pgIdxBits)), Mux(!hg && io.dpath.sfence.bits.rs2, valid(way) & g(way), 0.U)) } } val s0_valid = !l2_refill && arb.io.out.fire val s0_suitable = arb.io.out.bits.bits.vstage1 === arb.io.out.bits.bits.stage2 && !arb.io.out.bits.bits.need_gpa val s1_valid = RegNext(s0_valid && s0_suitable && arb.io.out.bits.valid) val s2_valid = RegNext(s1_valid) // read from tlb idx val s1_rdata = ram.read(arb.io.out.bits.bits.addr(idxBits-1, 0), s0_valid) val s2_rdata = s1_rdata.map(s1_rdway => code.decode(RegEnable(s1_rdway, s1_valid))) val s2_valid_vec = RegEnable(r_valid_vec, s1_valid) val s2_g_vec = RegEnable(VecInit(g.map(_(r_idx))), s1_valid) val s2_error = (0 until coreParams.nL2TLBWays).map(way => s2_valid_vec(way) && s2_rdata(way).error).orR when (s2_valid && s2_error) { valid.foreach { _ := 0.U }} // decode val s2_entry_vec = s2_rdata.map(_.uncorrected.asTypeOf(new L2TLBEntry(nL2TLBSets))) val s2_hit_vec = (0 until coreParams.nL2TLBWays).map(way => s2_valid_vec(way) && (r_tag === s2_entry_vec(way).tag)) val s2_hit = s2_valid && s2_hit_vec.orR io.dpath.perf.l2miss := s2_valid && !(s2_hit_vec.orR) io.dpath.perf.l2hit := s2_hit when (s2_hit) { l2_plru.access(r_idx, OHToUInt(s2_hit_vec)) assert((PopCount(s2_hit_vec) === 1.U) || s2_error, "L2 TLB multi-hit") } val s2_pte = Wire(new PTE) val s2_hit_entry = Mux1H(s2_hit_vec, s2_entry_vec) s2_pte.ppn := s2_hit_entry.ppn s2_pte.d := s2_hit_entry.d s2_pte.a := s2_hit_entry.a s2_pte.g := Mux1H(s2_hit_vec, s2_g_vec) s2_pte.u := s2_hit_entry.u s2_pte.x := s2_hit_entry.x s2_pte.w := s2_hit_entry.w s2_pte.r := s2_hit_entry.r s2_pte.v := true.B s2_pte.reserved_for_future := 0.U s2_pte.reserved_for_software := 0.U for (way <- 0 until coreParams.nL2TLBWays) { ccover(s2_hit && s2_hit_vec(way), s"L2_TLB_HIT_WAY$way", s"L2 TLB hit way$way") } (s2_hit, s2_error, s2_pte, Some(ram)) } // if SFENCE occurs during walk, don't refill PTE cache or L2 TLB until next walk invalidated := io.dpath.sfence.valid || (invalidated && state =/= s_ready) // mem request io.mem.keep_clock_enabled := false.B io.mem.req.valid := state === s_req || state === s_dummy1 io.mem.req.bits.phys := true.B io.mem.req.bits.cmd := M_XRD io.mem.req.bits.size := log2Ceil(xLen/8).U io.mem.req.bits.signed := false.B io.mem.req.bits.addr := pte_addr io.mem.req.bits.idx.foreach(_ := pte_addr) io.mem.req.bits.dprv := PRV.S.U // PTW accesses are S-mode by definition io.mem.req.bits.dv := do_both_stages && !stage2 io.mem.req.bits.tag := DontCare io.mem.req.bits.no_resp := false.B io.mem.req.bits.no_alloc := DontCare io.mem.req.bits.no_xcpt := DontCare io.mem.req.bits.data := DontCare io.mem.req.bits.mask := DontCare io.mem.s1_kill := l2_hit || (state =/= s_wait1) || resp_gf io.mem.s1_data := DontCare io.mem.s2_kill := false.B val pageGranularityPMPs = pmpGranularity >= (1 << pgIdxBits) require(!usingHypervisor || pageGranularityPMPs, s"hypervisor requires pmpGranularity >= ${1<<pgIdxBits}") val pmaPgLevelHomogeneous = (0 until pgLevels) map { i => val pgSize = BigInt(1) << (pgIdxBits + ((pgLevels - 1 - i) * pgLevelBits)) if (pageGranularityPMPs && i == pgLevels - 1) { require(TLBPageLookup.homogeneous(edge.manager.managers, pgSize), s"All memory regions must be $pgSize-byte aligned") true.B } else { TLBPageLookup(edge.manager.managers, xLen, p(CacheBlockBytes), pgSize, xLen/8)(r_pte.ppn << pgIdxBits).homogeneous } } val pmaHomogeneous = pmaPgLevelHomogeneous(count) val pmpHomogeneous = new PMPHomogeneityChecker(io.dpath.pmp).apply(r_pte.ppn << pgIdxBits, count) val homogeneous = pmaHomogeneous && pmpHomogeneous // response to tlb for (i <- 0 until io.requestor.size) { io.requestor(i).resp.valid := resp_valid(i) io.requestor(i).resp.bits.ae_ptw := resp_ae_ptw io.requestor(i).resp.bits.ae_final := resp_ae_final io.requestor(i).resp.bits.pf := resp_pf io.requestor(i).resp.bits.gf := resp_gf io.requestor(i).resp.bits.hr := resp_hr io.requestor(i).resp.bits.hw := resp_hw io.requestor(i).resp.bits.hx := resp_hx io.requestor(i).resp.bits.pte := r_pte io.requestor(i).resp.bits.level := max_count io.requestor(i).resp.bits.homogeneous := homogeneous || pageGranularityPMPs.B io.requestor(i).resp.bits.fragmented_superpage := resp_fragmented_superpage && pageGranularityPMPs.B io.requestor(i).resp.bits.gpa.valid := r_req.need_gpa io.requestor(i).resp.bits.gpa.bits := Cat(Mux(!stage2_final || !r_req.vstage1 || aux_count === (pgLevels - 1).U, aux_pte.ppn, makeFragmentedSuperpagePPN(aux_pte.ppn)(aux_count)), gpa_pgoff) io.requestor(i).resp.bits.gpa_is_pte := !stage2_final io.requestor(i).ptbr := io.dpath.ptbr io.requestor(i).hgatp := io.dpath.hgatp io.requestor(i).vsatp := io.dpath.vsatp io.requestor(i).customCSRs <> io.dpath.customCSRs io.requestor(i).status := io.dpath.status io.requestor(i).hstatus := io.dpath.hstatus io.requestor(i).gstatus := io.dpath.gstatus io.requestor(i).pmp := io.dpath.pmp } // control state machine val next_state = WireDefault(state) state := OptimizationBarrier(next_state) val do_switch = WireDefault(false.B) switch (state) { is (s_ready) { when (arb.io.out.fire) { val satp_initial_count = pgLevels.U - minPgLevels.U - satp.additionalPgLevels val vsatp_initial_count = pgLevels.U - minPgLevels.U - io.dpath.vsatp.additionalPgLevels val hgatp_initial_count = pgLevels.U - minPgLevels.U - io.dpath.hgatp.additionalPgLevels val aux_ppn = Mux(arb.io.out.bits.bits.vstage1, io.dpath.vsatp.ppn, arb.io.out.bits.bits.addr) r_req := arb.io.out.bits.bits r_req_dest := arb.io.chosen next_state := Mux(arb.io.out.bits.valid, s_req, s_ready) stage2 := arb.io.out.bits.bits.stage2 stage2_final := arb.io.out.bits.bits.stage2 && !arb.io.out.bits.bits.vstage1 count := Mux(arb.io.out.bits.bits.stage2, hgatp_initial_count, satp_initial_count) aux_count := Mux(arb.io.out.bits.bits.vstage1, vsatp_initial_count, 0.U) aux_pte.ppn := aux_ppn aux_pte.reserved_for_future := 0.U resp_ae_ptw := false.B resp_ae_final := false.B resp_pf := false.B resp_gf := checkInvalidHypervisorGPA(io.dpath.hgatp, aux_ppn) && arb.io.out.bits.bits.stage2 resp_hr := true.B resp_hw := true.B resp_hx := true.B resp_fragmented_superpage := false.B r_hgatp := io.dpath.hgatp assert(!arb.io.out.bits.bits.need_gpa || arb.io.out.bits.bits.stage2) } } is (s_req) { when(stage2 && count === r_hgatp_initial_count) { gpa_pgoff := Mux(aux_count === (pgLevels-1).U, r_req.addr << (xLen/8).log2, stage2_pte_cache_addr) } // pte_cache hit when (stage2_pte_cache_hit) { aux_count := aux_count + 1.U aux_pte.ppn := stage2_pte_cache_data aux_pte.reserved_for_future := 0.U pte_hit := true.B }.elsewhen (pte_cache_hit) { count := count + 1.U pte_hit := true.B }.otherwise { next_state := Mux(io.mem.req.ready, s_wait1, s_req) } when(resp_gf) { next_state := s_ready resp_valid(r_req_dest) := true.B } } is (s_wait1) { // This Mux is for the l2_error case; the l2_hit && !l2_error case is overriden below next_state := Mux(l2_hit, s_req, s_wait2) } is (s_wait2) { next_state := s_wait3 io.dpath.perf.pte_miss := count < (pgLevels-1).U when (io.mem.s2_xcpt.ae.ld) { resp_ae_ptw := true.B next_state := s_ready resp_valid(r_req_dest) := true.B } } is (s_fragment_superpage) { next_state := s_ready resp_valid(r_req_dest) := true.B when (!homogeneous) { count := (pgLevels-1).U resp_fragmented_superpage := true.B } when (do_both_stages) { resp_fragmented_superpage := true.B } } } val merged_pte = { val superpage_masks = (0 until pgLevels).map(i => ((BigInt(1) << pte.ppn.getWidth) - (BigInt(1) << (pgLevels-1-i)*pgLevelBits)).U) val superpage_mask = superpage_masks(Mux(stage2_final, max_count, (pgLevels-1).U)) val stage1_ppns = (0 until pgLevels-1).map(i => Cat(pte.ppn(pte.ppn.getWidth-1, (pgLevels-i-1)*pgLevelBits), aux_pte.ppn((pgLevels-i-1)*pgLevelBits-1,0))) :+ pte.ppn val stage1_ppn = stage1_ppns(count) makePTE(stage1_ppn & superpage_mask, aux_pte) } r_pte := OptimizationBarrier( // l2tlb hit->find a leaf PTE(l2_pte), respond to L1TLB Mux(l2_hit && !l2_error && !resp_gf, l2_pte, // S2 PTE cache hit -> proceed to the next level of walking, update the r_pte with hgatp Mux(state === s_req && stage2_pte_cache_hit, makeHypervisorRootPTE(r_hgatp, stage2_pte_cache_data, l2_pte), // pte cache hit->find a non-leaf PTE(pte_cache),continue to request mem Mux(state === s_req && pte_cache_hit, makePTE(pte_cache_data, l2_pte), // 2-stage translation Mux(do_switch, makeHypervisorRootPTE(r_hgatp, pte.ppn, r_pte), // when mem respond, store mem.resp.pte Mux(mem_resp_valid, Mux(!traverse && r_req.vstage1 && stage2, merged_pte, pte), // fragment_superpage Mux(state === s_fragment_superpage && !homogeneous && count =/= (pgLevels - 1).U, makePTE(makeFragmentedSuperpagePPN(r_pte.ppn)(count), r_pte), // when tlb request come->request mem, use root address in satp(or vsatp,hgatp) Mux(arb.io.out.fire, Mux(arb.io.out.bits.bits.stage2, makeHypervisorRootPTE(io.dpath.hgatp, io.dpath.vsatp.ppn, r_pte), makePTE(satp.ppn, r_pte)), r_pte)))))))) when (l2_hit && !l2_error && !resp_gf) { assert(state === s_req || state === s_wait1) next_state := s_ready resp_valid(r_req_dest) := true.B count := (pgLevels-1).U } when (mem_resp_valid) { assert(state === s_wait3) next_state := s_req when (traverse) { when (do_both_stages && !stage2) { do_switch := true.B } count := count + 1.U }.otherwise { val gf = (stage2 && !stage2_final && !pte.ur()) || (pte.leaf() && pte.reserved_for_future === 0.U && invalid_gpa) val ae = pte.v && invalid_paddr val pf = pte.v && pte.reserved_for_future =/= 0.U val success = pte.v && !ae && !pf && !gf when (do_both_stages && !stage2_final && success) { when (stage2) { stage2 := false.B count := aux_count }.otherwise { stage2_final := true.B do_switch := true.B } }.otherwise { // find a leaf pte, start l2 refill l2_refill := success && count === (pgLevels-1).U && !r_req.need_gpa && (!r_req.vstage1 && !r_req.stage2 || do_both_stages && aux_count === (pgLevels-1).U && pte.isFullPerm()) count := max_count when (pageGranularityPMPs.B && !(count === (pgLevels-1).U && (!do_both_stages || aux_count === (pgLevels-1).U))) { next_state := s_fragment_superpage }.otherwise { next_state := s_ready resp_valid(r_req_dest) := true.B } resp_ae_ptw := ae && count < (pgLevels-1).U && pte.table() resp_ae_final := ae && pte.leaf() resp_pf := pf && !stage2 resp_gf := gf || (pf && stage2) resp_hr := !stage2 || (!pf && !gf && pte.ur()) resp_hw := !stage2 || (!pf && !gf && pte.uw()) resp_hx := !stage2 || (!pf && !gf && pte.ux()) } } } when (io.mem.s2_nack) { assert(state === s_wait2) next_state := s_req } when (do_switch) { aux_count := Mux(traverse, count + 1.U, count) count := r_hgatp_initial_count aux_pte := Mux(traverse, pte, { val s1_ppns = (0 until pgLevels-1).map(i => Cat(pte.ppn(pte.ppn.getWidth-1, (pgLevels-i-1)*pgLevelBits), r_req.addr(((pgLevels-i-1)*pgLevelBits min vpnBits)-1,0).padTo((pgLevels-i-1)*pgLevelBits))) :+ pte.ppn makePTE(s1_ppns(count), pte) }) stage2 := true.B } for (i <- 0 until pgLevels) { val leaf = mem_resp_valid && !traverse && count === i.U ccover(leaf && pte.v && !invalid_paddr && !invalid_gpa && pte.reserved_for_future === 0.U, s"L$i", s"successful page-table access, level $i") ccover(leaf && pte.v && invalid_paddr, s"L${i}_BAD_PPN_MSB", s"PPN too large, level $i") ccover(leaf && pte.v && invalid_gpa, s"L${i}_BAD_GPA_MSB", s"GPA too large, level $i") ccover(leaf && pte.v && pte.reserved_for_future =/= 0.U, s"L${i}_BAD_RSV_MSB", s"reserved MSBs set, level $i") ccover(leaf && !mem_resp_data(0), s"L${i}_INVALID_PTE", s"page not present, level $i") if (i != pgLevels-1) ccover(leaf && !pte.v && mem_resp_data(0), s"L${i}_BAD_PPN_LSB", s"PPN LSBs not zero, level $i") } ccover(mem_resp_valid && count === (pgLevels-1).U && pte.table(), s"TOO_DEEP", s"page table too deep") ccover(io.mem.s2_nack, "NACK", "D$ nacked page-table access") ccover(state === s_wait2 && io.mem.s2_xcpt.ae.ld, "AE", "access exception while walking page table") } // leaving gated-clock domain private def ccover(cond: Bool, label: String, desc: String)(implicit sourceInfo: SourceInfo) = if (usingVM) property.cover(cond, s"PTW_$label", "MemorySystem;;" + desc) /** Relace PTE.ppn with ppn */ private def makePTE(ppn: UInt, default: PTE) = { val pte = WireDefault(default) pte.ppn := ppn pte } /** use hgatp and vpn to construct a new ppn */ private def makeHypervisorRootPTE(hgatp: PTBR, vpn: UInt, default: PTE) = { val count = pgLevels.U - minPgLevels.U - hgatp.additionalPgLevels val idxs = (0 to pgLevels-minPgLevels).map(i => (vpn >> (pgLevels-i)*pgLevelBits)) val lsbs = WireDefault(UInt(maxHypervisorExtraAddrBits.W), idxs(count)) val pte = WireDefault(default) pte.ppn := Cat(hgatp.ppn >> maxHypervisorExtraAddrBits, lsbs) pte } /** use hgatp and vpn to check for gpa out of range */ private def checkInvalidHypervisorGPA(hgatp: PTBR, vpn: UInt) = { val count = pgLevels.U - minPgLevels.U - hgatp.additionalPgLevels val idxs = (0 to pgLevels-minPgLevels).map(i => (vpn >> ((pgLevels-i)*pgLevelBits)+maxHypervisorExtraAddrBits)) idxs.extract(count) =/= 0.U } } /** Mix-ins for constructing tiles that might have a PTW */ trait CanHavePTW extends HasTileParameters with HasHellaCache { this: BaseTile => val module: CanHavePTWModule var nPTWPorts = 1 nDCachePorts += usingPTW.toInt } trait CanHavePTWModule extends HasHellaCacheModule { val outer: CanHavePTW val ptwPorts = ListBuffer(outer.dcache.module.io.ptw) val ptw = Module(new PTW(outer.nPTWPorts)(outer.dcache.node.edges.out(0), outer.p)) ptw.io.mem <> DontCare if (outer.usingPTW) { dcachePorts += ptw.io.mem } }

module ITLB_1( // @[TLB.scala:318:7] input clock, // @[TLB.scala:318:7] input reset, // @[TLB.scala:318:7] input io_req_valid, // @[TLB.scala:320:14] input [39:0] io_req_bits_vaddr, // @[TLB.scala:320:14] input [1:0] io_req_bits_prv, // @[TLB.scala:320:14] input io_req_bits_v, // @[TLB.scala:320:14] output io_resp_miss, // @[TLB.scala:320:14] output [31:0] io_resp_paddr, // @[TLB.scala:320:14] output [39:0] io_resp_gpa, // @[TLB.scala:320:14] output io_resp_pf_ld, // @[TLB.scala:320:14] output io_resp_pf_inst, // @[TLB.scala:320:14] output io_resp_ae_ld, // @[TLB.scala:320:14] output io_resp_ae_inst, // @[TLB.scala:320:14] output io_resp_ma_ld, // @[TLB.scala:320:14] output io_resp_cacheable, // @[TLB.scala:320:14] output io_resp_prefetchable, // @[TLB.scala:320:14] input io_sfence_valid, // @[TLB.scala:320:14] input io_sfence_bits_rs1, // @[TLB.scala:320:14] input io_sfence_bits_rs2, // @[TLB.scala:320:14] input [38:0] io_sfence_bits_addr, // @[TLB.scala:320:14] input io_sfence_bits_asid, // @[TLB.scala:320:14] input io_sfence_bits_hv, // @[TLB.scala:320:14] input io_sfence_bits_hg, // @[TLB.scala:320:14] input io_ptw_req_ready, // @[TLB.scala:320:14] output io_ptw_req_valid, // @[TLB.scala:320:14] output [26:0] io_ptw_req_bits_bits_addr, // @[TLB.scala:320:14] output io_ptw_req_bits_bits_need_gpa, // @[TLB.scala:320:14] input io_ptw_resp_valid, // @[TLB.scala:320:14] input io_ptw_resp_bits_ae_ptw, // @[TLB.scala:320:14] input io_ptw_resp_bits_ae_final, // @[TLB.scala:320:14] input io_ptw_resp_bits_pf, // @[TLB.scala:320:14] input io_ptw_resp_bits_gf, // @[TLB.scala:320:14] input io_ptw_resp_bits_hr, // @[TLB.scala:320:14] input io_ptw_resp_bits_hw, // @[TLB.scala:320:14] input io_ptw_resp_bits_hx, // @[TLB.scala:320:14] input [9:0] io_ptw_resp_bits_pte_reserved_for_future, // @[TLB.scala:320:14] input [43:0] io_ptw_resp_bits_pte_ppn, // @[TLB.scala:320:14] input [1:0] io_ptw_resp_bits_pte_reserved_for_software, // @[TLB.scala:320:14] input io_ptw_resp_bits_pte_d, // @[TLB.scala:320:14] input io_ptw_resp_bits_pte_a, // @[TLB.scala:320:14] input io_ptw_resp_bits_pte_g, // @[TLB.scala:320:14] input io_ptw_resp_bits_pte_u, // @[TLB.scala:320:14] input io_ptw_resp_bits_pte_x, // @[TLB.scala:320:14] input io_ptw_resp_bits_pte_w, // @[TLB.scala:320:14] input io_ptw_resp_bits_pte_r, // @[TLB.scala:320:14] input io_ptw_resp_bits_pte_v, // @[TLB.scala:320:14] input [1:0] io_ptw_resp_bits_level, // @[TLB.scala:320:14] input io_ptw_resp_bits_homogeneous, // @[TLB.scala:320:14] input io_ptw_resp_bits_gpa_valid, // @[TLB.scala:320:14] input [38:0] io_ptw_resp_bits_gpa_bits, // @[TLB.scala:320:14] input io_ptw_resp_bits_gpa_is_pte, // @[TLB.scala:320:14] input [3:0] io_ptw_ptbr_mode, // @[TLB.scala:320:14] input [43:0] io_ptw_ptbr_ppn, // @[TLB.scala:320:14] input io_ptw_status_debug, // @[TLB.scala:320:14] input io_ptw_status_cease, // @[TLB.scala:320:14] input io_ptw_status_wfi, // @[TLB.scala:320:14] input [1:0] io_ptw_status_dprv, // @[TLB.scala:320:14] input io_ptw_status_dv, // @[TLB.scala:320:14] input [1:0] io_ptw_status_prv, // @[TLB.scala:320:14] input io_ptw_status_v, // @[TLB.scala:320:14] input io_ptw_status_sd, // @[TLB.scala:320:14] input io_ptw_status_mpv, // @[TLB.scala:320:14] input io_ptw_status_gva, // @[TLB.scala:320:14] input io_ptw_status_tsr, // @[TLB.scala:320:14] input io_ptw_status_tw, // @[TLB.scala:320:14] input io_ptw_status_tvm, // @[TLB.scala:320:14] input io_ptw_status_mxr, // @[TLB.scala:320:14] input io_ptw_status_sum, // @[TLB.scala:320:14] input io_ptw_status_mprv, // @[TLB.scala:320:14] input [1:0] io_ptw_status_fs, // @[TLB.scala:320:14] input [1:0] io_ptw_status_mpp, // @[TLB.scala:320:14] input io_ptw_status_spp, // @[TLB.scala:320:14] input io_ptw_status_mpie, // @[TLB.scala:320:14] input io_ptw_status_spie, // @[TLB.scala:320:14] input io_ptw_status_mie, // @[TLB.scala:320:14] input io_ptw_status_sie, // @[TLB.scala:320:14] input io_ptw_pmp_0_cfg_l, // @[TLB.scala:320:14] input [1:0] io_ptw_pmp_0_cfg_a, // @[TLB.scala:320:14] input io_ptw_pmp_0_cfg_x, // @[TLB.scala:320:14] input io_ptw_pmp_0_cfg_w, // @[TLB.scala:320:14] input io_ptw_pmp_0_cfg_r, // @[TLB.scala:320:14] input [29:0] io_ptw_pmp_0_addr, // @[TLB.scala:320:14] input [31:0] io_ptw_pmp_0_mask, // @[TLB.scala:320:14] input io_ptw_pmp_1_cfg_l, // @[TLB.scala:320:14] input [1:0] io_ptw_pmp_1_cfg_a, // @[TLB.scala:320:14] input io_ptw_pmp_1_cfg_x, // @[TLB.scala:320:14] input io_ptw_pmp_1_cfg_w, // @[TLB.scala:320:14] input io_ptw_pmp_1_cfg_r, // @[TLB.scala:320:14] input [29:0] io_ptw_pmp_1_addr, // @[TLB.scala:320:14] input [31:0] io_ptw_pmp_1_mask, // @[TLB.scala:320:14] input io_ptw_pmp_2_cfg_l, // @[TLB.scala:320:14] input [1:0] io_ptw_pmp_2_cfg_a, // @[TLB.scala:320:14] input io_ptw_pmp_2_cfg_x, // @[TLB.scala:320:14] input io_ptw_pmp_2_cfg_w, // @[TLB.scala:320:14] input io_ptw_pmp_2_cfg_r, // @[TLB.scala:320:14] input [29:0] io_ptw_pmp_2_addr, // @[TLB.scala:320:14] input [31:0] io_ptw_pmp_2_mask, // @[TLB.scala:320:14] input io_ptw_pmp_3_cfg_l, // @[TLB.scala:320:14] input [1:0] io_ptw_pmp_3_cfg_a, // @[TLB.scala:320:14] input io_ptw_pmp_3_cfg_x, // @[TLB.scala:320:14] input io_ptw_pmp_3_cfg_w, // @[TLB.scala:320:14] input io_ptw_pmp_3_cfg_r, // @[TLB.scala:320:14] input [29:0] io_ptw_pmp_3_addr, // @[TLB.scala:320:14] input [31:0] io_ptw_pmp_3_mask, // @[TLB.scala:320:14] input io_ptw_pmp_4_cfg_l, // @[TLB.scala:320:14] input [1:0] io_ptw_pmp_4_cfg_a, // @[TLB.scala:320:14] input io_ptw_pmp_4_cfg_x, // @[TLB.scala:320:14] input io_ptw_pmp_4_cfg_w, // @[TLB.scala:320:14] input io_ptw_pmp_4_cfg_r, // @[TLB.scala:320:14] input [29:0] io_ptw_pmp_4_addr, // @[TLB.scala:320:14] input [31:0] io_ptw_pmp_4_mask, // @[TLB.scala:320:14] input io_ptw_pmp_5_cfg_l, // @[TLB.scala:320:14] input [1:0] io_ptw_pmp_5_cfg_a, // @[TLB.scala:320:14] input io_ptw_pmp_5_cfg_x, // @[TLB.scala:320:14] input io_ptw_pmp_5_cfg_w, // @[TLB.scala:320:14] input io_ptw_pmp_5_cfg_r, // @[TLB.scala:320:14] input [29:0] io_ptw_pmp_5_addr, // @[TLB.scala:320:14] input [31:0] io_ptw_pmp_5_mask, // @[TLB.scala:320:14] input io_ptw_pmp_6_cfg_l, // @[TLB.scala:320:14] input [1:0] io_ptw_pmp_6_cfg_a, // @[TLB.scala:320:14] input io_ptw_pmp_6_cfg_x, // @[TLB.scala:320:14] input io_ptw_pmp_6_cfg_w, // @[TLB.scala:320:14] input io_ptw_pmp_6_cfg_r, // @[TLB.scala:320:14] input [29:0] io_ptw_pmp_6_addr, // @[TLB.scala:320:14] input [31:0] io_ptw_pmp_6_mask, // @[TLB.scala:320:14] input io_ptw_pmp_7_cfg_l, // @[TLB.scala:320:14] input [1:0] io_ptw_pmp_7_cfg_a, // @[TLB.scala:320:14] input io_ptw_pmp_7_cfg_x, // @[TLB.scala:320:14] input io_ptw_pmp_7_cfg_w, // @[TLB.scala:320:14] input io_ptw_pmp_7_cfg_r, // @[TLB.scala:320:14] input [29:0] io_ptw_pmp_7_addr, // @[TLB.scala:320:14] input [31:0] io_ptw_pmp_7_mask // @[TLB.scala:320:14] ); wire [19:0] _entries_barrier_12_io_y_ppn; // @[package.scala:267:25] wire _entries_barrier_12_io_y_u; // @[package.scala:267:25] wire _entries_barrier_12_io_y_ae_ptw; // @[package.scala:267:25] wire _entries_barrier_12_io_y_ae_final; // @[package.scala:267:25] wire _entries_barrier_12_io_y_ae_stage2; // @[package.scala:267:25] wire _entries_barrier_12_io_y_pf; // @[package.scala:267:25] wire _entries_barrier_12_io_y_gf; // @[package.scala:267:25] wire _entries_barrier_12_io_y_sw; // @[package.scala:267:25] wire _entries_barrier_12_io_y_sx; // @[package.scala:267:25] wire _entries_barrier_12_io_y_sr; // @[package.scala:267:25] wire _entries_barrier_12_io_y_hw; // @[package.scala:267:25] wire _entries_barrier_12_io_y_hx; // @[package.scala:267:25] wire _entries_barrier_12_io_y_hr; // @[package.scala:267:25] wire [19:0] _entries_barrier_11_io_y_ppn; // @[package.scala:267:25] wire _entries_barrier_11_io_y_u; // @[package.scala:267:25] wire _entries_barrier_11_io_y_ae_ptw; // @[package.scala:267:25] wire _entries_barrier_11_io_y_ae_final; // @[package.scala:267:25] wire _entries_barrier_11_io_y_ae_stage2; // @[package.scala:267:25] wire _entries_barrier_11_io_y_pf; // @[package.scala:267:25] wire _entries_barrier_11_io_y_gf; // @[package.scala:267:25] wire _entries_barrier_11_io_y_sw; // @[package.scala:267:25] wire _entries_barrier_11_io_y_sx; // @[package.scala:267:25] wire _entries_barrier_11_io_y_sr; // @[package.scala:267:25] wire _entries_barrier_11_io_y_hw; // @[package.scala:267:25] wire _entries_barrier_11_io_y_hx; // @[package.scala:267:25] wire _entries_barrier_11_io_y_hr; // @[package.scala:267:25] wire _entries_barrier_11_io_y_pw; // @[package.scala:267:25] wire _entries_barrier_11_io_y_px; // @[package.scala:267:25] wire _entries_barrier_11_io_y_pr; // @[package.scala:267:25] wire _entries_barrier_11_io_y_ppp; // @[package.scala:267:25] wire _entries_barrier_11_io_y_pal; // @[package.scala:267:25] wire _entries_barrier_11_io_y_paa; // @[package.scala:267:25] wire _entries_barrier_11_io_y_eff; // @[package.scala:267:25] wire _entries_barrier_11_io_y_c; // @[package.scala:267:25] wire [19:0] _entries_barrier_10_io_y_ppn; // @[package.scala:267:25] wire _entries_barrier_10_io_y_u; // @[package.scala:267:25] wire _entries_barrier_10_io_y_ae_ptw; // @[package.scala:267:25] wire _entries_barrier_10_io_y_ae_final; // @[package.scala:267:25] wire _entries_barrier_10_io_y_ae_stage2; // @[package.scala:267:25] wire _entries_barrier_10_io_y_pf; // @[package.scala:267:25] wire _entries_barrier_10_io_y_gf; // @[package.scala:267:25] wire _entries_barrier_10_io_y_sw; // @[package.scala:267:25] wire _entries_barrier_10_io_y_sx; // @[package.scala:267:25] wire _entries_barrier_10_io_y_sr; // @[package.scala:267:25] wire _entries_barrier_10_io_y_hw; // @[package.scala:267:25] wire _entries_barrier_10_io_y_hx; // @[package.scala:267:25] wire _entries_barrier_10_io_y_hr; // @[package.scala:267:25] wire _entries_barrier_10_io_y_pw; // @[package.scala:267:25] wire _entries_barrier_10_io_y_px; // @[package.scala:267:25] wire _entries_barrier_10_io_y_pr; // @[package.scala:267:25] wire _entries_barrier_10_io_y_ppp; // @[package.scala:267:25] wire _entries_barrier_10_io_y_pal; // @[package.scala:267:25] wire _entries_barrier_10_io_y_paa; // @[package.scala:267:25] wire _entries_barrier_10_io_y_eff; // @[package.scala:267:25] wire _entries_barrier_10_io_y_c; // @[package.scala:267:25] wire [19:0] _entries_barrier_9_io_y_ppn; // @[package.scala:267:25] wire _entries_barrier_9_io_y_u; // @[package.scala:267:25] wire _entries_barrier_9_io_y_ae_ptw; // @[package.scala:267:25] wire _entries_barrier_9_io_y_ae_final; // @[package.scala:267:25] wire _entries_barrier_9_io_y_ae_stage2; // @[package.scala:267:25] wire _entries_barrier_9_io_y_pf; // @[package.scala:267:25] wire _entries_barrier_9_io_y_gf; // @[package.scala:267:25] wire _entries_barrier_9_io_y_sw; // @[package.scala:267:25] wire _entries_barrier_9_io_y_sx; // @[package.scala:267:25] wire _entries_barrier_9_io_y_sr; // @[package.scala:267:25] wire _entries_barrier_9_io_y_hw; // @[package.scala:267:25] wire _entries_barrier_9_io_y_hx; // @[package.scala:267:25] wire _entries_barrier_9_io_y_hr; // @[package.scala:267:25] wire _entries_barrier_9_io_y_pw; // @[package.scala:267:25] wire _entries_barrier_9_io_y_px; // @[package.scala:267:25] wire _entries_barrier_9_io_y_pr; // @[package.scala:267:25] wire _entries_barrier_9_io_y_ppp; // @[package.scala:267:25] wire _entries_barrier_9_io_y_pal; // @[package.scala:267:25] wire _entries_barrier_9_io_y_paa; // @[package.scala:267:25] wire _entries_barrier_9_io_y_eff; // @[package.scala:267:25] wire _entries_barrier_9_io_y_c; // @[package.scala:267:25] wire [19:0] _entries_barrier_8_io_y_ppn; // @[package.scala:267:25] wire _entries_barrier_8_io_y_u; // @[package.scala:267:25] wire _entries_barrier_8_io_y_ae_ptw; // @[package.scala:267:25] wire _entries_barrier_8_io_y_ae_final; // @[package.scala:267:25] wire _entries_barrier_8_io_y_ae_stage2; // @[package.scala:267:25] wire _entries_barrier_8_io_y_pf; // @[package.scala:267:25] wire _entries_barrier_8_io_y_gf; // @[package.scala:267:25] wire _entries_barrier_8_io_y_sw; // @[package.scala:267:25] wire _entries_barrier_8_io_y_sx; // @[package.scala:267:25] wire _entries_barrier_8_io_y_sr; // @[package.scala:267:25] wire _entries_barrier_8_io_y_hw; // @[package.scala:267:25] wire _entries_barrier_8_io_y_hx; // @[package.scala:267:25] wire _entries_barrier_8_io_y_hr; // @[package.scala:267:25] wire _entries_barrier_8_io_y_pw; // @[package.scala:267:25] wire _entries_barrier_8_io_y_px; // @[package.scala:267:25] wire _entries_barrier_8_io_y_pr; // @[package.scala:267:25] wire _entries_barrier_8_io_y_ppp; // @[package.scala:267:25] wire _entries_barrier_8_io_y_pal; // @[package.scala:267:25] wire _entries_barrier_8_io_y_paa; // @[package.scala:267:25] wire _entries_barrier_8_io_y_eff; // @[package.scala:267:25] wire _entries_barrier_8_io_y_c; // @[package.scala:267:25] wire [19:0] _entries_barrier_7_io_y_ppn; // @[package.scala:267:25] wire _entries_barrier_7_io_y_u; // @[package.scala:267:25] wire _entries_barrier_7_io_y_ae_ptw; // @[package.scala:267:25] wire _entries_barrier_7_io_y_ae_final; // @[package.scala:267:25] wire _entries_barrier_7_io_y_ae_stage2; // @[package.scala:267:25] wire _entries_barrier_7_io_y_pf; // @[package.scala:267:25] wire _entries_barrier_7_io_y_gf; // @[package.scala:267:25] wire _entries_barrier_7_io_y_sw; // @[package.scala:267:25] wire _entries_barrier_7_io_y_sx; // @[package.scala:267:25] wire _entries_barrier_7_io_y_sr; // @[package.scala:267:25] wire _entries_barrier_7_io_y_hw; // @[package.scala:267:25] wire _entries_barrier_7_io_y_hx; // @[package.scala:267:25] wire _entries_barrier_7_io_y_hr; // @[package.scala:267:25] wire _entries_barrier_7_io_y_pw; // @[package.scala:267:25] wire _entries_barrier_7_io_y_px; // @[package.scala:267:25] wire _entries_barrier_7_io_y_pr; // @[package.scala:267:25] wire _entries_barrier_7_io_y_ppp; // @[package.scala:267:25] wire _entries_barrier_7_io_y_pal; // @[package.scala:267:25] wire _entries_barrier_7_io_y_paa; // @[package.scala:267:25] wire _entries_barrier_7_io_y_eff; // @[package.scala:267:25] wire _entries_barrier_7_io_y_c; // @[package.scala:267:25] wire [19:0] _entries_barrier_6_io_y_ppn; // @[package.scala:267:25] wire _entries_barrier_6_io_y_u; // @[package.scala:267:25] wire _entries_barrier_6_io_y_ae_ptw; // @[package.scala:267:25] wire _entries_barrier_6_io_y_ae_final; // @[package.scala:267:25] wire _entries_barrier_6_io_y_ae_stage2; // @[package.scala:267:25] wire _entries_barrier_6_io_y_pf; // @[package.scala:267:25] wire _entries_barrier_6_io_y_gf; // @[package.scala:267:25] wire _entries_barrier_6_io_y_sw; // @[package.scala:267:25] wire _entries_barrier_6_io_y_sx; // @[package.scala:267:25] wire _entries_barrier_6_io_y_sr; // @[package.scala:267:25] wire _entries_barrier_6_io_y_hw; // @[package.scala:267:25] wire _entries_barrier_6_io_y_hx; // @[package.scala:267:25] wire _entries_barrier_6_io_y_hr; // @[package.scala:267:25] wire _entries_barrier_6_io_y_pw; // @[package.scala:267:25] wire _entries_barrier_6_io_y_px; // @[package.scala:267:25] wire _entries_barrier_6_io_y_pr; // @[package.scala:267:25] wire _entries_barrier_6_io_y_ppp; // @[package.scala:267:25] wire _entries_barrier_6_io_y_pal; // @[package.scala:267:25] wire _entries_barrier_6_io_y_paa; // @[package.scala:267:25] wire _entries_barrier_6_io_y_eff; // @[package.scala:267:25] wire _entries_barrier_6_io_y_c; // @[package.scala:267:25] wire [19:0] _entries_barrier_5_io_y_ppn; // @[package.scala:267:25] wire _entries_barrier_5_io_y_u; // @[package.scala:267:25] wire _entries_barrier_5_io_y_ae_ptw; // @[package.scala:267:25] wire _entries_barrier_5_io_y_ae_final; // @[package.scala:267:25] wire _entries_barrier_5_io_y_ae_stage2; // @[package.scala:267:25] wire _entries_barrier_5_io_y_pf; // @[package.scala:267:25] wire _entries_barrier_5_io_y_gf; // @[package.scala:267:25] wire _entries_barrier_5_io_y_sw; // @[package.scala:267:25] wire _entries_barrier_5_io_y_sx; // @[package.scala:267:25] wire _entries_barrier_5_io_y_sr; // @[package.scala:267:25] wire _entries_barrier_5_io_y_hw; // @[package.scala:267:25] wire _entries_barrier_5_io_y_hx; // @[package.scala:267:25] wire _entries_barrier_5_io_y_hr; // @[package.scala:267:25] wire _entries_barrier_5_io_y_pw; // @[package.scala:267:25] wire _entries_barrier_5_io_y_px; // @[package.scala:267:25] wire _entries_barrier_5_io_y_pr; // @[package.scala:267:25] wire _entries_barrier_5_io_y_ppp; // @[package.scala:267:25] wire _entries_barrier_5_io_y_pal; // @[package.scala:267:25] wire _entries_barrier_5_io_y_paa; // @[package.scala:267:25] wire _entries_barrier_5_io_y_eff; // @[package.scala:267:25] wire _entries_barrier_5_io_y_c; // @[package.scala:267:25] wire [19:0] _entries_barrier_4_io_y_ppn; // @[package.scala:267:25] wire _entries_barrier_4_io_y_u; // @[package.scala:267:25] wire _entries_barrier_4_io_y_ae_ptw; // @[package.scala:267:25] wire _entries_barrier_4_io_y_ae_final; // @[package.scala:267:25] wire _entries_barrier_4_io_y_ae_stage2; // @[package.scala:267:25] wire _entries_barrier_4_io_y_pf; // @[package.scala:267:25] wire _entries_barrier_4_io_y_gf; // @[package.scala:267:25] wire _entries_barrier_4_io_y_sw; // @[package.scala:267:25] wire _entries_barrier_4_io_y_sx; // @[package.scala:267:25] wire _entries_barrier_4_io_y_sr; // @[package.scala:267:25] wire _entries_barrier_4_io_y_hw; // @[package.scala:267:25] wire _entries_barrier_4_io_y_hx; // @[package.scala:267:25] wire _entries_barrier_4_io_y_hr; // @[package.scala:267:25] wire _entries_barrier_4_io_y_pw; // @[package.scala:267:25] wire _entries_barrier_4_io_y_px; // @[package.scala:267:25] wire _entries_barrier_4_io_y_pr; // @[package.scala:267:25] wire _entries_barrier_4_io_y_ppp; // @[package.scala:267:25] wire _entries_barrier_4_io_y_pal; // @[package.scala:267:25] wire _entries_barrier_4_io_y_paa; // @[package.scala:267:25] wire _entries_barrier_4_io_y_eff; // @[package.scala:267:25] wire _entries_barrier_4_io_y_c; // @[package.scala:267:25] wire [19:0] _entries_barrier_3_io_y_ppn; // @[package.scala:267:25] wire _entries_barrier_3_io_y_u; // @[package.scala:267:25] wire _entries_barrier_3_io_y_ae_ptw; // @[package.scala:267:25] wire _entries_barrier_3_io_y_ae_final; // @[package.scala:267:25] wire _entries_barrier_3_io_y_ae_stage2; // @[package.scala:267:25] wire _entries_barrier_3_io_y_pf; // @[package.scala:267:25] wire _entries_barrier_3_io_y_gf; // @[package.scala:267:25] wire _entries_barrier_3_io_y_sw; // @[package.scala:267:25] wire _entries_barrier_3_io_y_sx; // @[package.scala:267:25] wire _entries_barrier_3_io_y_sr; // @[package.scala:267:25] wire _entries_barrier_3_io_y_hw; // @[package.scala:267:25] wire _entries_barrier_3_io_y_hx; // @[package.scala:267:25] wire _entries_barrier_3_io_y_hr; // @[package.scala:267:25] wire _entries_barrier_3_io_y_pw; // @[package.scala:267:25] wire _entries_barrier_3_io_y_px; // @[package.scala:267:25] wire _entries_barrier_3_io_y_pr; // @[package.scala:267:25] wire _entries_barrier_3_io_y_ppp; // @[package.scala:267:25] wire _entries_barrier_3_io_y_pal; // @[package.scala:267:25] wire _entries_barrier_3_io_y_paa; // @[package.scala:267:25] wire _entries_barrier_3_io_y_eff; // @[package.scala:267:25] wire _entries_barrier_3_io_y_c; // @[package.scala:267:25] wire [19:0] _entries_barrier_2_io_y_ppn; // @[package.scala:267:25] wire _entries_barrier_2_io_y_u; // @[package.scala:267:25] wire _entries_barrier_2_io_y_ae_ptw; // @[package.scala:267:25] wire _entries_barrier_2_io_y_ae_final; // @[package.scala:267:25] wire _entries_barrier_2_io_y_ae_stage2; // @[package.scala:267:25] wire _entries_barrier_2_io_y_pf; // @[package.scala:267:25] wire _entries_barrier_2_io_y_gf; // @[package.scala:267:25] wire _entries_barrier_2_io_y_sw; // @[package.scala:267:25] wire _entries_barrier_2_io_y_sx; // @[package.scala:267:25] wire _entries_barrier_2_io_y_sr; // @[package.scala:267:25] wire _entries_barrier_2_io_y_hw; // @[package.scala:267:25] wire _entries_barrier_2_io_y_hx; // @[package.scala:267:25] wire _entries_barrier_2_io_y_hr; // @[package.scala:267:25] wire _entries_barrier_2_io_y_pw; // @[package.scala:267:25] wire _entries_barrier_2_io_y_px; // @[package.scala:267:25] wire _entries_barrier_2_io_y_pr; // @[package.scala:267:25] wire _entries_barrier_2_io_y_ppp; // @[package.scala:267:25] wire _entries_barrier_2_io_y_pal; // @[package.scala:267:25] wire _entries_barrier_2_io_y_paa; // @[package.scala:267:25] wire _entries_barrier_2_io_y_eff; // @[package.scala:267:25] wire _entries_barrier_2_io_y_c; // @[package.scala:267:25] wire [19:0] _entries_barrier_1_io_y_ppn; // @[package.scala:267:25] wire _entries_barrier_1_io_y_u; // @[package.scala:267:25] wire _entries_barrier_1_io_y_ae_ptw; // @[package.scala:267:25] wire _entries_barrier_1_io_y_ae_final; // @[package.scala:267:25] wire _entries_barrier_1_io_y_ae_stage2; // @[package.scala:267:25] wire _entries_barrier_1_io_y_pf; // @[package.scala:267:25] wire _entries_barrier_1_io_y_gf; // @[package.scala:267:25] wire _entries_barrier_1_io_y_sw; // @[package.scala:267:25] wire _entries_barrier_1_io_y_sx; // @[package.scala:267:25] wire _entries_barrier_1_io_y_sr; // @[package.scala:267:25] wire _entries_barrier_1_io_y_hw; // @[package.scala:267:25] wire _entries_barrier_1_io_y_hx; // @[package.scala:267:25] wire _entries_barrier_1_io_y_hr; // @[package.scala:267:25] wire _entries_barrier_1_io_y_pw; // @[package.scala:267:25] wire _entries_barrier_1_io_y_px; // @[package.scala:267:25] wire _entries_barrier_1_io_y_pr; // @[package.scala:267:25] wire _entries_barrier_1_io_y_ppp; // @[package.scala:267:25] wire _entries_barrier_1_io_y_pal; // @[package.scala:267:25] wire _entries_barrier_1_io_y_paa; // @[package.scala:267:25] wire _entries_barrier_1_io_y_eff; // @[package.scala:267:25] wire _entries_barrier_1_io_y_c; // @[package.scala:267:25] wire [19:0] _entries_barrier_io_y_ppn; // @[package.scala:267:25] wire _entries_barrier_io_y_u; // @[package.scala:267:25] wire _entries_barrier_io_y_ae_ptw; // @[package.scala:267:25] wire _entries_barrier_io_y_ae_final; // @[package.scala:267:25] wire _entries_barrier_io_y_ae_stage2; // @[package.scala:267:25] wire _entries_barrier_io_y_pf; // @[package.scala:267:25] wire _entries_barrier_io_y_gf; // @[package.scala:267:25] wire _entries_barrier_io_y_sw; // @[package.scala:267:25] wire _entries_barrier_io_y_sx; // @[package.scala:267:25] wire _entries_barrier_io_y_sr; // @[package.scala:267:25] wire _entries_barrier_io_y_hw; // @[package.scala:267:25] wire _entries_barrier_io_y_hx; // @[package.scala:267:25] wire _entries_barrier_io_y_hr; // @[package.scala:267:25] wire _entries_barrier_io_y_pw; // @[package.scala:267:25] wire _entries_barrier_io_y_px; // @[package.scala:267:25] wire _entries_barrier_io_y_pr; // @[package.scala:267:25] wire _entries_barrier_io_y_ppp; // @[package.scala:267:25] wire _entries_barrier_io_y_pal; // @[package.scala:267:25] wire _entries_barrier_io_y_paa; // @[package.scala:267:25] wire _entries_barrier_io_y_eff; // @[package.scala:267:25] wire _entries_barrier_io_y_c; // @[package.scala:267:25] wire _pma_io_resp_r; // @[TLB.scala:422:19] wire _pma_io_resp_w; // @[TLB.scala:422:19] wire _pma_io_resp_pp; // @[TLB.scala:422:19] wire _pma_io_resp_al; // @[TLB.scala:422:19] wire _pma_io_resp_aa; // @[TLB.scala:422:19] wire _pma_io_resp_x; // @[TLB.scala:422:19] wire _pma_io_resp_eff; // @[TLB.scala:422:19] wire _pmp_io_r; // @[TLB.scala:416:19] wire _pmp_io_w; // @[TLB.scala:416:19] wire _pmp_io_x; // @[TLB.scala:416:19] wire [19:0] _mpu_ppn_barrier_io_y_ppn; // @[package.scala:267:25] wire io_req_valid_0 = io_req_valid; // @[TLB.scala:318:7] wire [39:0] io_req_bits_vaddr_0 = io_req_bits_vaddr; // @[TLB.scala:318:7] wire [1:0] io_req_bits_prv_0 = io_req_bits_prv; // @[TLB.scala:318:7] wire io_req_bits_v_0 = io_req_bits_v; // @[TLB.scala:318:7] wire io_sfence_valid_0 = io_sfence_valid; // @[TLB.scala:318:7] wire io_sfence_bits_rs1_0 = io_sfence_bits_rs1; // @[TLB.scala:318:7] wire io_sfence_bits_rs2_0 = io_sfence_bits_rs2; // @[TLB.scala:318:7] wire [38:0] io_sfence_bits_addr_0 = io_sfence_bits_addr; // @[TLB.scala:318:7] wire io_sfence_bits_asid_0 = io_sfence_bits_asid; // @[TLB.scala:318:7] wire io_sfence_bits_hv_0 = io_sfence_bits_hv; // @[TLB.scala:318:7] wire io_sfence_bits_hg_0 = io_sfence_bits_hg; // @[TLB.scala:318:7] wire io_ptw_req_ready_0 = io_ptw_req_ready; // @[TLB.scala:318:7] wire io_ptw_resp_valid_0 = io_ptw_resp_valid; // @[TLB.scala:318:7] wire io_ptw_resp_bits_ae_ptw_0 = io_ptw_resp_bits_ae_ptw; // @[TLB.scala:318:7] wire io_ptw_resp_bits_ae_final_0 = io_ptw_resp_bits_ae_final; // @[TLB.scala:318:7] wire io_ptw_resp_bits_pf_0 = io_ptw_resp_bits_pf; // @[TLB.scala:318:7] wire io_ptw_resp_bits_gf_0 = io_ptw_resp_bits_gf; // @[TLB.scala:318:7] wire io_ptw_resp_bits_hr_0 = io_ptw_resp_bits_hr; // @[TLB.scala:318:7] wire io_ptw_resp_bits_hw_0 = io_ptw_resp_bits_hw; // @[TLB.scala:318:7] wire io_ptw_resp_bits_hx_0 = io_ptw_resp_bits_hx; // @[TLB.scala:318:7] wire [9:0] io_ptw_resp_bits_pte_reserved_for_future_0 = io_ptw_resp_bits_pte_reserved_for_future; // @[TLB.scala:318:7] wire [43:0] io_ptw_resp_bits_pte_ppn_0 = io_ptw_resp_bits_pte_ppn; // @[TLB.scala:318:7] wire [1:0] io_ptw_resp_bits_pte_reserved_for_software_0 = io_ptw_resp_bits_pte_reserved_for_software; // @[TLB.scala:318:7] wire io_ptw_resp_bits_pte_d_0 = io_ptw_resp_bits_pte_d; // @[TLB.scala:318:7] wire io_ptw_resp_bits_pte_a_0 = io_ptw_resp_bits_pte_a; // @[TLB.scala:318:7] wire io_ptw_resp_bits_pte_g_0 = io_ptw_resp_bits_pte_g; // @[TLB.scala:318:7] wire io_ptw_resp_bits_pte_u_0 = io_ptw_resp_bits_pte_u; // @[TLB.scala:318:7] wire io_ptw_resp_bits_pte_x_0 = io_ptw_resp_bits_pte_x; // @[TLB.scala:318:7] wire io_ptw_resp_bits_pte_w_0 = io_ptw_resp_bits_pte_w; // @[TLB.scala:318:7] wire io_ptw_resp_bits_pte_r_0 = io_ptw_resp_bits_pte_r; // @[TLB.scala:318:7] wire io_ptw_resp_bits_pte_v_0 = io_ptw_resp_bits_pte_v; // @[TLB.scala:318:7] wire [1:0] io_ptw_resp_bits_level_0 = io_ptw_resp_bits_level; // @[TLB.scala:318:7] wire io_ptw_resp_bits_homogeneous_0 = io_ptw_resp_bits_homogeneous; // @[TLB.scala:318:7] wire io_ptw_resp_bits_gpa_valid_0 = io_ptw_resp_bits_gpa_valid; // @[TLB.scala:318:7] wire [38:0] io_ptw_resp_bits_gpa_bits_0 = io_ptw_resp_bits_gpa_bits; // @[TLB.scala:318:7] wire io_ptw_resp_bits_gpa_is_pte_0 = io_ptw_resp_bits_gpa_is_pte; // @[TLB.scala:318:7] wire [3:0] io_ptw_ptbr_mode_0 = io_ptw_ptbr_mode; // @[TLB.scala:318:7] wire [43:0] io_ptw_ptbr_ppn_0 = io_ptw_ptbr_ppn; // @[TLB.scala:318:7] wire io_ptw_status_debug_0 = io_ptw_status_debug; // @[TLB.scala:318:7] wire io_ptw_status_cease_0 = io_ptw_status_cease; // @[TLB.scala:318:7] wire io_ptw_status_wfi_0 = io_ptw_status_wfi; // @[TLB.scala:318:7] wire [1:0] io_ptw_status_dprv_0 = io_ptw_status_dprv; // @[TLB.scala:318:7] wire io_ptw_status_dv_0 = io_ptw_status_dv; // @[TLB.scala:318:7] wire [1:0] io_ptw_status_prv_0 = io_ptw_status_prv; // @[TLB.scala:318:7] wire io_ptw_status_v_0 = io_ptw_status_v; // @[TLB.scala:318:7] wire io_ptw_status_sd_0 = io_ptw_status_sd; // @[TLB.scala:318:7] wire io_ptw_status_mpv_0 = io_ptw_status_mpv; // @[TLB.scala:318:7] wire io_ptw_status_gva_0 = io_ptw_status_gva; // @[TLB.scala:318:7] wire io_ptw_status_tsr_0 = io_ptw_status_tsr; // @[TLB.scala:318:7] wire io_ptw_status_tw_0 = io_ptw_status_tw; // @[TLB.scala:318:7] wire io_ptw_status_tvm_0 = io_ptw_status_tvm; // @[TLB.scala:318:7] wire io_ptw_status_mxr_0 = io_ptw_status_mxr; // @[TLB.scala:318:7] wire io_ptw_status_sum_0 = io_ptw_status_sum; // @[TLB.scala:318:7] wire io_ptw_status_mprv_0 = io_ptw_status_mprv; // @[TLB.scala:318:7] wire [1:0] io_ptw_status_fs_0 = io_ptw_status_fs; // @[TLB.scala:318:7] wire [1:0] io_ptw_status_mpp_0 = io_ptw_status_mpp; // @[TLB.scala:318:7] wire io_ptw_status_spp_0 = io_ptw_status_spp; // @[TLB.scala:318:7] wire io_ptw_status_mpie_0 = io_ptw_status_mpie; // @[TLB.scala:318:7] wire io_ptw_status_spie_0 = io_ptw_status_spie; // @[TLB.scala:318:7] wire io_ptw_status_mie_0 = io_ptw_status_mie; // @[TLB.scala:318:7] wire io_ptw_status_sie_0 = io_ptw_status_sie; // @[TLB.scala:318:7] wire io_ptw_pmp_0_cfg_l_0 = io_ptw_pmp_0_cfg_l; // @[TLB.scala:318:7] wire [1:0] io_ptw_pmp_0_cfg_a_0 = io_ptw_pmp_0_cfg_a; // @[TLB.scala:318:7] wire io_ptw_pmp_0_cfg_x_0 = io_ptw_pmp_0_cfg_x; // @[TLB.scala:318:7] wire io_ptw_pmp_0_cfg_w_0 = io_ptw_pmp_0_cfg_w; // @[TLB.scala:318:7] wire io_ptw_pmp_0_cfg_r_0 = io_ptw_pmp_0_cfg_r; // @[TLB.scala:318:7] wire [29:0] io_ptw_pmp_0_addr_0 = io_ptw_pmp_0_addr; // @[TLB.scala:318:7] wire [31:0] io_ptw_pmp_0_mask_0 = io_ptw_pmp_0_mask; // @[TLB.scala:318:7] wire io_ptw_pmp_1_cfg_l_0 = io_ptw_pmp_1_cfg_l; // @[TLB.scala:318:7] wire [1:0] io_ptw_pmp_1_cfg_a_0 = io_ptw_pmp_1_cfg_a; // @[TLB.scala:318:7] wire io_ptw_pmp_1_cfg_x_0 = io_ptw_pmp_1_cfg_x; // @[TLB.scala:318:7] wire io_ptw_pmp_1_cfg_w_0 = io_ptw_pmp_1_cfg_w; // @[TLB.scala:318:7] wire io_ptw_pmp_1_cfg_r_0 = io_ptw_pmp_1_cfg_r; // @[TLB.scala:318:7] wire [29:0] io_ptw_pmp_1_addr_0 = io_ptw_pmp_1_addr; // @[TLB.scala:318:7] wire [31:0] io_ptw_pmp_1_mask_0 = io_ptw_pmp_1_mask; // @[TLB.scala:318:7] wire io_ptw_pmp_2_cfg_l_0 = io_ptw_pmp_2_cfg_l; // @[TLB.scala:318:7] wire [1:0] io_ptw_pmp_2_cfg_a_0 = io_ptw_pmp_2_cfg_a; // @[TLB.scala:318:7] wire io_ptw_pmp_2_cfg_x_0 = io_ptw_pmp_2_cfg_x; // @[TLB.scala:318:7] wire io_ptw_pmp_2_cfg_w_0 = io_ptw_pmp_2_cfg_w; // @[TLB.scala:318:7] wire io_ptw_pmp_2_cfg_r_0 = io_ptw_pmp_2_cfg_r; // @[TLB.scala:318:7] wire [29:0] io_ptw_pmp_2_addr_0 = io_ptw_pmp_2_addr; // @[TLB.scala:318:7] wire [31:0] io_ptw_pmp_2_mask_0 = io_ptw_pmp_2_mask; // @[TLB.scala:318:7] wire io_ptw_pmp_3_cfg_l_0 = io_ptw_pmp_3_cfg_l; // @[TLB.scala:318:7] wire [1:0] io_ptw_pmp_3_cfg_a_0 = io_ptw_pmp_3_cfg_a; // @[TLB.scala:318:7] wire io_ptw_pmp_3_cfg_x_0 = io_ptw_pmp_3_cfg_x; // @[TLB.scala:318:7] wire io_ptw_pmp_3_cfg_w_0 = io_ptw_pmp_3_cfg_w; // @[TLB.scala:318:7] wire io_ptw_pmp_3_cfg_r_0 = io_ptw_pmp_3_cfg_r; // @[TLB.scala:318:7] wire [29:0] io_ptw_pmp_3_addr_0 = io_ptw_pmp_3_addr; // @[TLB.scala:318:7] wire [31:0] io_ptw_pmp_3_mask_0 = io_ptw_pmp_3_mask; // @[TLB.scala:318:7] wire io_ptw_pmp_4_cfg_l_0 = io_ptw_pmp_4_cfg_l; // @[TLB.scala:318:7] wire [1:0] io_ptw_pmp_4_cfg_a_0 = io_ptw_pmp_4_cfg_a; // @[TLB.scala:318:7] wire io_ptw_pmp_4_cfg_x_0 = io_ptw_pmp_4_cfg_x; // @[TLB.scala:318:7] wire io_ptw_pmp_4_cfg_w_0 = io_ptw_pmp_4_cfg_w; // @[TLB.scala:318:7] wire io_ptw_pmp_4_cfg_r_0 = io_ptw_pmp_4_cfg_r; // @[TLB.scala:318:7] wire [29:0] io_ptw_pmp_4_addr_0 = io_ptw_pmp_4_addr; // @[TLB.scala:318:7] wire [31:0] io_ptw_pmp_4_mask_0 = io_ptw_pmp_4_mask; // @[TLB.scala:318:7] wire io_ptw_pmp_5_cfg_l_0 = io_ptw_pmp_5_cfg_l; // @[TLB.scala:318:7] wire [1:0] io_ptw_pmp_5_cfg_a_0 = io_ptw_pmp_5_cfg_a; // @[TLB.scala:318:7] wire io_ptw_pmp_5_cfg_x_0 = io_ptw_pmp_5_cfg_x; // @[TLB.scala:318:7] wire io_ptw_pmp_5_cfg_w_0 = io_ptw_pmp_5_cfg_w; // @[TLB.scala:318:7] wire io_ptw_pmp_5_cfg_r_0 = io_ptw_pmp_5_cfg_r; // @[TLB.scala:318:7] wire [29:0] io_ptw_pmp_5_addr_0 = io_ptw_pmp_5_addr; // @[TLB.scala:318:7] wire [31:0] io_ptw_pmp_5_mask_0 = io_ptw_pmp_5_mask; // @[TLB.scala:318:7] wire io_ptw_pmp_6_cfg_l_0 = io_ptw_pmp_6_cfg_l; // @[TLB.scala:318:7] wire [1:0] io_ptw_pmp_6_cfg_a_0 = io_ptw_pmp_6_cfg_a; // @[TLB.scala:318:7] wire io_ptw_pmp_6_cfg_x_0 = io_ptw_pmp_6_cfg_x; // @[TLB.scala:318:7] wire io_ptw_pmp_6_cfg_w_0 = io_ptw_pmp_6_cfg_w; // @[TLB.scala:318:7] wire io_ptw_pmp_6_cfg_r_0 = io_ptw_pmp_6_cfg_r; // @[TLB.scala:318:7] wire [29:0] io_ptw_pmp_6_addr_0 = io_ptw_pmp_6_addr; // @[TLB.scala:318:7] wire [31:0] io_ptw_pmp_6_mask_0 = io_ptw_pmp_6_mask; // @[TLB.scala:318:7] wire io_ptw_pmp_7_cfg_l_0 = io_ptw_pmp_7_cfg_l; // @[TLB.scala:318:7] wire [1:0] io_ptw_pmp_7_cfg_a_0 = io_ptw_pmp_7_cfg_a; // @[TLB.scala:318:7] wire io_ptw_pmp_7_cfg_x_0 = io_ptw_pmp_7_cfg_x; // @[TLB.scala:318:7] wire io_ptw_pmp_7_cfg_w_0 = io_ptw_pmp_7_cfg_w; // @[TLB.scala:318:7] wire io_ptw_pmp_7_cfg_r_0 = io_ptw_pmp_7_cfg_r; // @[TLB.scala:318:7] wire [29:0] io_ptw_pmp_7_addr_0 = io_ptw_pmp_7_addr; // @[TLB.scala:318:7] wire [31:0] io_ptw_pmp_7_mask_0 = io_ptw_pmp_7_mask; // @[TLB.scala:318:7] wire io_req_bits_passthrough = 1'h0; // @[TLB.scala:318:7] wire io_resp_gpa_is_pte = 1'h0; // @[TLB.scala:318:7] wire io_resp_pf_st = 1'h0; // @[TLB.scala:318:7] wire io_resp_gf_ld = 1'h0; // @[TLB.scala:318:7] wire io_resp_gf_st = 1'h0; // @[TLB.scala:318:7] wire io_resp_gf_inst = 1'h0; // @[TLB.scala:318:7] wire io_resp_ae_st = 1'h0; // @[TLB.scala:318:7] wire io_resp_ma_st = 1'h0; // @[TLB.scala:318:7] wire io_resp_ma_inst = 1'h0; // @[TLB.scala:318:7] wire io_resp_must_alloc = 1'h0; // @[TLB.scala:318:7] wire io_ptw_req_bits_bits_vstage1 = 1'h0; // @[TLB.scala:318:7] wire io_ptw_req_bits_bits_stage2 = 1'h0; // @[TLB.scala:318:7] wire io_ptw_resp_bits_fragmented_superpage = 1'h0; // @[TLB.scala:318:7] wire io_ptw_status_mbe = 1'h0; // @[TLB.scala:318:7] wire io_ptw_status_sbe = 1'h0; // @[TLB.scala:318:7] wire io_ptw_status_sd_rv32 = 1'h0; // @[TLB.scala:318:7] wire io_ptw_status_ube = 1'h0; // @[TLB.scala:318:7] wire io_ptw_status_upie = 1'h0; // @[TLB.scala:318:7] wire io_ptw_status_hie = 1'h0; // @[TLB.scala:318:7] wire io_ptw_status_uie = 1'h0; // @[TLB.scala:318:7] wire io_ptw_hstatus_vtsr = 1'h0; // @[TLB.scala:318:7] wire io_ptw_hstatus_vtw = 1'h0; // @[TLB.scala:318:7] wire io_ptw_hstatus_vtvm = 1'h0; // @[TLB.scala:318:7] wire io_ptw_hstatus_hu = 1'h0; // @[TLB.scala:318:7] wire io_ptw_hstatus_spvp = 1'h0; // @[TLB.scala:318:7] wire io_ptw_hstatus_spv = 1'h0; // @[TLB.scala:318:7] wire io_ptw_hstatus_gva = 1'h0; // @[TLB.scala:318:7] wire io_ptw_hstatus_vsbe = 1'h0; // @[TLB.scala:318:7] wire io_ptw_gstatus_debug = 1'h0; // @[TLB.scala:318:7] wire io_ptw_gstatus_cease = 1'h0; // @[TLB.scala:318:7] wire io_ptw_gstatus_wfi = 1'h0; // @[TLB.scala:318:7] wire io_ptw_gstatus_dv = 1'h0; // @[TLB.scala:318:7] wire io_ptw_gstatus_v = 1'h0; // @[TLB.scala:318:7] wire io_ptw_gstatus_sd = 1'h0; // @[TLB.scala:318:7] wire io_ptw_gstatus_mpv = 1'h0; // @[TLB.scala:318:7] wire io_ptw_gstatus_gva = 1'h0; // @[TLB.scala:318:7] wire io_ptw_gstatus_mbe = 1'h0; // @[TLB.scala:318:7] wire io_ptw_gstatus_sbe = 1'h0; // @[TLB.scala:318:7] wire io_ptw_gstatus_sd_rv32 = 1'h0; // @[TLB.scala:318:7] wire io_ptw_gstatus_tsr = 1'h0; // @[TLB.scala:318:7] wire io_ptw_gstatus_tw = 1'h0; // @[TLB.scala:318:7] wire io_ptw_gstatus_tvm = 1'h0; // @[TLB.scala:318:7] wire io_ptw_gstatus_mxr = 1'h0; // @[TLB.scala:318:7] wire io_ptw_gstatus_sum = 1'h0; // @[TLB.scala:318:7] wire io_ptw_gstatus_mprv = 1'h0; // @[TLB.scala:318:7] wire io_ptw_gstatus_spp = 1'h0; // @[TLB.scala:318:7] wire io_ptw_gstatus_mpie = 1'h0; // @[TLB.scala:318:7] wire io_ptw_gstatus_ube = 1'h0; // @[TLB.scala:318:7] wire io_ptw_gstatus_spie = 1'h0; // @[TLB.scala:318:7] wire io_ptw_gstatus_upie = 1'h0; // @[TLB.scala:318:7] wire io_ptw_gstatus_mie = 1'h0; // @[TLB.scala:318:7] wire io_ptw_gstatus_hie = 1'h0; // @[TLB.scala:318:7] wire io_ptw_gstatus_sie = 1'h0; // @[TLB.scala:318:7] wire io_ptw_gstatus_uie = 1'h0; // @[TLB.scala:318:7] wire io_ptw_customCSRs_csrs_0_ren = 1'h0; // @[TLB.scala:318:7] wire io_ptw_customCSRs_csrs_0_wen = 1'h0; // @[TLB.scala:318:7] wire io_ptw_customCSRs_csrs_0_stall = 1'h0; // @[TLB.scala:318:7] wire io_ptw_customCSRs_csrs_0_set = 1'h0; // @[TLB.scala:318:7] wire io_ptw_customCSRs_csrs_1_ren = 1'h0; // @[TLB.scala:318:7] wire io_ptw_customCSRs_csrs_1_wen = 1'h0; // @[TLB.scala:318:7] wire io_ptw_customCSRs_csrs_1_stall = 1'h0; // @[TLB.scala:318:7] wire io_ptw_customCSRs_csrs_1_set = 1'h0; // @[TLB.scala:318:7] wire io_kill = 1'h0; // @[TLB.scala:318:7] wire priv_v = 1'h0; // @[TLB.scala:369:34] wire _vstage1_en_T = 1'h0; // @[TLB.scala:376:38] wire _vstage1_en_T_1 = 1'h0; // @[TLB.scala:376:68] wire vstage1_en = 1'h0; // @[TLB.scala:376:48] wire _stage2_en_T = 1'h0; // @[TLB.scala:378:38] wire _stage2_en_T_1 = 1'h0; // @[TLB.scala:378:68] wire stage2_en = 1'h0; // @[TLB.scala:378:48] wire _vsatp_mode_mismatch_T = 1'h0; // @[TLB.scala:403:52] wire _vsatp_mode_mismatch_T_1 = 1'h0; // @[TLB.scala:403:37] wire vsatp_mode_mismatch = 1'h0; // @[TLB.scala:403:78] wire _superpage_hits_ignore_T = 1'h0; // @[TLB.scala:182:28] wire superpage_hits_ignore = 1'h0; // @[TLB.scala:182:34] wire _superpage_hits_ignore_T_3 = 1'h0; // @[TLB.scala:182:28] wire superpage_hits_ignore_3 = 1'h0; // @[TLB.scala:182:34] wire _superpage_hits_ignore_T_6 = 1'h0; // @[TLB.scala:182:28] wire superpage_hits_ignore_6 = 1'h0; // @[TLB.scala:182:34] wire _superpage_hits_ignore_T_9 = 1'h0; // @[TLB.scala:182:28] wire superpage_hits_ignore_9 = 1'h0; // @[TLB.scala:182:34] wire _hitsVec_ignore_T = 1'h0; // @[TLB.scala:182:28] wire hitsVec_ignore = 1'h0; // @[TLB.scala:182:34] wire _hitsVec_ignore_T_3 = 1'h0; // @[TLB.scala:182:28] wire hitsVec_ignore_3 = 1'h0; // @[TLB.scala:182:34] wire _hitsVec_ignore_T_6 = 1'h0; // @[TLB.scala:182:28] wire hitsVec_ignore_6 = 1'h0; // @[TLB.scala:182:34] wire _hitsVec_ignore_T_9 = 1'h0; // @[TLB.scala:182:28] wire hitsVec_ignore_9 = 1'h0; // @[TLB.scala:182:34] wire _hitsVec_ignore_T_12 = 1'h0; // @[TLB.scala:182:28] wire hitsVec_ignore_12 = 1'h0; // @[TLB.scala:182:34] wire refill_v = 1'h0; // @[TLB.scala:448:33] wire newEntry_ae_stage2 = 1'h0; // @[TLB.scala:449:24] wire newEntry_fragmented_superpage = 1'h0; // @[TLB.scala:449:24] wire _newEntry_ae_stage2_T_1 = 1'h0; // @[TLB.scala:456:84] wire _waddr_T = 1'h0; // @[TLB.scala:477:45] wire _mxr_T = 1'h0; // @[TLB.scala:518:36] wire _cmd_lrsc_T = 1'h0; // @[package.scala:16:47] wire _cmd_lrsc_T_1 = 1'h0; // @[package.scala:16:47] wire _cmd_lrsc_T_2 = 1'h0; // @[package.scala:81:59] wire cmd_lrsc = 1'h0; // @[TLB.scala:570:33] wire _cmd_amo_logical_T = 1'h0; // @[package.scala:16:47] wire _cmd_amo_logical_T_1 = 1'h0; // @[package.scala:16:47] wire _cmd_amo_logical_T_2 = 1'h0; // @[package.scala:16:47] wire _cmd_amo_logical_T_3 = 1'h0; // @[package.scala:16:47] wire _cmd_amo_logical_T_4 = 1'h0; // @[package.scala:81:59] wire _cmd_amo_logical_T_5 = 1'h0; // @[package.scala:81:59] wire _cmd_amo_logical_T_6 = 1'h0; // @[package.scala:81:59] wire cmd_amo_logical = 1'h0; // @[TLB.scala:571:40] wire _cmd_amo_arithmetic_T = 1'h0; // @[package.scala:16:47] wire _cmd_amo_arithmetic_T_1 = 1'h0; // @[package.scala:16:47] wire _cmd_amo_arithmetic_T_2 = 1'h0; // @[package.scala:16:47] wire _cmd_amo_arithmetic_T_3 = 1'h0; // @[package.scala:16:47] wire _cmd_amo_arithmetic_T_4 = 1'h0; // @[package.scala:16:47] wire _cmd_amo_arithmetic_T_5 = 1'h0; // @[package.scala:81:59] wire _cmd_amo_arithmetic_T_6 = 1'h0; // @[package.scala:81:59] wire _cmd_amo_arithmetic_T_7 = 1'h0; // @[package.scala:81:59] wire _cmd_amo_arithmetic_T_8 = 1'h0; // @[package.scala:81:59] wire cmd_amo_arithmetic = 1'h0; // @[TLB.scala:572:43] wire cmd_put_partial = 1'h0; // @[TLB.scala:573:41] wire _cmd_read_T_1 = 1'h0; // @[package.scala:16:47] wire _cmd_read_T_2 = 1'h0; // @[package.scala:16:47] wire _cmd_read_T_3 = 1'h0; // @[package.scala:16:47] wire _cmd_read_T_7 = 1'h0; // @[package.scala:16:47] wire _cmd_read_T_8 = 1'h0; // @[package.scala:16:47] wire _cmd_read_T_9 = 1'h0; // @[package.scala:16:47] wire _cmd_read_T_10 = 1'h0; // @[package.scala:16:47] wire _cmd_read_T_11 = 1'h0; // @[package.scala:81:59] wire _cmd_read_T_12 = 1'h0; // @[package.scala:81:59] wire _cmd_read_T_13 = 1'h0; // @[package.scala:81:59] wire _cmd_read_T_14 = 1'h0; // @[package.scala:16:47] wire _cmd_read_T_15 = 1'h0; // @[package.scala:16:47] wire _cmd_read_T_16 = 1'h0; // @[package.scala:16:47] wire _cmd_read_T_17 = 1'h0; // @[package.scala:16:47] wire _cmd_read_T_18 = 1'h0; // @[package.scala:16:47] wire _cmd_read_T_19 = 1'h0; // @[package.scala:81:59] wire _cmd_read_T_20 = 1'h0; // @[package.scala:81:59] wire _cmd_read_T_21 = 1'h0; // @[package.scala:81:59] wire _cmd_read_T_22 = 1'h0; // @[package.scala:81:59] wire _cmd_read_T_23 = 1'h0; // @[Consts.scala:87:44] wire _cmd_readx_T = 1'h0; // @[TLB.scala:575:56] wire cmd_readx = 1'h0; // @[TLB.scala:575:37] wire _cmd_write_T = 1'h0; // @[Consts.scala:90:32] wire _cmd_write_T_1 = 1'h0; // @[Consts.scala:90:49] wire _cmd_write_T_2 = 1'h0; // @[Consts.scala:90:42] wire _cmd_write_T_3 = 1'h0; // @[Consts.scala:90:66] wire _cmd_write_T_4 = 1'h0; // @[Consts.scala:90:59] wire _cmd_write_T_5 = 1'h0; // @[package.scala:16:47] wire _cmd_write_T_6 = 1'h0; // @[package.scala:16:47] wire _cmd_write_T_7 = 1'h0; // @[package.scala:16:47] wire _cmd_write_T_8 = 1'h0; // @[package.scala:16:47] wire _cmd_write_T_9 = 1'h0; // @[package.scala:81:59] wire _cmd_write_T_10 = 1'h0; // @[package.scala:81:59] wire _cmd_write_T_11 = 1'h0; // @[package.scala:81:59] wire _cmd_write_T_12 = 1'h0; // @[package.scala:16:47] wire _cmd_write_T_13 = 1'h0; // @[package.scala:16:47] wire _cmd_write_T_14 = 1'h0; // @[package.scala:16:47] wire _cmd_write_T_15 = 1'h0; // @[package.scala:16:47] wire _cmd_write_T_16 = 1'h0; // @[package.scala:16:47] wire _cmd_write_T_17 = 1'h0; // @[package.scala:81:59] wire _cmd_write_T_18 = 1'h0; // @[package.scala:81:59] wire _cmd_write_T_19 = 1'h0; // @[package.scala:81:59] wire _cmd_write_T_20 = 1'h0; // @[package.scala:81:59] wire _cmd_write_T_21 = 1'h0; // @[Consts.scala:87:44] wire cmd_write = 1'h0; // @[Consts.scala:90:76] wire _cmd_write_perms_T = 1'h0; // @[package.scala:16:47] wire _cmd_write_perms_T_1 = 1'h0; // @[package.scala:16:47] wire _cmd_write_perms_T_2 = 1'h0; // @[package.scala:81:59] wire cmd_write_perms = 1'h0; // @[TLB.scala:577:35] wire _gf_ld_array_T = 1'h0; // @[TLB.scala:600:32] wire _gf_st_array_T = 1'h0; // @[TLB.scala:601:32] wire _multipleHits_T_6 = 1'h0; // @[Misc.scala:183:37] wire _multipleHits_T_15 = 1'h0; // @[Misc.scala:183:37] wire _multipleHits_T_27 = 1'h0; // @[Misc.scala:183:37] wire _multipleHits_T_35 = 1'h0; // @[Misc.scala:183:37] wire _multipleHits_T_40 = 1'h0; // @[Misc.scala:183:37] wire _io_resp_pf_st_T = 1'h0; // @[TLB.scala:634:28] wire _io_resp_pf_st_T_2 = 1'h0; // @[TLB.scala:634:72] wire _io_resp_pf_st_T_3 = 1'h0; // @[TLB.scala:634:48] wire _io_resp_gf_ld_T = 1'h0; // @[TLB.scala:637:29] wire _io_resp_gf_ld_T_2 = 1'h0; // @[TLB.scala:637:66] wire _io_resp_gf_ld_T_3 = 1'h0; // @[TLB.scala:637:42] wire _io_resp_gf_st_T = 1'h0; // @[TLB.scala:638:29] wire _io_resp_gf_st_T_2 = 1'h0; // @[TLB.scala:638:73] wire _io_resp_gf_st_T_3 = 1'h0; // @[TLB.scala:638:49] wire _io_resp_gf_inst_T_1 = 1'h0; // @[TLB.scala:639:56] wire _io_resp_gf_inst_T_2 = 1'h0; // @[TLB.scala:639:30] wire _io_resp_ae_st_T_1 = 1'h0; // @[TLB.scala:642:41] wire _io_resp_ma_st_T = 1'h0; // @[TLB.scala:646:31] wire _io_resp_must_alloc_T_1 = 1'h0; // @[TLB.scala:649:51] wire _io_resp_gpa_is_pte_T = 1'h0; // @[TLB.scala:655:36] wire hv = 1'h0; // @[TLB.scala:721:36] wire hg = 1'h0; // @[TLB.scala:722:36] wire hv_1 = 1'h0; // @[TLB.scala:721:36] wire hg_1 = 1'h0; // @[TLB.scala:722:36] wire hv_2 = 1'h0; // @[TLB.scala:721:36] wire hg_2 = 1'h0; // @[TLB.scala:722:36] wire hv_3 = 1'h0; // @[TLB.scala:721:36] wire hg_3 = 1'h0; // @[TLB.scala:722:36] wire hv_4 = 1'h0; // @[TLB.scala:721:36] wire hg_4 = 1'h0; // @[TLB.scala:722:36] wire hv_5 = 1'h0; // @[TLB.scala:721:36] wire hg_5 = 1'h0; // @[TLB.scala:722:36] wire hv_6 = 1'h0; // @[TLB.scala:721:36] wire hg_6 = 1'h0; // @[TLB.scala:722:36] wire hv_7 = 1'h0; // @[TLB.scala:721:36] wire hg_7 = 1'h0; // @[TLB.scala:722:36] wire hv_8 = 1'h0; // @[TLB.scala:721:36] wire hg_8 = 1'h0; // @[TLB.scala:722:36] wire _ignore_T = 1'h0; // @[TLB.scala:182:28] wire ignore = 1'h0; // @[TLB.scala:182:34] wire hv_9 = 1'h0; // @[TLB.scala:721:36] wire hg_9 = 1'h0; // @[TLB.scala:722:36] wire _ignore_T_3 = 1'h0; // @[TLB.scala:182:28] wire ignore_3 = 1'h0; // @[TLB.scala:182:34] wire hv_10 = 1'h0; // @[TLB.scala:721:36] wire hg_10 = 1'h0; // @[TLB.scala:722:36] wire _ignore_T_6 = 1'h0; // @[TLB.scala:182:28] wire ignore_6 = 1'h0; // @[TLB.scala:182:34] wire hv_11 = 1'h0; // @[TLB.scala:721:36] wire hg_11 = 1'h0; // @[TLB.scala:722:36] wire _ignore_T_9 = 1'h0; // @[TLB.scala:182:28] wire ignore_9 = 1'h0; // @[TLB.scala:182:34] wire hv_12 = 1'h0; // @[TLB.scala:721:36] wire hg_12 = 1'h0; // @[TLB.scala:722:36] wire _ignore_T_12 = 1'h0; // @[TLB.scala:182:28] wire ignore_12 = 1'h0; // @[TLB.scala:182:34] wire [15:0] io_ptw_ptbr_asid = 16'h0; // @[TLB.scala:318:7] wire [15:0] io_ptw_hgatp_asid = 16'h0; // @[TLB.scala:318:7] wire [15:0] io_ptw_vsatp_asid = 16'h0; // @[TLB.scala:318:7] wire [15:0] satp_asid = 16'h0; // @[TLB.scala:373:17] wire [31:0] io_ptw_status_isa = 32'h14112D; // @[TLB.scala:318:7] wire [22:0] io_ptw_status_zero2 = 23'h0; // @[TLB.scala:318:7] wire [22:0] io_ptw_gstatus_zero2 = 23'h0; // @[TLB.scala:318:7] wire [7:0] io_ptw_status_zero1 = 8'h0; // @[TLB.scala:318:7] wire [7:0] io_ptw_gstatus_zero1 = 8'h0; // @[TLB.scala:318:7] wire [1:0] io_ptw_status_xs = 2'h0; // @[TLB.scala:318:7] wire [1:0] io_ptw_status_vs = 2'h0; // @[TLB.scala:318:7] wire [1:0] io_ptw_hstatus_vsxl = 2'h0; // @[TLB.scala:318:7] wire [1:0] io_ptw_hstatus_zero3 = 2'h0; // @[TLB.scala:318:7] wire [1:0] io_ptw_hstatus_zero2 = 2'h0; // @[TLB.scala:318:7] wire [1:0] io_ptw_gstatus_dprv = 2'h0; // @[TLB.scala:318:7] wire [1:0] io_ptw_gstatus_prv = 2'h0; // @[TLB.scala:318:7] wire [1:0] io_ptw_gstatus_sxl = 2'h0; // @[TLB.scala:318:7] wire [1:0] io_ptw_gstatus_uxl = 2'h0; // @[TLB.scala:318:7] wire [1:0] io_ptw_gstatus_xs = 2'h0; // @[TLB.scala:318:7] wire [1:0] io_ptw_gstatus_fs = 2'h0; // @[TLB.scala:318:7] wire [1:0] io_ptw_gstatus_mpp = 2'h0; // @[TLB.scala:318:7] wire [1:0] io_ptw_gstatus_vs = 2'h0; // @[TLB.scala:318:7] wire [1:0] io_ptw_pmp_0_cfg_res = 2'h0; // @[TLB.scala:318:7] wire [1:0] io_ptw_pmp_1_cfg_res = 2'h0; // @[TLB.scala:318:7] wire [1:0] io_ptw_pmp_2_cfg_res = 2'h0; // @[TLB.scala:318:7] wire [1:0] io_ptw_pmp_3_cfg_res = 2'h0; // @[TLB.scala:318:7] wire [1:0] io_ptw_pmp_4_cfg_res = 2'h0; // @[TLB.scala:318:7] wire [1:0] io_ptw_pmp_5_cfg_res = 2'h0; // @[TLB.scala:318:7] wire [1:0] io_ptw_pmp_6_cfg_res = 2'h0; // @[TLB.scala:318:7] wire [1:0] io_ptw_pmp_7_cfg_res = 2'h0; // @[TLB.scala:318:7] wire [1:0] io_req_bits_size = 2'h3; // @[TLB.scala:318:7] wire [1:0] io_resp_size = 2'h3; // @[TLB.scala:318:7] wire [4:0] io_req_bits_cmd = 5'h0; // @[TLB.scala:318:7] wire [4:0] io_resp_cmd = 5'h0; // @[TLB.scala:318:7] wire [4:0] io_ptw_hstatus_zero1 = 5'h0; // @[TLB.scala:318:7] wire io_ptw_req_bits_valid = 1'h1; // @[TLB.scala:318:7] wire _vm_enabled_T_2 = 1'h1; // @[TLB.scala:399:64] wire _vsatp_mode_mismatch_T_2 = 1'h1; // @[TLB.scala:403:81] wire _homogeneous_T_59 = 1'h1; // @[TLBPermissions.scala:87:22] wire superpage_hits_ignore_2 = 1'h1; // @[TLB.scala:182:34] wire _superpage_hits_T_13 = 1'h1; // @[TLB.scala:183:40] wire superpage_hits_ignore_5 = 1'h1; // @[TLB.scala:182:34] wire _superpage_hits_T_27 = 1'h1; // @[TLB.scala:183:40] wire superpage_hits_ignore_8 = 1'h1; // @[TLB.scala:182:34] wire _superpage_hits_T_41 = 1'h1; // @[TLB.scala:183:40] wire superpage_hits_ignore_11 = 1'h1; // @[TLB.scala:182:34] wire _superpage_hits_T_55 = 1'h1; // @[TLB.scala:183:40] wire hitsVec_ignore_2 = 1'h1; // @[TLB.scala:182:34] wire _hitsVec_T_61 = 1'h1; // @[TLB.scala:183:40] wire hitsVec_ignore_5 = 1'h1; // @[TLB.scala:182:34] wire _hitsVec_T_76 = 1'h1; // @[TLB.scala:183:40] wire hitsVec_ignore_8 = 1'h1; // @[TLB.scala:182:34] wire _hitsVec_T_91 = 1'h1; // @[TLB.scala:183:40] wire hitsVec_ignore_11 = 1'h1; // @[TLB.scala:182:34] wire _hitsVec_T_106 = 1'h1; // @[TLB.scala:183:40] wire ppn_ignore_1 = 1'h1; // @[TLB.scala:197:34] wire ppn_ignore_3 = 1'h1; // @[TLB.scala:197:34] wire ppn_ignore_5 = 1'h1; // @[TLB.scala:197:34] wire ppn_ignore_7 = 1'h1; // @[TLB.scala:197:34] wire _stage2_bypass_T = 1'h1; // @[TLB.scala:523:42] wire _bad_va_T_1 = 1'h1; // @[TLB.scala:560:26] wire _cmd_read_T = 1'h1; // @[package.scala:16:47] wire _cmd_read_T_4 = 1'h1; // @[package.scala:81:59] wire _cmd_read_T_5 = 1'h1; // @[package.scala:81:59] wire _cmd_read_T_6 = 1'h1; // @[package.scala:81:59] wire cmd_read = 1'h1; // @[Consts.scala:89:68] wire _gpa_hits_hit_mask_T_3 = 1'h1; // @[TLB.scala:606:107] wire _tlb_miss_T = 1'h1; // @[TLB.scala:613:32] wire _io_resp_gpa_page_T = 1'h1; // @[TLB.scala:657:20] wire _io_ptw_req_bits_valid_T = 1'h1; // @[TLB.scala:663:28] wire ignore_2 = 1'h1; // @[TLB.scala:182:34] wire ignore_5 = 1'h1; // @[TLB.scala:182:34] wire ignore_8 = 1'h1; // @[TLB.scala:182:34] wire ignore_11 = 1'h1; // @[TLB.scala:182:34] wire [3:0] io_ptw_hgatp_mode = 4'h0; // @[TLB.scala:318:7] wire [3:0] io_ptw_vsatp_mode = 4'h0; // @[TLB.scala:318:7] wire [43:0] io_ptw_hgatp_ppn = 44'h0; // @[TLB.scala:318:7] wire [43:0] io_ptw_vsatp_ppn = 44'h0; // @[TLB.scala:318:7] wire [1:0] io_ptw_status_sxl = 2'h2; // @[TLB.scala:318:7] wire [1:0] io_ptw_status_uxl = 2'h2; // @[TLB.scala:318:7] wire [29:0] io_ptw_hstatus_zero6 = 30'h0; // @[TLB.scala:318:7] wire [8:0] io_ptw_hstatus_zero5 = 9'h0; // @[TLB.scala:318:7] wire [5:0] io_ptw_hstatus_vgein = 6'h0; // @[TLB.scala:318:7] wire [31:0] io_ptw_gstatus_isa = 32'h0; // @[TLB.scala:318:7] wire [63:0] io_ptw_customCSRs_csrs_0_wdata = 64'h0; // @[TLB.scala:318:7] wire [63:0] io_ptw_customCSRs_csrs_0_value = 64'h0; // @[TLB.scala:318:7] wire [63:0] io_ptw_customCSRs_csrs_0_sdata = 64'h0; // @[TLB.scala:318:7] wire [63:0] io_ptw_customCSRs_csrs_1_wdata = 64'h0; // @[TLB.scala:318:7] wire [63:0] io_ptw_customCSRs_csrs_1_value = 64'h0; // @[TLB.scala:318:7] wire [63:0] io_ptw_customCSRs_csrs_1_sdata = 64'h0; // @[TLB.scala:318:7] wire [13:0] _ae_array_T_2 = 14'h0; // @[TLB.scala:583:8] wire [13:0] _ae_st_array_T_2 = 14'h0; // @[TLB.scala:588:8] wire [13:0] _ae_st_array_T_4 = 14'h0; // @[TLB.scala:589:8] wire [13:0] _ae_st_array_T_5 = 14'h0; // @[TLB.scala:588:53] wire [13:0] _ae_st_array_T_7 = 14'h0; // @[TLB.scala:590:8] wire [13:0] _ae_st_array_T_8 = 14'h0; // @[TLB.scala:589:53] wire [13:0] _ae_st_array_T_10 = 14'h0; // @[TLB.scala:591:8] wire [13:0] ae_st_array = 14'h0; // @[TLB.scala:590:53] wire [13:0] _must_alloc_array_T_1 = 14'h0; // @[TLB.scala:593:8] wire [13:0] _must_alloc_array_T_3 = 14'h0; // @[TLB.scala:594:8] wire [13:0] _must_alloc_array_T_4 = 14'h0; // @[TLB.scala:593:43] wire [13:0] _must_alloc_array_T_6 = 14'h0; // @[TLB.scala:595:8] wire [13:0] _must_alloc_array_T_7 = 14'h0; // @[TLB.scala:594:43] wire [13:0] _must_alloc_array_T_9 = 14'h0; // @[TLB.scala:596:8] wire [13:0] must_alloc_array = 14'h0; // @[TLB.scala:595:46] wire [13:0] pf_st_array = 14'h0; // @[TLB.scala:598:24] wire [13:0] _gf_ld_array_T_2 = 14'h0; // @[TLB.scala:600:46] wire [13:0] gf_ld_array = 14'h0; // @[TLB.scala:600:24] wire [13:0] _gf_st_array_T_1 = 14'h0; // @[TLB.scala:601:53] wire [13:0] gf_st_array = 14'h0; // @[TLB.scala:601:24] wire [13:0] _gf_inst_array_T = 14'h0; // @[TLB.scala:602:36] wire [13:0] gf_inst_array = 14'h0; // @[TLB.scala:602:26] wire [13:0] _io_resp_pf_st_T_1 = 14'h0; // @[TLB.scala:634:64] wire [13:0] _io_resp_gf_ld_T_1 = 14'h0; // @[TLB.scala:637:58] wire [13:0] _io_resp_gf_st_T_1 = 14'h0; // @[TLB.scala:638:65] wire [13:0] _io_resp_gf_inst_T = 14'h0; // @[TLB.scala:639:48] wire [13:0] _io_resp_ae_st_T = 14'h0; // @[TLB.scala:642:33] wire [13:0] _io_resp_must_alloc_T = 14'h0; // @[TLB.scala:649:43] wire [6:0] _state_vec_WIRE_0 = 7'h0; // @[Replacement.scala:305:25] wire [12:0] stage2_bypass = 13'h1FFF; // @[TLB.scala:523:27] wire [12:0] _hr_array_T_4 = 13'h1FFF; // @[TLB.scala:524:111] wire [12:0] _hw_array_T_1 = 13'h1FFF; // @[TLB.scala:525:55] wire [12:0] _hx_array_T_1 = 13'h1FFF; // @[TLB.scala:526:55] wire [12:0] _gpa_hits_hit_mask_T_4 = 13'h1FFF; // @[TLB.scala:606:88] wire [12:0] gpa_hits_hit_mask = 13'h1FFF; // @[TLB.scala:606:82] wire [12:0] _gpa_hits_T_1 = 13'h1FFF; // @[TLB.scala:607:16] wire [12:0] gpa_hits = 13'h1FFF; // @[TLB.scala:607:14] wire [12:0] _stage1_bypass_T = 13'h0; // @[TLB.scala:517:27] wire [12:0] stage1_bypass = 13'h0; // @[TLB.scala:517:61] wire [12:0] _gpa_hits_T = 13'h0; // @[TLB.scala:607:30] wire [13:0] hr_array = 14'h3FFF; // @[TLB.scala:524:21] wire [13:0] hw_array = 14'h3FFF; // @[TLB.scala:525:21] wire [13:0] hx_array = 14'h3FFF; // @[TLB.scala:526:21] wire [13:0] _must_alloc_array_T_8 = 14'h3FFF; // @[TLB.scala:596:19] wire [13:0] _gf_ld_array_T_1 = 14'h3FFF; // @[TLB.scala:600:50] wire [3:0] _misaligned_T_2 = 4'h7; // @[TLB.scala:550:69] wire [4:0] _misaligned_T_1 = 5'h7; // @[TLB.scala:550:69] wire [3:0] _misaligned_T = 4'h8; // @[OneHot.scala:58:35] wire _io_req_ready_T; // @[TLB.scala:631:25] wire _io_resp_miss_T_2; // @[TLB.scala:651:64] wire [31:0] _io_resp_paddr_T_1; // @[TLB.scala:652:23] wire [39:0] _io_resp_gpa_T; // @[TLB.scala:659:8] wire _io_resp_pf_ld_T_3; // @[TLB.scala:633:41] wire _io_resp_pf_inst_T_2; // @[TLB.scala:635:29] wire _io_resp_ae_ld_T_1; // @[TLB.scala:641:41] wire _io_resp_ae_inst_T_2; // @[TLB.scala:643:41] wire _io_resp_ma_ld_T; // @[TLB.scala:645:31] wire _io_resp_cacheable_T_1; // @[TLB.scala:648:41] wire _io_resp_prefetchable_T_2; // @[TLB.scala:650:59] wire _io_ptw_req_valid_T; // @[TLB.scala:662:29] wire do_refill = io_ptw_resp_valid_0; // @[TLB.scala:318:7, :408:29] wire newEntry_ae_ptw = io_ptw_resp_bits_ae_ptw_0; // @[TLB.scala:318:7, :449:24] wire newEntry_ae_final = io_ptw_resp_bits_ae_final_0; // @[TLB.scala:318:7, :449:24] wire newEntry_pf = io_ptw_resp_bits_pf_0; // @[TLB.scala:318:7, :449:24] wire newEntry_gf = io_ptw_resp_bits_gf_0; // @[TLB.scala:318:7, :449:24] wire newEntry_hr = io_ptw_resp_bits_hr_0; // @[TLB.scala:318:7, :449:24] wire newEntry_hw = io_ptw_resp_bits_hw_0; // @[TLB.scala:318:7, :449:24] wire newEntry_hx = io_ptw_resp_bits_hx_0; // @[TLB.scala:318:7, :449:24] wire newEntry_u = io_ptw_resp_bits_pte_u_0; // @[TLB.scala:318:7, :449:24] wire [1:0] _special_entry_level_T = io_ptw_resp_bits_level_0; // @[package.scala:163:13] wire [3:0] satp_mode = io_ptw_ptbr_mode_0; // @[TLB.scala:318:7, :373:17] wire [43:0] satp_ppn = io_ptw_ptbr_ppn_0; // @[TLB.scala:318:7, :373:17] wire mxr = io_ptw_status_mxr_0; // @[TLB.scala:318:7, :518:31] wire sum = io_ptw_status_sum_0; // @[TLB.scala:318:7, :510:16] wire io_req_ready; // @[TLB.scala:318:7] wire io_resp_pf_ld_0; // @[TLB.scala:318:7] wire io_resp_pf_inst_0; // @[TLB.scala:318:7] wire io_resp_ae_ld_0; // @[TLB.scala:318:7] wire io_resp_ae_inst_0; // @[TLB.scala:318:7] wire io_resp_ma_ld_0; // @[TLB.scala:318:7] wire io_resp_miss_0; // @[TLB.scala:318:7] wire [31:0] io_resp_paddr_0; // @[TLB.scala:318:7] wire [39:0] io_resp_gpa_0; // @[TLB.scala:318:7] wire io_resp_cacheable_0; // @[TLB.scala:318:7] wire io_resp_prefetchable_0; // @[TLB.scala:318:7] wire [26:0] io_ptw_req_bits_bits_addr_0; // @[TLB.scala:318:7] wire io_ptw_req_bits_bits_need_gpa_0; // @[TLB.scala:318:7] wire io_ptw_req_valid_0; // @[TLB.scala:318:7] wire [26:0] vpn = io_req_bits_vaddr_0[38:12]; // @[TLB.scala:318:7, :335:30] wire [26:0] _ppn_T_5 = vpn; // @[TLB.scala:198:28, :335:30] wire [26:0] _ppn_T_13 = vpn; // @[TLB.scala:198:28, :335:30] wire [26:0] _ppn_T_21 = vpn; // @[TLB.scala:198:28, :335:30] wire [26:0] _ppn_T_29 = vpn; // @[TLB.scala:198:28, :335:30] reg [1:0] sectored_entries_0_0_level; // @[TLB.scala:339:29] reg [26:0] sectored_entries_0_0_tag_vpn; // @[TLB.scala:339:29] reg sectored_entries_0_0_tag_v; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_0_data_0; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_0_data_1; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_0_data_2; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_0_data_3; // @[TLB.scala:339:29] reg sectored_entries_0_0_valid_0; // @[TLB.scala:339:29] reg sectored_entries_0_0_valid_1; // @[TLB.scala:339:29] reg sectored_entries_0_0_valid_2; // @[TLB.scala:339:29] reg sectored_entries_0_0_valid_3; // @[TLB.scala:339:29] reg [1:0] sectored_entries_0_1_level; // @[TLB.scala:339:29] reg [26:0] sectored_entries_0_1_tag_vpn; // @[TLB.scala:339:29] reg sectored_entries_0_1_tag_v; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_1_data_0; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_1_data_1; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_1_data_2; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_1_data_3; // @[TLB.scala:339:29] reg sectored_entries_0_1_valid_0; // @[TLB.scala:339:29] reg sectored_entries_0_1_valid_1; // @[TLB.scala:339:29] reg sectored_entries_0_1_valid_2; // @[TLB.scala:339:29] reg sectored_entries_0_1_valid_3; // @[TLB.scala:339:29] reg [1:0] sectored_entries_0_2_level; // @[TLB.scala:339:29] reg [26:0] sectored_entries_0_2_tag_vpn; // @[TLB.scala:339:29] reg sectored_entries_0_2_tag_v; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_2_data_0; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_2_data_1; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_2_data_2; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_2_data_3; // @[TLB.scala:339:29] reg sectored_entries_0_2_valid_0; // @[TLB.scala:339:29] reg sectored_entries_0_2_valid_1; // @[TLB.scala:339:29] reg sectored_entries_0_2_valid_2; // @[TLB.scala:339:29] reg sectored_entries_0_2_valid_3; // @[TLB.scala:339:29] reg [1:0] sectored_entries_0_3_level; // @[TLB.scala:339:29] reg [26:0] sectored_entries_0_3_tag_vpn; // @[TLB.scala:339:29] reg sectored_entries_0_3_tag_v; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_3_data_0; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_3_data_1; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_3_data_2; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_3_data_3; // @[TLB.scala:339:29] reg sectored_entries_0_3_valid_0; // @[TLB.scala:339:29] reg sectored_entries_0_3_valid_1; // @[TLB.scala:339:29] reg sectored_entries_0_3_valid_2; // @[TLB.scala:339:29] reg sectored_entries_0_3_valid_3; // @[TLB.scala:339:29] reg [1:0] sectored_entries_0_4_level; // @[TLB.scala:339:29] reg [26:0] sectored_entries_0_4_tag_vpn; // @[TLB.scala:339:29] reg sectored_entries_0_4_tag_v; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_4_data_0; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_4_data_1; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_4_data_2; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_4_data_3; // @[TLB.scala:339:29] reg sectored_entries_0_4_valid_0; // @[TLB.scala:339:29] reg sectored_entries_0_4_valid_1; // @[TLB.scala:339:29] reg sectored_entries_0_4_valid_2; // @[TLB.scala:339:29] reg sectored_entries_0_4_valid_3; // @[TLB.scala:339:29] reg [1:0] sectored_entries_0_5_level; // @[TLB.scala:339:29] reg [26:0] sectored_entries_0_5_tag_vpn; // @[TLB.scala:339:29] reg sectored_entries_0_5_tag_v; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_5_data_0; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_5_data_1; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_5_data_2; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_5_data_3; // @[TLB.scala:339:29] reg sectored_entries_0_5_valid_0; // @[TLB.scala:339:29] reg sectored_entries_0_5_valid_1; // @[TLB.scala:339:29] reg sectored_entries_0_5_valid_2; // @[TLB.scala:339:29] reg sectored_entries_0_5_valid_3; // @[TLB.scala:339:29] reg [1:0] sectored_entries_0_6_level; // @[TLB.scala:339:29] reg [26:0] sectored_entries_0_6_tag_vpn; // @[TLB.scala:339:29] reg sectored_entries_0_6_tag_v; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_6_data_0; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_6_data_1; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_6_data_2; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_6_data_3; // @[TLB.scala:339:29] reg sectored_entries_0_6_valid_0; // @[TLB.scala:339:29] reg sectored_entries_0_6_valid_1; // @[TLB.scala:339:29] reg sectored_entries_0_6_valid_2; // @[TLB.scala:339:29] reg sectored_entries_0_6_valid_3; // @[TLB.scala:339:29] reg [1:0] sectored_entries_0_7_level; // @[TLB.scala:339:29] reg [26:0] sectored_entries_0_7_tag_vpn; // @[TLB.scala:339:29] reg sectored_entries_0_7_tag_v; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_7_data_0; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_7_data_1; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_7_data_2; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_7_data_3; // @[TLB.scala:339:29] reg sectored_entries_0_7_valid_0; // @[TLB.scala:339:29] reg sectored_entries_0_7_valid_1; // @[TLB.scala:339:29] reg sectored_entries_0_7_valid_2; // @[TLB.scala:339:29] reg sectored_entries_0_7_valid_3; // @[TLB.scala:339:29] reg [1:0] superpage_entries_0_level; // @[TLB.scala:341:30] reg [26:0] superpage_entries_0_tag_vpn; // @[TLB.scala:341:30] reg superpage_entries_0_tag_v; // @[TLB.scala:341:30] reg [41:0] superpage_entries_0_data_0; // @[TLB.scala:341:30] wire [41:0] _entries_WIRE_17 = superpage_entries_0_data_0; // @[TLB.scala:170:77, :341:30] reg superpage_entries_0_valid_0; // @[TLB.scala:341:30] reg [1:0] superpage_entries_1_level; // @[TLB.scala:341:30] reg [26:0] superpage_entries_1_tag_vpn; // @[TLB.scala:341:30] reg superpage_entries_1_tag_v; // @[TLB.scala:341:30] reg [41:0] superpage_entries_1_data_0; // @[TLB.scala:341:30] wire [41:0] _entries_WIRE_19 = superpage_entries_1_data_0; // @[TLB.scala:170:77, :341:30] reg superpage_entries_1_valid_0; // @[TLB.scala:341:30] reg [1:0] superpage_entries_2_level; // @[TLB.scala:341:30] reg [26:0] superpage_entries_2_tag_vpn; // @[TLB.scala:341:30] reg superpage_entries_2_tag_v; // @[TLB.scala:341:30] reg [41:0] superpage_entries_2_data_0; // @[TLB.scala:341:30] wire [41:0] _entries_WIRE_21 = superpage_entries_2_data_0; // @[TLB.scala:170:77, :341:30] reg superpage_entries_2_valid_0; // @[TLB.scala:341:30] reg [1:0] superpage_entries_3_level; // @[TLB.scala:341:30] reg [26:0] superpage_entries_3_tag_vpn; // @[TLB.scala:341:30] reg superpage_entries_3_tag_v; // @[TLB.scala:341:30] reg [41:0] superpage_entries_3_data_0; // @[TLB.scala:341:30] wire [41:0] _entries_WIRE_23 = superpage_entries_3_data_0; // @[TLB.scala:170:77, :341:30] reg superpage_entries_3_valid_0; // @[TLB.scala:341:30] reg [1:0] special_entry_level; // @[TLB.scala:346:56] reg [26:0] special_entry_tag_vpn; // @[TLB.scala:346:56] reg special_entry_tag_v; // @[TLB.scala:346:56] reg [41:0] special_entry_data_0; // @[TLB.scala:346:56] wire [41:0] _mpu_ppn_WIRE_1 = special_entry_data_0; // @[TLB.scala:170:77, :346:56] wire [41:0] _entries_WIRE_25 = special_entry_data_0; // @[TLB.scala:170:77, :346:56] reg special_entry_valid_0; // @[TLB.scala:346:56] reg [1:0] state; // @[TLB.scala:352:22] reg [26:0] r_refill_tag; // @[TLB.scala:354:25] assign io_ptw_req_bits_bits_addr_0 = r_refill_tag; // @[TLB.scala:318:7, :354:25] reg [1:0] r_superpage_repl_addr; // @[TLB.scala:355:34] wire [1:0] waddr = r_superpage_repl_addr; // @[TLB.scala:355:34, :477:22] reg [2:0] r_sectored_repl_addr; // @[TLB.scala:356:33] reg r_sectored_hit_valid; // @[TLB.scala:357:27] reg [2:0] r_sectored_hit_bits; // @[TLB.scala:357:27] reg r_superpage_hit_valid; // @[TLB.scala:358:28] reg [1:0] r_superpage_hit_bits; // @[TLB.scala:358:28] reg r_need_gpa; // @[TLB.scala:361:23] assign io_ptw_req_bits_bits_need_gpa_0 = r_need_gpa; // @[TLB.scala:318:7, :361:23] reg r_gpa_valid; // @[TLB.scala:362:24] reg [38:0] r_gpa; // @[TLB.scala:363:18] reg [26:0] r_gpa_vpn; // @[TLB.scala:364:22] reg r_gpa_is_pte; // @[TLB.scala:365:25] wire priv_s = io_req_bits_prv_0[0]; // @[TLB.scala:318:7, :370:20] wire priv_uses_vm = ~(io_req_bits_prv_0[1]); // @[TLB.scala:318:7, :372:27] wire _stage1_en_T = satp_mode[3]; // @[TLB.scala:373:17, :374:41] wire stage1_en = _stage1_en_T; // @[TLB.scala:374:{29,41}] wire _vm_enabled_T = stage1_en; // @[TLB.scala:374:29, :399:31] wire _vm_enabled_T_1 = _vm_enabled_T & priv_uses_vm; // @[TLB.scala:372:27, :399:{31,45}] wire vm_enabled = _vm_enabled_T_1; // @[TLB.scala:399:{45,61}] wire _mpu_ppn_T = vm_enabled; // @[TLB.scala:399:61, :413:32] wire _tlb_miss_T_1 = vm_enabled; // @[TLB.scala:399:61, :613:29] wire [19:0] refill_ppn = io_ptw_resp_bits_pte_ppn_0[19:0]; // @[TLB.scala:318:7, :406:44] wire [19:0] newEntry_ppn = io_ptw_resp_bits_pte_ppn_0[19:0]; // @[TLB.scala:318:7, :406:44, :449:24] wire _mpu_priv_T = do_refill; // @[TLB.scala:408:29, :415:52] wire _io_resp_miss_T = do_refill; // @[TLB.scala:408:29, :651:29] wire _T_51 = state == 2'h1; // @[package.scala:16:47] wire _invalidate_refill_T; // @[package.scala:16:47] assign _invalidate_refill_T = _T_51; // @[package.scala:16:47] assign _io_ptw_req_valid_T = _T_51; // @[package.scala:16:47] wire _invalidate_refill_T_1 = &state; // @[package.scala:16:47] wire _invalidate_refill_T_2 = _invalidate_refill_T | _invalidate_refill_T_1; // @[package.scala:16:47, :81:59] wire invalidate_refill = _invalidate_refill_T_2 | io_sfence_valid_0; // @[package.scala:81:59] wire [19:0] _mpu_ppn_T_23; // @[TLB.scala:170:77] wire _mpu_ppn_T_22; // @[TLB.scala:170:77] wire _mpu_ppn_T_21; // @[TLB.scala:170:77] wire _mpu_ppn_T_20; // @[TLB.scala:170:77] wire _mpu_ppn_T_19; // @[TLB.scala:170:77] wire _mpu_ppn_T_18; // @[TLB.scala:170:77] wire _mpu_ppn_T_17; // @[TLB.scala:170:77] wire _mpu_ppn_T_16; // @[TLB.scala:170:77] wire _mpu_ppn_T_15; // @[TLB.scala:170:77] wire _mpu_ppn_T_14; // @[TLB.scala:170:77] wire _mpu_ppn_T_13; // @[TLB.scala:170:77] wire _mpu_ppn_T_12; // @[TLB.scala:170:77] wire _mpu_ppn_T_11; // @[TLB.scala:170:77] wire _mpu_ppn_T_10; // @[TLB.scala:170:77] wire _mpu_ppn_T_9; // @[TLB.scala:170:77] wire _mpu_ppn_T_8; // @[TLB.scala:170:77] wire _mpu_ppn_T_7; // @[TLB.scala:170:77] wire _mpu_ppn_T_6; // @[TLB.scala:170:77] wire _mpu_ppn_T_5; // @[TLB.scala:170:77] wire _mpu_ppn_T_4; // @[TLB.scala:170:77] wire _mpu_ppn_T_3; // @[TLB.scala:170:77] wire _mpu_ppn_T_2; // @[TLB.scala:170:77] wire _mpu_ppn_T_1; // @[TLB.scala:170:77] assign _mpu_ppn_T_1 = _mpu_ppn_WIRE_1[0]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_fragmented_superpage = _mpu_ppn_T_1; // @[TLB.scala:170:77] assign _mpu_ppn_T_2 = _mpu_ppn_WIRE_1[1]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_c = _mpu_ppn_T_2; // @[TLB.scala:170:77] assign _mpu_ppn_T_3 = _mpu_ppn_WIRE_1[2]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_eff = _mpu_ppn_T_3; // @[TLB.scala:170:77] assign _mpu_ppn_T_4 = _mpu_ppn_WIRE_1[3]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_paa = _mpu_ppn_T_4; // @[TLB.scala:170:77] assign _mpu_ppn_T_5 = _mpu_ppn_WIRE_1[4]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_pal = _mpu_ppn_T_5; // @[TLB.scala:170:77] assign _mpu_ppn_T_6 = _mpu_ppn_WIRE_1[5]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_ppp = _mpu_ppn_T_6; // @[TLB.scala:170:77] assign _mpu_ppn_T_7 = _mpu_ppn_WIRE_1[6]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_pr = _mpu_ppn_T_7; // @[TLB.scala:170:77] assign _mpu_ppn_T_8 = _mpu_ppn_WIRE_1[7]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_px = _mpu_ppn_T_8; // @[TLB.scala:170:77] assign _mpu_ppn_T_9 = _mpu_ppn_WIRE_1[8]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_pw = _mpu_ppn_T_9; // @[TLB.scala:170:77] assign _mpu_ppn_T_10 = _mpu_ppn_WIRE_1[9]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_hr = _mpu_ppn_T_10; // @[TLB.scala:170:77] assign _mpu_ppn_T_11 = _mpu_ppn_WIRE_1[10]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_hx = _mpu_ppn_T_11; // @[TLB.scala:170:77] assign _mpu_ppn_T_12 = _mpu_ppn_WIRE_1[11]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_hw = _mpu_ppn_T_12; // @[TLB.scala:170:77] assign _mpu_ppn_T_13 = _mpu_ppn_WIRE_1[12]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_sr = _mpu_ppn_T_13; // @[TLB.scala:170:77] assign _mpu_ppn_T_14 = _mpu_ppn_WIRE_1[13]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_sx = _mpu_ppn_T_14; // @[TLB.scala:170:77] assign _mpu_ppn_T_15 = _mpu_ppn_WIRE_1[14]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_sw = _mpu_ppn_T_15; // @[TLB.scala:170:77] assign _mpu_ppn_T_16 = _mpu_ppn_WIRE_1[15]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_gf = _mpu_ppn_T_16; // @[TLB.scala:170:77] assign _mpu_ppn_T_17 = _mpu_ppn_WIRE_1[16]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_pf = _mpu_ppn_T_17; // @[TLB.scala:170:77] assign _mpu_ppn_T_18 = _mpu_ppn_WIRE_1[17]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_ae_stage2 = _mpu_ppn_T_18; // @[TLB.scala:170:77] assign _mpu_ppn_T_19 = _mpu_ppn_WIRE_1[18]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_ae_final = _mpu_ppn_T_19; // @[TLB.scala:170:77] assign _mpu_ppn_T_20 = _mpu_ppn_WIRE_1[19]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_ae_ptw = _mpu_ppn_T_20; // @[TLB.scala:170:77] assign _mpu_ppn_T_21 = _mpu_ppn_WIRE_1[20]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_g = _mpu_ppn_T_21; // @[TLB.scala:170:77] assign _mpu_ppn_T_22 = _mpu_ppn_WIRE_1[21]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_u = _mpu_ppn_T_22; // @[TLB.scala:170:77] assign _mpu_ppn_T_23 = _mpu_ppn_WIRE_1[41:22]; // @[TLB.scala:170:77] wire [19:0] _mpu_ppn_WIRE_ppn = _mpu_ppn_T_23; // @[TLB.scala:170:77] wire [1:0] mpu_ppn_res = _mpu_ppn_barrier_io_y_ppn[19:18]; // @[package.scala:267:25] wire _GEN = special_entry_level == 2'h0; // @[TLB.scala:197:28, :346:56] wire _mpu_ppn_ignore_T; // @[TLB.scala:197:28] assign _mpu_ppn_ignore_T = _GEN; // @[TLB.scala:197:28] wire _hitsVec_ignore_T_13; // @[TLB.scala:182:28] assign _hitsVec_ignore_T_13 = _GEN; // @[TLB.scala:182:28, :197:28] wire _ppn_ignore_T_8; // @[TLB.scala:197:28] assign _ppn_ignore_T_8 = _GEN; // @[TLB.scala:197:28] wire _ignore_T_13; // @[TLB.scala:182:28] assign _ignore_T_13 = _GEN; // @[TLB.scala:182:28, :197:28] wire mpu_ppn_ignore = _mpu_ppn_ignore_T; // @[TLB.scala:197:{28,34}] wire [26:0] _mpu_ppn_T_24 = mpu_ppn_ignore ? vpn : 27'h0; // @[TLB.scala:197:34, :198:28, :335:30] wire [26:0] _mpu_ppn_T_25 = {_mpu_ppn_T_24[26:20], _mpu_ppn_T_24[19:0] | _mpu_ppn_barrier_io_y_ppn}; // @[package.scala:267:25] wire [8:0] _mpu_ppn_T_26 = _mpu_ppn_T_25[17:9]; // @[TLB.scala:198:{47,58}] wire [10:0] _mpu_ppn_T_27 = {mpu_ppn_res, _mpu_ppn_T_26}; // @[TLB.scala:195:26, :198:{18,58}] wire _mpu_ppn_ignore_T_1 = ~(special_entry_level[1]); // @[TLB.scala:197:28, :346:56] wire mpu_ppn_ignore_1 = _mpu_ppn_ignore_T_1; // @[TLB.scala:197:{28,34}] wire [26:0] _mpu_ppn_T_28 = mpu_ppn_ignore_1 ? vpn : 27'h0; // @[TLB.scala:197:34, :198:28, :335:30] wire [26:0] _mpu_ppn_T_29 = {_mpu_ppn_T_28[26:20], _mpu_ppn_T_28[19:0] | _mpu_ppn_barrier_io_y_ppn}; // @[package.scala:267:25] wire [8:0] _mpu_ppn_T_30 = _mpu_ppn_T_29[8:0]; // @[TLB.scala:198:{47,58}] wire [19:0] _mpu_ppn_T_31 = {_mpu_ppn_T_27, _mpu_ppn_T_30}; // @[TLB.scala:198:{18,58}] wire [27:0] _mpu_ppn_T_32 = io_req_bits_vaddr_0[39:12]; // @[TLB.scala:318:7, :413:146] wire [27:0] _mpu_ppn_T_33 = _mpu_ppn_T ? {8'h0, _mpu_ppn_T_31} : _mpu_ppn_T_32; // @[TLB.scala:198:18, :413:{20,32,146}] wire [27:0] mpu_ppn = do_refill ? {8'h0, refill_ppn} : _mpu_ppn_T_33; // @[TLB.scala:406:44, :408:29, :412:20, :413:20] wire [11:0] _mpu_physaddr_T = io_req_bits_vaddr_0[11:0]; // @[TLB.scala:318:7, :414:52] wire [11:0] _io_resp_paddr_T = io_req_bits_vaddr_0[11:0]; // @[TLB.scala:318:7, :414:52, :652:46] wire [11:0] _io_resp_gpa_offset_T_1 = io_req_bits_vaddr_0[11:0]; // @[TLB.scala:318:7, :414:52, :658:82] wire [39:0] mpu_physaddr = {mpu_ppn, _mpu_physaddr_T}; // @[TLB.scala:412:20, :414:{25,52}] wire [39:0] _homogeneous_T = mpu_physaddr; // @[TLB.scala:414:25] wire [39:0] _homogeneous_T_67 = mpu_physaddr; // @[TLB.scala:414:25] wire [39:0] _deny_access_to_debug_T_1 = mpu_physaddr; // @[TLB.scala:414:25] wire _mpu_priv_T_1 = _mpu_priv_T; // @[TLB.scala:415:{38,52}] wire [2:0] _mpu_priv_T_2 = {io_ptw_status_debug_0, io_req_bits_prv_0}; // @[TLB.scala:318:7, :415:103] wire [2:0] mpu_priv = _mpu_priv_T_1 ? 3'h1 : _mpu_priv_T_2; // @[TLB.scala:415:{27,38,103}] wire cacheable; // @[TLB.scala:425:41] wire newEntry_c = cacheable; // @[TLB.scala:425:41, :449:24] wire [40:0] _homogeneous_T_1 = {1'h0, _homogeneous_T}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_2 = _homogeneous_T_1 & 41'h1FFFFFFE000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_3 = _homogeneous_T_2; // @[Parameters.scala:137:46] wire _homogeneous_T_4 = _homogeneous_T_3 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _homogeneous_T_50 = _homogeneous_T_4; // @[TLBPermissions.scala:101:65] wire [39:0] _GEN_0 = {mpu_physaddr[39:14], mpu_physaddr[13:0] ^ 14'h3000}; // @[TLB.scala:414:25] wire [39:0] _homogeneous_T_5; // @[Parameters.scala:137:31] assign _homogeneous_T_5 = _GEN_0; // @[Parameters.scala:137:31] wire [39:0] _homogeneous_T_72; // @[Parameters.scala:137:31] assign _homogeneous_T_72 = _GEN_0; // @[Parameters.scala:137:31] wire [40:0] _homogeneous_T_6 = {1'h0, _homogeneous_T_5}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_7 = _homogeneous_T_6 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_8 = _homogeneous_T_7; // @[Parameters.scala:137:46] wire _homogeneous_T_9 = _homogeneous_T_8 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] _GEN_1 = {mpu_physaddr[39:17], mpu_physaddr[16:0] ^ 17'h10000}; // @[TLB.scala:414:25] wire [39:0] _homogeneous_T_10; // @[Parameters.scala:137:31] assign _homogeneous_T_10 = _GEN_1; // @[Parameters.scala:137:31] wire [39:0] _homogeneous_T_60; // @[Parameters.scala:137:31] assign _homogeneous_T_60 = _GEN_1; // @[Parameters.scala:137:31] wire [39:0] _homogeneous_T_77; // @[Parameters.scala:137:31] assign _homogeneous_T_77 = _GEN_1; // @[Parameters.scala:137:31] wire [39:0] _homogeneous_T_109; // @[Parameters.scala:137:31] assign _homogeneous_T_109 = _GEN_1; // @[Parameters.scala:137:31] wire [39:0] _homogeneous_T_116; // @[Parameters.scala:137:31] assign _homogeneous_T_116 = _GEN_1; // @[Parameters.scala:137:31] wire [40:0] _homogeneous_T_11 = {1'h0, _homogeneous_T_10}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_12 = _homogeneous_T_11 & 41'h1FFFFFF0000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_13 = _homogeneous_T_12; // @[Parameters.scala:137:46] wire _homogeneous_T_14 = _homogeneous_T_13 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] _homogeneous_T_15 = {mpu_physaddr[39:21], mpu_physaddr[20:0] ^ 21'h100000}; // @[TLB.scala:414:25] wire [40:0] _homogeneous_T_16 = {1'h0, _homogeneous_T_15}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_17 = _homogeneous_T_16 & 41'h1FFFFFEF000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_18 = _homogeneous_T_17; // @[Parameters.scala:137:46] wire _homogeneous_T_19 = _homogeneous_T_18 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] _homogeneous_T_20 = {mpu_physaddr[39:26], mpu_physaddr[25:0] ^ 26'h2000000}; // @[TLB.scala:414:25] wire [40:0] _homogeneous_T_21 = {1'h0, _homogeneous_T_20}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_22 = _homogeneous_T_21 & 41'h1FFFFFF0000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_23 = _homogeneous_T_22; // @[Parameters.scala:137:46] wire _homogeneous_T_24 = _homogeneous_T_23 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] _homogeneous_T_25 = {mpu_physaddr[39:26], mpu_physaddr[25:0] ^ 26'h2010000}; // @[TLB.scala:414:25] wire [40:0] _homogeneous_T_26 = {1'h0, _homogeneous_T_25}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_27 = _homogeneous_T_26 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_28 = _homogeneous_T_27; // @[Parameters.scala:137:46] wire _homogeneous_T_29 = _homogeneous_T_28 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] _GEN_2 = {mpu_physaddr[39:28], mpu_physaddr[27:0] ^ 28'h8000000}; // @[TLB.scala:414:25] wire [39:0] _homogeneous_T_30; // @[Parameters.scala:137:31] assign _homogeneous_T_30 = _GEN_2; // @[Parameters.scala:137:31] wire [39:0] _homogeneous_T_82; // @[Parameters.scala:137:31] assign _homogeneous_T_82 = _GEN_2; // @[Parameters.scala:137:31] wire [39:0] _homogeneous_T_97; // @[Parameters.scala:137:31] assign _homogeneous_T_97 = _GEN_2; // @[Parameters.scala:137:31] wire [40:0] _homogeneous_T_31 = {1'h0, _homogeneous_T_30}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_32 = _homogeneous_T_31 & 41'h1FFFFFF0000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_33 = _homogeneous_T_32; // @[Parameters.scala:137:46] wire _homogeneous_T_34 = _homogeneous_T_33 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] _homogeneous_T_35 = {mpu_physaddr[39:28], mpu_physaddr[27:0] ^ 28'hC000000}; // @[TLB.scala:414:25] wire [40:0] _homogeneous_T_36 = {1'h0, _homogeneous_T_35}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_37 = _homogeneous_T_36 & 41'h1FFFC000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_38 = _homogeneous_T_37; // @[Parameters.scala:137:46] wire _homogeneous_T_39 = _homogeneous_T_38 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] _homogeneous_T_40 = {mpu_physaddr[39:29], mpu_physaddr[28:0] ^ 29'h10020000}; // @[TLB.scala:414:25] wire [40:0] _homogeneous_T_41 = {1'h0, _homogeneous_T_40}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_42 = _homogeneous_T_41 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_43 = _homogeneous_T_42; // @[Parameters.scala:137:46] wire _homogeneous_T_44 = _homogeneous_T_43 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] _GEN_3 = {mpu_physaddr[39:32], mpu_physaddr[31:0] ^ 32'h80000000}; // @[TLB.scala:414:25, :417:15] wire [39:0] _homogeneous_T_45; // @[Parameters.scala:137:31] assign _homogeneous_T_45 = _GEN_3; // @[Parameters.scala:137:31] wire [39:0] _homogeneous_T_87; // @[Parameters.scala:137:31] assign _homogeneous_T_87 = _GEN_3; // @[Parameters.scala:137:31] wire [39:0] _homogeneous_T_102; // @[Parameters.scala:137:31] assign _homogeneous_T_102 = _GEN_3; // @[Parameters.scala:137:31] wire [40:0] _homogeneous_T_46 = {1'h0, _homogeneous_T_45}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_47 = _homogeneous_T_46 & 41'h1FFF0000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_48 = _homogeneous_T_47; // @[Parameters.scala:137:46] wire _homogeneous_T_49 = _homogeneous_T_48 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _homogeneous_T_51 = _homogeneous_T_50 | _homogeneous_T_9; // @[TLBPermissions.scala:101:65] wire _homogeneous_T_52 = _homogeneous_T_51 | _homogeneous_T_14; // @[TLBPermissions.scala:101:65] wire _homogeneous_T_53 = _homogeneous_T_52 | _homogeneous_T_19; // @[TLBPermissions.scala:101:65] wire _homogeneous_T_54 = _homogeneous_T_53 | _homogeneous_T_24; // @[TLBPermissions.scala:101:65] wire _homogeneous_T_55 = _homogeneous_T_54 | _homogeneous_T_29; // @[TLBPermissions.scala:101:65] wire _homogeneous_T_56 = _homogeneous_T_55 | _homogeneous_T_34; // @[TLBPermissions.scala:101:65] wire _homogeneous_T_57 = _homogeneous_T_56 | _homogeneous_T_39; // @[TLBPermissions.scala:101:65] wire _homogeneous_T_58 = _homogeneous_T_57 | _homogeneous_T_44; // @[TLBPermissions.scala:101:65] wire homogeneous = _homogeneous_T_58 | _homogeneous_T_49; // @[TLBPermissions.scala:101:65] wire [40:0] _homogeneous_T_61 = {1'h0, _homogeneous_T_60}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_62 = _homogeneous_T_61 & 41'h8A110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_63 = _homogeneous_T_62; // @[Parameters.scala:137:46] wire _homogeneous_T_64 = _homogeneous_T_63 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _homogeneous_T_65 = _homogeneous_T_64; // @[TLBPermissions.scala:87:66] wire _homogeneous_T_66 = ~_homogeneous_T_65; // @[TLBPermissions.scala:87:{22,66}] wire [40:0] _homogeneous_T_68 = {1'h0, _homogeneous_T_67}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_69 = _homogeneous_T_68 & 41'h9E113000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_70 = _homogeneous_T_69; // @[Parameters.scala:137:46] wire _homogeneous_T_71 = _homogeneous_T_70 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _homogeneous_T_92 = _homogeneous_T_71; // @[TLBPermissions.scala:85:66] wire [40:0] _homogeneous_T_73 = {1'h0, _homogeneous_T_72}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_74 = _homogeneous_T_73 & 41'h9E113000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_75 = _homogeneous_T_74; // @[Parameters.scala:137:46] wire _homogeneous_T_76 = _homogeneous_T_75 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _homogeneous_T_78 = {1'h0, _homogeneous_T_77}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_79 = _homogeneous_T_78 & 41'h9E110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_80 = _homogeneous_T_79; // @[Parameters.scala:137:46] wire _homogeneous_T_81 = _homogeneous_T_80 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _homogeneous_T_83 = {1'h0, _homogeneous_T_82}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_84 = _homogeneous_T_83 & 41'h9E110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_85 = _homogeneous_T_84; // @[Parameters.scala:137:46] wire _homogeneous_T_86 = _homogeneous_T_85 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _homogeneous_T_88 = {1'h0, _homogeneous_T_87}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_89 = _homogeneous_T_88 & 41'h90000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_90 = _homogeneous_T_89; // @[Parameters.scala:137:46] wire _homogeneous_T_91 = _homogeneous_T_90 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _homogeneous_T_93 = _homogeneous_T_92 | _homogeneous_T_76; // @[TLBPermissions.scala:85:66] wire _homogeneous_T_94 = _homogeneous_T_93 | _homogeneous_T_81; // @[TLBPermissions.scala:85:66] wire _homogeneous_T_95 = _homogeneous_T_94 | _homogeneous_T_86; // @[TLBPermissions.scala:85:66] wire _homogeneous_T_96 = _homogeneous_T_95 | _homogeneous_T_91; // @[TLBPermissions.scala:85:66] wire [40:0] _homogeneous_T_98 = {1'h0, _homogeneous_T_97}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_99 = _homogeneous_T_98 & 41'h8E000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_100 = _homogeneous_T_99; // @[Parameters.scala:137:46] wire _homogeneous_T_101 = _homogeneous_T_100 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _homogeneous_T_107 = _homogeneous_T_101; // @[TLBPermissions.scala:85:66] wire [40:0] _homogeneous_T_103 = {1'h0, _homogeneous_T_102}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_104 = _homogeneous_T_103 & 41'h80000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_105 = _homogeneous_T_104; // @[Parameters.scala:137:46] wire _homogeneous_T_106 = _homogeneous_T_105 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _homogeneous_T_108 = _homogeneous_T_107 | _homogeneous_T_106; // @[TLBPermissions.scala:85:66] wire [40:0] _homogeneous_T_110 = {1'h0, _homogeneous_T_109}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_111 = _homogeneous_T_110 & 41'h8A110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_112 = _homogeneous_T_111; // @[Parameters.scala:137:46] wire _homogeneous_T_113 = _homogeneous_T_112 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _homogeneous_T_114 = _homogeneous_T_113; // @[TLBPermissions.scala:87:66] wire _homogeneous_T_115 = ~_homogeneous_T_114; // @[TLBPermissions.scala:87:{22,66}] wire [40:0] _homogeneous_T_117 = {1'h0, _homogeneous_T_116}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_118 = _homogeneous_T_117 & 41'h8A110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_119 = _homogeneous_T_118; // @[Parameters.scala:137:46] wire _homogeneous_T_120 = _homogeneous_T_119 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _homogeneous_T_121 = _homogeneous_T_120; // @[TLBPermissions.scala:87:66] wire _homogeneous_T_122 = ~_homogeneous_T_121; // @[TLBPermissions.scala:87:{22,66}] wire _deny_access_to_debug_T = ~(mpu_priv[2]); // @[TLB.scala:415:27, :428:39] wire [40:0] _deny_access_to_debug_T_2 = {1'h0, _deny_access_to_debug_T_1}; // @[Parameters.scala:137:{31,41}] wire [40:0] _deny_access_to_debug_T_3 = _deny_access_to_debug_T_2 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}] wire [40:0] _deny_access_to_debug_T_4 = _deny_access_to_debug_T_3; // @[Parameters.scala:137:46] wire _deny_access_to_debug_T_5 = _deny_access_to_debug_T_4 == 41'h0; // @[Parameters.scala:137:{46,59}] wire deny_access_to_debug = _deny_access_to_debug_T & _deny_access_to_debug_T_5; // @[TLB.scala:428:{39,50}] wire _prot_r_T = ~deny_access_to_debug; // @[TLB.scala:428:50, :429:33] wire _prot_r_T_1 = _pma_io_resp_r & _prot_r_T; // @[TLB.scala:422:19, :429:{30,33}] wire prot_r = _prot_r_T_1 & _pmp_io_r; // @[TLB.scala:416:19, :429:{30,55}] wire newEntry_pr = prot_r; // @[TLB.scala:429:55, :449:24] wire _prot_w_T = ~deny_access_to_debug; // @[TLB.scala:428:50, :429:33, :430:33] wire _prot_w_T_1 = _pma_io_resp_w & _prot_w_T; // @[TLB.scala:422:19, :430:{30,33}] wire prot_w = _prot_w_T_1 & _pmp_io_w; // @[TLB.scala:416:19, :430:{30,55}] wire newEntry_pw = prot_w; // @[TLB.scala:430:55, :449:24] wire _prot_x_T = ~deny_access_to_debug; // @[TLB.scala:428:50, :429:33, :434:33] wire _prot_x_T_1 = _pma_io_resp_x & _prot_x_T; // @[TLB.scala:422:19, :434:{30,33}] wire prot_x = _prot_x_T_1 & _pmp_io_x; // @[TLB.scala:416:19, :434:{30,55}] wire newEntry_px = prot_x; // @[TLB.scala:434:55, :449:24] wire _GEN_4 = sectored_entries_0_0_valid_0 | sectored_entries_0_0_valid_1; // @[package.scala:81:59] wire _sector_hits_T; // @[package.scala:81:59] assign _sector_hits_T = _GEN_4; // @[package.scala:81:59] wire _r_sectored_repl_addr_valids_T; // @[package.scala:81:59] assign _r_sectored_repl_addr_valids_T = _GEN_4; // @[package.scala:81:59] wire _sector_hits_T_1 = _sector_hits_T | sectored_entries_0_0_valid_2; // @[package.scala:81:59] wire _sector_hits_T_2 = _sector_hits_T_1 | sectored_entries_0_0_valid_3; // @[package.scala:81:59] wire [26:0] _T_176 = sectored_entries_0_0_tag_vpn ^ vpn; // @[TLB.scala:174:61, :335:30, :339:29] wire [26:0] _sector_hits_T_3; // @[TLB.scala:174:61] assign _sector_hits_T_3 = _T_176; // @[TLB.scala:174:61] wire [26:0] _hitsVec_T; // @[TLB.scala:174:61] assign _hitsVec_T = _T_176; // @[TLB.scala:174:61] wire [24:0] _sector_hits_T_4 = _sector_hits_T_3[26:2]; // @[TLB.scala:174:{61,68}] wire _sector_hits_T_5 = _sector_hits_T_4 == 25'h0; // @[TLB.scala:174:{68,86}] wire _sector_hits_T_6 = ~sectored_entries_0_0_tag_v; // @[TLB.scala:174:105, :339:29] wire _sector_hits_T_7 = _sector_hits_T_5 & _sector_hits_T_6; // @[TLB.scala:174:{86,95,105}] wire sector_hits_0 = _sector_hits_T_2 & _sector_hits_T_7; // @[package.scala:81:59] wire _GEN_5 = sectored_entries_0_1_valid_0 | sectored_entries_0_1_valid_1; // @[package.scala:81:59] wire _sector_hits_T_8; // @[package.scala:81:59] assign _sector_hits_T_8 = _GEN_5; // @[package.scala:81:59] wire _r_sectored_repl_addr_valids_T_3; // @[package.scala:81:59] assign _r_sectored_repl_addr_valids_T_3 = _GEN_5; // @[package.scala:81:59] wire _sector_hits_T_9 = _sector_hits_T_8 | sectored_entries_0_1_valid_2; // @[package.scala:81:59] wire _sector_hits_T_10 = _sector_hits_T_9 | sectored_entries_0_1_valid_3; // @[package.scala:81:59] wire [26:0] _T_597 = sectored_entries_0_1_tag_vpn ^ vpn; // @[TLB.scala:174:61, :335:30, :339:29] wire [26:0] _sector_hits_T_11; // @[TLB.scala:174:61] assign _sector_hits_T_11 = _T_597; // @[TLB.scala:174:61] wire [26:0] _hitsVec_T_6; // @[TLB.scala:174:61] assign _hitsVec_T_6 = _T_597; // @[TLB.scala:174:61] wire [24:0] _sector_hits_T_12 = _sector_hits_T_11[26:2]; // @[TLB.scala:174:{61,68}] wire _sector_hits_T_13 = _sector_hits_T_12 == 25'h0; // @[TLB.scala:174:{68,86}] wire _sector_hits_T_14 = ~sectored_entries_0_1_tag_v; // @[TLB.scala:174:105, :339:29] wire _sector_hits_T_15 = _sector_hits_T_13 & _sector_hits_T_14; // @[TLB.scala:174:{86,95,105}] wire sector_hits_1 = _sector_hits_T_10 & _sector_hits_T_15; // @[package.scala:81:59] wire _GEN_6 = sectored_entries_0_2_valid_0 | sectored_entries_0_2_valid_1; // @[package.scala:81:59] wire _sector_hits_T_16; // @[package.scala:81:59] assign _sector_hits_T_16 = _GEN_6; // @[package.scala:81:59] wire _r_sectored_repl_addr_valids_T_6; // @[package.scala:81:59] assign _r_sectored_repl_addr_valids_T_6 = _GEN_6; // @[package.scala:81:59] wire _sector_hits_T_17 = _sector_hits_T_16 | sectored_entries_0_2_valid_2; // @[package.scala:81:59] wire _sector_hits_T_18 = _sector_hits_T_17 | sectored_entries_0_2_valid_3; // @[package.scala:81:59] wire [26:0] _T_1018 = sectored_entries_0_2_tag_vpn ^ vpn; // @[TLB.scala:174:61, :335:30, :339:29] wire [26:0] _sector_hits_T_19; // @[TLB.scala:174:61] assign _sector_hits_T_19 = _T_1018; // @[TLB.scala:174:61] wire [26:0] _hitsVec_T_12; // @[TLB.scala:174:61] assign _hitsVec_T_12 = _T_1018; // @[TLB.scala:174:61] wire [24:0] _sector_hits_T_20 = _sector_hits_T_19[26:2]; // @[TLB.scala:174:{61,68}] wire _sector_hits_T_21 = _sector_hits_T_20 == 25'h0; // @[TLB.scala:174:{68,86}] wire _sector_hits_T_22 = ~sectored_entries_0_2_tag_v; // @[TLB.scala:174:105, :339:29] wire _sector_hits_T_23 = _sector_hits_T_21 & _sector_hits_T_22; // @[TLB.scala:174:{86,95,105}] wire sector_hits_2 = _sector_hits_T_18 & _sector_hits_T_23; // @[package.scala:81:59] wire _GEN_7 = sectored_entries_0_3_valid_0 | sectored_entries_0_3_valid_1; // @[package.scala:81:59] wire _sector_hits_T_24; // @[package.scala:81:59] assign _sector_hits_T_24 = _GEN_7; // @[package.scala:81:59] wire _r_sectored_repl_addr_valids_T_9; // @[package.scala:81:59] assign _r_sectored_repl_addr_valids_T_9 = _GEN_7; // @[package.scala:81:59] wire _sector_hits_T_25 = _sector_hits_T_24 | sectored_entries_0_3_valid_2; // @[package.scala:81:59] wire _sector_hits_T_26 = _sector_hits_T_25 | sectored_entries_0_3_valid_3; // @[package.scala:81:59] wire [26:0] _T_1439 = sectored_entries_0_3_tag_vpn ^ vpn; // @[TLB.scala:174:61, :335:30, :339:29] wire [26:0] _sector_hits_T_27; // @[TLB.scala:174:61] assign _sector_hits_T_27 = _T_1439; // @[TLB.scala:174:61] wire [26:0] _hitsVec_T_18; // @[TLB.scala:174:61] assign _hitsVec_T_18 = _T_1439; // @[TLB.scala:174:61] wire [24:0] _sector_hits_T_28 = _sector_hits_T_27[26:2]; // @[TLB.scala:174:{61,68}] wire _sector_hits_T_29 = _sector_hits_T_28 == 25'h0; // @[TLB.scala:174:{68,86}] wire _sector_hits_T_30 = ~sectored_entries_0_3_tag_v; // @[TLB.scala:174:105, :339:29] wire _sector_hits_T_31 = _sector_hits_T_29 & _sector_hits_T_30; // @[TLB.scala:174:{86,95,105}] wire sector_hits_3 = _sector_hits_T_26 & _sector_hits_T_31; // @[package.scala:81:59] wire _GEN_8 = sectored_entries_0_4_valid_0 | sectored_entries_0_4_valid_1; // @[package.scala:81:59] wire _sector_hits_T_32; // @[package.scala:81:59] assign _sector_hits_T_32 = _GEN_8; // @[package.scala:81:59] wire _r_sectored_repl_addr_valids_T_12; // @[package.scala:81:59] assign _r_sectored_repl_addr_valids_T_12 = _GEN_8; // @[package.scala:81:59] wire _sector_hits_T_33 = _sector_hits_T_32 | sectored_entries_0_4_valid_2; // @[package.scala:81:59] wire _sector_hits_T_34 = _sector_hits_T_33 | sectored_entries_0_4_valid_3; // @[package.scala:81:59] wire [26:0] _T_1860 = sectored_entries_0_4_tag_vpn ^ vpn; // @[TLB.scala:174:61, :335:30, :339:29] wire [26:0] _sector_hits_T_35; // @[TLB.scala:174:61] assign _sector_hits_T_35 = _T_1860; // @[TLB.scala:174:61] wire [26:0] _hitsVec_T_24; // @[TLB.scala:174:61] assign _hitsVec_T_24 = _T_1860; // @[TLB.scala:174:61] wire [24:0] _sector_hits_T_36 = _sector_hits_T_35[26:2]; // @[TLB.scala:174:{61,68}] wire _sector_hits_T_37 = _sector_hits_T_36 == 25'h0; // @[TLB.scala:174:{68,86}] wire _sector_hits_T_38 = ~sectored_entries_0_4_tag_v; // @[TLB.scala:174:105, :339:29] wire _sector_hits_T_39 = _sector_hits_T_37 & _sector_hits_T_38; // @[TLB.scala:174:{86,95,105}] wire sector_hits_4 = _sector_hits_T_34 & _sector_hits_T_39; // @[package.scala:81:59] wire _GEN_9 = sectored_entries_0_5_valid_0 | sectored_entries_0_5_valid_1; // @[package.scala:81:59] wire _sector_hits_T_40; // @[package.scala:81:59] assign _sector_hits_T_40 = _GEN_9; // @[package.scala:81:59] wire _r_sectored_repl_addr_valids_T_15; // @[package.scala:81:59] assign _r_sectored_repl_addr_valids_T_15 = _GEN_9; // @[package.scala:81:59] wire _sector_hits_T_41 = _sector_hits_T_40 | sectored_entries_0_5_valid_2; // @[package.scala:81:59] wire _sector_hits_T_42 = _sector_hits_T_41 | sectored_entries_0_5_valid_3; // @[package.scala:81:59] wire [26:0] _T_2281 = sectored_entries_0_5_tag_vpn ^ vpn; // @[TLB.scala:174:61, :335:30, :339:29] wire [26:0] _sector_hits_T_43; // @[TLB.scala:174:61] assign _sector_hits_T_43 = _T_2281; // @[TLB.scala:174:61] wire [26:0] _hitsVec_T_30; // @[TLB.scala:174:61] assign _hitsVec_T_30 = _T_2281; // @[TLB.scala:174:61] wire [24:0] _sector_hits_T_44 = _sector_hits_T_43[26:2]; // @[TLB.scala:174:{61,68}] wire _sector_hits_T_45 = _sector_hits_T_44 == 25'h0; // @[TLB.scala:174:{68,86}] wire _sector_hits_T_46 = ~sectored_entries_0_5_tag_v; // @[TLB.scala:174:105, :339:29] wire _sector_hits_T_47 = _sector_hits_T_45 & _sector_hits_T_46; // @[TLB.scala:174:{86,95,105}] wire sector_hits_5 = _sector_hits_T_42 & _sector_hits_T_47; // @[package.scala:81:59] wire _GEN_10 = sectored_entries_0_6_valid_0 | sectored_entries_0_6_valid_1; // @[package.scala:81:59] wire _sector_hits_T_48; // @[package.scala:81:59] assign _sector_hits_T_48 = _GEN_10; // @[package.scala:81:59] wire _r_sectored_repl_addr_valids_T_18; // @[package.scala:81:59] assign _r_sectored_repl_addr_valids_T_18 = _GEN_10; // @[package.scala:81:59] wire _sector_hits_T_49 = _sector_hits_T_48 | sectored_entries_0_6_valid_2; // @[package.scala:81:59] wire _sector_hits_T_50 = _sector_hits_T_49 | sectored_entries_0_6_valid_3; // @[package.scala:81:59] wire [26:0] _T_2702 = sectored_entries_0_6_tag_vpn ^ vpn; // @[TLB.scala:174:61, :335:30, :339:29] wire [26:0] _sector_hits_T_51; // @[TLB.scala:174:61] assign _sector_hits_T_51 = _T_2702; // @[TLB.scala:174:61] wire [26:0] _hitsVec_T_36; // @[TLB.scala:174:61] assign _hitsVec_T_36 = _T_2702; // @[TLB.scala:174:61] wire [24:0] _sector_hits_T_52 = _sector_hits_T_51[26:2]; // @[TLB.scala:174:{61,68}] wire _sector_hits_T_53 = _sector_hits_T_52 == 25'h0; // @[TLB.scala:174:{68,86}] wire _sector_hits_T_54 = ~sectored_entries_0_6_tag_v; // @[TLB.scala:174:105, :339:29] wire _sector_hits_T_55 = _sector_hits_T_53 & _sector_hits_T_54; // @[TLB.scala:174:{86,95,105}] wire sector_hits_6 = _sector_hits_T_50 & _sector_hits_T_55; // @[package.scala:81:59] wire _GEN_11 = sectored_entries_0_7_valid_0 | sectored_entries_0_7_valid_1; // @[package.scala:81:59] wire _sector_hits_T_56; // @[package.scala:81:59] assign _sector_hits_T_56 = _GEN_11; // @[package.scala:81:59] wire _r_sectored_repl_addr_valids_T_21; // @[package.scala:81:59] assign _r_sectored_repl_addr_valids_T_21 = _GEN_11; // @[package.scala:81:59] wire _sector_hits_T_57 = _sector_hits_T_56 | sectored_entries_0_7_valid_2; // @[package.scala:81:59] wire _sector_hits_T_58 = _sector_hits_T_57 | sectored_entries_0_7_valid_3; // @[package.scala:81:59] wire [26:0] _T_3123 = sectored_entries_0_7_tag_vpn ^ vpn; // @[TLB.scala:174:61, :335:30, :339:29] wire [26:0] _sector_hits_T_59; // @[TLB.scala:174:61] assign _sector_hits_T_59 = _T_3123; // @[TLB.scala:174:61] wire [26:0] _hitsVec_T_42; // @[TLB.scala:174:61] assign _hitsVec_T_42 = _T_3123; // @[TLB.scala:174:61] wire [24:0] _sector_hits_T_60 = _sector_hits_T_59[26:2]; // @[TLB.scala:174:{61,68}] wire _sector_hits_T_61 = _sector_hits_T_60 == 25'h0; // @[TLB.scala:174:{68,86}] wire _sector_hits_T_62 = ~sectored_entries_0_7_tag_v; // @[TLB.scala:174:105, :339:29] wire _sector_hits_T_63 = _sector_hits_T_61 & _sector_hits_T_62; // @[TLB.scala:174:{86,95,105}] wire sector_hits_7 = _sector_hits_T_58 & _sector_hits_T_63; // @[package.scala:81:59] wire _superpage_hits_tagMatch_T = ~superpage_entries_0_tag_v; // @[TLB.scala:178:43, :341:30] wire superpage_hits_tagMatch = superpage_entries_0_valid_0 & _superpage_hits_tagMatch_T; // @[TLB.scala:178:{33,43}, :341:30] wire [26:0] _T_3446 = superpage_entries_0_tag_vpn ^ vpn; // @[TLB.scala:183:52, :335:30, :341:30] wire [26:0] _superpage_hits_T; // @[TLB.scala:183:52] assign _superpage_hits_T = _T_3446; // @[TLB.scala:183:52] wire [26:0] _superpage_hits_T_5; // @[TLB.scala:183:52] assign _superpage_hits_T_5 = _T_3446; // @[TLB.scala:183:52] wire [26:0] _superpage_hits_T_10; // @[TLB.scala:183:52] assign _superpage_hits_T_10 = _T_3446; // @[TLB.scala:183:52] wire [26:0] _hitsVec_T_48; // @[TLB.scala:183:52] assign _hitsVec_T_48 = _T_3446; // @[TLB.scala:183:52] wire [26:0] _hitsVec_T_53; // @[TLB.scala:183:52] assign _hitsVec_T_53 = _T_3446; // @[TLB.scala:183:52] wire [26:0] _hitsVec_T_58; // @[TLB.scala:183:52] assign _hitsVec_T_58 = _T_3446; // @[TLB.scala:183:52] wire [8:0] _superpage_hits_T_1 = _superpage_hits_T[26:18]; // @[TLB.scala:183:{52,58}] wire _superpage_hits_T_2 = _superpage_hits_T_1 == 9'h0; // @[TLB.scala:183:{58,79}] wire _superpage_hits_T_3 = _superpage_hits_T_2; // @[TLB.scala:183:{40,79}] wire _superpage_hits_T_4 = superpage_hits_tagMatch & _superpage_hits_T_3; // @[TLB.scala:178:33, :183:{29,40}] wire _GEN_12 = superpage_entries_0_level == 2'h0; // @[TLB.scala:182:28, :341:30] wire _superpage_hits_ignore_T_1; // @[TLB.scala:182:28] assign _superpage_hits_ignore_T_1 = _GEN_12; // @[TLB.scala:182:28] wire _hitsVec_ignore_T_1; // @[TLB.scala:182:28] assign _hitsVec_ignore_T_1 = _GEN_12; // @[TLB.scala:182:28] wire _ppn_ignore_T; // @[TLB.scala:197:28] assign _ppn_ignore_T = _GEN_12; // @[TLB.scala:182:28, :197:28] wire _ignore_T_1; // @[TLB.scala:182:28] assign _ignore_T_1 = _GEN_12; // @[TLB.scala:182:28] wire superpage_hits_ignore_1 = _superpage_hits_ignore_T_1; // @[TLB.scala:182:{28,34}] wire [8:0] _superpage_hits_T_6 = _superpage_hits_T_5[17:9]; // @[TLB.scala:183:{52,58}] wire _superpage_hits_T_7 = _superpage_hits_T_6 == 9'h0; // @[TLB.scala:183:{58,79}] wire _superpage_hits_T_8 = superpage_hits_ignore_1 | _superpage_hits_T_7; // @[TLB.scala:182:34, :183:{40,79}] wire _superpage_hits_T_9 = _superpage_hits_T_4 & _superpage_hits_T_8; // @[TLB.scala:183:{29,40}] wire superpage_hits_0 = _superpage_hits_T_9; // @[TLB.scala:183:29] wire _superpage_hits_ignore_T_2 = ~(superpage_entries_0_level[1]); // @[TLB.scala:182:28, :341:30] wire [8:0] _superpage_hits_T_11 = _superpage_hits_T_10[8:0]; // @[TLB.scala:183:{52,58}] wire _superpage_hits_T_12 = _superpage_hits_T_11 == 9'h0; // @[TLB.scala:183:{58,79}] wire _superpage_hits_tagMatch_T_1 = ~superpage_entries_1_tag_v; // @[TLB.scala:178:43, :341:30] wire superpage_hits_tagMatch_1 = superpage_entries_1_valid_0 & _superpage_hits_tagMatch_T_1; // @[TLB.scala:178:{33,43}, :341:30] wire [26:0] _T_3544 = superpage_entries_1_tag_vpn ^ vpn; // @[TLB.scala:183:52, :335:30, :341:30] wire [26:0] _superpage_hits_T_14; // @[TLB.scala:183:52] assign _superpage_hits_T_14 = _T_3544; // @[TLB.scala:183:52] wire [26:0] _superpage_hits_T_19; // @[TLB.scala:183:52] assign _superpage_hits_T_19 = _T_3544; // @[TLB.scala:183:52] wire [26:0] _superpage_hits_T_24; // @[TLB.scala:183:52] assign _superpage_hits_T_24 = _T_3544; // @[TLB.scala:183:52] wire [26:0] _hitsVec_T_63; // @[TLB.scala:183:52] assign _hitsVec_T_63 = _T_3544; // @[TLB.scala:183:52] wire [26:0] _hitsVec_T_68; // @[TLB.scala:183:52] assign _hitsVec_T_68 = _T_3544; // @[TLB.scala:183:52] wire [26:0] _hitsVec_T_73; // @[TLB.scala:183:52] assign _hitsVec_T_73 = _T_3544; // @[TLB.scala:183:52] wire [8:0] _superpage_hits_T_15 = _superpage_hits_T_14[26:18]; // @[TLB.scala:183:{52,58}] wire _superpage_hits_T_16 = _superpage_hits_T_15 == 9'h0; // @[TLB.scala:183:{58,79}] wire _superpage_hits_T_17 = _superpage_hits_T_16; // @[TLB.scala:183:{40,79}] wire _superpage_hits_T_18 = superpage_hits_tagMatch_1 & _superpage_hits_T_17; // @[TLB.scala:178:33, :183:{29,40}] wire _GEN_13 = superpage_entries_1_level == 2'h0; // @[TLB.scala:182:28, :341:30] wire _superpage_hits_ignore_T_4; // @[TLB.scala:182:28] assign _superpage_hits_ignore_T_4 = _GEN_13; // @[TLB.scala:182:28] wire _hitsVec_ignore_T_4; // @[TLB.scala:182:28] assign _hitsVec_ignore_T_4 = _GEN_13; // @[TLB.scala:182:28] wire _ppn_ignore_T_2; // @[TLB.scala:197:28] assign _ppn_ignore_T_2 = _GEN_13; // @[TLB.scala:182:28, :197:28] wire _ignore_T_4; // @[TLB.scala:182:28] assign _ignore_T_4 = _GEN_13; // @[TLB.scala:182:28] wire superpage_hits_ignore_4 = _superpage_hits_ignore_T_4; // @[TLB.scala:182:{28,34}] wire [8:0] _superpage_hits_T_20 = _superpage_hits_T_19[17:9]; // @[TLB.scala:183:{52,58}] wire _superpage_hits_T_21 = _superpage_hits_T_20 == 9'h0; // @[TLB.scala:183:{58,79}] wire _superpage_hits_T_22 = superpage_hits_ignore_4 | _superpage_hits_T_21; // @[TLB.scala:182:34, :183:{40,79}] wire _superpage_hits_T_23 = _superpage_hits_T_18 & _superpage_hits_T_22; // @[TLB.scala:183:{29,40}] wire superpage_hits_1 = _superpage_hits_T_23; // @[TLB.scala:183:29] wire _superpage_hits_ignore_T_5 = ~(superpage_entries_1_level[1]); // @[TLB.scala:182:28, :341:30] wire [8:0] _superpage_hits_T_25 = _superpage_hits_T_24[8:0]; // @[TLB.scala:183:{52,58}] wire _superpage_hits_T_26 = _superpage_hits_T_25 == 9'h0; // @[TLB.scala:183:{58,79}] wire _superpage_hits_tagMatch_T_2 = ~superpage_entries_2_tag_v; // @[TLB.scala:178:43, :341:30] wire superpage_hits_tagMatch_2 = superpage_entries_2_valid_0 & _superpage_hits_tagMatch_T_2; // @[TLB.scala:178:{33,43}, :341:30] wire [26:0] _T_3642 = superpage_entries_2_tag_vpn ^ vpn; // @[TLB.scala:183:52, :335:30, :341:30] wire [26:0] _superpage_hits_T_28; // @[TLB.scala:183:52] assign _superpage_hits_T_28 = _T_3642; // @[TLB.scala:183:52] wire [26:0] _superpage_hits_T_33; // @[TLB.scala:183:52] assign _superpage_hits_T_33 = _T_3642; // @[TLB.scala:183:52] wire [26:0] _superpage_hits_T_38; // @[TLB.scala:183:52] assign _superpage_hits_T_38 = _T_3642; // @[TLB.scala:183:52] wire [26:0] _hitsVec_T_78; // @[TLB.scala:183:52] assign _hitsVec_T_78 = _T_3642; // @[TLB.scala:183:52] wire [26:0] _hitsVec_T_83; // @[TLB.scala:183:52] assign _hitsVec_T_83 = _T_3642; // @[TLB.scala:183:52] wire [26:0] _hitsVec_T_88; // @[TLB.scala:183:52] assign _hitsVec_T_88 = _T_3642; // @[TLB.scala:183:52] wire [8:0] _superpage_hits_T_29 = _superpage_hits_T_28[26:18]; // @[TLB.scala:183:{52,58}] wire _superpage_hits_T_30 = _superpage_hits_T_29 == 9'h0; // @[TLB.scala:183:{58,79}] wire _superpage_hits_T_31 = _superpage_hits_T_30; // @[TLB.scala:183:{40,79}] wire _superpage_hits_T_32 = superpage_hits_tagMatch_2 & _superpage_hits_T_31; // @[TLB.scala:178:33, :183:{29,40}] wire _GEN_14 = superpage_entries_2_level == 2'h0; // @[TLB.scala:182:28, :341:30] wire _superpage_hits_ignore_T_7; // @[TLB.scala:182:28] assign _superpage_hits_ignore_T_7 = _GEN_14; // @[TLB.scala:182:28] wire _hitsVec_ignore_T_7; // @[TLB.scala:182:28] assign _hitsVec_ignore_T_7 = _GEN_14; // @[TLB.scala:182:28] wire _ppn_ignore_T_4; // @[TLB.scala:197:28] assign _ppn_ignore_T_4 = _GEN_14; // @[TLB.scala:182:28, :197:28] wire _ignore_T_7; // @[TLB.scala:182:28] assign _ignore_T_7 = _GEN_14; // @[TLB.scala:182:28] wire superpage_hits_ignore_7 = _superpage_hits_ignore_T_7; // @[TLB.scala:182:{28,34}] wire [8:0] _superpage_hits_T_34 = _superpage_hits_T_33[17:9]; // @[TLB.scala:183:{52,58}] wire _superpage_hits_T_35 = _superpage_hits_T_34 == 9'h0; // @[TLB.scala:183:{58,79}] wire _superpage_hits_T_36 = superpage_hits_ignore_7 | _superpage_hits_T_35; // @[TLB.scala:182:34, :183:{40,79}] wire _superpage_hits_T_37 = _superpage_hits_T_32 & _superpage_hits_T_36; // @[TLB.scala:183:{29,40}] wire superpage_hits_2 = _superpage_hits_T_37; // @[TLB.scala:183:29] wire _superpage_hits_ignore_T_8 = ~(superpage_entries_2_level[1]); // @[TLB.scala:182:28, :341:30] wire [8:0] _superpage_hits_T_39 = _superpage_hits_T_38[8:0]; // @[TLB.scala:183:{52,58}] wire _superpage_hits_T_40 = _superpage_hits_T_39 == 9'h0; // @[TLB.scala:183:{58,79}] wire _superpage_hits_tagMatch_T_3 = ~superpage_entries_3_tag_v; // @[TLB.scala:178:43, :341:30] wire superpage_hits_tagMatch_3 = superpage_entries_3_valid_0 & _superpage_hits_tagMatch_T_3; // @[TLB.scala:178:{33,43}, :341:30] wire [26:0] _T_3740 = superpage_entries_3_tag_vpn ^ vpn; // @[TLB.scala:183:52, :335:30, :341:30] wire [26:0] _superpage_hits_T_42; // @[TLB.scala:183:52] assign _superpage_hits_T_42 = _T_3740; // @[TLB.scala:183:52] wire [26:0] _superpage_hits_T_47; // @[TLB.scala:183:52] assign _superpage_hits_T_47 = _T_3740; // @[TLB.scala:183:52] wire [26:0] _superpage_hits_T_52; // @[TLB.scala:183:52] assign _superpage_hits_T_52 = _T_3740; // @[TLB.scala:183:52] wire [26:0] _hitsVec_T_93; // @[TLB.scala:183:52] assign _hitsVec_T_93 = _T_3740; // @[TLB.scala:183:52] wire [26:0] _hitsVec_T_98; // @[TLB.scala:183:52] assign _hitsVec_T_98 = _T_3740; // @[TLB.scala:183:52] wire [26:0] _hitsVec_T_103; // @[TLB.scala:183:52] assign _hitsVec_T_103 = _T_3740; // @[TLB.scala:183:52] wire [8:0] _superpage_hits_T_43 = _superpage_hits_T_42[26:18]; // @[TLB.scala:183:{52,58}] wire _superpage_hits_T_44 = _superpage_hits_T_43 == 9'h0; // @[TLB.scala:183:{58,79}] wire _superpage_hits_T_45 = _superpage_hits_T_44; // @[TLB.scala:183:{40,79}] wire _superpage_hits_T_46 = superpage_hits_tagMatch_3 & _superpage_hits_T_45; // @[TLB.scala:178:33, :183:{29,40}] wire _GEN_15 = superpage_entries_3_level == 2'h0; // @[TLB.scala:182:28, :341:30] wire _superpage_hits_ignore_T_10; // @[TLB.scala:182:28] assign _superpage_hits_ignore_T_10 = _GEN_15; // @[TLB.scala:182:28] wire _hitsVec_ignore_T_10; // @[TLB.scala:182:28] assign _hitsVec_ignore_T_10 = _GEN_15; // @[TLB.scala:182:28] wire _ppn_ignore_T_6; // @[TLB.scala:197:28] assign _ppn_ignore_T_6 = _GEN_15; // @[TLB.scala:182:28, :197:28] wire _ignore_T_10; // @[TLB.scala:182:28] assign _ignore_T_10 = _GEN_15; // @[TLB.scala:182:28] wire superpage_hits_ignore_10 = _superpage_hits_ignore_T_10; // @[TLB.scala:182:{28,34}] wire [8:0] _superpage_hits_T_48 = _superpage_hits_T_47[17:9]; // @[TLB.scala:183:{52,58}] wire _superpage_hits_T_49 = _superpage_hits_T_48 == 9'h0; // @[TLB.scala:183:{58,79}] wire _superpage_hits_T_50 = superpage_hits_ignore_10 | _superpage_hits_T_49; // @[TLB.scala:182:34, :183:{40,79}] wire _superpage_hits_T_51 = _superpage_hits_T_46 & _superpage_hits_T_50; // @[TLB.scala:183:{29,40}] wire superpage_hits_3 = _superpage_hits_T_51; // @[TLB.scala:183:29] wire _superpage_hits_ignore_T_11 = ~(superpage_entries_3_level[1]); // @[TLB.scala:182:28, :341:30] wire [8:0] _superpage_hits_T_53 = _superpage_hits_T_52[8:0]; // @[TLB.scala:183:{52,58}] wire _superpage_hits_T_54 = _superpage_hits_T_53 == 9'h0; // @[TLB.scala:183:{58,79}] wire [1:0] hitsVec_idx = vpn[1:0]; // @[package.scala:163:13] wire [1:0] hitsVec_idx_1 = vpn[1:0]; // @[package.scala:163:13] wire [1:0] hitsVec_idx_2 = vpn[1:0]; // @[package.scala:163:13] wire [1:0] hitsVec_idx_3 = vpn[1:0]; // @[package.scala:163:13] wire [1:0] hitsVec_idx_4 = vpn[1:0]; // @[package.scala:163:13] wire [1:0] hitsVec_idx_5 = vpn[1:0]; // @[package.scala:163:13] wire [1:0] hitsVec_idx_6 = vpn[1:0]; // @[package.scala:163:13] wire [1:0] hitsVec_idx_7 = vpn[1:0]; // @[package.scala:163:13] wire [1:0] _entries_T = vpn[1:0]; // @[package.scala:163:13] wire [1:0] _entries_T_24 = vpn[1:0]; // @[package.scala:163:13] wire [1:0] _entries_T_48 = vpn[1:0]; // @[package.scala:163:13] wire [1:0] _entries_T_72 = vpn[1:0]; // @[package.scala:163:13] wire [1:0] _entries_T_96 = vpn[1:0]; // @[package.scala:163:13] wire [1:0] _entries_T_120 = vpn[1:0]; // @[package.scala:163:13] wire [1:0] _entries_T_144 = vpn[1:0]; // @[package.scala:163:13] wire [1:0] _entries_T_168 = vpn[1:0]; // @[package.scala:163:13] wire [24:0] _hitsVec_T_1 = _hitsVec_T[26:2]; // @[TLB.scala:174:{61,68}] wire _hitsVec_T_2 = _hitsVec_T_1 == 25'h0; // @[TLB.scala:174:{68,86}] wire _hitsVec_T_3 = ~sectored_entries_0_0_tag_v; // @[TLB.scala:174:105, :339:29] wire _hitsVec_T_4 = _hitsVec_T_2 & _hitsVec_T_3; // @[TLB.scala:174:{86,95,105}] wire [3:0] _GEN_16 = {{sectored_entries_0_0_valid_3}, {sectored_entries_0_0_valid_2}, {sectored_entries_0_0_valid_1}, {sectored_entries_0_0_valid_0}}; // @[TLB.scala:188:18, :339:29] wire _hitsVec_T_5 = _GEN_16[hitsVec_idx] & _hitsVec_T_4; // @[package.scala:163:13] wire hitsVec_0 = vm_enabled & _hitsVec_T_5; // @[TLB.scala:188:18, :399:61, :440:44] wire [24:0] _hitsVec_T_7 = _hitsVec_T_6[26:2]; // @[TLB.scala:174:{61,68}] wire _hitsVec_T_8 = _hitsVec_T_7 == 25'h0; // @[TLB.scala:174:{68,86}] wire _hitsVec_T_9 = ~sectored_entries_0_1_tag_v; // @[TLB.scala:174:105, :339:29] wire _hitsVec_T_10 = _hitsVec_T_8 & _hitsVec_T_9; // @[TLB.scala:174:{86,95,105}] wire [3:0] _GEN_17 = {{sectored_entries_0_1_valid_3}, {sectored_entries_0_1_valid_2}, {sectored_entries_0_1_valid_1}, {sectored_entries_0_1_valid_0}}; // @[TLB.scala:188:18, :339:29] wire _hitsVec_T_11 = _GEN_17[hitsVec_idx_1] & _hitsVec_T_10; // @[package.scala:163:13] wire hitsVec_1 = vm_enabled & _hitsVec_T_11; // @[TLB.scala:188:18, :399:61, :440:44] wire [24:0] _hitsVec_T_13 = _hitsVec_T_12[26:2]; // @[TLB.scala:174:{61,68}] wire _hitsVec_T_14 = _hitsVec_T_13 == 25'h0; // @[TLB.scala:174:{68,86}] wire _hitsVec_T_15 = ~sectored_entries_0_2_tag_v; // @[TLB.scala:174:105, :339:29] wire _hitsVec_T_16 = _hitsVec_T_14 & _hitsVec_T_15; // @[TLB.scala:174:{86,95,105}] wire [3:0] _GEN_18 = {{sectored_entries_0_2_valid_3}, {sectored_entries_0_2_valid_2}, {sectored_entries_0_2_valid_1}, {sectored_entries_0_2_valid_0}}; // @[TLB.scala:188:18, :339:29] wire _hitsVec_T_17 = _GEN_18[hitsVec_idx_2] & _hitsVec_T_16; // @[package.scala:163:13] wire hitsVec_2 = vm_enabled & _hitsVec_T_17; // @[TLB.scala:188:18, :399:61, :440:44] wire [24:0] _hitsVec_T_19 = _hitsVec_T_18[26:2]; // @[TLB.scala:174:{61,68}] wire _hitsVec_T_20 = _hitsVec_T_19 == 25'h0; // @[TLB.scala:174:{68,86}] wire _hitsVec_T_21 = ~sectored_entries_0_3_tag_v; // @[TLB.scala:174:105, :339:29] wire _hitsVec_T_22 = _hitsVec_T_20 & _hitsVec_T_21; // @[TLB.scala:174:{86,95,105}] wire [3:0] _GEN_19 = {{sectored_entries_0_3_valid_3}, {sectored_entries_0_3_valid_2}, {sectored_entries_0_3_valid_1}, {sectored_entries_0_3_valid_0}}; // @[TLB.scala:188:18, :339:29] wire _hitsVec_T_23 = _GEN_19[hitsVec_idx_3] & _hitsVec_T_22; // @[package.scala:163:13] wire hitsVec_3 = vm_enabled & _hitsVec_T_23; // @[TLB.scala:188:18, :399:61, :440:44] wire [24:0] _hitsVec_T_25 = _hitsVec_T_24[26:2]; // @[TLB.scala:174:{61,68}] wire _hitsVec_T_26 = _hitsVec_T_25 == 25'h0; // @[TLB.scala:174:{68,86}] wire _hitsVec_T_27 = ~sectored_entries_0_4_tag_v; // @[TLB.scala:174:105, :339:29] wire _hitsVec_T_28 = _hitsVec_T_26 & _hitsVec_T_27; // @[TLB.scala:174:{86,95,105}] wire [3:0] _GEN_20 = {{sectored_entries_0_4_valid_3}, {sectored_entries_0_4_valid_2}, {sectored_entries_0_4_valid_1}, {sectored_entries_0_4_valid_0}}; // @[TLB.scala:188:18, :339:29] wire _hitsVec_T_29 = _GEN_20[hitsVec_idx_4] & _hitsVec_T_28; // @[package.scala:163:13] wire hitsVec_4 = vm_enabled & _hitsVec_T_29; // @[TLB.scala:188:18, :399:61, :440:44] wire [24:0] _hitsVec_T_31 = _hitsVec_T_30[26:2]; // @[TLB.scala:174:{61,68}] wire _hitsVec_T_32 = _hitsVec_T_31 == 25'h0; // @[TLB.scala:174:{68,86}] wire _hitsVec_T_33 = ~sectored_entries_0_5_tag_v; // @[TLB.scala:174:105, :339:29] wire _hitsVec_T_34 = _hitsVec_T_32 & _hitsVec_T_33; // @[TLB.scala:174:{86,95,105}] wire [3:0] _GEN_21 = {{sectored_entries_0_5_valid_3}, {sectored_entries_0_5_valid_2}, {sectored_entries_0_5_valid_1}, {sectored_entries_0_5_valid_0}}; // @[TLB.scala:188:18, :339:29] wire _hitsVec_T_35 = _GEN_21[hitsVec_idx_5] & _hitsVec_T_34; // @[package.scala:163:13] wire hitsVec_5 = vm_enabled & _hitsVec_T_35; // @[TLB.scala:188:18, :399:61, :440:44] wire [24:0] _hitsVec_T_37 = _hitsVec_T_36[26:2]; // @[TLB.scala:174:{61,68}] wire _hitsVec_T_38 = _hitsVec_T_37 == 25'h0; // @[TLB.scala:174:{68,86}] wire _hitsVec_T_39 = ~sectored_entries_0_6_tag_v; // @[TLB.scala:174:105, :339:29] wire _hitsVec_T_40 = _hitsVec_T_38 & _hitsVec_T_39; // @[TLB.scala:174:{86,95,105}] wire [3:0] _GEN_22 = {{sectored_entries_0_6_valid_3}, {sectored_entries_0_6_valid_2}, {sectored_entries_0_6_valid_1}, {sectored_entries_0_6_valid_0}}; // @[TLB.scala:188:18, :339:29] wire _hitsVec_T_41 = _GEN_22[hitsVec_idx_6] & _hitsVec_T_40; // @[package.scala:163:13] wire hitsVec_6 = vm_enabled & _hitsVec_T_41; // @[TLB.scala:188:18, :399:61, :440:44] wire [24:0] _hitsVec_T_43 = _hitsVec_T_42[26:2]; // @[TLB.scala:174:{61,68}] wire _hitsVec_T_44 = _hitsVec_T_43 == 25'h0; // @[TLB.scala:174:{68,86}] wire _hitsVec_T_45 = ~sectored_entries_0_7_tag_v; // @[TLB.scala:174:105, :339:29] wire _hitsVec_T_46 = _hitsVec_T_44 & _hitsVec_T_45; // @[TLB.scala:174:{86,95,105}] wire [3:0] _GEN_23 = {{sectored_entries_0_7_valid_3}, {sectored_entries_0_7_valid_2}, {sectored_entries_0_7_valid_1}, {sectored_entries_0_7_valid_0}}; // @[TLB.scala:188:18, :339:29] wire _hitsVec_T_47 = _GEN_23[hitsVec_idx_7] & _hitsVec_T_46; // @[package.scala:163:13] wire hitsVec_7 = vm_enabled & _hitsVec_T_47; // @[TLB.scala:188:18, :399:61, :440:44] wire _hitsVec_tagMatch_T = ~superpage_entries_0_tag_v; // @[TLB.scala:178:43, :341:30] wire hitsVec_tagMatch = superpage_entries_0_valid_0 & _hitsVec_tagMatch_T; // @[TLB.scala:178:{33,43}, :341:30] wire [8:0] _hitsVec_T_49 = _hitsVec_T_48[26:18]; // @[TLB.scala:183:{52,58}] wire _hitsVec_T_50 = _hitsVec_T_49 == 9'h0; // @[TLB.scala:183:{58,79}] wire _hitsVec_T_51 = _hitsVec_T_50; // @[TLB.scala:183:{40,79}] wire _hitsVec_T_52 = hitsVec_tagMatch & _hitsVec_T_51; // @[TLB.scala:178:33, :183:{29,40}] wire hitsVec_ignore_1 = _hitsVec_ignore_T_1; // @[TLB.scala:182:{28,34}] wire [8:0] _hitsVec_T_54 = _hitsVec_T_53[17:9]; // @[TLB.scala:183:{52,58}] wire _hitsVec_T_55 = _hitsVec_T_54 == 9'h0; // @[TLB.scala:183:{58,79}] wire _hitsVec_T_56 = hitsVec_ignore_1 | _hitsVec_T_55; // @[TLB.scala:182:34, :183:{40,79}] wire _hitsVec_T_57 = _hitsVec_T_52 & _hitsVec_T_56; // @[TLB.scala:183:{29,40}] wire _hitsVec_T_62 = _hitsVec_T_57; // @[TLB.scala:183:29] wire _hitsVec_ignore_T_2 = ~(superpage_entries_0_level[1]); // @[TLB.scala:182:28, :341:30] wire [8:0] _hitsVec_T_59 = _hitsVec_T_58[8:0]; // @[TLB.scala:183:{52,58}] wire _hitsVec_T_60 = _hitsVec_T_59 == 9'h0; // @[TLB.scala:183:{58,79}] wire hitsVec_8 = vm_enabled & _hitsVec_T_62; // @[TLB.scala:183:29, :399:61, :440:44] wire _hitsVec_tagMatch_T_1 = ~superpage_entries_1_tag_v; // @[TLB.scala:178:43, :341:30] wire hitsVec_tagMatch_1 = superpage_entries_1_valid_0 & _hitsVec_tagMatch_T_1; // @[TLB.scala:178:{33,43}, :341:30] wire [8:0] _hitsVec_T_64 = _hitsVec_T_63[26:18]; // @[TLB.scala:183:{52,58}] wire _hitsVec_T_65 = _hitsVec_T_64 == 9'h0; // @[TLB.scala:183:{58,79}] wire _hitsVec_T_66 = _hitsVec_T_65; // @[TLB.scala:183:{40,79}] wire _hitsVec_T_67 = hitsVec_tagMatch_1 & _hitsVec_T_66; // @[TLB.scala:178:33, :183:{29,40}] wire hitsVec_ignore_4 = _hitsVec_ignore_T_4; // @[TLB.scala:182:{28,34}] wire [8:0] _hitsVec_T_69 = _hitsVec_T_68[17:9]; // @[TLB.scala:183:{52,58}] wire _hitsVec_T_70 = _hitsVec_T_69 == 9'h0; // @[TLB.scala:183:{58,79}] wire _hitsVec_T_71 = hitsVec_ignore_4 | _hitsVec_T_70; // @[TLB.scala:182:34, :183:{40,79}] wire _hitsVec_T_72 = _hitsVec_T_67 & _hitsVec_T_71; // @[TLB.scala:183:{29,40}] wire _hitsVec_T_77 = _hitsVec_T_72; // @[TLB.scala:183:29] wire _hitsVec_ignore_T_5 = ~(superpage_entries_1_level[1]); // @[TLB.scala:182:28, :341:30] wire [8:0] _hitsVec_T_74 = _hitsVec_T_73[8:0]; // @[TLB.scala:183:{52,58}] wire _hitsVec_T_75 = _hitsVec_T_74 == 9'h0; // @[TLB.scala:183:{58,79}] wire hitsVec_9 = vm_enabled & _hitsVec_T_77; // @[TLB.scala:183:29, :399:61, :440:44] wire _hitsVec_tagMatch_T_2 = ~superpage_entries_2_tag_v; // @[TLB.scala:178:43, :341:30] wire hitsVec_tagMatch_2 = superpage_entries_2_valid_0 & _hitsVec_tagMatch_T_2; // @[TLB.scala:178:{33,43}, :341:30] wire [8:0] _hitsVec_T_79 = _hitsVec_T_78[26:18]; // @[TLB.scala:183:{52,58}] wire _hitsVec_T_80 = _hitsVec_T_79 == 9'h0; // @[TLB.scala:183:{58,79}] wire _hitsVec_T_81 = _hitsVec_T_80; // @[TLB.scala:183:{40,79}] wire _hitsVec_T_82 = hitsVec_tagMatch_2 & _hitsVec_T_81; // @[TLB.scala:178:33, :183:{29,40}] wire hitsVec_ignore_7 = _hitsVec_ignore_T_7; // @[TLB.scala:182:{28,34}] wire [8:0] _hitsVec_T_84 = _hitsVec_T_83[17:9]; // @[TLB.scala:183:{52,58}] wire _hitsVec_T_85 = _hitsVec_T_84 == 9'h0; // @[TLB.scala:183:{58,79}] wire _hitsVec_T_86 = hitsVec_ignore_7 | _hitsVec_T_85; // @[TLB.scala:182:34, :183:{40,79}] wire _hitsVec_T_87 = _hitsVec_T_82 & _hitsVec_T_86; // @[TLB.scala:183:{29,40}] wire _hitsVec_T_92 = _hitsVec_T_87; // @[TLB.scala:183:29] wire _hitsVec_ignore_T_8 = ~(superpage_entries_2_level[1]); // @[TLB.scala:182:28, :341:30] wire [8:0] _hitsVec_T_89 = _hitsVec_T_88[8:0]; // @[TLB.scala:183:{52,58}] wire _hitsVec_T_90 = _hitsVec_T_89 == 9'h0; // @[TLB.scala:183:{58,79}] wire hitsVec_10 = vm_enabled & _hitsVec_T_92; // @[TLB.scala:183:29, :399:61, :440:44] wire _hitsVec_tagMatch_T_3 = ~superpage_entries_3_tag_v; // @[TLB.scala:178:43, :341:30] wire hitsVec_tagMatch_3 = superpage_entries_3_valid_0 & _hitsVec_tagMatch_T_3; // @[TLB.scala:178:{33,43}, :341:30] wire [8:0] _hitsVec_T_94 = _hitsVec_T_93[26:18]; // @[TLB.scala:183:{52,58}] wire _hitsVec_T_95 = _hitsVec_T_94 == 9'h0; // @[TLB.scala:183:{58,79}] wire _hitsVec_T_96 = _hitsVec_T_95; // @[TLB.scala:183:{40,79}] wire _hitsVec_T_97 = hitsVec_tagMatch_3 & _hitsVec_T_96; // @[TLB.scala:178:33, :183:{29,40}] wire hitsVec_ignore_10 = _hitsVec_ignore_T_10; // @[TLB.scala:182:{28,34}] wire [8:0] _hitsVec_T_99 = _hitsVec_T_98[17:9]; // @[TLB.scala:183:{52,58}] wire _hitsVec_T_100 = _hitsVec_T_99 == 9'h0; // @[TLB.scala:183:{58,79}] wire _hitsVec_T_101 = hitsVec_ignore_10 | _hitsVec_T_100; // @[TLB.scala:182:34, :183:{40,79}] wire _hitsVec_T_102 = _hitsVec_T_97 & _hitsVec_T_101; // @[TLB.scala:183:{29,40}] wire _hitsVec_T_107 = _hitsVec_T_102; // @[TLB.scala:183:29] wire _hitsVec_ignore_T_11 = ~(superpage_entries_3_level[1]); // @[TLB.scala:182:28, :341:30] wire [8:0] _hitsVec_T_104 = _hitsVec_T_103[8:0]; // @[TLB.scala:183:{52,58}] wire _hitsVec_T_105 = _hitsVec_T_104 == 9'h0; // @[TLB.scala:183:{58,79}] wire hitsVec_11 = vm_enabled & _hitsVec_T_107; // @[TLB.scala:183:29, :399:61, :440:44] wire _hitsVec_tagMatch_T_4 = ~special_entry_tag_v; // @[TLB.scala:178:43, :346:56] wire hitsVec_tagMatch_4 = special_entry_valid_0 & _hitsVec_tagMatch_T_4; // @[TLB.scala:178:{33,43}, :346:56] wire [26:0] _T_3838 = special_entry_tag_vpn ^ vpn; // @[TLB.scala:183:52, :335:30, :346:56] wire [26:0] _hitsVec_T_108; // @[TLB.scala:183:52] assign _hitsVec_T_108 = _T_3838; // @[TLB.scala:183:52] wire [26:0] _hitsVec_T_113; // @[TLB.scala:183:52] assign _hitsVec_T_113 = _T_3838; // @[TLB.scala:183:52] wire [26:0] _hitsVec_T_118; // @[TLB.scala:183:52] assign _hitsVec_T_118 = _T_3838; // @[TLB.scala:183:52] wire [8:0] _hitsVec_T_109 = _hitsVec_T_108[26:18]; // @[TLB.scala:183:{52,58}] wire _hitsVec_T_110 = _hitsVec_T_109 == 9'h0; // @[TLB.scala:183:{58,79}] wire _hitsVec_T_111 = _hitsVec_T_110; // @[TLB.scala:183:{40,79}] wire _hitsVec_T_112 = hitsVec_tagMatch_4 & _hitsVec_T_111; // @[TLB.scala:178:33, :183:{29,40}] wire hitsVec_ignore_13 = _hitsVec_ignore_T_13; // @[TLB.scala:182:{28,34}] wire [8:0] _hitsVec_T_114 = _hitsVec_T_113[17:9]; // @[TLB.scala:183:{52,58}] wire _hitsVec_T_115 = _hitsVec_T_114 == 9'h0; // @[TLB.scala:183:{58,79}] wire _hitsVec_T_116 = hitsVec_ignore_13 | _hitsVec_T_115; // @[TLB.scala:182:34, :183:{40,79}] wire _hitsVec_T_117 = _hitsVec_T_112 & _hitsVec_T_116; // @[TLB.scala:183:{29,40}] wire _hitsVec_ignore_T_14 = ~(special_entry_level[1]); // @[TLB.scala:182:28, :197:28, :346:56] wire hitsVec_ignore_14 = _hitsVec_ignore_T_14; // @[TLB.scala:182:{28,34}] wire [8:0] _hitsVec_T_119 = _hitsVec_T_118[8:0]; // @[TLB.scala:183:{52,58}] wire _hitsVec_T_120 = _hitsVec_T_119 == 9'h0; // @[TLB.scala:183:{58,79}] wire _hitsVec_T_121 = hitsVec_ignore_14 | _hitsVec_T_120; // @[TLB.scala:182:34, :183:{40,79}] wire _hitsVec_T_122 = _hitsVec_T_117 & _hitsVec_T_121; // @[TLB.scala:183:{29,40}] wire hitsVec_12 = vm_enabled & _hitsVec_T_122; // @[TLB.scala:183:29, :399:61, :440:44] wire [1:0] real_hits_lo_lo_hi = {hitsVec_2, hitsVec_1}; // @[package.scala:45:27] wire [2:0] real_hits_lo_lo = {real_hits_lo_lo_hi, hitsVec_0}; // @[package.scala:45:27] wire [1:0] real_hits_lo_hi_hi = {hitsVec_5, hitsVec_4}; // @[package.scala:45:27] wire [2:0] real_hits_lo_hi = {real_hits_lo_hi_hi, hitsVec_3}; // @[package.scala:45:27] wire [5:0] real_hits_lo = {real_hits_lo_hi, real_hits_lo_lo}; // @[package.scala:45:27] wire [1:0] real_hits_hi_lo_hi = {hitsVec_8, hitsVec_7}; // @[package.scala:45:27] wire [2:0] real_hits_hi_lo = {real_hits_hi_lo_hi, hitsVec_6}; // @[package.scala:45:27] wire [1:0] real_hits_hi_hi_lo = {hitsVec_10, hitsVec_9}; // @[package.scala:45:27] wire [1:0] real_hits_hi_hi_hi = {hitsVec_12, hitsVec_11}; // @[package.scala:45:27] wire [3:0] real_hits_hi_hi = {real_hits_hi_hi_hi, real_hits_hi_hi_lo}; // @[package.scala:45:27] wire [6:0] real_hits_hi = {real_hits_hi_hi, real_hits_hi_lo}; // @[package.scala:45:27] wire [12:0] real_hits = {real_hits_hi, real_hits_lo}; // @[package.scala:45:27] wire [12:0] _tlb_hit_T = real_hits; // @[package.scala:45:27] wire _hits_T = ~vm_enabled; // @[TLB.scala:399:61, :442:18] wire [13:0] hits = {_hits_T, real_hits}; // @[package.scala:45:27] wire _newEntry_g_T; // @[TLB.scala:453:25] wire _newEntry_sw_T_6; // @[PTW.scala:151:40] wire _newEntry_sx_T_5; // @[PTW.scala:153:35] wire _newEntry_sr_T_5; // @[PTW.scala:149:35] wire newEntry_g; // @[TLB.scala:449:24] wire newEntry_sw; // @[TLB.scala:449:24] wire newEntry_sx; // @[TLB.scala:449:24] wire newEntry_sr; // @[TLB.scala:449:24] wire newEntry_ppp; // @[TLB.scala:449:24] wire newEntry_pal; // @[TLB.scala:449:24] wire newEntry_paa; // @[TLB.scala:449:24] wire newEntry_eff; // @[TLB.scala:449:24] assign _newEntry_g_T = io_ptw_resp_bits_pte_g_0 & io_ptw_resp_bits_pte_v_0; // @[TLB.scala:318:7, :453:25] assign newEntry_g = _newEntry_g_T; // @[TLB.scala:449:24, :453:25] wire _newEntry_ae_stage2_T = io_ptw_resp_bits_ae_final_0 & io_ptw_resp_bits_gpa_is_pte_0; // @[TLB.scala:318:7, :456:53] wire _newEntry_sr_T = ~io_ptw_resp_bits_pte_w_0; // @[TLB.scala:318:7] wire _newEntry_sr_T_1 = io_ptw_resp_bits_pte_x_0 & _newEntry_sr_T; // @[TLB.scala:318:7] wire _newEntry_sr_T_2 = io_ptw_resp_bits_pte_r_0 | _newEntry_sr_T_1; // @[TLB.scala:318:7] wire _newEntry_sr_T_3 = io_ptw_resp_bits_pte_v_0 & _newEntry_sr_T_2; // @[TLB.scala:318:7] wire _newEntry_sr_T_4 = _newEntry_sr_T_3 & io_ptw_resp_bits_pte_a_0; // @[TLB.scala:318:7] assign _newEntry_sr_T_5 = _newEntry_sr_T_4 & io_ptw_resp_bits_pte_r_0; // @[TLB.scala:318:7] assign newEntry_sr = _newEntry_sr_T_5; // @[TLB.scala:449:24] wire _newEntry_sw_T = ~io_ptw_resp_bits_pte_w_0; // @[TLB.scala:318:7] wire _newEntry_sw_T_1 = io_ptw_resp_bits_pte_x_0 & _newEntry_sw_T; // @[TLB.scala:318:7] wire _newEntry_sw_T_2 = io_ptw_resp_bits_pte_r_0 | _newEntry_sw_T_1; // @[TLB.scala:318:7] wire _newEntry_sw_T_3 = io_ptw_resp_bits_pte_v_0 & _newEntry_sw_T_2; // @[TLB.scala:318:7] wire _newEntry_sw_T_4 = _newEntry_sw_T_3 & io_ptw_resp_bits_pte_a_0; // @[TLB.scala:318:7] wire _newEntry_sw_T_5 = _newEntry_sw_T_4 & io_ptw_resp_bits_pte_w_0; // @[TLB.scala:318:7] assign _newEntry_sw_T_6 = _newEntry_sw_T_5 & io_ptw_resp_bits_pte_d_0; // @[TLB.scala:318:7] assign newEntry_sw = _newEntry_sw_T_6; // @[TLB.scala:449:24] wire _newEntry_sx_T = ~io_ptw_resp_bits_pte_w_0; // @[TLB.scala:318:7] wire _newEntry_sx_T_1 = io_ptw_resp_bits_pte_x_0 & _newEntry_sx_T; // @[TLB.scala:318:7] wire _newEntry_sx_T_2 = io_ptw_resp_bits_pte_r_0 | _newEntry_sx_T_1; // @[TLB.scala:318:7] wire _newEntry_sx_T_3 = io_ptw_resp_bits_pte_v_0 & _newEntry_sx_T_2; // @[TLB.scala:318:7] wire _newEntry_sx_T_4 = _newEntry_sx_T_3 & io_ptw_resp_bits_pte_a_0; // @[TLB.scala:318:7] assign _newEntry_sx_T_5 = _newEntry_sx_T_4 & io_ptw_resp_bits_pte_x_0; // @[TLB.scala:318:7] assign newEntry_sx = _newEntry_sx_T_5; // @[TLB.scala:449:24] wire [1:0] _GEN_24 = {newEntry_c, 1'h0}; // @[TLB.scala:217:24, :449:24] wire [1:0] special_entry_data_0_lo_lo_lo; // @[TLB.scala:217:24] assign special_entry_data_0_lo_lo_lo = _GEN_24; // @[TLB.scala:217:24] wire [1:0] superpage_entries_0_data_0_lo_lo_lo; // @[TLB.scala:217:24] assign superpage_entries_0_data_0_lo_lo_lo = _GEN_24; // @[TLB.scala:217:24] wire [1:0] superpage_entries_1_data_0_lo_lo_lo; // @[TLB.scala:217:24] assign superpage_entries_1_data_0_lo_lo_lo = _GEN_24; // @[TLB.scala:217:24] wire [1:0] superpage_entries_2_data_0_lo_lo_lo; // @[TLB.scala:217:24] assign superpage_entries_2_data_0_lo_lo_lo = _GEN_24; // @[TLB.scala:217:24] wire [1:0] superpage_entries_3_data_0_lo_lo_lo; // @[TLB.scala:217:24] assign superpage_entries_3_data_0_lo_lo_lo = _GEN_24; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_0_data_lo_lo_lo; // @[TLB.scala:217:24] assign sectored_entries_0_0_data_lo_lo_lo = _GEN_24; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_1_data_lo_lo_lo; // @[TLB.scala:217:24] assign sectored_entries_0_1_data_lo_lo_lo = _GEN_24; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_2_data_lo_lo_lo; // @[TLB.scala:217:24] assign sectored_entries_0_2_data_lo_lo_lo = _GEN_24; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_3_data_lo_lo_lo; // @[TLB.scala:217:24] assign sectored_entries_0_3_data_lo_lo_lo = _GEN_24; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_4_data_lo_lo_lo; // @[TLB.scala:217:24] assign sectored_entries_0_4_data_lo_lo_lo = _GEN_24; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_5_data_lo_lo_lo; // @[TLB.scala:217:24] assign sectored_entries_0_5_data_lo_lo_lo = _GEN_24; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_6_data_lo_lo_lo; // @[TLB.scala:217:24] assign sectored_entries_0_6_data_lo_lo_lo = _GEN_24; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_7_data_lo_lo_lo; // @[TLB.scala:217:24] assign sectored_entries_0_7_data_lo_lo_lo = _GEN_24; // @[TLB.scala:217:24] wire [1:0] _GEN_25 = {newEntry_pal, newEntry_paa}; // @[TLB.scala:217:24, :449:24] wire [1:0] special_entry_data_0_lo_lo_hi_hi; // @[TLB.scala:217:24] assign special_entry_data_0_lo_lo_hi_hi = _GEN_25; // @[TLB.scala:217:24] wire [1:0] superpage_entries_0_data_0_lo_lo_hi_hi; // @[TLB.scala:217:24] assign superpage_entries_0_data_0_lo_lo_hi_hi = _GEN_25; // @[TLB.scala:217:24] wire [1:0] superpage_entries_1_data_0_lo_lo_hi_hi; // @[TLB.scala:217:24] assign superpage_entries_1_data_0_lo_lo_hi_hi = _GEN_25; // @[TLB.scala:217:24] wire [1:0] superpage_entries_2_data_0_lo_lo_hi_hi; // @[TLB.scala:217:24] assign superpage_entries_2_data_0_lo_lo_hi_hi = _GEN_25; // @[TLB.scala:217:24] wire [1:0] superpage_entries_3_data_0_lo_lo_hi_hi; // @[TLB.scala:217:24] assign superpage_entries_3_data_0_lo_lo_hi_hi = _GEN_25; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_0_data_lo_lo_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_0_data_lo_lo_hi_hi = _GEN_25; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_1_data_lo_lo_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_1_data_lo_lo_hi_hi = _GEN_25; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_2_data_lo_lo_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_2_data_lo_lo_hi_hi = _GEN_25; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_3_data_lo_lo_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_3_data_lo_lo_hi_hi = _GEN_25; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_4_data_lo_lo_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_4_data_lo_lo_hi_hi = _GEN_25; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_5_data_lo_lo_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_5_data_lo_lo_hi_hi = _GEN_25; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_6_data_lo_lo_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_6_data_lo_lo_hi_hi = _GEN_25; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_7_data_lo_lo_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_7_data_lo_lo_hi_hi = _GEN_25; // @[TLB.scala:217:24] wire [2:0] special_entry_data_0_lo_lo_hi = {special_entry_data_0_lo_lo_hi_hi, newEntry_eff}; // @[TLB.scala:217:24, :449:24] wire [4:0] special_entry_data_0_lo_lo = {special_entry_data_0_lo_lo_hi, special_entry_data_0_lo_lo_lo}; // @[TLB.scala:217:24] wire [1:0] _GEN_26 = {newEntry_px, newEntry_pr}; // @[TLB.scala:217:24, :449:24] wire [1:0] special_entry_data_0_lo_hi_lo_hi; // @[TLB.scala:217:24] assign special_entry_data_0_lo_hi_lo_hi = _GEN_26; // @[TLB.scala:217:24] wire [1:0] superpage_entries_0_data_0_lo_hi_lo_hi; // @[TLB.scala:217:24] assign superpage_entries_0_data_0_lo_hi_lo_hi = _GEN_26; // @[TLB.scala:217:24] wire [1:0] superpage_entries_1_data_0_lo_hi_lo_hi; // @[TLB.scala:217:24] assign superpage_entries_1_data_0_lo_hi_lo_hi = _GEN_26; // @[TLB.scala:217:24] wire [1:0] superpage_entries_2_data_0_lo_hi_lo_hi; // @[TLB.scala:217:24] assign superpage_entries_2_data_0_lo_hi_lo_hi = _GEN_26; // @[TLB.scala:217:24] wire [1:0] superpage_entries_3_data_0_lo_hi_lo_hi; // @[TLB.scala:217:24] assign superpage_entries_3_data_0_lo_hi_lo_hi = _GEN_26; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_0_data_lo_hi_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_0_0_data_lo_hi_lo_hi = _GEN_26; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_1_data_lo_hi_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_0_1_data_lo_hi_lo_hi = _GEN_26; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_2_data_lo_hi_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_0_2_data_lo_hi_lo_hi = _GEN_26; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_3_data_lo_hi_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_0_3_data_lo_hi_lo_hi = _GEN_26; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_4_data_lo_hi_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_0_4_data_lo_hi_lo_hi = _GEN_26; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_5_data_lo_hi_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_0_5_data_lo_hi_lo_hi = _GEN_26; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_6_data_lo_hi_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_0_6_data_lo_hi_lo_hi = _GEN_26; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_7_data_lo_hi_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_0_7_data_lo_hi_lo_hi = _GEN_26; // @[TLB.scala:217:24] wire [2:0] special_entry_data_0_lo_hi_lo = {special_entry_data_0_lo_hi_lo_hi, newEntry_ppp}; // @[TLB.scala:217:24, :449:24] wire [1:0] _GEN_27 = {newEntry_hx, newEntry_hr}; // @[TLB.scala:217:24, :449:24] wire [1:0] special_entry_data_0_lo_hi_hi_hi; // @[TLB.scala:217:24] assign special_entry_data_0_lo_hi_hi_hi = _GEN_27; // @[TLB.scala:217:24] wire [1:0] superpage_entries_0_data_0_lo_hi_hi_hi; // @[TLB.scala:217:24] assign superpage_entries_0_data_0_lo_hi_hi_hi = _GEN_27; // @[TLB.scala:217:24] wire [1:0] superpage_entries_1_data_0_lo_hi_hi_hi; // @[TLB.scala:217:24] assign superpage_entries_1_data_0_lo_hi_hi_hi = _GEN_27; // @[TLB.scala:217:24] wire [1:0] superpage_entries_2_data_0_lo_hi_hi_hi; // @[TLB.scala:217:24] assign superpage_entries_2_data_0_lo_hi_hi_hi = _GEN_27; // @[TLB.scala:217:24] wire [1:0] superpage_entries_3_data_0_lo_hi_hi_hi; // @[TLB.scala:217:24] assign superpage_entries_3_data_0_lo_hi_hi_hi = _GEN_27; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_0_data_lo_hi_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_0_data_lo_hi_hi_hi = _GEN_27; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_1_data_lo_hi_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_1_data_lo_hi_hi_hi = _GEN_27; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_2_data_lo_hi_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_2_data_lo_hi_hi_hi = _GEN_27; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_3_data_lo_hi_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_3_data_lo_hi_hi_hi = _GEN_27; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_4_data_lo_hi_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_4_data_lo_hi_hi_hi = _GEN_27; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_5_data_lo_hi_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_5_data_lo_hi_hi_hi = _GEN_27; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_6_data_lo_hi_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_6_data_lo_hi_hi_hi = _GEN_27; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_7_data_lo_hi_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_7_data_lo_hi_hi_hi = _GEN_27; // @[TLB.scala:217:24] wire [2:0] special_entry_data_0_lo_hi_hi = {special_entry_data_0_lo_hi_hi_hi, newEntry_pw}; // @[TLB.scala:217:24, :449:24] wire [5:0] special_entry_data_0_lo_hi = {special_entry_data_0_lo_hi_hi, special_entry_data_0_lo_hi_lo}; // @[TLB.scala:217:24] wire [10:0] special_entry_data_0_lo = {special_entry_data_0_lo_hi, special_entry_data_0_lo_lo}; // @[TLB.scala:217:24] wire [1:0] _GEN_28 = {newEntry_sx, newEntry_sr}; // @[TLB.scala:217:24, :449:24] wire [1:0] special_entry_data_0_hi_lo_lo_hi; // @[TLB.scala:217:24] assign special_entry_data_0_hi_lo_lo_hi = _GEN_28; // @[TLB.scala:217:24] wire [1:0] superpage_entries_0_data_0_hi_lo_lo_hi; // @[TLB.scala:217:24] assign superpage_entries_0_data_0_hi_lo_lo_hi = _GEN_28; // @[TLB.scala:217:24] wire [1:0] superpage_entries_1_data_0_hi_lo_lo_hi; // @[TLB.scala:217:24] assign superpage_entries_1_data_0_hi_lo_lo_hi = _GEN_28; // @[TLB.scala:217:24] wire [1:0] superpage_entries_2_data_0_hi_lo_lo_hi; // @[TLB.scala:217:24] assign superpage_entries_2_data_0_hi_lo_lo_hi = _GEN_28; // @[TLB.scala:217:24] wire [1:0] superpage_entries_3_data_0_hi_lo_lo_hi; // @[TLB.scala:217:24] assign superpage_entries_3_data_0_hi_lo_lo_hi = _GEN_28; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_0_data_hi_lo_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_0_0_data_hi_lo_lo_hi = _GEN_28; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_1_data_hi_lo_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_0_1_data_hi_lo_lo_hi = _GEN_28; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_2_data_hi_lo_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_0_2_data_hi_lo_lo_hi = _GEN_28; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_3_data_hi_lo_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_0_3_data_hi_lo_lo_hi = _GEN_28; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_4_data_hi_lo_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_0_4_data_hi_lo_lo_hi = _GEN_28; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_5_data_hi_lo_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_0_5_data_hi_lo_lo_hi = _GEN_28; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_6_data_hi_lo_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_0_6_data_hi_lo_lo_hi = _GEN_28; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_7_data_hi_lo_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_0_7_data_hi_lo_lo_hi = _GEN_28; // @[TLB.scala:217:24] wire [2:0] special_entry_data_0_hi_lo_lo = {special_entry_data_0_hi_lo_lo_hi, newEntry_hw}; // @[TLB.scala:217:24, :449:24] wire [1:0] _GEN_29 = {newEntry_pf, newEntry_gf}; // @[TLB.scala:217:24, :449:24] wire [1:0] special_entry_data_0_hi_lo_hi_hi; // @[TLB.scala:217:24] assign special_entry_data_0_hi_lo_hi_hi = _GEN_29; // @[TLB.scala:217:24] wire [1:0] superpage_entries_0_data_0_hi_lo_hi_hi; // @[TLB.scala:217:24] assign superpage_entries_0_data_0_hi_lo_hi_hi = _GEN_29; // @[TLB.scala:217:24] wire [1:0] superpage_entries_1_data_0_hi_lo_hi_hi; // @[TLB.scala:217:24] assign superpage_entries_1_data_0_hi_lo_hi_hi = _GEN_29; // @[TLB.scala:217:24] wire [1:0] superpage_entries_2_data_0_hi_lo_hi_hi; // @[TLB.scala:217:24] assign superpage_entries_2_data_0_hi_lo_hi_hi = _GEN_29; // @[TLB.scala:217:24] wire [1:0] superpage_entries_3_data_0_hi_lo_hi_hi; // @[TLB.scala:217:24] assign superpage_entries_3_data_0_hi_lo_hi_hi = _GEN_29; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_0_data_hi_lo_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_0_data_hi_lo_hi_hi = _GEN_29; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_1_data_hi_lo_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_1_data_hi_lo_hi_hi = _GEN_29; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_2_data_hi_lo_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_2_data_hi_lo_hi_hi = _GEN_29; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_3_data_hi_lo_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_3_data_hi_lo_hi_hi = _GEN_29; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_4_data_hi_lo_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_4_data_hi_lo_hi_hi = _GEN_29; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_5_data_hi_lo_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_5_data_hi_lo_hi_hi = _GEN_29; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_6_data_hi_lo_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_6_data_hi_lo_hi_hi = _GEN_29; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_7_data_hi_lo_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_7_data_hi_lo_hi_hi = _GEN_29; // @[TLB.scala:217:24] wire [2:0] special_entry_data_0_hi_lo_hi = {special_entry_data_0_hi_lo_hi_hi, newEntry_sw}; // @[TLB.scala:217:24, :449:24] wire [5:0] special_entry_data_0_hi_lo = {special_entry_data_0_hi_lo_hi, special_entry_data_0_hi_lo_lo}; // @[TLB.scala:217:24] wire [1:0] _GEN_30 = {newEntry_ae_ptw, newEntry_ae_final}; // @[TLB.scala:217:24, :449:24] wire [1:0] special_entry_data_0_hi_hi_lo_hi; // @[TLB.scala:217:24] assign special_entry_data_0_hi_hi_lo_hi = _GEN_30; // @[TLB.scala:217:24] wire [1:0] superpage_entries_0_data_0_hi_hi_lo_hi; // @[TLB.scala:217:24] assign superpage_entries_0_data_0_hi_hi_lo_hi = _GEN_30; // @[TLB.scala:217:24] wire [1:0] superpage_entries_1_data_0_hi_hi_lo_hi; // @[TLB.scala:217:24] assign superpage_entries_1_data_0_hi_hi_lo_hi = _GEN_30; // @[TLB.scala:217:24] wire [1:0] superpage_entries_2_data_0_hi_hi_lo_hi; // @[TLB.scala:217:24] assign superpage_entries_2_data_0_hi_hi_lo_hi = _GEN_30; // @[TLB.scala:217:24] wire [1:0] superpage_entries_3_data_0_hi_hi_lo_hi; // @[TLB.scala:217:24] assign superpage_entries_3_data_0_hi_hi_lo_hi = _GEN_30; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_0_data_hi_hi_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_0_0_data_hi_hi_lo_hi = _GEN_30; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_1_data_hi_hi_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_0_1_data_hi_hi_lo_hi = _GEN_30; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_2_data_hi_hi_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_0_2_data_hi_hi_lo_hi = _GEN_30; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_3_data_hi_hi_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_0_3_data_hi_hi_lo_hi = _GEN_30; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_4_data_hi_hi_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_0_4_data_hi_hi_lo_hi = _GEN_30; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_5_data_hi_hi_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_0_5_data_hi_hi_lo_hi = _GEN_30; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_6_data_hi_hi_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_0_6_data_hi_hi_lo_hi = _GEN_30; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_7_data_hi_hi_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_0_7_data_hi_hi_lo_hi = _GEN_30; // @[TLB.scala:217:24] wire [2:0] special_entry_data_0_hi_hi_lo = {special_entry_data_0_hi_hi_lo_hi, 1'h0}; // @[TLB.scala:217:24] wire [20:0] _GEN_31 = {newEntry_ppn, newEntry_u}; // @[TLB.scala:217:24, :449:24] wire [20:0] special_entry_data_0_hi_hi_hi_hi; // @[TLB.scala:217:24] assign special_entry_data_0_hi_hi_hi_hi = _GEN_31; // @[TLB.scala:217:24] wire [20:0] superpage_entries_0_data_0_hi_hi_hi_hi; // @[TLB.scala:217:24] assign superpage_entries_0_data_0_hi_hi_hi_hi = _GEN_31; // @[TLB.scala:217:24] wire [20:0] superpage_entries_1_data_0_hi_hi_hi_hi; // @[TLB.scala:217:24] assign superpage_entries_1_data_0_hi_hi_hi_hi = _GEN_31; // @[TLB.scala:217:24] wire [20:0] superpage_entries_2_data_0_hi_hi_hi_hi; // @[TLB.scala:217:24] assign superpage_entries_2_data_0_hi_hi_hi_hi = _GEN_31; // @[TLB.scala:217:24] wire [20:0] superpage_entries_3_data_0_hi_hi_hi_hi; // @[TLB.scala:217:24] assign superpage_entries_3_data_0_hi_hi_hi_hi = _GEN_31; // @[TLB.scala:217:24] wire [20:0] sectored_entries_0_0_data_hi_hi_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_0_data_hi_hi_hi_hi = _GEN_31; // @[TLB.scala:217:24] wire [20:0] sectored_entries_0_1_data_hi_hi_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_1_data_hi_hi_hi_hi = _GEN_31; // @[TLB.scala:217:24] wire [20:0] sectored_entries_0_2_data_hi_hi_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_2_data_hi_hi_hi_hi = _GEN_31; // @[TLB.scala:217:24] wire [20:0] sectored_entries_0_3_data_hi_hi_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_3_data_hi_hi_hi_hi = _GEN_31; // @[TLB.scala:217:24] wire [20:0] sectored_entries_0_4_data_hi_hi_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_4_data_hi_hi_hi_hi = _GEN_31; // @[TLB.scala:217:24] wire [20:0] sectored_entries_0_5_data_hi_hi_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_5_data_hi_hi_hi_hi = _GEN_31; // @[TLB.scala:217:24] wire [20:0] sectored_entries_0_6_data_hi_hi_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_6_data_hi_hi_hi_hi = _GEN_31; // @[TLB.scala:217:24] wire [20:0] sectored_entries_0_7_data_hi_hi_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_7_data_hi_hi_hi_hi = _GEN_31; // @[TLB.scala:217:24] wire [21:0] special_entry_data_0_hi_hi_hi = {special_entry_data_0_hi_hi_hi_hi, newEntry_g}; // @[TLB.scala:217:24, :449:24] wire [24:0] special_entry_data_0_hi_hi = {special_entry_data_0_hi_hi_hi, special_entry_data_0_hi_hi_lo}; // @[TLB.scala:217:24] wire [30:0] special_entry_data_0_hi = {special_entry_data_0_hi_hi, special_entry_data_0_hi_lo}; // @[TLB.scala:217:24] wire [41:0] _special_entry_data_0_T = {special_entry_data_0_hi, special_entry_data_0_lo}; // @[TLB.scala:217:24] wire _superpage_entries_0_level_T = io_ptw_resp_bits_level_0[0]; // @[package.scala:163:13] wire _superpage_entries_1_level_T = io_ptw_resp_bits_level_0[0]; // @[package.scala:163:13] wire _superpage_entries_2_level_T = io_ptw_resp_bits_level_0[0]; // @[package.scala:163:13] wire _superpage_entries_3_level_T = io_ptw_resp_bits_level_0[0]; // @[package.scala:163:13] wire [2:0] superpage_entries_0_data_0_lo_lo_hi = {superpage_entries_0_data_0_lo_lo_hi_hi, newEntry_eff}; // @[TLB.scala:217:24, :449:24] wire [4:0] superpage_entries_0_data_0_lo_lo = {superpage_entries_0_data_0_lo_lo_hi, superpage_entries_0_data_0_lo_lo_lo}; // @[TLB.scala:217:24] wire [2:0] superpage_entries_0_data_0_lo_hi_lo = {superpage_entries_0_data_0_lo_hi_lo_hi, newEntry_ppp}; // @[TLB.scala:217:24, :449:24] wire [2:0] superpage_entries_0_data_0_lo_hi_hi = {superpage_entries_0_data_0_lo_hi_hi_hi, newEntry_pw}; // @[TLB.scala:217:24, :449:24] wire [5:0] superpage_entries_0_data_0_lo_hi = {superpage_entries_0_data_0_lo_hi_hi, superpage_entries_0_data_0_lo_hi_lo}; // @[TLB.scala:217:24] wire [10:0] superpage_entries_0_data_0_lo = {superpage_entries_0_data_0_lo_hi, superpage_entries_0_data_0_lo_lo}; // @[TLB.scala:217:24] wire [2:0] superpage_entries_0_data_0_hi_lo_lo = {superpage_entries_0_data_0_hi_lo_lo_hi, newEntry_hw}; // @[TLB.scala:217:24, :449:24] wire [2:0] superpage_entries_0_data_0_hi_lo_hi = {superpage_entries_0_data_0_hi_lo_hi_hi, newEntry_sw}; // @[TLB.scala:217:24, :449:24] wire [5:0] superpage_entries_0_data_0_hi_lo = {superpage_entries_0_data_0_hi_lo_hi, superpage_entries_0_data_0_hi_lo_lo}; // @[TLB.scala:217:24] wire [2:0] superpage_entries_0_data_0_hi_hi_lo = {superpage_entries_0_data_0_hi_hi_lo_hi, 1'h0}; // @[TLB.scala:217:24] wire [21:0] superpage_entries_0_data_0_hi_hi_hi = {superpage_entries_0_data_0_hi_hi_hi_hi, newEntry_g}; // @[TLB.scala:217:24, :449:24] wire [24:0] superpage_entries_0_data_0_hi_hi = {superpage_entries_0_data_0_hi_hi_hi, superpage_entries_0_data_0_hi_hi_lo}; // @[TLB.scala:217:24] wire [30:0] superpage_entries_0_data_0_hi = {superpage_entries_0_data_0_hi_hi, superpage_entries_0_data_0_hi_lo}; // @[TLB.scala:217:24] wire [41:0] _superpage_entries_0_data_0_T = {superpage_entries_0_data_0_hi, superpage_entries_0_data_0_lo}; // @[TLB.scala:217:24] wire [2:0] superpage_entries_1_data_0_lo_lo_hi = {superpage_entries_1_data_0_lo_lo_hi_hi, newEntry_eff}; // @[TLB.scala:217:24, :449:24] wire [4:0] superpage_entries_1_data_0_lo_lo = {superpage_entries_1_data_0_lo_lo_hi, superpage_entries_1_data_0_lo_lo_lo}; // @[TLB.scala:217:24] wire [2:0] superpage_entries_1_data_0_lo_hi_lo = {superpage_entries_1_data_0_lo_hi_lo_hi, newEntry_ppp}; // @[TLB.scala:217:24, :449:24] wire [2:0] superpage_entries_1_data_0_lo_hi_hi = {superpage_entries_1_data_0_lo_hi_hi_hi, newEntry_pw}; // @[TLB.scala:217:24, :449:24] wire [5:0] superpage_entries_1_data_0_lo_hi = {superpage_entries_1_data_0_lo_hi_hi, superpage_entries_1_data_0_lo_hi_lo}; // @[TLB.scala:217:24] wire [10:0] superpage_entries_1_data_0_lo = {superpage_entries_1_data_0_lo_hi, superpage_entries_1_data_0_lo_lo}; // @[TLB.scala:217:24] wire [2:0] superpage_entries_1_data_0_hi_lo_lo = {superpage_entries_1_data_0_hi_lo_lo_hi, newEntry_hw}; // @[TLB.scala:217:24, :449:24] wire [2:0] superpage_entries_1_data_0_hi_lo_hi = {superpage_entries_1_data_0_hi_lo_hi_hi, newEntry_sw}; // @[TLB.scala:217:24, :449:24] wire [5:0] superpage_entries_1_data_0_hi_lo = {superpage_entries_1_data_0_hi_lo_hi, superpage_entries_1_data_0_hi_lo_lo}; // @[TLB.scala:217:24] wire [2:0] superpage_entries_1_data_0_hi_hi_lo = {superpage_entries_1_data_0_hi_hi_lo_hi, 1'h0}; // @[TLB.scala:217:24] wire [21:0] superpage_entries_1_data_0_hi_hi_hi = {superpage_entries_1_data_0_hi_hi_hi_hi, newEntry_g}; // @[TLB.scala:217:24, :449:24] wire [24:0] superpage_entries_1_data_0_hi_hi = {superpage_entries_1_data_0_hi_hi_hi, superpage_entries_1_data_0_hi_hi_lo}; // @[TLB.scala:217:24] wire [30:0] superpage_entries_1_data_0_hi = {superpage_entries_1_data_0_hi_hi, superpage_entries_1_data_0_hi_lo}; // @[TLB.scala:217:24] wire [41:0] _superpage_entries_1_data_0_T = {superpage_entries_1_data_0_hi, superpage_entries_1_data_0_lo}; // @[TLB.scala:217:24] wire [2:0] superpage_entries_2_data_0_lo_lo_hi = {superpage_entries_2_data_0_lo_lo_hi_hi, newEntry_eff}; // @[TLB.scala:217:24, :449:24] wire [4:0] superpage_entries_2_data_0_lo_lo = {superpage_entries_2_data_0_lo_lo_hi, superpage_entries_2_data_0_lo_lo_lo}; // @[TLB.scala:217:24] wire [2:0] superpage_entries_2_data_0_lo_hi_lo = {superpage_entries_2_data_0_lo_hi_lo_hi, newEntry_ppp}; // @[TLB.scala:217:24, :449:24] wire [2:0] superpage_entries_2_data_0_lo_hi_hi = {superpage_entries_2_data_0_lo_hi_hi_hi, newEntry_pw}; // @[TLB.scala:217:24, :449:24] wire [5:0] superpage_entries_2_data_0_lo_hi = {superpage_entries_2_data_0_lo_hi_hi, superpage_entries_2_data_0_lo_hi_lo}; // @[TLB.scala:217:24] wire [10:0] superpage_entries_2_data_0_lo = {superpage_entries_2_data_0_lo_hi, superpage_entries_2_data_0_lo_lo}; // @[TLB.scala:217:24] wire [2:0] superpage_entries_2_data_0_hi_lo_lo = {superpage_entries_2_data_0_hi_lo_lo_hi, newEntry_hw}; // @[TLB.scala:217:24, :449:24] wire [2:0] superpage_entries_2_data_0_hi_lo_hi = {superpage_entries_2_data_0_hi_lo_hi_hi, newEntry_sw}; // @[TLB.scala:217:24, :449:24] wire [5:0] superpage_entries_2_data_0_hi_lo = {superpage_entries_2_data_0_hi_lo_hi, superpage_entries_2_data_0_hi_lo_lo}; // @[TLB.scala:217:24] wire [2:0] superpage_entries_2_data_0_hi_hi_lo = {superpage_entries_2_data_0_hi_hi_lo_hi, 1'h0}; // @[TLB.scala:217:24] wire [21:0] superpage_entries_2_data_0_hi_hi_hi = {superpage_entries_2_data_0_hi_hi_hi_hi, newEntry_g}; // @[TLB.scala:217:24, :449:24] wire [24:0] superpage_entries_2_data_0_hi_hi = {superpage_entries_2_data_0_hi_hi_hi, superpage_entries_2_data_0_hi_hi_lo}; // @[TLB.scala:217:24] wire [30:0] superpage_entries_2_data_0_hi = {superpage_entries_2_data_0_hi_hi, superpage_entries_2_data_0_hi_lo}; // @[TLB.scala:217:24] wire [41:0] _superpage_entries_2_data_0_T = {superpage_entries_2_data_0_hi, superpage_entries_2_data_0_lo}; // @[TLB.scala:217:24] wire [2:0] superpage_entries_3_data_0_lo_lo_hi = {superpage_entries_3_data_0_lo_lo_hi_hi, newEntry_eff}; // @[TLB.scala:217:24, :449:24] wire [4:0] superpage_entries_3_data_0_lo_lo = {superpage_entries_3_data_0_lo_lo_hi, superpage_entries_3_data_0_lo_lo_lo}; // @[TLB.scala:217:24] wire [2:0] superpage_entries_3_data_0_lo_hi_lo = {superpage_entries_3_data_0_lo_hi_lo_hi, newEntry_ppp}; // @[TLB.scala:217:24, :449:24] wire [2:0] superpage_entries_3_data_0_lo_hi_hi = {superpage_entries_3_data_0_lo_hi_hi_hi, newEntry_pw}; // @[TLB.scala:217:24, :449:24] wire [5:0] superpage_entries_3_data_0_lo_hi = {superpage_entries_3_data_0_lo_hi_hi, superpage_entries_3_data_0_lo_hi_lo}; // @[TLB.scala:217:24] wire [10:0] superpage_entries_3_data_0_lo = {superpage_entries_3_data_0_lo_hi, superpage_entries_3_data_0_lo_lo}; // @[TLB.scala:217:24] wire [2:0] superpage_entries_3_data_0_hi_lo_lo = {superpage_entries_3_data_0_hi_lo_lo_hi, newEntry_hw}; // @[TLB.scala:217:24, :449:24] wire [2:0] superpage_entries_3_data_0_hi_lo_hi = {superpage_entries_3_data_0_hi_lo_hi_hi, newEntry_sw}; // @[TLB.scala:217:24, :449:24] wire [5:0] superpage_entries_3_data_0_hi_lo = {superpage_entries_3_data_0_hi_lo_hi, superpage_entries_3_data_0_hi_lo_lo}; // @[TLB.scala:217:24] wire [2:0] superpage_entries_3_data_0_hi_hi_lo = {superpage_entries_3_data_0_hi_hi_lo_hi, 1'h0}; // @[TLB.scala:217:24] wire [21:0] superpage_entries_3_data_0_hi_hi_hi = {superpage_entries_3_data_0_hi_hi_hi_hi, newEntry_g}; // @[TLB.scala:217:24, :449:24] wire [24:0] superpage_entries_3_data_0_hi_hi = {superpage_entries_3_data_0_hi_hi_hi, superpage_entries_3_data_0_hi_hi_lo}; // @[TLB.scala:217:24] wire [30:0] superpage_entries_3_data_0_hi = {superpage_entries_3_data_0_hi_hi, superpage_entries_3_data_0_hi_lo}; // @[TLB.scala:217:24] wire [41:0] _superpage_entries_3_data_0_T = {superpage_entries_3_data_0_hi, superpage_entries_3_data_0_lo}; // @[TLB.scala:217:24] wire [2:0] waddr_1 = r_sectored_hit_valid ? r_sectored_hit_bits : r_sectored_repl_addr; // @[TLB.scala:356:33, :357:27, :485:22] wire [1:0] idx = r_refill_tag[1:0]; // @[package.scala:163:13] wire [1:0] idx_1 = r_refill_tag[1:0]; // @[package.scala:163:13] wire [1:0] idx_2 = r_refill_tag[1:0]; // @[package.scala:163:13] wire [1:0] idx_3 = r_refill_tag[1:0]; // @[package.scala:163:13] wire [1:0] idx_4 = r_refill_tag[1:0]; // @[package.scala:163:13] wire [1:0] idx_5 = r_refill_tag[1:0]; // @[package.scala:163:13] wire [1:0] idx_6 = r_refill_tag[1:0]; // @[package.scala:163:13] wire [1:0] idx_7 = r_refill_tag[1:0]; // @[package.scala:163:13] wire [2:0] sectored_entries_0_0_data_lo_lo_hi = {sectored_entries_0_0_data_lo_lo_hi_hi, newEntry_eff}; // @[TLB.scala:217:24, :449:24] wire [4:0] sectored_entries_0_0_data_lo_lo = {sectored_entries_0_0_data_lo_lo_hi, sectored_entries_0_0_data_lo_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_0_data_lo_hi_lo = {sectored_entries_0_0_data_lo_hi_lo_hi, newEntry_ppp}; // @[TLB.scala:217:24, :449:24] wire [2:0] sectored_entries_0_0_data_lo_hi_hi = {sectored_entries_0_0_data_lo_hi_hi_hi, newEntry_pw}; // @[TLB.scala:217:24, :449:24] wire [5:0] sectored_entries_0_0_data_lo_hi = {sectored_entries_0_0_data_lo_hi_hi, sectored_entries_0_0_data_lo_hi_lo}; // @[TLB.scala:217:24] wire [10:0] sectored_entries_0_0_data_lo = {sectored_entries_0_0_data_lo_hi, sectored_entries_0_0_data_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_0_data_hi_lo_lo = {sectored_entries_0_0_data_hi_lo_lo_hi, newEntry_hw}; // @[TLB.scala:217:24, :449:24] wire [2:0] sectored_entries_0_0_data_hi_lo_hi = {sectored_entries_0_0_data_hi_lo_hi_hi, newEntry_sw}; // @[TLB.scala:217:24, :449:24] wire [5:0] sectored_entries_0_0_data_hi_lo = {sectored_entries_0_0_data_hi_lo_hi, sectored_entries_0_0_data_hi_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_0_data_hi_hi_lo = {sectored_entries_0_0_data_hi_hi_lo_hi, 1'h0}; // @[TLB.scala:217:24] wire [21:0] sectored_entries_0_0_data_hi_hi_hi = {sectored_entries_0_0_data_hi_hi_hi_hi, newEntry_g}; // @[TLB.scala:217:24, :449:24] wire [24:0] sectored_entries_0_0_data_hi_hi = {sectored_entries_0_0_data_hi_hi_hi, sectored_entries_0_0_data_hi_hi_lo}; // @[TLB.scala:217:24] wire [30:0] sectored_entries_0_0_data_hi = {sectored_entries_0_0_data_hi_hi, sectored_entries_0_0_data_hi_lo}; // @[TLB.scala:217:24] wire [41:0] _sectored_entries_0_0_data_T = {sectored_entries_0_0_data_hi, sectored_entries_0_0_data_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_1_data_lo_lo_hi = {sectored_entries_0_1_data_lo_lo_hi_hi, newEntry_eff}; // @[TLB.scala:217:24, :449:24] wire [4:0] sectored_entries_0_1_data_lo_lo = {sectored_entries_0_1_data_lo_lo_hi, sectored_entries_0_1_data_lo_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_1_data_lo_hi_lo = {sectored_entries_0_1_data_lo_hi_lo_hi, newEntry_ppp}; // @[TLB.scala:217:24, :449:24] wire [2:0] sectored_entries_0_1_data_lo_hi_hi = {sectored_entries_0_1_data_lo_hi_hi_hi, newEntry_pw}; // @[TLB.scala:217:24, :449:24] wire [5:0] sectored_entries_0_1_data_lo_hi = {sectored_entries_0_1_data_lo_hi_hi, sectored_entries_0_1_data_lo_hi_lo}; // @[TLB.scala:217:24] wire [10:0] sectored_entries_0_1_data_lo = {sectored_entries_0_1_data_lo_hi, sectored_entries_0_1_data_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_1_data_hi_lo_lo = {sectored_entries_0_1_data_hi_lo_lo_hi, newEntry_hw}; // @[TLB.scala:217:24, :449:24] wire [2:0] sectored_entries_0_1_data_hi_lo_hi = {sectored_entries_0_1_data_hi_lo_hi_hi, newEntry_sw}; // @[TLB.scala:217:24, :449:24] wire [5:0] sectored_entries_0_1_data_hi_lo = {sectored_entries_0_1_data_hi_lo_hi, sectored_entries_0_1_data_hi_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_1_data_hi_hi_lo = {sectored_entries_0_1_data_hi_hi_lo_hi, 1'h0}; // @[TLB.scala:217:24] wire [21:0] sectored_entries_0_1_data_hi_hi_hi = {sectored_entries_0_1_data_hi_hi_hi_hi, newEntry_g}; // @[TLB.scala:217:24, :449:24] wire [24:0] sectored_entries_0_1_data_hi_hi = {sectored_entries_0_1_data_hi_hi_hi, sectored_entries_0_1_data_hi_hi_lo}; // @[TLB.scala:217:24] wire [30:0] sectored_entries_0_1_data_hi = {sectored_entries_0_1_data_hi_hi, sectored_entries_0_1_data_hi_lo}; // @[TLB.scala:217:24] wire [41:0] _sectored_entries_0_1_data_T = {sectored_entries_0_1_data_hi, sectored_entries_0_1_data_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_2_data_lo_lo_hi = {sectored_entries_0_2_data_lo_lo_hi_hi, newEntry_eff}; // @[TLB.scala:217:24, :449:24] wire [4:0] sectored_entries_0_2_data_lo_lo = {sectored_entries_0_2_data_lo_lo_hi, sectored_entries_0_2_data_lo_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_2_data_lo_hi_lo = {sectored_entries_0_2_data_lo_hi_lo_hi, newEntry_ppp}; // @[TLB.scala:217:24, :449:24] wire [2:0] sectored_entries_0_2_data_lo_hi_hi = {sectored_entries_0_2_data_lo_hi_hi_hi, newEntry_pw}; // @[TLB.scala:217:24, :449:24] wire [5:0] sectored_entries_0_2_data_lo_hi = {sectored_entries_0_2_data_lo_hi_hi, sectored_entries_0_2_data_lo_hi_lo}; // @[TLB.scala:217:24] wire [10:0] sectored_entries_0_2_data_lo = {sectored_entries_0_2_data_lo_hi, sectored_entries_0_2_data_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_2_data_hi_lo_lo = {sectored_entries_0_2_data_hi_lo_lo_hi, newEntry_hw}; // @[TLB.scala:217:24, :449:24] wire [2:0] sectored_entries_0_2_data_hi_lo_hi = {sectored_entries_0_2_data_hi_lo_hi_hi, newEntry_sw}; // @[TLB.scala:217:24, :449:24] wire [5:0] sectored_entries_0_2_data_hi_lo = {sectored_entries_0_2_data_hi_lo_hi, sectored_entries_0_2_data_hi_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_2_data_hi_hi_lo = {sectored_entries_0_2_data_hi_hi_lo_hi, 1'h0}; // @[TLB.scala:217:24] wire [21:0] sectored_entries_0_2_data_hi_hi_hi = {sectored_entries_0_2_data_hi_hi_hi_hi, newEntry_g}; // @[TLB.scala:217:24, :449:24] wire [24:0] sectored_entries_0_2_data_hi_hi = {sectored_entries_0_2_data_hi_hi_hi, sectored_entries_0_2_data_hi_hi_lo}; // @[TLB.scala:217:24] wire [30:0] sectored_entries_0_2_data_hi = {sectored_entries_0_2_data_hi_hi, sectored_entries_0_2_data_hi_lo}; // @[TLB.scala:217:24] wire [41:0] _sectored_entries_0_2_data_T = {sectored_entries_0_2_data_hi, sectored_entries_0_2_data_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_3_data_lo_lo_hi = {sectored_entries_0_3_data_lo_lo_hi_hi, newEntry_eff}; // @[TLB.scala:217:24, :449:24] wire [4:0] sectored_entries_0_3_data_lo_lo = {sectored_entries_0_3_data_lo_lo_hi, sectored_entries_0_3_data_lo_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_3_data_lo_hi_lo = {sectored_entries_0_3_data_lo_hi_lo_hi, newEntry_ppp}; // @[TLB.scala:217:24, :449:24] wire [2:0] sectored_entries_0_3_data_lo_hi_hi = {sectored_entries_0_3_data_lo_hi_hi_hi, newEntry_pw}; // @[TLB.scala:217:24, :449:24] wire [5:0] sectored_entries_0_3_data_lo_hi = {sectored_entries_0_3_data_lo_hi_hi, sectored_entries_0_3_data_lo_hi_lo}; // @[TLB.scala:217:24] wire [10:0] sectored_entries_0_3_data_lo = {sectored_entries_0_3_data_lo_hi, sectored_entries_0_3_data_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_3_data_hi_lo_lo = {sectored_entries_0_3_data_hi_lo_lo_hi, newEntry_hw}; // @[TLB.scala:217:24, :449:24] wire [2:0] sectored_entries_0_3_data_hi_lo_hi = {sectored_entries_0_3_data_hi_lo_hi_hi, newEntry_sw}; // @[TLB.scala:217:24, :449:24] wire [5:0] sectored_entries_0_3_data_hi_lo = {sectored_entries_0_3_data_hi_lo_hi, sectored_entries_0_3_data_hi_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_3_data_hi_hi_lo = {sectored_entries_0_3_data_hi_hi_lo_hi, 1'h0}; // @[TLB.scala:217:24] wire [21:0] sectored_entries_0_3_data_hi_hi_hi = {sectored_entries_0_3_data_hi_hi_hi_hi, newEntry_g}; // @[TLB.scala:217:24, :449:24] wire [24:0] sectored_entries_0_3_data_hi_hi = {sectored_entries_0_3_data_hi_hi_hi, sectored_entries_0_3_data_hi_hi_lo}; // @[TLB.scala:217:24] wire [30:0] sectored_entries_0_3_data_hi = {sectored_entries_0_3_data_hi_hi, sectored_entries_0_3_data_hi_lo}; // @[TLB.scala:217:24] wire [41:0] _sectored_entries_0_3_data_T = {sectored_entries_0_3_data_hi, sectored_entries_0_3_data_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_4_data_lo_lo_hi = {sectored_entries_0_4_data_lo_lo_hi_hi, newEntry_eff}; // @[TLB.scala:217:24, :449:24] wire [4:0] sectored_entries_0_4_data_lo_lo = {sectored_entries_0_4_data_lo_lo_hi, sectored_entries_0_4_data_lo_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_4_data_lo_hi_lo = {sectored_entries_0_4_data_lo_hi_lo_hi, newEntry_ppp}; // @[TLB.scala:217:24, :449:24] wire [2:0] sectored_entries_0_4_data_lo_hi_hi = {sectored_entries_0_4_data_lo_hi_hi_hi, newEntry_pw}; // @[TLB.scala:217:24, :449:24] wire [5:0] sectored_entries_0_4_data_lo_hi = {sectored_entries_0_4_data_lo_hi_hi, sectored_entries_0_4_data_lo_hi_lo}; // @[TLB.scala:217:24] wire [10:0] sectored_entries_0_4_data_lo = {sectored_entries_0_4_data_lo_hi, sectored_entries_0_4_data_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_4_data_hi_lo_lo = {sectored_entries_0_4_data_hi_lo_lo_hi, newEntry_hw}; // @[TLB.scala:217:24, :449:24] wire [2:0] sectored_entries_0_4_data_hi_lo_hi = {sectored_entries_0_4_data_hi_lo_hi_hi, newEntry_sw}; // @[TLB.scala:217:24, :449:24] wire [5:0] sectored_entries_0_4_data_hi_lo = {sectored_entries_0_4_data_hi_lo_hi, sectored_entries_0_4_data_hi_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_4_data_hi_hi_lo = {sectored_entries_0_4_data_hi_hi_lo_hi, 1'h0}; // @[TLB.scala:217:24] wire [21:0] sectored_entries_0_4_data_hi_hi_hi = {sectored_entries_0_4_data_hi_hi_hi_hi, newEntry_g}; // @[TLB.scala:217:24, :449:24] wire [24:0] sectored_entries_0_4_data_hi_hi = {sectored_entries_0_4_data_hi_hi_hi, sectored_entries_0_4_data_hi_hi_lo}; // @[TLB.scala:217:24] wire [30:0] sectored_entries_0_4_data_hi = {sectored_entries_0_4_data_hi_hi, sectored_entries_0_4_data_hi_lo}; // @[TLB.scala:217:24] wire [41:0] _sectored_entries_0_4_data_T = {sectored_entries_0_4_data_hi, sectored_entries_0_4_data_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_5_data_lo_lo_hi = {sectored_entries_0_5_data_lo_lo_hi_hi, newEntry_eff}; // @[TLB.scala:217:24, :449:24] wire [4:0] sectored_entries_0_5_data_lo_lo = {sectored_entries_0_5_data_lo_lo_hi, sectored_entries_0_5_data_lo_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_5_data_lo_hi_lo = {sectored_entries_0_5_data_lo_hi_lo_hi, newEntry_ppp}; // @[TLB.scala:217:24, :449:24] wire [2:0] sectored_entries_0_5_data_lo_hi_hi = {sectored_entries_0_5_data_lo_hi_hi_hi, newEntry_pw}; // @[TLB.scala:217:24, :449:24] wire [5:0] sectored_entries_0_5_data_lo_hi = {sectored_entries_0_5_data_lo_hi_hi, sectored_entries_0_5_data_lo_hi_lo}; // @[TLB.scala:217:24] wire [10:0] sectored_entries_0_5_data_lo = {sectored_entries_0_5_data_lo_hi, sectored_entries_0_5_data_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_5_data_hi_lo_lo = {sectored_entries_0_5_data_hi_lo_lo_hi, newEntry_hw}; // @[TLB.scala:217:24, :449:24] wire [2:0] sectored_entries_0_5_data_hi_lo_hi = {sectored_entries_0_5_data_hi_lo_hi_hi, newEntry_sw}; // @[TLB.scala:217:24, :449:24] wire [5:0] sectored_entries_0_5_data_hi_lo = {sectored_entries_0_5_data_hi_lo_hi, sectored_entries_0_5_data_hi_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_5_data_hi_hi_lo = {sectored_entries_0_5_data_hi_hi_lo_hi, 1'h0}; // @[TLB.scala:217:24] wire [21:0] sectored_entries_0_5_data_hi_hi_hi = {sectored_entries_0_5_data_hi_hi_hi_hi, newEntry_g}; // @[TLB.scala:217:24, :449:24] wire [24:0] sectored_entries_0_5_data_hi_hi = {sectored_entries_0_5_data_hi_hi_hi, sectored_entries_0_5_data_hi_hi_lo}; // @[TLB.scala:217:24] wire [30:0] sectored_entries_0_5_data_hi = {sectored_entries_0_5_data_hi_hi, sectored_entries_0_5_data_hi_lo}; // @[TLB.scala:217:24] wire [41:0] _sectored_entries_0_5_data_T = {sectored_entries_0_5_data_hi, sectored_entries_0_5_data_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_6_data_lo_lo_hi = {sectored_entries_0_6_data_lo_lo_hi_hi, newEntry_eff}; // @[TLB.scala:217:24, :449:24] wire [4:0] sectored_entries_0_6_data_lo_lo = {sectored_entries_0_6_data_lo_lo_hi, sectored_entries_0_6_data_lo_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_6_data_lo_hi_lo = {sectored_entries_0_6_data_lo_hi_lo_hi, newEntry_ppp}; // @[TLB.scala:217:24, :449:24] wire [2:0] sectored_entries_0_6_data_lo_hi_hi = {sectored_entries_0_6_data_lo_hi_hi_hi, newEntry_pw}; // @[TLB.scala:217:24, :449:24] wire [5:0] sectored_entries_0_6_data_lo_hi = {sectored_entries_0_6_data_lo_hi_hi, sectored_entries_0_6_data_lo_hi_lo}; // @[TLB.scala:217:24] wire [10:0] sectored_entries_0_6_data_lo = {sectored_entries_0_6_data_lo_hi, sectored_entries_0_6_data_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_6_data_hi_lo_lo = {sectored_entries_0_6_data_hi_lo_lo_hi, newEntry_hw}; // @[TLB.scala:217:24, :449:24] wire [2:0] sectored_entries_0_6_data_hi_lo_hi = {sectored_entries_0_6_data_hi_lo_hi_hi, newEntry_sw}; // @[TLB.scala:217:24, :449:24] wire [5:0] sectored_entries_0_6_data_hi_lo = {sectored_entries_0_6_data_hi_lo_hi, sectored_entries_0_6_data_hi_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_6_data_hi_hi_lo = {sectored_entries_0_6_data_hi_hi_lo_hi, 1'h0}; // @[TLB.scala:217:24] wire [21:0] sectored_entries_0_6_data_hi_hi_hi = {sectored_entries_0_6_data_hi_hi_hi_hi, newEntry_g}; // @[TLB.scala:217:24, :449:24] wire [24:0] sectored_entries_0_6_data_hi_hi = {sectored_entries_0_6_data_hi_hi_hi, sectored_entries_0_6_data_hi_hi_lo}; // @[TLB.scala:217:24] wire [30:0] sectored_entries_0_6_data_hi = {sectored_entries_0_6_data_hi_hi, sectored_entries_0_6_data_hi_lo}; // @[TLB.scala:217:24] wire [41:0] _sectored_entries_0_6_data_T = {sectored_entries_0_6_data_hi, sectored_entries_0_6_data_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_7_data_lo_lo_hi = {sectored_entries_0_7_data_lo_lo_hi_hi, newEntry_eff}; // @[TLB.scala:217:24, :449:24] wire [4:0] sectored_entries_0_7_data_lo_lo = {sectored_entries_0_7_data_lo_lo_hi, sectored_entries_0_7_data_lo_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_7_data_lo_hi_lo = {sectored_entries_0_7_data_lo_hi_lo_hi, newEntry_ppp}; // @[TLB.scala:217:24, :449:24] wire [2:0] sectored_entries_0_7_data_lo_hi_hi = {sectored_entries_0_7_data_lo_hi_hi_hi, newEntry_pw}; // @[TLB.scala:217:24, :449:24] wire [5:0] sectored_entries_0_7_data_lo_hi = {sectored_entries_0_7_data_lo_hi_hi, sectored_entries_0_7_data_lo_hi_lo}; // @[TLB.scala:217:24] wire [10:0] sectored_entries_0_7_data_lo = {sectored_entries_0_7_data_lo_hi, sectored_entries_0_7_data_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_7_data_hi_lo_lo = {sectored_entries_0_7_data_hi_lo_lo_hi, newEntry_hw}; // @[TLB.scala:217:24, :449:24] wire [2:0] sectored_entries_0_7_data_hi_lo_hi = {sectored_entries_0_7_data_hi_lo_hi_hi, newEntry_sw}; // @[TLB.scala:217:24, :449:24] wire [5:0] sectored_entries_0_7_data_hi_lo = {sectored_entries_0_7_data_hi_lo_hi, sectored_entries_0_7_data_hi_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_7_data_hi_hi_lo = {sectored_entries_0_7_data_hi_hi_lo_hi, 1'h0}; // @[TLB.scala:217:24] wire [21:0] sectored_entries_0_7_data_hi_hi_hi = {sectored_entries_0_7_data_hi_hi_hi_hi, newEntry_g}; // @[TLB.scala:217:24, :449:24] wire [24:0] sectored_entries_0_7_data_hi_hi = {sectored_entries_0_7_data_hi_hi_hi, sectored_entries_0_7_data_hi_hi_lo}; // @[TLB.scala:217:24] wire [30:0] sectored_entries_0_7_data_hi = {sectored_entries_0_7_data_hi_hi, sectored_entries_0_7_data_hi_lo}; // @[TLB.scala:217:24] wire [41:0] _sectored_entries_0_7_data_T = {sectored_entries_0_7_data_hi, sectored_entries_0_7_data_lo}; // @[TLB.scala:217:24] wire [19:0] _entries_T_23; // @[TLB.scala:170:77] wire _entries_T_22; // @[TLB.scala:170:77] wire _entries_T_21; // @[TLB.scala:170:77] wire _entries_T_20; // @[TLB.scala:170:77] wire _entries_T_19; // @[TLB.scala:170:77] wire _entries_T_18; // @[TLB.scala:170:77] wire _entries_T_17; // @[TLB.scala:170:77] wire _entries_T_16; // @[TLB.scala:170:77] wire _entries_T_15; // @[TLB.scala:170:77] wire _entries_T_14; // @[TLB.scala:170:77] wire _entries_T_13; // @[TLB.scala:170:77] wire _entries_T_12; // @[TLB.scala:170:77] wire _entries_T_11; // @[TLB.scala:170:77] wire _entries_T_10; // @[TLB.scala:170:77] wire _entries_T_9; // @[TLB.scala:170:77] wire _entries_T_8; // @[TLB.scala:170:77] wire _entries_T_7; // @[TLB.scala:170:77] wire _entries_T_6; // @[TLB.scala:170:77] wire _entries_T_5; // @[TLB.scala:170:77] wire _entries_T_4; // @[TLB.scala:170:77] wire _entries_T_3; // @[TLB.scala:170:77] wire _entries_T_2; // @[TLB.scala:170:77] wire _entries_T_1; // @[TLB.scala:170:77] wire [3:0][41:0] _GEN_32 = {{sectored_entries_0_0_data_3}, {sectored_entries_0_0_data_2}, {sectored_entries_0_0_data_1}, {sectored_entries_0_0_data_0}}; // @[TLB.scala:170:77, :339:29] wire [41:0] _entries_WIRE_1 = _GEN_32[_entries_T]; // @[package.scala:163:13] assign _entries_T_1 = _entries_WIRE_1[0]; // @[TLB.scala:170:77] wire _entries_WIRE_fragmented_superpage = _entries_T_1; // @[TLB.scala:170:77] assign _entries_T_2 = _entries_WIRE_1[1]; // @[TLB.scala:170:77] wire _entries_WIRE_c = _entries_T_2; // @[TLB.scala:170:77] assign _entries_T_3 = _entries_WIRE_1[2]; // @[TLB.scala:170:77] wire _entries_WIRE_eff = _entries_T_3; // @[TLB.scala:170:77] assign _entries_T_4 = _entries_WIRE_1[3]; // @[TLB.scala:170:77] wire _entries_WIRE_paa = _entries_T_4; // @[TLB.scala:170:77] assign _entries_T_5 = _entries_WIRE_1[4]; // @[TLB.scala:170:77] wire _entries_WIRE_pal = _entries_T_5; // @[TLB.scala:170:77] assign _entries_T_6 = _entries_WIRE_1[5]; // @[TLB.scala:170:77] wire _entries_WIRE_ppp = _entries_T_6; // @[TLB.scala:170:77] assign _entries_T_7 = _entries_WIRE_1[6]; // @[TLB.scala:170:77] wire _entries_WIRE_pr = _entries_T_7; // @[TLB.scala:170:77] assign _entries_T_8 = _entries_WIRE_1[7]; // @[TLB.scala:170:77] wire _entries_WIRE_px = _entries_T_8; // @[TLB.scala:170:77] assign _entries_T_9 = _entries_WIRE_1[8]; // @[TLB.scala:170:77] wire _entries_WIRE_pw = _entries_T_9; // @[TLB.scala:170:77] assign _entries_T_10 = _entries_WIRE_1[9]; // @[TLB.scala:170:77] wire _entries_WIRE_hr = _entries_T_10; // @[TLB.scala:170:77] assign _entries_T_11 = _entries_WIRE_1[10]; // @[TLB.scala:170:77] wire _entries_WIRE_hx = _entries_T_11; // @[TLB.scala:170:77] assign _entries_T_12 = _entries_WIRE_1[11]; // @[TLB.scala:170:77] wire _entries_WIRE_hw = _entries_T_12; // @[TLB.scala:170:77] assign _entries_T_13 = _entries_WIRE_1[12]; // @[TLB.scala:170:77] wire _entries_WIRE_sr = _entries_T_13; // @[TLB.scala:170:77] assign _entries_T_14 = _entries_WIRE_1[13]; // @[TLB.scala:170:77] wire _entries_WIRE_sx = _entries_T_14; // @[TLB.scala:170:77] assign _entries_T_15 = _entries_WIRE_1[14]; // @[TLB.scala:170:77] wire _entries_WIRE_sw = _entries_T_15; // @[TLB.scala:170:77] assign _entries_T_16 = _entries_WIRE_1[15]; // @[TLB.scala:170:77] wire _entries_WIRE_gf = _entries_T_16; // @[TLB.scala:170:77] assign _entries_T_17 = _entries_WIRE_1[16]; // @[TLB.scala:170:77] wire _entries_WIRE_pf = _entries_T_17; // @[TLB.scala:170:77] assign _entries_T_18 = _entries_WIRE_1[17]; // @[TLB.scala:170:77] wire _entries_WIRE_ae_stage2 = _entries_T_18; // @[TLB.scala:170:77] assign _entries_T_19 = _entries_WIRE_1[18]; // @[TLB.scala:170:77] wire _entries_WIRE_ae_final = _entries_T_19; // @[TLB.scala:170:77] assign _entries_T_20 = _entries_WIRE_1[19]; // @[TLB.scala:170:77] wire _entries_WIRE_ae_ptw = _entries_T_20; // @[TLB.scala:170:77] assign _entries_T_21 = _entries_WIRE_1[20]; // @[TLB.scala:170:77] wire _entries_WIRE_g = _entries_T_21; // @[TLB.scala:170:77] assign _entries_T_22 = _entries_WIRE_1[21]; // @[TLB.scala:170:77] wire _entries_WIRE_u = _entries_T_22; // @[TLB.scala:170:77] assign _entries_T_23 = _entries_WIRE_1[41:22]; // @[TLB.scala:170:77] wire [19:0] _entries_WIRE_ppn = _entries_T_23; // @[TLB.scala:170:77] wire [19:0] _entries_T_47; // @[TLB.scala:170:77] wire _entries_T_46; // @[TLB.scala:170:77] wire _entries_T_45; // @[TLB.scala:170:77] wire _entries_T_44; // @[TLB.scala:170:77] wire _entries_T_43; // @[TLB.scala:170:77] wire _entries_T_42; // @[TLB.scala:170:77] wire _entries_T_41; // @[TLB.scala:170:77] wire _entries_T_40; // @[TLB.scala:170:77] wire _entries_T_39; // @[TLB.scala:170:77] wire _entries_T_38; // @[TLB.scala:170:77] wire _entries_T_37; // @[TLB.scala:170:77] wire _entries_T_36; // @[TLB.scala:170:77] wire _entries_T_35; // @[TLB.scala:170:77] wire _entries_T_34; // @[TLB.scala:170:77] wire _entries_T_33; // @[TLB.scala:170:77] wire _entries_T_32; // @[TLB.scala:170:77] wire _entries_T_31; // @[TLB.scala:170:77] wire _entries_T_30; // @[TLB.scala:170:77] wire _entries_T_29; // @[TLB.scala:170:77] wire _entries_T_28; // @[TLB.scala:170:77] wire _entries_T_27; // @[TLB.scala:170:77] wire _entries_T_26; // @[TLB.scala:170:77] wire _entries_T_25; // @[TLB.scala:170:77] wire [3:0][41:0] _GEN_33 = {{sectored_entries_0_1_data_3}, {sectored_entries_0_1_data_2}, {sectored_entries_0_1_data_1}, {sectored_entries_0_1_data_0}}; // @[TLB.scala:170:77, :339:29] wire [41:0] _entries_WIRE_3 = _GEN_33[_entries_T_24]; // @[package.scala:163:13] assign _entries_T_25 = _entries_WIRE_3[0]; // @[TLB.scala:170:77] wire _entries_WIRE_2_fragmented_superpage = _entries_T_25; // @[TLB.scala:170:77] assign _entries_T_26 = _entries_WIRE_3[1]; // @[TLB.scala:170:77] wire _entries_WIRE_2_c = _entries_T_26; // @[TLB.scala:170:77] assign _entries_T_27 = _entries_WIRE_3[2]; // @[TLB.scala:170:77] wire _entries_WIRE_2_eff = _entries_T_27; // @[TLB.scala:170:77] assign _entries_T_28 = _entries_WIRE_3[3]; // @[TLB.scala:170:77] wire _entries_WIRE_2_paa = _entries_T_28; // @[TLB.scala:170:77] assign _entries_T_29 = _entries_WIRE_3[4]; // @[TLB.scala:170:77] wire _entries_WIRE_2_pal = _entries_T_29; // @[TLB.scala:170:77] assign _entries_T_30 = _entries_WIRE_3[5]; // @[TLB.scala:170:77] wire _entries_WIRE_2_ppp = _entries_T_30; // @[TLB.scala:170:77] assign _entries_T_31 = _entries_WIRE_3[6]; // @[TLB.scala:170:77] wire _entries_WIRE_2_pr = _entries_T_31; // @[TLB.scala:170:77] assign _entries_T_32 = _entries_WIRE_3[7]; // @[TLB.scala:170:77] wire _entries_WIRE_2_px = _entries_T_32; // @[TLB.scala:170:77] assign _entries_T_33 = _entries_WIRE_3[8]; // @[TLB.scala:170:77] wire _entries_WIRE_2_pw = _entries_T_33; // @[TLB.scala:170:77] assign _entries_T_34 = _entries_WIRE_3[9]; // @[TLB.scala:170:77] wire _entries_WIRE_2_hr = _entries_T_34; // @[TLB.scala:170:77] assign _entries_T_35 = _entries_WIRE_3[10]; // @[TLB.scala:170:77] wire _entries_WIRE_2_hx = _entries_T_35; // @[TLB.scala:170:77] assign _entries_T_36 = _entries_WIRE_3[11]; // @[TLB.scala:170:77] wire _entries_WIRE_2_hw = _entries_T_36; // @[TLB.scala:170:77] assign _entries_T_37 = _entries_WIRE_3[12]; // @[TLB.scala:170:77] wire _entries_WIRE_2_sr = _entries_T_37; // @[TLB.scala:170:77] assign _entries_T_38 = _entries_WIRE_3[13]; // @[TLB.scala:170:77] wire _entries_WIRE_2_sx = _entries_T_38; // @[TLB.scala:170:77] assign _entries_T_39 = _entries_WIRE_3[14]; // @[TLB.scala:170:77] wire _entries_WIRE_2_sw = _entries_T_39; // @[TLB.scala:170:77] assign _entries_T_40 = _entries_WIRE_3[15]; // @[TLB.scala:170:77] wire _entries_WIRE_2_gf = _entries_T_40; // @[TLB.scala:170:77] assign _entries_T_41 = _entries_WIRE_3[16]; // @[TLB.scala:170:77] wire _entries_WIRE_2_pf = _entries_T_41; // @[TLB.scala:170:77] assign _entries_T_42 = _entries_WIRE_3[17]; // @[TLB.scala:170:77] wire _entries_WIRE_2_ae_stage2 = _entries_T_42; // @[TLB.scala:170:77] assign _entries_T_43 = _entries_WIRE_3[18]; // @[TLB.scala:170:77] wire _entries_WIRE_2_ae_final = _entries_T_43; // @[TLB.scala:170:77] assign _entries_T_44 = _entries_WIRE_3[19]; // @[TLB.scala:170:77] wire _entries_WIRE_2_ae_ptw = _entries_T_44; // @[TLB.scala:170:77] assign _entries_T_45 = _entries_WIRE_3[20]; // @[TLB.scala:170:77] wire _entries_WIRE_2_g = _entries_T_45; // @[TLB.scala:170:77] assign _entries_T_46 = _entries_WIRE_3[21]; // @[TLB.scala:170:77] wire _entries_WIRE_2_u = _entries_T_46; // @[TLB.scala:170:77] assign _entries_T_47 = _entries_WIRE_3[41:22]; // @[TLB.scala:170:77] wire [19:0] _entries_WIRE_2_ppn = _entries_T_47; // @[TLB.scala:170:77] wire [19:0] _entries_T_71; // @[TLB.scala:170:77] wire _entries_T_70; // @[TLB.scala:170:77] wire _entries_T_69; // @[TLB.scala:170:77] wire _entries_T_68; // @[TLB.scala:170:77] wire _entries_T_67; // @[TLB.scala:170:77] wire _entries_T_66; // @[TLB.scala:170:77] wire _entries_T_65; // @[TLB.scala:170:77] wire _entries_T_64; // @[TLB.scala:170:77] wire _entries_T_63; // @[TLB.scala:170:77] wire _entries_T_62; // @[TLB.scala:170:77] wire _entries_T_61; // @[TLB.scala:170:77] wire _entries_T_60; // @[TLB.scala:170:77] wire _entries_T_59; // @[TLB.scala:170:77] wire _entries_T_58; // @[TLB.scala:170:77] wire _entries_T_57; // @[TLB.scala:170:77] wire _entries_T_56; // @[TLB.scala:170:77] wire _entries_T_55; // @[TLB.scala:170:77] wire _entries_T_54; // @[TLB.scala:170:77] wire _entries_T_53; // @[TLB.scala:170:77] wire _entries_T_52; // @[TLB.scala:170:77] wire _entries_T_51; // @[TLB.scala:170:77] wire _entries_T_50; // @[TLB.scala:170:77] wire _entries_T_49; // @[TLB.scala:170:77] wire [3:0][41:0] _GEN_34 = {{sectored_entries_0_2_data_3}, {sectored_entries_0_2_data_2}, {sectored_entries_0_2_data_1}, {sectored_entries_0_2_data_0}}; // @[TLB.scala:170:77, :339:29] wire [41:0] _entries_WIRE_5 = _GEN_34[_entries_T_48]; // @[package.scala:163:13] assign _entries_T_49 = _entries_WIRE_5[0]; // @[TLB.scala:170:77] wire _entries_WIRE_4_fragmented_superpage = _entries_T_49; // @[TLB.scala:170:77] assign _entries_T_50 = _entries_WIRE_5[1]; // @[TLB.scala:170:77] wire _entries_WIRE_4_c = _entries_T_50; // @[TLB.scala:170:77] assign _entries_T_51 = _entries_WIRE_5[2]; // @[TLB.scala:170:77] wire _entries_WIRE_4_eff = _entries_T_51; // @[TLB.scala:170:77] assign _entries_T_52 = _entries_WIRE_5[3]; // @[TLB.scala:170:77] wire _entries_WIRE_4_paa = _entries_T_52; // @[TLB.scala:170:77] assign _entries_T_53 = _entries_WIRE_5[4]; // @[TLB.scala:170:77] wire _entries_WIRE_4_pal = _entries_T_53; // @[TLB.scala:170:77] assign _entries_T_54 = _entries_WIRE_5[5]; // @[TLB.scala:170:77] wire _entries_WIRE_4_ppp = _entries_T_54; // @[TLB.scala:170:77] assign _entries_T_55 = _entries_WIRE_5[6]; // @[TLB.scala:170:77] wire _entries_WIRE_4_pr = _entries_T_55; // @[TLB.scala:170:77] assign _entries_T_56 = _entries_WIRE_5[7]; // @[TLB.scala:170:77] wire _entries_WIRE_4_px = _entries_T_56; // @[TLB.scala:170:77] assign _entries_T_57 = _entries_WIRE_5[8]; // @[TLB.scala:170:77] wire _entries_WIRE_4_pw = _entries_T_57; // @[TLB.scala:170:77] assign _entries_T_58 = _entries_WIRE_5[9]; // @[TLB.scala:170:77] wire _entries_WIRE_4_hr = _entries_T_58; // @[TLB.scala:170:77] assign _entries_T_59 = _entries_WIRE_5[10]; // @[TLB.scala:170:77] wire _entries_WIRE_4_hx = _entries_T_59; // @[TLB.scala:170:77] assign _entries_T_60 = _entries_WIRE_5[11]; // @[TLB.scala:170:77] wire _entries_WIRE_4_hw = _entries_T_60; // @[TLB.scala:170:77] assign _entries_T_61 = _entries_WIRE_5[12]; // @[TLB.scala:170:77] wire _entries_WIRE_4_sr = _entries_T_61; // @[TLB.scala:170:77] assign _entries_T_62 = _entries_WIRE_5[13]; // @[TLB.scala:170:77] wire _entries_WIRE_4_sx = _entries_T_62; // @[TLB.scala:170:77] assign _entries_T_63 = _entries_WIRE_5[14]; // @[TLB.scala:170:77] wire _entries_WIRE_4_sw = _entries_T_63; // @[TLB.scala:170:77] assign _entries_T_64 = _entries_WIRE_5[15]; // @[TLB.scala:170:77] wire _entries_WIRE_4_gf = _entries_T_64; // @[TLB.scala:170:77] assign _entries_T_65 = _entries_WIRE_5[16]; // @[TLB.scala:170:77] wire _entries_WIRE_4_pf = _entries_T_65; // @[TLB.scala:170:77] assign _entries_T_66 = _entries_WIRE_5[17]; // @[TLB.scala:170:77] wire _entries_WIRE_4_ae_stage2 = _entries_T_66; // @[TLB.scala:170:77] assign _entries_T_67 = _entries_WIRE_5[18]; // @[TLB.scala:170:77] wire _entries_WIRE_4_ae_final = _entries_T_67; // @[TLB.scala:170:77] assign _entries_T_68 = _entries_WIRE_5[19]; // @[TLB.scala:170:77] wire _entries_WIRE_4_ae_ptw = _entries_T_68; // @[TLB.scala:170:77] assign _entries_T_69 = _entries_WIRE_5[20]; // @[TLB.scala:170:77] wire _entries_WIRE_4_g = _entries_T_69; // @[TLB.scala:170:77] assign _entries_T_70 = _entries_WIRE_5[21]; // @[TLB.scala:170:77] wire _entries_WIRE_4_u = _entries_T_70; // @[TLB.scala:170:77] assign _entries_T_71 = _entries_WIRE_5[41:22]; // @[TLB.scala:170:77] wire [19:0] _entries_WIRE_4_ppn = _entries_T_71; // @[TLB.scala:170:77] wire [19:0] _entries_T_95; // @[TLB.scala:170:77] wire _entries_T_94; // @[TLB.scala:170:77] wire _entries_T_93; // @[TLB.scala:170:77] wire _entries_T_92; // @[TLB.scala:170:77] wire _entries_T_91; // @[TLB.scala:170:77] wire _entries_T_90; // @[TLB.scala:170:77] wire _entries_T_89; // @[TLB.scala:170:77] wire _entries_T_88; // @[TLB.scala:170:77] wire _entries_T_87; // @[TLB.scala:170:77] wire _entries_T_86; // @[TLB.scala:170:77] wire _entries_T_85; // @[TLB.scala:170:77] wire _entries_T_84; // @[TLB.scala:170:77] wire _entries_T_83; // @[TLB.scala:170:77] wire _entries_T_82; // @[TLB.scala:170:77] wire _entries_T_81; // @[TLB.scala:170:77] wire _entries_T_80; // @[TLB.scala:170:77] wire _entries_T_79; // @[TLB.scala:170:77] wire _entries_T_78; // @[TLB.scala:170:77] wire _entries_T_77; // @[TLB.scala:170:77] wire _entries_T_76; // @[TLB.scala:170:77] wire _entries_T_75; // @[TLB.scala:170:77] wire _entries_T_74; // @[TLB.scala:170:77] wire _entries_T_73; // @[TLB.scala:170:77] wire [3:0][41:0] _GEN_35 = {{sectored_entries_0_3_data_3}, {sectored_entries_0_3_data_2}, {sectored_entries_0_3_data_1}, {sectored_entries_0_3_data_0}}; // @[TLB.scala:170:77, :339:29] wire [41:0] _entries_WIRE_7 = _GEN_35[_entries_T_72]; // @[package.scala:163:13] assign _entries_T_73 = _entries_WIRE_7[0]; // @[TLB.scala:170:77] wire _entries_WIRE_6_fragmented_superpage = _entries_T_73; // @[TLB.scala:170:77] assign _entries_T_74 = _entries_WIRE_7[1]; // @[TLB.scala:170:77] wire _entries_WIRE_6_c = _entries_T_74; // @[TLB.scala:170:77] assign _entries_T_75 = _entries_WIRE_7[2]; // @[TLB.scala:170:77] wire _entries_WIRE_6_eff = _entries_T_75; // @[TLB.scala:170:77] assign _entries_T_76 = _entries_WIRE_7[3]; // @[TLB.scala:170:77] wire _entries_WIRE_6_paa = _entries_T_76; // @[TLB.scala:170:77] assign _entries_T_77 = _entries_WIRE_7[4]; // @[TLB.scala:170:77] wire _entries_WIRE_6_pal = _entries_T_77; // @[TLB.scala:170:77] assign _entries_T_78 = _entries_WIRE_7[5]; // @[TLB.scala:170:77] wire _entries_WIRE_6_ppp = _entries_T_78; // @[TLB.scala:170:77] assign _entries_T_79 = _entries_WIRE_7[6]; // @[TLB.scala:170:77] wire _entries_WIRE_6_pr = _entries_T_79; // @[TLB.scala:170:77] assign _entries_T_80 = _entries_WIRE_7[7]; // @[TLB.scala:170:77] wire _entries_WIRE_6_px = _entries_T_80; // @[TLB.scala:170:77] assign _entries_T_81 = _entries_WIRE_7[8]; // @[TLB.scala:170:77] wire _entries_WIRE_6_pw = _entries_T_81; // @[TLB.scala:170:77] assign _entries_T_82 = _entries_WIRE_7[9]; // @[TLB.scala:170:77] wire _entries_WIRE_6_hr = _entries_T_82; // @[TLB.scala:170:77] assign _entries_T_83 = _entries_WIRE_7[10]; // @[TLB.scala:170:77] wire _entries_WIRE_6_hx = _entries_T_83; // @[TLB.scala:170:77] assign _entries_T_84 = _entries_WIRE_7[11]; // @[TLB.scala:170:77] wire _entries_WIRE_6_hw = _entries_T_84; // @[TLB.scala:170:77] assign _entries_T_85 = _entries_WIRE_7[12]; // @[TLB.scala:170:77] wire _entries_WIRE_6_sr = _entries_T_85; // @[TLB.scala:170:77] assign _entries_T_86 = _entries_WIRE_7[13]; // @[TLB.scala:170:77] wire _entries_WIRE_6_sx = _entries_T_86; // @[TLB.scala:170:77] assign _entries_T_87 = _entries_WIRE_7[14]; // @[TLB.scala:170:77] wire _entries_WIRE_6_sw = _entries_T_87; // @[TLB.scala:170:77] assign _entries_T_88 = _entries_WIRE_7[15]; // @[TLB.scala:170:77] wire _entries_WIRE_6_gf = _entries_T_88; // @[TLB.scala:170:77] assign _entries_T_89 = _entries_WIRE_7[16]; // @[TLB.scala:170:77] wire _entries_WIRE_6_pf = _entries_T_89; // @[TLB.scala:170:77] assign _entries_T_90 = _entries_WIRE_7[17]; // @[TLB.scala:170:77] wire _entries_WIRE_6_ae_stage2 = _entries_T_90; // @[TLB.scala:170:77] assign _entries_T_91 = _entries_WIRE_7[18]; // @[TLB.scala:170:77] wire _entries_WIRE_6_ae_final = _entries_T_91; // @[TLB.scala:170:77] assign _entries_T_92 = _entries_WIRE_7[19]; // @[TLB.scala:170:77] wire _entries_WIRE_6_ae_ptw = _entries_T_92; // @[TLB.scala:170:77] assign _entries_T_93 = _entries_WIRE_7[20]; // @[TLB.scala:170:77] wire _entries_WIRE_6_g = _entries_T_93; // @[TLB.scala:170:77] assign _entries_T_94 = _entries_WIRE_7[21]; // @[TLB.scala:170:77] wire _entries_WIRE_6_u = _entries_T_94; // @[TLB.scala:170:77] assign _entries_T_95 = _entries_WIRE_7[41:22]; // @[TLB.scala:170:77] wire [19:0] _entries_WIRE_6_ppn = _entries_T_95; // @[TLB.scala:170:77] wire [19:0] _entries_T_119; // @[TLB.scala:170:77] wire _entries_T_118; // @[TLB.scala:170:77] wire _entries_T_117; // @[TLB.scala:170:77] wire _entries_T_116; // @[TLB.scala:170:77] wire _entries_T_115; // @[TLB.scala:170:77] wire _entries_T_114; // @[TLB.scala:170:77] wire _entries_T_113; // @[TLB.scala:170:77] wire _entries_T_112; // @[TLB.scala:170:77] wire _entries_T_111; // @[TLB.scala:170:77] wire _entries_T_110; // @[TLB.scala:170:77] wire _entries_T_109; // @[TLB.scala:170:77] wire _entries_T_108; // @[TLB.scala:170:77] wire _entries_T_107; // @[TLB.scala:170:77] wire _entries_T_106; // @[TLB.scala:170:77] wire _entries_T_105; // @[TLB.scala:170:77] wire _entries_T_104; // @[TLB.scala:170:77] wire _entries_T_103; // @[TLB.scala:170:77] wire _entries_T_102; // @[TLB.scala:170:77] wire _entries_T_101; // @[TLB.scala:170:77] wire _entries_T_100; // @[TLB.scala:170:77] wire _entries_T_99; // @[TLB.scala:170:77] wire _entries_T_98; // @[TLB.scala:170:77] wire _entries_T_97; // @[TLB.scala:170:77] wire [3:0][41:0] _GEN_36 = {{sectored_entries_0_4_data_3}, {sectored_entries_0_4_data_2}, {sectored_entries_0_4_data_1}, {sectored_entries_0_4_data_0}}; // @[TLB.scala:170:77, :339:29] wire [41:0] _entries_WIRE_9 = _GEN_36[_entries_T_96]; // @[package.scala:163:13] assign _entries_T_97 = _entries_WIRE_9[0]; // @[TLB.scala:170:77] wire _entries_WIRE_8_fragmented_superpage = _entries_T_97; // @[TLB.scala:170:77] assign _entries_T_98 = _entries_WIRE_9[1]; // @[TLB.scala:170:77] wire _entries_WIRE_8_c = _entries_T_98; // @[TLB.scala:170:77] assign _entries_T_99 = _entries_WIRE_9[2]; // @[TLB.scala:170:77] wire _entries_WIRE_8_eff = _entries_T_99; // @[TLB.scala:170:77] assign _entries_T_100 = _entries_WIRE_9[3]; // @[TLB.scala:170:77] wire _entries_WIRE_8_paa = _entries_T_100; // @[TLB.scala:170:77] assign _entries_T_101 = _entries_WIRE_9[4]; // @[TLB.scala:170:77] wire _entries_WIRE_8_pal = _entries_T_101; // @[TLB.scala:170:77] assign _entries_T_102 = _entries_WIRE_9[5]; // @[TLB.scala:170:77] wire _entries_WIRE_8_ppp = _entries_T_102; // @[TLB.scala:170:77] assign _entries_T_103 = _entries_WIRE_9[6]; // @[TLB.scala:170:77] wire _entries_WIRE_8_pr = _entries_T_103; // @[TLB.scala:170:77] assign _entries_T_104 = _entries_WIRE_9[7]; // @[TLB.scala:170:77] wire _entries_WIRE_8_px = _entries_T_104; // @[TLB.scala:170:77] assign _entries_T_105 = _entries_WIRE_9[8]; // @[TLB.scala:170:77] wire _entries_WIRE_8_pw = _entries_T_105; // @[TLB.scala:170:77] assign _entries_T_106 = _entries_WIRE_9[9]; // @[TLB.scala:170:77] wire _entries_WIRE_8_hr = _entries_T_106; // @[TLB.scala:170:77] assign _entries_T_107 = _entries_WIRE_9[10]; // @[TLB.scala:170:77] wire _entries_WIRE_8_hx = _entries_T_107; // @[TLB.scala:170:77] assign _entries_T_108 = _entries_WIRE_9[11]; // @[TLB.scala:170:77] wire _entries_WIRE_8_hw = _entries_T_108; // @[TLB.scala:170:77] assign _entries_T_109 = _entries_WIRE_9[12]; // @[TLB.scala:170:77] wire _entries_WIRE_8_sr = _entries_T_109; // @[TLB.scala:170:77] assign _entries_T_110 = _entries_WIRE_9[13]; // @[TLB.scala:170:77] wire _entries_WIRE_8_sx = _entries_T_110; // @[TLB.scala:170:77] assign _entries_T_111 = _entries_WIRE_9[14]; // @[TLB.scala:170:77] wire _entries_WIRE_8_sw = _entries_T_111; // @[TLB.scala:170:77] assign _entries_T_112 = _entries_WIRE_9[15]; // @[TLB.scala:170:77] wire _entries_WIRE_8_gf = _entries_T_112; // @[TLB.scala:170:77] assign _entries_T_113 = _entries_WIRE_9[16]; // @[TLB.scala:170:77] wire _entries_WIRE_8_pf = _entries_T_113; // @[TLB.scala:170:77] assign _entries_T_114 = _entries_WIRE_9[17]; // @[TLB.scala:170:77] wire _entries_WIRE_8_ae_stage2 = _entries_T_114; // @[TLB.scala:170:77] assign _entries_T_115 = _entries_WIRE_9[18]; // @[TLB.scala:170:77] wire _entries_WIRE_8_ae_final = _entries_T_115; // @[TLB.scala:170:77] assign _entries_T_116 = _entries_WIRE_9[19]; // @[TLB.scala:170:77] wire _entries_WIRE_8_ae_ptw = _entries_T_116; // @[TLB.scala:170:77] assign _entries_T_117 = _entries_WIRE_9[20]; // @[TLB.scala:170:77] wire _entries_WIRE_8_g = _entries_T_117; // @[TLB.scala:170:77] assign _entries_T_118 = _entries_WIRE_9[21]; // @[TLB.scala:170:77] wire _entries_WIRE_8_u = _entries_T_118; // @[TLB.scala:170:77] assign _entries_T_119 = _entries_WIRE_9[41:22]; // @[TLB.scala:170:77] wire [19:0] _entries_WIRE_8_ppn = _entries_T_119; // @[TLB.scala:170:77] wire [19:0] _entries_T_143; // @[TLB.scala:170:77] wire _entries_T_142; // @[TLB.scala:170:77] wire _entries_T_141; // @[TLB.scala:170:77] wire _entries_T_140; // @[TLB.scala:170:77] wire _entries_T_139; // @[TLB.scala:170:77] wire _entries_T_138; // @[TLB.scala:170:77] wire _entries_T_137; // @[TLB.scala:170:77] wire _entries_T_136; // @[TLB.scala:170:77] wire _entries_T_135; // @[TLB.scala:170:77] wire _entries_T_134; // @[TLB.scala:170:77] wire _entries_T_133; // @[TLB.scala:170:77] wire _entries_T_132; // @[TLB.scala:170:77] wire _entries_T_131; // @[TLB.scala:170:77] wire _entries_T_130; // @[TLB.scala:170:77] wire _entries_T_129; // @[TLB.scala:170:77] wire _entries_T_128; // @[TLB.scala:170:77] wire _entries_T_127; // @[TLB.scala:170:77] wire _entries_T_126; // @[TLB.scala:170:77] wire _entries_T_125; // @[TLB.scala:170:77] wire _entries_T_124; // @[TLB.scala:170:77] wire _entries_T_123; // @[TLB.scala:170:77] wire _entries_T_122; // @[TLB.scala:170:77] wire _entries_T_121; // @[TLB.scala:170:77] wire [3:0][41:0] _GEN_37 = {{sectored_entries_0_5_data_3}, {sectored_entries_0_5_data_2}, {sectored_entries_0_5_data_1}, {sectored_entries_0_5_data_0}}; // @[TLB.scala:170:77, :339:29] wire [41:0] _entries_WIRE_11 = _GEN_37[_entries_T_120]; // @[package.scala:163:13] assign _entries_T_121 = _entries_WIRE_11[0]; // @[TLB.scala:170:77] wire _entries_WIRE_10_fragmented_superpage = _entries_T_121; // @[TLB.scala:170:77] assign _entries_T_122 = _entries_WIRE_11[1]; // @[TLB.scala:170:77] wire _entries_WIRE_10_c = _entries_T_122; // @[TLB.scala:170:77] assign _entries_T_123 = _entries_WIRE_11[2]; // @[TLB.scala:170:77] wire _entries_WIRE_10_eff = _entries_T_123; // @[TLB.scala:170:77] assign _entries_T_124 = _entries_WIRE_11[3]; // @[TLB.scala:170:77] wire _entries_WIRE_10_paa = _entries_T_124; // @[TLB.scala:170:77] assign _entries_T_125 = _entries_WIRE_11[4]; // @[TLB.scala:170:77] wire _entries_WIRE_10_pal = _entries_T_125; // @[TLB.scala:170:77] assign _entries_T_126 = _entries_WIRE_11[5]; // @[TLB.scala:170:77] wire _entries_WIRE_10_ppp = _entries_T_126; // @[TLB.scala:170:77] assign _entries_T_127 = _entries_WIRE_11[6]; // @[TLB.scala:170:77] wire _entries_WIRE_10_pr = _entries_T_127; // @[TLB.scala:170:77] assign _entries_T_128 = _entries_WIRE_11[7]; // @[TLB.scala:170:77] wire _entries_WIRE_10_px = _entries_T_128; // @[TLB.scala:170:77] assign _entries_T_129 = _entries_WIRE_11[8]; // @[TLB.scala:170:77] wire _entries_WIRE_10_pw = _entries_T_129; // @[TLB.scala:170:77] assign _entries_T_130 = _entries_WIRE_11[9]; // @[TLB.scala:170:77] wire _entries_WIRE_10_hr = _entries_T_130; // @[TLB.scala:170:77] assign _entries_T_131 = _entries_WIRE_11[10]; // @[TLB.scala:170:77] wire _entries_WIRE_10_hx = _entries_T_131; // @[TLB.scala:170:77] assign _entries_T_132 = _entries_WIRE_11[11]; // @[TLB.scala:170:77] wire _entries_WIRE_10_hw = _entries_T_132; // @[TLB.scala:170:77] assign _entries_T_133 = _entries_WIRE_11[12]; // @[TLB.scala:170:77] wire _entries_WIRE_10_sr = _entries_T_133; // @[TLB.scala:170:77] assign _entries_T_134 = _entries_WIRE_11[13]; // @[TLB.scala:170:77] wire _entries_WIRE_10_sx = _entries_T_134; // @[TLB.scala:170:77] assign _entries_T_135 = _entries_WIRE_11[14]; // @[TLB.scala:170:77] wire _entries_WIRE_10_sw = _entries_T_135; // @[TLB.scala:170:77] assign _entries_T_136 = _entries_WIRE_11[15]; // @[TLB.scala:170:77] wire _entries_WIRE_10_gf = _entries_T_136; // @[TLB.scala:170:77] assign _entries_T_137 = _entries_WIRE_11[16]; // @[TLB.scala:170:77] wire _entries_WIRE_10_pf = _entries_T_137; // @[TLB.scala:170:77] assign _entries_T_138 = _entries_WIRE_11[17]; // @[TLB.scala:170:77] wire _entries_WIRE_10_ae_stage2 = _entries_T_138; // @[TLB.scala:170:77] assign _entries_T_139 = _entries_WIRE_11[18]; // @[TLB.scala:170:77] wire _entries_WIRE_10_ae_final = _entries_T_139; // @[TLB.scala:170:77] assign _entries_T_140 = _entries_WIRE_11[19]; // @[TLB.scala:170:77] wire _entries_WIRE_10_ae_ptw = _entries_T_140; // @[TLB.scala:170:77] assign _entries_T_141 = _entries_WIRE_11[20]; // @[TLB.scala:170:77] wire _entries_WIRE_10_g = _entries_T_141; // @[TLB.scala:170:77] assign _entries_T_142 = _entries_WIRE_11[21]; // @[TLB.scala:170:77] wire _entries_WIRE_10_u = _entries_T_142; // @[TLB.scala:170:77] assign _entries_T_143 = _entries_WIRE_11[41:22]; // @[TLB.scala:170:77] wire [19:0] _entries_WIRE_10_ppn = _entries_T_143; // @[TLB.scala:170:77] wire [19:0] _entries_T_167; // @[TLB.scala:170:77] wire _entries_T_166; // @[TLB.scala:170:77] wire _entries_T_165; // @[TLB.scala:170:77] wire _entries_T_164; // @[TLB.scala:170:77] wire _entries_T_163; // @[TLB.scala:170:77] wire _entries_T_162; // @[TLB.scala:170:77] wire _entries_T_161; // @[TLB.scala:170:77] wire _entries_T_160; // @[TLB.scala:170:77] wire _entries_T_159; // @[TLB.scala:170:77] wire _entries_T_158; // @[TLB.scala:170:77] wire _entries_T_157; // @[TLB.scala:170:77] wire _entries_T_156; // @[TLB.scala:170:77] wire _entries_T_155; // @[TLB.scala:170:77] wire _entries_T_154; // @[TLB.scala:170:77] wire _entries_T_153; // @[TLB.scala:170:77] wire _entries_T_152; // @[TLB.scala:170:77] wire _entries_T_151; // @[TLB.scala:170:77] wire _entries_T_150; // @[TLB.scala:170:77] wire _entries_T_149; // @[TLB.scala:170:77] wire _entries_T_148; // @[TLB.scala:170:77] wire _entries_T_147; // @[TLB.scala:170:77] wire _entries_T_146; // @[TLB.scala:170:77] wire _entries_T_145; // @[TLB.scala:170:77] wire [3:0][41:0] _GEN_38 = {{sectored_entries_0_6_data_3}, {sectored_entries_0_6_data_2}, {sectored_entries_0_6_data_1}, {sectored_entries_0_6_data_0}}; // @[TLB.scala:170:77, :339:29] wire [41:0] _entries_WIRE_13 = _GEN_38[_entries_T_144]; // @[package.scala:163:13] assign _entries_T_145 = _entries_WIRE_13[0]; // @[TLB.scala:170:77] wire _entries_WIRE_12_fragmented_superpage = _entries_T_145; // @[TLB.scala:170:77] assign _entries_T_146 = _entries_WIRE_13[1]; // @[TLB.scala:170:77] wire _entries_WIRE_12_c = _entries_T_146; // @[TLB.scala:170:77] assign _entries_T_147 = _entries_WIRE_13[2]; // @[TLB.scala:170:77] wire _entries_WIRE_12_eff = _entries_T_147; // @[TLB.scala:170:77] assign _entries_T_148 = _entries_WIRE_13[3]; // @[TLB.scala:170:77] wire _entries_WIRE_12_paa = _entries_T_148; // @[TLB.scala:170:77] assign _entries_T_149 = _entries_WIRE_13[4]; // @[TLB.scala:170:77] wire _entries_WIRE_12_pal = _entries_T_149; // @[TLB.scala:170:77] assign _entries_T_150 = _entries_WIRE_13[5]; // @[TLB.scala:170:77] wire _entries_WIRE_12_ppp = _entries_T_150; // @[TLB.scala:170:77] assign _entries_T_151 = _entries_WIRE_13[6]; // @[TLB.scala:170:77] wire _entries_WIRE_12_pr = _entries_T_151; // @[TLB.scala:170:77] assign _entries_T_152 = _entries_WIRE_13[7]; // @[TLB.scala:170:77] wire _entries_WIRE_12_px = _entries_T_152; // @[TLB.scala:170:77] assign _entries_T_153 = _entries_WIRE_13[8]; // @[TLB.scala:170:77] wire _entries_WIRE_12_pw = _entries_T_153; // @[TLB.scala:170:77] assign _entries_T_154 = _entries_WIRE_13[9]; // @[TLB.scala:170:77] wire _entries_WIRE_12_hr = _entries_T_154; // @[TLB.scala:170:77] assign _entries_T_155 = _entries_WIRE_13[10]; // @[TLB.scala:170:77] wire _entries_WIRE_12_hx = _entries_T_155; // @[TLB.scala:170:77] assign _entries_T_156 = _entries_WIRE_13[11]; // @[TLB.scala:170:77] wire _entries_WIRE_12_hw = _entries_T_156; // @[TLB.scala:170:77] assign _entries_T_157 = _entries_WIRE_13[12]; // @[TLB.scala:170:77] wire _entries_WIRE_12_sr = _entries_T_157; // @[TLB.scala:170:77] assign _entries_T_158 = _entries_WIRE_13[13]; // @[TLB.scala:170:77] wire _entries_WIRE_12_sx = _entries_T_158; // @[TLB.scala:170:77] assign _entries_T_159 = _entries_WIRE_13[14]; // @[TLB.scala:170:77] wire _entries_WIRE_12_sw = _entries_T_159; // @[TLB.scala:170:77] assign _entries_T_160 = _entries_WIRE_13[15]; // @[TLB.scala:170:77] wire _entries_WIRE_12_gf = _entries_T_160; // @[TLB.scala:170:77] assign _entries_T_161 = _entries_WIRE_13[16]; // @[TLB.scala:170:77] wire _entries_WIRE_12_pf = _entries_T_161; // @[TLB.scala:170:77] assign _entries_T_162 = _entries_WIRE_13[17]; // @[TLB.scala:170:77] wire _entries_WIRE_12_ae_stage2 = _entries_T_162; // @[TLB.scala:170:77] assign _entries_T_163 = _entries_WIRE_13[18]; // @[TLB.scala:170:77] wire _entries_WIRE_12_ae_final = _entries_T_163; // @[TLB.scala:170:77] assign _entries_T_164 = _entries_WIRE_13[19]; // @[TLB.scala:170:77] wire _entries_WIRE_12_ae_ptw = _entries_T_164; // @[TLB.scala:170:77] assign _entries_T_165 = _entries_WIRE_13[20]; // @[TLB.scala:170:77] wire _entries_WIRE_12_g = _entries_T_165; // @[TLB.scala:170:77] assign _entries_T_166 = _entries_WIRE_13[21]; // @[TLB.scala:170:77] wire _entries_WIRE_12_u = _entries_T_166; // @[TLB.scala:170:77] assign _entries_T_167 = _entries_WIRE_13[41:22]; // @[TLB.scala:170:77] wire [19:0] _entries_WIRE_12_ppn = _entries_T_167; // @[TLB.scala:170:77] wire [19:0] _entries_T_191; // @[TLB.scala:170:77] wire _entries_T_190; // @[TLB.scala:170:77] wire _entries_T_189; // @[TLB.scala:170:77] wire _entries_T_188; // @[TLB.scala:170:77] wire _entries_T_187; // @[TLB.scala:170:77] wire _entries_T_186; // @[TLB.scala:170:77] wire _entries_T_185; // @[TLB.scala:170:77] wire _entries_T_184; // @[TLB.scala:170:77] wire _entries_T_183; // @[TLB.scala:170:77] wire _entries_T_182; // @[TLB.scala:170:77] wire _entries_T_181; // @[TLB.scala:170:77] wire _entries_T_180; // @[TLB.scala:170:77] wire _entries_T_179; // @[TLB.scala:170:77] wire _entries_T_178; // @[TLB.scala:170:77] wire _entries_T_177; // @[TLB.scala:170:77] wire _entries_T_176; // @[TLB.scala:170:77] wire _entries_T_175; // @[TLB.scala:170:77] wire _entries_T_174; // @[TLB.scala:170:77] wire _entries_T_173; // @[TLB.scala:170:77] wire _entries_T_172; // @[TLB.scala:170:77] wire _entries_T_171; // @[TLB.scala:170:77] wire _entries_T_170; // @[TLB.scala:170:77] wire _entries_T_169; // @[TLB.scala:170:77] wire [3:0][41:0] _GEN_39 = {{sectored_entries_0_7_data_3}, {sectored_entries_0_7_data_2}, {sectored_entries_0_7_data_1}, {sectored_entries_0_7_data_0}}; // @[TLB.scala:170:77, :339:29] wire [41:0] _entries_WIRE_15 = _GEN_39[_entries_T_168]; // @[package.scala:163:13] assign _entries_T_169 = _entries_WIRE_15[0]; // @[TLB.scala:170:77] wire _entries_WIRE_14_fragmented_superpage = _entries_T_169; // @[TLB.scala:170:77] assign _entries_T_170 = _entries_WIRE_15[1]; // @[TLB.scala:170:77] wire _entries_WIRE_14_c = _entries_T_170; // @[TLB.scala:170:77] assign _entries_T_171 = _entries_WIRE_15[2]; // @[TLB.scala:170:77] wire _entries_WIRE_14_eff = _entries_T_171; // @[TLB.scala:170:77] assign _entries_T_172 = _entries_WIRE_15[3]; // @[TLB.scala:170:77] wire _entries_WIRE_14_paa = _entries_T_172; // @[TLB.scala:170:77] assign _entries_T_173 = _entries_WIRE_15[4]; // @[TLB.scala:170:77] wire _entries_WIRE_14_pal = _entries_T_173; // @[TLB.scala:170:77] assign _entries_T_174 = _entries_WIRE_15[5]; // @[TLB.scala:170:77] wire _entries_WIRE_14_ppp = _entries_T_174; // @[TLB.scala:170:77] assign _entries_T_175 = _entries_WIRE_15[6]; // @[TLB.scala:170:77] wire _entries_WIRE_14_pr = _entries_T_175; // @[TLB.scala:170:77] assign _entries_T_176 = _entries_WIRE_15[7]; // @[TLB.scala:170:77] wire _entries_WIRE_14_px = _entries_T_176; // @[TLB.scala:170:77] assign _entries_T_177 = _entries_WIRE_15[8]; // @[TLB.scala:170:77] wire _entries_WIRE_14_pw = _entries_T_177; // @[TLB.scala:170:77] assign _entries_T_178 = _entries_WIRE_15[9]; // @[TLB.scala:170:77] wire _entries_WIRE_14_hr = _entries_T_178; // @[TLB.scala:170:77] assign _entries_T_179 = _entries_WIRE_15[10]; // @[TLB.scala:170:77] wire _entries_WIRE_14_hx = _entries_T_179; // @[TLB.scala:170:77] assign _entries_T_180 = _entries_WIRE_15[11]; // @[TLB.scala:170:77] wire _entries_WIRE_14_hw = _entries_T_180; // @[TLB.scala:170:77] assign _entries_T_181 = _entries_WIRE_15[12]; // @[TLB.scala:170:77] wire _entries_WIRE_14_sr = _entries_T_181; // @[TLB.scala:170:77] assign _entries_T_182 = _entries_WIRE_15[13]; // @[TLB.scala:170:77] wire _entries_WIRE_14_sx = _entries_T_182; // @[TLB.scala:170:77] assign _entries_T_183 = _entries_WIRE_15[14]; // @[TLB.scala:170:77] wire _entries_WIRE_14_sw = _entries_T_183; // @[TLB.scala:170:77] assign _entries_T_184 = _entries_WIRE_15[15]; // @[TLB.scala:170:77] wire _entries_WIRE_14_gf = _entries_T_184; // @[TLB.scala:170:77] assign _entries_T_185 = _entries_WIRE_15[16]; // @[TLB.scala:170:77] wire _entries_WIRE_14_pf = _entries_T_185; // @[TLB.scala:170:77] assign _entries_T_186 = _entries_WIRE_15[17]; // @[TLB.scala:170:77] wire _entries_WIRE_14_ae_stage2 = _entries_T_186; // @[TLB.scala:170:77] assign _entries_T_187 = _entries_WIRE_15[18]; // @[TLB.scala:170:77] wire _entries_WIRE_14_ae_final = _entries_T_187; // @[TLB.scala:170:77] assign _entries_T_188 = _entries_WIRE_15[19]; // @[TLB.scala:170:77] wire _entries_WIRE_14_ae_ptw = _entries_T_188; // @[TLB.scala:170:77] assign _entries_T_189 = _entries_WIRE_15[20]; // @[TLB.scala:170:77] wire _entries_WIRE_14_g = _entries_T_189; // @[TLB.scala:170:77] assign _entries_T_190 = _entries_WIRE_15[21]; // @[TLB.scala:170:77] wire _entries_WIRE_14_u = _entries_T_190; // @[TLB.scala:170:77] assign _entries_T_191 = _entries_WIRE_15[41:22]; // @[TLB.scala:170:77] wire [19:0] _entries_WIRE_14_ppn = _entries_T_191; // @[TLB.scala:170:77] wire [19:0] _entries_T_214; // @[TLB.scala:170:77] wire _entries_T_213; // @[TLB.scala:170:77] wire _entries_T_212; // @[TLB.scala:170:77] wire _entries_T_211; // @[TLB.scala:170:77] wire _entries_T_210; // @[TLB.scala:170:77] wire _entries_T_209; // @[TLB.scala:170:77] wire _entries_T_208; // @[TLB.scala:170:77] wire _entries_T_207; // @[TLB.scala:170:77] wire _entries_T_206; // @[TLB.scala:170:77] wire _entries_T_205; // @[TLB.scala:170:77] wire _entries_T_204; // @[TLB.scala:170:77] wire _entries_T_203; // @[TLB.scala:170:77] wire _entries_T_202; // @[TLB.scala:170:77] wire _entries_T_201; // @[TLB.scala:170:77] wire _entries_T_200; // @[TLB.scala:170:77] wire _entries_T_199; // @[TLB.scala:170:77] wire _entries_T_198; // @[TLB.scala:170:77] wire _entries_T_197; // @[TLB.scala:170:77] wire _entries_T_196; // @[TLB.scala:170:77] wire _entries_T_195; // @[TLB.scala:170:77] wire _entries_T_194; // @[TLB.scala:170:77] wire _entries_T_193; // @[TLB.scala:170:77] wire _entries_T_192; // @[TLB.scala:170:77] assign _entries_T_192 = _entries_WIRE_17[0]; // @[TLB.scala:170:77] wire _entries_WIRE_16_fragmented_superpage = _entries_T_192; // @[TLB.scala:170:77] assign _entries_T_193 = _entries_WIRE_17[1]; // @[TLB.scala:170:77] wire _entries_WIRE_16_c = _entries_T_193; // @[TLB.scala:170:77] assign _entries_T_194 = _entries_WIRE_17[2]; // @[TLB.scala:170:77] wire _entries_WIRE_16_eff = _entries_T_194; // @[TLB.scala:170:77] assign _entries_T_195 = _entries_WIRE_17[3]; // @[TLB.scala:170:77] wire _entries_WIRE_16_paa = _entries_T_195; // @[TLB.scala:170:77] assign _entries_T_196 = _entries_WIRE_17[4]; // @[TLB.scala:170:77] wire _entries_WIRE_16_pal = _entries_T_196; // @[TLB.scala:170:77] assign _entries_T_197 = _entries_WIRE_17[5]; // @[TLB.scala:170:77] wire _entries_WIRE_16_ppp = _entries_T_197; // @[TLB.scala:170:77] assign _entries_T_198 = _entries_WIRE_17[6]; // @[TLB.scala:170:77] wire _entries_WIRE_16_pr = _entries_T_198; // @[TLB.scala:170:77] assign _entries_T_199 = _entries_WIRE_17[7]; // @[TLB.scala:170:77] wire _entries_WIRE_16_px = _entries_T_199; // @[TLB.scala:170:77] assign _entries_T_200 = _entries_WIRE_17[8]; // @[TLB.scala:170:77] wire _entries_WIRE_16_pw = _entries_T_200; // @[TLB.scala:170:77] assign _entries_T_201 = _entries_WIRE_17[9]; // @[TLB.scala:170:77] wire _entries_WIRE_16_hr = _entries_T_201; // @[TLB.scala:170:77] assign _entries_T_202 = _entries_WIRE_17[10]; // @[TLB.scala:170:77] wire _entries_WIRE_16_hx = _entries_T_202; // @[TLB.scala:170:77] assign _entries_T_203 = _entries_WIRE_17[11]; // @[TLB.scala:170:77] wire _entries_WIRE_16_hw = _entries_T_203; // @[TLB.scala:170:77] assign _entries_T_204 = _entries_WIRE_17[12]; // @[TLB.scala:170:77] wire _entries_WIRE_16_sr = _entries_T_204; // @[TLB.scala:170:77] assign _entries_T_205 = _entries_WIRE_17[13]; // @[TLB.scala:170:77] wire _entries_WIRE_16_sx = _entries_T_205; // @[TLB.scala:170:77] assign _entries_T_206 = _entries_WIRE_17[14]; // @[TLB.scala:170:77] wire _entries_WIRE_16_sw = _entries_T_206; // @[TLB.scala:170:77] assign _entries_T_207 = _entries_WIRE_17[15]; // @[TLB.scala:170:77] wire _entries_WIRE_16_gf = _entries_T_207; // @[TLB.scala:170:77] assign _entries_T_208 = _entries_WIRE_17[16]; // @[TLB.scala:170:77] wire _entries_WIRE_16_pf = _entries_T_208; // @[TLB.scala:170:77] assign _entries_T_209 = _entries_WIRE_17[17]; // @[TLB.scala:170:77] wire _entries_WIRE_16_ae_stage2 = _entries_T_209; // @[TLB.scala:170:77] assign _entries_T_210 = _entries_WIRE_17[18]; // @[TLB.scala:170:77] wire _entries_WIRE_16_ae_final = _entries_T_210; // @[TLB.scala:170:77] assign _entries_T_211 = _entries_WIRE_17[19]; // @[TLB.scala:170:77] wire _entries_WIRE_16_ae_ptw = _entries_T_211; // @[TLB.scala:170:77] assign _entries_T_212 = _entries_WIRE_17[20]; // @[TLB.scala:170:77] wire _entries_WIRE_16_g = _entries_T_212; // @[TLB.scala:170:77] assign _entries_T_213 = _entries_WIRE_17[21]; // @[TLB.scala:170:77] wire _entries_WIRE_16_u = _entries_T_213; // @[TLB.scala:170:77] assign _entries_T_214 = _entries_WIRE_17[41:22]; // @[TLB.scala:170:77] wire [19:0] _entries_WIRE_16_ppn = _entries_T_214; // @[TLB.scala:170:77] wire [19:0] _entries_T_237; // @[TLB.scala:170:77] wire _entries_T_236; // @[TLB.scala:170:77] wire _entries_T_235; // @[TLB.scala:170:77] wire _entries_T_234; // @[TLB.scala:170:77] wire _entries_T_233; // @[TLB.scala:170:77] wire _entries_T_232; // @[TLB.scala:170:77] wire _entries_T_231; // @[TLB.scala:170:77] wire _entries_T_230; // @[TLB.scala:170:77] wire _entries_T_229; // @[TLB.scala:170:77] wire _entries_T_228; // @[TLB.scala:170:77] wire _entries_T_227; // @[TLB.scala:170:77] wire _entries_T_226; // @[TLB.scala:170:77] wire _entries_T_225; // @[TLB.scala:170:77] wire _entries_T_224; // @[TLB.scala:170:77] wire _entries_T_223; // @[TLB.scala:170:77] wire _entries_T_222; // @[TLB.scala:170:77] wire _entries_T_221; // @[TLB.scala:170:77] wire _entries_T_220; // @[TLB.scala:170:77] wire _entries_T_219; // @[TLB.scala:170:77] wire _entries_T_218; // @[TLB.scala:170:77] wire _entries_T_217; // @[TLB.scala:170:77] wire _entries_T_216; // @[TLB.scala:170:77] wire _entries_T_215; // @[TLB.scala:170:77] assign _entries_T_215 = _entries_WIRE_19[0]; // @[TLB.scala:170:77] wire _entries_WIRE_18_fragmented_superpage = _entries_T_215; // @[TLB.scala:170:77] assign _entries_T_216 = _entries_WIRE_19[1]; // @[TLB.scala:170:77] wire _entries_WIRE_18_c = _entries_T_216; // @[TLB.scala:170:77] assign _entries_T_217 = _entries_WIRE_19[2]; // @[TLB.scala:170:77] wire _entries_WIRE_18_eff = _entries_T_217; // @[TLB.scala:170:77] assign _entries_T_218 = _entries_WIRE_19[3]; // @[TLB.scala:170:77] wire _entries_WIRE_18_paa = _entries_T_218; // @[TLB.scala:170:77] assign _entries_T_219 = _entries_WIRE_19[4]; // @[TLB.scala:170:77] wire _entries_WIRE_18_pal = _entries_T_219; // @[TLB.scala:170:77] assign _entries_T_220 = _entries_WIRE_19[5]; // @[TLB.scala:170:77] wire _entries_WIRE_18_ppp = _entries_T_220; // @[TLB.scala:170:77] assign _entries_T_221 = _entries_WIRE_19[6]; // @[TLB.scala:170:77] wire _entries_WIRE_18_pr = _entries_T_221; // @[TLB.scala:170:77] assign _entries_T_222 = _entries_WIRE_19[7]; // @[TLB.scala:170:77] wire _entries_WIRE_18_px = _entries_T_222; // @[TLB.scala:170:77] assign _entries_T_223 = _entries_WIRE_19[8]; // @[TLB.scala:170:77] wire _entries_WIRE_18_pw = _entries_T_223; // @[TLB.scala:170:77] assign _entries_T_224 = _entries_WIRE_19[9]; // @[TLB.scala:170:77] wire _entries_WIRE_18_hr = _entries_T_224; // @[TLB.scala:170:77] assign _entries_T_225 = _entries_WIRE_19[10]; // @[TLB.scala:170:77] wire _entries_WIRE_18_hx = _entries_T_225; // @[TLB.scala:170:77] assign _entries_T_226 = _entries_WIRE_19[11]; // @[TLB.scala:170:77] wire _entries_WIRE_18_hw = _entries_T_226; // @[TLB.scala:170:77] assign _entries_T_227 = _entries_WIRE_19[12]; // @[TLB.scala:170:77] wire _entries_WIRE_18_sr = _entries_T_227; // @[TLB.scala:170:77] assign _entries_T_228 = _entries_WIRE_19[13]; // @[TLB.scala:170:77] wire _entries_WIRE_18_sx = _entries_T_228; // @[TLB.scala:170:77] assign _entries_T_229 = _entries_WIRE_19[14]; // @[TLB.scala:170:77] wire _entries_WIRE_18_sw = _entries_T_229; // @[TLB.scala:170:77] assign _entries_T_230 = _entries_WIRE_19[15]; // @[TLB.scala:170:77] wire _entries_WIRE_18_gf = _entries_T_230; // @[TLB.scala:170:77] assign _entries_T_231 = _entries_WIRE_19[16]; // @[TLB.scala:170:77] wire _entries_WIRE_18_pf = _entries_T_231; // @[TLB.scala:170:77] assign _entries_T_232 = _entries_WIRE_19[17]; // @[TLB.scala:170:77] wire _entries_WIRE_18_ae_stage2 = _entries_T_232; // @[TLB.scala:170:77] assign _entries_T_233 = _entries_WIRE_19[18]; // @[TLB.scala:170:77] wire _entries_WIRE_18_ae_final = _entries_T_233; // @[TLB.scala:170:77] assign _entries_T_234 = _entries_WIRE_19[19]; // @[TLB.scala:170:77] wire _entries_WIRE_18_ae_ptw = _entries_T_234; // @[TLB.scala:170:77] assign _entries_T_235 = _entries_WIRE_19[20]; // @[TLB.scala:170:77] wire _entries_WIRE_18_g = _entries_T_235; // @[TLB.scala:170:77] assign _entries_T_236 = _entries_WIRE_19[21]; // @[TLB.scala:170:77] wire _entries_WIRE_18_u = _entries_T_236; // @[TLB.scala:170:77] assign _entries_T_237 = _entries_WIRE_19[41:22]; // @[TLB.scala:170:77] wire [19:0] _entries_WIRE_18_ppn = _entries_T_237; // @[TLB.scala:170:77] wire [19:0] _entries_T_260; // @[TLB.scala:170:77] wire _entries_T_259; // @[TLB.scala:170:77] wire _entries_T_258; // @[TLB.scala:170:77] wire _entries_T_257; // @[TLB.scala:170:77] wire _entries_T_256; // @[TLB.scala:170:77] wire _entries_T_255; // @[TLB.scala:170:77] wire _entries_T_254; // @[TLB.scala:170:77] wire _entries_T_253; // @[TLB.scala:170:77] wire _entries_T_252; // @[TLB.scala:170:77] wire _entries_T_251; // @[TLB.scala:170:77] wire _entries_T_250; // @[TLB.scala:170:77] wire _entries_T_249; // @[TLB.scala:170:77] wire _entries_T_248; // @[TLB.scala:170:77] wire _entries_T_247; // @[TLB.scala:170:77] wire _entries_T_246; // @[TLB.scala:170:77] wire _entries_T_245; // @[TLB.scala:170:77] wire _entries_T_244; // @[TLB.scala:170:77] wire _entries_T_243; // @[TLB.scala:170:77] wire _entries_T_242; // @[TLB.scala:170:77] wire _entries_T_241; // @[TLB.scala:170:77] wire _entries_T_240; // @[TLB.scala:170:77] wire _entries_T_239; // @[TLB.scala:170:77] wire _entries_T_238; // @[TLB.scala:170:77] assign _entries_T_238 = _entries_WIRE_21[0]; // @[TLB.scala:170:77] wire _entries_WIRE_20_fragmented_superpage = _entries_T_238; // @[TLB.scala:170:77] assign _entries_T_239 = _entries_WIRE_21[1]; // @[TLB.scala:170:77] wire _entries_WIRE_20_c = _entries_T_239; // @[TLB.scala:170:77] assign _entries_T_240 = _entries_WIRE_21[2]; // @[TLB.scala:170:77] wire _entries_WIRE_20_eff = _entries_T_240; // @[TLB.scala:170:77] assign _entries_T_241 = _entries_WIRE_21[3]; // @[TLB.scala:170:77] wire _entries_WIRE_20_paa = _entries_T_241; // @[TLB.scala:170:77] assign _entries_T_242 = _entries_WIRE_21[4]; // @[TLB.scala:170:77] wire _entries_WIRE_20_pal = _entries_T_242; // @[TLB.scala:170:77] assign _entries_T_243 = _entries_WIRE_21[5]; // @[TLB.scala:170:77] wire _entries_WIRE_20_ppp = _entries_T_243; // @[TLB.scala:170:77] assign _entries_T_244 = _entries_WIRE_21[6]; // @[TLB.scala:170:77] wire _entries_WIRE_20_pr = _entries_T_244; // @[TLB.scala:170:77] assign _entries_T_245 = _entries_WIRE_21[7]; // @[TLB.scala:170:77] wire _entries_WIRE_20_px = _entries_T_245; // @[TLB.scala:170:77] assign _entries_T_246 = _entries_WIRE_21[8]; // @[TLB.scala:170:77] wire _entries_WIRE_20_pw = _entries_T_246; // @[TLB.scala:170:77] assign _entries_T_247 = _entries_WIRE_21[9]; // @[TLB.scala:170:77] wire _entries_WIRE_20_hr = _entries_T_247; // @[TLB.scala:170:77] assign _entries_T_248 = _entries_WIRE_21[10]; // @[TLB.scala:170:77] wire _entries_WIRE_20_hx = _entries_T_248; // @[TLB.scala:170:77] assign _entries_T_249 = _entries_WIRE_21[11]; // @[TLB.scala:170:77] wire _entries_WIRE_20_hw = _entries_T_249; // @[TLB.scala:170:77] assign _entries_T_250 = _entries_WIRE_21[12]; // @[TLB.scala:170:77] wire _entries_WIRE_20_sr = _entries_T_250; // @[TLB.scala:170:77] assign _entries_T_251 = _entries_WIRE_21[13]; // @[TLB.scala:170:77] wire _entries_WIRE_20_sx = _entries_T_251; // @[TLB.scala:170:77] assign _entries_T_252 = _entries_WIRE_21[14]; // @[TLB.scala:170:77] wire _entries_WIRE_20_sw = _entries_T_252; // @[TLB.scala:170:77] assign _entries_T_253 = _entries_WIRE_21[15]; // @[TLB.scala:170:77] wire _entries_WIRE_20_gf = _entries_T_253; // @[TLB.scala:170:77] assign _entries_T_254 = _entries_WIRE_21[16]; // @[TLB.scala:170:77] wire _entries_WIRE_20_pf = _entries_T_254; // @[TLB.scala:170:77] assign _entries_T_255 = _entries_WIRE_21[17]; // @[TLB.scala:170:77] wire _entries_WIRE_20_ae_stage2 = _entries_T_255; // @[TLB.scala:170:77] assign _entries_T_256 = _entries_WIRE_21[18]; // @[TLB.scala:170:77] wire _entries_WIRE_20_ae_final = _entries_T_256; // @[TLB.scala:170:77] assign _entries_T_257 = _entries_WIRE_21[19]; // @[TLB.scala:170:77] wire _entries_WIRE_20_ae_ptw = _entries_T_257; // @[TLB.scala:170:77] assign _entries_T_258 = _entries_WIRE_21[20]; // @[TLB.scala:170:77] wire _entries_WIRE_20_g = _entries_T_258; // @[TLB.scala:170:77] assign _entries_T_259 = _entries_WIRE_21[21]; // @[TLB.scala:170:77] wire _entries_WIRE_20_u = _entries_T_259; // @[TLB.scala:170:77] assign _entries_T_260 = _entries_WIRE_21[41:22]; // @[TLB.scala:170:77] wire [19:0] _entries_WIRE_20_ppn = _entries_T_260; // @[TLB.scala:170:77] wire [19:0] _entries_T_283; // @[TLB.scala:170:77] wire _entries_T_282; // @[TLB.scala:170:77] wire _entries_T_281; // @[TLB.scala:170:77] wire _entries_T_280; // @[TLB.scala:170:77] wire _entries_T_279; // @[TLB.scala:170:77] wire _entries_T_278; // @[TLB.scala:170:77] wire _entries_T_277; // @[TLB.scala:170:77] wire _entries_T_276; // @[TLB.scala:170:77] wire _entries_T_275; // @[TLB.scala:170:77] wire _entries_T_274; // @[TLB.scala:170:77] wire _entries_T_273; // @[TLB.scala:170:77] wire _entries_T_272; // @[TLB.scala:170:77] wire _entries_T_271; // @[TLB.scala:170:77] wire _entries_T_270; // @[TLB.scala:170:77] wire _entries_T_269; // @[TLB.scala:170:77] wire _entries_T_268; // @[TLB.scala:170:77] wire _entries_T_267; // @[TLB.scala:170:77] wire _entries_T_266; // @[TLB.scala:170:77] wire _entries_T_265; // @[TLB.scala:170:77] wire _entries_T_264; // @[TLB.scala:170:77] wire _entries_T_263; // @[TLB.scala:170:77] wire _entries_T_262; // @[TLB.scala:170:77] wire _entries_T_261; // @[TLB.scala:170:77] assign _entries_T_261 = _entries_WIRE_23[0]; // @[TLB.scala:170:77] wire _entries_WIRE_22_fragmented_superpage = _entries_T_261; // @[TLB.scala:170:77] assign _entries_T_262 = _entries_WIRE_23[1]; // @[TLB.scala:170:77] wire _entries_WIRE_22_c = _entries_T_262; // @[TLB.scala:170:77] assign _entries_T_263 = _entries_WIRE_23[2]; // @[TLB.scala:170:77] wire _entries_WIRE_22_eff = _entries_T_263; // @[TLB.scala:170:77] assign _entries_T_264 = _entries_WIRE_23[3]; // @[TLB.scala:170:77] wire _entries_WIRE_22_paa = _entries_T_264; // @[TLB.scala:170:77] assign _entries_T_265 = _entries_WIRE_23[4]; // @[TLB.scala:170:77] wire _entries_WIRE_22_pal = _entries_T_265; // @[TLB.scala:170:77] assign _entries_T_266 = _entries_WIRE_23[5]; // @[TLB.scala:170:77] wire _entries_WIRE_22_ppp = _entries_T_266; // @[TLB.scala:170:77] assign _entries_T_267 = _entries_WIRE_23[6]; // @[TLB.scala:170:77] wire _entries_WIRE_22_pr = _entries_T_267; // @[TLB.scala:170:77] assign _entries_T_268 = _entries_WIRE_23[7]; // @[TLB.scala:170:77] wire _entries_WIRE_22_px = _entries_T_268; // @[TLB.scala:170:77] assign _entries_T_269 = _entries_WIRE_23[8]; // @[TLB.scala:170:77] wire _entries_WIRE_22_pw = _entries_T_269; // @[TLB.scala:170:77] assign _entries_T_270 = _entries_WIRE_23[9]; // @[TLB.scala:170:77] wire _entries_WIRE_22_hr = _entries_T_270; // @[TLB.scala:170:77] assign _entries_T_271 = _entries_WIRE_23[10]; // @[TLB.scala:170:77] wire _entries_WIRE_22_hx = _entries_T_271; // @[TLB.scala:170:77] assign _entries_T_272 = _entries_WIRE_23[11]; // @[TLB.scala:170:77] wire _entries_WIRE_22_hw = _entries_T_272; // @[TLB.scala:170:77] assign _entries_T_273 = _entries_WIRE_23[12]; // @[TLB.scala:170:77] wire _entries_WIRE_22_sr = _entries_T_273; // @[TLB.scala:170:77] assign _entries_T_274 = _entries_WIRE_23[13]; // @[TLB.scala:170:77] wire _entries_WIRE_22_sx = _entries_T_274; // @[TLB.scala:170:77] assign _entries_T_275 = _entries_WIRE_23[14]; // @[TLB.scala:170:77] wire _entries_WIRE_22_sw = _entries_T_275; // @[TLB.scala:170:77] assign _entries_T_276 = _entries_WIRE_23[15]; // @[TLB.scala:170:77] wire _entries_WIRE_22_gf = _entries_T_276; // @[TLB.scala:170:77] assign _entries_T_277 = _entries_WIRE_23[16]; // @[TLB.scala:170:77] wire _entries_WIRE_22_pf = _entries_T_277; // @[TLB.scala:170:77] assign _entries_T_278 = _entries_WIRE_23[17]; // @[TLB.scala:170:77] wire _entries_WIRE_22_ae_stage2 = _entries_T_278; // @[TLB.scala:170:77] assign _entries_T_279 = _entries_WIRE_23[18]; // @[TLB.scala:170:77] wire _entries_WIRE_22_ae_final = _entries_T_279; // @[TLB.scala:170:77] assign _entries_T_280 = _entries_WIRE_23[19]; // @[TLB.scala:170:77] wire _entries_WIRE_22_ae_ptw = _entries_T_280; // @[TLB.scala:170:77] assign _entries_T_281 = _entries_WIRE_23[20]; // @[TLB.scala:170:77] wire _entries_WIRE_22_g = _entries_T_281; // @[TLB.scala:170:77] assign _entries_T_282 = _entries_WIRE_23[21]; // @[TLB.scala:170:77] wire _entries_WIRE_22_u = _entries_T_282; // @[TLB.scala:170:77] assign _entries_T_283 = _entries_WIRE_23[41:22]; // @[TLB.scala:170:77] wire [19:0] _entries_WIRE_22_ppn = _entries_T_283; // @[TLB.scala:170:77] wire [19:0] _entries_T_306; // @[TLB.scala:170:77] wire _entries_T_305; // @[TLB.scala:170:77] wire _entries_T_304; // @[TLB.scala:170:77] wire _entries_T_303; // @[TLB.scala:170:77] wire _entries_T_302; // @[TLB.scala:170:77] wire _entries_T_301; // @[TLB.scala:170:77] wire _entries_T_300; // @[TLB.scala:170:77] wire _entries_T_299; // @[TLB.scala:170:77] wire _entries_T_298; // @[TLB.scala:170:77] wire _entries_T_297; // @[TLB.scala:170:77] wire _entries_T_296; // @[TLB.scala:170:77] wire _entries_T_295; // @[TLB.scala:170:77] wire _entries_T_294; // @[TLB.scala:170:77] wire _entries_T_293; // @[TLB.scala:170:77] wire _entries_T_292; // @[TLB.scala:170:77] wire _entries_T_291; // @[TLB.scala:170:77] wire _entries_T_290; // @[TLB.scala:170:77] wire _entries_T_289; // @[TLB.scala:170:77] wire _entries_T_288; // @[TLB.scala:170:77] wire _entries_T_287; // @[TLB.scala:170:77] wire _entries_T_286; // @[TLB.scala:170:77] wire _entries_T_285; // @[TLB.scala:170:77] wire _entries_T_284; // @[TLB.scala:170:77] assign _entries_T_284 = _entries_WIRE_25[0]; // @[TLB.scala:170:77] wire _entries_WIRE_24_fragmented_superpage = _entries_T_284; // @[TLB.scala:170:77] assign _entries_T_285 = _entries_WIRE_25[1]; // @[TLB.scala:170:77] wire _entries_WIRE_24_c = _entries_T_285; // @[TLB.scala:170:77] assign _entries_T_286 = _entries_WIRE_25[2]; // @[TLB.scala:170:77] wire _entries_WIRE_24_eff = _entries_T_286; // @[TLB.scala:170:77] assign _entries_T_287 = _entries_WIRE_25[3]; // @[TLB.scala:170:77] wire _entries_WIRE_24_paa = _entries_T_287; // @[TLB.scala:170:77] assign _entries_T_288 = _entries_WIRE_25[4]; // @[TLB.scala:170:77] wire _entries_WIRE_24_pal = _entries_T_288; // @[TLB.scala:170:77] assign _entries_T_289 = _entries_WIRE_25[5]; // @[TLB.scala:170:77] wire _entries_WIRE_24_ppp = _entries_T_289; // @[TLB.scala:170:77] assign _entries_T_290 = _entries_WIRE_25[6]; // @[TLB.scala:170:77] wire _entries_WIRE_24_pr = _entries_T_290; // @[TLB.scala:170:77] assign _entries_T_291 = _entries_WIRE_25[7]; // @[TLB.scala:170:77] wire _entries_WIRE_24_px = _entries_T_291; // @[TLB.scala:170:77] assign _entries_T_292 = _entries_WIRE_25[8]; // @[TLB.scala:170:77] wire _entries_WIRE_24_pw = _entries_T_292; // @[TLB.scala:170:77] assign _entries_T_293 = _entries_WIRE_25[9]; // @[TLB.scala:170:77] wire _entries_WIRE_24_hr = _entries_T_293; // @[TLB.scala:170:77] assign _entries_T_294 = _entries_WIRE_25[10]; // @[TLB.scala:170:77] wire _entries_WIRE_24_hx = _entries_T_294; // @[TLB.scala:170:77] assign _entries_T_295 = _entries_WIRE_25[11]; // @[TLB.scala:170:77] wire _entries_WIRE_24_hw = _entries_T_295; // @[TLB.scala:170:77] assign _entries_T_296 = _entries_WIRE_25[12]; // @[TLB.scala:170:77] wire _entries_WIRE_24_sr = _entries_T_296; // @[TLB.scala:170:77] assign _entries_T_297 = _entries_WIRE_25[13]; // @[TLB.scala:170:77] wire _entries_WIRE_24_sx = _entries_T_297; // @[TLB.scala:170:77] assign _entries_T_298 = _entries_WIRE_25[14]; // @[TLB.scala:170:77] wire _entries_WIRE_24_sw = _entries_T_298; // @[TLB.scala:170:77] assign _entries_T_299 = _entries_WIRE_25[15]; // @[TLB.scala:170:77] wire _entries_WIRE_24_gf = _entries_T_299; // @[TLB.scala:170:77] assign _entries_T_300 = _entries_WIRE_25[16]; // @[TLB.scala:170:77] wire _entries_WIRE_24_pf = _entries_T_300; // @[TLB.scala:170:77] assign _entries_T_301 = _entries_WIRE_25[17]; // @[TLB.scala:170:77] wire _entries_WIRE_24_ae_stage2 = _entries_T_301; // @[TLB.scala:170:77] assign _entries_T_302 = _entries_WIRE_25[18]; // @[TLB.scala:170:77] wire _entries_WIRE_24_ae_final = _entries_T_302; // @[TLB.scala:170:77] assign _entries_T_303 = _entries_WIRE_25[19]; // @[TLB.scala:170:77] wire _entries_WIRE_24_ae_ptw = _entries_T_303; // @[TLB.scala:170:77] assign _entries_T_304 = _entries_WIRE_25[20]; // @[TLB.scala:170:77] wire _entries_WIRE_24_g = _entries_T_304; // @[TLB.scala:170:77] assign _entries_T_305 = _entries_WIRE_25[21]; // @[TLB.scala:170:77] wire _entries_WIRE_24_u = _entries_T_305; // @[TLB.scala:170:77] assign _entries_T_306 = _entries_WIRE_25[41:22]; // @[TLB.scala:170:77] wire [19:0] _entries_WIRE_24_ppn = _entries_T_306; // @[TLB.scala:170:77] wire _ppn_T = ~vm_enabled; // @[TLB.scala:399:61, :442:18, :502:30] wire [1:0] ppn_res = _entries_barrier_8_io_y_ppn[19:18]; // @[package.scala:267:25] wire ppn_ignore = _ppn_ignore_T; // @[TLB.scala:197:{28,34}] wire [26:0] _ppn_T_1 = ppn_ignore ? vpn : 27'h0; // @[TLB.scala:197:34, :198:28, :335:30] wire [26:0] _ppn_T_2 = {_ppn_T_1[26:20], _ppn_T_1[19:0] | _entries_barrier_8_io_y_ppn}; // @[package.scala:267:25] wire [8:0] _ppn_T_3 = _ppn_T_2[17:9]; // @[TLB.scala:198:{47,58}] wire [10:0] _ppn_T_4 = {ppn_res, _ppn_T_3}; // @[TLB.scala:195:26, :198:{18,58}] wire _ppn_ignore_T_1 = ~(superpage_entries_0_level[1]); // @[TLB.scala:182:28, :197:28, :341:30] wire [26:0] _ppn_T_6 = {_ppn_T_5[26:20], _ppn_T_5[19:0] | _entries_barrier_8_io_y_ppn}; // @[package.scala:267:25] wire [8:0] _ppn_T_7 = _ppn_T_6[8:0]; // @[TLB.scala:198:{47,58}] wire [19:0] _ppn_T_8 = {_ppn_T_4, _ppn_T_7}; // @[TLB.scala:198:{18,58}] wire [1:0] ppn_res_1 = _entries_barrier_9_io_y_ppn[19:18]; // @[package.scala:267:25] wire ppn_ignore_2 = _ppn_ignore_T_2; // @[TLB.scala:197:{28,34}] wire [26:0] _ppn_T_9 = ppn_ignore_2 ? vpn : 27'h0; // @[TLB.scala:197:34, :198:28, :335:30] wire [26:0] _ppn_T_10 = {_ppn_T_9[26:20], _ppn_T_9[19:0] | _entries_barrier_9_io_y_ppn}; // @[package.scala:267:25] wire [8:0] _ppn_T_11 = _ppn_T_10[17:9]; // @[TLB.scala:198:{47,58}] wire [10:0] _ppn_T_12 = {ppn_res_1, _ppn_T_11}; // @[TLB.scala:195:26, :198:{18,58}] wire _ppn_ignore_T_3 = ~(superpage_entries_1_level[1]); // @[TLB.scala:182:28, :197:28, :341:30] wire [26:0] _ppn_T_14 = {_ppn_T_13[26:20], _ppn_T_13[19:0] | _entries_barrier_9_io_y_ppn}; // @[package.scala:267:25] wire [8:0] _ppn_T_15 = _ppn_T_14[8:0]; // @[TLB.scala:198:{47,58}] wire [19:0] _ppn_T_16 = {_ppn_T_12, _ppn_T_15}; // @[TLB.scala:198:{18,58}] wire [1:0] ppn_res_2 = _entries_barrier_10_io_y_ppn[19:18]; // @[package.scala:267:25] wire ppn_ignore_4 = _ppn_ignore_T_4; // @[TLB.scala:197:{28,34}] wire [26:0] _ppn_T_17 = ppn_ignore_4 ? vpn : 27'h0; // @[TLB.scala:197:34, :198:28, :335:30] wire [26:0] _ppn_T_18 = {_ppn_T_17[26:20], _ppn_T_17[19:0] | _entries_barrier_10_io_y_ppn}; // @[package.scala:267:25] wire [8:0] _ppn_T_19 = _ppn_T_18[17:9]; // @[TLB.scala:198:{47,58}] wire [10:0] _ppn_T_20 = {ppn_res_2, _ppn_T_19}; // @[TLB.scala:195:26, :198:{18,58}] wire _ppn_ignore_T_5 = ~(superpage_entries_2_level[1]); // @[TLB.scala:182:28, :197:28, :341:30] wire [26:0] _ppn_T_22 = {_ppn_T_21[26:20], _ppn_T_21[19:0] | _entries_barrier_10_io_y_ppn}; // @[package.scala:267:25] wire [8:0] _ppn_T_23 = _ppn_T_22[8:0]; // @[TLB.scala:198:{47,58}] wire [19:0] _ppn_T_24 = {_ppn_T_20, _ppn_T_23}; // @[TLB.scala:198:{18,58}] wire [1:0] ppn_res_3 = _entries_barrier_11_io_y_ppn[19:18]; // @[package.scala:267:25] wire ppn_ignore_6 = _ppn_ignore_T_6; // @[TLB.scala:197:{28,34}] wire [26:0] _ppn_T_25 = ppn_ignore_6 ? vpn : 27'h0; // @[TLB.scala:197:34, :198:28, :335:30] wire [26:0] _ppn_T_26 = {_ppn_T_25[26:20], _ppn_T_25[19:0] | _entries_barrier_11_io_y_ppn}; // @[package.scala:267:25] wire [8:0] _ppn_T_27 = _ppn_T_26[17:9]; // @[TLB.scala:198:{47,58}] wire [10:0] _ppn_T_28 = {ppn_res_3, _ppn_T_27}; // @[TLB.scala:195:26, :198:{18,58}] wire _ppn_ignore_T_7 = ~(superpage_entries_3_level[1]); // @[TLB.scala:182:28, :197:28, :341:30] wire [26:0] _ppn_T_30 = {_ppn_T_29[26:20], _ppn_T_29[19:0] | _entries_barrier_11_io_y_ppn}; // @[package.scala:267:25] wire [8:0] _ppn_T_31 = _ppn_T_30[8:0]; // @[TLB.scala:198:{47,58}] wire [19:0] _ppn_T_32 = {_ppn_T_28, _ppn_T_31}; // @[TLB.scala:198:{18,58}] wire [1:0] ppn_res_4 = _entries_barrier_12_io_y_ppn[19:18]; // @[package.scala:267:25] wire ppn_ignore_8 = _ppn_ignore_T_8; // @[TLB.scala:197:{28,34}] wire [26:0] _ppn_T_33 = ppn_ignore_8 ? vpn : 27'h0; // @[TLB.scala:197:34, :198:28, :335:30] wire [26:0] _ppn_T_34 = {_ppn_T_33[26:20], _ppn_T_33[19:0] | _entries_barrier_12_io_y_ppn}; // @[package.scala:267:25] wire [8:0] _ppn_T_35 = _ppn_T_34[17:9]; // @[TLB.scala:198:{47,58}] wire [10:0] _ppn_T_36 = {ppn_res_4, _ppn_T_35}; // @[TLB.scala:195:26, :198:{18,58}] wire _ppn_ignore_T_9 = ~(special_entry_level[1]); // @[TLB.scala:197:28, :346:56] wire ppn_ignore_9 = _ppn_ignore_T_9; // @[TLB.scala:197:{28,34}] wire [26:0] _ppn_T_37 = ppn_ignore_9 ? vpn : 27'h0; // @[TLB.scala:197:34, :198:28, :335:30] wire [26:0] _ppn_T_38 = {_ppn_T_37[26:20], _ppn_T_37[19:0] | _entries_barrier_12_io_y_ppn}; // @[package.scala:267:25] wire [8:0] _ppn_T_39 = _ppn_T_38[8:0]; // @[TLB.scala:198:{47,58}] wire [19:0] _ppn_T_40 = {_ppn_T_36, _ppn_T_39}; // @[TLB.scala:198:{18,58}] wire [19:0] _ppn_T_41 = vpn[19:0]; // @[TLB.scala:335:30, :502:125] wire [19:0] _ppn_T_42 = hitsVec_0 ? _entries_barrier_io_y_ppn : 20'h0; // @[Mux.scala:30:73] wire [19:0] _ppn_T_43 = hitsVec_1 ? _entries_barrier_1_io_y_ppn : 20'h0; // @[Mux.scala:30:73] wire [19:0] _ppn_T_44 = hitsVec_2 ? _entries_barrier_2_io_y_ppn : 20'h0; // @[Mux.scala:30:73] wire [19:0] _ppn_T_45 = hitsVec_3 ? _entries_barrier_3_io_y_ppn : 20'h0; // @[Mux.scala:30:73] wire [19:0] _ppn_T_46 = hitsVec_4 ? _entries_barrier_4_io_y_ppn : 20'h0; // @[Mux.scala:30:73] wire [19:0] _ppn_T_47 = hitsVec_5 ? _entries_barrier_5_io_y_ppn : 20'h0; // @[Mux.scala:30:73] wire [19:0] _ppn_T_48 = hitsVec_6 ? _entries_barrier_6_io_y_ppn : 20'h0; // @[Mux.scala:30:73] wire [19:0] _ppn_T_49 = hitsVec_7 ? _entries_barrier_7_io_y_ppn : 20'h0; // @[Mux.scala:30:73] wire [19:0] _ppn_T_50 = hitsVec_8 ? _ppn_T_8 : 20'h0; // @[Mux.scala:30:73] wire [19:0] _ppn_T_51 = hitsVec_9 ? _ppn_T_16 : 20'h0; // @[Mux.scala:30:73] wire [19:0] _ppn_T_52 = hitsVec_10 ? _ppn_T_24 : 20'h0; // @[Mux.scala:30:73] wire [19:0] _ppn_T_53 = hitsVec_11 ? _ppn_T_32 : 20'h0; // @[Mux.scala:30:73] wire [19:0] _ppn_T_54 = hitsVec_12 ? _ppn_T_40 : 20'h0; // @[Mux.scala:30:73] wire [19:0] _ppn_T_55 = _ppn_T ? _ppn_T_41 : 20'h0; // @[Mux.scala:30:73] wire [19:0] _ppn_T_56 = _ppn_T_42 | _ppn_T_43; // @[Mux.scala:30:73] wire [19:0] _ppn_T_57 = _ppn_T_56 | _ppn_T_44; // @[Mux.scala:30:73] wire [19:0] _ppn_T_58 = _ppn_T_57 | _ppn_T_45; // @[Mux.scala:30:73] wire [19:0] _ppn_T_59 = _ppn_T_58 | _ppn_T_46; // @[Mux.scala:30:73] wire [19:0] _ppn_T_60 = _ppn_T_59 | _ppn_T_47; // @[Mux.scala:30:73] wire [19:0] _ppn_T_61 = _ppn_T_60 | _ppn_T_48; // @[Mux.scala:30:73] wire [19:0] _ppn_T_62 = _ppn_T_61 | _ppn_T_49; // @[Mux.scala:30:73] wire [19:0] _ppn_T_63 = _ppn_T_62 | _ppn_T_50; // @[Mux.scala:30:73] wire [19:0] _ppn_T_64 = _ppn_T_63 | _ppn_T_51; // @[Mux.scala:30:73] wire [19:0] _ppn_T_65 = _ppn_T_64 | _ppn_T_52; // @[Mux.scala:30:73] wire [19:0] _ppn_T_66 = _ppn_T_65 | _ppn_T_53; // @[Mux.scala:30:73] wire [19:0] _ppn_T_67 = _ppn_T_66 | _ppn_T_54; // @[Mux.scala:30:73] wire [19:0] _ppn_T_68 = _ppn_T_67 | _ppn_T_55; // @[Mux.scala:30:73] wire [19:0] ppn = _ppn_T_68; // @[Mux.scala:30:73] wire [1:0] ptw_ae_array_lo_lo_hi = {_entries_barrier_2_io_y_ae_ptw, _entries_barrier_1_io_y_ae_ptw}; // @[package.scala:45:27, :267:25] wire [2:0] ptw_ae_array_lo_lo = {ptw_ae_array_lo_lo_hi, _entries_barrier_io_y_ae_ptw}; // @[package.scala:45:27, :267:25] wire [1:0] ptw_ae_array_lo_hi_hi = {_entries_barrier_5_io_y_ae_ptw, _entries_barrier_4_io_y_ae_ptw}; // @[package.scala:45:27, :267:25] wire [2:0] ptw_ae_array_lo_hi = {ptw_ae_array_lo_hi_hi, _entries_barrier_3_io_y_ae_ptw}; // @[package.scala:45:27, :267:25] wire [5:0] ptw_ae_array_lo = {ptw_ae_array_lo_hi, ptw_ae_array_lo_lo}; // @[package.scala:45:27] wire [1:0] ptw_ae_array_hi_lo_hi = {_entries_barrier_8_io_y_ae_ptw, _entries_barrier_7_io_y_ae_ptw}; // @[package.scala:45:27, :267:25] wire [2:0] ptw_ae_array_hi_lo = {ptw_ae_array_hi_lo_hi, _entries_barrier_6_io_y_ae_ptw}; // @[package.scala:45:27, :267:25] wire [1:0] ptw_ae_array_hi_hi_lo = {_entries_barrier_10_io_y_ae_ptw, _entries_barrier_9_io_y_ae_ptw}; // @[package.scala:45:27, :267:25] wire [1:0] ptw_ae_array_hi_hi_hi = {_entries_barrier_12_io_y_ae_ptw, _entries_barrier_11_io_y_ae_ptw}; // @[package.scala:45:27, :267:25] wire [3:0] ptw_ae_array_hi_hi = {ptw_ae_array_hi_hi_hi, ptw_ae_array_hi_hi_lo}; // @[package.scala:45:27] wire [6:0] ptw_ae_array_hi = {ptw_ae_array_hi_hi, ptw_ae_array_hi_lo}; // @[package.scala:45:27] wire [12:0] _ptw_ae_array_T = {ptw_ae_array_hi, ptw_ae_array_lo}; // @[package.scala:45:27] wire [13:0] ptw_ae_array = {1'h0, _ptw_ae_array_T}; // @[package.scala:45:27] wire [1:0] final_ae_array_lo_lo_hi = {_entries_barrier_2_io_y_ae_final, _entries_barrier_1_io_y_ae_final}; // @[package.scala:45:27, :267:25] wire [2:0] final_ae_array_lo_lo = {final_ae_array_lo_lo_hi, _entries_barrier_io_y_ae_final}; // @[package.scala:45:27, :267:25] wire [1:0] final_ae_array_lo_hi_hi = {_entries_barrier_5_io_y_ae_final, _entries_barrier_4_io_y_ae_final}; // @[package.scala:45:27, :267:25] wire [2:0] final_ae_array_lo_hi = {final_ae_array_lo_hi_hi, _entries_barrier_3_io_y_ae_final}; // @[package.scala:45:27, :267:25] wire [5:0] final_ae_array_lo = {final_ae_array_lo_hi, final_ae_array_lo_lo}; // @[package.scala:45:27] wire [1:0] final_ae_array_hi_lo_hi = {_entries_barrier_8_io_y_ae_final, _entries_barrier_7_io_y_ae_final}; // @[package.scala:45:27, :267:25] wire [2:0] final_ae_array_hi_lo = {final_ae_array_hi_lo_hi, _entries_barrier_6_io_y_ae_final}; // @[package.scala:45:27, :267:25] wire [1:0] final_ae_array_hi_hi_lo = {_entries_barrier_10_io_y_ae_final, _entries_barrier_9_io_y_ae_final}; // @[package.scala:45:27, :267:25] wire [1:0] final_ae_array_hi_hi_hi = {_entries_barrier_12_io_y_ae_final, _entries_barrier_11_io_y_ae_final}; // @[package.scala:45:27, :267:25] wire [3:0] final_ae_array_hi_hi = {final_ae_array_hi_hi_hi, final_ae_array_hi_hi_lo}; // @[package.scala:45:27] wire [6:0] final_ae_array_hi = {final_ae_array_hi_hi, final_ae_array_hi_lo}; // @[package.scala:45:27] wire [12:0] _final_ae_array_T = {final_ae_array_hi, final_ae_array_lo}; // @[package.scala:45:27] wire [13:0] final_ae_array = {1'h0, _final_ae_array_T}; // @[package.scala:45:27] wire [1:0] ptw_pf_array_lo_lo_hi = {_entries_barrier_2_io_y_pf, _entries_barrier_1_io_y_pf}; // @[package.scala:45:27, :267:25] wire [2:0] ptw_pf_array_lo_lo = {ptw_pf_array_lo_lo_hi, _entries_barrier_io_y_pf}; // @[package.scala:45:27, :267:25] wire [1:0] ptw_pf_array_lo_hi_hi = {_entries_barrier_5_io_y_pf, _entries_barrier_4_io_y_pf}; // @[package.scala:45:27, :267:25] wire [2:0] ptw_pf_array_lo_hi = {ptw_pf_array_lo_hi_hi, _entries_barrier_3_io_y_pf}; // @[package.scala:45:27, :267:25] wire [5:0] ptw_pf_array_lo = {ptw_pf_array_lo_hi, ptw_pf_array_lo_lo}; // @[package.scala:45:27] wire [1:0] ptw_pf_array_hi_lo_hi = {_entries_barrier_8_io_y_pf, _entries_barrier_7_io_y_pf}; // @[package.scala:45:27, :267:25] wire [2:0] ptw_pf_array_hi_lo = {ptw_pf_array_hi_lo_hi, _entries_barrier_6_io_y_pf}; // @[package.scala:45:27, :267:25] wire [1:0] ptw_pf_array_hi_hi_lo = {_entries_barrier_10_io_y_pf, _entries_barrier_9_io_y_pf}; // @[package.scala:45:27, :267:25] wire [1:0] ptw_pf_array_hi_hi_hi = {_entries_barrier_12_io_y_pf, _entries_barrier_11_io_y_pf}; // @[package.scala:45:27, :267:25] wire [3:0] ptw_pf_array_hi_hi = {ptw_pf_array_hi_hi_hi, ptw_pf_array_hi_hi_lo}; // @[package.scala:45:27] wire [6:0] ptw_pf_array_hi = {ptw_pf_array_hi_hi, ptw_pf_array_hi_lo}; // @[package.scala:45:27] wire [12:0] _ptw_pf_array_T = {ptw_pf_array_hi, ptw_pf_array_lo}; // @[package.scala:45:27] wire [13:0] ptw_pf_array = {1'h0, _ptw_pf_array_T}; // @[package.scala:45:27] wire [1:0] ptw_gf_array_lo_lo_hi = {_entries_barrier_2_io_y_gf, _entries_barrier_1_io_y_gf}; // @[package.scala:45:27, :267:25] wire [2:0] ptw_gf_array_lo_lo = {ptw_gf_array_lo_lo_hi, _entries_barrier_io_y_gf}; // @[package.scala:45:27, :267:25] wire [1:0] ptw_gf_array_lo_hi_hi = {_entries_barrier_5_io_y_gf, _entries_barrier_4_io_y_gf}; // @[package.scala:45:27, :267:25] wire [2:0] ptw_gf_array_lo_hi = {ptw_gf_array_lo_hi_hi, _entries_barrier_3_io_y_gf}; // @[package.scala:45:27, :267:25] wire [5:0] ptw_gf_array_lo = {ptw_gf_array_lo_hi, ptw_gf_array_lo_lo}; // @[package.scala:45:27] wire [1:0] ptw_gf_array_hi_lo_hi = {_entries_barrier_8_io_y_gf, _entries_barrier_7_io_y_gf}; // @[package.scala:45:27, :267:25] wire [2:0] ptw_gf_array_hi_lo = {ptw_gf_array_hi_lo_hi, _entries_barrier_6_io_y_gf}; // @[package.scala:45:27, :267:25] wire [1:0] ptw_gf_array_hi_hi_lo = {_entries_barrier_10_io_y_gf, _entries_barrier_9_io_y_gf}; // @[package.scala:45:27, :267:25] wire [1:0] ptw_gf_array_hi_hi_hi = {_entries_barrier_12_io_y_gf, _entries_barrier_11_io_y_gf}; // @[package.scala:45:27, :267:25] wire [3:0] ptw_gf_array_hi_hi = {ptw_gf_array_hi_hi_hi, ptw_gf_array_hi_hi_lo}; // @[package.scala:45:27] wire [6:0] ptw_gf_array_hi = {ptw_gf_array_hi_hi, ptw_gf_array_hi_lo}; // @[package.scala:45:27] wire [12:0] _ptw_gf_array_T = {ptw_gf_array_hi, ptw_gf_array_lo}; // @[package.scala:45:27] wire [13:0] ptw_gf_array = {1'h0, _ptw_gf_array_T}; // @[package.scala:45:27] wire [13:0] _gf_ld_array_T_3 = ptw_gf_array; // @[TLB.scala:509:25, :600:82] wire [13:0] _gf_st_array_T_2 = ptw_gf_array; // @[TLB.scala:509:25, :601:63] wire [13:0] _gf_inst_array_T_1 = ptw_gf_array; // @[TLB.scala:509:25, :602:46] wire _priv_rw_ok_T = ~priv_s; // @[TLB.scala:370:20, :513:24] wire _priv_rw_ok_T_1 = _priv_rw_ok_T | sum; // @[TLB.scala:510:16, :513:{24,32}] wire [1:0] _GEN_40 = {_entries_barrier_2_io_y_u, _entries_barrier_1_io_y_u}; // @[package.scala:45:27, :267:25] wire [1:0] priv_rw_ok_lo_lo_hi; // @[package.scala:45:27] assign priv_rw_ok_lo_lo_hi = _GEN_40; // @[package.scala:45:27] wire [1:0] priv_rw_ok_lo_lo_hi_1; // @[package.scala:45:27] assign priv_rw_ok_lo_lo_hi_1 = _GEN_40; // @[package.scala:45:27] wire [1:0] priv_x_ok_lo_lo_hi; // @[package.scala:45:27] assign priv_x_ok_lo_lo_hi = _GEN_40; // @[package.scala:45:27] wire [1:0] priv_x_ok_lo_lo_hi_1; // @[package.scala:45:27] assign priv_x_ok_lo_lo_hi_1 = _GEN_40; // @[package.scala:45:27] wire [2:0] priv_rw_ok_lo_lo = {priv_rw_ok_lo_lo_hi, _entries_barrier_io_y_u}; // @[package.scala:45:27, :267:25] wire [1:0] _GEN_41 = {_entries_barrier_5_io_y_u, _entries_barrier_4_io_y_u}; // @[package.scala:45:27, :267:25] wire [1:0] priv_rw_ok_lo_hi_hi; // @[package.scala:45:27] assign priv_rw_ok_lo_hi_hi = _GEN_41; // @[package.scala:45:27] wire [1:0] priv_rw_ok_lo_hi_hi_1; // @[package.scala:45:27] assign priv_rw_ok_lo_hi_hi_1 = _GEN_41; // @[package.scala:45:27] wire [1:0] priv_x_ok_lo_hi_hi; // @[package.scala:45:27] assign priv_x_ok_lo_hi_hi = _GEN_41; // @[package.scala:45:27] wire [1:0] priv_x_ok_lo_hi_hi_1; // @[package.scala:45:27] assign priv_x_ok_lo_hi_hi_1 = _GEN_41; // @[package.scala:45:27] wire [2:0] priv_rw_ok_lo_hi = {priv_rw_ok_lo_hi_hi, _entries_barrier_3_io_y_u}; // @[package.scala:45:27, :267:25] wire [5:0] priv_rw_ok_lo = {priv_rw_ok_lo_hi, priv_rw_ok_lo_lo}; // @[package.scala:45:27] wire [1:0] _GEN_42 = {_entries_barrier_8_io_y_u, _entries_barrier_7_io_y_u}; // @[package.scala:45:27, :267:25] wire [1:0] priv_rw_ok_hi_lo_hi; // @[package.scala:45:27] assign priv_rw_ok_hi_lo_hi = _GEN_42; // @[package.scala:45:27] wire [1:0] priv_rw_ok_hi_lo_hi_1; // @[package.scala:45:27] assign priv_rw_ok_hi_lo_hi_1 = _GEN_42; // @[package.scala:45:27] wire [1:0] priv_x_ok_hi_lo_hi; // @[package.scala:45:27] assign priv_x_ok_hi_lo_hi = _GEN_42; // @[package.scala:45:27] wire [1:0] priv_x_ok_hi_lo_hi_1; // @[package.scala:45:27] assign priv_x_ok_hi_lo_hi_1 = _GEN_42; // @[package.scala:45:27] wire [2:0] priv_rw_ok_hi_lo = {priv_rw_ok_hi_lo_hi, _entries_barrier_6_io_y_u}; // @[package.scala:45:27, :267:25] wire [1:0] _GEN_43 = {_entries_barrier_10_io_y_u, _entries_barrier_9_io_y_u}; // @[package.scala:45:27, :267:25] wire [1:0] priv_rw_ok_hi_hi_lo; // @[package.scala:45:27] assign priv_rw_ok_hi_hi_lo = _GEN_43; // @[package.scala:45:27] wire [1:0] priv_rw_ok_hi_hi_lo_1; // @[package.scala:45:27] assign priv_rw_ok_hi_hi_lo_1 = _GEN_43; // @[package.scala:45:27] wire [1:0] priv_x_ok_hi_hi_lo; // @[package.scala:45:27] assign priv_x_ok_hi_hi_lo = _GEN_43; // @[package.scala:45:27] wire [1:0] priv_x_ok_hi_hi_lo_1; // @[package.scala:45:27] assign priv_x_ok_hi_hi_lo_1 = _GEN_43; // @[package.scala:45:27] wire [1:0] _GEN_44 = {_entries_barrier_12_io_y_u, _entries_barrier_11_io_y_u}; // @[package.scala:45:27, :267:25] wire [1:0] priv_rw_ok_hi_hi_hi; // @[package.scala:45:27] assign priv_rw_ok_hi_hi_hi = _GEN_44; // @[package.scala:45:27] wire [1:0] priv_rw_ok_hi_hi_hi_1; // @[package.scala:45:27] assign priv_rw_ok_hi_hi_hi_1 = _GEN_44; // @[package.scala:45:27] wire [1:0] priv_x_ok_hi_hi_hi; // @[package.scala:45:27] assign priv_x_ok_hi_hi_hi = _GEN_44; // @[package.scala:45:27] wire [1:0] priv_x_ok_hi_hi_hi_1; // @[package.scala:45:27] assign priv_x_ok_hi_hi_hi_1 = _GEN_44; // @[package.scala:45:27] wire [3:0] priv_rw_ok_hi_hi = {priv_rw_ok_hi_hi_hi, priv_rw_ok_hi_hi_lo}; // @[package.scala:45:27] wire [6:0] priv_rw_ok_hi = {priv_rw_ok_hi_hi, priv_rw_ok_hi_lo}; // @[package.scala:45:27] wire [12:0] _priv_rw_ok_T_2 = {priv_rw_ok_hi, priv_rw_ok_lo}; // @[package.scala:45:27] wire [12:0] _priv_rw_ok_T_3 = _priv_rw_ok_T_1 ? _priv_rw_ok_T_2 : 13'h0; // @[package.scala:45:27] wire [2:0] priv_rw_ok_lo_lo_1 = {priv_rw_ok_lo_lo_hi_1, _entries_barrier_io_y_u}; // @[package.scala:45:27, :267:25] wire [2:0] priv_rw_ok_lo_hi_1 = {priv_rw_ok_lo_hi_hi_1, _entries_barrier_3_io_y_u}; // @[package.scala:45:27, :267:25] wire [5:0] priv_rw_ok_lo_1 = {priv_rw_ok_lo_hi_1, priv_rw_ok_lo_lo_1}; // @[package.scala:45:27] wire [2:0] priv_rw_ok_hi_lo_1 = {priv_rw_ok_hi_lo_hi_1, _entries_barrier_6_io_y_u}; // @[package.scala:45:27, :267:25] wire [3:0] priv_rw_ok_hi_hi_1 = {priv_rw_ok_hi_hi_hi_1, priv_rw_ok_hi_hi_lo_1}; // @[package.scala:45:27] wire [6:0] priv_rw_ok_hi_1 = {priv_rw_ok_hi_hi_1, priv_rw_ok_hi_lo_1}; // @[package.scala:45:27] wire [12:0] _priv_rw_ok_T_4 = {priv_rw_ok_hi_1, priv_rw_ok_lo_1}; // @[package.scala:45:27] wire [12:0] _priv_rw_ok_T_5 = ~_priv_rw_ok_T_4; // @[package.scala:45:27] wire [12:0] _priv_rw_ok_T_6 = priv_s ? _priv_rw_ok_T_5 : 13'h0; // @[TLB.scala:370:20, :513:{75,84}] wire [12:0] priv_rw_ok = _priv_rw_ok_T_3 | _priv_rw_ok_T_6; // @[TLB.scala:513:{23,70,75}] wire [2:0] priv_x_ok_lo_lo = {priv_x_ok_lo_lo_hi, _entries_barrier_io_y_u}; // @[package.scala:45:27, :267:25] wire [2:0] priv_x_ok_lo_hi = {priv_x_ok_lo_hi_hi, _entries_barrier_3_io_y_u}; // @[package.scala:45:27, :267:25] wire [5:0] priv_x_ok_lo = {priv_x_ok_lo_hi, priv_x_ok_lo_lo}; // @[package.scala:45:27] wire [2:0] priv_x_ok_hi_lo = {priv_x_ok_hi_lo_hi, _entries_barrier_6_io_y_u}; // @[package.scala:45:27, :267:25] wire [3:0] priv_x_ok_hi_hi = {priv_x_ok_hi_hi_hi, priv_x_ok_hi_hi_lo}; // @[package.scala:45:27] wire [6:0] priv_x_ok_hi = {priv_x_ok_hi_hi, priv_x_ok_hi_lo}; // @[package.scala:45:27] wire [12:0] _priv_x_ok_T = {priv_x_ok_hi, priv_x_ok_lo}; // @[package.scala:45:27] wire [12:0] _priv_x_ok_T_1 = ~_priv_x_ok_T; // @[package.scala:45:27] wire [2:0] priv_x_ok_lo_lo_1 = {priv_x_ok_lo_lo_hi_1, _entries_barrier_io_y_u}; // @[package.scala:45:27, :267:25] wire [2:0] priv_x_ok_lo_hi_1 = {priv_x_ok_lo_hi_hi_1, _entries_barrier_3_io_y_u}; // @[package.scala:45:27, :267:25] wire [5:0] priv_x_ok_lo_1 = {priv_x_ok_lo_hi_1, priv_x_ok_lo_lo_1}; // @[package.scala:45:27] wire [2:0] priv_x_ok_hi_lo_1 = {priv_x_ok_hi_lo_hi_1, _entries_barrier_6_io_y_u}; // @[package.scala:45:27, :267:25] wire [3:0] priv_x_ok_hi_hi_1 = {priv_x_ok_hi_hi_hi_1, priv_x_ok_hi_hi_lo_1}; // @[package.scala:45:27] wire [6:0] priv_x_ok_hi_1 = {priv_x_ok_hi_hi_1, priv_x_ok_hi_lo_1}; // @[package.scala:45:27] wire [12:0] _priv_x_ok_T_2 = {priv_x_ok_hi_1, priv_x_ok_lo_1}; // @[package.scala:45:27] wire [12:0] priv_x_ok = priv_s ? _priv_x_ok_T_1 : _priv_x_ok_T_2; // @[package.scala:45:27] wire _stage1_bypass_T_1 = ~stage1_en; // @[TLB.scala:374:29, :517:83] wire [12:0] _stage1_bypass_T_2 = {13{_stage1_bypass_T_1}}; // @[TLB.scala:517:{68,83}] wire [1:0] stage1_bypass_lo_lo_hi = {_entries_barrier_2_io_y_ae_stage2, _entries_barrier_1_io_y_ae_stage2}; // @[package.scala:45:27, :267:25] wire [2:0] stage1_bypass_lo_lo = {stage1_bypass_lo_lo_hi, _entries_barrier_io_y_ae_stage2}; // @[package.scala:45:27, :267:25] wire [1:0] stage1_bypass_lo_hi_hi = {_entries_barrier_5_io_y_ae_stage2, _entries_barrier_4_io_y_ae_stage2}; // @[package.scala:45:27, :267:25] wire [2:0] stage1_bypass_lo_hi = {stage1_bypass_lo_hi_hi, _entries_barrier_3_io_y_ae_stage2}; // @[package.scala:45:27, :267:25] wire [5:0] stage1_bypass_lo = {stage1_bypass_lo_hi, stage1_bypass_lo_lo}; // @[package.scala:45:27] wire [1:0] stage1_bypass_hi_lo_hi = {_entries_barrier_8_io_y_ae_stage2, _entries_barrier_7_io_y_ae_stage2}; // @[package.scala:45:27, :267:25] wire [2:0] stage1_bypass_hi_lo = {stage1_bypass_hi_lo_hi, _entries_barrier_6_io_y_ae_stage2}; // @[package.scala:45:27, :267:25] wire [1:0] stage1_bypass_hi_hi_lo = {_entries_barrier_10_io_y_ae_stage2, _entries_barrier_9_io_y_ae_stage2}; // @[package.scala:45:27, :267:25] wire [1:0] stage1_bypass_hi_hi_hi = {_entries_barrier_12_io_y_ae_stage2, _entries_barrier_11_io_y_ae_stage2}; // @[package.scala:45:27, :267:25] wire [3:0] stage1_bypass_hi_hi = {stage1_bypass_hi_hi_hi, stage1_bypass_hi_hi_lo}; // @[package.scala:45:27] wire [6:0] stage1_bypass_hi = {stage1_bypass_hi_hi, stage1_bypass_hi_lo}; // @[package.scala:45:27] wire [12:0] _stage1_bypass_T_3 = {stage1_bypass_hi, stage1_bypass_lo}; // @[package.scala:45:27] wire [12:0] _stage1_bypass_T_4 = _stage1_bypass_T_2 | _stage1_bypass_T_3; // @[package.scala:45:27] wire [1:0] r_array_lo_lo_hi = {_entries_barrier_2_io_y_sr, _entries_barrier_1_io_y_sr}; // @[package.scala:45:27, :267:25] wire [2:0] r_array_lo_lo = {r_array_lo_lo_hi, _entries_barrier_io_y_sr}; // @[package.scala:45:27, :267:25] wire [1:0] r_array_lo_hi_hi = {_entries_barrier_5_io_y_sr, _entries_barrier_4_io_y_sr}; // @[package.scala:45:27, :267:25] wire [2:0] r_array_lo_hi = {r_array_lo_hi_hi, _entries_barrier_3_io_y_sr}; // @[package.scala:45:27, :267:25] wire [5:0] r_array_lo = {r_array_lo_hi, r_array_lo_lo}; // @[package.scala:45:27] wire [1:0] r_array_hi_lo_hi = {_entries_barrier_8_io_y_sr, _entries_barrier_7_io_y_sr}; // @[package.scala:45:27, :267:25] wire [2:0] r_array_hi_lo = {r_array_hi_lo_hi, _entries_barrier_6_io_y_sr}; // @[package.scala:45:27, :267:25] wire [1:0] r_array_hi_hi_lo = {_entries_barrier_10_io_y_sr, _entries_barrier_9_io_y_sr}; // @[package.scala:45:27, :267:25] wire [1:0] r_array_hi_hi_hi = {_entries_barrier_12_io_y_sr, _entries_barrier_11_io_y_sr}; // @[package.scala:45:27, :267:25] wire [3:0] r_array_hi_hi = {r_array_hi_hi_hi, r_array_hi_hi_lo}; // @[package.scala:45:27] wire [6:0] r_array_hi = {r_array_hi_hi, r_array_hi_lo}; // @[package.scala:45:27] wire [12:0] _r_array_T = {r_array_hi, r_array_lo}; // @[package.scala:45:27] wire [1:0] _GEN_45 = {_entries_barrier_2_io_y_sx, _entries_barrier_1_io_y_sx}; // @[package.scala:45:27, :267:25] wire [1:0] r_array_lo_lo_hi_1; // @[package.scala:45:27] assign r_array_lo_lo_hi_1 = _GEN_45; // @[package.scala:45:27] wire [1:0] x_array_lo_lo_hi; // @[package.scala:45:27] assign x_array_lo_lo_hi = _GEN_45; // @[package.scala:45:27] wire [2:0] r_array_lo_lo_1 = {r_array_lo_lo_hi_1, _entries_barrier_io_y_sx}; // @[package.scala:45:27, :267:25] wire [1:0] _GEN_46 = {_entries_barrier_5_io_y_sx, _entries_barrier_4_io_y_sx}; // @[package.scala:45:27, :267:25] wire [1:0] r_array_lo_hi_hi_1; // @[package.scala:45:27] assign r_array_lo_hi_hi_1 = _GEN_46; // @[package.scala:45:27] wire [1:0] x_array_lo_hi_hi; // @[package.scala:45:27] assign x_array_lo_hi_hi = _GEN_46; // @[package.scala:45:27] wire [2:0] r_array_lo_hi_1 = {r_array_lo_hi_hi_1, _entries_barrier_3_io_y_sx}; // @[package.scala:45:27, :267:25] wire [5:0] r_array_lo_1 = {r_array_lo_hi_1, r_array_lo_lo_1}; // @[package.scala:45:27] wire [1:0] _GEN_47 = {_entries_barrier_8_io_y_sx, _entries_barrier_7_io_y_sx}; // @[package.scala:45:27, :267:25] wire [1:0] r_array_hi_lo_hi_1; // @[package.scala:45:27] assign r_array_hi_lo_hi_1 = _GEN_47; // @[package.scala:45:27] wire [1:0] x_array_hi_lo_hi; // @[package.scala:45:27] assign x_array_hi_lo_hi = _GEN_47; // @[package.scala:45:27] wire [2:0] r_array_hi_lo_1 = {r_array_hi_lo_hi_1, _entries_barrier_6_io_y_sx}; // @[package.scala:45:27, :267:25] wire [1:0] _GEN_48 = {_entries_barrier_10_io_y_sx, _entries_barrier_9_io_y_sx}; // @[package.scala:45:27, :267:25] wire [1:0] r_array_hi_hi_lo_1; // @[package.scala:45:27] assign r_array_hi_hi_lo_1 = _GEN_48; // @[package.scala:45:27] wire [1:0] x_array_hi_hi_lo; // @[package.scala:45:27] assign x_array_hi_hi_lo = _GEN_48; // @[package.scala:45:27] wire [1:0] _GEN_49 = {_entries_barrier_12_io_y_sx, _entries_barrier_11_io_y_sx}; // @[package.scala:45:27, :267:25] wire [1:0] r_array_hi_hi_hi_1; // @[package.scala:45:27] assign r_array_hi_hi_hi_1 = _GEN_49; // @[package.scala:45:27] wire [1:0] x_array_hi_hi_hi; // @[package.scala:45:27] assign x_array_hi_hi_hi = _GEN_49; // @[package.scala:45:27] wire [3:0] r_array_hi_hi_1 = {r_array_hi_hi_hi_1, r_array_hi_hi_lo_1}; // @[package.scala:45:27] wire [6:0] r_array_hi_1 = {r_array_hi_hi_1, r_array_hi_lo_1}; // @[package.scala:45:27] wire [12:0] _r_array_T_1 = {r_array_hi_1, r_array_lo_1}; // @[package.scala:45:27] wire [12:0] _r_array_T_2 = mxr ? _r_array_T_1 : 13'h0; // @[package.scala:45:27] wire [12:0] _r_array_T_3 = _r_array_T | _r_array_T_2; // @[package.scala:45:27] wire [12:0] _r_array_T_4 = priv_rw_ok & _r_array_T_3; // @[TLB.scala:513:70, :520:{41,69}] wire [12:0] _r_array_T_5 = _r_array_T_4; // @[TLB.scala:520:{41,113}] wire [13:0] r_array = {1'h1, _r_array_T_5}; // @[TLB.scala:520:{20,113}] wire [13:0] _pf_ld_array_T = r_array; // @[TLB.scala:520:20, :597:41] wire [1:0] w_array_lo_lo_hi = {_entries_barrier_2_io_y_sw, _entries_barrier_1_io_y_sw}; // @[package.scala:45:27, :267:25] wire [2:0] w_array_lo_lo = {w_array_lo_lo_hi, _entries_barrier_io_y_sw}; // @[package.scala:45:27, :267:25] wire [1:0] w_array_lo_hi_hi = {_entries_barrier_5_io_y_sw, _entries_barrier_4_io_y_sw}; // @[package.scala:45:27, :267:25] wire [2:0] w_array_lo_hi = {w_array_lo_hi_hi, _entries_barrier_3_io_y_sw}; // @[package.scala:45:27, :267:25] wire [5:0] w_array_lo = {w_array_lo_hi, w_array_lo_lo}; // @[package.scala:45:27] wire [1:0] w_array_hi_lo_hi = {_entries_barrier_8_io_y_sw, _entries_barrier_7_io_y_sw}; // @[package.scala:45:27, :267:25] wire [2:0] w_array_hi_lo = {w_array_hi_lo_hi, _entries_barrier_6_io_y_sw}; // @[package.scala:45:27, :267:25] wire [1:0] w_array_hi_hi_lo = {_entries_barrier_10_io_y_sw, _entries_barrier_9_io_y_sw}; // @[package.scala:45:27, :267:25] wire [1:0] w_array_hi_hi_hi = {_entries_barrier_12_io_y_sw, _entries_barrier_11_io_y_sw}; // @[package.scala:45:27, :267:25] wire [3:0] w_array_hi_hi = {w_array_hi_hi_hi, w_array_hi_hi_lo}; // @[package.scala:45:27] wire [6:0] w_array_hi = {w_array_hi_hi, w_array_hi_lo}; // @[package.scala:45:27] wire [12:0] _w_array_T = {w_array_hi, w_array_lo}; // @[package.scala:45:27] wire [12:0] _w_array_T_1 = priv_rw_ok & _w_array_T; // @[package.scala:45:27] wire [12:0] _w_array_T_2 = _w_array_T_1; // @[TLB.scala:521:{41,69}] wire [13:0] w_array = {1'h1, _w_array_T_2}; // @[TLB.scala:521:{20,69}] wire [2:0] x_array_lo_lo = {x_array_lo_lo_hi, _entries_barrier_io_y_sx}; // @[package.scala:45:27, :267:25] wire [2:0] x_array_lo_hi = {x_array_lo_hi_hi, _entries_barrier_3_io_y_sx}; // @[package.scala:45:27, :267:25] wire [5:0] x_array_lo = {x_array_lo_hi, x_array_lo_lo}; // @[package.scala:45:27] wire [2:0] x_array_hi_lo = {x_array_hi_lo_hi, _entries_barrier_6_io_y_sx}; // @[package.scala:45:27, :267:25] wire [3:0] x_array_hi_hi = {x_array_hi_hi_hi, x_array_hi_hi_lo}; // @[package.scala:45:27] wire [6:0] x_array_hi = {x_array_hi_hi, x_array_hi_lo}; // @[package.scala:45:27] wire [12:0] _x_array_T = {x_array_hi, x_array_lo}; // @[package.scala:45:27] wire [12:0] _x_array_T_1 = priv_x_ok & _x_array_T; // @[package.scala:45:27] wire [12:0] _x_array_T_2 = _x_array_T_1; // @[TLB.scala:522:{40,68}] wire [13:0] x_array = {1'h1, _x_array_T_2}; // @[TLB.scala:522:{20,68}] wire [1:0] hr_array_lo_lo_hi = {_entries_barrier_2_io_y_hr, _entries_barrier_1_io_y_hr}; // @[package.scala:45:27, :267:25] wire [2:0] hr_array_lo_lo = {hr_array_lo_lo_hi, _entries_barrier_io_y_hr}; // @[package.scala:45:27, :267:25] wire [1:0] hr_array_lo_hi_hi = {_entries_barrier_5_io_y_hr, _entries_barrier_4_io_y_hr}; // @[package.scala:45:27, :267:25] wire [2:0] hr_array_lo_hi = {hr_array_lo_hi_hi, _entries_barrier_3_io_y_hr}; // @[package.scala:45:27, :267:25] wire [5:0] hr_array_lo = {hr_array_lo_hi, hr_array_lo_lo}; // @[package.scala:45:27] wire [1:0] hr_array_hi_lo_hi = {_entries_barrier_8_io_y_hr, _entries_barrier_7_io_y_hr}; // @[package.scala:45:27, :267:25] wire [2:0] hr_array_hi_lo = {hr_array_hi_lo_hi, _entries_barrier_6_io_y_hr}; // @[package.scala:45:27, :267:25] wire [1:0] hr_array_hi_hi_lo = {_entries_barrier_10_io_y_hr, _entries_barrier_9_io_y_hr}; // @[package.scala:45:27, :267:25] wire [1:0] hr_array_hi_hi_hi = {_entries_barrier_12_io_y_hr, _entries_barrier_11_io_y_hr}; // @[package.scala:45:27, :267:25] wire [3:0] hr_array_hi_hi = {hr_array_hi_hi_hi, hr_array_hi_hi_lo}; // @[package.scala:45:27] wire [6:0] hr_array_hi = {hr_array_hi_hi, hr_array_hi_lo}; // @[package.scala:45:27] wire [12:0] _hr_array_T = {hr_array_hi, hr_array_lo}; // @[package.scala:45:27] wire [1:0] _GEN_50 = {_entries_barrier_2_io_y_hx, _entries_barrier_1_io_y_hx}; // @[package.scala:45:27, :267:25] wire [1:0] hr_array_lo_lo_hi_1; // @[package.scala:45:27] assign hr_array_lo_lo_hi_1 = _GEN_50; // @[package.scala:45:27] wire [1:0] hx_array_lo_lo_hi; // @[package.scala:45:27] assign hx_array_lo_lo_hi = _GEN_50; // @[package.scala:45:27] wire [2:0] hr_array_lo_lo_1 = {hr_array_lo_lo_hi_1, _entries_barrier_io_y_hx}; // @[package.scala:45:27, :267:25] wire [1:0] _GEN_51 = {_entries_barrier_5_io_y_hx, _entries_barrier_4_io_y_hx}; // @[package.scala:45:27, :267:25] wire [1:0] hr_array_lo_hi_hi_1; // @[package.scala:45:27] assign hr_array_lo_hi_hi_1 = _GEN_51; // @[package.scala:45:27] wire [1:0] hx_array_lo_hi_hi; // @[package.scala:45:27] assign hx_array_lo_hi_hi = _GEN_51; // @[package.scala:45:27] wire [2:0] hr_array_lo_hi_1 = {hr_array_lo_hi_hi_1, _entries_barrier_3_io_y_hx}; // @[package.scala:45:27, :267:25] wire [5:0] hr_array_lo_1 = {hr_array_lo_hi_1, hr_array_lo_lo_1}; // @[package.scala:45:27] wire [1:0] _GEN_52 = {_entries_barrier_8_io_y_hx, _entries_barrier_7_io_y_hx}; // @[package.scala:45:27, :267:25] wire [1:0] hr_array_hi_lo_hi_1; // @[package.scala:45:27] assign hr_array_hi_lo_hi_1 = _GEN_52; // @[package.scala:45:27] wire [1:0] hx_array_hi_lo_hi; // @[package.scala:45:27] assign hx_array_hi_lo_hi = _GEN_52; // @[package.scala:45:27] wire [2:0] hr_array_hi_lo_1 = {hr_array_hi_lo_hi_1, _entries_barrier_6_io_y_hx}; // @[package.scala:45:27, :267:25] wire [1:0] _GEN_53 = {_entries_barrier_10_io_y_hx, _entries_barrier_9_io_y_hx}; // @[package.scala:45:27, :267:25] wire [1:0] hr_array_hi_hi_lo_1; // @[package.scala:45:27] assign hr_array_hi_hi_lo_1 = _GEN_53; // @[package.scala:45:27] wire [1:0] hx_array_hi_hi_lo; // @[package.scala:45:27] assign hx_array_hi_hi_lo = _GEN_53; // @[package.scala:45:27] wire [1:0] _GEN_54 = {_entries_barrier_12_io_y_hx, _entries_barrier_11_io_y_hx}; // @[package.scala:45:27, :267:25] wire [1:0] hr_array_hi_hi_hi_1; // @[package.scala:45:27] assign hr_array_hi_hi_hi_1 = _GEN_54; // @[package.scala:45:27] wire [1:0] hx_array_hi_hi_hi; // @[package.scala:45:27] assign hx_array_hi_hi_hi = _GEN_54; // @[package.scala:45:27] wire [3:0] hr_array_hi_hi_1 = {hr_array_hi_hi_hi_1, hr_array_hi_hi_lo_1}; // @[package.scala:45:27] wire [6:0] hr_array_hi_1 = {hr_array_hi_hi_1, hr_array_hi_lo_1}; // @[package.scala:45:27] wire [12:0] _hr_array_T_1 = {hr_array_hi_1, hr_array_lo_1}; // @[package.scala:45:27] wire [12:0] _hr_array_T_2 = io_ptw_status_mxr_0 ? _hr_array_T_1 : 13'h0; // @[package.scala:45:27] wire [12:0] _hr_array_T_3 = _hr_array_T | _hr_array_T_2; // @[package.scala:45:27] wire [1:0] hw_array_lo_lo_hi = {_entries_barrier_2_io_y_hw, _entries_barrier_1_io_y_hw}; // @[package.scala:45:27, :267:25] wire [2:0] hw_array_lo_lo = {hw_array_lo_lo_hi, _entries_barrier_io_y_hw}; // @[package.scala:45:27, :267:25] wire [1:0] hw_array_lo_hi_hi = {_entries_barrier_5_io_y_hw, _entries_barrier_4_io_y_hw}; // @[package.scala:45:27, :267:25] wire [2:0] hw_array_lo_hi = {hw_array_lo_hi_hi, _entries_barrier_3_io_y_hw}; // @[package.scala:45:27, :267:25] wire [5:0] hw_array_lo = {hw_array_lo_hi, hw_array_lo_lo}; // @[package.scala:45:27] wire [1:0] hw_array_hi_lo_hi = {_entries_barrier_8_io_y_hw, _entries_barrier_7_io_y_hw}; // @[package.scala:45:27, :267:25] wire [2:0] hw_array_hi_lo = {hw_array_hi_lo_hi, _entries_barrier_6_io_y_hw}; // @[package.scala:45:27, :267:25] wire [1:0] hw_array_hi_hi_lo = {_entries_barrier_10_io_y_hw, _entries_barrier_9_io_y_hw}; // @[package.scala:45:27, :267:25] wire [1:0] hw_array_hi_hi_hi = {_entries_barrier_12_io_y_hw, _entries_barrier_11_io_y_hw}; // @[package.scala:45:27, :267:25] wire [3:0] hw_array_hi_hi = {hw_array_hi_hi_hi, hw_array_hi_hi_lo}; // @[package.scala:45:27] wire [6:0] hw_array_hi = {hw_array_hi_hi, hw_array_hi_lo}; // @[package.scala:45:27] wire [12:0] _hw_array_T = {hw_array_hi, hw_array_lo}; // @[package.scala:45:27] wire [2:0] hx_array_lo_lo = {hx_array_lo_lo_hi, _entries_barrier_io_y_hx}; // @[package.scala:45:27, :267:25] wire [2:0] hx_array_lo_hi = {hx_array_lo_hi_hi, _entries_barrier_3_io_y_hx}; // @[package.scala:45:27, :267:25] wire [5:0] hx_array_lo = {hx_array_lo_hi, hx_array_lo_lo}; // @[package.scala:45:27] wire [2:0] hx_array_hi_lo = {hx_array_hi_lo_hi, _entries_barrier_6_io_y_hx}; // @[package.scala:45:27, :267:25] wire [3:0] hx_array_hi_hi = {hx_array_hi_hi_hi, hx_array_hi_hi_lo}; // @[package.scala:45:27] wire [6:0] hx_array_hi = {hx_array_hi_hi, hx_array_hi_lo}; // @[package.scala:45:27] wire [12:0] _hx_array_T = {hx_array_hi, hx_array_lo}; // @[package.scala:45:27] wire [1:0] _pr_array_T = {2{prot_r}}; // @[TLB.scala:429:55, :529:26] wire [1:0] pr_array_lo_lo_hi = {_entries_barrier_2_io_y_pr, _entries_barrier_1_io_y_pr}; // @[package.scala:45:27, :267:25] wire [2:0] pr_array_lo_lo = {pr_array_lo_lo_hi, _entries_barrier_io_y_pr}; // @[package.scala:45:27, :267:25] wire [1:0] pr_array_lo_hi_hi = {_entries_barrier_5_io_y_pr, _entries_barrier_4_io_y_pr}; // @[package.scala:45:27, :267:25] wire [2:0] pr_array_lo_hi = {pr_array_lo_hi_hi, _entries_barrier_3_io_y_pr}; // @[package.scala:45:27, :267:25] wire [5:0] pr_array_lo = {pr_array_lo_hi, pr_array_lo_lo}; // @[package.scala:45:27] wire [1:0] pr_array_hi_lo_hi = {_entries_barrier_8_io_y_pr, _entries_barrier_7_io_y_pr}; // @[package.scala:45:27, :267:25] wire [2:0] pr_array_hi_lo = {pr_array_hi_lo_hi, _entries_barrier_6_io_y_pr}; // @[package.scala:45:27, :267:25] wire [1:0] pr_array_hi_hi_hi = {_entries_barrier_11_io_y_pr, _entries_barrier_10_io_y_pr}; // @[package.scala:45:27, :267:25] wire [2:0] pr_array_hi_hi = {pr_array_hi_hi_hi, _entries_barrier_9_io_y_pr}; // @[package.scala:45:27, :267:25] wire [5:0] pr_array_hi = {pr_array_hi_hi, pr_array_hi_lo}; // @[package.scala:45:27] wire [11:0] _pr_array_T_1 = {pr_array_hi, pr_array_lo}; // @[package.scala:45:27] wire [13:0] _pr_array_T_2 = {_pr_array_T, _pr_array_T_1}; // @[package.scala:45:27] wire [13:0] _GEN_55 = ptw_ae_array | final_ae_array; // @[TLB.scala:506:25, :507:27, :529:104] wire [13:0] _pr_array_T_3; // @[TLB.scala:529:104] assign _pr_array_T_3 = _GEN_55; // @[TLB.scala:529:104] wire [13:0] _pw_array_T_3; // @[TLB.scala:531:104] assign _pw_array_T_3 = _GEN_55; // @[TLB.scala:529:104, :531:104] wire [13:0] _px_array_T_3; // @[TLB.scala:533:104] assign _px_array_T_3 = _GEN_55; // @[TLB.scala:529:104, :533:104] wire [13:0] _pr_array_T_4 = ~_pr_array_T_3; // @[TLB.scala:529:{89,104}] wire [13:0] pr_array = _pr_array_T_2 & _pr_array_T_4; // @[TLB.scala:529:{21,87,89}] wire [1:0] _pw_array_T = {2{prot_w}}; // @[TLB.scala:430:55, :531:26] wire [1:0] pw_array_lo_lo_hi = {_entries_barrier_2_io_y_pw, _entries_barrier_1_io_y_pw}; // @[package.scala:45:27, :267:25] wire [2:0] pw_array_lo_lo = {pw_array_lo_lo_hi, _entries_barrier_io_y_pw}; // @[package.scala:45:27, :267:25] wire [1:0] pw_array_lo_hi_hi = {_entries_barrier_5_io_y_pw, _entries_barrier_4_io_y_pw}; // @[package.scala:45:27, :267:25] wire [2:0] pw_array_lo_hi = {pw_array_lo_hi_hi, _entries_barrier_3_io_y_pw}; // @[package.scala:45:27, :267:25] wire [5:0] pw_array_lo = {pw_array_lo_hi, pw_array_lo_lo}; // @[package.scala:45:27] wire [1:0] pw_array_hi_lo_hi = {_entries_barrier_8_io_y_pw, _entries_barrier_7_io_y_pw}; // @[package.scala:45:27, :267:25] wire [2:0] pw_array_hi_lo = {pw_array_hi_lo_hi, _entries_barrier_6_io_y_pw}; // @[package.scala:45:27, :267:25] wire [1:0] pw_array_hi_hi_hi = {_entries_barrier_11_io_y_pw, _entries_barrier_10_io_y_pw}; // @[package.scala:45:27, :267:25] wire [2:0] pw_array_hi_hi = {pw_array_hi_hi_hi, _entries_barrier_9_io_y_pw}; // @[package.scala:45:27, :267:25] wire [5:0] pw_array_hi = {pw_array_hi_hi, pw_array_hi_lo}; // @[package.scala:45:27] wire [11:0] _pw_array_T_1 = {pw_array_hi, pw_array_lo}; // @[package.scala:45:27] wire [13:0] _pw_array_T_2 = {_pw_array_T, _pw_array_T_1}; // @[package.scala:45:27] wire [13:0] _pw_array_T_4 = ~_pw_array_T_3; // @[TLB.scala:531:{89,104}] wire [13:0] pw_array = _pw_array_T_2 & _pw_array_T_4; // @[TLB.scala:531:{21,87,89}] wire [1:0] _px_array_T = {2{prot_x}}; // @[TLB.scala:434:55, :533:26] wire [1:0] px_array_lo_lo_hi = {_entries_barrier_2_io_y_px, _entries_barrier_1_io_y_px}; // @[package.scala:45:27, :267:25] wire [2:0] px_array_lo_lo = {px_array_lo_lo_hi, _entries_barrier_io_y_px}; // @[package.scala:45:27, :267:25] wire [1:0] px_array_lo_hi_hi = {_entries_barrier_5_io_y_px, _entries_barrier_4_io_y_px}; // @[package.scala:45:27, :267:25] wire [2:0] px_array_lo_hi = {px_array_lo_hi_hi, _entries_barrier_3_io_y_px}; // @[package.scala:45:27, :267:25] wire [5:0] px_array_lo = {px_array_lo_hi, px_array_lo_lo}; // @[package.scala:45:27] wire [1:0] px_array_hi_lo_hi = {_entries_barrier_8_io_y_px, _entries_barrier_7_io_y_px}; // @[package.scala:45:27, :267:25] wire [2:0] px_array_hi_lo = {px_array_hi_lo_hi, _entries_barrier_6_io_y_px}; // @[package.scala:45:27, :267:25] wire [1:0] px_array_hi_hi_hi = {_entries_barrier_11_io_y_px, _entries_barrier_10_io_y_px}; // @[package.scala:45:27, :267:25] wire [2:0] px_array_hi_hi = {px_array_hi_hi_hi, _entries_barrier_9_io_y_px}; // @[package.scala:45:27, :267:25] wire [5:0] px_array_hi = {px_array_hi_hi, px_array_hi_lo}; // @[package.scala:45:27] wire [11:0] _px_array_T_1 = {px_array_hi, px_array_lo}; // @[package.scala:45:27] wire [13:0] _px_array_T_2 = {_px_array_T, _px_array_T_1}; // @[package.scala:45:27] wire [13:0] _px_array_T_4 = ~_px_array_T_3; // @[TLB.scala:533:{89,104}] wire [13:0] px_array = _px_array_T_2 & _px_array_T_4; // @[TLB.scala:533:{21,87,89}] wire [1:0] _eff_array_T = {2{_pma_io_resp_eff}}; // @[TLB.scala:422:19, :535:27] wire [1:0] eff_array_lo_lo_hi = {_entries_barrier_2_io_y_eff, _entries_barrier_1_io_y_eff}; // @[package.scala:45:27, :267:25] wire [2:0] eff_array_lo_lo = {eff_array_lo_lo_hi, _entries_barrier_io_y_eff}; // @[package.scala:45:27, :267:25] wire [1:0] eff_array_lo_hi_hi = {_entries_barrier_5_io_y_eff, _entries_barrier_4_io_y_eff}; // @[package.scala:45:27, :267:25] wire [2:0] eff_array_lo_hi = {eff_array_lo_hi_hi, _entries_barrier_3_io_y_eff}; // @[package.scala:45:27, :267:25] wire [5:0] eff_array_lo = {eff_array_lo_hi, eff_array_lo_lo}; // @[package.scala:45:27] wire [1:0] eff_array_hi_lo_hi = {_entries_barrier_8_io_y_eff, _entries_barrier_7_io_y_eff}; // @[package.scala:45:27, :267:25] wire [2:0] eff_array_hi_lo = {eff_array_hi_lo_hi, _entries_barrier_6_io_y_eff}; // @[package.scala:45:27, :267:25] wire [1:0] eff_array_hi_hi_hi = {_entries_barrier_11_io_y_eff, _entries_barrier_10_io_y_eff}; // @[package.scala:45:27, :267:25] wire [2:0] eff_array_hi_hi = {eff_array_hi_hi_hi, _entries_barrier_9_io_y_eff}; // @[package.scala:45:27, :267:25] wire [5:0] eff_array_hi = {eff_array_hi_hi, eff_array_hi_lo}; // @[package.scala:45:27] wire [11:0] _eff_array_T_1 = {eff_array_hi, eff_array_lo}; // @[package.scala:45:27] wire [13:0] eff_array = {_eff_array_T, _eff_array_T_1}; // @[package.scala:45:27] wire [1:0] _c_array_T = {2{cacheable}}; // @[TLB.scala:425:41, :537:25] wire [1:0] _GEN_56 = {_entries_barrier_2_io_y_c, _entries_barrier_1_io_y_c}; // @[package.scala:45:27, :267:25] wire [1:0] c_array_lo_lo_hi; // @[package.scala:45:27] assign c_array_lo_lo_hi = _GEN_56; // @[package.scala:45:27] wire [1:0] prefetchable_array_lo_lo_hi; // @[package.scala:45:27] assign prefetchable_array_lo_lo_hi = _GEN_56; // @[package.scala:45:27] wire [2:0] c_array_lo_lo = {c_array_lo_lo_hi, _entries_barrier_io_y_c}; // @[package.scala:45:27, :267:25] wire [1:0] _GEN_57 = {_entries_barrier_5_io_y_c, _entries_barrier_4_io_y_c}; // @[package.scala:45:27, :267:25] wire [1:0] c_array_lo_hi_hi; // @[package.scala:45:27] assign c_array_lo_hi_hi = _GEN_57; // @[package.scala:45:27] wire [1:0] prefetchable_array_lo_hi_hi; // @[package.scala:45:27] assign prefetchable_array_lo_hi_hi = _GEN_57; // @[package.scala:45:27] wire [2:0] c_array_lo_hi = {c_array_lo_hi_hi, _entries_barrier_3_io_y_c}; // @[package.scala:45:27, :267:25] wire [5:0] c_array_lo = {c_array_lo_hi, c_array_lo_lo}; // @[package.scala:45:27] wire [1:0] _GEN_58 = {_entries_barrier_8_io_y_c, _entries_barrier_7_io_y_c}; // @[package.scala:45:27, :267:25] wire [1:0] c_array_hi_lo_hi; // @[package.scala:45:27] assign c_array_hi_lo_hi = _GEN_58; // @[package.scala:45:27] wire [1:0] prefetchable_array_hi_lo_hi; // @[package.scala:45:27] assign prefetchable_array_hi_lo_hi = _GEN_58; // @[package.scala:45:27] wire [2:0] c_array_hi_lo = {c_array_hi_lo_hi, _entries_barrier_6_io_y_c}; // @[package.scala:45:27, :267:25] wire [1:0] _GEN_59 = {_entries_barrier_11_io_y_c, _entries_barrier_10_io_y_c}; // @[package.scala:45:27, :267:25] wire [1:0] c_array_hi_hi_hi; // @[package.scala:45:27] assign c_array_hi_hi_hi = _GEN_59; // @[package.scala:45:27] wire [1:0] prefetchable_array_hi_hi_hi; // @[package.scala:45:27] assign prefetchable_array_hi_hi_hi = _GEN_59; // @[package.scala:45:27] wire [2:0] c_array_hi_hi = {c_array_hi_hi_hi, _entries_barrier_9_io_y_c}; // @[package.scala:45:27, :267:25] wire [5:0] c_array_hi = {c_array_hi_hi, c_array_hi_lo}; // @[package.scala:45:27] wire [11:0] _c_array_T_1 = {c_array_hi, c_array_lo}; // @[package.scala:45:27] wire [13:0] c_array = {_c_array_T, _c_array_T_1}; // @[package.scala:45:27] wire [13:0] lrscAllowed = c_array; // @[TLB.scala:537:20, :580:24] wire [1:0] _ppp_array_T = {2{_pma_io_resp_pp}}; // @[TLB.scala:422:19, :539:27] wire [1:0] ppp_array_lo_lo_hi = {_entries_barrier_2_io_y_ppp, _entries_barrier_1_io_y_ppp}; // @[package.scala:45:27, :267:25] wire [2:0] ppp_array_lo_lo = {ppp_array_lo_lo_hi, _entries_barrier_io_y_ppp}; // @[package.scala:45:27, :267:25] wire [1:0] ppp_array_lo_hi_hi = {_entries_barrier_5_io_y_ppp, _entries_barrier_4_io_y_ppp}; // @[package.scala:45:27, :267:25] wire [2:0] ppp_array_lo_hi = {ppp_array_lo_hi_hi, _entries_barrier_3_io_y_ppp}; // @[package.scala:45:27, :267:25] wire [5:0] ppp_array_lo = {ppp_array_lo_hi, ppp_array_lo_lo}; // @[package.scala:45:27] wire [1:0] ppp_array_hi_lo_hi = {_entries_barrier_8_io_y_ppp, _entries_barrier_7_io_y_ppp}; // @[package.scala:45:27, :267:25] wire [2:0] ppp_array_hi_lo = {ppp_array_hi_lo_hi, _entries_barrier_6_io_y_ppp}; // @[package.scala:45:27, :267:25] wire [1:0] ppp_array_hi_hi_hi = {_entries_barrier_11_io_y_ppp, _entries_barrier_10_io_y_ppp}; // @[package.scala:45:27, :267:25] wire [2:0] ppp_array_hi_hi = {ppp_array_hi_hi_hi, _entries_barrier_9_io_y_ppp}; // @[package.scala:45:27, :267:25] wire [5:0] ppp_array_hi = {ppp_array_hi_hi, ppp_array_hi_lo}; // @[package.scala:45:27] wire [11:0] _ppp_array_T_1 = {ppp_array_hi, ppp_array_lo}; // @[package.scala:45:27] wire [13:0] ppp_array = {_ppp_array_T, _ppp_array_T_1}; // @[package.scala:45:27] wire [1:0] _paa_array_T = {2{_pma_io_resp_aa}}; // @[TLB.scala:422:19, :541:27] wire [1:0] paa_array_lo_lo_hi = {_entries_barrier_2_io_y_paa, _entries_barrier_1_io_y_paa}; // @[package.scala:45:27, :267:25] wire [2:0] paa_array_lo_lo = {paa_array_lo_lo_hi, _entries_barrier_io_y_paa}; // @[package.scala:45:27, :267:25] wire [1:0] paa_array_lo_hi_hi = {_entries_barrier_5_io_y_paa, _entries_barrier_4_io_y_paa}; // @[package.scala:45:27, :267:25] wire [2:0] paa_array_lo_hi = {paa_array_lo_hi_hi, _entries_barrier_3_io_y_paa}; // @[package.scala:45:27, :267:25] wire [5:0] paa_array_lo = {paa_array_lo_hi, paa_array_lo_lo}; // @[package.scala:45:27] wire [1:0] paa_array_hi_lo_hi = {_entries_barrier_8_io_y_paa, _entries_barrier_7_io_y_paa}; // @[package.scala:45:27, :267:25] wire [2:0] paa_array_hi_lo = {paa_array_hi_lo_hi, _entries_barrier_6_io_y_paa}; // @[package.scala:45:27, :267:25] wire [1:0] paa_array_hi_hi_hi = {_entries_barrier_11_io_y_paa, _entries_barrier_10_io_y_paa}; // @[package.scala:45:27, :267:25] wire [2:0] paa_array_hi_hi = {paa_array_hi_hi_hi, _entries_barrier_9_io_y_paa}; // @[package.scala:45:27, :267:25] wire [5:0] paa_array_hi = {paa_array_hi_hi, paa_array_hi_lo}; // @[package.scala:45:27] wire [11:0] _paa_array_T_1 = {paa_array_hi, paa_array_lo}; // @[package.scala:45:27] wire [13:0] paa_array = {_paa_array_T, _paa_array_T_1}; // @[package.scala:45:27] wire [1:0] _pal_array_T = {2{_pma_io_resp_al}}; // @[TLB.scala:422:19, :543:27] wire [1:0] pal_array_lo_lo_hi = {_entries_barrier_2_io_y_pal, _entries_barrier_1_io_y_pal}; // @[package.scala:45:27, :267:25] wire [2:0] pal_array_lo_lo = {pal_array_lo_lo_hi, _entries_barrier_io_y_pal}; // @[package.scala:45:27, :267:25] wire [1:0] pal_array_lo_hi_hi = {_entries_barrier_5_io_y_pal, _entries_barrier_4_io_y_pal}; // @[package.scala:45:27, :267:25] wire [2:0] pal_array_lo_hi = {pal_array_lo_hi_hi, _entries_barrier_3_io_y_pal}; // @[package.scala:45:27, :267:25] wire [5:0] pal_array_lo = {pal_array_lo_hi, pal_array_lo_lo}; // @[package.scala:45:27] wire [1:0] pal_array_hi_lo_hi = {_entries_barrier_8_io_y_pal, _entries_barrier_7_io_y_pal}; // @[package.scala:45:27, :267:25] wire [2:0] pal_array_hi_lo = {pal_array_hi_lo_hi, _entries_barrier_6_io_y_pal}; // @[package.scala:45:27, :267:25] wire [1:0] pal_array_hi_hi_hi = {_entries_barrier_11_io_y_pal, _entries_barrier_10_io_y_pal}; // @[package.scala:45:27, :267:25] wire [2:0] pal_array_hi_hi = {pal_array_hi_hi_hi, _entries_barrier_9_io_y_pal}; // @[package.scala:45:27, :267:25] wire [5:0] pal_array_hi = {pal_array_hi_hi, pal_array_hi_lo}; // @[package.scala:45:27] wire [11:0] _pal_array_T_1 = {pal_array_hi, pal_array_lo}; // @[package.scala:45:27] wire [13:0] pal_array = {_pal_array_T, _pal_array_T_1}; // @[package.scala:45:27] wire [13:0] ppp_array_if_cached = ppp_array | c_array; // @[TLB.scala:537:20, :539:22, :544:39] wire [13:0] paa_array_if_cached = paa_array | c_array; // @[TLB.scala:537:20, :541:22, :545:39] wire [13:0] pal_array_if_cached = pal_array | c_array; // @[TLB.scala:537:20, :543:22, :546:39] wire _prefetchable_array_T = cacheable & homogeneous; // @[TLBPermissions.scala:101:65] wire [1:0] _prefetchable_array_T_1 = {_prefetchable_array_T, 1'h0}; // @[TLB.scala:547:{43,59}] wire [2:0] prefetchable_array_lo_lo = {prefetchable_array_lo_lo_hi, _entries_barrier_io_y_c}; // @[package.scala:45:27, :267:25] wire [2:0] prefetchable_array_lo_hi = {prefetchable_array_lo_hi_hi, _entries_barrier_3_io_y_c}; // @[package.scala:45:27, :267:25] wire [5:0] prefetchable_array_lo = {prefetchable_array_lo_hi, prefetchable_array_lo_lo}; // @[package.scala:45:27] wire [2:0] prefetchable_array_hi_lo = {prefetchable_array_hi_lo_hi, _entries_barrier_6_io_y_c}; // @[package.scala:45:27, :267:25] wire [2:0] prefetchable_array_hi_hi = {prefetchable_array_hi_hi_hi, _entries_barrier_9_io_y_c}; // @[package.scala:45:27, :267:25] wire [5:0] prefetchable_array_hi = {prefetchable_array_hi_hi, prefetchable_array_hi_lo}; // @[package.scala:45:27] wire [11:0] _prefetchable_array_T_2 = {prefetchable_array_hi, prefetchable_array_lo}; // @[package.scala:45:27] wire [13:0] prefetchable_array = {_prefetchable_array_T_1, _prefetchable_array_T_2}; // @[package.scala:45:27] wire [39:0] _misaligned_T_3 = {37'h0, io_req_bits_vaddr_0[2:0]}; // @[TLB.scala:318:7, :550:39] wire misaligned = |_misaligned_T_3; // @[TLB.scala:550:{39,77}] assign _io_resp_ma_ld_T = misaligned; // @[TLB.scala:550:77, :645:31] wire _bad_va_T = vm_enabled & stage1_en; // @[TLB.scala:374:29, :399:61, :568:21] wire [39:0] bad_va_maskedVAddr = io_req_bits_vaddr_0 & 40'hC000000000; // @[TLB.scala:318:7, :559:43] wire _bad_va_T_2 = bad_va_maskedVAddr == 40'h0; // @[TLB.scala:559:43, :560:51] wire _bad_va_T_3 = bad_va_maskedVAddr == 40'hC000000000; // @[TLB.scala:559:43, :560:86] wire _bad_va_T_4 = _bad_va_T_3; // @[TLB.scala:560:{71,86}] wire _bad_va_T_5 = _bad_va_T_2 | _bad_va_T_4; // @[TLB.scala:560:{51,59,71}] wire _bad_va_T_6 = ~_bad_va_T_5; // @[TLB.scala:560:{37,59}] wire _bad_va_T_7 = _bad_va_T_6; // @[TLB.scala:560:{34,37}] wire bad_va = _bad_va_T & _bad_va_T_7; // @[TLB.scala:560:34, :568:{21,34}] wire _io_resp_pf_ld_T = bad_va; // @[TLB.scala:568:34, :633:28] wire [13:0] _ae_array_T = misaligned ? eff_array : 14'h0; // @[TLB.scala:535:22, :550:77, :582:8] wire [13:0] ae_array = _ae_array_T; // @[TLB.scala:582:{8,37}] wire [13:0] _ae_array_T_1 = ~lrscAllowed; // @[TLB.scala:580:24, :583:19] wire [13:0] _ae_ld_array_T = ~pr_array; // @[TLB.scala:529:87, :586:46] wire [13:0] _ae_ld_array_T_1 = ae_array | _ae_ld_array_T; // @[TLB.scala:582:37, :586:{44,46}] wire [13:0] ae_ld_array = _ae_ld_array_T_1; // @[TLB.scala:586:{24,44}] wire [13:0] _ae_st_array_T = ~pw_array; // @[TLB.scala:531:87, :588:37] wire [13:0] _ae_st_array_T_1 = ae_array | _ae_st_array_T; // @[TLB.scala:582:37, :588:{35,37}] wire [13:0] _ae_st_array_T_3 = ~ppp_array_if_cached; // @[TLB.scala:544:39, :589:26] wire [13:0] _ae_st_array_T_6 = ~pal_array_if_cached; // @[TLB.scala:546:39, :590:26] wire [13:0] _ae_st_array_T_9 = ~paa_array_if_cached; // @[TLB.scala:545:39, :591:29] wire [13:0] _must_alloc_array_T = ~ppp_array; // @[TLB.scala:539:22, :593:26] wire [13:0] _must_alloc_array_T_2 = ~pal_array; // @[TLB.scala:543:22, :594:26] wire [13:0] _must_alloc_array_T_5 = ~paa_array; // @[TLB.scala:541:22, :595:29] wire [13:0] _pf_ld_array_T_1 = ~_pf_ld_array_T; // @[TLB.scala:597:{37,41}] wire [13:0] _pf_ld_array_T_2 = ~ptw_ae_array; // @[TLB.scala:506:25, :597:73] wire [13:0] _pf_ld_array_T_3 = _pf_ld_array_T_1 & _pf_ld_array_T_2; // @[TLB.scala:597:{37,71,73}] wire [13:0] _pf_ld_array_T_4 = _pf_ld_array_T_3 | ptw_pf_array; // @[TLB.scala:508:25, :597:{71,88}] wire [13:0] _pf_ld_array_T_5 = ~ptw_gf_array; // @[TLB.scala:509:25, :597:106] wire [13:0] _pf_ld_array_T_6 = _pf_ld_array_T_4 & _pf_ld_array_T_5; // @[TLB.scala:597:{88,104,106}] wire [13:0] pf_ld_array = _pf_ld_array_T_6; // @[TLB.scala:597:{24,104}] wire [13:0] _pf_st_array_T = ~w_array; // @[TLB.scala:521:20, :598:44] wire [13:0] _pf_st_array_T_1 = ~ptw_ae_array; // @[TLB.scala:506:25, :597:73, :598:55] wire [13:0] _pf_st_array_T_2 = _pf_st_array_T & _pf_st_array_T_1; // @[TLB.scala:598:{44,53,55}] wire [13:0] _pf_st_array_T_3 = _pf_st_array_T_2 | ptw_pf_array; // @[TLB.scala:508:25, :598:{53,70}] wire [13:0] _pf_st_array_T_4 = ~ptw_gf_array; // @[TLB.scala:509:25, :597:106, :598:88] wire [13:0] _pf_st_array_T_5 = _pf_st_array_T_3 & _pf_st_array_T_4; // @[TLB.scala:598:{70,86,88}] wire [13:0] _pf_inst_array_T = ~x_array; // @[TLB.scala:522:20, :599:25] wire [13:0] _pf_inst_array_T_1 = ~ptw_ae_array; // @[TLB.scala:506:25, :597:73, :599:36] wire [13:0] _pf_inst_array_T_2 = _pf_inst_array_T & _pf_inst_array_T_1; // @[TLB.scala:599:{25,34,36}] wire [13:0] _pf_inst_array_T_3 = _pf_inst_array_T_2 | ptw_pf_array; // @[TLB.scala:508:25, :599:{34,51}] wire [13:0] _pf_inst_array_T_4 = ~ptw_gf_array; // @[TLB.scala:509:25, :597:106, :599:69] wire [13:0] pf_inst_array = _pf_inst_array_T_3 & _pf_inst_array_T_4; // @[TLB.scala:599:{51,67,69}] wire [13:0] _gf_ld_array_T_4 = ~ptw_ae_array; // @[TLB.scala:506:25, :597:73, :600:100] wire [13:0] _gf_ld_array_T_5 = _gf_ld_array_T_3 & _gf_ld_array_T_4; // @[TLB.scala:600:{82,98,100}] wire [13:0] _gf_st_array_T_3 = ~ptw_ae_array; // @[TLB.scala:506:25, :597:73, :601:81] wire [13:0] _gf_st_array_T_4 = _gf_st_array_T_2 & _gf_st_array_T_3; // @[TLB.scala:601:{63,79,81}] wire [13:0] _gf_inst_array_T_2 = ~ptw_ae_array; // @[TLB.scala:506:25, :597:73, :602:64] wire [13:0] _gf_inst_array_T_3 = _gf_inst_array_T_1 & _gf_inst_array_T_2; // @[TLB.scala:602:{46,62,64}] wire _gpa_hits_hit_mask_T = r_gpa_vpn == vpn; // @[TLB.scala:335:30, :364:22, :606:73] wire _gpa_hits_hit_mask_T_1 = r_gpa_valid & _gpa_hits_hit_mask_T; // @[TLB.scala:362:24, :606:{60,73}] wire [11:0] _gpa_hits_hit_mask_T_2 = {12{_gpa_hits_hit_mask_T_1}}; // @[TLB.scala:606:{24,60}] wire tlb_hit_if_not_gpa_miss = |real_hits; // @[package.scala:45:27] wire tlb_hit = |_tlb_hit_T; // @[TLB.scala:611:{28,40}] wire _tlb_miss_T_2 = ~bad_va; // @[TLB.scala:568:34, :613:56] wire _tlb_miss_T_3 = _tlb_miss_T_1 & _tlb_miss_T_2; // @[TLB.scala:613:{29,53,56}] wire _tlb_miss_T_4 = ~tlb_hit; // @[TLB.scala:611:40, :613:67] wire tlb_miss = _tlb_miss_T_3 & _tlb_miss_T_4; // @[TLB.scala:613:{53,64,67}] reg [6:0] state_vec_0; // @[Replacement.scala:305:17] reg [2:0] state_reg_1; // @[Replacement.scala:168:70] wire [1:0] _GEN_60 = {sector_hits_1, sector_hits_0}; // @[OneHot.scala:21:45] wire [1:0] lo_lo; // @[OneHot.scala:21:45] assign lo_lo = _GEN_60; // @[OneHot.scala:21:45] wire [1:0] r_sectored_hit_bits_lo_lo; // @[OneHot.scala:21:45] assign r_sectored_hit_bits_lo_lo = _GEN_60; // @[OneHot.scala:21:45] wire [1:0] _GEN_61 = {sector_hits_3, sector_hits_2}; // @[OneHot.scala:21:45] wire [1:0] lo_hi; // @[OneHot.scala:21:45] assign lo_hi = _GEN_61; // @[OneHot.scala:21:45] wire [1:0] r_sectored_hit_bits_lo_hi; // @[OneHot.scala:21:45] assign r_sectored_hit_bits_lo_hi = _GEN_61; // @[OneHot.scala:21:45] wire [3:0] lo = {lo_hi, lo_lo}; // @[OneHot.scala:21:45] wire [3:0] lo_1 = lo; // @[OneHot.scala:21:45, :31:18] wire [1:0] _GEN_62 = {sector_hits_5, sector_hits_4}; // @[OneHot.scala:21:45] wire [1:0] hi_lo; // @[OneHot.scala:21:45] assign hi_lo = _GEN_62; // @[OneHot.scala:21:45] wire [1:0] r_sectored_hit_bits_hi_lo; // @[OneHot.scala:21:45] assign r_sectored_hit_bits_hi_lo = _GEN_62; // @[OneHot.scala:21:45] wire [1:0] _GEN_63 = {sector_hits_7, sector_hits_6}; // @[OneHot.scala:21:45] wire [1:0] hi_hi; // @[OneHot.scala:21:45] assign hi_hi = _GEN_63; // @[OneHot.scala:21:45] wire [1:0] r_sectored_hit_bits_hi_hi; // @[OneHot.scala:21:45] assign r_sectored_hit_bits_hi_hi = _GEN_63; // @[OneHot.scala:21:45] wire [3:0] hi = {hi_hi, hi_lo}; // @[OneHot.scala:21:45] wire [3:0] hi_1 = hi; // @[OneHot.scala:21:45, :30:18] wire [3:0] _T_33 = hi_1 | lo_1; // @[OneHot.scala:30:18, :31:18, :32:28] wire [1:0] hi_2 = _T_33[3:2]; // @[OneHot.scala:30:18, :32:28] wire [1:0] lo_2 = _T_33[1:0]; // @[OneHot.scala:31:18, :32:28] wire [2:0] state_vec_0_touch_way_sized = {|hi_1, |hi_2, hi_2[1] | lo_2[1]}; // @[OneHot.scala:30:18, :31:18, :32:{10,14,28}] wire _state_vec_0_set_left_older_T = state_vec_0_touch_way_sized[2]; // @[package.scala:163:13] wire state_vec_0_set_left_older = ~_state_vec_0_set_left_older_T; // @[Replacement.scala:196:{33,43}] wire [2:0] state_vec_0_left_subtree_state = state_vec_0[5:3]; // @[package.scala:163:13] wire [2:0] r_sectored_repl_addr_left_subtree_state = state_vec_0[5:3]; // @[package.scala:163:13] wire [2:0] state_vec_0_right_subtree_state = state_vec_0[2:0]; // @[Replacement.scala:198:38, :305:17] wire [2:0] r_sectored_repl_addr_right_subtree_state = state_vec_0[2:0]; // @[Replacement.scala:198:38, :245:38, :305:17] wire [1:0] _state_vec_0_T = state_vec_0_touch_way_sized[1:0]; // @[package.scala:163:13] wire [1:0] _state_vec_0_T_11 = state_vec_0_touch_way_sized[1:0]; // @[package.scala:163:13] wire _state_vec_0_set_left_older_T_1 = _state_vec_0_T[1]; // @[package.scala:163:13] wire state_vec_0_set_left_older_1 = ~_state_vec_0_set_left_older_T_1; // @[Replacement.scala:196:{33,43}] wire state_vec_0_left_subtree_state_1 = state_vec_0_left_subtree_state[1]; // @[package.scala:163:13] wire state_vec_0_right_subtree_state_1 = state_vec_0_left_subtree_state[0]; // @[package.scala:163:13] wire _state_vec_0_T_1 = _state_vec_0_T[0]; // @[package.scala:163:13] wire _state_vec_0_T_5 = _state_vec_0_T[0]; // @[package.scala:163:13] wire _state_vec_0_T_2 = _state_vec_0_T_1; // @[package.scala:163:13] wire _state_vec_0_T_3 = ~_state_vec_0_T_2; // @[Replacement.scala:218:{7,17}] wire _state_vec_0_T_4 = state_vec_0_set_left_older_1 ? state_vec_0_left_subtree_state_1 : _state_vec_0_T_3; // @[package.scala:163:13] wire _state_vec_0_T_6 = _state_vec_0_T_5; // @[Replacement.scala:207:62, :218:17] wire _state_vec_0_T_7 = ~_state_vec_0_T_6; // @[Replacement.scala:218:{7,17}] wire _state_vec_0_T_8 = state_vec_0_set_left_older_1 ? _state_vec_0_T_7 : state_vec_0_right_subtree_state_1; // @[Replacement.scala:196:33, :198:38, :206:16, :218:7] wire [1:0] state_vec_0_hi = {state_vec_0_set_left_older_1, _state_vec_0_T_4}; // @[Replacement.scala:196:33, :202:12, :203:16] wire [2:0] _state_vec_0_T_9 = {state_vec_0_hi, _state_vec_0_T_8}; // @[Replacement.scala:202:12, :206:16] wire [2:0] _state_vec_0_T_10 = state_vec_0_set_left_older ? state_vec_0_left_subtree_state : _state_vec_0_T_9; // @[package.scala:163:13] wire _state_vec_0_set_left_older_T_2 = _state_vec_0_T_11[1]; // @[Replacement.scala:196:43, :207:62] wire state_vec_0_set_left_older_2 = ~_state_vec_0_set_left_older_T_2; // @[Replacement.scala:196:{33,43}] wire state_vec_0_left_subtree_state_2 = state_vec_0_right_subtree_state[1]; // @[package.scala:163:13] wire state_vec_0_right_subtree_state_2 = state_vec_0_right_subtree_state[0]; // @[Replacement.scala:198:38] wire _state_vec_0_T_12 = _state_vec_0_T_11[0]; // @[package.scala:163:13] wire _state_vec_0_T_16 = _state_vec_0_T_11[0]; // @[package.scala:163:13] wire _state_vec_0_T_13 = _state_vec_0_T_12; // @[package.scala:163:13] wire _state_vec_0_T_14 = ~_state_vec_0_T_13; // @[Replacement.scala:218:{7,17}] wire _state_vec_0_T_15 = state_vec_0_set_left_older_2 ? state_vec_0_left_subtree_state_2 : _state_vec_0_T_14; // @[package.scala:163:13] wire _state_vec_0_T_17 = _state_vec_0_T_16; // @[Replacement.scala:207:62, :218:17] wire _state_vec_0_T_18 = ~_state_vec_0_T_17; // @[Replacement.scala:218:{7,17}] wire _state_vec_0_T_19 = state_vec_0_set_left_older_2 ? _state_vec_0_T_18 : state_vec_0_right_subtree_state_2; // @[Replacement.scala:196:33, :198:38, :206:16, :218:7] wire [1:0] state_vec_0_hi_1 = {state_vec_0_set_left_older_2, _state_vec_0_T_15}; // @[Replacement.scala:196:33, :202:12, :203:16] wire [2:0] _state_vec_0_T_20 = {state_vec_0_hi_1, _state_vec_0_T_19}; // @[Replacement.scala:202:12, :206:16] wire [2:0] _state_vec_0_T_21 = state_vec_0_set_left_older ? _state_vec_0_T_20 : state_vec_0_right_subtree_state; // @[Replacement.scala:196:33, :198:38, :202:12, :206:16] wire [3:0] state_vec_0_hi_2 = {state_vec_0_set_left_older, _state_vec_0_T_10}; // @[Replacement.scala:196:33, :202:12, :203:16] wire [6:0] _state_vec_0_T_22 = {state_vec_0_hi_2, _state_vec_0_T_21}; // @[Replacement.scala:202:12, :206:16] wire [1:0] _GEN_64 = {superpage_hits_1, superpage_hits_0}; // @[OneHot.scala:21:45] wire [1:0] lo_3; // @[OneHot.scala:21:45] assign lo_3 = _GEN_64; // @[OneHot.scala:21:45] wire [1:0] r_superpage_hit_bits_lo; // @[OneHot.scala:21:45] assign r_superpage_hit_bits_lo = _GEN_64; // @[OneHot.scala:21:45] wire [1:0] lo_4 = lo_3; // @[OneHot.scala:21:45, :31:18] wire [1:0] _GEN_65 = {superpage_hits_3, superpage_hits_2}; // @[OneHot.scala:21:45] wire [1:0] hi_3; // @[OneHot.scala:21:45] assign hi_3 = _GEN_65; // @[OneHot.scala:21:45] wire [1:0] r_superpage_hit_bits_hi; // @[OneHot.scala:21:45] assign r_superpage_hit_bits_hi = _GEN_65; // @[OneHot.scala:21:45] wire [1:0] hi_4 = hi_3; // @[OneHot.scala:21:45, :30:18] wire [1:0] state_reg_touch_way_sized = {|hi_4, hi_4[1] | lo_4[1]}; // @[OneHot.scala:30:18, :31:18, :32:{10,14,28}] wire _state_reg_set_left_older_T = state_reg_touch_way_sized[1]; // @[package.scala:163:13] wire state_reg_set_left_older = ~_state_reg_set_left_older_T; // @[Replacement.scala:196:{33,43}] wire state_reg_left_subtree_state = state_reg_1[1]; // @[package.scala:163:13] wire r_superpage_repl_addr_left_subtree_state = state_reg_1[1]; // @[package.scala:163:13] wire state_reg_right_subtree_state = state_reg_1[0]; // @[Replacement.scala:168:70, :198:38] wire r_superpage_repl_addr_right_subtree_state = state_reg_1[0]; // @[Replacement.scala:168:70, :198:38, :245:38] wire _state_reg_T = state_reg_touch_way_sized[0]; // @[package.scala:163:13] wire _state_reg_T_4 = state_reg_touch_way_sized[0]; // @[package.scala:163:13] wire _state_reg_T_1 = _state_reg_T; // @[package.scala:163:13] wire _state_reg_T_2 = ~_state_reg_T_1; // @[Replacement.scala:218:{7,17}] wire _state_reg_T_3 = state_reg_set_left_older ? state_reg_left_subtree_state : _state_reg_T_2; // @[package.scala:163:13] wire _state_reg_T_5 = _state_reg_T_4; // @[Replacement.scala:207:62, :218:17] wire _state_reg_T_6 = ~_state_reg_T_5; // @[Replacement.scala:218:{7,17}] wire _state_reg_T_7 = state_reg_set_left_older ? _state_reg_T_6 : state_reg_right_subtree_state; // @[Replacement.scala:196:33, :198:38, :206:16, :218:7] wire [1:0] state_reg_hi = {state_reg_set_left_older, _state_reg_T_3}; // @[Replacement.scala:196:33, :202:12, :203:16] wire [2:0] _state_reg_T_8 = {state_reg_hi, _state_reg_T_7}; // @[Replacement.scala:202:12, :206:16] wire [5:0] _multipleHits_T = real_hits[5:0]; // @[package.scala:45:27] wire [2:0] _multipleHits_T_1 = _multipleHits_T[2:0]; // @[Misc.scala:181:37] wire _multipleHits_T_2 = _multipleHits_T_1[0]; // @[Misc.scala:181:37] wire multipleHits_leftOne = _multipleHits_T_2; // @[Misc.scala:178:18, :181:37] wire [1:0] _multipleHits_T_3 = _multipleHits_T_1[2:1]; // @[Misc.scala:181:37, :182:39] wire _multipleHits_T_4 = _multipleHits_T_3[0]; // @[Misc.scala:181:37, :182:39] wire multipleHits_leftOne_1 = _multipleHits_T_4; // @[Misc.scala:178:18, :181:37] wire _multipleHits_T_5 = _multipleHits_T_3[1]; // @[Misc.scala:182:39] wire multipleHits_rightOne = _multipleHits_T_5; // @[Misc.scala:178:18, :182:39] wire multipleHits_rightOne_1 = multipleHits_leftOne_1 | multipleHits_rightOne; // @[Misc.scala:178:18, :183:16] wire _multipleHits_T_7 = multipleHits_leftOne_1 & multipleHits_rightOne; // @[Misc.scala:178:18, :183:61] wire multipleHits_rightTwo = _multipleHits_T_7; // @[Misc.scala:183:{49,61}] wire _multipleHits_T_8 = multipleHits_rightTwo; // @[Misc.scala:183:{37,49}] wire multipleHits_leftOne_2 = multipleHits_leftOne | multipleHits_rightOne_1; // @[Misc.scala:178:18, :183:16] wire _multipleHits_T_9 = multipleHits_leftOne & multipleHits_rightOne_1; // @[Misc.scala:178:18, :183:{16,61}] wire multipleHits_leftTwo = _multipleHits_T_8 | _multipleHits_T_9; // @[Misc.scala:183:{37,49,61}] wire [2:0] _multipleHits_T_10 = _multipleHits_T[5:3]; // @[Misc.scala:181:37, :182:39] wire _multipleHits_T_11 = _multipleHits_T_10[0]; // @[Misc.scala:181:37, :182:39] wire multipleHits_leftOne_3 = _multipleHits_T_11; // @[Misc.scala:178:18, :181:37] wire [1:0] _multipleHits_T_12 = _multipleHits_T_10[2:1]; // @[Misc.scala:182:39] wire _multipleHits_T_13 = _multipleHits_T_12[0]; // @[Misc.scala:181:37, :182:39] wire multipleHits_leftOne_4 = _multipleHits_T_13; // @[Misc.scala:178:18, :181:37] wire _multipleHits_T_14 = _multipleHits_T_12[1]; // @[Misc.scala:182:39] wire multipleHits_rightOne_2 = _multipleHits_T_14; // @[Misc.scala:178:18, :182:39] wire multipleHits_rightOne_3 = multipleHits_leftOne_4 | multipleHits_rightOne_2; // @[Misc.scala:178:18, :183:16] wire _multipleHits_T_16 = multipleHits_leftOne_4 & multipleHits_rightOne_2; // @[Misc.scala:178:18, :183:61] wire multipleHits_rightTwo_1 = _multipleHits_T_16; // @[Misc.scala:183:{49,61}] wire _multipleHits_T_17 = multipleHits_rightTwo_1; // @[Misc.scala:183:{37,49}] wire multipleHits_rightOne_4 = multipleHits_leftOne_3 | multipleHits_rightOne_3; // @[Misc.scala:178:18, :183:16] wire _multipleHits_T_18 = multipleHits_leftOne_3 & multipleHits_rightOne_3; // @[Misc.scala:178:18, :183:{16,61}] wire multipleHits_rightTwo_2 = _multipleHits_T_17 | _multipleHits_T_18; // @[Misc.scala:183:{37,49,61}] wire multipleHits_leftOne_5 = multipleHits_leftOne_2 | multipleHits_rightOne_4; // @[Misc.scala:183:16] wire _multipleHits_T_19 = multipleHits_leftTwo | multipleHits_rightTwo_2; // @[Misc.scala:183:{37,49}] wire _multipleHits_T_20 = multipleHits_leftOne_2 & multipleHits_rightOne_4; // @[Misc.scala:183:{16,61}] wire multipleHits_leftTwo_1 = _multipleHits_T_19 | _multipleHits_T_20; // @[Misc.scala:183:{37,49,61}] wire [6:0] _multipleHits_T_21 = real_hits[12:6]; // @[package.scala:45:27] wire [2:0] _multipleHits_T_22 = _multipleHits_T_21[2:0]; // @[Misc.scala:181:37, :182:39] wire _multipleHits_T_23 = _multipleHits_T_22[0]; // @[Misc.scala:181:37] wire multipleHits_leftOne_6 = _multipleHits_T_23; // @[Misc.scala:178:18, :181:37] wire [1:0] _multipleHits_T_24 = _multipleHits_T_22[2:1]; // @[Misc.scala:181:37, :182:39] wire _multipleHits_T_25 = _multipleHits_T_24[0]; // @[Misc.scala:181:37, :182:39] wire multipleHits_leftOne_7 = _multipleHits_T_25; // @[Misc.scala:178:18, :181:37] wire _multipleHits_T_26 = _multipleHits_T_24[1]; // @[Misc.scala:182:39] wire multipleHits_rightOne_5 = _multipleHits_T_26; // @[Misc.scala:178:18, :182:39] wire multipleHits_rightOne_6 = multipleHits_leftOne_7 | multipleHits_rightOne_5; // @[Misc.scala:178:18, :183:16] wire _multipleHits_T_28 = multipleHits_leftOne_7 & multipleHits_rightOne_5; // @[Misc.scala:178:18, :183:61] wire multipleHits_rightTwo_3 = _multipleHits_T_28; // @[Misc.scala:183:{49,61}] wire _multipleHits_T_29 = multipleHits_rightTwo_3; // @[Misc.scala:183:{37,49}] wire multipleHits_leftOne_8 = multipleHits_leftOne_6 | multipleHits_rightOne_6; // @[Misc.scala:178:18, :183:16] wire _multipleHits_T_30 = multipleHits_leftOne_6 & multipleHits_rightOne_6; // @[Misc.scala:178:18, :183:{16,61}] wire multipleHits_leftTwo_2 = _multipleHits_T_29 | _multipleHits_T_30; // @[Misc.scala:183:{37,49,61}] wire [3:0] _multipleHits_T_31 = _multipleHits_T_21[6:3]; // @[Misc.scala:182:39] wire [1:0] _multipleHits_T_32 = _multipleHits_T_31[1:0]; // @[Misc.scala:181:37, :182:39] wire _multipleHits_T_33 = _multipleHits_T_32[0]; // @[Misc.scala:181:37] wire multipleHits_leftOne_9 = _multipleHits_T_33; // @[Misc.scala:178:18, :181:37] wire _multipleHits_T_34 = _multipleHits_T_32[1]; // @[Misc.scala:181:37, :182:39] wire multipleHits_rightOne_7 = _multipleHits_T_34; // @[Misc.scala:178:18, :182:39] wire multipleHits_leftOne_10 = multipleHits_leftOne_9 | multipleHits_rightOne_7; // @[Misc.scala:178:18, :183:16] wire _multipleHits_T_36 = multipleHits_leftOne_9 & multipleHits_rightOne_7; // @[Misc.scala:178:18, :183:61] wire multipleHits_leftTwo_3 = _multipleHits_T_36; // @[Misc.scala:183:{49,61}] wire [1:0] _multipleHits_T_37 = _multipleHits_T_31[3:2]; // @[Misc.scala:182:39] wire _multipleHits_T_38 = _multipleHits_T_37[0]; // @[Misc.scala:181:37, :182:39] wire multipleHits_leftOne_11 = _multipleHits_T_38; // @[Misc.scala:178:18, :181:37] wire _multipleHits_T_39 = _multipleHits_T_37[1]; // @[Misc.scala:182:39] wire multipleHits_rightOne_8 = _multipleHits_T_39; // @[Misc.scala:178:18, :182:39] wire multipleHits_rightOne_9 = multipleHits_leftOne_11 | multipleHits_rightOne_8; // @[Misc.scala:178:18, :183:16] wire _multipleHits_T_41 = multipleHits_leftOne_11 & multipleHits_rightOne_8; // @[Misc.scala:178:18, :183:61] wire multipleHits_rightTwo_4 = _multipleHits_T_41; // @[Misc.scala:183:{49,61}] wire multipleHits_rightOne_10 = multipleHits_leftOne_10 | multipleHits_rightOne_9; // @[Misc.scala:183:16] wire _multipleHits_T_42 = multipleHits_leftTwo_3 | multipleHits_rightTwo_4; // @[Misc.scala:183:{37,49}] wire _multipleHits_T_43 = multipleHits_leftOne_10 & multipleHits_rightOne_9; // @[Misc.scala:183:{16,61}] wire multipleHits_rightTwo_5 = _multipleHits_T_42 | _multipleHits_T_43; // @[Misc.scala:183:{37,49,61}] wire multipleHits_rightOne_11 = multipleHits_leftOne_8 | multipleHits_rightOne_10; // @[Misc.scala:183:16] wire _multipleHits_T_44 = multipleHits_leftTwo_2 | multipleHits_rightTwo_5; // @[Misc.scala:183:{37,49}] wire _multipleHits_T_45 = multipleHits_leftOne_8 & multipleHits_rightOne_10; // @[Misc.scala:183:{16,61}] wire multipleHits_rightTwo_6 = _multipleHits_T_44 | _multipleHits_T_45; // @[Misc.scala:183:{37,49,61}] wire _multipleHits_T_46 = multipleHits_leftOne_5 | multipleHits_rightOne_11; // @[Misc.scala:183:16] wire _multipleHits_T_47 = multipleHits_leftTwo_1 | multipleHits_rightTwo_6; // @[Misc.scala:183:{37,49}] wire _multipleHits_T_48 = multipleHits_leftOne_5 & multipleHits_rightOne_11; // @[Misc.scala:183:{16,61}] wire multipleHits = _multipleHits_T_47 | _multipleHits_T_48; // @[Misc.scala:183:{37,49,61}] assign _io_req_ready_T = state == 2'h0; // @[TLB.scala:352:22, :631:25] assign io_req_ready = _io_req_ready_T; // @[TLB.scala:318:7, :631:25] wire [13:0] _io_resp_pf_ld_T_1 = pf_ld_array & hits; // @[TLB.scala:442:17, :597:24, :633:57] wire _io_resp_pf_ld_T_2 = |_io_resp_pf_ld_T_1; // @[TLB.scala:633:{57,65}] assign _io_resp_pf_ld_T_3 = _io_resp_pf_ld_T | _io_resp_pf_ld_T_2; // @[TLB.scala:633:{28,41,65}] assign io_resp_pf_ld_0 = _io_resp_pf_ld_T_3; // @[TLB.scala:318:7, :633:41] wire [13:0] _io_resp_pf_inst_T = pf_inst_array & hits; // @[TLB.scala:442:17, :599:67, :635:47] wire _io_resp_pf_inst_T_1 = |_io_resp_pf_inst_T; // @[TLB.scala:635:{47,55}] assign _io_resp_pf_inst_T_2 = bad_va | _io_resp_pf_inst_T_1; // @[TLB.scala:568:34, :635:{29,55}] assign io_resp_pf_inst_0 = _io_resp_pf_inst_T_2; // @[TLB.scala:318:7, :635:29] wire [13:0] _io_resp_ae_ld_T = ae_ld_array & hits; // @[TLB.scala:442:17, :586:24, :641:33] assign _io_resp_ae_ld_T_1 = |_io_resp_ae_ld_T; // @[TLB.scala:641:{33,41}] assign io_resp_ae_ld_0 = _io_resp_ae_ld_T_1; // @[TLB.scala:318:7, :641:41] wire [13:0] _io_resp_ae_inst_T = ~px_array; // @[TLB.scala:533:87, :643:23] wire [13:0] _io_resp_ae_inst_T_1 = _io_resp_ae_inst_T & hits; // @[TLB.scala:442:17, :643:{23,33}] assign _io_resp_ae_inst_T_2 = |_io_resp_ae_inst_T_1; // @[TLB.scala:643:{33,41}] assign io_resp_ae_inst_0 = _io_resp_ae_inst_T_2; // @[TLB.scala:318:7, :643:41] assign io_resp_ma_ld_0 = _io_resp_ma_ld_T; // @[TLB.scala:318:7, :645:31] wire [13:0] _io_resp_cacheable_T = c_array & hits; // @[TLB.scala:442:17, :537:20, :648:33] assign _io_resp_cacheable_T_1 = |_io_resp_cacheable_T; // @[TLB.scala:648:{33,41}] assign io_resp_cacheable_0 = _io_resp_cacheable_T_1; // @[TLB.scala:318:7, :648:41] wire [13:0] _io_resp_prefetchable_T = prefetchable_array & hits; // @[TLB.scala:442:17, :547:31, :650:47] wire _io_resp_prefetchable_T_1 = |_io_resp_prefetchable_T; // @[TLB.scala:650:{47,55}] assign _io_resp_prefetchable_T_2 = _io_resp_prefetchable_T_1; // @[TLB.scala:650:{55,59}] assign io_resp_prefetchable_0 = _io_resp_prefetchable_T_2; // @[TLB.scala:318:7, :650:59] wire _io_resp_miss_T_1 = _io_resp_miss_T | tlb_miss; // @[TLB.scala:613:64, :651:{29,52}] assign _io_resp_miss_T_2 = _io_resp_miss_T_1 | multipleHits; // @[Misc.scala:183:49] assign io_resp_miss_0 = _io_resp_miss_T_2; // @[TLB.scala:318:7, :651:64] assign _io_resp_paddr_T_1 = {ppn, _io_resp_paddr_T}; // @[Mux.scala:30:73] assign io_resp_paddr_0 = _io_resp_paddr_T_1; // @[TLB.scala:318:7, :652:23] wire [27:0] _io_resp_gpa_page_T_1 = {1'h0, vpn}; // @[TLB.scala:335:30, :657:36] wire [27:0] io_resp_gpa_page = _io_resp_gpa_page_T_1; // @[TLB.scala:657:{19,36}] wire [26:0] _io_resp_gpa_page_T_2 = r_gpa[38:12]; // @[TLB.scala:363:18, :657:58] wire [11:0] _io_resp_gpa_offset_T = r_gpa[11:0]; // @[TLB.scala:363:18, :658:47] wire [11:0] io_resp_gpa_offset = _io_resp_gpa_offset_T_1; // @[TLB.scala:658:{21,82}] assign _io_resp_gpa_T = {io_resp_gpa_page, io_resp_gpa_offset}; // @[TLB.scala:657:19, :658:21, :659:8] assign io_resp_gpa_0 = _io_resp_gpa_T; // @[TLB.scala:318:7, :659:8] assign io_ptw_req_valid_0 = _io_ptw_req_valid_T; // @[TLB.scala:318:7, :662:29] wire r_superpage_repl_addr_left_subtree_older = state_reg_1[2]; // @[Replacement.scala:168:70, :243:38] wire _r_superpage_repl_addr_T = r_superpage_repl_addr_left_subtree_state; // @[package.scala:163:13] wire _r_superpage_repl_addr_T_1 = r_superpage_repl_addr_right_subtree_state; // @[Replacement.scala:245:38, :262:12] wire _r_superpage_repl_addr_T_2 = r_superpage_repl_addr_left_subtree_older ? _r_superpage_repl_addr_T : _r_superpage_repl_addr_T_1; // @[Replacement.scala:243:38, :250:16, :262:12] wire [1:0] _r_superpage_repl_addr_T_3 = {r_superpage_repl_addr_left_subtree_older, _r_superpage_repl_addr_T_2}; // @[Replacement.scala:243:38, :249:12, :250:16] wire [1:0] r_superpage_repl_addr_valids_lo = {superpage_entries_1_valid_0, superpage_entries_0_valid_0}; // @[package.scala:45:27] wire [1:0] r_superpage_repl_addr_valids_hi = {superpage_entries_3_valid_0, superpage_entries_2_valid_0}; // @[package.scala:45:27] wire [3:0] r_superpage_repl_addr_valids = {r_superpage_repl_addr_valids_hi, r_superpage_repl_addr_valids_lo}; // @[package.scala:45:27] wire _r_superpage_repl_addr_T_4 = &r_superpage_repl_addr_valids; // @[package.scala:45:27] wire [3:0] _r_superpage_repl_addr_T_5 = ~r_superpage_repl_addr_valids; // @[package.scala:45:27] wire _r_superpage_repl_addr_T_6 = _r_superpage_repl_addr_T_5[0]; // @[OneHot.scala:48:45] wire _r_superpage_repl_addr_T_7 = _r_superpage_repl_addr_T_5[1]; // @[OneHot.scala:48:45] wire _r_superpage_repl_addr_T_8 = _r_superpage_repl_addr_T_5[2]; // @[OneHot.scala:48:45] wire _r_superpage_repl_addr_T_9 = _r_superpage_repl_addr_T_5[3]; // @[OneHot.scala:48:45] wire [1:0] _r_superpage_repl_addr_T_10 = {1'h1, ~_r_superpage_repl_addr_T_8}; // @[OneHot.scala:48:45] wire [1:0] _r_superpage_repl_addr_T_11 = _r_superpage_repl_addr_T_7 ? 2'h1 : _r_superpage_repl_addr_T_10; // @[OneHot.scala:48:45] wire [1:0] _r_superpage_repl_addr_T_12 = _r_superpage_repl_addr_T_6 ? 2'h0 : _r_superpage_repl_addr_T_11; // @[OneHot.scala:48:45] wire [1:0] _r_superpage_repl_addr_T_13 = _r_superpage_repl_addr_T_4 ? _r_superpage_repl_addr_T_3 : _r_superpage_repl_addr_T_12; // @[Mux.scala:50:70] wire r_sectored_repl_addr_left_subtree_older = state_vec_0[6]; // @[Replacement.scala:243:38, :305:17] wire r_sectored_repl_addr_left_subtree_older_1 = r_sectored_repl_addr_left_subtree_state[2]; // @[package.scala:163:13] wire r_sectored_repl_addr_left_subtree_state_1 = r_sectored_repl_addr_left_subtree_state[1]; // @[package.scala:163:13] wire _r_sectored_repl_addr_T = r_sectored_repl_addr_left_subtree_state_1; // @[package.scala:163:13] wire r_sectored_repl_addr_right_subtree_state_1 = r_sectored_repl_addr_left_subtree_state[0]; // @[package.scala:163:13] wire _r_sectored_repl_addr_T_1 = r_sectored_repl_addr_right_subtree_state_1; // @[Replacement.scala:245:38, :262:12] wire _r_sectored_repl_addr_T_2 = r_sectored_repl_addr_left_subtree_older_1 ? _r_sectored_repl_addr_T : _r_sectored_repl_addr_T_1; // @[Replacement.scala:243:38, :250:16, :262:12] wire [1:0] _r_sectored_repl_addr_T_3 = {r_sectored_repl_addr_left_subtree_older_1, _r_sectored_repl_addr_T_2}; // @[Replacement.scala:243:38, :249:12, :250:16] wire r_sectored_repl_addr_left_subtree_older_2 = r_sectored_repl_addr_right_subtree_state[2]; // @[Replacement.scala:243:38, :245:38] wire r_sectored_repl_addr_left_subtree_state_2 = r_sectored_repl_addr_right_subtree_state[1]; // @[package.scala:163:13] wire _r_sectored_repl_addr_T_4 = r_sectored_repl_addr_left_subtree_state_2; // @[package.scala:163:13] wire r_sectored_repl_addr_right_subtree_state_2 = r_sectored_repl_addr_right_subtree_state[0]; // @[Replacement.scala:245:38] wire _r_sectored_repl_addr_T_5 = r_sectored_repl_addr_right_subtree_state_2; // @[Replacement.scala:245:38, :262:12] wire _r_sectored_repl_addr_T_6 = r_sectored_repl_addr_left_subtree_older_2 ? _r_sectored_repl_addr_T_4 : _r_sectored_repl_addr_T_5; // @[Replacement.scala:243:38, :250:16, :262:12] wire [1:0] _r_sectored_repl_addr_T_7 = {r_sectored_repl_addr_left_subtree_older_2, _r_sectored_repl_addr_T_6}; // @[Replacement.scala:243:38, :249:12, :250:16] wire [1:0] _r_sectored_repl_addr_T_8 = r_sectored_repl_addr_left_subtree_older ? _r_sectored_repl_addr_T_3 : _r_sectored_repl_addr_T_7; // @[Replacement.scala:243:38, :249:12, :250:16] wire [2:0] _r_sectored_repl_addr_T_9 = {r_sectored_repl_addr_left_subtree_older, _r_sectored_repl_addr_T_8}; // @[Replacement.scala:243:38, :249:12, :250:16] wire _r_sectored_repl_addr_valids_T_1 = _r_sectored_repl_addr_valids_T | sectored_entries_0_0_valid_2; // @[package.scala:81:59] wire _r_sectored_repl_addr_valids_T_2 = _r_sectored_repl_addr_valids_T_1 | sectored_entries_0_0_valid_3; // @[package.scala:81:59] wire _r_sectored_repl_addr_valids_T_4 = _r_sectored_repl_addr_valids_T_3 | sectored_entries_0_1_valid_2; // @[package.scala:81:59] wire _r_sectored_repl_addr_valids_T_5 = _r_sectored_repl_addr_valids_T_4 | sectored_entries_0_1_valid_3; // @[package.scala:81:59] wire _r_sectored_repl_addr_valids_T_7 = _r_sectored_repl_addr_valids_T_6 | sectored_entries_0_2_valid_2; // @[package.scala:81:59] wire _r_sectored_repl_addr_valids_T_8 = _r_sectored_repl_addr_valids_T_7 | sectored_entries_0_2_valid_3; // @[package.scala:81:59] wire _r_sectored_repl_addr_valids_T_10 = _r_sectored_repl_addr_valids_T_9 | sectored_entries_0_3_valid_2; // @[package.scala:81:59] wire _r_sectored_repl_addr_valids_T_11 = _r_sectored_repl_addr_valids_T_10 | sectored_entries_0_3_valid_3; // @[package.scala:81:59] wire _r_sectored_repl_addr_valids_T_13 = _r_sectored_repl_addr_valids_T_12 | sectored_entries_0_4_valid_2; // @[package.scala:81:59] wire _r_sectored_repl_addr_valids_T_14 = _r_sectored_repl_addr_valids_T_13 | sectored_entries_0_4_valid_3; // @[package.scala:81:59] wire _r_sectored_repl_addr_valids_T_16 = _r_sectored_repl_addr_valids_T_15 | sectored_entries_0_5_valid_2; // @[package.scala:81:59] wire _r_sectored_repl_addr_valids_T_17 = _r_sectored_repl_addr_valids_T_16 | sectored_entries_0_5_valid_3; // @[package.scala:81:59] wire _r_sectored_repl_addr_valids_T_19 = _r_sectored_repl_addr_valids_T_18 | sectored_entries_0_6_valid_2; // @[package.scala:81:59] wire _r_sectored_repl_addr_valids_T_20 = _r_sectored_repl_addr_valids_T_19 | sectored_entries_0_6_valid_3; // @[package.scala:81:59] wire _r_sectored_repl_addr_valids_T_22 = _r_sectored_repl_addr_valids_T_21 | sectored_entries_0_7_valid_2; // @[package.scala:81:59] wire _r_sectored_repl_addr_valids_T_23 = _r_sectored_repl_addr_valids_T_22 | sectored_entries_0_7_valid_3; // @[package.scala:81:59] wire [1:0] r_sectored_repl_addr_valids_lo_lo = {_r_sectored_repl_addr_valids_T_5, _r_sectored_repl_addr_valids_T_2}; // @[package.scala:45:27, :81:59] wire [1:0] r_sectored_repl_addr_valids_lo_hi = {_r_sectored_repl_addr_valids_T_11, _r_sectored_repl_addr_valids_T_8}; // @[package.scala:45:27, :81:59] wire [3:0] r_sectored_repl_addr_valids_lo = {r_sectored_repl_addr_valids_lo_hi, r_sectored_repl_addr_valids_lo_lo}; // @[package.scala:45:27] wire [1:0] r_sectored_repl_addr_valids_hi_lo = {_r_sectored_repl_addr_valids_T_17, _r_sectored_repl_addr_valids_T_14}; // @[package.scala:45:27, :81:59] wire [1:0] r_sectored_repl_addr_valids_hi_hi = {_r_sectored_repl_addr_valids_T_23, _r_sectored_repl_addr_valids_T_20}; // @[package.scala:45:27, :81:59] wire [3:0] r_sectored_repl_addr_valids_hi = {r_sectored_repl_addr_valids_hi_hi, r_sectored_repl_addr_valids_hi_lo}; // @[package.scala:45:27] wire [7:0] r_sectored_repl_addr_valids = {r_sectored_repl_addr_valids_hi, r_sectored_repl_addr_valids_lo}; // @[package.scala:45:27] wire _r_sectored_repl_addr_T_10 = &r_sectored_repl_addr_valids; // @[package.scala:45:27] wire [7:0] _r_sectored_repl_addr_T_11 = ~r_sectored_repl_addr_valids; // @[package.scala:45:27] wire _r_sectored_repl_addr_T_12 = _r_sectored_repl_addr_T_11[0]; // @[OneHot.scala:48:45] wire _r_sectored_repl_addr_T_13 = _r_sectored_repl_addr_T_11[1]; // @[OneHot.scala:48:45] wire _r_sectored_repl_addr_T_14 = _r_sectored_repl_addr_T_11[2]; // @[OneHot.scala:48:45] wire _r_sectored_repl_addr_T_15 = _r_sectored_repl_addr_T_11[3]; // @[OneHot.scala:48:45] wire _r_sectored_repl_addr_T_16 = _r_sectored_repl_addr_T_11[4]; // @[OneHot.scala:48:45] wire _r_sectored_repl_addr_T_17 = _r_sectored_repl_addr_T_11[5]; // @[OneHot.scala:48:45] wire _r_sectored_repl_addr_T_18 = _r_sectored_repl_addr_T_11[6]; // @[OneHot.scala:48:45] wire _r_sectored_repl_addr_T_19 = _r_sectored_repl_addr_T_11[7]; // @[OneHot.scala:48:45] wire [2:0] _r_sectored_repl_addr_T_20 = {2'h3, ~_r_sectored_repl_addr_T_18}; // @[OneHot.scala:48:45] wire [2:0] _r_sectored_repl_addr_T_21 = _r_sectored_repl_addr_T_17 ? 3'h5 : _r_sectored_repl_addr_T_20; // @[OneHot.scala:48:45] wire [2:0] _r_sectored_repl_addr_T_22 = _r_sectored_repl_addr_T_16 ? 3'h4 : _r_sectored_repl_addr_T_21; // @[OneHot.scala:48:45] wire [2:0] _r_sectored_repl_addr_T_23 = _r_sectored_repl_addr_T_15 ? 3'h3 : _r_sectored_repl_addr_T_22; // @[OneHot.scala:48:45] wire [2:0] _r_sectored_repl_addr_T_24 = _r_sectored_repl_addr_T_14 ? 3'h2 : _r_sectored_repl_addr_T_23; // @[OneHot.scala:48:45] wire [2:0] _r_sectored_repl_addr_T_25 = _r_sectored_repl_addr_T_13 ? 3'h1 : _r_sectored_repl_addr_T_24; // @[OneHot.scala:48:45] wire [2:0] _r_sectored_repl_addr_T_26 = _r_sectored_repl_addr_T_12 ? 3'h0 : _r_sectored_repl_addr_T_25; // @[OneHot.scala:48:45] wire [2:0] _r_sectored_repl_addr_T_27 = _r_sectored_repl_addr_T_10 ? _r_sectored_repl_addr_T_9 : _r_sectored_repl_addr_T_26; // @[Mux.scala:50:70] wire _r_sectored_hit_valid_T = sector_hits_0 | sector_hits_1; // @[package.scala:81:59] wire _r_sectored_hit_valid_T_1 = _r_sectored_hit_valid_T | sector_hits_2; // @[package.scala:81:59] wire _r_sectored_hit_valid_T_2 = _r_sectored_hit_valid_T_1 | sector_hits_3; // @[package.scala:81:59] wire _r_sectored_hit_valid_T_3 = _r_sectored_hit_valid_T_2 | sector_hits_4; // @[package.scala:81:59] wire _r_sectored_hit_valid_T_4 = _r_sectored_hit_valid_T_3 | sector_hits_5; // @[package.scala:81:59] wire _r_sectored_hit_valid_T_5 = _r_sectored_hit_valid_T_4 | sector_hits_6; // @[package.scala:81:59] wire _r_sectored_hit_valid_T_6 = _r_sectored_hit_valid_T_5 | sector_hits_7; // @[package.scala:81:59] wire [3:0] r_sectored_hit_bits_lo = {r_sectored_hit_bits_lo_hi, r_sectored_hit_bits_lo_lo}; // @[OneHot.scala:21:45] wire [3:0] r_sectored_hit_bits_hi = {r_sectored_hit_bits_hi_hi, r_sectored_hit_bits_hi_lo}; // @[OneHot.scala:21:45] wire [7:0] _r_sectored_hit_bits_T = {r_sectored_hit_bits_hi, r_sectored_hit_bits_lo}; // @[OneHot.scala:21:45] wire [3:0] r_sectored_hit_bits_hi_1 = _r_sectored_hit_bits_T[7:4]; // @[OneHot.scala:21:45, :30:18] wire [3:0] r_sectored_hit_bits_lo_1 = _r_sectored_hit_bits_T[3:0]; // @[OneHot.scala:21:45, :31:18] wire _r_sectored_hit_bits_T_1 = |r_sectored_hit_bits_hi_1; // @[OneHot.scala:30:18, :32:14] wire [3:0] _r_sectored_hit_bits_T_2 = r_sectored_hit_bits_hi_1 | r_sectored_hit_bits_lo_1; // @[OneHot.scala:30:18, :31:18, :32:28] wire [1:0] r_sectored_hit_bits_hi_2 = _r_sectored_hit_bits_T_2[3:2]; // @[OneHot.scala:30:18, :32:28] wire [1:0] r_sectored_hit_bits_lo_2 = _r_sectored_hit_bits_T_2[1:0]; // @[OneHot.scala:31:18, :32:28] wire _r_sectored_hit_bits_T_3 = |r_sectored_hit_bits_hi_2; // @[OneHot.scala:30:18, :32:14] wire [1:0] _r_sectored_hit_bits_T_4 = r_sectored_hit_bits_hi_2 | r_sectored_hit_bits_lo_2; // @[OneHot.scala:30:18, :31:18, :32:28] wire _r_sectored_hit_bits_T_5 = _r_sectored_hit_bits_T_4[1]; // @[OneHot.scala:32:28] wire [1:0] _r_sectored_hit_bits_T_6 = {_r_sectored_hit_bits_T_3, _r_sectored_hit_bits_T_5}; // @[OneHot.scala:32:{10,14}] wire [2:0] _r_sectored_hit_bits_T_7 = {_r_sectored_hit_bits_T_1, _r_sectored_hit_bits_T_6}; // @[OneHot.scala:32:{10,14}] wire _r_superpage_hit_valid_T = superpage_hits_0 | superpage_hits_1; // @[package.scala:81:59] wire _r_superpage_hit_valid_T_1 = _r_superpage_hit_valid_T | superpage_hits_2; // @[package.scala:81:59] wire _r_superpage_hit_valid_T_2 = _r_superpage_hit_valid_T_1 | superpage_hits_3; // @[package.scala:81:59] wire [3:0] _r_superpage_hit_bits_T = {r_superpage_hit_bits_hi, r_superpage_hit_bits_lo}; // @[OneHot.scala:21:45] wire [1:0] r_superpage_hit_bits_hi_1 = _r_superpage_hit_bits_T[3:2]; // @[OneHot.scala:21:45, :30:18] wire [1:0] r_superpage_hit_bits_lo_1 = _r_superpage_hit_bits_T[1:0]; // @[OneHot.scala:21:45, :31:18] wire _r_superpage_hit_bits_T_1 = |r_superpage_hit_bits_hi_1; // @[OneHot.scala:30:18, :32:14] wire [1:0] _r_superpage_hit_bits_T_2 = r_superpage_hit_bits_hi_1 | r_superpage_hit_bits_lo_1; // @[OneHot.scala:30:18, :31:18, :32:28] wire _r_superpage_hit_bits_T_3 = _r_superpage_hit_bits_T_2[1]; // @[OneHot.scala:32:28] wire [1:0] _r_superpage_hit_bits_T_4 = {_r_superpage_hit_bits_T_1, _r_superpage_hit_bits_T_3}; // @[OneHot.scala:32:{10,14}] wire [1:0] _state_T = {1'h1, io_sfence_valid_0}; // @[TLB.scala:318:7, :704:45]

Generate the Verilog code corresponding to the following Chisel files. File Monitor.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceLine import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import freechips.rocketchip.diplomacy.EnableMonitors import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode} import freechips.rocketchip.util.PlusArg case class TLMonitorArgs(edge: TLEdge) abstract class TLMonitorBase(args: TLMonitorArgs) extends Module { val io = IO(new Bundle { val in = Input(new TLBundle(args.edge.bundle)) }) def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit legalize(io.in, args.edge, reset) } object TLMonitor { def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = { if (enable) { EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) } } else { node } } } class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args) { require (args.edge.params(TLMonitorStrictMode) || (! args.edge.params(TestplanTestType).formal)) val cover_prop_class = PropertyClass.Default //Like assert but can flip to being an assumption for formal verification def monAssert(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir, cond, message, PropertyClass.Default) } def assume(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir.flip, cond, message, PropertyClass.Default) } def extra = { args.edge.sourceInfo match { case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)" case _ => "" } } def visible(address: UInt, source: UInt, edge: TLEdge) = edge.client.clients.map { c => !c.sourceId.contains(source) || c.visibility.map(_.contains(address)).reduce(_ || _) }.reduce(_ && _) def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = { //switch this flag to turn on diplomacy in error messages def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n" monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra) // Reuse these subexpressions to save some firrtl lines val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility") //The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B //TODO: check for acquireT? when (bundle.opcode === TLMessages.AcquireBlock) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra) } when (bundle.opcode === TLMessages.AcquirePerm) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra) monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra) monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra) monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra) } } def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = { monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra) monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility") // Reuse these subexpressions to save some firrtl lines val address_ok = edge.manager.containsSafe(edge.address(bundle)) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source when (bundle.opcode === TLMessages.Probe) { assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra) assume (address_ok, "'B' channel Probe carries unmanaged address" + extra) assume (legal_source, "'B' channel Probe carries source that is not first source" + extra) assume (is_aligned, "'B' channel Probe address not aligned to size" + extra) assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra) assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra) assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra) monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra) monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra) monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra) monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra) } } def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = { monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val address_ok = edge.manager.containsSafe(edge.address(bundle)) monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility") when (bundle.opcode === TLMessages.ProbeAck) { monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra) } when (bundle.opcode === TLMessages.ProbeAckData) { monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.Release) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra) monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra) } when (bundle.opcode === TLMessages.ReleaseData) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.AccessAck) { monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra) } when (bundle.opcode === TLMessages.HintAck) { monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra) } } def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = { assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val sink_ok = bundle.sink < edge.manager.endSinkId.U val deny_put_ok = edge.manager.mayDenyPut.B val deny_get_ok = edge.manager.mayDenyGet.B when (bundle.opcode === TLMessages.ReleaseAck) { assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra) assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra) assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra) } when (bundle.opcode === TLMessages.Grant) { assume (source_ok, "'D' channel Grant carries invalid source ID" + extra) assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra) assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel Grant is denied" + extra) } when (bundle.opcode === TLMessages.GrantData) { assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra) assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra) assume (!bundle.denied || bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra) assume (deny_get_ok || !bundle.denied, "'D' channel GrantData is denied" + extra) } when (bundle.opcode === TLMessages.AccessAck) { assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel AccessAck is denied" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra) assume (!bundle.denied || bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra) assume (deny_get_ok || !bundle.denied, "'D' channel AccessAckData is denied" + extra) } when (bundle.opcode === TLMessages.HintAck) { assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel HintAck is denied" + extra) } } def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = { val sink_ok = bundle.sink < edge.manager.endSinkId.U monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra) } def legalizeFormat(bundle: TLBundle, edge: TLEdge) = { when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) } when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) } when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) } when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) } } else { monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra) monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra) monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra) } } def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = { val a_first = edge.first(a.bits, a.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (a.valid && !a_first) { monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra) monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra) monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra) monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra) monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra) } when (a.fire && a_first) { opcode := a.bits.opcode param := a.bits.param size := a.bits.size source := a.bits.source address := a.bits.address } } def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = { val b_first = edge.first(b.bits, b.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (b.valid && !b_first) { monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra) monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra) monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra) monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra) monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra) } when (b.fire && b_first) { opcode := b.bits.opcode param := b.bits.param size := b.bits.size source := b.bits.source address := b.bits.address } } def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = { // Symbolic variable val sym_source = Wire(UInt(edge.client.endSourceId.W)) // TODO: Connect sym_source to a fixed value for simulation and to a // free wire in formal sym_source := 0.U // Type casting Int to UInt val maxSourceId = Wire(UInt(edge.client.endSourceId.W)) maxSourceId := edge.client.endSourceId.U // Delayed verison of sym_source val sym_source_d = Reg(UInt(edge.client.endSourceId.W)) sym_source_d := sym_source // These will be constraints for FV setup Property( MonitorDirection.Monitor, (sym_source === sym_source_d), "sym_source should remain stable", PropertyClass.Default) Property( MonitorDirection.Monitor, (sym_source <= maxSourceId), "sym_source should take legal value", PropertyClass.Default) val my_resp_pend = RegInit(false.B) val my_opcode = Reg(UInt()) val my_size = Reg(UInt()) val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire) val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire) val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source) val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source) val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat) val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend) when (my_set_resp_pend) { my_resp_pend := true.B } .elsewhen (my_clr_resp_pend) { my_resp_pend := false.B } when (my_a_first_beat) { my_opcode := bundle.a.bits.opcode my_size := bundle.a.bits.size } val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size) val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode) val my_resp_opcode_legal = Wire(Bool()) when ((my_resp_opcode === TLMessages.Get) || (my_resp_opcode === TLMessages.ArithmeticData) || (my_resp_opcode === TLMessages.LogicalData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData) } .elsewhen ((my_resp_opcode === TLMessages.PutFullData) || (my_resp_opcode === TLMessages.PutPartialData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck) } .otherwise { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck) } monAssert (IfThen(my_resp_pend, !my_a_first_beat), "Request message should not be sent with a source ID, for which a response message" + "is already pending (not received until current cycle) for a prior request message" + "with the same source ID" + extra) assume (IfThen(my_clr_resp_pend, (my_set_resp_pend || my_resp_pend)), "Response message should be accepted with a source ID only if a request message with the" + "same source ID has been accepted or is being accepted in the current cycle" + extra) assume (IfThen(my_d_first_beat, (my_a_first_beat || my_resp_pend)), "Response message should be sent with a source ID only if a request message with the" + "same source ID has been accepted or is being sent in the current cycle" + extra) assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)), "If d_valid is 1, then d_size should be same as a_size of the corresponding request" + "message" + extra) assume (IfThen(my_d_first_beat, my_resp_opcode_legal), "If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" + "request message" + extra) } def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = { val c_first = edge.first(c.bits, c.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (c.valid && !c_first) { monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra) monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra) monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra) monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra) monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra) } when (c.fire && c_first) { opcode := c.bits.opcode param := c.bits.param size := c.bits.size source := c.bits.source address := c.bits.address } } def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = { val d_first = edge.first(d.bits, d.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val sink = Reg(UInt()) val denied = Reg(Bool()) when (d.valid && !d_first) { assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra) assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra) assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra) assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra) assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra) assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra) } when (d.fire && d_first) { opcode := d.bits.opcode param := d.bits.param size := d.bits.size source := d.bits.source sink := d.bits.sink denied := d.bits.denied } } def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = { legalizeMultibeatA(bundle.a, edge) legalizeMultibeatD(bundle.d, edge) if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { legalizeMultibeatB(bundle.b, edge) legalizeMultibeatC(bundle.c, edge) } } //This is left in for almond which doesn't adhere to the tilelink protocol @deprecated("Use legalizeADSource instead if possible","") def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.client.endSourceId.W)) val a_first = edge.first(bundle.a.bits, bundle.a.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val a_set = WireInit(0.U(edge.client.endSourceId.W)) when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) assume((a_set | inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra) } if (edge.manager.minLatency > 0) { assume(a_set =/= d_clr || !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight | a_set) & ~d_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") assert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = { val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size) val log_a_size_bus_size = log2Ceil(a_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error inflight.suggestName("inflight") val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) inflight_opcodes.suggestName("inflight_opcodes") val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) inflight_sizes.suggestName("inflight_sizes") val a_first = edge.first(bundle.a.bits, bundle.a.fire) a_first.suggestName("a_first") val d_first = edge.first(bundle.d.bits, bundle.d.fire) d_first.suggestName("d_first") val a_set = WireInit(0.U(edge.client.endSourceId.W)) val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) a_set.suggestName("a_set") a_set_wo_ready.suggestName("a_set_wo_ready") val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) a_opcodes_set.suggestName("a_opcodes_set") val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) a_sizes_set.suggestName("a_sizes_set") val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W)) a_opcode_lookup.suggestName("a_opcode_lookup") a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W)) a_size_lookup.suggestName("a_size_lookup") a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant)) val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant)) val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W)) a_opcodes_set_interm.suggestName("a_opcodes_set_interm") val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W)) a_sizes_set_interm.suggestName("a_sizes_set_interm") when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) { a_set_wo_ready := UIntToOH(bundle.a.bits.source) } when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) | 1.U a_sizes_set_interm := (bundle.a.bits.size << 1.U) | 1.U a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U) a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U) monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) d_opcodes_clr.suggestName("d_opcodes_clr") val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) || (bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra) assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) || (bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra) assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) { assume((!bundle.d.ready) || bundle.a.ready, "ready check") } if (edge.manager.minLatency > 0) { assume(a_set_wo_ready =/= d_clr_wo_ready || !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight | a_set) & ~d_clr inflight_opcodes := (inflight_opcodes | a_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes | a_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = { val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size) val log_c_size_bus_size = log2Ceil(c_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) inflight.suggestName("inflight") inflight_opcodes.suggestName("inflight_opcodes") inflight_sizes.suggestName("inflight_sizes") val c_first = edge.first(bundle.c.bits, bundle.c.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) c_first.suggestName("c_first") d_first.suggestName("d_first") val c_set = WireInit(0.U(edge.client.endSourceId.W)) val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) c_set.suggestName("c_set") c_set_wo_ready.suggestName("c_set_wo_ready") c_opcodes_set.suggestName("c_opcodes_set") c_sizes_set.suggestName("c_sizes_set") val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W)) val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W)) c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U c_opcode_lookup.suggestName("c_opcode_lookup") c_size_lookup.suggestName("c_size_lookup") val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W)) val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W)) c_opcodes_set_interm.suggestName("c_opcodes_set_interm") c_sizes_set_interm.suggestName("c_sizes_set_interm") when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) { c_set_wo_ready := UIntToOH(bundle.c.bits.source) } when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) { c_set := UIntToOH(bundle.c.bits.source) c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) | 1.U c_sizes_set_interm := (bundle.c.bits.size << 1.U) | 1.U c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U) c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U) monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra) } val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck || bundle.c.bits.opcode === TLMessages.ProbeAckData val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") d_opcodes_clr.suggestName("d_opcodes_clr") d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) { assume((!bundle.d.ready) || bundle.c.ready, "ready check") } if (edge.manager.minLatency > 0) { when (c_set_wo_ready.orR) { assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra) } } inflight := (inflight | c_set) & ~d_clr inflight_opcodes := (inflight_opcodes | c_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes | c_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.c.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.manager.endSinkId.W)) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val e_first = true.B val d_set = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) { d_set := UIntToOH(bundle.d.bits.sink) assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra) } val e_clr = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) { e_clr := UIntToOH(bundle.e.bits.sink) monAssert((d_set | inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra) } // edge.client.minLatency applies to BC, not DE inflight := (inflight | d_set) & ~e_clr } def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = { val sourceBits = log2Ceil(edge.client.endSourceId) val tooBig = 14 // >16kB worth of flight information gets to be too much if (sourceBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked") } else { if (args.edge.params(TestplanTestType).simulation) { if (args.edge.params(TLMonitorStrictMode)) { legalizeADSource(bundle, edge) legalizeCDSource(bundle, edge) } else { legalizeADSourceOld(bundle, edge) } } if (args.edge.params(TestplanTestType).formal) { legalizeADSourceFormal(bundle, edge) } } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { // legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize... val sinkBits = log2Ceil(edge.manager.endSinkId) if (sinkBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked") } else { legalizeDESink(bundle, edge) } } } def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = { legalizeFormat (bundle, edge) legalizeMultibeat (bundle, edge) legalizeUnique (bundle, edge) } } File Misc.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import scala.math._ class ParameterizedBundle(implicit p: Parameters) extends Bundle trait Clocked extends Bundle { val clock = Clock() val reset = Bool() } object DecoupledHelper { def apply(rvs: Bool*) = new DecoupledHelper(rvs) } class DecoupledHelper(val rvs: Seq[Bool]) { def fire(exclude: Bool, includes: Bool*) = { require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!") (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _) } def fire() = { rvs.reduce(_ && _) } } object MuxT { def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2)) def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3)) def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4)) } /** Creates a cascade of n MuxTs to search for a key value. */ object MuxTLookup { def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } } object ValidMux { def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]*): ValidIO[T] = { apply(v1 +: v2.toSeq) } def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = { val out = Wire(Valid(valids.head.bits.cloneType)) out.valid := valids.map(_.valid).reduce(_ || _) out.bits := MuxCase(valids.head.bits, valids.map(v => (v.valid -> v.bits))) out } } object Str { def apply(s: String): UInt = { var i = BigInt(0) require(s.forall(validChar _)) for (c <- s) i = (i << 8) | c i.U((s.length*8).W) } def apply(x: Char): UInt = { require(validChar(x)) x.U(8.W) } def apply(x: UInt): UInt = apply(x, 10) def apply(x: UInt, radix: Int): UInt = { val rad = radix.U val w = x.getWidth require(w > 0) var q = x var s = digit(q % rad) for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s) } s } def apply(x: SInt): UInt = apply(x, 10) def apply(x: SInt, radix: Int): UInt = { val neg = x < 0.S val abs = x.abs.asUInt if (radix != 10) { Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix)) } else { val rad = radix.U val w = abs.getWidth require(w > 0) var q = abs var s = digit(q % rad) var needSign = neg for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad val placeSpace = q === 0.U val space = Mux(needSign, Str('-'), Str(' ')) needSign = needSign && !placeSpace s = Cat(Mux(placeSpace, space, digit(q % rad)), s) } Cat(Mux(needSign, Str('-'), Str(' ')), s) } } private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0) private def validChar(x: Char) = x == (x & 0xFF) } object Split { def apply(x: UInt, n0: Int) = { val w = x.getWidth (x.extract(w-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n2: Int, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } } object Random { def apply(mod: Int, random: UInt): UInt = { if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0) else PriorityEncoder(partition(apply(1 << log2Up(mod*8), random), mod)) } def apply(mod: Int): UInt = apply(mod, randomizer) def oneHot(mod: Int, random: UInt): UInt = { if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0)) else PriorityEncoderOH(partition(apply(1 << log2Up(mod*8), random), mod)).asUInt } def oneHot(mod: Int): UInt = oneHot(mod, randomizer) private def randomizer = LFSR(16) private def partition(value: UInt, slices: Int) = Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U) } object Majority { def apply(in: Set[Bool]): Bool = { val n = (in.size >> 1) + 1 val clauses = in.subsets(n).map(_.reduce(_ && _)) clauses.reduce(_ || _) } def apply(in: Seq[Bool]): Bool = apply(in.toSet) def apply(in: UInt): Bool = apply(in.asBools.toSet) } object PopCountAtLeast { private def two(x: UInt): (Bool, Bool) = x.getWidth match { case 1 => (x.asBool, false.B) case n => val half = x.getWidth / 2 val (leftOne, leftTwo) = two(x(half - 1, 0)) val (rightOne, rightTwo) = two(x(x.getWidth - 1, half)) (leftOne || rightOne, leftTwo || rightTwo || (leftOne && rightOne)) } def apply(x: UInt, n: Int): Bool = n match { case 0 => true.B case 1 => x.orR case 2 => two(x)._2 case 3 => PopCount(x) >= n.U } } // This gets used everywhere, so make the smallest circuit possible ... // Given an address and size, create a mask of beatBytes size // eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111 // groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01 object MaskGen { def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = { require (groupBy >= 1 && beatBytes >= groupBy) require (isPow2(beatBytes) && isPow2(groupBy)) val lgBytes = log2Ceil(beatBytes) val sizeOH = UIntToOH(lgSize | 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) | (groupBy*2 - 1).U def helper(i: Int): Seq[(Bool, Bool)] = { if (i == 0) { Seq((lgSize >= lgBytes.asUInt, true.B)) } else { val sub = helper(i-1) val size = sizeOH(lgBytes - i) val bit = addr_lo(lgBytes - i) val nbit = !bit Seq.tabulate (1 << i) { j => val (sub_acc, sub_eq) = sub(j/2) val eq = sub_eq && (if (j % 2 == 1) bit else nbit) val acc = sub_acc || (size && eq) (acc, eq) } } } if (groupBy == beatBytes) 1.U else Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse) } } File PlusArg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.experimental._ import chisel3.util.HasBlackBoxResource @deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05") case class PlusArgInfo(default: BigInt, docstring: String) /** Case class for PlusArg information * * @tparam A scala type of the PlusArg value * @param default optional default value * @param docstring text to include in the help * @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT) */ private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String) /** Typeclass for converting a type to a doctype string * @tparam A some type */ trait Doctypeable[A] { /** Return the doctype string for some option */ def toDoctype(a: Option[A]): String } /** Object containing implementations of the Doctypeable typeclass */ object Doctypes { /** Converts an Int => "INT" */ implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" } /** Converts a BigInt => "INT" */ implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" } /** Converts a String => "STRING" */ implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" } } class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map( "FORMAT" -> StringParam(format), "DEFAULT" -> IntParam(default), "WIDTH" -> IntParam(width) )) with HasBlackBoxResource { val io = IO(new Bundle { val out = Output(UInt(width.W)) }) addResource("/vsrc/plusarg_reader.v") } /* This wrapper class has no outputs, making it clear it is a simulation-only construct */ class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module { val io = IO(new Bundle { val count = Input(UInt(width.W)) }) val max = Module(new plusarg_reader(format, default, docstring, width)).io.out when (max > 0.U) { assert (io.count < max, s"Timeout exceeded: $docstring") } } import Doctypes._ object PlusArg { /** PlusArg("foo") will return 42.U if the simulation is run with +foo=42 * Do not use this as an initial register value. The value is set in an * initial block and thus accessing it from another initial is racey. * Add a docstring to document the arg, which can be dumped in an elaboration * pass. */ def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out } /** PlusArg.timeout(name, default, docstring)(count) will use chisel.assert * to kill the simulation when count exceeds the specified integer argument. * Default 0 will never assert. */ def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count } } object PlusArgArtefacts { private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty /* Add a new PlusArg */ @deprecated( "Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05" ) def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring) /** Add a new PlusArg * * @tparam A scala type of the PlusArg value * @param name name for the PlusArg * @param default optional default value * @param docstring text to include in the help */ def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit = artefacts = artefacts ++ Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default))) /* From plus args, generate help text */ private def serializeHelp_cHeader(tab: String = ""): String = artefacts .map{ case(arg, info) => s"""|$tab+$arg=${info.doctype}\\n\\ |$tab${" "*20}${info.docstring}\\n\\ |""".stripMargin ++ info.default.map{ case default => s"$tab${" "*22}(default=${default})\\n\\\n"}.getOrElse("") }.toSeq.mkString("\\n\\\n") ++ "\"" /* From plus args, generate a char array of their names */ private def serializeArray_cHeader(tab: String = ""): String = { val prettyTab = tab + " " * 44 // Length of 'static const ...' s"${tab}static const char * verilog_plusargs [] = {\\\n" ++ artefacts .map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" } .mkString("")++ s"${prettyTab}0};" } /* Generate C code to be included in emulator.cc that helps with * argument parsing based on available Verilog PlusArgs */ def serialize_cHeader(): String = s"""|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\ |${serializeHelp_cHeader(" "*7)} |${serializeArray_cHeader()} |""".stripMargin } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /** Like Vec.apply(idx), but tolerates indices of mismatched width */ def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /** Any Data subtype that has a Bool member named valid. */ type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /** converts from camel case to to underscores, also removing all spaces */ def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /** converts spaces or underscores to hyphens, also lowering case */ def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y | (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y || y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /** Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation */ def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.diplomacy import chisel3._ import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor} import freechips.rocketchip.util.ShiftQueue /** Options for describing the attributes of memory regions */ object RegionType { // Define the 'more relaxed than' ordering val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS) sealed trait T extends Ordered[T] { def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this) } case object CACHED extends T // an intermediate agent may have cached a copy of the region for you case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively } // A non-empty half-open range; [start, end) case class IdRange(start: Int, end: Int) extends Ordered[IdRange] { require (start >= 0, s"Ids cannot be negative, but got: $start.") require (start <= end, "Id ranges cannot be negative.") def compare(x: IdRange) = { val primary = (this.start - x.start).signum val secondary = (x.end - this.end).signum if (primary != 0) primary else secondary } def overlaps(x: IdRange) = start < x.end && x.start < end def contains(x: IdRange) = start <= x.start && x.end <= end def contains(x: Int) = start <= x && x < end def contains(x: UInt) = if (size == 0) { false.B } else if (size == 1) { // simple comparison x === start.U } else { // find index of largest different bit val largestDeltaBit = log2Floor(start ^ (end-1)) val smallestCommonBit = largestDeltaBit + 1 // may not exist in x val uncommonMask = (1 << smallestCommonBit) - 1 val uncommonBits = (x | 0.U(smallestCommonBit.W))(largestDeltaBit, 0) // the prefix must match exactly (note: may shift ALL bits away) (x >> smallestCommonBit) === (start >> smallestCommonBit).U && // firrtl constant prop range analysis can eliminate these two: (start & uncommonMask).U <= uncommonBits && uncommonBits <= ((end-1) & uncommonMask).U } def shift(x: Int) = IdRange(start+x, end+x) def size = end - start def isEmpty = end == start def range = start until end } object IdRange { def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else { val ranges = s.sorted (ranges.tail zip ranges.init) find { case (a, b) => a overlaps b } } } // An potentially empty inclusive range of 2-powers [min, max] (in bytes) case class TransferSizes(min: Int, max: Int) { def this(x: Int) = this(x, x) require (min <= max, s"Min transfer $min > max transfer $max") require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)") require (max == 0 || isPow2(max), s"TransferSizes must be a power of 2, got: $max") require (min == 0 || isPow2(min), s"TransferSizes must be a power of 2, got: $min") require (max == 0 || min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)") def none = min == 0 def contains(x: Int) = isPow2(x) && min <= x && x <= max def containsLg(x: Int) = contains(1 << x) def containsLg(x: UInt) = if (none) false.B else if (min == max) { log2Ceil(min).U === x } else { log2Ceil(min).U <= x && x <= log2Ceil(max).U } def contains(x: TransferSizes) = x.none || (min <= x.min && x.max <= max) def intersect(x: TransferSizes) = if (x.max < min || max < x.min) TransferSizes.none else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max)) // Not a union, because the result may contain sizes contained by neither term // NOT TO BE CONFUSED WITH COVERPOINTS def mincover(x: TransferSizes) = { if (none) { x } else if (x.none) { this } else { TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max)) } } override def toString() = "TransferSizes[%d, %d]".format(min, max) } object TransferSizes { def apply(x: Int) = new TransferSizes(x) val none = new TransferSizes(0) def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _) def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _) implicit def asBool(x: TransferSizes) = !x.none } // AddressSets specify the address space managed by the manager // Base is the base address, and mask are the bits consumed by the manager // e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff // e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ... case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet] { // Forbid misaligned base address (and empty sets) require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}") require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous // We do allow negative mask (=> ignore all high bits) def contains(x: BigInt) = ((x ^ base) & ~mask) == 0 def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S // turn x into an address contained in this set def legalize(x: UInt): UInt = base.U | (mask.U & x) // overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1) def overlaps(x: AddressSet) = (~(mask | x.mask) & (base ^ x.base)) == 0 // contains iff bitwise: x.mask => mask && contains(x.base) def contains(x: AddressSet) = ((x.mask | (base ^ x.base)) & ~mask) == 0 // The number of bytes to which the manager must be aligned def alignment = ((mask + 1) & ~mask) // Is this a contiguous memory range def contiguous = alignment == mask+1 def finite = mask >= 0 def max = { require (finite, "Max cannot be calculated on infinite mask"); base | mask } // Widen the match function to ignore all bits in imask def widen(imask: BigInt) = AddressSet(base & ~imask, mask | imask) // Return an AddressSet that only contains the addresses both sets contain def intersect(x: AddressSet): Option[AddressSet] = { if (!overlaps(x)) { None } else { val r_mask = mask & x.mask val r_base = base | x.base Some(AddressSet(r_base, r_mask)) } } def subtract(x: AddressSet): Seq[AddressSet] = { intersect(x) match { case None => Seq(this) case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit => val nmask = (mask & (bit-1)) | remove.mask val nbase = (remove.base ^ bit) & ~nmask AddressSet(nbase, nmask) } } } // AddressSets have one natural Ordering (the containment order, if contiguous) def compare(x: AddressSet) = { val primary = (this.base - x.base).signum // smallest address first val secondary = (x.mask - this.mask).signum // largest mask first if (primary != 0) primary else secondary } // We always want to see things in hex override def toString() = { if (mask >= 0) { "AddressSet(0x%x, 0x%x)".format(base, mask) } else { "AddressSet(0x%x, ~0x%x)".format(base, ~mask) } } def toRanges = { require (finite, "Ranges cannot be calculated on infinite mask") val size = alignment val fragments = mask & ~(size-1) val bits = bitIndexes(fragments) (BigInt(0) until (BigInt(1) << bits.size)).map { i => val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) } AddressRange(off, size) } } } object AddressSet { val everything = AddressSet(0, -1) def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = { if (size == 0) tail.reverse else { val maxBaseAlignment = base & (-base) // 0 for infinite (LSB) val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size val step = if (maxBaseAlignment == 0 || maxBaseAlignment > maxSizeAlignment) maxSizeAlignment else maxBaseAlignment misaligned(base+step, size-step, AddressSet(base, step-1) +: tail) } } def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = { // Pair terms up by ignoring 'bit' seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) => if (seq.size == 1) { seq.head // singleton -> unaffected } else { key.copy(mask = key.mask | bit) // pair - widen mask by bit } }.toList } def unify(seq: Seq[AddressSet]): Seq[AddressSet] = { val bits = seq.map(_.base).foldLeft(BigInt(0))(_ | _) AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted } def enumerateMask(mask: BigInt): Seq[BigInt] = { def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] = if (id == mask) (id +: tail).reverse else helper(((~mask | id) + 1) & mask, id +: tail) helper(0, Nil) } def enumerateBits(mask: BigInt): Seq[BigInt] = { def helper(x: BigInt): Seq[BigInt] = { if (x == 0) { Nil } else { val bit = x & (-x) bit +: helper(x & ~bit) } } helper(mask) } } case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean) { require (depth >= 0, "Buffer depth must be >= 0") def isDefined = depth > 0 def latency = if (isDefined && !flow) 1 else 0 def apply[T <: Data](x: DecoupledIO[T]) = if (isDefined) Queue(x, depth, flow=flow, pipe=pipe) else x def irrevocable[T <: Data](x: ReadyValidIO[T]) = if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe) else x def sq[T <: Data](x: DecoupledIO[T]) = if (!isDefined) x else { val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe)) sq.io.enq <> x sq.io.deq } override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "") } object BufferParams { implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false) val default = BufferParams(2) val none = BufferParams(0) val flow = BufferParams(1, true, false) val pipe = BufferParams(1, false, true) } case class TriStateValue(value: Boolean, set: Boolean) { def update(orig: Boolean) = if (set) value else orig } object TriStateValue { implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true) def unset = TriStateValue(false, false) } trait DirectedBuffers[T] { def copyIn(x: BufferParams): T def copyOut(x: BufferParams): T def copyInOut(x: BufferParams): T } trait IdMapEntry { def name: String def from: IdRange def to: IdRange def isCache: Boolean def requestFifo: Boolean def maxTransactionsInFlight: Option[Int] def pretty(fmt: String) = if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5 fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } else { fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } } abstract class IdMap[T <: IdMapEntry] { protected val fmt: String val mapping: Seq[T] def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n") } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) || !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.ProbeAckData || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode | small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U || beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }

module TLMonitor_63( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input io_in_a_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_b_ready, // @[Monitor.scala:20:14] input io_in_b_valid, // @[Monitor.scala:20:14] input [2:0] io_in_b_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_b_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_b_bits_size, // @[Monitor.scala:20:14] input io_in_b_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_b_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_b_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_b_bits_data, // @[Monitor.scala:20:14] input io_in_b_bits_corrupt, // @[Monitor.scala:20:14] input io_in_c_ready, // @[Monitor.scala:20:14] input io_in_c_valid, // @[Monitor.scala:20:14] input [2:0] io_in_c_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_c_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_c_bits_size, // @[Monitor.scala:20:14] input io_in_c_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_c_bits_address, // @[Monitor.scala:20:14] input [63:0] io_in_c_bits_data, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input io_in_d_bits_source, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt, // @[Monitor.scala:20:14] input io_in_e_ready, // @[Monitor.scala:20:14] input io_in_e_valid, // @[Monitor.scala:20:14] input [2:0] io_in_e_bits_sink // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [31:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_b_ready_0 = io_in_b_ready; // @[Monitor.scala:36:7] wire io_in_b_valid_0 = io_in_b_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_b_bits_opcode_0 = io_in_b_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_b_bits_param_0 = io_in_b_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_b_bits_size_0 = io_in_b_bits_size; // @[Monitor.scala:36:7] wire io_in_b_bits_source_0 = io_in_b_bits_source; // @[Monitor.scala:36:7] wire [31:0] io_in_b_bits_address_0 = io_in_b_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_b_bits_mask_0 = io_in_b_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_b_bits_data_0 = io_in_b_bits_data; // @[Monitor.scala:36:7] wire io_in_b_bits_corrupt_0 = io_in_b_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_c_ready_0 = io_in_c_ready; // @[Monitor.scala:36:7] wire io_in_c_valid_0 = io_in_c_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_c_bits_opcode_0 = io_in_c_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_c_bits_param_0 = io_in_c_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_c_bits_size_0 = io_in_c_bits_size; // @[Monitor.scala:36:7] wire io_in_c_bits_source_0 = io_in_c_bits_source; // @[Monitor.scala:36:7] wire [31:0] io_in_c_bits_address_0 = io_in_c_bits_address; // @[Monitor.scala:36:7] wire [63:0] io_in_c_bits_data_0 = io_in_c_bits_data; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7] wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_e_ready_0 = io_in_e_ready; // @[Monitor.scala:36:7] wire io_in_e_valid_0 = io_in_e_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_e_bits_sink_0 = io_in_e_bits_sink; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire io_in_c_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire _legal_source_T_2 = 1'h0; // @[Mux.scala:30:73] wire [15:0] _a_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _c_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hFF; // @[Monitor.scala:724:57] wire [16:0] _a_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _c_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hFF; // @[Monitor.scala:724:57] wire [15:0] _a_size_lookup_T_3 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _c_size_lookup_T_3 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [8:0] b_first_beats1 = 9'h0; // @[Edges.scala:221:14] wire [8:0] b_first_count = 9'h0; // @[Edges.scala:234:25] wire sink_ok = 1'h1; // @[Monitor.scala:309:31] wire sink_ok_1 = 1'h1; // @[Monitor.scala:367:31] wire _b_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire b_first_last = 1'h1; // @[Edges.scala:232:33] wire [3:0] _a_size_lookup_T_2 = 4'h8; // @[Monitor.scala:641:117] wire [3:0] _d_sizes_clr_T = 4'h8; // @[Monitor.scala:681:48] wire [3:0] _c_size_lookup_T_2 = 4'h8; // @[Monitor.scala:750:119] wire [3:0] _d_sizes_clr_T_6 = 4'h8; // @[Monitor.scala:791:48] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire _source_ok_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _mask_sizeOH_T_3 = io_in_b_bits_size_0; // @[Misc.scala:202:34] wire _legal_source_T_1 = io_in_b_bits_source_0; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T = io_in_b_bits_address_0; // @[Monitor.scala:36:7] wire _source_ok_T_5 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_70 = io_in_c_bits_address_0; // @[Monitor.scala:36:7] wire _source_ok_T_3 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire _source_ok_T = ~io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31] wire _source_ok_WIRE_1 = _source_ok_T_1; // @[Parameters.scala:1138:31] wire source_ok = _source_ok_WIRE_0 | _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46] wire [26:0] _GEN = 27'hFFF << io_in_a_bits_size_0; // @[package.scala:243:71] wire [26:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [11:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [31:0] _is_aligned_T = {20'h0, io_in_a_bits_address_0[11:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 32'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 4'h2; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire _source_ok_T_2 = ~io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_0 = _source_ok_T_2; // @[Parameters.scala:1138:31] wire _source_ok_WIRE_1_1 = _source_ok_T_3; // @[Parameters.scala:1138:31] wire source_ok_1 = _source_ok_WIRE_1_0 | _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46] wire [32:0] _address_ok_T_1 = {1'h0, _address_ok_T}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_2 = _address_ok_T_1 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_3 = _address_ok_T_2; // @[Parameters.scala:137:46] wire _address_ok_T_4 = _address_ok_T_3 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_0 = _address_ok_T_4; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_5 = {io_in_b_bits_address_0[31:13], io_in_b_bits_address_0[12:0] ^ 13'h1000}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_6 = {1'h0, _address_ok_T_5}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_7 = _address_ok_T_6 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_8 = _address_ok_T_7; // @[Parameters.scala:137:46] wire _address_ok_T_9 = _address_ok_T_8 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1 = _address_ok_T_9; // @[Parameters.scala:612:40] wire [13:0] _GEN_0 = io_in_b_bits_address_0[13:0] ^ 14'h3000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_10 = {io_in_b_bits_address_0[31:14], _GEN_0}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_11 = {1'h0, _address_ok_T_10}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_12 = _address_ok_T_11 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_13 = _address_ok_T_12; // @[Parameters.scala:137:46] wire _address_ok_T_14 = _address_ok_T_13 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_2 = _address_ok_T_14; // @[Parameters.scala:612:40] wire [16:0] _GEN_1 = io_in_b_bits_address_0[16:0] ^ 17'h10000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_15 = {io_in_b_bits_address_0[31:17], _GEN_1}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_16 = {1'h0, _address_ok_T_15}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_17 = _address_ok_T_16 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_18 = _address_ok_T_17; // @[Parameters.scala:137:46] wire _address_ok_T_19 = _address_ok_T_18 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_3 = _address_ok_T_19; // @[Parameters.scala:612:40] wire [20:0] _GEN_2 = io_in_b_bits_address_0[20:0] ^ 21'h100000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_20 = {io_in_b_bits_address_0[31:21], _GEN_2}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_21 = {1'h0, _address_ok_T_20}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_22 = _address_ok_T_21 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_23 = _address_ok_T_22; // @[Parameters.scala:137:46] wire _address_ok_T_24 = _address_ok_T_23 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_4 = _address_ok_T_24; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_25 = {io_in_b_bits_address_0[31:21], io_in_b_bits_address_0[20:0] ^ 21'h110000}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_26 = {1'h0, _address_ok_T_25}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_27 = _address_ok_T_26 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_28 = _address_ok_T_27; // @[Parameters.scala:137:46] wire _address_ok_T_29 = _address_ok_T_28 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_5 = _address_ok_T_29; // @[Parameters.scala:612:40] wire [25:0] _GEN_3 = io_in_b_bits_address_0[25:0] ^ 26'h2000000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_30 = {io_in_b_bits_address_0[31:26], _GEN_3}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_31 = {1'h0, _address_ok_T_30}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_32 = _address_ok_T_31 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_33 = _address_ok_T_32; // @[Parameters.scala:137:46] wire _address_ok_T_34 = _address_ok_T_33 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_6 = _address_ok_T_34; // @[Parameters.scala:612:40] wire [25:0] _GEN_4 = io_in_b_bits_address_0[25:0] ^ 26'h2010000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_35 = {io_in_b_bits_address_0[31:26], _GEN_4}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_36 = {1'h0, _address_ok_T_35}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_37 = _address_ok_T_36 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_38 = _address_ok_T_37; // @[Parameters.scala:137:46] wire _address_ok_T_39 = _address_ok_T_38 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_7 = _address_ok_T_39; // @[Parameters.scala:612:40] wire [27:0] _GEN_5 = io_in_b_bits_address_0[27:0] ^ 28'h8000000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_40 = {io_in_b_bits_address_0[31:28], _GEN_5}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_41 = {1'h0, _address_ok_T_40}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_42 = _address_ok_T_41 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_43 = _address_ok_T_42; // @[Parameters.scala:137:46] wire _address_ok_T_44 = _address_ok_T_43 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_8 = _address_ok_T_44; // @[Parameters.scala:612:40] wire [27:0] _GEN_6 = io_in_b_bits_address_0[27:0] ^ 28'hC000000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_45 = {io_in_b_bits_address_0[31:28], _GEN_6}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_46 = {1'h0, _address_ok_T_45}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_47 = _address_ok_T_46 & 33'h1FC000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_48 = _address_ok_T_47; // @[Parameters.scala:137:46] wire _address_ok_T_49 = _address_ok_T_48 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_9 = _address_ok_T_49; // @[Parameters.scala:612:40] wire [28:0] _GEN_7 = io_in_b_bits_address_0[28:0] ^ 29'h10020000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_50 = {io_in_b_bits_address_0[31:29], _GEN_7}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_51 = {1'h0, _address_ok_T_50}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_52 = _address_ok_T_51 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_53 = _address_ok_T_52; // @[Parameters.scala:137:46] wire _address_ok_T_54 = _address_ok_T_53 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_10 = _address_ok_T_54; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_55 = io_in_b_bits_address_0 ^ 32'h80000000; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_56 = {1'h0, _address_ok_T_55}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_57 = _address_ok_T_56 & 33'h1F0000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_58 = _address_ok_T_57; // @[Parameters.scala:137:46] wire _address_ok_T_59 = _address_ok_T_58 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_11 = _address_ok_T_59; // @[Parameters.scala:612:40] wire _address_ok_T_60 = _address_ok_WIRE_0 | _address_ok_WIRE_1; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_61 = _address_ok_T_60 | _address_ok_WIRE_2; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_62 = _address_ok_T_61 | _address_ok_WIRE_3; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_63 = _address_ok_T_62 | _address_ok_WIRE_4; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_64 = _address_ok_T_63 | _address_ok_WIRE_5; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_65 = _address_ok_T_64 | _address_ok_WIRE_6; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_66 = _address_ok_T_65 | _address_ok_WIRE_7; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_67 = _address_ok_T_66 | _address_ok_WIRE_8; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_68 = _address_ok_T_67 | _address_ok_WIRE_9; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_69 = _address_ok_T_68 | _address_ok_WIRE_10; // @[Parameters.scala:612:40, :636:64] wire address_ok = _address_ok_T_69 | _address_ok_WIRE_11; // @[Parameters.scala:612:40, :636:64] wire [26:0] _GEN_8 = 27'hFFF << io_in_b_bits_size_0; // @[package.scala:243:71] wire [26:0] _is_aligned_mask_T_2; // @[package.scala:243:71] assign _is_aligned_mask_T_2 = _GEN_8; // @[package.scala:243:71] wire [26:0] _b_first_beats1_decode_T; // @[package.scala:243:71] assign _b_first_beats1_decode_T = _GEN_8; // @[package.scala:243:71] wire [11:0] _is_aligned_mask_T_3 = _is_aligned_mask_T_2[11:0]; // @[package.scala:243:{71,76}] wire [11:0] is_aligned_mask_1 = ~_is_aligned_mask_T_3; // @[package.scala:243:{46,76}] wire [31:0] _is_aligned_T_1 = {20'h0, io_in_b_bits_address_0[11:0] & is_aligned_mask_1}; // @[package.scala:243:46] wire is_aligned_1 = _is_aligned_T_1 == 32'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount_1 = _mask_sizeOH_T_3[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_4 = 4'h1 << mask_sizeOH_shiftAmount_1; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_5 = _mask_sizeOH_T_4[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH_1 = {_mask_sizeOH_T_5[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1_1 = io_in_b_bits_size_0 > 4'h2; // @[Misc.scala:206:21] wire mask_sub_sub_size_1 = mask_sizeOH_1[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit_1 = io_in_b_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2_1 = mask_sub_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit_1 = ~mask_sub_sub_bit_1; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2_1 = mask_sub_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T_2 = mask_sub_sub_size_1 & mask_sub_sub_0_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1_1 = mask_sub_sub_sub_0_1_1 | _mask_sub_sub_acc_T_2; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_3 = mask_sub_sub_size_1 & mask_sub_sub_1_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1_1 = mask_sub_sub_sub_0_1_1 | _mask_sub_sub_acc_T_3; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size_1 = mask_sizeOH_1[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit_1 = io_in_b_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit_1 = ~mask_sub_bit_1; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2_1 = mask_sub_sub_0_2_1 & mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_4 = mask_sub_size_1 & mask_sub_0_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1_1 = mask_sub_sub_0_1_1 | _mask_sub_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2_1 = mask_sub_sub_0_2_1 & mask_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_5 = mask_sub_size_1 & mask_sub_1_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1_1 = mask_sub_sub_0_1_1 | _mask_sub_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2_1 = mask_sub_sub_1_2_1 & mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_6 = mask_sub_size_1 & mask_sub_2_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1_1 = mask_sub_sub_1_1_1 | _mask_sub_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2_1 = mask_sub_sub_1_2_1 & mask_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_7 = mask_sub_size_1 & mask_sub_3_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1_1 = mask_sub_sub_1_1_1 | _mask_sub_acc_T_7; // @[Misc.scala:215:{29,38}] wire mask_size_1 = mask_sizeOH_1[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit_1 = io_in_b_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit_1 = ~mask_bit_1; // @[Misc.scala:210:26, :211:20] wire mask_eq_8 = mask_sub_0_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_8 = mask_size_1 & mask_eq_8; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_8 = mask_sub_0_1_1 | _mask_acc_T_8; // @[Misc.scala:215:{29,38}] wire mask_eq_9 = mask_sub_0_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_9 = mask_size_1 & mask_eq_9; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_9 = mask_sub_0_1_1 | _mask_acc_T_9; // @[Misc.scala:215:{29,38}] wire mask_eq_10 = mask_sub_1_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_10 = mask_size_1 & mask_eq_10; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_10 = mask_sub_1_1_1 | _mask_acc_T_10; // @[Misc.scala:215:{29,38}] wire mask_eq_11 = mask_sub_1_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_11 = mask_size_1 & mask_eq_11; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_11 = mask_sub_1_1_1 | _mask_acc_T_11; // @[Misc.scala:215:{29,38}] wire mask_eq_12 = mask_sub_2_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_12 = mask_size_1 & mask_eq_12; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_12 = mask_sub_2_1_1 | _mask_acc_T_12; // @[Misc.scala:215:{29,38}] wire mask_eq_13 = mask_sub_2_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_13 = mask_size_1 & mask_eq_13; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_13 = mask_sub_2_1_1 | _mask_acc_T_13; // @[Misc.scala:215:{29,38}] wire mask_eq_14 = mask_sub_3_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_14 = mask_size_1 & mask_eq_14; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_14 = mask_sub_3_1_1 | _mask_acc_T_14; // @[Misc.scala:215:{29,38}] wire mask_eq_15 = mask_sub_3_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_15 = mask_size_1 & mask_eq_15; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_15 = mask_sub_3_1_1 | _mask_acc_T_15; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo_1 = {mask_acc_9, mask_acc_8}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi_1 = {mask_acc_11, mask_acc_10}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo_1 = {mask_lo_hi_1, mask_lo_lo_1}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo_1 = {mask_acc_13, mask_acc_12}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi_1 = {mask_acc_15, mask_acc_14}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi_1 = {mask_hi_hi_1, mask_hi_lo_1}; // @[Misc.scala:222:10] wire [7:0] mask_1 = {mask_hi_1, mask_lo_1}; // @[Misc.scala:222:10] wire _legal_source_T = ~io_in_b_bits_source_0; // @[Monitor.scala:36:7] wire _legal_source_WIRE_0 = _legal_source_T; // @[Parameters.scala:1138:31] wire _legal_source_WIRE_1 = _legal_source_T_1; // @[Parameters.scala:1138:31] wire _legal_source_T_3 = _legal_source_WIRE_1; // @[Mux.scala:30:73] wire _legal_source_T_4 = _legal_source_T_3; // @[Mux.scala:30:73] wire _legal_source_WIRE_1_0 = _legal_source_T_4; // @[Mux.scala:30:73] wire legal_source = _legal_source_WIRE_1_0 == io_in_b_bits_source_0; // @[Mux.scala:30:73] wire _source_ok_T_4 = ~io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire _source_ok_WIRE_2_0 = _source_ok_T_4; // @[Parameters.scala:1138:31] wire _source_ok_WIRE_2_1 = _source_ok_T_5; // @[Parameters.scala:1138:31] wire source_ok_2 = _source_ok_WIRE_2_0 | _source_ok_WIRE_2_1; // @[Parameters.scala:1138:31, :1139:46] wire [26:0] _GEN_9 = 27'hFFF << io_in_c_bits_size_0; // @[package.scala:243:71] wire [26:0] _is_aligned_mask_T_4; // @[package.scala:243:71] assign _is_aligned_mask_T_4 = _GEN_9; // @[package.scala:243:71] wire [26:0] _c_first_beats1_decode_T; // @[package.scala:243:71] assign _c_first_beats1_decode_T = _GEN_9; // @[package.scala:243:71] wire [26:0] _c_first_beats1_decode_T_3; // @[package.scala:243:71] assign _c_first_beats1_decode_T_3 = _GEN_9; // @[package.scala:243:71] wire [11:0] _is_aligned_mask_T_5 = _is_aligned_mask_T_4[11:0]; // @[package.scala:243:{71,76}] wire [11:0] is_aligned_mask_2 = ~_is_aligned_mask_T_5; // @[package.scala:243:{46,76}] wire [31:0] _is_aligned_T_2 = {20'h0, io_in_c_bits_address_0[11:0] & is_aligned_mask_2}; // @[package.scala:243:46] wire is_aligned_2 = _is_aligned_T_2 == 32'h0; // @[Edges.scala:21:{16,24}] wire [32:0] _address_ok_T_71 = {1'h0, _address_ok_T_70}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_72 = _address_ok_T_71 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_73 = _address_ok_T_72; // @[Parameters.scala:137:46] wire _address_ok_T_74 = _address_ok_T_73 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_0 = _address_ok_T_74; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_75 = {io_in_c_bits_address_0[31:13], io_in_c_bits_address_0[12:0] ^ 13'h1000}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_76 = {1'h0, _address_ok_T_75}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_77 = _address_ok_T_76 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_78 = _address_ok_T_77; // @[Parameters.scala:137:46] wire _address_ok_T_79 = _address_ok_T_78 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_1 = _address_ok_T_79; // @[Parameters.scala:612:40] wire [13:0] _GEN_10 = io_in_c_bits_address_0[13:0] ^ 14'h3000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_80 = {io_in_c_bits_address_0[31:14], _GEN_10}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_81 = {1'h0, _address_ok_T_80}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_82 = _address_ok_T_81 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_83 = _address_ok_T_82; // @[Parameters.scala:137:46] wire _address_ok_T_84 = _address_ok_T_83 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_2 = _address_ok_T_84; // @[Parameters.scala:612:40] wire [16:0] _GEN_11 = io_in_c_bits_address_0[16:0] ^ 17'h10000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_85 = {io_in_c_bits_address_0[31:17], _GEN_11}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_86 = {1'h0, _address_ok_T_85}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_87 = _address_ok_T_86 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_88 = _address_ok_T_87; // @[Parameters.scala:137:46] wire _address_ok_T_89 = _address_ok_T_88 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_3 = _address_ok_T_89; // @[Parameters.scala:612:40] wire [20:0] _GEN_12 = io_in_c_bits_address_0[20:0] ^ 21'h100000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_90 = {io_in_c_bits_address_0[31:21], _GEN_12}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_91 = {1'h0, _address_ok_T_90}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_92 = _address_ok_T_91 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_93 = _address_ok_T_92; // @[Parameters.scala:137:46] wire _address_ok_T_94 = _address_ok_T_93 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_4 = _address_ok_T_94; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_95 = {io_in_c_bits_address_0[31:21], io_in_c_bits_address_0[20:0] ^ 21'h110000}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_96 = {1'h0, _address_ok_T_95}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_97 = _address_ok_T_96 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_98 = _address_ok_T_97; // @[Parameters.scala:137:46] wire _address_ok_T_99 = _address_ok_T_98 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_5 = _address_ok_T_99; // @[Parameters.scala:612:40] wire [25:0] _GEN_13 = io_in_c_bits_address_0[25:0] ^ 26'h2000000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_100 = {io_in_c_bits_address_0[31:26], _GEN_13}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_101 = {1'h0, _address_ok_T_100}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_102 = _address_ok_T_101 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_103 = _address_ok_T_102; // @[Parameters.scala:137:46] wire _address_ok_T_104 = _address_ok_T_103 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_6 = _address_ok_T_104; // @[Parameters.scala:612:40] wire [25:0] _GEN_14 = io_in_c_bits_address_0[25:0] ^ 26'h2010000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_105 = {io_in_c_bits_address_0[31:26], _GEN_14}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_106 = {1'h0, _address_ok_T_105}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_107 = _address_ok_T_106 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_108 = _address_ok_T_107; // @[Parameters.scala:137:46] wire _address_ok_T_109 = _address_ok_T_108 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_7 = _address_ok_T_109; // @[Parameters.scala:612:40] wire [27:0] _GEN_15 = io_in_c_bits_address_0[27:0] ^ 28'h8000000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_110 = {io_in_c_bits_address_0[31:28], _GEN_15}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_111 = {1'h0, _address_ok_T_110}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_112 = _address_ok_T_111 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_113 = _address_ok_T_112; // @[Parameters.scala:137:46] wire _address_ok_T_114 = _address_ok_T_113 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_8 = _address_ok_T_114; // @[Parameters.scala:612:40] wire [27:0] _GEN_16 = io_in_c_bits_address_0[27:0] ^ 28'hC000000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_115 = {io_in_c_bits_address_0[31:28], _GEN_16}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_116 = {1'h0, _address_ok_T_115}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_117 = _address_ok_T_116 & 33'h1FC000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_118 = _address_ok_T_117; // @[Parameters.scala:137:46] wire _address_ok_T_119 = _address_ok_T_118 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_9 = _address_ok_T_119; // @[Parameters.scala:612:40] wire [28:0] _GEN_17 = io_in_c_bits_address_0[28:0] ^ 29'h10020000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_120 = {io_in_c_bits_address_0[31:29], _GEN_17}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_121 = {1'h0, _address_ok_T_120}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_122 = _address_ok_T_121 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_123 = _address_ok_T_122; // @[Parameters.scala:137:46] wire _address_ok_T_124 = _address_ok_T_123 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_10 = _address_ok_T_124; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_125 = io_in_c_bits_address_0 ^ 32'h80000000; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_126 = {1'h0, _address_ok_T_125}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_127 = _address_ok_T_126 & 33'h1F0000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_128 = _address_ok_T_127; // @[Parameters.scala:137:46] wire _address_ok_T_129 = _address_ok_T_128 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_11 = _address_ok_T_129; // @[Parameters.scala:612:40] wire _address_ok_T_130 = _address_ok_WIRE_1_0 | _address_ok_WIRE_1_1; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_131 = _address_ok_T_130 | _address_ok_WIRE_1_2; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_132 = _address_ok_T_131 | _address_ok_WIRE_1_3; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_133 = _address_ok_T_132 | _address_ok_WIRE_1_4; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_134 = _address_ok_T_133 | _address_ok_WIRE_1_5; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_135 = _address_ok_T_134 | _address_ok_WIRE_1_6; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_136 = _address_ok_T_135 | _address_ok_WIRE_1_7; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_137 = _address_ok_T_136 | _address_ok_WIRE_1_8; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_138 = _address_ok_T_137 | _address_ok_WIRE_1_9; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_139 = _address_ok_T_138 | _address_ok_WIRE_1_10; // @[Parameters.scala:612:40, :636:64] wire address_ok_1 = _address_ok_T_139 | _address_ok_WIRE_1_11; // @[Parameters.scala:612:40, :636:64] wire _T_2389 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_2389; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_2389; // @[Decoupled.scala:51:35] wire [11:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [8:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [8:0] a_first_counter; // @[Edges.scala:229:27] wire [9:0] _a_first_counter1_T = {1'h0, a_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] a_first_counter1 = _a_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [8:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [3:0] size; // @[Monitor.scala:389:22] reg source; // @[Monitor.scala:390:22] reg [31:0] address; // @[Monitor.scala:391:22] wire _T_2463 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_2463; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_2463; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_2463; // @[Decoupled.scala:51:35] wire _d_first_T_3; // @[Decoupled.scala:51:35] assign _d_first_T_3 = _T_2463; // @[Decoupled.scala:51:35] wire [26:0] _GEN_18 = 27'hFFF << io_in_d_bits_size_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_18; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_18; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_18; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_9; // @[package.scala:243:71] assign _d_first_beats1_decode_T_9 = _GEN_18; // @[package.scala:243:71] wire [11:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_3 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [8:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T = {1'h0, d_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1 = _d_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [3:0] size_1; // @[Monitor.scala:540:22] reg source_1; // @[Monitor.scala:541:22] reg [2:0] sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] wire _b_first_T = io_in_b_ready_0 & io_in_b_valid_0; // @[Decoupled.scala:51:35] wire b_first_done = _b_first_T; // @[Decoupled.scala:51:35] wire [11:0] _b_first_beats1_decode_T_1 = _b_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _b_first_beats1_decode_T_2 = ~_b_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] b_first_beats1_decode = _b_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire _b_first_beats1_opdata_T = io_in_b_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire b_first_beats1_opdata = ~_b_first_beats1_opdata_T; // @[Edges.scala:97:{28,37}] reg [8:0] b_first_counter; // @[Edges.scala:229:27] wire [9:0] _b_first_counter1_T = {1'h0, b_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] b_first_counter1 = _b_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire b_first = b_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _b_first_last_T = b_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire [8:0] _b_first_count_T = ~b_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] _b_first_counter_T = b_first ? 9'h0 : b_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [2:0] opcode_2; // @[Monitor.scala:410:22] reg [1:0] param_2; // @[Monitor.scala:411:22] reg [3:0] size_2; // @[Monitor.scala:412:22] reg source_2; // @[Monitor.scala:413:22] reg [31:0] address_1; // @[Monitor.scala:414:22] wire _T_2460 = io_in_c_ready_0 & io_in_c_valid_0; // @[Decoupled.scala:51:35] wire _c_first_T; // @[Decoupled.scala:51:35] assign _c_first_T = _T_2460; // @[Decoupled.scala:51:35] wire _c_first_T_1; // @[Decoupled.scala:51:35] assign _c_first_T_1 = _T_2460; // @[Decoupled.scala:51:35] wire [11:0] _c_first_beats1_decode_T_1 = _c_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _c_first_beats1_decode_T_2 = ~_c_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] c_first_beats1_decode = _c_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire c_first_beats1_opdata = io_in_c_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire c_first_beats1_opdata_1 = io_in_c_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [8:0] c_first_beats1 = c_first_beats1_opdata ? c_first_beats1_decode : 9'h0; // @[Edges.scala:102:36, :220:59, :221:14] reg [8:0] c_first_counter; // @[Edges.scala:229:27] wire [9:0] _c_first_counter1_T = {1'h0, c_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] c_first_counter1 = _c_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire c_first = c_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _c_first_last_T = c_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _c_first_last_T_1 = c_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire c_first_last = _c_first_last_T | _c_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire c_first_done = c_first_last & _c_first_T; // @[Decoupled.scala:51:35] wire [8:0] _c_first_count_T = ~c_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] c_first_count = c_first_beats1 & _c_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _c_first_counter_T = c_first ? c_first_beats1 : c_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_3; // @[Monitor.scala:515:22] reg [2:0] param_3; // @[Monitor.scala:516:22] reg [3:0] size_3; // @[Monitor.scala:517:22] reg source_3; // @[Monitor.scala:518:22] reg [31:0] address_2; // @[Monitor.scala:519:22] reg [1:0] inflight; // @[Monitor.scala:614:27] reg [7:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [15:0] inflight_sizes; // @[Monitor.scala:618:33] wire [11:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [8:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [8:0] a_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] a_first_counter1_1 = _a_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [11:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_1 = _d_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [1:0] a_set; // @[Monitor.scala:626:34] wire [1:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [7:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [15:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [3:0] _GEN_19 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [3:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_19; // @[Monitor.scala:637:69] wire [3:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_19; // @[Monitor.scala:637:69, :680:101] wire [3:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_19; // @[Monitor.scala:637:69, :749:69] wire [3:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_19; // @[Monitor.scala:637:69, :790:101] wire [7:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [15:0] _a_opcode_lookup_T_6 = {8'h0, _a_opcode_lookup_T_1 & 8'hF}; // @[Monitor.scala:637:{44,97}] wire [15:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [7:0] a_size_lookup; // @[Monitor.scala:639:33] wire [3:0] _GEN_20 = {io_in_d_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :641:65] wire [3:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_20; // @[Monitor.scala:641:65] wire [3:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_20; // @[Monitor.scala:641:65, :681:99] wire [3:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_20; // @[Monitor.scala:641:65, :750:67] wire [3:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_20; // @[Monitor.scala:641:65, :791:99] wire [15:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [15:0] _a_size_lookup_T_6 = _a_size_lookup_T_1 & 16'hFF; // @[Monitor.scala:641:{40,91}] wire [15:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[15:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[7:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [4:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [1:0] _GEN_21 = {1'h0, io_in_a_bits_source_0}; // @[OneHot.scala:58:35] wire [1:0] _GEN_22 = 2'h1 << _GEN_21; // @[OneHot.scala:58:35] wire [1:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_22; // @[OneHot.scala:58:35] wire [1:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_22; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T : 2'h0; // @[OneHot.scala:58:35] wire _T_2315 = _T_2389 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_2315 ? _a_set_T : 2'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_2315 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [4:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [4:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_2315 ? _a_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [3:0] _a_opcodes_set_T = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [18:0] _a_opcodes_set_T_1 = {15'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_2315 ? _a_opcodes_set_T_1[7:0] : 8'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [3:0] _a_sizes_set_T = {io_in_a_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :660:77] wire [19:0] _a_sizes_set_T_1 = {15'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :660:{52,77}] assign a_sizes_set = _T_2315 ? _a_sizes_set_T_1[15:0] : 16'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [1:0] d_clr; // @[Monitor.scala:664:34] wire [1:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [7:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [15:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_23 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_23; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_23; // @[Monitor.scala:673:46, :783:46] wire _T_2361 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [1:0] _GEN_24 = {1'h0, io_in_d_bits_source_0}; // @[OneHot.scala:58:35] wire [1:0] _GEN_25 = 2'h1 << _GEN_24; // @[OneHot.scala:58:35] wire [1:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_25; // @[OneHot.scala:58:35] wire [1:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_25; // @[OneHot.scala:58:35] wire [1:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_25; // @[OneHot.scala:58:35] wire [1:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_25; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_2361 & ~d_release_ack ? _d_clr_wo_ready_T : 2'h0; // @[OneHot.scala:58:35] wire _T_2330 = _T_2463 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_2330 ? _d_clr_T : 2'h0; // @[OneHot.scala:58:35] wire [30:0] _d_opcodes_clr_T_5 = 31'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_2330 ? _d_opcodes_clr_T_5[7:0] : 8'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [30:0] _d_sizes_clr_T_5 = 31'hFF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_2330 ? _d_sizes_clr_T_5[15:0] : 16'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [1:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [1:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [1:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [7:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [7:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [7:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [15:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [15:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [15:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [1:0] inflight_1; // @[Monitor.scala:726:35] reg [7:0] inflight_opcodes_1; // @[Monitor.scala:727:35] reg [15:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [11:0] _c_first_beats1_decode_T_4 = _c_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _c_first_beats1_decode_T_5 = ~_c_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] c_first_beats1_decode_1 = _c_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire [8:0] c_first_beats1_1 = c_first_beats1_opdata_1 ? c_first_beats1_decode_1 : 9'h0; // @[Edges.scala:102:36, :220:59, :221:14] reg [8:0] c_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _c_first_counter1_T_1 = {1'h0, c_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] c_first_counter1_1 = _c_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire c_first_1 = c_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _c_first_last_T_2 = c_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _c_first_last_T_3 = c_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire c_first_last_1 = _c_first_last_T_2 | _c_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire c_first_done_1 = c_first_last_1 & _c_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _c_first_count_T_1 = ~c_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] c_first_count_1 = c_first_beats1_1 & _c_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _c_first_counter_T_1 = c_first_1 ? c_first_beats1_1 : c_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [11:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_2; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_2 = _d_first_counter1_T_2[8:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [1:0] c_set; // @[Monitor.scala:738:34] wire [1:0] c_set_wo_ready; // @[Monitor.scala:739:34] wire [7:0] c_opcodes_set; // @[Monitor.scala:740:34] wire [15:0] c_sizes_set; // @[Monitor.scala:741:34] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [7:0] c_size_lookup; // @[Monitor.scala:748:35] wire [7:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [15:0] _c_opcode_lookup_T_6 = {8'h0, _c_opcode_lookup_T_1 & 8'hF}; // @[Monitor.scala:749:{44,97}] wire [15:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [15:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [15:0] _c_size_lookup_T_6 = _c_size_lookup_T_1 & 16'hFF; // @[Monitor.scala:750:{42,93}] wire [15:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[15:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[7:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [3:0] c_opcodes_set_interm; // @[Monitor.scala:754:40] wire [4:0] c_sizes_set_interm; // @[Monitor.scala:755:40] wire _same_cycle_resp_T_3 = io_in_c_valid_0 & c_first_1; // @[Monitor.scala:36:7, :759:26, :795:44] wire _same_cycle_resp_T_4 = io_in_c_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _same_cycle_resp_T_5 = io_in_c_bits_opcode_0[1]; // @[Monitor.scala:36:7] wire [1:0] _GEN_26 = {1'h0, io_in_c_bits_source_0}; // @[OneHot.scala:58:35] wire [1:0] _GEN_27 = 2'h1 << _GEN_26; // @[OneHot.scala:58:35] wire [1:0] _c_set_wo_ready_T; // @[OneHot.scala:58:35] assign _c_set_wo_ready_T = _GEN_27; // @[OneHot.scala:58:35] wire [1:0] _c_set_T; // @[OneHot.scala:58:35] assign _c_set_T = _GEN_27; // @[OneHot.scala:58:35] assign c_set_wo_ready = _same_cycle_resp_T_3 & _same_cycle_resp_T_4 & _same_cycle_resp_T_5 ? _c_set_wo_ready_T : 2'h0; // @[OneHot.scala:58:35] wire _T_2402 = _T_2460 & c_first_1 & _same_cycle_resp_T_4 & _same_cycle_resp_T_5; // @[Decoupled.scala:51:35] assign c_set = _T_2402 ? _c_set_T : 2'h0; // @[OneHot.scala:58:35] wire [3:0] _c_opcodes_set_interm_T = {io_in_c_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :765:53] wire [3:0] _c_opcodes_set_interm_T_1 = {_c_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:765:{53,61}] assign c_opcodes_set_interm = _T_2402 ? _c_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:754:40, :763:{25,36,70}, :765:{28,61}] wire [4:0] _c_sizes_set_interm_T = {io_in_c_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :766:51] wire [4:0] _c_sizes_set_interm_T_1 = {_c_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:766:{51,59}] assign c_sizes_set_interm = _T_2402 ? _c_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:755:40, :763:{25,36,70}, :766:{28,59}] wire [3:0] _c_opcodes_set_T = {1'h0, io_in_c_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :767:79] wire [18:0] _c_opcodes_set_T_1 = {15'h0, c_opcodes_set_interm} << _c_opcodes_set_T; // @[Monitor.scala:754:40, :767:{54,79}] assign c_opcodes_set = _T_2402 ? _c_opcodes_set_T_1[7:0] : 8'h0; // @[Monitor.scala:740:34, :763:{25,36,70}, :767:{28,54}] wire [3:0] _c_sizes_set_T = {io_in_c_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :768:77] wire [19:0] _c_sizes_set_T_1 = {15'h0, c_sizes_set_interm} << _c_sizes_set_T; // @[Monitor.scala:755:40, :768:{52,77}] assign c_sizes_set = _T_2402 ? _c_sizes_set_T_1[15:0] : 16'h0; // @[Monitor.scala:741:34, :763:{25,36,70}, :768:{28,52}] wire _c_probe_ack_T = io_in_c_bits_opcode_0 == 3'h4; // @[Monitor.scala:36:7, :772:47] wire _c_probe_ack_T_1 = io_in_c_bits_opcode_0 == 3'h5; // @[Monitor.scala:36:7, :772:95] wire c_probe_ack = _c_probe_ack_T | _c_probe_ack_T_1; // @[Monitor.scala:772:{47,71,95}] wire [1:0] d_clr_1; // @[Monitor.scala:774:34] wire [1:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [7:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [15:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_2433 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_2433 & d_release_ack_1 ? _d_clr_wo_ready_T_1 : 2'h0; // @[OneHot.scala:58:35] wire _T_2415 = _T_2463 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_2415 ? _d_clr_T_1 : 2'h0; // @[OneHot.scala:58:35] wire [30:0] _d_opcodes_clr_T_11 = 31'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_2415 ? _d_opcodes_clr_T_11[7:0] : 8'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [30:0] _d_sizes_clr_T_11 = 31'hFF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_2415 ? _d_sizes_clr_T_11[15:0] : 16'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_6 = _same_cycle_resp_T_4 & _same_cycle_resp_T_5; // @[Edges.scala:68:{36,40,51}] wire _same_cycle_resp_T_7 = _same_cycle_resp_T_3 & _same_cycle_resp_T_6; // @[Monitor.scala:795:{44,55}] wire _same_cycle_resp_T_8 = io_in_c_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :795:113] wire same_cycle_resp_1 = _same_cycle_resp_T_7 & _same_cycle_resp_T_8; // @[Monitor.scala:795:{55,88,113}] wire [1:0] _inflight_T_3 = inflight_1 | c_set; // @[Monitor.scala:726:35, :738:34, :814:35] wire [1:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [1:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [7:0] _inflight_opcodes_T_3 = inflight_opcodes_1 | c_opcodes_set; // @[Monitor.scala:727:35, :740:34, :815:43] wire [7:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [7:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [15:0] _inflight_sizes_T_3 = inflight_sizes_1 | c_sizes_set; // @[Monitor.scala:728:35, :741:34, :816:41] wire [15:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [15:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27] wire [32:0] _watchdog_T_2 = {1'h0, watchdog_1} + 33'h1; // @[Monitor.scala:818:27, :823:26] wire [31:0] _watchdog_T_3 = _watchdog_T_2[31:0]; // @[Monitor.scala:823:26] reg [7:0] inflight_2; // @[Monitor.scala:828:27] wire [11:0] _d_first_beats1_decode_T_10 = _d_first_beats1_decode_T_9[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_11 = ~_d_first_beats1_decode_T_10; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_3 = _d_first_beats1_decode_T_11[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_3 = d_first_beats1_opdata_3 ? d_first_beats1_decode_3 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_3; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_3 = {1'h0, d_first_counter_3} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_3 = _d_first_counter1_T_3[8:0]; // @[Edges.scala:230:28] wire d_first_3 = d_first_counter_3 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_6 = d_first_counter_3 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_7 = d_first_beats1_3 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_3 = _d_first_last_T_6 | _d_first_last_T_7; // @[Edges.scala:232:{25,33,43}] wire d_first_done_3 = d_first_last_3 & _d_first_T_3; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_3 = ~d_first_counter1_3; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_3 = d_first_beats1_3 & _d_first_count_T_3; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_3 = d_first_3 ? d_first_beats1_3 : d_first_counter1_3; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [7:0] d_set; // @[Monitor.scala:833:25] wire _T_2469 = _T_2463 & d_first_3 & io_in_d_bits_opcode_0[2] & ~(io_in_d_bits_opcode_0[1]); // @[Decoupled.scala:51:35] wire [7:0] _GEN_28 = {5'h0, io_in_d_bits_sink_0}; // @[OneHot.scala:58:35] wire [7:0] _d_set_T = 8'h1 << _GEN_28; // @[OneHot.scala:58:35] assign d_set = _T_2469 ? _d_set_T : 8'h0; // @[OneHot.scala:58:35] wire [7:0] e_clr; // @[Monitor.scala:839:25] wire _T_2478 = io_in_e_ready_0 & io_in_e_valid_0; // @[Decoupled.scala:51:35] wire [7:0] _GEN_29 = {5'h0, io_in_e_bits_sink_0}; // @[OneHot.scala:58:35] wire [7:0] _e_clr_T = 8'h1 << _GEN_29; // @[OneHot.scala:58:35] assign e_clr = _T_2478 ? _e_clr_T : 8'h0; // @[OneHot.scala:58:35]

Generate the Verilog code corresponding to the following Chisel files. File SynchronizerReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util.{RegEnable, Cat} /** These wrap behavioral * shift and next registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * * These are built up of *ResetSynchronizerPrimitiveShiftReg, * intended to be replaced by the integrator's metastable flops chains or replaced * at this level if they have a multi-bit wide synchronizer primitive. * The different types vary in their reset behavior: * NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin * AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep * 1-bit-wide shift registers. * SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg * * [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference. * * ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross * Clock Domains. */ object SynchronizerResetType extends Enumeration { val NonSync, Inferred, Sync, Async = Value } // Note: this should not be used directly. // Use the companion object to generate this with the correct reset type mixin. private class SynchronizerPrimitiveShiftReg( sync: Int, init: Boolean, resetType: SynchronizerResetType.Value) extends AbstractPipelineReg(1) { val initInt = if (init) 1 else 0 val initPostfix = resetType match { case SynchronizerResetType.NonSync => "" case _ => s"_i${initInt}" } override def desiredName = s"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}" val chain = List.tabulate(sync) { i => val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B) reg.suggestName(s"sync_$i") } chain.last := io.d.asBool (chain.init zip chain.tail).foreach { case (sink, source) => sink := source } io.q := chain.head.asUInt } private object SynchronizerPrimitiveShiftReg { def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = { val gen: () => SynchronizerPrimitiveShiftReg = resetType match { case SynchronizerResetType.NonSync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) case SynchronizerResetType.Async => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset case SynchronizerResetType.Sync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset case SynchronizerResetType.Inferred => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) } AbstractPipelineReg(gen(), in) } } // Note: This module may end up with a non-AsyncReset type reset. // But the Primitives within will always have AsyncReset type. class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asAsyncReset){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async) } } io.q := Cat(output.reverse) } object AsyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } // Note: This module may end up with a non-Bool type reset. // But the Primitives within will always have Bool reset type. @deprecated("SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.", "rocket-chip 1.2") class SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asBool){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync) } } io.q := Cat(output.reverse) } object SyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred) } io.q := Cat(output.reverse) } object ResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}" val output = Seq.tabulate(w) { i => SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync) } io.q := Cat(output.reverse) } object SynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, None) def apply [T <: Data](in: T): T = apply (in, 3, None) } class ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module { override def desiredName = s"ClockCrossingReg_w${w}" val io = IO(new Bundle{ val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) val en = Input(Bool()) }) val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en) io.q := cdc_reg } object ClockCrossingReg { def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = { val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit)) name.foreach{ cdc_reg.suggestName(_) } cdc_reg.io.d := in.asUInt cdc_reg.io.en := en cdc_reg.io.q.asTypeOf(in) } }

module ClockCrossingReg_w32_9( // @[SynchronizerReg.scala:191:7] input clock, // @[SynchronizerReg.scala:191:7] input reset, // @[SynchronizerReg.scala:191:7] input [31:0] io_d, // @[SynchronizerReg.scala:195:14] output [31:0] io_q, // @[SynchronizerReg.scala:195:14] input io_en // @[SynchronizerReg.scala:195:14] ); wire [31:0] io_d_0 = io_d; // @[SynchronizerReg.scala:191:7] wire io_en_0 = io_en; // @[SynchronizerReg.scala:191:7] wire [31:0] io_q_0; // @[SynchronizerReg.scala:191:7] reg [31:0] cdc_reg; // @[SynchronizerReg.scala:201:76] assign io_q_0 = cdc_reg; // @[SynchronizerReg.scala:191:7, :201:76] always @(posedge clock) begin // @[SynchronizerReg.scala:191:7] if (io_en_0) // @[SynchronizerReg.scala:191:7] cdc_reg <= io_d_0; // @[SynchronizerReg.scala:191:7, :201:76] always @(posedge) assign io_q = io_q_0; // @[SynchronizerReg.scala:191:7] endmodule

Generate the Verilog code corresponding to the following Chisel files. File Error.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.devices.tilelink import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.resources.SimpleDevice import freechips.rocketchip.tilelink.{TLArbiter, TLMessages, TLPermissions} /** Adds a /dev/null slave that generates TL error response messages */ class TLError(params: DevNullParams, buffer: Boolean = true, beatBytes: Int = 4)(implicit p: Parameters) extends DevNullDevice(params, minLatency = if (buffer) 1 else 0, beatBytes, new SimpleDevice("error-device", Seq("sifive,error0"))) { lazy val module = new Impl class Impl extends LazyModuleImp(this) { import TLMessages._ import TLPermissions._ val (in, edge) = node.in(0) val a = if (buffer) {Queue(in.a, 1)} else in.a val da = Wire(chiselTypeOf(in.d)) val idle = RegInit(true.B) val a_last = edge.last(a) val (da_first, da_last, _) = edge.firstlast(da) assert (idle || da_first) // we only send Grant, never GrantData => simplified flow control below a.ready := (da.ready && da_last && idle) || !a_last da.valid := a.valid && a_last && idle da.bits.opcode := TLMessages.adResponse(a.bits.opcode) da.bits.param := 0.U // toT, but error grants must be handled transiently (ie: you don't keep permissions) da.bits.size := a.bits.size da.bits.source := a.bits.source da.bits.sink := 0.U da.bits.denied := true.B da.bits.data := 0.U da.bits.corrupt := edge.hasData(da.bits) if (params.acquire) { val c = if (buffer) {Queue(in.c, 1)} else in.c val dc = Wire(chiselTypeOf(in.d)) val c_last = edge.last(c) val dc_last = edge.last(dc) // Only allow one Grant in-flight at a time when (da.fire && da.bits.opcode === Grant) { idle := false.B } when (in.e.fire) { idle := true.B } c.ready := (dc.ready && dc_last) || !c_last dc.valid := c.valid && c_last // ReleaseAck is not allowed to report failure dc.bits.opcode := ReleaseAck dc.bits.param := VecInit(toB, toN, toN)(c.bits.param(1,0)) dc.bits.size := c.bits.size dc.bits.source := c.bits.source dc.bits.sink := 0.U dc.bits.denied := false.B dc.bits.data := 0.U dc.bits.corrupt := false.B // Combine response channels TLArbiter.lowest(edge, in.d, dc, da) } else { in.d <> da } // We never probe or issue B requests in.b.valid := false.B // Sink GrantAcks in.e.ready := true.B } } File Nodes.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.nodes._ import freechips.rocketchip.util.{AsyncQueueParams,RationalDirection} case object TLMonitorBuilder extends Field[TLMonitorArgs => TLMonitorBase](args => new TLMonitor(args)) object TLImp extends NodeImp[TLMasterPortParameters, TLSlavePortParameters, TLEdgeOut, TLEdgeIn, TLBundle] { def edgeO(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeOut(pd, pu, p, sourceInfo) def edgeI(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeIn (pd, pu, p, sourceInfo) def bundleO(eo: TLEdgeOut) = TLBundle(eo.bundle) def bundleI(ei: TLEdgeIn) = TLBundle(ei.bundle) def render(ei: TLEdgeIn) = RenderedEdge(colour = "#000000" /* black */, label = (ei.manager.beatBytes * 8).toString) override def monitor(bundle: TLBundle, edge: TLEdgeIn): Unit = { val monitor = Module(edge.params(TLMonitorBuilder)(TLMonitorArgs(edge))) monitor.io.in := bundle } override def mixO(pd: TLMasterPortParameters, node: OutwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLMasterPortParameters = pd.v1copy(clients = pd.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }) override def mixI(pu: TLSlavePortParameters, node: InwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLSlavePortParameters = pu.v1copy(managers = pu.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }) } trait TLFormatNode extends FormatNode[TLEdgeIn, TLEdgeOut] case class TLClientNode(portParams: Seq[TLMasterPortParameters])(implicit valName: ValName) extends SourceNode(TLImp)(portParams) with TLFormatNode case class TLManagerNode(portParams: Seq[TLSlavePortParameters])(implicit valName: ValName) extends SinkNode(TLImp)(portParams) with TLFormatNode case class TLAdapterNode( clientFn: TLMasterPortParameters => TLMasterPortParameters = { s => s }, managerFn: TLSlavePortParameters => TLSlavePortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLImp)(clientFn, managerFn) with TLFormatNode case class TLJunctionNode( clientFn: Seq[TLMasterPortParameters] => Seq[TLMasterPortParameters], managerFn: Seq[TLSlavePortParameters] => Seq[TLSlavePortParameters])( implicit valName: ValName) extends JunctionNode(TLImp)(clientFn, managerFn) with TLFormatNode case class TLIdentityNode()(implicit valName: ValName) extends IdentityNode(TLImp)() with TLFormatNode object TLNameNode { def apply(name: ValName) = TLIdentityNode()(name) def apply(name: Option[String]): TLIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLIdentityNode = apply(Some(name)) } case class TLEphemeralNode()(implicit valName: ValName) extends EphemeralNode(TLImp)() object TLTempNode { def apply(): TLEphemeralNode = TLEphemeralNode()(ValName("temp")) } case class TLNexusNode( clientFn: Seq[TLMasterPortParameters] => TLMasterPortParameters, managerFn: Seq[TLSlavePortParameters] => TLSlavePortParameters)( implicit valName: ValName) extends NexusNode(TLImp)(clientFn, managerFn) with TLFormatNode abstract class TLCustomNode(implicit valName: ValName) extends CustomNode(TLImp) with TLFormatNode // Asynchronous crossings trait TLAsyncFormatNode extends FormatNode[TLAsyncEdgeParameters, TLAsyncEdgeParameters] object TLAsyncImp extends SimpleNodeImp[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncEdgeParameters, TLAsyncBundle] { def edge(pd: TLAsyncClientPortParameters, pu: TLAsyncManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLAsyncEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLAsyncEdgeParameters) = new TLAsyncBundle(e.bundle) def render(e: TLAsyncEdgeParameters) = RenderedEdge(colour = "#ff0000" /* red */, label = e.manager.async.depth.toString) override def mixO(pd: TLAsyncClientPortParameters, node: OutwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLAsyncManagerPortParameters, node: InwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLAsyncAdapterNode( clientFn: TLAsyncClientPortParameters => TLAsyncClientPortParameters = { s => s }, managerFn: TLAsyncManagerPortParameters => TLAsyncManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLAsyncImp)(clientFn, managerFn) with TLAsyncFormatNode case class TLAsyncIdentityNode()(implicit valName: ValName) extends IdentityNode(TLAsyncImp)() with TLAsyncFormatNode object TLAsyncNameNode { def apply(name: ValName) = TLAsyncIdentityNode()(name) def apply(name: Option[String]): TLAsyncIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLAsyncIdentityNode = apply(Some(name)) } case class TLAsyncSourceNode(sync: Option[Int])(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLAsyncImp)( dFn = { p => TLAsyncClientPortParameters(p) }, uFn = { p => p.base.v1copy(minLatency = p.base.minLatency + sync.getOrElse(p.async.sync)) }) with FormatNode[TLEdgeIn, TLAsyncEdgeParameters] // discard cycles in other clock domain case class TLAsyncSinkNode(async: AsyncQueueParams)(implicit valName: ValName) extends MixedAdapterNode(TLAsyncImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = p.base.minLatency + async.sync) }, uFn = { p => TLAsyncManagerPortParameters(async, p) }) with FormatNode[TLAsyncEdgeParameters, TLEdgeOut] // Rationally related crossings trait TLRationalFormatNode extends FormatNode[TLRationalEdgeParameters, TLRationalEdgeParameters] object TLRationalImp extends SimpleNodeImp[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalEdgeParameters, TLRationalBundle] { def edge(pd: TLRationalClientPortParameters, pu: TLRationalManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLRationalEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLRationalEdgeParameters) = new TLRationalBundle(e.bundle) def render(e: TLRationalEdgeParameters) = RenderedEdge(colour = "#00ff00" /* green */) override def mixO(pd: TLRationalClientPortParameters, node: OutwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLRationalManagerPortParameters, node: InwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLRationalAdapterNode( clientFn: TLRationalClientPortParameters => TLRationalClientPortParameters = { s => s }, managerFn: TLRationalManagerPortParameters => TLRationalManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLRationalImp)(clientFn, managerFn) with TLRationalFormatNode case class TLRationalIdentityNode()(implicit valName: ValName) extends IdentityNode(TLRationalImp)() with TLRationalFormatNode object TLRationalNameNode { def apply(name: ValName) = TLRationalIdentityNode()(name) def apply(name: Option[String]): TLRationalIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLRationalIdentityNode = apply(Some(name)) } case class TLRationalSourceNode()(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLRationalImp)( dFn = { p => TLRationalClientPortParameters(p) }, uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLRationalEdgeParameters] // discard cycles from other clock domain case class TLRationalSinkNode(direction: RationalDirection)(implicit valName: ValName) extends MixedAdapterNode(TLRationalImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = 1) }, uFn = { p => TLRationalManagerPortParameters(direction, p) }) with FormatNode[TLRationalEdgeParameters, TLEdgeOut] // Credited version of TileLink channels trait TLCreditedFormatNode extends FormatNode[TLCreditedEdgeParameters, TLCreditedEdgeParameters] object TLCreditedImp extends SimpleNodeImp[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedEdgeParameters, TLCreditedBundle] { def edge(pd: TLCreditedClientPortParameters, pu: TLCreditedManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLCreditedEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLCreditedEdgeParameters) = new TLCreditedBundle(e.bundle) def render(e: TLCreditedEdgeParameters) = RenderedEdge(colour = "#ffff00" /* yellow */, e.delay.toString) override def mixO(pd: TLCreditedClientPortParameters, node: OutwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLCreditedManagerPortParameters, node: InwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLCreditedAdapterNode( clientFn: TLCreditedClientPortParameters => TLCreditedClientPortParameters = { s => s }, managerFn: TLCreditedManagerPortParameters => TLCreditedManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLCreditedImp)(clientFn, managerFn) with TLCreditedFormatNode case class TLCreditedIdentityNode()(implicit valName: ValName) extends IdentityNode(TLCreditedImp)() with TLCreditedFormatNode object TLCreditedNameNode { def apply(name: ValName) = TLCreditedIdentityNode()(name) def apply(name: Option[String]): TLCreditedIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLCreditedIdentityNode = apply(Some(name)) } case class TLCreditedSourceNode(delay: TLCreditedDelay)(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLCreditedImp)( dFn = { p => TLCreditedClientPortParameters(delay, p) }, uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLCreditedEdgeParameters] // discard cycles from other clock domain case class TLCreditedSinkNode(delay: TLCreditedDelay)(implicit valName: ValName) extends MixedAdapterNode(TLCreditedImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = 1) }, uFn = { p => TLCreditedManagerPortParameters(delay, p) }) with FormatNode[TLCreditedEdgeParameters, TLEdgeOut] File Bundles.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import freechips.rocketchip.util._ import scala.collection.immutable.ListMap import chisel3.util.Decoupled import chisel3.util.DecoupledIO import chisel3.reflect.DataMirror abstract class TLBundleBase(val params: TLBundleParameters) extends Bundle // common combos in lazy policy: // Put + Acquire // Release + AccessAck object TLMessages { // A B C D E def PutFullData = 0.U // . . => AccessAck def PutPartialData = 1.U // . . => AccessAck def ArithmeticData = 2.U // . . => AccessAckData def LogicalData = 3.U // . . => AccessAckData def Get = 4.U // . . => AccessAckData def Hint = 5.U // . . => HintAck def AcquireBlock = 6.U // . => Grant[Data] def AcquirePerm = 7.U // . => Grant[Data] def Probe = 6.U // . => ProbeAck[Data] def AccessAck = 0.U // . . def AccessAckData = 1.U // . . def HintAck = 2.U // . . def ProbeAck = 4.U // . def ProbeAckData = 5.U // . def Release = 6.U // . => ReleaseAck def ReleaseData = 7.U // . => ReleaseAck def Grant = 4.U // . => GrantAck def GrantData = 5.U // . => GrantAck def ReleaseAck = 6.U // . def GrantAck = 0.U // . def isA(x: UInt) = x <= AcquirePerm def isB(x: UInt) = x <= Probe def isC(x: UInt) = x <= ReleaseData def isD(x: UInt) = x <= ReleaseAck def adResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, Grant, Grant) def bcResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, ProbeAck, ProbeAck) def a = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("AcquireBlock",TLPermissions.PermMsgGrow), ("AcquirePerm",TLPermissions.PermMsgGrow)) def b = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("Probe",TLPermissions.PermMsgCap)) def c = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("ProbeAck",TLPermissions.PermMsgReport), ("ProbeAckData",TLPermissions.PermMsgReport), ("Release",TLPermissions.PermMsgReport), ("ReleaseData",TLPermissions.PermMsgReport)) def d = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("Grant",TLPermissions.PermMsgCap), ("GrantData",TLPermissions.PermMsgCap), ("ReleaseAck",TLPermissions.PermMsgReserved)) } /** * The three primary TileLink permissions are: * (T)runk: the agent is (or is on inwards path to) the global point of serialization. * (B)ranch: the agent is on an outwards path to * (N)one: * These permissions are permuted by transfer operations in various ways. * Operations can cap permissions, request for them to be grown or shrunk, * or for a report on their current status. */ object TLPermissions { val aWidth = 2 val bdWidth = 2 val cWidth = 3 // Cap types (Grant = new permissions, Probe = permisions <= target) def toT = 0.U(bdWidth.W) def toB = 1.U(bdWidth.W) def toN = 2.U(bdWidth.W) def isCap(x: UInt) = x <= toN // Grow types (Acquire = permissions >= target) def NtoB = 0.U(aWidth.W) def NtoT = 1.U(aWidth.W) def BtoT = 2.U(aWidth.W) def isGrow(x: UInt) = x <= BtoT // Shrink types (ProbeAck, Release) def TtoB = 0.U(cWidth.W) def TtoN = 1.U(cWidth.W) def BtoN = 2.U(cWidth.W) def isShrink(x: UInt) = x <= BtoN // Report types (ProbeAck, Release) def TtoT = 3.U(cWidth.W) def BtoB = 4.U(cWidth.W) def NtoN = 5.U(cWidth.W) def isReport(x: UInt) = x <= NtoN def PermMsgGrow:Seq[String] = Seq("Grow NtoB", "Grow NtoT", "Grow BtoT") def PermMsgCap:Seq[String] = Seq("Cap toT", "Cap toB", "Cap toN") def PermMsgReport:Seq[String] = Seq("Shrink TtoB", "Shrink TtoN", "Shrink BtoN", "Report TotT", "Report BtoB", "Report NtoN") def PermMsgReserved:Seq[String] = Seq("Reserved") } object TLAtomics { val width = 3 // Arithmetic types def MIN = 0.U(width.W) def MAX = 1.U(width.W) def MINU = 2.U(width.W) def MAXU = 3.U(width.W) def ADD = 4.U(width.W) def isArithmetic(x: UInt) = x <= ADD // Logical types def XOR = 0.U(width.W) def OR = 1.U(width.W) def AND = 2.U(width.W) def SWAP = 3.U(width.W) def isLogical(x: UInt) = x <= SWAP def ArithMsg:Seq[String] = Seq("MIN", "MAX", "MINU", "MAXU", "ADD") def LogicMsg:Seq[String] = Seq("XOR", "OR", "AND", "SWAP") } object TLHints { val width = 1 def PREFETCH_READ = 0.U(width.W) def PREFETCH_WRITE = 1.U(width.W) def isHints(x: UInt) = x <= PREFETCH_WRITE def HintsMsg:Seq[String] = Seq("PrefetchRead", "PrefetchWrite") } sealed trait TLChannel extends TLBundleBase { val channelName: String } sealed trait TLDataChannel extends TLChannel sealed trait TLAddrChannel extends TLDataChannel final class TLBundleA(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleA_${params.shortName}" val channelName = "'A' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(List(TLAtomics.width, TLPermissions.aWidth, TLHints.width).max.W) // amo_opcode || grow perms || hint val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleB(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleB_${params.shortName}" val channelName = "'B' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val address = UInt(params.addressBits.W) // from // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleC(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleC_${params.shortName}" val channelName = "'C' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.cWidth.W) // shrink or report perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleD(params: TLBundleParameters) extends TLBundleBase(params) with TLDataChannel { override def typeName = s"TLBundleD_${params.shortName}" val channelName = "'D' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val sink = UInt(params.sinkBits.W) // from val denied = Bool() // implies corrupt iff *Data val user = BundleMap(params.responseFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleE(params: TLBundleParameters) extends TLBundleBase(params) with TLChannel { override def typeName = s"TLBundleE_${params.shortName}" val channelName = "'E' channel" val sink = UInt(params.sinkBits.W) // to } class TLBundle(val params: TLBundleParameters) extends Record { // Emulate a Bundle with elements abcde or ad depending on params.hasBCE private val optA = Some (Decoupled(new TLBundleA(params))) private val optB = params.hasBCE.option(Flipped(Decoupled(new TLBundleB(params)))) private val optC = params.hasBCE.option(Decoupled(new TLBundleC(params))) private val optD = Some (Flipped(Decoupled(new TLBundleD(params)))) private val optE = params.hasBCE.option(Decoupled(new TLBundleE(params))) def a: DecoupledIO[TLBundleA] = optA.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleA(params))))) def b: DecoupledIO[TLBundleB] = optB.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleB(params))))) def c: DecoupledIO[TLBundleC] = optC.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleC(params))))) def d: DecoupledIO[TLBundleD] = optD.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleD(params))))) def e: DecoupledIO[TLBundleE] = optE.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleE(params))))) val elements = if (params.hasBCE) ListMap("e" -> e, "d" -> d, "c" -> c, "b" -> b, "a" -> a) else ListMap("d" -> d, "a" -> a) def tieoff(): Unit = { DataMirror.specifiedDirectionOf(a.ready) match { case SpecifiedDirection.Input => a.ready := false.B c.ready := false.B e.ready := false.B b.valid := false.B d.valid := false.B case SpecifiedDirection.Output => a.valid := false.B c.valid := false.B e.valid := false.B b.ready := false.B d.ready := false.B case _ => } } } object TLBundle { def apply(params: TLBundleParameters) = new TLBundle(params) } class TLAsyncBundleBase(val params: TLAsyncBundleParameters) extends Bundle class TLAsyncBundle(params: TLAsyncBundleParameters) extends TLAsyncBundleBase(params) { val a = new AsyncBundle(new TLBundleA(params.base), params.async) val b = Flipped(new AsyncBundle(new TLBundleB(params.base), params.async)) val c = new AsyncBundle(new TLBundleC(params.base), params.async) val d = Flipped(new AsyncBundle(new TLBundleD(params.base), params.async)) val e = new AsyncBundle(new TLBundleE(params.base), params.async) } class TLRationalBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = RationalIO(new TLBundleA(params)) val b = Flipped(RationalIO(new TLBundleB(params))) val c = RationalIO(new TLBundleC(params)) val d = Flipped(RationalIO(new TLBundleD(params))) val e = RationalIO(new TLBundleE(params)) } class TLCreditedBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = CreditedIO(new TLBundleA(params)) val b = Flipped(CreditedIO(new TLBundleB(params))) val c = CreditedIO(new TLBundleC(params)) val d = Flipped(CreditedIO(new TLBundleD(params))) val e = CreditedIO(new TLBundleE(params)) } File LazyModuleImp.scala: package org.chipsalliance.diplomacy.lazymodule import chisel3.{withClockAndReset, Module, RawModule, Reset, _} import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo} import firrtl.passes.InlineAnnotation import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.nodes.Dangle import scala.collection.immutable.SortedMap /** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]]. * * This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy. */ sealed trait LazyModuleImpLike extends RawModule { /** [[LazyModule]] that contains this instance. */ val wrapper: LazyModule /** IOs that will be automatically "punched" for this instance. */ val auto: AutoBundle /** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */ protected[diplomacy] val dangles: Seq[Dangle] // [[wrapper.module]] had better not be accessed while LazyModules are still being built! require( LazyModule.scope.isEmpty, s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}" ) /** Set module name. Defaults to the containing LazyModule's desiredName. */ override def desiredName: String = wrapper.desiredName suggestName(wrapper.suggestedName) /** [[Parameters]] for chisel [[Module]]s. */ implicit val p: Parameters = wrapper.p /** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and * submodules. */ protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = { // 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]], // 2. return [[Dangle]]s from each module. val childDangles = wrapper.children.reverse.flatMap { c => implicit val sourceInfo: SourceInfo = c.info c.cloneProto.map { cp => // If the child is a clone, then recursively set cloneProto of its children as well def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = { require(bases.size == clones.size) (bases.zip(clones)).map { case (l, r) => require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}") l.cloneProto = Some(r) assignCloneProtos(l.children, r.children) } } assignCloneProtos(c.children, cp.children) // Clone the child module as a record, and get its [[AutoBundle]] val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName) val clonedAuto = clone("auto").asInstanceOf[AutoBundle] // Get the empty [[Dangle]]'s of the cloned child val rawDangles = c.cloneDangles() require(rawDangles.size == clonedAuto.elements.size) // Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) } dangles }.getOrElse { // For non-clones, instantiate the child module val mod = try { Module(c.module) } catch { case e: ChiselException => { println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}") throw e } } mod.dangles } } // Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]]. // This will result in a sequence of [[Dangle]] from these [[BaseNode]]s. val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate()) // Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]] val allDangles = nodeDangles ++ childDangles // Group [[allDangles]] by their [[source]]. val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*) // For each [[source]] set of [[Dangle]]s of size 2, ensure that these // can be connected as a source-sink pair (have opposite flipped value). // Make the connection and mark them as [[done]]. val done = Set() ++ pairing.values.filter(_.size == 2).map { case Seq(a, b) => require(a.flipped != b.flipped) // @todo <> in chisel3 makes directionless connection. if (a.flipped) { a.data <> b.data } else { b.data <> a.data } a.source case _ => None } // Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module. val forward = allDangles.filter(d => !done(d.source)) // Generate [[AutoBundle]] IO from [[forward]]. val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*)) // Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]] val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) => if (d.flipped) { d.data <> io } else { io <> d.data } d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name) } // Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]]. wrapper.inModuleBody.reverse.foreach { _() } if (wrapper.shouldBeInlined) { chisel3.experimental.annotate(new ChiselAnnotation { def toFirrtl = InlineAnnotation(toNamed) }) } // Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]]. (auto, dangles) } } /** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike { /** Instantiate hardware of this `Module`. */ val (auto, dangles) = instantiate() } /** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike { // These wires are the default clock+reset for all LazyModule children. // It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the // [[LazyRawModuleImp]] children. // Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly. /** drive clock explicitly. */ val childClock: Clock = Wire(Clock()) /** drive reset explicitly. */ val childReset: Reset = Wire(Reset()) // the default is that these are disabled childClock := false.B.asClock childReset := chisel3.DontCare def provideImplicitClockToLazyChildren: Boolean = false val (auto, dangles) = if (provideImplicitClockToLazyChildren) { withClockAndReset(childClock, childReset) { instantiate() } } else { instantiate() } } File MixedNode.scala: package org.chipsalliance.diplomacy.nodes import chisel3.{Data, DontCare, Wire} import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.{Field, Parameters} import org.chipsalliance.diplomacy.ValName import org.chipsalliance.diplomacy.sourceLine /** One side metadata of a [[Dangle]]. * * Describes one side of an edge going into or out of a [[BaseNode]]. * * @param serial * the global [[BaseNode.serial]] number of the [[BaseNode]] that this [[HalfEdge]] connects to. * @param index * the `index` in the [[BaseNode]]'s input or output port list that this [[HalfEdge]] belongs to. */ case class HalfEdge(serial: Int, index: Int) extends Ordered[HalfEdge] { import scala.math.Ordered.orderingToOrdered def compare(that: HalfEdge): Int = HalfEdge.unapply(this).compare(HalfEdge.unapply(that)) } /** [[Dangle]] captures the `IO` information of a [[LazyModule]] and which two [[BaseNode]]s the [[Edges]]/[[Bundle]] * connects. * * [[Dangle]]s are generated by [[BaseNode.instantiate]] using [[MixedNode.danglesOut]] and [[MixedNode.danglesIn]] , * [[LazyModuleImp.instantiate]] connects those that go to internal or explicit IO connections in a [[LazyModule]]. * * @param source * the source [[HalfEdge]] of this [[Dangle]], which captures the source [[BaseNode]] and the port `index` within * that [[BaseNode]]. * @param sink * sink [[HalfEdge]] of this [[Dangle]], which captures the sink [[BaseNode]] and the port `index` within that * [[BaseNode]]. * @param flipped * flip or not in [[AutoBundle.makeElements]]. If true this corresponds to `danglesOut`, if false it corresponds to * `danglesIn`. * @param dataOpt * actual [[Data]] for the hardware connection. Can be empty if this belongs to a cloned module */ case class Dangle(source: HalfEdge, sink: HalfEdge, flipped: Boolean, name: String, dataOpt: Option[Data]) { def data = dataOpt.get } /** [[Edges]] is a collection of parameters describing the functionality and connection for an interface, which is often * derived from the interconnection protocol and can inform the parameterization of the hardware bundles that actually * implement the protocol. */ case class Edges[EI, EO](in: Seq[EI], out: Seq[EO]) /** A field available in [[Parameters]] used to determine whether [[InwardNodeImp.monitor]] will be called. */ case object MonitorsEnabled extends Field[Boolean](true) /** When rendering the edge in a graphical format, flip the order in which the edges' source and sink are presented. * * For example, when rendering graphML, yEd by default tries to put the source node vertically above the sink node, but * [[RenderFlipped]] inverts this relationship. When a particular [[LazyModule]] contains both source nodes and sink * nodes, flipping the rendering of one node's edge will usual produce a more concise visual layout for the * [[LazyModule]]. */ case object RenderFlipped extends Field[Boolean](false) /** The sealed node class in the package, all node are derived from it. * * @param inner * Sink interface implementation. * @param outer * Source interface implementation. * @param valName * val name of this node. * @tparam DI * Downward-flowing parameters received on the inner side of the node. It is usually a brunch of parameters * describing the protocol parameters from a source. For an [[InwardNode]], it is determined by the connected * [[OutwardNode]]. Since it can be connected to multiple sources, this parameter is always a Seq of source port * parameters. * @tparam UI * Upward-flowing parameters generated by the inner side of the node. It is usually a brunch of parameters describing * the protocol parameters of a sink. For an [[InwardNode]], it is determined itself. * @tparam EI * Edge Parameters describing a connection on the inner side of the node. It is usually a brunch of transfers * specified for a sink according to protocol. * @tparam BI * Bundle type used when connecting to the inner side of the node. It is a hardware interface of this sink interface. * It should extends from [[chisel3.Data]], which represents the real hardware. * @tparam DO * Downward-flowing parameters generated on the outer side of the node. It is usually a brunch of parameters * describing the protocol parameters of a source. For an [[OutwardNode]], it is determined itself. * @tparam UO * Upward-flowing parameters received by the outer side of the node. It is usually a brunch of parameters describing * the protocol parameters from a sink. For an [[OutwardNode]], it is determined by the connected [[InwardNode]]. * Since it can be connected to multiple sinks, this parameter is always a Seq of sink port parameters. * @tparam EO * Edge Parameters describing a connection on the outer side of the node. It is usually a brunch of transfers * specified for a source according to protocol. * @tparam BO * Bundle type used when connecting to the outer side of the node. It is a hardware interface of this source * interface. It should extends from [[chisel3.Data]], which represents the real hardware. * * @note * Call Graph of [[MixedNode]] * - line `─`: source is process by a function and generate pass to others * - Arrow `→`: target of arrow is generated by source * * {{{ * (from the other node) * ┌─────────────────────────────────────────────────────────[[InwardNode.uiParams]]─────────────┐ * ↓ │ * (binding node when elaboration) [[OutwardNode.uoParams]]────────────────────────[[MixedNode.mapParamsU]]→──────────┐ │ * [[InwardNode.accPI]] │ │ │ * │ │ (based on protocol) │ * │ │ [[MixedNode.inner.edgeI]] │ * │ │ ↓ │ * ↓ │ │ │ * (immobilize after elaboration) (inward port from [[OutwardNode]]) │ ↓ │ * [[InwardNode.iBindings]]──┐ [[MixedNode.iDirectPorts]]────────────────────→[[MixedNode.iPorts]] [[InwardNode.uiParams]] │ * │ │ ↑ │ │ │ * │ │ │ [[OutwardNode.doParams]] │ │ * │ │ │ (from the other node) │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * │ │ │ └────────┬──────────────┤ │ * │ │ │ │ │ │ * │ │ │ │ (based on protocol) │ * │ │ │ │ [[MixedNode.inner.edgeI]] │ * │ │ │ │ │ │ * │ │ (from the other node) │ ↓ │ * │ └───[[OutwardNode.oPortMapping]] [[OutwardNode.oStar]] │ [[MixedNode.edgesIn]]───┐ │ * │ ↑ ↑ │ │ ↓ │ * │ │ │ │ │ [[MixedNode.in]] │ * │ │ │ │ ↓ ↑ │ * │ (solve star connection) │ │ │ [[MixedNode.bundleIn]]──┘ │ * ├───[[MixedNode.resolveStar]]→─┼─────────────────────────────┤ └────────────────────────────────────┐ │ * │ │ │ [[MixedNode.bundleOut]]─┐ │ │ * │ │ │ ↑ ↓ │ │ * │ │ │ │ [[MixedNode.out]] │ │ * │ ↓ ↓ │ ↑ │ │ * │ ┌─────[[InwardNode.iPortMapping]] [[InwardNode.iStar]] [[MixedNode.edgesOut]]──┘ │ │ * │ │ (from the other node) ↑ │ │ * │ │ │ │ │ │ * │ │ │ [[MixedNode.outer.edgeO]] │ │ * │ │ │ (based on protocol) │ │ * │ │ │ │ │ │ * │ │ │ ┌────────────────────────────────────────┤ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * (immobilize after elaboration)│ ↓ │ │ │ │ * [[OutwardNode.oBindings]]─┘ [[MixedNode.oDirectPorts]]───→[[MixedNode.oPorts]] [[OutwardNode.doParams]] │ │ * ↑ (inward port from [[OutwardNode]]) │ │ │ │ * │ ┌─────────────────────────────────────────┤ │ │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * [[OutwardNode.accPO]] │ ↓ │ │ │ * (binding node when elaboration) │ [[InwardNode.diParams]]─────→[[MixedNode.mapParamsD]]────────────────────────────┘ │ │ * │ ↑ │ │ * │ └──────────────────────────────────────────────────────────────────────────────────────────┘ │ * └──────────────────────────────────────────────────────────────────────────────────────────────────────────┘ * }}} */ abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data]( val inner: InwardNodeImp[DI, UI, EI, BI], val outer: OutwardNodeImp[DO, UO, EO, BO] )( implicit valName: ValName) extends BaseNode with NodeHandle[DI, UI, EI, BI, DO, UO, EO, BO] with InwardNode[DI, UI, BI] with OutwardNode[DO, UO, BO] { // Generate a [[NodeHandle]] with inward and outward node are both this node. val inward = this val outward = this /** Debug info of nodes binding. */ def bindingInfo: String = s"""$iBindingInfo |$oBindingInfo |""".stripMargin /** Debug info of ports connecting. */ def connectedPortsInfo: String = s"""${oPorts.size} outward ports connected: [${oPorts.map(_._2.name).mkString(",")}] |${iPorts.size} inward ports connected: [${iPorts.map(_._2.name).mkString(",")}] |""".stripMargin /** Debug info of parameters propagations. */ def parametersInfo: String = s"""${doParams.size} downstream outward parameters: [${doParams.mkString(",")}] |${uoParams.size} upstream outward parameters: [${uoParams.mkString(",")}] |${diParams.size} downstream inward parameters: [${diParams.mkString(",")}] |${uiParams.size} upstream inward parameters: [${uiParams.mkString(",")}] |""".stripMargin /** For a given node, converts [[OutwardNode.accPO]] and [[InwardNode.accPI]] to [[MixedNode.oPortMapping]] and * [[MixedNode.iPortMapping]]. * * Given counts of known inward and outward binding and inward and outward star bindings, return the resolved inward * stars and outward stars. * * This method will also validate the arguments and throw a runtime error if the values are unsuitable for this type * of node. * * @param iKnown * Number of known-size ([[BIND_ONCE]]) input bindings. * @param oKnown * Number of known-size ([[BIND_ONCE]]) output bindings. * @param iStar * Number of unknown size ([[BIND_STAR]]) input bindings. * @param oStar * Number of unknown size ([[BIND_STAR]]) output bindings. * @return * A Tuple of the resolved number of input and output connections. */ protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStar: Int, oStar: Int): (Int, Int) /** Function to generate downward-flowing outward params from the downward-flowing input params and the current output * ports. * * @param n * The size of the output sequence to generate. * @param p * Sequence of downward-flowing input parameters of this node. * @return * A `n`-sized sequence of downward-flowing output edge parameters. */ protected[diplomacy] def mapParamsD(n: Int, p: Seq[DI]): Seq[DO] /** Function to generate upward-flowing input parameters from the upward-flowing output parameters [[uiParams]]. * * @param n * Size of the output sequence. * @param p * Upward-flowing output edge parameters. * @return * A n-sized sequence of upward-flowing input edge parameters. */ protected[diplomacy] def mapParamsU(n: Int, p: Seq[UO]): Seq[UI] /** @return * The sink cardinality of the node, the number of outputs bound with [[BIND_QUERY]] summed with inputs bound with * [[BIND_STAR]]. */ protected[diplomacy] lazy val sinkCard: Int = oBindings.count(_._3 == BIND_QUERY) + iBindings.count(_._3 == BIND_STAR) /** @return * The source cardinality of this node, the number of inputs bound with [[BIND_QUERY]] summed with the number of * output bindings bound with [[BIND_STAR]]. */ protected[diplomacy] lazy val sourceCard: Int = iBindings.count(_._3 == BIND_QUERY) + oBindings.count(_._3 == BIND_STAR) /** @return list of nodes involved in flex bindings with this node. */ protected[diplomacy] lazy val flexes: Seq[BaseNode] = oBindings.filter(_._3 == BIND_FLEX).map(_._2) ++ iBindings.filter(_._3 == BIND_FLEX).map(_._2) /** Resolves the flex to be either source or sink and returns the offset where the [[BIND_STAR]] operators begin * greedily taking up the remaining connections. * * @return * A value >= 0 if it is sink cardinality, a negative value for source cardinality. The magnitude of the return * value is not relevant. */ protected[diplomacy] lazy val flexOffset: Int = { /** Recursively performs a depth-first search of the [[flexes]], [[BaseNode]]s connected to this node with flex * operators. The algorithm bottoms out when we either get to a node we have already visited or when we get to a * connection that is not a flex and can set the direction for us. Otherwise, recurse by visiting the `flexes` of * each node in the current set and decide whether they should be added to the set or not. * * @return * the mapping of [[BaseNode]] indexed by their serial numbers. */ def DFS(v: BaseNode, visited: Map[Int, BaseNode]): Map[Int, BaseNode] = { if (visited.contains(v.serial) || !v.flexibleArityDirection) { visited } else { v.flexes.foldLeft(visited + (v.serial -> v))((sum, n) => DFS(n, sum)) } } /** Determine which [[BaseNode]] are involved in resolving the flex connections to/from this node. * * @example * {{{ * a :*=* b :*=* c * d :*=* b * e :*=* f * }}} * * `flexSet` for `a`, `b`, `c`, or `d` will be `Set(a, b, c, d)` `flexSet` for `e` or `f` will be `Set(e,f)` */ val flexSet = DFS(this, Map()).values /** The total number of :*= operators where we're on the left. */ val allSink = flexSet.map(_.sinkCard).sum /** The total number of :=* operators used when we're on the right. */ val allSource = flexSet.map(_.sourceCard).sum require( allSink == 0 || allSource == 0, s"The nodes ${flexSet.map(_.name)} which are inter-connected by :*=* have ${allSink} :*= operators and ${allSource} :=* operators connected to them, making it impossible to determine cardinality inference direction." ) allSink - allSource } /** @return A value >= 0 if it is sink cardinality, a negative value for source cardinality. */ protected[diplomacy] def edgeArityDirection(n: BaseNode): Int = { if (flexibleArityDirection) flexOffset else if (n.flexibleArityDirection) n.flexOffset else 0 } /** For a node which is connected between two nodes, select the one that will influence the direction of the flex * resolution. */ protected[diplomacy] def edgeAritySelect(n: BaseNode, l: => Int, r: => Int): Int = { val dir = edgeArityDirection(n) if (dir < 0) l else if (dir > 0) r else 1 } /** Ensure that the same node is not visited twice in resolving `:*=`, etc operators. */ private var starCycleGuard = false /** Resolve all the star operators into concrete indicies. As connections are being made, some may be "star" * connections which need to be resolved. In some way to determine how many actual edges they correspond to. We also * need to build up the ranges of edges which correspond to each binding operator, so that We can apply the correct * edge parameters and later build up correct bundle connections. * * [[oPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that oPort (binding * operator). [[iPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that iPort * (binding operator). [[oStar]]: `Int` the value to return for this node `N` for any `N :*= foo` or `N :*=* foo :*= * bar` [[iStar]]: `Int` the value to return for this node `N` for any `foo :=* N` or `bar :=* foo :*=* N` */ protected[diplomacy] lazy val ( oPortMapping: Seq[(Int, Int)], iPortMapping: Seq[(Int, Int)], oStar: Int, iStar: Int ) = { try { if (starCycleGuard) throw StarCycleException() starCycleGuard = true // For a given node N... // Number of foo :=* N // + Number of bar :=* foo :*=* N val oStars = oBindings.count { case (_, n, b, _, _) => b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) < 0) } // Number of N :*= foo // + Number of N :*=* foo :*= bar val iStars = iBindings.count { case (_, n, b, _, _) => b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) > 0) } // 1 for foo := N // + bar.iStar for bar :*= foo :*=* N // + foo.iStar for foo :*= N // + 0 for foo :=* N val oKnown = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, 0, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => 0 } }.sum // 1 for N := foo // + bar.oStar for N :*=* foo :=* bar // + foo.oStar for N :=* foo // + 0 for N :*= foo val iKnown = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, 0) case BIND_QUERY => n.oStar case BIND_STAR => 0 } }.sum // Resolve star depends on the node subclass to implement the algorithm for this. val (iStar, oStar) = resolveStar(iKnown, oKnown, iStars, oStars) // Cumulative list of resolved outward binding range starting points val oSum = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, oStar, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => oStar } }.scanLeft(0)(_ + _) // Cumulative list of resolved inward binding range starting points val iSum = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, iStar) case BIND_QUERY => n.oStar case BIND_STAR => iStar } }.scanLeft(0)(_ + _) // Create ranges for each binding based on the running sums and return // those along with resolved values for the star operations. (oSum.init.zip(oSum.tail), iSum.init.zip(iSum.tail), oStar, iStar) } catch { case c: StarCycleException => throw c.copy(loop = context +: c.loop) } } /** Sequence of inward ports. * * This should be called after all star bindings are resolved. * * Each element is: `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. * `n` Instance of inward node. `p` View of [[Parameters]] where this connection was made. `s` Source info where this * connection was made in the source code. */ protected[diplomacy] lazy val oDirectPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oBindings.flatMap { case (i, n, _, p, s) => // for each binding operator in this node, look at what it connects to val (start, end) = n.iPortMapping(i) (start until end).map { j => (j, n, p, s) } } /** Sequence of outward ports. * * This should be called after all star bindings are resolved. * * `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. `n` Instance of * outward node. `p` View of [[Parameters]] where this connection was made. `s` [[SourceInfo]] where this connection * was made in the source code. */ protected[diplomacy] lazy val iDirectPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iBindings.flatMap { case (i, n, _, p, s) => // query this port index range of this node in the other side of node. val (start, end) = n.oPortMapping(i) (start until end).map { j => (j, n, p, s) } } // Ephemeral nodes ( which have non-None iForward/oForward) have in_degree = out_degree // Thus, there must exist an Eulerian path and the below algorithms terminate @scala.annotation.tailrec private def oTrace( tuple: (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) ): (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.iForward(i) match { case None => (i, n, p, s) case Some((j, m)) => oTrace((j, m, p, s)) } } @scala.annotation.tailrec private def iTrace( tuple: (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) ): (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.oForward(i) match { case None => (i, n, p, s) case Some((j, m)) => iTrace((j, m, p, s)) } } /** Final output ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - Numeric index of this binding in the [[InwardNode]] on the other end. * - [[InwardNode]] on the other end of this binding. * - A view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. */ lazy val oPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oDirectPorts.map(oTrace) /** Final input ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - numeric index of this binding in [[OutwardNode]] on the other end. * - [[OutwardNode]] on the other end of this binding. * - a view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. */ lazy val iPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iDirectPorts.map(iTrace) private var oParamsCycleGuard = false protected[diplomacy] lazy val diParams: Seq[DI] = iPorts.map { case (i, n, _, _) => n.doParams(i) } protected[diplomacy] lazy val doParams: Seq[DO] = { try { if (oParamsCycleGuard) throw DownwardCycleException() oParamsCycleGuard = true val o = mapParamsD(oPorts.size, diParams) require( o.size == oPorts.size, s"""Diplomacy has detected a problem with your graph: |At the following node, the number of outward ports should equal the number of produced outward parameters. |$context |$connectedPortsInfo |Downstreamed inward parameters: [${diParams.mkString(",")}] |Produced outward parameters: [${o.mkString(",")}] |""".stripMargin ) o.map(outer.mixO(_, this)) } catch { case c: DownwardCycleException => throw c.copy(loop = context +: c.loop) } } private var iParamsCycleGuard = false protected[diplomacy] lazy val uoParams: Seq[UO] = oPorts.map { case (o, n, _, _) => n.uiParams(o) } protected[diplomacy] lazy val uiParams: Seq[UI] = { try { if (iParamsCycleGuard) throw UpwardCycleException() iParamsCycleGuard = true val i = mapParamsU(iPorts.size, uoParams) require( i.size == iPorts.size, s"""Diplomacy has detected a problem with your graph: |At the following node, the number of inward ports should equal the number of produced inward parameters. |$context |$connectedPortsInfo |Upstreamed outward parameters: [${uoParams.mkString(",")}] |Produced inward parameters: [${i.mkString(",")}] |""".stripMargin ) i.map(inner.mixI(_, this)) } catch { case c: UpwardCycleException => throw c.copy(loop = context +: c.loop) } } /** Outward edge parameters. */ protected[diplomacy] lazy val edgesOut: Seq[EO] = (oPorts.zip(doParams)).map { case ((i, n, p, s), o) => outer.edgeO(o, n.uiParams(i), p, s) } /** Inward edge parameters. */ protected[diplomacy] lazy val edgesIn: Seq[EI] = (iPorts.zip(uiParams)).map { case ((o, n, p, s), i) => inner.edgeI(n.doParams(o), i, p, s) } /** A tuple of the input edge parameters and output edge parameters for the edges bound to this node. * * If you need to access to the edges of a foreign Node, use this method (in/out create bundles). */ lazy val edges: Edges[EI, EO] = Edges(edgesIn, edgesOut) /** Create actual Wires corresponding to the Bundles parameterized by the outward edges of this node. */ protected[diplomacy] lazy val bundleOut: Seq[BO] = edgesOut.map { e => val x = Wire(outer.bundleO(e)).suggestName(s"${valName.value}Out") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } /** Create actual Wires corresponding to the Bundles parameterized by the inward edges of this node. */ protected[diplomacy] lazy val bundleIn: Seq[BI] = edgesIn.map { e => val x = Wire(inner.bundleI(e)).suggestName(s"${valName.value}In") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } private def emptyDanglesOut: Seq[Dangle] = oPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(serial, i), sink = HalfEdge(n.serial, j), flipped = false, name = wirePrefix + "out", dataOpt = None ) } private def emptyDanglesIn: Seq[Dangle] = iPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(n.serial, j), sink = HalfEdge(serial, i), flipped = true, name = wirePrefix + "in", dataOpt = None ) } /** Create the [[Dangle]]s which describe the connections from this node output to other nodes inputs. */ protected[diplomacy] def danglesOut: Seq[Dangle] = emptyDanglesOut.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleOut(i))) } /** Create the [[Dangle]]s which describe the connections from this node input from other nodes outputs. */ protected[diplomacy] def danglesIn: Seq[Dangle] = emptyDanglesIn.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleIn(i))) } private[diplomacy] var instantiated = false /** Gather Bundle and edge parameters of outward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. */ def out: Seq[(BO, EO)] = { require( instantiated, s"$name.out should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleOut.zip(edgesOut) } /** Gather Bundle and edge parameters of inward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. */ def in: Seq[(BI, EI)] = { require( instantiated, s"$name.in should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleIn.zip(edgesIn) } /** Actually instantiate this node during [[LazyModuleImp]] evaluation. Mark that it's safe to use the Bundle wires, * instantiate monitors on all input ports if appropriate, and return all the dangles of this node. */ protected[diplomacy] def instantiate(): Seq[Dangle] = { instantiated = true if (!circuitIdentity) { (iPorts.zip(in)).foreach { case ((_, _, p, _), (b, e)) => if (p(MonitorsEnabled)) inner.monitor(b, e) } } danglesOut ++ danglesIn } protected[diplomacy] def cloneDangles(): Seq[Dangle] = emptyDanglesOut ++ emptyDanglesIn /** Connects the outward part of a node with the inward part of this node. */ protected[diplomacy] def bind( h: OutwardNode[DI, UI, BI], binding: NodeBinding )( implicit p: Parameters, sourceInfo: SourceInfo ): Unit = { val x = this // x := y val y = h sourceLine(sourceInfo, " at ", "") val i = x.iPushed val o = y.oPushed y.oPush( i, x, binding match { case BIND_ONCE => BIND_ONCE case BIND_FLEX => BIND_FLEX case BIND_STAR => BIND_QUERY case BIND_QUERY => BIND_STAR } ) x.iPush(o, y, binding) } /* Metadata for printing the node graph. */ def inputs: Seq[(OutwardNode[DI, UI, BI], RenderedEdge)] = (iPorts.zip(edgesIn)).map { case ((_, n, p, _), e) => val re = inner.render(e) (n, re.copy(flipped = re.flipped != p(RenderFlipped))) } /** Metadata for printing the node graph */ def outputs: Seq[(InwardNode[DO, UO, BO], RenderedEdge)] = oPorts.map { case (i, n, _, _) => (n, n.inputs(i)._2) } } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) || !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.ProbeAckData || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode | small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U || beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }

module TLError( // @[Error.scala:21:9] input clock, // @[Error.scala:21:9] input reset, // @[Error.scala:21:9] output auto_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [7:0] auto_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [13:0] auto_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [3:0] auto_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [7:0] auto_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_corrupt // @[LazyModuleImp.scala:107:25] ); wire _a_q_io_deq_valid; // @[Decoupled.scala:362:21] wire [2:0] _a_q_io_deq_bits_opcode; // @[Decoupled.scala:362:21] wire [3:0] _a_q_io_deq_bits_size; // @[Decoupled.scala:362:21] wire auto_in_a_valid_0 = auto_in_a_valid; // @[Error.scala:21:9] wire [2:0] auto_in_a_bits_opcode_0 = auto_in_a_bits_opcode; // @[Error.scala:21:9] wire [2:0] auto_in_a_bits_param_0 = auto_in_a_bits_param; // @[Error.scala:21:9] wire [3:0] auto_in_a_bits_size_0 = auto_in_a_bits_size; // @[Error.scala:21:9] wire [7:0] auto_in_a_bits_source_0 = auto_in_a_bits_source; // @[Error.scala:21:9] wire [13:0] auto_in_a_bits_address_0 = auto_in_a_bits_address; // @[Error.scala:21:9] wire [7:0] auto_in_a_bits_mask_0 = auto_in_a_bits_mask; // @[Error.scala:21:9] wire [63:0] auto_in_a_bits_data_0 = auto_in_a_bits_data; // @[Error.scala:21:9] wire auto_in_a_bits_corrupt_0 = auto_in_a_bits_corrupt; // @[Error.scala:21:9] wire auto_in_d_ready_0 = auto_in_d_ready; // @[Error.scala:21:9] wire [7:0][2:0] _GEN = '{3'h4, 3'h4, 3'h2, 3'h1, 3'h1, 3'h1, 3'h0, 3'h0}; wire auto_in_d_bits_denied = 1'h1; // @[Error.scala:21:9] wire nodeIn_d_bits_denied = 1'h1; // @[MixedNode.scala:551:17] wire da_bits_denied = 1'h1; // @[Error.scala:28:18] wire [1:0] auto_in_d_bits_param = 2'h0; // @[Error.scala:21:9] wire [1:0] nodeIn_d_bits_param = 2'h0; // @[MixedNode.scala:551:17] wire [1:0] da_bits_param = 2'h0; // @[Error.scala:28:18] wire auto_in_d_bits_sink = 1'h0; // @[Error.scala:21:9] wire nodeIn_d_bits_sink = 1'h0; // @[MixedNode.scala:551:17] wire da_bits_sink = 1'h0; // @[Error.scala:28:18] wire [63:0] auto_in_d_bits_data = 64'h0; // @[Error.scala:21:9] wire [63:0] nodeIn_d_bits_data = 64'h0; // @[MixedNode.scala:551:17] wire [63:0] da_bits_data = 64'h0; // @[Error.scala:28:18] wire [2:0] _da_bits_opcode_WIRE_6 = 3'h4; // @[Bundles.scala:47:27] wire [2:0] _da_bits_opcode_WIRE_7 = 3'h4; // @[Bundles.scala:47:27] wire [2:0] _da_bits_opcode_WIRE_5 = 3'h2; // @[Bundles.scala:47:27] wire [2:0] _da_bits_opcode_WIRE_2 = 3'h1; // @[Bundles.scala:47:27] wire [2:0] _da_bits_opcode_WIRE_3 = 3'h1; // @[Bundles.scala:47:27] wire [2:0] _da_bits_opcode_WIRE_4 = 3'h1; // @[Bundles.scala:47:27] wire [2:0] _da_bits_opcode_WIRE_0 = 3'h0; // @[Bundles.scala:47:27] wire [2:0] _da_bits_opcode_WIRE_1 = 3'h0; // @[Bundles.scala:47:27] wire nodeIn_a_ready; // @[MixedNode.scala:551:17] wire nodeIn_a_valid = auto_in_a_valid_0; // @[Error.scala:21:9] wire [2:0] nodeIn_a_bits_opcode = auto_in_a_bits_opcode_0; // @[Error.scala:21:9] wire [2:0] nodeIn_a_bits_param = auto_in_a_bits_param_0; // @[Error.scala:21:9] wire [3:0] nodeIn_a_bits_size = auto_in_a_bits_size_0; // @[Error.scala:21:9] wire [7:0] nodeIn_a_bits_source = auto_in_a_bits_source_0; // @[Error.scala:21:9] wire [13:0] nodeIn_a_bits_address = auto_in_a_bits_address_0; // @[Error.scala:21:9] wire [7:0] nodeIn_a_bits_mask = auto_in_a_bits_mask_0; // @[Error.scala:21:9] wire [63:0] nodeIn_a_bits_data = auto_in_a_bits_data_0; // @[Error.scala:21:9] wire nodeIn_a_bits_corrupt = auto_in_a_bits_corrupt_0; // @[Error.scala:21:9] wire nodeIn_d_ready = auto_in_d_ready_0; // @[Error.scala:21:9] wire nodeIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [3:0] nodeIn_d_bits_size; // @[MixedNode.scala:551:17] wire [7:0] nodeIn_d_bits_source; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_corrupt; // @[MixedNode.scala:551:17] wire auto_in_a_ready_0; // @[Error.scala:21:9] wire [2:0] auto_in_d_bits_opcode_0; // @[Error.scala:21:9] wire [3:0] auto_in_d_bits_size_0; // @[Error.scala:21:9] wire [7:0] auto_in_d_bits_source_0; // @[Error.scala:21:9] wire auto_in_d_bits_corrupt_0; // @[Error.scala:21:9] wire auto_in_d_valid_0; // @[Error.scala:21:9] assign auto_in_a_ready_0 = nodeIn_a_ready; // @[Error.scala:21:9] wire da_ready = nodeIn_d_ready; // @[Error.scala:28:18] wire da_valid; // @[Error.scala:28:18] assign auto_in_d_valid_0 = nodeIn_d_valid; // @[Error.scala:21:9] wire [2:0] da_bits_opcode; // @[Error.scala:28:18] assign auto_in_d_bits_opcode_0 = nodeIn_d_bits_opcode; // @[Error.scala:21:9] wire [3:0] da_bits_size; // @[Error.scala:28:18] assign auto_in_d_bits_size_0 = nodeIn_d_bits_size; // @[Error.scala:21:9] wire [7:0] da_bits_source; // @[Error.scala:28:18] assign auto_in_d_bits_source_0 = nodeIn_d_bits_source; // @[Error.scala:21:9] wire da_bits_corrupt; // @[Error.scala:28:18] assign auto_in_d_bits_corrupt_0 = nodeIn_d_bits_corrupt; // @[Error.scala:21:9] wire _da_valid_T_1; // @[Error.scala:36:35] assign nodeIn_d_valid = da_valid; // @[Error.scala:28:18] assign nodeIn_d_bits_opcode = da_bits_opcode; // @[Error.scala:28:18] assign nodeIn_d_bits_size = da_bits_size; // @[Error.scala:28:18] assign nodeIn_d_bits_source = da_bits_source; // @[Error.scala:28:18] wire da_bits_corrupt_opdata; // @[Edges.scala:106:36] assign nodeIn_d_bits_corrupt = da_bits_corrupt; // @[Error.scala:28:18] wire _q_io_deq_ready_T_3; // @[Error.scala:35:46] wire _a_last_T = _q_io_deq_ready_T_3 & _a_q_io_deq_valid; // @[Decoupled.scala:51:35, :362:21] wire [26:0] _a_last_beats1_decode_T = 27'hFFF << _a_q_io_deq_bits_size; // @[Decoupled.scala:362:21] wire [11:0] _a_last_beats1_decode_T_1 = _a_last_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_last_beats1_decode_T_2 = ~_a_last_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] a_last_beats1_decode = _a_last_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire _a_last_beats1_opdata_T = _a_q_io_deq_bits_opcode[2]; // @[Decoupled.scala:362:21] wire a_last_beats1_opdata = ~_a_last_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [8:0] a_last_beats1 = a_last_beats1_opdata ? a_last_beats1_decode : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [8:0] a_last_counter; // @[Edges.scala:229:27] wire [9:0] _a_last_counter1_T = {1'h0, a_last_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] a_last_counter1 = _a_last_counter1_T[8:0]; // @[Edges.scala:230:28] wire a_last_first = a_last_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _a_last_last_T = a_last_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _a_last_last_T_1 = a_last_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire a_last = _a_last_last_T | _a_last_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_last_done = a_last & _a_last_T; // @[Decoupled.scala:51:35] wire [8:0] _a_last_count_T = ~a_last_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] a_last_count = a_last_beats1 & _a_last_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _a_last_counter_T = a_last_first ? a_last_beats1 : a_last_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire _T = da_ready & da_valid; // @[Decoupled.scala:51:35] wire [26:0] _r_beats1_decode_T = 27'hFFF << da_bits_size; // @[package.scala:243:71] wire [11:0] _r_beats1_decode_T_1 = _r_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _r_beats1_decode_T_2 = ~_r_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] r_beats1_decode = _r_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire r_beats1_opdata = da_bits_opcode[0]; // @[Edges.scala:106:36] assign da_bits_corrupt_opdata = da_bits_opcode[0]; // @[Edges.scala:106:36] wire [8:0] r_beats1 = r_beats1_opdata ? r_beats1_decode : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] r_counter; // @[Edges.scala:229:27] wire [9:0] _r_counter1_T = {1'h0, r_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] r_counter1 = _r_counter1_T[8:0]; // @[Edges.scala:230:28] wire da_first = r_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _r_last_T = r_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _r_last_T_1 = r_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire da_last = _r_last_T | _r_last_T_1; // @[Edges.scala:232:{25,33,43}] wire r_3 = da_last & _T; // @[Decoupled.scala:51:35] wire [8:0] _r_count_T = ~r_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] r_4 = r_beats1 & _r_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _r_counter_T = da_first ? r_beats1 : r_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire _q_io_deq_ready_T = da_ready & da_last; // @[Edges.scala:232:33] wire _q_io_deq_ready_T_1 = _q_io_deq_ready_T; // @[Error.scala:35:{26,37}] wire _q_io_deq_ready_T_2 = ~a_last; // @[Edges.scala:232:33] assign _q_io_deq_ready_T_3 = _q_io_deq_ready_T_1 | _q_io_deq_ready_T_2; // @[Error.scala:35:{37,46,49}] wire _da_valid_T = _a_q_io_deq_valid & a_last; // @[Decoupled.scala:362:21] assign _da_valid_T_1 = _da_valid_T; // @[Error.scala:36:{25,35}] assign da_valid = _da_valid_T_1; // @[Error.scala:28:18, :36:35] assign da_bits_opcode = _GEN[_a_q_io_deq_bits_opcode]; // @[Decoupled.scala:362:21] assign da_bits_corrupt = da_bits_corrupt_opdata; // @[Edges.scala:106:36] always @(posedge clock) begin // @[Error.scala:21:9] if (reset) begin // @[Error.scala:21:9] a_last_counter <= 9'h0; // @[Edges.scala:229:27] r_counter <= 9'h0; // @[Edges.scala:229:27] end else begin // @[Error.scala:21:9] if (_a_last_T) // @[Decoupled.scala:51:35] a_last_counter <= _a_last_counter_T; // @[Edges.scala:229:27, :236:21] if (_T) // @[Decoupled.scala:51:35] r_counter <= _r_counter_T; // @[Edges.scala:229:27, :236:21] end always @(posedge) TLMonitor_27 monitor ( // @[Nodes.scala:27:25] .clock (clock), .reset (reset), .io_in_a_ready (nodeIn_a_ready), // @[MixedNode.scala:551:17] .io_in_a_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17] .io_in_a_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17] .io_in_a_bits_param (nodeIn_a_bits_param), // @[MixedNode.scala:551:17] .io_in_a_bits_size (nodeIn_a_bits_size), // @[MixedNode.scala:551:17] .io_in_a_bits_source (nodeIn_a_bits_source), // @[MixedNode.scala:551:17] .io_in_a_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17] .io_in_a_bits_mask (nodeIn_a_bits_mask), // @[MixedNode.scala:551:17] .io_in_a_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17] .io_in_a_bits_corrupt (nodeIn_a_bits_corrupt), // @[MixedNode.scala:551:17] .io_in_d_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17] .io_in_d_valid (nodeIn_d_valid), // @[MixedNode.scala:551:17] .io_in_d_bits_opcode (nodeIn_d_bits_opcode), // @[MixedNode.scala:551:17] .io_in_d_bits_size (nodeIn_d_bits_size), // @[MixedNode.scala:551:17] .io_in_d_bits_source (nodeIn_d_bits_source), // @[MixedNode.scala:551:17] .io_in_d_bits_corrupt (nodeIn_d_bits_corrupt) // @[MixedNode.scala:551:17] ); // @[Nodes.scala:27:25] Queue1_TLBundleA_a14d64s8k1z4u a_q ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (nodeIn_a_ready), .io_enq_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17] .io_enq_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17] .io_enq_bits_param (nodeIn_a_bits_param), // @[MixedNode.scala:551:17] .io_enq_bits_size (nodeIn_a_bits_size), // @[MixedNode.scala:551:17] .io_enq_bits_source (nodeIn_a_bits_source), // @[MixedNode.scala:551:17] .io_enq_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17] .io_enq_bits_mask (nodeIn_a_bits_mask), // @[MixedNode.scala:551:17] .io_enq_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17] .io_enq_bits_corrupt (nodeIn_a_bits_corrupt), // @[MixedNode.scala:551:17] .io_deq_ready (_q_io_deq_ready_T_3), // @[Error.scala:35:46] .io_deq_valid (_a_q_io_deq_valid), .io_deq_bits_opcode (_a_q_io_deq_bits_opcode), .io_deq_bits_size (_a_q_io_deq_bits_size), .io_deq_bits_source (da_bits_source) ); // @[Decoupled.scala:362:21] assign da_bits_size = _a_q_io_deq_bits_size; // @[Decoupled.scala:362:21] assign auto_in_a_ready = auto_in_a_ready_0; // @[Error.scala:21:9] assign auto_in_d_valid = auto_in_d_valid_0; // @[Error.scala:21:9] assign auto_in_d_bits_opcode = auto_in_d_bits_opcode_0; // @[Error.scala:21:9] assign auto_in_d_bits_size = auto_in_d_bits_size_0; // @[Error.scala:21:9] assign auto_in_d_bits_source = auto_in_d_bits_source_0; // @[Error.scala:21:9] assign auto_in_d_bits_corrupt = auto_in_d_bits_corrupt_0; // @[Error.scala:21:9] endmodule

Generate the Verilog code corresponding to the following Chisel files. File Monitor.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceLine import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import freechips.rocketchip.diplomacy.EnableMonitors import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode} import freechips.rocketchip.util.PlusArg case class TLMonitorArgs(edge: TLEdge) abstract class TLMonitorBase(args: TLMonitorArgs) extends Module { val io = IO(new Bundle { val in = Input(new TLBundle(args.edge.bundle)) }) def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit legalize(io.in, args.edge, reset) } object TLMonitor { def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = { if (enable) { EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) } } else { node } } } class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args) { require (args.edge.params(TLMonitorStrictMode) || (! args.edge.params(TestplanTestType).formal)) val cover_prop_class = PropertyClass.Default //Like assert but can flip to being an assumption for formal verification def monAssert(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir, cond, message, PropertyClass.Default) } def assume(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir.flip, cond, message, PropertyClass.Default) } def extra = { args.edge.sourceInfo match { case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)" case _ => "" } } def visible(address: UInt, source: UInt, edge: TLEdge) = edge.client.clients.map { c => !c.sourceId.contains(source) || c.visibility.map(_.contains(address)).reduce(_ || _) }.reduce(_ && _) def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = { //switch this flag to turn on diplomacy in error messages def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n" monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra) // Reuse these subexpressions to save some firrtl lines val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility") //The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B //TODO: check for acquireT? when (bundle.opcode === TLMessages.AcquireBlock) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra) } when (bundle.opcode === TLMessages.AcquirePerm) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra) monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra) monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra) monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra) } } def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = { monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra) monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility") // Reuse these subexpressions to save some firrtl lines val address_ok = edge.manager.containsSafe(edge.address(bundle)) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source when (bundle.opcode === TLMessages.Probe) { assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra) assume (address_ok, "'B' channel Probe carries unmanaged address" + extra) assume (legal_source, "'B' channel Probe carries source that is not first source" + extra) assume (is_aligned, "'B' channel Probe address not aligned to size" + extra) assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra) assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra) assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra) monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra) monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra) monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra) monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra) } } def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = { monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val address_ok = edge.manager.containsSafe(edge.address(bundle)) monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility") when (bundle.opcode === TLMessages.ProbeAck) { monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra) } when (bundle.opcode === TLMessages.ProbeAckData) { monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.Release) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra) monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra) } when (bundle.opcode === TLMessages.ReleaseData) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.AccessAck) { monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra) } when (bundle.opcode === TLMessages.HintAck) { monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra) } } def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = { assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val sink_ok = bundle.sink < edge.manager.endSinkId.U val deny_put_ok = edge.manager.mayDenyPut.B val deny_get_ok = edge.manager.mayDenyGet.B when (bundle.opcode === TLMessages.ReleaseAck) { assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra) assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra) assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra) } when (bundle.opcode === TLMessages.Grant) { assume (source_ok, "'D' channel Grant carries invalid source ID" + extra) assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra) assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel Grant is denied" + extra) } when (bundle.opcode === TLMessages.GrantData) { assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra) assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra) assume (!bundle.denied || bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra) assume (deny_get_ok || !bundle.denied, "'D' channel GrantData is denied" + extra) } when (bundle.opcode === TLMessages.AccessAck) { assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel AccessAck is denied" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra) assume (!bundle.denied || bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra) assume (deny_get_ok || !bundle.denied, "'D' channel AccessAckData is denied" + extra) } when (bundle.opcode === TLMessages.HintAck) { assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel HintAck is denied" + extra) } } def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = { val sink_ok = bundle.sink < edge.manager.endSinkId.U monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra) } def legalizeFormat(bundle: TLBundle, edge: TLEdge) = { when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) } when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) } when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) } when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) } } else { monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra) monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra) monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra) } } def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = { val a_first = edge.first(a.bits, a.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (a.valid && !a_first) { monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra) monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra) monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra) monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra) monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra) } when (a.fire && a_first) { opcode := a.bits.opcode param := a.bits.param size := a.bits.size source := a.bits.source address := a.bits.address } } def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = { val b_first = edge.first(b.bits, b.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (b.valid && !b_first) { monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra) monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra) monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra) monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra) monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra) } when (b.fire && b_first) { opcode := b.bits.opcode param := b.bits.param size := b.bits.size source := b.bits.source address := b.bits.address } } def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = { // Symbolic variable val sym_source = Wire(UInt(edge.client.endSourceId.W)) // TODO: Connect sym_source to a fixed value for simulation and to a // free wire in formal sym_source := 0.U // Type casting Int to UInt val maxSourceId = Wire(UInt(edge.client.endSourceId.W)) maxSourceId := edge.client.endSourceId.U // Delayed verison of sym_source val sym_source_d = Reg(UInt(edge.client.endSourceId.W)) sym_source_d := sym_source // These will be constraints for FV setup Property( MonitorDirection.Monitor, (sym_source === sym_source_d), "sym_source should remain stable", PropertyClass.Default) Property( MonitorDirection.Monitor, (sym_source <= maxSourceId), "sym_source should take legal value", PropertyClass.Default) val my_resp_pend = RegInit(false.B) val my_opcode = Reg(UInt()) val my_size = Reg(UInt()) val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire) val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire) val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source) val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source) val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat) val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend) when (my_set_resp_pend) { my_resp_pend := true.B } .elsewhen (my_clr_resp_pend) { my_resp_pend := false.B } when (my_a_first_beat) { my_opcode := bundle.a.bits.opcode my_size := bundle.a.bits.size } val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size) val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode) val my_resp_opcode_legal = Wire(Bool()) when ((my_resp_opcode === TLMessages.Get) || (my_resp_opcode === TLMessages.ArithmeticData) || (my_resp_opcode === TLMessages.LogicalData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData) } .elsewhen ((my_resp_opcode === TLMessages.PutFullData) || (my_resp_opcode === TLMessages.PutPartialData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck) } .otherwise { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck) } monAssert (IfThen(my_resp_pend, !my_a_first_beat), "Request message should not be sent with a source ID, for which a response message" + "is already pending (not received until current cycle) for a prior request message" + "with the same source ID" + extra) assume (IfThen(my_clr_resp_pend, (my_set_resp_pend || my_resp_pend)), "Response message should be accepted with a source ID only if a request message with the" + "same source ID has been accepted or is being accepted in the current cycle" + extra) assume (IfThen(my_d_first_beat, (my_a_first_beat || my_resp_pend)), "Response message should be sent with a source ID only if a request message with the" + "same source ID has been accepted or is being sent in the current cycle" + extra) assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)), "If d_valid is 1, then d_size should be same as a_size of the corresponding request" + "message" + extra) assume (IfThen(my_d_first_beat, my_resp_opcode_legal), "If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" + "request message" + extra) } def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = { val c_first = edge.first(c.bits, c.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (c.valid && !c_first) { monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra) monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra) monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra) monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra) monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra) } when (c.fire && c_first) { opcode := c.bits.opcode param := c.bits.param size := c.bits.size source := c.bits.source address := c.bits.address } } def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = { val d_first = edge.first(d.bits, d.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val sink = Reg(UInt()) val denied = Reg(Bool()) when (d.valid && !d_first) { assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra) assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra) assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra) assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra) assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra) assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra) } when (d.fire && d_first) { opcode := d.bits.opcode param := d.bits.param size := d.bits.size source := d.bits.source sink := d.bits.sink denied := d.bits.denied } } def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = { legalizeMultibeatA(bundle.a, edge) legalizeMultibeatD(bundle.d, edge) if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { legalizeMultibeatB(bundle.b, edge) legalizeMultibeatC(bundle.c, edge) } } //This is left in for almond which doesn't adhere to the tilelink protocol @deprecated("Use legalizeADSource instead if possible","") def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.client.endSourceId.W)) val a_first = edge.first(bundle.a.bits, bundle.a.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val a_set = WireInit(0.U(edge.client.endSourceId.W)) when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) assume((a_set | inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra) } if (edge.manager.minLatency > 0) { assume(a_set =/= d_clr || !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight | a_set) & ~d_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") assert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = { val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size) val log_a_size_bus_size = log2Ceil(a_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error inflight.suggestName("inflight") val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) inflight_opcodes.suggestName("inflight_opcodes") val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) inflight_sizes.suggestName("inflight_sizes") val a_first = edge.first(bundle.a.bits, bundle.a.fire) a_first.suggestName("a_first") val d_first = edge.first(bundle.d.bits, bundle.d.fire) d_first.suggestName("d_first") val a_set = WireInit(0.U(edge.client.endSourceId.W)) val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) a_set.suggestName("a_set") a_set_wo_ready.suggestName("a_set_wo_ready") val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) a_opcodes_set.suggestName("a_opcodes_set") val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) a_sizes_set.suggestName("a_sizes_set") val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W)) a_opcode_lookup.suggestName("a_opcode_lookup") a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W)) a_size_lookup.suggestName("a_size_lookup") a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant)) val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant)) val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W)) a_opcodes_set_interm.suggestName("a_opcodes_set_interm") val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W)) a_sizes_set_interm.suggestName("a_sizes_set_interm") when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) { a_set_wo_ready := UIntToOH(bundle.a.bits.source) } when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) | 1.U a_sizes_set_interm := (bundle.a.bits.size << 1.U) | 1.U a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U) a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U) monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) d_opcodes_clr.suggestName("d_opcodes_clr") val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) || (bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra) assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) || (bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra) assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) { assume((!bundle.d.ready) || bundle.a.ready, "ready check") } if (edge.manager.minLatency > 0) { assume(a_set_wo_ready =/= d_clr_wo_ready || !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight | a_set) & ~d_clr inflight_opcodes := (inflight_opcodes | a_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes | a_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = { val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size) val log_c_size_bus_size = log2Ceil(c_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) inflight.suggestName("inflight") inflight_opcodes.suggestName("inflight_opcodes") inflight_sizes.suggestName("inflight_sizes") val c_first = edge.first(bundle.c.bits, bundle.c.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) c_first.suggestName("c_first") d_first.suggestName("d_first") val c_set = WireInit(0.U(edge.client.endSourceId.W)) val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) c_set.suggestName("c_set") c_set_wo_ready.suggestName("c_set_wo_ready") c_opcodes_set.suggestName("c_opcodes_set") c_sizes_set.suggestName("c_sizes_set") val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W)) val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W)) c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U c_opcode_lookup.suggestName("c_opcode_lookup") c_size_lookup.suggestName("c_size_lookup") val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W)) val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W)) c_opcodes_set_interm.suggestName("c_opcodes_set_interm") c_sizes_set_interm.suggestName("c_sizes_set_interm") when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) { c_set_wo_ready := UIntToOH(bundle.c.bits.source) } when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) { c_set := UIntToOH(bundle.c.bits.source) c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) | 1.U c_sizes_set_interm := (bundle.c.bits.size << 1.U) | 1.U c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U) c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U) monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra) } val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck || bundle.c.bits.opcode === TLMessages.ProbeAckData val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") d_opcodes_clr.suggestName("d_opcodes_clr") d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) { assume((!bundle.d.ready) || bundle.c.ready, "ready check") } if (edge.manager.minLatency > 0) { when (c_set_wo_ready.orR) { assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra) } } inflight := (inflight | c_set) & ~d_clr inflight_opcodes := (inflight_opcodes | c_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes | c_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.c.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.manager.endSinkId.W)) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val e_first = true.B val d_set = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) { d_set := UIntToOH(bundle.d.bits.sink) assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra) } val e_clr = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) { e_clr := UIntToOH(bundle.e.bits.sink) monAssert((d_set | inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra) } // edge.client.minLatency applies to BC, not DE inflight := (inflight | d_set) & ~e_clr } def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = { val sourceBits = log2Ceil(edge.client.endSourceId) val tooBig = 14 // >16kB worth of flight information gets to be too much if (sourceBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked") } else { if (args.edge.params(TestplanTestType).simulation) { if (args.edge.params(TLMonitorStrictMode)) { legalizeADSource(bundle, edge) legalizeCDSource(bundle, edge) } else { legalizeADSourceOld(bundle, edge) } } if (args.edge.params(TestplanTestType).formal) { legalizeADSourceFormal(bundle, edge) } } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { // legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize... val sinkBits = log2Ceil(edge.manager.endSinkId) if (sinkBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked") } else { legalizeDESink(bundle, edge) } } } def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = { legalizeFormat (bundle, edge) legalizeMultibeat (bundle, edge) legalizeUnique (bundle, edge) } } File PlusArg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.experimental._ import chisel3.util.HasBlackBoxResource @deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05") case class PlusArgInfo(default: BigInt, docstring: String) /** Case class for PlusArg information * * @tparam A scala type of the PlusArg value * @param default optional default value * @param docstring text to include in the help * @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT) */ private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String) /** Typeclass for converting a type to a doctype string * @tparam A some type */ trait Doctypeable[A] { /** Return the doctype string for some option */ def toDoctype(a: Option[A]): String } /** Object containing implementations of the Doctypeable typeclass */ object Doctypes { /** Converts an Int => "INT" */ implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" } /** Converts a BigInt => "INT" */ implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" } /** Converts a String => "STRING" */ implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" } } class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map( "FORMAT" -> StringParam(format), "DEFAULT" -> IntParam(default), "WIDTH" -> IntParam(width) )) with HasBlackBoxResource { val io = IO(new Bundle { val out = Output(UInt(width.W)) }) addResource("/vsrc/plusarg_reader.v") } /* This wrapper class has no outputs, making it clear it is a simulation-only construct */ class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module { val io = IO(new Bundle { val count = Input(UInt(width.W)) }) val max = Module(new plusarg_reader(format, default, docstring, width)).io.out when (max > 0.U) { assert (io.count < max, s"Timeout exceeded: $docstring") } } import Doctypes._ object PlusArg { /** PlusArg("foo") will return 42.U if the simulation is run with +foo=42 * Do not use this as an initial register value. The value is set in an * initial block and thus accessing it from another initial is racey. * Add a docstring to document the arg, which can be dumped in an elaboration * pass. */ def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out } /** PlusArg.timeout(name, default, docstring)(count) will use chisel.assert * to kill the simulation when count exceeds the specified integer argument. * Default 0 will never assert. */ def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count } } object PlusArgArtefacts { private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty /* Add a new PlusArg */ @deprecated( "Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05" ) def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring) /** Add a new PlusArg * * @tparam A scala type of the PlusArg value * @param name name for the PlusArg * @param default optional default value * @param docstring text to include in the help */ def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit = artefacts = artefacts ++ Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default))) /* From plus args, generate help text */ private def serializeHelp_cHeader(tab: String = ""): String = artefacts .map{ case(arg, info) => s"""|$tab+$arg=${info.doctype}\\n\\ |$tab${" "*20}${info.docstring}\\n\\ |""".stripMargin ++ info.default.map{ case default => s"$tab${" "*22}(default=${default})\\n\\\n"}.getOrElse("") }.toSeq.mkString("\\n\\\n") ++ "\"" /* From plus args, generate a char array of their names */ private def serializeArray_cHeader(tab: String = ""): String = { val prettyTab = tab + " " * 44 // Length of 'static const ...' s"${tab}static const char * verilog_plusargs [] = {\\\n" ++ artefacts .map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" } .mkString("")++ s"${prettyTab}0};" } /* Generate C code to be included in emulator.cc that helps with * argument parsing based on available Verilog PlusArgs */ def serialize_cHeader(): String = s"""|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\ |${serializeHelp_cHeader(" "*7)} |${serializeArray_cHeader()} |""".stripMargin } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) || !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.ProbeAckData || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode | small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U || beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }

module TLMonitor_44( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [8:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire a_first_done = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala:51:35] reg a_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [8:0] address; // @[Monitor.scala:391:22] reg d_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [1:0] size_1; // @[Monitor.scala:540:22] reg sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] reg [1:0] inflight; // @[Monitor.scala:614:27] reg [3:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [3:0] inflight_sizes; // @[Monitor.scala:618:33] reg a_first_counter_1; // @[Edges.scala:229:27] reg d_first_counter_1; // @[Edges.scala:229:27] wire a_set = a_first_done & ~a_first_counter_1; // @[Decoupled.scala:51:35] wire d_release_ack = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala:673:46] wire _GEN = io_in_d_bits_opcode != 3'h6; // @[Monitor.scala:673:46, :674:74] reg [31:0] watchdog; // @[Monitor.scala:709:27] reg [1:0] inflight_1; // @[Monitor.scala:726:35] reg [3:0] inflight_sizes_1; // @[Monitor.scala:728:35] reg d_first_counter_2; // @[Edges.scala:229:27] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]

Generate the Verilog code corresponding to the following Chisel files. File ShiftReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ // Similar to the Chisel ShiftRegister but allows the user to suggest a // name to the registers that get instantiated, and // to provide a reset value. object ShiftRegInit { def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T = (0 until n).foldRight(in) { case (i, next) => { val r = RegNext(next, init) name.foreach { na => r.suggestName(s"${na}_${i}") } r } } } /** These wrap behavioral * shift registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * The different types vary in their reset behavior: * AsyncResetShiftReg -- Asynchronously reset register array * A W(width) x D(depth) sized array is constructed from D instantiations of a * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg, * but only used for timing applications */ abstract class AbstractPipelineReg(w: Int = 1) extends Module { val io = IO(new Bundle { val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) } ) } object AbstractPipelineReg { def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = { val chain = Module(gen) name.foreach{ chain.suggestName(_) } chain.io.d := in.asUInt chain.io.q.asTypeOf(in) } } class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) { require(depth > 0, "Depth must be greater than 0.") override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}" val chain = List.tabulate(depth) { i => Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}") } chain.last.io.d := io.d chain.last.io.en := true.B (chain.init zip chain.tail).foreach { case (sink, source) => sink.io.d := source.io.q sink.io.en := true.B } io.q := chain.head.io.q } object AsyncResetShiftReg { def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name) def apply [T <: Data](in: T, depth: Int, name: Option[String]): T = apply(in, depth, 0, name) def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T = apply(in, depth, init.litValue.toInt, name) def apply [T <: Data](in: T, depth: Int, init: T): T = apply (in, depth, init.litValue.toInt, None) } File SynchronizerReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util.{RegEnable, Cat} /** These wrap behavioral * shift and next registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * * These are built up of *ResetSynchronizerPrimitiveShiftReg, * intended to be replaced by the integrator's metastable flops chains or replaced * at this level if they have a multi-bit wide synchronizer primitive. * The different types vary in their reset behavior: * NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin * AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep * 1-bit-wide shift registers. * SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg * * [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference. * * ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross * Clock Domains. */ object SynchronizerResetType extends Enumeration { val NonSync, Inferred, Sync, Async = Value } // Note: this should not be used directly. // Use the companion object to generate this with the correct reset type mixin. private class SynchronizerPrimitiveShiftReg( sync: Int, init: Boolean, resetType: SynchronizerResetType.Value) extends AbstractPipelineReg(1) { val initInt = if (init) 1 else 0 val initPostfix = resetType match { case SynchronizerResetType.NonSync => "" case _ => s"_i${initInt}" } override def desiredName = s"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}" val chain = List.tabulate(sync) { i => val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B) reg.suggestName(s"sync_$i") } chain.last := io.d.asBool (chain.init zip chain.tail).foreach { case (sink, source) => sink := source } io.q := chain.head.asUInt } private object SynchronizerPrimitiveShiftReg { def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = { val gen: () => SynchronizerPrimitiveShiftReg = resetType match { case SynchronizerResetType.NonSync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) case SynchronizerResetType.Async => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset case SynchronizerResetType.Sync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset case SynchronizerResetType.Inferred => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) } AbstractPipelineReg(gen(), in) } } // Note: This module may end up with a non-AsyncReset type reset. // But the Primitives within will always have AsyncReset type. class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asAsyncReset){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async) } } io.q := Cat(output.reverse) } object AsyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } // Note: This module may end up with a non-Bool type reset. // But the Primitives within will always have Bool reset type. @deprecated("SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.", "rocket-chip 1.2") class SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asBool){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync) } } io.q := Cat(output.reverse) } object SyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred) } io.q := Cat(output.reverse) } object ResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}" val output = Seq.tabulate(w) { i => SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync) } io.q := Cat(output.reverse) } object SynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, None) def apply [T <: Data](in: T): T = apply (in, 3, None) } class ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module { override def desiredName = s"ClockCrossingReg_w${w}" val io = IO(new Bundle{ val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) val en = Input(Bool()) }) val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en) io.q := cdc_reg } object ClockCrossingReg { def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = { val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit)) name.foreach{ cdc_reg.suggestName(_) } cdc_reg.io.d := in.asUInt cdc_reg.io.en := en cdc_reg.io.q.asTypeOf(in) } }

module AsyncResetSynchronizerShiftReg_w1_d3_i0_239( // @[SynchronizerReg.scala:80:7] input clock, // @[SynchronizerReg.scala:80:7] input reset, // @[SynchronizerReg.scala:80:7] input io_d, // @[ShiftReg.scala:36:14] output io_q // @[ShiftReg.scala:36:14] ); wire io_d_0 = io_d; // @[SynchronizerReg.scala:80:7] wire _output_T = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_1 = io_d_0; // @[SynchronizerReg.scala:80:7, :87:41] wire output_0; // @[ShiftReg.scala:48:24] wire io_q_0; // @[SynchronizerReg.scala:80:7] assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_439 output_chain ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_1), // @[SynchronizerReg.scala:87:41] .io_q (output_0) ); // @[ShiftReg.scala:45:23] assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7] endmodule

Generate the Verilog code corresponding to the following Chisel files. File Monitor.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceLine import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import freechips.rocketchip.diplomacy.EnableMonitors import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode} import freechips.rocketchip.util.PlusArg case class TLMonitorArgs(edge: TLEdge) abstract class TLMonitorBase(args: TLMonitorArgs) extends Module { val io = IO(new Bundle { val in = Input(new TLBundle(args.edge.bundle)) }) def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit legalize(io.in, args.edge, reset) } object TLMonitor { def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = { if (enable) { EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) } } else { node } } } class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args) { require (args.edge.params(TLMonitorStrictMode) || (! args.edge.params(TestplanTestType).formal)) val cover_prop_class = PropertyClass.Default //Like assert but can flip to being an assumption for formal verification def monAssert(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir, cond, message, PropertyClass.Default) } def assume(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir.flip, cond, message, PropertyClass.Default) } def extra = { args.edge.sourceInfo match { case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)" case _ => "" } } def visible(address: UInt, source: UInt, edge: TLEdge) = edge.client.clients.map { c => !c.sourceId.contains(source) || c.visibility.map(_.contains(address)).reduce(_ || _) }.reduce(_ && _) def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = { //switch this flag to turn on diplomacy in error messages def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n" monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra) // Reuse these subexpressions to save some firrtl lines val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility") //The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B //TODO: check for acquireT? when (bundle.opcode === TLMessages.AcquireBlock) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra) } when (bundle.opcode === TLMessages.AcquirePerm) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra) monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra) monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra) monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra) } } def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = { monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra) monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility") // Reuse these subexpressions to save some firrtl lines val address_ok = edge.manager.containsSafe(edge.address(bundle)) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source when (bundle.opcode === TLMessages.Probe) { assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra) assume (address_ok, "'B' channel Probe carries unmanaged address" + extra) assume (legal_source, "'B' channel Probe carries source that is not first source" + extra) assume (is_aligned, "'B' channel Probe address not aligned to size" + extra) assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra) assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra) assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra) monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra) monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra) monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra) monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra) } } def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = { monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val address_ok = edge.manager.containsSafe(edge.address(bundle)) monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility") when (bundle.opcode === TLMessages.ProbeAck) { monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra) } when (bundle.opcode === TLMessages.ProbeAckData) { monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.Release) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra) monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra) } when (bundle.opcode === TLMessages.ReleaseData) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.AccessAck) { monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra) } when (bundle.opcode === TLMessages.HintAck) { monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra) } } def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = { assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val sink_ok = bundle.sink < edge.manager.endSinkId.U val deny_put_ok = edge.manager.mayDenyPut.B val deny_get_ok = edge.manager.mayDenyGet.B when (bundle.opcode === TLMessages.ReleaseAck) { assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra) assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra) assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra) } when (bundle.opcode === TLMessages.Grant) { assume (source_ok, "'D' channel Grant carries invalid source ID" + extra) assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra) assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel Grant is denied" + extra) } when (bundle.opcode === TLMessages.GrantData) { assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra) assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra) assume (!bundle.denied || bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra) assume (deny_get_ok || !bundle.denied, "'D' channel GrantData is denied" + extra) } when (bundle.opcode === TLMessages.AccessAck) { assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel AccessAck is denied" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra) assume (!bundle.denied || bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra) assume (deny_get_ok || !bundle.denied, "'D' channel AccessAckData is denied" + extra) } when (bundle.opcode === TLMessages.HintAck) { assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel HintAck is denied" + extra) } } def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = { val sink_ok = bundle.sink < edge.manager.endSinkId.U monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra) } def legalizeFormat(bundle: TLBundle, edge: TLEdge) = { when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) } when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) } when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) } when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) } } else { monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra) monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra) monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra) } } def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = { val a_first = edge.first(a.bits, a.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (a.valid && !a_first) { monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra) monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra) monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra) monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra) monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra) } when (a.fire && a_first) { opcode := a.bits.opcode param := a.bits.param size := a.bits.size source := a.bits.source address := a.bits.address } } def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = { val b_first = edge.first(b.bits, b.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (b.valid && !b_first) { monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra) monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra) monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra) monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra) monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra) } when (b.fire && b_first) { opcode := b.bits.opcode param := b.bits.param size := b.bits.size source := b.bits.source address := b.bits.address } } def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = { // Symbolic variable val sym_source = Wire(UInt(edge.client.endSourceId.W)) // TODO: Connect sym_source to a fixed value for simulation and to a // free wire in formal sym_source := 0.U // Type casting Int to UInt val maxSourceId = Wire(UInt(edge.client.endSourceId.W)) maxSourceId := edge.client.endSourceId.U // Delayed verison of sym_source val sym_source_d = Reg(UInt(edge.client.endSourceId.W)) sym_source_d := sym_source // These will be constraints for FV setup Property( MonitorDirection.Monitor, (sym_source === sym_source_d), "sym_source should remain stable", PropertyClass.Default) Property( MonitorDirection.Monitor, (sym_source <= maxSourceId), "sym_source should take legal value", PropertyClass.Default) val my_resp_pend = RegInit(false.B) val my_opcode = Reg(UInt()) val my_size = Reg(UInt()) val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire) val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire) val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source) val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source) val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat) val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend) when (my_set_resp_pend) { my_resp_pend := true.B } .elsewhen (my_clr_resp_pend) { my_resp_pend := false.B } when (my_a_first_beat) { my_opcode := bundle.a.bits.opcode my_size := bundle.a.bits.size } val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size) val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode) val my_resp_opcode_legal = Wire(Bool()) when ((my_resp_opcode === TLMessages.Get) || (my_resp_opcode === TLMessages.ArithmeticData) || (my_resp_opcode === TLMessages.LogicalData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData) } .elsewhen ((my_resp_opcode === TLMessages.PutFullData) || (my_resp_opcode === TLMessages.PutPartialData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck) } .otherwise { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck) } monAssert (IfThen(my_resp_pend, !my_a_first_beat), "Request message should not be sent with a source ID, for which a response message" + "is already pending (not received until current cycle) for a prior request message" + "with the same source ID" + extra) assume (IfThen(my_clr_resp_pend, (my_set_resp_pend || my_resp_pend)), "Response message should be accepted with a source ID only if a request message with the" + "same source ID has been accepted or is being accepted in the current cycle" + extra) assume (IfThen(my_d_first_beat, (my_a_first_beat || my_resp_pend)), "Response message should be sent with a source ID only if a request message with the" + "same source ID has been accepted or is being sent in the current cycle" + extra) assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)), "If d_valid is 1, then d_size should be same as a_size of the corresponding request" + "message" + extra) assume (IfThen(my_d_first_beat, my_resp_opcode_legal), "If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" + "request message" + extra) } def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = { val c_first = edge.first(c.bits, c.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (c.valid && !c_first) { monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra) monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra) monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra) monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra) monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra) } when (c.fire && c_first) { opcode := c.bits.opcode param := c.bits.param size := c.bits.size source := c.bits.source address := c.bits.address } } def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = { val d_first = edge.first(d.bits, d.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val sink = Reg(UInt()) val denied = Reg(Bool()) when (d.valid && !d_first) { assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra) assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra) assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra) assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra) assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra) assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra) } when (d.fire && d_first) { opcode := d.bits.opcode param := d.bits.param size := d.bits.size source := d.bits.source sink := d.bits.sink denied := d.bits.denied } } def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = { legalizeMultibeatA(bundle.a, edge) legalizeMultibeatD(bundle.d, edge) if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { legalizeMultibeatB(bundle.b, edge) legalizeMultibeatC(bundle.c, edge) } } //This is left in for almond which doesn't adhere to the tilelink protocol @deprecated("Use legalizeADSource instead if possible","") def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.client.endSourceId.W)) val a_first = edge.first(bundle.a.bits, bundle.a.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val a_set = WireInit(0.U(edge.client.endSourceId.W)) when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) assume((a_set | inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra) } if (edge.manager.minLatency > 0) { assume(a_set =/= d_clr || !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight | a_set) & ~d_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") assert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = { val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size) val log_a_size_bus_size = log2Ceil(a_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error inflight.suggestName("inflight") val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) inflight_opcodes.suggestName("inflight_opcodes") val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) inflight_sizes.suggestName("inflight_sizes") val a_first = edge.first(bundle.a.bits, bundle.a.fire) a_first.suggestName("a_first") val d_first = edge.first(bundle.d.bits, bundle.d.fire) d_first.suggestName("d_first") val a_set = WireInit(0.U(edge.client.endSourceId.W)) val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) a_set.suggestName("a_set") a_set_wo_ready.suggestName("a_set_wo_ready") val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) a_opcodes_set.suggestName("a_opcodes_set") val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) a_sizes_set.suggestName("a_sizes_set") val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W)) a_opcode_lookup.suggestName("a_opcode_lookup") a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W)) a_size_lookup.suggestName("a_size_lookup") a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant)) val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant)) val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W)) a_opcodes_set_interm.suggestName("a_opcodes_set_interm") val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W)) a_sizes_set_interm.suggestName("a_sizes_set_interm") when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) { a_set_wo_ready := UIntToOH(bundle.a.bits.source) } when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) | 1.U a_sizes_set_interm := (bundle.a.bits.size << 1.U) | 1.U a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U) a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U) monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) d_opcodes_clr.suggestName("d_opcodes_clr") val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) || (bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra) assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) || (bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra) assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) { assume((!bundle.d.ready) || bundle.a.ready, "ready check") } if (edge.manager.minLatency > 0) { assume(a_set_wo_ready =/= d_clr_wo_ready || !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight | a_set) & ~d_clr inflight_opcodes := (inflight_opcodes | a_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes | a_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = { val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size) val log_c_size_bus_size = log2Ceil(c_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) inflight.suggestName("inflight") inflight_opcodes.suggestName("inflight_opcodes") inflight_sizes.suggestName("inflight_sizes") val c_first = edge.first(bundle.c.bits, bundle.c.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) c_first.suggestName("c_first") d_first.suggestName("d_first") val c_set = WireInit(0.U(edge.client.endSourceId.W)) val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) c_set.suggestName("c_set") c_set_wo_ready.suggestName("c_set_wo_ready") c_opcodes_set.suggestName("c_opcodes_set") c_sizes_set.suggestName("c_sizes_set") val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W)) val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W)) c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U c_opcode_lookup.suggestName("c_opcode_lookup") c_size_lookup.suggestName("c_size_lookup") val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W)) val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W)) c_opcodes_set_interm.suggestName("c_opcodes_set_interm") c_sizes_set_interm.suggestName("c_sizes_set_interm") when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) { c_set_wo_ready := UIntToOH(bundle.c.bits.source) } when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) { c_set := UIntToOH(bundle.c.bits.source) c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) | 1.U c_sizes_set_interm := (bundle.c.bits.size << 1.U) | 1.U c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U) c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U) monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra) } val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck || bundle.c.bits.opcode === TLMessages.ProbeAckData val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") d_opcodes_clr.suggestName("d_opcodes_clr") d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) { assume((!bundle.d.ready) || bundle.c.ready, "ready check") } if (edge.manager.minLatency > 0) { when (c_set_wo_ready.orR) { assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra) } } inflight := (inflight | c_set) & ~d_clr inflight_opcodes := (inflight_opcodes | c_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes | c_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.c.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.manager.endSinkId.W)) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val e_first = true.B val d_set = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) { d_set := UIntToOH(bundle.d.bits.sink) assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra) } val e_clr = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) { e_clr := UIntToOH(bundle.e.bits.sink) monAssert((d_set | inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra) } // edge.client.minLatency applies to BC, not DE inflight := (inflight | d_set) & ~e_clr } def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = { val sourceBits = log2Ceil(edge.client.endSourceId) val tooBig = 14 // >16kB worth of flight information gets to be too much if (sourceBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked") } else { if (args.edge.params(TestplanTestType).simulation) { if (args.edge.params(TLMonitorStrictMode)) { legalizeADSource(bundle, edge) legalizeCDSource(bundle, edge) } else { legalizeADSourceOld(bundle, edge) } } if (args.edge.params(TestplanTestType).formal) { legalizeADSourceFormal(bundle, edge) } } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { // legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize... val sinkBits = log2Ceil(edge.manager.endSinkId) if (sinkBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked") } else { legalizeDESink(bundle, edge) } } } def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = { legalizeFormat (bundle, edge) legalizeMultibeat (bundle, edge) legalizeUnique (bundle, edge) } } File Misc.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import scala.math._ class ParameterizedBundle(implicit p: Parameters) extends Bundle trait Clocked extends Bundle { val clock = Clock() val reset = Bool() } object DecoupledHelper { def apply(rvs: Bool*) = new DecoupledHelper(rvs) } class DecoupledHelper(val rvs: Seq[Bool]) { def fire(exclude: Bool, includes: Bool*) = { require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!") (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _) } def fire() = { rvs.reduce(_ && _) } } object MuxT { def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2)) def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3)) def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4)) } /** Creates a cascade of n MuxTs to search for a key value. */ object MuxTLookup { def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } } object ValidMux { def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]*): ValidIO[T] = { apply(v1 +: v2.toSeq) } def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = { val out = Wire(Valid(valids.head.bits.cloneType)) out.valid := valids.map(_.valid).reduce(_ || _) out.bits := MuxCase(valids.head.bits, valids.map(v => (v.valid -> v.bits))) out } } object Str { def apply(s: String): UInt = { var i = BigInt(0) require(s.forall(validChar _)) for (c <- s) i = (i << 8) | c i.U((s.length*8).W) } def apply(x: Char): UInt = { require(validChar(x)) x.U(8.W) } def apply(x: UInt): UInt = apply(x, 10) def apply(x: UInt, radix: Int): UInt = { val rad = radix.U val w = x.getWidth require(w > 0) var q = x var s = digit(q % rad) for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s) } s } def apply(x: SInt): UInt = apply(x, 10) def apply(x: SInt, radix: Int): UInt = { val neg = x < 0.S val abs = x.abs.asUInt if (radix != 10) { Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix)) } else { val rad = radix.U val w = abs.getWidth require(w > 0) var q = abs var s = digit(q % rad) var needSign = neg for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad val placeSpace = q === 0.U val space = Mux(needSign, Str('-'), Str(' ')) needSign = needSign && !placeSpace s = Cat(Mux(placeSpace, space, digit(q % rad)), s) } Cat(Mux(needSign, Str('-'), Str(' ')), s) } } private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0) private def validChar(x: Char) = x == (x & 0xFF) } object Split { def apply(x: UInt, n0: Int) = { val w = x.getWidth (x.extract(w-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n2: Int, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } } object Random { def apply(mod: Int, random: UInt): UInt = { if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0) else PriorityEncoder(partition(apply(1 << log2Up(mod*8), random), mod)) } def apply(mod: Int): UInt = apply(mod, randomizer) def oneHot(mod: Int, random: UInt): UInt = { if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0)) else PriorityEncoderOH(partition(apply(1 << log2Up(mod*8), random), mod)).asUInt } def oneHot(mod: Int): UInt = oneHot(mod, randomizer) private def randomizer = LFSR(16) private def partition(value: UInt, slices: Int) = Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U) } object Majority { def apply(in: Set[Bool]): Bool = { val n = (in.size >> 1) + 1 val clauses = in.subsets(n).map(_.reduce(_ && _)) clauses.reduce(_ || _) } def apply(in: Seq[Bool]): Bool = apply(in.toSet) def apply(in: UInt): Bool = apply(in.asBools.toSet) } object PopCountAtLeast { private def two(x: UInt): (Bool, Bool) = x.getWidth match { case 1 => (x.asBool, false.B) case n => val half = x.getWidth / 2 val (leftOne, leftTwo) = two(x(half - 1, 0)) val (rightOne, rightTwo) = two(x(x.getWidth - 1, half)) (leftOne || rightOne, leftTwo || rightTwo || (leftOne && rightOne)) } def apply(x: UInt, n: Int): Bool = n match { case 0 => true.B case 1 => x.orR case 2 => two(x)._2 case 3 => PopCount(x) >= n.U } } // This gets used everywhere, so make the smallest circuit possible ... // Given an address and size, create a mask of beatBytes size // eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111 // groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01 object MaskGen { def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = { require (groupBy >= 1 && beatBytes >= groupBy) require (isPow2(beatBytes) && isPow2(groupBy)) val lgBytes = log2Ceil(beatBytes) val sizeOH = UIntToOH(lgSize | 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) | (groupBy*2 - 1).U def helper(i: Int): Seq[(Bool, Bool)] = { if (i == 0) { Seq((lgSize >= lgBytes.asUInt, true.B)) } else { val sub = helper(i-1) val size = sizeOH(lgBytes - i) val bit = addr_lo(lgBytes - i) val nbit = !bit Seq.tabulate (1 << i) { j => val (sub_acc, sub_eq) = sub(j/2) val eq = sub_eq && (if (j % 2 == 1) bit else nbit) val acc = sub_acc || (size && eq) (acc, eq) } } } if (groupBy == beatBytes) 1.U else Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse) } } File PlusArg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.experimental._ import chisel3.util.HasBlackBoxResource @deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05") case class PlusArgInfo(default: BigInt, docstring: String) /** Case class for PlusArg information * * @tparam A scala type of the PlusArg value * @param default optional default value * @param docstring text to include in the help * @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT) */ private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String) /** Typeclass for converting a type to a doctype string * @tparam A some type */ trait Doctypeable[A] { /** Return the doctype string for some option */ def toDoctype(a: Option[A]): String } /** Object containing implementations of the Doctypeable typeclass */ object Doctypes { /** Converts an Int => "INT" */ implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" } /** Converts a BigInt => "INT" */ implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" } /** Converts a String => "STRING" */ implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" } } class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map( "FORMAT" -> StringParam(format), "DEFAULT" -> IntParam(default), "WIDTH" -> IntParam(width) )) with HasBlackBoxResource { val io = IO(new Bundle { val out = Output(UInt(width.W)) }) addResource("/vsrc/plusarg_reader.v") } /* This wrapper class has no outputs, making it clear it is a simulation-only construct */ class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module { val io = IO(new Bundle { val count = Input(UInt(width.W)) }) val max = Module(new plusarg_reader(format, default, docstring, width)).io.out when (max > 0.U) { assert (io.count < max, s"Timeout exceeded: $docstring") } } import Doctypes._ object PlusArg { /** PlusArg("foo") will return 42.U if the simulation is run with +foo=42 * Do not use this as an initial register value. The value is set in an * initial block and thus accessing it from another initial is racey. * Add a docstring to document the arg, which can be dumped in an elaboration * pass. */ def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out } /** PlusArg.timeout(name, default, docstring)(count) will use chisel.assert * to kill the simulation when count exceeds the specified integer argument. * Default 0 will never assert. */ def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count } } object PlusArgArtefacts { private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty /* Add a new PlusArg */ @deprecated( "Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05" ) def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring) /** Add a new PlusArg * * @tparam A scala type of the PlusArg value * @param name name for the PlusArg * @param default optional default value * @param docstring text to include in the help */ def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit = artefacts = artefacts ++ Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default))) /* From plus args, generate help text */ private def serializeHelp_cHeader(tab: String = ""): String = artefacts .map{ case(arg, info) => s"""|$tab+$arg=${info.doctype}\\n\\ |$tab${" "*20}${info.docstring}\\n\\ |""".stripMargin ++ info.default.map{ case default => s"$tab${" "*22}(default=${default})\\n\\\n"}.getOrElse("") }.toSeq.mkString("\\n\\\n") ++ "\"" /* From plus args, generate a char array of their names */ private def serializeArray_cHeader(tab: String = ""): String = { val prettyTab = tab + " " * 44 // Length of 'static const ...' s"${tab}static const char * verilog_plusargs [] = {\\\n" ++ artefacts .map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" } .mkString("")++ s"${prettyTab}0};" } /* Generate C code to be included in emulator.cc that helps with * argument parsing based on available Verilog PlusArgs */ def serialize_cHeader(): String = s"""|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\ |${serializeHelp_cHeader(" "*7)} |${serializeArray_cHeader()} |""".stripMargin } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /** Like Vec.apply(idx), but tolerates indices of mismatched width */ def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /** Any Data subtype that has a Bool member named valid. */ type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /** converts from camel case to to underscores, also removing all spaces */ def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /** converts spaces or underscores to hyphens, also lowering case */ def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y | (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y || y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /** Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation */ def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Bundles.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import freechips.rocketchip.util._ import scala.collection.immutable.ListMap import chisel3.util.Decoupled import chisel3.util.DecoupledIO import chisel3.reflect.DataMirror abstract class TLBundleBase(val params: TLBundleParameters) extends Bundle // common combos in lazy policy: // Put + Acquire // Release + AccessAck object TLMessages { // A B C D E def PutFullData = 0.U // . . => AccessAck def PutPartialData = 1.U // . . => AccessAck def ArithmeticData = 2.U // . . => AccessAckData def LogicalData = 3.U // . . => AccessAckData def Get = 4.U // . . => AccessAckData def Hint = 5.U // . . => HintAck def AcquireBlock = 6.U // . => Grant[Data] def AcquirePerm = 7.U // . => Grant[Data] def Probe = 6.U // . => ProbeAck[Data] def AccessAck = 0.U // . . def AccessAckData = 1.U // . . def HintAck = 2.U // . . def ProbeAck = 4.U // . def ProbeAckData = 5.U // . def Release = 6.U // . => ReleaseAck def ReleaseData = 7.U // . => ReleaseAck def Grant = 4.U // . => GrantAck def GrantData = 5.U // . => GrantAck def ReleaseAck = 6.U // . def GrantAck = 0.U // . def isA(x: UInt) = x <= AcquirePerm def isB(x: UInt) = x <= Probe def isC(x: UInt) = x <= ReleaseData def isD(x: UInt) = x <= ReleaseAck def adResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, Grant, Grant) def bcResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, ProbeAck, ProbeAck) def a = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("AcquireBlock",TLPermissions.PermMsgGrow), ("AcquirePerm",TLPermissions.PermMsgGrow)) def b = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("Probe",TLPermissions.PermMsgCap)) def c = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("ProbeAck",TLPermissions.PermMsgReport), ("ProbeAckData",TLPermissions.PermMsgReport), ("Release",TLPermissions.PermMsgReport), ("ReleaseData",TLPermissions.PermMsgReport)) def d = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("Grant",TLPermissions.PermMsgCap), ("GrantData",TLPermissions.PermMsgCap), ("ReleaseAck",TLPermissions.PermMsgReserved)) } /** * The three primary TileLink permissions are: * (T)runk: the agent is (or is on inwards path to) the global point of serialization. * (B)ranch: the agent is on an outwards path to * (N)one: * These permissions are permuted by transfer operations in various ways. * Operations can cap permissions, request for them to be grown or shrunk, * or for a report on their current status. */ object TLPermissions { val aWidth = 2 val bdWidth = 2 val cWidth = 3 // Cap types (Grant = new permissions, Probe = permisions <= target) def toT = 0.U(bdWidth.W) def toB = 1.U(bdWidth.W) def toN = 2.U(bdWidth.W) def isCap(x: UInt) = x <= toN // Grow types (Acquire = permissions >= target) def NtoB = 0.U(aWidth.W) def NtoT = 1.U(aWidth.W) def BtoT = 2.U(aWidth.W) def isGrow(x: UInt) = x <= BtoT // Shrink types (ProbeAck, Release) def TtoB = 0.U(cWidth.W) def TtoN = 1.U(cWidth.W) def BtoN = 2.U(cWidth.W) def isShrink(x: UInt) = x <= BtoN // Report types (ProbeAck, Release) def TtoT = 3.U(cWidth.W) def BtoB = 4.U(cWidth.W) def NtoN = 5.U(cWidth.W) def isReport(x: UInt) = x <= NtoN def PermMsgGrow:Seq[String] = Seq("Grow NtoB", "Grow NtoT", "Grow BtoT") def PermMsgCap:Seq[String] = Seq("Cap toT", "Cap toB", "Cap toN") def PermMsgReport:Seq[String] = Seq("Shrink TtoB", "Shrink TtoN", "Shrink BtoN", "Report TotT", "Report BtoB", "Report NtoN") def PermMsgReserved:Seq[String] = Seq("Reserved") } object TLAtomics { val width = 3 // Arithmetic types def MIN = 0.U(width.W) def MAX = 1.U(width.W) def MINU = 2.U(width.W) def MAXU = 3.U(width.W) def ADD = 4.U(width.W) def isArithmetic(x: UInt) = x <= ADD // Logical types def XOR = 0.U(width.W) def OR = 1.U(width.W) def AND = 2.U(width.W) def SWAP = 3.U(width.W) def isLogical(x: UInt) = x <= SWAP def ArithMsg:Seq[String] = Seq("MIN", "MAX", "MINU", "MAXU", "ADD") def LogicMsg:Seq[String] = Seq("XOR", "OR", "AND", "SWAP") } object TLHints { val width = 1 def PREFETCH_READ = 0.U(width.W) def PREFETCH_WRITE = 1.U(width.W) def isHints(x: UInt) = x <= PREFETCH_WRITE def HintsMsg:Seq[String] = Seq("PrefetchRead", "PrefetchWrite") } sealed trait TLChannel extends TLBundleBase { val channelName: String } sealed trait TLDataChannel extends TLChannel sealed trait TLAddrChannel extends TLDataChannel final class TLBundleA(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleA_${params.shortName}" val channelName = "'A' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(List(TLAtomics.width, TLPermissions.aWidth, TLHints.width).max.W) // amo_opcode || grow perms || hint val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleB(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleB_${params.shortName}" val channelName = "'B' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val address = UInt(params.addressBits.W) // from // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleC(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleC_${params.shortName}" val channelName = "'C' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.cWidth.W) // shrink or report perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleD(params: TLBundleParameters) extends TLBundleBase(params) with TLDataChannel { override def typeName = s"TLBundleD_${params.shortName}" val channelName = "'D' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val sink = UInt(params.sinkBits.W) // from val denied = Bool() // implies corrupt iff *Data val user = BundleMap(params.responseFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleE(params: TLBundleParameters) extends TLBundleBase(params) with TLChannel { override def typeName = s"TLBundleE_${params.shortName}" val channelName = "'E' channel" val sink = UInt(params.sinkBits.W) // to } class TLBundle(val params: TLBundleParameters) extends Record { // Emulate a Bundle with elements abcde or ad depending on params.hasBCE private val optA = Some (Decoupled(new TLBundleA(params))) private val optB = params.hasBCE.option(Flipped(Decoupled(new TLBundleB(params)))) private val optC = params.hasBCE.option(Decoupled(new TLBundleC(params))) private val optD = Some (Flipped(Decoupled(new TLBundleD(params)))) private val optE = params.hasBCE.option(Decoupled(new TLBundleE(params))) def a: DecoupledIO[TLBundleA] = optA.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleA(params))))) def b: DecoupledIO[TLBundleB] = optB.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleB(params))))) def c: DecoupledIO[TLBundleC] = optC.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleC(params))))) def d: DecoupledIO[TLBundleD] = optD.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleD(params))))) def e: DecoupledIO[TLBundleE] = optE.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleE(params))))) val elements = if (params.hasBCE) ListMap("e" -> e, "d" -> d, "c" -> c, "b" -> b, "a" -> a) else ListMap("d" -> d, "a" -> a) def tieoff(): Unit = { DataMirror.specifiedDirectionOf(a.ready) match { case SpecifiedDirection.Input => a.ready := false.B c.ready := false.B e.ready := false.B b.valid := false.B d.valid := false.B case SpecifiedDirection.Output => a.valid := false.B c.valid := false.B e.valid := false.B b.ready := false.B d.ready := false.B case _ => } } } object TLBundle { def apply(params: TLBundleParameters) = new TLBundle(params) } class TLAsyncBundleBase(val params: TLAsyncBundleParameters) extends Bundle class TLAsyncBundle(params: TLAsyncBundleParameters) extends TLAsyncBundleBase(params) { val a = new AsyncBundle(new TLBundleA(params.base), params.async) val b = Flipped(new AsyncBundle(new TLBundleB(params.base), params.async)) val c = new AsyncBundle(new TLBundleC(params.base), params.async) val d = Flipped(new AsyncBundle(new TLBundleD(params.base), params.async)) val e = new AsyncBundle(new TLBundleE(params.base), params.async) } class TLRationalBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = RationalIO(new TLBundleA(params)) val b = Flipped(RationalIO(new TLBundleB(params))) val c = RationalIO(new TLBundleC(params)) val d = Flipped(RationalIO(new TLBundleD(params))) val e = RationalIO(new TLBundleE(params)) } class TLCreditedBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = CreditedIO(new TLBundleA(params)) val b = Flipped(CreditedIO(new TLBundleB(params))) val c = CreditedIO(new TLBundleC(params)) val d = Flipped(CreditedIO(new TLBundleD(params))) val e = CreditedIO(new TLBundleE(params)) } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.diplomacy import chisel3._ import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor} import freechips.rocketchip.util.ShiftQueue /** Options for describing the attributes of memory regions */ object RegionType { // Define the 'more relaxed than' ordering val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS) sealed trait T extends Ordered[T] { def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this) } case object CACHED extends T // an intermediate agent may have cached a copy of the region for you case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively } // A non-empty half-open range; [start, end) case class IdRange(start: Int, end: Int) extends Ordered[IdRange] { require (start >= 0, s"Ids cannot be negative, but got: $start.") require (start <= end, "Id ranges cannot be negative.") def compare(x: IdRange) = { val primary = (this.start - x.start).signum val secondary = (x.end - this.end).signum if (primary != 0) primary else secondary } def overlaps(x: IdRange) = start < x.end && x.start < end def contains(x: IdRange) = start <= x.start && x.end <= end def contains(x: Int) = start <= x && x < end def contains(x: UInt) = if (size == 0) { false.B } else if (size == 1) { // simple comparison x === start.U } else { // find index of largest different bit val largestDeltaBit = log2Floor(start ^ (end-1)) val smallestCommonBit = largestDeltaBit + 1 // may not exist in x val uncommonMask = (1 << smallestCommonBit) - 1 val uncommonBits = (x | 0.U(smallestCommonBit.W))(largestDeltaBit, 0) // the prefix must match exactly (note: may shift ALL bits away) (x >> smallestCommonBit) === (start >> smallestCommonBit).U && // firrtl constant prop range analysis can eliminate these two: (start & uncommonMask).U <= uncommonBits && uncommonBits <= ((end-1) & uncommonMask).U } def shift(x: Int) = IdRange(start+x, end+x) def size = end - start def isEmpty = end == start def range = start until end } object IdRange { def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else { val ranges = s.sorted (ranges.tail zip ranges.init) find { case (a, b) => a overlaps b } } } // An potentially empty inclusive range of 2-powers [min, max] (in bytes) case class TransferSizes(min: Int, max: Int) { def this(x: Int) = this(x, x) require (min <= max, s"Min transfer $min > max transfer $max") require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)") require (max == 0 || isPow2(max), s"TransferSizes must be a power of 2, got: $max") require (min == 0 || isPow2(min), s"TransferSizes must be a power of 2, got: $min") require (max == 0 || min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)") def none = min == 0 def contains(x: Int) = isPow2(x) && min <= x && x <= max def containsLg(x: Int) = contains(1 << x) def containsLg(x: UInt) = if (none) false.B else if (min == max) { log2Ceil(min).U === x } else { log2Ceil(min).U <= x && x <= log2Ceil(max).U } def contains(x: TransferSizes) = x.none || (min <= x.min && x.max <= max) def intersect(x: TransferSizes) = if (x.max < min || max < x.min) TransferSizes.none else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max)) // Not a union, because the result may contain sizes contained by neither term // NOT TO BE CONFUSED WITH COVERPOINTS def mincover(x: TransferSizes) = { if (none) { x } else if (x.none) { this } else { TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max)) } } override def toString() = "TransferSizes[%d, %d]".format(min, max) } object TransferSizes { def apply(x: Int) = new TransferSizes(x) val none = new TransferSizes(0) def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _) def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _) implicit def asBool(x: TransferSizes) = !x.none } // AddressSets specify the address space managed by the manager // Base is the base address, and mask are the bits consumed by the manager // e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff // e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ... case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet] { // Forbid misaligned base address (and empty sets) require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}") require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous // We do allow negative mask (=> ignore all high bits) def contains(x: BigInt) = ((x ^ base) & ~mask) == 0 def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S // turn x into an address contained in this set def legalize(x: UInt): UInt = base.U | (mask.U & x) // overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1) def overlaps(x: AddressSet) = (~(mask | x.mask) & (base ^ x.base)) == 0 // contains iff bitwise: x.mask => mask && contains(x.base) def contains(x: AddressSet) = ((x.mask | (base ^ x.base)) & ~mask) == 0 // The number of bytes to which the manager must be aligned def alignment = ((mask + 1) & ~mask) // Is this a contiguous memory range def contiguous = alignment == mask+1 def finite = mask >= 0 def max = { require (finite, "Max cannot be calculated on infinite mask"); base | mask } // Widen the match function to ignore all bits in imask def widen(imask: BigInt) = AddressSet(base & ~imask, mask | imask) // Return an AddressSet that only contains the addresses both sets contain def intersect(x: AddressSet): Option[AddressSet] = { if (!overlaps(x)) { None } else { val r_mask = mask & x.mask val r_base = base | x.base Some(AddressSet(r_base, r_mask)) } } def subtract(x: AddressSet): Seq[AddressSet] = { intersect(x) match { case None => Seq(this) case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit => val nmask = (mask & (bit-1)) | remove.mask val nbase = (remove.base ^ bit) & ~nmask AddressSet(nbase, nmask) } } } // AddressSets have one natural Ordering (the containment order, if contiguous) def compare(x: AddressSet) = { val primary = (this.base - x.base).signum // smallest address first val secondary = (x.mask - this.mask).signum // largest mask first if (primary != 0) primary else secondary } // We always want to see things in hex override def toString() = { if (mask >= 0) { "AddressSet(0x%x, 0x%x)".format(base, mask) } else { "AddressSet(0x%x, ~0x%x)".format(base, ~mask) } } def toRanges = { require (finite, "Ranges cannot be calculated on infinite mask") val size = alignment val fragments = mask & ~(size-1) val bits = bitIndexes(fragments) (BigInt(0) until (BigInt(1) << bits.size)).map { i => val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) } AddressRange(off, size) } } } object AddressSet { val everything = AddressSet(0, -1) def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = { if (size == 0) tail.reverse else { val maxBaseAlignment = base & (-base) // 0 for infinite (LSB) val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size val step = if (maxBaseAlignment == 0 || maxBaseAlignment > maxSizeAlignment) maxSizeAlignment else maxBaseAlignment misaligned(base+step, size-step, AddressSet(base, step-1) +: tail) } } def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = { // Pair terms up by ignoring 'bit' seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) => if (seq.size == 1) { seq.head // singleton -> unaffected } else { key.copy(mask = key.mask | bit) // pair - widen mask by bit } }.toList } def unify(seq: Seq[AddressSet]): Seq[AddressSet] = { val bits = seq.map(_.base).foldLeft(BigInt(0))(_ | _) AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted } def enumerateMask(mask: BigInt): Seq[BigInt] = { def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] = if (id == mask) (id +: tail).reverse else helper(((~mask | id) + 1) & mask, id +: tail) helper(0, Nil) } def enumerateBits(mask: BigInt): Seq[BigInt] = { def helper(x: BigInt): Seq[BigInt] = { if (x == 0) { Nil } else { val bit = x & (-x) bit +: helper(x & ~bit) } } helper(mask) } } case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean) { require (depth >= 0, "Buffer depth must be >= 0") def isDefined = depth > 0 def latency = if (isDefined && !flow) 1 else 0 def apply[T <: Data](x: DecoupledIO[T]) = if (isDefined) Queue(x, depth, flow=flow, pipe=pipe) else x def irrevocable[T <: Data](x: ReadyValidIO[T]) = if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe) else x def sq[T <: Data](x: DecoupledIO[T]) = if (!isDefined) x else { val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe)) sq.io.enq <> x sq.io.deq } override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "") } object BufferParams { implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false) val default = BufferParams(2) val none = BufferParams(0) val flow = BufferParams(1, true, false) val pipe = BufferParams(1, false, true) } case class TriStateValue(value: Boolean, set: Boolean) { def update(orig: Boolean) = if (set) value else orig } object TriStateValue { implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true) def unset = TriStateValue(false, false) } trait DirectedBuffers[T] { def copyIn(x: BufferParams): T def copyOut(x: BufferParams): T def copyInOut(x: BufferParams): T } trait IdMapEntry { def name: String def from: IdRange def to: IdRange def isCache: Boolean def requestFifo: Boolean def maxTransactionsInFlight: Option[Int] def pretty(fmt: String) = if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5 fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } else { fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } } abstract class IdMap[T <: IdMapEntry] { protected val fmt: String val mapping: Seq[T] def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n") } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) || !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.ProbeAckData || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode | small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U || beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }

module TLMonitor_54( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [1:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [10:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [16:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [10:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [1:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [10:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [16:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [10:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_sink = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_denied = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire _source_ok_T = 1'h0; // @[Parameters.scala:54:10] wire _source_ok_T_6 = 1'h0; // @[Parameters.scala:54:10] wire sink_ok = 1'h0; // @[Monitor.scala:309:31] wire a_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire a_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire a_first_count = 1'h0; // @[Edges.scala:234:25] wire d_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire d_first_count = 1'h0; // @[Edges.scala:234:25] wire a_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59] wire a_first_beats1_1 = 1'h0; // @[Edges.scala:221:14] wire a_first_count_1 = 1'h0; // @[Edges.scala:234:25] wire d_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1_1 = 1'h0; // @[Edges.scala:221:14] wire d_first_count_1 = 1'h0; // @[Edges.scala:234:25] wire d_release_ack = 1'h0; // @[Monitor.scala:673:46] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire c_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_first_count_T = 1'h0; // @[Edges.scala:234:27] wire c_first_count = 1'h0; // @[Edges.scala:234:25] wire _c_first_counter_T = 1'h0; // @[Edges.scala:236:21] wire d_first_beats1_decode_2 = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1_2 = 1'h0; // @[Edges.scala:221:14] wire d_first_count_2 = 1'h0; // @[Edges.scala:234:25] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire d_release_ack_1 = 1'h0; // @[Monitor.scala:783:46] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire _source_ok_T_1 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:54:67] wire _source_ok_T_7 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_8 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:54:67] wire _a_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire a_first_last = 1'h1; // @[Edges.scala:232:33] wire d_first_beats1_opdata = 1'h1; // @[Edges.scala:106:36] wire _d_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire d_first_last = 1'h1; // @[Edges.scala:232:33] wire _a_first_last_T_3 = 1'h1; // @[Edges.scala:232:43] wire a_first_last_1 = 1'h1; // @[Edges.scala:232:33] wire d_first_beats1_opdata_1 = 1'h1; // @[Edges.scala:106:36] wire _d_first_last_T_3 = 1'h1; // @[Edges.scala:232:43] wire d_first_last_1 = 1'h1; // @[Edges.scala:232:33] wire c_first_counter1 = 1'h1; // @[Edges.scala:230:28] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire d_first_beats1_opdata_2 = 1'h1; // @[Edges.scala:106:36] wire _d_first_last_T_5 = 1'h1; // @[Edges.scala:232:43] wire d_first_last_2 = 1'h1; // @[Edges.scala:232:33] wire [1:0] _c_first_counter1_T = 2'h3; // @[Edges.scala:230:28] wire [1:0] io_in_d_bits_param = 2'h0; // @[Monitor.scala:36:7] wire [1:0] _c_first_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_first_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_first_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_first_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_set_wo_ready_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_set_wo_ready_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_opcodes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_opcodes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_sizes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_sizes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_opcodes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_opcodes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_sizes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_sizes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_probe_ack_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_probe_ack_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_probe_ack_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_probe_ack_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_4_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_5_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [2:0] io_in_d_bits_opcode = 3'h1; // @[Monitor.scala:36:7] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] _c_sizes_set_interm_T_1 = 3'h1; // @[Monitor.scala:766:59] wire [4159:0] _inflight_opcodes_T_4 = 4160'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF; // @[Monitor.scala:815:62] wire [4159:0] _inflight_sizes_T_4 = 4160'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF; // @[Monitor.scala:816:58] wire [1039:0] _inflight_T_4 = 1040'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF; // @[Monitor.scala:814:46] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [16:0] _c_first_WIRE_bits_address = 17'h0; // @[Bundles.scala:265:74] wire [16:0] _c_first_WIRE_1_bits_address = 17'h0; // @[Bundles.scala:265:61] wire [16:0] _c_first_WIRE_2_bits_address = 17'h0; // @[Bundles.scala:265:74] wire [16:0] _c_first_WIRE_3_bits_address = 17'h0; // @[Bundles.scala:265:61] wire [16:0] _c_set_wo_ready_WIRE_bits_address = 17'h0; // @[Bundles.scala:265:74] wire [16:0] _c_set_wo_ready_WIRE_1_bits_address = 17'h0; // @[Bundles.scala:265:61] wire [16:0] _c_set_WIRE_bits_address = 17'h0; // @[Bundles.scala:265:74] wire [16:0] _c_set_WIRE_1_bits_address = 17'h0; // @[Bundles.scala:265:61] wire [16:0] _c_opcodes_set_interm_WIRE_bits_address = 17'h0; // @[Bundles.scala:265:74] wire [16:0] _c_opcodes_set_interm_WIRE_1_bits_address = 17'h0; // @[Bundles.scala:265:61] wire [16:0] _c_sizes_set_interm_WIRE_bits_address = 17'h0; // @[Bundles.scala:265:74] wire [16:0] _c_sizes_set_interm_WIRE_1_bits_address = 17'h0; // @[Bundles.scala:265:61] wire [16:0] _c_opcodes_set_WIRE_bits_address = 17'h0; // @[Bundles.scala:265:74] wire [16:0] _c_opcodes_set_WIRE_1_bits_address = 17'h0; // @[Bundles.scala:265:61] wire [16:0] _c_sizes_set_WIRE_bits_address = 17'h0; // @[Bundles.scala:265:74] wire [16:0] _c_sizes_set_WIRE_1_bits_address = 17'h0; // @[Bundles.scala:265:61] wire [16:0] _c_probe_ack_WIRE_bits_address = 17'h0; // @[Bundles.scala:265:74] wire [16:0] _c_probe_ack_WIRE_1_bits_address = 17'h0; // @[Bundles.scala:265:61] wire [16:0] _c_probe_ack_WIRE_2_bits_address = 17'h0; // @[Bundles.scala:265:74] wire [16:0] _c_probe_ack_WIRE_3_bits_address = 17'h0; // @[Bundles.scala:265:61] wire [16:0] _same_cycle_resp_WIRE_bits_address = 17'h0; // @[Bundles.scala:265:74] wire [16:0] _same_cycle_resp_WIRE_1_bits_address = 17'h0; // @[Bundles.scala:265:61] wire [16:0] _same_cycle_resp_WIRE_2_bits_address = 17'h0; // @[Bundles.scala:265:74] wire [16:0] _same_cycle_resp_WIRE_3_bits_address = 17'h0; // @[Bundles.scala:265:61] wire [16:0] _same_cycle_resp_WIRE_4_bits_address = 17'h0; // @[Bundles.scala:265:74] wire [16:0] _same_cycle_resp_WIRE_5_bits_address = 17'h0; // @[Bundles.scala:265:61] wire [10:0] _c_first_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_first_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_first_WIRE_2_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_first_WIRE_3_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_set_wo_ready_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_set_wo_ready_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_set_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_set_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_opcodes_set_interm_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_opcodes_set_interm_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_sizes_set_interm_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_sizes_set_interm_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_opcodes_set_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_opcodes_set_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_sizes_set_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_sizes_set_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_probe_ack_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_probe_ack_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_probe_ack_WIRE_2_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_probe_ack_WIRE_3_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _same_cycle_resp_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _same_cycle_resp_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _same_cycle_resp_WIRE_2_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _same_cycle_resp_WIRE_3_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _same_cycle_resp_WIRE_4_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _same_cycle_resp_WIRE_5_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_beats1_decode_T_2 = 3'h0; // @[package.scala:243:46] wire [2:0] c_sizes_set_interm = 3'h0; // @[Monitor.scala:755:40] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_T = 3'h0; // @[Monitor.scala:766:51] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [4159:0] c_opcodes_set = 4160'h0; // @[Monitor.scala:740:34] wire [4159:0] c_sizes_set = 4160'h0; // @[Monitor.scala:741:34] wire [4159:0] d_opcodes_clr_1 = 4160'h0; // @[Monitor.scala:776:34] wire [4159:0] d_sizes_clr_1 = 4160'h0; // @[Monitor.scala:777:34] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [1039:0] c_set = 1040'h0; // @[Monitor.scala:738:34] wire [1039:0] c_set_wo_ready = 1040'h0; // @[Monitor.scala:739:34] wire [1039:0] d_clr_1 = 1040'h0; // @[Monitor.scala:774:34] wire [1039:0] d_clr_wo_ready_1 = 1040'h0; // @[Monitor.scala:775:34] wire [16385:0] _c_sizes_set_T_1 = 16386'h0; // @[Monitor.scala:768:52] wire [13:0] _c_opcodes_set_T = 14'h0; // @[Monitor.scala:767:79] wire [13:0] _c_sizes_set_T = 14'h0; // @[Monitor.scala:768:77] wire [16386:0] _c_opcodes_set_T_1 = 16387'h0; // @[Monitor.scala:767:54] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [2047:0] _c_set_wo_ready_T = 2048'h1; // @[OneHot.scala:58:35] wire [2047:0] _c_set_T = 2048'h1; // @[OneHot.scala:58:35] wire [2:0] _c_first_beats1_decode_T_1 = 3'h7; // @[package.scala:243:76] wire [5:0] _c_first_beats1_decode_T = 6'h7; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48] wire [10:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _source_ok_uncommonBits_T_1 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] source_ok_uncommonBits = _source_ok_uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_4 = source_ok_uncommonBits < 11'h410; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_5 = _source_ok_T_4; // @[Parameters.scala:56:48, :57:20] wire _source_ok_WIRE_0 = _source_ok_T_5; // @[Parameters.scala:1138:31] wire [5:0] _GEN = 6'h7 << io_in_a_bits_size_0; // @[package.scala:243:71] wire [5:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [5:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [5:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [2:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[2:0]; // @[package.scala:243:{71,76}] wire [2:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [16:0] _is_aligned_T = {14'h0, io_in_a_bits_address_0[2:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 17'h0; // @[Edges.scala:21:{16,24}] wire [2:0] _mask_sizeOH_T = {1'h0, io_in_a_bits_size_0}; // @[Misc.scala:202:34] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = &io_in_a_bits_size_0; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [10:0] uncommonBits = _uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_1 = _uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_2 = _uncommonBits_T_2; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_3 = _uncommonBits_T_3; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_4 = _uncommonBits_T_4; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_5 = _uncommonBits_T_5; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_6 = _uncommonBits_T_6; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_7 = _uncommonBits_T_7; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_8 = _uncommonBits_T_8; // @[Parameters.scala:52:{29,56}] wire [10:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_10 = source_ok_uncommonBits_1 < 11'h410; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_11 = _source_ok_T_10; // @[Parameters.scala:56:48, :57:20] wire _source_ok_WIRE_1_0 = _source_ok_T_11; // @[Parameters.scala:1138:31] wire _T_659 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_659; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_659; // @[Decoupled.scala:51:35] wire a_first_done = _a_first_T; // @[Decoupled.scala:51:35] wire [2:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] reg a_first_counter; // @[Edges.scala:229:27] wire _a_first_last_T = a_first_counter; // @[Edges.scala:229:27, :232:25] wire [1:0] _a_first_counter1_T = {1'h0, a_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28] wire a_first_counter1 = _a_first_counter1_T[0]; // @[Edges.scala:230:28] wire a_first = ~a_first_counter; // @[Edges.scala:229:27, :231:25] wire _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire _a_first_counter_T = ~a_first & a_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [1:0] size; // @[Monitor.scala:389:22] reg [10:0] source; // @[Monitor.scala:390:22] reg [16:0] address; // @[Monitor.scala:391:22] wire _T_727 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_727; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_727; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_727; // @[Decoupled.scala:51:35] wire d_first_done = _d_first_T; // @[Decoupled.scala:51:35] wire [5:0] _GEN_0 = 6'h7 << io_in_d_bits_size_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [2:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] reg d_first_counter; // @[Edges.scala:229:27] wire _d_first_last_T = d_first_counter; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T = {1'h0, d_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1 = _d_first_counter1_T[0]; // @[Edges.scala:230:28] wire d_first = ~d_first_counter; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T = ~d_first & d_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [1:0] size_1; // @[Monitor.scala:540:22] reg [10:0] source_1; // @[Monitor.scala:541:22] reg [1039:0] inflight; // @[Monitor.scala:614:27] reg [4159:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [4159:0] inflight_sizes; // @[Monitor.scala:618:33] wire a_first_done_1 = _a_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] reg a_first_counter_1; // @[Edges.scala:229:27] wire _a_first_last_T_2 = a_first_counter_1; // @[Edges.scala:229:27, :232:25] wire [1:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28] wire a_first_counter1_1 = _a_first_counter1_T_1[0]; // @[Edges.scala:230:28] wire a_first_1 = ~a_first_counter_1; // @[Edges.scala:229:27, :231:25] wire _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire _a_first_counter_T_1 = ~a_first_1 & a_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21] wire d_first_done_1 = _d_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] reg d_first_counter_1; // @[Edges.scala:229:27] wire _d_first_last_T_2 = d_first_counter_1; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1_1 = _d_first_counter1_T_1[0]; // @[Edges.scala:230:28] wire d_first_1 = ~d_first_counter_1; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T_1 = ~d_first_1 & d_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21] wire [1039:0] a_set; // @[Monitor.scala:626:34] wire [1039:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [4159:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [4159:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [13:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [13:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [13:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :641:65] wire [13:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [13:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :681:99] wire [13:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [13:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :750:67] wire [13:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [13:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :791:99] wire [4159:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [4159:0] _a_opcode_lookup_T_6 = {4156'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [4159:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[4159:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [3:0] a_size_lookup; // @[Monitor.scala:639:33] wire [4159:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [4159:0] _a_size_lookup_T_6 = {4156'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}] wire [4159:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[4159:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [2:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [2047:0] _GEN_2 = 2048'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [2047:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_2; // @[OneHot.scala:58:35] wire [2047:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_2; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[1039:0] : 1040'h0; // @[OneHot.scala:58:35] wire _T_592 = _T_659 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_592 ? _a_set_T[1039:0] : 1040'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_592 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [2:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [2:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[2:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_592 ? _a_sizes_set_interm_T_1 : 3'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [13:0] _GEN_3 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [13:0] _a_opcodes_set_T; // @[Monitor.scala:659:79] assign _a_opcodes_set_T = _GEN_3; // @[Monitor.scala:659:79] wire [13:0] _a_sizes_set_T; // @[Monitor.scala:660:77] assign _a_sizes_set_T = _GEN_3; // @[Monitor.scala:659:79, :660:77] wire [16386:0] _a_opcodes_set_T_1 = {16383'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_592 ? _a_opcodes_set_T_1[4159:0] : 4160'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [16385:0] _a_sizes_set_T_1 = {16383'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_592 ? _a_sizes_set_T_1[4159:0] : 4160'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [1039:0] d_clr; // @[Monitor.scala:664:34] wire [1039:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [4159:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [4159:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _T_638 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [2047:0] _GEN_4 = 2048'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [2047:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_4; // @[OneHot.scala:58:35] wire [2047:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_4; // @[OneHot.scala:58:35] wire [2047:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_4; // @[OneHot.scala:58:35] wire [2047:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_4; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_638 ? _d_clr_wo_ready_T[1039:0] : 1040'h0; // @[OneHot.scala:58:35] wire _T_605 = _T_727 & d_first_1; // @[Decoupled.scala:51:35] assign d_clr = _T_605 ? _d_clr_T[1039:0] : 1040'h0; // @[OneHot.scala:58:35] wire [16398:0] _d_opcodes_clr_T_5 = 16399'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_605 ? _d_opcodes_clr_T_5[4159:0] : 4160'h0; // @[Monitor.scala:668:33, :678:{25,89}, :680:{21,76}] wire [16398:0] _d_sizes_clr_T_5 = 16399'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_605 ? _d_sizes_clr_T_5[4159:0] : 4160'h0; // @[Monitor.scala:670:31, :678:{25,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [1039:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [1039:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [1039:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [4159:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [4159:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [4159:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [4159:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [4159:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [4159:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [1039:0] inflight_1; // @[Monitor.scala:726:35] wire [1039:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [4159:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [4159:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [4159:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [4159:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire d_first_done_2 = _d_first_T_2; // @[Decoupled.scala:51:35] wire [2:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] reg d_first_counter_2; // @[Edges.scala:229:27] wire _d_first_last_T_4 = d_first_counter_2; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1_2 = _d_first_counter1_T_2[0]; // @[Edges.scala:230:28] wire d_first_2 = ~d_first_counter_2; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T_2 = ~d_first_2 & d_first_counter1_2; // @[Edges.scala:230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [3:0] c_size_lookup; // @[Monitor.scala:748:35] wire [4159:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [4159:0] _c_opcode_lookup_T_6 = {4156'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [4159:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[4159:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [4159:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [4159:0] _c_size_lookup_T_6 = {4156'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}] wire [4159:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[4159:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [16398:0] _d_opcodes_clr_T_11 = 16399'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] wire [16398:0] _d_sizes_clr_T_11 = 16399'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 11'h0; // @[Monitor.scala:36:7, :795:113] wire [1039:0] _inflight_T_5 = _inflight_T_3; // @[Monitor.scala:814:{35,44}] wire [4159:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3; // @[Monitor.scala:815:{43,60}] wire [4159:0] _inflight_sizes_T_5 = _inflight_sizes_T_3; // @[Monitor.scala:816:{41,56}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]

Generate the Verilog code corresponding to the following Chisel files. File EgressUnit.scala: package constellation.router import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.{Field, Parameters} import freechips.rocketchip.util._ import constellation.channel._ import constellation.routing.{FlowRoutingBundle} class EgressUnit(coupleSAVA: Boolean, combineSAST: Boolean, inParams: Seq[ChannelParams], ingressParams: Seq[IngressChannelParams], cParam: EgressChannelParams) (implicit p: Parameters) extends AbstractOutputUnit(inParams, ingressParams, cParam)(p) { class EgressUnitIO extends AbstractOutputUnitIO(inParams, ingressParams, cParam) { val out = Decoupled(new EgressFlit(cParam.payloadBits)) } val io = IO(new EgressUnitIO) val channel_empty = RegInit(true.B) val flow = Reg(new FlowRoutingBundle) val q = Module(new Queue(new EgressFlit(cParam.payloadBits), 3 - (if (combineSAST) 1 else 0), flow=true)) q.io.enq.valid := io.in(0).valid q.io.enq.bits.head := io.in(0).bits.head q.io.enq.bits.tail := io.in(0).bits.tail val flows = cParam.possibleFlows.toSeq if (flows.size == 0) { q.io.enq.bits.ingress_id := 0.U(1.W) } else { q.io.enq.bits.ingress_id := Mux1H( flows.map(f => (f.ingressNode.U === io.in(0).bits.flow.ingress_node && f.ingressNodeId.U === io.in(0).bits.flow.ingress_node_id)), flows.map(f => f.ingressId.U(ingressIdBits.W)) ) } q.io.enq.bits.payload := io.in(0).bits.payload io.out <> q.io.deq assert(!(q.io.enq.valid && !q.io.enq.ready)) io.credit_available(0) := q.io.count === 0.U io.channel_status(0).occupied := !channel_empty io.channel_status(0).flow := flow when (io.credit_alloc(0).alloc && io.credit_alloc(0).tail) { channel_empty := true.B if (coupleSAVA) io.channel_status(0).occupied := false.B } when (io.allocs(0).alloc) { channel_empty := false.B flow := io.allocs(0).flow } }

module EgressUnit_15( // @[EgressUnit.scala:12:7] input clock, // @[EgressUnit.scala:12:7] input reset, // @[EgressUnit.scala:12:7] input io_in_0_valid, // @[EgressUnit.scala:18:14] input io_in_0_bits_head, // @[EgressUnit.scala:18:14] input io_in_0_bits_tail, // @[EgressUnit.scala:18:14] input [72:0] io_in_0_bits_payload, // @[EgressUnit.scala:18:14] input [3:0] io_in_0_bits_flow_ingress_node, // @[EgressUnit.scala:18:14] input [2:0] io_in_0_bits_flow_ingress_node_id, // @[EgressUnit.scala:18:14] output io_credit_available_0, // @[EgressUnit.scala:18:14] output io_channel_status_0_occupied, // @[EgressUnit.scala:18:14] input io_allocs_0_alloc, // @[EgressUnit.scala:18:14] input io_credit_alloc_0_alloc, // @[EgressUnit.scala:18:14] input io_credit_alloc_0_tail, // @[EgressUnit.scala:18:14] output io_out_valid, // @[EgressUnit.scala:18:14] output io_out_bits_head, // @[EgressUnit.scala:18:14] output io_out_bits_tail, // @[EgressUnit.scala:18:14] output [72:0] io_out_bits_payload // @[EgressUnit.scala:18:14] ); wire _q_io_enq_ready; // @[EgressUnit.scala:22:17] wire [1:0] _q_io_count; // @[EgressUnit.scala:22:17] reg channel_empty; // @[EgressUnit.scala:20:30] wire _q_io_enq_bits_ingress_id_T_10 = io_in_0_bits_flow_ingress_node_id == 3'h2; // @[EgressUnit.scala:32:27]

Generate the Verilog code corresponding to the following Chisel files. File PMA.scala: // See LICENSE.SiFive for license details. // See LICENSE.Berkeley for license details. package freechips.rocketchip.rocket import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config._ import freechips.rocketchip.devices.debug.DebugModuleKey import freechips.rocketchip.diplomacy.RegionType import freechips.rocketchip.subsystem.CacheBlockBytes import freechips.rocketchip.tile.{CoreModule, CoreBundle} import freechips.rocketchip.tilelink.{TLSlavePortParameters, TLManagerParameters} class PMAChecker(manager: TLSlavePortParameters)(implicit p: Parameters) extends CoreModule()(p) { val io = IO(new Bundle { val paddr = Input(UInt()) val resp = Output(new Bundle { val cacheable = Bool() val r = Bool() val w = Bool() val pp = Bool() val al = Bool() val aa = Bool() val x = Bool() val eff = Bool() }) }) // PMA // check exist a slave can consume this address. val legal_address = manager.findSafe(io.paddr).reduce(_||_) // check utility to help check SoC property. def fastCheck(member: TLManagerParameters => Boolean) = legal_address && manager.fastProperty(io.paddr, member, (b:Boolean) => b.B) io.resp.cacheable := fastCheck(_.supportsAcquireB) io.resp.r := fastCheck(_.supportsGet) io.resp.w := fastCheck(_.supportsPutFull) io.resp.pp := fastCheck(_.supportsPutPartial) io.resp.al := fastCheck(_.supportsLogical) io.resp.aa := fastCheck(_.supportsArithmetic) io.resp.x := fastCheck(_.executable) io.resp.eff := fastCheck(Seq(RegionType.PUT_EFFECTS, RegionType.GET_EFFECTS) contains _.regionType) } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.diplomacy import chisel3._ import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor} import freechips.rocketchip.util.ShiftQueue /** Options for describing the attributes of memory regions */ object RegionType { // Define the 'more relaxed than' ordering val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS) sealed trait T extends Ordered[T] { def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this) } case object CACHED extends T // an intermediate agent may have cached a copy of the region for you case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively } // A non-empty half-open range; [start, end) case class IdRange(start: Int, end: Int) extends Ordered[IdRange] { require (start >= 0, s"Ids cannot be negative, but got: $start.") require (start <= end, "Id ranges cannot be negative.") def compare(x: IdRange) = { val primary = (this.start - x.start).signum val secondary = (x.end - this.end).signum if (primary != 0) primary else secondary } def overlaps(x: IdRange) = start < x.end && x.start < end def contains(x: IdRange) = start <= x.start && x.end <= end def contains(x: Int) = start <= x && x < end def contains(x: UInt) = if (size == 0) { false.B } else if (size == 1) { // simple comparison x === start.U } else { // find index of largest different bit val largestDeltaBit = log2Floor(start ^ (end-1)) val smallestCommonBit = largestDeltaBit + 1 // may not exist in x val uncommonMask = (1 << smallestCommonBit) - 1 val uncommonBits = (x | 0.U(smallestCommonBit.W))(largestDeltaBit, 0) // the prefix must match exactly (note: may shift ALL bits away) (x >> smallestCommonBit) === (start >> smallestCommonBit).U && // firrtl constant prop range analysis can eliminate these two: (start & uncommonMask).U <= uncommonBits && uncommonBits <= ((end-1) & uncommonMask).U } def shift(x: Int) = IdRange(start+x, end+x) def size = end - start def isEmpty = end == start def range = start until end } object IdRange { def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else { val ranges = s.sorted (ranges.tail zip ranges.init) find { case (a, b) => a overlaps b } } } // An potentially empty inclusive range of 2-powers [min, max] (in bytes) case class TransferSizes(min: Int, max: Int) { def this(x: Int) = this(x, x) require (min <= max, s"Min transfer $min > max transfer $max") require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)") require (max == 0 || isPow2(max), s"TransferSizes must be a power of 2, got: $max") require (min == 0 || isPow2(min), s"TransferSizes must be a power of 2, got: $min") require (max == 0 || min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)") def none = min == 0 def contains(x: Int) = isPow2(x) && min <= x && x <= max def containsLg(x: Int) = contains(1 << x) def containsLg(x: UInt) = if (none) false.B else if (min == max) { log2Ceil(min).U === x } else { log2Ceil(min).U <= x && x <= log2Ceil(max).U } def contains(x: TransferSizes) = x.none || (min <= x.min && x.max <= max) def intersect(x: TransferSizes) = if (x.max < min || max < x.min) TransferSizes.none else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max)) // Not a union, because the result may contain sizes contained by neither term // NOT TO BE CONFUSED WITH COVERPOINTS def mincover(x: TransferSizes) = { if (none) { x } else if (x.none) { this } else { TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max)) } } override def toString() = "TransferSizes[%d, %d]".format(min, max) } object TransferSizes { def apply(x: Int) = new TransferSizes(x) val none = new TransferSizes(0) def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _) def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _) implicit def asBool(x: TransferSizes) = !x.none } // AddressSets specify the address space managed by the manager // Base is the base address, and mask are the bits consumed by the manager // e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff // e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ... case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet] { // Forbid misaligned base address (and empty sets) require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}") require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous // We do allow negative mask (=> ignore all high bits) def contains(x: BigInt) = ((x ^ base) & ~mask) == 0 def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S // turn x into an address contained in this set def legalize(x: UInt): UInt = base.U | (mask.U & x) // overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1) def overlaps(x: AddressSet) = (~(mask | x.mask) & (base ^ x.base)) == 0 // contains iff bitwise: x.mask => mask && contains(x.base) def contains(x: AddressSet) = ((x.mask | (base ^ x.base)) & ~mask) == 0 // The number of bytes to which the manager must be aligned def alignment = ((mask + 1) & ~mask) // Is this a contiguous memory range def contiguous = alignment == mask+1 def finite = mask >= 0 def max = { require (finite, "Max cannot be calculated on infinite mask"); base | mask } // Widen the match function to ignore all bits in imask def widen(imask: BigInt) = AddressSet(base & ~imask, mask | imask) // Return an AddressSet that only contains the addresses both sets contain def intersect(x: AddressSet): Option[AddressSet] = { if (!overlaps(x)) { None } else { val r_mask = mask & x.mask val r_base = base | x.base Some(AddressSet(r_base, r_mask)) } } def subtract(x: AddressSet): Seq[AddressSet] = { intersect(x) match { case None => Seq(this) case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit => val nmask = (mask & (bit-1)) | remove.mask val nbase = (remove.base ^ bit) & ~nmask AddressSet(nbase, nmask) } } } // AddressSets have one natural Ordering (the containment order, if contiguous) def compare(x: AddressSet) = { val primary = (this.base - x.base).signum // smallest address first val secondary = (x.mask - this.mask).signum // largest mask first if (primary != 0) primary else secondary } // We always want to see things in hex override def toString() = { if (mask >= 0) { "AddressSet(0x%x, 0x%x)".format(base, mask) } else { "AddressSet(0x%x, ~0x%x)".format(base, ~mask) } } def toRanges = { require (finite, "Ranges cannot be calculated on infinite mask") val size = alignment val fragments = mask & ~(size-1) val bits = bitIndexes(fragments) (BigInt(0) until (BigInt(1) << bits.size)).map { i => val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) } AddressRange(off, size) } } } object AddressSet { val everything = AddressSet(0, -1) def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = { if (size == 0) tail.reverse else { val maxBaseAlignment = base & (-base) // 0 for infinite (LSB) val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size val step = if (maxBaseAlignment == 0 || maxBaseAlignment > maxSizeAlignment) maxSizeAlignment else maxBaseAlignment misaligned(base+step, size-step, AddressSet(base, step-1) +: tail) } } def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = { // Pair terms up by ignoring 'bit' seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) => if (seq.size == 1) { seq.head // singleton -> unaffected } else { key.copy(mask = key.mask | bit) // pair - widen mask by bit } }.toList } def unify(seq: Seq[AddressSet]): Seq[AddressSet] = { val bits = seq.map(_.base).foldLeft(BigInt(0))(_ | _) AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted } def enumerateMask(mask: BigInt): Seq[BigInt] = { def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] = if (id == mask) (id +: tail).reverse else helper(((~mask | id) + 1) & mask, id +: tail) helper(0, Nil) } def enumerateBits(mask: BigInt): Seq[BigInt] = { def helper(x: BigInt): Seq[BigInt] = { if (x == 0) { Nil } else { val bit = x & (-x) bit +: helper(x & ~bit) } } helper(mask) } } case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean) { require (depth >= 0, "Buffer depth must be >= 0") def isDefined = depth > 0 def latency = if (isDefined && !flow) 1 else 0 def apply[T <: Data](x: DecoupledIO[T]) = if (isDefined) Queue(x, depth, flow=flow, pipe=pipe) else x def irrevocable[T <: Data](x: ReadyValidIO[T]) = if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe) else x def sq[T <: Data](x: DecoupledIO[T]) = if (!isDefined) x else { val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe)) sq.io.enq <> x sq.io.deq } override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "") } object BufferParams { implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false) val default = BufferParams(2) val none = BufferParams(0) val flow = BufferParams(1, true, false) val pipe = BufferParams(1, false, true) } case class TriStateValue(value: Boolean, set: Boolean) { def update(orig: Boolean) = if (set) value else orig } object TriStateValue { implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true) def unset = TriStateValue(false, false) } trait DirectedBuffers[T] { def copyIn(x: BufferParams): T def copyOut(x: BufferParams): T def copyInOut(x: BufferParams): T } trait IdMapEntry { def name: String def from: IdRange def to: IdRange def isCache: Boolean def requestFifo: Boolean def maxTransactionsInFlight: Option[Int] def pretty(fmt: String) = if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5 fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } else { fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } } abstract class IdMap[T <: IdMapEntry] { protected val fmt: String val mapping: Seq[T] def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n") }

module PMAChecker_2( // @[PMA.scala:18:7] input clock, // @[PMA.scala:18:7] input reset, // @[PMA.scala:18:7] input [48:0] io_paddr, // @[PMA.scala:19:14] output io_resp_cacheable, // @[PMA.scala:19:14] output io_resp_r, // @[PMA.scala:19:14] output io_resp_w, // @[PMA.scala:19:14] output io_resp_pp, // @[PMA.scala:19:14] output io_resp_al, // @[PMA.scala:19:14] output io_resp_aa, // @[PMA.scala:19:14] output io_resp_x, // @[PMA.scala:19:14] output io_resp_eff // @[PMA.scala:19:14] ); wire [48:0] io_paddr_0 = io_paddr; // @[PMA.scala:18:7] wire [49:0] _io_resp_r_T_2 = 50'h0; // @[Parameters.scala:137:46] wire [49:0] _io_resp_r_T_3 = 50'h0; // @[Parameters.scala:137:46] wire _io_resp_r_T_4 = 1'h1; // @[Parameters.scala:137:59] wire _io_resp_cacheable_T_28 = 1'h0; // @[Mux.scala:30:73] wire _io_resp_w_T_47 = 1'h0; // @[Mux.scala:30:73] wire _io_resp_pp_T_47 = 1'h0; // @[Mux.scala:30:73] wire _io_resp_al_T_47 = 1'h0; // @[Mux.scala:30:73] wire _io_resp_aa_T_47 = 1'h0; // @[Mux.scala:30:73] wire _io_resp_x_T_65 = 1'h0; // @[Mux.scala:30:73] wire _io_resp_eff_T_59 = 1'h0; // @[Mux.scala:30:73] wire [48:0] _legal_address_T = io_paddr_0; // @[PMA.scala:18:7] wire [48:0] _io_resp_cacheable_T = io_paddr_0; // @[PMA.scala:18:7] wire _io_resp_cacheable_T_31; // @[PMA.scala:39:19] wire [48:0] _io_resp_r_T = io_paddr_0; // @[PMA.scala:18:7] wire [48:0] _io_resp_w_T = io_paddr_0; // @[PMA.scala:18:7] wire [48:0] _io_resp_pp_T = io_paddr_0; // @[PMA.scala:18:7] wire [48:0] _io_resp_al_T = io_paddr_0; // @[PMA.scala:18:7] wire [48:0] _io_resp_aa_T = io_paddr_0; // @[PMA.scala:18:7] wire [48:0] _io_resp_x_T = io_paddr_0; // @[PMA.scala:18:7] wire [48:0] _io_resp_eff_T = io_paddr_0; // @[PMA.scala:18:7] wire _io_resp_r_T_5; // @[PMA.scala:39:19] wire _io_resp_w_T_49; // @[PMA.scala:39:19] wire _io_resp_pp_T_49; // @[PMA.scala:39:19] wire _io_resp_al_T_49; // @[PMA.scala:39:19] wire _io_resp_aa_T_49; // @[PMA.scala:39:19] wire _io_resp_x_T_67; // @[PMA.scala:39:19] wire _io_resp_eff_T_61; // @[PMA.scala:39:19] wire io_resp_cacheable_0; // @[PMA.scala:18:7] wire io_resp_r_0; // @[PMA.scala:18:7] wire io_resp_w_0; // @[PMA.scala:18:7] wire io_resp_pp_0; // @[PMA.scala:18:7] wire io_resp_al_0; // @[PMA.scala:18:7] wire io_resp_aa_0; // @[PMA.scala:18:7] wire io_resp_x_0; // @[PMA.scala:18:7] wire io_resp_eff_0; // @[PMA.scala:18:7] wire [49:0] _legal_address_T_1 = {1'h0, _legal_address_T}; // @[Parameters.scala:137:{31,41}] wire [49:0] _legal_address_T_2 = _legal_address_T_1 & 50'h3FFFFFFFFF000; // @[Parameters.scala:137:{41,46}] wire [49:0] _legal_address_T_3 = _legal_address_T_2; // @[Parameters.scala:137:46] wire _legal_address_T_4 = _legal_address_T_3 == 50'h0; // @[Parameters.scala:137:{46,59}] wire _legal_address_WIRE_0 = _legal_address_T_4; // @[Parameters.scala:612:40] wire [48:0] _GEN = {io_paddr_0[48:13], io_paddr_0[12:0] ^ 13'h1000}; // @[PMA.scala:18:7] wire [48:0] _legal_address_T_5; // @[Parameters.scala:137:31] assign _legal_address_T_5 = _GEN; // @[Parameters.scala:137:31] wire [48:0] _io_resp_x_T_29; // @[Parameters.scala:137:31] assign _io_resp_x_T_29 = _GEN; // @[Parameters.scala:137:31] wire [49:0] _legal_address_T_6 = {1'h0, _legal_address_T_5}; // @[Parameters.scala:137:{31,41}] wire [49:0] _legal_address_T_7 = _legal_address_T_6 & 50'h3FFFFFFFFF000; // @[Parameters.scala:137:{41,46}] wire [49:0] _legal_address_T_8 = _legal_address_T_7; // @[Parameters.scala:137:46] wire _legal_address_T_9 = _legal_address_T_8 == 50'h0; // @[Parameters.scala:137:{46,59}] wire _legal_address_WIRE_1 = _legal_address_T_9; // @[Parameters.scala:612:40] wire [48:0] _GEN_0 = {io_paddr_0[48:14], io_paddr_0[13:0] ^ 14'h3000}; // @[PMA.scala:18:7] wire [48:0] _legal_address_T_10; // @[Parameters.scala:137:31] assign _legal_address_T_10 = _GEN_0; // @[Parameters.scala:137:31] wire [48:0] _io_resp_x_T_5; // @[Parameters.scala:137:31] assign _io_resp_x_T_5 = _GEN_0; // @[Parameters.scala:137:31] wire [48:0] _io_resp_eff_T_35; // @[Parameters.scala:137:31] assign _io_resp_eff_T_35 = _GEN_0; // @[Parameters.scala:137:31] wire [49:0] _legal_address_T_11 = {1'h0, _legal_address_T_10}; // @[Parameters.scala:137:{31,41}] wire [49:0] _legal_address_T_12 = _legal_address_T_11 & 50'h3FFFFFFFFF000; // @[Parameters.scala:137:{41,46}] wire [49:0] _legal_address_T_13 = _legal_address_T_12; // @[Parameters.scala:137:46] wire _legal_address_T_14 = _legal_address_T_13 == 50'h0; // @[Parameters.scala:137:{46,59}] wire _legal_address_WIRE_2 = _legal_address_T_14; // @[Parameters.scala:612:40] wire [48:0] _GEN_1 = {io_paddr_0[48:17], io_paddr_0[16:0] ^ 17'h10000}; // @[PMA.scala:18:7] wire [48:0] _legal_address_T_15; // @[Parameters.scala:137:31] assign _legal_address_T_15 = _GEN_1; // @[Parameters.scala:137:31] wire [48:0] _io_resp_cacheable_T_5; // @[Parameters.scala:137:31] assign _io_resp_cacheable_T_5 = _GEN_1; // @[Parameters.scala:137:31] wire [48:0] _io_resp_w_T_41; // @[Parameters.scala:137:31] assign _io_resp_w_T_41 = _GEN_1; // @[Parameters.scala:137:31] wire [48:0] _io_resp_pp_T_41; // @[Parameters.scala:137:31] assign _io_resp_pp_T_41 = _GEN_1; // @[Parameters.scala:137:31] wire [48:0] _io_resp_al_T_41; // @[Parameters.scala:137:31] assign _io_resp_al_T_41 = _GEN_1; // @[Parameters.scala:137:31] wire [48:0] _io_resp_aa_T_41; // @[Parameters.scala:137:31] assign _io_resp_aa_T_41 = _GEN_1; // @[Parameters.scala:137:31] wire [48:0] _io_resp_x_T_10; // @[Parameters.scala:137:31] assign _io_resp_x_T_10 = _GEN_1; // @[Parameters.scala:137:31] wire [48:0] _io_resp_eff_T_40; // @[Parameters.scala:137:31] assign _io_resp_eff_T_40 = _GEN_1; // @[Parameters.scala:137:31] wire [49:0] _legal_address_T_16 = {1'h0, _legal_address_T_15}; // @[Parameters.scala:137:{31,41}] wire [49:0] _legal_address_T_17 = _legal_address_T_16 & 50'h3FFFFFFFF0000; // @[Parameters.scala:137:{41,46}] wire [49:0] _legal_address_T_18 = _legal_address_T_17; // @[Parameters.scala:137:46] wire _legal_address_T_19 = _legal_address_T_18 == 50'h0; // @[Parameters.scala:137:{46,59}] wire _legal_address_WIRE_3 = _legal_address_T_19; // @[Parameters.scala:612:40] wire [48:0] _GEN_2 = {io_paddr_0[48:21], io_paddr_0[20:0] ^ 21'h100000}; // @[PMA.scala:18:7] wire [48:0] _legal_address_T_20; // @[Parameters.scala:137:31] assign _legal_address_T_20 = _GEN_2; // @[Parameters.scala:137:31] wire [48:0] _io_resp_w_T_5; // @[Parameters.scala:137:31] assign _io_resp_w_T_5 = _GEN_2; // @[Parameters.scala:137:31] wire [48:0] _io_resp_pp_T_5; // @[Parameters.scala:137:31] assign _io_resp_pp_T_5 = _GEN_2; // @[Parameters.scala:137:31] wire [48:0] _io_resp_al_T_5; // @[Parameters.scala:137:31] assign _io_resp_al_T_5 = _GEN_2; // @[Parameters.scala:137:31] wire [48:0] _io_resp_aa_T_5; // @[Parameters.scala:137:31] assign _io_resp_aa_T_5 = _GEN_2; // @[Parameters.scala:137:31] wire [48:0] _io_resp_x_T_34; // @[Parameters.scala:137:31] assign _io_resp_x_T_34 = _GEN_2; // @[Parameters.scala:137:31] wire [48:0] _io_resp_eff_T_5; // @[Parameters.scala:137:31] assign _io_resp_eff_T_5 = _GEN_2; // @[Parameters.scala:137:31] wire [49:0] _legal_address_T_21 = {1'h0, _legal_address_T_20}; // @[Parameters.scala:137:{31,41}] wire [49:0] _legal_address_T_22 = _legal_address_T_21 & 50'h3FFFFFFFFF000; // @[Parameters.scala:137:{41,46}] wire [49:0] _legal_address_T_23 = _legal_address_T_22; // @[Parameters.scala:137:46] wire _legal_address_T_24 = _legal_address_T_23 == 50'h0; // @[Parameters.scala:137:{46,59}] wire _legal_address_WIRE_4 = _legal_address_T_24; // @[Parameters.scala:612:40] wire [48:0] _legal_address_T_25 = {io_paddr_0[48:21], io_paddr_0[20:0] ^ 21'h110000}; // @[PMA.scala:18:7] wire [49:0] _legal_address_T_26 = {1'h0, _legal_address_T_25}; // @[Parameters.scala:137:{31,41}] wire [49:0] _legal_address_T_27 = _legal_address_T_26 & 50'h3FFFFFFFFF000; // @[Parameters.scala:137:{41,46}] wire [49:0] _legal_address_T_28 = _legal_address_T_27; // @[Parameters.scala:137:46] wire _legal_address_T_29 = _legal_address_T_28 == 50'h0; // @[Parameters.scala:137:{46,59}] wire _legal_address_WIRE_5 = _legal_address_T_29; // @[Parameters.scala:612:40] wire [48:0] _GEN_3 = {io_paddr_0[48:26], io_paddr_0[25:0] ^ 26'h2000000}; // @[PMA.scala:18:7] wire [48:0] _legal_address_T_30; // @[Parameters.scala:137:31] assign _legal_address_T_30 = _GEN_3; // @[Parameters.scala:137:31] wire [48:0] _io_resp_x_T_39; // @[Parameters.scala:137:31] assign _io_resp_x_T_39 = _GEN_3; // @[Parameters.scala:137:31] wire [48:0] _io_resp_eff_T_10; // @[Parameters.scala:137:31] assign _io_resp_eff_T_10 = _GEN_3; // @[Parameters.scala:137:31] wire [49:0] _legal_address_T_31 = {1'h0, _legal_address_T_30}; // @[Parameters.scala:137:{31,41}] wire [49:0] _legal_address_T_32 = _legal_address_T_31 & 50'h3FFFFFFFF0000; // @[Parameters.scala:137:{41,46}] wire [49:0] _legal_address_T_33 = _legal_address_T_32; // @[Parameters.scala:137:46] wire _legal_address_T_34 = _legal_address_T_33 == 50'h0; // @[Parameters.scala:137:{46,59}] wire _legal_address_WIRE_6 = _legal_address_T_34; // @[Parameters.scala:612:40] wire [48:0] _GEN_4 = {io_paddr_0[48:26], io_paddr_0[25:0] ^ 26'h2010000}; // @[PMA.scala:18:7] wire [48:0] _legal_address_T_35; // @[Parameters.scala:137:31] assign _legal_address_T_35 = _GEN_4; // @[Parameters.scala:137:31] wire [48:0] _io_resp_w_T_10; // @[Parameters.scala:137:31] assign _io_resp_w_T_10 = _GEN_4; // @[Parameters.scala:137:31] wire [48:0] _io_resp_pp_T_10; // @[Parameters.scala:137:31] assign _io_resp_pp_T_10 = _GEN_4; // @[Parameters.scala:137:31] wire [48:0] _io_resp_al_T_10; // @[Parameters.scala:137:31] assign _io_resp_al_T_10 = _GEN_4; // @[Parameters.scala:137:31] wire [48:0] _io_resp_aa_T_10; // @[Parameters.scala:137:31] assign _io_resp_aa_T_10 = _GEN_4; // @[Parameters.scala:137:31] wire [48:0] _io_resp_x_T_44; // @[Parameters.scala:137:31] assign _io_resp_x_T_44 = _GEN_4; // @[Parameters.scala:137:31] wire [48:0] _io_resp_eff_T_15; // @[Parameters.scala:137:31] assign _io_resp_eff_T_15 = _GEN_4; // @[Parameters.scala:137:31] wire [49:0] _legal_address_T_36 = {1'h0, _legal_address_T_35}; // @[Parameters.scala:137:{31,41}] wire [49:0] _legal_address_T_37 = _legal_address_T_36 & 50'h3FFFFFFFFF000; // @[Parameters.scala:137:{41,46}] wire [49:0] _legal_address_T_38 = _legal_address_T_37; // @[Parameters.scala:137:46] wire _legal_address_T_39 = _legal_address_T_38 == 50'h0; // @[Parameters.scala:137:{46,59}] wire _legal_address_WIRE_7 = _legal_address_T_39; // @[Parameters.scala:612:40] wire [48:0] _GEN_5 = {io_paddr_0[48:28], io_paddr_0[27:0] ^ 28'h8000000}; // @[PMA.scala:18:7] wire [48:0] _legal_address_T_40; // @[Parameters.scala:137:31] assign _legal_address_T_40 = _GEN_5; // @[Parameters.scala:137:31] wire [48:0] _io_resp_cacheable_T_17; // @[Parameters.scala:137:31] assign _io_resp_cacheable_T_17 = _GEN_5; // @[Parameters.scala:137:31] wire [48:0] _io_resp_w_T_15; // @[Parameters.scala:137:31] assign _io_resp_w_T_15 = _GEN_5; // @[Parameters.scala:137:31] wire [48:0] _io_resp_w_T_20; // @[Parameters.scala:137:31] assign _io_resp_w_T_20 = _GEN_5; // @[Parameters.scala:137:31] wire [48:0] _io_resp_pp_T_15; // @[Parameters.scala:137:31] assign _io_resp_pp_T_15 = _GEN_5; // @[Parameters.scala:137:31] wire [48:0] _io_resp_pp_T_20; // @[Parameters.scala:137:31] assign _io_resp_pp_T_20 = _GEN_5; // @[Parameters.scala:137:31] wire [48:0] _io_resp_al_T_15; // @[Parameters.scala:137:31] assign _io_resp_al_T_15 = _GEN_5; // @[Parameters.scala:137:31] wire [48:0] _io_resp_al_T_20; // @[Parameters.scala:137:31] assign _io_resp_al_T_20 = _GEN_5; // @[Parameters.scala:137:31] wire [48:0] _io_resp_aa_T_15; // @[Parameters.scala:137:31] assign _io_resp_aa_T_15 = _GEN_5; // @[Parameters.scala:137:31] wire [48:0] _io_resp_aa_T_20; // @[Parameters.scala:137:31] assign _io_resp_aa_T_20 = _GEN_5; // @[Parameters.scala:137:31] wire [48:0] _io_resp_x_T_15; // @[Parameters.scala:137:31] assign _io_resp_x_T_15 = _GEN_5; // @[Parameters.scala:137:31] wire [48:0] _io_resp_eff_T_45; // @[Parameters.scala:137:31] assign _io_resp_eff_T_45 = _GEN_5; // @[Parameters.scala:137:31] wire [49:0] _legal_address_T_41 = {1'h0, _legal_address_T_40}; // @[Parameters.scala:137:{31,41}] wire [49:0] _legal_address_T_42 = _legal_address_T_41 & 50'h3FFFFFFFF0000; // @[Parameters.scala:137:{41,46}] wire [49:0] _legal_address_T_43 = _legal_address_T_42; // @[Parameters.scala:137:46] wire _legal_address_T_44 = _legal_address_T_43 == 50'h0; // @[Parameters.scala:137:{46,59}] wire _legal_address_WIRE_8 = _legal_address_T_44; // @[Parameters.scala:612:40] wire [48:0] _GEN_6 = {io_paddr_0[48:28], io_paddr_0[27:0] ^ 28'hC000000}; // @[PMA.scala:18:7] wire [48:0] _legal_address_T_45; // @[Parameters.scala:137:31] assign _legal_address_T_45 = _GEN_6; // @[Parameters.scala:137:31] wire [48:0] _io_resp_cacheable_T_10; // @[Parameters.scala:137:31] assign _io_resp_cacheable_T_10 = _GEN_6; // @[Parameters.scala:137:31] wire [48:0] _io_resp_x_T_49; // @[Parameters.scala:137:31] assign _io_resp_x_T_49 = _GEN_6; // @[Parameters.scala:137:31] wire [48:0] _io_resp_eff_T_20; // @[Parameters.scala:137:31] assign _io_resp_eff_T_20 = _GEN_6; // @[Parameters.scala:137:31] wire [49:0] _legal_address_T_46 = {1'h0, _legal_address_T_45}; // @[Parameters.scala:137:{31,41}] wire [49:0] _legal_address_T_47 = _legal_address_T_46 & 50'h3FFFFFC000000; // @[Parameters.scala:137:{41,46}] wire [49:0] _legal_address_T_48 = _legal_address_T_47; // @[Parameters.scala:137:46] wire _legal_address_T_49 = _legal_address_T_48 == 50'h0; // @[Parameters.scala:137:{46,59}] wire _legal_address_WIRE_9 = _legal_address_T_49; // @[Parameters.scala:612:40] wire [48:0] _legal_address_T_50 = {io_paddr_0[48:29], io_paddr_0[28:0] ^ 29'h10020000}; // @[PMA.scala:18:7] wire [49:0] _legal_address_T_51 = {1'h0, _legal_address_T_50}; // @[Parameters.scala:137:{31,41}] wire [49:0] _legal_address_T_52 = _legal_address_T_51 & 50'h3FFFFFFFFF000; // @[Parameters.scala:137:{41,46}] wire [49:0] _legal_address_T_53 = _legal_address_T_52; // @[Parameters.scala:137:46] wire _legal_address_T_54 = _legal_address_T_53 == 50'h0; // @[Parameters.scala:137:{46,59}] wire _legal_address_WIRE_10 = _legal_address_T_54; // @[Parameters.scala:612:40] wire [48:0] _GEN_7 = {io_paddr_0[48:32], io_paddr_0[31:0] ^ 32'h80000000}; // @[PMA.scala:18:7] wire [48:0] _legal_address_T_55; // @[Parameters.scala:137:31] assign _legal_address_T_55 = _GEN_7; // @[Parameters.scala:137:31] wire [48:0] _io_resp_cacheable_T_22; // @[Parameters.scala:137:31] assign _io_resp_cacheable_T_22 = _GEN_7; // @[Parameters.scala:137:31] wire [48:0] _io_resp_w_T_30; // @[Parameters.scala:137:31] assign _io_resp_w_T_30 = _GEN_7; // @[Parameters.scala:137:31] wire [48:0] _io_resp_pp_T_30; // @[Parameters.scala:137:31] assign _io_resp_pp_T_30 = _GEN_7; // @[Parameters.scala:137:31] wire [48:0] _io_resp_al_T_30; // @[Parameters.scala:137:31] assign _io_resp_al_T_30 = _GEN_7; // @[Parameters.scala:137:31] wire [48:0] _io_resp_aa_T_30; // @[Parameters.scala:137:31] assign _io_resp_aa_T_30 = _GEN_7; // @[Parameters.scala:137:31] wire [48:0] _io_resp_x_T_20; // @[Parameters.scala:137:31] assign _io_resp_x_T_20 = _GEN_7; // @[Parameters.scala:137:31] wire [48:0] _io_resp_eff_T_50; // @[Parameters.scala:137:31] assign _io_resp_eff_T_50 = _GEN_7; // @[Parameters.scala:137:31] wire [49:0] _legal_address_T_56 = {1'h0, _legal_address_T_55}; // @[Parameters.scala:137:{31,41}] wire [49:0] _legal_address_T_57 = _legal_address_T_56 & 50'h3FFFFF0000000; // @[Parameters.scala:137:{41,46}] wire [49:0] _legal_address_T_58 = _legal_address_T_57; // @[Parameters.scala:137:46] wire _legal_address_T_59 = _legal_address_T_58 == 50'h0; // @[Parameters.scala:137:{46,59}] wire _legal_address_WIRE_11 = _legal_address_T_59; // @[Parameters.scala:612:40] wire _legal_address_T_60 = _legal_address_WIRE_0 | _legal_address_WIRE_1; // @[Parameters.scala:612:40] wire _legal_address_T_61 = _legal_address_T_60 | _legal_address_WIRE_2; // @[Parameters.scala:612:40] wire _legal_address_T_62 = _legal_address_T_61 | _legal_address_WIRE_3; // @[Parameters.scala:612:40] wire _legal_address_T_63 = _legal_address_T_62 | _legal_address_WIRE_4; // @[Parameters.scala:612:40] wire _legal_address_T_64 = _legal_address_T_63 | _legal_address_WIRE_5; // @[Parameters.scala:612:40] wire _legal_address_T_65 = _legal_address_T_64 | _legal_address_WIRE_6; // @[Parameters.scala:612:40] wire _legal_address_T_66 = _legal_address_T_65 | _legal_address_WIRE_7; // @[Parameters.scala:612:40] wire _legal_address_T_67 = _legal_address_T_66 | _legal_address_WIRE_8; // @[Parameters.scala:612:40] wire _legal_address_T_68 = _legal_address_T_67 | _legal_address_WIRE_9; // @[Parameters.scala:612:40] wire _legal_address_T_69 = _legal_address_T_68 | _legal_address_WIRE_10; // @[Parameters.scala:612:40] wire legal_address = _legal_address_T_69 | _legal_address_WIRE_11; // @[Parameters.scala:612:40] assign _io_resp_r_T_5 = legal_address; // @[PMA.scala:36:58, :39:19] wire [49:0] _io_resp_cacheable_T_1 = {1'h0, _io_resp_cacheable_T}; // @[Parameters.scala:137:{31,41}] wire [49:0] _io_resp_cacheable_T_2 = _io_resp_cacheable_T_1 & 50'h8C000000; // @[Parameters.scala:137:{41,46}] wire [49:0] _io_resp_cacheable_T_3 = _io_resp_cacheable_T_2; // @[Parameters.scala:137:46] wire _io_resp_cacheable_T_4 = _io_resp_cacheable_T_3 == 50'h0; // @[Parameters.scala:137:{46,59}] wire [49:0] _io_resp_cacheable_T_6 = {1'h0, _io_resp_cacheable_T_5}; // @[Parameters.scala:137:{31,41}] wire [49:0] _io_resp_cacheable_T_7 = _io_resp_cacheable_T_6 & 50'h8C011000; // @[Parameters.scala:137:{41,46}] wire [49:0] _io_resp_cacheable_T_8 = _io_resp_cacheable_T_7; // @[Parameters.scala:137:46] wire _io_resp_cacheable_T_9 = _io_resp_cacheable_T_8 == 50'h0; // @[Parameters.scala:137:{46,59}] wire [49:0] _io_resp_cacheable_T_11 = {1'h0, _io_resp_cacheable_T_10}; // @[Parameters.scala:137:{31,41}] wire [49:0] _io_resp_cacheable_T_12 = _io_resp_cacheable_T_11 & 50'h8C000000; // @[Parameters.scala:137:{41,46}] wire [49:0] _io_resp_cacheable_T_13 = _io_resp_cacheable_T_12; // @[Parameters.scala:137:46] wire _io_resp_cacheable_T_14 = _io_resp_cacheable_T_13 == 50'h0; // @[Parameters.scala:137:{46,59}] wire _io_resp_cacheable_T_15 = _io_resp_cacheable_T_4 | _io_resp_cacheable_T_9; // @[Parameters.scala:629:89] wire _io_resp_cacheable_T_16 = _io_resp_cacheable_T_15 | _io_resp_cacheable_T_14; // @[Parameters.scala:629:89] wire [49:0] _io_resp_cacheable_T_18 = {1'h0, _io_resp_cacheable_T_17}; // @[Parameters.scala:137:{31,41}] wire [49:0] _io_resp_cacheable_T_19 = _io_resp_cacheable_T_18 & 50'h8C010000; // @[Parameters.scala:137:{41,46}] wire [49:0] _io_resp_cacheable_T_20 = _io_resp_cacheable_T_19; // @[Parameters.scala:137:46] wire _io_resp_cacheable_T_21 = _io_resp_cacheable_T_20 == 50'h0; // @[Parameters.scala:137:{46,59}] wire [49:0] _io_resp_cacheable_T_23 = {1'h0, _io_resp_cacheable_T_22}; // @[Parameters.scala:137:{31,41}] wire [49:0] _io_resp_cacheable_T_24 = _io_resp_cacheable_T_23 & 50'h80000000; // @[Parameters.scala:137:{41,46}] wire [49:0] _io_resp_cacheable_T_25 = _io_resp_cacheable_T_24; // @[Parameters.scala:137:46] wire _io_resp_cacheable_T_26 = _io_resp_cacheable_T_25 == 50'h0; // @[Parameters.scala:137:{46,59}] wire _io_resp_cacheable_T_27 = _io_resp_cacheable_T_21 | _io_resp_cacheable_T_26; // @[Parameters.scala:629:89] wire _io_resp_cacheable_T_29 = _io_resp_cacheable_T_27; // @[Mux.scala:30:73] wire _io_resp_cacheable_T_30 = _io_resp_cacheable_T_29; // @[Mux.scala:30:73] wire _io_resp_cacheable_WIRE = _io_resp_cacheable_T_30; // @[Mux.scala:30:73] assign _io_resp_cacheable_T_31 = legal_address & _io_resp_cacheable_WIRE; // @[Mux.scala:30:73] assign io_resp_cacheable_0 = _io_resp_cacheable_T_31; // @[PMA.scala:18:7, :39:19] wire [49:0] _io_resp_r_T_1 = {1'h0, _io_resp_r_T}; // @[Parameters.scala:137:{31,41}] assign io_resp_r_0 = _io_resp_r_T_5; // @[PMA.scala:18:7, :39:19] wire [49:0] _io_resp_w_T_1 = {1'h0, _io_resp_w_T}; // @[Parameters.scala:137:{31,41}] wire [49:0] _io_resp_w_T_2 = _io_resp_w_T_1 & 50'h98110000; // @[Parameters.scala:137:{41,46}] wire [49:0] _io_resp_w_T_3 = _io_resp_w_T_2; // @[Parameters.scala:137:46] wire _io_resp_w_T_4 = _io_resp_w_T_3 == 50'h0; // @[Parameters.scala:137:{46,59}] wire [49:0] _io_resp_w_T_6 = {1'h0, _io_resp_w_T_5}; // @[Parameters.scala:137:{31,41}] wire [49:0] _io_resp_w_T_7 = _io_resp_w_T_6 & 50'h9A101000; // @[Parameters.scala:137:{41,46}] wire [49:0] _io_resp_w_T_8 = _io_resp_w_T_7; // @[Parameters.scala:137:46] wire _io_resp_w_T_9 = _io_resp_w_T_8 == 50'h0; // @[Parameters.scala:137:{46,59}] wire [49:0] _io_resp_w_T_11 = {1'h0, _io_resp_w_T_10}; // @[Parameters.scala:137:{31,41}] wire [49:0] _io_resp_w_T_12 = _io_resp_w_T_11 & 50'h9A111000; // @[Parameters.scala:137:{41,46}] wire [49:0] _io_resp_w_T_13 = _io_resp_w_T_12; // @[Parameters.scala:137:46] wire _io_resp_w_T_14 = _io_resp_w_T_13 == 50'h0; // @[Parameters.scala:137:{46,59}] wire [49:0] _io_resp_w_T_16 = {1'h0, _io_resp_w_T_15}; // @[Parameters.scala:137:{31,41}] wire [49:0] _io_resp_w_T_17 = _io_resp_w_T_16 & 50'h98000000; // @[Parameters.scala:137:{41,46}] wire [49:0] _io_resp_w_T_18 = _io_resp_w_T_17; // @[Parameters.scala:137:46] wire _io_resp_w_T_19 = _io_resp_w_T_18 == 50'h0; // @[Parameters.scala:137:{46,59}] wire [49:0] _io_resp_w_T_21 = {1'h0, _io_resp_w_T_20}; // @[Parameters.scala:137:{31,41}] wire [49:0] _io_resp_w_T_22 = _io_resp_w_T_21 & 50'h9A110000; // @[Parameters.scala:137:{41,46}] wire [49:0] _io_resp_w_T_23 = _io_resp_w_T_22; // @[Parameters.scala:137:46] wire _io_resp_w_T_24 = _io_resp_w_T_23 == 50'h0; // @[Parameters.scala:137:{46,59}] wire [48:0] _GEN_8 = {io_paddr_0[48:29], io_paddr_0[28:0] ^ 29'h10000000}; // @[PMA.scala:18:7] wire [48:0] _io_resp_w_T_25; // @[Parameters.scala:137:31] assign _io_resp_w_T_25 = _GEN_8; // @[Parameters.scala:137:31] wire [48:0] _io_resp_pp_T_25; // @[Parameters.scala:137:31] assign _io_resp_pp_T_25 = _GEN_8; // @[Parameters.scala:137:31] wire [48:0] _io_resp_al_T_25; // @[Parameters.scala:137:31] assign _io_resp_al_T_25 = _GEN_8; // @[Parameters.scala:137:31] wire [48:0] _io_resp_aa_T_25; // @[Parameters.scala:137:31] assign _io_resp_aa_T_25 = _GEN_8; // @[Parameters.scala:137:31] wire [48:0] _io_resp_x_T_54; // @[Parameters.scala:137:31] assign _io_resp_x_T_54 = _GEN_8; // @[Parameters.scala:137:31] wire [48:0] _io_resp_eff_T_25; // @[Parameters.scala:137:31] assign _io_resp_eff_T_25 = _GEN_8; // @[Parameters.scala:137:31] wire [49:0] _io_resp_w_T_26 = {1'h0, _io_resp_w_T_25}; // @[Parameters.scala:137:{31,41}] wire [49:0] _io_resp_w_T_27 = _io_resp_w_T_26 & 50'h9A111000; // @[Parameters.scala:137:{41,46}] wire [49:0] _io_resp_w_T_28 = _io_resp_w_T_27; // @[Parameters.scala:137:46] wire _io_resp_w_T_29 = _io_resp_w_T_28 == 50'h0; // @[Parameters.scala:137:{46,59}] wire [49:0] _io_resp_w_T_31 = {1'h0, _io_resp_w_T_30}; // @[Parameters.scala:137:{31,41}] wire [49:0] _io_resp_w_T_32 = _io_resp_w_T_31 & 50'h90000000; // @[Parameters.scala:137:{41,46}] wire [49:0] _io_resp_w_T_33 = _io_resp_w_T_32; // @[Parameters.scala:137:46] wire _io_resp_w_T_34 = _io_resp_w_T_33 == 50'h0; // @[Parameters.scala:137:{46,59}] wire _io_resp_w_T_35 = _io_resp_w_T_4 | _io_resp_w_T_9; // @[Parameters.scala:629:89] wire _io_resp_w_T_36 = _io_resp_w_T_35 | _io_resp_w_T_14; // @[Parameters.scala:629:89] wire _io_resp_w_T_37 = _io_resp_w_T_36 | _io_resp_w_T_19; // @[Parameters.scala:629:89] wire _io_resp_w_T_38 = _io_resp_w_T_37 | _io_resp_w_T_24; // @[Parameters.scala:629:89] wire _io_resp_w_T_39 = _io_resp_w_T_38 | _io_resp_w_T_29; // @[Parameters.scala:629:89] wire _io_resp_w_T_40 = _io_resp_w_T_39 | _io_resp_w_T_34; // @[Parameters.scala:629:89] wire _io_resp_w_T_46 = _io_resp_w_T_40; // @[Mux.scala:30:73] wire [49:0] _io_resp_w_T_42 = {1'h0, _io_resp_w_T_41}; // @[Parameters.scala:137:{31,41}] wire [49:0] _io_resp_w_T_43 = _io_resp_w_T_42 & 50'h9A110000; // @[Parameters.scala:137:{41,46}] wire [49:0] _io_resp_w_T_44 = _io_resp_w_T_43; // @[Parameters.scala:137:46] wire _io_resp_w_T_45 = _io_resp_w_T_44 == 50'h0; // @[Parameters.scala:137:{46,59}] wire _io_resp_w_T_48 = _io_resp_w_T_46; // @[Mux.scala:30:73] wire _io_resp_w_WIRE = _io_resp_w_T_48; // @[Mux.scala:30:73] assign _io_resp_w_T_49 = legal_address & _io_resp_w_WIRE; // @[Mux.scala:30:73] assign io_resp_w_0 = _io_resp_w_T_49; // @[PMA.scala:18:7, :39:19] wire [49:0] _io_resp_pp_T_1 = {1'h0, _io_resp_pp_T}; // @[Parameters.scala:137:{31,41}] wire [49:0] _io_resp_pp_T_2 = _io_resp_pp_T_1 & 50'h98110000; // @[Parameters.scala:137:{41,46}] wire [49:0] _io_resp_pp_T_3 = _io_resp_pp_T_2; // @[Parameters.scala:137:46] wire _io_resp_pp_T_4 = _io_resp_pp_T_3 == 50'h0; // @[Parameters.scala:137:{46,59}] wire [49:0] _io_resp_pp_T_6 = {1'h0, _io_resp_pp_T_5}; // @[Parameters.scala:137:{31,41}] wire [49:0] _io_resp_pp_T_7 = _io_resp_pp_T_6 & 50'h9A101000; // @[Parameters.scala:137:{41,46}] wire [49:0] _io_resp_pp_T_8 = _io_resp_pp_T_7; // @[Parameters.scala:137:46] wire _io_resp_pp_T_9 = _io_resp_pp_T_8 == 50'h0; // @[Parameters.scala:137:{46,59}] wire [49:0] _io_resp_pp_T_11 = {1'h0, _io_resp_pp_T_10}; // @[Parameters.scala:137:{31,41}] wire [49:0] _io_resp_pp_T_12 = _io_resp_pp_T_11 & 50'h9A111000; // @[Parameters.scala:137:{41,46}] wire [49:0] _io_resp_pp_T_13 = _io_resp_pp_T_12; // @[Parameters.scala:137:46] wire _io_resp_pp_T_14 = _io_resp_pp_T_13 == 50'h0; // @[Parameters.scala:137:{46,59}] wire [49:0] _io_resp_pp_T_16 = {1'h0, _io_resp_pp_T_15}; // @[Parameters.scala:137:{31,41}] wire [49:0] _io_resp_pp_T_17 = _io_resp_pp_T_16 & 50'h98000000; // @[Parameters.scala:137:{41,46}] wire [49:0] _io_resp_pp_T_18 = _io_resp_pp_T_17; // @[Parameters.scala:137:46] wire _io_resp_pp_T_19 = _io_resp_pp_T_18 == 50'h0; // @[Parameters.scala:137:{46,59}] wire [49:0] _io_resp_pp_T_21 = {1'h0, _io_resp_pp_T_20}; // @[Parameters.scala:137:{31,41}] wire [49:0] _io_resp_pp_T_22 = _io_resp_pp_T_21 & 50'h9A110000; // @[Parameters.scala:137:{41,46}] wire [49:0] _io_resp_pp_T_23 = _io_resp_pp_T_22; // @[Parameters.scala:137:46] wire _io_resp_pp_T_24 = _io_resp_pp_T_23 == 50'h0; // @[Parameters.scala:137:{46,59}] wire [49:0] _io_resp_pp_T_26 = {1'h0, _io_resp_pp_T_25}; // @[Parameters.scala:137:{31,41}] wire [49:0] _io_resp_pp_T_27 = _io_resp_pp_T_26 & 50'h9A111000; // @[Parameters.scala:137:{41,46}] wire [49:0] _io_resp_pp_T_28 = _io_resp_pp_T_27; // @[Parameters.scala:137:46] wire _io_resp_pp_T_29 = _io_resp_pp_T_28 == 50'h0; // @[Parameters.scala:137:{46,59}] wire [49:0] _io_resp_pp_T_31 = {1'h0, _io_resp_pp_T_30}; // @[Parameters.scala:137:{31,41}] wire [49:0] _io_resp_pp_T_32 = _io_resp_pp_T_31 & 50'h90000000; // @[Parameters.scala:137:{41,46}] wire [49:0] _io_resp_pp_T_33 = _io_resp_pp_T_32; // @[Parameters.scala:137:46] wire _io_resp_pp_T_34 = _io_resp_pp_T_33 == 50'h0; // @[Parameters.scala:137:{46,59}] wire _io_resp_pp_T_35 = _io_resp_pp_T_4 | _io_resp_pp_T_9; // @[Parameters.scala:629:89] wire _io_resp_pp_T_36 = _io_resp_pp_T_35 | _io_resp_pp_T_14; // @[Parameters.scala:629:89] wire _io_resp_pp_T_37 = _io_resp_pp_T_36 | _io_resp_pp_T_19; // @[Parameters.scala:629:89] wire _io_resp_pp_T_38 = _io_resp_pp_T_37 | _io_resp_pp_T_24; // @[Parameters.scala:629:89] wire _io_resp_pp_T_39 = _io_resp_pp_T_38 | _io_resp_pp_T_29; // @[Parameters.scala:629:89] wire _io_resp_pp_T_40 = _io_resp_pp_T_39 | _io_resp_pp_T_34; // @[Parameters.scala:629:89] wire _io_resp_pp_T_46 = _io_resp_pp_T_40; // @[Mux.scala:30:73] wire [49:0] _io_resp_pp_T_42 = {1'h0, _io_resp_pp_T_41}; // @[Parameters.scala:137:{31,41}] wire [49:0] _io_resp_pp_T_43 = _io_resp_pp_T_42 & 50'h9A110000; // @[Parameters.scala:137:{41,46}] wire [49:0] _io_resp_pp_T_44 = _io_resp_pp_T_43; // @[Parameters.scala:137:46] wire _io_resp_pp_T_45 = _io_resp_pp_T_44 == 50'h0; // @[Parameters.scala:137:{46,59}] wire _io_resp_pp_T_48 = _io_resp_pp_T_46; // @[Mux.scala:30:73] wire _io_resp_pp_WIRE = _io_resp_pp_T_48; // @[Mux.scala:30:73] assign _io_resp_pp_T_49 = legal_address & _io_resp_pp_WIRE; // @[Mux.scala:30:73] assign io_resp_pp_0 = _io_resp_pp_T_49; // @[PMA.scala:18:7, :39:19] wire [49:0] _io_resp_al_T_1 = {1'h0, _io_resp_al_T}; // @[Parameters.scala:137:{31,41}] wire [49:0] _io_resp_al_T_2 = _io_resp_al_T_1 & 50'h98110000; // @[Parameters.scala:137:{41,46}] wire [49:0] _io_resp_al_T_3 = _io_resp_al_T_2; // @[Parameters.scala:137:46] wire _io_resp_al_T_4 = _io_resp_al_T_3 == 50'h0; // @[Parameters.scala:137:{46,59}] wire [49:0] _io_resp_al_T_6 = {1'h0, _io_resp_al_T_5}; // @[Parameters.scala:137:{31,41}] wire [49:0] _io_resp_al_T_7 = _io_resp_al_T_6 & 50'h9A101000; // @[Parameters.scala:137:{41,46}] wire [49:0] _io_resp_al_T_8 = _io_resp_al_T_7; // @[Parameters.scala:137:46] wire _io_resp_al_T_9 = _io_resp_al_T_8 == 50'h0; // @[Parameters.scala:137:{46,59}] wire [49:0] _io_resp_al_T_11 = {1'h0, _io_resp_al_T_10}; // @[Parameters.scala:137:{31,41}] wire [49:0] _io_resp_al_T_12 = _io_resp_al_T_11 & 50'h9A111000; // @[Parameters.scala:137:{41,46}] wire [49:0] _io_resp_al_T_13 = _io_resp_al_T_12; // @[Parameters.scala:137:46] wire _io_resp_al_T_14 = _io_resp_al_T_13 == 50'h0; // @[Parameters.scala:137:{46,59}] wire [49:0] _io_resp_al_T_16 = {1'h0, _io_resp_al_T_15}; // @[Parameters.scala:137:{31,41}] wire [49:0] _io_resp_al_T_17 = _io_resp_al_T_16 & 50'h98000000; // @[Parameters.scala:137:{41,46}] wire [49:0] _io_resp_al_T_18 = _io_resp_al_T_17; // @[Parameters.scala:137:46] wire _io_resp_al_T_19 = _io_resp_al_T_18 == 50'h0; // @[Parameters.scala:137:{46,59}] wire [49:0] _io_resp_al_T_21 = {1'h0, _io_resp_al_T_20}; // @[Parameters.scala:137:{31,41}] wire [49:0] _io_resp_al_T_22 = _io_resp_al_T_21 & 50'h9A110000; // @[Parameters.scala:137:{41,46}] wire [49:0] _io_resp_al_T_23 = _io_resp_al_T_22; // @[Parameters.scala:137:46] wire _io_resp_al_T_24 = _io_resp_al_T_23 == 50'h0; // @[Parameters.scala:137:{46,59}] wire [49:0] _io_resp_al_T_26 = {1'h0, _io_resp_al_T_25}; // @[Parameters.scala:137:{31,41}] wire [49:0] _io_resp_al_T_27 = _io_resp_al_T_26 & 50'h9A111000; // @[Parameters.scala:137:{41,46}] wire [49:0] _io_resp_al_T_28 = _io_resp_al_T_27; // @[Parameters.scala:137:46] wire _io_resp_al_T_29 = _io_resp_al_T_28 == 50'h0; // @[Parameters.scala:137:{46,59}] wire [49:0] _io_resp_al_T_31 = {1'h0, _io_resp_al_T_30}; // @[Parameters.scala:137:{31,41}] wire [49:0] _io_resp_al_T_32 = _io_resp_al_T_31 & 50'h90000000; // @[Parameters.scala:137:{41,46}] wire [49:0] _io_resp_al_T_33 = _io_resp_al_T_32; // @[Parameters.scala:137:46] wire _io_resp_al_T_34 = _io_resp_al_T_33 == 50'h0; // @[Parameters.scala:137:{46,59}] wire _io_resp_al_T_35 = _io_resp_al_T_4 | _io_resp_al_T_9; // @[Parameters.scala:629:89] wire _io_resp_al_T_36 = _io_resp_al_T_35 | _io_resp_al_T_14; // @[Parameters.scala:629:89] wire _io_resp_al_T_37 = _io_resp_al_T_36 | _io_resp_al_T_19; // @[Parameters.scala:629:89] wire _io_resp_al_T_38 = _io_resp_al_T_37 | _io_resp_al_T_24; // @[Parameters.scala:629:89] wire _io_resp_al_T_39 = _io_resp_al_T_38 | _io_resp_al_T_29; // @[Parameters.scala:629:89] wire _io_resp_al_T_40 = _io_resp_al_T_39 | _io_resp_al_T_34; // @[Parameters.scala:629:89] wire _io_resp_al_T_46 = _io_resp_al_T_40; // @[Mux.scala:30:73] wire [49:0] _io_resp_al_T_42 = {1'h0, _io_resp_al_T_41}; // @[Parameters.scala:137:{31,41}] wire [49:0] _io_resp_al_T_43 = _io_resp_al_T_42 & 50'h9A110000; // @[Parameters.scala:137:{41,46}] wire [49:0] _io_resp_al_T_44 = _io_resp_al_T_43; // @[Parameters.scala:137:46] wire _io_resp_al_T_45 = _io_resp_al_T_44 == 50'h0; // @[Parameters.scala:137:{46,59}] wire _io_resp_al_T_48 = _io_resp_al_T_46; // @[Mux.scala:30:73] wire _io_resp_al_WIRE = _io_resp_al_T_48; // @[Mux.scala:30:73] assign _io_resp_al_T_49 = legal_address & _io_resp_al_WIRE; // @[Mux.scala:30:73] assign io_resp_al_0 = _io_resp_al_T_49; // @[PMA.scala:18:7, :39:19] wire [49:0] _io_resp_aa_T_1 = {1'h0, _io_resp_aa_T}; // @[Parameters.scala:137:{31,41}] wire [49:0] _io_resp_aa_T_2 = _io_resp_aa_T_1 & 50'h98110000; // @[Parameters.scala:137:{41,46}] wire [49:0] _io_resp_aa_T_3 = _io_resp_aa_T_2; // @[Parameters.scala:137:46] wire _io_resp_aa_T_4 = _io_resp_aa_T_3 == 50'h0; // @[Parameters.scala:137:{46,59}] wire [49:0] _io_resp_aa_T_6 = {1'h0, _io_resp_aa_T_5}; // @[Parameters.scala:137:{31,41}] wire [49:0] _io_resp_aa_T_7 = _io_resp_aa_T_6 & 50'h9A101000; // @[Parameters.scala:137:{41,46}] wire [49:0] _io_resp_aa_T_8 = _io_resp_aa_T_7; // @[Parameters.scala:137:46] wire _io_resp_aa_T_9 = _io_resp_aa_T_8 == 50'h0; // @[Parameters.scala:137:{46,59}] wire [49:0] _io_resp_aa_T_11 = {1'h0, _io_resp_aa_T_10}; // @[Parameters.scala:137:{31,41}] wire [49:0] _io_resp_aa_T_12 = _io_resp_aa_T_11 & 50'h9A111000; // @[Parameters.scala:137:{41,46}] wire [49:0] _io_resp_aa_T_13 = _io_resp_aa_T_12; // @[Parameters.scala:137:46] wire _io_resp_aa_T_14 = _io_resp_aa_T_13 == 50'h0; // @[Parameters.scala:137:{46,59}] wire [49:0] _io_resp_aa_T_16 = {1'h0, _io_resp_aa_T_15}; // @[Parameters.scala:137:{31,41}] wire [49:0] _io_resp_aa_T_17 = _io_resp_aa_T_16 & 50'h98000000; // @[Parameters.scala:137:{41,46}] wire [49:0] _io_resp_aa_T_18 = _io_resp_aa_T_17; // @[Parameters.scala:137:46] wire _io_resp_aa_T_19 = _io_resp_aa_T_18 == 50'h0; // @[Parameters.scala:137:{46,59}] wire [49:0] _io_resp_aa_T_21 = {1'h0, _io_resp_aa_T_20}; // @[Parameters.scala:137:{31,41}] wire [49:0] _io_resp_aa_T_22 = _io_resp_aa_T_21 & 50'h9A110000; // @[Parameters.scala:137:{41,46}] wire [49:0] _io_resp_aa_T_23 = _io_resp_aa_T_22; // @[Parameters.scala:137:46] wire _io_resp_aa_T_24 = _io_resp_aa_T_23 == 50'h0; // @[Parameters.scala:137:{46,59}] wire [49:0] _io_resp_aa_T_26 = {1'h0, _io_resp_aa_T_25}; // @[Parameters.scala:137:{31,41}] wire [49:0] _io_resp_aa_T_27 = _io_resp_aa_T_26 & 50'h9A111000; // @[Parameters.scala:137:{41,46}] wire [49:0] _io_resp_aa_T_28 = _io_resp_aa_T_27; // @[Parameters.scala:137:46] wire _io_resp_aa_T_29 = _io_resp_aa_T_28 == 50'h0; // @[Parameters.scala:137:{46,59}] wire [49:0] _io_resp_aa_T_31 = {1'h0, _io_resp_aa_T_30}; // @[Parameters.scala:137:{31,41}] wire [49:0] _io_resp_aa_T_32 = _io_resp_aa_T_31 & 50'h90000000; // @[Parameters.scala:137:{41,46}] wire [49:0] _io_resp_aa_T_33 = _io_resp_aa_T_32; // @[Parameters.scala:137:46] wire _io_resp_aa_T_34 = _io_resp_aa_T_33 == 50'h0; // @[Parameters.scala:137:{46,59}] wire _io_resp_aa_T_35 = _io_resp_aa_T_4 | _io_resp_aa_T_9; // @[Parameters.scala:629:89] wire _io_resp_aa_T_36 = _io_resp_aa_T_35 | _io_resp_aa_T_14; // @[Parameters.scala:629:89] wire _io_resp_aa_T_37 = _io_resp_aa_T_36 | _io_resp_aa_T_19; // @[Parameters.scala:629:89] wire _io_resp_aa_T_38 = _io_resp_aa_T_37 | _io_resp_aa_T_24; // @[Parameters.scala:629:89] wire _io_resp_aa_T_39 = _io_resp_aa_T_38 | _io_resp_aa_T_29; // @[Parameters.scala:629:89] wire _io_resp_aa_T_40 = _io_resp_aa_T_39 | _io_resp_aa_T_34; // @[Parameters.scala:629:89] wire _io_resp_aa_T_46 = _io_resp_aa_T_40; // @[Mux.scala:30:73] wire [49:0] _io_resp_aa_T_42 = {1'h0, _io_resp_aa_T_41}; // @[Parameters.scala:137:{31,41}] wire [49:0] _io_resp_aa_T_43 = _io_resp_aa_T_42 & 50'h9A110000; // @[Parameters.scala:137:{41,46}] wire [49:0] _io_resp_aa_T_44 = _io_resp_aa_T_43; // @[Parameters.scala:137:46] wire _io_resp_aa_T_45 = _io_resp_aa_T_44 == 50'h0; // @[Parameters.scala:137:{46,59}] wire _io_resp_aa_T_48 = _io_resp_aa_T_46; // @[Mux.scala:30:73] wire _io_resp_aa_WIRE = _io_resp_aa_T_48; // @[Mux.scala:30:73] assign _io_resp_aa_T_49 = legal_address & _io_resp_aa_WIRE; // @[Mux.scala:30:73] assign io_resp_aa_0 = _io_resp_aa_T_49; // @[PMA.scala:18:7, :39:19] wire [49:0] _io_resp_x_T_1 = {1'h0, _io_resp_x_T}; // @[Parameters.scala:137:{31,41}] wire [49:0] _io_resp_x_T_2 = _io_resp_x_T_1 & 50'h9E113000; // @[Parameters.scala:137:{41,46}] wire [49:0] _io_resp_x_T_3 = _io_resp_x_T_2; // @[Parameters.scala:137:46] wire _io_resp_x_T_4 = _io_resp_x_T_3 == 50'h0; // @[Parameters.scala:137:{46,59}] wire [49:0] _io_resp_x_T_6 = {1'h0, _io_resp_x_T_5}; // @[Parameters.scala:137:{31,41}] wire [49:0] _io_resp_x_T_7 = _io_resp_x_T_6 & 50'h9E113000; // @[Parameters.scala:137:{41,46}] wire [49:0] _io_resp_x_T_8 = _io_resp_x_T_7; // @[Parameters.scala:137:46] wire _io_resp_x_T_9 = _io_resp_x_T_8 == 50'h0; // @[Parameters.scala:137:{46,59}] wire [49:0] _io_resp_x_T_11 = {1'h0, _io_resp_x_T_10}; // @[Parameters.scala:137:{31,41}] wire [49:0] _io_resp_x_T_12 = _io_resp_x_T_11 & 50'h9E110000; // @[Parameters.scala:137:{41,46}] wire [49:0] _io_resp_x_T_13 = _io_resp_x_T_12; // @[Parameters.scala:137:46] wire _io_resp_x_T_14 = _io_resp_x_T_13 == 50'h0; // @[Parameters.scala:137:{46,59}] wire [49:0] _io_resp_x_T_16 = {1'h0, _io_resp_x_T_15}; // @[Parameters.scala:137:{31,41}] wire [49:0] _io_resp_x_T_17 = _io_resp_x_T_16 & 50'h9E110000; // @[Parameters.scala:137:{41,46}] wire [49:0] _io_resp_x_T_18 = _io_resp_x_T_17; // @[Parameters.scala:137:46] wire _io_resp_x_T_19 = _io_resp_x_T_18 == 50'h0; // @[Parameters.scala:137:{46,59}] wire [49:0] _io_resp_x_T_21 = {1'h0, _io_resp_x_T_20}; // @[Parameters.scala:137:{31,41}] wire [49:0] _io_resp_x_T_22 = _io_resp_x_T_21 & 50'h90000000; // @[Parameters.scala:137:{41,46}] wire [49:0] _io_resp_x_T_23 = _io_resp_x_T_22; // @[Parameters.scala:137:46] wire _io_resp_x_T_24 = _io_resp_x_T_23 == 50'h0; // @[Parameters.scala:137:{46,59}] wire _io_resp_x_T_25 = _io_resp_x_T_4 | _io_resp_x_T_9; // @[Parameters.scala:629:89] wire _io_resp_x_T_26 = _io_resp_x_T_25 | _io_resp_x_T_14; // @[Parameters.scala:629:89] wire _io_resp_x_T_27 = _io_resp_x_T_26 | _io_resp_x_T_19; // @[Parameters.scala:629:89] wire _io_resp_x_T_28 = _io_resp_x_T_27 | _io_resp_x_T_24; // @[Parameters.scala:629:89] wire _io_resp_x_T_64 = _io_resp_x_T_28; // @[Mux.scala:30:73] wire [49:0] _io_resp_x_T_30 = {1'h0, _io_resp_x_T_29}; // @[Parameters.scala:137:{31,41}] wire [49:0] _io_resp_x_T_31 = _io_resp_x_T_30 & 50'h9E113000; // @[Parameters.scala:137:{41,46}] wire [49:0] _io_resp_x_T_32 = _io_resp_x_T_31; // @[Parameters.scala:137:46] wire _io_resp_x_T_33 = _io_resp_x_T_32 == 50'h0; // @[Parameters.scala:137:{46,59}] wire [49:0] _io_resp_x_T_35 = {1'h0, _io_resp_x_T_34}; // @[Parameters.scala:137:{31,41}] wire [49:0] _io_resp_x_T_36 = _io_resp_x_T_35 & 50'h9E103000; // @[Parameters.scala:137:{41,46}] wire [49:0] _io_resp_x_T_37 = _io_resp_x_T_36; // @[Parameters.scala:137:46] wire _io_resp_x_T_38 = _io_resp_x_T_37 == 50'h0; // @[Parameters.scala:137:{46,59}] wire [49:0] _io_resp_x_T_40 = {1'h0, _io_resp_x_T_39}; // @[Parameters.scala:137:{31,41}] wire [49:0] _io_resp_x_T_41 = _io_resp_x_T_40 & 50'h9E110000; // @[Parameters.scala:137:{41,46}] wire [49:0] _io_resp_x_T_42 = _io_resp_x_T_41; // @[Parameters.scala:137:46] wire _io_resp_x_T_43 = _io_resp_x_T_42 == 50'h0; // @[Parameters.scala:137:{46,59}] wire [49:0] _io_resp_x_T_45 = {1'h0, _io_resp_x_T_44}; // @[Parameters.scala:137:{31,41}] wire [49:0] _io_resp_x_T_46 = _io_resp_x_T_45 & 50'h9E113000; // @[Parameters.scala:137:{41,46}] wire [49:0] _io_resp_x_T_47 = _io_resp_x_T_46; // @[Parameters.scala:137:46] wire _io_resp_x_T_48 = _io_resp_x_T_47 == 50'h0; // @[Parameters.scala:137:{46,59}] wire [49:0] _io_resp_x_T_50 = {1'h0, _io_resp_x_T_49}; // @[Parameters.scala:137:{31,41}] wire [49:0] _io_resp_x_T_51 = _io_resp_x_T_50 & 50'h9C000000; // @[Parameters.scala:137:{41,46}] wire [49:0] _io_resp_x_T_52 = _io_resp_x_T_51; // @[Parameters.scala:137:46] wire _io_resp_x_T_53 = _io_resp_x_T_52 == 50'h0; // @[Parameters.scala:137:{46,59}] wire [49:0] _io_resp_x_T_55 = {1'h0, _io_resp_x_T_54}; // @[Parameters.scala:137:{31,41}] wire [49:0] _io_resp_x_T_56 = _io_resp_x_T_55 & 50'h9E113000; // @[Parameters.scala:137:{41,46}] wire [49:0] _io_resp_x_T_57 = _io_resp_x_T_56; // @[Parameters.scala:137:46] wire _io_resp_x_T_58 = _io_resp_x_T_57 == 50'h0; // @[Parameters.scala:137:{46,59}] wire _io_resp_x_T_59 = _io_resp_x_T_33 | _io_resp_x_T_38; // @[Parameters.scala:629:89] wire _io_resp_x_T_60 = _io_resp_x_T_59 | _io_resp_x_T_43; // @[Parameters.scala:629:89] wire _io_resp_x_T_61 = _io_resp_x_T_60 | _io_resp_x_T_48; // @[Parameters.scala:629:89] wire _io_resp_x_T_62 = _io_resp_x_T_61 | _io_resp_x_T_53; // @[Parameters.scala:629:89] wire _io_resp_x_T_63 = _io_resp_x_T_62 | _io_resp_x_T_58; // @[Parameters.scala:629:89] wire _io_resp_x_T_66 = _io_resp_x_T_64; // @[Mux.scala:30:73] wire _io_resp_x_WIRE = _io_resp_x_T_66; // @[Mux.scala:30:73] assign _io_resp_x_T_67 = legal_address & _io_resp_x_WIRE; // @[Mux.scala:30:73] assign io_resp_x_0 = _io_resp_x_T_67; // @[PMA.scala:18:7, :39:19] wire [49:0] _io_resp_eff_T_1 = {1'h0, _io_resp_eff_T}; // @[Parameters.scala:137:{31,41}] wire [49:0] _io_resp_eff_T_2 = _io_resp_eff_T_1 & 50'h9E112000; // @[Parameters.scala:137:{41,46}] wire [49:0] _io_resp_eff_T_3 = _io_resp_eff_T_2; // @[Parameters.scala:137:46] wire _io_resp_eff_T_4 = _io_resp_eff_T_3 == 50'h0; // @[Parameters.scala:137:{46,59}] wire [49:0] _io_resp_eff_T_6 = {1'h0, _io_resp_eff_T_5}; // @[Parameters.scala:137:{31,41}] wire [49:0] _io_resp_eff_T_7 = _io_resp_eff_T_6 & 50'h9E103000; // @[Parameters.scala:137:{41,46}] wire [49:0] _io_resp_eff_T_8 = _io_resp_eff_T_7; // @[Parameters.scala:137:46] wire _io_resp_eff_T_9 = _io_resp_eff_T_8 == 50'h0; // @[Parameters.scala:137:{46,59}] wire [49:0] _io_resp_eff_T_11 = {1'h0, _io_resp_eff_T_10}; // @[Parameters.scala:137:{31,41}] wire [49:0] _io_resp_eff_T_12 = _io_resp_eff_T_11 & 50'h9E110000; // @[Parameters.scala:137:{41,46}] wire [49:0] _io_resp_eff_T_13 = _io_resp_eff_T_12; // @[Parameters.scala:137:46] wire _io_resp_eff_T_14 = _io_resp_eff_T_13 == 50'h0; // @[Parameters.scala:137:{46,59}] wire [49:0] _io_resp_eff_T_16 = {1'h0, _io_resp_eff_T_15}; // @[Parameters.scala:137:{31,41}] wire [49:0] _io_resp_eff_T_17 = _io_resp_eff_T_16 & 50'h9E113000; // @[Parameters.scala:137:{41,46}] wire [49:0] _io_resp_eff_T_18 = _io_resp_eff_T_17; // @[Parameters.scala:137:46] wire _io_resp_eff_T_19 = _io_resp_eff_T_18 == 50'h0; // @[Parameters.scala:137:{46,59}] wire [49:0] _io_resp_eff_T_21 = {1'h0, _io_resp_eff_T_20}; // @[Parameters.scala:137:{31,41}] wire [49:0] _io_resp_eff_T_22 = _io_resp_eff_T_21 & 50'h9C000000; // @[Parameters.scala:137:{41,46}] wire [49:0] _io_resp_eff_T_23 = _io_resp_eff_T_22; // @[Parameters.scala:137:46] wire _io_resp_eff_T_24 = _io_resp_eff_T_23 == 50'h0; // @[Parameters.scala:137:{46,59}] wire [49:0] _io_resp_eff_T_26 = {1'h0, _io_resp_eff_T_25}; // @[Parameters.scala:137:{31,41}] wire [49:0] _io_resp_eff_T_27 = _io_resp_eff_T_26 & 50'h9E113000; // @[Parameters.scala:137:{41,46}] wire [49:0] _io_resp_eff_T_28 = _io_resp_eff_T_27; // @[Parameters.scala:137:46] wire _io_resp_eff_T_29 = _io_resp_eff_T_28 == 50'h0; // @[Parameters.scala:137:{46,59}] wire _io_resp_eff_T_30 = _io_resp_eff_T_4 | _io_resp_eff_T_9; // @[Parameters.scala:629:89] wire _io_resp_eff_T_31 = _io_resp_eff_T_30 | _io_resp_eff_T_14; // @[Parameters.scala:629:89] wire _io_resp_eff_T_32 = _io_resp_eff_T_31 | _io_resp_eff_T_19; // @[Parameters.scala:629:89] wire _io_resp_eff_T_33 = _io_resp_eff_T_32 | _io_resp_eff_T_24; // @[Parameters.scala:629:89] wire _io_resp_eff_T_34 = _io_resp_eff_T_33 | _io_resp_eff_T_29; // @[Parameters.scala:629:89] wire _io_resp_eff_T_58 = _io_resp_eff_T_34; // @[Mux.scala:30:73] wire [49:0] _io_resp_eff_T_36 = {1'h0, _io_resp_eff_T_35}; // @[Parameters.scala:137:{31,41}] wire [49:0] _io_resp_eff_T_37 = _io_resp_eff_T_36 & 50'h9E113000; // @[Parameters.scala:137:{41,46}] wire [49:0] _io_resp_eff_T_38 = _io_resp_eff_T_37; // @[Parameters.scala:137:46] wire _io_resp_eff_T_39 = _io_resp_eff_T_38 == 50'h0; // @[Parameters.scala:137:{46,59}] wire [49:0] _io_resp_eff_T_41 = {1'h0, _io_resp_eff_T_40}; // @[Parameters.scala:137:{31,41}] wire [49:0] _io_resp_eff_T_42 = _io_resp_eff_T_41 & 50'h9E110000; // @[Parameters.scala:137:{41,46}] wire [49:0] _io_resp_eff_T_43 = _io_resp_eff_T_42; // @[Parameters.scala:137:46] wire _io_resp_eff_T_44 = _io_resp_eff_T_43 == 50'h0; // @[Parameters.scala:137:{46,59}] wire [49:0] _io_resp_eff_T_46 = {1'h0, _io_resp_eff_T_45}; // @[Parameters.scala:137:{31,41}] wire [49:0] _io_resp_eff_T_47 = _io_resp_eff_T_46 & 50'h9E110000; // @[Parameters.scala:137:{41,46}] wire [49:0] _io_resp_eff_T_48 = _io_resp_eff_T_47; // @[Parameters.scala:137:46] wire _io_resp_eff_T_49 = _io_resp_eff_T_48 == 50'h0; // @[Parameters.scala:137:{46,59}] wire [49:0] _io_resp_eff_T_51 = {1'h0, _io_resp_eff_T_50}; // @[Parameters.scala:137:{31,41}] wire [49:0] _io_resp_eff_T_52 = _io_resp_eff_T_51 & 50'h90000000; // @[Parameters.scala:137:{41,46}] wire [49:0] _io_resp_eff_T_53 = _io_resp_eff_T_52; // @[Parameters.scala:137:46] wire _io_resp_eff_T_54 = _io_resp_eff_T_53 == 50'h0; // @[Parameters.scala:137:{46,59}] wire _io_resp_eff_T_55 = _io_resp_eff_T_39 | _io_resp_eff_T_44; // @[Parameters.scala:629:89] wire _io_resp_eff_T_56 = _io_resp_eff_T_55 | _io_resp_eff_T_49; // @[Parameters.scala:629:89] wire _io_resp_eff_T_57 = _io_resp_eff_T_56 | _io_resp_eff_T_54; // @[Parameters.scala:629:89] wire _io_resp_eff_T_60 = _io_resp_eff_T_58; // @[Mux.scala:30:73] wire _io_resp_eff_WIRE = _io_resp_eff_T_60; // @[Mux.scala:30:73] assign _io_resp_eff_T_61 = legal_address & _io_resp_eff_WIRE; // @[Mux.scala:30:73] assign io_resp_eff_0 = _io_resp_eff_T_61; // @[PMA.scala:18:7, :39:19] assign io_resp_cacheable = io_resp_cacheable_0; // @[PMA.scala:18:7] assign io_resp_r = io_resp_r_0; // @[PMA.scala:18:7] assign io_resp_w = io_resp_w_0; // @[PMA.scala:18:7] assign io_resp_pp = io_resp_pp_0; // @[PMA.scala:18:7] assign io_resp_al = io_resp_al_0; // @[PMA.scala:18:7] assign io_resp_aa = io_resp_aa_0; // @[PMA.scala:18:7] assign io_resp_x = io_resp_x_0; // @[PMA.scala:18:7] assign io_resp_eff = io_resp_eff_0; // @[PMA.scala:18:7] endmodule

Generate the Verilog code corresponding to the following Chisel files. File ShiftReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ // Similar to the Chisel ShiftRegister but allows the user to suggest a // name to the registers that get instantiated, and // to provide a reset value. object ShiftRegInit { def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T = (0 until n).foldRight(in) { case (i, next) => { val r = RegNext(next, init) name.foreach { na => r.suggestName(s"${na}_${i}") } r } } } /** These wrap behavioral * shift registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * The different types vary in their reset behavior: * AsyncResetShiftReg -- Asynchronously reset register array * A W(width) x D(depth) sized array is constructed from D instantiations of a * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg, * but only used for timing applications */ abstract class AbstractPipelineReg(w: Int = 1) extends Module { val io = IO(new Bundle { val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) } ) } object AbstractPipelineReg { def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = { val chain = Module(gen) name.foreach{ chain.suggestName(_) } chain.io.d := in.asUInt chain.io.q.asTypeOf(in) } } class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) { require(depth > 0, "Depth must be greater than 0.") override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}" val chain = List.tabulate(depth) { i => Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}") } chain.last.io.d := io.d chain.last.io.en := true.B (chain.init zip chain.tail).foreach { case (sink, source) => sink.io.d := source.io.q sink.io.en := true.B } io.q := chain.head.io.q } object AsyncResetShiftReg { def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name) def apply [T <: Data](in: T, depth: Int, name: Option[String]): T = apply(in, depth, 0, name) def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T = apply(in, depth, init.litValue.toInt, name) def apply [T <: Data](in: T, depth: Int, init: T): T = apply (in, depth, init.litValue.toInt, None) } File SynchronizerReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util.{RegEnable, Cat} /** These wrap behavioral * shift and next registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * * These are built up of *ResetSynchronizerPrimitiveShiftReg, * intended to be replaced by the integrator's metastable flops chains or replaced * at this level if they have a multi-bit wide synchronizer primitive. * The different types vary in their reset behavior: * NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin * AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep * 1-bit-wide shift registers. * SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg * * [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference. * * ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross * Clock Domains. */ object SynchronizerResetType extends Enumeration { val NonSync, Inferred, Sync, Async = Value } // Note: this should not be used directly. // Use the companion object to generate this with the correct reset type mixin. private class SynchronizerPrimitiveShiftReg( sync: Int, init: Boolean, resetType: SynchronizerResetType.Value) extends AbstractPipelineReg(1) { val initInt = if (init) 1 else 0 val initPostfix = resetType match { case SynchronizerResetType.NonSync => "" case _ => s"_i${initInt}" } override def desiredName = s"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}" val chain = List.tabulate(sync) { i => val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B) reg.suggestName(s"sync_$i") } chain.last := io.d.asBool (chain.init zip chain.tail).foreach { case (sink, source) => sink := source } io.q := chain.head.asUInt } private object SynchronizerPrimitiveShiftReg { def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = { val gen: () => SynchronizerPrimitiveShiftReg = resetType match { case SynchronizerResetType.NonSync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) case SynchronizerResetType.Async => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset case SynchronizerResetType.Sync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset case SynchronizerResetType.Inferred => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) } AbstractPipelineReg(gen(), in) } } // Note: This module may end up with a non-AsyncReset type reset. // But the Primitives within will always have AsyncReset type. class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asAsyncReset){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async) } } io.q := Cat(output.reverse) } object AsyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } // Note: This module may end up with a non-Bool type reset. // But the Primitives within will always have Bool reset type. @deprecated("SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.", "rocket-chip 1.2") class SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asBool){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync) } } io.q := Cat(output.reverse) } object SyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred) } io.q := Cat(output.reverse) } object ResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}" val output = Seq.tabulate(w) { i => SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync) } io.q := Cat(output.reverse) } object SynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, None) def apply [T <: Data](in: T): T = apply (in, 3, None) } class ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module { override def desiredName = s"ClockCrossingReg_w${w}" val io = IO(new Bundle{ val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) val en = Input(Bool()) }) val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en) io.q := cdc_reg } object ClockCrossingReg { def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = { val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit)) name.foreach{ cdc_reg.suggestName(_) } cdc_reg.io.d := in.asUInt cdc_reg.io.en := en cdc_reg.io.q.asTypeOf(in) } }

module AsyncResetSynchronizerShiftReg_w1_d3_i0_165( // @[SynchronizerReg.scala:80:7] input clock, // @[SynchronizerReg.scala:80:7] input reset, // @[SynchronizerReg.scala:80:7] output io_q // @[ShiftReg.scala:36:14] ); wire _output_T = reset; // @[SynchronizerReg.scala:86:21] wire io_d = 1'h1; // @[SynchronizerReg.scala:80:7, :87:41] wire _output_T_1 = 1'h1; // @[SynchronizerReg.scala:80:7, :87:41] wire output_0; // @[ShiftReg.scala:48:24] wire io_q_0; // @[SynchronizerReg.scala:80:7] assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_289 output_chain ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T), // @[SynchronizerReg.scala:86:21] .io_q (output_0) ); // @[ShiftReg.scala:45:23] assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7] endmodule

Generate the Verilog code corresponding to the following Chisel files. File InputUnit.scala: package constellation.router import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.{Field, Parameters} import freechips.rocketchip.util._ import constellation.channel._ import constellation.routing.{FlowRoutingBundle} import constellation.noc.{HasNoCParams} class AbstractInputUnitIO( val cParam: BaseChannelParams, val outParams: Seq[ChannelParams], val egressParams: Seq[EgressChannelParams], )(implicit val p: Parameters) extends Bundle with HasRouterOutputParams { val nodeId = cParam.destId val router_req = Decoupled(new RouteComputerReq) val router_resp = Input(new RouteComputerResp(outParams, egressParams)) val vcalloc_req = Decoupled(new VCAllocReq(cParam, outParams, egressParams)) val vcalloc_resp = Input(new VCAllocResp(outParams, egressParams)) val out_credit_available = Input(MixedVec(allOutParams.map { u => Vec(u.nVirtualChannels, Bool()) })) val salloc_req = Vec(cParam.destSpeedup, Decoupled(new SwitchAllocReq(outParams, egressParams))) val out = Vec(cParam.destSpeedup, Valid(new SwitchBundle(outParams, egressParams))) val debug = Output(new Bundle { val va_stall = UInt(log2Ceil(cParam.nVirtualChannels).W) val sa_stall = UInt(log2Ceil(cParam.nVirtualChannels).W) }) val block = Input(Bool()) } abstract class AbstractInputUnit( val cParam: BaseChannelParams, val outParams: Seq[ChannelParams], val egressParams: Seq[EgressChannelParams] )(implicit val p: Parameters) extends Module with HasRouterOutputParams with HasNoCParams { val nodeId = cParam.destId def io: AbstractInputUnitIO } class InputBuffer(cParam: ChannelParams)(implicit p: Parameters) extends Module { val nVirtualChannels = cParam.nVirtualChannels val io = IO(new Bundle { val enq = Flipped(Vec(cParam.srcSpeedup, Valid(new Flit(cParam.payloadBits)))) val deq = Vec(cParam.nVirtualChannels, Decoupled(new BaseFlit(cParam.payloadBits))) }) val useOutputQueues = cParam.useOutputQueues val delims = if (useOutputQueues) { cParam.virtualChannelParams.map(u => if (u.traversable) u.bufferSize else 0).scanLeft(0)(_+_) } else { // If no queuing, have to add an additional slot since head == tail implies empty // TODO this should be fixed, should use all slots available cParam.virtualChannelParams.map(u => if (u.traversable) u.bufferSize + 1 else 0).scanLeft(0)(_+_) } val starts = delims.dropRight(1).zipWithIndex.map { case (s,i) => if (cParam.virtualChannelParams(i).traversable) s else 0 } val ends = delims.tail.zipWithIndex.map { case (s,i) => if (cParam.virtualChannelParams(i).traversable) s else 0 } val fullSize = delims.last // Ugly case. Use multiple queues if ((cParam.srcSpeedup > 1 || cParam.destSpeedup > 1 || fullSize <= 1) || !cParam.unifiedBuffer) { require(useOutputQueues) val qs = cParam.virtualChannelParams.map(v => Module(new Queue(new BaseFlit(cParam.payloadBits), v.bufferSize))) qs.zipWithIndex.foreach { case (q,i) => val sel = io.enq.map(f => f.valid && f.bits.virt_channel_id === i.U) q.io.enq.valid := sel.orR q.io.enq.bits.head := Mux1H(sel, io.enq.map(_.bits.head)) q.io.enq.bits.tail := Mux1H(sel, io.enq.map(_.bits.tail)) q.io.enq.bits.payload := Mux1H(sel, io.enq.map(_.bits.payload)) io.deq(i) <> q.io.deq } } else { val mem = Mem(fullSize, new BaseFlit(cParam.payloadBits)) val heads = RegInit(VecInit(starts.map(_.U(log2Ceil(fullSize).W)))) val tails = RegInit(VecInit(starts.map(_.U(log2Ceil(fullSize).W)))) val empty = (heads zip tails).map(t => t._1 === t._2) val qs = Seq.fill(nVirtualChannels) { Module(new Queue(new BaseFlit(cParam.payloadBits), 1, pipe=true)) } qs.foreach(_.io.enq.valid := false.B) qs.foreach(_.io.enq.bits := DontCare) val vc_sel = UIntToOH(io.enq(0).bits.virt_channel_id) val flit = Wire(new BaseFlit(cParam.payloadBits)) val direct_to_q = (Mux1H(vc_sel, qs.map(_.io.enq.ready)) && Mux1H(vc_sel, empty)) && useOutputQueues.B flit.head := io.enq(0).bits.head flit.tail := io.enq(0).bits.tail flit.payload := io.enq(0).bits.payload when (io.enq(0).valid && !direct_to_q) { val tail = tails(io.enq(0).bits.virt_channel_id) mem.write(tail, flit) tails(io.enq(0).bits.virt_channel_id) := Mux( tail === Mux1H(vc_sel, ends.map(_ - 1).map(_ max 0).map(_.U)), Mux1H(vc_sel, starts.map(_.U)), tail + 1.U) } .elsewhen (io.enq(0).valid && direct_to_q) { for (i <- 0 until nVirtualChannels) { when (io.enq(0).bits.virt_channel_id === i.U) { qs(i).io.enq.valid := true.B qs(i).io.enq.bits := flit } } } if (useOutputQueues) { val can_to_q = (0 until nVirtualChannels).map { i => !empty(i) && qs(i).io.enq.ready } val to_q_oh = PriorityEncoderOH(can_to_q) val to_q = OHToUInt(to_q_oh) when (can_to_q.orR) { val head = Mux1H(to_q_oh, heads) heads(to_q) := Mux( head === Mux1H(to_q_oh, ends.map(_ - 1).map(_ max 0).map(_.U)), Mux1H(to_q_oh, starts.map(_.U)), head + 1.U) for (i <- 0 until nVirtualChannels) { when (to_q_oh(i)) { qs(i).io.enq.valid := true.B qs(i).io.enq.bits := mem.read(head) } } } for (i <- 0 until nVirtualChannels) { io.deq(i) <> qs(i).io.deq } } else { qs.map(_.io.deq.ready := false.B) val ready_sel = io.deq.map(_.ready) val fire = io.deq.map(_.fire) assert(PopCount(fire) <= 1.U) val head = Mux1H(fire, heads) when (fire.orR) { val fire_idx = OHToUInt(fire) heads(fire_idx) := Mux( head === Mux1H(fire, ends.map(_ - 1).map(_ max 0).map(_.U)), Mux1H(fire, starts.map(_.U)), head + 1.U) } val read_flit = mem.read(head) for (i <- 0 until nVirtualChannels) { io.deq(i).valid := !empty(i) io.deq(i).bits := read_flit } } } } class InputUnit(cParam: ChannelParams, outParams: Seq[ChannelParams], egressParams: Seq[EgressChannelParams], combineRCVA: Boolean, combineSAST: Boolean ) (implicit p: Parameters) extends AbstractInputUnit(cParam, outParams, egressParams)(p) { val nVirtualChannels = cParam.nVirtualChannels val virtualChannelParams = cParam.virtualChannelParams class InputUnitIO extends AbstractInputUnitIO(cParam, outParams, egressParams) { val in = Flipped(new Channel(cParam.asInstanceOf[ChannelParams])) } val io = IO(new InputUnitIO) val g_i :: g_r :: g_v :: g_a :: g_c :: Nil = Enum(5) class InputState extends Bundle { val g = UInt(3.W) val vc_sel = MixedVec(allOutParams.map { u => Vec(u.nVirtualChannels, Bool()) }) val flow = new FlowRoutingBundle val fifo_deps = UInt(nVirtualChannels.W) } val input_buffer = Module(new InputBuffer(cParam)) for (i <- 0 until cParam.srcSpeedup) { input_buffer.io.enq(i) := io.in.flit(i) } input_buffer.io.deq.foreach(_.ready := false.B) val route_arbiter = Module(new Arbiter( new RouteComputerReq, nVirtualChannels )) io.router_req <> route_arbiter.io.out val states = Reg(Vec(nVirtualChannels, new InputState)) val anyFifo = cParam.possibleFlows.map(_.fifo).reduce(_||_) val allFifo = cParam.possibleFlows.map(_.fifo).reduce(_&&_) if (anyFifo) { val idle_mask = VecInit(states.map(_.g === g_i)).asUInt for (s <- states) for (i <- 0 until nVirtualChannels) s.fifo_deps := s.fifo_deps & ~idle_mask } for (i <- 0 until cParam.srcSpeedup) { when (io.in.flit(i).fire && io.in.flit(i).bits.head) { val id = io.in.flit(i).bits.virt_channel_id assert(id < nVirtualChannels.U) assert(states(id).g === g_i) val at_dest = io.in.flit(i).bits.flow.egress_node === nodeId.U states(id).g := Mux(at_dest, g_v, g_r) states(id).vc_sel.foreach(_.foreach(_ := false.B)) for (o <- 0 until nEgress) { when (o.U === io.in.flit(i).bits.flow.egress_node_id) { states(id).vc_sel(o+nOutputs)(0) := true.B } } states(id).flow := io.in.flit(i).bits.flow if (anyFifo) { val fifo = cParam.possibleFlows.filter(_.fifo).map(_.isFlow(io.in.flit(i).bits.flow)).toSeq.orR states(id).fifo_deps := VecInit(states.zipWithIndex.map { case (s, j) => s.g =/= g_i && s.flow.asUInt === io.in.flit(i).bits.flow.asUInt && j.U =/= id }).asUInt } } } (route_arbiter.io.in zip states).zipWithIndex.map { case ((i,s),idx) => if (virtualChannelParams(idx).traversable) { i.valid := s.g === g_r i.bits.flow := s.flow i.bits.src_virt_id := idx.U when (i.fire) { s.g := g_v } } else { i.valid := false.B i.bits := DontCare } } when (io.router_req.fire) { val id = io.router_req.bits.src_virt_id assert(states(id).g === g_r) states(id).g := g_v for (i <- 0 until nVirtualChannels) { when (i.U === id) { states(i).vc_sel := io.router_resp.vc_sel } } } val mask = RegInit(0.U(nVirtualChannels.W)) val vcalloc_reqs = Wire(Vec(nVirtualChannels, new VCAllocReq(cParam, outParams, egressParams))) val vcalloc_vals = Wire(Vec(nVirtualChannels, Bool())) val vcalloc_filter = PriorityEncoderOH(Cat(vcalloc_vals.asUInt, vcalloc_vals.asUInt & ~mask)) val vcalloc_sel = vcalloc_filter(nVirtualChannels-1,0) | (vcalloc_filter >> nVirtualChannels) // Prioritize incoming packetes when (io.router_req.fire) { mask := (1.U << io.router_req.bits.src_virt_id) - 1.U } .elsewhen (vcalloc_vals.orR) { mask := Mux1H(vcalloc_sel, (0 until nVirtualChannels).map { w => ~(0.U((w+1).W)) }) } io.vcalloc_req.valid := vcalloc_vals.orR io.vcalloc_req.bits := Mux1H(vcalloc_sel, vcalloc_reqs) states.zipWithIndex.map { case (s,idx) => if (virtualChannelParams(idx).traversable) { vcalloc_vals(idx) := s.g === g_v && s.fifo_deps === 0.U vcalloc_reqs(idx).in_vc := idx.U vcalloc_reqs(idx).vc_sel := s.vc_sel vcalloc_reqs(idx).flow := s.flow when (vcalloc_vals(idx) && vcalloc_sel(idx) && io.vcalloc_req.ready) { s.g := g_a } if (combineRCVA) { when (route_arbiter.io.in(idx).fire) { vcalloc_vals(idx) := true.B vcalloc_reqs(idx).vc_sel := io.router_resp.vc_sel } } } else { vcalloc_vals(idx) := false.B vcalloc_reqs(idx) := DontCare } } io.debug.va_stall := PopCount(vcalloc_vals) - io.vcalloc_req.ready when (io.vcalloc_req.fire) { for (i <- 0 until nVirtualChannels) { when (vcalloc_sel(i)) { states(i).vc_sel := io.vcalloc_resp.vc_sel states(i).g := g_a if (!combineRCVA) { assert(states(i).g === g_v) } } } } val salloc_arb = Module(new SwitchArbiter( nVirtualChannels, cParam.destSpeedup, outParams, egressParams )) (states zip salloc_arb.io.in).zipWithIndex.map { case ((s,r),i) => if (virtualChannelParams(i).traversable) { val credit_available = (s.vc_sel.asUInt & io.out_credit_available.asUInt) =/= 0.U r.valid := s.g === g_a && credit_available && input_buffer.io.deq(i).valid r.bits.vc_sel := s.vc_sel val deq_tail = input_buffer.io.deq(i).bits.tail r.bits.tail := deq_tail when (r.fire && deq_tail) { s.g := g_i } input_buffer.io.deq(i).ready := r.ready } else { r.valid := false.B r.bits := DontCare } } io.debug.sa_stall := PopCount(salloc_arb.io.in.map(r => r.valid && !r.ready)) io.salloc_req <> salloc_arb.io.out when (io.block) { salloc_arb.io.out.foreach(_.ready := false.B) io.salloc_req.foreach(_.valid := false.B) } class OutBundle extends Bundle { val valid = Bool() val vid = UInt(virtualChannelBits.W) val out_vid = UInt(log2Up(allOutParams.map(_.nVirtualChannels).max).W) val flit = new Flit(cParam.payloadBits) } val salloc_outs = if (combineSAST) { Wire(Vec(cParam.destSpeedup, new OutBundle)) } else { Reg(Vec(cParam.destSpeedup, new OutBundle)) } io.in.credit_return := salloc_arb.io.out.zipWithIndex.map { case (o, i) => Mux(o.fire, salloc_arb.io.chosen_oh(i), 0.U) }.reduce(_|_) io.in.vc_free := salloc_arb.io.out.zipWithIndex.map { case (o, i) => Mux(o.fire && Mux1H(salloc_arb.io.chosen_oh(i), input_buffer.io.deq.map(_.bits.tail)), salloc_arb.io.chosen_oh(i), 0.U) }.reduce(_|_) for (i <- 0 until cParam.destSpeedup) { val salloc_out = salloc_outs(i) salloc_out.valid := salloc_arb.io.out(i).fire salloc_out.vid := OHToUInt(salloc_arb.io.chosen_oh(i)) val vc_sel = Mux1H(salloc_arb.io.chosen_oh(i), states.map(_.vc_sel)) val channel_oh = vc_sel.map(_.reduce(_||_)).toSeq val virt_channel = Mux1H(channel_oh, vc_sel.map(v => OHToUInt(v)).toSeq) when (salloc_arb.io.out(i).fire) { salloc_out.out_vid := virt_channel salloc_out.flit.payload := Mux1H(salloc_arb.io.chosen_oh(i), input_buffer.io.deq.map(_.bits.payload)) salloc_out.flit.head := Mux1H(salloc_arb.io.chosen_oh(i), input_buffer.io.deq.map(_.bits.head)) salloc_out.flit.tail := Mux1H(salloc_arb.io.chosen_oh(i), input_buffer.io.deq.map(_.bits.tail)) salloc_out.flit.flow := Mux1H(salloc_arb.io.chosen_oh(i), states.map(_.flow)) } .otherwise { salloc_out.out_vid := DontCare salloc_out.flit := DontCare } salloc_out.flit.virt_channel_id := DontCare // this gets set in the switch io.out(i).valid := salloc_out.valid io.out(i).bits.flit := salloc_out.flit io.out(i).bits.out_virt_channel := salloc_out.out_vid } def filterVCSel(sel: MixedVec[Vec[Bool]], srcV: Int) = { if (virtualChannelParams(srcV).traversable) { outParams.zipWithIndex.map { case (oP, oI) => (0 until oP.nVirtualChannels).map { oV => var allow = false virtualChannelParams(srcV).possibleFlows.foreach { pI => allow = allow || routingRelation( cParam.channelRoutingInfos(srcV), oP.channelRoutingInfos(oV), pI ) } if (!allow) sel(oI)(oV) := false.B } } } } (0 until nVirtualChannels).map { i => if (!virtualChannelParams(i).traversable) states(i) := DontCare filterVCSel(states(i).vc_sel, i) } when (reset.asBool) { states.foreach(_.g := g_i) } }

module InputUnit_15( // @[InputUnit.scala:158:7] input clock, // @[InputUnit.scala:158:7] input reset, // @[InputUnit.scala:158:7] output [2:0] io_router_req_bits_src_virt_id, // @[InputUnit.scala:170:14] output [2:0] io_router_req_bits_flow_vnet_id, // @[InputUnit.scala:170:14] output [4:0] io_router_req_bits_flow_ingress_node, // @[InputUnit.scala:170:14] output [1:0] io_router_req_bits_flow_ingress_node_id, // @[InputUnit.scala:170:14] output [4:0] io_router_req_bits_flow_egress_node, // @[InputUnit.scala:170:14] output [1:0] io_router_req_bits_flow_egress_node_id, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_2_1, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_2_2, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_2_3, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_2_4, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_2_5, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_2_6, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_2_7, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_0_1, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_0_2, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_0_3, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_0_4, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_0_5, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_0_6, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_0_7, // @[InputUnit.scala:170:14] input io_vcalloc_req_ready, // @[InputUnit.scala:170:14] output io_vcalloc_req_valid, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_2_1, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_2_2, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_2_3, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_2_4, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_2_5, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_2_6, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_2_7, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_0_1, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_0_2, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_0_3, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_0_4, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_0_5, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_0_6, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_0_7, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_2_1, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_2_2, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_2_3, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_2_4, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_2_5, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_2_6, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_2_7, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_0_1, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_0_2, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_0_3, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_0_4, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_0_5, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_0_6, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_0_7, // @[InputUnit.scala:170:14] input io_out_credit_available_2_1, // @[InputUnit.scala:170:14] input io_out_credit_available_2_2, // @[InputUnit.scala:170:14] input io_out_credit_available_2_3, // @[InputUnit.scala:170:14] input io_out_credit_available_2_4, // @[InputUnit.scala:170:14] input io_out_credit_available_2_5, // @[InputUnit.scala:170:14] input io_out_credit_available_2_6, // @[InputUnit.scala:170:14] input io_out_credit_available_2_7, // @[InputUnit.scala:170:14] input io_out_credit_available_1_4, // @[InputUnit.scala:170:14] input io_out_credit_available_1_5, // @[InputUnit.scala:170:14] input io_out_credit_available_1_6, // @[InputUnit.scala:170:14] input io_out_credit_available_1_7, // @[InputUnit.scala:170:14] input io_out_credit_available_0_1, // @[InputUnit.scala:170:14] input io_out_credit_available_0_2, // @[InputUnit.scala:170:14] input io_out_credit_available_0_3, // @[InputUnit.scala:170:14] input io_out_credit_available_0_4, // @[InputUnit.scala:170:14] input io_out_credit_available_0_5, // @[InputUnit.scala:170:14] input io_out_credit_available_0_6, // @[InputUnit.scala:170:14] input io_out_credit_available_0_7, // @[InputUnit.scala:170:14] input io_salloc_req_0_ready, // @[InputUnit.scala:170:14] output io_salloc_req_0_valid, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_2_0, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_2_1, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_2_2, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_2_3, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_2_4, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_2_5, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_2_6, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_2_7, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_1_0, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_1_1, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_1_2, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_1_3, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_1_4, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_1_5, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_1_6, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_1_7, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_0_1, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_0_2, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_0_3, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_0_4, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_0_5, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_0_6, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_0_7, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_tail, // @[InputUnit.scala:170:14] output io_out_0_valid, // @[InputUnit.scala:170:14] output io_out_0_bits_flit_head, // @[InputUnit.scala:170:14] output io_out_0_bits_flit_tail, // @[InputUnit.scala:170:14] output [72:0] io_out_0_bits_flit_payload, // @[InputUnit.scala:170:14] output [2:0] io_out_0_bits_flit_flow_vnet_id, // @[InputUnit.scala:170:14] output [4:0] io_out_0_bits_flit_flow_ingress_node, // @[InputUnit.scala:170:14] output [1:0] io_out_0_bits_flit_flow_ingress_node_id, // @[InputUnit.scala:170:14] output [4:0] io_out_0_bits_flit_flow_egress_node, // @[InputUnit.scala:170:14] output [1:0] io_out_0_bits_flit_flow_egress_node_id, // @[InputUnit.scala:170:14] output [2:0] io_out_0_bits_out_virt_channel, // @[InputUnit.scala:170:14] output [2:0] io_debug_va_stall, // @[InputUnit.scala:170:14] output [2:0] io_debug_sa_stall, // @[InputUnit.scala:170:14] input io_in_flit_0_valid, // @[InputUnit.scala:170:14] input io_in_flit_0_bits_head, // @[InputUnit.scala:170:14] input io_in_flit_0_bits_tail, // @[InputUnit.scala:170:14] input [72:0] io_in_flit_0_bits_payload, // @[InputUnit.scala:170:14] input [2:0] io_in_flit_0_bits_flow_vnet_id, // @[InputUnit.scala:170:14] input [4:0] io_in_flit_0_bits_flow_ingress_node, // @[InputUnit.scala:170:14] input [1:0] io_in_flit_0_bits_flow_ingress_node_id, // @[InputUnit.scala:170:14] input [4:0] io_in_flit_0_bits_flow_egress_node, // @[InputUnit.scala:170:14] input [1:0] io_in_flit_0_bits_flow_egress_node_id, // @[InputUnit.scala:170:14] input [2:0] io_in_flit_0_bits_virt_channel_id, // @[InputUnit.scala:170:14] output [7:0] io_in_credit_return, // @[InputUnit.scala:170:14] output [7:0] io_in_vc_free // @[InputUnit.scala:170:14] ); wire vcalloc_vals_7; // @[InputUnit.scala:266:32] wire vcalloc_vals_6; // @[InputUnit.scala:266:32] wire vcalloc_vals_5; // @[InputUnit.scala:266:32] wire vcalloc_vals_4; // @[InputUnit.scala:266:32] wire vcalloc_vals_3; // @[InputUnit.scala:266:32] wire vcalloc_vals_2; // @[InputUnit.scala:266:32] wire vcalloc_vals_1; // @[InputUnit.scala:266:32] wire _salloc_arb_io_in_1_ready; // @[InputUnit.scala:296:26] wire _salloc_arb_io_in_2_ready; // @[InputUnit.scala:296:26] wire _salloc_arb_io_in_3_ready; // @[InputUnit.scala:296:26] wire _salloc_arb_io_in_4_ready; // @[InputUnit.scala:296:26] wire _salloc_arb_io_in_5_ready; // @[InputUnit.scala:296:26] wire _salloc_arb_io_in_6_ready; // @[InputUnit.scala:296:26] wire _salloc_arb_io_in_7_ready; // @[InputUnit.scala:296:26] wire _salloc_arb_io_out_0_valid; // @[InputUnit.scala:296:26] wire [7:0] _salloc_arb_io_chosen_oh_0; // @[InputUnit.scala:296:26] wire _route_arbiter_io_in_1_ready; // @[InputUnit.scala:187:29] wire _route_arbiter_io_in_2_ready; // @[InputUnit.scala:187:29] wire _route_arbiter_io_in_3_ready; // @[InputUnit.scala:187:29] wire _route_arbiter_io_in_4_ready; // @[InputUnit.scala:187:29] wire _route_arbiter_io_in_5_ready; // @[InputUnit.scala:187:29] wire _route_arbiter_io_in_6_ready; // @[InputUnit.scala:187:29] wire _route_arbiter_io_in_7_ready; // @[InputUnit.scala:187:29] wire _route_arbiter_io_out_valid; // @[InputUnit.scala:187:29] wire [2:0] _route_arbiter_io_out_bits_src_virt_id; // @[InputUnit.scala:187:29] wire _input_buffer_io_deq_0_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_0_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_0_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_1_valid; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_1_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_1_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_1_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_2_valid; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_2_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_2_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_2_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_3_valid; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_3_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_3_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_3_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_4_valid; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_4_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_4_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_4_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_5_valid; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_5_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_5_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_5_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_6_valid; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_6_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_6_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_6_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_7_valid; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_7_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_7_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_7_bits_payload; // @[InputUnit.scala:181:28] reg [2:0] states_1_g; // @[InputUnit.scala:192:19] reg states_1_vc_sel_2_1; // @[InputUnit.scala:192:19] reg states_1_vc_sel_0_1; // @[InputUnit.scala:192:19] reg states_1_vc_sel_0_2; // @[InputUnit.scala:192:19] reg states_1_vc_sel_0_3; // @[InputUnit.scala:192:19] reg states_1_vc_sel_0_4; // @[InputUnit.scala:192:19] reg states_1_vc_sel_0_5; // @[InputUnit.scala:192:19] reg states_1_vc_sel_0_6; // @[InputUnit.scala:192:19] reg states_1_vc_sel_0_7; // @[InputUnit.scala:192:19] reg [2:0] states_1_flow_vnet_id; // @[InputUnit.scala:192:19] reg [4:0] states_1_flow_ingress_node; // @[InputUnit.scala:192:19] reg [1:0] states_1_flow_ingress_node_id; // @[InputUnit.scala:192:19] reg [4:0] states_1_flow_egress_node; // @[InputUnit.scala:192:19] reg [1:0] states_1_flow_egress_node_id; // @[InputUnit.scala:192:19] reg [2:0] states_2_g; // @[InputUnit.scala:192:19] reg states_2_vc_sel_2_1; // @[InputUnit.scala:192:19] reg states_2_vc_sel_2_2; // @[InputUnit.scala:192:19] reg states_2_vc_sel_2_3; // @[InputUnit.scala:192:19] reg states_2_vc_sel_2_4; // @[InputUnit.scala:192:19] reg states_2_vc_sel_2_5; // @[InputUnit.scala:192:19] reg states_2_vc_sel_2_6; // @[InputUnit.scala:192:19] reg states_2_vc_sel_2_7; // @[InputUnit.scala:192:19] reg states_2_vc_sel_0_1; // @[InputUnit.scala:192:19] reg states_2_vc_sel_0_2; // @[InputUnit.scala:192:19] reg states_2_vc_sel_0_3; // @[InputUnit.scala:192:19] reg states_2_vc_sel_0_4; // @[InputUnit.scala:192:19] reg states_2_vc_sel_0_5; // @[InputUnit.scala:192:19] reg states_2_vc_sel_0_6; // @[InputUnit.scala:192:19] reg states_2_vc_sel_0_7; // @[InputUnit.scala:192:19] reg [2:0] states_2_flow_vnet_id; // @[InputUnit.scala:192:19] reg [4:0] states_2_flow_ingress_node; // @[InputUnit.scala:192:19] reg [1:0] states_2_flow_ingress_node_id; // @[InputUnit.scala:192:19] reg [4:0] states_2_flow_egress_node; // @[InputUnit.scala:192:19] reg [1:0] states_2_flow_egress_node_id; // @[InputUnit.scala:192:19] reg [2:0] states_3_g; // @[InputUnit.scala:192:19] reg states_3_vc_sel_2_1; // @[InputUnit.scala:192:19] reg states_3_vc_sel_2_2; // @[InputUnit.scala:192:19] reg states_3_vc_sel_2_3; // @[InputUnit.scala:192:19] reg states_3_vc_sel_2_4; // @[InputUnit.scala:192:19] reg states_3_vc_sel_2_5; // @[InputUnit.scala:192:19] reg states_3_vc_sel_2_6; // @[InputUnit.scala:192:19] reg states_3_vc_sel_2_7; // @[InputUnit.scala:192:19] reg states_3_vc_sel_0_1; // @[InputUnit.scala:192:19] reg states_3_vc_sel_0_2; // @[InputUnit.scala:192:19] reg states_3_vc_sel_0_3; // @[InputUnit.scala:192:19] reg states_3_vc_sel_0_4; // @[InputUnit.scala:192:19] reg states_3_vc_sel_0_5; // @[InputUnit.scala:192:19] reg states_3_vc_sel_0_6; // @[InputUnit.scala:192:19] reg states_3_vc_sel_0_7; // @[InputUnit.scala:192:19] reg [2:0] states_3_flow_vnet_id; // @[InputUnit.scala:192:19] reg [4:0] states_3_flow_ingress_node; // @[InputUnit.scala:192:19] reg [1:0] states_3_flow_ingress_node_id; // @[InputUnit.scala:192:19] reg [4:0] states_3_flow_egress_node; // @[InputUnit.scala:192:19] reg [1:0] states_3_flow_egress_node_id; // @[InputUnit.scala:192:19] reg [2:0] states_4_g; // @[InputUnit.scala:192:19] reg states_4_vc_sel_2_1; // @[InputUnit.scala:192:19] reg states_4_vc_sel_2_2; // @[InputUnit.scala:192:19] reg states_4_vc_sel_2_3; // @[InputUnit.scala:192:19] reg states_4_vc_sel_2_4; // @[InputUnit.scala:192:19] reg states_4_vc_sel_2_5; // @[InputUnit.scala:192:19] reg states_4_vc_sel_2_6; // @[InputUnit.scala:192:19] reg states_4_vc_sel_2_7; // @[InputUnit.scala:192:19] reg states_4_vc_sel_0_1; // @[InputUnit.scala:192:19] reg states_4_vc_sel_0_2; // @[InputUnit.scala:192:19] reg states_4_vc_sel_0_3; // @[InputUnit.scala:192:19] reg states_4_vc_sel_0_4; // @[InputUnit.scala:192:19] reg states_4_vc_sel_0_5; // @[InputUnit.scala:192:19] reg states_4_vc_sel_0_6; // @[InputUnit.scala:192:19] reg states_4_vc_sel_0_7; // @[InputUnit.scala:192:19] reg [2:0] states_4_flow_vnet_id; // @[InputUnit.scala:192:19] reg [4:0] states_4_flow_ingress_node; // @[InputUnit.scala:192:19] reg [1:0] states_4_flow_ingress_node_id; // @[InputUnit.scala:192:19] reg [4:0] states_4_flow_egress_node; // @[InputUnit.scala:192:19] reg [1:0] states_4_flow_egress_node_id; // @[InputUnit.scala:192:19] reg [2:0] states_5_g; // @[InputUnit.scala:192:19] reg states_5_vc_sel_2_1; // @[InputUnit.scala:192:19] reg states_5_vc_sel_2_2; // @[InputUnit.scala:192:19] reg states_5_vc_sel_2_3; // @[InputUnit.scala:192:19] reg states_5_vc_sel_2_4; // @[InputUnit.scala:192:19] reg states_5_vc_sel_2_5; // @[InputUnit.scala:192:19] reg states_5_vc_sel_2_6; // @[InputUnit.scala:192:19] reg states_5_vc_sel_2_7; // @[InputUnit.scala:192:19] reg states_5_vc_sel_0_1; // @[InputUnit.scala:192:19] reg states_5_vc_sel_0_2; // @[InputUnit.scala:192:19] reg states_5_vc_sel_0_3; // @[InputUnit.scala:192:19] reg states_5_vc_sel_0_4; // @[InputUnit.scala:192:19] reg states_5_vc_sel_0_5; // @[InputUnit.scala:192:19] reg states_5_vc_sel_0_6; // @[InputUnit.scala:192:19] reg states_5_vc_sel_0_7; // @[InputUnit.scala:192:19] reg [2:0] states_5_flow_vnet_id; // @[InputUnit.scala:192:19] reg [4:0] states_5_flow_ingress_node; // @[InputUnit.scala:192:19] reg [1:0] states_5_flow_ingress_node_id; // @[InputUnit.scala:192:19] reg [4:0] states_5_flow_egress_node; // @[InputUnit.scala:192:19] reg [1:0] states_5_flow_egress_node_id; // @[InputUnit.scala:192:19] reg [2:0] states_6_g; // @[InputUnit.scala:192:19] reg states_6_vc_sel_2_1; // @[InputUnit.scala:192:19] reg states_6_vc_sel_2_2; // @[InputUnit.scala:192:19] reg states_6_vc_sel_2_3; // @[InputUnit.scala:192:19] reg states_6_vc_sel_2_4; // @[InputUnit.scala:192:19] reg states_6_vc_sel_2_5; // @[InputUnit.scala:192:19] reg states_6_vc_sel_2_6; // @[InputUnit.scala:192:19] reg states_6_vc_sel_2_7; // @[InputUnit.scala:192:19] reg states_6_vc_sel_0_1; // @[InputUnit.scala:192:19] reg states_6_vc_sel_0_2; // @[InputUnit.scala:192:19] reg states_6_vc_sel_0_3; // @[InputUnit.scala:192:19] reg states_6_vc_sel_0_4; // @[InputUnit.scala:192:19] reg states_6_vc_sel_0_5; // @[InputUnit.scala:192:19] reg states_6_vc_sel_0_6; // @[InputUnit.scala:192:19] reg states_6_vc_sel_0_7; // @[InputUnit.scala:192:19] reg [2:0] states_6_flow_vnet_id; // @[InputUnit.scala:192:19] reg [4:0] states_6_flow_ingress_node; // @[InputUnit.scala:192:19] reg [1:0] states_6_flow_ingress_node_id; // @[InputUnit.scala:192:19] reg [4:0] states_6_flow_egress_node; // @[InputUnit.scala:192:19] reg [1:0] states_6_flow_egress_node_id; // @[InputUnit.scala:192:19] reg [2:0] states_7_g; // @[InputUnit.scala:192:19] reg states_7_vc_sel_2_1; // @[InputUnit.scala:192:19] reg states_7_vc_sel_2_2; // @[InputUnit.scala:192:19] reg states_7_vc_sel_2_3; // @[InputUnit.scala:192:19] reg states_7_vc_sel_2_4; // @[InputUnit.scala:192:19] reg states_7_vc_sel_2_5; // @[InputUnit.scala:192:19] reg states_7_vc_sel_2_6; // @[InputUnit.scala:192:19] reg states_7_vc_sel_2_7; // @[InputUnit.scala:192:19] reg states_7_vc_sel_0_1; // @[InputUnit.scala:192:19] reg states_7_vc_sel_0_2; // @[InputUnit.scala:192:19] reg states_7_vc_sel_0_3; // @[InputUnit.scala:192:19] reg states_7_vc_sel_0_4; // @[InputUnit.scala:192:19] reg states_7_vc_sel_0_5; // @[InputUnit.scala:192:19] reg states_7_vc_sel_0_6; // @[InputUnit.scala:192:19] reg states_7_vc_sel_0_7; // @[InputUnit.scala:192:19] reg [2:0] states_7_flow_vnet_id; // @[InputUnit.scala:192:19] reg [4:0] states_7_flow_ingress_node; // @[InputUnit.scala:192:19] reg [1:0] states_7_flow_ingress_node_id; // @[InputUnit.scala:192:19] reg [4:0] states_7_flow_egress_node; // @[InputUnit.scala:192:19] reg [1:0] states_7_flow_egress_node_id; // @[InputUnit.scala:192:19] wire _GEN = io_in_flit_0_valid & io_in_flit_0_bits_head; // @[InputUnit.scala:205:30] wire route_arbiter_io_in_1_valid = states_1_g == 3'h1; // @[InputUnit.scala:192:19, :229:22] wire route_arbiter_io_in_2_valid = states_2_g == 3'h1; // @[InputUnit.scala:192:19, :229:22] wire route_arbiter_io_in_3_valid = states_3_g == 3'h1; // @[InputUnit.scala:192:19, :229:22] wire route_arbiter_io_in_4_valid = states_4_g == 3'h1; // @[InputUnit.scala:192:19, :229:22] wire route_arbiter_io_in_5_valid = states_5_g == 3'h1; // @[InputUnit.scala:192:19, :229:22] wire route_arbiter_io_in_6_valid = states_6_g == 3'h1; // @[InputUnit.scala:192:19, :229:22] wire route_arbiter_io_in_7_valid = states_7_g == 3'h1; // @[InputUnit.scala:192:19, :229:22] reg [7:0] mask; // @[InputUnit.scala:250:21] wire [7:0] _vcalloc_filter_T_3 = {vcalloc_vals_7, vcalloc_vals_6, vcalloc_vals_5, vcalloc_vals_4, vcalloc_vals_3, vcalloc_vals_2, vcalloc_vals_1, 1'h0} & ~mask; // @[InputUnit.scala:250:21, :253:{80,87,89}, :266:32] wire [15:0] vcalloc_filter = _vcalloc_filter_T_3[0] ? 16'h1 : _vcalloc_filter_T_3[1] ? 16'h2 : _vcalloc_filter_T_3[2] ? 16'h4 : _vcalloc_filter_T_3[3] ? 16'h8 : _vcalloc_filter_T_3[4] ? 16'h10 : _vcalloc_filter_T_3[5] ? 16'h20 : _vcalloc_filter_T_3[6] ? 16'h40 : _vcalloc_filter_T_3[7] ? 16'h80 : vcalloc_vals_1 ? 16'h200 : vcalloc_vals_2 ? 16'h400 : vcalloc_vals_3 ? 16'h800 : vcalloc_vals_4 ? 16'h1000 : vcalloc_vals_5 ? 16'h2000 : vcalloc_vals_6 ? 16'h4000 : {vcalloc_vals_7, 15'h0}; // @[OneHot.scala:85:71] wire [7:0] vcalloc_sel = vcalloc_filter[7:0] | vcalloc_filter[15:8]; // @[Mux.scala:50:70] wire io_vcalloc_req_valid_0 = vcalloc_vals_1 | vcalloc_vals_2 | vcalloc_vals_3 | vcalloc_vals_4 | vcalloc_vals_5 | vcalloc_vals_6 | vcalloc_vals_7; // @[package.scala:81:59] assign vcalloc_vals_1 = states_1_g == 3'h2; // @[InputUnit.scala:192:19, :266:32] assign vcalloc_vals_2 = states_2_g == 3'h2; // @[InputUnit.scala:192:19, :266:32] assign vcalloc_vals_3 = states_3_g == 3'h2; // @[InputUnit.scala:192:19, :266:32] assign vcalloc_vals_4 = states_4_g == 3'h2; // @[InputUnit.scala:192:19, :266:32] assign vcalloc_vals_5 = states_5_g == 3'h2; // @[InputUnit.scala:192:19, :266:32] assign vcalloc_vals_6 = states_6_g == 3'h2; // @[InputUnit.scala:192:19, :266:32] assign vcalloc_vals_7 = states_7_g == 3'h2; // @[InputUnit.scala:192:19, :266:32] wire _GEN_0 = io_vcalloc_req_ready & io_vcalloc_req_valid_0; // @[Decoupled.scala:51:35] wire _GEN_1 = _GEN_0 & vcalloc_sel[1]; // @[Mux.scala:32:36] wire _GEN_2 = _GEN_0 & vcalloc_sel[2]; // @[Mux.scala:32:36] wire _GEN_3 = _GEN_0 & vcalloc_sel[3]; // @[Mux.scala:32:36] wire _GEN_4 = _GEN_0 & vcalloc_sel[4]; // @[Mux.scala:32:36] wire _GEN_5 = _GEN_0 & vcalloc_sel[5]; // @[Mux.scala:32:36] wire _GEN_6 = _GEN_0 & vcalloc_sel[6]; // @[Mux.scala:32:36] wire _GEN_7 = _GEN_0 & vcalloc_sel[7]; // @[Mux.scala:32:36]

Generate the Verilog code corresponding to the following Chisel files. File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /** Like Vec.apply(idx), but tolerates indices of mismatched width */ def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /** Any Data subtype that has a Bool member named valid. */ type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /** converts from camel case to to underscores, also removing all spaces */ def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /** converts spaces or underscores to hyphens, also lowering case */ def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y | (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y || y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /** Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation */ def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag }

module OptimizationBarrier_TLBEntryData_26( // @[package.scala:267:30] input clock, // @[package.scala:267:30] input reset, // @[package.scala:267:30] input [19:0] io_x_ppn, // @[package.scala:268:18] input io_x_u, // @[package.scala:268:18] input io_x_g, // @[package.scala:268:18] input io_x_ae_ptw, // @[package.scala:268:18] input io_x_ae_final, // @[package.scala:268:18] input io_x_ae_stage2, // @[package.scala:268:18] input io_x_pf, // @[package.scala:268:18] input io_x_gf, // @[package.scala:268:18] input io_x_sw, // @[package.scala:268:18] input io_x_sx, // @[package.scala:268:18] input io_x_sr, // @[package.scala:268:18] input io_x_hw, // @[package.scala:268:18] input io_x_hx, // @[package.scala:268:18] input io_x_hr, // @[package.scala:268:18] input io_x_pw, // @[package.scala:268:18] input io_x_px, // @[package.scala:268:18] input io_x_pr, // @[package.scala:268:18] input io_x_ppp, // @[package.scala:268:18] input io_x_pal, // @[package.scala:268:18] input io_x_paa, // @[package.scala:268:18] input io_x_eff, // @[package.scala:268:18] input io_x_c, // @[package.scala:268:18] input io_x_fragmented_superpage, // @[package.scala:268:18] output [19:0] io_y_ppn, // @[package.scala:268:18] output io_y_u, // @[package.scala:268:18] output io_y_ae_ptw, // @[package.scala:268:18] output io_y_ae_final, // @[package.scala:268:18] output io_y_ae_stage2, // @[package.scala:268:18] output io_y_pf, // @[package.scala:268:18] output io_y_gf, // @[package.scala:268:18] output io_y_sw, // @[package.scala:268:18] output io_y_sx, // @[package.scala:268:18] output io_y_sr, // @[package.scala:268:18] output io_y_hw, // @[package.scala:268:18] output io_y_hx, // @[package.scala:268:18] output io_y_hr, // @[package.scala:268:18] output io_y_pw, // @[package.scala:268:18] output io_y_px, // @[package.scala:268:18] output io_y_pr, // @[package.scala:268:18] output io_y_ppp, // @[package.scala:268:18] output io_y_pal, // @[package.scala:268:18] output io_y_paa, // @[package.scala:268:18] output io_y_eff, // @[package.scala:268:18] output io_y_c // @[package.scala:268:18] ); wire [19:0] io_x_ppn_0 = io_x_ppn; // @[package.scala:267:30] wire io_x_u_0 = io_x_u; // @[package.scala:267:30] wire io_x_g_0 = io_x_g; // @[package.scala:267:30] wire io_x_ae_ptw_0 = io_x_ae_ptw; // @[package.scala:267:30] wire io_x_ae_final_0 = io_x_ae_final; // @[package.scala:267:30] wire io_x_ae_stage2_0 = io_x_ae_stage2; // @[package.scala:267:30] wire io_x_pf_0 = io_x_pf; // @[package.scala:267:30] wire io_x_gf_0 = io_x_gf; // @[package.scala:267:30] wire io_x_sw_0 = io_x_sw; // @[package.scala:267:30] wire io_x_sx_0 = io_x_sx; // @[package.scala:267:30] wire io_x_sr_0 = io_x_sr; // @[package.scala:267:30] wire io_x_hw_0 = io_x_hw; // @[package.scala:267:30] wire io_x_hx_0 = io_x_hx; // @[package.scala:267:30] wire io_x_hr_0 = io_x_hr; // @[package.scala:267:30] wire io_x_pw_0 = io_x_pw; // @[package.scala:267:30] wire io_x_px_0 = io_x_px; // @[package.scala:267:30] wire io_x_pr_0 = io_x_pr; // @[package.scala:267:30] wire io_x_ppp_0 = io_x_ppp; // @[package.scala:267:30] wire io_x_pal_0 = io_x_pal; // @[package.scala:267:30] wire io_x_paa_0 = io_x_paa; // @[package.scala:267:30] wire io_x_eff_0 = io_x_eff; // @[package.scala:267:30] wire io_x_c_0 = io_x_c; // @[package.scala:267:30] wire io_x_fragmented_superpage_0 = io_x_fragmented_superpage; // @[package.scala:267:30] wire [19:0] io_y_ppn_0 = io_x_ppn_0; // @[package.scala:267:30] wire io_y_u_0 = io_x_u_0; // @[package.scala:267:30] wire io_y_g = io_x_g_0; // @[package.scala:267:30] wire io_y_ae_ptw_0 = io_x_ae_ptw_0; // @[package.scala:267:30] wire io_y_ae_final_0 = io_x_ae_final_0; // @[package.scala:267:30] wire io_y_ae_stage2_0 = io_x_ae_stage2_0; // @[package.scala:267:30] wire io_y_pf_0 = io_x_pf_0; // @[package.scala:267:30] wire io_y_gf_0 = io_x_gf_0; // @[package.scala:267:30] wire io_y_sw_0 = io_x_sw_0; // @[package.scala:267:30] wire io_y_sx_0 = io_x_sx_0; // @[package.scala:267:30] wire io_y_sr_0 = io_x_sr_0; // @[package.scala:267:30] wire io_y_hw_0 = io_x_hw_0; // @[package.scala:267:30] wire io_y_hx_0 = io_x_hx_0; // @[package.scala:267:30] wire io_y_hr_0 = io_x_hr_0; // @[package.scala:267:30] wire io_y_pw_0 = io_x_pw_0; // @[package.scala:267:30] wire io_y_px_0 = io_x_px_0; // @[package.scala:267:30] wire io_y_pr_0 = io_x_pr_0; // @[package.scala:267:30] wire io_y_ppp_0 = io_x_ppp_0; // @[package.scala:267:30] wire io_y_pal_0 = io_x_pal_0; // @[package.scala:267:30] wire io_y_paa_0 = io_x_paa_0; // @[package.scala:267:30] wire io_y_eff_0 = io_x_eff_0; // @[package.scala:267:30] wire io_y_c_0 = io_x_c_0; // @[package.scala:267:30] wire io_y_fragmented_superpage = io_x_fragmented_superpage_0; // @[package.scala:267:30] assign io_y_ppn = io_y_ppn_0; // @[package.scala:267:30] assign io_y_u = io_y_u_0; // @[package.scala:267:30] assign io_y_ae_ptw = io_y_ae_ptw_0; // @[package.scala:267:30] assign io_y_ae_final = io_y_ae_final_0; // @[package.scala:267:30] assign io_y_ae_stage2 = io_y_ae_stage2_0; // @[package.scala:267:30] assign io_y_pf = io_y_pf_0; // @[package.scala:267:30] assign io_y_gf = io_y_gf_0; // @[package.scala:267:30] assign io_y_sw = io_y_sw_0; // @[package.scala:267:30] assign io_y_sx = io_y_sx_0; // @[package.scala:267:30] assign io_y_sr = io_y_sr_0; // @[package.scala:267:30] assign io_y_hw = io_y_hw_0; // @[package.scala:267:30] assign io_y_hx = io_y_hx_0; // @[package.scala:267:30] assign io_y_hr = io_y_hr_0; // @[package.scala:267:30] assign io_y_pw = io_y_pw_0; // @[package.scala:267:30] assign io_y_px = io_y_px_0; // @[package.scala:267:30] assign io_y_pr = io_y_pr_0; // @[package.scala:267:30] assign io_y_ppp = io_y_ppp_0; // @[package.scala:267:30] assign io_y_pal = io_y_pal_0; // @[package.scala:267:30] assign io_y_paa = io_y_paa_0; // @[package.scala:267:30] assign io_y_eff = io_y_eff_0; // @[package.scala:267:30] assign io_y_c = io_y_c_0; // @[package.scala:267:30] endmodule

Generate the Verilog code corresponding to the following Chisel files. File ShiftReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ // Similar to the Chisel ShiftRegister but allows the user to suggest a // name to the registers that get instantiated, and // to provide a reset value. object ShiftRegInit { def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T = (0 until n).foldRight(in) { case (i, next) => { val r = RegNext(next, init) name.foreach { na => r.suggestName(s"${na}_${i}") } r } } } /** These wrap behavioral * shift registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * The different types vary in their reset behavior: * AsyncResetShiftReg -- Asynchronously reset register array * A W(width) x D(depth) sized array is constructed from D instantiations of a * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg, * but only used for timing applications */ abstract class AbstractPipelineReg(w: Int = 1) extends Module { val io = IO(new Bundle { val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) } ) } object AbstractPipelineReg { def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = { val chain = Module(gen) name.foreach{ chain.suggestName(_) } chain.io.d := in.asUInt chain.io.q.asTypeOf(in) } } class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) { require(depth > 0, "Depth must be greater than 0.") override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}" val chain = List.tabulate(depth) { i => Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}") } chain.last.io.d := io.d chain.last.io.en := true.B (chain.init zip chain.tail).foreach { case (sink, source) => sink.io.d := source.io.q sink.io.en := true.B } io.q := chain.head.io.q } object AsyncResetShiftReg { def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name) def apply [T <: Data](in: T, depth: Int, name: Option[String]): T = apply(in, depth, 0, name) def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T = apply(in, depth, init.litValue.toInt, name) def apply [T <: Data](in: T, depth: Int, init: T): T = apply (in, depth, init.litValue.toInt, None) } File SynchronizerReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util.{RegEnable, Cat} /** These wrap behavioral * shift and next registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * * These are built up of *ResetSynchronizerPrimitiveShiftReg, * intended to be replaced by the integrator's metastable flops chains or replaced * at this level if they have a multi-bit wide synchronizer primitive. * The different types vary in their reset behavior: * NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin * AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep * 1-bit-wide shift registers. * SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg * * [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference. * * ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross * Clock Domains. */ object SynchronizerResetType extends Enumeration { val NonSync, Inferred, Sync, Async = Value } // Note: this should not be used directly. // Use the companion object to generate this with the correct reset type mixin. private class SynchronizerPrimitiveShiftReg( sync: Int, init: Boolean, resetType: SynchronizerResetType.Value) extends AbstractPipelineReg(1) { val initInt = if (init) 1 else 0 val initPostfix = resetType match { case SynchronizerResetType.NonSync => "" case _ => s"_i${initInt}" } override def desiredName = s"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}" val chain = List.tabulate(sync) { i => val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B) reg.suggestName(s"sync_$i") } chain.last := io.d.asBool (chain.init zip chain.tail).foreach { case (sink, source) => sink := source } io.q := chain.head.asUInt } private object SynchronizerPrimitiveShiftReg { def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = { val gen: () => SynchronizerPrimitiveShiftReg = resetType match { case SynchronizerResetType.NonSync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) case SynchronizerResetType.Async => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset case SynchronizerResetType.Sync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset case SynchronizerResetType.Inferred => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) } AbstractPipelineReg(gen(), in) } } // Note: This module may end up with a non-AsyncReset type reset. // But the Primitives within will always have AsyncReset type. class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asAsyncReset){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async) } } io.q := Cat(output.reverse) } object AsyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } // Note: This module may end up with a non-Bool type reset. // But the Primitives within will always have Bool reset type. @deprecated("SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.", "rocket-chip 1.2") class SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asBool){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync) } } io.q := Cat(output.reverse) } object SyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred) } io.q := Cat(output.reverse) } object ResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}" val output = Seq.tabulate(w) { i => SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync) } io.q := Cat(output.reverse) } object SynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, None) def apply [T <: Data](in: T): T = apply (in, 3, None) } class ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module { override def desiredName = s"ClockCrossingReg_w${w}" val io = IO(new Bundle{ val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) val en = Input(Bool()) }) val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en) io.q := cdc_reg } object ClockCrossingReg { def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = { val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit)) name.foreach{ cdc_reg.suggestName(_) } cdc_reg.io.d := in.asUInt cdc_reg.io.en := en cdc_reg.io.q.asTypeOf(in) } } File AsyncQueue.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ case class AsyncQueueParams( depth: Int = 8, sync: Int = 3, safe: Boolean = true, // If safe is true, then effort is made to resynchronize the crossing indices when either side is reset. // This makes it safe/possible to reset one side of the crossing (but not the other) when the queue is empty. narrow: Boolean = false) // If narrow is true then the read mux is moved to the source side of the crossing. // This reduces the number of level shifters in the case where the clock crossing is also a voltage crossing, // at the expense of a combinational path from the sink to the source and back to the sink. { require (depth > 0 && isPow2(depth)) require (sync >= 2) val bits = log2Ceil(depth) val wires = if (narrow) 1 else depth } object AsyncQueueParams { // When there is only one entry, we don't need narrow. def singleton(sync: Int = 3, safe: Boolean = true) = AsyncQueueParams(1, sync, safe, false) } class AsyncBundleSafety extends Bundle { val ridx_valid = Input (Bool()) val widx_valid = Output(Bool()) val source_reset_n = Output(Bool()) val sink_reset_n = Input (Bool()) } class AsyncBundle[T <: Data](private val gen: T, val params: AsyncQueueParams = AsyncQueueParams()) extends Bundle { // Data-path synchronization val mem = Output(Vec(params.wires, gen)) val ridx = Input (UInt((params.bits+1).W)) val widx = Output(UInt((params.bits+1).W)) val index = params.narrow.option(Input(UInt(params.bits.W))) // Signals used to self-stabilize a safe AsyncQueue val safe = params.safe.option(new AsyncBundleSafety) } object GrayCounter { def apply(bits: Int, increment: Bool = true.B, clear: Bool = false.B, name: String = "binary"): UInt = { val incremented = Wire(UInt(bits.W)) val binary = RegNext(next=incremented, init=0.U).suggestName(name) incremented := Mux(clear, 0.U, binary + increment.asUInt) incremented ^ (incremented >> 1) } } class AsyncValidSync(sync: Int, desc: String) extends RawModule { val io = IO(new Bundle { val in = Input(Bool()) val out = Output(Bool()) }) val clock = IO(Input(Clock())) val reset = IO(Input(AsyncReset())) withClockAndReset(clock, reset){ io.out := AsyncResetSynchronizerShiftReg(io.in, sync, Some(desc)) } } class AsyncQueueSource[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module { override def desiredName = s"AsyncQueueSource_${gen.typeName}" val io = IO(new Bundle { // These come from the source domain val enq = Flipped(Decoupled(gen)) // These cross to the sink clock domain val async = new AsyncBundle(gen, params) }) val bits = params.bits val sink_ready = WireInit(true.B) val mem = Reg(Vec(params.depth, gen)) // This does NOT need to be reset at all. val widx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.enq.fire, !sink_ready, "widx_bin")) val ridx = AsyncResetSynchronizerShiftReg(io.async.ridx, params.sync, Some("ridx_gray")) val ready = sink_ready && widx =/= (ridx ^ (params.depth | params.depth >> 1).U) val index = if (bits == 0) 0.U else io.async.widx(bits-1, 0) ^ (io.async.widx(bits, bits) << (bits-1)) when (io.enq.fire) { mem(index) := io.enq.bits } val ready_reg = withReset(reset.asAsyncReset)(RegNext(next=ready, init=false.B).suggestName("ready_reg")) io.enq.ready := ready_reg && sink_ready val widx_reg = withReset(reset.asAsyncReset)(RegNext(next=widx, init=0.U).suggestName("widx_gray")) io.async.widx := widx_reg io.async.index match { case Some(index) => io.async.mem(0) := mem(index) case None => io.async.mem := mem } io.async.safe.foreach { sio => val source_valid_0 = Module(new AsyncValidSync(params.sync, "source_valid_0")) val source_valid_1 = Module(new AsyncValidSync(params.sync, "source_valid_1")) val sink_extend = Module(new AsyncValidSync(params.sync, "sink_extend")) val sink_valid = Module(new AsyncValidSync(params.sync, "sink_valid")) source_valid_0.reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset source_valid_1.reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset sink_extend .reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset sink_valid .reset := reset.asAsyncReset source_valid_0.clock := clock source_valid_1.clock := clock sink_extend .clock := clock sink_valid .clock := clock source_valid_0.io.in := true.B source_valid_1.io.in := source_valid_0.io.out sio.widx_valid := source_valid_1.io.out sink_extend.io.in := sio.ridx_valid sink_valid.io.in := sink_extend.io.out sink_ready := sink_valid.io.out sio.source_reset_n := !reset.asBool // Assert that if there is stuff in the queue, then reset cannot happen // Impossible to write because dequeue can occur on the receiving side, // then reset allowed to happen, but write side cannot know that dequeue // occurred. // TODO: write some sort of sanity check assertion for users // that denote don't reset when there is activity // assert (!(reset || !sio.sink_reset_n) || !io.enq.valid, "Enqueue while sink is reset and AsyncQueueSource is unprotected") // assert (!reset_rise || prev_idx_match.asBool, "Sink reset while AsyncQueueSource not empty") } } class AsyncQueueSink[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module { override def desiredName = s"AsyncQueueSink_${gen.typeName}" val io = IO(new Bundle { // These come from the sink domain val deq = Decoupled(gen) // These cross to the source clock domain val async = Flipped(new AsyncBundle(gen, params)) }) val bits = params.bits val source_ready = WireInit(true.B) val ridx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.deq.fire, !source_ready, "ridx_bin")) val widx = AsyncResetSynchronizerShiftReg(io.async.widx, params.sync, Some("widx_gray")) val valid = source_ready && ridx =/= widx // The mux is safe because timing analysis ensures ridx has reached the register // On an ASIC, changes to the unread location cannot affect the selected value // On an FPGA, only one input changes at a time => mem updates don't cause glitches // The register only latches when the selected valued is not being written val index = if (bits == 0) 0.U else ridx(bits-1, 0) ^ (ridx(bits, bits) << (bits-1)) io.async.index.foreach { _ := index } // This register does not NEED to be reset, as its contents will not // be considered unless the asynchronously reset deq valid register is set. // It is possible that bits latches when the source domain is reset / has power cut // This is safe, because isolation gates brought mem low before the zeroed widx reached us val deq_bits_nxt = io.async.mem(if (params.narrow) 0.U else index) io.deq.bits := ClockCrossingReg(deq_bits_nxt, en = valid, doInit = false, name = Some("deq_bits_reg")) val valid_reg = withReset(reset.asAsyncReset)(RegNext(next=valid, init=false.B).suggestName("valid_reg")) io.deq.valid := valid_reg && source_ready val ridx_reg = withReset(reset.asAsyncReset)(RegNext(next=ridx, init=0.U).suggestName("ridx_gray")) io.async.ridx := ridx_reg io.async.safe.foreach { sio => val sink_valid_0 = Module(new AsyncValidSync(params.sync, "sink_valid_0")) val sink_valid_1 = Module(new AsyncValidSync(params.sync, "sink_valid_1")) val source_extend = Module(new AsyncValidSync(params.sync, "source_extend")) val source_valid = Module(new AsyncValidSync(params.sync, "source_valid")) sink_valid_0 .reset := (reset.asBool || !sio.source_reset_n).asAsyncReset sink_valid_1 .reset := (reset.asBool || !sio.source_reset_n).asAsyncReset source_extend.reset := (reset.asBool || !sio.source_reset_n).asAsyncReset source_valid .reset := reset.asAsyncReset sink_valid_0 .clock := clock sink_valid_1 .clock := clock source_extend.clock := clock source_valid .clock := clock sink_valid_0.io.in := true.B sink_valid_1.io.in := sink_valid_0.io.out sio.ridx_valid := sink_valid_1.io.out source_extend.io.in := sio.widx_valid source_valid.io.in := source_extend.io.out source_ready := source_valid.io.out sio.sink_reset_n := !reset.asBool // TODO: write some sort of sanity check assertion for users // that denote don't reset when there is activity // // val reset_and_extend = !source_ready || !sio.source_reset_n || reset.asBool // val reset_and_extend_prev = RegNext(reset_and_extend, true.B) // val reset_rise = !reset_and_extend_prev && reset_and_extend // val prev_idx_match = AsyncResetReg(updateData=(io.async.widx===io.async.ridx), resetData=0) // assert (!reset_rise || prev_idx_match.asBool, "Source reset while AsyncQueueSink not empty") } } object FromAsyncBundle { // Sometimes it makes sense for the sink to have different sync than the source def apply[T <: Data](x: AsyncBundle[T]): DecoupledIO[T] = apply(x, x.params.sync) def apply[T <: Data](x: AsyncBundle[T], sync: Int): DecoupledIO[T] = { val sink = Module(new AsyncQueueSink(chiselTypeOf(x.mem(0)), x.params.copy(sync = sync))) sink.io.async <> x sink.io.deq } } object ToAsyncBundle { def apply[T <: Data](x: ReadyValidIO[T], params: AsyncQueueParams = AsyncQueueParams()): AsyncBundle[T] = { val source = Module(new AsyncQueueSource(chiselTypeOf(x.bits), params)) source.io.enq <> x source.io.async } } class AsyncQueue[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Crossing[T] { val io = IO(new CrossingIO(gen)) val source = withClockAndReset(io.enq_clock, io.enq_reset) { Module(new AsyncQueueSource(gen, params)) } val sink = withClockAndReset(io.deq_clock, io.deq_reset) { Module(new AsyncQueueSink (gen, params)) } source.io.enq <> io.enq io.deq <> sink.io.deq sink.io.async <> source.io.async }

module AsyncQueueSink_Phit( // @[AsyncQueue.scala:136:7] input clock, // @[AsyncQueue.scala:136:7] input reset, // @[AsyncQueue.scala:136:7] input io_deq_ready, // @[AsyncQueue.scala:139:14] output io_deq_valid, // @[AsyncQueue.scala:139:14] output [31:0] io_deq_bits_phit, // @[AsyncQueue.scala:139:14] input [31:0] io_async_mem_0_phit, // @[AsyncQueue.scala:139:14] input [31:0] io_async_mem_1_phit, // @[AsyncQueue.scala:139:14] input [31:0] io_async_mem_2_phit, // @[AsyncQueue.scala:139:14] input [31:0] io_async_mem_3_phit, // @[AsyncQueue.scala:139:14] input [31:0] io_async_mem_4_phit, // @[AsyncQueue.scala:139:14] input [31:0] io_async_mem_5_phit, // @[AsyncQueue.scala:139:14] input [31:0] io_async_mem_6_phit, // @[AsyncQueue.scala:139:14] input [31:0] io_async_mem_7_phit, // @[AsyncQueue.scala:139:14] output [3:0] io_async_ridx, // @[AsyncQueue.scala:139:14] input [3:0] io_async_widx, // @[AsyncQueue.scala:139:14] output io_async_safe_ridx_valid, // @[AsyncQueue.scala:139:14] input io_async_safe_widx_valid, // @[AsyncQueue.scala:139:14] input io_async_safe_source_reset_n, // @[AsyncQueue.scala:139:14] output io_async_safe_sink_reset_n // @[AsyncQueue.scala:139:14] ); wire _source_extend_io_out; // @[AsyncQueue.scala:175:31] wire _sink_valid_0_io_out; // @[AsyncQueue.scala:172:33] wire io_deq_ready_0 = io_deq_ready; // @[AsyncQueue.scala:136:7] wire [31:0] io_async_mem_0_phit_0 = io_async_mem_0_phit; // @[AsyncQueue.scala:136:7] wire [31:0] io_async_mem_1_phit_0 = io_async_mem_1_phit; // @[AsyncQueue.scala:136:7] wire [31:0] io_async_mem_2_phit_0 = io_async_mem_2_phit; // @[AsyncQueue.scala:136:7] wire [31:0] io_async_mem_3_phit_0 = io_async_mem_3_phit; // @[AsyncQueue.scala:136:7] wire [31:0] io_async_mem_4_phit_0 = io_async_mem_4_phit; // @[AsyncQueue.scala:136:7] wire [31:0] io_async_mem_5_phit_0 = io_async_mem_5_phit; // @[AsyncQueue.scala:136:7] wire [31:0] io_async_mem_6_phit_0 = io_async_mem_6_phit; // @[AsyncQueue.scala:136:7] wire [31:0] io_async_mem_7_phit_0 = io_async_mem_7_phit; // @[AsyncQueue.scala:136:7] wire [3:0] io_async_widx_0 = io_async_widx; // @[AsyncQueue.scala:136:7] wire io_async_safe_widx_valid_0 = io_async_safe_widx_valid; // @[AsyncQueue.scala:136:7] wire io_async_safe_source_reset_n_0 = io_async_safe_source_reset_n; // @[AsyncQueue.scala:136:7] wire _ridx_T = reset; // @[AsyncQueue.scala:148:30] wire _valid_reg_T = reset; // @[AsyncQueue.scala:165:35] wire _ridx_reg_T = reset; // @[AsyncQueue.scala:168:34] wire _sink_valid_0_reset_T = reset; // @[AsyncQueue.scala:177:35] wire _sink_valid_1_reset_T = reset; // @[AsyncQueue.scala:178:35] wire _source_extend_reset_T = reset; // @[AsyncQueue.scala:179:35] wire _source_valid_reset_T = reset; // @[AsyncQueue.scala:180:34] wire _io_async_safe_sink_reset_n_T = reset; // @[AsyncQueue.scala:193:32] wire _io_deq_valid_T; // @[AsyncQueue.scala:166:29] wire [31:0] _io_deq_bits_WIRE_phit; // @[SynchronizerReg.scala:211:26] wire _io_async_safe_sink_reset_n_T_1; // @[AsyncQueue.scala:193:25] wire [31:0] io_deq_bits_phit_0; // @[AsyncQueue.scala:136:7] wire io_deq_valid_0; // @[AsyncQueue.scala:136:7] wire io_async_safe_ridx_valid_0; // @[AsyncQueue.scala:136:7] wire io_async_safe_sink_reset_n_0; // @[AsyncQueue.scala:136:7] wire [3:0] io_async_ridx_0; // @[AsyncQueue.scala:136:7] wire source_ready; // @[AsyncQueue.scala:147:30] wire _ridx_T_1 = io_deq_ready_0 & io_deq_valid_0; // @[Decoupled.scala:51:35] wire _ridx_T_2 = ~source_ready; // @[AsyncQueue.scala:147:30, :148:77] wire [3:0] _ridx_incremented_T_2; // @[AsyncQueue.scala:53:23] wire [3:0] ridx_incremented; // @[AsyncQueue.scala:51:27] reg [3:0] ridx_ridx_bin; // @[AsyncQueue.scala:52:25] wire [4:0] _ridx_incremented_T = {1'h0, ridx_ridx_bin} + {4'h0, _ridx_T_1}; // @[Decoupled.scala:51:35] wire [3:0] _ridx_incremented_T_1 = _ridx_incremented_T[3:0]; // @[AsyncQueue.scala:53:43] assign _ridx_incremented_T_2 = _ridx_T_2 ? 4'h0 : _ridx_incremented_T_1; // @[AsyncQueue.scala:52:25, :53:{23,43}, :148:77] assign ridx_incremented = _ridx_incremented_T_2; // @[AsyncQueue.scala:51:27, :53:23] wire [2:0] _ridx_T_3 = ridx_incremented[3:1]; // @[AsyncQueue.scala:51:27, :54:32] wire [3:0] ridx = {ridx_incremented[3], ridx_incremented[2:0] ^ _ridx_T_3}; // @[AsyncQueue.scala:51:27, :54:{17,32}] wire [3:0] widx; // @[ShiftReg.scala:48:24] wire _valid_T = ridx != widx; // @[ShiftReg.scala:48:24] wire valid = source_ready & _valid_T; // @[AsyncQueue.scala:147:30, :150:{28,36}] wire [2:0] _index_T = ridx[2:0]; // @[AsyncQueue.scala:54:17, :156:43] wire _index_T_1 = ridx[3]; // @[AsyncQueue.scala:54:17, :156:62] wire [2:0] _index_T_2 = {_index_T_1, 2'h0}; // @[AsyncQueue.scala:156:{62,75}] wire [2:0] index = _index_T ^ _index_T_2; // @[AsyncQueue.scala:156:{43,55,75}] wire [7:0][31:0] _GEN = {{io_async_mem_7_phit_0}, {io_async_mem_6_phit_0}, {io_async_mem_5_phit_0}, {io_async_mem_4_phit_0}, {io_async_mem_3_phit_0}, {io_async_mem_2_phit_0}, {io_async_mem_1_phit_0}, {io_async_mem_0_phit_0}}; // @[SynchronizerReg.scala:209:18] wire [31:0] _io_deq_bits_T; // @[SynchronizerReg.scala:211:26] assign io_deq_bits_phit_0 = _io_deq_bits_WIRE_phit; // @[SynchronizerReg.scala:211:26] wire [31:0] _io_deq_bits_WIRE_1; // @[SynchronizerReg.scala:211:26] assign _io_deq_bits_T = _io_deq_bits_WIRE_1; // @[SynchronizerReg.scala:211:26] assign _io_deq_bits_WIRE_phit = _io_deq_bits_T; // @[SynchronizerReg.scala:211:26] reg valid_reg; // @[AsyncQueue.scala:165:56] assign _io_deq_valid_T = valid_reg & source_ready; // @[AsyncQueue.scala:147:30, :165:56, :166:29] assign io_deq_valid_0 = _io_deq_valid_T; // @[AsyncQueue.scala:136:7, :166:29] reg [3:0] ridx_gray; // @[AsyncQueue.scala:168:55] assign io_async_ridx_0 = ridx_gray; // @[AsyncQueue.scala:136:7, :168:55] wire _sink_valid_0_reset_T_1 = ~io_async_safe_source_reset_n_0; // @[AsyncQueue.scala:136:7, :177:45] wire _sink_valid_0_reset_T_2 = _sink_valid_0_reset_T | _sink_valid_0_reset_T_1; // @[AsyncQueue.scala:177:{35,42,45}] wire _sink_valid_0_reset_T_3 = _sink_valid_0_reset_T_2; // @[AsyncQueue.scala:177:{42,66}] wire _sink_valid_1_reset_T_1 = ~io_async_safe_source_reset_n_0; // @[AsyncQueue.scala:136:7, :177:45, :178:45] wire _sink_valid_1_reset_T_2 = _sink_valid_1_reset_T | _sink_valid_1_reset_T_1; // @[AsyncQueue.scala:178:{35,42,45}] wire _sink_valid_1_reset_T_3 = _sink_valid_1_reset_T_2; // @[AsyncQueue.scala:178:{42,66}] wire _source_extend_reset_T_1 = ~io_async_safe_source_reset_n_0; // @[AsyncQueue.scala:136:7, :177:45, :179:45] wire _source_extend_reset_T_2 = _source_extend_reset_T | _source_extend_reset_T_1; // @[AsyncQueue.scala:179:{35,42,45}] wire _source_extend_reset_T_3 = _source_extend_reset_T_2; // @[AsyncQueue.scala:179:{42,66}] assign _io_async_safe_sink_reset_n_T_1 = ~_io_async_safe_sink_reset_n_T; // @[AsyncQueue.scala:193:{25,32}] assign io_async_safe_sink_reset_n_0 = _io_async_safe_sink_reset_n_T_1; // @[AsyncQueue.scala:136:7, :193:25] always @(posedge clock or posedge _ridx_T) begin // @[AsyncQueue.scala:136:7, :148:30] if (_ridx_T) // @[AsyncQueue.scala:136:7, :148:30] ridx_ridx_bin <= 4'h0; // @[AsyncQueue.scala:52:25] else // @[AsyncQueue.scala:136:7] ridx_ridx_bin <= ridx_incremented; // @[AsyncQueue.scala:51:27, :52:25] always @(posedge, posedge) always @(posedge clock or posedge _valid_reg_T) begin // @[AsyncQueue.scala:136:7, :165:35] if (_valid_reg_T) // @[AsyncQueue.scala:136:7, :165:35] valid_reg <= 1'h0; // @[AsyncQueue.scala:165:56] else // @[AsyncQueue.scala:136:7] valid_reg <= valid; // @[AsyncQueue.scala:150:28, :165:56] always @(posedge, posedge) always @(posedge clock or posedge _ridx_reg_T) begin // @[AsyncQueue.scala:136:7, :168:34] if (_ridx_reg_T) // @[AsyncQueue.scala:136:7, :168:34] ridx_gray <= 4'h0; // @[AsyncQueue.scala:52:25, :168:55] else // @[AsyncQueue.scala:136:7] ridx_gray <= ridx; // @[AsyncQueue.scala:54:17, :168:55] always @(posedge, posedge)

Generate the Verilog code corresponding to the following Chisel files. File Nodes.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.nodes._ import freechips.rocketchip.util.{AsyncQueueParams,RationalDirection} case object TLMonitorBuilder extends Field[TLMonitorArgs => TLMonitorBase](args => new TLMonitor(args)) object TLImp extends NodeImp[TLMasterPortParameters, TLSlavePortParameters, TLEdgeOut, TLEdgeIn, TLBundle] { def edgeO(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeOut(pd, pu, p, sourceInfo) def edgeI(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeIn (pd, pu, p, sourceInfo) def bundleO(eo: TLEdgeOut) = TLBundle(eo.bundle) def bundleI(ei: TLEdgeIn) = TLBundle(ei.bundle) def render(ei: TLEdgeIn) = RenderedEdge(colour = "#000000" /* black */, label = (ei.manager.beatBytes * 8).toString) override def monitor(bundle: TLBundle, edge: TLEdgeIn): Unit = { val monitor = Module(edge.params(TLMonitorBuilder)(TLMonitorArgs(edge))) monitor.io.in := bundle } override def mixO(pd: TLMasterPortParameters, node: OutwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLMasterPortParameters = pd.v1copy(clients = pd.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }) override def mixI(pu: TLSlavePortParameters, node: InwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLSlavePortParameters = pu.v1copy(managers = pu.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }) } trait TLFormatNode extends FormatNode[TLEdgeIn, TLEdgeOut] case class TLClientNode(portParams: Seq[TLMasterPortParameters])(implicit valName: ValName) extends SourceNode(TLImp)(portParams) with TLFormatNode case class TLManagerNode(portParams: Seq[TLSlavePortParameters])(implicit valName: ValName) extends SinkNode(TLImp)(portParams) with TLFormatNode case class TLAdapterNode( clientFn: TLMasterPortParameters => TLMasterPortParameters = { s => s }, managerFn: TLSlavePortParameters => TLSlavePortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLImp)(clientFn, managerFn) with TLFormatNode case class TLJunctionNode( clientFn: Seq[TLMasterPortParameters] => Seq[TLMasterPortParameters], managerFn: Seq[TLSlavePortParameters] => Seq[TLSlavePortParameters])( implicit valName: ValName) extends JunctionNode(TLImp)(clientFn, managerFn) with TLFormatNode case class TLIdentityNode()(implicit valName: ValName) extends IdentityNode(TLImp)() with TLFormatNode object TLNameNode { def apply(name: ValName) = TLIdentityNode()(name) def apply(name: Option[String]): TLIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLIdentityNode = apply(Some(name)) } case class TLEphemeralNode()(implicit valName: ValName) extends EphemeralNode(TLImp)() object TLTempNode { def apply(): TLEphemeralNode = TLEphemeralNode()(ValName("temp")) } case class TLNexusNode( clientFn: Seq[TLMasterPortParameters] => TLMasterPortParameters, managerFn: Seq[TLSlavePortParameters] => TLSlavePortParameters)( implicit valName: ValName) extends NexusNode(TLImp)(clientFn, managerFn) with TLFormatNode abstract class TLCustomNode(implicit valName: ValName) extends CustomNode(TLImp) with TLFormatNode // Asynchronous crossings trait TLAsyncFormatNode extends FormatNode[TLAsyncEdgeParameters, TLAsyncEdgeParameters] object TLAsyncImp extends SimpleNodeImp[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncEdgeParameters, TLAsyncBundle] { def edge(pd: TLAsyncClientPortParameters, pu: TLAsyncManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLAsyncEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLAsyncEdgeParameters) = new TLAsyncBundle(e.bundle) def render(e: TLAsyncEdgeParameters) = RenderedEdge(colour = "#ff0000" /* red */, label = e.manager.async.depth.toString) override def mixO(pd: TLAsyncClientPortParameters, node: OutwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLAsyncManagerPortParameters, node: InwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLAsyncAdapterNode( clientFn: TLAsyncClientPortParameters => TLAsyncClientPortParameters = { s => s }, managerFn: TLAsyncManagerPortParameters => TLAsyncManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLAsyncImp)(clientFn, managerFn) with TLAsyncFormatNode case class TLAsyncIdentityNode()(implicit valName: ValName) extends IdentityNode(TLAsyncImp)() with TLAsyncFormatNode object TLAsyncNameNode { def apply(name: ValName) = TLAsyncIdentityNode()(name) def apply(name: Option[String]): TLAsyncIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLAsyncIdentityNode = apply(Some(name)) } case class TLAsyncSourceNode(sync: Option[Int])(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLAsyncImp)( dFn = { p => TLAsyncClientPortParameters(p) }, uFn = { p => p.base.v1copy(minLatency = p.base.minLatency + sync.getOrElse(p.async.sync)) }) with FormatNode[TLEdgeIn, TLAsyncEdgeParameters] // discard cycles in other clock domain case class TLAsyncSinkNode(async: AsyncQueueParams)(implicit valName: ValName) extends MixedAdapterNode(TLAsyncImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = p.base.minLatency + async.sync) }, uFn = { p => TLAsyncManagerPortParameters(async, p) }) with FormatNode[TLAsyncEdgeParameters, TLEdgeOut] // Rationally related crossings trait TLRationalFormatNode extends FormatNode[TLRationalEdgeParameters, TLRationalEdgeParameters] object TLRationalImp extends SimpleNodeImp[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalEdgeParameters, TLRationalBundle] { def edge(pd: TLRationalClientPortParameters, pu: TLRationalManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLRationalEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLRationalEdgeParameters) = new TLRationalBundle(e.bundle) def render(e: TLRationalEdgeParameters) = RenderedEdge(colour = "#00ff00" /* green */) override def mixO(pd: TLRationalClientPortParameters, node: OutwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLRationalManagerPortParameters, node: InwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLRationalAdapterNode( clientFn: TLRationalClientPortParameters => TLRationalClientPortParameters = { s => s }, managerFn: TLRationalManagerPortParameters => TLRationalManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLRationalImp)(clientFn, managerFn) with TLRationalFormatNode case class TLRationalIdentityNode()(implicit valName: ValName) extends IdentityNode(TLRationalImp)() with TLRationalFormatNode object TLRationalNameNode { def apply(name: ValName) = TLRationalIdentityNode()(name) def apply(name: Option[String]): TLRationalIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLRationalIdentityNode = apply(Some(name)) } case class TLRationalSourceNode()(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLRationalImp)( dFn = { p => TLRationalClientPortParameters(p) }, uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLRationalEdgeParameters] // discard cycles from other clock domain case class TLRationalSinkNode(direction: RationalDirection)(implicit valName: ValName) extends MixedAdapterNode(TLRationalImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = 1) }, uFn = { p => TLRationalManagerPortParameters(direction, p) }) with FormatNode[TLRationalEdgeParameters, TLEdgeOut] // Credited version of TileLink channels trait TLCreditedFormatNode extends FormatNode[TLCreditedEdgeParameters, TLCreditedEdgeParameters] object TLCreditedImp extends SimpleNodeImp[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedEdgeParameters, TLCreditedBundle] { def edge(pd: TLCreditedClientPortParameters, pu: TLCreditedManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLCreditedEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLCreditedEdgeParameters) = new TLCreditedBundle(e.bundle) def render(e: TLCreditedEdgeParameters) = RenderedEdge(colour = "#ffff00" /* yellow */, e.delay.toString) override def mixO(pd: TLCreditedClientPortParameters, node: OutwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLCreditedManagerPortParameters, node: InwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLCreditedAdapterNode( clientFn: TLCreditedClientPortParameters => TLCreditedClientPortParameters = { s => s }, managerFn: TLCreditedManagerPortParameters => TLCreditedManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLCreditedImp)(clientFn, managerFn) with TLCreditedFormatNode case class TLCreditedIdentityNode()(implicit valName: ValName) extends IdentityNode(TLCreditedImp)() with TLCreditedFormatNode object TLCreditedNameNode { def apply(name: ValName) = TLCreditedIdentityNode()(name) def apply(name: Option[String]): TLCreditedIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLCreditedIdentityNode = apply(Some(name)) } case class TLCreditedSourceNode(delay: TLCreditedDelay)(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLCreditedImp)( dFn = { p => TLCreditedClientPortParameters(delay, p) }, uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLCreditedEdgeParameters] // discard cycles from other clock domain case class TLCreditedSinkNode(delay: TLCreditedDelay)(implicit valName: ValName) extends MixedAdapterNode(TLCreditedImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = 1) }, uFn = { p => TLCreditedManagerPortParameters(delay, p) }) with FormatNode[TLCreditedEdgeParameters, TLEdgeOut] File RegisterRouter.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.nodes._ import freechips.rocketchip.diplomacy.{AddressSet, TransferSizes} import freechips.rocketchip.resources.{Device, Resource, ResourceBindings} import freechips.rocketchip.prci.{NoCrossing} import freechips.rocketchip.regmapper.{RegField, RegMapper, RegMapperParams, RegMapperInput, RegisterRouter} import freechips.rocketchip.util.{BundleField, ControlKey, ElaborationArtefacts, GenRegDescsAnno} import scala.math.min class TLRegisterRouterExtraBundle(val sourceBits: Int, val sizeBits: Int) extends Bundle { val source = UInt((sourceBits max 1).W) val size = UInt((sizeBits max 1).W) } case object TLRegisterRouterExtra extends ControlKey[TLRegisterRouterExtraBundle]("tlrr_extra") case class TLRegisterRouterExtraField(sourceBits: Int, sizeBits: Int) extends BundleField[TLRegisterRouterExtraBundle](TLRegisterRouterExtra, Output(new TLRegisterRouterExtraBundle(sourceBits, sizeBits)), x => { x.size := 0.U x.source := 0.U }) /** TLRegisterNode is a specialized TL SinkNode that encapsulates MMIO registers. * It provides functionality for describing and outputting metdata about the registers in several formats. * It also provides a concrete implementation of a regmap function that will be used * to wire a map of internal registers associated with this node to the node's interconnect port. */ case class TLRegisterNode( address: Seq[AddressSet], device: Device, deviceKey: String = "reg/control", concurrency: Int = 0, beatBytes: Int = 4, undefZero: Boolean = true, executable: Boolean = false)( implicit valName: ValName) extends SinkNode(TLImp)(Seq(TLSlavePortParameters.v1( Seq(TLSlaveParameters.v1( address = address, resources = Seq(Resource(device, deviceKey)), executable = executable, supportsGet = TransferSizes(1, beatBytes), supportsPutPartial = TransferSizes(1, beatBytes), supportsPutFull = TransferSizes(1, beatBytes), fifoId = Some(0))), // requests are handled in order beatBytes = beatBytes, minLatency = min(concurrency, 1)))) with TLFormatNode // the Queue adds at most one cycle { val size = 1 << log2Ceil(1 + address.map(_.max).max - address.map(_.base).min) require (size >= beatBytes) address.foreach { case a => require (a.widen(size-1).base == address.head.widen(size-1).base, s"TLRegisterNode addresses (${address}) must be aligned to its size ${size}") } // Calling this method causes the matching TL2 bundle to be // configured to route all requests to the listed RegFields. def regmap(mapping: RegField.Map*) = { val (bundleIn, edge) = this.in(0) val a = bundleIn.a val d = bundleIn.d val fields = TLRegisterRouterExtraField(edge.bundle.sourceBits, edge.bundle.sizeBits) +: a.bits.params.echoFields val params = RegMapperParams(log2Up(size/beatBytes), beatBytes, fields) val in = Wire(Decoupled(new RegMapperInput(params))) in.bits.read := a.bits.opcode === TLMessages.Get in.bits.index := edge.addr_hi(a.bits) in.bits.data := a.bits.data in.bits.mask := a.bits.mask Connectable.waiveUnmatched(in.bits.extra, a.bits.echo) match { case (lhs, rhs) => lhs :<= rhs } val a_extra = in.bits.extra(TLRegisterRouterExtra) a_extra.source := a.bits.source a_extra.size := a.bits.size // Invoke the register map builder val out = RegMapper(beatBytes, concurrency, undefZero, in, mapping:_*) // No flow control needed in.valid := a.valid a.ready := in.ready d.valid := out.valid out.ready := d.ready // We must restore the size to enable width adapters to work val d_extra = out.bits.extra(TLRegisterRouterExtra) d.bits := edge.AccessAck(toSource = d_extra.source, lgSize = d_extra.size) // avoid a Mux on the data bus by manually overriding two fields d.bits.data := out.bits.data Connectable.waiveUnmatched(d.bits.echo, out.bits.extra) match { case (lhs, rhs) => lhs :<= rhs } d.bits.opcode := Mux(out.bits.read, TLMessages.AccessAckData, TLMessages.AccessAck) // Tie off unused channels bundleIn.b.valid := false.B bundleIn.c.ready := true.B bundleIn.e.ready := true.B genRegDescsJson(mapping:_*) } def genRegDescsJson(mapping: RegField.Map*): Unit = { // Dump out the register map for documentation purposes. val base = address.head.base val baseHex = s"0x${base.toInt.toHexString}" val name = s"${device.describe(ResourceBindings()).name}.At${baseHex}" val json = GenRegDescsAnno.serialize(base, name, mapping:_*) var suffix = 0 while( ElaborationArtefacts.contains(s"${baseHex}.${suffix}.regmap.json")) { suffix = suffix + 1 } ElaborationArtefacts.add(s"${baseHex}.${suffix}.regmap.json", json) val module = Module.currentModule.get.asInstanceOf[RawModule] GenRegDescsAnno.anno( module, base, mapping:_*) } } /** Mix HasTLControlRegMap into any subclass of RegisterRouter to gain helper functions for attaching a device control register map to TileLink. * - The intended use case is that controlNode will diplomatically publish a SW-visible device's memory-mapped control registers. * - Use the clock crossing helper controlXing to externally connect controlNode to a TileLink interconnect. * - Use the mapping helper function regmap to internally fill out the space of device control registers. */ trait HasTLControlRegMap { this: RegisterRouter => protected val controlNode = TLRegisterNode( address = address, device = device, deviceKey = "reg/control", concurrency = concurrency, beatBytes = beatBytes, undefZero = undefZero, executable = executable) // Externally, this helper should be used to connect the register control port to a bus val controlXing: TLInwardClockCrossingHelper = this.crossIn(controlNode) // Backwards-compatibility default node accessor with no clock crossing lazy val node: TLInwardNode = controlXing(NoCrossing) // Internally, this function should be used to populate the control port with registers protected def regmap(mapping: RegField.Map*): Unit = { controlNode.regmap(mapping:_*) } } File TileResetSetter.scala: package chipyard.clocking import chisel3._ import chisel3.util._ import chisel3.experimental.Analog import org.chipsalliance.cde.config._ import freechips.rocketchip.subsystem._ import freechips.rocketchip.diplomacy._ import freechips.rocketchip.prci._ import freechips.rocketchip.util._ import freechips.rocketchip.tilelink._ import freechips.rocketchip.devices.tilelink._ import freechips.rocketchip.regmapper._ import freechips.rocketchip.subsystem._ // Currently only works if all tiles are already driven by independent clock groups // TODO: After https://github.com/chipsalliance/rocket-chip/pull/2842 is merged, we should // always put all tiles on independent clock groups class TileResetSetter(address: BigInt, beatBytes: Int, tileNames: Seq[String], initResetHarts: Seq[Int])(implicit p: Parameters) extends LazyModule { val device = new SimpleDevice("tile-reset-setter", Nil) val tlNode = TLRegisterNode(Seq(AddressSet(address, 4096-1)), device, "reg/control", beatBytes=beatBytes) val clockNode = ClockGroupIdentityNode() lazy val module = new LazyModuleImp(this) { val nTiles = p(TilesLocated(InSubsystem)).size require (nTiles <= 4096 / 4) val tile_async_resets = Wire(Vec(nTiles, Reset())) val r_tile_resets = (0 until nTiles).map({ i => tile_async_resets(i) := true.B.asAsyncReset // Remove this line after https://github.com/chipsalliance/rocket-chip/pull/2842 withReset (tile_async_resets(i)) { Module(new AsyncResetRegVec(w=1, init=(if (initResetHarts.contains(i)) 1 else 0))) } }) if (nTiles > 0) tlNode.regmap((0 until nTiles).map({ i => i * 4 -> Seq(RegField.rwReg(1, r_tile_resets(i).io)) }): _*) val tileMap = tileNames.zipWithIndex.map({ case (n, i) => n -> (tile_async_resets(i), r_tile_resets(i).io.q, address + i * 4) }) (clockNode.out zip clockNode.in).map { case ((o, _), (i, _)) => (o.member.elements zip i.member.elements).foreach { case ((name, oD), (_, iD)) => oD.clock := iD.clock oD.reset := iD.reset for ((n, (rIn, rOut, addr)) <- tileMap) { if (name.contains(n)) { println(s"${addr.toString(16)}: Tile $name reset control") // Async because the reset coming out of the AsyncResetRegVec is // clocked to the bus this is attached to, not the clock in this // clock bundle. We expect a ClockGroupResetSynchronizer downstream // to synchronize the resets // Also, this or enforces that the tiles come out of reset after the reset of the system oD.reset := (rOut.asBool || iD.reset.asBool).asAsyncReset rIn := iD.reset } } } } } } File MuxLiteral.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util.log2Ceil import scala.reflect.ClassTag /* MuxLiteral creates a lookup table from a key to a list of values. * Unlike MuxLookup, the table keys must be exclusive literals. */ object MuxLiteral { def apply[T <: Data:ClassTag](index: UInt, default: T, first: (UInt, T), rest: (UInt, T)*): T = apply(index, default, first :: rest.toList) def apply[T <: Data:ClassTag](index: UInt, default: T, cases: Seq[(UInt, T)]): T = MuxTable(index, default, cases.map { case (k, v) => (k.litValue, v) }) } object MuxSeq { def apply[T <: Data:ClassTag](index: UInt, default: T, first: T, rest: T*): T = apply(index, default, first :: rest.toList) def apply[T <: Data:ClassTag](index: UInt, default: T, cases: Seq[T]): T = MuxTable(index, default, cases.zipWithIndex.map { case (v, i) => (BigInt(i), v) }) } object MuxTable { def apply[T <: Data:ClassTag](index: UInt, default: T, first: (BigInt, T), rest: (BigInt, T)*): T = apply(index, default, first :: rest.toList) def apply[T <: Data:ClassTag](index: UInt, default: T, cases: Seq[(BigInt, T)]): T = { /* All keys must be >= 0 and distinct */ cases.foreach { case (k, _) => require (k >= 0) } require (cases.map(_._1).distinct.size == cases.size) /* Filter out any cases identical to the default */ val simple = cases.filter { case (k, v) => !default.isLit || !v.isLit || v.litValue != default.litValue } val maxKey = (BigInt(0) +: simple.map(_._1)).max val endIndex = BigInt(1) << log2Ceil(maxKey+1) if (simple.isEmpty) { default } else if (endIndex <= 2*simple.size) { /* The dense encoding case uses a Vec */ val table = Array.fill(endIndex.toInt) { default } simple.foreach { case (k, v) => table(k.toInt) = v } Mux(index >= endIndex.U, default, VecInit(table)(index)) } else { /* The sparse encoding case uses switch */ val out = WireDefault(default) simple.foldLeft(new chisel3.util.SwitchContext(index, None, Set.empty)) { case (acc, (k, v)) => acc.is (k.U) { out := v } } out } } } File LazyModuleImp.scala: package org.chipsalliance.diplomacy.lazymodule import chisel3.{withClockAndReset, Module, RawModule, Reset, _} import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo} import firrtl.passes.InlineAnnotation import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.nodes.Dangle import scala.collection.immutable.SortedMap /** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]]. * * This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy. */ sealed trait LazyModuleImpLike extends RawModule { /** [[LazyModule]] that contains this instance. */ val wrapper: LazyModule /** IOs that will be automatically "punched" for this instance. */ val auto: AutoBundle /** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */ protected[diplomacy] val dangles: Seq[Dangle] // [[wrapper.module]] had better not be accessed while LazyModules are still being built! require( LazyModule.scope.isEmpty, s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}" ) /** Set module name. Defaults to the containing LazyModule's desiredName. */ override def desiredName: String = wrapper.desiredName suggestName(wrapper.suggestedName) /** [[Parameters]] for chisel [[Module]]s. */ implicit val p: Parameters = wrapper.p /** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and * submodules. */ protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = { // 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]], // 2. return [[Dangle]]s from each module. val childDangles = wrapper.children.reverse.flatMap { c => implicit val sourceInfo: SourceInfo = c.info c.cloneProto.map { cp => // If the child is a clone, then recursively set cloneProto of its children as well def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = { require(bases.size == clones.size) (bases.zip(clones)).map { case (l, r) => require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}") l.cloneProto = Some(r) assignCloneProtos(l.children, r.children) } } assignCloneProtos(c.children, cp.children) // Clone the child module as a record, and get its [[AutoBundle]] val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName) val clonedAuto = clone("auto").asInstanceOf[AutoBundle] // Get the empty [[Dangle]]'s of the cloned child val rawDangles = c.cloneDangles() require(rawDangles.size == clonedAuto.elements.size) // Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) } dangles }.getOrElse { // For non-clones, instantiate the child module val mod = try { Module(c.module) } catch { case e: ChiselException => { println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}") throw e } } mod.dangles } } // Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]]. // This will result in a sequence of [[Dangle]] from these [[BaseNode]]s. val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate()) // Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]] val allDangles = nodeDangles ++ childDangles // Group [[allDangles]] by their [[source]]. val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*) // For each [[source]] set of [[Dangle]]s of size 2, ensure that these // can be connected as a source-sink pair (have opposite flipped value). // Make the connection and mark them as [[done]]. val done = Set() ++ pairing.values.filter(_.size == 2).map { case Seq(a, b) => require(a.flipped != b.flipped) // @todo <> in chisel3 makes directionless connection. if (a.flipped) { a.data <> b.data } else { b.data <> a.data } a.source case _ => None } // Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module. val forward = allDangles.filter(d => !done(d.source)) // Generate [[AutoBundle]] IO from [[forward]]. val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*)) // Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]] val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) => if (d.flipped) { d.data <> io } else { io <> d.data } d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name) } // Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]]. wrapper.inModuleBody.reverse.foreach { _() } if (wrapper.shouldBeInlined) { chisel3.experimental.annotate(new ChiselAnnotation { def toFirrtl = InlineAnnotation(toNamed) }) } // Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]]. (auto, dangles) } } /** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike { /** Instantiate hardware of this `Module`. */ val (auto, dangles) = instantiate() } /** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike { // These wires are the default clock+reset for all LazyModule children. // It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the // [[LazyRawModuleImp]] children. // Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly. /** drive clock explicitly. */ val childClock: Clock = Wire(Clock()) /** drive reset explicitly. */ val childReset: Reset = Wire(Reset()) // the default is that these are disabled childClock := false.B.asClock childReset := chisel3.DontCare def provideImplicitClockToLazyChildren: Boolean = false val (auto, dangles) = if (provideImplicitClockToLazyChildren) { withClockAndReset(childClock, childReset) { instantiate() } } else { instantiate() } } File MixedNode.scala: package org.chipsalliance.diplomacy.nodes import chisel3.{Data, DontCare, Wire} import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.{Field, Parameters} import org.chipsalliance.diplomacy.ValName import org.chipsalliance.diplomacy.sourceLine /** One side metadata of a [[Dangle]]. * * Describes one side of an edge going into or out of a [[BaseNode]]. * * @param serial * the global [[BaseNode.serial]] number of the [[BaseNode]] that this [[HalfEdge]] connects to. * @param index * the `index` in the [[BaseNode]]'s input or output port list that this [[HalfEdge]] belongs to. */ case class HalfEdge(serial: Int, index: Int) extends Ordered[HalfEdge] { import scala.math.Ordered.orderingToOrdered def compare(that: HalfEdge): Int = HalfEdge.unapply(this).compare(HalfEdge.unapply(that)) } /** [[Dangle]] captures the `IO` information of a [[LazyModule]] and which two [[BaseNode]]s the [[Edges]]/[[Bundle]] * connects. * * [[Dangle]]s are generated by [[BaseNode.instantiate]] using [[MixedNode.danglesOut]] and [[MixedNode.danglesIn]] , * [[LazyModuleImp.instantiate]] connects those that go to internal or explicit IO connections in a [[LazyModule]]. * * @param source * the source [[HalfEdge]] of this [[Dangle]], which captures the source [[BaseNode]] and the port `index` within * that [[BaseNode]]. * @param sink * sink [[HalfEdge]] of this [[Dangle]], which captures the sink [[BaseNode]] and the port `index` within that * [[BaseNode]]. * @param flipped * flip or not in [[AutoBundle.makeElements]]. If true this corresponds to `danglesOut`, if false it corresponds to * `danglesIn`. * @param dataOpt * actual [[Data]] for the hardware connection. Can be empty if this belongs to a cloned module */ case class Dangle(source: HalfEdge, sink: HalfEdge, flipped: Boolean, name: String, dataOpt: Option[Data]) { def data = dataOpt.get } /** [[Edges]] is a collection of parameters describing the functionality and connection for an interface, which is often * derived from the interconnection protocol and can inform the parameterization of the hardware bundles that actually * implement the protocol. */ case class Edges[EI, EO](in: Seq[EI], out: Seq[EO]) /** A field available in [[Parameters]] used to determine whether [[InwardNodeImp.monitor]] will be called. */ case object MonitorsEnabled extends Field[Boolean](true) /** When rendering the edge in a graphical format, flip the order in which the edges' source and sink are presented. * * For example, when rendering graphML, yEd by default tries to put the source node vertically above the sink node, but * [[RenderFlipped]] inverts this relationship. When a particular [[LazyModule]] contains both source nodes and sink * nodes, flipping the rendering of one node's edge will usual produce a more concise visual layout for the * [[LazyModule]]. */ case object RenderFlipped extends Field[Boolean](false) /** The sealed node class in the package, all node are derived from it. * * @param inner * Sink interface implementation. * @param outer * Source interface implementation. * @param valName * val name of this node. * @tparam DI * Downward-flowing parameters received on the inner side of the node. It is usually a brunch of parameters * describing the protocol parameters from a source. For an [[InwardNode]], it is determined by the connected * [[OutwardNode]]. Since it can be connected to multiple sources, this parameter is always a Seq of source port * parameters. * @tparam UI * Upward-flowing parameters generated by the inner side of the node. It is usually a brunch of parameters describing * the protocol parameters of a sink. For an [[InwardNode]], it is determined itself. * @tparam EI * Edge Parameters describing a connection on the inner side of the node. It is usually a brunch of transfers * specified for a sink according to protocol. * @tparam BI * Bundle type used when connecting to the inner side of the node. It is a hardware interface of this sink interface. * It should extends from [[chisel3.Data]], which represents the real hardware. * @tparam DO * Downward-flowing parameters generated on the outer side of the node. It is usually a brunch of parameters * describing the protocol parameters of a source. For an [[OutwardNode]], it is determined itself. * @tparam UO * Upward-flowing parameters received by the outer side of the node. It is usually a brunch of parameters describing * the protocol parameters from a sink. For an [[OutwardNode]], it is determined by the connected [[InwardNode]]. * Since it can be connected to multiple sinks, this parameter is always a Seq of sink port parameters. * @tparam EO * Edge Parameters describing a connection on the outer side of the node. It is usually a brunch of transfers * specified for a source according to protocol. * @tparam BO * Bundle type used when connecting to the outer side of the node. It is a hardware interface of this source * interface. It should extends from [[chisel3.Data]], which represents the real hardware. * * @note * Call Graph of [[MixedNode]] * - line `─`: source is process by a function and generate pass to others * - Arrow `→`: target of arrow is generated by source * * {{{ * (from the other node) * ┌─────────────────────────────────────────────────────────[[InwardNode.uiParams]]─────────────┐ * ↓ │ * (binding node when elaboration) [[OutwardNode.uoParams]]────────────────────────[[MixedNode.mapParamsU]]→──────────┐ │ * [[InwardNode.accPI]] │ │ │ * │ │ (based on protocol) │ * │ │ [[MixedNode.inner.edgeI]] │ * │ │ ↓ │ * ↓ │ │ │ * (immobilize after elaboration) (inward port from [[OutwardNode]]) │ ↓ │ * [[InwardNode.iBindings]]──┐ [[MixedNode.iDirectPorts]]────────────────────→[[MixedNode.iPorts]] [[InwardNode.uiParams]] │ * │ │ ↑ │ │ │ * │ │ │ [[OutwardNode.doParams]] │ │ * │ │ │ (from the other node) │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * │ │ │ └────────┬──────────────┤ │ * │ │ │ │ │ │ * │ │ │ │ (based on protocol) │ * │ │ │ │ [[MixedNode.inner.edgeI]] │ * │ │ │ │ │ │ * │ │ (from the other node) │ ↓ │ * │ └───[[OutwardNode.oPortMapping]] [[OutwardNode.oStar]] │ [[MixedNode.edgesIn]]───┐ │ * │ ↑ ↑ │ │ ↓ │ * │ │ │ │ │ [[MixedNode.in]] │ * │ │ │ │ ↓ ↑ │ * │ (solve star connection) │ │ │ [[MixedNode.bundleIn]]──┘ │ * ├───[[MixedNode.resolveStar]]→─┼─────────────────────────────┤ └────────────────────────────────────┐ │ * │ │ │ [[MixedNode.bundleOut]]─┐ │ │ * │ │ │ ↑ ↓ │ │ * │ │ │ │ [[MixedNode.out]] │ │ * │ ↓ ↓ │ ↑ │ │ * │ ┌─────[[InwardNode.iPortMapping]] [[InwardNode.iStar]] [[MixedNode.edgesOut]]──┘ │ │ * │ │ (from the other node) ↑ │ │ * │ │ │ │ │ │ * │ │ │ [[MixedNode.outer.edgeO]] │ │ * │ │ │ (based on protocol) │ │ * │ │ │ │ │ │ * │ │ │ ┌────────────────────────────────────────┤ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * (immobilize after elaboration)│ ↓ │ │ │ │ * [[OutwardNode.oBindings]]─┘ [[MixedNode.oDirectPorts]]───→[[MixedNode.oPorts]] [[OutwardNode.doParams]] │ │ * ↑ (inward port from [[OutwardNode]]) │ │ │ │ * │ ┌─────────────────────────────────────────┤ │ │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * [[OutwardNode.accPO]] │ ↓ │ │ │ * (binding node when elaboration) │ [[InwardNode.diParams]]─────→[[MixedNode.mapParamsD]]────────────────────────────┘ │ │ * │ ↑ │ │ * │ └──────────────────────────────────────────────────────────────────────────────────────────┘ │ * └──────────────────────────────────────────────────────────────────────────────────────────────────────────┘ * }}} */ abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data]( val inner: InwardNodeImp[DI, UI, EI, BI], val outer: OutwardNodeImp[DO, UO, EO, BO] )( implicit valName: ValName) extends BaseNode with NodeHandle[DI, UI, EI, BI, DO, UO, EO, BO] with InwardNode[DI, UI, BI] with OutwardNode[DO, UO, BO] { // Generate a [[NodeHandle]] with inward and outward node are both this node. val inward = this val outward = this /** Debug info of nodes binding. */ def bindingInfo: String = s"""$iBindingInfo |$oBindingInfo |""".stripMargin /** Debug info of ports connecting. */ def connectedPortsInfo: String = s"""${oPorts.size} outward ports connected: [${oPorts.map(_._2.name).mkString(",")}] |${iPorts.size} inward ports connected: [${iPorts.map(_._2.name).mkString(",")}] |""".stripMargin /** Debug info of parameters propagations. */ def parametersInfo: String = s"""${doParams.size} downstream outward parameters: [${doParams.mkString(",")}] |${uoParams.size} upstream outward parameters: [${uoParams.mkString(",")}] |${diParams.size} downstream inward parameters: [${diParams.mkString(",")}] |${uiParams.size} upstream inward parameters: [${uiParams.mkString(",")}] |""".stripMargin /** For a given node, converts [[OutwardNode.accPO]] and [[InwardNode.accPI]] to [[MixedNode.oPortMapping]] and * [[MixedNode.iPortMapping]]. * * Given counts of known inward and outward binding and inward and outward star bindings, return the resolved inward * stars and outward stars. * * This method will also validate the arguments and throw a runtime error if the values are unsuitable for this type * of node. * * @param iKnown * Number of known-size ([[BIND_ONCE]]) input bindings. * @param oKnown * Number of known-size ([[BIND_ONCE]]) output bindings. * @param iStar * Number of unknown size ([[BIND_STAR]]) input bindings. * @param oStar * Number of unknown size ([[BIND_STAR]]) output bindings. * @return * A Tuple of the resolved number of input and output connections. */ protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStar: Int, oStar: Int): (Int, Int) /** Function to generate downward-flowing outward params from the downward-flowing input params and the current output * ports. * * @param n * The size of the output sequence to generate. * @param p * Sequence of downward-flowing input parameters of this node. * @return * A `n`-sized sequence of downward-flowing output edge parameters. */ protected[diplomacy] def mapParamsD(n: Int, p: Seq[DI]): Seq[DO] /** Function to generate upward-flowing input parameters from the upward-flowing output parameters [[uiParams]]. * * @param n * Size of the output sequence. * @param p * Upward-flowing output edge parameters. * @return * A n-sized sequence of upward-flowing input edge parameters. */ protected[diplomacy] def mapParamsU(n: Int, p: Seq[UO]): Seq[UI] /** @return * The sink cardinality of the node, the number of outputs bound with [[BIND_QUERY]] summed with inputs bound with * [[BIND_STAR]]. */ protected[diplomacy] lazy val sinkCard: Int = oBindings.count(_._3 == BIND_QUERY) + iBindings.count(_._3 == BIND_STAR) /** @return * The source cardinality of this node, the number of inputs bound with [[BIND_QUERY]] summed with the number of * output bindings bound with [[BIND_STAR]]. */ protected[diplomacy] lazy val sourceCard: Int = iBindings.count(_._3 == BIND_QUERY) + oBindings.count(_._3 == BIND_STAR) /** @return list of nodes involved in flex bindings with this node. */ protected[diplomacy] lazy val flexes: Seq[BaseNode] = oBindings.filter(_._3 == BIND_FLEX).map(_._2) ++ iBindings.filter(_._3 == BIND_FLEX).map(_._2) /** Resolves the flex to be either source or sink and returns the offset where the [[BIND_STAR]] operators begin * greedily taking up the remaining connections. * * @return * A value >= 0 if it is sink cardinality, a negative value for source cardinality. The magnitude of the return * value is not relevant. */ protected[diplomacy] lazy val flexOffset: Int = { /** Recursively performs a depth-first search of the [[flexes]], [[BaseNode]]s connected to this node with flex * operators. The algorithm bottoms out when we either get to a node we have already visited or when we get to a * connection that is not a flex and can set the direction for us. Otherwise, recurse by visiting the `flexes` of * each node in the current set and decide whether they should be added to the set or not. * * @return * the mapping of [[BaseNode]] indexed by their serial numbers. */ def DFS(v: BaseNode, visited: Map[Int, BaseNode]): Map[Int, BaseNode] = { if (visited.contains(v.serial) || !v.flexibleArityDirection) { visited } else { v.flexes.foldLeft(visited + (v.serial -> v))((sum, n) => DFS(n, sum)) } } /** Determine which [[BaseNode]] are involved in resolving the flex connections to/from this node. * * @example * {{{ * a :*=* b :*=* c * d :*=* b * e :*=* f * }}} * * `flexSet` for `a`, `b`, `c`, or `d` will be `Set(a, b, c, d)` `flexSet` for `e` or `f` will be `Set(e,f)` */ val flexSet = DFS(this, Map()).values /** The total number of :*= operators where we're on the left. */ val allSink = flexSet.map(_.sinkCard).sum /** The total number of :=* operators used when we're on the right. */ val allSource = flexSet.map(_.sourceCard).sum require( allSink == 0 || allSource == 0, s"The nodes ${flexSet.map(_.name)} which are inter-connected by :*=* have ${allSink} :*= operators and ${allSource} :=* operators connected to them, making it impossible to determine cardinality inference direction." ) allSink - allSource } /** @return A value >= 0 if it is sink cardinality, a negative value for source cardinality. */ protected[diplomacy] def edgeArityDirection(n: BaseNode): Int = { if (flexibleArityDirection) flexOffset else if (n.flexibleArityDirection) n.flexOffset else 0 } /** For a node which is connected between two nodes, select the one that will influence the direction of the flex * resolution. */ protected[diplomacy] def edgeAritySelect(n: BaseNode, l: => Int, r: => Int): Int = { val dir = edgeArityDirection(n) if (dir < 0) l else if (dir > 0) r else 1 } /** Ensure that the same node is not visited twice in resolving `:*=`, etc operators. */ private var starCycleGuard = false /** Resolve all the star operators into concrete indicies. As connections are being made, some may be "star" * connections which need to be resolved. In some way to determine how many actual edges they correspond to. We also * need to build up the ranges of edges which correspond to each binding operator, so that We can apply the correct * edge parameters and later build up correct bundle connections. * * [[oPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that oPort (binding * operator). [[iPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that iPort * (binding operator). [[oStar]]: `Int` the value to return for this node `N` for any `N :*= foo` or `N :*=* foo :*= * bar` [[iStar]]: `Int` the value to return for this node `N` for any `foo :=* N` or `bar :=* foo :*=* N` */ protected[diplomacy] lazy val ( oPortMapping: Seq[(Int, Int)], iPortMapping: Seq[(Int, Int)], oStar: Int, iStar: Int ) = { try { if (starCycleGuard) throw StarCycleException() starCycleGuard = true // For a given node N... // Number of foo :=* N // + Number of bar :=* foo :*=* N val oStars = oBindings.count { case (_, n, b, _, _) => b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) < 0) } // Number of N :*= foo // + Number of N :*=* foo :*= bar val iStars = iBindings.count { case (_, n, b, _, _) => b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) > 0) } // 1 for foo := N // + bar.iStar for bar :*= foo :*=* N // + foo.iStar for foo :*= N // + 0 for foo :=* N val oKnown = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, 0, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => 0 } }.sum // 1 for N := foo // + bar.oStar for N :*=* foo :=* bar // + foo.oStar for N :=* foo // + 0 for N :*= foo val iKnown = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, 0) case BIND_QUERY => n.oStar case BIND_STAR => 0 } }.sum // Resolve star depends on the node subclass to implement the algorithm for this. val (iStar, oStar) = resolveStar(iKnown, oKnown, iStars, oStars) // Cumulative list of resolved outward binding range starting points val oSum = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, oStar, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => oStar } }.scanLeft(0)(_ + _) // Cumulative list of resolved inward binding range starting points val iSum = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, iStar) case BIND_QUERY => n.oStar case BIND_STAR => iStar } }.scanLeft(0)(_ + _) // Create ranges for each binding based on the running sums and return // those along with resolved values for the star operations. (oSum.init.zip(oSum.tail), iSum.init.zip(iSum.tail), oStar, iStar) } catch { case c: StarCycleException => throw c.copy(loop = context +: c.loop) } } /** Sequence of inward ports. * * This should be called after all star bindings are resolved. * * Each element is: `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. * `n` Instance of inward node. `p` View of [[Parameters]] where this connection was made. `s` Source info where this * connection was made in the source code. */ protected[diplomacy] lazy val oDirectPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oBindings.flatMap { case (i, n, _, p, s) => // for each binding operator in this node, look at what it connects to val (start, end) = n.iPortMapping(i) (start until end).map { j => (j, n, p, s) } } /** Sequence of outward ports. * * This should be called after all star bindings are resolved. * * `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. `n` Instance of * outward node. `p` View of [[Parameters]] where this connection was made. `s` [[SourceInfo]] where this connection * was made in the source code. */ protected[diplomacy] lazy val iDirectPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iBindings.flatMap { case (i, n, _, p, s) => // query this port index range of this node in the other side of node. val (start, end) = n.oPortMapping(i) (start until end).map { j => (j, n, p, s) } } // Ephemeral nodes ( which have non-None iForward/oForward) have in_degree = out_degree // Thus, there must exist an Eulerian path and the below algorithms terminate @scala.annotation.tailrec private def oTrace( tuple: (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) ): (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.iForward(i) match { case None => (i, n, p, s) case Some((j, m)) => oTrace((j, m, p, s)) } } @scala.annotation.tailrec private def iTrace( tuple: (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) ): (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.oForward(i) match { case None => (i, n, p, s) case Some((j, m)) => iTrace((j, m, p, s)) } } /** Final output ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - Numeric index of this binding in the [[InwardNode]] on the other end. * - [[InwardNode]] on the other end of this binding. * - A view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. */ lazy val oPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oDirectPorts.map(oTrace) /** Final input ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - numeric index of this binding in [[OutwardNode]] on the other end. * - [[OutwardNode]] on the other end of this binding. * - a view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. */ lazy val iPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iDirectPorts.map(iTrace) private var oParamsCycleGuard = false protected[diplomacy] lazy val diParams: Seq[DI] = iPorts.map { case (i, n, _, _) => n.doParams(i) } protected[diplomacy] lazy val doParams: Seq[DO] = { try { if (oParamsCycleGuard) throw DownwardCycleException() oParamsCycleGuard = true val o = mapParamsD(oPorts.size, diParams) require( o.size == oPorts.size, s"""Diplomacy has detected a problem with your graph: |At the following node, the number of outward ports should equal the number of produced outward parameters. |$context |$connectedPortsInfo |Downstreamed inward parameters: [${diParams.mkString(",")}] |Produced outward parameters: [${o.mkString(",")}] |""".stripMargin ) o.map(outer.mixO(_, this)) } catch { case c: DownwardCycleException => throw c.copy(loop = context +: c.loop) } } private var iParamsCycleGuard = false protected[diplomacy] lazy val uoParams: Seq[UO] = oPorts.map { case (o, n, _, _) => n.uiParams(o) } protected[diplomacy] lazy val uiParams: Seq[UI] = { try { if (iParamsCycleGuard) throw UpwardCycleException() iParamsCycleGuard = true val i = mapParamsU(iPorts.size, uoParams) require( i.size == iPorts.size, s"""Diplomacy has detected a problem with your graph: |At the following node, the number of inward ports should equal the number of produced inward parameters. |$context |$connectedPortsInfo |Upstreamed outward parameters: [${uoParams.mkString(",")}] |Produced inward parameters: [${i.mkString(",")}] |""".stripMargin ) i.map(inner.mixI(_, this)) } catch { case c: UpwardCycleException => throw c.copy(loop = context +: c.loop) } } /** Outward edge parameters. */ protected[diplomacy] lazy val edgesOut: Seq[EO] = (oPorts.zip(doParams)).map { case ((i, n, p, s), o) => outer.edgeO(o, n.uiParams(i), p, s) } /** Inward edge parameters. */ protected[diplomacy] lazy val edgesIn: Seq[EI] = (iPorts.zip(uiParams)).map { case ((o, n, p, s), i) => inner.edgeI(n.doParams(o), i, p, s) } /** A tuple of the input edge parameters and output edge parameters for the edges bound to this node. * * If you need to access to the edges of a foreign Node, use this method (in/out create bundles). */ lazy val edges: Edges[EI, EO] = Edges(edgesIn, edgesOut) /** Create actual Wires corresponding to the Bundles parameterized by the outward edges of this node. */ protected[diplomacy] lazy val bundleOut: Seq[BO] = edgesOut.map { e => val x = Wire(outer.bundleO(e)).suggestName(s"${valName.value}Out") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } /** Create actual Wires corresponding to the Bundles parameterized by the inward edges of this node. */ protected[diplomacy] lazy val bundleIn: Seq[BI] = edgesIn.map { e => val x = Wire(inner.bundleI(e)).suggestName(s"${valName.value}In") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } private def emptyDanglesOut: Seq[Dangle] = oPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(serial, i), sink = HalfEdge(n.serial, j), flipped = false, name = wirePrefix + "out", dataOpt = None ) } private def emptyDanglesIn: Seq[Dangle] = iPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(n.serial, j), sink = HalfEdge(serial, i), flipped = true, name = wirePrefix + "in", dataOpt = None ) } /** Create the [[Dangle]]s which describe the connections from this node output to other nodes inputs. */ protected[diplomacy] def danglesOut: Seq[Dangle] = emptyDanglesOut.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleOut(i))) } /** Create the [[Dangle]]s which describe the connections from this node input from other nodes outputs. */ protected[diplomacy] def danglesIn: Seq[Dangle] = emptyDanglesIn.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleIn(i))) } private[diplomacy] var instantiated = false /** Gather Bundle and edge parameters of outward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. */ def out: Seq[(BO, EO)] = { require( instantiated, s"$name.out should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleOut.zip(edgesOut) } /** Gather Bundle and edge parameters of inward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. */ def in: Seq[(BI, EI)] = { require( instantiated, s"$name.in should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleIn.zip(edgesIn) } /** Actually instantiate this node during [[LazyModuleImp]] evaluation. Mark that it's safe to use the Bundle wires, * instantiate monitors on all input ports if appropriate, and return all the dangles of this node. */ protected[diplomacy] def instantiate(): Seq[Dangle] = { instantiated = true if (!circuitIdentity) { (iPorts.zip(in)).foreach { case ((_, _, p, _), (b, e)) => if (p(MonitorsEnabled)) inner.monitor(b, e) } } danglesOut ++ danglesIn } protected[diplomacy] def cloneDangles(): Seq[Dangle] = emptyDanglesOut ++ emptyDanglesIn /** Connects the outward part of a node with the inward part of this node. */ protected[diplomacy] def bind( h: OutwardNode[DI, UI, BI], binding: NodeBinding )( implicit p: Parameters, sourceInfo: SourceInfo ): Unit = { val x = this // x := y val y = h sourceLine(sourceInfo, " at ", "") val i = x.iPushed val o = y.oPushed y.oPush( i, x, binding match { case BIND_ONCE => BIND_ONCE case BIND_FLEX => BIND_FLEX case BIND_STAR => BIND_QUERY case BIND_QUERY => BIND_STAR } ) x.iPush(o, y, binding) } /* Metadata for printing the node graph. */ def inputs: Seq[(OutwardNode[DI, UI, BI], RenderedEdge)] = (iPorts.zip(edgesIn)).map { case ((_, n, p, _), e) => val re = inner.render(e) (n, re.copy(flipped = re.flipped != p(RenderFlipped))) } /** Metadata for printing the node graph */ def outputs: Seq[(InwardNode[DO, UO, BO], RenderedEdge)] = oPorts.map { case (i, n, _, _) => (n, n.inputs(i)._2) } } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) || !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.ProbeAckData || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode | small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U || beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }

module TileResetSetter( // @[TileResetSetter.scala:26:25] input clock, // @[TileResetSetter.scala:26:25] input reset, // @[TileResetSetter.scala:26:25] input auto_clock_in_member_allClocks_uncore_clock, // @[LazyModuleImp.scala:107:25] input auto_clock_in_member_allClocks_uncore_reset, // @[LazyModuleImp.scala:107:25] output auto_clock_out_member_allClocks_uncore_clock, // @[LazyModuleImp.scala:107:25] output auto_clock_out_member_allClocks_uncore_reset, // @[LazyModuleImp.scala:107:25] output auto_tl_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_tl_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_tl_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_tl_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [1:0] auto_tl_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [10:0] auto_tl_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [20:0] auto_tl_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_tl_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_tl_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_tl_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_tl_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_tl_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_tl_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_tl_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [10:0] auto_tl_in_d_bits_source // @[LazyModuleImp.scala:107:25] ); wire out_front_valid; // @[RegisterRouter.scala:87:24] wire out_front_ready; // @[RegisterRouter.scala:87:24] wire out_bits_read; // @[RegisterRouter.scala:87:24] wire [10:0] out_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:87:24] wire [8:0] in_bits_index; // @[RegisterRouter.scala:73:18] wire in_bits_read; // @[RegisterRouter.scala:73:18] wire auto_clock_in_member_allClocks_uncore_clock_0 = auto_clock_in_member_allClocks_uncore_clock; // @[TileResetSetter.scala:26:25] wire auto_clock_in_member_allClocks_uncore_reset_0 = auto_clock_in_member_allClocks_uncore_reset; // @[TileResetSetter.scala:26:25] wire auto_tl_in_a_valid_0 = auto_tl_in_a_valid; // @[TileResetSetter.scala:26:25] wire [2:0] auto_tl_in_a_bits_opcode_0 = auto_tl_in_a_bits_opcode; // @[TileResetSetter.scala:26:25] wire [2:0] auto_tl_in_a_bits_param_0 = auto_tl_in_a_bits_param; // @[TileResetSetter.scala:26:25] wire [1:0] auto_tl_in_a_bits_size_0 = auto_tl_in_a_bits_size; // @[TileResetSetter.scala:26:25] wire [10:0] auto_tl_in_a_bits_source_0 = auto_tl_in_a_bits_source; // @[TileResetSetter.scala:26:25] wire [20:0] auto_tl_in_a_bits_address_0 = auto_tl_in_a_bits_address; // @[TileResetSetter.scala:26:25] wire [7:0] auto_tl_in_a_bits_mask_0 = auto_tl_in_a_bits_mask; // @[TileResetSetter.scala:26:25] wire [63:0] auto_tl_in_a_bits_data_0 = auto_tl_in_a_bits_data; // @[TileResetSetter.scala:26:25] wire auto_tl_in_a_bits_corrupt_0 = auto_tl_in_a_bits_corrupt; // @[TileResetSetter.scala:26:25] wire auto_tl_in_d_ready_0 = auto_tl_in_d_ready; // @[TileResetSetter.scala:26:25] wire [1:0] _out_frontSel_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _out_backSel_T = 2'h1; // @[OneHot.scala:58:35] wire [8:0] out_maskMatch = 9'h1FF; // @[RegisterRouter.scala:87:24] wire tile_async_resets_0 = 1'h1; // @[TileResetSetter.scala:29:33] wire _tile_async_resets_0_T = 1'h1; // @[TileResetSetter.scala:31:38] wire out_frontSel_0 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_backSel_0 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_5 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48] wire out_rifireMux = 1'h1; // @[MuxLiteral.scala:49:10] wire out_wifireMux_out = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_6 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48] wire out_wifireMux = 1'h1; // @[MuxLiteral.scala:49:10] wire out_rofireMux_out = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_5 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48] wire out_rofireMux = 1'h1; // @[MuxLiteral.scala:49:10] wire out_wofireMux_out = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_6 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48] wire out_wofireMux = 1'h1; // @[MuxLiteral.scala:49:10] wire out_iready = 1'h1; // @[RegisterRouter.scala:87:24] wire out_oready = 1'h1; // @[RegisterRouter.scala:87:24] wire [2:0] tlNodeIn_d_bits_d_opcode = 3'h0; // @[Edges.scala:792:17] wire [1:0] auto_tl_in_d_bits_param = 2'h0; // @[TileResetSetter.scala:26:25] wire [1:0] tlNodeIn_d_bits_param = 2'h0; // @[MixedNode.scala:551:17] wire [1:0] tlNodeIn_d_bits_d_param = 2'h0; // @[Edges.scala:792:17] wire auto_tl_in_d_bits_sink = 1'h0; // @[TileResetSetter.scala:26:25] wire auto_tl_in_d_bits_denied = 1'h0; // @[TileResetSetter.scala:26:25] wire auto_tl_in_d_bits_corrupt = 1'h0; // @[TileResetSetter.scala:26:25] wire tlNodeIn_d_bits_sink = 1'h0; // @[MixedNode.scala:551:17] wire tlNodeIn_d_bits_denied = 1'h0; // @[MixedNode.scala:551:17] wire tlNodeIn_d_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17] wire _out_T_7 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_T_8 = 1'h0; // @[RegisterRouter.scala:87:24] wire out_frontSel_1 = 1'h0; // @[RegisterRouter.scala:87:24] wire out_backSel_1 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_6 = 1'h0; // @[MuxLiteral.scala:49:17] wire _out_wifireMux_T_7 = 1'h0; // @[MuxLiteral.scala:49:17] wire _out_rofireMux_T_6 = 1'h0; // @[MuxLiteral.scala:49:17] wire _out_wofireMux_T_7 = 1'h0; // @[MuxLiteral.scala:49:17] wire _out_out_bits_data_T = 1'h0; // @[MuxLiteral.scala:49:17] wire _out_out_bits_data_T_2 = 1'h0; // @[MuxLiteral.scala:49:17] wire _out_out_bits_data_WIRE_1_0 = 1'h0; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_T_3 = 1'h0; // @[MuxLiteral.scala:49:10] wire _out_out_bits_data_T_4 = 1'h0; // @[RegisterRouter.scala:87:24] wire tlNodeIn_d_bits_d_sink = 1'h0; // @[Edges.scala:792:17] wire tlNodeIn_d_bits_d_denied = 1'h0; // @[Edges.scala:792:17] wire tlNodeIn_d_bits_d_corrupt = 1'h0; // @[Edges.scala:792:17] wire [63:0] auto_tl_in_d_bits_data = 64'h0; // @[TileResetSetter.scala:26:25] wire [63:0] tlNodeIn_d_bits_data = 64'h0; // @[MixedNode.scala:551:17] wire [63:0] out_bits_data = 64'h0; // @[RegisterRouter.scala:87:24] wire [63:0] tlNodeIn_d_bits_d_data = 64'h0; // @[Edges.scala:792:17] wire clockNodeIn_member_allClocks_uncore_clock = auto_clock_in_member_allClocks_uncore_clock_0; // @[MixedNode.scala:551:17] wire clockNodeOut_member_allClocks_uncore_clock; // @[MixedNode.scala:542:17] wire clockNodeIn_member_allClocks_uncore_reset = auto_clock_in_member_allClocks_uncore_reset_0; // @[MixedNode.scala:551:17] wire clockNodeOut_member_allClocks_uncore_reset; // @[MixedNode.scala:542:17] wire tlNodeIn_a_ready; // @[MixedNode.scala:551:17] wire tlNodeIn_a_valid = auto_tl_in_a_valid_0; // @[MixedNode.scala:551:17] wire [2:0] tlNodeIn_a_bits_opcode = auto_tl_in_a_bits_opcode_0; // @[MixedNode.scala:551:17] wire [2:0] tlNodeIn_a_bits_param = auto_tl_in_a_bits_param_0; // @[MixedNode.scala:551:17] wire [1:0] tlNodeIn_a_bits_size = auto_tl_in_a_bits_size_0; // @[MixedNode.scala:551:17] wire [10:0] tlNodeIn_a_bits_source = auto_tl_in_a_bits_source_0; // @[MixedNode.scala:551:17] wire [20:0] tlNodeIn_a_bits_address = auto_tl_in_a_bits_address_0; // @[MixedNode.scala:551:17] wire [7:0] tlNodeIn_a_bits_mask = auto_tl_in_a_bits_mask_0; // @[MixedNode.scala:551:17] wire [63:0] tlNodeIn_a_bits_data = auto_tl_in_a_bits_data_0; // @[MixedNode.scala:551:17] wire tlNodeIn_a_bits_corrupt = auto_tl_in_a_bits_corrupt_0; // @[MixedNode.scala:551:17] wire tlNodeIn_d_ready = auto_tl_in_d_ready_0; // @[MixedNode.scala:551:17] wire tlNodeIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] tlNodeIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] tlNodeIn_d_bits_size; // @[MixedNode.scala:551:17] wire [10:0] tlNodeIn_d_bits_source; // @[MixedNode.scala:551:17] wire auto_clock_out_member_allClocks_uncore_clock_0; // @[TileResetSetter.scala:26:25] wire auto_clock_out_member_allClocks_uncore_reset_0; // @[TileResetSetter.scala:26:25] wire auto_tl_in_a_ready_0; // @[TileResetSetter.scala:26:25] wire [2:0] auto_tl_in_d_bits_opcode_0; // @[TileResetSetter.scala:26:25] wire [1:0] auto_tl_in_d_bits_size_0; // @[TileResetSetter.scala:26:25] wire [10:0] auto_tl_in_d_bits_source_0; // @[TileResetSetter.scala:26:25] wire auto_tl_in_d_valid_0; // @[TileResetSetter.scala:26:25] wire in_ready; // @[RegisterRouter.scala:73:18] assign auto_tl_in_a_ready_0 = tlNodeIn_a_ready; // @[MixedNode.scala:551:17] wire in_valid = tlNodeIn_a_valid; // @[RegisterRouter.scala:73:18] wire [1:0] in_bits_extra_tlrr_extra_size = tlNodeIn_a_bits_size; // @[RegisterRouter.scala:73:18] wire [10:0] in_bits_extra_tlrr_extra_source = tlNodeIn_a_bits_source; // @[RegisterRouter.scala:73:18] wire [7:0] in_bits_mask = tlNodeIn_a_bits_mask; // @[RegisterRouter.scala:73:18] wire [63:0] in_bits_data = tlNodeIn_a_bits_data; // @[RegisterRouter.scala:73:18] wire out_ready = tlNodeIn_d_ready; // @[RegisterRouter.scala:87:24] wire out_valid; // @[RegisterRouter.scala:87:24] assign auto_tl_in_d_valid_0 = tlNodeIn_d_valid; // @[MixedNode.scala:551:17] assign auto_tl_in_d_bits_opcode_0 = tlNodeIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] tlNodeIn_d_bits_d_size; // @[Edges.scala:792:17] assign auto_tl_in_d_bits_size_0 = tlNodeIn_d_bits_size; // @[MixedNode.scala:551:17] wire [10:0] tlNodeIn_d_bits_d_source; // @[Edges.scala:792:17] assign auto_tl_in_d_bits_source_0 = tlNodeIn_d_bits_source; // @[MixedNode.scala:551:17] assign auto_clock_out_member_allClocks_uncore_clock_0 = clockNodeOut_member_allClocks_uncore_clock; // @[MixedNode.scala:542:17] assign auto_clock_out_member_allClocks_uncore_reset_0 = clockNodeOut_member_allClocks_uncore_reset; // @[MixedNode.scala:542:17] assign clockNodeOut_member_allClocks_uncore_clock = clockNodeIn_member_allClocks_uncore_clock; // @[MixedNode.scala:542:17, :551:17] assign clockNodeOut_member_allClocks_uncore_reset = clockNodeIn_member_allClocks_uncore_reset; // @[MixedNode.scala:542:17, :551:17] wire _out_in_ready_T; // @[RegisterRouter.scala:87:24] assign tlNodeIn_a_ready = in_ready; // @[RegisterRouter.scala:73:18] wire _in_bits_read_T; // @[RegisterRouter.scala:74:36] wire _out_front_valid_T = in_valid; // @[RegisterRouter.scala:73:18, :87:24] wire out_front_bits_read = in_bits_read; // @[RegisterRouter.scala:73:18, :87:24] wire [8:0] out_front_bits_index = in_bits_index; // @[RegisterRouter.scala:73:18, :87:24] wire [63:0] out_front_bits_data = in_bits_data; // @[RegisterRouter.scala:73:18, :87:24] wire [7:0] out_front_bits_mask = in_bits_mask; // @[RegisterRouter.scala:73:18, :87:24] wire [10:0] out_front_bits_extra_tlrr_extra_source = in_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:73:18, :87:24] wire [1:0] out_front_bits_extra_tlrr_extra_size = in_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:73:18, :87:24] assign _in_bits_read_T = tlNodeIn_a_bits_opcode == 3'h4; // @[RegisterRouter.scala:74:36] assign in_bits_read = _in_bits_read_T; // @[RegisterRouter.scala:73:18, :74:36] wire [17:0] _in_bits_index_T = tlNodeIn_a_bits_address[20:3]; // @[Edges.scala:192:34] assign in_bits_index = _in_bits_index_T[8:0]; // @[RegisterRouter.scala:73:18, :75:19] wire _out_front_ready_T = out_ready; // @[RegisterRouter.scala:87:24] wire _out_out_valid_T; // @[RegisterRouter.scala:87:24] assign tlNodeIn_d_valid = out_valid; // @[RegisterRouter.scala:87:24] wire _tlNodeIn_d_bits_opcode_T = out_bits_read; // @[RegisterRouter.scala:87:24, :105:25] assign tlNodeIn_d_bits_d_source = out_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:87:24] wire [1:0] out_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:87:24] assign tlNodeIn_d_bits_d_size = out_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:87:24] assign _out_in_ready_T = out_front_ready; // @[RegisterRouter.scala:87:24] assign _out_out_valid_T = out_front_valid; // @[RegisterRouter.scala:87:24] assign out_bits_read = out_front_bits_read; // @[RegisterRouter.scala:87:24] wire [8:0] out_findex = out_front_bits_index; // @[RegisterRouter.scala:87:24] wire [8:0] out_bindex = out_front_bits_index; // @[RegisterRouter.scala:87:24] assign out_bits_extra_tlrr_extra_source = out_front_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:87:24] assign out_bits_extra_tlrr_extra_size = out_front_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:87:24] wire _out_T = out_findex == 9'h0; // @[RegisterRouter.scala:87:24] wire _out_T_1 = out_bindex == 9'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24] wire _out_out_bits_data_WIRE_0 = _out_T_1; // @[MuxLiteral.scala:49:48] wire out_rivalid_0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24] wire out_wivalid_0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24] wire out_roready_0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24] wire out_woready_0; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T = out_front_bits_mask[0]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T = out_front_bits_mask[0]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_1 = out_front_bits_mask[1]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_1 = out_front_bits_mask[1]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_2 = out_front_bits_mask[2]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_2 = out_front_bits_mask[2]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_3 = out_front_bits_mask[3]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_3 = out_front_bits_mask[3]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_4 = out_front_bits_mask[4]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_4 = out_front_bits_mask[4]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_5 = out_front_bits_mask[5]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_5 = out_front_bits_mask[5]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_6 = out_front_bits_mask[6]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_6 = out_front_bits_mask[6]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_7 = out_front_bits_mask[7]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_7 = out_front_bits_mask[7]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_8 = {8{_out_frontMask_T}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_9 = {8{_out_frontMask_T_1}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_10 = {8{_out_frontMask_T_2}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_11 = {8{_out_frontMask_T_3}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_12 = {8{_out_frontMask_T_4}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_13 = {8{_out_frontMask_T_5}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_14 = {8{_out_frontMask_T_6}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_15 = {8{_out_frontMask_T_7}}; // @[RegisterRouter.scala:87:24] wire [15:0] out_frontMask_lo_lo = {_out_frontMask_T_9, _out_frontMask_T_8}; // @[RegisterRouter.scala:87:24] wire [15:0] out_frontMask_lo_hi = {_out_frontMask_T_11, _out_frontMask_T_10}; // @[RegisterRouter.scala:87:24] wire [31:0] out_frontMask_lo = {out_frontMask_lo_hi, out_frontMask_lo_lo}; // @[RegisterRouter.scala:87:24] wire [15:0] out_frontMask_hi_lo = {_out_frontMask_T_13, _out_frontMask_T_12}; // @[RegisterRouter.scala:87:24] wire [15:0] out_frontMask_hi_hi = {_out_frontMask_T_15, _out_frontMask_T_14}; // @[RegisterRouter.scala:87:24] wire [31:0] out_frontMask_hi = {out_frontMask_hi_hi, out_frontMask_hi_lo}; // @[RegisterRouter.scala:87:24] wire [63:0] out_frontMask = {out_frontMask_hi, out_frontMask_lo}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_8 = {8{_out_backMask_T}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_9 = {8{_out_backMask_T_1}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_10 = {8{_out_backMask_T_2}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_11 = {8{_out_backMask_T_3}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_12 = {8{_out_backMask_T_4}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_13 = {8{_out_backMask_T_5}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_14 = {8{_out_backMask_T_6}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_15 = {8{_out_backMask_T_7}}; // @[RegisterRouter.scala:87:24] wire [15:0] out_backMask_lo_lo = {_out_backMask_T_9, _out_backMask_T_8}; // @[RegisterRouter.scala:87:24] wire [15:0] out_backMask_lo_hi = {_out_backMask_T_11, _out_backMask_T_10}; // @[RegisterRouter.scala:87:24] wire [31:0] out_backMask_lo = {out_backMask_lo_hi, out_backMask_lo_lo}; // @[RegisterRouter.scala:87:24] wire [15:0] out_backMask_hi_lo = {_out_backMask_T_13, _out_backMask_T_12}; // @[RegisterRouter.scala:87:24] wire [15:0] out_backMask_hi_hi = {_out_backMask_T_15, _out_backMask_T_14}; // @[RegisterRouter.scala:87:24] wire [31:0] out_backMask_hi = {out_backMask_hi_hi, out_backMask_hi_lo}; // @[RegisterRouter.scala:87:24] wire [63:0] out_backMask = {out_backMask_hi, out_backMask_lo}; // @[RegisterRouter.scala:87:24] wire _out_rimask_T = out_frontMask[0]; // @[RegisterRouter.scala:87:24] wire _out_wimask_T = out_frontMask[0]; // @[RegisterRouter.scala:87:24] wire out_rimask = _out_rimask_T; // @[RegisterRouter.scala:87:24] wire out_wimask = _out_wimask_T; // @[RegisterRouter.scala:87:24] wire _out_romask_T = out_backMask[0]; // @[RegisterRouter.scala:87:24] wire _out_womask_T = out_backMask[0]; // @[RegisterRouter.scala:87:24] wire out_romask = _out_romask_T; // @[RegisterRouter.scala:87:24] wire out_womask = _out_womask_T; // @[RegisterRouter.scala:87:24] wire out_f_rivalid = out_rivalid_0 & out_rimask; // @[RegisterRouter.scala:87:24] wire out_f_roready = out_roready_0 & out_romask; // @[RegisterRouter.scala:87:24] wire out_f_wivalid = out_wivalid_0 & out_wimask; // @[RegisterRouter.scala:87:24] wire out_f_woready = out_woready_0 & out_womask; // @[RegisterRouter.scala:87:24] wire _out_T_2 = out_front_bits_data[0]; // @[RegisterRouter.scala:87:24] wire _out_T_3 = ~out_rimask; // @[RegisterRouter.scala:87:24] wire _out_T_4 = ~out_wimask; // @[RegisterRouter.scala:87:24] wire _out_T_5 = ~out_romask; // @[RegisterRouter.scala:87:24] wire _out_T_6 = ~out_womask; // @[RegisterRouter.scala:87:24] wire _GEN = in_valid & out_front_ready; // @[RegisterRouter.scala:73:18, :87:24] wire _out_rifireMux_T; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T = _GEN; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T = _GEN; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1 = _out_rifireMux_T & out_front_bits_read; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_2 = _out_rifireMux_T_1; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_3 = _out_rifireMux_T_2 & _out_T; // @[RegisterRouter.scala:87:24] assign out_rivalid_0 = _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_4 = ~_out_T; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1 = ~out_front_bits_read; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_2 = _out_wifireMux_T & _out_wifireMux_T_1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_3 = _out_wifireMux_T_2; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_4 = _out_wifireMux_T_3 & _out_T; // @[RegisterRouter.scala:87:24] assign out_wivalid_0 = _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_5 = ~_out_T; // @[RegisterRouter.scala:87:24] wire _GEN_0 = out_front_valid & out_ready; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T = _GEN_0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T = _GEN_0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1 = _out_rofireMux_T & out_front_bits_read; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_2 = _out_rofireMux_T_1; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_3 = _out_rofireMux_T_2 & _out_T_1; // @[RegisterRouter.scala:87:24] assign out_roready_0 = _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_4 = ~_out_T_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1 = ~out_front_bits_read; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_2 = _out_wofireMux_T & _out_wofireMux_T_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_3 = _out_wofireMux_T_2; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_4 = _out_wofireMux_T_3 & _out_T_1; // @[RegisterRouter.scala:87:24] assign out_woready_0 = _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_5 = ~_out_T_1; // @[RegisterRouter.scala:87:24] assign in_ready = _out_in_ready_T; // @[RegisterRouter.scala:73:18, :87:24] assign out_front_valid = _out_front_valid_T; // @[RegisterRouter.scala:87:24] assign out_front_ready = _out_front_ready_T; // @[RegisterRouter.scala:87:24] assign out_valid = _out_out_valid_T; // @[RegisterRouter.scala:87:24] wire _out_out_bits_data_T_1 = _out_out_bits_data_WIRE_0; // @[MuxLiteral.scala:49:{10,48}] assign tlNodeIn_d_bits_size = tlNodeIn_d_bits_d_size; // @[Edges.scala:792:17] assign tlNodeIn_d_bits_source = tlNodeIn_d_bits_d_source; // @[Edges.scala:792:17] assign tlNodeIn_d_bits_opcode = {2'h0, _tlNodeIn_d_bits_opcode_T}; // @[RegisterRouter.scala:105:{19,25}] TLMonitor_60 monitor ( // @[Nodes.scala:27:25] .clock (clock), .reset (reset), .io_in_a_ready (tlNodeIn_a_ready), // @[MixedNode.scala:551:17] .io_in_a_valid (tlNodeIn_a_valid), // @[MixedNode.scala:551:17] .io_in_a_bits_opcode (tlNodeIn_a_bits_opcode), // @[MixedNode.scala:551:17] .io_in_a_bits_param (tlNodeIn_a_bits_param), // @[MixedNode.scala:551:17] .io_in_a_bits_size (tlNodeIn_a_bits_size), // @[MixedNode.scala:551:17] .io_in_a_bits_source (tlNodeIn_a_bits_source), // @[MixedNode.scala:551:17] .io_in_a_bits_address (tlNodeIn_a_bits_address), // @[MixedNode.scala:551:17] .io_in_a_bits_mask (tlNodeIn_a_bits_mask), // @[MixedNode.scala:551:17] .io_in_a_bits_data (tlNodeIn_a_bits_data), // @[MixedNode.scala:551:17] .io_in_a_bits_corrupt (tlNodeIn_a_bits_corrupt), // @[MixedNode.scala:551:17] .io_in_d_ready (tlNodeIn_d_ready), // @[MixedNode.scala:551:17] .io_in_d_valid (tlNodeIn_d_valid), // @[MixedNode.scala:551:17] .io_in_d_bits_opcode (tlNodeIn_d_bits_opcode), // @[MixedNode.scala:551:17] .io_in_d_bits_size (tlNodeIn_d_bits_size), // @[MixedNode.scala:551:17] .io_in_d_bits_source (tlNodeIn_d_bits_source) // @[MixedNode.scala:551:17] ); // @[Nodes.scala:27:25] AsyncResetRegVec_w1_i0_6 r_tile_resets_0 ( // @[TileResetSetter.scala:33:15] .clock (clock), .io_d (_out_T_2), // @[RegisterRouter.scala:87:24] .io_en (out_f_woready) // @[RegisterRouter.scala:87:24] ); // @[TileResetSetter.scala:33:15] assign auto_clock_out_member_allClocks_uncore_clock = auto_clock_out_member_allClocks_uncore_clock_0; // @[TileResetSetter.scala:26:25] assign auto_clock_out_member_allClocks_uncore_reset = auto_clock_out_member_allClocks_uncore_reset_0; // @[TileResetSetter.scala:26:25] assign auto_tl_in_a_ready = auto_tl_in_a_ready_0; // @[TileResetSetter.scala:26:25] assign auto_tl_in_d_valid = auto_tl_in_d_valid_0; // @[TileResetSetter.scala:26:25] assign auto_tl_in_d_bits_opcode = auto_tl_in_d_bits_opcode_0; // @[TileResetSetter.scala:26:25] assign auto_tl_in_d_bits_size = auto_tl_in_d_bits_size_0; // @[TileResetSetter.scala:26:25] assign auto_tl_in_d_bits_source = auto_tl_in_d_bits_source_0; // @[TileResetSetter.scala:26:25] endmodule

Generate the Verilog code corresponding to the following Chisel files. File Tile.scala: // See README.md for license details. package gemmini import chisel3._ import chisel3.util._ import Util._ /** * A Tile is a purely combinational 2D array of passThrough PEs. * a, b, s, and in_propag are broadcast across the entire array and are passed through to the Tile's outputs * @param width The data width of each PE in bits * @param rows Number of PEs on each row * @param columns Number of PEs on each column */ class Tile[T <: Data](inputType: T, outputType: T, accType: T, df: Dataflow.Value, tree_reduction: Boolean, max_simultaneous_matmuls: Int, val rows: Int, val columns: Int)(implicit ev: Arithmetic[T]) extends Module { val io = IO(new Bundle { val in_a = Input(Vec(rows, inputType)) val in_b = Input(Vec(columns, outputType)) // This is the output of the tile next to it val in_d = Input(Vec(columns, outputType)) val in_control = Input(Vec(columns, new PEControl(accType))) val in_id = Input(Vec(columns, UInt(log2Up(max_simultaneous_matmuls).W))) val in_last = Input(Vec(columns, Bool())) val out_a = Output(Vec(rows, inputType)) val out_c = Output(Vec(columns, outputType)) val out_b = Output(Vec(columns, outputType)) val out_control = Output(Vec(columns, new PEControl(accType))) val out_id = Output(Vec(columns, UInt(log2Up(max_simultaneous_matmuls).W))) val out_last = Output(Vec(columns, Bool())) val in_valid = Input(Vec(columns, Bool())) val out_valid = Output(Vec(columns, Bool())) val bad_dataflow = Output(Bool()) }) import ev._ val tile = Seq.fill(rows, columns)(Module(new PE(inputType, outputType, accType, df, max_simultaneous_matmuls))) val tileT = tile.transpose // TODO: abstract hori/vert broadcast, all these connections look the same // Broadcast 'a' horizontally across the Tile for (r <- 0 until rows) { tile(r).foldLeft(io.in_a(r)) { case (in_a, pe) => pe.io.in_a := in_a pe.io.out_a } } // Broadcast 'b' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_b(c)) { case (in_b, pe) => pe.io.in_b := (if (tree_reduction) in_b.zero else in_b) pe.io.out_b } } // Broadcast 'd' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_d(c)) { case (in_d, pe) => pe.io.in_d := in_d pe.io.out_c } } // Broadcast 'control' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_control(c)) { case (in_ctrl, pe) => pe.io.in_control := in_ctrl pe.io.out_control } } // Broadcast 'garbage' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_valid(c)) { case (v, pe) => pe.io.in_valid := v pe.io.out_valid } } // Broadcast 'id' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_id(c)) { case (id, pe) => pe.io.in_id := id pe.io.out_id } } // Broadcast 'last' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_last(c)) { case (last, pe) => pe.io.in_last := last pe.io.out_last } } // Drive the Tile's bottom IO for (c <- 0 until columns) { io.out_c(c) := tile(rows-1)(c).io.out_c io.out_control(c) := tile(rows-1)(c).io.out_control io.out_id(c) := tile(rows-1)(c).io.out_id io.out_last(c) := tile(rows-1)(c).io.out_last io.out_valid(c) := tile(rows-1)(c).io.out_valid io.out_b(c) := { if (tree_reduction) { val prods = tileT(c).map(_.io.out_b) accumulateTree(prods :+ io.in_b(c)) } else { tile(rows - 1)(c).io.out_b } } } io.bad_dataflow := tile.map(_.map(_.io.bad_dataflow).reduce(_||_)).reduce(_||_) // Drive the Tile's right IO for (r <- 0 until rows) { io.out_a(r) := tile(r)(columns-1).io.out_a } }

module Tile_80( // @[Tile.scala:16:7] input clock, // @[Tile.scala:16:7] input reset, // @[Tile.scala:16:7] input [7:0] io_in_a_0, // @[Tile.scala:17:14] input [19:0] io_in_b_0, // @[Tile.scala:17:14] input [19:0] io_in_d_0, // @[Tile.scala:17:14] input io_in_control_0_dataflow, // @[Tile.scala:17:14] input io_in_control_0_propagate, // @[Tile.scala:17:14] input [4:0] io_in_control_0_shift, // @[Tile.scala:17:14] input [2:0] io_in_id_0, // @[Tile.scala:17:14] input io_in_last_0, // @[Tile.scala:17:14] output [7:0] io_out_a_0, // @[Tile.scala:17:14] output [19:0] io_out_c_0, // @[Tile.scala:17:14] output [19:0] io_out_b_0, // @[Tile.scala:17:14] output io_out_control_0_dataflow, // @[Tile.scala:17:14] output io_out_control_0_propagate, // @[Tile.scala:17:14] output [4:0] io_out_control_0_shift, // @[Tile.scala:17:14] output [2:0] io_out_id_0, // @[Tile.scala:17:14] output io_out_last_0, // @[Tile.scala:17:14] input io_in_valid_0, // @[Tile.scala:17:14] output io_out_valid_0 // @[Tile.scala:17:14] ); wire [7:0] io_in_a_0_0 = io_in_a_0; // @[Tile.scala:16:7] wire [19:0] io_in_b_0_0 = io_in_b_0; // @[Tile.scala:16:7] wire [19:0] io_in_d_0_0 = io_in_d_0; // @[Tile.scala:16:7] wire io_in_control_0_dataflow_0 = io_in_control_0_dataflow; // @[Tile.scala:16:7] wire io_in_control_0_propagate_0 = io_in_control_0_propagate; // @[Tile.scala:16:7] wire [4:0] io_in_control_0_shift_0 = io_in_control_0_shift; // @[Tile.scala:16:7] wire [2:0] io_in_id_0_0 = io_in_id_0; // @[Tile.scala:16:7] wire io_in_last_0_0 = io_in_last_0; // @[Tile.scala:16:7] wire io_in_valid_0_0 = io_in_valid_0; // @[Tile.scala:16:7] wire io_bad_dataflow = 1'h0; // @[Tile.scala:16:7, :17:14, :42:44] wire [7:0] io_out_a_0_0; // @[Tile.scala:16:7] wire [19:0] io_out_c_0_0; // @[Tile.scala:16:7] wire [19:0] io_out_b_0_0; // @[Tile.scala:16:7] wire io_out_control_0_dataflow_0; // @[Tile.scala:16:7] wire io_out_control_0_propagate_0; // @[Tile.scala:16:7] wire [4:0] io_out_control_0_shift_0; // @[Tile.scala:16:7] wire [2:0] io_out_id_0_0; // @[Tile.scala:16:7] wire io_out_last_0_0; // @[Tile.scala:16:7] wire io_out_valid_0_0; // @[Tile.scala:16:7] PE_336 tile_0_0 ( // @[Tile.scala:42:44] .clock (clock), .reset (reset), .io_in_a (io_in_a_0_0), // @[Tile.scala:16:7] .io_in_b (io_in_b_0_0), // @[Tile.scala:16:7] .io_in_d (io_in_d_0_0), // @[Tile.scala:16:7] .io_out_a (io_out_a_0_0), .io_out_b (io_out_b_0_0), .io_out_c (io_out_c_0_0), .io_in_control_dataflow (io_in_control_0_dataflow_0), // @[Tile.scala:16:7] .io_in_control_propagate (io_in_control_0_propagate_0), // @[Tile.scala:16:7] .io_in_control_shift (io_in_control_0_shift_0), // @[Tile.scala:16:7] .io_out_control_dataflow (io_out_control_0_dataflow_0), .io_out_control_propagate (io_out_control_0_propagate_0), .io_out_control_shift (io_out_control_0_shift_0), .io_in_id (io_in_id_0_0), // @[Tile.scala:16:7] .io_out_id (io_out_id_0_0), .io_in_last (io_in_last_0_0), // @[Tile.scala:16:7] .io_out_last (io_out_last_0_0), .io_in_valid (io_in_valid_0_0), // @[Tile.scala:16:7] .io_out_valid (io_out_valid_0_0) ); // @[Tile.scala:42:44] assign io_out_a_0 = io_out_a_0_0; // @[Tile.scala:16:7] assign io_out_c_0 = io_out_c_0_0; // @[Tile.scala:16:7] assign io_out_b_0 = io_out_b_0_0; // @[Tile.scala:16:7] assign io_out_control_0_dataflow = io_out_control_0_dataflow_0; // @[Tile.scala:16:7] assign io_out_control_0_propagate = io_out_control_0_propagate_0; // @[Tile.scala:16:7] assign io_out_control_0_shift = io_out_control_0_shift_0; // @[Tile.scala:16:7] assign io_out_id_0 = io_out_id_0_0; // @[Tile.scala:16:7] assign io_out_last_0 = io_out_last_0_0; // @[Tile.scala:16:7] assign io_out_valid_0 = io_out_valid_0_0; // @[Tile.scala:16:7] endmodule

Generate the Verilog code corresponding to the following Chisel files. File RoundAnyRawFNToRecFN.scala: /*============================================================================ This Chisel source file is part of a pre-release version of the HardFloat IEEE Floating-Point Arithmetic Package, by John R. Hauser (with some contributions from Yunsup Lee and Andrew Waterman, mainly concerning testing). Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the University of California. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions, and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions, and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the University nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. =============================================================================*/ package hardfloat import chisel3._ import chisel3.util.Fill import consts._ //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- class RoundAnyRawFNToRecFN( inExpWidth: Int, inSigWidth: Int, outExpWidth: Int, outSigWidth: Int, options: Int ) extends RawModule { override def desiredName = s"RoundAnyRawFNToRecFN_ie${inExpWidth}_is${inSigWidth}_oe${outExpWidth}_os${outSigWidth}" val io = IO(new Bundle { val invalidExc = Input(Bool()) // overrides 'infiniteExc' and 'in' val infiniteExc = Input(Bool()) // overrides 'in' except for 'in.sign' val in = Input(new RawFloat(inExpWidth, inSigWidth)) // (allowed exponent range has limits) val roundingMode = Input(UInt(3.W)) val detectTininess = Input(UInt(1.W)) val out = Output(Bits((outExpWidth + outSigWidth + 1).W)) val exceptionFlags = Output(Bits(5.W)) }) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val sigMSBitAlwaysZero = ((options & flRoundOpt_sigMSBitAlwaysZero) != 0) val effectiveInSigWidth = if (sigMSBitAlwaysZero) inSigWidth else inSigWidth + 1 val neverUnderflows = ((options & (flRoundOpt_neverUnderflows | flRoundOpt_subnormsAlwaysExact) ) != 0) || (inExpWidth < outExpWidth) val neverOverflows = ((options & flRoundOpt_neverOverflows) != 0) || (inExpWidth < outExpWidth) val outNaNExp = BigInt(7)<<(outExpWidth - 2) val outInfExp = BigInt(6)<<(outExpWidth - 2) val outMaxFiniteExp = outInfExp - 1 val outMinNormExp = (BigInt(1)<<(outExpWidth - 1)) + 2 val outMinNonzeroExp = outMinNormExp - outSigWidth + 1 //------------------------------------------------------------------------ //------------------------------------------------------------------------ val roundingMode_near_even = (io.roundingMode === round_near_even) val roundingMode_minMag = (io.roundingMode === round_minMag) val roundingMode_min = (io.roundingMode === round_min) val roundingMode_max = (io.roundingMode === round_max) val roundingMode_near_maxMag = (io.roundingMode === round_near_maxMag) val roundingMode_odd = (io.roundingMode === round_odd) val roundMagUp = (roundingMode_min && io.in.sign) || (roundingMode_max && ! io.in.sign) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val sAdjustedExp = if (inExpWidth < outExpWidth) (io.in.sExp +& ((BigInt(1)<<outExpWidth) - (BigInt(1)<<inExpWidth)).S )(outExpWidth, 0).zext else if (inExpWidth == outExpWidth) io.in.sExp else io.in.sExp +& ((BigInt(1)<<outExpWidth) - (BigInt(1)<<inExpWidth)).S val adjustedSig = if (inSigWidth <= outSigWidth + 2) io.in.sig<<(outSigWidth - inSigWidth + 2) else (io.in.sig(inSigWidth, inSigWidth - outSigWidth - 1) ## io.in.sig(inSigWidth - outSigWidth - 2, 0).orR ) val doShiftSigDown1 = if (sigMSBitAlwaysZero) false.B else adjustedSig(outSigWidth + 2) val common_expOut = Wire(UInt((outExpWidth + 1).W)) val common_fractOut = Wire(UInt((outSigWidth - 1).W)) val common_overflow = Wire(Bool()) val common_totalUnderflow = Wire(Bool()) val common_underflow = Wire(Bool()) val common_inexact = Wire(Bool()) if ( neverOverflows && neverUnderflows && (effectiveInSigWidth <= outSigWidth) ) { //-------------------------------------------------------------------- //-------------------------------------------------------------------- common_expOut := sAdjustedExp(outExpWidth, 0) + doShiftSigDown1 common_fractOut := Mux(doShiftSigDown1, adjustedSig(outSigWidth + 1, 3), adjustedSig(outSigWidth, 2) ) common_overflow := false.B common_totalUnderflow := false.B common_underflow := false.B common_inexact := false.B } else { //-------------------------------------------------------------------- //-------------------------------------------------------------------- val roundMask = if (neverUnderflows) 0.U(outSigWidth.W) ## doShiftSigDown1 ## 3.U(2.W) else (lowMask( sAdjustedExp(outExpWidth, 0), outMinNormExp - outSigWidth - 1, outMinNormExp ) | doShiftSigDown1) ## 3.U(2.W) val shiftedRoundMask = 0.U(1.W) ## roundMask>>1 val roundPosMask = ~shiftedRoundMask & roundMask val roundPosBit = (adjustedSig & roundPosMask).orR val anyRoundExtra = (adjustedSig & shiftedRoundMask).orR val anyRound = roundPosBit || anyRoundExtra val roundIncr = ((roundingMode_near_even || roundingMode_near_maxMag) && roundPosBit) || (roundMagUp && anyRound) val roundedSig: Bits = Mux(roundIncr, (((adjustedSig | roundMask)>>2) +& 1.U) & ~Mux(roundingMode_near_even && roundPosBit && ! anyRoundExtra, roundMask>>1, 0.U((outSigWidth + 2).W) ), (adjustedSig & ~roundMask)>>2 | Mux(roundingMode_odd && anyRound, roundPosMask>>1, 0.U) ) //*** IF SIG WIDTH IS VERY NARROW, NEED TO ACCOUNT FOR ROUND-EVEN ZEROING //*** M.S. BIT OF SUBNORMAL SIG? val sRoundedExp = sAdjustedExp +& (roundedSig>>outSigWidth).asUInt.zext common_expOut := sRoundedExp(outExpWidth, 0) common_fractOut := Mux(doShiftSigDown1, roundedSig(outSigWidth - 1, 1), roundedSig(outSigWidth - 2, 0) ) common_overflow := (if (neverOverflows) false.B else //*** REWRITE BASED ON BEFORE-ROUNDING EXPONENT?: (sRoundedExp>>(outExpWidth - 1) >= 3.S)) common_totalUnderflow := (if (neverUnderflows) false.B else //*** WOULD BE GOOD ENOUGH TO USE EXPONENT BEFORE ROUNDING?: (sRoundedExp < outMinNonzeroExp.S)) val unboundedRange_roundPosBit = Mux(doShiftSigDown1, adjustedSig(2), adjustedSig(1)) val unboundedRange_anyRound = (doShiftSigDown1 && adjustedSig(2)) || adjustedSig(1, 0).orR val unboundedRange_roundIncr = ((roundingMode_near_even || roundingMode_near_maxMag) && unboundedRange_roundPosBit) || (roundMagUp && unboundedRange_anyRound) val roundCarry = Mux(doShiftSigDown1, roundedSig(outSigWidth + 1), roundedSig(outSigWidth) ) common_underflow := (if (neverUnderflows) false.B else common_totalUnderflow || //*** IF SIG WIDTH IS VERY NARROW, NEED TO ACCOUNT FOR ROUND-EVEN ZEROING //*** M.S. BIT OF SUBNORMAL SIG? (anyRound && ((sAdjustedExp>>outExpWidth) <= 0.S) && Mux(doShiftSigDown1, roundMask(3), roundMask(2)) && ! ((io.detectTininess === tininess_afterRounding) && ! Mux(doShiftSigDown1, roundMask(4), roundMask(3) ) && roundCarry && roundPosBit && unboundedRange_roundIncr))) common_inexact := common_totalUnderflow || anyRound } //------------------------------------------------------------------------ //------------------------------------------------------------------------ val isNaNOut = io.invalidExc || io.in.isNaN val notNaN_isSpecialInfOut = io.infiniteExc || io.in.isInf val commonCase = ! isNaNOut && ! notNaN_isSpecialInfOut && ! io.in.isZero val overflow = commonCase && common_overflow val underflow = commonCase && common_underflow val inexact = overflow || (commonCase && common_inexact) val overflow_roundMagUp = roundingMode_near_even || roundingMode_near_maxMag || roundMagUp val pegMinNonzeroMagOut = commonCase && common_totalUnderflow && (roundMagUp || roundingMode_odd) val pegMaxFiniteMagOut = overflow && ! overflow_roundMagUp val notNaN_isInfOut = notNaN_isSpecialInfOut || (overflow && overflow_roundMagUp) val signOut = Mux(isNaNOut, false.B, io.in.sign) val expOut = (common_expOut & ~Mux(io.in.isZero || common_totalUnderflow, (BigInt(7)<<(outExpWidth - 2)).U((outExpWidth + 1).W), 0.U ) & ~Mux(pegMinNonzeroMagOut, ~outMinNonzeroExp.U((outExpWidth + 1).W), 0.U ) & ~Mux(pegMaxFiniteMagOut, (BigInt(1)<<(outExpWidth - 1)).U((outExpWidth + 1).W), 0.U ) & ~Mux(notNaN_isInfOut, (BigInt(1)<<(outExpWidth - 2)).U((outExpWidth + 1).W), 0.U )) | Mux(pegMinNonzeroMagOut, outMinNonzeroExp.U((outExpWidth + 1).W), 0.U ) | Mux(pegMaxFiniteMagOut, outMaxFiniteExp.U((outExpWidth + 1).W), 0.U ) | Mux(notNaN_isInfOut, outInfExp.U((outExpWidth + 1).W), 0.U) | Mux(isNaNOut, outNaNExp.U((outExpWidth + 1).W), 0.U) val fractOut = Mux(isNaNOut || io.in.isZero || common_totalUnderflow, Mux(isNaNOut, (BigInt(1)<<(outSigWidth - 2)).U, 0.U), common_fractOut ) | Fill(outSigWidth - 1, pegMaxFiniteMagOut) io.out := signOut ## expOut ## fractOut io.exceptionFlags := io.invalidExc ## io.infiniteExc ## overflow ## underflow ## inexact } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- class RoundRawFNToRecFN(expWidth: Int, sigWidth: Int, options: Int) extends RawModule { override def desiredName = s"RoundRawFNToRecFN_e${expWidth}_s${sigWidth}" val io = IO(new Bundle { val invalidExc = Input(Bool()) // overrides 'infiniteExc' and 'in' val infiniteExc = Input(Bool()) // overrides 'in' except for 'in.sign' val in = Input(new RawFloat(expWidth, sigWidth + 2)) val roundingMode = Input(UInt(3.W)) val detectTininess = Input(UInt(1.W)) val out = Output(Bits((expWidth + sigWidth + 1).W)) val exceptionFlags = Output(Bits(5.W)) }) val roundAnyRawFNToRecFN = Module( new RoundAnyRawFNToRecFN( expWidth, sigWidth + 2, expWidth, sigWidth, options)) roundAnyRawFNToRecFN.io.invalidExc := io.invalidExc roundAnyRawFNToRecFN.io.infiniteExc := io.infiniteExc roundAnyRawFNToRecFN.io.in := io.in roundAnyRawFNToRecFN.io.roundingMode := io.roundingMode roundAnyRawFNToRecFN.io.detectTininess := io.detectTininess io.out := roundAnyRawFNToRecFN.io.out io.exceptionFlags := roundAnyRawFNToRecFN.io.exceptionFlags }

module RoundRawFNToRecFN_e8_s24_125( // @[RoundAnyRawFNToRecFN.scala:295:5] input io_invalidExc, // @[RoundAnyRawFNToRecFN.scala:299:16] input io_in_isNaN, // @[RoundAnyRawFNToRecFN.scala:299:16] input io_in_isInf, // @[RoundAnyRawFNToRecFN.scala:299:16] input io_in_isZero, // @[RoundAnyRawFNToRecFN.scala:299:16] input io_in_sign, // @[RoundAnyRawFNToRecFN.scala:299:16] input [9:0] io_in_sExp, // @[RoundAnyRawFNToRecFN.scala:299:16] input [26:0] io_in_sig, // @[RoundAnyRawFNToRecFN.scala:299:16] output [32:0] io_out, // @[RoundAnyRawFNToRecFN.scala:299:16] output [4:0] io_exceptionFlags // @[RoundAnyRawFNToRecFN.scala:299:16] ); wire io_invalidExc_0 = io_invalidExc; // @[RoundAnyRawFNToRecFN.scala:295:5] wire io_in_isNaN_0 = io_in_isNaN; // @[RoundAnyRawFNToRecFN.scala:295:5] wire io_in_isInf_0 = io_in_isInf; // @[RoundAnyRawFNToRecFN.scala:295:5] wire io_in_isZero_0 = io_in_isZero; // @[RoundAnyRawFNToRecFN.scala:295:5] wire io_in_sign_0 = io_in_sign; // @[RoundAnyRawFNToRecFN.scala:295:5] wire [9:0] io_in_sExp_0 = io_in_sExp; // @[RoundAnyRawFNToRecFN.scala:295:5] wire [26:0] io_in_sig_0 = io_in_sig; // @[RoundAnyRawFNToRecFN.scala:295:5] wire io_detectTininess = 1'h1; // @[RoundAnyRawFNToRecFN.scala:295:5, :299:16, :310:15] wire [2:0] io_roundingMode = 3'h0; // @[RoundAnyRawFNToRecFN.scala:295:5, :299:16, :310:15] wire io_infiniteExc = 1'h0; // @[RoundAnyRawFNToRecFN.scala:295:5, :299:16, :310:15] wire [32:0] io_out_0; // @[RoundAnyRawFNToRecFN.scala:295:5] wire [4:0] io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:295:5] RoundAnyRawFNToRecFN_ie8_is26_oe8_os24_125 roundAnyRawFNToRecFN ( // @[RoundAnyRawFNToRecFN.scala:310:15] .io_invalidExc (io_invalidExc_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_isNaN (io_in_isNaN_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_isInf (io_in_isInf_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_isZero (io_in_isZero_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_sign (io_in_sign_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_sExp (io_in_sExp_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_sig (io_in_sig_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_out (io_out_0), .io_exceptionFlags (io_exceptionFlags_0) ); // @[RoundAnyRawFNToRecFN.scala:310:15] assign io_out = io_out_0; // @[RoundAnyRawFNToRecFN.scala:295:5] assign io_exceptionFlags = io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:295:5] endmodule

Generate the Verilog code corresponding to the following Chisel files. File Tile.scala: // See README.md for license details. package gemmini import chisel3._ import chisel3.util._ import Util._ /** * A Tile is a purely combinational 2D array of passThrough PEs. * a, b, s, and in_propag are broadcast across the entire array and are passed through to the Tile's outputs * @param width The data width of each PE in bits * @param rows Number of PEs on each row * @param columns Number of PEs on each column */ class Tile[T <: Data](inputType: T, outputType: T, accType: T, df: Dataflow.Value, tree_reduction: Boolean, max_simultaneous_matmuls: Int, val rows: Int, val columns: Int)(implicit ev: Arithmetic[T]) extends Module { val io = IO(new Bundle { val in_a = Input(Vec(rows, inputType)) val in_b = Input(Vec(columns, outputType)) // This is the output of the tile next to it val in_d = Input(Vec(columns, outputType)) val in_control = Input(Vec(columns, new PEControl(accType))) val in_id = Input(Vec(columns, UInt(log2Up(max_simultaneous_matmuls).W))) val in_last = Input(Vec(columns, Bool())) val out_a = Output(Vec(rows, inputType)) val out_c = Output(Vec(columns, outputType)) val out_b = Output(Vec(columns, outputType)) val out_control = Output(Vec(columns, new PEControl(accType))) val out_id = Output(Vec(columns, UInt(log2Up(max_simultaneous_matmuls).W))) val out_last = Output(Vec(columns, Bool())) val in_valid = Input(Vec(columns, Bool())) val out_valid = Output(Vec(columns, Bool())) val bad_dataflow = Output(Bool()) }) import ev._ val tile = Seq.fill(rows, columns)(Module(new PE(inputType, outputType, accType, df, max_simultaneous_matmuls))) val tileT = tile.transpose // TODO: abstract hori/vert broadcast, all these connections look the same // Broadcast 'a' horizontally across the Tile for (r <- 0 until rows) { tile(r).foldLeft(io.in_a(r)) { case (in_a, pe) => pe.io.in_a := in_a pe.io.out_a } } // Broadcast 'b' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_b(c)) { case (in_b, pe) => pe.io.in_b := (if (tree_reduction) in_b.zero else in_b) pe.io.out_b } } // Broadcast 'd' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_d(c)) { case (in_d, pe) => pe.io.in_d := in_d pe.io.out_c } } // Broadcast 'control' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_control(c)) { case (in_ctrl, pe) => pe.io.in_control := in_ctrl pe.io.out_control } } // Broadcast 'garbage' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_valid(c)) { case (v, pe) => pe.io.in_valid := v pe.io.out_valid } } // Broadcast 'id' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_id(c)) { case (id, pe) => pe.io.in_id := id pe.io.out_id } } // Broadcast 'last' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_last(c)) { case (last, pe) => pe.io.in_last := last pe.io.out_last } } // Drive the Tile's bottom IO for (c <- 0 until columns) { io.out_c(c) := tile(rows-1)(c).io.out_c io.out_control(c) := tile(rows-1)(c).io.out_control io.out_id(c) := tile(rows-1)(c).io.out_id io.out_last(c) := tile(rows-1)(c).io.out_last io.out_valid(c) := tile(rows-1)(c).io.out_valid io.out_b(c) := { if (tree_reduction) { val prods = tileT(c).map(_.io.out_b) accumulateTree(prods :+ io.in_b(c)) } else { tile(rows - 1)(c).io.out_b } } } io.bad_dataflow := tile.map(_.map(_.io.bad_dataflow).reduce(_||_)).reduce(_||_) // Drive the Tile's right IO for (r <- 0 until rows) { io.out_a(r) := tile(r)(columns-1).io.out_a } }

module Tile_201( // @[Tile.scala:16:7] input clock, // @[Tile.scala:16:7] input reset, // @[Tile.scala:16:7] input [7:0] io_in_a_0, // @[Tile.scala:17:14] input [19:0] io_in_b_0, // @[Tile.scala:17:14] input [19:0] io_in_d_0, // @[Tile.scala:17:14] input io_in_control_0_dataflow, // @[Tile.scala:17:14] input io_in_control_0_propagate, // @[Tile.scala:17:14] input [4:0] io_in_control_0_shift, // @[Tile.scala:17:14] input [2:0] io_in_id_0, // @[Tile.scala:17:14] input io_in_last_0, // @[Tile.scala:17:14] output [7:0] io_out_a_0, // @[Tile.scala:17:14] output [19:0] io_out_c_0, // @[Tile.scala:17:14] output [19:0] io_out_b_0, // @[Tile.scala:17:14] output io_out_control_0_dataflow, // @[Tile.scala:17:14] output io_out_control_0_propagate, // @[Tile.scala:17:14] output [4:0] io_out_control_0_shift, // @[Tile.scala:17:14] output [2:0] io_out_id_0, // @[Tile.scala:17:14] output io_out_last_0, // @[Tile.scala:17:14] input io_in_valid_0, // @[Tile.scala:17:14] output io_out_valid_0 // @[Tile.scala:17:14] ); wire [7:0] io_in_a_0_0 = io_in_a_0; // @[Tile.scala:16:7] wire [19:0] io_in_b_0_0 = io_in_b_0; // @[Tile.scala:16:7] wire [19:0] io_in_d_0_0 = io_in_d_0; // @[Tile.scala:16:7] wire io_in_control_0_dataflow_0 = io_in_control_0_dataflow; // @[Tile.scala:16:7] wire io_in_control_0_propagate_0 = io_in_control_0_propagate; // @[Tile.scala:16:7] wire [4:0] io_in_control_0_shift_0 = io_in_control_0_shift; // @[Tile.scala:16:7] wire [2:0] io_in_id_0_0 = io_in_id_0; // @[Tile.scala:16:7] wire io_in_last_0_0 = io_in_last_0; // @[Tile.scala:16:7] wire io_in_valid_0_0 = io_in_valid_0; // @[Tile.scala:16:7] wire io_bad_dataflow = 1'h0; // @[Tile.scala:16:7, :17:14, :42:44] wire [7:0] io_out_a_0_0; // @[Tile.scala:16:7] wire [19:0] io_out_c_0_0; // @[Tile.scala:16:7] wire [19:0] io_out_b_0_0; // @[Tile.scala:16:7] wire io_out_control_0_dataflow_0; // @[Tile.scala:16:7] wire io_out_control_0_propagate_0; // @[Tile.scala:16:7] wire [4:0] io_out_control_0_shift_0; // @[Tile.scala:16:7] wire [2:0] io_out_id_0_0; // @[Tile.scala:16:7] wire io_out_last_0_0; // @[Tile.scala:16:7] wire io_out_valid_0_0; // @[Tile.scala:16:7] PE_457 tile_0_0 ( // @[Tile.scala:42:44] .clock (clock), .reset (reset), .io_in_a (io_in_a_0_0), // @[Tile.scala:16:7] .io_in_b (io_in_b_0_0), // @[Tile.scala:16:7] .io_in_d (io_in_d_0_0), // @[Tile.scala:16:7] .io_out_a (io_out_a_0_0), .io_out_b (io_out_b_0_0), .io_out_c (io_out_c_0_0), .io_in_control_dataflow (io_in_control_0_dataflow_0), // @[Tile.scala:16:7] .io_in_control_propagate (io_in_control_0_propagate_0), // @[Tile.scala:16:7] .io_in_control_shift (io_in_control_0_shift_0), // @[Tile.scala:16:7] .io_out_control_dataflow (io_out_control_0_dataflow_0), .io_out_control_propagate (io_out_control_0_propagate_0), .io_out_control_shift (io_out_control_0_shift_0), .io_in_id (io_in_id_0_0), // @[Tile.scala:16:7] .io_out_id (io_out_id_0_0), .io_in_last (io_in_last_0_0), // @[Tile.scala:16:7] .io_out_last (io_out_last_0_0), .io_in_valid (io_in_valid_0_0), // @[Tile.scala:16:7] .io_out_valid (io_out_valid_0_0) ); // @[Tile.scala:42:44] assign io_out_a_0 = io_out_a_0_0; // @[Tile.scala:16:7] assign io_out_c_0 = io_out_c_0_0; // @[Tile.scala:16:7] assign io_out_b_0 = io_out_b_0_0; // @[Tile.scala:16:7] assign io_out_control_0_dataflow = io_out_control_0_dataflow_0; // @[Tile.scala:16:7] assign io_out_control_0_propagate = io_out_control_0_propagate_0; // @[Tile.scala:16:7] assign io_out_control_0_shift = io_out_control_0_shift_0; // @[Tile.scala:16:7] assign io_out_id_0 = io_out_id_0_0; // @[Tile.scala:16:7] assign io_out_last_0 = io_out_last_0_0; // @[Tile.scala:16:7] assign io_out_valid_0 = io_out_valid_0_0; // @[Tile.scala:16:7] endmodule

Generate the Verilog code corresponding to the following Chisel files. File PMA.scala: // See LICENSE.SiFive for license details. // See LICENSE.Berkeley for license details. package freechips.rocketchip.rocket import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config._ import freechips.rocketchip.devices.debug.DebugModuleKey import freechips.rocketchip.diplomacy.RegionType import freechips.rocketchip.subsystem.CacheBlockBytes import freechips.rocketchip.tile.{CoreModule, CoreBundle} import freechips.rocketchip.tilelink.{TLSlavePortParameters, TLManagerParameters} class PMAChecker(manager: TLSlavePortParameters)(implicit p: Parameters) extends CoreModule()(p) { val io = IO(new Bundle { val paddr = Input(UInt()) val resp = Output(new Bundle { val cacheable = Bool() val r = Bool() val w = Bool() val pp = Bool() val al = Bool() val aa = Bool() val x = Bool() val eff = Bool() }) }) // PMA // check exist a slave can consume this address. val legal_address = manager.findSafe(io.paddr).reduce(_||_) // check utility to help check SoC property. def fastCheck(member: TLManagerParameters => Boolean) = legal_address && manager.fastProperty(io.paddr, member, (b:Boolean) => b.B) io.resp.cacheable := fastCheck(_.supportsAcquireB) io.resp.r := fastCheck(_.supportsGet) io.resp.w := fastCheck(_.supportsPutFull) io.resp.pp := fastCheck(_.supportsPutPartial) io.resp.al := fastCheck(_.supportsLogical) io.resp.aa := fastCheck(_.supportsArithmetic) io.resp.x := fastCheck(_.executable) io.resp.eff := fastCheck(Seq(RegionType.PUT_EFFECTS, RegionType.GET_EFFECTS) contains _.regionType) } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.diplomacy import chisel3._ import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor} import freechips.rocketchip.util.ShiftQueue /** Options for describing the attributes of memory regions */ object RegionType { // Define the 'more relaxed than' ordering val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS) sealed trait T extends Ordered[T] { def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this) } case object CACHED extends T // an intermediate agent may have cached a copy of the region for you case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively } // A non-empty half-open range; [start, end) case class IdRange(start: Int, end: Int) extends Ordered[IdRange] { require (start >= 0, s"Ids cannot be negative, but got: $start.") require (start <= end, "Id ranges cannot be negative.") def compare(x: IdRange) = { val primary = (this.start - x.start).signum val secondary = (x.end - this.end).signum if (primary != 0) primary else secondary } def overlaps(x: IdRange) = start < x.end && x.start < end def contains(x: IdRange) = start <= x.start && x.end <= end def contains(x: Int) = start <= x && x < end def contains(x: UInt) = if (size == 0) { false.B } else if (size == 1) { // simple comparison x === start.U } else { // find index of largest different bit val largestDeltaBit = log2Floor(start ^ (end-1)) val smallestCommonBit = largestDeltaBit + 1 // may not exist in x val uncommonMask = (1 << smallestCommonBit) - 1 val uncommonBits = (x | 0.U(smallestCommonBit.W))(largestDeltaBit, 0) // the prefix must match exactly (note: may shift ALL bits away) (x >> smallestCommonBit) === (start >> smallestCommonBit).U && // firrtl constant prop range analysis can eliminate these two: (start & uncommonMask).U <= uncommonBits && uncommonBits <= ((end-1) & uncommonMask).U } def shift(x: Int) = IdRange(start+x, end+x) def size = end - start def isEmpty = end == start def range = start until end } object IdRange { def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else { val ranges = s.sorted (ranges.tail zip ranges.init) find { case (a, b) => a overlaps b } } } // An potentially empty inclusive range of 2-powers [min, max] (in bytes) case class TransferSizes(min: Int, max: Int) { def this(x: Int) = this(x, x) require (min <= max, s"Min transfer $min > max transfer $max") require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)") require (max == 0 || isPow2(max), s"TransferSizes must be a power of 2, got: $max") require (min == 0 || isPow2(min), s"TransferSizes must be a power of 2, got: $min") require (max == 0 || min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)") def none = min == 0 def contains(x: Int) = isPow2(x) && min <= x && x <= max def containsLg(x: Int) = contains(1 << x) def containsLg(x: UInt) = if (none) false.B else if (min == max) { log2Ceil(min).U === x } else { log2Ceil(min).U <= x && x <= log2Ceil(max).U } def contains(x: TransferSizes) = x.none || (min <= x.min && x.max <= max) def intersect(x: TransferSizes) = if (x.max < min || max < x.min) TransferSizes.none else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max)) // Not a union, because the result may contain sizes contained by neither term // NOT TO BE CONFUSED WITH COVERPOINTS def mincover(x: TransferSizes) = { if (none) { x } else if (x.none) { this } else { TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max)) } } override def toString() = "TransferSizes[%d, %d]".format(min, max) } object TransferSizes { def apply(x: Int) = new TransferSizes(x) val none = new TransferSizes(0) def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _) def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _) implicit def asBool(x: TransferSizes) = !x.none } // AddressSets specify the address space managed by the manager // Base is the base address, and mask are the bits consumed by the manager // e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff // e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ... case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet] { // Forbid misaligned base address (and empty sets) require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}") require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous // We do allow negative mask (=> ignore all high bits) def contains(x: BigInt) = ((x ^ base) & ~mask) == 0 def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S // turn x into an address contained in this set def legalize(x: UInt): UInt = base.U | (mask.U & x) // overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1) def overlaps(x: AddressSet) = (~(mask | x.mask) & (base ^ x.base)) == 0 // contains iff bitwise: x.mask => mask && contains(x.base) def contains(x: AddressSet) = ((x.mask | (base ^ x.base)) & ~mask) == 0 // The number of bytes to which the manager must be aligned def alignment = ((mask + 1) & ~mask) // Is this a contiguous memory range def contiguous = alignment == mask+1 def finite = mask >= 0 def max = { require (finite, "Max cannot be calculated on infinite mask"); base | mask } // Widen the match function to ignore all bits in imask def widen(imask: BigInt) = AddressSet(base & ~imask, mask | imask) // Return an AddressSet that only contains the addresses both sets contain def intersect(x: AddressSet): Option[AddressSet] = { if (!overlaps(x)) { None } else { val r_mask = mask & x.mask val r_base = base | x.base Some(AddressSet(r_base, r_mask)) } } def subtract(x: AddressSet): Seq[AddressSet] = { intersect(x) match { case None => Seq(this) case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit => val nmask = (mask & (bit-1)) | remove.mask val nbase = (remove.base ^ bit) & ~nmask AddressSet(nbase, nmask) } } } // AddressSets have one natural Ordering (the containment order, if contiguous) def compare(x: AddressSet) = { val primary = (this.base - x.base).signum // smallest address first val secondary = (x.mask - this.mask).signum // largest mask first if (primary != 0) primary else secondary } // We always want to see things in hex override def toString() = { if (mask >= 0) { "AddressSet(0x%x, 0x%x)".format(base, mask) } else { "AddressSet(0x%x, ~0x%x)".format(base, ~mask) } } def toRanges = { require (finite, "Ranges cannot be calculated on infinite mask") val size = alignment val fragments = mask & ~(size-1) val bits = bitIndexes(fragments) (BigInt(0) until (BigInt(1) << bits.size)).map { i => val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) } AddressRange(off, size) } } } object AddressSet { val everything = AddressSet(0, -1) def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = { if (size == 0) tail.reverse else { val maxBaseAlignment = base & (-base) // 0 for infinite (LSB) val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size val step = if (maxBaseAlignment == 0 || maxBaseAlignment > maxSizeAlignment) maxSizeAlignment else maxBaseAlignment misaligned(base+step, size-step, AddressSet(base, step-1) +: tail) } } def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = { // Pair terms up by ignoring 'bit' seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) => if (seq.size == 1) { seq.head // singleton -> unaffected } else { key.copy(mask = key.mask | bit) // pair - widen mask by bit } }.toList } def unify(seq: Seq[AddressSet]): Seq[AddressSet] = { val bits = seq.map(_.base).foldLeft(BigInt(0))(_ | _) AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted } def enumerateMask(mask: BigInt): Seq[BigInt] = { def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] = if (id == mask) (id +: tail).reverse else helper(((~mask | id) + 1) & mask, id +: tail) helper(0, Nil) } def enumerateBits(mask: BigInt): Seq[BigInt] = { def helper(x: BigInt): Seq[BigInt] = { if (x == 0) { Nil } else { val bit = x & (-x) bit +: helper(x & ~bit) } } helper(mask) } } case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean) { require (depth >= 0, "Buffer depth must be >= 0") def isDefined = depth > 0 def latency = if (isDefined && !flow) 1 else 0 def apply[T <: Data](x: DecoupledIO[T]) = if (isDefined) Queue(x, depth, flow=flow, pipe=pipe) else x def irrevocable[T <: Data](x: ReadyValidIO[T]) = if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe) else x def sq[T <: Data](x: DecoupledIO[T]) = if (!isDefined) x else { val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe)) sq.io.enq <> x sq.io.deq } override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "") } object BufferParams { implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false) val default = BufferParams(2) val none = BufferParams(0) val flow = BufferParams(1, true, false) val pipe = BufferParams(1, false, true) } case class TriStateValue(value: Boolean, set: Boolean) { def update(orig: Boolean) = if (set) value else orig } object TriStateValue { implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true) def unset = TriStateValue(false, false) } trait DirectedBuffers[T] { def copyIn(x: BufferParams): T def copyOut(x: BufferParams): T def copyInOut(x: BufferParams): T } trait IdMapEntry { def name: String def from: IdRange def to: IdRange def isCache: Boolean def requestFifo: Boolean def maxTransactionsInFlight: Option[Int] def pretty(fmt: String) = if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5 fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } else { fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } } abstract class IdMap[T <: IdMapEntry] { protected val fmt: String val mapping: Seq[T] def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n") }

module PMAChecker_1( // @[PMA.scala:18:7] input clock, // @[PMA.scala:18:7] input reset, // @[PMA.scala:18:7] input [33:0] io_paddr, // @[PMA.scala:19:14] output io_resp_r, // @[PMA.scala:19:14] output io_resp_w, // @[PMA.scala:19:14] output io_resp_pp, // @[PMA.scala:19:14] output io_resp_al, // @[PMA.scala:19:14] output io_resp_aa, // @[PMA.scala:19:14] output io_resp_x, // @[PMA.scala:19:14] output io_resp_eff // @[PMA.scala:19:14] ); wire [33:0] io_paddr_0 = io_paddr; // @[PMA.scala:18:7] wire [34:0] _io_resp_cacheable_T_2 = 35'h0; // @[Parameters.scala:137:46] wire [34:0] _io_resp_cacheable_T_3 = 35'h0; // @[Parameters.scala:137:46] wire [34:0] _io_resp_r_T_2 = 35'h0; // @[Parameters.scala:137:46] wire [34:0] _io_resp_r_T_3 = 35'h0; // @[Parameters.scala:137:46] wire _io_resp_cacheable_T_4 = 1'h1; // @[Parameters.scala:137:59] wire _io_resp_r_T_4 = 1'h1; // @[Parameters.scala:137:59] wire io_resp_cacheable = 1'h0; // @[PMA.scala:18:7] wire _io_resp_cacheable_T_5 = 1'h0; // @[PMA.scala:39:19] wire _io_resp_w_T_29 = 1'h0; // @[Mux.scala:30:73] wire _io_resp_pp_T_29 = 1'h0; // @[Mux.scala:30:73] wire _io_resp_al_T_29 = 1'h0; // @[Mux.scala:30:73] wire _io_resp_aa_T_29 = 1'h0; // @[Mux.scala:30:73] wire _io_resp_x_T_59 = 1'h0; // @[Mux.scala:30:73] wire _io_resp_eff_T_47 = 1'h0; // @[Mux.scala:30:73] wire [33:0] _legal_address_T = io_paddr_0; // @[PMA.scala:18:7] wire [33:0] _io_resp_cacheable_T = io_paddr_0; // @[PMA.scala:18:7] wire [33:0] _io_resp_r_T = io_paddr_0; // @[PMA.scala:18:7] wire [33:0] _io_resp_w_T = io_paddr_0; // @[PMA.scala:18:7] wire [33:0] _io_resp_pp_T = io_paddr_0; // @[PMA.scala:18:7] wire [33:0] _io_resp_al_T = io_paddr_0; // @[PMA.scala:18:7] wire [33:0] _io_resp_aa_T = io_paddr_0; // @[PMA.scala:18:7] wire [33:0] _io_resp_x_T = io_paddr_0; // @[PMA.scala:18:7] wire [33:0] _io_resp_eff_T = io_paddr_0; // @[PMA.scala:18:7] wire _io_resp_r_T_5; // @[PMA.scala:39:19] wire _io_resp_w_T_31; // @[PMA.scala:39:19] wire _io_resp_pp_T_31; // @[PMA.scala:39:19] wire _io_resp_al_T_31; // @[PMA.scala:39:19] wire _io_resp_aa_T_31; // @[PMA.scala:39:19] wire _io_resp_x_T_61; // @[PMA.scala:39:19] wire _io_resp_eff_T_49; // @[PMA.scala:39:19] wire io_resp_r_0; // @[PMA.scala:18:7] wire io_resp_w_0; // @[PMA.scala:18:7] wire io_resp_pp_0; // @[PMA.scala:18:7] wire io_resp_al_0; // @[PMA.scala:18:7] wire io_resp_aa_0; // @[PMA.scala:18:7] wire io_resp_x_0; // @[PMA.scala:18:7] wire io_resp_eff_0; // @[PMA.scala:18:7] wire [34:0] _legal_address_T_1 = {1'h0, _legal_address_T}; // @[Parameters.scala:137:{31,41}] wire [34:0] _legal_address_T_2 = _legal_address_T_1 & 35'h7FFFFF000; // @[Parameters.scala:137:{41,46}] wire [34:0] _legal_address_T_3 = _legal_address_T_2; // @[Parameters.scala:137:46] wire _legal_address_T_4 = _legal_address_T_3 == 35'h0; // @[Parameters.scala:137:{46,59}] wire _legal_address_WIRE_0 = _legal_address_T_4; // @[Parameters.scala:612:40] wire [33:0] _GEN = {io_paddr_0[33:13], io_paddr_0[12:0] ^ 13'h1000}; // @[PMA.scala:18:7] wire [33:0] _legal_address_T_5; // @[Parameters.scala:137:31] assign _legal_address_T_5 = _GEN; // @[Parameters.scala:137:31] wire [33:0] _io_resp_x_T_29; // @[Parameters.scala:137:31] assign _io_resp_x_T_29 = _GEN; // @[Parameters.scala:137:31] wire [34:0] _legal_address_T_6 = {1'h0, _legal_address_T_5}; // @[Parameters.scala:137:{31,41}] wire [34:0] _legal_address_T_7 = _legal_address_T_6 & 35'h7FFFFF000; // @[Parameters.scala:137:{41,46}] wire [34:0] _legal_address_T_8 = _legal_address_T_7; // @[Parameters.scala:137:46] wire _legal_address_T_9 = _legal_address_T_8 == 35'h0; // @[Parameters.scala:137:{46,59}] wire _legal_address_WIRE_1 = _legal_address_T_9; // @[Parameters.scala:612:40] wire [33:0] _GEN_0 = {io_paddr_0[33:14], io_paddr_0[13:0] ^ 14'h3000}; // @[PMA.scala:18:7] wire [33:0] _legal_address_T_10; // @[Parameters.scala:137:31] assign _legal_address_T_10 = _GEN_0; // @[Parameters.scala:137:31] wire [33:0] _io_resp_x_T_5; // @[Parameters.scala:137:31] assign _io_resp_x_T_5 = _GEN_0; // @[Parameters.scala:137:31] wire [33:0] _io_resp_eff_T_29; // @[Parameters.scala:137:31] assign _io_resp_eff_T_29 = _GEN_0; // @[Parameters.scala:137:31] wire [34:0] _legal_address_T_11 = {1'h0, _legal_address_T_10}; // @[Parameters.scala:137:{31,41}] wire [34:0] _legal_address_T_12 = _legal_address_T_11 & 35'h7FFFFF000; // @[Parameters.scala:137:{41,46}] wire [34:0] _legal_address_T_13 = _legal_address_T_12; // @[Parameters.scala:137:46] wire _legal_address_T_14 = _legal_address_T_13 == 35'h0; // @[Parameters.scala:137:{46,59}] wire _legal_address_WIRE_2 = _legal_address_T_14; // @[Parameters.scala:612:40] wire [33:0] _GEN_1 = {io_paddr_0[33:17], io_paddr_0[16:0] ^ 17'h10000}; // @[PMA.scala:18:7] wire [33:0] _legal_address_T_15; // @[Parameters.scala:137:31] assign _legal_address_T_15 = _GEN_1; // @[Parameters.scala:137:31] wire [33:0] _io_resp_w_T_23; // @[Parameters.scala:137:31] assign _io_resp_w_T_23 = _GEN_1; // @[Parameters.scala:137:31] wire [33:0] _io_resp_pp_T_23; // @[Parameters.scala:137:31] assign _io_resp_pp_T_23 = _GEN_1; // @[Parameters.scala:137:31] wire [33:0] _io_resp_al_T_17; // @[Parameters.scala:137:31] assign _io_resp_al_T_17 = _GEN_1; // @[Parameters.scala:137:31] wire [33:0] _io_resp_aa_T_17; // @[Parameters.scala:137:31] assign _io_resp_aa_T_17 = _GEN_1; // @[Parameters.scala:137:31] wire [33:0] _io_resp_x_T_10; // @[Parameters.scala:137:31] assign _io_resp_x_T_10 = _GEN_1; // @[Parameters.scala:137:31] wire [33:0] _io_resp_eff_T_34; // @[Parameters.scala:137:31] assign _io_resp_eff_T_34 = _GEN_1; // @[Parameters.scala:137:31] wire [34:0] _legal_address_T_16 = {1'h0, _legal_address_T_15}; // @[Parameters.scala:137:{31,41}] wire [34:0] _legal_address_T_17 = _legal_address_T_16 & 35'h7FFFF0000; // @[Parameters.scala:137:{41,46}] wire [34:0] _legal_address_T_18 = _legal_address_T_17; // @[Parameters.scala:137:46] wire _legal_address_T_19 = _legal_address_T_18 == 35'h0; // @[Parameters.scala:137:{46,59}] wire _legal_address_WIRE_3 = _legal_address_T_19; // @[Parameters.scala:612:40] wire [33:0] _GEN_2 = {io_paddr_0[33:21], io_paddr_0[20:0] ^ 21'h100000}; // @[PMA.scala:18:7] wire [33:0] _legal_address_T_20; // @[Parameters.scala:137:31] assign _legal_address_T_20 = _GEN_2; // @[Parameters.scala:137:31] wire [33:0] _io_resp_w_T_5; // @[Parameters.scala:137:31] assign _io_resp_w_T_5 = _GEN_2; // @[Parameters.scala:137:31] wire [33:0] _io_resp_pp_T_5; // @[Parameters.scala:137:31] assign _io_resp_pp_T_5 = _GEN_2; // @[Parameters.scala:137:31] wire [33:0] _io_resp_al_T_5; // @[Parameters.scala:137:31] assign _io_resp_al_T_5 = _GEN_2; // @[Parameters.scala:137:31] wire [33:0] _io_resp_aa_T_5; // @[Parameters.scala:137:31] assign _io_resp_aa_T_5 = _GEN_2; // @[Parameters.scala:137:31] wire [33:0] _io_resp_x_T_34; // @[Parameters.scala:137:31] assign _io_resp_x_T_34 = _GEN_2; // @[Parameters.scala:137:31] wire [33:0] _io_resp_eff_T_5; // @[Parameters.scala:137:31] assign _io_resp_eff_T_5 = _GEN_2; // @[Parameters.scala:137:31] wire [34:0] _legal_address_T_21 = {1'h0, _legal_address_T_20}; // @[Parameters.scala:137:{31,41}] wire [34:0] _legal_address_T_22 = _legal_address_T_21 & 35'h7FFFFF000; // @[Parameters.scala:137:{41,46}] wire [34:0] _legal_address_T_23 = _legal_address_T_22; // @[Parameters.scala:137:46] wire _legal_address_T_24 = _legal_address_T_23 == 35'h0; // @[Parameters.scala:137:{46,59}] wire _legal_address_WIRE_4 = _legal_address_T_24; // @[Parameters.scala:612:40] wire [33:0] _legal_address_T_25 = {io_paddr_0[33:21], io_paddr_0[20:0] ^ 21'h110000}; // @[PMA.scala:18:7] wire [34:0] _legal_address_T_26 = {1'h0, _legal_address_T_25}; // @[Parameters.scala:137:{31,41}] wire [34:0] _legal_address_T_27 = _legal_address_T_26 & 35'h7FFFFF000; // @[Parameters.scala:137:{41,46}] wire [34:0] _legal_address_T_28 = _legal_address_T_27; // @[Parameters.scala:137:46] wire _legal_address_T_29 = _legal_address_T_28 == 35'h0; // @[Parameters.scala:137:{46,59}] wire _legal_address_WIRE_5 = _legal_address_T_29; // @[Parameters.scala:612:40] wire [33:0] _GEN_3 = {io_paddr_0[33:26], io_paddr_0[25:0] ^ 26'h2000000}; // @[PMA.scala:18:7] wire [33:0] _legal_address_T_30; // @[Parameters.scala:137:31] assign _legal_address_T_30 = _GEN_3; // @[Parameters.scala:137:31] wire [33:0] _io_resp_x_T_39; // @[Parameters.scala:137:31] assign _io_resp_x_T_39 = _GEN_3; // @[Parameters.scala:137:31] wire [33:0] _io_resp_eff_T_10; // @[Parameters.scala:137:31] assign _io_resp_eff_T_10 = _GEN_3; // @[Parameters.scala:137:31] wire [34:0] _legal_address_T_31 = {1'h0, _legal_address_T_30}; // @[Parameters.scala:137:{31,41}] wire [34:0] _legal_address_T_32 = _legal_address_T_31 & 35'h7FFFF0000; // @[Parameters.scala:137:{41,46}] wire [34:0] _legal_address_T_33 = _legal_address_T_32; // @[Parameters.scala:137:46] wire _legal_address_T_34 = _legal_address_T_33 == 35'h0; // @[Parameters.scala:137:{46,59}] wire _legal_address_WIRE_6 = _legal_address_T_34; // @[Parameters.scala:612:40] wire [33:0] _legal_address_T_35 = {io_paddr_0[33:28], io_paddr_0[27:0] ^ 28'hC000000}; // @[PMA.scala:18:7] wire [34:0] _legal_address_T_36 = {1'h0, _legal_address_T_35}; // @[Parameters.scala:137:{31,41}] wire [34:0] _legal_address_T_37 = _legal_address_T_36 & 35'h7FC000000; // @[Parameters.scala:137:{41,46}] wire [34:0] _legal_address_T_38 = _legal_address_T_37; // @[Parameters.scala:137:46] wire _legal_address_T_39 = _legal_address_T_38 == 35'h0; // @[Parameters.scala:137:{46,59}] wire _legal_address_WIRE_7 = _legal_address_T_39; // @[Parameters.scala:612:40] wire [33:0] _legal_address_T_40 = {io_paddr_0[33:29], io_paddr_0[28:0] ^ 29'h10020000}; // @[PMA.scala:18:7] wire [34:0] _legal_address_T_41 = {1'h0, _legal_address_T_40}; // @[Parameters.scala:137:{31,41}] wire [34:0] _legal_address_T_42 = _legal_address_T_41 & 35'h7FFFFF000; // @[Parameters.scala:137:{41,46}] wire [34:0] _legal_address_T_43 = _legal_address_T_42; // @[Parameters.scala:137:46] wire _legal_address_T_44 = _legal_address_T_43 == 35'h0; // @[Parameters.scala:137:{46,59}] wire _legal_address_WIRE_8 = _legal_address_T_44; // @[Parameters.scala:612:40] wire [33:0] _legal_address_T_45 = {io_paddr_0[33:31], io_paddr_0[30:0] ^ 31'h60000000}; // @[PMA.scala:18:7] wire [34:0] _legal_address_T_46 = {1'h0, _legal_address_T_45}; // @[Parameters.scala:137:{31,41}] wire [34:0] _legal_address_T_47 = _legal_address_T_46 & 35'h7E0000000; // @[Parameters.scala:137:{41,46}] wire [34:0] _legal_address_T_48 = _legal_address_T_47; // @[Parameters.scala:137:46] wire _legal_address_T_49 = _legal_address_T_48 == 35'h0; // @[Parameters.scala:137:{46,59}] wire _legal_address_WIRE_9 = _legal_address_T_49; // @[Parameters.scala:612:40] wire [33:0] _GEN_4 = {io_paddr_0[33:32], io_paddr_0[31:0] ^ 32'h80000000}; // @[PMA.scala:18:7] wire [33:0] _legal_address_T_50; // @[Parameters.scala:137:31] assign _legal_address_T_50 = _GEN_4; // @[Parameters.scala:137:31] wire [33:0] _io_resp_x_T_20; // @[Parameters.scala:137:31] assign _io_resp_x_T_20 = _GEN_4; // @[Parameters.scala:137:31] wire [33:0] _io_resp_eff_T_39; // @[Parameters.scala:137:31] assign _io_resp_eff_T_39 = _GEN_4; // @[Parameters.scala:137:31] wire [34:0] _legal_address_T_51 = {1'h0, _legal_address_T_50}; // @[Parameters.scala:137:{31,41}] wire [34:0] _legal_address_T_52 = _legal_address_T_51 & 35'h7FFFFC000; // @[Parameters.scala:137:{41,46}] wire [34:0] _legal_address_T_53 = _legal_address_T_52; // @[Parameters.scala:137:46] wire _legal_address_T_54 = _legal_address_T_53 == 35'h0; // @[Parameters.scala:137:{46,59}] wire _legal_address_WIRE_10 = _legal_address_T_54; // @[Parameters.scala:612:40] wire _legal_address_T_55 = _legal_address_WIRE_0 | _legal_address_WIRE_1; // @[Parameters.scala:612:40] wire _legal_address_T_56 = _legal_address_T_55 | _legal_address_WIRE_2; // @[Parameters.scala:612:40] wire _legal_address_T_57 = _legal_address_T_56 | _legal_address_WIRE_3; // @[Parameters.scala:612:40] wire _legal_address_T_58 = _legal_address_T_57 | _legal_address_WIRE_4; // @[Parameters.scala:612:40] wire _legal_address_T_59 = _legal_address_T_58 | _legal_address_WIRE_5; // @[Parameters.scala:612:40] wire _legal_address_T_60 = _legal_address_T_59 | _legal_address_WIRE_6; // @[Parameters.scala:612:40] wire _legal_address_T_61 = _legal_address_T_60 | _legal_address_WIRE_7; // @[Parameters.scala:612:40] wire _legal_address_T_62 = _legal_address_T_61 | _legal_address_WIRE_8; // @[Parameters.scala:612:40] wire _legal_address_T_63 = _legal_address_T_62 | _legal_address_WIRE_9; // @[Parameters.scala:612:40] wire legal_address = _legal_address_T_63 | _legal_address_WIRE_10; // @[Parameters.scala:612:40] assign _io_resp_r_T_5 = legal_address; // @[PMA.scala:36:58, :39:19] wire [34:0] _io_resp_cacheable_T_1 = {1'h0, _io_resp_cacheable_T}; // @[Parameters.scala:137:{31,41}] wire [34:0] _io_resp_r_T_1 = {1'h0, _io_resp_r_T}; // @[Parameters.scala:137:{31,41}] assign io_resp_r_0 = _io_resp_r_T_5; // @[PMA.scala:18:7, :39:19] wire [34:0] _io_resp_w_T_1 = {1'h0, _io_resp_w_T}; // @[Parameters.scala:137:{31,41}] wire [34:0] _io_resp_w_T_2 = _io_resp_w_T_1 & 35'h48110000; // @[Parameters.scala:137:{41,46}] wire [34:0] _io_resp_w_T_3 = _io_resp_w_T_2; // @[Parameters.scala:137:46] wire _io_resp_w_T_4 = _io_resp_w_T_3 == 35'h0; // @[Parameters.scala:137:{46,59}] wire [34:0] _io_resp_w_T_6 = {1'h0, _io_resp_w_T_5}; // @[Parameters.scala:137:{31,41}] wire [34:0] _io_resp_w_T_7 = _io_resp_w_T_6 & 35'hC8101000; // @[Parameters.scala:137:{41,46}] wire [34:0] _io_resp_w_T_8 = _io_resp_w_T_7; // @[Parameters.scala:137:46] wire _io_resp_w_T_9 = _io_resp_w_T_8 == 35'h0; // @[Parameters.scala:137:{46,59}] wire [33:0] _GEN_5 = {io_paddr_0[33:28], io_paddr_0[27:0] ^ 28'h8000000}; // @[PMA.scala:18:7] wire [33:0] _io_resp_w_T_10; // @[Parameters.scala:137:31] assign _io_resp_w_T_10 = _GEN_5; // @[Parameters.scala:137:31] wire [33:0] _io_resp_pp_T_10; // @[Parameters.scala:137:31] assign _io_resp_pp_T_10 = _GEN_5; // @[Parameters.scala:137:31] wire [33:0] _io_resp_al_T_10; // @[Parameters.scala:137:31] assign _io_resp_al_T_10 = _GEN_5; // @[Parameters.scala:137:31] wire [33:0] _io_resp_aa_T_10; // @[Parameters.scala:137:31] assign _io_resp_aa_T_10 = _GEN_5; // @[Parameters.scala:137:31] wire [33:0] _io_resp_x_T_44; // @[Parameters.scala:137:31] assign _io_resp_x_T_44 = _GEN_5; // @[Parameters.scala:137:31] wire [33:0] _io_resp_eff_T_15; // @[Parameters.scala:137:31] assign _io_resp_eff_T_15 = _GEN_5; // @[Parameters.scala:137:31] wire [34:0] _io_resp_w_T_11 = {1'h0, _io_resp_w_T_10}; // @[Parameters.scala:137:{31,41}] wire [34:0] _io_resp_w_T_12 = _io_resp_w_T_11 & 35'hC8000000; // @[Parameters.scala:137:{41,46}] wire [34:0] _io_resp_w_T_13 = _io_resp_w_T_12; // @[Parameters.scala:137:46] wire _io_resp_w_T_14 = _io_resp_w_T_13 == 35'h0; // @[Parameters.scala:137:{46,59}] wire [33:0] _GEN_6 = {io_paddr_0[33:31], io_paddr_0[30:0] ^ 31'h40000000}; // @[PMA.scala:18:7] wire [33:0] _io_resp_w_T_15; // @[Parameters.scala:137:31] assign _io_resp_w_T_15 = _GEN_6; // @[Parameters.scala:137:31] wire [33:0] _io_resp_pp_T_15; // @[Parameters.scala:137:31] assign _io_resp_pp_T_15 = _GEN_6; // @[Parameters.scala:137:31] wire [33:0] _io_resp_al_T_22; // @[Parameters.scala:137:31] assign _io_resp_al_T_22 = _GEN_6; // @[Parameters.scala:137:31] wire [33:0] _io_resp_aa_T_22; // @[Parameters.scala:137:31] assign _io_resp_aa_T_22 = _GEN_6; // @[Parameters.scala:137:31] wire [33:0] _io_resp_x_T_15; // @[Parameters.scala:137:31] assign _io_resp_x_T_15 = _GEN_6; // @[Parameters.scala:137:31] wire [33:0] _io_resp_eff_T_20; // @[Parameters.scala:137:31] assign _io_resp_eff_T_20 = _GEN_6; // @[Parameters.scala:137:31] wire [34:0] _io_resp_w_T_16 = {1'h0, _io_resp_w_T_15}; // @[Parameters.scala:137:{31,41}] wire [34:0] _io_resp_w_T_17 = _io_resp_w_T_16 & 35'hC0000000; // @[Parameters.scala:137:{41,46}] wire [34:0] _io_resp_w_T_18 = _io_resp_w_T_17; // @[Parameters.scala:137:46] wire _io_resp_w_T_19 = _io_resp_w_T_18 == 35'h0; // @[Parameters.scala:137:{46,59}] wire _io_resp_w_T_20 = _io_resp_w_T_4 | _io_resp_w_T_9; // @[Parameters.scala:629:89] wire _io_resp_w_T_21 = _io_resp_w_T_20 | _io_resp_w_T_14; // @[Parameters.scala:629:89] wire _io_resp_w_T_22 = _io_resp_w_T_21 | _io_resp_w_T_19; // @[Parameters.scala:629:89] wire _io_resp_w_T_28 = _io_resp_w_T_22; // @[Mux.scala:30:73] wire [34:0] _io_resp_w_T_24 = {1'h0, _io_resp_w_T_23}; // @[Parameters.scala:137:{31,41}] wire [34:0] _io_resp_w_T_25 = _io_resp_w_T_24 & 35'hC8110000; // @[Parameters.scala:137:{41,46}] wire [34:0] _io_resp_w_T_26 = _io_resp_w_T_25; // @[Parameters.scala:137:46] wire _io_resp_w_T_27 = _io_resp_w_T_26 == 35'h0; // @[Parameters.scala:137:{46,59}] wire _io_resp_w_T_30 = _io_resp_w_T_28; // @[Mux.scala:30:73] wire _io_resp_w_WIRE = _io_resp_w_T_30; // @[Mux.scala:30:73] assign _io_resp_w_T_31 = legal_address & _io_resp_w_WIRE; // @[Mux.scala:30:73] assign io_resp_w_0 = _io_resp_w_T_31; // @[PMA.scala:18:7, :39:19] wire [34:0] _io_resp_pp_T_1 = {1'h0, _io_resp_pp_T}; // @[Parameters.scala:137:{31,41}] wire [34:0] _io_resp_pp_T_2 = _io_resp_pp_T_1 & 35'h48110000; // @[Parameters.scala:137:{41,46}] wire [34:0] _io_resp_pp_T_3 = _io_resp_pp_T_2; // @[Parameters.scala:137:46] wire _io_resp_pp_T_4 = _io_resp_pp_T_3 == 35'h0; // @[Parameters.scala:137:{46,59}] wire [34:0] _io_resp_pp_T_6 = {1'h0, _io_resp_pp_T_5}; // @[Parameters.scala:137:{31,41}] wire [34:0] _io_resp_pp_T_7 = _io_resp_pp_T_6 & 35'hC8101000; // @[Parameters.scala:137:{41,46}] wire [34:0] _io_resp_pp_T_8 = _io_resp_pp_T_7; // @[Parameters.scala:137:46] wire _io_resp_pp_T_9 = _io_resp_pp_T_8 == 35'h0; // @[Parameters.scala:137:{46,59}] wire [34:0] _io_resp_pp_T_11 = {1'h0, _io_resp_pp_T_10}; // @[Parameters.scala:137:{31,41}] wire [34:0] _io_resp_pp_T_12 = _io_resp_pp_T_11 & 35'hC8000000; // @[Parameters.scala:137:{41,46}] wire [34:0] _io_resp_pp_T_13 = _io_resp_pp_T_12; // @[Parameters.scala:137:46] wire _io_resp_pp_T_14 = _io_resp_pp_T_13 == 35'h0; // @[Parameters.scala:137:{46,59}] wire [34:0] _io_resp_pp_T_16 = {1'h0, _io_resp_pp_T_15}; // @[Parameters.scala:137:{31,41}] wire [34:0] _io_resp_pp_T_17 = _io_resp_pp_T_16 & 35'hC0000000; // @[Parameters.scala:137:{41,46}] wire [34:0] _io_resp_pp_T_18 = _io_resp_pp_T_17; // @[Parameters.scala:137:46] wire _io_resp_pp_T_19 = _io_resp_pp_T_18 == 35'h0; // @[Parameters.scala:137:{46,59}] wire _io_resp_pp_T_20 = _io_resp_pp_T_4 | _io_resp_pp_T_9; // @[Parameters.scala:629:89] wire _io_resp_pp_T_21 = _io_resp_pp_T_20 | _io_resp_pp_T_14; // @[Parameters.scala:629:89] wire _io_resp_pp_T_22 = _io_resp_pp_T_21 | _io_resp_pp_T_19; // @[Parameters.scala:629:89] wire _io_resp_pp_T_28 = _io_resp_pp_T_22; // @[Mux.scala:30:73] wire [34:0] _io_resp_pp_T_24 = {1'h0, _io_resp_pp_T_23}; // @[Parameters.scala:137:{31,41}] wire [34:0] _io_resp_pp_T_25 = _io_resp_pp_T_24 & 35'hC8110000; // @[Parameters.scala:137:{41,46}] wire [34:0] _io_resp_pp_T_26 = _io_resp_pp_T_25; // @[Parameters.scala:137:46] wire _io_resp_pp_T_27 = _io_resp_pp_T_26 == 35'h0; // @[Parameters.scala:137:{46,59}] wire _io_resp_pp_T_30 = _io_resp_pp_T_28; // @[Mux.scala:30:73] wire _io_resp_pp_WIRE = _io_resp_pp_T_30; // @[Mux.scala:30:73] assign _io_resp_pp_T_31 = legal_address & _io_resp_pp_WIRE; // @[Mux.scala:30:73] assign io_resp_pp_0 = _io_resp_pp_T_31; // @[PMA.scala:18:7, :39:19] wire [34:0] _io_resp_al_T_1 = {1'h0, _io_resp_al_T}; // @[Parameters.scala:137:{31,41}] wire [34:0] _io_resp_al_T_2 = _io_resp_al_T_1 & 35'h48110000; // @[Parameters.scala:137:{41,46}] wire [34:0] _io_resp_al_T_3 = _io_resp_al_T_2; // @[Parameters.scala:137:46] wire _io_resp_al_T_4 = _io_resp_al_T_3 == 35'h0; // @[Parameters.scala:137:{46,59}] wire [34:0] _io_resp_al_T_6 = {1'h0, _io_resp_al_T_5}; // @[Parameters.scala:137:{31,41}] wire [34:0] _io_resp_al_T_7 = _io_resp_al_T_6 & 35'h48101000; // @[Parameters.scala:137:{41,46}] wire [34:0] _io_resp_al_T_8 = _io_resp_al_T_7; // @[Parameters.scala:137:46] wire _io_resp_al_T_9 = _io_resp_al_T_8 == 35'h0; // @[Parameters.scala:137:{46,59}] wire [34:0] _io_resp_al_T_11 = {1'h0, _io_resp_al_T_10}; // @[Parameters.scala:137:{31,41}] wire [34:0] _io_resp_al_T_12 = _io_resp_al_T_11 & 35'h48000000; // @[Parameters.scala:137:{41,46}] wire [34:0] _io_resp_al_T_13 = _io_resp_al_T_12; // @[Parameters.scala:137:46] wire _io_resp_al_T_14 = _io_resp_al_T_13 == 35'h0; // @[Parameters.scala:137:{46,59}] wire _io_resp_al_T_15 = _io_resp_al_T_4 | _io_resp_al_T_9; // @[Parameters.scala:629:89] wire _io_resp_al_T_16 = _io_resp_al_T_15 | _io_resp_al_T_14; // @[Parameters.scala:629:89] wire _io_resp_al_T_28 = _io_resp_al_T_16; // @[Mux.scala:30:73] wire [34:0] _io_resp_al_T_18 = {1'h0, _io_resp_al_T_17}; // @[Parameters.scala:137:{31,41}] wire [34:0] _io_resp_al_T_19 = _io_resp_al_T_18 & 35'h48110000; // @[Parameters.scala:137:{41,46}] wire [34:0] _io_resp_al_T_20 = _io_resp_al_T_19; // @[Parameters.scala:137:46] wire _io_resp_al_T_21 = _io_resp_al_T_20 == 35'h0; // @[Parameters.scala:137:{46,59}] wire [34:0] _io_resp_al_T_23 = {1'h0, _io_resp_al_T_22}; // @[Parameters.scala:137:{31,41}] wire [34:0] _io_resp_al_T_24 = _io_resp_al_T_23 & 35'h40000000; // @[Parameters.scala:137:{41,46}] wire [34:0] _io_resp_al_T_25 = _io_resp_al_T_24; // @[Parameters.scala:137:46] wire _io_resp_al_T_26 = _io_resp_al_T_25 == 35'h0; // @[Parameters.scala:137:{46,59}] wire _io_resp_al_T_27 = _io_resp_al_T_21 | _io_resp_al_T_26; // @[Parameters.scala:629:89] wire _io_resp_al_T_30 = _io_resp_al_T_28; // @[Mux.scala:30:73] wire _io_resp_al_WIRE = _io_resp_al_T_30; // @[Mux.scala:30:73] assign _io_resp_al_T_31 = legal_address & _io_resp_al_WIRE; // @[Mux.scala:30:73] assign io_resp_al_0 = _io_resp_al_T_31; // @[PMA.scala:18:7, :39:19] wire [34:0] _io_resp_aa_T_1 = {1'h0, _io_resp_aa_T}; // @[Parameters.scala:137:{31,41}] wire [34:0] _io_resp_aa_T_2 = _io_resp_aa_T_1 & 35'h48110000; // @[Parameters.scala:137:{41,46}] wire [34:0] _io_resp_aa_T_3 = _io_resp_aa_T_2; // @[Parameters.scala:137:46] wire _io_resp_aa_T_4 = _io_resp_aa_T_3 == 35'h0; // @[Parameters.scala:137:{46,59}] wire [34:0] _io_resp_aa_T_6 = {1'h0, _io_resp_aa_T_5}; // @[Parameters.scala:137:{31,41}] wire [34:0] _io_resp_aa_T_7 = _io_resp_aa_T_6 & 35'h48101000; // @[Parameters.scala:137:{41,46}] wire [34:0] _io_resp_aa_T_8 = _io_resp_aa_T_7; // @[Parameters.scala:137:46] wire _io_resp_aa_T_9 = _io_resp_aa_T_8 == 35'h0; // @[Parameters.scala:137:{46,59}] wire [34:0] _io_resp_aa_T_11 = {1'h0, _io_resp_aa_T_10}; // @[Parameters.scala:137:{31,41}] wire [34:0] _io_resp_aa_T_12 = _io_resp_aa_T_11 & 35'h48000000; // @[Parameters.scala:137:{41,46}] wire [34:0] _io_resp_aa_T_13 = _io_resp_aa_T_12; // @[Parameters.scala:137:46] wire _io_resp_aa_T_14 = _io_resp_aa_T_13 == 35'h0; // @[Parameters.scala:137:{46,59}] wire _io_resp_aa_T_15 = _io_resp_aa_T_4 | _io_resp_aa_T_9; // @[Parameters.scala:629:89] wire _io_resp_aa_T_16 = _io_resp_aa_T_15 | _io_resp_aa_T_14; // @[Parameters.scala:629:89] wire _io_resp_aa_T_28 = _io_resp_aa_T_16; // @[Mux.scala:30:73] wire [34:0] _io_resp_aa_T_18 = {1'h0, _io_resp_aa_T_17}; // @[Parameters.scala:137:{31,41}] wire [34:0] _io_resp_aa_T_19 = _io_resp_aa_T_18 & 35'h48110000; // @[Parameters.scala:137:{41,46}] wire [34:0] _io_resp_aa_T_20 = _io_resp_aa_T_19; // @[Parameters.scala:137:46] wire _io_resp_aa_T_21 = _io_resp_aa_T_20 == 35'h0; // @[Parameters.scala:137:{46,59}] wire [34:0] _io_resp_aa_T_23 = {1'h0, _io_resp_aa_T_22}; // @[Parameters.scala:137:{31,41}] wire [34:0] _io_resp_aa_T_24 = _io_resp_aa_T_23 & 35'h40000000; // @[Parameters.scala:137:{41,46}] wire [34:0] _io_resp_aa_T_25 = _io_resp_aa_T_24; // @[Parameters.scala:137:46] wire _io_resp_aa_T_26 = _io_resp_aa_T_25 == 35'h0; // @[Parameters.scala:137:{46,59}] wire _io_resp_aa_T_27 = _io_resp_aa_T_21 | _io_resp_aa_T_26; // @[Parameters.scala:629:89] wire _io_resp_aa_T_30 = _io_resp_aa_T_28; // @[Mux.scala:30:73] wire _io_resp_aa_WIRE = _io_resp_aa_T_30; // @[Mux.scala:30:73] assign _io_resp_aa_T_31 = legal_address & _io_resp_aa_WIRE; // @[Mux.scala:30:73] assign io_resp_aa_0 = _io_resp_aa_T_31; // @[PMA.scala:18:7, :39:19] wire [34:0] _io_resp_x_T_1 = {1'h0, _io_resp_x_T}; // @[Parameters.scala:137:{31,41}] wire [34:0] _io_resp_x_T_2 = _io_resp_x_T_1 & 35'hDA113000; // @[Parameters.scala:137:{41,46}] wire [34:0] _io_resp_x_T_3 = _io_resp_x_T_2; // @[Parameters.scala:137:46] wire _io_resp_x_T_4 = _io_resp_x_T_3 == 35'h0; // @[Parameters.scala:137:{46,59}] wire [34:0] _io_resp_x_T_6 = {1'h0, _io_resp_x_T_5}; // @[Parameters.scala:137:{31,41}] wire [34:0] _io_resp_x_T_7 = _io_resp_x_T_6 & 35'hDA113000; // @[Parameters.scala:137:{41,46}] wire [34:0] _io_resp_x_T_8 = _io_resp_x_T_7; // @[Parameters.scala:137:46] wire _io_resp_x_T_9 = _io_resp_x_T_8 == 35'h0; // @[Parameters.scala:137:{46,59}] wire [34:0] _io_resp_x_T_11 = {1'h0, _io_resp_x_T_10}; // @[Parameters.scala:137:{31,41}] wire [34:0] _io_resp_x_T_12 = _io_resp_x_T_11 & 35'hDA110000; // @[Parameters.scala:137:{41,46}] wire [34:0] _io_resp_x_T_13 = _io_resp_x_T_12; // @[Parameters.scala:137:46] wire _io_resp_x_T_14 = _io_resp_x_T_13 == 35'h0; // @[Parameters.scala:137:{46,59}] wire [34:0] _io_resp_x_T_16 = {1'h0, _io_resp_x_T_15}; // @[Parameters.scala:137:{31,41}] wire [34:0] _io_resp_x_T_17 = _io_resp_x_T_16 & 35'hC0000000; // @[Parameters.scala:137:{41,46}] wire [34:0] _io_resp_x_T_18 = _io_resp_x_T_17; // @[Parameters.scala:137:46] wire _io_resp_x_T_19 = _io_resp_x_T_18 == 35'h0; // @[Parameters.scala:137:{46,59}] wire [34:0] _io_resp_x_T_21 = {1'h0, _io_resp_x_T_20}; // @[Parameters.scala:137:{31,41}] wire [34:0] _io_resp_x_T_22 = _io_resp_x_T_21 & 35'hDA110000; // @[Parameters.scala:137:{41,46}] wire [34:0] _io_resp_x_T_23 = _io_resp_x_T_22; // @[Parameters.scala:137:46] wire _io_resp_x_T_24 = _io_resp_x_T_23 == 35'h0; // @[Parameters.scala:137:{46,59}] wire _io_resp_x_T_25 = _io_resp_x_T_4 | _io_resp_x_T_9; // @[Parameters.scala:629:89] wire _io_resp_x_T_26 = _io_resp_x_T_25 | _io_resp_x_T_14; // @[Parameters.scala:629:89] wire _io_resp_x_T_27 = _io_resp_x_T_26 | _io_resp_x_T_19; // @[Parameters.scala:629:89] wire _io_resp_x_T_28 = _io_resp_x_T_27 | _io_resp_x_T_24; // @[Parameters.scala:629:89] wire _io_resp_x_T_58 = _io_resp_x_T_28; // @[Mux.scala:30:73] wire [34:0] _io_resp_x_T_30 = {1'h0, _io_resp_x_T_29}; // @[Parameters.scala:137:{31,41}] wire [34:0] _io_resp_x_T_31 = _io_resp_x_T_30 & 35'hDA113000; // @[Parameters.scala:137:{41,46}] wire [34:0] _io_resp_x_T_32 = _io_resp_x_T_31; // @[Parameters.scala:137:46] wire _io_resp_x_T_33 = _io_resp_x_T_32 == 35'h0; // @[Parameters.scala:137:{46,59}] wire [34:0] _io_resp_x_T_35 = {1'h0, _io_resp_x_T_34}; // @[Parameters.scala:137:{31,41}] wire [34:0] _io_resp_x_T_36 = _io_resp_x_T_35 & 35'hDA103000; // @[Parameters.scala:137:{41,46}] wire [34:0] _io_resp_x_T_37 = _io_resp_x_T_36; // @[Parameters.scala:137:46] wire _io_resp_x_T_38 = _io_resp_x_T_37 == 35'h0; // @[Parameters.scala:137:{46,59}] wire [34:0] _io_resp_x_T_40 = {1'h0, _io_resp_x_T_39}; // @[Parameters.scala:137:{31,41}] wire [34:0] _io_resp_x_T_41 = _io_resp_x_T_40 & 35'hDA110000; // @[Parameters.scala:137:{41,46}] wire [34:0] _io_resp_x_T_42 = _io_resp_x_T_41; // @[Parameters.scala:137:46] wire _io_resp_x_T_43 = _io_resp_x_T_42 == 35'h0; // @[Parameters.scala:137:{46,59}] wire [34:0] _io_resp_x_T_45 = {1'h0, _io_resp_x_T_44}; // @[Parameters.scala:137:{31,41}] wire [34:0] _io_resp_x_T_46 = _io_resp_x_T_45 & 35'hD8000000; // @[Parameters.scala:137:{41,46}] wire [34:0] _io_resp_x_T_47 = _io_resp_x_T_46; // @[Parameters.scala:137:46] wire _io_resp_x_T_48 = _io_resp_x_T_47 == 35'h0; // @[Parameters.scala:137:{46,59}] wire [33:0] _io_resp_x_T_49 = {io_paddr_0[33:29], io_paddr_0[28:0] ^ 29'h10000000}; // @[PMA.scala:18:7] wire [34:0] _io_resp_x_T_50 = {1'h0, _io_resp_x_T_49}; // @[Parameters.scala:137:{31,41}] wire [34:0] _io_resp_x_T_51 = _io_resp_x_T_50 & 35'hDA113000; // @[Parameters.scala:137:{41,46}] wire [34:0] _io_resp_x_T_52 = _io_resp_x_T_51; // @[Parameters.scala:137:46] wire _io_resp_x_T_53 = _io_resp_x_T_52 == 35'h0; // @[Parameters.scala:137:{46,59}] wire _io_resp_x_T_54 = _io_resp_x_T_33 | _io_resp_x_T_38; // @[Parameters.scala:629:89] wire _io_resp_x_T_55 = _io_resp_x_T_54 | _io_resp_x_T_43; // @[Parameters.scala:629:89] wire _io_resp_x_T_56 = _io_resp_x_T_55 | _io_resp_x_T_48; // @[Parameters.scala:629:89] wire _io_resp_x_T_57 = _io_resp_x_T_56 | _io_resp_x_T_53; // @[Parameters.scala:629:89] wire _io_resp_x_T_60 = _io_resp_x_T_58; // @[Mux.scala:30:73] wire _io_resp_x_WIRE = _io_resp_x_T_60; // @[Mux.scala:30:73] assign _io_resp_x_T_61 = legal_address & _io_resp_x_WIRE; // @[Mux.scala:30:73] assign io_resp_x_0 = _io_resp_x_T_61; // @[PMA.scala:18:7, :39:19] wire [34:0] _io_resp_eff_T_1 = {1'h0, _io_resp_eff_T}; // @[Parameters.scala:137:{31,41}] wire [34:0] _io_resp_eff_T_2 = _io_resp_eff_T_1 & 35'hCA112000; // @[Parameters.scala:137:{41,46}] wire [34:0] _io_resp_eff_T_3 = _io_resp_eff_T_2; // @[Parameters.scala:137:46] wire _io_resp_eff_T_4 = _io_resp_eff_T_3 == 35'h0; // @[Parameters.scala:137:{46,59}] wire [34:0] _io_resp_eff_T_6 = {1'h0, _io_resp_eff_T_5}; // @[Parameters.scala:137:{31,41}] wire [34:0] _io_resp_eff_T_7 = _io_resp_eff_T_6 & 35'hCA103000; // @[Parameters.scala:137:{41,46}] wire [34:0] _io_resp_eff_T_8 = _io_resp_eff_T_7; // @[Parameters.scala:137:46] wire _io_resp_eff_T_9 = _io_resp_eff_T_8 == 35'h0; // @[Parameters.scala:137:{46,59}] wire [34:0] _io_resp_eff_T_11 = {1'h0, _io_resp_eff_T_10}; // @[Parameters.scala:137:{31,41}] wire [34:0] _io_resp_eff_T_12 = _io_resp_eff_T_11 & 35'hCA110000; // @[Parameters.scala:137:{41,46}] wire [34:0] _io_resp_eff_T_13 = _io_resp_eff_T_12; // @[Parameters.scala:137:46] wire _io_resp_eff_T_14 = _io_resp_eff_T_13 == 35'h0; // @[Parameters.scala:137:{46,59}] wire [34:0] _io_resp_eff_T_16 = {1'h0, _io_resp_eff_T_15}; // @[Parameters.scala:137:{31,41}] wire [34:0] _io_resp_eff_T_17 = _io_resp_eff_T_16 & 35'hC8000000; // @[Parameters.scala:137:{41,46}] wire [34:0] _io_resp_eff_T_18 = _io_resp_eff_T_17; // @[Parameters.scala:137:46] wire _io_resp_eff_T_19 = _io_resp_eff_T_18 == 35'h0; // @[Parameters.scala:137:{46,59}] wire [34:0] _io_resp_eff_T_21 = {1'h0, _io_resp_eff_T_20}; // @[Parameters.scala:137:{31,41}] wire [34:0] _io_resp_eff_T_22 = _io_resp_eff_T_21 & 35'hC0000000; // @[Parameters.scala:137:{41,46}] wire [34:0] _io_resp_eff_T_23 = _io_resp_eff_T_22; // @[Parameters.scala:137:46] wire _io_resp_eff_T_24 = _io_resp_eff_T_23 == 35'h0; // @[Parameters.scala:137:{46,59}] wire _io_resp_eff_T_25 = _io_resp_eff_T_4 | _io_resp_eff_T_9; // @[Parameters.scala:629:89] wire _io_resp_eff_T_26 = _io_resp_eff_T_25 | _io_resp_eff_T_14; // @[Parameters.scala:629:89] wire _io_resp_eff_T_27 = _io_resp_eff_T_26 | _io_resp_eff_T_19; // @[Parameters.scala:629:89] wire _io_resp_eff_T_28 = _io_resp_eff_T_27 | _io_resp_eff_T_24; // @[Parameters.scala:629:89] wire _io_resp_eff_T_46 = _io_resp_eff_T_28; // @[Mux.scala:30:73] wire [34:0] _io_resp_eff_T_30 = {1'h0, _io_resp_eff_T_29}; // @[Parameters.scala:137:{31,41}] wire [34:0] _io_resp_eff_T_31 = _io_resp_eff_T_30 & 35'hCA113000; // @[Parameters.scala:137:{41,46}] wire [34:0] _io_resp_eff_T_32 = _io_resp_eff_T_31; // @[Parameters.scala:137:46] wire _io_resp_eff_T_33 = _io_resp_eff_T_32 == 35'h0; // @[Parameters.scala:137:{46,59}] wire [34:0] _io_resp_eff_T_35 = {1'h0, _io_resp_eff_T_34}; // @[Parameters.scala:137:{31,41}] wire [34:0] _io_resp_eff_T_36 = _io_resp_eff_T_35 & 35'hCA110000; // @[Parameters.scala:137:{41,46}] wire [34:0] _io_resp_eff_T_37 = _io_resp_eff_T_36; // @[Parameters.scala:137:46] wire _io_resp_eff_T_38 = _io_resp_eff_T_37 == 35'h0; // @[Parameters.scala:137:{46,59}] wire [34:0] _io_resp_eff_T_40 = {1'h0, _io_resp_eff_T_39}; // @[Parameters.scala:137:{31,41}] wire [34:0] _io_resp_eff_T_41 = _io_resp_eff_T_40 & 35'hCA110000; // @[Parameters.scala:137:{41,46}] wire [34:0] _io_resp_eff_T_42 = _io_resp_eff_T_41; // @[Parameters.scala:137:46] wire _io_resp_eff_T_43 = _io_resp_eff_T_42 == 35'h0; // @[Parameters.scala:137:{46,59}] wire _io_resp_eff_T_44 = _io_resp_eff_T_33 | _io_resp_eff_T_38; // @[Parameters.scala:629:89] wire _io_resp_eff_T_45 = _io_resp_eff_T_44 | _io_resp_eff_T_43; // @[Parameters.scala:629:89] wire _io_resp_eff_T_48 = _io_resp_eff_T_46; // @[Mux.scala:30:73] wire _io_resp_eff_WIRE = _io_resp_eff_T_48; // @[Mux.scala:30:73] assign _io_resp_eff_T_49 = legal_address & _io_resp_eff_WIRE; // @[Mux.scala:30:73] assign io_resp_eff_0 = _io_resp_eff_T_49; // @[PMA.scala:18:7, :39:19] assign io_resp_r = io_resp_r_0; // @[PMA.scala:18:7] assign io_resp_w = io_resp_w_0; // @[PMA.scala:18:7] assign io_resp_pp = io_resp_pp_0; // @[PMA.scala:18:7] assign io_resp_al = io_resp_al_0; // @[PMA.scala:18:7] assign io_resp_aa = io_resp_aa_0; // @[PMA.scala:18:7] assign io_resp_x = io_resp_x_0; // @[PMA.scala:18:7] assign io_resp_eff = io_resp_eff_0; // @[PMA.scala:18:7] endmodule

Generate the Verilog code corresponding to the following Chisel files. File primitives.scala: /*============================================================================ This Chisel source file is part of a pre-release version of the HardFloat IEEE Floating-Point Arithmetic Package, by John R. Hauser (with some contributions from Yunsup Lee and Andrew Waterman, mainly concerning testing). Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the University of California. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions, and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions, and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the University nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. =============================================================================*/ package hardfloat import chisel3._ import chisel3.util._ //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- object lowMask { def apply(in: UInt, topBound: BigInt, bottomBound: BigInt): UInt = { require(topBound != bottomBound) val numInVals = BigInt(1)<<in.getWidth if (topBound < bottomBound) { lowMask(~in, numInVals - 1 - topBound, numInVals - 1 - bottomBound) } else if (numInVals > 64 /* Empirical */) { // For simulation performance, we should avoid generating // exteremely wide shifters, so we divide and conquer. // Empirically, this does not impact synthesis QoR. val mid = numInVals / 2 val msb = in(in.getWidth - 1) val lsbs = in(in.getWidth - 2, 0) if (mid < topBound) { if (mid <= bottomBound) { Mux(msb, lowMask(lsbs, topBound - mid, bottomBound - mid), 0.U ) } else { Mux(msb, lowMask(lsbs, topBound - mid, 0) ## ((BigInt(1)<<(mid - bottomBound).toInt) - 1).U, lowMask(lsbs, mid, bottomBound) ) } } else { ~Mux(msb, 0.U, ~lowMask(lsbs, topBound, bottomBound)) } } else { val shift = (BigInt(-1)<<numInVals.toInt).S>>in Reverse( shift( (numInVals - 1 - bottomBound).toInt, (numInVals - topBound).toInt ) ) } } } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- object countLeadingZeros { def apply(in: UInt): UInt = PriorityEncoder(in.asBools.reverse) } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- object orReduceBy2 { def apply(in: UInt): UInt = { val reducedWidth = (in.getWidth + 1)>>1 val reducedVec = Wire(Vec(reducedWidth, Bool())) for (ix <- 0 until reducedWidth - 1) { reducedVec(ix) := in(ix * 2 + 1, ix * 2).orR } reducedVec(reducedWidth - 1) := in(in.getWidth - 1, (reducedWidth - 1) * 2).orR reducedVec.asUInt } } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- object orReduceBy4 { def apply(in: UInt): UInt = { val reducedWidth = (in.getWidth + 3)>>2 val reducedVec = Wire(Vec(reducedWidth, Bool())) for (ix <- 0 until reducedWidth - 1) { reducedVec(ix) := in(ix * 4 + 3, ix * 4).orR } reducedVec(reducedWidth - 1) := in(in.getWidth - 1, (reducedWidth - 1) * 4).orR reducedVec.asUInt } } File MulAddRecFN.scala: /*============================================================================ This Chisel source file is part of a pre-release version of the HardFloat IEEE Floating-Point Arithmetic Package, by John R. Hauser (with some contributions from Yunsup Lee and Andrew Waterman, mainly concerning testing). Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the University of California. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions, and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions, and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the University nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. =============================================================================*/ package hardfloat import chisel3._ import chisel3.util._ import consts._ //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- class MulAddRecFN_interIo(expWidth: Int, sigWidth: Int) extends Bundle { //*** ENCODE SOME OF THESE CASES IN FEWER BITS?: val isSigNaNAny = Bool() val isNaNAOrB = Bool() val isInfA = Bool() val isZeroA = Bool() val isInfB = Bool() val isZeroB = Bool() val signProd = Bool() val isNaNC = Bool() val isInfC = Bool() val isZeroC = Bool() val sExpSum = SInt((expWidth + 2).W) val doSubMags = Bool() val CIsDominant = Bool() val CDom_CAlignDist = UInt(log2Ceil(sigWidth + 1).W) val highAlignedSigC = UInt((sigWidth + 2).W) val bit0AlignedSigC = UInt(1.W) } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- class MulAddRecFNToRaw_preMul(expWidth: Int, sigWidth: Int) extends RawModule { override def desiredName = s"MulAddRecFNToRaw_preMul_e${expWidth}_s${sigWidth}" val io = IO(new Bundle { val op = Input(Bits(2.W)) val a = Input(Bits((expWidth + sigWidth + 1).W)) val b = Input(Bits((expWidth + sigWidth + 1).W)) val c = Input(Bits((expWidth + sigWidth + 1).W)) val mulAddA = Output(UInt(sigWidth.W)) val mulAddB = Output(UInt(sigWidth.W)) val mulAddC = Output(UInt((sigWidth * 2).W)) val toPostMul = Output(new MulAddRecFN_interIo(expWidth, sigWidth)) }) //------------------------------------------------------------------------ //------------------------------------------------------------------------ //*** POSSIBLE TO REDUCE THIS BY 1 OR 2 BITS? (CURRENTLY 2 BITS BETWEEN //*** UNSHIFTED C AND PRODUCT): val sigSumWidth = sigWidth * 3 + 3 //------------------------------------------------------------------------ //------------------------------------------------------------------------ val rawA = rawFloatFromRecFN(expWidth, sigWidth, io.a) val rawB = rawFloatFromRecFN(expWidth, sigWidth, io.b) val rawC = rawFloatFromRecFN(expWidth, sigWidth, io.c) val signProd = rawA.sign ^ rawB.sign ^ io.op(1) //*** REVIEW THE BIAS FOR 'sExpAlignedProd': val sExpAlignedProd = rawA.sExp +& rawB.sExp + (-(BigInt(1)<<expWidth) + sigWidth + 3).S val doSubMags = signProd ^ rawC.sign ^ io.op(0) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val sNatCAlignDist = sExpAlignedProd - rawC.sExp val posNatCAlignDist = sNatCAlignDist(expWidth + 1, 0) val isMinCAlign = rawA.isZero || rawB.isZero || (sNatCAlignDist < 0.S) val CIsDominant = ! rawC.isZero && (isMinCAlign || (posNatCAlignDist <= sigWidth.U)) val CAlignDist = Mux(isMinCAlign, 0.U, Mux(posNatCAlignDist < (sigSumWidth - 1).U, posNatCAlignDist(log2Ceil(sigSumWidth) - 1, 0), (sigSumWidth - 1).U ) ) val mainAlignedSigC = (Mux(doSubMags, ~rawC.sig, rawC.sig) ## Fill(sigSumWidth - sigWidth + 2, doSubMags)).asSInt>>CAlignDist val reduced4CExtra = (orReduceBy4(rawC.sig<<((sigSumWidth - sigWidth - 1) & 3)) & lowMask( CAlignDist>>2, //*** NOT NEEDED?: // (sigSumWidth + 2)>>2, (sigSumWidth - 1)>>2, (sigSumWidth - sigWidth - 1)>>2 ) ).orR val alignedSigC = Cat(mainAlignedSigC>>3, Mux(doSubMags, mainAlignedSigC(2, 0).andR && ! reduced4CExtra, mainAlignedSigC(2, 0).orR || reduced4CExtra ) ) //------------------------------------------------------------------------ //------------------------------------------------------------------------ io.mulAddA := rawA.sig io.mulAddB := rawB.sig io.mulAddC := alignedSigC(sigWidth * 2, 1) io.toPostMul.isSigNaNAny := isSigNaNRawFloat(rawA) || isSigNaNRawFloat(rawB) || isSigNaNRawFloat(rawC) io.toPostMul.isNaNAOrB := rawA.isNaN || rawB.isNaN io.toPostMul.isInfA := rawA.isInf io.toPostMul.isZeroA := rawA.isZero io.toPostMul.isInfB := rawB.isInf io.toPostMul.isZeroB := rawB.isZero io.toPostMul.signProd := signProd io.toPostMul.isNaNC := rawC.isNaN io.toPostMul.isInfC := rawC.isInf io.toPostMul.isZeroC := rawC.isZero io.toPostMul.sExpSum := Mux(CIsDominant, rawC.sExp, sExpAlignedProd - sigWidth.S) io.toPostMul.doSubMags := doSubMags io.toPostMul.CIsDominant := CIsDominant io.toPostMul.CDom_CAlignDist := CAlignDist(log2Ceil(sigWidth + 1) - 1, 0) io.toPostMul.highAlignedSigC := alignedSigC(sigSumWidth - 1, sigWidth * 2 + 1) io.toPostMul.bit0AlignedSigC := alignedSigC(0) } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- class MulAddRecFNToRaw_postMul(expWidth: Int, sigWidth: Int) extends RawModule { override def desiredName = s"MulAddRecFNToRaw_postMul_e${expWidth}_s${sigWidth}" val io = IO(new Bundle { val fromPreMul = Input(new MulAddRecFN_interIo(expWidth, sigWidth)) val mulAddResult = Input(UInt((sigWidth * 2 + 1).W)) val roundingMode = Input(UInt(3.W)) val invalidExc = Output(Bool()) val rawOut = Output(new RawFloat(expWidth, sigWidth + 2)) }) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val sigSumWidth = sigWidth * 3 + 3 //------------------------------------------------------------------------ //------------------------------------------------------------------------ val roundingMode_min = (io.roundingMode === round_min) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val opSignC = io.fromPreMul.signProd ^ io.fromPreMul.doSubMags val sigSum = Cat(Mux(io.mulAddResult(sigWidth * 2), io.fromPreMul.highAlignedSigC + 1.U, io.fromPreMul.highAlignedSigC ), io.mulAddResult(sigWidth * 2 - 1, 0), io.fromPreMul.bit0AlignedSigC ) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val CDom_sign = opSignC val CDom_sExp = io.fromPreMul.sExpSum - io.fromPreMul.doSubMags.zext val CDom_absSigSum = Mux(io.fromPreMul.doSubMags, ~sigSum(sigSumWidth - 1, sigWidth + 1), 0.U(1.W) ## //*** IF GAP IS REDUCED TO 1 BIT, MUST REDUCE THIS COMPONENT TO 1 BIT TOO: io.fromPreMul.highAlignedSigC(sigWidth + 1, sigWidth) ## sigSum(sigSumWidth - 3, sigWidth + 2) ) val CDom_absSigSumExtra = Mux(io.fromPreMul.doSubMags, (~sigSum(sigWidth, 1)).orR, sigSum(sigWidth + 1, 1).orR ) val CDom_mainSig = (CDom_absSigSum<<io.fromPreMul.CDom_CAlignDist)( sigWidth * 2 + 1, sigWidth - 3) val CDom_reduced4SigExtra = (orReduceBy4(CDom_absSigSum(sigWidth - 1, 0)<<(~sigWidth & 3)) & lowMask(io.fromPreMul.CDom_CAlignDist>>2, 0, sigWidth>>2)).orR val CDom_sig = Cat(CDom_mainSig>>3, CDom_mainSig(2, 0).orR || CDom_reduced4SigExtra || CDom_absSigSumExtra ) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val notCDom_signSigSum = sigSum(sigWidth * 2 + 3) val notCDom_absSigSum = Mux(notCDom_signSigSum, ~sigSum(sigWidth * 2 + 2, 0), sigSum(sigWidth * 2 + 2, 0) + io.fromPreMul.doSubMags ) val notCDom_reduced2AbsSigSum = orReduceBy2(notCDom_absSigSum) val notCDom_normDistReduced2 = countLeadingZeros(notCDom_reduced2AbsSigSum) val notCDom_nearNormDist = notCDom_normDistReduced2<<1 val notCDom_sExp = io.fromPreMul.sExpSum - notCDom_nearNormDist.asUInt.zext val notCDom_mainSig = (notCDom_absSigSum<<notCDom_nearNormDist)( sigWidth * 2 + 3, sigWidth - 1) val notCDom_reduced4SigExtra = (orReduceBy2( notCDom_reduced2AbsSigSum(sigWidth>>1, 0)<<((sigWidth>>1) & 1)) & lowMask(notCDom_normDistReduced2>>1, 0, (sigWidth + 2)>>2) ).orR val notCDom_sig = Cat(notCDom_mainSig>>3, notCDom_mainSig(2, 0).orR || notCDom_reduced4SigExtra ) val notCDom_completeCancellation = (notCDom_sig(sigWidth + 2, sigWidth + 1) === 0.U) val notCDom_sign = Mux(notCDom_completeCancellation, roundingMode_min, io.fromPreMul.signProd ^ notCDom_signSigSum ) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val notNaN_isInfProd = io.fromPreMul.isInfA || io.fromPreMul.isInfB val notNaN_isInfOut = notNaN_isInfProd || io.fromPreMul.isInfC val notNaN_addZeros = (io.fromPreMul.isZeroA || io.fromPreMul.isZeroB) && io.fromPreMul.isZeroC io.invalidExc := io.fromPreMul.isSigNaNAny || (io.fromPreMul.isInfA && io.fromPreMul.isZeroB) || (io.fromPreMul.isZeroA && io.fromPreMul.isInfB) || (! io.fromPreMul.isNaNAOrB && (io.fromPreMul.isInfA || io.fromPreMul.isInfB) && io.fromPreMul.isInfC && io.fromPreMul.doSubMags) io.rawOut.isNaN := io.fromPreMul.isNaNAOrB || io.fromPreMul.isNaNC io.rawOut.isInf := notNaN_isInfOut //*** IMPROVE?: io.rawOut.isZero := notNaN_addZeros || (! io.fromPreMul.CIsDominant && notCDom_completeCancellation) io.rawOut.sign := (notNaN_isInfProd && io.fromPreMul.signProd) || (io.fromPreMul.isInfC && opSignC) || (notNaN_addZeros && ! roundingMode_min && io.fromPreMul.signProd && opSignC) || (notNaN_addZeros && roundingMode_min && (io.fromPreMul.signProd || opSignC)) || (! notNaN_isInfOut && ! notNaN_addZeros && Mux(io.fromPreMul.CIsDominant, CDom_sign, notCDom_sign)) io.rawOut.sExp := Mux(io.fromPreMul.CIsDominant, CDom_sExp, notCDom_sExp) io.rawOut.sig := Mux(io.fromPreMul.CIsDominant, CDom_sig, notCDom_sig) } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- class MulAddRecFN(expWidth: Int, sigWidth: Int) extends RawModule { override def desiredName = s"MulAddRecFN_e${expWidth}_s${sigWidth}" val io = IO(new Bundle { val op = Input(Bits(2.W)) val a = Input(Bits((expWidth + sigWidth + 1).W)) val b = Input(Bits((expWidth + sigWidth + 1).W)) val c = Input(Bits((expWidth + sigWidth + 1).W)) val roundingMode = Input(UInt(3.W)) val detectTininess = Input(UInt(1.W)) val out = Output(Bits((expWidth + sigWidth + 1).W)) val exceptionFlags = Output(Bits(5.W)) }) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val mulAddRecFNToRaw_preMul = Module(new MulAddRecFNToRaw_preMul(expWidth, sigWidth)) val mulAddRecFNToRaw_postMul = Module(new MulAddRecFNToRaw_postMul(expWidth, sigWidth)) mulAddRecFNToRaw_preMul.io.op := io.op mulAddRecFNToRaw_preMul.io.a := io.a mulAddRecFNToRaw_preMul.io.b := io.b mulAddRecFNToRaw_preMul.io.c := io.c val mulAddResult = (mulAddRecFNToRaw_preMul.io.mulAddA * mulAddRecFNToRaw_preMul.io.mulAddB) +& mulAddRecFNToRaw_preMul.io.mulAddC mulAddRecFNToRaw_postMul.io.fromPreMul := mulAddRecFNToRaw_preMul.io.toPostMul mulAddRecFNToRaw_postMul.io.mulAddResult := mulAddResult mulAddRecFNToRaw_postMul.io.roundingMode := io.roundingMode //------------------------------------------------------------------------ //------------------------------------------------------------------------ val roundRawFNToRecFN = Module(new RoundRawFNToRecFN(expWidth, sigWidth, 0)) roundRawFNToRecFN.io.invalidExc := mulAddRecFNToRaw_postMul.io.invalidExc roundRawFNToRecFN.io.infiniteExc := false.B roundRawFNToRecFN.io.in := mulAddRecFNToRaw_postMul.io.rawOut roundRawFNToRecFN.io.roundingMode := io.roundingMode roundRawFNToRecFN.io.detectTininess := io.detectTininess io.out := roundRawFNToRecFN.io.out io.exceptionFlags := roundRawFNToRecFN.io.exceptionFlags } File rawFloatFromRecFN.scala: /*============================================================================ This Chisel source file is part of a pre-release version of the HardFloat IEEE Floating-Point Arithmetic Package, by John R. Hauser (with some contributions from Yunsup Lee and Andrew Waterman, mainly concerning testing). Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of California. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions, and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions, and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the University nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. =============================================================================*/ package hardfloat import chisel3._ import chisel3.util._ /*---------------------------------------------------------------------------- | In the result, no more than one of 'isNaN', 'isInf', and 'isZero' will be | set. *----------------------------------------------------------------------------*/ object rawFloatFromRecFN { def apply(expWidth: Int, sigWidth: Int, in: Bits): RawFloat = { val exp = in(expWidth + sigWidth - 1, sigWidth - 1) val isZero = exp(expWidth, expWidth - 2) === 0.U val isSpecial = exp(expWidth, expWidth - 1) === 3.U val out = Wire(new RawFloat(expWidth, sigWidth)) out.isNaN := isSpecial && exp(expWidth - 2) out.isInf := isSpecial && ! exp(expWidth - 2) out.isZero := isZero out.sign := in(expWidth + sigWidth) out.sExp := exp.zext out.sig := 0.U(1.W) ## ! isZero ## in(sigWidth - 2, 0) out } } File common.scala: /*============================================================================ This Chisel source file is part of a pre-release version of the HardFloat IEEE Floating-Point Arithmetic Package, by John R. Hauser (with some contributions from Yunsup Lee and Andrew Waterman, mainly concerning testing). Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017, 2018 The Regents of the University of California. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions, and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions, and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the University nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. =============================================================================*/ package hardfloat import chisel3._ object consts { /*------------------------------------------------------------------------ | For rounding to integer values, rounding mode 'odd' rounds to minimum | magnitude instead, same as 'minMag'. *------------------------------------------------------------------------*/ def round_near_even = "b000".U(3.W) def round_minMag = "b001".U(3.W) def round_min = "b010".U(3.W) def round_max = "b011".U(3.W) def round_near_maxMag = "b100".U(3.W) def round_odd = "b110".U(3.W) /*------------------------------------------------------------------------ *------------------------------------------------------------------------*/ def tininess_beforeRounding = 0.U def tininess_afterRounding = 1.U /*------------------------------------------------------------------------ *------------------------------------------------------------------------*/ def flRoundOpt_sigMSBitAlwaysZero = 1 def flRoundOpt_subnormsAlwaysExact = 2 def flRoundOpt_neverUnderflows = 4 def flRoundOpt_neverOverflows = 8 /*------------------------------------------------------------------------ *------------------------------------------------------------------------*/ def divSqrtOpt_twoBitsPerCycle = 16 } class RawFloat(val expWidth: Int, val sigWidth: Int) extends Bundle { val isNaN: Bool = Bool() // overrides all other fields val isInf: Bool = Bool() // overrides 'isZero', 'sExp', and 'sig' val isZero: Bool = Bool() // overrides 'sExp' and 'sig' val sign: Bool = Bool() val sExp: SInt = SInt((expWidth + 2).W) val sig: UInt = UInt((sigWidth + 1).W) // 2 m.s. bits cannot both be 0 } //*** CHANGE THIS INTO A '.isSigNaN' METHOD OF THE 'RawFloat' CLASS: object isSigNaNRawFloat { def apply(in: RawFloat): Bool = in.isNaN && !in.sig(in.sigWidth - 2) }

module MulAddRecFNToRaw_preMul_e8_s24_63( // @[MulAddRecFN.scala:71:7] input [32:0] io_a, // @[MulAddRecFN.scala:74:16] input [32:0] io_c, // @[MulAddRecFN.scala:74:16] output [23:0] io_mulAddA, // @[MulAddRecFN.scala:74:16] output [47:0] io_mulAddC, // @[MulAddRecFN.scala:74:16] output io_toPostMul_isSigNaNAny, // @[MulAddRecFN.scala:74:16] output io_toPostMul_isNaNAOrB, // @[MulAddRecFN.scala:74:16] output io_toPostMul_isInfA, // @[MulAddRecFN.scala:74:16] output io_toPostMul_isZeroA, // @[MulAddRecFN.scala:74:16] output io_toPostMul_signProd, // @[MulAddRecFN.scala:74:16] output io_toPostMul_isNaNC, // @[MulAddRecFN.scala:74:16] output io_toPostMul_isInfC, // @[MulAddRecFN.scala:74:16] output io_toPostMul_isZeroC, // @[MulAddRecFN.scala:74:16] output [9:0] io_toPostMul_sExpSum, // @[MulAddRecFN.scala:74:16] output io_toPostMul_doSubMags, // @[MulAddRecFN.scala:74:16] output io_toPostMul_CIsDominant, // @[MulAddRecFN.scala:74:16] output [4:0] io_toPostMul_CDom_CAlignDist, // @[MulAddRecFN.scala:74:16] output [25:0] io_toPostMul_highAlignedSigC, // @[MulAddRecFN.scala:74:16] output io_toPostMul_bit0AlignedSigC // @[MulAddRecFN.scala:74:16] ); wire rawA_sign; // @[rawFloatFromRecFN.scala:55:23] wire rawA_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire [32:0] io_a_0 = io_a; // @[MulAddRecFN.scala:71:7] wire [32:0] io_c_0 = io_c; // @[MulAddRecFN.scala:71:7] wire [8:0] rawB_exp = 9'h100; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _rawB_isZero_T = 3'h4; // @[rawFloatFromRecFN.scala:52:28] wire [1:0] _rawB_isSpecial_T = 2'h2; // @[rawFloatFromRecFN.scala:53:28] wire [9:0] rawB_sExp = 10'h100; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire [9:0] _rawB_out_sExp_T = 10'h100; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire [1:0] _rawB_out_sig_T_1 = 2'h1; // @[rawFloatFromRecFN.scala:61:32] wire [22:0] _rawB_out_sig_T_2 = 23'h0; // @[rawFloatFromRecFN.scala:61:49] wire [24:0] rawB_sig = 25'h800000; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire [24:0] _rawB_out_sig_T_3 = 25'h800000; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire _rawB_out_isInf_T_1 = 1'h1; // @[rawFloatFromRecFN.scala:57:36, :61:35] wire _rawB_out_sig_T = 1'h1; // @[rawFloatFromRecFN.scala:57:36, :61:35] wire _io_toPostMul_isSigNaNAny_T_4 = 1'h1; // @[rawFloatFromRecFN.scala:57:36, :61:35] wire io_toPostMul_isInfB = 1'h0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_isZeroB = 1'h0; // @[MulAddRecFN.scala:71:7] wire rawB_isZero = 1'h0; // @[rawFloatFromRecFN.scala:52:53] wire rawB_isSpecial = 1'h0; // @[rawFloatFromRecFN.scala:53:53] wire rawB_isNaN = 1'h0; // @[rawFloatFromRecFN.scala:55:23] wire rawB_isInf = 1'h0; // @[rawFloatFromRecFN.scala:55:23] wire rawB_isZero_0 = 1'h0; // @[rawFloatFromRecFN.scala:55:23] wire rawB_sign = 1'h0; // @[rawFloatFromRecFN.scala:55:23] wire _rawB_out_isNaN_T = 1'h0; // @[rawFloatFromRecFN.scala:56:41] wire _rawB_out_isNaN_T_1 = 1'h0; // @[rawFloatFromRecFN.scala:56:33] wire _rawB_out_isInf_T = 1'h0; // @[rawFloatFromRecFN.scala:57:41] wire _rawB_out_isInf_T_2 = 1'h0; // @[rawFloatFromRecFN.scala:57:33] wire _rawB_out_sign_T = 1'h0; // @[rawFloatFromRecFN.scala:59:25] wire _signProd_T_1 = 1'h0; // @[MulAddRecFN.scala:97:49] wire _doSubMags_T_1 = 1'h0; // @[MulAddRecFN.scala:102:49] wire _io_toPostMul_isSigNaNAny_T_3 = 1'h0; // @[common.scala:82:56] wire _io_toPostMul_isSigNaNAny_T_5 = 1'h0; // @[common.scala:82:46] wire [23:0] io_mulAddB = 24'h800000; // @[MulAddRecFN.scala:71:7, :74:16, :142:16] wire [32:0] io_b = 33'h80000000; // @[MulAddRecFN.scala:71:7, :74:16] wire [1:0] io_op = 2'h0; // @[MulAddRecFN.scala:71:7, :74:16] wire [47:0] _io_mulAddC_T; // @[MulAddRecFN.scala:143:30] wire _io_toPostMul_isSigNaNAny_T_10; // @[MulAddRecFN.scala:146:58] wire _io_toPostMul_isNaNAOrB_T; // @[MulAddRecFN.scala:148:42] wire rawA_isInf; // @[rawFloatFromRecFN.scala:55:23] wire rawA_isZero; // @[rawFloatFromRecFN.scala:55:23] wire signProd; // @[MulAddRecFN.scala:97:42] wire rawC_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire rawC_isInf; // @[rawFloatFromRecFN.scala:55:23] wire rawC_isZero; // @[rawFloatFromRecFN.scala:55:23] wire doSubMags; // @[MulAddRecFN.scala:102:42] wire CIsDominant; // @[MulAddRecFN.scala:110:23] wire [4:0] _io_toPostMul_CDom_CAlignDist_T; // @[MulAddRecFN.scala:161:47] wire [25:0] _io_toPostMul_highAlignedSigC_T; // @[MulAddRecFN.scala:163:20] wire _io_toPostMul_bit0AlignedSigC_T; // @[MulAddRecFN.scala:164:48] wire io_toPostMul_isSigNaNAny_0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_isNaNAOrB_0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_isInfA_0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_isZeroA_0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_signProd_0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_isNaNC_0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_isInfC_0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_isZeroC_0; // @[MulAddRecFN.scala:71:7] wire [9:0] io_toPostMul_sExpSum_0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_doSubMags_0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_CIsDominant_0; // @[MulAddRecFN.scala:71:7] wire [4:0] io_toPostMul_CDom_CAlignDist_0; // @[MulAddRecFN.scala:71:7] wire [25:0] io_toPostMul_highAlignedSigC_0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_bit0AlignedSigC_0; // @[MulAddRecFN.scala:71:7] wire [23:0] io_mulAddA_0; // @[MulAddRecFN.scala:71:7] wire [47:0] io_mulAddC_0; // @[MulAddRecFN.scala:71:7] wire [8:0] rawA_exp = io_a_0[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _rawA_isZero_T = rawA_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire rawA_isZero_0 = _rawA_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] assign rawA_isZero = rawA_isZero_0; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _rawA_isSpecial_T = rawA_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire rawA_isSpecial = &_rawA_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _rawA_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33] wire _rawA_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33] assign _io_toPostMul_isNaNAOrB_T = rawA_isNaN; // @[rawFloatFromRecFN.scala:55:23] assign io_toPostMul_isInfA_0 = rawA_isInf; // @[rawFloatFromRecFN.scala:55:23] assign io_toPostMul_isZeroA_0 = rawA_isZero; // @[rawFloatFromRecFN.scala:55:23] wire _rawA_out_sign_T; // @[rawFloatFromRecFN.scala:59:25] wire _isMinCAlign_T = rawA_isZero; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] _rawA_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27] wire _signProd_T = rawA_sign; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] _rawA_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44] wire [9:0] rawA_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] rawA_sig; // @[rawFloatFromRecFN.scala:55:23] wire _rawA_out_isNaN_T = rawA_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _rawA_out_isInf_T = rawA_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _rawA_out_isNaN_T_1 = rawA_isSpecial & _rawA_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign rawA_isNaN = _rawA_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _rawA_out_isInf_T_1 = ~_rawA_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _rawA_out_isInf_T_2 = rawA_isSpecial & _rawA_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign rawA_isInf = _rawA_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _rawA_out_sign_T = io_a_0[32]; // @[rawFloatFromRecFN.scala:59:25] assign rawA_sign = _rawA_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _rawA_out_sExp_T = {1'h0, rawA_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign rawA_sExp = _rawA_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _rawA_out_sig_T = ~rawA_isZero_0; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _rawA_out_sig_T_1 = {1'h0, _rawA_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _rawA_out_sig_T_2 = io_a_0[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _rawA_out_sig_T_3 = {_rawA_out_sig_T_1, _rawA_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign rawA_sig = _rawA_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire [8:0] rawC_exp = io_c_0[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _rawC_isZero_T = rawC_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire rawC_isZero_0 = _rawC_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] assign rawC_isZero = rawC_isZero_0; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _rawC_isSpecial_T = rawC_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire rawC_isSpecial = &_rawC_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _rawC_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33] assign io_toPostMul_isNaNC_0 = rawC_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire _rawC_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33] assign io_toPostMul_isInfC_0 = rawC_isInf; // @[rawFloatFromRecFN.scala:55:23] assign io_toPostMul_isZeroC_0 = rawC_isZero; // @[rawFloatFromRecFN.scala:55:23] wire _rawC_out_sign_T; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _rawC_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _rawC_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44] wire rawC_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] rawC_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] rawC_sig; // @[rawFloatFromRecFN.scala:55:23] wire _rawC_out_isNaN_T = rawC_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _rawC_out_isInf_T = rawC_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _rawC_out_isNaN_T_1 = rawC_isSpecial & _rawC_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign rawC_isNaN = _rawC_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _rawC_out_isInf_T_1 = ~_rawC_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _rawC_out_isInf_T_2 = rawC_isSpecial & _rawC_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign rawC_isInf = _rawC_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _rawC_out_sign_T = io_c_0[32]; // @[rawFloatFromRecFN.scala:59:25] assign rawC_sign = _rawC_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _rawC_out_sExp_T = {1'h0, rawC_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign rawC_sExp = _rawC_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _rawC_out_sig_T = ~rawC_isZero_0; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _rawC_out_sig_T_1 = {1'h0, _rawC_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _rawC_out_sig_T_2 = io_c_0[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _rawC_out_sig_T_3 = {_rawC_out_sig_T_1, _rawC_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign rawC_sig = _rawC_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44] assign signProd = _signProd_T; // @[MulAddRecFN.scala:97:{30,42}] assign io_toPostMul_signProd_0 = signProd; // @[MulAddRecFN.scala:71:7, :97:42] wire [10:0] _sExpAlignedProd_T = {rawA_sExp[9], rawA_sExp} + 11'h100; // @[rawFloatFromRecFN.scala:55:23] wire [11:0] _sExpAlignedProd_T_1 = {_sExpAlignedProd_T[10], _sExpAlignedProd_T} - 12'hE5; // @[MulAddRecFN.scala:100:{19,32}] wire [10:0] _sExpAlignedProd_T_2 = _sExpAlignedProd_T_1[10:0]; // @[MulAddRecFN.scala:100:32] wire [10:0] sExpAlignedProd = _sExpAlignedProd_T_2; // @[MulAddRecFN.scala:100:32] wire _doSubMags_T = signProd ^ rawC_sign; // @[rawFloatFromRecFN.scala:55:23] assign doSubMags = _doSubMags_T; // @[MulAddRecFN.scala:102:{30,42}] assign io_toPostMul_doSubMags_0 = doSubMags; // @[MulAddRecFN.scala:71:7, :102:42] wire [11:0] _GEN = {sExpAlignedProd[10], sExpAlignedProd}; // @[MulAddRecFN.scala:100:32, :106:42] wire [11:0] _sNatCAlignDist_T = _GEN - {{2{rawC_sExp[9]}}, rawC_sExp}; // @[rawFloatFromRecFN.scala:55:23] wire [10:0] _sNatCAlignDist_T_1 = _sNatCAlignDist_T[10:0]; // @[MulAddRecFN.scala:106:42] wire [10:0] sNatCAlignDist = _sNatCAlignDist_T_1; // @[MulAddRecFN.scala:106:42] wire [9:0] posNatCAlignDist = sNatCAlignDist[9:0]; // @[MulAddRecFN.scala:106:42, :107:42] wire _isMinCAlign_T_1 = $signed(sNatCAlignDist) < 11'sh0; // @[MulAddRecFN.scala:106:42, :108:69] wire isMinCAlign = _isMinCAlign_T | _isMinCAlign_T_1; // @[MulAddRecFN.scala:108:{35,50,69}] wire _CIsDominant_T = ~rawC_isZero; // @[rawFloatFromRecFN.scala:55:23] wire _CIsDominant_T_1 = posNatCAlignDist < 10'h19; // @[MulAddRecFN.scala:107:42, :110:60] wire _CIsDominant_T_2 = isMinCAlign | _CIsDominant_T_1; // @[MulAddRecFN.scala:108:50, :110:{39,60}] assign CIsDominant = _CIsDominant_T & _CIsDominant_T_2; // @[MulAddRecFN.scala:110:{9,23,39}] assign io_toPostMul_CIsDominant_0 = CIsDominant; // @[MulAddRecFN.scala:71:7, :110:23] wire _CAlignDist_T = posNatCAlignDist < 10'h4A; // @[MulAddRecFN.scala:107:42, :114:34] wire [6:0] _CAlignDist_T_1 = posNatCAlignDist[6:0]; // @[MulAddRecFN.scala:107:42, :115:33] wire [6:0] _CAlignDist_T_2 = _CAlignDist_T ? _CAlignDist_T_1 : 7'h4A; // @[MulAddRecFN.scala:114:{16,34}, :115:33] wire [6:0] CAlignDist = isMinCAlign ? 7'h0 : _CAlignDist_T_2; // @[MulAddRecFN.scala:108:50, :112:12, :114:16] wire [24:0] _mainAlignedSigC_T = ~rawC_sig; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] _mainAlignedSigC_T_1 = doSubMags ? _mainAlignedSigC_T : rawC_sig; // @[rawFloatFromRecFN.scala:55:23] wire [52:0] _mainAlignedSigC_T_2 = {53{doSubMags}}; // @[MulAddRecFN.scala:102:42, :120:53] wire [77:0] _mainAlignedSigC_T_3 = {_mainAlignedSigC_T_1, _mainAlignedSigC_T_2}; // @[MulAddRecFN.scala:120:{13,46,53}] wire [77:0] _mainAlignedSigC_T_4 = _mainAlignedSigC_T_3; // @[MulAddRecFN.scala:120:{46,94}] wire [77:0] mainAlignedSigC = $signed($signed(_mainAlignedSigC_T_4) >>> CAlignDist); // @[MulAddRecFN.scala:112:12, :120:{94,100}] wire [26:0] _reduced4CExtra_T = {rawC_sig, 2'h0}; // @[rawFloatFromRecFN.scala:55:23] wire _reduced4CExtra_reducedVec_0_T_1; // @[primitives.scala:120:54] wire _reduced4CExtra_reducedVec_1_T_1; // @[primitives.scala:120:54] wire _reduced4CExtra_reducedVec_2_T_1; // @[primitives.scala:120:54] wire _reduced4CExtra_reducedVec_3_T_1; // @[primitives.scala:120:54] wire _reduced4CExtra_reducedVec_4_T_1; // @[primitives.scala:120:54] wire _reduced4CExtra_reducedVec_5_T_1; // @[primitives.scala:120:54] wire _reduced4CExtra_reducedVec_6_T_1; // @[primitives.scala:123:57] wire reduced4CExtra_reducedVec_0; // @[primitives.scala:118:30] wire reduced4CExtra_reducedVec_1; // @[primitives.scala:118:30] wire reduced4CExtra_reducedVec_2; // @[primitives.scala:118:30] wire reduced4CExtra_reducedVec_3; // @[primitives.scala:118:30] wire reduced4CExtra_reducedVec_4; // @[primitives.scala:118:30] wire reduced4CExtra_reducedVec_5; // @[primitives.scala:118:30] wire reduced4CExtra_reducedVec_6; // @[primitives.scala:118:30] wire [3:0] _reduced4CExtra_reducedVec_0_T = _reduced4CExtra_T[3:0]; // @[primitives.scala:120:33] assign _reduced4CExtra_reducedVec_0_T_1 = |_reduced4CExtra_reducedVec_0_T; // @[primitives.scala:120:{33,54}] assign reduced4CExtra_reducedVec_0 = _reduced4CExtra_reducedVec_0_T_1; // @[primitives.scala:118:30, :120:54] wire [3:0] _reduced4CExtra_reducedVec_1_T = _reduced4CExtra_T[7:4]; // @[primitives.scala:120:33] assign _reduced4CExtra_reducedVec_1_T_1 = |_reduced4CExtra_reducedVec_1_T; // @[primitives.scala:120:{33,54}] assign reduced4CExtra_reducedVec_1 = _reduced4CExtra_reducedVec_1_T_1; // @[primitives.scala:118:30, :120:54] wire [3:0] _reduced4CExtra_reducedVec_2_T = _reduced4CExtra_T[11:8]; // @[primitives.scala:120:33] assign _reduced4CExtra_reducedVec_2_T_1 = |_reduced4CExtra_reducedVec_2_T; // @[primitives.scala:120:{33,54}] assign reduced4CExtra_reducedVec_2 = _reduced4CExtra_reducedVec_2_T_1; // @[primitives.scala:118:30, :120:54] wire [3:0] _reduced4CExtra_reducedVec_3_T = _reduced4CExtra_T[15:12]; // @[primitives.scala:120:33] assign _reduced4CExtra_reducedVec_3_T_1 = |_reduced4CExtra_reducedVec_3_T; // @[primitives.scala:120:{33,54}] assign reduced4CExtra_reducedVec_3 = _reduced4CExtra_reducedVec_3_T_1; // @[primitives.scala:118:30, :120:54] wire [3:0] _reduced4CExtra_reducedVec_4_T = _reduced4CExtra_T[19:16]; // @[primitives.scala:120:33] assign _reduced4CExtra_reducedVec_4_T_1 = |_reduced4CExtra_reducedVec_4_T; // @[primitives.scala:120:{33,54}] assign reduced4CExtra_reducedVec_4 = _reduced4CExtra_reducedVec_4_T_1; // @[primitives.scala:118:30, :120:54] wire [3:0] _reduced4CExtra_reducedVec_5_T = _reduced4CExtra_T[23:20]; // @[primitives.scala:120:33] assign _reduced4CExtra_reducedVec_5_T_1 = |_reduced4CExtra_reducedVec_5_T; // @[primitives.scala:120:{33,54}] assign reduced4CExtra_reducedVec_5 = _reduced4CExtra_reducedVec_5_T_1; // @[primitives.scala:118:30, :120:54] wire [2:0] _reduced4CExtra_reducedVec_6_T = _reduced4CExtra_T[26:24]; // @[primitives.scala:123:15] assign _reduced4CExtra_reducedVec_6_T_1 = |_reduced4CExtra_reducedVec_6_T; // @[primitives.scala:123:{15,57}] assign reduced4CExtra_reducedVec_6 = _reduced4CExtra_reducedVec_6_T_1; // @[primitives.scala:118:30, :123:57] wire [1:0] reduced4CExtra_lo_hi = {reduced4CExtra_reducedVec_2, reduced4CExtra_reducedVec_1}; // @[primitives.scala:118:30, :124:20] wire [2:0] reduced4CExtra_lo = {reduced4CExtra_lo_hi, reduced4CExtra_reducedVec_0}; // @[primitives.scala:118:30, :124:20] wire [1:0] reduced4CExtra_hi_lo = {reduced4CExtra_reducedVec_4, reduced4CExtra_reducedVec_3}; // @[primitives.scala:118:30, :124:20] wire [1:0] reduced4CExtra_hi_hi = {reduced4CExtra_reducedVec_6, reduced4CExtra_reducedVec_5}; // @[primitives.scala:118:30, :124:20] wire [3:0] reduced4CExtra_hi = {reduced4CExtra_hi_hi, reduced4CExtra_hi_lo}; // @[primitives.scala:124:20] wire [6:0] _reduced4CExtra_T_1 = {reduced4CExtra_hi, reduced4CExtra_lo}; // @[primitives.scala:124:20] wire [4:0] _reduced4CExtra_T_2 = CAlignDist[6:2]; // @[MulAddRecFN.scala:112:12, :124:28] wire [32:0] reduced4CExtra_shift = $signed(33'sh100000000 >>> _reduced4CExtra_T_2); // @[primitives.scala:76:56] wire [5:0] _reduced4CExtra_T_3 = reduced4CExtra_shift[19:14]; // @[primitives.scala:76:56, :78:22] wire [3:0] _reduced4CExtra_T_4 = _reduced4CExtra_T_3[3:0]; // @[primitives.scala:77:20, :78:22] wire [1:0] _reduced4CExtra_T_5 = _reduced4CExtra_T_4[1:0]; // @[primitives.scala:77:20] wire _reduced4CExtra_T_6 = _reduced4CExtra_T_5[0]; // @[primitives.scala:77:20] wire _reduced4CExtra_T_7 = _reduced4CExtra_T_5[1]; // @[primitives.scala:77:20] wire [1:0] _reduced4CExtra_T_8 = {_reduced4CExtra_T_6, _reduced4CExtra_T_7}; // @[primitives.scala:77:20] wire [1:0] _reduced4CExtra_T_9 = _reduced4CExtra_T_4[3:2]; // @[primitives.scala:77:20] wire _reduced4CExtra_T_10 = _reduced4CExtra_T_9[0]; // @[primitives.scala:77:20] wire _reduced4CExtra_T_11 = _reduced4CExtra_T_9[1]; // @[primitives.scala:77:20] wire [1:0] _reduced4CExtra_T_12 = {_reduced4CExtra_T_10, _reduced4CExtra_T_11}; // @[primitives.scala:77:20] wire [3:0] _reduced4CExtra_T_13 = {_reduced4CExtra_T_8, _reduced4CExtra_T_12}; // @[primitives.scala:77:20] wire [1:0] _reduced4CExtra_T_14 = _reduced4CExtra_T_3[5:4]; // @[primitives.scala:77:20, :78:22] wire _reduced4CExtra_T_15 = _reduced4CExtra_T_14[0]; // @[primitives.scala:77:20] wire _reduced4CExtra_T_16 = _reduced4CExtra_T_14[1]; // @[primitives.scala:77:20] wire [1:0] _reduced4CExtra_T_17 = {_reduced4CExtra_T_15, _reduced4CExtra_T_16}; // @[primitives.scala:77:20] wire [5:0] _reduced4CExtra_T_18 = {_reduced4CExtra_T_13, _reduced4CExtra_T_17}; // @[primitives.scala:77:20] wire [6:0] _reduced4CExtra_T_19 = {1'h0, _reduced4CExtra_T_1[5:0] & _reduced4CExtra_T_18}; // @[primitives.scala:77:20, :124:20] wire reduced4CExtra = |_reduced4CExtra_T_19; // @[MulAddRecFN.scala:122:68, :130:11] wire [74:0] _alignedSigC_T = mainAlignedSigC[77:3]; // @[MulAddRecFN.scala:120:100, :132:28] wire [74:0] alignedSigC_hi = _alignedSigC_T; // @[MulAddRecFN.scala:132:{12,28}] wire [2:0] _alignedSigC_T_1 = mainAlignedSigC[2:0]; // @[MulAddRecFN.scala:120:100, :134:32] wire [2:0] _alignedSigC_T_5 = mainAlignedSigC[2:0]; // @[MulAddRecFN.scala:120:100, :134:32, :135:32] wire _alignedSigC_T_2 = &_alignedSigC_T_1; // @[MulAddRecFN.scala:134:{32,39}] wire _alignedSigC_T_3 = ~reduced4CExtra; // @[MulAddRecFN.scala:130:11, :134:47] wire _alignedSigC_T_4 = _alignedSigC_T_2 & _alignedSigC_T_3; // @[MulAddRecFN.scala:134:{39,44,47}] wire _alignedSigC_T_6 = |_alignedSigC_T_5; // @[MulAddRecFN.scala:135:{32,39}] wire _alignedSigC_T_7 = _alignedSigC_T_6 | reduced4CExtra; // @[MulAddRecFN.scala:130:11, :135:{39,44}] wire _alignedSigC_T_8 = doSubMags ? _alignedSigC_T_4 : _alignedSigC_T_7; // @[MulAddRecFN.scala:102:42, :133:16, :134:44, :135:44] wire [75:0] alignedSigC = {alignedSigC_hi, _alignedSigC_T_8}; // @[MulAddRecFN.scala:132:12, :133:16] assign io_mulAddA_0 = rawA_sig[23:0]; // @[rawFloatFromRecFN.scala:55:23] assign _io_mulAddC_T = alignedSigC[48:1]; // @[MulAddRecFN.scala:132:12, :143:30] assign io_mulAddC_0 = _io_mulAddC_T; // @[MulAddRecFN.scala:71:7, :143:30] wire _io_toPostMul_isSigNaNAny_T = rawA_sig[22]; // @[rawFloatFromRecFN.scala:55:23] wire _io_toPostMul_isSigNaNAny_T_1 = ~_io_toPostMul_isSigNaNAny_T; // @[common.scala:82:{49,56}] wire _io_toPostMul_isSigNaNAny_T_2 = rawA_isNaN & _io_toPostMul_isSigNaNAny_T_1; // @[rawFloatFromRecFN.scala:55:23] wire _io_toPostMul_isSigNaNAny_T_6 = _io_toPostMul_isSigNaNAny_T_2; // @[common.scala:82:46] wire _io_toPostMul_isSigNaNAny_T_7 = rawC_sig[22]; // @[rawFloatFromRecFN.scala:55:23] wire _io_toPostMul_isSigNaNAny_T_8 = ~_io_toPostMul_isSigNaNAny_T_7; // @[common.scala:82:{49,56}] wire _io_toPostMul_isSigNaNAny_T_9 = rawC_isNaN & _io_toPostMul_isSigNaNAny_T_8; // @[rawFloatFromRecFN.scala:55:23] assign _io_toPostMul_isSigNaNAny_T_10 = _io_toPostMul_isSigNaNAny_T_6 | _io_toPostMul_isSigNaNAny_T_9; // @[common.scala:82:46] assign io_toPostMul_isSigNaNAny_0 = _io_toPostMul_isSigNaNAny_T_10; // @[MulAddRecFN.scala:71:7, :146:58] assign io_toPostMul_isNaNAOrB_0 = _io_toPostMul_isNaNAOrB_T; // @[MulAddRecFN.scala:71:7, :148:42] wire [11:0] _io_toPostMul_sExpSum_T = _GEN - 12'h18; // @[MulAddRecFN.scala:106:42, :158:53] wire [10:0] _io_toPostMul_sExpSum_T_1 = _io_toPostMul_sExpSum_T[10:0]; // @[MulAddRecFN.scala:158:53] wire [10:0] _io_toPostMul_sExpSum_T_2 = _io_toPostMul_sExpSum_T_1; // @[MulAddRecFN.scala:158:53] wire [10:0] _io_toPostMul_sExpSum_T_3 = CIsDominant ? {rawC_sExp[9], rawC_sExp} : _io_toPostMul_sExpSum_T_2; // @[rawFloatFromRecFN.scala:55:23] assign io_toPostMul_sExpSum_0 = _io_toPostMul_sExpSum_T_3[9:0]; // @[MulAddRecFN.scala:71:7, :157:28, :158:12] assign _io_toPostMul_CDom_CAlignDist_T = CAlignDist[4:0]; // @[MulAddRecFN.scala:112:12, :161:47] assign io_toPostMul_CDom_CAlignDist_0 = _io_toPostMul_CDom_CAlignDist_T; // @[MulAddRecFN.scala:71:7, :161:47] assign _io_toPostMul_highAlignedSigC_T = alignedSigC[74:49]; // @[MulAddRecFN.scala:132:12, :163:20] assign io_toPostMul_highAlignedSigC_0 = _io_toPostMul_highAlignedSigC_T; // @[MulAddRecFN.scala:71:7, :163:20] assign _io_toPostMul_bit0AlignedSigC_T = alignedSigC[0]; // @[MulAddRecFN.scala:132:12, :164:48] assign io_toPostMul_bit0AlignedSigC_0 = _io_toPostMul_bit0AlignedSigC_T; // @[MulAddRecFN.scala:71:7, :164:48] assign io_mulAddA = io_mulAddA_0; // @[MulAddRecFN.scala:71:7] assign io_mulAddC = io_mulAddC_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_isSigNaNAny = io_toPostMul_isSigNaNAny_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_isNaNAOrB = io_toPostMul_isNaNAOrB_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_isInfA = io_toPostMul_isInfA_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_isZeroA = io_toPostMul_isZeroA_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_signProd = io_toPostMul_signProd_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_isNaNC = io_toPostMul_isNaNC_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_isInfC = io_toPostMul_isInfC_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_isZeroC = io_toPostMul_isZeroC_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_sExpSum = io_toPostMul_sExpSum_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_doSubMags = io_toPostMul_doSubMags_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_CIsDominant = io_toPostMul_CIsDominant_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_CDom_CAlignDist = io_toPostMul_CDom_CAlignDist_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_highAlignedSigC = io_toPostMul_highAlignedSigC_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_bit0AlignedSigC = io_toPostMul_bit0AlignedSigC_0; // @[MulAddRecFN.scala:71:7] endmodule

Generate the Verilog code corresponding to the following Chisel files. File HellaQueue.scala: // See LICENSE.Berkeley for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ class HellaFlowQueue[T <: Data](val entries: Int)(data: => T) extends Module { val io = IO(new QueueIO(data, entries)) require(entries > 1) val do_flow = Wire(Bool()) val do_enq = io.enq.fire && !do_flow val do_deq = io.deq.fire && !do_flow val maybe_full = RegInit(false.B) val enq_ptr = Counter(do_enq, entries)._1 val (deq_ptr, deq_done) = Counter(do_deq, entries) when (do_enq =/= do_deq) { maybe_full := do_enq } val ptr_match = enq_ptr === deq_ptr val empty = ptr_match && !maybe_full val full = ptr_match && maybe_full val atLeastTwo = full || enq_ptr - deq_ptr >= 2.U do_flow := empty && io.deq.ready val ram = SyncReadMem(entries, data) when (do_enq) { ram.write(enq_ptr, io.enq.bits) } // BUG! does not hold the output of the SRAM when !ready // ... However, HellaQueue is correct due to the pipe stage val ren = io.deq.ready && (atLeastTwo || !io.deq.valid && !empty) val raddr = Mux(io.deq.valid, Mux(deq_done, 0.U, deq_ptr + 1.U), deq_ptr) val ram_out_valid = RegNext(ren) io.deq.valid := Mux(empty, io.enq.valid, ram_out_valid) io.enq.ready := !full io.deq.bits := Mux(empty, io.enq.bits, ram.read(raddr, ren)) // Count was never correctly set. To keep the same behavior across chisel3 upgrade, we are explicitly setting it to DontCare io.count := DontCare } class HellaQueue[T <: Data](val entries: Int)(data: => T) extends Module { val io = IO(new QueueIO(data, entries)) val fq = Module(new HellaFlowQueue(entries)(data)) fq.io.enq <> io.enq io.deq <> Queue(fq.io.deq, 1, pipe = true) io.count := fq.io.count } object HellaQueue { def apply[T <: Data](enq: DecoupledIO[T], entries: Int) = { val q = Module((new HellaQueue(entries)) { enq.bits }) q.io.enq.valid := enq.valid // not using <> so that override is allowed q.io.enq.bits := enq.bits enq.ready := q.io.enq.ready q.io.deq } }

module HellaQueue_1( // @[HellaQueue.scala:44:7] input clock, // @[HellaQueue.scala:44:7] input reset, // @[HellaQueue.scala:44:7] output io_enq_ready, // @[HellaQueue.scala:45:14] input io_enq_valid, // @[HellaQueue.scala:45:14] input [63:0] io_enq_bits, // @[HellaQueue.scala:45:14] input io_deq_ready, // @[HellaQueue.scala:45:14] output io_deq_valid, // @[HellaQueue.scala:45:14] output [63:0] io_deq_bits // @[HellaQueue.scala:45:14] ); wire _io_deq_q_io_enq_ready; // @[Decoupled.scala:362:21] wire _fq_io_deq_valid; // @[HellaQueue.scala:47:18] wire [63:0] _fq_io_deq_bits; // @[HellaQueue.scala:47:18] wire io_enq_valid_0 = io_enq_valid; // @[HellaQueue.scala:44:7] wire [63:0] io_enq_bits_0 = io_enq_bits; // @[HellaQueue.scala:44:7] wire io_deq_ready_0 = io_deq_ready; // @[HellaQueue.scala:44:7] wire [6:0] io_count = 7'h0; // @[HellaQueue.scala:44:7, :45:14, :47:18] wire io_enq_ready_0; // @[HellaQueue.scala:44:7] wire io_deq_valid_0; // @[HellaQueue.scala:44:7] wire [63:0] io_deq_bits_0; // @[HellaQueue.scala:44:7] HellaFlowQueue_1 fq ( // @[HellaQueue.scala:47:18] .clock (clock), .reset (reset), .io_enq_ready (io_enq_ready_0), .io_enq_valid (io_enq_valid_0), // @[HellaQueue.scala:44:7] .io_enq_bits (io_enq_bits_0), // @[HellaQueue.scala:44:7] .io_deq_ready (_io_deq_q_io_enq_ready), // @[Decoupled.scala:362:21] .io_deq_valid (_fq_io_deq_valid), .io_deq_bits (_fq_io_deq_bits) ); // @[HellaQueue.scala:47:18] Queue1_UInt64_1 io_deq_q ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (_io_deq_q_io_enq_ready), .io_enq_valid (_fq_io_deq_valid), // @[HellaQueue.scala:47:18] .io_enq_bits (_fq_io_deq_bits), // @[HellaQueue.scala:47:18] .io_deq_ready (io_deq_ready_0), // @[HellaQueue.scala:44:7] .io_deq_valid (io_deq_valid_0), .io_deq_bits (io_deq_bits_0) ); // @[Decoupled.scala:362:21] assign io_enq_ready = io_enq_ready_0; // @[HellaQueue.scala:44:7] assign io_deq_valid = io_deq_valid_0; // @[HellaQueue.scala:44:7] assign io_deq_bits = io_deq_bits_0; // @[HellaQueue.scala:44:7] endmodule

Generate the Verilog code corresponding to the following Chisel files. File ShiftReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ // Similar to the Chisel ShiftRegister but allows the user to suggest a // name to the registers that get instantiated, and // to provide a reset value. object ShiftRegInit { def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T = (0 until n).foldRight(in) { case (i, next) => { val r = RegNext(next, init) name.foreach { na => r.suggestName(s"${na}_${i}") } r } } } /** These wrap behavioral * shift registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * The different types vary in their reset behavior: * AsyncResetShiftReg -- Asynchronously reset register array * A W(width) x D(depth) sized array is constructed from D instantiations of a * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg, * but only used for timing applications */ abstract class AbstractPipelineReg(w: Int = 1) extends Module { val io = IO(new Bundle { val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) } ) } object AbstractPipelineReg { def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = { val chain = Module(gen) name.foreach{ chain.suggestName(_) } chain.io.d := in.asUInt chain.io.q.asTypeOf(in) } } class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) { require(depth > 0, "Depth must be greater than 0.") override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}" val chain = List.tabulate(depth) { i => Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}") } chain.last.io.d := io.d chain.last.io.en := true.B (chain.init zip chain.tail).foreach { case (sink, source) => sink.io.d := source.io.q sink.io.en := true.B } io.q := chain.head.io.q } object AsyncResetShiftReg { def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name) def apply [T <: Data](in: T, depth: Int, name: Option[String]): T = apply(in, depth, 0, name) def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T = apply(in, depth, init.litValue.toInt, name) def apply [T <: Data](in: T, depth: Int, init: T): T = apply (in, depth, init.litValue.toInt, None) } File AsyncQueue.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ case class AsyncQueueParams( depth: Int = 8, sync: Int = 3, safe: Boolean = true, // If safe is true, then effort is made to resynchronize the crossing indices when either side is reset. // This makes it safe/possible to reset one side of the crossing (but not the other) when the queue is empty. narrow: Boolean = false) // If narrow is true then the read mux is moved to the source side of the crossing. // This reduces the number of level shifters in the case where the clock crossing is also a voltage crossing, // at the expense of a combinational path from the sink to the source and back to the sink. { require (depth > 0 && isPow2(depth)) require (sync >= 2) val bits = log2Ceil(depth) val wires = if (narrow) 1 else depth } object AsyncQueueParams { // When there is only one entry, we don't need narrow. def singleton(sync: Int = 3, safe: Boolean = true) = AsyncQueueParams(1, sync, safe, false) } class AsyncBundleSafety extends Bundle { val ridx_valid = Input (Bool()) val widx_valid = Output(Bool()) val source_reset_n = Output(Bool()) val sink_reset_n = Input (Bool()) } class AsyncBundle[T <: Data](private val gen: T, val params: AsyncQueueParams = AsyncQueueParams()) extends Bundle { // Data-path synchronization val mem = Output(Vec(params.wires, gen)) val ridx = Input (UInt((params.bits+1).W)) val widx = Output(UInt((params.bits+1).W)) val index = params.narrow.option(Input(UInt(params.bits.W))) // Signals used to self-stabilize a safe AsyncQueue val safe = params.safe.option(new AsyncBundleSafety) } object GrayCounter { def apply(bits: Int, increment: Bool = true.B, clear: Bool = false.B, name: String = "binary"): UInt = { val incremented = Wire(UInt(bits.W)) val binary = RegNext(next=incremented, init=0.U).suggestName(name) incremented := Mux(clear, 0.U, binary + increment.asUInt) incremented ^ (incremented >> 1) } } class AsyncValidSync(sync: Int, desc: String) extends RawModule { val io = IO(new Bundle { val in = Input(Bool()) val out = Output(Bool()) }) val clock = IO(Input(Clock())) val reset = IO(Input(AsyncReset())) withClockAndReset(clock, reset){ io.out := AsyncResetSynchronizerShiftReg(io.in, sync, Some(desc)) } } class AsyncQueueSource[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module { override def desiredName = s"AsyncQueueSource_${gen.typeName}" val io = IO(new Bundle { // These come from the source domain val enq = Flipped(Decoupled(gen)) // These cross to the sink clock domain val async = new AsyncBundle(gen, params) }) val bits = params.bits val sink_ready = WireInit(true.B) val mem = Reg(Vec(params.depth, gen)) // This does NOT need to be reset at all. val widx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.enq.fire, !sink_ready, "widx_bin")) val ridx = AsyncResetSynchronizerShiftReg(io.async.ridx, params.sync, Some("ridx_gray")) val ready = sink_ready && widx =/= (ridx ^ (params.depth | params.depth >> 1).U) val index = if (bits == 0) 0.U else io.async.widx(bits-1, 0) ^ (io.async.widx(bits, bits) << (bits-1)) when (io.enq.fire) { mem(index) := io.enq.bits } val ready_reg = withReset(reset.asAsyncReset)(RegNext(next=ready, init=false.B).suggestName("ready_reg")) io.enq.ready := ready_reg && sink_ready val widx_reg = withReset(reset.asAsyncReset)(RegNext(next=widx, init=0.U).suggestName("widx_gray")) io.async.widx := widx_reg io.async.index match { case Some(index) => io.async.mem(0) := mem(index) case None => io.async.mem := mem } io.async.safe.foreach { sio => val source_valid_0 = Module(new AsyncValidSync(params.sync, "source_valid_0")) val source_valid_1 = Module(new AsyncValidSync(params.sync, "source_valid_1")) val sink_extend = Module(new AsyncValidSync(params.sync, "sink_extend")) val sink_valid = Module(new AsyncValidSync(params.sync, "sink_valid")) source_valid_0.reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset source_valid_1.reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset sink_extend .reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset sink_valid .reset := reset.asAsyncReset source_valid_0.clock := clock source_valid_1.clock := clock sink_extend .clock := clock sink_valid .clock := clock source_valid_0.io.in := true.B source_valid_1.io.in := source_valid_0.io.out sio.widx_valid := source_valid_1.io.out sink_extend.io.in := sio.ridx_valid sink_valid.io.in := sink_extend.io.out sink_ready := sink_valid.io.out sio.source_reset_n := !reset.asBool // Assert that if there is stuff in the queue, then reset cannot happen // Impossible to write because dequeue can occur on the receiving side, // then reset allowed to happen, but write side cannot know that dequeue // occurred. // TODO: write some sort of sanity check assertion for users // that denote don't reset when there is activity // assert (!(reset || !sio.sink_reset_n) || !io.enq.valid, "Enqueue while sink is reset and AsyncQueueSource is unprotected") // assert (!reset_rise || prev_idx_match.asBool, "Sink reset while AsyncQueueSource not empty") } } class AsyncQueueSink[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module { override def desiredName = s"AsyncQueueSink_${gen.typeName}" val io = IO(new Bundle { // These come from the sink domain val deq = Decoupled(gen) // These cross to the source clock domain val async = Flipped(new AsyncBundle(gen, params)) }) val bits = params.bits val source_ready = WireInit(true.B) val ridx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.deq.fire, !source_ready, "ridx_bin")) val widx = AsyncResetSynchronizerShiftReg(io.async.widx, params.sync, Some("widx_gray")) val valid = source_ready && ridx =/= widx // The mux is safe because timing analysis ensures ridx has reached the register // On an ASIC, changes to the unread location cannot affect the selected value // On an FPGA, only one input changes at a time => mem updates don't cause glitches // The register only latches when the selected valued is not being written val index = if (bits == 0) 0.U else ridx(bits-1, 0) ^ (ridx(bits, bits) << (bits-1)) io.async.index.foreach { _ := index } // This register does not NEED to be reset, as its contents will not // be considered unless the asynchronously reset deq valid register is set. // It is possible that bits latches when the source domain is reset / has power cut // This is safe, because isolation gates brought mem low before the zeroed widx reached us val deq_bits_nxt = io.async.mem(if (params.narrow) 0.U else index) io.deq.bits := ClockCrossingReg(deq_bits_nxt, en = valid, doInit = false, name = Some("deq_bits_reg")) val valid_reg = withReset(reset.asAsyncReset)(RegNext(next=valid, init=false.B).suggestName("valid_reg")) io.deq.valid := valid_reg && source_ready val ridx_reg = withReset(reset.asAsyncReset)(RegNext(next=ridx, init=0.U).suggestName("ridx_gray")) io.async.ridx := ridx_reg io.async.safe.foreach { sio => val sink_valid_0 = Module(new AsyncValidSync(params.sync, "sink_valid_0")) val sink_valid_1 = Module(new AsyncValidSync(params.sync, "sink_valid_1")) val source_extend = Module(new AsyncValidSync(params.sync, "source_extend")) val source_valid = Module(new AsyncValidSync(params.sync, "source_valid")) sink_valid_0 .reset := (reset.asBool || !sio.source_reset_n).asAsyncReset sink_valid_1 .reset := (reset.asBool || !sio.source_reset_n).asAsyncReset source_extend.reset := (reset.asBool || !sio.source_reset_n).asAsyncReset source_valid .reset := reset.asAsyncReset sink_valid_0 .clock := clock sink_valid_1 .clock := clock source_extend.clock := clock source_valid .clock := clock sink_valid_0.io.in := true.B sink_valid_1.io.in := sink_valid_0.io.out sio.ridx_valid := sink_valid_1.io.out source_extend.io.in := sio.widx_valid source_valid.io.in := source_extend.io.out source_ready := source_valid.io.out sio.sink_reset_n := !reset.asBool // TODO: write some sort of sanity check assertion for users // that denote don't reset when there is activity // // val reset_and_extend = !source_ready || !sio.source_reset_n || reset.asBool // val reset_and_extend_prev = RegNext(reset_and_extend, true.B) // val reset_rise = !reset_and_extend_prev && reset_and_extend // val prev_idx_match = AsyncResetReg(updateData=(io.async.widx===io.async.ridx), resetData=0) // assert (!reset_rise || prev_idx_match.asBool, "Source reset while AsyncQueueSink not empty") } } object FromAsyncBundle { // Sometimes it makes sense for the sink to have different sync than the source def apply[T <: Data](x: AsyncBundle[T]): DecoupledIO[T] = apply(x, x.params.sync) def apply[T <: Data](x: AsyncBundle[T], sync: Int): DecoupledIO[T] = { val sink = Module(new AsyncQueueSink(chiselTypeOf(x.mem(0)), x.params.copy(sync = sync))) sink.io.async <> x sink.io.deq } } object ToAsyncBundle { def apply[T <: Data](x: ReadyValidIO[T], params: AsyncQueueParams = AsyncQueueParams()): AsyncBundle[T] = { val source = Module(new AsyncQueueSource(chiselTypeOf(x.bits), params)) source.io.enq <> x source.io.async } } class AsyncQueue[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Crossing[T] { val io = IO(new CrossingIO(gen)) val source = withClockAndReset(io.enq_clock, io.enq_reset) { Module(new AsyncQueueSource(gen, params)) } val sink = withClockAndReset(io.deq_clock, io.deq_reset) { Module(new AsyncQueueSink (gen, params)) } source.io.enq <> io.enq io.deq <> sink.io.deq sink.io.async <> source.io.async }

module AsyncValidSync_115( // @[AsyncQueue.scala:58:7] input io_in, // @[AsyncQueue.scala:59:14] output io_out, // @[AsyncQueue.scala:59:14] input clock, // @[AsyncQueue.scala:63:17] input reset // @[AsyncQueue.scala:64:17] ); wire io_in_0 = io_in; // @[AsyncQueue.scala:58:7] wire _io_out_WIRE; // @[ShiftReg.scala:48:24] wire io_out_0; // @[AsyncQueue.scala:58:7] assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24] AsyncResetSynchronizerShiftReg_w1_d3_i0_130 io_out_sink_valid ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (reset), .io_d (io_in_0), // @[AsyncQueue.scala:58:7] .io_q (_io_out_WIRE) ); // @[ShiftReg.scala:45:23] assign io_out = io_out_0; // @[AsyncQueue.scala:58:7] endmodule

Generate the Verilog code corresponding to the following Chisel files. File Buffer.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.diplomacy.BufferParams class TLBufferNode ( a: BufferParams, b: BufferParams, c: BufferParams, d: BufferParams, e: BufferParams)(implicit valName: ValName) extends TLAdapterNode( clientFn = { p => p.v1copy(minLatency = p.minLatency + b.latency + c.latency) }, managerFn = { p => p.v1copy(minLatency = p.minLatency + a.latency + d.latency) } ) { override lazy val nodedebugstring = s"a:${a.toString}, b:${b.toString}, c:${c.toString}, d:${d.toString}, e:${e.toString}" override def circuitIdentity = List(a,b,c,d,e).forall(_ == BufferParams.none) } class TLBuffer( a: BufferParams, b: BufferParams, c: BufferParams, d: BufferParams, e: BufferParams)(implicit p: Parameters) extends LazyModule { def this(ace: BufferParams, bd: BufferParams)(implicit p: Parameters) = this(ace, bd, ace, bd, ace) def this(abcde: BufferParams)(implicit p: Parameters) = this(abcde, abcde) def this()(implicit p: Parameters) = this(BufferParams.default) val node = new TLBufferNode(a, b, c, d, e) lazy val module = new Impl class Impl extends LazyModuleImp(this) { def headBundle = node.out.head._2.bundle override def desiredName = (Seq("TLBuffer") ++ node.out.headOption.map(_._2.bundle.shortName)).mkString("_") (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out.a <> a(in .a) in .d <> d(out.d) if (edgeOut.manager.anySupportAcquireB && edgeOut.client.anySupportProbe) { in .b <> b(out.b) out.c <> c(in .c) out.e <> e(in .e) } else { in.b.valid := false.B in.c.ready := true.B in.e.ready := true.B out.b.ready := true.B out.c.valid := false.B out.e.valid := false.B } } } } object TLBuffer { def apply() (implicit p: Parameters): TLNode = apply(BufferParams.default) def apply(abcde: BufferParams) (implicit p: Parameters): TLNode = apply(abcde, abcde) def apply(ace: BufferParams, bd: BufferParams)(implicit p: Parameters): TLNode = apply(ace, bd, ace, bd, ace) def apply( a: BufferParams, b: BufferParams, c: BufferParams, d: BufferParams, e: BufferParams)(implicit p: Parameters): TLNode = { val buffer = LazyModule(new TLBuffer(a, b, c, d, e)) buffer.node } def chain(depth: Int, name: Option[String] = None)(implicit p: Parameters): Seq[TLNode] = { val buffers = Seq.fill(depth) { LazyModule(new TLBuffer()) } name.foreach { n => buffers.zipWithIndex.foreach { case (b, i) => b.suggestName(s"${n}_${i}") } } buffers.map(_.node) } def chainNode(depth: Int, name: Option[String] = None)(implicit p: Parameters): TLNode = { chain(depth, name) .reduceLeftOption(_ :*=* _) .getOrElse(TLNameNode("no_buffer")) } } File Nodes.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.nodes._ import freechips.rocketchip.util.{AsyncQueueParams,RationalDirection} case object TLMonitorBuilder extends Field[TLMonitorArgs => TLMonitorBase](args => new TLMonitor(args)) object TLImp extends NodeImp[TLMasterPortParameters, TLSlavePortParameters, TLEdgeOut, TLEdgeIn, TLBundle] { def edgeO(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeOut(pd, pu, p, sourceInfo) def edgeI(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeIn (pd, pu, p, sourceInfo) def bundleO(eo: TLEdgeOut) = TLBundle(eo.bundle) def bundleI(ei: TLEdgeIn) = TLBundle(ei.bundle) def render(ei: TLEdgeIn) = RenderedEdge(colour = "#000000" /* black */, label = (ei.manager.beatBytes * 8).toString) override def monitor(bundle: TLBundle, edge: TLEdgeIn): Unit = { val monitor = Module(edge.params(TLMonitorBuilder)(TLMonitorArgs(edge))) monitor.io.in := bundle } override def mixO(pd: TLMasterPortParameters, node: OutwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLMasterPortParameters = pd.v1copy(clients = pd.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }) override def mixI(pu: TLSlavePortParameters, node: InwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLSlavePortParameters = pu.v1copy(managers = pu.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }) } trait TLFormatNode extends FormatNode[TLEdgeIn, TLEdgeOut] case class TLClientNode(portParams: Seq[TLMasterPortParameters])(implicit valName: ValName) extends SourceNode(TLImp)(portParams) with TLFormatNode case class TLManagerNode(portParams: Seq[TLSlavePortParameters])(implicit valName: ValName) extends SinkNode(TLImp)(portParams) with TLFormatNode case class TLAdapterNode( clientFn: TLMasterPortParameters => TLMasterPortParameters = { s => s }, managerFn: TLSlavePortParameters => TLSlavePortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLImp)(clientFn, managerFn) with TLFormatNode case class TLJunctionNode( clientFn: Seq[TLMasterPortParameters] => Seq[TLMasterPortParameters], managerFn: Seq[TLSlavePortParameters] => Seq[TLSlavePortParameters])( implicit valName: ValName) extends JunctionNode(TLImp)(clientFn, managerFn) with TLFormatNode case class TLIdentityNode()(implicit valName: ValName) extends IdentityNode(TLImp)() with TLFormatNode object TLNameNode { def apply(name: ValName) = TLIdentityNode()(name) def apply(name: Option[String]): TLIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLIdentityNode = apply(Some(name)) } case class TLEphemeralNode()(implicit valName: ValName) extends EphemeralNode(TLImp)() object TLTempNode { def apply(): TLEphemeralNode = TLEphemeralNode()(ValName("temp")) } case class TLNexusNode( clientFn: Seq[TLMasterPortParameters] => TLMasterPortParameters, managerFn: Seq[TLSlavePortParameters] => TLSlavePortParameters)( implicit valName: ValName) extends NexusNode(TLImp)(clientFn, managerFn) with TLFormatNode abstract class TLCustomNode(implicit valName: ValName) extends CustomNode(TLImp) with TLFormatNode // Asynchronous crossings trait TLAsyncFormatNode extends FormatNode[TLAsyncEdgeParameters, TLAsyncEdgeParameters] object TLAsyncImp extends SimpleNodeImp[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncEdgeParameters, TLAsyncBundle] { def edge(pd: TLAsyncClientPortParameters, pu: TLAsyncManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLAsyncEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLAsyncEdgeParameters) = new TLAsyncBundle(e.bundle) def render(e: TLAsyncEdgeParameters) = RenderedEdge(colour = "#ff0000" /* red */, label = e.manager.async.depth.toString) override def mixO(pd: TLAsyncClientPortParameters, node: OutwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLAsyncManagerPortParameters, node: InwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLAsyncAdapterNode( clientFn: TLAsyncClientPortParameters => TLAsyncClientPortParameters = { s => s }, managerFn: TLAsyncManagerPortParameters => TLAsyncManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLAsyncImp)(clientFn, managerFn) with TLAsyncFormatNode case class TLAsyncIdentityNode()(implicit valName: ValName) extends IdentityNode(TLAsyncImp)() with TLAsyncFormatNode object TLAsyncNameNode { def apply(name: ValName) = TLAsyncIdentityNode()(name) def apply(name: Option[String]): TLAsyncIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLAsyncIdentityNode = apply(Some(name)) } case class TLAsyncSourceNode(sync: Option[Int])(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLAsyncImp)( dFn = { p => TLAsyncClientPortParameters(p) }, uFn = { p => p.base.v1copy(minLatency = p.base.minLatency + sync.getOrElse(p.async.sync)) }) with FormatNode[TLEdgeIn, TLAsyncEdgeParameters] // discard cycles in other clock domain case class TLAsyncSinkNode(async: AsyncQueueParams)(implicit valName: ValName) extends MixedAdapterNode(TLAsyncImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = p.base.minLatency + async.sync) }, uFn = { p => TLAsyncManagerPortParameters(async, p) }) with FormatNode[TLAsyncEdgeParameters, TLEdgeOut] // Rationally related crossings trait TLRationalFormatNode extends FormatNode[TLRationalEdgeParameters, TLRationalEdgeParameters] object TLRationalImp extends SimpleNodeImp[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalEdgeParameters, TLRationalBundle] { def edge(pd: TLRationalClientPortParameters, pu: TLRationalManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLRationalEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLRationalEdgeParameters) = new TLRationalBundle(e.bundle) def render(e: TLRationalEdgeParameters) = RenderedEdge(colour = "#00ff00" /* green */) override def mixO(pd: TLRationalClientPortParameters, node: OutwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLRationalManagerPortParameters, node: InwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLRationalAdapterNode( clientFn: TLRationalClientPortParameters => TLRationalClientPortParameters = { s => s }, managerFn: TLRationalManagerPortParameters => TLRationalManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLRationalImp)(clientFn, managerFn) with TLRationalFormatNode case class TLRationalIdentityNode()(implicit valName: ValName) extends IdentityNode(TLRationalImp)() with TLRationalFormatNode object TLRationalNameNode { def apply(name: ValName) = TLRationalIdentityNode()(name) def apply(name: Option[String]): TLRationalIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLRationalIdentityNode = apply(Some(name)) } case class TLRationalSourceNode()(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLRationalImp)( dFn = { p => TLRationalClientPortParameters(p) }, uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLRationalEdgeParameters] // discard cycles from other clock domain case class TLRationalSinkNode(direction: RationalDirection)(implicit valName: ValName) extends MixedAdapterNode(TLRationalImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = 1) }, uFn = { p => TLRationalManagerPortParameters(direction, p) }) with FormatNode[TLRationalEdgeParameters, TLEdgeOut] // Credited version of TileLink channels trait TLCreditedFormatNode extends FormatNode[TLCreditedEdgeParameters, TLCreditedEdgeParameters] object TLCreditedImp extends SimpleNodeImp[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedEdgeParameters, TLCreditedBundle] { def edge(pd: TLCreditedClientPortParameters, pu: TLCreditedManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLCreditedEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLCreditedEdgeParameters) = new TLCreditedBundle(e.bundle) def render(e: TLCreditedEdgeParameters) = RenderedEdge(colour = "#ffff00" /* yellow */, e.delay.toString) override def mixO(pd: TLCreditedClientPortParameters, node: OutwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLCreditedManagerPortParameters, node: InwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLCreditedAdapterNode( clientFn: TLCreditedClientPortParameters => TLCreditedClientPortParameters = { s => s }, managerFn: TLCreditedManagerPortParameters => TLCreditedManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLCreditedImp)(clientFn, managerFn) with TLCreditedFormatNode case class TLCreditedIdentityNode()(implicit valName: ValName) extends IdentityNode(TLCreditedImp)() with TLCreditedFormatNode object TLCreditedNameNode { def apply(name: ValName) = TLCreditedIdentityNode()(name) def apply(name: Option[String]): TLCreditedIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLCreditedIdentityNode = apply(Some(name)) } case class TLCreditedSourceNode(delay: TLCreditedDelay)(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLCreditedImp)( dFn = { p => TLCreditedClientPortParameters(delay, p) }, uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLCreditedEdgeParameters] // discard cycles from other clock domain case class TLCreditedSinkNode(delay: TLCreditedDelay)(implicit valName: ValName) extends MixedAdapterNode(TLCreditedImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = 1) }, uFn = { p => TLCreditedManagerPortParameters(delay, p) }) with FormatNode[TLCreditedEdgeParameters, TLEdgeOut] File LazyModuleImp.scala: package org.chipsalliance.diplomacy.lazymodule import chisel3.{withClockAndReset, Module, RawModule, Reset, _} import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo} import firrtl.passes.InlineAnnotation import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.nodes.Dangle import scala.collection.immutable.SortedMap /** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]]. * * This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy. */ sealed trait LazyModuleImpLike extends RawModule { /** [[LazyModule]] that contains this instance. */ val wrapper: LazyModule /** IOs that will be automatically "punched" for this instance. */ val auto: AutoBundle /** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */ protected[diplomacy] val dangles: Seq[Dangle] // [[wrapper.module]] had better not be accessed while LazyModules are still being built! require( LazyModule.scope.isEmpty, s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}" ) /** Set module name. Defaults to the containing LazyModule's desiredName. */ override def desiredName: String = wrapper.desiredName suggestName(wrapper.suggestedName) /** [[Parameters]] for chisel [[Module]]s. */ implicit val p: Parameters = wrapper.p /** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and * submodules. */ protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = { // 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]], // 2. return [[Dangle]]s from each module. val childDangles = wrapper.children.reverse.flatMap { c => implicit val sourceInfo: SourceInfo = c.info c.cloneProto.map { cp => // If the child is a clone, then recursively set cloneProto of its children as well def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = { require(bases.size == clones.size) (bases.zip(clones)).map { case (l, r) => require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}") l.cloneProto = Some(r) assignCloneProtos(l.children, r.children) } } assignCloneProtos(c.children, cp.children) // Clone the child module as a record, and get its [[AutoBundle]] val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName) val clonedAuto = clone("auto").asInstanceOf[AutoBundle] // Get the empty [[Dangle]]'s of the cloned child val rawDangles = c.cloneDangles() require(rawDangles.size == clonedAuto.elements.size) // Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) } dangles }.getOrElse { // For non-clones, instantiate the child module val mod = try { Module(c.module) } catch { case e: ChiselException => { println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}") throw e } } mod.dangles } } // Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]]. // This will result in a sequence of [[Dangle]] from these [[BaseNode]]s. val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate()) // Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]] val allDangles = nodeDangles ++ childDangles // Group [[allDangles]] by their [[source]]. val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*) // For each [[source]] set of [[Dangle]]s of size 2, ensure that these // can be connected as a source-sink pair (have opposite flipped value). // Make the connection and mark them as [[done]]. val done = Set() ++ pairing.values.filter(_.size == 2).map { case Seq(a, b) => require(a.flipped != b.flipped) // @todo <> in chisel3 makes directionless connection. if (a.flipped) { a.data <> b.data } else { b.data <> a.data } a.source case _ => None } // Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module. val forward = allDangles.filter(d => !done(d.source)) // Generate [[AutoBundle]] IO from [[forward]]. val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*)) // Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]] val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) => if (d.flipped) { d.data <> io } else { io <> d.data } d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name) } // Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]]. wrapper.inModuleBody.reverse.foreach { _() } if (wrapper.shouldBeInlined) { chisel3.experimental.annotate(new ChiselAnnotation { def toFirrtl = InlineAnnotation(toNamed) }) } // Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]]. (auto, dangles) } } /** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike { /** Instantiate hardware of this `Module`. */ val (auto, dangles) = instantiate() } /** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike { // These wires are the default clock+reset for all LazyModule children. // It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the // [[LazyRawModuleImp]] children. // Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly. /** drive clock explicitly. */ val childClock: Clock = Wire(Clock()) /** drive reset explicitly. */ val childReset: Reset = Wire(Reset()) // the default is that these are disabled childClock := false.B.asClock childReset := chisel3.DontCare def provideImplicitClockToLazyChildren: Boolean = false val (auto, dangles) = if (provideImplicitClockToLazyChildren) { withClockAndReset(childClock, childReset) { instantiate() } } else { instantiate() } } File MixedNode.scala: package org.chipsalliance.diplomacy.nodes import chisel3.{Data, DontCare, Wire} import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.{Field, Parameters} import org.chipsalliance.diplomacy.ValName import org.chipsalliance.diplomacy.sourceLine /** One side metadata of a [[Dangle]]. * * Describes one side of an edge going into or out of a [[BaseNode]]. * * @param serial * the global [[BaseNode.serial]] number of the [[BaseNode]] that this [[HalfEdge]] connects to. * @param index * the `index` in the [[BaseNode]]'s input or output port list that this [[HalfEdge]] belongs to. */ case class HalfEdge(serial: Int, index: Int) extends Ordered[HalfEdge] { import scala.math.Ordered.orderingToOrdered def compare(that: HalfEdge): Int = HalfEdge.unapply(this).compare(HalfEdge.unapply(that)) } /** [[Dangle]] captures the `IO` information of a [[LazyModule]] and which two [[BaseNode]]s the [[Edges]]/[[Bundle]] * connects. * * [[Dangle]]s are generated by [[BaseNode.instantiate]] using [[MixedNode.danglesOut]] and [[MixedNode.danglesIn]] , * [[LazyModuleImp.instantiate]] connects those that go to internal or explicit IO connections in a [[LazyModule]]. * * @param source * the source [[HalfEdge]] of this [[Dangle]], which captures the source [[BaseNode]] and the port `index` within * that [[BaseNode]]. * @param sink * sink [[HalfEdge]] of this [[Dangle]], which captures the sink [[BaseNode]] and the port `index` within that * [[BaseNode]]. * @param flipped * flip or not in [[AutoBundle.makeElements]]. If true this corresponds to `danglesOut`, if false it corresponds to * `danglesIn`. * @param dataOpt * actual [[Data]] for the hardware connection. Can be empty if this belongs to a cloned module */ case class Dangle(source: HalfEdge, sink: HalfEdge, flipped: Boolean, name: String, dataOpt: Option[Data]) { def data = dataOpt.get } /** [[Edges]] is a collection of parameters describing the functionality and connection for an interface, which is often * derived from the interconnection protocol and can inform the parameterization of the hardware bundles that actually * implement the protocol. */ case class Edges[EI, EO](in: Seq[EI], out: Seq[EO]) /** A field available in [[Parameters]] used to determine whether [[InwardNodeImp.monitor]] will be called. */ case object MonitorsEnabled extends Field[Boolean](true) /** When rendering the edge in a graphical format, flip the order in which the edges' source and sink are presented. * * For example, when rendering graphML, yEd by default tries to put the source node vertically above the sink node, but * [[RenderFlipped]] inverts this relationship. When a particular [[LazyModule]] contains both source nodes and sink * nodes, flipping the rendering of one node's edge will usual produce a more concise visual layout for the * [[LazyModule]]. */ case object RenderFlipped extends Field[Boolean](false) /** The sealed node class in the package, all node are derived from it. * * @param inner * Sink interface implementation. * @param outer * Source interface implementation. * @param valName * val name of this node. * @tparam DI * Downward-flowing parameters received on the inner side of the node. It is usually a brunch of parameters * describing the protocol parameters from a source. For an [[InwardNode]], it is determined by the connected * [[OutwardNode]]. Since it can be connected to multiple sources, this parameter is always a Seq of source port * parameters. * @tparam UI * Upward-flowing parameters generated by the inner side of the node. It is usually a brunch of parameters describing * the protocol parameters of a sink. For an [[InwardNode]], it is determined itself. * @tparam EI * Edge Parameters describing a connection on the inner side of the node. It is usually a brunch of transfers * specified for a sink according to protocol. * @tparam BI * Bundle type used when connecting to the inner side of the node. It is a hardware interface of this sink interface. * It should extends from [[chisel3.Data]], which represents the real hardware. * @tparam DO * Downward-flowing parameters generated on the outer side of the node. It is usually a brunch of parameters * describing the protocol parameters of a source. For an [[OutwardNode]], it is determined itself. * @tparam UO * Upward-flowing parameters received by the outer side of the node. It is usually a brunch of parameters describing * the protocol parameters from a sink. For an [[OutwardNode]], it is determined by the connected [[InwardNode]]. * Since it can be connected to multiple sinks, this parameter is always a Seq of sink port parameters. * @tparam EO * Edge Parameters describing a connection on the outer side of the node. It is usually a brunch of transfers * specified for a source according to protocol. * @tparam BO * Bundle type used when connecting to the outer side of the node. It is a hardware interface of this source * interface. It should extends from [[chisel3.Data]], which represents the real hardware. * * @note * Call Graph of [[MixedNode]] * - line `─`: source is process by a function and generate pass to others * - Arrow `→`: target of arrow is generated by source * * {{{ * (from the other node) * ┌─────────────────────────────────────────────────────────[[InwardNode.uiParams]]─────────────┐ * ↓ │ * (binding node when elaboration) [[OutwardNode.uoParams]]────────────────────────[[MixedNode.mapParamsU]]→──────────┐ │ * [[InwardNode.accPI]] │ │ │ * │ │ (based on protocol) │ * │ │ [[MixedNode.inner.edgeI]] │ * │ │ ↓ │ * ↓ │ │ │ * (immobilize after elaboration) (inward port from [[OutwardNode]]) │ ↓ │ * [[InwardNode.iBindings]]──┐ [[MixedNode.iDirectPorts]]────────────────────→[[MixedNode.iPorts]] [[InwardNode.uiParams]] │ * │ │ ↑ │ │ │ * │ │ │ [[OutwardNode.doParams]] │ │ * │ │ │ (from the other node) │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * │ │ │ └────────┬──────────────┤ │ * │ │ │ │ │ │ * │ │ │ │ (based on protocol) │ * │ │ │ │ [[MixedNode.inner.edgeI]] │ * │ │ │ │ │ │ * │ │ (from the other node) │ ↓ │ * │ └───[[OutwardNode.oPortMapping]] [[OutwardNode.oStar]] │ [[MixedNode.edgesIn]]───┐ │ * │ ↑ ↑ │ │ ↓ │ * │ │ │ │ │ [[MixedNode.in]] │ * │ │ │ │ ↓ ↑ │ * │ (solve star connection) │ │ │ [[MixedNode.bundleIn]]──┘ │ * ├───[[MixedNode.resolveStar]]→─┼─────────────────────────────┤ └────────────────────────────────────┐ │ * │ │ │ [[MixedNode.bundleOut]]─┐ │ │ * │ │ │ ↑ ↓ │ │ * │ │ │ │ [[MixedNode.out]] │ │ * │ ↓ ↓ │ ↑ │ │ * │ ┌─────[[InwardNode.iPortMapping]] [[InwardNode.iStar]] [[MixedNode.edgesOut]]──┘ │ │ * │ │ (from the other node) ↑ │ │ * │ │ │ │ │ │ * │ │ │ [[MixedNode.outer.edgeO]] │ │ * │ │ │ (based on protocol) │ │ * │ │ │ │ │ │ * │ │ │ ┌────────────────────────────────────────┤ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * (immobilize after elaboration)│ ↓ │ │ │ │ * [[OutwardNode.oBindings]]─┘ [[MixedNode.oDirectPorts]]───→[[MixedNode.oPorts]] [[OutwardNode.doParams]] │ │ * ↑ (inward port from [[OutwardNode]]) │ │ │ │ * │ ┌─────────────────────────────────────────┤ │ │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * [[OutwardNode.accPO]] │ ↓ │ │ │ * (binding node when elaboration) │ [[InwardNode.diParams]]─────→[[MixedNode.mapParamsD]]────────────────────────────┘ │ │ * │ ↑ │ │ * │ └──────────────────────────────────────────────────────────────────────────────────────────┘ │ * └──────────────────────────────────────────────────────────────────────────────────────────────────────────┘ * }}} */ abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data]( val inner: InwardNodeImp[DI, UI, EI, BI], val outer: OutwardNodeImp[DO, UO, EO, BO] )( implicit valName: ValName) extends BaseNode with NodeHandle[DI, UI, EI, BI, DO, UO, EO, BO] with InwardNode[DI, UI, BI] with OutwardNode[DO, UO, BO] { // Generate a [[NodeHandle]] with inward and outward node are both this node. val inward = this val outward = this /** Debug info of nodes binding. */ def bindingInfo: String = s"""$iBindingInfo |$oBindingInfo |""".stripMargin /** Debug info of ports connecting. */ def connectedPortsInfo: String = s"""${oPorts.size} outward ports connected: [${oPorts.map(_._2.name).mkString(",")}] |${iPorts.size} inward ports connected: [${iPorts.map(_._2.name).mkString(",")}] |""".stripMargin /** Debug info of parameters propagations. */ def parametersInfo: String = s"""${doParams.size} downstream outward parameters: [${doParams.mkString(",")}] |${uoParams.size} upstream outward parameters: [${uoParams.mkString(",")}] |${diParams.size} downstream inward parameters: [${diParams.mkString(",")}] |${uiParams.size} upstream inward parameters: [${uiParams.mkString(",")}] |""".stripMargin /** For a given node, converts [[OutwardNode.accPO]] and [[InwardNode.accPI]] to [[MixedNode.oPortMapping]] and * [[MixedNode.iPortMapping]]. * * Given counts of known inward and outward binding and inward and outward star bindings, return the resolved inward * stars and outward stars. * * This method will also validate the arguments and throw a runtime error if the values are unsuitable for this type * of node. * * @param iKnown * Number of known-size ([[BIND_ONCE]]) input bindings. * @param oKnown * Number of known-size ([[BIND_ONCE]]) output bindings. * @param iStar * Number of unknown size ([[BIND_STAR]]) input bindings. * @param oStar * Number of unknown size ([[BIND_STAR]]) output bindings. * @return * A Tuple of the resolved number of input and output connections. */ protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStar: Int, oStar: Int): (Int, Int) /** Function to generate downward-flowing outward params from the downward-flowing input params and the current output * ports. * * @param n * The size of the output sequence to generate. * @param p * Sequence of downward-flowing input parameters of this node. * @return * A `n`-sized sequence of downward-flowing output edge parameters. */ protected[diplomacy] def mapParamsD(n: Int, p: Seq[DI]): Seq[DO] /** Function to generate upward-flowing input parameters from the upward-flowing output parameters [[uiParams]]. * * @param n * Size of the output sequence. * @param p * Upward-flowing output edge parameters. * @return * A n-sized sequence of upward-flowing input edge parameters. */ protected[diplomacy] def mapParamsU(n: Int, p: Seq[UO]): Seq[UI] /** @return * The sink cardinality of the node, the number of outputs bound with [[BIND_QUERY]] summed with inputs bound with * [[BIND_STAR]]. */ protected[diplomacy] lazy val sinkCard: Int = oBindings.count(_._3 == BIND_QUERY) + iBindings.count(_._3 == BIND_STAR) /** @return * The source cardinality of this node, the number of inputs bound with [[BIND_QUERY]] summed with the number of * output bindings bound with [[BIND_STAR]]. */ protected[diplomacy] lazy val sourceCard: Int = iBindings.count(_._3 == BIND_QUERY) + oBindings.count(_._3 == BIND_STAR) /** @return list of nodes involved in flex bindings with this node. */ protected[diplomacy] lazy val flexes: Seq[BaseNode] = oBindings.filter(_._3 == BIND_FLEX).map(_._2) ++ iBindings.filter(_._3 == BIND_FLEX).map(_._2) /** Resolves the flex to be either source or sink and returns the offset where the [[BIND_STAR]] operators begin * greedily taking up the remaining connections. * * @return * A value >= 0 if it is sink cardinality, a negative value for source cardinality. The magnitude of the return * value is not relevant. */ protected[diplomacy] lazy val flexOffset: Int = { /** Recursively performs a depth-first search of the [[flexes]], [[BaseNode]]s connected to this node with flex * operators. The algorithm bottoms out when we either get to a node we have already visited or when we get to a * connection that is not a flex and can set the direction for us. Otherwise, recurse by visiting the `flexes` of * each node in the current set and decide whether they should be added to the set or not. * * @return * the mapping of [[BaseNode]] indexed by their serial numbers. */ def DFS(v: BaseNode, visited: Map[Int, BaseNode]): Map[Int, BaseNode] = { if (visited.contains(v.serial) || !v.flexibleArityDirection) { visited } else { v.flexes.foldLeft(visited + (v.serial -> v))((sum, n) => DFS(n, sum)) } } /** Determine which [[BaseNode]] are involved in resolving the flex connections to/from this node. * * @example * {{{ * a :*=* b :*=* c * d :*=* b * e :*=* f * }}} * * `flexSet` for `a`, `b`, `c`, or `d` will be `Set(a, b, c, d)` `flexSet` for `e` or `f` will be `Set(e,f)` */ val flexSet = DFS(this, Map()).values /** The total number of :*= operators where we're on the left. */ val allSink = flexSet.map(_.sinkCard).sum /** The total number of :=* operators used when we're on the right. */ val allSource = flexSet.map(_.sourceCard).sum require( allSink == 0 || allSource == 0, s"The nodes ${flexSet.map(_.name)} which are inter-connected by :*=* have ${allSink} :*= operators and ${allSource} :=* operators connected to them, making it impossible to determine cardinality inference direction." ) allSink - allSource } /** @return A value >= 0 if it is sink cardinality, a negative value for source cardinality. */ protected[diplomacy] def edgeArityDirection(n: BaseNode): Int = { if (flexibleArityDirection) flexOffset else if (n.flexibleArityDirection) n.flexOffset else 0 } /** For a node which is connected between two nodes, select the one that will influence the direction of the flex * resolution. */ protected[diplomacy] def edgeAritySelect(n: BaseNode, l: => Int, r: => Int): Int = { val dir = edgeArityDirection(n) if (dir < 0) l else if (dir > 0) r else 1 } /** Ensure that the same node is not visited twice in resolving `:*=`, etc operators. */ private var starCycleGuard = false /** Resolve all the star operators into concrete indicies. As connections are being made, some may be "star" * connections which need to be resolved. In some way to determine how many actual edges they correspond to. We also * need to build up the ranges of edges which correspond to each binding operator, so that We can apply the correct * edge parameters and later build up correct bundle connections. * * [[oPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that oPort (binding * operator). [[iPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that iPort * (binding operator). [[oStar]]: `Int` the value to return for this node `N` for any `N :*= foo` or `N :*=* foo :*= * bar` [[iStar]]: `Int` the value to return for this node `N` for any `foo :=* N` or `bar :=* foo :*=* N` */ protected[diplomacy] lazy val ( oPortMapping: Seq[(Int, Int)], iPortMapping: Seq[(Int, Int)], oStar: Int, iStar: Int ) = { try { if (starCycleGuard) throw StarCycleException() starCycleGuard = true // For a given node N... // Number of foo :=* N // + Number of bar :=* foo :*=* N val oStars = oBindings.count { case (_, n, b, _, _) => b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) < 0) } // Number of N :*= foo // + Number of N :*=* foo :*= bar val iStars = iBindings.count { case (_, n, b, _, _) => b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) > 0) } // 1 for foo := N // + bar.iStar for bar :*= foo :*=* N // + foo.iStar for foo :*= N // + 0 for foo :=* N val oKnown = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, 0, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => 0 } }.sum // 1 for N := foo // + bar.oStar for N :*=* foo :=* bar // + foo.oStar for N :=* foo // + 0 for N :*= foo val iKnown = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, 0) case BIND_QUERY => n.oStar case BIND_STAR => 0 } }.sum // Resolve star depends on the node subclass to implement the algorithm for this. val (iStar, oStar) = resolveStar(iKnown, oKnown, iStars, oStars) // Cumulative list of resolved outward binding range starting points val oSum = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, oStar, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => oStar } }.scanLeft(0)(_ + _) // Cumulative list of resolved inward binding range starting points val iSum = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, iStar) case BIND_QUERY => n.oStar case BIND_STAR => iStar } }.scanLeft(0)(_ + _) // Create ranges for each binding based on the running sums and return // those along with resolved values for the star operations. (oSum.init.zip(oSum.tail), iSum.init.zip(iSum.tail), oStar, iStar) } catch { case c: StarCycleException => throw c.copy(loop = context +: c.loop) } } /** Sequence of inward ports. * * This should be called after all star bindings are resolved. * * Each element is: `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. * `n` Instance of inward node. `p` View of [[Parameters]] where this connection was made. `s` Source info where this * connection was made in the source code. */ protected[diplomacy] lazy val oDirectPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oBindings.flatMap { case (i, n, _, p, s) => // for each binding operator in this node, look at what it connects to val (start, end) = n.iPortMapping(i) (start until end).map { j => (j, n, p, s) } } /** Sequence of outward ports. * * This should be called after all star bindings are resolved. * * `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. `n` Instance of * outward node. `p` View of [[Parameters]] where this connection was made. `s` [[SourceInfo]] where this connection * was made in the source code. */ protected[diplomacy] lazy val iDirectPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iBindings.flatMap { case (i, n, _, p, s) => // query this port index range of this node in the other side of node. val (start, end) = n.oPortMapping(i) (start until end).map { j => (j, n, p, s) } } // Ephemeral nodes ( which have non-None iForward/oForward) have in_degree = out_degree // Thus, there must exist an Eulerian path and the below algorithms terminate @scala.annotation.tailrec private def oTrace( tuple: (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) ): (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.iForward(i) match { case None => (i, n, p, s) case Some((j, m)) => oTrace((j, m, p, s)) } } @scala.annotation.tailrec private def iTrace( tuple: (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) ): (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.oForward(i) match { case None => (i, n, p, s) case Some((j, m)) => iTrace((j, m, p, s)) } } /** Final output ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - Numeric index of this binding in the [[InwardNode]] on the other end. * - [[InwardNode]] on the other end of this binding. * - A view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. */ lazy val oPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oDirectPorts.map(oTrace) /** Final input ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - numeric index of this binding in [[OutwardNode]] on the other end. * - [[OutwardNode]] on the other end of this binding. * - a view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. */ lazy val iPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iDirectPorts.map(iTrace) private var oParamsCycleGuard = false protected[diplomacy] lazy val diParams: Seq[DI] = iPorts.map { case (i, n, _, _) => n.doParams(i) } protected[diplomacy] lazy val doParams: Seq[DO] = { try { if (oParamsCycleGuard) throw DownwardCycleException() oParamsCycleGuard = true val o = mapParamsD(oPorts.size, diParams) require( o.size == oPorts.size, s"""Diplomacy has detected a problem with your graph: |At the following node, the number of outward ports should equal the number of produced outward parameters. |$context |$connectedPortsInfo |Downstreamed inward parameters: [${diParams.mkString(",")}] |Produced outward parameters: [${o.mkString(",")}] |""".stripMargin ) o.map(outer.mixO(_, this)) } catch { case c: DownwardCycleException => throw c.copy(loop = context +: c.loop) } } private var iParamsCycleGuard = false protected[diplomacy] lazy val uoParams: Seq[UO] = oPorts.map { case (o, n, _, _) => n.uiParams(o) } protected[diplomacy] lazy val uiParams: Seq[UI] = { try { if (iParamsCycleGuard) throw UpwardCycleException() iParamsCycleGuard = true val i = mapParamsU(iPorts.size, uoParams) require( i.size == iPorts.size, s"""Diplomacy has detected a problem with your graph: |At the following node, the number of inward ports should equal the number of produced inward parameters. |$context |$connectedPortsInfo |Upstreamed outward parameters: [${uoParams.mkString(",")}] |Produced inward parameters: [${i.mkString(",")}] |""".stripMargin ) i.map(inner.mixI(_, this)) } catch { case c: UpwardCycleException => throw c.copy(loop = context +: c.loop) } } /** Outward edge parameters. */ protected[diplomacy] lazy val edgesOut: Seq[EO] = (oPorts.zip(doParams)).map { case ((i, n, p, s), o) => outer.edgeO(o, n.uiParams(i), p, s) } /** Inward edge parameters. */ protected[diplomacy] lazy val edgesIn: Seq[EI] = (iPorts.zip(uiParams)).map { case ((o, n, p, s), i) => inner.edgeI(n.doParams(o), i, p, s) } /** A tuple of the input edge parameters and output edge parameters for the edges bound to this node. * * If you need to access to the edges of a foreign Node, use this method (in/out create bundles). */ lazy val edges: Edges[EI, EO] = Edges(edgesIn, edgesOut) /** Create actual Wires corresponding to the Bundles parameterized by the outward edges of this node. */ protected[diplomacy] lazy val bundleOut: Seq[BO] = edgesOut.map { e => val x = Wire(outer.bundleO(e)).suggestName(s"${valName.value}Out") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } /** Create actual Wires corresponding to the Bundles parameterized by the inward edges of this node. */ protected[diplomacy] lazy val bundleIn: Seq[BI] = edgesIn.map { e => val x = Wire(inner.bundleI(e)).suggestName(s"${valName.value}In") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } private def emptyDanglesOut: Seq[Dangle] = oPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(serial, i), sink = HalfEdge(n.serial, j), flipped = false, name = wirePrefix + "out", dataOpt = None ) } private def emptyDanglesIn: Seq[Dangle] = iPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(n.serial, j), sink = HalfEdge(serial, i), flipped = true, name = wirePrefix + "in", dataOpt = None ) } /** Create the [[Dangle]]s which describe the connections from this node output to other nodes inputs. */ protected[diplomacy] def danglesOut: Seq[Dangle] = emptyDanglesOut.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleOut(i))) } /** Create the [[Dangle]]s which describe the connections from this node input from other nodes outputs. */ protected[diplomacy] def danglesIn: Seq[Dangle] = emptyDanglesIn.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleIn(i))) } private[diplomacy] var instantiated = false /** Gather Bundle and edge parameters of outward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. */ def out: Seq[(BO, EO)] = { require( instantiated, s"$name.out should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleOut.zip(edgesOut) } /** Gather Bundle and edge parameters of inward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. */ def in: Seq[(BI, EI)] = { require( instantiated, s"$name.in should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleIn.zip(edgesIn) } /** Actually instantiate this node during [[LazyModuleImp]] evaluation. Mark that it's safe to use the Bundle wires, * instantiate monitors on all input ports if appropriate, and return all the dangles of this node. */ protected[diplomacy] def instantiate(): Seq[Dangle] = { instantiated = true if (!circuitIdentity) { (iPorts.zip(in)).foreach { case ((_, _, p, _), (b, e)) => if (p(MonitorsEnabled)) inner.monitor(b, e) } } danglesOut ++ danglesIn } protected[diplomacy] def cloneDangles(): Seq[Dangle] = emptyDanglesOut ++ emptyDanglesIn /** Connects the outward part of a node with the inward part of this node. */ protected[diplomacy] def bind( h: OutwardNode[DI, UI, BI], binding: NodeBinding )( implicit p: Parameters, sourceInfo: SourceInfo ): Unit = { val x = this // x := y val y = h sourceLine(sourceInfo, " at ", "") val i = x.iPushed val o = y.oPushed y.oPush( i, x, binding match { case BIND_ONCE => BIND_ONCE case BIND_FLEX => BIND_FLEX case BIND_STAR => BIND_QUERY case BIND_QUERY => BIND_STAR } ) x.iPush(o, y, binding) } /* Metadata for printing the node graph. */ def inputs: Seq[(OutwardNode[DI, UI, BI], RenderedEdge)] = (iPorts.zip(edgesIn)).map { case ((_, n, p, _), e) => val re = inner.render(e) (n, re.copy(flipped = re.flipped != p(RenderFlipped))) } /** Metadata for printing the node graph */ def outputs: Seq[(InwardNode[DO, UO, BO], RenderedEdge)] = oPorts.map { case (i, n, _, _) => (n, n.inputs(i)._2) } }

module TLBuffer_a29d64s7k1z3u( // @[Buffer.scala:40:9] input clock, // @[Buffer.scala:40:9] input reset, // @[Buffer.scala:40:9] output auto_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [6:0] auto_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [28:0] auto_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_d_bits_param, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [6:0] auto_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [63:0] auto_in_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [6:0] auto_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [28:0] auto_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [6:0] auto_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input [63:0] auto_out_d_bits_data // @[LazyModuleImp.scala:107:25] ); wire auto_in_a_valid_0 = auto_in_a_valid; // @[Buffer.scala:40:9] wire [2:0] auto_in_a_bits_opcode_0 = auto_in_a_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] auto_in_a_bits_param_0 = auto_in_a_bits_param; // @[Buffer.scala:40:9] wire [2:0] auto_in_a_bits_size_0 = auto_in_a_bits_size; // @[Buffer.scala:40:9] wire [6:0] auto_in_a_bits_source_0 = auto_in_a_bits_source; // @[Buffer.scala:40:9] wire [28:0] auto_in_a_bits_address_0 = auto_in_a_bits_address; // @[Buffer.scala:40:9] wire [7:0] auto_in_a_bits_mask_0 = auto_in_a_bits_mask; // @[Buffer.scala:40:9] wire [63:0] auto_in_a_bits_data_0 = auto_in_a_bits_data; // @[Buffer.scala:40:9] wire auto_in_a_bits_corrupt_0 = auto_in_a_bits_corrupt; // @[Buffer.scala:40:9] wire auto_in_d_ready_0 = auto_in_d_ready; // @[Buffer.scala:40:9] wire auto_out_a_ready_0 = auto_out_a_ready; // @[Buffer.scala:40:9] wire auto_out_d_valid_0 = auto_out_d_valid; // @[Buffer.scala:40:9] wire [2:0] auto_out_d_bits_opcode_0 = auto_out_d_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] auto_out_d_bits_size_0 = auto_out_d_bits_size; // @[Buffer.scala:40:9] wire [6:0] auto_out_d_bits_source_0 = auto_out_d_bits_source; // @[Buffer.scala:40:9] wire [63:0] auto_out_d_bits_data_0 = auto_out_d_bits_data; // @[Buffer.scala:40:9] wire auto_out_d_bits_sink = 1'h0; // @[Decoupled.scala:362:21] wire auto_out_d_bits_denied = 1'h0; // @[Decoupled.scala:362:21] wire auto_out_d_bits_corrupt = 1'h0; // @[Decoupled.scala:362:21] wire nodeOut_d_bits_sink = 1'h0; // @[Decoupled.scala:362:21] wire nodeOut_d_bits_denied = 1'h0; // @[Decoupled.scala:362:21] wire nodeOut_d_bits_corrupt = 1'h0; // @[Decoupled.scala:362:21] wire [1:0] auto_out_d_bits_param = 2'h0; // @[Decoupled.scala:362:21] wire nodeIn_a_ready; // @[MixedNode.scala:551:17] wire [1:0] nodeOut_d_bits_param = 2'h0; // @[Decoupled.scala:362:21] wire nodeIn_a_valid = auto_in_a_valid_0; // @[Buffer.scala:40:9] wire [2:0] nodeIn_a_bits_opcode = auto_in_a_bits_opcode_0; // @[Buffer.scala:40:9] wire [2:0] nodeIn_a_bits_param = auto_in_a_bits_param_0; // @[Buffer.scala:40:9] wire [2:0] nodeIn_a_bits_size = auto_in_a_bits_size_0; // @[Buffer.scala:40:9] wire [6:0] nodeIn_a_bits_source = auto_in_a_bits_source_0; // @[Buffer.scala:40:9] wire [28:0] nodeIn_a_bits_address = auto_in_a_bits_address_0; // @[Buffer.scala:40:9] wire [7:0] nodeIn_a_bits_mask = auto_in_a_bits_mask_0; // @[Buffer.scala:40:9] wire [63:0] nodeIn_a_bits_data = auto_in_a_bits_data_0; // @[Buffer.scala:40:9] wire nodeIn_a_bits_corrupt = auto_in_a_bits_corrupt_0; // @[Buffer.scala:40:9] wire nodeIn_d_ready = auto_in_d_ready_0; // @[Buffer.scala:40:9] wire nodeIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] nodeIn_d_bits_param; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_d_bits_size; // @[MixedNode.scala:551:17] wire [6:0] nodeIn_d_bits_source; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_sink; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_denied; // @[MixedNode.scala:551:17] wire [63:0] nodeIn_d_bits_data; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_corrupt; // @[MixedNode.scala:551:17] wire nodeOut_a_ready = auto_out_a_ready_0; // @[Buffer.scala:40:9] wire nodeOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_a_bits_param; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_a_bits_size; // @[MixedNode.scala:542:17] wire [6:0] nodeOut_a_bits_source; // @[MixedNode.scala:542:17] wire [28:0] nodeOut_a_bits_address; // @[MixedNode.scala:542:17] wire [7:0] nodeOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [63:0] nodeOut_a_bits_data; // @[MixedNode.scala:542:17] wire nodeOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire nodeOut_d_ready; // @[MixedNode.scala:542:17] wire nodeOut_d_valid = auto_out_d_valid_0; // @[Buffer.scala:40:9] wire [2:0] nodeOut_d_bits_opcode = auto_out_d_bits_opcode_0; // @[Buffer.scala:40:9] wire [2:0] nodeOut_d_bits_size = auto_out_d_bits_size_0; // @[Buffer.scala:40:9] wire [6:0] nodeOut_d_bits_source = auto_out_d_bits_source_0; // @[Buffer.scala:40:9] wire [63:0] nodeOut_d_bits_data = auto_out_d_bits_data_0; // @[Buffer.scala:40:9] wire auto_in_a_ready_0; // @[Buffer.scala:40:9] wire [2:0] auto_in_d_bits_opcode_0; // @[Buffer.scala:40:9] wire [1:0] auto_in_d_bits_param_0; // @[Buffer.scala:40:9] wire [2:0] auto_in_d_bits_size_0; // @[Buffer.scala:40:9] wire [6:0] auto_in_d_bits_source_0; // @[Buffer.scala:40:9] wire auto_in_d_bits_sink_0; // @[Buffer.scala:40:9] wire auto_in_d_bits_denied_0; // @[Buffer.scala:40:9] wire [63:0] auto_in_d_bits_data_0; // @[Buffer.scala:40:9] wire auto_in_d_bits_corrupt_0; // @[Buffer.scala:40:9] wire auto_in_d_valid_0; // @[Buffer.scala:40:9] wire [2:0] auto_out_a_bits_opcode_0; // @[Buffer.scala:40:9] wire [2:0] auto_out_a_bits_param_0; // @[Buffer.scala:40:9] wire [2:0] auto_out_a_bits_size_0; // @[Buffer.scala:40:9] wire [6:0] auto_out_a_bits_source_0; // @[Buffer.scala:40:9] wire [28:0] auto_out_a_bits_address_0; // @[Buffer.scala:40:9] wire [7:0] auto_out_a_bits_mask_0; // @[Buffer.scala:40:9] wire [63:0] auto_out_a_bits_data_0; // @[Buffer.scala:40:9] wire auto_out_a_bits_corrupt_0; // @[Buffer.scala:40:9] wire auto_out_a_valid_0; // @[Buffer.scala:40:9] wire auto_out_d_ready_0; // @[Buffer.scala:40:9] assign auto_in_a_ready_0 = nodeIn_a_ready; // @[Buffer.scala:40:9] assign auto_in_d_valid_0 = nodeIn_d_valid; // @[Buffer.scala:40:9] assign auto_in_d_bits_opcode_0 = nodeIn_d_bits_opcode; // @[Buffer.scala:40:9] assign auto_in_d_bits_param_0 = nodeIn_d_bits_param; // @[Buffer.scala:40:9] assign auto_in_d_bits_size_0 = nodeIn_d_bits_size; // @[Buffer.scala:40:9] assign auto_in_d_bits_source_0 = nodeIn_d_bits_source; // @[Buffer.scala:40:9] assign auto_in_d_bits_sink_0 = nodeIn_d_bits_sink; // @[Buffer.scala:40:9] assign auto_in_d_bits_denied_0 = nodeIn_d_bits_denied; // @[Buffer.scala:40:9] assign auto_in_d_bits_data_0 = nodeIn_d_bits_data; // @[Buffer.scala:40:9] assign auto_in_d_bits_corrupt_0 = nodeIn_d_bits_corrupt; // @[Buffer.scala:40:9] assign auto_out_a_valid_0 = nodeOut_a_valid; // @[Buffer.scala:40:9] assign auto_out_a_bits_opcode_0 = nodeOut_a_bits_opcode; // @[Buffer.scala:40:9] assign auto_out_a_bits_param_0 = nodeOut_a_bits_param; // @[Buffer.scala:40:9] assign auto_out_a_bits_size_0 = nodeOut_a_bits_size; // @[Buffer.scala:40:9] assign auto_out_a_bits_source_0 = nodeOut_a_bits_source; // @[Buffer.scala:40:9] assign auto_out_a_bits_address_0 = nodeOut_a_bits_address; // @[Buffer.scala:40:9] assign auto_out_a_bits_mask_0 = nodeOut_a_bits_mask; // @[Buffer.scala:40:9] assign auto_out_a_bits_data_0 = nodeOut_a_bits_data; // @[Buffer.scala:40:9] assign auto_out_a_bits_corrupt_0 = nodeOut_a_bits_corrupt; // @[Buffer.scala:40:9] assign auto_out_d_ready_0 = nodeOut_d_ready; // @[Buffer.scala:40:9] TLMonitor_4 monitor ( // @[Nodes.scala:27:25] .clock (clock), .reset (reset), .io_in_a_ready (nodeIn_a_ready), // @[MixedNode.scala:551:17] .io_in_a_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17] .io_in_a_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17] .io_in_a_bits_param (nodeIn_a_bits_param), // @[MixedNode.scala:551:17] .io_in_a_bits_size (nodeIn_a_bits_size), // @[MixedNode.scala:551:17] .io_in_a_bits_source (nodeIn_a_bits_source), // @[MixedNode.scala:551:17] .io_in_a_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17] .io_in_a_bits_mask (nodeIn_a_bits_mask), // @[MixedNode.scala:551:17] .io_in_a_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17] .io_in_a_bits_corrupt (nodeIn_a_bits_corrupt), // @[MixedNode.scala:551:17] .io_in_d_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17] .io_in_d_valid (nodeIn_d_valid), // @[MixedNode.scala:551:17] .io_in_d_bits_opcode (nodeIn_d_bits_opcode), // @[MixedNode.scala:551:17] .io_in_d_bits_param (nodeIn_d_bits_param), // @[MixedNode.scala:551:17] .io_in_d_bits_size (nodeIn_d_bits_size), // @[MixedNode.scala:551:17] .io_in_d_bits_source (nodeIn_d_bits_source), // @[MixedNode.scala:551:17] .io_in_d_bits_sink (nodeIn_d_bits_sink), // @[MixedNode.scala:551:17] .io_in_d_bits_denied (nodeIn_d_bits_denied), // @[MixedNode.scala:551:17] .io_in_d_bits_data (nodeIn_d_bits_data), // @[MixedNode.scala:551:17] .io_in_d_bits_corrupt (nodeIn_d_bits_corrupt) // @[MixedNode.scala:551:17] ); // @[Nodes.scala:27:25] Queue2_TLBundleA_a29d64s7k1z3u nodeOut_a_q ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (nodeIn_a_ready), .io_enq_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17] .io_enq_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17] .io_enq_bits_param (nodeIn_a_bits_param), // @[MixedNode.scala:551:17] .io_enq_bits_size (nodeIn_a_bits_size), // @[MixedNode.scala:551:17] .io_enq_bits_source (nodeIn_a_bits_source), // @[MixedNode.scala:551:17] .io_enq_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17] .io_enq_bits_mask (nodeIn_a_bits_mask), // @[MixedNode.scala:551:17] .io_enq_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17] .io_enq_bits_corrupt (nodeIn_a_bits_corrupt), // @[MixedNode.scala:551:17] .io_deq_ready (nodeOut_a_ready), // @[MixedNode.scala:542:17] .io_deq_valid (nodeOut_a_valid), .io_deq_bits_opcode (nodeOut_a_bits_opcode), .io_deq_bits_param (nodeOut_a_bits_param), .io_deq_bits_size (nodeOut_a_bits_size), .io_deq_bits_source (nodeOut_a_bits_source), .io_deq_bits_address (nodeOut_a_bits_address), .io_deq_bits_mask (nodeOut_a_bits_mask), .io_deq_bits_data (nodeOut_a_bits_data), .io_deq_bits_corrupt (nodeOut_a_bits_corrupt) ); // @[Decoupled.scala:362:21] Queue2_TLBundleD_a29d64s7k1z3u nodeIn_d_q ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (nodeOut_d_ready), .io_enq_valid (nodeOut_d_valid), // @[MixedNode.scala:542:17] .io_enq_bits_opcode (nodeOut_d_bits_opcode), // @[MixedNode.scala:542:17] .io_enq_bits_size (nodeOut_d_bits_size), // @[MixedNode.scala:542:17] .io_enq_bits_source (nodeOut_d_bits_source), // @[MixedNode.scala:542:17] .io_enq_bits_data (nodeOut_d_bits_data), // @[MixedNode.scala:542:17] .io_deq_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17] .io_deq_valid (nodeIn_d_valid), .io_deq_bits_opcode (nodeIn_d_bits_opcode), .io_deq_bits_param (nodeIn_d_bits_param), .io_deq_bits_size (nodeIn_d_bits_size), .io_deq_bits_source (nodeIn_d_bits_source), .io_deq_bits_sink (nodeIn_d_bits_sink), .io_deq_bits_denied (nodeIn_d_bits_denied), .io_deq_bits_data (nodeIn_d_bits_data), .io_deq_bits_corrupt (nodeIn_d_bits_corrupt) ); // @[Decoupled.scala:362:21] assign auto_in_a_ready = auto_in_a_ready_0; // @[Buffer.scala:40:9] assign auto_in_d_valid = auto_in_d_valid_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_opcode = auto_in_d_bits_opcode_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_param = auto_in_d_bits_param_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_size = auto_in_d_bits_size_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_source = auto_in_d_bits_source_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_sink = auto_in_d_bits_sink_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_denied = auto_in_d_bits_denied_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_data = auto_in_d_bits_data_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_corrupt = auto_in_d_bits_corrupt_0; // @[Buffer.scala:40:9] assign auto_out_a_valid = auto_out_a_valid_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_opcode = auto_out_a_bits_opcode_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_param = auto_out_a_bits_param_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_size = auto_out_a_bits_size_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_source = auto_out_a_bits_source_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_address = auto_out_a_bits_address_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_mask = auto_out_a_bits_mask_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_data = auto_out_a_bits_data_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_corrupt = auto_out_a_bits_corrupt_0; // @[Buffer.scala:40:9] assign auto_out_d_ready = auto_out_d_ready_0; // @[Buffer.scala:40:9] endmodule

Generate the Verilog code corresponding to the following Chisel files. File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /** Like Vec.apply(idx), but tolerates indices of mismatched width */ def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /** Any Data subtype that has a Bool member named valid. */ type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /** converts from camel case to to underscores, also removing all spaces */ def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /** converts spaces or underscores to hyphens, also lowering case */ def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y | (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y || y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /** Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation */ def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag }

module OptimizationBarrier_EntryData_12( // @[package.scala:267:30] input clock, // @[package.scala:267:30] input reset, // @[package.scala:267:30] input [19:0] io_x_ppn, // @[package.scala:268:18] input io_x_u, // @[package.scala:268:18] input io_x_g, // @[package.scala:268:18] input io_x_ae, // @[package.scala:268:18] input io_x_sw, // @[package.scala:268:18] input io_x_sx, // @[package.scala:268:18] input io_x_sr, // @[package.scala:268:18] input io_x_pw, // @[package.scala:268:18] input io_x_px, // @[package.scala:268:18] input io_x_pr, // @[package.scala:268:18] input io_x_pal, // @[package.scala:268:18] input io_x_paa, // @[package.scala:268:18] input io_x_eff, // @[package.scala:268:18] input io_x_c, // @[package.scala:268:18] input io_x_fragmented_superpage, // @[package.scala:268:18] output [19:0] io_y_ppn, // @[package.scala:268:18] output io_y_u, // @[package.scala:268:18] output io_y_g, // @[package.scala:268:18] output io_y_ae, // @[package.scala:268:18] output io_y_sw, // @[package.scala:268:18] output io_y_sx, // @[package.scala:268:18] output io_y_sr, // @[package.scala:268:18] output io_y_pw, // @[package.scala:268:18] output io_y_px, // @[package.scala:268:18] output io_y_pr, // @[package.scala:268:18] output io_y_pal, // @[package.scala:268:18] output io_y_paa, // @[package.scala:268:18] output io_y_eff, // @[package.scala:268:18] output io_y_c, // @[package.scala:268:18] output io_y_fragmented_superpage // @[package.scala:268:18] ); wire [19:0] io_x_ppn_0 = io_x_ppn; // @[package.scala:267:30] wire io_x_u_0 = io_x_u; // @[package.scala:267:30] wire io_x_g_0 = io_x_g; // @[package.scala:267:30] wire io_x_ae_0 = io_x_ae; // @[package.scala:267:30] wire io_x_sw_0 = io_x_sw; // @[package.scala:267:30] wire io_x_sx_0 = io_x_sx; // @[package.scala:267:30] wire io_x_sr_0 = io_x_sr; // @[package.scala:267:30] wire io_x_pw_0 = io_x_pw; // @[package.scala:267:30] wire io_x_px_0 = io_x_px; // @[package.scala:267:30] wire io_x_pr_0 = io_x_pr; // @[package.scala:267:30] wire io_x_pal_0 = io_x_pal; // @[package.scala:267:30] wire io_x_paa_0 = io_x_paa; // @[package.scala:267:30] wire io_x_eff_0 = io_x_eff; // @[package.scala:267:30] wire io_x_c_0 = io_x_c; // @[package.scala:267:30] wire io_x_fragmented_superpage_0 = io_x_fragmented_superpage; // @[package.scala:267:30] wire [19:0] io_y_ppn_0 = io_x_ppn_0; // @[package.scala:267:30] wire io_y_u_0 = io_x_u_0; // @[package.scala:267:30] wire io_y_g_0 = io_x_g_0; // @[package.scala:267:30] wire io_y_ae_0 = io_x_ae_0; // @[package.scala:267:30] wire io_y_sw_0 = io_x_sw_0; // @[package.scala:267:30] wire io_y_sx_0 = io_x_sx_0; // @[package.scala:267:30] wire io_y_sr_0 = io_x_sr_0; // @[package.scala:267:30] wire io_y_pw_0 = io_x_pw_0; // @[package.scala:267:30] wire io_y_px_0 = io_x_px_0; // @[package.scala:267:30] wire io_y_pr_0 = io_x_pr_0; // @[package.scala:267:30] wire io_y_pal_0 = io_x_pal_0; // @[package.scala:267:30] wire io_y_paa_0 = io_x_paa_0; // @[package.scala:267:30] wire io_y_eff_0 = io_x_eff_0; // @[package.scala:267:30] wire io_y_c_0 = io_x_c_0; // @[package.scala:267:30] wire io_y_fragmented_superpage_0 = io_x_fragmented_superpage_0; // @[package.scala:267:30] assign io_y_ppn = io_y_ppn_0; // @[package.scala:267:30] assign io_y_u = io_y_u_0; // @[package.scala:267:30] assign io_y_g = io_y_g_0; // @[package.scala:267:30] assign io_y_ae = io_y_ae_0; // @[package.scala:267:30] assign io_y_sw = io_y_sw_0; // @[package.scala:267:30] assign io_y_sx = io_y_sx_0; // @[package.scala:267:30] assign io_y_sr = io_y_sr_0; // @[package.scala:267:30] assign io_y_pw = io_y_pw_0; // @[package.scala:267:30] assign io_y_px = io_y_px_0; // @[package.scala:267:30] assign io_y_pr = io_y_pr_0; // @[package.scala:267:30] assign io_y_pal = io_y_pal_0; // @[package.scala:267:30] assign io_y_paa = io_y_paa_0; // @[package.scala:267:30] assign io_y_eff = io_y_eff_0; // @[package.scala:267:30] assign io_y_c = io_y_c_0; // @[package.scala:267:30] assign io_y_fragmented_superpage = io_y_fragmented_superpage_0; // @[package.scala:267:30] endmodule

Generate the Verilog code corresponding to the following Chisel files. File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /** Like Vec.apply(idx), but tolerates indices of mismatched width */ def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /** Any Data subtype that has a Bool member named valid. */ type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /** converts from camel case to to underscores, also removing all spaces */ def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /** converts spaces or underscores to hyphens, also lowering case */ def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y | (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y || y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /** Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation */ def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File DCache.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.rocket import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config._ import freechips.rocketchip.amba.AMBAProt import freechips.rocketchip.diplomacy.{BufferParams} import freechips.rocketchip.prci.{ClockCrossingType, RationalCrossing, SynchronousCrossing, AsynchronousCrossing, CreditedCrossing} import freechips.rocketchip.tile.{CoreBundle, LookupByHartId} import freechips.rocketchip.tilelink.{TLFIFOFixer,ClientMetadata, TLBundleA, TLAtomics, TLBundleB, TLPermissions} import freechips.rocketchip.tilelink.TLMessages.{AccessAck, HintAck, AccessAckData, Grant, GrantData, ReleaseAck} import freechips.rocketchip.util.{CanHaveErrors, ClockGate, IdentityCode, ReplacementPolicy, DescribedSRAM, property} import freechips.rocketchip.util.BooleanToAugmentedBoolean import freechips.rocketchip.util.UIntToAugmentedUInt import freechips.rocketchip.util.UIntIsOneOf import freechips.rocketchip.util.IntToAugmentedInt import freechips.rocketchip.util.SeqToAugmentedSeq import freechips.rocketchip.util.SeqBoolBitwiseOps // TODO: delete this trait once deduplication is smart enough to avoid globally inlining matching circuits trait InlineInstance { self: chisel3.experimental.BaseModule => chisel3.experimental.annotate( new chisel3.experimental.ChiselAnnotation { def toFirrtl: firrtl.annotations.Annotation = firrtl.passes.InlineAnnotation(self.toNamed) } ) } class DCacheErrors(implicit p: Parameters) extends L1HellaCacheBundle()(p) with CanHaveErrors { val correctable = (cacheParams.tagCode.canCorrect || cacheParams.dataCode.canCorrect).option(Valid(UInt(paddrBits.W))) val uncorrectable = (cacheParams.tagCode.canDetect || cacheParams.dataCode.canDetect).option(Valid(UInt(paddrBits.W))) val bus = Valid(UInt(paddrBits.W)) } class DCacheDataReq(implicit p: Parameters) extends L1HellaCacheBundle()(p) { val addr = UInt(untagBits.W) val write = Bool() val wdata = UInt((encBits * rowBytes / eccBytes).W) val wordMask = UInt((rowBytes / subWordBytes).W) val eccMask = UInt((wordBytes / eccBytes).W) val way_en = UInt(nWays.W) } class DCacheDataArray(implicit p: Parameters) extends L1HellaCacheModule()(p) { val io = IO(new Bundle { val req = Flipped(Valid(new DCacheDataReq)) val resp = Output(Vec(nWays, UInt((req.bits.wdata.getWidth).W))) }) require(rowBits % subWordBits == 0, "rowBits must be a multiple of subWordBits") val eccMask = if (eccBits == subWordBits) Seq(true.B) else io.req.bits.eccMask.asBools val wMask = if (nWays == 1) eccMask else (0 until nWays).flatMap(i => eccMask.map(_ && io.req.bits.way_en(i))) val wWords = io.req.bits.wdata.grouped(encBits * (subWordBits / eccBits)) val addr = io.req.bits.addr >> rowOffBits val data_arrays = Seq.tabulate(rowBits / subWordBits) { i => DescribedSRAM( name = s"${tileParams.baseName}_dcache_data_arrays_${i}", desc = "DCache Data Array", size = nSets * cacheBlockBytes / rowBytes, data = Vec(nWays * (subWordBits / eccBits), UInt(encBits.W)) ) } val rdata = for ((array , i) <- data_arrays.zipWithIndex) yield { val valid = io.req.valid && ((data_arrays.size == 1).B || io.req.bits.wordMask(i)) when (valid && io.req.bits.write) { val wMaskSlice = (0 until wMask.size).filter(j => i % (wordBits/subWordBits) == (j % (wordBytes/eccBytes)) / (subWordBytes/eccBytes)).map(wMask(_)) val wData = wWords(i).grouped(encBits) array.write(addr, VecInit((0 until nWays).flatMap(i => wData)), wMaskSlice) } val data = array.read(addr, valid && !io.req.bits.write) data.grouped(subWordBits / eccBits).map(_.asUInt).toSeq } (io.resp zip rdata.transpose).foreach { case (resp, data) => resp := data.asUInt } } class DCacheMetadataReq(implicit p: Parameters) extends L1HellaCacheBundle()(p) { val write = Bool() val addr = UInt(vaddrBitsExtended.W) val idx = UInt(idxBits.W) val way_en = UInt(nWays.W) val data = UInt(cacheParams.tagCode.width(new L1Metadata().getWidth).W) } class DCache(staticIdForMetadataUseOnly: Int, val crossing: ClockCrossingType)(implicit p: Parameters) extends HellaCache(staticIdForMetadataUseOnly)(p) { override lazy val module = new DCacheModule(this) } class DCacheTLBPort(implicit p: Parameters) extends CoreBundle()(p) { val req = Flipped(Decoupled(new TLBReq(coreDataBytes.log2))) val s1_resp = Output(new TLBResp(coreDataBytes.log2)) val s2_kill = Input(Bool()) } class DCacheModule(outer: DCache) extends HellaCacheModule(outer) { val tECC = cacheParams.tagCode val dECC = cacheParams.dataCode require(subWordBits % eccBits == 0, "subWordBits must be a multiple of eccBits") require(eccBytes == 1 || !dECC.isInstanceOf[IdentityCode]) require(cacheParams.silentDrop || cacheParams.acquireBeforeRelease, "!silentDrop requires acquireBeforeRelease") val usingRMW = eccBytes > 1 || usingAtomicsInCache val mmioOffset = outer.firstMMIO edge.manager.requireFifo(TLFIFOFixer.allVolatile) // TileLink pipelining MMIO requests val clock_en_reg = Reg(Bool()) io.cpu.clock_enabled := clock_en_reg val gated_clock = if (!cacheParams.clockGate) clock else ClockGate(clock, clock_en_reg, "dcache_clock_gate") class DCacheModuleImpl { // entering gated-clock domain val tlb = Module(new TLB(false, log2Ceil(coreDataBytes), TLBConfig(nTLBSets, nTLBWays, cacheParams.nTLBBasePageSectors, cacheParams.nTLBSuperpages))) val pma_checker = Module(new TLB(false, log2Ceil(coreDataBytes), TLBConfig(nTLBSets, nTLBWays, cacheParams.nTLBBasePageSectors, cacheParams.nTLBSuperpages)) with InlineInstance) // tags val replacer = ReplacementPolicy.fromString(cacheParams.replacementPolicy, nWays) /** Metadata Arbiter: * 0: Tag update on reset * 1: Tag update on ECC error * 2: Tag update on hit * 3: Tag update on refill * 4: Tag update on release * 5: Tag update on flush * 6: Tag update on probe * 7: Tag update on CPU request */ val metaArb = Module(new Arbiter(new DCacheMetadataReq, 8) with InlineInstance) val tag_array = DescribedSRAM( name = s"${tileParams.baseName}_dcache_tag_array", desc = "DCache Tag Array", size = nSets, data = Vec(nWays, chiselTypeOf(metaArb.io.out.bits.data)) ) // data val data = Module(new DCacheDataArray) /** Data Arbiter * 0: data from pending store buffer * 1: data from TL-D refill * 2: release to TL-A * 3: hit path to CPU */ val dataArb = Module(new Arbiter(new DCacheDataReq, 4) with InlineInstance) dataArb.io.in.tail.foreach(_.bits.wdata := dataArb.io.in.head.bits.wdata) // tie off write ports by default data.io.req.bits <> dataArb.io.out.bits data.io.req.valid := dataArb.io.out.valid dataArb.io.out.ready := true.B metaArb.io.out.ready := clock_en_reg val tl_out_a = Wire(chiselTypeOf(tl_out.a)) tl_out.a <> { val a_queue_depth = outer.crossing match { case RationalCrossing(_) => // TODO make this depend on the actual ratio? if (cacheParams.separateUncachedResp) (maxUncachedInFlight + 1) / 2 else 2 min maxUncachedInFlight-1 case SynchronousCrossing(BufferParams.none) => 1 // Need some buffering to guarantee livelock freedom case SynchronousCrossing(_) => 0 // Adequate buffering within the crossing case _: AsynchronousCrossing => 0 // Adequate buffering within the crossing case _: CreditedCrossing => 0 // Adequate buffering within the crossing } Queue(tl_out_a, a_queue_depth, flow = true) } val (tl_out_c, release_queue_empty) = if (cacheParams.acquireBeforeRelease) { val q = Module(new Queue(chiselTypeOf(tl_out.c.bits), cacheDataBeats, flow = true)) tl_out.c <> q.io.deq (q.io.enq, q.io.count === 0.U) } else { (tl_out.c, true.B) } val s1_valid = RegNext(io.cpu.req.fire, false.B) val s1_probe = RegNext(tl_out.b.fire, false.B) val probe_bits = RegEnable(tl_out.b.bits, tl_out.b.fire) // TODO has data now :( val s1_nack = WireDefault(false.B) val s1_valid_masked = s1_valid && !io.cpu.s1_kill val s1_valid_not_nacked = s1_valid && !s1_nack val s1_tlb_req_valid = RegNext(io.tlb_port.req.fire, false.B) val s2_tlb_req_valid = RegNext(s1_tlb_req_valid, false.B) val s0_clk_en = metaArb.io.out.valid && !metaArb.io.out.bits.write val s0_req = WireInit(io.cpu.req.bits) s0_req.addr := Cat(metaArb.io.out.bits.addr >> blockOffBits, io.cpu.req.bits.addr(blockOffBits-1,0)) s0_req.idx.foreach(_ := Cat(metaArb.io.out.bits.idx, s0_req.addr(blockOffBits-1, 0))) when (!metaArb.io.in(7).ready) { s0_req.phys := true.B } val s1_req = RegEnable(s0_req, s0_clk_en) val s1_vaddr = Cat(s1_req.idx.getOrElse(s1_req.addr) >> tagLSB, s1_req.addr(tagLSB-1, 0)) val s0_tlb_req = WireInit(io.tlb_port.req.bits) when (!io.tlb_port.req.fire) { s0_tlb_req.passthrough := s0_req.phys s0_tlb_req.vaddr := s0_req.addr s0_tlb_req.size := s0_req.size s0_tlb_req.cmd := s0_req.cmd s0_tlb_req.prv := s0_req.dprv s0_tlb_req.v := s0_req.dv } val s1_tlb_req = RegEnable(s0_tlb_req, s0_clk_en || io.tlb_port.req.valid) val s1_read = isRead(s1_req.cmd) val s1_write = isWrite(s1_req.cmd) val s1_readwrite = s1_read || s1_write val s1_sfence = s1_req.cmd === M_SFENCE || s1_req.cmd === M_HFENCEV || s1_req.cmd === M_HFENCEG val s1_flush_line = s1_req.cmd === M_FLUSH_ALL && s1_req.size(0) val s1_flush_valid = Reg(Bool()) val s1_waw_hazard = Wire(Bool()) val s_ready :: s_voluntary_writeback :: s_probe_rep_dirty :: s_probe_rep_clean :: s_probe_retry :: s_probe_rep_miss :: s_voluntary_write_meta :: s_probe_write_meta :: s_dummy :: s_voluntary_release :: Nil = Enum(10) val supports_flush = outer.flushOnFenceI || coreParams.haveCFlush val flushed = RegInit(true.B) val flushing = RegInit(false.B) val flushing_req = Reg(chiselTypeOf(s1_req)) val cached_grant_wait = RegInit(false.B) val resetting = RegInit(false.B) val flushCounter = RegInit((nSets * (nWays-1)).U(log2Ceil(nSets * nWays).W)) val release_ack_wait = RegInit(false.B) val release_ack_addr = Reg(UInt(paddrBits.W)) val release_state = RegInit(s_ready) val refill_way = Reg(UInt()) val any_pstore_valid = Wire(Bool()) val inWriteback = release_state.isOneOf(s_voluntary_writeback, s_probe_rep_dirty) val releaseWay = Wire(UInt()) io.cpu.req.ready := (release_state === s_ready) && !cached_grant_wait && !s1_nack // I/O MSHRs val uncachedInFlight = RegInit(VecInit(Seq.fill(maxUncachedInFlight)(false.B))) val uncachedReqs = Reg(Vec(maxUncachedInFlight, new HellaCacheReq)) val uncachedResp = WireInit(new HellaCacheReq, DontCare) // hit initiation path val s0_read = isRead(io.cpu.req.bits.cmd) dataArb.io.in(3).valid := io.cpu.req.valid && likelyNeedsRead(io.cpu.req.bits) dataArb.io.in(3).bits := dataArb.io.in(1).bits dataArb.io.in(3).bits.write := false.B dataArb.io.in(3).bits.addr := Cat(io.cpu.req.bits.idx.getOrElse(io.cpu.req.bits.addr) >> tagLSB, io.cpu.req.bits.addr(tagLSB-1, 0)) dataArb.io.in(3).bits.wordMask := { val mask = (subWordBytes.log2 until rowOffBits).foldLeft(1.U) { case (in, i) => val upper_mask = Mux((i >= wordBytes.log2).B || io.cpu.req.bits.size <= i.U, 0.U, ((BigInt(1) << (1 << (i - subWordBytes.log2)))-1).U) val upper = Mux(io.cpu.req.bits.addr(i), in, 0.U) | upper_mask val lower = Mux(io.cpu.req.bits.addr(i), 0.U, in) upper ## lower } Fill(subWordBytes / eccBytes, mask) } dataArb.io.in(3).bits.eccMask := ~0.U((wordBytes / eccBytes).W) dataArb.io.in(3).bits.way_en := ~0.U(nWays.W) when (!dataArb.io.in(3).ready && s0_read) { io.cpu.req.ready := false.B } val s1_did_read = RegEnable(dataArb.io.in(3).ready && (io.cpu.req.valid && needsRead(io.cpu.req.bits)), s0_clk_en) val s1_read_mask = RegEnable(dataArb.io.in(3).bits.wordMask, s0_clk_en) metaArb.io.in(7).valid := io.cpu.req.valid metaArb.io.in(7).bits.write := false.B metaArb.io.in(7).bits.idx := dataArb.io.in(3).bits.addr(idxMSB, idxLSB) metaArb.io.in(7).bits.addr := io.cpu.req.bits.addr metaArb.io.in(7).bits.way_en := metaArb.io.in(4).bits.way_en metaArb.io.in(7).bits.data := metaArb.io.in(4).bits.data when (!metaArb.io.in(7).ready) { io.cpu.req.ready := false.B } // address translation val s1_cmd_uses_tlb = s1_readwrite || s1_flush_line || s1_req.cmd === M_WOK io.ptw <> tlb.io.ptw tlb.io.kill := io.cpu.s2_kill || s2_tlb_req_valid && io.tlb_port.s2_kill tlb.io.req.valid := s1_tlb_req_valid || s1_valid && !io.cpu.s1_kill && s1_cmd_uses_tlb tlb.io.req.bits := s1_tlb_req when (!tlb.io.req.ready && !tlb.io.ptw.resp.valid && !io.cpu.req.bits.phys) { io.cpu.req.ready := false.B } when (!s1_tlb_req_valid && s1_valid && s1_cmd_uses_tlb && tlb.io.resp.miss) { s1_nack := true.B } tlb.io.sfence.valid := s1_valid && !io.cpu.s1_kill && s1_sfence tlb.io.sfence.bits.rs1 := s1_req.size(0) tlb.io.sfence.bits.rs2 := s1_req.size(1) tlb.io.sfence.bits.asid := io.cpu.s1_data.data tlb.io.sfence.bits.addr := s1_req.addr tlb.io.sfence.bits.hv := s1_req.cmd === M_HFENCEV tlb.io.sfence.bits.hg := s1_req.cmd === M_HFENCEG io.tlb_port.req.ready := clock_en_reg io.tlb_port.s1_resp := tlb.io.resp when (s1_tlb_req_valid && s1_valid && !(s1_req.phys && s1_req.no_xcpt)) { s1_nack := true.B } pma_checker.io <> DontCare pma_checker.io.req.bits.passthrough := true.B pma_checker.io.req.bits.vaddr := s1_req.addr pma_checker.io.req.bits.size := s1_req.size pma_checker.io.req.bits.cmd := s1_req.cmd pma_checker.io.req.bits.prv := s1_req.dprv pma_checker.io.req.bits.v := s1_req.dv val s1_paddr = Cat(Mux(s1_tlb_req_valid, s1_req.addr(paddrBits-1, pgIdxBits), tlb.io.resp.paddr >> pgIdxBits), s1_req.addr(pgIdxBits-1, 0)) val s1_victim_way = Wire(UInt()) val (s1_hit_way, s1_hit_state, s1_meta) = if (usingDataScratchpad) { val baseAddr = p(LookupByHartId)(_.dcache.flatMap(_.scratch.map(_.U)), io_hartid.get) | io_mmio_address_prefix.get val inScratchpad = s1_paddr >= baseAddr && s1_paddr < baseAddr + (nSets * cacheBlockBytes).U val hitState = Mux(inScratchpad, ClientMetadata.maximum, ClientMetadata.onReset) val dummyMeta = L1Metadata(0.U, ClientMetadata.onReset) (inScratchpad, hitState, Seq(tECC.encode(dummyMeta.asUInt))) } else { val metaReq = metaArb.io.out val metaIdx = metaReq.bits.idx when (metaReq.valid && metaReq.bits.write) { val wmask = if (nWays == 1) Seq(true.B) else metaReq.bits.way_en.asBools tag_array.write(metaIdx, VecInit(Seq.fill(nWays)(metaReq.bits.data)), wmask) } val s1_meta = tag_array.read(metaIdx, metaReq.valid && !metaReq.bits.write) val s1_meta_uncorrected = s1_meta.map(tECC.decode(_).uncorrected.asTypeOf(new L1Metadata)) val s1_tag = s1_paddr >> tagLSB val s1_meta_hit_way = s1_meta_uncorrected.map(r => r.coh.isValid() && r.tag === s1_tag).asUInt val s1_meta_hit_state = ( s1_meta_uncorrected.map(r => Mux(r.tag === s1_tag && !s1_flush_valid, r.coh.asUInt, 0.U)) .reduce (_|_)).asTypeOf(chiselTypeOf(ClientMetadata.onReset)) (s1_meta_hit_way, s1_meta_hit_state, s1_meta) } val s1_data_way = WireDefault(if (nWays == 1) 1.U else Mux(inWriteback, releaseWay, s1_hit_way)) val tl_d_data_encoded = Wire(chiselTypeOf(encodeData(tl_out.d.bits.data, false.B))) val s1_all_data_ways = VecInit(data.io.resp ++ (!cacheParams.separateUncachedResp).option(tl_d_data_encoded)) val s1_mask_xwr = new StoreGen(s1_req.size, s1_req.addr, 0.U, wordBytes).mask val s1_mask = Mux(s1_req.cmd === M_PWR, io.cpu.s1_data.mask, s1_mask_xwr) // for partial writes, s1_data.mask must be a subset of s1_mask_xwr assert(!(s1_valid_masked && s1_req.cmd === M_PWR) || (s1_mask_xwr | ~io.cpu.s1_data.mask).andR) val s2_valid = RegNext(s1_valid_masked && !s1_sfence, init=false.B) val s2_valid_no_xcpt = s2_valid && !io.cpu.s2_xcpt.asUInt.orR val s2_probe = RegNext(s1_probe, init=false.B) val releaseInFlight = s1_probe || s2_probe || release_state =/= s_ready val s2_not_nacked_in_s1 = RegNext(!s1_nack) val s2_valid_not_nacked_in_s1 = s2_valid && s2_not_nacked_in_s1 val s2_valid_masked = s2_valid_no_xcpt && s2_not_nacked_in_s1 val s2_valid_not_killed = s2_valid_masked && !io.cpu.s2_kill val s2_req = Reg(chiselTypeOf(io.cpu.req.bits)) val s2_cmd_flush_all = s2_req.cmd === M_FLUSH_ALL && !s2_req.size(0) val s2_cmd_flush_line = s2_req.cmd === M_FLUSH_ALL && s2_req.size(0) val s2_tlb_xcpt = Reg(chiselTypeOf(tlb.io.resp)) val s2_pma = Reg(chiselTypeOf(tlb.io.resp)) val s2_uncached_resp_addr = Reg(chiselTypeOf(s2_req.addr)) // should be DCE'd in synthesis when (s1_valid_not_nacked || s1_flush_valid) { s2_req := s1_req s2_req.addr := s1_paddr s2_tlb_xcpt := tlb.io.resp s2_pma := Mux(s1_tlb_req_valid, pma_checker.io.resp, tlb.io.resp) } val s2_vaddr = Cat(RegEnable(s1_vaddr, s1_valid_not_nacked || s1_flush_valid) >> tagLSB, s2_req.addr(tagLSB-1, 0)) val s2_read = isRead(s2_req.cmd) val s2_write = isWrite(s2_req.cmd) val s2_readwrite = s2_read || s2_write val s2_flush_valid_pre_tag_ecc = RegNext(s1_flush_valid) val s1_meta_decoded = s1_meta.map(tECC.decode(_)) val s1_meta_clk_en = s1_valid_not_nacked || s1_flush_valid || s1_probe val s2_meta_correctable_errors = s1_meta_decoded.map(m => RegEnable(m.correctable, s1_meta_clk_en)).asUInt val s2_meta_uncorrectable_errors = s1_meta_decoded.map(m => RegEnable(m.uncorrectable, s1_meta_clk_en)).asUInt val s2_meta_error_uncorrectable = s2_meta_uncorrectable_errors.orR val s2_meta_corrected = s1_meta_decoded.map(m => RegEnable(m.corrected, s1_meta_clk_en).asTypeOf(new L1Metadata)) val s2_meta_error = (s2_meta_uncorrectable_errors | s2_meta_correctable_errors).orR val s2_flush_valid = s2_flush_valid_pre_tag_ecc && !s2_meta_error val s2_data = { val wordsPerRow = rowBits / subWordBits val en = s1_valid || inWriteback || io.cpu.replay_next val word_en = Mux(inWriteback, Fill(wordsPerRow, 1.U), Mux(s1_did_read, s1_read_mask, 0.U)) val s1_way_words = s1_all_data_ways.map(_.grouped(dECC.width(eccBits) * (subWordBits / eccBits))) if (cacheParams.pipelineWayMux) { val s1_word_en = Mux(io.cpu.replay_next, 0.U, word_en) (for (i <- 0 until wordsPerRow) yield { val s2_way_en = RegEnable(Mux(s1_word_en(i), s1_data_way, 0.U), en) val s2_way_words = (0 until nWays).map(j => RegEnable(s1_way_words(j)(i), en && word_en(i))) (0 until nWays).map(j => Mux(s2_way_en(j), s2_way_words(j), 0.U)).reduce(_|_) }).asUInt } else { val s1_word_en = Mux(!io.cpu.replay_next, word_en, UIntToOH(uncachedResp.addr.extract(log2Up(rowBits/8)-1, log2Up(wordBytes)), wordsPerRow)) (for (i <- 0 until wordsPerRow) yield { RegEnable(Mux1H(Mux(s1_word_en(i), s1_data_way, 0.U), s1_way_words.map(_(i))), en) }).asUInt } } val s2_probe_way = RegEnable(s1_hit_way, s1_probe) val s2_probe_state = RegEnable(s1_hit_state, s1_probe) val s2_hit_way = RegEnable(s1_hit_way, s1_valid_not_nacked) val s2_hit_state = RegEnable(s1_hit_state, s1_valid_not_nacked || s1_flush_valid) val s2_waw_hazard = RegEnable(s1_waw_hazard, s1_valid_not_nacked) val s2_store_merge = Wire(Bool()) val s2_hit_valid = s2_hit_state.isValid() val (s2_hit, s2_grow_param, s2_new_hit_state) = s2_hit_state.onAccess(s2_req.cmd) val s2_data_decoded = decodeData(s2_data) val s2_word_idx = s2_req.addr.extract(log2Up(rowBits/8)-1, log2Up(wordBytes)) val s2_data_error = s2_data_decoded.map(_.error).orR val s2_data_error_uncorrectable = s2_data_decoded.map(_.uncorrectable).orR val s2_data_corrected = (s2_data_decoded.map(_.corrected): Seq[UInt]).asUInt val s2_data_uncorrected = (s2_data_decoded.map(_.uncorrected): Seq[UInt]).asUInt val s2_valid_hit_maybe_flush_pre_data_ecc_and_waw = s2_valid_masked && !s2_meta_error && s2_hit val s2_no_alloc_hazard = if (!usingVM || pgIdxBits >= untagBits) false.B else { // make sure that any in-flight non-allocating accesses are ordered before // any allocating accesses. this can only happen if aliasing is possible. val any_no_alloc_in_flight = Reg(Bool()) when (!uncachedInFlight.asUInt.orR) { any_no_alloc_in_flight := false.B } when (s2_valid && s2_req.no_alloc) { any_no_alloc_in_flight := true.B } val s1_need_check = any_no_alloc_in_flight || s2_valid && s2_req.no_alloc val concerns = (uncachedInFlight zip uncachedReqs) :+ (s2_valid && s2_req.no_alloc, s2_req) val s1_uncached_hits = concerns.map { c => val concern_wmask = new StoreGen(c._2.size, c._2.addr, 0.U, wordBytes).mask val addr_match = (c._2.addr ^ s1_paddr)(pgIdxBits+pgLevelBits-1, wordBytes.log2) === 0.U val mask_match = (concern_wmask & s1_mask_xwr).orR || c._2.cmd === M_PWR || s1_req.cmd === M_PWR val cmd_match = isWrite(c._2.cmd) || isWrite(s1_req.cmd) c._1 && s1_need_check && cmd_match && addr_match && mask_match } val s2_uncached_hits = RegEnable(s1_uncached_hits.asUInt, s1_valid_not_nacked) s2_uncached_hits.orR } val s2_valid_hit_pre_data_ecc_and_waw = s2_valid_hit_maybe_flush_pre_data_ecc_and_waw && s2_readwrite && !s2_no_alloc_hazard val s2_valid_flush_line = s2_valid_hit_maybe_flush_pre_data_ecc_and_waw && s2_cmd_flush_line val s2_valid_hit_pre_data_ecc = s2_valid_hit_pre_data_ecc_and_waw && (!s2_waw_hazard || s2_store_merge) val s2_valid_data_error = s2_valid_hit_pre_data_ecc_and_waw && s2_data_error val s2_valid_hit = s2_valid_hit_pre_data_ecc && !s2_data_error val s2_valid_miss = s2_valid_masked && s2_readwrite && !s2_meta_error && !s2_hit val s2_uncached = !s2_pma.cacheable || s2_req.no_alloc && !s2_pma.must_alloc && !s2_hit_valid val s2_valid_cached_miss = s2_valid_miss && !s2_uncached && !uncachedInFlight.asUInt.orR dontTouch(s2_valid_cached_miss) val s2_want_victimize = (!usingDataScratchpad).B && (s2_valid_cached_miss || s2_valid_flush_line || s2_valid_data_error || s2_flush_valid) val s2_cannot_victimize = !s2_flush_valid && io.cpu.s2_kill val s2_victimize = s2_want_victimize && !s2_cannot_victimize val s2_valid_uncached_pending = s2_valid_miss && s2_uncached && !uncachedInFlight.asUInt.andR val s2_victim_way = UIntToOH(RegEnable(s1_victim_way, s1_valid_not_nacked || s1_flush_valid)) val s2_victim_or_hit_way = Mux(s2_hit_valid, s2_hit_way, s2_victim_way) val s2_victim_tag = Mux(s2_valid_data_error || s2_valid_flush_line, s2_req.addr(paddrBits-1, tagLSB), Mux1H(s2_victim_way, s2_meta_corrected).tag) val s2_victim_state = Mux(s2_hit_valid, s2_hit_state, Mux1H(s2_victim_way, s2_meta_corrected).coh) val (s2_prb_ack_data, s2_report_param, probeNewCoh)= s2_probe_state.onProbe(probe_bits.param) val (s2_victim_dirty, s2_shrink_param, voluntaryNewCoh) = s2_victim_state.onCacheControl(M_FLUSH) dontTouch(s2_victim_dirty) val s2_update_meta = s2_hit_state =/= s2_new_hit_state val s2_dont_nack_uncached = s2_valid_uncached_pending && tl_out_a.ready val s2_dont_nack_misc = s2_valid_masked && !s2_meta_error && (supports_flush.B && s2_cmd_flush_all && flushed && !flushing || supports_flush.B && s2_cmd_flush_line && !s2_hit || s2_req.cmd === M_WOK) io.cpu.s2_nack := s2_valid_no_xcpt && !s2_dont_nack_uncached && !s2_dont_nack_misc && !s2_valid_hit when (io.cpu.s2_nack || (s2_valid_hit_pre_data_ecc_and_waw && s2_update_meta)) { s1_nack := true.B } // tag updates on ECC errors val s2_first_meta_corrected = PriorityMux(s2_meta_correctable_errors, s2_meta_corrected) metaArb.io.in(1).valid := s2_meta_error && (s2_valid_masked || s2_flush_valid_pre_tag_ecc || s2_probe) metaArb.io.in(1).bits.write := true.B metaArb.io.in(1).bits.way_en := s2_meta_uncorrectable_errors | Mux(s2_meta_error_uncorrectable, 0.U, PriorityEncoderOH(s2_meta_correctable_errors)) metaArb.io.in(1).bits.idx := Mux(s2_probe, probeIdx(probe_bits), s2_vaddr(idxMSB, idxLSB)) metaArb.io.in(1).bits.addr := Cat(io.cpu.req.bits.addr >> untagBits, metaArb.io.in(1).bits.idx << blockOffBits) metaArb.io.in(1).bits.data := tECC.encode { val new_meta = WireDefault(s2_first_meta_corrected) when (s2_meta_error_uncorrectable) { new_meta.coh := ClientMetadata.onReset } new_meta.asUInt } // tag updates on hit metaArb.io.in(2).valid := s2_valid_hit_pre_data_ecc_and_waw && s2_update_meta metaArb.io.in(2).bits.write := !io.cpu.s2_kill metaArb.io.in(2).bits.way_en := s2_victim_or_hit_way metaArb.io.in(2).bits.idx := s2_vaddr(idxMSB, idxLSB) metaArb.io.in(2).bits.addr := Cat(io.cpu.req.bits.addr >> untagBits, s2_vaddr(idxMSB, 0)) metaArb.io.in(2).bits.data := tECC.encode(L1Metadata(s2_req.addr >> tagLSB, s2_new_hit_state).asUInt) // load reservations and TL error reporting val s2_lr = (usingAtomics && !usingDataScratchpad).B && s2_req.cmd === M_XLR val s2_sc = (usingAtomics && !usingDataScratchpad).B && s2_req.cmd === M_XSC val lrscCount = RegInit(0.U) val lrscValid = lrscCount > lrscBackoff.U val lrscBackingOff = lrscCount > 0.U && !lrscValid val lrscAddr = Reg(UInt()) val lrscAddrMatch = lrscAddr === (s2_req.addr >> blockOffBits) val s2_sc_fail = s2_sc && !(lrscValid && lrscAddrMatch) when ((s2_valid_hit && s2_lr && !cached_grant_wait || s2_valid_cached_miss) && !io.cpu.s2_kill) { lrscCount := Mux(s2_hit, (lrscCycles - 1).U, 0.U) lrscAddr := s2_req.addr >> blockOffBits } when (lrscCount > 0.U) { lrscCount := lrscCount - 1.U } when (s2_valid_not_killed && lrscValid) { lrscCount := lrscBackoff.U } when (s1_probe) { lrscCount := 0.U } // don't perform data correction if it might clobber a recent store val s2_correct = s2_data_error && !any_pstore_valid && !RegNext(any_pstore_valid || s2_valid) && usingDataScratchpad.B // pending store buffer val s2_valid_correct = s2_valid_hit_pre_data_ecc_and_waw && s2_correct && !io.cpu.s2_kill def s2_store_valid_pre_kill = s2_valid_hit && s2_write && !s2_sc_fail def s2_store_valid = s2_store_valid_pre_kill && !io.cpu.s2_kill val pstore1_cmd = RegEnable(s1_req.cmd, s1_valid_not_nacked && s1_write) val pstore1_addr = RegEnable(s1_vaddr, s1_valid_not_nacked && s1_write) val pstore1_data = RegEnable(io.cpu.s1_data.data, s1_valid_not_nacked && s1_write) val pstore1_way = RegEnable(s1_hit_way, s1_valid_not_nacked && s1_write) val pstore1_mask = RegEnable(s1_mask, s1_valid_not_nacked && s1_write) val pstore1_storegen_data = WireDefault(pstore1_data) val pstore1_rmw = usingRMW.B && RegEnable(needsRead(s1_req), s1_valid_not_nacked && s1_write) val pstore1_merge_likely = s2_valid_not_nacked_in_s1 && s2_write && s2_store_merge val pstore1_merge = s2_store_valid && s2_store_merge val pstore2_valid = RegInit(false.B) val pstore_drain_opportunistic = !(io.cpu.req.valid && likelyNeedsRead(io.cpu.req.bits)) && !(s1_valid && s1_waw_hazard) val pstore_drain_on_miss = releaseInFlight || RegNext(io.cpu.s2_nack) val pstore1_held = RegInit(false.B) val pstore1_valid_likely = s2_valid && s2_write || pstore1_held def pstore1_valid_not_rmw(s2_kill: Bool) = s2_valid_hit_pre_data_ecc && s2_write && !s2_kill || pstore1_held val pstore1_valid = s2_store_valid || pstore1_held any_pstore_valid := pstore1_held || pstore2_valid val pstore_drain_structural = pstore1_valid_likely && pstore2_valid && ((s1_valid && s1_write) || pstore1_rmw) assert(pstore1_rmw || pstore1_valid_not_rmw(io.cpu.s2_kill) === pstore1_valid) ccover(pstore_drain_structural, "STORE_STRUCTURAL_HAZARD", "D$ read-modify-write structural hazard") ccover(pstore1_valid && pstore_drain_on_miss, "STORE_DRAIN_ON_MISS", "D$ store buffer drain on miss") ccover(s1_valid_not_nacked && s1_waw_hazard, "WAW_HAZARD", "D$ write-after-write hazard") def should_pstore_drain(truly: Bool) = { val s2_kill = truly && io.cpu.s2_kill !pstore1_merge_likely && (usingRMW.B && pstore_drain_structural || (((pstore1_valid_not_rmw(s2_kill) && !pstore1_rmw) || pstore2_valid) && (pstore_drain_opportunistic || pstore_drain_on_miss))) } val pstore_drain = should_pstore_drain(true.B) pstore1_held := (s2_store_valid && !s2_store_merge || pstore1_held) && pstore2_valid && !pstore_drain val advance_pstore1 = (pstore1_valid || s2_valid_correct) && (pstore2_valid === pstore_drain) pstore2_valid := pstore2_valid && !pstore_drain || advance_pstore1 val pstore2_addr = RegEnable(Mux(s2_correct, s2_vaddr, pstore1_addr), advance_pstore1) val pstore2_way = RegEnable(Mux(s2_correct, s2_hit_way, pstore1_way), advance_pstore1) val pstore2_storegen_data = { for (i <- 0 until wordBytes) yield RegEnable(pstore1_storegen_data(8*(i+1)-1, 8*i), advance_pstore1 || pstore1_merge && pstore1_mask(i)) }.asUInt val pstore2_storegen_mask = { val mask = Reg(UInt(wordBytes.W)) when (advance_pstore1 || pstore1_merge) { val mergedMask = pstore1_mask | Mux(pstore1_merge, mask, 0.U) mask := ~Mux(s2_correct, 0.U, ~mergedMask) } mask } s2_store_merge := (if (eccBytes == 1) false.B else { ccover(pstore1_merge, "STORE_MERGED", "D$ store merged") // only merge stores to ECC granules that are already stored-to, to avoid // WAW hazards val wordMatch = (eccMask(pstore2_storegen_mask) | ~eccMask(pstore1_mask)).andR val idxMatch = s2_vaddr(untagBits-1, log2Ceil(wordBytes)) === pstore2_addr(untagBits-1, log2Ceil(wordBytes)) val tagMatch = (s2_hit_way & pstore2_way).orR pstore2_valid && wordMatch && idxMatch && tagMatch }) dataArb.io.in(0).valid := should_pstore_drain(false.B) dataArb.io.in(0).bits.write := pstore_drain dataArb.io.in(0).bits.addr := Mux(pstore2_valid, pstore2_addr, pstore1_addr) dataArb.io.in(0).bits.way_en := Mux(pstore2_valid, pstore2_way, pstore1_way) dataArb.io.in(0).bits.wdata := encodeData(Fill(rowWords, Mux(pstore2_valid, pstore2_storegen_data, pstore1_data)), false.B) dataArb.io.in(0).bits.wordMask := { val eccMask = dataArb.io.in(0).bits.eccMask.asBools.grouped(subWordBytes/eccBytes).map(_.orR).toSeq.asUInt val wordMask = UIntToOH(Mux(pstore2_valid, pstore2_addr, pstore1_addr).extract(rowOffBits-1, wordBytes.log2)) FillInterleaved(wordBytes/subWordBytes, wordMask) & Fill(rowBytes/wordBytes, eccMask) } dataArb.io.in(0).bits.eccMask := eccMask(Mux(pstore2_valid, pstore2_storegen_mask, pstore1_mask)) // store->load RAW hazard detection def s1Depends(addr: UInt, mask: UInt) = addr(idxMSB, wordOffBits) === s1_vaddr(idxMSB, wordOffBits) && Mux(s1_write, (eccByteMask(mask) & eccByteMask(s1_mask_xwr)).orR, (mask & s1_mask_xwr).orR) val s1_hazard = (pstore1_valid_likely && s1Depends(pstore1_addr, pstore1_mask)) || (pstore2_valid && s1Depends(pstore2_addr, pstore2_storegen_mask)) val s1_raw_hazard = s1_read && s1_hazard s1_waw_hazard := (if (eccBytes == 1) false.B else { ccover(s1_valid_not_nacked && s1_waw_hazard, "WAW_HAZARD", "D$ write-after-write hazard") s1_write && (s1_hazard || needsRead(s1_req) && !s1_did_read) }) when (s1_valid && s1_raw_hazard) { s1_nack := true.B } // performance hints to processor io.cpu.s2_nack_cause_raw := RegNext(s1_raw_hazard) || !(!s2_waw_hazard || s2_store_merge) // Prepare a TileLink request message that initiates a transaction val a_source = PriorityEncoder(~uncachedInFlight.asUInt << mmioOffset) // skip the MSHR val acquire_address = (s2_req.addr >> idxLSB) << idxLSB val access_address = s2_req.addr val a_size = s2_req.size val a_data = Fill(beatWords, pstore1_data) val a_mask = pstore1_mask << (access_address.extract(beatBytes.log2-1, wordBytes.log2) << 3) val get = edge.Get(a_source, access_address, a_size)._2 val put = edge.Put(a_source, access_address, a_size, a_data)._2 val putpartial = edge.Put(a_source, access_address, a_size, a_data, a_mask)._2 val atomics = if (edge.manager.anySupportLogical) { MuxLookup(s2_req.cmd, WireDefault(0.U.asTypeOf(new TLBundleA(edge.bundle))))(Array( M_XA_SWAP -> edge.Logical(a_source, access_address, a_size, a_data, TLAtomics.SWAP)._2, M_XA_XOR -> edge.Logical(a_source, access_address, a_size, a_data, TLAtomics.XOR) ._2, M_XA_OR -> edge.Logical(a_source, access_address, a_size, a_data, TLAtomics.OR) ._2, M_XA_AND -> edge.Logical(a_source, access_address, a_size, a_data, TLAtomics.AND) ._2, M_XA_ADD -> edge.Arithmetic(a_source, access_address, a_size, a_data, TLAtomics.ADD)._2, M_XA_MIN -> edge.Arithmetic(a_source, access_address, a_size, a_data, TLAtomics.MIN)._2, M_XA_MAX -> edge.Arithmetic(a_source, access_address, a_size, a_data, TLAtomics.MAX)._2, M_XA_MINU -> edge.Arithmetic(a_source, access_address, a_size, a_data, TLAtomics.MINU)._2, M_XA_MAXU -> edge.Arithmetic(a_source, access_address, a_size, a_data, TLAtomics.MAXU)._2)) } else { // If no managers support atomics, assert fail if processor asks for them assert (!(tl_out_a.valid && s2_read && s2_write && s2_uncached)) WireDefault(new TLBundleA(edge.bundle), DontCare) } tl_out_a.valid := !io.cpu.s2_kill && (s2_valid_uncached_pending || (s2_valid_cached_miss && !(release_ack_wait && (s2_req.addr ^ release_ack_addr)(((pgIdxBits + pgLevelBits) min paddrBits) - 1, idxLSB) === 0.U) && (cacheParams.acquireBeforeRelease.B && !release_ack_wait && release_queue_empty || !s2_victim_dirty))) tl_out_a.bits := Mux(!s2_uncached, acquire(s2_vaddr, s2_req.addr, s2_grow_param), Mux(!s2_write, get, Mux(s2_req.cmd === M_PWR, putpartial, Mux(!s2_read, put, atomics)))) // Drive APROT Bits tl_out_a.bits.user.lift(AMBAProt).foreach { x => val user_bit_cacheable = s2_pma.cacheable x.privileged := s2_req.dprv === PRV.M.U || user_bit_cacheable // if the address is cacheable, enable outer caches x.bufferable := user_bit_cacheable x.modifiable := user_bit_cacheable x.readalloc := user_bit_cacheable x.writealloc := user_bit_cacheable // Following are always tied off x.fetch := false.B x.secure := true.B } // Set pending bits for outstanding TileLink transaction val a_sel = UIntToOH(a_source, maxUncachedInFlight+mmioOffset) >> mmioOffset when (tl_out_a.fire) { when (s2_uncached) { (a_sel.asBools zip (uncachedInFlight zip uncachedReqs)) foreach { case (s, (f, r)) => when (s) { f := true.B r := s2_req r.cmd := Mux(s2_write, Mux(s2_req.cmd === M_PWR, M_PWR, M_XWR), M_XRD) } } }.otherwise { cached_grant_wait := true.B refill_way := s2_victim_or_hit_way } } // grant val (d_first, d_last, d_done, d_address_inc) = edge.addr_inc(tl_out.d) val (d_opc, grantIsUncached, grantIsUncachedData) = { val uncachedGrantOpcodesSansData = Seq(AccessAck, HintAck) val uncachedGrantOpcodesWithData = Seq(AccessAckData) val uncachedGrantOpcodes = uncachedGrantOpcodesWithData ++ uncachedGrantOpcodesSansData val whole_opc = tl_out.d.bits.opcode if (usingDataScratchpad) { assert(!tl_out.d.valid || whole_opc.isOneOf(uncachedGrantOpcodes)) // the only valid TL-D messages are uncached, so we can do some pruning val opc = whole_opc(uncachedGrantOpcodes.map(_.getWidth).max - 1, 0) val data = DecodeLogic(opc, uncachedGrantOpcodesWithData, uncachedGrantOpcodesSansData) (opc, true.B, data) } else { (whole_opc, whole_opc.isOneOf(uncachedGrantOpcodes), whole_opc.isOneOf(uncachedGrantOpcodesWithData)) } } tl_d_data_encoded := encodeData(tl_out.d.bits.data, tl_out.d.bits.corrupt && !io.ptw.customCSRs.suppressCorruptOnGrantData && !grantIsUncached) val grantIsCached = d_opc.isOneOf(Grant, GrantData) val grantIsVoluntary = d_opc === ReleaseAck // Clears a different pending bit val grantIsRefill = d_opc === GrantData // Writes the data array val grantInProgress = RegInit(false.B) val blockProbeAfterGrantCount = RegInit(0.U) when (blockProbeAfterGrantCount > 0.U) { blockProbeAfterGrantCount := blockProbeAfterGrantCount - 1.U } val canAcceptCachedGrant = !release_state.isOneOf(s_voluntary_writeback, s_voluntary_write_meta, s_voluntary_release) tl_out.d.ready := Mux(grantIsCached, (!d_first || tl_out.e.ready) && canAcceptCachedGrant, true.B) val uncachedRespIdxOH = UIntToOH(tl_out.d.bits.source, maxUncachedInFlight+mmioOffset) >> mmioOffset uncachedResp := Mux1H(uncachedRespIdxOH, uncachedReqs) when (tl_out.d.fire) { when (grantIsCached) { grantInProgress := true.B assert(cached_grant_wait, "A GrantData was unexpected by the dcache.") when(d_last) { cached_grant_wait := false.B grantInProgress := false.B blockProbeAfterGrantCount := (blockProbeAfterGrantCycles - 1).U replacer.miss } } .elsewhen (grantIsUncached) { (uncachedRespIdxOH.asBools zip uncachedInFlight) foreach { case (s, f) => when (s && d_last) { assert(f, "An AccessAck was unexpected by the dcache.") // TODO must handle Ack coming back on same cycle! f := false.B } } when (grantIsUncachedData) { if (!cacheParams.separateUncachedResp) { if (!cacheParams.pipelineWayMux) s1_data_way := 1.U << nWays s2_req.cmd := M_XRD s2_req.size := uncachedResp.size s2_req.signed := uncachedResp.signed s2_req.tag := uncachedResp.tag s2_req.addr := { require(rowOffBits >= beatOffBits) val dontCareBits = s1_paddr >> rowOffBits << rowOffBits dontCareBits | uncachedResp.addr(beatOffBits-1, 0) } s2_uncached_resp_addr := uncachedResp.addr } } } .elsewhen (grantIsVoluntary) { assert(release_ack_wait, "A ReleaseAck was unexpected by the dcache.") // TODO should handle Ack coming back on same cycle! release_ack_wait := false.B } } // Finish TileLink transaction by issuing a GrantAck tl_out.e.valid := tl_out.d.valid && d_first && grantIsCached && canAcceptCachedGrant tl_out.e.bits := edge.GrantAck(tl_out.d.bits) assert(tl_out.e.fire === (tl_out.d.fire && d_first && grantIsCached)) // data refill // note this ready-valid signaling ignores E-channel backpressure, which // benignly means the data RAM might occasionally be redundantly written dataArb.io.in(1).valid := tl_out.d.valid && grantIsRefill && canAcceptCachedGrant when (grantIsRefill && !dataArb.io.in(1).ready) { tl_out.e.valid := false.B tl_out.d.ready := false.B } if (!usingDataScratchpad) { dataArb.io.in(1).bits.write := true.B dataArb.io.in(1).bits.addr := (s2_vaddr >> idxLSB) << idxLSB | d_address_inc dataArb.io.in(1).bits.way_en := refill_way dataArb.io.in(1).bits.wdata := tl_d_data_encoded dataArb.io.in(1).bits.wordMask := ~0.U((rowBytes / subWordBytes).W) dataArb.io.in(1).bits.eccMask := ~0.U((wordBytes / eccBytes).W) } else { dataArb.io.in(1).bits := dataArb.io.in(0).bits } // tag updates on refill // ignore backpressure from metaArb, which can only be caused by tag ECC // errors on hit-under-miss. failing to write the new tag will leave the // line invalid, so we'll simply request the line again later. metaArb.io.in(3).valid := grantIsCached && d_done && !tl_out.d.bits.denied metaArb.io.in(3).bits.write := true.B metaArb.io.in(3).bits.way_en := refill_way metaArb.io.in(3).bits.idx := s2_vaddr(idxMSB, idxLSB) metaArb.io.in(3).bits.addr := Cat(io.cpu.req.bits.addr >> untagBits, s2_vaddr(idxMSB, 0)) metaArb.io.in(3).bits.data := tECC.encode(L1Metadata(s2_req.addr >> tagLSB, s2_hit_state.onGrant(s2_req.cmd, tl_out.d.bits.param)).asUInt) if (!cacheParams.separateUncachedResp) { // don't accept uncached grants if there's a structural hazard on s2_data... val blockUncachedGrant = Reg(Bool()) blockUncachedGrant := dataArb.io.out.valid when (grantIsUncachedData && (blockUncachedGrant || s1_valid)) { tl_out.d.ready := false.B // ...but insert bubble to guarantee grant's eventual forward progress when (tl_out.d.valid) { io.cpu.req.ready := false.B dataArb.io.in(1).valid := true.B dataArb.io.in(1).bits.write := false.B blockUncachedGrant := !dataArb.io.in(1).ready } } } ccover(tl_out.d.valid && !tl_out.d.ready, "BLOCK_D", "D$ D-channel blocked") // Handle an incoming TileLink Probe message val block_probe_for_core_progress = blockProbeAfterGrantCount > 0.U || lrscValid val block_probe_for_pending_release_ack = release_ack_wait && (tl_out.b.bits.address ^ release_ack_addr)(((pgIdxBits + pgLevelBits) min paddrBits) - 1, idxLSB) === 0.U val block_probe_for_ordering = releaseInFlight || block_probe_for_pending_release_ack || grantInProgress metaArb.io.in(6).valid := tl_out.b.valid && (!block_probe_for_core_progress || lrscBackingOff) tl_out.b.ready := metaArb.io.in(6).ready && !(block_probe_for_core_progress || block_probe_for_ordering || s1_valid || s2_valid) metaArb.io.in(6).bits.write := false.B metaArb.io.in(6).bits.idx := probeIdx(tl_out.b.bits) metaArb.io.in(6).bits.addr := Cat(io.cpu.req.bits.addr >> paddrBits, tl_out.b.bits.address) metaArb.io.in(6).bits.way_en := metaArb.io.in(4).bits.way_en metaArb.io.in(6).bits.data := metaArb.io.in(4).bits.data // replacement policy s1_victim_way := (if (replacer.perSet && nWays > 1) { val repl_array = Mem(nSets, UInt(replacer.nBits.W)) val s1_repl_idx = s1_req.addr(idxBits+blockOffBits-1, blockOffBits) val s2_repl_idx = s2_vaddr(idxBits+blockOffBits-1, blockOffBits) val s2_repl_state = Reg(UInt(replacer.nBits.W)) val s2_new_repl_state = replacer.get_next_state(s2_repl_state, OHToUInt(s2_hit_way)) val s2_repl_wen = s2_valid_masked && s2_hit_way.orR && s2_repl_state =/= s2_new_repl_state val s1_repl_state = Mux(s2_repl_wen && s2_repl_idx === s1_repl_idx, s2_new_repl_state, repl_array(s1_repl_idx)) when (s1_valid_not_nacked) { s2_repl_state := s1_repl_state } val waddr = Mux(resetting, flushCounter(idxBits-1, 0), s2_repl_idx) val wdata = Mux(resetting, 0.U, s2_new_repl_state) val wen = resetting || s2_repl_wen when (wen) { repl_array(waddr) := wdata } replacer.get_replace_way(s1_repl_state) } else { replacer.way }) // release val (c_first, c_last, releaseDone, c_count) = edge.count(tl_out_c) val releaseRejected = Wire(Bool()) val s1_release_data_valid = RegNext(dataArb.io.in(2).fire) val s2_release_data_valid = RegNext(s1_release_data_valid && !releaseRejected) releaseRejected := s2_release_data_valid && !tl_out_c.fire val releaseDataBeat = Cat(0.U, c_count) + Mux(releaseRejected, 0.U, s1_release_data_valid + Cat(0.U, s2_release_data_valid)) val nackResponseMessage = edge.ProbeAck(b = probe_bits, reportPermissions = TLPermissions.NtoN) val cleanReleaseMessage = edge.ProbeAck(b = probe_bits, reportPermissions = s2_report_param) val dirtyReleaseMessage = edge.ProbeAck(b = probe_bits, reportPermissions = s2_report_param, data = 0.U) tl_out_c.valid := (s2_release_data_valid || (!cacheParams.silentDrop.B && release_state === s_voluntary_release)) && !(c_first && release_ack_wait) tl_out_c.bits := nackResponseMessage val newCoh = WireDefault(probeNewCoh) releaseWay := s2_probe_way if (!usingDataScratchpad) { when (s2_victimize) { assert(s2_valid_flush_line || s2_flush_valid || io.cpu.s2_nack) val discard_line = s2_valid_flush_line && s2_req.size(1) || s2_flush_valid && flushing_req.size(1) release_state := Mux(s2_victim_dirty && !discard_line, s_voluntary_writeback, Mux(!cacheParams.silentDrop.B && !release_ack_wait && release_queue_empty && s2_victim_state.isValid() && (s2_valid_flush_line || s2_flush_valid || s2_readwrite && !s2_hit_valid), s_voluntary_release, s_voluntary_write_meta)) probe_bits := addressToProbe(s2_vaddr, Cat(s2_victim_tag, s2_req.addr(tagLSB-1, idxLSB)) << idxLSB) } when (s2_probe) { val probeNack = WireDefault(true.B) when (s2_meta_error) { release_state := s_probe_retry }.elsewhen (s2_prb_ack_data) { release_state := s_probe_rep_dirty }.elsewhen (s2_probe_state.isValid()) { tl_out_c.valid := true.B tl_out_c.bits := cleanReleaseMessage release_state := Mux(releaseDone, s_probe_write_meta, s_probe_rep_clean) }.otherwise { tl_out_c.valid := true.B probeNack := !releaseDone release_state := Mux(releaseDone, s_ready, s_probe_rep_miss) } when (probeNack) { s1_nack := true.B } } when (release_state === s_probe_retry) { metaArb.io.in(6).valid := true.B metaArb.io.in(6).bits.idx := probeIdx(probe_bits) metaArb.io.in(6).bits.addr := Cat(io.cpu.req.bits.addr >> paddrBits, probe_bits.address) when (metaArb.io.in(6).ready) { release_state := s_ready s1_probe := true.B } } when (release_state === s_probe_rep_miss) { tl_out_c.valid := true.B when (releaseDone) { release_state := s_ready } } when (release_state === s_probe_rep_clean) { tl_out_c.valid := true.B tl_out_c.bits := cleanReleaseMessage when (releaseDone) { release_state := s_probe_write_meta } } when (release_state === s_probe_rep_dirty) { tl_out_c.bits := dirtyReleaseMessage when (releaseDone) { release_state := s_probe_write_meta } } when (release_state.isOneOf(s_voluntary_writeback, s_voluntary_write_meta, s_voluntary_release)) { when (release_state === s_voluntary_release) { tl_out_c.bits := edge.Release(fromSource = 0.U, toAddress = 0.U, lgSize = lgCacheBlockBytes.U, shrinkPermissions = s2_shrink_param)._2 }.otherwise { tl_out_c.bits := edge.Release(fromSource = 0.U, toAddress = 0.U, lgSize = lgCacheBlockBytes.U, shrinkPermissions = s2_shrink_param, data = 0.U)._2 } newCoh := voluntaryNewCoh releaseWay := s2_victim_or_hit_way when (releaseDone) { release_state := s_voluntary_write_meta } when (tl_out_c.fire && c_first) { release_ack_wait := true.B release_ack_addr := probe_bits.address } } tl_out_c.bits.source := probe_bits.source tl_out_c.bits.address := probe_bits.address tl_out_c.bits.data := s2_data_corrected tl_out_c.bits.corrupt := inWriteback && s2_data_error_uncorrectable } tl_out_c.bits.user.lift(AMBAProt).foreach { x => x.fetch := false.B x.secure := true.B x.privileged := true.B x.bufferable := true.B x.modifiable := true.B x.readalloc := true.B x.writealloc := true.B } dataArb.io.in(2).valid := inWriteback && releaseDataBeat < refillCycles.U dataArb.io.in(2).bits := dataArb.io.in(1).bits dataArb.io.in(2).bits.write := false.B dataArb.io.in(2).bits.addr := (probeIdx(probe_bits) << blockOffBits) | (releaseDataBeat(log2Up(refillCycles)-1,0) << rowOffBits) dataArb.io.in(2).bits.wordMask := ~0.U((rowBytes / subWordBytes).W) dataArb.io.in(2).bits.eccMask := ~0.U((wordBytes / eccBytes).W) dataArb.io.in(2).bits.way_en := ~0.U(nWays.W) metaArb.io.in(4).valid := release_state.isOneOf(s_voluntary_write_meta, s_probe_write_meta) metaArb.io.in(4).bits.write := true.B metaArb.io.in(4).bits.way_en := releaseWay metaArb.io.in(4).bits.idx := probeIdx(probe_bits) metaArb.io.in(4).bits.addr := Cat(io.cpu.req.bits.addr >> untagBits, probe_bits.address(idxMSB, 0)) metaArb.io.in(4).bits.data := tECC.encode(L1Metadata(tl_out_c.bits.address >> tagLSB, newCoh).asUInt) when (metaArb.io.in(4).fire) { release_state := s_ready } // cached response (io.cpu.resp.bits: Data).waiveAll :<>= (s2_req: Data).waiveAll io.cpu.resp.bits.has_data := s2_read io.cpu.resp.bits.replay := false.B io.cpu.s2_uncached := s2_uncached && !s2_hit io.cpu.s2_paddr := s2_req.addr io.cpu.s2_gpa := s2_tlb_xcpt.gpa io.cpu.s2_gpa_is_pte := s2_tlb_xcpt.gpa_is_pte // report whether there are any outstanding accesses. disregard any // slave-port accesses, since they don't affect local memory ordering. val s1_isSlavePortAccess = s1_req.no_xcpt val s2_isSlavePortAccess = s2_req.no_xcpt io.cpu.ordered := !(s1_valid && !s1_isSlavePortAccess || s2_valid && !s2_isSlavePortAccess || cached_grant_wait || uncachedInFlight.asUInt.orR) io.cpu.store_pending := (cached_grant_wait && isWrite(s2_req.cmd)) || uncachedInFlight.asUInt.orR val s1_xcpt_valid = tlb.io.req.valid && !s1_isSlavePortAccess && !s1_nack io.cpu.s2_xcpt := Mux(RegNext(s1_xcpt_valid), s2_tlb_xcpt, 0.U.asTypeOf(s2_tlb_xcpt)) if (usingDataScratchpad) { assert(!(s2_valid_masked && s2_req.cmd.isOneOf(M_XLR, M_XSC))) } else { ccover(tl_out.b.valid && !tl_out.b.ready, "BLOCK_B", "D$ B-channel blocked") } // uncached response val s1_uncached_data_word = { val word_idx = uncachedResp.addr.extract(log2Up(rowBits/8)-1, log2Up(wordBytes)) val words = tl_out.d.bits.data.grouped(wordBits) words(word_idx) } val s2_uncached_data_word = RegEnable(s1_uncached_data_word, io.cpu.replay_next) val doUncachedResp = RegNext(io.cpu.replay_next) io.cpu.resp.valid := (s2_valid_hit_pre_data_ecc || doUncachedResp) && !s2_data_error io.cpu.replay_next := tl_out.d.fire && grantIsUncachedData && !cacheParams.separateUncachedResp.B when (doUncachedResp) { assert(!s2_valid_hit) io.cpu.resp.bits.replay := true.B io.cpu.resp.bits.addr := s2_uncached_resp_addr } io.cpu.uncached_resp.map { resp => resp.valid := tl_out.d.valid && grantIsUncachedData resp.bits.tag := uncachedResp.tag resp.bits.size := uncachedResp.size resp.bits.signed := uncachedResp.signed resp.bits.data := new LoadGen(uncachedResp.size, uncachedResp.signed, uncachedResp.addr, s1_uncached_data_word, false.B, wordBytes).data resp.bits.data_raw := s1_uncached_data_word when (grantIsUncachedData && !resp.ready) { tl_out.d.ready := false.B } } // load data subword mux/sign extension val s2_data_word = (0 until rowBits by wordBits).map(i => s2_data_uncorrected(wordBits+i-1,i)).reduce(_|_) val s2_data_word_corrected = (0 until rowBits by wordBits).map(i => s2_data_corrected(wordBits+i-1,i)).reduce(_|_) val s2_data_word_possibly_uncached = Mux(cacheParams.pipelineWayMux.B && doUncachedResp, s2_uncached_data_word, 0.U) | s2_data_word val loadgen = new LoadGen(s2_req.size, s2_req.signed, s2_req.addr, s2_data_word_possibly_uncached, s2_sc, wordBytes) io.cpu.resp.bits.data := loadgen.data | s2_sc_fail io.cpu.resp.bits.data_word_bypass := loadgen.wordData io.cpu.resp.bits.data_raw := s2_data_word io.cpu.resp.bits.store_data := pstore1_data // AMOs if (usingRMW) { val amoalus = (0 until coreDataBits / xLen).map { i => val amoalu = Module(new AMOALU(xLen)) amoalu.io.mask := pstore1_mask >> (i * xBytes) amoalu.io.cmd := (if (usingAtomicsInCache) pstore1_cmd else M_XWR) amoalu.io.lhs := s2_data_word >> (i * xLen) amoalu.io.rhs := pstore1_data >> (i * xLen) amoalu } pstore1_storegen_data := (if (!usingDataScratchpad) amoalus.map(_.io.out).asUInt else { val mask = FillInterleaved(8, Mux(s2_correct, 0.U, pstore1_mask)) amoalus.map(_.io.out_unmasked).asUInt & mask | s2_data_word_corrected & ~mask }) } else if (!usingAtomics) { assert(!(s1_valid_masked && s1_read && s1_write), "unsupported D$ operation") } if (coreParams.useVector) { edge.manager.managers.foreach { m => // Statically ensure that no-allocate accesses are permitted. // We could consider turning some of these into dynamic PMA checks. require(!m.supportsAcquireB || m.supportsGet, "With a vector unit, cacheable memory must support Get") require(!m.supportsAcquireT || m.supportsPutPartial, "With a vector unit, cacheable memory must support PutPartial") } } // flushes if (!usingDataScratchpad) when (RegNext(reset.asBool)) { resetting := true.B } val flushCounterNext = flushCounter +& 1.U val flushDone = (flushCounterNext >> log2Ceil(nSets)) === nWays.U val flushCounterWrap = flushCounterNext(log2Ceil(nSets)-1, 0) ccover(s2_valid_masked && s2_cmd_flush_all && s2_meta_error, "TAG_ECC_ERROR_DURING_FENCE_I", "D$ ECC error in tag array during cache flush") ccover(s2_valid_masked && s2_cmd_flush_all && s2_data_error, "DATA_ECC_ERROR_DURING_FENCE_I", "D$ ECC error in data array during cache flush") s1_flush_valid := metaArb.io.in(5).fire && !s1_flush_valid && !s2_flush_valid_pre_tag_ecc && release_state === s_ready && !release_ack_wait metaArb.io.in(5).valid := flushing && !flushed metaArb.io.in(5).bits.write := false.B metaArb.io.in(5).bits.idx := flushCounter(idxBits-1, 0) metaArb.io.in(5).bits.addr := Cat(io.cpu.req.bits.addr >> untagBits, metaArb.io.in(5).bits.idx << blockOffBits) metaArb.io.in(5).bits.way_en := metaArb.io.in(4).bits.way_en metaArb.io.in(5).bits.data := metaArb.io.in(4).bits.data // Only flush D$ on FENCE.I if some cached executable regions are untracked. if (supports_flush) { when (s2_valid_masked && s2_cmd_flush_all) { when (!flushed && !io.cpu.s2_kill && !release_ack_wait && !uncachedInFlight.asUInt.orR) { flushing := true.B flushing_req := s2_req } } when (tl_out_a.fire && !s2_uncached) { flushed := false.B } when (flushing) { s1_victim_way := flushCounter >> log2Up(nSets) when (s2_flush_valid) { flushCounter := flushCounterNext when (flushDone) { flushed := true.B if (!isPow2(nWays)) flushCounter := flushCounterWrap } } when (flushed && release_state === s_ready && !release_ack_wait) { flushing := false.B } } } metaArb.io.in(0).valid := resetting metaArb.io.in(0).bits := metaArb.io.in(5).bits metaArb.io.in(0).bits.write := true.B metaArb.io.in(0).bits.way_en := ~0.U(nWays.W) metaArb.io.in(0).bits.data := tECC.encode(L1Metadata(0.U, ClientMetadata.onReset).asUInt) when (resetting) { flushCounter := flushCounterNext when (flushDone) { resetting := false.B if (!isPow2(nWays)) flushCounter := flushCounterWrap } } // gate the clock clock_en_reg := !cacheParams.clockGate.B || io.ptw.customCSRs.disableDCacheClockGate || io.cpu.keep_clock_enabled || metaArb.io.out.valid || // subsumes resetting || flushing s1_probe || s2_probe || s1_valid || s2_valid || io.tlb_port.req.valid || s1_tlb_req_valid || s2_tlb_req_valid || pstore1_held || pstore2_valid || release_state =/= s_ready || release_ack_wait || !release_queue_empty || !tlb.io.req.ready || cached_grant_wait || uncachedInFlight.asUInt.orR || lrscCount > 0.U || blockProbeAfterGrantCount > 0.U // performance events io.cpu.perf.acquire := edge.done(tl_out_a) io.cpu.perf.release := edge.done(tl_out_c) io.cpu.perf.grant := tl_out.d.valid && d_last io.cpu.perf.tlbMiss := io.ptw.req.fire io.cpu.perf.storeBufferEmptyAfterLoad := !( (s1_valid && s1_write) || ((s2_valid && s2_write && !s2_waw_hazard) || pstore1_held) || pstore2_valid) io.cpu.perf.storeBufferEmptyAfterStore := !( (s1_valid && s1_write) || (s2_valid && s2_write && pstore1_rmw) || ((s2_valid && s2_write && !s2_waw_hazard || pstore1_held) && pstore2_valid)) io.cpu.perf.canAcceptStoreThenLoad := !( ((s2_valid && s2_write && pstore1_rmw) && (s1_valid && s1_write && !s1_waw_hazard)) || (pstore2_valid && pstore1_valid_likely && (s1_valid && s1_write))) io.cpu.perf.canAcceptStoreThenRMW := io.cpu.perf.canAcceptStoreThenLoad && !pstore2_valid io.cpu.perf.canAcceptLoadThenLoad := !((s1_valid && s1_write && needsRead(s1_req)) && ((s2_valid && s2_write && !s2_waw_hazard || pstore1_held) || pstore2_valid)) io.cpu.perf.blocked := { // stop reporting blocked just before unblocking to avoid overly conservative stalling val beatsBeforeEnd = outer.crossing match { case SynchronousCrossing(_) => 2 case RationalCrossing(_) => 1 // assumes 1 < ratio <= 2; need more bookkeeping for optimal handling of >2 case _: AsynchronousCrossing => 1 // likewise case _: CreditedCrossing => 1 // likewise } val near_end_of_refill = if (cacheBlockBytes / beatBytes <= beatsBeforeEnd) tl_out.d.valid else { val refill_count = RegInit(0.U((cacheBlockBytes / beatBytes).log2.W)) when (tl_out.d.fire && grantIsRefill) { refill_count := refill_count + 1.U } refill_count >= (cacheBlockBytes / beatBytes - beatsBeforeEnd).U } cached_grant_wait && !near_end_of_refill } // report errors val (data_error, data_error_uncorrectable, data_error_addr) = if (usingDataScratchpad) (s2_valid_data_error, s2_data_error_uncorrectable, s2_req.addr) else { (RegNext(tl_out_c.fire && inWriteback && s2_data_error), RegNext(s2_data_error_uncorrectable), probe_bits.address) // This is stable for a cycle after tl_out_c.fire, so don't need a register } { val error_addr = Mux(metaArb.io.in(1).valid, Cat(s2_first_meta_corrected.tag, metaArb.io.in(1).bits.addr(tagLSB-1, idxLSB)), data_error_addr >> idxLSB) << idxLSB io.errors.uncorrectable.foreach { u => u.valid := metaArb.io.in(1).valid && s2_meta_error_uncorrectable || data_error && data_error_uncorrectable u.bits := error_addr } io.errors.correctable.foreach { c => c.valid := metaArb.io.in(1).valid || data_error c.bits := error_addr io.errors.uncorrectable.foreach { u => when (u.valid) { c.valid := false.B } } } io.errors.bus.valid := tl_out.d.fire && (tl_out.d.bits.denied || tl_out.d.bits.corrupt) io.errors.bus.bits := Mux(grantIsCached, s2_req.addr >> idxLSB << idxLSB, 0.U) ccoverNotScratchpad(io.errors.bus.valid && grantIsCached, "D_ERROR_CACHED", "D$ D-channel error, cached") ccover(io.errors.bus.valid && !grantIsCached, "D_ERROR_UNCACHED", "D$ D-channel error, uncached") } if (usingDataScratchpad) { val data_error_cover = Seq( property.CoverBoolean(!data_error, Seq("no_data_error")), property.CoverBoolean(data_error && !data_error_uncorrectable, Seq("data_correctable_error")), property.CoverBoolean(data_error && data_error_uncorrectable, Seq("data_uncorrectable_error"))) val request_source = Seq( property.CoverBoolean(s2_isSlavePortAccess, Seq("from_TL")), property.CoverBoolean(!s2_isSlavePortAccess, Seq("from_CPU"))) property.cover(new property.CrossProperty( Seq(data_error_cover, request_source), Seq(), "MemorySystem;;Scratchpad Memory Bit Flip Cross Covers")) } else { val data_error_type = Seq( property.CoverBoolean(!s2_valid_data_error, Seq("no_data_error")), property.CoverBoolean(s2_valid_data_error && !s2_data_error_uncorrectable, Seq("data_correctable_error")), property.CoverBoolean(s2_valid_data_error && s2_data_error_uncorrectable, Seq("data_uncorrectable_error"))) val data_error_dirty = Seq( property.CoverBoolean(!s2_victim_dirty, Seq("data_clean")), property.CoverBoolean(s2_victim_dirty, Seq("data_dirty"))) val request_source = if (supports_flush) { Seq( property.CoverBoolean(!flushing, Seq("access")), property.CoverBoolean(flushing, Seq("during_flush"))) } else { Seq(property.CoverBoolean(true.B, Seq("never_flush"))) } val tag_error_cover = Seq( property.CoverBoolean( !s2_meta_error, Seq("no_tag_error")), property.CoverBoolean( s2_meta_error && !s2_meta_error_uncorrectable, Seq("tag_correctable_error")), property.CoverBoolean( s2_meta_error && s2_meta_error_uncorrectable, Seq("tag_uncorrectable_error"))) property.cover(new property.CrossProperty( Seq(data_error_type, data_error_dirty, request_source, tag_error_cover), Seq(), "MemorySystem;;Cache Memory Bit Flip Cross Covers")) } } // leaving gated-clock domain val dcacheImpl = withClock (gated_clock) { new DCacheModuleImpl } def encodeData(x: UInt, poison: Bool) = x.grouped(eccBits).map(dECC.encode(_, if (dECC.canDetect) poison else false.B)).asUInt def dummyEncodeData(x: UInt) = x.grouped(eccBits).map(dECC.swizzle(_)).asUInt def decodeData(x: UInt) = x.grouped(dECC.width(eccBits)).map(dECC.decode(_)) def eccMask(byteMask: UInt) = byteMask.grouped(eccBytes).map(_.orR).asUInt def eccByteMask(byteMask: UInt) = FillInterleaved(eccBytes, eccMask(byteMask)) def likelyNeedsRead(req: HellaCacheReq) = { val res = !req.cmd.isOneOf(M_XWR, M_PFW) || req.size < log2Ceil(eccBytes).U assert(!needsRead(req) || res) res } def needsRead(req: HellaCacheReq) = isRead(req.cmd) || (isWrite(req.cmd) && (req.cmd === M_PWR || req.size < log2Ceil(eccBytes).U)) def ccover(cond: Bool, label: String, desc: String)(implicit sourceInfo: SourceInfo) = property.cover(cond, s"DCACHE_$label", "MemorySystem;;" + desc) def ccoverNotScratchpad(cond: Bool, label: String, desc: String)(implicit sourceInfo: SourceInfo) = if (!usingDataScratchpad) ccover(cond, label, desc) require(!usingVM || tagLSB <= pgIdxBits, s"D$$ set size must not exceed ${1<<(pgIdxBits-10)} KiB; got ${(nSets * cacheBlockBytes)>>10} KiB") def tagLSB: Int = untagBits def probeIdx(b: TLBundleB): UInt = b.address(idxMSB, idxLSB) def addressToProbe(vaddr: UInt, paddr: UInt): TLBundleB = { val res = Wire(new TLBundleB(edge.bundle)) res :#= DontCare res.address := paddr res.source := (mmioOffset - 1).U res } def acquire(vaddr: UInt, paddr: UInt, param: UInt): TLBundleA = { if (!edge.manager.anySupportAcquireB) WireDefault(0.U.asTypeOf(new TLBundleA(edge.bundle))) else edge.AcquireBlock(0.U, paddr >> lgCacheBlockBytes << lgCacheBlockBytes, lgCacheBlockBytes.U, param)._2 } } File DescribedSRAM.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3.{Data, SyncReadMem, Vec} import chisel3.util.log2Ceil object DescribedSRAM { def apply[T <: Data]( name: String, desc: String, size: BigInt, // depth data: T ): SyncReadMem[T] = { val mem = SyncReadMem(size, data) mem.suggestName(name) val granWidth = data match { case v: Vec[_] => v.head.getWidth case d => d.getWidth } val uid = 0 Annotated.srams( component = mem, name = name, address_width = log2Ceil(size), data_width = data.getWidth, depth = size, description = desc, write_mask_granularity = granWidth ) mem } }

module DCacheDataArray( // @[DCache.scala:49:7] input clock, // @[DCache.scala:49:7] input reset, // @[DCache.scala:49:7] input io_req_valid, // @[DCache.scala:50:14] input [11:0] io_req_bits_addr, // @[DCache.scala:50:14] input io_req_bits_write, // @[DCache.scala:50:14] input [63:0] io_req_bits_wdata, // @[DCache.scala:50:14] input io_req_bits_wordMask, // @[DCache.scala:50:14] input [7:0] io_req_bits_eccMask, // @[DCache.scala:50:14] input [7:0] io_req_bits_way_en, // @[DCache.scala:50:14] output [63:0] io_resp_0, // @[DCache.scala:50:14] output [63:0] io_resp_1, // @[DCache.scala:50:14] output [63:0] io_resp_2, // @[DCache.scala:50:14] output [63:0] io_resp_3, // @[DCache.scala:50:14] output [63:0] io_resp_4, // @[DCache.scala:50:14] output [63:0] io_resp_5, // @[DCache.scala:50:14] output [63:0] io_resp_6, // @[DCache.scala:50:14] output [63:0] io_resp_7 // @[DCache.scala:50:14] ); wire [511:0] _rockettile_dcache_data_arrays_0_RW0_rdata; // @[DescribedSRAM.scala:17:26] wire io_req_valid_0 = io_req_valid; // @[DCache.scala:49:7] wire [11:0] io_req_bits_addr_0 = io_req_bits_addr; // @[DCache.scala:49:7] wire io_req_bits_write_0 = io_req_bits_write; // @[DCache.scala:49:7] wire [63:0] io_req_bits_wdata_0 = io_req_bits_wdata; // @[DCache.scala:49:7] wire io_req_bits_wordMask_0 = io_req_bits_wordMask; // @[DCache.scala:49:7] wire [7:0] io_req_bits_eccMask_0 = io_req_bits_eccMask; // @[DCache.scala:49:7] wire [7:0] io_req_bits_way_en_0 = io_req_bits_way_en; // @[DCache.scala:49:7] wire _rdata_valid_T_1 = 1'h1; // @[DCache.scala:71:60] wire rdata_valid = io_req_valid_0; // @[DCache.scala:49:7, :71:30] wire [63:0] wWords_0 = io_req_bits_wdata_0; // @[package.scala:211:50] wire _rdata_valid_T = io_req_bits_wordMask_0; // @[DCache.scala:49:7, :71:83] wire [63:0] rdata_0_0; // @[package.scala:45:27] wire [63:0] rdata_0_1; // @[package.scala:45:27] wire [63:0] rdata_0_2; // @[package.scala:45:27] wire [63:0] rdata_0_3; // @[package.scala:45:27] wire [63:0] rdata_0_4; // @[package.scala:45:27] wire [63:0] rdata_0_5; // @[package.scala:45:27] wire [63:0] rdata_0_6; // @[package.scala:45:27] wire [63:0] rdata_0_7; // @[package.scala:45:27] wire [63:0] io_resp_0_0; // @[DCache.scala:49:7] wire [63:0] io_resp_1_0; // @[DCache.scala:49:7] wire [63:0] io_resp_2_0; // @[DCache.scala:49:7] wire [63:0] io_resp_3_0; // @[DCache.scala:49:7] wire [63:0] io_resp_4_0; // @[DCache.scala:49:7] wire [63:0] io_resp_5_0; // @[DCache.scala:49:7] wire [63:0] io_resp_6_0; // @[DCache.scala:49:7] wire [63:0] io_resp_7_0; // @[DCache.scala:49:7] wire eccMask_0 = io_req_bits_eccMask_0[0]; // @[DCache.scala:49:7, :56:82] wire eccMask_1 = io_req_bits_eccMask_0[1]; // @[DCache.scala:49:7, :56:82] wire eccMask_2 = io_req_bits_eccMask_0[2]; // @[DCache.scala:49:7, :56:82] wire eccMask_3 = io_req_bits_eccMask_0[3]; // @[DCache.scala:49:7, :56:82] wire eccMask_4 = io_req_bits_eccMask_0[4]; // @[DCache.scala:49:7, :56:82] wire eccMask_5 = io_req_bits_eccMask_0[5]; // @[DCache.scala:49:7, :56:82] wire eccMask_6 = io_req_bits_eccMask_0[6]; // @[DCache.scala:49:7, :56:82] wire eccMask_7 = io_req_bits_eccMask_0[7]; // @[DCache.scala:49:7, :56:82] wire _wMask_T = io_req_bits_way_en_0[0]; // @[DCache.scala:49:7, :57:108] wire _wMask_T_1 = io_req_bits_way_en_0[0]; // @[DCache.scala:49:7, :57:108] wire _wMask_T_2 = io_req_bits_way_en_0[0]; // @[DCache.scala:49:7, :57:108] wire _wMask_T_3 = io_req_bits_way_en_0[0]; // @[DCache.scala:49:7, :57:108] wire _wMask_T_4 = io_req_bits_way_en_0[0]; // @[DCache.scala:49:7, :57:108] wire _wMask_T_5 = io_req_bits_way_en_0[0]; // @[DCache.scala:49:7, :57:108] wire _wMask_T_6 = io_req_bits_way_en_0[0]; // @[DCache.scala:49:7, :57:108] wire _wMask_T_7 = io_req_bits_way_en_0[0]; // @[DCache.scala:49:7, :57:108] wire wMask_0 = eccMask_0 & _wMask_T; // @[DCache.scala:56:82, :57:{87,108}] wire wMask_1 = eccMask_1 & _wMask_T_1; // @[DCache.scala:56:82, :57:{87,108}] wire wMask_2 = eccMask_2 & _wMask_T_2; // @[DCache.scala:56:82, :57:{87,108}] wire wMask_3 = eccMask_3 & _wMask_T_3; // @[DCache.scala:56:82, :57:{87,108}] wire wMask_4 = eccMask_4 & _wMask_T_4; // @[DCache.scala:56:82, :57:{87,108}] wire wMask_5 = eccMask_5 & _wMask_T_5; // @[DCache.scala:56:82, :57:{87,108}] wire wMask_6 = eccMask_6 & _wMask_T_6; // @[DCache.scala:56:82, :57:{87,108}] wire wMask_7 = eccMask_7 & _wMask_T_7; // @[DCache.scala:56:82, :57:{87,108}] wire _wMask_T_8 = io_req_bits_way_en_0[1]; // @[DCache.scala:49:7, :57:108] wire _wMask_T_9 = io_req_bits_way_en_0[1]; // @[DCache.scala:49:7, :57:108] wire _wMask_T_10 = io_req_bits_way_en_0[1]; // @[DCache.scala:49:7, :57:108] wire _wMask_T_11 = io_req_bits_way_en_0[1]; // @[DCache.scala:49:7, :57:108] wire _wMask_T_12 = io_req_bits_way_en_0[1]; // @[DCache.scala:49:7, :57:108] wire _wMask_T_13 = io_req_bits_way_en_0[1]; // @[DCache.scala:49:7, :57:108] wire _wMask_T_14 = io_req_bits_way_en_0[1]; // @[DCache.scala:49:7, :57:108] wire _wMask_T_15 = io_req_bits_way_en_0[1]; // @[DCache.scala:49:7, :57:108] wire wMask_8 = eccMask_0 & _wMask_T_8; // @[DCache.scala:56:82, :57:{87,108}] wire wMask_9 = eccMask_1 & _wMask_T_9; // @[DCache.scala:56:82, :57:{87,108}] wire wMask_10 = eccMask_2 & _wMask_T_10; // @[DCache.scala:56:82, :57:{87,108}] wire wMask_11 = eccMask_3 & _wMask_T_11; // @[DCache.scala:56:82, :57:{87,108}] wire wMask_12 = eccMask_4 & _wMask_T_12; // @[DCache.scala:56:82, :57:{87,108}] wire wMask_13 = eccMask_5 & _wMask_T_13; // @[DCache.scala:56:82, :57:{87,108}] wire wMask_14 = eccMask_6 & _wMask_T_14; // @[DCache.scala:56:82, :57:{87,108}] wire wMask_15 = eccMask_7 & _wMask_T_15; // @[DCache.scala:56:82, :57:{87,108}] wire _wMask_T_16 = io_req_bits_way_en_0[2]; // @[DCache.scala:49:7, :57:108] wire _wMask_T_17 = io_req_bits_way_en_0[2]; // @[DCache.scala:49:7, :57:108] wire _wMask_T_18 = io_req_bits_way_en_0[2]; // @[DCache.scala:49:7, :57:108] wire _wMask_T_19 = io_req_bits_way_en_0[2]; // @[DCache.scala:49:7, :57:108] wire _wMask_T_20 = io_req_bits_way_en_0[2]; // @[DCache.scala:49:7, :57:108] wire _wMask_T_21 = io_req_bits_way_en_0[2]; // @[DCache.scala:49:7, :57:108] wire _wMask_T_22 = io_req_bits_way_en_0[2]; // @[DCache.scala:49:7, :57:108] wire _wMask_T_23 = io_req_bits_way_en_0[2]; // @[DCache.scala:49:7, :57:108] wire wMask_16 = eccMask_0 & _wMask_T_16; // @[DCache.scala:56:82, :57:{87,108}] wire wMask_17 = eccMask_1 & _wMask_T_17; // @[DCache.scala:56:82, :57:{87,108}] wire wMask_18 = eccMask_2 & _wMask_T_18; // @[DCache.scala:56:82, :57:{87,108}] wire wMask_19 = eccMask_3 & _wMask_T_19; // @[DCache.scala:56:82, :57:{87,108}] wire wMask_20 = eccMask_4 & _wMask_T_20; // @[DCache.scala:56:82, :57:{87,108}] wire wMask_21 = eccMask_5 & _wMask_T_21; // @[DCache.scala:56:82, :57:{87,108}] wire wMask_22 = eccMask_6 & _wMask_T_22; // @[DCache.scala:56:82, :57:{87,108}] wire wMask_23 = eccMask_7 & _wMask_T_23; // @[DCache.scala:56:82, :57:{87,108}] wire _wMask_T_24 = io_req_bits_way_en_0[3]; // @[DCache.scala:49:7, :57:108] wire _wMask_T_25 = io_req_bits_way_en_0[3]; // @[DCache.scala:49:7, :57:108] wire _wMask_T_26 = io_req_bits_way_en_0[3]; // @[DCache.scala:49:7, :57:108] wire _wMask_T_27 = io_req_bits_way_en_0[3]; // @[DCache.scala:49:7, :57:108] wire _wMask_T_28 = io_req_bits_way_en_0[3]; // @[DCache.scala:49:7, :57:108] wire _wMask_T_29 = io_req_bits_way_en_0[3]; // @[DCache.scala:49:7, :57:108] wire _wMask_T_30 = io_req_bits_way_en_0[3]; // @[DCache.scala:49:7, :57:108] wire _wMask_T_31 = io_req_bits_way_en_0[3]; // @[DCache.scala:49:7, :57:108] wire wMask_24 = eccMask_0 & _wMask_T_24; // @[DCache.scala:56:82, :57:{87,108}] wire wMask_25 = eccMask_1 & _wMask_T_25; // @[DCache.scala:56:82, :57:{87,108}] wire wMask_26 = eccMask_2 & _wMask_T_26; // @[DCache.scala:56:82, :57:{87,108}] wire wMask_27 = eccMask_3 & _wMask_T_27; // @[DCache.scala:56:82, :57:{87,108}] wire wMask_28 = eccMask_4 & _wMask_T_28; // @[DCache.scala:56:82, :57:{87,108}] wire wMask_29 = eccMask_5 & _wMask_T_29; // @[DCache.scala:56:82, :57:{87,108}] wire wMask_30 = eccMask_6 & _wMask_T_30; // @[DCache.scala:56:82, :57:{87,108}] wire wMask_31 = eccMask_7 & _wMask_T_31; // @[DCache.scala:56:82, :57:{87,108}] wire _wMask_T_32 = io_req_bits_way_en_0[4]; // @[DCache.scala:49:7, :57:108] wire _wMask_T_33 = io_req_bits_way_en_0[4]; // @[DCache.scala:49:7, :57:108] wire _wMask_T_34 = io_req_bits_way_en_0[4]; // @[DCache.scala:49:7, :57:108] wire _wMask_T_35 = io_req_bits_way_en_0[4]; // @[DCache.scala:49:7, :57:108] wire _wMask_T_36 = io_req_bits_way_en_0[4]; // @[DCache.scala:49:7, :57:108] wire _wMask_T_37 = io_req_bits_way_en_0[4]; // @[DCache.scala:49:7, :57:108] wire _wMask_T_38 = io_req_bits_way_en_0[4]; // @[DCache.scala:49:7, :57:108] wire _wMask_T_39 = io_req_bits_way_en_0[4]; // @[DCache.scala:49:7, :57:108] wire wMask_32 = eccMask_0 & _wMask_T_32; // @[DCache.scala:56:82, :57:{87,108}] wire wMask_33 = eccMask_1 & _wMask_T_33; // @[DCache.scala:56:82, :57:{87,108}] wire wMask_34 = eccMask_2 & _wMask_T_34; // @[DCache.scala:56:82, :57:{87,108}] wire wMask_35 = eccMask_3 & _wMask_T_35; // @[DCache.scala:56:82, :57:{87,108}] wire wMask_36 = eccMask_4 & _wMask_T_36; // @[DCache.scala:56:82, :57:{87,108}] wire wMask_37 = eccMask_5 & _wMask_T_37; // @[DCache.scala:56:82, :57:{87,108}] wire wMask_38 = eccMask_6 & _wMask_T_38; // @[DCache.scala:56:82, :57:{87,108}] wire wMask_39 = eccMask_7 & _wMask_T_39; // @[DCache.scala:56:82, :57:{87,108}] wire _wMask_T_40 = io_req_bits_way_en_0[5]; // @[DCache.scala:49:7, :57:108] wire _wMask_T_41 = io_req_bits_way_en_0[5]; // @[DCache.scala:49:7, :57:108] wire _wMask_T_42 = io_req_bits_way_en_0[5]; // @[DCache.scala:49:7, :57:108] wire _wMask_T_43 = io_req_bits_way_en_0[5]; // @[DCache.scala:49:7, :57:108] wire _wMask_T_44 = io_req_bits_way_en_0[5]; // @[DCache.scala:49:7, :57:108] wire _wMask_T_45 = io_req_bits_way_en_0[5]; // @[DCache.scala:49:7, :57:108] wire _wMask_T_46 = io_req_bits_way_en_0[5]; // @[DCache.scala:49:7, :57:108] wire _wMask_T_47 = io_req_bits_way_en_0[5]; // @[DCache.scala:49:7, :57:108] wire wMask_40 = eccMask_0 & _wMask_T_40; // @[DCache.scala:56:82, :57:{87,108}] wire wMask_41 = eccMask_1 & _wMask_T_41; // @[DCache.scala:56:82, :57:{87,108}] wire wMask_42 = eccMask_2 & _wMask_T_42; // @[DCache.scala:56:82, :57:{87,108}] wire wMask_43 = eccMask_3 & _wMask_T_43; // @[DCache.scala:56:82, :57:{87,108}] wire wMask_44 = eccMask_4 & _wMask_T_44; // @[DCache.scala:56:82, :57:{87,108}] wire wMask_45 = eccMask_5 & _wMask_T_45; // @[DCache.scala:56:82, :57:{87,108}] wire wMask_46 = eccMask_6 & _wMask_T_46; // @[DCache.scala:56:82, :57:{87,108}] wire wMask_47 = eccMask_7 & _wMask_T_47; // @[DCache.scala:56:82, :57:{87,108}] wire _wMask_T_48 = io_req_bits_way_en_0[6]; // @[DCache.scala:49:7, :57:108] wire _wMask_T_49 = io_req_bits_way_en_0[6]; // @[DCache.scala:49:7, :57:108] wire _wMask_T_50 = io_req_bits_way_en_0[6]; // @[DCache.scala:49:7, :57:108] wire _wMask_T_51 = io_req_bits_way_en_0[6]; // @[DCache.scala:49:7, :57:108] wire _wMask_T_52 = io_req_bits_way_en_0[6]; // @[DCache.scala:49:7, :57:108] wire _wMask_T_53 = io_req_bits_way_en_0[6]; // @[DCache.scala:49:7, :57:108] wire _wMask_T_54 = io_req_bits_way_en_0[6]; // @[DCache.scala:49:7, :57:108] wire _wMask_T_55 = io_req_bits_way_en_0[6]; // @[DCache.scala:49:7, :57:108] wire wMask_48 = eccMask_0 & _wMask_T_48; // @[DCache.scala:56:82, :57:{87,108}] wire wMask_49 = eccMask_1 & _wMask_T_49; // @[DCache.scala:56:82, :57:{87,108}] wire wMask_50 = eccMask_2 & _wMask_T_50; // @[DCache.scala:56:82, :57:{87,108}] wire wMask_51 = eccMask_3 & _wMask_T_51; // @[DCache.scala:56:82, :57:{87,108}] wire wMask_52 = eccMask_4 & _wMask_T_52; // @[DCache.scala:56:82, :57:{87,108}] wire wMask_53 = eccMask_5 & _wMask_T_53; // @[DCache.scala:56:82, :57:{87,108}] wire wMask_54 = eccMask_6 & _wMask_T_54; // @[DCache.scala:56:82, :57:{87,108}] wire wMask_55 = eccMask_7 & _wMask_T_55; // @[DCache.scala:56:82, :57:{87,108}] wire _wMask_T_56 = io_req_bits_way_en_0[7]; // @[DCache.scala:49:7, :57:108] wire _wMask_T_57 = io_req_bits_way_en_0[7]; // @[DCache.scala:49:7, :57:108] wire _wMask_T_58 = io_req_bits_way_en_0[7]; // @[DCache.scala:49:7, :57:108] wire _wMask_T_59 = io_req_bits_way_en_0[7]; // @[DCache.scala:49:7, :57:108] wire _wMask_T_60 = io_req_bits_way_en_0[7]; // @[DCache.scala:49:7, :57:108] wire _wMask_T_61 = io_req_bits_way_en_0[7]; // @[DCache.scala:49:7, :57:108] wire _wMask_T_62 = io_req_bits_way_en_0[7]; // @[DCache.scala:49:7, :57:108] wire _wMask_T_63 = io_req_bits_way_en_0[7]; // @[DCache.scala:49:7, :57:108] wire wMask_56 = eccMask_0 & _wMask_T_56; // @[DCache.scala:56:82, :57:{87,108}] wire wMask_57 = eccMask_1 & _wMask_T_57; // @[DCache.scala:56:82, :57:{87,108}] wire wMask_58 = eccMask_2 & _wMask_T_58; // @[DCache.scala:56:82, :57:{87,108}] wire wMask_59 = eccMask_3 & _wMask_T_59; // @[DCache.scala:56:82, :57:{87,108}] wire wMask_60 = eccMask_4 & _wMask_T_60; // @[DCache.scala:56:82, :57:{87,108}] wire wMask_61 = eccMask_5 & _wMask_T_61; // @[DCache.scala:56:82, :57:{87,108}] wire wMask_62 = eccMask_6 & _wMask_T_62; // @[DCache.scala:56:82, :57:{87,108}] wire wMask_63 = eccMask_7 & _wMask_T_63; // @[DCache.scala:56:82, :57:{87,108}] wire [8:0] addr = io_req_bits_addr_0[11:3]; // @[DCache.scala:49:7, :59:31] wire [8:0] _rdata_data_WIRE = addr; // @[DCache.scala:59:31, :77:26] wire _rdata_T; // @[DCache.scala:72:17] wire _rdata_data_T_1; // @[DCache.scala:77:39] wire [7:0] _rdata_WIRE_0; // @[DCache.scala:75:32] wire [7:0] _rdata_WIRE_1; // @[DCache.scala:75:32] wire [7:0] _rdata_WIRE_2; // @[DCache.scala:75:32] wire [7:0] _rdata_WIRE_3; // @[DCache.scala:75:32] wire [7:0] _rdata_WIRE_4; // @[DCache.scala:75:32] wire [7:0] _rdata_WIRE_5; // @[DCache.scala:75:32] wire [7:0] _rdata_WIRE_6; // @[DCache.scala:75:32] wire [7:0] _rdata_WIRE_7; // @[DCache.scala:75:32] wire [7:0] _rdata_WIRE_8; // @[DCache.scala:75:32] wire [7:0] _rdata_WIRE_9; // @[DCache.scala:75:32] wire [7:0] _rdata_WIRE_10; // @[DCache.scala:75:32] wire [7:0] _rdata_WIRE_11; // @[DCache.scala:75:32] wire [7:0] _rdata_WIRE_12; // @[DCache.scala:75:32] wire [7:0] _rdata_WIRE_13; // @[DCache.scala:75:32] wire [7:0] _rdata_WIRE_14; // @[DCache.scala:75:32] wire [7:0] _rdata_WIRE_15; // @[DCache.scala:75:32] wire [7:0] _rdata_WIRE_16; // @[DCache.scala:75:32] wire [7:0] _rdata_WIRE_17; // @[DCache.scala:75:32] wire [7:0] _rdata_WIRE_18; // @[DCache.scala:75:32] wire [7:0] _rdata_WIRE_19; // @[DCache.scala:75:32] wire [7:0] _rdata_WIRE_20; // @[DCache.scala:75:32] wire [7:0] _rdata_WIRE_21; // @[DCache.scala:75:32] wire [7:0] _rdata_WIRE_22; // @[DCache.scala:75:32] wire [7:0] _rdata_WIRE_23; // @[DCache.scala:75:32] wire [7:0] _rdata_WIRE_24; // @[DCache.scala:75:32] wire [7:0] _rdata_WIRE_25; // @[DCache.scala:75:32] wire [7:0] _rdata_WIRE_26; // @[DCache.scala:75:32] wire [7:0] _rdata_WIRE_27; // @[DCache.scala:75:32] wire [7:0] _rdata_WIRE_28; // @[DCache.scala:75:32] wire [7:0] _rdata_WIRE_29; // @[DCache.scala:75:32] wire [7:0] _rdata_WIRE_30; // @[DCache.scala:75:32] wire [7:0] _rdata_WIRE_31; // @[DCache.scala:75:32] wire [7:0] _rdata_WIRE_32; // @[DCache.scala:75:32] wire [7:0] _rdata_WIRE_33; // @[DCache.scala:75:32] wire [7:0] _rdata_WIRE_34; // @[DCache.scala:75:32] wire [7:0] _rdata_WIRE_35; // @[DCache.scala:75:32] wire [7:0] _rdata_WIRE_36; // @[DCache.scala:75:32] wire [7:0] _rdata_WIRE_37; // @[DCache.scala:75:32] wire [7:0] _rdata_WIRE_38; // @[DCache.scala:75:32] wire [7:0] _rdata_WIRE_39; // @[DCache.scala:75:32] wire [7:0] _rdata_WIRE_40; // @[DCache.scala:75:32] wire [7:0] _rdata_WIRE_41; // @[DCache.scala:75:32] wire [7:0] _rdata_WIRE_42; // @[DCache.scala:75:32] wire [7:0] _rdata_WIRE_43; // @[DCache.scala:75:32] wire [7:0] _rdata_WIRE_44; // @[DCache.scala:75:32] wire [7:0] _rdata_WIRE_45; // @[DCache.scala:75:32] wire [7:0] _rdata_WIRE_46; // @[DCache.scala:75:32] wire [7:0] _rdata_WIRE_47; // @[DCache.scala:75:32] wire [7:0] _rdata_WIRE_48; // @[DCache.scala:75:32] wire [7:0] _rdata_WIRE_49; // @[DCache.scala:75:32] wire [7:0] _rdata_WIRE_50; // @[DCache.scala:75:32] wire [7:0] _rdata_WIRE_51; // @[DCache.scala:75:32] wire [7:0] _rdata_WIRE_52; // @[DCache.scala:75:32] wire [7:0] _rdata_WIRE_53; // @[DCache.scala:75:32] wire [7:0] _rdata_WIRE_54; // @[DCache.scala:75:32] wire [7:0] _rdata_WIRE_55; // @[DCache.scala:75:32] wire [7:0] _rdata_WIRE_56; // @[DCache.scala:75:32] wire [7:0] _rdata_WIRE_57; // @[DCache.scala:75:32] wire [7:0] _rdata_WIRE_58; // @[DCache.scala:75:32] wire [7:0] _rdata_WIRE_59; // @[DCache.scala:75:32] wire [7:0] _rdata_WIRE_60; // @[DCache.scala:75:32] wire [7:0] _rdata_WIRE_61; // @[DCache.scala:75:32] wire [7:0] _rdata_WIRE_62; // @[DCache.scala:75:32] wire [7:0] _rdata_WIRE_63; // @[DCache.scala:75:32] assign _rdata_T = rdata_valid & io_req_bits_write_0; // @[DCache.scala:49:7, :71:30, :72:17] wire [7:0] rdata_wData_0 = wWords_0[7:0]; // @[package.scala:211:50] assign _rdata_WIRE_0 = rdata_wData_0; // @[package.scala:211:50] assign _rdata_WIRE_8 = rdata_wData_0; // @[package.scala:211:50] assign _rdata_WIRE_16 = rdata_wData_0; // @[package.scala:211:50] assign _rdata_WIRE_24 = rdata_wData_0; // @[package.scala:211:50] assign _rdata_WIRE_32 = rdata_wData_0; // @[package.scala:211:50] assign _rdata_WIRE_40 = rdata_wData_0; // @[package.scala:211:50] assign _rdata_WIRE_48 = rdata_wData_0; // @[package.scala:211:50] assign _rdata_WIRE_56 = rdata_wData_0; // @[package.scala:211:50] wire [7:0] rdata_wData_1 = wWords_0[15:8]; // @[package.scala:211:50] assign _rdata_WIRE_1 = rdata_wData_1; // @[package.scala:211:50] assign _rdata_WIRE_9 = rdata_wData_1; // @[package.scala:211:50] assign _rdata_WIRE_17 = rdata_wData_1; // @[package.scala:211:50] assign _rdata_WIRE_25 = rdata_wData_1; // @[package.scala:211:50] assign _rdata_WIRE_33 = rdata_wData_1; // @[package.scala:211:50] assign _rdata_WIRE_41 = rdata_wData_1; // @[package.scala:211:50] assign _rdata_WIRE_49 = rdata_wData_1; // @[package.scala:211:50] assign _rdata_WIRE_57 = rdata_wData_1; // @[package.scala:211:50] wire [7:0] rdata_wData_2 = wWords_0[23:16]; // @[package.scala:211:50] assign _rdata_WIRE_2 = rdata_wData_2; // @[package.scala:211:50] assign _rdata_WIRE_10 = rdata_wData_2; // @[package.scala:211:50] assign _rdata_WIRE_18 = rdata_wData_2; // @[package.scala:211:50] assign _rdata_WIRE_26 = rdata_wData_2; // @[package.scala:211:50] assign _rdata_WIRE_34 = rdata_wData_2; // @[package.scala:211:50] assign _rdata_WIRE_42 = rdata_wData_2; // @[package.scala:211:50] assign _rdata_WIRE_50 = rdata_wData_2; // @[package.scala:211:50] assign _rdata_WIRE_58 = rdata_wData_2; // @[package.scala:211:50] wire [7:0] rdata_wData_3 = wWords_0[31:24]; // @[package.scala:211:50] assign _rdata_WIRE_3 = rdata_wData_3; // @[package.scala:211:50] assign _rdata_WIRE_11 = rdata_wData_3; // @[package.scala:211:50] assign _rdata_WIRE_19 = rdata_wData_3; // @[package.scala:211:50] assign _rdata_WIRE_27 = rdata_wData_3; // @[package.scala:211:50] assign _rdata_WIRE_35 = rdata_wData_3; // @[package.scala:211:50] assign _rdata_WIRE_43 = rdata_wData_3; // @[package.scala:211:50] assign _rdata_WIRE_51 = rdata_wData_3; // @[package.scala:211:50] assign _rdata_WIRE_59 = rdata_wData_3; // @[package.scala:211:50] wire [7:0] rdata_wData_4 = wWords_0[39:32]; // @[package.scala:211:50] assign _rdata_WIRE_4 = rdata_wData_4; // @[package.scala:211:50] assign _rdata_WIRE_12 = rdata_wData_4; // @[package.scala:211:50] assign _rdata_WIRE_20 = rdata_wData_4; // @[package.scala:211:50] assign _rdata_WIRE_28 = rdata_wData_4; // @[package.scala:211:50] assign _rdata_WIRE_36 = rdata_wData_4; // @[package.scala:211:50] assign _rdata_WIRE_44 = rdata_wData_4; // @[package.scala:211:50] assign _rdata_WIRE_52 = rdata_wData_4; // @[package.scala:211:50] assign _rdata_WIRE_60 = rdata_wData_4; // @[package.scala:211:50] wire [7:0] rdata_wData_5 = wWords_0[47:40]; // @[package.scala:211:50] assign _rdata_WIRE_5 = rdata_wData_5; // @[package.scala:211:50] assign _rdata_WIRE_13 = rdata_wData_5; // @[package.scala:211:50] assign _rdata_WIRE_21 = rdata_wData_5; // @[package.scala:211:50] assign _rdata_WIRE_29 = rdata_wData_5; // @[package.scala:211:50] assign _rdata_WIRE_37 = rdata_wData_5; // @[package.scala:211:50] assign _rdata_WIRE_45 = rdata_wData_5; // @[package.scala:211:50] assign _rdata_WIRE_53 = rdata_wData_5; // @[package.scala:211:50] assign _rdata_WIRE_61 = rdata_wData_5; // @[package.scala:211:50] wire [7:0] rdata_wData_6 = wWords_0[55:48]; // @[package.scala:211:50] assign _rdata_WIRE_6 = rdata_wData_6; // @[package.scala:211:50] assign _rdata_WIRE_14 = rdata_wData_6; // @[package.scala:211:50] assign _rdata_WIRE_22 = rdata_wData_6; // @[package.scala:211:50] assign _rdata_WIRE_30 = rdata_wData_6; // @[package.scala:211:50] assign _rdata_WIRE_38 = rdata_wData_6; // @[package.scala:211:50] assign _rdata_WIRE_46 = rdata_wData_6; // @[package.scala:211:50] assign _rdata_WIRE_54 = rdata_wData_6; // @[package.scala:211:50] assign _rdata_WIRE_62 = rdata_wData_6; // @[package.scala:211:50] wire [7:0] rdata_wData_7 = wWords_0[63:56]; // @[package.scala:211:50] assign _rdata_WIRE_7 = rdata_wData_7; // @[package.scala:211:50] assign _rdata_WIRE_15 = rdata_wData_7; // @[package.scala:211:50] assign _rdata_WIRE_23 = rdata_wData_7; // @[package.scala:211:50] assign _rdata_WIRE_31 = rdata_wData_7; // @[package.scala:211:50] assign _rdata_WIRE_39 = rdata_wData_7; // @[package.scala:211:50] assign _rdata_WIRE_47 = rdata_wData_7; // @[package.scala:211:50] assign _rdata_WIRE_55 = rdata_wData_7; // @[package.scala:211:50] assign _rdata_WIRE_63 = rdata_wData_7; // @[package.scala:211:50] wire _rdata_data_T = ~io_req_bits_write_0; // @[DCache.scala:49:7, :77:42] assign _rdata_data_T_1 = rdata_valid & _rdata_data_T; // @[DCache.scala:71:30, :77:{39,42}] wire [15:0] rdata_lo_lo = _rockettile_dcache_data_arrays_0_RW0_rdata[15:0]; // @[package.scala:45:27] wire [15:0] rdata_lo_hi = _rockettile_dcache_data_arrays_0_RW0_rdata[31:16]; // @[package.scala:45:27] wire [31:0] rdata_lo = {rdata_lo_hi, rdata_lo_lo}; // @[package.scala:45:27] wire [15:0] rdata_hi_lo = _rockettile_dcache_data_arrays_0_RW0_rdata[47:32]; // @[package.scala:45:27] wire [15:0] rdata_hi_hi = _rockettile_dcache_data_arrays_0_RW0_rdata[63:48]; // @[package.scala:45:27] wire [31:0] rdata_hi = {rdata_hi_hi, rdata_hi_lo}; // @[package.scala:45:27] assign rdata_0_0 = {rdata_hi, rdata_lo}; // @[package.scala:45:27] assign io_resp_0_0 = rdata_0_0; // @[package.scala:45:27] wire [15:0] rdata_lo_lo_1 = _rockettile_dcache_data_arrays_0_RW0_rdata[79:64]; // @[package.scala:45:27] wire [15:0] rdata_lo_hi_1 = _rockettile_dcache_data_arrays_0_RW0_rdata[95:80]; // @[package.scala:45:27] wire [31:0] rdata_lo_1 = {rdata_lo_hi_1, rdata_lo_lo_1}; // @[package.scala:45:27] wire [15:0] rdata_hi_lo_1 = _rockettile_dcache_data_arrays_0_RW0_rdata[111:96]; // @[package.scala:45:27] wire [15:0] rdata_hi_hi_1 = _rockettile_dcache_data_arrays_0_RW0_rdata[127:112]; // @[package.scala:45:27] wire [31:0] rdata_hi_1 = {rdata_hi_hi_1, rdata_hi_lo_1}; // @[package.scala:45:27] assign rdata_0_1 = {rdata_hi_1, rdata_lo_1}; // @[package.scala:45:27] assign io_resp_1_0 = rdata_0_1; // @[package.scala:45:27] wire [15:0] rdata_lo_lo_2 = _rockettile_dcache_data_arrays_0_RW0_rdata[143:128]; // @[package.scala:45:27] wire [15:0] rdata_lo_hi_2 = _rockettile_dcache_data_arrays_0_RW0_rdata[159:144]; // @[package.scala:45:27] wire [31:0] rdata_lo_2 = {rdata_lo_hi_2, rdata_lo_lo_2}; // @[package.scala:45:27] wire [15:0] rdata_hi_lo_2 = _rockettile_dcache_data_arrays_0_RW0_rdata[175:160]; // @[package.scala:45:27] wire [15:0] rdata_hi_hi_2 = _rockettile_dcache_data_arrays_0_RW0_rdata[191:176]; // @[package.scala:45:27] wire [31:0] rdata_hi_2 = {rdata_hi_hi_2, rdata_hi_lo_2}; // @[package.scala:45:27] assign rdata_0_2 = {rdata_hi_2, rdata_lo_2}; // @[package.scala:45:27] assign io_resp_2_0 = rdata_0_2; // @[package.scala:45:27] wire [15:0] rdata_lo_lo_3 = _rockettile_dcache_data_arrays_0_RW0_rdata[207:192]; // @[package.scala:45:27] wire [15:0] rdata_lo_hi_3 = _rockettile_dcache_data_arrays_0_RW0_rdata[223:208]; // @[package.scala:45:27] wire [31:0] rdata_lo_3 = {rdata_lo_hi_3, rdata_lo_lo_3}; // @[package.scala:45:27] wire [15:0] rdata_hi_lo_3 = _rockettile_dcache_data_arrays_0_RW0_rdata[239:224]; // @[package.scala:45:27] wire [15:0] rdata_hi_hi_3 = _rockettile_dcache_data_arrays_0_RW0_rdata[255:240]; // @[package.scala:45:27] wire [31:0] rdata_hi_3 = {rdata_hi_hi_3, rdata_hi_lo_3}; // @[package.scala:45:27] assign rdata_0_3 = {rdata_hi_3, rdata_lo_3}; // @[package.scala:45:27] assign io_resp_3_0 = rdata_0_3; // @[package.scala:45:27] wire [15:0] rdata_lo_lo_4 = _rockettile_dcache_data_arrays_0_RW0_rdata[271:256]; // @[package.scala:45:27] wire [15:0] rdata_lo_hi_4 = _rockettile_dcache_data_arrays_0_RW0_rdata[287:272]; // @[package.scala:45:27] wire [31:0] rdata_lo_4 = {rdata_lo_hi_4, rdata_lo_lo_4}; // @[package.scala:45:27] wire [15:0] rdata_hi_lo_4 = _rockettile_dcache_data_arrays_0_RW0_rdata[303:288]; // @[package.scala:45:27] wire [15:0] rdata_hi_hi_4 = _rockettile_dcache_data_arrays_0_RW0_rdata[319:304]; // @[package.scala:45:27] wire [31:0] rdata_hi_4 = {rdata_hi_hi_4, rdata_hi_lo_4}; // @[package.scala:45:27] assign rdata_0_4 = {rdata_hi_4, rdata_lo_4}; // @[package.scala:45:27] assign io_resp_4_0 = rdata_0_4; // @[package.scala:45:27] wire [15:0] rdata_lo_lo_5 = _rockettile_dcache_data_arrays_0_RW0_rdata[335:320]; // @[package.scala:45:27] wire [15:0] rdata_lo_hi_5 = _rockettile_dcache_data_arrays_0_RW0_rdata[351:336]; // @[package.scala:45:27] wire [31:0] rdata_lo_5 = {rdata_lo_hi_5, rdata_lo_lo_5}; // @[package.scala:45:27] wire [15:0] rdata_hi_lo_5 = _rockettile_dcache_data_arrays_0_RW0_rdata[367:352]; // @[package.scala:45:27] wire [15:0] rdata_hi_hi_5 = _rockettile_dcache_data_arrays_0_RW0_rdata[383:368]; // @[package.scala:45:27] wire [31:0] rdata_hi_5 = {rdata_hi_hi_5, rdata_hi_lo_5}; // @[package.scala:45:27] assign rdata_0_5 = {rdata_hi_5, rdata_lo_5}; // @[package.scala:45:27] assign io_resp_5_0 = rdata_0_5; // @[package.scala:45:27] wire [15:0] rdata_lo_lo_6 = _rockettile_dcache_data_arrays_0_RW0_rdata[399:384]; // @[package.scala:45:27] wire [15:0] rdata_lo_hi_6 = _rockettile_dcache_data_arrays_0_RW0_rdata[415:400]; // @[package.scala:45:27] wire [31:0] rdata_lo_6 = {rdata_lo_hi_6, rdata_lo_lo_6}; // @[package.scala:45:27] wire [15:0] rdata_hi_lo_6 = _rockettile_dcache_data_arrays_0_RW0_rdata[431:416]; // @[package.scala:45:27] wire [15:0] rdata_hi_hi_6 = _rockettile_dcache_data_arrays_0_RW0_rdata[447:432]; // @[package.scala:45:27] wire [31:0] rdata_hi_6 = {rdata_hi_hi_6, rdata_hi_lo_6}; // @[package.scala:45:27] assign rdata_0_6 = {rdata_hi_6, rdata_lo_6}; // @[package.scala:45:27] assign io_resp_6_0 = rdata_0_6; // @[package.scala:45:27] wire [15:0] rdata_lo_lo_7 = _rockettile_dcache_data_arrays_0_RW0_rdata[463:448]; // @[package.scala:45:27] wire [15:0] rdata_lo_hi_7 = _rockettile_dcache_data_arrays_0_RW0_rdata[479:464]; // @[package.scala:45:27] wire [31:0] rdata_lo_7 = {rdata_lo_hi_7, rdata_lo_lo_7}; // @[package.scala:45:27] wire [15:0] rdata_hi_lo_7 = _rockettile_dcache_data_arrays_0_RW0_rdata[495:480]; // @[package.scala:45:27] wire [15:0] rdata_hi_hi_7 = _rockettile_dcache_data_arrays_0_RW0_rdata[511:496]; // @[package.scala:45:27] wire [31:0] rdata_hi_7 = {rdata_hi_hi_7, rdata_hi_lo_7}; // @[package.scala:45:27] assign rdata_0_7 = {rdata_hi_7, rdata_lo_7}; // @[package.scala:45:27] assign io_resp_7_0 = rdata_0_7; // @[package.scala:45:27] rockettile_dcache_data_arrays_0 rockettile_dcache_data_arrays_0 ( // @[DescribedSRAM.scala:17:26] .RW0_addr (_rdata_T ? addr : _rdata_data_WIRE), // @[DescribedSRAM.scala:17:26] .RW0_en (_rdata_data_T_1 | _rdata_T), // @[DescribedSRAM.scala:17:26] .RW0_clk (clock), .RW0_wmode (io_req_bits_write_0), // @[DCache.scala:49:7] .RW0_wdata ({_rdata_WIRE_63, _rdata_WIRE_62, _rdata_WIRE_61, _rdata_WIRE_60, _rdata_WIRE_59, _rdata_WIRE_58, _rdata_WIRE_57, _rdata_WIRE_56, _rdata_WIRE_55, _rdata_WIRE_54, _rdata_WIRE_53, _rdata_WIRE_52, _rdata_WIRE_51, _rdata_WIRE_50, _rdata_WIRE_49, _rdata_WIRE_48, _rdata_WIRE_47, _rdata_WIRE_46, _rdata_WIRE_45, _rdata_WIRE_44, _rdata_WIRE_43, _rdata_WIRE_42, _rdata_WIRE_41, _rdata_WIRE_40, _rdata_WIRE_39, _rdata_WIRE_38, _rdata_WIRE_37, _rdata_WIRE_36, _rdata_WIRE_35, _rdata_WIRE_34, _rdata_WIRE_33, _rdata_WIRE_32, _rdata_WIRE_31, _rdata_WIRE_30, _rdata_WIRE_29, _rdata_WIRE_28, _rdata_WIRE_27, _rdata_WIRE_26, _rdata_WIRE_25, _rdata_WIRE_24, _rdata_WIRE_23, _rdata_WIRE_22, _rdata_WIRE_21, _rdata_WIRE_20, _rdata_WIRE_19, _rdata_WIRE_18, _rdata_WIRE_17, _rdata_WIRE_16, _rdata_WIRE_15, _rdata_WIRE_14, _rdata_WIRE_13, _rdata_WIRE_12, _rdata_WIRE_11, _rdata_WIRE_10, _rdata_WIRE_9, _rdata_WIRE_8, _rdata_WIRE_7, _rdata_WIRE_6, _rdata_WIRE_5, _rdata_WIRE_4, _rdata_WIRE_3, _rdata_WIRE_2, _rdata_WIRE_1, _rdata_WIRE_0}), // @[DescribedSRAM.scala:17:26] .RW0_rdata (_rockettile_dcache_data_arrays_0_RW0_rdata), .RW0_wmask ({wMask_63, wMask_62, wMask_61, wMask_60, wMask_59, wMask_58, wMask_57, wMask_56, wMask_55, wMask_54, wMask_53, wMask_52, wMask_51, wMask_50, wMask_49, wMask_48, wMask_47, wMask_46, wMask_45, wMask_44, wMask_43, wMask_42, wMask_41, wMask_40, wMask_39, wMask_38, wMask_37, wMask_36, wMask_35, wMask_34, wMask_33, wMask_32, wMask_31, wMask_30, wMask_29, wMask_28, wMask_27, wMask_26, wMask_25, wMask_24, wMask_23, wMask_22, wMask_21, wMask_20, wMask_19, wMask_18, wMask_17, wMask_16, wMask_15, wMask_14, wMask_13, wMask_12, wMask_11, wMask_10, wMask_9, wMask_8, wMask_7, wMask_6, wMask_5, wMask_4, wMask_3, wMask_2, wMask_1, wMask_0}) // @[DescribedSRAM.scala:17:26] ); // @[DescribedSRAM.scala:17:26] assign io_resp_0 = io_resp_0_0; // @[DCache.scala:49:7] assign io_resp_1 = io_resp_1_0; // @[DCache.scala:49:7] assign io_resp_2 = io_resp_2_0; // @[DCache.scala:49:7] assign io_resp_3 = io_resp_3_0; // @[DCache.scala:49:7] assign io_resp_4 = io_resp_4_0; // @[DCache.scala:49:7] assign io_resp_5 = io_resp_5_0; // @[DCache.scala:49:7] assign io_resp_6 = io_resp_6_0; // @[DCache.scala:49:7] assign io_resp_7 = io_resp_7_0; // @[DCache.scala:49:7] endmodule

Generate the Verilog code corresponding to the following Chisel files. File FPU.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.tile import chisel3._ import chisel3.util._ import chisel3.{DontCare, WireInit, withClock, withReset} import chisel3.experimental.SourceInfo import chisel3.experimental.dataview._ import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.rocket._ import freechips.rocketchip.rocket.Instructions._ import freechips.rocketchip.util._ import freechips.rocketchip.util.property case class FPUParams( minFLen: Int = 32, fLen: Int = 64, divSqrt: Boolean = true, sfmaLatency: Int = 3, dfmaLatency: Int = 4, fpmuLatency: Int = 2, ifpuLatency: Int = 2 ) object FPConstants { val RM_SZ = 3 val FLAGS_SZ = 5 } trait HasFPUCtrlSigs { val ldst = Bool() val wen = Bool() val ren1 = Bool() val ren2 = Bool() val ren3 = Bool() val swap12 = Bool() val swap23 = Bool() val typeTagIn = UInt(2.W) val typeTagOut = UInt(2.W) val fromint = Bool() val toint = Bool() val fastpipe = Bool() val fma = Bool() val div = Bool() val sqrt = Bool() val wflags = Bool() val vec = Bool() } class FPUCtrlSigs extends Bundle with HasFPUCtrlSigs class FPUDecoder(implicit p: Parameters) extends FPUModule()(p) { val io = IO(new Bundle { val inst = Input(Bits(32.W)) val sigs = Output(new FPUCtrlSigs()) }) private val X2 = BitPat.dontCare(2) val default = List(X,X,X,X,X,X,X,X2,X2,X,X,X,X,X,X,X,N) val h: Array[(BitPat, List[BitPat])] = Array(FLH -> List(Y,Y,N,N,N,X,X,X2,X2,N,N,N,N,N,N,N,N), FSH -> List(Y,N,N,Y,N,Y,X, I, H,N,Y,N,N,N,N,N,N), FMV_H_X -> List(N,Y,N,N,N,X,X, H, I,Y,N,N,N,N,N,N,N), FCVT_H_W -> List(N,Y,N,N,N,X,X, H, H,Y,N,N,N,N,N,Y,N), FCVT_H_WU-> List(N,Y,N,N,N,X,X, H, H,Y,N,N,N,N,N,Y,N), FCVT_H_L -> List(N,Y,N,N,N,X,X, H, H,Y,N,N,N,N,N,Y,N), FCVT_H_LU-> List(N,Y,N,N,N,X,X, H, H,Y,N,N,N,N,N,Y,N), FMV_X_H -> List(N,N,Y,N,N,N,X, I, H,N,Y,N,N,N,N,N,N), FCLASS_H -> List(N,N,Y,N,N,N,X, H, H,N,Y,N,N,N,N,N,N), FCVT_W_H -> List(N,N,Y,N,N,N,X, H,X2,N,Y,N,N,N,N,Y,N), FCVT_WU_H-> List(N,N,Y,N,N,N,X, H,X2,N,Y,N,N,N,N,Y,N), FCVT_L_H -> List(N,N,Y,N,N,N,X, H,X2,N,Y,N,N,N,N,Y,N), FCVT_LU_H-> List(N,N,Y,N,N,N,X, H,X2,N,Y,N,N,N,N,Y,N), FCVT_S_H -> List(N,Y,Y,N,N,N,X, H, S,N,N,Y,N,N,N,Y,N), FCVT_H_S -> List(N,Y,Y,N,N,N,X, S, H,N,N,Y,N,N,N,Y,N), FEQ_H -> List(N,N,Y,Y,N,N,N, H, H,N,Y,N,N,N,N,Y,N), FLT_H -> List(N,N,Y,Y,N,N,N, H, H,N,Y,N,N,N,N,Y,N), FLE_H -> List(N,N,Y,Y,N,N,N, H, H,N,Y,N,N,N,N,Y,N), FSGNJ_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,Y,N,N,N,N,N), FSGNJN_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,Y,N,N,N,N,N), FSGNJX_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,Y,N,N,N,N,N), FMIN_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,Y,N,N,N,Y,N), FMAX_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,Y,N,N,N,Y,N), FADD_H -> List(N,Y,Y,Y,N,N,Y, H, H,N,N,N,Y,N,N,Y,N), FSUB_H -> List(N,Y,Y,Y,N,N,Y, H, H,N,N,N,Y,N,N,Y,N), FMUL_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,N,Y,N,N,Y,N), FMADD_H -> List(N,Y,Y,Y,Y,N,N, H, H,N,N,N,Y,N,N,Y,N), FMSUB_H -> List(N,Y,Y,Y,Y,N,N, H, H,N,N,N,Y,N,N,Y,N), FNMADD_H -> List(N,Y,Y,Y,Y,N,N, H, H,N,N,N,Y,N,N,Y,N), FNMSUB_H -> List(N,Y,Y,Y,Y,N,N, H, H,N,N,N,Y,N,N,Y,N), FDIV_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,N,N,Y,N,Y,N), FSQRT_H -> List(N,Y,Y,N,N,N,X, H, H,N,N,N,N,N,Y,Y,N)) val f: Array[(BitPat, List[BitPat])] = Array(FLW -> List(Y,Y,N,N,N,X,X,X2,X2,N,N,N,N,N,N,N,N), FSW -> List(Y,N,N,Y,N,Y,X, I, S,N,Y,N,N,N,N,N,N), FMV_W_X -> List(N,Y,N,N,N,X,X, S, I,Y,N,N,N,N,N,N,N), FCVT_S_W -> List(N,Y,N,N,N,X,X, S, S,Y,N,N,N,N,N,Y,N), FCVT_S_WU-> List(N,Y,N,N,N,X,X, S, S,Y,N,N,N,N,N,Y,N), FCVT_S_L -> List(N,Y,N,N,N,X,X, S, S,Y,N,N,N,N,N,Y,N), FCVT_S_LU-> List(N,Y,N,N,N,X,X, S, S,Y,N,N,N,N,N,Y,N), FMV_X_W -> List(N,N,Y,N,N,N,X, I, S,N,Y,N,N,N,N,N,N), FCLASS_S -> List(N,N,Y,N,N,N,X, S, S,N,Y,N,N,N,N,N,N), FCVT_W_S -> List(N,N,Y,N,N,N,X, S,X2,N,Y,N,N,N,N,Y,N), FCVT_WU_S-> List(N,N,Y,N,N,N,X, S,X2,N,Y,N,N,N,N,Y,N), FCVT_L_S -> List(N,N,Y,N,N,N,X, S,X2,N,Y,N,N,N,N,Y,N), FCVT_LU_S-> List(N,N,Y,N,N,N,X, S,X2,N,Y,N,N,N,N,Y,N), FEQ_S -> List(N,N,Y,Y,N,N,N, S, S,N,Y,N,N,N,N,Y,N), FLT_S -> List(N,N,Y,Y,N,N,N, S, S,N,Y,N,N,N,N,Y,N), FLE_S -> List(N,N,Y,Y,N,N,N, S, S,N,Y,N,N,N,N,Y,N), FSGNJ_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,Y,N,N,N,N,N), FSGNJN_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,Y,N,N,N,N,N), FSGNJX_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,Y,N,N,N,N,N), FMIN_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,Y,N,N,N,Y,N), FMAX_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,Y,N,N,N,Y,N), FADD_S -> List(N,Y,Y,Y,N,N,Y, S, S,N,N,N,Y,N,N,Y,N), FSUB_S -> List(N,Y,Y,Y,N,N,Y, S, S,N,N,N,Y,N,N,Y,N), FMUL_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,N,Y,N,N,Y,N), FMADD_S -> List(N,Y,Y,Y,Y,N,N, S, S,N,N,N,Y,N,N,Y,N), FMSUB_S -> List(N,Y,Y,Y,Y,N,N, S, S,N,N,N,Y,N,N,Y,N), FNMADD_S -> List(N,Y,Y,Y,Y,N,N, S, S,N,N,N,Y,N,N,Y,N), FNMSUB_S -> List(N,Y,Y,Y,Y,N,N, S, S,N,N,N,Y,N,N,Y,N), FDIV_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,N,N,Y,N,Y,N), FSQRT_S -> List(N,Y,Y,N,N,N,X, S, S,N,N,N,N,N,Y,Y,N)) val d: Array[(BitPat, List[BitPat])] = Array(FLD -> List(Y,Y,N,N,N,X,X,X2,X2,N,N,N,N,N,N,N,N), FSD -> List(Y,N,N,Y,N,Y,X, I, D,N,Y,N,N,N,N,N,N), FMV_D_X -> List(N,Y,N,N,N,X,X, D, I,Y,N,N,N,N,N,N,N), FCVT_D_W -> List(N,Y,N,N,N,X,X, D, D,Y,N,N,N,N,N,Y,N), FCVT_D_WU-> List(N,Y,N,N,N,X,X, D, D,Y,N,N,N,N,N,Y,N), FCVT_D_L -> List(N,Y,N,N,N,X,X, D, D,Y,N,N,N,N,N,Y,N), FCVT_D_LU-> List(N,Y,N,N,N,X,X, D, D,Y,N,N,N,N,N,Y,N), FMV_X_D -> List(N,N,Y,N,N,N,X, I, D,N,Y,N,N,N,N,N,N), FCLASS_D -> List(N,N,Y,N,N,N,X, D, D,N,Y,N,N,N,N,N,N), FCVT_W_D -> List(N,N,Y,N,N,N,X, D,X2,N,Y,N,N,N,N,Y,N), FCVT_WU_D-> List(N,N,Y,N,N,N,X, D,X2,N,Y,N,N,N,N,Y,N), FCVT_L_D -> List(N,N,Y,N,N,N,X, D,X2,N,Y,N,N,N,N,Y,N), FCVT_LU_D-> List(N,N,Y,N,N,N,X, D,X2,N,Y,N,N,N,N,Y,N), FCVT_S_D -> List(N,Y,Y,N,N,N,X, D, S,N,N,Y,N,N,N,Y,N), FCVT_D_S -> List(N,Y,Y,N,N,N,X, S, D,N,N,Y,N,N,N,Y,N), FEQ_D -> List(N,N,Y,Y,N,N,N, D, D,N,Y,N,N,N,N,Y,N), FLT_D -> List(N,N,Y,Y,N,N,N, D, D,N,Y,N,N,N,N,Y,N), FLE_D -> List(N,N,Y,Y,N,N,N, D, D,N,Y,N,N,N,N,Y,N), FSGNJ_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,Y,N,N,N,N,N), FSGNJN_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,Y,N,N,N,N,N), FSGNJX_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,Y,N,N,N,N,N), FMIN_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,Y,N,N,N,Y,N), FMAX_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,Y,N,N,N,Y,N), FADD_D -> List(N,Y,Y,Y,N,N,Y, D, D,N,N,N,Y,N,N,Y,N), FSUB_D -> List(N,Y,Y,Y,N,N,Y, D, D,N,N,N,Y,N,N,Y,N), FMUL_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,N,Y,N,N,Y,N), FMADD_D -> List(N,Y,Y,Y,Y,N,N, D, D,N,N,N,Y,N,N,Y,N), FMSUB_D -> List(N,Y,Y,Y,Y,N,N, D, D,N,N,N,Y,N,N,Y,N), FNMADD_D -> List(N,Y,Y,Y,Y,N,N, D, D,N,N,N,Y,N,N,Y,N), FNMSUB_D -> List(N,Y,Y,Y,Y,N,N, D, D,N,N,N,Y,N,N,Y,N), FDIV_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,N,N,Y,N,Y,N), FSQRT_D -> List(N,Y,Y,N,N,N,X, D, D,N,N,N,N,N,Y,Y,N)) val fcvt_hd: Array[(BitPat, List[BitPat])] = Array(FCVT_H_D -> List(N,Y,Y,N,N,N,X, D, H,N,N,Y,N,N,N,Y,N), FCVT_D_H -> List(N,Y,Y,N,N,N,X, H, D,N,N,Y,N,N,N,Y,N)) val vfmv_f_s: Array[(BitPat, List[BitPat])] = Array(VFMV_F_S -> List(N,Y,N,N,N,N,X,X2,X2,N,N,N,N,N,N,N,Y)) val insns = ((minFLen, fLen) match { case (32, 32) => f case (16, 32) => h ++ f case (32, 64) => f ++ d case (16, 64) => h ++ f ++ d ++ fcvt_hd case other => throw new Exception(s"minFLen = ${minFLen} & fLen = ${fLen} is an unsupported configuration") }) ++ (if (usingVector) vfmv_f_s else Array[(BitPat, List[BitPat])]()) val decoder = DecodeLogic(io.inst, default, insns) val s = io.sigs val sigs = Seq(s.ldst, s.wen, s.ren1, s.ren2, s.ren3, s.swap12, s.swap23, s.typeTagIn, s.typeTagOut, s.fromint, s.toint, s.fastpipe, s.fma, s.div, s.sqrt, s.wflags, s.vec) sigs zip decoder map {case(s,d) => s := d} } class FPUCoreIO(implicit p: Parameters) extends CoreBundle()(p) { val hartid = Input(UInt(hartIdLen.W)) val time = Input(UInt(xLen.W)) val inst = Input(Bits(32.W)) val fromint_data = Input(Bits(xLen.W)) val fcsr_rm = Input(Bits(FPConstants.RM_SZ.W)) val fcsr_flags = Valid(Bits(FPConstants.FLAGS_SZ.W)) val v_sew = Input(UInt(3.W)) val store_data = Output(Bits(fLen.W)) val toint_data = Output(Bits(xLen.W)) val ll_resp_val = Input(Bool()) val ll_resp_type = Input(Bits(3.W)) val ll_resp_tag = Input(UInt(5.W)) val ll_resp_data = Input(Bits(fLen.W)) val valid = Input(Bool()) val fcsr_rdy = Output(Bool()) val nack_mem = Output(Bool()) val illegal_rm = Output(Bool()) val killx = Input(Bool()) val killm = Input(Bool()) val dec = Output(new FPUCtrlSigs()) val sboard_set = Output(Bool()) val sboard_clr = Output(Bool()) val sboard_clra = Output(UInt(5.W)) val keep_clock_enabled = Input(Bool()) } class FPUIO(implicit p: Parameters) extends FPUCoreIO ()(p) { val cp_req = Flipped(Decoupled(new FPInput())) //cp doesn't pay attn to kill sigs val cp_resp = Decoupled(new FPResult()) } class FPResult(implicit p: Parameters) extends CoreBundle()(p) { val data = Bits((fLen+1).W) val exc = Bits(FPConstants.FLAGS_SZ.W) } class IntToFPInput(implicit p: Parameters) extends CoreBundle()(p) with HasFPUCtrlSigs { val rm = Bits(FPConstants.RM_SZ.W) val typ = Bits(2.W) val in1 = Bits(xLen.W) } class FPInput(implicit p: Parameters) extends CoreBundle()(p) with HasFPUCtrlSigs { val rm = Bits(FPConstants.RM_SZ.W) val fmaCmd = Bits(2.W) val typ = Bits(2.W) val fmt = Bits(2.W) val in1 = Bits((fLen+1).W) val in2 = Bits((fLen+1).W) val in3 = Bits((fLen+1).W) } case class FType(exp: Int, sig: Int) { def ieeeWidth = exp + sig def recodedWidth = ieeeWidth + 1 def ieeeQNaN = ((BigInt(1) << (ieeeWidth - 1)) - (BigInt(1) << (sig - 2))).U(ieeeWidth.W) def qNaN = ((BigInt(7) << (exp + sig - 3)) + (BigInt(1) << (sig - 2))).U(recodedWidth.W) def isNaN(x: UInt) = x(sig + exp - 1, sig + exp - 3).andR def isSNaN(x: UInt) = isNaN(x) && !x(sig - 2) def classify(x: UInt) = { val sign = x(sig + exp) val code = x(exp + sig - 1, exp + sig - 3) val codeHi = code(2, 1) val isSpecial = codeHi === 3.U val isHighSubnormalIn = x(exp + sig - 3, sig - 1) < 2.U val isSubnormal = code === 1.U || codeHi === 1.U && isHighSubnormalIn val isNormal = codeHi === 1.U && !isHighSubnormalIn || codeHi === 2.U val isZero = code === 0.U val isInf = isSpecial && !code(0) val isNaN = code.andR val isSNaN = isNaN && !x(sig-2) val isQNaN = isNaN && x(sig-2) Cat(isQNaN, isSNaN, isInf && !sign, isNormal && !sign, isSubnormal && !sign, isZero && !sign, isZero && sign, isSubnormal && sign, isNormal && sign, isInf && sign) } // convert between formats, ignoring rounding, range, NaN def unsafeConvert(x: UInt, to: FType) = if (this == to) x else { val sign = x(sig + exp) val fractIn = x(sig - 2, 0) val expIn = x(sig + exp - 1, sig - 1) val fractOut = fractIn << to.sig >> sig val expOut = { val expCode = expIn(exp, exp - 2) val commonCase = (expIn + (1 << to.exp).U) - (1 << exp).U Mux(expCode === 0.U || expCode >= 6.U, Cat(expCode, commonCase(to.exp - 3, 0)), commonCase(to.exp, 0)) } Cat(sign, expOut, fractOut) } private def ieeeBundle = { val expWidth = exp class IEEEBundle extends Bundle { val sign = Bool() val exp = UInt(expWidth.W) val sig = UInt((ieeeWidth-expWidth-1).W) } new IEEEBundle } def unpackIEEE(x: UInt) = x.asTypeOf(ieeeBundle) def recode(x: UInt) = hardfloat.recFNFromFN(exp, sig, x) def ieee(x: UInt) = hardfloat.fNFromRecFN(exp, sig, x) } object FType { val H = new FType(5, 11) val S = new FType(8, 24) val D = new FType(11, 53) val all = List(H, S, D) } trait HasFPUParameters { require(fLen == 0 || FType.all.exists(_.ieeeWidth == fLen)) val minFLen: Int val fLen: Int def xLen: Int val minXLen = 32 val nIntTypes = log2Ceil(xLen/minXLen) + 1 def floatTypes = FType.all.filter(t => minFLen <= t.ieeeWidth && t.ieeeWidth <= fLen) def minType = floatTypes.head def maxType = floatTypes.last def prevType(t: FType) = floatTypes(typeTag(t) - 1) def maxExpWidth = maxType.exp def maxSigWidth = maxType.sig def typeTag(t: FType) = floatTypes.indexOf(t) def typeTagWbOffset = (FType.all.indexOf(minType) + 1).U def typeTagGroup(t: FType) = (if (floatTypes.contains(t)) typeTag(t) else typeTag(maxType)).U // typeTag def H = typeTagGroup(FType.H) def S = typeTagGroup(FType.S) def D = typeTagGroup(FType.D) def I = typeTag(maxType).U private def isBox(x: UInt, t: FType): Bool = x(t.sig + t.exp, t.sig + t.exp - 4).andR private def box(x: UInt, xt: FType, y: UInt, yt: FType): UInt = { require(xt.ieeeWidth == 2 * yt.ieeeWidth) val swizzledNaN = Cat( x(xt.sig + xt.exp, xt.sig + xt.exp - 3), x(xt.sig - 2, yt.recodedWidth - 1).andR, x(xt.sig + xt.exp - 5, xt.sig), y(yt.recodedWidth - 2), x(xt.sig - 2, yt.recodedWidth - 1), y(yt.recodedWidth - 1), y(yt.recodedWidth - 3, 0)) Mux(xt.isNaN(x), swizzledNaN, x) } // implement NaN unboxing for FU inputs def unbox(x: UInt, tag: UInt, exactType: Option[FType]): UInt = { val outType = exactType.getOrElse(maxType) def helper(x: UInt, t: FType): Seq[(Bool, UInt)] = { val prev = if (t == minType) { Seq() } else { val prevT = prevType(t) val unswizzled = Cat( x(prevT.sig + prevT.exp - 1), x(t.sig - 1), x(prevT.sig + prevT.exp - 2, 0)) val prev = helper(unswizzled, prevT) val isbox = isBox(x, t) prev.map(p => (isbox && p._1, p._2)) } prev :+ (true.B, t.unsafeConvert(x, outType)) } val (oks, floats) = helper(x, maxType).unzip if (exactType.isEmpty || floatTypes.size == 1) { Mux(oks(tag), floats(tag), maxType.qNaN) } else { val t = exactType.get floats(typeTag(t)) | Mux(oks(typeTag(t)), 0.U, t.qNaN) } } // make sure that the redundant bits in the NaN-boxed encoding are consistent def consistent(x: UInt): Bool = { def helper(x: UInt, t: FType): Bool = if (typeTag(t) == 0) true.B else { val prevT = prevType(t) val unswizzled = Cat( x(prevT.sig + prevT.exp - 1), x(t.sig - 1), x(prevT.sig + prevT.exp - 2, 0)) val prevOK = !isBox(x, t) || helper(unswizzled, prevT) val curOK = !t.isNaN(x) || x(t.sig + t.exp - 4) === x(t.sig - 2, prevT.recodedWidth - 1).andR prevOK && curOK } helper(x, maxType) } // generate a NaN box from an FU result def box(x: UInt, t: FType): UInt = { if (t == maxType) { x } else { val nt = floatTypes(typeTag(t) + 1) val bigger = box(((BigInt(1) << nt.recodedWidth)-1).U, nt, x, t) bigger | ((BigInt(1) << maxType.recodedWidth) - (BigInt(1) << nt.recodedWidth)).U } } // generate a NaN box from an FU result def box(x: UInt, tag: UInt): UInt = { val opts = floatTypes.map(t => box(x, t)) opts(tag) } // zap bits that hardfloat thinks are don't-cares, but we do care about def sanitizeNaN(x: UInt, t: FType): UInt = { if (typeTag(t) == 0) { x } else { val maskedNaN = x & ~((BigInt(1) << (t.sig-1)) | (BigInt(1) << (t.sig+t.exp-4))).U(t.recodedWidth.W) Mux(t.isNaN(x), maskedNaN, x) } } // implement NaN boxing and recoding for FL*/fmv.*.x def recode(x: UInt, tag: UInt): UInt = { def helper(x: UInt, t: FType): UInt = { if (typeTag(t) == 0) { t.recode(x) } else { val prevT = prevType(t) box(t.recode(x), t, helper(x, prevT), prevT) } } // fill MSBs of subword loads to emulate a wider load of a NaN-boxed value val boxes = floatTypes.map(t => ((BigInt(1) << maxType.ieeeWidth) - (BigInt(1) << t.ieeeWidth)).U) helper(boxes(tag) | x, maxType) } // implement NaN unboxing and un-recoding for FS*/fmv.x.* def ieee(x: UInt, t: FType = maxType): UInt = { if (typeTag(t) == 0) { t.ieee(x) } else { val unrecoded = t.ieee(x) val prevT = prevType(t) val prevRecoded = Cat( x(prevT.recodedWidth-2), x(t.sig-1), x(prevT.recodedWidth-3, 0)) val prevUnrecoded = ieee(prevRecoded, prevT) Cat(unrecoded >> prevT.ieeeWidth, Mux(t.isNaN(x), prevUnrecoded, unrecoded(prevT.ieeeWidth-1, 0))) } } } abstract class FPUModule(implicit val p: Parameters) extends Module with HasCoreParameters with HasFPUParameters class FPToInt(implicit p: Parameters) extends FPUModule()(p) with ShouldBeRetimed { class Output extends Bundle { val in = new FPInput val lt = Bool() val store = Bits(fLen.W) val toint = Bits(xLen.W) val exc = Bits(FPConstants.FLAGS_SZ.W) } val io = IO(new Bundle { val in = Flipped(Valid(new FPInput)) val out = Valid(new Output) }) val in = RegEnable(io.in.bits, io.in.valid) val valid = RegNext(io.in.valid) val dcmp = Module(new hardfloat.CompareRecFN(maxExpWidth, maxSigWidth)) dcmp.io.a := in.in1 dcmp.io.b := in.in2 dcmp.io.signaling := !in.rm(1) val tag = in.typeTagOut val toint_ieee = (floatTypes.map(t => if (t == FType.H) Fill(maxType.ieeeWidth / minXLen, ieee(in.in1)(15, 0).sextTo(minXLen)) else Fill(maxType.ieeeWidth / t.ieeeWidth, ieee(in.in1)(t.ieeeWidth - 1, 0))): Seq[UInt])(tag) val toint = WireDefault(toint_ieee) val intType = WireDefault(in.fmt(0)) io.out.bits.store := (floatTypes.map(t => Fill(fLen / t.ieeeWidth, ieee(in.in1)(t.ieeeWidth - 1, 0))): Seq[UInt])(tag) io.out.bits.toint := ((0 until nIntTypes).map(i => toint((minXLen << i) - 1, 0).sextTo(xLen)): Seq[UInt])(intType) io.out.bits.exc := 0.U when (in.rm(0)) { val classify_out = (floatTypes.map(t => t.classify(maxType.unsafeConvert(in.in1, t))): Seq[UInt])(tag) toint := classify_out | (toint_ieee >> minXLen << minXLen) intType := false.B } when (in.wflags) { // feq/flt/fle, fcvt toint := (~in.rm & Cat(dcmp.io.lt, dcmp.io.eq)).orR | (toint_ieee >> minXLen << minXLen) io.out.bits.exc := dcmp.io.exceptionFlags intType := false.B when (!in.ren2) { // fcvt val cvtType = in.typ.extract(log2Ceil(nIntTypes), 1) intType := cvtType val conv = Module(new hardfloat.RecFNToIN(maxExpWidth, maxSigWidth, xLen)) conv.io.in := in.in1 conv.io.roundingMode := in.rm conv.io.signedOut := ~in.typ(0) toint := conv.io.out io.out.bits.exc := Cat(conv.io.intExceptionFlags(2, 1).orR, 0.U(3.W), conv.io.intExceptionFlags(0)) for (i <- 0 until nIntTypes-1) { val w = minXLen << i when (cvtType === i.U) { val narrow = Module(new hardfloat.RecFNToIN(maxExpWidth, maxSigWidth, w)) narrow.io.in := in.in1 narrow.io.roundingMode := in.rm narrow.io.signedOut := ~in.typ(0) val excSign = in.in1(maxExpWidth + maxSigWidth) && !maxType.isNaN(in.in1) val excOut = Cat(conv.io.signedOut === excSign, Fill(w-1, !excSign)) val invalid = conv.io.intExceptionFlags(2) || narrow.io.intExceptionFlags(1) when (invalid) { toint := Cat(conv.io.out >> w, excOut) } io.out.bits.exc := Cat(invalid, 0.U(3.W), !invalid && conv.io.intExceptionFlags(0)) } } } } io.out.valid := valid io.out.bits.lt := dcmp.io.lt || (dcmp.io.a.asSInt < 0.S && dcmp.io.b.asSInt >= 0.S) io.out.bits.in := in } class IntToFP(val latency: Int)(implicit p: Parameters) extends FPUModule()(p) with ShouldBeRetimed { val io = IO(new Bundle { val in = Flipped(Valid(new IntToFPInput)) val out = Valid(new FPResult) }) val in = Pipe(io.in) val tag = in.bits.typeTagIn val mux = Wire(new FPResult) mux.exc := 0.U mux.data := recode(in.bits.in1, tag) val intValue = { val res = WireDefault(in.bits.in1.asSInt) for (i <- 0 until nIntTypes-1) { val smallInt = in.bits.in1((minXLen << i) - 1, 0) when (in.bits.typ.extract(log2Ceil(nIntTypes), 1) === i.U) { res := Mux(in.bits.typ(0), smallInt.zext, smallInt.asSInt) } } res.asUInt } when (in.bits.wflags) { // fcvt // could be improved for RVD/RVQ with a single variable-position rounding // unit, rather than N fixed-position ones val i2fResults = for (t <- floatTypes) yield { val i2f = Module(new hardfloat.INToRecFN(xLen, t.exp, t.sig)) i2f.io.signedIn := ~in.bits.typ(0) i2f.io.in := intValue i2f.io.roundingMode := in.bits.rm i2f.io.detectTininess := hardfloat.consts.tininess_afterRounding (sanitizeNaN(i2f.io.out, t), i2f.io.exceptionFlags) } val (data, exc) = i2fResults.unzip val dataPadded = data.init.map(d => Cat(data.last >> d.getWidth, d)) :+ data.last mux.data := dataPadded(tag) mux.exc := exc(tag) } io.out <> Pipe(in.valid, mux, latency-1) } class FPToFP(val latency: Int)(implicit p: Parameters) extends FPUModule()(p) with ShouldBeRetimed { val io = IO(new Bundle { val in = Flipped(Valid(new FPInput)) val out = Valid(new FPResult) val lt = Input(Bool()) // from FPToInt }) val in = Pipe(io.in) val signNum = Mux(in.bits.rm(1), in.bits.in1 ^ in.bits.in2, Mux(in.bits.rm(0), ~in.bits.in2, in.bits.in2)) val fsgnj = Cat(signNum(fLen), in.bits.in1(fLen-1, 0)) val fsgnjMux = Wire(new FPResult) fsgnjMux.exc := 0.U fsgnjMux.data := fsgnj when (in.bits.wflags) { // fmin/fmax val isnan1 = maxType.isNaN(in.bits.in1) val isnan2 = maxType.isNaN(in.bits.in2) val isInvalid = maxType.isSNaN(in.bits.in1) || maxType.isSNaN(in.bits.in2) val isNaNOut = isnan1 && isnan2 val isLHS = isnan2 || in.bits.rm(0) =/= io.lt && !isnan1 fsgnjMux.exc := isInvalid << 4 fsgnjMux.data := Mux(isNaNOut, maxType.qNaN, Mux(isLHS, in.bits.in1, in.bits.in2)) } val inTag = in.bits.typeTagIn val outTag = in.bits.typeTagOut val mux = WireDefault(fsgnjMux) for (t <- floatTypes.init) { when (outTag === typeTag(t).U) { mux.data := Cat(fsgnjMux.data >> t.recodedWidth, maxType.unsafeConvert(fsgnjMux.data, t)) } } when (in.bits.wflags && !in.bits.ren2) { // fcvt if (floatTypes.size > 1) { // widening conversions simply canonicalize NaN operands val widened = Mux(maxType.isNaN(in.bits.in1), maxType.qNaN, in.bits.in1) fsgnjMux.data := widened fsgnjMux.exc := maxType.isSNaN(in.bits.in1) << 4 // narrowing conversions require rounding (for RVQ, this could be // optimized to use a single variable-position rounding unit, rather // than two fixed-position ones) for (outType <- floatTypes.init) when (outTag === typeTag(outType).U && ((typeTag(outType) == 0).B || outTag < inTag)) { val narrower = Module(new hardfloat.RecFNToRecFN(maxType.exp, maxType.sig, outType.exp, outType.sig)) narrower.io.in := in.bits.in1 narrower.io.roundingMode := in.bits.rm narrower.io.detectTininess := hardfloat.consts.tininess_afterRounding val narrowed = sanitizeNaN(narrower.io.out, outType) mux.data := Cat(fsgnjMux.data >> narrowed.getWidth, narrowed) mux.exc := narrower.io.exceptionFlags } } } io.out <> Pipe(in.valid, mux, latency-1) } class MulAddRecFNPipe(latency: Int, expWidth: Int, sigWidth: Int) extends Module { override def desiredName = s"MulAddRecFNPipe_l${latency}_e${expWidth}_s${sigWidth}" require(latency<=2) val io = IO(new Bundle { val validin = Input(Bool()) val op = Input(Bits(2.W)) val a = Input(Bits((expWidth + sigWidth + 1).W)) val b = Input(Bits((expWidth + sigWidth + 1).W)) val c = Input(Bits((expWidth + sigWidth + 1).W)) val roundingMode = Input(UInt(3.W)) val detectTininess = Input(UInt(1.W)) val out = Output(Bits((expWidth + sigWidth + 1).W)) val exceptionFlags = Output(Bits(5.W)) val validout = Output(Bool()) }) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val mulAddRecFNToRaw_preMul = Module(new hardfloat.MulAddRecFNToRaw_preMul(expWidth, sigWidth)) val mulAddRecFNToRaw_postMul = Module(new hardfloat.MulAddRecFNToRaw_postMul(expWidth, sigWidth)) mulAddRecFNToRaw_preMul.io.op := io.op mulAddRecFNToRaw_preMul.io.a := io.a mulAddRecFNToRaw_preMul.io.b := io.b mulAddRecFNToRaw_preMul.io.c := io.c val mulAddResult = (mulAddRecFNToRaw_preMul.io.mulAddA * mulAddRecFNToRaw_preMul.io.mulAddB) +& mulAddRecFNToRaw_preMul.io.mulAddC val valid_stage0 = Wire(Bool()) val roundingMode_stage0 = Wire(UInt(3.W)) val detectTininess_stage0 = Wire(UInt(1.W)) val postmul_regs = if(latency>0) 1 else 0 mulAddRecFNToRaw_postMul.io.fromPreMul := Pipe(io.validin, mulAddRecFNToRaw_preMul.io.toPostMul, postmul_regs).bits mulAddRecFNToRaw_postMul.io.mulAddResult := Pipe(io.validin, mulAddResult, postmul_regs).bits mulAddRecFNToRaw_postMul.io.roundingMode := Pipe(io.validin, io.roundingMode, postmul_regs).bits roundingMode_stage0 := Pipe(io.validin, io.roundingMode, postmul_regs).bits detectTininess_stage0 := Pipe(io.validin, io.detectTininess, postmul_regs).bits valid_stage0 := Pipe(io.validin, false.B, postmul_regs).valid //------------------------------------------------------------------------ //------------------------------------------------------------------------ val roundRawFNToRecFN = Module(new hardfloat.RoundRawFNToRecFN(expWidth, sigWidth, 0)) val round_regs = if(latency==2) 1 else 0 roundRawFNToRecFN.io.invalidExc := Pipe(valid_stage0, mulAddRecFNToRaw_postMul.io.invalidExc, round_regs).bits roundRawFNToRecFN.io.in := Pipe(valid_stage0, mulAddRecFNToRaw_postMul.io.rawOut, round_regs).bits roundRawFNToRecFN.io.roundingMode := Pipe(valid_stage0, roundingMode_stage0, round_regs).bits roundRawFNToRecFN.io.detectTininess := Pipe(valid_stage0, detectTininess_stage0, round_regs).bits io.validout := Pipe(valid_stage0, false.B, round_regs).valid roundRawFNToRecFN.io.infiniteExc := false.B io.out := roundRawFNToRecFN.io.out io.exceptionFlags := roundRawFNToRecFN.io.exceptionFlags } class FPUFMAPipe(val latency: Int, val t: FType) (implicit p: Parameters) extends FPUModule()(p) with ShouldBeRetimed { override def desiredName = s"FPUFMAPipe_l${latency}_f${t.ieeeWidth}" require(latency>0) val io = IO(new Bundle { val in = Flipped(Valid(new FPInput)) val out = Valid(new FPResult) }) val valid = RegNext(io.in.valid) val in = Reg(new FPInput) when (io.in.valid) { val one = 1.U << (t.sig + t.exp - 1) val zero = (io.in.bits.in1 ^ io.in.bits.in2) & (1.U << (t.sig + t.exp)) val cmd_fma = io.in.bits.ren3 val cmd_addsub = io.in.bits.swap23 in := io.in.bits when (cmd_addsub) { in.in2 := one } when (!(cmd_fma || cmd_addsub)) { in.in3 := zero } } val fma = Module(new MulAddRecFNPipe((latency-1) min 2, t.exp, t.sig)) fma.io.validin := valid fma.io.op := in.fmaCmd fma.io.roundingMode := in.rm fma.io.detectTininess := hardfloat.consts.tininess_afterRounding fma.io.a := in.in1 fma.io.b := in.in2 fma.io.c := in.in3 val res = Wire(new FPResult) res.data := sanitizeNaN(fma.io.out, t) res.exc := fma.io.exceptionFlags io.out := Pipe(fma.io.validout, res, (latency-3) max 0) } class FPU(cfg: FPUParams)(implicit p: Parameters) extends FPUModule()(p) { val io = IO(new FPUIO) val (useClockGating, useDebugROB) = coreParams match { case r: RocketCoreParams => val sz = if (r.debugROB.isDefined) r.debugROB.get.size else 1 (r.clockGate, sz < 1) case _ => (false, false) } val clock_en_reg = Reg(Bool()) val clock_en = clock_en_reg || io.cp_req.valid val gated_clock = if (!useClockGating) clock else ClockGate(clock, clock_en, "fpu_clock_gate") val fp_decoder = Module(new FPUDecoder) fp_decoder.io.inst := io.inst val id_ctrl = WireInit(fp_decoder.io.sigs) coreParams match { case r: RocketCoreParams => r.vector.map(v => { val v_decode = v.decoder(p) // Only need to get ren1 v_decode.io.inst := io.inst v_decode.io.vconfig := DontCare // core deals with this when (v_decode.io.legal && v_decode.io.read_frs1) { id_ctrl.ren1 := true.B id_ctrl.swap12 := false.B id_ctrl.toint := true.B id_ctrl.typeTagIn := I id_ctrl.typeTagOut := Mux(io.v_sew === 3.U, D, S) } when (v_decode.io.write_frd) { id_ctrl.wen := true.B } })} val ex_reg_valid = RegNext(io.valid, false.B) val ex_reg_inst = RegEnable(io.inst, io.valid) val ex_reg_ctrl = RegEnable(id_ctrl, io.valid) val ex_ra = List.fill(3)(Reg(UInt())) // load/vector response val load_wb = RegNext(io.ll_resp_val) val load_wb_typeTag = RegEnable(io.ll_resp_type(1,0) - typeTagWbOffset, io.ll_resp_val) val load_wb_data = RegEnable(io.ll_resp_data, io.ll_resp_val) val load_wb_tag = RegEnable(io.ll_resp_tag, io.ll_resp_val) class FPUImpl { // entering gated-clock domain val req_valid = ex_reg_valid || io.cp_req.valid val ex_cp_valid = io.cp_req.fire val mem_cp_valid = RegNext(ex_cp_valid, false.B) val wb_cp_valid = RegNext(mem_cp_valid, false.B) val mem_reg_valid = RegInit(false.B) val killm = (io.killm || io.nack_mem) && !mem_cp_valid // Kill X-stage instruction if M-stage is killed. This prevents it from // speculatively being sent to the div-sqrt unit, which can cause priority // inversion for two back-to-back divides, the first of which is killed. val killx = io.killx || mem_reg_valid && killm mem_reg_valid := ex_reg_valid && !killx || ex_cp_valid val mem_reg_inst = RegEnable(ex_reg_inst, ex_reg_valid) val wb_reg_valid = RegNext(mem_reg_valid && (!killm || mem_cp_valid), false.B) val cp_ctrl = Wire(new FPUCtrlSigs) cp_ctrl :<>= io.cp_req.bits.viewAsSupertype(new FPUCtrlSigs) io.cp_resp.valid := false.B io.cp_resp.bits.data := 0.U io.cp_resp.bits.exc := DontCare val ex_ctrl = Mux(ex_cp_valid, cp_ctrl, ex_reg_ctrl) val mem_ctrl = RegEnable(ex_ctrl, req_valid) val wb_ctrl = RegEnable(mem_ctrl, mem_reg_valid) // CoreMonitorBundle to monitor fp register file writes val frfWriteBundle = Seq.fill(2)(WireInit(new CoreMonitorBundle(xLen, fLen), DontCare)) frfWriteBundle.foreach { i => i.clock := clock i.reset := reset i.hartid := io.hartid i.timer := io.time(31,0) i.valid := false.B i.wrenx := false.B i.wrenf := false.B i.excpt := false.B } // regfile val regfile = Mem(32, Bits((fLen+1).W)) when (load_wb) { val wdata = recode(load_wb_data, load_wb_typeTag) regfile(load_wb_tag) := wdata assert(consistent(wdata)) if (enableCommitLog) printf("f%d p%d 0x%x\n", load_wb_tag, load_wb_tag + 32.U, ieee(wdata)) if (useDebugROB) DebugROB.pushWb(clock, reset, io.hartid, load_wb, load_wb_tag + 32.U, ieee(wdata)) frfWriteBundle(0).wrdst := load_wb_tag frfWriteBundle(0).wrenf := true.B frfWriteBundle(0).wrdata := ieee(wdata) } val ex_rs = ex_ra.map(a => regfile(a)) when (io.valid) { when (id_ctrl.ren1) { when (!id_ctrl.swap12) { ex_ra(0) := io.inst(19,15) } when (id_ctrl.swap12) { ex_ra(1) := io.inst(19,15) } } when (id_ctrl.ren2) { when (id_ctrl.swap12) { ex_ra(0) := io.inst(24,20) } when (id_ctrl.swap23) { ex_ra(2) := io.inst(24,20) } when (!id_ctrl.swap12 && !id_ctrl.swap23) { ex_ra(1) := io.inst(24,20) } } when (id_ctrl.ren3) { ex_ra(2) := io.inst(31,27) } } val ex_rm = Mux(ex_reg_inst(14,12) === 7.U, io.fcsr_rm, ex_reg_inst(14,12)) def fuInput(minT: Option[FType]): FPInput = { val req = Wire(new FPInput) val tag = ex_ctrl.typeTagIn req.viewAsSupertype(new Bundle with HasFPUCtrlSigs) :#= ex_ctrl.viewAsSupertype(new Bundle with HasFPUCtrlSigs) req.rm := ex_rm req.in1 := unbox(ex_rs(0), tag, minT) req.in2 := unbox(ex_rs(1), tag, minT) req.in3 := unbox(ex_rs(2), tag, minT) req.typ := ex_reg_inst(21,20) req.fmt := ex_reg_inst(26,25) req.fmaCmd := ex_reg_inst(3,2) | (!ex_ctrl.ren3 && ex_reg_inst(27)) when (ex_cp_valid) { req := io.cp_req.bits when (io.cp_req.bits.swap12) { req.in1 := io.cp_req.bits.in2 req.in2 := io.cp_req.bits.in1 } when (io.cp_req.bits.swap23) { req.in2 := io.cp_req.bits.in3 req.in3 := io.cp_req.bits.in2 } } req } val sfma = Module(new FPUFMAPipe(cfg.sfmaLatency, FType.S)) sfma.io.in.valid := req_valid && ex_ctrl.fma && ex_ctrl.typeTagOut === S sfma.io.in.bits := fuInput(Some(sfma.t)) val fpiu = Module(new FPToInt) fpiu.io.in.valid := req_valid && (ex_ctrl.toint || ex_ctrl.div || ex_ctrl.sqrt || (ex_ctrl.fastpipe && ex_ctrl.wflags)) fpiu.io.in.bits := fuInput(None) io.store_data := fpiu.io.out.bits.store io.toint_data := fpiu.io.out.bits.toint when(fpiu.io.out.valid && mem_cp_valid && mem_ctrl.toint){ io.cp_resp.bits.data := fpiu.io.out.bits.toint io.cp_resp.valid := true.B } val ifpu = Module(new IntToFP(cfg.ifpuLatency)) ifpu.io.in.valid := req_valid && ex_ctrl.fromint ifpu.io.in.bits := fpiu.io.in.bits ifpu.io.in.bits.in1 := Mux(ex_cp_valid, io.cp_req.bits.in1, io.fromint_data) val fpmu = Module(new FPToFP(cfg.fpmuLatency)) fpmu.io.in.valid := req_valid && ex_ctrl.fastpipe fpmu.io.in.bits := fpiu.io.in.bits fpmu.io.lt := fpiu.io.out.bits.lt val divSqrt_wen = WireDefault(false.B) val divSqrt_inFlight = WireDefault(false.B) val divSqrt_waddr = Reg(UInt(5.W)) val divSqrt_cp = Reg(Bool()) val divSqrt_typeTag = Wire(UInt(log2Up(floatTypes.size).W)) val divSqrt_wdata = Wire(UInt((fLen+1).W)) val divSqrt_flags = Wire(UInt(FPConstants.FLAGS_SZ.W)) divSqrt_typeTag := DontCare divSqrt_wdata := DontCare divSqrt_flags := DontCare // writeback arbitration case class Pipe(p: Module, lat: Int, cond: (FPUCtrlSigs) => Bool, res: FPResult) val pipes = List( Pipe(fpmu, fpmu.latency, (c: FPUCtrlSigs) => c.fastpipe, fpmu.io.out.bits), Pipe(ifpu, ifpu.latency, (c: FPUCtrlSigs) => c.fromint, ifpu.io.out.bits), Pipe(sfma, sfma.latency, (c: FPUCtrlSigs) => c.fma && c.typeTagOut === S, sfma.io.out.bits)) ++ (fLen > 32).option({ val dfma = Module(new FPUFMAPipe(cfg.dfmaLatency, FType.D)) dfma.io.in.valid := req_valid && ex_ctrl.fma && ex_ctrl.typeTagOut === D dfma.io.in.bits := fuInput(Some(dfma.t)) Pipe(dfma, dfma.latency, (c: FPUCtrlSigs) => c.fma && c.typeTagOut === D, dfma.io.out.bits) }) ++ (minFLen == 16).option({ val hfma = Module(new FPUFMAPipe(cfg.sfmaLatency, FType.H)) hfma.io.in.valid := req_valid && ex_ctrl.fma && ex_ctrl.typeTagOut === H hfma.io.in.bits := fuInput(Some(hfma.t)) Pipe(hfma, hfma.latency, (c: FPUCtrlSigs) => c.fma && c.typeTagOut === H, hfma.io.out.bits) }) def latencyMask(c: FPUCtrlSigs, offset: Int) = { require(pipes.forall(_.lat >= offset)) pipes.map(p => Mux(p.cond(c), (1 << p.lat-offset).U, 0.U)).reduce(_|_) } def pipeid(c: FPUCtrlSigs) = pipes.zipWithIndex.map(p => Mux(p._1.cond(c), p._2.U, 0.U)).reduce(_|_) val maxLatency = pipes.map(_.lat).max val memLatencyMask = latencyMask(mem_ctrl, 2) class WBInfo extends Bundle { val rd = UInt(5.W) val typeTag = UInt(log2Up(floatTypes.size).W) val cp = Bool() val pipeid = UInt(log2Ceil(pipes.size).W) } val wen = RegInit(0.U((maxLatency-1).W)) val wbInfo = Reg(Vec(maxLatency-1, new WBInfo)) val mem_wen = mem_reg_valid && (mem_ctrl.fma || mem_ctrl.fastpipe || mem_ctrl.fromint) val write_port_busy = RegEnable(mem_wen && (memLatencyMask & latencyMask(ex_ctrl, 1)).orR || (wen & latencyMask(ex_ctrl, 0)).orR, req_valid) ccover(mem_reg_valid && write_port_busy, "WB_STRUCTURAL", "structural hazard on writeback") for (i <- 0 until maxLatency-2) { when (wen(i+1)) { wbInfo(i) := wbInfo(i+1) } } wen := wen >> 1 when (mem_wen) { when (!killm) { wen := wen >> 1 | memLatencyMask } for (i <- 0 until maxLatency-1) { when (!write_port_busy && memLatencyMask(i)) { wbInfo(i).cp := mem_cp_valid wbInfo(i).typeTag := mem_ctrl.typeTagOut wbInfo(i).pipeid := pipeid(mem_ctrl) wbInfo(i).rd := mem_reg_inst(11,7) } } } val waddr = Mux(divSqrt_wen, divSqrt_waddr, wbInfo(0).rd) val wb_cp = Mux(divSqrt_wen, divSqrt_cp, wbInfo(0).cp) val wtypeTag = Mux(divSqrt_wen, divSqrt_typeTag, wbInfo(0).typeTag) val wdata = box(Mux(divSqrt_wen, divSqrt_wdata, (pipes.map(_.res.data): Seq[UInt])(wbInfo(0).pipeid)), wtypeTag) val wexc = (pipes.map(_.res.exc): Seq[UInt])(wbInfo(0).pipeid) when ((!wbInfo(0).cp && wen(0)) || divSqrt_wen) { assert(consistent(wdata)) regfile(waddr) := wdata if (enableCommitLog) { printf("f%d p%d 0x%x\n", waddr, waddr + 32.U, ieee(wdata)) } frfWriteBundle(1).wrdst := waddr frfWriteBundle(1).wrenf := true.B frfWriteBundle(1).wrdata := ieee(wdata) } if (useDebugROB) { DebugROB.pushWb(clock, reset, io.hartid, (!wbInfo(0).cp && wen(0)) || divSqrt_wen, waddr + 32.U, ieee(wdata)) } when (wb_cp && (wen(0) || divSqrt_wen)) { io.cp_resp.bits.data := wdata io.cp_resp.valid := true.B } assert(!io.cp_req.valid || pipes.forall(_.lat == pipes.head.lat).B, s"FPU only supports coprocessor if FMA pipes have uniform latency ${pipes.map(_.lat)}") // Avoid structural hazards and nacking of external requests // toint responds in the MEM stage, so an incoming toint can induce a structural hazard against inflight FMAs io.cp_req.ready := !ex_reg_valid && !(cp_ctrl.toint && wen =/= 0.U) && !divSqrt_inFlight val wb_toint_valid = wb_reg_valid && wb_ctrl.toint val wb_toint_exc = RegEnable(fpiu.io.out.bits.exc, mem_ctrl.toint) io.fcsr_flags.valid := wb_toint_valid || divSqrt_wen || wen(0) io.fcsr_flags.bits := Mux(wb_toint_valid, wb_toint_exc, 0.U) | Mux(divSqrt_wen, divSqrt_flags, 0.U) | Mux(wen(0), wexc, 0.U) val divSqrt_write_port_busy = (mem_ctrl.div || mem_ctrl.sqrt) && wen.orR io.fcsr_rdy := !(ex_reg_valid && ex_ctrl.wflags || mem_reg_valid && mem_ctrl.wflags || wb_reg_valid && wb_ctrl.toint || wen.orR || divSqrt_inFlight) io.nack_mem := (write_port_busy || divSqrt_write_port_busy || divSqrt_inFlight) && !mem_cp_valid io.dec <> id_ctrl def useScoreboard(f: ((Pipe, Int)) => Bool) = pipes.zipWithIndex.filter(_._1.lat > 3).map(x => f(x)).fold(false.B)(_||_) io.sboard_set := wb_reg_valid && !wb_cp_valid && RegNext(useScoreboard(_._1.cond(mem_ctrl)) || mem_ctrl.div || mem_ctrl.sqrt || mem_ctrl.vec) io.sboard_clr := !wb_cp_valid && (divSqrt_wen || (wen(0) && useScoreboard(x => wbInfo(0).pipeid === x._2.U))) io.sboard_clra := waddr ccover(io.sboard_clr && load_wb, "DUAL_WRITEBACK", "load and FMA writeback on same cycle") // we don't currently support round-max-magnitude (rm=4) io.illegal_rm := io.inst(14,12).isOneOf(5.U, 6.U) || io.inst(14,12) === 7.U && io.fcsr_rm >= 5.U if (cfg.divSqrt) { val divSqrt_inValid = mem_reg_valid && (mem_ctrl.div || mem_ctrl.sqrt) && !divSqrt_inFlight val divSqrt_killed = RegNext(divSqrt_inValid && killm, true.B) when (divSqrt_inValid) { divSqrt_waddr := mem_reg_inst(11,7) divSqrt_cp := mem_cp_valid } ccover(divSqrt_inFlight && divSqrt_killed, "DIV_KILLED", "divide killed after issued to divider") ccover(divSqrt_inFlight && mem_reg_valid && (mem_ctrl.div || mem_ctrl.sqrt), "DIV_BUSY", "divider structural hazard") ccover(mem_reg_valid && divSqrt_write_port_busy, "DIV_WB_STRUCTURAL", "structural hazard on division writeback") for (t <- floatTypes) { val tag = mem_ctrl.typeTagOut val divSqrt = withReset(divSqrt_killed) { Module(new hardfloat.DivSqrtRecFN_small(t.exp, t.sig, 0)) } divSqrt.io.inValid := divSqrt_inValid && tag === typeTag(t).U divSqrt.io.sqrtOp := mem_ctrl.sqrt divSqrt.io.a := maxType.unsafeConvert(fpiu.io.out.bits.in.in1, t) divSqrt.io.b := maxType.unsafeConvert(fpiu.io.out.bits.in.in2, t) divSqrt.io.roundingMode := fpiu.io.out.bits.in.rm divSqrt.io.detectTininess := hardfloat.consts.tininess_afterRounding when (!divSqrt.io.inReady) { divSqrt_inFlight := true.B } // only 1 in flight when (divSqrt.io.outValid_div || divSqrt.io.outValid_sqrt) { divSqrt_wen := !divSqrt_killed divSqrt_wdata := sanitizeNaN(divSqrt.io.out, t) divSqrt_flags := divSqrt.io.exceptionFlags divSqrt_typeTag := typeTag(t).U } } when (divSqrt_killed) { divSqrt_inFlight := false.B } } else { when (id_ctrl.div || id_ctrl.sqrt) { io.illegal_rm := true.B } } // gate the clock clock_en_reg := !useClockGating.B || io.keep_clock_enabled || // chicken bit io.valid || // ID stage req_valid || // EX stage mem_reg_valid || mem_cp_valid || // MEM stage wb_reg_valid || wb_cp_valid || // WB stage wen.orR || divSqrt_inFlight || // post-WB stage io.ll_resp_val // load writeback } // leaving gated-clock domain val fpuImpl = withClock (gated_clock) { new FPUImpl } def ccover(cond: Bool, label: String, desc: String)(implicit sourceInfo: SourceInfo) = property.cover(cond, s"FPU_$label", "Core;;" + desc) }

module FPUFMAPipe_l4_f64_2( // @[FPU.scala:697:7] input clock, // @[FPU.scala:697:7] input reset, // @[FPU.scala:697:7] input io_in_valid, // @[FPU.scala:702:14] input io_in_bits_ldst, // @[FPU.scala:702:14] input io_in_bits_wen, // @[FPU.scala:702:14] input io_in_bits_ren1, // @[FPU.scala:702:14] input io_in_bits_ren2, // @[FPU.scala:702:14] input io_in_bits_ren3, // @[FPU.scala:702:14] input io_in_bits_swap12, // @[FPU.scala:702:14] input io_in_bits_swap23, // @[FPU.scala:702:14] input [1:0] io_in_bits_typeTagIn, // @[FPU.scala:702:14] input [1:0] io_in_bits_typeTagOut, // @[FPU.scala:702:14] input io_in_bits_fromint, // @[FPU.scala:702:14] input io_in_bits_toint, // @[FPU.scala:702:14] input io_in_bits_fastpipe, // @[FPU.scala:702:14] input io_in_bits_fma, // @[FPU.scala:702:14] input io_in_bits_div, // @[FPU.scala:702:14] input io_in_bits_sqrt, // @[FPU.scala:702:14] input io_in_bits_wflags, // @[FPU.scala:702:14] input io_in_bits_vec, // @[FPU.scala:702:14] input [2:0] io_in_bits_rm, // @[FPU.scala:702:14] input [1:0] io_in_bits_fmaCmd, // @[FPU.scala:702:14] input [1:0] io_in_bits_typ, // @[FPU.scala:702:14] input [1:0] io_in_bits_fmt, // @[FPU.scala:702:14] input [64:0] io_in_bits_in1, // @[FPU.scala:702:14] input [64:0] io_in_bits_in2, // @[FPU.scala:702:14] input [64:0] io_in_bits_in3, // @[FPU.scala:702:14] output [64:0] io_out_bits_data, // @[FPU.scala:702:14] output [4:0] io_out_bits_exc // @[FPU.scala:702:14] ); wire [64:0] _fma_io_out; // @[FPU.scala:719:19] wire _fma_io_validout; // @[FPU.scala:719:19] wire io_in_valid_0 = io_in_valid; // @[FPU.scala:697:7] wire io_in_bits_ldst_0 = io_in_bits_ldst; // @[FPU.scala:697:7] wire io_in_bits_wen_0 = io_in_bits_wen; // @[FPU.scala:697:7] wire io_in_bits_ren1_0 = io_in_bits_ren1; // @[FPU.scala:697:7] wire io_in_bits_ren2_0 = io_in_bits_ren2; // @[FPU.scala:697:7] wire io_in_bits_ren3_0 = io_in_bits_ren3; // @[FPU.scala:697:7] wire io_in_bits_swap12_0 = io_in_bits_swap12; // @[FPU.scala:697:7] wire io_in_bits_swap23_0 = io_in_bits_swap23; // @[FPU.scala:697:7] wire [1:0] io_in_bits_typeTagIn_0 = io_in_bits_typeTagIn; // @[FPU.scala:697:7] wire [1:0] io_in_bits_typeTagOut_0 = io_in_bits_typeTagOut; // @[FPU.scala:697:7] wire io_in_bits_fromint_0 = io_in_bits_fromint; // @[FPU.scala:697:7] wire io_in_bits_toint_0 = io_in_bits_toint; // @[FPU.scala:697:7] wire io_in_bits_fastpipe_0 = io_in_bits_fastpipe; // @[FPU.scala:697:7] wire io_in_bits_fma_0 = io_in_bits_fma; // @[FPU.scala:697:7] wire io_in_bits_div_0 = io_in_bits_div; // @[FPU.scala:697:7] wire io_in_bits_sqrt_0 = io_in_bits_sqrt; // @[FPU.scala:697:7] wire io_in_bits_wflags_0 = io_in_bits_wflags; // @[FPU.scala:697:7] wire io_in_bits_vec_0 = io_in_bits_vec; // @[FPU.scala:697:7] wire [2:0] io_in_bits_rm_0 = io_in_bits_rm; // @[FPU.scala:697:7] wire [1:0] io_in_bits_fmaCmd_0 = io_in_bits_fmaCmd; // @[FPU.scala:697:7] wire [1:0] io_in_bits_typ_0 = io_in_bits_typ; // @[FPU.scala:697:7] wire [1:0] io_in_bits_fmt_0 = io_in_bits_fmt; // @[FPU.scala:697:7] wire [64:0] io_in_bits_in1_0 = io_in_bits_in1; // @[FPU.scala:697:7] wire [64:0] io_in_bits_in2_0 = io_in_bits_in2; // @[FPU.scala:697:7] wire [64:0] io_in_bits_in3_0 = io_in_bits_in3; // @[FPU.scala:697:7] wire [63:0] one = 64'h8000000000000000; // @[FPU.scala:710:19] wire [64:0] _zero_T_1 = 65'h10000000000000000; // @[FPU.scala:711:57] wire [64:0] _res_data_maskedNaN_T = 65'h1EFEFFFFFFFFFFFFF; // @[FPU.scala:413:27] wire io_out_pipe_out_valid; // @[Valid.scala:135:21] wire [64:0] io_out_pipe_out_bits_data; // @[Valid.scala:135:21] wire [4:0] io_out_pipe_out_bits_exc; // @[Valid.scala:135:21] wire [64:0] io_out_bits_data_0; // @[FPU.scala:697:7] wire [4:0] io_out_bits_exc_0; // @[FPU.scala:697:7] wire io_out_valid; // @[FPU.scala:697:7] reg valid; // @[FPU.scala:707:22] reg in_ldst; // @[FPU.scala:708:15] reg in_wen; // @[FPU.scala:708:15] reg in_ren1; // @[FPU.scala:708:15] reg in_ren2; // @[FPU.scala:708:15] reg in_ren3; // @[FPU.scala:708:15] reg in_swap12; // @[FPU.scala:708:15] reg in_swap23; // @[FPU.scala:708:15] reg [1:0] in_typeTagIn; // @[FPU.scala:708:15] reg [1:0] in_typeTagOut; // @[FPU.scala:708:15] reg in_fromint; // @[FPU.scala:708:15] reg in_toint; // @[FPU.scala:708:15] reg in_fastpipe; // @[FPU.scala:708:15] reg in_fma; // @[FPU.scala:708:15] reg in_div; // @[FPU.scala:708:15] reg in_sqrt; // @[FPU.scala:708:15] reg in_wflags; // @[FPU.scala:708:15] reg in_vec; // @[FPU.scala:708:15] reg [2:0] in_rm; // @[FPU.scala:708:15] reg [1:0] in_fmaCmd; // @[FPU.scala:708:15] reg [1:0] in_typ; // @[FPU.scala:708:15] reg [1:0] in_fmt; // @[FPU.scala:708:15] reg [64:0] in_in1; // @[FPU.scala:708:15] reg [64:0] in_in2; // @[FPU.scala:708:15] reg [64:0] in_in3; // @[FPU.scala:708:15] wire [64:0] _zero_T = io_in_bits_in1_0 ^ io_in_bits_in2_0; // @[FPU.scala:697:7, :711:32] wire [64:0] zero = _zero_T & 65'h10000000000000000; // @[FPU.scala:711:{32,50}] wire [64:0] _res_data_T_2; // @[FPU.scala:414:10] wire [64:0] res_data; // @[FPU.scala:728:17] wire [4:0] res_exc; // @[FPU.scala:728:17] wire [64:0] res_data_maskedNaN = _fma_io_out & 65'h1EFEFFFFFFFFFFFFF; // @[FPU.scala:413:25, :719:19] wire [2:0] _res_data_T = _fma_io_out[63:61]; // @[FPU.scala:249:25, :719:19] wire _res_data_T_1 = &_res_data_T; // @[FPU.scala:249:{25,56}] assign _res_data_T_2 = _res_data_T_1 ? res_data_maskedNaN : _fma_io_out; // @[FPU.scala:249:56, :413:25, :414:10, :719:19] assign res_data = _res_data_T_2; // @[FPU.scala:414:10, :728:17] reg io_out_pipe_v; // @[Valid.scala:141:24] assign io_out_pipe_out_valid = io_out_pipe_v; // @[Valid.scala:135:21, :141:24] reg [64:0] io_out_pipe_b_data; // @[Valid.scala:142:26] assign io_out_pipe_out_bits_data = io_out_pipe_b_data; // @[Valid.scala:135:21, :142:26] reg [4:0] io_out_pipe_b_exc; // @[Valid.scala:142:26] assign io_out_pipe_out_bits_exc = io_out_pipe_b_exc; // @[Valid.scala:135:21, :142:26] assign io_out_valid = io_out_pipe_out_valid; // @[Valid.scala:135:21] assign io_out_bits_data_0 = io_out_pipe_out_bits_data; // @[Valid.scala:135:21] assign io_out_bits_exc_0 = io_out_pipe_out_bits_exc; // @[Valid.scala:135:21] always @(posedge clock) begin // @[FPU.scala:697:7] valid <= io_in_valid_0; // @[FPU.scala:697:7, :707:22] if (io_in_valid_0) begin // @[FPU.scala:697:7] in_ldst <= io_in_bits_ldst_0; // @[FPU.scala:697:7, :708:15] in_wen <= io_in_bits_wen_0; // @[FPU.scala:697:7, :708:15] in_ren1 <= io_in_bits_ren1_0; // @[FPU.scala:697:7, :708:15] in_ren2 <= io_in_bits_ren2_0; // @[FPU.scala:697:7, :708:15] in_ren3 <= io_in_bits_ren3_0; // @[FPU.scala:697:7, :708:15] in_swap12 <= io_in_bits_swap12_0; // @[FPU.scala:697:7, :708:15] in_swap23 <= io_in_bits_swap23_0; // @[FPU.scala:697:7, :708:15] in_typeTagIn <= io_in_bits_typeTagIn_0; // @[FPU.scala:697:7, :708:15] in_typeTagOut <= io_in_bits_typeTagOut_0; // @[FPU.scala:697:7, :708:15] in_fromint <= io_in_bits_fromint_0; // @[FPU.scala:697:7, :708:15] in_toint <= io_in_bits_toint_0; // @[FPU.scala:697:7, :708:15] in_fastpipe <= io_in_bits_fastpipe_0; // @[FPU.scala:697:7, :708:15] in_fma <= io_in_bits_fma_0; // @[FPU.scala:697:7, :708:15] in_div <= io_in_bits_div_0; // @[FPU.scala:697:7, :708:15] in_sqrt <= io_in_bits_sqrt_0; // @[FPU.scala:697:7, :708:15] in_wflags <= io_in_bits_wflags_0; // @[FPU.scala:697:7, :708:15] in_vec <= io_in_bits_vec_0; // @[FPU.scala:697:7, :708:15] in_rm <= io_in_bits_rm_0; // @[FPU.scala:697:7, :708:15] in_fmaCmd <= io_in_bits_fmaCmd_0; // @[FPU.scala:697:7, :708:15] in_typ <= io_in_bits_typ_0; // @[FPU.scala:697:7, :708:15] in_fmt <= io_in_bits_fmt_0; // @[FPU.scala:697:7, :708:15] in_in1 <= io_in_bits_in1_0; // @[FPU.scala:697:7, :708:15] in_in2 <= io_in_bits_swap23_0 ? 65'h8000000000000000 : io_in_bits_in2_0; // @[FPU.scala:697:7, :708:15, :714:8, :715:{23,32}] in_in3 <= io_in_bits_ren3_0 | io_in_bits_swap23_0 ? io_in_bits_in3_0 : zero; // @[FPU.scala:697:7, :708:15, :711:50, :714:8, :716:{21,37,46}] end if (_fma_io_validout) begin // @[FPU.scala:719:19] io_out_pipe_b_data <= res_data; // @[Valid.scala:142:26] io_out_pipe_b_exc <= res_exc; // @[Valid.scala:142:26] end if (reset) // @[FPU.scala:697:7] io_out_pipe_v <= 1'h0; // @[Valid.scala:141:24] else // @[FPU.scala:697:7] io_out_pipe_v <= _fma_io_validout; // @[Valid.scala:141:24] always @(posedge) MulAddRecFNPipe_l2_e11_s53_2 fma ( // @[FPU.scala:719:19] .clock (clock), .reset (reset), .io_validin (valid), // @[FPU.scala:707:22] .io_op (in_fmaCmd), // @[FPU.scala:708:15] .io_a (in_in1), // @[FPU.scala:708:15] .io_b (in_in2), // @[FPU.scala:708:15] .io_c (in_in3), // @[FPU.scala:708:15] .io_roundingMode (in_rm), // @[FPU.scala:708:15] .io_out (_fma_io_out), .io_exceptionFlags (res_exc), .io_validout (_fma_io_validout) ); // @[FPU.scala:719:19] assign io_out_bits_data = io_out_bits_data_0; // @[FPU.scala:697:7] assign io_out_bits_exc = io_out_bits_exc_0; // @[FPU.scala:697:7] endmodule

Generate the Verilog code corresponding to the following Chisel files. File PE.scala: // See README.md for license details. package gemmini import chisel3._ import chisel3.util._ class PEControl[T <: Data : Arithmetic](accType: T) extends Bundle { val dataflow = UInt(1.W) // TODO make this an Enum val propagate = UInt(1.W) // Which register should be propagated (and which should be accumulated)? val shift = UInt(log2Up(accType.getWidth).W) // TODO this isn't correct for Floats } class MacUnit[T <: Data](inputType: T, cType: T, dType: T) (implicit ev: Arithmetic[T]) extends Module { import ev._ val io = IO(new Bundle { val in_a = Input(inputType) val in_b = Input(inputType) val in_c = Input(cType) val out_d = Output(dType) }) io.out_d := io.in_c.mac(io.in_a, io.in_b) } // TODO update documentation /** * A PE implementing a MAC operation. Configured as fully combinational when integrated into a Mesh. * @param width Data width of operands */ class PE[T <: Data](inputType: T, outputType: T, accType: T, df: Dataflow.Value, max_simultaneous_matmuls: Int) (implicit ev: Arithmetic[T]) extends Module { // Debugging variables import ev._ val io = IO(new Bundle { val in_a = Input(inputType) val in_b = Input(outputType) val in_d = Input(outputType) val out_a = Output(inputType) val out_b = Output(outputType) val out_c = Output(outputType) val in_control = Input(new PEControl(accType)) val out_control = Output(new PEControl(accType)) val in_id = Input(UInt(log2Up(max_simultaneous_matmuls).W)) val out_id = Output(UInt(log2Up(max_simultaneous_matmuls).W)) val in_last = Input(Bool()) val out_last = Output(Bool()) val in_valid = Input(Bool()) val out_valid = Output(Bool()) val bad_dataflow = Output(Bool()) }) val cType = if (df == Dataflow.WS) inputType else accType // When creating PEs that support multiple dataflows, the // elaboration/synthesis tools often fail to consolidate and de-duplicate // MAC units. To force mac circuitry to be re-used, we create a "mac_unit" // module here which just performs a single MAC operation val mac_unit = Module(new MacUnit(inputType, if (df == Dataflow.WS) outputType else accType, outputType)) val a = io.in_a val b = io.in_b val d = io.in_d val c1 = Reg(cType) val c2 = Reg(cType) val dataflow = io.in_control.dataflow val prop = io.in_control.propagate val shift = io.in_control.shift val id = io.in_id val last = io.in_last val valid = io.in_valid io.out_a := a io.out_control.dataflow := dataflow io.out_control.propagate := prop io.out_control.shift := shift io.out_id := id io.out_last := last io.out_valid := valid mac_unit.io.in_a := a val last_s = RegEnable(prop, valid) val flip = last_s =/= prop val shift_offset = Mux(flip, shift, 0.U) // Which dataflow are we using? val OUTPUT_STATIONARY = Dataflow.OS.id.U(1.W) val WEIGHT_STATIONARY = Dataflow.WS.id.U(1.W) // Is c1 being computed on, or propagated forward (in the output-stationary dataflow)? val COMPUTE = 0.U(1.W) val PROPAGATE = 1.U(1.W) io.bad_dataflow := false.B when ((df == Dataflow.OS).B || ((df == Dataflow.BOTH).B && dataflow === OUTPUT_STATIONARY)) { when(prop === PROPAGATE) { io.out_c := (c1 >> shift_offset).clippedToWidthOf(outputType) io.out_b := b mac_unit.io.in_b := b.asTypeOf(inputType) mac_unit.io.in_c := c2 c2 := mac_unit.io.out_d c1 := d.withWidthOf(cType) }.otherwise { io.out_c := (c2 >> shift_offset).clippedToWidthOf(outputType) io.out_b := b mac_unit.io.in_b := b.asTypeOf(inputType) mac_unit.io.in_c := c1 c1 := mac_unit.io.out_d c2 := d.withWidthOf(cType) } }.elsewhen ((df == Dataflow.WS).B || ((df == Dataflow.BOTH).B && dataflow === WEIGHT_STATIONARY)) { when(prop === PROPAGATE) { io.out_c := c1 mac_unit.io.in_b := c2.asTypeOf(inputType) mac_unit.io.in_c := b io.out_b := mac_unit.io.out_d c1 := d }.otherwise { io.out_c := c2 mac_unit.io.in_b := c1.asTypeOf(inputType) mac_unit.io.in_c := b io.out_b := mac_unit.io.out_d c2 := d } }.otherwise { io.bad_dataflow := true.B //assert(false.B, "unknown dataflow") io.out_c := DontCare io.out_b := DontCare mac_unit.io.in_b := b.asTypeOf(inputType) mac_unit.io.in_c := c2 } when (!valid) { c1 := c1 c2 := c2 mac_unit.io.in_b := DontCare mac_unit.io.in_c := DontCare } } File Arithmetic.scala: // A simple type class for Chisel datatypes that can add and multiply. To add your own type, simply create your own: // implicit MyTypeArithmetic extends Arithmetic[MyType] { ... } package gemmini import chisel3._ import chisel3.util._ import hardfloat._ // Bundles that represent the raw bits of custom datatypes case class Float(expWidth: Int, sigWidth: Int) extends Bundle { val bits = UInt((expWidth + sigWidth).W) val bias: Int = (1 << (expWidth-1)) - 1 } case class DummySInt(w: Int) extends Bundle { val bits = UInt(w.W) def dontCare: DummySInt = { val o = Wire(new DummySInt(w)) o.bits := 0.U o } } // The Arithmetic typeclass which implements various arithmetic operations on custom datatypes abstract class Arithmetic[T <: Data] { implicit def cast(t: T): ArithmeticOps[T] } abstract class ArithmeticOps[T <: Data](self: T) { def *(t: T): T def mac(m1: T, m2: T): T // Returns (m1 * m2 + self) def +(t: T): T def -(t: T): T def >>(u: UInt): T // This is a rounding shift! Rounds away from 0 def >(t: T): Bool def identity: T def withWidthOf(t: T): T def clippedToWidthOf(t: T): T // Like "withWidthOf", except that it saturates def relu: T def zero: T def minimum: T // Optional parameters, which only need to be defined if you want to enable various optimizations for transformers def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[T])] = None def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[T])] = None def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = None def mult_with_reciprocal[U <: Data](reciprocal: U) = self } object Arithmetic { implicit object UIntArithmetic extends Arithmetic[UInt] { override implicit def cast(self: UInt) = new ArithmeticOps(self) { override def *(t: UInt) = self * t override def mac(m1: UInt, m2: UInt) = m1 * m2 + self override def +(t: UInt) = self + t override def -(t: UInt) = self - t override def >>(u: UInt) = { // The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm // TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here? val point_five = Mux(u === 0.U, 0.U, self(u - 1.U)) val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U val ones_digit = self(u) val r = point_five & (zeros | ones_digit) (self >> u).asUInt + r } override def >(t: UInt): Bool = self > t override def withWidthOf(t: UInt) = self.asTypeOf(t) override def clippedToWidthOf(t: UInt) = { val sat = ((1 << (t.getWidth-1))-1).U Mux(self > sat, sat, self)(t.getWidth-1, 0) } override def relu: UInt = self override def zero: UInt = 0.U override def identity: UInt = 1.U override def minimum: UInt = 0.U } } implicit object SIntArithmetic extends Arithmetic[SInt] { override implicit def cast(self: SInt) = new ArithmeticOps(self) { override def *(t: SInt) = self * t override def mac(m1: SInt, m2: SInt) = m1 * m2 + self override def +(t: SInt) = self + t override def -(t: SInt) = self - t override def >>(u: UInt) = { // The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm // TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here? val point_five = Mux(u === 0.U, 0.U, self(u - 1.U)) val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U val ones_digit = self(u) val r = (point_five & (zeros | ones_digit)).asBool (self >> u).asSInt + Mux(r, 1.S, 0.S) } override def >(t: SInt): Bool = self > t override def withWidthOf(t: SInt) = { if (self.getWidth >= t.getWidth) self(t.getWidth-1, 0).asSInt else { val sign_bits = t.getWidth - self.getWidth val sign = self(self.getWidth-1) Cat(Cat(Seq.fill(sign_bits)(sign)), self).asTypeOf(t) } } override def clippedToWidthOf(t: SInt): SInt = { val maxsat = ((1 << (t.getWidth-1))-1).S val minsat = (-(1 << (t.getWidth-1))).S MuxCase(self, Seq((self > maxsat) -> maxsat, (self < minsat) -> minsat))(t.getWidth-1, 0).asSInt } override def relu: SInt = Mux(self >= 0.S, self, 0.S) override def zero: SInt = 0.S override def identity: SInt = 1.S override def minimum: SInt = (-(1 << (self.getWidth-1))).S override def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = { // TODO this uses a floating point divider, but we should use an integer divider instead val input = Wire(Decoupled(denom_t.cloneType)) val output = Wire(Decoupled(self.cloneType)) // We translate our integer to floating-point form so that we can use the hardfloat divider val expWidth = log2Up(self.getWidth) + 1 val sigWidth = self.getWidth def sin_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def uin_to_float(x: UInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := false.B in_to_rec_fn.io.in := x in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def float_to_in(x: UInt) = { val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth)) rec_fn_to_in.io.signedOut := true.B rec_fn_to_in.io.in := x rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag rec_fn_to_in.io.out.asSInt } val self_rec = sin_to_float(self) val denom_rec = uin_to_float(input.bits) // Instantiate the hardloat divider val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options)) input.ready := divider.io.inReady divider.io.inValid := input.valid divider.io.sqrtOp := false.B divider.io.a := self_rec divider.io.b := denom_rec divider.io.roundingMode := consts.round_minMag divider.io.detectTininess := consts.tininess_afterRounding output.valid := divider.io.outValid_div output.bits := float_to_in(divider.io.out) assert(!output.valid || output.ready) Some((input, output)) } override def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = { // TODO this uses a floating point divider, but we should use an integer divider instead val input = Wire(Decoupled(UInt(0.W))) val output = Wire(Decoupled(self.cloneType)) input.bits := DontCare // We translate our integer to floating-point form so that we can use the hardfloat divider val expWidth = log2Up(self.getWidth) + 1 val sigWidth = self.getWidth def in_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def float_to_in(x: UInt) = { val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth)) rec_fn_to_in.io.signedOut := true.B rec_fn_to_in.io.in := x rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag rec_fn_to_in.io.out.asSInt } val self_rec = in_to_float(self) // Instantiate the hardloat sqrt val sqrter = Module(new DivSqrtRecFN_small(expWidth, sigWidth, 0)) input.ready := sqrter.io.inReady sqrter.io.inValid := input.valid sqrter.io.sqrtOp := true.B sqrter.io.a := self_rec sqrter.io.b := DontCare sqrter.io.roundingMode := consts.round_minMag sqrter.io.detectTininess := consts.tininess_afterRounding output.valid := sqrter.io.outValid_sqrt output.bits := float_to_in(sqrter.io.out) assert(!output.valid || output.ready) Some((input, output)) } override def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = u match { case Float(expWidth, sigWidth) => val input = Wire(Decoupled(UInt(0.W))) val output = Wire(Decoupled(u.cloneType)) input.bits := DontCare // We translate our integer to floating-point form so that we can use the hardfloat divider def in_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } val self_rec = in_to_float(self) val one_rec = in_to_float(1.S) // Instantiate the hardloat divider val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options)) input.ready := divider.io.inReady divider.io.inValid := input.valid divider.io.sqrtOp := false.B divider.io.a := one_rec divider.io.b := self_rec divider.io.roundingMode := consts.round_near_even divider.io.detectTininess := consts.tininess_afterRounding output.valid := divider.io.outValid_div output.bits := fNFromRecFN(expWidth, sigWidth, divider.io.out).asTypeOf(u) assert(!output.valid || output.ready) Some((input, output)) case _ => None } override def mult_with_reciprocal[U <: Data](reciprocal: U): SInt = reciprocal match { case recip @ Float(expWidth, sigWidth) => def in_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def float_to_in(x: UInt) = { val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth)) rec_fn_to_in.io.signedOut := true.B rec_fn_to_in.io.in := x rec_fn_to_in.io.roundingMode := consts.round_minMag rec_fn_to_in.io.out.asSInt } val self_rec = in_to_float(self) val reciprocal_rec = recFNFromFN(expWidth, sigWidth, recip.bits) // Instantiate the hardloat divider val muladder = Module(new MulRecFN(expWidth, sigWidth)) muladder.io.roundingMode := consts.round_near_even muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := self_rec muladder.io.b := reciprocal_rec float_to_in(muladder.io.out) case _ => self } } } implicit object FloatArithmetic extends Arithmetic[Float] { // TODO Floating point arithmetic currently switches between recoded and standard formats for every operation. However, it should stay in the recoded format as it travels through the systolic array override implicit def cast(self: Float): ArithmeticOps[Float] = new ArithmeticOps(self) { override def *(t: Float): Float = { val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth)) t_resizer.io.in := t_rec t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag t_resizer.io.detectTininess := consts.tininess_afterRounding val t_rec_resized = t_resizer.io.out val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth)) muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := self_rec muladder.io.b := t_rec_resized val out = Wire(Float(self.expWidth, self.sigWidth)) out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) out } override def mac(m1: Float, m2: Float): Float = { // Recode all operands val m1_rec = recFNFromFN(m1.expWidth, m1.sigWidth, m1.bits) val m2_rec = recFNFromFN(m2.expWidth, m2.sigWidth, m2.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Resize m1 to self's width val m1_resizer = Module(new RecFNToRecFN(m1.expWidth, m1.sigWidth, self.expWidth, self.sigWidth)) m1_resizer.io.in := m1_rec m1_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag m1_resizer.io.detectTininess := consts.tininess_afterRounding val m1_rec_resized = m1_resizer.io.out // Resize m2 to self's width val m2_resizer = Module(new RecFNToRecFN(m2.expWidth, m2.sigWidth, self.expWidth, self.sigWidth)) m2_resizer.io.in := m2_rec m2_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag m2_resizer.io.detectTininess := consts.tininess_afterRounding val m2_rec_resized = m2_resizer.io.out // Perform multiply-add val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth)) muladder.io.op := 0.U muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := m1_rec_resized muladder.io.b := m2_rec_resized muladder.io.c := self_rec // Convert result to standard format // TODO remove these intermediate recodings val out = Wire(Float(self.expWidth, self.sigWidth)) out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) out } override def +(t: Float): Float = { require(self.getWidth >= t.getWidth) // This just makes it easier to write the resizing code // Recode all operands val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Generate 1 as a float val in_to_rec_fn = Module(new INToRecFN(1, self.expWidth, self.sigWidth)) in_to_rec_fn.io.signedIn := false.B in_to_rec_fn.io.in := 1.U in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding val one_rec = in_to_rec_fn.io.out // Resize t val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth)) t_resizer.io.in := t_rec t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag t_resizer.io.detectTininess := consts.tininess_afterRounding val t_rec_resized = t_resizer.io.out // Perform addition val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth)) muladder.io.op := 0.U muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := t_rec_resized muladder.io.b := one_rec muladder.io.c := self_rec val result = Wire(Float(self.expWidth, self.sigWidth)) result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) result } override def -(t: Float): Float = { val t_sgn = t.bits(t.getWidth-1) val neg_t = Cat(~t_sgn, t.bits(t.getWidth-2,0)).asTypeOf(t) self + neg_t } override def >>(u: UInt): Float = { // Recode self val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Get 2^(-u) as a recoded float val shift_exp = Wire(UInt(self.expWidth.W)) shift_exp := self.bias.U - u val shift_fn = Cat(0.U(1.W), shift_exp, 0.U((self.sigWidth-1).W)) val shift_rec = recFNFromFN(self.expWidth, self.sigWidth, shift_fn) assert(shift_exp =/= 0.U, "scaling by denormalized numbers is not currently supported") // Multiply self and 2^(-u) val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth)) muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := self_rec muladder.io.b := shift_rec val result = Wire(Float(self.expWidth, self.sigWidth)) result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) result } override def >(t: Float): Bool = { // Recode all operands val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Resize t to self's width val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth)) t_resizer.io.in := t_rec t_resizer.io.roundingMode := consts.round_near_even t_resizer.io.detectTininess := consts.tininess_afterRounding val t_rec_resized = t_resizer.io.out val comparator = Module(new CompareRecFN(self.expWidth, self.sigWidth)) comparator.io.a := self_rec comparator.io.b := t_rec_resized comparator.io.signaling := false.B comparator.io.gt } override def withWidthOf(t: Float): Float = { val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth)) resizer.io.in := self_rec resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag resizer.io.detectTininess := consts.tininess_afterRounding val result = Wire(Float(t.expWidth, t.sigWidth)) result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out) result } override def clippedToWidthOf(t: Float): Float = { // TODO check for overflow. Right now, we just assume that overflow doesn't happen val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth)) resizer.io.in := self_rec resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag resizer.io.detectTininess := consts.tininess_afterRounding val result = Wire(Float(t.expWidth, t.sigWidth)) result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out) result } override def relu: Float = { val raw = rawFloatFromFN(self.expWidth, self.sigWidth, self.bits) val result = Wire(Float(self.expWidth, self.sigWidth)) result.bits := Mux(!raw.isZero && raw.sign, 0.U, self.bits) result } override def zero: Float = 0.U.asTypeOf(self) override def identity: Float = Cat(0.U(2.W), ~(0.U((self.expWidth-1).W)), 0.U((self.sigWidth-1).W)).asTypeOf(self) override def minimum: Float = Cat(1.U, ~(0.U(self.expWidth.W)), 0.U((self.sigWidth-1).W)).asTypeOf(self) } } implicit object DummySIntArithmetic extends Arithmetic[DummySInt] { override implicit def cast(self: DummySInt) = new ArithmeticOps(self) { override def *(t: DummySInt) = self.dontCare override def mac(m1: DummySInt, m2: DummySInt) = self.dontCare override def +(t: DummySInt) = self.dontCare override def -(t: DummySInt) = self.dontCare override def >>(t: UInt) = self.dontCare override def >(t: DummySInt): Bool = false.B override def identity = self.dontCare override def withWidthOf(t: DummySInt) = self.dontCare override def clippedToWidthOf(t: DummySInt) = self.dontCare override def relu = self.dontCare override def zero = self.dontCare override def minimum: DummySInt = self.dontCare } } }

module PE_288( // @[PE.scala:31:7] input clock, // @[PE.scala:31:7] input reset, // @[PE.scala:31:7] input [7:0] io_in_a, // @[PE.scala:35:14] input [19:0] io_in_b, // @[PE.scala:35:14] input [19:0] io_in_d, // @[PE.scala:35:14] output [7:0] io_out_a, // @[PE.scala:35:14] output [19:0] io_out_b, // @[PE.scala:35:14] output [19:0] io_out_c, // @[PE.scala:35:14] input io_in_control_dataflow, // @[PE.scala:35:14] input io_in_control_propagate, // @[PE.scala:35:14] input [4:0] io_in_control_shift, // @[PE.scala:35:14] output io_out_control_dataflow, // @[PE.scala:35:14] output io_out_control_propagate, // @[PE.scala:35:14] output [4:0] io_out_control_shift, // @[PE.scala:35:14] input [2:0] io_in_id, // @[PE.scala:35:14] output [2:0] io_out_id, // @[PE.scala:35:14] input io_in_last, // @[PE.scala:35:14] output io_out_last, // @[PE.scala:35:14] input io_in_valid, // @[PE.scala:35:14] output io_out_valid // @[PE.scala:35:14] ); wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:31:7] wire [19:0] io_in_b_0 = io_in_b; // @[PE.scala:31:7] wire [19:0] io_in_d_0 = io_in_d; // @[PE.scala:31:7] wire io_in_control_dataflow_0 = io_in_control_dataflow; // @[PE.scala:31:7] wire io_in_control_propagate_0 = io_in_control_propagate; // @[PE.scala:31:7] wire [4:0] io_in_control_shift_0 = io_in_control_shift; // @[PE.scala:31:7] wire [2:0] io_in_id_0 = io_in_id; // @[PE.scala:31:7] wire io_in_last_0 = io_in_last; // @[PE.scala:31:7] wire io_in_valid_0 = io_in_valid; // @[PE.scala:31:7] wire io_bad_dataflow = 1'h0; // @[PE.scala:31:7] wire _io_out_c_T_5 = 1'h0; // @[Arithmetic.scala:125:33] wire _io_out_c_T_6 = 1'h0; // @[Arithmetic.scala:125:60] wire _io_out_c_T_16 = 1'h0; // @[Arithmetic.scala:125:33] wire _io_out_c_T_17 = 1'h0; // @[Arithmetic.scala:125:60] wire [7:0] io_out_a_0 = io_in_a_0; // @[PE.scala:31:7] wire [19:0] _mac_unit_io_in_b_T = io_in_b_0; // @[PE.scala:31:7, :106:37] wire [19:0] _mac_unit_io_in_b_T_2 = io_in_b_0; // @[PE.scala:31:7, :113:37] wire [19:0] _mac_unit_io_in_b_T_8 = io_in_b_0; // @[PE.scala:31:7, :137:35] wire io_out_control_dataflow_0 = io_in_control_dataflow_0; // @[PE.scala:31:7] wire io_out_control_propagate_0 = io_in_control_propagate_0; // @[PE.scala:31:7] wire [4:0] io_out_control_shift_0 = io_in_control_shift_0; // @[PE.scala:31:7] wire [2:0] io_out_id_0 = io_in_id_0; // @[PE.scala:31:7] wire io_out_last_0 = io_in_last_0; // @[PE.scala:31:7] wire io_out_valid_0 = io_in_valid_0; // @[PE.scala:31:7] wire [19:0] io_out_b_0; // @[PE.scala:31:7] wire [19:0] io_out_c_0; // @[PE.scala:31:7] reg [7:0] c1; // @[PE.scala:70:15] wire [7:0] _io_out_c_zeros_T_1 = c1; // @[PE.scala:70:15] wire [7:0] _mac_unit_io_in_b_T_6 = c1; // @[PE.scala:70:15, :127:38] reg [7:0] c2; // @[PE.scala:71:15] wire [7:0] _io_out_c_zeros_T_10 = c2; // @[PE.scala:71:15] wire [7:0] _mac_unit_io_in_b_T_4 = c2; // @[PE.scala:71:15, :121:38] reg last_s; // @[PE.scala:89:25] wire flip = last_s != io_in_control_propagate_0; // @[PE.scala:31:7, :89:25, :90:21] wire [4:0] shift_offset = flip ? io_in_control_shift_0 : 5'h0; // @[PE.scala:31:7, :90:21, :91:25] wire _GEN = shift_offset == 5'h0; // @[PE.scala:91:25] wire _io_out_c_point_five_T; // @[Arithmetic.scala:101:32] assign _io_out_c_point_five_T = _GEN; // @[Arithmetic.scala:101:32] wire _io_out_c_point_five_T_5; // @[Arithmetic.scala:101:32] assign _io_out_c_point_five_T_5 = _GEN; // @[Arithmetic.scala:101:32] wire [5:0] _GEN_0 = {1'h0, shift_offset} - 6'h1; // @[PE.scala:91:25] wire [5:0] _io_out_c_point_five_T_1; // @[Arithmetic.scala:101:53] assign _io_out_c_point_five_T_1 = _GEN_0; // @[Arithmetic.scala:101:53] wire [5:0] _io_out_c_zeros_T_2; // @[Arithmetic.scala:102:66] assign _io_out_c_zeros_T_2 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66] wire [5:0] _io_out_c_point_five_T_6; // @[Arithmetic.scala:101:53] assign _io_out_c_point_five_T_6 = _GEN_0; // @[Arithmetic.scala:101:53] wire [5:0] _io_out_c_zeros_T_11; // @[Arithmetic.scala:102:66] assign _io_out_c_zeros_T_11 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66] wire [4:0] _io_out_c_point_five_T_2 = _io_out_c_point_five_T_1[4:0]; // @[Arithmetic.scala:101:53] wire [7:0] _io_out_c_point_five_T_3 = $signed($signed(c1) >>> _io_out_c_point_five_T_2); // @[PE.scala:70:15] wire _io_out_c_point_five_T_4 = _io_out_c_point_five_T_3[0]; // @[Arithmetic.scala:101:50] wire io_out_c_point_five = ~_io_out_c_point_five_T & _io_out_c_point_five_T_4; // @[Arithmetic.scala:101:{29,32,50}] wire _GEN_1 = shift_offset < 5'h2; // @[PE.scala:91:25] wire _io_out_c_zeros_T; // @[Arithmetic.scala:102:27] assign _io_out_c_zeros_T = _GEN_1; // @[Arithmetic.scala:102:27] wire _io_out_c_zeros_T_9; // @[Arithmetic.scala:102:27] assign _io_out_c_zeros_T_9 = _GEN_1; // @[Arithmetic.scala:102:27] wire [4:0] _io_out_c_zeros_T_3 = _io_out_c_zeros_T_2[4:0]; // @[Arithmetic.scala:102:66] wire [31:0] _io_out_c_zeros_T_4 = 32'h1 << _io_out_c_zeros_T_3; // @[Arithmetic.scala:102:{60,66}] wire [32:0] _io_out_c_zeros_T_5 = {1'h0, _io_out_c_zeros_T_4} - 33'h1; // @[Arithmetic.scala:102:{60,81}] wire [31:0] _io_out_c_zeros_T_6 = _io_out_c_zeros_T_5[31:0]; // @[Arithmetic.scala:102:81] wire [31:0] _io_out_c_zeros_T_7 = {24'h0, _io_out_c_zeros_T_6[7:0] & _io_out_c_zeros_T_1}; // @[Arithmetic.scala:102:{45,52,81}] wire [31:0] _io_out_c_zeros_T_8 = _io_out_c_zeros_T ? 32'h0 : _io_out_c_zeros_T_7; // @[Arithmetic.scala:102:{24,27,52}] wire io_out_c_zeros = |_io_out_c_zeros_T_8; // @[Arithmetic.scala:102:{24,89}] wire [7:0] _GEN_2 = {3'h0, shift_offset}; // @[PE.scala:91:25] wire [7:0] _GEN_3 = $signed($signed(c1) >>> _GEN_2); // @[PE.scala:70:15] wire [7:0] _io_out_c_ones_digit_T; // @[Arithmetic.scala:103:30] assign _io_out_c_ones_digit_T = _GEN_3; // @[Arithmetic.scala:103:30] wire [7:0] _io_out_c_T; // @[Arithmetic.scala:107:15] assign _io_out_c_T = _GEN_3; // @[Arithmetic.scala:103:30, :107:15] wire io_out_c_ones_digit = _io_out_c_ones_digit_T[0]; // @[Arithmetic.scala:103:30] wire _io_out_c_r_T = io_out_c_zeros | io_out_c_ones_digit; // @[Arithmetic.scala:102:89, :103:30, :105:38] wire _io_out_c_r_T_1 = io_out_c_point_five & _io_out_c_r_T; // @[Arithmetic.scala:101:29, :105:{29,38}] wire io_out_c_r = _io_out_c_r_T_1; // @[Arithmetic.scala:105:{29,53}] wire [1:0] _io_out_c_T_1 = {1'h0, io_out_c_r}; // @[Arithmetic.scala:105:53, :107:33] wire [8:0] _io_out_c_T_2 = {_io_out_c_T[7], _io_out_c_T} + {{7{_io_out_c_T_1[1]}}, _io_out_c_T_1}; // @[Arithmetic.scala:107:{15,28,33}] wire [7:0] _io_out_c_T_3 = _io_out_c_T_2[7:0]; // @[Arithmetic.scala:107:28] wire [7:0] _io_out_c_T_4 = _io_out_c_T_3; // @[Arithmetic.scala:107:28] wire [19:0] _io_out_c_T_7 = {{12{_io_out_c_T_4[7]}}, _io_out_c_T_4}; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_8 = _io_out_c_T_7; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_9 = _io_out_c_T_8; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_10 = _io_out_c_T_9; // @[Arithmetic.scala:125:{81,99}] wire [19:0] _mac_unit_io_in_b_T_1 = _mac_unit_io_in_b_T; // @[PE.scala:106:37] wire [7:0] _mac_unit_io_in_b_WIRE = _mac_unit_io_in_b_T_1[7:0]; // @[PE.scala:106:37] wire [7:0] _c1_T = io_in_d_0[7:0]; // @[PE.scala:31:7] wire [7:0] _c2_T = io_in_d_0[7:0]; // @[PE.scala:31:7] wire [7:0] _c1_T_1 = _c1_T; // @[Arithmetic.scala:114:{15,33}] wire [4:0] _io_out_c_point_five_T_7 = _io_out_c_point_five_T_6[4:0]; // @[Arithmetic.scala:101:53] wire [7:0] _io_out_c_point_five_T_8 = $signed($signed(c2) >>> _io_out_c_point_five_T_7); // @[PE.scala:71:15] wire _io_out_c_point_five_T_9 = _io_out_c_point_five_T_8[0]; // @[Arithmetic.scala:101:50] wire io_out_c_point_five_1 = ~_io_out_c_point_five_T_5 & _io_out_c_point_five_T_9; // @[Arithmetic.scala:101:{29,32,50}] wire [4:0] _io_out_c_zeros_T_12 = _io_out_c_zeros_T_11[4:0]; // @[Arithmetic.scala:102:66] wire [31:0] _io_out_c_zeros_T_13 = 32'h1 << _io_out_c_zeros_T_12; // @[Arithmetic.scala:102:{60,66}] wire [32:0] _io_out_c_zeros_T_14 = {1'h0, _io_out_c_zeros_T_13} - 33'h1; // @[Arithmetic.scala:102:{60,81}] wire [31:0] _io_out_c_zeros_T_15 = _io_out_c_zeros_T_14[31:0]; // @[Arithmetic.scala:102:81] wire [31:0] _io_out_c_zeros_T_16 = {24'h0, _io_out_c_zeros_T_15[7:0] & _io_out_c_zeros_T_10}; // @[Arithmetic.scala:102:{45,52,81}] wire [31:0] _io_out_c_zeros_T_17 = _io_out_c_zeros_T_9 ? 32'h0 : _io_out_c_zeros_T_16; // @[Arithmetic.scala:102:{24,27,52}] wire io_out_c_zeros_1 = |_io_out_c_zeros_T_17; // @[Arithmetic.scala:102:{24,89}] wire [7:0] _GEN_4 = $signed($signed(c2) >>> _GEN_2); // @[PE.scala:71:15] wire [7:0] _io_out_c_ones_digit_T_1; // @[Arithmetic.scala:103:30] assign _io_out_c_ones_digit_T_1 = _GEN_4; // @[Arithmetic.scala:103:30] wire [7:0] _io_out_c_T_11; // @[Arithmetic.scala:107:15] assign _io_out_c_T_11 = _GEN_4; // @[Arithmetic.scala:103:30, :107:15] wire io_out_c_ones_digit_1 = _io_out_c_ones_digit_T_1[0]; // @[Arithmetic.scala:103:30] wire _io_out_c_r_T_2 = io_out_c_zeros_1 | io_out_c_ones_digit_1; // @[Arithmetic.scala:102:89, :103:30, :105:38] wire _io_out_c_r_T_3 = io_out_c_point_five_1 & _io_out_c_r_T_2; // @[Arithmetic.scala:101:29, :105:{29,38}] wire io_out_c_r_1 = _io_out_c_r_T_3; // @[Arithmetic.scala:105:{29,53}] wire [1:0] _io_out_c_T_12 = {1'h0, io_out_c_r_1}; // @[Arithmetic.scala:105:53, :107:33] wire [8:0] _io_out_c_T_13 = {_io_out_c_T_11[7], _io_out_c_T_11} + {{7{_io_out_c_T_12[1]}}, _io_out_c_T_12}; // @[Arithmetic.scala:107:{15,28,33}] wire [7:0] _io_out_c_T_14 = _io_out_c_T_13[7:0]; // @[Arithmetic.scala:107:28] wire [7:0] _io_out_c_T_15 = _io_out_c_T_14; // @[Arithmetic.scala:107:28] wire [19:0] _io_out_c_T_18 = {{12{_io_out_c_T_15[7]}}, _io_out_c_T_15}; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_19 = _io_out_c_T_18; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_20 = _io_out_c_T_19; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_21 = _io_out_c_T_20; // @[Arithmetic.scala:125:{81,99}] wire [19:0] _mac_unit_io_in_b_T_3 = _mac_unit_io_in_b_T_2; // @[PE.scala:113:37] wire [7:0] _mac_unit_io_in_b_WIRE_1 = _mac_unit_io_in_b_T_3[7:0]; // @[PE.scala:113:37] wire [7:0] _c2_T_1 = _c2_T; // @[Arithmetic.scala:114:{15,33}] wire [7:0] _mac_unit_io_in_b_T_5; // @[PE.scala:121:38] assign _mac_unit_io_in_b_T_5 = _mac_unit_io_in_b_T_4; // @[PE.scala:121:38] wire [7:0] _mac_unit_io_in_b_WIRE_2 = _mac_unit_io_in_b_T_5; // @[PE.scala:121:38] assign io_out_c_0 = io_in_control_propagate_0 ? {{12{c1[7]}}, c1} : {{12{c2[7]}}, c2}; // @[PE.scala:31:7, :70:15, :71:15, :119:30, :120:16, :126:16] wire [7:0] _mac_unit_io_in_b_T_7; // @[PE.scala:127:38] assign _mac_unit_io_in_b_T_7 = _mac_unit_io_in_b_T_6; // @[PE.scala:127:38] wire [7:0] _mac_unit_io_in_b_WIRE_3 = _mac_unit_io_in_b_T_7; // @[PE.scala:127:38] wire [19:0] _mac_unit_io_in_b_T_9 = _mac_unit_io_in_b_T_8; // @[PE.scala:137:35] wire [7:0] _mac_unit_io_in_b_WIRE_4 = _mac_unit_io_in_b_T_9[7:0]; // @[PE.scala:137:35] always @(posedge clock) begin // @[PE.scala:31:7] if (io_in_valid_0 & io_in_control_propagate_0) // @[PE.scala:31:7, :102:95, :141:17, :142:8] c1 <= io_in_d_0[7:0]; // @[PE.scala:31:7, :70:15] if (~(~io_in_valid_0 | io_in_control_propagate_0)) // @[PE.scala:31:7, :71:15, :102:95, :119:30, :130:10, :141:{9,17}, :143:8] c2 <= io_in_d_0[7:0]; // @[PE.scala:31:7, :71:15] if (io_in_valid_0) // @[PE.scala:31:7] last_s <= io_in_control_propagate_0; // @[PE.scala:31:7, :89:25] always @(posedge) MacUnit_32 mac_unit ( // @[PE.scala:64:24] .clock (clock), .reset (reset), .io_in_a (io_in_a_0), // @[PE.scala:31:7] .io_in_b (io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE_2 : _mac_unit_io_in_b_WIRE_3), // @[PE.scala:31:7, :119:30, :121:{24,38}, :127:{24,38}] .io_in_c (io_in_b_0), // @[PE.scala:31:7] .io_out_d (io_out_b_0) ); // @[PE.scala:64:24] assign io_out_a = io_out_a_0; // @[PE.scala:31:7] assign io_out_b = io_out_b_0; // @[PE.scala:31:7] assign io_out_c = io_out_c_0; // @[PE.scala:31:7] assign io_out_control_dataflow = io_out_control_dataflow_0; // @[PE.scala:31:7] assign io_out_control_propagate = io_out_control_propagate_0; // @[PE.scala:31:7] assign io_out_control_shift = io_out_control_shift_0; // @[PE.scala:31:7] assign io_out_id = io_out_id_0; // @[PE.scala:31:7] assign io_out_last = io_out_last_0; // @[PE.scala:31:7] assign io_out_valid = io_out_valid_0; // @[PE.scala:31:7] endmodule

Generate the Verilog code corresponding to the following Chisel files. File util.scala: //****************************************************************************** // Copyright (c) 2015 - 2019, The Regents of the University of California (Regents). // All Rights Reserved. See LICENSE and LICENSE.SiFive for license details. //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ // Utility Functions //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ package boom.v3.util import chisel3._ import chisel3.util._ import freechips.rocketchip.rocket.Instructions._ import freechips.rocketchip.rocket._ import freechips.rocketchip.util.{Str} import org.chipsalliance.cde.config.{Parameters} import freechips.rocketchip.tile.{TileKey} import boom.v3.common.{MicroOp} import boom.v3.exu.{BrUpdateInfo} /** * Object to XOR fold a input register of fullLength into a compressedLength. */ object Fold { def apply(input: UInt, compressedLength: Int, fullLength: Int): UInt = { val clen = compressedLength val hlen = fullLength if (hlen <= clen) { input } else { var res = 0.U(clen.W) var remaining = input.asUInt for (i <- 0 to hlen-1 by clen) { val len = if (i + clen > hlen ) (hlen - i) else clen require(len > 0) res = res(clen-1,0) ^ remaining(len-1,0) remaining = remaining >> len.U } res } } } /** * Object to check if MicroOp was killed due to a branch mispredict. * Uses "Fast" branch masks */ object IsKilledByBranch { def apply(brupdate: BrUpdateInfo, uop: MicroOp): Bool = { return maskMatch(brupdate.b1.mispredict_mask, uop.br_mask) } def apply(brupdate: BrUpdateInfo, uop_mask: UInt): Bool = { return maskMatch(brupdate.b1.mispredict_mask, uop_mask) } } /** * Object to return new MicroOp with a new BR mask given a MicroOp mask * and old BR mask. */ object GetNewUopAndBrMask { def apply(uop: MicroOp, brupdate: BrUpdateInfo) (implicit p: Parameters): MicroOp = { val newuop = WireInit(uop) newuop.br_mask := uop.br_mask & ~brupdate.b1.resolve_mask newuop } } /** * Object to return a BR mask given a MicroOp mask and old BR mask. */ object GetNewBrMask { def apply(brupdate: BrUpdateInfo, uop: MicroOp): UInt = { return uop.br_mask & ~brupdate.b1.resolve_mask } def apply(brupdate: BrUpdateInfo, br_mask: UInt): UInt = { return br_mask & ~brupdate.b1.resolve_mask } } object UpdateBrMask { def apply(brupdate: BrUpdateInfo, uop: MicroOp): MicroOp = { val out = WireInit(uop) out.br_mask := GetNewBrMask(brupdate, uop) out } def apply[T <: boom.v3.common.HasBoomUOP](brupdate: BrUpdateInfo, bundle: T): T = { val out = WireInit(bundle) out.uop.br_mask := GetNewBrMask(brupdate, bundle.uop.br_mask) out } def apply[T <: boom.v3.common.HasBoomUOP](brupdate: BrUpdateInfo, bundle: Valid[T]): Valid[T] = { val out = WireInit(bundle) out.bits.uop.br_mask := GetNewBrMask(brupdate, bundle.bits.uop.br_mask) out.valid := bundle.valid && !IsKilledByBranch(brupdate, bundle.bits.uop.br_mask) out } } /** * Object to check if at least 1 bit matches in two masks */ object maskMatch { def apply(msk1: UInt, msk2: UInt): Bool = (msk1 & msk2) =/= 0.U } /** * Object to clear one bit in a mask given an index */ object clearMaskBit { def apply(msk: UInt, idx: UInt): UInt = (msk & ~(1.U << idx))(msk.getWidth-1, 0) } /** * Object to shift a register over by one bit and concat a new one */ object PerformShiftRegister { def apply(reg_val: UInt, new_bit: Bool): UInt = { reg_val := Cat(reg_val(reg_val.getWidth-1, 0).asUInt, new_bit.asUInt).asUInt reg_val } } /** * Object to shift a register over by one bit, wrapping the top bit around to the bottom * (XOR'ed with a new-bit), and evicting a bit at index HLEN. * This is used to simulate a longer HLEN-width shift register that is folded * down to a compressed CLEN. */ object PerformCircularShiftRegister { def apply(csr: UInt, new_bit: Bool, evict_bit: Bool, hlen: Int, clen: Int): UInt = { val carry = csr(clen-1) val newval = Cat(csr, new_bit ^ carry) ^ (evict_bit << (hlen % clen).U) newval } } /** * Object to increment an input value, wrapping it if * necessary. */ object WrapAdd { // "n" is the number of increments, so we wrap at n-1. def apply(value: UInt, amt: UInt, n: Int): UInt = { if (isPow2(n)) { (value + amt)(log2Ceil(n)-1,0) } else { val sum = Cat(0.U(1.W), value) + Cat(0.U(1.W), amt) Mux(sum >= n.U, sum - n.U, sum) } } } /** * Object to decrement an input value, wrapping it if * necessary. */ object WrapSub { // "n" is the number of increments, so we wrap to n-1. def apply(value: UInt, amt: Int, n: Int): UInt = { if (isPow2(n)) { (value - amt.U)(log2Ceil(n)-1,0) } else { val v = Cat(0.U(1.W), value) val b = Cat(0.U(1.W), amt.U) Mux(value >= amt.U, value - amt.U, n.U - amt.U + value) } } } /** * Object to increment an input value, wrapping it if * necessary. */ object WrapInc { // "n" is the number of increments, so we wrap at n-1. def apply(value: UInt, n: Int): UInt = { if (isPow2(n)) { (value + 1.U)(log2Ceil(n)-1,0) } else { val wrap = (value === (n-1).U) Mux(wrap, 0.U, value + 1.U) } } } /** * Object to decrement an input value, wrapping it if * necessary. */ object WrapDec { // "n" is the number of increments, so we wrap at n-1. def apply(value: UInt, n: Int): UInt = { if (isPow2(n)) { (value - 1.U)(log2Ceil(n)-1,0) } else { val wrap = (value === 0.U) Mux(wrap, (n-1).U, value - 1.U) } } } /** * Object to mask off lower bits of a PC to align to a "b" * Byte boundary. */ object AlignPCToBoundary { def apply(pc: UInt, b: Int): UInt = { // Invert for scenario where pc longer than b // (which would clear all bits above size(b)). ~(~pc | (b-1).U) } } /** * Object to rotate a signal left by one */ object RotateL1 { def apply(signal: UInt): UInt = { val w = signal.getWidth val out = Cat(signal(w-2,0), signal(w-1)) return out } } /** * Object to sext a value to a particular length. */ object Sext { def apply(x: UInt, length: Int): UInt = { if (x.getWidth == length) return x else return Cat(Fill(length-x.getWidth, x(x.getWidth-1)), x) } } /** * Object to translate from BOOM's special "packed immediate" to a 32b signed immediate * Asking for U-type gives it shifted up 12 bits. */ object ImmGen { import boom.v3.common.{LONGEST_IMM_SZ, IS_B, IS_I, IS_J, IS_S, IS_U} def apply(ip: UInt, isel: UInt): SInt = { val sign = ip(LONGEST_IMM_SZ-1).asSInt val i30_20 = Mux(isel === IS_U, ip(18,8).asSInt, sign) val i19_12 = Mux(isel === IS_U || isel === IS_J, ip(7,0).asSInt, sign) val i11 = Mux(isel === IS_U, 0.S, Mux(isel === IS_J || isel === IS_B, ip(8).asSInt, sign)) val i10_5 = Mux(isel === IS_U, 0.S, ip(18,14).asSInt) val i4_1 = Mux(isel === IS_U, 0.S, ip(13,9).asSInt) val i0 = Mux(isel === IS_S || isel === IS_I, ip(8).asSInt, 0.S) return Cat(sign, i30_20, i19_12, i11, i10_5, i4_1, i0).asSInt } } /** * Object to get the FP rounding mode out of a packed immediate. */ object ImmGenRm { def apply(ip: UInt): UInt = { return ip(2,0) } } /** * Object to get the FP function fype from a packed immediate. * Note: only works if !(IS_B or IS_S) */ object ImmGenTyp { def apply(ip: UInt): UInt = { return ip(9,8) } } /** * Object to see if an instruction is a JALR. */ object DebugIsJALR { def apply(inst: UInt): Bool = { // TODO Chisel not sure why this won't compile // val is_jalr = rocket.DecodeLogic(inst, List(Bool(false)), // Array( // JALR -> Bool(true))) inst(6,0) === "b1100111".U } } /** * Object to take an instruction and output its branch or jal target. Only used * for a debug assert (no where else would we jump straight from instruction * bits to a target). */ object DebugGetBJImm { def apply(inst: UInt): UInt = { // TODO Chisel not sure why this won't compile //val csignals = //rocket.DecodeLogic(inst, // List(Bool(false), Bool(false)), // Array( // BEQ -> List(Bool(true ), Bool(false)), // BNE -> List(Bool(true ), Bool(false)), // BGE -> List(Bool(true ), Bool(false)), // BGEU -> List(Bool(true ), Bool(false)), // BLT -> List(Bool(true ), Bool(false)), // BLTU -> List(Bool(true ), Bool(false)) // )) //val is_br :: nothing :: Nil = csignals val is_br = (inst(6,0) === "b1100011".U) val br_targ = Cat(Fill(12, inst(31)), Fill(8,inst(31)), inst(7), inst(30,25), inst(11,8), 0.U(1.W)) val jal_targ= Cat(Fill(12, inst(31)), inst(19,12), inst(20), inst(30,25), inst(24,21), 0.U(1.W)) Mux(is_br, br_targ, jal_targ) } } /** * Object to return the lowest bit position after the head. */ object AgePriorityEncoder { def apply(in: Seq[Bool], head: UInt): UInt = { val n = in.size val width = log2Ceil(in.size) val n_padded = 1 << width val temp_vec = (0 until n_padded).map(i => if (i < n) in(i) && i.U >= head else false.B) ++ in val idx = PriorityEncoder(temp_vec) idx(width-1, 0) //discard msb } } /** * Object to determine whether queue * index i0 is older than index i1. */ object IsOlder { def apply(i0: UInt, i1: UInt, head: UInt) = ((i0 < i1) ^ (i0 < head) ^ (i1 < head)) } /** * Set all bits at or below the highest order '1'. */ object MaskLower { def apply(in: UInt) = { val n = in.getWidth (0 until n).map(i => in >> i.U).reduce(_|_) } } /** * Set all bits at or above the lowest order '1'. */ object MaskUpper { def apply(in: UInt) = { val n = in.getWidth (0 until n).map(i => (in << i.U)(n-1,0)).reduce(_|_) } } /** * Transpose a matrix of Chisel Vecs. */ object Transpose { def apply[T <: chisel3.Data](in: Vec[Vec[T]]) = { val n = in(0).size VecInit((0 until n).map(i => VecInit(in.map(row => row(i))))) } } /** * N-wide one-hot priority encoder. */ object SelectFirstN { def apply(in: UInt, n: Int) = { val sels = Wire(Vec(n, UInt(in.getWidth.W))) var mask = in for (i <- 0 until n) { sels(i) := PriorityEncoderOH(mask) mask = mask & ~sels(i) } sels } } /** * Connect the first k of n valid input interfaces to k output interfaces. */ class Compactor[T <: chisel3.Data](n: Int, k: Int, gen: T) extends Module { require(n >= k) val io = IO(new Bundle { val in = Vec(n, Flipped(DecoupledIO(gen))) val out = Vec(k, DecoupledIO(gen)) }) if (n == k) { io.out <> io.in } else { val counts = io.in.map(_.valid).scanLeft(1.U(k.W)) ((c,e) => Mux(e, (c<<1)(k-1,0), c)) val sels = Transpose(VecInit(counts map (c => VecInit(c.asBools)))) map (col => (col zip io.in.map(_.valid)) map {case (c,v) => c && v}) val in_readys = counts map (row => (row.asBools zip io.out.map(_.ready)) map {case (c,r) => c && r} reduce (_||_)) val out_valids = sels map (col => col.reduce(_||_)) val out_data = sels map (s => Mux1H(s, io.in.map(_.bits))) in_readys zip io.in foreach {case (r,i) => i.ready := r} out_valids zip out_data zip io.out foreach {case ((v,d),o) => o.valid := v; o.bits := d} } } /** * Create a queue that can be killed with a branch kill signal. * Assumption: enq.valid only high if not killed by branch (so don't check IsKilled on io.enq). */ class BranchKillableQueue[T <: boom.v3.common.HasBoomUOP](gen: T, entries: Int, flush_fn: boom.v3.common.MicroOp => Bool = u => true.B, flow: Boolean = true) (implicit p: org.chipsalliance.cde.config.Parameters) extends boom.v3.common.BoomModule()(p) with boom.v3.common.HasBoomCoreParameters { val io = IO(new Bundle { val enq = Flipped(Decoupled(gen)) val deq = Decoupled(gen) val brupdate = Input(new BrUpdateInfo()) val flush = Input(Bool()) val empty = Output(Bool()) val count = Output(UInt(log2Ceil(entries).W)) }) val ram = Mem(entries, gen) val valids = RegInit(VecInit(Seq.fill(entries) {false.B})) val uops = Reg(Vec(entries, new MicroOp)) val enq_ptr = Counter(entries) val deq_ptr = Counter(entries) val maybe_full = RegInit(false.B) val ptr_match = enq_ptr.value === deq_ptr.value io.empty := ptr_match && !maybe_full val full = ptr_match && maybe_full val do_enq = WireInit(io.enq.fire) val do_deq = WireInit((io.deq.ready || !valids(deq_ptr.value)) && !io.empty) for (i <- 0 until entries) { val mask = uops(i).br_mask val uop = uops(i) valids(i) := valids(i) && !IsKilledByBranch(io.brupdate, mask) && !(io.flush && flush_fn(uop)) when (valids(i)) { uops(i).br_mask := GetNewBrMask(io.brupdate, mask) } } when (do_enq) { ram(enq_ptr.value) := io.enq.bits valids(enq_ptr.value) := true.B //!IsKilledByBranch(io.brupdate, io.enq.bits.uop) uops(enq_ptr.value) := io.enq.bits.uop uops(enq_ptr.value).br_mask := GetNewBrMask(io.brupdate, io.enq.bits.uop) enq_ptr.inc() } when (do_deq) { valids(deq_ptr.value) := false.B deq_ptr.inc() } when (do_enq =/= do_deq) { maybe_full := do_enq } io.enq.ready := !full val out = Wire(gen) out := ram(deq_ptr.value) out.uop := uops(deq_ptr.value) io.deq.valid := !io.empty && valids(deq_ptr.value) && !IsKilledByBranch(io.brupdate, out.uop) && !(io.flush && flush_fn(out.uop)) io.deq.bits := out io.deq.bits.uop.br_mask := GetNewBrMask(io.brupdate, out.uop) // For flow queue behavior. if (flow) { when (io.empty) { io.deq.valid := io.enq.valid //&& !IsKilledByBranch(io.brupdate, io.enq.bits.uop) io.deq.bits := io.enq.bits io.deq.bits.uop.br_mask := GetNewBrMask(io.brupdate, io.enq.bits.uop) do_deq := false.B when (io.deq.ready) { do_enq := false.B } } } private val ptr_diff = enq_ptr.value - deq_ptr.value if (isPow2(entries)) { io.count := Cat(maybe_full && ptr_match, ptr_diff) } else { io.count := Mux(ptr_match, Mux(maybe_full, entries.asUInt, 0.U), Mux(deq_ptr.value > enq_ptr.value, entries.asUInt + ptr_diff, ptr_diff)) } } // ------------------------------------------ // Printf helper functions // ------------------------------------------ object BoolToChar { /** * Take in a Chisel Bool and convert it into a Str * based on the Chars given * * @param c_bool Chisel Bool * @param trueChar Scala Char if bool is true * @param falseChar Scala Char if bool is false * @return UInt ASCII Char for "trueChar" or "falseChar" */ def apply(c_bool: Bool, trueChar: Char, falseChar: Char = '-'): UInt = { Mux(c_bool, Str(trueChar), Str(falseChar)) } } object CfiTypeToChars { /** * Get a Vec of Strs that can be used for printing * * @param cfi_type specific cfi type * @return Vec of Strs (must be indexed to get specific char) */ def apply(cfi_type: UInt) = { val strings = Seq("----", "BR ", "JAL ", "JALR") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(cfi_type) } } object BpdTypeToChars { /** * Get a Vec of Strs that can be used for printing * * @param bpd_type specific bpd type * @return Vec of Strs (must be indexed to get specific char) */ def apply(bpd_type: UInt) = { val strings = Seq("BR ", "JUMP", "----", "RET ", "----", "CALL", "----", "----") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(bpd_type) } } object RobTypeToChars { /** * Get a Vec of Strs that can be used for printing * * @param rob_type specific rob type * @return Vec of Strs (must be indexed to get specific char) */ def apply(rob_type: UInt) = { val strings = Seq("RST", "NML", "RBK", " WT") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(rob_type) } } object XRegToChars { /** * Get a Vec of Strs that can be used for printing * * @param xreg specific register number * @return Vec of Strs (must be indexed to get specific char) */ def apply(xreg: UInt) = { val strings = Seq(" x0", " ra", " sp", " gp", " tp", " t0", " t1", " t2", " s0", " s1", " a0", " a1", " a2", " a3", " a4", " a5", " a6", " a7", " s2", " s3", " s4", " s5", " s6", " s7", " s8", " s9", "s10", "s11", " t3", " t4", " t5", " t6") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(xreg) } } object FPRegToChars { /** * Get a Vec of Strs that can be used for printing * * @param fpreg specific register number * @return Vec of Strs (must be indexed to get specific char) */ def apply(fpreg: UInt) = { val strings = Seq(" ft0", " ft1", " ft2", " ft3", " ft4", " ft5", " ft6", " ft7", " fs0", " fs1", " fa0", " fa1", " fa2", " fa3", " fa4", " fa5", " fa6", " fa7", " fs2", " fs3", " fs4", " fs5", " fs6", " fs7", " fs8", " fs9", "fs10", "fs11", " ft8", " ft9", "ft10", "ft11") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(fpreg) } } object BoomCoreStringPrefix { /** * Add prefix to BOOM strings (currently only adds the hartId) * * @param strs list of strings * @return String combining the list with the prefix per line */ def apply(strs: String*)(implicit p: Parameters) = { val prefix = "[C" + s"${p(TileKey).tileId}" + "] " strs.map(str => prefix + str + "\n").mkString("") } } File consts.scala: //****************************************************************************** // Copyright (c) 2011 - 2018, The Regents of the University of California (Regents). // All Rights Reserved. See LICENSE and LICENSE.SiFive for license details. //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ // RISCV Processor Constants //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ package boom.v3.common.constants import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util.Str import freechips.rocketchip.rocket.RVCExpander /** * Mixin for issue queue types */ trait IQType { val IQT_SZ = 3 val IQT_INT = 1.U(IQT_SZ.W) val IQT_MEM = 2.U(IQT_SZ.W) val IQT_FP = 4.U(IQT_SZ.W) val IQT_MFP = 6.U(IQT_SZ.W) } /** * Mixin for scalar operation constants */ trait ScalarOpConstants { val X = BitPat("b?") val Y = BitPat("b1") val N = BitPat("b0") //************************************ // Extra Constants // Which branch predictor predicted us val BSRC_SZ = 2 val BSRC_1 = 0.U(BSRC_SZ.W) // 1-cycle branch pred val BSRC_2 = 1.U(BSRC_SZ.W) // 2-cycle branch pred val BSRC_3 = 2.U(BSRC_SZ.W) // 3-cycle branch pred val BSRC_C = 3.U(BSRC_SZ.W) // core branch resolution //************************************ // Control Signals // CFI types val CFI_SZ = 3 val CFI_X = 0.U(CFI_SZ.W) // Not a CFI instruction val CFI_BR = 1.U(CFI_SZ.W) // Branch val CFI_JAL = 2.U(CFI_SZ.W) // JAL val CFI_JALR = 3.U(CFI_SZ.W) // JALR // PC Select Signal val PC_PLUS4 = 0.U(2.W) // PC + 4 val PC_BRJMP = 1.U(2.W) // brjmp_target val PC_JALR = 2.U(2.W) // jump_reg_target // Branch Type val BR_N = 0.U(4.W) // Next val BR_NE = 1.U(4.W) // Branch on NotEqual val BR_EQ = 2.U(4.W) // Branch on Equal val BR_GE = 3.U(4.W) // Branch on Greater/Equal val BR_GEU = 4.U(4.W) // Branch on Greater/Equal Unsigned val BR_LT = 5.U(4.W) // Branch on Less Than val BR_LTU = 6.U(4.W) // Branch on Less Than Unsigned val BR_J = 7.U(4.W) // Jump val BR_JR = 8.U(4.W) // Jump Register // RS1 Operand Select Signal val OP1_RS1 = 0.U(2.W) // Register Source #1 val OP1_ZERO= 1.U(2.W) val OP1_PC = 2.U(2.W) val OP1_X = BitPat("b??") // RS2 Operand Select Signal val OP2_RS2 = 0.U(3.W) // Register Source #2 val OP2_IMM = 1.U(3.W) // immediate val OP2_ZERO= 2.U(3.W) // constant 0 val OP2_NEXT= 3.U(3.W) // constant 2/4 (for PC+2/4) val OP2_IMMC= 4.U(3.W) // for CSR imm found in RS1 val OP2_X = BitPat("b???") // Register File Write Enable Signal val REN_0 = false.B val REN_1 = true.B // Is 32b Word or 64b Doubldword? val SZ_DW = 1 val DW_X = true.B // Bool(xLen==64) val DW_32 = false.B val DW_64 = true.B val DW_XPR = true.B // Bool(xLen==64) // Memory Enable Signal val MEN_0 = false.B val MEN_1 = true.B val MEN_X = false.B // Immediate Extend Select val IS_I = 0.U(3.W) // I-Type (LD,ALU) val IS_S = 1.U(3.W) // S-Type (ST) val IS_B = 2.U(3.W) // SB-Type (BR) val IS_U = 3.U(3.W) // U-Type (LUI/AUIPC) val IS_J = 4.U(3.W) // UJ-Type (J/JAL) val IS_X = BitPat("b???") // Decode Stage Control Signals val RT_FIX = 0.U(2.W) val RT_FLT = 1.U(2.W) val RT_PAS = 3.U(2.W) // pass-through (prs1 := lrs1, etc) val RT_X = 2.U(2.W) // not-a-register (but shouldn't get a busy-bit, etc.) // TODO rename RT_NAR // Micro-op opcodes // TODO change micro-op opcodes into using enum val UOPC_SZ = 7 val uopX = BitPat.dontCare(UOPC_SZ) val uopNOP = 0.U(UOPC_SZ.W) val uopLD = 1.U(UOPC_SZ.W) val uopSTA = 2.U(UOPC_SZ.W) // store address generation val uopSTD = 3.U(UOPC_SZ.W) // store data generation val uopLUI = 4.U(UOPC_SZ.W) val uopADDI = 5.U(UOPC_SZ.W) val uopANDI = 6.U(UOPC_SZ.W) val uopORI = 7.U(UOPC_SZ.W) val uopXORI = 8.U(UOPC_SZ.W) val uopSLTI = 9.U(UOPC_SZ.W) val uopSLTIU= 10.U(UOPC_SZ.W) val uopSLLI = 11.U(UOPC_SZ.W) val uopSRAI = 12.U(UOPC_SZ.W) val uopSRLI = 13.U(UOPC_SZ.W) val uopSLL = 14.U(UOPC_SZ.W) val uopADD = 15.U(UOPC_SZ.W) val uopSUB = 16.U(UOPC_SZ.W) val uopSLT = 17.U(UOPC_SZ.W) val uopSLTU = 18.U(UOPC_SZ.W) val uopAND = 19.U(UOPC_SZ.W) val uopOR = 20.U(UOPC_SZ.W) val uopXOR = 21.U(UOPC_SZ.W) val uopSRA = 22.U(UOPC_SZ.W) val uopSRL = 23.U(UOPC_SZ.W) val uopBEQ = 24.U(UOPC_SZ.W) val uopBNE = 25.U(UOPC_SZ.W) val uopBGE = 26.U(UOPC_SZ.W) val uopBGEU = 27.U(UOPC_SZ.W) val uopBLT = 28.U(UOPC_SZ.W) val uopBLTU = 29.U(UOPC_SZ.W) val uopCSRRW= 30.U(UOPC_SZ.W) val uopCSRRS= 31.U(UOPC_SZ.W) val uopCSRRC= 32.U(UOPC_SZ.W) val uopCSRRWI=33.U(UOPC_SZ.W) val uopCSRRSI=34.U(UOPC_SZ.W) val uopCSRRCI=35.U(UOPC_SZ.W) val uopJ = 36.U(UOPC_SZ.W) val uopJAL = 37.U(UOPC_SZ.W) val uopJALR = 38.U(UOPC_SZ.W) val uopAUIPC= 39.U(UOPC_SZ.W) //val uopSRET = 40.U(UOPC_SZ.W) val uopCFLSH= 41.U(UOPC_SZ.W) val uopFENCE= 42.U(UOPC_SZ.W) val uopADDIW= 43.U(UOPC_SZ.W) val uopADDW = 44.U(UOPC_SZ.W) val uopSUBW = 45.U(UOPC_SZ.W) val uopSLLIW= 46.U(UOPC_SZ.W) val uopSLLW = 47.U(UOPC_SZ.W) val uopSRAIW= 48.U(UOPC_SZ.W) val uopSRAW = 49.U(UOPC_SZ.W) val uopSRLIW= 50.U(UOPC_SZ.W) val uopSRLW = 51.U(UOPC_SZ.W) val uopMUL = 52.U(UOPC_SZ.W) val uopMULH = 53.U(UOPC_SZ.W) val uopMULHU= 54.U(UOPC_SZ.W) val uopMULHSU=55.U(UOPC_SZ.W) val uopMULW = 56.U(UOPC_SZ.W) val uopDIV = 57.U(UOPC_SZ.W) val uopDIVU = 58.U(UOPC_SZ.W) val uopREM = 59.U(UOPC_SZ.W) val uopREMU = 60.U(UOPC_SZ.W) val uopDIVW = 61.U(UOPC_SZ.W) val uopDIVUW= 62.U(UOPC_SZ.W) val uopREMW = 63.U(UOPC_SZ.W) val uopREMUW= 64.U(UOPC_SZ.W) val uopFENCEI = 65.U(UOPC_SZ.W) // = 66.U(UOPC_SZ.W) val uopAMO_AG = 67.U(UOPC_SZ.W) // AMO-address gen (use normal STD for datagen) val uopFMV_W_X = 68.U(UOPC_SZ.W) val uopFMV_D_X = 69.U(UOPC_SZ.W) val uopFMV_X_W = 70.U(UOPC_SZ.W) val uopFMV_X_D = 71.U(UOPC_SZ.W) val uopFSGNJ_S = 72.U(UOPC_SZ.W) val uopFSGNJ_D = 73.U(UOPC_SZ.W) val uopFCVT_S_D = 74.U(UOPC_SZ.W) val uopFCVT_D_S = 75.U(UOPC_SZ.W) val uopFCVT_S_X = 76.U(UOPC_SZ.W) val uopFCVT_D_X = 77.U(UOPC_SZ.W) val uopFCVT_X_S = 78.U(UOPC_SZ.W) val uopFCVT_X_D = 79.U(UOPC_SZ.W) val uopCMPR_S = 80.U(UOPC_SZ.W) val uopCMPR_D = 81.U(UOPC_SZ.W) val uopFCLASS_S = 82.U(UOPC_SZ.W) val uopFCLASS_D = 83.U(UOPC_SZ.W) val uopFMINMAX_S = 84.U(UOPC_SZ.W) val uopFMINMAX_D = 85.U(UOPC_SZ.W) // = 86.U(UOPC_SZ.W) val uopFADD_S = 87.U(UOPC_SZ.W) val uopFSUB_S = 88.U(UOPC_SZ.W) val uopFMUL_S = 89.U(UOPC_SZ.W) val uopFADD_D = 90.U(UOPC_SZ.W) val uopFSUB_D = 91.U(UOPC_SZ.W) val uopFMUL_D = 92.U(UOPC_SZ.W) val uopFMADD_S = 93.U(UOPC_SZ.W) val uopFMSUB_S = 94.U(UOPC_SZ.W) val uopFNMADD_S = 95.U(UOPC_SZ.W) val uopFNMSUB_S = 96.U(UOPC_SZ.W) val uopFMADD_D = 97.U(UOPC_SZ.W) val uopFMSUB_D = 98.U(UOPC_SZ.W) val uopFNMADD_D = 99.U(UOPC_SZ.W) val uopFNMSUB_D = 100.U(UOPC_SZ.W) val uopFDIV_S = 101.U(UOPC_SZ.W) val uopFDIV_D = 102.U(UOPC_SZ.W) val uopFSQRT_S = 103.U(UOPC_SZ.W) val uopFSQRT_D = 104.U(UOPC_SZ.W) val uopWFI = 105.U(UOPC_SZ.W) // pass uop down the CSR pipeline val uopERET = 106.U(UOPC_SZ.W) // pass uop down the CSR pipeline, also is ERET val uopSFENCE = 107.U(UOPC_SZ.W) val uopROCC = 108.U(UOPC_SZ.W) val uopMOV = 109.U(UOPC_SZ.W) // conditional mov decoded from "add rd, x0, rs2" // The Bubble Instruction (Machine generated NOP) // Insert (XOR x0,x0,x0) which is different from software compiler // generated NOPs which are (ADDI x0, x0, 0). // Reasoning for this is to let visualizers and stat-trackers differentiate // between software NOPs and machine-generated Bubbles in the pipeline. val BUBBLE = (0x4033).U(32.W) def NullMicroOp()(implicit p: Parameters): boom.v3.common.MicroOp = { val uop = Wire(new boom.v3.common.MicroOp) uop := DontCare // Overridden in the following lines uop.uopc := uopNOP // maybe not required, but helps on asserts that try to catch spurious behavior uop.bypassable := false.B uop.fp_val := false.B uop.uses_stq := false.B uop.uses_ldq := false.B uop.pdst := 0.U uop.dst_rtype := RT_X val cs = Wire(new boom.v3.common.CtrlSignals()) cs := DontCare // Overridden in the following lines cs.br_type := BR_N cs.csr_cmd := freechips.rocketchip.rocket.CSR.N cs.is_load := false.B cs.is_sta := false.B cs.is_std := false.B uop.ctrl := cs uop } } /** * Mixin for RISCV constants */ trait RISCVConstants { // abstract out instruction decode magic numbers val RD_MSB = 11 val RD_LSB = 7 val RS1_MSB = 19 val RS1_LSB = 15 val RS2_MSB = 24 val RS2_LSB = 20 val RS3_MSB = 31 val RS3_LSB = 27 val CSR_ADDR_MSB = 31 val CSR_ADDR_LSB = 20 val CSR_ADDR_SZ = 12 // location of the fifth bit in the shamt (for checking for illegal ops for SRAIW,etc.) val SHAMT_5_BIT = 25 val LONGEST_IMM_SZ = 20 val X0 = 0.U val RA = 1.U // return address register // memory consistency model // The C/C++ atomics MCM requires that two loads to the same address maintain program order. // The Cortex A9 does NOT enforce load/load ordering (which leads to buggy behavior). val MCM_ORDER_DEPENDENT_LOADS = true val jal_opc = (0x6f).U val jalr_opc = (0x67).U def GetUop(inst: UInt): UInt = inst(6,0) def GetRd (inst: UInt): UInt = inst(RD_MSB,RD_LSB) def GetRs1(inst: UInt): UInt = inst(RS1_MSB,RS1_LSB) def ExpandRVC(inst: UInt)(implicit p: Parameters): UInt = { val rvc_exp = Module(new RVCExpander) rvc_exp.io.in := inst Mux(rvc_exp.io.rvc, rvc_exp.io.out.bits, inst) } // Note: Accepts only EXPANDED rvc instructions def ComputeBranchTarget(pc: UInt, inst: UInt, xlen: Int)(implicit p: Parameters): UInt = { val b_imm32 = Cat(Fill(20,inst(31)), inst(7), inst(30,25), inst(11,8), 0.U(1.W)) ((pc.asSInt + b_imm32.asSInt).asSInt & (-2).S).asUInt } // Note: Accepts only EXPANDED rvc instructions def ComputeJALTarget(pc: UInt, inst: UInt, xlen: Int)(implicit p: Parameters): UInt = { val j_imm32 = Cat(Fill(12,inst(31)), inst(19,12), inst(20), inst(30,25), inst(24,21), 0.U(1.W)) ((pc.asSInt + j_imm32.asSInt).asSInt & (-2).S).asUInt } // Note: Accepts only EXPANDED rvc instructions def GetCfiType(inst: UInt)(implicit p: Parameters): UInt = { val bdecode = Module(new boom.v3.exu.BranchDecode) bdecode.io.inst := inst bdecode.io.pc := 0.U bdecode.io.out.cfi_type } } /** * Mixin for exception cause constants */ trait ExcCauseConstants { // a memory disambigious misspeculation occurred val MINI_EXCEPTION_MEM_ORDERING = 16.U val MINI_EXCEPTION_CSR_REPLAY = 17.U require (!freechips.rocketchip.rocket.Causes.all.contains(16)) require (!freechips.rocketchip.rocket.Causes.all.contains(17)) } File issue-slot.scala: //****************************************************************************** // Copyright (c) 2015 - 2018, The Regents of the University of California (Regents). // All Rights Reserved. See LICENSE and LICENSE.SiFive for license details. //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ // RISCV Processor Issue Slot Logic //-------------------------------------------------------------------------- //------------------------------------------------------------------------------ // // Note: stores (and AMOs) are "broken down" into 2 uops, but stored within a single issue-slot. // TODO XXX make a separate issueSlot for MemoryIssueSlots, and only they break apart stores. // TODO Disable ldspec for FP queue. package boom.v3.exu import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.Parameters import boom.v3.common._ import boom.v3.util._ import FUConstants._ /** * IO bundle to interact with Issue slot * * @param numWakeupPorts number of wakeup ports for the slot */ class IssueSlotIO(val numWakeupPorts: Int)(implicit p: Parameters) extends BoomBundle { val valid = Output(Bool()) val will_be_valid = Output(Bool()) // TODO code review, do we need this signal so explicitely? val request = Output(Bool()) val request_hp = Output(Bool()) val grant = Input(Bool()) val brupdate = Input(new BrUpdateInfo()) val kill = Input(Bool()) // pipeline flush val clear = Input(Bool()) // entry being moved elsewhere (not mutually exclusive with grant) val ldspec_miss = Input(Bool()) // Previous cycle's speculative load wakeup was mispredicted. val wakeup_ports = Flipped(Vec(numWakeupPorts, Valid(new IqWakeup(maxPregSz)))) val pred_wakeup_port = Flipped(Valid(UInt(log2Ceil(ftqSz).W))) val spec_ld_wakeup = Flipped(Vec(memWidth, Valid(UInt(width=maxPregSz.W)))) val in_uop = Flipped(Valid(new MicroOp())) // if valid, this WILL overwrite an entry! val out_uop = Output(new MicroOp()) // the updated slot uop; will be shifted upwards in a collasping queue. val uop = Output(new MicroOp()) // the current Slot's uop. Sent down the pipeline when issued. val debug = { val result = new Bundle { val p1 = Bool() val p2 = Bool() val p3 = Bool() val ppred = Bool() val state = UInt(width=2.W) } Output(result) } } /** * Single issue slot. Holds a uop within the issue queue * * @param numWakeupPorts number of wakeup ports */ class IssueSlot(val numWakeupPorts: Int)(implicit p: Parameters) extends BoomModule with IssueUnitConstants { val io = IO(new IssueSlotIO(numWakeupPorts)) // slot invalid? // slot is valid, holding 1 uop // slot is valid, holds 2 uops (like a store) def is_invalid = state === s_invalid def is_valid = state =/= s_invalid val next_state = Wire(UInt()) // the next state of this slot (which might then get moved to a new slot) val next_uopc = Wire(UInt()) // the next uopc of this slot (which might then get moved to a new slot) val next_lrs1_rtype = Wire(UInt()) // the next reg type of this slot (which might then get moved to a new slot) val next_lrs2_rtype = Wire(UInt()) // the next reg type of this slot (which might then get moved to a new slot) val state = RegInit(s_invalid) val p1 = RegInit(false.B) val p2 = RegInit(false.B) val p3 = RegInit(false.B) val ppred = RegInit(false.B) // Poison if woken up by speculative load. // Poison lasts 1 cycle (as ldMiss will come on the next cycle). // SO if poisoned is true, set it to false! val p1_poisoned = RegInit(false.B) val p2_poisoned = RegInit(false.B) p1_poisoned := false.B p2_poisoned := false.B val next_p1_poisoned = Mux(io.in_uop.valid, io.in_uop.bits.iw_p1_poisoned, p1_poisoned) val next_p2_poisoned = Mux(io.in_uop.valid, io.in_uop.bits.iw_p2_poisoned, p2_poisoned) val slot_uop = RegInit(NullMicroOp) val next_uop = Mux(io.in_uop.valid, io.in_uop.bits, slot_uop) //----------------------------------------------------------------------------- // next slot state computation // compute the next state for THIS entry slot (in a collasping queue, the // current uop may get moved elsewhere, and a new uop can enter when (io.kill) { state := s_invalid } .elsewhen (io.in_uop.valid) { state := io.in_uop.bits.iw_state } .elsewhen (io.clear) { state := s_invalid } .otherwise { state := next_state } //----------------------------------------------------------------------------- // "update" state // compute the next state for the micro-op in this slot. This micro-op may // be moved elsewhere, so the "next_state" travels with it. // defaults next_state := state next_uopc := slot_uop.uopc next_lrs1_rtype := slot_uop.lrs1_rtype next_lrs2_rtype := slot_uop.lrs2_rtype when (io.kill) { next_state := s_invalid } .elsewhen ((io.grant && (state === s_valid_1)) || (io.grant && (state === s_valid_2) && p1 && p2 && ppred)) { // try to issue this uop. when (!(io.ldspec_miss && (p1_poisoned || p2_poisoned))) { next_state := s_invalid } } .elsewhen (io.grant && (state === s_valid_2)) { when (!(io.ldspec_miss && (p1_poisoned || p2_poisoned))) { next_state := s_valid_1 when (p1) { slot_uop.uopc := uopSTD next_uopc := uopSTD slot_uop.lrs1_rtype := RT_X next_lrs1_rtype := RT_X } .otherwise { slot_uop.lrs2_rtype := RT_X next_lrs2_rtype := RT_X } } } when (io.in_uop.valid) { slot_uop := io.in_uop.bits assert (is_invalid || io.clear || io.kill, "trying to overwrite a valid issue slot.") } // Wakeup Compare Logic // these signals are the "next_p*" for the current slot's micro-op. // they are important for shifting the current slot_uop up to an other entry. val next_p1 = WireInit(p1) val next_p2 = WireInit(p2) val next_p3 = WireInit(p3) val next_ppred = WireInit(ppred) when (io.in_uop.valid) { p1 := !(io.in_uop.bits.prs1_busy) p2 := !(io.in_uop.bits.prs2_busy) p3 := !(io.in_uop.bits.prs3_busy) ppred := !(io.in_uop.bits.ppred_busy) } when (io.ldspec_miss && next_p1_poisoned) { assert(next_uop.prs1 =/= 0.U, "Poison bit can't be set for prs1=x0!") p1 := false.B } when (io.ldspec_miss && next_p2_poisoned) { assert(next_uop.prs2 =/= 0.U, "Poison bit can't be set for prs2=x0!") p2 := false.B } for (i <- 0 until numWakeupPorts) { when (io.wakeup_ports(i).valid && (io.wakeup_ports(i).bits.pdst === next_uop.prs1)) { p1 := true.B } when (io.wakeup_ports(i).valid && (io.wakeup_ports(i).bits.pdst === next_uop.prs2)) { p2 := true.B } when (io.wakeup_ports(i).valid && (io.wakeup_ports(i).bits.pdst === next_uop.prs3)) { p3 := true.B } } when (io.pred_wakeup_port.valid && io.pred_wakeup_port.bits === next_uop.ppred) { ppred := true.B } for (w <- 0 until memWidth) { assert (!(io.spec_ld_wakeup(w).valid && io.spec_ld_wakeup(w).bits === 0.U), "Loads to x0 should never speculatively wakeup other instructions") } // TODO disable if FP IQ. for (w <- 0 until memWidth) { when (io.spec_ld_wakeup(w).valid && io.spec_ld_wakeup(w).bits === next_uop.prs1 && next_uop.lrs1_rtype === RT_FIX) { p1 := true.B p1_poisoned := true.B assert (!next_p1_poisoned) } when (io.spec_ld_wakeup(w).valid && io.spec_ld_wakeup(w).bits === next_uop.prs2 && next_uop.lrs2_rtype === RT_FIX) { p2 := true.B p2_poisoned := true.B assert (!next_p2_poisoned) } } // Handle branch misspeculations val next_br_mask = GetNewBrMask(io.brupdate, slot_uop) // was this micro-op killed by a branch? if yes, we can't let it be valid if // we compact it into an other entry when (IsKilledByBranch(io.brupdate, slot_uop)) { next_state := s_invalid } when (!io.in_uop.valid) { slot_uop.br_mask := next_br_mask } //------------------------------------------------------------- // Request Logic io.request := is_valid && p1 && p2 && p3 && ppred && !io.kill val high_priority = slot_uop.is_br || slot_uop.is_jal || slot_uop.is_jalr io.request_hp := io.request && high_priority when (state === s_valid_1) { io.request := p1 && p2 && p3 && ppred && !io.kill } .elsewhen (state === s_valid_2) { io.request := (p1 || p2) && ppred && !io.kill } .otherwise { io.request := false.B } //assign outputs io.valid := is_valid io.uop := slot_uop io.uop.iw_p1_poisoned := p1_poisoned io.uop.iw_p2_poisoned := p2_poisoned // micro-op will vacate due to grant. val may_vacate = io.grant && ((state === s_valid_1) || (state === s_valid_2) && p1 && p2 && ppred) val squash_grant = io.ldspec_miss && (p1_poisoned || p2_poisoned) io.will_be_valid := is_valid && !(may_vacate && !squash_grant) io.out_uop := slot_uop io.out_uop.iw_state := next_state io.out_uop.uopc := next_uopc io.out_uop.lrs1_rtype := next_lrs1_rtype io.out_uop.lrs2_rtype := next_lrs2_rtype io.out_uop.br_mask := next_br_mask io.out_uop.prs1_busy := !p1 io.out_uop.prs2_busy := !p2 io.out_uop.prs3_busy := !p3 io.out_uop.ppred_busy := !ppred io.out_uop.iw_p1_poisoned := p1_poisoned io.out_uop.iw_p2_poisoned := p2_poisoned when (state === s_valid_2) { when (p1 && p2 && ppred) { ; // send out the entire instruction as one uop } .elsewhen (p1 && ppred) { io.uop.uopc := slot_uop.uopc io.uop.lrs2_rtype := RT_X } .elsewhen (p2 && ppred) { io.uop.uopc := uopSTD io.uop.lrs1_rtype := RT_X } } // debug outputs io.debug.p1 := p1 io.debug.p2 := p2 io.debug.p3 := p3 io.debug.ppred := ppred io.debug.state := state }

module IssueSlot_7( // @[issue-slot.scala:69:7] input clock, // @[issue-slot.scala:69:7] input reset, // @[issue-slot.scala:69:7] output io_valid, // @[issue-slot.scala:73:14] output io_will_be_valid, // @[issue-slot.scala:73:14] output io_request, // @[issue-slot.scala:73:14] output io_request_hp, // @[issue-slot.scala:73:14] input io_grant, // @[issue-slot.scala:73:14] input [15:0] io_brupdate_b1_resolve_mask, // @[issue-slot.scala:73:14] input [15:0] io_brupdate_b1_mispredict_mask, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_uopc, // @[issue-slot.scala:73:14] input [31:0] io_brupdate_b2_uop_inst, // @[issue-slot.scala:73:14] input [31:0] io_brupdate_b2_uop_debug_inst, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_rvc, // @[issue-slot.scala:73:14] input [39:0] io_brupdate_b2_uop_debug_pc, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_uop_iq_type, // @[issue-slot.scala:73:14] input [9:0] io_brupdate_b2_uop_fu_code, // @[issue-slot.scala:73:14] input [3:0] io_brupdate_b2_uop_ctrl_br_type, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_ctrl_op1_sel, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_uop_ctrl_op2_sel, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_uop_ctrl_imm_sel, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_ctrl_op_fcn, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ctrl_fcn_dw, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_uop_ctrl_csr_cmd, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ctrl_is_load, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ctrl_is_sta, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ctrl_is_std, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_iw_state, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_iw_p1_poisoned, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_iw_p2_poisoned, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_br, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_jalr, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_jal, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_sfb, // @[issue-slot.scala:73:14] input [15:0] io_brupdate_b2_uop_br_mask, // @[issue-slot.scala:73:14] input [3:0] io_brupdate_b2_uop_br_tag, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_ftq_idx, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_edge_inst, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_pc_lob, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_taken, // @[issue-slot.scala:73:14] input [19:0] io_brupdate_b2_uop_imm_packed, // @[issue-slot.scala:73:14] input [11:0] io_brupdate_b2_uop_csr_addr, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_rob_idx, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_ldq_idx, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_stq_idx, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_rxq_idx, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_pdst, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_prs1, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_prs2, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_prs3, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_ppred, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_prs1_busy, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_prs2_busy, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_prs3_busy, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ppred_busy, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_stale_pdst, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_exception, // @[issue-slot.scala:73:14] input [63:0] io_brupdate_b2_uop_exc_cause, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_bypassable, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_mem_cmd, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_mem_size, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_mem_signed, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_fence, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_fencei, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_amo, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_uses_ldq, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_uses_stq, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_sys_pc2epc, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_unique, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_flush_on_commit, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ldst_is_rs1, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_ldst, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_lrs1, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_lrs2, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_lrs3, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ldst_val, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_dst_rtype, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_lrs1_rtype, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_lrs2_rtype, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_frs3_en, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_fp_val, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_fp_single, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_xcpt_pf_if, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_xcpt_ae_if, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_xcpt_ma_if, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_bp_debug_if, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_bp_xcpt_if, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_debug_fsrc, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_debug_tsrc, // @[issue-slot.scala:73:14] input io_brupdate_b2_valid, // @[issue-slot.scala:73:14] input io_brupdate_b2_mispredict, // @[issue-slot.scala:73:14] input io_brupdate_b2_taken, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_cfi_type, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_pc_sel, // @[issue-slot.scala:73:14] input [39:0] io_brupdate_b2_jalr_target, // @[issue-slot.scala:73:14] input [20:0] io_brupdate_b2_target_offset, // @[issue-slot.scala:73:14] input io_kill, // @[issue-slot.scala:73:14] input io_clear, // @[issue-slot.scala:73:14] input io_wakeup_ports_0_valid, // @[issue-slot.scala:73:14] input [6:0] io_wakeup_ports_0_bits_pdst, // @[issue-slot.scala:73:14] input io_wakeup_ports_1_valid, // @[issue-slot.scala:73:14] input [6:0] io_wakeup_ports_1_bits_pdst, // @[issue-slot.scala:73:14] input io_in_uop_valid, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_uopc, // @[issue-slot.scala:73:14] input [31:0] io_in_uop_bits_inst, // @[issue-slot.scala:73:14] input [31:0] io_in_uop_bits_debug_inst, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_rvc, // @[issue-slot.scala:73:14] input [39:0] io_in_uop_bits_debug_pc, // @[issue-slot.scala:73:14] input [2:0] io_in_uop_bits_iq_type, // @[issue-slot.scala:73:14] input [9:0] io_in_uop_bits_fu_code, // @[issue-slot.scala:73:14] input [3:0] io_in_uop_bits_ctrl_br_type, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_ctrl_op1_sel, // @[issue-slot.scala:73:14] input [2:0] io_in_uop_bits_ctrl_op2_sel, // @[issue-slot.scala:73:14] input [2:0] io_in_uop_bits_ctrl_imm_sel, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_ctrl_op_fcn, // @[issue-slot.scala:73:14] input io_in_uop_bits_ctrl_fcn_dw, // @[issue-slot.scala:73:14] input [2:0] io_in_uop_bits_ctrl_csr_cmd, // @[issue-slot.scala:73:14] input io_in_uop_bits_ctrl_is_load, // @[issue-slot.scala:73:14] input io_in_uop_bits_ctrl_is_sta, // @[issue-slot.scala:73:14] input io_in_uop_bits_ctrl_is_std, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_iw_state, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_br, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_jalr, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_jal, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_sfb, // @[issue-slot.scala:73:14] input [15:0] io_in_uop_bits_br_mask, // @[issue-slot.scala:73:14] input [3:0] io_in_uop_bits_br_tag, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_ftq_idx, // @[issue-slot.scala:73:14] input io_in_uop_bits_edge_inst, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_pc_lob, // @[issue-slot.scala:73:14] input io_in_uop_bits_taken, // @[issue-slot.scala:73:14] input [19:0] io_in_uop_bits_imm_packed, // @[issue-slot.scala:73:14] input [11:0] io_in_uop_bits_csr_addr, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_rob_idx, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_ldq_idx, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_stq_idx, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_rxq_idx, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_pdst, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_prs1, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_prs2, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_prs3, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_ppred, // @[issue-slot.scala:73:14] input io_in_uop_bits_prs1_busy, // @[issue-slot.scala:73:14] input io_in_uop_bits_prs2_busy, // @[issue-slot.scala:73:14] input io_in_uop_bits_prs3_busy, // @[issue-slot.scala:73:14] input io_in_uop_bits_ppred_busy, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_stale_pdst, // @[issue-slot.scala:73:14] input io_in_uop_bits_exception, // @[issue-slot.scala:73:14] input [63:0] io_in_uop_bits_exc_cause, // @[issue-slot.scala:73:14] input io_in_uop_bits_bypassable, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_mem_cmd, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_mem_size, // @[issue-slot.scala:73:14] input io_in_uop_bits_mem_signed, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_fence, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_fencei, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_amo, // @[issue-slot.scala:73:14] input io_in_uop_bits_uses_ldq, // @[issue-slot.scala:73:14] input io_in_uop_bits_uses_stq, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_sys_pc2epc, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_unique, // @[issue-slot.scala:73:14] input io_in_uop_bits_flush_on_commit, // @[issue-slot.scala:73:14] input io_in_uop_bits_ldst_is_rs1, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_ldst, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_lrs1, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_lrs2, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_lrs3, // @[issue-slot.scala:73:14] input io_in_uop_bits_ldst_val, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_dst_rtype, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_lrs1_rtype, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_lrs2_rtype, // @[issue-slot.scala:73:14] input io_in_uop_bits_frs3_en, // @[issue-slot.scala:73:14] input io_in_uop_bits_fp_val, // @[issue-slot.scala:73:14] input io_in_uop_bits_fp_single, // @[issue-slot.scala:73:14] input io_in_uop_bits_xcpt_pf_if, // @[issue-slot.scala:73:14] input io_in_uop_bits_xcpt_ae_if, // @[issue-slot.scala:73:14] input io_in_uop_bits_xcpt_ma_if, // @[issue-slot.scala:73:14] input io_in_uop_bits_bp_debug_if, // @[issue-slot.scala:73:14] input io_in_uop_bits_bp_xcpt_if, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_debug_fsrc, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_debug_tsrc, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_uopc, // @[issue-slot.scala:73:14] output [31:0] io_out_uop_inst, // @[issue-slot.scala:73:14] output [31:0] io_out_uop_debug_inst, // @[issue-slot.scala:73:14] output io_out_uop_is_rvc, // @[issue-slot.scala:73:14] output [39:0] io_out_uop_debug_pc, // @[issue-slot.scala:73:14] output [2:0] io_out_uop_iq_type, // @[issue-slot.scala:73:14] output [9:0] io_out_uop_fu_code, // @[issue-slot.scala:73:14] output [3:0] io_out_uop_ctrl_br_type, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_ctrl_op1_sel, // @[issue-slot.scala:73:14] output [2:0] io_out_uop_ctrl_op2_sel, // @[issue-slot.scala:73:14] output [2:0] io_out_uop_ctrl_imm_sel, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_ctrl_op_fcn, // @[issue-slot.scala:73:14] output io_out_uop_ctrl_fcn_dw, // @[issue-slot.scala:73:14] output [2:0] io_out_uop_ctrl_csr_cmd, // @[issue-slot.scala:73:14] output io_out_uop_ctrl_is_load, // @[issue-slot.scala:73:14] output io_out_uop_ctrl_is_sta, // @[issue-slot.scala:73:14] output io_out_uop_ctrl_is_std, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_iw_state, // @[issue-slot.scala:73:14] output io_out_uop_is_br, // @[issue-slot.scala:73:14] output io_out_uop_is_jalr, // @[issue-slot.scala:73:14] output io_out_uop_is_jal, // @[issue-slot.scala:73:14] output io_out_uop_is_sfb, // @[issue-slot.scala:73:14] output [15:0] io_out_uop_br_mask, // @[issue-slot.scala:73:14] output [3:0] io_out_uop_br_tag, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_ftq_idx, // @[issue-slot.scala:73:14] output io_out_uop_edge_inst, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_pc_lob, // @[issue-slot.scala:73:14] output io_out_uop_taken, // @[issue-slot.scala:73:14] output [19:0] io_out_uop_imm_packed, // @[issue-slot.scala:73:14] output [11:0] io_out_uop_csr_addr, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_rob_idx, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_ldq_idx, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_stq_idx, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_rxq_idx, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_pdst, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_prs1, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_prs2, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_prs3, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_ppred, // @[issue-slot.scala:73:14] output io_out_uop_prs1_busy, // @[issue-slot.scala:73:14] output io_out_uop_prs2_busy, // @[issue-slot.scala:73:14] output io_out_uop_prs3_busy, // @[issue-slot.scala:73:14] output io_out_uop_ppred_busy, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_stale_pdst, // @[issue-slot.scala:73:14] output io_out_uop_exception, // @[issue-slot.scala:73:14] output [63:0] io_out_uop_exc_cause, // @[issue-slot.scala:73:14] output io_out_uop_bypassable, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_mem_cmd, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_mem_size, // @[issue-slot.scala:73:14] output io_out_uop_mem_signed, // @[issue-slot.scala:73:14] output io_out_uop_is_fence, // @[issue-slot.scala:73:14] output io_out_uop_is_fencei, // @[issue-slot.scala:73:14] output io_out_uop_is_amo, // @[issue-slot.scala:73:14] output io_out_uop_uses_ldq, // @[issue-slot.scala:73:14] output io_out_uop_uses_stq, // @[issue-slot.scala:73:14] output io_out_uop_is_sys_pc2epc, // @[issue-slot.scala:73:14] output io_out_uop_is_unique, // @[issue-slot.scala:73:14] output io_out_uop_flush_on_commit, // @[issue-slot.scala:73:14] output io_out_uop_ldst_is_rs1, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_ldst, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_lrs1, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_lrs2, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_lrs3, // @[issue-slot.scala:73:14] output io_out_uop_ldst_val, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_dst_rtype, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_lrs1_rtype, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_lrs2_rtype, // @[issue-slot.scala:73:14] output io_out_uop_frs3_en, // @[issue-slot.scala:73:14] output io_out_uop_fp_val, // @[issue-slot.scala:73:14] output io_out_uop_fp_single, // @[issue-slot.scala:73:14] output io_out_uop_xcpt_pf_if, // @[issue-slot.scala:73:14] output io_out_uop_xcpt_ae_if, // @[issue-slot.scala:73:14] output io_out_uop_xcpt_ma_if, // @[issue-slot.scala:73:14] output io_out_uop_bp_debug_if, // @[issue-slot.scala:73:14] output io_out_uop_bp_xcpt_if, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_debug_fsrc, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_debug_tsrc, // @[issue-slot.scala:73:14] output [6:0] io_uop_uopc, // @[issue-slot.scala:73:14] output [31:0] io_uop_inst, // @[issue-slot.scala:73:14] output [31:0] io_uop_debug_inst, // @[issue-slot.scala:73:14] output io_uop_is_rvc, // @[issue-slot.scala:73:14] output [39:0] io_uop_debug_pc, // @[issue-slot.scala:73:14] output [2:0] io_uop_iq_type, // @[issue-slot.scala:73:14] output [9:0] io_uop_fu_code, // @[issue-slot.scala:73:14] output [3:0] io_uop_ctrl_br_type, // @[issue-slot.scala:73:14] output [1:0] io_uop_ctrl_op1_sel, // @[issue-slot.scala:73:14] output [2:0] io_uop_ctrl_op2_sel, // @[issue-slot.scala:73:14] output [2:0] io_uop_ctrl_imm_sel, // @[issue-slot.scala:73:14] output [4:0] io_uop_ctrl_op_fcn, // @[issue-slot.scala:73:14] output io_uop_ctrl_fcn_dw, // @[issue-slot.scala:73:14] output [2:0] io_uop_ctrl_csr_cmd, // @[issue-slot.scala:73:14] output io_uop_ctrl_is_load, // @[issue-slot.scala:73:14] output io_uop_ctrl_is_sta, // @[issue-slot.scala:73:14] output io_uop_ctrl_is_std, // @[issue-slot.scala:73:14] output [1:0] io_uop_iw_state, // @[issue-slot.scala:73:14] output io_uop_is_br, // @[issue-slot.scala:73:14] output io_uop_is_jalr, // @[issue-slot.scala:73:14] output io_uop_is_jal, // @[issue-slot.scala:73:14] output io_uop_is_sfb, // @[issue-slot.scala:73:14] output [15:0] io_uop_br_mask, // @[issue-slot.scala:73:14] output [3:0] io_uop_br_tag, // @[issue-slot.scala:73:14] output [4:0] io_uop_ftq_idx, // @[issue-slot.scala:73:14] output io_uop_edge_inst, // @[issue-slot.scala:73:14] output [5:0] io_uop_pc_lob, // @[issue-slot.scala:73:14] output io_uop_taken, // @[issue-slot.scala:73:14] output [19:0] io_uop_imm_packed, // @[issue-slot.scala:73:14] output [11:0] io_uop_csr_addr, // @[issue-slot.scala:73:14] output [6:0] io_uop_rob_idx, // @[issue-slot.scala:73:14] output [4:0] io_uop_ldq_idx, // @[issue-slot.scala:73:14] output [4:0] io_uop_stq_idx, // @[issue-slot.scala:73:14] output [1:0] io_uop_rxq_idx, // @[issue-slot.scala:73:14] output [6:0] io_uop_pdst, // @[issue-slot.scala:73:14] output [6:0] io_uop_prs1, // @[issue-slot.scala:73:14] output [6:0] io_uop_prs2, // @[issue-slot.scala:73:14] output [6:0] io_uop_prs3, // @[issue-slot.scala:73:14] output [4:0] io_uop_ppred, // @[issue-slot.scala:73:14] output io_uop_prs1_busy, // @[issue-slot.scala:73:14] output io_uop_prs2_busy, // @[issue-slot.scala:73:14] output io_uop_prs3_busy, // @[issue-slot.scala:73:14] output io_uop_ppred_busy, // @[issue-slot.scala:73:14] output [6:0] io_uop_stale_pdst, // @[issue-slot.scala:73:14] output io_uop_exception, // @[issue-slot.scala:73:14] output [63:0] io_uop_exc_cause, // @[issue-slot.scala:73:14] output io_uop_bypassable, // @[issue-slot.scala:73:14] output [4:0] io_uop_mem_cmd, // @[issue-slot.scala:73:14] output [1:0] io_uop_mem_size, // @[issue-slot.scala:73:14] output io_uop_mem_signed, // @[issue-slot.scala:73:14] output io_uop_is_fence, // @[issue-slot.scala:73:14] output io_uop_is_fencei, // @[issue-slot.scala:73:14] output io_uop_is_amo, // @[issue-slot.scala:73:14] output io_uop_uses_ldq, // @[issue-slot.scala:73:14] output io_uop_uses_stq, // @[issue-slot.scala:73:14] output io_uop_is_sys_pc2epc, // @[issue-slot.scala:73:14] output io_uop_is_unique, // @[issue-slot.scala:73:14] output io_uop_flush_on_commit, // @[issue-slot.scala:73:14] output io_uop_ldst_is_rs1, // @[issue-slot.scala:73:14] output [5:0] io_uop_ldst, // @[issue-slot.scala:73:14] output [5:0] io_uop_lrs1, // @[issue-slot.scala:73:14] output [5:0] io_uop_lrs2, // @[issue-slot.scala:73:14] output [5:0] io_uop_lrs3, // @[issue-slot.scala:73:14] output io_uop_ldst_val, // @[issue-slot.scala:73:14] output [1:0] io_uop_dst_rtype, // @[issue-slot.scala:73:14] output [1:0] io_uop_lrs1_rtype, // @[issue-slot.scala:73:14] output [1:0] io_uop_lrs2_rtype, // @[issue-slot.scala:73:14] output io_uop_frs3_en, // @[issue-slot.scala:73:14] output io_uop_fp_val, // @[issue-slot.scala:73:14] output io_uop_fp_single, // @[issue-slot.scala:73:14] output io_uop_xcpt_pf_if, // @[issue-slot.scala:73:14] output io_uop_xcpt_ae_if, // @[issue-slot.scala:73:14] output io_uop_xcpt_ma_if, // @[issue-slot.scala:73:14] output io_uop_bp_debug_if, // @[issue-slot.scala:73:14] output io_uop_bp_xcpt_if, // @[issue-slot.scala:73:14] output [1:0] io_uop_debug_fsrc, // @[issue-slot.scala:73:14] output [1:0] io_uop_debug_tsrc, // @[issue-slot.scala:73:14] output io_debug_p1, // @[issue-slot.scala:73:14] output io_debug_p2, // @[issue-slot.scala:73:14] output io_debug_p3, // @[issue-slot.scala:73:14] output io_debug_ppred, // @[issue-slot.scala:73:14] output [1:0] io_debug_state // @[issue-slot.scala:73:14] ); wire io_grant_0 = io_grant; // @[issue-slot.scala:69:7] wire [15:0] io_brupdate_b1_resolve_mask_0 = io_brupdate_b1_resolve_mask; // @[issue-slot.scala:69:7] wire [15:0] io_brupdate_b1_mispredict_mask_0 = io_brupdate_b1_mispredict_mask; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_uopc_0 = io_brupdate_b2_uop_uopc; // @[issue-slot.scala:69:7] wire [31:0] io_brupdate_b2_uop_inst_0 = io_brupdate_b2_uop_inst; // @[issue-slot.scala:69:7] wire [31:0] io_brupdate_b2_uop_debug_inst_0 = io_brupdate_b2_uop_debug_inst; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_rvc_0 = io_brupdate_b2_uop_is_rvc; // @[issue-slot.scala:69:7] wire [39:0] io_brupdate_b2_uop_debug_pc_0 = io_brupdate_b2_uop_debug_pc; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_uop_iq_type_0 = io_brupdate_b2_uop_iq_type; // @[issue-slot.scala:69:7] wire [9:0] io_brupdate_b2_uop_fu_code_0 = io_brupdate_b2_uop_fu_code; // @[issue-slot.scala:69:7] wire [3:0] io_brupdate_b2_uop_ctrl_br_type_0 = io_brupdate_b2_uop_ctrl_br_type; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_ctrl_op1_sel_0 = io_brupdate_b2_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_uop_ctrl_op2_sel_0 = io_brupdate_b2_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_uop_ctrl_imm_sel_0 = io_brupdate_b2_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_ctrl_op_fcn_0 = io_brupdate_b2_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ctrl_fcn_dw_0 = io_brupdate_b2_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_uop_ctrl_csr_cmd_0 = io_brupdate_b2_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ctrl_is_load_0 = io_brupdate_b2_uop_ctrl_is_load; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ctrl_is_sta_0 = io_brupdate_b2_uop_ctrl_is_sta; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ctrl_is_std_0 = io_brupdate_b2_uop_ctrl_is_std; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_iw_state_0 = io_brupdate_b2_uop_iw_state; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_iw_p1_poisoned_0 = io_brupdate_b2_uop_iw_p1_poisoned; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_iw_p2_poisoned_0 = io_brupdate_b2_uop_iw_p2_poisoned; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_br_0 = io_brupdate_b2_uop_is_br; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_jalr_0 = io_brupdate_b2_uop_is_jalr; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_jal_0 = io_brupdate_b2_uop_is_jal; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_sfb_0 = io_brupdate_b2_uop_is_sfb; // @[issue-slot.scala:69:7] wire [15:0] io_brupdate_b2_uop_br_mask_0 = io_brupdate_b2_uop_br_mask; // @[issue-slot.scala:69:7] wire [3:0] io_brupdate_b2_uop_br_tag_0 = io_brupdate_b2_uop_br_tag; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_ftq_idx_0 = io_brupdate_b2_uop_ftq_idx; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_edge_inst_0 = io_brupdate_b2_uop_edge_inst; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_pc_lob_0 = io_brupdate_b2_uop_pc_lob; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_taken_0 = io_brupdate_b2_uop_taken; // @[issue-slot.scala:69:7] wire [19:0] io_brupdate_b2_uop_imm_packed_0 = io_brupdate_b2_uop_imm_packed; // @[issue-slot.scala:69:7] wire [11:0] io_brupdate_b2_uop_csr_addr_0 = io_brupdate_b2_uop_csr_addr; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_rob_idx_0 = io_brupdate_b2_uop_rob_idx; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_ldq_idx_0 = io_brupdate_b2_uop_ldq_idx; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_stq_idx_0 = io_brupdate_b2_uop_stq_idx; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_rxq_idx_0 = io_brupdate_b2_uop_rxq_idx; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_pdst_0 = io_brupdate_b2_uop_pdst; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_prs1_0 = io_brupdate_b2_uop_prs1; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_prs2_0 = io_brupdate_b2_uop_prs2; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_prs3_0 = io_brupdate_b2_uop_prs3; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_ppred_0 = io_brupdate_b2_uop_ppred; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_prs1_busy_0 = io_brupdate_b2_uop_prs1_busy; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_prs2_busy_0 = io_brupdate_b2_uop_prs2_busy; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_prs3_busy_0 = io_brupdate_b2_uop_prs3_busy; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ppred_busy_0 = io_brupdate_b2_uop_ppred_busy; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_stale_pdst_0 = io_brupdate_b2_uop_stale_pdst; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_exception_0 = io_brupdate_b2_uop_exception; // @[issue-slot.scala:69:7] wire [63:0] io_brupdate_b2_uop_exc_cause_0 = io_brupdate_b2_uop_exc_cause; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_bypassable_0 = io_brupdate_b2_uop_bypassable; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_mem_cmd_0 = io_brupdate_b2_uop_mem_cmd; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_mem_size_0 = io_brupdate_b2_uop_mem_size; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_mem_signed_0 = io_brupdate_b2_uop_mem_signed; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_fence_0 = io_brupdate_b2_uop_is_fence; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_fencei_0 = io_brupdate_b2_uop_is_fencei; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_amo_0 = io_brupdate_b2_uop_is_amo; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_uses_ldq_0 = io_brupdate_b2_uop_uses_ldq; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_uses_stq_0 = io_brupdate_b2_uop_uses_stq; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_sys_pc2epc_0 = io_brupdate_b2_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_unique_0 = io_brupdate_b2_uop_is_unique; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_flush_on_commit_0 = io_brupdate_b2_uop_flush_on_commit; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ldst_is_rs1_0 = io_brupdate_b2_uop_ldst_is_rs1; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_ldst_0 = io_brupdate_b2_uop_ldst; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_lrs1_0 = io_brupdate_b2_uop_lrs1; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_lrs2_0 = io_brupdate_b2_uop_lrs2; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_lrs3_0 = io_brupdate_b2_uop_lrs3; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ldst_val_0 = io_brupdate_b2_uop_ldst_val; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_dst_rtype_0 = io_brupdate_b2_uop_dst_rtype; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_lrs1_rtype_0 = io_brupdate_b2_uop_lrs1_rtype; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_lrs2_rtype_0 = io_brupdate_b2_uop_lrs2_rtype; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_frs3_en_0 = io_brupdate_b2_uop_frs3_en; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_fp_val_0 = io_brupdate_b2_uop_fp_val; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_fp_single_0 = io_brupdate_b2_uop_fp_single; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_xcpt_pf_if_0 = io_brupdate_b2_uop_xcpt_pf_if; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_xcpt_ae_if_0 = io_brupdate_b2_uop_xcpt_ae_if; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_xcpt_ma_if_0 = io_brupdate_b2_uop_xcpt_ma_if; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_bp_debug_if_0 = io_brupdate_b2_uop_bp_debug_if; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_bp_xcpt_if_0 = io_brupdate_b2_uop_bp_xcpt_if; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_debug_fsrc_0 = io_brupdate_b2_uop_debug_fsrc; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_debug_tsrc_0 = io_brupdate_b2_uop_debug_tsrc; // @[issue-slot.scala:69:7] wire io_brupdate_b2_valid_0 = io_brupdate_b2_valid; // @[issue-slot.scala:69:7] wire io_brupdate_b2_mispredict_0 = io_brupdate_b2_mispredict; // @[issue-slot.scala:69:7] wire io_brupdate_b2_taken_0 = io_brupdate_b2_taken; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_cfi_type_0 = io_brupdate_b2_cfi_type; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_pc_sel_0 = io_brupdate_b2_pc_sel; // @[issue-slot.scala:69:7] wire [39:0] io_brupdate_b2_jalr_target_0 = io_brupdate_b2_jalr_target; // @[issue-slot.scala:69:7] wire [20:0] io_brupdate_b2_target_offset_0 = io_brupdate_b2_target_offset; // @[issue-slot.scala:69:7] wire io_kill_0 = io_kill; // @[issue-slot.scala:69:7] wire io_clear_0 = io_clear; // @[issue-slot.scala:69:7] wire io_wakeup_ports_0_valid_0 = io_wakeup_ports_0_valid; // @[issue-slot.scala:69:7] wire [6:0] io_wakeup_ports_0_bits_pdst_0 = io_wakeup_ports_0_bits_pdst; // @[issue-slot.scala:69:7] wire io_wakeup_ports_1_valid_0 = io_wakeup_ports_1_valid; // @[issue-slot.scala:69:7] wire [6:0] io_wakeup_ports_1_bits_pdst_0 = io_wakeup_ports_1_bits_pdst; // @[issue-slot.scala:69:7] wire io_in_uop_valid_0 = io_in_uop_valid; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_uopc_0 = io_in_uop_bits_uopc; // @[issue-slot.scala:69:7] wire [31:0] io_in_uop_bits_inst_0 = io_in_uop_bits_inst; // @[issue-slot.scala:69:7] wire [31:0] io_in_uop_bits_debug_inst_0 = io_in_uop_bits_debug_inst; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_rvc_0 = io_in_uop_bits_is_rvc; // @[issue-slot.scala:69:7] wire [39:0] io_in_uop_bits_debug_pc_0 = io_in_uop_bits_debug_pc; // @[issue-slot.scala:69:7] wire [2:0] io_in_uop_bits_iq_type_0 = io_in_uop_bits_iq_type; // @[issue-slot.scala:69:7] wire [9:0] io_in_uop_bits_fu_code_0 = io_in_uop_bits_fu_code; // @[issue-slot.scala:69:7] wire [3:0] io_in_uop_bits_ctrl_br_type_0 = io_in_uop_bits_ctrl_br_type; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_ctrl_op1_sel_0 = io_in_uop_bits_ctrl_op1_sel; // @[issue-slot.scala:69:7] wire [2:0] io_in_uop_bits_ctrl_op2_sel_0 = io_in_uop_bits_ctrl_op2_sel; // @[issue-slot.scala:69:7] wire [2:0] io_in_uop_bits_ctrl_imm_sel_0 = io_in_uop_bits_ctrl_imm_sel; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_ctrl_op_fcn_0 = io_in_uop_bits_ctrl_op_fcn; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ctrl_fcn_dw_0 = io_in_uop_bits_ctrl_fcn_dw; // @[issue-slot.scala:69:7] wire [2:0] io_in_uop_bits_ctrl_csr_cmd_0 = io_in_uop_bits_ctrl_csr_cmd; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ctrl_is_load_0 = io_in_uop_bits_ctrl_is_load; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ctrl_is_sta_0 = io_in_uop_bits_ctrl_is_sta; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ctrl_is_std_0 = io_in_uop_bits_ctrl_is_std; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_iw_state_0 = io_in_uop_bits_iw_state; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_br_0 = io_in_uop_bits_is_br; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_jalr_0 = io_in_uop_bits_is_jalr; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_jal_0 = io_in_uop_bits_is_jal; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_sfb_0 = io_in_uop_bits_is_sfb; // @[issue-slot.scala:69:7] wire [15:0] io_in_uop_bits_br_mask_0 = io_in_uop_bits_br_mask; // @[issue-slot.scala:69:7] wire [3:0] io_in_uop_bits_br_tag_0 = io_in_uop_bits_br_tag; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_ftq_idx_0 = io_in_uop_bits_ftq_idx; // @[issue-slot.scala:69:7] wire io_in_uop_bits_edge_inst_0 = io_in_uop_bits_edge_inst; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_pc_lob_0 = io_in_uop_bits_pc_lob; // @[issue-slot.scala:69:7] wire io_in_uop_bits_taken_0 = io_in_uop_bits_taken; // @[issue-slot.scala:69:7] wire [19:0] io_in_uop_bits_imm_packed_0 = io_in_uop_bits_imm_packed; // @[issue-slot.scala:69:7] wire [11:0] io_in_uop_bits_csr_addr_0 = io_in_uop_bits_csr_addr; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_rob_idx_0 = io_in_uop_bits_rob_idx; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_ldq_idx_0 = io_in_uop_bits_ldq_idx; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_stq_idx_0 = io_in_uop_bits_stq_idx; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_rxq_idx_0 = io_in_uop_bits_rxq_idx; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_pdst_0 = io_in_uop_bits_pdst; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_prs1_0 = io_in_uop_bits_prs1; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_prs2_0 = io_in_uop_bits_prs2; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_prs3_0 = io_in_uop_bits_prs3; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_ppred_0 = io_in_uop_bits_ppred; // @[issue-slot.scala:69:7] wire io_in_uop_bits_prs1_busy_0 = io_in_uop_bits_prs1_busy; // @[issue-slot.scala:69:7] wire io_in_uop_bits_prs2_busy_0 = io_in_uop_bits_prs2_busy; // @[issue-slot.scala:69:7] wire io_in_uop_bits_prs3_busy_0 = io_in_uop_bits_prs3_busy; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ppred_busy_0 = io_in_uop_bits_ppred_busy; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_stale_pdst_0 = io_in_uop_bits_stale_pdst; // @[issue-slot.scala:69:7] wire io_in_uop_bits_exception_0 = io_in_uop_bits_exception; // @[issue-slot.scala:69:7] wire [63:0] io_in_uop_bits_exc_cause_0 = io_in_uop_bits_exc_cause; // @[issue-slot.scala:69:7] wire io_in_uop_bits_bypassable_0 = io_in_uop_bits_bypassable; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_mem_cmd_0 = io_in_uop_bits_mem_cmd; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_mem_size_0 = io_in_uop_bits_mem_size; // @[issue-slot.scala:69:7] wire io_in_uop_bits_mem_signed_0 = io_in_uop_bits_mem_signed; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_fence_0 = io_in_uop_bits_is_fence; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_fencei_0 = io_in_uop_bits_is_fencei; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_amo_0 = io_in_uop_bits_is_amo; // @[issue-slot.scala:69:7] wire io_in_uop_bits_uses_ldq_0 = io_in_uop_bits_uses_ldq; // @[issue-slot.scala:69:7] wire io_in_uop_bits_uses_stq_0 = io_in_uop_bits_uses_stq; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_sys_pc2epc_0 = io_in_uop_bits_is_sys_pc2epc; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_unique_0 = io_in_uop_bits_is_unique; // @[issue-slot.scala:69:7] wire io_in_uop_bits_flush_on_commit_0 = io_in_uop_bits_flush_on_commit; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ldst_is_rs1_0 = io_in_uop_bits_ldst_is_rs1; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_ldst_0 = io_in_uop_bits_ldst; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_lrs1_0 = io_in_uop_bits_lrs1; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_lrs2_0 = io_in_uop_bits_lrs2; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_lrs3_0 = io_in_uop_bits_lrs3; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ldst_val_0 = io_in_uop_bits_ldst_val; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_dst_rtype_0 = io_in_uop_bits_dst_rtype; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_lrs1_rtype_0 = io_in_uop_bits_lrs1_rtype; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_lrs2_rtype_0 = io_in_uop_bits_lrs2_rtype; // @[issue-slot.scala:69:7] wire io_in_uop_bits_frs3_en_0 = io_in_uop_bits_frs3_en; // @[issue-slot.scala:69:7] wire io_in_uop_bits_fp_val_0 = io_in_uop_bits_fp_val; // @[issue-slot.scala:69:7] wire io_in_uop_bits_fp_single_0 = io_in_uop_bits_fp_single; // @[issue-slot.scala:69:7] wire io_in_uop_bits_xcpt_pf_if_0 = io_in_uop_bits_xcpt_pf_if; // @[issue-slot.scala:69:7] wire io_in_uop_bits_xcpt_ae_if_0 = io_in_uop_bits_xcpt_ae_if; // @[issue-slot.scala:69:7] wire io_in_uop_bits_xcpt_ma_if_0 = io_in_uop_bits_xcpt_ma_if; // @[issue-slot.scala:69:7] wire io_in_uop_bits_bp_debug_if_0 = io_in_uop_bits_bp_debug_if; // @[issue-slot.scala:69:7] wire io_in_uop_bits_bp_xcpt_if_0 = io_in_uop_bits_bp_xcpt_if; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_debug_fsrc_0 = io_in_uop_bits_debug_fsrc; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_debug_tsrc_0 = io_in_uop_bits_debug_tsrc; // @[issue-slot.scala:69:7] wire io_ldspec_miss = 1'h0; // @[issue-slot.scala:69:7] wire io_wakeup_ports_0_bits_poisoned = 1'h0; // @[issue-slot.scala:69:7] wire io_wakeup_ports_1_bits_poisoned = 1'h0; // @[issue-slot.scala:69:7] wire io_pred_wakeup_port_valid = 1'h0; // @[issue-slot.scala:69:7] wire io_spec_ld_wakeup_0_valid = 1'h0; // @[issue-slot.scala:69:7] wire io_in_uop_bits_iw_p1_poisoned = 1'h0; // @[issue-slot.scala:69:7] wire io_in_uop_bits_iw_p2_poisoned = 1'h0; // @[issue-slot.scala:69:7] wire io_out_uop_iw_p1_poisoned = 1'h0; // @[issue-slot.scala:69:7] wire io_out_uop_iw_p2_poisoned = 1'h0; // @[issue-slot.scala:69:7] wire io_uop_iw_p1_poisoned = 1'h0; // @[issue-slot.scala:69:7] wire io_uop_iw_p2_poisoned = 1'h0; // @[issue-slot.scala:69:7] wire next_p1_poisoned = 1'h0; // @[issue-slot.scala:99:29] wire next_p2_poisoned = 1'h0; // @[issue-slot.scala:100:29] wire slot_uop_uop_is_rvc = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ctrl_fcn_dw = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ctrl_is_load = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ctrl_is_sta = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ctrl_is_std = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_iw_p1_poisoned = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_iw_p2_poisoned = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_br = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_jalr = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_jal = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_sfb = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_edge_inst = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_taken = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_prs1_busy = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_prs2_busy = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_prs3_busy = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ppred_busy = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_exception = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_bypassable = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_mem_signed = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_fence = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_fencei = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_amo = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_uses_ldq = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_uses_stq = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_sys_pc2epc = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_unique = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_flush_on_commit = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ldst_is_rs1 = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ldst_val = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_frs3_en = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_fp_val = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_fp_single = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_xcpt_pf_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_xcpt_ae_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_xcpt_ma_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_bp_debug_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_bp_xcpt_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_cs_fcn_dw = 1'h0; // @[consts.scala:279:18] wire slot_uop_cs_is_load = 1'h0; // @[consts.scala:279:18] wire slot_uop_cs_is_sta = 1'h0; // @[consts.scala:279:18] wire slot_uop_cs_is_std = 1'h0; // @[consts.scala:279:18] wire _squash_grant_T = 1'h0; // @[issue-slot.scala:261:53] wire squash_grant = 1'h0; // @[issue-slot.scala:261:37] wire [4:0] io_pred_wakeup_port_bits = 5'h0; // @[issue-slot.scala:69:7] wire [4:0] slot_uop_uop_ctrl_op_fcn = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_uop_ftq_idx = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_uop_ldq_idx = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_uop_stq_idx = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_uop_ppred = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_uop_mem_cmd = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_cs_op_fcn = 5'h0; // @[consts.scala:279:18] wire [6:0] io_spec_ld_wakeup_0_bits = 7'h0; // @[issue-slot.scala:69:7] wire [6:0] slot_uop_uop_uopc = 7'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_rob_idx = 7'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_pdst = 7'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_prs1 = 7'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_prs2 = 7'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_prs3 = 7'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_stale_pdst = 7'h0; // @[consts.scala:269:19] wire _io_will_be_valid_T_1 = 1'h1; // @[issue-slot.scala:262:51] wire [1:0] slot_uop_uop_ctrl_op1_sel = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_iw_state = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_rxq_idx = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_mem_size = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_lrs1_rtype = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_lrs2_rtype = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_debug_fsrc = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_debug_tsrc = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_cs_op1_sel = 2'h0; // @[consts.scala:279:18] wire [2:0] slot_uop_uop_iq_type = 3'h0; // @[consts.scala:269:19] wire [2:0] slot_uop_uop_ctrl_op2_sel = 3'h0; // @[consts.scala:269:19] wire [2:0] slot_uop_uop_ctrl_imm_sel = 3'h0; // @[consts.scala:269:19] wire [2:0] slot_uop_uop_ctrl_csr_cmd = 3'h0; // @[consts.scala:269:19] wire [2:0] slot_uop_cs_op2_sel = 3'h0; // @[consts.scala:279:18] wire [2:0] slot_uop_cs_imm_sel = 3'h0; // @[consts.scala:279:18] wire [2:0] slot_uop_cs_csr_cmd = 3'h0; // @[consts.scala:279:18] wire [3:0] slot_uop_uop_ctrl_br_type = 4'h0; // @[consts.scala:269:19] wire [3:0] slot_uop_uop_br_tag = 4'h0; // @[consts.scala:269:19] wire [3:0] slot_uop_cs_br_type = 4'h0; // @[consts.scala:279:18] wire [1:0] slot_uop_uop_dst_rtype = 2'h2; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_pc_lob = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_ldst = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_lrs1 = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_lrs2 = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_lrs3 = 6'h0; // @[consts.scala:269:19] wire [63:0] slot_uop_uop_exc_cause = 64'h0; // @[consts.scala:269:19] wire [11:0] slot_uop_uop_csr_addr = 12'h0; // @[consts.scala:269:19] wire [19:0] slot_uop_uop_imm_packed = 20'h0; // @[consts.scala:269:19] wire [15:0] slot_uop_uop_br_mask = 16'h0; // @[consts.scala:269:19] wire [9:0] slot_uop_uop_fu_code = 10'h0; // @[consts.scala:269:19] wire [39:0] slot_uop_uop_debug_pc = 40'h0; // @[consts.scala:269:19] wire [31:0] slot_uop_uop_inst = 32'h0; // @[consts.scala:269:19] wire [31:0] slot_uop_uop_debug_inst = 32'h0; // @[consts.scala:269:19] wire _io_valid_T; // @[issue-slot.scala:79:24] wire _io_will_be_valid_T_4; // @[issue-slot.scala:262:32] wire _io_request_hp_T; // @[issue-slot.scala:243:31] wire [6:0] next_uopc; // @[issue-slot.scala:82:29] wire [1:0] next_state; // @[issue-slot.scala:81:29] wire [15:0] next_br_mask; // @[util.scala:85:25] wire _io_out_uop_prs1_busy_T; // @[issue-slot.scala:270:28] wire _io_out_uop_prs2_busy_T; // @[issue-slot.scala:271:28] wire _io_out_uop_prs3_busy_T; // @[issue-slot.scala:272:28] wire _io_out_uop_ppred_busy_T; // @[issue-slot.scala:273:28] wire [1:0] next_lrs1_rtype; // @[issue-slot.scala:83:29] wire [1:0] next_lrs2_rtype; // @[issue-slot.scala:84:29] wire [3:0] io_out_uop_ctrl_br_type_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_ctrl_op1_sel_0; // @[issue-slot.scala:69:7] wire [2:0] io_out_uop_ctrl_op2_sel_0; // @[issue-slot.scala:69:7] wire [2:0] io_out_uop_ctrl_imm_sel_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_ctrl_op_fcn_0; // @[issue-slot.scala:69:7] wire io_out_uop_ctrl_fcn_dw_0; // @[issue-slot.scala:69:7] wire [2:0] io_out_uop_ctrl_csr_cmd_0; // @[issue-slot.scala:69:7] wire io_out_uop_ctrl_is_load_0; // @[issue-slot.scala:69:7] wire io_out_uop_ctrl_is_sta_0; // @[issue-slot.scala:69:7] wire io_out_uop_ctrl_is_std_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_uopc_0; // @[issue-slot.scala:69:7] wire [31:0] io_out_uop_inst_0; // @[issue-slot.scala:69:7] wire [31:0] io_out_uop_debug_inst_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_rvc_0; // @[issue-slot.scala:69:7] wire [39:0] io_out_uop_debug_pc_0; // @[issue-slot.scala:69:7] wire [2:0] io_out_uop_iq_type_0; // @[issue-slot.scala:69:7] wire [9:0] io_out_uop_fu_code_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_iw_state_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_br_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_jalr_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_jal_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_sfb_0; // @[issue-slot.scala:69:7] wire [15:0] io_out_uop_br_mask_0; // @[issue-slot.scala:69:7] wire [3:0] io_out_uop_br_tag_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_ftq_idx_0; // @[issue-slot.scala:69:7] wire io_out_uop_edge_inst_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_pc_lob_0; // @[issue-slot.scala:69:7] wire io_out_uop_taken_0; // @[issue-slot.scala:69:7] wire [19:0] io_out_uop_imm_packed_0; // @[issue-slot.scala:69:7] wire [11:0] io_out_uop_csr_addr_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_rob_idx_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_ldq_idx_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_stq_idx_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_rxq_idx_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_pdst_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_prs1_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_prs2_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_prs3_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_ppred_0; // @[issue-slot.scala:69:7] wire io_out_uop_prs1_busy_0; // @[issue-slot.scala:69:7] wire io_out_uop_prs2_busy_0; // @[issue-slot.scala:69:7] wire io_out_uop_prs3_busy_0; // @[issue-slot.scala:69:7] wire io_out_uop_ppred_busy_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_stale_pdst_0; // @[issue-slot.scala:69:7] wire io_out_uop_exception_0; // @[issue-slot.scala:69:7] wire [63:0] io_out_uop_exc_cause_0; // @[issue-slot.scala:69:7] wire io_out_uop_bypassable_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_mem_cmd_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_mem_size_0; // @[issue-slot.scala:69:7] wire io_out_uop_mem_signed_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_fence_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_fencei_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_amo_0; // @[issue-slot.scala:69:7] wire io_out_uop_uses_ldq_0; // @[issue-slot.scala:69:7] wire io_out_uop_uses_stq_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_sys_pc2epc_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_unique_0; // @[issue-slot.scala:69:7] wire io_out_uop_flush_on_commit_0; // @[issue-slot.scala:69:7] wire io_out_uop_ldst_is_rs1_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_ldst_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_lrs1_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_lrs2_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_lrs3_0; // @[issue-slot.scala:69:7] wire io_out_uop_ldst_val_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_dst_rtype_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_lrs1_rtype_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_lrs2_rtype_0; // @[issue-slot.scala:69:7] wire io_out_uop_frs3_en_0; // @[issue-slot.scala:69:7] wire io_out_uop_fp_val_0; // @[issue-slot.scala:69:7] wire io_out_uop_fp_single_0; // @[issue-slot.scala:69:7] wire io_out_uop_xcpt_pf_if_0; // @[issue-slot.scala:69:7] wire io_out_uop_xcpt_ae_if_0; // @[issue-slot.scala:69:7] wire io_out_uop_xcpt_ma_if_0; // @[issue-slot.scala:69:7] wire io_out_uop_bp_debug_if_0; // @[issue-slot.scala:69:7] wire io_out_uop_bp_xcpt_if_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_debug_fsrc_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_debug_tsrc_0; // @[issue-slot.scala:69:7] wire [3:0] io_uop_ctrl_br_type_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_ctrl_op1_sel_0; // @[issue-slot.scala:69:7] wire [2:0] io_uop_ctrl_op2_sel_0; // @[issue-slot.scala:69:7] wire [2:0] io_uop_ctrl_imm_sel_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_ctrl_op_fcn_0; // @[issue-slot.scala:69:7] wire io_uop_ctrl_fcn_dw_0; // @[issue-slot.scala:69:7] wire [2:0] io_uop_ctrl_csr_cmd_0; // @[issue-slot.scala:69:7] wire io_uop_ctrl_is_load_0; // @[issue-slot.scala:69:7] wire io_uop_ctrl_is_sta_0; // @[issue-slot.scala:69:7] wire io_uop_ctrl_is_std_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_uopc_0; // @[issue-slot.scala:69:7] wire [31:0] io_uop_inst_0; // @[issue-slot.scala:69:7] wire [31:0] io_uop_debug_inst_0; // @[issue-slot.scala:69:7] wire io_uop_is_rvc_0; // @[issue-slot.scala:69:7] wire [39:0] io_uop_debug_pc_0; // @[issue-slot.scala:69:7] wire [2:0] io_uop_iq_type_0; // @[issue-slot.scala:69:7] wire [9:0] io_uop_fu_code_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_iw_state_0; // @[issue-slot.scala:69:7] wire io_uop_is_br_0; // @[issue-slot.scala:69:7] wire io_uop_is_jalr_0; // @[issue-slot.scala:69:7] wire io_uop_is_jal_0; // @[issue-slot.scala:69:7] wire io_uop_is_sfb_0; // @[issue-slot.scala:69:7] wire [15:0] io_uop_br_mask_0; // @[issue-slot.scala:69:7] wire [3:0] io_uop_br_tag_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_ftq_idx_0; // @[issue-slot.scala:69:7] wire io_uop_edge_inst_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_pc_lob_0; // @[issue-slot.scala:69:7] wire io_uop_taken_0; // @[issue-slot.scala:69:7] wire [19:0] io_uop_imm_packed_0; // @[issue-slot.scala:69:7] wire [11:0] io_uop_csr_addr_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_rob_idx_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_ldq_idx_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_stq_idx_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_rxq_idx_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_pdst_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_prs1_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_prs2_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_prs3_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_ppred_0; // @[issue-slot.scala:69:7] wire io_uop_prs1_busy_0; // @[issue-slot.scala:69:7] wire io_uop_prs2_busy_0; // @[issue-slot.scala:69:7] wire io_uop_prs3_busy_0; // @[issue-slot.scala:69:7] wire io_uop_ppred_busy_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_stale_pdst_0; // @[issue-slot.scala:69:7] wire io_uop_exception_0; // @[issue-slot.scala:69:7] wire [63:0] io_uop_exc_cause_0; // @[issue-slot.scala:69:7] wire io_uop_bypassable_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_mem_cmd_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_mem_size_0; // @[issue-slot.scala:69:7] wire io_uop_mem_signed_0; // @[issue-slot.scala:69:7] wire io_uop_is_fence_0; // @[issue-slot.scala:69:7] wire io_uop_is_fencei_0; // @[issue-slot.scala:69:7] wire io_uop_is_amo_0; // @[issue-slot.scala:69:7] wire io_uop_uses_ldq_0; // @[issue-slot.scala:69:7] wire io_uop_uses_stq_0; // @[issue-slot.scala:69:7] wire io_uop_is_sys_pc2epc_0; // @[issue-slot.scala:69:7] wire io_uop_is_unique_0; // @[issue-slot.scala:69:7] wire io_uop_flush_on_commit_0; // @[issue-slot.scala:69:7] wire io_uop_ldst_is_rs1_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_ldst_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_lrs1_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_lrs2_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_lrs3_0; // @[issue-slot.scala:69:7] wire io_uop_ldst_val_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_dst_rtype_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_lrs1_rtype_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_lrs2_rtype_0; // @[issue-slot.scala:69:7] wire io_uop_frs3_en_0; // @[issue-slot.scala:69:7] wire io_uop_fp_val_0; // @[issue-slot.scala:69:7] wire io_uop_fp_single_0; // @[issue-slot.scala:69:7] wire io_uop_xcpt_pf_if_0; // @[issue-slot.scala:69:7] wire io_uop_xcpt_ae_if_0; // @[issue-slot.scala:69:7] wire io_uop_xcpt_ma_if_0; // @[issue-slot.scala:69:7] wire io_uop_bp_debug_if_0; // @[issue-slot.scala:69:7] wire io_uop_bp_xcpt_if_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_debug_fsrc_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_debug_tsrc_0; // @[issue-slot.scala:69:7] wire io_debug_p1_0; // @[issue-slot.scala:69:7] wire io_debug_p2_0; // @[issue-slot.scala:69:7] wire io_debug_p3_0; // @[issue-slot.scala:69:7] wire io_debug_ppred_0; // @[issue-slot.scala:69:7] wire [1:0] io_debug_state_0; // @[issue-slot.scala:69:7] wire io_valid_0; // @[issue-slot.scala:69:7] wire io_will_be_valid_0; // @[issue-slot.scala:69:7] wire io_request_0; // @[issue-slot.scala:69:7] wire io_request_hp_0; // @[issue-slot.scala:69:7] assign io_out_uop_iw_state_0 = next_state; // @[issue-slot.scala:69:7, :81:29] assign io_out_uop_uopc_0 = next_uopc; // @[issue-slot.scala:69:7, :82:29] assign io_out_uop_lrs1_rtype_0 = next_lrs1_rtype; // @[issue-slot.scala:69:7, :83:29] assign io_out_uop_lrs2_rtype_0 = next_lrs2_rtype; // @[issue-slot.scala:69:7, :84:29] reg [1:0] state; // @[issue-slot.scala:86:22] assign io_debug_state_0 = state; // @[issue-slot.scala:69:7, :86:22] reg p1; // @[issue-slot.scala:87:22] assign io_debug_p1_0 = p1; // @[issue-slot.scala:69:7, :87:22] wire next_p1 = p1; // @[issue-slot.scala:87:22, :163:25] reg p2; // @[issue-slot.scala:88:22] assign io_debug_p2_0 = p2; // @[issue-slot.scala:69:7, :88:22] wire next_p2 = p2; // @[issue-slot.scala:88:22, :164:25] reg p3; // @[issue-slot.scala:89:22] assign io_debug_p3_0 = p3; // @[issue-slot.scala:69:7, :89:22] wire next_p3 = p3; // @[issue-slot.scala:89:22, :165:25] reg ppred; // @[issue-slot.scala:90:22] assign io_debug_ppred_0 = ppred; // @[issue-slot.scala:69:7, :90:22] wire next_ppred = ppred; // @[issue-slot.scala:90:22, :166:28] reg [6:0] slot_uop_uopc; // @[issue-slot.scala:102:25] reg [31:0] slot_uop_inst; // @[issue-slot.scala:102:25] assign io_out_uop_inst_0 = slot_uop_inst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_inst_0 = slot_uop_inst; // @[issue-slot.scala:69:7, :102:25] reg [31:0] slot_uop_debug_inst; // @[issue-slot.scala:102:25] assign io_out_uop_debug_inst_0 = slot_uop_debug_inst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_debug_inst_0 = slot_uop_debug_inst; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_rvc; // @[issue-slot.scala:102:25] assign io_out_uop_is_rvc_0 = slot_uop_is_rvc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_rvc_0 = slot_uop_is_rvc; // @[issue-slot.scala:69:7, :102:25] reg [39:0] slot_uop_debug_pc; // @[issue-slot.scala:102:25] assign io_out_uop_debug_pc_0 = slot_uop_debug_pc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_debug_pc_0 = slot_uop_debug_pc; // @[issue-slot.scala:69:7, :102:25] reg [2:0] slot_uop_iq_type; // @[issue-slot.scala:102:25] assign io_out_uop_iq_type_0 = slot_uop_iq_type; // @[issue-slot.scala:69:7, :102:25] assign io_uop_iq_type_0 = slot_uop_iq_type; // @[issue-slot.scala:69:7, :102:25] reg [9:0] slot_uop_fu_code; // @[issue-slot.scala:102:25] assign io_out_uop_fu_code_0 = slot_uop_fu_code; // @[issue-slot.scala:69:7, :102:25] assign io_uop_fu_code_0 = slot_uop_fu_code; // @[issue-slot.scala:69:7, :102:25] reg [3:0] slot_uop_ctrl_br_type; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_br_type_0 = slot_uop_ctrl_br_type; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_br_type_0 = slot_uop_ctrl_br_type; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_ctrl_op1_sel; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_op1_sel_0 = slot_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_op1_sel_0 = slot_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7, :102:25] reg [2:0] slot_uop_ctrl_op2_sel; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_op2_sel_0 = slot_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_op2_sel_0 = slot_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7, :102:25] reg [2:0] slot_uop_ctrl_imm_sel; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_imm_sel_0 = slot_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_imm_sel_0 = slot_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_ctrl_op_fcn; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_op_fcn_0 = slot_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_op_fcn_0 = slot_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_fcn_dw_0 = slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_fcn_dw_0 = slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7, :102:25] reg [2:0] slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_csr_cmd_0 = slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_csr_cmd_0 = slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ctrl_is_load; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_is_load_0 = slot_uop_ctrl_is_load; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_is_load_0 = slot_uop_ctrl_is_load; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ctrl_is_sta; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_is_sta_0 = slot_uop_ctrl_is_sta; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_is_sta_0 = slot_uop_ctrl_is_sta; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ctrl_is_std; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_is_std_0 = slot_uop_ctrl_is_std; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_is_std_0 = slot_uop_ctrl_is_std; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_iw_state; // @[issue-slot.scala:102:25] assign io_uop_iw_state_0 = slot_uop_iw_state; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_iw_p1_poisoned; // @[issue-slot.scala:102:25] reg slot_uop_iw_p2_poisoned; // @[issue-slot.scala:102:25] reg slot_uop_is_br; // @[issue-slot.scala:102:25] assign io_out_uop_is_br_0 = slot_uop_is_br; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_br_0 = slot_uop_is_br; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_jalr; // @[issue-slot.scala:102:25] assign io_out_uop_is_jalr_0 = slot_uop_is_jalr; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_jalr_0 = slot_uop_is_jalr; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_jal; // @[issue-slot.scala:102:25] assign io_out_uop_is_jal_0 = slot_uop_is_jal; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_jal_0 = slot_uop_is_jal; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_sfb; // @[issue-slot.scala:102:25] assign io_out_uop_is_sfb_0 = slot_uop_is_sfb; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_sfb_0 = slot_uop_is_sfb; // @[issue-slot.scala:69:7, :102:25] reg [15:0] slot_uop_br_mask; // @[issue-slot.scala:102:25] assign io_uop_br_mask_0 = slot_uop_br_mask; // @[issue-slot.scala:69:7, :102:25] reg [3:0] slot_uop_br_tag; // @[issue-slot.scala:102:25] assign io_out_uop_br_tag_0 = slot_uop_br_tag; // @[issue-slot.scala:69:7, :102:25] assign io_uop_br_tag_0 = slot_uop_br_tag; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_ftq_idx; // @[issue-slot.scala:102:25] assign io_out_uop_ftq_idx_0 = slot_uop_ftq_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ftq_idx_0 = slot_uop_ftq_idx; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_edge_inst; // @[issue-slot.scala:102:25] assign io_out_uop_edge_inst_0 = slot_uop_edge_inst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_edge_inst_0 = slot_uop_edge_inst; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_pc_lob; // @[issue-slot.scala:102:25] assign io_out_uop_pc_lob_0 = slot_uop_pc_lob; // @[issue-slot.scala:69:7, :102:25] assign io_uop_pc_lob_0 = slot_uop_pc_lob; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_taken; // @[issue-slot.scala:102:25] assign io_out_uop_taken_0 = slot_uop_taken; // @[issue-slot.scala:69:7, :102:25] assign io_uop_taken_0 = slot_uop_taken; // @[issue-slot.scala:69:7, :102:25] reg [19:0] slot_uop_imm_packed; // @[issue-slot.scala:102:25] assign io_out_uop_imm_packed_0 = slot_uop_imm_packed; // @[issue-slot.scala:69:7, :102:25] assign io_uop_imm_packed_0 = slot_uop_imm_packed; // @[issue-slot.scala:69:7, :102:25] reg [11:0] slot_uop_csr_addr; // @[issue-slot.scala:102:25] assign io_out_uop_csr_addr_0 = slot_uop_csr_addr; // @[issue-slot.scala:69:7, :102:25] assign io_uop_csr_addr_0 = slot_uop_csr_addr; // @[issue-slot.scala:69:7, :102:25] reg [6:0] slot_uop_rob_idx; // @[issue-slot.scala:102:25] assign io_out_uop_rob_idx_0 = slot_uop_rob_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_rob_idx_0 = slot_uop_rob_idx; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_ldq_idx; // @[issue-slot.scala:102:25] assign io_out_uop_ldq_idx_0 = slot_uop_ldq_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ldq_idx_0 = slot_uop_ldq_idx; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_stq_idx; // @[issue-slot.scala:102:25] assign io_out_uop_stq_idx_0 = slot_uop_stq_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_stq_idx_0 = slot_uop_stq_idx; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_rxq_idx; // @[issue-slot.scala:102:25] assign io_out_uop_rxq_idx_0 = slot_uop_rxq_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_rxq_idx_0 = slot_uop_rxq_idx; // @[issue-slot.scala:69:7, :102:25] reg [6:0] slot_uop_pdst; // @[issue-slot.scala:102:25] assign io_out_uop_pdst_0 = slot_uop_pdst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_pdst_0 = slot_uop_pdst; // @[issue-slot.scala:69:7, :102:25] reg [6:0] slot_uop_prs1; // @[issue-slot.scala:102:25] assign io_out_uop_prs1_0 = slot_uop_prs1; // @[issue-slot.scala:69:7, :102:25] assign io_uop_prs1_0 = slot_uop_prs1; // @[issue-slot.scala:69:7, :102:25] reg [6:0] slot_uop_prs2; // @[issue-slot.scala:102:25] assign io_out_uop_prs2_0 = slot_uop_prs2; // @[issue-slot.scala:69:7, :102:25] assign io_uop_prs2_0 = slot_uop_prs2; // @[issue-slot.scala:69:7, :102:25] reg [6:0] slot_uop_prs3; // @[issue-slot.scala:102:25] assign io_out_uop_prs3_0 = slot_uop_prs3; // @[issue-slot.scala:69:7, :102:25] assign io_uop_prs3_0 = slot_uop_prs3; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_ppred; // @[issue-slot.scala:102:25] assign io_out_uop_ppred_0 = slot_uop_ppred; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ppred_0 = slot_uop_ppred; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_prs1_busy; // @[issue-slot.scala:102:25] assign io_uop_prs1_busy_0 = slot_uop_prs1_busy; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_prs2_busy; // @[issue-slot.scala:102:25] assign io_uop_prs2_busy_0 = slot_uop_prs2_busy; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_prs3_busy; // @[issue-slot.scala:102:25] assign io_uop_prs3_busy_0 = slot_uop_prs3_busy; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ppred_busy; // @[issue-slot.scala:102:25] assign io_uop_ppred_busy_0 = slot_uop_ppred_busy; // @[issue-slot.scala:69:7, :102:25] reg [6:0] slot_uop_stale_pdst; // @[issue-slot.scala:102:25] assign io_out_uop_stale_pdst_0 = slot_uop_stale_pdst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_stale_pdst_0 = slot_uop_stale_pdst; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_exception; // @[issue-slot.scala:102:25] assign io_out_uop_exception_0 = slot_uop_exception; // @[issue-slot.scala:69:7, :102:25] assign io_uop_exception_0 = slot_uop_exception; // @[issue-slot.scala:69:7, :102:25] reg [63:0] slot_uop_exc_cause; // @[issue-slot.scala:102:25] assign io_out_uop_exc_cause_0 = slot_uop_exc_cause; // @[issue-slot.scala:69:7, :102:25] assign io_uop_exc_cause_0 = slot_uop_exc_cause; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_bypassable; // @[issue-slot.scala:102:25] assign io_out_uop_bypassable_0 = slot_uop_bypassable; // @[issue-slot.scala:69:7, :102:25] assign io_uop_bypassable_0 = slot_uop_bypassable; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_mem_cmd; // @[issue-slot.scala:102:25] assign io_out_uop_mem_cmd_0 = slot_uop_mem_cmd; // @[issue-slot.scala:69:7, :102:25] assign io_uop_mem_cmd_0 = slot_uop_mem_cmd; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_mem_size; // @[issue-slot.scala:102:25] assign io_out_uop_mem_size_0 = slot_uop_mem_size; // @[issue-slot.scala:69:7, :102:25] assign io_uop_mem_size_0 = slot_uop_mem_size; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_mem_signed; // @[issue-slot.scala:102:25] assign io_out_uop_mem_signed_0 = slot_uop_mem_signed; // @[issue-slot.scala:69:7, :102:25] assign io_uop_mem_signed_0 = slot_uop_mem_signed; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_fence; // @[issue-slot.scala:102:25] assign io_out_uop_is_fence_0 = slot_uop_is_fence; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_fence_0 = slot_uop_is_fence; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_fencei; // @[issue-slot.scala:102:25] assign io_out_uop_is_fencei_0 = slot_uop_is_fencei; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_fencei_0 = slot_uop_is_fencei; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_amo; // @[issue-slot.scala:102:25] assign io_out_uop_is_amo_0 = slot_uop_is_amo; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_amo_0 = slot_uop_is_amo; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_uses_ldq; // @[issue-slot.scala:102:25] assign io_out_uop_uses_ldq_0 = slot_uop_uses_ldq; // @[issue-slot.scala:69:7, :102:25] assign io_uop_uses_ldq_0 = slot_uop_uses_ldq; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_uses_stq; // @[issue-slot.scala:102:25] assign io_out_uop_uses_stq_0 = slot_uop_uses_stq; // @[issue-slot.scala:69:7, :102:25] assign io_uop_uses_stq_0 = slot_uop_uses_stq; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_sys_pc2epc; // @[issue-slot.scala:102:25] assign io_out_uop_is_sys_pc2epc_0 = slot_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_sys_pc2epc_0 = slot_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_unique; // @[issue-slot.scala:102:25] assign io_out_uop_is_unique_0 = slot_uop_is_unique; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_unique_0 = slot_uop_is_unique; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_flush_on_commit; // @[issue-slot.scala:102:25] assign io_out_uop_flush_on_commit_0 = slot_uop_flush_on_commit; // @[issue-slot.scala:69:7, :102:25] assign io_uop_flush_on_commit_0 = slot_uop_flush_on_commit; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ldst_is_rs1; // @[issue-slot.scala:102:25] assign io_out_uop_ldst_is_rs1_0 = slot_uop_ldst_is_rs1; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ldst_is_rs1_0 = slot_uop_ldst_is_rs1; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_ldst; // @[issue-slot.scala:102:25] assign io_out_uop_ldst_0 = slot_uop_ldst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ldst_0 = slot_uop_ldst; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_lrs1; // @[issue-slot.scala:102:25] assign io_out_uop_lrs1_0 = slot_uop_lrs1; // @[issue-slot.scala:69:7, :102:25] assign io_uop_lrs1_0 = slot_uop_lrs1; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_lrs2; // @[issue-slot.scala:102:25] assign io_out_uop_lrs2_0 = slot_uop_lrs2; // @[issue-slot.scala:69:7, :102:25] assign io_uop_lrs2_0 = slot_uop_lrs2; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_lrs3; // @[issue-slot.scala:102:25] assign io_out_uop_lrs3_0 = slot_uop_lrs3; // @[issue-slot.scala:69:7, :102:25] assign io_uop_lrs3_0 = slot_uop_lrs3; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ldst_val; // @[issue-slot.scala:102:25] assign io_out_uop_ldst_val_0 = slot_uop_ldst_val; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ldst_val_0 = slot_uop_ldst_val; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_dst_rtype; // @[issue-slot.scala:102:25] assign io_out_uop_dst_rtype_0 = slot_uop_dst_rtype; // @[issue-slot.scala:69:7, :102:25] assign io_uop_dst_rtype_0 = slot_uop_dst_rtype; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_lrs1_rtype; // @[issue-slot.scala:102:25] reg [1:0] slot_uop_lrs2_rtype; // @[issue-slot.scala:102:25] reg slot_uop_frs3_en; // @[issue-slot.scala:102:25] assign io_out_uop_frs3_en_0 = slot_uop_frs3_en; // @[issue-slot.scala:69:7, :102:25] assign io_uop_frs3_en_0 = slot_uop_frs3_en; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_fp_val; // @[issue-slot.scala:102:25] assign io_out_uop_fp_val_0 = slot_uop_fp_val; // @[issue-slot.scala:69:7, :102:25] assign io_uop_fp_val_0 = slot_uop_fp_val; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_fp_single; // @[issue-slot.scala:102:25] assign io_out_uop_fp_single_0 = slot_uop_fp_single; // @[issue-slot.scala:69:7, :102:25] assign io_uop_fp_single_0 = slot_uop_fp_single; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_xcpt_pf_if; // @[issue-slot.scala:102:25] assign io_out_uop_xcpt_pf_if_0 = slot_uop_xcpt_pf_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_xcpt_pf_if_0 = slot_uop_xcpt_pf_if; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_xcpt_ae_if; // @[issue-slot.scala:102:25] assign io_out_uop_xcpt_ae_if_0 = slot_uop_xcpt_ae_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_xcpt_ae_if_0 = slot_uop_xcpt_ae_if; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_xcpt_ma_if; // @[issue-slot.scala:102:25] assign io_out_uop_xcpt_ma_if_0 = slot_uop_xcpt_ma_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_xcpt_ma_if_0 = slot_uop_xcpt_ma_if; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_bp_debug_if; // @[issue-slot.scala:102:25] assign io_out_uop_bp_debug_if_0 = slot_uop_bp_debug_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_bp_debug_if_0 = slot_uop_bp_debug_if; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_bp_xcpt_if; // @[issue-slot.scala:102:25] assign io_out_uop_bp_xcpt_if_0 = slot_uop_bp_xcpt_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_bp_xcpt_if_0 = slot_uop_bp_xcpt_if; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_debug_fsrc; // @[issue-slot.scala:102:25] assign io_out_uop_debug_fsrc_0 = slot_uop_debug_fsrc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_debug_fsrc_0 = slot_uop_debug_fsrc; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_debug_tsrc; // @[issue-slot.scala:102:25] assign io_out_uop_debug_tsrc_0 = slot_uop_debug_tsrc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_debug_tsrc_0 = slot_uop_debug_tsrc; // @[issue-slot.scala:69:7, :102:25] wire [6:0] next_uop_uopc = io_in_uop_valid_0 ? io_in_uop_bits_uopc_0 : slot_uop_uopc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [31:0] next_uop_inst = io_in_uop_valid_0 ? io_in_uop_bits_inst_0 : slot_uop_inst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [31:0] next_uop_debug_inst = io_in_uop_valid_0 ? io_in_uop_bits_debug_inst_0 : slot_uop_debug_inst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_rvc = io_in_uop_valid_0 ? io_in_uop_bits_is_rvc_0 : slot_uop_is_rvc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [39:0] next_uop_debug_pc = io_in_uop_valid_0 ? io_in_uop_bits_debug_pc_0 : slot_uop_debug_pc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [2:0] next_uop_iq_type = io_in_uop_valid_0 ? io_in_uop_bits_iq_type_0 : slot_uop_iq_type; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [9:0] next_uop_fu_code = io_in_uop_valid_0 ? io_in_uop_bits_fu_code_0 : slot_uop_fu_code; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [3:0] next_uop_ctrl_br_type = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_br_type_0 : slot_uop_ctrl_br_type; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_ctrl_op1_sel = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_op1_sel_0 : slot_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [2:0] next_uop_ctrl_op2_sel = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_op2_sel_0 : slot_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [2:0] next_uop_ctrl_imm_sel = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_imm_sel_0 : slot_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_ctrl_op_fcn = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_op_fcn_0 : slot_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ctrl_fcn_dw = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_fcn_dw_0 : slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [2:0] next_uop_ctrl_csr_cmd = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_csr_cmd_0 : slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ctrl_is_load = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_is_load_0 : slot_uop_ctrl_is_load; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ctrl_is_sta = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_is_sta_0 : slot_uop_ctrl_is_sta; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ctrl_is_std = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_is_std_0 : slot_uop_ctrl_is_std; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_iw_state = io_in_uop_valid_0 ? io_in_uop_bits_iw_state_0 : slot_uop_iw_state; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_iw_p1_poisoned = ~io_in_uop_valid_0 & slot_uop_iw_p1_poisoned; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_iw_p2_poisoned = ~io_in_uop_valid_0 & slot_uop_iw_p2_poisoned; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_br = io_in_uop_valid_0 ? io_in_uop_bits_is_br_0 : slot_uop_is_br; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_jalr = io_in_uop_valid_0 ? io_in_uop_bits_is_jalr_0 : slot_uop_is_jalr; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_jal = io_in_uop_valid_0 ? io_in_uop_bits_is_jal_0 : slot_uop_is_jal; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_sfb = io_in_uop_valid_0 ? io_in_uop_bits_is_sfb_0 : slot_uop_is_sfb; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [15:0] next_uop_br_mask = io_in_uop_valid_0 ? io_in_uop_bits_br_mask_0 : slot_uop_br_mask; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [3:0] next_uop_br_tag = io_in_uop_valid_0 ? io_in_uop_bits_br_tag_0 : slot_uop_br_tag; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_ftq_idx = io_in_uop_valid_0 ? io_in_uop_bits_ftq_idx_0 : slot_uop_ftq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_edge_inst = io_in_uop_valid_0 ? io_in_uop_bits_edge_inst_0 : slot_uop_edge_inst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_pc_lob = io_in_uop_valid_0 ? io_in_uop_bits_pc_lob_0 : slot_uop_pc_lob; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_taken = io_in_uop_valid_0 ? io_in_uop_bits_taken_0 : slot_uop_taken; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [19:0] next_uop_imm_packed = io_in_uop_valid_0 ? io_in_uop_bits_imm_packed_0 : slot_uop_imm_packed; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [11:0] next_uop_csr_addr = io_in_uop_valid_0 ? io_in_uop_bits_csr_addr_0 : slot_uop_csr_addr; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [6:0] next_uop_rob_idx = io_in_uop_valid_0 ? io_in_uop_bits_rob_idx_0 : slot_uop_rob_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_ldq_idx = io_in_uop_valid_0 ? io_in_uop_bits_ldq_idx_0 : slot_uop_ldq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_stq_idx = io_in_uop_valid_0 ? io_in_uop_bits_stq_idx_0 : slot_uop_stq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_rxq_idx = io_in_uop_valid_0 ? io_in_uop_bits_rxq_idx_0 : slot_uop_rxq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [6:0] next_uop_pdst = io_in_uop_valid_0 ? io_in_uop_bits_pdst_0 : slot_uop_pdst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [6:0] next_uop_prs1 = io_in_uop_valid_0 ? io_in_uop_bits_prs1_0 : slot_uop_prs1; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [6:0] next_uop_prs2 = io_in_uop_valid_0 ? io_in_uop_bits_prs2_0 : slot_uop_prs2; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [6:0] next_uop_prs3 = io_in_uop_valid_0 ? io_in_uop_bits_prs3_0 : slot_uop_prs3; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_ppred = io_in_uop_valid_0 ? io_in_uop_bits_ppred_0 : slot_uop_ppred; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_prs1_busy = io_in_uop_valid_0 ? io_in_uop_bits_prs1_busy_0 : slot_uop_prs1_busy; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_prs2_busy = io_in_uop_valid_0 ? io_in_uop_bits_prs2_busy_0 : slot_uop_prs2_busy; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_prs3_busy = io_in_uop_valid_0 ? io_in_uop_bits_prs3_busy_0 : slot_uop_prs3_busy; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ppred_busy = io_in_uop_valid_0 ? io_in_uop_bits_ppred_busy_0 : slot_uop_ppred_busy; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [6:0] next_uop_stale_pdst = io_in_uop_valid_0 ? io_in_uop_bits_stale_pdst_0 : slot_uop_stale_pdst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_exception = io_in_uop_valid_0 ? io_in_uop_bits_exception_0 : slot_uop_exception; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [63:0] next_uop_exc_cause = io_in_uop_valid_0 ? io_in_uop_bits_exc_cause_0 : slot_uop_exc_cause; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_bypassable = io_in_uop_valid_0 ? io_in_uop_bits_bypassable_0 : slot_uop_bypassable; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_mem_cmd = io_in_uop_valid_0 ? io_in_uop_bits_mem_cmd_0 : slot_uop_mem_cmd; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_mem_size = io_in_uop_valid_0 ? io_in_uop_bits_mem_size_0 : slot_uop_mem_size; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_mem_signed = io_in_uop_valid_0 ? io_in_uop_bits_mem_signed_0 : slot_uop_mem_signed; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_fence = io_in_uop_valid_0 ? io_in_uop_bits_is_fence_0 : slot_uop_is_fence; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_fencei = io_in_uop_valid_0 ? io_in_uop_bits_is_fencei_0 : slot_uop_is_fencei; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_amo = io_in_uop_valid_0 ? io_in_uop_bits_is_amo_0 : slot_uop_is_amo; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_uses_ldq = io_in_uop_valid_0 ? io_in_uop_bits_uses_ldq_0 : slot_uop_uses_ldq; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_uses_stq = io_in_uop_valid_0 ? io_in_uop_bits_uses_stq_0 : slot_uop_uses_stq; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_sys_pc2epc = io_in_uop_valid_0 ? io_in_uop_bits_is_sys_pc2epc_0 : slot_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_unique = io_in_uop_valid_0 ? io_in_uop_bits_is_unique_0 : slot_uop_is_unique; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_flush_on_commit = io_in_uop_valid_0 ? io_in_uop_bits_flush_on_commit_0 : slot_uop_flush_on_commit; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ldst_is_rs1 = io_in_uop_valid_0 ? io_in_uop_bits_ldst_is_rs1_0 : slot_uop_ldst_is_rs1; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_ldst = io_in_uop_valid_0 ? io_in_uop_bits_ldst_0 : slot_uop_ldst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_lrs1 = io_in_uop_valid_0 ? io_in_uop_bits_lrs1_0 : slot_uop_lrs1; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_lrs2 = io_in_uop_valid_0 ? io_in_uop_bits_lrs2_0 : slot_uop_lrs2; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_lrs3 = io_in_uop_valid_0 ? io_in_uop_bits_lrs3_0 : slot_uop_lrs3; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ldst_val = io_in_uop_valid_0 ? io_in_uop_bits_ldst_val_0 : slot_uop_ldst_val; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_dst_rtype = io_in_uop_valid_0 ? io_in_uop_bits_dst_rtype_0 : slot_uop_dst_rtype; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_lrs1_rtype = io_in_uop_valid_0 ? io_in_uop_bits_lrs1_rtype_0 : slot_uop_lrs1_rtype; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_lrs2_rtype = io_in_uop_valid_0 ? io_in_uop_bits_lrs2_rtype_0 : slot_uop_lrs2_rtype; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_frs3_en = io_in_uop_valid_0 ? io_in_uop_bits_frs3_en_0 : slot_uop_frs3_en; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_fp_val = io_in_uop_valid_0 ? io_in_uop_bits_fp_val_0 : slot_uop_fp_val; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_fp_single = io_in_uop_valid_0 ? io_in_uop_bits_fp_single_0 : slot_uop_fp_single; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_xcpt_pf_if = io_in_uop_valid_0 ? io_in_uop_bits_xcpt_pf_if_0 : slot_uop_xcpt_pf_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_xcpt_ae_if = io_in_uop_valid_0 ? io_in_uop_bits_xcpt_ae_if_0 : slot_uop_xcpt_ae_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_xcpt_ma_if = io_in_uop_valid_0 ? io_in_uop_bits_xcpt_ma_if_0 : slot_uop_xcpt_ma_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_bp_debug_if = io_in_uop_valid_0 ? io_in_uop_bits_bp_debug_if_0 : slot_uop_bp_debug_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_bp_xcpt_if = io_in_uop_valid_0 ? io_in_uop_bits_bp_xcpt_if_0 : slot_uop_bp_xcpt_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_debug_fsrc = io_in_uop_valid_0 ? io_in_uop_bits_debug_fsrc_0 : slot_uop_debug_fsrc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_debug_tsrc = io_in_uop_valid_0 ? io_in_uop_bits_debug_tsrc_0 : slot_uop_debug_tsrc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire _T_11 = state == 2'h2; // @[issue-slot.scala:86:22, :134:25] wire _T_7 = io_grant_0 & state == 2'h1 | io_grant_0 & _T_11 & p1 & p2 & ppred; // @[issue-slot.scala:69:7, :86:22, :87:22, :88:22, :90:22, :133:{26,36,52}, :134:{15,25,40,46,52}] wire _T_12 = io_grant_0 & _T_11; // @[issue-slot.scala:69:7, :134:25, :139:25] wire _GEN = io_kill_0 | _T_7; // @[issue-slot.scala:69:7, :102:25, :131:18, :133:52, :134:63, :139:51] wire _GEN_0 = _GEN | ~(_T_12 & p1); // @[issue-slot.scala:87:22, :102:25, :131:18, :134:63, :139:{25,51}, :140:62, :142:17, :143:23] assign next_uopc = _GEN_0 ? slot_uop_uopc : 7'h3; // @[issue-slot.scala:82:29, :102:25, :131:18, :134:63, :139:51] assign next_lrs1_rtype = _GEN_0 ? slot_uop_lrs1_rtype : 2'h2; // @[issue-slot.scala:83:29, :102:25, :131:18, :134:63, :139:51] wire _GEN_1 = _GEN | ~_T_12 | p1; // @[issue-slot.scala:87:22, :102:25, :131:18, :134:63, :139:{25,51}, :140:62, :142:17] assign next_lrs2_rtype = _GEN_1 ? slot_uop_lrs2_rtype : 2'h2; // @[issue-slot.scala:84:29, :102:25, :131:18, :134:63, :139:51, :140:62, :142:17]

Generate the Verilog code corresponding to the following Chisel files. File MulRecFN.scala: /*============================================================================ This Chisel source file is part of a pre-release version of the HardFloat IEEE Floating-Point Arithmetic Package, by John R. Hauser (ported from Verilog to Chisel by Andrew Waterman). Copyright 2019, 2020 The Regents of the University of California. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions, and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions, and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the University nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. =============================================================================*/ package hardfloat import chisel3._ import chisel3.util._ import consts._ //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- class MulFullRawFN(expWidth: Int, sigWidth: Int) extends chisel3.RawModule { val io = IO(new Bundle { val a = Input(new RawFloat(expWidth, sigWidth)) val b = Input(new RawFloat(expWidth, sigWidth)) val invalidExc = Output(Bool()) val rawOut = Output(new RawFloat(expWidth, sigWidth*2 - 1)) }) /*------------------------------------------------------------------------ *------------------------------------------------------------------------*/ val notSigNaN_invalidExc = (io.a.isInf && io.b.isZero) || (io.a.isZero && io.b.isInf) val notNaN_isInfOut = io.a.isInf || io.b.isInf val notNaN_isZeroOut = io.a.isZero || io.b.isZero val notNaN_signOut = io.a.sign ^ io.b.sign val common_sExpOut = io.a.sExp + io.b.sExp - (1<<expWidth).S val common_sigOut = (io.a.sig * io.b.sig)(sigWidth*2 - 1, 0) /*------------------------------------------------------------------------ *------------------------------------------------------------------------*/ io.invalidExc := isSigNaNRawFloat(io.a) || isSigNaNRawFloat(io.b) || notSigNaN_invalidExc io.rawOut.isInf := notNaN_isInfOut io.rawOut.isZero := notNaN_isZeroOut io.rawOut.sExp := common_sExpOut io.rawOut.isNaN := io.a.isNaN || io.b.isNaN io.rawOut.sign := notNaN_signOut io.rawOut.sig := common_sigOut } class MulRawFN(expWidth: Int, sigWidth: Int) extends chisel3.RawModule { val io = IO(new Bundle { val a = Input(new RawFloat(expWidth, sigWidth)) val b = Input(new RawFloat(expWidth, sigWidth)) val invalidExc = Output(Bool()) val rawOut = Output(new RawFloat(expWidth, sigWidth + 2)) }) val mulFullRaw = Module(new MulFullRawFN(expWidth, sigWidth)) mulFullRaw.io.a := io.a mulFullRaw.io.b := io.b io.invalidExc := mulFullRaw.io.invalidExc io.rawOut := mulFullRaw.io.rawOut io.rawOut.sig := { val sig = mulFullRaw.io.rawOut.sig Cat(sig >> (sigWidth - 2), sig(sigWidth - 3, 0).orR) } } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- class MulRecFN(expWidth: Int, sigWidth: Int) extends chisel3.RawModule { val io = IO(new Bundle { val a = Input(UInt((expWidth + sigWidth + 1).W)) val b = Input(UInt((expWidth + sigWidth + 1).W)) val roundingMode = Input(UInt(3.W)) val detectTininess = Input(Bool()) val out = Output(UInt((expWidth + sigWidth + 1).W)) val exceptionFlags = Output(UInt(5.W)) }) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val mulRawFN = Module(new MulRawFN(expWidth, sigWidth)) mulRawFN.io.a := rawFloatFromRecFN(expWidth, sigWidth, io.a) mulRawFN.io.b := rawFloatFromRecFN(expWidth, sigWidth, io.b) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val roundRawFNToRecFN = Module(new RoundRawFNToRecFN(expWidth, sigWidth, 0)) roundRawFNToRecFN.io.invalidExc := mulRawFN.io.invalidExc roundRawFNToRecFN.io.infiniteExc := false.B roundRawFNToRecFN.io.in := mulRawFN.io.rawOut roundRawFNToRecFN.io.roundingMode := io.roundingMode roundRawFNToRecFN.io.detectTininess := io.detectTininess io.out := roundRawFNToRecFN.io.out io.exceptionFlags := roundRawFNToRecFN.io.exceptionFlags } File rawFloatFromRecFN.scala: /*============================================================================ This Chisel source file is part of a pre-release version of the HardFloat IEEE Floating-Point Arithmetic Package, by John R. Hauser (with some contributions from Yunsup Lee and Andrew Waterman, mainly concerning testing). Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of California. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions, and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions, and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the University nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. =============================================================================*/ package hardfloat import chisel3._ import chisel3.util._ /*---------------------------------------------------------------------------- | In the result, no more than one of 'isNaN', 'isInf', and 'isZero' will be | set. *----------------------------------------------------------------------------*/ object rawFloatFromRecFN { def apply(expWidth: Int, sigWidth: Int, in: Bits): RawFloat = { val exp = in(expWidth + sigWidth - 1, sigWidth - 1) val isZero = exp(expWidth, expWidth - 2) === 0.U val isSpecial = exp(expWidth, expWidth - 1) === 3.U val out = Wire(new RawFloat(expWidth, sigWidth)) out.isNaN := isSpecial && exp(expWidth - 2) out.isInf := isSpecial && ! exp(expWidth - 2) out.isZero := isZero out.sign := in(expWidth + sigWidth) out.sExp := exp.zext out.sig := 0.U(1.W) ## ! isZero ## in(sigWidth - 2, 0) out } }

module MulRecFN_43( // @[MulRecFN.scala:100:7] input [32:0] io_a, // @[MulRecFN.scala:102:16] input [32:0] io_b, // @[MulRecFN.scala:102:16] output [32:0] io_out // @[MulRecFN.scala:102:16] ); wire _mulRawFN_io_invalidExc; // @[MulRecFN.scala:113:26] wire _mulRawFN_io_rawOut_isNaN; // @[MulRecFN.scala:113:26] wire _mulRawFN_io_rawOut_isInf; // @[MulRecFN.scala:113:26] wire _mulRawFN_io_rawOut_isZero; // @[MulRecFN.scala:113:26] wire _mulRawFN_io_rawOut_sign; // @[MulRecFN.scala:113:26] wire [9:0] _mulRawFN_io_rawOut_sExp; // @[MulRecFN.scala:113:26] wire [26:0] _mulRawFN_io_rawOut_sig; // @[MulRecFN.scala:113:26] wire [32:0] io_a_0 = io_a; // @[MulRecFN.scala:100:7] wire [32:0] io_b_0 = io_b; // @[MulRecFN.scala:100:7] wire io_detectTininess = 1'h1; // @[MulRecFN.scala:100:7, :102:16, :121:15] wire [2:0] io_roundingMode = 3'h0; // @[MulRecFN.scala:100:7, :102:16, :121:15] wire [32:0] io_out_0; // @[MulRecFN.scala:100:7] wire [4:0] io_exceptionFlags; // @[MulRecFN.scala:100:7] wire [8:0] mulRawFN_io_a_exp = io_a_0[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _mulRawFN_io_a_isZero_T = mulRawFN_io_a_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire mulRawFN_io_a_isZero = _mulRawFN_io_a_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire mulRawFN_io_a_out_isZero = mulRawFN_io_a_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _mulRawFN_io_a_isSpecial_T = mulRawFN_io_a_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire mulRawFN_io_a_isSpecial = &_mulRawFN_io_a_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _mulRawFN_io_a_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33] wire _mulRawFN_io_a_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33] wire _mulRawFN_io_a_out_sign_T; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _mulRawFN_io_a_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _mulRawFN_io_a_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44] wire mulRawFN_io_a_out_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire mulRawFN_io_a_out_isInf; // @[rawFloatFromRecFN.scala:55:23] wire mulRawFN_io_a_out_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] mulRawFN_io_a_out_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] mulRawFN_io_a_out_sig; // @[rawFloatFromRecFN.scala:55:23] wire _mulRawFN_io_a_out_isNaN_T = mulRawFN_io_a_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _mulRawFN_io_a_out_isInf_T = mulRawFN_io_a_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _mulRawFN_io_a_out_isNaN_T_1 = mulRawFN_io_a_isSpecial & _mulRawFN_io_a_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign mulRawFN_io_a_out_isNaN = _mulRawFN_io_a_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _mulRawFN_io_a_out_isInf_T_1 = ~_mulRawFN_io_a_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _mulRawFN_io_a_out_isInf_T_2 = mulRawFN_io_a_isSpecial & _mulRawFN_io_a_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign mulRawFN_io_a_out_isInf = _mulRawFN_io_a_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _mulRawFN_io_a_out_sign_T = io_a_0[32]; // @[rawFloatFromRecFN.scala:59:25] assign mulRawFN_io_a_out_sign = _mulRawFN_io_a_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _mulRawFN_io_a_out_sExp_T = {1'h0, mulRawFN_io_a_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign mulRawFN_io_a_out_sExp = _mulRawFN_io_a_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _mulRawFN_io_a_out_sig_T = ~mulRawFN_io_a_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _mulRawFN_io_a_out_sig_T_1 = {1'h0, _mulRawFN_io_a_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _mulRawFN_io_a_out_sig_T_2 = io_a_0[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _mulRawFN_io_a_out_sig_T_3 = {_mulRawFN_io_a_out_sig_T_1, _mulRawFN_io_a_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign mulRawFN_io_a_out_sig = _mulRawFN_io_a_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire [8:0] mulRawFN_io_b_exp = io_b_0[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _mulRawFN_io_b_isZero_T = mulRawFN_io_b_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire mulRawFN_io_b_isZero = _mulRawFN_io_b_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire mulRawFN_io_b_out_isZero = mulRawFN_io_b_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _mulRawFN_io_b_isSpecial_T = mulRawFN_io_b_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire mulRawFN_io_b_isSpecial = &_mulRawFN_io_b_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _mulRawFN_io_b_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33] wire _mulRawFN_io_b_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33] wire _mulRawFN_io_b_out_sign_T; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _mulRawFN_io_b_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _mulRawFN_io_b_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44] wire mulRawFN_io_b_out_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire mulRawFN_io_b_out_isInf; // @[rawFloatFromRecFN.scala:55:23] wire mulRawFN_io_b_out_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] mulRawFN_io_b_out_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] mulRawFN_io_b_out_sig; // @[rawFloatFromRecFN.scala:55:23] wire _mulRawFN_io_b_out_isNaN_T = mulRawFN_io_b_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _mulRawFN_io_b_out_isInf_T = mulRawFN_io_b_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _mulRawFN_io_b_out_isNaN_T_1 = mulRawFN_io_b_isSpecial & _mulRawFN_io_b_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign mulRawFN_io_b_out_isNaN = _mulRawFN_io_b_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _mulRawFN_io_b_out_isInf_T_1 = ~_mulRawFN_io_b_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _mulRawFN_io_b_out_isInf_T_2 = mulRawFN_io_b_isSpecial & _mulRawFN_io_b_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign mulRawFN_io_b_out_isInf = _mulRawFN_io_b_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _mulRawFN_io_b_out_sign_T = io_b_0[32]; // @[rawFloatFromRecFN.scala:59:25] assign mulRawFN_io_b_out_sign = _mulRawFN_io_b_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _mulRawFN_io_b_out_sExp_T = {1'h0, mulRawFN_io_b_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign mulRawFN_io_b_out_sExp = _mulRawFN_io_b_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _mulRawFN_io_b_out_sig_T = ~mulRawFN_io_b_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _mulRawFN_io_b_out_sig_T_1 = {1'h0, _mulRawFN_io_b_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _mulRawFN_io_b_out_sig_T_2 = io_b_0[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _mulRawFN_io_b_out_sig_T_3 = {_mulRawFN_io_b_out_sig_T_1, _mulRawFN_io_b_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign mulRawFN_io_b_out_sig = _mulRawFN_io_b_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44] MulRawFN_43 mulRawFN ( // @[MulRecFN.scala:113:26] .io_a_isNaN (mulRawFN_io_a_out_isNaN), // @[rawFloatFromRecFN.scala:55:23] .io_a_isInf (mulRawFN_io_a_out_isInf), // @[rawFloatFromRecFN.scala:55:23] .io_a_isZero (mulRawFN_io_a_out_isZero), // @[rawFloatFromRecFN.scala:55:23] .io_a_sign (mulRawFN_io_a_out_sign), // @[rawFloatFromRecFN.scala:55:23] .io_a_sExp (mulRawFN_io_a_out_sExp), // @[rawFloatFromRecFN.scala:55:23] .io_a_sig (mulRawFN_io_a_out_sig), // @[rawFloatFromRecFN.scala:55:23] .io_b_isNaN (mulRawFN_io_b_out_isNaN), // @[rawFloatFromRecFN.scala:55:23] .io_b_isInf (mulRawFN_io_b_out_isInf), // @[rawFloatFromRecFN.scala:55:23] .io_b_isZero (mulRawFN_io_b_out_isZero), // @[rawFloatFromRecFN.scala:55:23] .io_b_sign (mulRawFN_io_b_out_sign), // @[rawFloatFromRecFN.scala:55:23] .io_b_sExp (mulRawFN_io_b_out_sExp), // @[rawFloatFromRecFN.scala:55:23] .io_b_sig (mulRawFN_io_b_out_sig), // @[rawFloatFromRecFN.scala:55:23] .io_invalidExc (_mulRawFN_io_invalidExc), .io_rawOut_isNaN (_mulRawFN_io_rawOut_isNaN), .io_rawOut_isInf (_mulRawFN_io_rawOut_isInf), .io_rawOut_isZero (_mulRawFN_io_rawOut_isZero), .io_rawOut_sign (_mulRawFN_io_rawOut_sign), .io_rawOut_sExp (_mulRawFN_io_rawOut_sExp), .io_rawOut_sig (_mulRawFN_io_rawOut_sig) ); // @[MulRecFN.scala:113:26] RoundRawFNToRecFN_e8_s24_117 roundRawFNToRecFN ( // @[MulRecFN.scala:121:15] .io_invalidExc (_mulRawFN_io_invalidExc), // @[MulRecFN.scala:113:26] .io_in_isNaN (_mulRawFN_io_rawOut_isNaN), // @[MulRecFN.scala:113:26] .io_in_isInf (_mulRawFN_io_rawOut_isInf), // @[MulRecFN.scala:113:26] .io_in_isZero (_mulRawFN_io_rawOut_isZero), // @[MulRecFN.scala:113:26] .io_in_sign (_mulRawFN_io_rawOut_sign), // @[MulRecFN.scala:113:26] .io_in_sExp (_mulRawFN_io_rawOut_sExp), // @[MulRecFN.scala:113:26] .io_in_sig (_mulRawFN_io_rawOut_sig), // @[MulRecFN.scala:113:26] .io_out (io_out_0), .io_exceptionFlags (io_exceptionFlags) ); // @[MulRecFN.scala:121:15] assign io_out = io_out_0; // @[MulRecFN.scala:100:7] endmodule

Generate the Verilog code corresponding to the following Chisel files. File RegMapFIFO.scala: package sifive.blocks.util import chisel3._ import chisel3.util._ import freechips.rocketchip.regmapper._ // MSB indicates full status object NonBlockingEnqueue { def apply(enq: DecoupledIO[UInt], regWidth: Int = 32): Seq[RegField] = { val enqWidth = enq.bits.getWidth val quash = Wire(Bool()) require(enqWidth > 0) require(regWidth > enqWidth) Seq( RegField(enqWidth, RegReadFn(0.U), RegWriteFn((valid, data) => { enq.valid := valid && !quash enq.bits := data true.B }), RegFieldDesc("data", "Transmit data", access=RegFieldAccessType.W)), RegField(regWidth - enqWidth - 1), RegField(1, !enq.ready, RegWriteFn((valid, data) => { quash := valid && data(0) true.B }), RegFieldDesc("full", "Transmit FIFO full", access=RegFieldAccessType.R, volatile=true))) } } // MSB indicates empty status object NonBlockingDequeue { def apply(deq: DecoupledIO[UInt], regWidth: Int = 32): Seq[RegField] = { val deqWidth = deq.bits.getWidth require(deqWidth > 0) require(regWidth > deqWidth) Seq( RegField.r(deqWidth, RegReadFn(ready => { deq.ready := ready (true.B, deq.bits) }), RegFieldDesc("data", "Receive data", volatile=true)), RegField(regWidth - deqWidth - 1), RegField.r(1, !deq.valid, RegFieldDesc("empty", "Receive FIFO empty", volatile=true))) } } /* Copyright 2016 SiFive, Inc. Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License. */ File Buffer.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.diplomacy.BufferParams class TLBufferNode ( a: BufferParams, b: BufferParams, c: BufferParams, d: BufferParams, e: BufferParams)(implicit valName: ValName) extends TLAdapterNode( clientFn = { p => p.v1copy(minLatency = p.minLatency + b.latency + c.latency) }, managerFn = { p => p.v1copy(minLatency = p.minLatency + a.latency + d.latency) } ) { override lazy val nodedebugstring = s"a:${a.toString}, b:${b.toString}, c:${c.toString}, d:${d.toString}, e:${e.toString}" override def circuitIdentity = List(a,b,c,d,e).forall(_ == BufferParams.none) } class TLBuffer( a: BufferParams, b: BufferParams, c: BufferParams, d: BufferParams, e: BufferParams)(implicit p: Parameters) extends LazyModule { def this(ace: BufferParams, bd: BufferParams)(implicit p: Parameters) = this(ace, bd, ace, bd, ace) def this(abcde: BufferParams)(implicit p: Parameters) = this(abcde, abcde) def this()(implicit p: Parameters) = this(BufferParams.default) val node = new TLBufferNode(a, b, c, d, e) lazy val module = new Impl class Impl extends LazyModuleImp(this) { def headBundle = node.out.head._2.bundle override def desiredName = (Seq("TLBuffer") ++ node.out.headOption.map(_._2.bundle.shortName)).mkString("_") (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out.a <> a(in .a) in .d <> d(out.d) if (edgeOut.manager.anySupportAcquireB && edgeOut.client.anySupportProbe) { in .b <> b(out.b) out.c <> c(in .c) out.e <> e(in .e) } else { in.b.valid := false.B in.c.ready := true.B in.e.ready := true.B out.b.ready := true.B out.c.valid := false.B out.e.valid := false.B } } } } object TLBuffer { def apply() (implicit p: Parameters): TLNode = apply(BufferParams.default) def apply(abcde: BufferParams) (implicit p: Parameters): TLNode = apply(abcde, abcde) def apply(ace: BufferParams, bd: BufferParams)(implicit p: Parameters): TLNode = apply(ace, bd, ace, bd, ace) def apply( a: BufferParams, b: BufferParams, c: BufferParams, d: BufferParams, e: BufferParams)(implicit p: Parameters): TLNode = { val buffer = LazyModule(new TLBuffer(a, b, c, d, e)) buffer.node } def chain(depth: Int, name: Option[String] = None)(implicit p: Parameters): Seq[TLNode] = { val buffers = Seq.fill(depth) { LazyModule(new TLBuffer()) } name.foreach { n => buffers.zipWithIndex.foreach { case (b, i) => b.suggestName(s"${n}_${i}") } } buffers.map(_.node) } def chainNode(depth: Int, name: Option[String] = None)(implicit p: Parameters): TLNode = { chain(depth, name) .reduceLeftOption(_ :*=* _) .getOrElse(TLNameNode("no_buffer")) } } File UART.scala: package sifive.blocks.devices.uart import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.{Field, Parameters} import freechips.rocketchip.diplomacy._ import freechips.rocketchip.interrupts._ import freechips.rocketchip.prci._ import freechips.rocketchip.regmapper._ import freechips.rocketchip.subsystem._ import freechips.rocketchip.tilelink._ import freechips.rocketchip.devices.tilelink._ import freechips.rocketchip.util._ import sifive.blocks.util._ /** UART parameters * * @param address uart device TL base address * @param dataBits number of bits in data frame * @param stopBits number of stop bits * @param divisorBits width of baud rate divisor * @param oversample constructs the times of sampling for every data bit * @param nSamples number of reserved Rx sampling result for decide one data bit * @param nTxEntries number of entries in fifo between TL bus and Tx * @param nRxEntries number of entries in fifo between TL bus and Rx * @param includeFourWire additional CTS/RTS ports for flow control * @param includeParity parity support * @param includeIndependentParity Tx and Rx have opposite parity modes * @param initBaudRate initial baud rate * * @note baud rate divisor = clk frequency / baud rate. It means the number of clk period for one data bit. * Calculated in [[UARTAttachParams.attachTo()]] * * @example To configure a 8N1 UART with features below: * {{{ * 8 entries of Tx and Rx fifo * Baud rate = 115200 * Rx samples each data bit 16 times * Uses 3 sample result for each data bit * }}} * Set the stopBits as below and keep the other parameter unchanged * {{{ * stopBits = 1 * }}} * */ case class UARTParams( address: BigInt, dataBits: Int = 8, stopBits: Int = 2, divisorBits: Int = 16, oversample: Int = 4, nSamples: Int = 3, nTxEntries: Int = 8, nRxEntries: Int = 8, includeFourWire: Boolean = false, includeParity: Boolean = false, includeIndependentParity: Boolean = false, // Tx and Rx have opposite parity modes initBaudRate: BigInt = BigInt(115200), ) extends DeviceParams { def oversampleFactor = 1 << oversample require(divisorBits > oversample) require(oversampleFactor > nSamples) require((dataBits == 8) || (dataBits == 9)) } class UARTPortIO(val c: UARTParams) extends Bundle { val txd = Output(Bool()) val rxd = Input(Bool()) val cts_n = c.includeFourWire.option(Input(Bool())) val rts_n = c.includeFourWire.option(Output(Bool())) } class UARTInterrupts extends Bundle { val rxwm = Bool() val txwm = Bool() } //abstract class UART(busWidthBytes: Int, val c: UARTParams, divisorInit: Int = 0) /** UART Module organizes Tx and Rx module with fifo and generates control signals for them according to CSRs and UART parameters. * * ==Component== * - Tx * - Tx fifo * - Rx * - Rx fifo * - TL bus to soc * * ==IO== * [[UARTPortIO]] * * ==Datapass== * {{{ * TL bus -> Tx fifo -> Tx * TL bus <- Rx fifo <- Rx * }}} * * @param divisorInit: number of clk period for one data bit */ class UART(busWidthBytes: Int, val c: UARTParams, divisorInit: Int = 0) (implicit p: Parameters) extends IORegisterRouter( RegisterRouterParams( name = "serial", compat = Seq("sifive,uart0"), base = c.address, beatBytes = busWidthBytes), new UARTPortIO(c)) //with HasInterruptSources { with HasInterruptSources with HasTLControlRegMap { def nInterrupts = 1 + c.includeParity.toInt ResourceBinding { Resource(ResourceAnchors.aliases, "uart").bind(ResourceAlias(device.label)) } require(divisorInit != 0, "UART divisor wasn't initialized during instantiation") require(divisorInit >> c.divisorBits == 0, s"UART divisor reg (width $c.divisorBits) not wide enough to hold $divisorInit") lazy val module = new LazyModuleImp(this) { val txm = Module(new UARTTx(c)) val txq = Module(new Queue(UInt(c.dataBits.W), c.nTxEntries)) val rxm = Module(new UARTRx(c)) val rxq = Module(new Queue(UInt(c.dataBits.W), c.nRxEntries)) val div = RegInit(divisorInit.U(c.divisorBits.W)) private val stopCountBits = log2Up(c.stopBits) private val txCountBits = log2Floor(c.nTxEntries) + 1 private val rxCountBits = log2Floor(c.nRxEntries) + 1 val txen = RegInit(false.B) val rxen = RegInit(false.B) val enwire4 = RegInit(false.B) val invpol = RegInit(false.B) val enparity = RegInit(false.B) val parity = RegInit(false.B) // Odd parity - 1 , Even parity - 0 val errorparity = RegInit(false.B) val errie = RegInit(false.B) val txwm = RegInit(0.U(txCountBits.W)) val rxwm = RegInit(0.U(rxCountBits.W)) val nstop = RegInit(0.U(stopCountBits.W)) val data8or9 = RegInit(true.B) if (c.includeFourWire){ txm.io.en := txen && (!port.cts_n.get || !enwire4) txm.io.cts_n.get := port.cts_n.get } else txm.io.en := txen txm.io.in <> txq.io.deq txm.io.div := div txm.io.nstop := nstop port.txd := txm.io.out if (c.dataBits == 9) { txm.io.data8or9.get := data8or9 rxm.io.data8or9.get := data8or9 } rxm.io.en := rxen rxm.io.in := port.rxd rxq.io.enq.valid := rxm.io.out.valid rxq.io.enq.bits := rxm.io.out.bits rxm.io.div := div val tx_busy = (txm.io.tx_busy || txq.io.count.orR) && txen port.rts_n.foreach { r => r := Mux(enwire4, !(rxq.io.count < c.nRxEntries.U), tx_busy ^ invpol) } if (c.includeParity) { txm.io.enparity.get := enparity txm.io.parity.get := parity rxm.io.parity.get := parity ^ c.includeIndependentParity.B // independent parity on tx and rx rxm.io.enparity.get := enparity errorparity := rxm.io.errorparity.get || errorparity interrupts(1) := errorparity && errie } val ie = RegInit(0.U.asTypeOf(new UARTInterrupts())) val ip = Wire(new UARTInterrupts) ip.txwm := (txq.io.count < txwm) ip.rxwm := (rxq.io.count > rxwm) interrupts(0) := (ip.txwm && ie.txwm) || (ip.rxwm && ie.rxwm) val mapping = Seq( UARTCtrlRegs.txfifo -> RegFieldGroup("txdata",Some("Transmit data"), NonBlockingEnqueue(txq.io.enq)), UARTCtrlRegs.rxfifo -> RegFieldGroup("rxdata",Some("Receive data"), NonBlockingDequeue(rxq.io.deq)), UARTCtrlRegs.txctrl -> RegFieldGroup("txctrl",Some("Serial transmit control"),Seq( RegField(1, txen, RegFieldDesc("txen","Transmit enable", reset=Some(0))), RegField(stopCountBits, nstop, RegFieldDesc("nstop","Number of stop bits", reset=Some(0))))), UARTCtrlRegs.rxctrl -> Seq(RegField(1, rxen, RegFieldDesc("rxen","Receive enable", reset=Some(0)))), UARTCtrlRegs.txmark -> Seq(RegField(txCountBits, txwm, RegFieldDesc("txcnt","Transmit watermark level", reset=Some(0)))), UARTCtrlRegs.rxmark -> Seq(RegField(rxCountBits, rxwm, RegFieldDesc("rxcnt","Receive watermark level", reset=Some(0)))), UARTCtrlRegs.ie -> RegFieldGroup("ie",Some("Serial interrupt enable"),Seq( RegField(1, ie.txwm, RegFieldDesc("txwm_ie","Transmit watermark interrupt enable", reset=Some(0))), RegField(1, ie.rxwm, RegFieldDesc("rxwm_ie","Receive watermark interrupt enable", reset=Some(0))))), UARTCtrlRegs.ip -> RegFieldGroup("ip",Some("Serial interrupt pending"),Seq( RegField.r(1, ip.txwm, RegFieldDesc("txwm_ip","Transmit watermark interrupt pending", volatile=true)), RegField.r(1, ip.rxwm, RegFieldDesc("rxwm_ip","Receive watermark interrupt pending", volatile=true)))), UARTCtrlRegs.div -> Seq( RegField(c.divisorBits, div, RegFieldDesc("div","Baud rate divisor",reset=Some(divisorInit)))) ) val optionalparity = if (c.includeParity) Seq( UARTCtrlRegs.parity -> RegFieldGroup("paritygenandcheck",Some("Odd/Even Parity Generation/Checking"),Seq( RegField(1, enparity, RegFieldDesc("enparity","Enable Parity Generation/Checking", reset=Some(0))), RegField(1, parity, RegFieldDesc("parity","Odd(1)/Even(0) Parity", reset=Some(0))), RegField(1, errorparity, RegFieldDesc("errorparity","Parity Status Sticky Bit", reset=Some(0))), RegField(1, errie, RegFieldDesc("errie","Interrupt on error in parity enable", reset=Some(0)))))) else Nil val optionalwire4 = if (c.includeFourWire) Seq( UARTCtrlRegs.wire4 -> RegFieldGroup("wire4",Some("Configure Clear-to-send / Request-to-send ports / RS-485"),Seq( RegField(1, enwire4, RegFieldDesc("enwire4","Enable CTS/RTS(1) or RS-485(0)", reset=Some(0))), RegField(1, invpol, RegFieldDesc("invpol","Invert polarity of RTS in RS-485 mode", reset=Some(0))) ))) else Nil val optional8or9 = if (c.dataBits == 9) Seq( UARTCtrlRegs.either8or9 -> RegFieldGroup("ConfigurableDataBits",Some("Configure number of data bits to be transmitted"),Seq( RegField(1, data8or9, RegFieldDesc("databits8or9","Data Bits to be 8(1) or 9(0)", reset=Some(1)))))) else Nil regmap(mapping ++ optionalparity ++ optionalwire4 ++ optional8or9:_*) } } class TLUART(busWidthBytes: Int, params: UARTParams, divinit: Int)(implicit p: Parameters) extends UART(busWidthBytes, params, divinit) with HasTLControlRegMap case class UARTLocated(loc: HierarchicalLocation) extends Field[Seq[UARTAttachParams]](Nil) case class UARTAttachParams( device: UARTParams, controlWhere: TLBusWrapperLocation = PBUS, blockerAddr: Option[BigInt] = None, controlXType: ClockCrossingType = NoCrossing, intXType: ClockCrossingType = NoCrossing) extends DeviceAttachParams { def attachTo(where: Attachable)(implicit p: Parameters): TLUART = where { val name = s"uart_${UART.nextId()}" val tlbus = where.locateTLBusWrapper(controlWhere) val divinit = (tlbus.dtsFrequency.get / device.initBaudRate).toInt val uartClockDomainWrapper = LazyModule(new ClockSinkDomain(take = None, name = Some("TLUART"))) val uart = uartClockDomainWrapper { LazyModule(new TLUART(tlbus.beatBytes, device, divinit)) } uart.suggestName(name) tlbus.coupleTo(s"device_named_$name") { bus => val blockerOpt = blockerAddr.map { a => val blocker = LazyModule(new TLClockBlocker(BasicBusBlockerParams(a, tlbus.beatBytes, tlbus.beatBytes))) tlbus.coupleTo(s"bus_blocker_for_$name") { blocker.controlNode := TLFragmenter(tlbus, Some("UART_Blocker")) := _ } blocker } uartClockDomainWrapper.clockNode := (controlXType match { case _: SynchronousCrossing => tlbus.dtsClk.map(_.bind(uart.device)) tlbus.fixedClockNode case _: RationalCrossing => tlbus.clockNode case _: AsynchronousCrossing => val uartClockGroup = ClockGroup() uartClockGroup := where.allClockGroupsNode blockerOpt.map { _.clockNode := uartClockGroup } .getOrElse { uartClockGroup } }) (uart.controlXing(controlXType) := TLFragmenter(tlbus, Some("UART")) := blockerOpt.map { _.node := bus } .getOrElse { bus }) } (intXType match { case _: SynchronousCrossing => where.ibus.fromSync case _: RationalCrossing => where.ibus.fromRational case _: AsynchronousCrossing => where.ibus.fromAsync }) := uart.intXing(intXType) uart } } object UART { val nextId = { var i = -1; () => { i += 1; i} } def makePort(node: BundleBridgeSource[UARTPortIO], name: String)(implicit p: Parameters): ModuleValue[UARTPortIO] = { val uartNode = node.makeSink() InModuleBody { uartNode.makeIO()(ValName(name)) } } def tieoff(port: UARTPortIO) { port.rxd := 1.U if (port.c.includeFourWire) { port.cts_n.foreach { ct => ct := false.B } // active-low } } def loopback(port: UARTPortIO) { port.rxd := port.txd if (port.c.includeFourWire) { port.cts_n.get := port.rts_n.get } } } /* Copyright 2016 SiFive, Inc. Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License. */ File Crossing.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.interrupts import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.util.{SynchronizerShiftReg, AsyncResetReg} @deprecated("IntXing does not ensure interrupt source is glitch free. Use IntSyncSource and IntSyncSink", "rocket-chip 1.2") class IntXing(sync: Int = 3)(implicit p: Parameters) extends LazyModule { val intnode = IntAdapterNode() lazy val module = new Impl class Impl extends LazyModuleImp(this) { (intnode.in zip intnode.out) foreach { case ((in, _), (out, _)) => out := SynchronizerShiftReg(in, sync) } } } object IntSyncCrossingSource { def apply(alreadyRegistered: Boolean = false)(implicit p: Parameters) = { val intsource = LazyModule(new IntSyncCrossingSource(alreadyRegistered)) intsource.node } } class IntSyncCrossingSource(alreadyRegistered: Boolean = false)(implicit p: Parameters) extends LazyModule { val node = IntSyncSourceNode(alreadyRegistered) lazy val module = if (alreadyRegistered) (new ImplRegistered) else (new Impl) class Impl extends LazyModuleImp(this) { def outSize = node.out.headOption.map(_._1.sync.size).getOrElse(0) override def desiredName = s"IntSyncCrossingSource_n${node.out.size}x${outSize}" (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out.sync := AsyncResetReg(Cat(in.reverse)).asBools } } class ImplRegistered extends LazyRawModuleImp(this) { def outSize = node.out.headOption.map(_._1.sync.size).getOrElse(0) override def desiredName = s"IntSyncCrossingSource_n${node.out.size}x${outSize}_Registered" (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out.sync := in } } } object IntSyncCrossingSink { @deprecated("IntSyncCrossingSink which used the `sync` parameter to determine crossing type is deprecated. Use IntSyncAsyncCrossingSink, IntSyncRationalCrossingSink, or IntSyncSyncCrossingSink instead for > 1, 1, and 0 sync values respectively", "rocket-chip 1.2") def apply(sync: Int = 3)(implicit p: Parameters) = { val intsink = LazyModule(new IntSyncAsyncCrossingSink(sync)) intsink.node } } class IntSyncAsyncCrossingSink(sync: Int = 3)(implicit p: Parameters) extends LazyModule { val node = IntSyncSinkNode(sync) lazy val module = new Impl class Impl extends LazyModuleImp(this) { override def desiredName = s"IntSyncAsyncCrossingSink_n${node.out.size}x${node.out.head._1.size}" (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out := SynchronizerShiftReg(in.sync, sync) } } } object IntSyncAsyncCrossingSink { def apply(sync: Int = 3)(implicit p: Parameters) = { val intsink = LazyModule(new IntSyncAsyncCrossingSink(sync)) intsink.node } } class IntSyncSyncCrossingSink()(implicit p: Parameters) extends LazyModule { val node = IntSyncSinkNode(0) lazy val module = new Impl class Impl extends LazyRawModuleImp(this) { def outSize = node.out.headOption.map(_._1.size).getOrElse(0) override def desiredName = s"IntSyncSyncCrossingSink_n${node.out.size}x${outSize}" (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out := in.sync } } } object IntSyncSyncCrossingSink { def apply()(implicit p: Parameters) = { val intsink = LazyModule(new IntSyncSyncCrossingSink()) intsink.node } } class IntSyncRationalCrossingSink()(implicit p: Parameters) extends LazyModule { val node = IntSyncSinkNode(1) lazy val module = new Impl class Impl extends LazyModuleImp(this) { def outSize = node.out.headOption.map(_._1.size).getOrElse(0) override def desiredName = s"IntSyncRationalCrossingSink_n${node.out.size}x${outSize}" (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out := RegNext(in.sync) } } } object IntSyncRationalCrossingSink { def apply()(implicit p: Parameters) = { val intsink = LazyModule(new IntSyncRationalCrossingSink()) intsink.node } } File Nodes.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.nodes._ import freechips.rocketchip.util.{AsyncQueueParams,RationalDirection} case object TLMonitorBuilder extends Field[TLMonitorArgs => TLMonitorBase](args => new TLMonitor(args)) object TLImp extends NodeImp[TLMasterPortParameters, TLSlavePortParameters, TLEdgeOut, TLEdgeIn, TLBundle] { def edgeO(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeOut(pd, pu, p, sourceInfo) def edgeI(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeIn (pd, pu, p, sourceInfo) def bundleO(eo: TLEdgeOut) = TLBundle(eo.bundle) def bundleI(ei: TLEdgeIn) = TLBundle(ei.bundle) def render(ei: TLEdgeIn) = RenderedEdge(colour = "#000000" /* black */, label = (ei.manager.beatBytes * 8).toString) override def monitor(bundle: TLBundle, edge: TLEdgeIn): Unit = { val monitor = Module(edge.params(TLMonitorBuilder)(TLMonitorArgs(edge))) monitor.io.in := bundle } override def mixO(pd: TLMasterPortParameters, node: OutwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLMasterPortParameters = pd.v1copy(clients = pd.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }) override def mixI(pu: TLSlavePortParameters, node: InwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLSlavePortParameters = pu.v1copy(managers = pu.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }) } trait TLFormatNode extends FormatNode[TLEdgeIn, TLEdgeOut] case class TLClientNode(portParams: Seq[TLMasterPortParameters])(implicit valName: ValName) extends SourceNode(TLImp)(portParams) with TLFormatNode case class TLManagerNode(portParams: Seq[TLSlavePortParameters])(implicit valName: ValName) extends SinkNode(TLImp)(portParams) with TLFormatNode case class TLAdapterNode( clientFn: TLMasterPortParameters => TLMasterPortParameters = { s => s }, managerFn: TLSlavePortParameters => TLSlavePortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLImp)(clientFn, managerFn) with TLFormatNode case class TLJunctionNode( clientFn: Seq[TLMasterPortParameters] => Seq[TLMasterPortParameters], managerFn: Seq[TLSlavePortParameters] => Seq[TLSlavePortParameters])( implicit valName: ValName) extends JunctionNode(TLImp)(clientFn, managerFn) with TLFormatNode case class TLIdentityNode()(implicit valName: ValName) extends IdentityNode(TLImp)() with TLFormatNode object TLNameNode { def apply(name: ValName) = TLIdentityNode()(name) def apply(name: Option[String]): TLIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLIdentityNode = apply(Some(name)) } case class TLEphemeralNode()(implicit valName: ValName) extends EphemeralNode(TLImp)() object TLTempNode { def apply(): TLEphemeralNode = TLEphemeralNode()(ValName("temp")) } case class TLNexusNode( clientFn: Seq[TLMasterPortParameters] => TLMasterPortParameters, managerFn: Seq[TLSlavePortParameters] => TLSlavePortParameters)( implicit valName: ValName) extends NexusNode(TLImp)(clientFn, managerFn) with TLFormatNode abstract class TLCustomNode(implicit valName: ValName) extends CustomNode(TLImp) with TLFormatNode // Asynchronous crossings trait TLAsyncFormatNode extends FormatNode[TLAsyncEdgeParameters, TLAsyncEdgeParameters] object TLAsyncImp extends SimpleNodeImp[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncEdgeParameters, TLAsyncBundle] { def edge(pd: TLAsyncClientPortParameters, pu: TLAsyncManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLAsyncEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLAsyncEdgeParameters) = new TLAsyncBundle(e.bundle) def render(e: TLAsyncEdgeParameters) = RenderedEdge(colour = "#ff0000" /* red */, label = e.manager.async.depth.toString) override def mixO(pd: TLAsyncClientPortParameters, node: OutwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLAsyncManagerPortParameters, node: InwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLAsyncAdapterNode( clientFn: TLAsyncClientPortParameters => TLAsyncClientPortParameters = { s => s }, managerFn: TLAsyncManagerPortParameters => TLAsyncManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLAsyncImp)(clientFn, managerFn) with TLAsyncFormatNode case class TLAsyncIdentityNode()(implicit valName: ValName) extends IdentityNode(TLAsyncImp)() with TLAsyncFormatNode object TLAsyncNameNode { def apply(name: ValName) = TLAsyncIdentityNode()(name) def apply(name: Option[String]): TLAsyncIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLAsyncIdentityNode = apply(Some(name)) } case class TLAsyncSourceNode(sync: Option[Int])(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLAsyncImp)( dFn = { p => TLAsyncClientPortParameters(p) }, uFn = { p => p.base.v1copy(minLatency = p.base.minLatency + sync.getOrElse(p.async.sync)) }) with FormatNode[TLEdgeIn, TLAsyncEdgeParameters] // discard cycles in other clock domain case class TLAsyncSinkNode(async: AsyncQueueParams)(implicit valName: ValName) extends MixedAdapterNode(TLAsyncImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = p.base.minLatency + async.sync) }, uFn = { p => TLAsyncManagerPortParameters(async, p) }) with FormatNode[TLAsyncEdgeParameters, TLEdgeOut] // Rationally related crossings trait TLRationalFormatNode extends FormatNode[TLRationalEdgeParameters, TLRationalEdgeParameters] object TLRationalImp extends SimpleNodeImp[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalEdgeParameters, TLRationalBundle] { def edge(pd: TLRationalClientPortParameters, pu: TLRationalManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLRationalEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLRationalEdgeParameters) = new TLRationalBundle(e.bundle) def render(e: TLRationalEdgeParameters) = RenderedEdge(colour = "#00ff00" /* green */) override def mixO(pd: TLRationalClientPortParameters, node: OutwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLRationalManagerPortParameters, node: InwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLRationalAdapterNode( clientFn: TLRationalClientPortParameters => TLRationalClientPortParameters = { s => s }, managerFn: TLRationalManagerPortParameters => TLRationalManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLRationalImp)(clientFn, managerFn) with TLRationalFormatNode case class TLRationalIdentityNode()(implicit valName: ValName) extends IdentityNode(TLRationalImp)() with TLRationalFormatNode object TLRationalNameNode { def apply(name: ValName) = TLRationalIdentityNode()(name) def apply(name: Option[String]): TLRationalIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLRationalIdentityNode = apply(Some(name)) } case class TLRationalSourceNode()(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLRationalImp)( dFn = { p => TLRationalClientPortParameters(p) }, uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLRationalEdgeParameters] // discard cycles from other clock domain case class TLRationalSinkNode(direction: RationalDirection)(implicit valName: ValName) extends MixedAdapterNode(TLRationalImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = 1) }, uFn = { p => TLRationalManagerPortParameters(direction, p) }) with FormatNode[TLRationalEdgeParameters, TLEdgeOut] // Credited version of TileLink channels trait TLCreditedFormatNode extends FormatNode[TLCreditedEdgeParameters, TLCreditedEdgeParameters] object TLCreditedImp extends SimpleNodeImp[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedEdgeParameters, TLCreditedBundle] { def edge(pd: TLCreditedClientPortParameters, pu: TLCreditedManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLCreditedEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLCreditedEdgeParameters) = new TLCreditedBundle(e.bundle) def render(e: TLCreditedEdgeParameters) = RenderedEdge(colour = "#ffff00" /* yellow */, e.delay.toString) override def mixO(pd: TLCreditedClientPortParameters, node: OutwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLCreditedManagerPortParameters, node: InwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLCreditedAdapterNode( clientFn: TLCreditedClientPortParameters => TLCreditedClientPortParameters = { s => s }, managerFn: TLCreditedManagerPortParameters => TLCreditedManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLCreditedImp)(clientFn, managerFn) with TLCreditedFormatNode case class TLCreditedIdentityNode()(implicit valName: ValName) extends IdentityNode(TLCreditedImp)() with TLCreditedFormatNode object TLCreditedNameNode { def apply(name: ValName) = TLCreditedIdentityNode()(name) def apply(name: Option[String]): TLCreditedIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLCreditedIdentityNode = apply(Some(name)) } case class TLCreditedSourceNode(delay: TLCreditedDelay)(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLCreditedImp)( dFn = { p => TLCreditedClientPortParameters(delay, p) }, uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLCreditedEdgeParameters] // discard cycles from other clock domain case class TLCreditedSinkNode(delay: TLCreditedDelay)(implicit valName: ValName) extends MixedAdapterNode(TLCreditedImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = 1) }, uFn = { p => TLCreditedManagerPortParameters(delay, p) }) with FormatNode[TLCreditedEdgeParameters, TLEdgeOut] File RegisterRouter.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.nodes._ import freechips.rocketchip.diplomacy.{AddressSet, TransferSizes} import freechips.rocketchip.resources.{Device, Resource, ResourceBindings} import freechips.rocketchip.prci.{NoCrossing} import freechips.rocketchip.regmapper.{RegField, RegMapper, RegMapperParams, RegMapperInput, RegisterRouter} import freechips.rocketchip.util.{BundleField, ControlKey, ElaborationArtefacts, GenRegDescsAnno} import scala.math.min class TLRegisterRouterExtraBundle(val sourceBits: Int, val sizeBits: Int) extends Bundle { val source = UInt((sourceBits max 1).W) val size = UInt((sizeBits max 1).W) } case object TLRegisterRouterExtra extends ControlKey[TLRegisterRouterExtraBundle]("tlrr_extra") case class TLRegisterRouterExtraField(sourceBits: Int, sizeBits: Int) extends BundleField[TLRegisterRouterExtraBundle](TLRegisterRouterExtra, Output(new TLRegisterRouterExtraBundle(sourceBits, sizeBits)), x => { x.size := 0.U x.source := 0.U }) /** TLRegisterNode is a specialized TL SinkNode that encapsulates MMIO registers. * It provides functionality for describing and outputting metdata about the registers in several formats. * It also provides a concrete implementation of a regmap function that will be used * to wire a map of internal registers associated with this node to the node's interconnect port. */ case class TLRegisterNode( address: Seq[AddressSet], device: Device, deviceKey: String = "reg/control", concurrency: Int = 0, beatBytes: Int = 4, undefZero: Boolean = true, executable: Boolean = false)( implicit valName: ValName) extends SinkNode(TLImp)(Seq(TLSlavePortParameters.v1( Seq(TLSlaveParameters.v1( address = address, resources = Seq(Resource(device, deviceKey)), executable = executable, supportsGet = TransferSizes(1, beatBytes), supportsPutPartial = TransferSizes(1, beatBytes), supportsPutFull = TransferSizes(1, beatBytes), fifoId = Some(0))), // requests are handled in order beatBytes = beatBytes, minLatency = min(concurrency, 1)))) with TLFormatNode // the Queue adds at most one cycle { val size = 1 << log2Ceil(1 + address.map(_.max).max - address.map(_.base).min) require (size >= beatBytes) address.foreach { case a => require (a.widen(size-1).base == address.head.widen(size-1).base, s"TLRegisterNode addresses (${address}) must be aligned to its size ${size}") } // Calling this method causes the matching TL2 bundle to be // configured to route all requests to the listed RegFields. def regmap(mapping: RegField.Map*) = { val (bundleIn, edge) = this.in(0) val a = bundleIn.a val d = bundleIn.d val fields = TLRegisterRouterExtraField(edge.bundle.sourceBits, edge.bundle.sizeBits) +: a.bits.params.echoFields val params = RegMapperParams(log2Up(size/beatBytes), beatBytes, fields) val in = Wire(Decoupled(new RegMapperInput(params))) in.bits.read := a.bits.opcode === TLMessages.Get in.bits.index := edge.addr_hi(a.bits) in.bits.data := a.bits.data in.bits.mask := a.bits.mask Connectable.waiveUnmatched(in.bits.extra, a.bits.echo) match { case (lhs, rhs) => lhs :<= rhs } val a_extra = in.bits.extra(TLRegisterRouterExtra) a_extra.source := a.bits.source a_extra.size := a.bits.size // Invoke the register map builder val out = RegMapper(beatBytes, concurrency, undefZero, in, mapping:_*) // No flow control needed in.valid := a.valid a.ready := in.ready d.valid := out.valid out.ready := d.ready // We must restore the size to enable width adapters to work val d_extra = out.bits.extra(TLRegisterRouterExtra) d.bits := edge.AccessAck(toSource = d_extra.source, lgSize = d_extra.size) // avoid a Mux on the data bus by manually overriding two fields d.bits.data := out.bits.data Connectable.waiveUnmatched(d.bits.echo, out.bits.extra) match { case (lhs, rhs) => lhs :<= rhs } d.bits.opcode := Mux(out.bits.read, TLMessages.AccessAckData, TLMessages.AccessAck) // Tie off unused channels bundleIn.b.valid := false.B bundleIn.c.ready := true.B bundleIn.e.ready := true.B genRegDescsJson(mapping:_*) } def genRegDescsJson(mapping: RegField.Map*): Unit = { // Dump out the register map for documentation purposes. val base = address.head.base val baseHex = s"0x${base.toInt.toHexString}" val name = s"${device.describe(ResourceBindings()).name}.At${baseHex}" val json = GenRegDescsAnno.serialize(base, name, mapping:_*) var suffix = 0 while( ElaborationArtefacts.contains(s"${baseHex}.${suffix}.regmap.json")) { suffix = suffix + 1 } ElaborationArtefacts.add(s"${baseHex}.${suffix}.regmap.json", json) val module = Module.currentModule.get.asInstanceOf[RawModule] GenRegDescsAnno.anno( module, base, mapping:_*) } } /** Mix HasTLControlRegMap into any subclass of RegisterRouter to gain helper functions for attaching a device control register map to TileLink. * - The intended use case is that controlNode will diplomatically publish a SW-visible device's memory-mapped control registers. * - Use the clock crossing helper controlXing to externally connect controlNode to a TileLink interconnect. * - Use the mapping helper function regmap to internally fill out the space of device control registers. */ trait HasTLControlRegMap { this: RegisterRouter => protected val controlNode = TLRegisterNode( address = address, device = device, deviceKey = "reg/control", concurrency = concurrency, beatBytes = beatBytes, undefZero = undefZero, executable = executable) // Externally, this helper should be used to connect the register control port to a bus val controlXing: TLInwardClockCrossingHelper = this.crossIn(controlNode) // Backwards-compatibility default node accessor with no clock crossing lazy val node: TLInwardNode = controlXing(NoCrossing) // Internally, this function should be used to populate the control port with registers protected def regmap(mapping: RegField.Map*): Unit = { controlNode.regmap(mapping:_*) } } File MuxLiteral.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util.log2Ceil import scala.reflect.ClassTag /* MuxLiteral creates a lookup table from a key to a list of values. * Unlike MuxLookup, the table keys must be exclusive literals. */ object MuxLiteral { def apply[T <: Data:ClassTag](index: UInt, default: T, first: (UInt, T), rest: (UInt, T)*): T = apply(index, default, first :: rest.toList) def apply[T <: Data:ClassTag](index: UInt, default: T, cases: Seq[(UInt, T)]): T = MuxTable(index, default, cases.map { case (k, v) => (k.litValue, v) }) } object MuxSeq { def apply[T <: Data:ClassTag](index: UInt, default: T, first: T, rest: T*): T = apply(index, default, first :: rest.toList) def apply[T <: Data:ClassTag](index: UInt, default: T, cases: Seq[T]): T = MuxTable(index, default, cases.zipWithIndex.map { case (v, i) => (BigInt(i), v) }) } object MuxTable { def apply[T <: Data:ClassTag](index: UInt, default: T, first: (BigInt, T), rest: (BigInt, T)*): T = apply(index, default, first :: rest.toList) def apply[T <: Data:ClassTag](index: UInt, default: T, cases: Seq[(BigInt, T)]): T = { /* All keys must be >= 0 and distinct */ cases.foreach { case (k, _) => require (k >= 0) } require (cases.map(_._1).distinct.size == cases.size) /* Filter out any cases identical to the default */ val simple = cases.filter { case (k, v) => !default.isLit || !v.isLit || v.litValue != default.litValue } val maxKey = (BigInt(0) +: simple.map(_._1)).max val endIndex = BigInt(1) << log2Ceil(maxKey+1) if (simple.isEmpty) { default } else if (endIndex <= 2*simple.size) { /* The dense encoding case uses a Vec */ val table = Array.fill(endIndex.toInt) { default } simple.foreach { case (k, v) => table(k.toInt) = v } Mux(index >= endIndex.U, default, VecInit(table)(index)) } else { /* The sparse encoding case uses switch */ val out = WireDefault(default) simple.foldLeft(new chisel3.util.SwitchContext(index, None, Set.empty)) { case (acc, (k, v)) => acc.is (k.U) { out := v } } out } } } File LazyModuleImp.scala: package org.chipsalliance.diplomacy.lazymodule import chisel3.{withClockAndReset, Module, RawModule, Reset, _} import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo} import firrtl.passes.InlineAnnotation import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.nodes.Dangle import scala.collection.immutable.SortedMap /** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]]. * * This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy. */ sealed trait LazyModuleImpLike extends RawModule { /** [[LazyModule]] that contains this instance. */ val wrapper: LazyModule /** IOs that will be automatically "punched" for this instance. */ val auto: AutoBundle /** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */ protected[diplomacy] val dangles: Seq[Dangle] // [[wrapper.module]] had better not be accessed while LazyModules are still being built! require( LazyModule.scope.isEmpty, s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}" ) /** Set module name. Defaults to the containing LazyModule's desiredName. */ override def desiredName: String = wrapper.desiredName suggestName(wrapper.suggestedName) /** [[Parameters]] for chisel [[Module]]s. */ implicit val p: Parameters = wrapper.p /** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and * submodules. */ protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = { // 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]], // 2. return [[Dangle]]s from each module. val childDangles = wrapper.children.reverse.flatMap { c => implicit val sourceInfo: SourceInfo = c.info c.cloneProto.map { cp => // If the child is a clone, then recursively set cloneProto of its children as well def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = { require(bases.size == clones.size) (bases.zip(clones)).map { case (l, r) => require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}") l.cloneProto = Some(r) assignCloneProtos(l.children, r.children) } } assignCloneProtos(c.children, cp.children) // Clone the child module as a record, and get its [[AutoBundle]] val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName) val clonedAuto = clone("auto").asInstanceOf[AutoBundle] // Get the empty [[Dangle]]'s of the cloned child val rawDangles = c.cloneDangles() require(rawDangles.size == clonedAuto.elements.size) // Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) } dangles }.getOrElse { // For non-clones, instantiate the child module val mod = try { Module(c.module) } catch { case e: ChiselException => { println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}") throw e } } mod.dangles } } // Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]]. // This will result in a sequence of [[Dangle]] from these [[BaseNode]]s. val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate()) // Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]] val allDangles = nodeDangles ++ childDangles // Group [[allDangles]] by their [[source]]. val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*) // For each [[source]] set of [[Dangle]]s of size 2, ensure that these // can be connected as a source-sink pair (have opposite flipped value). // Make the connection and mark them as [[done]]. val done = Set() ++ pairing.values.filter(_.size == 2).map { case Seq(a, b) => require(a.flipped != b.flipped) // @todo <> in chisel3 makes directionless connection. if (a.flipped) { a.data <> b.data } else { b.data <> a.data } a.source case _ => None } // Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module. val forward = allDangles.filter(d => !done(d.source)) // Generate [[AutoBundle]] IO from [[forward]]. val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*)) // Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]] val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) => if (d.flipped) { d.data <> io } else { io <> d.data } d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name) } // Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]]. wrapper.inModuleBody.reverse.foreach { _() } if (wrapper.shouldBeInlined) { chisel3.experimental.annotate(new ChiselAnnotation { def toFirrtl = InlineAnnotation(toNamed) }) } // Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]]. (auto, dangles) } } /** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike { /** Instantiate hardware of this `Module`. */ val (auto, dangles) = instantiate() } /** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike { // These wires are the default clock+reset for all LazyModule children. // It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the // [[LazyRawModuleImp]] children. // Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly. /** drive clock explicitly. */ val childClock: Clock = Wire(Clock()) /** drive reset explicitly. */ val childReset: Reset = Wire(Reset()) // the default is that these are disabled childClock := false.B.asClock childReset := chisel3.DontCare def provideImplicitClockToLazyChildren: Boolean = false val (auto, dangles) = if (provideImplicitClockToLazyChildren) { withClockAndReset(childClock, childReset) { instantiate() } } else { instantiate() } } File MixedNode.scala: package org.chipsalliance.diplomacy.nodes import chisel3.{Data, DontCare, Wire} import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.{Field, Parameters} import org.chipsalliance.diplomacy.ValName import org.chipsalliance.diplomacy.sourceLine /** One side metadata of a [[Dangle]]. * * Describes one side of an edge going into or out of a [[BaseNode]]. * * @param serial * the global [[BaseNode.serial]] number of the [[BaseNode]] that this [[HalfEdge]] connects to. * @param index * the `index` in the [[BaseNode]]'s input or output port list that this [[HalfEdge]] belongs to. */ case class HalfEdge(serial: Int, index: Int) extends Ordered[HalfEdge] { import scala.math.Ordered.orderingToOrdered def compare(that: HalfEdge): Int = HalfEdge.unapply(this).compare(HalfEdge.unapply(that)) } /** [[Dangle]] captures the `IO` information of a [[LazyModule]] and which two [[BaseNode]]s the [[Edges]]/[[Bundle]] * connects. * * [[Dangle]]s are generated by [[BaseNode.instantiate]] using [[MixedNode.danglesOut]] and [[MixedNode.danglesIn]] , * [[LazyModuleImp.instantiate]] connects those that go to internal or explicit IO connections in a [[LazyModule]]. * * @param source * the source [[HalfEdge]] of this [[Dangle]], which captures the source [[BaseNode]] and the port `index` within * that [[BaseNode]]. * @param sink * sink [[HalfEdge]] of this [[Dangle]], which captures the sink [[BaseNode]] and the port `index` within that * [[BaseNode]]. * @param flipped * flip or not in [[AutoBundle.makeElements]]. If true this corresponds to `danglesOut`, if false it corresponds to * `danglesIn`. * @param dataOpt * actual [[Data]] for the hardware connection. Can be empty if this belongs to a cloned module */ case class Dangle(source: HalfEdge, sink: HalfEdge, flipped: Boolean, name: String, dataOpt: Option[Data]) { def data = dataOpt.get } /** [[Edges]] is a collection of parameters describing the functionality and connection for an interface, which is often * derived from the interconnection protocol and can inform the parameterization of the hardware bundles that actually * implement the protocol. */ case class Edges[EI, EO](in: Seq[EI], out: Seq[EO]) /** A field available in [[Parameters]] used to determine whether [[InwardNodeImp.monitor]] will be called. */ case object MonitorsEnabled extends Field[Boolean](true) /** When rendering the edge in a graphical format, flip the order in which the edges' source and sink are presented. * * For example, when rendering graphML, yEd by default tries to put the source node vertically above the sink node, but * [[RenderFlipped]] inverts this relationship. When a particular [[LazyModule]] contains both source nodes and sink * nodes, flipping the rendering of one node's edge will usual produce a more concise visual layout for the * [[LazyModule]]. */ case object RenderFlipped extends Field[Boolean](false) /** The sealed node class in the package, all node are derived from it. * * @param inner * Sink interface implementation. * @param outer * Source interface implementation. * @param valName * val name of this node. * @tparam DI * Downward-flowing parameters received on the inner side of the node. It is usually a brunch of parameters * describing the protocol parameters from a source. For an [[InwardNode]], it is determined by the connected * [[OutwardNode]]. Since it can be connected to multiple sources, this parameter is always a Seq of source port * parameters. * @tparam UI * Upward-flowing parameters generated by the inner side of the node. It is usually a brunch of parameters describing * the protocol parameters of a sink. For an [[InwardNode]], it is determined itself. * @tparam EI * Edge Parameters describing a connection on the inner side of the node. It is usually a brunch of transfers * specified for a sink according to protocol. * @tparam BI * Bundle type used when connecting to the inner side of the node. It is a hardware interface of this sink interface. * It should extends from [[chisel3.Data]], which represents the real hardware. * @tparam DO * Downward-flowing parameters generated on the outer side of the node. It is usually a brunch of parameters * describing the protocol parameters of a source. For an [[OutwardNode]], it is determined itself. * @tparam UO * Upward-flowing parameters received by the outer side of the node. It is usually a brunch of parameters describing * the protocol parameters from a sink. For an [[OutwardNode]], it is determined by the connected [[InwardNode]]. * Since it can be connected to multiple sinks, this parameter is always a Seq of sink port parameters. * @tparam EO * Edge Parameters describing a connection on the outer side of the node. It is usually a brunch of transfers * specified for a source according to protocol. * @tparam BO * Bundle type used when connecting to the outer side of the node. It is a hardware interface of this source * interface. It should extends from [[chisel3.Data]], which represents the real hardware. * * @note * Call Graph of [[MixedNode]] * - line `─`: source is process by a function and generate pass to others * - Arrow `→`: target of arrow is generated by source * * {{{ * (from the other node) * ┌─────────────────────────────────────────────────────────[[InwardNode.uiParams]]─────────────┐ * ↓ │ * (binding node when elaboration) [[OutwardNode.uoParams]]────────────────────────[[MixedNode.mapParamsU]]→──────────┐ │ * [[InwardNode.accPI]] │ │ │ * │ │ (based on protocol) │ * │ │ [[MixedNode.inner.edgeI]] │ * │ │ ↓ │ * ↓ │ │ │ * (immobilize after elaboration) (inward port from [[OutwardNode]]) │ ↓ │ * [[InwardNode.iBindings]]──┐ [[MixedNode.iDirectPorts]]────────────────────→[[MixedNode.iPorts]] [[InwardNode.uiParams]] │ * │ │ ↑ │ │ │ * │ │ │ [[OutwardNode.doParams]] │ │ * │ │ │ (from the other node) │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * │ │ │ └────────┬──────────────┤ │ * │ │ │ │ │ │ * │ │ │ │ (based on protocol) │ * │ │ │ │ [[MixedNode.inner.edgeI]] │ * │ │ │ │ │ │ * │ │ (from the other node) │ ↓ │ * │ └───[[OutwardNode.oPortMapping]] [[OutwardNode.oStar]] │ [[MixedNode.edgesIn]]───┐ │ * │ ↑ ↑ │ │ ↓ │ * │ │ │ │ │ [[MixedNode.in]] │ * │ │ │ │ ↓ ↑ │ * │ (solve star connection) │ │ │ [[MixedNode.bundleIn]]──┘ │ * ├───[[MixedNode.resolveStar]]→─┼─────────────────────────────┤ └────────────────────────────────────┐ │ * │ │ │ [[MixedNode.bundleOut]]─┐ │ │ * │ │ │ ↑ ↓ │ │ * │ │ │ │ [[MixedNode.out]] │ │ * │ ↓ ↓ │ ↑ │ │ * │ ┌─────[[InwardNode.iPortMapping]] [[InwardNode.iStar]] [[MixedNode.edgesOut]]──┘ │ │ * │ │ (from the other node) ↑ │ │ * │ │ │ │ │ │ * │ │ │ [[MixedNode.outer.edgeO]] │ │ * │ │ │ (based on protocol) │ │ * │ │ │ │ │ │ * │ │ │ ┌────────────────────────────────────────┤ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * (immobilize after elaboration)│ ↓ │ │ │ │ * [[OutwardNode.oBindings]]─┘ [[MixedNode.oDirectPorts]]───→[[MixedNode.oPorts]] [[OutwardNode.doParams]] │ │ * ↑ (inward port from [[OutwardNode]]) │ │ │ │ * │ ┌─────────────────────────────────────────┤ │ │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * [[OutwardNode.accPO]] │ ↓ │ │ │ * (binding node when elaboration) │ [[InwardNode.diParams]]─────→[[MixedNode.mapParamsD]]────────────────────────────┘ │ │ * │ ↑ │ │ * │ └──────────────────────────────────────────────────────────────────────────────────────────┘ │ * └──────────────────────────────────────────────────────────────────────────────────────────────────────────┘ * }}} */ abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data]( val inner: InwardNodeImp[DI, UI, EI, BI], val outer: OutwardNodeImp[DO, UO, EO, BO] )( implicit valName: ValName) extends BaseNode with NodeHandle[DI, UI, EI, BI, DO, UO, EO, BO] with InwardNode[DI, UI, BI] with OutwardNode[DO, UO, BO] { // Generate a [[NodeHandle]] with inward and outward node are both this node. val inward = this val outward = this /** Debug info of nodes binding. */ def bindingInfo: String = s"""$iBindingInfo |$oBindingInfo |""".stripMargin /** Debug info of ports connecting. */ def connectedPortsInfo: String = s"""${oPorts.size} outward ports connected: [${oPorts.map(_._2.name).mkString(",")}] |${iPorts.size} inward ports connected: [${iPorts.map(_._2.name).mkString(",")}] |""".stripMargin /** Debug info of parameters propagations. */ def parametersInfo: String = s"""${doParams.size} downstream outward parameters: [${doParams.mkString(",")}] |${uoParams.size} upstream outward parameters: [${uoParams.mkString(",")}] |${diParams.size} downstream inward parameters: [${diParams.mkString(",")}] |${uiParams.size} upstream inward parameters: [${uiParams.mkString(",")}] |""".stripMargin /** For a given node, converts [[OutwardNode.accPO]] and [[InwardNode.accPI]] to [[MixedNode.oPortMapping]] and * [[MixedNode.iPortMapping]]. * * Given counts of known inward and outward binding and inward and outward star bindings, return the resolved inward * stars and outward stars. * * This method will also validate the arguments and throw a runtime error if the values are unsuitable for this type * of node. * * @param iKnown * Number of known-size ([[BIND_ONCE]]) input bindings. * @param oKnown * Number of known-size ([[BIND_ONCE]]) output bindings. * @param iStar * Number of unknown size ([[BIND_STAR]]) input bindings. * @param oStar * Number of unknown size ([[BIND_STAR]]) output bindings. * @return * A Tuple of the resolved number of input and output connections. */ protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStar: Int, oStar: Int): (Int, Int) /** Function to generate downward-flowing outward params from the downward-flowing input params and the current output * ports. * * @param n * The size of the output sequence to generate. * @param p * Sequence of downward-flowing input parameters of this node. * @return * A `n`-sized sequence of downward-flowing output edge parameters. */ protected[diplomacy] def mapParamsD(n: Int, p: Seq[DI]): Seq[DO] /** Function to generate upward-flowing input parameters from the upward-flowing output parameters [[uiParams]]. * * @param n * Size of the output sequence. * @param p * Upward-flowing output edge parameters. * @return * A n-sized sequence of upward-flowing input edge parameters. */ protected[diplomacy] def mapParamsU(n: Int, p: Seq[UO]): Seq[UI] /** @return * The sink cardinality of the node, the number of outputs bound with [[BIND_QUERY]] summed with inputs bound with * [[BIND_STAR]]. */ protected[diplomacy] lazy val sinkCard: Int = oBindings.count(_._3 == BIND_QUERY) + iBindings.count(_._3 == BIND_STAR) /** @return * The source cardinality of this node, the number of inputs bound with [[BIND_QUERY]] summed with the number of * output bindings bound with [[BIND_STAR]]. */ protected[diplomacy] lazy val sourceCard: Int = iBindings.count(_._3 == BIND_QUERY) + oBindings.count(_._3 == BIND_STAR) /** @return list of nodes involved in flex bindings with this node. */ protected[diplomacy] lazy val flexes: Seq[BaseNode] = oBindings.filter(_._3 == BIND_FLEX).map(_._2) ++ iBindings.filter(_._3 == BIND_FLEX).map(_._2) /** Resolves the flex to be either source or sink and returns the offset where the [[BIND_STAR]] operators begin * greedily taking up the remaining connections. * * @return * A value >= 0 if it is sink cardinality, a negative value for source cardinality. The magnitude of the return * value is not relevant. */ protected[diplomacy] lazy val flexOffset: Int = { /** Recursively performs a depth-first search of the [[flexes]], [[BaseNode]]s connected to this node with flex * operators. The algorithm bottoms out when we either get to a node we have already visited or when we get to a * connection that is not a flex and can set the direction for us. Otherwise, recurse by visiting the `flexes` of * each node in the current set and decide whether they should be added to the set or not. * * @return * the mapping of [[BaseNode]] indexed by their serial numbers. */ def DFS(v: BaseNode, visited: Map[Int, BaseNode]): Map[Int, BaseNode] = { if (visited.contains(v.serial) || !v.flexibleArityDirection) { visited } else { v.flexes.foldLeft(visited + (v.serial -> v))((sum, n) => DFS(n, sum)) } } /** Determine which [[BaseNode]] are involved in resolving the flex connections to/from this node. * * @example * {{{ * a :*=* b :*=* c * d :*=* b * e :*=* f * }}} * * `flexSet` for `a`, `b`, `c`, or `d` will be `Set(a, b, c, d)` `flexSet` for `e` or `f` will be `Set(e,f)` */ val flexSet = DFS(this, Map()).values /** The total number of :*= operators where we're on the left. */ val allSink = flexSet.map(_.sinkCard).sum /** The total number of :=* operators used when we're on the right. */ val allSource = flexSet.map(_.sourceCard).sum require( allSink == 0 || allSource == 0, s"The nodes ${flexSet.map(_.name)} which are inter-connected by :*=* have ${allSink} :*= operators and ${allSource} :=* operators connected to them, making it impossible to determine cardinality inference direction." ) allSink - allSource } /** @return A value >= 0 if it is sink cardinality, a negative value for source cardinality. */ protected[diplomacy] def edgeArityDirection(n: BaseNode): Int = { if (flexibleArityDirection) flexOffset else if (n.flexibleArityDirection) n.flexOffset else 0 } /** For a node which is connected between two nodes, select the one that will influence the direction of the flex * resolution. */ protected[diplomacy] def edgeAritySelect(n: BaseNode, l: => Int, r: => Int): Int = { val dir = edgeArityDirection(n) if (dir < 0) l else if (dir > 0) r else 1 } /** Ensure that the same node is not visited twice in resolving `:*=`, etc operators. */ private var starCycleGuard = false /** Resolve all the star operators into concrete indicies. As connections are being made, some may be "star" * connections which need to be resolved. In some way to determine how many actual edges they correspond to. We also * need to build up the ranges of edges which correspond to each binding operator, so that We can apply the correct * edge parameters and later build up correct bundle connections. * * [[oPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that oPort (binding * operator). [[iPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that iPort * (binding operator). [[oStar]]: `Int` the value to return for this node `N` for any `N :*= foo` or `N :*=* foo :*= * bar` [[iStar]]: `Int` the value to return for this node `N` for any `foo :=* N` or `bar :=* foo :*=* N` */ protected[diplomacy] lazy val ( oPortMapping: Seq[(Int, Int)], iPortMapping: Seq[(Int, Int)], oStar: Int, iStar: Int ) = { try { if (starCycleGuard) throw StarCycleException() starCycleGuard = true // For a given node N... // Number of foo :=* N // + Number of bar :=* foo :*=* N val oStars = oBindings.count { case (_, n, b, _, _) => b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) < 0) } // Number of N :*= foo // + Number of N :*=* foo :*= bar val iStars = iBindings.count { case (_, n, b, _, _) => b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) > 0) } // 1 for foo := N // + bar.iStar for bar :*= foo :*=* N // + foo.iStar for foo :*= N // + 0 for foo :=* N val oKnown = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, 0, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => 0 } }.sum // 1 for N := foo // + bar.oStar for N :*=* foo :=* bar // + foo.oStar for N :=* foo // + 0 for N :*= foo val iKnown = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, 0) case BIND_QUERY => n.oStar case BIND_STAR => 0 } }.sum // Resolve star depends on the node subclass to implement the algorithm for this. val (iStar, oStar) = resolveStar(iKnown, oKnown, iStars, oStars) // Cumulative list of resolved outward binding range starting points val oSum = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, oStar, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => oStar } }.scanLeft(0)(_ + _) // Cumulative list of resolved inward binding range starting points val iSum = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, iStar) case BIND_QUERY => n.oStar case BIND_STAR => iStar } }.scanLeft(0)(_ + _) // Create ranges for each binding based on the running sums and return // those along with resolved values for the star operations. (oSum.init.zip(oSum.tail), iSum.init.zip(iSum.tail), oStar, iStar) } catch { case c: StarCycleException => throw c.copy(loop = context +: c.loop) } } /** Sequence of inward ports. * * This should be called after all star bindings are resolved. * * Each element is: `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. * `n` Instance of inward node. `p` View of [[Parameters]] where this connection was made. `s` Source info where this * connection was made in the source code. */ protected[diplomacy] lazy val oDirectPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oBindings.flatMap { case (i, n, _, p, s) => // for each binding operator in this node, look at what it connects to val (start, end) = n.iPortMapping(i) (start until end).map { j => (j, n, p, s) } } /** Sequence of outward ports. * * This should be called after all star bindings are resolved. * * `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. `n` Instance of * outward node. `p` View of [[Parameters]] where this connection was made. `s` [[SourceInfo]] where this connection * was made in the source code. */ protected[diplomacy] lazy val iDirectPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iBindings.flatMap { case (i, n, _, p, s) => // query this port index range of this node in the other side of node. val (start, end) = n.oPortMapping(i) (start until end).map { j => (j, n, p, s) } } // Ephemeral nodes ( which have non-None iForward/oForward) have in_degree = out_degree // Thus, there must exist an Eulerian path and the below algorithms terminate @scala.annotation.tailrec private def oTrace( tuple: (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) ): (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.iForward(i) match { case None => (i, n, p, s) case Some((j, m)) => oTrace((j, m, p, s)) } } @scala.annotation.tailrec private def iTrace( tuple: (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) ): (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.oForward(i) match { case None => (i, n, p, s) case Some((j, m)) => iTrace((j, m, p, s)) } } /** Final output ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - Numeric index of this binding in the [[InwardNode]] on the other end. * - [[InwardNode]] on the other end of this binding. * - A view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. */ lazy val oPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oDirectPorts.map(oTrace) /** Final input ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - numeric index of this binding in [[OutwardNode]] on the other end. * - [[OutwardNode]] on the other end of this binding. * - a view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. */ lazy val iPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iDirectPorts.map(iTrace) private var oParamsCycleGuard = false protected[diplomacy] lazy val diParams: Seq[DI] = iPorts.map { case (i, n, _, _) => n.doParams(i) } protected[diplomacy] lazy val doParams: Seq[DO] = { try { if (oParamsCycleGuard) throw DownwardCycleException() oParamsCycleGuard = true val o = mapParamsD(oPorts.size, diParams) require( o.size == oPorts.size, s"""Diplomacy has detected a problem with your graph: |At the following node, the number of outward ports should equal the number of produced outward parameters. |$context |$connectedPortsInfo |Downstreamed inward parameters: [${diParams.mkString(",")}] |Produced outward parameters: [${o.mkString(",")}] |""".stripMargin ) o.map(outer.mixO(_, this)) } catch { case c: DownwardCycleException => throw c.copy(loop = context +: c.loop) } } private var iParamsCycleGuard = false protected[diplomacy] lazy val uoParams: Seq[UO] = oPorts.map { case (o, n, _, _) => n.uiParams(o) } protected[diplomacy] lazy val uiParams: Seq[UI] = { try { if (iParamsCycleGuard) throw UpwardCycleException() iParamsCycleGuard = true val i = mapParamsU(iPorts.size, uoParams) require( i.size == iPorts.size, s"""Diplomacy has detected a problem with your graph: |At the following node, the number of inward ports should equal the number of produced inward parameters. |$context |$connectedPortsInfo |Upstreamed outward parameters: [${uoParams.mkString(",")}] |Produced inward parameters: [${i.mkString(",")}] |""".stripMargin ) i.map(inner.mixI(_, this)) } catch { case c: UpwardCycleException => throw c.copy(loop = context +: c.loop) } } /** Outward edge parameters. */ protected[diplomacy] lazy val edgesOut: Seq[EO] = (oPorts.zip(doParams)).map { case ((i, n, p, s), o) => outer.edgeO(o, n.uiParams(i), p, s) } /** Inward edge parameters. */ protected[diplomacy] lazy val edgesIn: Seq[EI] = (iPorts.zip(uiParams)).map { case ((o, n, p, s), i) => inner.edgeI(n.doParams(o), i, p, s) } /** A tuple of the input edge parameters and output edge parameters for the edges bound to this node. * * If you need to access to the edges of a foreign Node, use this method (in/out create bundles). */ lazy val edges: Edges[EI, EO] = Edges(edgesIn, edgesOut) /** Create actual Wires corresponding to the Bundles parameterized by the outward edges of this node. */ protected[diplomacy] lazy val bundleOut: Seq[BO] = edgesOut.map { e => val x = Wire(outer.bundleO(e)).suggestName(s"${valName.value}Out") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } /** Create actual Wires corresponding to the Bundles parameterized by the inward edges of this node. */ protected[diplomacy] lazy val bundleIn: Seq[BI] = edgesIn.map { e => val x = Wire(inner.bundleI(e)).suggestName(s"${valName.value}In") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } private def emptyDanglesOut: Seq[Dangle] = oPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(serial, i), sink = HalfEdge(n.serial, j), flipped = false, name = wirePrefix + "out", dataOpt = None ) } private def emptyDanglesIn: Seq[Dangle] = iPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(n.serial, j), sink = HalfEdge(serial, i), flipped = true, name = wirePrefix + "in", dataOpt = None ) } /** Create the [[Dangle]]s which describe the connections from this node output to other nodes inputs. */ protected[diplomacy] def danglesOut: Seq[Dangle] = emptyDanglesOut.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleOut(i))) } /** Create the [[Dangle]]s which describe the connections from this node input from other nodes outputs. */ protected[diplomacy] def danglesIn: Seq[Dangle] = emptyDanglesIn.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleIn(i))) } private[diplomacy] var instantiated = false /** Gather Bundle and edge parameters of outward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. */ def out: Seq[(BO, EO)] = { require( instantiated, s"$name.out should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleOut.zip(edgesOut) } /** Gather Bundle and edge parameters of inward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. */ def in: Seq[(BI, EI)] = { require( instantiated, s"$name.in should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleIn.zip(edgesIn) } /** Actually instantiate this node during [[LazyModuleImp]] evaluation. Mark that it's safe to use the Bundle wires, * instantiate monitors on all input ports if appropriate, and return all the dangles of this node. */ protected[diplomacy] def instantiate(): Seq[Dangle] = { instantiated = true if (!circuitIdentity) { (iPorts.zip(in)).foreach { case ((_, _, p, _), (b, e)) => if (p(MonitorsEnabled)) inner.monitor(b, e) } } danglesOut ++ danglesIn } protected[diplomacy] def cloneDangles(): Seq[Dangle] = emptyDanglesOut ++ emptyDanglesIn /** Connects the outward part of a node with the inward part of this node. */ protected[diplomacy] def bind( h: OutwardNode[DI, UI, BI], binding: NodeBinding )( implicit p: Parameters, sourceInfo: SourceInfo ): Unit = { val x = this // x := y val y = h sourceLine(sourceInfo, " at ", "") val i = x.iPushed val o = y.oPushed y.oPush( i, x, binding match { case BIND_ONCE => BIND_ONCE case BIND_FLEX => BIND_FLEX case BIND_STAR => BIND_QUERY case BIND_QUERY => BIND_STAR } ) x.iPush(o, y, binding) } /* Metadata for printing the node graph. */ def inputs: Seq[(OutwardNode[DI, UI, BI], RenderedEdge)] = (iPorts.zip(edgesIn)).map { case ((_, n, p, _), e) => val re = inner.render(e) (n, re.copy(flipped = re.flipped != p(RenderFlipped))) } /** Metadata for printing the node graph */ def outputs: Seq[(InwardNode[DO, UO, BO], RenderedEdge)] = oPorts.map { case (i, n, _, _) => (n, n.inputs(i)._2) } } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) || !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.ProbeAckData || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode | small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U || beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }

module TLUART( // @[UART.scala:127:25] input clock, // @[UART.scala:127:25] input reset, // @[UART.scala:127:25] output auto_int_xing_out_sync_0, // @[LazyModuleImp.scala:107:25] output auto_control_xing_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_control_xing_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_control_xing_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_control_xing_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [1:0] auto_control_xing_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [13:0] auto_control_xing_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [28:0] auto_control_xing_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_control_xing_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_control_xing_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_control_xing_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_control_xing_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_control_xing_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_control_xing_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_control_xing_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [13:0] auto_control_xing_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output [63:0] auto_control_xing_in_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_io_out_txd, // @[LazyModuleImp.scala:107:25] input auto_io_out_rxd // @[LazyModuleImp.scala:107:25] ); wire out_front_valid; // @[RegisterRouter.scala:87:24] wire out_front_ready; // @[RegisterRouter.scala:87:24] wire out_bits_read; // @[RegisterRouter.scala:87:24] wire [13:0] out_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:87:24] wire [8:0] in_bits_index; // @[RegisterRouter.scala:73:18] wire in_bits_read; // @[RegisterRouter.scala:73:18] wire buffer_auto_out_d_valid; // @[Buffer.scala:40:9] wire buffer_auto_out_d_ready; // @[Buffer.scala:40:9] wire [63:0] buffer_auto_out_d_bits_data; // @[Buffer.scala:40:9] wire [13:0] buffer_auto_out_d_bits_source; // @[Buffer.scala:40:9] wire [1:0] buffer_auto_out_d_bits_size; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_out_d_bits_opcode; // @[Buffer.scala:40:9] wire buffer_auto_out_a_valid; // @[Buffer.scala:40:9] wire buffer_auto_out_a_ready; // @[Buffer.scala:40:9] wire buffer_auto_out_a_bits_corrupt; // @[Buffer.scala:40:9] wire [63:0] buffer_auto_out_a_bits_data; // @[Buffer.scala:40:9] wire [7:0] buffer_auto_out_a_bits_mask; // @[Buffer.scala:40:9] wire [28:0] buffer_auto_out_a_bits_address; // @[Buffer.scala:40:9] wire [13:0] buffer_auto_out_a_bits_source; // @[Buffer.scala:40:9] wire [1:0] buffer_auto_out_a_bits_size; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_out_a_bits_param; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_out_a_bits_opcode; // @[Buffer.scala:40:9] wire buffer_auto_in_d_valid; // @[Buffer.scala:40:9] wire buffer_auto_in_d_ready; // @[Buffer.scala:40:9] wire [63:0] buffer_auto_in_d_bits_data; // @[Buffer.scala:40:9] wire [13:0] buffer_auto_in_d_bits_source; // @[Buffer.scala:40:9] wire [1:0] buffer_auto_in_d_bits_size; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_in_d_bits_opcode; // @[Buffer.scala:40:9] wire buffer_auto_in_a_valid; // @[Buffer.scala:40:9] wire buffer_auto_in_a_ready; // @[Buffer.scala:40:9] wire buffer_auto_in_a_bits_corrupt; // @[Buffer.scala:40:9] wire [63:0] buffer_auto_in_a_bits_data; // @[Buffer.scala:40:9] wire [7:0] buffer_auto_in_a_bits_mask; // @[Buffer.scala:40:9] wire [28:0] buffer_auto_in_a_bits_address; // @[Buffer.scala:40:9] wire [13:0] buffer_auto_in_a_bits_source; // @[Buffer.scala:40:9] wire [1:0] buffer_auto_in_a_bits_size; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_in_a_bits_param; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_in_a_bits_opcode; // @[Buffer.scala:40:9] wire _rxq_io_deq_valid; // @[UART.scala:133:19] wire [7:0] _rxq_io_deq_bits; // @[UART.scala:133:19] wire [3:0] _rxq_io_count; // @[UART.scala:133:19] wire _rxm_io_out_valid; // @[UART.scala:132:19] wire [7:0] _rxm_io_out_bits; // @[UART.scala:132:19] wire _txq_io_enq_ready; // @[UART.scala:130:19] wire _txq_io_deq_valid; // @[UART.scala:130:19] wire [7:0] _txq_io_deq_bits; // @[UART.scala:130:19] wire [3:0] _txq_io_count; // @[UART.scala:130:19] wire _txm_io_in_ready; // @[UART.scala:129:19] wire _txm_io_tx_busy; // @[UART.scala:129:19] wire auto_control_xing_in_a_valid_0 = auto_control_xing_in_a_valid; // @[UART.scala:127:25] wire [2:0] auto_control_xing_in_a_bits_opcode_0 = auto_control_xing_in_a_bits_opcode; // @[UART.scala:127:25] wire [2:0] auto_control_xing_in_a_bits_param_0 = auto_control_xing_in_a_bits_param; // @[UART.scala:127:25] wire [1:0] auto_control_xing_in_a_bits_size_0 = auto_control_xing_in_a_bits_size; // @[UART.scala:127:25] wire [13:0] auto_control_xing_in_a_bits_source_0 = auto_control_xing_in_a_bits_source; // @[UART.scala:127:25] wire [28:0] auto_control_xing_in_a_bits_address_0 = auto_control_xing_in_a_bits_address; // @[UART.scala:127:25] wire [7:0] auto_control_xing_in_a_bits_mask_0 = auto_control_xing_in_a_bits_mask; // @[UART.scala:127:25] wire [63:0] auto_control_xing_in_a_bits_data_0 = auto_control_xing_in_a_bits_data; // @[UART.scala:127:25] wire auto_control_xing_in_a_bits_corrupt_0 = auto_control_xing_in_a_bits_corrupt; // @[UART.scala:127:25] wire auto_control_xing_in_d_ready_0 = auto_control_xing_in_d_ready; // @[UART.scala:127:25] wire auto_io_out_rxd_0 = auto_io_out_rxd; // @[UART.scala:127:25] wire [8:0] out_maskMatch = 9'h1FC; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_15 = 8'h0; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_16 = 8'h0; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T = 8'h0; // @[RegisterRouter.scala:87:24] wire [8:0] out_prepend = 9'h0; // @[RegisterRouter.scala:87:24] wire [30:0] _out_T_24 = 31'h0; // @[RegisterRouter.scala:87:24] wire [30:0] _out_T_25 = 31'h0; // @[RegisterRouter.scala:87:24] wire [30:0] _out_prepend_T_1 = 31'h0; // @[RegisterRouter.scala:87:24] wire [2:0] controlNodeIn_d_bits_d_opcode = 3'h0; // @[Edges.scala:792:17] wire [63:0] controlNodeIn_d_bits_d_data = 64'h0; // @[Edges.scala:792:17] wire auto_control_xing_in_d_bits_sink = 1'h0; // @[UART.scala:127:25] wire auto_control_xing_in_d_bits_denied = 1'h0; // @[UART.scala:127:25] wire auto_control_xing_in_d_bits_corrupt = 1'h0; // @[UART.scala:127:25] wire buffer_auto_in_d_bits_sink = 1'h0; // @[Buffer.scala:40:9] wire buffer_auto_in_d_bits_denied = 1'h0; // @[Buffer.scala:40:9] wire buffer_auto_in_d_bits_corrupt = 1'h0; // @[Buffer.scala:40:9] wire buffer_auto_out_d_bits_sink = 1'h0; // @[Buffer.scala:40:9] wire buffer_auto_out_d_bits_denied = 1'h0; // @[Buffer.scala:40:9] wire buffer_auto_out_d_bits_corrupt = 1'h0; // @[Buffer.scala:40:9] wire buffer_nodeOut_d_bits_sink = 1'h0; // @[MixedNode.scala:542:17] wire buffer_nodeOut_d_bits_denied = 1'h0; // @[MixedNode.scala:542:17] wire buffer_nodeOut_d_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17] wire buffer_nodeIn_d_bits_sink = 1'h0; // @[MixedNode.scala:551:17] wire buffer_nodeIn_d_bits_denied = 1'h0; // @[MixedNode.scala:551:17] wire buffer_nodeIn_d_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17] wire controlNodeIn_d_bits_sink = 1'h0; // @[MixedNode.scala:551:17] wire controlNodeIn_d_bits_denied = 1'h0; // @[MixedNode.scala:551:17] wire controlNodeIn_d_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17] wire controlXingOut_d_bits_sink = 1'h0; // @[MixedNode.scala:542:17] wire controlXingOut_d_bits_denied = 1'h0; // @[MixedNode.scala:542:17] wire controlXingOut_d_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17] wire controlXingIn_d_bits_sink = 1'h0; // @[MixedNode.scala:551:17] wire controlXingIn_d_bits_denied = 1'h0; // @[MixedNode.scala:551:17] wire controlXingIn_d_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17] wire _ie_WIRE_rxwm = 1'h0; // @[UART.scala:186:32] wire _ie_WIRE_txwm = 1'h0; // @[UART.scala:186:32] wire _out_rifireMux_T_18 = 1'h0; // @[MuxLiteral.scala:49:17] wire _out_wifireMux_T_19 = 1'h0; // @[MuxLiteral.scala:49:17] wire _out_rofireMux_T_18 = 1'h0; // @[MuxLiteral.scala:49:17] wire _out_wofireMux_T_19 = 1'h0; // @[MuxLiteral.scala:49:17] wire _out_out_bits_data_T = 1'h0; // @[MuxLiteral.scala:49:17] wire _out_out_bits_data_T_2 = 1'h0; // @[MuxLiteral.scala:49:17] wire controlNodeIn_d_bits_d_sink = 1'h0; // @[Edges.scala:792:17] wire controlNodeIn_d_bits_d_denied = 1'h0; // @[Edges.scala:792:17] wire controlNodeIn_d_bits_d_corrupt = 1'h0; // @[Edges.scala:792:17] wire [1:0] auto_control_xing_in_d_bits_param = 2'h0; // @[UART.scala:127:25] wire [1:0] buffer_auto_in_d_bits_param = 2'h0; // @[Buffer.scala:40:9] wire [1:0] buffer_auto_out_d_bits_param = 2'h0; // @[Buffer.scala:40:9] wire [1:0] buffer_nodeOut_d_bits_param = 2'h0; // @[MixedNode.scala:542:17] wire [1:0] buffer_nodeIn_d_bits_param = 2'h0; // @[MixedNode.scala:551:17] wire [1:0] controlNodeIn_d_bits_param = 2'h0; // @[MixedNode.scala:551:17] wire [1:0] controlXingOut_d_bits_param = 2'h0; // @[MixedNode.scala:542:17] wire [1:0] controlXingIn_d_bits_param = 2'h0; // @[MixedNode.scala:551:17] wire [1:0] controlNodeIn_d_bits_d_param = 2'h0; // @[Edges.scala:792:17] wire intXingOut_sync_0; // @[MixedNode.scala:542:17] wire out_rifireMux_out = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_5 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_1 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_9 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_2 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_13 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_3 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_17 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_2 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_3 = 1'h1; // @[MuxLiteral.scala:49:48] wire out_rifireMux = 1'h1; // @[MuxLiteral.scala:49:10] wire out_wifireMux_out = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_6 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_1 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_10 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_2 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_14 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_3 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_18 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_2 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_3 = 1'h1; // @[MuxLiteral.scala:49:48] wire out_wifireMux = 1'h1; // @[MuxLiteral.scala:49:10] wire out_rofireMux_out = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_5 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_1 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_9 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_2 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_13 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_3 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_17 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_2 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_3 = 1'h1; // @[MuxLiteral.scala:49:48] wire out_rofireMux = 1'h1; // @[MuxLiteral.scala:49:10] wire out_wofireMux_out = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_6 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_1 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_10 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_2 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_14 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_3 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_18 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_2 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_3 = 1'h1; // @[MuxLiteral.scala:49:48] wire out_wofireMux = 1'h1; // @[MuxLiteral.scala:49:10] wire out_iready = 1'h1; // @[RegisterRouter.scala:87:24] wire out_oready = 1'h1; // @[RegisterRouter.scala:87:24] wire controlXingIn_a_ready; // @[MixedNode.scala:551:17] wire controlXingIn_a_valid = auto_control_xing_in_a_valid_0; // @[UART.scala:127:25] wire [2:0] controlXingIn_a_bits_opcode = auto_control_xing_in_a_bits_opcode_0; // @[UART.scala:127:25] wire [2:0] controlXingIn_a_bits_param = auto_control_xing_in_a_bits_param_0; // @[UART.scala:127:25] wire [1:0] controlXingIn_a_bits_size = auto_control_xing_in_a_bits_size_0; // @[UART.scala:127:25] wire [13:0] controlXingIn_a_bits_source = auto_control_xing_in_a_bits_source_0; // @[UART.scala:127:25] wire [28:0] controlXingIn_a_bits_address = auto_control_xing_in_a_bits_address_0; // @[UART.scala:127:25] wire [7:0] controlXingIn_a_bits_mask = auto_control_xing_in_a_bits_mask_0; // @[UART.scala:127:25] wire [63:0] controlXingIn_a_bits_data = auto_control_xing_in_a_bits_data_0; // @[UART.scala:127:25] wire controlXingIn_a_bits_corrupt = auto_control_xing_in_a_bits_corrupt_0; // @[UART.scala:127:25] wire controlXingIn_d_ready = auto_control_xing_in_d_ready_0; // @[UART.scala:127:25] wire controlXingIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] controlXingIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] controlXingIn_d_bits_size; // @[MixedNode.scala:551:17] wire [13:0] controlXingIn_d_bits_source; // @[MixedNode.scala:551:17] wire [63:0] controlXingIn_d_bits_data; // @[MixedNode.scala:551:17] wire ioNodeOut_txd; // @[MixedNode.scala:542:17] wire ioNodeOut_rxd = auto_io_out_rxd_0; // @[UART.scala:127:25] wire auto_int_xing_out_sync_0_0; // @[UART.scala:127:25] wire auto_control_xing_in_a_ready_0; // @[UART.scala:127:25] wire [2:0] auto_control_xing_in_d_bits_opcode_0; // @[UART.scala:127:25] wire [1:0] auto_control_xing_in_d_bits_size_0; // @[UART.scala:127:25] wire [13:0] auto_control_xing_in_d_bits_source_0; // @[UART.scala:127:25] wire [63:0] auto_control_xing_in_d_bits_data_0; // @[UART.scala:127:25] wire auto_control_xing_in_d_valid_0; // @[UART.scala:127:25] wire auto_io_out_txd_0; // @[UART.scala:127:25] wire buffer_nodeIn_a_ready; // @[MixedNode.scala:551:17] wire controlXingOut_a_ready = buffer_auto_in_a_ready; // @[Buffer.scala:40:9] wire controlXingOut_a_valid; // @[MixedNode.scala:542:17] wire buffer_nodeIn_a_valid = buffer_auto_in_a_valid; // @[Buffer.scala:40:9] wire [2:0] controlXingOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] buffer_nodeIn_a_bits_opcode = buffer_auto_in_a_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] controlXingOut_a_bits_param; // @[MixedNode.scala:542:17] wire [2:0] buffer_nodeIn_a_bits_param = buffer_auto_in_a_bits_param; // @[Buffer.scala:40:9] wire [1:0] controlXingOut_a_bits_size; // @[MixedNode.scala:542:17] wire [1:0] buffer_nodeIn_a_bits_size = buffer_auto_in_a_bits_size; // @[Buffer.scala:40:9] wire [13:0] controlXingOut_a_bits_source; // @[MixedNode.scala:542:17] wire [13:0] buffer_nodeIn_a_bits_source = buffer_auto_in_a_bits_source; // @[Buffer.scala:40:9] wire [28:0] controlXingOut_a_bits_address; // @[MixedNode.scala:542:17] wire [28:0] buffer_nodeIn_a_bits_address = buffer_auto_in_a_bits_address; // @[Buffer.scala:40:9] wire [7:0] controlXingOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [7:0] buffer_nodeIn_a_bits_mask = buffer_auto_in_a_bits_mask; // @[Buffer.scala:40:9] wire [63:0] controlXingOut_a_bits_data; // @[MixedNode.scala:542:17] wire [63:0] buffer_nodeIn_a_bits_data = buffer_auto_in_a_bits_data; // @[Buffer.scala:40:9] wire controlXingOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire buffer_nodeIn_a_bits_corrupt = buffer_auto_in_a_bits_corrupt; // @[Buffer.scala:40:9] wire controlXingOut_d_ready; // @[MixedNode.scala:542:17] wire buffer_nodeIn_d_ready = buffer_auto_in_d_ready; // @[Buffer.scala:40:9] wire buffer_nodeIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] buffer_nodeIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire controlXingOut_d_valid = buffer_auto_in_d_valid; // @[Buffer.scala:40:9] wire [2:0] controlXingOut_d_bits_opcode = buffer_auto_in_d_bits_opcode; // @[Buffer.scala:40:9] wire [1:0] buffer_nodeIn_d_bits_size; // @[MixedNode.scala:551:17] wire [13:0] buffer_nodeIn_d_bits_source; // @[MixedNode.scala:551:17] wire [1:0] controlXingOut_d_bits_size = buffer_auto_in_d_bits_size; // @[Buffer.scala:40:9] wire [13:0] controlXingOut_d_bits_source = buffer_auto_in_d_bits_source; // @[Buffer.scala:40:9] wire [63:0] buffer_nodeIn_d_bits_data; // @[MixedNode.scala:551:17] wire [63:0] controlXingOut_d_bits_data = buffer_auto_in_d_bits_data; // @[Buffer.scala:40:9] wire controlNodeIn_a_ready; // @[MixedNode.scala:551:17] wire buffer_nodeOut_a_ready = buffer_auto_out_a_ready; // @[Buffer.scala:40:9] wire buffer_nodeOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] buffer_nodeOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire controlNodeIn_a_valid = buffer_auto_out_a_valid; // @[Buffer.scala:40:9] wire [2:0] buffer_nodeOut_a_bits_param; // @[MixedNode.scala:542:17] wire [2:0] controlNodeIn_a_bits_opcode = buffer_auto_out_a_bits_opcode; // @[Buffer.scala:40:9] wire [1:0] buffer_nodeOut_a_bits_size; // @[MixedNode.scala:542:17] wire [2:0] controlNodeIn_a_bits_param = buffer_auto_out_a_bits_param; // @[Buffer.scala:40:9] wire [13:0] buffer_nodeOut_a_bits_source; // @[MixedNode.scala:542:17] wire [1:0] controlNodeIn_a_bits_size = buffer_auto_out_a_bits_size; // @[Buffer.scala:40:9] wire [28:0] buffer_nodeOut_a_bits_address; // @[MixedNode.scala:542:17] wire [13:0] controlNodeIn_a_bits_source = buffer_auto_out_a_bits_source; // @[Buffer.scala:40:9] wire [7:0] buffer_nodeOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [28:0] controlNodeIn_a_bits_address = buffer_auto_out_a_bits_address; // @[Buffer.scala:40:9] wire [63:0] buffer_nodeOut_a_bits_data; // @[MixedNode.scala:542:17] wire [7:0] controlNodeIn_a_bits_mask = buffer_auto_out_a_bits_mask; // @[Buffer.scala:40:9] wire buffer_nodeOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire [63:0] controlNodeIn_a_bits_data = buffer_auto_out_a_bits_data; // @[Buffer.scala:40:9] wire buffer_nodeOut_d_ready; // @[MixedNode.scala:542:17] wire controlNodeIn_a_bits_corrupt = buffer_auto_out_a_bits_corrupt; // @[Buffer.scala:40:9] wire controlNodeIn_d_ready = buffer_auto_out_d_ready; // @[Buffer.scala:40:9] wire controlNodeIn_d_valid; // @[MixedNode.scala:551:17] wire buffer_nodeOut_d_valid = buffer_auto_out_d_valid; // @[Buffer.scala:40:9] wire [2:0] controlNodeIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [2:0] buffer_nodeOut_d_bits_opcode = buffer_auto_out_d_bits_opcode; // @[Buffer.scala:40:9] wire [1:0] controlNodeIn_d_bits_size; // @[MixedNode.scala:551:17] wire [1:0] buffer_nodeOut_d_bits_size = buffer_auto_out_d_bits_size; // @[Buffer.scala:40:9] wire [13:0] controlNodeIn_d_bits_source; // @[MixedNode.scala:551:17] wire [13:0] buffer_nodeOut_d_bits_source = buffer_auto_out_d_bits_source; // @[Buffer.scala:40:9] wire [63:0] controlNodeIn_d_bits_data; // @[MixedNode.scala:551:17] wire [63:0] buffer_nodeOut_d_bits_data = buffer_auto_out_d_bits_data; // @[Buffer.scala:40:9] assign buffer_nodeIn_a_ready = buffer_nodeOut_a_ready; // @[MixedNode.scala:542:17, :551:17] assign buffer_auto_out_a_valid = buffer_nodeOut_a_valid; // @[Buffer.scala:40:9] assign buffer_auto_out_a_bits_opcode = buffer_nodeOut_a_bits_opcode; // @[Buffer.scala:40:9] assign buffer_auto_out_a_bits_param = buffer_nodeOut_a_bits_param; // @[Buffer.scala:40:9] assign buffer_auto_out_a_bits_size = buffer_nodeOut_a_bits_size; // @[Buffer.scala:40:9] assign buffer_auto_out_a_bits_source = buffer_nodeOut_a_bits_source; // @[Buffer.scala:40:9] assign buffer_auto_out_a_bits_address = buffer_nodeOut_a_bits_address; // @[Buffer.scala:40:9] assign buffer_auto_out_a_bits_mask = buffer_nodeOut_a_bits_mask; // @[Buffer.scala:40:9] assign buffer_auto_out_a_bits_data = buffer_nodeOut_a_bits_data; // @[Buffer.scala:40:9] assign buffer_auto_out_a_bits_corrupt = buffer_nodeOut_a_bits_corrupt; // @[Buffer.scala:40:9] assign buffer_auto_out_d_ready = buffer_nodeOut_d_ready; // @[Buffer.scala:40:9] assign buffer_nodeIn_d_valid = buffer_nodeOut_d_valid; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeIn_d_bits_opcode = buffer_nodeOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeIn_d_bits_size = buffer_nodeOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeIn_d_bits_source = buffer_nodeOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeIn_d_bits_data = buffer_nodeOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17] assign buffer_auto_in_a_ready = buffer_nodeIn_a_ready; // @[Buffer.scala:40:9] assign buffer_nodeOut_a_valid = buffer_nodeIn_a_valid; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeOut_a_bits_opcode = buffer_nodeIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeOut_a_bits_param = buffer_nodeIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeOut_a_bits_size = buffer_nodeIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeOut_a_bits_source = buffer_nodeIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeOut_a_bits_address = buffer_nodeIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeOut_a_bits_mask = buffer_nodeIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeOut_a_bits_data = buffer_nodeIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeOut_a_bits_corrupt = buffer_nodeIn_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeOut_d_ready = buffer_nodeIn_d_ready; // @[MixedNode.scala:542:17, :551:17] assign buffer_auto_in_d_valid = buffer_nodeIn_d_valid; // @[Buffer.scala:40:9] assign buffer_auto_in_d_bits_opcode = buffer_nodeIn_d_bits_opcode; // @[Buffer.scala:40:9] assign buffer_auto_in_d_bits_size = buffer_nodeIn_d_bits_size; // @[Buffer.scala:40:9] assign buffer_auto_in_d_bits_source = buffer_nodeIn_d_bits_source; // @[Buffer.scala:40:9] assign buffer_auto_in_d_bits_data = buffer_nodeIn_d_bits_data; // @[Buffer.scala:40:9] assign auto_io_out_txd_0 = ioNodeOut_txd; // @[UART.scala:127:25] wire _intnodeOut_0_T_2; // @[UART.scala:191:41] wire intnodeOut_0; // @[MixedNode.scala:542:17] wire in_ready; // @[RegisterRouter.scala:73:18] assign buffer_auto_out_a_ready = controlNodeIn_a_ready; // @[Buffer.scala:40:9] wire in_valid = controlNodeIn_a_valid; // @[RegisterRouter.scala:73:18] wire [1:0] in_bits_extra_tlrr_extra_size = controlNodeIn_a_bits_size; // @[RegisterRouter.scala:73:18] wire [13:0] in_bits_extra_tlrr_extra_source = controlNodeIn_a_bits_source; // @[RegisterRouter.scala:73:18] wire [7:0] in_bits_mask = controlNodeIn_a_bits_mask; // @[RegisterRouter.scala:73:18] wire [63:0] in_bits_data = controlNodeIn_a_bits_data; // @[RegisterRouter.scala:73:18] wire out_ready = controlNodeIn_d_ready; // @[RegisterRouter.scala:87:24] wire out_valid; // @[RegisterRouter.scala:87:24] assign buffer_auto_out_d_valid = controlNodeIn_d_valid; // @[Buffer.scala:40:9] assign buffer_auto_out_d_bits_opcode = controlNodeIn_d_bits_opcode; // @[Buffer.scala:40:9] wire [1:0] controlNodeIn_d_bits_d_size; // @[Edges.scala:792:17] assign buffer_auto_out_d_bits_size = controlNodeIn_d_bits_size; // @[Buffer.scala:40:9] wire [13:0] controlNodeIn_d_bits_d_source; // @[Edges.scala:792:17] assign buffer_auto_out_d_bits_source = controlNodeIn_d_bits_source; // @[Buffer.scala:40:9] wire [63:0] out_bits_data; // @[RegisterRouter.scala:87:24] assign buffer_auto_out_d_bits_data = controlNodeIn_d_bits_data; // @[Buffer.scala:40:9] assign controlXingIn_a_ready = controlXingOut_a_ready; // @[MixedNode.scala:542:17, :551:17] assign buffer_auto_in_a_valid = controlXingOut_a_valid; // @[Buffer.scala:40:9] assign buffer_auto_in_a_bits_opcode = controlXingOut_a_bits_opcode; // @[Buffer.scala:40:9] assign buffer_auto_in_a_bits_param = controlXingOut_a_bits_param; // @[Buffer.scala:40:9] assign buffer_auto_in_a_bits_size = controlXingOut_a_bits_size; // @[Buffer.scala:40:9] assign buffer_auto_in_a_bits_source = controlXingOut_a_bits_source; // @[Buffer.scala:40:9] assign buffer_auto_in_a_bits_address = controlXingOut_a_bits_address; // @[Buffer.scala:40:9] assign buffer_auto_in_a_bits_mask = controlXingOut_a_bits_mask; // @[Buffer.scala:40:9] assign buffer_auto_in_a_bits_data = controlXingOut_a_bits_data; // @[Buffer.scala:40:9] assign buffer_auto_in_a_bits_corrupt = controlXingOut_a_bits_corrupt; // @[Buffer.scala:40:9] assign buffer_auto_in_d_ready = controlXingOut_d_ready; // @[Buffer.scala:40:9] assign controlXingIn_d_valid = controlXingOut_d_valid; // @[MixedNode.scala:542:17, :551:17] assign controlXingIn_d_bits_opcode = controlXingOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign controlXingIn_d_bits_size = controlXingOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17] assign controlXingIn_d_bits_source = controlXingOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17] assign controlXingIn_d_bits_data = controlXingOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17] assign auto_control_xing_in_a_ready_0 = controlXingIn_a_ready; // @[UART.scala:127:25] assign controlXingOut_a_valid = controlXingIn_a_valid; // @[MixedNode.scala:542:17, :551:17] assign controlXingOut_a_bits_opcode = controlXingIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign controlXingOut_a_bits_param = controlXingIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17] assign controlXingOut_a_bits_size = controlXingIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17] assign controlXingOut_a_bits_source = controlXingIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17] assign controlXingOut_a_bits_address = controlXingIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17] assign controlXingOut_a_bits_mask = controlXingIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign controlXingOut_a_bits_data = controlXingIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17] assign controlXingOut_a_bits_corrupt = controlXingIn_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign controlXingOut_d_ready = controlXingIn_d_ready; // @[MixedNode.scala:542:17, :551:17] assign auto_control_xing_in_d_valid_0 = controlXingIn_d_valid; // @[UART.scala:127:25] assign auto_control_xing_in_d_bits_opcode_0 = controlXingIn_d_bits_opcode; // @[UART.scala:127:25] assign auto_control_xing_in_d_bits_size_0 = controlXingIn_d_bits_size; // @[UART.scala:127:25] assign auto_control_xing_in_d_bits_source_0 = controlXingIn_d_bits_source; // @[UART.scala:127:25] assign auto_control_xing_in_d_bits_data_0 = controlXingIn_d_bits_data; // @[UART.scala:127:25] wire intXingIn_sync_0; // @[MixedNode.scala:551:17] assign auto_int_xing_out_sync_0_0 = intXingOut_sync_0; // @[UART.scala:127:25] assign intXingOut_sync_0 = intXingIn_sync_0; // @[MixedNode.scala:542:17, :551:17] reg [15:0] div; // @[UART.scala:135:20] wire [15:0] _out_T_166 = div; // @[RegisterRouter.scala:87:24] reg txen; // @[UART.scala:141:21] wire _out_T_71 = txen; // @[RegisterRouter.scala:87:24] reg rxen; // @[UART.scala:142:21] reg [3:0] txwm; // @[UART.scala:149:21] reg [3:0] rxwm; // @[UART.scala:150:21] reg nstop; // @[UART.scala:151:22] wire _tx_busy_T = |_txq_io_count; // @[UART.scala:130:19, :175:49] wire _tx_busy_T_1 = _txm_io_tx_busy | _tx_busy_T; // @[UART.scala:129:19, :175:{33,49}] wire tx_busy = _tx_busy_T_1 & txen; // @[UART.scala:141:21, :175:{33,54}] reg ie_rxwm; // @[UART.scala:186:19] reg ie_txwm; // @[UART.scala:186:19] wire _out_T_126 = ie_txwm; // @[RegisterRouter.scala:87:24] wire _ip_rxwm_T; // @[UART.scala:190:28] wire _ip_txwm_T; // @[UART.scala:189:28] wire ip_rxwm; // @[UART.scala:187:16] wire ip_txwm; // @[UART.scala:187:16] assign _ip_txwm_T = _txq_io_count < txwm; // @[UART.scala:130:19, :149:21, :189:28] assign ip_txwm = _ip_txwm_T; // @[UART.scala:187:16, :189:28] assign _ip_rxwm_T = _rxq_io_count > rxwm; // @[UART.scala:133:19, :150:21, :190:28] assign ip_rxwm = _ip_rxwm_T; // @[UART.scala:187:16, :190:28] wire _intnodeOut_0_T = ip_txwm & ie_txwm; // @[UART.scala:186:19, :187:16, :191:29] wire _intnodeOut_0_T_1 = ip_rxwm & ie_rxwm; // @[UART.scala:186:19, :187:16, :191:53] assign _intnodeOut_0_T_2 = _intnodeOut_0_T | _intnodeOut_0_T_1; // @[UART.scala:191:{29,41,53}] assign intnodeOut_0 = _intnodeOut_0_T_2; // @[UART.scala:191:41] wire _out_quash_T_1; // @[RegMapFIFO.scala:26:26] wire quash; // @[RegMapFIFO.scala:11:21] wire _out_in_ready_T; // @[RegisterRouter.scala:87:24] assign controlNodeIn_a_ready = in_ready; // @[RegisterRouter.scala:73:18] wire _in_bits_read_T; // @[RegisterRouter.scala:74:36] wire _out_front_valid_T = in_valid; // @[RegisterRouter.scala:73:18, :87:24] wire out_front_bits_read = in_bits_read; // @[RegisterRouter.scala:73:18, :87:24] wire [8:0] out_front_bits_index = in_bits_index; // @[RegisterRouter.scala:73:18, :87:24] wire [63:0] out_front_bits_data = in_bits_data; // @[RegisterRouter.scala:73:18, :87:24] wire [7:0] out_front_bits_mask = in_bits_mask; // @[RegisterRouter.scala:73:18, :87:24] wire [13:0] out_front_bits_extra_tlrr_extra_source = in_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:73:18, :87:24] wire [1:0] out_front_bits_extra_tlrr_extra_size = in_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:73:18, :87:24] assign _in_bits_read_T = controlNodeIn_a_bits_opcode == 3'h4; // @[RegisterRouter.scala:74:36] assign in_bits_read = _in_bits_read_T; // @[RegisterRouter.scala:73:18, :74:36] wire [25:0] _in_bits_index_T = controlNodeIn_a_bits_address[28:3]; // @[Edges.scala:192:34] assign in_bits_index = _in_bits_index_T[8:0]; // @[RegisterRouter.scala:73:18, :75:19] wire _out_front_ready_T = out_ready; // @[RegisterRouter.scala:87:24] wire _out_out_valid_T; // @[RegisterRouter.scala:87:24] assign controlNodeIn_d_valid = out_valid; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_T_4; // @[RegisterRouter.scala:87:24] wire _controlNodeIn_d_bits_opcode_T = out_bits_read; // @[RegisterRouter.scala:87:24, :105:25] assign controlNodeIn_d_bits_data = out_bits_data; // @[RegisterRouter.scala:87:24] assign controlNodeIn_d_bits_d_source = out_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:87:24] wire [1:0] out_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:87:24] assign controlNodeIn_d_bits_d_size = out_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:87:24] assign _out_in_ready_T = out_front_ready; // @[RegisterRouter.scala:87:24] assign _out_out_valid_T = out_front_valid; // @[RegisterRouter.scala:87:24] assign out_bits_read = out_front_bits_read; // @[RegisterRouter.scala:87:24] assign out_bits_extra_tlrr_extra_source = out_front_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:87:24] assign out_bits_extra_tlrr_extra_size = out_front_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:87:24] wire [8:0] _GEN = out_front_bits_index & 9'h1FC; // @[RegisterRouter.scala:87:24] wire [8:0] out_findex; // @[RegisterRouter.scala:87:24] assign out_findex = _GEN; // @[RegisterRouter.scala:87:24] wire [8:0] out_bindex; // @[RegisterRouter.scala:87:24] assign out_bindex = _GEN; // @[RegisterRouter.scala:87:24] wire _GEN_0 = out_findex == 9'h0; // @[RegisterRouter.scala:87:24] wire _out_T; // @[RegisterRouter.scala:87:24] assign _out_T = _GEN_0; // @[RegisterRouter.scala:87:24] wire _out_T_2; // @[RegisterRouter.scala:87:24] assign _out_T_2 = _GEN_0; // @[RegisterRouter.scala:87:24] wire _out_T_4; // @[RegisterRouter.scala:87:24] assign _out_T_4 = _GEN_0; // @[RegisterRouter.scala:87:24] wire _out_T_6; // @[RegisterRouter.scala:87:24] assign _out_T_6 = _GEN_0; // @[RegisterRouter.scala:87:24] wire _GEN_1 = out_bindex == 9'h0; // @[RegisterRouter.scala:87:24] wire _out_T_1; // @[RegisterRouter.scala:87:24] assign _out_T_1 = _GEN_1; // @[RegisterRouter.scala:87:24] wire _out_T_3; // @[RegisterRouter.scala:87:24] assign _out_T_3 = _GEN_1; // @[RegisterRouter.scala:87:24] wire _out_T_5; // @[RegisterRouter.scala:87:24] assign _out_T_5 = _GEN_1; // @[RegisterRouter.scala:87:24] wire _out_T_7; // @[RegisterRouter.scala:87:24] assign _out_T_7 = _GEN_1; // @[RegisterRouter.scala:87:24] wire _out_out_bits_data_WIRE_0 = _out_T_1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_1 = _out_T_3; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2 = _out_T_5; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24] wire _out_out_bits_data_WIRE_3 = _out_T_7; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_T_7; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_11; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_15; // @[RegisterRouter.scala:87:24] wire out_rivalid_0; // @[RegisterRouter.scala:87:24] wire out_rivalid_1; // @[RegisterRouter.scala:87:24] wire out_rivalid_2; // @[RegisterRouter.scala:87:24] wire out_rivalid_3; // @[RegisterRouter.scala:87:24] wire out_rivalid_4; // @[RegisterRouter.scala:87:24] wire out_rivalid_5; // @[RegisterRouter.scala:87:24] wire out_rivalid_6; // @[RegisterRouter.scala:87:24] wire out_rivalid_7; // @[RegisterRouter.scala:87:24] wire out_rivalid_8; // @[RegisterRouter.scala:87:24] wire out_rivalid_9; // @[RegisterRouter.scala:87:24] wire out_rivalid_10; // @[RegisterRouter.scala:87:24] wire out_rivalid_11; // @[RegisterRouter.scala:87:24] wire out_rivalid_12; // @[RegisterRouter.scala:87:24] wire out_rivalid_13; // @[RegisterRouter.scala:87:24] wire out_rivalid_14; // @[RegisterRouter.scala:87:24] wire out_rivalid_15; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_8; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_12; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_16; // @[RegisterRouter.scala:87:24] wire out_wivalid_0; // @[RegisterRouter.scala:87:24] wire out_wivalid_1; // @[RegisterRouter.scala:87:24] wire out_wivalid_2; // @[RegisterRouter.scala:87:24] wire out_wivalid_3; // @[RegisterRouter.scala:87:24] wire out_wivalid_4; // @[RegisterRouter.scala:87:24] wire out_wivalid_5; // @[RegisterRouter.scala:87:24] wire out_wivalid_6; // @[RegisterRouter.scala:87:24] wire out_wivalid_7; // @[RegisterRouter.scala:87:24] wire out_wivalid_8; // @[RegisterRouter.scala:87:24] wire out_wivalid_9; // @[RegisterRouter.scala:87:24] wire out_wivalid_10; // @[RegisterRouter.scala:87:24] wire out_wivalid_11; // @[RegisterRouter.scala:87:24] wire out_wivalid_12; // @[RegisterRouter.scala:87:24] wire out_wivalid_13; // @[RegisterRouter.scala:87:24] wire out_wivalid_14; // @[RegisterRouter.scala:87:24] wire out_wivalid_15; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_7; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_11; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_15; // @[RegisterRouter.scala:87:24] wire out_roready_0; // @[RegisterRouter.scala:87:24] wire out_roready_1; // @[RegisterRouter.scala:87:24] wire out_roready_2; // @[RegisterRouter.scala:87:24] wire out_roready_3; // @[RegisterRouter.scala:87:24] wire out_roready_4; // @[RegisterRouter.scala:87:24] wire out_roready_5; // @[RegisterRouter.scala:87:24] wire out_roready_6; // @[RegisterRouter.scala:87:24] wire out_roready_7; // @[RegisterRouter.scala:87:24] wire out_roready_8; // @[RegisterRouter.scala:87:24] wire out_roready_9; // @[RegisterRouter.scala:87:24] wire out_roready_10; // @[RegisterRouter.scala:87:24] wire out_roready_11; // @[RegisterRouter.scala:87:24] wire out_roready_12; // @[RegisterRouter.scala:87:24] wire out_roready_13; // @[RegisterRouter.scala:87:24] wire out_roready_14; // @[RegisterRouter.scala:87:24] wire out_roready_15; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_8; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_12; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_16; // @[RegisterRouter.scala:87:24] wire out_woready_0; // @[RegisterRouter.scala:87:24] wire out_woready_1; // @[RegisterRouter.scala:87:24] wire out_woready_2; // @[RegisterRouter.scala:87:24] wire out_woready_3; // @[RegisterRouter.scala:87:24] wire out_woready_4; // @[RegisterRouter.scala:87:24] wire out_woready_5; // @[RegisterRouter.scala:87:24] wire out_woready_6; // @[RegisterRouter.scala:87:24] wire out_woready_7; // @[RegisterRouter.scala:87:24] wire out_woready_8; // @[RegisterRouter.scala:87:24] wire out_woready_9; // @[RegisterRouter.scala:87:24] wire out_woready_10; // @[RegisterRouter.scala:87:24] wire out_woready_11; // @[RegisterRouter.scala:87:24] wire out_woready_12; // @[RegisterRouter.scala:87:24] wire out_woready_13; // @[RegisterRouter.scala:87:24] wire out_woready_14; // @[RegisterRouter.scala:87:24] wire out_woready_15; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T = out_front_bits_mask[0]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T = out_front_bits_mask[0]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_1 = out_front_bits_mask[1]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_1 = out_front_bits_mask[1]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_2 = out_front_bits_mask[2]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_2 = out_front_bits_mask[2]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_3 = out_front_bits_mask[3]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_3 = out_front_bits_mask[3]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_4 = out_front_bits_mask[4]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_4 = out_front_bits_mask[4]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_5 = out_front_bits_mask[5]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_5 = out_front_bits_mask[5]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_6 = out_front_bits_mask[6]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_6 = out_front_bits_mask[6]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_7 = out_front_bits_mask[7]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_7 = out_front_bits_mask[7]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_8 = {8{_out_frontMask_T}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_9 = {8{_out_frontMask_T_1}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_10 = {8{_out_frontMask_T_2}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_11 = {8{_out_frontMask_T_3}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_12 = {8{_out_frontMask_T_4}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_13 = {8{_out_frontMask_T_5}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_14 = {8{_out_frontMask_T_6}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_15 = {8{_out_frontMask_T_7}}; // @[RegisterRouter.scala:87:24] wire [15:0] out_frontMask_lo_lo = {_out_frontMask_T_9, _out_frontMask_T_8}; // @[RegisterRouter.scala:87:24] wire [15:0] out_frontMask_lo_hi = {_out_frontMask_T_11, _out_frontMask_T_10}; // @[RegisterRouter.scala:87:24] wire [31:0] out_frontMask_lo = {out_frontMask_lo_hi, out_frontMask_lo_lo}; // @[RegisterRouter.scala:87:24] wire [15:0] out_frontMask_hi_lo = {_out_frontMask_T_13, _out_frontMask_T_12}; // @[RegisterRouter.scala:87:24] wire [15:0] out_frontMask_hi_hi = {_out_frontMask_T_15, _out_frontMask_T_14}; // @[RegisterRouter.scala:87:24] wire [31:0] out_frontMask_hi = {out_frontMask_hi_hi, out_frontMask_hi_lo}; // @[RegisterRouter.scala:87:24] wire [63:0] out_frontMask = {out_frontMask_hi, out_frontMask_lo}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_8 = {8{_out_backMask_T}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_9 = {8{_out_backMask_T_1}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_10 = {8{_out_backMask_T_2}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_11 = {8{_out_backMask_T_3}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_12 = {8{_out_backMask_T_4}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_13 = {8{_out_backMask_T_5}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_14 = {8{_out_backMask_T_6}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_15 = {8{_out_backMask_T_7}}; // @[RegisterRouter.scala:87:24] wire [15:0] out_backMask_lo_lo = {_out_backMask_T_9, _out_backMask_T_8}; // @[RegisterRouter.scala:87:24] wire [15:0] out_backMask_lo_hi = {_out_backMask_T_11, _out_backMask_T_10}; // @[RegisterRouter.scala:87:24] wire [31:0] out_backMask_lo = {out_backMask_lo_hi, out_backMask_lo_lo}; // @[RegisterRouter.scala:87:24] wire [15:0] out_backMask_hi_lo = {_out_backMask_T_13, _out_backMask_T_12}; // @[RegisterRouter.scala:87:24] wire [15:0] out_backMask_hi_hi = {_out_backMask_T_15, _out_backMask_T_14}; // @[RegisterRouter.scala:87:24] wire [31:0] out_backMask_hi = {out_backMask_hi_hi, out_backMask_hi_lo}; // @[RegisterRouter.scala:87:24] wire [63:0] out_backMask = {out_backMask_hi, out_backMask_lo}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24] wire out_rimask = |_out_rimask_T; // @[RegisterRouter.scala:87:24] wire out_wimask = &_out_wimask_T; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T = out_backMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T = out_backMask[7:0]; // @[RegisterRouter.scala:87:24] wire out_romask = |_out_romask_T; // @[RegisterRouter.scala:87:24] wire out_womask = &_out_womask_T; // @[RegisterRouter.scala:87:24] wire out_f_rivalid = out_rivalid_0 & out_rimask; // @[RegisterRouter.scala:87:24] wire out_f_roready = out_roready_0 & out_romask; // @[RegisterRouter.scala:87:24] wire out_f_wivalid = out_wivalid_0 & out_wimask; // @[RegisterRouter.scala:87:24] wire _out_T_9 = out_f_wivalid; // @[RegisterRouter.scala:87:24] wire out_f_woready = out_woready_0 & out_womask; // @[RegisterRouter.scala:87:24] wire _out_T_10 = out_f_woready; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8 = out_front_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire _out_txq_io_enq_valid_T = ~quash; // @[RegMapFIFO.scala:11:21, :18:33] wire _out_txq_io_enq_valid_T_1 = out_f_woready & _out_txq_io_enq_valid_T; // @[RegisterRouter.scala:87:24] wire _out_T_11 = ~out_rimask; // @[RegisterRouter.scala:87:24] wire _out_T_12 = ~out_wimask; // @[RegisterRouter.scala:87:24] wire _out_T_13 = ~out_romask; // @[RegisterRouter.scala:87:24] wire _out_T_14 = ~out_womask; // @[RegisterRouter.scala:87:24] wire [22:0] _out_rimask_T_1 = out_frontMask[30:8]; // @[RegisterRouter.scala:87:24] wire [22:0] _out_wimask_T_1 = out_frontMask[30:8]; // @[RegisterRouter.scala:87:24] wire out_rimask_1 = |_out_rimask_T_1; // @[RegisterRouter.scala:87:24] wire out_wimask_1 = &_out_wimask_T_1; // @[RegisterRouter.scala:87:24] wire [22:0] _out_romask_T_1 = out_backMask[30:8]; // @[RegisterRouter.scala:87:24] wire [22:0] _out_womask_T_1 = out_backMask[30:8]; // @[RegisterRouter.scala:87:24] wire out_romask_1 = |_out_romask_T_1; // @[RegisterRouter.scala:87:24] wire out_womask_1 = &_out_womask_T_1; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1 = out_rivalid_1 & out_rimask_1; // @[RegisterRouter.scala:87:24] wire _out_T_18 = out_f_rivalid_1; // @[RegisterRouter.scala:87:24] wire out_f_roready_1 = out_roready_1 & out_romask_1; // @[RegisterRouter.scala:87:24] wire _out_T_19 = out_f_roready_1; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1 = out_wivalid_1 & out_wimask_1; // @[RegisterRouter.scala:87:24] wire out_f_woready_1 = out_woready_1 & out_womask_1; // @[RegisterRouter.scala:87:24] wire [22:0] _out_T_17 = out_front_bits_data[30:8]; // @[RegisterRouter.scala:87:24] wire _out_T_20 = ~out_rimask_1; // @[RegisterRouter.scala:87:24] wire _out_T_21 = ~out_wimask_1; // @[RegisterRouter.scala:87:24] wire _out_T_22 = ~out_romask_1; // @[RegisterRouter.scala:87:24] wire _out_T_23 = ~out_womask_1; // @[RegisterRouter.scala:87:24] wire _out_rimask_T_2 = out_frontMask[31]; // @[RegisterRouter.scala:87:24] wire _out_wimask_T_2 = out_frontMask[31]; // @[RegisterRouter.scala:87:24] wire out_rimask_2 = _out_rimask_T_2; // @[RegisterRouter.scala:87:24] wire out_wimask_2 = _out_wimask_T_2; // @[RegisterRouter.scala:87:24] wire _out_romask_T_2 = out_backMask[31]; // @[RegisterRouter.scala:87:24] wire _out_womask_T_2 = out_backMask[31]; // @[RegisterRouter.scala:87:24] wire out_romask_2 = _out_romask_T_2; // @[RegisterRouter.scala:87:24] wire out_womask_2 = _out_womask_T_2; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_2 = out_rivalid_2 & out_rimask_2; // @[RegisterRouter.scala:87:24] wire _out_T_27 = out_f_rivalid_2; // @[RegisterRouter.scala:87:24] wire out_f_roready_2 = out_roready_2 & out_romask_2; // @[RegisterRouter.scala:87:24] wire _out_T_28 = out_f_roready_2; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_2 = out_wivalid_2 & out_wimask_2; // @[RegisterRouter.scala:87:24] wire out_f_woready_2 = out_woready_2 & out_womask_2; // @[RegisterRouter.scala:87:24] wire _out_T_26 = out_front_bits_data[31]; // @[RegisterRouter.scala:87:24] wire _out_quash_T = _out_T_26; // @[RegisterRouter.scala:87:24] assign _out_quash_T_1 = out_f_woready_2 & _out_quash_T; // @[RegisterRouter.scala:87:24] assign quash = _out_quash_T_1; // @[RegMapFIFO.scala:11:21, :26:26] wire _out_T_29 = ~out_rimask_2; // @[RegisterRouter.scala:87:24] wire _out_T_30 = ~out_wimask_2; // @[RegisterRouter.scala:87:24] wire _out_T_31 = ~out_romask_2; // @[RegisterRouter.scala:87:24] wire _out_T_32 = ~out_womask_2; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_1 = {~_txq_io_enq_ready, 31'h0}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_33 = out_prepend_1; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_34 = _out_T_33; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_2 = _out_T_34; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_3 = out_frontMask[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_3 = out_frontMask[39:32]; // @[RegisterRouter.scala:87:24] wire out_rimask_3 = |_out_rimask_T_3; // @[RegisterRouter.scala:87:24] wire out_wimask_3 = &_out_wimask_T_3; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_3 = out_backMask[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_3 = out_backMask[39:32]; // @[RegisterRouter.scala:87:24] wire out_romask_3 = |_out_romask_T_3; // @[RegisterRouter.scala:87:24] wire out_womask_3 = &_out_womask_T_3; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_3 = out_rivalid_3 & out_rimask_3; // @[RegisterRouter.scala:87:24] wire _out_T_36 = out_f_rivalid_3; // @[RegisterRouter.scala:87:24] wire out_f_roready_3 = out_roready_3 & out_romask_3; // @[RegisterRouter.scala:87:24] wire _out_T_37 = out_f_roready_3; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_3 = out_wivalid_3 & out_wimask_3; // @[RegisterRouter.scala:87:24] wire out_f_woready_3 = out_woready_3 & out_womask_3; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_35 = out_front_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire _out_T_38 = ~out_rimask_3; // @[RegisterRouter.scala:87:24] wire _out_T_39 = ~out_wimask_3; // @[RegisterRouter.scala:87:24] wire _out_T_40 = ~out_romask_3; // @[RegisterRouter.scala:87:24] wire _out_T_41 = ~out_womask_3; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_2 = {_rxq_io_deq_bits, _out_prepend_T_2}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_42 = out_prepend_2; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_43 = _out_T_42; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_3 = _out_T_43; // @[RegisterRouter.scala:87:24] wire [22:0] _out_rimask_T_4 = out_frontMask[62:40]; // @[RegisterRouter.scala:87:24] wire [22:0] _out_wimask_T_4 = out_frontMask[62:40]; // @[RegisterRouter.scala:87:24] wire out_rimask_4 = |_out_rimask_T_4; // @[RegisterRouter.scala:87:24] wire out_wimask_4 = &_out_wimask_T_4; // @[RegisterRouter.scala:87:24] wire [22:0] _out_romask_T_4 = out_backMask[62:40]; // @[RegisterRouter.scala:87:24] wire [22:0] _out_womask_T_4 = out_backMask[62:40]; // @[RegisterRouter.scala:87:24] wire out_romask_4 = |_out_romask_T_4; // @[RegisterRouter.scala:87:24] wire out_womask_4 = &_out_womask_T_4; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_4 = out_rivalid_4 & out_rimask_4; // @[RegisterRouter.scala:87:24] wire _out_T_45 = out_f_rivalid_4; // @[RegisterRouter.scala:87:24] wire out_f_roready_4 = out_roready_4 & out_romask_4; // @[RegisterRouter.scala:87:24] wire _out_T_46 = out_f_roready_4; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_4 = out_wivalid_4 & out_wimask_4; // @[RegisterRouter.scala:87:24] wire out_f_woready_4 = out_woready_4 & out_womask_4; // @[RegisterRouter.scala:87:24] wire [22:0] _out_T_44 = out_front_bits_data[62:40]; // @[RegisterRouter.scala:87:24] wire _out_T_47 = ~out_rimask_4; // @[RegisterRouter.scala:87:24] wire _out_T_48 = ~out_wimask_4; // @[RegisterRouter.scala:87:24] wire _out_T_49 = ~out_romask_4; // @[RegisterRouter.scala:87:24] wire _out_T_50 = ~out_womask_4; // @[RegisterRouter.scala:87:24] wire [40:0] out_prepend_3 = {1'h0, _out_prepend_T_3}; // @[RegisterRouter.scala:87:24] wire [62:0] _out_T_51 = {22'h0, out_prepend_3}; // @[RegisterRouter.scala:87:24] wire [62:0] _out_T_52 = _out_T_51; // @[RegisterRouter.scala:87:24] wire [62:0] _out_prepend_T_4 = _out_T_52; // @[RegisterRouter.scala:87:24] wire _out_rimask_T_5 = out_frontMask[63]; // @[RegisterRouter.scala:87:24] wire _out_wimask_T_5 = out_frontMask[63]; // @[RegisterRouter.scala:87:24] wire out_rimask_5 = _out_rimask_T_5; // @[RegisterRouter.scala:87:24] wire out_wimask_5 = _out_wimask_T_5; // @[RegisterRouter.scala:87:24] wire _out_romask_T_5 = out_backMask[63]; // @[RegisterRouter.scala:87:24] wire _out_womask_T_5 = out_backMask[63]; // @[RegisterRouter.scala:87:24] wire out_romask_5 = _out_romask_T_5; // @[RegisterRouter.scala:87:24] wire out_womask_5 = _out_womask_T_5; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_5 = out_rivalid_5 & out_rimask_5; // @[RegisterRouter.scala:87:24] wire _out_T_54 = out_f_rivalid_5; // @[RegisterRouter.scala:87:24] wire out_f_roready_5 = out_roready_5 & out_romask_5; // @[RegisterRouter.scala:87:24] wire _out_T_55 = out_f_roready_5; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_5 = out_wivalid_5 & out_wimask_5; // @[RegisterRouter.scala:87:24] wire out_f_woready_5 = out_woready_5 & out_womask_5; // @[RegisterRouter.scala:87:24] wire _out_T_53 = out_front_bits_data[63]; // @[RegisterRouter.scala:87:24] wire _out_T_56 = ~out_rimask_5; // @[RegisterRouter.scala:87:24] wire _out_T_57 = ~out_wimask_5; // @[RegisterRouter.scala:87:24] wire _out_T_58 = ~out_romask_5; // @[RegisterRouter.scala:87:24] wire _out_T_59 = ~out_womask_5; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_4 = {~_rxq_io_deq_valid, _out_prepend_T_4}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_60 = out_prepend_4; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_61 = _out_T_60; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_1_0 = _out_T_61; // @[MuxLiteral.scala:49:48] wire _out_rimask_T_6 = out_frontMask[0]; // @[RegisterRouter.scala:87:24] wire _out_wimask_T_6 = out_frontMask[0]; // @[RegisterRouter.scala:87:24] wire _out_rimask_T_11 = out_frontMask[0]; // @[RegisterRouter.scala:87:24] wire _out_wimask_T_11 = out_frontMask[0]; // @[RegisterRouter.scala:87:24] wire out_rimask_6 = _out_rimask_T_6; // @[RegisterRouter.scala:87:24] wire out_wimask_6 = _out_wimask_T_6; // @[RegisterRouter.scala:87:24] wire _out_romask_T_6 = out_backMask[0]; // @[RegisterRouter.scala:87:24] wire _out_womask_T_6 = out_backMask[0]; // @[RegisterRouter.scala:87:24] wire _out_romask_T_11 = out_backMask[0]; // @[RegisterRouter.scala:87:24] wire _out_womask_T_11 = out_backMask[0]; // @[RegisterRouter.scala:87:24] wire out_romask_6 = _out_romask_T_6; // @[RegisterRouter.scala:87:24] wire out_womask_6 = _out_womask_T_6; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_6 = out_rivalid_6 & out_rimask_6; // @[RegisterRouter.scala:87:24] wire _out_T_63 = out_f_rivalid_6; // @[RegisterRouter.scala:87:24] wire out_f_roready_6 = out_roready_6 & out_romask_6; // @[RegisterRouter.scala:87:24] wire _out_T_64 = out_f_roready_6; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_6 = out_wivalid_6 & out_wimask_6; // @[RegisterRouter.scala:87:24] wire _out_T_65 = out_f_wivalid_6; // @[RegisterRouter.scala:87:24] wire out_f_woready_6 = out_woready_6 & out_womask_6; // @[RegisterRouter.scala:87:24] wire _out_T_66 = out_f_woready_6; // @[RegisterRouter.scala:87:24] wire _out_T_62 = out_front_bits_data[0]; // @[RegisterRouter.scala:87:24] wire _out_T_117 = out_front_bits_data[0]; // @[RegisterRouter.scala:87:24] wire _out_T_67 = ~out_rimask_6; // @[RegisterRouter.scala:87:24] wire _out_T_68 = ~out_wimask_6; // @[RegisterRouter.scala:87:24] wire _out_T_69 = ~out_romask_6; // @[RegisterRouter.scala:87:24] wire _out_T_70 = ~out_womask_6; // @[RegisterRouter.scala:87:24] wire _out_T_72 = _out_T_71; // @[RegisterRouter.scala:87:24] wire _out_prepend_T_5 = _out_T_72; // @[RegisterRouter.scala:87:24] wire _out_rimask_T_7 = out_frontMask[1]; // @[RegisterRouter.scala:87:24] wire _out_wimask_T_7 = out_frontMask[1]; // @[RegisterRouter.scala:87:24] wire _out_rimask_T_12 = out_frontMask[1]; // @[RegisterRouter.scala:87:24] wire _out_wimask_T_12 = out_frontMask[1]; // @[RegisterRouter.scala:87:24] wire out_rimask_7 = _out_rimask_T_7; // @[RegisterRouter.scala:87:24] wire out_wimask_7 = _out_wimask_T_7; // @[RegisterRouter.scala:87:24] wire _out_romask_T_7 = out_backMask[1]; // @[RegisterRouter.scala:87:24] wire _out_womask_T_7 = out_backMask[1]; // @[RegisterRouter.scala:87:24] wire _out_romask_T_12 = out_backMask[1]; // @[RegisterRouter.scala:87:24] wire _out_womask_T_12 = out_backMask[1]; // @[RegisterRouter.scala:87:24] wire out_romask_7 = _out_romask_T_7; // @[RegisterRouter.scala:87:24] wire out_womask_7 = _out_womask_T_7; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_7 = out_rivalid_7 & out_rimask_7; // @[RegisterRouter.scala:87:24] wire _out_T_74 = out_f_rivalid_7; // @[RegisterRouter.scala:87:24] wire out_f_roready_7 = out_roready_7 & out_romask_7; // @[RegisterRouter.scala:87:24] wire _out_T_75 = out_f_roready_7; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_7 = out_wivalid_7 & out_wimask_7; // @[RegisterRouter.scala:87:24] wire _out_T_76 = out_f_wivalid_7; // @[RegisterRouter.scala:87:24] wire out_f_woready_7 = out_woready_7 & out_womask_7; // @[RegisterRouter.scala:87:24] wire _out_T_77 = out_f_woready_7; // @[RegisterRouter.scala:87:24] wire _out_T_73 = out_front_bits_data[1]; // @[RegisterRouter.scala:87:24] wire _out_T_128 = out_front_bits_data[1]; // @[RegisterRouter.scala:87:24] wire _out_T_78 = ~out_rimask_7; // @[RegisterRouter.scala:87:24] wire _out_T_79 = ~out_wimask_7; // @[RegisterRouter.scala:87:24] wire _out_T_80 = ~out_romask_7; // @[RegisterRouter.scala:87:24] wire _out_T_81 = ~out_womask_7; // @[RegisterRouter.scala:87:24] wire [1:0] out_prepend_5 = {nstop, _out_prepend_T_5}; // @[RegisterRouter.scala:87:24] wire [1:0] _out_T_82 = out_prepend_5; // @[RegisterRouter.scala:87:24] wire [1:0] _out_T_83 = _out_T_82; // @[RegisterRouter.scala:87:24] wire [3:0] _out_rimask_T_8 = out_frontMask[19:16]; // @[RegisterRouter.scala:87:24] wire [3:0] _out_wimask_T_8 = out_frontMask[19:16]; // @[RegisterRouter.scala:87:24] wire out_rimask_8 = |_out_rimask_T_8; // @[RegisterRouter.scala:87:24] wire out_wimask_8 = &_out_wimask_T_8; // @[RegisterRouter.scala:87:24] wire [3:0] _out_romask_T_8 = out_backMask[19:16]; // @[RegisterRouter.scala:87:24] wire [3:0] _out_womask_T_8 = out_backMask[19:16]; // @[RegisterRouter.scala:87:24] wire out_romask_8 = |_out_romask_T_8; // @[RegisterRouter.scala:87:24] wire out_womask_8 = &_out_womask_T_8; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_8 = out_rivalid_8 & out_rimask_8; // @[RegisterRouter.scala:87:24] wire _out_T_85 = out_f_rivalid_8; // @[RegisterRouter.scala:87:24] wire out_f_roready_8 = out_roready_8 & out_romask_8; // @[RegisterRouter.scala:87:24] wire _out_T_86 = out_f_roready_8; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_8 = out_wivalid_8 & out_wimask_8; // @[RegisterRouter.scala:87:24] wire _out_T_87 = out_f_wivalid_8; // @[RegisterRouter.scala:87:24] wire out_f_woready_8 = out_woready_8 & out_womask_8; // @[RegisterRouter.scala:87:24] wire _out_T_88 = out_f_woready_8; // @[RegisterRouter.scala:87:24] wire [3:0] _out_T_84 = out_front_bits_data[19:16]; // @[RegisterRouter.scala:87:24] wire _out_T_89 = ~out_rimask_8; // @[RegisterRouter.scala:87:24] wire _out_T_90 = ~out_wimask_8; // @[RegisterRouter.scala:87:24] wire _out_T_91 = ~out_romask_8; // @[RegisterRouter.scala:87:24] wire _out_T_92 = ~out_womask_8; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_6 = {14'h0, _out_T_83}; // @[RegisterRouter.scala:87:24] wire [19:0] out_prepend_6 = {txwm, _out_prepend_T_6}; // @[RegisterRouter.scala:87:24] wire [19:0] _out_T_93 = out_prepend_6; // @[RegisterRouter.scala:87:24] wire [19:0] _out_T_94 = _out_T_93; // @[RegisterRouter.scala:87:24] wire _out_rimask_T_9 = out_frontMask[32]; // @[RegisterRouter.scala:87:24] wire _out_wimask_T_9 = out_frontMask[32]; // @[RegisterRouter.scala:87:24] wire _out_rimask_T_13 = out_frontMask[32]; // @[RegisterRouter.scala:87:24] wire _out_wimask_T_13 = out_frontMask[32]; // @[RegisterRouter.scala:87:24] wire out_rimask_9 = _out_rimask_T_9; // @[RegisterRouter.scala:87:24] wire out_wimask_9 = _out_wimask_T_9; // @[RegisterRouter.scala:87:24] wire _out_romask_T_9 = out_backMask[32]; // @[RegisterRouter.scala:87:24] wire _out_womask_T_9 = out_backMask[32]; // @[RegisterRouter.scala:87:24] wire _out_romask_T_13 = out_backMask[32]; // @[RegisterRouter.scala:87:24] wire _out_womask_T_13 = out_backMask[32]; // @[RegisterRouter.scala:87:24] wire out_romask_9 = _out_romask_T_9; // @[RegisterRouter.scala:87:24] wire out_womask_9 = _out_womask_T_9; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_9 = out_rivalid_9 & out_rimask_9; // @[RegisterRouter.scala:87:24] wire _out_T_96 = out_f_rivalid_9; // @[RegisterRouter.scala:87:24] wire out_f_roready_9 = out_roready_9 & out_romask_9; // @[RegisterRouter.scala:87:24] wire _out_T_97 = out_f_roready_9; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_9 = out_wivalid_9 & out_wimask_9; // @[RegisterRouter.scala:87:24] wire _out_T_98 = out_f_wivalid_9; // @[RegisterRouter.scala:87:24] wire out_f_woready_9 = out_woready_9 & out_womask_9; // @[RegisterRouter.scala:87:24] wire _out_T_99 = out_f_woready_9; // @[RegisterRouter.scala:87:24] wire _out_T_95 = out_front_bits_data[32]; // @[RegisterRouter.scala:87:24] wire _out_T_139 = out_front_bits_data[32]; // @[RegisterRouter.scala:87:24] wire _out_T_100 = ~out_rimask_9; // @[RegisterRouter.scala:87:24] wire _out_T_101 = ~out_wimask_9; // @[RegisterRouter.scala:87:24] wire _out_T_102 = ~out_romask_9; // @[RegisterRouter.scala:87:24] wire _out_T_103 = ~out_womask_9; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_7 = {12'h0, _out_T_94}; // @[RegisterRouter.scala:87:24] wire [32:0] out_prepend_7 = {rxen, _out_prepend_T_7}; // @[RegisterRouter.scala:87:24] wire [32:0] _out_T_104 = out_prepend_7; // @[RegisterRouter.scala:87:24] wire [32:0] _out_T_105 = _out_T_104; // @[RegisterRouter.scala:87:24] wire [3:0] _out_rimask_T_10 = out_frontMask[51:48]; // @[RegisterRouter.scala:87:24] wire [3:0] _out_wimask_T_10 = out_frontMask[51:48]; // @[RegisterRouter.scala:87:24] wire out_rimask_10 = |_out_rimask_T_10; // @[RegisterRouter.scala:87:24] wire out_wimask_10 = &_out_wimask_T_10; // @[RegisterRouter.scala:87:24] wire [3:0] _out_romask_T_10 = out_backMask[51:48]; // @[RegisterRouter.scala:87:24] wire [3:0] _out_womask_T_10 = out_backMask[51:48]; // @[RegisterRouter.scala:87:24] wire out_romask_10 = |_out_romask_T_10; // @[RegisterRouter.scala:87:24] wire out_womask_10 = &_out_womask_T_10; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_10 = out_rivalid_10 & out_rimask_10; // @[RegisterRouter.scala:87:24] wire _out_T_107 = out_f_rivalid_10; // @[RegisterRouter.scala:87:24] wire out_f_roready_10 = out_roready_10 & out_romask_10; // @[RegisterRouter.scala:87:24] wire _out_T_108 = out_f_roready_10; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_10 = out_wivalid_10 & out_wimask_10; // @[RegisterRouter.scala:87:24] wire _out_T_109 = out_f_wivalid_10; // @[RegisterRouter.scala:87:24] wire out_f_woready_10 = out_woready_10 & out_womask_10; // @[RegisterRouter.scala:87:24] wire _out_T_110 = out_f_woready_10; // @[RegisterRouter.scala:87:24] wire [3:0] _out_T_106 = out_front_bits_data[51:48]; // @[RegisterRouter.scala:87:24] wire _out_T_111 = ~out_rimask_10; // @[RegisterRouter.scala:87:24] wire _out_T_112 = ~out_wimask_10; // @[RegisterRouter.scala:87:24] wire _out_T_113 = ~out_romask_10; // @[RegisterRouter.scala:87:24] wire _out_T_114 = ~out_womask_10; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_8 = {15'h0, _out_T_105}; // @[RegisterRouter.scala:87:24] wire [51:0] out_prepend_8 = {rxwm, _out_prepend_T_8}; // @[RegisterRouter.scala:87:24] wire [51:0] _out_T_115 = out_prepend_8; // @[RegisterRouter.scala:87:24] wire [51:0] _out_T_116 = _out_T_115; // @[RegisterRouter.scala:87:24] wire out_rimask_11 = _out_rimask_T_11; // @[RegisterRouter.scala:87:24] wire out_wimask_11 = _out_wimask_T_11; // @[RegisterRouter.scala:87:24] wire out_romask_11 = _out_romask_T_11; // @[RegisterRouter.scala:87:24] wire out_womask_11 = _out_womask_T_11; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_11 = out_rivalid_11 & out_rimask_11; // @[RegisterRouter.scala:87:24] wire _out_T_118 = out_f_rivalid_11; // @[RegisterRouter.scala:87:24] wire out_f_roready_11 = out_roready_11 & out_romask_11; // @[RegisterRouter.scala:87:24] wire _out_T_119 = out_f_roready_11; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_11 = out_wivalid_11 & out_wimask_11; // @[RegisterRouter.scala:87:24] wire _out_T_120 = out_f_wivalid_11; // @[RegisterRouter.scala:87:24] wire out_f_woready_11 = out_woready_11 & out_womask_11; // @[RegisterRouter.scala:87:24] wire _out_T_121 = out_f_woready_11; // @[RegisterRouter.scala:87:24] wire _out_T_122 = ~out_rimask_11; // @[RegisterRouter.scala:87:24] wire _out_T_123 = ~out_wimask_11; // @[RegisterRouter.scala:87:24] wire _out_T_124 = ~out_romask_11; // @[RegisterRouter.scala:87:24] wire _out_T_125 = ~out_womask_11; // @[RegisterRouter.scala:87:24] wire _out_T_127 = _out_T_126; // @[RegisterRouter.scala:87:24] wire _out_prepend_T_9 = _out_T_127; // @[RegisterRouter.scala:87:24] wire out_rimask_12 = _out_rimask_T_12; // @[RegisterRouter.scala:87:24] wire out_wimask_12 = _out_wimask_T_12; // @[RegisterRouter.scala:87:24] wire out_romask_12 = _out_romask_T_12; // @[RegisterRouter.scala:87:24] wire out_womask_12 = _out_womask_T_12; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_12 = out_rivalid_12 & out_rimask_12; // @[RegisterRouter.scala:87:24] wire _out_T_129 = out_f_rivalid_12; // @[RegisterRouter.scala:87:24] wire out_f_roready_12 = out_roready_12 & out_romask_12; // @[RegisterRouter.scala:87:24] wire _out_T_130 = out_f_roready_12; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_12 = out_wivalid_12 & out_wimask_12; // @[RegisterRouter.scala:87:24] wire _out_T_131 = out_f_wivalid_12; // @[RegisterRouter.scala:87:24] wire out_f_woready_12 = out_woready_12 & out_womask_12; // @[RegisterRouter.scala:87:24] wire _out_T_132 = out_f_woready_12; // @[RegisterRouter.scala:87:24] wire _out_T_133 = ~out_rimask_12; // @[RegisterRouter.scala:87:24] wire _out_T_134 = ~out_wimask_12; // @[RegisterRouter.scala:87:24] wire _out_T_135 = ~out_romask_12; // @[RegisterRouter.scala:87:24] wire _out_T_136 = ~out_womask_12; // @[RegisterRouter.scala:87:24] wire [1:0] out_prepend_9 = {ie_rxwm, _out_prepend_T_9}; // @[RegisterRouter.scala:87:24] wire [1:0] _out_T_137 = out_prepend_9; // @[RegisterRouter.scala:87:24] wire [1:0] _out_T_138 = _out_T_137; // @[RegisterRouter.scala:87:24] wire out_rimask_13 = _out_rimask_T_13; // @[RegisterRouter.scala:87:24] wire out_wimask_13 = _out_wimask_T_13; // @[RegisterRouter.scala:87:24] wire out_romask_13 = _out_romask_T_13; // @[RegisterRouter.scala:87:24] wire out_womask_13 = _out_womask_T_13; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_13 = out_rivalid_13 & out_rimask_13; // @[RegisterRouter.scala:87:24] wire _out_T_140 = out_f_rivalid_13; // @[RegisterRouter.scala:87:24] wire out_f_roready_13 = out_roready_13 & out_romask_13; // @[RegisterRouter.scala:87:24] wire _out_T_141 = out_f_roready_13; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_13 = out_wivalid_13 & out_wimask_13; // @[RegisterRouter.scala:87:24] wire out_f_woready_13 = out_woready_13 & out_womask_13; // @[RegisterRouter.scala:87:24] wire _out_T_142 = ~out_rimask_13; // @[RegisterRouter.scala:87:24] wire _out_T_143 = ~out_wimask_13; // @[RegisterRouter.scala:87:24] wire _out_T_144 = ~out_romask_13; // @[RegisterRouter.scala:87:24] wire _out_T_145 = ~out_womask_13; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_10 = {30'h0, _out_T_138}; // @[RegisterRouter.scala:87:24] wire [32:0] out_prepend_10 = {ip_txwm, _out_prepend_T_10}; // @[RegisterRouter.scala:87:24] wire [32:0] _out_T_146 = out_prepend_10; // @[RegisterRouter.scala:87:24] wire [32:0] _out_T_147 = _out_T_146; // @[RegisterRouter.scala:87:24] wire [32:0] _out_prepend_T_11 = _out_T_147; // @[RegisterRouter.scala:87:24] wire _out_rimask_T_14 = out_frontMask[33]; // @[RegisterRouter.scala:87:24] wire _out_wimask_T_14 = out_frontMask[33]; // @[RegisterRouter.scala:87:24] wire out_rimask_14 = _out_rimask_T_14; // @[RegisterRouter.scala:87:24] wire out_wimask_14 = _out_wimask_T_14; // @[RegisterRouter.scala:87:24] wire _out_romask_T_14 = out_backMask[33]; // @[RegisterRouter.scala:87:24] wire _out_womask_T_14 = out_backMask[33]; // @[RegisterRouter.scala:87:24] wire out_romask_14 = _out_romask_T_14; // @[RegisterRouter.scala:87:24] wire out_womask_14 = _out_womask_T_14; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_14 = out_rivalid_14 & out_rimask_14; // @[RegisterRouter.scala:87:24] wire _out_T_149 = out_f_rivalid_14; // @[RegisterRouter.scala:87:24] wire out_f_roready_14 = out_roready_14 & out_romask_14; // @[RegisterRouter.scala:87:24] wire _out_T_150 = out_f_roready_14; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_14 = out_wivalid_14 & out_wimask_14; // @[RegisterRouter.scala:87:24] wire out_f_woready_14 = out_woready_14 & out_womask_14; // @[RegisterRouter.scala:87:24] wire _out_T_148 = out_front_bits_data[33]; // @[RegisterRouter.scala:87:24] wire _out_T_151 = ~out_rimask_14; // @[RegisterRouter.scala:87:24] wire _out_T_152 = ~out_wimask_14; // @[RegisterRouter.scala:87:24] wire _out_T_153 = ~out_romask_14; // @[RegisterRouter.scala:87:24] wire _out_T_154 = ~out_womask_14; // @[RegisterRouter.scala:87:24] wire [33:0] out_prepend_11 = {ip_rxwm, _out_prepend_T_11}; // @[RegisterRouter.scala:87:24] wire [33:0] _out_T_155 = out_prepend_11; // @[RegisterRouter.scala:87:24] wire [33:0] _out_T_156 = _out_T_155; // @[RegisterRouter.scala:87:24] wire [15:0] _out_rimask_T_15 = out_frontMask[15:0]; // @[RegisterRouter.scala:87:24] wire [15:0] _out_wimask_T_15 = out_frontMask[15:0]; // @[RegisterRouter.scala:87:24] wire out_rimask_15 = |_out_rimask_T_15; // @[RegisterRouter.scala:87:24] wire out_wimask_15 = &_out_wimask_T_15; // @[RegisterRouter.scala:87:24] wire [15:0] _out_romask_T_15 = out_backMask[15:0]; // @[RegisterRouter.scala:87:24] wire [15:0] _out_womask_T_15 = out_backMask[15:0]; // @[RegisterRouter.scala:87:24] wire out_romask_15 = |_out_romask_T_15; // @[RegisterRouter.scala:87:24] wire out_womask_15 = &_out_womask_T_15; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_15 = out_rivalid_15 & out_rimask_15; // @[RegisterRouter.scala:87:24] wire _out_T_158 = out_f_rivalid_15; // @[RegisterRouter.scala:87:24] wire out_f_roready_15 = out_roready_15 & out_romask_15; // @[RegisterRouter.scala:87:24] wire _out_T_159 = out_f_roready_15; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_15 = out_wivalid_15 & out_wimask_15; // @[RegisterRouter.scala:87:24] wire _out_T_160 = out_f_wivalid_15; // @[RegisterRouter.scala:87:24] wire out_f_woready_15 = out_woready_15 & out_womask_15; // @[RegisterRouter.scala:87:24] wire _out_T_161 = out_f_woready_15; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_157 = out_front_bits_data[15:0]; // @[RegisterRouter.scala:87:24] wire _out_T_162 = ~out_rimask_15; // @[RegisterRouter.scala:87:24] wire _out_T_163 = ~out_wimask_15; // @[RegisterRouter.scala:87:24] wire _out_T_164 = ~out_romask_15; // @[RegisterRouter.scala:87:24] wire _out_T_165 = ~out_womask_15; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_167 = _out_T_166; // @[RegisterRouter.scala:87:24] wire _out_iindex_T = out_front_bits_index[0]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T = out_front_bits_index[0]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_1 = out_front_bits_index[1]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_1 = out_front_bits_index[1]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_2 = out_front_bits_index[2]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_2 = out_front_bits_index[2]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_3 = out_front_bits_index[3]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_3 = out_front_bits_index[3]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_4 = out_front_bits_index[4]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_4 = out_front_bits_index[4]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_5 = out_front_bits_index[5]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_5 = out_front_bits_index[5]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_6 = out_front_bits_index[6]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_6 = out_front_bits_index[6]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_7 = out_front_bits_index[7]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_7 = out_front_bits_index[7]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_8 = out_front_bits_index[8]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_8 = out_front_bits_index[8]; // @[RegisterRouter.scala:87:24] wire [1:0] out_iindex = {_out_iindex_T_1, _out_iindex_T}; // @[RegisterRouter.scala:87:24] wire [1:0] out_oindex = {_out_oindex_T_1, _out_oindex_T}; // @[RegisterRouter.scala:87:24] wire [3:0] _out_frontSel_T = 4'h1 << out_iindex; // @[OneHot.scala:58:35] wire out_frontSel_0 = _out_frontSel_T[0]; // @[OneHot.scala:58:35] wire out_frontSel_1 = _out_frontSel_T[1]; // @[OneHot.scala:58:35] wire out_frontSel_2 = _out_frontSel_T[2]; // @[OneHot.scala:58:35] wire out_frontSel_3 = _out_frontSel_T[3]; // @[OneHot.scala:58:35] wire [3:0] _out_backSel_T = 4'h1 << out_oindex; // @[OneHot.scala:58:35] wire out_backSel_0 = _out_backSel_T[0]; // @[OneHot.scala:58:35] wire out_backSel_1 = _out_backSel_T[1]; // @[OneHot.scala:58:35] wire out_backSel_2 = _out_backSel_T[2]; // @[OneHot.scala:58:35] wire out_backSel_3 = _out_backSel_T[3]; // @[OneHot.scala:58:35] wire _GEN_2 = in_valid & out_front_ready; // @[RegisterRouter.scala:73:18, :87:24] wire _out_rifireMux_T; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T = _GEN_2; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T = _GEN_2; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1 = _out_rifireMux_T & out_front_bits_read; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_2 = _out_rifireMux_T_1 & out_frontSel_0; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_3 = _out_rifireMux_T_2 & _out_T; // @[RegisterRouter.scala:87:24] assign out_rivalid_0 = _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24] assign out_rivalid_1 = _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24] assign out_rivalid_2 = _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24] assign out_rivalid_3 = _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24] assign out_rivalid_4 = _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24] assign out_rivalid_5 = _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_4 = ~_out_T; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_6 = _out_rifireMux_T_1 & out_frontSel_1; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_7 = _out_rifireMux_T_6 & _out_T_2; // @[RegisterRouter.scala:87:24] assign out_rivalid_6 = _out_rifireMux_T_7; // @[RegisterRouter.scala:87:24] assign out_rivalid_7 = _out_rifireMux_T_7; // @[RegisterRouter.scala:87:24] assign out_rivalid_8 = _out_rifireMux_T_7; // @[RegisterRouter.scala:87:24] assign out_rivalid_9 = _out_rifireMux_T_7; // @[RegisterRouter.scala:87:24] assign out_rivalid_10 = _out_rifireMux_T_7; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_8 = ~_out_T_2; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_10 = _out_rifireMux_T_1 & out_frontSel_2; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_11 = _out_rifireMux_T_10 & _out_T_4; // @[RegisterRouter.scala:87:24] assign out_rivalid_11 = _out_rifireMux_T_11; // @[RegisterRouter.scala:87:24] assign out_rivalid_12 = _out_rifireMux_T_11; // @[RegisterRouter.scala:87:24] assign out_rivalid_13 = _out_rifireMux_T_11; // @[RegisterRouter.scala:87:24] assign out_rivalid_14 = _out_rifireMux_T_11; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_12 = ~_out_T_4; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_14 = _out_rifireMux_T_1 & out_frontSel_3; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_15 = _out_rifireMux_T_14 & _out_T_6; // @[RegisterRouter.scala:87:24] assign out_rivalid_15 = _out_rifireMux_T_15; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_16 = ~_out_T_6; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1 = ~out_front_bits_read; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_2 = _out_wifireMux_T & _out_wifireMux_T_1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_3 = _out_wifireMux_T_2 & out_frontSel_0; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_4 = _out_wifireMux_T_3 & _out_T; // @[RegisterRouter.scala:87:24] assign out_wivalid_0 = _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24] assign out_wivalid_1 = _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24] assign out_wivalid_2 = _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24] assign out_wivalid_3 = _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24] assign out_wivalid_4 = _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24] assign out_wivalid_5 = _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_5 = ~_out_T; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_7 = _out_wifireMux_T_2 & out_frontSel_1; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_8 = _out_wifireMux_T_7 & _out_T_2; // @[RegisterRouter.scala:87:24] assign out_wivalid_6 = _out_wifireMux_T_8; // @[RegisterRouter.scala:87:24] assign out_wivalid_7 = _out_wifireMux_T_8; // @[RegisterRouter.scala:87:24] assign out_wivalid_8 = _out_wifireMux_T_8; // @[RegisterRouter.scala:87:24] assign out_wivalid_9 = _out_wifireMux_T_8; // @[RegisterRouter.scala:87:24] assign out_wivalid_10 = _out_wifireMux_T_8; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_9 = ~_out_T_2; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_11 = _out_wifireMux_T_2 & out_frontSel_2; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_12 = _out_wifireMux_T_11 & _out_T_4; // @[RegisterRouter.scala:87:24] assign out_wivalid_11 = _out_wifireMux_T_12; // @[RegisterRouter.scala:87:24] assign out_wivalid_12 = _out_wifireMux_T_12; // @[RegisterRouter.scala:87:24] assign out_wivalid_13 = _out_wifireMux_T_12; // @[RegisterRouter.scala:87:24] assign out_wivalid_14 = _out_wifireMux_T_12; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_13 = ~_out_T_4; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_15 = _out_wifireMux_T_2 & out_frontSel_3; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_16 = _out_wifireMux_T_15 & _out_T_6; // @[RegisterRouter.scala:87:24] assign out_wivalid_15 = _out_wifireMux_T_16; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_17 = ~_out_T_6; // @[RegisterRouter.scala:87:24] wire _GEN_3 = out_front_valid & out_ready; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T = _GEN_3; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T = _GEN_3; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1 = _out_rofireMux_T & out_front_bits_read; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_2 = _out_rofireMux_T_1 & out_backSel_0; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_3 = _out_rofireMux_T_2 & _out_T_1; // @[RegisterRouter.scala:87:24] assign out_roready_0 = _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24] assign out_roready_1 = _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24] assign out_roready_2 = _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24] assign out_roready_3 = _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24] assign out_roready_4 = _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24] assign out_roready_5 = _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_4 = ~_out_T_1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_6 = _out_rofireMux_T_1 & out_backSel_1; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_7 = _out_rofireMux_T_6 & _out_T_3; // @[RegisterRouter.scala:87:24] assign out_roready_6 = _out_rofireMux_T_7; // @[RegisterRouter.scala:87:24] assign out_roready_7 = _out_rofireMux_T_7; // @[RegisterRouter.scala:87:24] assign out_roready_8 = _out_rofireMux_T_7; // @[RegisterRouter.scala:87:24] assign out_roready_9 = _out_rofireMux_T_7; // @[RegisterRouter.scala:87:24] assign out_roready_10 = _out_rofireMux_T_7; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_8 = ~_out_T_3; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_10 = _out_rofireMux_T_1 & out_backSel_2; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_11 = _out_rofireMux_T_10 & _out_T_5; // @[RegisterRouter.scala:87:24] assign out_roready_11 = _out_rofireMux_T_11; // @[RegisterRouter.scala:87:24] assign out_roready_12 = _out_rofireMux_T_11; // @[RegisterRouter.scala:87:24] assign out_roready_13 = _out_rofireMux_T_11; // @[RegisterRouter.scala:87:24] assign out_roready_14 = _out_rofireMux_T_11; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_12 = ~_out_T_5; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_14 = _out_rofireMux_T_1 & out_backSel_3; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_15 = _out_rofireMux_T_14 & _out_T_7; // @[RegisterRouter.scala:87:24] assign out_roready_15 = _out_rofireMux_T_15; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_16 = ~_out_T_7; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1 = ~out_front_bits_read; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_2 = _out_wofireMux_T & _out_wofireMux_T_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_3 = _out_wofireMux_T_2 & out_backSel_0; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_4 = _out_wofireMux_T_3 & _out_T_1; // @[RegisterRouter.scala:87:24] assign out_woready_0 = _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24] assign out_woready_1 = _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24] assign out_woready_2 = _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24] assign out_woready_3 = _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24] assign out_woready_4 = _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24] assign out_woready_5 = _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_5 = ~_out_T_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_7 = _out_wofireMux_T_2 & out_backSel_1; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_8 = _out_wofireMux_T_7 & _out_T_3; // @[RegisterRouter.scala:87:24] assign out_woready_6 = _out_wofireMux_T_8; // @[RegisterRouter.scala:87:24] assign out_woready_7 = _out_wofireMux_T_8; // @[RegisterRouter.scala:87:24] assign out_woready_8 = _out_wofireMux_T_8; // @[RegisterRouter.scala:87:24] assign out_woready_9 = _out_wofireMux_T_8; // @[RegisterRouter.scala:87:24] assign out_woready_10 = _out_wofireMux_T_8; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_9 = ~_out_T_3; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_11 = _out_wofireMux_T_2 & out_backSel_2; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_12 = _out_wofireMux_T_11 & _out_T_5; // @[RegisterRouter.scala:87:24] assign out_woready_11 = _out_wofireMux_T_12; // @[RegisterRouter.scala:87:24] assign out_woready_12 = _out_wofireMux_T_12; // @[RegisterRouter.scala:87:24] assign out_woready_13 = _out_wofireMux_T_12; // @[RegisterRouter.scala:87:24] assign out_woready_14 = _out_wofireMux_T_12; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_13 = ~_out_T_5; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_15 = _out_wofireMux_T_2 & out_backSel_3; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_16 = _out_wofireMux_T_15 & _out_T_7; // @[RegisterRouter.scala:87:24] assign out_woready_15 = _out_wofireMux_T_16; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_17 = ~_out_T_7; // @[RegisterRouter.scala:87:24] assign in_ready = _out_in_ready_T; // @[RegisterRouter.scala:73:18, :87:24] assign out_front_valid = _out_front_valid_T; // @[RegisterRouter.scala:87:24] assign out_front_ready = _out_front_ready_T; // @[RegisterRouter.scala:87:24] assign out_valid = _out_out_valid_T; // @[RegisterRouter.scala:87:24] wire [3:0] _GEN_4 = {{_out_out_bits_data_WIRE_3}, {_out_out_bits_data_WIRE_2}, {_out_out_bits_data_WIRE_1}, {_out_out_bits_data_WIRE_0}}; // @[MuxLiteral.scala:49:{10,48}] wire _out_out_bits_data_T_1 = _GEN_4[out_oindex]; // @[MuxLiteral.scala:49:10] wire [63:0] _out_out_bits_data_WIRE_1_1 = {12'h0, _out_T_116}; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_1_2 = {30'h0, _out_T_156}; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_1_3 = {48'h0, _out_T_167}; // @[MuxLiteral.scala:49:48] wire [3:0][63:0] _GEN_5 = {{_out_out_bits_data_WIRE_1_3}, {_out_out_bits_data_WIRE_1_2}, {_out_out_bits_data_WIRE_1_1}, {_out_out_bits_data_WIRE_1_0}}; // @[MuxLiteral.scala:49:{10,48}] wire [63:0] _out_out_bits_data_T_3 = _GEN_5[out_oindex]; // @[MuxLiteral.scala:49:10] assign _out_out_bits_data_T_4 = _out_out_bits_data_T_1 ? _out_out_bits_data_T_3 : 64'h0; // @[MuxLiteral.scala:49:10] assign out_bits_data = _out_out_bits_data_T_4; // @[RegisterRouter.scala:87:24] assign controlNodeIn_d_bits_size = controlNodeIn_d_bits_d_size; // @[Edges.scala:792:17] assign controlNodeIn_d_bits_source = controlNodeIn_d_bits_d_source; // @[Edges.scala:792:17] assign controlNodeIn_d_bits_opcode = {2'h0, _controlNodeIn_d_bits_opcode_T}; // @[RegisterRouter.scala:105:{19,25}] always @(posedge clock) begin // @[UART.scala:127:25] if (reset) begin // @[UART.scala:127:25] div <= 16'h10F4; // @[UART.scala:135:20] txen <= 1'h0; // @[UART.scala:141:21] rxen <= 1'h0; // @[UART.scala:142:21] txwm <= 4'h0; // @[UART.scala:149:21] rxwm <= 4'h0; // @[UART.scala:150:21] nstop <= 1'h0; // @[UART.scala:151:22] ie_rxwm <= 1'h0; // @[UART.scala:186:19] ie_txwm <= 1'h0; // @[UART.scala:186:19] end else begin // @[UART.scala:127:25] if (out_f_woready_15) // @[RegisterRouter.scala:87:24] div <= _out_T_157; // @[RegisterRouter.scala:87:24] if (out_f_woready_6) // @[RegisterRouter.scala:87:24] txen <= _out_T_62; // @[RegisterRouter.scala:87:24] if (out_f_woready_9) // @[RegisterRouter.scala:87:24] rxen <= _out_T_95; // @[RegisterRouter.scala:87:24] if (out_f_woready_8) // @[RegisterRouter.scala:87:24] txwm <= _out_T_84; // @[RegisterRouter.scala:87:24] if (out_f_woready_10) // @[RegisterRouter.scala:87:24] rxwm <= _out_T_106; // @[RegisterRouter.scala:87:24] if (out_f_woready_7) // @[RegisterRouter.scala:87:24] nstop <= _out_T_73; // @[RegisterRouter.scala:87:24] if (out_f_woready_12) // @[RegisterRouter.scala:87:24] ie_rxwm <= _out_T_128; // @[RegisterRouter.scala:87:24] if (out_f_woready_11) // @[RegisterRouter.scala:87:24] ie_txwm <= _out_T_117; // @[RegisterRouter.scala:87:24] end always @(posedge) IntSyncCrossingSource_n1x1_5 intsource ( // @[Crossing.scala:29:31] .clock (clock), .reset (reset), .auto_in_0 (intnodeOut_0), // @[MixedNode.scala:542:17] .auto_out_sync_0 (intXingIn_sync_0) ); // @[Crossing.scala:29:31] TLMonitor_108 monitor ( // @[Nodes.scala:27:25] .clock (clock), .reset (reset), .io_in_a_ready (controlNodeIn_a_ready), // @[MixedNode.scala:551:17] .io_in_a_valid (controlNodeIn_a_valid), // @[MixedNode.scala:551:17] .io_in_a_bits_opcode (controlNodeIn_a_bits_opcode), // @[MixedNode.scala:551:17] .io_in_a_bits_param (controlNodeIn_a_bits_param), // @[MixedNode.scala:551:17] .io_in_a_bits_size (controlNodeIn_a_bits_size), // @[MixedNode.scala:551:17] .io_in_a_bits_source (controlNodeIn_a_bits_source), // @[MixedNode.scala:551:17] .io_in_a_bits_address (controlNodeIn_a_bits_address), // @[MixedNode.scala:551:17] .io_in_a_bits_mask (controlNodeIn_a_bits_mask), // @[MixedNode.scala:551:17] .io_in_a_bits_data (controlNodeIn_a_bits_data), // @[MixedNode.scala:551:17] .io_in_a_bits_corrupt (controlNodeIn_a_bits_corrupt), // @[MixedNode.scala:551:17] .io_in_d_ready (controlNodeIn_d_ready), // @[MixedNode.scala:551:17] .io_in_d_valid (controlNodeIn_d_valid), // @[MixedNode.scala:551:17] .io_in_d_bits_opcode (controlNodeIn_d_bits_opcode), // @[MixedNode.scala:551:17] .io_in_d_bits_size (controlNodeIn_d_bits_size), // @[MixedNode.scala:551:17] .io_in_d_bits_source (controlNodeIn_d_bits_source), // @[MixedNode.scala:551:17] .io_in_d_bits_data (controlNodeIn_d_bits_data) // @[MixedNode.scala:551:17] ); // @[Nodes.scala:27:25] UARTTx txm ( // @[UART.scala:129:19] .clock (clock), .reset (reset), .io_en (txen), // @[UART.scala:141:21] .io_in_ready (_txm_io_in_ready), .io_in_valid (_txq_io_deq_valid), // @[UART.scala:130:19] .io_in_bits (_txq_io_deq_bits), // @[UART.scala:130:19] .io_out (ioNodeOut_txd), .io_div (div), // @[UART.scala:135:20] .io_nstop (nstop), // @[UART.scala:151:22] .io_tx_busy (_txm_io_tx_busy) ); // @[UART.scala:129:19] Queue8_UInt8 txq ( // @[UART.scala:130:19] .clock (clock), .reset (reset), .io_enq_ready (_txq_io_enq_ready), .io_enq_valid (_out_txq_io_enq_valid_T_1), // @[RegMapFIFO.scala:18:30] .io_enq_bits (_out_T_8), // @[RegisterRouter.scala:87:24] .io_deq_ready (_txm_io_in_ready), // @[UART.scala:129:19] .io_deq_valid (_txq_io_deq_valid), .io_deq_bits (_txq_io_deq_bits), .io_count (_txq_io_count) ); // @[UART.scala:130:19] UARTRx rxm ( // @[UART.scala:132:19] .clock (clock), .reset (reset), .io_en (rxen), // @[UART.scala:142:21] .io_in (ioNodeOut_rxd), // @[MixedNode.scala:542:17] .io_out_valid (_rxm_io_out_valid), .io_out_bits (_rxm_io_out_bits), .io_div (div) // @[UART.scala:135:20] ); // @[UART.scala:132:19] Queue8_UInt8_1 rxq ( // @[UART.scala:133:19] .clock (clock), .reset (reset), .io_enq_valid (_rxm_io_out_valid), // @[UART.scala:132:19] .io_enq_bits (_rxm_io_out_bits), // @[UART.scala:132:19] .io_deq_ready (out_f_roready_3), // @[RegisterRouter.scala:87:24] .io_deq_valid (_rxq_io_deq_valid), .io_deq_bits (_rxq_io_deq_bits), .io_count (_rxq_io_count) ); // @[UART.scala:133:19] assign auto_int_xing_out_sync_0 = auto_int_xing_out_sync_0_0; // @[UART.scala:127:25] assign auto_control_xing_in_a_ready = auto_control_xing_in_a_ready_0; // @[UART.scala:127:25] assign auto_control_xing_in_d_valid = auto_control_xing_in_d_valid_0; // @[UART.scala:127:25] assign auto_control_xing_in_d_bits_opcode = auto_control_xing_in_d_bits_opcode_0; // @[UART.scala:127:25] assign auto_control_xing_in_d_bits_size = auto_control_xing_in_d_bits_size_0; // @[UART.scala:127:25] assign auto_control_xing_in_d_bits_source = auto_control_xing_in_d_bits_source_0; // @[UART.scala:127:25] assign auto_control_xing_in_d_bits_data = auto_control_xing_in_d_bits_data_0; // @[UART.scala:127:25] assign auto_io_out_txd = auto_io_out_txd_0; // @[UART.scala:127:25] endmodule

Generate the Verilog code corresponding to the following Chisel files. File ShiftReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ // Similar to the Chisel ShiftRegister but allows the user to suggest a // name to the registers that get instantiated, and // to provide a reset value. object ShiftRegInit { def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T = (0 until n).foldRight(in) { case (i, next) => { val r = RegNext(next, init) name.foreach { na => r.suggestName(s"${na}_${i}") } r } } } /** These wrap behavioral * shift registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * The different types vary in their reset behavior: * AsyncResetShiftReg -- Asynchronously reset register array * A W(width) x D(depth) sized array is constructed from D instantiations of a * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg, * but only used for timing applications */ abstract class AbstractPipelineReg(w: Int = 1) extends Module { val io = IO(new Bundle { val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) } ) } object AbstractPipelineReg { def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = { val chain = Module(gen) name.foreach{ chain.suggestName(_) } chain.io.d := in.asUInt chain.io.q.asTypeOf(in) } } class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) { require(depth > 0, "Depth must be greater than 0.") override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}" val chain = List.tabulate(depth) { i => Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}") } chain.last.io.d := io.d chain.last.io.en := true.B (chain.init zip chain.tail).foreach { case (sink, source) => sink.io.d := source.io.q sink.io.en := true.B } io.q := chain.head.io.q } object AsyncResetShiftReg { def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name) def apply [T <: Data](in: T, depth: Int, name: Option[String]): T = apply(in, depth, 0, name) def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T = apply(in, depth, init.litValue.toInt, name) def apply [T <: Data](in: T, depth: Int, init: T): T = apply (in, depth, init.litValue.toInt, None) } File AsyncQueue.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ case class AsyncQueueParams( depth: Int = 8, sync: Int = 3, safe: Boolean = true, // If safe is true, then effort is made to resynchronize the crossing indices when either side is reset. // This makes it safe/possible to reset one side of the crossing (but not the other) when the queue is empty. narrow: Boolean = false) // If narrow is true then the read mux is moved to the source side of the crossing. // This reduces the number of level shifters in the case where the clock crossing is also a voltage crossing, // at the expense of a combinational path from the sink to the source and back to the sink. { require (depth > 0 && isPow2(depth)) require (sync >= 2) val bits = log2Ceil(depth) val wires = if (narrow) 1 else depth } object AsyncQueueParams { // When there is only one entry, we don't need narrow. def singleton(sync: Int = 3, safe: Boolean = true) = AsyncQueueParams(1, sync, safe, false) } class AsyncBundleSafety extends Bundle { val ridx_valid = Input (Bool()) val widx_valid = Output(Bool()) val source_reset_n = Output(Bool()) val sink_reset_n = Input (Bool()) } class AsyncBundle[T <: Data](private val gen: T, val params: AsyncQueueParams = AsyncQueueParams()) extends Bundle { // Data-path synchronization val mem = Output(Vec(params.wires, gen)) val ridx = Input (UInt((params.bits+1).W)) val widx = Output(UInt((params.bits+1).W)) val index = params.narrow.option(Input(UInt(params.bits.W))) // Signals used to self-stabilize a safe AsyncQueue val safe = params.safe.option(new AsyncBundleSafety) } object GrayCounter { def apply(bits: Int, increment: Bool = true.B, clear: Bool = false.B, name: String = "binary"): UInt = { val incremented = Wire(UInt(bits.W)) val binary = RegNext(next=incremented, init=0.U).suggestName(name) incremented := Mux(clear, 0.U, binary + increment.asUInt) incremented ^ (incremented >> 1) } } class AsyncValidSync(sync: Int, desc: String) extends RawModule { val io = IO(new Bundle { val in = Input(Bool()) val out = Output(Bool()) }) val clock = IO(Input(Clock())) val reset = IO(Input(AsyncReset())) withClockAndReset(clock, reset){ io.out := AsyncResetSynchronizerShiftReg(io.in, sync, Some(desc)) } } class AsyncQueueSource[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module { override def desiredName = s"AsyncQueueSource_${gen.typeName}" val io = IO(new Bundle { // These come from the source domain val enq = Flipped(Decoupled(gen)) // These cross to the sink clock domain val async = new AsyncBundle(gen, params) }) val bits = params.bits val sink_ready = WireInit(true.B) val mem = Reg(Vec(params.depth, gen)) // This does NOT need to be reset at all. val widx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.enq.fire, !sink_ready, "widx_bin")) val ridx = AsyncResetSynchronizerShiftReg(io.async.ridx, params.sync, Some("ridx_gray")) val ready = sink_ready && widx =/= (ridx ^ (params.depth | params.depth >> 1).U) val index = if (bits == 0) 0.U else io.async.widx(bits-1, 0) ^ (io.async.widx(bits, bits) << (bits-1)) when (io.enq.fire) { mem(index) := io.enq.bits } val ready_reg = withReset(reset.asAsyncReset)(RegNext(next=ready, init=false.B).suggestName("ready_reg")) io.enq.ready := ready_reg && sink_ready val widx_reg = withReset(reset.asAsyncReset)(RegNext(next=widx, init=0.U).suggestName("widx_gray")) io.async.widx := widx_reg io.async.index match { case Some(index) => io.async.mem(0) := mem(index) case None => io.async.mem := mem } io.async.safe.foreach { sio => val source_valid_0 = Module(new AsyncValidSync(params.sync, "source_valid_0")) val source_valid_1 = Module(new AsyncValidSync(params.sync, "source_valid_1")) val sink_extend = Module(new AsyncValidSync(params.sync, "sink_extend")) val sink_valid = Module(new AsyncValidSync(params.sync, "sink_valid")) source_valid_0.reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset source_valid_1.reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset sink_extend .reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset sink_valid .reset := reset.asAsyncReset source_valid_0.clock := clock source_valid_1.clock := clock sink_extend .clock := clock sink_valid .clock := clock source_valid_0.io.in := true.B source_valid_1.io.in := source_valid_0.io.out sio.widx_valid := source_valid_1.io.out sink_extend.io.in := sio.ridx_valid sink_valid.io.in := sink_extend.io.out sink_ready := sink_valid.io.out sio.source_reset_n := !reset.asBool // Assert that if there is stuff in the queue, then reset cannot happen // Impossible to write because dequeue can occur on the receiving side, // then reset allowed to happen, but write side cannot know that dequeue // occurred. // TODO: write some sort of sanity check assertion for users // that denote don't reset when there is activity // assert (!(reset || !sio.sink_reset_n) || !io.enq.valid, "Enqueue while sink is reset and AsyncQueueSource is unprotected") // assert (!reset_rise || prev_idx_match.asBool, "Sink reset while AsyncQueueSource not empty") } } class AsyncQueueSink[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module { override def desiredName = s"AsyncQueueSink_${gen.typeName}" val io = IO(new Bundle { // These come from the sink domain val deq = Decoupled(gen) // These cross to the source clock domain val async = Flipped(new AsyncBundle(gen, params)) }) val bits = params.bits val source_ready = WireInit(true.B) val ridx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.deq.fire, !source_ready, "ridx_bin")) val widx = AsyncResetSynchronizerShiftReg(io.async.widx, params.sync, Some("widx_gray")) val valid = source_ready && ridx =/= widx // The mux is safe because timing analysis ensures ridx has reached the register // On an ASIC, changes to the unread location cannot affect the selected value // On an FPGA, only one input changes at a time => mem updates don't cause glitches // The register only latches when the selected valued is not being written val index = if (bits == 0) 0.U else ridx(bits-1, 0) ^ (ridx(bits, bits) << (bits-1)) io.async.index.foreach { _ := index } // This register does not NEED to be reset, as its contents will not // be considered unless the asynchronously reset deq valid register is set. // It is possible that bits latches when the source domain is reset / has power cut // This is safe, because isolation gates brought mem low before the zeroed widx reached us val deq_bits_nxt = io.async.mem(if (params.narrow) 0.U else index) io.deq.bits := ClockCrossingReg(deq_bits_nxt, en = valid, doInit = false, name = Some("deq_bits_reg")) val valid_reg = withReset(reset.asAsyncReset)(RegNext(next=valid, init=false.B).suggestName("valid_reg")) io.deq.valid := valid_reg && source_ready val ridx_reg = withReset(reset.asAsyncReset)(RegNext(next=ridx, init=0.U).suggestName("ridx_gray")) io.async.ridx := ridx_reg io.async.safe.foreach { sio => val sink_valid_0 = Module(new AsyncValidSync(params.sync, "sink_valid_0")) val sink_valid_1 = Module(new AsyncValidSync(params.sync, "sink_valid_1")) val source_extend = Module(new AsyncValidSync(params.sync, "source_extend")) val source_valid = Module(new AsyncValidSync(params.sync, "source_valid")) sink_valid_0 .reset := (reset.asBool || !sio.source_reset_n).asAsyncReset sink_valid_1 .reset := (reset.asBool || !sio.source_reset_n).asAsyncReset source_extend.reset := (reset.asBool || !sio.source_reset_n).asAsyncReset source_valid .reset := reset.asAsyncReset sink_valid_0 .clock := clock sink_valid_1 .clock := clock source_extend.clock := clock source_valid .clock := clock sink_valid_0.io.in := true.B sink_valid_1.io.in := sink_valid_0.io.out sio.ridx_valid := sink_valid_1.io.out source_extend.io.in := sio.widx_valid source_valid.io.in := source_extend.io.out source_ready := source_valid.io.out sio.sink_reset_n := !reset.asBool // TODO: write some sort of sanity check assertion for users // that denote don't reset when there is activity // // val reset_and_extend = !source_ready || !sio.source_reset_n || reset.asBool // val reset_and_extend_prev = RegNext(reset_and_extend, true.B) // val reset_rise = !reset_and_extend_prev && reset_and_extend // val prev_idx_match = AsyncResetReg(updateData=(io.async.widx===io.async.ridx), resetData=0) // assert (!reset_rise || prev_idx_match.asBool, "Source reset while AsyncQueueSink not empty") } } object FromAsyncBundle { // Sometimes it makes sense for the sink to have different sync than the source def apply[T <: Data](x: AsyncBundle[T]): DecoupledIO[T] = apply(x, x.params.sync) def apply[T <: Data](x: AsyncBundle[T], sync: Int): DecoupledIO[T] = { val sink = Module(new AsyncQueueSink(chiselTypeOf(x.mem(0)), x.params.copy(sync = sync))) sink.io.async <> x sink.io.deq } } object ToAsyncBundle { def apply[T <: Data](x: ReadyValidIO[T], params: AsyncQueueParams = AsyncQueueParams()): AsyncBundle[T] = { val source = Module(new AsyncQueueSource(chiselTypeOf(x.bits), params)) source.io.enq <> x source.io.async } } class AsyncQueue[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Crossing[T] { val io = IO(new CrossingIO(gen)) val source = withClockAndReset(io.enq_clock, io.enq_reset) { Module(new AsyncQueueSource(gen, params)) } val sink = withClockAndReset(io.deq_clock, io.deq_reset) { Module(new AsyncQueueSink (gen, params)) } source.io.enq <> io.enq io.deq <> sink.io.deq sink.io.async <> source.io.async } File LazyModuleImp.scala: package org.chipsalliance.diplomacy.lazymodule import chisel3.{withClockAndReset, Module, RawModule, Reset, _} import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo} import firrtl.passes.InlineAnnotation import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.nodes.Dangle import scala.collection.immutable.SortedMap /** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]]. * * This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy. */ sealed trait LazyModuleImpLike extends RawModule { /** [[LazyModule]] that contains this instance. */ val wrapper: LazyModule /** IOs that will be automatically "punched" for this instance. */ val auto: AutoBundle /** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */ protected[diplomacy] val dangles: Seq[Dangle] // [[wrapper.module]] had better not be accessed while LazyModules are still being built! require( LazyModule.scope.isEmpty, s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}" ) /** Set module name. Defaults to the containing LazyModule's desiredName. */ override def desiredName: String = wrapper.desiredName suggestName(wrapper.suggestedName) /** [[Parameters]] for chisel [[Module]]s. */ implicit val p: Parameters = wrapper.p /** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and * submodules. */ protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = { // 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]], // 2. return [[Dangle]]s from each module. val childDangles = wrapper.children.reverse.flatMap { c => implicit val sourceInfo: SourceInfo = c.info c.cloneProto.map { cp => // If the child is a clone, then recursively set cloneProto of its children as well def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = { require(bases.size == clones.size) (bases.zip(clones)).map { case (l, r) => require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}") l.cloneProto = Some(r) assignCloneProtos(l.children, r.children) } } assignCloneProtos(c.children, cp.children) // Clone the child module as a record, and get its [[AutoBundle]] val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName) val clonedAuto = clone("auto").asInstanceOf[AutoBundle] // Get the empty [[Dangle]]'s of the cloned child val rawDangles = c.cloneDangles() require(rawDangles.size == clonedAuto.elements.size) // Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) } dangles }.getOrElse { // For non-clones, instantiate the child module val mod = try { Module(c.module) } catch { case e: ChiselException => { println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}") throw e } } mod.dangles } } // Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]]. // This will result in a sequence of [[Dangle]] from these [[BaseNode]]s. val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate()) // Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]] val allDangles = nodeDangles ++ childDangles // Group [[allDangles]] by their [[source]]. val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*) // For each [[source]] set of [[Dangle]]s of size 2, ensure that these // can be connected as a source-sink pair (have opposite flipped value). // Make the connection and mark them as [[done]]. val done = Set() ++ pairing.values.filter(_.size == 2).map { case Seq(a, b) => require(a.flipped != b.flipped) // @todo <> in chisel3 makes directionless connection. if (a.flipped) { a.data <> b.data } else { b.data <> a.data } a.source case _ => None } // Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module. val forward = allDangles.filter(d => !done(d.source)) // Generate [[AutoBundle]] IO from [[forward]]. val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*)) // Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]] val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) => if (d.flipped) { d.data <> io } else { io <> d.data } d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name) } // Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]]. wrapper.inModuleBody.reverse.foreach { _() } if (wrapper.shouldBeInlined) { chisel3.experimental.annotate(new ChiselAnnotation { def toFirrtl = InlineAnnotation(toNamed) }) } // Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]]. (auto, dangles) } } /** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike { /** Instantiate hardware of this `Module`. */ val (auto, dangles) = instantiate() } /** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike { // These wires are the default clock+reset for all LazyModule children. // It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the // [[LazyRawModuleImp]] children. // Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly. /** drive clock explicitly. */ val childClock: Clock = Wire(Clock()) /** drive reset explicitly. */ val childReset: Reset = Wire(Reset()) // the default is that these are disabled childClock := false.B.asClock childReset := chisel3.DontCare def provideImplicitClockToLazyChildren: Boolean = false val (auto, dangles) = if (provideImplicitClockToLazyChildren) { withClockAndReset(childClock, childReset) { instantiate() } } else { instantiate() } } File Debug.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.devices.debug import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.amba.apb.{APBFanout, APBToTL} import freechips.rocketchip.devices.debug.systembusaccess.{SBToTL, SystemBusAccessModule} import freechips.rocketchip.devices.tilelink.{DevNullParams, TLBusBypass, TLError} import freechips.rocketchip.diplomacy.{AddressSet, BufferParams} import freechips.rocketchip.resources.{Description, Device, Resource, ResourceBindings, ResourceString, SimpleDevice} import freechips.rocketchip.interrupts.{IntNexusNode, IntSinkParameters, IntSinkPortParameters, IntSourceParameters, IntSourcePortParameters, IntSyncCrossingSource, IntSyncIdentityNode} import freechips.rocketchip.regmapper.{RegField, RegFieldAccessType, RegFieldDesc, RegFieldGroup, RegFieldWrType, RegReadFn, RegWriteFn} import freechips.rocketchip.rocket.{CSRs, Instructions} import freechips.rocketchip.tile.MaxHartIdBits import freechips.rocketchip.tilelink.{TLAsyncCrossingSink, TLAsyncCrossingSource, TLBuffer, TLRegisterNode, TLXbar} import freechips.rocketchip.util.{Annotated, AsyncBundle, AsyncQueueParams, AsyncResetSynchronizerShiftReg, FromAsyncBundle, ParameterizedBundle, ResetSynchronizerShiftReg, ToAsyncBundle} import freechips.rocketchip.util.SeqBoolBitwiseOps import freechips.rocketchip.util.SeqToAugmentedSeq import freechips.rocketchip.util.BooleanToAugmentedBoolean object DsbBusConsts { def sbAddrWidth = 12 def sbIdWidth = 10 } object DsbRegAddrs{ // These are used by the ROM. def HALTED = 0x100 def GOING = 0x104 def RESUMING = 0x108 def EXCEPTION = 0x10C def WHERETO = 0x300 // This needs to be aligned for up to lq/sq // This shows up in HartInfo, and needs to be aligned // to enable up to LQ/SQ instructions. def DATA = 0x380 // We want DATA to immediately follow PROGBUF so that we can // use them interchangeably. Leave another slot if there is an // implicit ebreak. def PROGBUF(cfg:DebugModuleParams) = { val tmp = DATA - (cfg.nProgramBufferWords * 4) if (cfg.hasImplicitEbreak) (tmp - 4) else tmp } // This is unused if hasImpEbreak is false, and just points to the end of the PROGBUF. def IMPEBREAK(cfg: DebugModuleParams) = { DATA - 4 } // We want abstract to be immediately before PROGBUF // because we auto-generate 2 (or 5) instructions. def ABSTRACT(cfg:DebugModuleParams) = PROGBUF(cfg) - (cfg.nAbstractInstructions * 4) def FLAGS = 0x400 def ROMBASE = 0x800 } /** Enumerations used both in the hardware * and in the configuration specification. */ object DebugModuleAccessType extends scala.Enumeration { type DebugModuleAccessType = Value val Access8Bit, Access16Bit, Access32Bit, Access64Bit, Access128Bit = Value } object DebugAbstractCommandError extends scala.Enumeration { type DebugAbstractCommandError = Value val Success, ErrBusy, ErrNotSupported, ErrException, ErrHaltResume = Value } object DebugAbstractCommandType extends scala.Enumeration { type DebugAbstractCommandType = Value val AccessRegister, QuickAccess = Value } /** Parameters exposed to the top-level design, set based on * external requirements, etc. * * This object checks that the parameters conform to the * full specification. The implementation which receives this * object can perform more checks on what that implementation * actually supports. * @param nComponents Number of components to support debugging. * @param baseAddress Base offest for debugEntry and debugException * @param nDMIAddrSize Size of the Debug Bus Address * @param nAbstractDataWords Number of 32-bit words for Abstract Commands * @param nProgamBufferWords Number of 32-bit words for Program Buffer * @param hasBusMaster Whether or not a bus master should be included * @param clockGate Whether or not to use dmactive as the clockgate for debug module * @param maxSupportedSBAccess Maximum transaction size supported by System Bus Access logic. * @param supportQuickAccess Whether or not to support the quick access command. * @param supportHartArray Whether or not to implement the hart array register (if >1 hart). * @param nHaltGroups Number of halt groups * @param nExtTriggers Number of external triggers * @param hasHartResets Feature to reset all the currently selected harts * @param hasImplicitEbreak There is an additional RO program buffer word containing an ebreak * @param crossingHasSafeReset Include "safe" logic in Async Crossings so that only one side needs to be reset. */ case class DebugModuleParams ( baseAddress : BigInt = BigInt(0), nDMIAddrSize : Int = 7, nProgramBufferWords: Int = 16, nAbstractDataWords : Int = 4, nScratch : Int = 1, hasBusMaster : Boolean = false, clockGate : Boolean = true, maxSupportedSBAccess : Int = 32, supportQuickAccess : Boolean = false, supportHartArray : Boolean = true, nHaltGroups : Int = 1, nExtTriggers : Int = 0, hasHartResets : Boolean = false, hasImplicitEbreak : Boolean = false, hasAuthentication : Boolean = false, crossingHasSafeReset : Boolean = true ) { require ((nDMIAddrSize >= 7) && (nDMIAddrSize <= 32), s"Legal DMIAddrSize is 7-32, not ${nDMIAddrSize}") require ((nAbstractDataWords > 0) && (nAbstractDataWords <= 16), s"Legal nAbstractDataWords is 0-16, not ${nAbstractDataWords}") require ((nProgramBufferWords >= 0) && (nProgramBufferWords <= 16), s"Legal nProgramBufferWords is 0-16, not ${nProgramBufferWords}") require (nHaltGroups < 32, s"Legal nHaltGroups is 0-31, not ${nHaltGroups}") require (nExtTriggers <= 16, s"Legal nExtTriggers is 0-16, not ${nExtTriggers}") if (supportQuickAccess) { // TODO: Check that quick access requirements are met. } def address = AddressSet(baseAddress, 0xFFF) /** the base address of DM */ def atzero = (baseAddress == 0) /** The number of generated instructions * * When the base address is not zero, we need more instruction also, * more dscratch registers) to load/store memory mapped data register * because they may no longer be directly addressible with x0 + 12-bit imm */ def nAbstractInstructions = if (atzero) 2 else 5 def debugEntry: BigInt = baseAddress + 0x800 def debugException: BigInt = baseAddress + 0x808 def nDscratch: Int = if (atzero) 1 else 2 } object DefaultDebugModuleParams { def apply(xlen:Int /*TODO , val configStringAddr: Int*/): DebugModuleParams = { new DebugModuleParams().copy( nAbstractDataWords = (if (xlen == 32) 1 else if (xlen == 64) 2 else 4), maxSupportedSBAccess = xlen ) } } case object DebugModuleKey extends Field[Option[DebugModuleParams]](Some(DebugModuleParams())) /** Functional parameters exposed to the design configuration. * * hartIdToHartSel: For systems where hart ids are not 1:1 with hartsel, provide the mapping. * hartSelToHartId: Provide inverse mapping of the above */ case class DebugModuleHartSelFuncs ( hartIdToHartSel : (UInt) => UInt = (x:UInt) => x, hartSelToHartId : (UInt) => UInt = (x:UInt) => x ) case object DebugModuleHartSelKey extends Field(DebugModuleHartSelFuncs()) class DebugExtTriggerOut (val nExtTriggers: Int) extends Bundle { val req = Output(UInt(nExtTriggers.W)) val ack = Input(UInt(nExtTriggers.W)) } class DebugExtTriggerIn (val nExtTriggers: Int) extends Bundle { val req = Input(UInt(nExtTriggers.W)) val ack = Output(UInt(nExtTriggers.W)) } class DebugExtTriggerIO () (implicit val p: Parameters) extends ParameterizedBundle()(p) { val out = new DebugExtTriggerOut(p(DebugModuleKey).get.nExtTriggers) val in = new DebugExtTriggerIn (p(DebugModuleKey).get.nExtTriggers) } class DebugAuthenticationIO () (implicit val p: Parameters) extends ParameterizedBundle()(p) { val dmactive = Output(Bool()) val dmAuthWrite = Output(Bool()) val dmAuthRead = Output(Bool()) val dmAuthWdata = Output(UInt(32.W)) val dmAuthBusy = Input(Bool()) val dmAuthRdata = Input(UInt(32.W)) val dmAuthenticated = Input(Bool()) } // ***************************************** // Module Interfaces // // ***************************************** /** Control signals for Inner, generated in Outer * {{{ * run control: resumreq, ackhavereset, halt-on-reset mask * hart select: hasel, hartsel and the hart array mask * }}} */ class DebugInternalBundle (val nComponents: Int)(implicit val p: Parameters) extends ParameterizedBundle()(p) { /** resume request */ val resumereq = Bool() /** hart select */ val hartsel = UInt(10.W) /** reset acknowledge */ val ackhavereset = Bool() /** hart array enable */ val hasel = Bool() /** hart array mask */ val hamask = Vec(nComponents, Bool()) /** halt-on-reset mask */ val hrmask = Vec(nComponents, Bool()) } /** structure for top-level Debug Module signals which aren't the bus interfaces. */ class DebugCtrlBundle (nComponents: Int)(implicit val p: Parameters) extends ParameterizedBundle()(p) { /** debug availability status for all harts */ val debugUnavail = Input(Vec(nComponents, Bool())) /** reset signal * * for every part of the hardware platform, * including every hart, except for the DM and any * logic required to access the DM */ val ndreset = Output(Bool()) /** reset signal for the DM itself */ val dmactive = Output(Bool()) /** dmactive acknowlege */ val dmactiveAck = Input(Bool()) } // ***************************************** // Debug Module // // ***************************************** /** Parameterized version of the Debug Module defined in the * RISC-V Debug Specification * * DebugModule is a slave to two asynchronous masters: * The Debug Bus (DMI) -- This is driven by an external debugger * * The System Bus -- This services requests from the cores. Generally * this interface should only be active at the request * of the debugger, but the Debug Module may also * provide the default MTVEC since it is mapped * to address 0x0. * * DebugModule is responsible for control registers and RAM, and * Debug ROM. It runs partially off of the dmiClk (e.g. TCK) and * the TL clock. Therefore, it is divided into "Outer" portion (running * off dmiClock and dmiReset) and "Inner" (running off tl_clock and tl_reset). * This allows DMCONTROL.haltreq, hartsel, hasel, hawindowsel, hawindow, dmactive, * and ndreset to be modified even while the Core is in reset or not being clocked. * Not all reads from the Debugger to the Debug Module will actually complete * in these scenarios either, they will just block until tl_clock and tl_reset * allow them to complete. This is not strictly necessary for * proper debugger functionality. */ // Local reg mapper function : Notify when written, but give the value as well. object WNotifyWire { def apply(n: Int, value: UInt, set: Bool, name: String, desc: String) : RegField = { RegField(n, 0.U, RegWriteFn((valid, data) => { set := valid value := data true.B }), Some(RegFieldDesc(name = name, desc = desc, access = RegFieldAccessType.W))) } } // Local reg mapper function : Notify when accessed either as read or write. object RWNotify { def apply (n: Int, rVal: UInt, wVal: UInt, rNotify: Bool, wNotify: Bool, desc: Option[RegFieldDesc] = None): RegField = { RegField(n, RegReadFn ((ready) => {rNotify := ready ; (true.B, rVal)}), RegWriteFn((valid, data) => { wNotify := valid when (valid) {wVal := data} true.B } ), desc) } } // Local reg mapper function : Notify with value when written, take read input as presented. // This allows checking or correcting the write value before storing it in the register field. object WNotifyVal { def apply(n: Int, rVal: UInt, wVal: UInt, wNotify: Bool, desc: RegFieldDesc): RegField = { RegField(n, rVal, RegWriteFn((valid, data) => { wNotify := valid wVal := data true.B } ), desc) } } class TLDebugModuleOuter(device: Device)(implicit p: Parameters) extends LazyModule { // For Shorter Register Names import DMI_RegAddrs._ val cfg = p(DebugModuleKey).get val intnode = IntNexusNode( sourceFn = { _ => IntSourcePortParameters(Seq(IntSourceParameters(1, Seq(Resource(device, "int"))))) }, sinkFn = { _ => IntSinkPortParameters(Seq(IntSinkParameters())) }, outputRequiresInput = false) val dmiNode = TLRegisterNode ( address = AddressSet.misaligned(DMI_DMCONTROL << 2, 4) ++ AddressSet.misaligned(DMI_HARTINFO << 2, 4) ++ AddressSet.misaligned(DMI_HAWINDOWSEL << 2, 4) ++ AddressSet.misaligned(DMI_HAWINDOW << 2, 4), device = device, beatBytes = 4, executable = false ) lazy val module = new Impl class Impl extends LazyModuleImp(this) { require (intnode.edges.in.size == 0, "Debug Module does not accept interrupts") val nComponents = intnode.out.size def getNComponents = () => nComponents val supportHartArray = cfg.supportHartArray && (nComponents > 1) // no hart array if only one hart val io = IO(new Bundle { /** structure for top-level Debug Module signals which aren't the bus interfaces. */ val ctrl = (new DebugCtrlBundle(nComponents)) /** control signals for Inner, generated in Outer */ val innerCtrl = new DecoupledIO(new DebugInternalBundle(nComponents)) /** debug interruption from Inner to Outer * * contains 2 type of debug interruption causes: * - halt group * - halt-on-reset */ val hgDebugInt = Input(Vec(nComponents, Bool())) /** hart reset request to core */ val hartResetReq = cfg.hasHartResets.option(Output(Vec(nComponents, Bool()))) /** authentication support */ val dmAuthenticated = cfg.hasAuthentication.option(Input(Bool())) }) val omRegMap = withReset(reset.asAsyncReset) { // FIXME: Instead of casting reset to ensure it is Async, assert/require reset.Type == AsyncReset (when this feature is available) val dmAuthenticated = io.dmAuthenticated.map( dma => ResetSynchronizerShiftReg(in=dma, sync=3, name=Some("dmAuthenticated_sync"))).getOrElse(true.B) //----DMCONTROL (The whole point of 'Outer' is to maintain this register on dmiClock (e.g. TCK) domain, so that it // can be written even if 'Inner' is not being clocked or is in reset. This allows halting // harts while the rest of the system is in reset. It doesn't really allow any other // register accesses, which will keep returning 'busy' to the debugger interface. val DMCONTROLReset = WireInit(0.U.asTypeOf(new DMCONTROLFields())) val DMCONTROLNxt = WireInit(0.U.asTypeOf(new DMCONTROLFields())) val DMCONTROLReg = RegNext(next=DMCONTROLNxt, init=0.U.asTypeOf(DMCONTROLNxt)).suggestName("DMCONTROLReg") val hartsel_mask = if (nComponents > 1) ((1 << p(MaxHartIdBits)) - 1).U else 0.U val DMCONTROLWrData = WireInit(0.U.asTypeOf(new DMCONTROLFields())) val dmactiveWrEn = WireInit(false.B) val ndmresetWrEn = WireInit(false.B) val clrresethaltreqWrEn = WireInit(false.B) val setresethaltreqWrEn = WireInit(false.B) val hartselloWrEn = WireInit(false.B) val haselWrEn = WireInit(false.B) val ackhaveresetWrEn = WireInit(false.B) val hartresetWrEn = WireInit(false.B) val resumereqWrEn = WireInit(false.B) val haltreqWrEn = WireInit(false.B) val dmactive = DMCONTROLReg.dmactive DMCONTROLNxt := DMCONTROLReg when (~dmactive) { DMCONTROLNxt := DMCONTROLReset } .otherwise { when (dmAuthenticated && ndmresetWrEn) { DMCONTROLNxt.ndmreset := DMCONTROLWrData.ndmreset } when (dmAuthenticated && hartselloWrEn) { DMCONTROLNxt.hartsello := DMCONTROLWrData.hartsello & hartsel_mask} when (dmAuthenticated && haselWrEn) { DMCONTROLNxt.hasel := DMCONTROLWrData.hasel } when (dmAuthenticated && hartresetWrEn) { DMCONTROLNxt.hartreset := DMCONTROLWrData.hartreset } when (dmAuthenticated && haltreqWrEn) { DMCONTROLNxt.haltreq := DMCONTROLWrData.haltreq } } // Put this last to override its own effects. when (dmactiveWrEn) { DMCONTROLNxt.dmactive := DMCONTROLWrData.dmactive } //----HARTINFO // DATA registers are mapped to memory. The dataaddr field of HARTINFO has only // 12 bits and assumes the DM base is 0. If not at 0, then HARTINFO reads as 0 // (implying nonexistence according to the Debug Spec). val HARTINFORdData = WireInit(0.U.asTypeOf(new HARTINFOFields())) if (cfg.atzero) when (dmAuthenticated) { HARTINFORdData.dataaccess := true.B HARTINFORdData.datasize := cfg.nAbstractDataWords.U HARTINFORdData.dataaddr := DsbRegAddrs.DATA.U HARTINFORdData.nscratch := cfg.nScratch.U } //-------------------------------------------------------------- // Hart array mask and window // hamask is hart array mask(1 bit per component), which doesn't include the hart selected by dmcontrol.hartsello // HAWINDOWSEL selects a 32-bit slice of HAMASK to be visible for read/write in HAWINDOW //-------------------------------------------------------------- val hamask = WireInit(VecInit(Seq.fill(nComponents) {false.B} )) def haWindowSize = 32 // The following need to be declared even if supportHartArray is false due to reference // at compile time by dmiNode.regmap val HAWINDOWSELWrData = WireInit(0.U.asTypeOf(new HAWINDOWSELFields())) val HAWINDOWSELWrEn = WireInit(false.B) val HAWINDOWRdData = WireInit(0.U.asTypeOf(new HAWINDOWFields())) val HAWINDOWWrData = WireInit(0.U.asTypeOf(new HAWINDOWFields())) val HAWINDOWWrEn = WireInit(false.B) /** whether the hart is selected */ def hartSelected(hart: Int): Bool = { ((io.innerCtrl.bits.hartsel === hart.U) || (if (supportHartArray) io.innerCtrl.bits.hasel && io.innerCtrl.bits.hamask(hart) else false.B)) } val HAWINDOWSELNxt = WireInit(0.U.asTypeOf(new HAWINDOWSELFields())) val HAWINDOWSELReg = RegNext(next=HAWINDOWSELNxt, init=0.U.asTypeOf(HAWINDOWSELNxt)) if (supportHartArray) { val HAWINDOWSELReset = WireInit(0.U.asTypeOf(new HAWINDOWSELFields())) HAWINDOWSELNxt := HAWINDOWSELReg when (~dmactive || ~dmAuthenticated) { HAWINDOWSELNxt := HAWINDOWSELReset } .otherwise { when (HAWINDOWSELWrEn) { // Unneeded upper bits of HAWINDOWSEL are tied to 0. Entire register is 0 if all harts fit in one window if (nComponents > haWindowSize) { HAWINDOWSELNxt.hawindowsel := HAWINDOWSELWrData.hawindowsel & ((1 << (log2Up(nComponents) - 5)) - 1).U } else { HAWINDOWSELNxt.hawindowsel := 0.U } } } val numHAMASKSlices = ((nComponents - 1)/haWindowSize)+1 HAWINDOWRdData.maskdata := 0.U // default, overridden below // for each slice,use a hamaskReg to store the selection info for (ii <- 0 until numHAMASKSlices) { val sliceMask = if (nComponents > ((ii*haWindowSize) + haWindowSize-1)) (BigInt(1) << haWindowSize) - 1 // All harts in this slice exist else (BigInt(1)<<(nComponents - (ii*haWindowSize))) - 1 // Partial last slice val HAMASKRst = WireInit(0.U.asTypeOf(new HAWINDOWFields())) val HAMASKNxt = WireInit(0.U.asTypeOf(new HAWINDOWFields())) val HAMASKReg = RegNext(next=HAMASKNxt, init=0.U.asTypeOf(HAMASKNxt)) when (ii.U === HAWINDOWSELReg.hawindowsel) { HAWINDOWRdData.maskdata := HAMASKReg.asUInt & sliceMask.U } HAMASKNxt.maskdata := HAMASKReg.asUInt when (~dmactive || ~dmAuthenticated) { HAMASKNxt := HAMASKRst }.otherwise { when (HAWINDOWWrEn && (ii.U === HAWINDOWSELReg.hawindowsel)) { HAMASKNxt.maskdata := HAWINDOWWrData.maskdata } } // drive each slice of hamask with stored HAMASKReg or with new value being written for (jj <- 0 until haWindowSize) { if (((ii*haWindowSize) + jj) < nComponents) { val tempWrData = HAWINDOWWrData.maskdata.asBools val tempMaskReg = HAMASKReg.asUInt.asBools when (HAWINDOWWrEn && (ii.U === HAWINDOWSELReg.hawindowsel)) { hamask(ii*haWindowSize + jj) := tempWrData(jj) }.otherwise { hamask(ii*haWindowSize + jj) := tempMaskReg(jj) } } } } } //-------------------------------------------------------------- // Halt-on-reset // hrmaskReg is current set of harts that should halt-on-reset // Reset state (dmactive=0) is all zeroes // Bits are set by writing 1 to DMCONTROL.setresethaltreq // Bits are cleared by writing 1 to DMCONTROL.clrresethaltreq // Spec says if both are 1, then clrresethaltreq is executed // hrmask is the halt-on-reset mask which will be sent to inner //-------------------------------------------------------------- val hrmask = Wire(Vec(nComponents, Bool())) val hrmaskNxt = Wire(Vec(nComponents, Bool())) val hrmaskReg = RegNext(next=hrmaskNxt, init=0.U.asTypeOf(hrmaskNxt)).suggestName("hrmaskReg") hrmaskNxt := hrmaskReg for (component <- 0 until nComponents) { when (~dmactive || ~dmAuthenticated) { hrmaskNxt(component) := false.B }.elsewhen (clrresethaltreqWrEn && DMCONTROLWrData.clrresethaltreq && hartSelected(component)) { hrmaskNxt(component) := false.B }.elsewhen (setresethaltreqWrEn && DMCONTROLWrData.setresethaltreq && hartSelected(component)) { hrmaskNxt(component) := true.B } } hrmask := hrmaskNxt val dmControlRegFields = RegFieldGroup("dmcontrol", Some("debug module control register"), Seq( WNotifyVal(1, DMCONTROLReg.dmactive & io.ctrl.dmactiveAck, DMCONTROLWrData.dmactive, dmactiveWrEn, RegFieldDesc("dmactive", "debug module active", reset=Some(0))), WNotifyVal(1, DMCONTROLReg.ndmreset, DMCONTROLWrData.ndmreset, ndmresetWrEn, RegFieldDesc("ndmreset", "debug module reset output", reset=Some(0))), WNotifyVal(1, 0.U, DMCONTROLWrData.clrresethaltreq, clrresethaltreqWrEn, RegFieldDesc("clrresethaltreq", "clear reset halt request", reset=Some(0), access=RegFieldAccessType.W)), WNotifyVal(1, 0.U, DMCONTROLWrData.setresethaltreq, setresethaltreqWrEn, RegFieldDesc("setresethaltreq", "set reset halt request", reset=Some(0), access=RegFieldAccessType.W)), RegField(12), if (nComponents > 1) WNotifyVal(p(MaxHartIdBits), DMCONTROLReg.hartsello, DMCONTROLWrData.hartsello, hartselloWrEn, RegFieldDesc("hartsello", "hart select low", reset=Some(0))) else RegField(1), if (nComponents > 1) RegField(10-p(MaxHartIdBits)) else RegField(9), if (supportHartArray) WNotifyVal(1, DMCONTROLReg.hasel, DMCONTROLWrData.hasel, haselWrEn, RegFieldDesc("hasel", "hart array select", reset=Some(0))) else RegField(1), RegField(1), WNotifyVal(1, 0.U, DMCONTROLWrData.ackhavereset, ackhaveresetWrEn, RegFieldDesc("ackhavereset", "acknowledge reset", reset=Some(0), access=RegFieldAccessType.W)), if (cfg.hasHartResets) WNotifyVal(1, DMCONTROLReg.hartreset, DMCONTROLWrData.hartreset, hartresetWrEn, RegFieldDesc("hartreset", "hart reset request", reset=Some(0))) else RegField(1), WNotifyVal(1, 0.U, DMCONTROLWrData.resumereq, resumereqWrEn, RegFieldDesc("resumereq", "resume request", reset=Some(0), access=RegFieldAccessType.W)), WNotifyVal(1, DMCONTROLReg.haltreq, DMCONTROLWrData.haltreq, haltreqWrEn, // Spec says W, but maintaining previous behavior RegFieldDesc("haltreq", "halt request", reset=Some(0))) )) val hartinfoRegFields = RegFieldGroup("dmi_hartinfo", Some("hart information"), Seq( RegField.r(12, HARTINFORdData.dataaddr, RegFieldDesc("dataaddr", "data address", reset=Some(if (cfg.atzero) DsbRegAddrs.DATA else 0))), RegField.r(4, HARTINFORdData.datasize, RegFieldDesc("datasize", "number of DATA registers", reset=Some(if (cfg.atzero) cfg.nAbstractDataWords else 0))), RegField.r(1, HARTINFORdData.dataaccess, RegFieldDesc("dataaccess", "data access type", reset=Some(if (cfg.atzero) 1 else 0))), RegField(3), RegField.r(4, HARTINFORdData.nscratch, RegFieldDesc("nscratch", "number of scratch registers", reset=Some(if (cfg.atzero) cfg.nScratch else 0))) )) //-------------------------------------------------------------- // DMI register decoder for Outer //-------------------------------------------------------------- // regmap addresses are byte offsets from lowest address def DMI_DMCONTROL_OFFSET = 0 def DMI_HARTINFO_OFFSET = ((DMI_HARTINFO - DMI_DMCONTROL) << 2) def DMI_HAWINDOWSEL_OFFSET = ((DMI_HAWINDOWSEL - DMI_DMCONTROL) << 2) def DMI_HAWINDOW_OFFSET = ((DMI_HAWINDOW - DMI_DMCONTROL) << 2) val omRegMap = dmiNode.regmap( DMI_DMCONTROL_OFFSET -> dmControlRegFields, DMI_HARTINFO_OFFSET -> hartinfoRegFields, DMI_HAWINDOWSEL_OFFSET -> (if (supportHartArray && (nComponents > 32)) Seq( WNotifyVal(log2Up(nComponents)-5, HAWINDOWSELReg.hawindowsel, HAWINDOWSELWrData.hawindowsel, HAWINDOWSELWrEn, RegFieldDesc("hawindowsel", "hart array window select", reset=Some(0)))) else Nil), DMI_HAWINDOW_OFFSET -> (if (supportHartArray) Seq( WNotifyVal(if (nComponents > 31) 32 else nComponents, HAWINDOWRdData.maskdata, HAWINDOWWrData.maskdata, HAWINDOWWrEn, RegFieldDesc("hawindow", "hart array window", reset=Some(0), volatile=(nComponents > 32)))) else Nil) ) //-------------------------------------------------------------- // Interrupt Registers //-------------------------------------------------------------- val debugIntNxt = WireInit(VecInit(Seq.fill(nComponents) {false.B} )) val debugIntRegs = RegNext(next=debugIntNxt, init=0.U.asTypeOf(debugIntNxt)).suggestName("debugIntRegs") debugIntNxt := debugIntRegs val (intnode_out, _) = intnode.out.unzip for (component <- 0 until nComponents) { intnode_out(component)(0) := debugIntRegs(component) | io.hgDebugInt(component) } // sends debug interruption to Core when dmcs.haltreq is set, for (component <- 0 until nComponents) { when (~dmactive || ~dmAuthenticated) { debugIntNxt(component) := false.B }. otherwise { when (haltreqWrEn && ((DMCONTROLWrData.hartsello === component.U) || (if (supportHartArray) DMCONTROLWrData.hasel && hamask(component) else false.B))) { debugIntNxt(component) := DMCONTROLWrData.haltreq } } } // Halt request registers are set & cleared by writes to DMCONTROL.haltreq // resumereq also causes the core to execute a 'dret', // so resumereq is passed through to Inner. // hartsel/hasel/hamask must also be used by the DebugModule state machine, // so it is passed to Inner. // These registers ensure that requests to dmInner are not lost if inner clock isn't running or requests occur too close together. // If the innerCtrl async queue is not ready, the notification will be posted and held until ready is received. // Additional notifications that occur while one is already waiting update the pending data so that the last value written is sent. // Volatile events resumereq and ackhavereset are registered when they occur and remain pending until ready is received. val innerCtrlValid = Wire(Bool()) val innerCtrlValidReg = RegInit(false.B).suggestName("innerCtrlValidReg") val innerCtrlResumeReqReg = RegInit(false.B).suggestName("innerCtrlResumeReqReg") val innerCtrlAckHaveResetReg = RegInit(false.B).suggestName("innerCtrlAckHaveResetReg") innerCtrlValid := hartselloWrEn | resumereqWrEn | ackhaveresetWrEn | setresethaltreqWrEn | clrresethaltreqWrEn | haselWrEn | (HAWINDOWWrEn & supportHartArray.B) innerCtrlValidReg := io.innerCtrl.valid & ~io.innerCtrl.ready // Hold innerctrl request until the async queue accepts it innerCtrlResumeReqReg := io.innerCtrl.bits.resumereq & ~io.innerCtrl.ready // Hold resumereq until accepted innerCtrlAckHaveResetReg := io.innerCtrl.bits.ackhavereset & ~io.innerCtrl.ready // Hold ackhavereset until accepted io.innerCtrl.valid := innerCtrlValid | innerCtrlValidReg io.innerCtrl.bits.hartsel := Mux(hartselloWrEn, DMCONTROLWrData.hartsello, DMCONTROLReg.hartsello) io.innerCtrl.bits.resumereq := (resumereqWrEn & DMCONTROLWrData.resumereq) | innerCtrlResumeReqReg io.innerCtrl.bits.ackhavereset := (ackhaveresetWrEn & DMCONTROLWrData.ackhavereset) | innerCtrlAckHaveResetReg io.innerCtrl.bits.hrmask := hrmask if (supportHartArray) { io.innerCtrl.bits.hasel := Mux(haselWrEn, DMCONTROLWrData.hasel, DMCONTROLReg.hasel) io.innerCtrl.bits.hamask := hamask } else { io.innerCtrl.bits.hasel := DontCare io.innerCtrl.bits.hamask := DontCare } io.ctrl.ndreset := DMCONTROLReg.ndmreset io.ctrl.dmactive := DMCONTROLReg.dmactive // hart reset mechanism implementation if (cfg.hasHartResets) { val hartResetNxt = Wire(Vec(nComponents, Bool())) val hartResetReg = RegNext(next=hartResetNxt, init=0.U.asTypeOf(hartResetNxt)) for (component <- 0 until nComponents) { hartResetNxt(component) := DMCONTROLReg.hartreset & hartSelected(component) io.hartResetReq.get(component) := hartResetReg(component) } } omRegMap // FIXME: Remove this when withReset is removed }} } // wrap a Outer with a DMIToTL, derived by dmi clock & reset class TLDebugModuleOuterAsync(device: Device)(implicit p: Parameters) extends LazyModule { val cfg = p(DebugModuleKey).get val dmiXbar = LazyModule (new TLXbar(nameSuffix = Some("dmixbar"))) val dmi2tlOpt = (!p(ExportDebug).apb).option({ val dmi2tl = LazyModule(new DMIToTL()) dmiXbar.node := dmi2tl.node dmi2tl }) val apbNodeOpt = p(ExportDebug).apb.option({ val apb2tl = LazyModule(new APBToTL()) val apb2tlBuffer = LazyModule(new TLBuffer(BufferParams.pipe)) val dmTopAddr = (1 << cfg.nDMIAddrSize) << 2 val tlErrorParams = DevNullParams(AddressSet.misaligned(dmTopAddr, APBDebugConsts.apbDebugRegBase-dmTopAddr), maxAtomic=0, maxTransfer=4) val tlError = LazyModule(new TLError(tlErrorParams, buffer=false)) val apbXbar = LazyModule(new APBFanout()) val apbRegs = LazyModule(new APBDebugRegisters()) apbRegs.node := apbXbar.node apb2tl.node := apbXbar.node apb2tlBuffer.node := apb2tl.node dmiXbar.node := apb2tlBuffer.node tlError.node := dmiXbar.node apbXbar.node }) val dmOuter = LazyModule( new TLDebugModuleOuter(device)) val intnode = IntSyncIdentityNode() intnode :*= IntSyncCrossingSource(alreadyRegistered = true) :*= dmOuter.intnode val dmiBypass = LazyModule(new TLBusBypass(beatBytes=4, bufferError=false, maxAtomic=0, maxTransfer=4)) val dmiInnerNode = TLAsyncCrossingSource() := dmiBypass.node := dmiXbar.node dmOuter.dmiNode := dmiXbar.node lazy val module = new Impl class Impl extends LazyRawModuleImp(this) { val nComponents = dmOuter.intnode.edges.out.size val io = IO(new Bundle { val dmi_clock = Input(Clock()) val dmi_reset = Input(Reset()) /** Debug Module Interface bewteen DM and DTM * * The DTM provides access to one or more Debug Modules (DMs) using DMI */ val dmi = (!p(ExportDebug).apb).option(Flipped(new DMIIO()(p))) // Optional APB Interface is fully diplomatic so is not listed here. val ctrl = new DebugCtrlBundle(nComponents) /** conrol signals for Inner, generated in Outer */ val innerCtrl = new AsyncBundle(new DebugInternalBundle(nComponents), AsyncQueueParams.singleton(safe=cfg.crossingHasSafeReset)) /** debug interruption generated in Inner */ val hgDebugInt = Input(Vec(nComponents, Bool())) /** hart reset request to core */ val hartResetReq = p(DebugModuleKey).get.hasHartResets.option(Output(Vec(nComponents, Bool()))) /** Authentication signal from core */ val dmAuthenticated = p(DebugModuleKey).get.hasAuthentication.option(Input(Bool())) }) val rf_reset = IO(Input(Reset())) // RF transform childClock := io.dmi_clock childReset := io.dmi_reset override def provideImplicitClockToLazyChildren = true withClockAndReset(childClock, childReset) { dmi2tlOpt.foreach { _.module.io.dmi <> io.dmi.get } val dmactiveAck = AsyncResetSynchronizerShiftReg(in=io.ctrl.dmactiveAck, sync=3, name=Some("dmactiveAckSync")) dmiBypass.module.io.bypass := ~io.ctrl.dmactive | ~dmactiveAck io.ctrl <> dmOuter.module.io.ctrl dmOuter.module.io.ctrl.dmactiveAck := dmactiveAck // send synced version down to dmOuter io.innerCtrl <> ToAsyncBundle(dmOuter.module.io.innerCtrl, AsyncQueueParams.singleton(safe=cfg.crossingHasSafeReset)) dmOuter.module.io.hgDebugInt := io.hgDebugInt io.hartResetReq.foreach { x => dmOuter.module.io.hartResetReq.foreach {y => x := y}} io.dmAuthenticated.foreach { x => dmOuter.module.io.dmAuthenticated.foreach { y => y := x}} } } } class TLDebugModuleInner(device: Device, getNComponents: () => Int, beatBytes: Int)(implicit p: Parameters) extends LazyModule { // For Shorter Register Names import DMI_RegAddrs._ val cfg = p(DebugModuleKey).get def getCfg = () => cfg val dmTopAddr = (1 << cfg.nDMIAddrSize) << 2 /** dmiNode address set */ val dmiNode = TLRegisterNode( // Address is range 0 to 0x1FF except DMCONTROL, HARTINFO, HAWINDOWSEL, HAWINDOW which are handled by Outer address = AddressSet.misaligned(0, DMI_DMCONTROL << 2) ++ AddressSet.misaligned((DMI_DMCONTROL + 1) << 2, ((DMI_HARTINFO << 2) - ((DMI_DMCONTROL + 1) << 2))) ++ AddressSet.misaligned((DMI_HARTINFO + 1) << 2, ((DMI_HAWINDOWSEL << 2) - ((DMI_HARTINFO + 1) << 2))) ++ AddressSet.misaligned((DMI_HAWINDOW + 1) << 2, (dmTopAddr - ((DMI_HAWINDOW + 1) << 2))), device = device, beatBytes = 4, executable = false ) val tlNode = TLRegisterNode( address=Seq(cfg.address), device=device, beatBytes=beatBytes, executable=true ) val sb2tlOpt = cfg.hasBusMaster.option(LazyModule(new SBToTL())) // If we want to support custom registers read through Abstract Commands, // provide a place to bring them into the debug module. What this connects // to is up to the implementation. val customNode = new DebugCustomSink() lazy val module = new Impl class Impl extends LazyModuleImp(this){ val nComponents = getNComponents() Annotated.params(this, cfg) val supportHartArray = cfg.supportHartArray & (nComponents > 1) val nExtTriggers = cfg.nExtTriggers val nHaltGroups = if ((nComponents > 1) | (nExtTriggers > 0)) cfg.nHaltGroups else 0 // no halt groups possible if single hart with no external triggers val hartSelFuncs = if (getNComponents() > 1) p(DebugModuleHartSelKey) else DebugModuleHartSelFuncs( hartIdToHartSel = (x) => 0.U, hartSelToHartId = (x) => x ) val io = IO(new Bundle { /** dm reset signal passed in from Outer */ val dmactive = Input(Bool()) /** conrol signals for Inner * * it's generated by Outer and comes in */ val innerCtrl = Flipped(new DecoupledIO(new DebugInternalBundle(nComponents))) /** debug unavail signal passed in from Outer*/ val debugUnavail = Input(Vec(nComponents, Bool())) /** debug interruption from Inner to Outer * * contain 2 type of debug interruption causes: * - halt group * - halt-on-reset */ val hgDebugInt = Output(Vec(nComponents, Bool())) /** interface for trigger */ val extTrigger = (nExtTriggers > 0).option(new DebugExtTriggerIO()) /** vector to indicate which hart is in reset * * dm receives it from core and sends it to Inner */ val hartIsInReset = Input(Vec(nComponents, Bool())) val tl_clock = Input(Clock()) val tl_reset = Input(Reset()) /** Debug Authentication signals from core */ val auth = cfg.hasAuthentication.option(new DebugAuthenticationIO()) }) sb2tlOpt.map { sb => sb.module.clock := io.tl_clock sb.module.reset := io.tl_reset sb.module.rf_reset := io.tl_reset } //-------------------------------------------------------------- // Import constants for shorter variable names //-------------------------------------------------------------- import DMI_RegAddrs._ import DsbRegAddrs._ import DsbBusConsts._ //-------------------------------------------------------------- // Sanity Check Configuration For this implementation. //-------------------------------------------------------------- require (cfg.supportQuickAccess == false, "No Quick Access support yet") require ((nHaltGroups > 0) || (nExtTriggers == 0), "External triggers require at least 1 halt group") //-------------------------------------------------------------- // Register & Wire Declarations (which need to be pre-declared) //-------------------------------------------------------------- // run control regs: tracking all the harts // implements: see implementation-specific bits part /** all harts halted status */ val haltedBitRegs = Reg(UInt(nComponents.W)) /** all harts resume request status */ val resumeReqRegs = Reg(UInt(nComponents.W)) /** all harts have reset status */ val haveResetBitRegs = Reg(UInt(nComponents.W)) // default is 1,after resume, resumeAcks get 0 /** all harts resume ack status */ val resumeAcks = Wire(UInt(nComponents.W)) // --- regmapper outputs // hart state Id and En // in Hart Bus Access ROM val hartHaltedWrEn = Wire(Bool()) val hartHaltedId = Wire(UInt(sbIdWidth.W)) val hartGoingWrEn = Wire(Bool()) val hartGoingId = Wire(UInt(sbIdWidth.W)) val hartResumingWrEn = Wire(Bool()) val hartResumingId = Wire(UInt(sbIdWidth.W)) val hartExceptionWrEn = Wire(Bool()) val hartExceptionId = Wire(UInt(sbIdWidth.W)) // progbuf and abstract data: byte-addressable control logic // AccessLegal is set only when state = waiting // RdEn and WrEnMaybe : contrl signal drived by DMI bus val dmiProgramBufferRdEn = WireInit(VecInit(Seq.fill(cfg.nProgramBufferWords * 4) {false.B} )) val dmiProgramBufferAccessLegal = WireInit(false.B) val dmiProgramBufferWrEnMaybe = WireInit(VecInit(Seq.fill(cfg.nProgramBufferWords * 4) {false.B} )) val dmiAbstractDataRdEn = WireInit(VecInit(Seq.fill(cfg.nAbstractDataWords * 4) {false.B} )) val dmiAbstractDataAccessLegal = WireInit(false.B) val dmiAbstractDataWrEnMaybe = WireInit(VecInit(Seq.fill(cfg.nAbstractDataWords * 4) {false.B} )) //-------------------------------------------------------------- // Registers coming from 'CONTROL' in Outer //-------------------------------------------------------------- val dmAuthenticated = io.auth.map(a => a.dmAuthenticated).getOrElse(true.B) val selectedHartReg = Reg(UInt(p(MaxHartIdBits).W)) // hamaskFull is a vector of all selected harts including hartsel, whether or not supportHartArray is true val hamaskFull = WireInit(VecInit(Seq.fill(nComponents) {false.B} )) if (nComponents > 1) { when (~io.dmactive) { selectedHartReg := 0.U }.elsewhen (io.innerCtrl.fire){ selectedHartReg := io.innerCtrl.bits.hartsel } } if (supportHartArray) { val hamaskZero = WireInit(VecInit(Seq.fill(nComponents) {false.B} )) val hamaskReg = Reg(Vec(nComponents, Bool())) when (~io.dmactive || ~dmAuthenticated) { hamaskReg := hamaskZero }.elsewhen (io.innerCtrl.fire){ hamaskReg := Mux(io.innerCtrl.bits.hasel, io.innerCtrl.bits.hamask, hamaskZero) } hamaskFull := hamaskReg } // Outer.hamask doesn't consider the hart selected by dmcontrol.hartsello, // so append it here when (selectedHartReg < nComponents.U) { hamaskFull(if (nComponents == 1) 0.U(0.W) else selectedHartReg) := true.B } io.innerCtrl.ready := true.B // Construct a Vec from io.innerCtrl fields indicating whether each hart is being selected in this write // A hart may be selected by hartsel field or by hart array val hamaskWrSel = WireInit(VecInit(Seq.fill(nComponents) {false.B} )) for (component <- 0 until nComponents ) { hamaskWrSel(component) := ((io.innerCtrl.bits.hartsel === component.U) || (if (supportHartArray) io.innerCtrl.bits.hasel && io.innerCtrl.bits.hamask(component) else false.B)) } //------------------------------------- // Halt-on-reset logic // hrmask is set in dmOuter and passed in // Debug interrupt is generated when a reset occurs whose corresponding hrmask bit is set // Debug interrupt is maintained until the hart enters halted state //------------------------------------- val hrReset = WireInit(VecInit(Seq.fill(nComponents) { false.B } )) val hrDebugInt = Wire(Vec(nComponents, Bool())) val hrmaskReg = RegInit(hrReset) val hartIsInResetSync = Wire(Vec(nComponents, Bool())) for (component <- 0 until nComponents) { hartIsInResetSync(component) := AsyncResetSynchronizerShiftReg(io.hartIsInReset(component), 3, Some(s"debug_hartReset_$component")) } when (~io.dmactive || ~dmAuthenticated) { hrmaskReg := hrReset }.elsewhen (io.innerCtrl.fire){ hrmaskReg := io.innerCtrl.bits.hrmask } withReset(reset.asAsyncReset) { // ensure interrupt requests are negated at first clock edge val hrDebugIntReg = RegInit(VecInit(Seq.fill(nComponents) { false.B } )) when (~io.dmactive || ~dmAuthenticated) { hrDebugIntReg := hrReset }.otherwise { hrDebugIntReg := hrmaskReg & (hartIsInResetSync | // set debugInt during reset (hrDebugIntReg & ~(haltedBitRegs.asBools))) // maintain until core halts } hrDebugInt := hrDebugIntReg } //-------------------------------------------------------------- // DMI Registers //-------------------------------------------------------------- //----DMSTATUS val DMSTATUSRdData = WireInit(0.U.asTypeOf(new DMSTATUSFields())) DMSTATUSRdData.authenticated := dmAuthenticated DMSTATUSRdData.version := 2.U // Version 0.13 io.auth.map(a => DMSTATUSRdData.authbusy := a.dmAuthBusy) val resumereq = io.innerCtrl.fire && io.innerCtrl.bits.resumereq when (dmAuthenticated) { DMSTATUSRdData.hasresethaltreq := true.B DMSTATUSRdData.anynonexistent := (selectedHartReg >= nComponents.U) // only hartsel can be nonexistent // all harts nonexistent if hartsel is out of range and there are no harts selected in the hart array DMSTATUSRdData.allnonexistent := (selectedHartReg >= nComponents.U) & (~hamaskFull.reduce(_ | _)) when (~DMSTATUSRdData.allnonexistent) { // if no existent harts selected, all other status is false DMSTATUSRdData.anyunavail := (io.debugUnavail & hamaskFull).reduce(_ | _) DMSTATUSRdData.anyhalted := ((~io.debugUnavail & (haltedBitRegs.asBools)) & hamaskFull).reduce(_ | _) DMSTATUSRdData.anyrunning := ((~io.debugUnavail & ~(haltedBitRegs.asBools)) & hamaskFull).reduce(_ | _) DMSTATUSRdData.anyhavereset := (haveResetBitRegs.asBools & hamaskFull).reduce(_ | _) DMSTATUSRdData.anyresumeack := (resumeAcks.asBools & hamaskFull).reduce(_ | _) when (~DMSTATUSRdData.anynonexistent) { // if one hart is nonexistent, no 'all' status is set DMSTATUSRdData.allunavail := (io.debugUnavail | ~hamaskFull).reduce(_ & _) DMSTATUSRdData.allhalted := ((~io.debugUnavail & (haltedBitRegs.asBools)) | ~hamaskFull).reduce(_ & _) DMSTATUSRdData.allrunning := ((~io.debugUnavail & ~(haltedBitRegs.asBools)) | ~hamaskFull).reduce(_ & _) DMSTATUSRdData.allhavereset := (haveResetBitRegs.asBools | ~hamaskFull).reduce(_ & _) DMSTATUSRdData.allresumeack := (resumeAcks.asBools | ~hamaskFull).reduce(_ & _) } } //TODO DMSTATUSRdData.confstrptrvalid := false.B DMSTATUSRdData.impebreak := (cfg.hasImplicitEbreak).B } when(~io.dmactive || ~dmAuthenticated) { haveResetBitRegs := 0.U }.otherwise { when (io.innerCtrl.fire && io.innerCtrl.bits.ackhavereset) { haveResetBitRegs := (haveResetBitRegs & (~(hamaskWrSel.asUInt))) | hartIsInResetSync.asUInt }.otherwise { haveResetBitRegs := haveResetBitRegs | hartIsInResetSync.asUInt } } //----DMCS2 (Halt Groups) val DMCS2RdData = WireInit(0.U.asTypeOf(new DMCS2Fields())) val DMCS2WrData = WireInit(0.U.asTypeOf(new DMCS2Fields())) val hgselectWrEn = WireInit(false.B) val hgwriteWrEn = WireInit(false.B) val haltgroupWrEn = WireInit(false.B) val exttriggerWrEn = WireInit(false.B) val hgDebugInt = WireInit(VecInit(Seq.fill(nComponents) {false.B} )) if (nHaltGroups > 0) withReset (reset.asAsyncReset) { // async reset ensures triggers don't falsely fire during startup val hgBits = log2Up(nHaltGroups) // hgParticipate: Each entry indicates which hg that entity belongs to (1 to nHartGroups). 0 means no hg assigned. val hgParticipateHart = RegInit(VecInit(Seq.fill(nComponents)(0.U(hgBits.W)))) val hgParticipateTrig = if (nExtTriggers > 0) RegInit(VecInit(Seq.fill(nExtTriggers)(0.U(hgBits.W)))) else Nil // assign group index to current seledcted harts for (component <- 0 until nComponents) { when (~io.dmactive || ~dmAuthenticated) { hgParticipateHart(component) := 0.U }.otherwise { when (haltgroupWrEn & DMCS2WrData.hgwrite & ~DMCS2WrData.hgselect & hamaskFull(component) & (DMCS2WrData.haltgroup <= nHaltGroups.U)) { hgParticipateHart(component) := DMCS2WrData.haltgroup } } } DMCS2RdData.haltgroup := hgParticipateHart(if (nComponents == 1) 0.U(0.W) else selectedHartReg) if (nExtTriggers > 0) { val hgSelect = Reg(Bool()) when (~io.dmactive || ~dmAuthenticated) { hgSelect := false.B }.otherwise { when (hgselectWrEn) { hgSelect := DMCS2WrData.hgselect } } // assign group index to trigger for (trigger <- 0 until nExtTriggers) { when (~io.dmactive || ~dmAuthenticated) { hgParticipateTrig(trigger) := 0.U }.otherwise { when (haltgroupWrEn & DMCS2WrData.hgwrite & DMCS2WrData.hgselect & (DMCS2WrData.exttrigger === trigger.U) & (DMCS2WrData.haltgroup <= nHaltGroups.U)) { hgParticipateTrig(trigger) := DMCS2WrData.haltgroup } } } DMCS2RdData.hgselect := hgSelect when (hgSelect) { DMCS2RdData.haltgroup := hgParticipateTrig(0) } // If there is only 1 ext trigger, then the exttrigger field is fixed at 0 // Otherwise, instantiate a register with only the number of bits required if (nExtTriggers > 1) { val trigBits = log2Up(nExtTriggers-1) val hgExtTrigger = Reg(UInt(trigBits.W)) when (~io.dmactive || ~dmAuthenticated) { hgExtTrigger := 0.U }.otherwise { when (exttriggerWrEn & (DMCS2WrData.exttrigger < nExtTriggers.U)) { hgExtTrigger := DMCS2WrData.exttrigger } } DMCS2RdData.exttrigger := hgExtTrigger when (hgSelect) { DMCS2RdData.haltgroup := hgParticipateTrig(hgExtTrigger) } } } // Halt group state machine // IDLE: Go to FIRED when any hart in this hg writes to HALTED while its HaltedBitRegs=0 // or when any trigin assigned to this hg occurs // FIRED: Back to IDLE when all harts in this hg have set their haltedBitRegs // and all trig out in this hg have been acknowledged val hgFired = RegInit (VecInit(Seq.fill(nHaltGroups+1) {false.B} )) val hgHartFiring = WireInit(VecInit(Seq.fill(nHaltGroups+1) {false.B} )) // which hg's are firing due to hart halting val hgTrigFiring = WireInit(VecInit(Seq.fill(nHaltGroups+1) {false.B} )) // which hg's are firing due to trig in val hgHartsAllHalted = WireInit(VecInit(Seq.fill(nHaltGroups+1) {false.B} )) // in which hg's have all harts halted val hgTrigsAllAcked = WireInit(VecInit(Seq.fill(nHaltGroups+1) { true.B} )) // in which hg's have all trigouts been acked io.extTrigger.foreach {extTrigger => val extTriggerInReq = Wire(Vec(nExtTriggers, Bool())) val extTriggerOutAck = Wire(Vec(nExtTriggers, Bool())) extTriggerInReq := extTrigger.in.req.asBools extTriggerOutAck := extTrigger.out.ack.asBools val trigInReq = ResetSynchronizerShiftReg(in=extTriggerInReq, sync=3, name=Some("dm_extTriggerInReqSync")) val trigOutAck = ResetSynchronizerShiftReg(in=extTriggerOutAck, sync=3, name=Some("dm_extTriggerOutAckSync")) for (hg <- 1 to nHaltGroups) { hgTrigFiring(hg) := (trigInReq & ~RegNext(trigInReq) & hgParticipateTrig.map(_ === hg.U)).reduce(_ | _) hgTrigsAllAcked(hg) := (trigOutAck | hgParticipateTrig.map(_ =/= hg.U)).reduce(_ & _) } extTrigger.in.ack := trigInReq.asUInt } for (hg <- 1 to nHaltGroups) { hgHartFiring(hg) := hartHaltedWrEn & ~haltedBitRegs(hartHaltedId) & (hgParticipateHart(hartSelFuncs.hartIdToHartSel(hartHaltedId)) === hg.U) hgHartsAllHalted(hg) := (haltedBitRegs.asBools | hgParticipateHart.map(_ =/= hg.U)).reduce(_ & _) when (~io.dmactive || ~dmAuthenticated) { hgFired(hg) := false.B }.elsewhen (~hgFired(hg) & (hgHartFiring(hg) | hgTrigFiring(hg))) { hgFired(hg) := true.B }.elsewhen ( hgFired(hg) & hgHartsAllHalted(hg) & hgTrigsAllAcked(hg)) { hgFired(hg) := false.B } } // For each hg that has fired, assert debug interrupt to each hart in that hg for (component <- 0 until nComponents) { hgDebugInt(component) := hgFired(hgParticipateHart(component)) } // For each hg that has fired, assert trigger out for all external triggers in that hg io.extTrigger.foreach {extTrigger => val extTriggerOutReq = RegInit(VecInit(Seq.fill(cfg.nExtTriggers) {false.B} )) for (trig <- 0 until nExtTriggers) { extTriggerOutReq(trig) := hgFired(hgParticipateTrig(trig)) } extTrigger.out.req := extTriggerOutReq.asUInt } } io.hgDebugInt := hgDebugInt | hrDebugInt //----HALTSUM* val numHaltedStatus = ((nComponents - 1) / 32) + 1 val haltedStatus = Wire(Vec(numHaltedStatus, Bits(32.W))) for (ii <- 0 until numHaltedStatus) { when (dmAuthenticated) { haltedStatus(ii) := haltedBitRegs >> (ii*32) }.otherwise { haltedStatus(ii) := 0.U } } val haltedSummary = Cat(haltedStatus.map(_.orR).reverse) val HALTSUM1RdData = haltedSummary.asTypeOf(new HALTSUM1Fields()) val selectedHaltedStatus = Mux((selectedHartReg >> 5) > numHaltedStatus.U, 0.U, haltedStatus(selectedHartReg >> 5)) val HALTSUM0RdData = selectedHaltedStatus.asTypeOf(new HALTSUM0Fields()) // Since we only support 1024 harts, we don't implement HALTSUM2 or HALTSUM3 //----ABSTRACTCS val ABSTRACTCSReset = WireInit(0.U.asTypeOf(new ABSTRACTCSFields())) ABSTRACTCSReset.datacount := cfg.nAbstractDataWords.U ABSTRACTCSReset.progbufsize := cfg.nProgramBufferWords.U val ABSTRACTCSReg = Reg(new ABSTRACTCSFields()) val ABSTRACTCSWrData = WireInit(0.U.asTypeOf(new ABSTRACTCSFields())) val ABSTRACTCSRdData = WireInit(ABSTRACTCSReg) val ABSTRACTCSRdEn = WireInit(false.B) val ABSTRACTCSWrEnMaybe = WireInit(false.B) val ABSTRACTCSWrEnLegal = WireInit(false.B) val ABSTRACTCSWrEn = ABSTRACTCSWrEnMaybe && ABSTRACTCSWrEnLegal // multiple error types // find implement in the state machine part val errorBusy = WireInit(false.B) val errorException = WireInit(false.B) val errorUnsupported = WireInit(false.B) val errorHaltResume = WireInit(false.B) when (~io.dmactive || ~dmAuthenticated) { ABSTRACTCSReg := ABSTRACTCSReset }.otherwise { when (errorBusy){ ABSTRACTCSReg.cmderr := DebugAbstractCommandError.ErrBusy.id.U }.elsewhen (errorException) { ABSTRACTCSReg.cmderr := DebugAbstractCommandError.ErrException.id.U }.elsewhen (errorUnsupported) { ABSTRACTCSReg.cmderr := DebugAbstractCommandError.ErrNotSupported.id.U }.elsewhen (errorHaltResume) { ABSTRACTCSReg.cmderr := DebugAbstractCommandError.ErrHaltResume.id.U }.otherwise { //W1C when (ABSTRACTCSWrEn){ ABSTRACTCSReg.cmderr := ABSTRACTCSReg.cmderr & ~(ABSTRACTCSWrData.cmderr); } } } // For busy, see below state machine. val abstractCommandBusy = WireInit(true.B) ABSTRACTCSRdData.busy := abstractCommandBusy when (~dmAuthenticated) { // read value must be 0 when not authenticated ABSTRACTCSRdData.datacount := 0.U ABSTRACTCSRdData.progbufsize := 0.U } //---- ABSTRACTAUTO // It is a mask indicating whether datai/probufi have the autoexcution permisson // this part aims to produce 3 wires : autoexecData,autoexecProg,autoexec // first two specify which reg supports autoexec // autoexec is a control signal, meaning there is at least one enabled autoexec reg // when autoexec is set, generate instructions using COMMAND register val ABSTRACTAUTOReset = WireInit(0.U.asTypeOf(new ABSTRACTAUTOFields())) val ABSTRACTAUTOReg = Reg(new ABSTRACTAUTOFields()) val ABSTRACTAUTOWrData = WireInit(0.U.asTypeOf(new ABSTRACTAUTOFields())) val ABSTRACTAUTORdData = WireInit(ABSTRACTAUTOReg) val ABSTRACTAUTORdEn = WireInit(false.B) val autoexecdataWrEnMaybe = WireInit(false.B) val autoexecprogbufWrEnMaybe = WireInit(false.B) val ABSTRACTAUTOWrEnLegal = WireInit(false.B) when (~io.dmactive || ~dmAuthenticated) { ABSTRACTAUTOReg := ABSTRACTAUTOReset }.otherwise { when (autoexecprogbufWrEnMaybe && ABSTRACTAUTOWrEnLegal) { ABSTRACTAUTOReg.autoexecprogbuf := ABSTRACTAUTOWrData.autoexecprogbuf & ( (1 << cfg.nProgramBufferWords) - 1).U } when (autoexecdataWrEnMaybe && ABSTRACTAUTOWrEnLegal) { ABSTRACTAUTOReg.autoexecdata := ABSTRACTAUTOWrData.autoexecdata & ( (1 << cfg.nAbstractDataWords) - 1).U } } // Abstract Data access vector(byte-addressable) val dmiAbstractDataAccessVec = WireInit(VecInit(Seq.fill(cfg.nAbstractDataWords * 4) {false.B} )) dmiAbstractDataAccessVec := (dmiAbstractDataWrEnMaybe zip dmiAbstractDataRdEn).map{ case (r,w) => r | w} // Program Buffer access vector(byte-addressable) val dmiProgramBufferAccessVec = WireInit(VecInit(Seq.fill(cfg.nProgramBufferWords * 4) {false.B} )) dmiProgramBufferAccessVec := (dmiProgramBufferWrEnMaybe zip dmiProgramBufferRdEn).map{ case (r,w) => r | w} // at least one word access val dmiAbstractDataAccess = dmiAbstractDataAccessVec.reduce(_ || _ ) val dmiProgramBufferAccess = dmiProgramBufferAccessVec.reduce(_ || _) // This will take the shorter of the lists, which is what we want. val autoexecData = WireInit(VecInit(Seq.fill(cfg.nAbstractDataWords) {false.B} )) val autoexecProg = WireInit(VecInit(Seq.fill(cfg.nProgramBufferWords) {false.B} )) (autoexecData zip ABSTRACTAUTOReg.autoexecdata.asBools).zipWithIndex.foreach {case (t, i) => t._1 := dmiAbstractDataAccessVec(i * 4) && t._2 } (autoexecProg zip ABSTRACTAUTOReg.autoexecprogbuf.asBools).zipWithIndex.foreach {case (t, i) => t._1 := dmiProgramBufferAccessVec(i * 4) && t._2} val autoexec = autoexecData.reduce(_ || _) || autoexecProg.reduce(_ || _) //---- COMMAND val COMMANDReset = WireInit(0.U.asTypeOf(new COMMANDFields())) val COMMANDReg = Reg(new COMMANDFields()) val COMMANDWrDataVal = WireInit(0.U(32.W)) val COMMANDWrData = WireInit(COMMANDWrDataVal.asTypeOf(new COMMANDFields())) val COMMANDWrEnMaybe = WireInit(false.B) val COMMANDWrEnLegal = WireInit(false.B) val COMMANDRdEn = WireInit(false.B) val COMMANDWrEn = COMMANDWrEnMaybe && COMMANDWrEnLegal val COMMANDRdData = COMMANDReg when (~io.dmactive || ~dmAuthenticated) { COMMANDReg := COMMANDReset }.otherwise { when (COMMANDWrEn) { COMMANDReg := COMMANDWrData } } // --- Abstract Data // These are byte addressible, s.t. the Processor can use // byte-addressible instructions to store to them. val abstractDataMem = Reg(Vec(cfg.nAbstractDataWords*4, UInt(8.W))) val abstractDataNxt = WireInit(abstractDataMem) // --- Program Buffer // byte-addressible mem val programBufferMem = Reg(Vec(cfg.nProgramBufferWords*4, UInt(8.W))) val programBufferNxt = WireInit(programBufferMem) //-------------------------------------------------------------- // These bits are implementation-specific bits set // by harts executing code. //-------------------------------------------------------------- // Run control logic when (~io.dmactive || ~dmAuthenticated) { haltedBitRegs := 0.U resumeReqRegs := 0.U }.otherwise { //remove those harts in reset resumeReqRegs := resumeReqRegs & ~(hartIsInResetSync.asUInt) val hartHaltedIdIndex = UIntToOH(hartSelFuncs.hartIdToHartSel(hartHaltedId)) val hartResumingIdIndex = UIntToOH(hartSelFuncs.hartIdToHartSel(hartResumingId)) val hartselIndex = UIntToOH(io.innerCtrl.bits.hartsel) when (hartHaltedWrEn) { // add those harts halting and remove those in reset haltedBitRegs := (haltedBitRegs | hartHaltedIdIndex) & ~(hartIsInResetSync.asUInt) }.elsewhen (hartResumingWrEn) { // remove those harts in reset and those in resume haltedBitRegs := (haltedBitRegs & ~(hartResumingIdIndex)) & ~(hartIsInResetSync.asUInt) }.otherwise { // remove those harts in reset haltedBitRegs := haltedBitRegs & ~(hartIsInResetSync.asUInt) } when (hartResumingWrEn) { // remove those harts in resume and those in reset resumeReqRegs := (resumeReqRegs & ~(hartResumingIdIndex)) & ~(hartIsInResetSync.asUInt) } when (resumereq) { // set all sleceted harts to resumeReq, remove those in reset resumeReqRegs := (resumeReqRegs | hamaskWrSel.asUInt) & ~(hartIsInResetSync.asUInt) } } when (resumereq) { // next cycle resumeAcls will be the negation of next cycle resumeReqRegs resumeAcks := (~resumeReqRegs & ~(hamaskWrSel.asUInt)) }.otherwise { resumeAcks := ~resumeReqRegs } //---- AUTHDATA val authRdEnMaybe = WireInit(false.B) val authWrEnMaybe = WireInit(false.B) io.auth.map { a => a.dmactive := io.dmactive a.dmAuthRead := authRdEnMaybe & ~a.dmAuthBusy a.dmAuthWrite := authWrEnMaybe & ~a.dmAuthBusy } val dmstatusRegFields = RegFieldGroup("dmi_dmstatus", Some("debug module status register"), Seq( RegField.r(4, DMSTATUSRdData.version, RegFieldDesc("version", "version", reset=Some(2))), RegField.r(1, DMSTATUSRdData.confstrptrvalid, RegFieldDesc("confstrptrvalid", "confstrptrvalid", reset=Some(0))), RegField.r(1, DMSTATUSRdData.hasresethaltreq, RegFieldDesc("hasresethaltreq", "hasresethaltreq", reset=Some(1))), RegField.r(1, DMSTATUSRdData.authbusy, RegFieldDesc("authbusy", "authbusy", reset=Some(0))), RegField.r(1, DMSTATUSRdData.authenticated, RegFieldDesc("authenticated", "authenticated", reset=Some(1))), RegField.r(1, DMSTATUSRdData.anyhalted, RegFieldDesc("anyhalted", "anyhalted", reset=Some(0))), RegField.r(1, DMSTATUSRdData.allhalted, RegFieldDesc("allhalted", "allhalted", reset=Some(0))), RegField.r(1, DMSTATUSRdData.anyrunning, RegFieldDesc("anyrunning", "anyrunning", reset=Some(1))), RegField.r(1, DMSTATUSRdData.allrunning, RegFieldDesc("allrunning", "allrunning", reset=Some(1))), RegField.r(1, DMSTATUSRdData.anyunavail, RegFieldDesc("anyunavail", "anyunavail", reset=Some(0))), RegField.r(1, DMSTATUSRdData.allunavail, RegFieldDesc("allunavail", "allunavail", reset=Some(0))), RegField.r(1, DMSTATUSRdData.anynonexistent, RegFieldDesc("anynonexistent", "anynonexistent", reset=Some(0))), RegField.r(1, DMSTATUSRdData.allnonexistent, RegFieldDesc("allnonexistent", "allnonexistent", reset=Some(0))), RegField.r(1, DMSTATUSRdData.anyresumeack, RegFieldDesc("anyresumeack", "anyresumeack", reset=Some(1))), RegField.r(1, DMSTATUSRdData.allresumeack, RegFieldDesc("allresumeack", "allresumeack", reset=Some(1))), RegField.r(1, DMSTATUSRdData.anyhavereset, RegFieldDesc("anyhavereset", "anyhavereset", reset=Some(0))), RegField.r(1, DMSTATUSRdData.allhavereset, RegFieldDesc("allhavereset", "allhavereset", reset=Some(0))), RegField(2), RegField.r(1, DMSTATUSRdData.impebreak, RegFieldDesc("impebreak", "impebreak", reset=Some(if (cfg.hasImplicitEbreak) 1 else 0))) )) val dmcs2RegFields = RegFieldGroup("dmi_dmcs2", Some("debug module control/status register 2"), Seq( WNotifyVal(1, DMCS2RdData.hgselect, DMCS2WrData.hgselect, hgselectWrEn, RegFieldDesc("hgselect", "select halt groups or external triggers", reset=Some(0), volatile=true)), WNotifyVal(1, 0.U, DMCS2WrData.hgwrite, hgwriteWrEn, RegFieldDesc("hgwrite", "write 1 to change halt groups", reset=None, access=RegFieldAccessType.W)), WNotifyVal(5, DMCS2RdData.haltgroup, DMCS2WrData.haltgroup, haltgroupWrEn, RegFieldDesc("haltgroup", "halt group", reset=Some(0), volatile=true)), if (nExtTriggers > 1) WNotifyVal(4, DMCS2RdData.exttrigger, DMCS2WrData.exttrigger, exttriggerWrEn, RegFieldDesc("exttrigger", "external trigger select", reset=Some(0), volatile=true)) else RegField(4) )) val abstractcsRegFields = RegFieldGroup("dmi_abstractcs", Some("abstract command control/status"), Seq( RegField.r(4, ABSTRACTCSRdData.datacount, RegFieldDesc("datacount", "number of DATA registers", reset=Some(cfg.nAbstractDataWords))), RegField(4), WNotifyVal(3, ABSTRACTCSRdData.cmderr, ABSTRACTCSWrData.cmderr, ABSTRACTCSWrEnMaybe, RegFieldDesc("cmderr", "command error", reset=Some(0), wrType=Some(RegFieldWrType.ONE_TO_CLEAR))), RegField(1), RegField.r(1, ABSTRACTCSRdData.busy, RegFieldDesc("busy", "busy", reset=Some(0))), RegField(11), RegField.r(5, ABSTRACTCSRdData.progbufsize, RegFieldDesc("progbufsize", "number of PROGBUF registers", reset=Some(cfg.nProgramBufferWords))) )) val (sbcsFields, sbAddrFields, sbDataFields): (Seq[RegField], Seq[Seq[RegField]], Seq[Seq[RegField]]) = sb2tlOpt.map{ sb2tl => SystemBusAccessModule(sb2tl, io.dmactive, dmAuthenticated)(p) }.getOrElse((Seq.empty[RegField], Seq.fill[Seq[RegField]](4)(Seq.empty[RegField]), Seq.fill[Seq[RegField]](4)(Seq.empty[RegField]))) //-------------------------------------------------------------- // Program Buffer Access (DMI ... System Bus can override) //-------------------------------------------------------------- val omRegMap = dmiNode.regmap( (DMI_DMSTATUS << 2) -> dmstatusRegFields, //TODO (DMI_CFGSTRADDR0 << 2) -> cfgStrAddrFields, (DMI_DMCS2 << 2) -> (if (nHaltGroups > 0) dmcs2RegFields else Nil), (DMI_HALTSUM0 << 2) -> RegFieldGroup("dmi_haltsum0", Some("Halt Summary 0"), Seq(RegField.r(32, HALTSUM0RdData.asUInt, RegFieldDesc("dmi_haltsum0", "halt summary 0")))), (DMI_HALTSUM1 << 2) -> RegFieldGroup("dmi_haltsum1", Some("Halt Summary 1"), Seq(RegField.r(32, HALTSUM1RdData.asUInt, RegFieldDesc("dmi_haltsum1", "halt summary 1")))), (DMI_ABSTRACTCS << 2) -> abstractcsRegFields, (DMI_ABSTRACTAUTO<< 2) -> RegFieldGroup("dmi_abstractauto", Some("abstract command autoexec"), Seq( WNotifyVal(cfg.nAbstractDataWords, ABSTRACTAUTORdData.autoexecdata, ABSTRACTAUTOWrData.autoexecdata, autoexecdataWrEnMaybe, RegFieldDesc("autoexecdata", "abstract command data autoexec", reset=Some(0))), RegField(16-cfg.nAbstractDataWords), WNotifyVal(cfg.nProgramBufferWords, ABSTRACTAUTORdData.autoexecprogbuf, ABSTRACTAUTOWrData.autoexecprogbuf, autoexecprogbufWrEnMaybe, RegFieldDesc("autoexecprogbuf", "abstract command progbuf autoexec", reset=Some(0))))), (DMI_COMMAND << 2) -> RegFieldGroup("dmi_command", Some("Abstract Command Register"), Seq(RWNotify(32, COMMANDRdData.asUInt, COMMANDWrDataVal, COMMANDRdEn, COMMANDWrEnMaybe, Some(RegFieldDesc("dmi_command", "abstract command register", reset=Some(0), volatile=true))))), (DMI_DATA0 << 2) -> RegFieldGroup("dmi_data", Some("abstract command data registers"), abstractDataMem.zipWithIndex.map{case (x, i) => RWNotify(8, Mux(dmAuthenticated, x, 0.U), abstractDataNxt(i), dmiAbstractDataRdEn(i), dmiAbstractDataWrEnMaybe(i), Some(RegFieldDesc(s"dmi_data_$i", s"abstract command data register $i", reset = Some(0), volatile=true)))}, false), (DMI_PROGBUF0 << 2) -> RegFieldGroup("dmi_progbuf", Some("abstract command progbuf registers"), programBufferMem.zipWithIndex.map{case (x, i) => RWNotify(8, Mux(dmAuthenticated, x, 0.U), programBufferNxt(i), dmiProgramBufferRdEn(i), dmiProgramBufferWrEnMaybe(i), Some(RegFieldDesc(s"dmi_progbuf_$i", s"abstract command progbuf register $i", reset = Some(0))))}, false), (DMI_AUTHDATA << 2) -> (if (cfg.hasAuthentication) RegFieldGroup("dmi_authdata", Some("authentication data exchange register"), Seq(RWNotify(32, io.auth.get.dmAuthRdata, io.auth.get.dmAuthWdata, authRdEnMaybe, authWrEnMaybe, Some(RegFieldDesc("authdata", "authentication data exchange", volatile=true))))) else Nil), (DMI_SBCS << 2) -> sbcsFields, (DMI_SBDATA0 << 2) -> sbDataFields(0), (DMI_SBDATA1 << 2) -> sbDataFields(1), (DMI_SBDATA2 << 2) -> sbDataFields(2), (DMI_SBDATA3 << 2) -> sbDataFields(3), (DMI_SBADDRESS0 << 2) -> sbAddrFields(0), (DMI_SBADDRESS1 << 2) -> sbAddrFields(1), (DMI_SBADDRESS2 << 2) -> sbAddrFields(2), (DMI_SBADDRESS3 << 2) -> sbAddrFields(3) ) // Abstract data mem is written by both the tile link interface and DMI... abstractDataMem.zipWithIndex.foreach { case (x, i) => when (dmAuthenticated && dmiAbstractDataWrEnMaybe(i) && dmiAbstractDataAccessLegal) { x := abstractDataNxt(i) } } // ... and also by custom register read (if implemented) val (customs, customParams) = customNode.in.unzip val needCustom = (customs.size > 0) && (customParams.head.addrs.size > 0) def getNeedCustom = () => needCustom if (needCustom) { val (custom, customP) = customNode.in.head require(customP.width % 8 == 0, s"Debug Custom width must be divisible by 8, not ${customP.width}") val custom_data = custom.data.asBools val custom_bytes = Seq.tabulate(customP.width/8){i => custom_data.slice(i*8, (i+1)*8).asUInt} when (custom.ready && custom.valid) { (abstractDataMem zip custom_bytes).zipWithIndex.foreach {case ((a, b), i) => a := b } } } programBufferMem.zipWithIndex.foreach { case (x, i) => when (dmAuthenticated && dmiProgramBufferWrEnMaybe(i) && dmiProgramBufferAccessLegal) { x := programBufferNxt(i) } } //-------------------------------------------------------------- // "Variable" ROM Generation //-------------------------------------------------------------- val goReg = Reg(Bool()) val goAbstract = WireInit(false.B) val goCustom = WireInit(false.B) val jalAbstract = WireInit(Instructions.JAL.value.U.asTypeOf(new GeneratedUJ())) jalAbstract.setImm(ABSTRACT(cfg) - WHERETO) when (~io.dmactive){ goReg := false.B }.otherwise { when (goAbstract) { goReg := true.B }.elsewhen (hartGoingWrEn){ assert(hartGoingId === 0.U, "Unexpected 'GOING' hart.")//Chisel3 #540 %x, expected %x", hartGoingId, 0.U) goReg := false.B } } class flagBundle extends Bundle { val reserved = UInt(6.W) val resume = Bool() val go = Bool() } val flags = WireInit(VecInit(Seq.fill(1 << selectedHartReg.getWidth) {0.U.asTypeOf(new flagBundle())} )) assert ((hartSelFuncs.hartSelToHartId(selectedHartReg) < flags.size.U), s"HartSel to HartId Mapping is illegal for this Debug Implementation, because HartID must be < ${flags.size} for it to work.") flags(hartSelFuncs.hartSelToHartId(selectedHartReg)).go := goReg for (component <- 0 until nComponents) { val componentSel = WireInit(component.U) flags(hartSelFuncs.hartSelToHartId(componentSel)).resume := resumeReqRegs(component) } //---------------------------- // Abstract Command Decoding & Generation //---------------------------- val accessRegisterCommandWr = WireInit(COMMANDWrData.asUInt.asTypeOf(new ACCESS_REGISTERFields())) /** real COMMAND*/ val accessRegisterCommandReg = WireInit(COMMANDReg.asUInt.asTypeOf(new ACCESS_REGISTERFields())) // TODO: Quick Access class GeneratedI extends Bundle { val imm = UInt(12.W) val rs1 = UInt(5.W) val funct3 = UInt(3.W) val rd = UInt(5.W) val opcode = UInt(7.W) } class GeneratedS extends Bundle { val immhi = UInt(7.W) val rs2 = UInt(5.W) val rs1 = UInt(5.W) val funct3 = UInt(3.W) val immlo = UInt(5.W) val opcode = UInt(7.W) } class GeneratedCSR extends Bundle { val imm = UInt(12.W) val rs1 = UInt(5.W) val funct3 = UInt(3.W) val rd = UInt(5.W) val opcode = UInt(7.W) } class GeneratedUJ extends Bundle { val imm3 = UInt(1.W) val imm0 = UInt(10.W) val imm1 = UInt(1.W) val imm2 = UInt(8.W) val rd = UInt(5.W) val opcode = UInt(7.W) def setImm(imm: Int) : Unit = { // TODO: Check bounds of imm. require(imm % 2 == 0, "Immediate must be even for UJ encoding.") val immWire = WireInit(imm.S(21.W)) val immBits = WireInit(VecInit(immWire.asBools)) imm0 := immBits.slice(1, 1 + 10).asUInt imm1 := immBits.slice(11, 11 + 11).asUInt imm2 := immBits.slice(12, 12 + 8).asUInt imm3 := immBits.slice(20, 20 + 1).asUInt } } require((cfg.atzero && cfg.nAbstractInstructions == 2) || (!cfg.atzero && cfg.nAbstractInstructions == 5), "Mismatch between DebugModuleParams atzero and nAbstractInstructions") val abstractGeneratedMem = Reg(Vec(cfg.nAbstractInstructions, (UInt(32.W)))) def abstractGeneratedI(cfg: DebugModuleParams): UInt = { val inst = Wire(new GeneratedI()) val offset = if (cfg.atzero) DATA else (DATA-0x800) & 0xFFF val base = if (cfg.atzero) 0.U else Mux(accessRegisterCommandReg.regno(0), 8.U, 9.U) inst.opcode := (Instructions.LW.value.U.asTypeOf(new GeneratedI())).opcode inst.rd := (accessRegisterCommandReg.regno & 0x1F.U) inst.funct3 := accessRegisterCommandReg.size inst.rs1 := base inst.imm := offset.U inst.asUInt } def abstractGeneratedS(cfg: DebugModuleParams): UInt = { val inst = Wire(new GeneratedS()) val offset = if (cfg.atzero) DATA else (DATA-0x800) & 0xFFF val base = if (cfg.atzero) 0.U else Mux(accessRegisterCommandReg.regno(0), 8.U, 9.U) inst.opcode := (Instructions.SW.value.U.asTypeOf(new GeneratedS())).opcode inst.immlo := (offset & 0x1F).U inst.funct3 := accessRegisterCommandReg.size inst.rs1 := base inst.rs2 := (accessRegisterCommandReg.regno & 0x1F.U) inst.immhi := (offset >> 5).U inst.asUInt } def abstractGeneratedCSR: UInt = { val inst = Wire(new GeneratedCSR()) val base = Mux(accessRegisterCommandReg.regno(0), 8.U, 9.U) // use s0 as base for odd regs, s1 as base for even regs inst := (Instructions.CSRRW.value.U.asTypeOf(new GeneratedCSR())) inst.imm := CSRs.dscratch1.U inst.rs1 := base inst.rd := base inst.asUInt } val nop = Wire(new GeneratedI()) nop := Instructions.ADDI.value.U.asTypeOf(new GeneratedI()) nop.rd := 0.U nop.rs1 := 0.U nop.imm := 0.U val isa = Wire(new GeneratedI()) isa := Instructions.ADDIW.value.U.asTypeOf(new GeneratedI()) isa.rd := 0.U isa.rs1 := 0.U isa.imm := 0.U when (goAbstract) { if (cfg.nAbstractInstructions == 2) { // ABSTRACT(0): Transfer: LW or SW, else NOP // ABSTRACT(1): Postexec: NOP else EBREAK abstractGeneratedMem(0) := Mux(accessRegisterCommandReg.transfer, Mux(accessRegisterCommandReg.write, abstractGeneratedI(cfg), abstractGeneratedS(cfg)), nop.asUInt ) abstractGeneratedMem(1) := Mux(accessRegisterCommandReg.postexec, nop.asUInt, Instructions.EBREAK.value.U) } else { // Entry: All regs in GPRs, dscratch1=offset 0x800 in DM // ABSTRACT(0): CheckISA: ADDW or NOP (exception here if size=3 and not RV64) // ABSTRACT(1): CSRRW s1,dscratch1,s1 or CSRRW s0,dscratch1,s0 // ABSTRACT(2): Transfer: LW, SW, LD, SD else NOP // ABSTRACT(3): CSRRW s1,dscratch1,s1 or CSRRW s0,dscratch1,s0 // ABSTRACT(4): Postexec: NOP else EBREAK abstractGeneratedMem(0) := Mux(accessRegisterCommandReg.transfer && accessRegisterCommandReg.size =/= 2.U, isa.asUInt, nop.asUInt) abstractGeneratedMem(1) := abstractGeneratedCSR abstractGeneratedMem(2) := Mux(accessRegisterCommandReg.transfer, Mux(accessRegisterCommandReg.write, abstractGeneratedI(cfg), abstractGeneratedS(cfg)), nop.asUInt ) abstractGeneratedMem(3) := abstractGeneratedCSR abstractGeneratedMem(4) := Mux(accessRegisterCommandReg.postexec, nop.asUInt, Instructions.EBREAK.value.U) } } //-------------------------------------------------------------- // Drive Custom Access //-------------------------------------------------------------- if (needCustom) { val (custom, customP) = customNode.in.head custom.addr := accessRegisterCommandReg.regno custom.valid := goCustom } //-------------------------------------------------------------- // Hart Bus Access //-------------------------------------------------------------- tlNode.regmap( // This memory is writable. HALTED -> Seq(WNotifyWire(sbIdWidth, hartHaltedId, hartHaltedWrEn, "debug_hart_halted", "Debug ROM Causes hart to write its hartID here when it is in Debug Mode.")), GOING -> Seq(WNotifyWire(sbIdWidth, hartGoingId, hartGoingWrEn, "debug_hart_going", "Debug ROM causes hart to write 0 here when it begins executing Debug Mode instructions.")), RESUMING -> Seq(WNotifyWire(sbIdWidth, hartResumingId, hartResumingWrEn, "debug_hart_resuming", "Debug ROM causes hart to write its hartID here when it leaves Debug Mode.")), EXCEPTION -> Seq(WNotifyWire(sbIdWidth, hartExceptionId, hartExceptionWrEn, "debug_hart_exception", "Debug ROM causes hart to write 0 here if it gets an exception in Debug Mode.")), DATA -> RegFieldGroup("debug_data", Some("Data used to communicate with Debug Module"), abstractDataMem.zipWithIndex.map {case (x, i) => RegField(8, x, RegFieldDesc(s"debug_data_$i", ""))}), PROGBUF(cfg)-> RegFieldGroup("debug_progbuf", Some("Program buffer used to communicate with Debug Module"), programBufferMem.zipWithIndex.map {case (x, i) => RegField(8, x, RegFieldDesc(s"debug_progbuf_$i", ""))}), // These sections are read-only. IMPEBREAK(cfg)-> {if (cfg.hasImplicitEbreak) Seq(RegField.r(32, Instructions.EBREAK.value.U, RegFieldDesc("debug_impebreak", "Debug Implicit EBREAK", reset=Some(Instructions.EBREAK.value)))) else Nil}, WHERETO -> Seq(RegField.r(32, jalAbstract.asUInt, RegFieldDesc("debug_whereto", "Instruction filled in by Debug Module to control hart in Debug Mode", volatile = true))), ABSTRACT(cfg) -> RegFieldGroup("debug_abstract", Some("Instructions generated by Debug Module"), abstractGeneratedMem.zipWithIndex.map{ case (x,i) => RegField.r(32, x, RegFieldDesc(s"debug_abstract_$i", "", volatile=true))}), FLAGS -> RegFieldGroup("debug_flags", Some("Memory region used to control hart going/resuming in Debug Mode"), if (nComponents == 1) { Seq.tabulate(1024) { i => RegField.r(8, flags(0).asUInt, RegFieldDesc(s"debug_flags_$i", "", volatile=true)) } } else { flags.zipWithIndex.map{case(x, i) => RegField.r(8, x.asUInt, RegFieldDesc(s"debug_flags_$i", "", volatile=true))} }), ROMBASE -> RegFieldGroup("debug_rom", Some("Debug ROM"), (if (cfg.atzero) DebugRomContents() else DebugRomNonzeroContents()).zipWithIndex.map{case (x, i) => RegField.r(8, (x & 0xFF).U(8.W), RegFieldDesc(s"debug_rom_$i", "", reset=Some(x)))}) ) // Override System Bus accesses with dmactive reset. when (~io.dmactive){ abstractDataMem.foreach {x => x := 0.U} programBufferMem.foreach {x => x := 0.U} } //-------------------------------------------------------------- // Abstract Command State Machine //-------------------------------------------------------------- object CtrlState extends scala.Enumeration { type CtrlState = Value val Waiting, CheckGenerate, Exec, Custom = Value def apply( t : Value) : UInt = { t.id.U(log2Up(values.size).W) } } import CtrlState._ // This is not an initialization! val ctrlStateReg = Reg(chiselTypeOf(CtrlState(Waiting))) val hartHalted = haltedBitRegs(if (nComponents == 1) 0.U(0.W) else selectedHartReg) val ctrlStateNxt = WireInit(ctrlStateReg) //------------------------ // DMI Register Control and Status abstractCommandBusy := (ctrlStateReg =/= CtrlState(Waiting)) ABSTRACTCSWrEnLegal := (ctrlStateReg === CtrlState(Waiting)) COMMANDWrEnLegal := (ctrlStateReg === CtrlState(Waiting)) ABSTRACTAUTOWrEnLegal := (ctrlStateReg === CtrlState(Waiting)) dmiAbstractDataAccessLegal := (ctrlStateReg === CtrlState(Waiting)) dmiProgramBufferAccessLegal := (ctrlStateReg === CtrlState(Waiting)) errorBusy := (ABSTRACTCSWrEnMaybe && ~ABSTRACTCSWrEnLegal) || (autoexecdataWrEnMaybe && ~ABSTRACTAUTOWrEnLegal) || (autoexecprogbufWrEnMaybe && ~ABSTRACTAUTOWrEnLegal) || (COMMANDWrEnMaybe && ~COMMANDWrEnLegal) || (dmiAbstractDataAccess && ~dmiAbstractDataAccessLegal) || (dmiProgramBufferAccess && ~dmiProgramBufferAccessLegal) // TODO: Maybe Quick Access val commandWrIsAccessRegister = (COMMANDWrData.cmdtype === DebugAbstractCommandType.AccessRegister.id.U) val commandRegIsAccessRegister = (COMMANDReg.cmdtype === DebugAbstractCommandType.AccessRegister.id.U) val commandWrIsUnsupported = COMMANDWrEn && !commandWrIsAccessRegister val commandRegIsUnsupported = WireInit(true.B) val commandRegBadHaltResume = WireInit(false.B) // We only support abstract commands for GPRs and any custom registers, if specified. val accessRegIsLegalSize = (accessRegisterCommandReg.size === 2.U) || (accessRegisterCommandReg.size === 3.U) val accessRegIsGPR = (accessRegisterCommandReg.regno >= 0x1000.U && accessRegisterCommandReg.regno <= 0x101F.U) && accessRegIsLegalSize val accessRegIsCustom = if (needCustom) { val (custom, customP) = customNode.in.head customP.addrs.foldLeft(false.B){ (result, current) => result || (current.U === accessRegisterCommandReg.regno)} } else false.B when (commandRegIsAccessRegister) { when (accessRegIsCustom && accessRegisterCommandReg.transfer && accessRegisterCommandReg.write === false.B) { commandRegIsUnsupported := false.B }.elsewhen (!accessRegisterCommandReg.transfer || accessRegIsGPR) { commandRegIsUnsupported := false.B commandRegBadHaltResume := ~hartHalted } } val wrAccessRegisterCommand = COMMANDWrEn && commandWrIsAccessRegister && (ABSTRACTCSReg.cmderr === 0.U) val regAccessRegisterCommand = autoexec && commandRegIsAccessRegister && (ABSTRACTCSReg.cmderr === 0.U) //------------------------ // Variable ROM STATE MACHINE // ----------------------- when (ctrlStateReg === CtrlState(Waiting)){ when (wrAccessRegisterCommand || regAccessRegisterCommand) { ctrlStateNxt := CtrlState(CheckGenerate) }.elsewhen (commandWrIsUnsupported) { // These checks are really on the command type. errorUnsupported := true.B }.elsewhen (autoexec && commandRegIsUnsupported) { errorUnsupported := true.B } }.elsewhen (ctrlStateReg === CtrlState(CheckGenerate)){ // We use this state to ensure that the COMMAND has been // registered by the time that we need to use it, to avoid // generating it directly from the COMMANDWrData. // This 'commandRegIsUnsupported' is really just checking the // AccessRegisterCommand parameters (regno) when (commandRegIsUnsupported) { errorUnsupported := true.B ctrlStateNxt := CtrlState(Waiting) }.elsewhen (commandRegBadHaltResume){ errorHaltResume := true.B ctrlStateNxt := CtrlState(Waiting) }.otherwise { when(accessRegIsCustom) { ctrlStateNxt := CtrlState(Custom) }.otherwise { ctrlStateNxt := CtrlState(Exec) goAbstract := true.B } } }.elsewhen (ctrlStateReg === CtrlState(Exec)) { // We can't just look at 'hartHalted' here, because // hartHaltedWrEn is overloaded to mean 'got an ebreak' // which may have happened when we were already halted. when(goReg === false.B && hartHaltedWrEn && (hartSelFuncs.hartIdToHartSel(hartHaltedId) === selectedHartReg)){ ctrlStateNxt := CtrlState(Waiting) } when(hartExceptionWrEn) { assert(hartExceptionId === 0.U, "Unexpected 'EXCEPTION' hart")//Chisel3 #540, %x, expected %x", hartExceptionId, 0.U) ctrlStateNxt := CtrlState(Waiting) errorException := true.B } }.elsewhen (ctrlStateReg === CtrlState(Custom)) { assert(needCustom.B, "Should not be in custom state unless we need it.") goCustom := true.B val (custom, customP) = customNode.in.head when (custom.ready && custom.valid) { ctrlStateNxt := CtrlState(Waiting) } } when (~io.dmactive || ~dmAuthenticated) { ctrlStateReg := CtrlState(Waiting) }.otherwise { ctrlStateReg := ctrlStateNxt } assert ((!io.dmactive || !hartExceptionWrEn || ctrlStateReg === CtrlState(Exec)), "Unexpected EXCEPTION write: should only get it in Debug Module EXEC state") } } // Wrapper around TL Debug Module Inner and an Async DMI Sink interface. // Handles the synchronization of dmactive, which is used as a synchronous reset // inside the Inner block. // Also is the Sink side of hartsel & resumereq fields of DMCONTROL. class TLDebugModuleInnerAsync(device: Device, getNComponents: () => Int, beatBytes: Int)(implicit p: Parameters) extends LazyModule{ val cfg = p(DebugModuleKey).get val dmInner = LazyModule(new TLDebugModuleInner(device, getNComponents, beatBytes)) val dmiXing = LazyModule(new TLAsyncCrossingSink(AsyncQueueParams.singleton(safe=cfg.crossingHasSafeReset))) val dmiNode = dmiXing.node val tlNode = dmInner.tlNode dmInner.dmiNode := dmiXing.node // Require that there are no registers in TL interface, so that spurious // processor accesses to the DM don't need to enable the clock. We don't // require this property of the SBA, because the debugger is responsible for // raising dmactive (hence enabling the clock) during these transactions. require(dmInner.tlNode.concurrency == 0) lazy val module = new Impl class Impl extends LazyRawModuleImp(this) { // Clock/reset domains: // debug_clock / debug_reset = Debug inner domain // tl_clock / tl_reset = tilelink domain (External: clock / reset) // val io = IO(new Bundle { val debug_clock = Input(Clock()) val debug_reset = Input(Reset()) val tl_clock = Input(Clock()) val tl_reset = Input(Reset()) // These are all asynchronous and come from Outer /** reset signal for DM */ val dmactive = Input(Bool()) /** conrol signals for Inner * * generated in Outer */ val innerCtrl = Flipped(new AsyncBundle(new DebugInternalBundle(getNComponents()), AsyncQueueParams.singleton(safe=cfg.crossingHasSafeReset))) // This comes from tlClk domain. /** debug available status */ val debugUnavail = Input(Vec(getNComponents(), Bool())) /** debug interruption*/ val hgDebugInt = Output(Vec(getNComponents(), Bool())) val extTrigger = (p(DebugModuleKey).get.nExtTriggers > 0).option(new DebugExtTriggerIO()) /** vector to indicate which hart is in reset * * dm receives it from core and sends it to Inner */ val hartIsInReset = Input(Vec(getNComponents(), Bool())) /** Debug Authentication signals from core */ val auth = p(DebugModuleKey).get.hasAuthentication.option(new DebugAuthenticationIO()) }) val rf_reset = IO(Input(Reset())) // RF transform childClock := io.debug_clock childReset := io.debug_reset override def provideImplicitClockToLazyChildren = true val dmactive_synced = withClockAndReset(childClock, childReset) { val dmactive_synced = AsyncResetSynchronizerShiftReg(in=io.dmactive, sync=3, name=Some("dmactiveSync")) dmInner.module.clock := io.debug_clock dmInner.module.reset := io.debug_reset dmInner.module.io.tl_clock := io.tl_clock dmInner.module.io.tl_reset := io.tl_reset dmInner.module.io.dmactive := dmactive_synced dmInner.module.io.innerCtrl <> FromAsyncBundle(io.innerCtrl) dmInner.module.io.debugUnavail := io.debugUnavail io.hgDebugInt := dmInner.module.io.hgDebugInt io.extTrigger.foreach { x => dmInner.module.io.extTrigger.foreach {y => x <> y}} dmInner.module.io.hartIsInReset := io.hartIsInReset io.auth.foreach { x => dmInner.module.io.auth.foreach {y => x <> y}} dmactive_synced } } } /** Create a version of the TLDebugModule which includes a synchronization interface * internally for the DMI. This is no longer optional outside of this module * because the Clock must run when tl_clock isn't running or tl_reset is asserted. */ class TLDebugModule(beatBytes: Int)(implicit p: Parameters) extends LazyModule { val device = new SimpleDevice("debug-controller", Seq("sifive,debug-013","riscv,debug-013")){ override val alwaysExtended = true override def describe(resources: ResourceBindings): Description = { val Description(name, mapping) = super.describe(resources) val attach = Map( "debug-attach" -> ( (if (p(ExportDebug).apb) Seq(ResourceString("apb")) else Seq()) ++ (if (p(ExportDebug).jtag) Seq(ResourceString("jtag")) else Seq()) ++ (if (p(ExportDebug).cjtag) Seq(ResourceString("cjtag")) else Seq()) ++ (if (p(ExportDebug).dmi) Seq(ResourceString("dmi")) else Seq()))) Description(name, mapping ++ attach) } } val dmOuter : TLDebugModuleOuterAsync = LazyModule(new TLDebugModuleOuterAsync(device)(p)) val dmInner : TLDebugModuleInnerAsync = LazyModule(new TLDebugModuleInnerAsync(device, () => {dmOuter.dmOuter.intnode.edges.out.size}, beatBytes)(p)) val node = dmInner.tlNode val intnode = dmOuter.intnode val apbNodeOpt = dmOuter.apbNodeOpt dmInner.dmiNode := dmOuter.dmiInnerNode lazy val module = new Impl class Impl extends LazyRawModuleImp(this) { val nComponents = dmOuter.dmOuter.intnode.edges.out.size // Clock/reset domains: // tl_clock / tl_reset = tilelink domain // debug_clock / debug_reset = Inner debug (synchronous to tl_clock) // apb_clock / apb_reset = Outer debug with APB // dmiClock / dmiReset = Outer debug without APB // val io = IO(new Bundle { val debug_clock = Input(Clock()) val debug_reset = Input(Reset()) val tl_clock = Input(Clock()) val tl_reset = Input(Reset()) /** Debug control signals generated in Outer */ val ctrl = new DebugCtrlBundle(nComponents) /** Debug Module Interface bewteen DM and DTM * * The DTM provides access to one or more Debug Modules (DMs) using DMI */ val dmi = (!p(ExportDebug).apb).option(Flipped(new ClockedDMIIO())) val apb_clock = p(ExportDebug).apb.option(Input(Clock())) val apb_reset = p(ExportDebug).apb.option(Input(Reset())) val extTrigger = (p(DebugModuleKey).get.nExtTriggers > 0).option(new DebugExtTriggerIO()) /** vector to indicate which hart is in reset * * dm receives it from core and sends it to Inner */ val hartIsInReset = Input(Vec(nComponents, Bool())) /** hart reset request generated by hartreset-logic in Outer */ val hartResetReq = p(DebugModuleKey).get.hasHartResets.option(Output(Vec(nComponents, Bool()))) /** Debug Authentication signals from core */ val auth = p(DebugModuleKey).get.hasAuthentication.option(new DebugAuthenticationIO()) }) childClock := io.tl_clock childReset := io.tl_reset override def provideImplicitClockToLazyChildren = true dmOuter.module.io.dmi.foreach { dmOuterDMI => dmOuterDMI <> io.dmi.get.dmi dmOuter.module.io.dmi_reset := io.dmi.get.dmiReset dmOuter.module.io.dmi_clock := io.dmi.get.dmiClock dmOuter.module.rf_reset := io.dmi.get.dmiReset } (io.apb_clock zip io.apb_reset) foreach { case (c, r) => dmOuter.module.io.dmi_reset := r dmOuter.module.io.dmi_clock := c dmOuter.module.rf_reset := r } dmInner.module.rf_reset := io.debug_reset dmInner.module.io.debug_clock := io.debug_clock dmInner.module.io.debug_reset := io.debug_reset dmInner.module.io.tl_clock := io.tl_clock dmInner.module.io.tl_reset := io.tl_reset dmInner.module.io.innerCtrl <> dmOuter.module.io.innerCtrl dmInner.module.io.dmactive := dmOuter.module.io.ctrl.dmactive dmInner.module.io.debugUnavail := io.ctrl.debugUnavail dmOuter.module.io.hgDebugInt := dmInner.module.io.hgDebugInt io.ctrl <> dmOuter.module.io.ctrl io.extTrigger.foreach { x => dmInner.module.io.extTrigger.foreach {y => x <> y}} dmInner.module.io.hartIsInReset := io.hartIsInReset io.hartResetReq.foreach { x => dmOuter.module.io.hartResetReq.foreach {y => x := y}} io.auth.foreach { x => dmOuter.module.io.dmAuthenticated.get := x.dmAuthenticated } io.auth.foreach { x => dmInner.module.io.auth.foreach {y => x <> y}} } }

module TLDebugModuleInnerAsync( // @[Debug.scala:1871:9] input [2:0] auto_dmiXing_in_a_mem_0_opcode, // @[LazyModuleImp.scala:107:25] input [8:0] auto_dmiXing_in_a_mem_0_address, // @[LazyModuleImp.scala:107:25] input [31:0] auto_dmiXing_in_a_mem_0_data, // @[LazyModuleImp.scala:107:25] output auto_dmiXing_in_a_ridx, // @[LazyModuleImp.scala:107:25] input auto_dmiXing_in_a_widx, // @[LazyModuleImp.scala:107:25] output auto_dmiXing_in_a_safe_ridx_valid, // @[LazyModuleImp.scala:107:25] input auto_dmiXing_in_a_safe_widx_valid, // @[LazyModuleImp.scala:107:25] input auto_dmiXing_in_a_safe_source_reset_n, // @[LazyModuleImp.scala:107:25] output auto_dmiXing_in_a_safe_sink_reset_n, // @[LazyModuleImp.scala:107:25] output [2:0] auto_dmiXing_in_d_mem_0_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_dmiXing_in_d_mem_0_size, // @[LazyModuleImp.scala:107:25] output auto_dmiXing_in_d_mem_0_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_dmiXing_in_d_mem_0_data, // @[LazyModuleImp.scala:107:25] input auto_dmiXing_in_d_ridx, // @[LazyModuleImp.scala:107:25] output auto_dmiXing_in_d_widx, // @[LazyModuleImp.scala:107:25] input auto_dmiXing_in_d_safe_ridx_valid, // @[LazyModuleImp.scala:107:25] output auto_dmiXing_in_d_safe_widx_valid, // @[LazyModuleImp.scala:107:25] output auto_dmiXing_in_d_safe_source_reset_n, // @[LazyModuleImp.scala:107:25] input auto_dmiXing_in_d_safe_sink_reset_n, // @[LazyModuleImp.scala:107:25] input auto_dmInner_sb2tlOpt_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_dmInner_sb2tlOpt_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_dmInner_sb2tlOpt_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [3:0] auto_dmInner_sb2tlOpt_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [31:0] auto_dmInner_sb2tlOpt_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_dmInner_sb2tlOpt_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_dmInner_sb2tlOpt_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_dmInner_sb2tlOpt_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_dmInner_sb2tlOpt_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_dmInner_sb2tlOpt_out_d_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_dmInner_sb2tlOpt_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [6:0] auto_dmInner_sb2tlOpt_out_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_dmInner_sb2tlOpt_out_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [7:0] auto_dmInner_sb2tlOpt_out_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_dmInner_sb2tlOpt_out_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_dmInner_tl_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_dmInner_tl_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_dmInner_tl_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_dmInner_tl_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [1:0] auto_dmInner_tl_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [10:0] auto_dmInner_tl_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [11:0] auto_dmInner_tl_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_dmInner_tl_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_dmInner_tl_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_dmInner_tl_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_dmInner_tl_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_dmInner_tl_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_dmInner_tl_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_dmInner_tl_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [10:0] auto_dmInner_tl_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output [63:0] auto_dmInner_tl_in_d_bits_data, // @[LazyModuleImp.scala:107:25] input io_debug_clock, // @[Debug.scala:1877:16] input io_debug_reset, // @[Debug.scala:1877:16] input io_tl_clock, // @[Debug.scala:1877:16] input io_tl_reset, // @[Debug.scala:1877:16] input io_dmactive, // @[Debug.scala:1877:16] input io_innerCtrl_mem_0_resumereq, // @[Debug.scala:1877:16] input [9:0] io_innerCtrl_mem_0_hartsel, // @[Debug.scala:1877:16] input io_innerCtrl_mem_0_ackhavereset, // @[Debug.scala:1877:16] input io_innerCtrl_mem_0_hrmask_0, // @[Debug.scala:1877:16] output io_innerCtrl_ridx, // @[Debug.scala:1877:16] input io_innerCtrl_widx, // @[Debug.scala:1877:16] output io_innerCtrl_safe_ridx_valid, // @[Debug.scala:1877:16] input io_innerCtrl_safe_widx_valid, // @[Debug.scala:1877:16] input io_innerCtrl_safe_source_reset_n, // @[Debug.scala:1877:16] output io_innerCtrl_safe_sink_reset_n, // @[Debug.scala:1877:16] output io_hgDebugInt_0, // @[Debug.scala:1877:16] input io_hartIsInReset_0, // @[Debug.scala:1877:16] input rf_reset // @[Debug.scala:1904:22] ); wire _dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_valid; // @[AsyncQueue.scala:211:22] wire _dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_bits_resumereq; // @[AsyncQueue.scala:211:22] wire [9:0] _dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_bits_hartsel; // @[AsyncQueue.scala:211:22] wire _dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_bits_ackhavereset; // @[AsyncQueue.scala:211:22] wire _dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_bits_hasel; // @[AsyncQueue.scala:211:22] wire _dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_bits_hamask_0; // @[AsyncQueue.scala:211:22] wire _dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_bits_hrmask_0; // @[AsyncQueue.scala:211:22] wire _dmiXing_auto_out_a_valid; // @[Debug.scala:1858:27] wire [2:0] _dmiXing_auto_out_a_bits_opcode; // @[Debug.scala:1858:27] wire [2:0] _dmiXing_auto_out_a_bits_param; // @[Debug.scala:1858:27] wire [1:0] _dmiXing_auto_out_a_bits_size; // @[Debug.scala:1858:27] wire _dmiXing_auto_out_a_bits_source; // @[Debug.scala:1858:27] wire [8:0] _dmiXing_auto_out_a_bits_address; // @[Debug.scala:1858:27] wire [3:0] _dmiXing_auto_out_a_bits_mask; // @[Debug.scala:1858:27] wire [31:0] _dmiXing_auto_out_a_bits_data; // @[Debug.scala:1858:27] wire _dmiXing_auto_out_a_bits_corrupt; // @[Debug.scala:1858:27] wire _dmiXing_auto_out_d_ready; // @[Debug.scala:1858:27] wire _dmInner_auto_dmi_in_a_ready; // @[Debug.scala:1857:27] wire _dmInner_auto_dmi_in_d_valid; // @[Debug.scala:1857:27] wire [2:0] _dmInner_auto_dmi_in_d_bits_opcode; // @[Debug.scala:1857:27] wire [1:0] _dmInner_auto_dmi_in_d_bits_size; // @[Debug.scala:1857:27] wire _dmInner_auto_dmi_in_d_bits_source; // @[Debug.scala:1857:27] wire [31:0] _dmInner_auto_dmi_in_d_bits_data; // @[Debug.scala:1857:27] wire [2:0] auto_dmiXing_in_a_mem_0_opcode_0 = auto_dmiXing_in_a_mem_0_opcode; // @[Debug.scala:1871:9] wire [8:0] auto_dmiXing_in_a_mem_0_address_0 = auto_dmiXing_in_a_mem_0_address; // @[Debug.scala:1871:9] wire [31:0] auto_dmiXing_in_a_mem_0_data_0 = auto_dmiXing_in_a_mem_0_data; // @[Debug.scala:1871:9] wire auto_dmiXing_in_a_widx_0 = auto_dmiXing_in_a_widx; // @[Debug.scala:1871:9] wire auto_dmiXing_in_a_safe_widx_valid_0 = auto_dmiXing_in_a_safe_widx_valid; // @[Debug.scala:1871:9] wire auto_dmiXing_in_a_safe_source_reset_n_0 = auto_dmiXing_in_a_safe_source_reset_n; // @[Debug.scala:1871:9] wire auto_dmiXing_in_d_ridx_0 = auto_dmiXing_in_d_ridx; // @[Debug.scala:1871:9] wire auto_dmiXing_in_d_safe_ridx_valid_0 = auto_dmiXing_in_d_safe_ridx_valid; // @[Debug.scala:1871:9] wire auto_dmiXing_in_d_safe_sink_reset_n_0 = auto_dmiXing_in_d_safe_sink_reset_n; // @[Debug.scala:1871:9] wire auto_dmInner_sb2tlOpt_out_a_ready_0 = auto_dmInner_sb2tlOpt_out_a_ready; // @[Debug.scala:1871:9] wire auto_dmInner_sb2tlOpt_out_d_valid_0 = auto_dmInner_sb2tlOpt_out_d_valid; // @[Debug.scala:1871:9] wire [2:0] auto_dmInner_sb2tlOpt_out_d_bits_opcode_0 = auto_dmInner_sb2tlOpt_out_d_bits_opcode; // @[Debug.scala:1871:9] wire [1:0] auto_dmInner_sb2tlOpt_out_d_bits_param_0 = auto_dmInner_sb2tlOpt_out_d_bits_param; // @[Debug.scala:1871:9] wire [3:0] auto_dmInner_sb2tlOpt_out_d_bits_size_0 = auto_dmInner_sb2tlOpt_out_d_bits_size; // @[Debug.scala:1871:9] wire [6:0] auto_dmInner_sb2tlOpt_out_d_bits_sink_0 = auto_dmInner_sb2tlOpt_out_d_bits_sink; // @[Debug.scala:1871:9] wire auto_dmInner_sb2tlOpt_out_d_bits_denied_0 = auto_dmInner_sb2tlOpt_out_d_bits_denied; // @[Debug.scala:1871:9] wire [7:0] auto_dmInner_sb2tlOpt_out_d_bits_data_0 = auto_dmInner_sb2tlOpt_out_d_bits_data; // @[Debug.scala:1871:9] wire auto_dmInner_sb2tlOpt_out_d_bits_corrupt_0 = auto_dmInner_sb2tlOpt_out_d_bits_corrupt; // @[Debug.scala:1871:9] wire auto_dmInner_tl_in_a_valid_0 = auto_dmInner_tl_in_a_valid; // @[Debug.scala:1871:9] wire [2:0] auto_dmInner_tl_in_a_bits_opcode_0 = auto_dmInner_tl_in_a_bits_opcode; // @[Debug.scala:1871:9] wire [2:0] auto_dmInner_tl_in_a_bits_param_0 = auto_dmInner_tl_in_a_bits_param; // @[Debug.scala:1871:9] wire [1:0] auto_dmInner_tl_in_a_bits_size_0 = auto_dmInner_tl_in_a_bits_size; // @[Debug.scala:1871:9] wire [10:0] auto_dmInner_tl_in_a_bits_source_0 = auto_dmInner_tl_in_a_bits_source; // @[Debug.scala:1871:9] wire [11:0] auto_dmInner_tl_in_a_bits_address_0 = auto_dmInner_tl_in_a_bits_address; // @[Debug.scala:1871:9] wire [7:0] auto_dmInner_tl_in_a_bits_mask_0 = auto_dmInner_tl_in_a_bits_mask; // @[Debug.scala:1871:9] wire [63:0] auto_dmInner_tl_in_a_bits_data_0 = auto_dmInner_tl_in_a_bits_data; // @[Debug.scala:1871:9] wire auto_dmInner_tl_in_a_bits_corrupt_0 = auto_dmInner_tl_in_a_bits_corrupt; // @[Debug.scala:1871:9] wire auto_dmInner_tl_in_d_ready_0 = auto_dmInner_tl_in_d_ready; // @[Debug.scala:1871:9] wire io_debug_clock_0 = io_debug_clock; // @[Debug.scala:1871:9] wire io_debug_reset_0 = io_debug_reset; // @[Debug.scala:1871:9] wire io_tl_clock_0 = io_tl_clock; // @[Debug.scala:1871:9] wire io_tl_reset_0 = io_tl_reset; // @[Debug.scala:1871:9] wire io_dmactive_0 = io_dmactive; // @[Debug.scala:1871:9] wire io_innerCtrl_mem_0_resumereq_0 = io_innerCtrl_mem_0_resumereq; // @[Debug.scala:1871:9] wire [9:0] io_innerCtrl_mem_0_hartsel_0 = io_innerCtrl_mem_0_hartsel; // @[Debug.scala:1871:9] wire io_innerCtrl_mem_0_ackhavereset_0 = io_innerCtrl_mem_0_ackhavereset; // @[Debug.scala:1871:9] wire io_innerCtrl_mem_0_hrmask_0_0 = io_innerCtrl_mem_0_hrmask_0; // @[Debug.scala:1871:9] wire io_innerCtrl_widx_0 = io_innerCtrl_widx; // @[Debug.scala:1871:9] wire io_innerCtrl_safe_widx_valid_0 = io_innerCtrl_safe_widx_valid; // @[Debug.scala:1871:9] wire io_innerCtrl_safe_source_reset_n_0 = io_innerCtrl_safe_source_reset_n; // @[Debug.scala:1871:9] wire io_hartIsInReset_0_0 = io_hartIsInReset_0; // @[Debug.scala:1871:9] wire auto_dmiXing_in_a_mem_0_source = 1'h0; // @[Debug.scala:1871:9] wire auto_dmiXing_in_a_mem_0_corrupt = 1'h0; // @[Debug.scala:1871:9] wire auto_dmiXing_in_b_mem_0_source = 1'h0; // @[Debug.scala:1871:9] wire auto_dmiXing_in_b_mem_0_corrupt = 1'h0; // @[Debug.scala:1871:9] wire auto_dmiXing_in_b_ridx = 1'h0; // @[Debug.scala:1871:9] wire auto_dmiXing_in_b_widx = 1'h0; // @[Debug.scala:1871:9] wire auto_dmiXing_in_b_safe_ridx_valid = 1'h0; // @[Debug.scala:1871:9] wire auto_dmiXing_in_b_safe_widx_valid = 1'h0; // @[Debug.scala:1871:9] wire auto_dmiXing_in_b_safe_source_reset_n = 1'h0; // @[Debug.scala:1871:9] wire auto_dmiXing_in_b_safe_sink_reset_n = 1'h0; // @[Debug.scala:1871:9] wire auto_dmiXing_in_c_mem_0_source = 1'h0; // @[Debug.scala:1871:9] wire auto_dmiXing_in_c_mem_0_corrupt = 1'h0; // @[Debug.scala:1871:9] wire auto_dmiXing_in_c_ridx = 1'h0; // @[Debug.scala:1871:9] wire auto_dmiXing_in_c_widx = 1'h0; // @[Debug.scala:1871:9] wire auto_dmiXing_in_c_safe_ridx_valid = 1'h0; // @[Debug.scala:1871:9] wire auto_dmiXing_in_c_safe_widx_valid = 1'h0; // @[Debug.scala:1871:9] wire auto_dmiXing_in_c_safe_source_reset_n = 1'h0; // @[Debug.scala:1871:9] wire auto_dmiXing_in_c_safe_sink_reset_n = 1'h0; // @[Debug.scala:1871:9] wire auto_dmiXing_in_d_mem_0_sink = 1'h0; // @[Debug.scala:1871:9] wire auto_dmiXing_in_d_mem_0_denied = 1'h0; // @[Debug.scala:1871:9] wire auto_dmiXing_in_d_mem_0_corrupt = 1'h0; // @[Debug.scala:1871:9] wire auto_dmiXing_in_e_mem_0_sink = 1'h0; // @[Debug.scala:1871:9] wire auto_dmiXing_in_e_ridx = 1'h0; // @[Debug.scala:1871:9] wire auto_dmiXing_in_e_widx = 1'h0; // @[Debug.scala:1871:9] wire auto_dmiXing_in_e_safe_ridx_valid = 1'h0; // @[Debug.scala:1871:9] wire auto_dmiXing_in_e_safe_widx_valid = 1'h0; // @[Debug.scala:1871:9] wire auto_dmiXing_in_e_safe_source_reset_n = 1'h0; // @[Debug.scala:1871:9] wire auto_dmiXing_in_e_safe_sink_reset_n = 1'h0; // @[Debug.scala:1871:9] wire auto_dmInner_sb2tlOpt_out_a_bits_source = 1'h0; // @[Debug.scala:1871:9] wire auto_dmInner_sb2tlOpt_out_a_bits_corrupt = 1'h0; // @[Debug.scala:1871:9] wire auto_dmInner_sb2tlOpt_out_d_bits_source = 1'h0; // @[Debug.scala:1871:9] wire auto_dmInner_custom_in_addr = 1'h0; // @[Debug.scala:1871:9] wire auto_dmInner_custom_in_ready = 1'h0; // @[Debug.scala:1871:9] wire auto_dmInner_custom_in_valid = 1'h0; // @[Debug.scala:1871:9] wire auto_dmInner_tl_in_d_bits_sink = 1'h0; // @[Debug.scala:1871:9] wire auto_dmInner_tl_in_d_bits_denied = 1'h0; // @[Debug.scala:1871:9] wire auto_dmInner_tl_in_d_bits_corrupt = 1'h0; // @[Debug.scala:1871:9] wire io_innerCtrl_mem_0_hasel = 1'h0; // @[Debug.scala:1871:9] wire io_innerCtrl_mem_0_hamask_0 = 1'h0; // @[Debug.scala:1871:9] wire io_debugUnavail_0 = 1'h0; // @[Debug.scala:1871:9] wire _childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25] wire auto_dmInner_sb2tlOpt_out_a_bits_mask = 1'h1; // @[AsyncQueue.scala:211:22] wire [31:0] auto_dmiXing_in_b_mem_0_data = 32'h0; // @[Debug.scala:1858:27, :1871:9] wire [31:0] auto_dmiXing_in_c_mem_0_data = 32'h0; // @[Debug.scala:1858:27, :1871:9] wire [3:0] auto_dmiXing_in_b_mem_0_mask = 4'h0; // @[Debug.scala:1858:27, :1871:9] wire [8:0] auto_dmiXing_in_b_mem_0_address = 9'h0; // @[Debug.scala:1858:27, :1871:9] wire [8:0] auto_dmiXing_in_c_mem_0_address = 9'h0; // @[Debug.scala:1858:27, :1871:9] wire [1:0] auto_dmiXing_in_b_mem_0_param = 2'h0; // @[Debug.scala:1871:9] wire [1:0] auto_dmiXing_in_b_mem_0_size = 2'h0; // @[Debug.scala:1871:9] wire [1:0] auto_dmiXing_in_c_mem_0_size = 2'h0; // @[Debug.scala:1871:9] wire [1:0] auto_dmiXing_in_d_mem_0_param = 2'h0; // @[Debug.scala:1871:9] wire [1:0] auto_dmInner_tl_in_d_bits_param = 2'h0; // @[Debug.scala:1871:9] wire [3:0] auto_dmiXing_in_a_mem_0_mask = 4'hF; // @[Debug.scala:1858:27, :1871:9] wire [1:0] auto_dmiXing_in_a_mem_0_size = 2'h2; // @[Debug.scala:1858:27, :1871:9] wire [2:0] auto_dmiXing_in_a_mem_0_param = 3'h0; // @[Debug.scala:1871:9] wire [2:0] auto_dmiXing_in_b_mem_0_opcode = 3'h0; // @[Debug.scala:1871:9] wire [2:0] auto_dmiXing_in_c_mem_0_opcode = 3'h0; // @[Debug.scala:1871:9] wire [2:0] auto_dmiXing_in_c_mem_0_param = 3'h0; // @[Debug.scala:1871:9] wire [2:0] auto_dmInner_sb2tlOpt_out_a_bits_param = 3'h0; // @[Debug.scala:1871:9] wire childClock = io_debug_clock_0; // @[Debug.scala:1871:9] wire childReset = io_debug_reset_0; // @[Debug.scala:1871:9] wire auto_dmiXing_in_a_safe_ridx_valid_0; // @[Debug.scala:1871:9] wire auto_dmiXing_in_a_safe_sink_reset_n_0; // @[Debug.scala:1871:9] wire auto_dmiXing_in_a_ridx_0; // @[Debug.scala:1871:9] wire [2:0] auto_dmiXing_in_d_mem_0_opcode_0; // @[Debug.scala:1871:9] wire [1:0] auto_dmiXing_in_d_mem_0_size_0; // @[Debug.scala:1871:9] wire auto_dmiXing_in_d_mem_0_source_0; // @[Debug.scala:1871:9] wire [31:0] auto_dmiXing_in_d_mem_0_data_0; // @[Debug.scala:1871:9] wire auto_dmiXing_in_d_safe_widx_valid_0; // @[Debug.scala:1871:9] wire auto_dmiXing_in_d_safe_source_reset_n_0; // @[Debug.scala:1871:9] wire auto_dmiXing_in_d_widx_0; // @[Debug.scala:1871:9] wire [2:0] auto_dmInner_sb2tlOpt_out_a_bits_opcode_0; // @[Debug.scala:1871:9] wire [3:0] auto_dmInner_sb2tlOpt_out_a_bits_size_0; // @[Debug.scala:1871:9] wire [31:0] auto_dmInner_sb2tlOpt_out_a_bits_address_0; // @[Debug.scala:1871:9] wire [7:0] auto_dmInner_sb2tlOpt_out_a_bits_data_0; // @[Debug.scala:1871:9] wire auto_dmInner_sb2tlOpt_out_a_valid_0; // @[Debug.scala:1871:9] wire auto_dmInner_sb2tlOpt_out_d_ready_0; // @[Debug.scala:1871:9] wire auto_dmInner_tl_in_a_ready_0; // @[Debug.scala:1871:9] wire [2:0] auto_dmInner_tl_in_d_bits_opcode_0; // @[Debug.scala:1871:9] wire [1:0] auto_dmInner_tl_in_d_bits_size_0; // @[Debug.scala:1871:9] wire [10:0] auto_dmInner_tl_in_d_bits_source_0; // @[Debug.scala:1871:9] wire [63:0] auto_dmInner_tl_in_d_bits_data_0; // @[Debug.scala:1871:9] wire auto_dmInner_tl_in_d_valid_0; // @[Debug.scala:1871:9] wire io_innerCtrl_safe_ridx_valid_0; // @[Debug.scala:1871:9] wire io_innerCtrl_safe_sink_reset_n_0; // @[Debug.scala:1871:9] wire io_innerCtrl_ridx_0; // @[Debug.scala:1871:9] wire io_hgDebugInt_0_0; // @[Debug.scala:1871:9] wire dmactive_synced; // @[ShiftReg.scala:48:24] TLDebugModuleInner dmInner ( // @[Debug.scala:1857:27] .clock (io_debug_clock_0), // @[Debug.scala:1871:9] .reset (io_debug_reset_0), // @[Debug.scala:1871:9] .auto_sb2tlOpt_out_a_ready (auto_dmInner_sb2tlOpt_out_a_ready_0), // @[Debug.scala:1871:9] .auto_sb2tlOpt_out_a_valid (auto_dmInner_sb2tlOpt_out_a_valid_0), .auto_sb2tlOpt_out_a_bits_opcode (auto_dmInner_sb2tlOpt_out_a_bits_opcode_0), .auto_sb2tlOpt_out_a_bits_size (auto_dmInner_sb2tlOpt_out_a_bits_size_0), .auto_sb2tlOpt_out_a_bits_address (auto_dmInner_sb2tlOpt_out_a_bits_address_0), .auto_sb2tlOpt_out_a_bits_data (auto_dmInner_sb2tlOpt_out_a_bits_data_0), .auto_sb2tlOpt_out_d_ready (auto_dmInner_sb2tlOpt_out_d_ready_0), .auto_sb2tlOpt_out_d_valid (auto_dmInner_sb2tlOpt_out_d_valid_0), // @[Debug.scala:1871:9] .auto_sb2tlOpt_out_d_bits_opcode (auto_dmInner_sb2tlOpt_out_d_bits_opcode_0), // @[Debug.scala:1871:9] .auto_sb2tlOpt_out_d_bits_param (auto_dmInner_sb2tlOpt_out_d_bits_param_0), // @[Debug.scala:1871:9] .auto_sb2tlOpt_out_d_bits_size (auto_dmInner_sb2tlOpt_out_d_bits_size_0), // @[Debug.scala:1871:9] .auto_sb2tlOpt_out_d_bits_sink (auto_dmInner_sb2tlOpt_out_d_bits_sink_0), // @[Debug.scala:1871:9] .auto_sb2tlOpt_out_d_bits_denied (auto_dmInner_sb2tlOpt_out_d_bits_denied_0), // @[Debug.scala:1871:9] .auto_sb2tlOpt_out_d_bits_data (auto_dmInner_sb2tlOpt_out_d_bits_data_0), // @[Debug.scala:1871:9] .auto_sb2tlOpt_out_d_bits_corrupt (auto_dmInner_sb2tlOpt_out_d_bits_corrupt_0), // @[Debug.scala:1871:9] .auto_tl_in_a_ready (auto_dmInner_tl_in_a_ready_0), .auto_tl_in_a_valid (auto_dmInner_tl_in_a_valid_0), // @[Debug.scala:1871:9] .auto_tl_in_a_bits_opcode (auto_dmInner_tl_in_a_bits_opcode_0), // @[Debug.scala:1871:9] .auto_tl_in_a_bits_param (auto_dmInner_tl_in_a_bits_param_0), // @[Debug.scala:1871:9] .auto_tl_in_a_bits_size (auto_dmInner_tl_in_a_bits_size_0), // @[Debug.scala:1871:9] .auto_tl_in_a_bits_source (auto_dmInner_tl_in_a_bits_source_0), // @[Debug.scala:1871:9] .auto_tl_in_a_bits_address (auto_dmInner_tl_in_a_bits_address_0), // @[Debug.scala:1871:9] .auto_tl_in_a_bits_mask (auto_dmInner_tl_in_a_bits_mask_0), // @[Debug.scala:1871:9] .auto_tl_in_a_bits_data (auto_dmInner_tl_in_a_bits_data_0), // @[Debug.scala:1871:9] .auto_tl_in_a_bits_corrupt (auto_dmInner_tl_in_a_bits_corrupt_0), // @[Debug.scala:1871:9] .auto_tl_in_d_ready (auto_dmInner_tl_in_d_ready_0), // @[Debug.scala:1871:9] .auto_tl_in_d_valid (auto_dmInner_tl_in_d_valid_0), .auto_tl_in_d_bits_opcode (auto_dmInner_tl_in_d_bits_opcode_0), .auto_tl_in_d_bits_size (auto_dmInner_tl_in_d_bits_size_0), .auto_tl_in_d_bits_source (auto_dmInner_tl_in_d_bits_source_0), .auto_tl_in_d_bits_data (auto_dmInner_tl_in_d_bits_data_0), .auto_dmi_in_a_ready (_dmInner_auto_dmi_in_a_ready), .auto_dmi_in_a_valid (_dmiXing_auto_out_a_valid), // @[Debug.scala:1858:27] .auto_dmi_in_a_bits_opcode (_dmiXing_auto_out_a_bits_opcode), // @[Debug.scala:1858:27] .auto_dmi_in_a_bits_param (_dmiXing_auto_out_a_bits_param), // @[Debug.scala:1858:27] .auto_dmi_in_a_bits_size (_dmiXing_auto_out_a_bits_size), // @[Debug.scala:1858:27] .auto_dmi_in_a_bits_source (_dmiXing_auto_out_a_bits_source), // @[Debug.scala:1858:27] .auto_dmi_in_a_bits_address (_dmiXing_auto_out_a_bits_address), // @[Debug.scala:1858:27] .auto_dmi_in_a_bits_mask (_dmiXing_auto_out_a_bits_mask), // @[Debug.scala:1858:27] .auto_dmi_in_a_bits_data (_dmiXing_auto_out_a_bits_data), // @[Debug.scala:1858:27] .auto_dmi_in_a_bits_corrupt (_dmiXing_auto_out_a_bits_corrupt), // @[Debug.scala:1858:27] .auto_dmi_in_d_ready (_dmiXing_auto_out_d_ready), // @[Debug.scala:1858:27] .auto_dmi_in_d_valid (_dmInner_auto_dmi_in_d_valid), .auto_dmi_in_d_bits_opcode (_dmInner_auto_dmi_in_d_bits_opcode), .auto_dmi_in_d_bits_size (_dmInner_auto_dmi_in_d_bits_size), .auto_dmi_in_d_bits_source (_dmInner_auto_dmi_in_d_bits_source), .auto_dmi_in_d_bits_data (_dmInner_auto_dmi_in_d_bits_data), .io_dmactive (dmactive_synced), // @[ShiftReg.scala:48:24] .io_innerCtrl_valid (_dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_valid), // @[AsyncQueue.scala:211:22] .io_innerCtrl_bits_resumereq (_dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_bits_resumereq), // @[AsyncQueue.scala:211:22] .io_innerCtrl_bits_hartsel (_dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_bits_hartsel), // @[AsyncQueue.scala:211:22] .io_innerCtrl_bits_ackhavereset (_dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_bits_ackhavereset), // @[AsyncQueue.scala:211:22] .io_innerCtrl_bits_hasel (_dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_bits_hasel), // @[AsyncQueue.scala:211:22] .io_innerCtrl_bits_hamask_0 (_dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_bits_hamask_0), // @[AsyncQueue.scala:211:22] .io_innerCtrl_bits_hrmask_0 (_dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_bits_hrmask_0), // @[AsyncQueue.scala:211:22] .io_hgDebugInt_0 (io_hgDebugInt_0_0), .io_hartIsInReset_0 (io_hartIsInReset_0_0), // @[Debug.scala:1871:9] .io_tl_clock (io_tl_clock_0), // @[Debug.scala:1871:9] .io_tl_reset (io_tl_reset_0) // @[Debug.scala:1871:9] ); // @[Debug.scala:1857:27] TLAsyncCrossingSink_a9d32s1k1z2u dmiXing ( // @[Debug.scala:1858:27] .clock (childClock), // @[LazyModuleImp.scala:155:31] .reset (childReset), // @[LazyModuleImp.scala:158:31] .auto_in_a_mem_0_opcode (auto_dmiXing_in_a_mem_0_opcode_0), // @[Debug.scala:1871:9] .auto_in_a_mem_0_address (auto_dmiXing_in_a_mem_0_address_0), // @[Debug.scala:1871:9] .auto_in_a_mem_0_data (auto_dmiXing_in_a_mem_0_data_0), // @[Debug.scala:1871:9] .auto_in_a_ridx (auto_dmiXing_in_a_ridx_0), .auto_in_a_widx (auto_dmiXing_in_a_widx_0), // @[Debug.scala:1871:9] .auto_in_a_safe_ridx_valid (auto_dmiXing_in_a_safe_ridx_valid_0), .auto_in_a_safe_widx_valid (auto_dmiXing_in_a_safe_widx_valid_0), // @[Debug.scala:1871:9] .auto_in_a_safe_source_reset_n (auto_dmiXing_in_a_safe_source_reset_n_0), // @[Debug.scala:1871:9] .auto_in_a_safe_sink_reset_n (auto_dmiXing_in_a_safe_sink_reset_n_0), .auto_in_d_mem_0_opcode (auto_dmiXing_in_d_mem_0_opcode_0), .auto_in_d_mem_0_size (auto_dmiXing_in_d_mem_0_size_0), .auto_in_d_mem_0_source (auto_dmiXing_in_d_mem_0_source_0), .auto_in_d_mem_0_data (auto_dmiXing_in_d_mem_0_data_0), .auto_in_d_ridx (auto_dmiXing_in_d_ridx_0), // @[Debug.scala:1871:9] .auto_in_d_widx (auto_dmiXing_in_d_widx_0), .auto_in_d_safe_ridx_valid (auto_dmiXing_in_d_safe_ridx_valid_0), // @[Debug.scala:1871:9] .auto_in_d_safe_widx_valid (auto_dmiXing_in_d_safe_widx_valid_0), .auto_in_d_safe_source_reset_n (auto_dmiXing_in_d_safe_source_reset_n_0), .auto_in_d_safe_sink_reset_n (auto_dmiXing_in_d_safe_sink_reset_n_0), // @[Debug.scala:1871:9] .auto_out_a_ready (_dmInner_auto_dmi_in_a_ready), // @[Debug.scala:1857:27] .auto_out_a_valid (_dmiXing_auto_out_a_valid), .auto_out_a_bits_opcode (_dmiXing_auto_out_a_bits_opcode), .auto_out_a_bits_param (_dmiXing_auto_out_a_bits_param), .auto_out_a_bits_size (_dmiXing_auto_out_a_bits_size), .auto_out_a_bits_source (_dmiXing_auto_out_a_bits_source), .auto_out_a_bits_address (_dmiXing_auto_out_a_bits_address), .auto_out_a_bits_mask (_dmiXing_auto_out_a_bits_mask), .auto_out_a_bits_data (_dmiXing_auto_out_a_bits_data), .auto_out_a_bits_corrupt (_dmiXing_auto_out_a_bits_corrupt), .auto_out_d_ready (_dmiXing_auto_out_d_ready), .auto_out_d_valid (_dmInner_auto_dmi_in_d_valid), // @[Debug.scala:1857:27] .auto_out_d_bits_opcode (_dmInner_auto_dmi_in_d_bits_opcode), // @[Debug.scala:1857:27] .auto_out_d_bits_size (_dmInner_auto_dmi_in_d_bits_size), // @[Debug.scala:1857:27] .auto_out_d_bits_source (_dmInner_auto_dmi_in_d_bits_source), // @[Debug.scala:1857:27] .auto_out_d_bits_data (_dmInner_auto_dmi_in_d_bits_data) // @[Debug.scala:1857:27] ); // @[Debug.scala:1858:27] AsyncResetSynchronizerShiftReg_w1_d3_i0_27 dmactive_synced_dmactive_synced_dmactiveSync ( // @[ShiftReg.scala:45:23] .clock (childClock), // @[LazyModuleImp.scala:155:31] .reset (childReset), // @[LazyModuleImp.scala:158:31] .io_d (io_dmactive_0), // @[Debug.scala:1871:9] .io_q (dmactive_synced) ); // @[ShiftReg.scala:45:23] AsyncQueueSink_DebugInternalBundle dmactive_synced_dmInner_io_innerCtrl_sink ( // @[AsyncQueue.scala:211:22] .clock (childClock), // @[LazyModuleImp.scala:155:31] .reset (childReset), // @[LazyModuleImp.scala:158:31] .io_deq_valid (_dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_valid), .io_deq_bits_resumereq (_dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_bits_resumereq), .io_deq_bits_hartsel (_dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_bits_hartsel), .io_deq_bits_ackhavereset (_dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_bits_ackhavereset), .io_deq_bits_hasel (_dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_bits_hasel), .io_deq_bits_hamask_0 (_dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_bits_hamask_0), .io_deq_bits_hrmask_0 (_dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_bits_hrmask_0), .io_async_mem_0_resumereq (io_innerCtrl_mem_0_resumereq_0), // @[Debug.scala:1871:9] .io_async_mem_0_hartsel (io_innerCtrl_mem_0_hartsel_0), // @[Debug.scala:1871:9] .io_async_mem_0_ackhavereset (io_innerCtrl_mem_0_ackhavereset_0), // @[Debug.scala:1871:9] .io_async_mem_0_hrmask_0 (io_innerCtrl_mem_0_hrmask_0_0), // @[Debug.scala:1871:9] .io_async_ridx (io_innerCtrl_ridx_0), .io_async_widx (io_innerCtrl_widx_0), // @[Debug.scala:1871:9] .io_async_safe_ridx_valid (io_innerCtrl_safe_ridx_valid_0), .io_async_safe_widx_valid (io_innerCtrl_safe_widx_valid_0), // @[Debug.scala:1871:9] .io_async_safe_source_reset_n (io_innerCtrl_safe_source_reset_n_0), // @[Debug.scala:1871:9] .io_async_safe_sink_reset_n (io_innerCtrl_safe_sink_reset_n_0) ); // @[AsyncQueue.scala:211:22] assign auto_dmiXing_in_a_ridx = auto_dmiXing_in_a_ridx_0; // @[Debug.scala:1871:9] assign auto_dmiXing_in_a_safe_ridx_valid = auto_dmiXing_in_a_safe_ridx_valid_0; // @[Debug.scala:1871:9] assign auto_dmiXing_in_a_safe_sink_reset_n = auto_dmiXing_in_a_safe_sink_reset_n_0; // @[Debug.scala:1871:9] assign auto_dmiXing_in_d_mem_0_opcode = auto_dmiXing_in_d_mem_0_opcode_0; // @[Debug.scala:1871:9] assign auto_dmiXing_in_d_mem_0_size = auto_dmiXing_in_d_mem_0_size_0; // @[Debug.scala:1871:9] assign auto_dmiXing_in_d_mem_0_source = auto_dmiXing_in_d_mem_0_source_0; // @[Debug.scala:1871:9] assign auto_dmiXing_in_d_mem_0_data = auto_dmiXing_in_d_mem_0_data_0; // @[Debug.scala:1871:9] assign auto_dmiXing_in_d_widx = auto_dmiXing_in_d_widx_0; // @[Debug.scala:1871:9] assign auto_dmiXing_in_d_safe_widx_valid = auto_dmiXing_in_d_safe_widx_valid_0; // @[Debug.scala:1871:9] assign auto_dmiXing_in_d_safe_source_reset_n = auto_dmiXing_in_d_safe_source_reset_n_0; // @[Debug.scala:1871:9] assign auto_dmInner_sb2tlOpt_out_a_valid = auto_dmInner_sb2tlOpt_out_a_valid_0; // @[Debug.scala:1871:9] assign auto_dmInner_sb2tlOpt_out_a_bits_opcode = auto_dmInner_sb2tlOpt_out_a_bits_opcode_0; // @[Debug.scala:1871:9] assign auto_dmInner_sb2tlOpt_out_a_bits_size = auto_dmInner_sb2tlOpt_out_a_bits_size_0; // @[Debug.scala:1871:9] assign auto_dmInner_sb2tlOpt_out_a_bits_address = auto_dmInner_sb2tlOpt_out_a_bits_address_0; // @[Debug.scala:1871:9] assign auto_dmInner_sb2tlOpt_out_a_bits_data = auto_dmInner_sb2tlOpt_out_a_bits_data_0; // @[Debug.scala:1871:9] assign auto_dmInner_sb2tlOpt_out_d_ready = auto_dmInner_sb2tlOpt_out_d_ready_0; // @[Debug.scala:1871:9] assign auto_dmInner_tl_in_a_ready = auto_dmInner_tl_in_a_ready_0; // @[Debug.scala:1871:9] assign auto_dmInner_tl_in_d_valid = auto_dmInner_tl_in_d_valid_0; // @[Debug.scala:1871:9] assign auto_dmInner_tl_in_d_bits_opcode = auto_dmInner_tl_in_d_bits_opcode_0; // @[Debug.scala:1871:9] assign auto_dmInner_tl_in_d_bits_size = auto_dmInner_tl_in_d_bits_size_0; // @[Debug.scala:1871:9] assign auto_dmInner_tl_in_d_bits_source = auto_dmInner_tl_in_d_bits_source_0; // @[Debug.scala:1871:9] assign auto_dmInner_tl_in_d_bits_data = auto_dmInner_tl_in_d_bits_data_0; // @[Debug.scala:1871:9] assign io_innerCtrl_ridx = io_innerCtrl_ridx_0; // @[Debug.scala:1871:9] assign io_innerCtrl_safe_ridx_valid = io_innerCtrl_safe_ridx_valid_0; // @[Debug.scala:1871:9] assign io_innerCtrl_safe_sink_reset_n = io_innerCtrl_safe_sink_reset_n_0; // @[Debug.scala:1871:9] assign io_hgDebugInt_0 = io_hgDebugInt_0_0; // @[Debug.scala:1871:9] endmodule

Generate the Verilog code corresponding to the following Chisel files. File SourceB.scala: /* * Copyright 2019 SiFive, Inc. * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You should have received a copy of LICENSE.Apache2 along with * this software. If not, you may obtain a copy at * * https://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ package sifive.blocks.inclusivecache import chisel3._ import chisel3.util._ import freechips.rocketchip.tilelink._ import freechips.rocketchip.util._ class SourceBRequest(params: InclusiveCacheParameters) extends InclusiveCacheBundle(params) { val param = UInt(3.W) val tag = UInt(params.tagBits.W) val set = UInt(params.setBits.W) val clients = UInt(params.clientBits.W) } class SourceB(params: InclusiveCacheParameters) extends Module { val io = IO(new Bundle { val req = Flipped(Decoupled(new SourceBRequest(params))) val b = Decoupled(new TLBundleB(params.inner.bundle)) }) if (params.firstLevel) { // Tie off unused ports io.req.ready := true.B io.b.valid := false.B io.b.bits := DontCare } else { val remain = RegInit(0.U(params.clientBits.W)) val remain_set = WireInit(init = 0.U(params.clientBits.W)) val remain_clr = WireInit(init = 0.U(params.clientBits.W)) remain := (remain | remain_set) & ~remain_clr val busy = remain.orR val todo = Mux(busy, remain, io.req.bits.clients) val next = ~(leftOR(todo) << 1) & todo if (params.clientBits > 1) { params.ccover(PopCount(remain) > 1.U, "SOURCEB_MULTI_PROBE", "Had to probe more than one client") } assert (!io.req.valid || io.req.bits.clients =/= 0.U) io.req.ready := !busy when (io.req.fire) { remain_set := io.req.bits.clients } // No restrictions on the type of buffer used here val b = Wire(chiselTypeOf(io.b)) io.b <> params.micro.innerBuf.b(b) b.valid := busy || io.req.valid when (b.fire) { remain_clr := next } params.ccover(b.valid && !b.ready, "SOURCEB_STALL", "Backpressured when issuing a probe") val tag = Mux(!busy, io.req.bits.tag, RegEnable(io.req.bits.tag, io.req.fire)) val set = Mux(!busy, io.req.bits.set, RegEnable(io.req.bits.set, io.req.fire)) val param = Mux(!busy, io.req.bits.param, RegEnable(io.req.bits.param, io.req.fire)) b.bits.opcode := TLMessages.Probe b.bits.param := param b.bits.size := params.offsetBits .U b.bits.source := params.clientSource(next) b.bits.address := params.expandAddress(tag, set, 0.U) b.bits.mask := ~0.U(params.inner.manager.beatBytes.W) b.bits.data := 0.U b.bits.corrupt := false.B } } File Parameters.scala: /* * Copyright 2019 SiFive, Inc. * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You should have received a copy of LICENSE.Apache2 along with * this software. If not, you may obtain a copy at * * https://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ package sifive.blocks.inclusivecache import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config._ import freechips.rocketchip.diplomacy._ import freechips.rocketchip.tilelink._ import freechips.rocketchip.util._ import freechips.rocketchip.util.property.cover import scala.math.{min,max} case class CacheParameters( level: Int, ways: Int, sets: Int, blockBytes: Int, beatBytes: Int, // inner hintsSkipProbe: Boolean) { require (ways > 0) require (sets > 0) require (blockBytes > 0 && isPow2(blockBytes)) require (beatBytes > 0 && isPow2(beatBytes)) require (blockBytes >= beatBytes) val blocks = ways * sets val sizeBytes = blocks * blockBytes val blockBeats = blockBytes/beatBytes } case class InclusiveCachePortParameters( a: BufferParams, b: BufferParams, c: BufferParams, d: BufferParams, e: BufferParams) { def apply()(implicit p: Parameters, valName: ValName) = LazyModule(new TLBuffer(a, b, c, d, e)) } object InclusiveCachePortParameters { val none = InclusiveCachePortParameters( a = BufferParams.none, b = BufferParams.none, c = BufferParams.none, d = BufferParams.none, e = BufferParams.none) val full = InclusiveCachePortParameters( a = BufferParams.default, b = BufferParams.default, c = BufferParams.default, d = BufferParams.default, e = BufferParams.default) // This removes feed-through paths from C=>A and A=>C val fullC = InclusiveCachePortParameters( a = BufferParams.none, b = BufferParams.none, c = BufferParams.default, d = BufferParams.none, e = BufferParams.none) val flowAD = InclusiveCachePortParameters( a = BufferParams.flow, b = BufferParams.none, c = BufferParams.none, d = BufferParams.flow, e = BufferParams.none) val flowAE = InclusiveCachePortParameters( a = BufferParams.flow, b = BufferParams.none, c = BufferParams.none, d = BufferParams.none, e = BufferParams.flow) // For innerBuf: // SinkA: no restrictions, flows into scheduler+putbuffer // SourceB: no restrictions, flows out of scheduler // sinkC: no restrictions, flows into scheduler+putbuffer & buffered to bankedStore // SourceD: no restrictions, flows out of bankedStore/regout // SinkE: no restrictions, flows into scheduler // // ... so while none is possible, you probably want at least flowAC to cut ready // from the scheduler delay and flowD to ease SourceD back-pressure // For outerBufer: // SourceA: must not be pipe, flows out of scheduler // SinkB: no restrictions, flows into scheduler // SourceC: pipe is useless, flows out of bankedStore/regout, parameter depth ignored // SinkD: no restrictions, flows into scheduler & bankedStore // SourceE: must not be pipe, flows out of scheduler // // ... AE take the channel ready into the scheduler, so you need at least flowAE } case class InclusiveCacheMicroParameters( writeBytes: Int, // backing store update granularity memCycles: Int = 40, // # of L2 clock cycles for a memory round-trip (50ns @ 800MHz) portFactor: Int = 4, // numSubBanks = (widest TL port * portFactor) / writeBytes dirReg: Boolean = false, innerBuf: InclusiveCachePortParameters = InclusiveCachePortParameters.fullC, // or none outerBuf: InclusiveCachePortParameters = InclusiveCachePortParameters.full) // or flowAE { require (writeBytes > 0 && isPow2(writeBytes)) require (memCycles > 0) require (portFactor >= 2) // for inner RMW and concurrent outer Relase + Grant } case class InclusiveCacheControlParameters( address: BigInt, beatBytes: Int, bankedControl: Boolean) case class InclusiveCacheParameters( cache: CacheParameters, micro: InclusiveCacheMicroParameters, control: Boolean, inner: TLEdgeIn, outer: TLEdgeOut)(implicit val p: Parameters) { require (cache.ways > 1) require (cache.sets > 1 && isPow2(cache.sets)) require (micro.writeBytes <= inner.manager.beatBytes) require (micro.writeBytes <= outer.manager.beatBytes) require (inner.manager.beatBytes <= cache.blockBytes) require (outer.manager.beatBytes <= cache.blockBytes) // Require that all cached address ranges have contiguous blocks outer.manager.managers.flatMap(_.address).foreach { a => require (a.alignment >= cache.blockBytes) } // If we are the first level cache, we do not need to support inner-BCE val firstLevel = !inner.client.clients.exists(_.supports.probe) // If we are the last level cache, we do not need to support outer-B val lastLevel = !outer.manager.managers.exists(_.regionType > RegionType.UNCACHED) require (lastLevel) // Provision enough resources to achieve full throughput with missing single-beat accesses val mshrs = InclusiveCacheParameters.all_mshrs(cache, micro) val secondary = max(mshrs, micro.memCycles - mshrs) val putLists = micro.memCycles // allow every request to be single beat val putBeats = max(2*cache.blockBeats, micro.memCycles) val relLists = 2 val relBeats = relLists*cache.blockBeats val flatAddresses = AddressSet.unify(outer.manager.managers.flatMap(_.address)) val pickMask = AddressDecoder(flatAddresses.map(Seq(_)), flatAddresses.map(_.mask).reduce(_|_)) def bitOffsets(x: BigInt, offset: Int = 0, tail: List[Int] = List.empty[Int]): List[Int] = if (x == 0) tail.reverse else bitOffsets(x >> 1, offset + 1, if ((x & 1) == 1) offset :: tail else tail) val addressMapping = bitOffsets(pickMask) val addressBits = addressMapping.size // println(s"addresses: ${flatAddresses} => ${pickMask} => ${addressBits}") val allClients = inner.client.clients.size val clientBitsRaw = inner.client.clients.filter(_.supports.probe).size val clientBits = max(1, clientBitsRaw) val stateBits = 2 val wayBits = log2Ceil(cache.ways) val setBits = log2Ceil(cache.sets) val offsetBits = log2Ceil(cache.blockBytes) val tagBits = addressBits - setBits - offsetBits val putBits = log2Ceil(max(putLists, relLists)) require (tagBits > 0) require (offsetBits > 0) val innerBeatBits = (offsetBits - log2Ceil(inner.manager.beatBytes)) max 1 val outerBeatBits = (offsetBits - log2Ceil(outer.manager.beatBytes)) max 1 val innerMaskBits = inner.manager.beatBytes / micro.writeBytes val outerMaskBits = outer.manager.beatBytes / micro.writeBytes def clientBit(source: UInt): UInt = { if (clientBitsRaw == 0) { 0.U } else { Cat(inner.client.clients.filter(_.supports.probe).map(_.sourceId.contains(source)).reverse) } } def clientSource(bit: UInt): UInt = { if (clientBitsRaw == 0) { 0.U } else { Mux1H(bit, inner.client.clients.filter(_.supports.probe).map(c => c.sourceId.start.U)) } } def parseAddress(x: UInt): (UInt, UInt, UInt) = { val offset = Cat(addressMapping.map(o => x(o,o)).reverse) val set = offset >> offsetBits val tag = set >> setBits (tag(tagBits-1, 0), set(setBits-1, 0), offset(offsetBits-1, 0)) } def widen(x: UInt, width: Int): UInt = { val y = x | 0.U(width.W) assert (y >> width === 0.U) y(width-1, 0) } def expandAddress(tag: UInt, set: UInt, offset: UInt): UInt = { val base = Cat(widen(tag, tagBits), widen(set, setBits), widen(offset, offsetBits)) val bits = Array.fill(outer.bundle.addressBits) { 0.U(1.W) } addressMapping.zipWithIndex.foreach { case (a, i) => bits(a) = base(i,i) } Cat(bits.reverse) } def restoreAddress(expanded: UInt): UInt = { val missingBits = flatAddresses .map { a => (a.widen(pickMask).base, a.widen(~pickMask)) } // key is the bits to restore on match .groupBy(_._1) .view .mapValues(_.map(_._2)) val muxMask = AddressDecoder(missingBits.values.toList) val mux = missingBits.toList.map { case (bits, addrs) => val widen = addrs.map(_.widen(~muxMask)) val matches = AddressSet .unify(widen.distinct) .map(_.contains(expanded)) .reduce(_ || _) (matches, bits.U) } expanded | Mux1H(mux) } def dirReg[T <: Data](x: T, en: Bool = true.B): T = { if (micro.dirReg) RegEnable(x, en) else x } def ccover(cond: Bool, label: String, desc: String)(implicit sourceInfo: SourceInfo) = cover(cond, "CCACHE_L" + cache.level + "_" + label, "MemorySystem;;" + desc) } object MetaData { val stateBits = 2 def INVALID: UInt = 0.U(stateBits.W) // way is empty def BRANCH: UInt = 1.U(stateBits.W) // outer slave cache is trunk def TRUNK: UInt = 2.U(stateBits.W) // unique inner master cache is trunk def TIP: UInt = 3.U(stateBits.W) // we are trunk, inner masters are branch // Does a request need trunk? def needT(opcode: UInt, param: UInt): Bool = { !opcode(2) || (opcode === TLMessages.Hint && param === TLHints.PREFETCH_WRITE) || ((opcode === TLMessages.AcquireBlock || opcode === TLMessages.AcquirePerm) && param =/= TLPermissions.NtoB) } // Does a request prove the client need not be probed? def skipProbeN(opcode: UInt, hintsSkipProbe: Boolean): Bool = { // Acquire(toB) and Get => is N, so no probe // Acquire(*toT) => is N or B, but need T, so no probe // Hint => could be anything, so probe IS needed, if hintsSkipProbe is enabled, skip probe the same client // Put* => is N or B, so probe IS needed opcode === TLMessages.AcquireBlock || opcode === TLMessages.AcquirePerm || opcode === TLMessages.Get || (opcode === TLMessages.Hint && hintsSkipProbe.B) } def isToN(param: UInt): Bool = { param === TLPermissions.TtoN || param === TLPermissions.BtoN || param === TLPermissions.NtoN } def isToB(param: UInt): Bool = { param === TLPermissions.TtoB || param === TLPermissions.BtoB } } object InclusiveCacheParameters { val lfsrBits = 10 val L2ControlAddress = 0x2010000 val L2ControlSize = 0x1000 def out_mshrs(cache: CacheParameters, micro: InclusiveCacheMicroParameters): Int = { // We need 2-3 normal MSHRs to cover the Directory latency // To fully exploit memory bandwidth-delay-product, we need memCyles/blockBeats MSHRs max(if (micro.dirReg) 3 else 2, (micro.memCycles + cache.blockBeats - 1) / cache.blockBeats) } def all_mshrs(cache: CacheParameters, micro: InclusiveCacheMicroParameters): Int = // We need a dedicated MSHR for B+C each 2 + out_mshrs(cache, micro) } class InclusiveCacheBundle(params: InclusiveCacheParameters) extends Bundle

module SourceB( // @[SourceB.scala:33:7] input clock, // @[SourceB.scala:33:7] input reset, // @[SourceB.scala:33:7] output io_req_ready, // @[SourceB.scala:35:14] input io_req_valid, // @[SourceB.scala:35:14] input [2:0] io_req_bits_param, // @[SourceB.scala:35:14] input [12:0] io_req_bits_tag, // @[SourceB.scala:35:14] input [9:0] io_req_bits_set, // @[SourceB.scala:35:14] input [3:0] io_req_bits_clients, // @[SourceB.scala:35:14] input io_b_ready, // @[SourceB.scala:35:14] output io_b_valid, // @[SourceB.scala:35:14] output [1:0] io_b_bits_param, // @[SourceB.scala:35:14] output [6:0] io_b_bits_source, // @[SourceB.scala:35:14] output [31:0] io_b_bits_address // @[SourceB.scala:35:14] ); wire io_req_valid_0 = io_req_valid; // @[SourceB.scala:33:7] wire [2:0] io_req_bits_param_0 = io_req_bits_param; // @[SourceB.scala:33:7] wire [12:0] io_req_bits_tag_0 = io_req_bits_tag; // @[SourceB.scala:33:7] wire [9:0] io_req_bits_set_0 = io_req_bits_set; // @[SourceB.scala:33:7] wire [3:0] io_req_bits_clients_0 = io_req_bits_clients; // @[SourceB.scala:33:7] wire io_b_ready_0 = io_b_ready; // @[SourceB.scala:33:7] wire _b_bits_address_base_T_2 = reset; // @[Parameters.scala:222:12] wire _b_bits_address_base_T_8 = reset; // @[Parameters.scala:222:12] wire _b_bits_address_base_T_14 = reset; // @[Parameters.scala:222:12] wire [2:0] io_b_bits_opcode = 3'h6; // @[SourceB.scala:33:7] wire [2:0] io_b_bits_size = 3'h6; // @[SourceB.scala:33:7] wire [2:0] b_bits_opcode = 3'h6; // @[SourceB.scala:65:17] wire [2:0] b_bits_size = 3'h6; // @[SourceB.scala:65:17] wire [15:0] io_b_bits_mask = 16'hFFFF; // @[SourceB.scala:33:7] wire [15:0] b_bits_mask = 16'hFFFF; // @[SourceB.scala:65:17] wire [15:0] _b_bits_mask_T = 16'hFFFF; // @[SourceB.scala:81:23] wire [127:0] io_b_bits_data = 128'h0; // @[SourceB.scala:33:7] wire [127:0] b_bits_data = 128'h0; // @[SourceB.scala:65:17] wire io_b_bits_corrupt = 1'h0; // @[SourceB.scala:33:7] wire b_bits_corrupt = 1'h0; // @[SourceB.scala:65:17] wire _b_bits_address_base_T = 1'h0; // @[Parameters.scala:222:15] wire _b_bits_address_base_T_4 = 1'h0; // @[Parameters.scala:222:12] wire _b_bits_address_base_T_6 = 1'h0; // @[Parameters.scala:222:15] wire _b_bits_address_base_T_10 = 1'h0; // @[Parameters.scala:222:12] wire _b_bits_address_base_T_12 = 1'h0; // @[Parameters.scala:222:15] wire _b_bits_address_base_T_16 = 1'h0; // @[Parameters.scala:222:12] wire [1:0] b_bits_address_hi_hi_hi_lo = 2'h0; // @[Parameters.scala:230:8] wire [5:0] b_bits_address_base_y_2 = 6'h0; // @[Parameters.scala:221:15] wire [5:0] _b_bits_address_base_T_17 = 6'h0; // @[Parameters.scala:223:6] wire _b_bits_address_base_T_1 = 1'h1; // @[Parameters.scala:222:24] wire _b_bits_address_base_T_7 = 1'h1; // @[Parameters.scala:222:24] wire _b_bits_address_base_T_13 = 1'h1; // @[Parameters.scala:222:24] wire _io_req_ready_T; // @[SourceB.scala:61:21] wire b_ready = io_b_ready_0; // @[SourceB.scala:33:7, :65:17] wire b_valid; // @[SourceB.scala:65:17] wire [1:0] b_bits_param; // @[SourceB.scala:65:17] wire [6:0] b_bits_source; // @[SourceB.scala:65:17] wire [31:0] b_bits_address; // @[SourceB.scala:65:17] wire io_req_ready_0; // @[SourceB.scala:33:7] wire [1:0] io_b_bits_param_0; // @[SourceB.scala:33:7] wire [6:0] io_b_bits_source_0; // @[SourceB.scala:33:7] wire [31:0] io_b_bits_address_0; // @[SourceB.scala:33:7] wire io_b_valid_0; // @[SourceB.scala:33:7] reg [3:0] remain; // @[SourceB.scala:46:25] wire [3:0] remain_set; // @[SourceB.scala:47:30] wire [3:0] remain_clr; // @[SourceB.scala:48:30] wire [3:0] _remain_T = remain | remain_set; // @[SourceB.scala:46:25, :47:30, :49:23] wire [3:0] _remain_T_1 = ~remain_clr; // @[SourceB.scala:48:30, :49:39] wire [3:0] _remain_T_2 = _remain_T & _remain_T_1; // @[SourceB.scala:49:{23,37,39}] wire busy = |remain; // @[SourceB.scala:46:25, :51:23] wire [3:0] todo = busy ? remain : io_req_bits_clients_0; // @[SourceB.scala:33:7, :46:25, :51:23, :52:19] wire [4:0] _next_T = {todo, 1'h0}; // @[package.scala:253:48] wire [3:0] _next_T_1 = _next_T[3:0]; // @[package.scala:253:{48,53}] wire [3:0] _next_T_2 = todo | _next_T_1; // @[package.scala:253:{43,53}] wire [5:0] _next_T_3 = {_next_T_2, 2'h0}; // @[package.scala:253:{43,48}] wire [3:0] _next_T_4 = _next_T_3[3:0]; // @[package.scala:253:{48,53}] wire [3:0] _next_T_5 = _next_T_2 | _next_T_4; // @[package.scala:253:{43,53}] wire [3:0] _next_T_6 = _next_T_5; // @[package.scala:253:43, :254:17] wire [4:0] _next_T_7 = {_next_T_6, 1'h0}; // @[package.scala:254:17] wire [4:0] _next_T_8 = ~_next_T_7; // @[SourceB.scala:53:{16,31}] wire [4:0] next = {1'h0, _next_T_8[3:0] & todo}; // @[SourceB.scala:52:19, :53:{16,37}]

Generate the Verilog code corresponding to the following Chisel files. File Nodes.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.nodes._ import freechips.rocketchip.util.{AsyncQueueParams,RationalDirection} case object TLMonitorBuilder extends Field[TLMonitorArgs => TLMonitorBase](args => new TLMonitor(args)) object TLImp extends NodeImp[TLMasterPortParameters, TLSlavePortParameters, TLEdgeOut, TLEdgeIn, TLBundle] { def edgeO(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeOut(pd, pu, p, sourceInfo) def edgeI(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeIn (pd, pu, p, sourceInfo) def bundleO(eo: TLEdgeOut) = TLBundle(eo.bundle) def bundleI(ei: TLEdgeIn) = TLBundle(ei.bundle) def render(ei: TLEdgeIn) = RenderedEdge(colour = "#000000" /* black */, label = (ei.manager.beatBytes * 8).toString) override def monitor(bundle: TLBundle, edge: TLEdgeIn): Unit = { val monitor = Module(edge.params(TLMonitorBuilder)(TLMonitorArgs(edge))) monitor.io.in := bundle } override def mixO(pd: TLMasterPortParameters, node: OutwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLMasterPortParameters = pd.v1copy(clients = pd.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }) override def mixI(pu: TLSlavePortParameters, node: InwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLSlavePortParameters = pu.v1copy(managers = pu.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }) } trait TLFormatNode extends FormatNode[TLEdgeIn, TLEdgeOut] case class TLClientNode(portParams: Seq[TLMasterPortParameters])(implicit valName: ValName) extends SourceNode(TLImp)(portParams) with TLFormatNode case class TLManagerNode(portParams: Seq[TLSlavePortParameters])(implicit valName: ValName) extends SinkNode(TLImp)(portParams) with TLFormatNode case class TLAdapterNode( clientFn: TLMasterPortParameters => TLMasterPortParameters = { s => s }, managerFn: TLSlavePortParameters => TLSlavePortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLImp)(clientFn, managerFn) with TLFormatNode case class TLJunctionNode( clientFn: Seq[TLMasterPortParameters] => Seq[TLMasterPortParameters], managerFn: Seq[TLSlavePortParameters] => Seq[TLSlavePortParameters])( implicit valName: ValName) extends JunctionNode(TLImp)(clientFn, managerFn) with TLFormatNode case class TLIdentityNode()(implicit valName: ValName) extends IdentityNode(TLImp)() with TLFormatNode object TLNameNode { def apply(name: ValName) = TLIdentityNode()(name) def apply(name: Option[String]): TLIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLIdentityNode = apply(Some(name)) } case class TLEphemeralNode()(implicit valName: ValName) extends EphemeralNode(TLImp)() object TLTempNode { def apply(): TLEphemeralNode = TLEphemeralNode()(ValName("temp")) } case class TLNexusNode( clientFn: Seq[TLMasterPortParameters] => TLMasterPortParameters, managerFn: Seq[TLSlavePortParameters] => TLSlavePortParameters)( implicit valName: ValName) extends NexusNode(TLImp)(clientFn, managerFn) with TLFormatNode abstract class TLCustomNode(implicit valName: ValName) extends CustomNode(TLImp) with TLFormatNode // Asynchronous crossings trait TLAsyncFormatNode extends FormatNode[TLAsyncEdgeParameters, TLAsyncEdgeParameters] object TLAsyncImp extends SimpleNodeImp[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncEdgeParameters, TLAsyncBundle] { def edge(pd: TLAsyncClientPortParameters, pu: TLAsyncManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLAsyncEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLAsyncEdgeParameters) = new TLAsyncBundle(e.bundle) def render(e: TLAsyncEdgeParameters) = RenderedEdge(colour = "#ff0000" /* red */, label = e.manager.async.depth.toString) override def mixO(pd: TLAsyncClientPortParameters, node: OutwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLAsyncManagerPortParameters, node: InwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLAsyncAdapterNode( clientFn: TLAsyncClientPortParameters => TLAsyncClientPortParameters = { s => s }, managerFn: TLAsyncManagerPortParameters => TLAsyncManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLAsyncImp)(clientFn, managerFn) with TLAsyncFormatNode case class TLAsyncIdentityNode()(implicit valName: ValName) extends IdentityNode(TLAsyncImp)() with TLAsyncFormatNode object TLAsyncNameNode { def apply(name: ValName) = TLAsyncIdentityNode()(name) def apply(name: Option[String]): TLAsyncIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLAsyncIdentityNode = apply(Some(name)) } case class TLAsyncSourceNode(sync: Option[Int])(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLAsyncImp)( dFn = { p => TLAsyncClientPortParameters(p) }, uFn = { p => p.base.v1copy(minLatency = p.base.minLatency + sync.getOrElse(p.async.sync)) }) with FormatNode[TLEdgeIn, TLAsyncEdgeParameters] // discard cycles in other clock domain case class TLAsyncSinkNode(async: AsyncQueueParams)(implicit valName: ValName) extends MixedAdapterNode(TLAsyncImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = p.base.minLatency + async.sync) }, uFn = { p => TLAsyncManagerPortParameters(async, p) }) with FormatNode[TLAsyncEdgeParameters, TLEdgeOut] // Rationally related crossings trait TLRationalFormatNode extends FormatNode[TLRationalEdgeParameters, TLRationalEdgeParameters] object TLRationalImp extends SimpleNodeImp[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalEdgeParameters, TLRationalBundle] { def edge(pd: TLRationalClientPortParameters, pu: TLRationalManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLRationalEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLRationalEdgeParameters) = new TLRationalBundle(e.bundle) def render(e: TLRationalEdgeParameters) = RenderedEdge(colour = "#00ff00" /* green */) override def mixO(pd: TLRationalClientPortParameters, node: OutwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLRationalManagerPortParameters, node: InwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLRationalAdapterNode( clientFn: TLRationalClientPortParameters => TLRationalClientPortParameters = { s => s }, managerFn: TLRationalManagerPortParameters => TLRationalManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLRationalImp)(clientFn, managerFn) with TLRationalFormatNode case class TLRationalIdentityNode()(implicit valName: ValName) extends IdentityNode(TLRationalImp)() with TLRationalFormatNode object TLRationalNameNode { def apply(name: ValName) = TLRationalIdentityNode()(name) def apply(name: Option[String]): TLRationalIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLRationalIdentityNode = apply(Some(name)) } case class TLRationalSourceNode()(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLRationalImp)( dFn = { p => TLRationalClientPortParameters(p) }, uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLRationalEdgeParameters] // discard cycles from other clock domain case class TLRationalSinkNode(direction: RationalDirection)(implicit valName: ValName) extends MixedAdapterNode(TLRationalImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = 1) }, uFn = { p => TLRationalManagerPortParameters(direction, p) }) with FormatNode[TLRationalEdgeParameters, TLEdgeOut] // Credited version of TileLink channels trait TLCreditedFormatNode extends FormatNode[TLCreditedEdgeParameters, TLCreditedEdgeParameters] object TLCreditedImp extends SimpleNodeImp[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedEdgeParameters, TLCreditedBundle] { def edge(pd: TLCreditedClientPortParameters, pu: TLCreditedManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLCreditedEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLCreditedEdgeParameters) = new TLCreditedBundle(e.bundle) def render(e: TLCreditedEdgeParameters) = RenderedEdge(colour = "#ffff00" /* yellow */, e.delay.toString) override def mixO(pd: TLCreditedClientPortParameters, node: OutwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLCreditedManagerPortParameters, node: InwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLCreditedAdapterNode( clientFn: TLCreditedClientPortParameters => TLCreditedClientPortParameters = { s => s }, managerFn: TLCreditedManagerPortParameters => TLCreditedManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLCreditedImp)(clientFn, managerFn) with TLCreditedFormatNode case class TLCreditedIdentityNode()(implicit valName: ValName) extends IdentityNode(TLCreditedImp)() with TLCreditedFormatNode object TLCreditedNameNode { def apply(name: ValName) = TLCreditedIdentityNode()(name) def apply(name: Option[String]): TLCreditedIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLCreditedIdentityNode = apply(Some(name)) } case class TLCreditedSourceNode(delay: TLCreditedDelay)(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLCreditedImp)( dFn = { p => TLCreditedClientPortParameters(delay, p) }, uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLCreditedEdgeParameters] // discard cycles from other clock domain case class TLCreditedSinkNode(delay: TLCreditedDelay)(implicit valName: ValName) extends MixedAdapterNode(TLCreditedImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = 1) }, uFn = { p => TLCreditedManagerPortParameters(delay, p) }) with FormatNode[TLCreditedEdgeParameters, TLEdgeOut] File RegisterRouter.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.nodes._ import freechips.rocketchip.diplomacy.{AddressSet, TransferSizes} import freechips.rocketchip.resources.{Device, Resource, ResourceBindings} import freechips.rocketchip.prci.{NoCrossing} import freechips.rocketchip.regmapper.{RegField, RegMapper, RegMapperParams, RegMapperInput, RegisterRouter} import freechips.rocketchip.util.{BundleField, ControlKey, ElaborationArtefacts, GenRegDescsAnno} import scala.math.min class TLRegisterRouterExtraBundle(val sourceBits: Int, val sizeBits: Int) extends Bundle { val source = UInt((sourceBits max 1).W) val size = UInt((sizeBits max 1).W) } case object TLRegisterRouterExtra extends ControlKey[TLRegisterRouterExtraBundle]("tlrr_extra") case class TLRegisterRouterExtraField(sourceBits: Int, sizeBits: Int) extends BundleField[TLRegisterRouterExtraBundle](TLRegisterRouterExtra, Output(new TLRegisterRouterExtraBundle(sourceBits, sizeBits)), x => { x.size := 0.U x.source := 0.U }) /** TLRegisterNode is a specialized TL SinkNode that encapsulates MMIO registers. * It provides functionality for describing and outputting metdata about the registers in several formats. * It also provides a concrete implementation of a regmap function that will be used * to wire a map of internal registers associated with this node to the node's interconnect port. */ case class TLRegisterNode( address: Seq[AddressSet], device: Device, deviceKey: String = "reg/control", concurrency: Int = 0, beatBytes: Int = 4, undefZero: Boolean = true, executable: Boolean = false)( implicit valName: ValName) extends SinkNode(TLImp)(Seq(TLSlavePortParameters.v1( Seq(TLSlaveParameters.v1( address = address, resources = Seq(Resource(device, deviceKey)), executable = executable, supportsGet = TransferSizes(1, beatBytes), supportsPutPartial = TransferSizes(1, beatBytes), supportsPutFull = TransferSizes(1, beatBytes), fifoId = Some(0))), // requests are handled in order beatBytes = beatBytes, minLatency = min(concurrency, 1)))) with TLFormatNode // the Queue adds at most one cycle { val size = 1 << log2Ceil(1 + address.map(_.max).max - address.map(_.base).min) require (size >= beatBytes) address.foreach { case a => require (a.widen(size-1).base == address.head.widen(size-1).base, s"TLRegisterNode addresses (${address}) must be aligned to its size ${size}") } // Calling this method causes the matching TL2 bundle to be // configured to route all requests to the listed RegFields. def regmap(mapping: RegField.Map*) = { val (bundleIn, edge) = this.in(0) val a = bundleIn.a val d = bundleIn.d val fields = TLRegisterRouterExtraField(edge.bundle.sourceBits, edge.bundle.sizeBits) +: a.bits.params.echoFields val params = RegMapperParams(log2Up(size/beatBytes), beatBytes, fields) val in = Wire(Decoupled(new RegMapperInput(params))) in.bits.read := a.bits.opcode === TLMessages.Get in.bits.index := edge.addr_hi(a.bits) in.bits.data := a.bits.data in.bits.mask := a.bits.mask Connectable.waiveUnmatched(in.bits.extra, a.bits.echo) match { case (lhs, rhs) => lhs :<= rhs } val a_extra = in.bits.extra(TLRegisterRouterExtra) a_extra.source := a.bits.source a_extra.size := a.bits.size // Invoke the register map builder val out = RegMapper(beatBytes, concurrency, undefZero, in, mapping:_*) // No flow control needed in.valid := a.valid a.ready := in.ready d.valid := out.valid out.ready := d.ready // We must restore the size to enable width adapters to work val d_extra = out.bits.extra(TLRegisterRouterExtra) d.bits := edge.AccessAck(toSource = d_extra.source, lgSize = d_extra.size) // avoid a Mux on the data bus by manually overriding two fields d.bits.data := out.bits.data Connectable.waiveUnmatched(d.bits.echo, out.bits.extra) match { case (lhs, rhs) => lhs :<= rhs } d.bits.opcode := Mux(out.bits.read, TLMessages.AccessAckData, TLMessages.AccessAck) // Tie off unused channels bundleIn.b.valid := false.B bundleIn.c.ready := true.B bundleIn.e.ready := true.B genRegDescsJson(mapping:_*) } def genRegDescsJson(mapping: RegField.Map*): Unit = { // Dump out the register map for documentation purposes. val base = address.head.base val baseHex = s"0x${base.toInt.toHexString}" val name = s"${device.describe(ResourceBindings()).name}.At${baseHex}" val json = GenRegDescsAnno.serialize(base, name, mapping:_*) var suffix = 0 while( ElaborationArtefacts.contains(s"${baseHex}.${suffix}.regmap.json")) { suffix = suffix + 1 } ElaborationArtefacts.add(s"${baseHex}.${suffix}.regmap.json", json) val module = Module.currentModule.get.asInstanceOf[RawModule] GenRegDescsAnno.anno( module, base, mapping:_*) } } /** Mix HasTLControlRegMap into any subclass of RegisterRouter to gain helper functions for attaching a device control register map to TileLink. * - The intended use case is that controlNode will diplomatically publish a SW-visible device's memory-mapped control registers. * - Use the clock crossing helper controlXing to externally connect controlNode to a TileLink interconnect. * - Use the mapping helper function regmap to internally fill out the space of device control registers. */ trait HasTLControlRegMap { this: RegisterRouter => protected val controlNode = TLRegisterNode( address = address, device = device, deviceKey = "reg/control", concurrency = concurrency, beatBytes = beatBytes, undefZero = undefZero, executable = executable) // Externally, this helper should be used to connect the register control port to a bus val controlXing: TLInwardClockCrossingHelper = this.crossIn(controlNode) // Backwards-compatibility default node accessor with no clock crossing lazy val node: TLInwardNode = controlXing(NoCrossing) // Internally, this function should be used to populate the control port with registers protected def regmap(mapping: RegField.Map*): Unit = { controlNode.regmap(mapping:_*) } } File RegField.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.regmapper import chisel3._ import chisel3.util.{DecoupledIO, ReadyValidIO} import org.json4s.JsonDSL._ import org.json4s.JsonAST.JValue import freechips.rocketchip.util.{SimpleRegIO} case class RegReadFn private(combinational: Boolean, fn: (Bool, Bool) => (Bool, Bool, UInt)) object RegReadFn { // (ivalid: Bool, oready: Bool) => (iready: Bool, ovalid: Bool, data: UInt) // iready may combinationally depend on oready // all other combinational dependencies forbidden (e.g. ovalid <= ivalid) // effects must become visible on the cycle after ovalid && oready // data is only inspected when ovalid && oready implicit def apply(x: (Bool, Bool) => (Bool, Bool, UInt)) = new RegReadFn(false, x) implicit def apply(x: RegisterReadIO[UInt]): RegReadFn = RegReadFn((ivalid, oready) => { x.request.valid := ivalid x.response.ready := oready (x.request.ready, x.response.valid, x.response.bits) }) // (ready: Bool) => (valid: Bool, data: UInt) // valid must not combinationally depend on ready // effects must become visible on the cycle after valid && ready implicit def apply(x: Bool => (Bool, UInt)) = new RegReadFn(true, { case (_, oready) => val (ovalid, data) = x(oready) (true.B, ovalid, data) }) // read from a ReadyValidIO (only safe if there is a consistent source of data) implicit def apply(x: ReadyValidIO[UInt]):RegReadFn = RegReadFn(ready => { x.ready := ready; (x.valid, x.bits) }) // read from a register implicit def apply(x: UInt):RegReadFn = RegReadFn(ready => (true.B, x)) // noop implicit def apply(x: Unit):RegReadFn = RegReadFn(0.U) } case class RegWriteFn private(combinational: Boolean, fn: (Bool, Bool, UInt) => (Bool, Bool)) object RegWriteFn { // (ivalid: Bool, oready: Bool, data: UInt) => (iready: Bool, ovalid: Bool) // iready may combinationally depend on both oready and data // all other combinational dependencies forbidden (e.g. ovalid <= ivalid) // effects must become visible on the cycle after ovalid && oready // data should only be used for an effect when ivalid && iready implicit def apply(x: (Bool, Bool, UInt) => (Bool, Bool)) = new RegWriteFn(false, x) implicit def apply(x: RegisterWriteIO[UInt]): RegWriteFn = RegWriteFn((ivalid, oready, data) => { x.request.valid := ivalid x.request.bits := data x.response.ready := oready (x.request.ready, x.response.valid) }) // (valid: Bool, data: UInt) => (ready: Bool) // ready may combinationally depend on data (but not valid) // effects must become visible on the cycle after valid && ready implicit def apply(x: (Bool, UInt) => Bool) = // combinational => data valid on oready new RegWriteFn(true, { case (_, oready, data) => (true.B, x(oready, data)) }) // write to a DecoupledIO (only safe if there is a consistent sink draining data) // NOTE: this is not an IrrevocableIO (even on TL2) because other fields could cause a lowered valid implicit def apply(x: DecoupledIO[UInt]): RegWriteFn = RegWriteFn((valid, data) => { x.valid := valid; x.bits := data; x.ready }) // updates a register (or adds a mux to a wire) implicit def apply(x: UInt): RegWriteFn = RegWriteFn((valid, data) => { when (valid) { x := data }; true.B }) // noop implicit def apply(x: Unit): RegWriteFn = RegWriteFn((valid, data) => { true.B }) } case class RegField(width: Int, read: RegReadFn, write: RegWriteFn, desc: Option[RegFieldDesc]) { require (width >= 0, s"RegField width must be >= 0, not $width") def pipelined = !read.combinational || !write.combinational def readOnly = this.copy(write = (), desc = this.desc.map(_.copy(access = RegFieldAccessType.R))) def toJson(byteOffset: Int, bitOffset: Int): JValue = { ( ("byteOffset" -> s"0x${byteOffset.toHexString}") ~ ("bitOffset" -> bitOffset) ~ ("bitWidth" -> width) ~ ("name" -> desc.map(_.name)) ~ ("description" -> desc.map{ d=> if (d.desc == "") None else Some(d.desc)}) ~ ("resetValue" -> desc.map{_.reset}) ~ ("group" -> desc.map{_.group}) ~ ("groupDesc" -> desc.map{_.groupDesc}) ~ ("accessType" -> desc.map {d => d.access.toString}) ~ ("writeType" -> desc.map {d => d.wrType.map(_.toString)}) ~ ("readAction" -> desc.map {d => d.rdAction.map(_.toString)}) ~ ("volatile" -> desc.map {d => if (d.volatile) Some(true) else None}) ~ ("enumerations" -> desc.map {d => Option(d.enumerations.map { case (key, (name, edesc)) => (("value" -> key) ~ ("name" -> name) ~ ("description" -> edesc)) }).filter(_.nonEmpty)}) ) } } object RegField { // Byte address => sequence of bitfields, lowest index => lowest address type Map = (Int, Seq[RegField]) def apply(n: Int) : RegField = apply(n, (), (), Some(RegFieldDesc.reserved)) def apply(n: Int, desc: RegFieldDesc) : RegField = apply(n, (), (), Some(desc)) def apply(n: Int, r: RegReadFn, w: RegWriteFn) : RegField = apply(n, r, w, None) def apply(n: Int, r: RegReadFn, w: RegWriteFn, desc: RegFieldDesc) : RegField = apply(n, r, w, Some(desc)) def apply(n: Int, rw: UInt) : RegField = apply(n, rw, rw, None) def apply(n: Int, rw: UInt, desc: RegFieldDesc) : RegField = apply(n, rw, rw, Some(desc)) def r(n: Int, r: RegReadFn) : RegField = apply(n, r, (), None) def r(n: Int, r: RegReadFn, desc: RegFieldDesc) : RegField = apply(n, r, (), Some(desc.copy(access = RegFieldAccessType.R))) def w(n: Int, w: RegWriteFn) : RegField = apply(n, (), w, None) def w(n: Int, w: RegWriteFn, desc: RegFieldDesc) : RegField = apply(n, (), w, Some(desc.copy(access = RegFieldAccessType.W))) // This RegField allows 'set' to set bits in 'reg'. // and to clear bits when the bus writes bits of value 1. // Setting takes priority over clearing. def w1ToClear(n: Int, reg: UInt, set: UInt, desc: Option[RegFieldDesc] = None): RegField = RegField(n, reg, RegWriteFn((valid, data) => { reg := (~((~reg) | Mux(valid, data, 0.U))) | set; true.B }), desc.map{_.copy(access = RegFieldAccessType.RW, wrType=Some(RegFieldWrType.ONE_TO_CLEAR), volatile = true)}) // This RegField wraps an explicit register // (e.g. Black-Boxed Register) to create a R/W register. def rwReg(n: Int, bb: SimpleRegIO, desc: Option[RegFieldDesc] = None) : RegField = RegField(n, bb.q, RegWriteFn((valid, data) => { bb.en := valid bb.d := data true.B }), desc) // Create byte-sized read-write RegFields out of a large UInt register. // It is updated when any of the (implemented) bytes are written, the non-written // bytes are just copied over from their current value. // Because the RegField are all byte-sized, this is also suitable when a register is larger // than the intended bus width of the device (atomic updates are impossible). def bytes(reg: UInt, numBytes: Int, desc: Option[RegFieldDesc]): Seq[RegField] = { require(reg.getWidth * 8 >= numBytes, "Can't break a ${reg.getWidth}-bit-wide register into only ${numBytes} bytes.") val numFullBytes = reg.getWidth/8 val numPartialBytes = if ((reg.getWidth % 8) > 0) 1 else 0 val numPadBytes = numBytes - numFullBytes - numPartialBytes val pad = reg | 0.U((8*numBytes).W) val oldBytes = VecInit.tabulate(numBytes) { i => pad(8*(i+1)-1, 8*i) } val newBytes = WireDefault(oldBytes) val valids = WireDefault(VecInit.fill(numBytes) { false.B }) when (valids.reduce(_ || _)) { reg := newBytes.asUInt } def wrFn(i: Int): RegWriteFn = RegWriteFn((valid, data) => { valids(i) := valid when (valid) {newBytes(i) := data} true.B }) val fullBytes = Seq.tabulate(numFullBytes) { i => val newDesc = desc.map {d => d.copy(name = d.name + s"_$i")} RegField(8, oldBytes(i), wrFn(i), newDesc)} val partialBytes = if (numPartialBytes > 0) { val newDesc = desc.map {d => d.copy(name = d.name + s"_$numFullBytes")} Seq(RegField(reg.getWidth % 8, oldBytes(numFullBytes), wrFn(numFullBytes), newDesc), RegField(8 - (reg.getWidth % 8))) } else Nil val padBytes = Seq.fill(numPadBytes){RegField(8)} fullBytes ++ partialBytes ++ padBytes } def bytes(reg: UInt, desc: Option[RegFieldDesc]): Seq[RegField] = { val width = reg.getWidth require (width % 8 == 0, s"RegField.bytes must be called on byte-sized reg, not ${width} bits") bytes(reg, width/8, desc) } def bytes(reg: UInt, numBytes: Int): Seq[RegField] = bytes(reg, numBytes, None) def bytes(reg: UInt): Seq[RegField] = bytes(reg, None) } trait HasRegMap { def regmap(mapping: RegField.Map*): Unit val interrupts: Vec[Bool] } // See Example.scala for an example of how to use regmap File MuxLiteral.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util.log2Ceil import scala.reflect.ClassTag /* MuxLiteral creates a lookup table from a key to a list of values. * Unlike MuxLookup, the table keys must be exclusive literals. */ object MuxLiteral { def apply[T <: Data:ClassTag](index: UInt, default: T, first: (UInt, T), rest: (UInt, T)*): T = apply(index, default, first :: rest.toList) def apply[T <: Data:ClassTag](index: UInt, default: T, cases: Seq[(UInt, T)]): T = MuxTable(index, default, cases.map { case (k, v) => (k.litValue, v) }) } object MuxSeq { def apply[T <: Data:ClassTag](index: UInt, default: T, first: T, rest: T*): T = apply(index, default, first :: rest.toList) def apply[T <: Data:ClassTag](index: UInt, default: T, cases: Seq[T]): T = MuxTable(index, default, cases.zipWithIndex.map { case (v, i) => (BigInt(i), v) }) } object MuxTable { def apply[T <: Data:ClassTag](index: UInt, default: T, first: (BigInt, T), rest: (BigInt, T)*): T = apply(index, default, first :: rest.toList) def apply[T <: Data:ClassTag](index: UInt, default: T, cases: Seq[(BigInt, T)]): T = { /* All keys must be >= 0 and distinct */ cases.foreach { case (k, _) => require (k >= 0) } require (cases.map(_._1).distinct.size == cases.size) /* Filter out any cases identical to the default */ val simple = cases.filter { case (k, v) => !default.isLit || !v.isLit || v.litValue != default.litValue } val maxKey = (BigInt(0) +: simple.map(_._1)).max val endIndex = BigInt(1) << log2Ceil(maxKey+1) if (simple.isEmpty) { default } else if (endIndex <= 2*simple.size) { /* The dense encoding case uses a Vec */ val table = Array.fill(endIndex.toInt) { default } simple.foreach { case (k, v) => table(k.toInt) = v } Mux(index >= endIndex.U, default, VecInit(table)(index)) } else { /* The sparse encoding case uses switch */ val out = WireDefault(default) simple.foldLeft(new chisel3.util.SwitchContext(index, None, Set.empty)) { case (acc, (k, v)) => acc.is (k.U) { out := v } } out } } } File LazyModuleImp.scala: package org.chipsalliance.diplomacy.lazymodule import chisel3.{withClockAndReset, Module, RawModule, Reset, _} import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo} import firrtl.passes.InlineAnnotation import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.nodes.Dangle import scala.collection.immutable.SortedMap /** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]]. * * This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy. */ sealed trait LazyModuleImpLike extends RawModule { /** [[LazyModule]] that contains this instance. */ val wrapper: LazyModule /** IOs that will be automatically "punched" for this instance. */ val auto: AutoBundle /** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */ protected[diplomacy] val dangles: Seq[Dangle] // [[wrapper.module]] had better not be accessed while LazyModules are still being built! require( LazyModule.scope.isEmpty, s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}" ) /** Set module name. Defaults to the containing LazyModule's desiredName. */ override def desiredName: String = wrapper.desiredName suggestName(wrapper.suggestedName) /** [[Parameters]] for chisel [[Module]]s. */ implicit val p: Parameters = wrapper.p /** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and * submodules. */ protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = { // 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]], // 2. return [[Dangle]]s from each module. val childDangles = wrapper.children.reverse.flatMap { c => implicit val sourceInfo: SourceInfo = c.info c.cloneProto.map { cp => // If the child is a clone, then recursively set cloneProto of its children as well def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = { require(bases.size == clones.size) (bases.zip(clones)).map { case (l, r) => require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}") l.cloneProto = Some(r) assignCloneProtos(l.children, r.children) } } assignCloneProtos(c.children, cp.children) // Clone the child module as a record, and get its [[AutoBundle]] val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName) val clonedAuto = clone("auto").asInstanceOf[AutoBundle] // Get the empty [[Dangle]]'s of the cloned child val rawDangles = c.cloneDangles() require(rawDangles.size == clonedAuto.elements.size) // Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) } dangles }.getOrElse { // For non-clones, instantiate the child module val mod = try { Module(c.module) } catch { case e: ChiselException => { println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}") throw e } } mod.dangles } } // Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]]. // This will result in a sequence of [[Dangle]] from these [[BaseNode]]s. val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate()) // Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]] val allDangles = nodeDangles ++ childDangles // Group [[allDangles]] by their [[source]]. val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*) // For each [[source]] set of [[Dangle]]s of size 2, ensure that these // can be connected as a source-sink pair (have opposite flipped value). // Make the connection and mark them as [[done]]. val done = Set() ++ pairing.values.filter(_.size == 2).map { case Seq(a, b) => require(a.flipped != b.flipped) // @todo <> in chisel3 makes directionless connection. if (a.flipped) { a.data <> b.data } else { b.data <> a.data } a.source case _ => None } // Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module. val forward = allDangles.filter(d => !done(d.source)) // Generate [[AutoBundle]] IO from [[forward]]. val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*)) // Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]] val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) => if (d.flipped) { d.data <> io } else { io <> d.data } d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name) } // Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]]. wrapper.inModuleBody.reverse.foreach { _() } if (wrapper.shouldBeInlined) { chisel3.experimental.annotate(new ChiselAnnotation { def toFirrtl = InlineAnnotation(toNamed) }) } // Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]]. (auto, dangles) } } /** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike { /** Instantiate hardware of this `Module`. */ val (auto, dangles) = instantiate() } /** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike { // These wires are the default clock+reset for all LazyModule children. // It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the // [[LazyRawModuleImp]] children. // Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly. /** drive clock explicitly. */ val childClock: Clock = Wire(Clock()) /** drive reset explicitly. */ val childReset: Reset = Wire(Reset()) // the default is that these are disabled childClock := false.B.asClock childReset := chisel3.DontCare def provideImplicitClockToLazyChildren: Boolean = false val (auto, dangles) = if (provideImplicitClockToLazyChildren) { withClockAndReset(childClock, childReset) { instantiate() } } else { instantiate() } } File MixedNode.scala: package org.chipsalliance.diplomacy.nodes import chisel3.{Data, DontCare, Wire} import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.{Field, Parameters} import org.chipsalliance.diplomacy.ValName import org.chipsalliance.diplomacy.sourceLine /** One side metadata of a [[Dangle]]. * * Describes one side of an edge going into or out of a [[BaseNode]]. * * @param serial * the global [[BaseNode.serial]] number of the [[BaseNode]] that this [[HalfEdge]] connects to. * @param index * the `index` in the [[BaseNode]]'s input or output port list that this [[HalfEdge]] belongs to. */ case class HalfEdge(serial: Int, index: Int) extends Ordered[HalfEdge] { import scala.math.Ordered.orderingToOrdered def compare(that: HalfEdge): Int = HalfEdge.unapply(this).compare(HalfEdge.unapply(that)) } /** [[Dangle]] captures the `IO` information of a [[LazyModule]] and which two [[BaseNode]]s the [[Edges]]/[[Bundle]] * connects. * * [[Dangle]]s are generated by [[BaseNode.instantiate]] using [[MixedNode.danglesOut]] and [[MixedNode.danglesIn]] , * [[LazyModuleImp.instantiate]] connects those that go to internal or explicit IO connections in a [[LazyModule]]. * * @param source * the source [[HalfEdge]] of this [[Dangle]], which captures the source [[BaseNode]] and the port `index` within * that [[BaseNode]]. * @param sink * sink [[HalfEdge]] of this [[Dangle]], which captures the sink [[BaseNode]] and the port `index` within that * [[BaseNode]]. * @param flipped * flip or not in [[AutoBundle.makeElements]]. If true this corresponds to `danglesOut`, if false it corresponds to * `danglesIn`. * @param dataOpt * actual [[Data]] for the hardware connection. Can be empty if this belongs to a cloned module */ case class Dangle(source: HalfEdge, sink: HalfEdge, flipped: Boolean, name: String, dataOpt: Option[Data]) { def data = dataOpt.get } /** [[Edges]] is a collection of parameters describing the functionality and connection for an interface, which is often * derived from the interconnection protocol and can inform the parameterization of the hardware bundles that actually * implement the protocol. */ case class Edges[EI, EO](in: Seq[EI], out: Seq[EO]) /** A field available in [[Parameters]] used to determine whether [[InwardNodeImp.monitor]] will be called. */ case object MonitorsEnabled extends Field[Boolean](true) /** When rendering the edge in a graphical format, flip the order in which the edges' source and sink are presented. * * For example, when rendering graphML, yEd by default tries to put the source node vertically above the sink node, but * [[RenderFlipped]] inverts this relationship. When a particular [[LazyModule]] contains both source nodes and sink * nodes, flipping the rendering of one node's edge will usual produce a more concise visual layout for the * [[LazyModule]]. */ case object RenderFlipped extends Field[Boolean](false) /** The sealed node class in the package, all node are derived from it. * * @param inner * Sink interface implementation. * @param outer * Source interface implementation. * @param valName * val name of this node. * @tparam DI * Downward-flowing parameters received on the inner side of the node. It is usually a brunch of parameters * describing the protocol parameters from a source. For an [[InwardNode]], it is determined by the connected * [[OutwardNode]]. Since it can be connected to multiple sources, this parameter is always a Seq of source port * parameters. * @tparam UI * Upward-flowing parameters generated by the inner side of the node. It is usually a brunch of parameters describing * the protocol parameters of a sink. For an [[InwardNode]], it is determined itself. * @tparam EI * Edge Parameters describing a connection on the inner side of the node. It is usually a brunch of transfers * specified for a sink according to protocol. * @tparam BI * Bundle type used when connecting to the inner side of the node. It is a hardware interface of this sink interface. * It should extends from [[chisel3.Data]], which represents the real hardware. * @tparam DO * Downward-flowing parameters generated on the outer side of the node. It is usually a brunch of parameters * describing the protocol parameters of a source. For an [[OutwardNode]], it is determined itself. * @tparam UO * Upward-flowing parameters received by the outer side of the node. It is usually a brunch of parameters describing * the protocol parameters from a sink. For an [[OutwardNode]], it is determined by the connected [[InwardNode]]. * Since it can be connected to multiple sinks, this parameter is always a Seq of sink port parameters. * @tparam EO * Edge Parameters describing a connection on the outer side of the node. It is usually a brunch of transfers * specified for a source according to protocol. * @tparam BO * Bundle type used when connecting to the outer side of the node. It is a hardware interface of this source * interface. It should extends from [[chisel3.Data]], which represents the real hardware. * * @note * Call Graph of [[MixedNode]] * - line `─`: source is process by a function and generate pass to others * - Arrow `→`: target of arrow is generated by source * * {{{ * (from the other node) * ┌─────────────────────────────────────────────────────────[[InwardNode.uiParams]]─────────────┐ * ↓ │ * (binding node when elaboration) [[OutwardNode.uoParams]]────────────────────────[[MixedNode.mapParamsU]]→──────────┐ │ * [[InwardNode.accPI]] │ │ │ * │ │ (based on protocol) │ * │ │ [[MixedNode.inner.edgeI]] │ * │ │ ↓ │ * ↓ │ │ │ * (immobilize after elaboration) (inward port from [[OutwardNode]]) │ ↓ │ * [[InwardNode.iBindings]]──┐ [[MixedNode.iDirectPorts]]────────────────────→[[MixedNode.iPorts]] [[InwardNode.uiParams]] │ * │ │ ↑ │ │ │ * │ │ │ [[OutwardNode.doParams]] │ │ * │ │ │ (from the other node) │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * │ │ │ └────────┬──────────────┤ │ * │ │ │ │ │ │ * │ │ │ │ (based on protocol) │ * │ │ │ │ [[MixedNode.inner.edgeI]] │ * │ │ │ │ │ │ * │ │ (from the other node) │ ↓ │ * │ └───[[OutwardNode.oPortMapping]] [[OutwardNode.oStar]] │ [[MixedNode.edgesIn]]───┐ │ * │ ↑ ↑ │ │ ↓ │ * │ │ │ │ │ [[MixedNode.in]] │ * │ │ │ │ ↓ ↑ │ * │ (solve star connection) │ │ │ [[MixedNode.bundleIn]]──┘ │ * ├───[[MixedNode.resolveStar]]→─┼─────────────────────────────┤ └────────────────────────────────────┐ │ * │ │ │ [[MixedNode.bundleOut]]─┐ │ │ * │ │ │ ↑ ↓ │ │ * │ │ │ │ [[MixedNode.out]] │ │ * │ ↓ ↓ │ ↑ │ │ * │ ┌─────[[InwardNode.iPortMapping]] [[InwardNode.iStar]] [[MixedNode.edgesOut]]──┘ │ │ * │ │ (from the other node) ↑ │ │ * │ │ │ │ │ │ * │ │ │ [[MixedNode.outer.edgeO]] │ │ * │ │ │ (based on protocol) │ │ * │ │ │ │ │ │ * │ │ │ ┌────────────────────────────────────────┤ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * (immobilize after elaboration)│ ↓ │ │ │ │ * [[OutwardNode.oBindings]]─┘ [[MixedNode.oDirectPorts]]───→[[MixedNode.oPorts]] [[OutwardNode.doParams]] │ │ * ↑ (inward port from [[OutwardNode]]) │ │ │ │ * │ ┌─────────────────────────────────────────┤ │ │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * [[OutwardNode.accPO]] │ ↓ │ │ │ * (binding node when elaboration) │ [[InwardNode.diParams]]─────→[[MixedNode.mapParamsD]]────────────────────────────┘ │ │ * │ ↑ │ │ * │ └──────────────────────────────────────────────────────────────────────────────────────────┘ │ * └──────────────────────────────────────────────────────────────────────────────────────────────────────────┘ * }}} */ abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data]( val inner: InwardNodeImp[DI, UI, EI, BI], val outer: OutwardNodeImp[DO, UO, EO, BO] )( implicit valName: ValName) extends BaseNode with NodeHandle[DI, UI, EI, BI, DO, UO, EO, BO] with InwardNode[DI, UI, BI] with OutwardNode[DO, UO, BO] { // Generate a [[NodeHandle]] with inward and outward node are both this node. val inward = this val outward = this /** Debug info of nodes binding. */ def bindingInfo: String = s"""$iBindingInfo |$oBindingInfo |""".stripMargin /** Debug info of ports connecting. */ def connectedPortsInfo: String = s"""${oPorts.size} outward ports connected: [${oPorts.map(_._2.name).mkString(",")}] |${iPorts.size} inward ports connected: [${iPorts.map(_._2.name).mkString(",")}] |""".stripMargin /** Debug info of parameters propagations. */ def parametersInfo: String = s"""${doParams.size} downstream outward parameters: [${doParams.mkString(",")}] |${uoParams.size} upstream outward parameters: [${uoParams.mkString(",")}] |${diParams.size} downstream inward parameters: [${diParams.mkString(",")}] |${uiParams.size} upstream inward parameters: [${uiParams.mkString(",")}] |""".stripMargin /** For a given node, converts [[OutwardNode.accPO]] and [[InwardNode.accPI]] to [[MixedNode.oPortMapping]] and * [[MixedNode.iPortMapping]]. * * Given counts of known inward and outward binding and inward and outward star bindings, return the resolved inward * stars and outward stars. * * This method will also validate the arguments and throw a runtime error if the values are unsuitable for this type * of node. * * @param iKnown * Number of known-size ([[BIND_ONCE]]) input bindings. * @param oKnown * Number of known-size ([[BIND_ONCE]]) output bindings. * @param iStar * Number of unknown size ([[BIND_STAR]]) input bindings. * @param oStar * Number of unknown size ([[BIND_STAR]]) output bindings. * @return * A Tuple of the resolved number of input and output connections. */ protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStar: Int, oStar: Int): (Int, Int) /** Function to generate downward-flowing outward params from the downward-flowing input params and the current output * ports. * * @param n * The size of the output sequence to generate. * @param p * Sequence of downward-flowing input parameters of this node. * @return * A `n`-sized sequence of downward-flowing output edge parameters. */ protected[diplomacy] def mapParamsD(n: Int, p: Seq[DI]): Seq[DO] /** Function to generate upward-flowing input parameters from the upward-flowing output parameters [[uiParams]]. * * @param n * Size of the output sequence. * @param p * Upward-flowing output edge parameters. * @return * A n-sized sequence of upward-flowing input edge parameters. */ protected[diplomacy] def mapParamsU(n: Int, p: Seq[UO]): Seq[UI] /** @return * The sink cardinality of the node, the number of outputs bound with [[BIND_QUERY]] summed with inputs bound with * [[BIND_STAR]]. */ protected[diplomacy] lazy val sinkCard: Int = oBindings.count(_._3 == BIND_QUERY) + iBindings.count(_._3 == BIND_STAR) /** @return * The source cardinality of this node, the number of inputs bound with [[BIND_QUERY]] summed with the number of * output bindings bound with [[BIND_STAR]]. */ protected[diplomacy] lazy val sourceCard: Int = iBindings.count(_._3 == BIND_QUERY) + oBindings.count(_._3 == BIND_STAR) /** @return list of nodes involved in flex bindings with this node. */ protected[diplomacy] lazy val flexes: Seq[BaseNode] = oBindings.filter(_._3 == BIND_FLEX).map(_._2) ++ iBindings.filter(_._3 == BIND_FLEX).map(_._2) /** Resolves the flex to be either source or sink and returns the offset where the [[BIND_STAR]] operators begin * greedily taking up the remaining connections. * * @return * A value >= 0 if it is sink cardinality, a negative value for source cardinality. The magnitude of the return * value is not relevant. */ protected[diplomacy] lazy val flexOffset: Int = { /** Recursively performs a depth-first search of the [[flexes]], [[BaseNode]]s connected to this node with flex * operators. The algorithm bottoms out when we either get to a node we have already visited or when we get to a * connection that is not a flex and can set the direction for us. Otherwise, recurse by visiting the `flexes` of * each node in the current set and decide whether they should be added to the set or not. * * @return * the mapping of [[BaseNode]] indexed by their serial numbers. */ def DFS(v: BaseNode, visited: Map[Int, BaseNode]): Map[Int, BaseNode] = { if (visited.contains(v.serial) || !v.flexibleArityDirection) { visited } else { v.flexes.foldLeft(visited + (v.serial -> v))((sum, n) => DFS(n, sum)) } } /** Determine which [[BaseNode]] are involved in resolving the flex connections to/from this node. * * @example * {{{ * a :*=* b :*=* c * d :*=* b * e :*=* f * }}} * * `flexSet` for `a`, `b`, `c`, or `d` will be `Set(a, b, c, d)` `flexSet` for `e` or `f` will be `Set(e,f)` */ val flexSet = DFS(this, Map()).values /** The total number of :*= operators where we're on the left. */ val allSink = flexSet.map(_.sinkCard).sum /** The total number of :=* operators used when we're on the right. */ val allSource = flexSet.map(_.sourceCard).sum require( allSink == 0 || allSource == 0, s"The nodes ${flexSet.map(_.name)} which are inter-connected by :*=* have ${allSink} :*= operators and ${allSource} :=* operators connected to them, making it impossible to determine cardinality inference direction." ) allSink - allSource } /** @return A value >= 0 if it is sink cardinality, a negative value for source cardinality. */ protected[diplomacy] def edgeArityDirection(n: BaseNode): Int = { if (flexibleArityDirection) flexOffset else if (n.flexibleArityDirection) n.flexOffset else 0 } /** For a node which is connected between two nodes, select the one that will influence the direction of the flex * resolution. */ protected[diplomacy] def edgeAritySelect(n: BaseNode, l: => Int, r: => Int): Int = { val dir = edgeArityDirection(n) if (dir < 0) l else if (dir > 0) r else 1 } /** Ensure that the same node is not visited twice in resolving `:*=`, etc operators. */ private var starCycleGuard = false /** Resolve all the star operators into concrete indicies. As connections are being made, some may be "star" * connections which need to be resolved. In some way to determine how many actual edges they correspond to. We also * need to build up the ranges of edges which correspond to each binding operator, so that We can apply the correct * edge parameters and later build up correct bundle connections. * * [[oPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that oPort (binding * operator). [[iPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that iPort * (binding operator). [[oStar]]: `Int` the value to return for this node `N` for any `N :*= foo` or `N :*=* foo :*= * bar` [[iStar]]: `Int` the value to return for this node `N` for any `foo :=* N` or `bar :=* foo :*=* N` */ protected[diplomacy] lazy val ( oPortMapping: Seq[(Int, Int)], iPortMapping: Seq[(Int, Int)], oStar: Int, iStar: Int ) = { try { if (starCycleGuard) throw StarCycleException() starCycleGuard = true // For a given node N... // Number of foo :=* N // + Number of bar :=* foo :*=* N val oStars = oBindings.count { case (_, n, b, _, _) => b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) < 0) } // Number of N :*= foo // + Number of N :*=* foo :*= bar val iStars = iBindings.count { case (_, n, b, _, _) => b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) > 0) } // 1 for foo := N // + bar.iStar for bar :*= foo :*=* N // + foo.iStar for foo :*= N // + 0 for foo :=* N val oKnown = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, 0, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => 0 } }.sum // 1 for N := foo // + bar.oStar for N :*=* foo :=* bar // + foo.oStar for N :=* foo // + 0 for N :*= foo val iKnown = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, 0) case BIND_QUERY => n.oStar case BIND_STAR => 0 } }.sum // Resolve star depends on the node subclass to implement the algorithm for this. val (iStar, oStar) = resolveStar(iKnown, oKnown, iStars, oStars) // Cumulative list of resolved outward binding range starting points val oSum = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, oStar, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => oStar } }.scanLeft(0)(_ + _) // Cumulative list of resolved inward binding range starting points val iSum = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, iStar) case BIND_QUERY => n.oStar case BIND_STAR => iStar } }.scanLeft(0)(_ + _) // Create ranges for each binding based on the running sums and return // those along with resolved values for the star operations. (oSum.init.zip(oSum.tail), iSum.init.zip(iSum.tail), oStar, iStar) } catch { case c: StarCycleException => throw c.copy(loop = context +: c.loop) } } /** Sequence of inward ports. * * This should be called after all star bindings are resolved. * * Each element is: `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. * `n` Instance of inward node. `p` View of [[Parameters]] where this connection was made. `s` Source info where this * connection was made in the source code. */ protected[diplomacy] lazy val oDirectPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oBindings.flatMap { case (i, n, _, p, s) => // for each binding operator in this node, look at what it connects to val (start, end) = n.iPortMapping(i) (start until end).map { j => (j, n, p, s) } } /** Sequence of outward ports. * * This should be called after all star bindings are resolved. * * `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. `n` Instance of * outward node. `p` View of [[Parameters]] where this connection was made. `s` [[SourceInfo]] where this connection * was made in the source code. */ protected[diplomacy] lazy val iDirectPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iBindings.flatMap { case (i, n, _, p, s) => // query this port index range of this node in the other side of node. val (start, end) = n.oPortMapping(i) (start until end).map { j => (j, n, p, s) } } // Ephemeral nodes ( which have non-None iForward/oForward) have in_degree = out_degree // Thus, there must exist an Eulerian path and the below algorithms terminate @scala.annotation.tailrec private def oTrace( tuple: (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) ): (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.iForward(i) match { case None => (i, n, p, s) case Some((j, m)) => oTrace((j, m, p, s)) } } @scala.annotation.tailrec private def iTrace( tuple: (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) ): (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.oForward(i) match { case None => (i, n, p, s) case Some((j, m)) => iTrace((j, m, p, s)) } } /** Final output ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - Numeric index of this binding in the [[InwardNode]] on the other end. * - [[InwardNode]] on the other end of this binding. * - A view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. */ lazy val oPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oDirectPorts.map(oTrace) /** Final input ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - numeric index of this binding in [[OutwardNode]] on the other end. * - [[OutwardNode]] on the other end of this binding. * - a view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. */ lazy val iPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iDirectPorts.map(iTrace) private var oParamsCycleGuard = false protected[diplomacy] lazy val diParams: Seq[DI] = iPorts.map { case (i, n, _, _) => n.doParams(i) } protected[diplomacy] lazy val doParams: Seq[DO] = { try { if (oParamsCycleGuard) throw DownwardCycleException() oParamsCycleGuard = true val o = mapParamsD(oPorts.size, diParams) require( o.size == oPorts.size, s"""Diplomacy has detected a problem with your graph: |At the following node, the number of outward ports should equal the number of produced outward parameters. |$context |$connectedPortsInfo |Downstreamed inward parameters: [${diParams.mkString(",")}] |Produced outward parameters: [${o.mkString(",")}] |""".stripMargin ) o.map(outer.mixO(_, this)) } catch { case c: DownwardCycleException => throw c.copy(loop = context +: c.loop) } } private var iParamsCycleGuard = false protected[diplomacy] lazy val uoParams: Seq[UO] = oPorts.map { case (o, n, _, _) => n.uiParams(o) } protected[diplomacy] lazy val uiParams: Seq[UI] = { try { if (iParamsCycleGuard) throw UpwardCycleException() iParamsCycleGuard = true val i = mapParamsU(iPorts.size, uoParams) require( i.size == iPorts.size, s"""Diplomacy has detected a problem with your graph: |At the following node, the number of inward ports should equal the number of produced inward parameters. |$context |$connectedPortsInfo |Upstreamed outward parameters: [${uoParams.mkString(",")}] |Produced inward parameters: [${i.mkString(",")}] |""".stripMargin ) i.map(inner.mixI(_, this)) } catch { case c: UpwardCycleException => throw c.copy(loop = context +: c.loop) } } /** Outward edge parameters. */ protected[diplomacy] lazy val edgesOut: Seq[EO] = (oPorts.zip(doParams)).map { case ((i, n, p, s), o) => outer.edgeO(o, n.uiParams(i), p, s) } /** Inward edge parameters. */ protected[diplomacy] lazy val edgesIn: Seq[EI] = (iPorts.zip(uiParams)).map { case ((o, n, p, s), i) => inner.edgeI(n.doParams(o), i, p, s) } /** A tuple of the input edge parameters and output edge parameters for the edges bound to this node. * * If you need to access to the edges of a foreign Node, use this method (in/out create bundles). */ lazy val edges: Edges[EI, EO] = Edges(edgesIn, edgesOut) /** Create actual Wires corresponding to the Bundles parameterized by the outward edges of this node. */ protected[diplomacy] lazy val bundleOut: Seq[BO] = edgesOut.map { e => val x = Wire(outer.bundleO(e)).suggestName(s"${valName.value}Out") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } /** Create actual Wires corresponding to the Bundles parameterized by the inward edges of this node. */ protected[diplomacy] lazy val bundleIn: Seq[BI] = edgesIn.map { e => val x = Wire(inner.bundleI(e)).suggestName(s"${valName.value}In") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } private def emptyDanglesOut: Seq[Dangle] = oPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(serial, i), sink = HalfEdge(n.serial, j), flipped = false, name = wirePrefix + "out", dataOpt = None ) } private def emptyDanglesIn: Seq[Dangle] = iPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(n.serial, j), sink = HalfEdge(serial, i), flipped = true, name = wirePrefix + "in", dataOpt = None ) } /** Create the [[Dangle]]s which describe the connections from this node output to other nodes inputs. */ protected[diplomacy] def danglesOut: Seq[Dangle] = emptyDanglesOut.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleOut(i))) } /** Create the [[Dangle]]s which describe the connections from this node input from other nodes outputs. */ protected[diplomacy] def danglesIn: Seq[Dangle] = emptyDanglesIn.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleIn(i))) } private[diplomacy] var instantiated = false /** Gather Bundle and edge parameters of outward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. */ def out: Seq[(BO, EO)] = { require( instantiated, s"$name.out should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleOut.zip(edgesOut) } /** Gather Bundle and edge parameters of inward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. */ def in: Seq[(BI, EI)] = { require( instantiated, s"$name.in should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleIn.zip(edgesIn) } /** Actually instantiate this node during [[LazyModuleImp]] evaluation. Mark that it's safe to use the Bundle wires, * instantiate monitors on all input ports if appropriate, and return all the dangles of this node. */ protected[diplomacy] def instantiate(): Seq[Dangle] = { instantiated = true if (!circuitIdentity) { (iPorts.zip(in)).foreach { case ((_, _, p, _), (b, e)) => if (p(MonitorsEnabled)) inner.monitor(b, e) } } danglesOut ++ danglesIn } protected[diplomacy] def cloneDangles(): Seq[Dangle] = emptyDanglesOut ++ emptyDanglesIn /** Connects the outward part of a node with the inward part of this node. */ protected[diplomacy] def bind( h: OutwardNode[DI, UI, BI], binding: NodeBinding )( implicit p: Parameters, sourceInfo: SourceInfo ): Unit = { val x = this // x := y val y = h sourceLine(sourceInfo, " at ", "") val i = x.iPushed val o = y.oPushed y.oPush( i, x, binding match { case BIND_ONCE => BIND_ONCE case BIND_FLEX => BIND_FLEX case BIND_STAR => BIND_QUERY case BIND_QUERY => BIND_STAR } ) x.iPush(o, y, binding) } /* Metadata for printing the node graph. */ def inputs: Seq[(OutwardNode[DI, UI, BI], RenderedEdge)] = (iPorts.zip(edgesIn)).map { case ((_, n, p, _), e) => val re = inner.render(e) (n, re.copy(flipped = re.flipped != p(RenderFlipped))) } /** Metadata for printing the node graph */ def outputs: Seq[(InwardNode[DO, UO, BO], RenderedEdge)] = oPorts.map { case (i, n, _, _) => (n, n.inputs(i)._2) } } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) || !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.ProbeAckData || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode | small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U || beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } } File CLINT.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.devices.tilelink import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.diplomacy.{AddressSet} import freechips.rocketchip.resources.{Resource, SimpleDevice} import freechips.rocketchip.interrupts.{IntNexusNode, IntSinkParameters, IntSinkPortParameters, IntSourceParameters, IntSourcePortParameters} import freechips.rocketchip.regmapper.{RegField, RegFieldDesc, RegFieldGroup} import freechips.rocketchip.subsystem.{BaseSubsystem, CBUS, TLBusWrapperLocation} import freechips.rocketchip.tilelink.{TLFragmenter, TLRegisterNode} import freechips.rocketchip.util.Annotated object CLINTConsts { def msipOffset(hart: Int) = hart * msipBytes def timecmpOffset(hart: Int) = 0x4000 + hart * timecmpBytes def timeOffset = 0xbff8 def msipBytes = 4 def timecmpBytes = 8 def size = 0x10000 def timeWidth = 64 def ipiWidth = 32 def ints = 2 } case class CLINTParams(baseAddress: BigInt = 0x02000000, intStages: Int = 0) { def address = AddressSet(baseAddress, CLINTConsts.size-1) } case object CLINTKey extends Field[Option[CLINTParams]](None) case class CLINTAttachParams( slaveWhere: TLBusWrapperLocation = CBUS ) case object CLINTAttachKey extends Field(CLINTAttachParams()) class CLINT(params: CLINTParams, beatBytes: Int)(implicit p: Parameters) extends LazyModule { import CLINTConsts._ // clint0 => at most 4095 devices val device = new SimpleDevice("clint", Seq("riscv,clint0")) { override val alwaysExtended = true } val node: TLRegisterNode = TLRegisterNode( address = Seq(params.address), device = device, beatBytes = beatBytes) val intnode : IntNexusNode = IntNexusNode( sourceFn = { _ => IntSourcePortParameters(Seq(IntSourceParameters(ints, Seq(Resource(device, "int"))))) }, sinkFn = { _ => IntSinkPortParameters(Seq(IntSinkParameters())) }, outputRequiresInput = false) lazy val module = new Impl class Impl extends LazyModuleImp(this) { Annotated.params(this, params) require (intnode.edges.in.size == 0, "CLINT only produces interrupts; it does not accept them") val io = IO(new Bundle { val rtcTick = Input(Bool()) }) val time = RegInit(0.U(timeWidth.W)) when (io.rtcTick) { time := time + 1.U } val nTiles = intnode.out.size val timecmp = Seq.fill(nTiles) { Reg(UInt(timeWidth.W)) } val ipi = Seq.fill(nTiles) { RegInit(0.U(1.W)) } val (intnode_out, _) = intnode.out.unzip intnode_out.zipWithIndex.foreach { case (int, i) => int(0) := ShiftRegister(ipi(i)(0), params.intStages) // msip int(1) := ShiftRegister(time.asUInt >= timecmp(i).asUInt, params.intStages) // mtip } /* 0000 msip hart 0 * 0004 msip hart 1 * 4000 mtimecmp hart 0 lo * 4004 mtimecmp hart 0 hi * 4008 mtimecmp hart 1 lo * 400c mtimecmp hart 1 hi * bff8 mtime lo * bffc mtime hi */ node.regmap( 0 -> RegFieldGroup ("msip", Some("MSIP Bits"), ipi.zipWithIndex.flatMap{ case (r, i) => RegField(1, r, RegFieldDesc(s"msip_$i", s"MSIP bit for Hart $i", reset=Some(0))) :: RegField(ipiWidth - 1) :: Nil }), timecmpOffset(0) -> timecmp.zipWithIndex.flatMap{ case (t, i) => RegFieldGroup(s"mtimecmp_$i", Some(s"MTIMECMP for hart $i"), RegField.bytes(t, Some(RegFieldDesc(s"mtimecmp_$i", "", reset=None))))}, timeOffset -> RegFieldGroup("mtime", Some("Timer Register"), RegField.bytes(time, Some(RegFieldDesc("mtime", "", reset=Some(0), volatile=true)))) ) } } /** Trait that will connect a CLINT to a subsystem */ trait CanHavePeripheryCLINT { this: BaseSubsystem => val (clintOpt, clintDomainOpt, clintTickOpt) = p(CLINTKey).map { params => val tlbus = locateTLBusWrapper(p(CLINTAttachKey).slaveWhere) val clintDomainWrapper = tlbus.generateSynchronousDomain("CLINT").suggestName("clint_domain") val clint = clintDomainWrapper { LazyModule(new CLINT(params, tlbus.beatBytes)) } clintDomainWrapper { clint.node := tlbus.coupleTo("clint") { TLFragmenter(tlbus, Some("CLINT")) := _ } } val clintTick = clintDomainWrapper { InModuleBody { val tick = IO(Input(Bool())) clint.module.io.rtcTick := tick tick }} (clint, clintDomainWrapper, clintTick) }.unzip3 }

module CLINT( // @[CLINT.scala:65:9] input clock, // @[CLINT.scala:65:9] input reset, // @[CLINT.scala:65:9] output auto_int_out_0, // @[LazyModuleImp.scala:107:25] output auto_int_out_1, // @[LazyModuleImp.scala:107:25] output auto_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [1:0] auto_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [12:0] auto_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [25:0] auto_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [12:0] auto_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output [63:0] auto_in_d_bits_data, // @[LazyModuleImp.scala:107:25] input io_rtcTick // @[CLINT.scala:69:16] ); wire out_front_valid; // @[RegisterRouter.scala:87:24] wire out_front_ready; // @[RegisterRouter.scala:87:24] wire out_bits_read; // @[RegisterRouter.scala:87:24] wire [12:0] out_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:87:24] wire [12:0] in_bits_index; // @[RegisterRouter.scala:73:18] wire in_bits_read; // @[RegisterRouter.scala:73:18] wire auto_in_a_valid_0 = auto_in_a_valid; // @[CLINT.scala:65:9] wire [2:0] auto_in_a_bits_opcode_0 = auto_in_a_bits_opcode; // @[CLINT.scala:65:9] wire [2:0] auto_in_a_bits_param_0 = auto_in_a_bits_param; // @[CLINT.scala:65:9] wire [1:0] auto_in_a_bits_size_0 = auto_in_a_bits_size; // @[CLINT.scala:65:9] wire [12:0] auto_in_a_bits_source_0 = auto_in_a_bits_source; // @[CLINT.scala:65:9] wire [25:0] auto_in_a_bits_address_0 = auto_in_a_bits_address; // @[CLINT.scala:65:9] wire [7:0] auto_in_a_bits_mask_0 = auto_in_a_bits_mask; // @[CLINT.scala:65:9] wire [63:0] auto_in_a_bits_data_0 = auto_in_a_bits_data; // @[CLINT.scala:65:9] wire auto_in_a_bits_corrupt_0 = auto_in_a_bits_corrupt; // @[CLINT.scala:65:9] wire auto_in_d_ready_0 = auto_in_d_ready; // @[CLINT.scala:65:9] wire io_rtcTick_0 = io_rtcTick; // @[CLINT.scala:65:9] wire [12:0] out_maskMatch = 13'h7FF; // @[RegisterRouter.scala:87:24] wire [2:0] nodeIn_d_bits_d_opcode = 3'h0; // @[Edges.scala:792:17] wire [63:0] _out_out_bits_data_WIRE_1_3 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] nodeIn_d_bits_d_data = 64'h0; // @[Edges.scala:792:17] wire auto_in_d_bits_sink = 1'h0; // @[CLINT.scala:65:9] wire auto_in_d_bits_denied = 1'h0; // @[CLINT.scala:65:9] wire auto_in_d_bits_corrupt = 1'h0; // @[CLINT.scala:65:9] wire nodeIn_d_bits_sink = 1'h0; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_denied = 1'h0; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17] wire _valids_WIRE_0 = 1'h0; // @[RegField.scala:153:53] wire _valids_WIRE_1 = 1'h0; // @[RegField.scala:153:53] wire _valids_WIRE_2 = 1'h0; // @[RegField.scala:153:53] wire _valids_WIRE_3 = 1'h0; // @[RegField.scala:153:53] wire _valids_WIRE_4 = 1'h0; // @[RegField.scala:153:53] wire _valids_WIRE_5 = 1'h0; // @[RegField.scala:153:53] wire _valids_WIRE_6 = 1'h0; // @[RegField.scala:153:53] wire _valids_WIRE_7 = 1'h0; // @[RegField.scala:153:53] wire _valids_WIRE_1_0 = 1'h0; // @[RegField.scala:153:53] wire _valids_WIRE_1_1 = 1'h0; // @[RegField.scala:153:53] wire _valids_WIRE_1_2 = 1'h0; // @[RegField.scala:153:53] wire _valids_WIRE_1_3 = 1'h0; // @[RegField.scala:153:53] wire _valids_WIRE_1_4 = 1'h0; // @[RegField.scala:153:53] wire _valids_WIRE_1_5 = 1'h0; // @[RegField.scala:153:53] wire _valids_WIRE_1_6 = 1'h0; // @[RegField.scala:153:53] wire _valids_WIRE_1_7 = 1'h0; // @[RegField.scala:153:53] wire _out_rifireMux_T_16 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_18 = 1'h0; // @[MuxLiteral.scala:49:17] wire _out_wifireMux_T_17 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_19 = 1'h0; // @[MuxLiteral.scala:49:17] wire _out_rofireMux_T_16 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_18 = 1'h0; // @[MuxLiteral.scala:49:17] wire _out_wofireMux_T_17 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_19 = 1'h0; // @[MuxLiteral.scala:49:17] wire _out_out_bits_data_T = 1'h0; // @[MuxLiteral.scala:49:17] wire _out_out_bits_data_T_2 = 1'h0; // @[MuxLiteral.scala:49:17] wire nodeIn_d_bits_d_sink = 1'h0; // @[Edges.scala:792:17] wire nodeIn_d_bits_d_denied = 1'h0; // @[Edges.scala:792:17] wire nodeIn_d_bits_d_corrupt = 1'h0; // @[Edges.scala:792:17] wire [1:0] auto_in_d_bits_param = 2'h0; // @[CLINT.scala:65:9] wire [1:0] nodeIn_d_bits_param = 2'h0; // @[MixedNode.scala:551:17] wire [1:0] nodeIn_d_bits_d_param = 2'h0; // @[Edges.scala:792:17] wire intnodeOut_0; // @[MixedNode.scala:542:17] wire out_rifireMux_out = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_5 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_1 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_9 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_2 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_13 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_3 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_17 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_2 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_3 = 1'h1; // @[MuxLiteral.scala:49:48] wire out_rifireMux = 1'h1; // @[MuxLiteral.scala:49:10] wire out_wifireMux_out = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_6 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_1 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_10 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_2 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_14 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_3 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_18 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_2 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_3 = 1'h1; // @[MuxLiteral.scala:49:48] wire out_wifireMux = 1'h1; // @[MuxLiteral.scala:49:10] wire out_rofireMux_out = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_5 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_1 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_9 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_2 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_13 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_3 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_17 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_2 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_3 = 1'h1; // @[MuxLiteral.scala:49:48] wire out_rofireMux = 1'h1; // @[MuxLiteral.scala:49:10] wire out_wofireMux_out = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_6 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_1 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_10 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_2 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_14 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_3 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_18 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_2 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_3 = 1'h1; // @[MuxLiteral.scala:49:48] wire out_wofireMux = 1'h1; // @[MuxLiteral.scala:49:10] wire out_iready = 1'h1; // @[RegisterRouter.scala:87:24] wire out_oready = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_out_bits_data_WIRE_3 = 1'h1; // @[MuxLiteral.scala:49:48] wire intnodeOut_1; // @[MixedNode.scala:542:17] wire nodeIn_a_ready; // @[MixedNode.scala:551:17] wire nodeIn_a_valid = auto_in_a_valid_0; // @[CLINT.scala:65:9] wire [2:0] nodeIn_a_bits_opcode = auto_in_a_bits_opcode_0; // @[CLINT.scala:65:9] wire [2:0] nodeIn_a_bits_param = auto_in_a_bits_param_0; // @[CLINT.scala:65:9] wire [1:0] nodeIn_a_bits_size = auto_in_a_bits_size_0; // @[CLINT.scala:65:9] wire [12:0] nodeIn_a_bits_source = auto_in_a_bits_source_0; // @[CLINT.scala:65:9] wire [25:0] nodeIn_a_bits_address = auto_in_a_bits_address_0; // @[CLINT.scala:65:9] wire [7:0] nodeIn_a_bits_mask = auto_in_a_bits_mask_0; // @[CLINT.scala:65:9] wire [63:0] nodeIn_a_bits_data = auto_in_a_bits_data_0; // @[CLINT.scala:65:9] wire nodeIn_a_bits_corrupt = auto_in_a_bits_corrupt_0; // @[CLINT.scala:65:9] wire nodeIn_d_ready = auto_in_d_ready_0; // @[CLINT.scala:65:9] wire nodeIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] nodeIn_d_bits_size; // @[MixedNode.scala:551:17] wire [12:0] nodeIn_d_bits_source; // @[MixedNode.scala:551:17] wire [63:0] nodeIn_d_bits_data; // @[MixedNode.scala:551:17] wire auto_int_out_0_0; // @[CLINT.scala:65:9] wire auto_int_out_1_0; // @[CLINT.scala:65:9] wire auto_in_a_ready_0; // @[CLINT.scala:65:9] wire [2:0] auto_in_d_bits_opcode_0; // @[CLINT.scala:65:9] wire [1:0] auto_in_d_bits_size_0; // @[CLINT.scala:65:9] wire [12:0] auto_in_d_bits_source_0; // @[CLINT.scala:65:9] wire [63:0] auto_in_d_bits_data_0; // @[CLINT.scala:65:9] wire auto_in_d_valid_0; // @[CLINT.scala:65:9] wire in_ready; // @[RegisterRouter.scala:73:18] assign auto_in_a_ready_0 = nodeIn_a_ready; // @[CLINT.scala:65:9] wire in_valid = nodeIn_a_valid; // @[RegisterRouter.scala:73:18] wire [1:0] in_bits_extra_tlrr_extra_size = nodeIn_a_bits_size; // @[RegisterRouter.scala:73:18] wire [12:0] in_bits_extra_tlrr_extra_source = nodeIn_a_bits_source; // @[RegisterRouter.scala:73:18] wire [7:0] in_bits_mask = nodeIn_a_bits_mask; // @[RegisterRouter.scala:73:18] wire [63:0] in_bits_data = nodeIn_a_bits_data; // @[RegisterRouter.scala:73:18] wire out_ready = nodeIn_d_ready; // @[RegisterRouter.scala:87:24] wire out_valid; // @[RegisterRouter.scala:87:24] assign auto_in_d_valid_0 = nodeIn_d_valid; // @[CLINT.scala:65:9] assign auto_in_d_bits_opcode_0 = nodeIn_d_bits_opcode; // @[CLINT.scala:65:9] wire [1:0] nodeIn_d_bits_d_size; // @[Edges.scala:792:17] assign auto_in_d_bits_size_0 = nodeIn_d_bits_size; // @[CLINT.scala:65:9] wire [12:0] nodeIn_d_bits_d_source; // @[Edges.scala:792:17] assign auto_in_d_bits_source_0 = nodeIn_d_bits_source; // @[CLINT.scala:65:9] wire [63:0] out_bits_data; // @[RegisterRouter.scala:87:24] assign auto_in_d_bits_data_0 = nodeIn_d_bits_data; // @[CLINT.scala:65:9] wire _intnodeOut_0_T; // @[CLINT.scala:82:37] assign auto_int_out_0_0 = intnodeOut_0; // @[CLINT.scala:65:9] wire _intnodeOut_1_T; // @[CLINT.scala:83:43] assign auto_int_out_1_0 = intnodeOut_1; // @[CLINT.scala:65:9] reg [63:0] time_0; // @[CLINT.scala:73:23] wire [63:0] pad_1 = time_0; // @[RegField.scala:150:19] wire [64:0] _time_T = {1'h0, time_0} + 65'h1; // @[CLINT.scala:73:23, :74:38] wire [63:0] _time_T_1 = _time_T[63:0]; // @[CLINT.scala:74:38] reg [63:0] timecmp_0; // @[CLINT.scala:77:41] wire [63:0] pad = timecmp_0; // @[RegField.scala:150:19] reg ipi_0; // @[CLINT.scala:78:41] assign _intnodeOut_0_T = ipi_0; // @[CLINT.scala:78:41, :82:37] wire _out_T_15 = ipi_0; // @[RegisterRouter.scala:87:24] assign intnodeOut_0 = _intnodeOut_0_T; // @[CLINT.scala:82:37] assign _intnodeOut_1_T = time_0 >= timecmp_0; // @[CLINT.scala:73:23, :77:41, :83:43] assign intnodeOut_1 = _intnodeOut_1_T; // @[CLINT.scala:83:43] wire [7:0] _oldBytes_T = pad[7:0]; // @[RegField.scala:150:19, :151:57] wire [7:0] oldBytes_0 = _oldBytes_T; // @[RegField.scala:151:{47,57}] wire [7:0] _oldBytes_T_1 = pad[15:8]; // @[RegField.scala:150:19, :151:57] wire [7:0] oldBytes_1 = _oldBytes_T_1; // @[RegField.scala:151:{47,57}] wire [7:0] _oldBytes_T_2 = pad[23:16]; // @[RegField.scala:150:19, :151:57] wire [7:0] oldBytes_2 = _oldBytes_T_2; // @[RegField.scala:151:{47,57}] wire [7:0] _oldBytes_T_3 = pad[31:24]; // @[RegField.scala:150:19, :151:57] wire [7:0] oldBytes_3 = _oldBytes_T_3; // @[RegField.scala:151:{47,57}] wire [7:0] _oldBytes_T_4 = pad[39:32]; // @[RegField.scala:150:19, :151:57] wire [7:0] oldBytes_4 = _oldBytes_T_4; // @[RegField.scala:151:{47,57}] wire [7:0] _oldBytes_T_5 = pad[47:40]; // @[RegField.scala:150:19, :151:57] wire [7:0] oldBytes_5 = _oldBytes_T_5; // @[RegField.scala:151:{47,57}] wire [7:0] _oldBytes_T_6 = pad[55:48]; // @[RegField.scala:150:19, :151:57] wire [7:0] oldBytes_6 = _oldBytes_T_6; // @[RegField.scala:151:{47,57}] wire [7:0] _oldBytes_T_7 = pad[63:56]; // @[RegField.scala:150:19, :151:57] wire [7:0] oldBytes_7 = _oldBytes_T_7; // @[RegField.scala:151:{47,57}] wire [7:0] _out_T_123 = oldBytes_0; // @[RegisterRouter.scala:87:24] wire [7:0] newBytes_0; // @[RegField.scala:152:31] wire [7:0] newBytes_1; // @[RegField.scala:152:31] wire [7:0] newBytes_2; // @[RegField.scala:152:31] wire [7:0] newBytes_3; // @[RegField.scala:152:31] wire [7:0] newBytes_4; // @[RegField.scala:152:31] wire [7:0] newBytes_5; // @[RegField.scala:152:31] wire [7:0] newBytes_6; // @[RegField.scala:152:31] wire [7:0] newBytes_7; // @[RegField.scala:152:31] wire out_f_woready_10; // @[RegisterRouter.scala:87:24] wire out_f_woready_11; // @[RegisterRouter.scala:87:24] wire out_f_woready_12; // @[RegisterRouter.scala:87:24] wire out_f_woready_13; // @[RegisterRouter.scala:87:24] wire out_f_woready_14; // @[RegisterRouter.scala:87:24] wire out_f_woready_15; // @[RegisterRouter.scala:87:24] wire out_f_woready_16; // @[RegisterRouter.scala:87:24] wire out_f_woready_17; // @[RegisterRouter.scala:87:24] wire valids_0; // @[RegField.scala:153:29] wire valids_1; // @[RegField.scala:153:29] wire valids_2; // @[RegField.scala:153:29] wire valids_3; // @[RegField.scala:153:29] wire valids_4; // @[RegField.scala:153:29] wire valids_5; // @[RegField.scala:153:29] wire valids_6; // @[RegField.scala:153:29] wire valids_7; // @[RegField.scala:153:29] wire [15:0] timecmp_0_lo_lo = {newBytes_1, newBytes_0}; // @[RegField.scala:152:31, :154:52] wire [15:0] timecmp_0_lo_hi = {newBytes_3, newBytes_2}; // @[RegField.scala:152:31, :154:52] wire [31:0] timecmp_0_lo = {timecmp_0_lo_hi, timecmp_0_lo_lo}; // @[RegField.scala:154:52] wire [15:0] timecmp_0_hi_lo = {newBytes_5, newBytes_4}; // @[RegField.scala:152:31, :154:52] wire [15:0] timecmp_0_hi_hi = {newBytes_7, newBytes_6}; // @[RegField.scala:152:31, :154:52] wire [31:0] timecmp_0_hi = {timecmp_0_hi_hi, timecmp_0_hi_lo}; // @[RegField.scala:154:52] wire [63:0] _timecmp_0_T = {timecmp_0_hi, timecmp_0_lo}; // @[RegField.scala:154:52] wire [7:0] _oldBytes_T_8 = pad_1[7:0]; // @[RegField.scala:150:19, :151:57] wire [7:0] oldBytes_1_0 = _oldBytes_T_8; // @[RegField.scala:151:{47,57}] wire [7:0] _oldBytes_T_9 = pad_1[15:8]; // @[RegField.scala:150:19, :151:57] wire [7:0] oldBytes_1_1 = _oldBytes_T_9; // @[RegField.scala:151:{47,57}] wire [7:0] _oldBytes_T_10 = pad_1[23:16]; // @[RegField.scala:150:19, :151:57] wire [7:0] oldBytes_1_2 = _oldBytes_T_10; // @[RegField.scala:151:{47,57}] wire [7:0] _oldBytes_T_11 = pad_1[31:24]; // @[RegField.scala:150:19, :151:57] wire [7:0] oldBytes_1_3 = _oldBytes_T_11; // @[RegField.scala:151:{47,57}] wire [7:0] _oldBytes_T_12 = pad_1[39:32]; // @[RegField.scala:150:19, :151:57] wire [7:0] oldBytes_1_4 = _oldBytes_T_12; // @[RegField.scala:151:{47,57}] wire [7:0] _oldBytes_T_13 = pad_1[47:40]; // @[RegField.scala:150:19, :151:57] wire [7:0] oldBytes_1_5 = _oldBytes_T_13; // @[RegField.scala:151:{47,57}] wire [7:0] _oldBytes_T_14 = pad_1[55:48]; // @[RegField.scala:150:19, :151:57] wire [7:0] oldBytes_1_6 = _oldBytes_T_14; // @[RegField.scala:151:{47,57}] wire [7:0] _oldBytes_T_15 = pad_1[63:56]; // @[RegField.scala:150:19, :151:57] wire [7:0] oldBytes_1_7 = _oldBytes_T_15; // @[RegField.scala:151:{47,57}] wire [7:0] _out_T_35 = oldBytes_1_0; // @[RegisterRouter.scala:87:24] wire [7:0] newBytes_1_0; // @[RegField.scala:152:31] wire [7:0] newBytes_1_1; // @[RegField.scala:152:31] wire [7:0] newBytes_1_2; // @[RegField.scala:152:31] wire [7:0] newBytes_1_3; // @[RegField.scala:152:31] wire [7:0] newBytes_1_4; // @[RegField.scala:152:31] wire [7:0] newBytes_1_5; // @[RegField.scala:152:31] wire [7:0] newBytes_1_6; // @[RegField.scala:152:31] wire [7:0] newBytes_1_7; // @[RegField.scala:152:31] wire out_f_woready_2; // @[RegisterRouter.scala:87:24] wire out_f_woready_3; // @[RegisterRouter.scala:87:24] wire out_f_woready_4; // @[RegisterRouter.scala:87:24] wire out_f_woready_5; // @[RegisterRouter.scala:87:24] wire out_f_woready_6; // @[RegisterRouter.scala:87:24] wire out_f_woready_7; // @[RegisterRouter.scala:87:24] wire out_f_woready_8; // @[RegisterRouter.scala:87:24] wire out_f_woready_9; // @[RegisterRouter.scala:87:24] wire valids_1_0; // @[RegField.scala:153:29] wire valids_1_1; // @[RegField.scala:153:29] wire valids_1_2; // @[RegField.scala:153:29] wire valids_1_3; // @[RegField.scala:153:29] wire valids_1_4; // @[RegField.scala:153:29] wire valids_1_5; // @[RegField.scala:153:29] wire valids_1_6; // @[RegField.scala:153:29] wire valids_1_7; // @[RegField.scala:153:29] wire [15:0] time_lo_lo = {newBytes_1_1, newBytes_1_0}; // @[RegField.scala:152:31, :154:52] wire [15:0] time_lo_hi = {newBytes_1_3, newBytes_1_2}; // @[RegField.scala:152:31, :154:52] wire [31:0] time_lo = {time_lo_hi, time_lo_lo}; // @[RegField.scala:154:52] wire [15:0] time_hi_lo = {newBytes_1_5, newBytes_1_4}; // @[RegField.scala:152:31, :154:52] wire [15:0] time_hi_hi = {newBytes_1_7, newBytes_1_6}; // @[RegField.scala:152:31, :154:52] wire [31:0] time_hi = {time_hi_hi, time_hi_lo}; // @[RegField.scala:154:52] wire [63:0] _time_T_2 = {time_hi, time_lo}; // @[RegField.scala:154:52] wire _out_in_ready_T; // @[RegisterRouter.scala:87:24] assign nodeIn_a_ready = in_ready; // @[RegisterRouter.scala:73:18] wire _in_bits_read_T; // @[RegisterRouter.scala:74:36] wire _out_front_valid_T = in_valid; // @[RegisterRouter.scala:73:18, :87:24] wire out_front_bits_read = in_bits_read; // @[RegisterRouter.scala:73:18, :87:24] wire [12:0] out_front_bits_index = in_bits_index; // @[RegisterRouter.scala:73:18, :87:24] wire [63:0] out_front_bits_data = in_bits_data; // @[RegisterRouter.scala:73:18, :87:24] wire [7:0] out_front_bits_mask = in_bits_mask; // @[RegisterRouter.scala:73:18, :87:24] wire [12:0] out_front_bits_extra_tlrr_extra_source = in_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:73:18, :87:24] wire [1:0] out_front_bits_extra_tlrr_extra_size = in_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:73:18, :87:24] assign _in_bits_read_T = nodeIn_a_bits_opcode == 3'h4; // @[RegisterRouter.scala:74:36] assign in_bits_read = _in_bits_read_T; // @[RegisterRouter.scala:73:18, :74:36] wire [22:0] _in_bits_index_T = nodeIn_a_bits_address[25:3]; // @[Edges.scala:192:34] assign in_bits_index = _in_bits_index_T[12:0]; // @[RegisterRouter.scala:73:18, :75:19] wire _out_front_ready_T = out_ready; // @[RegisterRouter.scala:87:24] wire _out_out_valid_T; // @[RegisterRouter.scala:87:24] assign nodeIn_d_valid = out_valid; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_T_4; // @[RegisterRouter.scala:87:24] wire _nodeIn_d_bits_opcode_T = out_bits_read; // @[RegisterRouter.scala:87:24, :105:25] assign nodeIn_d_bits_data = out_bits_data; // @[RegisterRouter.scala:87:24] assign nodeIn_d_bits_d_source = out_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:87:24] wire [1:0] out_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:87:24] assign nodeIn_d_bits_d_size = out_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:87:24] assign _out_in_ready_T = out_front_ready; // @[RegisterRouter.scala:87:24] assign _out_out_valid_T = out_front_valid; // @[RegisterRouter.scala:87:24] assign out_bits_read = out_front_bits_read; // @[RegisterRouter.scala:87:24] assign out_bits_extra_tlrr_extra_source = out_front_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:87:24] assign out_bits_extra_tlrr_extra_size = out_front_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:87:24] wire [12:0] _GEN = out_front_bits_index & 13'h7FF; // @[RegisterRouter.scala:87:24] wire [12:0] out_findex; // @[RegisterRouter.scala:87:24] assign out_findex = _GEN; // @[RegisterRouter.scala:87:24] wire [12:0] out_bindex; // @[RegisterRouter.scala:87:24] assign out_bindex = _GEN; // @[RegisterRouter.scala:87:24] wire _GEN_0 = out_findex == 13'h0; // @[RegisterRouter.scala:87:24] wire _out_T; // @[RegisterRouter.scala:87:24] assign _out_T = _GEN_0; // @[RegisterRouter.scala:87:24] wire _out_T_4; // @[RegisterRouter.scala:87:24] assign _out_T_4 = _GEN_0; // @[RegisterRouter.scala:87:24] wire _GEN_1 = out_bindex == 13'h0; // @[RegisterRouter.scala:87:24] wire _out_T_1; // @[RegisterRouter.scala:87:24] assign _out_T_1 = _GEN_1; // @[RegisterRouter.scala:87:24] wire _out_T_5; // @[RegisterRouter.scala:87:24] assign _out_T_5 = _GEN_1; // @[RegisterRouter.scala:87:24] wire _out_out_bits_data_WIRE_0 = _out_T_1; // @[MuxLiteral.scala:49:48] wire _out_T_2 = out_findex == 13'h7FF; // @[RegisterRouter.scala:87:24] wire _out_T_3 = out_bindex == 13'h7FF; // @[RegisterRouter.scala:87:24] wire _out_out_bits_data_WIRE_2 = _out_T_3; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24] wire _out_out_bits_data_WIRE_1 = _out_T_5; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_T_11; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_7; // @[RegisterRouter.scala:87:24] wire out_rivalid_0; // @[RegisterRouter.scala:87:24] wire out_rivalid_1; // @[RegisterRouter.scala:87:24] wire out_rivalid_2; // @[RegisterRouter.scala:87:24] wire out_rivalid_3; // @[RegisterRouter.scala:87:24] wire out_rivalid_4; // @[RegisterRouter.scala:87:24] wire out_rivalid_5; // @[RegisterRouter.scala:87:24] wire out_rivalid_6; // @[RegisterRouter.scala:87:24] wire out_rivalid_7; // @[RegisterRouter.scala:87:24] wire out_rivalid_8; // @[RegisterRouter.scala:87:24] wire out_rivalid_9; // @[RegisterRouter.scala:87:24] wire out_rivalid_10; // @[RegisterRouter.scala:87:24] wire out_rivalid_11; // @[RegisterRouter.scala:87:24] wire out_rivalid_12; // @[RegisterRouter.scala:87:24] wire out_rivalid_13; // @[RegisterRouter.scala:87:24] wire out_rivalid_14; // @[RegisterRouter.scala:87:24] wire out_rivalid_15; // @[RegisterRouter.scala:87:24] wire out_rivalid_16; // @[RegisterRouter.scala:87:24] wire out_rivalid_17; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_12; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_8; // @[RegisterRouter.scala:87:24] wire out_wivalid_0; // @[RegisterRouter.scala:87:24] wire out_wivalid_1; // @[RegisterRouter.scala:87:24] wire out_wivalid_2; // @[RegisterRouter.scala:87:24] wire out_wivalid_3; // @[RegisterRouter.scala:87:24] wire out_wivalid_4; // @[RegisterRouter.scala:87:24] wire out_wivalid_5; // @[RegisterRouter.scala:87:24] wire out_wivalid_6; // @[RegisterRouter.scala:87:24] wire out_wivalid_7; // @[RegisterRouter.scala:87:24] wire out_wivalid_8; // @[RegisterRouter.scala:87:24] wire out_wivalid_9; // @[RegisterRouter.scala:87:24] wire out_wivalid_10; // @[RegisterRouter.scala:87:24] wire out_wivalid_11; // @[RegisterRouter.scala:87:24] wire out_wivalid_12; // @[RegisterRouter.scala:87:24] wire out_wivalid_13; // @[RegisterRouter.scala:87:24] wire out_wivalid_14; // @[RegisterRouter.scala:87:24] wire out_wivalid_15; // @[RegisterRouter.scala:87:24] wire out_wivalid_16; // @[RegisterRouter.scala:87:24] wire out_wivalid_17; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_11; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_7; // @[RegisterRouter.scala:87:24] wire out_roready_0; // @[RegisterRouter.scala:87:24] wire out_roready_1; // @[RegisterRouter.scala:87:24] wire out_roready_2; // @[RegisterRouter.scala:87:24] wire out_roready_3; // @[RegisterRouter.scala:87:24] wire out_roready_4; // @[RegisterRouter.scala:87:24] wire out_roready_5; // @[RegisterRouter.scala:87:24] wire out_roready_6; // @[RegisterRouter.scala:87:24] wire out_roready_7; // @[RegisterRouter.scala:87:24] wire out_roready_8; // @[RegisterRouter.scala:87:24] wire out_roready_9; // @[RegisterRouter.scala:87:24] wire out_roready_10; // @[RegisterRouter.scala:87:24] wire out_roready_11; // @[RegisterRouter.scala:87:24] wire out_roready_12; // @[RegisterRouter.scala:87:24] wire out_roready_13; // @[RegisterRouter.scala:87:24] wire out_roready_14; // @[RegisterRouter.scala:87:24] wire out_roready_15; // @[RegisterRouter.scala:87:24] wire out_roready_16; // @[RegisterRouter.scala:87:24] wire out_roready_17; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_12; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_8; // @[RegisterRouter.scala:87:24] wire out_woready_0; // @[RegisterRouter.scala:87:24] wire out_woready_1; // @[RegisterRouter.scala:87:24] wire out_woready_2; // @[RegisterRouter.scala:87:24] wire out_woready_3; // @[RegisterRouter.scala:87:24] wire out_woready_4; // @[RegisterRouter.scala:87:24] wire out_woready_5; // @[RegisterRouter.scala:87:24] wire out_woready_6; // @[RegisterRouter.scala:87:24] wire out_woready_7; // @[RegisterRouter.scala:87:24] wire out_woready_8; // @[RegisterRouter.scala:87:24] wire out_woready_9; // @[RegisterRouter.scala:87:24] wire out_woready_10; // @[RegisterRouter.scala:87:24] wire out_woready_11; // @[RegisterRouter.scala:87:24] wire out_woready_12; // @[RegisterRouter.scala:87:24] wire out_woready_13; // @[RegisterRouter.scala:87:24] wire out_woready_14; // @[RegisterRouter.scala:87:24] wire out_woready_15; // @[RegisterRouter.scala:87:24] wire out_woready_16; // @[RegisterRouter.scala:87:24] wire out_woready_17; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T = out_front_bits_mask[0]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T = out_front_bits_mask[0]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_1 = out_front_bits_mask[1]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_1 = out_front_bits_mask[1]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_2 = out_front_bits_mask[2]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_2 = out_front_bits_mask[2]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_3 = out_front_bits_mask[3]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_3 = out_front_bits_mask[3]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_4 = out_front_bits_mask[4]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_4 = out_front_bits_mask[4]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_5 = out_front_bits_mask[5]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_5 = out_front_bits_mask[5]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_6 = out_front_bits_mask[6]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_6 = out_front_bits_mask[6]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_7 = out_front_bits_mask[7]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_7 = out_front_bits_mask[7]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_8 = {8{_out_frontMask_T}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_9 = {8{_out_frontMask_T_1}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_10 = {8{_out_frontMask_T_2}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_11 = {8{_out_frontMask_T_3}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_12 = {8{_out_frontMask_T_4}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_13 = {8{_out_frontMask_T_5}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_14 = {8{_out_frontMask_T_6}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_15 = {8{_out_frontMask_T_7}}; // @[RegisterRouter.scala:87:24] wire [15:0] out_frontMask_lo_lo = {_out_frontMask_T_9, _out_frontMask_T_8}; // @[RegisterRouter.scala:87:24] wire [15:0] out_frontMask_lo_hi = {_out_frontMask_T_11, _out_frontMask_T_10}; // @[RegisterRouter.scala:87:24] wire [31:0] out_frontMask_lo = {out_frontMask_lo_hi, out_frontMask_lo_lo}; // @[RegisterRouter.scala:87:24] wire [15:0] out_frontMask_hi_lo = {_out_frontMask_T_13, _out_frontMask_T_12}; // @[RegisterRouter.scala:87:24] wire [15:0] out_frontMask_hi_hi = {_out_frontMask_T_15, _out_frontMask_T_14}; // @[RegisterRouter.scala:87:24] wire [31:0] out_frontMask_hi = {out_frontMask_hi_hi, out_frontMask_hi_lo}; // @[RegisterRouter.scala:87:24] wire [63:0] out_frontMask = {out_frontMask_hi, out_frontMask_lo}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_8 = {8{_out_backMask_T}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_9 = {8{_out_backMask_T_1}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_10 = {8{_out_backMask_T_2}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_11 = {8{_out_backMask_T_3}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_12 = {8{_out_backMask_T_4}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_13 = {8{_out_backMask_T_5}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_14 = {8{_out_backMask_T_6}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_15 = {8{_out_backMask_T_7}}; // @[RegisterRouter.scala:87:24] wire [15:0] out_backMask_lo_lo = {_out_backMask_T_9, _out_backMask_T_8}; // @[RegisterRouter.scala:87:24] wire [15:0] out_backMask_lo_hi = {_out_backMask_T_11, _out_backMask_T_10}; // @[RegisterRouter.scala:87:24] wire [31:0] out_backMask_lo = {out_backMask_lo_hi, out_backMask_lo_lo}; // @[RegisterRouter.scala:87:24] wire [15:0] out_backMask_hi_lo = {_out_backMask_T_13, _out_backMask_T_12}; // @[RegisterRouter.scala:87:24] wire [15:0] out_backMask_hi_hi = {_out_backMask_T_15, _out_backMask_T_14}; // @[RegisterRouter.scala:87:24] wire [31:0] out_backMask_hi = {out_backMask_hi_hi, out_backMask_hi_lo}; // @[RegisterRouter.scala:87:24] wire [63:0] out_backMask = {out_backMask_hi, out_backMask_lo}; // @[RegisterRouter.scala:87:24] wire _out_rimask_T = out_frontMask[0]; // @[RegisterRouter.scala:87:24] wire _out_wimask_T = out_frontMask[0]; // @[RegisterRouter.scala:87:24] wire out_rimask = _out_rimask_T; // @[RegisterRouter.scala:87:24] wire out_wimask = _out_wimask_T; // @[RegisterRouter.scala:87:24] wire _out_romask_T = out_backMask[0]; // @[RegisterRouter.scala:87:24] wire _out_womask_T = out_backMask[0]; // @[RegisterRouter.scala:87:24] wire out_romask = _out_romask_T; // @[RegisterRouter.scala:87:24] wire out_womask = _out_womask_T; // @[RegisterRouter.scala:87:24] wire out_f_rivalid = out_rivalid_0 & out_rimask; // @[RegisterRouter.scala:87:24] wire _out_T_7 = out_f_rivalid; // @[RegisterRouter.scala:87:24] wire out_f_roready = out_roready_0 & out_romask; // @[RegisterRouter.scala:87:24] wire _out_T_8 = out_f_roready; // @[RegisterRouter.scala:87:24] wire out_f_wivalid = out_wivalid_0 & out_wimask; // @[RegisterRouter.scala:87:24] wire _out_T_9 = out_f_wivalid; // @[RegisterRouter.scala:87:24] wire out_f_woready = out_woready_0 & out_womask; // @[RegisterRouter.scala:87:24] wire _out_T_10 = out_f_woready; // @[RegisterRouter.scala:87:24] wire _out_T_6 = out_front_bits_data[0]; // @[RegisterRouter.scala:87:24] wire _out_T_11 = ~out_rimask; // @[RegisterRouter.scala:87:24] wire _out_T_12 = ~out_wimask; // @[RegisterRouter.scala:87:24] wire _out_T_13 = ~out_romask; // @[RegisterRouter.scala:87:24] wire _out_T_14 = ~out_womask; // @[RegisterRouter.scala:87:24] wire _out_T_16 = _out_T_15; // @[RegisterRouter.scala:87:24] wire _out_prepend_T = _out_T_16; // @[RegisterRouter.scala:87:24] wire [30:0] _out_rimask_T_1 = out_frontMask[31:1]; // @[RegisterRouter.scala:87:24] wire [30:0] _out_wimask_T_1 = out_frontMask[31:1]; // @[RegisterRouter.scala:87:24] wire out_rimask_1 = |_out_rimask_T_1; // @[RegisterRouter.scala:87:24] wire out_wimask_1 = &_out_wimask_T_1; // @[RegisterRouter.scala:87:24] wire [30:0] _out_romask_T_1 = out_backMask[31:1]; // @[RegisterRouter.scala:87:24] wire [30:0] _out_womask_T_1 = out_backMask[31:1]; // @[RegisterRouter.scala:87:24] wire out_romask_1 = |_out_romask_T_1; // @[RegisterRouter.scala:87:24] wire out_womask_1 = &_out_womask_T_1; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1 = out_rivalid_1 & out_rimask_1; // @[RegisterRouter.scala:87:24] wire _out_T_18 = out_f_rivalid_1; // @[RegisterRouter.scala:87:24] wire out_f_roready_1 = out_roready_1 & out_romask_1; // @[RegisterRouter.scala:87:24] wire _out_T_19 = out_f_roready_1; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1 = out_wivalid_1 & out_wimask_1; // @[RegisterRouter.scala:87:24] wire out_f_woready_1 = out_woready_1 & out_womask_1; // @[RegisterRouter.scala:87:24] wire [30:0] _out_T_17 = out_front_bits_data[31:1]; // @[RegisterRouter.scala:87:24] wire _out_T_20 = ~out_rimask_1; // @[RegisterRouter.scala:87:24] wire _out_T_21 = ~out_wimask_1; // @[RegisterRouter.scala:87:24] wire _out_T_22 = ~out_romask_1; // @[RegisterRouter.scala:87:24] wire _out_T_23 = ~out_womask_1; // @[RegisterRouter.scala:87:24] wire [1:0] out_prepend = {1'h0, _out_prepend_T}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_24 = {30'h0, out_prepend}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_25 = _out_T_24; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_2 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_2 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_10 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_10 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24] wire out_rimask_2 = |_out_rimask_T_2; // @[RegisterRouter.scala:87:24] wire out_wimask_2 = &_out_wimask_T_2; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_2 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_2 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_10 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_10 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24] wire out_romask_2 = |_out_romask_T_2; // @[RegisterRouter.scala:87:24] wire out_womask_2 = &_out_womask_T_2; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_2 = out_rivalid_2 & out_rimask_2; // @[RegisterRouter.scala:87:24] wire _out_T_27 = out_f_rivalid_2; // @[RegisterRouter.scala:87:24] wire out_f_roready_2 = out_roready_2 & out_romask_2; // @[RegisterRouter.scala:87:24] wire _out_T_28 = out_f_roready_2; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_2 = out_wivalid_2 & out_wimask_2; // @[RegisterRouter.scala:87:24] wire _out_T_29 = out_f_wivalid_2; // @[RegisterRouter.scala:87:24] assign out_f_woready_2 = out_woready_2 & out_womask_2; // @[RegisterRouter.scala:87:24] assign valids_1_0 = out_f_woready_2; // @[RegisterRouter.scala:87:24] wire _out_T_30 = out_f_woready_2; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_26 = out_front_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_114 = out_front_bits_data[7:0]; // @[RegisterRouter.scala:87:24] assign newBytes_1_0 = out_f_woready_2 ? _out_T_26 : oldBytes_1_0; // @[RegisterRouter.scala:87:24] wire _out_T_31 = ~out_rimask_2; // @[RegisterRouter.scala:87:24] wire _out_T_32 = ~out_wimask_2; // @[RegisterRouter.scala:87:24] wire _out_T_33 = ~out_romask_2; // @[RegisterRouter.scala:87:24] wire _out_T_34 = ~out_womask_2; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_36 = _out_T_35; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_1 = _out_T_36; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_3 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_3 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_11 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_11 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24] wire out_rimask_3 = |_out_rimask_T_3; // @[RegisterRouter.scala:87:24] wire out_wimask_3 = &_out_wimask_T_3; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_3 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_3 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_11 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_11 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24] wire out_romask_3 = |_out_romask_T_3; // @[RegisterRouter.scala:87:24] wire out_womask_3 = &_out_womask_T_3; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_3 = out_rivalid_3 & out_rimask_3; // @[RegisterRouter.scala:87:24] wire _out_T_38 = out_f_rivalid_3; // @[RegisterRouter.scala:87:24] wire out_f_roready_3 = out_roready_3 & out_romask_3; // @[RegisterRouter.scala:87:24] wire _out_T_39 = out_f_roready_3; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_3 = out_wivalid_3 & out_wimask_3; // @[RegisterRouter.scala:87:24] wire _out_T_40 = out_f_wivalid_3; // @[RegisterRouter.scala:87:24] assign out_f_woready_3 = out_woready_3 & out_womask_3; // @[RegisterRouter.scala:87:24] assign valids_1_1 = out_f_woready_3; // @[RegisterRouter.scala:87:24] wire _out_T_41 = out_f_woready_3; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_37 = out_front_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_125 = out_front_bits_data[15:8]; // @[RegisterRouter.scala:87:24] assign newBytes_1_1 = out_f_woready_3 ? _out_T_37 : oldBytes_1_1; // @[RegisterRouter.scala:87:24] wire _out_T_42 = ~out_rimask_3; // @[RegisterRouter.scala:87:24] wire _out_T_43 = ~out_wimask_3; // @[RegisterRouter.scala:87:24] wire _out_T_44 = ~out_romask_3; // @[RegisterRouter.scala:87:24] wire _out_T_45 = ~out_womask_3; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_1 = {oldBytes_1_1, _out_prepend_T_1}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_46 = out_prepend_1; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_47 = _out_T_46; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_2 = _out_T_47; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_4 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_4 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_12 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_12 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24] wire out_rimask_4 = |_out_rimask_T_4; // @[RegisterRouter.scala:87:24] wire out_wimask_4 = &_out_wimask_T_4; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_4 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_4 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_12 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_12 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24] wire out_romask_4 = |_out_romask_T_4; // @[RegisterRouter.scala:87:24] wire out_womask_4 = &_out_womask_T_4; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_4 = out_rivalid_4 & out_rimask_4; // @[RegisterRouter.scala:87:24] wire _out_T_49 = out_f_rivalid_4; // @[RegisterRouter.scala:87:24] wire out_f_roready_4 = out_roready_4 & out_romask_4; // @[RegisterRouter.scala:87:24] wire _out_T_50 = out_f_roready_4; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_4 = out_wivalid_4 & out_wimask_4; // @[RegisterRouter.scala:87:24] wire _out_T_51 = out_f_wivalid_4; // @[RegisterRouter.scala:87:24] assign out_f_woready_4 = out_woready_4 & out_womask_4; // @[RegisterRouter.scala:87:24] assign valids_1_2 = out_f_woready_4; // @[RegisterRouter.scala:87:24] wire _out_T_52 = out_f_woready_4; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_48 = out_front_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_136 = out_front_bits_data[23:16]; // @[RegisterRouter.scala:87:24] assign newBytes_1_2 = out_f_woready_4 ? _out_T_48 : oldBytes_1_2; // @[RegisterRouter.scala:87:24] wire _out_T_53 = ~out_rimask_4; // @[RegisterRouter.scala:87:24] wire _out_T_54 = ~out_wimask_4; // @[RegisterRouter.scala:87:24] wire _out_T_55 = ~out_romask_4; // @[RegisterRouter.scala:87:24] wire _out_T_56 = ~out_womask_4; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_2 = {oldBytes_1_2, _out_prepend_T_2}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_57 = out_prepend_2; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_58 = _out_T_57; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_3 = _out_T_58; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_5 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_5 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_13 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_13 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24] wire out_rimask_5 = |_out_rimask_T_5; // @[RegisterRouter.scala:87:24] wire out_wimask_5 = &_out_wimask_T_5; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_5 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_5 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_13 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_13 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24] wire out_romask_5 = |_out_romask_T_5; // @[RegisterRouter.scala:87:24] wire out_womask_5 = &_out_womask_T_5; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_5 = out_rivalid_5 & out_rimask_5; // @[RegisterRouter.scala:87:24] wire _out_T_60 = out_f_rivalid_5; // @[RegisterRouter.scala:87:24] wire out_f_roready_5 = out_roready_5 & out_romask_5; // @[RegisterRouter.scala:87:24] wire _out_T_61 = out_f_roready_5; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_5 = out_wivalid_5 & out_wimask_5; // @[RegisterRouter.scala:87:24] wire _out_T_62 = out_f_wivalid_5; // @[RegisterRouter.scala:87:24] assign out_f_woready_5 = out_woready_5 & out_womask_5; // @[RegisterRouter.scala:87:24] assign valids_1_3 = out_f_woready_5; // @[RegisterRouter.scala:87:24] wire _out_T_63 = out_f_woready_5; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_59 = out_front_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_147 = out_front_bits_data[31:24]; // @[RegisterRouter.scala:87:24] assign newBytes_1_3 = out_f_woready_5 ? _out_T_59 : oldBytes_1_3; // @[RegisterRouter.scala:87:24] wire _out_T_64 = ~out_rimask_5; // @[RegisterRouter.scala:87:24] wire _out_T_65 = ~out_wimask_5; // @[RegisterRouter.scala:87:24] wire _out_T_66 = ~out_romask_5; // @[RegisterRouter.scala:87:24] wire _out_T_67 = ~out_womask_5; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_3 = {oldBytes_1_3, _out_prepend_T_3}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_68 = out_prepend_3; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_69 = _out_T_68; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_4 = _out_T_69; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_6 = out_frontMask[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_6 = out_frontMask[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_14 = out_frontMask[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_14 = out_frontMask[39:32]; // @[RegisterRouter.scala:87:24] wire out_rimask_6 = |_out_rimask_T_6; // @[RegisterRouter.scala:87:24] wire out_wimask_6 = &_out_wimask_T_6; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_6 = out_backMask[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_6 = out_backMask[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_14 = out_backMask[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_14 = out_backMask[39:32]; // @[RegisterRouter.scala:87:24] wire out_romask_6 = |_out_romask_T_6; // @[RegisterRouter.scala:87:24] wire out_womask_6 = &_out_womask_T_6; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_6 = out_rivalid_6 & out_rimask_6; // @[RegisterRouter.scala:87:24] wire _out_T_71 = out_f_rivalid_6; // @[RegisterRouter.scala:87:24] wire out_f_roready_6 = out_roready_6 & out_romask_6; // @[RegisterRouter.scala:87:24] wire _out_T_72 = out_f_roready_6; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_6 = out_wivalid_6 & out_wimask_6; // @[RegisterRouter.scala:87:24] wire _out_T_73 = out_f_wivalid_6; // @[RegisterRouter.scala:87:24] assign out_f_woready_6 = out_woready_6 & out_womask_6; // @[RegisterRouter.scala:87:24] assign valids_1_4 = out_f_woready_6; // @[RegisterRouter.scala:87:24] wire _out_T_74 = out_f_woready_6; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_70 = out_front_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_158 = out_front_bits_data[39:32]; // @[RegisterRouter.scala:87:24] assign newBytes_1_4 = out_f_woready_6 ? _out_T_70 : oldBytes_1_4; // @[RegisterRouter.scala:87:24] wire _out_T_75 = ~out_rimask_6; // @[RegisterRouter.scala:87:24] wire _out_T_76 = ~out_wimask_6; // @[RegisterRouter.scala:87:24] wire _out_T_77 = ~out_romask_6; // @[RegisterRouter.scala:87:24] wire _out_T_78 = ~out_womask_6; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_4 = {oldBytes_1_4, _out_prepend_T_4}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_79 = out_prepend_4; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_80 = _out_T_79; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_5 = _out_T_80; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_7 = out_frontMask[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_7 = out_frontMask[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_15 = out_frontMask[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_15 = out_frontMask[47:40]; // @[RegisterRouter.scala:87:24] wire out_rimask_7 = |_out_rimask_T_7; // @[RegisterRouter.scala:87:24] wire out_wimask_7 = &_out_wimask_T_7; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_7 = out_backMask[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_7 = out_backMask[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_15 = out_backMask[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_15 = out_backMask[47:40]; // @[RegisterRouter.scala:87:24] wire out_romask_7 = |_out_romask_T_7; // @[RegisterRouter.scala:87:24] wire out_womask_7 = &_out_womask_T_7; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_7 = out_rivalid_7 & out_rimask_7; // @[RegisterRouter.scala:87:24] wire _out_T_82 = out_f_rivalid_7; // @[RegisterRouter.scala:87:24] wire out_f_roready_7 = out_roready_7 & out_romask_7; // @[RegisterRouter.scala:87:24] wire _out_T_83 = out_f_roready_7; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_7 = out_wivalid_7 & out_wimask_7; // @[RegisterRouter.scala:87:24] wire _out_T_84 = out_f_wivalid_7; // @[RegisterRouter.scala:87:24] assign out_f_woready_7 = out_woready_7 & out_womask_7; // @[RegisterRouter.scala:87:24] assign valids_1_5 = out_f_woready_7; // @[RegisterRouter.scala:87:24] wire _out_T_85 = out_f_woready_7; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_81 = out_front_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_169 = out_front_bits_data[47:40]; // @[RegisterRouter.scala:87:24] assign newBytes_1_5 = out_f_woready_7 ? _out_T_81 : oldBytes_1_5; // @[RegisterRouter.scala:87:24] wire _out_T_86 = ~out_rimask_7; // @[RegisterRouter.scala:87:24] wire _out_T_87 = ~out_wimask_7; // @[RegisterRouter.scala:87:24] wire _out_T_88 = ~out_romask_7; // @[RegisterRouter.scala:87:24] wire _out_T_89 = ~out_womask_7; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_5 = {oldBytes_1_5, _out_prepend_T_5}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_90 = out_prepend_5; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_91 = _out_T_90; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_6 = _out_T_91; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_8 = out_frontMask[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_8 = out_frontMask[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_16 = out_frontMask[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_16 = out_frontMask[55:48]; // @[RegisterRouter.scala:87:24] wire out_rimask_8 = |_out_rimask_T_8; // @[RegisterRouter.scala:87:24] wire out_wimask_8 = &_out_wimask_T_8; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_8 = out_backMask[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_8 = out_backMask[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_16 = out_backMask[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_16 = out_backMask[55:48]; // @[RegisterRouter.scala:87:24] wire out_romask_8 = |_out_romask_T_8; // @[RegisterRouter.scala:87:24] wire out_womask_8 = &_out_womask_T_8; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_8 = out_rivalid_8 & out_rimask_8; // @[RegisterRouter.scala:87:24] wire _out_T_93 = out_f_rivalid_8; // @[RegisterRouter.scala:87:24] wire out_f_roready_8 = out_roready_8 & out_romask_8; // @[RegisterRouter.scala:87:24] wire _out_T_94 = out_f_roready_8; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_8 = out_wivalid_8 & out_wimask_8; // @[RegisterRouter.scala:87:24] wire _out_T_95 = out_f_wivalid_8; // @[RegisterRouter.scala:87:24] assign out_f_woready_8 = out_woready_8 & out_womask_8; // @[RegisterRouter.scala:87:24] assign valids_1_6 = out_f_woready_8; // @[RegisterRouter.scala:87:24] wire _out_T_96 = out_f_woready_8; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_92 = out_front_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_180 = out_front_bits_data[55:48]; // @[RegisterRouter.scala:87:24] assign newBytes_1_6 = out_f_woready_8 ? _out_T_92 : oldBytes_1_6; // @[RegisterRouter.scala:87:24] wire _out_T_97 = ~out_rimask_8; // @[RegisterRouter.scala:87:24] wire _out_T_98 = ~out_wimask_8; // @[RegisterRouter.scala:87:24] wire _out_T_99 = ~out_romask_8; // @[RegisterRouter.scala:87:24] wire _out_T_100 = ~out_womask_8; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_6 = {oldBytes_1_6, _out_prepend_T_6}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_101 = out_prepend_6; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_102 = _out_T_101; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_7 = _out_T_102; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_9 = out_frontMask[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_9 = out_frontMask[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_17 = out_frontMask[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_17 = out_frontMask[63:56]; // @[RegisterRouter.scala:87:24] wire out_rimask_9 = |_out_rimask_T_9; // @[RegisterRouter.scala:87:24] wire out_wimask_9 = &_out_wimask_T_9; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_9 = out_backMask[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_9 = out_backMask[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_17 = out_backMask[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_17 = out_backMask[63:56]; // @[RegisterRouter.scala:87:24] wire out_romask_9 = |_out_romask_T_9; // @[RegisterRouter.scala:87:24] wire out_womask_9 = &_out_womask_T_9; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_9 = out_rivalid_9 & out_rimask_9; // @[RegisterRouter.scala:87:24] wire _out_T_104 = out_f_rivalid_9; // @[RegisterRouter.scala:87:24] wire out_f_roready_9 = out_roready_9 & out_romask_9; // @[RegisterRouter.scala:87:24] wire _out_T_105 = out_f_roready_9; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_9 = out_wivalid_9 & out_wimask_9; // @[RegisterRouter.scala:87:24] wire _out_T_106 = out_f_wivalid_9; // @[RegisterRouter.scala:87:24] assign out_f_woready_9 = out_woready_9 & out_womask_9; // @[RegisterRouter.scala:87:24] assign valids_1_7 = out_f_woready_9; // @[RegisterRouter.scala:87:24] wire _out_T_107 = out_f_woready_9; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_103 = out_front_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_191 = out_front_bits_data[63:56]; // @[RegisterRouter.scala:87:24] assign newBytes_1_7 = out_f_woready_9 ? _out_T_103 : oldBytes_1_7; // @[RegisterRouter.scala:87:24] wire _out_T_108 = ~out_rimask_9; // @[RegisterRouter.scala:87:24] wire _out_T_109 = ~out_wimask_9; // @[RegisterRouter.scala:87:24] wire _out_T_110 = ~out_romask_9; // @[RegisterRouter.scala:87:24] wire _out_T_111 = ~out_womask_9; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_7 = {oldBytes_1_7, _out_prepend_T_7}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_112 = out_prepend_7; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_113 = _out_T_112; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_1_2 = _out_T_113; // @[MuxLiteral.scala:49:48] wire out_rimask_10 = |_out_rimask_T_10; // @[RegisterRouter.scala:87:24] wire out_wimask_10 = &_out_wimask_T_10; // @[RegisterRouter.scala:87:24] wire out_romask_10 = |_out_romask_T_10; // @[RegisterRouter.scala:87:24] wire out_womask_10 = &_out_womask_T_10; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_10 = out_rivalid_10 & out_rimask_10; // @[RegisterRouter.scala:87:24] wire _out_T_115 = out_f_rivalid_10; // @[RegisterRouter.scala:87:24] wire out_f_roready_10 = out_roready_10 & out_romask_10; // @[RegisterRouter.scala:87:24] wire _out_T_116 = out_f_roready_10; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_10 = out_wivalid_10 & out_wimask_10; // @[RegisterRouter.scala:87:24] wire _out_T_117 = out_f_wivalid_10; // @[RegisterRouter.scala:87:24] assign out_f_woready_10 = out_woready_10 & out_womask_10; // @[RegisterRouter.scala:87:24] assign valids_0 = out_f_woready_10; // @[RegisterRouter.scala:87:24] wire _out_T_118 = out_f_woready_10; // @[RegisterRouter.scala:87:24] assign newBytes_0 = out_f_woready_10 ? _out_T_114 : oldBytes_0; // @[RegisterRouter.scala:87:24] wire _out_T_119 = ~out_rimask_10; // @[RegisterRouter.scala:87:24] wire _out_T_120 = ~out_wimask_10; // @[RegisterRouter.scala:87:24] wire _out_T_121 = ~out_romask_10; // @[RegisterRouter.scala:87:24] wire _out_T_122 = ~out_womask_10; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_124 = _out_T_123; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_8 = _out_T_124; // @[RegisterRouter.scala:87:24] wire out_rimask_11 = |_out_rimask_T_11; // @[RegisterRouter.scala:87:24] wire out_wimask_11 = &_out_wimask_T_11; // @[RegisterRouter.scala:87:24] wire out_romask_11 = |_out_romask_T_11; // @[RegisterRouter.scala:87:24] wire out_womask_11 = &_out_womask_T_11; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_11 = out_rivalid_11 & out_rimask_11; // @[RegisterRouter.scala:87:24] wire _out_T_126 = out_f_rivalid_11; // @[RegisterRouter.scala:87:24] wire out_f_roready_11 = out_roready_11 & out_romask_11; // @[RegisterRouter.scala:87:24] wire _out_T_127 = out_f_roready_11; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_11 = out_wivalid_11 & out_wimask_11; // @[RegisterRouter.scala:87:24] wire _out_T_128 = out_f_wivalid_11; // @[RegisterRouter.scala:87:24] assign out_f_woready_11 = out_woready_11 & out_womask_11; // @[RegisterRouter.scala:87:24] assign valids_1 = out_f_woready_11; // @[RegisterRouter.scala:87:24] wire _out_T_129 = out_f_woready_11; // @[RegisterRouter.scala:87:24] assign newBytes_1 = out_f_woready_11 ? _out_T_125 : oldBytes_1; // @[RegisterRouter.scala:87:24] wire _out_T_130 = ~out_rimask_11; // @[RegisterRouter.scala:87:24] wire _out_T_131 = ~out_wimask_11; // @[RegisterRouter.scala:87:24] wire _out_T_132 = ~out_romask_11; // @[RegisterRouter.scala:87:24] wire _out_T_133 = ~out_womask_11; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_8 = {oldBytes_1, _out_prepend_T_8}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_134 = out_prepend_8; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_135 = _out_T_134; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_9 = _out_T_135; // @[RegisterRouter.scala:87:24] wire out_rimask_12 = |_out_rimask_T_12; // @[RegisterRouter.scala:87:24] wire out_wimask_12 = &_out_wimask_T_12; // @[RegisterRouter.scala:87:24] wire out_romask_12 = |_out_romask_T_12; // @[RegisterRouter.scala:87:24] wire out_womask_12 = &_out_womask_T_12; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_12 = out_rivalid_12 & out_rimask_12; // @[RegisterRouter.scala:87:24] wire _out_T_137 = out_f_rivalid_12; // @[RegisterRouter.scala:87:24] wire out_f_roready_12 = out_roready_12 & out_romask_12; // @[RegisterRouter.scala:87:24] wire _out_T_138 = out_f_roready_12; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_12 = out_wivalid_12 & out_wimask_12; // @[RegisterRouter.scala:87:24] wire _out_T_139 = out_f_wivalid_12; // @[RegisterRouter.scala:87:24] assign out_f_woready_12 = out_woready_12 & out_womask_12; // @[RegisterRouter.scala:87:24] assign valids_2 = out_f_woready_12; // @[RegisterRouter.scala:87:24] wire _out_T_140 = out_f_woready_12; // @[RegisterRouter.scala:87:24] assign newBytes_2 = out_f_woready_12 ? _out_T_136 : oldBytes_2; // @[RegisterRouter.scala:87:24] wire _out_T_141 = ~out_rimask_12; // @[RegisterRouter.scala:87:24] wire _out_T_142 = ~out_wimask_12; // @[RegisterRouter.scala:87:24] wire _out_T_143 = ~out_romask_12; // @[RegisterRouter.scala:87:24] wire _out_T_144 = ~out_womask_12; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_9 = {oldBytes_2, _out_prepend_T_9}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_145 = out_prepend_9; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_146 = _out_T_145; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_10 = _out_T_146; // @[RegisterRouter.scala:87:24] wire out_rimask_13 = |_out_rimask_T_13; // @[RegisterRouter.scala:87:24] wire out_wimask_13 = &_out_wimask_T_13; // @[RegisterRouter.scala:87:24] wire out_romask_13 = |_out_romask_T_13; // @[RegisterRouter.scala:87:24] wire out_womask_13 = &_out_womask_T_13; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_13 = out_rivalid_13 & out_rimask_13; // @[RegisterRouter.scala:87:24] wire _out_T_148 = out_f_rivalid_13; // @[RegisterRouter.scala:87:24] wire out_f_roready_13 = out_roready_13 & out_romask_13; // @[RegisterRouter.scala:87:24] wire _out_T_149 = out_f_roready_13; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_13 = out_wivalid_13 & out_wimask_13; // @[RegisterRouter.scala:87:24] wire _out_T_150 = out_f_wivalid_13; // @[RegisterRouter.scala:87:24] assign out_f_woready_13 = out_woready_13 & out_womask_13; // @[RegisterRouter.scala:87:24] assign valids_3 = out_f_woready_13; // @[RegisterRouter.scala:87:24] wire _out_T_151 = out_f_woready_13; // @[RegisterRouter.scala:87:24] assign newBytes_3 = out_f_woready_13 ? _out_T_147 : oldBytes_3; // @[RegisterRouter.scala:87:24] wire _out_T_152 = ~out_rimask_13; // @[RegisterRouter.scala:87:24] wire _out_T_153 = ~out_wimask_13; // @[RegisterRouter.scala:87:24] wire _out_T_154 = ~out_romask_13; // @[RegisterRouter.scala:87:24] wire _out_T_155 = ~out_womask_13; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_10 = {oldBytes_3, _out_prepend_T_10}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_156 = out_prepend_10; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_157 = _out_T_156; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_11 = _out_T_157; // @[RegisterRouter.scala:87:24] wire out_rimask_14 = |_out_rimask_T_14; // @[RegisterRouter.scala:87:24] wire out_wimask_14 = &_out_wimask_T_14; // @[RegisterRouter.scala:87:24] wire out_romask_14 = |_out_romask_T_14; // @[RegisterRouter.scala:87:24] wire out_womask_14 = &_out_womask_T_14; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_14 = out_rivalid_14 & out_rimask_14; // @[RegisterRouter.scala:87:24] wire _out_T_159 = out_f_rivalid_14; // @[RegisterRouter.scala:87:24] wire out_f_roready_14 = out_roready_14 & out_romask_14; // @[RegisterRouter.scala:87:24] wire _out_T_160 = out_f_roready_14; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_14 = out_wivalid_14 & out_wimask_14; // @[RegisterRouter.scala:87:24] wire _out_T_161 = out_f_wivalid_14; // @[RegisterRouter.scala:87:24] assign out_f_woready_14 = out_woready_14 & out_womask_14; // @[RegisterRouter.scala:87:24] assign valids_4 = out_f_woready_14; // @[RegisterRouter.scala:87:24] wire _out_T_162 = out_f_woready_14; // @[RegisterRouter.scala:87:24] assign newBytes_4 = out_f_woready_14 ? _out_T_158 : oldBytes_4; // @[RegisterRouter.scala:87:24] wire _out_T_163 = ~out_rimask_14; // @[RegisterRouter.scala:87:24] wire _out_T_164 = ~out_wimask_14; // @[RegisterRouter.scala:87:24] wire _out_T_165 = ~out_romask_14; // @[RegisterRouter.scala:87:24] wire _out_T_166 = ~out_womask_14; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_11 = {oldBytes_4, _out_prepend_T_11}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_167 = out_prepend_11; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_168 = _out_T_167; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_12 = _out_T_168; // @[RegisterRouter.scala:87:24] wire out_rimask_15 = |_out_rimask_T_15; // @[RegisterRouter.scala:87:24] wire out_wimask_15 = &_out_wimask_T_15; // @[RegisterRouter.scala:87:24] wire out_romask_15 = |_out_romask_T_15; // @[RegisterRouter.scala:87:24] wire out_womask_15 = &_out_womask_T_15; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_15 = out_rivalid_15 & out_rimask_15; // @[RegisterRouter.scala:87:24] wire _out_T_170 = out_f_rivalid_15; // @[RegisterRouter.scala:87:24] wire out_f_roready_15 = out_roready_15 & out_romask_15; // @[RegisterRouter.scala:87:24] wire _out_T_171 = out_f_roready_15; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_15 = out_wivalid_15 & out_wimask_15; // @[RegisterRouter.scala:87:24] wire _out_T_172 = out_f_wivalid_15; // @[RegisterRouter.scala:87:24] assign out_f_woready_15 = out_woready_15 & out_womask_15; // @[RegisterRouter.scala:87:24] assign valids_5 = out_f_woready_15; // @[RegisterRouter.scala:87:24] wire _out_T_173 = out_f_woready_15; // @[RegisterRouter.scala:87:24] assign newBytes_5 = out_f_woready_15 ? _out_T_169 : oldBytes_5; // @[RegisterRouter.scala:87:24] wire _out_T_174 = ~out_rimask_15; // @[RegisterRouter.scala:87:24] wire _out_T_175 = ~out_wimask_15; // @[RegisterRouter.scala:87:24] wire _out_T_176 = ~out_romask_15; // @[RegisterRouter.scala:87:24] wire _out_T_177 = ~out_womask_15; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_12 = {oldBytes_5, _out_prepend_T_12}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_178 = out_prepend_12; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_179 = _out_T_178; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_13 = _out_T_179; // @[RegisterRouter.scala:87:24] wire out_rimask_16 = |_out_rimask_T_16; // @[RegisterRouter.scala:87:24] wire out_wimask_16 = &_out_wimask_T_16; // @[RegisterRouter.scala:87:24] wire out_romask_16 = |_out_romask_T_16; // @[RegisterRouter.scala:87:24] wire out_womask_16 = &_out_womask_T_16; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_16 = out_rivalid_16 & out_rimask_16; // @[RegisterRouter.scala:87:24] wire _out_T_181 = out_f_rivalid_16; // @[RegisterRouter.scala:87:24] wire out_f_roready_16 = out_roready_16 & out_romask_16; // @[RegisterRouter.scala:87:24] wire _out_T_182 = out_f_roready_16; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_16 = out_wivalid_16 & out_wimask_16; // @[RegisterRouter.scala:87:24] wire _out_T_183 = out_f_wivalid_16; // @[RegisterRouter.scala:87:24] assign out_f_woready_16 = out_woready_16 & out_womask_16; // @[RegisterRouter.scala:87:24] assign valids_6 = out_f_woready_16; // @[RegisterRouter.scala:87:24] wire _out_T_184 = out_f_woready_16; // @[RegisterRouter.scala:87:24] assign newBytes_6 = out_f_woready_16 ? _out_T_180 : oldBytes_6; // @[RegisterRouter.scala:87:24] wire _out_T_185 = ~out_rimask_16; // @[RegisterRouter.scala:87:24] wire _out_T_186 = ~out_wimask_16; // @[RegisterRouter.scala:87:24] wire _out_T_187 = ~out_romask_16; // @[RegisterRouter.scala:87:24] wire _out_T_188 = ~out_womask_16; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_13 = {oldBytes_6, _out_prepend_T_13}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_189 = out_prepend_13; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_190 = _out_T_189; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_14 = _out_T_190; // @[RegisterRouter.scala:87:24] wire out_rimask_17 = |_out_rimask_T_17; // @[RegisterRouter.scala:87:24] wire out_wimask_17 = &_out_wimask_T_17; // @[RegisterRouter.scala:87:24] wire out_romask_17 = |_out_romask_T_17; // @[RegisterRouter.scala:87:24] wire out_womask_17 = &_out_womask_T_17; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_17 = out_rivalid_17 & out_rimask_17; // @[RegisterRouter.scala:87:24] wire _out_T_192 = out_f_rivalid_17; // @[RegisterRouter.scala:87:24] wire out_f_roready_17 = out_roready_17 & out_romask_17; // @[RegisterRouter.scala:87:24] wire _out_T_193 = out_f_roready_17; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_17 = out_wivalid_17 & out_wimask_17; // @[RegisterRouter.scala:87:24] wire _out_T_194 = out_f_wivalid_17; // @[RegisterRouter.scala:87:24] assign out_f_woready_17 = out_woready_17 & out_womask_17; // @[RegisterRouter.scala:87:24] assign valids_7 = out_f_woready_17; // @[RegisterRouter.scala:87:24] wire _out_T_195 = out_f_woready_17; // @[RegisterRouter.scala:87:24] assign newBytes_7 = out_f_woready_17 ? _out_T_191 : oldBytes_7; // @[RegisterRouter.scala:87:24] wire _out_T_196 = ~out_rimask_17; // @[RegisterRouter.scala:87:24] wire _out_T_197 = ~out_wimask_17; // @[RegisterRouter.scala:87:24] wire _out_T_198 = ~out_romask_17; // @[RegisterRouter.scala:87:24] wire _out_T_199 = ~out_womask_17; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_14 = {oldBytes_7, _out_prepend_T_14}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_200 = out_prepend_14; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_201 = _out_T_200; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_1_1 = _out_T_201; // @[MuxLiteral.scala:49:48] wire _out_iindex_T = out_front_bits_index[0]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T = out_front_bits_index[0]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_1 = out_front_bits_index[1]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_1 = out_front_bits_index[1]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_2 = out_front_bits_index[2]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_2 = out_front_bits_index[2]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_3 = out_front_bits_index[3]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_3 = out_front_bits_index[3]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_4 = out_front_bits_index[4]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_4 = out_front_bits_index[4]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_5 = out_front_bits_index[5]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_5 = out_front_bits_index[5]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_6 = out_front_bits_index[6]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_6 = out_front_bits_index[6]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_7 = out_front_bits_index[7]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_7 = out_front_bits_index[7]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_8 = out_front_bits_index[8]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_8 = out_front_bits_index[8]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_9 = out_front_bits_index[9]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_9 = out_front_bits_index[9]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_10 = out_front_bits_index[10]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_10 = out_front_bits_index[10]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_11 = out_front_bits_index[11]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_11 = out_front_bits_index[11]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_12 = out_front_bits_index[12]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_12 = out_front_bits_index[12]; // @[RegisterRouter.scala:87:24] wire [1:0] out_iindex = {_out_iindex_T_12, _out_iindex_T_11}; // @[RegisterRouter.scala:87:24] wire [1:0] out_oindex = {_out_oindex_T_12, _out_oindex_T_11}; // @[RegisterRouter.scala:87:24] wire [3:0] _out_frontSel_T = 4'h1 << out_iindex; // @[OneHot.scala:58:35] wire out_frontSel_0 = _out_frontSel_T[0]; // @[OneHot.scala:58:35] wire out_frontSel_1 = _out_frontSel_T[1]; // @[OneHot.scala:58:35] wire out_frontSel_2 = _out_frontSel_T[2]; // @[OneHot.scala:58:35] wire out_frontSel_3 = _out_frontSel_T[3]; // @[OneHot.scala:58:35] wire [3:0] _out_backSel_T = 4'h1 << out_oindex; // @[OneHot.scala:58:35] wire out_backSel_0 = _out_backSel_T[0]; // @[OneHot.scala:58:35] wire out_backSel_1 = _out_backSel_T[1]; // @[OneHot.scala:58:35] wire out_backSel_2 = _out_backSel_T[2]; // @[OneHot.scala:58:35] wire out_backSel_3 = _out_backSel_T[3]; // @[OneHot.scala:58:35] wire _GEN_2 = in_valid & out_front_ready; // @[RegisterRouter.scala:73:18, :87:24] wire _out_rifireMux_T; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T = _GEN_2; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T = _GEN_2; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1 = _out_rifireMux_T & out_front_bits_read; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_2 = _out_rifireMux_T_1 & out_frontSel_0; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_3 = _out_rifireMux_T_2 & _out_T; // @[RegisterRouter.scala:87:24] assign out_rivalid_0 = _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24] assign out_rivalid_1 = _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_4 = ~_out_T; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_6 = _out_rifireMux_T_1 & out_frontSel_1; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_7 = _out_rifireMux_T_6 & _out_T_4; // @[RegisterRouter.scala:87:24] assign out_rivalid_10 = _out_rifireMux_T_7; // @[RegisterRouter.scala:87:24] assign out_rivalid_11 = _out_rifireMux_T_7; // @[RegisterRouter.scala:87:24] assign out_rivalid_12 = _out_rifireMux_T_7; // @[RegisterRouter.scala:87:24] assign out_rivalid_13 = _out_rifireMux_T_7; // @[RegisterRouter.scala:87:24] assign out_rivalid_14 = _out_rifireMux_T_7; // @[RegisterRouter.scala:87:24] assign out_rivalid_15 = _out_rifireMux_T_7; // @[RegisterRouter.scala:87:24] assign out_rivalid_16 = _out_rifireMux_T_7; // @[RegisterRouter.scala:87:24] assign out_rivalid_17 = _out_rifireMux_T_7; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_8 = ~_out_T_4; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_10 = _out_rifireMux_T_1 & out_frontSel_2; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_11 = _out_rifireMux_T_10 & _out_T_2; // @[RegisterRouter.scala:87:24] assign out_rivalid_2 = _out_rifireMux_T_11; // @[RegisterRouter.scala:87:24] assign out_rivalid_3 = _out_rifireMux_T_11; // @[RegisterRouter.scala:87:24] assign out_rivalid_4 = _out_rifireMux_T_11; // @[RegisterRouter.scala:87:24] assign out_rivalid_5 = _out_rifireMux_T_11; // @[RegisterRouter.scala:87:24] assign out_rivalid_6 = _out_rifireMux_T_11; // @[RegisterRouter.scala:87:24] assign out_rivalid_7 = _out_rifireMux_T_11; // @[RegisterRouter.scala:87:24] assign out_rivalid_8 = _out_rifireMux_T_11; // @[RegisterRouter.scala:87:24] assign out_rivalid_9 = _out_rifireMux_T_11; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_12 = ~_out_T_2; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_14 = _out_rifireMux_T_1 & out_frontSel_3; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_15 = _out_rifireMux_T_14; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1 = ~out_front_bits_read; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_2 = _out_wifireMux_T & _out_wifireMux_T_1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_3 = _out_wifireMux_T_2 & out_frontSel_0; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_4 = _out_wifireMux_T_3 & _out_T; // @[RegisterRouter.scala:87:24] assign out_wivalid_0 = _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24] assign out_wivalid_1 = _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_5 = ~_out_T; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_7 = _out_wifireMux_T_2 & out_frontSel_1; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_8 = _out_wifireMux_T_7 & _out_T_4; // @[RegisterRouter.scala:87:24] assign out_wivalid_10 = _out_wifireMux_T_8; // @[RegisterRouter.scala:87:24] assign out_wivalid_11 = _out_wifireMux_T_8; // @[RegisterRouter.scala:87:24] assign out_wivalid_12 = _out_wifireMux_T_8; // @[RegisterRouter.scala:87:24] assign out_wivalid_13 = _out_wifireMux_T_8; // @[RegisterRouter.scala:87:24] assign out_wivalid_14 = _out_wifireMux_T_8; // @[RegisterRouter.scala:87:24] assign out_wivalid_15 = _out_wifireMux_T_8; // @[RegisterRouter.scala:87:24] assign out_wivalid_16 = _out_wifireMux_T_8; // @[RegisterRouter.scala:87:24] assign out_wivalid_17 = _out_wifireMux_T_8; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_9 = ~_out_T_4; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_11 = _out_wifireMux_T_2 & out_frontSel_2; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_12 = _out_wifireMux_T_11 & _out_T_2; // @[RegisterRouter.scala:87:24] assign out_wivalid_2 = _out_wifireMux_T_12; // @[RegisterRouter.scala:87:24] assign out_wivalid_3 = _out_wifireMux_T_12; // @[RegisterRouter.scala:87:24] assign out_wivalid_4 = _out_wifireMux_T_12; // @[RegisterRouter.scala:87:24] assign out_wivalid_5 = _out_wifireMux_T_12; // @[RegisterRouter.scala:87:24] assign out_wivalid_6 = _out_wifireMux_T_12; // @[RegisterRouter.scala:87:24] assign out_wivalid_7 = _out_wifireMux_T_12; // @[RegisterRouter.scala:87:24] assign out_wivalid_8 = _out_wifireMux_T_12; // @[RegisterRouter.scala:87:24] assign out_wivalid_9 = _out_wifireMux_T_12; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_13 = ~_out_T_2; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_15 = _out_wifireMux_T_2 & out_frontSel_3; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_16 = _out_wifireMux_T_15; // @[RegisterRouter.scala:87:24] wire _GEN_3 = out_front_valid & out_ready; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T = _GEN_3; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T = _GEN_3; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1 = _out_rofireMux_T & out_front_bits_read; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_2 = _out_rofireMux_T_1 & out_backSel_0; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_3 = _out_rofireMux_T_2 & _out_T_1; // @[RegisterRouter.scala:87:24] assign out_roready_0 = _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24] assign out_roready_1 = _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_4 = ~_out_T_1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_6 = _out_rofireMux_T_1 & out_backSel_1; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_7 = _out_rofireMux_T_6 & _out_T_5; // @[RegisterRouter.scala:87:24] assign out_roready_10 = _out_rofireMux_T_7; // @[RegisterRouter.scala:87:24] assign out_roready_11 = _out_rofireMux_T_7; // @[RegisterRouter.scala:87:24] assign out_roready_12 = _out_rofireMux_T_7; // @[RegisterRouter.scala:87:24] assign out_roready_13 = _out_rofireMux_T_7; // @[RegisterRouter.scala:87:24] assign out_roready_14 = _out_rofireMux_T_7; // @[RegisterRouter.scala:87:24] assign out_roready_15 = _out_rofireMux_T_7; // @[RegisterRouter.scala:87:24] assign out_roready_16 = _out_rofireMux_T_7; // @[RegisterRouter.scala:87:24] assign out_roready_17 = _out_rofireMux_T_7; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_8 = ~_out_T_5; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_10 = _out_rofireMux_T_1 & out_backSel_2; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_11 = _out_rofireMux_T_10 & _out_T_3; // @[RegisterRouter.scala:87:24] assign out_roready_2 = _out_rofireMux_T_11; // @[RegisterRouter.scala:87:24] assign out_roready_3 = _out_rofireMux_T_11; // @[RegisterRouter.scala:87:24] assign out_roready_4 = _out_rofireMux_T_11; // @[RegisterRouter.scala:87:24] assign out_roready_5 = _out_rofireMux_T_11; // @[RegisterRouter.scala:87:24] assign out_roready_6 = _out_rofireMux_T_11; // @[RegisterRouter.scala:87:24] assign out_roready_7 = _out_rofireMux_T_11; // @[RegisterRouter.scala:87:24] assign out_roready_8 = _out_rofireMux_T_11; // @[RegisterRouter.scala:87:24] assign out_roready_9 = _out_rofireMux_T_11; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_12 = ~_out_T_3; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_14 = _out_rofireMux_T_1 & out_backSel_3; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_15 = _out_rofireMux_T_14; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1 = ~out_front_bits_read; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_2 = _out_wofireMux_T & _out_wofireMux_T_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_3 = _out_wofireMux_T_2 & out_backSel_0; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_4 = _out_wofireMux_T_3 & _out_T_1; // @[RegisterRouter.scala:87:24] assign out_woready_0 = _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24] assign out_woready_1 = _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_5 = ~_out_T_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_7 = _out_wofireMux_T_2 & out_backSel_1; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_8 = _out_wofireMux_T_7 & _out_T_5; // @[RegisterRouter.scala:87:24] assign out_woready_10 = _out_wofireMux_T_8; // @[RegisterRouter.scala:87:24] assign out_woready_11 = _out_wofireMux_T_8; // @[RegisterRouter.scala:87:24] assign out_woready_12 = _out_wofireMux_T_8; // @[RegisterRouter.scala:87:24] assign out_woready_13 = _out_wofireMux_T_8; // @[RegisterRouter.scala:87:24] assign out_woready_14 = _out_wofireMux_T_8; // @[RegisterRouter.scala:87:24] assign out_woready_15 = _out_wofireMux_T_8; // @[RegisterRouter.scala:87:24] assign out_woready_16 = _out_wofireMux_T_8; // @[RegisterRouter.scala:87:24] assign out_woready_17 = _out_wofireMux_T_8; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_9 = ~_out_T_5; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_11 = _out_wofireMux_T_2 & out_backSel_2; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_12 = _out_wofireMux_T_11 & _out_T_3; // @[RegisterRouter.scala:87:24] assign out_woready_2 = _out_wofireMux_T_12; // @[RegisterRouter.scala:87:24] assign out_woready_3 = _out_wofireMux_T_12; // @[RegisterRouter.scala:87:24] assign out_woready_4 = _out_wofireMux_T_12; // @[RegisterRouter.scala:87:24] assign out_woready_5 = _out_wofireMux_T_12; // @[RegisterRouter.scala:87:24] assign out_woready_6 = _out_wofireMux_T_12; // @[RegisterRouter.scala:87:24] assign out_woready_7 = _out_wofireMux_T_12; // @[RegisterRouter.scala:87:24] assign out_woready_8 = _out_wofireMux_T_12; // @[RegisterRouter.scala:87:24] assign out_woready_9 = _out_wofireMux_T_12; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_13 = ~_out_T_3; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_15 = _out_wofireMux_T_2 & out_backSel_3; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_16 = _out_wofireMux_T_15; // @[RegisterRouter.scala:87:24] assign in_ready = _out_in_ready_T; // @[RegisterRouter.scala:73:18, :87:24] assign out_front_valid = _out_front_valid_T; // @[RegisterRouter.scala:87:24] assign out_front_ready = _out_front_ready_T; // @[RegisterRouter.scala:87:24] assign out_valid = _out_out_valid_T; // @[RegisterRouter.scala:87:24] wire [3:0] _GEN_4 = {{1'h1}, {_out_out_bits_data_WIRE_2}, {_out_out_bits_data_WIRE_1}, {_out_out_bits_data_WIRE_0}}; // @[MuxLiteral.scala:49:{10,48}] wire _out_out_bits_data_T_1 = _GEN_4[out_oindex]; // @[MuxLiteral.scala:49:10] wire [63:0] _out_out_bits_data_WIRE_1_0 = {32'h0, _out_T_25}; // @[MuxLiteral.scala:49:48] wire [3:0][63:0] _GEN_5 = {{64'h0}, {_out_out_bits_data_WIRE_1_2}, {_out_out_bits_data_WIRE_1_1}, {_out_out_bits_data_WIRE_1_0}}; // @[MuxLiteral.scala:49:{10,48}] wire [63:0] _out_out_bits_data_T_3 = _GEN_5[out_oindex]; // @[MuxLiteral.scala:49:10] assign _out_out_bits_data_T_4 = _out_out_bits_data_T_1 ? _out_out_bits_data_T_3 : 64'h0; // @[MuxLiteral.scala:49:10] assign out_bits_data = _out_out_bits_data_T_4; // @[RegisterRouter.scala:87:24] assign nodeIn_d_bits_size = nodeIn_d_bits_d_size; // @[Edges.scala:792:17] assign nodeIn_d_bits_source = nodeIn_d_bits_d_source; // @[Edges.scala:792:17] assign nodeIn_d_bits_opcode = {2'h0, _nodeIn_d_bits_opcode_T}; // @[RegisterRouter.scala:105:{19,25}] always @(posedge clock) begin // @[CLINT.scala:65:9] if (reset) begin // @[CLINT.scala:65:9] time_0 <= 64'h0; // @[CLINT.scala:73:23] ipi_0 <= 1'h0; // @[CLINT.scala:78:41] end else begin // @[CLINT.scala:65:9] if (valids_1_0 | valids_1_1 | valids_1_2 | valids_1_3 | valids_1_4 | valids_1_5 | valids_1_6 | valids_1_7) // @[RegField.scala:153:29, :154:27] time_0 <= _time_T_2; // @[RegField.scala:154:52] else if (io_rtcTick_0) // @[CLINT.scala:65:9] time_0 <= _time_T_1; // @[CLINT.scala:73:23, :74:38] if (out_f_woready) // @[RegisterRouter.scala:87:24] ipi_0 <= _out_T_6; // @[RegisterRouter.scala:87:24] end if (valids_0 | valids_1 | valids_2 | valids_3 | valids_4 | valids_5 | valids_6 | valids_7) // @[RegField.scala:153:29, :154:27] timecmp_0 <= _timecmp_0_T; // @[RegField.scala:154:52] always @(posedge) TLMonitor_42 monitor ( // @[Nodes.scala:27:25] .clock (clock), .reset (reset), .io_in_a_ready (nodeIn_a_ready), // @[MixedNode.scala:551:17] .io_in_a_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17] .io_in_a_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17] .io_in_a_bits_param (nodeIn_a_bits_param), // @[MixedNode.scala:551:17] .io_in_a_bits_size (nodeIn_a_bits_size), // @[MixedNode.scala:551:17] .io_in_a_bits_source (nodeIn_a_bits_source), // @[MixedNode.scala:551:17] .io_in_a_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17] .io_in_a_bits_mask (nodeIn_a_bits_mask), // @[MixedNode.scala:551:17] .io_in_a_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17] .io_in_a_bits_corrupt (nodeIn_a_bits_corrupt), // @[MixedNode.scala:551:17] .io_in_d_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17] .io_in_d_valid (nodeIn_d_valid), // @[MixedNode.scala:551:17] .io_in_d_bits_opcode (nodeIn_d_bits_opcode), // @[MixedNode.scala:551:17] .io_in_d_bits_size (nodeIn_d_bits_size), // @[MixedNode.scala:551:17] .io_in_d_bits_source (nodeIn_d_bits_source), // @[MixedNode.scala:551:17] .io_in_d_bits_data (nodeIn_d_bits_data) // @[MixedNode.scala:551:17] ); // @[Nodes.scala:27:25] assign auto_int_out_0 = auto_int_out_0_0; // @[CLINT.scala:65:9] assign auto_int_out_1 = auto_int_out_1_0; // @[CLINT.scala:65:9] assign auto_in_a_ready = auto_in_a_ready_0; // @[CLINT.scala:65:9] assign auto_in_d_valid = auto_in_d_valid_0; // @[CLINT.scala:65:9] assign auto_in_d_bits_opcode = auto_in_d_bits_opcode_0; // @[CLINT.scala:65:9] assign auto_in_d_bits_size = auto_in_d_bits_size_0; // @[CLINT.scala:65:9] assign auto_in_d_bits_source = auto_in_d_bits_source_0; // @[CLINT.scala:65:9] assign auto_in_d_bits_data = auto_in_d_bits_data_0; // @[CLINT.scala:65:9] endmodule

Generate the Verilog code corresponding to the following Chisel files. File Monitor.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceLine import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import freechips.rocketchip.diplomacy.EnableMonitors import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode} import freechips.rocketchip.util.PlusArg case class TLMonitorArgs(edge: TLEdge) abstract class TLMonitorBase(args: TLMonitorArgs) extends Module { val io = IO(new Bundle { val in = Input(new TLBundle(args.edge.bundle)) }) def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit legalize(io.in, args.edge, reset) } object TLMonitor { def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = { if (enable) { EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) } } else { node } } } class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args) { require (args.edge.params(TLMonitorStrictMode) || (! args.edge.params(TestplanTestType).formal)) val cover_prop_class = PropertyClass.Default //Like assert but can flip to being an assumption for formal verification def monAssert(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir, cond, message, PropertyClass.Default) } def assume(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir.flip, cond, message, PropertyClass.Default) } def extra = { args.edge.sourceInfo match { case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)" case _ => "" } } def visible(address: UInt, source: UInt, edge: TLEdge) = edge.client.clients.map { c => !c.sourceId.contains(source) || c.visibility.map(_.contains(address)).reduce(_ || _) }.reduce(_ && _) def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = { //switch this flag to turn on diplomacy in error messages def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n" monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra) // Reuse these subexpressions to save some firrtl lines val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility") //The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B //TODO: check for acquireT? when (bundle.opcode === TLMessages.AcquireBlock) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra) } when (bundle.opcode === TLMessages.AcquirePerm) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra) monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra) monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra) monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra) } } def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = { monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra) monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility") // Reuse these subexpressions to save some firrtl lines val address_ok = edge.manager.containsSafe(edge.address(bundle)) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source when (bundle.opcode === TLMessages.Probe) { assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra) assume (address_ok, "'B' channel Probe carries unmanaged address" + extra) assume (legal_source, "'B' channel Probe carries source that is not first source" + extra) assume (is_aligned, "'B' channel Probe address not aligned to size" + extra) assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra) assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra) assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra) monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra) monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra) monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra) monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra) } } def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = { monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val address_ok = edge.manager.containsSafe(edge.address(bundle)) monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility") when (bundle.opcode === TLMessages.ProbeAck) { monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra) } when (bundle.opcode === TLMessages.ProbeAckData) { monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.Release) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra) monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra) } when (bundle.opcode === TLMessages.ReleaseData) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.AccessAck) { monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra) } when (bundle.opcode === TLMessages.HintAck) { monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra) } } def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = { assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val sink_ok = bundle.sink < edge.manager.endSinkId.U val deny_put_ok = edge.manager.mayDenyPut.B val deny_get_ok = edge.manager.mayDenyGet.B when (bundle.opcode === TLMessages.ReleaseAck) { assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra) assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra) assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra) } when (bundle.opcode === TLMessages.Grant) { assume (source_ok, "'D' channel Grant carries invalid source ID" + extra) assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra) assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel Grant is denied" + extra) } when (bundle.opcode === TLMessages.GrantData) { assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra) assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra) assume (!bundle.denied || bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra) assume (deny_get_ok || !bundle.denied, "'D' channel GrantData is denied" + extra) } when (bundle.opcode === TLMessages.AccessAck) { assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel AccessAck is denied" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra) assume (!bundle.denied || bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra) assume (deny_get_ok || !bundle.denied, "'D' channel AccessAckData is denied" + extra) } when (bundle.opcode === TLMessages.HintAck) { assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel HintAck is denied" + extra) } } def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = { val sink_ok = bundle.sink < edge.manager.endSinkId.U monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra) } def legalizeFormat(bundle: TLBundle, edge: TLEdge) = { when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) } when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) } when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) } when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) } } else { monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra) monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra) monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra) } } def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = { val a_first = edge.first(a.bits, a.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (a.valid && !a_first) { monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra) monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra) monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra) monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra) monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra) } when (a.fire && a_first) { opcode := a.bits.opcode param := a.bits.param size := a.bits.size source := a.bits.source address := a.bits.address } } def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = { val b_first = edge.first(b.bits, b.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (b.valid && !b_first) { monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra) monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra) monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra) monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra) monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra) } when (b.fire && b_first) { opcode := b.bits.opcode param := b.bits.param size := b.bits.size source := b.bits.source address := b.bits.address } } def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = { // Symbolic variable val sym_source = Wire(UInt(edge.client.endSourceId.W)) // TODO: Connect sym_source to a fixed value for simulation and to a // free wire in formal sym_source := 0.U // Type casting Int to UInt val maxSourceId = Wire(UInt(edge.client.endSourceId.W)) maxSourceId := edge.client.endSourceId.U // Delayed verison of sym_source val sym_source_d = Reg(UInt(edge.client.endSourceId.W)) sym_source_d := sym_source // These will be constraints for FV setup Property( MonitorDirection.Monitor, (sym_source === sym_source_d), "sym_source should remain stable", PropertyClass.Default) Property( MonitorDirection.Monitor, (sym_source <= maxSourceId), "sym_source should take legal value", PropertyClass.Default) val my_resp_pend = RegInit(false.B) val my_opcode = Reg(UInt()) val my_size = Reg(UInt()) val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire) val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire) val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source) val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source) val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat) val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend) when (my_set_resp_pend) { my_resp_pend := true.B } .elsewhen (my_clr_resp_pend) { my_resp_pend := false.B } when (my_a_first_beat) { my_opcode := bundle.a.bits.opcode my_size := bundle.a.bits.size } val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size) val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode) val my_resp_opcode_legal = Wire(Bool()) when ((my_resp_opcode === TLMessages.Get) || (my_resp_opcode === TLMessages.ArithmeticData) || (my_resp_opcode === TLMessages.LogicalData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData) } .elsewhen ((my_resp_opcode === TLMessages.PutFullData) || (my_resp_opcode === TLMessages.PutPartialData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck) } .otherwise { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck) } monAssert (IfThen(my_resp_pend, !my_a_first_beat), "Request message should not be sent with a source ID, for which a response message" + "is already pending (not received until current cycle) for a prior request message" + "with the same source ID" + extra) assume (IfThen(my_clr_resp_pend, (my_set_resp_pend || my_resp_pend)), "Response message should be accepted with a source ID only if a request message with the" + "same source ID has been accepted or is being accepted in the current cycle" + extra) assume (IfThen(my_d_first_beat, (my_a_first_beat || my_resp_pend)), "Response message should be sent with a source ID only if a request message with the" + "same source ID has been accepted or is being sent in the current cycle" + extra) assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)), "If d_valid is 1, then d_size should be same as a_size of the corresponding request" + "message" + extra) assume (IfThen(my_d_first_beat, my_resp_opcode_legal), "If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" + "request message" + extra) } def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = { val c_first = edge.first(c.bits, c.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (c.valid && !c_first) { monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra) monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra) monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra) monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra) monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra) } when (c.fire && c_first) { opcode := c.bits.opcode param := c.bits.param size := c.bits.size source := c.bits.source address := c.bits.address } } def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = { val d_first = edge.first(d.bits, d.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val sink = Reg(UInt()) val denied = Reg(Bool()) when (d.valid && !d_first) { assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra) assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra) assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra) assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra) assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra) assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra) } when (d.fire && d_first) { opcode := d.bits.opcode param := d.bits.param size := d.bits.size source := d.bits.source sink := d.bits.sink denied := d.bits.denied } } def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = { legalizeMultibeatA(bundle.a, edge) legalizeMultibeatD(bundle.d, edge) if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { legalizeMultibeatB(bundle.b, edge) legalizeMultibeatC(bundle.c, edge) } } //This is left in for almond which doesn't adhere to the tilelink protocol @deprecated("Use legalizeADSource instead if possible","") def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.client.endSourceId.W)) val a_first = edge.first(bundle.a.bits, bundle.a.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val a_set = WireInit(0.U(edge.client.endSourceId.W)) when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) assume((a_set | inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra) } if (edge.manager.minLatency > 0) { assume(a_set =/= d_clr || !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight | a_set) & ~d_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") assert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = { val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size) val log_a_size_bus_size = log2Ceil(a_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error inflight.suggestName("inflight") val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) inflight_opcodes.suggestName("inflight_opcodes") val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) inflight_sizes.suggestName("inflight_sizes") val a_first = edge.first(bundle.a.bits, bundle.a.fire) a_first.suggestName("a_first") val d_first = edge.first(bundle.d.bits, bundle.d.fire) d_first.suggestName("d_first") val a_set = WireInit(0.U(edge.client.endSourceId.W)) val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) a_set.suggestName("a_set") a_set_wo_ready.suggestName("a_set_wo_ready") val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) a_opcodes_set.suggestName("a_opcodes_set") val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) a_sizes_set.suggestName("a_sizes_set") val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W)) a_opcode_lookup.suggestName("a_opcode_lookup") a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W)) a_size_lookup.suggestName("a_size_lookup") a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant)) val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant)) val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W)) a_opcodes_set_interm.suggestName("a_opcodes_set_interm") val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W)) a_sizes_set_interm.suggestName("a_sizes_set_interm") when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) { a_set_wo_ready := UIntToOH(bundle.a.bits.source) } when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) | 1.U a_sizes_set_interm := (bundle.a.bits.size << 1.U) | 1.U a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U) a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U) monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) d_opcodes_clr.suggestName("d_opcodes_clr") val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) || (bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra) assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) || (bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra) assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) { assume((!bundle.d.ready) || bundle.a.ready, "ready check") } if (edge.manager.minLatency > 0) { assume(a_set_wo_ready =/= d_clr_wo_ready || !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight | a_set) & ~d_clr inflight_opcodes := (inflight_opcodes | a_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes | a_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = { val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size) val log_c_size_bus_size = log2Ceil(c_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) inflight.suggestName("inflight") inflight_opcodes.suggestName("inflight_opcodes") inflight_sizes.suggestName("inflight_sizes") val c_first = edge.first(bundle.c.bits, bundle.c.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) c_first.suggestName("c_first") d_first.suggestName("d_first") val c_set = WireInit(0.U(edge.client.endSourceId.W)) val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) c_set.suggestName("c_set") c_set_wo_ready.suggestName("c_set_wo_ready") c_opcodes_set.suggestName("c_opcodes_set") c_sizes_set.suggestName("c_sizes_set") val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W)) val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W)) c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U c_opcode_lookup.suggestName("c_opcode_lookup") c_size_lookup.suggestName("c_size_lookup") val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W)) val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W)) c_opcodes_set_interm.suggestName("c_opcodes_set_interm") c_sizes_set_interm.suggestName("c_sizes_set_interm") when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) { c_set_wo_ready := UIntToOH(bundle.c.bits.source) } when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) { c_set := UIntToOH(bundle.c.bits.source) c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) | 1.U c_sizes_set_interm := (bundle.c.bits.size << 1.U) | 1.U c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U) c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U) monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra) } val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck || bundle.c.bits.opcode === TLMessages.ProbeAckData val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") d_opcodes_clr.suggestName("d_opcodes_clr") d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) { assume((!bundle.d.ready) || bundle.c.ready, "ready check") } if (edge.manager.minLatency > 0) { when (c_set_wo_ready.orR) { assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra) } } inflight := (inflight | c_set) & ~d_clr inflight_opcodes := (inflight_opcodes | c_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes | c_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.c.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.manager.endSinkId.W)) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val e_first = true.B val d_set = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) { d_set := UIntToOH(bundle.d.bits.sink) assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra) } val e_clr = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) { e_clr := UIntToOH(bundle.e.bits.sink) monAssert((d_set | inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra) } // edge.client.minLatency applies to BC, not DE inflight := (inflight | d_set) & ~e_clr } def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = { val sourceBits = log2Ceil(edge.client.endSourceId) val tooBig = 14 // >16kB worth of flight information gets to be too much if (sourceBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked") } else { if (args.edge.params(TestplanTestType).simulation) { if (args.edge.params(TLMonitorStrictMode)) { legalizeADSource(bundle, edge) legalizeCDSource(bundle, edge) } else { legalizeADSourceOld(bundle, edge) } } if (args.edge.params(TestplanTestType).formal) { legalizeADSourceFormal(bundle, edge) } } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { // legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize... val sinkBits = log2Ceil(edge.manager.endSinkId) if (sinkBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked") } else { legalizeDESink(bundle, edge) } } } def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = { legalizeFormat (bundle, edge) legalizeMultibeat (bundle, edge) legalizeUnique (bundle, edge) } } File Misc.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import scala.math._ class ParameterizedBundle(implicit p: Parameters) extends Bundle trait Clocked extends Bundle { val clock = Clock() val reset = Bool() } object DecoupledHelper { def apply(rvs: Bool*) = new DecoupledHelper(rvs) } class DecoupledHelper(val rvs: Seq[Bool]) { def fire(exclude: Bool, includes: Bool*) = { require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!") (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _) } def fire() = { rvs.reduce(_ && _) } } object MuxT { def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2)) def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3)) def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4)) } /** Creates a cascade of n MuxTs to search for a key value. */ object MuxTLookup { def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } } object ValidMux { def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]*): ValidIO[T] = { apply(v1 +: v2.toSeq) } def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = { val out = Wire(Valid(valids.head.bits.cloneType)) out.valid := valids.map(_.valid).reduce(_ || _) out.bits := MuxCase(valids.head.bits, valids.map(v => (v.valid -> v.bits))) out } } object Str { def apply(s: String): UInt = { var i = BigInt(0) require(s.forall(validChar _)) for (c <- s) i = (i << 8) | c i.U((s.length*8).W) } def apply(x: Char): UInt = { require(validChar(x)) x.U(8.W) } def apply(x: UInt): UInt = apply(x, 10) def apply(x: UInt, radix: Int): UInt = { val rad = radix.U val w = x.getWidth require(w > 0) var q = x var s = digit(q % rad) for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s) } s } def apply(x: SInt): UInt = apply(x, 10) def apply(x: SInt, radix: Int): UInt = { val neg = x < 0.S val abs = x.abs.asUInt if (radix != 10) { Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix)) } else { val rad = radix.U val w = abs.getWidth require(w > 0) var q = abs var s = digit(q % rad) var needSign = neg for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad val placeSpace = q === 0.U val space = Mux(needSign, Str('-'), Str(' ')) needSign = needSign && !placeSpace s = Cat(Mux(placeSpace, space, digit(q % rad)), s) } Cat(Mux(needSign, Str('-'), Str(' ')), s) } } private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0) private def validChar(x: Char) = x == (x & 0xFF) } object Split { def apply(x: UInt, n0: Int) = { val w = x.getWidth (x.extract(w-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n2: Int, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } } object Random { def apply(mod: Int, random: UInt): UInt = { if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0) else PriorityEncoder(partition(apply(1 << log2Up(mod*8), random), mod)) } def apply(mod: Int): UInt = apply(mod, randomizer) def oneHot(mod: Int, random: UInt): UInt = { if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0)) else PriorityEncoderOH(partition(apply(1 << log2Up(mod*8), random), mod)).asUInt } def oneHot(mod: Int): UInt = oneHot(mod, randomizer) private def randomizer = LFSR(16) private def partition(value: UInt, slices: Int) = Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U) } object Majority { def apply(in: Set[Bool]): Bool = { val n = (in.size >> 1) + 1 val clauses = in.subsets(n).map(_.reduce(_ && _)) clauses.reduce(_ || _) } def apply(in: Seq[Bool]): Bool = apply(in.toSet) def apply(in: UInt): Bool = apply(in.asBools.toSet) } object PopCountAtLeast { private def two(x: UInt): (Bool, Bool) = x.getWidth match { case 1 => (x.asBool, false.B) case n => val half = x.getWidth / 2 val (leftOne, leftTwo) = two(x(half - 1, 0)) val (rightOne, rightTwo) = two(x(x.getWidth - 1, half)) (leftOne || rightOne, leftTwo || rightTwo || (leftOne && rightOne)) } def apply(x: UInt, n: Int): Bool = n match { case 0 => true.B case 1 => x.orR case 2 => two(x)._2 case 3 => PopCount(x) >= n.U } } // This gets used everywhere, so make the smallest circuit possible ... // Given an address and size, create a mask of beatBytes size // eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111 // groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01 object MaskGen { def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = { require (groupBy >= 1 && beatBytes >= groupBy) require (isPow2(beatBytes) && isPow2(groupBy)) val lgBytes = log2Ceil(beatBytes) val sizeOH = UIntToOH(lgSize | 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) | (groupBy*2 - 1).U def helper(i: Int): Seq[(Bool, Bool)] = { if (i == 0) { Seq((lgSize >= lgBytes.asUInt, true.B)) } else { val sub = helper(i-1) val size = sizeOH(lgBytes - i) val bit = addr_lo(lgBytes - i) val nbit = !bit Seq.tabulate (1 << i) { j => val (sub_acc, sub_eq) = sub(j/2) val eq = sub_eq && (if (j % 2 == 1) bit else nbit) val acc = sub_acc || (size && eq) (acc, eq) } } } if (groupBy == beatBytes) 1.U else Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse) } } File PlusArg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.experimental._ import chisel3.util.HasBlackBoxResource @deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05") case class PlusArgInfo(default: BigInt, docstring: String) /** Case class for PlusArg information * * @tparam A scala type of the PlusArg value * @param default optional default value * @param docstring text to include in the help * @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT) */ private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String) /** Typeclass for converting a type to a doctype string * @tparam A some type */ trait Doctypeable[A] { /** Return the doctype string for some option */ def toDoctype(a: Option[A]): String } /** Object containing implementations of the Doctypeable typeclass */ object Doctypes { /** Converts an Int => "INT" */ implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" } /** Converts a BigInt => "INT" */ implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" } /** Converts a String => "STRING" */ implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" } } class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map( "FORMAT" -> StringParam(format), "DEFAULT" -> IntParam(default), "WIDTH" -> IntParam(width) )) with HasBlackBoxResource { val io = IO(new Bundle { val out = Output(UInt(width.W)) }) addResource("/vsrc/plusarg_reader.v") } /* This wrapper class has no outputs, making it clear it is a simulation-only construct */ class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module { val io = IO(new Bundle { val count = Input(UInt(width.W)) }) val max = Module(new plusarg_reader(format, default, docstring, width)).io.out when (max > 0.U) { assert (io.count < max, s"Timeout exceeded: $docstring") } } import Doctypes._ object PlusArg { /** PlusArg("foo") will return 42.U if the simulation is run with +foo=42 * Do not use this as an initial register value. The value is set in an * initial block and thus accessing it from another initial is racey. * Add a docstring to document the arg, which can be dumped in an elaboration * pass. */ def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out } /** PlusArg.timeout(name, default, docstring)(count) will use chisel.assert * to kill the simulation when count exceeds the specified integer argument. * Default 0 will never assert. */ def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count } } object PlusArgArtefacts { private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty /* Add a new PlusArg */ @deprecated( "Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05" ) def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring) /** Add a new PlusArg * * @tparam A scala type of the PlusArg value * @param name name for the PlusArg * @param default optional default value * @param docstring text to include in the help */ def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit = artefacts = artefacts ++ Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default))) /* From plus args, generate help text */ private def serializeHelp_cHeader(tab: String = ""): String = artefacts .map{ case(arg, info) => s"""|$tab+$arg=${info.doctype}\\n\\ |$tab${" "*20}${info.docstring}\\n\\ |""".stripMargin ++ info.default.map{ case default => s"$tab${" "*22}(default=${default})\\n\\\n"}.getOrElse("") }.toSeq.mkString("\\n\\\n") ++ "\"" /* From plus args, generate a char array of their names */ private def serializeArray_cHeader(tab: String = ""): String = { val prettyTab = tab + " " * 44 // Length of 'static const ...' s"${tab}static const char * verilog_plusargs [] = {\\\n" ++ artefacts .map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" } .mkString("")++ s"${prettyTab}0};" } /* Generate C code to be included in emulator.cc that helps with * argument parsing based on available Verilog PlusArgs */ def serialize_cHeader(): String = s"""|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\ |${serializeHelp_cHeader(" "*7)} |${serializeArray_cHeader()} |""".stripMargin } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /** Like Vec.apply(idx), but tolerates indices of mismatched width */ def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /** Any Data subtype that has a Bool member named valid. */ type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /** converts from camel case to to underscores, also removing all spaces */ def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /** converts spaces or underscores to hyphens, also lowering case */ def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y | (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y || y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /** Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation */ def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.diplomacy import chisel3._ import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor} import freechips.rocketchip.util.ShiftQueue /** Options for describing the attributes of memory regions */ object RegionType { // Define the 'more relaxed than' ordering val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS) sealed trait T extends Ordered[T] { def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this) } case object CACHED extends T // an intermediate agent may have cached a copy of the region for you case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively } // A non-empty half-open range; [start, end) case class IdRange(start: Int, end: Int) extends Ordered[IdRange] { require (start >= 0, s"Ids cannot be negative, but got: $start.") require (start <= end, "Id ranges cannot be negative.") def compare(x: IdRange) = { val primary = (this.start - x.start).signum val secondary = (x.end - this.end).signum if (primary != 0) primary else secondary } def overlaps(x: IdRange) = start < x.end && x.start < end def contains(x: IdRange) = start <= x.start && x.end <= end def contains(x: Int) = start <= x && x < end def contains(x: UInt) = if (size == 0) { false.B } else if (size == 1) { // simple comparison x === start.U } else { // find index of largest different bit val largestDeltaBit = log2Floor(start ^ (end-1)) val smallestCommonBit = largestDeltaBit + 1 // may not exist in x val uncommonMask = (1 << smallestCommonBit) - 1 val uncommonBits = (x | 0.U(smallestCommonBit.W))(largestDeltaBit, 0) // the prefix must match exactly (note: may shift ALL bits away) (x >> smallestCommonBit) === (start >> smallestCommonBit).U && // firrtl constant prop range analysis can eliminate these two: (start & uncommonMask).U <= uncommonBits && uncommonBits <= ((end-1) & uncommonMask).U } def shift(x: Int) = IdRange(start+x, end+x) def size = end - start def isEmpty = end == start def range = start until end } object IdRange { def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else { val ranges = s.sorted (ranges.tail zip ranges.init) find { case (a, b) => a overlaps b } } } // An potentially empty inclusive range of 2-powers [min, max] (in bytes) case class TransferSizes(min: Int, max: Int) { def this(x: Int) = this(x, x) require (min <= max, s"Min transfer $min > max transfer $max") require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)") require (max == 0 || isPow2(max), s"TransferSizes must be a power of 2, got: $max") require (min == 0 || isPow2(min), s"TransferSizes must be a power of 2, got: $min") require (max == 0 || min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)") def none = min == 0 def contains(x: Int) = isPow2(x) && min <= x && x <= max def containsLg(x: Int) = contains(1 << x) def containsLg(x: UInt) = if (none) false.B else if (min == max) { log2Ceil(min).U === x } else { log2Ceil(min).U <= x && x <= log2Ceil(max).U } def contains(x: TransferSizes) = x.none || (min <= x.min && x.max <= max) def intersect(x: TransferSizes) = if (x.max < min || max < x.min) TransferSizes.none else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max)) // Not a union, because the result may contain sizes contained by neither term // NOT TO BE CONFUSED WITH COVERPOINTS def mincover(x: TransferSizes) = { if (none) { x } else if (x.none) { this } else { TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max)) } } override def toString() = "TransferSizes[%d, %d]".format(min, max) } object TransferSizes { def apply(x: Int) = new TransferSizes(x) val none = new TransferSizes(0) def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _) def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _) implicit def asBool(x: TransferSizes) = !x.none } // AddressSets specify the address space managed by the manager // Base is the base address, and mask are the bits consumed by the manager // e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff // e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ... case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet] { // Forbid misaligned base address (and empty sets) require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}") require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous // We do allow negative mask (=> ignore all high bits) def contains(x: BigInt) = ((x ^ base) & ~mask) == 0 def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S // turn x into an address contained in this set def legalize(x: UInt): UInt = base.U | (mask.U & x) // overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1) def overlaps(x: AddressSet) = (~(mask | x.mask) & (base ^ x.base)) == 0 // contains iff bitwise: x.mask => mask && contains(x.base) def contains(x: AddressSet) = ((x.mask | (base ^ x.base)) & ~mask) == 0 // The number of bytes to which the manager must be aligned def alignment = ((mask + 1) & ~mask) // Is this a contiguous memory range def contiguous = alignment == mask+1 def finite = mask >= 0 def max = { require (finite, "Max cannot be calculated on infinite mask"); base | mask } // Widen the match function to ignore all bits in imask def widen(imask: BigInt) = AddressSet(base & ~imask, mask | imask) // Return an AddressSet that only contains the addresses both sets contain def intersect(x: AddressSet): Option[AddressSet] = { if (!overlaps(x)) { None } else { val r_mask = mask & x.mask val r_base = base | x.base Some(AddressSet(r_base, r_mask)) } } def subtract(x: AddressSet): Seq[AddressSet] = { intersect(x) match { case None => Seq(this) case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit => val nmask = (mask & (bit-1)) | remove.mask val nbase = (remove.base ^ bit) & ~nmask AddressSet(nbase, nmask) } } } // AddressSets have one natural Ordering (the containment order, if contiguous) def compare(x: AddressSet) = { val primary = (this.base - x.base).signum // smallest address first val secondary = (x.mask - this.mask).signum // largest mask first if (primary != 0) primary else secondary } // We always want to see things in hex override def toString() = { if (mask >= 0) { "AddressSet(0x%x, 0x%x)".format(base, mask) } else { "AddressSet(0x%x, ~0x%x)".format(base, ~mask) } } def toRanges = { require (finite, "Ranges cannot be calculated on infinite mask") val size = alignment val fragments = mask & ~(size-1) val bits = bitIndexes(fragments) (BigInt(0) until (BigInt(1) << bits.size)).map { i => val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) } AddressRange(off, size) } } } object AddressSet { val everything = AddressSet(0, -1) def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = { if (size == 0) tail.reverse else { val maxBaseAlignment = base & (-base) // 0 for infinite (LSB) val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size val step = if (maxBaseAlignment == 0 || maxBaseAlignment > maxSizeAlignment) maxSizeAlignment else maxBaseAlignment misaligned(base+step, size-step, AddressSet(base, step-1) +: tail) } } def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = { // Pair terms up by ignoring 'bit' seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) => if (seq.size == 1) { seq.head // singleton -> unaffected } else { key.copy(mask = key.mask | bit) // pair - widen mask by bit } }.toList } def unify(seq: Seq[AddressSet]): Seq[AddressSet] = { val bits = seq.map(_.base).foldLeft(BigInt(0))(_ | _) AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted } def enumerateMask(mask: BigInt): Seq[BigInt] = { def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] = if (id == mask) (id +: tail).reverse else helper(((~mask | id) + 1) & mask, id +: tail) helper(0, Nil) } def enumerateBits(mask: BigInt): Seq[BigInt] = { def helper(x: BigInt): Seq[BigInt] = { if (x == 0) { Nil } else { val bit = x & (-x) bit +: helper(x & ~bit) } } helper(mask) } } case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean) { require (depth >= 0, "Buffer depth must be >= 0") def isDefined = depth > 0 def latency = if (isDefined && !flow) 1 else 0 def apply[T <: Data](x: DecoupledIO[T]) = if (isDefined) Queue(x, depth, flow=flow, pipe=pipe) else x def irrevocable[T <: Data](x: ReadyValidIO[T]) = if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe) else x def sq[T <: Data](x: DecoupledIO[T]) = if (!isDefined) x else { val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe)) sq.io.enq <> x sq.io.deq } override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "") } object BufferParams { implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false) val default = BufferParams(2) val none = BufferParams(0) val flow = BufferParams(1, true, false) val pipe = BufferParams(1, false, true) } case class TriStateValue(value: Boolean, set: Boolean) { def update(orig: Boolean) = if (set) value else orig } object TriStateValue { implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true) def unset = TriStateValue(false, false) } trait DirectedBuffers[T] { def copyIn(x: BufferParams): T def copyOut(x: BufferParams): T def copyInOut(x: BufferParams): T } trait IdMapEntry { def name: String def from: IdRange def to: IdRange def isCache: Boolean def requestFifo: Boolean def maxTransactionsInFlight: Option[Int] def pretty(fmt: String) = if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5 fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } else { fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } } abstract class IdMap[T <: IdMapEntry] { protected val fmt: String val mapping: Seq[T] def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n") } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) || !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.ProbeAckData || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode | small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U || beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }

module TLMonitor_60( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [1:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [11:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [11:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [11:0] io_in_d_bits_source // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire a_first_done = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala:51:35] reg a_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [1:0] size; // @[Monitor.scala:389:22] reg [11:0] source; // @[Monitor.scala:390:22] reg [11:0] address; // @[Monitor.scala:391:22] reg d_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] size_1; // @[Monitor.scala:540:22] reg [11:0] source_1; // @[Monitor.scala:541:22] reg [2063:0] inflight; // @[Monitor.scala:614:27] reg [8255:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [8255:0] inflight_sizes; // @[Monitor.scala:618:33] reg a_first_counter_1; // @[Edges.scala:229:27] reg d_first_counter_1; // @[Edges.scala:229:27] wire _GEN = a_first_done & ~a_first_counter_1; // @[Decoupled.scala:51:35] wire d_release_ack = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala:673:46] wire _GEN_0 = io_in_d_bits_opcode != 3'h6; // @[Monitor.scala:673:46, :674:74] reg [31:0] watchdog; // @[Monitor.scala:709:27] reg [2063:0] inflight_1; // @[Monitor.scala:726:35] reg [8255:0] inflight_sizes_1; // @[Monitor.scala:728:35] reg d_first_counter_2; // @[Edges.scala:229:27] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]

Generate the Verilog code corresponding to the following Chisel files. File FIFOFixer.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.lazymodule._ import org.chipsalliance.diplomacy.nodes._ import freechips.rocketchip.diplomacy.RegionType import freechips.rocketchip.util.property class TLFIFOFixer(policy: TLFIFOFixer.Policy = TLFIFOFixer.all)(implicit p: Parameters) extends LazyModule { private def fifoMap(seq: Seq[TLSlaveParameters]) = { val (flatManagers, keepManagers) = seq.partition(policy) // We need to be careful if one flatManager and one keepManager share an existing domain // Erring on the side of caution, we will also flatten the keepManager in this case val flatDomains = Set(flatManagers.flatMap(_.fifoId):_*) // => ID 0 val keepDomains = Set(keepManagers.flatMap(_.fifoId):_*) -- flatDomains // => IDs compacted // Calculate what the FIFO domains look like after the fixer is applied val flatMap = flatDomains.map { x => (x, 0) }.toMap val keepMap = keepDomains.scanLeft((-1,0)) { case ((_,s),x) => (x, s+1) }.toMap val map = flatMap ++ keepMap val fixMap = seq.map { m => m.fifoId match { case None => if (policy(m)) Some(0) else None case Some(id) => Some(map(id)) // also flattens some who did not ask } } // Compress the FIFO domain space of those we are combining val reMap = flatDomains.scanLeft((-1,-1)) { case ((_,s),x) => (x, s+1) }.toMap val splatMap = seq.map { m => m.fifoId match { case None => None case Some(id) => reMap.lift(id) } } (fixMap, splatMap) } val node = new AdapterNode(TLImp)( { cp => cp }, { mp => val (fixMap, _) = fifoMap(mp.managers) mp.v1copy(managers = (fixMap zip mp.managers) map { case (id, m) => m.v1copy(fifoId = id) }) }) with TLFormatNode { override def circuitIdentity = edges.in.map(_.client.clients.filter(c => c.requestFifo && c.sourceId.size > 1).size).sum == 0 } lazy val module = new Impl class Impl extends LazyModuleImp(this) { (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => val (fixMap, splatMap) = fifoMap(edgeOut.manager.managers) // Do we need to serialize the request to this manager? val a_notFIFO = edgeIn.manager.fastProperty(in.a.bits.address, _.fifoId != Some(0), (b:Boolean) => b.B) // Compact the IDs of the cases we serialize val compacted = ((fixMap zip splatMap) zip edgeOut.manager.managers) flatMap { case ((f, s), m) => if (f == Some(0)) Some(m.v1copy(fifoId = s)) else None } val sinks = if (compacted.exists(_.supportsAcquireB)) edgeOut.manager.endSinkId else 0 val a_id = if (compacted.isEmpty) 0.U else edgeOut.manager.v1copy(managers = compacted, endSinkId = sinks).findFifoIdFast(in.a.bits.address) val a_noDomain = a_id === 0.U if (false) { println(s"FIFOFixer for: ${edgeIn.client.clients.map(_.name).mkString(", ")}") println(s"make FIFO: ${edgeIn.manager.managers.filter(_.fifoId==Some(0)).map(_.name).mkString(", ")}") println(s"not FIFO: ${edgeIn.manager.managers.filter(_.fifoId!=Some(0)).map(_.name).mkString(", ")}") println(s"domains: ${compacted.groupBy(_.name).mapValues(_.map(_.fifoId))}") println("") } // Count beats val a_first = edgeIn.first(in.a) val d_first = edgeOut.first(out.d) && out.d.bits.opcode =/= TLMessages.ReleaseAck // Keep one bit for each source recording if there is an outstanding request that must be made FIFO // Sources unused in the stall signal calculation should be pruned by DCE val flight = RegInit(VecInit(Seq.fill(edgeIn.client.endSourceId) { false.B })) when (a_first && in.a.fire) { flight(in.a.bits.source) := !a_notFIFO } when (d_first && in.d.fire) { flight(in.d.bits.source) := false.B } val stalls = edgeIn.client.clients.filter(c => c.requestFifo && c.sourceId.size > 1).map { c => val a_sel = c.sourceId.contains(in.a.bits.source) val id = RegEnable(a_id, in.a.fire && a_sel && !a_notFIFO) val track = flight.slice(c.sourceId.start, c.sourceId.end) a_sel && a_first && track.reduce(_ || _) && (a_noDomain || id =/= a_id) } val stall = stalls.foldLeft(false.B)(_||_) out.a <> in.a in.d <> out.d out.a.valid := in.a.valid && (a_notFIFO || !stall) in.a.ready := out.a.ready && (a_notFIFO || !stall) if (edgeOut.manager.anySupportAcquireB && edgeOut.client.anySupportProbe) { in .b <> out.b out.c <> in .c out.e <> in .e } else { in.b.valid := false.B in.c.ready := true.B in.e.ready := true.B out.b.ready := true.B out.c.valid := false.B out.e.valid := false.B } //Functional cover properties property.cover(in.a.valid && stall, "COVER FIFOFIXER STALL", "Cover: Stall occured for a valid transaction") val SourceIdFIFOed = RegInit(0.U(edgeIn.client.endSourceId.W)) val SourceIdSet = WireDefault(0.U(edgeIn.client.endSourceId.W)) val SourceIdClear = WireDefault(0.U(edgeIn.client.endSourceId.W)) when (a_first && in.a.fire && !a_notFIFO) { SourceIdSet := UIntToOH(in.a.bits.source) } when (d_first && in.d.fire) { SourceIdClear := UIntToOH(in.d.bits.source) } SourceIdFIFOed := SourceIdFIFOed | SourceIdSet val allIDs_FIFOed = SourceIdFIFOed===Fill(SourceIdFIFOed.getWidth, 1.U) property.cover(allIDs_FIFOed, "COVER all sources", "Cover: FIFOFIXER covers all Source IDs") //property.cover(flight.reduce(_ && _), "COVER full", "Cover: FIFO is full with all Source IDs") property.cover(!(flight.reduce(_ || _)), "COVER empty", "Cover: FIFO is empty") property.cover(SourceIdSet > 0.U, "COVER at least one push", "Cover: At least one Source ID is pushed") property.cover(SourceIdClear > 0.U, "COVER at least one pop", "Cover: At least one Source ID is popped") } } } object TLFIFOFixer { // Which slaves should have their FIFOness combined? // NOTE: this transformation is still only applied for masters with requestFifo type Policy = TLSlaveParameters => Boolean import RegionType._ val all: Policy = m => true val allFIFO: Policy = m => m.fifoId.isDefined val allVolatile: Policy = m => m.regionType <= VOLATILE def apply(policy: Policy = all)(implicit p: Parameters): TLNode = { val fixer = LazyModule(new TLFIFOFixer(policy)) fixer.node } } File Buffer.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.diplomacy.BufferParams class TLBufferNode ( a: BufferParams, b: BufferParams, c: BufferParams, d: BufferParams, e: BufferParams)(implicit valName: ValName) extends TLAdapterNode( clientFn = { p => p.v1copy(minLatency = p.minLatency + b.latency + c.latency) }, managerFn = { p => p.v1copy(minLatency = p.minLatency + a.latency + d.latency) } ) { override lazy val nodedebugstring = s"a:${a.toString}, b:${b.toString}, c:${c.toString}, d:${d.toString}, e:${e.toString}" override def circuitIdentity = List(a,b,c,d,e).forall(_ == BufferParams.none) } class TLBuffer( a: BufferParams, b: BufferParams, c: BufferParams, d: BufferParams, e: BufferParams)(implicit p: Parameters) extends LazyModule { def this(ace: BufferParams, bd: BufferParams)(implicit p: Parameters) = this(ace, bd, ace, bd, ace) def this(abcde: BufferParams)(implicit p: Parameters) = this(abcde, abcde) def this()(implicit p: Parameters) = this(BufferParams.default) val node = new TLBufferNode(a, b, c, d, e) lazy val module = new Impl class Impl extends LazyModuleImp(this) { def headBundle = node.out.head._2.bundle override def desiredName = (Seq("TLBuffer") ++ node.out.headOption.map(_._2.bundle.shortName)).mkString("_") (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out.a <> a(in .a) in .d <> d(out.d) if (edgeOut.manager.anySupportAcquireB && edgeOut.client.anySupportProbe) { in .b <> b(out.b) out.c <> c(in .c) out.e <> e(in .e) } else { in.b.valid := false.B in.c.ready := true.B in.e.ready := true.B out.b.ready := true.B out.c.valid := false.B out.e.valid := false.B } } } } object TLBuffer { def apply() (implicit p: Parameters): TLNode = apply(BufferParams.default) def apply(abcde: BufferParams) (implicit p: Parameters): TLNode = apply(abcde, abcde) def apply(ace: BufferParams, bd: BufferParams)(implicit p: Parameters): TLNode = apply(ace, bd, ace, bd, ace) def apply( a: BufferParams, b: BufferParams, c: BufferParams, d: BufferParams, e: BufferParams)(implicit p: Parameters): TLNode = { val buffer = LazyModule(new TLBuffer(a, b, c, d, e)) buffer.node } def chain(depth: Int, name: Option[String] = None)(implicit p: Parameters): Seq[TLNode] = { val buffers = Seq.fill(depth) { LazyModule(new TLBuffer()) } name.foreach { n => buffers.zipWithIndex.foreach { case (b, i) => b.suggestName(s"${n}_${i}") } } buffers.map(_.node) } def chainNode(depth: Int, name: Option[String] = None)(implicit p: Parameters): TLNode = { chain(depth, name) .reduceLeftOption(_ :*=* _) .getOrElse(TLNameNode("no_buffer")) } } File Misc.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import scala.math._ class ParameterizedBundle(implicit p: Parameters) extends Bundle trait Clocked extends Bundle { val clock = Clock() val reset = Bool() } object DecoupledHelper { def apply(rvs: Bool*) = new DecoupledHelper(rvs) } class DecoupledHelper(val rvs: Seq[Bool]) { def fire(exclude: Bool, includes: Bool*) = { require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!") (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _) } def fire() = { rvs.reduce(_ && _) } } object MuxT { def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2)) def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3)) def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4)) } /** Creates a cascade of n MuxTs to search for a key value. */ object MuxTLookup { def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } } object ValidMux { def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]*): ValidIO[T] = { apply(v1 +: v2.toSeq) } def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = { val out = Wire(Valid(valids.head.bits.cloneType)) out.valid := valids.map(_.valid).reduce(_ || _) out.bits := MuxCase(valids.head.bits, valids.map(v => (v.valid -> v.bits))) out } } object Str { def apply(s: String): UInt = { var i = BigInt(0) require(s.forall(validChar _)) for (c <- s) i = (i << 8) | c i.U((s.length*8).W) } def apply(x: Char): UInt = { require(validChar(x)) x.U(8.W) } def apply(x: UInt): UInt = apply(x, 10) def apply(x: UInt, radix: Int): UInt = { val rad = radix.U val w = x.getWidth require(w > 0) var q = x var s = digit(q % rad) for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s) } s } def apply(x: SInt): UInt = apply(x, 10) def apply(x: SInt, radix: Int): UInt = { val neg = x < 0.S val abs = x.abs.asUInt if (radix != 10) { Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix)) } else { val rad = radix.U val w = abs.getWidth require(w > 0) var q = abs var s = digit(q % rad) var needSign = neg for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad val placeSpace = q === 0.U val space = Mux(needSign, Str('-'), Str(' ')) needSign = needSign && !placeSpace s = Cat(Mux(placeSpace, space, digit(q % rad)), s) } Cat(Mux(needSign, Str('-'), Str(' ')), s) } } private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0) private def validChar(x: Char) = x == (x & 0xFF) } object Split { def apply(x: UInt, n0: Int) = { val w = x.getWidth (x.extract(w-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n2: Int, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } } object Random { def apply(mod: Int, random: UInt): UInt = { if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0) else PriorityEncoder(partition(apply(1 << log2Up(mod*8), random), mod)) } def apply(mod: Int): UInt = apply(mod, randomizer) def oneHot(mod: Int, random: UInt): UInt = { if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0)) else PriorityEncoderOH(partition(apply(1 << log2Up(mod*8), random), mod)).asUInt } def oneHot(mod: Int): UInt = oneHot(mod, randomizer) private def randomizer = LFSR(16) private def partition(value: UInt, slices: Int) = Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U) } object Majority { def apply(in: Set[Bool]): Bool = { val n = (in.size >> 1) + 1 val clauses = in.subsets(n).map(_.reduce(_ && _)) clauses.reduce(_ || _) } def apply(in: Seq[Bool]): Bool = apply(in.toSet) def apply(in: UInt): Bool = apply(in.asBools.toSet) } object PopCountAtLeast { private def two(x: UInt): (Bool, Bool) = x.getWidth match { case 1 => (x.asBool, false.B) case n => val half = x.getWidth / 2 val (leftOne, leftTwo) = two(x(half - 1, 0)) val (rightOne, rightTwo) = two(x(x.getWidth - 1, half)) (leftOne || rightOne, leftTwo || rightTwo || (leftOne && rightOne)) } def apply(x: UInt, n: Int): Bool = n match { case 0 => true.B case 1 => x.orR case 2 => two(x)._2 case 3 => PopCount(x) >= n.U } } // This gets used everywhere, so make the smallest circuit possible ... // Given an address and size, create a mask of beatBytes size // eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111 // groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01 object MaskGen { def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = { require (groupBy >= 1 && beatBytes >= groupBy) require (isPow2(beatBytes) && isPow2(groupBy)) val lgBytes = log2Ceil(beatBytes) val sizeOH = UIntToOH(lgSize | 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) | (groupBy*2 - 1).U def helper(i: Int): Seq[(Bool, Bool)] = { if (i == 0) { Seq((lgSize >= lgBytes.asUInt, true.B)) } else { val sub = helper(i-1) val size = sizeOH(lgBytes - i) val bit = addr_lo(lgBytes - i) val nbit = !bit Seq.tabulate (1 << i) { j => val (sub_acc, sub_eq) = sub(j/2) val eq = sub_eq && (if (j % 2 == 1) bit else nbit) val acc = sub_acc || (size && eq) (acc, eq) } } } if (groupBy == beatBytes) 1.U else Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse) } } File AtomicAutomata.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.diplomacy.{AddressSet, TransferSizes} import freechips.rocketchip.util.leftOR import scala.math.{min,max} // Ensures that all downstream RW managers support Atomic operations. // If !passthrough, intercept all Atomics. Otherwise, only intercept those unsupported downstream. class TLAtomicAutomata(logical: Boolean = true, arithmetic: Boolean = true, concurrency: Int = 1, passthrough: Boolean = true)(implicit p: Parameters) extends LazyModule { require (concurrency >= 1) val node = TLAdapterNode( managerFn = { case mp => mp.v1copy(managers = mp.managers.map { m => val ourSupport = TransferSizes(1, mp.beatBytes) def widen(x: TransferSizes) = if (passthrough && x.min <= 2*mp.beatBytes) TransferSizes(1, max(mp.beatBytes, x.max)) else ourSupport val canDoit = m.supportsPutFull.contains(ourSupport) && m.supportsGet.contains(ourSupport) // Blow up if there are devices to which we cannot add Atomics, because their R|W are too inflexible require (!m.supportsPutFull || !m.supportsGet || canDoit, s"${m.name} has $ourSupport, needed PutFull(${m.supportsPutFull}) or Get(${m.supportsGet})") m.v1copy( supportsArithmetic = if (!arithmetic || !canDoit) m.supportsArithmetic else widen(m.supportsArithmetic), supportsLogical = if (!logical || !canDoit) m.supportsLogical else widen(m.supportsLogical), mayDenyGet = m.mayDenyGet || m.mayDenyPut) })}) lazy val module = new Impl class Impl extends LazyModuleImp(this) { (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => val managers = edgeOut.manager.managers val beatBytes = edgeOut.manager.beatBytes // To which managers are we adding atomic support? val ourSupport = TransferSizes(1, beatBytes) val managersNeedingHelp = managers.filter { m => m.supportsPutFull.contains(ourSupport) && m.supportsGet.contains(ourSupport) && ((logical && !m.supportsLogical .contains(ourSupport)) || (arithmetic && !m.supportsArithmetic.contains(ourSupport)) || !passthrough) // we will do atomics for everyone we can } // Managers that need help with atomics must necessarily have this node as the root of a tree in the node graph. // (But they must also ensure no sideband operations can get between the read and write.) val violations = managersNeedingHelp.flatMap(_.findTreeViolation()).map { node => (node.name, node.inputs.map(_._1.name)) } require(violations.isEmpty, s"AtomicAutomata can only help nodes for which it is at the root of a diplomatic node tree," + "but the following violations were found:\n" + violations.map(v => s"(${v._1} has parents ${v._2})").mkString("\n")) // We cannot add atomics to a non-FIFO manager managersNeedingHelp foreach { m => require (m.fifoId.isDefined) } // We need to preserve FIFO semantics across FIFO domains, not managers // Suppose you have Put(42) Atomic(+1) both inflight; valid results: 42 or 43 // If we allow Put(42) Get() Put(+1) concurrent; valid results: 42 43 OR undef // Making non-FIFO work requires waiting for all Acks to come back (=> use FIFOFixer) val domainsNeedingHelp = managersNeedingHelp.map(_.fifoId.get).distinct // Don't overprovision the CAM val camSize = min(domainsNeedingHelp.size, concurrency) // Compact the fifoIds to only those we care about def camFifoId(m: TLSlaveParameters) = m.fifoId.map(id => max(0, domainsNeedingHelp.indexOf(id))).getOrElse(0) // CAM entry state machine val FREE = 0.U // unused waiting on Atomic from A val GET = 3.U // Get sent down A waiting on AccessDataAck from D val AMO = 2.U // AccessDataAck sent up D waiting for A availability val ACK = 1.U // Put sent down A waiting for PutAck from D val params = TLAtomicAutomata.CAMParams(out.a.bits.params, domainsNeedingHelp.size) // Do we need to do anything at all? if (camSize > 0) { val initval = Wire(new TLAtomicAutomata.CAM_S(params)) initval.state := FREE val cam_s = RegInit(VecInit.fill(camSize)(initval)) val cam_a = Reg(Vec(camSize, new TLAtomicAutomata.CAM_A(params))) val cam_d = Reg(Vec(camSize, new TLAtomicAutomata.CAM_D(params))) val cam_free = cam_s.map(_.state === FREE) val cam_amo = cam_s.map(_.state === AMO) val cam_abusy = cam_s.map(e => e.state === GET || e.state === AMO) // A is blocked val cam_dmatch = cam_s.map(e => e.state =/= FREE) // D should inspect these entries // Can the manager already handle this message? val a_address = edgeIn.address(in.a.bits) val a_size = edgeIn.size(in.a.bits) val a_canLogical = passthrough.B && edgeOut.manager.supportsLogicalFast (a_address, a_size) val a_canArithmetic = passthrough.B && edgeOut.manager.supportsArithmeticFast(a_address, a_size) val a_isLogical = in.a.bits.opcode === TLMessages.LogicalData val a_isArithmetic = in.a.bits.opcode === TLMessages.ArithmeticData val a_isSupported = Mux(a_isLogical, a_canLogical, Mux(a_isArithmetic, a_canArithmetic, true.B)) // Must we do a Put? val a_cam_any_put = cam_amo.reduce(_ || _) val a_cam_por_put = cam_amo.scanLeft(false.B)(_||_).init val a_cam_sel_put = (cam_amo zip a_cam_por_put) map { case (a, b) => a && !b } val a_cam_a = PriorityMux(cam_amo, cam_a) val a_cam_d = PriorityMux(cam_amo, cam_d) val a_a = a_cam_a.bits.data val a_d = a_cam_d.data // Does the A request conflict with an inflight AMO? val a_fifoId = edgeOut.manager.fastProperty(a_address, camFifoId _, (i:Int) => i.U) val a_cam_busy = (cam_abusy zip cam_a.map(_.fifoId === a_fifoId)) map { case (a,b) => a&&b } reduce (_||_) // (Where) are we are allocating in the CAM? val a_cam_any_free = cam_free.reduce(_ || _) val a_cam_por_free = cam_free.scanLeft(false.B)(_||_).init val a_cam_sel_free = (cam_free zip a_cam_por_free) map { case (a,b) => a && !b } // Logical AMO val indexes = Seq.tabulate(beatBytes*8) { i => Cat(a_a(i,i), a_d(i,i)) } val logic_out = Cat(indexes.map(x => a_cam_a.lut(x).asUInt).reverse) // Arithmetic AMO val unsigned = a_cam_a.bits.param(1) val take_max = a_cam_a.bits.param(0) val adder = a_cam_a.bits.param(2) val mask = a_cam_a.bits.mask val signSel = ~(~mask | (mask >> 1)) val signbits_a = Cat(Seq.tabulate(beatBytes) { i => a_a(8*i+7,8*i+7) } .reverse) val signbits_d = Cat(Seq.tabulate(beatBytes) { i => a_d(8*i+7,8*i+7) } .reverse) // Move the selected sign bit into the first byte position it will extend val signbit_a = ((signbits_a & signSel) << 1)(beatBytes-1, 0) val signbit_d = ((signbits_d & signSel) << 1)(beatBytes-1, 0) val signext_a = FillInterleaved(8, leftOR(signbit_a)) val signext_d = FillInterleaved(8, leftOR(signbit_d)) // NOTE: sign-extension does not change the relative ordering in EITHER unsigned or signed arithmetic val wide_mask = FillInterleaved(8, mask) val a_a_ext = (a_a & wide_mask) | signext_a val a_d_ext = (a_d & wide_mask) | signext_d val a_d_inv = Mux(adder, a_d_ext, ~a_d_ext) val adder_out = a_a_ext + a_d_inv val h = 8*beatBytes-1 // now sign-extended; use biggest bit val a_bigger_uneq = unsigned === a_a_ext(h) // result if high bits are unequal val a_bigger = Mux(a_a_ext(h) === a_d_ext(h), !adder_out(h), a_bigger_uneq) val pick_a = take_max === a_bigger val arith_out = Mux(adder, adder_out, Mux(pick_a, a_a, a_d)) // AMO result data val amo_data = if (!logical) arith_out else if (!arithmetic) logic_out else Mux(a_cam_a.bits.opcode(0), logic_out, arith_out) // Potentially mutate the message from inner val source_i = Wire(chiselTypeOf(in.a)) val a_allow = !a_cam_busy && (a_isSupported || a_cam_any_free) in.a.ready := source_i.ready && a_allow source_i.valid := in.a.valid && a_allow source_i.bits := in.a.bits when (!a_isSupported) { // minimal mux difference source_i.bits.opcode := TLMessages.Get source_i.bits.param := 0.U } // Potentially take the message from the CAM val source_c = Wire(chiselTypeOf(in.a)) source_c.valid := a_cam_any_put source_c.bits := edgeOut.Put( fromSource = a_cam_a.bits.source, toAddress = edgeIn.address(a_cam_a.bits), lgSize = a_cam_a.bits.size, data = amo_data, corrupt = a_cam_a.bits.corrupt || a_cam_d.corrupt)._2 source_c.bits.user :<= a_cam_a.bits.user source_c.bits.echo :<= a_cam_a.bits.echo // Finishing an AMO from the CAM has highest priority TLArbiter(TLArbiter.lowestIndexFirst)(out.a, (0.U, source_c), (edgeOut.numBeats1(in.a.bits), source_i)) // Capture the A state into the CAM when (source_i.fire && !a_isSupported) { (a_cam_sel_free zip cam_a) foreach { case (en, r) => when (en) { r.fifoId := a_fifoId r.bits := in.a.bits r.lut := MuxLookup(in.a.bits.param(1, 0), 0.U(4.W))(Array( TLAtomics.AND -> 0x8.U, TLAtomics.OR -> 0xe.U, TLAtomics.XOR -> 0x6.U, TLAtomics.SWAP -> 0xc.U)) } } (a_cam_sel_free zip cam_s) foreach { case (en, r) => when (en) { r.state := GET } } } // Advance the put state when (source_c.fire) { (a_cam_sel_put zip cam_s) foreach { case (en, r) => when (en) { r.state := ACK } } } // We need to deal with a potential D response in the same cycle as the A request val d_first = edgeOut.first(out.d) val d_cam_sel_raw = cam_a.map(_.bits.source === in.d.bits.source) val d_cam_sel_match = (d_cam_sel_raw zip cam_dmatch) map { case (a,b) => a&&b } val d_cam_data = Mux1H(d_cam_sel_match, cam_d.map(_.data)) val d_cam_denied = Mux1H(d_cam_sel_match, cam_d.map(_.denied)) val d_cam_corrupt = Mux1H(d_cam_sel_match, cam_d.map(_.corrupt)) val d_cam_sel_bypass = if (edgeOut.manager.minLatency > 0) false.B else out.d.bits.source === in.a.bits.source && in.a.valid && !a_isSupported val d_cam_sel = (a_cam_sel_free zip d_cam_sel_match) map { case (a,d) => Mux(d_cam_sel_bypass, a, d) } val d_cam_sel_any = d_cam_sel_bypass || d_cam_sel_match.reduce(_ || _) val d_ackd = out.d.bits.opcode === TLMessages.AccessAckData val d_ack = out.d.bits.opcode === TLMessages.AccessAck when (out.d.fire && d_first) { (d_cam_sel zip cam_d) foreach { case (en, r) => when (en && d_ackd) { r.data := out.d.bits.data r.denied := out.d.bits.denied r.corrupt := out.d.bits.corrupt } } (d_cam_sel zip cam_s) foreach { case (en, r) => when (en) { // Note: it is important that this comes AFTER the := GET, so we can go FREE=>GET=>AMO in one cycle r.state := Mux(d_ackd, AMO, FREE) } } } val d_drop = d_first && d_ackd && d_cam_sel_any val d_replace = d_first && d_ack && d_cam_sel_match.reduce(_ || _) in.d.valid := out.d.valid && !d_drop out.d.ready := in.d.ready || d_drop in.d.bits := out.d.bits when (d_replace) { // minimal muxes in.d.bits.opcode := TLMessages.AccessAckData in.d.bits.data := d_cam_data in.d.bits.corrupt := d_cam_corrupt || out.d.bits.denied in.d.bits.denied := d_cam_denied || out.d.bits.denied } } else { out.a.valid := in.a.valid in.a.ready := out.a.ready out.a.bits := in.a.bits in.d.valid := out.d.valid out.d.ready := in.d.ready in.d.bits := out.d.bits } if (edgeOut.manager.anySupportAcquireB && edgeIn.client.anySupportProbe) { in.b.valid := out.b.valid out.b.ready := in.b.ready in.b.bits := out.b.bits out.c.valid := in.c.valid in.c.ready := out.c.ready out.c.bits := in.c.bits out.e.valid := in.e.valid in.e.ready := out.e.ready out.e.bits := in.e.bits } else { in.b.valid := false.B in.c.ready := true.B in.e.ready := true.B out.b.ready := true.B out.c.valid := false.B out.e.valid := false.B } } } } object TLAtomicAutomata { def apply(logical: Boolean = true, arithmetic: Boolean = true, concurrency: Int = 1, passthrough: Boolean = true, nameSuffix: Option[String] = None)(implicit p: Parameters): TLNode = { val atomics = LazyModule(new TLAtomicAutomata(logical, arithmetic, concurrency, passthrough) { override lazy val desiredName = (Seq("TLAtomicAutomata") ++ nameSuffix).mkString("_") }) atomics.node } case class CAMParams(a: TLBundleParameters, domainsNeedingHelp: Int) class CAM_S(val params: CAMParams) extends Bundle { val state = UInt(2.W) } class CAM_A(val params: CAMParams) extends Bundle { val bits = new TLBundleA(params.a) val fifoId = UInt(log2Up(params.domainsNeedingHelp).W) val lut = UInt(4.W) } class CAM_D(val params: CAMParams) extends Bundle { val data = UInt(params.a.dataBits.W) val denied = Bool() val corrupt = Bool() } } // Synthesizable unit tests import freechips.rocketchip.unittest._ class TLRAMAtomicAutomata(txns: Int)(implicit p: Parameters) extends LazyModule { val fuzz = LazyModule(new TLFuzzer(txns)) val model = LazyModule(new TLRAMModel("AtomicAutomata")) val ram = LazyModule(new TLRAM(AddressSet(0x0, 0x3ff))) // Confirm that the AtomicAutomata combines read + write errors import TLMessages._ val test = new RequestPattern({a: TLBundleA => val doesA = a.opcode === ArithmeticData || a.opcode === LogicalData val doesR = a.opcode === Get || doesA val doesW = a.opcode === PutFullData || a.opcode === PutPartialData || doesA (doesR && RequestPattern.overlaps(Seq(AddressSet(0x08, ~0x08)))(a)) || (doesW && RequestPattern.overlaps(Seq(AddressSet(0x10, ~0x10)))(a)) }) (ram.node := TLErrorEvaluator(test) := TLFragmenter(4, 256) := TLDelayer(0.1) := TLAtomicAutomata() := TLDelayer(0.1) := TLErrorEvaluator(test, testOn=true, testOff=true) := model.node := fuzz.node) lazy val module = new Impl class Impl extends LazyModuleImp(this) with UnitTestModule { io.finished := fuzz.module.io.finished } } class TLRAMAtomicAutomataTest(txns: Int = 5000, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) { val dut = Module(LazyModule(new TLRAMAtomicAutomata(txns)).module) io.finished := dut.io.finished dut.io.start := io.start } File ClockDomain.scala: package freechips.rocketchip.prci import chisel3._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.lazymodule._ abstract class Domain(implicit p: Parameters) extends LazyModule with HasDomainCrossing { def clockBundle: ClockBundle lazy val module = new Impl class Impl extends LazyRawModuleImp(this) { childClock := clockBundle.clock childReset := clockBundle.reset override def provideImplicitClockToLazyChildren = true // these are just for backwards compatibility with external devices // that were manually wiring themselves to the domain's clock/reset input: val clock = IO(Output(chiselTypeOf(clockBundle.clock))) val reset = IO(Output(chiselTypeOf(clockBundle.reset))) clock := clockBundle.clock reset := clockBundle.reset } } abstract class ClockDomain(implicit p: Parameters) extends Domain with HasClockDomainCrossing class ClockSinkDomain(val clockSinkParams: ClockSinkParameters)(implicit p: Parameters) extends ClockDomain { def this(take: Option[ClockParameters] = None, name: Option[String] = None)(implicit p: Parameters) = this(ClockSinkParameters(take = take, name = name)) val clockNode = ClockSinkNode(Seq(clockSinkParams)) def clockBundle = clockNode.in.head._1 override lazy val desiredName = (clockSinkParams.name.toSeq :+ "ClockSinkDomain").mkString } class ClockSourceDomain(val clockSourceParams: ClockSourceParameters)(implicit p: Parameters) extends ClockDomain { def this(give: Option[ClockParameters] = None, name: Option[String] = None)(implicit p: Parameters) = this(ClockSourceParameters(give = give, name = name)) val clockNode = ClockSourceNode(Seq(clockSourceParams)) def clockBundle = clockNode.out.head._1 override lazy val desiredName = (clockSourceParams.name.toSeq :+ "ClockSourceDomain").mkString } abstract class ResetDomain(implicit p: Parameters) extends Domain with HasResetDomainCrossing File PeripheryBus.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.subsystem import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.devices.tilelink.{BuiltInZeroDeviceParams, BuiltInErrorDeviceParams, HasBuiltInDeviceParams, BuiltInDevices} import freechips.rocketchip.diplomacy.BufferParams import freechips.rocketchip.tilelink.{ RegionReplicator, ReplicatedRegion, HasTLBusParams, HasRegionReplicatorParams, TLBusWrapper, TLBusWrapperInstantiationLike, TLFIFOFixer, TLNode, TLXbar, TLInwardNode, TLOutwardNode, TLBuffer, TLWidthWidget, TLAtomicAutomata, TLEdge } import freechips.rocketchip.util.Location case class BusAtomics( arithmetic: Boolean = true, buffer: BufferParams = BufferParams.default, widenBytes: Option[Int] = None ) case class PeripheryBusParams( beatBytes: Int, blockBytes: Int, atomics: Option[BusAtomics] = Some(BusAtomics()), dtsFrequency: Option[BigInt] = None, zeroDevice: Option[BuiltInZeroDeviceParams] = None, errorDevice: Option[BuiltInErrorDeviceParams] = None, replication: Option[ReplicatedRegion] = None) extends HasTLBusParams with HasBuiltInDeviceParams with HasRegionReplicatorParams with TLBusWrapperInstantiationLike { def instantiate(context: HasTileLinkLocations, loc: Location[TLBusWrapper])(implicit p: Parameters): PeripheryBus = { val pbus = LazyModule(new PeripheryBus(this, loc.name)) pbus.suggestName(loc.name) context.tlBusWrapperLocationMap += (loc -> pbus) pbus } } class PeripheryBus(params: PeripheryBusParams, name: String)(implicit p: Parameters) extends TLBusWrapper(params, name) { override lazy val desiredName = s"PeripheryBus_$name" private val replicator = params.replication.map(r => LazyModule(new RegionReplicator(r))) val prefixNode = replicator.map { r => r.prefix := addressPrefixNexusNode addressPrefixNexusNode } private val fixer = LazyModule(new TLFIFOFixer(TLFIFOFixer.all)) private val node: TLNode = params.atomics.map { pa => val in_xbar = LazyModule(new TLXbar(nameSuffix = Some(s"${name}_in"))) val out_xbar = LazyModule(new TLXbar(nameSuffix = Some(s"${name}_out"))) val fixer_node = replicator.map(fixer.node :*= _.node).getOrElse(fixer.node) (out_xbar.node :*= fixer_node :*= TLBuffer(pa.buffer) :*= (pa.widenBytes.filter(_ > beatBytes).map { w => TLWidthWidget(w) :*= TLAtomicAutomata(arithmetic = pa.arithmetic, nameSuffix = Some(name)) } .getOrElse { TLAtomicAutomata(arithmetic = pa.arithmetic, nameSuffix = Some(name)) }) :*= in_xbar.node) } .getOrElse { TLXbar() :*= fixer.node } def inwardNode: TLInwardNode = node def outwardNode: TLOutwardNode = node def busView: TLEdge = fixer.node.edges.in.head val builtInDevices: BuiltInDevices = BuiltInDevices.attach(params, outwardNode) } File ClockGroup.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.prci import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.lazymodule._ import org.chipsalliance.diplomacy.nodes._ import freechips.rocketchip.resources.FixedClockResource case class ClockGroupingNode(groupName: String)(implicit valName: ValName) extends MixedNexusNode(ClockGroupImp, ClockImp)( dFn = { _ => ClockSourceParameters() }, uFn = { seq => ClockGroupSinkParameters(name = groupName, members = seq) }) { override def circuitIdentity = outputs.size == 1 } class ClockGroup(groupName: String)(implicit p: Parameters) extends LazyModule { val node = ClockGroupingNode(groupName) lazy val module = new Impl class Impl extends LazyRawModuleImp(this) { val (in, _) = node.in(0) val (out, _) = node.out.unzip require (node.in.size == 1) require (in.member.size == out.size) (in.member.data zip out) foreach { case (i, o) => o := i } } } object ClockGroup { def apply()(implicit p: Parameters, valName: ValName) = LazyModule(new ClockGroup(valName.name)).node } case class ClockGroupAggregateNode(groupName: String)(implicit valName: ValName) extends NexusNode(ClockGroupImp)( dFn = { _ => ClockGroupSourceParameters() }, uFn = { seq => ClockGroupSinkParameters(name = groupName, members = seq.flatMap(_.members))}) { override def circuitIdentity = outputs.size == 1 } class ClockGroupAggregator(groupName: String)(implicit p: Parameters) extends LazyModule { val node = ClockGroupAggregateNode(groupName) override lazy val desiredName = s"ClockGroupAggregator_$groupName" lazy val module = new Impl class Impl extends LazyRawModuleImp(this) { val (in, _) = node.in.unzip val (out, _) = node.out.unzip val outputs = out.flatMap(_.member.data) require (node.in.size == 1, s"Aggregator for groupName: ${groupName} had ${node.in.size} inward edges instead of 1") require (in.head.member.size == outputs.size) in.head.member.data.zip(outputs).foreach { case (i, o) => o := i } } } object ClockGroupAggregator { def apply()(implicit p: Parameters, valName: ValName) = LazyModule(new ClockGroupAggregator(valName.name)).node } class SimpleClockGroupSource(numSources: Int = 1)(implicit p: Parameters) extends LazyModule { val node = ClockGroupSourceNode(List.fill(numSources) { ClockGroupSourceParameters() }) lazy val module = new Impl class Impl extends LazyModuleImp(this) { val (out, _) = node.out.unzip out.map { out: ClockGroupBundle => out.member.data.foreach { o => o.clock := clock; o.reset := reset } } } } object SimpleClockGroupSource { def apply(num: Int = 1)(implicit p: Parameters, valName: ValName) = LazyModule(new SimpleClockGroupSource(num)).node } case class FixedClockBroadcastNode(fixedClockOpt: Option[ClockParameters])(implicit valName: ValName) extends NexusNode(ClockImp)( dFn = { seq => fixedClockOpt.map(_ => ClockSourceParameters(give = fixedClockOpt)).orElse(seq.headOption).getOrElse(ClockSourceParameters()) }, uFn = { seq => fixedClockOpt.map(_ => ClockSinkParameters(take = fixedClockOpt)).orElse(seq.headOption).getOrElse(ClockSinkParameters()) }, inputRequiresOutput = false) { def fixedClockResources(name: String, prefix: String = "soc/"): Seq[Option[FixedClockResource]] = Seq(fixedClockOpt.map(t => new FixedClockResource(name, t.freqMHz, prefix))) } class FixedClockBroadcast(fixedClockOpt: Option[ClockParameters])(implicit p: Parameters) extends LazyModule { val node = new FixedClockBroadcastNode(fixedClockOpt) { override def circuitIdentity = outputs.size == 1 } lazy val module = new Impl class Impl extends LazyRawModuleImp(this) { val (in, _) = node.in(0) val (out, _) = node.out.unzip override def desiredName = s"FixedClockBroadcast_${out.size}" require (node.in.size == 1, "FixedClockBroadcast can only broadcast a single clock") out.foreach { _ := in } } } object FixedClockBroadcast { def apply(fixedClockOpt: Option[ClockParameters] = None)(implicit p: Parameters, valName: ValName) = LazyModule(new FixedClockBroadcast(fixedClockOpt)).node } case class PRCIClockGroupNode()(implicit valName: ValName) extends NexusNode(ClockGroupImp)( dFn = { _ => ClockGroupSourceParameters() }, uFn = { _ => ClockGroupSinkParameters("prci", Nil) }, outputRequiresInput = false) File WidthWidget.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.diplomacy.AddressSet import freechips.rocketchip.util.{Repeater, UIntToOH1} // innBeatBytes => the new client-facing bus width class TLWidthWidget(innerBeatBytes: Int)(implicit p: Parameters) extends LazyModule { private def noChangeRequired(manager: TLManagerPortParameters) = manager.beatBytes == innerBeatBytes val node = new TLAdapterNode( clientFn = { case c => c }, managerFn = { case m => m.v1copy(beatBytes = innerBeatBytes) }){ override def circuitIdentity = edges.out.map(_.manager).forall(noChangeRequired) } override lazy val desiredName = s"TLWidthWidget$innerBeatBytes" lazy val module = new Impl class Impl extends LazyModuleImp(this) { def merge[T <: TLDataChannel](edgeIn: TLEdge, in: DecoupledIO[T], edgeOut: TLEdge, out: DecoupledIO[T]) = { val inBytes = edgeIn.manager.beatBytes val outBytes = edgeOut.manager.beatBytes val ratio = outBytes / inBytes val keepBits = log2Ceil(outBytes) val dropBits = log2Ceil(inBytes) val countBits = log2Ceil(ratio) val size = edgeIn.size(in.bits) val hasData = edgeIn.hasData(in.bits) val limit = UIntToOH1(size, keepBits) >> dropBits val count = RegInit(0.U(countBits.W)) val first = count === 0.U val last = count === limit || !hasData val enable = Seq.tabulate(ratio) { i => !((count ^ i.U) & limit).orR } val corrupt_reg = RegInit(false.B) val corrupt_in = edgeIn.corrupt(in.bits) val corrupt_out = corrupt_in || corrupt_reg when (in.fire) { count := count + 1.U corrupt_reg := corrupt_out when (last) { count := 0.U corrupt_reg := false.B } } def helper(idata: UInt): UInt = { // rdata is X until the first time a multi-beat write occurs. // Prevent the X from leaking outside by jamming the mux control until // the first time rdata is written (and hence no longer X). val rdata_written_once = RegInit(false.B) val masked_enable = enable.map(_ || !rdata_written_once) val odata = Seq.fill(ratio) { WireInit(idata) } val rdata = Reg(Vec(ratio-1, chiselTypeOf(idata))) val pdata = rdata :+ idata val mdata = (masked_enable zip (odata zip pdata)) map { case (e, (o, p)) => Mux(e, o, p) } when (in.fire && !last) { rdata_written_once := true.B (rdata zip mdata) foreach { case (r, m) => r := m } } Cat(mdata.reverse) } in.ready := out.ready || !last out.valid := in.valid && last out.bits := in.bits // Don't put down hardware if we never carry data edgeOut.data(out.bits) := (if (edgeIn.staticHasData(in.bits) == Some(false)) 0.U else helper(edgeIn.data(in.bits))) edgeOut.corrupt(out.bits) := corrupt_out (out.bits, in.bits) match { case (o: TLBundleA, i: TLBundleA) => o.mask := edgeOut.mask(o.address, o.size) & Mux(hasData, helper(i.mask), ~0.U(outBytes.W)) case (o: TLBundleB, i: TLBundleB) => o.mask := edgeOut.mask(o.address, o.size) & Mux(hasData, helper(i.mask), ~0.U(outBytes.W)) case (o: TLBundleC, i: TLBundleC) => () case (o: TLBundleD, i: TLBundleD) => () case _ => require(false, "Impossible bundle combination in WidthWidget") } } def split[T <: TLDataChannel](edgeIn: TLEdge, in: DecoupledIO[T], edgeOut: TLEdge, out: DecoupledIO[T], sourceMap: UInt => UInt) = { val inBytes = edgeIn.manager.beatBytes val outBytes = edgeOut.manager.beatBytes val ratio = inBytes / outBytes val keepBits = log2Ceil(inBytes) val dropBits = log2Ceil(outBytes) val countBits = log2Ceil(ratio) val size = edgeIn.size(in.bits) val hasData = edgeIn.hasData(in.bits) val limit = UIntToOH1(size, keepBits) >> dropBits val count = RegInit(0.U(countBits.W)) val first = count === 0.U val last = count === limit || !hasData when (out.fire) { count := count + 1.U when (last) { count := 0.U } } // For sub-beat transfer, extract which part matters val sel = in.bits match { case a: TLBundleA => a.address(keepBits-1, dropBits) case b: TLBundleB => b.address(keepBits-1, dropBits) case c: TLBundleC => c.address(keepBits-1, dropBits) case d: TLBundleD => { val sel = sourceMap(d.source) val hold = Mux(first, sel, RegEnable(sel, first)) // a_first is not for whole xfer hold & ~limit // if more than one a_first/xfer, the address must be aligned anyway } } val index = sel | count def helper(idata: UInt, width: Int): UInt = { val mux = VecInit.tabulate(ratio) { i => idata((i+1)*outBytes*width-1, i*outBytes*width) } mux(index) } out.bits := in.bits out.valid := in.valid in.ready := out.ready // Don't put down hardware if we never carry data edgeOut.data(out.bits) := (if (edgeIn.staticHasData(in.bits) == Some(false)) 0.U else helper(edgeIn.data(in.bits), 8)) (out.bits, in.bits) match { case (o: TLBundleA, i: TLBundleA) => o.mask := helper(i.mask, 1) case (o: TLBundleB, i: TLBundleB) => o.mask := helper(i.mask, 1) case (o: TLBundleC, i: TLBundleC) => () // replicating corrupt to all beats is ok case (o: TLBundleD, i: TLBundleD) => () case _ => require(false, "Impossbile bundle combination in WidthWidget") } // Repeat the input if we're not last !last } def splice[T <: TLDataChannel](edgeIn: TLEdge, in: DecoupledIO[T], edgeOut: TLEdge, out: DecoupledIO[T], sourceMap: UInt => UInt) = { if (edgeIn.manager.beatBytes == edgeOut.manager.beatBytes) { // nothing to do; pass it through out.bits := in.bits out.valid := in.valid in.ready := out.ready } else if (edgeIn.manager.beatBytes > edgeOut.manager.beatBytes) { // split input to output val repeat = Wire(Bool()) val repeated = Repeater(in, repeat) val cated = Wire(chiselTypeOf(repeated)) cated <> repeated edgeIn.data(cated.bits) := Cat( edgeIn.data(repeated.bits)(edgeIn.manager.beatBytes*8-1, edgeOut.manager.beatBytes*8), edgeIn.data(in.bits)(edgeOut.manager.beatBytes*8-1, 0)) repeat := split(edgeIn, cated, edgeOut, out, sourceMap) } else { // merge input to output merge(edgeIn, in, edgeOut, out) } } (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => // If the master is narrower than the slave, the D channel must be narrowed. // This is tricky, because the D channel has no address data. // Thus, you don't know which part of a sub-beat transfer to extract. // To fix this, we record the relevant address bits for all sources. // The assumption is that this sort of situation happens only where // you connect a narrow master to the system bus, so there are few sources. def sourceMap(source_bits: UInt) = { val source = if (edgeIn.client.endSourceId == 1) 0.U(0.W) else source_bits require (edgeOut.manager.beatBytes > edgeIn.manager.beatBytes) val keepBits = log2Ceil(edgeOut.manager.beatBytes) val dropBits = log2Ceil(edgeIn.manager.beatBytes) val sources = Reg(Vec(edgeIn.client.endSourceId, UInt((keepBits-dropBits).W))) val a_sel = in.a.bits.address(keepBits-1, dropBits) when (in.a.fire) { if (edgeIn.client.endSourceId == 1) { // avoid extraction-index-width warning sources(0) := a_sel } else { sources(in.a.bits.source) := a_sel } } // depopulate unused source registers: edgeIn.client.unusedSources.foreach { id => sources(id) := 0.U } val bypass = in.a.valid && in.a.bits.source === source if (edgeIn.manager.minLatency > 0) sources(source) else Mux(bypass, a_sel, sources(source)) } splice(edgeIn, in.a, edgeOut, out.a, sourceMap) splice(edgeOut, out.d, edgeIn, in.d, sourceMap) if (edgeOut.manager.anySupportAcquireB && edgeIn.client.anySupportProbe) { splice(edgeOut, out.b, edgeIn, in.b, sourceMap) splice(edgeIn, in.c, edgeOut, out.c, sourceMap) out.e.valid := in.e.valid out.e.bits := in.e.bits in.e.ready := out.e.ready } else { in.b.valid := false.B in.c.ready := true.B in.e.ready := true.B out.b.ready := true.B out.c.valid := false.B out.e.valid := false.B } } } } object TLWidthWidget { def apply(innerBeatBytes: Int)(implicit p: Parameters): TLNode = { val widget = LazyModule(new TLWidthWidget(innerBeatBytes)) widget.node } def apply(wrapper: TLBusWrapper)(implicit p: Parameters): TLNode = apply(wrapper.beatBytes) } // Synthesizable unit tests import freechips.rocketchip.unittest._ class TLRAMWidthWidget(first: Int, second: Int, txns: Int)(implicit p: Parameters) extends LazyModule { val fuzz = LazyModule(new TLFuzzer(txns)) val model = LazyModule(new TLRAMModel("WidthWidget")) val ram = LazyModule(new TLRAM(AddressSet(0x0, 0x3ff))) (ram.node := TLDelayer(0.1) := TLFragmenter(4, 256) := TLWidthWidget(second) := TLWidthWidget(first) := TLDelayer(0.1) := model.node := fuzz.node) lazy val module = new Impl class Impl extends LazyModuleImp(this) with UnitTestModule { io.finished := fuzz.module.io.finished } } class TLRAMWidthWidgetTest(little: Int, big: Int, txns: Int = 5000, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) { val dut = Module(LazyModule(new TLRAMWidthWidget(little,big,txns)).module) dut.io.start := DontCare io.finished := dut.io.finished } File LazyModuleImp.scala: package org.chipsalliance.diplomacy.lazymodule import chisel3.{withClockAndReset, Module, RawModule, Reset, _} import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo} import firrtl.passes.InlineAnnotation import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.nodes.Dangle import scala.collection.immutable.SortedMap /** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]]. * * This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy. */ sealed trait LazyModuleImpLike extends RawModule { /** [[LazyModule]] that contains this instance. */ val wrapper: LazyModule /** IOs that will be automatically "punched" for this instance. */ val auto: AutoBundle /** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */ protected[diplomacy] val dangles: Seq[Dangle] // [[wrapper.module]] had better not be accessed while LazyModules are still being built! require( LazyModule.scope.isEmpty, s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}" ) /** Set module name. Defaults to the containing LazyModule's desiredName. */ override def desiredName: String = wrapper.desiredName suggestName(wrapper.suggestedName) /** [[Parameters]] for chisel [[Module]]s. */ implicit val p: Parameters = wrapper.p /** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and * submodules. */ protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = { // 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]], // 2. return [[Dangle]]s from each module. val childDangles = wrapper.children.reverse.flatMap { c => implicit val sourceInfo: SourceInfo = c.info c.cloneProto.map { cp => // If the child is a clone, then recursively set cloneProto of its children as well def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = { require(bases.size == clones.size) (bases.zip(clones)).map { case (l, r) => require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}") l.cloneProto = Some(r) assignCloneProtos(l.children, r.children) } } assignCloneProtos(c.children, cp.children) // Clone the child module as a record, and get its [[AutoBundle]] val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName) val clonedAuto = clone("auto").asInstanceOf[AutoBundle] // Get the empty [[Dangle]]'s of the cloned child val rawDangles = c.cloneDangles() require(rawDangles.size == clonedAuto.elements.size) // Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) } dangles }.getOrElse { // For non-clones, instantiate the child module val mod = try { Module(c.module) } catch { case e: ChiselException => { println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}") throw e } } mod.dangles } } // Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]]. // This will result in a sequence of [[Dangle]] from these [[BaseNode]]s. val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate()) // Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]] val allDangles = nodeDangles ++ childDangles // Group [[allDangles]] by their [[source]]. val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*) // For each [[source]] set of [[Dangle]]s of size 2, ensure that these // can be connected as a source-sink pair (have opposite flipped value). // Make the connection and mark them as [[done]]. val done = Set() ++ pairing.values.filter(_.size == 2).map { case Seq(a, b) => require(a.flipped != b.flipped) // @todo <> in chisel3 makes directionless connection. if (a.flipped) { a.data <> b.data } else { b.data <> a.data } a.source case _ => None } // Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module. val forward = allDangles.filter(d => !done(d.source)) // Generate [[AutoBundle]] IO from [[forward]]. val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*)) // Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]] val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) => if (d.flipped) { d.data <> io } else { io <> d.data } d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name) } // Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]]. wrapper.inModuleBody.reverse.foreach { _() } if (wrapper.shouldBeInlined) { chisel3.experimental.annotate(new ChiselAnnotation { def toFirrtl = InlineAnnotation(toNamed) }) } // Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]]. (auto, dangles) } } /** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike { /** Instantiate hardware of this `Module`. */ val (auto, dangles) = instantiate() } /** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike { // These wires are the default clock+reset for all LazyModule children. // It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the // [[LazyRawModuleImp]] children. // Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly. /** drive clock explicitly. */ val childClock: Clock = Wire(Clock()) /** drive reset explicitly. */ val childReset: Reset = Wire(Reset()) // the default is that these are disabled childClock := false.B.asClock childReset := chisel3.DontCare def provideImplicitClockToLazyChildren: Boolean = false val (auto, dangles) = if (provideImplicitClockToLazyChildren) { withClockAndReset(childClock, childReset) { instantiate() } } else { instantiate() } } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.nodes._ import freechips.rocketchip.diplomacy.{ AddressDecoder, AddressSet, BufferParams, DirectedBuffers, IdMap, IdMapEntry, IdRange, RegionType, TransferSizes } import freechips.rocketchip.resources.{Resource, ResourceAddress, ResourcePermissions} import freechips.rocketchip.util.{ AsyncQueueParams, BundleField, BundleFieldBase, BundleKeyBase, CreditedDelay, groupByIntoSeq, RationalDirection, SimpleProduct } import scala.math.max //These transfer sizes describe requests issued from masters on the A channel that will be responded by slaves on the D channel case class TLMasterToSlaveTransferSizes( // Supports both Acquire+Release of the following two sizes: acquireT: TransferSizes = TransferSizes.none, acquireB: TransferSizes = TransferSizes.none, arithmetic: TransferSizes = TransferSizes.none, logical: TransferSizes = TransferSizes.none, get: TransferSizes = TransferSizes.none, putFull: TransferSizes = TransferSizes.none, putPartial: TransferSizes = TransferSizes.none, hint: TransferSizes = TransferSizes.none) extends TLCommonTransferSizes { def intersect(rhs: TLMasterToSlaveTransferSizes) = TLMasterToSlaveTransferSizes( acquireT = acquireT .intersect(rhs.acquireT), acquireB = acquireB .intersect(rhs.acquireB), arithmetic = arithmetic.intersect(rhs.arithmetic), logical = logical .intersect(rhs.logical), get = get .intersect(rhs.get), putFull = putFull .intersect(rhs.putFull), putPartial = putPartial.intersect(rhs.putPartial), hint = hint .intersect(rhs.hint)) def mincover(rhs: TLMasterToSlaveTransferSizes) = TLMasterToSlaveTransferSizes( acquireT = acquireT .mincover(rhs.acquireT), acquireB = acquireB .mincover(rhs.acquireB), arithmetic = arithmetic.mincover(rhs.arithmetic), logical = logical .mincover(rhs.logical), get = get .mincover(rhs.get), putFull = putFull .mincover(rhs.putFull), putPartial = putPartial.mincover(rhs.putPartial), hint = hint .mincover(rhs.hint)) // Reduce rendering to a simple yes/no per field override def toString = { def str(x: TransferSizes, flag: String) = if (x.none) "" else flag def flags = Vector( str(acquireT, "T"), str(acquireB, "B"), str(arithmetic, "A"), str(logical, "L"), str(get, "G"), str(putFull, "F"), str(putPartial, "P"), str(hint, "H")) flags.mkString } // Prints out the actual information in a user readable way def infoString = { s"""acquireT = ${acquireT} |acquireB = ${acquireB} |arithmetic = ${arithmetic} |logical = ${logical} |get = ${get} |putFull = ${putFull} |putPartial = ${putPartial} |hint = ${hint} | |""".stripMargin } } object TLMasterToSlaveTransferSizes { def unknownEmits = TLMasterToSlaveTransferSizes( acquireT = TransferSizes(1, 4096), acquireB = TransferSizes(1, 4096), arithmetic = TransferSizes(1, 4096), logical = TransferSizes(1, 4096), get = TransferSizes(1, 4096), putFull = TransferSizes(1, 4096), putPartial = TransferSizes(1, 4096), hint = TransferSizes(1, 4096)) def unknownSupports = TLMasterToSlaveTransferSizes() } //These transfer sizes describe requests issued from slaves on the B channel that will be responded by masters on the C channel case class TLSlaveToMasterTransferSizes( probe: TransferSizes = TransferSizes.none, arithmetic: TransferSizes = TransferSizes.none, logical: TransferSizes = TransferSizes.none, get: TransferSizes = TransferSizes.none, putFull: TransferSizes = TransferSizes.none, putPartial: TransferSizes = TransferSizes.none, hint: TransferSizes = TransferSizes.none ) extends TLCommonTransferSizes { def intersect(rhs: TLSlaveToMasterTransferSizes) = TLSlaveToMasterTransferSizes( probe = probe .intersect(rhs.probe), arithmetic = arithmetic.intersect(rhs.arithmetic), logical = logical .intersect(rhs.logical), get = get .intersect(rhs.get), putFull = putFull .intersect(rhs.putFull), putPartial = putPartial.intersect(rhs.putPartial), hint = hint .intersect(rhs.hint) ) def mincover(rhs: TLSlaveToMasterTransferSizes) = TLSlaveToMasterTransferSizes( probe = probe .mincover(rhs.probe), arithmetic = arithmetic.mincover(rhs.arithmetic), logical = logical .mincover(rhs.logical), get = get .mincover(rhs.get), putFull = putFull .mincover(rhs.putFull), putPartial = putPartial.mincover(rhs.putPartial), hint = hint .mincover(rhs.hint) ) // Reduce rendering to a simple yes/no per field override def toString = { def str(x: TransferSizes, flag: String) = if (x.none) "" else flag def flags = Vector( str(probe, "P"), str(arithmetic, "A"), str(logical, "L"), str(get, "G"), str(putFull, "F"), str(putPartial, "P"), str(hint, "H")) flags.mkString } // Prints out the actual information in a user readable way def infoString = { s"""probe = ${probe} |arithmetic = ${arithmetic} |logical = ${logical} |get = ${get} |putFull = ${putFull} |putPartial = ${putPartial} |hint = ${hint} | |""".stripMargin } } object TLSlaveToMasterTransferSizes { def unknownEmits = TLSlaveToMasterTransferSizes( arithmetic = TransferSizes(1, 4096), logical = TransferSizes(1, 4096), get = TransferSizes(1, 4096), putFull = TransferSizes(1, 4096), putPartial = TransferSizes(1, 4096), hint = TransferSizes(1, 4096), probe = TransferSizes(1, 4096)) def unknownSupports = TLSlaveToMasterTransferSizes() } trait TLCommonTransferSizes { def arithmetic: TransferSizes def logical: TransferSizes def get: TransferSizes def putFull: TransferSizes def putPartial: TransferSizes def hint: TransferSizes } class TLSlaveParameters private( val nodePath: Seq[BaseNode], val resources: Seq[Resource], setName: Option[String], val address: Seq[AddressSet], val regionType: RegionType.T, val executable: Boolean, val fifoId: Option[Int], val supports: TLMasterToSlaveTransferSizes, val emits: TLSlaveToMasterTransferSizes, // By default, slaves are forbidden from issuing 'denied' responses (it prevents Fragmentation) val alwaysGrantsT: Boolean, // typically only true for CacheCork'd read-write devices; dual: neverReleaseData // If fifoId=Some, all accesses sent to the same fifoId are executed and ACK'd in FIFO order // Note: you can only rely on this FIFO behaviour if your TLMasterParameters include requestFifo val mayDenyGet: Boolean, // applies to: AccessAckData, GrantData val mayDenyPut: Boolean) // applies to: AccessAck, Grant, HintAck // ReleaseAck may NEVER be denied extends SimpleProduct { def sortedAddress = address.sorted override def canEqual(that: Any): Boolean = that.isInstanceOf[TLSlaveParameters] override def productPrefix = "TLSlaveParameters" // We intentionally omit nodePath for equality testing / formatting def productArity: Int = 11 def productElement(n: Int): Any = n match { case 0 => name case 1 => address case 2 => resources case 3 => regionType case 4 => executable case 5 => fifoId case 6 => supports case 7 => emits case 8 => alwaysGrantsT case 9 => mayDenyGet case 10 => mayDenyPut case _ => throw new IndexOutOfBoundsException(n.toString) } def supportsAcquireT: TransferSizes = supports.acquireT def supportsAcquireB: TransferSizes = supports.acquireB def supportsArithmetic: TransferSizes = supports.arithmetic def supportsLogical: TransferSizes = supports.logical def supportsGet: TransferSizes = supports.get def supportsPutFull: TransferSizes = supports.putFull def supportsPutPartial: TransferSizes = supports.putPartial def supportsHint: TransferSizes = supports.hint require (!address.isEmpty, "Address cannot be empty") address.foreach { a => require (a.finite, "Address must be finite") } address.combinations(2).foreach { case Seq(x,y) => require (!x.overlaps(y), s"$x and $y overlap.") } require (supportsPutFull.contains(supportsPutPartial), s"PutFull($supportsPutFull) < PutPartial($supportsPutPartial)") require (supportsPutFull.contains(supportsArithmetic), s"PutFull($supportsPutFull) < Arithmetic($supportsArithmetic)") require (supportsPutFull.contains(supportsLogical), s"PutFull($supportsPutFull) < Logical($supportsLogical)") require (supportsGet.contains(supportsArithmetic), s"Get($supportsGet) < Arithmetic($supportsArithmetic)") require (supportsGet.contains(supportsLogical), s"Get($supportsGet) < Logical($supportsLogical)") require (supportsAcquireB.contains(supportsAcquireT), s"AcquireB($supportsAcquireB) < AcquireT($supportsAcquireT)") require (!alwaysGrantsT || supportsAcquireT, s"Must supportAcquireT if promising to always grantT") // Make sure that the regionType agrees with the capabilities require (!supportsAcquireB || regionType >= RegionType.UNCACHED) // acquire -> uncached, tracked, cached require (regionType <= RegionType.UNCACHED || supportsAcquireB) // tracked, cached -> acquire require (regionType != RegionType.UNCACHED || supportsGet) // uncached -> supportsGet val name = setName.orElse(nodePath.lastOption.map(_.lazyModule.name)).getOrElse("disconnected") val maxTransfer = List( // Largest supported transfer of all types supportsAcquireT.max, supportsAcquireB.max, supportsArithmetic.max, supportsLogical.max, supportsGet.max, supportsPutFull.max, supportsPutPartial.max).max val maxAddress = address.map(_.max).max val minAlignment = address.map(_.alignment).min // The device had better not support a transfer larger than its alignment require (minAlignment >= maxTransfer, s"Bad $address: minAlignment ($minAlignment) must be >= maxTransfer ($maxTransfer)") def toResource: ResourceAddress = { ResourceAddress(address, ResourcePermissions( r = supportsAcquireB || supportsGet, w = supportsAcquireT || supportsPutFull, x = executable, c = supportsAcquireB, a = supportsArithmetic && supportsLogical)) } def findTreeViolation() = nodePath.find { case _: MixedAdapterNode[_, _, _, _, _, _, _, _] => false case _: SinkNode[_, _, _, _, _] => false case node => node.inputs.size != 1 } def isTree = findTreeViolation() == None def infoString = { s"""Slave Name = ${name} |Slave Address = ${address} |supports = ${supports.infoString} | |""".stripMargin } def v1copy( address: Seq[AddressSet] = address, resources: Seq[Resource] = resources, regionType: RegionType.T = regionType, executable: Boolean = executable, nodePath: Seq[BaseNode] = nodePath, supportsAcquireT: TransferSizes = supports.acquireT, supportsAcquireB: TransferSizes = supports.acquireB, supportsArithmetic: TransferSizes = supports.arithmetic, supportsLogical: TransferSizes = supports.logical, supportsGet: TransferSizes = supports.get, supportsPutFull: TransferSizes = supports.putFull, supportsPutPartial: TransferSizes = supports.putPartial, supportsHint: TransferSizes = supports.hint, mayDenyGet: Boolean = mayDenyGet, mayDenyPut: Boolean = mayDenyPut, alwaysGrantsT: Boolean = alwaysGrantsT, fifoId: Option[Int] = fifoId) = { new TLSlaveParameters( setName = setName, address = address, resources = resources, regionType = regionType, executable = executable, nodePath = nodePath, supports = TLMasterToSlaveTransferSizes( acquireT = supportsAcquireT, acquireB = supportsAcquireB, arithmetic = supportsArithmetic, logical = supportsLogical, get = supportsGet, putFull = supportsPutFull, putPartial = supportsPutPartial, hint = supportsHint), emits = emits, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut, alwaysGrantsT = alwaysGrantsT, fifoId = fifoId) } def v2copy( nodePath: Seq[BaseNode] = nodePath, resources: Seq[Resource] = resources, name: Option[String] = setName, address: Seq[AddressSet] = address, regionType: RegionType.T = regionType, executable: Boolean = executable, fifoId: Option[Int] = fifoId, supports: TLMasterToSlaveTransferSizes = supports, emits: TLSlaveToMasterTransferSizes = emits, alwaysGrantsT: Boolean = alwaysGrantsT, mayDenyGet: Boolean = mayDenyGet, mayDenyPut: Boolean = mayDenyPut) = { new TLSlaveParameters( nodePath = nodePath, resources = resources, setName = name, address = address, regionType = regionType, executable = executable, fifoId = fifoId, supports = supports, emits = emits, alwaysGrantsT = alwaysGrantsT, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut) } @deprecated("Use v1copy instead of copy","") def copy( address: Seq[AddressSet] = address, resources: Seq[Resource] = resources, regionType: RegionType.T = regionType, executable: Boolean = executable, nodePath: Seq[BaseNode] = nodePath, supportsAcquireT: TransferSizes = supports.acquireT, supportsAcquireB: TransferSizes = supports.acquireB, supportsArithmetic: TransferSizes = supports.arithmetic, supportsLogical: TransferSizes = supports.logical, supportsGet: TransferSizes = supports.get, supportsPutFull: TransferSizes = supports.putFull, supportsPutPartial: TransferSizes = supports.putPartial, supportsHint: TransferSizes = supports.hint, mayDenyGet: Boolean = mayDenyGet, mayDenyPut: Boolean = mayDenyPut, alwaysGrantsT: Boolean = alwaysGrantsT, fifoId: Option[Int] = fifoId) = { v1copy( address = address, resources = resources, regionType = regionType, executable = executable, nodePath = nodePath, supportsAcquireT = supportsAcquireT, supportsAcquireB = supportsAcquireB, supportsArithmetic = supportsArithmetic, supportsLogical = supportsLogical, supportsGet = supportsGet, supportsPutFull = supportsPutFull, supportsPutPartial = supportsPutPartial, supportsHint = supportsHint, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut, alwaysGrantsT = alwaysGrantsT, fifoId = fifoId) } } object TLSlaveParameters { def v1( address: Seq[AddressSet], resources: Seq[Resource] = Seq(), regionType: RegionType.T = RegionType.GET_EFFECTS, executable: Boolean = false, nodePath: Seq[BaseNode] = Seq(), supportsAcquireT: TransferSizes = TransferSizes.none, supportsAcquireB: TransferSizes = TransferSizes.none, supportsArithmetic: TransferSizes = TransferSizes.none, supportsLogical: TransferSizes = TransferSizes.none, supportsGet: TransferSizes = TransferSizes.none, supportsPutFull: TransferSizes = TransferSizes.none, supportsPutPartial: TransferSizes = TransferSizes.none, supportsHint: TransferSizes = TransferSizes.none, mayDenyGet: Boolean = false, mayDenyPut: Boolean = false, alwaysGrantsT: Boolean = false, fifoId: Option[Int] = None) = { new TLSlaveParameters( setName = None, address = address, resources = resources, regionType = regionType, executable = executable, nodePath = nodePath, supports = TLMasterToSlaveTransferSizes( acquireT = supportsAcquireT, acquireB = supportsAcquireB, arithmetic = supportsArithmetic, logical = supportsLogical, get = supportsGet, putFull = supportsPutFull, putPartial = supportsPutPartial, hint = supportsHint), emits = TLSlaveToMasterTransferSizes.unknownEmits, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut, alwaysGrantsT = alwaysGrantsT, fifoId = fifoId) } def v2( address: Seq[AddressSet], nodePath: Seq[BaseNode] = Seq(), resources: Seq[Resource] = Seq(), name: Option[String] = None, regionType: RegionType.T = RegionType.GET_EFFECTS, executable: Boolean = false, fifoId: Option[Int] = None, supports: TLMasterToSlaveTransferSizes = TLMasterToSlaveTransferSizes.unknownSupports, emits: TLSlaveToMasterTransferSizes = TLSlaveToMasterTransferSizes.unknownEmits, alwaysGrantsT: Boolean = false, mayDenyGet: Boolean = false, mayDenyPut: Boolean = false) = { new TLSlaveParameters( nodePath = nodePath, resources = resources, setName = name, address = address, regionType = regionType, executable = executable, fifoId = fifoId, supports = supports, emits = emits, alwaysGrantsT = alwaysGrantsT, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut) } } object TLManagerParameters { @deprecated("Use TLSlaveParameters.v1 instead of TLManagerParameters","") def apply( address: Seq[AddressSet], resources: Seq[Resource] = Seq(), regionType: RegionType.T = RegionType.GET_EFFECTS, executable: Boolean = false, nodePath: Seq[BaseNode] = Seq(), supportsAcquireT: TransferSizes = TransferSizes.none, supportsAcquireB: TransferSizes = TransferSizes.none, supportsArithmetic: TransferSizes = TransferSizes.none, supportsLogical: TransferSizes = TransferSizes.none, supportsGet: TransferSizes = TransferSizes.none, supportsPutFull: TransferSizes = TransferSizes.none, supportsPutPartial: TransferSizes = TransferSizes.none, supportsHint: TransferSizes = TransferSizes.none, mayDenyGet: Boolean = false, mayDenyPut: Boolean = false, alwaysGrantsT: Boolean = false, fifoId: Option[Int] = None) = TLSlaveParameters.v1( address, resources, regionType, executable, nodePath, supportsAcquireT, supportsAcquireB, supportsArithmetic, supportsLogical, supportsGet, supportsPutFull, supportsPutPartial, supportsHint, mayDenyGet, mayDenyPut, alwaysGrantsT, fifoId, ) } case class TLChannelBeatBytes(a: Option[Int], b: Option[Int], c: Option[Int], d: Option[Int]) { def members = Seq(a, b, c, d) members.collect { case Some(beatBytes) => require (isPow2(beatBytes), "Data channel width must be a power of 2") } } object TLChannelBeatBytes{ def apply(beatBytes: Int): TLChannelBeatBytes = TLChannelBeatBytes( Some(beatBytes), Some(beatBytes), Some(beatBytes), Some(beatBytes)) def apply(): TLChannelBeatBytes = TLChannelBeatBytes( None, None, None, None) } class TLSlavePortParameters private( val slaves: Seq[TLSlaveParameters], val channelBytes: TLChannelBeatBytes, val endSinkId: Int, val minLatency: Int, val responseFields: Seq[BundleFieldBase], val requestKeys: Seq[BundleKeyBase]) extends SimpleProduct { def sortedSlaves = slaves.sortBy(_.sortedAddress.head) override def canEqual(that: Any): Boolean = that.isInstanceOf[TLSlavePortParameters] override def productPrefix = "TLSlavePortParameters" def productArity: Int = 6 def productElement(n: Int): Any = n match { case 0 => slaves case 1 => channelBytes case 2 => endSinkId case 3 => minLatency case 4 => responseFields case 5 => requestKeys case _ => throw new IndexOutOfBoundsException(n.toString) } require (!slaves.isEmpty, "Slave ports must have slaves") require (endSinkId >= 0, "Sink ids cannot be negative") require (minLatency >= 0, "Minimum required latency cannot be negative") // Using this API implies you cannot handle mixed-width busses def beatBytes = { channelBytes.members.foreach { width => require (width.isDefined && width == channelBytes.a) } channelBytes.a.get } // TODO this should be deprecated def managers = slaves def requireFifo(policy: TLFIFOFixer.Policy = TLFIFOFixer.allFIFO) = { val relevant = slaves.filter(m => policy(m)) relevant.foreach { m => require(m.fifoId == relevant.head.fifoId, s"${m.name} had fifoId ${m.fifoId}, which was not homogeneous (${slaves.map(s => (s.name, s.fifoId))}) ") } } // Bounds on required sizes def maxAddress = slaves.map(_.maxAddress).max def maxTransfer = slaves.map(_.maxTransfer).max def mayDenyGet = slaves.exists(_.mayDenyGet) def mayDenyPut = slaves.exists(_.mayDenyPut) // Diplomatically determined operation sizes emitted by all outward Slaves // as opposed to emits* which generate circuitry to check which specific addresses val allEmitClaims = slaves.map(_.emits).reduce( _ intersect _) // Operation Emitted by at least one outward Slaves // as opposed to emits* which generate circuitry to check which specific addresses val anyEmitClaims = slaves.map(_.emits).reduce(_ mincover _) // Diplomatically determined operation sizes supported by all outward Slaves // as opposed to supports* which generate circuitry to check which specific addresses val allSupportClaims = slaves.map(_.supports).reduce( _ intersect _) val allSupportAcquireT = allSupportClaims.acquireT val allSupportAcquireB = allSupportClaims.acquireB val allSupportArithmetic = allSupportClaims.arithmetic val allSupportLogical = allSupportClaims.logical val allSupportGet = allSupportClaims.get val allSupportPutFull = allSupportClaims.putFull val allSupportPutPartial = allSupportClaims.putPartial val allSupportHint = allSupportClaims.hint // Operation supported by at least one outward Slaves // as opposed to supports* which generate circuitry to check which specific addresses val anySupportClaims = slaves.map(_.supports).reduce(_ mincover _) val anySupportAcquireT = !anySupportClaims.acquireT.none val anySupportAcquireB = !anySupportClaims.acquireB.none val anySupportArithmetic = !anySupportClaims.arithmetic.none val anySupportLogical = !anySupportClaims.logical.none val anySupportGet = !anySupportClaims.get.none val anySupportPutFull = !anySupportClaims.putFull.none val anySupportPutPartial = !anySupportClaims.putPartial.none val anySupportHint = !anySupportClaims.hint.none // Supporting Acquire means being routable for GrantAck require ((endSinkId == 0) == !anySupportAcquireB) // These return Option[TLSlaveParameters] for your convenience def find(address: BigInt) = slaves.find(_.address.exists(_.contains(address))) // The safe version will check the entire address def findSafe(address: UInt) = VecInit(sortedSlaves.map(_.address.map(_.contains(address)).reduce(_ || _))) // The fast version assumes the address is valid (you probably want fastProperty instead of this function) def findFast(address: UInt) = { val routingMask = AddressDecoder(slaves.map(_.address)) VecInit(sortedSlaves.map(_.address.map(_.widen(~routingMask)).distinct.map(_.contains(address)).reduce(_ || _))) } // Compute the simplest AddressSets that decide a key def fastPropertyGroup[K](p: TLSlaveParameters => K): Seq[(K, Seq[AddressSet])] = { val groups = groupByIntoSeq(sortedSlaves.map(m => (p(m), m.address)))( _._1).map { case (k, vs) => k -> vs.flatMap(_._2) } val reductionMask = AddressDecoder(groups.map(_._2)) groups.map { case (k, seq) => k -> AddressSet.unify(seq.map(_.widen(~reductionMask)).distinct) } } // Select a property def fastProperty[K, D <: Data](address: UInt, p: TLSlaveParameters => K, d: K => D): D = Mux1H(fastPropertyGroup(p).map { case (v, a) => (a.map(_.contains(address)).reduce(_||_), d(v)) }) // Note: returns the actual fifoId + 1 or 0 if None def findFifoIdFast(address: UInt) = fastProperty(address, _.fifoId.map(_+1).getOrElse(0), (i:Int) => i.U) def hasFifoIdFast(address: UInt) = fastProperty(address, _.fifoId.isDefined, (b:Boolean) => b.B) // Does this Port manage this ID/address? def containsSafe(address: UInt) = findSafe(address).reduce(_ || _) private def addressHelper( // setting safe to false indicates that all addresses are expected to be legal, which might reduce circuit complexity safe: Boolean, // member filters out the sizes being checked based on the opcode being emitted or supported member: TLSlaveParameters => TransferSizes, address: UInt, lgSize: UInt, // range provides a limit on the sizes that are expected to be evaluated, which might reduce circuit complexity range: Option[TransferSizes]): Bool = { // trim reduces circuit complexity by intersecting checked sizes with the range argument def trim(x: TransferSizes) = range.map(_.intersect(x)).getOrElse(x) // groupBy returns an unordered map, convert back to Seq and sort the result for determinism // groupByIntoSeq is turning slaves into trimmed membership sizes // We are grouping all the slaves by their transfer size where // if they support the trimmed size then // member is the type of transfer that you are looking for (What you are trying to filter on) // When you consider membership, you are trimming the sizes to only the ones that you care about // you are filtering the slaves based on both whether they support a particular opcode and the size // Grouping the slaves based on the actual transfer size range they support // intersecting the range and checking their membership // FOR SUPPORTCASES instead of returning the list of slaves, // you are returning a map from transfer size to the set of // address sets that are supported for that transfer size // find all the slaves that support a certain type of operation and then group their addresses by the supported size // for every size there could be multiple address ranges // safety is a trade off between checking between all possible addresses vs only the addresses // that are known to have supported sizes // the trade off is 'checking all addresses is a more expensive circuit but will always give you // the right answer even if you give it an illegal address' // the not safe version is a cheaper circuit but if you give it an illegal address then it might produce the wrong answer // fast presumes address legality // This groupByIntoSeq deterministically groups all address sets for which a given `member` transfer size applies. // In the resulting Map of cases, the keys are transfer sizes and the values are all address sets which emit or support that size. val supportCases = groupByIntoSeq(slaves)(m => trim(member(m))).map { case (k: TransferSizes, vs: Seq[TLSlaveParameters]) => k -> vs.flatMap(_.address) } // safe produces a circuit that compares against all possible addresses, // whereas fast presumes that the address is legal but uses an efficient address decoder val mask = if (safe) ~BigInt(0) else AddressDecoder(supportCases.map(_._2)) // Simplified creates the most concise possible representation of each cases' address sets based on the mask. val simplified = supportCases.map { case (k, seq) => k -> AddressSet.unify(seq.map(_.widen(~mask)).distinct) } simplified.map { case (s, a) => // s is a size, you are checking for this size either the size of the operation is in s // We return an or-reduction of all the cases, checking whether any contains both the dynamic size and dynamic address on the wire. ((Some(s) == range).B || s.containsLg(lgSize)) && a.map(_.contains(address)).reduce(_||_) }.foldLeft(false.B)(_||_) } def supportsAcquireTSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.acquireT, address, lgSize, range) def supportsAcquireBSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.acquireB, address, lgSize, range) def supportsArithmeticSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.arithmetic, address, lgSize, range) def supportsLogicalSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.logical, address, lgSize, range) def supportsGetSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.get, address, lgSize, range) def supportsPutFullSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.putFull, address, lgSize, range) def supportsPutPartialSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.putPartial, address, lgSize, range) def supportsHintSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.hint, address, lgSize, range) def supportsAcquireTFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.acquireT, address, lgSize, range) def supportsAcquireBFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.acquireB, address, lgSize, range) def supportsArithmeticFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.arithmetic, address, lgSize, range) def supportsLogicalFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.logical, address, lgSize, range) def supportsGetFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.get, address, lgSize, range) def supportsPutFullFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.putFull, address, lgSize, range) def supportsPutPartialFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.putPartial, address, lgSize, range) def supportsHintFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.hint, address, lgSize, range) def emitsProbeSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.probe, address, lgSize, range) def emitsArithmeticSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.arithmetic, address, lgSize, range) def emitsLogicalSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.logical, address, lgSize, range) def emitsGetSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.get, address, lgSize, range) def emitsPutFullSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.putFull, address, lgSize, range) def emitsPutPartialSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.putPartial, address, lgSize, range) def emitsHintSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.hint, address, lgSize, range) def findTreeViolation() = slaves.flatMap(_.findTreeViolation()).headOption def isTree = !slaves.exists(!_.isTree) def infoString = "Slave Port Beatbytes = " + beatBytes + "\n" + "Slave Port MinLatency = " + minLatency + "\n\n" + slaves.map(_.infoString).mkString def v1copy( managers: Seq[TLSlaveParameters] = slaves, beatBytes: Int = -1, endSinkId: Int = endSinkId, minLatency: Int = minLatency, responseFields: Seq[BundleFieldBase] = responseFields, requestKeys: Seq[BundleKeyBase] = requestKeys) = { new TLSlavePortParameters( slaves = managers, channelBytes = if (beatBytes != -1) TLChannelBeatBytes(beatBytes) else channelBytes, endSinkId = endSinkId, minLatency = minLatency, responseFields = responseFields, requestKeys = requestKeys) } def v2copy( slaves: Seq[TLSlaveParameters] = slaves, channelBytes: TLChannelBeatBytes = channelBytes, endSinkId: Int = endSinkId, minLatency: Int = minLatency, responseFields: Seq[BundleFieldBase] = responseFields, requestKeys: Seq[BundleKeyBase] = requestKeys) = { new TLSlavePortParameters( slaves = slaves, channelBytes = channelBytes, endSinkId = endSinkId, minLatency = minLatency, responseFields = responseFields, requestKeys = requestKeys) } @deprecated("Use v1copy instead of copy","") def copy( managers: Seq[TLSlaveParameters] = slaves, beatBytes: Int = -1, endSinkId: Int = endSinkId, minLatency: Int = minLatency, responseFields: Seq[BundleFieldBase] = responseFields, requestKeys: Seq[BundleKeyBase] = requestKeys) = { v1copy( managers, beatBytes, endSinkId, minLatency, responseFields, requestKeys) } } object TLSlavePortParameters { def v1( managers: Seq[TLSlaveParameters], beatBytes: Int, endSinkId: Int = 0, minLatency: Int = 0, responseFields: Seq[BundleFieldBase] = Nil, requestKeys: Seq[BundleKeyBase] = Nil) = { new TLSlavePortParameters( slaves = managers, channelBytes = TLChannelBeatBytes(beatBytes), endSinkId = endSinkId, minLatency = minLatency, responseFields = responseFields, requestKeys = requestKeys) } } object TLManagerPortParameters { @deprecated("Use TLSlavePortParameters.v1 instead of TLManagerPortParameters","") def apply( managers: Seq[TLSlaveParameters], beatBytes: Int, endSinkId: Int = 0, minLatency: Int = 0, responseFields: Seq[BundleFieldBase] = Nil, requestKeys: Seq[BundleKeyBase] = Nil) = { TLSlavePortParameters.v1( managers, beatBytes, endSinkId, minLatency, responseFields, requestKeys) } } class TLMasterParameters private( val nodePath: Seq[BaseNode], val resources: Seq[Resource], val name: String, val visibility: Seq[AddressSet], val unusedRegionTypes: Set[RegionType.T], val executesOnly: Boolean, val requestFifo: Boolean, // only a request, not a requirement. applies to A, not C. val supports: TLSlaveToMasterTransferSizes, val emits: TLMasterToSlaveTransferSizes, val neverReleasesData: Boolean, val sourceId: IdRange) extends SimpleProduct { override def canEqual(that: Any): Boolean = that.isInstanceOf[TLMasterParameters] override def productPrefix = "TLMasterParameters" // We intentionally omit nodePath for equality testing / formatting def productArity: Int = 10 def productElement(n: Int): Any = n match { case 0 => name case 1 => sourceId case 2 => resources case 3 => visibility case 4 => unusedRegionTypes case 5 => executesOnly case 6 => requestFifo case 7 => supports case 8 => emits case 9 => neverReleasesData case _ => throw new IndexOutOfBoundsException(n.toString) } require (!sourceId.isEmpty) require (!visibility.isEmpty) require (supports.putFull.contains(supports.putPartial)) // We only support these operations if we support Probe (ie: we're a cache) require (supports.probe.contains(supports.arithmetic)) require (supports.probe.contains(supports.logical)) require (supports.probe.contains(supports.get)) require (supports.probe.contains(supports.putFull)) require (supports.probe.contains(supports.putPartial)) require (supports.probe.contains(supports.hint)) visibility.combinations(2).foreach { case Seq(x,y) => require (!x.overlaps(y), s"$x and $y overlap.") } val maxTransfer = List( supports.probe.max, supports.arithmetic.max, supports.logical.max, supports.get.max, supports.putFull.max, supports.putPartial.max).max def infoString = { s"""Master Name = ${name} |visibility = ${visibility} |emits = ${emits.infoString} |sourceId = ${sourceId} | |""".stripMargin } def v1copy( name: String = name, sourceId: IdRange = sourceId, nodePath: Seq[BaseNode] = nodePath, requestFifo: Boolean = requestFifo, visibility: Seq[AddressSet] = visibility, supportsProbe: TransferSizes = supports.probe, supportsArithmetic: TransferSizes = supports.arithmetic, supportsLogical: TransferSizes = supports.logical, supportsGet: TransferSizes = supports.get, supportsPutFull: TransferSizes = supports.putFull, supportsPutPartial: TransferSizes = supports.putPartial, supportsHint: TransferSizes = supports.hint) = { new TLMasterParameters( nodePath = nodePath, resources = this.resources, name = name, visibility = visibility, unusedRegionTypes = this.unusedRegionTypes, executesOnly = this.executesOnly, requestFifo = requestFifo, supports = TLSlaveToMasterTransferSizes( probe = supportsProbe, arithmetic = supportsArithmetic, logical = supportsLogical, get = supportsGet, putFull = supportsPutFull, putPartial = supportsPutPartial, hint = supportsHint), emits = this.emits, neverReleasesData = this.neverReleasesData, sourceId = sourceId) } def v2copy( nodePath: Seq[BaseNode] = nodePath, resources: Seq[Resource] = resources, name: String = name, visibility: Seq[AddressSet] = visibility, unusedRegionTypes: Set[RegionType.T] = unusedRegionTypes, executesOnly: Boolean = executesOnly, requestFifo: Boolean = requestFifo, supports: TLSlaveToMasterTransferSizes = supports, emits: TLMasterToSlaveTransferSizes = emits, neverReleasesData: Boolean = neverReleasesData, sourceId: IdRange = sourceId) = { new TLMasterParameters( nodePath = nodePath, resources = resources, name = name, visibility = visibility, unusedRegionTypes = unusedRegionTypes, executesOnly = executesOnly, requestFifo = requestFifo, supports = supports, emits = emits, neverReleasesData = neverReleasesData, sourceId = sourceId) } @deprecated("Use v1copy instead of copy","") def copy( name: String = name, sourceId: IdRange = sourceId, nodePath: Seq[BaseNode] = nodePath, requestFifo: Boolean = requestFifo, visibility: Seq[AddressSet] = visibility, supportsProbe: TransferSizes = supports.probe, supportsArithmetic: TransferSizes = supports.arithmetic, supportsLogical: TransferSizes = supports.logical, supportsGet: TransferSizes = supports.get, supportsPutFull: TransferSizes = supports.putFull, supportsPutPartial: TransferSizes = supports.putPartial, supportsHint: TransferSizes = supports.hint) = { v1copy( name = name, sourceId = sourceId, nodePath = nodePath, requestFifo = requestFifo, visibility = visibility, supportsProbe = supportsProbe, supportsArithmetic = supportsArithmetic, supportsLogical = supportsLogical, supportsGet = supportsGet, supportsPutFull = supportsPutFull, supportsPutPartial = supportsPutPartial, supportsHint = supportsHint) } } object TLMasterParameters { def v1( name: String, sourceId: IdRange = IdRange(0,1), nodePath: Seq[BaseNode] = Seq(), requestFifo: Boolean = false, visibility: Seq[AddressSet] = Seq(AddressSet(0, ~0)), supportsProbe: TransferSizes = TransferSizes.none, supportsArithmetic: TransferSizes = TransferSizes.none, supportsLogical: TransferSizes = TransferSizes.none, supportsGet: TransferSizes = TransferSizes.none, supportsPutFull: TransferSizes = TransferSizes.none, supportsPutPartial: TransferSizes = TransferSizes.none, supportsHint: TransferSizes = TransferSizes.none) = { new TLMasterParameters( nodePath = nodePath, resources = Nil, name = name, visibility = visibility, unusedRegionTypes = Set(), executesOnly = false, requestFifo = requestFifo, supports = TLSlaveToMasterTransferSizes( probe = supportsProbe, arithmetic = supportsArithmetic, logical = supportsLogical, get = supportsGet, putFull = supportsPutFull, putPartial = supportsPutPartial, hint = supportsHint), emits = TLMasterToSlaveTransferSizes.unknownEmits, neverReleasesData = false, sourceId = sourceId) } def v2( nodePath: Seq[BaseNode] = Seq(), resources: Seq[Resource] = Nil, name: String, visibility: Seq[AddressSet] = Seq(AddressSet(0, ~0)), unusedRegionTypes: Set[RegionType.T] = Set(), executesOnly: Boolean = false, requestFifo: Boolean = false, supports: TLSlaveToMasterTransferSizes = TLSlaveToMasterTransferSizes.unknownSupports, emits: TLMasterToSlaveTransferSizes = TLMasterToSlaveTransferSizes.unknownEmits, neverReleasesData: Boolean = false, sourceId: IdRange = IdRange(0,1)) = { new TLMasterParameters( nodePath = nodePath, resources = resources, name = name, visibility = visibility, unusedRegionTypes = unusedRegionTypes, executesOnly = executesOnly, requestFifo = requestFifo, supports = supports, emits = emits, neverReleasesData = neverReleasesData, sourceId = sourceId) } } object TLClientParameters { @deprecated("Use TLMasterParameters.v1 instead of TLClientParameters","") def apply( name: String, sourceId: IdRange = IdRange(0,1), nodePath: Seq[BaseNode] = Seq(), requestFifo: Boolean = false, visibility: Seq[AddressSet] = Seq(AddressSet.everything), supportsProbe: TransferSizes = TransferSizes.none, supportsArithmetic: TransferSizes = TransferSizes.none, supportsLogical: TransferSizes = TransferSizes.none, supportsGet: TransferSizes = TransferSizes.none, supportsPutFull: TransferSizes = TransferSizes.none, supportsPutPartial: TransferSizes = TransferSizes.none, supportsHint: TransferSizes = TransferSizes.none) = { TLMasterParameters.v1( name = name, sourceId = sourceId, nodePath = nodePath, requestFifo = requestFifo, visibility = visibility, supportsProbe = supportsProbe, supportsArithmetic = supportsArithmetic, supportsLogical = supportsLogical, supportsGet = supportsGet, supportsPutFull = supportsPutFull, supportsPutPartial = supportsPutPartial, supportsHint = supportsHint) } } class TLMasterPortParameters private( val masters: Seq[TLMasterParameters], val channelBytes: TLChannelBeatBytes, val minLatency: Int, val echoFields: Seq[BundleFieldBase], val requestFields: Seq[BundleFieldBase], val responseKeys: Seq[BundleKeyBase]) extends SimpleProduct { override def canEqual(that: Any): Boolean = that.isInstanceOf[TLMasterPortParameters] override def productPrefix = "TLMasterPortParameters" def productArity: Int = 6 def productElement(n: Int): Any = n match { case 0 => masters case 1 => channelBytes case 2 => minLatency case 3 => echoFields case 4 => requestFields case 5 => responseKeys case _ => throw new IndexOutOfBoundsException(n.toString) } require (!masters.isEmpty) require (minLatency >= 0) def clients = masters // Require disjoint ranges for Ids IdRange.overlaps(masters.map(_.sourceId)).foreach { case (x, y) => require (!x.overlaps(y), s"TLClientParameters.sourceId ${x} overlaps ${y}") } // Bounds on required sizes def endSourceId = masters.map(_.sourceId.end).max def maxTransfer = masters.map(_.maxTransfer).max // The unused sources < endSourceId def unusedSources: Seq[Int] = { val usedSources = masters.map(_.sourceId).sortBy(_.start) ((Seq(0) ++ usedSources.map(_.end)) zip usedSources.map(_.start)) flatMap { case (end, start) => end until start } } // Diplomatically determined operation sizes emitted by all inward Masters // as opposed to emits* which generate circuitry to check which specific addresses val allEmitClaims = masters.map(_.emits).reduce( _ intersect _) // Diplomatically determined operation sizes Emitted by at least one inward Masters // as opposed to emits* which generate circuitry to check which specific addresses val anyEmitClaims = masters.map(_.emits).reduce(_ mincover _) // Diplomatically determined operation sizes supported by all inward Masters // as opposed to supports* which generate circuitry to check which specific addresses val allSupportProbe = masters.map(_.supports.probe) .reduce(_ intersect _) val allSupportArithmetic = masters.map(_.supports.arithmetic).reduce(_ intersect _) val allSupportLogical = masters.map(_.supports.logical) .reduce(_ intersect _) val allSupportGet = masters.map(_.supports.get) .reduce(_ intersect _) val allSupportPutFull = masters.map(_.supports.putFull) .reduce(_ intersect _) val allSupportPutPartial = masters.map(_.supports.putPartial).reduce(_ intersect _) val allSupportHint = masters.map(_.supports.hint) .reduce(_ intersect _) // Diplomatically determined operation sizes supported by at least one master // as opposed to supports* which generate circuitry to check which specific addresses val anySupportProbe = masters.map(!_.supports.probe.none) .reduce(_ || _) val anySupportArithmetic = masters.map(!_.supports.arithmetic.none).reduce(_ || _) val anySupportLogical = masters.map(!_.supports.logical.none) .reduce(_ || _) val anySupportGet = masters.map(!_.supports.get.none) .reduce(_ || _) val anySupportPutFull = masters.map(!_.supports.putFull.none) .reduce(_ || _) val anySupportPutPartial = masters.map(!_.supports.putPartial.none).reduce(_ || _) val anySupportHint = masters.map(!_.supports.hint.none) .reduce(_ || _) // These return Option[TLMasterParameters] for your convenience def find(id: Int) = masters.find(_.sourceId.contains(id)) // Synthesizable lookup methods def find(id: UInt) = VecInit(masters.map(_.sourceId.contains(id))) def contains(id: UInt) = find(id).reduce(_ || _) def requestFifo(id: UInt) = Mux1H(find(id), masters.map(c => c.requestFifo.B)) // Available during RTL runtime, checks to see if (id, size) is supported by the master's (client's) diplomatic parameters private def sourceIdHelper(member: TLMasterParameters => TransferSizes)(id: UInt, lgSize: UInt) = { val allSame = masters.map(member(_) == member(masters(0))).reduce(_ && _) // this if statement is a coarse generalization of the groupBy in the sourceIdHelper2 version; // the case where there is only one group. if (allSame) member(masters(0)).containsLg(lgSize) else { // Find the master associated with ID and returns whether that particular master is able to receive transaction of lgSize Mux1H(find(id), masters.map(member(_).containsLg(lgSize))) } } // Check for support of a given operation at a specific id val supportsProbe = sourceIdHelper(_.supports.probe) _ val supportsArithmetic = sourceIdHelper(_.supports.arithmetic) _ val supportsLogical = sourceIdHelper(_.supports.logical) _ val supportsGet = sourceIdHelper(_.supports.get) _ val supportsPutFull = sourceIdHelper(_.supports.putFull) _ val supportsPutPartial = sourceIdHelper(_.supports.putPartial) _ val supportsHint = sourceIdHelper(_.supports.hint) _ // TODO: Merge sourceIdHelper2 with sourceIdHelper private def sourceIdHelper2( member: TLMasterParameters => TransferSizes, sourceId: UInt, lgSize: UInt): Bool = { // Because sourceIds are uniquely owned by each master, we use them to group the // cases that have to be checked. val emitCases = groupByIntoSeq(masters)(m => member(m)).map { case (k, vs) => k -> vs.map(_.sourceId) } emitCases.map { case (s, a) => (s.containsLg(lgSize)) && a.map(_.contains(sourceId)).reduce(_||_) }.foldLeft(false.B)(_||_) } // Check for emit of a given operation at a specific id def emitsAcquireT (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.acquireT, sourceId, lgSize) def emitsAcquireB (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.acquireB, sourceId, lgSize) def emitsArithmetic(sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.arithmetic, sourceId, lgSize) def emitsLogical (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.logical, sourceId, lgSize) def emitsGet (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.get, sourceId, lgSize) def emitsPutFull (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.putFull, sourceId, lgSize) def emitsPutPartial(sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.putPartial, sourceId, lgSize) def emitsHint (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.hint, sourceId, lgSize) def infoString = masters.map(_.infoString).mkString def v1copy( clients: Seq[TLMasterParameters] = masters, minLatency: Int = minLatency, echoFields: Seq[BundleFieldBase] = echoFields, requestFields: Seq[BundleFieldBase] = requestFields, responseKeys: Seq[BundleKeyBase] = responseKeys) = { new TLMasterPortParameters( masters = clients, channelBytes = channelBytes, minLatency = minLatency, echoFields = echoFields, requestFields = requestFields, responseKeys = responseKeys) } def v2copy( masters: Seq[TLMasterParameters] = masters, channelBytes: TLChannelBeatBytes = channelBytes, minLatency: Int = minLatency, echoFields: Seq[BundleFieldBase] = echoFields, requestFields: Seq[BundleFieldBase] = requestFields, responseKeys: Seq[BundleKeyBase] = responseKeys) = { new TLMasterPortParameters( masters = masters, channelBytes = channelBytes, minLatency = minLatency, echoFields = echoFields, requestFields = requestFields, responseKeys = responseKeys) } @deprecated("Use v1copy instead of copy","") def copy( clients: Seq[TLMasterParameters] = masters, minLatency: Int = minLatency, echoFields: Seq[BundleFieldBase] = echoFields, requestFields: Seq[BundleFieldBase] = requestFields, responseKeys: Seq[BundleKeyBase] = responseKeys) = { v1copy( clients, minLatency, echoFields, requestFields, responseKeys) } } object TLClientPortParameters { @deprecated("Use TLMasterPortParameters.v1 instead of TLClientPortParameters","") def apply( clients: Seq[TLMasterParameters], minLatency: Int = 0, echoFields: Seq[BundleFieldBase] = Nil, requestFields: Seq[BundleFieldBase] = Nil, responseKeys: Seq[BundleKeyBase] = Nil) = { TLMasterPortParameters.v1( clients, minLatency, echoFields, requestFields, responseKeys) } } object TLMasterPortParameters { def v1( clients: Seq[TLMasterParameters], minLatency: Int = 0, echoFields: Seq[BundleFieldBase] = Nil, requestFields: Seq[BundleFieldBase] = Nil, responseKeys: Seq[BundleKeyBase] = Nil) = { new TLMasterPortParameters( masters = clients, channelBytes = TLChannelBeatBytes(), minLatency = minLatency, echoFields = echoFields, requestFields = requestFields, responseKeys = responseKeys) } def v2( masters: Seq[TLMasterParameters], channelBytes: TLChannelBeatBytes = TLChannelBeatBytes(), minLatency: Int = 0, echoFields: Seq[BundleFieldBase] = Nil, requestFields: Seq[BundleFieldBase] = Nil, responseKeys: Seq[BundleKeyBase] = Nil) = { new TLMasterPortParameters( masters = masters, channelBytes = channelBytes, minLatency = minLatency, echoFields = echoFields, requestFields = requestFields, responseKeys = responseKeys) } } case class TLBundleParameters( addressBits: Int, dataBits: Int, sourceBits: Int, sinkBits: Int, sizeBits: Int, echoFields: Seq[BundleFieldBase], requestFields: Seq[BundleFieldBase], responseFields: Seq[BundleFieldBase], hasBCE: Boolean) { // Chisel has issues with 0-width wires require (addressBits >= 1) require (dataBits >= 8) require (sourceBits >= 1) require (sinkBits >= 1) require (sizeBits >= 1) require (isPow2(dataBits)) echoFields.foreach { f => require (f.key.isControl, s"${f} is not a legal echo field") } val addrLoBits = log2Up(dataBits/8) // Used to uniquify bus IP names def shortName = s"a${addressBits}d${dataBits}s${sourceBits}k${sinkBits}z${sizeBits}" + (if (hasBCE) "c" else "u") def union(x: TLBundleParameters) = TLBundleParameters( max(addressBits, x.addressBits), max(dataBits, x.dataBits), max(sourceBits, x.sourceBits), max(sinkBits, x.sinkBits), max(sizeBits, x.sizeBits), echoFields = BundleField.union(echoFields ++ x.echoFields), requestFields = BundleField.union(requestFields ++ x.requestFields), responseFields = BundleField.union(responseFields ++ x.responseFields), hasBCE || x.hasBCE) } object TLBundleParameters { val emptyBundleParams = TLBundleParameters( addressBits = 1, dataBits = 8, sourceBits = 1, sinkBits = 1, sizeBits = 1, echoFields = Nil, requestFields = Nil, responseFields = Nil, hasBCE = false) def union(x: Seq[TLBundleParameters]) = x.foldLeft(emptyBundleParams)((x,y) => x.union(y)) def apply(master: TLMasterPortParameters, slave: TLSlavePortParameters) = new TLBundleParameters( addressBits = log2Up(slave.maxAddress + 1), dataBits = slave.beatBytes * 8, sourceBits = log2Up(master.endSourceId), sinkBits = log2Up(slave.endSinkId), sizeBits = log2Up(log2Ceil(max(master.maxTransfer, slave.maxTransfer))+1), echoFields = master.echoFields, requestFields = BundleField.accept(master.requestFields, slave.requestKeys), responseFields = BundleField.accept(slave.responseFields, master.responseKeys), hasBCE = master.anySupportProbe && slave.anySupportAcquireB) } case class TLEdgeParameters( master: TLMasterPortParameters, slave: TLSlavePortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge { // legacy names: def manager = slave def client = master val maxTransfer = max(master.maxTransfer, slave.maxTransfer) val maxLgSize = log2Ceil(maxTransfer) // Sanity check the link... require (maxTransfer >= slave.beatBytes, s"Link's max transfer (${maxTransfer}) < ${slave.slaves.map(_.name)}'s beatBytes (${slave.beatBytes})") def diplomaticClaimsMasterToSlave = master.anyEmitClaims.intersect(slave.anySupportClaims) val bundle = TLBundleParameters(master, slave) def formatEdge = master.infoString + "\n" + slave.infoString } case class TLCreditedDelay( a: CreditedDelay, b: CreditedDelay, c: CreditedDelay, d: CreditedDelay, e: CreditedDelay) { def + (that: TLCreditedDelay): TLCreditedDelay = TLCreditedDelay( a = a + that.a, b = b + that.b, c = c + that.c, d = d + that.d, e = e + that.e) override def toString = s"(${a}, ${b}, ${c}, ${d}, ${e})" } object TLCreditedDelay { def apply(delay: CreditedDelay): TLCreditedDelay = apply(delay, delay.flip, delay, delay.flip, delay) } case class TLCreditedManagerPortParameters(delay: TLCreditedDelay, base: TLSlavePortParameters) {def infoString = base.infoString} case class TLCreditedClientPortParameters(delay: TLCreditedDelay, base: TLMasterPortParameters) {def infoString = base.infoString} case class TLCreditedEdgeParameters(client: TLCreditedClientPortParameters, manager: TLCreditedManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge { val delay = client.delay + manager.delay val bundle = TLBundleParameters(client.base, manager.base) def formatEdge = client.infoString + "\n" + manager.infoString } case class TLAsyncManagerPortParameters(async: AsyncQueueParams, base: TLSlavePortParameters) {def infoString = base.infoString} case class TLAsyncClientPortParameters(base: TLMasterPortParameters) {def infoString = base.infoString} case class TLAsyncBundleParameters(async: AsyncQueueParams, base: TLBundleParameters) case class TLAsyncEdgeParameters(client: TLAsyncClientPortParameters, manager: TLAsyncManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge { val bundle = TLAsyncBundleParameters(manager.async, TLBundleParameters(client.base, manager.base)) def formatEdge = client.infoString + "\n" + manager.infoString } case class TLRationalManagerPortParameters(direction: RationalDirection, base: TLSlavePortParameters) {def infoString = base.infoString} case class TLRationalClientPortParameters(base: TLMasterPortParameters) {def infoString = base.infoString} case class TLRationalEdgeParameters(client: TLRationalClientPortParameters, manager: TLRationalManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge { val bundle = TLBundleParameters(client.base, manager.base) def formatEdge = client.infoString + "\n" + manager.infoString } // To be unified, devices must agree on all of these terms case class ManagerUnificationKey( resources: Seq[Resource], regionType: RegionType.T, executable: Boolean, supportsAcquireT: TransferSizes, supportsAcquireB: TransferSizes, supportsArithmetic: TransferSizes, supportsLogical: TransferSizes, supportsGet: TransferSizes, supportsPutFull: TransferSizes, supportsPutPartial: TransferSizes, supportsHint: TransferSizes) object ManagerUnificationKey { def apply(x: TLSlaveParameters): ManagerUnificationKey = ManagerUnificationKey( resources = x.resources, regionType = x.regionType, executable = x.executable, supportsAcquireT = x.supportsAcquireT, supportsAcquireB = x.supportsAcquireB, supportsArithmetic = x.supportsArithmetic, supportsLogical = x.supportsLogical, supportsGet = x.supportsGet, supportsPutFull = x.supportsPutFull, supportsPutPartial = x.supportsPutPartial, supportsHint = x.supportsHint) } object ManagerUnification { def apply(slaves: Seq[TLSlaveParameters]): List[TLSlaveParameters] = { slaves.groupBy(ManagerUnificationKey.apply).values.map { seq => val agree = seq.forall(_.fifoId == seq.head.fifoId) seq(0).v1copy( address = AddressSet.unify(seq.flatMap(_.address)), fifoId = if (agree) seq(0).fifoId else None) }.toList } } case class TLBufferParams( a: BufferParams = BufferParams.none, b: BufferParams = BufferParams.none, c: BufferParams = BufferParams.none, d: BufferParams = BufferParams.none, e: BufferParams = BufferParams.none ) extends DirectedBuffers[TLBufferParams] { def copyIn(x: BufferParams) = this.copy(b = x, d = x) def copyOut(x: BufferParams) = this.copy(a = x, c = x, e = x) def copyInOut(x: BufferParams) = this.copyIn(x).copyOut(x) } /** Pretty printing of TL source id maps */ class TLSourceIdMap(tl: TLMasterPortParameters) extends IdMap[TLSourceIdMapEntry] { private val tlDigits = String.valueOf(tl.endSourceId-1).length() protected val fmt = s"\t[%${tlDigits}d, %${tlDigits}d) %s%s%s" private val sorted = tl.masters.sortBy(_.sourceId) val mapping: Seq[TLSourceIdMapEntry] = sorted.map { case c => TLSourceIdMapEntry(c.sourceId, c.name, c.supports.probe, c.requestFifo) } } case class TLSourceIdMapEntry(tlId: IdRange, name: String, isCache: Boolean, requestFifo: Boolean) extends IdMapEntry { val from = tlId val to = tlId val maxTransactionsInFlight = Some(tlId.size) } File MixedNode.scala: package org.chipsalliance.diplomacy.nodes import chisel3.{Data, DontCare, Wire} import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.{Field, Parameters} import org.chipsalliance.diplomacy.ValName import org.chipsalliance.diplomacy.sourceLine /** One side metadata of a [[Dangle]]. * * Describes one side of an edge going into or out of a [[BaseNode]]. * * @param serial * the global [[BaseNode.serial]] number of the [[BaseNode]] that this [[HalfEdge]] connects to. * @param index * the `index` in the [[BaseNode]]'s input or output port list that this [[HalfEdge]] belongs to. */ case class HalfEdge(serial: Int, index: Int) extends Ordered[HalfEdge] { import scala.math.Ordered.orderingToOrdered def compare(that: HalfEdge): Int = HalfEdge.unapply(this).compare(HalfEdge.unapply(that)) } /** [[Dangle]] captures the `IO` information of a [[LazyModule]] and which two [[BaseNode]]s the [[Edges]]/[[Bundle]] * connects. * * [[Dangle]]s are generated by [[BaseNode.instantiate]] using [[MixedNode.danglesOut]] and [[MixedNode.danglesIn]] , * [[LazyModuleImp.instantiate]] connects those that go to internal or explicit IO connections in a [[LazyModule]]. * * @param source * the source [[HalfEdge]] of this [[Dangle]], which captures the source [[BaseNode]] and the port `index` within * that [[BaseNode]]. * @param sink * sink [[HalfEdge]] of this [[Dangle]], which captures the sink [[BaseNode]] and the port `index` within that * [[BaseNode]]. * @param flipped * flip or not in [[AutoBundle.makeElements]]. If true this corresponds to `danglesOut`, if false it corresponds to * `danglesIn`. * @param dataOpt * actual [[Data]] for the hardware connection. Can be empty if this belongs to a cloned module */ case class Dangle(source: HalfEdge, sink: HalfEdge, flipped: Boolean, name: String, dataOpt: Option[Data]) { def data = dataOpt.get } /** [[Edges]] is a collection of parameters describing the functionality and connection for an interface, which is often * derived from the interconnection protocol and can inform the parameterization of the hardware bundles that actually * implement the protocol. */ case class Edges[EI, EO](in: Seq[EI], out: Seq[EO]) /** A field available in [[Parameters]] used to determine whether [[InwardNodeImp.monitor]] will be called. */ case object MonitorsEnabled extends Field[Boolean](true) /** When rendering the edge in a graphical format, flip the order in which the edges' source and sink are presented. * * For example, when rendering graphML, yEd by default tries to put the source node vertically above the sink node, but * [[RenderFlipped]] inverts this relationship. When a particular [[LazyModule]] contains both source nodes and sink * nodes, flipping the rendering of one node's edge will usual produce a more concise visual layout for the * [[LazyModule]]. */ case object RenderFlipped extends Field[Boolean](false) /** The sealed node class in the package, all node are derived from it. * * @param inner * Sink interface implementation. * @param outer * Source interface implementation. * @param valName * val name of this node. * @tparam DI * Downward-flowing parameters received on the inner side of the node. It is usually a brunch of parameters * describing the protocol parameters from a source. For an [[InwardNode]], it is determined by the connected * [[OutwardNode]]. Since it can be connected to multiple sources, this parameter is always a Seq of source port * parameters. * @tparam UI * Upward-flowing parameters generated by the inner side of the node. It is usually a brunch of parameters describing * the protocol parameters of a sink. For an [[InwardNode]], it is determined itself. * @tparam EI * Edge Parameters describing a connection on the inner side of the node. It is usually a brunch of transfers * specified for a sink according to protocol. * @tparam BI * Bundle type used when connecting to the inner side of the node. It is a hardware interface of this sink interface. * It should extends from [[chisel3.Data]], which represents the real hardware. * @tparam DO * Downward-flowing parameters generated on the outer side of the node. It is usually a brunch of parameters * describing the protocol parameters of a source. For an [[OutwardNode]], it is determined itself. * @tparam UO * Upward-flowing parameters received by the outer side of the node. It is usually a brunch of parameters describing * the protocol parameters from a sink. For an [[OutwardNode]], it is determined by the connected [[InwardNode]]. * Since it can be connected to multiple sinks, this parameter is always a Seq of sink port parameters. * @tparam EO * Edge Parameters describing a connection on the outer side of the node. It is usually a brunch of transfers * specified for a source according to protocol. * @tparam BO * Bundle type used when connecting to the outer side of the node. It is a hardware interface of this source * interface. It should extends from [[chisel3.Data]], which represents the real hardware. * * @note * Call Graph of [[MixedNode]] * - line `─`: source is process by a function and generate pass to others * - Arrow `→`: target of arrow is generated by source * * {{{ * (from the other node) * ┌─────────────────────────────────────────────────────────[[InwardNode.uiParams]]─────────────┐ * ↓ │ * (binding node when elaboration) [[OutwardNode.uoParams]]────────────────────────[[MixedNode.mapParamsU]]→──────────┐ │ * [[InwardNode.accPI]] │ │ │ * │ │ (based on protocol) │ * │ │ [[MixedNode.inner.edgeI]] │ * │ │ ↓ │ * ↓ │ │ │ * (immobilize after elaboration) (inward port from [[OutwardNode]]) │ ↓ │ * [[InwardNode.iBindings]]──┐ [[MixedNode.iDirectPorts]]────────────────────→[[MixedNode.iPorts]] [[InwardNode.uiParams]] │ * │ │ ↑ │ │ │ * │ │ │ [[OutwardNode.doParams]] │ │ * │ │ │ (from the other node) │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * │ │ │ └────────┬──────────────┤ │ * │ │ │ │ │ │ * │ │ │ │ (based on protocol) │ * │ │ │ │ [[MixedNode.inner.edgeI]] │ * │ │ │ │ │ │ * │ │ (from the other node) │ ↓ │ * │ └───[[OutwardNode.oPortMapping]] [[OutwardNode.oStar]] │ [[MixedNode.edgesIn]]───┐ │ * │ ↑ ↑ │ │ ↓ │ * │ │ │ │ │ [[MixedNode.in]] │ * │ │ │ │ ↓ ↑ │ * │ (solve star connection) │ │ │ [[MixedNode.bundleIn]]──┘ │ * ├───[[MixedNode.resolveStar]]→─┼─────────────────────────────┤ └────────────────────────────────────┐ │ * │ │ │ [[MixedNode.bundleOut]]─┐ │ │ * │ │ │ ↑ ↓ │ │ * │ │ │ │ [[MixedNode.out]] │ │ * │ ↓ ↓ │ ↑ │ │ * │ ┌─────[[InwardNode.iPortMapping]] [[InwardNode.iStar]] [[MixedNode.edgesOut]]──┘ │ │ * │ │ (from the other node) ↑ │ │ * │ │ │ │ │ │ * │ │ │ [[MixedNode.outer.edgeO]] │ │ * │ │ │ (based on protocol) │ │ * │ │ │ │ │ │ * │ │ │ ┌────────────────────────────────────────┤ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * (immobilize after elaboration)│ ↓ │ │ │ │ * [[OutwardNode.oBindings]]─┘ [[MixedNode.oDirectPorts]]───→[[MixedNode.oPorts]] [[OutwardNode.doParams]] │ │ * ↑ (inward port from [[OutwardNode]]) │ │ │ │ * │ ┌─────────────────────────────────────────┤ │ │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * [[OutwardNode.accPO]] │ ↓ │ │ │ * (binding node when elaboration) │ [[InwardNode.diParams]]─────→[[MixedNode.mapParamsD]]────────────────────────────┘ │ │ * │ ↑ │ │ * │ └──────────────────────────────────────────────────────────────────────────────────────────┘ │ * └──────────────────────────────────────────────────────────────────────────────────────────────────────────┘ * }}} */ abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data]( val inner: InwardNodeImp[DI, UI, EI, BI], val outer: OutwardNodeImp[DO, UO, EO, BO] )( implicit valName: ValName) extends BaseNode with NodeHandle[DI, UI, EI, BI, DO, UO, EO, BO] with InwardNode[DI, UI, BI] with OutwardNode[DO, UO, BO] { // Generate a [[NodeHandle]] with inward and outward node are both this node. val inward = this val outward = this /** Debug info of nodes binding. */ def bindingInfo: String = s"""$iBindingInfo |$oBindingInfo |""".stripMargin /** Debug info of ports connecting. */ def connectedPortsInfo: String = s"""${oPorts.size} outward ports connected: [${oPorts.map(_._2.name).mkString(",")}] |${iPorts.size} inward ports connected: [${iPorts.map(_._2.name).mkString(",")}] |""".stripMargin /** Debug info of parameters propagations. */ def parametersInfo: String = s"""${doParams.size} downstream outward parameters: [${doParams.mkString(",")}] |${uoParams.size} upstream outward parameters: [${uoParams.mkString(",")}] |${diParams.size} downstream inward parameters: [${diParams.mkString(",")}] |${uiParams.size} upstream inward parameters: [${uiParams.mkString(",")}] |""".stripMargin /** For a given node, converts [[OutwardNode.accPO]] and [[InwardNode.accPI]] to [[MixedNode.oPortMapping]] and * [[MixedNode.iPortMapping]]. * * Given counts of known inward and outward binding and inward and outward star bindings, return the resolved inward * stars and outward stars. * * This method will also validate the arguments and throw a runtime error if the values are unsuitable for this type * of node. * * @param iKnown * Number of known-size ([[BIND_ONCE]]) input bindings. * @param oKnown * Number of known-size ([[BIND_ONCE]]) output bindings. * @param iStar * Number of unknown size ([[BIND_STAR]]) input bindings. * @param oStar * Number of unknown size ([[BIND_STAR]]) output bindings. * @return * A Tuple of the resolved number of input and output connections. */ protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStar: Int, oStar: Int): (Int, Int) /** Function to generate downward-flowing outward params from the downward-flowing input params and the current output * ports. * * @param n * The size of the output sequence to generate. * @param p * Sequence of downward-flowing input parameters of this node. * @return * A `n`-sized sequence of downward-flowing output edge parameters. */ protected[diplomacy] def mapParamsD(n: Int, p: Seq[DI]): Seq[DO] /** Function to generate upward-flowing input parameters from the upward-flowing output parameters [[uiParams]]. * * @param n * Size of the output sequence. * @param p * Upward-flowing output edge parameters. * @return * A n-sized sequence of upward-flowing input edge parameters. */ protected[diplomacy] def mapParamsU(n: Int, p: Seq[UO]): Seq[UI] /** @return * The sink cardinality of the node, the number of outputs bound with [[BIND_QUERY]] summed with inputs bound with * [[BIND_STAR]]. */ protected[diplomacy] lazy val sinkCard: Int = oBindings.count(_._3 == BIND_QUERY) + iBindings.count(_._3 == BIND_STAR) /** @return * The source cardinality of this node, the number of inputs bound with [[BIND_QUERY]] summed with the number of * output bindings bound with [[BIND_STAR]]. */ protected[diplomacy] lazy val sourceCard: Int = iBindings.count(_._3 == BIND_QUERY) + oBindings.count(_._3 == BIND_STAR) /** @return list of nodes involved in flex bindings with this node. */ protected[diplomacy] lazy val flexes: Seq[BaseNode] = oBindings.filter(_._3 == BIND_FLEX).map(_._2) ++ iBindings.filter(_._3 == BIND_FLEX).map(_._2) /** Resolves the flex to be either source or sink and returns the offset where the [[BIND_STAR]] operators begin * greedily taking up the remaining connections. * * @return * A value >= 0 if it is sink cardinality, a negative value for source cardinality. The magnitude of the return * value is not relevant. */ protected[diplomacy] lazy val flexOffset: Int = { /** Recursively performs a depth-first search of the [[flexes]], [[BaseNode]]s connected to this node with flex * operators. The algorithm bottoms out when we either get to a node we have already visited or when we get to a * connection that is not a flex and can set the direction for us. Otherwise, recurse by visiting the `flexes` of * each node in the current set and decide whether they should be added to the set or not. * * @return * the mapping of [[BaseNode]] indexed by their serial numbers. */ def DFS(v: BaseNode, visited: Map[Int, BaseNode]): Map[Int, BaseNode] = { if (visited.contains(v.serial) || !v.flexibleArityDirection) { visited } else { v.flexes.foldLeft(visited + (v.serial -> v))((sum, n) => DFS(n, sum)) } } /** Determine which [[BaseNode]] are involved in resolving the flex connections to/from this node. * * @example * {{{ * a :*=* b :*=* c * d :*=* b * e :*=* f * }}} * * `flexSet` for `a`, `b`, `c`, or `d` will be `Set(a, b, c, d)` `flexSet` for `e` or `f` will be `Set(e,f)` */ val flexSet = DFS(this, Map()).values /** The total number of :*= operators where we're on the left. */ val allSink = flexSet.map(_.sinkCard).sum /** The total number of :=* operators used when we're on the right. */ val allSource = flexSet.map(_.sourceCard).sum require( allSink == 0 || allSource == 0, s"The nodes ${flexSet.map(_.name)} which are inter-connected by :*=* have ${allSink} :*= operators and ${allSource} :=* operators connected to them, making it impossible to determine cardinality inference direction." ) allSink - allSource } /** @return A value >= 0 if it is sink cardinality, a negative value for source cardinality. */ protected[diplomacy] def edgeArityDirection(n: BaseNode): Int = { if (flexibleArityDirection) flexOffset else if (n.flexibleArityDirection) n.flexOffset else 0 } /** For a node which is connected between two nodes, select the one that will influence the direction of the flex * resolution. */ protected[diplomacy] def edgeAritySelect(n: BaseNode, l: => Int, r: => Int): Int = { val dir = edgeArityDirection(n) if (dir < 0) l else if (dir > 0) r else 1 } /** Ensure that the same node is not visited twice in resolving `:*=`, etc operators. */ private var starCycleGuard = false /** Resolve all the star operators into concrete indicies. As connections are being made, some may be "star" * connections which need to be resolved. In some way to determine how many actual edges they correspond to. We also * need to build up the ranges of edges which correspond to each binding operator, so that We can apply the correct * edge parameters and later build up correct bundle connections. * * [[oPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that oPort (binding * operator). [[iPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that iPort * (binding operator). [[oStar]]: `Int` the value to return for this node `N` for any `N :*= foo` or `N :*=* foo :*= * bar` [[iStar]]: `Int` the value to return for this node `N` for any `foo :=* N` or `bar :=* foo :*=* N` */ protected[diplomacy] lazy val ( oPortMapping: Seq[(Int, Int)], iPortMapping: Seq[(Int, Int)], oStar: Int, iStar: Int ) = { try { if (starCycleGuard) throw StarCycleException() starCycleGuard = true // For a given node N... // Number of foo :=* N // + Number of bar :=* foo :*=* N val oStars = oBindings.count { case (_, n, b, _, _) => b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) < 0) } // Number of N :*= foo // + Number of N :*=* foo :*= bar val iStars = iBindings.count { case (_, n, b, _, _) => b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) > 0) } // 1 for foo := N // + bar.iStar for bar :*= foo :*=* N // + foo.iStar for foo :*= N // + 0 for foo :=* N val oKnown = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, 0, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => 0 } }.sum // 1 for N := foo // + bar.oStar for N :*=* foo :=* bar // + foo.oStar for N :=* foo // + 0 for N :*= foo val iKnown = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, 0) case BIND_QUERY => n.oStar case BIND_STAR => 0 } }.sum // Resolve star depends on the node subclass to implement the algorithm for this. val (iStar, oStar) = resolveStar(iKnown, oKnown, iStars, oStars) // Cumulative list of resolved outward binding range starting points val oSum = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, oStar, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => oStar } }.scanLeft(0)(_ + _) // Cumulative list of resolved inward binding range starting points val iSum = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, iStar) case BIND_QUERY => n.oStar case BIND_STAR => iStar } }.scanLeft(0)(_ + _) // Create ranges for each binding based on the running sums and return // those along with resolved values for the star operations. (oSum.init.zip(oSum.tail), iSum.init.zip(iSum.tail), oStar, iStar) } catch { case c: StarCycleException => throw c.copy(loop = context +: c.loop) } } /** Sequence of inward ports. * * This should be called after all star bindings are resolved. * * Each element is: `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. * `n` Instance of inward node. `p` View of [[Parameters]] where this connection was made. `s` Source info where this * connection was made in the source code. */ protected[diplomacy] lazy val oDirectPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oBindings.flatMap { case (i, n, _, p, s) => // for each binding operator in this node, look at what it connects to val (start, end) = n.iPortMapping(i) (start until end).map { j => (j, n, p, s) } } /** Sequence of outward ports. * * This should be called after all star bindings are resolved. * * `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. `n` Instance of * outward node. `p` View of [[Parameters]] where this connection was made. `s` [[SourceInfo]] where this connection * was made in the source code. */ protected[diplomacy] lazy val iDirectPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iBindings.flatMap { case (i, n, _, p, s) => // query this port index range of this node in the other side of node. val (start, end) = n.oPortMapping(i) (start until end).map { j => (j, n, p, s) } } // Ephemeral nodes ( which have non-None iForward/oForward) have in_degree = out_degree // Thus, there must exist an Eulerian path and the below algorithms terminate @scala.annotation.tailrec private def oTrace( tuple: (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) ): (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.iForward(i) match { case None => (i, n, p, s) case Some((j, m)) => oTrace((j, m, p, s)) } } @scala.annotation.tailrec private def iTrace( tuple: (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) ): (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.oForward(i) match { case None => (i, n, p, s) case Some((j, m)) => iTrace((j, m, p, s)) } } /** Final output ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - Numeric index of this binding in the [[InwardNode]] on the other end. * - [[InwardNode]] on the other end of this binding. * - A view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. */ lazy val oPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oDirectPorts.map(oTrace) /** Final input ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - numeric index of this binding in [[OutwardNode]] on the other end. * - [[OutwardNode]] on the other end of this binding. * - a view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. */ lazy val iPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iDirectPorts.map(iTrace) private var oParamsCycleGuard = false protected[diplomacy] lazy val diParams: Seq[DI] = iPorts.map { case (i, n, _, _) => n.doParams(i) } protected[diplomacy] lazy val doParams: Seq[DO] = { try { if (oParamsCycleGuard) throw DownwardCycleException() oParamsCycleGuard = true val o = mapParamsD(oPorts.size, diParams) require( o.size == oPorts.size, s"""Diplomacy has detected a problem with your graph: |At the following node, the number of outward ports should equal the number of produced outward parameters. |$context |$connectedPortsInfo |Downstreamed inward parameters: [${diParams.mkString(",")}] |Produced outward parameters: [${o.mkString(",")}] |""".stripMargin ) o.map(outer.mixO(_, this)) } catch { case c: DownwardCycleException => throw c.copy(loop = context +: c.loop) } } private var iParamsCycleGuard = false protected[diplomacy] lazy val uoParams: Seq[UO] = oPorts.map { case (o, n, _, _) => n.uiParams(o) } protected[diplomacy] lazy val uiParams: Seq[UI] = { try { if (iParamsCycleGuard) throw UpwardCycleException() iParamsCycleGuard = true val i = mapParamsU(iPorts.size, uoParams) require( i.size == iPorts.size, s"""Diplomacy has detected a problem with your graph: |At the following node, the number of inward ports should equal the number of produced inward parameters. |$context |$connectedPortsInfo |Upstreamed outward parameters: [${uoParams.mkString(",")}] |Produced inward parameters: [${i.mkString(",")}] |""".stripMargin ) i.map(inner.mixI(_, this)) } catch { case c: UpwardCycleException => throw c.copy(loop = context +: c.loop) } } /** Outward edge parameters. */ protected[diplomacy] lazy val edgesOut: Seq[EO] = (oPorts.zip(doParams)).map { case ((i, n, p, s), o) => outer.edgeO(o, n.uiParams(i), p, s) } /** Inward edge parameters. */ protected[diplomacy] lazy val edgesIn: Seq[EI] = (iPorts.zip(uiParams)).map { case ((o, n, p, s), i) => inner.edgeI(n.doParams(o), i, p, s) } /** A tuple of the input edge parameters and output edge parameters for the edges bound to this node. * * If you need to access to the edges of a foreign Node, use this method (in/out create bundles). */ lazy val edges: Edges[EI, EO] = Edges(edgesIn, edgesOut) /** Create actual Wires corresponding to the Bundles parameterized by the outward edges of this node. */ protected[diplomacy] lazy val bundleOut: Seq[BO] = edgesOut.map { e => val x = Wire(outer.bundleO(e)).suggestName(s"${valName.value}Out") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } /** Create actual Wires corresponding to the Bundles parameterized by the inward edges of this node. */ protected[diplomacy] lazy val bundleIn: Seq[BI] = edgesIn.map { e => val x = Wire(inner.bundleI(e)).suggestName(s"${valName.value}In") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } private def emptyDanglesOut: Seq[Dangle] = oPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(serial, i), sink = HalfEdge(n.serial, j), flipped = false, name = wirePrefix + "out", dataOpt = None ) } private def emptyDanglesIn: Seq[Dangle] = iPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(n.serial, j), sink = HalfEdge(serial, i), flipped = true, name = wirePrefix + "in", dataOpt = None ) } /** Create the [[Dangle]]s which describe the connections from this node output to other nodes inputs. */ protected[diplomacy] def danglesOut: Seq[Dangle] = emptyDanglesOut.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleOut(i))) } /** Create the [[Dangle]]s which describe the connections from this node input from other nodes outputs. */ protected[diplomacy] def danglesIn: Seq[Dangle] = emptyDanglesIn.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleIn(i))) } private[diplomacy] var instantiated = false /** Gather Bundle and edge parameters of outward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. */ def out: Seq[(BO, EO)] = { require( instantiated, s"$name.out should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleOut.zip(edgesOut) } /** Gather Bundle and edge parameters of inward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. */ def in: Seq[(BI, EI)] = { require( instantiated, s"$name.in should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleIn.zip(edgesIn) } /** Actually instantiate this node during [[LazyModuleImp]] evaluation. Mark that it's safe to use the Bundle wires, * instantiate monitors on all input ports if appropriate, and return all the dangles of this node. */ protected[diplomacy] def instantiate(): Seq[Dangle] = { instantiated = true if (!circuitIdentity) { (iPorts.zip(in)).foreach { case ((_, _, p, _), (b, e)) => if (p(MonitorsEnabled)) inner.monitor(b, e) } } danglesOut ++ danglesIn } protected[diplomacy] def cloneDangles(): Seq[Dangle] = emptyDanglesOut ++ emptyDanglesIn /** Connects the outward part of a node with the inward part of this node. */ protected[diplomacy] def bind( h: OutwardNode[DI, UI, BI], binding: NodeBinding )( implicit p: Parameters, sourceInfo: SourceInfo ): Unit = { val x = this // x := y val y = h sourceLine(sourceInfo, " at ", "") val i = x.iPushed val o = y.oPushed y.oPush( i, x, binding match { case BIND_ONCE => BIND_ONCE case BIND_FLEX => BIND_FLEX case BIND_STAR => BIND_QUERY case BIND_QUERY => BIND_STAR } ) x.iPush(o, y, binding) } /* Metadata for printing the node graph. */ def inputs: Seq[(OutwardNode[DI, UI, BI], RenderedEdge)] = (iPorts.zip(edgesIn)).map { case ((_, n, p, _), e) => val re = inner.render(e) (n, re.copy(flipped = re.flipped != p(RenderFlipped))) } /** Metadata for printing the node graph */ def outputs: Seq[(InwardNode[DO, UO, BO], RenderedEdge)] = oPorts.map { case (i, n, _, _) => (n, n.inputs(i)._2) } } File CustomBootPin.scala: package testchipip.boot import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config._ import freechips.rocketchip.diplomacy._ import freechips.rocketchip.tilelink._ import freechips.rocketchip.devices.tilelink._ import freechips.rocketchip.regmapper._ import freechips.rocketchip.subsystem._ case class CustomBootPinParams( customBootAddress: BigInt = 0x80000000L, // Default is DRAM_BASE masterWhere: TLBusWrapperLocation = CBUS // This needs to write to clint and bootaddrreg, which are on CBUS/PBUS ) case object CustomBootPinKey extends Field[Option[CustomBootPinParams]](None) trait CanHavePeripheryCustomBootPin { this: BaseSubsystem => val custom_boot_pin = p(CustomBootPinKey).map { params => require(p(BootAddrRegKey).isDefined, "CustomBootPin relies on existence of BootAddrReg") val tlbus = locateTLBusWrapper(params.masterWhere) val clientParams = TLMasterPortParameters.v1( clients = Seq(TLMasterParameters.v1( name = "custom-boot", sourceId = IdRange(0, 1), )), minLatency = 1 ) val inner_io = tlbus { val node = TLClientNode(Seq(clientParams)) tlbus.coupleFrom(s"port_named_custom_boot_pin") ({ _ := node }) InModuleBody { val custom_boot = IO(Input(Bool())).suggestName("custom_boot") val (tl, edge) = node.out(0) val inactive :: waiting_bootaddr_reg_a :: waiting_bootaddr_reg_d :: waiting_msip_a :: waiting_msip_d :: dead :: Nil = Enum(6) val state = RegInit(inactive) tl.a.valid := false.B tl.a.bits := DontCare tl.d.ready := true.B switch (state) { is (inactive) { when (custom_boot) { state := waiting_bootaddr_reg_a } } is (waiting_bootaddr_reg_a) { tl.a.valid := true.B tl.a.bits := edge.Put( toAddress = p(BootAddrRegKey).get.bootRegAddress.U, fromSource = 0.U, lgSize = 2.U, data = params.customBootAddress.U )._2 when (tl.a.fire) { state := waiting_bootaddr_reg_d } } is (waiting_bootaddr_reg_d) { when (tl.d.fire) { state := waiting_msip_a } } is (waiting_msip_a) { tl.a.valid := true.B tl.a.bits := edge.Put( toAddress = (p(CLINTKey).get.baseAddress + CLINTConsts.msipOffset(0)).U, // msip for hart0 fromSource = 0.U, lgSize = log2Ceil(CLINTConsts.msipBytes).U, data = 1.U )._2 when (tl.a.fire) { state := waiting_msip_d } } is (waiting_msip_d) { when (tl.d.fire) { state := dead } } is (dead) { when (!custom_boot) { state := inactive } } } custom_boot } } val outer_io = InModuleBody { val custom_boot = IO(Input(Bool())).suggestName("custom_boot") inner_io := custom_boot custom_boot } outer_io } } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) || !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.ProbeAckData || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode | small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U || beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } } File LazyScope.scala: package org.chipsalliance.diplomacy.lazymodule import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.ValName /** Allows dynamic creation of [[Module]] hierarchy and "shoving" logic into a [[LazyModule]]. */ trait LazyScope { this: LazyModule => override def toString: String = s"LazyScope named $name" /** Evaluate `body` in the current [[LazyModule.scope]] */ def apply[T](body: => T): T = { // Preserve the previous value of the [[LazyModule.scope]], because when calling [[apply]] function, // [[LazyModule.scope]] will be altered. val saved = LazyModule.scope // [[LazyModule.scope]] stack push. LazyModule.scope = Some(this) // Evaluate [[body]] in the current `scope`, saving the result to [[out]]. val out = body // Check that the `scope` after evaluating `body` is the same as when we started. require(LazyModule.scope.isDefined, s"LazyScope $name tried to exit, but scope was empty!") require( LazyModule.scope.get eq this, s"LazyScope $name exited before LazyModule ${LazyModule.scope.get.name} was closed" ) // [[LazyModule.scope]] stack pop. LazyModule.scope = saved out } } /** Used to automatically create a level of module hierarchy (a [[SimpleLazyModule]]) within which [[LazyModule]]s can * be instantiated and connected. * * It will instantiate a [[SimpleLazyModule]] to manage evaluation of `body` and evaluate `body` code snippets in this * scope. */ object LazyScope { /** Create a [[LazyScope]] with an implicit instance name. * * @param body * code executed within the generated [[SimpleLazyModule]]. * @param valName * instance name of generated [[SimpleLazyModule]]. * @param p * [[Parameters]] propagated to [[SimpleLazyModule]]. */ def apply[T]( body: => T )( implicit valName: ValName, p: Parameters ): T = { apply(valName.value, "SimpleLazyModule", None)(body)(p) } /** Create a [[LazyScope]] with an explicitly defined instance name. * * @param name * instance name of generated [[SimpleLazyModule]]. * @param body * code executed within the generated `SimpleLazyModule` * @param p * [[Parameters]] propagated to [[SimpleLazyModule]]. */ def apply[T]( name: String )(body: => T )( implicit p: Parameters ): T = { apply(name, "SimpleLazyModule", None)(body)(p) } /** Create a [[LazyScope]] with an explicit instance and class name, and control inlining. * * @param name * instance name of generated [[SimpleLazyModule]]. * @param desiredModuleName * class name of generated [[SimpleLazyModule]]. * @param overrideInlining * tell FIRRTL that this [[SimpleLazyModule]]'s module should be inlined. * @param body * code executed within the generated `SimpleLazyModule` * @param p * [[Parameters]] propagated to [[SimpleLazyModule]]. */ def apply[T]( name: String, desiredModuleName: String, overrideInlining: Option[Boolean] = None )(body: => T )( implicit p: Parameters ): T = { val scope = LazyModule(new SimpleLazyModule with LazyScope { override lazy val desiredName = desiredModuleName override def shouldBeInlined = overrideInlining.getOrElse(super.shouldBeInlined) }).suggestName(name) scope { body } } /** Create a [[LazyScope]] to temporarily group children for some reason, but tell Firrtl to inline it. * * For example, we might want to control a set of children's clocks but then not keep the parent wrapper. * * @param body * code executed within the generated `SimpleLazyModule` * @param p * [[Parameters]] propagated to [[SimpleLazyModule]]. */ def inline[T]( body: => T )( implicit p: Parameters ): T = { apply("noname", "ShouldBeInlined", Some(false))(body)(p) } }

module PeripheryBus_cbus( // @[ClockDomain.scala:14:9] input auto_coupler_to_prci_ctrl_fixer_anon_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_prci_ctrl_fixer_anon_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [2:0] auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [8:0] auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [20:0] auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_prci_ctrl_fixer_anon_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_coupler_to_prci_ctrl_fixer_anon_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_coupler_to_prci_ctrl_fixer_anon_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_coupler_to_prci_ctrl_fixer_anon_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [8:0] auto_coupler_to_prci_ctrl_fixer_anon_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input [63:0] auto_coupler_to_prci_ctrl_fixer_anon_out_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_coupler_to_bootrom_fragmenter_anon_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_bootrom_fragmenter_anon_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [1:0] auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [12:0] auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [16:0] auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_bootrom_fragmenter_anon_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_coupler_to_bootrom_fragmenter_anon_out_d_valid, // @[LazyModuleImp.scala:107:25] input [1:0] auto_coupler_to_bootrom_fragmenter_anon_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [12:0] auto_coupler_to_bootrom_fragmenter_anon_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input [63:0] auto_coupler_to_bootrom_fragmenter_anon_out_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_coupler_to_debug_fragmenter_anon_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_debug_fragmenter_anon_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_coupler_to_debug_fragmenter_anon_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_coupler_to_debug_fragmenter_anon_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [1:0] auto_coupler_to_debug_fragmenter_anon_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [12:0] auto_coupler_to_debug_fragmenter_anon_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [11:0] auto_coupler_to_debug_fragmenter_anon_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_coupler_to_debug_fragmenter_anon_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_coupler_to_debug_fragmenter_anon_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_debug_fragmenter_anon_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_debug_fragmenter_anon_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_coupler_to_debug_fragmenter_anon_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_coupler_to_debug_fragmenter_anon_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_coupler_to_debug_fragmenter_anon_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [12:0] auto_coupler_to_debug_fragmenter_anon_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input [63:0] auto_coupler_to_debug_fragmenter_anon_out_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_coupler_to_plic_fragmenter_anon_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_plic_fragmenter_anon_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_coupler_to_plic_fragmenter_anon_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_coupler_to_plic_fragmenter_anon_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [1:0] auto_coupler_to_plic_fragmenter_anon_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [12:0] auto_coupler_to_plic_fragmenter_anon_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [27:0] auto_coupler_to_plic_fragmenter_anon_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_coupler_to_plic_fragmenter_anon_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_coupler_to_plic_fragmenter_anon_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_plic_fragmenter_anon_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_plic_fragmenter_anon_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_coupler_to_plic_fragmenter_anon_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_coupler_to_plic_fragmenter_anon_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_coupler_to_plic_fragmenter_anon_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [12:0] auto_coupler_to_plic_fragmenter_anon_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input [63:0] auto_coupler_to_plic_fragmenter_anon_out_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_coupler_to_clint_fragmenter_anon_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_clint_fragmenter_anon_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_coupler_to_clint_fragmenter_anon_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_coupler_to_clint_fragmenter_anon_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [1:0] auto_coupler_to_clint_fragmenter_anon_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [12:0] auto_coupler_to_clint_fragmenter_anon_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [25:0] auto_coupler_to_clint_fragmenter_anon_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_coupler_to_clint_fragmenter_anon_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_coupler_to_clint_fragmenter_anon_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_clint_fragmenter_anon_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_clint_fragmenter_anon_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_coupler_to_clint_fragmenter_anon_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_coupler_to_clint_fragmenter_anon_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_coupler_to_clint_fragmenter_anon_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [12:0] auto_coupler_to_clint_fragmenter_anon_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input [63:0] auto_coupler_to_clint_fragmenter_anon_out_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_coupler_to_bus_named_pbus_bus_xing_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_bus_named_pbus_bus_xing_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [2:0] auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [8:0] auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [28:0] auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_bus_named_pbus_bus_xing_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_coupler_to_bus_named_pbus_bus_xing_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_coupler_to_bus_named_pbus_bus_xing_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_coupler_to_bus_named_pbus_bus_xing_out_d_bits_param, // @[LazyModuleImp.scala:107:25] input [2:0] auto_coupler_to_bus_named_pbus_bus_xing_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [8:0] auto_coupler_to_bus_named_pbus_bus_xing_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input auto_coupler_to_bus_named_pbus_bus_xing_out_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_coupler_to_bus_named_pbus_bus_xing_out_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_coupler_to_bus_named_pbus_bus_xing_out_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_coupler_to_bus_named_pbus_bus_xing_out_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_coupler_to_l2_ctrl_buffer_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_l2_ctrl_buffer_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_coupler_to_l2_ctrl_buffer_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_coupler_to_l2_ctrl_buffer_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [1:0] auto_coupler_to_l2_ctrl_buffer_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [12:0] auto_coupler_to_l2_ctrl_buffer_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [25:0] auto_coupler_to_l2_ctrl_buffer_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_coupler_to_l2_ctrl_buffer_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_coupler_to_l2_ctrl_buffer_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_l2_ctrl_buffer_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_l2_ctrl_buffer_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_coupler_to_l2_ctrl_buffer_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_coupler_to_l2_ctrl_buffer_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_coupler_to_l2_ctrl_buffer_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [12:0] auto_coupler_to_l2_ctrl_buffer_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input [63:0] auto_coupler_to_l2_ctrl_buffer_out_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_fixedClockNode_anon_out_5_clock, // @[LazyModuleImp.scala:107:25] output auto_fixedClockNode_anon_out_5_reset, // @[LazyModuleImp.scala:107:25] output auto_fixedClockNode_anon_out_4_clock, // @[LazyModuleImp.scala:107:25] output auto_fixedClockNode_anon_out_4_reset, // @[LazyModuleImp.scala:107:25] output auto_fixedClockNode_anon_out_3_clock, // @[LazyModuleImp.scala:107:25] output auto_fixedClockNode_anon_out_3_reset, // @[LazyModuleImp.scala:107:25] output auto_fixedClockNode_anon_out_2_clock, // @[LazyModuleImp.scala:107:25] output auto_fixedClockNode_anon_out_2_reset, // @[LazyModuleImp.scala:107:25] output auto_fixedClockNode_anon_out_1_clock, // @[LazyModuleImp.scala:107:25] output auto_fixedClockNode_anon_out_1_reset, // @[LazyModuleImp.scala:107:25] output auto_fixedClockNode_anon_out_0_clock, // @[LazyModuleImp.scala:107:25] output auto_fixedClockNode_anon_out_0_reset, // @[LazyModuleImp.scala:107:25] input auto_cbus_clock_groups_in_member_cbus_0_clock, // @[LazyModuleImp.scala:107:25] input auto_cbus_clock_groups_in_member_cbus_0_reset, // @[LazyModuleImp.scala:107:25] output auto_bus_xing_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_bus_xing_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_bus_xing_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_bus_xing_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_bus_xing_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [7:0] auto_bus_xing_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [28:0] auto_bus_xing_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_bus_xing_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_bus_xing_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_bus_xing_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_bus_xing_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_bus_xing_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_bus_xing_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_bus_xing_in_d_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_bus_xing_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [7:0] auto_bus_xing_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output auto_bus_xing_in_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_bus_xing_in_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [63:0] auto_bus_xing_in_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_bus_xing_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input custom_boot // @[CustomBootPin.scala:36:29] ); wire coupler_from_port_named_custom_boot_pin_auto_tl_out_d_valid; // @[LazyModuleImp.scala:138:7] wire coupler_from_port_named_custom_boot_pin_auto_tl_out_d_bits_corrupt; // @[LazyModuleImp.scala:138:7] wire [63:0] coupler_from_port_named_custom_boot_pin_auto_tl_out_d_bits_data; // @[LazyModuleImp.scala:138:7] wire coupler_from_port_named_custom_boot_pin_auto_tl_out_d_bits_denied; // @[LazyModuleImp.scala:138:7] wire coupler_from_port_named_custom_boot_pin_auto_tl_out_d_bits_sink; // @[LazyModuleImp.scala:138:7] wire [3:0] coupler_from_port_named_custom_boot_pin_auto_tl_out_d_bits_size; // @[LazyModuleImp.scala:138:7] wire [1:0] coupler_from_port_named_custom_boot_pin_auto_tl_out_d_bits_param; // @[LazyModuleImp.scala:138:7] wire [2:0] coupler_from_port_named_custom_boot_pin_auto_tl_out_d_bits_opcode; // @[LazyModuleImp.scala:138:7] wire coupler_from_port_named_custom_boot_pin_auto_tl_out_a_ready; // @[LazyModuleImp.scala:138:7] wire coupler_from_port_named_custom_boot_pin_auto_tl_in_d_valid; // @[LazyModuleImp.scala:138:7] wire coupler_from_port_named_custom_boot_pin_auto_tl_in_d_bits_corrupt; // @[LazyModuleImp.scala:138:7] wire [63:0] coupler_from_port_named_custom_boot_pin_auto_tl_in_d_bits_data; // @[LazyModuleImp.scala:138:7] wire coupler_from_port_named_custom_boot_pin_auto_tl_in_d_bits_denied; // @[LazyModuleImp.scala:138:7] wire coupler_from_port_named_custom_boot_pin_auto_tl_in_d_bits_sink; // @[LazyModuleImp.scala:138:7] wire [3:0] coupler_from_port_named_custom_boot_pin_auto_tl_in_d_bits_size; // @[LazyModuleImp.scala:138:7] wire [1:0] coupler_from_port_named_custom_boot_pin_auto_tl_in_d_bits_param; // @[LazyModuleImp.scala:138:7] wire [2:0] coupler_from_port_named_custom_boot_pin_auto_tl_in_d_bits_opcode; // @[LazyModuleImp.scala:138:7] wire coupler_from_port_named_custom_boot_pin_auto_tl_in_a_valid; // @[LazyModuleImp.scala:138:7] wire coupler_from_port_named_custom_boot_pin_auto_tl_in_a_ready; // @[LazyModuleImp.scala:138:7] wire [63:0] coupler_from_port_named_custom_boot_pin_auto_tl_in_a_bits_data; // @[LazyModuleImp.scala:138:7] wire [28:0] coupler_from_port_named_custom_boot_pin_auto_tl_in_a_bits_address; // @[LazyModuleImp.scala:138:7] wire coupler_to_bus_named_pbus_widget_auto_anon_out_d_valid; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_pbus_widget_auto_anon_out_d_ready; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_pbus_widget_auto_anon_out_d_bits_corrupt; // @[WidthWidget.scala:27:9] wire [63:0] coupler_to_bus_named_pbus_widget_auto_anon_out_d_bits_data; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_pbus_widget_auto_anon_out_d_bits_denied; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_pbus_widget_auto_anon_out_d_bits_sink; // @[WidthWidget.scala:27:9] wire [8:0] coupler_to_bus_named_pbus_widget_auto_anon_out_d_bits_source; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_pbus_widget_auto_anon_out_d_bits_size; // @[WidthWidget.scala:27:9] wire [1:0] coupler_to_bus_named_pbus_widget_auto_anon_out_d_bits_param; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_pbus_widget_auto_anon_out_d_bits_opcode; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_pbus_widget_auto_anon_out_a_valid; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_pbus_widget_auto_anon_out_a_ready; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_pbus_widget_auto_anon_out_a_bits_corrupt; // @[WidthWidget.scala:27:9] wire [63:0] coupler_to_bus_named_pbus_widget_auto_anon_out_a_bits_data; // @[WidthWidget.scala:27:9] wire [7:0] coupler_to_bus_named_pbus_widget_auto_anon_out_a_bits_mask; // @[WidthWidget.scala:27:9] wire [28:0] coupler_to_bus_named_pbus_widget_auto_anon_out_a_bits_address; // @[WidthWidget.scala:27:9] wire [8:0] coupler_to_bus_named_pbus_widget_auto_anon_out_a_bits_source; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_pbus_widget_auto_anon_out_a_bits_size; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_pbus_widget_auto_anon_out_a_bits_param; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_pbus_widget_auto_anon_out_a_bits_opcode; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_pbus_auto_widget_anon_in_d_ready; // @[LazyModuleImp.scala:138:7] wire coupler_to_bus_named_pbus_auto_widget_anon_in_a_valid; // @[LazyModuleImp.scala:138:7] wire coupler_to_bus_named_pbus_auto_widget_anon_in_a_bits_corrupt; // @[LazyModuleImp.scala:138:7] wire [63:0] coupler_to_bus_named_pbus_auto_widget_anon_in_a_bits_data; // @[LazyModuleImp.scala:138:7] wire [7:0] coupler_to_bus_named_pbus_auto_widget_anon_in_a_bits_mask; // @[LazyModuleImp.scala:138:7] wire [28:0] coupler_to_bus_named_pbus_auto_widget_anon_in_a_bits_address; // @[LazyModuleImp.scala:138:7] wire [8:0] coupler_to_bus_named_pbus_auto_widget_anon_in_a_bits_source; // @[LazyModuleImp.scala:138:7] wire [2:0] coupler_to_bus_named_pbus_auto_widget_anon_in_a_bits_size; // @[LazyModuleImp.scala:138:7] wire [2:0] coupler_to_bus_named_pbus_auto_widget_anon_in_a_bits_param; // @[LazyModuleImp.scala:138:7] wire [2:0] coupler_to_bus_named_pbus_auto_widget_anon_in_a_bits_opcode; // @[LazyModuleImp.scala:138:7] wire buffer_1_auto_out_d_valid; // @[Buffer.scala:40:9] wire buffer_1_auto_out_d_bits_corrupt; // @[Buffer.scala:40:9] wire [63:0] buffer_1_auto_out_d_bits_data; // @[Buffer.scala:40:9] wire buffer_1_auto_out_d_bits_denied; // @[Buffer.scala:40:9] wire buffer_1_auto_out_d_bits_sink; // @[Buffer.scala:40:9] wire [7:0] buffer_1_auto_out_d_bits_source; // @[Buffer.scala:40:9] wire [3:0] buffer_1_auto_out_d_bits_size; // @[Buffer.scala:40:9] wire [1:0] buffer_1_auto_out_d_bits_param; // @[Buffer.scala:40:9] wire [2:0] buffer_1_auto_out_d_bits_opcode; // @[Buffer.scala:40:9] wire buffer_1_auto_out_a_ready; // @[Buffer.scala:40:9] wire buffer_1_auto_in_d_valid; // @[Buffer.scala:40:9] wire buffer_1_auto_in_d_ready; // @[Buffer.scala:40:9] wire buffer_1_auto_in_d_bits_corrupt; // @[Buffer.scala:40:9] wire [63:0] buffer_1_auto_in_d_bits_data; // @[Buffer.scala:40:9] wire buffer_1_auto_in_d_bits_denied; // @[Buffer.scala:40:9] wire buffer_1_auto_in_d_bits_sink; // @[Buffer.scala:40:9] wire [7:0] buffer_1_auto_in_d_bits_source; // @[Buffer.scala:40:9] wire [3:0] buffer_1_auto_in_d_bits_size; // @[Buffer.scala:40:9] wire [1:0] buffer_1_auto_in_d_bits_param; // @[Buffer.scala:40:9] wire [2:0] buffer_1_auto_in_d_bits_opcode; // @[Buffer.scala:40:9] wire buffer_1_auto_in_a_valid; // @[Buffer.scala:40:9] wire buffer_1_auto_in_a_ready; // @[Buffer.scala:40:9] wire buffer_1_auto_in_a_bits_corrupt; // @[Buffer.scala:40:9] wire [63:0] buffer_1_auto_in_a_bits_data; // @[Buffer.scala:40:9] wire [7:0] buffer_1_auto_in_a_bits_mask; // @[Buffer.scala:40:9] wire [28:0] buffer_1_auto_in_a_bits_address; // @[Buffer.scala:40:9] wire [7:0] buffer_1_auto_in_a_bits_source; // @[Buffer.scala:40:9] wire [3:0] buffer_1_auto_in_a_bits_size; // @[Buffer.scala:40:9] wire [2:0] buffer_1_auto_in_a_bits_param; // @[Buffer.scala:40:9] wire [2:0] buffer_1_auto_in_a_bits_opcode; // @[Buffer.scala:40:9] wire fixer_auto_anon_out_d_valid; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_out_d_bits_corrupt; // @[FIFOFixer.scala:50:9] wire [63:0] fixer_auto_anon_out_d_bits_data; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_out_d_bits_denied; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_out_d_bits_sink; // @[FIFOFixer.scala:50:9] wire [8:0] fixer_auto_anon_out_d_bits_source; // @[FIFOFixer.scala:50:9] wire [3:0] fixer_auto_anon_out_d_bits_size; // @[FIFOFixer.scala:50:9] wire [1:0] fixer_auto_anon_out_d_bits_param; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_auto_anon_out_d_bits_opcode; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_out_a_ready; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_in_d_ready; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_in_a_valid; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_in_a_bits_corrupt; // @[FIFOFixer.scala:50:9] wire [63:0] fixer_auto_anon_in_a_bits_data; // @[FIFOFixer.scala:50:9] wire [7:0] fixer_auto_anon_in_a_bits_mask; // @[FIFOFixer.scala:50:9] wire [28:0] fixer_auto_anon_in_a_bits_address; // @[FIFOFixer.scala:50:9] wire [8:0] fixer_auto_anon_in_a_bits_source; // @[FIFOFixer.scala:50:9] wire [3:0] fixer_auto_anon_in_a_bits_size; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_auto_anon_in_a_bits_param; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_auto_anon_in_a_bits_opcode; // @[FIFOFixer.scala:50:9] wire cbus_clock_groups_auto_out_member_cbus_0_reset; // @[ClockGroup.scala:53:9] wire cbus_clock_groups_auto_out_member_cbus_0_clock; // @[ClockGroup.scala:53:9] wire _coupler_to_prci_ctrl_auto_tl_in_a_ready; // @[LazyScope.scala:98:27] wire _coupler_to_prci_ctrl_auto_tl_in_d_valid; // @[LazyScope.scala:98:27] wire [2:0] _coupler_to_prci_ctrl_auto_tl_in_d_bits_opcode; // @[LazyScope.scala:98:27] wire [1:0] _coupler_to_prci_ctrl_auto_tl_in_d_bits_param; // @[LazyScope.scala:98:27] wire [2:0] _coupler_to_prci_ctrl_auto_tl_in_d_bits_size; // @[LazyScope.scala:98:27] wire [8:0] _coupler_to_prci_ctrl_auto_tl_in_d_bits_source; // @[LazyScope.scala:98:27] wire _coupler_to_prci_ctrl_auto_tl_in_d_bits_sink; // @[LazyScope.scala:98:27] wire _coupler_to_prci_ctrl_auto_tl_in_d_bits_denied; // @[LazyScope.scala:98:27] wire [63:0] _coupler_to_prci_ctrl_auto_tl_in_d_bits_data; // @[LazyScope.scala:98:27] wire _coupler_to_prci_ctrl_auto_tl_in_d_bits_corrupt; // @[LazyScope.scala:98:27] wire _coupler_to_bootrom_auto_tl_in_a_ready; // @[LazyScope.scala:98:27] wire _coupler_to_bootrom_auto_tl_in_d_valid; // @[LazyScope.scala:98:27] wire [2:0] _coupler_to_bootrom_auto_tl_in_d_bits_size; // @[LazyScope.scala:98:27] wire [8:0] _coupler_to_bootrom_auto_tl_in_d_bits_source; // @[LazyScope.scala:98:27] wire [63:0] _coupler_to_bootrom_auto_tl_in_d_bits_data; // @[LazyScope.scala:98:27] wire _coupler_to_debug_auto_tl_in_a_ready; // @[LazyScope.scala:98:27] wire _coupler_to_debug_auto_tl_in_d_valid; // @[LazyScope.scala:98:27] wire [2:0] _coupler_to_debug_auto_tl_in_d_bits_opcode; // @[LazyScope.scala:98:27] wire [2:0] _coupler_to_debug_auto_tl_in_d_bits_size; // @[LazyScope.scala:98:27] wire [8:0] _coupler_to_debug_auto_tl_in_d_bits_source; // @[LazyScope.scala:98:27] wire [63:0] _coupler_to_debug_auto_tl_in_d_bits_data; // @[LazyScope.scala:98:27] wire _coupler_to_plic_auto_tl_in_a_ready; // @[LazyScope.scala:98:27] wire _coupler_to_plic_auto_tl_in_d_valid; // @[LazyScope.scala:98:27] wire [2:0] _coupler_to_plic_auto_tl_in_d_bits_opcode; // @[LazyScope.scala:98:27] wire [2:0] _coupler_to_plic_auto_tl_in_d_bits_size; // @[LazyScope.scala:98:27] wire [8:0] _coupler_to_plic_auto_tl_in_d_bits_source; // @[LazyScope.scala:98:27] wire [63:0] _coupler_to_plic_auto_tl_in_d_bits_data; // @[LazyScope.scala:98:27] wire _coupler_to_clint_auto_tl_in_a_ready; // @[LazyScope.scala:98:27] wire _coupler_to_clint_auto_tl_in_d_valid; // @[LazyScope.scala:98:27] wire [2:0] _coupler_to_clint_auto_tl_in_d_bits_opcode; // @[LazyScope.scala:98:27] wire [2:0] _coupler_to_clint_auto_tl_in_d_bits_size; // @[LazyScope.scala:98:27] wire [8:0] _coupler_to_clint_auto_tl_in_d_bits_source; // @[LazyScope.scala:98:27] wire [63:0] _coupler_to_clint_auto_tl_in_d_bits_data; // @[LazyScope.scala:98:27] wire _coupler_to_l2_ctrl_auto_tl_in_a_ready; // @[LazyScope.scala:98:27] wire _coupler_to_l2_ctrl_auto_tl_in_d_valid; // @[LazyScope.scala:98:27] wire [2:0] _coupler_to_l2_ctrl_auto_tl_in_d_bits_opcode; // @[LazyScope.scala:98:27] wire [1:0] _coupler_to_l2_ctrl_auto_tl_in_d_bits_param; // @[LazyScope.scala:98:27] wire [2:0] _coupler_to_l2_ctrl_auto_tl_in_d_bits_size; // @[LazyScope.scala:98:27] wire [8:0] _coupler_to_l2_ctrl_auto_tl_in_d_bits_source; // @[LazyScope.scala:98:27] wire _coupler_to_l2_ctrl_auto_tl_in_d_bits_sink; // @[LazyScope.scala:98:27] wire _coupler_to_l2_ctrl_auto_tl_in_d_bits_denied; // @[LazyScope.scala:98:27] wire [63:0] _coupler_to_l2_ctrl_auto_tl_in_d_bits_data; // @[LazyScope.scala:98:27] wire _coupler_to_l2_ctrl_auto_tl_in_d_bits_corrupt; // @[LazyScope.scala:98:27] wire _wrapped_error_device_auto_buffer_in_a_ready; // @[LazyScope.scala:98:27] wire _wrapped_error_device_auto_buffer_in_d_valid; // @[LazyScope.scala:98:27] wire [2:0] _wrapped_error_device_auto_buffer_in_d_bits_opcode; // @[LazyScope.scala:98:27] wire [1:0] _wrapped_error_device_auto_buffer_in_d_bits_param; // @[LazyScope.scala:98:27] wire [3:0] _wrapped_error_device_auto_buffer_in_d_bits_size; // @[LazyScope.scala:98:27] wire [8:0] _wrapped_error_device_auto_buffer_in_d_bits_source; // @[LazyScope.scala:98:27] wire _wrapped_error_device_auto_buffer_in_d_bits_sink; // @[LazyScope.scala:98:27] wire _wrapped_error_device_auto_buffer_in_d_bits_denied; // @[LazyScope.scala:98:27] wire [63:0] _wrapped_error_device_auto_buffer_in_d_bits_data; // @[LazyScope.scala:98:27] wire _wrapped_error_device_auto_buffer_in_d_bits_corrupt; // @[LazyScope.scala:98:27] wire _atomics_auto_in_a_ready; // @[AtomicAutomata.scala:289:29] wire _atomics_auto_in_d_valid; // @[AtomicAutomata.scala:289:29] wire [2:0] _atomics_auto_in_d_bits_opcode; // @[AtomicAutomata.scala:289:29] wire [1:0] _atomics_auto_in_d_bits_param; // @[AtomicAutomata.scala:289:29] wire [3:0] _atomics_auto_in_d_bits_size; // @[AtomicAutomata.scala:289:29] wire [8:0] _atomics_auto_in_d_bits_source; // @[AtomicAutomata.scala:289:29] wire _atomics_auto_in_d_bits_sink; // @[AtomicAutomata.scala:289:29] wire _atomics_auto_in_d_bits_denied; // @[AtomicAutomata.scala:289:29] wire [63:0] _atomics_auto_in_d_bits_data; // @[AtomicAutomata.scala:289:29] wire _atomics_auto_in_d_bits_corrupt; // @[AtomicAutomata.scala:289:29] wire _atomics_auto_out_a_valid; // @[AtomicAutomata.scala:289:29] wire [2:0] _atomics_auto_out_a_bits_opcode; // @[AtomicAutomata.scala:289:29] wire [2:0] _atomics_auto_out_a_bits_param; // @[AtomicAutomata.scala:289:29] wire [3:0] _atomics_auto_out_a_bits_size; // @[AtomicAutomata.scala:289:29] wire [8:0] _atomics_auto_out_a_bits_source; // @[AtomicAutomata.scala:289:29] wire [28:0] _atomics_auto_out_a_bits_address; // @[AtomicAutomata.scala:289:29] wire [7:0] _atomics_auto_out_a_bits_mask; // @[AtomicAutomata.scala:289:29] wire [63:0] _atomics_auto_out_a_bits_data; // @[AtomicAutomata.scala:289:29] wire _atomics_auto_out_a_bits_corrupt; // @[AtomicAutomata.scala:289:29] wire _atomics_auto_out_d_ready; // @[AtomicAutomata.scala:289:29] wire _buffer_auto_in_a_ready; // @[Buffer.scala:75:28] wire _buffer_auto_in_d_valid; // @[Buffer.scala:75:28] wire [2:0] _buffer_auto_in_d_bits_opcode; // @[Buffer.scala:75:28] wire [1:0] _buffer_auto_in_d_bits_param; // @[Buffer.scala:75:28] wire [3:0] _buffer_auto_in_d_bits_size; // @[Buffer.scala:75:28] wire [8:0] _buffer_auto_in_d_bits_source; // @[Buffer.scala:75:28] wire _buffer_auto_in_d_bits_sink; // @[Buffer.scala:75:28] wire _buffer_auto_in_d_bits_denied; // @[Buffer.scala:75:28] wire [63:0] _buffer_auto_in_d_bits_data; // @[Buffer.scala:75:28] wire _buffer_auto_in_d_bits_corrupt; // @[Buffer.scala:75:28] wire _out_xbar_auto_anon_out_7_a_valid; // @[PeripheryBus.scala:57:30] wire [2:0] _out_xbar_auto_anon_out_7_a_bits_opcode; // @[PeripheryBus.scala:57:30] wire [2:0] _out_xbar_auto_anon_out_7_a_bits_param; // @[PeripheryBus.scala:57:30] wire [2:0] _out_xbar_auto_anon_out_7_a_bits_size; // @[PeripheryBus.scala:57:30] wire [8:0] _out_xbar_auto_anon_out_7_a_bits_source; // @[PeripheryBus.scala:57:30] wire [20:0] _out_xbar_auto_anon_out_7_a_bits_address; // @[PeripheryBus.scala:57:30] wire [7:0] _out_xbar_auto_anon_out_7_a_bits_mask; // @[PeripheryBus.scala:57:30] wire [63:0] _out_xbar_auto_anon_out_7_a_bits_data; // @[PeripheryBus.scala:57:30] wire _out_xbar_auto_anon_out_7_a_bits_corrupt; // @[PeripheryBus.scala:57:30] wire _out_xbar_auto_anon_out_7_d_ready; // @[PeripheryBus.scala:57:30] wire _out_xbar_auto_anon_out_6_a_valid; // @[PeripheryBus.scala:57:30] wire [2:0] _out_xbar_auto_anon_out_6_a_bits_opcode; // @[PeripheryBus.scala:57:30] wire [2:0] _out_xbar_auto_anon_out_6_a_bits_param; // @[PeripheryBus.scala:57:30] wire [2:0] _out_xbar_auto_anon_out_6_a_bits_size; // @[PeripheryBus.scala:57:30] wire [8:0] _out_xbar_auto_anon_out_6_a_bits_source; // @[PeripheryBus.scala:57:30] wire [16:0] _out_xbar_auto_anon_out_6_a_bits_address; // @[PeripheryBus.scala:57:30] wire [7:0] _out_xbar_auto_anon_out_6_a_bits_mask; // @[PeripheryBus.scala:57:30] wire [63:0] _out_xbar_auto_anon_out_6_a_bits_data; // @[PeripheryBus.scala:57:30] wire _out_xbar_auto_anon_out_6_a_bits_corrupt; // @[PeripheryBus.scala:57:30] wire _out_xbar_auto_anon_out_6_d_ready; // @[PeripheryBus.scala:57:30] wire _out_xbar_auto_anon_out_5_a_valid; // @[PeripheryBus.scala:57:30] wire [2:0] _out_xbar_auto_anon_out_5_a_bits_opcode; // @[PeripheryBus.scala:57:30] wire [2:0] _out_xbar_auto_anon_out_5_a_bits_param; // @[PeripheryBus.scala:57:30] wire [2:0] _out_xbar_auto_anon_out_5_a_bits_size; // @[PeripheryBus.scala:57:30] wire [8:0] _out_xbar_auto_anon_out_5_a_bits_source; // @[PeripheryBus.scala:57:30] wire [11:0] _out_xbar_auto_anon_out_5_a_bits_address; // @[PeripheryBus.scala:57:30] wire [7:0] _out_xbar_auto_anon_out_5_a_bits_mask; // @[PeripheryBus.scala:57:30] wire [63:0] _out_xbar_auto_anon_out_5_a_bits_data; // @[PeripheryBus.scala:57:30] wire _out_xbar_auto_anon_out_5_a_bits_corrupt; // @[PeripheryBus.scala:57:30] wire _out_xbar_auto_anon_out_5_d_ready; // @[PeripheryBus.scala:57:30] wire _out_xbar_auto_anon_out_4_a_valid; // @[PeripheryBus.scala:57:30] wire [2:0] _out_xbar_auto_anon_out_4_a_bits_opcode; // @[PeripheryBus.scala:57:30] wire [2:0] _out_xbar_auto_anon_out_4_a_bits_param; // @[PeripheryBus.scala:57:30] wire [2:0] _out_xbar_auto_anon_out_4_a_bits_size; // @[PeripheryBus.scala:57:30] wire [8:0] _out_xbar_auto_anon_out_4_a_bits_source; // @[PeripheryBus.scala:57:30] wire [27:0] _out_xbar_auto_anon_out_4_a_bits_address; // @[PeripheryBus.scala:57:30] wire [7:0] _out_xbar_auto_anon_out_4_a_bits_mask; // @[PeripheryBus.scala:57:30] wire [63:0] _out_xbar_auto_anon_out_4_a_bits_data; // @[PeripheryBus.scala:57:30] wire _out_xbar_auto_anon_out_4_a_bits_corrupt; // @[PeripheryBus.scala:57:30] wire _out_xbar_auto_anon_out_4_d_ready; // @[PeripheryBus.scala:57:30] wire _out_xbar_auto_anon_out_3_a_valid; // @[PeripheryBus.scala:57:30] wire [2:0] _out_xbar_auto_anon_out_3_a_bits_opcode; // @[PeripheryBus.scala:57:30] wire [2:0] _out_xbar_auto_anon_out_3_a_bits_param; // @[PeripheryBus.scala:57:30] wire [2:0] _out_xbar_auto_anon_out_3_a_bits_size; // @[PeripheryBus.scala:57:30] wire [8:0] _out_xbar_auto_anon_out_3_a_bits_source; // @[PeripheryBus.scala:57:30] wire [25:0] _out_xbar_auto_anon_out_3_a_bits_address; // @[PeripheryBus.scala:57:30] wire [7:0] _out_xbar_auto_anon_out_3_a_bits_mask; // @[PeripheryBus.scala:57:30] wire [63:0] _out_xbar_auto_anon_out_3_a_bits_data; // @[PeripheryBus.scala:57:30] wire _out_xbar_auto_anon_out_3_a_bits_corrupt; // @[PeripheryBus.scala:57:30] wire _out_xbar_auto_anon_out_3_d_ready; // @[PeripheryBus.scala:57:30] wire _out_xbar_auto_anon_out_1_a_valid; // @[PeripheryBus.scala:57:30] wire [2:0] _out_xbar_auto_anon_out_1_a_bits_opcode; // @[PeripheryBus.scala:57:30] wire [2:0] _out_xbar_auto_anon_out_1_a_bits_param; // @[PeripheryBus.scala:57:30] wire [2:0] _out_xbar_auto_anon_out_1_a_bits_size; // @[PeripheryBus.scala:57:30] wire [8:0] _out_xbar_auto_anon_out_1_a_bits_source; // @[PeripheryBus.scala:57:30] wire [25:0] _out_xbar_auto_anon_out_1_a_bits_address; // @[PeripheryBus.scala:57:30] wire [7:0] _out_xbar_auto_anon_out_1_a_bits_mask; // @[PeripheryBus.scala:57:30] wire [63:0] _out_xbar_auto_anon_out_1_a_bits_data; // @[PeripheryBus.scala:57:30] wire _out_xbar_auto_anon_out_1_a_bits_corrupt; // @[PeripheryBus.scala:57:30] wire _out_xbar_auto_anon_out_1_d_ready; // @[PeripheryBus.scala:57:30] wire _out_xbar_auto_anon_out_0_a_valid; // @[PeripheryBus.scala:57:30] wire [2:0] _out_xbar_auto_anon_out_0_a_bits_opcode; // @[PeripheryBus.scala:57:30] wire [2:0] _out_xbar_auto_anon_out_0_a_bits_param; // @[PeripheryBus.scala:57:30] wire [3:0] _out_xbar_auto_anon_out_0_a_bits_size; // @[PeripheryBus.scala:57:30] wire [8:0] _out_xbar_auto_anon_out_0_a_bits_source; // @[PeripheryBus.scala:57:30] wire [13:0] _out_xbar_auto_anon_out_0_a_bits_address; // @[PeripheryBus.scala:57:30] wire [7:0] _out_xbar_auto_anon_out_0_a_bits_mask; // @[PeripheryBus.scala:57:30] wire [63:0] _out_xbar_auto_anon_out_0_a_bits_data; // @[PeripheryBus.scala:57:30] wire _out_xbar_auto_anon_out_0_a_bits_corrupt; // @[PeripheryBus.scala:57:30] wire _out_xbar_auto_anon_out_0_d_ready; // @[PeripheryBus.scala:57:30] wire _in_xbar_auto_anon_out_a_valid; // @[PeripheryBus.scala:56:29] wire [2:0] _in_xbar_auto_anon_out_a_bits_opcode; // @[PeripheryBus.scala:56:29] wire [2:0] _in_xbar_auto_anon_out_a_bits_param; // @[PeripheryBus.scala:56:29] wire [3:0] _in_xbar_auto_anon_out_a_bits_size; // @[PeripheryBus.scala:56:29] wire [8:0] _in_xbar_auto_anon_out_a_bits_source; // @[PeripheryBus.scala:56:29] wire [28:0] _in_xbar_auto_anon_out_a_bits_address; // @[PeripheryBus.scala:56:29] wire [7:0] _in_xbar_auto_anon_out_a_bits_mask; // @[PeripheryBus.scala:56:29] wire [63:0] _in_xbar_auto_anon_out_a_bits_data; // @[PeripheryBus.scala:56:29] wire _in_xbar_auto_anon_out_a_bits_corrupt; // @[PeripheryBus.scala:56:29] wire _in_xbar_auto_anon_out_d_ready; // @[PeripheryBus.scala:56:29] wire auto_coupler_to_prci_ctrl_fixer_anon_out_a_ready_0 = auto_coupler_to_prci_ctrl_fixer_anon_out_a_ready; // @[ClockDomain.scala:14:9] wire auto_coupler_to_prci_ctrl_fixer_anon_out_d_valid_0 = auto_coupler_to_prci_ctrl_fixer_anon_out_d_valid; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_to_prci_ctrl_fixer_anon_out_d_bits_opcode_0 = auto_coupler_to_prci_ctrl_fixer_anon_out_d_bits_opcode; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_to_prci_ctrl_fixer_anon_out_d_bits_size_0 = auto_coupler_to_prci_ctrl_fixer_anon_out_d_bits_size; // @[ClockDomain.scala:14:9] wire [8:0] auto_coupler_to_prci_ctrl_fixer_anon_out_d_bits_source_0 = auto_coupler_to_prci_ctrl_fixer_anon_out_d_bits_source; // @[ClockDomain.scala:14:9] wire [63:0] auto_coupler_to_prci_ctrl_fixer_anon_out_d_bits_data_0 = auto_coupler_to_prci_ctrl_fixer_anon_out_d_bits_data; // @[ClockDomain.scala:14:9] wire auto_coupler_to_bootrom_fragmenter_anon_out_a_ready_0 = auto_coupler_to_bootrom_fragmenter_anon_out_a_ready; // @[ClockDomain.scala:14:9] wire auto_coupler_to_bootrom_fragmenter_anon_out_d_valid_0 = auto_coupler_to_bootrom_fragmenter_anon_out_d_valid; // @[ClockDomain.scala:14:9] wire [1:0] auto_coupler_to_bootrom_fragmenter_anon_out_d_bits_size_0 = auto_coupler_to_bootrom_fragmenter_anon_out_d_bits_size; // @[ClockDomain.scala:14:9] wire [12:0] auto_coupler_to_bootrom_fragmenter_anon_out_d_bits_source_0 = auto_coupler_to_bootrom_fragmenter_anon_out_d_bits_source; // @[ClockDomain.scala:14:9] wire [63:0] auto_coupler_to_bootrom_fragmenter_anon_out_d_bits_data_0 = auto_coupler_to_bootrom_fragmenter_anon_out_d_bits_data; // @[ClockDomain.scala:14:9] wire auto_coupler_to_debug_fragmenter_anon_out_a_ready_0 = auto_coupler_to_debug_fragmenter_anon_out_a_ready; // @[ClockDomain.scala:14:9] wire auto_coupler_to_debug_fragmenter_anon_out_d_valid_0 = auto_coupler_to_debug_fragmenter_anon_out_d_valid; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_to_debug_fragmenter_anon_out_d_bits_opcode_0 = auto_coupler_to_debug_fragmenter_anon_out_d_bits_opcode; // @[ClockDomain.scala:14:9] wire [1:0] auto_coupler_to_debug_fragmenter_anon_out_d_bits_size_0 = auto_coupler_to_debug_fragmenter_anon_out_d_bits_size; // @[ClockDomain.scala:14:9] wire [12:0] auto_coupler_to_debug_fragmenter_anon_out_d_bits_source_0 = auto_coupler_to_debug_fragmenter_anon_out_d_bits_source; // @[ClockDomain.scala:14:9] wire [63:0] auto_coupler_to_debug_fragmenter_anon_out_d_bits_data_0 = auto_coupler_to_debug_fragmenter_anon_out_d_bits_data; // @[ClockDomain.scala:14:9] wire auto_coupler_to_plic_fragmenter_anon_out_a_ready_0 = auto_coupler_to_plic_fragmenter_anon_out_a_ready; // @[ClockDomain.scala:14:9] wire auto_coupler_to_plic_fragmenter_anon_out_d_valid_0 = auto_coupler_to_plic_fragmenter_anon_out_d_valid; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_to_plic_fragmenter_anon_out_d_bits_opcode_0 = auto_coupler_to_plic_fragmenter_anon_out_d_bits_opcode; // @[ClockDomain.scala:14:9] wire [1:0] auto_coupler_to_plic_fragmenter_anon_out_d_bits_size_0 = auto_coupler_to_plic_fragmenter_anon_out_d_bits_size; // @[ClockDomain.scala:14:9] wire [12:0] auto_coupler_to_plic_fragmenter_anon_out_d_bits_source_0 = auto_coupler_to_plic_fragmenter_anon_out_d_bits_source; // @[ClockDomain.scala:14:9] wire [63:0] auto_coupler_to_plic_fragmenter_anon_out_d_bits_data_0 = auto_coupler_to_plic_fragmenter_anon_out_d_bits_data; // @[ClockDomain.scala:14:9] wire auto_coupler_to_clint_fragmenter_anon_out_a_ready_0 = auto_coupler_to_clint_fragmenter_anon_out_a_ready; // @[ClockDomain.scala:14:9] wire auto_coupler_to_clint_fragmenter_anon_out_d_valid_0 = auto_coupler_to_clint_fragmenter_anon_out_d_valid; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_to_clint_fragmenter_anon_out_d_bits_opcode_0 = auto_coupler_to_clint_fragmenter_anon_out_d_bits_opcode; // @[ClockDomain.scala:14:9] wire [1:0] auto_coupler_to_clint_fragmenter_anon_out_d_bits_size_0 = auto_coupler_to_clint_fragmenter_anon_out_d_bits_size; // @[ClockDomain.scala:14:9] wire [12:0] auto_coupler_to_clint_fragmenter_anon_out_d_bits_source_0 = auto_coupler_to_clint_fragmenter_anon_out_d_bits_source; // @[ClockDomain.scala:14:9] wire [63:0] auto_coupler_to_clint_fragmenter_anon_out_d_bits_data_0 = auto_coupler_to_clint_fragmenter_anon_out_d_bits_data; // @[ClockDomain.scala:14:9] wire auto_coupler_to_bus_named_pbus_bus_xing_out_a_ready_0 = auto_coupler_to_bus_named_pbus_bus_xing_out_a_ready; // @[ClockDomain.scala:14:9] wire auto_coupler_to_bus_named_pbus_bus_xing_out_d_valid_0 = auto_coupler_to_bus_named_pbus_bus_xing_out_d_valid; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_to_bus_named_pbus_bus_xing_out_d_bits_opcode_0 = auto_coupler_to_bus_named_pbus_bus_xing_out_d_bits_opcode; // @[ClockDomain.scala:14:9] wire [1:0] auto_coupler_to_bus_named_pbus_bus_xing_out_d_bits_param_0 = auto_coupler_to_bus_named_pbus_bus_xing_out_d_bits_param; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_to_bus_named_pbus_bus_xing_out_d_bits_size_0 = auto_coupler_to_bus_named_pbus_bus_xing_out_d_bits_size; // @[ClockDomain.scala:14:9] wire [8:0] auto_coupler_to_bus_named_pbus_bus_xing_out_d_bits_source_0 = auto_coupler_to_bus_named_pbus_bus_xing_out_d_bits_source; // @[ClockDomain.scala:14:9] wire auto_coupler_to_bus_named_pbus_bus_xing_out_d_bits_sink_0 = auto_coupler_to_bus_named_pbus_bus_xing_out_d_bits_sink; // @[ClockDomain.scala:14:9] wire auto_coupler_to_bus_named_pbus_bus_xing_out_d_bits_denied_0 = auto_coupler_to_bus_named_pbus_bus_xing_out_d_bits_denied; // @[ClockDomain.scala:14:9] wire [63:0] auto_coupler_to_bus_named_pbus_bus_xing_out_d_bits_data_0 = auto_coupler_to_bus_named_pbus_bus_xing_out_d_bits_data; // @[ClockDomain.scala:14:9] wire auto_coupler_to_bus_named_pbus_bus_xing_out_d_bits_corrupt_0 = auto_coupler_to_bus_named_pbus_bus_xing_out_d_bits_corrupt; // @[ClockDomain.scala:14:9] wire auto_coupler_to_l2_ctrl_buffer_out_a_ready_0 = auto_coupler_to_l2_ctrl_buffer_out_a_ready; // @[ClockDomain.scala:14:9] wire auto_coupler_to_l2_ctrl_buffer_out_d_valid_0 = auto_coupler_to_l2_ctrl_buffer_out_d_valid; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_to_l2_ctrl_buffer_out_d_bits_opcode_0 = auto_coupler_to_l2_ctrl_buffer_out_d_bits_opcode; // @[ClockDomain.scala:14:9] wire [1:0] auto_coupler_to_l2_ctrl_buffer_out_d_bits_size_0 = auto_coupler_to_l2_ctrl_buffer_out_d_bits_size; // @[ClockDomain.scala:14:9] wire [12:0] auto_coupler_to_l2_ctrl_buffer_out_d_bits_source_0 = auto_coupler_to_l2_ctrl_buffer_out_d_bits_source; // @[ClockDomain.scala:14:9] wire [63:0] auto_coupler_to_l2_ctrl_buffer_out_d_bits_data_0 = auto_coupler_to_l2_ctrl_buffer_out_d_bits_data; // @[ClockDomain.scala:14:9] wire auto_cbus_clock_groups_in_member_cbus_0_clock_0 = auto_cbus_clock_groups_in_member_cbus_0_clock; // @[ClockDomain.scala:14:9] wire auto_cbus_clock_groups_in_member_cbus_0_reset_0 = auto_cbus_clock_groups_in_member_cbus_0_reset; // @[ClockDomain.scala:14:9] wire auto_bus_xing_in_a_valid_0 = auto_bus_xing_in_a_valid; // @[ClockDomain.scala:14:9] wire [2:0] auto_bus_xing_in_a_bits_opcode_0 = auto_bus_xing_in_a_bits_opcode; // @[ClockDomain.scala:14:9] wire [2:0] auto_bus_xing_in_a_bits_param_0 = auto_bus_xing_in_a_bits_param; // @[ClockDomain.scala:14:9] wire [3:0] auto_bus_xing_in_a_bits_size_0 = auto_bus_xing_in_a_bits_size; // @[ClockDomain.scala:14:9] wire [7:0] auto_bus_xing_in_a_bits_source_0 = auto_bus_xing_in_a_bits_source; // @[ClockDomain.scala:14:9] wire [28:0] auto_bus_xing_in_a_bits_address_0 = auto_bus_xing_in_a_bits_address; // @[ClockDomain.scala:14:9] wire [7:0] auto_bus_xing_in_a_bits_mask_0 = auto_bus_xing_in_a_bits_mask; // @[ClockDomain.scala:14:9] wire [63:0] auto_bus_xing_in_a_bits_data_0 = auto_bus_xing_in_a_bits_data; // @[ClockDomain.scala:14:9] wire auto_bus_xing_in_a_bits_corrupt_0 = auto_bus_xing_in_a_bits_corrupt; // @[ClockDomain.scala:14:9] wire auto_bus_xing_in_d_ready_0 = auto_bus_xing_in_d_ready; // @[ClockDomain.scala:14:9] wire [1:0] auto_coupler_to_prci_ctrl_fixer_anon_out_d_bits_param = 2'h0; // @[ClockDomain.scala:14:9] wire [1:0] auto_coupler_to_bootrom_fragmenter_anon_out_d_bits_param = 2'h0; // @[ClockDomain.scala:14:9] wire [1:0] auto_coupler_to_debug_fragmenter_anon_out_d_bits_param = 2'h0; // @[ClockDomain.scala:14:9] wire [1:0] auto_coupler_to_plic_fragmenter_anon_out_d_bits_param = 2'h0; // @[ClockDomain.scala:14:9] wire [1:0] auto_coupler_to_clint_fragmenter_anon_out_d_bits_param = 2'h0; // @[ClockDomain.scala:14:9] wire [1:0] auto_coupler_to_l2_ctrl_buffer_out_d_bits_param = 2'h0; // @[ClockDomain.scala:14:9] wire [1:0] nodeOut_a_bits_a_mask_hi_lo = 2'h0; // @[Misc.scala:222:10] wire [1:0] nodeOut_a_bits_a_mask_hi_hi = 2'h0; // @[Misc.scala:222:10] wire [1:0] nodeOut_a_bits_a_mask_hi_lo_1 = 2'h0; // @[Misc.scala:222:10] wire [1:0] nodeOut_a_bits_a_mask_hi_hi_1 = 2'h0; // @[Misc.scala:222:10] wire auto_coupler_to_prci_ctrl_fixer_anon_out_d_bits_sink = 1'h0; // @[ClockDomain.scala:14:9] wire auto_coupler_to_prci_ctrl_fixer_anon_out_d_bits_denied = 1'h0; // @[ClockDomain.scala:14:9] wire auto_coupler_to_prci_ctrl_fixer_anon_out_d_bits_corrupt = 1'h0; // @[ClockDomain.scala:14:9] wire auto_coupler_to_bootrom_fragmenter_anon_out_d_bits_sink = 1'h0; // @[ClockDomain.scala:14:9] wire auto_coupler_to_bootrom_fragmenter_anon_out_d_bits_denied = 1'h0; // @[ClockDomain.scala:14:9] wire auto_coupler_to_bootrom_fragmenter_anon_out_d_bits_corrupt = 1'h0; // @[ClockDomain.scala:14:9] wire auto_coupler_to_debug_fragmenter_anon_out_d_bits_sink = 1'h0; // @[ClockDomain.scala:14:9] wire auto_coupler_to_debug_fragmenter_anon_out_d_bits_denied = 1'h0; // @[ClockDomain.scala:14:9] wire auto_coupler_to_debug_fragmenter_anon_out_d_bits_corrupt = 1'h0; // @[ClockDomain.scala:14:9] wire auto_coupler_to_plic_fragmenter_anon_out_d_bits_sink = 1'h0; // @[ClockDomain.scala:14:9] wire auto_coupler_to_plic_fragmenter_anon_out_d_bits_denied = 1'h0; // @[ClockDomain.scala:14:9] wire auto_coupler_to_plic_fragmenter_anon_out_d_bits_corrupt = 1'h0; // @[ClockDomain.scala:14:9] wire auto_coupler_to_clint_fragmenter_anon_out_d_bits_sink = 1'h0; // @[ClockDomain.scala:14:9] wire auto_coupler_to_clint_fragmenter_anon_out_d_bits_denied = 1'h0; // @[ClockDomain.scala:14:9] wire auto_coupler_to_clint_fragmenter_anon_out_d_bits_corrupt = 1'h0; // @[ClockDomain.scala:14:9] wire auto_coupler_to_l2_ctrl_buffer_out_d_bits_sink = 1'h0; // @[ClockDomain.scala:14:9] wire auto_coupler_to_l2_ctrl_buffer_out_d_bits_denied = 1'h0; // @[ClockDomain.scala:14:9] wire auto_coupler_to_l2_ctrl_buffer_out_d_bits_corrupt = 1'h0; // @[ClockDomain.scala:14:9] wire _childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25] wire cbus_clock_groups_childClock = 1'h0; // @[LazyModuleImp.scala:155:31] wire cbus_clock_groups_childReset = 1'h0; // @[LazyModuleImp.scala:158:31] wire cbus_clock_groups__childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25] wire clockGroup_childClock = 1'h0; // @[LazyModuleImp.scala:155:31] wire clockGroup_childReset = 1'h0; // @[LazyModuleImp.scala:158:31] wire clockGroup__childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25] wire broadcast_childClock = 1'h0; // @[LazyModuleImp.scala:155:31] wire broadcast_childReset = 1'h0; // @[LazyModuleImp.scala:158:31] wire broadcast__childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25] wire fixer__flight_WIRE_0 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_1 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_2 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_3 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_4 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_5 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_6 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_7 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_8 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_9 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_10 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_11 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_12 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_13 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_14 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_15 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_16 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_17 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_18 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_19 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_20 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_21 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_22 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_23 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_24 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_25 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_26 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_27 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_28 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_29 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_30 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_31 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_32 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_33 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_34 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_35 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_36 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_37 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_38 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_39 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_40 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_41 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_42 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_43 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_44 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_45 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_46 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_47 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_48 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_49 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_50 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_51 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_52 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_53 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_54 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_55 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_56 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_57 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_58 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_59 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_60 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_61 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_62 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_63 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_64 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_65 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_66 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_67 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_68 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_69 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_70 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_71 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_72 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_73 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_74 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_75 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_76 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_77 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_78 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_79 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_80 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_81 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_82 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_83 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_84 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_85 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_86 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_87 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_88 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_89 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_90 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_91 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_92 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_93 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_94 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_95 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_96 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_97 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_98 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_99 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_100 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_101 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_102 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_103 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_104 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_105 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_106 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_107 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_108 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_109 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_110 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_111 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_112 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_113 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_114 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_115 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_116 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_117 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_118 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_119 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_120 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_121 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_122 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_123 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_124 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_125 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_126 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_127 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_128 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_129 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_130 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_131 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_132 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_133 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_134 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_135 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_136 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_137 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_138 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_139 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_140 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_141 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_142 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_143 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_144 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_145 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_146 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_147 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_148 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_149 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_150 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_151 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_152 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_153 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_154 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_155 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_156 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_157 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_158 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_159 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_160 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_161 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_162 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_163 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_164 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_165 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_166 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_167 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_168 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_169 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_170 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_171 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_172 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_173 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_174 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_175 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_176 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_177 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_178 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_179 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_180 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_181 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_182 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_183 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_184 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_185 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_186 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_187 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_188 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_189 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_190 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_191 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_192 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_193 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_194 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_195 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_196 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_197 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_198 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_199 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_200 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_201 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_202 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_203 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_204 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_205 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_206 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_207 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_208 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_209 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_210 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_211 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_212 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_213 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_214 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_215 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_216 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_217 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_218 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_219 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_220 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_221 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_222 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_223 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_224 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_225 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_226 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_227 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_228 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_229 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_230 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_231 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_232 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_233 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_234 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_235 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_236 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_237 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_238 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_239 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_240 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_241 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_242 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_243 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_244 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_245 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_246 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_247 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_248 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_249 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_250 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_251 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_252 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_253 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_254 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_255 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_256 = 1'h0; // @[FIFOFixer.scala:79:35] wire coupler_from_port_named_custom_boot_pin_auto_tl_in_a_bits_source = 1'h0; // @[LazyModuleImp.scala:138:7] wire coupler_from_port_named_custom_boot_pin_auto_tl_in_a_bits_corrupt = 1'h0; // @[LazyModuleImp.scala:138:7] wire coupler_from_port_named_custom_boot_pin_auto_tl_in_d_bits_source = 1'h0; // @[LazyModuleImp.scala:138:7] wire coupler_from_port_named_custom_boot_pin_auto_tl_out_a_bits_source = 1'h0; // @[LazyModuleImp.scala:138:7] wire coupler_from_port_named_custom_boot_pin_auto_tl_out_a_bits_corrupt = 1'h0; // @[LazyModuleImp.scala:138:7] wire coupler_from_port_named_custom_boot_pin_auto_tl_out_d_bits_source = 1'h0; // @[LazyModuleImp.scala:138:7] wire coupler_from_port_named_custom_boot_pin_tlOut_a_bits_source = 1'h0; // @[MixedNode.scala:542:17] wire coupler_from_port_named_custom_boot_pin_tlOut_a_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17] wire coupler_from_port_named_custom_boot_pin_tlOut_d_bits_source = 1'h0; // @[MixedNode.scala:542:17] wire coupler_from_port_named_custom_boot_pin_tlIn_a_bits_source = 1'h0; // @[MixedNode.scala:551:17] wire coupler_from_port_named_custom_boot_pin_tlIn_a_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17] wire coupler_from_port_named_custom_boot_pin_tlIn_d_bits_source = 1'h0; // @[MixedNode.scala:551:17] wire nodeOut_a_bits_source = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_a_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_d_bits_source = 1'h0; // @[MixedNode.scala:542:17] wire _nodeOut_a_bits_legal_T_8 = 1'h0; // @[Parameters.scala:137:59] wire _nodeOut_a_bits_legal_T_9 = 1'h0; // @[Parameters.scala:684:54] wire _nodeOut_a_bits_legal_T_23 = 1'h0; // @[Parameters.scala:137:59] wire _nodeOut_a_bits_legal_T_28 = 1'h0; // @[Parameters.scala:137:59] wire _nodeOut_a_bits_legal_T_33 = 1'h0; // @[Parameters.scala:137:59] wire _nodeOut_a_bits_legal_T_38 = 1'h0; // @[Parameters.scala:137:59] wire _nodeOut_a_bits_legal_T_43 = 1'h0; // @[Parameters.scala:137:59] wire _nodeOut_a_bits_legal_T_50 = 1'h0; // @[Parameters.scala:684:29] wire _nodeOut_a_bits_legal_T_55 = 1'h0; // @[Parameters.scala:137:59] wire _nodeOut_a_bits_legal_T_56 = 1'h0; // @[Parameters.scala:684:54] wire _nodeOut_a_bits_legal_T_57 = 1'h0; // @[Parameters.scala:686:26] wire nodeOut_a_bits_a_source = 1'h0; // @[Edges.scala:480:17] wire nodeOut_a_bits_a_corrupt = 1'h0; // @[Edges.scala:480:17] wire nodeOut_a_bits_a_mask_sub_sub_sub_0_1 = 1'h0; // @[Misc.scala:206:21] wire nodeOut_a_bits_a_mask_sub_sub_1_2 = 1'h0; // @[Misc.scala:214:27] wire _nodeOut_a_bits_a_mask_sub_sub_acc_T_1 = 1'h0; // @[Misc.scala:215:38] wire nodeOut_a_bits_a_mask_sub_sub_1_1 = 1'h0; // @[Misc.scala:215:29] wire nodeOut_a_bits_a_mask_sub_size = 1'h0; // @[Misc.scala:209:26] wire _nodeOut_a_bits_a_mask_sub_acc_T = 1'h0; // @[Misc.scala:215:38] wire nodeOut_a_bits_a_mask_sub_1_2 = 1'h0; // @[Misc.scala:214:27] wire _nodeOut_a_bits_a_mask_sub_acc_T_1 = 1'h0; // @[Misc.scala:215:38] wire nodeOut_a_bits_a_mask_sub_2_2 = 1'h0; // @[Misc.scala:214:27] wire _nodeOut_a_bits_a_mask_sub_acc_T_2 = 1'h0; // @[Misc.scala:215:38] wire nodeOut_a_bits_a_mask_sub_2_1 = 1'h0; // @[Misc.scala:215:29] wire nodeOut_a_bits_a_mask_sub_3_2 = 1'h0; // @[Misc.scala:214:27] wire _nodeOut_a_bits_a_mask_sub_acc_T_3 = 1'h0; // @[Misc.scala:215:38] wire nodeOut_a_bits_a_mask_sub_3_1 = 1'h0; // @[Misc.scala:215:29] wire nodeOut_a_bits_a_mask_eq_1 = 1'h0; // @[Misc.scala:214:27] wire _nodeOut_a_bits_a_mask_acc_T_1 = 1'h0; // @[Misc.scala:215:38] wire nodeOut_a_bits_a_mask_eq_2 = 1'h0; // @[Misc.scala:214:27] wire _nodeOut_a_bits_a_mask_acc_T_2 = 1'h0; // @[Misc.scala:215:38] wire nodeOut_a_bits_a_mask_eq_3 = 1'h0; // @[Misc.scala:214:27] wire _nodeOut_a_bits_a_mask_acc_T_3 = 1'h0; // @[Misc.scala:215:38] wire nodeOut_a_bits_a_mask_eq_4 = 1'h0; // @[Misc.scala:214:27] wire _nodeOut_a_bits_a_mask_acc_T_4 = 1'h0; // @[Misc.scala:215:38] wire nodeOut_a_bits_a_mask_acc_4 = 1'h0; // @[Misc.scala:215:29] wire nodeOut_a_bits_a_mask_eq_5 = 1'h0; // @[Misc.scala:214:27] wire _nodeOut_a_bits_a_mask_acc_T_5 = 1'h0; // @[Misc.scala:215:38] wire nodeOut_a_bits_a_mask_acc_5 = 1'h0; // @[Misc.scala:215:29] wire nodeOut_a_bits_a_mask_eq_6 = 1'h0; // @[Misc.scala:214:27] wire _nodeOut_a_bits_a_mask_acc_T_6 = 1'h0; // @[Misc.scala:215:38] wire nodeOut_a_bits_a_mask_acc_6 = 1'h0; // @[Misc.scala:215:29] wire nodeOut_a_bits_a_mask_eq_7 = 1'h0; // @[Misc.scala:214:27] wire _nodeOut_a_bits_a_mask_acc_T_7 = 1'h0; // @[Misc.scala:215:38] wire nodeOut_a_bits_a_mask_acc_7 = 1'h0; // @[Misc.scala:215:29] wire _nodeOut_a_bits_legal_T_67 = 1'h0; // @[Parameters.scala:137:59] wire _nodeOut_a_bits_legal_T_68 = 1'h0; // @[Parameters.scala:684:54] wire _nodeOut_a_bits_legal_T_77 = 1'h0; // @[Parameters.scala:137:59] wire _nodeOut_a_bits_legal_T_82 = 1'h0; // @[Parameters.scala:137:59] wire _nodeOut_a_bits_legal_T_92 = 1'h0; // @[Parameters.scala:137:59] wire _nodeOut_a_bits_legal_T_97 = 1'h0; // @[Parameters.scala:137:59] wire _nodeOut_a_bits_legal_T_102 = 1'h0; // @[Parameters.scala:137:59] wire _nodeOut_a_bits_legal_T_103 = 1'h0; // @[Parameters.scala:685:42] wire _nodeOut_a_bits_legal_T_109 = 1'h0; // @[Parameters.scala:684:29] wire _nodeOut_a_bits_legal_T_114 = 1'h0; // @[Parameters.scala:137:59] wire _nodeOut_a_bits_legal_T_115 = 1'h0; // @[Parameters.scala:684:54] wire _nodeOut_a_bits_legal_T_116 = 1'h0; // @[Parameters.scala:686:26] wire nodeOut_a_bits_a_1_source = 1'h0; // @[Edges.scala:480:17] wire nodeOut_a_bits_a_1_corrupt = 1'h0; // @[Edges.scala:480:17] wire nodeOut_a_bits_a_mask_sub_sub_sub_0_1_1 = 1'h0; // @[Misc.scala:206:21] wire nodeOut_a_bits_a_mask_sub_sub_1_2_1 = 1'h0; // @[Misc.scala:214:27] wire _nodeOut_a_bits_a_mask_sub_sub_acc_T_3 = 1'h0; // @[Misc.scala:215:38] wire nodeOut_a_bits_a_mask_sub_sub_1_1_1 = 1'h0; // @[Misc.scala:215:29] wire nodeOut_a_bits_a_mask_sub_size_1 = 1'h0; // @[Misc.scala:209:26] wire _nodeOut_a_bits_a_mask_sub_acc_T_4 = 1'h0; // @[Misc.scala:215:38] wire nodeOut_a_bits_a_mask_sub_1_2_1 = 1'h0; // @[Misc.scala:214:27] wire _nodeOut_a_bits_a_mask_sub_acc_T_5 = 1'h0; // @[Misc.scala:215:38] wire nodeOut_a_bits_a_mask_sub_2_2_1 = 1'h0; // @[Misc.scala:214:27] wire _nodeOut_a_bits_a_mask_sub_acc_T_6 = 1'h0; // @[Misc.scala:215:38] wire nodeOut_a_bits_a_mask_sub_2_1_1 = 1'h0; // @[Misc.scala:215:29] wire nodeOut_a_bits_a_mask_sub_3_2_1 = 1'h0; // @[Misc.scala:214:27] wire _nodeOut_a_bits_a_mask_sub_acc_T_7 = 1'h0; // @[Misc.scala:215:38] wire nodeOut_a_bits_a_mask_sub_3_1_1 = 1'h0; // @[Misc.scala:215:29] wire nodeOut_a_bits_a_mask_eq_9 = 1'h0; // @[Misc.scala:214:27] wire _nodeOut_a_bits_a_mask_acc_T_9 = 1'h0; // @[Misc.scala:215:38] wire nodeOut_a_bits_a_mask_eq_10 = 1'h0; // @[Misc.scala:214:27] wire _nodeOut_a_bits_a_mask_acc_T_10 = 1'h0; // @[Misc.scala:215:38] wire nodeOut_a_bits_a_mask_eq_11 = 1'h0; // @[Misc.scala:214:27] wire _nodeOut_a_bits_a_mask_acc_T_11 = 1'h0; // @[Misc.scala:215:38] wire nodeOut_a_bits_a_mask_eq_12 = 1'h0; // @[Misc.scala:214:27] wire _nodeOut_a_bits_a_mask_acc_T_12 = 1'h0; // @[Misc.scala:215:38] wire nodeOut_a_bits_a_mask_acc_12 = 1'h0; // @[Misc.scala:215:29] wire nodeOut_a_bits_a_mask_eq_13 = 1'h0; // @[Misc.scala:214:27] wire _nodeOut_a_bits_a_mask_acc_T_13 = 1'h0; // @[Misc.scala:215:38] wire nodeOut_a_bits_a_mask_acc_13 = 1'h0; // @[Misc.scala:215:29] wire nodeOut_a_bits_a_mask_eq_14 = 1'h0; // @[Misc.scala:214:27] wire _nodeOut_a_bits_a_mask_acc_T_14 = 1'h0; // @[Misc.scala:215:38] wire nodeOut_a_bits_a_mask_acc_14 = 1'h0; // @[Misc.scala:215:29] wire nodeOut_a_bits_a_mask_eq_15 = 1'h0; // @[Misc.scala:214:27] wire _nodeOut_a_bits_a_mask_acc_T_15 = 1'h0; // @[Misc.scala:215:38] wire nodeOut_a_bits_a_mask_acc_15 = 1'h0; // @[Misc.scala:215:29] wire [2:0] auto_coupler_to_bootrom_fragmenter_anon_out_d_bits_opcode = 3'h1; // @[ClockDomain.scala:14:9] wire [7:0] coupler_from_port_named_custom_boot_pin_auto_tl_in_a_bits_mask = 8'hF; // @[LazyModuleImp.scala:138:7] wire [7:0] coupler_from_port_named_custom_boot_pin_auto_tl_out_a_bits_mask = 8'hF; // @[LazyModuleImp.scala:138:7] wire [7:0] coupler_from_port_named_custom_boot_pin_tlOut_a_bits_mask = 8'hF; // @[MixedNode.scala:542:17] wire [7:0] coupler_from_port_named_custom_boot_pin_tlIn_a_bits_mask = 8'hF; // @[MixedNode.scala:551:17] wire [7:0] nodeOut_a_bits_mask = 8'hF; // @[MixedNode.scala:542:17] wire [7:0] nodeOut_a_bits_a_mask = 8'hF; // @[Edges.scala:480:17] wire [7:0] _nodeOut_a_bits_a_mask_T = 8'hF; // @[Misc.scala:222:10] wire [7:0] nodeOut_a_bits_a_1_mask = 8'hF; // @[Edges.scala:480:17] wire [7:0] _nodeOut_a_bits_a_mask_T_1 = 8'hF; // @[Misc.scala:222:10] wire [3:0] coupler_from_port_named_custom_boot_pin_auto_tl_in_a_bits_size = 4'h2; // @[LazyModuleImp.scala:138:7] wire [3:0] coupler_from_port_named_custom_boot_pin_auto_tl_out_a_bits_size = 4'h2; // @[LazyModuleImp.scala:138:7] wire [3:0] coupler_from_port_named_custom_boot_pin_tlOut_a_bits_size = 4'h2; // @[MixedNode.scala:542:17] wire [3:0] coupler_from_port_named_custom_boot_pin_tlIn_a_bits_size = 4'h2; // @[MixedNode.scala:551:17] wire [3:0] nodeOut_a_bits_size = 4'h2; // @[MixedNode.scala:542:17] wire [3:0] nodeOut_a_bits_a_size = 4'h2; // @[Edges.scala:480:17] wire [3:0] nodeOut_a_bits_a_1_size = 4'h2; // @[Edges.scala:480:17] wire [2:0] coupler_from_port_named_custom_boot_pin_auto_tl_in_a_bits_opcode = 3'h0; // @[LazyModuleImp.scala:138:7] wire [2:0] coupler_from_port_named_custom_boot_pin_auto_tl_in_a_bits_param = 3'h0; // @[LazyModuleImp.scala:138:7] wire [2:0] coupler_from_port_named_custom_boot_pin_auto_tl_out_a_bits_opcode = 3'h0; // @[LazyModuleImp.scala:138:7] wire [2:0] coupler_from_port_named_custom_boot_pin_auto_tl_out_a_bits_param = 3'h0; // @[LazyModuleImp.scala:138:7] wire [2:0] coupler_from_port_named_custom_boot_pin_tlOut_a_bits_opcode = 3'h0; // @[MixedNode.scala:542:17] wire [2:0] coupler_from_port_named_custom_boot_pin_tlOut_a_bits_param = 3'h0; // @[MixedNode.scala:542:17] wire [2:0] coupler_from_port_named_custom_boot_pin_tlIn_a_bits_opcode = 3'h0; // @[MixedNode.scala:551:17] wire [2:0] coupler_from_port_named_custom_boot_pin_tlIn_a_bits_param = 3'h0; // @[MixedNode.scala:551:17] wire [2:0] nodeOut_a_bits_opcode = 3'h0; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_a_bits_param = 3'h0; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_a_bits_a_opcode = 3'h0; // @[Edges.scala:480:17] wire [2:0] nodeOut_a_bits_a_param = 3'h0; // @[Edges.scala:480:17] wire [2:0] nodeOut_a_bits_a_1_opcode = 3'h0; // @[Edges.scala:480:17] wire [2:0] nodeOut_a_bits_a_1_param = 3'h0; // @[Edges.scala:480:17] wire [3:0] nodeOut_a_bits_a_mask_hi = 4'h0; // @[Misc.scala:222:10] wire [3:0] nodeOut_a_bits_a_mask_hi_1 = 4'h0; // @[Misc.scala:222:10] wire [3:0] nodeOut_a_bits_a_mask_lo = 4'hF; // @[Misc.scala:222:10] wire [3:0] nodeOut_a_bits_a_mask_lo_1 = 4'hF; // @[Misc.scala:222:10] wire [1:0] nodeOut_a_bits_a_mask_lo_lo = 2'h3; // @[Misc.scala:222:10] wire [1:0] nodeOut_a_bits_a_mask_lo_hi = 2'h3; // @[Misc.scala:222:10] wire [1:0] nodeOut_a_bits_a_mask_lo_lo_1 = 2'h3; // @[Misc.scala:222:10] wire [1:0] nodeOut_a_bits_a_mask_lo_hi_1 = 2'h3; // @[Misc.scala:222:10] wire fixer__a_notFIFO_T_4 = 1'h1; // @[Parameters.scala:137:59] wire fixer__flight_T = 1'h1; // @[FIFOFixer.scala:80:65] wire fixer__anonOut_a_valid_T = 1'h1; // @[FIFOFixer.scala:95:50] wire fixer__anonOut_a_valid_T_1 = 1'h1; // @[FIFOFixer.scala:95:47] wire fixer__anonIn_a_ready_T = 1'h1; // @[FIFOFixer.scala:96:50] wire fixer__anonIn_a_ready_T_1 = 1'h1; // @[FIFOFixer.scala:96:47] wire coupler_from_port_named_custom_boot_pin_auto_tl_in_d_ready = 1'h1; // @[LazyModuleImp.scala:138:7] wire coupler_from_port_named_custom_boot_pin_auto_tl_out_d_ready = 1'h1; // @[LazyModuleImp.scala:138:7] wire coupler_from_port_named_custom_boot_pin_tlOut_d_ready = 1'h1; // @[MixedNode.scala:542:17] wire coupler_from_port_named_custom_boot_pin_tlIn_d_ready = 1'h1; // @[MixedNode.scala:551:17] wire nodeOut_d_ready = 1'h1; // @[MixedNode.scala:542:17] wire _nodeOut_a_bits_legal_T = 1'h1; // @[Parameters.scala:92:28] wire _nodeOut_a_bits_legal_T_1 = 1'h1; // @[Parameters.scala:92:38] wire _nodeOut_a_bits_legal_T_2 = 1'h1; // @[Parameters.scala:92:33] wire _nodeOut_a_bits_legal_T_3 = 1'h1; // @[Parameters.scala:684:29] wire _nodeOut_a_bits_legal_T_10 = 1'h1; // @[Parameters.scala:92:28] wire _nodeOut_a_bits_legal_T_11 = 1'h1; // @[Parameters.scala:92:38] wire _nodeOut_a_bits_legal_T_12 = 1'h1; // @[Parameters.scala:92:33] wire _nodeOut_a_bits_legal_T_13 = 1'h1; // @[Parameters.scala:684:29] wire _nodeOut_a_bits_legal_T_18 = 1'h1; // @[Parameters.scala:137:59] wire _nodeOut_a_bits_legal_T_44 = 1'h1; // @[Parameters.scala:685:42] wire _nodeOut_a_bits_legal_T_45 = 1'h1; // @[Parameters.scala:685:42] wire _nodeOut_a_bits_legal_T_46 = 1'h1; // @[Parameters.scala:685:42] wire _nodeOut_a_bits_legal_T_47 = 1'h1; // @[Parameters.scala:685:42] wire _nodeOut_a_bits_legal_T_48 = 1'h1; // @[Parameters.scala:685:42] wire _nodeOut_a_bits_legal_T_49 = 1'h1; // @[Parameters.scala:684:54] wire _nodeOut_a_bits_legal_T_58 = 1'h1; // @[Parameters.scala:686:26] wire nodeOut_a_bits_legal = 1'h1; // @[Parameters.scala:686:26] wire nodeOut_a_bits_a_mask_sub_sub_size = 1'h1; // @[Misc.scala:209:26] wire nodeOut_a_bits_a_mask_sub_sub_nbit = 1'h1; // @[Misc.scala:211:20] wire nodeOut_a_bits_a_mask_sub_sub_0_2 = 1'h1; // @[Misc.scala:214:27] wire _nodeOut_a_bits_a_mask_sub_sub_acc_T = 1'h1; // @[Misc.scala:215:38] wire nodeOut_a_bits_a_mask_sub_sub_0_1 = 1'h1; // @[Misc.scala:215:29] wire nodeOut_a_bits_a_mask_sub_nbit = 1'h1; // @[Misc.scala:211:20] wire nodeOut_a_bits_a_mask_sub_0_2 = 1'h1; // @[Misc.scala:214:27] wire nodeOut_a_bits_a_mask_sub_0_1 = 1'h1; // @[Misc.scala:215:29] wire nodeOut_a_bits_a_mask_sub_1_1 = 1'h1; // @[Misc.scala:215:29] wire nodeOut_a_bits_a_mask_size = 1'h1; // @[Misc.scala:209:26] wire nodeOut_a_bits_a_mask_nbit = 1'h1; // @[Misc.scala:211:20] wire nodeOut_a_bits_a_mask_eq = 1'h1; // @[Misc.scala:214:27] wire _nodeOut_a_bits_a_mask_acc_T = 1'h1; // @[Misc.scala:215:38] wire nodeOut_a_bits_a_mask_acc = 1'h1; // @[Misc.scala:215:29] wire nodeOut_a_bits_a_mask_acc_1 = 1'h1; // @[Misc.scala:215:29] wire nodeOut_a_bits_a_mask_acc_2 = 1'h1; // @[Misc.scala:215:29] wire nodeOut_a_bits_a_mask_acc_3 = 1'h1; // @[Misc.scala:215:29] wire _nodeOut_a_bits_legal_T_59 = 1'h1; // @[Parameters.scala:92:28] wire _nodeOut_a_bits_legal_T_60 = 1'h1; // @[Parameters.scala:92:38] wire _nodeOut_a_bits_legal_T_61 = 1'h1; // @[Parameters.scala:92:33] wire _nodeOut_a_bits_legal_T_62 = 1'h1; // @[Parameters.scala:684:29] wire _nodeOut_a_bits_legal_T_69 = 1'h1; // @[Parameters.scala:92:28] wire _nodeOut_a_bits_legal_T_70 = 1'h1; // @[Parameters.scala:92:38] wire _nodeOut_a_bits_legal_T_71 = 1'h1; // @[Parameters.scala:92:33] wire _nodeOut_a_bits_legal_T_72 = 1'h1; // @[Parameters.scala:684:29] wire _nodeOut_a_bits_legal_T_87 = 1'h1; // @[Parameters.scala:137:59] wire _nodeOut_a_bits_legal_T_104 = 1'h1; // @[Parameters.scala:685:42] wire _nodeOut_a_bits_legal_T_105 = 1'h1; // @[Parameters.scala:685:42] wire _nodeOut_a_bits_legal_T_106 = 1'h1; // @[Parameters.scala:685:42] wire _nodeOut_a_bits_legal_T_107 = 1'h1; // @[Parameters.scala:685:42] wire _nodeOut_a_bits_legal_T_108 = 1'h1; // @[Parameters.scala:684:54] wire _nodeOut_a_bits_legal_T_117 = 1'h1; // @[Parameters.scala:686:26] wire nodeOut_a_bits_legal_1 = 1'h1; // @[Parameters.scala:686:26] wire nodeOut_a_bits_a_mask_sub_sub_size_1 = 1'h1; // @[Misc.scala:209:26] wire nodeOut_a_bits_a_mask_sub_sub_nbit_1 = 1'h1; // @[Misc.scala:211:20] wire nodeOut_a_bits_a_mask_sub_sub_0_2_1 = 1'h1; // @[Misc.scala:214:27] wire _nodeOut_a_bits_a_mask_sub_sub_acc_T_2 = 1'h1; // @[Misc.scala:215:38] wire nodeOut_a_bits_a_mask_sub_sub_0_1_1 = 1'h1; // @[Misc.scala:215:29] wire nodeOut_a_bits_a_mask_sub_nbit_1 = 1'h1; // @[Misc.scala:211:20] wire nodeOut_a_bits_a_mask_sub_0_2_1 = 1'h1; // @[Misc.scala:214:27] wire nodeOut_a_bits_a_mask_sub_0_1_1 = 1'h1; // @[Misc.scala:215:29] wire nodeOut_a_bits_a_mask_sub_1_1_1 = 1'h1; // @[Misc.scala:215:29] wire nodeOut_a_bits_a_mask_size_1 = 1'h1; // @[Misc.scala:209:26] wire nodeOut_a_bits_a_mask_nbit_1 = 1'h1; // @[Misc.scala:211:20] wire nodeOut_a_bits_a_mask_eq_8 = 1'h1; // @[Misc.scala:214:27] wire _nodeOut_a_bits_a_mask_acc_T_8 = 1'h1; // @[Misc.scala:215:38] wire nodeOut_a_bits_a_mask_acc_8 = 1'h1; // @[Misc.scala:215:29] wire nodeOut_a_bits_a_mask_acc_9 = 1'h1; // @[Misc.scala:215:29] wire nodeOut_a_bits_a_mask_acc_10 = 1'h1; // @[Misc.scala:215:29] wire nodeOut_a_bits_a_mask_acc_11 = 1'h1; // @[Misc.scala:215:29] wire [2:0] nodeOut_a_bits_a_mask_sizeOH = 3'h5; // @[Misc.scala:202:81] wire [2:0] nodeOut_a_bits_a_mask_sizeOH_1 = 3'h5; // @[Misc.scala:202:81] wire [2:0] _nodeOut_a_bits_a_mask_sizeOH_T_2 = 3'h4; // @[OneHot.scala:65:27] wire [2:0] _nodeOut_a_bits_a_mask_sizeOH_T_5 = 3'h4; // @[OneHot.scala:65:27] wire [3:0] _nodeOut_a_bits_a_mask_sizeOH_T_1 = 4'h4; // @[OneHot.scala:65:12] wire [3:0] _nodeOut_a_bits_a_mask_sizeOH_T_4 = 4'h4; // @[OneHot.scala:65:12] wire [1:0] nodeOut_a_bits_a_mask_sizeOH_shiftAmount = 2'h2; // @[OneHot.scala:64:49] wire [1:0] nodeOut_a_bits_a_mask_sizeOH_shiftAmount_1 = 2'h2; // @[OneHot.scala:64:49] wire [63:0] nodeOut_a_bits_a_1_data = 64'h1; // @[Edges.scala:480:17] wire [28:0] nodeOut_a_bits_a_1_address = 29'h2000000; // @[Edges.scala:480:17] wire [29:0] _nodeOut_a_bits_legal_T_112 = 30'h2010000; // @[Parameters.scala:137:46] wire [29:0] _nodeOut_a_bits_legal_T_113 = 30'h2010000; // @[Parameters.scala:137:46] wire [26:0] _nodeOut_a_bits_legal_T_111 = 27'h2010000; // @[Parameters.scala:137:41] wire [29:0] _nodeOut_a_bits_legal_T_99 = 30'h12000000; // @[Parameters.scala:137:41] wire [29:0] _nodeOut_a_bits_legal_T_100 = 30'h12000000; // @[Parameters.scala:137:46] wire [29:0] _nodeOut_a_bits_legal_T_101 = 30'h12000000; // @[Parameters.scala:137:46] wire [29:0] _nodeOut_a_bits_legal_T_36 = 30'h8000000; // @[Parameters.scala:137:46] wire [29:0] _nodeOut_a_bits_legal_T_37 = 30'h8000000; // @[Parameters.scala:137:46] wire [29:0] _nodeOut_a_bits_legal_T_95 = 30'h8000000; // @[Parameters.scala:137:46] wire [29:0] _nodeOut_a_bits_legal_T_96 = 30'h8000000; // @[Parameters.scala:137:46] wire [28:0] _nodeOut_a_bits_legal_T_94 = 29'hA000000; // @[Parameters.scala:137:41] wire [29:0] _nodeOut_a_bits_legal_T_53 = 30'h10000; // @[Parameters.scala:137:46] wire [29:0] _nodeOut_a_bits_legal_T_54 = 30'h10000; // @[Parameters.scala:137:46] wire [29:0] _nodeOut_a_bits_legal_T_90 = 30'h10000; // @[Parameters.scala:137:46] wire [29:0] _nodeOut_a_bits_legal_T_91 = 30'h10000; // @[Parameters.scala:137:46] wire [26:0] _nodeOut_a_bits_legal_T_89 = 27'h10000; // @[Parameters.scala:137:41] wire [29:0] fixer__a_notFIFO_T_2 = 30'h0; // @[Parameters.scala:137:46] wire [29:0] fixer__a_notFIFO_T_3 = 30'h0; // @[Parameters.scala:137:46] wire [29:0] _nodeOut_a_bits_legal_T_16 = 30'h0; // @[Parameters.scala:137:46] wire [29:0] _nodeOut_a_bits_legal_T_17 = 30'h0; // @[Parameters.scala:137:46] wire [29:0] _nodeOut_a_bits_legal_T_85 = 30'h0; // @[Parameters.scala:137:46] wire [29:0] _nodeOut_a_bits_legal_T_86 = 30'h0; // @[Parameters.scala:137:46] wire [26:0] _nodeOut_a_bits_legal_T_84 = 27'h0; // @[Parameters.scala:137:41] wire [29:0] _nodeOut_a_bits_legal_T_80 = 30'h2100000; // @[Parameters.scala:137:46] wire [29:0] _nodeOut_a_bits_legal_T_81 = 30'h2100000; // @[Parameters.scala:137:46] wire [26:0] _nodeOut_a_bits_legal_T_79 = 27'h2100000; // @[Parameters.scala:137:41] wire [29:0] _nodeOut_a_bits_legal_T_26 = 30'h2000000; // @[Parameters.scala:137:46] wire [29:0] _nodeOut_a_bits_legal_T_27 = 30'h2000000; // @[Parameters.scala:137:46] wire [29:0] _nodeOut_a_bits_legal_T_75 = 30'h2000000; // @[Parameters.scala:137:46] wire [29:0] _nodeOut_a_bits_legal_T_76 = 30'h2000000; // @[Parameters.scala:137:46] wire [26:0] _nodeOut_a_bits_legal_T_74 = 27'h2000000; // @[Parameters.scala:137:41] wire [29:0] _nodeOut_a_bits_legal_T_65 = 30'h2003000; // @[Parameters.scala:137:46] wire [29:0] _nodeOut_a_bits_legal_T_66 = 30'h2003000; // @[Parameters.scala:137:46] wire [26:0] _nodeOut_a_bits_legal_T_64 = 27'h2003000; // @[Parameters.scala:137:41] wire [63:0] nodeOut_a_bits_a_data = 64'h80000000; // @[Edges.scala:480:17] wire [28:0] nodeOut_a_bits_a_address = 29'h1000; // @[Edges.scala:480:17] wire [17:0] _nodeOut_a_bits_legal_T_52 = 18'h11000; // @[Parameters.scala:137:41] wire [29:0] _nodeOut_a_bits_legal_T_40 = 30'h10001000; // @[Parameters.scala:137:41] wire [29:0] _nodeOut_a_bits_legal_T_41 = 30'h10001000; // @[Parameters.scala:137:46] wire [29:0] _nodeOut_a_bits_legal_T_42 = 30'h10001000; // @[Parameters.scala:137:46] wire [28:0] _nodeOut_a_bits_legal_T_35 = 29'h8001000; // @[Parameters.scala:137:41] wire [29:0] _nodeOut_a_bits_legal_T_31 = 30'h2011000; // @[Parameters.scala:137:46] wire [29:0] _nodeOut_a_bits_legal_T_32 = 30'h2011000; // @[Parameters.scala:137:46] wire [26:0] _nodeOut_a_bits_legal_T_30 = 27'h2011000; // @[Parameters.scala:137:41] wire [26:0] _nodeOut_a_bits_legal_T_25 = 27'h2001000; // @[Parameters.scala:137:41] wire [29:0] _nodeOut_a_bits_legal_T_21 = 30'h101000; // @[Parameters.scala:137:46] wire [29:0] _nodeOut_a_bits_legal_T_22 = 30'h101000; // @[Parameters.scala:137:46] wire [21:0] _nodeOut_a_bits_legal_T_20 = 22'h101000; // @[Parameters.scala:137:41] wire [13:0] _nodeOut_a_bits_legal_T_15 = 14'h1000; // @[Parameters.scala:137:41] wire [29:0] _nodeOut_a_bits_legal_T_6 = 30'h2000; // @[Parameters.scala:137:46] wire [29:0] _nodeOut_a_bits_legal_T_7 = 30'h2000; // @[Parameters.scala:137:46] wire [14:0] _nodeOut_a_bits_legal_T_5 = 15'h2000; // @[Parameters.scala:137:41] wire [256:0] fixer__allIDs_FIFOed_T = 257'h1FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF; // @[FIFOFixer.scala:127:48] wire [28:0] _nodeOut_a_bits_legal_T_98 = 29'h12000000; // @[Parameters.scala:137:31] wire [27:0] _nodeOut_a_bits_legal_T_93 = 28'hA000000; // @[Parameters.scala:137:31] wire [25:0] _nodeOut_a_bits_legal_T_88 = 26'h10000; // @[Parameters.scala:137:31] wire [25:0] _nodeOut_a_bits_legal_T_83 = 26'h0; // @[Parameters.scala:137:31] wire [25:0] _nodeOut_a_bits_legal_T_78 = 26'h2100000; // @[Parameters.scala:137:31] wire [25:0] _nodeOut_a_bits_legal_T_63 = 26'h2003000; // @[Parameters.scala:137:31] wire [16:0] _nodeOut_a_bits_legal_T_51 = 17'h11000; // @[Parameters.scala:137:31] wire [28:0] _nodeOut_a_bits_legal_T_39 = 29'h10001000; // @[Parameters.scala:137:31] wire [27:0] _nodeOut_a_bits_legal_T_34 = 28'h8001000; // @[Parameters.scala:137:31] wire [25:0] _nodeOut_a_bits_legal_T_29 = 26'h2011000; // @[Parameters.scala:137:31] wire [25:0] _nodeOut_a_bits_legal_T_24 = 26'h2001000; // @[Parameters.scala:137:31] wire [20:0] _nodeOut_a_bits_legal_T_19 = 21'h101000; // @[Parameters.scala:137:31] wire [13:0] _nodeOut_a_bits_legal_T_4 = 14'h2000; // @[Parameters.scala:137:31] wire [2:0] _nodeOut_a_bits_a_mask_sizeOH_T = 3'h2; // @[Misc.scala:202:34] wire [2:0] _nodeOut_a_bits_a_mask_sizeOH_T_3 = 3'h2; // @[Misc.scala:202:34] wire [25:0] _nodeOut_a_bits_legal_T_110 = 26'h2010000; // @[Parameters.scala:137:31] wire [25:0] _nodeOut_a_bits_legal_T_73 = 26'h2000000; // @[Parameters.scala:137:31] wire [12:0] _nodeOut_a_bits_legal_T_14 = 13'h1000; // @[Parameters.scala:137:31] wire coupler_to_bus_named_pbus_auto_bus_xing_out_a_ready = auto_coupler_to_bus_named_pbus_bus_xing_out_a_ready_0; // @[ClockDomain.scala:14:9] wire coupler_to_bus_named_pbus_auto_bus_xing_out_a_valid; // @[LazyModuleImp.scala:138:7] wire [2:0] coupler_to_bus_named_pbus_auto_bus_xing_out_a_bits_opcode; // @[LazyModuleImp.scala:138:7] wire [2:0] coupler_to_bus_named_pbus_auto_bus_xing_out_a_bits_param; // @[LazyModuleImp.scala:138:7] wire [2:0] coupler_to_bus_named_pbus_auto_bus_xing_out_a_bits_size; // @[LazyModuleImp.scala:138:7] wire [8:0] coupler_to_bus_named_pbus_auto_bus_xing_out_a_bits_source; // @[LazyModuleImp.scala:138:7] wire [28:0] coupler_to_bus_named_pbus_auto_bus_xing_out_a_bits_address; // @[LazyModuleImp.scala:138:7] wire [7:0] coupler_to_bus_named_pbus_auto_bus_xing_out_a_bits_mask; // @[LazyModuleImp.scala:138:7] wire [63:0] coupler_to_bus_named_pbus_auto_bus_xing_out_a_bits_data; // @[LazyModuleImp.scala:138:7] wire coupler_to_bus_named_pbus_auto_bus_xing_out_a_bits_corrupt; // @[LazyModuleImp.scala:138:7] wire coupler_to_bus_named_pbus_auto_bus_xing_out_d_ready; // @[LazyModuleImp.scala:138:7] wire coupler_to_bus_named_pbus_auto_bus_xing_out_d_valid = auto_coupler_to_bus_named_pbus_bus_xing_out_d_valid_0; // @[ClockDomain.scala:14:9] wire [2:0] coupler_to_bus_named_pbus_auto_bus_xing_out_d_bits_opcode = auto_coupler_to_bus_named_pbus_bus_xing_out_d_bits_opcode_0; // @[ClockDomain.scala:14:9] wire [1:0] coupler_to_bus_named_pbus_auto_bus_xing_out_d_bits_param = auto_coupler_to_bus_named_pbus_bus_xing_out_d_bits_param_0; // @[ClockDomain.scala:14:9] wire [2:0] coupler_to_bus_named_pbus_auto_bus_xing_out_d_bits_size = auto_coupler_to_bus_named_pbus_bus_xing_out_d_bits_size_0; // @[ClockDomain.scala:14:9] wire [8:0] coupler_to_bus_named_pbus_auto_bus_xing_out_d_bits_source = auto_coupler_to_bus_named_pbus_bus_xing_out_d_bits_source_0; // @[ClockDomain.scala:14:9] wire coupler_to_bus_named_pbus_auto_bus_xing_out_d_bits_sink = auto_coupler_to_bus_named_pbus_bus_xing_out_d_bits_sink_0; // @[ClockDomain.scala:14:9] wire coupler_to_bus_named_pbus_auto_bus_xing_out_d_bits_denied = auto_coupler_to_bus_named_pbus_bus_xing_out_d_bits_denied_0; // @[ClockDomain.scala:14:9] wire [63:0] coupler_to_bus_named_pbus_auto_bus_xing_out_d_bits_data = auto_coupler_to_bus_named_pbus_bus_xing_out_d_bits_data_0; // @[ClockDomain.scala:14:9] wire coupler_to_bus_named_pbus_auto_bus_xing_out_d_bits_corrupt = auto_coupler_to_bus_named_pbus_bus_xing_out_d_bits_corrupt_0; // @[ClockDomain.scala:14:9] wire cbus_clock_groups_auto_in_member_cbus_0_clock = auto_cbus_clock_groups_in_member_cbus_0_clock_0; // @[ClockGroup.scala:53:9] wire cbus_clock_groups_auto_in_member_cbus_0_reset = auto_cbus_clock_groups_in_member_cbus_0_reset_0; // @[ClockGroup.scala:53:9] wire bus_xingIn_a_ready; // @[MixedNode.scala:551:17] wire bus_xingIn_a_valid = auto_bus_xing_in_a_valid_0; // @[ClockDomain.scala:14:9] wire [2:0] bus_xingIn_a_bits_opcode = auto_bus_xing_in_a_bits_opcode_0; // @[ClockDomain.scala:14:9] wire [2:0] bus_xingIn_a_bits_param = auto_bus_xing_in_a_bits_param_0; // @[ClockDomain.scala:14:9] wire [3:0] bus_xingIn_a_bits_size = auto_bus_xing_in_a_bits_size_0; // @[ClockDomain.scala:14:9] wire [7:0] bus_xingIn_a_bits_source = auto_bus_xing_in_a_bits_source_0; // @[ClockDomain.scala:14:9] wire [28:0] bus_xingIn_a_bits_address = auto_bus_xing_in_a_bits_address_0; // @[ClockDomain.scala:14:9] wire [7:0] bus_xingIn_a_bits_mask = auto_bus_xing_in_a_bits_mask_0; // @[ClockDomain.scala:14:9] wire [63:0] bus_xingIn_a_bits_data = auto_bus_xing_in_a_bits_data_0; // @[ClockDomain.scala:14:9] wire bus_xingIn_a_bits_corrupt = auto_bus_xing_in_a_bits_corrupt_0; // @[ClockDomain.scala:14:9] wire bus_xingIn_d_ready = auto_bus_xing_in_d_ready_0; // @[ClockDomain.scala:14:9] wire bus_xingIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] bus_xingIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] bus_xingIn_d_bits_param; // @[MixedNode.scala:551:17] wire [3:0] bus_xingIn_d_bits_size; // @[MixedNode.scala:551:17] wire [7:0] bus_xingIn_d_bits_source; // @[MixedNode.scala:551:17] wire bus_xingIn_d_bits_sink; // @[MixedNode.scala:551:17] wire bus_xingIn_d_bits_denied; // @[MixedNode.scala:551:17] wire [63:0] bus_xingIn_d_bits_data; // @[MixedNode.scala:551:17] wire bus_xingIn_d_bits_corrupt; // @[MixedNode.scala:551:17] wire [2:0] auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_opcode_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_param_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_size_0; // @[ClockDomain.scala:14:9] wire [8:0] auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_source_0; // @[ClockDomain.scala:14:9] wire [20:0] auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_address_0; // @[ClockDomain.scala:14:9] wire [7:0] auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_mask_0; // @[ClockDomain.scala:14:9] wire [63:0] auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_data_0; // @[ClockDomain.scala:14:9] wire auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_corrupt_0; // @[ClockDomain.scala:14:9] wire auto_coupler_to_prci_ctrl_fixer_anon_out_a_valid_0; // @[ClockDomain.scala:14:9] wire auto_coupler_to_prci_ctrl_fixer_anon_out_d_ready_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_opcode_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_param_0; // @[ClockDomain.scala:14:9] wire [1:0] auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_size_0; // @[ClockDomain.scala:14:9] wire [12:0] auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_source_0; // @[ClockDomain.scala:14:9] wire [16:0] auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_address_0; // @[ClockDomain.scala:14:9] wire [7:0] auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_mask_0; // @[ClockDomain.scala:14:9] wire [63:0] auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_data_0; // @[ClockDomain.scala:14:9] wire auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_corrupt_0; // @[ClockDomain.scala:14:9] wire auto_coupler_to_bootrom_fragmenter_anon_out_a_valid_0; // @[ClockDomain.scala:14:9] wire auto_coupler_to_bootrom_fragmenter_anon_out_d_ready_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_to_debug_fragmenter_anon_out_a_bits_opcode_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_to_debug_fragmenter_anon_out_a_bits_param_0; // @[ClockDomain.scala:14:9] wire [1:0] auto_coupler_to_debug_fragmenter_anon_out_a_bits_size_0; // @[ClockDomain.scala:14:9] wire [12:0] auto_coupler_to_debug_fragmenter_anon_out_a_bits_source_0; // @[ClockDomain.scala:14:9] wire [11:0] auto_coupler_to_debug_fragmenter_anon_out_a_bits_address_0; // @[ClockDomain.scala:14:9] wire [7:0] auto_coupler_to_debug_fragmenter_anon_out_a_bits_mask_0; // @[ClockDomain.scala:14:9] wire [63:0] auto_coupler_to_debug_fragmenter_anon_out_a_bits_data_0; // @[ClockDomain.scala:14:9] wire auto_coupler_to_debug_fragmenter_anon_out_a_bits_corrupt_0; // @[ClockDomain.scala:14:9] wire auto_coupler_to_debug_fragmenter_anon_out_a_valid_0; // @[ClockDomain.scala:14:9] wire auto_coupler_to_debug_fragmenter_anon_out_d_ready_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_to_plic_fragmenter_anon_out_a_bits_opcode_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_to_plic_fragmenter_anon_out_a_bits_param_0; // @[ClockDomain.scala:14:9] wire [1:0] auto_coupler_to_plic_fragmenter_anon_out_a_bits_size_0; // @[ClockDomain.scala:14:9] wire [12:0] auto_coupler_to_plic_fragmenter_anon_out_a_bits_source_0; // @[ClockDomain.scala:14:9] wire [27:0] auto_coupler_to_plic_fragmenter_anon_out_a_bits_address_0; // @[ClockDomain.scala:14:9] wire [7:0] auto_coupler_to_plic_fragmenter_anon_out_a_bits_mask_0; // @[ClockDomain.scala:14:9] wire [63:0] auto_coupler_to_plic_fragmenter_anon_out_a_bits_data_0; // @[ClockDomain.scala:14:9] wire auto_coupler_to_plic_fragmenter_anon_out_a_bits_corrupt_0; // @[ClockDomain.scala:14:9] wire auto_coupler_to_plic_fragmenter_anon_out_a_valid_0; // @[ClockDomain.scala:14:9] wire auto_coupler_to_plic_fragmenter_anon_out_d_ready_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_to_clint_fragmenter_anon_out_a_bits_opcode_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_to_clint_fragmenter_anon_out_a_bits_param_0; // @[ClockDomain.scala:14:9] wire [1:0] auto_coupler_to_clint_fragmenter_anon_out_a_bits_size_0; // @[ClockDomain.scala:14:9] wire [12:0] auto_coupler_to_clint_fragmenter_anon_out_a_bits_source_0; // @[ClockDomain.scala:14:9] wire [25:0] auto_coupler_to_clint_fragmenter_anon_out_a_bits_address_0; // @[ClockDomain.scala:14:9] wire [7:0] auto_coupler_to_clint_fragmenter_anon_out_a_bits_mask_0; // @[ClockDomain.scala:14:9] wire [63:0] auto_coupler_to_clint_fragmenter_anon_out_a_bits_data_0; // @[ClockDomain.scala:14:9] wire auto_coupler_to_clint_fragmenter_anon_out_a_bits_corrupt_0; // @[ClockDomain.scala:14:9] wire auto_coupler_to_clint_fragmenter_anon_out_a_valid_0; // @[ClockDomain.scala:14:9] wire auto_coupler_to_clint_fragmenter_anon_out_d_ready_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_opcode_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_param_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_size_0; // @[ClockDomain.scala:14:9] wire [8:0] auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_source_0; // @[ClockDomain.scala:14:9] wire [28:0] auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_address_0; // @[ClockDomain.scala:14:9] wire [7:0] auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_mask_0; // @[ClockDomain.scala:14:9] wire [63:0] auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_data_0; // @[ClockDomain.scala:14:9] wire auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_corrupt_0; // @[ClockDomain.scala:14:9] wire auto_coupler_to_bus_named_pbus_bus_xing_out_a_valid_0; // @[ClockDomain.scala:14:9] wire auto_coupler_to_bus_named_pbus_bus_xing_out_d_ready_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_to_l2_ctrl_buffer_out_a_bits_opcode_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_to_l2_ctrl_buffer_out_a_bits_param_0; // @[ClockDomain.scala:14:9] wire [1:0] auto_coupler_to_l2_ctrl_buffer_out_a_bits_size_0; // @[ClockDomain.scala:14:9] wire [12:0] auto_coupler_to_l2_ctrl_buffer_out_a_bits_source_0; // @[ClockDomain.scala:14:9] wire [25:0] auto_coupler_to_l2_ctrl_buffer_out_a_bits_address_0; // @[ClockDomain.scala:14:9] wire [7:0] auto_coupler_to_l2_ctrl_buffer_out_a_bits_mask_0; // @[ClockDomain.scala:14:9] wire [63:0] auto_coupler_to_l2_ctrl_buffer_out_a_bits_data_0; // @[ClockDomain.scala:14:9] wire auto_coupler_to_l2_ctrl_buffer_out_a_bits_corrupt_0; // @[ClockDomain.scala:14:9] wire auto_coupler_to_l2_ctrl_buffer_out_a_valid_0; // @[ClockDomain.scala:14:9] wire auto_coupler_to_l2_ctrl_buffer_out_d_ready_0; // @[ClockDomain.scala:14:9] wire auto_fixedClockNode_anon_out_5_clock_0; // @[ClockDomain.scala:14:9] wire auto_fixedClockNode_anon_out_5_reset_0; // @[ClockDomain.scala:14:9] wire auto_fixedClockNode_anon_out_4_clock_0; // @[ClockDomain.scala:14:9] wire auto_fixedClockNode_anon_out_4_reset_0; // @[ClockDomain.scala:14:9] wire auto_fixedClockNode_anon_out_3_clock_0; // @[ClockDomain.scala:14:9] wire auto_fixedClockNode_anon_out_3_reset_0; // @[ClockDomain.scala:14:9] wire auto_fixedClockNode_anon_out_2_clock_0; // @[ClockDomain.scala:14:9] wire auto_fixedClockNode_anon_out_2_reset_0; // @[ClockDomain.scala:14:9] wire auto_fixedClockNode_anon_out_1_clock_0; // @[ClockDomain.scala:14:9] wire auto_fixedClockNode_anon_out_1_reset_0; // @[ClockDomain.scala:14:9] wire auto_fixedClockNode_anon_out_0_clock_0; // @[ClockDomain.scala:14:9] wire auto_fixedClockNode_anon_out_0_reset_0; // @[ClockDomain.scala:14:9] wire auto_bus_xing_in_a_ready_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_bus_xing_in_d_bits_opcode_0; // @[ClockDomain.scala:14:9] wire [1:0] auto_bus_xing_in_d_bits_param_0; // @[ClockDomain.scala:14:9] wire [3:0] auto_bus_xing_in_d_bits_size_0; // @[ClockDomain.scala:14:9] wire [7:0] auto_bus_xing_in_d_bits_source_0; // @[ClockDomain.scala:14:9] wire auto_bus_xing_in_d_bits_sink_0; // @[ClockDomain.scala:14:9] wire auto_bus_xing_in_d_bits_denied_0; // @[ClockDomain.scala:14:9] wire [63:0] auto_bus_xing_in_d_bits_data_0; // @[ClockDomain.scala:14:9] wire auto_bus_xing_in_d_bits_corrupt_0; // @[ClockDomain.scala:14:9] wire auto_bus_xing_in_d_valid_0; // @[ClockDomain.scala:14:9] wire clockSinkNodeIn_clock; // @[MixedNode.scala:551:17] wire clockSinkNodeIn_reset; // @[MixedNode.scala:551:17] wire childClock; // @[LazyModuleImp.scala:155:31] wire childReset; // @[LazyModuleImp.scala:158:31] wire cbus_clock_groups_nodeIn_member_cbus_0_clock = cbus_clock_groups_auto_in_member_cbus_0_clock; // @[ClockGroup.scala:53:9] wire cbus_clock_groups_nodeOut_member_cbus_0_clock; // @[MixedNode.scala:542:17] wire cbus_clock_groups_nodeIn_member_cbus_0_reset = cbus_clock_groups_auto_in_member_cbus_0_reset; // @[ClockGroup.scala:53:9] wire cbus_clock_groups_nodeOut_member_cbus_0_reset; // @[MixedNode.scala:542:17] wire clockGroup_auto_in_member_cbus_0_clock = cbus_clock_groups_auto_out_member_cbus_0_clock; // @[ClockGroup.scala:24:9, :53:9] wire clockGroup_auto_in_member_cbus_0_reset = cbus_clock_groups_auto_out_member_cbus_0_reset; // @[ClockGroup.scala:24:9, :53:9] assign cbus_clock_groups_auto_out_member_cbus_0_clock = cbus_clock_groups_nodeOut_member_cbus_0_clock; // @[ClockGroup.scala:53:9] assign cbus_clock_groups_auto_out_member_cbus_0_reset = cbus_clock_groups_nodeOut_member_cbus_0_reset; // @[ClockGroup.scala:53:9] assign cbus_clock_groups_nodeOut_member_cbus_0_clock = cbus_clock_groups_nodeIn_member_cbus_0_clock; // @[MixedNode.scala:542:17, :551:17] assign cbus_clock_groups_nodeOut_member_cbus_0_reset = cbus_clock_groups_nodeIn_member_cbus_0_reset; // @[MixedNode.scala:542:17, :551:17] wire clockGroup_nodeIn_member_cbus_0_clock = clockGroup_auto_in_member_cbus_0_clock; // @[ClockGroup.scala:24:9] wire clockGroup_nodeOut_clock; // @[MixedNode.scala:542:17] wire clockGroup_nodeIn_member_cbus_0_reset = clockGroup_auto_in_member_cbus_0_reset; // @[ClockGroup.scala:24:9] wire clockGroup_nodeOut_reset; // @[MixedNode.scala:542:17] wire clockGroup_auto_out_clock; // @[ClockGroup.scala:24:9] wire clockGroup_auto_out_reset; // @[ClockGroup.scala:24:9] assign clockGroup_auto_out_clock = clockGroup_nodeOut_clock; // @[ClockGroup.scala:24:9] assign clockGroup_auto_out_reset = clockGroup_nodeOut_reset; // @[ClockGroup.scala:24:9] assign clockGroup_nodeOut_clock = clockGroup_nodeIn_member_cbus_0_clock; // @[MixedNode.scala:542:17, :551:17] assign clockGroup_nodeOut_reset = clockGroup_nodeIn_member_cbus_0_reset; // @[MixedNode.scala:542:17, :551:17] wire fixer_anonIn_a_ready; // @[MixedNode.scala:551:17] wire fixer_anonIn_a_valid = fixer_auto_anon_in_a_valid; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_anonIn_a_bits_opcode = fixer_auto_anon_in_a_bits_opcode; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_anonIn_a_bits_param = fixer_auto_anon_in_a_bits_param; // @[FIFOFixer.scala:50:9] wire [3:0] fixer_anonIn_a_bits_size = fixer_auto_anon_in_a_bits_size; // @[FIFOFixer.scala:50:9] wire [8:0] fixer_anonIn_a_bits_source = fixer_auto_anon_in_a_bits_source; // @[FIFOFixer.scala:50:9] wire [28:0] fixer_anonIn_a_bits_address = fixer_auto_anon_in_a_bits_address; // @[FIFOFixer.scala:50:9] wire [7:0] fixer_anonIn_a_bits_mask = fixer_auto_anon_in_a_bits_mask; // @[FIFOFixer.scala:50:9] wire [63:0] fixer_anonIn_a_bits_data = fixer_auto_anon_in_a_bits_data; // @[FIFOFixer.scala:50:9] wire fixer_anonIn_a_bits_corrupt = fixer_auto_anon_in_a_bits_corrupt; // @[FIFOFixer.scala:50:9] wire fixer_anonIn_d_ready = fixer_auto_anon_in_d_ready; // @[FIFOFixer.scala:50:9] wire fixer_anonIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] fixer_anonIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] fixer_anonIn_d_bits_param; // @[MixedNode.scala:551:17] wire [3:0] fixer_anonIn_d_bits_size; // @[MixedNode.scala:551:17] wire [8:0] fixer_anonIn_d_bits_source; // @[MixedNode.scala:551:17] wire fixer_anonIn_d_bits_sink; // @[MixedNode.scala:551:17] wire fixer_anonIn_d_bits_denied; // @[MixedNode.scala:551:17] wire [63:0] fixer_anonIn_d_bits_data; // @[MixedNode.scala:551:17] wire fixer_anonIn_d_bits_corrupt; // @[MixedNode.scala:551:17] wire fixer_anonOut_a_ready = fixer_auto_anon_out_a_ready; // @[FIFOFixer.scala:50:9] wire fixer_anonOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] fixer_anonOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] fixer_anonOut_a_bits_param; // @[MixedNode.scala:542:17] wire [3:0] fixer_anonOut_a_bits_size; // @[MixedNode.scala:542:17] wire [8:0] fixer_anonOut_a_bits_source; // @[MixedNode.scala:542:17] wire [28:0] fixer_anonOut_a_bits_address; // @[MixedNode.scala:542:17] wire [7:0] fixer_anonOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [63:0] fixer_anonOut_a_bits_data; // @[MixedNode.scala:542:17] wire fixer_anonOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire fixer_anonOut_d_ready; // @[MixedNode.scala:542:17] wire fixer_anonOut_d_valid = fixer_auto_anon_out_d_valid; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_anonOut_d_bits_opcode = fixer_auto_anon_out_d_bits_opcode; // @[FIFOFixer.scala:50:9] wire [1:0] fixer_anonOut_d_bits_param = fixer_auto_anon_out_d_bits_param; // @[FIFOFixer.scala:50:9] wire [3:0] fixer_anonOut_d_bits_size = fixer_auto_anon_out_d_bits_size; // @[FIFOFixer.scala:50:9] wire [8:0] fixer_anonOut_d_bits_source = fixer_auto_anon_out_d_bits_source; // @[FIFOFixer.scala:50:9] wire fixer_anonOut_d_bits_sink = fixer_auto_anon_out_d_bits_sink; // @[FIFOFixer.scala:50:9] wire fixer_anonOut_d_bits_denied = fixer_auto_anon_out_d_bits_denied; // @[FIFOFixer.scala:50:9] wire [63:0] fixer_anonOut_d_bits_data = fixer_auto_anon_out_d_bits_data; // @[FIFOFixer.scala:50:9] wire fixer_anonOut_d_bits_corrupt = fixer_auto_anon_out_d_bits_corrupt; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_in_a_ready; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_auto_anon_in_d_bits_opcode; // @[FIFOFixer.scala:50:9] wire [1:0] fixer_auto_anon_in_d_bits_param; // @[FIFOFixer.scala:50:9] wire [3:0] fixer_auto_anon_in_d_bits_size; // @[FIFOFixer.scala:50:9] wire [8:0] fixer_auto_anon_in_d_bits_source; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_in_d_bits_sink; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_in_d_bits_denied; // @[FIFOFixer.scala:50:9] wire [63:0] fixer_auto_anon_in_d_bits_data; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_in_d_bits_corrupt; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_in_d_valid; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_auto_anon_out_a_bits_opcode; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_auto_anon_out_a_bits_param; // @[FIFOFixer.scala:50:9] wire [3:0] fixer_auto_anon_out_a_bits_size; // @[FIFOFixer.scala:50:9] wire [8:0] fixer_auto_anon_out_a_bits_source; // @[FIFOFixer.scala:50:9] wire [28:0] fixer_auto_anon_out_a_bits_address; // @[FIFOFixer.scala:50:9] wire [7:0] fixer_auto_anon_out_a_bits_mask; // @[FIFOFixer.scala:50:9] wire [63:0] fixer_auto_anon_out_a_bits_data; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_out_a_bits_corrupt; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_out_a_valid; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_out_d_ready; // @[FIFOFixer.scala:50:9] wire fixer__anonOut_a_valid_T_2; // @[FIFOFixer.scala:95:33] wire fixer__anonIn_a_ready_T_2 = fixer_anonOut_a_ready; // @[FIFOFixer.scala:96:33] assign fixer_auto_anon_out_a_valid = fixer_anonOut_a_valid; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_out_a_bits_opcode = fixer_anonOut_a_bits_opcode; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_out_a_bits_param = fixer_anonOut_a_bits_param; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_out_a_bits_size = fixer_anonOut_a_bits_size; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_out_a_bits_source = fixer_anonOut_a_bits_source; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_out_a_bits_address = fixer_anonOut_a_bits_address; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_out_a_bits_mask = fixer_anonOut_a_bits_mask; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_out_a_bits_data = fixer_anonOut_a_bits_data; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_out_a_bits_corrupt = fixer_anonOut_a_bits_corrupt; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_out_d_ready = fixer_anonOut_d_ready; // @[FIFOFixer.scala:50:9] assign fixer_anonIn_d_valid = fixer_anonOut_d_valid; // @[MixedNode.scala:542:17, :551:17] assign fixer_anonIn_d_bits_opcode = fixer_anonOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign fixer_anonIn_d_bits_param = fixer_anonOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17] assign fixer_anonIn_d_bits_size = fixer_anonOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17] assign fixer_anonIn_d_bits_source = fixer_anonOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17] assign fixer_anonIn_d_bits_sink = fixer_anonOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17] assign fixer_anonIn_d_bits_denied = fixer_anonOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17] assign fixer_anonIn_d_bits_data = fixer_anonOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17] assign fixer_anonIn_d_bits_corrupt = fixer_anonOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign fixer_auto_anon_in_a_ready = fixer_anonIn_a_ready; // @[FIFOFixer.scala:50:9] assign fixer__anonOut_a_valid_T_2 = fixer_anonIn_a_valid; // @[FIFOFixer.scala:95:33] assign fixer_anonOut_a_bits_opcode = fixer_anonIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign fixer_anonOut_a_bits_param = fixer_anonIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17] assign fixer_anonOut_a_bits_size = fixer_anonIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17] assign fixer_anonOut_a_bits_source = fixer_anonIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17] assign fixer_anonOut_a_bits_address = fixer_anonIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17] wire [28:0] fixer__a_notFIFO_T = fixer_anonIn_a_bits_address; // @[Parameters.scala:137:31] wire [28:0] fixer__a_id_T = fixer_anonIn_a_bits_address; // @[Parameters.scala:137:31] assign fixer_anonOut_a_bits_mask = fixer_anonIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign fixer_anonOut_a_bits_data = fixer_anonIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17] assign fixer_anonOut_a_bits_corrupt = fixer_anonIn_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign fixer_anonOut_d_ready = fixer_anonIn_d_ready; // @[MixedNode.scala:542:17, :551:17] assign fixer_auto_anon_in_d_valid = fixer_anonIn_d_valid; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_in_d_bits_opcode = fixer_anonIn_d_bits_opcode; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_in_d_bits_param = fixer_anonIn_d_bits_param; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_in_d_bits_size = fixer_anonIn_d_bits_size; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_in_d_bits_source = fixer_anonIn_d_bits_source; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_in_d_bits_sink = fixer_anonIn_d_bits_sink; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_in_d_bits_denied = fixer_anonIn_d_bits_denied; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_in_d_bits_data = fixer_anonIn_d_bits_data; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_in_d_bits_corrupt = fixer_anonIn_d_bits_corrupt; // @[FIFOFixer.scala:50:9] wire [29:0] fixer__a_notFIFO_T_1 = {1'h0, fixer__a_notFIFO_T}; // @[Parameters.scala:137:{31,41}] wire [29:0] fixer__a_id_T_1 = {1'h0, fixer__a_id_T}; // @[Parameters.scala:137:{31,41}] wire [29:0] fixer__a_id_T_2 = fixer__a_id_T_1 & 30'h1A113000; // @[Parameters.scala:137:{41,46}] wire [29:0] fixer__a_id_T_3 = fixer__a_id_T_2; // @[Parameters.scala:137:46] wire fixer__a_id_T_4 = fixer__a_id_T_3 == 30'h0; // @[Parameters.scala:137:{46,59}] wire [28:0] fixer__a_id_T_5 = {fixer_anonIn_a_bits_address[28:13], fixer_anonIn_a_bits_address[12:0] ^ 13'h1000}; // @[Parameters.scala:137:31] wire [29:0] fixer__a_id_T_6 = {1'h0, fixer__a_id_T_5}; // @[Parameters.scala:137:{31,41}] wire [29:0] fixer__a_id_T_7 = fixer__a_id_T_6 & 30'h1A113000; // @[Parameters.scala:137:{41,46}] wire [29:0] fixer__a_id_T_8 = fixer__a_id_T_7; // @[Parameters.scala:137:46] wire fixer__a_id_T_9 = fixer__a_id_T_8 == 30'h0; // @[Parameters.scala:137:{46,59}] wire [28:0] fixer__a_id_T_10 = fixer_anonIn_a_bits_address ^ 29'h10000000; // @[Parameters.scala:137:31] wire [29:0] fixer__a_id_T_11 = {1'h0, fixer__a_id_T_10}; // @[Parameters.scala:137:{31,41}] wire [29:0] fixer__a_id_T_12 = fixer__a_id_T_11 & 30'h1A113000; // @[Parameters.scala:137:{41,46}] wire [29:0] fixer__a_id_T_13 = fixer__a_id_T_12; // @[Parameters.scala:137:46] wire fixer__a_id_T_14 = fixer__a_id_T_13 == 30'h0; // @[Parameters.scala:137:{46,59}] wire fixer__a_id_T_15 = fixer__a_id_T_9 | fixer__a_id_T_14; // @[Parameters.scala:629:89] wire [28:0] fixer__a_id_T_16 = {fixer_anonIn_a_bits_address[28:14], fixer_anonIn_a_bits_address[13:0] ^ 14'h3000}; // @[Parameters.scala:137:31] wire [29:0] fixer__a_id_T_17 = {1'h0, fixer__a_id_T_16}; // @[Parameters.scala:137:{31,41}] wire [29:0] fixer__a_id_T_18 = fixer__a_id_T_17 & 30'h1A113000; // @[Parameters.scala:137:{41,46}] wire [29:0] fixer__a_id_T_19 = fixer__a_id_T_18; // @[Parameters.scala:137:46] wire fixer__a_id_T_20 = fixer__a_id_T_19 == 30'h0; // @[Parameters.scala:137:{46,59}] wire fixer__a_id_T_48 = fixer__a_id_T_20; // @[Mux.scala:30:73] wire [28:0] fixer__a_id_T_21 = {fixer_anonIn_a_bits_address[28:17], fixer_anonIn_a_bits_address[16:0] ^ 17'h10000}; // @[Parameters.scala:137:31] wire [29:0] fixer__a_id_T_22 = {1'h0, fixer__a_id_T_21}; // @[Parameters.scala:137:{31,41}] wire [29:0] fixer__a_id_T_23 = fixer__a_id_T_22 & 30'h1A110000; // @[Parameters.scala:137:{41,46}] wire [29:0] fixer__a_id_T_24 = fixer__a_id_T_23; // @[Parameters.scala:137:46] wire fixer__a_id_T_25 = fixer__a_id_T_24 == 30'h0; // @[Parameters.scala:137:{46,59}] wire [28:0] fixer__a_id_T_26 = {fixer_anonIn_a_bits_address[28:21], fixer_anonIn_a_bits_address[20:0] ^ 21'h100000}; // @[Parameters.scala:137:31] wire [29:0] fixer__a_id_T_27 = {1'h0, fixer__a_id_T_26}; // @[Parameters.scala:137:{31,41}] wire [29:0] fixer__a_id_T_28 = fixer__a_id_T_27 & 30'h1A103000; // @[Parameters.scala:137:{41,46}] wire [29:0] fixer__a_id_T_29 = fixer__a_id_T_28; // @[Parameters.scala:137:46] wire fixer__a_id_T_30 = fixer__a_id_T_29 == 30'h0; // @[Parameters.scala:137:{46,59}] wire [28:0] fixer__a_id_T_31 = {fixer_anonIn_a_bits_address[28:26], fixer_anonIn_a_bits_address[25:0] ^ 26'h2000000}; // @[Parameters.scala:137:31] wire [29:0] fixer__a_id_T_32 = {1'h0, fixer__a_id_T_31}; // @[Parameters.scala:137:{31,41}] wire [29:0] fixer__a_id_T_33 = fixer__a_id_T_32 & 30'h1A110000; // @[Parameters.scala:137:{41,46}] wire [29:0] fixer__a_id_T_34 = fixer__a_id_T_33; // @[Parameters.scala:137:46] wire fixer__a_id_T_35 = fixer__a_id_T_34 == 30'h0; // @[Parameters.scala:137:{46,59}] wire [28:0] fixer__a_id_T_36 = {fixer_anonIn_a_bits_address[28:26], fixer_anonIn_a_bits_address[25:0] ^ 26'h2010000}; // @[Parameters.scala:137:31] wire [29:0] fixer__a_id_T_37 = {1'h0, fixer__a_id_T_36}; // @[Parameters.scala:137:{31,41}] wire [29:0] fixer__a_id_T_38 = fixer__a_id_T_37 & 30'h1A113000; // @[Parameters.scala:137:{41,46}] wire [29:0] fixer__a_id_T_39 = fixer__a_id_T_38; // @[Parameters.scala:137:46] wire fixer__a_id_T_40 = fixer__a_id_T_39 == 30'h0; // @[Parameters.scala:137:{46,59}] wire [28:0] fixer__a_id_T_41 = {fixer_anonIn_a_bits_address[28], fixer_anonIn_a_bits_address[27:0] ^ 28'h8000000}; // @[Parameters.scala:137:31] wire [29:0] fixer__a_id_T_42 = {1'h0, fixer__a_id_T_41}; // @[Parameters.scala:137:{31,41}] wire [29:0] fixer__a_id_T_43 = fixer__a_id_T_42 & 30'h18000000; // @[Parameters.scala:137:{41,46}] wire [29:0] fixer__a_id_T_44 = fixer__a_id_T_43; // @[Parameters.scala:137:46] wire fixer__a_id_T_45 = fixer__a_id_T_44 == 30'h0; // @[Parameters.scala:137:{46,59}] wire [1:0] fixer__a_id_T_46 = {fixer__a_id_T_4, 1'h0}; // @[Mux.scala:30:73] wire [2:0] fixer__a_id_T_47 = fixer__a_id_T_15 ? 3'h5 : 3'h0; // @[Mux.scala:30:73] wire [2:0] fixer__a_id_T_49 = {fixer__a_id_T_25, 2'h0}; // @[Mux.scala:30:73] wire [2:0] fixer__a_id_T_50 = fixer__a_id_T_30 ? 3'h6 : 3'h0; // @[Mux.scala:30:73] wire [2:0] fixer__a_id_T_51 = {3{fixer__a_id_T_35}}; // @[Mux.scala:30:73] wire [1:0] fixer__a_id_T_52 = {2{fixer__a_id_T_40}}; // @[Mux.scala:30:73] wire [3:0] fixer__a_id_T_53 = {fixer__a_id_T_45, 3'h0}; // @[Mux.scala:30:73] wire [2:0] fixer__a_id_T_54 = {1'h0, fixer__a_id_T_46} | fixer__a_id_T_47; // @[Mux.scala:30:73] wire [2:0] fixer__a_id_T_55 = {fixer__a_id_T_54[2:1], fixer__a_id_T_54[0] | fixer__a_id_T_48}; // @[Mux.scala:30:73] wire [2:0] fixer__a_id_T_56 = fixer__a_id_T_55 | fixer__a_id_T_49; // @[Mux.scala:30:73] wire [2:0] fixer__a_id_T_57 = fixer__a_id_T_56 | fixer__a_id_T_50; // @[Mux.scala:30:73] wire [2:0] fixer__a_id_T_58 = fixer__a_id_T_57 | fixer__a_id_T_51; // @[Mux.scala:30:73] wire [2:0] fixer__a_id_T_59 = {fixer__a_id_T_58[2], fixer__a_id_T_58[1:0] | fixer__a_id_T_52}; // @[Mux.scala:30:73] wire [3:0] fixer__a_id_T_60 = {1'h0, fixer__a_id_T_59} | fixer__a_id_T_53; // @[Mux.scala:30:73] wire [3:0] fixer_a_id = fixer__a_id_T_60; // @[Mux.scala:30:73] wire fixer_a_noDomain = fixer_a_id == 4'h0; // @[Mux.scala:30:73] wire fixer__a_first_T = fixer_anonIn_a_ready & fixer_anonIn_a_valid; // @[Decoupled.scala:51:35] wire [26:0] fixer__a_first_beats1_decode_T = 27'hFFF << fixer_anonIn_a_bits_size; // @[package.scala:243:71] wire [11:0] fixer__a_first_beats1_decode_T_1 = fixer__a_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] fixer__a_first_beats1_decode_T_2 = ~fixer__a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] fixer_a_first_beats1_decode = fixer__a_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire fixer__a_first_beats1_opdata_T = fixer_anonIn_a_bits_opcode[2]; // @[Edges.scala:92:37] wire fixer_a_first_beats1_opdata = ~fixer__a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [8:0] fixer_a_first_beats1 = fixer_a_first_beats1_opdata ? fixer_a_first_beats1_decode : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [8:0] fixer_a_first_counter; // @[Edges.scala:229:27] wire [9:0] fixer__a_first_counter1_T = {1'h0, fixer_a_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] fixer_a_first_counter1 = fixer__a_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire fixer_a_first = fixer_a_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire fixer__a_first_last_T = fixer_a_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire fixer__a_first_last_T_1 = fixer_a_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire fixer_a_first_last = fixer__a_first_last_T | fixer__a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire fixer_a_first_done = fixer_a_first_last & fixer__a_first_T; // @[Decoupled.scala:51:35] wire [8:0] fixer__a_first_count_T = ~fixer_a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] fixer_a_first_count = fixer_a_first_beats1 & fixer__a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] fixer__a_first_counter_T = fixer_a_first ? fixer_a_first_beats1 : fixer_a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire fixer__d_first_T = fixer_anonOut_d_ready & fixer_anonOut_d_valid; // @[Decoupled.scala:51:35] wire [26:0] fixer__d_first_beats1_decode_T = 27'hFFF << fixer_anonOut_d_bits_size; // @[package.scala:243:71] wire [11:0] fixer__d_first_beats1_decode_T_1 = fixer__d_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] fixer__d_first_beats1_decode_T_2 = ~fixer__d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] fixer_d_first_beats1_decode = fixer__d_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire fixer_d_first_beats1_opdata = fixer_anonOut_d_bits_opcode[0]; // @[Edges.scala:106:36] wire [8:0] fixer_d_first_beats1 = fixer_d_first_beats1_opdata ? fixer_d_first_beats1_decode : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] fixer_d_first_counter; // @[Edges.scala:229:27] wire [9:0] fixer__d_first_counter1_T = {1'h0, fixer_d_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] fixer_d_first_counter1 = fixer__d_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire fixer_d_first_first = fixer_d_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire fixer__d_first_last_T = fixer_d_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire fixer__d_first_last_T_1 = fixer_d_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire fixer_d_first_last = fixer__d_first_last_T | fixer__d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire fixer_d_first_done = fixer_d_first_last & fixer__d_first_T; // @[Decoupled.scala:51:35] wire [8:0] fixer__d_first_count_T = ~fixer_d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] fixer_d_first_count = fixer_d_first_beats1 & fixer__d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] fixer__d_first_counter_T = fixer_d_first_first ? fixer_d_first_beats1 : fixer_d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire fixer__d_first_T_1 = fixer_anonOut_d_bits_opcode != 3'h6; // @[FIFOFixer.scala:75:63] wire fixer_d_first = fixer_d_first_first & fixer__d_first_T_1; // @[FIFOFixer.scala:75:{42,63}] reg fixer_flight_0; // @[FIFOFixer.scala:79:27] reg fixer_flight_1; // @[FIFOFixer.scala:79:27] reg fixer_flight_2; // @[FIFOFixer.scala:79:27] reg fixer_flight_3; // @[FIFOFixer.scala:79:27] reg fixer_flight_4; // @[FIFOFixer.scala:79:27] reg fixer_flight_5; // @[FIFOFixer.scala:79:27] reg fixer_flight_6; // @[FIFOFixer.scala:79:27] reg fixer_flight_7; // @[FIFOFixer.scala:79:27] reg fixer_flight_8; // @[FIFOFixer.scala:79:27] reg fixer_flight_9; // @[FIFOFixer.scala:79:27] reg fixer_flight_10; // @[FIFOFixer.scala:79:27] reg fixer_flight_11; // @[FIFOFixer.scala:79:27] reg fixer_flight_12; // @[FIFOFixer.scala:79:27] reg fixer_flight_13; // @[FIFOFixer.scala:79:27] reg fixer_flight_14; // @[FIFOFixer.scala:79:27] reg fixer_flight_15; // @[FIFOFixer.scala:79:27] reg fixer_flight_16; // @[FIFOFixer.scala:79:27] reg fixer_flight_17; // @[FIFOFixer.scala:79:27] reg fixer_flight_18; // @[FIFOFixer.scala:79:27] reg fixer_flight_19; // @[FIFOFixer.scala:79:27] reg fixer_flight_20; // @[FIFOFixer.scala:79:27] reg fixer_flight_21; // @[FIFOFixer.scala:79:27] reg fixer_flight_22; // @[FIFOFixer.scala:79:27] reg fixer_flight_23; // @[FIFOFixer.scala:79:27] reg fixer_flight_24; // @[FIFOFixer.scala:79:27] reg fixer_flight_25; // @[FIFOFixer.scala:79:27] reg fixer_flight_26; // @[FIFOFixer.scala:79:27] reg fixer_flight_27; // @[FIFOFixer.scala:79:27] reg fixer_flight_28; // @[FIFOFixer.scala:79:27] reg fixer_flight_29; // @[FIFOFixer.scala:79:27] reg fixer_flight_30; // @[FIFOFixer.scala:79:27] reg fixer_flight_31; // @[FIFOFixer.scala:79:27] reg fixer_flight_32; // @[FIFOFixer.scala:79:27] reg fixer_flight_33; // @[FIFOFixer.scala:79:27] reg fixer_flight_34; // @[FIFOFixer.scala:79:27] reg fixer_flight_35; // @[FIFOFixer.scala:79:27] reg fixer_flight_36; // @[FIFOFixer.scala:79:27] reg fixer_flight_37; // @[FIFOFixer.scala:79:27] reg fixer_flight_38; // @[FIFOFixer.scala:79:27] reg fixer_flight_39; // @[FIFOFixer.scala:79:27] reg fixer_flight_40; // @[FIFOFixer.scala:79:27] reg fixer_flight_41; // @[FIFOFixer.scala:79:27] reg fixer_flight_42; // @[FIFOFixer.scala:79:27] reg fixer_flight_43; // @[FIFOFixer.scala:79:27] reg fixer_flight_44; // @[FIFOFixer.scala:79:27] reg fixer_flight_45; // @[FIFOFixer.scala:79:27] reg fixer_flight_46; // @[FIFOFixer.scala:79:27] reg fixer_flight_47; // @[FIFOFixer.scala:79:27] reg fixer_flight_48; // @[FIFOFixer.scala:79:27] reg fixer_flight_49; // @[FIFOFixer.scala:79:27] reg fixer_flight_50; // @[FIFOFixer.scala:79:27] reg fixer_flight_51; // @[FIFOFixer.scala:79:27] reg fixer_flight_52; // @[FIFOFixer.scala:79:27] reg fixer_flight_53; // @[FIFOFixer.scala:79:27] reg fixer_flight_54; // @[FIFOFixer.scala:79:27] reg fixer_flight_55; // @[FIFOFixer.scala:79:27] reg fixer_flight_56; // @[FIFOFixer.scala:79:27] reg fixer_flight_57; // @[FIFOFixer.scala:79:27] reg fixer_flight_58; // @[FIFOFixer.scala:79:27] reg fixer_flight_59; // @[FIFOFixer.scala:79:27] reg fixer_flight_60; // @[FIFOFixer.scala:79:27] reg fixer_flight_61; // @[FIFOFixer.scala:79:27] reg fixer_flight_62; // @[FIFOFixer.scala:79:27] reg fixer_flight_63; // @[FIFOFixer.scala:79:27] reg fixer_flight_64; // @[FIFOFixer.scala:79:27] reg fixer_flight_65; // @[FIFOFixer.scala:79:27] reg fixer_flight_66; // @[FIFOFixer.scala:79:27] reg fixer_flight_67; // @[FIFOFixer.scala:79:27] reg fixer_flight_68; // @[FIFOFixer.scala:79:27] reg fixer_flight_69; // @[FIFOFixer.scala:79:27] reg fixer_flight_70; // @[FIFOFixer.scala:79:27] reg fixer_flight_71; // @[FIFOFixer.scala:79:27] reg fixer_flight_72; // @[FIFOFixer.scala:79:27] reg fixer_flight_73; // @[FIFOFixer.scala:79:27] reg fixer_flight_74; // @[FIFOFixer.scala:79:27] reg fixer_flight_75; // @[FIFOFixer.scala:79:27] reg fixer_flight_76; // @[FIFOFixer.scala:79:27] reg fixer_flight_77; // @[FIFOFixer.scala:79:27] reg fixer_flight_78; // @[FIFOFixer.scala:79:27] reg fixer_flight_79; // @[FIFOFixer.scala:79:27] reg fixer_flight_80; // @[FIFOFixer.scala:79:27] reg fixer_flight_81; // @[FIFOFixer.scala:79:27] reg fixer_flight_82; // @[FIFOFixer.scala:79:27] reg fixer_flight_83; // @[FIFOFixer.scala:79:27] reg fixer_flight_84; // @[FIFOFixer.scala:79:27] reg fixer_flight_85; // @[FIFOFixer.scala:79:27] reg fixer_flight_86; // @[FIFOFixer.scala:79:27] reg fixer_flight_87; // @[FIFOFixer.scala:79:27] reg fixer_flight_88; // @[FIFOFixer.scala:79:27] reg fixer_flight_89; // @[FIFOFixer.scala:79:27] reg fixer_flight_90; // @[FIFOFixer.scala:79:27] reg fixer_flight_91; // @[FIFOFixer.scala:79:27] reg fixer_flight_92; // @[FIFOFixer.scala:79:27] reg fixer_flight_93; // @[FIFOFixer.scala:79:27] reg fixer_flight_94; // @[FIFOFixer.scala:79:27] reg fixer_flight_95; // @[FIFOFixer.scala:79:27] reg fixer_flight_96; // @[FIFOFixer.scala:79:27] reg fixer_flight_97; // @[FIFOFixer.scala:79:27] reg fixer_flight_98; // @[FIFOFixer.scala:79:27] reg fixer_flight_99; // @[FIFOFixer.scala:79:27] reg fixer_flight_100; // @[FIFOFixer.scala:79:27] reg fixer_flight_101; // @[FIFOFixer.scala:79:27] reg fixer_flight_102; // @[FIFOFixer.scala:79:27] reg fixer_flight_103; // @[FIFOFixer.scala:79:27] reg fixer_flight_104; // @[FIFOFixer.scala:79:27] reg fixer_flight_105; // @[FIFOFixer.scala:79:27] reg fixer_flight_106; // @[FIFOFixer.scala:79:27] reg fixer_flight_107; // @[FIFOFixer.scala:79:27] reg fixer_flight_108; // @[FIFOFixer.scala:79:27] reg fixer_flight_109; // @[FIFOFixer.scala:79:27] reg fixer_flight_110; // @[FIFOFixer.scala:79:27] reg fixer_flight_111; // @[FIFOFixer.scala:79:27] reg fixer_flight_112; // @[FIFOFixer.scala:79:27] reg fixer_flight_113; // @[FIFOFixer.scala:79:27] reg fixer_flight_114; // @[FIFOFixer.scala:79:27] reg fixer_flight_115; // @[FIFOFixer.scala:79:27] reg fixer_flight_116; // @[FIFOFixer.scala:79:27] reg fixer_flight_117; // @[FIFOFixer.scala:79:27] reg fixer_flight_118; // @[FIFOFixer.scala:79:27] reg fixer_flight_119; // @[FIFOFixer.scala:79:27] reg fixer_flight_120; // @[FIFOFixer.scala:79:27] reg fixer_flight_121; // @[FIFOFixer.scala:79:27] reg fixer_flight_122; // @[FIFOFixer.scala:79:27] reg fixer_flight_123; // @[FIFOFixer.scala:79:27] reg fixer_flight_124; // @[FIFOFixer.scala:79:27] reg fixer_flight_125; // @[FIFOFixer.scala:79:27] reg fixer_flight_126; // @[FIFOFixer.scala:79:27] reg fixer_flight_127; // @[FIFOFixer.scala:79:27] reg fixer_flight_128; // @[FIFOFixer.scala:79:27] reg fixer_flight_129; // @[FIFOFixer.scala:79:27] reg fixer_flight_130; // @[FIFOFixer.scala:79:27] reg fixer_flight_131; // @[FIFOFixer.scala:79:27] reg fixer_flight_132; // @[FIFOFixer.scala:79:27] reg fixer_flight_133; // @[FIFOFixer.scala:79:27] reg fixer_flight_134; // @[FIFOFixer.scala:79:27] reg fixer_flight_135; // @[FIFOFixer.scala:79:27] reg fixer_flight_136; // @[FIFOFixer.scala:79:27] reg fixer_flight_137; // @[FIFOFixer.scala:79:27] reg fixer_flight_138; // @[FIFOFixer.scala:79:27] reg fixer_flight_139; // @[FIFOFixer.scala:79:27] reg fixer_flight_140; // @[FIFOFixer.scala:79:27] reg fixer_flight_141; // @[FIFOFixer.scala:79:27] reg fixer_flight_142; // @[FIFOFixer.scala:79:27] reg fixer_flight_143; // @[FIFOFixer.scala:79:27] reg fixer_flight_144; // @[FIFOFixer.scala:79:27] reg fixer_flight_145; // @[FIFOFixer.scala:79:27] reg fixer_flight_146; // @[FIFOFixer.scala:79:27] reg fixer_flight_147; // @[FIFOFixer.scala:79:27] reg fixer_flight_148; // @[FIFOFixer.scala:79:27] reg fixer_flight_149; // @[FIFOFixer.scala:79:27] reg fixer_flight_150; // @[FIFOFixer.scala:79:27] reg fixer_flight_151; // @[FIFOFixer.scala:79:27] reg fixer_flight_152; // @[FIFOFixer.scala:79:27] reg fixer_flight_153; // @[FIFOFixer.scala:79:27] reg fixer_flight_154; // @[FIFOFixer.scala:79:27] reg fixer_flight_155; // @[FIFOFixer.scala:79:27] reg fixer_flight_156; // @[FIFOFixer.scala:79:27] reg fixer_flight_157; // @[FIFOFixer.scala:79:27] reg fixer_flight_158; // @[FIFOFixer.scala:79:27] reg fixer_flight_159; // @[FIFOFixer.scala:79:27] reg fixer_flight_160; // @[FIFOFixer.scala:79:27] reg fixer_flight_161; // @[FIFOFixer.scala:79:27] reg fixer_flight_162; // @[FIFOFixer.scala:79:27] reg fixer_flight_163; // @[FIFOFixer.scala:79:27] reg fixer_flight_164; // @[FIFOFixer.scala:79:27] reg fixer_flight_165; // @[FIFOFixer.scala:79:27] reg fixer_flight_166; // @[FIFOFixer.scala:79:27] reg fixer_flight_167; // @[FIFOFixer.scala:79:27] reg fixer_flight_168; // @[FIFOFixer.scala:79:27] reg fixer_flight_169; // @[FIFOFixer.scala:79:27] reg fixer_flight_170; // @[FIFOFixer.scala:79:27] reg fixer_flight_171; // @[FIFOFixer.scala:79:27] reg fixer_flight_172; // @[FIFOFixer.scala:79:27] reg fixer_flight_173; // @[FIFOFixer.scala:79:27] reg fixer_flight_174; // @[FIFOFixer.scala:79:27] reg fixer_flight_175; // @[FIFOFixer.scala:79:27] reg fixer_flight_176; // @[FIFOFixer.scala:79:27] reg fixer_flight_177; // @[FIFOFixer.scala:79:27] reg fixer_flight_178; // @[FIFOFixer.scala:79:27] reg fixer_flight_179; // @[FIFOFixer.scala:79:27] reg fixer_flight_180; // @[FIFOFixer.scala:79:27] reg fixer_flight_181; // @[FIFOFixer.scala:79:27] reg fixer_flight_182; // @[FIFOFixer.scala:79:27] reg fixer_flight_183; // @[FIFOFixer.scala:79:27] reg fixer_flight_184; // @[FIFOFixer.scala:79:27] reg fixer_flight_185; // @[FIFOFixer.scala:79:27] reg fixer_flight_186; // @[FIFOFixer.scala:79:27] reg fixer_flight_187; // @[FIFOFixer.scala:79:27] reg fixer_flight_188; // @[FIFOFixer.scala:79:27] reg fixer_flight_189; // @[FIFOFixer.scala:79:27] reg fixer_flight_190; // @[FIFOFixer.scala:79:27] reg fixer_flight_191; // @[FIFOFixer.scala:79:27] reg fixer_flight_192; // @[FIFOFixer.scala:79:27] reg fixer_flight_193; // @[FIFOFixer.scala:79:27] reg fixer_flight_194; // @[FIFOFixer.scala:79:27] reg fixer_flight_195; // @[FIFOFixer.scala:79:27] reg fixer_flight_196; // @[FIFOFixer.scala:79:27] reg fixer_flight_197; // @[FIFOFixer.scala:79:27] reg fixer_flight_198; // @[FIFOFixer.scala:79:27] reg fixer_flight_199; // @[FIFOFixer.scala:79:27] reg fixer_flight_200; // @[FIFOFixer.scala:79:27] reg fixer_flight_201; // @[FIFOFixer.scala:79:27] reg fixer_flight_202; // @[FIFOFixer.scala:79:27] reg fixer_flight_203; // @[FIFOFixer.scala:79:27] reg fixer_flight_204; // @[FIFOFixer.scala:79:27] reg fixer_flight_205; // @[FIFOFixer.scala:79:27] reg fixer_flight_206; // @[FIFOFixer.scala:79:27] reg fixer_flight_207; // @[FIFOFixer.scala:79:27] reg fixer_flight_208; // @[FIFOFixer.scala:79:27] reg fixer_flight_209; // @[FIFOFixer.scala:79:27] reg fixer_flight_210; // @[FIFOFixer.scala:79:27] reg fixer_flight_211; // @[FIFOFixer.scala:79:27] reg fixer_flight_212; // @[FIFOFixer.scala:79:27] reg fixer_flight_213; // @[FIFOFixer.scala:79:27] reg fixer_flight_214; // @[FIFOFixer.scala:79:27] reg fixer_flight_215; // @[FIFOFixer.scala:79:27] reg fixer_flight_216; // @[FIFOFixer.scala:79:27] reg fixer_flight_217; // @[FIFOFixer.scala:79:27] reg fixer_flight_218; // @[FIFOFixer.scala:79:27] reg fixer_flight_219; // @[FIFOFixer.scala:79:27] reg fixer_flight_220; // @[FIFOFixer.scala:79:27] reg fixer_flight_221; // @[FIFOFixer.scala:79:27] reg fixer_flight_222; // @[FIFOFixer.scala:79:27] reg fixer_flight_223; // @[FIFOFixer.scala:79:27] reg fixer_flight_224; // @[FIFOFixer.scala:79:27] reg fixer_flight_225; // @[FIFOFixer.scala:79:27] reg fixer_flight_226; // @[FIFOFixer.scala:79:27] reg fixer_flight_227; // @[FIFOFixer.scala:79:27] reg fixer_flight_228; // @[FIFOFixer.scala:79:27] reg fixer_flight_229; // @[FIFOFixer.scala:79:27] reg fixer_flight_230; // @[FIFOFixer.scala:79:27] reg fixer_flight_231; // @[FIFOFixer.scala:79:27] reg fixer_flight_232; // @[FIFOFixer.scala:79:27] reg fixer_flight_233; // @[FIFOFixer.scala:79:27] reg fixer_flight_234; // @[FIFOFixer.scala:79:27] reg fixer_flight_235; // @[FIFOFixer.scala:79:27] reg fixer_flight_236; // @[FIFOFixer.scala:79:27] reg fixer_flight_237; // @[FIFOFixer.scala:79:27] reg fixer_flight_238; // @[FIFOFixer.scala:79:27] reg fixer_flight_239; // @[FIFOFixer.scala:79:27] reg fixer_flight_240; // @[FIFOFixer.scala:79:27] reg fixer_flight_241; // @[FIFOFixer.scala:79:27] reg fixer_flight_242; // @[FIFOFixer.scala:79:27] reg fixer_flight_243; // @[FIFOFixer.scala:79:27] reg fixer_flight_244; // @[FIFOFixer.scala:79:27] reg fixer_flight_245; // @[FIFOFixer.scala:79:27] reg fixer_flight_246; // @[FIFOFixer.scala:79:27] reg fixer_flight_247; // @[FIFOFixer.scala:79:27] reg fixer_flight_248; // @[FIFOFixer.scala:79:27] reg fixer_flight_249; // @[FIFOFixer.scala:79:27] reg fixer_flight_250; // @[FIFOFixer.scala:79:27] reg fixer_flight_251; // @[FIFOFixer.scala:79:27] reg fixer_flight_252; // @[FIFOFixer.scala:79:27] reg fixer_flight_253; // @[FIFOFixer.scala:79:27] reg fixer_flight_254; // @[FIFOFixer.scala:79:27] reg fixer_flight_255; // @[FIFOFixer.scala:79:27] reg fixer_flight_256; // @[FIFOFixer.scala:79:27] wire fixer__T_2 = fixer_anonIn_d_ready & fixer_anonIn_d_valid; // @[Decoupled.scala:51:35] assign fixer_anonOut_a_valid = fixer__anonOut_a_valid_T_2; // @[FIFOFixer.scala:95:33] assign fixer_anonIn_a_ready = fixer__anonIn_a_ready_T_2; // @[FIFOFixer.scala:96:33] reg [256:0] fixer_SourceIdFIFOed; // @[FIFOFixer.scala:115:35] wire [256:0] fixer_SourceIdSet; // @[FIFOFixer.scala:116:36] wire [256:0] fixer_SourceIdClear; // @[FIFOFixer.scala:117:38] wire [511:0] fixer__SourceIdSet_T = 512'h1 << fixer_anonIn_a_bits_source; // @[OneHot.scala:58:35] assign fixer_SourceIdSet = fixer_a_first & fixer__a_first_T ? fixer__SourceIdSet_T[256:0] : 257'h0; // @[OneHot.scala:58:35] wire [511:0] fixer__SourceIdClear_T = 512'h1 << fixer_anonIn_d_bits_source; // @[OneHot.scala:58:35] assign fixer_SourceIdClear = fixer_d_first & fixer__T_2 ? fixer__SourceIdClear_T[256:0] : 257'h0; // @[OneHot.scala:58:35] wire [256:0] fixer__SourceIdFIFOed_T = fixer_SourceIdFIFOed | fixer_SourceIdSet; // @[FIFOFixer.scala:115:35, :116:36, :126:40] wire fixer_allIDs_FIFOed = &fixer_SourceIdFIFOed; // @[FIFOFixer.scala:115:35, :127:41] wire buffer_1_nodeIn_a_ready; // @[MixedNode.scala:551:17] wire bus_xingOut_a_ready = buffer_1_auto_in_a_ready; // @[Buffer.scala:40:9] wire bus_xingOut_a_valid; // @[MixedNode.scala:542:17] wire buffer_1_nodeIn_a_valid = buffer_1_auto_in_a_valid; // @[Buffer.scala:40:9] wire [2:0] bus_xingOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] buffer_1_nodeIn_a_bits_opcode = buffer_1_auto_in_a_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] bus_xingOut_a_bits_param; // @[MixedNode.scala:542:17] wire [2:0] buffer_1_nodeIn_a_bits_param = buffer_1_auto_in_a_bits_param; // @[Buffer.scala:40:9] wire [3:0] bus_xingOut_a_bits_size; // @[MixedNode.scala:542:17] wire [3:0] buffer_1_nodeIn_a_bits_size = buffer_1_auto_in_a_bits_size; // @[Buffer.scala:40:9] wire [7:0] bus_xingOut_a_bits_source; // @[MixedNode.scala:542:17] wire [7:0] buffer_1_nodeIn_a_bits_source = buffer_1_auto_in_a_bits_source; // @[Buffer.scala:40:9] wire [28:0] bus_xingOut_a_bits_address; // @[MixedNode.scala:542:17] wire [28:0] buffer_1_nodeIn_a_bits_address = buffer_1_auto_in_a_bits_address; // @[Buffer.scala:40:9] wire [7:0] bus_xingOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [7:0] buffer_1_nodeIn_a_bits_mask = buffer_1_auto_in_a_bits_mask; // @[Buffer.scala:40:9] wire [63:0] bus_xingOut_a_bits_data; // @[MixedNode.scala:542:17] wire [63:0] buffer_1_nodeIn_a_bits_data = buffer_1_auto_in_a_bits_data; // @[Buffer.scala:40:9] wire bus_xingOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire buffer_1_nodeIn_a_bits_corrupt = buffer_1_auto_in_a_bits_corrupt; // @[Buffer.scala:40:9] wire bus_xingOut_d_ready; // @[MixedNode.scala:542:17] wire buffer_1_nodeIn_d_ready = buffer_1_auto_in_d_ready; // @[Buffer.scala:40:9] wire buffer_1_nodeIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] buffer_1_nodeIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire bus_xingOut_d_valid = buffer_1_auto_in_d_valid; // @[Buffer.scala:40:9] wire [1:0] buffer_1_nodeIn_d_bits_param; // @[MixedNode.scala:551:17] wire [2:0] bus_xingOut_d_bits_opcode = buffer_1_auto_in_d_bits_opcode; // @[Buffer.scala:40:9] wire [3:0] buffer_1_nodeIn_d_bits_size; // @[MixedNode.scala:551:17] wire [1:0] bus_xingOut_d_bits_param = buffer_1_auto_in_d_bits_param; // @[Buffer.scala:40:9] wire [7:0] buffer_1_nodeIn_d_bits_source; // @[MixedNode.scala:551:17] wire [3:0] bus_xingOut_d_bits_size = buffer_1_auto_in_d_bits_size; // @[Buffer.scala:40:9] wire buffer_1_nodeIn_d_bits_sink; // @[MixedNode.scala:551:17] wire [7:0] bus_xingOut_d_bits_source = buffer_1_auto_in_d_bits_source; // @[Buffer.scala:40:9] wire buffer_1_nodeIn_d_bits_denied; // @[MixedNode.scala:551:17] wire bus_xingOut_d_bits_sink = buffer_1_auto_in_d_bits_sink; // @[Buffer.scala:40:9] wire [63:0] buffer_1_nodeIn_d_bits_data; // @[MixedNode.scala:551:17] wire bus_xingOut_d_bits_denied = buffer_1_auto_in_d_bits_denied; // @[Buffer.scala:40:9] wire buffer_1_nodeIn_d_bits_corrupt; // @[MixedNode.scala:551:17] wire [63:0] bus_xingOut_d_bits_data = buffer_1_auto_in_d_bits_data; // @[Buffer.scala:40:9] wire bus_xingOut_d_bits_corrupt = buffer_1_auto_in_d_bits_corrupt; // @[Buffer.scala:40:9] wire buffer_1_nodeOut_a_ready = buffer_1_auto_out_a_ready; // @[Buffer.scala:40:9] wire buffer_1_nodeOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] buffer_1_nodeOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] buffer_1_nodeOut_a_bits_param; // @[MixedNode.scala:542:17] wire [3:0] buffer_1_nodeOut_a_bits_size; // @[MixedNode.scala:542:17] wire [7:0] buffer_1_nodeOut_a_bits_source; // @[MixedNode.scala:542:17] wire [28:0] buffer_1_nodeOut_a_bits_address; // @[MixedNode.scala:542:17] wire [7:0] buffer_1_nodeOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [63:0] buffer_1_nodeOut_a_bits_data; // @[MixedNode.scala:542:17] wire buffer_1_nodeOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire buffer_1_nodeOut_d_ready; // @[MixedNode.scala:542:17] wire buffer_1_nodeOut_d_valid = buffer_1_auto_out_d_valid; // @[Buffer.scala:40:9] wire [2:0] buffer_1_nodeOut_d_bits_opcode = buffer_1_auto_out_d_bits_opcode; // @[Buffer.scala:40:9] wire [1:0] buffer_1_nodeOut_d_bits_param = buffer_1_auto_out_d_bits_param; // @[Buffer.scala:40:9] wire [3:0] buffer_1_nodeOut_d_bits_size = buffer_1_auto_out_d_bits_size; // @[Buffer.scala:40:9] wire [7:0] buffer_1_nodeOut_d_bits_source = buffer_1_auto_out_d_bits_source; // @[Buffer.scala:40:9] wire buffer_1_nodeOut_d_bits_sink = buffer_1_auto_out_d_bits_sink; // @[Buffer.scala:40:9] wire buffer_1_nodeOut_d_bits_denied = buffer_1_auto_out_d_bits_denied; // @[Buffer.scala:40:9] wire [63:0] buffer_1_nodeOut_d_bits_data = buffer_1_auto_out_d_bits_data; // @[Buffer.scala:40:9] wire buffer_1_nodeOut_d_bits_corrupt = buffer_1_auto_out_d_bits_corrupt; // @[Buffer.scala:40:9] wire [2:0] buffer_1_auto_out_a_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] buffer_1_auto_out_a_bits_param; // @[Buffer.scala:40:9] wire [3:0] buffer_1_auto_out_a_bits_size; // @[Buffer.scala:40:9] wire [7:0] buffer_1_auto_out_a_bits_source; // @[Buffer.scala:40:9] wire [28:0] buffer_1_auto_out_a_bits_address; // @[Buffer.scala:40:9] wire [7:0] buffer_1_auto_out_a_bits_mask; // @[Buffer.scala:40:9] wire [63:0] buffer_1_auto_out_a_bits_data; // @[Buffer.scala:40:9] wire buffer_1_auto_out_a_bits_corrupt; // @[Buffer.scala:40:9] wire buffer_1_auto_out_a_valid; // @[Buffer.scala:40:9] wire buffer_1_auto_out_d_ready; // @[Buffer.scala:40:9] assign buffer_1_nodeIn_a_ready = buffer_1_nodeOut_a_ready; // @[MixedNode.scala:542:17, :551:17] assign buffer_1_auto_out_a_valid = buffer_1_nodeOut_a_valid; // @[Buffer.scala:40:9] assign buffer_1_auto_out_a_bits_opcode = buffer_1_nodeOut_a_bits_opcode; // @[Buffer.scala:40:9] assign buffer_1_auto_out_a_bits_param = buffer_1_nodeOut_a_bits_param; // @[Buffer.scala:40:9] assign buffer_1_auto_out_a_bits_size = buffer_1_nodeOut_a_bits_size; // @[Buffer.scala:40:9] assign buffer_1_auto_out_a_bits_source = buffer_1_nodeOut_a_bits_source; // @[Buffer.scala:40:9] assign buffer_1_auto_out_a_bits_address = buffer_1_nodeOut_a_bits_address; // @[Buffer.scala:40:9] assign buffer_1_auto_out_a_bits_mask = buffer_1_nodeOut_a_bits_mask; // @[Buffer.scala:40:9] assign buffer_1_auto_out_a_bits_data = buffer_1_nodeOut_a_bits_data; // @[Buffer.scala:40:9] assign buffer_1_auto_out_a_bits_corrupt = buffer_1_nodeOut_a_bits_corrupt; // @[Buffer.scala:40:9] assign buffer_1_auto_out_d_ready = buffer_1_nodeOut_d_ready; // @[Buffer.scala:40:9] assign buffer_1_nodeIn_d_valid = buffer_1_nodeOut_d_valid; // @[MixedNode.scala:542:17, :551:17] assign buffer_1_nodeIn_d_bits_opcode = buffer_1_nodeOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign buffer_1_nodeIn_d_bits_param = buffer_1_nodeOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17] assign buffer_1_nodeIn_d_bits_size = buffer_1_nodeOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17] assign buffer_1_nodeIn_d_bits_source = buffer_1_nodeOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17] assign buffer_1_nodeIn_d_bits_sink = buffer_1_nodeOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17] assign buffer_1_nodeIn_d_bits_denied = buffer_1_nodeOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17] assign buffer_1_nodeIn_d_bits_data = buffer_1_nodeOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17] assign buffer_1_nodeIn_d_bits_corrupt = buffer_1_nodeOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign buffer_1_auto_in_a_ready = buffer_1_nodeIn_a_ready; // @[Buffer.scala:40:9] assign buffer_1_nodeOut_a_valid = buffer_1_nodeIn_a_valid; // @[MixedNode.scala:542:17, :551:17] assign buffer_1_nodeOut_a_bits_opcode = buffer_1_nodeIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign buffer_1_nodeOut_a_bits_param = buffer_1_nodeIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17] assign buffer_1_nodeOut_a_bits_size = buffer_1_nodeIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17] assign buffer_1_nodeOut_a_bits_source = buffer_1_nodeIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17] assign buffer_1_nodeOut_a_bits_address = buffer_1_nodeIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17] assign buffer_1_nodeOut_a_bits_mask = buffer_1_nodeIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign buffer_1_nodeOut_a_bits_data = buffer_1_nodeIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17] assign buffer_1_nodeOut_a_bits_corrupt = buffer_1_nodeIn_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign buffer_1_nodeOut_d_ready = buffer_1_nodeIn_d_ready; // @[MixedNode.scala:542:17, :551:17] assign buffer_1_auto_in_d_valid = buffer_1_nodeIn_d_valid; // @[Buffer.scala:40:9] assign buffer_1_auto_in_d_bits_opcode = buffer_1_nodeIn_d_bits_opcode; // @[Buffer.scala:40:9] assign buffer_1_auto_in_d_bits_param = buffer_1_nodeIn_d_bits_param; // @[Buffer.scala:40:9] assign buffer_1_auto_in_d_bits_size = buffer_1_nodeIn_d_bits_size; // @[Buffer.scala:40:9] assign buffer_1_auto_in_d_bits_source = buffer_1_nodeIn_d_bits_source; // @[Buffer.scala:40:9] assign buffer_1_auto_in_d_bits_sink = buffer_1_nodeIn_d_bits_sink; // @[Buffer.scala:40:9] assign buffer_1_auto_in_d_bits_denied = buffer_1_nodeIn_d_bits_denied; // @[Buffer.scala:40:9] assign buffer_1_auto_in_d_bits_data = buffer_1_nodeIn_d_bits_data; // @[Buffer.scala:40:9] assign buffer_1_auto_in_d_bits_corrupt = buffer_1_nodeIn_d_bits_corrupt; // @[Buffer.scala:40:9] wire coupler_to_bus_named_pbus_widget_auto_anon_in_a_ready; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_pbus_widget_auto_anon_in_a_valid = coupler_to_bus_named_pbus_auto_widget_anon_in_a_valid; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_pbus_widget_auto_anon_in_a_bits_opcode = coupler_to_bus_named_pbus_auto_widget_anon_in_a_bits_opcode; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_pbus_widget_auto_anon_in_a_bits_param = coupler_to_bus_named_pbus_auto_widget_anon_in_a_bits_param; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_pbus_widget_auto_anon_in_a_bits_size = coupler_to_bus_named_pbus_auto_widget_anon_in_a_bits_size; // @[WidthWidget.scala:27:9] wire [8:0] coupler_to_bus_named_pbus_widget_auto_anon_in_a_bits_source = coupler_to_bus_named_pbus_auto_widget_anon_in_a_bits_source; // @[WidthWidget.scala:27:9] wire [28:0] coupler_to_bus_named_pbus_widget_auto_anon_in_a_bits_address = coupler_to_bus_named_pbus_auto_widget_anon_in_a_bits_address; // @[WidthWidget.scala:27:9] wire [7:0] coupler_to_bus_named_pbus_widget_auto_anon_in_a_bits_mask = coupler_to_bus_named_pbus_auto_widget_anon_in_a_bits_mask; // @[WidthWidget.scala:27:9] wire [63:0] coupler_to_bus_named_pbus_widget_auto_anon_in_a_bits_data = coupler_to_bus_named_pbus_auto_widget_anon_in_a_bits_data; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_pbus_widget_auto_anon_in_a_bits_corrupt = coupler_to_bus_named_pbus_auto_widget_anon_in_a_bits_corrupt; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_pbus_widget_auto_anon_in_d_ready = coupler_to_bus_named_pbus_auto_widget_anon_in_d_ready; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_pbus_widget_auto_anon_in_d_valid; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_pbus_widget_auto_anon_in_d_bits_opcode; // @[WidthWidget.scala:27:9] wire [1:0] coupler_to_bus_named_pbus_widget_auto_anon_in_d_bits_param; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_pbus_widget_auto_anon_in_d_bits_size; // @[WidthWidget.scala:27:9] wire [8:0] coupler_to_bus_named_pbus_widget_auto_anon_in_d_bits_source; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_pbus_widget_auto_anon_in_d_bits_sink; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_pbus_widget_auto_anon_in_d_bits_denied; // @[WidthWidget.scala:27:9] wire [63:0] coupler_to_bus_named_pbus_widget_auto_anon_in_d_bits_data; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_pbus_widget_auto_anon_in_d_bits_corrupt; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_pbus_bus_xingOut_a_ready = coupler_to_bus_named_pbus_auto_bus_xing_out_a_ready; // @[MixedNode.scala:542:17] wire coupler_to_bus_named_pbus_bus_xingOut_a_valid; // @[MixedNode.scala:542:17] assign auto_coupler_to_bus_named_pbus_bus_xing_out_a_valid_0 = coupler_to_bus_named_pbus_auto_bus_xing_out_a_valid; // @[ClockDomain.scala:14:9] wire [2:0] coupler_to_bus_named_pbus_bus_xingOut_a_bits_opcode; // @[MixedNode.scala:542:17] assign auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_opcode_0 = coupler_to_bus_named_pbus_auto_bus_xing_out_a_bits_opcode; // @[ClockDomain.scala:14:9] wire [2:0] coupler_to_bus_named_pbus_bus_xingOut_a_bits_param; // @[MixedNode.scala:542:17] assign auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_param_0 = coupler_to_bus_named_pbus_auto_bus_xing_out_a_bits_param; // @[ClockDomain.scala:14:9] wire [2:0] coupler_to_bus_named_pbus_bus_xingOut_a_bits_size; // @[MixedNode.scala:542:17] assign auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_size_0 = coupler_to_bus_named_pbus_auto_bus_xing_out_a_bits_size; // @[ClockDomain.scala:14:9] wire [8:0] coupler_to_bus_named_pbus_bus_xingOut_a_bits_source; // @[MixedNode.scala:542:17] assign auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_source_0 = coupler_to_bus_named_pbus_auto_bus_xing_out_a_bits_source; // @[ClockDomain.scala:14:9] wire [28:0] coupler_to_bus_named_pbus_bus_xingOut_a_bits_address; // @[MixedNode.scala:542:17] assign auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_address_0 = coupler_to_bus_named_pbus_auto_bus_xing_out_a_bits_address; // @[ClockDomain.scala:14:9] wire [7:0] coupler_to_bus_named_pbus_bus_xingOut_a_bits_mask; // @[MixedNode.scala:542:17] assign auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_mask_0 = coupler_to_bus_named_pbus_auto_bus_xing_out_a_bits_mask; // @[ClockDomain.scala:14:9] wire [63:0] coupler_to_bus_named_pbus_bus_xingOut_a_bits_data; // @[MixedNode.scala:542:17] assign auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_data_0 = coupler_to_bus_named_pbus_auto_bus_xing_out_a_bits_data; // @[ClockDomain.scala:14:9] wire coupler_to_bus_named_pbus_bus_xingOut_a_bits_corrupt; // @[MixedNode.scala:542:17] assign auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_corrupt_0 = coupler_to_bus_named_pbus_auto_bus_xing_out_a_bits_corrupt; // @[ClockDomain.scala:14:9] wire coupler_to_bus_named_pbus_bus_xingOut_d_ready; // @[MixedNode.scala:542:17] assign auto_coupler_to_bus_named_pbus_bus_xing_out_d_ready_0 = coupler_to_bus_named_pbus_auto_bus_xing_out_d_ready; // @[ClockDomain.scala:14:9] wire coupler_to_bus_named_pbus_bus_xingOut_d_valid = coupler_to_bus_named_pbus_auto_bus_xing_out_d_valid; // @[MixedNode.scala:542:17] wire [2:0] coupler_to_bus_named_pbus_bus_xingOut_d_bits_opcode = coupler_to_bus_named_pbus_auto_bus_xing_out_d_bits_opcode; // @[MixedNode.scala:542:17] wire [1:0] coupler_to_bus_named_pbus_bus_xingOut_d_bits_param = coupler_to_bus_named_pbus_auto_bus_xing_out_d_bits_param; // @[MixedNode.scala:542:17] wire [2:0] coupler_to_bus_named_pbus_bus_xingOut_d_bits_size = coupler_to_bus_named_pbus_auto_bus_xing_out_d_bits_size; // @[MixedNode.scala:542:17] wire [8:0] coupler_to_bus_named_pbus_bus_xingOut_d_bits_source = coupler_to_bus_named_pbus_auto_bus_xing_out_d_bits_source; // @[MixedNode.scala:542:17] wire coupler_to_bus_named_pbus_bus_xingOut_d_bits_sink = coupler_to_bus_named_pbus_auto_bus_xing_out_d_bits_sink; // @[MixedNode.scala:542:17] wire coupler_to_bus_named_pbus_bus_xingOut_d_bits_denied = coupler_to_bus_named_pbus_auto_bus_xing_out_d_bits_denied; // @[MixedNode.scala:542:17] wire [63:0] coupler_to_bus_named_pbus_bus_xingOut_d_bits_data = coupler_to_bus_named_pbus_auto_bus_xing_out_d_bits_data; // @[MixedNode.scala:542:17] wire coupler_to_bus_named_pbus_bus_xingOut_d_bits_corrupt = coupler_to_bus_named_pbus_auto_bus_xing_out_d_bits_corrupt; // @[MixedNode.scala:542:17] wire coupler_to_bus_named_pbus_auto_widget_anon_in_a_ready; // @[LazyModuleImp.scala:138:7] wire [2:0] coupler_to_bus_named_pbus_auto_widget_anon_in_d_bits_opcode; // @[LazyModuleImp.scala:138:7] wire [1:0] coupler_to_bus_named_pbus_auto_widget_anon_in_d_bits_param; // @[LazyModuleImp.scala:138:7] wire [2:0] coupler_to_bus_named_pbus_auto_widget_anon_in_d_bits_size; // @[LazyModuleImp.scala:138:7] wire [8:0] coupler_to_bus_named_pbus_auto_widget_anon_in_d_bits_source; // @[LazyModuleImp.scala:138:7] wire coupler_to_bus_named_pbus_auto_widget_anon_in_d_bits_sink; // @[LazyModuleImp.scala:138:7] wire coupler_to_bus_named_pbus_auto_widget_anon_in_d_bits_denied; // @[LazyModuleImp.scala:138:7] wire [63:0] coupler_to_bus_named_pbus_auto_widget_anon_in_d_bits_data; // @[LazyModuleImp.scala:138:7] wire coupler_to_bus_named_pbus_auto_widget_anon_in_d_bits_corrupt; // @[LazyModuleImp.scala:138:7] wire coupler_to_bus_named_pbus_auto_widget_anon_in_d_valid; // @[LazyModuleImp.scala:138:7] wire coupler_to_bus_named_pbus_widget_anonIn_a_ready; // @[MixedNode.scala:551:17] assign coupler_to_bus_named_pbus_auto_widget_anon_in_a_ready = coupler_to_bus_named_pbus_widget_auto_anon_in_a_ready; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_pbus_widget_anonIn_a_valid = coupler_to_bus_named_pbus_widget_auto_anon_in_a_valid; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_pbus_widget_anonIn_a_bits_opcode = coupler_to_bus_named_pbus_widget_auto_anon_in_a_bits_opcode; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_pbus_widget_anonIn_a_bits_param = coupler_to_bus_named_pbus_widget_auto_anon_in_a_bits_param; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_pbus_widget_anonIn_a_bits_size = coupler_to_bus_named_pbus_widget_auto_anon_in_a_bits_size; // @[WidthWidget.scala:27:9] wire [8:0] coupler_to_bus_named_pbus_widget_anonIn_a_bits_source = coupler_to_bus_named_pbus_widget_auto_anon_in_a_bits_source; // @[WidthWidget.scala:27:9] wire [28:0] coupler_to_bus_named_pbus_widget_anonIn_a_bits_address = coupler_to_bus_named_pbus_widget_auto_anon_in_a_bits_address; // @[WidthWidget.scala:27:9] wire [7:0] coupler_to_bus_named_pbus_widget_anonIn_a_bits_mask = coupler_to_bus_named_pbus_widget_auto_anon_in_a_bits_mask; // @[WidthWidget.scala:27:9] wire [63:0] coupler_to_bus_named_pbus_widget_anonIn_a_bits_data = coupler_to_bus_named_pbus_widget_auto_anon_in_a_bits_data; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_pbus_widget_anonIn_a_bits_corrupt = coupler_to_bus_named_pbus_widget_auto_anon_in_a_bits_corrupt; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_pbus_widget_anonIn_d_ready = coupler_to_bus_named_pbus_widget_auto_anon_in_d_ready; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_pbus_widget_anonIn_d_valid; // @[MixedNode.scala:551:17] assign coupler_to_bus_named_pbus_auto_widget_anon_in_d_valid = coupler_to_bus_named_pbus_widget_auto_anon_in_d_valid; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_pbus_widget_anonIn_d_bits_opcode; // @[MixedNode.scala:551:17] assign coupler_to_bus_named_pbus_auto_widget_anon_in_d_bits_opcode = coupler_to_bus_named_pbus_widget_auto_anon_in_d_bits_opcode; // @[WidthWidget.scala:27:9] wire [1:0] coupler_to_bus_named_pbus_widget_anonIn_d_bits_param; // @[MixedNode.scala:551:17] assign coupler_to_bus_named_pbus_auto_widget_anon_in_d_bits_param = coupler_to_bus_named_pbus_widget_auto_anon_in_d_bits_param; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_pbus_widget_anonIn_d_bits_size; // @[MixedNode.scala:551:17] assign coupler_to_bus_named_pbus_auto_widget_anon_in_d_bits_size = coupler_to_bus_named_pbus_widget_auto_anon_in_d_bits_size; // @[WidthWidget.scala:27:9] wire [8:0] coupler_to_bus_named_pbus_widget_anonIn_d_bits_source; // @[MixedNode.scala:551:17] assign coupler_to_bus_named_pbus_auto_widget_anon_in_d_bits_source = coupler_to_bus_named_pbus_widget_auto_anon_in_d_bits_source; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_pbus_widget_anonIn_d_bits_sink; // @[MixedNode.scala:551:17] assign coupler_to_bus_named_pbus_auto_widget_anon_in_d_bits_sink = coupler_to_bus_named_pbus_widget_auto_anon_in_d_bits_sink; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_pbus_widget_anonIn_d_bits_denied; // @[MixedNode.scala:551:17] assign coupler_to_bus_named_pbus_auto_widget_anon_in_d_bits_denied = coupler_to_bus_named_pbus_widget_auto_anon_in_d_bits_denied; // @[WidthWidget.scala:27:9] wire [63:0] coupler_to_bus_named_pbus_widget_anonIn_d_bits_data; // @[MixedNode.scala:551:17] assign coupler_to_bus_named_pbus_auto_widget_anon_in_d_bits_data = coupler_to_bus_named_pbus_widget_auto_anon_in_d_bits_data; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_pbus_widget_anonIn_d_bits_corrupt; // @[MixedNode.scala:551:17] assign coupler_to_bus_named_pbus_auto_widget_anon_in_d_bits_corrupt = coupler_to_bus_named_pbus_widget_auto_anon_in_d_bits_corrupt; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_pbus_bus_xingIn_a_ready; // @[MixedNode.scala:551:17] wire coupler_to_bus_named_pbus_widget_anonOut_a_ready = coupler_to_bus_named_pbus_widget_auto_anon_out_a_ready; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_pbus_widget_anonOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] coupler_to_bus_named_pbus_widget_anonOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire coupler_to_bus_named_pbus_bus_xingIn_a_valid = coupler_to_bus_named_pbus_widget_auto_anon_out_a_valid; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_pbus_widget_anonOut_a_bits_param; // @[MixedNode.scala:542:17] wire [2:0] coupler_to_bus_named_pbus_bus_xingIn_a_bits_opcode = coupler_to_bus_named_pbus_widget_auto_anon_out_a_bits_opcode; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_pbus_widget_anonOut_a_bits_size; // @[MixedNode.scala:542:17] wire [2:0] coupler_to_bus_named_pbus_bus_xingIn_a_bits_param = coupler_to_bus_named_pbus_widget_auto_anon_out_a_bits_param; // @[WidthWidget.scala:27:9] wire [8:0] coupler_to_bus_named_pbus_widget_anonOut_a_bits_source; // @[MixedNode.scala:542:17] wire [2:0] coupler_to_bus_named_pbus_bus_xingIn_a_bits_size = coupler_to_bus_named_pbus_widget_auto_anon_out_a_bits_size; // @[WidthWidget.scala:27:9] wire [28:0] coupler_to_bus_named_pbus_widget_anonOut_a_bits_address; // @[MixedNode.scala:542:17] wire [8:0] coupler_to_bus_named_pbus_bus_xingIn_a_bits_source = coupler_to_bus_named_pbus_widget_auto_anon_out_a_bits_source; // @[WidthWidget.scala:27:9] wire [7:0] coupler_to_bus_named_pbus_widget_anonOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [28:0] coupler_to_bus_named_pbus_bus_xingIn_a_bits_address = coupler_to_bus_named_pbus_widget_auto_anon_out_a_bits_address; // @[WidthWidget.scala:27:9] wire [63:0] coupler_to_bus_named_pbus_widget_anonOut_a_bits_data; // @[MixedNode.scala:542:17] wire [7:0] coupler_to_bus_named_pbus_bus_xingIn_a_bits_mask = coupler_to_bus_named_pbus_widget_auto_anon_out_a_bits_mask; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_pbus_widget_anonOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire [63:0] coupler_to_bus_named_pbus_bus_xingIn_a_bits_data = coupler_to_bus_named_pbus_widget_auto_anon_out_a_bits_data; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_pbus_widget_anonOut_d_ready; // @[MixedNode.scala:542:17] wire coupler_to_bus_named_pbus_bus_xingIn_a_bits_corrupt = coupler_to_bus_named_pbus_widget_auto_anon_out_a_bits_corrupt; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_pbus_bus_xingIn_d_ready = coupler_to_bus_named_pbus_widget_auto_anon_out_d_ready; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_pbus_bus_xingIn_d_valid; // @[MixedNode.scala:551:17] wire coupler_to_bus_named_pbus_widget_anonOut_d_valid = coupler_to_bus_named_pbus_widget_auto_anon_out_d_valid; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_pbus_bus_xingIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [2:0] coupler_to_bus_named_pbus_widget_anonOut_d_bits_opcode = coupler_to_bus_named_pbus_widget_auto_anon_out_d_bits_opcode; // @[WidthWidget.scala:27:9] wire [1:0] coupler_to_bus_named_pbus_bus_xingIn_d_bits_param; // @[MixedNode.scala:551:17] wire [1:0] coupler_to_bus_named_pbus_widget_anonOut_d_bits_param = coupler_to_bus_named_pbus_widget_auto_anon_out_d_bits_param; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_pbus_bus_xingIn_d_bits_size; // @[MixedNode.scala:551:17] wire [2:0] coupler_to_bus_named_pbus_widget_anonOut_d_bits_size = coupler_to_bus_named_pbus_widget_auto_anon_out_d_bits_size; // @[WidthWidget.scala:27:9] wire [8:0] coupler_to_bus_named_pbus_bus_xingIn_d_bits_source; // @[MixedNode.scala:551:17] wire [8:0] coupler_to_bus_named_pbus_widget_anonOut_d_bits_source = coupler_to_bus_named_pbus_widget_auto_anon_out_d_bits_source; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_pbus_bus_xingIn_d_bits_sink; // @[MixedNode.scala:551:17] wire coupler_to_bus_named_pbus_widget_anonOut_d_bits_sink = coupler_to_bus_named_pbus_widget_auto_anon_out_d_bits_sink; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_pbus_bus_xingIn_d_bits_denied; // @[MixedNode.scala:551:17] wire coupler_to_bus_named_pbus_widget_anonOut_d_bits_denied = coupler_to_bus_named_pbus_widget_auto_anon_out_d_bits_denied; // @[WidthWidget.scala:27:9] wire [63:0] coupler_to_bus_named_pbus_bus_xingIn_d_bits_data; // @[MixedNode.scala:551:17] wire [63:0] coupler_to_bus_named_pbus_widget_anonOut_d_bits_data = coupler_to_bus_named_pbus_widget_auto_anon_out_d_bits_data; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_pbus_bus_xingIn_d_bits_corrupt; // @[MixedNode.scala:551:17] wire coupler_to_bus_named_pbus_widget_anonOut_d_bits_corrupt = coupler_to_bus_named_pbus_widget_auto_anon_out_d_bits_corrupt; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_pbus_widget_anonIn_a_ready = coupler_to_bus_named_pbus_widget_anonOut_a_ready; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_pbus_widget_auto_anon_out_a_valid = coupler_to_bus_named_pbus_widget_anonOut_a_valid; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_pbus_widget_auto_anon_out_a_bits_opcode = coupler_to_bus_named_pbus_widget_anonOut_a_bits_opcode; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_pbus_widget_auto_anon_out_a_bits_param = coupler_to_bus_named_pbus_widget_anonOut_a_bits_param; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_pbus_widget_auto_anon_out_a_bits_size = coupler_to_bus_named_pbus_widget_anonOut_a_bits_size; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_pbus_widget_auto_anon_out_a_bits_source = coupler_to_bus_named_pbus_widget_anonOut_a_bits_source; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_pbus_widget_auto_anon_out_a_bits_address = coupler_to_bus_named_pbus_widget_anonOut_a_bits_address; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_pbus_widget_auto_anon_out_a_bits_mask = coupler_to_bus_named_pbus_widget_anonOut_a_bits_mask; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_pbus_widget_auto_anon_out_a_bits_data = coupler_to_bus_named_pbus_widget_anonOut_a_bits_data; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_pbus_widget_auto_anon_out_a_bits_corrupt = coupler_to_bus_named_pbus_widget_anonOut_a_bits_corrupt; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_pbus_widget_auto_anon_out_d_ready = coupler_to_bus_named_pbus_widget_anonOut_d_ready; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_pbus_widget_anonIn_d_valid = coupler_to_bus_named_pbus_widget_anonOut_d_valid; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_pbus_widget_anonIn_d_bits_opcode = coupler_to_bus_named_pbus_widget_anonOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_pbus_widget_anonIn_d_bits_param = coupler_to_bus_named_pbus_widget_anonOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_pbus_widget_anonIn_d_bits_size = coupler_to_bus_named_pbus_widget_anonOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_pbus_widget_anonIn_d_bits_source = coupler_to_bus_named_pbus_widget_anonOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_pbus_widget_anonIn_d_bits_sink = coupler_to_bus_named_pbus_widget_anonOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_pbus_widget_anonIn_d_bits_denied = coupler_to_bus_named_pbus_widget_anonOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_pbus_widget_anonIn_d_bits_data = coupler_to_bus_named_pbus_widget_anonOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_pbus_widget_anonIn_d_bits_corrupt = coupler_to_bus_named_pbus_widget_anonOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_pbus_widget_auto_anon_in_a_ready = coupler_to_bus_named_pbus_widget_anonIn_a_ready; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_pbus_widget_anonOut_a_valid = coupler_to_bus_named_pbus_widget_anonIn_a_valid; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_pbus_widget_anonOut_a_bits_opcode = coupler_to_bus_named_pbus_widget_anonIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_pbus_widget_anonOut_a_bits_param = coupler_to_bus_named_pbus_widget_anonIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_pbus_widget_anonOut_a_bits_size = coupler_to_bus_named_pbus_widget_anonIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_pbus_widget_anonOut_a_bits_source = coupler_to_bus_named_pbus_widget_anonIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_pbus_widget_anonOut_a_bits_address = coupler_to_bus_named_pbus_widget_anonIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_pbus_widget_anonOut_a_bits_mask = coupler_to_bus_named_pbus_widget_anonIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_pbus_widget_anonOut_a_bits_data = coupler_to_bus_named_pbus_widget_anonIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_pbus_widget_anonOut_a_bits_corrupt = coupler_to_bus_named_pbus_widget_anonIn_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_pbus_widget_anonOut_d_ready = coupler_to_bus_named_pbus_widget_anonIn_d_ready; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_pbus_widget_auto_anon_in_d_valid = coupler_to_bus_named_pbus_widget_anonIn_d_valid; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_pbus_widget_auto_anon_in_d_bits_opcode = coupler_to_bus_named_pbus_widget_anonIn_d_bits_opcode; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_pbus_widget_auto_anon_in_d_bits_param = coupler_to_bus_named_pbus_widget_anonIn_d_bits_param; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_pbus_widget_auto_anon_in_d_bits_size = coupler_to_bus_named_pbus_widget_anonIn_d_bits_size; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_pbus_widget_auto_anon_in_d_bits_source = coupler_to_bus_named_pbus_widget_anonIn_d_bits_source; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_pbus_widget_auto_anon_in_d_bits_sink = coupler_to_bus_named_pbus_widget_anonIn_d_bits_sink; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_pbus_widget_auto_anon_in_d_bits_denied = coupler_to_bus_named_pbus_widget_anonIn_d_bits_denied; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_pbus_widget_auto_anon_in_d_bits_data = coupler_to_bus_named_pbus_widget_anonIn_d_bits_data; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_pbus_widget_auto_anon_in_d_bits_corrupt = coupler_to_bus_named_pbus_widget_anonIn_d_bits_corrupt; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_pbus_bus_xingIn_a_ready = coupler_to_bus_named_pbus_bus_xingOut_a_ready; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_pbus_auto_bus_xing_out_a_valid = coupler_to_bus_named_pbus_bus_xingOut_a_valid; // @[MixedNode.scala:542:17] assign coupler_to_bus_named_pbus_auto_bus_xing_out_a_bits_opcode = coupler_to_bus_named_pbus_bus_xingOut_a_bits_opcode; // @[MixedNode.scala:542:17] assign coupler_to_bus_named_pbus_auto_bus_xing_out_a_bits_param = coupler_to_bus_named_pbus_bus_xingOut_a_bits_param; // @[MixedNode.scala:542:17] assign coupler_to_bus_named_pbus_auto_bus_xing_out_a_bits_size = coupler_to_bus_named_pbus_bus_xingOut_a_bits_size; // @[MixedNode.scala:542:17] assign coupler_to_bus_named_pbus_auto_bus_xing_out_a_bits_source = coupler_to_bus_named_pbus_bus_xingOut_a_bits_source; // @[MixedNode.scala:542:17] assign coupler_to_bus_named_pbus_auto_bus_xing_out_a_bits_address = coupler_to_bus_named_pbus_bus_xingOut_a_bits_address; // @[MixedNode.scala:542:17] assign coupler_to_bus_named_pbus_auto_bus_xing_out_a_bits_mask = coupler_to_bus_named_pbus_bus_xingOut_a_bits_mask; // @[MixedNode.scala:542:17] assign coupler_to_bus_named_pbus_auto_bus_xing_out_a_bits_data = coupler_to_bus_named_pbus_bus_xingOut_a_bits_data; // @[MixedNode.scala:542:17] assign coupler_to_bus_named_pbus_auto_bus_xing_out_a_bits_corrupt = coupler_to_bus_named_pbus_bus_xingOut_a_bits_corrupt; // @[MixedNode.scala:542:17] assign coupler_to_bus_named_pbus_auto_bus_xing_out_d_ready = coupler_to_bus_named_pbus_bus_xingOut_d_ready; // @[MixedNode.scala:542:17] assign coupler_to_bus_named_pbus_bus_xingIn_d_valid = coupler_to_bus_named_pbus_bus_xingOut_d_valid; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_pbus_bus_xingIn_d_bits_opcode = coupler_to_bus_named_pbus_bus_xingOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_pbus_bus_xingIn_d_bits_param = coupler_to_bus_named_pbus_bus_xingOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_pbus_bus_xingIn_d_bits_size = coupler_to_bus_named_pbus_bus_xingOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_pbus_bus_xingIn_d_bits_source = coupler_to_bus_named_pbus_bus_xingOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_pbus_bus_xingIn_d_bits_sink = coupler_to_bus_named_pbus_bus_xingOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_pbus_bus_xingIn_d_bits_denied = coupler_to_bus_named_pbus_bus_xingOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_pbus_bus_xingIn_d_bits_data = coupler_to_bus_named_pbus_bus_xingOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_pbus_bus_xingIn_d_bits_corrupt = coupler_to_bus_named_pbus_bus_xingOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_pbus_widget_auto_anon_out_a_ready = coupler_to_bus_named_pbus_bus_xingIn_a_ready; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_pbus_bus_xingOut_a_valid = coupler_to_bus_named_pbus_bus_xingIn_a_valid; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_pbus_bus_xingOut_a_bits_opcode = coupler_to_bus_named_pbus_bus_xingIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_pbus_bus_xingOut_a_bits_param = coupler_to_bus_named_pbus_bus_xingIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_pbus_bus_xingOut_a_bits_size = coupler_to_bus_named_pbus_bus_xingIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_pbus_bus_xingOut_a_bits_source = coupler_to_bus_named_pbus_bus_xingIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_pbus_bus_xingOut_a_bits_address = coupler_to_bus_named_pbus_bus_xingIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_pbus_bus_xingOut_a_bits_mask = coupler_to_bus_named_pbus_bus_xingIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_pbus_bus_xingOut_a_bits_data = coupler_to_bus_named_pbus_bus_xingIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_pbus_bus_xingOut_a_bits_corrupt = coupler_to_bus_named_pbus_bus_xingIn_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_pbus_bus_xingOut_d_ready = coupler_to_bus_named_pbus_bus_xingIn_d_ready; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_pbus_widget_auto_anon_out_d_valid = coupler_to_bus_named_pbus_bus_xingIn_d_valid; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_pbus_widget_auto_anon_out_d_bits_opcode = coupler_to_bus_named_pbus_bus_xingIn_d_bits_opcode; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_pbus_widget_auto_anon_out_d_bits_param = coupler_to_bus_named_pbus_bus_xingIn_d_bits_param; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_pbus_widget_auto_anon_out_d_bits_size = coupler_to_bus_named_pbus_bus_xingIn_d_bits_size; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_pbus_widget_auto_anon_out_d_bits_source = coupler_to_bus_named_pbus_bus_xingIn_d_bits_source; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_pbus_widget_auto_anon_out_d_bits_sink = coupler_to_bus_named_pbus_bus_xingIn_d_bits_sink; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_pbus_widget_auto_anon_out_d_bits_denied = coupler_to_bus_named_pbus_bus_xingIn_d_bits_denied; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_pbus_widget_auto_anon_out_d_bits_data = coupler_to_bus_named_pbus_bus_xingIn_d_bits_data; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_pbus_widget_auto_anon_out_d_bits_corrupt = coupler_to_bus_named_pbus_bus_xingIn_d_bits_corrupt; // @[WidthWidget.scala:27:9] wire coupler_from_port_named_custom_boot_pin_tlIn_a_ready; // @[MixedNode.scala:551:17] wire nodeOut_a_ready = coupler_from_port_named_custom_boot_pin_auto_tl_in_a_ready; // @[MixedNode.scala:542:17] wire nodeOut_a_valid; // @[MixedNode.scala:542:17] wire coupler_from_port_named_custom_boot_pin_tlIn_a_valid = coupler_from_port_named_custom_boot_pin_auto_tl_in_a_valid; // @[MixedNode.scala:551:17] wire [28:0] nodeOut_a_bits_address; // @[MixedNode.scala:542:17] wire [28:0] coupler_from_port_named_custom_boot_pin_tlIn_a_bits_address = coupler_from_port_named_custom_boot_pin_auto_tl_in_a_bits_address; // @[MixedNode.scala:551:17] wire [63:0] nodeOut_a_bits_data; // @[MixedNode.scala:542:17] wire [63:0] coupler_from_port_named_custom_boot_pin_tlIn_a_bits_data = coupler_from_port_named_custom_boot_pin_auto_tl_in_a_bits_data; // @[MixedNode.scala:551:17] wire coupler_from_port_named_custom_boot_pin_tlIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] coupler_from_port_named_custom_boot_pin_tlIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire nodeOut_d_valid = coupler_from_port_named_custom_boot_pin_auto_tl_in_d_valid; // @[MixedNode.scala:542:17] wire [1:0] coupler_from_port_named_custom_boot_pin_tlIn_d_bits_param; // @[MixedNode.scala:551:17] wire [2:0] nodeOut_d_bits_opcode = coupler_from_port_named_custom_boot_pin_auto_tl_in_d_bits_opcode; // @[MixedNode.scala:542:17] wire [3:0] coupler_from_port_named_custom_boot_pin_tlIn_d_bits_size; // @[MixedNode.scala:551:17] wire [1:0] nodeOut_d_bits_param = coupler_from_port_named_custom_boot_pin_auto_tl_in_d_bits_param; // @[MixedNode.scala:542:17] wire [3:0] nodeOut_d_bits_size = coupler_from_port_named_custom_boot_pin_auto_tl_in_d_bits_size; // @[MixedNode.scala:542:17] wire coupler_from_port_named_custom_boot_pin_tlIn_d_bits_sink; // @[MixedNode.scala:551:17] wire coupler_from_port_named_custom_boot_pin_tlIn_d_bits_denied; // @[MixedNode.scala:551:17] wire nodeOut_d_bits_sink = coupler_from_port_named_custom_boot_pin_auto_tl_in_d_bits_sink; // @[MixedNode.scala:542:17] wire [63:0] coupler_from_port_named_custom_boot_pin_tlIn_d_bits_data; // @[MixedNode.scala:551:17] wire nodeOut_d_bits_denied = coupler_from_port_named_custom_boot_pin_auto_tl_in_d_bits_denied; // @[MixedNode.scala:542:17] wire coupler_from_port_named_custom_boot_pin_tlIn_d_bits_corrupt; // @[MixedNode.scala:551:17] wire [63:0] nodeOut_d_bits_data = coupler_from_port_named_custom_boot_pin_auto_tl_in_d_bits_data; // @[MixedNode.scala:542:17] wire nodeOut_d_bits_corrupt = coupler_from_port_named_custom_boot_pin_auto_tl_in_d_bits_corrupt; // @[MixedNode.scala:542:17] wire coupler_from_port_named_custom_boot_pin_tlOut_a_ready = coupler_from_port_named_custom_boot_pin_auto_tl_out_a_ready; // @[MixedNode.scala:542:17] wire coupler_from_port_named_custom_boot_pin_tlOut_a_valid; // @[MixedNode.scala:542:17] wire [28:0] coupler_from_port_named_custom_boot_pin_tlOut_a_bits_address; // @[MixedNode.scala:542:17] wire [63:0] coupler_from_port_named_custom_boot_pin_tlOut_a_bits_data; // @[MixedNode.scala:542:17] wire coupler_from_port_named_custom_boot_pin_tlOut_d_valid = coupler_from_port_named_custom_boot_pin_auto_tl_out_d_valid; // @[MixedNode.scala:542:17] wire [2:0] coupler_from_port_named_custom_boot_pin_tlOut_d_bits_opcode = coupler_from_port_named_custom_boot_pin_auto_tl_out_d_bits_opcode; // @[MixedNode.scala:542:17] wire [1:0] coupler_from_port_named_custom_boot_pin_tlOut_d_bits_param = coupler_from_port_named_custom_boot_pin_auto_tl_out_d_bits_param; // @[MixedNode.scala:542:17] wire [3:0] coupler_from_port_named_custom_boot_pin_tlOut_d_bits_size = coupler_from_port_named_custom_boot_pin_auto_tl_out_d_bits_size; // @[MixedNode.scala:542:17] wire coupler_from_port_named_custom_boot_pin_tlOut_d_bits_sink = coupler_from_port_named_custom_boot_pin_auto_tl_out_d_bits_sink; // @[MixedNode.scala:542:17] wire coupler_from_port_named_custom_boot_pin_tlOut_d_bits_denied = coupler_from_port_named_custom_boot_pin_auto_tl_out_d_bits_denied; // @[MixedNode.scala:542:17] wire [63:0] coupler_from_port_named_custom_boot_pin_tlOut_d_bits_data = coupler_from_port_named_custom_boot_pin_auto_tl_out_d_bits_data; // @[MixedNode.scala:542:17] wire coupler_from_port_named_custom_boot_pin_tlOut_d_bits_corrupt = coupler_from_port_named_custom_boot_pin_auto_tl_out_d_bits_corrupt; // @[MixedNode.scala:542:17] wire [28:0] coupler_from_port_named_custom_boot_pin_auto_tl_out_a_bits_address; // @[LazyModuleImp.scala:138:7] wire [63:0] coupler_from_port_named_custom_boot_pin_auto_tl_out_a_bits_data; // @[LazyModuleImp.scala:138:7] wire coupler_from_port_named_custom_boot_pin_auto_tl_out_a_valid; // @[LazyModuleImp.scala:138:7] assign coupler_from_port_named_custom_boot_pin_tlIn_a_ready = coupler_from_port_named_custom_boot_pin_tlOut_a_ready; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_port_named_custom_boot_pin_auto_tl_out_a_valid = coupler_from_port_named_custom_boot_pin_tlOut_a_valid; // @[MixedNode.scala:542:17] assign coupler_from_port_named_custom_boot_pin_auto_tl_out_a_bits_address = coupler_from_port_named_custom_boot_pin_tlOut_a_bits_address; // @[MixedNode.scala:542:17] assign coupler_from_port_named_custom_boot_pin_auto_tl_out_a_bits_data = coupler_from_port_named_custom_boot_pin_tlOut_a_bits_data; // @[MixedNode.scala:542:17] assign coupler_from_port_named_custom_boot_pin_tlIn_d_valid = coupler_from_port_named_custom_boot_pin_tlOut_d_valid; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_port_named_custom_boot_pin_tlIn_d_bits_opcode = coupler_from_port_named_custom_boot_pin_tlOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_port_named_custom_boot_pin_tlIn_d_bits_param = coupler_from_port_named_custom_boot_pin_tlOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_port_named_custom_boot_pin_tlIn_d_bits_size = coupler_from_port_named_custom_boot_pin_tlOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_port_named_custom_boot_pin_tlIn_d_bits_sink = coupler_from_port_named_custom_boot_pin_tlOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_port_named_custom_boot_pin_tlIn_d_bits_denied = coupler_from_port_named_custom_boot_pin_tlOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_port_named_custom_boot_pin_tlIn_d_bits_data = coupler_from_port_named_custom_boot_pin_tlOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_port_named_custom_boot_pin_tlIn_d_bits_corrupt = coupler_from_port_named_custom_boot_pin_tlOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_port_named_custom_boot_pin_auto_tl_in_a_ready = coupler_from_port_named_custom_boot_pin_tlIn_a_ready; // @[MixedNode.scala:551:17] assign coupler_from_port_named_custom_boot_pin_tlOut_a_valid = coupler_from_port_named_custom_boot_pin_tlIn_a_valid; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_port_named_custom_boot_pin_tlOut_a_bits_address = coupler_from_port_named_custom_boot_pin_tlIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_port_named_custom_boot_pin_tlOut_a_bits_data = coupler_from_port_named_custom_boot_pin_tlIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_port_named_custom_boot_pin_auto_tl_in_d_valid = coupler_from_port_named_custom_boot_pin_tlIn_d_valid; // @[MixedNode.scala:551:17] assign coupler_from_port_named_custom_boot_pin_auto_tl_in_d_bits_opcode = coupler_from_port_named_custom_boot_pin_tlIn_d_bits_opcode; // @[MixedNode.scala:551:17] assign coupler_from_port_named_custom_boot_pin_auto_tl_in_d_bits_param = coupler_from_port_named_custom_boot_pin_tlIn_d_bits_param; // @[MixedNode.scala:551:17] assign coupler_from_port_named_custom_boot_pin_auto_tl_in_d_bits_size = coupler_from_port_named_custom_boot_pin_tlIn_d_bits_size; // @[MixedNode.scala:551:17] assign coupler_from_port_named_custom_boot_pin_auto_tl_in_d_bits_sink = coupler_from_port_named_custom_boot_pin_tlIn_d_bits_sink; // @[MixedNode.scala:551:17] assign coupler_from_port_named_custom_boot_pin_auto_tl_in_d_bits_denied = coupler_from_port_named_custom_boot_pin_tlIn_d_bits_denied; // @[MixedNode.scala:551:17] assign coupler_from_port_named_custom_boot_pin_auto_tl_in_d_bits_data = coupler_from_port_named_custom_boot_pin_tlIn_d_bits_data; // @[MixedNode.scala:551:17] assign coupler_from_port_named_custom_boot_pin_auto_tl_in_d_bits_corrupt = coupler_from_port_named_custom_boot_pin_tlIn_d_bits_corrupt; // @[MixedNode.scala:551:17] assign childClock = clockSinkNodeIn_clock; // @[MixedNode.scala:551:17] assign childReset = clockSinkNodeIn_reset; // @[MixedNode.scala:551:17] assign bus_xingIn_a_ready = bus_xingOut_a_ready; // @[MixedNode.scala:542:17, :551:17] assign buffer_1_auto_in_a_valid = bus_xingOut_a_valid; // @[Buffer.scala:40:9] assign buffer_1_auto_in_a_bits_opcode = bus_xingOut_a_bits_opcode; // @[Buffer.scala:40:9] assign buffer_1_auto_in_a_bits_param = bus_xingOut_a_bits_param; // @[Buffer.scala:40:9] assign buffer_1_auto_in_a_bits_size = bus_xingOut_a_bits_size; // @[Buffer.scala:40:9] assign buffer_1_auto_in_a_bits_source = bus_xingOut_a_bits_source; // @[Buffer.scala:40:9] assign buffer_1_auto_in_a_bits_address = bus_xingOut_a_bits_address; // @[Buffer.scala:40:9] assign buffer_1_auto_in_a_bits_mask = bus_xingOut_a_bits_mask; // @[Buffer.scala:40:9] assign buffer_1_auto_in_a_bits_data = bus_xingOut_a_bits_data; // @[Buffer.scala:40:9] assign buffer_1_auto_in_a_bits_corrupt = bus_xingOut_a_bits_corrupt; // @[Buffer.scala:40:9] assign buffer_1_auto_in_d_ready = bus_xingOut_d_ready; // @[Buffer.scala:40:9] assign bus_xingIn_d_valid = bus_xingOut_d_valid; // @[MixedNode.scala:542:17, :551:17] assign bus_xingIn_d_bits_opcode = bus_xingOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign bus_xingIn_d_bits_param = bus_xingOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17] assign bus_xingIn_d_bits_size = bus_xingOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17] assign bus_xingIn_d_bits_source = bus_xingOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17] assign bus_xingIn_d_bits_sink = bus_xingOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17] assign bus_xingIn_d_bits_denied = bus_xingOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17] assign bus_xingIn_d_bits_data = bus_xingOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17] assign bus_xingIn_d_bits_corrupt = bus_xingOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign auto_bus_xing_in_a_ready_0 = bus_xingIn_a_ready; // @[ClockDomain.scala:14:9] assign bus_xingOut_a_valid = bus_xingIn_a_valid; // @[MixedNode.scala:542:17, :551:17] assign bus_xingOut_a_bits_opcode = bus_xingIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign bus_xingOut_a_bits_param = bus_xingIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17] assign bus_xingOut_a_bits_size = bus_xingIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17] assign bus_xingOut_a_bits_source = bus_xingIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17] assign bus_xingOut_a_bits_address = bus_xingIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17] assign bus_xingOut_a_bits_mask = bus_xingIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign bus_xingOut_a_bits_data = bus_xingIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17] assign bus_xingOut_a_bits_corrupt = bus_xingIn_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign bus_xingOut_d_ready = bus_xingIn_d_ready; // @[MixedNode.scala:542:17, :551:17] assign auto_bus_xing_in_d_valid_0 = bus_xingIn_d_valid; // @[ClockDomain.scala:14:9] assign auto_bus_xing_in_d_bits_opcode_0 = bus_xingIn_d_bits_opcode; // @[ClockDomain.scala:14:9] assign auto_bus_xing_in_d_bits_param_0 = bus_xingIn_d_bits_param; // @[ClockDomain.scala:14:9] assign auto_bus_xing_in_d_bits_size_0 = bus_xingIn_d_bits_size; // @[ClockDomain.scala:14:9] assign auto_bus_xing_in_d_bits_source_0 = bus_xingIn_d_bits_source; // @[ClockDomain.scala:14:9] assign auto_bus_xing_in_d_bits_sink_0 = bus_xingIn_d_bits_sink; // @[ClockDomain.scala:14:9] assign auto_bus_xing_in_d_bits_denied_0 = bus_xingIn_d_bits_denied; // @[ClockDomain.scala:14:9] assign auto_bus_xing_in_d_bits_data_0 = bus_xingIn_d_bits_data; // @[ClockDomain.scala:14:9] assign auto_bus_xing_in_d_bits_corrupt_0 = bus_xingIn_d_bits_corrupt; // @[ClockDomain.scala:14:9] assign coupler_from_port_named_custom_boot_pin_auto_tl_in_a_valid = nodeOut_a_valid; // @[MixedNode.scala:542:17] assign coupler_from_port_named_custom_boot_pin_auto_tl_in_a_bits_address = nodeOut_a_bits_address; // @[MixedNode.scala:542:17] assign coupler_from_port_named_custom_boot_pin_auto_tl_in_a_bits_data = nodeOut_a_bits_data; // @[MixedNode.scala:542:17] reg [2:0] state; // @[CustomBootPin.scala:39:28] wire _T_1 = state == 3'h1; // @[CustomBootPin.scala:39:28, :43:24] assign nodeOut_a_valid = (|state) & (_T_1 | state != 3'h2 & state == 3'h3); // @[CustomBootPin.scala:39:28, :40:20, :43:24, :46:24] assign nodeOut_a_bits_address = _T_1 ? 29'h1000 : 29'h2000000; // @[CustomBootPin.scala:43:24, :47:23] assign nodeOut_a_bits_data = _T_1 ? 64'h80000000 : 64'h1; // @[CustomBootPin.scala:43:24, :47:23] wire fixer__T_1 = fixer_a_first & fixer__a_first_T; // @[Decoupled.scala:51:35] wire fixer__T_3 = fixer_d_first & fixer__T_2; // @[Decoupled.scala:51:35] wire [2:0] _GEN = state == 3'h5 & ~custom_boot ? 3'h0 : state; // @[CustomBootPin.scala:39:28, :43:24, :67:{29,43,51}] wire [7:0][2:0] _GEN_0 = {{_GEN}, {_GEN}, {_GEN}, {nodeOut_d_valid ? 3'h5 : state}, {nodeOut_a_ready & nodeOut_a_valid ? 3'h4 : state}, {nodeOut_d_valid ? 3'h3 : state}, {nodeOut_a_ready & nodeOut_a_valid ? 3'h2 : state}, {custom_boot ? 3'h1 : state}}; // @[Decoupled.scala:51:35] always @(posedge childClock) begin // @[LazyModuleImp.scala:155:31] if (childReset) begin // @[LazyModuleImp.scala:155:31, :158:31] fixer_a_first_counter <= 9'h0; // @[Edges.scala:229:27] fixer_d_first_counter <= 9'h0; // @[Edges.scala:229:27] fixer_flight_0 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_1 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_2 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_3 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_4 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_5 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_6 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_7 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_8 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_9 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_10 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_11 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_12 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_13 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_14 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_15 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_16 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_17 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_18 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_19 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_20 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_21 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_22 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_23 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_24 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_25 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_26 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_27 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_28 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_29 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_30 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_31 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_32 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_33 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_34 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_35 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_36 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_37 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_38 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_39 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_40 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_41 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_42 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_43 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_44 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_45 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_46 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_47 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_48 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_49 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_50 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_51 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_52 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_53 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_54 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_55 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_56 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_57 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_58 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_59 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_60 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_61 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_62 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_63 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_64 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_65 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_66 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_67 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_68 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_69 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_70 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_71 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_72 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_73 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_74 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_75 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_76 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_77 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_78 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_79 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_80 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_81 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_82 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_83 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_84 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_85 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_86 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_87 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_88 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_89 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_90 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_91 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_92 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_93 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_94 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_95 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_96 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_97 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_98 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_99 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_100 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_101 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_102 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_103 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_104 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_105 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_106 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_107 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_108 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_109 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_110 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_111 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_112 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_113 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_114 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_115 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_116 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_117 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_118 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_119 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_120 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_121 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_122 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_123 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_124 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_125 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_126 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_127 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_128 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_129 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_130 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_131 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_132 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_133 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_134 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_135 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_136 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_137 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_138 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_139 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_140 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_141 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_142 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_143 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_144 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_145 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_146 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_147 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_148 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_149 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_150 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_151 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_152 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_153 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_154 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_155 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_156 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_157 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_158 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_159 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_160 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_161 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_162 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_163 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_164 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_165 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_166 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_167 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_168 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_169 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_170 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_171 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_172 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_173 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_174 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_175 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_176 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_177 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_178 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_179 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_180 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_181 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_182 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_183 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_184 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_185 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_186 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_187 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_188 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_189 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_190 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_191 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_192 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_193 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_194 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_195 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_196 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_197 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_198 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_199 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_200 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_201 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_202 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_203 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_204 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_205 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_206 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_207 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_208 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_209 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_210 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_211 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_212 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_213 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_214 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_215 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_216 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_217 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_218 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_219 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_220 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_221 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_222 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_223 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_224 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_225 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_226 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_227 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_228 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_229 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_230 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_231 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_232 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_233 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_234 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_235 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_236 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_237 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_238 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_239 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_240 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_241 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_242 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_243 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_244 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_245 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_246 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_247 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_248 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_249 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_250 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_251 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_252 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_253 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_254 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_255 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_256 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_SourceIdFIFOed <= 257'h0; // @[FIFOFixer.scala:115:35] state <= 3'h0; // @[CustomBootPin.scala:39:28] end else begin // @[LazyModuleImp.scala:155:31] if (fixer__a_first_T) // @[Decoupled.scala:51:35] fixer_a_first_counter <= fixer__a_first_counter_T; // @[Edges.scala:229:27, :236:21] if (fixer__d_first_T) // @[Decoupled.scala:51:35] fixer_d_first_counter <= fixer__d_first_counter_T; // @[Edges.scala:229:27, :236:21] fixer_flight_0 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'h0) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'h0 | fixer_flight_0); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_1 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'h1) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'h1 | fixer_flight_1); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_2 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'h2) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'h2 | fixer_flight_2); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_3 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'h3) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'h3 | fixer_flight_3); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_4 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'h4) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'h4 | fixer_flight_4); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_5 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'h5) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'h5 | fixer_flight_5); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_6 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'h6) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'h6 | fixer_flight_6); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_7 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'h7) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'h7 | fixer_flight_7); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_8 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'h8) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'h8 | fixer_flight_8); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_9 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'h9) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'h9 | fixer_flight_9); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_10 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'hA) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'hA | fixer_flight_10); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_11 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'hB) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'hB | fixer_flight_11); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_12 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'hC) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'hC | fixer_flight_12); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_13 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'hD) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'hD | fixer_flight_13); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_14 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'hE) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'hE | fixer_flight_14); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_15 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'hF) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'hF | fixer_flight_15); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_16 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'h10) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'h10 | fixer_flight_16); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_17 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'h11) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'h11 | fixer_flight_17); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_18 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'h12) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'h12 | fixer_flight_18); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_19 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'h13) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'h13 | fixer_flight_19); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_20 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'h14) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'h14 | fixer_flight_20); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_21 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'h15) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'h15 | fixer_flight_21); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_22 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'h16) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'h16 | fixer_flight_22); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_23 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'h17) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'h17 | fixer_flight_23); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_24 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'h18) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'h18 | fixer_flight_24); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_25 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'h19) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'h19 | fixer_flight_25); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_26 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'h1A) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'h1A | fixer_flight_26); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_27 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'h1B) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'h1B | fixer_flight_27); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_28 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'h1C) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'h1C | fixer_flight_28); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_29 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'h1D) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'h1D | fixer_flight_29); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_30 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'h1E) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'h1E | fixer_flight_30); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_31 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'h1F) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'h1F | fixer_flight_31); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_32 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'h20) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'h20 | fixer_flight_32); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_33 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'h21) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'h21 | fixer_flight_33); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_34 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'h22) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'h22 | fixer_flight_34); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_35 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'h23) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'h23 | fixer_flight_35); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_36 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'h24) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'h24 | fixer_flight_36); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_37 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'h25) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'h25 | fixer_flight_37); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_38 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'h26) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'h26 | fixer_flight_38); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_39 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'h27) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'h27 | fixer_flight_39); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_40 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'h28) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'h28 | fixer_flight_40); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_41 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'h29) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'h29 | fixer_flight_41); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_42 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'h2A) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'h2A | fixer_flight_42); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_43 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'h2B) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'h2B | fixer_flight_43); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_44 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'h2C) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'h2C | fixer_flight_44); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_45 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'h2D) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'h2D | fixer_flight_45); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_46 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'h2E) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'h2E | fixer_flight_46); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_47 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'h2F) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'h2F | fixer_flight_47); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_48 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'h30) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'h30 | fixer_flight_48); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_49 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'h31) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'h31 | fixer_flight_49); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_50 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'h32) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'h32 | fixer_flight_50); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_51 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'h33) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'h33 | fixer_flight_51); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_52 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'h34) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'h34 | fixer_flight_52); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_53 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'h35) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'h35 | fixer_flight_53); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_54 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'h36) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'h36 | fixer_flight_54); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_55 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'h37) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'h37 | fixer_flight_55); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_56 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'h38) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'h38 | fixer_flight_56); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_57 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'h39) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'h39 | fixer_flight_57); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_58 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'h3A) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'h3A | fixer_flight_58); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_59 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'h3B) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'h3B | fixer_flight_59); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_60 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'h3C) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'h3C | fixer_flight_60); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_61 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'h3D) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'h3D | fixer_flight_61); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_62 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'h3E) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'h3E | fixer_flight_62); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_63 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'h3F) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'h3F | fixer_flight_63); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_64 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'h40) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'h40 | fixer_flight_64); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_65 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'h41) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'h41 | fixer_flight_65); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_66 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'h42) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'h42 | fixer_flight_66); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_67 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'h43) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'h43 | fixer_flight_67); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_68 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'h44) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'h44 | fixer_flight_68); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_69 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'h45) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'h45 | fixer_flight_69); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_70 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'h46) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'h46 | fixer_flight_70); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_71 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'h47) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'h47 | fixer_flight_71); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_72 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'h48) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'h48 | fixer_flight_72); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_73 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'h49) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'h49 | fixer_flight_73); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_74 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'h4A) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'h4A | fixer_flight_74); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_75 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'h4B) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'h4B | fixer_flight_75); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_76 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'h4C) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'h4C | fixer_flight_76); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_77 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'h4D) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'h4D | fixer_flight_77); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_78 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'h4E) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'h4E | fixer_flight_78); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_79 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'h4F) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'h4F | fixer_flight_79); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_80 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'h50) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'h50 | fixer_flight_80); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_81 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'h51) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'h51 | fixer_flight_81); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_82 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'h52) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'h52 | fixer_flight_82); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_83 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'h53) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'h53 | fixer_flight_83); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_84 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'h54) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'h54 | fixer_flight_84); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_85 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'h55) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'h55 | fixer_flight_85); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_86 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'h56) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'h56 | fixer_flight_86); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_87 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'h57) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'h57 | fixer_flight_87); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_88 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'h58) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'h58 | fixer_flight_88); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_89 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'h59) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'h59 | fixer_flight_89); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_90 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'h5A) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'h5A | fixer_flight_90); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_91 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'h5B) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'h5B | fixer_flight_91); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_92 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'h5C) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'h5C | fixer_flight_92); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_93 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'h5D) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'h5D | fixer_flight_93); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_94 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'h5E) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'h5E | fixer_flight_94); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_95 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'h5F) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'h5F | fixer_flight_95); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_96 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'h60) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'h60 | fixer_flight_96); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_97 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'h61) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'h61 | fixer_flight_97); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_98 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'h62) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'h62 | fixer_flight_98); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_99 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'h63) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'h63 | fixer_flight_99); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_100 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'h64) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'h64 | fixer_flight_100); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_101 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'h65) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'h65 | fixer_flight_101); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_102 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'h66) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'h66 | fixer_flight_102); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_103 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'h67) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'h67 | fixer_flight_103); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_104 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'h68) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'h68 | fixer_flight_104); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_105 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'h69) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'h69 | fixer_flight_105); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_106 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'h6A) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'h6A | fixer_flight_106); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_107 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'h6B) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'h6B | fixer_flight_107); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_108 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'h6C) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'h6C | fixer_flight_108); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_109 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'h6D) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'h6D | fixer_flight_109); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_110 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'h6E) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'h6E | fixer_flight_110); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_111 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'h6F) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'h6F | fixer_flight_111); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_112 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'h70) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'h70 | fixer_flight_112); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_113 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'h71) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'h71 | fixer_flight_113); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_114 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'h72) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'h72 | fixer_flight_114); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_115 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'h73) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'h73 | fixer_flight_115); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_116 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'h74) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'h74 | fixer_flight_116); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_117 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'h75) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'h75 | fixer_flight_117); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_118 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'h76) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'h76 | fixer_flight_118); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_119 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'h77) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'h77 | fixer_flight_119); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_120 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'h78) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'h78 | fixer_flight_120); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_121 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'h79) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'h79 | fixer_flight_121); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_122 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'h7A) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'h7A | fixer_flight_122); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_123 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'h7B) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'h7B | fixer_flight_123); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_124 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'h7C) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'h7C | fixer_flight_124); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_125 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'h7D) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'h7D | fixer_flight_125); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_126 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'h7E) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'h7E | fixer_flight_126); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_127 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'h7F) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'h7F | fixer_flight_127); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_128 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'h80) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'h80 | fixer_flight_128); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_129 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'h81) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'h81 | fixer_flight_129); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_130 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'h82) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'h82 | fixer_flight_130); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_131 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'h83) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'h83 | fixer_flight_131); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_132 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'h84) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'h84 | fixer_flight_132); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_133 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'h85) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'h85 | fixer_flight_133); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_134 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'h86) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'h86 | fixer_flight_134); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_135 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'h87) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'h87 | fixer_flight_135); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_136 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'h88) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'h88 | fixer_flight_136); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_137 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'h89) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'h89 | fixer_flight_137); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_138 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'h8A) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'h8A | fixer_flight_138); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_139 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'h8B) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'h8B | fixer_flight_139); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_140 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'h8C) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'h8C | fixer_flight_140); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_141 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'h8D) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'h8D | fixer_flight_141); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_142 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'h8E) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'h8E | fixer_flight_142); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_143 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'h8F) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'h8F | fixer_flight_143); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_144 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'h90) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'h90 | fixer_flight_144); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_145 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'h91) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'h91 | fixer_flight_145); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_146 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'h92) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'h92 | fixer_flight_146); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_147 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'h93) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'h93 | fixer_flight_147); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_148 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'h94) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'h94 | fixer_flight_148); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_149 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'h95) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'h95 | fixer_flight_149); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_150 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'h96) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'h96 | fixer_flight_150); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_151 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'h97) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'h97 | fixer_flight_151); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_152 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'h98) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'h98 | fixer_flight_152); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_153 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'h99) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'h99 | fixer_flight_153); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_154 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'h9A) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'h9A | fixer_flight_154); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_155 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'h9B) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'h9B | fixer_flight_155); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_156 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'h9C) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'h9C | fixer_flight_156); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_157 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'h9D) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'h9D | fixer_flight_157); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_158 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'h9E) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'h9E | fixer_flight_158); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_159 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'h9F) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'h9F | fixer_flight_159); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_160 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'hA0) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'hA0 | fixer_flight_160); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_161 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'hA1) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'hA1 | fixer_flight_161); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_162 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'hA2) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'hA2 | fixer_flight_162); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_163 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'hA3) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'hA3 | fixer_flight_163); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_164 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'hA4) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'hA4 | fixer_flight_164); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_165 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'hA5) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'hA5 | fixer_flight_165); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_166 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'hA6) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'hA6 | fixer_flight_166); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_167 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'hA7) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'hA7 | fixer_flight_167); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_168 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'hA8) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'hA8 | fixer_flight_168); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_169 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'hA9) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'hA9 | fixer_flight_169); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_170 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'hAA) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'hAA | fixer_flight_170); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_171 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'hAB) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'hAB | fixer_flight_171); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_172 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'hAC) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'hAC | fixer_flight_172); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_173 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'hAD) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'hAD | fixer_flight_173); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_174 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'hAE) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'hAE | fixer_flight_174); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_175 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'hAF) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'hAF | fixer_flight_175); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_176 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'hB0) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'hB0 | fixer_flight_176); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_177 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'hB1) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'hB1 | fixer_flight_177); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_178 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'hB2) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'hB2 | fixer_flight_178); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_179 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'hB3) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'hB3 | fixer_flight_179); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_180 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'hB4) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'hB4 | fixer_flight_180); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_181 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'hB5) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'hB5 | fixer_flight_181); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_182 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'hB6) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'hB6 | fixer_flight_182); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_183 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'hB7) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'hB7 | fixer_flight_183); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_184 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'hB8) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'hB8 | fixer_flight_184); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_185 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'hB9) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'hB9 | fixer_flight_185); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_186 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'hBA) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'hBA | fixer_flight_186); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_187 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'hBB) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'hBB | fixer_flight_187); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_188 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'hBC) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'hBC | fixer_flight_188); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_189 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'hBD) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'hBD | fixer_flight_189); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_190 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'hBE) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'hBE | fixer_flight_190); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_191 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'hBF) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'hBF | fixer_flight_191); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_192 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'hC0) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'hC0 | fixer_flight_192); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_193 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'hC1) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'hC1 | fixer_flight_193); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_194 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'hC2) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'hC2 | fixer_flight_194); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_195 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'hC3) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'hC3 | fixer_flight_195); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_196 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'hC4) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'hC4 | fixer_flight_196); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_197 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'hC5) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'hC5 | fixer_flight_197); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_198 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'hC6) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'hC6 | fixer_flight_198); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_199 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'hC7) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'hC7 | fixer_flight_199); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_200 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'hC8) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'hC8 | fixer_flight_200); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_201 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'hC9) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'hC9 | fixer_flight_201); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_202 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'hCA) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'hCA | fixer_flight_202); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_203 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'hCB) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'hCB | fixer_flight_203); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_204 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'hCC) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'hCC | fixer_flight_204); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_205 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'hCD) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'hCD | fixer_flight_205); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_206 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'hCE) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'hCE | fixer_flight_206); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_207 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'hCF) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'hCF | fixer_flight_207); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_208 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'hD0) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'hD0 | fixer_flight_208); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_209 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'hD1) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'hD1 | fixer_flight_209); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_210 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'hD2) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'hD2 | fixer_flight_210); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_211 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'hD3) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'hD3 | fixer_flight_211); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_212 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'hD4) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'hD4 | fixer_flight_212); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_213 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'hD5) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'hD5 | fixer_flight_213); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_214 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'hD6) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'hD6 | fixer_flight_214); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_215 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'hD7) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'hD7 | fixer_flight_215); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_216 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'hD8) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'hD8 | fixer_flight_216); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_217 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'hD9) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'hD9 | fixer_flight_217); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_218 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'hDA) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'hDA | fixer_flight_218); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_219 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'hDB) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'hDB | fixer_flight_219); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_220 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'hDC) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'hDC | fixer_flight_220); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_221 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'hDD) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'hDD | fixer_flight_221); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_222 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'hDE) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'hDE | fixer_flight_222); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_223 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'hDF) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'hDF | fixer_flight_223); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_224 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'hE0) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'hE0 | fixer_flight_224); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_225 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'hE1) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'hE1 | fixer_flight_225); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_226 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'hE2) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'hE2 | fixer_flight_226); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_227 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'hE3) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'hE3 | fixer_flight_227); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_228 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'hE4) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'hE4 | fixer_flight_228); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_229 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'hE5) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'hE5 | fixer_flight_229); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_230 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'hE6) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'hE6 | fixer_flight_230); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_231 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'hE7) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'hE7 | fixer_flight_231); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_232 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'hE8) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'hE8 | fixer_flight_232); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_233 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'hE9) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'hE9 | fixer_flight_233); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_234 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'hEA) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'hEA | fixer_flight_234); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_235 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'hEB) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'hEB | fixer_flight_235); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_236 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'hEC) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'hEC | fixer_flight_236); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_237 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'hED) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'hED | fixer_flight_237); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_238 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'hEE) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'hEE | fixer_flight_238); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_239 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'hEF) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'hEF | fixer_flight_239); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_240 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'hF0) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'hF0 | fixer_flight_240); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_241 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'hF1) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'hF1 | fixer_flight_241); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_242 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'hF2) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'hF2 | fixer_flight_242); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_243 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'hF3) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'hF3 | fixer_flight_243); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_244 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'hF4) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'hF4 | fixer_flight_244); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_245 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'hF5) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'hF5 | fixer_flight_245); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_246 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'hF6) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'hF6 | fixer_flight_246); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_247 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'hF7) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'hF7 | fixer_flight_247); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_248 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'hF8) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'hF8 | fixer_flight_248); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_249 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'hF9) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'hF9 | fixer_flight_249); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_250 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'hFA) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'hFA | fixer_flight_250); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_251 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'hFB) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'hFB | fixer_flight_251); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_252 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'hFC) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'hFC | fixer_flight_252); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_253 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'hFD) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'hFD | fixer_flight_253); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_254 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'hFE) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'hFE | fixer_flight_254); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_255 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'hFF) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'hFF | fixer_flight_255); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_256 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 9'h100) & (fixer__T_1 & fixer_anonIn_a_bits_source == 9'h100 | fixer_flight_256); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_SourceIdFIFOed <= fixer__SourceIdFIFOed_T; // @[FIFOFixer.scala:115:35, :126:40] state <= _GEN_0[state]; // @[CustomBootPin.scala:39:28, :43:24, :44:46, :53:30, :55:58, :64:30, :66:50] end always @(posedge) FixedClockBroadcast_7 fixedClockNode ( // @[ClockGroup.scala:115:114] .auto_anon_in_clock (clockGroup_auto_out_clock), // @[ClockGroup.scala:24:9] .auto_anon_in_reset (clockGroup_auto_out_reset), // @[ClockGroup.scala:24:9] .auto_anon_out_6_clock (auto_fixedClockNode_anon_out_5_clock_0), .auto_anon_out_6_reset (auto_fixedClockNode_anon_out_5_reset_0), .auto_anon_out_5_clock (auto_fixedClockNode_anon_out_4_clock_0), .auto_anon_out_5_reset (auto_fixedClockNode_anon_out_4_reset_0), .auto_anon_out_4_clock (auto_fixedClockNode_anon_out_3_clock_0), .auto_anon_out_4_reset (auto_fixedClockNode_anon_out_3_reset_0), .auto_anon_out_3_clock (auto_fixedClockNode_anon_out_2_clock_0), .auto_anon_out_3_reset (auto_fixedClockNode_anon_out_2_reset_0), .auto_anon_out_2_clock (auto_fixedClockNode_anon_out_1_clock_0), .auto_anon_out_2_reset (auto_fixedClockNode_anon_out_1_reset_0), .auto_anon_out_1_clock (auto_fixedClockNode_anon_out_0_clock_0), .auto_anon_out_1_reset (auto_fixedClockNode_anon_out_0_reset_0), .auto_anon_out_0_clock (clockSinkNodeIn_clock), .auto_anon_out_0_reset (clockSinkNodeIn_reset) ); // @[ClockGroup.scala:115:114] TLXbar_cbus_in_i2_o1_a29d64s9k1z4u in_xbar ( // @[PeripheryBus.scala:56:29] .clock (childClock), // @[LazyModuleImp.scala:155:31] .reset (childReset), // @[LazyModuleImp.scala:158:31] .auto_anon_in_1_a_ready (coupler_from_port_named_custom_boot_pin_auto_tl_out_a_ready), .auto_anon_in_1_a_valid (coupler_from_port_named_custom_boot_pin_auto_tl_out_a_valid), // @[LazyModuleImp.scala:138:7] .auto_anon_in_1_a_bits_address (coupler_from_port_named_custom_boot_pin_auto_tl_out_a_bits_address), // @[LazyModuleImp.scala:138:7] .auto_anon_in_1_a_bits_data (coupler_from_port_named_custom_boot_pin_auto_tl_out_a_bits_data), // @[LazyModuleImp.scala:138:7] .auto_anon_in_1_d_valid (coupler_from_port_named_custom_boot_pin_auto_tl_out_d_valid), .auto_anon_in_1_d_bits_opcode (coupler_from_port_named_custom_boot_pin_auto_tl_out_d_bits_opcode), .auto_anon_in_1_d_bits_param (coupler_from_port_named_custom_boot_pin_auto_tl_out_d_bits_param), .auto_anon_in_1_d_bits_size (coupler_from_port_named_custom_boot_pin_auto_tl_out_d_bits_size), .auto_anon_in_1_d_bits_sink (coupler_from_port_named_custom_boot_pin_auto_tl_out_d_bits_sink), .auto_anon_in_1_d_bits_denied (coupler_from_port_named_custom_boot_pin_auto_tl_out_d_bits_denied), .auto_anon_in_1_d_bits_data (coupler_from_port_named_custom_boot_pin_auto_tl_out_d_bits_data), .auto_anon_in_1_d_bits_corrupt (coupler_from_port_named_custom_boot_pin_auto_tl_out_d_bits_corrupt), .auto_anon_in_0_a_ready (buffer_1_auto_out_a_ready), .auto_anon_in_0_a_valid (buffer_1_auto_out_a_valid), // @[Buffer.scala:40:9] .auto_anon_in_0_a_bits_opcode (buffer_1_auto_out_a_bits_opcode), // @[Buffer.scala:40:9] .auto_anon_in_0_a_bits_param (buffer_1_auto_out_a_bits_param), // @[Buffer.scala:40:9] .auto_anon_in_0_a_bits_size (buffer_1_auto_out_a_bits_size), // @[Buffer.scala:40:9] .auto_anon_in_0_a_bits_source (buffer_1_auto_out_a_bits_source), // @[Buffer.scala:40:9] .auto_anon_in_0_a_bits_address (buffer_1_auto_out_a_bits_address), // @[Buffer.scala:40:9] .auto_anon_in_0_a_bits_mask (buffer_1_auto_out_a_bits_mask), // @[Buffer.scala:40:9] .auto_anon_in_0_a_bits_data (buffer_1_auto_out_a_bits_data), // @[Buffer.scala:40:9] .auto_anon_in_0_a_bits_corrupt (buffer_1_auto_out_a_bits_corrupt), // @[Buffer.scala:40:9] .auto_anon_in_0_d_ready (buffer_1_auto_out_d_ready), // @[Buffer.scala:40:9] .auto_anon_in_0_d_valid (buffer_1_auto_out_d_valid), .auto_anon_in_0_d_bits_opcode (buffer_1_auto_out_d_bits_opcode), .auto_anon_in_0_d_bits_param (buffer_1_auto_out_d_bits_param), .auto_anon_in_0_d_bits_size (buffer_1_auto_out_d_bits_size), .auto_anon_in_0_d_bits_source (buffer_1_auto_out_d_bits_source), .auto_anon_in_0_d_bits_sink (buffer_1_auto_out_d_bits_sink), .auto_anon_in_0_d_bits_denied (buffer_1_auto_out_d_bits_denied), .auto_anon_in_0_d_bits_data (buffer_1_auto_out_d_bits_data), .auto_anon_in_0_d_bits_corrupt (buffer_1_auto_out_d_bits_corrupt), .auto_anon_out_a_ready (_atomics_auto_in_a_ready), // @[AtomicAutomata.scala:289:29] .auto_anon_out_a_valid (_in_xbar_auto_anon_out_a_valid), .auto_anon_out_a_bits_opcode (_in_xbar_auto_anon_out_a_bits_opcode), .auto_anon_out_a_bits_param (_in_xbar_auto_anon_out_a_bits_param), .auto_anon_out_a_bits_size (_in_xbar_auto_anon_out_a_bits_size), .auto_anon_out_a_bits_source (_in_xbar_auto_anon_out_a_bits_source), .auto_anon_out_a_bits_address (_in_xbar_auto_anon_out_a_bits_address), .auto_anon_out_a_bits_mask (_in_xbar_auto_anon_out_a_bits_mask), .auto_anon_out_a_bits_data (_in_xbar_auto_anon_out_a_bits_data), .auto_anon_out_a_bits_corrupt (_in_xbar_auto_anon_out_a_bits_corrupt), .auto_anon_out_d_ready (_in_xbar_auto_anon_out_d_ready), .auto_anon_out_d_valid (_atomics_auto_in_d_valid), // @[AtomicAutomata.scala:289:29] .auto_anon_out_d_bits_opcode (_atomics_auto_in_d_bits_opcode), // @[AtomicAutomata.scala:289:29] .auto_anon_out_d_bits_param (_atomics_auto_in_d_bits_param), // @[AtomicAutomata.scala:289:29] .auto_anon_out_d_bits_size (_atomics_auto_in_d_bits_size), // @[AtomicAutomata.scala:289:29] .auto_anon_out_d_bits_source (_atomics_auto_in_d_bits_source), // @[AtomicAutomata.scala:289:29] .auto_anon_out_d_bits_sink (_atomics_auto_in_d_bits_sink), // @[AtomicAutomata.scala:289:29] .auto_anon_out_d_bits_denied (_atomics_auto_in_d_bits_denied), // @[AtomicAutomata.scala:289:29] .auto_anon_out_d_bits_data (_atomics_auto_in_d_bits_data), // @[AtomicAutomata.scala:289:29] .auto_anon_out_d_bits_corrupt (_atomics_auto_in_d_bits_corrupt) // @[AtomicAutomata.scala:289:29] ); // @[PeripheryBus.scala:56:29] TLXbar_cbus_out_i1_o8_a29d64s9k1z4u out_xbar ( // @[PeripheryBus.scala:57:30] .clock (childClock), // @[LazyModuleImp.scala:155:31] .reset (childReset), // @[LazyModuleImp.scala:158:31] .auto_anon_in_a_ready (fixer_auto_anon_out_a_ready), .auto_anon_in_a_valid (fixer_auto_anon_out_a_valid), // @[FIFOFixer.scala:50:9] .auto_anon_in_a_bits_opcode (fixer_auto_anon_out_a_bits_opcode), // @[FIFOFixer.scala:50:9] .auto_anon_in_a_bits_param (fixer_auto_anon_out_a_bits_param), // @[FIFOFixer.scala:50:9] .auto_anon_in_a_bits_size (fixer_auto_anon_out_a_bits_size), // @[FIFOFixer.scala:50:9] .auto_anon_in_a_bits_source (fixer_auto_anon_out_a_bits_source), // @[FIFOFixer.scala:50:9] .auto_anon_in_a_bits_address (fixer_auto_anon_out_a_bits_address), // @[FIFOFixer.scala:50:9] .auto_anon_in_a_bits_mask (fixer_auto_anon_out_a_bits_mask), // @[FIFOFixer.scala:50:9] .auto_anon_in_a_bits_data (fixer_auto_anon_out_a_bits_data), // @[FIFOFixer.scala:50:9] .auto_anon_in_a_bits_corrupt (fixer_auto_anon_out_a_bits_corrupt), // @[FIFOFixer.scala:50:9] .auto_anon_in_d_ready (fixer_auto_anon_out_d_ready), // @[FIFOFixer.scala:50:9] .auto_anon_in_d_valid (fixer_auto_anon_out_d_valid), .auto_anon_in_d_bits_opcode (fixer_auto_anon_out_d_bits_opcode), .auto_anon_in_d_bits_param (fixer_auto_anon_out_d_bits_param), .auto_anon_in_d_bits_size (fixer_auto_anon_out_d_bits_size), .auto_anon_in_d_bits_source (fixer_auto_anon_out_d_bits_source), .auto_anon_in_d_bits_sink (fixer_auto_anon_out_d_bits_sink), .auto_anon_in_d_bits_denied (fixer_auto_anon_out_d_bits_denied), .auto_anon_in_d_bits_data (fixer_auto_anon_out_d_bits_data), .auto_anon_in_d_bits_corrupt (fixer_auto_anon_out_d_bits_corrupt), .auto_anon_out_7_a_ready (_coupler_to_prci_ctrl_auto_tl_in_a_ready), // @[LazyScope.scala:98:27] .auto_anon_out_7_a_valid (_out_xbar_auto_anon_out_7_a_valid), .auto_anon_out_7_a_bits_opcode (_out_xbar_auto_anon_out_7_a_bits_opcode), .auto_anon_out_7_a_bits_param (_out_xbar_auto_anon_out_7_a_bits_param), .auto_anon_out_7_a_bits_size (_out_xbar_auto_anon_out_7_a_bits_size), .auto_anon_out_7_a_bits_source (_out_xbar_auto_anon_out_7_a_bits_source), .auto_anon_out_7_a_bits_address (_out_xbar_auto_anon_out_7_a_bits_address), .auto_anon_out_7_a_bits_mask (_out_xbar_auto_anon_out_7_a_bits_mask), .auto_anon_out_7_a_bits_data (_out_xbar_auto_anon_out_7_a_bits_data), .auto_anon_out_7_a_bits_corrupt (_out_xbar_auto_anon_out_7_a_bits_corrupt), .auto_anon_out_7_d_ready (_out_xbar_auto_anon_out_7_d_ready), .auto_anon_out_7_d_valid (_coupler_to_prci_ctrl_auto_tl_in_d_valid), // @[LazyScope.scala:98:27] .auto_anon_out_7_d_bits_opcode (_coupler_to_prci_ctrl_auto_tl_in_d_bits_opcode), // @[LazyScope.scala:98:27] .auto_anon_out_7_d_bits_param (_coupler_to_prci_ctrl_auto_tl_in_d_bits_param), // @[LazyScope.scala:98:27] .auto_anon_out_7_d_bits_size (_coupler_to_prci_ctrl_auto_tl_in_d_bits_size), // @[LazyScope.scala:98:27] .auto_anon_out_7_d_bits_source (_coupler_to_prci_ctrl_auto_tl_in_d_bits_source), // @[LazyScope.scala:98:27] .auto_anon_out_7_d_bits_sink (_coupler_to_prci_ctrl_auto_tl_in_d_bits_sink), // @[LazyScope.scala:98:27] .auto_anon_out_7_d_bits_denied (_coupler_to_prci_ctrl_auto_tl_in_d_bits_denied), // @[LazyScope.scala:98:27] .auto_anon_out_7_d_bits_data (_coupler_to_prci_ctrl_auto_tl_in_d_bits_data), // @[LazyScope.scala:98:27] .auto_anon_out_7_d_bits_corrupt (_coupler_to_prci_ctrl_auto_tl_in_d_bits_corrupt), // @[LazyScope.scala:98:27] .auto_anon_out_6_a_ready (_coupler_to_bootrom_auto_tl_in_a_ready), // @[LazyScope.scala:98:27] .auto_anon_out_6_a_valid (_out_xbar_auto_anon_out_6_a_valid), .auto_anon_out_6_a_bits_opcode (_out_xbar_auto_anon_out_6_a_bits_opcode), .auto_anon_out_6_a_bits_param (_out_xbar_auto_anon_out_6_a_bits_param), .auto_anon_out_6_a_bits_size (_out_xbar_auto_anon_out_6_a_bits_size), .auto_anon_out_6_a_bits_source (_out_xbar_auto_anon_out_6_a_bits_source), .auto_anon_out_6_a_bits_address (_out_xbar_auto_anon_out_6_a_bits_address), .auto_anon_out_6_a_bits_mask (_out_xbar_auto_anon_out_6_a_bits_mask), .auto_anon_out_6_a_bits_data (_out_xbar_auto_anon_out_6_a_bits_data), .auto_anon_out_6_a_bits_corrupt (_out_xbar_auto_anon_out_6_a_bits_corrupt), .auto_anon_out_6_d_ready (_out_xbar_auto_anon_out_6_d_ready), .auto_anon_out_6_d_valid (_coupler_to_bootrom_auto_tl_in_d_valid), // @[LazyScope.scala:98:27] .auto_anon_out_6_d_bits_size (_coupler_to_bootrom_auto_tl_in_d_bits_size), // @[LazyScope.scala:98:27] .auto_anon_out_6_d_bits_source (_coupler_to_bootrom_auto_tl_in_d_bits_source), // @[LazyScope.scala:98:27] .auto_anon_out_6_d_bits_data (_coupler_to_bootrom_auto_tl_in_d_bits_data), // @[LazyScope.scala:98:27] .auto_anon_out_5_a_ready (_coupler_to_debug_auto_tl_in_a_ready), // @[LazyScope.scala:98:27] .auto_anon_out_5_a_valid (_out_xbar_auto_anon_out_5_a_valid), .auto_anon_out_5_a_bits_opcode (_out_xbar_auto_anon_out_5_a_bits_opcode), .auto_anon_out_5_a_bits_param (_out_xbar_auto_anon_out_5_a_bits_param), .auto_anon_out_5_a_bits_size (_out_xbar_auto_anon_out_5_a_bits_size), .auto_anon_out_5_a_bits_source (_out_xbar_auto_anon_out_5_a_bits_source), .auto_anon_out_5_a_bits_address (_out_xbar_auto_anon_out_5_a_bits_address), .auto_anon_out_5_a_bits_mask (_out_xbar_auto_anon_out_5_a_bits_mask), .auto_anon_out_5_a_bits_data (_out_xbar_auto_anon_out_5_a_bits_data), .auto_anon_out_5_a_bits_corrupt (_out_xbar_auto_anon_out_5_a_bits_corrupt), .auto_anon_out_5_d_ready (_out_xbar_auto_anon_out_5_d_ready), .auto_anon_out_5_d_valid (_coupler_to_debug_auto_tl_in_d_valid), // @[LazyScope.scala:98:27] .auto_anon_out_5_d_bits_opcode (_coupler_to_debug_auto_tl_in_d_bits_opcode), // @[LazyScope.scala:98:27] .auto_anon_out_5_d_bits_size (_coupler_to_debug_auto_tl_in_d_bits_size), // @[LazyScope.scala:98:27] .auto_anon_out_5_d_bits_source (_coupler_to_debug_auto_tl_in_d_bits_source), // @[LazyScope.scala:98:27] .auto_anon_out_5_d_bits_data (_coupler_to_debug_auto_tl_in_d_bits_data), // @[LazyScope.scala:98:27] .auto_anon_out_4_a_ready (_coupler_to_plic_auto_tl_in_a_ready), // @[LazyScope.scala:98:27] .auto_anon_out_4_a_valid (_out_xbar_auto_anon_out_4_a_valid), .auto_anon_out_4_a_bits_opcode (_out_xbar_auto_anon_out_4_a_bits_opcode), .auto_anon_out_4_a_bits_param (_out_xbar_auto_anon_out_4_a_bits_param), .auto_anon_out_4_a_bits_size (_out_xbar_auto_anon_out_4_a_bits_size), .auto_anon_out_4_a_bits_source (_out_xbar_auto_anon_out_4_a_bits_source), .auto_anon_out_4_a_bits_address (_out_xbar_auto_anon_out_4_a_bits_address), .auto_anon_out_4_a_bits_mask (_out_xbar_auto_anon_out_4_a_bits_mask), .auto_anon_out_4_a_bits_data (_out_xbar_auto_anon_out_4_a_bits_data), .auto_anon_out_4_a_bits_corrupt (_out_xbar_auto_anon_out_4_a_bits_corrupt), .auto_anon_out_4_d_ready (_out_xbar_auto_anon_out_4_d_ready), .auto_anon_out_4_d_valid (_coupler_to_plic_auto_tl_in_d_valid), // @[LazyScope.scala:98:27] .auto_anon_out_4_d_bits_opcode (_coupler_to_plic_auto_tl_in_d_bits_opcode), // @[LazyScope.scala:98:27] .auto_anon_out_4_d_bits_size (_coupler_to_plic_auto_tl_in_d_bits_size), // @[LazyScope.scala:98:27] .auto_anon_out_4_d_bits_source (_coupler_to_plic_auto_tl_in_d_bits_source), // @[LazyScope.scala:98:27] .auto_anon_out_4_d_bits_data (_coupler_to_plic_auto_tl_in_d_bits_data), // @[LazyScope.scala:98:27] .auto_anon_out_3_a_ready (_coupler_to_clint_auto_tl_in_a_ready), // @[LazyScope.scala:98:27] .auto_anon_out_3_a_valid (_out_xbar_auto_anon_out_3_a_valid), .auto_anon_out_3_a_bits_opcode (_out_xbar_auto_anon_out_3_a_bits_opcode), .auto_anon_out_3_a_bits_param (_out_xbar_auto_anon_out_3_a_bits_param), .auto_anon_out_3_a_bits_size (_out_xbar_auto_anon_out_3_a_bits_size), .auto_anon_out_3_a_bits_source (_out_xbar_auto_anon_out_3_a_bits_source), .auto_anon_out_3_a_bits_address (_out_xbar_auto_anon_out_3_a_bits_address), .auto_anon_out_3_a_bits_mask (_out_xbar_auto_anon_out_3_a_bits_mask), .auto_anon_out_3_a_bits_data (_out_xbar_auto_anon_out_3_a_bits_data), .auto_anon_out_3_a_bits_corrupt (_out_xbar_auto_anon_out_3_a_bits_corrupt), .auto_anon_out_3_d_ready (_out_xbar_auto_anon_out_3_d_ready), .auto_anon_out_3_d_valid (_coupler_to_clint_auto_tl_in_d_valid), // @[LazyScope.scala:98:27] .auto_anon_out_3_d_bits_opcode (_coupler_to_clint_auto_tl_in_d_bits_opcode), // @[LazyScope.scala:98:27] .auto_anon_out_3_d_bits_size (_coupler_to_clint_auto_tl_in_d_bits_size), // @[LazyScope.scala:98:27] .auto_anon_out_3_d_bits_source (_coupler_to_clint_auto_tl_in_d_bits_source), // @[LazyScope.scala:98:27] .auto_anon_out_3_d_bits_data (_coupler_to_clint_auto_tl_in_d_bits_data), // @[LazyScope.scala:98:27] .auto_anon_out_2_a_ready (coupler_to_bus_named_pbus_auto_widget_anon_in_a_ready), // @[LazyModuleImp.scala:138:7] .auto_anon_out_2_a_valid (coupler_to_bus_named_pbus_auto_widget_anon_in_a_valid), .auto_anon_out_2_a_bits_opcode (coupler_to_bus_named_pbus_auto_widget_anon_in_a_bits_opcode), .auto_anon_out_2_a_bits_param (coupler_to_bus_named_pbus_auto_widget_anon_in_a_bits_param), .auto_anon_out_2_a_bits_size (coupler_to_bus_named_pbus_auto_widget_anon_in_a_bits_size), .auto_anon_out_2_a_bits_source (coupler_to_bus_named_pbus_auto_widget_anon_in_a_bits_source), .auto_anon_out_2_a_bits_address (coupler_to_bus_named_pbus_auto_widget_anon_in_a_bits_address), .auto_anon_out_2_a_bits_mask (coupler_to_bus_named_pbus_auto_widget_anon_in_a_bits_mask), .auto_anon_out_2_a_bits_data (coupler_to_bus_named_pbus_auto_widget_anon_in_a_bits_data), .auto_anon_out_2_a_bits_corrupt (coupler_to_bus_named_pbus_auto_widget_anon_in_a_bits_corrupt), .auto_anon_out_2_d_ready (coupler_to_bus_named_pbus_auto_widget_anon_in_d_ready), .auto_anon_out_2_d_valid (coupler_to_bus_named_pbus_auto_widget_anon_in_d_valid), // @[LazyModuleImp.scala:138:7] .auto_anon_out_2_d_bits_opcode (coupler_to_bus_named_pbus_auto_widget_anon_in_d_bits_opcode), // @[LazyModuleImp.scala:138:7] .auto_anon_out_2_d_bits_param (coupler_to_bus_named_pbus_auto_widget_anon_in_d_bits_param), // @[LazyModuleImp.scala:138:7] .auto_anon_out_2_d_bits_size (coupler_to_bus_named_pbus_auto_widget_anon_in_d_bits_size), // @[LazyModuleImp.scala:138:7] .auto_anon_out_2_d_bits_source (coupler_to_bus_named_pbus_auto_widget_anon_in_d_bits_source), // @[LazyModuleImp.scala:138:7] .auto_anon_out_2_d_bits_sink (coupler_to_bus_named_pbus_auto_widget_anon_in_d_bits_sink), // @[LazyModuleImp.scala:138:7] .auto_anon_out_2_d_bits_denied (coupler_to_bus_named_pbus_auto_widget_anon_in_d_bits_denied), // @[LazyModuleImp.scala:138:7] .auto_anon_out_2_d_bits_data (coupler_to_bus_named_pbus_auto_widget_anon_in_d_bits_data), // @[LazyModuleImp.scala:138:7] .auto_anon_out_2_d_bits_corrupt (coupler_to_bus_named_pbus_auto_widget_anon_in_d_bits_corrupt), // @[LazyModuleImp.scala:138:7] .auto_anon_out_1_a_ready (_coupler_to_l2_ctrl_auto_tl_in_a_ready), // @[LazyScope.scala:98:27] .auto_anon_out_1_a_valid (_out_xbar_auto_anon_out_1_a_valid), .auto_anon_out_1_a_bits_opcode (_out_xbar_auto_anon_out_1_a_bits_opcode), .auto_anon_out_1_a_bits_param (_out_xbar_auto_anon_out_1_a_bits_param), .auto_anon_out_1_a_bits_size (_out_xbar_auto_anon_out_1_a_bits_size), .auto_anon_out_1_a_bits_source (_out_xbar_auto_anon_out_1_a_bits_source), .auto_anon_out_1_a_bits_address (_out_xbar_auto_anon_out_1_a_bits_address), .auto_anon_out_1_a_bits_mask (_out_xbar_auto_anon_out_1_a_bits_mask), .auto_anon_out_1_a_bits_data (_out_xbar_auto_anon_out_1_a_bits_data), .auto_anon_out_1_a_bits_corrupt (_out_xbar_auto_anon_out_1_a_bits_corrupt), .auto_anon_out_1_d_ready (_out_xbar_auto_anon_out_1_d_ready), .auto_anon_out_1_d_valid (_coupler_to_l2_ctrl_auto_tl_in_d_valid), // @[LazyScope.scala:98:27] .auto_anon_out_1_d_bits_opcode (_coupler_to_l2_ctrl_auto_tl_in_d_bits_opcode), // @[LazyScope.scala:98:27] .auto_anon_out_1_d_bits_param (_coupler_to_l2_ctrl_auto_tl_in_d_bits_param), // @[LazyScope.scala:98:27] .auto_anon_out_1_d_bits_size (_coupler_to_l2_ctrl_auto_tl_in_d_bits_size), // @[LazyScope.scala:98:27] .auto_anon_out_1_d_bits_source (_coupler_to_l2_ctrl_auto_tl_in_d_bits_source), // @[LazyScope.scala:98:27] .auto_anon_out_1_d_bits_sink (_coupler_to_l2_ctrl_auto_tl_in_d_bits_sink), // @[LazyScope.scala:98:27] .auto_anon_out_1_d_bits_denied (_coupler_to_l2_ctrl_auto_tl_in_d_bits_denied), // @[LazyScope.scala:98:27] .auto_anon_out_1_d_bits_data (_coupler_to_l2_ctrl_auto_tl_in_d_bits_data), // @[LazyScope.scala:98:27] .auto_anon_out_1_d_bits_corrupt (_coupler_to_l2_ctrl_auto_tl_in_d_bits_corrupt), // @[LazyScope.scala:98:27] .auto_anon_out_0_a_ready (_wrapped_error_device_auto_buffer_in_a_ready), // @[LazyScope.scala:98:27] .auto_anon_out_0_a_valid (_out_xbar_auto_anon_out_0_a_valid), .auto_anon_out_0_a_bits_opcode (_out_xbar_auto_anon_out_0_a_bits_opcode), .auto_anon_out_0_a_bits_param (_out_xbar_auto_anon_out_0_a_bits_param), .auto_anon_out_0_a_bits_size (_out_xbar_auto_anon_out_0_a_bits_size), .auto_anon_out_0_a_bits_source (_out_xbar_auto_anon_out_0_a_bits_source), .auto_anon_out_0_a_bits_address (_out_xbar_auto_anon_out_0_a_bits_address), .auto_anon_out_0_a_bits_mask (_out_xbar_auto_anon_out_0_a_bits_mask), .auto_anon_out_0_a_bits_data (_out_xbar_auto_anon_out_0_a_bits_data), .auto_anon_out_0_a_bits_corrupt (_out_xbar_auto_anon_out_0_a_bits_corrupt), .auto_anon_out_0_d_ready (_out_xbar_auto_anon_out_0_d_ready), .auto_anon_out_0_d_valid (_wrapped_error_device_auto_buffer_in_d_valid), // @[LazyScope.scala:98:27] .auto_anon_out_0_d_bits_opcode (_wrapped_error_device_auto_buffer_in_d_bits_opcode), // @[LazyScope.scala:98:27] .auto_anon_out_0_d_bits_param (_wrapped_error_device_auto_buffer_in_d_bits_param), // @[LazyScope.scala:98:27] .auto_anon_out_0_d_bits_size (_wrapped_error_device_auto_buffer_in_d_bits_size), // @[LazyScope.scala:98:27] .auto_anon_out_0_d_bits_source (_wrapped_error_device_auto_buffer_in_d_bits_source), // @[LazyScope.scala:98:27] .auto_anon_out_0_d_bits_sink (_wrapped_error_device_auto_buffer_in_d_bits_sink), // @[LazyScope.scala:98:27] .auto_anon_out_0_d_bits_denied (_wrapped_error_device_auto_buffer_in_d_bits_denied), // @[LazyScope.scala:98:27] .auto_anon_out_0_d_bits_data (_wrapped_error_device_auto_buffer_in_d_bits_data), // @[LazyScope.scala:98:27] .auto_anon_out_0_d_bits_corrupt (_wrapped_error_device_auto_buffer_in_d_bits_corrupt) // @[LazyScope.scala:98:27] ); // @[PeripheryBus.scala:57:30] TLBuffer_a29d64s9k1z4u buffer ( // @[Buffer.scala:75:28] .clock (childClock), // @[LazyModuleImp.scala:155:31] .reset (childReset), // @[LazyModuleImp.scala:158:31] .auto_in_a_ready (_buffer_auto_in_a_ready), .auto_in_a_valid (_atomics_auto_out_a_valid), // @[AtomicAutomata.scala:289:29] .auto_in_a_bits_opcode (_atomics_auto_out_a_bits_opcode), // @[AtomicAutomata.scala:289:29] .auto_in_a_bits_param (_atomics_auto_out_a_bits_param), // @[AtomicAutomata.scala:289:29] .auto_in_a_bits_size (_atomics_auto_out_a_bits_size), // @[AtomicAutomata.scala:289:29] .auto_in_a_bits_source (_atomics_auto_out_a_bits_source), // @[AtomicAutomata.scala:289:29] .auto_in_a_bits_address (_atomics_auto_out_a_bits_address), // @[AtomicAutomata.scala:289:29] .auto_in_a_bits_mask (_atomics_auto_out_a_bits_mask), // @[AtomicAutomata.scala:289:29] .auto_in_a_bits_data (_atomics_auto_out_a_bits_data), // @[AtomicAutomata.scala:289:29] .auto_in_a_bits_corrupt (_atomics_auto_out_a_bits_corrupt), // @[AtomicAutomata.scala:289:29] .auto_in_d_ready (_atomics_auto_out_d_ready), // @[AtomicAutomata.scala:289:29] .auto_in_d_valid (_buffer_auto_in_d_valid), .auto_in_d_bits_opcode (_buffer_auto_in_d_bits_opcode), .auto_in_d_bits_param (_buffer_auto_in_d_bits_param), .auto_in_d_bits_size (_buffer_auto_in_d_bits_size), .auto_in_d_bits_source (_buffer_auto_in_d_bits_source), .auto_in_d_bits_sink (_buffer_auto_in_d_bits_sink), .auto_in_d_bits_denied (_buffer_auto_in_d_bits_denied), .auto_in_d_bits_data (_buffer_auto_in_d_bits_data), .auto_in_d_bits_corrupt (_buffer_auto_in_d_bits_corrupt), .auto_out_a_ready (fixer_auto_anon_in_a_ready), // @[FIFOFixer.scala:50:9] .auto_out_a_valid (fixer_auto_anon_in_a_valid), .auto_out_a_bits_opcode (fixer_auto_anon_in_a_bits_opcode), .auto_out_a_bits_param (fixer_auto_anon_in_a_bits_param), .auto_out_a_bits_size (fixer_auto_anon_in_a_bits_size), .auto_out_a_bits_source (fixer_auto_anon_in_a_bits_source), .auto_out_a_bits_address (fixer_auto_anon_in_a_bits_address), .auto_out_a_bits_mask (fixer_auto_anon_in_a_bits_mask), .auto_out_a_bits_data (fixer_auto_anon_in_a_bits_data), .auto_out_a_bits_corrupt (fixer_auto_anon_in_a_bits_corrupt), .auto_out_d_ready (fixer_auto_anon_in_d_ready), .auto_out_d_valid (fixer_auto_anon_in_d_valid), // @[FIFOFixer.scala:50:9] .auto_out_d_bits_opcode (fixer_auto_anon_in_d_bits_opcode), // @[FIFOFixer.scala:50:9] .auto_out_d_bits_param (fixer_auto_anon_in_d_bits_param), // @[FIFOFixer.scala:50:9] .auto_out_d_bits_size (fixer_auto_anon_in_d_bits_size), // @[FIFOFixer.scala:50:9] .auto_out_d_bits_source (fixer_auto_anon_in_d_bits_source), // @[FIFOFixer.scala:50:9] .auto_out_d_bits_sink (fixer_auto_anon_in_d_bits_sink), // @[FIFOFixer.scala:50:9] .auto_out_d_bits_denied (fixer_auto_anon_in_d_bits_denied), // @[FIFOFixer.scala:50:9] .auto_out_d_bits_data (fixer_auto_anon_in_d_bits_data), // @[FIFOFixer.scala:50:9] .auto_out_d_bits_corrupt (fixer_auto_anon_in_d_bits_corrupt) // @[FIFOFixer.scala:50:9] ); // @[Buffer.scala:75:28] TLAtomicAutomata_cbus atomics ( // @[AtomicAutomata.scala:289:29] .clock (childClock), // @[LazyModuleImp.scala:155:31] .reset (childReset), // @[LazyModuleImp.scala:158:31] .auto_in_a_ready (_atomics_auto_in_a_ready), .auto_in_a_valid (_in_xbar_auto_anon_out_a_valid), // @[PeripheryBus.scala:56:29] .auto_in_a_bits_opcode (_in_xbar_auto_anon_out_a_bits_opcode), // @[PeripheryBus.scala:56:29] .auto_in_a_bits_param (_in_xbar_auto_anon_out_a_bits_param), // @[PeripheryBus.scala:56:29] .auto_in_a_bits_size (_in_xbar_auto_anon_out_a_bits_size), // @[PeripheryBus.scala:56:29] .auto_in_a_bits_source (_in_xbar_auto_anon_out_a_bits_source), // @[PeripheryBus.scala:56:29] .auto_in_a_bits_address (_in_xbar_auto_anon_out_a_bits_address), // @[PeripheryBus.scala:56:29] .auto_in_a_bits_mask (_in_xbar_auto_anon_out_a_bits_mask), // @[PeripheryBus.scala:56:29] .auto_in_a_bits_data (_in_xbar_auto_anon_out_a_bits_data), // @[PeripheryBus.scala:56:29] .auto_in_a_bits_corrupt (_in_xbar_auto_anon_out_a_bits_corrupt), // @[PeripheryBus.scala:56:29] .auto_in_d_ready (_in_xbar_auto_anon_out_d_ready), // @[PeripheryBus.scala:56:29] .auto_in_d_valid (_atomics_auto_in_d_valid), .auto_in_d_bits_opcode (_atomics_auto_in_d_bits_opcode), .auto_in_d_bits_param (_atomics_auto_in_d_bits_param), .auto_in_d_bits_size (_atomics_auto_in_d_bits_size), .auto_in_d_bits_source (_atomics_auto_in_d_bits_source), .auto_in_d_bits_sink (_atomics_auto_in_d_bits_sink), .auto_in_d_bits_denied (_atomics_auto_in_d_bits_denied), .auto_in_d_bits_data (_atomics_auto_in_d_bits_data), .auto_in_d_bits_corrupt (_atomics_auto_in_d_bits_corrupt), .auto_out_a_ready (_buffer_auto_in_a_ready), // @[Buffer.scala:75:28] .auto_out_a_valid (_atomics_auto_out_a_valid), .auto_out_a_bits_opcode (_atomics_auto_out_a_bits_opcode), .auto_out_a_bits_param (_atomics_auto_out_a_bits_param), .auto_out_a_bits_size (_atomics_auto_out_a_bits_size), .auto_out_a_bits_source (_atomics_auto_out_a_bits_source), .auto_out_a_bits_address (_atomics_auto_out_a_bits_address), .auto_out_a_bits_mask (_atomics_auto_out_a_bits_mask), .auto_out_a_bits_data (_atomics_auto_out_a_bits_data), .auto_out_a_bits_corrupt (_atomics_auto_out_a_bits_corrupt), .auto_out_d_ready (_atomics_auto_out_d_ready), .auto_out_d_valid (_buffer_auto_in_d_valid), // @[Buffer.scala:75:28] .auto_out_d_bits_opcode (_buffer_auto_in_d_bits_opcode), // @[Buffer.scala:75:28] .auto_out_d_bits_param (_buffer_auto_in_d_bits_param), // @[Buffer.scala:75:28] .auto_out_d_bits_size (_buffer_auto_in_d_bits_size), // @[Buffer.scala:75:28] .auto_out_d_bits_source (_buffer_auto_in_d_bits_source), // @[Buffer.scala:75:28] .auto_out_d_bits_sink (_buffer_auto_in_d_bits_sink), // @[Buffer.scala:75:28] .auto_out_d_bits_denied (_buffer_auto_in_d_bits_denied), // @[Buffer.scala:75:28] .auto_out_d_bits_data (_buffer_auto_in_d_bits_data), // @[Buffer.scala:75:28] .auto_out_d_bits_corrupt (_buffer_auto_in_d_bits_corrupt) // @[Buffer.scala:75:28] ); // @[AtomicAutomata.scala:289:29] ErrorDeviceWrapper wrapped_error_device ( // @[LazyScope.scala:98:27] .clock (childClock), // @[LazyModuleImp.scala:155:31] .reset (childReset), // @[LazyModuleImp.scala:158:31] .auto_buffer_in_a_ready (_wrapped_error_device_auto_buffer_in_a_ready), .auto_buffer_in_a_valid (_out_xbar_auto_anon_out_0_a_valid), // @[PeripheryBus.scala:57:30] .auto_buffer_in_a_bits_opcode (_out_xbar_auto_anon_out_0_a_bits_opcode), // @[PeripheryBus.scala:57:30] .auto_buffer_in_a_bits_param (_out_xbar_auto_anon_out_0_a_bits_param), // @[PeripheryBus.scala:57:30] .auto_buffer_in_a_bits_size (_out_xbar_auto_anon_out_0_a_bits_size), // @[PeripheryBus.scala:57:30] .auto_buffer_in_a_bits_source (_out_xbar_auto_anon_out_0_a_bits_source), // @[PeripheryBus.scala:57:30] .auto_buffer_in_a_bits_address (_out_xbar_auto_anon_out_0_a_bits_address), // @[PeripheryBus.scala:57:30] .auto_buffer_in_a_bits_mask (_out_xbar_auto_anon_out_0_a_bits_mask), // @[PeripheryBus.scala:57:30] .auto_buffer_in_a_bits_data (_out_xbar_auto_anon_out_0_a_bits_data), // @[PeripheryBus.scala:57:30] .auto_buffer_in_a_bits_corrupt (_out_xbar_auto_anon_out_0_a_bits_corrupt), // @[PeripheryBus.scala:57:30] .auto_buffer_in_d_ready (_out_xbar_auto_anon_out_0_d_ready), // @[PeripheryBus.scala:57:30] .auto_buffer_in_d_valid (_wrapped_error_device_auto_buffer_in_d_valid), .auto_buffer_in_d_bits_opcode (_wrapped_error_device_auto_buffer_in_d_bits_opcode), .auto_buffer_in_d_bits_param (_wrapped_error_device_auto_buffer_in_d_bits_param), .auto_buffer_in_d_bits_size (_wrapped_error_device_auto_buffer_in_d_bits_size), .auto_buffer_in_d_bits_source (_wrapped_error_device_auto_buffer_in_d_bits_source), .auto_buffer_in_d_bits_sink (_wrapped_error_device_auto_buffer_in_d_bits_sink), .auto_buffer_in_d_bits_denied (_wrapped_error_device_auto_buffer_in_d_bits_denied), .auto_buffer_in_d_bits_data (_wrapped_error_device_auto_buffer_in_d_bits_data), .auto_buffer_in_d_bits_corrupt (_wrapped_error_device_auto_buffer_in_d_bits_corrupt) ); // @[LazyScope.scala:98:27] TLInterconnectCoupler_cbus_to_l2_ctrl coupler_to_l2_ctrl ( // @[LazyScope.scala:98:27] .clock (childClock), // @[LazyModuleImp.scala:155:31] .reset (childReset), // @[LazyModuleImp.scala:158:31] .auto_buffer_out_a_ready (auto_coupler_to_l2_ctrl_buffer_out_a_ready_0), // @[ClockDomain.scala:14:9] .auto_buffer_out_a_valid (auto_coupler_to_l2_ctrl_buffer_out_a_valid_0), .auto_buffer_out_a_bits_opcode (auto_coupler_to_l2_ctrl_buffer_out_a_bits_opcode_0), .auto_buffer_out_a_bits_param (auto_coupler_to_l2_ctrl_buffer_out_a_bits_param_0), .auto_buffer_out_a_bits_size (auto_coupler_to_l2_ctrl_buffer_out_a_bits_size_0), .auto_buffer_out_a_bits_source (auto_coupler_to_l2_ctrl_buffer_out_a_bits_source_0), .auto_buffer_out_a_bits_address (auto_coupler_to_l2_ctrl_buffer_out_a_bits_address_0), .auto_buffer_out_a_bits_mask (auto_coupler_to_l2_ctrl_buffer_out_a_bits_mask_0), .auto_buffer_out_a_bits_data (auto_coupler_to_l2_ctrl_buffer_out_a_bits_data_0), .auto_buffer_out_a_bits_corrupt (auto_coupler_to_l2_ctrl_buffer_out_a_bits_corrupt_0), .auto_buffer_out_d_ready (auto_coupler_to_l2_ctrl_buffer_out_d_ready_0), .auto_buffer_out_d_valid (auto_coupler_to_l2_ctrl_buffer_out_d_valid_0), // @[ClockDomain.scala:14:9] .auto_buffer_out_d_bits_opcode (auto_coupler_to_l2_ctrl_buffer_out_d_bits_opcode_0), // @[ClockDomain.scala:14:9] .auto_buffer_out_d_bits_size (auto_coupler_to_l2_ctrl_buffer_out_d_bits_size_0), // @[ClockDomain.scala:14:9] .auto_buffer_out_d_bits_source (auto_coupler_to_l2_ctrl_buffer_out_d_bits_source_0), // @[ClockDomain.scala:14:9] .auto_buffer_out_d_bits_data (auto_coupler_to_l2_ctrl_buffer_out_d_bits_data_0), // @[ClockDomain.scala:14:9] .auto_tl_in_a_ready (_coupler_to_l2_ctrl_auto_tl_in_a_ready), .auto_tl_in_a_valid (_out_xbar_auto_anon_out_1_a_valid), // @[PeripheryBus.scala:57:30] .auto_tl_in_a_bits_opcode (_out_xbar_auto_anon_out_1_a_bits_opcode), // @[PeripheryBus.scala:57:30] .auto_tl_in_a_bits_param (_out_xbar_auto_anon_out_1_a_bits_param), // @[PeripheryBus.scala:57:30] .auto_tl_in_a_bits_size (_out_xbar_auto_anon_out_1_a_bits_size), // @[PeripheryBus.scala:57:30] .auto_tl_in_a_bits_source (_out_xbar_auto_anon_out_1_a_bits_source), // @[PeripheryBus.scala:57:30] .auto_tl_in_a_bits_address (_out_xbar_auto_anon_out_1_a_bits_address), // @[PeripheryBus.scala:57:30] .auto_tl_in_a_bits_mask (_out_xbar_auto_anon_out_1_a_bits_mask), // @[PeripheryBus.scala:57:30] .auto_tl_in_a_bits_data (_out_xbar_auto_anon_out_1_a_bits_data), // @[PeripheryBus.scala:57:30] .auto_tl_in_a_bits_corrupt (_out_xbar_auto_anon_out_1_a_bits_corrupt), // @[PeripheryBus.scala:57:30] .auto_tl_in_d_ready (_out_xbar_auto_anon_out_1_d_ready), // @[PeripheryBus.scala:57:30] .auto_tl_in_d_valid (_coupler_to_l2_ctrl_auto_tl_in_d_valid), .auto_tl_in_d_bits_opcode (_coupler_to_l2_ctrl_auto_tl_in_d_bits_opcode), .auto_tl_in_d_bits_param (_coupler_to_l2_ctrl_auto_tl_in_d_bits_param), .auto_tl_in_d_bits_size (_coupler_to_l2_ctrl_auto_tl_in_d_bits_size), .auto_tl_in_d_bits_source (_coupler_to_l2_ctrl_auto_tl_in_d_bits_source), .auto_tl_in_d_bits_sink (_coupler_to_l2_ctrl_auto_tl_in_d_bits_sink), .auto_tl_in_d_bits_denied (_coupler_to_l2_ctrl_auto_tl_in_d_bits_denied), .auto_tl_in_d_bits_data (_coupler_to_l2_ctrl_auto_tl_in_d_bits_data), .auto_tl_in_d_bits_corrupt (_coupler_to_l2_ctrl_auto_tl_in_d_bits_corrupt) ); // @[LazyScope.scala:98:27] TLInterconnectCoupler_cbus_to_clint coupler_to_clint ( // @[LazyScope.scala:98:27] .clock (childClock), // @[LazyModuleImp.scala:155:31] .reset (childReset), // @[LazyModuleImp.scala:158:31] .auto_fragmenter_anon_out_a_ready (auto_coupler_to_clint_fragmenter_anon_out_a_ready_0), // @[ClockDomain.scala:14:9] .auto_fragmenter_anon_out_a_valid (auto_coupler_to_clint_fragmenter_anon_out_a_valid_0), .auto_fragmenter_anon_out_a_bits_opcode (auto_coupler_to_clint_fragmenter_anon_out_a_bits_opcode_0), .auto_fragmenter_anon_out_a_bits_param (auto_coupler_to_clint_fragmenter_anon_out_a_bits_param_0), .auto_fragmenter_anon_out_a_bits_size (auto_coupler_to_clint_fragmenter_anon_out_a_bits_size_0), .auto_fragmenter_anon_out_a_bits_source (auto_coupler_to_clint_fragmenter_anon_out_a_bits_source_0), .auto_fragmenter_anon_out_a_bits_address (auto_coupler_to_clint_fragmenter_anon_out_a_bits_address_0), .auto_fragmenter_anon_out_a_bits_mask (auto_coupler_to_clint_fragmenter_anon_out_a_bits_mask_0), .auto_fragmenter_anon_out_a_bits_data (auto_coupler_to_clint_fragmenter_anon_out_a_bits_data_0), .auto_fragmenter_anon_out_a_bits_corrupt (auto_coupler_to_clint_fragmenter_anon_out_a_bits_corrupt_0), .auto_fragmenter_anon_out_d_ready (auto_coupler_to_clint_fragmenter_anon_out_d_ready_0), .auto_fragmenter_anon_out_d_valid (auto_coupler_to_clint_fragmenter_anon_out_d_valid_0), // @[ClockDomain.scala:14:9] .auto_fragmenter_anon_out_d_bits_opcode (auto_coupler_to_clint_fragmenter_anon_out_d_bits_opcode_0), // @[ClockDomain.scala:14:9] .auto_fragmenter_anon_out_d_bits_size (auto_coupler_to_clint_fragmenter_anon_out_d_bits_size_0), // @[ClockDomain.scala:14:9] .auto_fragmenter_anon_out_d_bits_source (auto_coupler_to_clint_fragmenter_anon_out_d_bits_source_0), // @[ClockDomain.scala:14:9] .auto_fragmenter_anon_out_d_bits_data (auto_coupler_to_clint_fragmenter_anon_out_d_bits_data_0), // @[ClockDomain.scala:14:9] .auto_tl_in_a_ready (_coupler_to_clint_auto_tl_in_a_ready), .auto_tl_in_a_valid (_out_xbar_auto_anon_out_3_a_valid), // @[PeripheryBus.scala:57:30] .auto_tl_in_a_bits_opcode (_out_xbar_auto_anon_out_3_a_bits_opcode), // @[PeripheryBus.scala:57:30] .auto_tl_in_a_bits_param (_out_xbar_auto_anon_out_3_a_bits_param), // @[PeripheryBus.scala:57:30] .auto_tl_in_a_bits_size (_out_xbar_auto_anon_out_3_a_bits_size), // @[PeripheryBus.scala:57:30] .auto_tl_in_a_bits_source (_out_xbar_auto_anon_out_3_a_bits_source), // @[PeripheryBus.scala:57:30] .auto_tl_in_a_bits_address (_out_xbar_auto_anon_out_3_a_bits_address), // @[PeripheryBus.scala:57:30] .auto_tl_in_a_bits_mask (_out_xbar_auto_anon_out_3_a_bits_mask), // @[PeripheryBus.scala:57:30] .auto_tl_in_a_bits_data (_out_xbar_auto_anon_out_3_a_bits_data), // @[PeripheryBus.scala:57:30] .auto_tl_in_a_bits_corrupt (_out_xbar_auto_anon_out_3_a_bits_corrupt), // @[PeripheryBus.scala:57:30] .auto_tl_in_d_ready (_out_xbar_auto_anon_out_3_d_ready), // @[PeripheryBus.scala:57:30] .auto_tl_in_d_valid (_coupler_to_clint_auto_tl_in_d_valid), .auto_tl_in_d_bits_opcode (_coupler_to_clint_auto_tl_in_d_bits_opcode), .auto_tl_in_d_bits_size (_coupler_to_clint_auto_tl_in_d_bits_size), .auto_tl_in_d_bits_source (_coupler_to_clint_auto_tl_in_d_bits_source), .auto_tl_in_d_bits_data (_coupler_to_clint_auto_tl_in_d_bits_data) ); // @[LazyScope.scala:98:27] TLInterconnectCoupler_cbus_to_plic coupler_to_plic ( // @[LazyScope.scala:98:27] .clock (childClock), // @[LazyModuleImp.scala:155:31] .reset (childReset), // @[LazyModuleImp.scala:158:31] .auto_fragmenter_anon_out_a_ready (auto_coupler_to_plic_fragmenter_anon_out_a_ready_0), // @[ClockDomain.scala:14:9] .auto_fragmenter_anon_out_a_valid (auto_coupler_to_plic_fragmenter_anon_out_a_valid_0), .auto_fragmenter_anon_out_a_bits_opcode (auto_coupler_to_plic_fragmenter_anon_out_a_bits_opcode_0), .auto_fragmenter_anon_out_a_bits_param (auto_coupler_to_plic_fragmenter_anon_out_a_bits_param_0), .auto_fragmenter_anon_out_a_bits_size (auto_coupler_to_plic_fragmenter_anon_out_a_bits_size_0), .auto_fragmenter_anon_out_a_bits_source (auto_coupler_to_plic_fragmenter_anon_out_a_bits_source_0), .auto_fragmenter_anon_out_a_bits_address (auto_coupler_to_plic_fragmenter_anon_out_a_bits_address_0), .auto_fragmenter_anon_out_a_bits_mask (auto_coupler_to_plic_fragmenter_anon_out_a_bits_mask_0), .auto_fragmenter_anon_out_a_bits_data (auto_coupler_to_plic_fragmenter_anon_out_a_bits_data_0), .auto_fragmenter_anon_out_a_bits_corrupt (auto_coupler_to_plic_fragmenter_anon_out_a_bits_corrupt_0), .auto_fragmenter_anon_out_d_ready (auto_coupler_to_plic_fragmenter_anon_out_d_ready_0), .auto_fragmenter_anon_out_d_valid (auto_coupler_to_plic_fragmenter_anon_out_d_valid_0), // @[ClockDomain.scala:14:9] .auto_fragmenter_anon_out_d_bits_opcode (auto_coupler_to_plic_fragmenter_anon_out_d_bits_opcode_0), // @[ClockDomain.scala:14:9] .auto_fragmenter_anon_out_d_bits_size (auto_coupler_to_plic_fragmenter_anon_out_d_bits_size_0), // @[ClockDomain.scala:14:9] .auto_fragmenter_anon_out_d_bits_source (auto_coupler_to_plic_fragmenter_anon_out_d_bits_source_0), // @[ClockDomain.scala:14:9] .auto_fragmenter_anon_out_d_bits_data (auto_coupler_to_plic_fragmenter_anon_out_d_bits_data_0), // @[ClockDomain.scala:14:9] .auto_tl_in_a_ready (_coupler_to_plic_auto_tl_in_a_ready), .auto_tl_in_a_valid (_out_xbar_auto_anon_out_4_a_valid), // @[PeripheryBus.scala:57:30] .auto_tl_in_a_bits_opcode (_out_xbar_auto_anon_out_4_a_bits_opcode), // @[PeripheryBus.scala:57:30] .auto_tl_in_a_bits_param (_out_xbar_auto_anon_out_4_a_bits_param), // @[PeripheryBus.scala:57:30] .auto_tl_in_a_bits_size (_out_xbar_auto_anon_out_4_a_bits_size), // @[PeripheryBus.scala:57:30] .auto_tl_in_a_bits_source (_out_xbar_auto_anon_out_4_a_bits_source), // @[PeripheryBus.scala:57:30] .auto_tl_in_a_bits_address (_out_xbar_auto_anon_out_4_a_bits_address), // @[PeripheryBus.scala:57:30] .auto_tl_in_a_bits_mask (_out_xbar_auto_anon_out_4_a_bits_mask), // @[PeripheryBus.scala:57:30] .auto_tl_in_a_bits_data (_out_xbar_auto_anon_out_4_a_bits_data), // @[PeripheryBus.scala:57:30] .auto_tl_in_a_bits_corrupt (_out_xbar_auto_anon_out_4_a_bits_corrupt), // @[PeripheryBus.scala:57:30] .auto_tl_in_d_ready (_out_xbar_auto_anon_out_4_d_ready), // @[PeripheryBus.scala:57:30] .auto_tl_in_d_valid (_coupler_to_plic_auto_tl_in_d_valid), .auto_tl_in_d_bits_opcode (_coupler_to_plic_auto_tl_in_d_bits_opcode), .auto_tl_in_d_bits_size (_coupler_to_plic_auto_tl_in_d_bits_size), .auto_tl_in_d_bits_source (_coupler_to_plic_auto_tl_in_d_bits_source), .auto_tl_in_d_bits_data (_coupler_to_plic_auto_tl_in_d_bits_data) ); // @[LazyScope.scala:98:27] TLInterconnectCoupler_cbus_to_debug coupler_to_debug ( // @[LazyScope.scala:98:27] .clock (childClock), // @[LazyModuleImp.scala:155:31] .reset (childReset), // @[LazyModuleImp.scala:158:31] .auto_fragmenter_anon_out_a_ready (auto_coupler_to_debug_fragmenter_anon_out_a_ready_0), // @[ClockDomain.scala:14:9] .auto_fragmenter_anon_out_a_valid (auto_coupler_to_debug_fragmenter_anon_out_a_valid_0), .auto_fragmenter_anon_out_a_bits_opcode (auto_coupler_to_debug_fragmenter_anon_out_a_bits_opcode_0), .auto_fragmenter_anon_out_a_bits_param (auto_coupler_to_debug_fragmenter_anon_out_a_bits_param_0), .auto_fragmenter_anon_out_a_bits_size (auto_coupler_to_debug_fragmenter_anon_out_a_bits_size_0), .auto_fragmenter_anon_out_a_bits_source (auto_coupler_to_debug_fragmenter_anon_out_a_bits_source_0), .auto_fragmenter_anon_out_a_bits_address (auto_coupler_to_debug_fragmenter_anon_out_a_bits_address_0), .auto_fragmenter_anon_out_a_bits_mask (auto_coupler_to_debug_fragmenter_anon_out_a_bits_mask_0), .auto_fragmenter_anon_out_a_bits_data (auto_coupler_to_debug_fragmenter_anon_out_a_bits_data_0), .auto_fragmenter_anon_out_a_bits_corrupt (auto_coupler_to_debug_fragmenter_anon_out_a_bits_corrupt_0), .auto_fragmenter_anon_out_d_ready (auto_coupler_to_debug_fragmenter_anon_out_d_ready_0), .auto_fragmenter_anon_out_d_valid (auto_coupler_to_debug_fragmenter_anon_out_d_valid_0), // @[ClockDomain.scala:14:9] .auto_fragmenter_anon_out_d_bits_opcode (auto_coupler_to_debug_fragmenter_anon_out_d_bits_opcode_0), // @[ClockDomain.scala:14:9] .auto_fragmenter_anon_out_d_bits_size (auto_coupler_to_debug_fragmenter_anon_out_d_bits_size_0), // @[ClockDomain.scala:14:9] .auto_fragmenter_anon_out_d_bits_source (auto_coupler_to_debug_fragmenter_anon_out_d_bits_source_0), // @[ClockDomain.scala:14:9] .auto_fragmenter_anon_out_d_bits_data (auto_coupler_to_debug_fragmenter_anon_out_d_bits_data_0), // @[ClockDomain.scala:14:9] .auto_tl_in_a_ready (_coupler_to_debug_auto_tl_in_a_ready), .auto_tl_in_a_valid (_out_xbar_auto_anon_out_5_a_valid), // @[PeripheryBus.scala:57:30] .auto_tl_in_a_bits_opcode (_out_xbar_auto_anon_out_5_a_bits_opcode), // @[PeripheryBus.scala:57:30] .auto_tl_in_a_bits_param (_out_xbar_auto_anon_out_5_a_bits_param), // @[PeripheryBus.scala:57:30] .auto_tl_in_a_bits_size (_out_xbar_auto_anon_out_5_a_bits_size), // @[PeripheryBus.scala:57:30] .auto_tl_in_a_bits_source (_out_xbar_auto_anon_out_5_a_bits_source), // @[PeripheryBus.scala:57:30] .auto_tl_in_a_bits_address (_out_xbar_auto_anon_out_5_a_bits_address), // @[PeripheryBus.scala:57:30] .auto_tl_in_a_bits_mask (_out_xbar_auto_anon_out_5_a_bits_mask), // @[PeripheryBus.scala:57:30] .auto_tl_in_a_bits_data (_out_xbar_auto_anon_out_5_a_bits_data), // @[PeripheryBus.scala:57:30] .auto_tl_in_a_bits_corrupt (_out_xbar_auto_anon_out_5_a_bits_corrupt), // @[PeripheryBus.scala:57:30] .auto_tl_in_d_ready (_out_xbar_auto_anon_out_5_d_ready), // @[PeripheryBus.scala:57:30] .auto_tl_in_d_valid (_coupler_to_debug_auto_tl_in_d_valid), .auto_tl_in_d_bits_opcode (_coupler_to_debug_auto_tl_in_d_bits_opcode), .auto_tl_in_d_bits_size (_coupler_to_debug_auto_tl_in_d_bits_size), .auto_tl_in_d_bits_source (_coupler_to_debug_auto_tl_in_d_bits_source), .auto_tl_in_d_bits_data (_coupler_to_debug_auto_tl_in_d_bits_data) ); // @[LazyScope.scala:98:27] TLInterconnectCoupler_cbus_to_bootrom coupler_to_bootrom ( // @[LazyScope.scala:98:27] .clock (childClock), // @[LazyModuleImp.scala:155:31] .reset (childReset), // @[LazyModuleImp.scala:158:31] .auto_fragmenter_anon_out_a_ready (auto_coupler_to_bootrom_fragmenter_anon_out_a_ready_0), // @[ClockDomain.scala:14:9] .auto_fragmenter_anon_out_a_valid (auto_coupler_to_bootrom_fragmenter_anon_out_a_valid_0), .auto_fragmenter_anon_out_a_bits_opcode (auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_opcode_0), .auto_fragmenter_anon_out_a_bits_param (auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_param_0), .auto_fragmenter_anon_out_a_bits_size (auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_size_0), .auto_fragmenter_anon_out_a_bits_source (auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_source_0), .auto_fragmenter_anon_out_a_bits_address (auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_address_0), .auto_fragmenter_anon_out_a_bits_mask (auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_mask_0), .auto_fragmenter_anon_out_a_bits_data (auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_data_0), .auto_fragmenter_anon_out_a_bits_corrupt (auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_corrupt_0), .auto_fragmenter_anon_out_d_ready (auto_coupler_to_bootrom_fragmenter_anon_out_d_ready_0), .auto_fragmenter_anon_out_d_valid (auto_coupler_to_bootrom_fragmenter_anon_out_d_valid_0), // @[ClockDomain.scala:14:9] .auto_fragmenter_anon_out_d_bits_size (auto_coupler_to_bootrom_fragmenter_anon_out_d_bits_size_0), // @[ClockDomain.scala:14:9] .auto_fragmenter_anon_out_d_bits_source (auto_coupler_to_bootrom_fragmenter_anon_out_d_bits_source_0), // @[ClockDomain.scala:14:9] .auto_fragmenter_anon_out_d_bits_data (auto_coupler_to_bootrom_fragmenter_anon_out_d_bits_data_0), // @[ClockDomain.scala:14:9] .auto_tl_in_a_ready (_coupler_to_bootrom_auto_tl_in_a_ready), .auto_tl_in_a_valid (_out_xbar_auto_anon_out_6_a_valid), // @[PeripheryBus.scala:57:30] .auto_tl_in_a_bits_opcode (_out_xbar_auto_anon_out_6_a_bits_opcode), // @[PeripheryBus.scala:57:30] .auto_tl_in_a_bits_param (_out_xbar_auto_anon_out_6_a_bits_param), // @[PeripheryBus.scala:57:30] .auto_tl_in_a_bits_size (_out_xbar_auto_anon_out_6_a_bits_size), // @[PeripheryBus.scala:57:30] .auto_tl_in_a_bits_source (_out_xbar_auto_anon_out_6_a_bits_source), // @[PeripheryBus.scala:57:30] .auto_tl_in_a_bits_address (_out_xbar_auto_anon_out_6_a_bits_address), // @[PeripheryBus.scala:57:30] .auto_tl_in_a_bits_mask (_out_xbar_auto_anon_out_6_a_bits_mask), // @[PeripheryBus.scala:57:30] .auto_tl_in_a_bits_data (_out_xbar_auto_anon_out_6_a_bits_data), // @[PeripheryBus.scala:57:30] .auto_tl_in_a_bits_corrupt (_out_xbar_auto_anon_out_6_a_bits_corrupt), // @[PeripheryBus.scala:57:30] .auto_tl_in_d_ready (_out_xbar_auto_anon_out_6_d_ready), // @[PeripheryBus.scala:57:30] .auto_tl_in_d_valid (_coupler_to_bootrom_auto_tl_in_d_valid), .auto_tl_in_d_bits_size (_coupler_to_bootrom_auto_tl_in_d_bits_size), .auto_tl_in_d_bits_source (_coupler_to_bootrom_auto_tl_in_d_bits_source), .auto_tl_in_d_bits_data (_coupler_to_bootrom_auto_tl_in_d_bits_data) ); // @[LazyScope.scala:98:27] TLInterconnectCoupler_cbus_to_prci_ctrl coupler_to_prci_ctrl ( // @[LazyScope.scala:98:27] .clock (childClock), // @[LazyModuleImp.scala:155:31] .reset (childReset), // @[LazyModuleImp.scala:158:31] .auto_fixer_anon_out_a_ready (auto_coupler_to_prci_ctrl_fixer_anon_out_a_ready_0), // @[ClockDomain.scala:14:9] .auto_fixer_anon_out_a_valid (auto_coupler_to_prci_ctrl_fixer_anon_out_a_valid_0), .auto_fixer_anon_out_a_bits_opcode (auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_opcode_0), .auto_fixer_anon_out_a_bits_param (auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_param_0), .auto_fixer_anon_out_a_bits_size (auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_size_0), .auto_fixer_anon_out_a_bits_source (auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_source_0), .auto_fixer_anon_out_a_bits_address (auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_address_0), .auto_fixer_anon_out_a_bits_mask (auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_mask_0), .auto_fixer_anon_out_a_bits_data (auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_data_0), .auto_fixer_anon_out_a_bits_corrupt (auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_corrupt_0), .auto_fixer_anon_out_d_ready (auto_coupler_to_prci_ctrl_fixer_anon_out_d_ready_0), .auto_fixer_anon_out_d_valid (auto_coupler_to_prci_ctrl_fixer_anon_out_d_valid_0), // @[ClockDomain.scala:14:9] .auto_fixer_anon_out_d_bits_opcode (auto_coupler_to_prci_ctrl_fixer_anon_out_d_bits_opcode_0), // @[ClockDomain.scala:14:9] .auto_fixer_anon_out_d_bits_size (auto_coupler_to_prci_ctrl_fixer_anon_out_d_bits_size_0), // @[ClockDomain.scala:14:9] .auto_fixer_anon_out_d_bits_source (auto_coupler_to_prci_ctrl_fixer_anon_out_d_bits_source_0), // @[ClockDomain.scala:14:9] .auto_fixer_anon_out_d_bits_data (auto_coupler_to_prci_ctrl_fixer_anon_out_d_bits_data_0), // @[ClockDomain.scala:14:9] .auto_tl_in_a_ready (_coupler_to_prci_ctrl_auto_tl_in_a_ready), .auto_tl_in_a_valid (_out_xbar_auto_anon_out_7_a_valid), // @[PeripheryBus.scala:57:30] .auto_tl_in_a_bits_opcode (_out_xbar_auto_anon_out_7_a_bits_opcode), // @[PeripheryBus.scala:57:30] .auto_tl_in_a_bits_param (_out_xbar_auto_anon_out_7_a_bits_param), // @[PeripheryBus.scala:57:30] .auto_tl_in_a_bits_size (_out_xbar_auto_anon_out_7_a_bits_size), // @[PeripheryBus.scala:57:30] .auto_tl_in_a_bits_source (_out_xbar_auto_anon_out_7_a_bits_source), // @[PeripheryBus.scala:57:30] .auto_tl_in_a_bits_address (_out_xbar_auto_anon_out_7_a_bits_address), // @[PeripheryBus.scala:57:30] .auto_tl_in_a_bits_mask (_out_xbar_auto_anon_out_7_a_bits_mask), // @[PeripheryBus.scala:57:30] .auto_tl_in_a_bits_data (_out_xbar_auto_anon_out_7_a_bits_data), // @[PeripheryBus.scala:57:30] .auto_tl_in_a_bits_corrupt (_out_xbar_auto_anon_out_7_a_bits_corrupt), // @[PeripheryBus.scala:57:30] .auto_tl_in_d_ready (_out_xbar_auto_anon_out_7_d_ready), // @[PeripheryBus.scala:57:30] .auto_tl_in_d_valid (_coupler_to_prci_ctrl_auto_tl_in_d_valid), .auto_tl_in_d_bits_opcode (_coupler_to_prci_ctrl_auto_tl_in_d_bits_opcode), .auto_tl_in_d_bits_param (_coupler_to_prci_ctrl_auto_tl_in_d_bits_param), .auto_tl_in_d_bits_size (_coupler_to_prci_ctrl_auto_tl_in_d_bits_size), .auto_tl_in_d_bits_source (_coupler_to_prci_ctrl_auto_tl_in_d_bits_source), .auto_tl_in_d_bits_sink (_coupler_to_prci_ctrl_auto_tl_in_d_bits_sink), .auto_tl_in_d_bits_denied (_coupler_to_prci_ctrl_auto_tl_in_d_bits_denied), .auto_tl_in_d_bits_data (_coupler_to_prci_ctrl_auto_tl_in_d_bits_data), .auto_tl_in_d_bits_corrupt (_coupler_to_prci_ctrl_auto_tl_in_d_bits_corrupt) ); // @[LazyScope.scala:98:27] assign auto_coupler_to_prci_ctrl_fixer_anon_out_a_valid = auto_coupler_to_prci_ctrl_fixer_anon_out_a_valid_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_opcode = auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_opcode_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_param = auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_param_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_size = auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_size_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_source = auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_source_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_address = auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_address_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_mask = auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_mask_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_data = auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_data_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_corrupt = auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_corrupt_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_prci_ctrl_fixer_anon_out_d_ready = auto_coupler_to_prci_ctrl_fixer_anon_out_d_ready_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bootrom_fragmenter_anon_out_a_valid = auto_coupler_to_bootrom_fragmenter_anon_out_a_valid_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_opcode = auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_opcode_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_param = auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_param_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_size = auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_size_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_source = auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_source_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_address = auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_address_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_mask = auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_mask_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_data = auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_data_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_corrupt = auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_corrupt_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bootrom_fragmenter_anon_out_d_ready = auto_coupler_to_bootrom_fragmenter_anon_out_d_ready_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_debug_fragmenter_anon_out_a_valid = auto_coupler_to_debug_fragmenter_anon_out_a_valid_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_debug_fragmenter_anon_out_a_bits_opcode = auto_coupler_to_debug_fragmenter_anon_out_a_bits_opcode_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_debug_fragmenter_anon_out_a_bits_param = auto_coupler_to_debug_fragmenter_anon_out_a_bits_param_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_debug_fragmenter_anon_out_a_bits_size = auto_coupler_to_debug_fragmenter_anon_out_a_bits_size_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_debug_fragmenter_anon_out_a_bits_source = auto_coupler_to_debug_fragmenter_anon_out_a_bits_source_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_debug_fragmenter_anon_out_a_bits_address = auto_coupler_to_debug_fragmenter_anon_out_a_bits_address_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_debug_fragmenter_anon_out_a_bits_mask = auto_coupler_to_debug_fragmenter_anon_out_a_bits_mask_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_debug_fragmenter_anon_out_a_bits_data = auto_coupler_to_debug_fragmenter_anon_out_a_bits_data_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_debug_fragmenter_anon_out_a_bits_corrupt = auto_coupler_to_debug_fragmenter_anon_out_a_bits_corrupt_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_debug_fragmenter_anon_out_d_ready = auto_coupler_to_debug_fragmenter_anon_out_d_ready_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_plic_fragmenter_anon_out_a_valid = auto_coupler_to_plic_fragmenter_anon_out_a_valid_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_plic_fragmenter_anon_out_a_bits_opcode = auto_coupler_to_plic_fragmenter_anon_out_a_bits_opcode_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_plic_fragmenter_anon_out_a_bits_param = auto_coupler_to_plic_fragmenter_anon_out_a_bits_param_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_plic_fragmenter_anon_out_a_bits_size = auto_coupler_to_plic_fragmenter_anon_out_a_bits_size_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_plic_fragmenter_anon_out_a_bits_source = auto_coupler_to_plic_fragmenter_anon_out_a_bits_source_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_plic_fragmenter_anon_out_a_bits_address = auto_coupler_to_plic_fragmenter_anon_out_a_bits_address_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_plic_fragmenter_anon_out_a_bits_mask = auto_coupler_to_plic_fragmenter_anon_out_a_bits_mask_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_plic_fragmenter_anon_out_a_bits_data = auto_coupler_to_plic_fragmenter_anon_out_a_bits_data_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_plic_fragmenter_anon_out_a_bits_corrupt = auto_coupler_to_plic_fragmenter_anon_out_a_bits_corrupt_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_plic_fragmenter_anon_out_d_ready = auto_coupler_to_plic_fragmenter_anon_out_d_ready_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_clint_fragmenter_anon_out_a_valid = auto_coupler_to_clint_fragmenter_anon_out_a_valid_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_clint_fragmenter_anon_out_a_bits_opcode = auto_coupler_to_clint_fragmenter_anon_out_a_bits_opcode_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_clint_fragmenter_anon_out_a_bits_param = auto_coupler_to_clint_fragmenter_anon_out_a_bits_param_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_clint_fragmenter_anon_out_a_bits_size = auto_coupler_to_clint_fragmenter_anon_out_a_bits_size_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_clint_fragmenter_anon_out_a_bits_source = auto_coupler_to_clint_fragmenter_anon_out_a_bits_source_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_clint_fragmenter_anon_out_a_bits_address = auto_coupler_to_clint_fragmenter_anon_out_a_bits_address_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_clint_fragmenter_anon_out_a_bits_mask = auto_coupler_to_clint_fragmenter_anon_out_a_bits_mask_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_clint_fragmenter_anon_out_a_bits_data = auto_coupler_to_clint_fragmenter_anon_out_a_bits_data_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_clint_fragmenter_anon_out_a_bits_corrupt = auto_coupler_to_clint_fragmenter_anon_out_a_bits_corrupt_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_clint_fragmenter_anon_out_d_ready = auto_coupler_to_clint_fragmenter_anon_out_d_ready_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bus_named_pbus_bus_xing_out_a_valid = auto_coupler_to_bus_named_pbus_bus_xing_out_a_valid_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_opcode = auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_opcode_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_param = auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_param_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_size = auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_size_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_source = auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_source_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_address = auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_address_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_mask = auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_mask_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_data = auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_data_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_corrupt = auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_corrupt_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bus_named_pbus_bus_xing_out_d_ready = auto_coupler_to_bus_named_pbus_bus_xing_out_d_ready_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_l2_ctrl_buffer_out_a_valid = auto_coupler_to_l2_ctrl_buffer_out_a_valid_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_l2_ctrl_buffer_out_a_bits_opcode = auto_coupler_to_l2_ctrl_buffer_out_a_bits_opcode_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_l2_ctrl_buffer_out_a_bits_param = auto_coupler_to_l2_ctrl_buffer_out_a_bits_param_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_l2_ctrl_buffer_out_a_bits_size = auto_coupler_to_l2_ctrl_buffer_out_a_bits_size_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_l2_ctrl_buffer_out_a_bits_source = auto_coupler_to_l2_ctrl_buffer_out_a_bits_source_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_l2_ctrl_buffer_out_a_bits_address = auto_coupler_to_l2_ctrl_buffer_out_a_bits_address_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_l2_ctrl_buffer_out_a_bits_mask = auto_coupler_to_l2_ctrl_buffer_out_a_bits_mask_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_l2_ctrl_buffer_out_a_bits_data = auto_coupler_to_l2_ctrl_buffer_out_a_bits_data_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_l2_ctrl_buffer_out_a_bits_corrupt = auto_coupler_to_l2_ctrl_buffer_out_a_bits_corrupt_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_l2_ctrl_buffer_out_d_ready = auto_coupler_to_l2_ctrl_buffer_out_d_ready_0; // @[ClockDomain.scala:14:9] assign auto_fixedClockNode_anon_out_5_clock = auto_fixedClockNode_anon_out_5_clock_0; // @[ClockDomain.scala:14:9] assign auto_fixedClockNode_anon_out_5_reset = auto_fixedClockNode_anon_out_5_reset_0; // @[ClockDomain.scala:14:9] assign auto_fixedClockNode_anon_out_4_clock = auto_fixedClockNode_anon_out_4_clock_0; // @[ClockDomain.scala:14:9] assign auto_fixedClockNode_anon_out_4_reset = auto_fixedClockNode_anon_out_4_reset_0; // @[ClockDomain.scala:14:9] assign auto_fixedClockNode_anon_out_3_clock = auto_fixedClockNode_anon_out_3_clock_0; // @[ClockDomain.scala:14:9] assign auto_fixedClockNode_anon_out_3_reset = auto_fixedClockNode_anon_out_3_reset_0; // @[ClockDomain.scala:14:9] assign auto_fixedClockNode_anon_out_2_clock = auto_fixedClockNode_anon_out_2_clock_0; // @[ClockDomain.scala:14:9] assign auto_fixedClockNode_anon_out_2_reset = auto_fixedClockNode_anon_out_2_reset_0; // @[ClockDomain.scala:14:9] assign auto_fixedClockNode_anon_out_1_clock = auto_fixedClockNode_anon_out_1_clock_0; // @[ClockDomain.scala:14:9] assign auto_fixedClockNode_anon_out_1_reset = auto_fixedClockNode_anon_out_1_reset_0; // @[ClockDomain.scala:14:9] assign auto_fixedClockNode_anon_out_0_clock = auto_fixedClockNode_anon_out_0_clock_0; // @[ClockDomain.scala:14:9] assign auto_fixedClockNode_anon_out_0_reset = auto_fixedClockNode_anon_out_0_reset_0; // @[ClockDomain.scala:14:9] assign auto_bus_xing_in_a_ready = auto_bus_xing_in_a_ready_0; // @[ClockDomain.scala:14:9] assign auto_bus_xing_in_d_valid = auto_bus_xing_in_d_valid_0; // @[ClockDomain.scala:14:9] assign auto_bus_xing_in_d_bits_opcode = auto_bus_xing_in_d_bits_opcode_0; // @[ClockDomain.scala:14:9] assign auto_bus_xing_in_d_bits_param = auto_bus_xing_in_d_bits_param_0; // @[ClockDomain.scala:14:9] assign auto_bus_xing_in_d_bits_size = auto_bus_xing_in_d_bits_size_0; // @[ClockDomain.scala:14:9] assign auto_bus_xing_in_d_bits_source = auto_bus_xing_in_d_bits_source_0; // @[ClockDomain.scala:14:9] assign auto_bus_xing_in_d_bits_sink = auto_bus_xing_in_d_bits_sink_0; // @[ClockDomain.scala:14:9] assign auto_bus_xing_in_d_bits_denied = auto_bus_xing_in_d_bits_denied_0; // @[ClockDomain.scala:14:9] assign auto_bus_xing_in_d_bits_data = auto_bus_xing_in_d_bits_data_0; // @[ClockDomain.scala:14:9] assign auto_bus_xing_in_d_bits_corrupt = auto_bus_xing_in_d_bits_corrupt_0; // @[ClockDomain.scala:14:9] endmodule

Generate the Verilog code corresponding to the following Chisel files. File Monitor.scala: package constellation.channel import chisel3._ import chisel3.util._ import freechips.rocketchip.diplomacy._ import org.chipsalliance.cde.config.{Parameters} import freechips.rocketchip.util._ import constellation.noc.{HasNoCParams} class NoCMonitor(val cParam: ChannelParams)(implicit val p: Parameters) extends Module with HasNoCParams { val io = IO(new Bundle { val in = Input(new Channel(cParam)) }) val in_flight = RegInit(VecInit(Seq.fill(cParam.nVirtualChannels) { false.B })) for (i <- 0 until cParam.srcSpeedup) { val flit = io.in.flit(i) when (flit.valid) { when (flit.bits.head) { in_flight(flit.bits.virt_channel_id) := true.B assert (!in_flight(flit.bits.virt_channel_id), "Flit head/tail sequencing is broken") } when (flit.bits.tail) { in_flight(flit.bits.virt_channel_id) := false.B } } val possibleFlows = cParam.possibleFlows when (flit.valid && flit.bits.head) { cParam match { case n: ChannelParams => n.virtualChannelParams.zipWithIndex.foreach { case (v,i) => assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR) } case _ => assert(cParam.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR) } } } } File Types.scala: package constellation.routing import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.{Parameters} import constellation.noc.{HasNoCParams} import constellation.channel.{Flit} /** A representation for 1 specific virtual channel in wormhole routing * * @param src the source node * @param vc ID for the virtual channel * @param dst the destination node * @param n_vc the number of virtual channels */ // BEGIN: ChannelRoutingInfo case class ChannelRoutingInfo( src: Int, dst: Int, vc: Int, n_vc: Int ) { // END: ChannelRoutingInfo require (src >= -1 && dst >= -1 && vc >= 0, s"Illegal $this") require (!(src == -1 && dst == -1), s"Illegal $this") require (vc < n_vc, s"Illegal $this") val isIngress = src == -1 val isEgress = dst == -1 } /** Represents the properties of a packet that are relevant for routing * ingressId and egressId uniquely identify a flow, but vnet and dst are used here * to simplify the implementation of routingrelations * * @param ingressId packet's source ingress point * @param egressId packet's destination egress point * @param vNet virtual subnetwork identifier * @param dst packet's destination node ID */ // BEGIN: FlowRoutingInfo case class FlowRoutingInfo( ingressId: Int, egressId: Int, vNetId: Int, ingressNode: Int, ingressNodeId: Int, egressNode: Int, egressNodeId: Int, fifo: Boolean ) { // END: FlowRoutingInfo def isFlow(f: FlowRoutingBundle): Bool = { (f.ingress_node === ingressNode.U && f.egress_node === egressNode.U && f.ingress_node_id === ingressNodeId.U && f.egress_node_id === egressNodeId.U) } def asLiteral(b: FlowRoutingBundle): BigInt = { Seq( (vNetId , b.vnet_id), (ingressNode , b.ingress_node), (ingressNodeId , b.ingress_node_id), (egressNode , b.egress_node), (egressNodeId , b.egress_node_id) ).foldLeft(0)((l, t) => { (l << t._2.getWidth) | t._1 }) } } class FlowRoutingBundle(implicit val p: Parameters) extends Bundle with HasNoCParams { // Instead of tracking ingress/egress ID, track the physical destination id and the offset at the destination // This simplifies the routing tables val vnet_id = UInt(log2Ceil(nVirtualNetworks).W) val ingress_node = UInt(log2Ceil(nNodes).W) val ingress_node_id = UInt(log2Ceil(maxIngressesAtNode).W) val egress_node = UInt(log2Ceil(nNodes).W) val egress_node_id = UInt(log2Ceil(maxEgressesAtNode).W) }

module NoCMonitor_53( // @[Monitor.scala:11:7] input clock, // @[Monitor.scala:11:7] input reset, // @[Monitor.scala:11:7] input io_in_flit_0_valid, // @[Monitor.scala:12:14] input io_in_flit_0_bits_head, // @[Monitor.scala:12:14] input io_in_flit_0_bits_tail, // @[Monitor.scala:12:14] input [5:0] io_in_flit_0_bits_flow_ingress_node, // @[Monitor.scala:12:14] input [2:0] io_in_flit_0_bits_flow_ingress_node_id, // @[Monitor.scala:12:14] input [5:0] io_in_flit_0_bits_flow_egress_node, // @[Monitor.scala:12:14] input [2:0] io_in_flit_0_bits_flow_egress_node_id, // @[Monitor.scala:12:14] input [4:0] io_in_flit_0_bits_virt_channel_id // @[Monitor.scala:12:14] ); reg in_flight_0; // @[Monitor.scala:16:26] reg in_flight_1; // @[Monitor.scala:16:26] reg in_flight_2; // @[Monitor.scala:16:26] reg in_flight_3; // @[Monitor.scala:16:26] reg in_flight_4; // @[Monitor.scala:16:26] reg in_flight_5; // @[Monitor.scala:16:26] reg in_flight_6; // @[Monitor.scala:16:26] reg in_flight_7; // @[Monitor.scala:16:26] reg in_flight_8; // @[Monitor.scala:16:26] reg in_flight_9; // @[Monitor.scala:16:26] reg in_flight_10; // @[Monitor.scala:16:26] reg in_flight_11; // @[Monitor.scala:16:26] reg in_flight_12; // @[Monitor.scala:16:26] reg in_flight_13; // @[Monitor.scala:16:26] reg in_flight_14; // @[Monitor.scala:16:26] reg in_flight_15; // @[Monitor.scala:16:26] reg in_flight_16; // @[Monitor.scala:16:26] reg in_flight_17; // @[Monitor.scala:16:26] reg in_flight_18; // @[Monitor.scala:16:26] reg in_flight_19; // @[Monitor.scala:16:26] reg in_flight_20; // @[Monitor.scala:16:26] reg in_flight_21; // @[Monitor.scala:16:26] wire _GEN = io_in_flit_0_bits_virt_channel_id == 5'h0; // @[Monitor.scala:21:46] wire _GEN_0 = io_in_flit_0_bits_virt_channel_id == 5'h1; // @[Monitor.scala:21:46] wire _GEN_1 = io_in_flit_0_bits_virt_channel_id == 5'h2; // @[Monitor.scala:21:46] wire _GEN_2 = io_in_flit_0_bits_virt_channel_id == 5'h3; // @[Monitor.scala:21:46] wire _GEN_3 = io_in_flit_0_bits_virt_channel_id == 5'h4; // @[Monitor.scala:21:46] wire _GEN_4 = io_in_flit_0_bits_virt_channel_id == 5'h5; // @[Monitor.scala:21:46] wire _GEN_5 = io_in_flit_0_bits_virt_channel_id == 5'h6; // @[Monitor.scala:21:46] wire _GEN_6 = io_in_flit_0_bits_virt_channel_id == 5'h7; // @[Monitor.scala:21:46] wire _GEN_7 = io_in_flit_0_bits_virt_channel_id == 5'h8; // @[Monitor.scala:21:46] wire _GEN_8 = io_in_flit_0_bits_virt_channel_id == 5'h9; // @[Monitor.scala:21:46] wire _GEN_9 = io_in_flit_0_bits_virt_channel_id == 5'hA; // @[Monitor.scala:21:46] wire _GEN_10 = io_in_flit_0_bits_virt_channel_id == 5'hB; // @[Monitor.scala:21:46] wire _GEN_11 = io_in_flit_0_bits_virt_channel_id == 5'hE; // @[Monitor.scala:21:46] wire _GEN_12 = io_in_flit_0_bits_virt_channel_id == 5'hF; // @[Monitor.scala:21:46] wire _GEN_13 = io_in_flit_0_bits_virt_channel_id == 5'h12; // @[Monitor.scala:21:46] wire _GEN_14 = io_in_flit_0_bits_virt_channel_id == 5'h13; // @[Monitor.scala:21:46]

Generate the Verilog code corresponding to the following Chisel files. File Fragmenter.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.diplomacy.{AddressSet, BufferParams, IdRange, TransferSizes} import freechips.rocketchip.util.{Repeater, OH1ToUInt, UIntToOH1} import scala.math.min import freechips.rocketchip.util.DataToAugmentedData object EarlyAck { sealed trait T case object AllPuts extends T case object PutFulls extends T case object None extends T } // minSize: minimum size of transfers supported by all outward managers // maxSize: maximum size of transfers supported after the Fragmenter is applied // alwaysMin: fragment all requests down to minSize (else fragment to maximum supported by manager) // earlyAck: should a multibeat Put should be acknowledged on the first beat or last beat // holdFirstDeny: allow the Fragmenter to unsafely combine multibeat Gets by taking the first denied for the whole burst // nameSuffix: appends a suffix to the module name // Fragmenter modifies: PutFull, PutPartial, LogicalData, Get, Hint // Fragmenter passes: ArithmeticData (truncated to minSize if alwaysMin) // Fragmenter cannot modify acquire (could livelock); thus it is unsafe to put caches on both sides class TLFragmenter(val minSize: Int, val maxSize: Int, val alwaysMin: Boolean = false, val earlyAck: EarlyAck.T = EarlyAck.None, val holdFirstDeny: Boolean = false, val nameSuffix: Option[String] = None)(implicit p: Parameters) extends LazyModule { require(isPow2 (maxSize), s"TLFragmenter expects pow2(maxSize), but got $maxSize") require(isPow2 (minSize), s"TLFragmenter expects pow2(minSize), but got $minSize") require(minSize <= maxSize, s"TLFragmenter expects min <= max, but got $minSize > $maxSize") val fragmentBits = log2Ceil(maxSize / minSize) val fullBits = if (earlyAck == EarlyAck.PutFulls) 1 else 0 val toggleBits = 1 val addedBits = fragmentBits + toggleBits + fullBits def expandTransfer(x: TransferSizes, op: String) = if (!x) x else { // validate that we can apply the fragmenter correctly require (x.max >= minSize, s"TLFragmenter (with parent $parent) max transfer size $op(${x.max}) must be >= min transfer size (${minSize})") TransferSizes(x.min, maxSize) } private def noChangeRequired = minSize == maxSize private def shrinkTransfer(x: TransferSizes) = if (!alwaysMin) x else if (x.min <= minSize) TransferSizes(x.min, min(minSize, x.max)) else TransferSizes.none private def mapManager(m: TLSlaveParameters) = m.v1copy( supportsArithmetic = shrinkTransfer(m.supportsArithmetic), supportsLogical = shrinkTransfer(m.supportsLogical), supportsGet = expandTransfer(m.supportsGet, "Get"), supportsPutFull = expandTransfer(m.supportsPutFull, "PutFull"), supportsPutPartial = expandTransfer(m.supportsPutPartial, "PutParital"), supportsHint = expandTransfer(m.supportsHint, "Hint")) val node = new TLAdapterNode( // We require that all the responses are mutually FIFO // Thus we need to compact all of the masters into one big master clientFn = { c => (if (noChangeRequired) c else c.v2copy( masters = Seq(TLMasterParameters.v2( name = "TLFragmenter", sourceId = IdRange(0, if (minSize == maxSize) c.endSourceId else (c.endSourceId << addedBits)), requestFifo = true, emits = TLMasterToSlaveTransferSizes( acquireT = shrinkTransfer(c.masters.map(_.emits.acquireT) .reduce(_ mincover _)), acquireB = shrinkTransfer(c.masters.map(_.emits.acquireB) .reduce(_ mincover _)), arithmetic = shrinkTransfer(c.masters.map(_.emits.arithmetic).reduce(_ mincover _)), logical = shrinkTransfer(c.masters.map(_.emits.logical) .reduce(_ mincover _)), get = shrinkTransfer(c.masters.map(_.emits.get) .reduce(_ mincover _)), putFull = shrinkTransfer(c.masters.map(_.emits.putFull) .reduce(_ mincover _)), putPartial = shrinkTransfer(c.masters.map(_.emits.putPartial).reduce(_ mincover _)), hint = shrinkTransfer(c.masters.map(_.emits.hint) .reduce(_ mincover _)) ) )) ))}, managerFn = { m => if (noChangeRequired) m else m.v2copy(slaves = m.slaves.map(mapManager)) } ) { override def circuitIdentity = noChangeRequired } lazy val module = new Impl class Impl extends LazyModuleImp(this) { override def desiredName = (Seq("TLFragmenter") ++ nameSuffix).mkString("_") (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => if (noChangeRequired) { out <> in } else { // All managers must share a common FIFO domain (responses might end up interleaved) val manager = edgeOut.manager val managers = manager.managers val beatBytes = manager.beatBytes val fifoId = managers(0).fifoId require (fifoId.isDefined && managers.map(_.fifoId == fifoId).reduce(_ && _)) require (!manager.anySupportAcquireB || !edgeOut.client.anySupportProbe, s"TLFragmenter (with parent $parent) can't fragment a caching client's requests into a cacheable region") require (minSize >= beatBytes, s"TLFragmenter (with parent $parent) can't support fragmenting ($minSize) to sub-beat ($beatBytes) accesses") // We can't support devices which are cached on both sides of us require (!edgeOut.manager.anySupportAcquireB || !edgeIn.client.anySupportProbe) // We can't support denied because we reassemble fragments require (!edgeOut.manager.mayDenyGet || holdFirstDeny, s"TLFragmenter (with parent $parent) can't support denials without holdFirstDeny=true") require (!edgeOut.manager.mayDenyPut || earlyAck == EarlyAck.None) /* The Fragmenter is a bit tricky, because there are 5 sizes in play: * max size -- the maximum transfer size possible * orig size -- the original pre-fragmenter size * frag size -- the modified post-fragmenter size * min size -- the threshold below which frag=orig * beat size -- the amount transfered on any given beat * * The relationships are as follows: * max >= orig >= frag * max > min >= beat * It IS possible that orig <= min (then frag=orig; ie: no fragmentation) * * The fragment# (sent via TL.source) is measured in multiples of min size. * Meanwhile, to track the progress, counters measure in multiples of beat size. * * Here is an example of a bus with max=256, min=8, beat=4 and a device supporting 16. * * in.A out.A (frag#) out.D (frag#) in.D gen# ack# * get64 get16 6 ackD16 6 ackD64 12 15 * ackD16 6 ackD64 14 * ackD16 6 ackD64 13 * ackD16 6 ackD64 12 * get16 4 ackD16 4 ackD64 8 11 * ackD16 4 ackD64 10 * ackD16 4 ackD64 9 * ackD16 4 ackD64 8 * get16 2 ackD16 2 ackD64 4 7 * ackD16 2 ackD64 6 * ackD16 2 ackD64 5 * ackD16 2 ackD64 4 * get16 0 ackD16 0 ackD64 0 3 * ackD16 0 ackD64 2 * ackD16 0 ackD64 1 * ackD16 0 ackD64 0 * * get8 get8 0 ackD8 0 ackD8 0 1 * ackD8 0 ackD8 0 * * get4 get4 0 ackD4 0 ackD4 0 0 * get1 get1 0 ackD1 0 ackD1 0 0 * * put64 put16 6 15 * put64 put16 6 14 * put64 put16 6 13 * put64 put16 6 ack16 6 12 12 * put64 put16 4 11 * put64 put16 4 10 * put64 put16 4 9 * put64 put16 4 ack16 4 8 8 * put64 put16 2 7 * put64 put16 2 6 * put64 put16 2 5 * put64 put16 2 ack16 2 4 4 * put64 put16 0 3 * put64 put16 0 2 * put64 put16 0 1 * put64 put16 0 ack16 0 ack64 0 0 * * put8 put8 0 1 * put8 put8 0 ack8 0 ack8 0 0 * * put4 put4 0 ack4 0 ack4 0 0 * put1 put1 0 ack1 0 ack1 0 0 */ val counterBits = log2Up(maxSize/beatBytes) val maxDownSize = if (alwaysMin) minSize else min(manager.maxTransfer, maxSize) // Consider the following waveform for two 4-beat bursts: // ---A----A------------ // -------D-----DDD-DDDD // Under TL rules, the second A can use the same source as the first A, // because the source is released for reuse on the first response beat. // // However, if we fragment the requests, it looks like this: // ---3210-3210--------- // -------3-----210-3210 // ... now we've broken the rules because 210 are twice inflight. // // This phenomenon means we can have essentially 2*maxSize/minSize-1 // fragmented transactions in flight per original transaction source. // // To keep the source unique, we encode the beat counter in the low // bits of the source. To solve the overlap, we use a toggle bit. // Whatever toggle bit the D is reassembling, A will use the opposite. // First, handle the return path val acknum = RegInit(0.U(counterBits.W)) val dOrig = Reg(UInt()) val dToggle = RegInit(false.B) val dFragnum = out.d.bits.source(fragmentBits-1, 0) val dFirst = acknum === 0.U val dLast = dFragnum === 0.U // only for AccessAck (!Data) val dsizeOH = UIntToOH (out.d.bits.size, log2Ceil(maxDownSize)+1) val dsizeOH1 = UIntToOH1(out.d.bits.size, log2Up(maxDownSize)) val dHasData = edgeOut.hasData(out.d.bits) // calculate new acknum val acknum_fragment = dFragnum << log2Ceil(minSize/beatBytes) val acknum_size = dsizeOH1 >> log2Ceil(beatBytes) assert (!out.d.valid || (acknum_fragment & acknum_size) === 0.U) val dFirst_acknum = acknum_fragment | Mux(dHasData, acknum_size, 0.U) val ack_decrement = Mux(dHasData, 1.U, dsizeOH >> log2Ceil(beatBytes)) // calculate the original size val dFirst_size = OH1ToUInt((dFragnum << log2Ceil(minSize)) | dsizeOH1) when (out.d.fire) { acknum := Mux(dFirst, dFirst_acknum, acknum - ack_decrement) when (dFirst) { dOrig := dFirst_size dToggle := out.d.bits.source(fragmentBits) } } // Swallow up non-data ack fragments val doEarlyAck = earlyAck match { case EarlyAck.AllPuts => true.B case EarlyAck.PutFulls => out.d.bits.source(fragmentBits+1) case EarlyAck.None => false.B } val drop = !dHasData && !Mux(doEarlyAck, dFirst, dLast) out.d.ready := in.d.ready || drop in.d.valid := out.d.valid && !drop in.d.bits := out.d.bits // pass most stuff unchanged in.d.bits.source := out.d.bits.source >> addedBits in.d.bits.size := Mux(dFirst, dFirst_size, dOrig) if (edgeOut.manager.mayDenyPut) { val r_denied = Reg(Bool()) val d_denied = (!dFirst && r_denied) || out.d.bits.denied when (out.d.fire) { r_denied := d_denied } in.d.bits.denied := d_denied } if (edgeOut.manager.mayDenyGet) { // Take denied only from the first beat and hold that value val d_denied = out.d.bits.denied holdUnless dFirst when (dHasData) { in.d.bits.denied := d_denied in.d.bits.corrupt := d_denied || out.d.bits.corrupt } } // What maximum transfer sizes do downstream devices support? val maxArithmetics = managers.map(_.supportsArithmetic.max) val maxLogicals = managers.map(_.supportsLogical.max) val maxGets = managers.map(_.supportsGet.max) val maxPutFulls = managers.map(_.supportsPutFull.max) val maxPutPartials = managers.map(_.supportsPutPartial.max) val maxHints = managers.map(m => if (m.supportsHint) maxDownSize else 0) // We assume that the request is valid => size 0 is impossible val lgMinSize = log2Ceil(minSize).U val maxLgArithmetics = maxArithmetics.map(m => if (m == 0) lgMinSize else log2Ceil(m).U) val maxLgLogicals = maxLogicals .map(m => if (m == 0) lgMinSize else log2Ceil(m).U) val maxLgGets = maxGets .map(m => if (m == 0) lgMinSize else log2Ceil(m).U) val maxLgPutFulls = maxPutFulls .map(m => if (m == 0) lgMinSize else log2Ceil(m).U) val maxLgPutPartials = maxPutPartials.map(m => if (m == 0) lgMinSize else log2Ceil(m).U) val maxLgHints = maxHints .map(m => if (m == 0) lgMinSize else log2Ceil(m).U) // Make the request repeatable val repeater = Module(new Repeater(in.a.bits)) repeater.io.enq <> in.a val in_a = repeater.io.deq // If this is infront of a single manager, these become constants val find = manager.findFast(edgeIn.address(in_a.bits)) val maxLgArithmetic = Mux1H(find, maxLgArithmetics) val maxLgLogical = Mux1H(find, maxLgLogicals) val maxLgGet = Mux1H(find, maxLgGets) val maxLgPutFull = Mux1H(find, maxLgPutFulls) val maxLgPutPartial = Mux1H(find, maxLgPutPartials) val maxLgHint = Mux1H(find, maxLgHints) val limit = if (alwaysMin) lgMinSize else MuxLookup(in_a.bits.opcode, lgMinSize)(Array( TLMessages.PutFullData -> maxLgPutFull, TLMessages.PutPartialData -> maxLgPutPartial, TLMessages.ArithmeticData -> maxLgArithmetic, TLMessages.LogicalData -> maxLgLogical, TLMessages.Get -> maxLgGet, TLMessages.Hint -> maxLgHint)) val aOrig = in_a.bits.size val aFrag = Mux(aOrig > limit, limit, aOrig) val aOrigOH1 = UIntToOH1(aOrig, log2Ceil(maxSize)) val aFragOH1 = UIntToOH1(aFrag, log2Up(maxDownSize)) val aHasData = edgeIn.hasData(in_a.bits) val aMask = Mux(aHasData, 0.U, aFragOH1) val gennum = RegInit(0.U(counterBits.W)) val aFirst = gennum === 0.U val old_gennum1 = Mux(aFirst, aOrigOH1 >> log2Ceil(beatBytes), gennum - 1.U) val new_gennum = ~(~old_gennum1 | (aMask >> log2Ceil(beatBytes))) // ~(~x|y) is width safe val aFragnum = ~(~(old_gennum1 >> log2Ceil(minSize/beatBytes)) | (aFragOH1 >> log2Ceil(minSize))) val aLast = aFragnum === 0.U val aToggle = !Mux(aFirst, dToggle, RegEnable(dToggle, aFirst)) val aFull = if (earlyAck == EarlyAck.PutFulls) Some(in_a.bits.opcode === TLMessages.PutFullData) else None when (out.a.fire) { gennum := new_gennum } repeater.io.repeat := !aHasData && aFragnum =/= 0.U out.a <> in_a out.a.bits.address := in_a.bits.address | ~(old_gennum1 << log2Ceil(beatBytes) | ~aOrigOH1 | aFragOH1 | (minSize-1).U) out.a.bits.source := Cat(Seq(in_a.bits.source) ++ aFull ++ Seq(aToggle.asUInt, aFragnum)) out.a.bits.size := aFrag // Optimize away some of the Repeater's registers assert (!repeater.io.full || !aHasData) out.a.bits.data := in.a.bits.data val fullMask = ((BigInt(1) << beatBytes) - 1).U assert (!repeater.io.full || in_a.bits.mask === fullMask) out.a.bits.mask := Mux(repeater.io.full, fullMask, in.a.bits.mask) out.a.bits.user.waiveAll :<= in.a.bits.user.subset(_.isData) // Tie off unused channels in.b.valid := false.B in.c.ready := true.B in.e.ready := true.B out.b.ready := true.B out.c.valid := false.B out.e.valid := false.B } } } } object TLFragmenter { def apply(minSize: Int, maxSize: Int, alwaysMin: Boolean = false, earlyAck: EarlyAck.T = EarlyAck.None, holdFirstDeny: Boolean = false, nameSuffix: Option[String] = None)(implicit p: Parameters): TLNode = { if (minSize <= maxSize) { val fragmenter = LazyModule(new TLFragmenter(minSize, maxSize, alwaysMin, earlyAck, holdFirstDeny, nameSuffix)) fragmenter.node } else { TLEphemeralNode()(ValName("no_fragmenter")) } } def apply(wrapper: TLBusWrapper, nameSuffix: Option[String])(implicit p: Parameters): TLNode = apply(wrapper.beatBytes, wrapper.blockBytes, nameSuffix = nameSuffix) def apply(wrapper: TLBusWrapper)(implicit p: Parameters): TLNode = apply(wrapper, None) } // Synthesizable unit tests import freechips.rocketchip.unittest._ class TLRAMFragmenter(ramBeatBytes: Int, maxSize: Int, txns: Int)(implicit p: Parameters) extends LazyModule { val fuzz = LazyModule(new TLFuzzer(txns)) val model = LazyModule(new TLRAMModel("Fragmenter")) val ram = LazyModule(new TLRAM(AddressSet(0x0, 0x3ff), beatBytes = ramBeatBytes)) (ram.node := TLDelayer(0.1) := TLBuffer(BufferParams.flow) := TLDelayer(0.1) := TLFragmenter(ramBeatBytes, maxSize, earlyAck = EarlyAck.AllPuts) := TLDelayer(0.1) := TLBuffer(BufferParams.flow) := TLFragmenter(ramBeatBytes, maxSize/2) := TLDelayer(0.1) := TLBuffer(BufferParams.flow) := model.node := fuzz.node) lazy val module = new Impl class Impl extends LazyModuleImp(this) with UnitTestModule { io.finished := fuzz.module.io.finished } } class TLRAMFragmenterTest(ramBeatBytes: Int, maxSize: Int, txns: Int = 5000, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) { val dut = Module(LazyModule(new TLRAMFragmenter(ramBeatBytes,maxSize,txns)).module) io.finished := dut.io.finished dut.io.start := io.start } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /** Like Vec.apply(idx), but tolerates indices of mismatched width */ def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /** Any Data subtype that has a Bool member named valid. */ type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /** converts from camel case to to underscores, also removing all spaces */ def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /** converts spaces or underscores to hyphens, also lowering case */ def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y | (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y || y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /** Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation */ def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Nodes.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.nodes._ import freechips.rocketchip.util.{AsyncQueueParams,RationalDirection} case object TLMonitorBuilder extends Field[TLMonitorArgs => TLMonitorBase](args => new TLMonitor(args)) object TLImp extends NodeImp[TLMasterPortParameters, TLSlavePortParameters, TLEdgeOut, TLEdgeIn, TLBundle] { def edgeO(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeOut(pd, pu, p, sourceInfo) def edgeI(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeIn (pd, pu, p, sourceInfo) def bundleO(eo: TLEdgeOut) = TLBundle(eo.bundle) def bundleI(ei: TLEdgeIn) = TLBundle(ei.bundle) def render(ei: TLEdgeIn) = RenderedEdge(colour = "#000000" /* black */, label = (ei.manager.beatBytes * 8).toString) override def monitor(bundle: TLBundle, edge: TLEdgeIn): Unit = { val monitor = Module(edge.params(TLMonitorBuilder)(TLMonitorArgs(edge))) monitor.io.in := bundle } override def mixO(pd: TLMasterPortParameters, node: OutwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLMasterPortParameters = pd.v1copy(clients = pd.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }) override def mixI(pu: TLSlavePortParameters, node: InwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLSlavePortParameters = pu.v1copy(managers = pu.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }) } trait TLFormatNode extends FormatNode[TLEdgeIn, TLEdgeOut] case class TLClientNode(portParams: Seq[TLMasterPortParameters])(implicit valName: ValName) extends SourceNode(TLImp)(portParams) with TLFormatNode case class TLManagerNode(portParams: Seq[TLSlavePortParameters])(implicit valName: ValName) extends SinkNode(TLImp)(portParams) with TLFormatNode case class TLAdapterNode( clientFn: TLMasterPortParameters => TLMasterPortParameters = { s => s }, managerFn: TLSlavePortParameters => TLSlavePortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLImp)(clientFn, managerFn) with TLFormatNode case class TLJunctionNode( clientFn: Seq[TLMasterPortParameters] => Seq[TLMasterPortParameters], managerFn: Seq[TLSlavePortParameters] => Seq[TLSlavePortParameters])( implicit valName: ValName) extends JunctionNode(TLImp)(clientFn, managerFn) with TLFormatNode case class TLIdentityNode()(implicit valName: ValName) extends IdentityNode(TLImp)() with TLFormatNode object TLNameNode { def apply(name: ValName) = TLIdentityNode()(name) def apply(name: Option[String]): TLIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLIdentityNode = apply(Some(name)) } case class TLEphemeralNode()(implicit valName: ValName) extends EphemeralNode(TLImp)() object TLTempNode { def apply(): TLEphemeralNode = TLEphemeralNode()(ValName("temp")) } case class TLNexusNode( clientFn: Seq[TLMasterPortParameters] => TLMasterPortParameters, managerFn: Seq[TLSlavePortParameters] => TLSlavePortParameters)( implicit valName: ValName) extends NexusNode(TLImp)(clientFn, managerFn) with TLFormatNode abstract class TLCustomNode(implicit valName: ValName) extends CustomNode(TLImp) with TLFormatNode // Asynchronous crossings trait TLAsyncFormatNode extends FormatNode[TLAsyncEdgeParameters, TLAsyncEdgeParameters] object TLAsyncImp extends SimpleNodeImp[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncEdgeParameters, TLAsyncBundle] { def edge(pd: TLAsyncClientPortParameters, pu: TLAsyncManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLAsyncEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLAsyncEdgeParameters) = new TLAsyncBundle(e.bundle) def render(e: TLAsyncEdgeParameters) = RenderedEdge(colour = "#ff0000" /* red */, label = e.manager.async.depth.toString) override def mixO(pd: TLAsyncClientPortParameters, node: OutwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLAsyncManagerPortParameters, node: InwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLAsyncAdapterNode( clientFn: TLAsyncClientPortParameters => TLAsyncClientPortParameters = { s => s }, managerFn: TLAsyncManagerPortParameters => TLAsyncManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLAsyncImp)(clientFn, managerFn) with TLAsyncFormatNode case class TLAsyncIdentityNode()(implicit valName: ValName) extends IdentityNode(TLAsyncImp)() with TLAsyncFormatNode object TLAsyncNameNode { def apply(name: ValName) = TLAsyncIdentityNode()(name) def apply(name: Option[String]): TLAsyncIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLAsyncIdentityNode = apply(Some(name)) } case class TLAsyncSourceNode(sync: Option[Int])(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLAsyncImp)( dFn = { p => TLAsyncClientPortParameters(p) }, uFn = { p => p.base.v1copy(minLatency = p.base.minLatency + sync.getOrElse(p.async.sync)) }) with FormatNode[TLEdgeIn, TLAsyncEdgeParameters] // discard cycles in other clock domain case class TLAsyncSinkNode(async: AsyncQueueParams)(implicit valName: ValName) extends MixedAdapterNode(TLAsyncImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = p.base.minLatency + async.sync) }, uFn = { p => TLAsyncManagerPortParameters(async, p) }) with FormatNode[TLAsyncEdgeParameters, TLEdgeOut] // Rationally related crossings trait TLRationalFormatNode extends FormatNode[TLRationalEdgeParameters, TLRationalEdgeParameters] object TLRationalImp extends SimpleNodeImp[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalEdgeParameters, TLRationalBundle] { def edge(pd: TLRationalClientPortParameters, pu: TLRationalManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLRationalEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLRationalEdgeParameters) = new TLRationalBundle(e.bundle) def render(e: TLRationalEdgeParameters) = RenderedEdge(colour = "#00ff00" /* green */) override def mixO(pd: TLRationalClientPortParameters, node: OutwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLRationalManagerPortParameters, node: InwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLRationalAdapterNode( clientFn: TLRationalClientPortParameters => TLRationalClientPortParameters = { s => s }, managerFn: TLRationalManagerPortParameters => TLRationalManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLRationalImp)(clientFn, managerFn) with TLRationalFormatNode case class TLRationalIdentityNode()(implicit valName: ValName) extends IdentityNode(TLRationalImp)() with TLRationalFormatNode object TLRationalNameNode { def apply(name: ValName) = TLRationalIdentityNode()(name) def apply(name: Option[String]): TLRationalIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLRationalIdentityNode = apply(Some(name)) } case class TLRationalSourceNode()(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLRationalImp)( dFn = { p => TLRationalClientPortParameters(p) }, uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLRationalEdgeParameters] // discard cycles from other clock domain case class TLRationalSinkNode(direction: RationalDirection)(implicit valName: ValName) extends MixedAdapterNode(TLRationalImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = 1) }, uFn = { p => TLRationalManagerPortParameters(direction, p) }) with FormatNode[TLRationalEdgeParameters, TLEdgeOut] // Credited version of TileLink channels trait TLCreditedFormatNode extends FormatNode[TLCreditedEdgeParameters, TLCreditedEdgeParameters] object TLCreditedImp extends SimpleNodeImp[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedEdgeParameters, TLCreditedBundle] { def edge(pd: TLCreditedClientPortParameters, pu: TLCreditedManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLCreditedEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLCreditedEdgeParameters) = new TLCreditedBundle(e.bundle) def render(e: TLCreditedEdgeParameters) = RenderedEdge(colour = "#ffff00" /* yellow */, e.delay.toString) override def mixO(pd: TLCreditedClientPortParameters, node: OutwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLCreditedManagerPortParameters, node: InwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLCreditedAdapterNode( clientFn: TLCreditedClientPortParameters => TLCreditedClientPortParameters = { s => s }, managerFn: TLCreditedManagerPortParameters => TLCreditedManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLCreditedImp)(clientFn, managerFn) with TLCreditedFormatNode case class TLCreditedIdentityNode()(implicit valName: ValName) extends IdentityNode(TLCreditedImp)() with TLCreditedFormatNode object TLCreditedNameNode { def apply(name: ValName) = TLCreditedIdentityNode()(name) def apply(name: Option[String]): TLCreditedIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLCreditedIdentityNode = apply(Some(name)) } case class TLCreditedSourceNode(delay: TLCreditedDelay)(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLCreditedImp)( dFn = { p => TLCreditedClientPortParameters(delay, p) }, uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLCreditedEdgeParameters] // discard cycles from other clock domain case class TLCreditedSinkNode(delay: TLCreditedDelay)(implicit valName: ValName) extends MixedAdapterNode(TLCreditedImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = 1) }, uFn = { p => TLCreditedManagerPortParameters(delay, p) }) with FormatNode[TLCreditedEdgeParameters, TLEdgeOut] File LazyModuleImp.scala: package org.chipsalliance.diplomacy.lazymodule import chisel3.{withClockAndReset, Module, RawModule, Reset, _} import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo} import firrtl.passes.InlineAnnotation import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.nodes.Dangle import scala.collection.immutable.SortedMap /** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]]. * * This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy. */ sealed trait LazyModuleImpLike extends RawModule { /** [[LazyModule]] that contains this instance. */ val wrapper: LazyModule /** IOs that will be automatically "punched" for this instance. */ val auto: AutoBundle /** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */ protected[diplomacy] val dangles: Seq[Dangle] // [[wrapper.module]] had better not be accessed while LazyModules are still being built! require( LazyModule.scope.isEmpty, s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}" ) /** Set module name. Defaults to the containing LazyModule's desiredName. */ override def desiredName: String = wrapper.desiredName suggestName(wrapper.suggestedName) /** [[Parameters]] for chisel [[Module]]s. */ implicit val p: Parameters = wrapper.p /** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and * submodules. */ protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = { // 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]], // 2. return [[Dangle]]s from each module. val childDangles = wrapper.children.reverse.flatMap { c => implicit val sourceInfo: SourceInfo = c.info c.cloneProto.map { cp => // If the child is a clone, then recursively set cloneProto of its children as well def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = { require(bases.size == clones.size) (bases.zip(clones)).map { case (l, r) => require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}") l.cloneProto = Some(r) assignCloneProtos(l.children, r.children) } } assignCloneProtos(c.children, cp.children) // Clone the child module as a record, and get its [[AutoBundle]] val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName) val clonedAuto = clone("auto").asInstanceOf[AutoBundle] // Get the empty [[Dangle]]'s of the cloned child val rawDangles = c.cloneDangles() require(rawDangles.size == clonedAuto.elements.size) // Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) } dangles }.getOrElse { // For non-clones, instantiate the child module val mod = try { Module(c.module) } catch { case e: ChiselException => { println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}") throw e } } mod.dangles } } // Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]]. // This will result in a sequence of [[Dangle]] from these [[BaseNode]]s. val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate()) // Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]] val allDangles = nodeDangles ++ childDangles // Group [[allDangles]] by their [[source]]. val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*) // For each [[source]] set of [[Dangle]]s of size 2, ensure that these // can be connected as a source-sink pair (have opposite flipped value). // Make the connection and mark them as [[done]]. val done = Set() ++ pairing.values.filter(_.size == 2).map { case Seq(a, b) => require(a.flipped != b.flipped) // @todo <> in chisel3 makes directionless connection. if (a.flipped) { a.data <> b.data } else { b.data <> a.data } a.source case _ => None } // Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module. val forward = allDangles.filter(d => !done(d.source)) // Generate [[AutoBundle]] IO from [[forward]]. val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*)) // Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]] val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) => if (d.flipped) { d.data <> io } else { io <> d.data } d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name) } // Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]]. wrapper.inModuleBody.reverse.foreach { _() } if (wrapper.shouldBeInlined) { chisel3.experimental.annotate(new ChiselAnnotation { def toFirrtl = InlineAnnotation(toNamed) }) } // Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]]. (auto, dangles) } } /** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike { /** Instantiate hardware of this `Module`. */ val (auto, dangles) = instantiate() } /** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike { // These wires are the default clock+reset for all LazyModule children. // It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the // [[LazyRawModuleImp]] children. // Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly. /** drive clock explicitly. */ val childClock: Clock = Wire(Clock()) /** drive reset explicitly. */ val childReset: Reset = Wire(Reset()) // the default is that these are disabled childClock := false.B.asClock childReset := chisel3.DontCare def provideImplicitClockToLazyChildren: Boolean = false val (auto, dangles) = if (provideImplicitClockToLazyChildren) { withClockAndReset(childClock, childReset) { instantiate() } } else { instantiate() } }

module TLFragmenter_TileResetSetter( // @[Fragmenter.scala:92:9] input clock, // @[Fragmenter.scala:92:9] input reset, // @[Fragmenter.scala:92:9] output auto_anon_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_anon_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [6:0] auto_anon_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [20:0] auto_anon_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_anon_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input auto_anon_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_anon_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_anon_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [6:0] auto_anon_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output [63:0] auto_anon_in_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_anon_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_anon_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [1:0] auto_anon_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [10:0] auto_anon_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [20:0] auto_anon_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_anon_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output auto_anon_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_anon_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_anon_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_anon_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [10:0] auto_anon_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input [63:0] auto_anon_out_d_bits_data // @[LazyModuleImp.scala:107:25] ); wire _repeater_io_full; // @[Fragmenter.scala:274:30] wire _repeater_io_enq_ready; // @[Fragmenter.scala:274:30] wire _repeater_io_deq_valid; // @[Fragmenter.scala:274:30] wire [2:0] _repeater_io_deq_bits_opcode; // @[Fragmenter.scala:274:30] wire [2:0] _repeater_io_deq_bits_size; // @[Fragmenter.scala:274:30] wire [6:0] _repeater_io_deq_bits_source; // @[Fragmenter.scala:274:30] wire [20:0] _repeater_io_deq_bits_address; // @[Fragmenter.scala:274:30] wire [7:0] _repeater_io_deq_bits_mask; // @[Fragmenter.scala:274:30] reg [2:0] acknum; // @[Fragmenter.scala:201:29] reg [2:0] dOrig; // @[Fragmenter.scala:202:24] reg dToggle; // @[Fragmenter.scala:203:30] wire dFirst = acknum == 3'h0; // @[Fragmenter.scala:201:29, :205:29] wire [5:0] _dsizeOH1_T = 6'h7 << auto_anon_out_d_bits_size; // @[package.scala:243:71] wire [2:0] _GEN = ~(auto_anon_out_d_bits_source[2:0]); // @[package.scala:241:49] wire [2:0] dFirst_size_hi = auto_anon_out_d_bits_source[2:0] & {1'h1, _GEN[2:1]}; // @[OneHot.scala:30:18] wire [2:0] _dFirst_size_T_8 = {1'h0, dFirst_size_hi[2:1]} | ~(_dsizeOH1_T[2:0]) & {_GEN[0], _dsizeOH1_T[2:1]}; // @[OneHot.scala:30:18, :31:18, :32:28] wire [2:0] dFirst_size = {|dFirst_size_hi, |(_dFirst_size_T_8[2:1]), _dFirst_size_T_8[2] | _dFirst_size_T_8[0]}; // @[OneHot.scala:30:18, :31:18, :32:{10,14,28}] wire drop = ~(auto_anon_out_d_bits_opcode[0]) & (|(auto_anon_out_d_bits_source[2:0])); // @[Fragmenter.scala:204:41, :206:30, :234:{20,30}] wire anonOut_d_ready = auto_anon_in_d_ready | drop; // @[Fragmenter.scala:234:30, :235:35] wire anonIn_d_valid = auto_anon_out_d_valid & ~drop; // @[Fragmenter.scala:234:30, :236:{36,39}] wire [2:0] anonIn_d_bits_size = dFirst ? dFirst_size : dOrig; // @[OneHot.scala:32:10] wire [12:0] _aOrigOH1_T = 13'h3F << _repeater_io_deq_bits_size; // @[package.scala:243:71] reg [2:0] gennum; // @[Fragmenter.scala:303:29] wire aFirst = gennum == 3'h0; // @[Fragmenter.scala:303:29, :304:29] wire [2:0] aFragnum = aFirst ? ~(_aOrigOH1_T[5:3]) : gennum - 3'h1; // @[package.scala:243:{46,71,76}] reg aToggle_r; // @[Fragmenter.scala:309:54]

Generate the Verilog code corresponding to the following Chisel files. File ShiftReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ // Similar to the Chisel ShiftRegister but allows the user to suggest a // name to the registers that get instantiated, and // to provide a reset value. object ShiftRegInit { def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T = (0 until n).foldRight(in) { case (i, next) => { val r = RegNext(next, init) name.foreach { na => r.suggestName(s"${na}_${i}") } r } } } /** These wrap behavioral * shift registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * The different types vary in their reset behavior: * AsyncResetShiftReg -- Asynchronously reset register array * A W(width) x D(depth) sized array is constructed from D instantiations of a * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg, * but only used for timing applications */ abstract class AbstractPipelineReg(w: Int = 1) extends Module { val io = IO(new Bundle { val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) } ) } object AbstractPipelineReg { def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = { val chain = Module(gen) name.foreach{ chain.suggestName(_) } chain.io.d := in.asUInt chain.io.q.asTypeOf(in) } } class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) { require(depth > 0, "Depth must be greater than 0.") override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}" val chain = List.tabulate(depth) { i => Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}") } chain.last.io.d := io.d chain.last.io.en := true.B (chain.init zip chain.tail).foreach { case (sink, source) => sink.io.d := source.io.q sink.io.en := true.B } io.q := chain.head.io.q } object AsyncResetShiftReg { def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name) def apply [T <: Data](in: T, depth: Int, name: Option[String]): T = apply(in, depth, 0, name) def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T = apply(in, depth, init.litValue.toInt, name) def apply [T <: Data](in: T, depth: Int, init: T): T = apply (in, depth, init.litValue.toInt, None) } File AsyncQueue.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ case class AsyncQueueParams( depth: Int = 8, sync: Int = 3, safe: Boolean = true, // If safe is true, then effort is made to resynchronize the crossing indices when either side is reset. // This makes it safe/possible to reset one side of the crossing (but not the other) when the queue is empty. narrow: Boolean = false) // If narrow is true then the read mux is moved to the source side of the crossing. // This reduces the number of level shifters in the case where the clock crossing is also a voltage crossing, // at the expense of a combinational path from the sink to the source and back to the sink. { require (depth > 0 && isPow2(depth)) require (sync >= 2) val bits = log2Ceil(depth) val wires = if (narrow) 1 else depth } object AsyncQueueParams { // When there is only one entry, we don't need narrow. def singleton(sync: Int = 3, safe: Boolean = true) = AsyncQueueParams(1, sync, safe, false) } class AsyncBundleSafety extends Bundle { val ridx_valid = Input (Bool()) val widx_valid = Output(Bool()) val source_reset_n = Output(Bool()) val sink_reset_n = Input (Bool()) } class AsyncBundle[T <: Data](private val gen: T, val params: AsyncQueueParams = AsyncQueueParams()) extends Bundle { // Data-path synchronization val mem = Output(Vec(params.wires, gen)) val ridx = Input (UInt((params.bits+1).W)) val widx = Output(UInt((params.bits+1).W)) val index = params.narrow.option(Input(UInt(params.bits.W))) // Signals used to self-stabilize a safe AsyncQueue val safe = params.safe.option(new AsyncBundleSafety) } object GrayCounter { def apply(bits: Int, increment: Bool = true.B, clear: Bool = false.B, name: String = "binary"): UInt = { val incremented = Wire(UInt(bits.W)) val binary = RegNext(next=incremented, init=0.U).suggestName(name) incremented := Mux(clear, 0.U, binary + increment.asUInt) incremented ^ (incremented >> 1) } } class AsyncValidSync(sync: Int, desc: String) extends RawModule { val io = IO(new Bundle { val in = Input(Bool()) val out = Output(Bool()) }) val clock = IO(Input(Clock())) val reset = IO(Input(AsyncReset())) withClockAndReset(clock, reset){ io.out := AsyncResetSynchronizerShiftReg(io.in, sync, Some(desc)) } } class AsyncQueueSource[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module { override def desiredName = s"AsyncQueueSource_${gen.typeName}" val io = IO(new Bundle { // These come from the source domain val enq = Flipped(Decoupled(gen)) // These cross to the sink clock domain val async = new AsyncBundle(gen, params) }) val bits = params.bits val sink_ready = WireInit(true.B) val mem = Reg(Vec(params.depth, gen)) // This does NOT need to be reset at all. val widx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.enq.fire, !sink_ready, "widx_bin")) val ridx = AsyncResetSynchronizerShiftReg(io.async.ridx, params.sync, Some("ridx_gray")) val ready = sink_ready && widx =/= (ridx ^ (params.depth | params.depth >> 1).U) val index = if (bits == 0) 0.U else io.async.widx(bits-1, 0) ^ (io.async.widx(bits, bits) << (bits-1)) when (io.enq.fire) { mem(index) := io.enq.bits } val ready_reg = withReset(reset.asAsyncReset)(RegNext(next=ready, init=false.B).suggestName("ready_reg")) io.enq.ready := ready_reg && sink_ready val widx_reg = withReset(reset.asAsyncReset)(RegNext(next=widx, init=0.U).suggestName("widx_gray")) io.async.widx := widx_reg io.async.index match { case Some(index) => io.async.mem(0) := mem(index) case None => io.async.mem := mem } io.async.safe.foreach { sio => val source_valid_0 = Module(new AsyncValidSync(params.sync, "source_valid_0")) val source_valid_1 = Module(new AsyncValidSync(params.sync, "source_valid_1")) val sink_extend = Module(new AsyncValidSync(params.sync, "sink_extend")) val sink_valid = Module(new AsyncValidSync(params.sync, "sink_valid")) source_valid_0.reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset source_valid_1.reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset sink_extend .reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset sink_valid .reset := reset.asAsyncReset source_valid_0.clock := clock source_valid_1.clock := clock sink_extend .clock := clock sink_valid .clock := clock source_valid_0.io.in := true.B source_valid_1.io.in := source_valid_0.io.out sio.widx_valid := source_valid_1.io.out sink_extend.io.in := sio.ridx_valid sink_valid.io.in := sink_extend.io.out sink_ready := sink_valid.io.out sio.source_reset_n := !reset.asBool // Assert that if there is stuff in the queue, then reset cannot happen // Impossible to write because dequeue can occur on the receiving side, // then reset allowed to happen, but write side cannot know that dequeue // occurred. // TODO: write some sort of sanity check assertion for users // that denote don't reset when there is activity // assert (!(reset || !sio.sink_reset_n) || !io.enq.valid, "Enqueue while sink is reset and AsyncQueueSource is unprotected") // assert (!reset_rise || prev_idx_match.asBool, "Sink reset while AsyncQueueSource not empty") } } class AsyncQueueSink[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module { override def desiredName = s"AsyncQueueSink_${gen.typeName}" val io = IO(new Bundle { // These come from the sink domain val deq = Decoupled(gen) // These cross to the source clock domain val async = Flipped(new AsyncBundle(gen, params)) }) val bits = params.bits val source_ready = WireInit(true.B) val ridx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.deq.fire, !source_ready, "ridx_bin")) val widx = AsyncResetSynchronizerShiftReg(io.async.widx, params.sync, Some("widx_gray")) val valid = source_ready && ridx =/= widx // The mux is safe because timing analysis ensures ridx has reached the register // On an ASIC, changes to the unread location cannot affect the selected value // On an FPGA, only one input changes at a time => mem updates don't cause glitches // The register only latches when the selected valued is not being written val index = if (bits == 0) 0.U else ridx(bits-1, 0) ^ (ridx(bits, bits) << (bits-1)) io.async.index.foreach { _ := index } // This register does not NEED to be reset, as its contents will not // be considered unless the asynchronously reset deq valid register is set. // It is possible that bits latches when the source domain is reset / has power cut // This is safe, because isolation gates brought mem low before the zeroed widx reached us val deq_bits_nxt = io.async.mem(if (params.narrow) 0.U else index) io.deq.bits := ClockCrossingReg(deq_bits_nxt, en = valid, doInit = false, name = Some("deq_bits_reg")) val valid_reg = withReset(reset.asAsyncReset)(RegNext(next=valid, init=false.B).suggestName("valid_reg")) io.deq.valid := valid_reg && source_ready val ridx_reg = withReset(reset.asAsyncReset)(RegNext(next=ridx, init=0.U).suggestName("ridx_gray")) io.async.ridx := ridx_reg io.async.safe.foreach { sio => val sink_valid_0 = Module(new AsyncValidSync(params.sync, "sink_valid_0")) val sink_valid_1 = Module(new AsyncValidSync(params.sync, "sink_valid_1")) val source_extend = Module(new AsyncValidSync(params.sync, "source_extend")) val source_valid = Module(new AsyncValidSync(params.sync, "source_valid")) sink_valid_0 .reset := (reset.asBool || !sio.source_reset_n).asAsyncReset sink_valid_1 .reset := (reset.asBool || !sio.source_reset_n).asAsyncReset source_extend.reset := (reset.asBool || !sio.source_reset_n).asAsyncReset source_valid .reset := reset.asAsyncReset sink_valid_0 .clock := clock sink_valid_1 .clock := clock source_extend.clock := clock source_valid .clock := clock sink_valid_0.io.in := true.B sink_valid_1.io.in := sink_valid_0.io.out sio.ridx_valid := sink_valid_1.io.out source_extend.io.in := sio.widx_valid source_valid.io.in := source_extend.io.out source_ready := source_valid.io.out sio.sink_reset_n := !reset.asBool // TODO: write some sort of sanity check assertion for users // that denote don't reset when there is activity // // val reset_and_extend = !source_ready || !sio.source_reset_n || reset.asBool // val reset_and_extend_prev = RegNext(reset_and_extend, true.B) // val reset_rise = !reset_and_extend_prev && reset_and_extend // val prev_idx_match = AsyncResetReg(updateData=(io.async.widx===io.async.ridx), resetData=0) // assert (!reset_rise || prev_idx_match.asBool, "Source reset while AsyncQueueSink not empty") } } object FromAsyncBundle { // Sometimes it makes sense for the sink to have different sync than the source def apply[T <: Data](x: AsyncBundle[T]): DecoupledIO[T] = apply(x, x.params.sync) def apply[T <: Data](x: AsyncBundle[T], sync: Int): DecoupledIO[T] = { val sink = Module(new AsyncQueueSink(chiselTypeOf(x.mem(0)), x.params.copy(sync = sync))) sink.io.async <> x sink.io.deq } } object ToAsyncBundle { def apply[T <: Data](x: ReadyValidIO[T], params: AsyncQueueParams = AsyncQueueParams()): AsyncBundle[T] = { val source = Module(new AsyncQueueSource(chiselTypeOf(x.bits), params)) source.io.enq <> x source.io.async } } class AsyncQueue[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Crossing[T] { val io = IO(new CrossingIO(gen)) val source = withClockAndReset(io.enq_clock, io.enq_reset) { Module(new AsyncQueueSource(gen, params)) } val sink = withClockAndReset(io.deq_clock, io.deq_reset) { Module(new AsyncQueueSink (gen, params)) } source.io.enq <> io.enq io.deq <> sink.io.deq sink.io.async <> source.io.async }

module AsyncValidSync_28( // @[AsyncQueue.scala:58:7] output io_out, // @[AsyncQueue.scala:59:14] input clock, // @[AsyncQueue.scala:63:17] input reset // @[AsyncQueue.scala:64:17] ); wire io_in = 1'h1; // @[ShiftReg.scala:45:23] wire _io_out_WIRE; // @[ShiftReg.scala:48:24] wire io_out_0; // @[AsyncQueue.scala:58:7] assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24] AsyncResetSynchronizerShiftReg_w1_d3_i0_38 io_out_sink_valid_0 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (reset), .io_q (_io_out_WIRE) ); // @[ShiftReg.scala:45:23] assign io_out = io_out_0; // @[AsyncQueue.scala:58:7] endmodule

Generate the Verilog code corresponding to the following Chisel files. File ShiftReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ // Similar to the Chisel ShiftRegister but allows the user to suggest a // name to the registers that get instantiated, and // to provide a reset value. object ShiftRegInit { def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T = (0 until n).foldRight(in) { case (i, next) => { val r = RegNext(next, init) name.foreach { na => r.suggestName(s"${na}_${i}") } r } } } /** These wrap behavioral * shift registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * The different types vary in their reset behavior: * AsyncResetShiftReg -- Asynchronously reset register array * A W(width) x D(depth) sized array is constructed from D instantiations of a * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg, * but only used for timing applications */ abstract class AbstractPipelineReg(w: Int = 1) extends Module { val io = IO(new Bundle { val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) } ) } object AbstractPipelineReg { def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = { val chain = Module(gen) name.foreach{ chain.suggestName(_) } chain.io.d := in.asUInt chain.io.q.asTypeOf(in) } } class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) { require(depth > 0, "Depth must be greater than 0.") override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}" val chain = List.tabulate(depth) { i => Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}") } chain.last.io.d := io.d chain.last.io.en := true.B (chain.init zip chain.tail).foreach { case (sink, source) => sink.io.d := source.io.q sink.io.en := true.B } io.q := chain.head.io.q } object AsyncResetShiftReg { def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name) def apply [T <: Data](in: T, depth: Int, name: Option[String]): T = apply(in, depth, 0, name) def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T = apply(in, depth, init.litValue.toInt, name) def apply [T <: Data](in: T, depth: Int, init: T): T = apply (in, depth, init.litValue.toInt, None) } File SynchronizerReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util.{RegEnable, Cat} /** These wrap behavioral * shift and next registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * * These are built up of *ResetSynchronizerPrimitiveShiftReg, * intended to be replaced by the integrator's metastable flops chains or replaced * at this level if they have a multi-bit wide synchronizer primitive. * The different types vary in their reset behavior: * NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin * AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep * 1-bit-wide shift registers. * SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg * * [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference. * * ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross * Clock Domains. */ object SynchronizerResetType extends Enumeration { val NonSync, Inferred, Sync, Async = Value } // Note: this should not be used directly. // Use the companion object to generate this with the correct reset type mixin. private class SynchronizerPrimitiveShiftReg( sync: Int, init: Boolean, resetType: SynchronizerResetType.Value) extends AbstractPipelineReg(1) { val initInt = if (init) 1 else 0 val initPostfix = resetType match { case SynchronizerResetType.NonSync => "" case _ => s"_i${initInt}" } override def desiredName = s"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}" val chain = List.tabulate(sync) { i => val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B) reg.suggestName(s"sync_$i") } chain.last := io.d.asBool (chain.init zip chain.tail).foreach { case (sink, source) => sink := source } io.q := chain.head.asUInt } private object SynchronizerPrimitiveShiftReg { def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = { val gen: () => SynchronizerPrimitiveShiftReg = resetType match { case SynchronizerResetType.NonSync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) case SynchronizerResetType.Async => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset case SynchronizerResetType.Sync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset case SynchronizerResetType.Inferred => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) } AbstractPipelineReg(gen(), in) } } // Note: This module may end up with a non-AsyncReset type reset. // But the Primitives within will always have AsyncReset type. class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asAsyncReset){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async) } } io.q := Cat(output.reverse) } object AsyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } // Note: This module may end up with a non-Bool type reset. // But the Primitives within will always have Bool reset type. @deprecated("SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.", "rocket-chip 1.2") class SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asBool){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync) } } io.q := Cat(output.reverse) } object SyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred) } io.q := Cat(output.reverse) } object ResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}" val output = Seq.tabulate(w) { i => SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync) } io.q := Cat(output.reverse) } object SynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, None) def apply [T <: Data](in: T): T = apply (in, 3, None) } class ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module { override def desiredName = s"ClockCrossingReg_w${w}" val io = IO(new Bundle{ val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) val en = Input(Bool()) }) val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en) io.q := cdc_reg } object ClockCrossingReg { def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = { val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit)) name.foreach{ cdc_reg.suggestName(_) } cdc_reg.io.d := in.asUInt cdc_reg.io.en := en cdc_reg.io.q.asTypeOf(in) } }

module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_103( // @[SynchronizerReg.scala:68:19] input clock, // @[SynchronizerReg.scala:68:19] input reset, // @[SynchronizerReg.scala:68:19] output io_q // @[ShiftReg.scala:36:14] ); wire io_d = 1'h1; // @[SynchronizerReg.scala:54:22, :68:19] wire _sync_2_T = 1'h1; // @[SynchronizerReg.scala:54:22, :68:19] wire io_q_0; // @[SynchronizerReg.scala:68:19] reg sync_0; // @[SynchronizerReg.scala:51:87] assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19] reg sync_1; // @[SynchronizerReg.scala:51:87] reg sync_2; // @[SynchronizerReg.scala:51:87] always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19] if (reset) begin // @[SynchronizerReg.scala:68:19] sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87] end else begin // @[SynchronizerReg.scala:68:19] sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87] sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87] sync_2 <= 1'h1; // @[SynchronizerReg.scala:51:87, :54:22, :68:19] end always @(posedge, posedge)

Generate the Verilog code corresponding to the following Chisel files. File SinkC.scala: /* * Copyright 2019 SiFive, Inc. * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You should have received a copy of LICENSE.Apache2 along with * this software. If not, you may obtain a copy at * * https://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ package sifive.blocks.inclusivecache import chisel3._ import chisel3.util._ import freechips.rocketchip.tilelink._ import freechips.rocketchip.util._ class SinkCResponse(params: InclusiveCacheParameters) extends InclusiveCacheBundle(params) { val last = Bool() val set = UInt(params.setBits.W) val tag = UInt(params.tagBits.W) val source = UInt(params.inner.bundle.sourceBits.W) val param = UInt(3.W) val data = Bool() } class PutBufferCEntry(params: InclusiveCacheParameters) extends InclusiveCacheBundle(params) { val data = UInt(params.inner.bundle.dataBits.W) val corrupt = Bool() } class SinkC(params: InclusiveCacheParameters) extends Module { val io = IO(new Bundle { val req = Decoupled(new FullRequest(params)) // Release val resp = Valid(new SinkCResponse(params)) // ProbeAck val c = Flipped(Decoupled(new TLBundleC(params.inner.bundle))) // Find 'way' via MSHR CAM lookup val set = UInt(params.setBits.W) val way = Flipped(UInt(params.wayBits.W)) // ProbeAck write-back val bs_adr = Decoupled(new BankedStoreInnerAddress(params)) val bs_dat = new BankedStoreInnerPoison(params) // SourceD sideband val rel_pop = Flipped(Decoupled(new PutBufferPop(params))) val rel_beat = new PutBufferCEntry(params) }) if (params.firstLevel) { // Tie off unused ports io.req.valid := false.B io.req.bits := DontCare io.resp.valid := false.B io.resp.bits := DontCare io.c.ready := true.B io.set := 0.U io.bs_adr.valid := false.B io.bs_adr.bits := DontCare io.bs_dat := DontCare io.rel_pop.ready := true.B io.rel_beat := DontCare } else { // No restrictions on the type of buffer val c = params.micro.innerBuf.c(io.c) val (tag, set, offset) = params.parseAddress(c.bits.address) val (first, last, _, beat) = params.inner.count(c) val hasData = params.inner.hasData(c.bits) val raw_resp = c.bits.opcode === TLMessages.ProbeAck || c.bits.opcode === TLMessages.ProbeAckData val resp = Mux(c.valid, raw_resp, RegEnable(raw_resp, c.valid)) // Handling of C is broken into two cases: // ProbeAck // if hasData, must be written to BankedStore // if last beat, trigger resp // Release // if first beat, trigger req // if hasData, go to putBuffer // if hasData && first beat, must claim a list assert (!(c.valid && c.bits.corrupt), "Data poisoning unavailable") io.set := Mux(c.valid, set, RegEnable(set, c.valid)) // finds us the way // Cut path from inner C to the BankedStore SRAM setup // ... this makes it easier to layout the L2 data banks far away val bs_adr = Wire(chiselTypeOf(io.bs_adr)) io.bs_adr <> Queue(bs_adr, 1, pipe=true) io.bs_dat.data := RegEnable(c.bits.data, bs_adr.fire) bs_adr.valid := resp && (!first || (c.valid && hasData)) bs_adr.bits.noop := !c.valid bs_adr.bits.way := io.way bs_adr.bits.set := io.set bs_adr.bits.beat := Mux(c.valid, beat, RegEnable(beat + bs_adr.ready.asUInt, c.valid)) bs_adr.bits.mask := ~0.U(params.innerMaskBits.W) params.ccover(bs_adr.valid && !bs_adr.ready, "SINKC_SRAM_STALL", "Data SRAM busy") io.resp.valid := resp && c.valid && (first || last) && (!hasData || bs_adr.ready) io.resp.bits.last := last io.resp.bits.set := set io.resp.bits.tag := tag io.resp.bits.source := c.bits.source io.resp.bits.param := c.bits.param io.resp.bits.data := hasData val putbuffer = Module(new ListBuffer(ListBufferParameters(new PutBufferCEntry(params), params.relLists, params.relBeats, false))) val lists = RegInit(0.U(params.relLists.W)) val lists_set = WireInit(init = 0.U(params.relLists.W)) val lists_clr = WireInit(init = 0.U(params.relLists.W)) lists := (lists | lists_set) & ~lists_clr val free = !lists.andR val freeOH = ~(leftOR(~lists) << 1) & ~lists val freeIdx = OHToUInt(freeOH) val req_block = first && !io.req.ready val buf_block = hasData && !putbuffer.io.push.ready val set_block = hasData && first && !free params.ccover(c.valid && !raw_resp && req_block, "SINKC_REQ_STALL", "No MSHR available to sink request") params.ccover(c.valid && !raw_resp && buf_block, "SINKC_BUF_STALL", "No space in putbuffer for beat") params.ccover(c.valid && !raw_resp && set_block, "SINKC_SET_STALL", "No space in putbuffer for request") c.ready := Mux(raw_resp, !hasData || bs_adr.ready, !req_block && !buf_block && !set_block) io.req.valid := !resp && c.valid && first && !buf_block && !set_block putbuffer.io.push.valid := !resp && c.valid && hasData && !req_block && !set_block when (!resp && c.valid && first && hasData && !req_block && !buf_block) { lists_set := freeOH } val put = Mux(first, freeIdx, RegEnable(freeIdx, first)) io.req.bits.prio := VecInit(4.U(3.W).asBools) io.req.bits.control:= false.B io.req.bits.opcode := c.bits.opcode io.req.bits.param := c.bits.param io.req.bits.size := c.bits.size io.req.bits.source := c.bits.source io.req.bits.offset := offset io.req.bits.set := set io.req.bits.tag := tag io.req.bits.put := put putbuffer.io.push.bits.index := put putbuffer.io.push.bits.data.data := c.bits.data putbuffer.io.push.bits.data.corrupt := c.bits.corrupt // Grant access to pop the data putbuffer.io.pop.bits := io.rel_pop.bits.index putbuffer.io.pop.valid := io.rel_pop.fire io.rel_pop.ready := putbuffer.io.valid(io.rel_pop.bits.index(log2Ceil(params.relLists)-1,0)) io.rel_beat := putbuffer.io.data when (io.rel_pop.fire && io.rel_pop.bits.last) { lists_clr := UIntToOH(io.rel_pop.bits.index, params.relLists) } } } File Parameters.scala: /* * Copyright 2019 SiFive, Inc. * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You should have received a copy of LICENSE.Apache2 along with * this software. If not, you may obtain a copy at * * https://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ package sifive.blocks.inclusivecache import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config._ import freechips.rocketchip.diplomacy._ import freechips.rocketchip.tilelink._ import freechips.rocketchip.util._ import freechips.rocketchip.util.property.cover import scala.math.{min,max} case class CacheParameters( level: Int, ways: Int, sets: Int, blockBytes: Int, beatBytes: Int, // inner hintsSkipProbe: Boolean) { require (ways > 0) require (sets > 0) require (blockBytes > 0 && isPow2(blockBytes)) require (beatBytes > 0 && isPow2(beatBytes)) require (blockBytes >= beatBytes) val blocks = ways * sets val sizeBytes = blocks * blockBytes val blockBeats = blockBytes/beatBytes } case class InclusiveCachePortParameters( a: BufferParams, b: BufferParams, c: BufferParams, d: BufferParams, e: BufferParams) { def apply()(implicit p: Parameters, valName: ValName) = LazyModule(new TLBuffer(a, b, c, d, e)) } object InclusiveCachePortParameters { val none = InclusiveCachePortParameters( a = BufferParams.none, b = BufferParams.none, c = BufferParams.none, d = BufferParams.none, e = BufferParams.none) val full = InclusiveCachePortParameters( a = BufferParams.default, b = BufferParams.default, c = BufferParams.default, d = BufferParams.default, e = BufferParams.default) // This removes feed-through paths from C=>A and A=>C val fullC = InclusiveCachePortParameters( a = BufferParams.none, b = BufferParams.none, c = BufferParams.default, d = BufferParams.none, e = BufferParams.none) val flowAD = InclusiveCachePortParameters( a = BufferParams.flow, b = BufferParams.none, c = BufferParams.none, d = BufferParams.flow, e = BufferParams.none) val flowAE = InclusiveCachePortParameters( a = BufferParams.flow, b = BufferParams.none, c = BufferParams.none, d = BufferParams.none, e = BufferParams.flow) // For innerBuf: // SinkA: no restrictions, flows into scheduler+putbuffer // SourceB: no restrictions, flows out of scheduler // sinkC: no restrictions, flows into scheduler+putbuffer & buffered to bankedStore // SourceD: no restrictions, flows out of bankedStore/regout // SinkE: no restrictions, flows into scheduler // // ... so while none is possible, you probably want at least flowAC to cut ready // from the scheduler delay and flowD to ease SourceD back-pressure // For outerBufer: // SourceA: must not be pipe, flows out of scheduler // SinkB: no restrictions, flows into scheduler // SourceC: pipe is useless, flows out of bankedStore/regout, parameter depth ignored // SinkD: no restrictions, flows into scheduler & bankedStore // SourceE: must not be pipe, flows out of scheduler // // ... AE take the channel ready into the scheduler, so you need at least flowAE } case class InclusiveCacheMicroParameters( writeBytes: Int, // backing store update granularity memCycles: Int = 40, // # of L2 clock cycles for a memory round-trip (50ns @ 800MHz) portFactor: Int = 4, // numSubBanks = (widest TL port * portFactor) / writeBytes dirReg: Boolean = false, innerBuf: InclusiveCachePortParameters = InclusiveCachePortParameters.fullC, // or none outerBuf: InclusiveCachePortParameters = InclusiveCachePortParameters.full) // or flowAE { require (writeBytes > 0 && isPow2(writeBytes)) require (memCycles > 0) require (portFactor >= 2) // for inner RMW and concurrent outer Relase + Grant } case class InclusiveCacheControlParameters( address: BigInt, beatBytes: Int, bankedControl: Boolean) case class InclusiveCacheParameters( cache: CacheParameters, micro: InclusiveCacheMicroParameters, control: Boolean, inner: TLEdgeIn, outer: TLEdgeOut)(implicit val p: Parameters) { require (cache.ways > 1) require (cache.sets > 1 && isPow2(cache.sets)) require (micro.writeBytes <= inner.manager.beatBytes) require (micro.writeBytes <= outer.manager.beatBytes) require (inner.manager.beatBytes <= cache.blockBytes) require (outer.manager.beatBytes <= cache.blockBytes) // Require that all cached address ranges have contiguous blocks outer.manager.managers.flatMap(_.address).foreach { a => require (a.alignment >= cache.blockBytes) } // If we are the first level cache, we do not need to support inner-BCE val firstLevel = !inner.client.clients.exists(_.supports.probe) // If we are the last level cache, we do not need to support outer-B val lastLevel = !outer.manager.managers.exists(_.regionType > RegionType.UNCACHED) require (lastLevel) // Provision enough resources to achieve full throughput with missing single-beat accesses val mshrs = InclusiveCacheParameters.all_mshrs(cache, micro) val secondary = max(mshrs, micro.memCycles - mshrs) val putLists = micro.memCycles // allow every request to be single beat val putBeats = max(2*cache.blockBeats, micro.memCycles) val relLists = 2 val relBeats = relLists*cache.blockBeats val flatAddresses = AddressSet.unify(outer.manager.managers.flatMap(_.address)) val pickMask = AddressDecoder(flatAddresses.map(Seq(_)), flatAddresses.map(_.mask).reduce(_|_)) def bitOffsets(x: BigInt, offset: Int = 0, tail: List[Int] = List.empty[Int]): List[Int] = if (x == 0) tail.reverse else bitOffsets(x >> 1, offset + 1, if ((x & 1) == 1) offset :: tail else tail) val addressMapping = bitOffsets(pickMask) val addressBits = addressMapping.size // println(s"addresses: ${flatAddresses} => ${pickMask} => ${addressBits}") val allClients = inner.client.clients.size val clientBitsRaw = inner.client.clients.filter(_.supports.probe).size val clientBits = max(1, clientBitsRaw) val stateBits = 2 val wayBits = log2Ceil(cache.ways) val setBits = log2Ceil(cache.sets) val offsetBits = log2Ceil(cache.blockBytes) val tagBits = addressBits - setBits - offsetBits val putBits = log2Ceil(max(putLists, relLists)) require (tagBits > 0) require (offsetBits > 0) val innerBeatBits = (offsetBits - log2Ceil(inner.manager.beatBytes)) max 1 val outerBeatBits = (offsetBits - log2Ceil(outer.manager.beatBytes)) max 1 val innerMaskBits = inner.manager.beatBytes / micro.writeBytes val outerMaskBits = outer.manager.beatBytes / micro.writeBytes def clientBit(source: UInt): UInt = { if (clientBitsRaw == 0) { 0.U } else { Cat(inner.client.clients.filter(_.supports.probe).map(_.sourceId.contains(source)).reverse) } } def clientSource(bit: UInt): UInt = { if (clientBitsRaw == 0) { 0.U } else { Mux1H(bit, inner.client.clients.filter(_.supports.probe).map(c => c.sourceId.start.U)) } } def parseAddress(x: UInt): (UInt, UInt, UInt) = { val offset = Cat(addressMapping.map(o => x(o,o)).reverse) val set = offset >> offsetBits val tag = set >> setBits (tag(tagBits-1, 0), set(setBits-1, 0), offset(offsetBits-1, 0)) } def widen(x: UInt, width: Int): UInt = { val y = x | 0.U(width.W) assert (y >> width === 0.U) y(width-1, 0) } def expandAddress(tag: UInt, set: UInt, offset: UInt): UInt = { val base = Cat(widen(tag, tagBits), widen(set, setBits), widen(offset, offsetBits)) val bits = Array.fill(outer.bundle.addressBits) { 0.U(1.W) } addressMapping.zipWithIndex.foreach { case (a, i) => bits(a) = base(i,i) } Cat(bits.reverse) } def restoreAddress(expanded: UInt): UInt = { val missingBits = flatAddresses .map { a => (a.widen(pickMask).base, a.widen(~pickMask)) } // key is the bits to restore on match .groupBy(_._1) .view .mapValues(_.map(_._2)) val muxMask = AddressDecoder(missingBits.values.toList) val mux = missingBits.toList.map { case (bits, addrs) => val widen = addrs.map(_.widen(~muxMask)) val matches = AddressSet .unify(widen.distinct) .map(_.contains(expanded)) .reduce(_ || _) (matches, bits.U) } expanded | Mux1H(mux) } def dirReg[T <: Data](x: T, en: Bool = true.B): T = { if (micro.dirReg) RegEnable(x, en) else x } def ccover(cond: Bool, label: String, desc: String)(implicit sourceInfo: SourceInfo) = cover(cond, "CCACHE_L" + cache.level + "_" + label, "MemorySystem;;" + desc) } object MetaData { val stateBits = 2 def INVALID: UInt = 0.U(stateBits.W) // way is empty def BRANCH: UInt = 1.U(stateBits.W) // outer slave cache is trunk def TRUNK: UInt = 2.U(stateBits.W) // unique inner master cache is trunk def TIP: UInt = 3.U(stateBits.W) // we are trunk, inner masters are branch // Does a request need trunk? def needT(opcode: UInt, param: UInt): Bool = { !opcode(2) || (opcode === TLMessages.Hint && param === TLHints.PREFETCH_WRITE) || ((opcode === TLMessages.AcquireBlock || opcode === TLMessages.AcquirePerm) && param =/= TLPermissions.NtoB) } // Does a request prove the client need not be probed? def skipProbeN(opcode: UInt, hintsSkipProbe: Boolean): Bool = { // Acquire(toB) and Get => is N, so no probe // Acquire(*toT) => is N or B, but need T, so no probe // Hint => could be anything, so probe IS needed, if hintsSkipProbe is enabled, skip probe the same client // Put* => is N or B, so probe IS needed opcode === TLMessages.AcquireBlock || opcode === TLMessages.AcquirePerm || opcode === TLMessages.Get || (opcode === TLMessages.Hint && hintsSkipProbe.B) } def isToN(param: UInt): Bool = { param === TLPermissions.TtoN || param === TLPermissions.BtoN || param === TLPermissions.NtoN } def isToB(param: UInt): Bool = { param === TLPermissions.TtoB || param === TLPermissions.BtoB } } object InclusiveCacheParameters { val lfsrBits = 10 val L2ControlAddress = 0x2010000 val L2ControlSize = 0x1000 def out_mshrs(cache: CacheParameters, micro: InclusiveCacheMicroParameters): Int = { // We need 2-3 normal MSHRs to cover the Directory latency // To fully exploit memory bandwidth-delay-product, we need memCyles/blockBeats MSHRs max(if (micro.dirReg) 3 else 2, (micro.memCycles + cache.blockBeats - 1) / cache.blockBeats) } def all_mshrs(cache: CacheParameters, micro: InclusiveCacheMicroParameters): Int = // We need a dedicated MSHR for B+C each 2 + out_mshrs(cache, micro) } class InclusiveCacheBundle(params: InclusiveCacheParameters) extends Bundle File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) || !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.ProbeAckData || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode | small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U || beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }

module SinkC( // @[SinkC.scala:41:7] input clock, // @[SinkC.scala:41:7] input reset, // @[SinkC.scala:41:7] input io_req_ready, // @[SinkC.scala:43:14] output io_req_valid, // @[SinkC.scala:43:14] output [2:0] io_req_bits_opcode, // @[SinkC.scala:43:14] output [2:0] io_req_bits_param, // @[SinkC.scala:43:14] output [2:0] io_req_bits_size, // @[SinkC.scala:43:14] output [7:0] io_req_bits_source, // @[SinkC.scala:43:14] output [12:0] io_req_bits_tag, // @[SinkC.scala:43:14] output [5:0] io_req_bits_offset, // @[SinkC.scala:43:14] output [5:0] io_req_bits_put, // @[SinkC.scala:43:14] output [9:0] io_req_bits_set, // @[SinkC.scala:43:14] output io_resp_valid, // @[SinkC.scala:43:14] output io_resp_bits_last, // @[SinkC.scala:43:14] output [9:0] io_resp_bits_set, // @[SinkC.scala:43:14] output [12:0] io_resp_bits_tag, // @[SinkC.scala:43:14] output [7:0] io_resp_bits_source, // @[SinkC.scala:43:14] output [2:0] io_resp_bits_param, // @[SinkC.scala:43:14] output io_resp_bits_data, // @[SinkC.scala:43:14] output io_c_ready, // @[SinkC.scala:43:14] input io_c_valid, // @[SinkC.scala:43:14] input [2:0] io_c_bits_opcode, // @[SinkC.scala:43:14] input [2:0] io_c_bits_param, // @[SinkC.scala:43:14] input [2:0] io_c_bits_size, // @[SinkC.scala:43:14] input [7:0] io_c_bits_source, // @[SinkC.scala:43:14] input [31:0] io_c_bits_address, // @[SinkC.scala:43:14] input [127:0] io_c_bits_data, // @[SinkC.scala:43:14] input io_c_bits_corrupt, // @[SinkC.scala:43:14] output [9:0] io_set, // @[SinkC.scala:43:14] input [2:0] io_way, // @[SinkC.scala:43:14] input io_bs_adr_ready, // @[SinkC.scala:43:14] output io_bs_adr_valid, // @[SinkC.scala:43:14] output io_bs_adr_bits_noop, // @[SinkC.scala:43:14] output [2:0] io_bs_adr_bits_way, // @[SinkC.scala:43:14] output [9:0] io_bs_adr_bits_set, // @[SinkC.scala:43:14] output [1:0] io_bs_adr_bits_beat, // @[SinkC.scala:43:14] output [1:0] io_bs_adr_bits_mask, // @[SinkC.scala:43:14] output [127:0] io_bs_dat_data, // @[SinkC.scala:43:14] output io_rel_pop_ready, // @[SinkC.scala:43:14] input io_rel_pop_valid, // @[SinkC.scala:43:14] input [5:0] io_rel_pop_bits_index, // @[SinkC.scala:43:14] input io_rel_pop_bits_last, // @[SinkC.scala:43:14] output [127:0] io_rel_beat_data, // @[SinkC.scala:43:14] output io_rel_beat_corrupt // @[SinkC.scala:43:14] ); wire [9:0] io_set_0; // @[SinkC.scala:41:7] wire _putbuffer_io_push_ready; // @[SinkC.scala:115:27] wire [1:0] _putbuffer_io_valid; // @[SinkC.scala:115:27] wire _c_q_io_deq_valid; // @[Decoupled.scala:362:21] wire [2:0] _c_q_io_deq_bits_opcode; // @[Decoupled.scala:362:21] wire [2:0] _c_q_io_deq_bits_param; // @[Decoupled.scala:362:21] wire [2:0] _c_q_io_deq_bits_size; // @[Decoupled.scala:362:21] wire [7:0] _c_q_io_deq_bits_source; // @[Decoupled.scala:362:21] wire [31:0] _c_q_io_deq_bits_address; // @[Decoupled.scala:362:21] wire [127:0] _c_q_io_deq_bits_data; // @[Decoupled.scala:362:21] wire _c_q_io_deq_bits_corrupt; // @[Decoupled.scala:362:21] wire io_req_ready_0 = io_req_ready; // @[SinkC.scala:41:7] wire io_c_valid_0 = io_c_valid; // @[SinkC.scala:41:7] wire [2:0] io_c_bits_opcode_0 = io_c_bits_opcode; // @[SinkC.scala:41:7] wire [2:0] io_c_bits_param_0 = io_c_bits_param; // @[SinkC.scala:41:7] wire [2:0] io_c_bits_size_0 = io_c_bits_size; // @[SinkC.scala:41:7] wire [7:0] io_c_bits_source_0 = io_c_bits_source; // @[SinkC.scala:41:7] wire [31:0] io_c_bits_address_0 = io_c_bits_address; // @[SinkC.scala:41:7] wire [127:0] io_c_bits_data_0 = io_c_bits_data; // @[SinkC.scala:41:7] wire io_c_bits_corrupt_0 = io_c_bits_corrupt; // @[SinkC.scala:41:7] wire [2:0] io_way_0 = io_way; // @[SinkC.scala:41:7] wire io_bs_adr_ready_0 = io_bs_adr_ready; // @[SinkC.scala:41:7] wire io_rel_pop_valid_0 = io_rel_pop_valid; // @[SinkC.scala:41:7] wire [5:0] io_rel_pop_bits_index_0 = io_rel_pop_bits_index; // @[SinkC.scala:41:7] wire io_rel_pop_bits_last_0 = io_rel_pop_bits_last; // @[SinkC.scala:41:7] wire io_req_bits_prio_0 = 1'h0; // @[SinkC.scala:41:7] wire io_req_bits_prio_1 = 1'h0; // @[SinkC.scala:41:7] wire io_req_bits_control = 1'h0; // @[SinkC.scala:41:7] wire io_req_bits_prio_2 = 1'h1; // @[SinkC.scala:41:7] wire [1:0] bs_adr_bits_mask = 2'h3; // @[SinkC.scala:96:22] wire [1:0] _bs_adr_bits_mask_T = 2'h3; // @[SinkC.scala:104:25] wire _io_req_valid_T_6; // @[SinkC.scala:136:61] wire [12:0] tag_1; // @[Parameters.scala:217:9] wire [5:0] offset_1; // @[Parameters.scala:217:50] wire [9:0] set_1; // @[Parameters.scala:217:28] wire _io_resp_valid_T_5; // @[SinkC.scala:107:57] wire last; // @[Edges.scala:232:33] wire hasData; // @[Edges.scala:102:36] wire [9:0] _io_set_T; // @[SinkC.scala:92:18] wire [9:0] bs_adr_bits_set = io_set_0; // @[SinkC.scala:41:7, :96:22] wire [2:0] bs_adr_bits_way = io_way_0; // @[SinkC.scala:41:7, :96:22] wire _io_rel_pop_ready_T_2; // @[SinkC.scala:160:43] wire [2:0] io_req_bits_opcode_0; // @[SinkC.scala:41:7] wire [2:0] io_req_bits_param_0; // @[SinkC.scala:41:7] wire [2:0] io_req_bits_size_0; // @[SinkC.scala:41:7] wire [7:0] io_req_bits_source_0; // @[SinkC.scala:41:7] wire [12:0] io_req_bits_tag_0; // @[SinkC.scala:41:7] wire [5:0] io_req_bits_offset_0; // @[SinkC.scala:41:7] wire [5:0] io_req_bits_put_0; // @[SinkC.scala:41:7] wire [9:0] io_req_bits_set_0; // @[SinkC.scala:41:7] wire io_req_valid_0; // @[SinkC.scala:41:7] wire io_resp_bits_last_0; // @[SinkC.scala:41:7] wire [9:0] io_resp_bits_set_0; // @[SinkC.scala:41:7] wire [12:0] io_resp_bits_tag_0; // @[SinkC.scala:41:7] wire [7:0] io_resp_bits_source_0; // @[SinkC.scala:41:7] wire [2:0] io_resp_bits_param_0; // @[SinkC.scala:41:7] wire io_resp_bits_data_0; // @[SinkC.scala:41:7] wire io_resp_valid_0; // @[SinkC.scala:41:7] wire io_c_ready_0; // @[SinkC.scala:41:7] wire io_bs_adr_bits_noop_0; // @[SinkC.scala:41:7] wire [2:0] io_bs_adr_bits_way_0; // @[SinkC.scala:41:7] wire [9:0] io_bs_adr_bits_set_0; // @[SinkC.scala:41:7] wire [1:0] io_bs_adr_bits_beat_0; // @[SinkC.scala:41:7] wire [1:0] io_bs_adr_bits_mask_0; // @[SinkC.scala:41:7] wire io_bs_adr_valid_0; // @[SinkC.scala:41:7] wire [127:0] io_bs_dat_data_0; // @[SinkC.scala:41:7] wire io_rel_pop_ready_0; // @[SinkC.scala:41:7] wire [127:0] io_rel_beat_data_0; // @[SinkC.scala:41:7] wire io_rel_beat_corrupt_0; // @[SinkC.scala:41:7] wire _offset_T = _c_q_io_deq_bits_address[0]; // @[Decoupled.scala:362:21] wire _offset_T_1 = _c_q_io_deq_bits_address[1]; // @[Decoupled.scala:362:21] wire _offset_T_2 = _c_q_io_deq_bits_address[2]; // @[Decoupled.scala:362:21] wire _offset_T_3 = _c_q_io_deq_bits_address[3]; // @[Decoupled.scala:362:21] wire _offset_T_4 = _c_q_io_deq_bits_address[4]; // @[Decoupled.scala:362:21] wire _offset_T_5 = _c_q_io_deq_bits_address[5]; // @[Decoupled.scala:362:21] wire _offset_T_6 = _c_q_io_deq_bits_address[6]; // @[Decoupled.scala:362:21] wire _offset_T_7 = _c_q_io_deq_bits_address[7]; // @[Decoupled.scala:362:21] wire _offset_T_8 = _c_q_io_deq_bits_address[8]; // @[Decoupled.scala:362:21] wire _offset_T_9 = _c_q_io_deq_bits_address[9]; // @[Decoupled.scala:362:21] wire _offset_T_10 = _c_q_io_deq_bits_address[10]; // @[Decoupled.scala:362:21] wire _offset_T_11 = _c_q_io_deq_bits_address[11]; // @[Decoupled.scala:362:21] wire _offset_T_12 = _c_q_io_deq_bits_address[12]; // @[Decoupled.scala:362:21] wire _offset_T_13 = _c_q_io_deq_bits_address[13]; // @[Decoupled.scala:362:21] wire _offset_T_14 = _c_q_io_deq_bits_address[14]; // @[Decoupled.scala:362:21] wire _offset_T_15 = _c_q_io_deq_bits_address[15]; // @[Decoupled.scala:362:21] wire _offset_T_16 = _c_q_io_deq_bits_address[16]; // @[Decoupled.scala:362:21] wire _offset_T_17 = _c_q_io_deq_bits_address[17]; // @[Decoupled.scala:362:21] wire _offset_T_18 = _c_q_io_deq_bits_address[18]; // @[Decoupled.scala:362:21] wire _offset_T_19 = _c_q_io_deq_bits_address[19]; // @[Decoupled.scala:362:21] wire _offset_T_20 = _c_q_io_deq_bits_address[20]; // @[Decoupled.scala:362:21] wire _offset_T_21 = _c_q_io_deq_bits_address[21]; // @[Decoupled.scala:362:21] wire _offset_T_22 = _c_q_io_deq_bits_address[22]; // @[Decoupled.scala:362:21] wire _offset_T_23 = _c_q_io_deq_bits_address[23]; // @[Decoupled.scala:362:21] wire _offset_T_24 = _c_q_io_deq_bits_address[24]; // @[Decoupled.scala:362:21] wire _offset_T_25 = _c_q_io_deq_bits_address[25]; // @[Decoupled.scala:362:21] wire _offset_T_26 = _c_q_io_deq_bits_address[26]; // @[Decoupled.scala:362:21] wire _offset_T_27 = _c_q_io_deq_bits_address[27]; // @[Decoupled.scala:362:21] wire _offset_T_28 = _c_q_io_deq_bits_address[31]; // @[Decoupled.scala:362:21] wire [1:0] offset_lo_lo_lo_hi = {_offset_T_2, _offset_T_1}; // @[Parameters.scala:214:{21,47}] wire [2:0] offset_lo_lo_lo = {offset_lo_lo_lo_hi, _offset_T}; // @[Parameters.scala:214:{21,47}] wire [1:0] offset_lo_lo_hi_lo = {_offset_T_4, _offset_T_3}; // @[Parameters.scala:214:{21,47}] wire [1:0] offset_lo_lo_hi_hi = {_offset_T_6, _offset_T_5}; // @[Parameters.scala:214:{21,47}] wire [3:0] offset_lo_lo_hi = {offset_lo_lo_hi_hi, offset_lo_lo_hi_lo}; // @[Parameters.scala:214:21] wire [6:0] offset_lo_lo = {offset_lo_lo_hi, offset_lo_lo_lo}; // @[Parameters.scala:214:21] wire [1:0] offset_lo_hi_lo_hi = {_offset_T_9, _offset_T_8}; // @[Parameters.scala:214:{21,47}] wire [2:0] offset_lo_hi_lo = {offset_lo_hi_lo_hi, _offset_T_7}; // @[Parameters.scala:214:{21,47}] wire [1:0] offset_lo_hi_hi_lo = {_offset_T_11, _offset_T_10}; // @[Parameters.scala:214:{21,47}] wire [1:0] offset_lo_hi_hi_hi = {_offset_T_13, _offset_T_12}; // @[Parameters.scala:214:{21,47}] wire [3:0] offset_lo_hi_hi = {offset_lo_hi_hi_hi, offset_lo_hi_hi_lo}; // @[Parameters.scala:214:21] wire [6:0] offset_lo_hi = {offset_lo_hi_hi, offset_lo_hi_lo}; // @[Parameters.scala:214:21] wire [13:0] offset_lo = {offset_lo_hi, offset_lo_lo}; // @[Parameters.scala:214:21] wire [1:0] offset_hi_lo_lo_hi = {_offset_T_16, _offset_T_15}; // @[Parameters.scala:214:{21,47}] wire [2:0] offset_hi_lo_lo = {offset_hi_lo_lo_hi, _offset_T_14}; // @[Parameters.scala:214:{21,47}] wire [1:0] offset_hi_lo_hi_lo = {_offset_T_18, _offset_T_17}; // @[Parameters.scala:214:{21,47}] wire [1:0] offset_hi_lo_hi_hi = {_offset_T_20, _offset_T_19}; // @[Parameters.scala:214:{21,47}] wire [3:0] offset_hi_lo_hi = {offset_hi_lo_hi_hi, offset_hi_lo_hi_lo}; // @[Parameters.scala:214:21] wire [6:0] offset_hi_lo = {offset_hi_lo_hi, offset_hi_lo_lo}; // @[Parameters.scala:214:21] wire [1:0] offset_hi_hi_lo_lo = {_offset_T_22, _offset_T_21}; // @[Parameters.scala:214:{21,47}] wire [1:0] offset_hi_hi_lo_hi = {_offset_T_24, _offset_T_23}; // @[Parameters.scala:214:{21,47}] wire [3:0] offset_hi_hi_lo = {offset_hi_hi_lo_hi, offset_hi_hi_lo_lo}; // @[Parameters.scala:214:21] wire [1:0] offset_hi_hi_hi_lo = {_offset_T_26, _offset_T_25}; // @[Parameters.scala:214:{21,47}] wire [1:0] offset_hi_hi_hi_hi = {_offset_T_28, _offset_T_27}; // @[Parameters.scala:214:{21,47}] wire [3:0] offset_hi_hi_hi = {offset_hi_hi_hi_hi, offset_hi_hi_hi_lo}; // @[Parameters.scala:214:21] wire [7:0] offset_hi_hi = {offset_hi_hi_hi, offset_hi_hi_lo}; // @[Parameters.scala:214:21] wire [14:0] offset_hi = {offset_hi_hi, offset_hi_lo}; // @[Parameters.scala:214:21] wire [28:0] offset = {offset_hi, offset_lo}; // @[Parameters.scala:214:21] wire [22:0] set = offset[28:6]; // @[Parameters.scala:214:21, :215:22] wire [12:0] tag = set[22:10]; // @[Parameters.scala:215:22, :216:19] assign tag_1 = tag; // @[Parameters.scala:216:19, :217:9] assign io_req_bits_tag_0 = tag_1; // @[SinkC.scala:41:7] assign io_resp_bits_tag_0 = tag_1; // @[SinkC.scala:41:7] assign set_1 = set[9:0]; // @[Parameters.scala:215:22, :217:28] assign io_req_bits_set_0 = set_1; // @[SinkC.scala:41:7] assign io_resp_bits_set_0 = set_1; // @[SinkC.scala:41:7] assign offset_1 = offset[5:0]; // @[Parameters.scala:214:21, :217:50] assign io_req_bits_offset_0 = offset_1; // @[SinkC.scala:41:7] wire _q_io_deq_ready_T_7; // @[SinkC.scala:134:19] wire _T = _q_io_deq_ready_T_7 & _c_q_io_deq_valid; // @[Decoupled.scala:51:35, :362:21] wire [12:0] _r_beats1_decode_T = 13'h3F << _c_q_io_deq_bits_size; // @[Decoupled.scala:362:21] wire [5:0] _r_beats1_decode_T_1 = _r_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _r_beats1_decode_T_2 = ~_r_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [1:0] r_beats1_decode = _r_beats1_decode_T_2[5:4]; // @[package.scala:243:46] wire r_beats1_opdata = _c_q_io_deq_bits_opcode[0]; // @[Decoupled.scala:362:21] assign hasData = _c_q_io_deq_bits_opcode[0]; // @[Decoupled.scala:362:21] wire [1:0] r_beats1 = r_beats1_opdata ? r_beats1_decode : 2'h0; // @[Edges.scala:102:36, :220:59, :221:14] reg [1:0] r_counter; // @[Edges.scala:229:27] wire [2:0] _r_counter1_T = {1'h0, r_counter} - 3'h1; // @[Edges.scala:229:27, :230:28] wire [1:0] r_counter1 = _r_counter1_T[1:0]; // @[Edges.scala:230:28] wire first = r_counter == 2'h0; // @[Edges.scala:229:27, :231:25] wire _r_last_T = r_counter == 2'h1; // @[Edges.scala:229:27, :232:25] wire _r_last_T_1 = r_beats1 == 2'h0; // @[Edges.scala:221:14, :232:43] assign last = _r_last_T | _r_last_T_1; // @[Edges.scala:232:{25,33,43}] assign io_resp_bits_last_0 = last; // @[Edges.scala:232:33] wire r_3 = last & _T; // @[Decoupled.scala:51:35] wire [1:0] _r_count_T = ~r_counter1; // @[Edges.scala:230:28, :234:27] wire [1:0] beat = r_beats1 & _r_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [1:0] _r_counter_T = first ? r_beats1 : r_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] assign io_resp_bits_data_0 = hasData; // @[Edges.scala:102:36] wire _raw_resp_T = _c_q_io_deq_bits_opcode == 3'h4; // @[Decoupled.scala:362:21] wire _raw_resp_T_1 = _c_q_io_deq_bits_opcode == 3'h5; // @[Decoupled.scala:362:21] wire raw_resp = _raw_resp_T | _raw_resp_T_1; // @[SinkC.scala:78:{34,58,75}] reg resp_r; // @[SinkC.scala:79:48] wire resp = _c_q_io_deq_valid ? raw_resp : resp_r; // @[Decoupled.scala:362:21]

Generate the Verilog code corresponding to the following Chisel files. File DescribedSRAM.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3.{Data, SyncReadMem, Vec} import chisel3.util.log2Ceil object DescribedSRAM { def apply[T <: Data]( name: String, desc: String, size: BigInt, // depth data: T ): SyncReadMem[T] = { val mem = SyncReadMem(size, data) mem.suggestName(name) val granWidth = data match { case v: Vec[_] => v.head.getWidth case d => d.getWidth } val uid = 0 Annotated.srams( component = mem, name = name, address_width = log2Ceil(size), data_width = data.getWidth, depth = size, description = desc, write_mask_granularity = granWidth ) mem } }

module rerocc_tile_dcache_tag_array_3( // @[DescribedSRAM.scala:17:26] input [1:0] RW0_addr, input RW0_en, input RW0_clk, input RW0_wmode, input [103:0] RW0_wdata, output [103:0] RW0_rdata, input [3:0] RW0_wmask ); rerocc_tile_dcache_tag_array_ext rerocc_tile_dcache_tag_array_ext ( // @[DescribedSRAM.scala:17:26] .RW0_addr (RW0_addr), .RW0_en (RW0_en), .RW0_clk (RW0_clk), .RW0_wmode (RW0_wmode), .RW0_wdata (RW0_wdata), .RW0_rdata (RW0_rdata), .RW0_wmask (RW0_wmask) ); // @[DescribedSRAM.scala:17:26] endmodule

Generate the Verilog code corresponding to the following Chisel files. File Tile.scala: // See README.md for license details. package gemmini import chisel3._ import chisel3.util._ import Util._ /** * A Tile is a purely combinational 2D array of passThrough PEs. * a, b, s, and in_propag are broadcast across the entire array and are passed through to the Tile's outputs * @param width The data width of each PE in bits * @param rows Number of PEs on each row * @param columns Number of PEs on each column */ class Tile[T <: Data](inputType: T, outputType: T, accType: T, df: Dataflow.Value, tree_reduction: Boolean, max_simultaneous_matmuls: Int, val rows: Int, val columns: Int)(implicit ev: Arithmetic[T]) extends Module { val io = IO(new Bundle { val in_a = Input(Vec(rows, inputType)) val in_b = Input(Vec(columns, outputType)) // This is the output of the tile next to it val in_d = Input(Vec(columns, outputType)) val in_control = Input(Vec(columns, new PEControl(accType))) val in_id = Input(Vec(columns, UInt(log2Up(max_simultaneous_matmuls).W))) val in_last = Input(Vec(columns, Bool())) val out_a = Output(Vec(rows, inputType)) val out_c = Output(Vec(columns, outputType)) val out_b = Output(Vec(columns, outputType)) val out_control = Output(Vec(columns, new PEControl(accType))) val out_id = Output(Vec(columns, UInt(log2Up(max_simultaneous_matmuls).W))) val out_last = Output(Vec(columns, Bool())) val in_valid = Input(Vec(columns, Bool())) val out_valid = Output(Vec(columns, Bool())) val bad_dataflow = Output(Bool()) }) import ev._ val tile = Seq.fill(rows, columns)(Module(new PE(inputType, outputType, accType, df, max_simultaneous_matmuls))) val tileT = tile.transpose // TODO: abstract hori/vert broadcast, all these connections look the same // Broadcast 'a' horizontally across the Tile for (r <- 0 until rows) { tile(r).foldLeft(io.in_a(r)) { case (in_a, pe) => pe.io.in_a := in_a pe.io.out_a } } // Broadcast 'b' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_b(c)) { case (in_b, pe) => pe.io.in_b := (if (tree_reduction) in_b.zero else in_b) pe.io.out_b } } // Broadcast 'd' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_d(c)) { case (in_d, pe) => pe.io.in_d := in_d pe.io.out_c } } // Broadcast 'control' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_control(c)) { case (in_ctrl, pe) => pe.io.in_control := in_ctrl pe.io.out_control } } // Broadcast 'garbage' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_valid(c)) { case (v, pe) => pe.io.in_valid := v pe.io.out_valid } } // Broadcast 'id' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_id(c)) { case (id, pe) => pe.io.in_id := id pe.io.out_id } } // Broadcast 'last' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_last(c)) { case (last, pe) => pe.io.in_last := last pe.io.out_last } } // Drive the Tile's bottom IO for (c <- 0 until columns) { io.out_c(c) := tile(rows-1)(c).io.out_c io.out_control(c) := tile(rows-1)(c).io.out_control io.out_id(c) := tile(rows-1)(c).io.out_id io.out_last(c) := tile(rows-1)(c).io.out_last io.out_valid(c) := tile(rows-1)(c).io.out_valid io.out_b(c) := { if (tree_reduction) { val prods = tileT(c).map(_.io.out_b) accumulateTree(prods :+ io.in_b(c)) } else { tile(rows - 1)(c).io.out_b } } } io.bad_dataflow := tile.map(_.map(_.io.bad_dataflow).reduce(_||_)).reduce(_||_) // Drive the Tile's right IO for (r <- 0 until rows) { io.out_a(r) := tile(r)(columns-1).io.out_a } }

module Tile_55( // @[Tile.scala:16:7] input clock, // @[Tile.scala:16:7] input reset, // @[Tile.scala:16:7] input [7:0] io_in_a_0, // @[Tile.scala:17:14] input [19:0] io_in_b_0, // @[Tile.scala:17:14] input [19:0] io_in_d_0, // @[Tile.scala:17:14] input io_in_control_0_dataflow, // @[Tile.scala:17:14] input io_in_control_0_propagate, // @[Tile.scala:17:14] input [4:0] io_in_control_0_shift, // @[Tile.scala:17:14] input [2:0] io_in_id_0, // @[Tile.scala:17:14] input io_in_last_0, // @[Tile.scala:17:14] output [7:0] io_out_a_0, // @[Tile.scala:17:14] output [19:0] io_out_c_0, // @[Tile.scala:17:14] output [19:0] io_out_b_0, // @[Tile.scala:17:14] output io_out_control_0_dataflow, // @[Tile.scala:17:14] output io_out_control_0_propagate, // @[Tile.scala:17:14] output [4:0] io_out_control_0_shift, // @[Tile.scala:17:14] output [2:0] io_out_id_0, // @[Tile.scala:17:14] output io_out_last_0, // @[Tile.scala:17:14] input io_in_valid_0, // @[Tile.scala:17:14] output io_out_valid_0, // @[Tile.scala:17:14] output io_bad_dataflow // @[Tile.scala:17:14] ); wire [7:0] io_in_a_0_0 = io_in_a_0; // @[Tile.scala:16:7] wire [19:0] io_in_b_0_0 = io_in_b_0; // @[Tile.scala:16:7] wire [19:0] io_in_d_0_0 = io_in_d_0; // @[Tile.scala:16:7] wire io_in_control_0_dataflow_0 = io_in_control_0_dataflow; // @[Tile.scala:16:7] wire io_in_control_0_propagate_0 = io_in_control_0_propagate; // @[Tile.scala:16:7] wire [4:0] io_in_control_0_shift_0 = io_in_control_0_shift; // @[Tile.scala:16:7] wire [2:0] io_in_id_0_0 = io_in_id_0; // @[Tile.scala:16:7] wire io_in_last_0_0 = io_in_last_0; // @[Tile.scala:16:7] wire io_in_valid_0_0 = io_in_valid_0; // @[Tile.scala:16:7] wire [7:0] io_out_a_0_0; // @[Tile.scala:16:7] wire [19:0] io_out_c_0_0; // @[Tile.scala:16:7] wire [19:0] io_out_b_0_0; // @[Tile.scala:16:7] wire io_out_control_0_dataflow_0; // @[Tile.scala:16:7] wire io_out_control_0_propagate_0; // @[Tile.scala:16:7] wire [4:0] io_out_control_0_shift_0; // @[Tile.scala:16:7] wire [2:0] io_out_id_0_0; // @[Tile.scala:16:7] wire io_out_last_0_0; // @[Tile.scala:16:7] wire io_out_valid_0_0; // @[Tile.scala:16:7] wire io_bad_dataflow_0; // @[Tile.scala:16:7] PE_311 tile_0_0 ( // @[Tile.scala:42:44] .clock (clock), .reset (reset), .io_in_a (io_in_a_0_0), // @[Tile.scala:16:7] .io_in_b (io_in_b_0_0), // @[Tile.scala:16:7] .io_in_d (io_in_d_0_0), // @[Tile.scala:16:7] .io_out_a (io_out_a_0_0), .io_out_b (io_out_b_0_0), .io_out_c (io_out_c_0_0), .io_in_control_dataflow (io_in_control_0_dataflow_0), // @[Tile.scala:16:7] .io_in_control_propagate (io_in_control_0_propagate_0), // @[Tile.scala:16:7] .io_in_control_shift (io_in_control_0_shift_0), // @[Tile.scala:16:7] .io_out_control_dataflow (io_out_control_0_dataflow_0), .io_out_control_propagate (io_out_control_0_propagate_0), .io_out_control_shift (io_out_control_0_shift_0), .io_in_id (io_in_id_0_0), // @[Tile.scala:16:7] .io_out_id (io_out_id_0_0), .io_in_last (io_in_last_0_0), // @[Tile.scala:16:7] .io_out_last (io_out_last_0_0), .io_in_valid (io_in_valid_0_0), // @[Tile.scala:16:7] .io_out_valid (io_out_valid_0_0), .io_bad_dataflow (io_bad_dataflow_0) ); // @[Tile.scala:42:44] assign io_out_a_0 = io_out_a_0_0; // @[Tile.scala:16:7] assign io_out_c_0 = io_out_c_0_0; // @[Tile.scala:16:7] assign io_out_b_0 = io_out_b_0_0; // @[Tile.scala:16:7] assign io_out_control_0_dataflow = io_out_control_0_dataflow_0; // @[Tile.scala:16:7] assign io_out_control_0_propagate = io_out_control_0_propagate_0; // @[Tile.scala:16:7] assign io_out_control_0_shift = io_out_control_0_shift_0; // @[Tile.scala:16:7] assign io_out_id_0 = io_out_id_0_0; // @[Tile.scala:16:7] assign io_out_last_0 = io_out_last_0_0; // @[Tile.scala:16:7] assign io_out_valid_0 = io_out_valid_0_0; // @[Tile.scala:16:7] assign io_bad_dataflow = io_bad_dataflow_0; // @[Tile.scala:16:7] endmodule

Generate the Verilog code corresponding to the following Chisel files. File ShiftReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ // Similar to the Chisel ShiftRegister but allows the user to suggest a // name to the registers that get instantiated, and // to provide a reset value. object ShiftRegInit { def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T = (0 until n).foldRight(in) { case (i, next) => { val r = RegNext(next, init) name.foreach { na => r.suggestName(s"${na}_${i}") } r } } } /** These wrap behavioral * shift registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * The different types vary in their reset behavior: * AsyncResetShiftReg -- Asynchronously reset register array * A W(width) x D(depth) sized array is constructed from D instantiations of a * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg, * but only used for timing applications */ abstract class AbstractPipelineReg(w: Int = 1) extends Module { val io = IO(new Bundle { val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) } ) } object AbstractPipelineReg { def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = { val chain = Module(gen) name.foreach{ chain.suggestName(_) } chain.io.d := in.asUInt chain.io.q.asTypeOf(in) } } class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) { require(depth > 0, "Depth must be greater than 0.") override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}" val chain = List.tabulate(depth) { i => Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}") } chain.last.io.d := io.d chain.last.io.en := true.B (chain.init zip chain.tail).foreach { case (sink, source) => sink.io.d := source.io.q sink.io.en := true.B } io.q := chain.head.io.q } object AsyncResetShiftReg { def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name) def apply [T <: Data](in: T, depth: Int, name: Option[String]): T = apply(in, depth, 0, name) def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T = apply(in, depth, init.litValue.toInt, name) def apply [T <: Data](in: T, depth: Int, init: T): T = apply (in, depth, init.litValue.toInt, None) } File SynchronizerReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util.{RegEnable, Cat} /** These wrap behavioral * shift and next registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * * These are built up of *ResetSynchronizerPrimitiveShiftReg, * intended to be replaced by the integrator's metastable flops chains or replaced * at this level if they have a multi-bit wide synchronizer primitive. * The different types vary in their reset behavior: * NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin * AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep * 1-bit-wide shift registers. * SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg * * [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference. * * ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross * Clock Domains. */ object SynchronizerResetType extends Enumeration { val NonSync, Inferred, Sync, Async = Value } // Note: this should not be used directly. // Use the companion object to generate this with the correct reset type mixin. private class SynchronizerPrimitiveShiftReg( sync: Int, init: Boolean, resetType: SynchronizerResetType.Value) extends AbstractPipelineReg(1) { val initInt = if (init) 1 else 0 val initPostfix = resetType match { case SynchronizerResetType.NonSync => "" case _ => s"_i${initInt}" } override def desiredName = s"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}" val chain = List.tabulate(sync) { i => val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B) reg.suggestName(s"sync_$i") } chain.last := io.d.asBool (chain.init zip chain.tail).foreach { case (sink, source) => sink := source } io.q := chain.head.asUInt } private object SynchronizerPrimitiveShiftReg { def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = { val gen: () => SynchronizerPrimitiveShiftReg = resetType match { case SynchronizerResetType.NonSync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) case SynchronizerResetType.Async => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset case SynchronizerResetType.Sync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset case SynchronizerResetType.Inferred => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) } AbstractPipelineReg(gen(), in) } } // Note: This module may end up with a non-AsyncReset type reset. // But the Primitives within will always have AsyncReset type. class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asAsyncReset){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async) } } io.q := Cat(output.reverse) } object AsyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } // Note: This module may end up with a non-Bool type reset. // But the Primitives within will always have Bool reset type. @deprecated("SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.", "rocket-chip 1.2") class SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asBool){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync) } } io.q := Cat(output.reverse) } object SyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred) } io.q := Cat(output.reverse) } object ResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}" val output = Seq.tabulate(w) { i => SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync) } io.q := Cat(output.reverse) } object SynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, None) def apply [T <: Data](in: T): T = apply (in, 3, None) } class ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module { override def desiredName = s"ClockCrossingReg_w${w}" val io = IO(new Bundle{ val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) val en = Input(Bool()) }) val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en) io.q := cdc_reg } object ClockCrossingReg { def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = { val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit)) name.foreach{ cdc_reg.suggestName(_) } cdc_reg.io.d := in.asUInt cdc_reg.io.en := en cdc_reg.io.q.asTypeOf(in) } }

module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_265( // @[SynchronizerReg.scala:68:19] input clock, // @[SynchronizerReg.scala:68:19] input reset, // @[SynchronizerReg.scala:68:19] input io_d, // @[ShiftReg.scala:36:14] output io_q // @[ShiftReg.scala:36:14] ); wire io_d_0 = io_d; // @[SynchronizerReg.scala:68:19] wire _sync_2_T = io_d_0; // @[SynchronizerReg.scala:54:22, :68:19] wire io_q_0; // @[SynchronizerReg.scala:68:19] reg sync_0; // @[SynchronizerReg.scala:51:87] assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19] reg sync_1; // @[SynchronizerReg.scala:51:87] reg sync_2; // @[SynchronizerReg.scala:51:87] always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19] if (reset) begin // @[SynchronizerReg.scala:68:19] sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87] end else begin // @[SynchronizerReg.scala:68:19] sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87] sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87] sync_2 <= _sync_2_T; // @[SynchronizerReg.scala:51:87, :54:22] end always @(posedge, posedge)

Generate the Verilog code corresponding to the following Chisel files. File PE.scala: // See README.md for license details. package gemmini import chisel3._ import chisel3.util._ class PEControl[T <: Data : Arithmetic](accType: T) extends Bundle { val dataflow = UInt(1.W) // TODO make this an Enum val propagate = UInt(1.W) // Which register should be propagated (and which should be accumulated)? val shift = UInt(log2Up(accType.getWidth).W) // TODO this isn't correct for Floats } class MacUnit[T <: Data](inputType: T, cType: T, dType: T) (implicit ev: Arithmetic[T]) extends Module { import ev._ val io = IO(new Bundle { val in_a = Input(inputType) val in_b = Input(inputType) val in_c = Input(cType) val out_d = Output(dType) }) io.out_d := io.in_c.mac(io.in_a, io.in_b) } // TODO update documentation /** * A PE implementing a MAC operation. Configured as fully combinational when integrated into a Mesh. * @param width Data width of operands */ class PE[T <: Data](inputType: T, outputType: T, accType: T, df: Dataflow.Value, max_simultaneous_matmuls: Int) (implicit ev: Arithmetic[T]) extends Module { // Debugging variables import ev._ val io = IO(new Bundle { val in_a = Input(inputType) val in_b = Input(outputType) val in_d = Input(outputType) val out_a = Output(inputType) val out_b = Output(outputType) val out_c = Output(outputType) val in_control = Input(new PEControl(accType)) val out_control = Output(new PEControl(accType)) val in_id = Input(UInt(log2Up(max_simultaneous_matmuls).W)) val out_id = Output(UInt(log2Up(max_simultaneous_matmuls).W)) val in_last = Input(Bool()) val out_last = Output(Bool()) val in_valid = Input(Bool()) val out_valid = Output(Bool()) val bad_dataflow = Output(Bool()) }) val cType = if (df == Dataflow.WS) inputType else accType // When creating PEs that support multiple dataflows, the // elaboration/synthesis tools often fail to consolidate and de-duplicate // MAC units. To force mac circuitry to be re-used, we create a "mac_unit" // module here which just performs a single MAC operation val mac_unit = Module(new MacUnit(inputType, if (df == Dataflow.WS) outputType else accType, outputType)) val a = io.in_a val b = io.in_b val d = io.in_d val c1 = Reg(cType) val c2 = Reg(cType) val dataflow = io.in_control.dataflow val prop = io.in_control.propagate val shift = io.in_control.shift val id = io.in_id val last = io.in_last val valid = io.in_valid io.out_a := a io.out_control.dataflow := dataflow io.out_control.propagate := prop io.out_control.shift := shift io.out_id := id io.out_last := last io.out_valid := valid mac_unit.io.in_a := a val last_s = RegEnable(prop, valid) val flip = last_s =/= prop val shift_offset = Mux(flip, shift, 0.U) // Which dataflow are we using? val OUTPUT_STATIONARY = Dataflow.OS.id.U(1.W) val WEIGHT_STATIONARY = Dataflow.WS.id.U(1.W) // Is c1 being computed on, or propagated forward (in the output-stationary dataflow)? val COMPUTE = 0.U(1.W) val PROPAGATE = 1.U(1.W) io.bad_dataflow := false.B when ((df == Dataflow.OS).B || ((df == Dataflow.BOTH).B && dataflow === OUTPUT_STATIONARY)) { when(prop === PROPAGATE) { io.out_c := (c1 >> shift_offset).clippedToWidthOf(outputType) io.out_b := b mac_unit.io.in_b := b.asTypeOf(inputType) mac_unit.io.in_c := c2 c2 := mac_unit.io.out_d c1 := d.withWidthOf(cType) }.otherwise { io.out_c := (c2 >> shift_offset).clippedToWidthOf(outputType) io.out_b := b mac_unit.io.in_b := b.asTypeOf(inputType) mac_unit.io.in_c := c1 c1 := mac_unit.io.out_d c2 := d.withWidthOf(cType) } }.elsewhen ((df == Dataflow.WS).B || ((df == Dataflow.BOTH).B && dataflow === WEIGHT_STATIONARY)) { when(prop === PROPAGATE) { io.out_c := c1 mac_unit.io.in_b := c2.asTypeOf(inputType) mac_unit.io.in_c := b io.out_b := mac_unit.io.out_d c1 := d }.otherwise { io.out_c := c2 mac_unit.io.in_b := c1.asTypeOf(inputType) mac_unit.io.in_c := b io.out_b := mac_unit.io.out_d c2 := d } }.otherwise { io.bad_dataflow := true.B //assert(false.B, "unknown dataflow") io.out_c := DontCare io.out_b := DontCare mac_unit.io.in_b := b.asTypeOf(inputType) mac_unit.io.in_c := c2 } when (!valid) { c1 := c1 c2 := c2 mac_unit.io.in_b := DontCare mac_unit.io.in_c := DontCare } } File Arithmetic.scala: // A simple type class for Chisel datatypes that can add and multiply. To add your own type, simply create your own: // implicit MyTypeArithmetic extends Arithmetic[MyType] { ... } package gemmini import chisel3._ import chisel3.util._ import hardfloat._ // Bundles that represent the raw bits of custom datatypes case class Float(expWidth: Int, sigWidth: Int) extends Bundle { val bits = UInt((expWidth + sigWidth).W) val bias: Int = (1 << (expWidth-1)) - 1 } case class DummySInt(w: Int) extends Bundle { val bits = UInt(w.W) def dontCare: DummySInt = { val o = Wire(new DummySInt(w)) o.bits := 0.U o } } // The Arithmetic typeclass which implements various arithmetic operations on custom datatypes abstract class Arithmetic[T <: Data] { implicit def cast(t: T): ArithmeticOps[T] } abstract class ArithmeticOps[T <: Data](self: T) { def *(t: T): T def mac(m1: T, m2: T): T // Returns (m1 * m2 + self) def +(t: T): T def -(t: T): T def >>(u: UInt): T // This is a rounding shift! Rounds away from 0 def >(t: T): Bool def identity: T def withWidthOf(t: T): T def clippedToWidthOf(t: T): T // Like "withWidthOf", except that it saturates def relu: T def zero: T def minimum: T // Optional parameters, which only need to be defined if you want to enable various optimizations for transformers def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[T])] = None def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[T])] = None def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = None def mult_with_reciprocal[U <: Data](reciprocal: U) = self } object Arithmetic { implicit object UIntArithmetic extends Arithmetic[UInt] { override implicit def cast(self: UInt) = new ArithmeticOps(self) { override def *(t: UInt) = self * t override def mac(m1: UInt, m2: UInt) = m1 * m2 + self override def +(t: UInt) = self + t override def -(t: UInt) = self - t override def >>(u: UInt) = { // The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm // TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here? val point_five = Mux(u === 0.U, 0.U, self(u - 1.U)) val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U val ones_digit = self(u) val r = point_five & (zeros | ones_digit) (self >> u).asUInt + r } override def >(t: UInt): Bool = self > t override def withWidthOf(t: UInt) = self.asTypeOf(t) override def clippedToWidthOf(t: UInt) = { val sat = ((1 << (t.getWidth-1))-1).U Mux(self > sat, sat, self)(t.getWidth-1, 0) } override def relu: UInt = self override def zero: UInt = 0.U override def identity: UInt = 1.U override def minimum: UInt = 0.U } } implicit object SIntArithmetic extends Arithmetic[SInt] { override implicit def cast(self: SInt) = new ArithmeticOps(self) { override def *(t: SInt) = self * t override def mac(m1: SInt, m2: SInt) = m1 * m2 + self override def +(t: SInt) = self + t override def -(t: SInt) = self - t override def >>(u: UInt) = { // The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm // TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here? val point_five = Mux(u === 0.U, 0.U, self(u - 1.U)) val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U val ones_digit = self(u) val r = (point_five & (zeros | ones_digit)).asBool (self >> u).asSInt + Mux(r, 1.S, 0.S) } override def >(t: SInt): Bool = self > t override def withWidthOf(t: SInt) = { if (self.getWidth >= t.getWidth) self(t.getWidth-1, 0).asSInt else { val sign_bits = t.getWidth - self.getWidth val sign = self(self.getWidth-1) Cat(Cat(Seq.fill(sign_bits)(sign)), self).asTypeOf(t) } } override def clippedToWidthOf(t: SInt): SInt = { val maxsat = ((1 << (t.getWidth-1))-1).S val minsat = (-(1 << (t.getWidth-1))).S MuxCase(self, Seq((self > maxsat) -> maxsat, (self < minsat) -> minsat))(t.getWidth-1, 0).asSInt } override def relu: SInt = Mux(self >= 0.S, self, 0.S) override def zero: SInt = 0.S override def identity: SInt = 1.S override def minimum: SInt = (-(1 << (self.getWidth-1))).S override def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = { // TODO this uses a floating point divider, but we should use an integer divider instead val input = Wire(Decoupled(denom_t.cloneType)) val output = Wire(Decoupled(self.cloneType)) // We translate our integer to floating-point form so that we can use the hardfloat divider val expWidth = log2Up(self.getWidth) + 1 val sigWidth = self.getWidth def sin_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def uin_to_float(x: UInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := false.B in_to_rec_fn.io.in := x in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def float_to_in(x: UInt) = { val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth)) rec_fn_to_in.io.signedOut := true.B rec_fn_to_in.io.in := x rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag rec_fn_to_in.io.out.asSInt } val self_rec = sin_to_float(self) val denom_rec = uin_to_float(input.bits) // Instantiate the hardloat divider val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options)) input.ready := divider.io.inReady divider.io.inValid := input.valid divider.io.sqrtOp := false.B divider.io.a := self_rec divider.io.b := denom_rec divider.io.roundingMode := consts.round_minMag divider.io.detectTininess := consts.tininess_afterRounding output.valid := divider.io.outValid_div output.bits := float_to_in(divider.io.out) assert(!output.valid || output.ready) Some((input, output)) } override def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = { // TODO this uses a floating point divider, but we should use an integer divider instead val input = Wire(Decoupled(UInt(0.W))) val output = Wire(Decoupled(self.cloneType)) input.bits := DontCare // We translate our integer to floating-point form so that we can use the hardfloat divider val expWidth = log2Up(self.getWidth) + 1 val sigWidth = self.getWidth def in_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def float_to_in(x: UInt) = { val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth)) rec_fn_to_in.io.signedOut := true.B rec_fn_to_in.io.in := x rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag rec_fn_to_in.io.out.asSInt } val self_rec = in_to_float(self) // Instantiate the hardloat sqrt val sqrter = Module(new DivSqrtRecFN_small(expWidth, sigWidth, 0)) input.ready := sqrter.io.inReady sqrter.io.inValid := input.valid sqrter.io.sqrtOp := true.B sqrter.io.a := self_rec sqrter.io.b := DontCare sqrter.io.roundingMode := consts.round_minMag sqrter.io.detectTininess := consts.tininess_afterRounding output.valid := sqrter.io.outValid_sqrt output.bits := float_to_in(sqrter.io.out) assert(!output.valid || output.ready) Some((input, output)) } override def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = u match { case Float(expWidth, sigWidth) => val input = Wire(Decoupled(UInt(0.W))) val output = Wire(Decoupled(u.cloneType)) input.bits := DontCare // We translate our integer to floating-point form so that we can use the hardfloat divider def in_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } val self_rec = in_to_float(self) val one_rec = in_to_float(1.S) // Instantiate the hardloat divider val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options)) input.ready := divider.io.inReady divider.io.inValid := input.valid divider.io.sqrtOp := false.B divider.io.a := one_rec divider.io.b := self_rec divider.io.roundingMode := consts.round_near_even divider.io.detectTininess := consts.tininess_afterRounding output.valid := divider.io.outValid_div output.bits := fNFromRecFN(expWidth, sigWidth, divider.io.out).asTypeOf(u) assert(!output.valid || output.ready) Some((input, output)) case _ => None } override def mult_with_reciprocal[U <: Data](reciprocal: U): SInt = reciprocal match { case recip @ Float(expWidth, sigWidth) => def in_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def float_to_in(x: UInt) = { val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth)) rec_fn_to_in.io.signedOut := true.B rec_fn_to_in.io.in := x rec_fn_to_in.io.roundingMode := consts.round_minMag rec_fn_to_in.io.out.asSInt } val self_rec = in_to_float(self) val reciprocal_rec = recFNFromFN(expWidth, sigWidth, recip.bits) // Instantiate the hardloat divider val muladder = Module(new MulRecFN(expWidth, sigWidth)) muladder.io.roundingMode := consts.round_near_even muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := self_rec muladder.io.b := reciprocal_rec float_to_in(muladder.io.out) case _ => self } } } implicit object FloatArithmetic extends Arithmetic[Float] { // TODO Floating point arithmetic currently switches between recoded and standard formats for every operation. However, it should stay in the recoded format as it travels through the systolic array override implicit def cast(self: Float): ArithmeticOps[Float] = new ArithmeticOps(self) { override def *(t: Float): Float = { val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth)) t_resizer.io.in := t_rec t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag t_resizer.io.detectTininess := consts.tininess_afterRounding val t_rec_resized = t_resizer.io.out val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth)) muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := self_rec muladder.io.b := t_rec_resized val out = Wire(Float(self.expWidth, self.sigWidth)) out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) out } override def mac(m1: Float, m2: Float): Float = { // Recode all operands val m1_rec = recFNFromFN(m1.expWidth, m1.sigWidth, m1.bits) val m2_rec = recFNFromFN(m2.expWidth, m2.sigWidth, m2.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Resize m1 to self's width val m1_resizer = Module(new RecFNToRecFN(m1.expWidth, m1.sigWidth, self.expWidth, self.sigWidth)) m1_resizer.io.in := m1_rec m1_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag m1_resizer.io.detectTininess := consts.tininess_afterRounding val m1_rec_resized = m1_resizer.io.out // Resize m2 to self's width val m2_resizer = Module(new RecFNToRecFN(m2.expWidth, m2.sigWidth, self.expWidth, self.sigWidth)) m2_resizer.io.in := m2_rec m2_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag m2_resizer.io.detectTininess := consts.tininess_afterRounding val m2_rec_resized = m2_resizer.io.out // Perform multiply-add val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth)) muladder.io.op := 0.U muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := m1_rec_resized muladder.io.b := m2_rec_resized muladder.io.c := self_rec // Convert result to standard format // TODO remove these intermediate recodings val out = Wire(Float(self.expWidth, self.sigWidth)) out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) out } override def +(t: Float): Float = { require(self.getWidth >= t.getWidth) // This just makes it easier to write the resizing code // Recode all operands val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Generate 1 as a float val in_to_rec_fn = Module(new INToRecFN(1, self.expWidth, self.sigWidth)) in_to_rec_fn.io.signedIn := false.B in_to_rec_fn.io.in := 1.U in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding val one_rec = in_to_rec_fn.io.out // Resize t val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth)) t_resizer.io.in := t_rec t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag t_resizer.io.detectTininess := consts.tininess_afterRounding val t_rec_resized = t_resizer.io.out // Perform addition val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth)) muladder.io.op := 0.U muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := t_rec_resized muladder.io.b := one_rec muladder.io.c := self_rec val result = Wire(Float(self.expWidth, self.sigWidth)) result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) result } override def -(t: Float): Float = { val t_sgn = t.bits(t.getWidth-1) val neg_t = Cat(~t_sgn, t.bits(t.getWidth-2,0)).asTypeOf(t) self + neg_t } override def >>(u: UInt): Float = { // Recode self val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Get 2^(-u) as a recoded float val shift_exp = Wire(UInt(self.expWidth.W)) shift_exp := self.bias.U - u val shift_fn = Cat(0.U(1.W), shift_exp, 0.U((self.sigWidth-1).W)) val shift_rec = recFNFromFN(self.expWidth, self.sigWidth, shift_fn) assert(shift_exp =/= 0.U, "scaling by denormalized numbers is not currently supported") // Multiply self and 2^(-u) val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth)) muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := self_rec muladder.io.b := shift_rec val result = Wire(Float(self.expWidth, self.sigWidth)) result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) result } override def >(t: Float): Bool = { // Recode all operands val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Resize t to self's width val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth)) t_resizer.io.in := t_rec t_resizer.io.roundingMode := consts.round_near_even t_resizer.io.detectTininess := consts.tininess_afterRounding val t_rec_resized = t_resizer.io.out val comparator = Module(new CompareRecFN(self.expWidth, self.sigWidth)) comparator.io.a := self_rec comparator.io.b := t_rec_resized comparator.io.signaling := false.B comparator.io.gt } override def withWidthOf(t: Float): Float = { val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth)) resizer.io.in := self_rec resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag resizer.io.detectTininess := consts.tininess_afterRounding val result = Wire(Float(t.expWidth, t.sigWidth)) result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out) result } override def clippedToWidthOf(t: Float): Float = { // TODO check for overflow. Right now, we just assume that overflow doesn't happen val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth)) resizer.io.in := self_rec resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag resizer.io.detectTininess := consts.tininess_afterRounding val result = Wire(Float(t.expWidth, t.sigWidth)) result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out) result } override def relu: Float = { val raw = rawFloatFromFN(self.expWidth, self.sigWidth, self.bits) val result = Wire(Float(self.expWidth, self.sigWidth)) result.bits := Mux(!raw.isZero && raw.sign, 0.U, self.bits) result } override def zero: Float = 0.U.asTypeOf(self) override def identity: Float = Cat(0.U(2.W), ~(0.U((self.expWidth-1).W)), 0.U((self.sigWidth-1).W)).asTypeOf(self) override def minimum: Float = Cat(1.U, ~(0.U(self.expWidth.W)), 0.U((self.sigWidth-1).W)).asTypeOf(self) } } implicit object DummySIntArithmetic extends Arithmetic[DummySInt] { override implicit def cast(self: DummySInt) = new ArithmeticOps(self) { override def *(t: DummySInt) = self.dontCare override def mac(m1: DummySInt, m2: DummySInt) = self.dontCare override def +(t: DummySInt) = self.dontCare override def -(t: DummySInt) = self.dontCare override def >>(t: UInt) = self.dontCare override def >(t: DummySInt): Bool = false.B override def identity = self.dontCare override def withWidthOf(t: DummySInt) = self.dontCare override def clippedToWidthOf(t: DummySInt) = self.dontCare override def relu = self.dontCare override def zero = self.dontCare override def minimum: DummySInt = self.dontCare } } }

module PE_350( // @[PE.scala:31:7] input clock, // @[PE.scala:31:7] input reset, // @[PE.scala:31:7] input [7:0] io_in_a, // @[PE.scala:35:14] input [19:0] io_in_b, // @[PE.scala:35:14] input [19:0] io_in_d, // @[PE.scala:35:14] output [7:0] io_out_a, // @[PE.scala:35:14] output [19:0] io_out_b, // @[PE.scala:35:14] output [19:0] io_out_c, // @[PE.scala:35:14] input io_in_control_dataflow, // @[PE.scala:35:14] input io_in_control_propagate, // @[PE.scala:35:14] input [4:0] io_in_control_shift, // @[PE.scala:35:14] output io_out_control_dataflow, // @[PE.scala:35:14] output io_out_control_propagate, // @[PE.scala:35:14] output [4:0] io_out_control_shift, // @[PE.scala:35:14] input [2:0] io_in_id, // @[PE.scala:35:14] output [2:0] io_out_id, // @[PE.scala:35:14] input io_in_last, // @[PE.scala:35:14] output io_out_last, // @[PE.scala:35:14] input io_in_valid, // @[PE.scala:35:14] output io_out_valid // @[PE.scala:35:14] ); wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:31:7] wire [19:0] io_in_b_0 = io_in_b; // @[PE.scala:31:7] wire [19:0] io_in_d_0 = io_in_d; // @[PE.scala:31:7] wire io_in_control_dataflow_0 = io_in_control_dataflow; // @[PE.scala:31:7] wire io_in_control_propagate_0 = io_in_control_propagate; // @[PE.scala:31:7] wire [4:0] io_in_control_shift_0 = io_in_control_shift; // @[PE.scala:31:7] wire [2:0] io_in_id_0 = io_in_id; // @[PE.scala:31:7] wire io_in_last_0 = io_in_last; // @[PE.scala:31:7] wire io_in_valid_0 = io_in_valid; // @[PE.scala:31:7] wire io_bad_dataflow = 1'h0; // @[PE.scala:31:7] wire _io_out_c_T_5 = 1'h0; // @[Arithmetic.scala:125:33] wire _io_out_c_T_6 = 1'h0; // @[Arithmetic.scala:125:60] wire _io_out_c_T_16 = 1'h0; // @[Arithmetic.scala:125:33] wire _io_out_c_T_17 = 1'h0; // @[Arithmetic.scala:125:60] wire [7:0] io_out_a_0 = io_in_a_0; // @[PE.scala:31:7] wire [19:0] _mac_unit_io_in_b_T = io_in_b_0; // @[PE.scala:31:7, :106:37] wire [19:0] _mac_unit_io_in_b_T_2 = io_in_b_0; // @[PE.scala:31:7, :113:37] wire [19:0] _mac_unit_io_in_b_T_8 = io_in_b_0; // @[PE.scala:31:7, :137:35] wire io_out_control_dataflow_0 = io_in_control_dataflow_0; // @[PE.scala:31:7] wire io_out_control_propagate_0 = io_in_control_propagate_0; // @[PE.scala:31:7] wire [4:0] io_out_control_shift_0 = io_in_control_shift_0; // @[PE.scala:31:7] wire [2:0] io_out_id_0 = io_in_id_0; // @[PE.scala:31:7] wire io_out_last_0 = io_in_last_0; // @[PE.scala:31:7] wire io_out_valid_0 = io_in_valid_0; // @[PE.scala:31:7] wire [19:0] io_out_b_0; // @[PE.scala:31:7] wire [19:0] io_out_c_0; // @[PE.scala:31:7] reg [7:0] c1; // @[PE.scala:70:15] wire [7:0] _io_out_c_zeros_T_1 = c1; // @[PE.scala:70:15] wire [7:0] _mac_unit_io_in_b_T_6 = c1; // @[PE.scala:70:15, :127:38] reg [7:0] c2; // @[PE.scala:71:15] wire [7:0] _io_out_c_zeros_T_10 = c2; // @[PE.scala:71:15] wire [7:0] _mac_unit_io_in_b_T_4 = c2; // @[PE.scala:71:15, :121:38] reg last_s; // @[PE.scala:89:25] wire flip = last_s != io_in_control_propagate_0; // @[PE.scala:31:7, :89:25, :90:21] wire [4:0] shift_offset = flip ? io_in_control_shift_0 : 5'h0; // @[PE.scala:31:7, :90:21, :91:25] wire _GEN = shift_offset == 5'h0; // @[PE.scala:91:25] wire _io_out_c_point_five_T; // @[Arithmetic.scala:101:32] assign _io_out_c_point_five_T = _GEN; // @[Arithmetic.scala:101:32] wire _io_out_c_point_five_T_5; // @[Arithmetic.scala:101:32] assign _io_out_c_point_five_T_5 = _GEN; // @[Arithmetic.scala:101:32] wire [5:0] _GEN_0 = {1'h0, shift_offset} - 6'h1; // @[PE.scala:91:25] wire [5:0] _io_out_c_point_five_T_1; // @[Arithmetic.scala:101:53] assign _io_out_c_point_five_T_1 = _GEN_0; // @[Arithmetic.scala:101:53] wire [5:0] _io_out_c_zeros_T_2; // @[Arithmetic.scala:102:66] assign _io_out_c_zeros_T_2 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66] wire [5:0] _io_out_c_point_five_T_6; // @[Arithmetic.scala:101:53] assign _io_out_c_point_five_T_6 = _GEN_0; // @[Arithmetic.scala:101:53] wire [5:0] _io_out_c_zeros_T_11; // @[Arithmetic.scala:102:66] assign _io_out_c_zeros_T_11 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66] wire [4:0] _io_out_c_point_five_T_2 = _io_out_c_point_five_T_1[4:0]; // @[Arithmetic.scala:101:53] wire [7:0] _io_out_c_point_five_T_3 = $signed($signed(c1) >>> _io_out_c_point_five_T_2); // @[PE.scala:70:15] wire _io_out_c_point_five_T_4 = _io_out_c_point_five_T_3[0]; // @[Arithmetic.scala:101:50] wire io_out_c_point_five = ~_io_out_c_point_five_T & _io_out_c_point_five_T_4; // @[Arithmetic.scala:101:{29,32,50}] wire _GEN_1 = shift_offset < 5'h2; // @[PE.scala:91:25] wire _io_out_c_zeros_T; // @[Arithmetic.scala:102:27] assign _io_out_c_zeros_T = _GEN_1; // @[Arithmetic.scala:102:27] wire _io_out_c_zeros_T_9; // @[Arithmetic.scala:102:27] assign _io_out_c_zeros_T_9 = _GEN_1; // @[Arithmetic.scala:102:27] wire [4:0] _io_out_c_zeros_T_3 = _io_out_c_zeros_T_2[4:0]; // @[Arithmetic.scala:102:66] wire [31:0] _io_out_c_zeros_T_4 = 32'h1 << _io_out_c_zeros_T_3; // @[Arithmetic.scala:102:{60,66}] wire [32:0] _io_out_c_zeros_T_5 = {1'h0, _io_out_c_zeros_T_4} - 33'h1; // @[Arithmetic.scala:102:{60,81}] wire [31:0] _io_out_c_zeros_T_6 = _io_out_c_zeros_T_5[31:0]; // @[Arithmetic.scala:102:81] wire [31:0] _io_out_c_zeros_T_7 = {24'h0, _io_out_c_zeros_T_6[7:0] & _io_out_c_zeros_T_1}; // @[Arithmetic.scala:102:{45,52,81}] wire [31:0] _io_out_c_zeros_T_8 = _io_out_c_zeros_T ? 32'h0 : _io_out_c_zeros_T_7; // @[Arithmetic.scala:102:{24,27,52}] wire io_out_c_zeros = |_io_out_c_zeros_T_8; // @[Arithmetic.scala:102:{24,89}] wire [7:0] _GEN_2 = {3'h0, shift_offset}; // @[PE.scala:91:25] wire [7:0] _GEN_3 = $signed($signed(c1) >>> _GEN_2); // @[PE.scala:70:15] wire [7:0] _io_out_c_ones_digit_T; // @[Arithmetic.scala:103:30] assign _io_out_c_ones_digit_T = _GEN_3; // @[Arithmetic.scala:103:30] wire [7:0] _io_out_c_T; // @[Arithmetic.scala:107:15] assign _io_out_c_T = _GEN_3; // @[Arithmetic.scala:103:30, :107:15] wire io_out_c_ones_digit = _io_out_c_ones_digit_T[0]; // @[Arithmetic.scala:103:30] wire _io_out_c_r_T = io_out_c_zeros | io_out_c_ones_digit; // @[Arithmetic.scala:102:89, :103:30, :105:38] wire _io_out_c_r_T_1 = io_out_c_point_five & _io_out_c_r_T; // @[Arithmetic.scala:101:29, :105:{29,38}] wire io_out_c_r = _io_out_c_r_T_1; // @[Arithmetic.scala:105:{29,53}] wire [1:0] _io_out_c_T_1 = {1'h0, io_out_c_r}; // @[Arithmetic.scala:105:53, :107:33] wire [8:0] _io_out_c_T_2 = {_io_out_c_T[7], _io_out_c_T} + {{7{_io_out_c_T_1[1]}}, _io_out_c_T_1}; // @[Arithmetic.scala:107:{15,28,33}] wire [7:0] _io_out_c_T_3 = _io_out_c_T_2[7:0]; // @[Arithmetic.scala:107:28] wire [7:0] _io_out_c_T_4 = _io_out_c_T_3; // @[Arithmetic.scala:107:28] wire [19:0] _io_out_c_T_7 = {{12{_io_out_c_T_4[7]}}, _io_out_c_T_4}; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_8 = _io_out_c_T_7; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_9 = _io_out_c_T_8; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_10 = _io_out_c_T_9; // @[Arithmetic.scala:125:{81,99}] wire [19:0] _mac_unit_io_in_b_T_1 = _mac_unit_io_in_b_T; // @[PE.scala:106:37] wire [7:0] _mac_unit_io_in_b_WIRE = _mac_unit_io_in_b_T_1[7:0]; // @[PE.scala:106:37] wire [7:0] _c1_T = io_in_d_0[7:0]; // @[PE.scala:31:7] wire [7:0] _c2_T = io_in_d_0[7:0]; // @[PE.scala:31:7] wire [7:0] _c1_T_1 = _c1_T; // @[Arithmetic.scala:114:{15,33}] wire [4:0] _io_out_c_point_five_T_7 = _io_out_c_point_five_T_6[4:0]; // @[Arithmetic.scala:101:53] wire [7:0] _io_out_c_point_five_T_8 = $signed($signed(c2) >>> _io_out_c_point_five_T_7); // @[PE.scala:71:15] wire _io_out_c_point_five_T_9 = _io_out_c_point_five_T_8[0]; // @[Arithmetic.scala:101:50] wire io_out_c_point_five_1 = ~_io_out_c_point_five_T_5 & _io_out_c_point_five_T_9; // @[Arithmetic.scala:101:{29,32,50}] wire [4:0] _io_out_c_zeros_T_12 = _io_out_c_zeros_T_11[4:0]; // @[Arithmetic.scala:102:66] wire [31:0] _io_out_c_zeros_T_13 = 32'h1 << _io_out_c_zeros_T_12; // @[Arithmetic.scala:102:{60,66}] wire [32:0] _io_out_c_zeros_T_14 = {1'h0, _io_out_c_zeros_T_13} - 33'h1; // @[Arithmetic.scala:102:{60,81}] wire [31:0] _io_out_c_zeros_T_15 = _io_out_c_zeros_T_14[31:0]; // @[Arithmetic.scala:102:81] wire [31:0] _io_out_c_zeros_T_16 = {24'h0, _io_out_c_zeros_T_15[7:0] & _io_out_c_zeros_T_10}; // @[Arithmetic.scala:102:{45,52,81}] wire [31:0] _io_out_c_zeros_T_17 = _io_out_c_zeros_T_9 ? 32'h0 : _io_out_c_zeros_T_16; // @[Arithmetic.scala:102:{24,27,52}] wire io_out_c_zeros_1 = |_io_out_c_zeros_T_17; // @[Arithmetic.scala:102:{24,89}] wire [7:0] _GEN_4 = $signed($signed(c2) >>> _GEN_2); // @[PE.scala:71:15] wire [7:0] _io_out_c_ones_digit_T_1; // @[Arithmetic.scala:103:30] assign _io_out_c_ones_digit_T_1 = _GEN_4; // @[Arithmetic.scala:103:30] wire [7:0] _io_out_c_T_11; // @[Arithmetic.scala:107:15] assign _io_out_c_T_11 = _GEN_4; // @[Arithmetic.scala:103:30, :107:15] wire io_out_c_ones_digit_1 = _io_out_c_ones_digit_T_1[0]; // @[Arithmetic.scala:103:30] wire _io_out_c_r_T_2 = io_out_c_zeros_1 | io_out_c_ones_digit_1; // @[Arithmetic.scala:102:89, :103:30, :105:38] wire _io_out_c_r_T_3 = io_out_c_point_five_1 & _io_out_c_r_T_2; // @[Arithmetic.scala:101:29, :105:{29,38}] wire io_out_c_r_1 = _io_out_c_r_T_3; // @[Arithmetic.scala:105:{29,53}] wire [1:0] _io_out_c_T_12 = {1'h0, io_out_c_r_1}; // @[Arithmetic.scala:105:53, :107:33] wire [8:0] _io_out_c_T_13 = {_io_out_c_T_11[7], _io_out_c_T_11} + {{7{_io_out_c_T_12[1]}}, _io_out_c_T_12}; // @[Arithmetic.scala:107:{15,28,33}] wire [7:0] _io_out_c_T_14 = _io_out_c_T_13[7:0]; // @[Arithmetic.scala:107:28] wire [7:0] _io_out_c_T_15 = _io_out_c_T_14; // @[Arithmetic.scala:107:28] wire [19:0] _io_out_c_T_18 = {{12{_io_out_c_T_15[7]}}, _io_out_c_T_15}; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_19 = _io_out_c_T_18; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_20 = _io_out_c_T_19; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_21 = _io_out_c_T_20; // @[Arithmetic.scala:125:{81,99}] wire [19:0] _mac_unit_io_in_b_T_3 = _mac_unit_io_in_b_T_2; // @[PE.scala:113:37] wire [7:0] _mac_unit_io_in_b_WIRE_1 = _mac_unit_io_in_b_T_3[7:0]; // @[PE.scala:113:37] wire [7:0] _c2_T_1 = _c2_T; // @[Arithmetic.scala:114:{15,33}] wire [7:0] _mac_unit_io_in_b_T_5; // @[PE.scala:121:38] assign _mac_unit_io_in_b_T_5 = _mac_unit_io_in_b_T_4; // @[PE.scala:121:38] wire [7:0] _mac_unit_io_in_b_WIRE_2 = _mac_unit_io_in_b_T_5; // @[PE.scala:121:38] assign io_out_c_0 = io_in_control_propagate_0 ? {{12{c1[7]}}, c1} : {{12{c2[7]}}, c2}; // @[PE.scala:31:7, :70:15, :71:15, :119:30, :120:16, :126:16] wire [7:0] _mac_unit_io_in_b_T_7; // @[PE.scala:127:38] assign _mac_unit_io_in_b_T_7 = _mac_unit_io_in_b_T_6; // @[PE.scala:127:38] wire [7:0] _mac_unit_io_in_b_WIRE_3 = _mac_unit_io_in_b_T_7; // @[PE.scala:127:38] wire [19:0] _mac_unit_io_in_b_T_9 = _mac_unit_io_in_b_T_8; // @[PE.scala:137:35] wire [7:0] _mac_unit_io_in_b_WIRE_4 = _mac_unit_io_in_b_T_9[7:0]; // @[PE.scala:137:35] always @(posedge clock) begin // @[PE.scala:31:7] if (io_in_valid_0 & io_in_control_propagate_0) // @[PE.scala:31:7, :102:95, :141:17, :142:8] c1 <= io_in_d_0[7:0]; // @[PE.scala:31:7, :70:15] if (~(~io_in_valid_0 | io_in_control_propagate_0)) // @[PE.scala:31:7, :71:15, :102:95, :119:30, :130:10, :141:{9,17}, :143:8] c2 <= io_in_d_0[7:0]; // @[PE.scala:31:7, :71:15] if (io_in_valid_0) // @[PE.scala:31:7] last_s <= io_in_control_propagate_0; // @[PE.scala:31:7, :89:25] always @(posedge) MacUnit_94 mac_unit ( // @[PE.scala:64:24] .clock (clock), .reset (reset), .io_in_a (io_in_a_0), // @[PE.scala:31:7] .io_in_b (io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE_2 : _mac_unit_io_in_b_WIRE_3), // @[PE.scala:31:7, :119:30, :121:{24,38}, :127:{24,38}] .io_in_c (io_in_b_0), // @[PE.scala:31:7] .io_out_d (io_out_b_0) ); // @[PE.scala:64:24] assign io_out_a = io_out_a_0; // @[PE.scala:31:7] assign io_out_b = io_out_b_0; // @[PE.scala:31:7] assign io_out_c = io_out_c_0; // @[PE.scala:31:7] assign io_out_control_dataflow = io_out_control_dataflow_0; // @[PE.scala:31:7] assign io_out_control_propagate = io_out_control_propagate_0; // @[PE.scala:31:7] assign io_out_control_shift = io_out_control_shift_0; // @[PE.scala:31:7] assign io_out_id = io_out_id_0; // @[PE.scala:31:7] assign io_out_last = io_out_last_0; // @[PE.scala:31:7] assign io_out_valid = io_out_valid_0; // @[PE.scala:31:7] endmodule

Generate the Verilog code corresponding to the following Chisel files. File UnsafeAXI4ToTL.scala: package ara import chisel3._ import chisel3.util._ import freechips.rocketchip.amba._ import freechips.rocketchip.amba.axi4._ import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.diplomacy._ import freechips.rocketchip.tilelink._ import freechips.rocketchip.util._ class ReorderData(val dataWidth: Int, val respWidth: Int, val userFields: Seq[BundleFieldBase]) extends Bundle { val data = UInt(dataWidth.W) val resp = UInt(respWidth.W) val last = Bool() val user = BundleMap(userFields) } /** Parameters for [[BaseReservableListBuffer]] and all child classes. * * @param numEntries Total number of elements that can be stored in the 'data' RAM * @param numLists Maximum number of linked lists * @param numBeats Maximum number of beats per entry */ case class ReservableListBufferParameters(numEntries: Int, numLists: Int, numBeats: Int) { // Avoid zero-width wires when we call 'log2Ceil' val entryBits = if (numEntries == 1) 1 else log2Ceil(numEntries) val listBits = if (numLists == 1) 1 else log2Ceil(numLists) val beatBits = if (numBeats == 1) 1 else log2Ceil(numBeats) } case class UnsafeAXI4ToTLNode(numTlTxns: Int, wcorrupt: Boolean)(implicit valName: ValName) extends MixedAdapterNode(AXI4Imp, TLImp)( dFn = { case mp => TLMasterPortParameters.v2( masters = mp.masters.zipWithIndex.map { case (m, i) => // Support 'numTlTxns' read requests and 'numTlTxns' write requests at once. val numSourceIds = numTlTxns * 2 TLMasterParameters.v2( name = m.name, sourceId = IdRange(i * numSourceIds, (i + 1) * numSourceIds), nodePath = m.nodePath ) }, echoFields = mp.echoFields, requestFields = AMBAProtField() +: mp.requestFields, responseKeys = mp.responseKeys ) }, uFn = { mp => AXI4SlavePortParameters( slaves = mp.managers.map { m => val maxXfer = TransferSizes(1, mp.beatBytes * (1 << AXI4Parameters.lenBits)) AXI4SlaveParameters( address = m.address, resources = m.resources, regionType = m.regionType, executable = m.executable, nodePath = m.nodePath, supportsWrite = m.supportsPutPartial.intersect(maxXfer), supportsRead = m.supportsGet.intersect(maxXfer), interleavedId = Some(0) // TL2 never interleaves D beats ) }, beatBytes = mp.beatBytes, minLatency = mp.minLatency, responseFields = mp.responseFields, requestKeys = (if (wcorrupt) Seq(AMBACorrupt) else Seq()) ++ mp.requestKeys.filter(_ != AMBAProt) ) } ) class UnsafeAXI4ToTL(numTlTxns: Int, wcorrupt: Boolean)(implicit p: Parameters) extends LazyModule { require(numTlTxns >= 1) require(isPow2(numTlTxns), s"Number of TileLink transactions ($numTlTxns) must be a power of 2") val node = UnsafeAXI4ToTLNode(numTlTxns, wcorrupt) lazy val module = new LazyModuleImp(this) { (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => edgeIn.master.masters.foreach { m => require(m.aligned, "AXI4ToTL requires aligned requests") } val numIds = edgeIn.master.endId val beatBytes = edgeOut.slave.beatBytes val maxTransfer = edgeOut.slave.maxTransfer val maxBeats = maxTransfer / beatBytes // Look for an Error device to redirect bad requests val errorDevs = edgeOut.slave.managers.filter(_.nodePath.last.lazyModule.className == "TLError") require(!errorDevs.isEmpty, "There is no TLError reachable from AXI4ToTL. One must be instantiated.") val errorDev = errorDevs.maxBy(_.maxTransfer) val errorDevAddr = errorDev.address.head.base require( errorDev.supportsPutPartial.contains(maxTransfer), s"Error device supports ${errorDev.supportsPutPartial} PutPartial but must support $maxTransfer" ) require( errorDev.supportsGet.contains(maxTransfer), s"Error device supports ${errorDev.supportsGet} Get but must support $maxTransfer" ) // All of the read-response reordering logic. val listBufData = new ReorderData(beatBytes * 8, edgeIn.bundle.respBits, out.d.bits.user.fields) val listBufParams = ReservableListBufferParameters(numTlTxns, numIds, maxBeats) val listBuffer = if (numTlTxns > 1) { Module(new ReservableListBuffer(listBufData, listBufParams)) } else { Module(new PassthroughListBuffer(listBufData, listBufParams)) } // To differentiate between read and write transaction IDs, we will set the MSB of the TileLink 'source' field to // 0 for read requests and 1 for write requests. val isReadSourceBit = 0.U(1.W) val isWriteSourceBit = 1.U(1.W) /* Read request logic */ val rOut = Wire(Decoupled(new TLBundleA(edgeOut.bundle))) val rBytes1 = in.ar.bits.bytes1() val rSize = OH1ToUInt(rBytes1) val rOk = edgeOut.slave.supportsGetSafe(in.ar.bits.addr, rSize) val rId = if (numTlTxns > 1) { Cat(isReadSourceBit, listBuffer.ioReservedIndex) } else { isReadSourceBit } val rAddr = Mux(rOk, in.ar.bits.addr, errorDevAddr.U | in.ar.bits.addr(log2Ceil(beatBytes) - 1, 0)) // Indicates if there are still valid TileLink source IDs left to use. val canIssueR = listBuffer.ioReserve.ready listBuffer.ioReserve.bits := in.ar.bits.id listBuffer.ioReserve.valid := in.ar.valid && rOut.ready in.ar.ready := rOut.ready && canIssueR rOut.valid := in.ar.valid && canIssueR rOut.bits :<= edgeOut.Get(rId, rAddr, rSize)._2 rOut.bits.user :<= in.ar.bits.user rOut.bits.user.lift(AMBAProt).foreach { rProt => rProt.privileged := in.ar.bits.prot(0) rProt.secure := !in.ar.bits.prot(1) rProt.fetch := in.ar.bits.prot(2) rProt.bufferable := in.ar.bits.cache(0) rProt.modifiable := in.ar.bits.cache(1) rProt.readalloc := in.ar.bits.cache(2) rProt.writealloc := in.ar.bits.cache(3) } /* Write request logic */ // Strip off the MSB, which identifies the transaction as read vs write. val strippedResponseSourceId = if (numTlTxns > 1) { out.d.bits.source((out.d.bits.source).getWidth - 2, 0) } else { // When there's only 1 TileLink transaction allowed for read/write, then this field is always 0. 0.U(1.W) } // Track when a write request burst is in progress. val writeBurstBusy = RegInit(false.B) when(in.w.fire) { writeBurstBusy := !in.w.bits.last } val usedWriteIds = RegInit(0.U(numTlTxns.W)) val canIssueW = !usedWriteIds.andR val usedWriteIdsSet = WireDefault(0.U(numTlTxns.W)) val usedWriteIdsClr = WireDefault(0.U(numTlTxns.W)) usedWriteIds := (usedWriteIds & ~usedWriteIdsClr) | usedWriteIdsSet // Since write responses can show up in the middle of a write burst, we need to ensure the write burst ID doesn't // change mid-burst. val freeWriteIdOHRaw = Wire(UInt(numTlTxns.W)) val freeWriteIdOH = freeWriteIdOHRaw holdUnless !writeBurstBusy val freeWriteIdIndex = OHToUInt(freeWriteIdOH) freeWriteIdOHRaw := ~(leftOR(~usedWriteIds) << 1) & ~usedWriteIds val wOut = Wire(Decoupled(new TLBundleA(edgeOut.bundle))) val wBytes1 = in.aw.bits.bytes1() val wSize = OH1ToUInt(wBytes1) val wOk = edgeOut.slave.supportsPutPartialSafe(in.aw.bits.addr, wSize) val wId = if (numTlTxns > 1) { Cat(isWriteSourceBit, freeWriteIdIndex) } else { isWriteSourceBit } val wAddr = Mux(wOk, in.aw.bits.addr, errorDevAddr.U | in.aw.bits.addr(log2Ceil(beatBytes) - 1, 0)) // Here, we're taking advantage of the Irrevocable behavior of AXI4 (once 'valid' is asserted it must remain // asserted until the handshake occurs). We will only accept W-channel beats when we have a valid AW beat, but // the AW-channel beat won't fire until the final W-channel beat fires. So, we have stable address/size/strb // bits during a W-channel burst. in.aw.ready := wOut.ready && in.w.valid && in.w.bits.last && canIssueW in.w.ready := wOut.ready && in.aw.valid && canIssueW wOut.valid := in.aw.valid && in.w.valid && canIssueW wOut.bits :<= edgeOut.Put(wId, wAddr, wSize, in.w.bits.data, in.w.bits.strb)._2 in.w.bits.user.lift(AMBACorrupt).foreach { wOut.bits.corrupt := _ } wOut.bits.user :<= in.aw.bits.user wOut.bits.user.lift(AMBAProt).foreach { wProt => wProt.privileged := in.aw.bits.prot(0) wProt.secure := !in.aw.bits.prot(1) wProt.fetch := in.aw.bits.prot(2) wProt.bufferable := in.aw.bits.cache(0) wProt.modifiable := in.aw.bits.cache(1) wProt.readalloc := in.aw.bits.cache(2) wProt.writealloc := in.aw.bits.cache(3) } // Merge the AXI4 read/write requests into the TL-A channel. TLArbiter(TLArbiter.roundRobin)(out.a, (0.U, rOut), (in.aw.bits.len, wOut)) /* Read/write response logic */ val okB = Wire(Irrevocable(new AXI4BundleB(edgeIn.bundle))) val okR = Wire(Irrevocable(new AXI4BundleR(edgeIn.bundle))) val dResp = Mux(out.d.bits.denied || out.d.bits.corrupt, AXI4Parameters.RESP_SLVERR, AXI4Parameters.RESP_OKAY) val dHasData = edgeOut.hasData(out.d.bits) val (_dFirst, dLast, _dDone, dCount) = edgeOut.count(out.d) val dNumBeats1 = edgeOut.numBeats1(out.d.bits) // Handle cases where writeack arrives before write is done val writeEarlyAck = (UIntToOH(strippedResponseSourceId) & usedWriteIds) === 0.U out.d.ready := Mux(dHasData, listBuffer.ioResponse.ready, okB.ready && !writeEarlyAck) listBuffer.ioDataOut.ready := okR.ready okR.valid := listBuffer.ioDataOut.valid okB.valid := out.d.valid && !dHasData && !writeEarlyAck listBuffer.ioResponse.valid := out.d.valid && dHasData listBuffer.ioResponse.bits.index := strippedResponseSourceId listBuffer.ioResponse.bits.data.data := out.d.bits.data listBuffer.ioResponse.bits.data.resp := dResp listBuffer.ioResponse.bits.data.last := dLast listBuffer.ioResponse.bits.data.user :<= out.d.bits.user listBuffer.ioResponse.bits.count := dCount listBuffer.ioResponse.bits.numBeats1 := dNumBeats1 okR.bits.id := listBuffer.ioDataOut.bits.listIndex okR.bits.data := listBuffer.ioDataOut.bits.payload.data okR.bits.resp := listBuffer.ioDataOut.bits.payload.resp okR.bits.last := listBuffer.ioDataOut.bits.payload.last okR.bits.user :<= listBuffer.ioDataOut.bits.payload.user // Upon the final beat in a write request, record a mapping from TileLink source ID to AXI write ID. Upon a write // response, mark the write transaction as complete. val writeIdMap = Mem(numTlTxns, UInt(log2Ceil(numIds).W)) val writeResponseId = writeIdMap.read(strippedResponseSourceId) when(wOut.fire) { writeIdMap.write(freeWriteIdIndex, in.aw.bits.id) } when(edgeOut.done(wOut)) { usedWriteIdsSet := freeWriteIdOH } when(okB.fire) { usedWriteIdsClr := UIntToOH(strippedResponseSourceId, numTlTxns) } okB.bits.id := writeResponseId okB.bits.resp := dResp okB.bits.user :<= out.d.bits.user // AXI4 needs irrevocable behaviour in.r <> Queue.irrevocable(okR, 1, flow = true) in.b <> Queue.irrevocable(okB, 1, flow = true) // Unused channels out.b.ready := true.B out.c.valid := false.B out.e.valid := false.B /* Alignment constraints. The AXI4Fragmenter should guarantee all of these constraints. */ def checkRequest[T <: AXI4BundleA](a: IrrevocableIO[T], reqType: String): Unit = { val lReqType = reqType.toLowerCase when(a.valid) { assert(a.bits.len < maxBeats.U, s"$reqType burst length (%d) must be less than $maxBeats", a.bits.len + 1.U) // Narrow transfers and FIXED bursts must be single-beat bursts. when(a.bits.len =/= 0.U) { assert( a.bits.size === log2Ceil(beatBytes).U, s"Narrow $lReqType transfers (%d < $beatBytes bytes) can't be multi-beat bursts (%d beats)", 1.U << a.bits.size, a.bits.len + 1.U ) assert( a.bits.burst =/= AXI4Parameters.BURST_FIXED, s"Fixed $lReqType bursts can't be multi-beat bursts (%d beats)", a.bits.len + 1.U ) } // Furthermore, the transfer size (a.bits.bytes1() + 1.U) must be naturally-aligned to the address (in // particular, during both WRAP and INCR bursts), but this constraint is already checked by TileLink // Monitors. Note that this alignment requirement means that WRAP bursts are identical to INCR bursts. } } checkRequest(in.ar, "Read") checkRequest(in.aw, "Write") } } } object UnsafeAXI4ToTL { def apply(numTlTxns: Int = 1, wcorrupt: Boolean = true)(implicit p: Parameters) = { val axi42tl = LazyModule(new UnsafeAXI4ToTL(numTlTxns, wcorrupt)) axi42tl.node } } /* ReservableListBuffer logic, and associated classes. */ class ResponsePayload[T <: Data](val data: T, val params: ReservableListBufferParameters) extends Bundle { val index = UInt(params.entryBits.W) val count = UInt(params.beatBits.W) val numBeats1 = UInt(params.beatBits.W) } class DataOutPayload[T <: Data](val payload: T, val params: ReservableListBufferParameters) extends Bundle { val listIndex = UInt(params.listBits.W) } /** Abstract base class to unify [[ReservableListBuffer]] and [[PassthroughListBuffer]]. */ abstract class BaseReservableListBuffer[T <: Data](gen: T, params: ReservableListBufferParameters) extends Module { require(params.numEntries > 0) require(params.numLists > 0) val ioReserve = IO(Flipped(Decoupled(UInt(params.listBits.W)))) val ioReservedIndex = IO(Output(UInt(params.entryBits.W))) val ioResponse = IO(Flipped(Decoupled(new ResponsePayload(gen, params)))) val ioDataOut = IO(Decoupled(new DataOutPayload(gen, params))) } /** A modified version of 'ListBuffer' from 'sifive/block-inclusivecache-sifive'. This module forces users to reserve * linked list entries (through the 'ioReserve' port) before writing data into those linked lists (through the * 'ioResponse' port). Each response is tagged to indicate which linked list it is written into. The responses for a * given linked list can come back out-of-order, but they will be read out through the 'ioDataOut' port in-order. * * ==Constructor== * @param gen Chisel type of linked list data element * @param params Other parameters * * ==Module IO== * @param ioReserve Index of list to reserve a new element in * @param ioReservedIndex Index of the entry that was reserved in the linked list, valid when 'ioReserve.fire' * @param ioResponse Payload containing response data and linked-list-entry index * @param ioDataOut Payload containing data read from response linked list and linked list index */ class ReservableListBuffer[T <: Data](gen: T, params: ReservableListBufferParameters) extends BaseReservableListBuffer(gen, params) { val valid = RegInit(0.U(params.numLists.W)) val head = Mem(params.numLists, UInt(params.entryBits.W)) val tail = Mem(params.numLists, UInt(params.entryBits.W)) val used = RegInit(0.U(params.numEntries.W)) val next = Mem(params.numEntries, UInt(params.entryBits.W)) val map = Mem(params.numEntries, UInt(params.listBits.W)) val dataMems = Seq.fill(params.numBeats) { SyncReadMem(params.numEntries, gen) } val dataIsPresent = RegInit(0.U(params.numEntries.W)) val beats = Mem(params.numEntries, UInt(params.beatBits.W)) // The 'data' SRAM should be single-ported (read-or-write), since dual-ported SRAMs are significantly slower. val dataMemReadEnable = WireDefault(false.B) val dataMemWriteEnable = WireDefault(false.B) assert(!(dataMemReadEnable && dataMemWriteEnable)) // 'freeOH' has a single bit set, which is the least-significant bit that is cleared in 'used'. So, it's the // lowest-index entry in the 'data' RAM which is free. val freeOH = Wire(UInt(params.numEntries.W)) val freeIndex = OHToUInt(freeOH) freeOH := ~(leftOR(~used) << 1) & ~used ioReservedIndex := freeIndex val validSet = WireDefault(0.U(params.numLists.W)) val validClr = WireDefault(0.U(params.numLists.W)) val usedSet = WireDefault(0.U(params.numEntries.W)) val usedClr = WireDefault(0.U(params.numEntries.W)) val dataIsPresentSet = WireDefault(0.U(params.numEntries.W)) val dataIsPresentClr = WireDefault(0.U(params.numEntries.W)) valid := (valid & ~validClr) | validSet used := (used & ~usedClr) | usedSet dataIsPresent := (dataIsPresent & ~dataIsPresentClr) | dataIsPresentSet /* Reservation logic signals */ val reserveTail = Wire(UInt(params.entryBits.W)) val reserveIsValid = Wire(Bool()) /* Response logic signals */ val responseIndex = Wire(UInt(params.entryBits.W)) val responseListIndex = Wire(UInt(params.listBits.W)) val responseHead = Wire(UInt(params.entryBits.W)) val responseTail = Wire(UInt(params.entryBits.W)) val nextResponseHead = Wire(UInt(params.entryBits.W)) val nextDataIsPresent = Wire(Bool()) val isResponseInOrder = Wire(Bool()) val isEndOfList = Wire(Bool()) val isLastBeat = Wire(Bool()) val isLastResponseBeat = Wire(Bool()) val isLastUnwindBeat = Wire(Bool()) /* Reservation logic */ reserveTail := tail.read(ioReserve.bits) reserveIsValid := valid(ioReserve.bits) ioReserve.ready := !used.andR // When we want to append-to and destroy the same linked list on the same cycle, we need to take special care that we // actually start a new list, rather than appending to a list that's about to disappear. val reserveResponseSameList = ioReserve.bits === responseListIndex val appendToAndDestroyList = ioReserve.fire && ioDataOut.fire && reserveResponseSameList && isEndOfList && isLastBeat when(ioReserve.fire) { validSet := UIntToOH(ioReserve.bits, params.numLists) usedSet := freeOH when(reserveIsValid && !appendToAndDestroyList) { next.write(reserveTail, freeIndex) }.otherwise { head.write(ioReserve.bits, freeIndex) } tail.write(ioReserve.bits, freeIndex) map.write(freeIndex, ioReserve.bits) } /* Response logic */ // The majority of the response logic (reading from and writing to the various RAMs) is common between the // response-from-IO case (ioResponse.fire) and the response-from-unwind case (unwindDataIsValid). // The read from the 'next' RAM should be performed at the address given by 'responseHead'. However, we only use the // 'nextResponseHead' signal when 'isResponseInOrder' is asserted (both in the response-from-IO and // response-from-unwind cases), which implies that 'responseHead' equals 'responseIndex'. 'responseHead' comes after // two back-to-back RAM reads, so indexing into the 'next' RAM with 'responseIndex' is much quicker. responseHead := head.read(responseListIndex) responseTail := tail.read(responseListIndex) nextResponseHead := next.read(responseIndex) nextDataIsPresent := dataIsPresent(nextResponseHead) // Note that when 'isEndOfList' is asserted, 'nextResponseHead' (and therefore 'nextDataIsPresent') is invalid, since // there isn't a next element in the linked list. isResponseInOrder := responseHead === responseIndex isEndOfList := responseHead === responseTail isLastResponseBeat := ioResponse.bits.count === ioResponse.bits.numBeats1 // When a response's last beat is sent to the output channel, mark it as completed. This can happen in two // situations: // 1. We receive an in-order response, which travels straight from 'ioResponse' to 'ioDataOut'. The 'data' SRAM // reservation was never needed. // 2. An entry is read out of the 'data' SRAM (within the unwind FSM). when(ioDataOut.fire && isLastBeat) { // Mark the reservation as no-longer-used. usedClr := UIntToOH(responseIndex, params.numEntries) // If the response is in-order, then we're popping an element from this linked list. when(isEndOfList) { // Once we pop the last element from a linked list, mark it as no-longer-present. validClr := UIntToOH(responseListIndex, params.numLists) }.otherwise { // Move the linked list's head pointer to the new head pointer. head.write(responseListIndex, nextResponseHead) } } // If we get an out-of-order response, then stash it in the 'data' SRAM for later unwinding. when(ioResponse.fire && !isResponseInOrder) { dataMemWriteEnable := true.B when(isLastResponseBeat) { dataIsPresentSet := UIntToOH(ioResponse.bits.index, params.numEntries) beats.write(ioResponse.bits.index, ioResponse.bits.numBeats1) } } // Use the 'ioResponse.bits.count' index (AKA the beat number) to select which 'data' SRAM to write to. val responseCountOH = UIntToOH(ioResponse.bits.count, params.numBeats) (responseCountOH.asBools zip dataMems) foreach { case (select, seqMem) => when(select && dataMemWriteEnable) { seqMem.write(ioResponse.bits.index, ioResponse.bits.data) } } /* Response unwind logic */ // Unwind FSM state definitions val sIdle :: sUnwinding :: Nil = Enum(2) val unwindState = RegInit(sIdle) val busyUnwinding = unwindState === sUnwinding val startUnwind = Wire(Bool()) val stopUnwind = Wire(Bool()) when(startUnwind) { unwindState := sUnwinding }.elsewhen(stopUnwind) { unwindState := sIdle } assert(!(startUnwind && stopUnwind)) // Start the unwind FSM when there is an old out-of-order response stored in the 'data' SRAM that is now about to // become the next in-order response. As noted previously, when 'isEndOfList' is asserted, 'nextDataIsPresent' is // invalid. // // Note that since an in-order response from 'ioResponse' to 'ioDataOut' starts the unwind FSM, we don't have to // worry about overwriting the 'data' SRAM's output when we start the unwind FSM. startUnwind := ioResponse.fire && isResponseInOrder && isLastResponseBeat && !isEndOfList && nextDataIsPresent // Stop the unwind FSM when the output channel consumes the final beat of an element from the unwind FSM, and one of // two things happens: // 1. We're still waiting for the next in-order response for this list (!nextDataIsPresent) // 2. There are no more outstanding responses in this list (isEndOfList) // // Including 'busyUnwinding' ensures this is a single-cycle pulse, and it never fires while in-order transactions are // passing from 'ioResponse' to 'ioDataOut'. stopUnwind := busyUnwinding && ioDataOut.fire && isLastUnwindBeat && (!nextDataIsPresent || isEndOfList) val isUnwindBurstOver = Wire(Bool()) val startNewBurst = startUnwind || (isUnwindBurstOver && dataMemReadEnable) // Track the number of beats left to unwind for each list entry. At the start of a new burst, we flop the number of // beats in this burst (minus 1) into 'unwindBeats1', and we reset the 'beatCounter' counter. With each beat, we // increment 'beatCounter' until it reaches 'unwindBeats1'. val unwindBeats1 = Reg(UInt(params.beatBits.W)) val nextBeatCounter = Wire(UInt(params.beatBits.W)) val beatCounter = RegNext(nextBeatCounter) isUnwindBurstOver := beatCounter === unwindBeats1 when(startNewBurst) { unwindBeats1 := beats.read(nextResponseHead) nextBeatCounter := 0.U }.elsewhen(dataMemReadEnable) { nextBeatCounter := beatCounter + 1.U }.otherwise { nextBeatCounter := beatCounter } // When unwinding, feed the next linked-list head pointer (read out of the 'next' RAM) back so we can unwind the next // entry in this linked list. Only update the pointer when we're actually moving to the next 'data' SRAM entry (which // happens at the start of reading a new stored burst). val unwindResponseIndex = RegEnable(nextResponseHead, startNewBurst) responseIndex := Mux(busyUnwinding, unwindResponseIndex, ioResponse.bits.index) // Hold 'nextResponseHead' static while we're in the middle of unwinding a multi-beat burst entry. We don't want the // SRAM read address to shift while reading beats from a burst. Note that this is identical to 'nextResponseHead // holdUnless startNewBurst', but 'unwindResponseIndex' already implements the 'RegEnable' signal in 'holdUnless'. val unwindReadAddress = Mux(startNewBurst, nextResponseHead, unwindResponseIndex) // The 'data' SRAM's output is valid if we read from the SRAM on the previous cycle. The SRAM's output stays valid // until it is consumed by the output channel (and if we don't read from the SRAM again on that same cycle). val unwindDataIsValid = RegInit(false.B) when(dataMemReadEnable) { unwindDataIsValid := true.B }.elsewhen(ioDataOut.fire) { unwindDataIsValid := false.B } isLastUnwindBeat := isUnwindBurstOver && unwindDataIsValid // Indicates if this is the last beat for both 'ioResponse'-to-'ioDataOut' and unwind-to-'ioDataOut' beats. isLastBeat := Mux(busyUnwinding, isLastUnwindBeat, isLastResponseBeat) // Select which SRAM to read from based on the beat counter. val dataOutputVec = Wire(Vec(params.numBeats, gen)) val nextBeatCounterOH = UIntToOH(nextBeatCounter, params.numBeats) (nextBeatCounterOH.asBools zip dataMems).zipWithIndex foreach { case ((select, seqMem), i) => dataOutputVec(i) := seqMem.read(unwindReadAddress, select && dataMemReadEnable) } // Select the current 'data' SRAM output beat, and save the output in a register in case we're being back-pressured // by 'ioDataOut'. This implements the functionality of 'readAndHold', but only on the single SRAM we're reading // from. val dataOutput = dataOutputVec(beatCounter) holdUnless RegNext(dataMemReadEnable) // Mark 'data' burst entries as no-longer-present as they get read out of the SRAM. when(dataMemReadEnable) { dataIsPresentClr := UIntToOH(unwindReadAddress, params.numEntries) } // As noted above, when starting the unwind FSM, we know the 'data' SRAM's output isn't valid, so it's safe to issue // a read command. Otherwise, only issue an SRAM read when the next 'unwindState' is 'sUnwinding', and if we know // we're not going to overwrite the SRAM's current output (the SRAM output is already valid, and it's not going to be // consumed by the output channel). val dontReadFromDataMem = unwindDataIsValid && !ioDataOut.ready dataMemReadEnable := startUnwind || (busyUnwinding && !stopUnwind && !dontReadFromDataMem) // While unwinding, prevent new reservations from overwriting the current 'map' entry that we're using. We need // 'responseListIndex' to be coherent for the entire unwind process. val rawResponseListIndex = map.read(responseIndex) val unwindResponseListIndex = RegEnable(rawResponseListIndex, startNewBurst) responseListIndex := Mux(busyUnwinding, unwindResponseListIndex, rawResponseListIndex) // Accept responses either when they can be passed through to the output channel, or if they're out-of-order and are // just going to be stashed in the 'data' SRAM. Never accept a response payload when we're busy unwinding, since that // could result in reading from and writing to the 'data' SRAM in the same cycle, and we want that SRAM to be // single-ported. ioResponse.ready := (ioDataOut.ready || !isResponseInOrder) && !busyUnwinding // Either pass an in-order response to the output channel, or data read from the unwind FSM. ioDataOut.valid := Mux(busyUnwinding, unwindDataIsValid, ioResponse.valid && isResponseInOrder) ioDataOut.bits.listIndex := responseListIndex ioDataOut.bits.payload := Mux(busyUnwinding, dataOutput, ioResponse.bits.data) // It's an error to get a response that isn't associated with a valid linked list. when(ioResponse.fire || unwindDataIsValid) { assert( valid(responseListIndex), "No linked list exists at index %d, mapped from %d", responseListIndex, responseIndex ) } when(busyUnwinding && dataMemReadEnable) { assert(isResponseInOrder, "Unwind FSM must read entries from SRAM in order") } } /** Specialized version of [[ReservableListBuffer]] for the case of numEntries == 1. * * Much of the complex logic in [[ReservableListBuffer]] can disappear in this case. For instance, we don't have to * reorder any responses, or store any linked lists. */ class PassthroughListBuffer[T <: Data](gen: T, params: ReservableListBufferParameters) extends BaseReservableListBuffer(gen, params) { require(params.numEntries == 1, s"PassthroughListBuffer is only valid when 'numEntries' (${params.numEntries}) is 1") val used = RegInit(0.U(params.numEntries.W)) val map = Mem(params.numEntries, UInt(params.listBits.W)) val usedSet = WireDefault(0.U(params.numEntries.W)) val usedClr = WireDefault(0.U(params.numEntries.W)) used := (used & ~usedClr) | usedSet ioReserve.ready := used === 0.U // Store which list index was reserved, we need to return this value when we get a response. when(ioReserve.fire) { usedSet := 1.U map.write(0.U, ioReserve.bits) } // There's only one valid linked list entry, which is at index 0. ioReservedIndex := 0.U val isLastResponseBeat = ioResponse.bits.count === ioResponse.bits.numBeats1 // Mark the linked list as empty when we get the last beat in a response. // Note that 'ioResponse.fire === ioDataOut.fire'. when(ioResponse.fire && isLastResponseBeat) { usedClr := 1.U } // Always pass the response data straight through, since we never need to reorder the response data. ioDataOut.bits.listIndex := map.read(0.U) ioDataOut.bits.payload := ioResponse.bits.data ioDataOut.valid := ioResponse.valid ioResponse.ready := ioDataOut.ready }

module dataMems_333( // @[UnsafeAXI4ToTL.scala:365:62] input [4:0] R0_addr, input R0_en, input R0_clk, output [66:0] R0_data, input [4:0] W0_addr, input W0_en, input W0_clk, input [66:0] W0_data ); dataMems_0_ext dataMems_0_ext ( // @[UnsafeAXI4ToTL.scala:365:62] .R0_addr (R0_addr), .R0_en (R0_en), .R0_clk (R0_clk), .R0_data (R0_data), .W0_addr (W0_addr), .W0_en (W0_en), .W0_clk (W0_clk), .W0_data (W0_data) ); // @[UnsafeAXI4ToTL.scala:365:62] endmodule

Generate the Verilog code corresponding to the following Chisel files. File util.scala: //****************************************************************************** // Copyright (c) 2015 - 2019, The Regents of the University of California (Regents). // All Rights Reserved. See LICENSE and LICENSE.SiFive for license details. //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ // Utility Functions //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ package boom.v3.util import chisel3._ import chisel3.util._ import freechips.rocketchip.rocket.Instructions._ import freechips.rocketchip.rocket._ import freechips.rocketchip.util.{Str} import org.chipsalliance.cde.config.{Parameters} import freechips.rocketchip.tile.{TileKey} import boom.v3.common.{MicroOp} import boom.v3.exu.{BrUpdateInfo} /** * Object to XOR fold a input register of fullLength into a compressedLength. */ object Fold { def apply(input: UInt, compressedLength: Int, fullLength: Int): UInt = { val clen = compressedLength val hlen = fullLength if (hlen <= clen) { input } else { var res = 0.U(clen.W) var remaining = input.asUInt for (i <- 0 to hlen-1 by clen) { val len = if (i + clen > hlen ) (hlen - i) else clen require(len > 0) res = res(clen-1,0) ^ remaining(len-1,0) remaining = remaining >> len.U } res } } } /** * Object to check if MicroOp was killed due to a branch mispredict. * Uses "Fast" branch masks */ object IsKilledByBranch { def apply(brupdate: BrUpdateInfo, uop: MicroOp): Bool = { return maskMatch(brupdate.b1.mispredict_mask, uop.br_mask) } def apply(brupdate: BrUpdateInfo, uop_mask: UInt): Bool = { return maskMatch(brupdate.b1.mispredict_mask, uop_mask) } } /** * Object to return new MicroOp with a new BR mask given a MicroOp mask * and old BR mask. */ object GetNewUopAndBrMask { def apply(uop: MicroOp, brupdate: BrUpdateInfo) (implicit p: Parameters): MicroOp = { val newuop = WireInit(uop) newuop.br_mask := uop.br_mask & ~brupdate.b1.resolve_mask newuop } } /** * Object to return a BR mask given a MicroOp mask and old BR mask. */ object GetNewBrMask { def apply(brupdate: BrUpdateInfo, uop: MicroOp): UInt = { return uop.br_mask & ~brupdate.b1.resolve_mask } def apply(brupdate: BrUpdateInfo, br_mask: UInt): UInt = { return br_mask & ~brupdate.b1.resolve_mask } } object UpdateBrMask { def apply(brupdate: BrUpdateInfo, uop: MicroOp): MicroOp = { val out = WireInit(uop) out.br_mask := GetNewBrMask(brupdate, uop) out } def apply[T <: boom.v3.common.HasBoomUOP](brupdate: BrUpdateInfo, bundle: T): T = { val out = WireInit(bundle) out.uop.br_mask := GetNewBrMask(brupdate, bundle.uop.br_mask) out } def apply[T <: boom.v3.common.HasBoomUOP](brupdate: BrUpdateInfo, bundle: Valid[T]): Valid[T] = { val out = WireInit(bundle) out.bits.uop.br_mask := GetNewBrMask(brupdate, bundle.bits.uop.br_mask) out.valid := bundle.valid && !IsKilledByBranch(brupdate, bundle.bits.uop.br_mask) out } } /** * Object to check if at least 1 bit matches in two masks */ object maskMatch { def apply(msk1: UInt, msk2: UInt): Bool = (msk1 & msk2) =/= 0.U } /** * Object to clear one bit in a mask given an index */ object clearMaskBit { def apply(msk: UInt, idx: UInt): UInt = (msk & ~(1.U << idx))(msk.getWidth-1, 0) } /** * Object to shift a register over by one bit and concat a new one */ object PerformShiftRegister { def apply(reg_val: UInt, new_bit: Bool): UInt = { reg_val := Cat(reg_val(reg_val.getWidth-1, 0).asUInt, new_bit.asUInt).asUInt reg_val } } /** * Object to shift a register over by one bit, wrapping the top bit around to the bottom * (XOR'ed with a new-bit), and evicting a bit at index HLEN. * This is used to simulate a longer HLEN-width shift register that is folded * down to a compressed CLEN. */ object PerformCircularShiftRegister { def apply(csr: UInt, new_bit: Bool, evict_bit: Bool, hlen: Int, clen: Int): UInt = { val carry = csr(clen-1) val newval = Cat(csr, new_bit ^ carry) ^ (evict_bit << (hlen % clen).U) newval } } /** * Object to increment an input value, wrapping it if * necessary. */ object WrapAdd { // "n" is the number of increments, so we wrap at n-1. def apply(value: UInt, amt: UInt, n: Int): UInt = { if (isPow2(n)) { (value + amt)(log2Ceil(n)-1,0) } else { val sum = Cat(0.U(1.W), value) + Cat(0.U(1.W), amt) Mux(sum >= n.U, sum - n.U, sum) } } } /** * Object to decrement an input value, wrapping it if * necessary. */ object WrapSub { // "n" is the number of increments, so we wrap to n-1. def apply(value: UInt, amt: Int, n: Int): UInt = { if (isPow2(n)) { (value - amt.U)(log2Ceil(n)-1,0) } else { val v = Cat(0.U(1.W), value) val b = Cat(0.U(1.W), amt.U) Mux(value >= amt.U, value - amt.U, n.U - amt.U + value) } } } /** * Object to increment an input value, wrapping it if * necessary. */ object WrapInc { // "n" is the number of increments, so we wrap at n-1. def apply(value: UInt, n: Int): UInt = { if (isPow2(n)) { (value + 1.U)(log2Ceil(n)-1,0) } else { val wrap = (value === (n-1).U) Mux(wrap, 0.U, value + 1.U) } } } /** * Object to decrement an input value, wrapping it if * necessary. */ object WrapDec { // "n" is the number of increments, so we wrap at n-1. def apply(value: UInt, n: Int): UInt = { if (isPow2(n)) { (value - 1.U)(log2Ceil(n)-1,0) } else { val wrap = (value === 0.U) Mux(wrap, (n-1).U, value - 1.U) } } } /** * Object to mask off lower bits of a PC to align to a "b" * Byte boundary. */ object AlignPCToBoundary { def apply(pc: UInt, b: Int): UInt = { // Invert for scenario where pc longer than b // (which would clear all bits above size(b)). ~(~pc | (b-1).U) } } /** * Object to rotate a signal left by one */ object RotateL1 { def apply(signal: UInt): UInt = { val w = signal.getWidth val out = Cat(signal(w-2,0), signal(w-1)) return out } } /** * Object to sext a value to a particular length. */ object Sext { def apply(x: UInt, length: Int): UInt = { if (x.getWidth == length) return x else return Cat(Fill(length-x.getWidth, x(x.getWidth-1)), x) } } /** * Object to translate from BOOM's special "packed immediate" to a 32b signed immediate * Asking for U-type gives it shifted up 12 bits. */ object ImmGen { import boom.v3.common.{LONGEST_IMM_SZ, IS_B, IS_I, IS_J, IS_S, IS_U} def apply(ip: UInt, isel: UInt): SInt = { val sign = ip(LONGEST_IMM_SZ-1).asSInt val i30_20 = Mux(isel === IS_U, ip(18,8).asSInt, sign) val i19_12 = Mux(isel === IS_U || isel === IS_J, ip(7,0).asSInt, sign) val i11 = Mux(isel === IS_U, 0.S, Mux(isel === IS_J || isel === IS_B, ip(8).asSInt, sign)) val i10_5 = Mux(isel === IS_U, 0.S, ip(18,14).asSInt) val i4_1 = Mux(isel === IS_U, 0.S, ip(13,9).asSInt) val i0 = Mux(isel === IS_S || isel === IS_I, ip(8).asSInt, 0.S) return Cat(sign, i30_20, i19_12, i11, i10_5, i4_1, i0).asSInt } } /** * Object to get the FP rounding mode out of a packed immediate. */ object ImmGenRm { def apply(ip: UInt): UInt = { return ip(2,0) } } /** * Object to get the FP function fype from a packed immediate. * Note: only works if !(IS_B or IS_S) */ object ImmGenTyp { def apply(ip: UInt): UInt = { return ip(9,8) } } /** * Object to see if an instruction is a JALR. */ object DebugIsJALR { def apply(inst: UInt): Bool = { // TODO Chisel not sure why this won't compile // val is_jalr = rocket.DecodeLogic(inst, List(Bool(false)), // Array( // JALR -> Bool(true))) inst(6,0) === "b1100111".U } } /** * Object to take an instruction and output its branch or jal target. Only used * for a debug assert (no where else would we jump straight from instruction * bits to a target). */ object DebugGetBJImm { def apply(inst: UInt): UInt = { // TODO Chisel not sure why this won't compile //val csignals = //rocket.DecodeLogic(inst, // List(Bool(false), Bool(false)), // Array( // BEQ -> List(Bool(true ), Bool(false)), // BNE -> List(Bool(true ), Bool(false)), // BGE -> List(Bool(true ), Bool(false)), // BGEU -> List(Bool(true ), Bool(false)), // BLT -> List(Bool(true ), Bool(false)), // BLTU -> List(Bool(true ), Bool(false)) // )) //val is_br :: nothing :: Nil = csignals val is_br = (inst(6,0) === "b1100011".U) val br_targ = Cat(Fill(12, inst(31)), Fill(8,inst(31)), inst(7), inst(30,25), inst(11,8), 0.U(1.W)) val jal_targ= Cat(Fill(12, inst(31)), inst(19,12), inst(20), inst(30,25), inst(24,21), 0.U(1.W)) Mux(is_br, br_targ, jal_targ) } } /** * Object to return the lowest bit position after the head. */ object AgePriorityEncoder { def apply(in: Seq[Bool], head: UInt): UInt = { val n = in.size val width = log2Ceil(in.size) val n_padded = 1 << width val temp_vec = (0 until n_padded).map(i => if (i < n) in(i) && i.U >= head else false.B) ++ in val idx = PriorityEncoder(temp_vec) idx(width-1, 0) //discard msb } } /** * Object to determine whether queue * index i0 is older than index i1. */ object IsOlder { def apply(i0: UInt, i1: UInt, head: UInt) = ((i0 < i1) ^ (i0 < head) ^ (i1 < head)) } /** * Set all bits at or below the highest order '1'. */ object MaskLower { def apply(in: UInt) = { val n = in.getWidth (0 until n).map(i => in >> i.U).reduce(_|_) } } /** * Set all bits at or above the lowest order '1'. */ object MaskUpper { def apply(in: UInt) = { val n = in.getWidth (0 until n).map(i => (in << i.U)(n-1,0)).reduce(_|_) } } /** * Transpose a matrix of Chisel Vecs. */ object Transpose { def apply[T <: chisel3.Data](in: Vec[Vec[T]]) = { val n = in(0).size VecInit((0 until n).map(i => VecInit(in.map(row => row(i))))) } } /** * N-wide one-hot priority encoder. */ object SelectFirstN { def apply(in: UInt, n: Int) = { val sels = Wire(Vec(n, UInt(in.getWidth.W))) var mask = in for (i <- 0 until n) { sels(i) := PriorityEncoderOH(mask) mask = mask & ~sels(i) } sels } } /** * Connect the first k of n valid input interfaces to k output interfaces. */ class Compactor[T <: chisel3.Data](n: Int, k: Int, gen: T) extends Module { require(n >= k) val io = IO(new Bundle { val in = Vec(n, Flipped(DecoupledIO(gen))) val out = Vec(k, DecoupledIO(gen)) }) if (n == k) { io.out <> io.in } else { val counts = io.in.map(_.valid).scanLeft(1.U(k.W)) ((c,e) => Mux(e, (c<<1)(k-1,0), c)) val sels = Transpose(VecInit(counts map (c => VecInit(c.asBools)))) map (col => (col zip io.in.map(_.valid)) map {case (c,v) => c && v}) val in_readys = counts map (row => (row.asBools zip io.out.map(_.ready)) map {case (c,r) => c && r} reduce (_||_)) val out_valids = sels map (col => col.reduce(_||_)) val out_data = sels map (s => Mux1H(s, io.in.map(_.bits))) in_readys zip io.in foreach {case (r,i) => i.ready := r} out_valids zip out_data zip io.out foreach {case ((v,d),o) => o.valid := v; o.bits := d} } } /** * Create a queue that can be killed with a branch kill signal. * Assumption: enq.valid only high if not killed by branch (so don't check IsKilled on io.enq). */ class BranchKillableQueue[T <: boom.v3.common.HasBoomUOP](gen: T, entries: Int, flush_fn: boom.v3.common.MicroOp => Bool = u => true.B, flow: Boolean = true) (implicit p: org.chipsalliance.cde.config.Parameters) extends boom.v3.common.BoomModule()(p) with boom.v3.common.HasBoomCoreParameters { val io = IO(new Bundle { val enq = Flipped(Decoupled(gen)) val deq = Decoupled(gen) val brupdate = Input(new BrUpdateInfo()) val flush = Input(Bool()) val empty = Output(Bool()) val count = Output(UInt(log2Ceil(entries).W)) }) val ram = Mem(entries, gen) val valids = RegInit(VecInit(Seq.fill(entries) {false.B})) val uops = Reg(Vec(entries, new MicroOp)) val enq_ptr = Counter(entries) val deq_ptr = Counter(entries) val maybe_full = RegInit(false.B) val ptr_match = enq_ptr.value === deq_ptr.value io.empty := ptr_match && !maybe_full val full = ptr_match && maybe_full val do_enq = WireInit(io.enq.fire) val do_deq = WireInit((io.deq.ready || !valids(deq_ptr.value)) && !io.empty) for (i <- 0 until entries) { val mask = uops(i).br_mask val uop = uops(i) valids(i) := valids(i) && !IsKilledByBranch(io.brupdate, mask) && !(io.flush && flush_fn(uop)) when (valids(i)) { uops(i).br_mask := GetNewBrMask(io.brupdate, mask) } } when (do_enq) { ram(enq_ptr.value) := io.enq.bits valids(enq_ptr.value) := true.B //!IsKilledByBranch(io.brupdate, io.enq.bits.uop) uops(enq_ptr.value) := io.enq.bits.uop uops(enq_ptr.value).br_mask := GetNewBrMask(io.brupdate, io.enq.bits.uop) enq_ptr.inc() } when (do_deq) { valids(deq_ptr.value) := false.B deq_ptr.inc() } when (do_enq =/= do_deq) { maybe_full := do_enq } io.enq.ready := !full val out = Wire(gen) out := ram(deq_ptr.value) out.uop := uops(deq_ptr.value) io.deq.valid := !io.empty && valids(deq_ptr.value) && !IsKilledByBranch(io.brupdate, out.uop) && !(io.flush && flush_fn(out.uop)) io.deq.bits := out io.deq.bits.uop.br_mask := GetNewBrMask(io.brupdate, out.uop) // For flow queue behavior. if (flow) { when (io.empty) { io.deq.valid := io.enq.valid //&& !IsKilledByBranch(io.brupdate, io.enq.bits.uop) io.deq.bits := io.enq.bits io.deq.bits.uop.br_mask := GetNewBrMask(io.brupdate, io.enq.bits.uop) do_deq := false.B when (io.deq.ready) { do_enq := false.B } } } private val ptr_diff = enq_ptr.value - deq_ptr.value if (isPow2(entries)) { io.count := Cat(maybe_full && ptr_match, ptr_diff) } else { io.count := Mux(ptr_match, Mux(maybe_full, entries.asUInt, 0.U), Mux(deq_ptr.value > enq_ptr.value, entries.asUInt + ptr_diff, ptr_diff)) } } // ------------------------------------------ // Printf helper functions // ------------------------------------------ object BoolToChar { /** * Take in a Chisel Bool and convert it into a Str * based on the Chars given * * @param c_bool Chisel Bool * @param trueChar Scala Char if bool is true * @param falseChar Scala Char if bool is false * @return UInt ASCII Char for "trueChar" or "falseChar" */ def apply(c_bool: Bool, trueChar: Char, falseChar: Char = '-'): UInt = { Mux(c_bool, Str(trueChar), Str(falseChar)) } } object CfiTypeToChars { /** * Get a Vec of Strs that can be used for printing * * @param cfi_type specific cfi type * @return Vec of Strs (must be indexed to get specific char) */ def apply(cfi_type: UInt) = { val strings = Seq("----", "BR ", "JAL ", "JALR") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(cfi_type) } } object BpdTypeToChars { /** * Get a Vec of Strs that can be used for printing * * @param bpd_type specific bpd type * @return Vec of Strs (must be indexed to get specific char) */ def apply(bpd_type: UInt) = { val strings = Seq("BR ", "JUMP", "----", "RET ", "----", "CALL", "----", "----") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(bpd_type) } } object RobTypeToChars { /** * Get a Vec of Strs that can be used for printing * * @param rob_type specific rob type * @return Vec of Strs (must be indexed to get specific char) */ def apply(rob_type: UInt) = { val strings = Seq("RST", "NML", "RBK", " WT") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(rob_type) } } object XRegToChars { /** * Get a Vec of Strs that can be used for printing * * @param xreg specific register number * @return Vec of Strs (must be indexed to get specific char) */ def apply(xreg: UInt) = { val strings = Seq(" x0", " ra", " sp", " gp", " tp", " t0", " t1", " t2", " s0", " s1", " a0", " a1", " a2", " a3", " a4", " a5", " a6", " a7", " s2", " s3", " s4", " s5", " s6", " s7", " s8", " s9", "s10", "s11", " t3", " t4", " t5", " t6") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(xreg) } } object FPRegToChars { /** * Get a Vec of Strs that can be used for printing * * @param fpreg specific register number * @return Vec of Strs (must be indexed to get specific char) */ def apply(fpreg: UInt) = { val strings = Seq(" ft0", " ft1", " ft2", " ft3", " ft4", " ft5", " ft6", " ft7", " fs0", " fs1", " fa0", " fa1", " fa2", " fa3", " fa4", " fa5", " fa6", " fa7", " fs2", " fs3", " fs4", " fs5", " fs6", " fs7", " fs8", " fs9", "fs10", "fs11", " ft8", " ft9", "ft10", "ft11") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(fpreg) } } object BoomCoreStringPrefix { /** * Add prefix to BOOM strings (currently only adds the hartId) * * @param strs list of strings * @return String combining the list with the prefix per line */ def apply(strs: String*)(implicit p: Parameters) = { val prefix = "[C" + s"${p(TileKey).tileId}" + "] " strs.map(str => prefix + str + "\n").mkString("") } } File consts.scala: //****************************************************************************** // Copyright (c) 2011 - 2018, The Regents of the University of California (Regents). // All Rights Reserved. See LICENSE and LICENSE.SiFive for license details. //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ // RISCV Processor Constants //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ package boom.v3.common.constants import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util.Str import freechips.rocketchip.rocket.RVCExpander /** * Mixin for issue queue types */ trait IQType { val IQT_SZ = 3 val IQT_INT = 1.U(IQT_SZ.W) val IQT_MEM = 2.U(IQT_SZ.W) val IQT_FP = 4.U(IQT_SZ.W) val IQT_MFP = 6.U(IQT_SZ.W) } /** * Mixin for scalar operation constants */ trait ScalarOpConstants { val X = BitPat("b?") val Y = BitPat("b1") val N = BitPat("b0") //************************************ // Extra Constants // Which branch predictor predicted us val BSRC_SZ = 2 val BSRC_1 = 0.U(BSRC_SZ.W) // 1-cycle branch pred val BSRC_2 = 1.U(BSRC_SZ.W) // 2-cycle branch pred val BSRC_3 = 2.U(BSRC_SZ.W) // 3-cycle branch pred val BSRC_C = 3.U(BSRC_SZ.W) // core branch resolution //************************************ // Control Signals // CFI types val CFI_SZ = 3 val CFI_X = 0.U(CFI_SZ.W) // Not a CFI instruction val CFI_BR = 1.U(CFI_SZ.W) // Branch val CFI_JAL = 2.U(CFI_SZ.W) // JAL val CFI_JALR = 3.U(CFI_SZ.W) // JALR // PC Select Signal val PC_PLUS4 = 0.U(2.W) // PC + 4 val PC_BRJMP = 1.U(2.W) // brjmp_target val PC_JALR = 2.U(2.W) // jump_reg_target // Branch Type val BR_N = 0.U(4.W) // Next val BR_NE = 1.U(4.W) // Branch on NotEqual val BR_EQ = 2.U(4.W) // Branch on Equal val BR_GE = 3.U(4.W) // Branch on Greater/Equal val BR_GEU = 4.U(4.W) // Branch on Greater/Equal Unsigned val BR_LT = 5.U(4.W) // Branch on Less Than val BR_LTU = 6.U(4.W) // Branch on Less Than Unsigned val BR_J = 7.U(4.W) // Jump val BR_JR = 8.U(4.W) // Jump Register // RS1 Operand Select Signal val OP1_RS1 = 0.U(2.W) // Register Source #1 val OP1_ZERO= 1.U(2.W) val OP1_PC = 2.U(2.W) val OP1_X = BitPat("b??") // RS2 Operand Select Signal val OP2_RS2 = 0.U(3.W) // Register Source #2 val OP2_IMM = 1.U(3.W) // immediate val OP2_ZERO= 2.U(3.W) // constant 0 val OP2_NEXT= 3.U(3.W) // constant 2/4 (for PC+2/4) val OP2_IMMC= 4.U(3.W) // for CSR imm found in RS1 val OP2_X = BitPat("b???") // Register File Write Enable Signal val REN_0 = false.B val REN_1 = true.B // Is 32b Word or 64b Doubldword? val SZ_DW = 1 val DW_X = true.B // Bool(xLen==64) val DW_32 = false.B val DW_64 = true.B val DW_XPR = true.B // Bool(xLen==64) // Memory Enable Signal val MEN_0 = false.B val MEN_1 = true.B val MEN_X = false.B // Immediate Extend Select val IS_I = 0.U(3.W) // I-Type (LD,ALU) val IS_S = 1.U(3.W) // S-Type (ST) val IS_B = 2.U(3.W) // SB-Type (BR) val IS_U = 3.U(3.W) // U-Type (LUI/AUIPC) val IS_J = 4.U(3.W) // UJ-Type (J/JAL) val IS_X = BitPat("b???") // Decode Stage Control Signals val RT_FIX = 0.U(2.W) val RT_FLT = 1.U(2.W) val RT_PAS = 3.U(2.W) // pass-through (prs1 := lrs1, etc) val RT_X = 2.U(2.W) // not-a-register (but shouldn't get a busy-bit, etc.) // TODO rename RT_NAR // Micro-op opcodes // TODO change micro-op opcodes into using enum val UOPC_SZ = 7 val uopX = BitPat.dontCare(UOPC_SZ) val uopNOP = 0.U(UOPC_SZ.W) val uopLD = 1.U(UOPC_SZ.W) val uopSTA = 2.U(UOPC_SZ.W) // store address generation val uopSTD = 3.U(UOPC_SZ.W) // store data generation val uopLUI = 4.U(UOPC_SZ.W) val uopADDI = 5.U(UOPC_SZ.W) val uopANDI = 6.U(UOPC_SZ.W) val uopORI = 7.U(UOPC_SZ.W) val uopXORI = 8.U(UOPC_SZ.W) val uopSLTI = 9.U(UOPC_SZ.W) val uopSLTIU= 10.U(UOPC_SZ.W) val uopSLLI = 11.U(UOPC_SZ.W) val uopSRAI = 12.U(UOPC_SZ.W) val uopSRLI = 13.U(UOPC_SZ.W) val uopSLL = 14.U(UOPC_SZ.W) val uopADD = 15.U(UOPC_SZ.W) val uopSUB = 16.U(UOPC_SZ.W) val uopSLT = 17.U(UOPC_SZ.W) val uopSLTU = 18.U(UOPC_SZ.W) val uopAND = 19.U(UOPC_SZ.W) val uopOR = 20.U(UOPC_SZ.W) val uopXOR = 21.U(UOPC_SZ.W) val uopSRA = 22.U(UOPC_SZ.W) val uopSRL = 23.U(UOPC_SZ.W) val uopBEQ = 24.U(UOPC_SZ.W) val uopBNE = 25.U(UOPC_SZ.W) val uopBGE = 26.U(UOPC_SZ.W) val uopBGEU = 27.U(UOPC_SZ.W) val uopBLT = 28.U(UOPC_SZ.W) val uopBLTU = 29.U(UOPC_SZ.W) val uopCSRRW= 30.U(UOPC_SZ.W) val uopCSRRS= 31.U(UOPC_SZ.W) val uopCSRRC= 32.U(UOPC_SZ.W) val uopCSRRWI=33.U(UOPC_SZ.W) val uopCSRRSI=34.U(UOPC_SZ.W) val uopCSRRCI=35.U(UOPC_SZ.W) val uopJ = 36.U(UOPC_SZ.W) val uopJAL = 37.U(UOPC_SZ.W) val uopJALR = 38.U(UOPC_SZ.W) val uopAUIPC= 39.U(UOPC_SZ.W) //val uopSRET = 40.U(UOPC_SZ.W) val uopCFLSH= 41.U(UOPC_SZ.W) val uopFENCE= 42.U(UOPC_SZ.W) val uopADDIW= 43.U(UOPC_SZ.W) val uopADDW = 44.U(UOPC_SZ.W) val uopSUBW = 45.U(UOPC_SZ.W) val uopSLLIW= 46.U(UOPC_SZ.W) val uopSLLW = 47.U(UOPC_SZ.W) val uopSRAIW= 48.U(UOPC_SZ.W) val uopSRAW = 49.U(UOPC_SZ.W) val uopSRLIW= 50.U(UOPC_SZ.W) val uopSRLW = 51.U(UOPC_SZ.W) val uopMUL = 52.U(UOPC_SZ.W) val uopMULH = 53.U(UOPC_SZ.W) val uopMULHU= 54.U(UOPC_SZ.W) val uopMULHSU=55.U(UOPC_SZ.W) val uopMULW = 56.U(UOPC_SZ.W) val uopDIV = 57.U(UOPC_SZ.W) val uopDIVU = 58.U(UOPC_SZ.W) val uopREM = 59.U(UOPC_SZ.W) val uopREMU = 60.U(UOPC_SZ.W) val uopDIVW = 61.U(UOPC_SZ.W) val uopDIVUW= 62.U(UOPC_SZ.W) val uopREMW = 63.U(UOPC_SZ.W) val uopREMUW= 64.U(UOPC_SZ.W) val uopFENCEI = 65.U(UOPC_SZ.W) // = 66.U(UOPC_SZ.W) val uopAMO_AG = 67.U(UOPC_SZ.W) // AMO-address gen (use normal STD for datagen) val uopFMV_W_X = 68.U(UOPC_SZ.W) val uopFMV_D_X = 69.U(UOPC_SZ.W) val uopFMV_X_W = 70.U(UOPC_SZ.W) val uopFMV_X_D = 71.U(UOPC_SZ.W) val uopFSGNJ_S = 72.U(UOPC_SZ.W) val uopFSGNJ_D = 73.U(UOPC_SZ.W) val uopFCVT_S_D = 74.U(UOPC_SZ.W) val uopFCVT_D_S = 75.U(UOPC_SZ.W) val uopFCVT_S_X = 76.U(UOPC_SZ.W) val uopFCVT_D_X = 77.U(UOPC_SZ.W) val uopFCVT_X_S = 78.U(UOPC_SZ.W) val uopFCVT_X_D = 79.U(UOPC_SZ.W) val uopCMPR_S = 80.U(UOPC_SZ.W) val uopCMPR_D = 81.U(UOPC_SZ.W) val uopFCLASS_S = 82.U(UOPC_SZ.W) val uopFCLASS_D = 83.U(UOPC_SZ.W) val uopFMINMAX_S = 84.U(UOPC_SZ.W) val uopFMINMAX_D = 85.U(UOPC_SZ.W) // = 86.U(UOPC_SZ.W) val uopFADD_S = 87.U(UOPC_SZ.W) val uopFSUB_S = 88.U(UOPC_SZ.W) val uopFMUL_S = 89.U(UOPC_SZ.W) val uopFADD_D = 90.U(UOPC_SZ.W) val uopFSUB_D = 91.U(UOPC_SZ.W) val uopFMUL_D = 92.U(UOPC_SZ.W) val uopFMADD_S = 93.U(UOPC_SZ.W) val uopFMSUB_S = 94.U(UOPC_SZ.W) val uopFNMADD_S = 95.U(UOPC_SZ.W) val uopFNMSUB_S = 96.U(UOPC_SZ.W) val uopFMADD_D = 97.U(UOPC_SZ.W) val uopFMSUB_D = 98.U(UOPC_SZ.W) val uopFNMADD_D = 99.U(UOPC_SZ.W) val uopFNMSUB_D = 100.U(UOPC_SZ.W) val uopFDIV_S = 101.U(UOPC_SZ.W) val uopFDIV_D = 102.U(UOPC_SZ.W) val uopFSQRT_S = 103.U(UOPC_SZ.W) val uopFSQRT_D = 104.U(UOPC_SZ.W) val uopWFI = 105.U(UOPC_SZ.W) // pass uop down the CSR pipeline val uopERET = 106.U(UOPC_SZ.W) // pass uop down the CSR pipeline, also is ERET val uopSFENCE = 107.U(UOPC_SZ.W) val uopROCC = 108.U(UOPC_SZ.W) val uopMOV = 109.U(UOPC_SZ.W) // conditional mov decoded from "add rd, x0, rs2" // The Bubble Instruction (Machine generated NOP) // Insert (XOR x0,x0,x0) which is different from software compiler // generated NOPs which are (ADDI x0, x0, 0). // Reasoning for this is to let visualizers and stat-trackers differentiate // between software NOPs and machine-generated Bubbles in the pipeline. val BUBBLE = (0x4033).U(32.W) def NullMicroOp()(implicit p: Parameters): boom.v3.common.MicroOp = { val uop = Wire(new boom.v3.common.MicroOp) uop := DontCare // Overridden in the following lines uop.uopc := uopNOP // maybe not required, but helps on asserts that try to catch spurious behavior uop.bypassable := false.B uop.fp_val := false.B uop.uses_stq := false.B uop.uses_ldq := false.B uop.pdst := 0.U uop.dst_rtype := RT_X val cs = Wire(new boom.v3.common.CtrlSignals()) cs := DontCare // Overridden in the following lines cs.br_type := BR_N cs.csr_cmd := freechips.rocketchip.rocket.CSR.N cs.is_load := false.B cs.is_sta := false.B cs.is_std := false.B uop.ctrl := cs uop } } /** * Mixin for RISCV constants */ trait RISCVConstants { // abstract out instruction decode magic numbers val RD_MSB = 11 val RD_LSB = 7 val RS1_MSB = 19 val RS1_LSB = 15 val RS2_MSB = 24 val RS2_LSB = 20 val RS3_MSB = 31 val RS3_LSB = 27 val CSR_ADDR_MSB = 31 val CSR_ADDR_LSB = 20 val CSR_ADDR_SZ = 12 // location of the fifth bit in the shamt (for checking for illegal ops for SRAIW,etc.) val SHAMT_5_BIT = 25 val LONGEST_IMM_SZ = 20 val X0 = 0.U val RA = 1.U // return address register // memory consistency model // The C/C++ atomics MCM requires that two loads to the same address maintain program order. // The Cortex A9 does NOT enforce load/load ordering (which leads to buggy behavior). val MCM_ORDER_DEPENDENT_LOADS = true val jal_opc = (0x6f).U val jalr_opc = (0x67).U def GetUop(inst: UInt): UInt = inst(6,0) def GetRd (inst: UInt): UInt = inst(RD_MSB,RD_LSB) def GetRs1(inst: UInt): UInt = inst(RS1_MSB,RS1_LSB) def ExpandRVC(inst: UInt)(implicit p: Parameters): UInt = { val rvc_exp = Module(new RVCExpander) rvc_exp.io.in := inst Mux(rvc_exp.io.rvc, rvc_exp.io.out.bits, inst) } // Note: Accepts only EXPANDED rvc instructions def ComputeBranchTarget(pc: UInt, inst: UInt, xlen: Int)(implicit p: Parameters): UInt = { val b_imm32 = Cat(Fill(20,inst(31)), inst(7), inst(30,25), inst(11,8), 0.U(1.W)) ((pc.asSInt + b_imm32.asSInt).asSInt & (-2).S).asUInt } // Note: Accepts only EXPANDED rvc instructions def ComputeJALTarget(pc: UInt, inst: UInt, xlen: Int)(implicit p: Parameters): UInt = { val j_imm32 = Cat(Fill(12,inst(31)), inst(19,12), inst(20), inst(30,25), inst(24,21), 0.U(1.W)) ((pc.asSInt + j_imm32.asSInt).asSInt & (-2).S).asUInt } // Note: Accepts only EXPANDED rvc instructions def GetCfiType(inst: UInt)(implicit p: Parameters): UInt = { val bdecode = Module(new boom.v3.exu.BranchDecode) bdecode.io.inst := inst bdecode.io.pc := 0.U bdecode.io.out.cfi_type } } /** * Mixin for exception cause constants */ trait ExcCauseConstants { // a memory disambigious misspeculation occurred val MINI_EXCEPTION_MEM_ORDERING = 16.U val MINI_EXCEPTION_CSR_REPLAY = 17.U require (!freechips.rocketchip.rocket.Causes.all.contains(16)) require (!freechips.rocketchip.rocket.Causes.all.contains(17)) } File issue-slot.scala: //****************************************************************************** // Copyright (c) 2015 - 2018, The Regents of the University of California (Regents). // All Rights Reserved. See LICENSE and LICENSE.SiFive for license details. //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ // RISCV Processor Issue Slot Logic //-------------------------------------------------------------------------- //------------------------------------------------------------------------------ // // Note: stores (and AMOs) are "broken down" into 2 uops, but stored within a single issue-slot. // TODO XXX make a separate issueSlot for MemoryIssueSlots, and only they break apart stores. // TODO Disable ldspec for FP queue. package boom.v3.exu import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.Parameters import boom.v3.common._ import boom.v3.util._ import FUConstants._ /** * IO bundle to interact with Issue slot * * @param numWakeupPorts number of wakeup ports for the slot */ class IssueSlotIO(val numWakeupPorts: Int)(implicit p: Parameters) extends BoomBundle { val valid = Output(Bool()) val will_be_valid = Output(Bool()) // TODO code review, do we need this signal so explicitely? val request = Output(Bool()) val request_hp = Output(Bool()) val grant = Input(Bool()) val brupdate = Input(new BrUpdateInfo()) val kill = Input(Bool()) // pipeline flush val clear = Input(Bool()) // entry being moved elsewhere (not mutually exclusive with grant) val ldspec_miss = Input(Bool()) // Previous cycle's speculative load wakeup was mispredicted. val wakeup_ports = Flipped(Vec(numWakeupPorts, Valid(new IqWakeup(maxPregSz)))) val pred_wakeup_port = Flipped(Valid(UInt(log2Ceil(ftqSz).W))) val spec_ld_wakeup = Flipped(Vec(memWidth, Valid(UInt(width=maxPregSz.W)))) val in_uop = Flipped(Valid(new MicroOp())) // if valid, this WILL overwrite an entry! val out_uop = Output(new MicroOp()) // the updated slot uop; will be shifted upwards in a collasping queue. val uop = Output(new MicroOp()) // the current Slot's uop. Sent down the pipeline when issued. val debug = { val result = new Bundle { val p1 = Bool() val p2 = Bool() val p3 = Bool() val ppred = Bool() val state = UInt(width=2.W) } Output(result) } } /** * Single issue slot. Holds a uop within the issue queue * * @param numWakeupPorts number of wakeup ports */ class IssueSlot(val numWakeupPorts: Int)(implicit p: Parameters) extends BoomModule with IssueUnitConstants { val io = IO(new IssueSlotIO(numWakeupPorts)) // slot invalid? // slot is valid, holding 1 uop // slot is valid, holds 2 uops (like a store) def is_invalid = state === s_invalid def is_valid = state =/= s_invalid val next_state = Wire(UInt()) // the next state of this slot (which might then get moved to a new slot) val next_uopc = Wire(UInt()) // the next uopc of this slot (which might then get moved to a new slot) val next_lrs1_rtype = Wire(UInt()) // the next reg type of this slot (which might then get moved to a new slot) val next_lrs2_rtype = Wire(UInt()) // the next reg type of this slot (which might then get moved to a new slot) val state = RegInit(s_invalid) val p1 = RegInit(false.B) val p2 = RegInit(false.B) val p3 = RegInit(false.B) val ppred = RegInit(false.B) // Poison if woken up by speculative load. // Poison lasts 1 cycle (as ldMiss will come on the next cycle). // SO if poisoned is true, set it to false! val p1_poisoned = RegInit(false.B) val p2_poisoned = RegInit(false.B) p1_poisoned := false.B p2_poisoned := false.B val next_p1_poisoned = Mux(io.in_uop.valid, io.in_uop.bits.iw_p1_poisoned, p1_poisoned) val next_p2_poisoned = Mux(io.in_uop.valid, io.in_uop.bits.iw_p2_poisoned, p2_poisoned) val slot_uop = RegInit(NullMicroOp) val next_uop = Mux(io.in_uop.valid, io.in_uop.bits, slot_uop) //----------------------------------------------------------------------------- // next slot state computation // compute the next state for THIS entry slot (in a collasping queue, the // current uop may get moved elsewhere, and a new uop can enter when (io.kill) { state := s_invalid } .elsewhen (io.in_uop.valid) { state := io.in_uop.bits.iw_state } .elsewhen (io.clear) { state := s_invalid } .otherwise { state := next_state } //----------------------------------------------------------------------------- // "update" state // compute the next state for the micro-op in this slot. This micro-op may // be moved elsewhere, so the "next_state" travels with it. // defaults next_state := state next_uopc := slot_uop.uopc next_lrs1_rtype := slot_uop.lrs1_rtype next_lrs2_rtype := slot_uop.lrs2_rtype when (io.kill) { next_state := s_invalid } .elsewhen ((io.grant && (state === s_valid_1)) || (io.grant && (state === s_valid_2) && p1 && p2 && ppred)) { // try to issue this uop. when (!(io.ldspec_miss && (p1_poisoned || p2_poisoned))) { next_state := s_invalid } } .elsewhen (io.grant && (state === s_valid_2)) { when (!(io.ldspec_miss && (p1_poisoned || p2_poisoned))) { next_state := s_valid_1 when (p1) { slot_uop.uopc := uopSTD next_uopc := uopSTD slot_uop.lrs1_rtype := RT_X next_lrs1_rtype := RT_X } .otherwise { slot_uop.lrs2_rtype := RT_X next_lrs2_rtype := RT_X } } } when (io.in_uop.valid) { slot_uop := io.in_uop.bits assert (is_invalid || io.clear || io.kill, "trying to overwrite a valid issue slot.") } // Wakeup Compare Logic // these signals are the "next_p*" for the current slot's micro-op. // they are important for shifting the current slot_uop up to an other entry. val next_p1 = WireInit(p1) val next_p2 = WireInit(p2) val next_p3 = WireInit(p3) val next_ppred = WireInit(ppred) when (io.in_uop.valid) { p1 := !(io.in_uop.bits.prs1_busy) p2 := !(io.in_uop.bits.prs2_busy) p3 := !(io.in_uop.bits.prs3_busy) ppred := !(io.in_uop.bits.ppred_busy) } when (io.ldspec_miss && next_p1_poisoned) { assert(next_uop.prs1 =/= 0.U, "Poison bit can't be set for prs1=x0!") p1 := false.B } when (io.ldspec_miss && next_p2_poisoned) { assert(next_uop.prs2 =/= 0.U, "Poison bit can't be set for prs2=x0!") p2 := false.B } for (i <- 0 until numWakeupPorts) { when (io.wakeup_ports(i).valid && (io.wakeup_ports(i).bits.pdst === next_uop.prs1)) { p1 := true.B } when (io.wakeup_ports(i).valid && (io.wakeup_ports(i).bits.pdst === next_uop.prs2)) { p2 := true.B } when (io.wakeup_ports(i).valid && (io.wakeup_ports(i).bits.pdst === next_uop.prs3)) { p3 := true.B } } when (io.pred_wakeup_port.valid && io.pred_wakeup_port.bits === next_uop.ppred) { ppred := true.B } for (w <- 0 until memWidth) { assert (!(io.spec_ld_wakeup(w).valid && io.spec_ld_wakeup(w).bits === 0.U), "Loads to x0 should never speculatively wakeup other instructions") } // TODO disable if FP IQ. for (w <- 0 until memWidth) { when (io.spec_ld_wakeup(w).valid && io.spec_ld_wakeup(w).bits === next_uop.prs1 && next_uop.lrs1_rtype === RT_FIX) { p1 := true.B p1_poisoned := true.B assert (!next_p1_poisoned) } when (io.spec_ld_wakeup(w).valid && io.spec_ld_wakeup(w).bits === next_uop.prs2 && next_uop.lrs2_rtype === RT_FIX) { p2 := true.B p2_poisoned := true.B assert (!next_p2_poisoned) } } // Handle branch misspeculations val next_br_mask = GetNewBrMask(io.brupdate, slot_uop) // was this micro-op killed by a branch? if yes, we can't let it be valid if // we compact it into an other entry when (IsKilledByBranch(io.brupdate, slot_uop)) { next_state := s_invalid } when (!io.in_uop.valid) { slot_uop.br_mask := next_br_mask } //------------------------------------------------------------- // Request Logic io.request := is_valid && p1 && p2 && p3 && ppred && !io.kill val high_priority = slot_uop.is_br || slot_uop.is_jal || slot_uop.is_jalr io.request_hp := io.request && high_priority when (state === s_valid_1) { io.request := p1 && p2 && p3 && ppred && !io.kill } .elsewhen (state === s_valid_2) { io.request := (p1 || p2) && ppred && !io.kill } .otherwise { io.request := false.B } //assign outputs io.valid := is_valid io.uop := slot_uop io.uop.iw_p1_poisoned := p1_poisoned io.uop.iw_p2_poisoned := p2_poisoned // micro-op will vacate due to grant. val may_vacate = io.grant && ((state === s_valid_1) || (state === s_valid_2) && p1 && p2 && ppred) val squash_grant = io.ldspec_miss && (p1_poisoned || p2_poisoned) io.will_be_valid := is_valid && !(may_vacate && !squash_grant) io.out_uop := slot_uop io.out_uop.iw_state := next_state io.out_uop.uopc := next_uopc io.out_uop.lrs1_rtype := next_lrs1_rtype io.out_uop.lrs2_rtype := next_lrs2_rtype io.out_uop.br_mask := next_br_mask io.out_uop.prs1_busy := !p1 io.out_uop.prs2_busy := !p2 io.out_uop.prs3_busy := !p3 io.out_uop.ppred_busy := !ppred io.out_uop.iw_p1_poisoned := p1_poisoned io.out_uop.iw_p2_poisoned := p2_poisoned when (state === s_valid_2) { when (p1 && p2 && ppred) { ; // send out the entire instruction as one uop } .elsewhen (p1 && ppred) { io.uop.uopc := slot_uop.uopc io.uop.lrs2_rtype := RT_X } .elsewhen (p2 && ppred) { io.uop.uopc := uopSTD io.uop.lrs1_rtype := RT_X } } // debug outputs io.debug.p1 := p1 io.debug.p2 := p2 io.debug.p3 := p3 io.debug.ppred := ppred io.debug.state := state }

module IssueSlot_36( // @[issue-slot.scala:69:7] input clock, // @[issue-slot.scala:69:7] input reset, // @[issue-slot.scala:69:7] output io_valid, // @[issue-slot.scala:73:14] output io_will_be_valid, // @[issue-slot.scala:73:14] output io_request, // @[issue-slot.scala:73:14] output io_request_hp, // @[issue-slot.scala:73:14] input io_grant, // @[issue-slot.scala:73:14] input [7:0] io_brupdate_b1_resolve_mask, // @[issue-slot.scala:73:14] input [7:0] io_brupdate_b1_mispredict_mask, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_uopc, // @[issue-slot.scala:73:14] input [31:0] io_brupdate_b2_uop_inst, // @[issue-slot.scala:73:14] input [31:0] io_brupdate_b2_uop_debug_inst, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_rvc, // @[issue-slot.scala:73:14] input [39:0] io_brupdate_b2_uop_debug_pc, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_uop_iq_type, // @[issue-slot.scala:73:14] input [9:0] io_brupdate_b2_uop_fu_code, // @[issue-slot.scala:73:14] input [3:0] io_brupdate_b2_uop_ctrl_br_type, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_ctrl_op1_sel, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_uop_ctrl_op2_sel, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_uop_ctrl_imm_sel, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_ctrl_op_fcn, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ctrl_fcn_dw, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_uop_ctrl_csr_cmd, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ctrl_is_load, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ctrl_is_sta, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ctrl_is_std, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_iw_state, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_iw_p1_poisoned, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_iw_p2_poisoned, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_br, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_jalr, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_jal, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_sfb, // @[issue-slot.scala:73:14] input [7:0] io_brupdate_b2_uop_br_mask, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_uop_br_tag, // @[issue-slot.scala:73:14] input [3:0] io_brupdate_b2_uop_ftq_idx, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_edge_inst, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_pc_lob, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_taken, // @[issue-slot.scala:73:14] input [19:0] io_brupdate_b2_uop_imm_packed, // @[issue-slot.scala:73:14] input [11:0] io_brupdate_b2_uop_csr_addr, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_rob_idx, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_uop_ldq_idx, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_uop_stq_idx, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_rxq_idx, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_pdst, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_prs1, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_prs2, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_prs3, // @[issue-slot.scala:73:14] input [3:0] io_brupdate_b2_uop_ppred, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_prs1_busy, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_prs2_busy, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_prs3_busy, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ppred_busy, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_stale_pdst, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_exception, // @[issue-slot.scala:73:14] input [63:0] io_brupdate_b2_uop_exc_cause, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_bypassable, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_mem_cmd, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_mem_size, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_mem_signed, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_fence, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_fencei, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_amo, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_uses_ldq, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_uses_stq, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_sys_pc2epc, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_unique, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_flush_on_commit, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ldst_is_rs1, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_ldst, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_lrs1, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_lrs2, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_lrs3, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ldst_val, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_dst_rtype, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_lrs1_rtype, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_lrs2_rtype, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_frs3_en, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_fp_val, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_fp_single, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_xcpt_pf_if, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_xcpt_ae_if, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_xcpt_ma_if, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_bp_debug_if, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_bp_xcpt_if, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_debug_fsrc, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_debug_tsrc, // @[issue-slot.scala:73:14] input io_brupdate_b2_valid, // @[issue-slot.scala:73:14] input io_brupdate_b2_mispredict, // @[issue-slot.scala:73:14] input io_brupdate_b2_taken, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_cfi_type, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_pc_sel, // @[issue-slot.scala:73:14] input [39:0] io_brupdate_b2_jalr_target, // @[issue-slot.scala:73:14] input [20:0] io_brupdate_b2_target_offset, // @[issue-slot.scala:73:14] input io_kill, // @[issue-slot.scala:73:14] input io_clear, // @[issue-slot.scala:73:14] input io_ldspec_miss, // @[issue-slot.scala:73:14] input io_wakeup_ports_0_valid, // @[issue-slot.scala:73:14] input [5:0] io_wakeup_ports_0_bits_pdst, // @[issue-slot.scala:73:14] input io_wakeup_ports_0_bits_poisoned, // @[issue-slot.scala:73:14] input io_wakeup_ports_1_valid, // @[issue-slot.scala:73:14] input [5:0] io_wakeup_ports_1_bits_pdst, // @[issue-slot.scala:73:14] input io_wakeup_ports_1_bits_poisoned, // @[issue-slot.scala:73:14] input io_wakeup_ports_2_valid, // @[issue-slot.scala:73:14] input [5:0] io_wakeup_ports_2_bits_pdst, // @[issue-slot.scala:73:14] input io_wakeup_ports_2_bits_poisoned, // @[issue-slot.scala:73:14] input io_spec_ld_wakeup_0_valid, // @[issue-slot.scala:73:14] input [5:0] io_spec_ld_wakeup_0_bits, // @[issue-slot.scala:73:14] input io_in_uop_valid, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_uopc, // @[issue-slot.scala:73:14] input [31:0] io_in_uop_bits_inst, // @[issue-slot.scala:73:14] input [31:0] io_in_uop_bits_debug_inst, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_rvc, // @[issue-slot.scala:73:14] input [39:0] io_in_uop_bits_debug_pc, // @[issue-slot.scala:73:14] input [2:0] io_in_uop_bits_iq_type, // @[issue-slot.scala:73:14] input [9:0] io_in_uop_bits_fu_code, // @[issue-slot.scala:73:14] input [3:0] io_in_uop_bits_ctrl_br_type, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_ctrl_op1_sel, // @[issue-slot.scala:73:14] input [2:0] io_in_uop_bits_ctrl_op2_sel, // @[issue-slot.scala:73:14] input [2:0] io_in_uop_bits_ctrl_imm_sel, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_ctrl_op_fcn, // @[issue-slot.scala:73:14] input io_in_uop_bits_ctrl_fcn_dw, // @[issue-slot.scala:73:14] input [2:0] io_in_uop_bits_ctrl_csr_cmd, // @[issue-slot.scala:73:14] input io_in_uop_bits_ctrl_is_load, // @[issue-slot.scala:73:14] input io_in_uop_bits_ctrl_is_sta, // @[issue-slot.scala:73:14] input io_in_uop_bits_ctrl_is_std, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_iw_state, // @[issue-slot.scala:73:14] input io_in_uop_bits_iw_p1_poisoned, // @[issue-slot.scala:73:14] input io_in_uop_bits_iw_p2_poisoned, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_br, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_jalr, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_jal, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_sfb, // @[issue-slot.scala:73:14] input [7:0] io_in_uop_bits_br_mask, // @[issue-slot.scala:73:14] input [2:0] io_in_uop_bits_br_tag, // @[issue-slot.scala:73:14] input [3:0] io_in_uop_bits_ftq_idx, // @[issue-slot.scala:73:14] input io_in_uop_bits_edge_inst, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_pc_lob, // @[issue-slot.scala:73:14] input io_in_uop_bits_taken, // @[issue-slot.scala:73:14] input [19:0] io_in_uop_bits_imm_packed, // @[issue-slot.scala:73:14] input [11:0] io_in_uop_bits_csr_addr, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_rob_idx, // @[issue-slot.scala:73:14] input [2:0] io_in_uop_bits_ldq_idx, // @[issue-slot.scala:73:14] input [2:0] io_in_uop_bits_stq_idx, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_rxq_idx, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_pdst, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_prs1, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_prs2, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_prs3, // @[issue-slot.scala:73:14] input [3:0] io_in_uop_bits_ppred, // @[issue-slot.scala:73:14] input io_in_uop_bits_prs1_busy, // @[issue-slot.scala:73:14] input io_in_uop_bits_prs2_busy, // @[issue-slot.scala:73:14] input io_in_uop_bits_prs3_busy, // @[issue-slot.scala:73:14] input io_in_uop_bits_ppred_busy, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_stale_pdst, // @[issue-slot.scala:73:14] input io_in_uop_bits_exception, // @[issue-slot.scala:73:14] input [63:0] io_in_uop_bits_exc_cause, // @[issue-slot.scala:73:14] input io_in_uop_bits_bypassable, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_mem_cmd, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_mem_size, // @[issue-slot.scala:73:14] input io_in_uop_bits_mem_signed, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_fence, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_fencei, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_amo, // @[issue-slot.scala:73:14] input io_in_uop_bits_uses_ldq, // @[issue-slot.scala:73:14] input io_in_uop_bits_uses_stq, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_sys_pc2epc, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_unique, // @[issue-slot.scala:73:14] input io_in_uop_bits_flush_on_commit, // @[issue-slot.scala:73:14] input io_in_uop_bits_ldst_is_rs1, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_ldst, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_lrs1, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_lrs2, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_lrs3, // @[issue-slot.scala:73:14] input io_in_uop_bits_ldst_val, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_dst_rtype, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_lrs1_rtype, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_lrs2_rtype, // @[issue-slot.scala:73:14] input io_in_uop_bits_frs3_en, // @[issue-slot.scala:73:14] input io_in_uop_bits_fp_val, // @[issue-slot.scala:73:14] input io_in_uop_bits_fp_single, // @[issue-slot.scala:73:14] input io_in_uop_bits_xcpt_pf_if, // @[issue-slot.scala:73:14] input io_in_uop_bits_xcpt_ae_if, // @[issue-slot.scala:73:14] input io_in_uop_bits_xcpt_ma_if, // @[issue-slot.scala:73:14] input io_in_uop_bits_bp_debug_if, // @[issue-slot.scala:73:14] input io_in_uop_bits_bp_xcpt_if, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_debug_fsrc, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_debug_tsrc, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_uopc, // @[issue-slot.scala:73:14] output [31:0] io_out_uop_inst, // @[issue-slot.scala:73:14] output [31:0] io_out_uop_debug_inst, // @[issue-slot.scala:73:14] output io_out_uop_is_rvc, // @[issue-slot.scala:73:14] output [39:0] io_out_uop_debug_pc, // @[issue-slot.scala:73:14] output [2:0] io_out_uop_iq_type, // @[issue-slot.scala:73:14] output [9:0] io_out_uop_fu_code, // @[issue-slot.scala:73:14] output [3:0] io_out_uop_ctrl_br_type, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_ctrl_op1_sel, // @[issue-slot.scala:73:14] output [2:0] io_out_uop_ctrl_op2_sel, // @[issue-slot.scala:73:14] output [2:0] io_out_uop_ctrl_imm_sel, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_ctrl_op_fcn, // @[issue-slot.scala:73:14] output io_out_uop_ctrl_fcn_dw, // @[issue-slot.scala:73:14] output [2:0] io_out_uop_ctrl_csr_cmd, // @[issue-slot.scala:73:14] output io_out_uop_ctrl_is_load, // @[issue-slot.scala:73:14] output io_out_uop_ctrl_is_sta, // @[issue-slot.scala:73:14] output io_out_uop_ctrl_is_std, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_iw_state, // @[issue-slot.scala:73:14] output io_out_uop_iw_p1_poisoned, // @[issue-slot.scala:73:14] output io_out_uop_iw_p2_poisoned, // @[issue-slot.scala:73:14] output io_out_uop_is_br, // @[issue-slot.scala:73:14] output io_out_uop_is_jalr, // @[issue-slot.scala:73:14] output io_out_uop_is_jal, // @[issue-slot.scala:73:14] output io_out_uop_is_sfb, // @[issue-slot.scala:73:14] output [7:0] io_out_uop_br_mask, // @[issue-slot.scala:73:14] output [2:0] io_out_uop_br_tag, // @[issue-slot.scala:73:14] output [3:0] io_out_uop_ftq_idx, // @[issue-slot.scala:73:14] output io_out_uop_edge_inst, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_pc_lob, // @[issue-slot.scala:73:14] output io_out_uop_taken, // @[issue-slot.scala:73:14] output [19:0] io_out_uop_imm_packed, // @[issue-slot.scala:73:14] output [11:0] io_out_uop_csr_addr, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_rob_idx, // @[issue-slot.scala:73:14] output [2:0] io_out_uop_ldq_idx, // @[issue-slot.scala:73:14] output [2:0] io_out_uop_stq_idx, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_rxq_idx, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_pdst, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_prs1, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_prs2, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_prs3, // @[issue-slot.scala:73:14] output [3:0] io_out_uop_ppred, // @[issue-slot.scala:73:14] output io_out_uop_prs1_busy, // @[issue-slot.scala:73:14] output io_out_uop_prs2_busy, // @[issue-slot.scala:73:14] output io_out_uop_prs3_busy, // @[issue-slot.scala:73:14] output io_out_uop_ppred_busy, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_stale_pdst, // @[issue-slot.scala:73:14] output io_out_uop_exception, // @[issue-slot.scala:73:14] output [63:0] io_out_uop_exc_cause, // @[issue-slot.scala:73:14] output io_out_uop_bypassable, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_mem_cmd, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_mem_size, // @[issue-slot.scala:73:14] output io_out_uop_mem_signed, // @[issue-slot.scala:73:14] output io_out_uop_is_fence, // @[issue-slot.scala:73:14] output io_out_uop_is_fencei, // @[issue-slot.scala:73:14] output io_out_uop_is_amo, // @[issue-slot.scala:73:14] output io_out_uop_uses_ldq, // @[issue-slot.scala:73:14] output io_out_uop_uses_stq, // @[issue-slot.scala:73:14] output io_out_uop_is_sys_pc2epc, // @[issue-slot.scala:73:14] output io_out_uop_is_unique, // @[issue-slot.scala:73:14] output io_out_uop_flush_on_commit, // @[issue-slot.scala:73:14] output io_out_uop_ldst_is_rs1, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_ldst, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_lrs1, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_lrs2, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_lrs3, // @[issue-slot.scala:73:14] output io_out_uop_ldst_val, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_dst_rtype, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_lrs1_rtype, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_lrs2_rtype, // @[issue-slot.scala:73:14] output io_out_uop_frs3_en, // @[issue-slot.scala:73:14] output io_out_uop_fp_val, // @[issue-slot.scala:73:14] output io_out_uop_fp_single, // @[issue-slot.scala:73:14] output io_out_uop_xcpt_pf_if, // @[issue-slot.scala:73:14] output io_out_uop_xcpt_ae_if, // @[issue-slot.scala:73:14] output io_out_uop_xcpt_ma_if, // @[issue-slot.scala:73:14] output io_out_uop_bp_debug_if, // @[issue-slot.scala:73:14] output io_out_uop_bp_xcpt_if, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_debug_fsrc, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_debug_tsrc, // @[issue-slot.scala:73:14] output [6:0] io_uop_uopc, // @[issue-slot.scala:73:14] output [31:0] io_uop_inst, // @[issue-slot.scala:73:14] output [31:0] io_uop_debug_inst, // @[issue-slot.scala:73:14] output io_uop_is_rvc, // @[issue-slot.scala:73:14] output [39:0] io_uop_debug_pc, // @[issue-slot.scala:73:14] output [2:0] io_uop_iq_type, // @[issue-slot.scala:73:14] output [9:0] io_uop_fu_code, // @[issue-slot.scala:73:14] output [3:0] io_uop_ctrl_br_type, // @[issue-slot.scala:73:14] output [1:0] io_uop_ctrl_op1_sel, // @[issue-slot.scala:73:14] output [2:0] io_uop_ctrl_op2_sel, // @[issue-slot.scala:73:14] output [2:0] io_uop_ctrl_imm_sel, // @[issue-slot.scala:73:14] output [4:0] io_uop_ctrl_op_fcn, // @[issue-slot.scala:73:14] output io_uop_ctrl_fcn_dw, // @[issue-slot.scala:73:14] output [2:0] io_uop_ctrl_csr_cmd, // @[issue-slot.scala:73:14] output io_uop_ctrl_is_load, // @[issue-slot.scala:73:14] output io_uop_ctrl_is_sta, // @[issue-slot.scala:73:14] output io_uop_ctrl_is_std, // @[issue-slot.scala:73:14] output [1:0] io_uop_iw_state, // @[issue-slot.scala:73:14] output io_uop_iw_p1_poisoned, // @[issue-slot.scala:73:14] output io_uop_iw_p2_poisoned, // @[issue-slot.scala:73:14] output io_uop_is_br, // @[issue-slot.scala:73:14] output io_uop_is_jalr, // @[issue-slot.scala:73:14] output io_uop_is_jal, // @[issue-slot.scala:73:14] output io_uop_is_sfb, // @[issue-slot.scala:73:14] output [7:0] io_uop_br_mask, // @[issue-slot.scala:73:14] output [2:0] io_uop_br_tag, // @[issue-slot.scala:73:14] output [3:0] io_uop_ftq_idx, // @[issue-slot.scala:73:14] output io_uop_edge_inst, // @[issue-slot.scala:73:14] output [5:0] io_uop_pc_lob, // @[issue-slot.scala:73:14] output io_uop_taken, // @[issue-slot.scala:73:14] output [19:0] io_uop_imm_packed, // @[issue-slot.scala:73:14] output [11:0] io_uop_csr_addr, // @[issue-slot.scala:73:14] output [4:0] io_uop_rob_idx, // @[issue-slot.scala:73:14] output [2:0] io_uop_ldq_idx, // @[issue-slot.scala:73:14] output [2:0] io_uop_stq_idx, // @[issue-slot.scala:73:14] output [1:0] io_uop_rxq_idx, // @[issue-slot.scala:73:14] output [5:0] io_uop_pdst, // @[issue-slot.scala:73:14] output [5:0] io_uop_prs1, // @[issue-slot.scala:73:14] output [5:0] io_uop_prs2, // @[issue-slot.scala:73:14] output [5:0] io_uop_prs3, // @[issue-slot.scala:73:14] output [3:0] io_uop_ppred, // @[issue-slot.scala:73:14] output io_uop_prs1_busy, // @[issue-slot.scala:73:14] output io_uop_prs2_busy, // @[issue-slot.scala:73:14] output io_uop_prs3_busy, // @[issue-slot.scala:73:14] output io_uop_ppred_busy, // @[issue-slot.scala:73:14] output [5:0] io_uop_stale_pdst, // @[issue-slot.scala:73:14] output io_uop_exception, // @[issue-slot.scala:73:14] output [63:0] io_uop_exc_cause, // @[issue-slot.scala:73:14] output io_uop_bypassable, // @[issue-slot.scala:73:14] output [4:0] io_uop_mem_cmd, // @[issue-slot.scala:73:14] output [1:0] io_uop_mem_size, // @[issue-slot.scala:73:14] output io_uop_mem_signed, // @[issue-slot.scala:73:14] output io_uop_is_fence, // @[issue-slot.scala:73:14] output io_uop_is_fencei, // @[issue-slot.scala:73:14] output io_uop_is_amo, // @[issue-slot.scala:73:14] output io_uop_uses_ldq, // @[issue-slot.scala:73:14] output io_uop_uses_stq, // @[issue-slot.scala:73:14] output io_uop_is_sys_pc2epc, // @[issue-slot.scala:73:14] output io_uop_is_unique, // @[issue-slot.scala:73:14] output io_uop_flush_on_commit, // @[issue-slot.scala:73:14] output io_uop_ldst_is_rs1, // @[issue-slot.scala:73:14] output [5:0] io_uop_ldst, // @[issue-slot.scala:73:14] output [5:0] io_uop_lrs1, // @[issue-slot.scala:73:14] output [5:0] io_uop_lrs2, // @[issue-slot.scala:73:14] output [5:0] io_uop_lrs3, // @[issue-slot.scala:73:14] output io_uop_ldst_val, // @[issue-slot.scala:73:14] output [1:0] io_uop_dst_rtype, // @[issue-slot.scala:73:14] output [1:0] io_uop_lrs1_rtype, // @[issue-slot.scala:73:14] output [1:0] io_uop_lrs2_rtype, // @[issue-slot.scala:73:14] output io_uop_frs3_en, // @[issue-slot.scala:73:14] output io_uop_fp_val, // @[issue-slot.scala:73:14] output io_uop_fp_single, // @[issue-slot.scala:73:14] output io_uop_xcpt_pf_if, // @[issue-slot.scala:73:14] output io_uop_xcpt_ae_if, // @[issue-slot.scala:73:14] output io_uop_xcpt_ma_if, // @[issue-slot.scala:73:14] output io_uop_bp_debug_if, // @[issue-slot.scala:73:14] output io_uop_bp_xcpt_if, // @[issue-slot.scala:73:14] output [1:0] io_uop_debug_fsrc, // @[issue-slot.scala:73:14] output [1:0] io_uop_debug_tsrc, // @[issue-slot.scala:73:14] output io_debug_p1, // @[issue-slot.scala:73:14] output io_debug_p2, // @[issue-slot.scala:73:14] output io_debug_p3, // @[issue-slot.scala:73:14] output io_debug_ppred, // @[issue-slot.scala:73:14] output [1:0] io_debug_state // @[issue-slot.scala:73:14] ); wire io_grant_0 = io_grant; // @[issue-slot.scala:69:7] wire [7:0] io_brupdate_b1_resolve_mask_0 = io_brupdate_b1_resolve_mask; // @[issue-slot.scala:69:7] wire [7:0] io_brupdate_b1_mispredict_mask_0 = io_brupdate_b1_mispredict_mask; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_uopc_0 = io_brupdate_b2_uop_uopc; // @[issue-slot.scala:69:7] wire [31:0] io_brupdate_b2_uop_inst_0 = io_brupdate_b2_uop_inst; // @[issue-slot.scala:69:7] wire [31:0] io_brupdate_b2_uop_debug_inst_0 = io_brupdate_b2_uop_debug_inst; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_rvc_0 = io_brupdate_b2_uop_is_rvc; // @[issue-slot.scala:69:7] wire [39:0] io_brupdate_b2_uop_debug_pc_0 = io_brupdate_b2_uop_debug_pc; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_uop_iq_type_0 = io_brupdate_b2_uop_iq_type; // @[issue-slot.scala:69:7] wire [9:0] io_brupdate_b2_uop_fu_code_0 = io_brupdate_b2_uop_fu_code; // @[issue-slot.scala:69:7] wire [3:0] io_brupdate_b2_uop_ctrl_br_type_0 = io_brupdate_b2_uop_ctrl_br_type; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_ctrl_op1_sel_0 = io_brupdate_b2_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_uop_ctrl_op2_sel_0 = io_brupdate_b2_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_uop_ctrl_imm_sel_0 = io_brupdate_b2_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_ctrl_op_fcn_0 = io_brupdate_b2_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ctrl_fcn_dw_0 = io_brupdate_b2_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_uop_ctrl_csr_cmd_0 = io_brupdate_b2_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ctrl_is_load_0 = io_brupdate_b2_uop_ctrl_is_load; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ctrl_is_sta_0 = io_brupdate_b2_uop_ctrl_is_sta; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ctrl_is_std_0 = io_brupdate_b2_uop_ctrl_is_std; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_iw_state_0 = io_brupdate_b2_uop_iw_state; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_iw_p1_poisoned_0 = io_brupdate_b2_uop_iw_p1_poisoned; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_iw_p2_poisoned_0 = io_brupdate_b2_uop_iw_p2_poisoned; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_br_0 = io_brupdate_b2_uop_is_br; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_jalr_0 = io_brupdate_b2_uop_is_jalr; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_jal_0 = io_brupdate_b2_uop_is_jal; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_sfb_0 = io_brupdate_b2_uop_is_sfb; // @[issue-slot.scala:69:7] wire [7:0] io_brupdate_b2_uop_br_mask_0 = io_brupdate_b2_uop_br_mask; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_uop_br_tag_0 = io_brupdate_b2_uop_br_tag; // @[issue-slot.scala:69:7] wire [3:0] io_brupdate_b2_uop_ftq_idx_0 = io_brupdate_b2_uop_ftq_idx; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_edge_inst_0 = io_brupdate_b2_uop_edge_inst; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_pc_lob_0 = io_brupdate_b2_uop_pc_lob; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_taken_0 = io_brupdate_b2_uop_taken; // @[issue-slot.scala:69:7] wire [19:0] io_brupdate_b2_uop_imm_packed_0 = io_brupdate_b2_uop_imm_packed; // @[issue-slot.scala:69:7] wire [11:0] io_brupdate_b2_uop_csr_addr_0 = io_brupdate_b2_uop_csr_addr; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_rob_idx_0 = io_brupdate_b2_uop_rob_idx; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_uop_ldq_idx_0 = io_brupdate_b2_uop_ldq_idx; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_uop_stq_idx_0 = io_brupdate_b2_uop_stq_idx; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_rxq_idx_0 = io_brupdate_b2_uop_rxq_idx; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_pdst_0 = io_brupdate_b2_uop_pdst; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_prs1_0 = io_brupdate_b2_uop_prs1; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_prs2_0 = io_brupdate_b2_uop_prs2; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_prs3_0 = io_brupdate_b2_uop_prs3; // @[issue-slot.scala:69:7] wire [3:0] io_brupdate_b2_uop_ppred_0 = io_brupdate_b2_uop_ppred; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_prs1_busy_0 = io_brupdate_b2_uop_prs1_busy; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_prs2_busy_0 = io_brupdate_b2_uop_prs2_busy; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_prs3_busy_0 = io_brupdate_b2_uop_prs3_busy; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ppred_busy_0 = io_brupdate_b2_uop_ppred_busy; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_stale_pdst_0 = io_brupdate_b2_uop_stale_pdst; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_exception_0 = io_brupdate_b2_uop_exception; // @[issue-slot.scala:69:7] wire [63:0] io_brupdate_b2_uop_exc_cause_0 = io_brupdate_b2_uop_exc_cause; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_bypassable_0 = io_brupdate_b2_uop_bypassable; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_mem_cmd_0 = io_brupdate_b2_uop_mem_cmd; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_mem_size_0 = io_brupdate_b2_uop_mem_size; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_mem_signed_0 = io_brupdate_b2_uop_mem_signed; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_fence_0 = io_brupdate_b2_uop_is_fence; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_fencei_0 = io_brupdate_b2_uop_is_fencei; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_amo_0 = io_brupdate_b2_uop_is_amo; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_uses_ldq_0 = io_brupdate_b2_uop_uses_ldq; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_uses_stq_0 = io_brupdate_b2_uop_uses_stq; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_sys_pc2epc_0 = io_brupdate_b2_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_unique_0 = io_brupdate_b2_uop_is_unique; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_flush_on_commit_0 = io_brupdate_b2_uop_flush_on_commit; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ldst_is_rs1_0 = io_brupdate_b2_uop_ldst_is_rs1; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_ldst_0 = io_brupdate_b2_uop_ldst; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_lrs1_0 = io_brupdate_b2_uop_lrs1; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_lrs2_0 = io_brupdate_b2_uop_lrs2; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_lrs3_0 = io_brupdate_b2_uop_lrs3; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ldst_val_0 = io_brupdate_b2_uop_ldst_val; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_dst_rtype_0 = io_brupdate_b2_uop_dst_rtype; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_lrs1_rtype_0 = io_brupdate_b2_uop_lrs1_rtype; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_lrs2_rtype_0 = io_brupdate_b2_uop_lrs2_rtype; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_frs3_en_0 = io_brupdate_b2_uop_frs3_en; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_fp_val_0 = io_brupdate_b2_uop_fp_val; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_fp_single_0 = io_brupdate_b2_uop_fp_single; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_xcpt_pf_if_0 = io_brupdate_b2_uop_xcpt_pf_if; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_xcpt_ae_if_0 = io_brupdate_b2_uop_xcpt_ae_if; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_xcpt_ma_if_0 = io_brupdate_b2_uop_xcpt_ma_if; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_bp_debug_if_0 = io_brupdate_b2_uop_bp_debug_if; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_bp_xcpt_if_0 = io_brupdate_b2_uop_bp_xcpt_if; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_debug_fsrc_0 = io_brupdate_b2_uop_debug_fsrc; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_debug_tsrc_0 = io_brupdate_b2_uop_debug_tsrc; // @[issue-slot.scala:69:7] wire io_brupdate_b2_valid_0 = io_brupdate_b2_valid; // @[issue-slot.scala:69:7] wire io_brupdate_b2_mispredict_0 = io_brupdate_b2_mispredict; // @[issue-slot.scala:69:7] wire io_brupdate_b2_taken_0 = io_brupdate_b2_taken; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_cfi_type_0 = io_brupdate_b2_cfi_type; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_pc_sel_0 = io_brupdate_b2_pc_sel; // @[issue-slot.scala:69:7] wire [39:0] io_brupdate_b2_jalr_target_0 = io_brupdate_b2_jalr_target; // @[issue-slot.scala:69:7] wire [20:0] io_brupdate_b2_target_offset_0 = io_brupdate_b2_target_offset; // @[issue-slot.scala:69:7] wire io_kill_0 = io_kill; // @[issue-slot.scala:69:7] wire io_clear_0 = io_clear; // @[issue-slot.scala:69:7] wire io_ldspec_miss_0 = io_ldspec_miss; // @[issue-slot.scala:69:7] wire io_wakeup_ports_0_valid_0 = io_wakeup_ports_0_valid; // @[issue-slot.scala:69:7] wire [5:0] io_wakeup_ports_0_bits_pdst_0 = io_wakeup_ports_0_bits_pdst; // @[issue-slot.scala:69:7] wire io_wakeup_ports_0_bits_poisoned_0 = io_wakeup_ports_0_bits_poisoned; // @[issue-slot.scala:69:7] wire io_wakeup_ports_1_valid_0 = io_wakeup_ports_1_valid; // @[issue-slot.scala:69:7] wire [5:0] io_wakeup_ports_1_bits_pdst_0 = io_wakeup_ports_1_bits_pdst; // @[issue-slot.scala:69:7] wire io_wakeup_ports_1_bits_poisoned_0 = io_wakeup_ports_1_bits_poisoned; // @[issue-slot.scala:69:7] wire io_wakeup_ports_2_valid_0 = io_wakeup_ports_2_valid; // @[issue-slot.scala:69:7] wire [5:0] io_wakeup_ports_2_bits_pdst_0 = io_wakeup_ports_2_bits_pdst; // @[issue-slot.scala:69:7] wire io_wakeup_ports_2_bits_poisoned_0 = io_wakeup_ports_2_bits_poisoned; // @[issue-slot.scala:69:7] wire io_spec_ld_wakeup_0_valid_0 = io_spec_ld_wakeup_0_valid; // @[issue-slot.scala:69:7] wire [5:0] io_spec_ld_wakeup_0_bits_0 = io_spec_ld_wakeup_0_bits; // @[issue-slot.scala:69:7] wire io_in_uop_valid_0 = io_in_uop_valid; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_uopc_0 = io_in_uop_bits_uopc; // @[issue-slot.scala:69:7] wire [31:0] io_in_uop_bits_inst_0 = io_in_uop_bits_inst; // @[issue-slot.scala:69:7] wire [31:0] io_in_uop_bits_debug_inst_0 = io_in_uop_bits_debug_inst; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_rvc_0 = io_in_uop_bits_is_rvc; // @[issue-slot.scala:69:7] wire [39:0] io_in_uop_bits_debug_pc_0 = io_in_uop_bits_debug_pc; // @[issue-slot.scala:69:7] wire [2:0] io_in_uop_bits_iq_type_0 = io_in_uop_bits_iq_type; // @[issue-slot.scala:69:7] wire [9:0] io_in_uop_bits_fu_code_0 = io_in_uop_bits_fu_code; // @[issue-slot.scala:69:7] wire [3:0] io_in_uop_bits_ctrl_br_type_0 = io_in_uop_bits_ctrl_br_type; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_ctrl_op1_sel_0 = io_in_uop_bits_ctrl_op1_sel; // @[issue-slot.scala:69:7] wire [2:0] io_in_uop_bits_ctrl_op2_sel_0 = io_in_uop_bits_ctrl_op2_sel; // @[issue-slot.scala:69:7] wire [2:0] io_in_uop_bits_ctrl_imm_sel_0 = io_in_uop_bits_ctrl_imm_sel; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_ctrl_op_fcn_0 = io_in_uop_bits_ctrl_op_fcn; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ctrl_fcn_dw_0 = io_in_uop_bits_ctrl_fcn_dw; // @[issue-slot.scala:69:7] wire [2:0] io_in_uop_bits_ctrl_csr_cmd_0 = io_in_uop_bits_ctrl_csr_cmd; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ctrl_is_load_0 = io_in_uop_bits_ctrl_is_load; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ctrl_is_sta_0 = io_in_uop_bits_ctrl_is_sta; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ctrl_is_std_0 = io_in_uop_bits_ctrl_is_std; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_iw_state_0 = io_in_uop_bits_iw_state; // @[issue-slot.scala:69:7] wire io_in_uop_bits_iw_p1_poisoned_0 = io_in_uop_bits_iw_p1_poisoned; // @[issue-slot.scala:69:7] wire io_in_uop_bits_iw_p2_poisoned_0 = io_in_uop_bits_iw_p2_poisoned; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_br_0 = io_in_uop_bits_is_br; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_jalr_0 = io_in_uop_bits_is_jalr; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_jal_0 = io_in_uop_bits_is_jal; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_sfb_0 = io_in_uop_bits_is_sfb; // @[issue-slot.scala:69:7] wire [7:0] io_in_uop_bits_br_mask_0 = io_in_uop_bits_br_mask; // @[issue-slot.scala:69:7] wire [2:0] io_in_uop_bits_br_tag_0 = io_in_uop_bits_br_tag; // @[issue-slot.scala:69:7] wire [3:0] io_in_uop_bits_ftq_idx_0 = io_in_uop_bits_ftq_idx; // @[issue-slot.scala:69:7] wire io_in_uop_bits_edge_inst_0 = io_in_uop_bits_edge_inst; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_pc_lob_0 = io_in_uop_bits_pc_lob; // @[issue-slot.scala:69:7] wire io_in_uop_bits_taken_0 = io_in_uop_bits_taken; // @[issue-slot.scala:69:7] wire [19:0] io_in_uop_bits_imm_packed_0 = io_in_uop_bits_imm_packed; // @[issue-slot.scala:69:7] wire [11:0] io_in_uop_bits_csr_addr_0 = io_in_uop_bits_csr_addr; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_rob_idx_0 = io_in_uop_bits_rob_idx; // @[issue-slot.scala:69:7] wire [2:0] io_in_uop_bits_ldq_idx_0 = io_in_uop_bits_ldq_idx; // @[issue-slot.scala:69:7] wire [2:0] io_in_uop_bits_stq_idx_0 = io_in_uop_bits_stq_idx; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_rxq_idx_0 = io_in_uop_bits_rxq_idx; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_pdst_0 = io_in_uop_bits_pdst; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_prs1_0 = io_in_uop_bits_prs1; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_prs2_0 = io_in_uop_bits_prs2; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_prs3_0 = io_in_uop_bits_prs3; // @[issue-slot.scala:69:7] wire [3:0] io_in_uop_bits_ppred_0 = io_in_uop_bits_ppred; // @[issue-slot.scala:69:7] wire io_in_uop_bits_prs1_busy_0 = io_in_uop_bits_prs1_busy; // @[issue-slot.scala:69:7] wire io_in_uop_bits_prs2_busy_0 = io_in_uop_bits_prs2_busy; // @[issue-slot.scala:69:7] wire io_in_uop_bits_prs3_busy_0 = io_in_uop_bits_prs3_busy; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ppred_busy_0 = io_in_uop_bits_ppred_busy; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_stale_pdst_0 = io_in_uop_bits_stale_pdst; // @[issue-slot.scala:69:7] wire io_in_uop_bits_exception_0 = io_in_uop_bits_exception; // @[issue-slot.scala:69:7] wire [63:0] io_in_uop_bits_exc_cause_0 = io_in_uop_bits_exc_cause; // @[issue-slot.scala:69:7] wire io_in_uop_bits_bypassable_0 = io_in_uop_bits_bypassable; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_mem_cmd_0 = io_in_uop_bits_mem_cmd; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_mem_size_0 = io_in_uop_bits_mem_size; // @[issue-slot.scala:69:7] wire io_in_uop_bits_mem_signed_0 = io_in_uop_bits_mem_signed; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_fence_0 = io_in_uop_bits_is_fence; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_fencei_0 = io_in_uop_bits_is_fencei; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_amo_0 = io_in_uop_bits_is_amo; // @[issue-slot.scala:69:7] wire io_in_uop_bits_uses_ldq_0 = io_in_uop_bits_uses_ldq; // @[issue-slot.scala:69:7] wire io_in_uop_bits_uses_stq_0 = io_in_uop_bits_uses_stq; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_sys_pc2epc_0 = io_in_uop_bits_is_sys_pc2epc; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_unique_0 = io_in_uop_bits_is_unique; // @[issue-slot.scala:69:7] wire io_in_uop_bits_flush_on_commit_0 = io_in_uop_bits_flush_on_commit; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ldst_is_rs1_0 = io_in_uop_bits_ldst_is_rs1; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_ldst_0 = io_in_uop_bits_ldst; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_lrs1_0 = io_in_uop_bits_lrs1; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_lrs2_0 = io_in_uop_bits_lrs2; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_lrs3_0 = io_in_uop_bits_lrs3; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ldst_val_0 = io_in_uop_bits_ldst_val; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_dst_rtype_0 = io_in_uop_bits_dst_rtype; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_lrs1_rtype_0 = io_in_uop_bits_lrs1_rtype; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_lrs2_rtype_0 = io_in_uop_bits_lrs2_rtype; // @[issue-slot.scala:69:7] wire io_in_uop_bits_frs3_en_0 = io_in_uop_bits_frs3_en; // @[issue-slot.scala:69:7] wire io_in_uop_bits_fp_val_0 = io_in_uop_bits_fp_val; // @[issue-slot.scala:69:7] wire io_in_uop_bits_fp_single_0 = io_in_uop_bits_fp_single; // @[issue-slot.scala:69:7] wire io_in_uop_bits_xcpt_pf_if_0 = io_in_uop_bits_xcpt_pf_if; // @[issue-slot.scala:69:7] wire io_in_uop_bits_xcpt_ae_if_0 = io_in_uop_bits_xcpt_ae_if; // @[issue-slot.scala:69:7] wire io_in_uop_bits_xcpt_ma_if_0 = io_in_uop_bits_xcpt_ma_if; // @[issue-slot.scala:69:7] wire io_in_uop_bits_bp_debug_if_0 = io_in_uop_bits_bp_debug_if; // @[issue-slot.scala:69:7] wire io_in_uop_bits_bp_xcpt_if_0 = io_in_uop_bits_bp_xcpt_if; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_debug_fsrc_0 = io_in_uop_bits_debug_fsrc; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_debug_tsrc_0 = io_in_uop_bits_debug_tsrc; // @[issue-slot.scala:69:7] wire io_pred_wakeup_port_valid = 1'h0; // @[issue-slot.scala:69:7] wire slot_uop_uop_is_rvc = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ctrl_fcn_dw = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ctrl_is_load = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ctrl_is_sta = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ctrl_is_std = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_iw_p1_poisoned = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_iw_p2_poisoned = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_br = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_jalr = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_jal = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_sfb = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_edge_inst = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_taken = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_prs1_busy = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_prs2_busy = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_prs3_busy = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ppred_busy = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_exception = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_bypassable = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_mem_signed = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_fence = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_fencei = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_amo = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_uses_ldq = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_uses_stq = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_sys_pc2epc = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_unique = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_flush_on_commit = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ldst_is_rs1 = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ldst_val = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_frs3_en = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_fp_val = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_fp_single = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_xcpt_pf_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_xcpt_ae_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_xcpt_ma_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_bp_debug_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_bp_xcpt_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_cs_fcn_dw = 1'h0; // @[consts.scala:279:18] wire slot_uop_cs_is_load = 1'h0; // @[consts.scala:279:18] wire slot_uop_cs_is_sta = 1'h0; // @[consts.scala:279:18] wire slot_uop_cs_is_std = 1'h0; // @[consts.scala:279:18] wire [3:0] io_pred_wakeup_port_bits = 4'h0; // @[issue-slot.scala:69:7] wire [3:0] slot_uop_uop_ctrl_br_type = 4'h0; // @[consts.scala:269:19] wire [3:0] slot_uop_uop_ftq_idx = 4'h0; // @[consts.scala:269:19] wire [3:0] slot_uop_uop_ppred = 4'h0; // @[consts.scala:269:19] wire [3:0] slot_uop_cs_br_type = 4'h0; // @[consts.scala:279:18] wire [2:0] slot_uop_uop_iq_type = 3'h0; // @[consts.scala:269:19] wire [2:0] slot_uop_uop_ctrl_op2_sel = 3'h0; // @[consts.scala:269:19] wire [2:0] slot_uop_uop_ctrl_imm_sel = 3'h0; // @[consts.scala:269:19] wire [2:0] slot_uop_uop_ctrl_csr_cmd = 3'h0; // @[consts.scala:269:19] wire [2:0] slot_uop_uop_br_tag = 3'h0; // @[consts.scala:269:19] wire [2:0] slot_uop_uop_ldq_idx = 3'h0; // @[consts.scala:269:19] wire [2:0] slot_uop_uop_stq_idx = 3'h0; // @[consts.scala:269:19] wire [2:0] slot_uop_cs_op2_sel = 3'h0; // @[consts.scala:279:18] wire [2:0] slot_uop_cs_imm_sel = 3'h0; // @[consts.scala:279:18] wire [2:0] slot_uop_cs_csr_cmd = 3'h0; // @[consts.scala:279:18] wire [4:0] slot_uop_uop_ctrl_op_fcn = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_uop_rob_idx = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_uop_mem_cmd = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_cs_op_fcn = 5'h0; // @[consts.scala:279:18] wire [1:0] slot_uop_uop_ctrl_op1_sel = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_iw_state = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_rxq_idx = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_mem_size = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_lrs1_rtype = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_lrs2_rtype = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_debug_fsrc = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_debug_tsrc = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_cs_op1_sel = 2'h0; // @[consts.scala:279:18] wire [1:0] slot_uop_uop_dst_rtype = 2'h2; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_pc_lob = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_pdst = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_prs1 = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_prs2 = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_prs3 = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_stale_pdst = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_ldst = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_lrs1 = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_lrs2 = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_lrs3 = 6'h0; // @[consts.scala:269:19] wire [63:0] slot_uop_uop_exc_cause = 64'h0; // @[consts.scala:269:19] wire [11:0] slot_uop_uop_csr_addr = 12'h0; // @[consts.scala:269:19] wire [19:0] slot_uop_uop_imm_packed = 20'h0; // @[consts.scala:269:19] wire [7:0] slot_uop_uop_br_mask = 8'h0; // @[consts.scala:269:19] wire [9:0] slot_uop_uop_fu_code = 10'h0; // @[consts.scala:269:19] wire [39:0] slot_uop_uop_debug_pc = 40'h0; // @[consts.scala:269:19] wire [31:0] slot_uop_uop_inst = 32'h0; // @[consts.scala:269:19] wire [31:0] slot_uop_uop_debug_inst = 32'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_uopc = 7'h0; // @[consts.scala:269:19] wire _io_valid_T; // @[issue-slot.scala:79:24] wire _io_will_be_valid_T_4; // @[issue-slot.scala:262:32] wire _io_request_hp_T; // @[issue-slot.scala:243:31] wire [6:0] next_uopc; // @[issue-slot.scala:82:29] wire [1:0] next_state; // @[issue-slot.scala:81:29] wire [7:0] next_br_mask; // @[util.scala:85:25] wire _io_out_uop_prs1_busy_T; // @[issue-slot.scala:270:28] wire _io_out_uop_prs2_busy_T; // @[issue-slot.scala:271:28] wire _io_out_uop_prs3_busy_T; // @[issue-slot.scala:272:28] wire _io_out_uop_ppred_busy_T; // @[issue-slot.scala:273:28] wire [1:0] next_lrs1_rtype; // @[issue-slot.scala:83:29] wire [1:0] next_lrs2_rtype; // @[issue-slot.scala:84:29] wire [3:0] io_out_uop_ctrl_br_type_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_ctrl_op1_sel_0; // @[issue-slot.scala:69:7] wire [2:0] io_out_uop_ctrl_op2_sel_0; // @[issue-slot.scala:69:7] wire [2:0] io_out_uop_ctrl_imm_sel_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_ctrl_op_fcn_0; // @[issue-slot.scala:69:7] wire io_out_uop_ctrl_fcn_dw_0; // @[issue-slot.scala:69:7] wire [2:0] io_out_uop_ctrl_csr_cmd_0; // @[issue-slot.scala:69:7] wire io_out_uop_ctrl_is_load_0; // @[issue-slot.scala:69:7] wire io_out_uop_ctrl_is_sta_0; // @[issue-slot.scala:69:7] wire io_out_uop_ctrl_is_std_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_uopc_0; // @[issue-slot.scala:69:7] wire [31:0] io_out_uop_inst_0; // @[issue-slot.scala:69:7] wire [31:0] io_out_uop_debug_inst_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_rvc_0; // @[issue-slot.scala:69:7] wire [39:0] io_out_uop_debug_pc_0; // @[issue-slot.scala:69:7] wire [2:0] io_out_uop_iq_type_0; // @[issue-slot.scala:69:7] wire [9:0] io_out_uop_fu_code_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_iw_state_0; // @[issue-slot.scala:69:7] wire io_out_uop_iw_p1_poisoned_0; // @[issue-slot.scala:69:7] wire io_out_uop_iw_p2_poisoned_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_br_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_jalr_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_jal_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_sfb_0; // @[issue-slot.scala:69:7] wire [7:0] io_out_uop_br_mask_0; // @[issue-slot.scala:69:7] wire [2:0] io_out_uop_br_tag_0; // @[issue-slot.scala:69:7] wire [3:0] io_out_uop_ftq_idx_0; // @[issue-slot.scala:69:7] wire io_out_uop_edge_inst_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_pc_lob_0; // @[issue-slot.scala:69:7] wire io_out_uop_taken_0; // @[issue-slot.scala:69:7] wire [19:0] io_out_uop_imm_packed_0; // @[issue-slot.scala:69:7] wire [11:0] io_out_uop_csr_addr_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_rob_idx_0; // @[issue-slot.scala:69:7] wire [2:0] io_out_uop_ldq_idx_0; // @[issue-slot.scala:69:7] wire [2:0] io_out_uop_stq_idx_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_rxq_idx_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_pdst_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_prs1_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_prs2_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_prs3_0; // @[issue-slot.scala:69:7] wire [3:0] io_out_uop_ppred_0; // @[issue-slot.scala:69:7] wire io_out_uop_prs1_busy_0; // @[issue-slot.scala:69:7] wire io_out_uop_prs2_busy_0; // @[issue-slot.scala:69:7] wire io_out_uop_prs3_busy_0; // @[issue-slot.scala:69:7] wire io_out_uop_ppred_busy_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_stale_pdst_0; // @[issue-slot.scala:69:7] wire io_out_uop_exception_0; // @[issue-slot.scala:69:7] wire [63:0] io_out_uop_exc_cause_0; // @[issue-slot.scala:69:7] wire io_out_uop_bypassable_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_mem_cmd_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_mem_size_0; // @[issue-slot.scala:69:7] wire io_out_uop_mem_signed_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_fence_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_fencei_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_amo_0; // @[issue-slot.scala:69:7] wire io_out_uop_uses_ldq_0; // @[issue-slot.scala:69:7] wire io_out_uop_uses_stq_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_sys_pc2epc_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_unique_0; // @[issue-slot.scala:69:7] wire io_out_uop_flush_on_commit_0; // @[issue-slot.scala:69:7] wire io_out_uop_ldst_is_rs1_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_ldst_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_lrs1_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_lrs2_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_lrs3_0; // @[issue-slot.scala:69:7] wire io_out_uop_ldst_val_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_dst_rtype_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_lrs1_rtype_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_lrs2_rtype_0; // @[issue-slot.scala:69:7] wire io_out_uop_frs3_en_0; // @[issue-slot.scala:69:7] wire io_out_uop_fp_val_0; // @[issue-slot.scala:69:7] wire io_out_uop_fp_single_0; // @[issue-slot.scala:69:7] wire io_out_uop_xcpt_pf_if_0; // @[issue-slot.scala:69:7] wire io_out_uop_xcpt_ae_if_0; // @[issue-slot.scala:69:7] wire io_out_uop_xcpt_ma_if_0; // @[issue-slot.scala:69:7] wire io_out_uop_bp_debug_if_0; // @[issue-slot.scala:69:7] wire io_out_uop_bp_xcpt_if_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_debug_fsrc_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_debug_tsrc_0; // @[issue-slot.scala:69:7] wire [3:0] io_uop_ctrl_br_type_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_ctrl_op1_sel_0; // @[issue-slot.scala:69:7] wire [2:0] io_uop_ctrl_op2_sel_0; // @[issue-slot.scala:69:7] wire [2:0] io_uop_ctrl_imm_sel_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_ctrl_op_fcn_0; // @[issue-slot.scala:69:7] wire io_uop_ctrl_fcn_dw_0; // @[issue-slot.scala:69:7] wire [2:0] io_uop_ctrl_csr_cmd_0; // @[issue-slot.scala:69:7] wire io_uop_ctrl_is_load_0; // @[issue-slot.scala:69:7] wire io_uop_ctrl_is_sta_0; // @[issue-slot.scala:69:7] wire io_uop_ctrl_is_std_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_uopc_0; // @[issue-slot.scala:69:7] wire [31:0] io_uop_inst_0; // @[issue-slot.scala:69:7] wire [31:0] io_uop_debug_inst_0; // @[issue-slot.scala:69:7] wire io_uop_is_rvc_0; // @[issue-slot.scala:69:7] wire [39:0] io_uop_debug_pc_0; // @[issue-slot.scala:69:7] wire [2:0] io_uop_iq_type_0; // @[issue-slot.scala:69:7] wire [9:0] io_uop_fu_code_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_iw_state_0; // @[issue-slot.scala:69:7] wire io_uop_iw_p1_poisoned_0; // @[issue-slot.scala:69:7] wire io_uop_iw_p2_poisoned_0; // @[issue-slot.scala:69:7] wire io_uop_is_br_0; // @[issue-slot.scala:69:7] wire io_uop_is_jalr_0; // @[issue-slot.scala:69:7] wire io_uop_is_jal_0; // @[issue-slot.scala:69:7] wire io_uop_is_sfb_0; // @[issue-slot.scala:69:7] wire [7:0] io_uop_br_mask_0; // @[issue-slot.scala:69:7] wire [2:0] io_uop_br_tag_0; // @[issue-slot.scala:69:7] wire [3:0] io_uop_ftq_idx_0; // @[issue-slot.scala:69:7] wire io_uop_edge_inst_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_pc_lob_0; // @[issue-slot.scala:69:7] wire io_uop_taken_0; // @[issue-slot.scala:69:7] wire [19:0] io_uop_imm_packed_0; // @[issue-slot.scala:69:7] wire [11:0] io_uop_csr_addr_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_rob_idx_0; // @[issue-slot.scala:69:7] wire [2:0] io_uop_ldq_idx_0; // @[issue-slot.scala:69:7] wire [2:0] io_uop_stq_idx_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_rxq_idx_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_pdst_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_prs1_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_prs2_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_prs3_0; // @[issue-slot.scala:69:7] wire [3:0] io_uop_ppred_0; // @[issue-slot.scala:69:7] wire io_uop_prs1_busy_0; // @[issue-slot.scala:69:7] wire io_uop_prs2_busy_0; // @[issue-slot.scala:69:7] wire io_uop_prs3_busy_0; // @[issue-slot.scala:69:7] wire io_uop_ppred_busy_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_stale_pdst_0; // @[issue-slot.scala:69:7] wire io_uop_exception_0; // @[issue-slot.scala:69:7] wire [63:0] io_uop_exc_cause_0; // @[issue-slot.scala:69:7] wire io_uop_bypassable_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_mem_cmd_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_mem_size_0; // @[issue-slot.scala:69:7] wire io_uop_mem_signed_0; // @[issue-slot.scala:69:7] wire io_uop_is_fence_0; // @[issue-slot.scala:69:7] wire io_uop_is_fencei_0; // @[issue-slot.scala:69:7] wire io_uop_is_amo_0; // @[issue-slot.scala:69:7] wire io_uop_uses_ldq_0; // @[issue-slot.scala:69:7] wire io_uop_uses_stq_0; // @[issue-slot.scala:69:7] wire io_uop_is_sys_pc2epc_0; // @[issue-slot.scala:69:7] wire io_uop_is_unique_0; // @[issue-slot.scala:69:7] wire io_uop_flush_on_commit_0; // @[issue-slot.scala:69:7] wire io_uop_ldst_is_rs1_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_ldst_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_lrs1_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_lrs2_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_lrs3_0; // @[issue-slot.scala:69:7] wire io_uop_ldst_val_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_dst_rtype_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_lrs1_rtype_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_lrs2_rtype_0; // @[issue-slot.scala:69:7] wire io_uop_frs3_en_0; // @[issue-slot.scala:69:7] wire io_uop_fp_val_0; // @[issue-slot.scala:69:7] wire io_uop_fp_single_0; // @[issue-slot.scala:69:7] wire io_uop_xcpt_pf_if_0; // @[issue-slot.scala:69:7] wire io_uop_xcpt_ae_if_0; // @[issue-slot.scala:69:7] wire io_uop_xcpt_ma_if_0; // @[issue-slot.scala:69:7] wire io_uop_bp_debug_if_0; // @[issue-slot.scala:69:7] wire io_uop_bp_xcpt_if_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_debug_fsrc_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_debug_tsrc_0; // @[issue-slot.scala:69:7] wire io_debug_p1_0; // @[issue-slot.scala:69:7] wire io_debug_p2_0; // @[issue-slot.scala:69:7] wire io_debug_p3_0; // @[issue-slot.scala:69:7] wire io_debug_ppred_0; // @[issue-slot.scala:69:7] wire [1:0] io_debug_state_0; // @[issue-slot.scala:69:7] wire io_valid_0; // @[issue-slot.scala:69:7] wire io_will_be_valid_0; // @[issue-slot.scala:69:7] wire io_request_0; // @[issue-slot.scala:69:7] wire io_request_hp_0; // @[issue-slot.scala:69:7] assign io_out_uop_iw_state_0 = next_state; // @[issue-slot.scala:69:7, :81:29] assign io_out_uop_uopc_0 = next_uopc; // @[issue-slot.scala:69:7, :82:29] assign io_out_uop_lrs1_rtype_0 = next_lrs1_rtype; // @[issue-slot.scala:69:7, :83:29] assign io_out_uop_lrs2_rtype_0 = next_lrs2_rtype; // @[issue-slot.scala:69:7, :84:29] reg [1:0] state; // @[issue-slot.scala:86:22] assign io_debug_state_0 = state; // @[issue-slot.scala:69:7, :86:22] reg p1; // @[issue-slot.scala:87:22] assign io_debug_p1_0 = p1; // @[issue-slot.scala:69:7, :87:22] wire next_p1 = p1; // @[issue-slot.scala:87:22, :163:25] reg p2; // @[issue-slot.scala:88:22] assign io_debug_p2_0 = p2; // @[issue-slot.scala:69:7, :88:22] wire next_p2 = p2; // @[issue-slot.scala:88:22, :164:25] reg p3; // @[issue-slot.scala:89:22] assign io_debug_p3_0 = p3; // @[issue-slot.scala:69:7, :89:22] wire next_p3 = p3; // @[issue-slot.scala:89:22, :165:25] reg ppred; // @[issue-slot.scala:90:22] assign io_debug_ppred_0 = ppred; // @[issue-slot.scala:69:7, :90:22] wire next_ppred = ppred; // @[issue-slot.scala:90:22, :166:28] reg p1_poisoned; // @[issue-slot.scala:95:28] assign io_out_uop_iw_p1_poisoned_0 = p1_poisoned; // @[issue-slot.scala:69:7, :95:28] assign io_uop_iw_p1_poisoned_0 = p1_poisoned; // @[issue-slot.scala:69:7, :95:28] reg p2_poisoned; // @[issue-slot.scala:96:28] assign io_out_uop_iw_p2_poisoned_0 = p2_poisoned; // @[issue-slot.scala:69:7, :96:28] assign io_uop_iw_p2_poisoned_0 = p2_poisoned; // @[issue-slot.scala:69:7, :96:28] wire next_p1_poisoned = io_in_uop_valid_0 ? io_in_uop_bits_iw_p1_poisoned_0 : p1_poisoned; // @[issue-slot.scala:69:7, :95:28, :99:29] wire next_p2_poisoned = io_in_uop_valid_0 ? io_in_uop_bits_iw_p2_poisoned_0 : p2_poisoned; // @[issue-slot.scala:69:7, :96:28, :100:29] reg [6:0] slot_uop_uopc; // @[issue-slot.scala:102:25] reg [31:0] slot_uop_inst; // @[issue-slot.scala:102:25] assign io_out_uop_inst_0 = slot_uop_inst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_inst_0 = slot_uop_inst; // @[issue-slot.scala:69:7, :102:25] reg [31:0] slot_uop_debug_inst; // @[issue-slot.scala:102:25] assign io_out_uop_debug_inst_0 = slot_uop_debug_inst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_debug_inst_0 = slot_uop_debug_inst; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_rvc; // @[issue-slot.scala:102:25] assign io_out_uop_is_rvc_0 = slot_uop_is_rvc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_rvc_0 = slot_uop_is_rvc; // @[issue-slot.scala:69:7, :102:25] reg [39:0] slot_uop_debug_pc; // @[issue-slot.scala:102:25] assign io_out_uop_debug_pc_0 = slot_uop_debug_pc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_debug_pc_0 = slot_uop_debug_pc; // @[issue-slot.scala:69:7, :102:25] reg [2:0] slot_uop_iq_type; // @[issue-slot.scala:102:25] assign io_out_uop_iq_type_0 = slot_uop_iq_type; // @[issue-slot.scala:69:7, :102:25] assign io_uop_iq_type_0 = slot_uop_iq_type; // @[issue-slot.scala:69:7, :102:25] reg [9:0] slot_uop_fu_code; // @[issue-slot.scala:102:25] assign io_out_uop_fu_code_0 = slot_uop_fu_code; // @[issue-slot.scala:69:7, :102:25] assign io_uop_fu_code_0 = slot_uop_fu_code; // @[issue-slot.scala:69:7, :102:25] reg [3:0] slot_uop_ctrl_br_type; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_br_type_0 = slot_uop_ctrl_br_type; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_br_type_0 = slot_uop_ctrl_br_type; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_ctrl_op1_sel; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_op1_sel_0 = slot_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_op1_sel_0 = slot_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7, :102:25] reg [2:0] slot_uop_ctrl_op2_sel; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_op2_sel_0 = slot_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_op2_sel_0 = slot_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7, :102:25] reg [2:0] slot_uop_ctrl_imm_sel; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_imm_sel_0 = slot_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_imm_sel_0 = slot_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_ctrl_op_fcn; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_op_fcn_0 = slot_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_op_fcn_0 = slot_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_fcn_dw_0 = slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_fcn_dw_0 = slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7, :102:25] reg [2:0] slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_csr_cmd_0 = slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_csr_cmd_0 = slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ctrl_is_load; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_is_load_0 = slot_uop_ctrl_is_load; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_is_load_0 = slot_uop_ctrl_is_load; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ctrl_is_sta; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_is_sta_0 = slot_uop_ctrl_is_sta; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_is_sta_0 = slot_uop_ctrl_is_sta; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ctrl_is_std; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_is_std_0 = slot_uop_ctrl_is_std; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_is_std_0 = slot_uop_ctrl_is_std; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_iw_state; // @[issue-slot.scala:102:25] assign io_uop_iw_state_0 = slot_uop_iw_state; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_iw_p1_poisoned; // @[issue-slot.scala:102:25] reg slot_uop_iw_p2_poisoned; // @[issue-slot.scala:102:25] reg slot_uop_is_br; // @[issue-slot.scala:102:25] assign io_out_uop_is_br_0 = slot_uop_is_br; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_br_0 = slot_uop_is_br; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_jalr; // @[issue-slot.scala:102:25] assign io_out_uop_is_jalr_0 = slot_uop_is_jalr; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_jalr_0 = slot_uop_is_jalr; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_jal; // @[issue-slot.scala:102:25] assign io_out_uop_is_jal_0 = slot_uop_is_jal; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_jal_0 = slot_uop_is_jal; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_sfb; // @[issue-slot.scala:102:25] assign io_out_uop_is_sfb_0 = slot_uop_is_sfb; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_sfb_0 = slot_uop_is_sfb; // @[issue-slot.scala:69:7, :102:25] reg [7:0] slot_uop_br_mask; // @[issue-slot.scala:102:25] assign io_uop_br_mask_0 = slot_uop_br_mask; // @[issue-slot.scala:69:7, :102:25] reg [2:0] slot_uop_br_tag; // @[issue-slot.scala:102:25] assign io_out_uop_br_tag_0 = slot_uop_br_tag; // @[issue-slot.scala:69:7, :102:25] assign io_uop_br_tag_0 = slot_uop_br_tag; // @[issue-slot.scala:69:7, :102:25] reg [3:0] slot_uop_ftq_idx; // @[issue-slot.scala:102:25] assign io_out_uop_ftq_idx_0 = slot_uop_ftq_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ftq_idx_0 = slot_uop_ftq_idx; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_edge_inst; // @[issue-slot.scala:102:25] assign io_out_uop_edge_inst_0 = slot_uop_edge_inst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_edge_inst_0 = slot_uop_edge_inst; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_pc_lob; // @[issue-slot.scala:102:25] assign io_out_uop_pc_lob_0 = slot_uop_pc_lob; // @[issue-slot.scala:69:7, :102:25] assign io_uop_pc_lob_0 = slot_uop_pc_lob; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_taken; // @[issue-slot.scala:102:25] assign io_out_uop_taken_0 = slot_uop_taken; // @[issue-slot.scala:69:7, :102:25] assign io_uop_taken_0 = slot_uop_taken; // @[issue-slot.scala:69:7, :102:25] reg [19:0] slot_uop_imm_packed; // @[issue-slot.scala:102:25] assign io_out_uop_imm_packed_0 = slot_uop_imm_packed; // @[issue-slot.scala:69:7, :102:25] assign io_uop_imm_packed_0 = slot_uop_imm_packed; // @[issue-slot.scala:69:7, :102:25] reg [11:0] slot_uop_csr_addr; // @[issue-slot.scala:102:25] assign io_out_uop_csr_addr_0 = slot_uop_csr_addr; // @[issue-slot.scala:69:7, :102:25] assign io_uop_csr_addr_0 = slot_uop_csr_addr; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_rob_idx; // @[issue-slot.scala:102:25] assign io_out_uop_rob_idx_0 = slot_uop_rob_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_rob_idx_0 = slot_uop_rob_idx; // @[issue-slot.scala:69:7, :102:25] reg [2:0] slot_uop_ldq_idx; // @[issue-slot.scala:102:25] assign io_out_uop_ldq_idx_0 = slot_uop_ldq_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ldq_idx_0 = slot_uop_ldq_idx; // @[issue-slot.scala:69:7, :102:25] reg [2:0] slot_uop_stq_idx; // @[issue-slot.scala:102:25] assign io_out_uop_stq_idx_0 = slot_uop_stq_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_stq_idx_0 = slot_uop_stq_idx; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_rxq_idx; // @[issue-slot.scala:102:25] assign io_out_uop_rxq_idx_0 = slot_uop_rxq_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_rxq_idx_0 = slot_uop_rxq_idx; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_pdst; // @[issue-slot.scala:102:25] assign io_out_uop_pdst_0 = slot_uop_pdst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_pdst_0 = slot_uop_pdst; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_prs1; // @[issue-slot.scala:102:25] assign io_out_uop_prs1_0 = slot_uop_prs1; // @[issue-slot.scala:69:7, :102:25] assign io_uop_prs1_0 = slot_uop_prs1; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_prs2; // @[issue-slot.scala:102:25] assign io_out_uop_prs2_0 = slot_uop_prs2; // @[issue-slot.scala:69:7, :102:25] assign io_uop_prs2_0 = slot_uop_prs2; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_prs3; // @[issue-slot.scala:102:25] assign io_out_uop_prs3_0 = slot_uop_prs3; // @[issue-slot.scala:69:7, :102:25] assign io_uop_prs3_0 = slot_uop_prs3; // @[issue-slot.scala:69:7, :102:25] reg [3:0] slot_uop_ppred; // @[issue-slot.scala:102:25] assign io_out_uop_ppred_0 = slot_uop_ppred; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ppred_0 = slot_uop_ppred; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_prs1_busy; // @[issue-slot.scala:102:25] assign io_uop_prs1_busy_0 = slot_uop_prs1_busy; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_prs2_busy; // @[issue-slot.scala:102:25] assign io_uop_prs2_busy_0 = slot_uop_prs2_busy; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_prs3_busy; // @[issue-slot.scala:102:25] assign io_uop_prs3_busy_0 = slot_uop_prs3_busy; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ppred_busy; // @[issue-slot.scala:102:25] assign io_uop_ppred_busy_0 = slot_uop_ppred_busy; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_stale_pdst; // @[issue-slot.scala:102:25] assign io_out_uop_stale_pdst_0 = slot_uop_stale_pdst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_stale_pdst_0 = slot_uop_stale_pdst; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_exception; // @[issue-slot.scala:102:25] assign io_out_uop_exception_0 = slot_uop_exception; // @[issue-slot.scala:69:7, :102:25] assign io_uop_exception_0 = slot_uop_exception; // @[issue-slot.scala:69:7, :102:25] reg [63:0] slot_uop_exc_cause; // @[issue-slot.scala:102:25] assign io_out_uop_exc_cause_0 = slot_uop_exc_cause; // @[issue-slot.scala:69:7, :102:25] assign io_uop_exc_cause_0 = slot_uop_exc_cause; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_bypassable; // @[issue-slot.scala:102:25] assign io_out_uop_bypassable_0 = slot_uop_bypassable; // @[issue-slot.scala:69:7, :102:25] assign io_uop_bypassable_0 = slot_uop_bypassable; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_mem_cmd; // @[issue-slot.scala:102:25] assign io_out_uop_mem_cmd_0 = slot_uop_mem_cmd; // @[issue-slot.scala:69:7, :102:25] assign io_uop_mem_cmd_0 = slot_uop_mem_cmd; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_mem_size; // @[issue-slot.scala:102:25] assign io_out_uop_mem_size_0 = slot_uop_mem_size; // @[issue-slot.scala:69:7, :102:25] assign io_uop_mem_size_0 = slot_uop_mem_size; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_mem_signed; // @[issue-slot.scala:102:25] assign io_out_uop_mem_signed_0 = slot_uop_mem_signed; // @[issue-slot.scala:69:7, :102:25] assign io_uop_mem_signed_0 = slot_uop_mem_signed; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_fence; // @[issue-slot.scala:102:25] assign io_out_uop_is_fence_0 = slot_uop_is_fence; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_fence_0 = slot_uop_is_fence; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_fencei; // @[issue-slot.scala:102:25] assign io_out_uop_is_fencei_0 = slot_uop_is_fencei; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_fencei_0 = slot_uop_is_fencei; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_amo; // @[issue-slot.scala:102:25] assign io_out_uop_is_amo_0 = slot_uop_is_amo; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_amo_0 = slot_uop_is_amo; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_uses_ldq; // @[issue-slot.scala:102:25] assign io_out_uop_uses_ldq_0 = slot_uop_uses_ldq; // @[issue-slot.scala:69:7, :102:25] assign io_uop_uses_ldq_0 = slot_uop_uses_ldq; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_uses_stq; // @[issue-slot.scala:102:25] assign io_out_uop_uses_stq_0 = slot_uop_uses_stq; // @[issue-slot.scala:69:7, :102:25] assign io_uop_uses_stq_0 = slot_uop_uses_stq; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_sys_pc2epc; // @[issue-slot.scala:102:25] assign io_out_uop_is_sys_pc2epc_0 = slot_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_sys_pc2epc_0 = slot_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_unique; // @[issue-slot.scala:102:25] assign io_out_uop_is_unique_0 = slot_uop_is_unique; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_unique_0 = slot_uop_is_unique; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_flush_on_commit; // @[issue-slot.scala:102:25] assign io_out_uop_flush_on_commit_0 = slot_uop_flush_on_commit; // @[issue-slot.scala:69:7, :102:25] assign io_uop_flush_on_commit_0 = slot_uop_flush_on_commit; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ldst_is_rs1; // @[issue-slot.scala:102:25] assign io_out_uop_ldst_is_rs1_0 = slot_uop_ldst_is_rs1; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ldst_is_rs1_0 = slot_uop_ldst_is_rs1; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_ldst; // @[issue-slot.scala:102:25] assign io_out_uop_ldst_0 = slot_uop_ldst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ldst_0 = slot_uop_ldst; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_lrs1; // @[issue-slot.scala:102:25] assign io_out_uop_lrs1_0 = slot_uop_lrs1; // @[issue-slot.scala:69:7, :102:25] assign io_uop_lrs1_0 = slot_uop_lrs1; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_lrs2; // @[issue-slot.scala:102:25] assign io_out_uop_lrs2_0 = slot_uop_lrs2; // @[issue-slot.scala:69:7, :102:25] assign io_uop_lrs2_0 = slot_uop_lrs2; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_lrs3; // @[issue-slot.scala:102:25] assign io_out_uop_lrs3_0 = slot_uop_lrs3; // @[issue-slot.scala:69:7, :102:25] assign io_uop_lrs3_0 = slot_uop_lrs3; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ldst_val; // @[issue-slot.scala:102:25] assign io_out_uop_ldst_val_0 = slot_uop_ldst_val; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ldst_val_0 = slot_uop_ldst_val; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_dst_rtype; // @[issue-slot.scala:102:25] assign io_out_uop_dst_rtype_0 = slot_uop_dst_rtype; // @[issue-slot.scala:69:7, :102:25] assign io_uop_dst_rtype_0 = slot_uop_dst_rtype; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_lrs1_rtype; // @[issue-slot.scala:102:25] reg [1:0] slot_uop_lrs2_rtype; // @[issue-slot.scala:102:25] reg slot_uop_frs3_en; // @[issue-slot.scala:102:25] assign io_out_uop_frs3_en_0 = slot_uop_frs3_en; // @[issue-slot.scala:69:7, :102:25] assign io_uop_frs3_en_0 = slot_uop_frs3_en; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_fp_val; // @[issue-slot.scala:102:25] assign io_out_uop_fp_val_0 = slot_uop_fp_val; // @[issue-slot.scala:69:7, :102:25] assign io_uop_fp_val_0 = slot_uop_fp_val; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_fp_single; // @[issue-slot.scala:102:25] assign io_out_uop_fp_single_0 = slot_uop_fp_single; // @[issue-slot.scala:69:7, :102:25] assign io_uop_fp_single_0 = slot_uop_fp_single; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_xcpt_pf_if; // @[issue-slot.scala:102:25] assign io_out_uop_xcpt_pf_if_0 = slot_uop_xcpt_pf_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_xcpt_pf_if_0 = slot_uop_xcpt_pf_if; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_xcpt_ae_if; // @[issue-slot.scala:102:25] assign io_out_uop_xcpt_ae_if_0 = slot_uop_xcpt_ae_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_xcpt_ae_if_0 = slot_uop_xcpt_ae_if; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_xcpt_ma_if; // @[issue-slot.scala:102:25] assign io_out_uop_xcpt_ma_if_0 = slot_uop_xcpt_ma_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_xcpt_ma_if_0 = slot_uop_xcpt_ma_if; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_bp_debug_if; // @[issue-slot.scala:102:25] assign io_out_uop_bp_debug_if_0 = slot_uop_bp_debug_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_bp_debug_if_0 = slot_uop_bp_debug_if; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_bp_xcpt_if; // @[issue-slot.scala:102:25] assign io_out_uop_bp_xcpt_if_0 = slot_uop_bp_xcpt_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_bp_xcpt_if_0 = slot_uop_bp_xcpt_if; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_debug_fsrc; // @[issue-slot.scala:102:25] assign io_out_uop_debug_fsrc_0 = slot_uop_debug_fsrc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_debug_fsrc_0 = slot_uop_debug_fsrc; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_debug_tsrc; // @[issue-slot.scala:102:25] assign io_out_uop_debug_tsrc_0 = slot_uop_debug_tsrc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_debug_tsrc_0 = slot_uop_debug_tsrc; // @[issue-slot.scala:69:7, :102:25] wire [6:0] next_uop_uopc = io_in_uop_valid_0 ? io_in_uop_bits_uopc_0 : slot_uop_uopc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [31:0] next_uop_inst = io_in_uop_valid_0 ? io_in_uop_bits_inst_0 : slot_uop_inst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [31:0] next_uop_debug_inst = io_in_uop_valid_0 ? io_in_uop_bits_debug_inst_0 : slot_uop_debug_inst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_rvc = io_in_uop_valid_0 ? io_in_uop_bits_is_rvc_0 : slot_uop_is_rvc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [39:0] next_uop_debug_pc = io_in_uop_valid_0 ? io_in_uop_bits_debug_pc_0 : slot_uop_debug_pc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [2:0] next_uop_iq_type = io_in_uop_valid_0 ? io_in_uop_bits_iq_type_0 : slot_uop_iq_type; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [9:0] next_uop_fu_code = io_in_uop_valid_0 ? io_in_uop_bits_fu_code_0 : slot_uop_fu_code; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [3:0] next_uop_ctrl_br_type = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_br_type_0 : slot_uop_ctrl_br_type; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_ctrl_op1_sel = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_op1_sel_0 : slot_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [2:0] next_uop_ctrl_op2_sel = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_op2_sel_0 : slot_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [2:0] next_uop_ctrl_imm_sel = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_imm_sel_0 : slot_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_ctrl_op_fcn = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_op_fcn_0 : slot_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ctrl_fcn_dw = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_fcn_dw_0 : slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [2:0] next_uop_ctrl_csr_cmd = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_csr_cmd_0 : slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ctrl_is_load = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_is_load_0 : slot_uop_ctrl_is_load; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ctrl_is_sta = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_is_sta_0 : slot_uop_ctrl_is_sta; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ctrl_is_std = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_is_std_0 : slot_uop_ctrl_is_std; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_iw_state = io_in_uop_valid_0 ? io_in_uop_bits_iw_state_0 : slot_uop_iw_state; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_iw_p1_poisoned = io_in_uop_valid_0 ? io_in_uop_bits_iw_p1_poisoned_0 : slot_uop_iw_p1_poisoned; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_iw_p2_poisoned = io_in_uop_valid_0 ? io_in_uop_bits_iw_p2_poisoned_0 : slot_uop_iw_p2_poisoned; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_br = io_in_uop_valid_0 ? io_in_uop_bits_is_br_0 : slot_uop_is_br; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_jalr = io_in_uop_valid_0 ? io_in_uop_bits_is_jalr_0 : slot_uop_is_jalr; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_jal = io_in_uop_valid_0 ? io_in_uop_bits_is_jal_0 : slot_uop_is_jal; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_sfb = io_in_uop_valid_0 ? io_in_uop_bits_is_sfb_0 : slot_uop_is_sfb; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [7:0] next_uop_br_mask = io_in_uop_valid_0 ? io_in_uop_bits_br_mask_0 : slot_uop_br_mask; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [2:0] next_uop_br_tag = io_in_uop_valid_0 ? io_in_uop_bits_br_tag_0 : slot_uop_br_tag; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [3:0] next_uop_ftq_idx = io_in_uop_valid_0 ? io_in_uop_bits_ftq_idx_0 : slot_uop_ftq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_edge_inst = io_in_uop_valid_0 ? io_in_uop_bits_edge_inst_0 : slot_uop_edge_inst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_pc_lob = io_in_uop_valid_0 ? io_in_uop_bits_pc_lob_0 : slot_uop_pc_lob; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_taken = io_in_uop_valid_0 ? io_in_uop_bits_taken_0 : slot_uop_taken; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [19:0] next_uop_imm_packed = io_in_uop_valid_0 ? io_in_uop_bits_imm_packed_0 : slot_uop_imm_packed; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [11:0] next_uop_csr_addr = io_in_uop_valid_0 ? io_in_uop_bits_csr_addr_0 : slot_uop_csr_addr; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_rob_idx = io_in_uop_valid_0 ? io_in_uop_bits_rob_idx_0 : slot_uop_rob_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [2:0] next_uop_ldq_idx = io_in_uop_valid_0 ? io_in_uop_bits_ldq_idx_0 : slot_uop_ldq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [2:0] next_uop_stq_idx = io_in_uop_valid_0 ? io_in_uop_bits_stq_idx_0 : slot_uop_stq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_rxq_idx = io_in_uop_valid_0 ? io_in_uop_bits_rxq_idx_0 : slot_uop_rxq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_pdst = io_in_uop_valid_0 ? io_in_uop_bits_pdst_0 : slot_uop_pdst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_prs1 = io_in_uop_valid_0 ? io_in_uop_bits_prs1_0 : slot_uop_prs1; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_prs2 = io_in_uop_valid_0 ? io_in_uop_bits_prs2_0 : slot_uop_prs2; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_prs3 = io_in_uop_valid_0 ? io_in_uop_bits_prs3_0 : slot_uop_prs3; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [3:0] next_uop_ppred = io_in_uop_valid_0 ? io_in_uop_bits_ppred_0 : slot_uop_ppred; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_prs1_busy = io_in_uop_valid_0 ? io_in_uop_bits_prs1_busy_0 : slot_uop_prs1_busy; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_prs2_busy = io_in_uop_valid_0 ? io_in_uop_bits_prs2_busy_0 : slot_uop_prs2_busy; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_prs3_busy = io_in_uop_valid_0 ? io_in_uop_bits_prs3_busy_0 : slot_uop_prs3_busy; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ppred_busy = io_in_uop_valid_0 ? io_in_uop_bits_ppred_busy_0 : slot_uop_ppred_busy; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_stale_pdst = io_in_uop_valid_0 ? io_in_uop_bits_stale_pdst_0 : slot_uop_stale_pdst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_exception = io_in_uop_valid_0 ? io_in_uop_bits_exception_0 : slot_uop_exception; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [63:0] next_uop_exc_cause = io_in_uop_valid_0 ? io_in_uop_bits_exc_cause_0 : slot_uop_exc_cause; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_bypassable = io_in_uop_valid_0 ? io_in_uop_bits_bypassable_0 : slot_uop_bypassable; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_mem_cmd = io_in_uop_valid_0 ? io_in_uop_bits_mem_cmd_0 : slot_uop_mem_cmd; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_mem_size = io_in_uop_valid_0 ? io_in_uop_bits_mem_size_0 : slot_uop_mem_size; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_mem_signed = io_in_uop_valid_0 ? io_in_uop_bits_mem_signed_0 : slot_uop_mem_signed; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_fence = io_in_uop_valid_0 ? io_in_uop_bits_is_fence_0 : slot_uop_is_fence; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_fencei = io_in_uop_valid_0 ? io_in_uop_bits_is_fencei_0 : slot_uop_is_fencei; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_amo = io_in_uop_valid_0 ? io_in_uop_bits_is_amo_0 : slot_uop_is_amo; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_uses_ldq = io_in_uop_valid_0 ? io_in_uop_bits_uses_ldq_0 : slot_uop_uses_ldq; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_uses_stq = io_in_uop_valid_0 ? io_in_uop_bits_uses_stq_0 : slot_uop_uses_stq; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_sys_pc2epc = io_in_uop_valid_0 ? io_in_uop_bits_is_sys_pc2epc_0 : slot_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_unique = io_in_uop_valid_0 ? io_in_uop_bits_is_unique_0 : slot_uop_is_unique; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_flush_on_commit = io_in_uop_valid_0 ? io_in_uop_bits_flush_on_commit_0 : slot_uop_flush_on_commit; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ldst_is_rs1 = io_in_uop_valid_0 ? io_in_uop_bits_ldst_is_rs1_0 : slot_uop_ldst_is_rs1; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_ldst = io_in_uop_valid_0 ? io_in_uop_bits_ldst_0 : slot_uop_ldst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_lrs1 = io_in_uop_valid_0 ? io_in_uop_bits_lrs1_0 : slot_uop_lrs1; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_lrs2 = io_in_uop_valid_0 ? io_in_uop_bits_lrs2_0 : slot_uop_lrs2; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_lrs3 = io_in_uop_valid_0 ? io_in_uop_bits_lrs3_0 : slot_uop_lrs3; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ldst_val = io_in_uop_valid_0 ? io_in_uop_bits_ldst_val_0 : slot_uop_ldst_val; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_dst_rtype = io_in_uop_valid_0 ? io_in_uop_bits_dst_rtype_0 : slot_uop_dst_rtype; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_lrs1_rtype = io_in_uop_valid_0 ? io_in_uop_bits_lrs1_rtype_0 : slot_uop_lrs1_rtype; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_lrs2_rtype = io_in_uop_valid_0 ? io_in_uop_bits_lrs2_rtype_0 : slot_uop_lrs2_rtype; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_frs3_en = io_in_uop_valid_0 ? io_in_uop_bits_frs3_en_0 : slot_uop_frs3_en; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_fp_val = io_in_uop_valid_0 ? io_in_uop_bits_fp_val_0 : slot_uop_fp_val; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_fp_single = io_in_uop_valid_0 ? io_in_uop_bits_fp_single_0 : slot_uop_fp_single; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_xcpt_pf_if = io_in_uop_valid_0 ? io_in_uop_bits_xcpt_pf_if_0 : slot_uop_xcpt_pf_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_xcpt_ae_if = io_in_uop_valid_0 ? io_in_uop_bits_xcpt_ae_if_0 : slot_uop_xcpt_ae_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_xcpt_ma_if = io_in_uop_valid_0 ? io_in_uop_bits_xcpt_ma_if_0 : slot_uop_xcpt_ma_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_bp_debug_if = io_in_uop_valid_0 ? io_in_uop_bits_bp_debug_if_0 : slot_uop_bp_debug_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_bp_xcpt_if = io_in_uop_valid_0 ? io_in_uop_bits_bp_xcpt_if_0 : slot_uop_bp_xcpt_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_debug_fsrc = io_in_uop_valid_0 ? io_in_uop_bits_debug_fsrc_0 : slot_uop_debug_fsrc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_debug_tsrc = io_in_uop_valid_0 ? io_in_uop_bits_debug_tsrc_0 : slot_uop_debug_tsrc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire _T_11 = state == 2'h2; // @[issue-slot.scala:86:22, :134:25] wire _T_7 = io_grant_0 & state == 2'h1 | io_grant_0 & _T_11 & p1 & p2 & ppred; // @[issue-slot.scala:69:7, :86:22, :87:22, :88:22, :90:22, :133:{26,36,52}, :134:{15,25,40,46,52}] wire _T_12 = io_grant_0 & _T_11; // @[issue-slot.scala:69:7, :134:25, :139:25] wire _T_14 = io_ldspec_miss_0 & (p1_poisoned | p2_poisoned); // @[issue-slot.scala:69:7, :95:28, :96:28, :140:{28,44}] wire _GEN = _T_12 & ~_T_14; // @[issue-slot.scala:126:14, :139:{25,51}, :140:{11,28,62}, :141:18] wire _GEN_0 = io_kill_0 | _T_7; // @[issue-slot.scala:69:7, :102:25, :131:18, :133:52, :134:63, :139:51] wire _GEN_1 = _GEN_0 | ~(_T_12 & ~_T_14 & p1); // @[issue-slot.scala:87:22, :102:25, :131:18, :134:63, :139:{25,51}, :140:{11,28,62}, :142:17, :143:23] assign next_uopc = _GEN_1 ? slot_uop_uopc : 7'h3; // @[issue-slot.scala:82:29, :102:25, :131:18, :134:63, :139:51] assign next_lrs1_rtype = _GEN_1 ? slot_uop_lrs1_rtype : 2'h2; // @[issue-slot.scala:83:29, :102:25, :131:18, :134:63, :139:51] wire _GEN_2 = _GEN_0 | ~_GEN | p1; // @[issue-slot.scala:87:22, :102:25, :126:14, :131:18, :134:63, :139:51, :140:62, :141:18, :142:17] assign next_lrs2_rtype = _GEN_2 ? slot_uop_lrs2_rtype : 2'h2; // @[issue-slot.scala:84:29, :102:25, :131:18, :134:63, :139:51, :140:62, :142:17] wire _p1_T = ~io_in_uop_bits_prs1_busy_0; // @[issue-slot.scala:69:7, :169:11] wire _p2_T = ~io_in_uop_bits_prs2_busy_0; // @[issue-slot.scala:69:7, :170:11] wire _p3_T = ~io_in_uop_bits_prs3_busy_0; // @[issue-slot.scala:69:7, :171:11] wire _ppred_T = ~io_in_uop_bits_ppred_busy_0; // @[issue-slot.scala:69:7, :172:14] wire _T_22 = io_ldspec_miss_0 & next_p1_poisoned; // @[issue-slot.scala:69:7, :99:29, :175:24] wire _T_27 = io_ldspec_miss_0 & next_p2_poisoned; // @[issue-slot.scala:69:7, :100:29, :179:24] wire _T_61 = io_spec_ld_wakeup_0_valid_0 & io_spec_ld_wakeup_0_bits_0 == next_uop_prs1 & next_uop_lrs1_rtype == 2'h0; // @[issue-slot.scala:69:7, :103:21, :209:38, :210:{33,51}, :211:27] wire _T_69 = io_spec_ld_wakeup_0_valid_0 & io_spec_ld_wakeup_0_bits_0 == next_uop_prs2 & next_uop_lrs2_rtype == 2'h0; // @[issue-slot.scala:69:7, :103:21, :216:38, :217:{33,51}, :218:27]

Generate the Verilog code corresponding to the following Chisel files. File Tile.scala: // See README.md for license details. package gemmini import chisel3._ import chisel3.util._ import Util._ /** * A Tile is a purely combinational 2D array of passThrough PEs. * a, b, s, and in_propag are broadcast across the entire array and are passed through to the Tile's outputs * @param width The data width of each PE in bits * @param rows Number of PEs on each row * @param columns Number of PEs on each column */ class Tile[T <: Data](inputType: T, outputType: T, accType: T, df: Dataflow.Value, tree_reduction: Boolean, max_simultaneous_matmuls: Int, val rows: Int, val columns: Int)(implicit ev: Arithmetic[T]) extends Module { val io = IO(new Bundle { val in_a = Input(Vec(rows, inputType)) val in_b = Input(Vec(columns, outputType)) // This is the output of the tile next to it val in_d = Input(Vec(columns, outputType)) val in_control = Input(Vec(columns, new PEControl(accType))) val in_id = Input(Vec(columns, UInt(log2Up(max_simultaneous_matmuls).W))) val in_last = Input(Vec(columns, Bool())) val out_a = Output(Vec(rows, inputType)) val out_c = Output(Vec(columns, outputType)) val out_b = Output(Vec(columns, outputType)) val out_control = Output(Vec(columns, new PEControl(accType))) val out_id = Output(Vec(columns, UInt(log2Up(max_simultaneous_matmuls).W))) val out_last = Output(Vec(columns, Bool())) val in_valid = Input(Vec(columns, Bool())) val out_valid = Output(Vec(columns, Bool())) val bad_dataflow = Output(Bool()) }) import ev._ val tile = Seq.fill(rows, columns)(Module(new PE(inputType, outputType, accType, df, max_simultaneous_matmuls))) val tileT = tile.transpose // TODO: abstract hori/vert broadcast, all these connections look the same // Broadcast 'a' horizontally across the Tile for (r <- 0 until rows) { tile(r).foldLeft(io.in_a(r)) { case (in_a, pe) => pe.io.in_a := in_a pe.io.out_a } } // Broadcast 'b' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_b(c)) { case (in_b, pe) => pe.io.in_b := (if (tree_reduction) in_b.zero else in_b) pe.io.out_b } } // Broadcast 'd' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_d(c)) { case (in_d, pe) => pe.io.in_d := in_d pe.io.out_c } } // Broadcast 'control' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_control(c)) { case (in_ctrl, pe) => pe.io.in_control := in_ctrl pe.io.out_control } } // Broadcast 'garbage' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_valid(c)) { case (v, pe) => pe.io.in_valid := v pe.io.out_valid } } // Broadcast 'id' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_id(c)) { case (id, pe) => pe.io.in_id := id pe.io.out_id } } // Broadcast 'last' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_last(c)) { case (last, pe) => pe.io.in_last := last pe.io.out_last } } // Drive the Tile's bottom IO for (c <- 0 until columns) { io.out_c(c) := tile(rows-1)(c).io.out_c io.out_control(c) := tile(rows-1)(c).io.out_control io.out_id(c) := tile(rows-1)(c).io.out_id io.out_last(c) := tile(rows-1)(c).io.out_last io.out_valid(c) := tile(rows-1)(c).io.out_valid io.out_b(c) := { if (tree_reduction) { val prods = tileT(c).map(_.io.out_b) accumulateTree(prods :+ io.in_b(c)) } else { tile(rows - 1)(c).io.out_b } } } io.bad_dataflow := tile.map(_.map(_.io.bad_dataflow).reduce(_||_)).reduce(_||_) // Drive the Tile's right IO for (r <- 0 until rows) { io.out_a(r) := tile(r)(columns-1).io.out_a } }

module Tile_166( // @[Tile.scala:16:7] input clock, // @[Tile.scala:16:7] input reset, // @[Tile.scala:16:7] input [7:0] io_in_a_0, // @[Tile.scala:17:14] input [19:0] io_in_b_0, // @[Tile.scala:17:14] input [19:0] io_in_d_0, // @[Tile.scala:17:14] input io_in_control_0_dataflow, // @[Tile.scala:17:14] input io_in_control_0_propagate, // @[Tile.scala:17:14] input [4:0] io_in_control_0_shift, // @[Tile.scala:17:14] input [2:0] io_in_id_0, // @[Tile.scala:17:14] input io_in_last_0, // @[Tile.scala:17:14] output [7:0] io_out_a_0, // @[Tile.scala:17:14] output [19:0] io_out_c_0, // @[Tile.scala:17:14] output [19:0] io_out_b_0, // @[Tile.scala:17:14] output io_out_control_0_dataflow, // @[Tile.scala:17:14] output io_out_control_0_propagate, // @[Tile.scala:17:14] output [4:0] io_out_control_0_shift, // @[Tile.scala:17:14] output [2:0] io_out_id_0, // @[Tile.scala:17:14] output io_out_last_0, // @[Tile.scala:17:14] input io_in_valid_0, // @[Tile.scala:17:14] output io_out_valid_0, // @[Tile.scala:17:14] output io_bad_dataflow // @[Tile.scala:17:14] ); wire [7:0] io_in_a_0_0 = io_in_a_0; // @[Tile.scala:16:7] wire [19:0] io_in_b_0_0 = io_in_b_0; // @[Tile.scala:16:7] wire [19:0] io_in_d_0_0 = io_in_d_0; // @[Tile.scala:16:7] wire io_in_control_0_dataflow_0 = io_in_control_0_dataflow; // @[Tile.scala:16:7] wire io_in_control_0_propagate_0 = io_in_control_0_propagate; // @[Tile.scala:16:7] wire [4:0] io_in_control_0_shift_0 = io_in_control_0_shift; // @[Tile.scala:16:7] wire [2:0] io_in_id_0_0 = io_in_id_0; // @[Tile.scala:16:7] wire io_in_last_0_0 = io_in_last_0; // @[Tile.scala:16:7] wire io_in_valid_0_0 = io_in_valid_0; // @[Tile.scala:16:7] wire [7:0] io_out_a_0_0; // @[Tile.scala:16:7] wire [19:0] io_out_c_0_0; // @[Tile.scala:16:7] wire [19:0] io_out_b_0_0; // @[Tile.scala:16:7] wire io_out_control_0_dataflow_0; // @[Tile.scala:16:7] wire io_out_control_0_propagate_0; // @[Tile.scala:16:7] wire [4:0] io_out_control_0_shift_0; // @[Tile.scala:16:7] wire [2:0] io_out_id_0_0; // @[Tile.scala:16:7] wire io_out_last_0_0; // @[Tile.scala:16:7] wire io_out_valid_0_0; // @[Tile.scala:16:7] wire io_bad_dataflow_0; // @[Tile.scala:16:7] PE_422 tile_0_0 ( // @[Tile.scala:42:44] .clock (clock), .reset (reset), .io_in_a (io_in_a_0_0), // @[Tile.scala:16:7] .io_in_b (io_in_b_0_0), // @[Tile.scala:16:7] .io_in_d (io_in_d_0_0), // @[Tile.scala:16:7] .io_out_a (io_out_a_0_0), .io_out_b (io_out_b_0_0), .io_out_c (io_out_c_0_0), .io_in_control_dataflow (io_in_control_0_dataflow_0), // @[Tile.scala:16:7] .io_in_control_propagate (io_in_control_0_propagate_0), // @[Tile.scala:16:7] .io_in_control_shift (io_in_control_0_shift_0), // @[Tile.scala:16:7] .io_out_control_dataflow (io_out_control_0_dataflow_0), .io_out_control_propagate (io_out_control_0_propagate_0), .io_out_control_shift (io_out_control_0_shift_0), .io_in_id (io_in_id_0_0), // @[Tile.scala:16:7] .io_out_id (io_out_id_0_0), .io_in_last (io_in_last_0_0), // @[Tile.scala:16:7] .io_out_last (io_out_last_0_0), .io_in_valid (io_in_valid_0_0), // @[Tile.scala:16:7] .io_out_valid (io_out_valid_0_0), .io_bad_dataflow (io_bad_dataflow_0) ); // @[Tile.scala:42:44] assign io_out_a_0 = io_out_a_0_0; // @[Tile.scala:16:7] assign io_out_c_0 = io_out_c_0_0; // @[Tile.scala:16:7] assign io_out_b_0 = io_out_b_0_0; // @[Tile.scala:16:7] assign io_out_control_0_dataflow = io_out_control_0_dataflow_0; // @[Tile.scala:16:7] assign io_out_control_0_propagate = io_out_control_0_propagate_0; // @[Tile.scala:16:7] assign io_out_control_0_shift = io_out_control_0_shift_0; // @[Tile.scala:16:7] assign io_out_id_0 = io_out_id_0_0; // @[Tile.scala:16:7] assign io_out_last_0 = io_out_last_0_0; // @[Tile.scala:16:7] assign io_out_valid_0 = io_out_valid_0_0; // @[Tile.scala:16:7] assign io_bad_dataflow = io_bad_dataflow_0; // @[Tile.scala:16:7] endmodule

Generate the Verilog code corresponding to the following Chisel files. File Tile.scala: // See README.md for license details. package gemmini import chisel3._ import chisel3.util._ import Util._ /** * A Tile is a purely combinational 2D array of passThrough PEs. * a, b, s, and in_propag are broadcast across the entire array and are passed through to the Tile's outputs * @param width The data width of each PE in bits * @param rows Number of PEs on each row * @param columns Number of PEs on each column */ class Tile[T <: Data](inputType: T, outputType: T, accType: T, df: Dataflow.Value, tree_reduction: Boolean, max_simultaneous_matmuls: Int, val rows: Int, val columns: Int)(implicit ev: Arithmetic[T]) extends Module { val io = IO(new Bundle { val in_a = Input(Vec(rows, inputType)) val in_b = Input(Vec(columns, outputType)) // This is the output of the tile next to it val in_d = Input(Vec(columns, outputType)) val in_control = Input(Vec(columns, new PEControl(accType))) val in_id = Input(Vec(columns, UInt(log2Up(max_simultaneous_matmuls).W))) val in_last = Input(Vec(columns, Bool())) val out_a = Output(Vec(rows, inputType)) val out_c = Output(Vec(columns, outputType)) val out_b = Output(Vec(columns, outputType)) val out_control = Output(Vec(columns, new PEControl(accType))) val out_id = Output(Vec(columns, UInt(log2Up(max_simultaneous_matmuls).W))) val out_last = Output(Vec(columns, Bool())) val in_valid = Input(Vec(columns, Bool())) val out_valid = Output(Vec(columns, Bool())) val bad_dataflow = Output(Bool()) }) import ev._ val tile = Seq.fill(rows, columns)(Module(new PE(inputType, outputType, accType, df, max_simultaneous_matmuls))) val tileT = tile.transpose // TODO: abstract hori/vert broadcast, all these connections look the same // Broadcast 'a' horizontally across the Tile for (r <- 0 until rows) { tile(r).foldLeft(io.in_a(r)) { case (in_a, pe) => pe.io.in_a := in_a pe.io.out_a } } // Broadcast 'b' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_b(c)) { case (in_b, pe) => pe.io.in_b := (if (tree_reduction) in_b.zero else in_b) pe.io.out_b } } // Broadcast 'd' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_d(c)) { case (in_d, pe) => pe.io.in_d := in_d pe.io.out_c } } // Broadcast 'control' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_control(c)) { case (in_ctrl, pe) => pe.io.in_control := in_ctrl pe.io.out_control } } // Broadcast 'garbage' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_valid(c)) { case (v, pe) => pe.io.in_valid := v pe.io.out_valid } } // Broadcast 'id' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_id(c)) { case (id, pe) => pe.io.in_id := id pe.io.out_id } } // Broadcast 'last' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_last(c)) { case (last, pe) => pe.io.in_last := last pe.io.out_last } } // Drive the Tile's bottom IO for (c <- 0 until columns) { io.out_c(c) := tile(rows-1)(c).io.out_c io.out_control(c) := tile(rows-1)(c).io.out_control io.out_id(c) := tile(rows-1)(c).io.out_id io.out_last(c) := tile(rows-1)(c).io.out_last io.out_valid(c) := tile(rows-1)(c).io.out_valid io.out_b(c) := { if (tree_reduction) { val prods = tileT(c).map(_.io.out_b) accumulateTree(prods :+ io.in_b(c)) } else { tile(rows - 1)(c).io.out_b } } } io.bad_dataflow := tile.map(_.map(_.io.bad_dataflow).reduce(_||_)).reduce(_||_) // Drive the Tile's right IO for (r <- 0 until rows) { io.out_a(r) := tile(r)(columns-1).io.out_a } }

module Tile_230( // @[Tile.scala:16:7] input clock, // @[Tile.scala:16:7] input reset, // @[Tile.scala:16:7] input [7:0] io_in_a_0, // @[Tile.scala:17:14] input [19:0] io_in_b_0, // @[Tile.scala:17:14] input [19:0] io_in_d_0, // @[Tile.scala:17:14] input io_in_control_0_dataflow, // @[Tile.scala:17:14] input io_in_control_0_propagate, // @[Tile.scala:17:14] input [4:0] io_in_control_0_shift, // @[Tile.scala:17:14] input [2:0] io_in_id_0, // @[Tile.scala:17:14] input io_in_last_0, // @[Tile.scala:17:14] output [7:0] io_out_a_0, // @[Tile.scala:17:14] output [19:0] io_out_c_0, // @[Tile.scala:17:14] output [19:0] io_out_b_0, // @[Tile.scala:17:14] output io_out_control_0_dataflow, // @[Tile.scala:17:14] output io_out_control_0_propagate, // @[Tile.scala:17:14] output [4:0] io_out_control_0_shift, // @[Tile.scala:17:14] output [2:0] io_out_id_0, // @[Tile.scala:17:14] output io_out_last_0, // @[Tile.scala:17:14] input io_in_valid_0, // @[Tile.scala:17:14] output io_out_valid_0 // @[Tile.scala:17:14] ); wire [7:0] io_in_a_0_0 = io_in_a_0; // @[Tile.scala:16:7] wire [19:0] io_in_b_0_0 = io_in_b_0; // @[Tile.scala:16:7] wire [19:0] io_in_d_0_0 = io_in_d_0; // @[Tile.scala:16:7] wire io_in_control_0_dataflow_0 = io_in_control_0_dataflow; // @[Tile.scala:16:7] wire io_in_control_0_propagate_0 = io_in_control_0_propagate; // @[Tile.scala:16:7] wire [4:0] io_in_control_0_shift_0 = io_in_control_0_shift; // @[Tile.scala:16:7] wire [2:0] io_in_id_0_0 = io_in_id_0; // @[Tile.scala:16:7] wire io_in_last_0_0 = io_in_last_0; // @[Tile.scala:16:7] wire io_in_valid_0_0 = io_in_valid_0; // @[Tile.scala:16:7] wire io_bad_dataflow = 1'h0; // @[Tile.scala:16:7, :17:14, :42:44] wire [7:0] io_out_a_0_0; // @[Tile.scala:16:7] wire [19:0] io_out_c_0_0; // @[Tile.scala:16:7] wire [19:0] io_out_b_0_0; // @[Tile.scala:16:7] wire io_out_control_0_dataflow_0; // @[Tile.scala:16:7] wire io_out_control_0_propagate_0; // @[Tile.scala:16:7] wire [4:0] io_out_control_0_shift_0; // @[Tile.scala:16:7] wire [2:0] io_out_id_0_0; // @[Tile.scala:16:7] wire io_out_last_0_0; // @[Tile.scala:16:7] wire io_out_valid_0_0; // @[Tile.scala:16:7] PE_486 tile_0_0 ( // @[Tile.scala:42:44] .clock (clock), .reset (reset), .io_in_a (io_in_a_0_0), // @[Tile.scala:16:7] .io_in_b (io_in_b_0_0), // @[Tile.scala:16:7] .io_in_d (io_in_d_0_0), // @[Tile.scala:16:7] .io_out_a (io_out_a_0_0), .io_out_b (io_out_b_0_0), .io_out_c (io_out_c_0_0), .io_in_control_dataflow (io_in_control_0_dataflow_0), // @[Tile.scala:16:7] .io_in_control_propagate (io_in_control_0_propagate_0), // @[Tile.scala:16:7] .io_in_control_shift (io_in_control_0_shift_0), // @[Tile.scala:16:7] .io_out_control_dataflow (io_out_control_0_dataflow_0), .io_out_control_propagate (io_out_control_0_propagate_0), .io_out_control_shift (io_out_control_0_shift_0), .io_in_id (io_in_id_0_0), // @[Tile.scala:16:7] .io_out_id (io_out_id_0_0), .io_in_last (io_in_last_0_0), // @[Tile.scala:16:7] .io_out_last (io_out_last_0_0), .io_in_valid (io_in_valid_0_0), // @[Tile.scala:16:7] .io_out_valid (io_out_valid_0_0) ); // @[Tile.scala:42:44] assign io_out_a_0 = io_out_a_0_0; // @[Tile.scala:16:7] assign io_out_c_0 = io_out_c_0_0; // @[Tile.scala:16:7] assign io_out_b_0 = io_out_b_0_0; // @[Tile.scala:16:7] assign io_out_control_0_dataflow = io_out_control_0_dataflow_0; // @[Tile.scala:16:7] assign io_out_control_0_propagate = io_out_control_0_propagate_0; // @[Tile.scala:16:7] assign io_out_control_0_shift = io_out_control_0_shift_0; // @[Tile.scala:16:7] assign io_out_id_0 = io_out_id_0_0; // @[Tile.scala:16:7] assign io_out_last_0 = io_out_last_0_0; // @[Tile.scala:16:7] assign io_out_valid_0 = io_out_valid_0_0; // @[Tile.scala:16:7] endmodule

Generate the Verilog code corresponding to the following Chisel files. File HellaCache.scala: // See LICENSE.SiFive for license details. // See LICENSE.Berkeley for license details. package freechips.rocketchip.rocket import chisel3.{dontTouch, _} import chisel3.util._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.bundlebridge._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.amba.AMBAProtField import freechips.rocketchip.diplomacy.{IdRange, TransferSizes, RegionType} import freechips.rocketchip.tile.{L1CacheParams, HasL1CacheParameters, HasCoreParameters, CoreBundle, HasNonDiplomaticTileParameters, BaseTile, HasTileParameters} import freechips.rocketchip.tilelink.{TLMasterParameters, TLClientNode, TLMasterPortParameters, TLEdgeOut, TLWidthWidget, TLFIFOFixer, ClientMetadata} import freechips.rocketchip.util.{Code, RandomReplacement, ParameterizedBundle} import freechips.rocketchip.util.{BooleanToAugmentedBoolean, IntToAugmentedInt} import scala.collection.mutable.ListBuffer case class DCacheParams( nSets: Int = 64, nWays: Int = 4, rowBits: Int = 64, subWordBits: Option[Int] = None, replacementPolicy: String = "random", nTLBSets: Int = 1, nTLBWays: Int = 32, nTLBBasePageSectors: Int = 4, nTLBSuperpages: Int = 4, tagECC: Option[String] = None, dataECC: Option[String] = None, dataECCBytes: Int = 1, nMSHRs: Int = 1, nSDQ: Int = 17, nRPQ: Int = 16, nMMIOs: Int = 1, blockBytes: Int = 64, separateUncachedResp: Boolean = false, acquireBeforeRelease: Boolean = false, pipelineWayMux: Boolean = false, clockGate: Boolean = false, scratch: Option[BigInt] = None) extends L1CacheParams { def tagCode: Code = Code.fromString(tagECC) def dataCode: Code = Code.fromString(dataECC) def dataScratchpadBytes: Int = scratch.map(_ => nSets*blockBytes).getOrElse(0) def replacement = new RandomReplacement(nWays) def silentDrop: Boolean = !acquireBeforeRelease require((!scratch.isDefined || nWays == 1), "Scratchpad only allowed in direct-mapped cache.") require((!scratch.isDefined || nMSHRs == 0), "Scratchpad only allowed in blocking cache.") if (scratch.isEmpty) require(isPow2(nSets), s"nSets($nSets) must be pow2") } trait HasL1HellaCacheParameters extends HasL1CacheParameters with HasCoreParameters { val cacheParams = tileParams.dcache.get val cfg = cacheParams def wordBits = coreDataBits def wordBytes = coreDataBytes def subWordBits = cacheParams.subWordBits.getOrElse(wordBits) def subWordBytes = subWordBits / 8 def wordOffBits = log2Up(wordBytes) def beatBytes = cacheBlockBytes / cacheDataBeats def beatWords = beatBytes / wordBytes def beatOffBits = log2Up(beatBytes) def idxMSB = untagBits-1 def idxLSB = blockOffBits def offsetmsb = idxLSB-1 def offsetlsb = wordOffBits def rowWords = rowBits/wordBits def doNarrowRead = coreDataBits * nWays % rowBits == 0 def eccBytes = cacheParams.dataECCBytes val eccBits = cacheParams.dataECCBytes * 8 val encBits = cacheParams.dataCode.width(eccBits) val encWordBits = encBits * (wordBits / eccBits) def encDataBits = cacheParams.dataCode.width(coreDataBits) // NBDCache only def encRowBits = encDataBits*rowWords def lrscCycles = coreParams.lrscCycles // ISA requires 16-insn LRSC sequences to succeed def lrscBackoff = 3 // disallow LRSC reacquisition briefly def blockProbeAfterGrantCycles = 8 // give the processor some time to issue a request after a grant def nIOMSHRs = cacheParams.nMMIOs def maxUncachedInFlight = cacheParams.nMMIOs def dataScratchpadSize = cacheParams.dataScratchpadBytes require(rowBits >= coreDataBits, s"rowBits($rowBits) < coreDataBits($coreDataBits)") if (!usingDataScratchpad) require(rowBits == cacheDataBits, s"rowBits($rowBits) != cacheDataBits($cacheDataBits)") // would need offset addr for puts if data width < xlen require(xLen <= cacheDataBits, s"xLen($xLen) > cacheDataBits($cacheDataBits)") } abstract class L1HellaCacheModule(implicit val p: Parameters) extends Module with HasL1HellaCacheParameters abstract class L1HellaCacheBundle(implicit val p: Parameters) extends ParameterizedBundle()(p) with HasL1HellaCacheParameters /** Bundle definitions for HellaCache interfaces */ trait HasCoreMemOp extends HasL1HellaCacheParameters { val addr = UInt(coreMaxAddrBits.W) val idx = (usingVM && untagBits > pgIdxBits).option(UInt(coreMaxAddrBits.W)) val tag = UInt((coreParams.dcacheReqTagBits + log2Ceil(dcacheArbPorts)).W) val cmd = UInt(M_SZ.W) val size = UInt(log2Ceil(coreDataBytes.log2 + 1).W) val signed = Bool() val dprv = UInt(PRV.SZ.W) val dv = Bool() } trait HasCoreData extends HasCoreParameters { val data = UInt(coreDataBits.W) val mask = UInt(coreDataBytes.W) } class HellaCacheReqInternal(implicit p: Parameters) extends CoreBundle()(p) with HasCoreMemOp { val phys = Bool() val no_resp = Bool() // The dcache may omit generating a response for this request val no_alloc = Bool() val no_xcpt = Bool() } class HellaCacheReq(implicit p: Parameters) extends HellaCacheReqInternal()(p) with HasCoreData class HellaCacheResp(implicit p: Parameters) extends CoreBundle()(p) with HasCoreMemOp with HasCoreData { val replay = Bool() val has_data = Bool() val data_word_bypass = UInt(coreDataBits.W) val data_raw = UInt(coreDataBits.W) val store_data = UInt(coreDataBits.W) } class AlignmentExceptions extends Bundle { val ld = Bool() val st = Bool() } class HellaCacheExceptions extends Bundle { val ma = new AlignmentExceptions val pf = new AlignmentExceptions val gf = new AlignmentExceptions val ae = new AlignmentExceptions } class HellaCacheWriteData(implicit p: Parameters) extends CoreBundle()(p) with HasCoreData class HellaCachePerfEvents extends Bundle { val acquire = Bool() val release = Bool() val grant = Bool() val tlbMiss = Bool() val blocked = Bool() val canAcceptStoreThenLoad = Bool() val canAcceptStoreThenRMW = Bool() val canAcceptLoadThenLoad = Bool() val storeBufferEmptyAfterLoad = Bool() val storeBufferEmptyAfterStore = Bool() } // interface between D$ and processor/DTLB class HellaCacheIO(implicit p: Parameters) extends CoreBundle()(p) { val req = Decoupled(new HellaCacheReq) val s1_kill = Output(Bool()) // kill previous cycle's req val s1_data = Output(new HellaCacheWriteData()) // data for previous cycle's req val s2_nack = Input(Bool()) // req from two cycles ago is rejected val s2_nack_cause_raw = Input(Bool()) // reason for nack is store-load RAW hazard (performance hint) val s2_kill = Output(Bool()) // kill req from two cycles ago val s2_uncached = Input(Bool()) // advisory signal that the access is MMIO val s2_paddr = Input(UInt(paddrBits.W)) // translated address val resp = Flipped(Valid(new HellaCacheResp)) val replay_next = Input(Bool()) val s2_xcpt = Input(new HellaCacheExceptions) val s2_gpa = Input(UInt(vaddrBitsExtended.W)) val s2_gpa_is_pte = Input(Bool()) val uncached_resp = tileParams.dcache.get.separateUncachedResp.option(Flipped(Decoupled(new HellaCacheResp))) val ordered = Input(Bool()) val store_pending = Input(Bool()) // there is a store in a store buffer somewhere val perf = Input(new HellaCachePerfEvents()) val keep_clock_enabled = Output(Bool()) // should D$ avoid clock-gating itself? val clock_enabled = Input(Bool()) // is D$ currently being clocked? } /** Base classes for Diplomatic TL2 HellaCaches */ abstract class HellaCache(tileId: Int)(implicit p: Parameters) extends LazyModule with HasNonDiplomaticTileParameters { protected val cfg = tileParams.dcache.get protected def cacheClientParameters = cfg.scratch.map(x => Seq()).getOrElse(Seq(TLMasterParameters.v1( name = s"Core ${tileId} DCache", sourceId = IdRange(0, 1 max cfg.nMSHRs), supportsProbe = TransferSizes(cfg.blockBytes, cfg.blockBytes)))) protected def mmioClientParameters = Seq(TLMasterParameters.v1( name = s"Core ${tileId} DCache MMIO", sourceId = IdRange(firstMMIO, firstMMIO + cfg.nMMIOs), requestFifo = true)) def firstMMIO = (cacheClientParameters.map(_.sourceId.end) :+ 0).max val node = TLClientNode(Seq(TLMasterPortParameters.v1( clients = cacheClientParameters ++ mmioClientParameters, minLatency = 1, requestFields = tileParams.core.useVM.option(Seq()).getOrElse(Seq(AMBAProtField()))))) val hartIdSinkNodeOpt = cfg.scratch.map(_ => BundleBridgeSink[UInt]()) val mmioAddressPrefixSinkNodeOpt = cfg.scratch.map(_ => BundleBridgeSink[UInt]()) val module: HellaCacheModule def flushOnFenceI = cfg.scratch.isEmpty && !node.edges.out(0).manager.managers.forall(m => !m.supportsAcquireB || !m.executable || m.regionType >= RegionType.TRACKED || m.regionType <= RegionType.IDEMPOTENT) def canSupportCFlushLine = !usingVM || cfg.blockBytes * cfg.nSets <= (1 << pgIdxBits) require(!tileParams.core.haveCFlush || cfg.scratch.isEmpty, "CFLUSH_D_L1 instruction requires a D$") } class HellaCacheBundle(implicit p: Parameters) extends CoreBundle()(p) { val cpu = Flipped(new HellaCacheIO) val ptw = new TLBPTWIO() val errors = new DCacheErrors val tlb_port = new DCacheTLBPort } class HellaCacheModule(outer: HellaCache) extends LazyModuleImp(outer) with HasL1HellaCacheParameters { implicit val edge: TLEdgeOut = outer.node.edges.out(0) val (tl_out, _) = outer.node.out(0) val io = IO(new HellaCacheBundle) val io_hartid = outer.hartIdSinkNodeOpt.map(_.bundle) val io_mmio_address_prefix = outer.mmioAddressPrefixSinkNodeOpt.map(_.bundle) dontTouch(io.cpu.resp) // Users like to monitor these fields even if the core ignores some signals dontTouch(io.cpu.s1_data) require(rowBits == edge.bundle.dataBits) private val fifoManagers = edge.manager.managers.filter(TLFIFOFixer.allVolatile) fifoManagers.foreach { m => require (m.fifoId == fifoManagers.head.fifoId, s"IOMSHRs must be FIFO for all regions with effects, but HellaCache sees\n"+ s"${m.nodePath.map(_.name)}\nversus\n${fifoManagers.head.nodePath.map(_.name)}") } } /** Support overriding which HellaCache is instantiated */ case object BuildHellaCache extends Field[BaseTile => Parameters => HellaCache](HellaCacheFactory.apply) object HellaCacheFactory { def apply(tile: BaseTile)(p: Parameters): HellaCache = { if (tile.tileParams.dcache.get.nMSHRs == 0) new DCache(tile.tileId, tile.crossing)(p) else new NonBlockingDCache(tile.tileId)(p) } } /** Mix-ins for constructing tiles that have a HellaCache */ trait HasHellaCache { this: BaseTile => val module: HasHellaCacheModule implicit val p: Parameters var nDCachePorts = 0 lazy val dcache: HellaCache = LazyModule(p(BuildHellaCache)(this)(p)) tlMasterXbar.node := TLWidthWidget(tileParams.dcache.get.rowBits/8) := dcache.node dcache.hartIdSinkNodeOpt.map { _ := hartIdNexusNode } dcache.mmioAddressPrefixSinkNodeOpt.map { _ := mmioAddressPrefixNexusNode } InModuleBody { dcache.module.io.tlb_port := DontCare } } trait HasHellaCacheModule { val outer: HasHellaCache with HasTileParameters implicit val p: Parameters val dcachePorts = ListBuffer[HellaCacheIO]() val dcacheArb = Module(new HellaCacheArbiter(outer.nDCachePorts)(outer.p)) outer.dcache.module.io.cpu <> dcacheArb.io.mem } /** Metadata array used for all HellaCaches */ class L1Metadata(implicit p: Parameters) extends L1HellaCacheBundle()(p) { val coh = new ClientMetadata val tag = UInt(tagBits.W) } object L1Metadata { def apply(tag: Bits, coh: ClientMetadata)(implicit p: Parameters) = { val meta = Wire(new L1Metadata) meta.tag := tag meta.coh := coh meta } } class L1MetaReadReq(implicit p: Parameters) extends L1HellaCacheBundle()(p) { val idx = UInt(idxBits.W) val way_en = UInt(nWays.W) val tag = UInt(tagBits.W) } class L1MetaWriteReq(implicit p: Parameters) extends L1MetaReadReq()(p) { val data = new L1Metadata } class L1MetadataArray[T <: L1Metadata](onReset: () => T)(implicit p: Parameters) extends L1HellaCacheModule()(p) { val rstVal = onReset() val io = IO(new Bundle { val read = Flipped(Decoupled(new L1MetaReadReq)) val write = Flipped(Decoupled(new L1MetaWriteReq)) val resp = Output(Vec(nWays, rstVal.cloneType)) }) val rst_cnt = RegInit(0.U(log2Up(nSets+1).W)) val rst = rst_cnt < nSets.U val waddr = Mux(rst, rst_cnt, io.write.bits.idx) val wdata = Mux(rst, rstVal, io.write.bits.data).asUInt val wmask = Mux(rst || (nWays == 1).B, (-1).S, io.write.bits.way_en.asSInt).asBools val rmask = Mux(rst || (nWays == 1).B, (-1).S, io.read.bits.way_en.asSInt).asBools when (rst) { rst_cnt := rst_cnt+1.U } val metabits = rstVal.getWidth val tag_array = SyncReadMem(nSets, Vec(nWays, UInt(metabits.W))) val wen = rst || io.write.valid when (wen) { tag_array.write(waddr, VecInit.fill(nWays)(wdata), wmask) } io.resp := tag_array.read(io.read.bits.idx, io.read.fire).map(_.asTypeOf(chiselTypeOf(rstVal))) io.read.ready := !wen // so really this could be a 6T RAM io.write.ready := !rst } File Interrupts.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tile import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import freechips.rocketchip.resources.{Device, DeviceSnippet, Description, ResourceBinding, ResourceInt} import freechips.rocketchip.interrupts.{IntIdentityNode, IntSinkNode, IntSinkPortSimple, IntSourceNode, IntSourcePortSimple} import freechips.rocketchip.util.CanHaveErrors import freechips.rocketchip.resources.{IntToProperty, StringToProperty} import freechips.rocketchip.util.BooleanToAugmentedBoolean class NMI(val w: Int) extends Bundle { val rnmi = Bool() val rnmi_interrupt_vector = UInt(w.W) val rnmi_exception_vector = UInt(w.W) } class TileInterrupts(implicit p: Parameters) extends CoreBundle()(p) { val debug = Bool() val mtip = Bool() val msip = Bool() val meip = Bool() val seip = usingSupervisor.option(Bool()) val lip = Vec(coreParams.nLocalInterrupts, Bool()) val nmi = usingNMI.option(new NMI(resetVectorLen)) } // Use diplomatic interrupts to external interrupts from the subsystem into the tile trait SinksExternalInterrupts { this: BaseTile => val intInwardNode = intXbar.intnode :=* IntIdentityNode()(ValName("int_local")) protected val intSinkNode = IntSinkNode(IntSinkPortSimple()) intSinkNode := intXbar.intnode def cpuDevice: Device val intcDevice = new DeviceSnippet { override def parent = Some(cpuDevice) def describe(): Description = { Description("interrupt-controller", Map( "compatible" -> "riscv,cpu-intc".asProperty, "interrupt-controller" -> Nil, "#interrupt-cells" -> 1.asProperty)) } } ResourceBinding { intSinkNode.edges.in.flatMap(_.source.sources).map { case s => for (i <- s.range.start until s.range.end) { csrIntMap.lift(i).foreach { j => s.resources.foreach { r => r.bind(intcDevice, ResourceInt(j)) } } } } } // TODO: the order of the following two functions must match, and // also match the order which things are connected to the // per-tile crossbar in subsystem.HasTiles.connectInterrupts // debug, msip, mtip, meip, seip, lip offsets in CSRs def csrIntMap: List[Int] = { val nlips = tileParams.core.nLocalInterrupts val seip = if (usingSupervisor) Seq(9) else Nil List(65535, 3, 7, 11) ++ seip ++ List.tabulate(nlips)(_ + 16) } // go from flat diplomatic Interrupts to bundled TileInterrupts def decodeCoreInterrupts(core: TileInterrupts): Unit = { val async_ips = Seq(core.debug) val periph_ips = Seq( core.msip, core.mtip, core.meip) val seip = if (core.seip.isDefined) Seq(core.seip.get) else Nil val core_ips = core.lip val (interrupts, _) = intSinkNode.in(0) (async_ips ++ periph_ips ++ seip ++ core_ips).zip(interrupts).foreach { case(c, i) => c := i } } } trait SourcesExternalNotifications { this: BaseTile => // Report unrecoverable error conditions val haltNode = IntSourceNode(IntSourcePortSimple()) def reportHalt(could_halt: Option[Bool]): Unit = { val (halt_and_catch_fire, _) = haltNode.out(0) halt_and_catch_fire(0) := could_halt.map(RegEnable(true.B, false.B, _)).getOrElse(false.B) } def reportHalt(errors: Seq[CanHaveErrors]): Unit = { reportHalt(errors.flatMap(_.uncorrectable).map(_.valid).reduceOption(_||_)) } // Report when the tile has ceased to retire instructions val ceaseNode = IntSourceNode(IntSourcePortSimple()) def reportCease(could_cease: Option[Bool], quiescenceCycles: Int = 8): Unit = { def waitForQuiescence(cease: Bool): Bool = { // don't report cease until signal is stable for longer than any pipeline depth val count = RegInit(0.U(log2Ceil(quiescenceCycles + 1).W)) val saturated = count >= quiescenceCycles.U when (!cease) { count := 0.U } when (cease && !saturated) { count := count + 1.U } saturated } val (cease, _) = ceaseNode.out(0) cease(0) := could_cease.map{ c => val cease = (waitForQuiescence(c)) // Test-Only Code -- val prev_cease = RegNext(cease, false.B) assert(!(prev_cease & !cease), "CEASE line can not glitch once raised") cease }.getOrElse(false.B) } // Report when the tile is waiting for an interrupt val wfiNode = IntSourceNode(IntSourcePortSimple()) def reportWFI(could_wfi: Option[Bool]): Unit = { val (wfi, _) = wfiNode.out(0) wfi(0) := could_wfi.map(RegNext(_, init=false.B)).getOrElse(false.B) } } File Frontend.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.rocket import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.bundlebridge._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.tile.{CoreBundle, BaseTile} import freechips.rocketchip.tilelink.{TLWidthWidget, TLEdgeOut} import freechips.rocketchip.util.{ClockGate, ShiftQueue, property} import freechips.rocketchip.util.UIntToAugmentedUInt class FrontendReq(implicit p: Parameters) extends CoreBundle()(p) { val pc = UInt(vaddrBitsExtended.W) val speculative = Bool() } class FrontendExceptions extends Bundle { val pf = new Bundle { val inst = Bool() } val gf = new Bundle { val inst = Bool() } val ae = new Bundle { val inst = Bool() } } class FrontendResp(implicit p: Parameters) extends CoreBundle()(p) { val btb = new BTBResp val pc = UInt(vaddrBitsExtended.W) // ID stage PC val data = UInt((fetchWidth * coreInstBits).W) val mask = Bits(fetchWidth.W) val xcpt = new FrontendExceptions val replay = Bool() } class FrontendPerfEvents extends Bundle { val acquire = Bool() val tlbMiss = Bool() } class FrontendIO(implicit p: Parameters) extends CoreBundle()(p) { val might_request = Output(Bool()) val clock_enabled = Input(Bool()) val req = Valid(new FrontendReq) val sfence = Valid(new SFenceReq) val resp = Flipped(Decoupled(new FrontendResp)) val gpa = Flipped(Valid(UInt(vaddrBitsExtended.W))) val gpa_is_pte = Input(Bool()) val btb_update = Valid(new BTBUpdate) val bht_update = Valid(new BHTUpdate) val ras_update = Valid(new RASUpdate) val flush_icache = Output(Bool()) val npc = Input(UInt(vaddrBitsExtended.W)) val perf = Input(new FrontendPerfEvents()) val progress = Output(Bool()) } class Frontend(val icacheParams: ICacheParams, tileId: Int)(implicit p: Parameters) extends LazyModule { lazy val module = new FrontendModule(this) val icache = LazyModule(new ICache(icacheParams, tileId)) val masterNode = icache.masterNode val slaveNode = icache.slaveNode val resetVectorSinkNode = BundleBridgeSink[UInt](Some(() => UInt(masterNode.edges.out.head.bundle.addressBits.W))) } class FrontendBundle(val outer: Frontend) extends CoreBundle()(outer.p) { val cpu = Flipped(new FrontendIO()) val ptw = new TLBPTWIO() val errors = new ICacheErrors } class FrontendModule(outer: Frontend) extends LazyModuleImp(outer) with HasRocketCoreParameters with HasL1ICacheParameters { val io = IO(new FrontendBundle(outer)) val io_reset_vector = outer.resetVectorSinkNode.bundle implicit val edge: TLEdgeOut = outer.masterNode.edges.out(0) val icache = outer.icache.module require(fetchWidth*coreInstBytes == outer.icacheParams.fetchBytes) val fq = withReset(reset.asBool || io.cpu.req.valid) { Module(new ShiftQueue(new FrontendResp, 5, flow = true)) } val clock_en_reg = Reg(Bool()) val clock_en = clock_en_reg || io.cpu.might_request io.cpu.clock_enabled := clock_en assert(!(io.cpu.req.valid || io.cpu.sfence.valid || io.cpu.flush_icache || io.cpu.bht_update.valid || io.cpu.btb_update.valid) || io.cpu.might_request) val gated_clock = if (!rocketParams.clockGate) clock else ClockGate(clock, clock_en, "icache_clock_gate") icache.clock := gated_clock icache.io.clock_enabled := clock_en withClock (gated_clock) { // entering gated-clock domain val tlb = Module(new TLB(true, log2Ceil(fetchBytes), TLBConfig(nTLBSets, nTLBWays, outer.icacheParams.nTLBBasePageSectors, outer.icacheParams.nTLBSuperpages))) val s1_valid = Reg(Bool()) val s2_valid = RegInit(false.B) val s0_fq_has_space = !fq.io.mask(fq.io.mask.getWidth-3) || (!fq.io.mask(fq.io.mask.getWidth-2) && (!s1_valid || !s2_valid)) || (!fq.io.mask(fq.io.mask.getWidth-1) && (!s1_valid && !s2_valid)) val s0_valid = io.cpu.req.valid || s0_fq_has_space s1_valid := s0_valid val s1_pc = Reg(UInt(vaddrBitsExtended.W)) val s1_speculative = Reg(Bool()) val s2_pc = RegInit(t = UInt(vaddrBitsExtended.W), alignPC(io_reset_vector)) val s2_btb_resp_valid = if (usingBTB) Reg(Bool()) else false.B val s2_btb_resp_bits = Reg(new BTBResp) val s2_btb_taken = s2_btb_resp_valid && s2_btb_resp_bits.taken val s2_tlb_resp = Reg(tlb.io.resp.cloneType) val s2_xcpt = s2_tlb_resp.ae.inst || s2_tlb_resp.pf.inst || s2_tlb_resp.gf.inst val s2_speculative = RegInit(false.B) val s2_partial_insn_valid = RegInit(false.B) val s2_partial_insn = Reg(UInt(coreInstBits.W)) val wrong_path = RegInit(false.B) val s1_base_pc = ~(~s1_pc | (fetchBytes - 1).U) val ntpc = s1_base_pc + fetchBytes.U val predicted_npc = WireDefault(ntpc) val predicted_taken = WireDefault(false.B) val s2_replay = Wire(Bool()) s2_replay := (s2_valid && !fq.io.enq.fire) || RegNext(s2_replay && !s0_valid, true.B) val npc = Mux(s2_replay, s2_pc, predicted_npc) s1_pc := io.cpu.npc // consider RVC fetches across blocks to be non-speculative if the first // part was non-speculative val s0_speculative = if (usingCompressed) s1_speculative || s2_valid && !s2_speculative || predicted_taken else true.B s1_speculative := Mux(io.cpu.req.valid, io.cpu.req.bits.speculative, Mux(s2_replay, s2_speculative, s0_speculative)) val s2_redirect = WireDefault(io.cpu.req.valid) s2_valid := false.B when (!s2_replay) { s2_valid := !s2_redirect s2_pc := s1_pc s2_speculative := s1_speculative s2_tlb_resp := tlb.io.resp } val recent_progress_counter_init = 3.U val recent_progress_counter = RegInit(recent_progress_counter_init) val recent_progress = recent_progress_counter > 0.U when(io.ptw.req.fire && recent_progress) { recent_progress_counter := recent_progress_counter - 1.U } when(io.cpu.progress) { recent_progress_counter := recent_progress_counter_init } val s2_kill_speculative_tlb_refill = s2_speculative && !recent_progress io.ptw <> tlb.io.ptw tlb.io.req.valid := s1_valid && !s2_replay tlb.io.req.bits.cmd := M_XRD // Frontend only reads tlb.io.req.bits.vaddr := s1_pc tlb.io.req.bits.passthrough := false.B tlb.io.req.bits.size := log2Ceil(coreInstBytes*fetchWidth).U tlb.io.req.bits.prv := io.ptw.status.prv tlb.io.req.bits.v := io.ptw.status.v tlb.io.sfence := io.cpu.sfence tlb.io.kill := !s2_valid || s2_kill_speculative_tlb_refill icache.io.req.valid := s0_valid icache.io.req.bits.addr := io.cpu.npc icache.io.invalidate := io.cpu.flush_icache icache.io.s1_paddr := tlb.io.resp.paddr icache.io.s2_vaddr := s2_pc icache.io.s1_kill := s2_redirect || tlb.io.resp.miss || s2_replay val s2_can_speculatively_refill = s2_tlb_resp.cacheable && !io.ptw.customCSRs.asInstanceOf[RocketCustomCSRs].disableSpeculativeICacheRefill icache.io.s2_kill := s2_speculative && !s2_can_speculatively_refill || s2_xcpt icache.io.s2_cacheable := s2_tlb_resp.cacheable icache.io.s2_prefetch := s2_tlb_resp.prefetchable && !io.ptw.customCSRs.asInstanceOf[RocketCustomCSRs].disableICachePrefetch fq.io.enq.valid := RegNext(s1_valid) && s2_valid && (icache.io.resp.valid || (s2_kill_speculative_tlb_refill && s2_tlb_resp.miss) || (!s2_tlb_resp.miss && icache.io.s2_kill)) fq.io.enq.bits.pc := s2_pc io.cpu.npc := alignPC(Mux(io.cpu.req.valid, io.cpu.req.bits.pc, npc)) fq.io.enq.bits.data := icache.io.resp.bits.data fq.io.enq.bits.mask := ((1 << fetchWidth)-1).U << s2_pc.extract(log2Ceil(fetchWidth)+log2Ceil(coreInstBytes)-1, log2Ceil(coreInstBytes)) fq.io.enq.bits.replay := (icache.io.resp.bits.replay || icache.io.s2_kill && !icache.io.resp.valid && !s2_xcpt) || (s2_kill_speculative_tlb_refill && s2_tlb_resp.miss) fq.io.enq.bits.btb := s2_btb_resp_bits fq.io.enq.bits.btb.taken := s2_btb_taken fq.io.enq.bits.xcpt := s2_tlb_resp assert(!(s2_speculative && io.ptw.customCSRs.asInstanceOf[RocketCustomCSRs].disableSpeculativeICacheRefill && !icache.io.s2_kill)) when (icache.io.resp.valid && icache.io.resp.bits.ae) { fq.io.enq.bits.xcpt.ae.inst := true.B } if (usingBTB) { val btb = Module(new BTB) btb.io.flush := false.B btb.io.req.valid := false.B btb.io.req.bits.addr := s1_pc btb.io.btb_update := io.cpu.btb_update btb.io.bht_update := io.cpu.bht_update btb.io.ras_update.valid := false.B btb.io.ras_update.bits := DontCare btb.io.bht_advance.valid := false.B btb.io.bht_advance.bits := DontCare when (!s2_replay) { btb.io.req.valid := !s2_redirect s2_btb_resp_valid := btb.io.resp.valid s2_btb_resp_bits := btb.io.resp.bits } when (btb.io.resp.valid && btb.io.resp.bits.taken) { predicted_npc := btb.io.resp.bits.target.sextTo(vaddrBitsExtended) predicted_taken := true.B } val force_taken = io.ptw.customCSRs.bpmStatic when (io.ptw.customCSRs.flushBTB) { btb.io.flush := true.B } when (force_taken) { btb.io.bht_update.valid := false.B } val s2_base_pc = ~(~s2_pc | (fetchBytes-1).U) val taken_idx = Wire(UInt()) val after_idx = Wire(UInt()) val useRAS = WireDefault(false.B) val updateBTB = WireDefault(false.B) // If !prevTaken, ras_update / bht_update is always invalid. taken_idx := DontCare after_idx := DontCare def scanInsns(idx: Int, prevValid: Bool, prevBits: UInt, prevTaken: Bool): Bool = { def insnIsRVC(bits: UInt) = bits(1,0) =/= 3.U val prevRVI = prevValid && !insnIsRVC(prevBits) val valid = fq.io.enq.bits.mask(idx) && !prevRVI val bits = fq.io.enq.bits.data(coreInstBits*(idx+1)-1, coreInstBits*idx) val rvc = insnIsRVC(bits) val rviBits = Cat(bits, prevBits) val rviBranch = rviBits(6,0) === Instructions.BEQ.value.U.extract(6,0) val rviJump = rviBits(6,0) === Instructions.JAL.value.U.extract(6,0) val rviJALR = rviBits(6,0) === Instructions.JALR.value.U.extract(6,0) val rviReturn = rviJALR && !rviBits(7) && BitPat("b00?01") === rviBits(19,15) val rviCall = (rviJALR || rviJump) && rviBits(7) val rvcBranch = bits === Instructions.C_BEQZ || bits === Instructions.C_BNEZ val rvcJAL = (xLen == 32).B && bits === Instructions32.C_JAL val rvcJump = bits === Instructions.C_J || rvcJAL val rvcImm = Mux(bits(14), new RVCDecoder(bits, xLen, fLen).bImm.asSInt, new RVCDecoder(bits, xLen, fLen).jImm.asSInt) val rvcJR = bits === Instructions.C_MV && bits(6,2) === 0.U val rvcReturn = rvcJR && BitPat("b00?01") === bits(11,7) val rvcJALR = bits === Instructions.C_ADD && bits(6,2) === 0.U val rvcCall = rvcJAL || rvcJALR val rviImm = Mux(rviBits(3), ImmGen(IMM_UJ, rviBits), ImmGen(IMM_SB, rviBits)) val predict_taken = s2_btb_resp_bits.bht.taken || force_taken val taken = prevRVI && (rviJump || rviJALR || rviBranch && predict_taken) || valid && (rvcJump || rvcJALR || rvcJR || rvcBranch && predict_taken) val predictReturn = btb.io.ras_head.valid && (prevRVI && rviReturn || valid && rvcReturn) val predictJump = prevRVI && rviJump || valid && rvcJump val predictBranch = predict_taken && (prevRVI && rviBranch || valid && rvcBranch) when (s2_valid && s2_btb_resp_valid && s2_btb_resp_bits.bridx === idx.U && valid && !rvc) { // The BTB has predicted that the middle of an RVI instruction is // a branch! Flush the BTB and the pipeline. btb.io.flush := true.B fq.io.enq.bits.replay := true.B wrong_path := true.B ccover(wrong_path, "BTB_NON_CFI_ON_WRONG_PATH", "BTB predicted a non-branch was taken while on the wrong path") } when (!prevTaken) { taken_idx := idx.U after_idx := (idx + 1).U btb.io.ras_update.valid := fq.io.enq.fire && !wrong_path && (prevRVI && (rviCall || rviReturn) || valid && (rvcCall || rvcReturn)) btb.io.ras_update.bits.cfiType := Mux(Mux(prevRVI, rviReturn, rvcReturn), CFIType.ret, Mux(Mux(prevRVI, rviCall, rvcCall), CFIType.call, Mux(Mux(prevRVI, rviBranch, rvcBranch) && !force_taken, CFIType.branch, CFIType.jump))) when (!s2_btb_taken) { when (fq.io.enq.fire && taken && !predictBranch && !predictJump && !predictReturn) { wrong_path := true.B } when (s2_valid && predictReturn) { useRAS := true.B } when (s2_valid && (predictBranch || predictJump)) { val pc = s2_base_pc | (idx*coreInstBytes).U val npc = if (idx == 0) pc.asSInt + Mux(prevRVI, rviImm -& 2.S, rvcImm) else Mux(prevRVI, pc - coreInstBytes.U, pc).asSInt + Mux(prevRVI, rviImm, rvcImm) predicted_npc := npc.asUInt } } when (prevRVI && rviBranch || valid && rvcBranch) { btb.io.bht_advance.valid := fq.io.enq.fire && !wrong_path btb.io.bht_advance.bits := s2_btb_resp_bits } when (!s2_btb_resp_valid && (predictBranch && s2_btb_resp_bits.bht.strongly_taken || predictJump || predictReturn)) { updateBTB := true.B } } if (idx == fetchWidth-1) { when (fq.io.enq.fire) { s2_partial_insn_valid := false.B when (valid && !prevTaken && !rvc) { s2_partial_insn_valid := true.B s2_partial_insn := bits | 0x3.U } } prevTaken || taken } else { scanInsns(idx + 1, valid, bits, prevTaken || taken) } } when (!io.cpu.btb_update.valid) { val fetch_bubble_likely = !fq.io.mask(1) btb.io.btb_update.valid := fq.io.enq.fire && !wrong_path && fetch_bubble_likely && updateBTB btb.io.btb_update.bits.prediction.entry := tileParams.btb.get.nEntries.U btb.io.btb_update.bits.isValid := true.B btb.io.btb_update.bits.cfiType := btb.io.ras_update.bits.cfiType btb.io.btb_update.bits.br_pc := s2_base_pc | (taken_idx << log2Ceil(coreInstBytes)) btb.io.btb_update.bits.pc := s2_base_pc } btb.io.ras_update.bits.returnAddr := s2_base_pc + (after_idx << log2Ceil(coreInstBytes)) val taken = scanInsns(0, s2_partial_insn_valid, s2_partial_insn, false.B) when (useRAS) { predicted_npc := btb.io.ras_head.bits } when (fq.io.enq.fire && (s2_btb_taken || taken)) { s2_partial_insn_valid := false.B } when (!s2_btb_taken) { when (taken) { fq.io.enq.bits.btb.bridx := taken_idx fq.io.enq.bits.btb.taken := true.B fq.io.enq.bits.btb.entry := tileParams.btb.get.nEntries.U when (fq.io.enq.fire) { s2_redirect := true.B } } } assert(!s2_partial_insn_valid || fq.io.enq.bits.mask(0)) when (s2_redirect) { s2_partial_insn_valid := false.B } when (io.cpu.req.valid) { wrong_path := false.B } } io.cpu.resp <> fq.io.deq // supply guest physical address to commit stage val gpa_valid = Reg(Bool()) val gpa = Reg(UInt(vaddrBitsExtended.W)) val gpa_is_pte = Reg(Bool()) when (fq.io.enq.fire && s2_tlb_resp.gf.inst) { when (!gpa_valid) { gpa := s2_tlb_resp.gpa gpa_is_pte := s2_tlb_resp.gpa_is_pte } gpa_valid := true.B } when (io.cpu.req.valid) { gpa_valid := false.B } io.cpu.gpa.valid := gpa_valid io.cpu.gpa.bits := gpa io.cpu.gpa_is_pte := gpa_is_pte // performance events io.cpu.perf.acquire := icache.io.perf.acquire io.cpu.perf.tlbMiss := io.ptw.req.fire io.errors := icache.io.errors // gate the clock clock_en_reg := !rocketParams.clockGate.B || io.cpu.might_request || // chicken bit icache.io.keep_clock_enabled || // I$ miss or ITIM access s1_valid || s2_valid || // some fetch in flight !tlb.io.req.ready || // handling TLB miss !fq.io.mask(fq.io.mask.getWidth-1) // queue not full } // leaving gated-clock domain def alignPC(pc: UInt) = ~(~pc | (coreInstBytes - 1).U) def ccover(cond: Bool, label: String, desc: String)(implicit sourceInfo: SourceInfo) = property.cover(cond, s"FRONTEND_$label", "Rocket;;" + desc) } /** Mix-ins for constructing tiles that have an ICache-based pipeline frontend */ trait HasICacheFrontend extends CanHavePTW { this: BaseTile => val module: HasICacheFrontendModule val frontend = LazyModule(new Frontend(tileParams.icache.get, tileId)) tlMasterXbar.node := TLWidthWidget(tileParams.icache.get.rowBits/8) := frontend.masterNode connectTLSlave(frontend.slaveNode, tileParams.core.fetchBytes) frontend.icache.hartIdSinkNodeOpt.foreach { _ := hartIdNexusNode } frontend.icache.mmioAddressPrefixSinkNodeOpt.foreach { _ := mmioAddressPrefixNexusNode } frontend.resetVectorSinkNode := resetVectorNexusNode nPTWPorts += 1 // This should be a None in the case of not having an ITIM address, when we // don't actually use the device that is instantiated in the frontend. private val deviceOpt = if (tileParams.icache.get.itimAddr.isDefined) Some(frontend.icache.device) else None } trait HasICacheFrontendModule extends CanHavePTWModule { val outer: HasICacheFrontend ptwPorts += outer.frontend.module.io.ptw } File LazyModuleImp.scala: package org.chipsalliance.diplomacy.lazymodule import chisel3.{withClockAndReset, Module, RawModule, Reset, _} import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo} import firrtl.passes.InlineAnnotation import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.nodes.Dangle import scala.collection.immutable.SortedMap /** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]]. * * This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy. */ sealed trait LazyModuleImpLike extends RawModule { /** [[LazyModule]] that contains this instance. */ val wrapper: LazyModule /** IOs that will be automatically "punched" for this instance. */ val auto: AutoBundle /** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */ protected[diplomacy] val dangles: Seq[Dangle] // [[wrapper.module]] had better not be accessed while LazyModules are still being built! require( LazyModule.scope.isEmpty, s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}" ) /** Set module name. Defaults to the containing LazyModule's desiredName. */ override def desiredName: String = wrapper.desiredName suggestName(wrapper.suggestedName) /** [[Parameters]] for chisel [[Module]]s. */ implicit val p: Parameters = wrapper.p /** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and * submodules. */ protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = { // 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]], // 2. return [[Dangle]]s from each module. val childDangles = wrapper.children.reverse.flatMap { c => implicit val sourceInfo: SourceInfo = c.info c.cloneProto.map { cp => // If the child is a clone, then recursively set cloneProto of its children as well def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = { require(bases.size == clones.size) (bases.zip(clones)).map { case (l, r) => require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}") l.cloneProto = Some(r) assignCloneProtos(l.children, r.children) } } assignCloneProtos(c.children, cp.children) // Clone the child module as a record, and get its [[AutoBundle]] val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName) val clonedAuto = clone("auto").asInstanceOf[AutoBundle] // Get the empty [[Dangle]]'s of the cloned child val rawDangles = c.cloneDangles() require(rawDangles.size == clonedAuto.elements.size) // Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) } dangles }.getOrElse { // For non-clones, instantiate the child module val mod = try { Module(c.module) } catch { case e: ChiselException => { println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}") throw e } } mod.dangles } } // Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]]. // This will result in a sequence of [[Dangle]] from these [[BaseNode]]s. val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate()) // Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]] val allDangles = nodeDangles ++ childDangles // Group [[allDangles]] by their [[source]]. val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*) // For each [[source]] set of [[Dangle]]s of size 2, ensure that these // can be connected as a source-sink pair (have opposite flipped value). // Make the connection and mark them as [[done]]. val done = Set() ++ pairing.values.filter(_.size == 2).map { case Seq(a, b) => require(a.flipped != b.flipped) // @todo <> in chisel3 makes directionless connection. if (a.flipped) { a.data <> b.data } else { b.data <> a.data } a.source case _ => None } // Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module. val forward = allDangles.filter(d => !done(d.source)) // Generate [[AutoBundle]] IO from [[forward]]. val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*)) // Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]] val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) => if (d.flipped) { d.data <> io } else { io <> d.data } d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name) } // Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]]. wrapper.inModuleBody.reverse.foreach { _() } if (wrapper.shouldBeInlined) { chisel3.experimental.annotate(new ChiselAnnotation { def toFirrtl = InlineAnnotation(toNamed) }) } // Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]]. (auto, dangles) } } /** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike { /** Instantiate hardware of this `Module`. */ val (auto, dangles) = instantiate() } /** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike { // These wires are the default clock+reset for all LazyModule children. // It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the // [[LazyRawModuleImp]] children. // Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly. /** drive clock explicitly. */ val childClock: Clock = Wire(Clock()) /** drive reset explicitly. */ val childReset: Reset = Wire(Reset()) // the default is that these are disabled childClock := false.B.asClock childReset := chisel3.DontCare def provideImplicitClockToLazyChildren: Boolean = false val (auto, dangles) = if (provideImplicitClockToLazyChildren) { withClockAndReset(childClock, childReset) { instantiate() } } else { instantiate() } } File PTW.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.rocket import chisel3._ import chisel3.util.{Arbiter, Cat, Decoupled, Enum, Mux1H, OHToUInt, PopCount, PriorityEncoder, PriorityEncoderOH, RegEnable, UIntToOH, Valid, is, isPow2, log2Ceil, switch} import chisel3.withClock import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.subsystem.CacheBlockBytes import freechips.rocketchip.tile._ import freechips.rocketchip.tilelink._ import freechips.rocketchip.util._ import freechips.rocketchip.util.property import scala.collection.mutable.ListBuffer /** PTE request from TLB to PTW * * TLB send a PTE request to PTW when L1TLB miss */ class PTWReq(implicit p: Parameters) extends CoreBundle()(p) { val addr = UInt(vpnBits.W) val need_gpa = Bool() val vstage1 = Bool() val stage2 = Bool() } /** PTE info from L2TLB to TLB * * containing: target PTE, exceptions, two-satge tanslation info */ class PTWResp(implicit p: Parameters) extends CoreBundle()(p) { /** ptw access exception */ val ae_ptw = Bool() /** final access exception */ val ae_final = Bool() /** page fault */ val pf = Bool() /** guest page fault */ val gf = Bool() /** hypervisor read */ val hr = Bool() /** hypervisor write */ val hw = Bool() /** hypervisor execute */ val hx = Bool() /** PTE to refill L1TLB * * source: L2TLB */ val pte = new PTE /** pte pglevel */ val level = UInt(log2Ceil(pgLevels).W) /** fragmented_superpage support */ val fragmented_superpage = Bool() /** homogeneous for both pma and pmp */ val homogeneous = Bool() val gpa = Valid(UInt(vaddrBits.W)) val gpa_is_pte = Bool() } /** IO between TLB and PTW * * PTW receives : * - PTE request * - CSRs info * - pmp results from PMP(in TLB) */ class TLBPTWIO(implicit p: Parameters) extends CoreBundle()(p) with HasCoreParameters { val req = Decoupled(Valid(new PTWReq)) val resp = Flipped(Valid(new PTWResp)) val ptbr = Input(new PTBR()) val hgatp = Input(new PTBR()) val vsatp = Input(new PTBR()) val status = Input(new MStatus()) val hstatus = Input(new HStatus()) val gstatus = Input(new MStatus()) val pmp = Input(Vec(nPMPs, new PMP)) val customCSRs = Flipped(coreParams.customCSRs) } /** PTW performance statistics */ class PTWPerfEvents extends Bundle { val l2miss = Bool() val l2hit = Bool() val pte_miss = Bool() val pte_hit = Bool() } /** Datapath IO between PTW and Core * * PTW receives CSRs info, pmp checks, sfence instruction info * * PTW sends its performance statistics to core */ class DatapathPTWIO(implicit p: Parameters) extends CoreBundle()(p) with HasCoreParameters { val ptbr = Input(new PTBR()) val hgatp = Input(new PTBR()) val vsatp = Input(new PTBR()) val sfence = Flipped(Valid(new SFenceReq)) val status = Input(new MStatus()) val hstatus = Input(new HStatus()) val gstatus = Input(new MStatus()) val pmp = Input(Vec(nPMPs, new PMP)) val perf = Output(new PTWPerfEvents()) val customCSRs = Flipped(coreParams.customCSRs) /** enable clock generated by ptw */ val clock_enabled = Output(Bool()) } /** PTE template for transmission * * contains useful methods to check PTE attributes * @see RV-priv spec 4.3.1 for pgae table entry format */ class PTE(implicit p: Parameters) extends CoreBundle()(p) { val reserved_for_future = UInt(10.W) val ppn = UInt(44.W) val reserved_for_software = Bits(2.W) /** dirty bit */ val d = Bool() /** access bit */ val a = Bool() /** global mapping */ val g = Bool() /** user mode accessible */ val u = Bool() /** whether the page is executable */ val x = Bool() /** whether the page is writable */ val w = Bool() /** whether the page is readable */ val r = Bool() /** valid bit */ val v = Bool() /** return true if find a pointer to next level page table */ def table(dummy: Int = 0) = v && !r && !w && !x && !d && !a && !u && reserved_for_future === 0.U /** return true if find a leaf PTE */ def leaf(dummy: Int = 0) = v && (r || (x && !w)) && a /** user read */ def ur(dummy: Int = 0) = sr() && u /** user write*/ def uw(dummy: Int = 0) = sw() && u /** user execute */ def ux(dummy: Int = 0) = sx() && u /** supervisor read */ def sr(dummy: Int = 0) = leaf() && r /** supervisor write */ def sw(dummy: Int = 0) = leaf() && w && d /** supervisor execute */ def sx(dummy: Int = 0) = leaf() && x /** full permission: writable and executable in user mode */ def isFullPerm(dummy: Int = 0) = uw() && ux() } /** L2TLB PTE template * * contains tag bits * @param nSets number of sets in L2TLB * @see RV-priv spec 4.3.1 for page table entry format */ class L2TLBEntry(nSets: Int)(implicit p: Parameters) extends CoreBundle()(p) with HasCoreParameters { val idxBits = log2Ceil(nSets) val tagBits = maxSVAddrBits - pgIdxBits - idxBits + (if (usingHypervisor) 1 else 0) val tag = UInt(tagBits.W) val ppn = UInt(ppnBits.W) /** dirty bit */ val d = Bool() /** access bit */ val a = Bool() /** user mode accessible */ val u = Bool() /** whether the page is executable */ val x = Bool() /** whether the page is writable */ val w = Bool() /** whether the page is readable */ val r = Bool() } /** PTW contains L2TLB, and performs page table walk for high level TLB, and cache queries from L1 TLBs(I$, D$, RoCC) * * It performs hierarchy page table query to mem for the desired leaf PTE and cache them in l2tlb. * Besides leaf PTEs, it also caches non-leaf PTEs in pte_cache to accerlerate the process. * * ==Structure== * - l2tlb : for leaf PTEs * - set-associative (configurable with [[CoreParams.nL2TLBEntries]]and [[CoreParams.nL2TLBWays]])) * - PLRU * - pte_cache: for non-leaf PTEs * - set-associative * - LRU * - s2_pte_cache: for non-leaf PTEs in 2-stage translation * - set-associative * - PLRU * * l2tlb Pipeline: 3 stage * {{{ * stage 0 : read * stage 1 : decode * stage 2 : hit check * }}} * ==State Machine== * s_ready: ready to reveive request from TLB * s_req: request mem; pte_cache hit judge * s_wait1: deal with l2tlb error * s_wait2: final hit judge * s_wait3: receive mem response * s_fragment_superpage: for superpage PTE * * @note l2tlb hit happens in s_req or s_wait1 * @see RV-priv spec 4.3-4.6 for Virtual-Memory System * @see RV-priv spec 8.5 for Two-Stage Address Translation * @todo details in two-stage translation */ class PTW(n: Int)(implicit edge: TLEdgeOut, p: Parameters) extends CoreModule()(p) { val io = IO(new Bundle { /** to n TLB */ val requestor = Flipped(Vec(n, new TLBPTWIO)) /** to HellaCache */ val mem = new HellaCacheIO /** to Core * * contains CSRs info and performance statistics */ val dpath = new DatapathPTWIO }) val s_ready :: s_req :: s_wait1 :: s_dummy1 :: s_wait2 :: s_wait3 :: s_dummy2 :: s_fragment_superpage :: Nil = Enum(8) val state = RegInit(s_ready) val l2_refill_wire = Wire(Bool()) /** Arbiter to arbite request from n TLB */ val arb = Module(new Arbiter(Valid(new PTWReq), n)) // use TLB req as arbitor's input arb.io.in <> io.requestor.map(_.req) // receive req only when s_ready and not in refill arb.io.out.ready := (state === s_ready) && !l2_refill_wire val resp_valid = RegNext(VecInit(Seq.fill(io.requestor.size)(false.B))) val clock_en = state =/= s_ready || l2_refill_wire || arb.io.out.valid || io.dpath.sfence.valid || io.dpath.customCSRs.disableDCacheClockGate io.dpath.clock_enabled := usingVM.B && clock_en val gated_clock = if (!usingVM || !tileParams.dcache.get.clockGate) clock else ClockGate(clock, clock_en, "ptw_clock_gate") withClock (gated_clock) { // entering gated-clock domain val invalidated = Reg(Bool()) /** current PTE level * {{{ * 0 <= count <= pgLevel-1 * count = pgLevel - 1 : leaf PTE * count < pgLevel - 1 : non-leaf PTE * }}} */ val count = Reg(UInt(log2Ceil(pgLevels).W)) val resp_ae_ptw = Reg(Bool()) val resp_ae_final = Reg(Bool()) val resp_pf = Reg(Bool()) val resp_gf = Reg(Bool()) val resp_hr = Reg(Bool()) val resp_hw = Reg(Bool()) val resp_hx = Reg(Bool()) val resp_fragmented_superpage = Reg(Bool()) /** tlb request */ val r_req = Reg(new PTWReq) /** current selected way in arbitor */ val r_req_dest = Reg(Bits()) // to respond to L1TLB : l2_hit // to construct mem.req.addr val r_pte = Reg(new PTE) val r_hgatp = Reg(new PTBR) // 2-stage pageLevel val aux_count = Reg(UInt(log2Ceil(pgLevels).W)) /** pte for 2-stage translation */ val aux_pte = Reg(new PTE) val gpa_pgoff = Reg(UInt(pgIdxBits.W)) // only valid in resp_gf case val stage2 = Reg(Bool()) val stage2_final = Reg(Bool()) val satp = Mux(arb.io.out.bits.bits.vstage1, io.dpath.vsatp, io.dpath.ptbr) val r_hgatp_initial_count = pgLevels.U - minPgLevels.U - r_hgatp.additionalPgLevels /** 2-stage translation both enable */ val do_both_stages = r_req.vstage1 && r_req.stage2 val max_count = count max aux_count val vpn = Mux(r_req.vstage1 && stage2, aux_pte.ppn, r_req.addr) val mem_resp_valid = RegNext(io.mem.resp.valid) val mem_resp_data = RegNext(io.mem.resp.bits.data) io.mem.uncached_resp.map { resp => assert(!(resp.valid && io.mem.resp.valid)) resp.ready := true.B when (resp.valid) { mem_resp_valid := true.B mem_resp_data := resp.bits.data } } // construct pte from mem.resp val (pte, invalid_paddr, invalid_gpa) = { val tmp = mem_resp_data.asTypeOf(new PTE()) val res = WireDefault(tmp) res.ppn := Mux(do_both_stages && !stage2, tmp.ppn(vpnBits.min(tmp.ppn.getWidth)-1, 0), tmp.ppn(ppnBits-1, 0)) when (tmp.r || tmp.w || tmp.x) { // for superpage mappings, make sure PPN LSBs are zero for (i <- 0 until pgLevels-1) when (count <= i.U && tmp.ppn((pgLevels-1-i)*pgLevelBits-1, (pgLevels-2-i)*pgLevelBits) =/= 0.U) { res.v := false.B } } (res, Mux(do_both_stages && !stage2, (tmp.ppn >> vpnBits) =/= 0.U, (tmp.ppn >> ppnBits) =/= 0.U), do_both_stages && !stage2 && checkInvalidHypervisorGPA(r_hgatp, tmp.ppn)) } // find non-leaf PTE, need traverse val traverse = pte.table() && !invalid_paddr && !invalid_gpa && count < (pgLevels-1).U /** address send to mem for enquerry */ val pte_addr = if (!usingVM) 0.U else { val vpn_idxs = (0 until pgLevels).map { i => val width = pgLevelBits + (if (i <= pgLevels - minPgLevels) hypervisorExtraAddrBits else 0) (vpn >> (pgLevels - i - 1) * pgLevelBits)(width - 1, 0) } val mask = Mux(stage2 && count === r_hgatp_initial_count, ((1 << (hypervisorExtraAddrBits + pgLevelBits)) - 1).U, ((1 << pgLevelBits) - 1).U) val vpn_idx = vpn_idxs(count) & mask val raw_pte_addr = ((r_pte.ppn << pgLevelBits) | vpn_idx) << log2Ceil(xLen / 8) val size = if (usingHypervisor) vaddrBits else paddrBits //use r_pte.ppn as page table base address //use vpn slice as offset raw_pte_addr.apply(size.min(raw_pte_addr.getWidth) - 1, 0) } /** stage2_pte_cache input addr */ val stage2_pte_cache_addr = if (!usingHypervisor) 0.U else { val vpn_idxs = (0 until pgLevels - 1).map { i => (r_req.addr >> (pgLevels - i - 1) * pgLevelBits)(pgLevelBits - 1, 0) } val vpn_idx = vpn_idxs(aux_count) val raw_s2_pte_cache_addr = Cat(aux_pte.ppn, vpn_idx) << log2Ceil(xLen / 8) raw_s2_pte_cache_addr(vaddrBits.min(raw_s2_pte_cache_addr.getWidth) - 1, 0) } def makeFragmentedSuperpagePPN(ppn: UInt): Seq[UInt] = { (pgLevels-1 until 0 by -1).map(i => Cat(ppn >> (pgLevelBits*i), r_req.addr(((pgLevelBits*i) min vpnBits)-1, 0).padTo(pgLevelBits*i))) } /** PTECache caches non-leaf PTE * @param s2 true: 2-stage address translation */ def makePTECache(s2: Boolean): (Bool, UInt) = if (coreParams.nPTECacheEntries == 0) { (false.B, 0.U) } else { val plru = new PseudoLRU(coreParams.nPTECacheEntries) val valid = RegInit(0.U(coreParams.nPTECacheEntries.W)) val tags = Reg(Vec(coreParams.nPTECacheEntries, UInt((if (usingHypervisor) 1 + vaddrBits else paddrBits).W))) // not include full pte, only ppn val data = Reg(Vec(coreParams.nPTECacheEntries, UInt((if (usingHypervisor && s2) vpnBits else ppnBits).W))) val can_hit = if (s2) count === r_hgatp_initial_count && aux_count < (pgLevels-1).U && r_req.vstage1 && stage2 && !stage2_final else count < (pgLevels-1).U && Mux(r_req.vstage1, stage2, !r_req.stage2) val can_refill = if (s2) do_both_stages && !stage2 && !stage2_final else can_hit val tag = if (s2) Cat(true.B, stage2_pte_cache_addr.padTo(vaddrBits)) else Cat(r_req.vstage1, pte_addr.padTo(if (usingHypervisor) vaddrBits else paddrBits)) val hits = tags.map(_ === tag).asUInt & valid val hit = hits.orR && can_hit // refill with mem response when (mem_resp_valid && traverse && can_refill && !hits.orR && !invalidated) { val r = Mux(valid.andR, plru.way, PriorityEncoder(~valid)) valid := valid | UIntToOH(r) tags(r) := tag data(r) := pte.ppn plru.access(r) } // replace when (hit && state === s_req) { plru.access(OHToUInt(hits)) } when (io.dpath.sfence.valid && (!io.dpath.sfence.bits.rs1 || usingHypervisor.B && io.dpath.sfence.bits.hg)) { valid := 0.U } val lcount = if (s2) aux_count else count for (i <- 0 until pgLevels-1) { ccover(hit && state === s_req && lcount === i.U, s"PTE_CACHE_HIT_L$i", s"PTE cache hit, level $i") } (hit, Mux1H(hits, data)) } // generate pte_cache val (pte_cache_hit, pte_cache_data) = makePTECache(false) // generate pte_cache with 2-stage translation val (stage2_pte_cache_hit, stage2_pte_cache_data) = makePTECache(true) // pte_cache hit or 2-stage pte_cache hit val pte_hit = RegNext(false.B) io.dpath.perf.pte_miss := false.B io.dpath.perf.pte_hit := pte_hit && (state === s_req) && !io.dpath.perf.l2hit assert(!(io.dpath.perf.l2hit && (io.dpath.perf.pte_miss || io.dpath.perf.pte_hit)), "PTE Cache Hit/Miss Performance Monitor Events are lower priority than L2TLB Hit event") // l2_refill happens when find the leaf pte val l2_refill = RegNext(false.B) l2_refill_wire := l2_refill io.dpath.perf.l2miss := false.B io.dpath.perf.l2hit := false.B // l2tlb val (l2_hit, l2_error, l2_pte, l2_tlb_ram) = if (coreParams.nL2TLBEntries == 0) (false.B, false.B, WireDefault(0.U.asTypeOf(new PTE)), None) else { val code = new ParityCode require(isPow2(coreParams.nL2TLBEntries)) require(isPow2(coreParams.nL2TLBWays)) require(coreParams.nL2TLBEntries >= coreParams.nL2TLBWays) val nL2TLBSets = coreParams.nL2TLBEntries / coreParams.nL2TLBWays require(isPow2(nL2TLBSets)) val idxBits = log2Ceil(nL2TLBSets) val l2_plru = new SetAssocLRU(nL2TLBSets, coreParams.nL2TLBWays, "plru") val ram = DescribedSRAM( name = "l2_tlb_ram", desc = "L2 TLB", size = nL2TLBSets, data = Vec(coreParams.nL2TLBWays, UInt(code.width(new L2TLBEntry(nL2TLBSets).getWidth).W)) ) val g = Reg(Vec(coreParams.nL2TLBWays, UInt(nL2TLBSets.W))) val valid = RegInit(VecInit(Seq.fill(coreParams.nL2TLBWays)(0.U(nL2TLBSets.W)))) // use r_req to construct tag val (r_tag, r_idx) = Split(Cat(r_req.vstage1, r_req.addr(maxSVAddrBits-pgIdxBits-1, 0)), idxBits) /** the valid vec for the selected set(including n ways) */ val r_valid_vec = valid.map(_(r_idx)).asUInt val r_valid_vec_q = Reg(UInt(coreParams.nL2TLBWays.W)) val r_l2_plru_way = Reg(UInt(log2Ceil(coreParams.nL2TLBWays max 1).W)) r_valid_vec_q := r_valid_vec // replacement way r_l2_plru_way := (if (coreParams.nL2TLBWays > 1) l2_plru.way(r_idx) else 0.U) // refill with r_pte(leaf pte) when (l2_refill && !invalidated) { val entry = Wire(new L2TLBEntry(nL2TLBSets)) entry.ppn := r_pte.ppn entry.d := r_pte.d entry.a := r_pte.a entry.u := r_pte.u entry.x := r_pte.x entry.w := r_pte.w entry.r := r_pte.r entry.tag := r_tag // if all the way are valid, use plru to select one way to be replaced, // otherwise use PriorityEncoderOH to select one val wmask = if (coreParams.nL2TLBWays > 1) Mux(r_valid_vec_q.andR, UIntToOH(r_l2_plru_way, coreParams.nL2TLBWays), PriorityEncoderOH(~r_valid_vec_q)) else 1.U(1.W) ram.write(r_idx, VecInit(Seq.fill(coreParams.nL2TLBWays)(code.encode(entry.asUInt))), wmask.asBools) val mask = UIntToOH(r_idx) for (way <- 0 until coreParams.nL2TLBWays) { when (wmask(way)) { valid(way) := valid(way) | mask g(way) := Mux(r_pte.g, g(way) | mask, g(way) & ~mask) } } } // sfence happens when (io.dpath.sfence.valid) { val hg = usingHypervisor.B && io.dpath.sfence.bits.hg for (way <- 0 until coreParams.nL2TLBWays) { valid(way) := Mux(!hg && io.dpath.sfence.bits.rs1, valid(way) & ~UIntToOH(io.dpath.sfence.bits.addr(idxBits+pgIdxBits-1, pgIdxBits)), Mux(!hg && io.dpath.sfence.bits.rs2, valid(way) & g(way), 0.U)) } } val s0_valid = !l2_refill && arb.io.out.fire val s0_suitable = arb.io.out.bits.bits.vstage1 === arb.io.out.bits.bits.stage2 && !arb.io.out.bits.bits.need_gpa val s1_valid = RegNext(s0_valid && s0_suitable && arb.io.out.bits.valid) val s2_valid = RegNext(s1_valid) // read from tlb idx val s1_rdata = ram.read(arb.io.out.bits.bits.addr(idxBits-1, 0), s0_valid) val s2_rdata = s1_rdata.map(s1_rdway => code.decode(RegEnable(s1_rdway, s1_valid))) val s2_valid_vec = RegEnable(r_valid_vec, s1_valid) val s2_g_vec = RegEnable(VecInit(g.map(_(r_idx))), s1_valid) val s2_error = (0 until coreParams.nL2TLBWays).map(way => s2_valid_vec(way) && s2_rdata(way).error).orR when (s2_valid && s2_error) { valid.foreach { _ := 0.U }} // decode val s2_entry_vec = s2_rdata.map(_.uncorrected.asTypeOf(new L2TLBEntry(nL2TLBSets))) val s2_hit_vec = (0 until coreParams.nL2TLBWays).map(way => s2_valid_vec(way) && (r_tag === s2_entry_vec(way).tag)) val s2_hit = s2_valid && s2_hit_vec.orR io.dpath.perf.l2miss := s2_valid && !(s2_hit_vec.orR) io.dpath.perf.l2hit := s2_hit when (s2_hit) { l2_plru.access(r_idx, OHToUInt(s2_hit_vec)) assert((PopCount(s2_hit_vec) === 1.U) || s2_error, "L2 TLB multi-hit") } val s2_pte = Wire(new PTE) val s2_hit_entry = Mux1H(s2_hit_vec, s2_entry_vec) s2_pte.ppn := s2_hit_entry.ppn s2_pte.d := s2_hit_entry.d s2_pte.a := s2_hit_entry.a s2_pte.g := Mux1H(s2_hit_vec, s2_g_vec) s2_pte.u := s2_hit_entry.u s2_pte.x := s2_hit_entry.x s2_pte.w := s2_hit_entry.w s2_pte.r := s2_hit_entry.r s2_pte.v := true.B s2_pte.reserved_for_future := 0.U s2_pte.reserved_for_software := 0.U for (way <- 0 until coreParams.nL2TLBWays) { ccover(s2_hit && s2_hit_vec(way), s"L2_TLB_HIT_WAY$way", s"L2 TLB hit way$way") } (s2_hit, s2_error, s2_pte, Some(ram)) } // if SFENCE occurs during walk, don't refill PTE cache or L2 TLB until next walk invalidated := io.dpath.sfence.valid || (invalidated && state =/= s_ready) // mem request io.mem.keep_clock_enabled := false.B io.mem.req.valid := state === s_req || state === s_dummy1 io.mem.req.bits.phys := true.B io.mem.req.bits.cmd := M_XRD io.mem.req.bits.size := log2Ceil(xLen/8).U io.mem.req.bits.signed := false.B io.mem.req.bits.addr := pte_addr io.mem.req.bits.idx.foreach(_ := pte_addr) io.mem.req.bits.dprv := PRV.S.U // PTW accesses are S-mode by definition io.mem.req.bits.dv := do_both_stages && !stage2 io.mem.req.bits.tag := DontCare io.mem.req.bits.no_resp := false.B io.mem.req.bits.no_alloc := DontCare io.mem.req.bits.no_xcpt := DontCare io.mem.req.bits.data := DontCare io.mem.req.bits.mask := DontCare io.mem.s1_kill := l2_hit || (state =/= s_wait1) || resp_gf io.mem.s1_data := DontCare io.mem.s2_kill := false.B val pageGranularityPMPs = pmpGranularity >= (1 << pgIdxBits) require(!usingHypervisor || pageGranularityPMPs, s"hypervisor requires pmpGranularity >= ${1<<pgIdxBits}") val pmaPgLevelHomogeneous = (0 until pgLevels) map { i => val pgSize = BigInt(1) << (pgIdxBits + ((pgLevels - 1 - i) * pgLevelBits)) if (pageGranularityPMPs && i == pgLevels - 1) { require(TLBPageLookup.homogeneous(edge.manager.managers, pgSize), s"All memory regions must be $pgSize-byte aligned") true.B } else { TLBPageLookup(edge.manager.managers, xLen, p(CacheBlockBytes), pgSize, xLen/8)(r_pte.ppn << pgIdxBits).homogeneous } } val pmaHomogeneous = pmaPgLevelHomogeneous(count) val pmpHomogeneous = new PMPHomogeneityChecker(io.dpath.pmp).apply(r_pte.ppn << pgIdxBits, count) val homogeneous = pmaHomogeneous && pmpHomogeneous // response to tlb for (i <- 0 until io.requestor.size) { io.requestor(i).resp.valid := resp_valid(i) io.requestor(i).resp.bits.ae_ptw := resp_ae_ptw io.requestor(i).resp.bits.ae_final := resp_ae_final io.requestor(i).resp.bits.pf := resp_pf io.requestor(i).resp.bits.gf := resp_gf io.requestor(i).resp.bits.hr := resp_hr io.requestor(i).resp.bits.hw := resp_hw io.requestor(i).resp.bits.hx := resp_hx io.requestor(i).resp.bits.pte := r_pte io.requestor(i).resp.bits.level := max_count io.requestor(i).resp.bits.homogeneous := homogeneous || pageGranularityPMPs.B io.requestor(i).resp.bits.fragmented_superpage := resp_fragmented_superpage && pageGranularityPMPs.B io.requestor(i).resp.bits.gpa.valid := r_req.need_gpa io.requestor(i).resp.bits.gpa.bits := Cat(Mux(!stage2_final || !r_req.vstage1 || aux_count === (pgLevels - 1).U, aux_pte.ppn, makeFragmentedSuperpagePPN(aux_pte.ppn)(aux_count)), gpa_pgoff) io.requestor(i).resp.bits.gpa_is_pte := !stage2_final io.requestor(i).ptbr := io.dpath.ptbr io.requestor(i).hgatp := io.dpath.hgatp io.requestor(i).vsatp := io.dpath.vsatp io.requestor(i).customCSRs <> io.dpath.customCSRs io.requestor(i).status := io.dpath.status io.requestor(i).hstatus := io.dpath.hstatus io.requestor(i).gstatus := io.dpath.gstatus io.requestor(i).pmp := io.dpath.pmp } // control state machine val next_state = WireDefault(state) state := OptimizationBarrier(next_state) val do_switch = WireDefault(false.B) switch (state) { is (s_ready) { when (arb.io.out.fire) { val satp_initial_count = pgLevels.U - minPgLevels.U - satp.additionalPgLevels val vsatp_initial_count = pgLevels.U - minPgLevels.U - io.dpath.vsatp.additionalPgLevels val hgatp_initial_count = pgLevels.U - minPgLevels.U - io.dpath.hgatp.additionalPgLevels val aux_ppn = Mux(arb.io.out.bits.bits.vstage1, io.dpath.vsatp.ppn, arb.io.out.bits.bits.addr) r_req := arb.io.out.bits.bits r_req_dest := arb.io.chosen next_state := Mux(arb.io.out.bits.valid, s_req, s_ready) stage2 := arb.io.out.bits.bits.stage2 stage2_final := arb.io.out.bits.bits.stage2 && !arb.io.out.bits.bits.vstage1 count := Mux(arb.io.out.bits.bits.stage2, hgatp_initial_count, satp_initial_count) aux_count := Mux(arb.io.out.bits.bits.vstage1, vsatp_initial_count, 0.U) aux_pte.ppn := aux_ppn aux_pte.reserved_for_future := 0.U resp_ae_ptw := false.B resp_ae_final := false.B resp_pf := false.B resp_gf := checkInvalidHypervisorGPA(io.dpath.hgatp, aux_ppn) && arb.io.out.bits.bits.stage2 resp_hr := true.B resp_hw := true.B resp_hx := true.B resp_fragmented_superpage := false.B r_hgatp := io.dpath.hgatp assert(!arb.io.out.bits.bits.need_gpa || arb.io.out.bits.bits.stage2) } } is (s_req) { when(stage2 && count === r_hgatp_initial_count) { gpa_pgoff := Mux(aux_count === (pgLevels-1).U, r_req.addr << (xLen/8).log2, stage2_pte_cache_addr) } // pte_cache hit when (stage2_pte_cache_hit) { aux_count := aux_count + 1.U aux_pte.ppn := stage2_pte_cache_data aux_pte.reserved_for_future := 0.U pte_hit := true.B }.elsewhen (pte_cache_hit) { count := count + 1.U pte_hit := true.B }.otherwise { next_state := Mux(io.mem.req.ready, s_wait1, s_req) } when(resp_gf) { next_state := s_ready resp_valid(r_req_dest) := true.B } } is (s_wait1) { // This Mux is for the l2_error case; the l2_hit && !l2_error case is overriden below next_state := Mux(l2_hit, s_req, s_wait2) } is (s_wait2) { next_state := s_wait3 io.dpath.perf.pte_miss := count < (pgLevels-1).U when (io.mem.s2_xcpt.ae.ld) { resp_ae_ptw := true.B next_state := s_ready resp_valid(r_req_dest) := true.B } } is (s_fragment_superpage) { next_state := s_ready resp_valid(r_req_dest) := true.B when (!homogeneous) { count := (pgLevels-1).U resp_fragmented_superpage := true.B } when (do_both_stages) { resp_fragmented_superpage := true.B } } } val merged_pte = { val superpage_masks = (0 until pgLevels).map(i => ((BigInt(1) << pte.ppn.getWidth) - (BigInt(1) << (pgLevels-1-i)*pgLevelBits)).U) val superpage_mask = superpage_masks(Mux(stage2_final, max_count, (pgLevels-1).U)) val stage1_ppns = (0 until pgLevels-1).map(i => Cat(pte.ppn(pte.ppn.getWidth-1, (pgLevels-i-1)*pgLevelBits), aux_pte.ppn((pgLevels-i-1)*pgLevelBits-1,0))) :+ pte.ppn val stage1_ppn = stage1_ppns(count) makePTE(stage1_ppn & superpage_mask, aux_pte) } r_pte := OptimizationBarrier( // l2tlb hit->find a leaf PTE(l2_pte), respond to L1TLB Mux(l2_hit && !l2_error && !resp_gf, l2_pte, // S2 PTE cache hit -> proceed to the next level of walking, update the r_pte with hgatp Mux(state === s_req && stage2_pte_cache_hit, makeHypervisorRootPTE(r_hgatp, stage2_pte_cache_data, l2_pte), // pte cache hit->find a non-leaf PTE(pte_cache),continue to request mem Mux(state === s_req && pte_cache_hit, makePTE(pte_cache_data, l2_pte), // 2-stage translation Mux(do_switch, makeHypervisorRootPTE(r_hgatp, pte.ppn, r_pte), // when mem respond, store mem.resp.pte Mux(mem_resp_valid, Mux(!traverse && r_req.vstage1 && stage2, merged_pte, pte), // fragment_superpage Mux(state === s_fragment_superpage && !homogeneous && count =/= (pgLevels - 1).U, makePTE(makeFragmentedSuperpagePPN(r_pte.ppn)(count), r_pte), // when tlb request come->request mem, use root address in satp(or vsatp,hgatp) Mux(arb.io.out.fire, Mux(arb.io.out.bits.bits.stage2, makeHypervisorRootPTE(io.dpath.hgatp, io.dpath.vsatp.ppn, r_pte), makePTE(satp.ppn, r_pte)), r_pte)))))))) when (l2_hit && !l2_error && !resp_gf) { assert(state === s_req || state === s_wait1) next_state := s_ready resp_valid(r_req_dest) := true.B count := (pgLevels-1).U } when (mem_resp_valid) { assert(state === s_wait3) next_state := s_req when (traverse) { when (do_both_stages && !stage2) { do_switch := true.B } count := count + 1.U }.otherwise { val gf = (stage2 && !stage2_final && !pte.ur()) || (pte.leaf() && pte.reserved_for_future === 0.U && invalid_gpa) val ae = pte.v && invalid_paddr val pf = pte.v && pte.reserved_for_future =/= 0.U val success = pte.v && !ae && !pf && !gf when (do_both_stages && !stage2_final && success) { when (stage2) { stage2 := false.B count := aux_count }.otherwise { stage2_final := true.B do_switch := true.B } }.otherwise { // find a leaf pte, start l2 refill l2_refill := success && count === (pgLevels-1).U && !r_req.need_gpa && (!r_req.vstage1 && !r_req.stage2 || do_both_stages && aux_count === (pgLevels-1).U && pte.isFullPerm()) count := max_count when (pageGranularityPMPs.B && !(count === (pgLevels-1).U && (!do_both_stages || aux_count === (pgLevels-1).U))) { next_state := s_fragment_superpage }.otherwise { next_state := s_ready resp_valid(r_req_dest) := true.B } resp_ae_ptw := ae && count < (pgLevels-1).U && pte.table() resp_ae_final := ae && pte.leaf() resp_pf := pf && !stage2 resp_gf := gf || (pf && stage2) resp_hr := !stage2 || (!pf && !gf && pte.ur()) resp_hw := !stage2 || (!pf && !gf && pte.uw()) resp_hx := !stage2 || (!pf && !gf && pte.ux()) } } } when (io.mem.s2_nack) { assert(state === s_wait2) next_state := s_req } when (do_switch) { aux_count := Mux(traverse, count + 1.U, count) count := r_hgatp_initial_count aux_pte := Mux(traverse, pte, { val s1_ppns = (0 until pgLevels-1).map(i => Cat(pte.ppn(pte.ppn.getWidth-1, (pgLevels-i-1)*pgLevelBits), r_req.addr(((pgLevels-i-1)*pgLevelBits min vpnBits)-1,0).padTo((pgLevels-i-1)*pgLevelBits))) :+ pte.ppn makePTE(s1_ppns(count), pte) }) stage2 := true.B } for (i <- 0 until pgLevels) { val leaf = mem_resp_valid && !traverse && count === i.U ccover(leaf && pte.v && !invalid_paddr && !invalid_gpa && pte.reserved_for_future === 0.U, s"L$i", s"successful page-table access, level $i") ccover(leaf && pte.v && invalid_paddr, s"L${i}_BAD_PPN_MSB", s"PPN too large, level $i") ccover(leaf && pte.v && invalid_gpa, s"L${i}_BAD_GPA_MSB", s"GPA too large, level $i") ccover(leaf && pte.v && pte.reserved_for_future =/= 0.U, s"L${i}_BAD_RSV_MSB", s"reserved MSBs set, level $i") ccover(leaf && !mem_resp_data(0), s"L${i}_INVALID_PTE", s"page not present, level $i") if (i != pgLevels-1) ccover(leaf && !pte.v && mem_resp_data(0), s"L${i}_BAD_PPN_LSB", s"PPN LSBs not zero, level $i") } ccover(mem_resp_valid && count === (pgLevels-1).U && pte.table(), s"TOO_DEEP", s"page table too deep") ccover(io.mem.s2_nack, "NACK", "D$ nacked page-table access") ccover(state === s_wait2 && io.mem.s2_xcpt.ae.ld, "AE", "access exception while walking page table") } // leaving gated-clock domain private def ccover(cond: Bool, label: String, desc: String)(implicit sourceInfo: SourceInfo) = if (usingVM) property.cover(cond, s"PTW_$label", "MemorySystem;;" + desc) /** Relace PTE.ppn with ppn */ private def makePTE(ppn: UInt, default: PTE) = { val pte = WireDefault(default) pte.ppn := ppn pte } /** use hgatp and vpn to construct a new ppn */ private def makeHypervisorRootPTE(hgatp: PTBR, vpn: UInt, default: PTE) = { val count = pgLevels.U - minPgLevels.U - hgatp.additionalPgLevels val idxs = (0 to pgLevels-minPgLevels).map(i => (vpn >> (pgLevels-i)*pgLevelBits)) val lsbs = WireDefault(UInt(maxHypervisorExtraAddrBits.W), idxs(count)) val pte = WireDefault(default) pte.ppn := Cat(hgatp.ppn >> maxHypervisorExtraAddrBits, lsbs) pte } /** use hgatp and vpn to check for gpa out of range */ private def checkInvalidHypervisorGPA(hgatp: PTBR, vpn: UInt) = { val count = pgLevels.U - minPgLevels.U - hgatp.additionalPgLevels val idxs = (0 to pgLevels-minPgLevels).map(i => (vpn >> ((pgLevels-i)*pgLevelBits)+maxHypervisorExtraAddrBits)) idxs.extract(count) =/= 0.U } } /** Mix-ins for constructing tiles that might have a PTW */ trait CanHavePTW extends HasTileParameters with HasHellaCache { this: BaseTile => val module: CanHavePTWModule var nPTWPorts = 1 nDCachePorts += usingPTW.toInt } trait CanHavePTWModule extends HasHellaCacheModule { val outer: CanHavePTW val ptwPorts = ListBuffer(outer.dcache.module.io.ptw) val ptw = Module(new PTW(outer.nPTWPorts)(outer.dcache.node.edges.out(0), outer.p)) ptw.io.mem <> DontCare if (outer.usingPTW) { dcachePorts += ptw.io.mem } } File HierarchicalElement.scala: package freechips.rocketchip.subsystem import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.devices.debug.TLDebugModule import freechips.rocketchip.diplomacy.{BufferParams} import freechips.rocketchip.interrupts.IntXbar import freechips.rocketchip.prci.{ClockSinkParameters, ResetCrossingType, ClockCrossingType} import freechips.rocketchip.tile.{LookupByHartIdImpl, TraceBundle} import freechips.rocketchip.tilelink.{TLNode, TLIdentityNode, TLXbar, TLBuffer, TLInwardNode, TLOutwardNode} trait HierarchicalElementParams { val baseName: String // duplicated instances shouuld share a base name val uniqueName: String val clockSinkParams: ClockSinkParameters } abstract class InstantiableHierarchicalElementParams[ElementType <: BaseHierarchicalElement] extends HierarchicalElementParams /** An interface for describing the parameteization of how HierarchicalElements are connected to interconnects */ trait HierarchicalElementCrossingParamsLike { /** The type of clock crossing that should be inserted at the element boundary. */ def crossingType: ClockCrossingType /** Parameters describing the contents and behavior of the point where the element is attached as an interconnect master. */ def master: HierarchicalElementPortParamsLike /** Parameters describing the contents and behavior of the point where the element is attached as an interconnect slave. */ def slave: HierarchicalElementPortParamsLike /** The subnetwork location of the device selecting the apparent base address of MMIO devices inside the element */ def mmioBaseAddressPrefixWhere: TLBusWrapperLocation /** Inject a reset management subgraph that effects the element child reset only */ def resetCrossingType: ResetCrossingType /** Keep the element clock separate from the interconnect clock (e.g. even if they are synchronous to one another) */ def forceSeparateClockReset: Boolean } /** An interface for describing the parameterization of how a particular element port is connected to an interconnect */ trait HierarchicalElementPortParamsLike { /** The subnetwork location of the interconnect to which this element port should be connected. */ def where: TLBusWrapperLocation /** Allows port-specific adapters to be injected into the interconnect side of the attachment point. */ def injectNode(context: Attachable)(implicit p: Parameters): TLNode } abstract class BaseHierarchicalElement (val crossing: ClockCrossingType)(implicit p: Parameters) extends LazyModule()(p) with CrossesToOnlyOneClockDomain { def module: BaseHierarchicalElementModuleImp[BaseHierarchicalElement] protected val tlOtherMastersNode = TLIdentityNode() protected val tlMasterXbar = LazyModule(new TLXbar(nameSuffix = Some(s"MasterXbar_$desiredName"))) protected val tlSlaveXbar = LazyModule(new TLXbar(nameSuffix = Some(s"SlaveXbar_$desiredName"))) protected val intXbar = LazyModule(new IntXbar) def masterNode: TLOutwardNode def slaveNode: TLInwardNode /** Helper function to insert additional buffers on master ports at the boundary of the tile. * * The boundary buffering needed to cut feed-through paths is * microarchitecture specific, so this may need to be overridden * in subclasses of this class. */ def makeMasterBoundaryBuffers(crossing: ClockCrossingType)(implicit p: Parameters) = TLBuffer(BufferParams.none) /** Helper function to insert additional buffers on slave ports at the boundary of the tile. * * The boundary buffering needed to cut feed-through paths is * microarchitecture specific, so this may need to be overridden * in subclasses of this class. */ def makeSlaveBoundaryBuffers(crossing: ClockCrossingType)(implicit p: Parameters) = TLBuffer(BufferParams.none) } abstract class BaseHierarchicalElementModuleImp[+L <: BaseHierarchicalElement](val outer: L) extends LazyModuleImp(outer) File RocketTile.scala: // See LICENSE.SiFive for license details. // See LICENSE.Berkeley for license details. package freechips.rocketchip.tile import chisel3._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.devices.tilelink.{BasicBusBlockerParams, BasicBusBlocker} import freechips.rocketchip.diplomacy.{ AddressSet, DisableMonitors, BufferParams } import freechips.rocketchip.resources.{ SimpleDevice, Description, ResourceAnchors, ResourceBindings, ResourceBinding, Resource, ResourceAddress, } import freechips.rocketchip.interrupts.IntIdentityNode import freechips.rocketchip.tilelink.{TLIdentityNode, TLBuffer} import freechips.rocketchip.rocket.{ RocketCoreParams, ICacheParams, DCacheParams, BTBParams, HasHellaCache, HasICacheFrontend, ScratchpadSlavePort, HasICacheFrontendModule, Rocket } import freechips.rocketchip.subsystem.HierarchicalElementCrossingParamsLike import freechips.rocketchip.prci.{ClockSinkParameters, RationalCrossing, ClockCrossingType} import freechips.rocketchip.util.{Annotated, InOrderArbiter} import freechips.rocketchip.util.BooleanToAugmentedBoolean case class RocketTileBoundaryBufferParams(force: Boolean = false) case class RocketTileParams( core: RocketCoreParams = RocketCoreParams(), icache: Option[ICacheParams] = Some(ICacheParams()), dcache: Option[DCacheParams] = Some(DCacheParams()), btb: Option[BTBParams] = Some(BTBParams()), dataScratchpadBytes: Int = 0, tileId: Int = 0, beuAddr: Option[BigInt] = None, blockerCtrlAddr: Option[BigInt] = None, clockSinkParams: ClockSinkParameters = ClockSinkParameters(), boundaryBuffers: Option[RocketTileBoundaryBufferParams] = None ) extends InstantiableTileParams[RocketTile] { require(icache.isDefined) require(dcache.isDefined) val baseName = "rockettile" val uniqueName = s"${baseName}_$tileId" def instantiate(crossing: HierarchicalElementCrossingParamsLike, lookup: LookupByHartIdImpl)(implicit p: Parameters): RocketTile = { new RocketTile(this, crossing, lookup) } } class RocketTile private( val rocketParams: RocketTileParams, crossing: ClockCrossingType, lookup: LookupByHartIdImpl, q: Parameters) extends BaseTile(rocketParams, crossing, lookup, q) with SinksExternalInterrupts with SourcesExternalNotifications with HasLazyRoCC // implies CanHaveSharedFPU with CanHavePTW with HasHellaCache with HasHellaCache with HasICacheFrontend { // Private constructor ensures altered LazyModule.p is used implicitly def this(params: RocketTileParams, crossing: HierarchicalElementCrossingParamsLike, lookup: LookupByHartIdImpl)(implicit p: Parameters) = this(params, crossing.crossingType, lookup, p) val intOutwardNode = rocketParams.beuAddr map { _ => IntIdentityNode() } val slaveNode = TLIdentityNode() val masterNode = visibilityNode val dtim_adapter = tileParams.dcache.flatMap { d => d.scratch.map { s => LazyModule(new ScratchpadSlavePort(AddressSet.misaligned(s, d.dataScratchpadBytes), lazyCoreParamsView.coreDataBytes, tileParams.core.useAtomics && !tileParams.core.useAtomicsOnlyForIO)) }} dtim_adapter.foreach(lm => connectTLSlave(lm.node, lm.node.portParams.head.beatBytes)) val bus_error_unit = rocketParams.beuAddr map { a => val beu = LazyModule(new BusErrorUnit(new L1BusErrors, BusErrorUnitParams(a), xLen/8)) intOutwardNode.get := beu.intNode connectTLSlave(beu.node, xBytes) beu } val tile_master_blocker = tileParams.blockerCtrlAddr .map(BasicBusBlockerParams(_, xBytes, masterPortBeatBytes, deadlock = true)) .map(bp => LazyModule(new BasicBusBlocker(bp))) tile_master_blocker.foreach(lm => connectTLSlave(lm.controlNode, xBytes)) // TODO: this doesn't block other masters, e.g. RoCCs tlOtherMastersNode := tile_master_blocker.map { _.node := tlMasterXbar.node } getOrElse { tlMasterXbar.node } masterNode :=* tlOtherMastersNode DisableMonitors { implicit p => tlSlaveXbar.node :*= slaveNode } nDCachePorts += 1 /*core */ + (dtim_adapter.isDefined).toInt + rocketParams.core.vector.map(_.useDCache.toInt).getOrElse(0) val dtimProperty = dtim_adapter.map(d => Map( "sifive,dtim" -> d.device.asProperty)).getOrElse(Nil) val itimProperty = frontend.icache.itimProperty.toSeq.flatMap(p => Map("sifive,itim" -> p)) val beuProperty = bus_error_unit.map(d => Map( "sifive,buserror" -> d.device.asProperty)).getOrElse(Nil) val cpuDevice: SimpleDevice = new SimpleDevice("cpu", Seq("sifive,rocket0", "riscv")) { override def parent = Some(ResourceAnchors.cpus) override def describe(resources: ResourceBindings): Description = { val Description(name, mapping) = super.describe(resources) Description(name, mapping ++ cpuProperties ++ nextLevelCacheProperty ++ tileProperties ++ dtimProperty ++ itimProperty ++ beuProperty) } } val vector_unit = rocketParams.core.vector.map(v => LazyModule(v.build(p))) vector_unit.foreach(vu => tlMasterXbar.node :=* vu.atlNode) vector_unit.foreach(vu => tlOtherMastersNode :=* vu.tlNode) ResourceBinding { Resource(cpuDevice, "reg").bind(ResourceAddress(tileId)) } override lazy val module = new RocketTileModuleImp(this) override def makeMasterBoundaryBuffers(crossing: ClockCrossingType)(implicit p: Parameters) = (rocketParams.boundaryBuffers, crossing) match { case (Some(RocketTileBoundaryBufferParams(true )), _) => TLBuffer() case (Some(RocketTileBoundaryBufferParams(false)), _: RationalCrossing) => TLBuffer(BufferParams.none, BufferParams.flow, BufferParams.none, BufferParams.flow, BufferParams(1)) case _ => TLBuffer(BufferParams.none) } override def makeSlaveBoundaryBuffers(crossing: ClockCrossingType)(implicit p: Parameters) = (rocketParams.boundaryBuffers, crossing) match { case (Some(RocketTileBoundaryBufferParams(true )), _) => TLBuffer() case (Some(RocketTileBoundaryBufferParams(false)), _: RationalCrossing) => TLBuffer(BufferParams.flow, BufferParams.none, BufferParams.none, BufferParams.none, BufferParams.none) case _ => TLBuffer(BufferParams.none) } } class RocketTileModuleImp(outer: RocketTile) extends BaseTileModuleImp(outer) with HasFpuOpt with HasLazyRoCCModule with HasICacheFrontendModule { Annotated.params(this, outer.rocketParams) val core = Module(new Rocket(outer)(outer.p)) outer.vector_unit.foreach { v => core.io.vector.get <> v.module.io.core v.module.io.tlb <> outer.dcache.module.io.tlb_port } // reset vector is connected in the Frontend to s2_pc core.io.reset_vector := DontCare // Report unrecoverable error conditions; for now the only cause is cache ECC errors outer.reportHalt(List(outer.dcache.module.io.errors)) // Report when the tile has ceased to retire instructions; for now the only cause is clock gating outer.reportCease(outer.rocketParams.core.clockGate.option( !outer.dcache.module.io.cpu.clock_enabled && !outer.frontend.module.io.cpu.clock_enabled && !ptw.io.dpath.clock_enabled && core.io.cease)) outer.reportWFI(Some(core.io.wfi)) outer.decodeCoreInterrupts(core.io.interrupts) // Decode the interrupt vector outer.bus_error_unit.foreach { beu => core.io.interrupts.buserror.get := beu.module.io.interrupt beu.module.io.errors.dcache := outer.dcache.module.io.errors beu.module.io.errors.icache := outer.frontend.module.io.errors } core.io.interrupts.nmi.foreach { nmi => nmi := outer.nmiSinkNode.get.bundle } // Pass through various external constants and reports that were bundle-bridged into the tile outer.traceSourceNode.bundle <> core.io.trace core.io.traceStall := outer.traceAuxSinkNode.bundle.stall outer.bpwatchSourceNode.bundle <> core.io.bpwatch core.io.hartid := outer.hartIdSinkNode.bundle require(core.io.hartid.getWidth >= outer.hartIdSinkNode.bundle.getWidth, s"core hartid wire (${core.io.hartid.getWidth}b) truncates external hartid wire (${outer.hartIdSinkNode.bundle.getWidth}b)") // Connect the core pipeline to other intra-tile modules outer.frontend.module.io.cpu <> core.io.imem dcachePorts += core.io.dmem // TODO outer.dcachePorts += () => module.core.io.dmem ?? fpuOpt foreach { fpu => core.io.fpu :<>= fpu.io.waiveAs[FPUCoreIO](_.cp_req, _.cp_resp) } if (fpuOpt.isEmpty) { core.io.fpu := DontCare } outer.vector_unit foreach { v => if (outer.rocketParams.core.vector.get.useDCache) { dcachePorts += v.module.io.dmem } else { v.module.io.dmem := DontCare } } core.io.ptw <> ptw.io.dpath // Connect the coprocessor interfaces if (outer.roccs.size > 0) { cmdRouter.get.io.in <> core.io.rocc.cmd outer.roccs.foreach{ lm => lm.module.io.exception := core.io.rocc.exception lm.module.io.fpu_req.ready := DontCare lm.module.io.fpu_resp.valid := DontCare lm.module.io.fpu_resp.bits.data := DontCare lm.module.io.fpu_resp.bits.exc := DontCare } core.io.rocc.resp <> respArb.get.io.out core.io.rocc.busy <> (cmdRouter.get.io.busy || outer.roccs.map(_.module.io.busy).reduce(_ || _)) core.io.rocc.interrupt := outer.roccs.map(_.module.io.interrupt).reduce(_ || _) (core.io.rocc.csrs zip roccCSRIOs.flatten).foreach { t => t._2 <> t._1 } } else { // tie off core.io.rocc.cmd.ready := false.B core.io.rocc.resp.valid := false.B core.io.rocc.resp.bits := DontCare core.io.rocc.busy := DontCare core.io.rocc.interrupt := DontCare } // Dont care mem since not all RoCC need accessing memory core.io.rocc.mem := DontCare // Rocket has higher priority to DTIM than other TileLink clients outer.dtim_adapter.foreach { lm => dcachePorts += lm.module.io.dmem } // TODO eliminate this redundancy val h = dcachePorts.size val c = core.dcacheArbPorts val o = outer.nDCachePorts require(h == c, s"port list size was $h, core expected $c") require(h == o, s"port list size was $h, outer counted $o") // TODO figure out how to move the below into their respective mix-ins dcacheArb.io.requestor <> dcachePorts.toSeq ptw.io.requestor <> ptwPorts.toSeq } trait HasFpuOpt { this: RocketTileModuleImp => val fpuOpt = outer.tileParams.core.fpu.map(params => Module(new FPU(params)(outer.p))) fpuOpt.foreach { fpu => val nRoCCFPUPorts = outer.roccs.count(_.usesFPU) val nFPUPorts = nRoCCFPUPorts + outer.rocketParams.core.useVector.toInt if (nFPUPorts > 0) { val fpArb = Module(new InOrderArbiter(new FPInput()(outer.p), new FPResult()(outer.p), nFPUPorts)) fpu.io.cp_req <> fpArb.io.out_req fpArb.io.out_resp <> fpu.io.cp_resp val fp_rocc_ios = outer.roccs.filter(_.usesFPU).map(_.module.io) for (i <- 0 until nRoCCFPUPorts) { fpArb.io.in_req(i) <> fp_rocc_ios(i).fpu_req fp_rocc_ios(i).fpu_resp <> fpArb.io.in_resp(i) } outer.vector_unit.foreach(vu => { fpArb.io.in_req(nRoCCFPUPorts) <> vu.module.io.fp_req vu.module.io.fp_resp <> fpArb.io.in_resp(nRoCCFPUPorts) }) } else { fpu.io.cp_req.valid := false.B fpu.io.cp_req.bits := DontCare fpu.io.cp_resp.ready := false.B } } }

module RocketTile( // @[RocketTile.scala:141:7] input clock, // @[RocketTile.scala:141:7] input reset, // @[RocketTile.scala:141:7] input auto_buffer_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_buffer_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_buffer_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_buffer_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_buffer_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [5:0] auto_buffer_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_buffer_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_buffer_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_buffer_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_buffer_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_buffer_out_b_ready, // @[LazyModuleImp.scala:107:25] input auto_buffer_out_b_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_buffer_out_b_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_buffer_out_b_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_buffer_out_b_bits_size, // @[LazyModuleImp.scala:107:25] input [5:0] auto_buffer_out_b_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_buffer_out_b_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_buffer_out_b_bits_mask, // @[LazyModuleImp.scala:107:25] input auto_buffer_out_b_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_buffer_out_c_ready, // @[LazyModuleImp.scala:107:25] output auto_buffer_out_c_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_buffer_out_c_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_buffer_out_c_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_buffer_out_c_bits_size, // @[LazyModuleImp.scala:107:25] output [5:0] auto_buffer_out_c_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_buffer_out_c_bits_address, // @[LazyModuleImp.scala:107:25] output [63:0] auto_buffer_out_c_bits_data, // @[LazyModuleImp.scala:107:25] output auto_buffer_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_buffer_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_buffer_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_buffer_out_d_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_buffer_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [5:0] auto_buffer_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input [2:0] auto_buffer_out_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_buffer_out_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_buffer_out_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_buffer_out_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_buffer_out_e_ready, // @[LazyModuleImp.scala:107:25] output auto_buffer_out_e_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_buffer_out_e_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_wfi_out_0, // @[LazyModuleImp.scala:107:25] input auto_int_local_in_3_0, // @[LazyModuleImp.scala:107:25] input auto_int_local_in_2_0, // @[LazyModuleImp.scala:107:25] input auto_int_local_in_1_0, // @[LazyModuleImp.scala:107:25] input auto_int_local_in_1_1, // @[LazyModuleImp.scala:107:25] input auto_int_local_in_0_0, // @[LazyModuleImp.scala:107:25] input auto_hartid_in // @[LazyModuleImp.scala:107:25] ); wire _core_io_imem_might_request; // @[RocketTile.scala:147:20] wire _core_io_imem_req_valid; // @[RocketTile.scala:147:20] wire [39:0] _core_io_imem_req_bits_pc; // @[RocketTile.scala:147:20] wire _core_io_imem_req_bits_speculative; // @[RocketTile.scala:147:20] wire _core_io_imem_sfence_valid; // @[RocketTile.scala:147:20] wire _core_io_imem_sfence_bits_rs1; // @[RocketTile.scala:147:20] wire _core_io_imem_sfence_bits_rs2; // @[RocketTile.scala:147:20] wire [38:0] _core_io_imem_sfence_bits_addr; // @[RocketTile.scala:147:20] wire _core_io_imem_resp_ready; // @[RocketTile.scala:147:20] wire _core_io_imem_btb_update_valid; // @[RocketTile.scala:147:20] wire [4:0] _core_io_imem_btb_update_bits_prediction_entry; // @[RocketTile.scala:147:20] wire [38:0] _core_io_imem_btb_update_bits_pc; // @[RocketTile.scala:147:20] wire _core_io_imem_btb_update_bits_isValid; // @[RocketTile.scala:147:20] wire [38:0] _core_io_imem_btb_update_bits_br_pc; // @[RocketTile.scala:147:20] wire [1:0] _core_io_imem_btb_update_bits_cfiType; // @[RocketTile.scala:147:20] wire _core_io_imem_bht_update_valid; // @[RocketTile.scala:147:20] wire [7:0] _core_io_imem_bht_update_bits_prediction_history; // @[RocketTile.scala:147:20] wire [38:0] _core_io_imem_bht_update_bits_pc; // @[RocketTile.scala:147:20] wire _core_io_imem_bht_update_bits_branch; // @[RocketTile.scala:147:20] wire _core_io_imem_bht_update_bits_taken; // @[RocketTile.scala:147:20] wire _core_io_imem_bht_update_bits_mispredict; // @[RocketTile.scala:147:20] wire _core_io_imem_flush_icache; // @[RocketTile.scala:147:20] wire _core_io_imem_progress; // @[RocketTile.scala:147:20] wire _core_io_dmem_req_valid; // @[RocketTile.scala:147:20] wire [39:0] _core_io_dmem_req_bits_addr; // @[RocketTile.scala:147:20] wire [7:0] _core_io_dmem_req_bits_tag; // @[RocketTile.scala:147:20] wire [4:0] _core_io_dmem_req_bits_cmd; // @[RocketTile.scala:147:20] wire [1:0] _core_io_dmem_req_bits_size; // @[RocketTile.scala:147:20] wire _core_io_dmem_req_bits_signed; // @[RocketTile.scala:147:20] wire [1:0] _core_io_dmem_req_bits_dprv; // @[RocketTile.scala:147:20] wire _core_io_dmem_req_bits_dv; // @[RocketTile.scala:147:20] wire _core_io_dmem_s1_kill; // @[RocketTile.scala:147:20] wire [63:0] _core_io_dmem_s1_data_data; // @[RocketTile.scala:147:20] wire [3:0] _core_io_ptw_ptbr_mode; // @[RocketTile.scala:147:20] wire [43:0] _core_io_ptw_ptbr_ppn; // @[RocketTile.scala:147:20] wire _core_io_ptw_sfence_valid; // @[RocketTile.scala:147:20] wire _core_io_ptw_sfence_bits_rs1; // @[RocketTile.scala:147:20] wire _core_io_ptw_status_debug; // @[RocketTile.scala:147:20] wire [1:0] _core_io_ptw_status_prv; // @[RocketTile.scala:147:20] wire _core_io_ptw_status_mxr; // @[RocketTile.scala:147:20] wire _core_io_ptw_status_sum; // @[RocketTile.scala:147:20] wire _core_io_ptw_pmp_0_cfg_l; // @[RocketTile.scala:147:20] wire [1:0] _core_io_ptw_pmp_0_cfg_a; // @[RocketTile.scala:147:20] wire _core_io_ptw_pmp_0_cfg_x; // @[RocketTile.scala:147:20] wire _core_io_ptw_pmp_0_cfg_w; // @[RocketTile.scala:147:20] wire _core_io_ptw_pmp_0_cfg_r; // @[RocketTile.scala:147:20] wire [29:0] _core_io_ptw_pmp_0_addr; // @[RocketTile.scala:147:20] wire [31:0] _core_io_ptw_pmp_0_mask; // @[RocketTile.scala:147:20] wire _core_io_ptw_pmp_1_cfg_l; // @[RocketTile.scala:147:20] wire [1:0] _core_io_ptw_pmp_1_cfg_a; // @[RocketTile.scala:147:20] wire _core_io_ptw_pmp_1_cfg_x; // @[RocketTile.scala:147:20] wire _core_io_ptw_pmp_1_cfg_w; // @[RocketTile.scala:147:20] wire _core_io_ptw_pmp_1_cfg_r; // @[RocketTile.scala:147:20] wire [29:0] _core_io_ptw_pmp_1_addr; // @[RocketTile.scala:147:20] wire [31:0] _core_io_ptw_pmp_1_mask; // @[RocketTile.scala:147:20] wire _core_io_ptw_pmp_2_cfg_l; // @[RocketTile.scala:147:20] wire [1:0] _core_io_ptw_pmp_2_cfg_a; // @[RocketTile.scala:147:20] wire _core_io_ptw_pmp_2_cfg_x; // @[RocketTile.scala:147:20] wire _core_io_ptw_pmp_2_cfg_w; // @[RocketTile.scala:147:20] wire _core_io_ptw_pmp_2_cfg_r; // @[RocketTile.scala:147:20] wire [29:0] _core_io_ptw_pmp_2_addr; // @[RocketTile.scala:147:20] wire [31:0] _core_io_ptw_pmp_2_mask; // @[RocketTile.scala:147:20] wire _core_io_ptw_pmp_3_cfg_l; // @[RocketTile.scala:147:20] wire [1:0] _core_io_ptw_pmp_3_cfg_a; // @[RocketTile.scala:147:20] wire _core_io_ptw_pmp_3_cfg_x; // @[RocketTile.scala:147:20] wire _core_io_ptw_pmp_3_cfg_w; // @[RocketTile.scala:147:20] wire _core_io_ptw_pmp_3_cfg_r; // @[RocketTile.scala:147:20] wire [29:0] _core_io_ptw_pmp_3_addr; // @[RocketTile.scala:147:20] wire [31:0] _core_io_ptw_pmp_3_mask; // @[RocketTile.scala:147:20] wire _core_io_ptw_pmp_4_cfg_l; // @[RocketTile.scala:147:20] wire [1:0] _core_io_ptw_pmp_4_cfg_a; // @[RocketTile.scala:147:20] wire _core_io_ptw_pmp_4_cfg_x; // @[RocketTile.scala:147:20] wire _core_io_ptw_pmp_4_cfg_w; // @[RocketTile.scala:147:20] wire _core_io_ptw_pmp_4_cfg_r; // @[RocketTile.scala:147:20] wire [29:0] _core_io_ptw_pmp_4_addr; // @[RocketTile.scala:147:20] wire [31:0] _core_io_ptw_pmp_4_mask; // @[RocketTile.scala:147:20] wire _core_io_ptw_pmp_5_cfg_l; // @[RocketTile.scala:147:20] wire [1:0] _core_io_ptw_pmp_5_cfg_a; // @[RocketTile.scala:147:20] wire _core_io_ptw_pmp_5_cfg_x; // @[RocketTile.scala:147:20] wire _core_io_ptw_pmp_5_cfg_w; // @[RocketTile.scala:147:20] wire _core_io_ptw_pmp_5_cfg_r; // @[RocketTile.scala:147:20] wire [29:0] _core_io_ptw_pmp_5_addr; // @[RocketTile.scala:147:20] wire [31:0] _core_io_ptw_pmp_5_mask; // @[RocketTile.scala:147:20] wire _core_io_ptw_pmp_6_cfg_l; // @[RocketTile.scala:147:20] wire [1:0] _core_io_ptw_pmp_6_cfg_a; // @[RocketTile.scala:147:20] wire _core_io_ptw_pmp_6_cfg_x; // @[RocketTile.scala:147:20] wire _core_io_ptw_pmp_6_cfg_w; // @[RocketTile.scala:147:20] wire _core_io_ptw_pmp_6_cfg_r; // @[RocketTile.scala:147:20] wire [29:0] _core_io_ptw_pmp_6_addr; // @[RocketTile.scala:147:20] wire [31:0] _core_io_ptw_pmp_6_mask; // @[RocketTile.scala:147:20] wire _core_io_ptw_pmp_7_cfg_l; // @[RocketTile.scala:147:20] wire [1:0] _core_io_ptw_pmp_7_cfg_a; // @[RocketTile.scala:147:20] wire _core_io_ptw_pmp_7_cfg_x; // @[RocketTile.scala:147:20] wire _core_io_ptw_pmp_7_cfg_w; // @[RocketTile.scala:147:20] wire _core_io_ptw_pmp_7_cfg_r; // @[RocketTile.scala:147:20] wire [29:0] _core_io_ptw_pmp_7_addr; // @[RocketTile.scala:147:20] wire [31:0] _core_io_ptw_pmp_7_mask; // @[RocketTile.scala:147:20] wire [63:0] _core_io_ptw_customCSRs_csrs_0_value; // @[RocketTile.scala:147:20] wire [31:0] _core_io_fpu_inst; // @[RocketTile.scala:147:20] wire [63:0] _core_io_fpu_fromint_data; // @[RocketTile.scala:147:20] wire [2:0] _core_io_fpu_fcsr_rm; // @[RocketTile.scala:147:20] wire [2:0] _core_io_fpu_v_sew; // @[RocketTile.scala:147:20] wire _core_io_fpu_ll_resp_val; // @[RocketTile.scala:147:20] wire [2:0] _core_io_fpu_ll_resp_type; // @[RocketTile.scala:147:20] wire [4:0] _core_io_fpu_ll_resp_tag; // @[RocketTile.scala:147:20] wire [63:0] _core_io_fpu_ll_resp_data; // @[RocketTile.scala:147:20] wire _core_io_fpu_valid; // @[RocketTile.scala:147:20] wire _core_io_fpu_killx; // @[RocketTile.scala:147:20] wire _core_io_fpu_killm; // @[RocketTile.scala:147:20] wire _core_io_wfi; // @[RocketTile.scala:147:20] wire _core_io_vector_status_dv; // @[RocketTile.scala:147:20] wire [1:0] _core_io_vector_status_prv; // @[RocketTile.scala:147:20] wire _core_io_vector_ex_valid; // @[RocketTile.scala:147:20] wire [31:0] _core_io_vector_ex_inst; // @[RocketTile.scala:147:20] wire [39:0] _core_io_vector_ex_pc; // @[RocketTile.scala:147:20] wire [8:0] _core_io_vector_ex_vconfig_vl; // @[RocketTile.scala:147:20] wire _core_io_vector_ex_vconfig_vtype_vill; // @[RocketTile.scala:147:20] wire [54:0] _core_io_vector_ex_vconfig_vtype_reserved; // @[RocketTile.scala:147:20] wire _core_io_vector_ex_vconfig_vtype_vma; // @[RocketTile.scala:147:20] wire _core_io_vector_ex_vconfig_vtype_vta; // @[RocketTile.scala:147:20] wire [2:0] _core_io_vector_ex_vconfig_vtype_vsew; // @[RocketTile.scala:147:20] wire _core_io_vector_ex_vconfig_vtype_vlmul_sign; // @[RocketTile.scala:147:20] wire [1:0] _core_io_vector_ex_vconfig_vtype_vlmul_mag; // @[RocketTile.scala:147:20] wire [7:0] _core_io_vector_ex_vstart; // @[RocketTile.scala:147:20] wire [63:0] _core_io_vector_ex_rs1; // @[RocketTile.scala:147:20] wire [63:0] _core_io_vector_ex_rs2; // @[RocketTile.scala:147:20] wire _core_io_vector_killm; // @[RocketTile.scala:147:20] wire [63:0] _core_io_vector_mem_frs1; // @[RocketTile.scala:147:20] wire _core_io_vector_wb_store_pending; // @[RocketTile.scala:147:20] wire [1:0] _core_io_vector_wb_vxrm; // @[RocketTile.scala:147:20] wire [2:0] _core_io_vector_wb_frm; // @[RocketTile.scala:147:20] wire _core_io_vector_resp_ready; // @[RocketTile.scala:147:20] wire _ptw_io_requestor_0_req_ready; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_resp_valid; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_resp_bits_ae_ptw; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_resp_bits_ae_final; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_resp_bits_pf; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_resp_bits_gf; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_resp_bits_hr; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_resp_bits_hw; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_resp_bits_hx; // @[PTW.scala:802:19] wire [43:0] _ptw_io_requestor_0_resp_bits_pte_ppn; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_resp_bits_pte_d; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_resp_bits_pte_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_resp_bits_pte_g; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_resp_bits_pte_u; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_resp_bits_pte_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_resp_bits_pte_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_resp_bits_pte_r; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_resp_bits_pte_v; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_0_resp_bits_level; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_resp_bits_homogeneous; // @[PTW.scala:802:19] wire [3:0] _ptw_io_requestor_0_ptbr_mode; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_status_debug; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_status_mxr; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_status_sum; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_pmp_0_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_0_pmp_0_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_pmp_0_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_pmp_0_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_pmp_0_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_0_pmp_0_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_0_pmp_0_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_pmp_1_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_0_pmp_1_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_pmp_1_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_pmp_1_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_pmp_1_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_0_pmp_1_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_0_pmp_1_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_pmp_2_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_0_pmp_2_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_pmp_2_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_pmp_2_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_pmp_2_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_0_pmp_2_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_0_pmp_2_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_pmp_3_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_0_pmp_3_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_pmp_3_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_pmp_3_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_pmp_3_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_0_pmp_3_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_0_pmp_3_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_pmp_4_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_0_pmp_4_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_pmp_4_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_pmp_4_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_pmp_4_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_0_pmp_4_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_0_pmp_4_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_pmp_5_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_0_pmp_5_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_pmp_5_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_pmp_5_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_pmp_5_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_0_pmp_5_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_0_pmp_5_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_pmp_6_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_0_pmp_6_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_pmp_6_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_pmp_6_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_pmp_6_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_0_pmp_6_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_0_pmp_6_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_pmp_7_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_0_pmp_7_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_pmp_7_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_pmp_7_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_pmp_7_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_0_pmp_7_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_0_pmp_7_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_req_ready; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_resp_valid; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_resp_bits_ae_ptw; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_resp_bits_ae_final; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_resp_bits_pf; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_resp_bits_gf; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_resp_bits_hr; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_resp_bits_hw; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_resp_bits_hx; // @[PTW.scala:802:19] wire [43:0] _ptw_io_requestor_1_resp_bits_pte_ppn; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_resp_bits_pte_d; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_resp_bits_pte_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_resp_bits_pte_g; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_resp_bits_pte_u; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_resp_bits_pte_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_resp_bits_pte_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_resp_bits_pte_r; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_resp_bits_pte_v; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_1_resp_bits_level; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_resp_bits_homogeneous; // @[PTW.scala:802:19] wire [3:0] _ptw_io_requestor_1_ptbr_mode; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_status_debug; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_1_status_prv; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_pmp_0_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_1_pmp_0_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_pmp_0_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_pmp_0_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_pmp_0_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_1_pmp_0_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_1_pmp_0_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_pmp_1_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_1_pmp_1_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_pmp_1_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_pmp_1_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_pmp_1_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_1_pmp_1_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_1_pmp_1_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_pmp_2_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_1_pmp_2_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_pmp_2_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_pmp_2_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_pmp_2_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_1_pmp_2_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_1_pmp_2_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_pmp_3_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_1_pmp_3_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_pmp_3_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_pmp_3_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_pmp_3_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_1_pmp_3_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_1_pmp_3_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_pmp_4_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_1_pmp_4_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_pmp_4_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_pmp_4_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_pmp_4_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_1_pmp_4_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_1_pmp_4_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_pmp_5_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_1_pmp_5_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_pmp_5_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_pmp_5_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_pmp_5_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_1_pmp_5_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_1_pmp_5_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_pmp_6_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_1_pmp_6_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_pmp_6_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_pmp_6_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_pmp_6_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_1_pmp_6_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_1_pmp_6_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_pmp_7_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_1_pmp_7_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_pmp_7_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_pmp_7_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_pmp_7_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_1_pmp_7_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_1_pmp_7_mask; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_1_customCSRs_csrs_0_value; // @[PTW.scala:802:19] wire _ptw_io_mem_req_valid; // @[PTW.scala:802:19] wire [39:0] _ptw_io_mem_req_bits_addr; // @[PTW.scala:802:19] wire _ptw_io_mem_s1_kill; // @[PTW.scala:802:19] wire _dcacheArb_io_requestor_0_req_ready; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_0_s2_nack; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_0_resp_valid; // @[HellaCache.scala:292:25] wire [63:0] _dcacheArb_io_requestor_0_resp_bits_data; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_0_s2_xcpt_ae_ld; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_1_req_ready; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_1_s2_nack; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_1_resp_valid; // @[HellaCache.scala:292:25] wire [7:0] _dcacheArb_io_requestor_1_resp_bits_tag; // @[HellaCache.scala:292:25] wire [1:0] _dcacheArb_io_requestor_1_resp_bits_size; // @[HellaCache.scala:292:25] wire [63:0] _dcacheArb_io_requestor_1_resp_bits_data; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_1_resp_bits_replay; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_1_resp_bits_has_data; // @[HellaCache.scala:292:25] wire [63:0] _dcacheArb_io_requestor_1_resp_bits_data_word_bypass; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_1_replay_next; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_1_s2_xcpt_ma_ld; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_1_s2_xcpt_ma_st; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_1_s2_xcpt_pf_ld; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_1_s2_xcpt_pf_st; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_1_s2_xcpt_ae_ld; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_1_s2_xcpt_ae_st; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_1_ordered; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_1_store_pending; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_1_perf_release; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_1_perf_grant; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_2_req_ready; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_2_s2_nack; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_2_resp_valid; // @[HellaCache.scala:292:25] wire [7:0] _dcacheArb_io_requestor_2_resp_bits_tag; // @[HellaCache.scala:292:25] wire [63:0] _dcacheArb_io_requestor_2_resp_bits_data_raw; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_2_s2_xcpt_ma_ld; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_2_s2_xcpt_ma_st; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_2_s2_xcpt_pf_ld; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_2_s2_xcpt_pf_st; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_2_s2_xcpt_ae_ld; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_2_s2_xcpt_ae_st; // @[HellaCache.scala:292:25] wire _dcacheArb_io_mem_req_valid; // @[HellaCache.scala:292:25] wire [39:0] _dcacheArb_io_mem_req_bits_addr; // @[HellaCache.scala:292:25] wire [7:0] _dcacheArb_io_mem_req_bits_tag; // @[HellaCache.scala:292:25] wire [4:0] _dcacheArb_io_mem_req_bits_cmd; // @[HellaCache.scala:292:25] wire [1:0] _dcacheArb_io_mem_req_bits_size; // @[HellaCache.scala:292:25] wire _dcacheArb_io_mem_req_bits_signed; // @[HellaCache.scala:292:25] wire [1:0] _dcacheArb_io_mem_req_bits_dprv; // @[HellaCache.scala:292:25] wire _dcacheArb_io_mem_req_bits_dv; // @[HellaCache.scala:292:25] wire _dcacheArb_io_mem_req_bits_phys; // @[HellaCache.scala:292:25] wire _dcacheArb_io_mem_req_bits_no_alloc; // @[HellaCache.scala:292:25] wire _dcacheArb_io_mem_req_bits_no_xcpt; // @[HellaCache.scala:292:25] wire [7:0] _dcacheArb_io_mem_req_bits_mask; // @[HellaCache.scala:292:25] wire _dcacheArb_io_mem_s1_kill; // @[HellaCache.scala:292:25] wire [63:0] _dcacheArb_io_mem_s1_data_data; // @[HellaCache.scala:292:25] wire [7:0] _dcacheArb_io_mem_s1_data_mask; // @[HellaCache.scala:292:25] wire _fpArb_io_in_req_0_ready; // @[RocketTile.scala:247:25] wire _fpArb_io_in_resp_0_valid; // @[RocketTile.scala:247:25] wire [64:0] _fpArb_io_in_resp_0_bits_data; // @[RocketTile.scala:247:25] wire _fpArb_io_out_req_valid; // @[RocketTile.scala:247:25] wire _fpArb_io_out_req_bits_ren2; // @[RocketTile.scala:247:25] wire [1:0] _fpArb_io_out_req_bits_typeTagIn; // @[RocketTile.scala:247:25] wire [1:0] _fpArb_io_out_req_bits_typeTagOut; // @[RocketTile.scala:247:25] wire _fpArb_io_out_req_bits_fromint; // @[RocketTile.scala:247:25] wire _fpArb_io_out_req_bits_toint; // @[RocketTile.scala:247:25] wire _fpArb_io_out_req_bits_fastpipe; // @[RocketTile.scala:247:25] wire _fpArb_io_out_req_bits_div; // @[RocketTile.scala:247:25] wire _fpArb_io_out_req_bits_sqrt; // @[RocketTile.scala:247:25] wire _fpArb_io_out_req_bits_wflags; // @[RocketTile.scala:247:25] wire [2:0] _fpArb_io_out_req_bits_rm; // @[RocketTile.scala:247:25] wire [1:0] _fpArb_io_out_req_bits_typ; // @[RocketTile.scala:247:25] wire [64:0] _fpArb_io_out_req_bits_in1; // @[RocketTile.scala:247:25] wire [64:0] _fpArb_io_out_req_bits_in2; // @[RocketTile.scala:247:25] wire _fpuOpt_io_fcsr_flags_valid; // @[RocketTile.scala:242:62] wire [4:0] _fpuOpt_io_fcsr_flags_bits; // @[RocketTile.scala:242:62] wire [63:0] _fpuOpt_io_store_data; // @[RocketTile.scala:242:62] wire [63:0] _fpuOpt_io_toint_data; // @[RocketTile.scala:242:62] wire _fpuOpt_io_fcsr_rdy; // @[RocketTile.scala:242:62] wire _fpuOpt_io_nack_mem; // @[RocketTile.scala:242:62] wire _fpuOpt_io_illegal_rm; // @[RocketTile.scala:242:62] wire _fpuOpt_io_dec_wen; // @[RocketTile.scala:242:62] wire _fpuOpt_io_dec_ren1; // @[RocketTile.scala:242:62] wire _fpuOpt_io_dec_ren2; // @[RocketTile.scala:242:62] wire _fpuOpt_io_dec_ren3; // @[RocketTile.scala:242:62] wire _fpuOpt_io_sboard_set; // @[RocketTile.scala:242:62] wire _fpuOpt_io_sboard_clr; // @[RocketTile.scala:242:62] wire [4:0] _fpuOpt_io_sboard_clra; // @[RocketTile.scala:242:62] wire _fpuOpt_io_cp_req_ready; // @[RocketTile.scala:242:62] wire _fpuOpt_io_cp_resp_valid; // @[RocketTile.scala:242:62] wire [64:0] _fpuOpt_io_cp_resp_bits_data; // @[RocketTile.scala:242:62] wire _vector_unit_auto_atl_out_a_valid; // @[RocketTile.scala:117:65] wire [2:0] _vector_unit_auto_atl_out_a_bits_opcode; // @[RocketTile.scala:117:65] wire [2:0] _vector_unit_auto_atl_out_a_bits_param; // @[RocketTile.scala:117:65] wire [3:0] _vector_unit_auto_atl_out_a_bits_size; // @[RocketTile.scala:117:65] wire [4:0] _vector_unit_auto_atl_out_a_bits_source; // @[RocketTile.scala:117:65] wire [31:0] _vector_unit_auto_atl_out_a_bits_address; // @[RocketTile.scala:117:65] wire [7:0] _vector_unit_auto_atl_out_a_bits_mask; // @[RocketTile.scala:117:65] wire [63:0] _vector_unit_auto_atl_out_a_bits_data; // @[RocketTile.scala:117:65] wire _vector_unit_auto_atl_out_a_bits_corrupt; // @[RocketTile.scala:117:65] wire _vector_unit_auto_atl_out_d_ready; // @[RocketTile.scala:117:65] wire _vector_unit_io_core_ex_ready; // @[RocketTile.scala:117:65] wire _vector_unit_io_core_mem_block_mem; // @[RocketTile.scala:117:65] wire _vector_unit_io_core_mem_block_all; // @[RocketTile.scala:117:65] wire _vector_unit_io_core_wb_replay; // @[RocketTile.scala:117:65] wire _vector_unit_io_core_wb_retire; // @[RocketTile.scala:117:65] wire [31:0] _vector_unit_io_core_wb_inst; // @[RocketTile.scala:117:65] wire [39:0] _vector_unit_io_core_wb_pc; // @[RocketTile.scala:117:65] wire _vector_unit_io_core_wb_xcpt; // @[RocketTile.scala:117:65] wire [4:0] _vector_unit_io_core_wb_cause; // @[RocketTile.scala:117:65] wire [39:0] _vector_unit_io_core_wb_tval; // @[RocketTile.scala:117:65] wire _vector_unit_io_core_resp_valid; // @[RocketTile.scala:117:65] wire _vector_unit_io_core_resp_bits_fp; // @[RocketTile.scala:117:65] wire [1:0] _vector_unit_io_core_resp_bits_size; // @[RocketTile.scala:117:65] wire [4:0] _vector_unit_io_core_resp_bits_rd; // @[RocketTile.scala:117:65] wire [63:0] _vector_unit_io_core_resp_bits_data; // @[RocketTile.scala:117:65] wire _vector_unit_io_core_set_vstart_valid; // @[RocketTile.scala:117:65] wire [7:0] _vector_unit_io_core_set_vstart_bits; // @[RocketTile.scala:117:65] wire _vector_unit_io_core_set_vxsat; // @[RocketTile.scala:117:65] wire _vector_unit_io_core_set_vconfig_valid; // @[RocketTile.scala:117:65] wire [8:0] _vector_unit_io_core_set_vconfig_bits_vl; // @[RocketTile.scala:117:65] wire _vector_unit_io_core_set_vconfig_bits_vtype_vill; // @[RocketTile.scala:117:65] wire [54:0] _vector_unit_io_core_set_vconfig_bits_vtype_reserved; // @[RocketTile.scala:117:65] wire _vector_unit_io_core_set_vconfig_bits_vtype_vma; // @[RocketTile.scala:117:65] wire _vector_unit_io_core_set_vconfig_bits_vtype_vta; // @[RocketTile.scala:117:65] wire [2:0] _vector_unit_io_core_set_vconfig_bits_vtype_vsew; // @[RocketTile.scala:117:65] wire _vector_unit_io_core_set_vconfig_bits_vtype_vlmul_sign; // @[RocketTile.scala:117:65] wire [1:0] _vector_unit_io_core_set_vconfig_bits_vtype_vlmul_mag; // @[RocketTile.scala:117:65] wire _vector_unit_io_core_set_fflags_valid; // @[RocketTile.scala:117:65] wire [4:0] _vector_unit_io_core_set_fflags_bits; // @[RocketTile.scala:117:65] wire _vector_unit_io_core_trap_check_busy; // @[RocketTile.scala:117:65] wire _vector_unit_io_core_backend_busy; // @[RocketTile.scala:117:65] wire _vector_unit_io_tlb_req_valid; // @[RocketTile.scala:117:65] wire [39:0] _vector_unit_io_tlb_req_bits_vaddr; // @[RocketTile.scala:117:65] wire [1:0] _vector_unit_io_tlb_req_bits_size; // @[RocketTile.scala:117:65] wire [4:0] _vector_unit_io_tlb_req_bits_cmd; // @[RocketTile.scala:117:65] wire [1:0] _vector_unit_io_tlb_req_bits_prv; // @[RocketTile.scala:117:65] wire _vector_unit_io_dmem_req_valid; // @[RocketTile.scala:117:65] wire [39:0] _vector_unit_io_dmem_req_bits_addr; // @[RocketTile.scala:117:65] wire [7:0] _vector_unit_io_dmem_req_bits_tag; // @[RocketTile.scala:117:65] wire [4:0] _vector_unit_io_dmem_req_bits_cmd; // @[RocketTile.scala:117:65] wire [1:0] _vector_unit_io_dmem_req_bits_size; // @[RocketTile.scala:117:65] wire _vector_unit_io_dmem_req_bits_signed; // @[RocketTile.scala:117:65] wire [1:0] _vector_unit_io_dmem_req_bits_dprv; // @[RocketTile.scala:117:65] wire _vector_unit_io_dmem_req_bits_dv; // @[RocketTile.scala:117:65] wire _vector_unit_io_dmem_req_bits_phys; // @[RocketTile.scala:117:65] wire _vector_unit_io_dmem_req_bits_no_alloc; // @[RocketTile.scala:117:65] wire _vector_unit_io_dmem_req_bits_no_xcpt; // @[RocketTile.scala:117:65] wire [7:0] _vector_unit_io_dmem_req_bits_mask; // @[RocketTile.scala:117:65] wire [63:0] _vector_unit_io_dmem_s1_data_data; // @[RocketTile.scala:117:65] wire [7:0] _vector_unit_io_dmem_s1_data_mask; // @[RocketTile.scala:117:65] wire _vector_unit_io_fp_req_valid; // @[RocketTile.scala:117:65] wire _vector_unit_io_fp_req_bits_ren2; // @[RocketTile.scala:117:65] wire [1:0] _vector_unit_io_fp_req_bits_typeTagIn; // @[RocketTile.scala:117:65] wire [1:0] _vector_unit_io_fp_req_bits_typeTagOut; // @[RocketTile.scala:117:65] wire _vector_unit_io_fp_req_bits_fromint; // @[RocketTile.scala:117:65] wire _vector_unit_io_fp_req_bits_toint; // @[RocketTile.scala:117:65] wire _vector_unit_io_fp_req_bits_fastpipe; // @[RocketTile.scala:117:65] wire _vector_unit_io_fp_req_bits_div; // @[RocketTile.scala:117:65] wire _vector_unit_io_fp_req_bits_sqrt; // @[RocketTile.scala:117:65] wire _vector_unit_io_fp_req_bits_wflags; // @[RocketTile.scala:117:65] wire [2:0] _vector_unit_io_fp_req_bits_rm; // @[RocketTile.scala:117:65] wire [1:0] _vector_unit_io_fp_req_bits_typ; // @[RocketTile.scala:117:65] wire [64:0] _vector_unit_io_fp_req_bits_in1; // @[RocketTile.scala:117:65] wire [64:0] _vector_unit_io_fp_req_bits_in2; // @[RocketTile.scala:117:65] wire _frontend_auto_icache_master_out_a_valid; // @[Frontend.scala:393:28] wire [31:0] _frontend_auto_icache_master_out_a_bits_address; // @[Frontend.scala:393:28] wire _frontend_io_cpu_resp_valid; // @[Frontend.scala:393:28] wire _frontend_io_cpu_resp_bits_btb_taken; // @[Frontend.scala:393:28] wire _frontend_io_cpu_resp_bits_btb_bridx; // @[Frontend.scala:393:28] wire [4:0] _frontend_io_cpu_resp_bits_btb_entry; // @[Frontend.scala:393:28] wire [7:0] _frontend_io_cpu_resp_bits_btb_bht_history; // @[Frontend.scala:393:28] wire [39:0] _frontend_io_cpu_resp_bits_pc; // @[Frontend.scala:393:28] wire [31:0] _frontend_io_cpu_resp_bits_data; // @[Frontend.scala:393:28] wire _frontend_io_cpu_resp_bits_xcpt_pf_inst; // @[Frontend.scala:393:28] wire _frontend_io_cpu_resp_bits_xcpt_gf_inst; // @[Frontend.scala:393:28] wire _frontend_io_cpu_resp_bits_xcpt_ae_inst; // @[Frontend.scala:393:28] wire _frontend_io_cpu_resp_bits_replay; // @[Frontend.scala:393:28] wire _frontend_io_ptw_req_valid; // @[Frontend.scala:393:28] wire _frontend_io_ptw_req_bits_valid; // @[Frontend.scala:393:28] wire [26:0] _frontend_io_ptw_req_bits_bits_addr; // @[Frontend.scala:393:28] wire _frontend_io_ptw_req_bits_bits_need_gpa; // @[Frontend.scala:393:28] wire _dcache_auto_out_a_valid; // @[HellaCache.scala:278:43] wire [2:0] _dcache_auto_out_a_bits_opcode; // @[HellaCache.scala:278:43] wire [2:0] _dcache_auto_out_a_bits_param; // @[HellaCache.scala:278:43] wire [3:0] _dcache_auto_out_a_bits_size; // @[HellaCache.scala:278:43] wire _dcache_auto_out_a_bits_source; // @[HellaCache.scala:278:43] wire [31:0] _dcache_auto_out_a_bits_address; // @[HellaCache.scala:278:43] wire [7:0] _dcache_auto_out_a_bits_mask; // @[HellaCache.scala:278:43] wire [63:0] _dcache_auto_out_a_bits_data; // @[HellaCache.scala:278:43] wire _dcache_auto_out_b_ready; // @[HellaCache.scala:278:43] wire _dcache_auto_out_c_valid; // @[HellaCache.scala:278:43] wire [2:0] _dcache_auto_out_c_bits_opcode; // @[HellaCache.scala:278:43] wire [2:0] _dcache_auto_out_c_bits_param; // @[HellaCache.scala:278:43] wire [3:0] _dcache_auto_out_c_bits_size; // @[HellaCache.scala:278:43] wire _dcache_auto_out_c_bits_source; // @[HellaCache.scala:278:43] wire [31:0] _dcache_auto_out_c_bits_address; // @[HellaCache.scala:278:43] wire [63:0] _dcache_auto_out_c_bits_data; // @[HellaCache.scala:278:43] wire _dcache_auto_out_d_ready; // @[HellaCache.scala:278:43] wire _dcache_auto_out_e_valid; // @[HellaCache.scala:278:43] wire [2:0] _dcache_auto_out_e_bits_sink; // @[HellaCache.scala:278:43] wire _dcache_io_cpu_req_ready; // @[HellaCache.scala:278:43] wire _dcache_io_cpu_s2_nack; // @[HellaCache.scala:278:43] wire _dcache_io_cpu_resp_valid; // @[HellaCache.scala:278:43] wire [7:0] _dcache_io_cpu_resp_bits_tag; // @[HellaCache.scala:278:43] wire [1:0] _dcache_io_cpu_resp_bits_size; // @[HellaCache.scala:278:43] wire [63:0] _dcache_io_cpu_resp_bits_data; // @[HellaCache.scala:278:43] wire _dcache_io_cpu_resp_bits_replay; // @[HellaCache.scala:278:43] wire _dcache_io_cpu_resp_bits_has_data; // @[HellaCache.scala:278:43] wire [63:0] _dcache_io_cpu_resp_bits_data_word_bypass; // @[HellaCache.scala:278:43] wire [63:0] _dcache_io_cpu_resp_bits_data_raw; // @[HellaCache.scala:278:43] wire _dcache_io_cpu_replay_next; // @[HellaCache.scala:278:43] wire _dcache_io_cpu_s2_xcpt_ma_ld; // @[HellaCache.scala:278:43] wire _dcache_io_cpu_s2_xcpt_ma_st; // @[HellaCache.scala:278:43] wire _dcache_io_cpu_s2_xcpt_pf_ld; // @[HellaCache.scala:278:43] wire _dcache_io_cpu_s2_xcpt_pf_st; // @[HellaCache.scala:278:43] wire _dcache_io_cpu_s2_xcpt_ae_ld; // @[HellaCache.scala:278:43] wire _dcache_io_cpu_s2_xcpt_ae_st; // @[HellaCache.scala:278:43] wire _dcache_io_cpu_ordered; // @[HellaCache.scala:278:43] wire _dcache_io_cpu_store_pending; // @[HellaCache.scala:278:43] wire _dcache_io_cpu_perf_release; // @[HellaCache.scala:278:43] wire _dcache_io_cpu_perf_grant; // @[HellaCache.scala:278:43] wire _dcache_io_ptw_req_valid; // @[HellaCache.scala:278:43] wire [26:0] _dcache_io_ptw_req_bits_bits_addr; // @[HellaCache.scala:278:43] wire _dcache_io_ptw_req_bits_bits_need_gpa; // @[HellaCache.scala:278:43] wire _dcache_io_tlb_port_s1_resp_miss; // @[HellaCache.scala:278:43] wire [31:0] _dcache_io_tlb_port_s1_resp_paddr; // @[HellaCache.scala:278:43] wire _dcache_io_tlb_port_s1_resp_pf_ld; // @[HellaCache.scala:278:43] wire _dcache_io_tlb_port_s1_resp_pf_st; // @[HellaCache.scala:278:43] wire _dcache_io_tlb_port_s1_resp_ae_ld; // @[HellaCache.scala:278:43] wire _dcache_io_tlb_port_s1_resp_ae_st; // @[HellaCache.scala:278:43] wire _dcache_io_tlb_port_s1_resp_ma_ld; // @[HellaCache.scala:278:43] wire _dcache_io_tlb_port_s1_resp_ma_st; // @[HellaCache.scala:278:43] wire [4:0] _dcache_io_tlb_port_s1_resp_cmd; // @[HellaCache.scala:278:43] wire _intXbar_auto_anon_out_0; // @[HierarchicalElement.scala:57:37] wire _intXbar_auto_anon_out_1; // @[HierarchicalElement.scala:57:37] wire _intXbar_auto_anon_out_2; // @[HierarchicalElement.scala:57:37] wire _intXbar_auto_anon_out_3; // @[HierarchicalElement.scala:57:37] wire _intXbar_auto_anon_out_4; // @[HierarchicalElement.scala:57:37] wire _tlMasterXbar_auto_anon_in_2_a_ready; // @[HierarchicalElement.scala:55:42] wire _tlMasterXbar_auto_anon_in_2_d_valid; // @[HierarchicalElement.scala:55:42] wire [2:0] _tlMasterXbar_auto_anon_in_2_d_bits_opcode; // @[HierarchicalElement.scala:55:42] wire [1:0] _tlMasterXbar_auto_anon_in_2_d_bits_param; // @[HierarchicalElement.scala:55:42] wire [3:0] _tlMasterXbar_auto_anon_in_2_d_bits_size; // @[HierarchicalElement.scala:55:42] wire [4:0] _tlMasterXbar_auto_anon_in_2_d_bits_source; // @[HierarchicalElement.scala:55:42] wire [2:0] _tlMasterXbar_auto_anon_in_2_d_bits_sink; // @[HierarchicalElement.scala:55:42] wire _tlMasterXbar_auto_anon_in_2_d_bits_denied; // @[HierarchicalElement.scala:55:42] wire [63:0] _tlMasterXbar_auto_anon_in_2_d_bits_data; // @[HierarchicalElement.scala:55:42] wire _tlMasterXbar_auto_anon_in_2_d_bits_corrupt; // @[HierarchicalElement.scala:55:42] wire _tlMasterXbar_auto_anon_in_1_a_ready; // @[HierarchicalElement.scala:55:42] wire _tlMasterXbar_auto_anon_in_1_d_valid; // @[HierarchicalElement.scala:55:42] wire [2:0] _tlMasterXbar_auto_anon_in_1_d_bits_opcode; // @[HierarchicalElement.scala:55:42] wire [3:0] _tlMasterXbar_auto_anon_in_1_d_bits_size; // @[HierarchicalElement.scala:55:42] wire [63:0] _tlMasterXbar_auto_anon_in_1_d_bits_data; // @[HierarchicalElement.scala:55:42] wire _tlMasterXbar_auto_anon_in_1_d_bits_corrupt; // @[HierarchicalElement.scala:55:42] wire _tlMasterXbar_auto_anon_in_0_a_ready; // @[HierarchicalElement.scala:55:42] wire _tlMasterXbar_auto_anon_in_0_b_valid; // @[HierarchicalElement.scala:55:42] wire [1:0] _tlMasterXbar_auto_anon_in_0_b_bits_param; // @[HierarchicalElement.scala:55:42] wire [3:0] _tlMasterXbar_auto_anon_in_0_b_bits_size; // @[HierarchicalElement.scala:55:42] wire _tlMasterXbar_auto_anon_in_0_b_bits_source; // @[HierarchicalElement.scala:55:42] wire [31:0] _tlMasterXbar_auto_anon_in_0_b_bits_address; // @[HierarchicalElement.scala:55:42] wire _tlMasterXbar_auto_anon_in_0_c_ready; // @[HierarchicalElement.scala:55:42] wire _tlMasterXbar_auto_anon_in_0_d_valid; // @[HierarchicalElement.scala:55:42] wire [2:0] _tlMasterXbar_auto_anon_in_0_d_bits_opcode; // @[HierarchicalElement.scala:55:42] wire [1:0] _tlMasterXbar_auto_anon_in_0_d_bits_param; // @[HierarchicalElement.scala:55:42] wire [3:0] _tlMasterXbar_auto_anon_in_0_d_bits_size; // @[HierarchicalElement.scala:55:42] wire _tlMasterXbar_auto_anon_in_0_d_bits_source; // @[HierarchicalElement.scala:55:42] wire [2:0] _tlMasterXbar_auto_anon_in_0_d_bits_sink; // @[HierarchicalElement.scala:55:42] wire _tlMasterXbar_auto_anon_in_0_d_bits_denied; // @[HierarchicalElement.scala:55:42] wire [63:0] _tlMasterXbar_auto_anon_in_0_d_bits_data; // @[HierarchicalElement.scala:55:42] wire _tlMasterXbar_auto_anon_in_0_e_ready; // @[HierarchicalElement.scala:55:42] reg wfiNodeOut_0_REG; // @[Interrupts.scala:131:36] always @(posedge clock) begin // @[RocketTile.scala:141:7] if (reset) // @[RocketTile.scala:141:7] wfiNodeOut_0_REG <= 1'h0; // @[RocketTile.scala:141:7] else // @[RocketTile.scala:141:7] wfiNodeOut_0_REG <= _core_io_wfi; // @[RocketTile.scala:147:20] always @(posedge)

Generate the Verilog code corresponding to the following Chisel files. File INToRecFN.scala: /*============================================================================ This Chisel source file is part of a pre-release version of the HardFloat IEEE Floating-Point Arithmetic Package, by John R. Hauser (with some contributions from Yunsup Lee and Andrew Waterman, mainly concerning testing). Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of California. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions, and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions, and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the University nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. =============================================================================*/ package hardfloat import chisel3._ import consts._ class INToRecFN(intWidth: Int, expWidth: Int, sigWidth: Int) extends RawModule { override def desiredName = s"INToRecFN_i${intWidth}_e${expWidth}_s${sigWidth}" val io = IO(new Bundle { val signedIn = Input(Bool()) val in = Input(Bits(intWidth.W)) val roundingMode = Input(UInt(3.W)) val detectTininess = Input(UInt(1.W)) val out = Output(Bits((expWidth + sigWidth + 1).W)) val exceptionFlags = Output(Bits(5.W)) }) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val intAsRawFloat = rawFloatFromIN(io.signedIn, io.in); val roundAnyRawFNToRecFN = Module( new RoundAnyRawFNToRecFN( intAsRawFloat.expWidth, intWidth, expWidth, sigWidth, flRoundOpt_sigMSBitAlwaysZero | flRoundOpt_neverUnderflows )) roundAnyRawFNToRecFN.io.invalidExc := false.B roundAnyRawFNToRecFN.io.infiniteExc := false.B roundAnyRawFNToRecFN.io.in := intAsRawFloat roundAnyRawFNToRecFN.io.roundingMode := io.roundingMode roundAnyRawFNToRecFN.io.detectTininess := io.detectTininess io.out := roundAnyRawFNToRecFN.io.out io.exceptionFlags := roundAnyRawFNToRecFN.io.exceptionFlags } File primitives.scala: /*============================================================================ This Chisel source file is part of a pre-release version of the HardFloat IEEE Floating-Point Arithmetic Package, by John R. Hauser (with some contributions from Yunsup Lee and Andrew Waterman, mainly concerning testing). Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the University of California. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions, and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions, and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the University nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. =============================================================================*/ package hardfloat import chisel3._ import chisel3.util._ //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- object lowMask { def apply(in: UInt, topBound: BigInt, bottomBound: BigInt): UInt = { require(topBound != bottomBound) val numInVals = BigInt(1)<<in.getWidth if (topBound < bottomBound) { lowMask(~in, numInVals - 1 - topBound, numInVals - 1 - bottomBound) } else if (numInVals > 64 /* Empirical */) { // For simulation performance, we should avoid generating // exteremely wide shifters, so we divide and conquer. // Empirically, this does not impact synthesis QoR. val mid = numInVals / 2 val msb = in(in.getWidth - 1) val lsbs = in(in.getWidth - 2, 0) if (mid < topBound) { if (mid <= bottomBound) { Mux(msb, lowMask(lsbs, topBound - mid, bottomBound - mid), 0.U ) } else { Mux(msb, lowMask(lsbs, topBound - mid, 0) ## ((BigInt(1)<<(mid - bottomBound).toInt) - 1).U, lowMask(lsbs, mid, bottomBound) ) } } else { ~Mux(msb, 0.U, ~lowMask(lsbs, topBound, bottomBound)) } } else { val shift = (BigInt(-1)<<numInVals.toInt).S>>in Reverse( shift( (numInVals - 1 - bottomBound).toInt, (numInVals - topBound).toInt ) ) } } } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- object countLeadingZeros { def apply(in: UInt): UInt = PriorityEncoder(in.asBools.reverse) } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- object orReduceBy2 { def apply(in: UInt): UInt = { val reducedWidth = (in.getWidth + 1)>>1 val reducedVec = Wire(Vec(reducedWidth, Bool())) for (ix <- 0 until reducedWidth - 1) { reducedVec(ix) := in(ix * 2 + 1, ix * 2).orR } reducedVec(reducedWidth - 1) := in(in.getWidth - 1, (reducedWidth - 1) * 2).orR reducedVec.asUInt } } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- object orReduceBy4 { def apply(in: UInt): UInt = { val reducedWidth = (in.getWidth + 3)>>2 val reducedVec = Wire(Vec(reducedWidth, Bool())) for (ix <- 0 until reducedWidth - 1) { reducedVec(ix) := in(ix * 4 + 3, ix * 4).orR } reducedVec(reducedWidth - 1) := in(in.getWidth - 1, (reducedWidth - 1) * 4).orR reducedVec.asUInt } } File rawFloatFromIN.scala: /*============================================================================ This Chisel source file is part of a pre-release version of the HardFloat IEEE Floating-Point Arithmetic Package, by John R. Hauser (with some contributions from Yunsup Lee and Andrew Waterman, mainly concerning testing). Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the University of California. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions, and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions, and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the University nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. =============================================================================*/ package hardfloat import chisel3._ import chisel3.util._ object rawFloatFromIN { def apply(signedIn: Bool, in: Bits): RawFloat = { val expWidth = log2Up(in.getWidth) + 1 //*** CHANGE THIS; CAN BE VERY LARGE: val extIntWidth = 1<<(expWidth - 1) val sign = signedIn && in(in.getWidth - 1) val absIn = Mux(sign, -in.asUInt, in.asUInt) val extAbsIn = (0.U(extIntWidth.W) ## absIn)(extIntWidth - 1, 0) val adjustedNormDist = countLeadingZeros(extAbsIn) val sig = (extAbsIn<<adjustedNormDist)( extIntWidth - 1, extIntWidth - in.getWidth) val out = Wire(new RawFloat(expWidth, in.getWidth)) out.isNaN := false.B out.isInf := false.B out.isZero := ! sig(in.getWidth - 1) out.sign := sign out.sExp := (2.U(2.W) ## ~adjustedNormDist(expWidth - 2, 0)).zext out.sig := sig out } }

module INToRecFN_i1_e8_s24_15(); // @[INToRecFN.scala:43:7] wire [1:0] _intAsRawFloat_absIn_T = 2'h3; // @[rawFloatFromIN.scala:52:31] wire [2:0] _intAsRawFloat_extAbsIn_T = 3'h1; // @[rawFloatFromIN.scala:53:44] wire [2:0] _intAsRawFloat_sig_T = 3'h2; // @[rawFloatFromIN.scala:56:22] wire [2:0] _intAsRawFloat_out_sExp_T_2 = 3'h4; // @[rawFloatFromIN.scala:64:33] wire [3:0] intAsRawFloat_sExp = 4'h4; // @[rawFloatFromIN.scala:59:23, :64:72] wire [3:0] _intAsRawFloat_out_sExp_T_3 = 4'h4; // @[rawFloatFromIN.scala:59:23, :64:72] wire [1:0] intAsRawFloat_extAbsIn = 2'h1; // @[rawFloatFromIN.scala:53:53, :59:23, :65:20] wire [1:0] intAsRawFloat_sig = 2'h1; // @[rawFloatFromIN.scala:53:53, :59:23, :65:20] wire [4:0] io_exceptionFlags = 5'h0; // @[INToRecFN.scala:43:7, :46:16, :60:15] wire [32:0] io_out = 33'h80000000; // @[INToRecFN.scala:43:7, :46:16, :60:15] wire [2:0] io_roundingMode = 3'h0; // @[INToRecFN.scala:43:7, :46:16, :60:15] wire io_in = 1'h1; // @[Mux.scala:50:70] wire io_detectTininess = 1'h1; // @[Mux.scala:50:70] wire _intAsRawFloat_sign_T = 1'h1; // @[Mux.scala:50:70] wire _intAsRawFloat_absIn_T_1 = 1'h1; // @[Mux.scala:50:70] wire intAsRawFloat_absIn = 1'h1; // @[Mux.scala:50:70] wire _intAsRawFloat_adjustedNormDist_T = 1'h1; // @[Mux.scala:50:70] wire intAsRawFloat_adjustedNormDist = 1'h1; // @[Mux.scala:50:70] wire intAsRawFloat_sig_0 = 1'h1; // @[Mux.scala:50:70] wire _intAsRawFloat_out_isZero_T = 1'h1; // @[Mux.scala:50:70] wire _intAsRawFloat_out_sExp_T = 1'h1; // @[Mux.scala:50:70] wire io_signedIn = 1'h0; // @[INToRecFN.scala:43:7] wire intAsRawFloat_sign = 1'h0; // @[rawFloatFromIN.scala:51:29] wire _intAsRawFloat_adjustedNormDist_T_1 = 1'h0; // @[primitives.scala:91:52] wire intAsRawFloat_isNaN = 1'h0; // @[rawFloatFromIN.scala:59:23] wire intAsRawFloat_isInf = 1'h0; // @[rawFloatFromIN.scala:59:23] wire intAsRawFloat_isZero = 1'h0; // @[rawFloatFromIN.scala:59:23] wire intAsRawFloat_sign_0 = 1'h0; // @[rawFloatFromIN.scala:59:23] wire _intAsRawFloat_out_isZero_T_1 = 1'h0; // @[rawFloatFromIN.scala:62:23] wire _intAsRawFloat_out_sExp_T_1 = 1'h0; // @[rawFloatFromIN.scala:64:36] RoundAnyRawFNToRecFN_ie2_is1_oe8_os24_15 roundAnyRawFNToRecFN (); // @[INToRecFN.scala:60:15] endmodule

Generate the Verilog code corresponding to the following Chisel files. File ExecutionUnit.scala: package saturn.exu import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config._ import freechips.rocketchip.rocket._ import freechips.rocketchip.util._ import freechips.rocketchip.tile._ import saturn.common._ class ExecutionUnit(genFUs: Seq[FunctionalUnitFactory])(implicit p: Parameters) extends CoreModule()(p) with HasVectorParams { val fus = genFUs.map(gen => Module(gen.generate(p))) val pipe_fus: Seq[PipelinedFunctionalUnit] = fus.collect { case p: PipelinedFunctionalUnit => p } val iter_fus: Seq[IterativeFunctionalUnit] = fus.collect { case i: IterativeFunctionalUnit => i } val pipe_depth = (pipe_fus.map(_.depth) :+ 0).max val io = IO(new Bundle { val iss = Flipped(Decoupled(new ExecuteMicroOp)) val iter_hazards = Output(Vec(iter_fus.size, Valid(new PipeHazard(pipe_depth)))) val iter_write = Decoupled(new VectorWrite(dLen)) val pipe_write = Output(Valid(new VectorWrite(dLen))) val acc_write = Output(Valid(new VectorWrite(dLen))) val scalar_write = Decoupled(new ScalarWrite) val pipe_hazards = Output(Vec(pipe_depth, Valid(new PipeHazard(pipe_depth)))) val issue_pipe_latency = Output(UInt((log2Ceil(pipe_depth) + 1).W)) val shared_fp_req = Decoupled(new FPInput()) val shared_fp_resp = Flipped(Valid(new FPResult())) val set_vxsat = Output(Bool()) val set_fflags = Output(Valid(UInt(5.W))) val busy = Output(Bool()) }) val sharedFPUnits = fus.collect { case fp: HasSharedFPUIO => fp } val hasSharedFPUnits = sharedFPUnits.size > 0 io.shared_fp_req.valid := false.B io.shared_fp_req.bits := DontCare if (sharedFPUnits.size > 0) { val shared_fp_arb = Module(new Arbiter(new FPInput, sharedFPUnits.size)) for ((u, i) <- sharedFPUnits.zipWithIndex) { val otherUnits = sharedFPUnits.zipWithIndex.filter(_._2 != i).map(_._1) val other_busy = otherUnits.map(_.io_fp_active).orR u.io_fp_req.ready := shared_fp_arb.io.in(i).ready && !other_busy shared_fp_arb.io.in(i).valid := u.io_fp_req.valid && !other_busy shared_fp_arb.io.in(i).bits := u.io_fp_req.bits u.io_fp_resp := io.shared_fp_resp } io.shared_fp_req <> shared_fp_arb.io.out } val pipe_stall = WireInit(false.B) fus.foreach { fu => fu.io.iss.op := io.iss.bits fu.io.iss.valid := io.iss.valid && !pipe_stall } val pipe_write_hazard = WireInit(false.B) val readies = fus.map(_.io.iss.ready) io.iss.ready := readies.orR && !pipe_write_hazard && !pipe_stall when (io.iss.valid) { assert(PopCount(readies) <= 1.U) } io.issue_pipe_latency := Mux1H(pipe_fus.map(_.io.iss.ready), pipe_fus.map(_.depth.U)) val pipe_write = WireInit(false.B) io.pipe_write.valid := false.B io.pipe_write.bits := DontCare io.iter_write.valid := false.B io.iter_write.bits := DontCare io.acc_write.valid := false.B io.acc_write.bits := DontCare io.busy := false.B io.set_vxsat := fus.map(_.io.set_vxsat).orR io.set_fflags.valid := fus.map(_.io.set_fflags.valid).orR io.set_fflags.bits := fus.map(f => Mux(f.io.set_fflags.valid, f.io.set_fflags.bits, 0.U)).reduce(_|_) val scalar_write_arb = Module(new Arbiter(new ScalarWrite, fus.size)) scalar_write_arb.io.in.zip(fus.map(_.io.scalar_write)).foreach { case (l, r) => l <> r } io.scalar_write <> scalar_write_arb.io.out if (pipe_fus.size > 0) { val pipe_iss_depth = Mux1H(pipe_fus.map(_.io.iss.ready), pipe_fus.map(_.depth.U)) val pipe_valids = Seq.fill(pipe_depth)(RegInit(false.B)) val pipe_sels = Seq.fill(pipe_depth)(Reg(UInt(pipe_fus.size.W))) val pipe_bits = Seq.fill(pipe_depth)(Reg(new ExecuteMicroOp)) val pipe_latencies = Seq.fill(pipe_depth)(Reg(UInt(log2Ceil(pipe_depth).W))) pipe_stall := Mux1H(pipe_sels.head, pipe_fus.map(_.io.pipe0_stall)) pipe_write_hazard := (0 until pipe_depth).map { i => pipe_valids(i) && pipe_latencies(i) === pipe_iss_depth }.orR val pipe_iss = io.iss.fire && pipe_fus.map(_.io.iss.ready).orR when (!pipe_stall) { pipe_valids.head := pipe_iss when (pipe_iss) { pipe_bits.head := io.iss.bits pipe_latencies.head := pipe_iss_depth - 1.U pipe_sels.head := VecInit(pipe_fus.map(_.io.iss.ready)).asUInt } } for (i <- 1 until pipe_depth) { val fire = pipe_valids(i-1) && pipe_latencies(i-1) =/= 0.U && !((i == 1).B && pipe_stall) pipe_valids(i) := fire when (fire) { pipe_bits(i) := pipe_bits(i-1) pipe_latencies(i) := pipe_latencies(i-1) - 1.U pipe_sels(i) := pipe_sels(i-1) } } for ((fu, j) <- pipe_fus.zipWithIndex) { for (i <- 0 until fu.depth) { fu.io.pipe(i).valid := pipe_valids(i) && pipe_sels(i)(j) fu.io.pipe(i).bits := Mux(pipe_valids(i) && pipe_sels(i)(j), pipe_bits(i), 0.U.asTypeOf(new ExecuteMicroOp)) } } val write_sel = pipe_valids.zip(pipe_latencies).map { case (v,l) => v && l === 0.U } val fu_sel = Mux1H(write_sel, pipe_sels) pipe_write := write_sel.orR when (write_sel.orR) { val acc = Mux1H(write_sel, pipe_bits.map(_.acc)) val tail = Mux1H(write_sel, pipe_bits.map(_.tail)) io.pipe_write.valid := Mux1H(fu_sel, pipe_fus.map(_.io.write.valid)) && (!acc || tail) io.pipe_write.bits := Mux1H(fu_sel, pipe_fus.map(_.io.write.bits)) io.acc_write.valid := acc && !tail io.acc_write.bits := Mux1H(fu_sel, pipe_fus.map(_.io.write.bits)) } when (pipe_valids.orR) { io.busy := true.B } for (i <- 0 until pipe_depth) { io.pipe_hazards(i).valid := pipe_valids(i) io.pipe_hazards(i).bits.eg := pipe_bits(i).wvd_eg when (pipe_latencies(i) === 0.U) { // hack to deal with compress unit io.pipe_hazards(i).bits.eg := Mux1H(pipe_sels(i), pipe_fus.map(_.io.write.bits.eg)) } io.pipe_hazards(i).bits.latency := pipe_latencies(i) } } if (iter_fus.size > 0) { val iter_write_arb = Module(new Arbiter(new VectorWrite(dLen), iter_fus.size)) iter_write_arb.io.in.zip(iter_fus.map(_.io.write)).foreach { case (l,r) => l <> r } iter_write_arb.io.out.ready := !pipe_write && io.iter_write.ready val acc = Mux1H(iter_write_arb.io.in.map(_.fire), iter_fus.map(_.io.acc)) val tail = Mux1H(iter_write_arb.io.in.map(_.fire), iter_fus.map(_.io.tail)) io.iter_write.valid := iter_write_arb.io.out.valid && (!acc || tail) && !pipe_write io.iter_write.bits.eg := iter_write_arb.io.out.bits.eg io.iter_write.bits.mask := iter_write_arb.io.out.bits.mask io.iter_write.bits.data := iter_write_arb.io.out.bits.data when (!pipe_write) { io.acc_write.valid := iter_write_arb.io.out.valid && acc io.acc_write.bits.eg := Mux1H(iter_write_arb.io.in.map(_.fire), iter_fus.map(_.io.write.bits.eg)) io.acc_write.bits.data := Mux1H(iter_write_arb.io.in.map(_.fire), iter_fus.map(_.io.write.bits.data)) io.acc_write.bits.mask := Mux1H(iter_write_arb.io.in.map(_.fire), iter_fus.map(_.io.write.bits.mask)) } when (iter_fus.map(_.io.busy).orR) { io.busy := true.B } for (i <- 0 until iter_fus.size) { io.iter_hazards(i) := iter_fus(i).io.hazard } } } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /** Like Vec.apply(idx), but tolerates indices of mismatched width */ def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /** Any Data subtype that has a Bool member named valid. */ type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /** converts from camel case to to underscores, also removing all spaces */ def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /** converts spaces or underscores to hyphens, also lowering case */ def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y | (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y || y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /** Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation */ def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag }

module ExecutionUnit( // @[ExecutionUnit.scala:11:7] input clock, // @[ExecutionUnit.scala:11:7] input reset, // @[ExecutionUnit.scala:11:7] output io_iss_ready, // @[ExecutionUnit.scala:19:14] input io_iss_valid, // @[ExecutionUnit.scala:19:14] input [5:0] io_iss_bits_eidx, // @[ExecutionUnit.scala:19:14] input [6:0] io_iss_bits_vl, // @[ExecutionUnit.scala:19:14] input [63:0] io_iss_bits_rvs1_data, // @[ExecutionUnit.scala:19:14] input [63:0] io_iss_bits_rvs2_data, // @[ExecutionUnit.scala:19:14] input [63:0] io_iss_bits_rvm_data, // @[ExecutionUnit.scala:19:14] input [63:0] io_iss_bits_rvs1_elem, // @[ExecutionUnit.scala:19:14] input [63:0] io_iss_bits_rvs2_elem, // @[ExecutionUnit.scala:19:14] input [63:0] io_iss_bits_rvd_elem, // @[ExecutionUnit.scala:19:14] input [1:0] io_iss_bits_rvs1_eew, // @[ExecutionUnit.scala:19:14] input [1:0] io_iss_bits_rvs2_eew, // @[ExecutionUnit.scala:19:14] input [1:0] io_iss_bits_rvd_eew, // @[ExecutionUnit.scala:19:14] input [1:0] io_iss_bits_vd_eew, // @[ExecutionUnit.scala:19:14] input [7:0] io_iss_bits_rmask, // @[ExecutionUnit.scala:19:14] input [7:0] io_iss_bits_wmask, // @[ExecutionUnit.scala:19:14] input [63:0] io_iss_bits_full_tail_mask, // @[ExecutionUnit.scala:19:14] input [4:0] io_iss_bits_wvd_eg, // @[ExecutionUnit.scala:19:14] input [2:0] io_iss_bits_funct3, // @[ExecutionUnit.scala:19:14] input [5:0] io_iss_bits_funct6, // @[ExecutionUnit.scala:19:14] input [4:0] io_iss_bits_rs1, // @[ExecutionUnit.scala:19:14] input [4:0] io_iss_bits_rs2, // @[ExecutionUnit.scala:19:14] input [4:0] io_iss_bits_rd, // @[ExecutionUnit.scala:19:14] input io_iss_bits_vm, // @[ExecutionUnit.scala:19:14] input io_iss_bits_head, // @[ExecutionUnit.scala:19:14] input io_iss_bits_tail, // @[ExecutionUnit.scala:19:14] input io_iss_bits_acc, // @[ExecutionUnit.scala:19:14] input [2:0] io_iss_bits_rm, // @[ExecutionUnit.scala:19:14] output io_iter_hazards_0_valid, // @[ExecutionUnit.scala:19:14] output [4:0] io_iter_hazards_0_bits_eg, // @[ExecutionUnit.scala:19:14] output io_iter_hazards_1_valid, // @[ExecutionUnit.scala:19:14] output [4:0] io_iter_hazards_1_bits_eg, // @[ExecutionUnit.scala:19:14] input io_iter_write_ready, // @[ExecutionUnit.scala:19:14] output io_iter_write_valid, // @[ExecutionUnit.scala:19:14] output [4:0] io_iter_write_bits_eg, // @[ExecutionUnit.scala:19:14] output [63:0] io_iter_write_bits_data, // @[ExecutionUnit.scala:19:14] output [63:0] io_iter_write_bits_mask, // @[ExecutionUnit.scala:19:14] output io_pipe_write_valid, // @[ExecutionUnit.scala:19:14] output [4:0] io_pipe_write_bits_eg, // @[ExecutionUnit.scala:19:14] output [63:0] io_pipe_write_bits_data, // @[ExecutionUnit.scala:19:14] output [63:0] io_pipe_write_bits_mask, // @[ExecutionUnit.scala:19:14] output io_acc_write_valid, // @[ExecutionUnit.scala:19:14] output [63:0] io_acc_write_bits_data, // @[ExecutionUnit.scala:19:14] output [63:0] io_acc_write_bits_mask, // @[ExecutionUnit.scala:19:14] input io_scalar_write_ready, // @[ExecutionUnit.scala:19:14] output io_scalar_write_valid, // @[ExecutionUnit.scala:19:14] output [63:0] io_scalar_write_bits_data, // @[ExecutionUnit.scala:19:14] output io_scalar_write_bits_fp, // @[ExecutionUnit.scala:19:14] output [1:0] io_scalar_write_bits_size, // @[ExecutionUnit.scala:19:14] output [4:0] io_scalar_write_bits_rd, // @[ExecutionUnit.scala:19:14] output io_pipe_hazards_0_valid, // @[ExecutionUnit.scala:19:14] output [4:0] io_pipe_hazards_0_bits_eg, // @[ExecutionUnit.scala:19:14] output io_pipe_hazards_1_valid, // @[ExecutionUnit.scala:19:14] output [4:0] io_pipe_hazards_1_bits_eg, // @[ExecutionUnit.scala:19:14] output io_pipe_hazards_2_valid, // @[ExecutionUnit.scala:19:14] output [4:0] io_pipe_hazards_2_bits_eg, // @[ExecutionUnit.scala:19:14] output io_pipe_hazards_3_valid, // @[ExecutionUnit.scala:19:14] output [4:0] io_pipe_hazards_3_bits_eg, // @[ExecutionUnit.scala:19:14] input io_shared_fp_req_ready, // @[ExecutionUnit.scala:19:14] output io_shared_fp_req_valid, // @[ExecutionUnit.scala:19:14] output io_shared_fp_req_bits_ren2, // @[ExecutionUnit.scala:19:14] output io_shared_fp_req_bits_ren3, // @[ExecutionUnit.scala:19:14] output io_shared_fp_req_bits_swap23, // @[ExecutionUnit.scala:19:14] output [1:0] io_shared_fp_req_bits_typeTagIn, // @[ExecutionUnit.scala:19:14] output [1:0] io_shared_fp_req_bits_typeTagOut, // @[ExecutionUnit.scala:19:14] output io_shared_fp_req_bits_fromint, // @[ExecutionUnit.scala:19:14] output io_shared_fp_req_bits_toint, // @[ExecutionUnit.scala:19:14] output io_shared_fp_req_bits_fastpipe, // @[ExecutionUnit.scala:19:14] output io_shared_fp_req_bits_fma, // @[ExecutionUnit.scala:19:14] output io_shared_fp_req_bits_div, // @[ExecutionUnit.scala:19:14] output io_shared_fp_req_bits_sqrt, // @[ExecutionUnit.scala:19:14] output io_shared_fp_req_bits_wflags, // @[ExecutionUnit.scala:19:14] output [2:0] io_shared_fp_req_bits_rm, // @[ExecutionUnit.scala:19:14] output [1:0] io_shared_fp_req_bits_fmaCmd, // @[ExecutionUnit.scala:19:14] output [1:0] io_shared_fp_req_bits_typ, // @[ExecutionUnit.scala:19:14] output [64:0] io_shared_fp_req_bits_in1, // @[ExecutionUnit.scala:19:14] output [64:0] io_shared_fp_req_bits_in2, // @[ExecutionUnit.scala:19:14] output [64:0] io_shared_fp_req_bits_in3, // @[ExecutionUnit.scala:19:14] input io_shared_fp_resp_valid, // @[ExecutionUnit.scala:19:14] input [64:0] io_shared_fp_resp_bits_data, // @[ExecutionUnit.scala:19:14] output io_set_vxsat, // @[ExecutionUnit.scala:19:14] output io_busy // @[ExecutionUnit.scala:19:14] ); wire pipe_write_hazard; // @[package.scala:81:59] wire _pipe_stall_T_13; // @[Mux.scala:30:73] wire _iter_write_arb_io_in_0_ready; // @[ExecutionUnit.scala:152:32] wire _iter_write_arb_io_in_1_ready; // @[ExecutionUnit.scala:152:32] wire _iter_write_arb_io_out_valid; // @[ExecutionUnit.scala:152:32] wire _scalar_write_arb_io_in_4_ready; // @[ExecutionUnit.scala:84:32] wire _shared_fp_arb_io_in_0_ready; // @[ExecutionUnit.scala:44:31] wire _shared_fp_arb_io_in_1_ready; // @[ExecutionUnit.scala:44:31] wire _fus_8_io_iss_ready; // @[ExecutionUnit.scala:12:37] wire _fus_8_io_write_valid; // @[ExecutionUnit.scala:12:37] wire [4:0] _fus_8_io_write_bits_eg; // @[ExecutionUnit.scala:12:37] wire [63:0] _fus_8_io_write_bits_data; // @[ExecutionUnit.scala:12:37] wire [63:0] _fus_8_io_write_bits_mask; // @[ExecutionUnit.scala:12:37] wire _fus_8_io_acc; // @[ExecutionUnit.scala:12:37] wire _fus_8_io_tail; // @[ExecutionUnit.scala:12:37] wire _fus_8_io_busy; // @[ExecutionUnit.scala:12:37] wire _fus_8_io_fp_req_valid; // @[ExecutionUnit.scala:12:37] wire _fus_8_io_fp_req_bits_ren2; // @[ExecutionUnit.scala:12:37] wire [1:0] _fus_8_io_fp_req_bits_typeTagIn; // @[ExecutionUnit.scala:12:37] wire [1:0] _fus_8_io_fp_req_bits_typeTagOut; // @[ExecutionUnit.scala:12:37] wire _fus_8_io_fp_req_bits_fromint; // @[ExecutionUnit.scala:12:37] wire _fus_8_io_fp_req_bits_toint; // @[ExecutionUnit.scala:12:37] wire _fus_8_io_fp_req_bits_fastpipe; // @[ExecutionUnit.scala:12:37] wire _fus_8_io_fp_req_bits_div; // @[ExecutionUnit.scala:12:37] wire _fus_8_io_fp_req_bits_sqrt; // @[ExecutionUnit.scala:12:37] wire _fus_8_io_fp_req_bits_wflags; // @[ExecutionUnit.scala:12:37] wire [2:0] _fus_8_io_fp_req_bits_rm; // @[ExecutionUnit.scala:12:37] wire [1:0] _fus_8_io_fp_req_bits_typ; // @[ExecutionUnit.scala:12:37] wire [64:0] _fus_8_io_fp_req_bits_in1; // @[ExecutionUnit.scala:12:37] wire [64:0] _fus_8_io_fp_req_bits_in2; // @[ExecutionUnit.scala:12:37] wire _fus_8_io_fp_active; // @[ExecutionUnit.scala:12:37] wire _fus_7_io_iss_ready; // @[ExecutionUnit.scala:12:37] wire _fus_7_io_write_valid; // @[ExecutionUnit.scala:12:37] wire [4:0] _fus_7_io_write_bits_eg; // @[ExecutionUnit.scala:12:37] wire [63:0] _fus_7_io_write_bits_data; // @[ExecutionUnit.scala:12:37] wire [63:0] _fus_7_io_write_bits_mask; // @[ExecutionUnit.scala:12:37] wire _fus_7_io_pipe0_stall; // @[ExecutionUnit.scala:12:37] wire _fus_7_io_fp_req_valid; // @[ExecutionUnit.scala:12:37] wire _fus_7_io_fp_req_bits_ren3; // @[ExecutionUnit.scala:12:37] wire _fus_7_io_fp_req_bits_swap23; // @[ExecutionUnit.scala:12:37] wire [1:0] _fus_7_io_fp_req_bits_typeTagIn; // @[ExecutionUnit.scala:12:37] wire [1:0] _fus_7_io_fp_req_bits_typeTagOut; // @[ExecutionUnit.scala:12:37] wire [2:0] _fus_7_io_fp_req_bits_rm; // @[ExecutionUnit.scala:12:37] wire [1:0] _fus_7_io_fp_req_bits_fmaCmd; // @[ExecutionUnit.scala:12:37] wire [64:0] _fus_7_io_fp_req_bits_in1; // @[ExecutionUnit.scala:12:37] wire [64:0] _fus_7_io_fp_req_bits_in2; // @[ExecutionUnit.scala:12:37] wire [64:0] _fus_7_io_fp_req_bits_in3; // @[ExecutionUnit.scala:12:37] wire _fus_7_io_fp_active; // @[ExecutionUnit.scala:12:37] wire _fus_6_io_iss_ready; // @[ExecutionUnit.scala:12:37] wire _fus_6_io_set_vxsat; // @[ExecutionUnit.scala:12:37] wire _fus_6_io_write_valid; // @[ExecutionUnit.scala:12:37] wire [4:0] _fus_6_io_write_bits_eg; // @[ExecutionUnit.scala:12:37] wire [63:0] _fus_6_io_write_bits_data; // @[ExecutionUnit.scala:12:37] wire [63:0] _fus_6_io_write_bits_mask; // @[ExecutionUnit.scala:12:37] wire _fus_5_io_iss_ready; // @[ExecutionUnit.scala:12:37] wire _fus_5_io_write_valid; // @[ExecutionUnit.scala:12:37] wire [4:0] _fus_5_io_write_bits_eg; // @[ExecutionUnit.scala:12:37] wire [63:0] _fus_5_io_write_bits_data; // @[ExecutionUnit.scala:12:37] wire [63:0] _fus_5_io_write_bits_mask; // @[ExecutionUnit.scala:12:37] wire _fus_4_io_iss_ready; // @[ExecutionUnit.scala:12:37] wire _fus_4_io_scalar_write_valid; // @[ExecutionUnit.scala:12:37] wire [63:0] _fus_4_io_scalar_write_bits_data; // @[ExecutionUnit.scala:12:37] wire _fus_4_io_scalar_write_bits_fp; // @[ExecutionUnit.scala:12:37] wire [1:0] _fus_4_io_scalar_write_bits_size; // @[ExecutionUnit.scala:12:37] wire [4:0] _fus_4_io_scalar_write_bits_rd; // @[ExecutionUnit.scala:12:37] wire _fus_4_io_write_valid; // @[ExecutionUnit.scala:12:37] wire [4:0] _fus_4_io_write_bits_eg; // @[ExecutionUnit.scala:12:37] wire [63:0] _fus_4_io_write_bits_data; // @[ExecutionUnit.scala:12:37] wire [63:0] _fus_4_io_write_bits_mask; // @[ExecutionUnit.scala:12:37] wire _fus_3_io_iss_ready; // @[ExecutionUnit.scala:12:37] wire _fus_3_io_write_valid; // @[ExecutionUnit.scala:12:37] wire [4:0] _fus_3_io_write_bits_eg; // @[ExecutionUnit.scala:12:37] wire [63:0] _fus_3_io_write_bits_data; // @[ExecutionUnit.scala:12:37] wire [63:0] _fus_3_io_write_bits_mask; // @[ExecutionUnit.scala:12:37] wire _fus_3_io_busy; // @[ExecutionUnit.scala:12:37] wire _fus_2_io_iss_ready; // @[ExecutionUnit.scala:12:37] wire _fus_2_io_write_valid; // @[ExecutionUnit.scala:12:37] wire [4:0] _fus_2_io_write_bits_eg; // @[ExecutionUnit.scala:12:37] wire [63:0] _fus_2_io_write_bits_data; // @[ExecutionUnit.scala:12:37] wire [63:0] _fus_2_io_write_bits_mask; // @[ExecutionUnit.scala:12:37] wire _fus_1_io_iss_ready; // @[ExecutionUnit.scala:12:37] wire _fus_1_io_set_vxsat; // @[ExecutionUnit.scala:12:37] wire _fus_1_io_write_valid; // @[ExecutionUnit.scala:12:37] wire [4:0] _fus_1_io_write_bits_eg; // @[ExecutionUnit.scala:12:37] wire [63:0] _fus_1_io_write_bits_data; // @[ExecutionUnit.scala:12:37] wire [63:0] _fus_1_io_write_bits_mask; // @[ExecutionUnit.scala:12:37] wire _fus_0_io_iss_ready; // @[ExecutionUnit.scala:12:37] wire _fus_0_io_set_vxsat; // @[ExecutionUnit.scala:12:37] wire _fus_0_io_write_valid; // @[ExecutionUnit.scala:12:37] wire [4:0] _fus_0_io_write_bits_eg; // @[ExecutionUnit.scala:12:37] wire [63:0] _fus_0_io_write_bits_data; // @[ExecutionUnit.scala:12:37] wire [63:0] _fus_0_io_write_bits_mask; // @[ExecutionUnit.scala:12:37] wire _pipe_iss_T_1 = _fus_0_io_iss_ready | _fus_1_io_iss_ready; // @[ExecutionUnit.scala:12:37] wire io_iss_ready_0 = (_pipe_iss_T_1 | _fus_2_io_iss_ready | _fus_3_io_iss_ready | _fus_4_io_iss_ready | _fus_5_io_iss_ready | _fus_6_io_iss_ready | _fus_7_io_iss_ready | _fus_8_io_iss_ready) & ~pipe_write_hazard & ~_pipe_stall_T_13; // @[Mux.scala:30:73]

Generate the Verilog code corresponding to the following Chisel files. File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /** Like Vec.apply(idx), but tolerates indices of mismatched width */ def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /** Any Data subtype that has a Bool member named valid. */ type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /** converts from camel case to to underscores, also removing all spaces */ def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /** converts spaces or underscores to hyphens, also lowering case */ def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y | (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y || y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /** Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation */ def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag }

module OptimizationBarrier_TLBEntryData( // @[package.scala:267:30] input clock, // @[package.scala:267:30] input reset, // @[package.scala:267:30] input [19:0] io_x_ppn, // @[package.scala:268:18] input io_x_u, // @[package.scala:268:18] input io_x_g, // @[package.scala:268:18] input io_x_ae_ptw, // @[package.scala:268:18] input io_x_ae_final, // @[package.scala:268:18] input io_x_ae_stage2, // @[package.scala:268:18] input io_x_pf, // @[package.scala:268:18] input io_x_gf, // @[package.scala:268:18] input io_x_sw, // @[package.scala:268:18] input io_x_sx, // @[package.scala:268:18] input io_x_sr, // @[package.scala:268:18] input io_x_hw, // @[package.scala:268:18] input io_x_hx, // @[package.scala:268:18] input io_x_hr, // @[package.scala:268:18] input io_x_pw, // @[package.scala:268:18] input io_x_px, // @[package.scala:268:18] input io_x_pr, // @[package.scala:268:18] input io_x_ppp, // @[package.scala:268:18] input io_x_pal, // @[package.scala:268:18] input io_x_paa, // @[package.scala:268:18] input io_x_eff, // @[package.scala:268:18] input io_x_c, // @[package.scala:268:18] input io_x_fragmented_superpage, // @[package.scala:268:18] output [19:0] io_y_ppn // @[package.scala:268:18] ); wire [19:0] io_x_ppn_0 = io_x_ppn; // @[package.scala:267:30] wire io_x_u_0 = io_x_u; // @[package.scala:267:30] wire io_x_g_0 = io_x_g; // @[package.scala:267:30] wire io_x_ae_ptw_0 = io_x_ae_ptw; // @[package.scala:267:30] wire io_x_ae_final_0 = io_x_ae_final; // @[package.scala:267:30] wire io_x_ae_stage2_0 = io_x_ae_stage2; // @[package.scala:267:30] wire io_x_pf_0 = io_x_pf; // @[package.scala:267:30] wire io_x_gf_0 = io_x_gf; // @[package.scala:267:30] wire io_x_sw_0 = io_x_sw; // @[package.scala:267:30] wire io_x_sx_0 = io_x_sx; // @[package.scala:267:30] wire io_x_sr_0 = io_x_sr; // @[package.scala:267:30] wire io_x_hw_0 = io_x_hw; // @[package.scala:267:30] wire io_x_hx_0 = io_x_hx; // @[package.scala:267:30] wire io_x_hr_0 = io_x_hr; // @[package.scala:267:30] wire io_x_pw_0 = io_x_pw; // @[package.scala:267:30] wire io_x_px_0 = io_x_px; // @[package.scala:267:30] wire io_x_pr_0 = io_x_pr; // @[package.scala:267:30] wire io_x_ppp_0 = io_x_ppp; // @[package.scala:267:30] wire io_x_pal_0 = io_x_pal; // @[package.scala:267:30] wire io_x_paa_0 = io_x_paa; // @[package.scala:267:30] wire io_x_eff_0 = io_x_eff; // @[package.scala:267:30] wire io_x_c_0 = io_x_c; // @[package.scala:267:30] wire io_x_fragmented_superpage_0 = io_x_fragmented_superpage; // @[package.scala:267:30] wire [19:0] io_y_ppn_0 = io_x_ppn_0; // @[package.scala:267:30] wire io_y_u = io_x_u_0; // @[package.scala:267:30] wire io_y_g = io_x_g_0; // @[package.scala:267:30] wire io_y_ae_ptw = io_x_ae_ptw_0; // @[package.scala:267:30] wire io_y_ae_final = io_x_ae_final_0; // @[package.scala:267:30] wire io_y_ae_stage2 = io_x_ae_stage2_0; // @[package.scala:267:30] wire io_y_pf = io_x_pf_0; // @[package.scala:267:30] wire io_y_gf = io_x_gf_0; // @[package.scala:267:30] wire io_y_sw = io_x_sw_0; // @[package.scala:267:30] wire io_y_sx = io_x_sx_0; // @[package.scala:267:30] wire io_y_sr = io_x_sr_0; // @[package.scala:267:30] wire io_y_hw = io_x_hw_0; // @[package.scala:267:30] wire io_y_hx = io_x_hx_0; // @[package.scala:267:30] wire io_y_hr = io_x_hr_0; // @[package.scala:267:30] wire io_y_pw = io_x_pw_0; // @[package.scala:267:30] wire io_y_px = io_x_px_0; // @[package.scala:267:30] wire io_y_pr = io_x_pr_0; // @[package.scala:267:30] wire io_y_ppp = io_x_ppp_0; // @[package.scala:267:30] wire io_y_pal = io_x_pal_0; // @[package.scala:267:30] wire io_y_paa = io_x_paa_0; // @[package.scala:267:30] wire io_y_eff = io_x_eff_0; // @[package.scala:267:30] wire io_y_c = io_x_c_0; // @[package.scala:267:30] wire io_y_fragmented_superpage = io_x_fragmented_superpage_0; // @[package.scala:267:30] assign io_y_ppn = io_y_ppn_0; // @[package.scala:267:30] endmodule

Generate the Verilog code corresponding to the following Chisel files. File Tile.scala: // See README.md for license details. package gemmini import chisel3._ import chisel3.util._ import Util._ /** * A Tile is a purely combinational 2D array of passThrough PEs. * a, b, s, and in_propag are broadcast across the entire array and are passed through to the Tile's outputs * @param width The data width of each PE in bits * @param rows Number of PEs on each row * @param columns Number of PEs on each column */ class Tile[T <: Data](inputType: T, outputType: T, accType: T, df: Dataflow.Value, tree_reduction: Boolean, max_simultaneous_matmuls: Int, val rows: Int, val columns: Int)(implicit ev: Arithmetic[T]) extends Module { val io = IO(new Bundle { val in_a = Input(Vec(rows, inputType)) val in_b = Input(Vec(columns, outputType)) // This is the output of the tile next to it val in_d = Input(Vec(columns, outputType)) val in_control = Input(Vec(columns, new PEControl(accType))) val in_id = Input(Vec(columns, UInt(log2Up(max_simultaneous_matmuls).W))) val in_last = Input(Vec(columns, Bool())) val out_a = Output(Vec(rows, inputType)) val out_c = Output(Vec(columns, outputType)) val out_b = Output(Vec(columns, outputType)) val out_control = Output(Vec(columns, new PEControl(accType))) val out_id = Output(Vec(columns, UInt(log2Up(max_simultaneous_matmuls).W))) val out_last = Output(Vec(columns, Bool())) val in_valid = Input(Vec(columns, Bool())) val out_valid = Output(Vec(columns, Bool())) val bad_dataflow = Output(Bool()) }) import ev._ val tile = Seq.fill(rows, columns)(Module(new PE(inputType, outputType, accType, df, max_simultaneous_matmuls))) val tileT = tile.transpose // TODO: abstract hori/vert broadcast, all these connections look the same // Broadcast 'a' horizontally across the Tile for (r <- 0 until rows) { tile(r).foldLeft(io.in_a(r)) { case (in_a, pe) => pe.io.in_a := in_a pe.io.out_a } } // Broadcast 'b' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_b(c)) { case (in_b, pe) => pe.io.in_b := (if (tree_reduction) in_b.zero else in_b) pe.io.out_b } } // Broadcast 'd' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_d(c)) { case (in_d, pe) => pe.io.in_d := in_d pe.io.out_c } } // Broadcast 'control' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_control(c)) { case (in_ctrl, pe) => pe.io.in_control := in_ctrl pe.io.out_control } } // Broadcast 'garbage' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_valid(c)) { case (v, pe) => pe.io.in_valid := v pe.io.out_valid } } // Broadcast 'id' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_id(c)) { case (id, pe) => pe.io.in_id := id pe.io.out_id } } // Broadcast 'last' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_last(c)) { case (last, pe) => pe.io.in_last := last pe.io.out_last } } // Drive the Tile's bottom IO for (c <- 0 until columns) { io.out_c(c) := tile(rows-1)(c).io.out_c io.out_control(c) := tile(rows-1)(c).io.out_control io.out_id(c) := tile(rows-1)(c).io.out_id io.out_last(c) := tile(rows-1)(c).io.out_last io.out_valid(c) := tile(rows-1)(c).io.out_valid io.out_b(c) := { if (tree_reduction) { val prods = tileT(c).map(_.io.out_b) accumulateTree(prods :+ io.in_b(c)) } else { tile(rows - 1)(c).io.out_b } } } io.bad_dataflow := tile.map(_.map(_.io.bad_dataflow).reduce(_||_)).reduce(_||_) // Drive the Tile's right IO for (r <- 0 until rows) { io.out_a(r) := tile(r)(columns-1).io.out_a } }

module Tile_208( // @[Tile.scala:16:7] input clock, // @[Tile.scala:16:7] input reset, // @[Tile.scala:16:7] input [7:0] io_in_a_0, // @[Tile.scala:17:14] input [19:0] io_in_b_0, // @[Tile.scala:17:14] input [19:0] io_in_d_0, // @[Tile.scala:17:14] input io_in_control_0_dataflow, // @[Tile.scala:17:14] input io_in_control_0_propagate, // @[Tile.scala:17:14] input [4:0] io_in_control_0_shift, // @[Tile.scala:17:14] input [2:0] io_in_id_0, // @[Tile.scala:17:14] input io_in_last_0, // @[Tile.scala:17:14] output [7:0] io_out_a_0, // @[Tile.scala:17:14] output [19:0] io_out_c_0, // @[Tile.scala:17:14] output [19:0] io_out_b_0, // @[Tile.scala:17:14] output io_out_control_0_dataflow, // @[Tile.scala:17:14] output io_out_control_0_propagate, // @[Tile.scala:17:14] output [4:0] io_out_control_0_shift, // @[Tile.scala:17:14] output [2:0] io_out_id_0, // @[Tile.scala:17:14] output io_out_last_0, // @[Tile.scala:17:14] input io_in_valid_0, // @[Tile.scala:17:14] output io_out_valid_0, // @[Tile.scala:17:14] output io_bad_dataflow // @[Tile.scala:17:14] ); wire [7:0] io_in_a_0_0 = io_in_a_0; // @[Tile.scala:16:7] wire [19:0] io_in_b_0_0 = io_in_b_0; // @[Tile.scala:16:7] wire [19:0] io_in_d_0_0 = io_in_d_0; // @[Tile.scala:16:7] wire io_in_control_0_dataflow_0 = io_in_control_0_dataflow; // @[Tile.scala:16:7] wire io_in_control_0_propagate_0 = io_in_control_0_propagate; // @[Tile.scala:16:7] wire [4:0] io_in_control_0_shift_0 = io_in_control_0_shift; // @[Tile.scala:16:7] wire [2:0] io_in_id_0_0 = io_in_id_0; // @[Tile.scala:16:7] wire io_in_last_0_0 = io_in_last_0; // @[Tile.scala:16:7] wire io_in_valid_0_0 = io_in_valid_0; // @[Tile.scala:16:7] wire [7:0] io_out_a_0_0; // @[Tile.scala:16:7] wire [19:0] io_out_c_0_0; // @[Tile.scala:16:7] wire [19:0] io_out_b_0_0; // @[Tile.scala:16:7] wire io_out_control_0_dataflow_0; // @[Tile.scala:16:7] wire io_out_control_0_propagate_0; // @[Tile.scala:16:7] wire [4:0] io_out_control_0_shift_0; // @[Tile.scala:16:7] wire [2:0] io_out_id_0_0; // @[Tile.scala:16:7] wire io_out_last_0_0; // @[Tile.scala:16:7] wire io_out_valid_0_0; // @[Tile.scala:16:7] wire io_bad_dataflow_0; // @[Tile.scala:16:7] PE_464 tile_0_0 ( // @[Tile.scala:42:44] .clock (clock), .reset (reset), .io_in_a (io_in_a_0_0), // @[Tile.scala:16:7] .io_in_b (io_in_b_0_0), // @[Tile.scala:16:7] .io_in_d (io_in_d_0_0), // @[Tile.scala:16:7] .io_out_a (io_out_a_0_0), .io_out_b (io_out_b_0_0), .io_out_c (io_out_c_0_0), .io_in_control_dataflow (io_in_control_0_dataflow_0), // @[Tile.scala:16:7] .io_in_control_propagate (io_in_control_0_propagate_0), // @[Tile.scala:16:7] .io_in_control_shift (io_in_control_0_shift_0), // @[Tile.scala:16:7] .io_out_control_dataflow (io_out_control_0_dataflow_0), .io_out_control_propagate (io_out_control_0_propagate_0), .io_out_control_shift (io_out_control_0_shift_0), .io_in_id (io_in_id_0_0), // @[Tile.scala:16:7] .io_out_id (io_out_id_0_0), .io_in_last (io_in_last_0_0), // @[Tile.scala:16:7] .io_out_last (io_out_last_0_0), .io_in_valid (io_in_valid_0_0), // @[Tile.scala:16:7] .io_out_valid (io_out_valid_0_0), .io_bad_dataflow (io_bad_dataflow_0) ); // @[Tile.scala:42:44] assign io_out_a_0 = io_out_a_0_0; // @[Tile.scala:16:7] assign io_out_c_0 = io_out_c_0_0; // @[Tile.scala:16:7] assign io_out_b_0 = io_out_b_0_0; // @[Tile.scala:16:7] assign io_out_control_0_dataflow = io_out_control_0_dataflow_0; // @[Tile.scala:16:7] assign io_out_control_0_propagate = io_out_control_0_propagate_0; // @[Tile.scala:16:7] assign io_out_control_0_shift = io_out_control_0_shift_0; // @[Tile.scala:16:7] assign io_out_id_0 = io_out_id_0_0; // @[Tile.scala:16:7] assign io_out_last_0 = io_out_last_0_0; // @[Tile.scala:16:7] assign io_out_valid_0 = io_out_valid_0_0; // @[Tile.scala:16:7] assign io_bad_dataflow = io_bad_dataflow_0; // @[Tile.scala:16:7] endmodule

Generate the Verilog code corresponding to the following Chisel files. File ShiftReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ // Similar to the Chisel ShiftRegister but allows the user to suggest a // name to the registers that get instantiated, and // to provide a reset value. object ShiftRegInit { def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T = (0 until n).foldRight(in) { case (i, next) => { val r = RegNext(next, init) name.foreach { na => r.suggestName(s"${na}_${i}") } r } } } /** These wrap behavioral * shift registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * The different types vary in their reset behavior: * AsyncResetShiftReg -- Asynchronously reset register array * A W(width) x D(depth) sized array is constructed from D instantiations of a * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg, * but only used for timing applications */ abstract class AbstractPipelineReg(w: Int = 1) extends Module { val io = IO(new Bundle { val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) } ) } object AbstractPipelineReg { def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = { val chain = Module(gen) name.foreach{ chain.suggestName(_) } chain.io.d := in.asUInt chain.io.q.asTypeOf(in) } } class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) { require(depth > 0, "Depth must be greater than 0.") override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}" val chain = List.tabulate(depth) { i => Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}") } chain.last.io.d := io.d chain.last.io.en := true.B (chain.init zip chain.tail).foreach { case (sink, source) => sink.io.d := source.io.q sink.io.en := true.B } io.q := chain.head.io.q } object AsyncResetShiftReg { def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name) def apply [T <: Data](in: T, depth: Int, name: Option[String]): T = apply(in, depth, 0, name) def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T = apply(in, depth, init.litValue.toInt, name) def apply [T <: Data](in: T, depth: Int, init: T): T = apply (in, depth, init.litValue.toInt, None) } File AsyncQueue.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ case class AsyncQueueParams( depth: Int = 8, sync: Int = 3, safe: Boolean = true, // If safe is true, then effort is made to resynchronize the crossing indices when either side is reset. // This makes it safe/possible to reset one side of the crossing (but not the other) when the queue is empty. narrow: Boolean = false) // If narrow is true then the read mux is moved to the source side of the crossing. // This reduces the number of level shifters in the case where the clock crossing is also a voltage crossing, // at the expense of a combinational path from the sink to the source and back to the sink. { require (depth > 0 && isPow2(depth)) require (sync >= 2) val bits = log2Ceil(depth) val wires = if (narrow) 1 else depth } object AsyncQueueParams { // When there is only one entry, we don't need narrow. def singleton(sync: Int = 3, safe: Boolean = true) = AsyncQueueParams(1, sync, safe, false) } class AsyncBundleSafety extends Bundle { val ridx_valid = Input (Bool()) val widx_valid = Output(Bool()) val source_reset_n = Output(Bool()) val sink_reset_n = Input (Bool()) } class AsyncBundle[T <: Data](private val gen: T, val params: AsyncQueueParams = AsyncQueueParams()) extends Bundle { // Data-path synchronization val mem = Output(Vec(params.wires, gen)) val ridx = Input (UInt((params.bits+1).W)) val widx = Output(UInt((params.bits+1).W)) val index = params.narrow.option(Input(UInt(params.bits.W))) // Signals used to self-stabilize a safe AsyncQueue val safe = params.safe.option(new AsyncBundleSafety) } object GrayCounter { def apply(bits: Int, increment: Bool = true.B, clear: Bool = false.B, name: String = "binary"): UInt = { val incremented = Wire(UInt(bits.W)) val binary = RegNext(next=incremented, init=0.U).suggestName(name) incremented := Mux(clear, 0.U, binary + increment.asUInt) incremented ^ (incremented >> 1) } } class AsyncValidSync(sync: Int, desc: String) extends RawModule { val io = IO(new Bundle { val in = Input(Bool()) val out = Output(Bool()) }) val clock = IO(Input(Clock())) val reset = IO(Input(AsyncReset())) withClockAndReset(clock, reset){ io.out := AsyncResetSynchronizerShiftReg(io.in, sync, Some(desc)) } } class AsyncQueueSource[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module { override def desiredName = s"AsyncQueueSource_${gen.typeName}" val io = IO(new Bundle { // These come from the source domain val enq = Flipped(Decoupled(gen)) // These cross to the sink clock domain val async = new AsyncBundle(gen, params) }) val bits = params.bits val sink_ready = WireInit(true.B) val mem = Reg(Vec(params.depth, gen)) // This does NOT need to be reset at all. val widx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.enq.fire, !sink_ready, "widx_bin")) val ridx = AsyncResetSynchronizerShiftReg(io.async.ridx, params.sync, Some("ridx_gray")) val ready = sink_ready && widx =/= (ridx ^ (params.depth | params.depth >> 1).U) val index = if (bits == 0) 0.U else io.async.widx(bits-1, 0) ^ (io.async.widx(bits, bits) << (bits-1)) when (io.enq.fire) { mem(index) := io.enq.bits } val ready_reg = withReset(reset.asAsyncReset)(RegNext(next=ready, init=false.B).suggestName("ready_reg")) io.enq.ready := ready_reg && sink_ready val widx_reg = withReset(reset.asAsyncReset)(RegNext(next=widx, init=0.U).suggestName("widx_gray")) io.async.widx := widx_reg io.async.index match { case Some(index) => io.async.mem(0) := mem(index) case None => io.async.mem := mem } io.async.safe.foreach { sio => val source_valid_0 = Module(new AsyncValidSync(params.sync, "source_valid_0")) val source_valid_1 = Module(new AsyncValidSync(params.sync, "source_valid_1")) val sink_extend = Module(new AsyncValidSync(params.sync, "sink_extend")) val sink_valid = Module(new AsyncValidSync(params.sync, "sink_valid")) source_valid_0.reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset source_valid_1.reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset sink_extend .reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset sink_valid .reset := reset.asAsyncReset source_valid_0.clock := clock source_valid_1.clock := clock sink_extend .clock := clock sink_valid .clock := clock source_valid_0.io.in := true.B source_valid_1.io.in := source_valid_0.io.out sio.widx_valid := source_valid_1.io.out sink_extend.io.in := sio.ridx_valid sink_valid.io.in := sink_extend.io.out sink_ready := sink_valid.io.out sio.source_reset_n := !reset.asBool // Assert that if there is stuff in the queue, then reset cannot happen // Impossible to write because dequeue can occur on the receiving side, // then reset allowed to happen, but write side cannot know that dequeue // occurred. // TODO: write some sort of sanity check assertion for users // that denote don't reset when there is activity // assert (!(reset || !sio.sink_reset_n) || !io.enq.valid, "Enqueue while sink is reset and AsyncQueueSource is unprotected") // assert (!reset_rise || prev_idx_match.asBool, "Sink reset while AsyncQueueSource not empty") } } class AsyncQueueSink[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module { override def desiredName = s"AsyncQueueSink_${gen.typeName}" val io = IO(new Bundle { // These come from the sink domain val deq = Decoupled(gen) // These cross to the source clock domain val async = Flipped(new AsyncBundle(gen, params)) }) val bits = params.bits val source_ready = WireInit(true.B) val ridx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.deq.fire, !source_ready, "ridx_bin")) val widx = AsyncResetSynchronizerShiftReg(io.async.widx, params.sync, Some("widx_gray")) val valid = source_ready && ridx =/= widx // The mux is safe because timing analysis ensures ridx has reached the register // On an ASIC, changes to the unread location cannot affect the selected value // On an FPGA, only one input changes at a time => mem updates don't cause glitches // The register only latches when the selected valued is not being written val index = if (bits == 0) 0.U else ridx(bits-1, 0) ^ (ridx(bits, bits) << (bits-1)) io.async.index.foreach { _ := index } // This register does not NEED to be reset, as its contents will not // be considered unless the asynchronously reset deq valid register is set. // It is possible that bits latches when the source domain is reset / has power cut // This is safe, because isolation gates brought mem low before the zeroed widx reached us val deq_bits_nxt = io.async.mem(if (params.narrow) 0.U else index) io.deq.bits := ClockCrossingReg(deq_bits_nxt, en = valid, doInit = false, name = Some("deq_bits_reg")) val valid_reg = withReset(reset.asAsyncReset)(RegNext(next=valid, init=false.B).suggestName("valid_reg")) io.deq.valid := valid_reg && source_ready val ridx_reg = withReset(reset.asAsyncReset)(RegNext(next=ridx, init=0.U).suggestName("ridx_gray")) io.async.ridx := ridx_reg io.async.safe.foreach { sio => val sink_valid_0 = Module(new AsyncValidSync(params.sync, "sink_valid_0")) val sink_valid_1 = Module(new AsyncValidSync(params.sync, "sink_valid_1")) val source_extend = Module(new AsyncValidSync(params.sync, "source_extend")) val source_valid = Module(new AsyncValidSync(params.sync, "source_valid")) sink_valid_0 .reset := (reset.asBool || !sio.source_reset_n).asAsyncReset sink_valid_1 .reset := (reset.asBool || !sio.source_reset_n).asAsyncReset source_extend.reset := (reset.asBool || !sio.source_reset_n).asAsyncReset source_valid .reset := reset.asAsyncReset sink_valid_0 .clock := clock sink_valid_1 .clock := clock source_extend.clock := clock source_valid .clock := clock sink_valid_0.io.in := true.B sink_valid_1.io.in := sink_valid_0.io.out sio.ridx_valid := sink_valid_1.io.out source_extend.io.in := sio.widx_valid source_valid.io.in := source_extend.io.out source_ready := source_valid.io.out sio.sink_reset_n := !reset.asBool // TODO: write some sort of sanity check assertion for users // that denote don't reset when there is activity // // val reset_and_extend = !source_ready || !sio.source_reset_n || reset.asBool // val reset_and_extend_prev = RegNext(reset_and_extend, true.B) // val reset_rise = !reset_and_extend_prev && reset_and_extend // val prev_idx_match = AsyncResetReg(updateData=(io.async.widx===io.async.ridx), resetData=0) // assert (!reset_rise || prev_idx_match.asBool, "Source reset while AsyncQueueSink not empty") } } object FromAsyncBundle { // Sometimes it makes sense for the sink to have different sync than the source def apply[T <: Data](x: AsyncBundle[T]): DecoupledIO[T] = apply(x, x.params.sync) def apply[T <: Data](x: AsyncBundle[T], sync: Int): DecoupledIO[T] = { val sink = Module(new AsyncQueueSink(chiselTypeOf(x.mem(0)), x.params.copy(sync = sync))) sink.io.async <> x sink.io.deq } } object ToAsyncBundle { def apply[T <: Data](x: ReadyValidIO[T], params: AsyncQueueParams = AsyncQueueParams()): AsyncBundle[T] = { val source = Module(new AsyncQueueSource(chiselTypeOf(x.bits), params)) source.io.enq <> x source.io.async } } class AsyncQueue[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Crossing[T] { val io = IO(new CrossingIO(gen)) val source = withClockAndReset(io.enq_clock, io.enq_reset) { Module(new AsyncQueueSource(gen, params)) } val sink = withClockAndReset(io.deq_clock, io.deq_reset) { Module(new AsyncQueueSink (gen, params)) } source.io.enq <> io.enq io.deq <> sink.io.deq sink.io.async <> source.io.async }

module AsyncValidSync_61( // @[AsyncQueue.scala:58:7] input io_in, // @[AsyncQueue.scala:59:14] output io_out, // @[AsyncQueue.scala:59:14] input clock, // @[AsyncQueue.scala:63:17] input reset // @[AsyncQueue.scala:64:17] ); wire io_in_0 = io_in; // @[AsyncQueue.scala:58:7] wire _io_out_WIRE; // @[ShiftReg.scala:48:24] wire io_out_0; // @[AsyncQueue.scala:58:7] assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24] AsyncResetSynchronizerShiftReg_w1_d3_i0_74 io_out_sink_valid_1 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (reset), .io_d (io_in_0), // @[AsyncQueue.scala:58:7] .io_q (_io_out_WIRE) ); // @[ShiftReg.scala:45:23] assign io_out = io_out_0; // @[AsyncQueue.scala:58:7] endmodule

Generate the Verilog code corresponding to the following Chisel files. File SinkA.scala: /* * Copyright 2019 SiFive, Inc. * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You should have received a copy of LICENSE.Apache2 along with * this software. If not, you may obtain a copy at * * https://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ package sifive.blocks.inclusivecache import chisel3._ import chisel3.util._ import freechips.rocketchip.tilelink._ import freechips.rocketchip.util._ class PutBufferAEntry(params: InclusiveCacheParameters) extends InclusiveCacheBundle(params) { val data = UInt(params.inner.bundle.dataBits.W) val mask = UInt((params.inner.bundle.dataBits/8).W) val corrupt = Bool() } class PutBufferPop(params: InclusiveCacheParameters) extends InclusiveCacheBundle(params) { val index = UInt(params.putBits.W) val last = Bool() } class SinkA(params: InclusiveCacheParameters) extends Module { val io = IO(new Bundle { val req = Decoupled(new FullRequest(params)) val a = Flipped(Decoupled(new TLBundleA(params.inner.bundle))) // for use by SourceD: val pb_pop = Flipped(Decoupled(new PutBufferPop(params))) val pb_beat = new PutBufferAEntry(params) }) // No restrictions on the type of buffer val a = params.micro.innerBuf.a(io.a) val putbuffer = Module(new ListBuffer(ListBufferParameters(new PutBufferAEntry(params), params.putLists, params.putBeats, false))) val lists = RegInit((0.U(params.putLists.W))) val lists_set = WireInit(init = 0.U(params.putLists.W)) val lists_clr = WireInit(init = 0.U(params.putLists.W)) lists := (lists | lists_set) & ~lists_clr val free = !lists.andR val freeOH = ~(leftOR(~lists) << 1) & ~lists val freeIdx = OHToUInt(freeOH) val first = params.inner.first(a) val hasData = params.inner.hasData(a.bits) // We need to split the A input to three places: // If it is the first beat, it must go to req // If it has Data, it must go to the putbuffer // If it has Data AND is the first beat, it must claim a list val req_block = first && !io.req.ready val buf_block = hasData && !putbuffer.io.push.ready val set_block = hasData && first && !free params.ccover(a.valid && req_block, "SINKA_REQ_STALL", "No MSHR available to sink request") params.ccover(a.valid && buf_block, "SINKA_BUF_STALL", "No space in putbuffer for beat") params.ccover(a.valid && set_block, "SINKA_SET_STALL", "No space in putbuffer for request") a.ready := !req_block && !buf_block && !set_block io.req.valid := a.valid && first && !buf_block && !set_block putbuffer.io.push.valid := a.valid && hasData && !req_block && !set_block when (a.valid && first && hasData && !req_block && !buf_block) { lists_set := freeOH } val (tag, set, offset) = params.parseAddress(a.bits.address) val put = Mux(first, freeIdx, RegEnable(freeIdx, first)) io.req.bits.prio := VecInit(1.U(3.W).asBools) io.req.bits.control:= false.B io.req.bits.opcode := a.bits.opcode io.req.bits.param := a.bits.param io.req.bits.size := a.bits.size io.req.bits.source := a.bits.source io.req.bits.offset := offset io.req.bits.set := set io.req.bits.tag := tag io.req.bits.put := put putbuffer.io.push.bits.index := put putbuffer.io.push.bits.data.data := a.bits.data putbuffer.io.push.bits.data.mask := a.bits.mask putbuffer.io.push.bits.data.corrupt := a.bits.corrupt // Grant access to pop the data putbuffer.io.pop.bits := io.pb_pop.bits.index putbuffer.io.pop.valid := io.pb_pop.fire io.pb_pop.ready := putbuffer.io.valid(io.pb_pop.bits.index) io.pb_beat := putbuffer.io.data when (io.pb_pop.fire && io.pb_pop.bits.last) { lists_clr := UIntToOH(io.pb_pop.bits.index, params.putLists) } } File Parameters.scala: /* * Copyright 2019 SiFive, Inc. * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You should have received a copy of LICENSE.Apache2 along with * this software. If not, you may obtain a copy at * * https://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ package sifive.blocks.inclusivecache import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config._ import freechips.rocketchip.diplomacy._ import freechips.rocketchip.tilelink._ import freechips.rocketchip.util._ import freechips.rocketchip.util.property.cover import scala.math.{min,max} case class CacheParameters( level: Int, ways: Int, sets: Int, blockBytes: Int, beatBytes: Int, // inner hintsSkipProbe: Boolean) { require (ways > 0) require (sets > 0) require (blockBytes > 0 && isPow2(blockBytes)) require (beatBytes > 0 && isPow2(beatBytes)) require (blockBytes >= beatBytes) val blocks = ways * sets val sizeBytes = blocks * blockBytes val blockBeats = blockBytes/beatBytes } case class InclusiveCachePortParameters( a: BufferParams, b: BufferParams, c: BufferParams, d: BufferParams, e: BufferParams) { def apply()(implicit p: Parameters, valName: ValName) = LazyModule(new TLBuffer(a, b, c, d, e)) } object InclusiveCachePortParameters { val none = InclusiveCachePortParameters( a = BufferParams.none, b = BufferParams.none, c = BufferParams.none, d = BufferParams.none, e = BufferParams.none) val full = InclusiveCachePortParameters( a = BufferParams.default, b = BufferParams.default, c = BufferParams.default, d = BufferParams.default, e = BufferParams.default) // This removes feed-through paths from C=>A and A=>C val fullC = InclusiveCachePortParameters( a = BufferParams.none, b = BufferParams.none, c = BufferParams.default, d = BufferParams.none, e = BufferParams.none) val flowAD = InclusiveCachePortParameters( a = BufferParams.flow, b = BufferParams.none, c = BufferParams.none, d = BufferParams.flow, e = BufferParams.none) val flowAE = InclusiveCachePortParameters( a = BufferParams.flow, b = BufferParams.none, c = BufferParams.none, d = BufferParams.none, e = BufferParams.flow) // For innerBuf: // SinkA: no restrictions, flows into scheduler+putbuffer // SourceB: no restrictions, flows out of scheduler // sinkC: no restrictions, flows into scheduler+putbuffer & buffered to bankedStore // SourceD: no restrictions, flows out of bankedStore/regout // SinkE: no restrictions, flows into scheduler // // ... so while none is possible, you probably want at least flowAC to cut ready // from the scheduler delay and flowD to ease SourceD back-pressure // For outerBufer: // SourceA: must not be pipe, flows out of scheduler // SinkB: no restrictions, flows into scheduler // SourceC: pipe is useless, flows out of bankedStore/regout, parameter depth ignored // SinkD: no restrictions, flows into scheduler & bankedStore // SourceE: must not be pipe, flows out of scheduler // // ... AE take the channel ready into the scheduler, so you need at least flowAE } case class InclusiveCacheMicroParameters( writeBytes: Int, // backing store update granularity memCycles: Int = 40, // # of L2 clock cycles for a memory round-trip (50ns @ 800MHz) portFactor: Int = 4, // numSubBanks = (widest TL port * portFactor) / writeBytes dirReg: Boolean = false, innerBuf: InclusiveCachePortParameters = InclusiveCachePortParameters.fullC, // or none outerBuf: InclusiveCachePortParameters = InclusiveCachePortParameters.full) // or flowAE { require (writeBytes > 0 && isPow2(writeBytes)) require (memCycles > 0) require (portFactor >= 2) // for inner RMW and concurrent outer Relase + Grant } case class InclusiveCacheControlParameters( address: BigInt, beatBytes: Int, bankedControl: Boolean) case class InclusiveCacheParameters( cache: CacheParameters, micro: InclusiveCacheMicroParameters, control: Boolean, inner: TLEdgeIn, outer: TLEdgeOut)(implicit val p: Parameters) { require (cache.ways > 1) require (cache.sets > 1 && isPow2(cache.sets)) require (micro.writeBytes <= inner.manager.beatBytes) require (micro.writeBytes <= outer.manager.beatBytes) require (inner.manager.beatBytes <= cache.blockBytes) require (outer.manager.beatBytes <= cache.blockBytes) // Require that all cached address ranges have contiguous blocks outer.manager.managers.flatMap(_.address).foreach { a => require (a.alignment >= cache.blockBytes) } // If we are the first level cache, we do not need to support inner-BCE val firstLevel = !inner.client.clients.exists(_.supports.probe) // If we are the last level cache, we do not need to support outer-B val lastLevel = !outer.manager.managers.exists(_.regionType > RegionType.UNCACHED) require (lastLevel) // Provision enough resources to achieve full throughput with missing single-beat accesses val mshrs = InclusiveCacheParameters.all_mshrs(cache, micro) val secondary = max(mshrs, micro.memCycles - mshrs) val putLists = micro.memCycles // allow every request to be single beat val putBeats = max(2*cache.blockBeats, micro.memCycles) val relLists = 2 val relBeats = relLists*cache.blockBeats val flatAddresses = AddressSet.unify(outer.manager.managers.flatMap(_.address)) val pickMask = AddressDecoder(flatAddresses.map(Seq(_)), flatAddresses.map(_.mask).reduce(_|_)) def bitOffsets(x: BigInt, offset: Int = 0, tail: List[Int] = List.empty[Int]): List[Int] = if (x == 0) tail.reverse else bitOffsets(x >> 1, offset + 1, if ((x & 1) == 1) offset :: tail else tail) val addressMapping = bitOffsets(pickMask) val addressBits = addressMapping.size // println(s"addresses: ${flatAddresses} => ${pickMask} => ${addressBits}") val allClients = inner.client.clients.size val clientBitsRaw = inner.client.clients.filter(_.supports.probe).size val clientBits = max(1, clientBitsRaw) val stateBits = 2 val wayBits = log2Ceil(cache.ways) val setBits = log2Ceil(cache.sets) val offsetBits = log2Ceil(cache.blockBytes) val tagBits = addressBits - setBits - offsetBits val putBits = log2Ceil(max(putLists, relLists)) require (tagBits > 0) require (offsetBits > 0) val innerBeatBits = (offsetBits - log2Ceil(inner.manager.beatBytes)) max 1 val outerBeatBits = (offsetBits - log2Ceil(outer.manager.beatBytes)) max 1 val innerMaskBits = inner.manager.beatBytes / micro.writeBytes val outerMaskBits = outer.manager.beatBytes / micro.writeBytes def clientBit(source: UInt): UInt = { if (clientBitsRaw == 0) { 0.U } else { Cat(inner.client.clients.filter(_.supports.probe).map(_.sourceId.contains(source)).reverse) } } def clientSource(bit: UInt): UInt = { if (clientBitsRaw == 0) { 0.U } else { Mux1H(bit, inner.client.clients.filter(_.supports.probe).map(c => c.sourceId.start.U)) } } def parseAddress(x: UInt): (UInt, UInt, UInt) = { val offset = Cat(addressMapping.map(o => x(o,o)).reverse) val set = offset >> offsetBits val tag = set >> setBits (tag(tagBits-1, 0), set(setBits-1, 0), offset(offsetBits-1, 0)) } def widen(x: UInt, width: Int): UInt = { val y = x | 0.U(width.W) assert (y >> width === 0.U) y(width-1, 0) } def expandAddress(tag: UInt, set: UInt, offset: UInt): UInt = { val base = Cat(widen(tag, tagBits), widen(set, setBits), widen(offset, offsetBits)) val bits = Array.fill(outer.bundle.addressBits) { 0.U(1.W) } addressMapping.zipWithIndex.foreach { case (a, i) => bits(a) = base(i,i) } Cat(bits.reverse) } def restoreAddress(expanded: UInt): UInt = { val missingBits = flatAddresses .map { a => (a.widen(pickMask).base, a.widen(~pickMask)) } // key is the bits to restore on match .groupBy(_._1) .view .mapValues(_.map(_._2)) val muxMask = AddressDecoder(missingBits.values.toList) val mux = missingBits.toList.map { case (bits, addrs) => val widen = addrs.map(_.widen(~muxMask)) val matches = AddressSet .unify(widen.distinct) .map(_.contains(expanded)) .reduce(_ || _) (matches, bits.U) } expanded | Mux1H(mux) } def dirReg[T <: Data](x: T, en: Bool = true.B): T = { if (micro.dirReg) RegEnable(x, en) else x } def ccover(cond: Bool, label: String, desc: String)(implicit sourceInfo: SourceInfo) = cover(cond, "CCACHE_L" + cache.level + "_" + label, "MemorySystem;;" + desc) } object MetaData { val stateBits = 2 def INVALID: UInt = 0.U(stateBits.W) // way is empty def BRANCH: UInt = 1.U(stateBits.W) // outer slave cache is trunk def TRUNK: UInt = 2.U(stateBits.W) // unique inner master cache is trunk def TIP: UInt = 3.U(stateBits.W) // we are trunk, inner masters are branch // Does a request need trunk? def needT(opcode: UInt, param: UInt): Bool = { !opcode(2) || (opcode === TLMessages.Hint && param === TLHints.PREFETCH_WRITE) || ((opcode === TLMessages.AcquireBlock || opcode === TLMessages.AcquirePerm) && param =/= TLPermissions.NtoB) } // Does a request prove the client need not be probed? def skipProbeN(opcode: UInt, hintsSkipProbe: Boolean): Bool = { // Acquire(toB) and Get => is N, so no probe // Acquire(*toT) => is N or B, but need T, so no probe // Hint => could be anything, so probe IS needed, if hintsSkipProbe is enabled, skip probe the same client // Put* => is N or B, so probe IS needed opcode === TLMessages.AcquireBlock || opcode === TLMessages.AcquirePerm || opcode === TLMessages.Get || (opcode === TLMessages.Hint && hintsSkipProbe.B) } def isToN(param: UInt): Bool = { param === TLPermissions.TtoN || param === TLPermissions.BtoN || param === TLPermissions.NtoN } def isToB(param: UInt): Bool = { param === TLPermissions.TtoB || param === TLPermissions.BtoB } } object InclusiveCacheParameters { val lfsrBits = 10 val L2ControlAddress = 0x2010000 val L2ControlSize = 0x1000 def out_mshrs(cache: CacheParameters, micro: InclusiveCacheMicroParameters): Int = { // We need 2-3 normal MSHRs to cover the Directory latency // To fully exploit memory bandwidth-delay-product, we need memCyles/blockBeats MSHRs max(if (micro.dirReg) 3 else 2, (micro.memCycles + cache.blockBeats - 1) / cache.blockBeats) } def all_mshrs(cache: CacheParameters, micro: InclusiveCacheMicroParameters): Int = // We need a dedicated MSHR for B+C each 2 + out_mshrs(cache, micro) } class InclusiveCacheBundle(params: InclusiveCacheParameters) extends Bundle File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) || !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.ProbeAckData || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode | small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U || beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }

module SinkA( // @[SinkA.scala:38:7] input clock, // @[SinkA.scala:38:7] input reset, // @[SinkA.scala:38:7] input io_req_ready, // @[SinkA.scala:40:14] output io_req_valid, // @[SinkA.scala:40:14] output [2:0] io_req_bits_opcode, // @[SinkA.scala:40:14] output [2:0] io_req_bits_param, // @[SinkA.scala:40:14] output [2:0] io_req_bits_size, // @[SinkA.scala:40:14] output [7:0] io_req_bits_source, // @[SinkA.scala:40:14] output [12:0] io_req_bits_tag, // @[SinkA.scala:40:14] output [5:0] io_req_bits_offset, // @[SinkA.scala:40:14] output [5:0] io_req_bits_put, // @[SinkA.scala:40:14] output [9:0] io_req_bits_set, // @[SinkA.scala:40:14] output io_a_ready, // @[SinkA.scala:40:14] input io_a_valid, // @[SinkA.scala:40:14] input [2:0] io_a_bits_opcode, // @[SinkA.scala:40:14] input [2:0] io_a_bits_param, // @[SinkA.scala:40:14] input [2:0] io_a_bits_size, // @[SinkA.scala:40:14] input [7:0] io_a_bits_source, // @[SinkA.scala:40:14] input [31:0] io_a_bits_address, // @[SinkA.scala:40:14] input [31:0] io_a_bits_mask, // @[SinkA.scala:40:14] input [255:0] io_a_bits_data, // @[SinkA.scala:40:14] input io_a_bits_corrupt, // @[SinkA.scala:40:14] output io_pb_pop_ready, // @[SinkA.scala:40:14] input io_pb_pop_valid, // @[SinkA.scala:40:14] input [5:0] io_pb_pop_bits_index, // @[SinkA.scala:40:14] input io_pb_pop_bits_last, // @[SinkA.scala:40:14] output [255:0] io_pb_beat_data, // @[SinkA.scala:40:14] output [31:0] io_pb_beat_mask, // @[SinkA.scala:40:14] output io_pb_beat_corrupt // @[SinkA.scala:40:14] ); wire _putbuffer_io_push_ready; // @[SinkA.scala:51:25] wire [39:0] _putbuffer_io_valid; // @[SinkA.scala:51:25] wire io_req_ready_0 = io_req_ready; // @[SinkA.scala:38:7] wire io_a_valid_0 = io_a_valid; // @[SinkA.scala:38:7] wire [2:0] io_a_bits_opcode_0 = io_a_bits_opcode; // @[SinkA.scala:38:7] wire [2:0] io_a_bits_param_0 = io_a_bits_param; // @[SinkA.scala:38:7] wire [2:0] io_a_bits_size_0 = io_a_bits_size; // @[SinkA.scala:38:7] wire [7:0] io_a_bits_source_0 = io_a_bits_source; // @[SinkA.scala:38:7] wire [31:0] io_a_bits_address_0 = io_a_bits_address; // @[SinkA.scala:38:7] wire [31:0] io_a_bits_mask_0 = io_a_bits_mask; // @[SinkA.scala:38:7] wire [255:0] io_a_bits_data_0 = io_a_bits_data; // @[SinkA.scala:38:7] wire io_a_bits_corrupt_0 = io_a_bits_corrupt; // @[SinkA.scala:38:7] wire io_pb_pop_valid_0 = io_pb_pop_valid; // @[SinkA.scala:38:7] wire [5:0] io_pb_pop_bits_index_0 = io_pb_pop_bits_index; // @[SinkA.scala:38:7] wire io_pb_pop_bits_last_0 = io_pb_pop_bits_last; // @[SinkA.scala:38:7] wire io_req_bits_prio_1 = 1'h0; // @[SinkA.scala:38:7] wire io_req_bits_prio_2 = 1'h0; // @[SinkA.scala:38:7] wire io_req_bits_control = 1'h0; // @[SinkA.scala:38:7] wire io_req_bits_prio_0 = 1'h1; // @[SinkA.scala:38:7] wire _io_req_valid_T_4; // @[SinkA.scala:79:50] wire [12:0] tag_1; // @[Parameters.scala:217:9] wire [5:0] offset_1; // @[Parameters.scala:217:50] wire [5:0] put; // @[SinkA.scala:84:16] wire [9:0] set_1; // @[Parameters.scala:217:28] wire _io_a_ready_T_4; // @[SinkA.scala:78:39] wire [2:0] io_req_bits_opcode_0 = io_a_bits_opcode_0; // @[SinkA.scala:38:7] wire [2:0] io_req_bits_param_0 = io_a_bits_param_0; // @[SinkA.scala:38:7] wire [2:0] io_req_bits_size_0 = io_a_bits_size_0; // @[SinkA.scala:38:7] wire [7:0] io_req_bits_source_0 = io_a_bits_source_0; // @[SinkA.scala:38:7] wire _io_pb_pop_ready_T_1; // @[SinkA.scala:105:40] wire [5:0] lists_clr_shiftAmount = io_pb_pop_bits_index_0; // @[OneHot.scala:64:49] wire [12:0] io_req_bits_tag_0; // @[SinkA.scala:38:7] wire [5:0] io_req_bits_offset_0; // @[SinkA.scala:38:7] wire [5:0] io_req_bits_put_0; // @[SinkA.scala:38:7] wire [9:0] io_req_bits_set_0; // @[SinkA.scala:38:7] wire io_req_valid_0; // @[SinkA.scala:38:7] wire io_a_ready_0; // @[SinkA.scala:38:7] wire io_pb_pop_ready_0; // @[SinkA.scala:38:7] wire [255:0] io_pb_beat_data_0; // @[SinkA.scala:38:7] wire [31:0] io_pb_beat_mask_0; // @[SinkA.scala:38:7] wire io_pb_beat_corrupt_0; // @[SinkA.scala:38:7] reg [39:0] lists; // @[SinkA.scala:52:22] wire [39:0] lists_set; // @[SinkA.scala:54:27] wire [39:0] lists_clr; // @[SinkA.scala:55:27] wire [39:0] _lists_T = lists | lists_set; // @[SinkA.scala:52:22, :54:27, :56:19] wire [39:0] _lists_T_1 = ~lists_clr; // @[SinkA.scala:55:27, :56:34] wire [39:0] _lists_T_2 = _lists_T & _lists_T_1; // @[SinkA.scala:56:{19,32,34}] wire _free_T = &lists; // @[SinkA.scala:52:22, :58:21] wire free = ~_free_T; // @[SinkA.scala:58:{14,21}] wire [39:0] _freeOH_T = ~lists; // @[SinkA.scala:52:22, :59:25] wire [40:0] _freeOH_T_1 = {_freeOH_T, 1'h0}; // @[package.scala:253:48] wire [39:0] _freeOH_T_2 = _freeOH_T_1[39:0]; // @[package.scala:253:{48,53}] wire [39:0] _freeOH_T_3 = _freeOH_T | _freeOH_T_2; // @[package.scala:253:{43,53}] wire [41:0] _freeOH_T_4 = {_freeOH_T_3, 2'h0}; // @[package.scala:253:{43,48}] wire [39:0] _freeOH_T_5 = _freeOH_T_4[39:0]; // @[package.scala:253:{48,53}] wire [39:0] _freeOH_T_6 = _freeOH_T_3 | _freeOH_T_5; // @[package.scala:253:{43,53}] wire [43:0] _freeOH_T_7 = {_freeOH_T_6, 4'h0}; // @[package.scala:253:{43,48}] wire [39:0] _freeOH_T_8 = _freeOH_T_7[39:0]; // @[package.scala:253:{48,53}] wire [39:0] _freeOH_T_9 = _freeOH_T_6 | _freeOH_T_8; // @[package.scala:253:{43,53}] wire [47:0] _freeOH_T_10 = {_freeOH_T_9, 8'h0}; // @[package.scala:253:{43,48}] wire [39:0] _freeOH_T_11 = _freeOH_T_10[39:0]; // @[package.scala:253:{48,53}] wire [39:0] _freeOH_T_12 = _freeOH_T_9 | _freeOH_T_11; // @[package.scala:253:{43,53}] wire [55:0] _freeOH_T_13 = {_freeOH_T_12, 16'h0}; // @[package.scala:253:{43,48}] wire [39:0] _freeOH_T_14 = _freeOH_T_13[39:0]; // @[package.scala:253:{48,53}] wire [39:0] _freeOH_T_15 = _freeOH_T_12 | _freeOH_T_14; // @[package.scala:253:{43,53}] wire [71:0] _freeOH_T_16 = {_freeOH_T_15, 32'h0}; // @[package.scala:253:{43,48}] wire [39:0] _freeOH_T_17 = _freeOH_T_16[39:0]; // @[package.scala:253:{48,53}] wire [39:0] _freeOH_T_18 = _freeOH_T_15 | _freeOH_T_17; // @[package.scala:253:{43,53}] wire [39:0] _freeOH_T_19 = _freeOH_T_18; // @[package.scala:253:43, :254:17] wire [40:0] _freeOH_T_20 = {_freeOH_T_19, 1'h0}; // @[package.scala:254:17] wire [40:0] _freeOH_T_21 = ~_freeOH_T_20; // @[SinkA.scala:59:{16,33}] wire [39:0] _freeOH_T_22 = ~lists; // @[SinkA.scala:52:22, :59:{25,41}] wire [40:0] freeOH = {1'h0, _freeOH_T_21[39:0] & _freeOH_T_22}; // @[SinkA.scala:59:{16,39,41}] wire [8:0] freeIdx_hi = freeOH[40:32]; // @[OneHot.scala:30:18] wire [31:0] freeIdx_lo = freeOH[31:0]; // @[OneHot.scala:31:18] wire _freeIdx_T = |freeIdx_hi; // @[OneHot.scala:30:18, :32:14] wire [31:0] _freeIdx_T_1 = {23'h0, freeIdx_hi} | freeIdx_lo; // @[OneHot.scala:30:18, :31:18, :32:28] wire [15:0] freeIdx_hi_1 = _freeIdx_T_1[31:16]; // @[OneHot.scala:30:18, :32:28] wire [15:0] freeIdx_lo_1 = _freeIdx_T_1[15:0]; // @[OneHot.scala:31:18, :32:28] wire _freeIdx_T_2 = |freeIdx_hi_1; // @[OneHot.scala:30:18, :32:14] wire [15:0] _freeIdx_T_3 = freeIdx_hi_1 | freeIdx_lo_1; // @[OneHot.scala:30:18, :31:18, :32:28] wire [7:0] freeIdx_hi_2 = _freeIdx_T_3[15:8]; // @[OneHot.scala:30:18, :32:28] wire [7:0] freeIdx_lo_2 = _freeIdx_T_3[7:0]; // @[OneHot.scala:31:18, :32:28] wire _freeIdx_T_4 = |freeIdx_hi_2; // @[OneHot.scala:30:18, :32:14] wire [7:0] _freeIdx_T_5 = freeIdx_hi_2 | freeIdx_lo_2; // @[OneHot.scala:30:18, :31:18, :32:28] wire [3:0] freeIdx_hi_3 = _freeIdx_T_5[7:4]; // @[OneHot.scala:30:18, :32:28] wire [3:0] freeIdx_lo_3 = _freeIdx_T_5[3:0]; // @[OneHot.scala:31:18, :32:28] wire _freeIdx_T_6 = |freeIdx_hi_3; // @[OneHot.scala:30:18, :32:14] wire [3:0] _freeIdx_T_7 = freeIdx_hi_3 | freeIdx_lo_3; // @[OneHot.scala:30:18, :31:18, :32:28] wire [1:0] freeIdx_hi_4 = _freeIdx_T_7[3:2]; // @[OneHot.scala:30:18, :32:28] wire [1:0] freeIdx_lo_4 = _freeIdx_T_7[1:0]; // @[OneHot.scala:31:18, :32:28] wire _freeIdx_T_8 = |freeIdx_hi_4; // @[OneHot.scala:30:18, :32:14] wire [1:0] _freeIdx_T_9 = freeIdx_hi_4 | freeIdx_lo_4; // @[OneHot.scala:30:18, :31:18, :32:28] wire _freeIdx_T_10 = _freeIdx_T_9[1]; // @[OneHot.scala:32:28] wire [1:0] _freeIdx_T_11 = {_freeIdx_T_8, _freeIdx_T_10}; // @[OneHot.scala:32:{10,14}] wire [2:0] _freeIdx_T_12 = {_freeIdx_T_6, _freeIdx_T_11}; // @[OneHot.scala:32:{10,14}] wire [3:0] _freeIdx_T_13 = {_freeIdx_T_4, _freeIdx_T_12}; // @[OneHot.scala:32:{10,14}] wire [4:0] _freeIdx_T_14 = {_freeIdx_T_2, _freeIdx_T_13}; // @[OneHot.scala:32:{10,14}] wire [5:0] freeIdx = {_freeIdx_T, _freeIdx_T_14}; // @[OneHot.scala:32:{10,14}] wire _first_T = io_a_ready_0 & io_a_valid_0; // @[Decoupled.scala:51:35] wire [12:0] _first_beats1_decode_T = 13'h3F << io_a_bits_size_0; // @[package.scala:243:71] wire [5:0] _first_beats1_decode_T_1 = _first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _first_beats1_decode_T_2 = ~_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire first_beats1_decode = _first_beats1_decode_T_2[5]; // @[package.scala:243:46] wire _first_beats1_opdata_T = io_a_bits_opcode_0[2]; // @[Edges.scala:92:37] wire _hasData_opdata_T = io_a_bits_opcode_0[2]; // @[Edges.scala:92:37] wire first_beats1_opdata = ~_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire first_beats1 = first_beats1_opdata & first_beats1_decode; // @[Edges.scala:92:28, :220:59, :221:14] reg first_counter; // @[Edges.scala:229:27] wire _first_last_T = first_counter; // @[Edges.scala:229:27, :232:25] wire [1:0] _first_counter1_T = {1'h0, first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28] wire first_counter1 = _first_counter1_T[0]; // @[Edges.scala:230:28] wire first = ~first_counter; // @[Edges.scala:229:27, :231:25] wire _first_last_T_1 = ~first_beats1; // @[Edges.scala:221:14, :232:43] wire first_last = _first_last_T | _first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire first_done = first_last & _first_T; // @[Decoupled.scala:51:35] wire _first_count_T = ~first_counter1; // @[Edges.scala:230:28, :234:27] wire first_count = first_beats1 & _first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire _first_counter_T = first ? first_beats1 : first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire hasData = ~_hasData_opdata_T; // @[Edges.scala:92:{28,37}] wire _req_block_T = ~io_req_ready_0; // @[SinkA.scala:38:7, :70:28] wire req_block = first & _req_block_T; // @[Edges.scala:231:25] wire _buf_block_T = ~_putbuffer_io_push_ready; // @[SinkA.scala:51:25, :71:30] wire buf_block = hasData & _buf_block_T; // @[Edges.scala:92:28] wire _set_block_T = hasData & first; // @[Edges.scala:92:28, :231:25] wire _set_block_T_1 = ~free; // @[SinkA.scala:58:14, :72:39] wire set_block = _set_block_T & _set_block_T_1; // @[SinkA.scala:72:{27,36,39}] wire _io_a_ready_T = ~req_block; // @[SinkA.scala:70:25, :78:14] wire _io_a_ready_T_1 = ~buf_block; // @[SinkA.scala:71:27, :78:28] wire _io_a_ready_T_2 = _io_a_ready_T & _io_a_ready_T_1; // @[SinkA.scala:78:{14,25,28}] wire _io_a_ready_T_3 = ~set_block; // @[SinkA.scala:72:36, :78:42] assign _io_a_ready_T_4 = _io_a_ready_T_2 & _io_a_ready_T_3; // @[SinkA.scala:78:{25,39,42}] assign io_a_ready_0 = _io_a_ready_T_4; // @[SinkA.scala:38:7, :78:39] wire _io_req_valid_T = io_a_valid_0 & first; // @[Edges.scala:231:25] wire _io_req_valid_T_1 = ~buf_block; // @[SinkA.scala:71:27, :78:28, :79:39] wire _io_req_valid_T_2 = _io_req_valid_T & _io_req_valid_T_1; // @[SinkA.scala:79:{27,36,39}] wire _io_req_valid_T_3 = ~set_block; // @[SinkA.scala:72:36, :78:42, :79:53] assign _io_req_valid_T_4 = _io_req_valid_T_2 & _io_req_valid_T_3; // @[SinkA.scala:79:{36,50,53}] assign io_req_valid_0 = _io_req_valid_T_4; // @[SinkA.scala:38:7, :79:50] wire _putbuffer_io_push_valid_T = io_a_valid_0 & hasData; // @[Edges.scala:92:28] wire _putbuffer_io_push_valid_T_1 = ~req_block; // @[SinkA.scala:70:25, :78:14, :80:52] wire _putbuffer_io_push_valid_T_2 = _putbuffer_io_push_valid_T & _putbuffer_io_push_valid_T_1; // @[SinkA.scala:80:{38,49,52}] wire _putbuffer_io_push_valid_T_3 = ~set_block; // @[SinkA.scala:72:36, :78:42, :80:66] wire _putbuffer_io_push_valid_T_4 = _putbuffer_io_push_valid_T_2 & _putbuffer_io_push_valid_T_3; // @[SinkA.scala:80:{49,63,66}] assign lists_set = _io_req_valid_T & hasData & ~req_block & ~buf_block ? freeOH[39:0] : 40'h0; // @[Edges.scala:92:28] wire _offset_T = io_a_bits_address_0[0]; // @[SinkA.scala:38:7] wire _offset_T_1 = io_a_bits_address_0[1]; // @[SinkA.scala:38:7] wire _offset_T_2 = io_a_bits_address_0[2]; // @[SinkA.scala:38:7] wire _offset_T_3 = io_a_bits_address_0[3]; // @[SinkA.scala:38:7] wire _offset_T_4 = io_a_bits_address_0[4]; // @[SinkA.scala:38:7] wire _offset_T_5 = io_a_bits_address_0[5]; // @[SinkA.scala:38:7] wire _offset_T_6 = io_a_bits_address_0[6]; // @[SinkA.scala:38:7] wire _offset_T_7 = io_a_bits_address_0[7]; // @[SinkA.scala:38:7] wire _offset_T_8 = io_a_bits_address_0[8]; // @[SinkA.scala:38:7] wire _offset_T_9 = io_a_bits_address_0[9]; // @[SinkA.scala:38:7] wire _offset_T_10 = io_a_bits_address_0[10]; // @[SinkA.scala:38:7] wire _offset_T_11 = io_a_bits_address_0[11]; // @[SinkA.scala:38:7] wire _offset_T_12 = io_a_bits_address_0[12]; // @[SinkA.scala:38:7] wire _offset_T_13 = io_a_bits_address_0[13]; // @[SinkA.scala:38:7] wire _offset_T_14 = io_a_bits_address_0[14]; // @[SinkA.scala:38:7] wire _offset_T_15 = io_a_bits_address_0[15]; // @[SinkA.scala:38:7] wire _offset_T_16 = io_a_bits_address_0[16]; // @[SinkA.scala:38:7] wire _offset_T_17 = io_a_bits_address_0[17]; // @[SinkA.scala:38:7] wire _offset_T_18 = io_a_bits_address_0[18]; // @[SinkA.scala:38:7] wire _offset_T_19 = io_a_bits_address_0[19]; // @[SinkA.scala:38:7] wire _offset_T_20 = io_a_bits_address_0[20]; // @[SinkA.scala:38:7] wire _offset_T_21 = io_a_bits_address_0[21]; // @[SinkA.scala:38:7] wire _offset_T_22 = io_a_bits_address_0[22]; // @[SinkA.scala:38:7] wire _offset_T_23 = io_a_bits_address_0[23]; // @[SinkA.scala:38:7] wire _offset_T_24 = io_a_bits_address_0[24]; // @[SinkA.scala:38:7] wire _offset_T_25 = io_a_bits_address_0[25]; // @[SinkA.scala:38:7] wire _offset_T_26 = io_a_bits_address_0[26]; // @[SinkA.scala:38:7] wire _offset_T_27 = io_a_bits_address_0[27]; // @[SinkA.scala:38:7] wire _offset_T_28 = io_a_bits_address_0[31]; // @[SinkA.scala:38:7] wire [1:0] offset_lo_lo_lo_hi = {_offset_T_2, _offset_T_1}; // @[Parameters.scala:214:{21,47}] wire [2:0] offset_lo_lo_lo = {offset_lo_lo_lo_hi, _offset_T}; // @[Parameters.scala:214:{21,47}] wire [1:0] offset_lo_lo_hi_lo = {_offset_T_4, _offset_T_3}; // @[Parameters.scala:214:{21,47}] wire [1:0] offset_lo_lo_hi_hi = {_offset_T_6, _offset_T_5}; // @[Parameters.scala:214:{21,47}] wire [3:0] offset_lo_lo_hi = {offset_lo_lo_hi_hi, offset_lo_lo_hi_lo}; // @[Parameters.scala:214:21] wire [6:0] offset_lo_lo = {offset_lo_lo_hi, offset_lo_lo_lo}; // @[Parameters.scala:214:21] wire [1:0] offset_lo_hi_lo_hi = {_offset_T_9, _offset_T_8}; // @[Parameters.scala:214:{21,47}] wire [2:0] offset_lo_hi_lo = {offset_lo_hi_lo_hi, _offset_T_7}; // @[Parameters.scala:214:{21,47}] wire [1:0] offset_lo_hi_hi_lo = {_offset_T_11, _offset_T_10}; // @[Parameters.scala:214:{21,47}] wire [1:0] offset_lo_hi_hi_hi = {_offset_T_13, _offset_T_12}; // @[Parameters.scala:214:{21,47}] wire [3:0] offset_lo_hi_hi = {offset_lo_hi_hi_hi, offset_lo_hi_hi_lo}; // @[Parameters.scala:214:21] wire [6:0] offset_lo_hi = {offset_lo_hi_hi, offset_lo_hi_lo}; // @[Parameters.scala:214:21] wire [13:0] offset_lo = {offset_lo_hi, offset_lo_lo}; // @[Parameters.scala:214:21] wire [1:0] offset_hi_lo_lo_hi = {_offset_T_16, _offset_T_15}; // @[Parameters.scala:214:{21,47}] wire [2:0] offset_hi_lo_lo = {offset_hi_lo_lo_hi, _offset_T_14}; // @[Parameters.scala:214:{21,47}] wire [1:0] offset_hi_lo_hi_lo = {_offset_T_18, _offset_T_17}; // @[Parameters.scala:214:{21,47}] wire [1:0] offset_hi_lo_hi_hi = {_offset_T_20, _offset_T_19}; // @[Parameters.scala:214:{21,47}] wire [3:0] offset_hi_lo_hi = {offset_hi_lo_hi_hi, offset_hi_lo_hi_lo}; // @[Parameters.scala:214:21] wire [6:0] offset_hi_lo = {offset_hi_lo_hi, offset_hi_lo_lo}; // @[Parameters.scala:214:21] wire [1:0] offset_hi_hi_lo_lo = {_offset_T_22, _offset_T_21}; // @[Parameters.scala:214:{21,47}] wire [1:0] offset_hi_hi_lo_hi = {_offset_T_24, _offset_T_23}; // @[Parameters.scala:214:{21,47}] wire [3:0] offset_hi_hi_lo = {offset_hi_hi_lo_hi, offset_hi_hi_lo_lo}; // @[Parameters.scala:214:21] wire [1:0] offset_hi_hi_hi_lo = {_offset_T_26, _offset_T_25}; // @[Parameters.scala:214:{21,47}] wire [1:0] offset_hi_hi_hi_hi = {_offset_T_28, _offset_T_27}; // @[Parameters.scala:214:{21,47}] wire [3:0] offset_hi_hi_hi = {offset_hi_hi_hi_hi, offset_hi_hi_hi_lo}; // @[Parameters.scala:214:21] wire [7:0] offset_hi_hi = {offset_hi_hi_hi, offset_hi_hi_lo}; // @[Parameters.scala:214:21] wire [14:0] offset_hi = {offset_hi_hi, offset_hi_lo}; // @[Parameters.scala:214:21] wire [28:0] offset = {offset_hi, offset_lo}; // @[Parameters.scala:214:21] wire [22:0] set = offset[28:6]; // @[Parameters.scala:214:21, :215:22] wire [12:0] tag = set[22:10]; // @[Parameters.scala:215:22, :216:19] assign tag_1 = tag; // @[Parameters.scala:216:19, :217:9] assign io_req_bits_tag_0 = tag_1; // @[SinkA.scala:38:7] assign set_1 = set[9:0]; // @[Parameters.scala:215:22, :217:28] assign io_req_bits_set_0 = set_1; // @[SinkA.scala:38:7] assign offset_1 = offset[5:0]; // @[Parameters.scala:214:21, :217:50] assign io_req_bits_offset_0 = offset_1; // @[SinkA.scala:38:7] reg [5:0] put_r; // @[SinkA.scala:84:42] assign put = first ? freeIdx : put_r; // @[OneHot.scala:32:10] assign io_req_bits_put_0 = put; // @[SinkA.scala:38:7, :84:16] wire _putbuffer_io_pop_valid_T = io_pb_pop_ready_0 & io_pb_pop_valid_0; // @[Decoupled.scala:51:35] wire [39:0] _io_pb_pop_ready_T = _putbuffer_io_valid >> io_pb_pop_bits_index_0; // @[SinkA.scala:38:7, :51:25, :105:40] assign _io_pb_pop_ready_T_1 = _io_pb_pop_ready_T[0]; // @[SinkA.scala:105:40] assign io_pb_pop_ready_0 = _io_pb_pop_ready_T_1; // @[SinkA.scala:38:7, :105:40] wire [63:0] _lists_clr_T = 64'h1 << lists_clr_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [39:0] _lists_clr_T_1 = _lists_clr_T[39:0]; // @[OneHot.scala:65:{12,27}] assign lists_clr = _putbuffer_io_pop_valid_T & io_pb_pop_bits_last_0 ? _lists_clr_T_1 : 40'h0; // @[OneHot.scala:65:27] always @(posedge clock) begin // @[SinkA.scala:38:7] if (reset) begin // @[SinkA.scala:38:7] lists <= 40'h0; // @[SinkA.scala:52:22] first_counter <= 1'h0; // @[Edges.scala:229:27] end else begin // @[SinkA.scala:38:7] lists <= _lists_T_2; // @[SinkA.scala:52:22, :56:32] if (_first_T) // @[Decoupled.scala:51:35] first_counter <= _first_counter_T; // @[Edges.scala:229:27, :236:21] end if (first) // @[Edges.scala:231:25] put_r <= freeIdx; // @[OneHot.scala:32:10] always @(posedge) ListBuffer_PutBufferAEntry_q40_e40 putbuffer ( // @[SinkA.scala:51:25] .clock (clock), .reset (reset), .io_push_ready (_putbuffer_io_push_ready), .io_push_valid (_putbuffer_io_push_valid_T_4), // @[SinkA.scala:80:63] .io_push_bits_index (put), // @[SinkA.scala:84:16] .io_push_bits_data_data (io_a_bits_data_0), // @[SinkA.scala:38:7] .io_push_bits_data_mask (io_a_bits_mask_0), // @[SinkA.scala:38:7] .io_push_bits_data_corrupt (io_a_bits_corrupt_0), // @[SinkA.scala:38:7] .io_valid (_putbuffer_io_valid), .io_pop_valid (_putbuffer_io_pop_valid_T), // @[Decoupled.scala:51:35] .io_pop_bits (io_pb_pop_bits_index_0), // @[SinkA.scala:38:7] .io_data_data (io_pb_beat_data_0), .io_data_mask (io_pb_beat_mask_0), .io_data_corrupt (io_pb_beat_corrupt_0) ); // @[SinkA.scala:51:25] assign io_req_valid = io_req_valid_0; // @[SinkA.scala:38:7] assign io_req_bits_opcode = io_req_bits_opcode_0; // @[SinkA.scala:38:7] assign io_req_bits_param = io_req_bits_param_0; // @[SinkA.scala:38:7] assign io_req_bits_size = io_req_bits_size_0; // @[SinkA.scala:38:7] assign io_req_bits_source = io_req_bits_source_0; // @[SinkA.scala:38:7] assign io_req_bits_tag = io_req_bits_tag_0; // @[SinkA.scala:38:7] assign io_req_bits_offset = io_req_bits_offset_0; // @[SinkA.scala:38:7] assign io_req_bits_put = io_req_bits_put_0; // @[SinkA.scala:38:7] assign io_req_bits_set = io_req_bits_set_0; // @[SinkA.scala:38:7] assign io_a_ready = io_a_ready_0; // @[SinkA.scala:38:7] assign io_pb_pop_ready = io_pb_pop_ready_0; // @[SinkA.scala:38:7] assign io_pb_beat_data = io_pb_beat_data_0; // @[SinkA.scala:38:7] assign io_pb_beat_mask = io_pb_beat_mask_0; // @[SinkA.scala:38:7] assign io_pb_beat_corrupt = io_pb_beat_corrupt_0; // @[SinkA.scala:38:7] endmodule

Generate the Verilog code corresponding to the following Chisel files. File Repeater.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util.{Decoupled, DecoupledIO} // A Repeater passes its input to its output, unless repeat is asserted. // When repeat is asserted, the Repeater copies the input and repeats it next cycle. class Repeater[T <: Data](gen: T) extends Module { override def desiredName = s"Repeater_${gen.typeName}" val io = IO( new Bundle { val repeat = Input(Bool()) val full = Output(Bool()) val enq = Flipped(Decoupled(gen.cloneType)) val deq = Decoupled(gen.cloneType) } ) val full = RegInit(false.B) val saved = Reg(gen.cloneType) // When !full, a repeater is pass-through io.deq.valid := io.enq.valid || full io.enq.ready := io.deq.ready && !full io.deq.bits := Mux(full, saved, io.enq.bits) io.full := full when (io.enq.fire && io.repeat) { full := true.B; saved := io.enq.bits } when (io.deq.fire && !io.repeat) { full := false.B } } object Repeater { def apply[T <: Data](enq: DecoupledIO[T], repeat: Bool): DecoupledIO[T] = { val repeater = Module(new Repeater(chiselTypeOf(enq.bits))) repeater.io.repeat := repeat repeater.io.enq <> enq repeater.io.deq } }

module Repeater_TLBundleA_a13d64s10k1z3u( // @[Repeater.scala:10:7] input clock, // @[Repeater.scala:10:7] input reset, // @[Repeater.scala:10:7] input io_repeat, // @[Repeater.scala:13:14] output io_full, // @[Repeater.scala:13:14] output io_enq_ready, // @[Repeater.scala:13:14] input io_enq_valid, // @[Repeater.scala:13:14] input [2:0] io_enq_bits_opcode, // @[Repeater.scala:13:14] input [2:0] io_enq_bits_param, // @[Repeater.scala:13:14] input [2:0] io_enq_bits_size, // @[Repeater.scala:13:14] input [9:0] io_enq_bits_source, // @[Repeater.scala:13:14] input [12:0] io_enq_bits_address, // @[Repeater.scala:13:14] input [7:0] io_enq_bits_mask, // @[Repeater.scala:13:14] input [63:0] io_enq_bits_data, // @[Repeater.scala:13:14] input io_enq_bits_corrupt, // @[Repeater.scala:13:14] input io_deq_ready, // @[Repeater.scala:13:14] output io_deq_valid, // @[Repeater.scala:13:14] output [2:0] io_deq_bits_opcode, // @[Repeater.scala:13:14] output [2:0] io_deq_bits_param, // @[Repeater.scala:13:14] output [2:0] io_deq_bits_size, // @[Repeater.scala:13:14] output [9:0] io_deq_bits_source, // @[Repeater.scala:13:14] output [12:0] io_deq_bits_address, // @[Repeater.scala:13:14] output [7:0] io_deq_bits_mask, // @[Repeater.scala:13:14] output io_deq_bits_corrupt // @[Repeater.scala:13:14] ); wire io_repeat_0 = io_repeat; // @[Repeater.scala:10:7] wire io_enq_valid_0 = io_enq_valid; // @[Repeater.scala:10:7] wire [2:0] io_enq_bits_opcode_0 = io_enq_bits_opcode; // @[Repeater.scala:10:7] wire [2:0] io_enq_bits_param_0 = io_enq_bits_param; // @[Repeater.scala:10:7] wire [2:0] io_enq_bits_size_0 = io_enq_bits_size; // @[Repeater.scala:10:7] wire [9:0] io_enq_bits_source_0 = io_enq_bits_source; // @[Repeater.scala:10:7] wire [12:0] io_enq_bits_address_0 = io_enq_bits_address; // @[Repeater.scala:10:7] wire [7:0] io_enq_bits_mask_0 = io_enq_bits_mask; // @[Repeater.scala:10:7] wire [63:0] io_enq_bits_data_0 = io_enq_bits_data; // @[Repeater.scala:10:7] wire io_enq_bits_corrupt_0 = io_enq_bits_corrupt; // @[Repeater.scala:10:7] wire io_deq_ready_0 = io_deq_ready; // @[Repeater.scala:10:7] wire _io_enq_ready_T_1; // @[Repeater.scala:25:32] wire _io_deq_valid_T; // @[Repeater.scala:24:32] wire [2:0] _io_deq_bits_T_opcode; // @[Repeater.scala:26:21] wire [2:0] _io_deq_bits_T_param; // @[Repeater.scala:26:21] wire [2:0] _io_deq_bits_T_size; // @[Repeater.scala:26:21] wire [9:0] _io_deq_bits_T_source; // @[Repeater.scala:26:21] wire [12:0] _io_deq_bits_T_address; // @[Repeater.scala:26:21] wire [7:0] _io_deq_bits_T_mask; // @[Repeater.scala:26:21] wire [63:0] _io_deq_bits_T_data; // @[Repeater.scala:26:21] wire _io_deq_bits_T_corrupt; // @[Repeater.scala:26:21] wire io_enq_ready_0; // @[Repeater.scala:10:7] wire [2:0] io_deq_bits_opcode_0; // @[Repeater.scala:10:7] wire [2:0] io_deq_bits_param_0; // @[Repeater.scala:10:7] wire [2:0] io_deq_bits_size_0; // @[Repeater.scala:10:7] wire [9:0] io_deq_bits_source_0; // @[Repeater.scala:10:7] wire [12:0] io_deq_bits_address_0; // @[Repeater.scala:10:7] wire [7:0] io_deq_bits_mask_0; // @[Repeater.scala:10:7] wire [63:0] io_deq_bits_data; // @[Repeater.scala:10:7] wire io_deq_bits_corrupt_0; // @[Repeater.scala:10:7] wire io_deq_valid_0; // @[Repeater.scala:10:7] wire io_full_0; // @[Repeater.scala:10:7] reg full; // @[Repeater.scala:20:21] assign io_full_0 = full; // @[Repeater.scala:10:7, :20:21] reg [2:0] saved_opcode; // @[Repeater.scala:21:18] reg [2:0] saved_param; // @[Repeater.scala:21:18] reg [2:0] saved_size; // @[Repeater.scala:21:18] reg [9:0] saved_source; // @[Repeater.scala:21:18] reg [12:0] saved_address; // @[Repeater.scala:21:18] reg [7:0] saved_mask; // @[Repeater.scala:21:18] reg [63:0] saved_data; // @[Repeater.scala:21:18] reg saved_corrupt; // @[Repeater.scala:21:18] assign _io_deq_valid_T = io_enq_valid_0 | full; // @[Repeater.scala:10:7, :20:21, :24:32] assign io_deq_valid_0 = _io_deq_valid_T; // @[Repeater.scala:10:7, :24:32] wire _io_enq_ready_T = ~full; // @[Repeater.scala:20:21, :25:35] assign _io_enq_ready_T_1 = io_deq_ready_0 & _io_enq_ready_T; // @[Repeater.scala:10:7, :25:{32,35}] assign io_enq_ready_0 = _io_enq_ready_T_1; // @[Repeater.scala:10:7, :25:32] assign _io_deq_bits_T_opcode = full ? saved_opcode : io_enq_bits_opcode_0; // @[Repeater.scala:10:7, :20:21, :21:18, :26:21] assign _io_deq_bits_T_param = full ? saved_param : io_enq_bits_param_0; // @[Repeater.scala:10:7, :20:21, :21:18, :26:21] assign _io_deq_bits_T_size = full ? saved_size : io_enq_bits_size_0; // @[Repeater.scala:10:7, :20:21, :21:18, :26:21] assign _io_deq_bits_T_source = full ? saved_source : io_enq_bits_source_0; // @[Repeater.scala:10:7, :20:21, :21:18, :26:21] assign _io_deq_bits_T_address = full ? saved_address : io_enq_bits_address_0; // @[Repeater.scala:10:7, :20:21, :21:18, :26:21] assign _io_deq_bits_T_mask = full ? saved_mask : io_enq_bits_mask_0; // @[Repeater.scala:10:7, :20:21, :21:18, :26:21] assign _io_deq_bits_T_data = full ? saved_data : io_enq_bits_data_0; // @[Repeater.scala:10:7, :20:21, :21:18, :26:21] assign _io_deq_bits_T_corrupt = full ? saved_corrupt : io_enq_bits_corrupt_0; // @[Repeater.scala:10:7, :20:21, :21:18, :26:21] assign io_deq_bits_opcode_0 = _io_deq_bits_T_opcode; // @[Repeater.scala:10:7, :26:21] assign io_deq_bits_param_0 = _io_deq_bits_T_param; // @[Repeater.scala:10:7, :26:21] assign io_deq_bits_size_0 = _io_deq_bits_T_size; // @[Repeater.scala:10:7, :26:21] assign io_deq_bits_source_0 = _io_deq_bits_T_source; // @[Repeater.scala:10:7, :26:21] assign io_deq_bits_address_0 = _io_deq_bits_T_address; // @[Repeater.scala:10:7, :26:21] assign io_deq_bits_mask_0 = _io_deq_bits_T_mask; // @[Repeater.scala:10:7, :26:21] assign io_deq_bits_data = _io_deq_bits_T_data; // @[Repeater.scala:10:7, :26:21] assign io_deq_bits_corrupt_0 = _io_deq_bits_T_corrupt; // @[Repeater.scala:10:7, :26:21] wire _T_1 = io_enq_ready_0 & io_enq_valid_0 & io_repeat_0; // @[Decoupled.scala:51:35] always @(posedge clock) begin // @[Repeater.scala:10:7] if (reset) // @[Repeater.scala:10:7] full <= 1'h0; // @[Repeater.scala:20:21] else // @[Repeater.scala:10:7] full <= ~(io_deq_ready_0 & io_deq_valid_0 & ~io_repeat_0) & (_T_1 | full); // @[Decoupled.scala:51:35] if (_T_1) begin // @[Decoupled.scala:51:35] saved_opcode <= io_enq_bits_opcode_0; // @[Repeater.scala:10:7, :21:18] saved_param <= io_enq_bits_param_0; // @[Repeater.scala:10:7, :21:18] saved_size <= io_enq_bits_size_0; // @[Repeater.scala:10:7, :21:18] saved_source <= io_enq_bits_source_0; // @[Repeater.scala:10:7, :21:18] saved_address <= io_enq_bits_address_0; // @[Repeater.scala:10:7, :21:18] saved_mask <= io_enq_bits_mask_0; // @[Repeater.scala:10:7, :21:18] saved_data <= io_enq_bits_data_0; // @[Repeater.scala:10:7, :21:18] saved_corrupt <= io_enq_bits_corrupt_0; // @[Repeater.scala:10:7, :21:18] end always @(posedge) assign io_full = io_full_0; // @[Repeater.scala:10:7] assign io_enq_ready = io_enq_ready_0; // @[Repeater.scala:10:7] assign io_deq_valid = io_deq_valid_0; // @[Repeater.scala:10:7] assign io_deq_bits_opcode = io_deq_bits_opcode_0; // @[Repeater.scala:10:7] assign io_deq_bits_param = io_deq_bits_param_0; // @[Repeater.scala:10:7] assign io_deq_bits_size = io_deq_bits_size_0; // @[Repeater.scala:10:7] assign io_deq_bits_source = io_deq_bits_source_0; // @[Repeater.scala:10:7] assign io_deq_bits_address = io_deq_bits_address_0; // @[Repeater.scala:10:7] assign io_deq_bits_mask = io_deq_bits_mask_0; // @[Repeater.scala:10:7] assign io_deq_bits_corrupt = io_deq_bits_corrupt_0; // @[Repeater.scala:10:7] endmodule

Generate the Verilog code corresponding to the following Chisel files. File RecFNToRecFN.scala: /*============================================================================ This Chisel source file is part of a pre-release version of the HardFloat IEEE Floating-Point Arithmetic Package, by John R. Hauser (with some contributions from Yunsup Lee and Andrew Waterman, mainly concerning testing). Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of California. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions, and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions, and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the University nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. =============================================================================*/ package hardfloat import chisel3._ import consts._ class RecFNToRecFN( inExpWidth: Int, inSigWidth: Int, outExpWidth: Int, outSigWidth: Int) extends chisel3.RawModule { val io = IO(new Bundle { val in = Input(Bits((inExpWidth + inSigWidth + 1).W)) val roundingMode = Input(UInt(3.W)) val detectTininess = Input(UInt(1.W)) val out = Output(Bits((outExpWidth + outSigWidth + 1).W)) val exceptionFlags = Output(Bits(5.W)) }) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val rawIn = rawFloatFromRecFN(inExpWidth, inSigWidth, io.in); if ((inExpWidth == outExpWidth) && (inSigWidth <= outSigWidth)) { //-------------------------------------------------------------------- //-------------------------------------------------------------------- io.out := io.in<<(outSigWidth - inSigWidth) io.exceptionFlags := isSigNaNRawFloat(rawIn) ## 0.U(4.W) } else { //-------------------------------------------------------------------- //-------------------------------------------------------------------- val roundAnyRawFNToRecFN = Module( new RoundAnyRawFNToRecFN( inExpWidth, inSigWidth, outExpWidth, outSigWidth, flRoundOpt_sigMSBitAlwaysZero )) roundAnyRawFNToRecFN.io.invalidExc := isSigNaNRawFloat(rawIn) roundAnyRawFNToRecFN.io.infiniteExc := false.B roundAnyRawFNToRecFN.io.in := rawIn roundAnyRawFNToRecFN.io.roundingMode := io.roundingMode roundAnyRawFNToRecFN.io.detectTininess := io.detectTininess io.out := roundAnyRawFNToRecFN.io.out io.exceptionFlags := roundAnyRawFNToRecFN.io.exceptionFlags } } File rawFloatFromRecFN.scala: /*============================================================================ This Chisel source file is part of a pre-release version of the HardFloat IEEE Floating-Point Arithmetic Package, by John R. Hauser (with some contributions from Yunsup Lee and Andrew Waterman, mainly concerning testing). Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of California. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions, and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions, and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the University nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. =============================================================================*/ package hardfloat import chisel3._ import chisel3.util._ /*---------------------------------------------------------------------------- | In the result, no more than one of 'isNaN', 'isInf', and 'isZero' will be | set. *----------------------------------------------------------------------------*/ object rawFloatFromRecFN { def apply(expWidth: Int, sigWidth: Int, in: Bits): RawFloat = { val exp = in(expWidth + sigWidth - 1, sigWidth - 1) val isZero = exp(expWidth, expWidth - 2) === 0.U val isSpecial = exp(expWidth, expWidth - 1) === 3.U val out = Wire(new RawFloat(expWidth, sigWidth)) out.isNaN := isSpecial && exp(expWidth - 2) out.isInf := isSpecial && ! exp(expWidth - 2) out.isZero := isZero out.sign := in(expWidth + sigWidth) out.sExp := exp.zext out.sig := 0.U(1.W) ## ! isZero ## in(sigWidth - 2, 0) out } }

module RecFNToRecFN_148( // @[RecFNToRecFN.scala:44:5] input [32:0] io_in, // @[RecFNToRecFN.scala:48:16] output [32:0] io_out // @[RecFNToRecFN.scala:48:16] ); wire [32:0] io_in_0 = io_in; // @[RecFNToRecFN.scala:44:5] wire io_detectTininess = 1'h1; // @[RecFNToRecFN.scala:44:5, :48:16] wire [2:0] io_roundingMode = 3'h0; // @[RecFNToRecFN.scala:44:5, :48:16] wire [32:0] _io_out_T = io_in_0; // @[RecFNToRecFN.scala:44:5, :64:35] wire [4:0] _io_exceptionFlags_T_3; // @[RecFNToRecFN.scala:65:54] wire [32:0] io_out_0; // @[RecFNToRecFN.scala:44:5] wire [4:0] io_exceptionFlags; // @[RecFNToRecFN.scala:44:5] wire [8:0] rawIn_exp = io_in_0[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _rawIn_isZero_T = rawIn_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire rawIn_isZero = _rawIn_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire rawIn_isZero_0 = rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _rawIn_isSpecial_T = rawIn_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire rawIn_isSpecial = &_rawIn_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33] wire _rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33] wire _rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44] wire rawIn_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23] wire rawIn_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] rawIn_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] rawIn_sig; // @[rawFloatFromRecFN.scala:55:23] wire _rawIn_out_isNaN_T = rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _rawIn_out_isInf_T = rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _rawIn_out_isNaN_T_1 = rawIn_isSpecial & _rawIn_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign rawIn_isNaN = _rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _rawIn_out_isInf_T_1 = ~_rawIn_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _rawIn_out_isInf_T_2 = rawIn_isSpecial & _rawIn_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign rawIn_isInf = _rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _rawIn_out_sign_T = io_in_0[32]; // @[rawFloatFromRecFN.scala:59:25] assign rawIn_sign = _rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _rawIn_out_sExp_T = {1'h0, rawIn_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign rawIn_sExp = _rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _rawIn_out_sig_T = ~rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _rawIn_out_sig_T_1 = {1'h0, _rawIn_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _rawIn_out_sig_T_2 = io_in_0[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _rawIn_out_sig_T_3 = {_rawIn_out_sig_T_1, _rawIn_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign rawIn_sig = _rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44] assign io_out_0 = _io_out_T; // @[RecFNToRecFN.scala:44:5, :64:35] wire _io_exceptionFlags_T = rawIn_sig[22]; // @[rawFloatFromRecFN.scala:55:23] wire _io_exceptionFlags_T_1 = ~_io_exceptionFlags_T; // @[common.scala:82:{49,56}] wire _io_exceptionFlags_T_2 = rawIn_isNaN & _io_exceptionFlags_T_1; // @[rawFloatFromRecFN.scala:55:23] assign _io_exceptionFlags_T_3 = {_io_exceptionFlags_T_2, 4'h0}; // @[common.scala:82:46] assign io_exceptionFlags = _io_exceptionFlags_T_3; // @[RecFNToRecFN.scala:44:5, :65:54] assign io_out = io_out_0; // @[RecFNToRecFN.scala:44:5] endmodule

Generate the Verilog code corresponding to the following Chisel files. File InputUnit.scala: package constellation.router import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.{Field, Parameters} import freechips.rocketchip.util._ import constellation.channel._ import constellation.routing.{FlowRoutingBundle} import constellation.noc.{HasNoCParams} class AbstractInputUnitIO( val cParam: BaseChannelParams, val outParams: Seq[ChannelParams], val egressParams: Seq[EgressChannelParams], )(implicit val p: Parameters) extends Bundle with HasRouterOutputParams { val nodeId = cParam.destId val router_req = Decoupled(new RouteComputerReq) val router_resp = Input(new RouteComputerResp(outParams, egressParams)) val vcalloc_req = Decoupled(new VCAllocReq(cParam, outParams, egressParams)) val vcalloc_resp = Input(new VCAllocResp(outParams, egressParams)) val out_credit_available = Input(MixedVec(allOutParams.map { u => Vec(u.nVirtualChannels, Bool()) })) val salloc_req = Vec(cParam.destSpeedup, Decoupled(new SwitchAllocReq(outParams, egressParams))) val out = Vec(cParam.destSpeedup, Valid(new SwitchBundle(outParams, egressParams))) val debug = Output(new Bundle { val va_stall = UInt(log2Ceil(cParam.nVirtualChannels).W) val sa_stall = UInt(log2Ceil(cParam.nVirtualChannels).W) }) val block = Input(Bool()) } abstract class AbstractInputUnit( val cParam: BaseChannelParams, val outParams: Seq[ChannelParams], val egressParams: Seq[EgressChannelParams] )(implicit val p: Parameters) extends Module with HasRouterOutputParams with HasNoCParams { val nodeId = cParam.destId def io: AbstractInputUnitIO } class InputBuffer(cParam: ChannelParams)(implicit p: Parameters) extends Module { val nVirtualChannels = cParam.nVirtualChannels val io = IO(new Bundle { val enq = Flipped(Vec(cParam.srcSpeedup, Valid(new Flit(cParam.payloadBits)))) val deq = Vec(cParam.nVirtualChannels, Decoupled(new BaseFlit(cParam.payloadBits))) }) val useOutputQueues = cParam.useOutputQueues val delims = if (useOutputQueues) { cParam.virtualChannelParams.map(u => if (u.traversable) u.bufferSize else 0).scanLeft(0)(_+_) } else { // If no queuing, have to add an additional slot since head == tail implies empty // TODO this should be fixed, should use all slots available cParam.virtualChannelParams.map(u => if (u.traversable) u.bufferSize + 1 else 0).scanLeft(0)(_+_) } val starts = delims.dropRight(1).zipWithIndex.map { case (s,i) => if (cParam.virtualChannelParams(i).traversable) s else 0 } val ends = delims.tail.zipWithIndex.map { case (s,i) => if (cParam.virtualChannelParams(i).traversable) s else 0 } val fullSize = delims.last // Ugly case. Use multiple queues if ((cParam.srcSpeedup > 1 || cParam.destSpeedup > 1 || fullSize <= 1) || !cParam.unifiedBuffer) { require(useOutputQueues) val qs = cParam.virtualChannelParams.map(v => Module(new Queue(new BaseFlit(cParam.payloadBits), v.bufferSize))) qs.zipWithIndex.foreach { case (q,i) => val sel = io.enq.map(f => f.valid && f.bits.virt_channel_id === i.U) q.io.enq.valid := sel.orR q.io.enq.bits.head := Mux1H(sel, io.enq.map(_.bits.head)) q.io.enq.bits.tail := Mux1H(sel, io.enq.map(_.bits.tail)) q.io.enq.bits.payload := Mux1H(sel, io.enq.map(_.bits.payload)) io.deq(i) <> q.io.deq } } else { val mem = Mem(fullSize, new BaseFlit(cParam.payloadBits)) val heads = RegInit(VecInit(starts.map(_.U(log2Ceil(fullSize).W)))) val tails = RegInit(VecInit(starts.map(_.U(log2Ceil(fullSize).W)))) val empty = (heads zip tails).map(t => t._1 === t._2) val qs = Seq.fill(nVirtualChannels) { Module(new Queue(new BaseFlit(cParam.payloadBits), 1, pipe=true)) } qs.foreach(_.io.enq.valid := false.B) qs.foreach(_.io.enq.bits := DontCare) val vc_sel = UIntToOH(io.enq(0).bits.virt_channel_id) val flit = Wire(new BaseFlit(cParam.payloadBits)) val direct_to_q = (Mux1H(vc_sel, qs.map(_.io.enq.ready)) && Mux1H(vc_sel, empty)) && useOutputQueues.B flit.head := io.enq(0).bits.head flit.tail := io.enq(0).bits.tail flit.payload := io.enq(0).bits.payload when (io.enq(0).valid && !direct_to_q) { val tail = tails(io.enq(0).bits.virt_channel_id) mem.write(tail, flit) tails(io.enq(0).bits.virt_channel_id) := Mux( tail === Mux1H(vc_sel, ends.map(_ - 1).map(_ max 0).map(_.U)), Mux1H(vc_sel, starts.map(_.U)), tail + 1.U) } .elsewhen (io.enq(0).valid && direct_to_q) { for (i <- 0 until nVirtualChannels) { when (io.enq(0).bits.virt_channel_id === i.U) { qs(i).io.enq.valid := true.B qs(i).io.enq.bits := flit } } } if (useOutputQueues) { val can_to_q = (0 until nVirtualChannels).map { i => !empty(i) && qs(i).io.enq.ready } val to_q_oh = PriorityEncoderOH(can_to_q) val to_q = OHToUInt(to_q_oh) when (can_to_q.orR) { val head = Mux1H(to_q_oh, heads) heads(to_q) := Mux( head === Mux1H(to_q_oh, ends.map(_ - 1).map(_ max 0).map(_.U)), Mux1H(to_q_oh, starts.map(_.U)), head + 1.U) for (i <- 0 until nVirtualChannels) { when (to_q_oh(i)) { qs(i).io.enq.valid := true.B qs(i).io.enq.bits := mem.read(head) } } } for (i <- 0 until nVirtualChannels) { io.deq(i) <> qs(i).io.deq } } else { qs.map(_.io.deq.ready := false.B) val ready_sel = io.deq.map(_.ready) val fire = io.deq.map(_.fire) assert(PopCount(fire) <= 1.U) val head = Mux1H(fire, heads) when (fire.orR) { val fire_idx = OHToUInt(fire) heads(fire_idx) := Mux( head === Mux1H(fire, ends.map(_ - 1).map(_ max 0).map(_.U)), Mux1H(fire, starts.map(_.U)), head + 1.U) } val read_flit = mem.read(head) for (i <- 0 until nVirtualChannels) { io.deq(i).valid := !empty(i) io.deq(i).bits := read_flit } } } } class InputUnit(cParam: ChannelParams, outParams: Seq[ChannelParams], egressParams: Seq[EgressChannelParams], combineRCVA: Boolean, combineSAST: Boolean ) (implicit p: Parameters) extends AbstractInputUnit(cParam, outParams, egressParams)(p) { val nVirtualChannels = cParam.nVirtualChannels val virtualChannelParams = cParam.virtualChannelParams class InputUnitIO extends AbstractInputUnitIO(cParam, outParams, egressParams) { val in = Flipped(new Channel(cParam.asInstanceOf[ChannelParams])) } val io = IO(new InputUnitIO) val g_i :: g_r :: g_v :: g_a :: g_c :: Nil = Enum(5) class InputState extends Bundle { val g = UInt(3.W) val vc_sel = MixedVec(allOutParams.map { u => Vec(u.nVirtualChannels, Bool()) }) val flow = new FlowRoutingBundle val fifo_deps = UInt(nVirtualChannels.W) } val input_buffer = Module(new InputBuffer(cParam)) for (i <- 0 until cParam.srcSpeedup) { input_buffer.io.enq(i) := io.in.flit(i) } input_buffer.io.deq.foreach(_.ready := false.B) val route_arbiter = Module(new Arbiter( new RouteComputerReq, nVirtualChannels )) io.router_req <> route_arbiter.io.out val states = Reg(Vec(nVirtualChannels, new InputState)) val anyFifo = cParam.possibleFlows.map(_.fifo).reduce(_||_) val allFifo = cParam.possibleFlows.map(_.fifo).reduce(_&&_) if (anyFifo) { val idle_mask = VecInit(states.map(_.g === g_i)).asUInt for (s <- states) for (i <- 0 until nVirtualChannels) s.fifo_deps := s.fifo_deps & ~idle_mask } for (i <- 0 until cParam.srcSpeedup) { when (io.in.flit(i).fire && io.in.flit(i).bits.head) { val id = io.in.flit(i).bits.virt_channel_id assert(id < nVirtualChannels.U) assert(states(id).g === g_i) val at_dest = io.in.flit(i).bits.flow.egress_node === nodeId.U states(id).g := Mux(at_dest, g_v, g_r) states(id).vc_sel.foreach(_.foreach(_ := false.B)) for (o <- 0 until nEgress) { when (o.U === io.in.flit(i).bits.flow.egress_node_id) { states(id).vc_sel(o+nOutputs)(0) := true.B } } states(id).flow := io.in.flit(i).bits.flow if (anyFifo) { val fifo = cParam.possibleFlows.filter(_.fifo).map(_.isFlow(io.in.flit(i).bits.flow)).toSeq.orR states(id).fifo_deps := VecInit(states.zipWithIndex.map { case (s, j) => s.g =/= g_i && s.flow.asUInt === io.in.flit(i).bits.flow.asUInt && j.U =/= id }).asUInt } } } (route_arbiter.io.in zip states).zipWithIndex.map { case ((i,s),idx) => if (virtualChannelParams(idx).traversable) { i.valid := s.g === g_r i.bits.flow := s.flow i.bits.src_virt_id := idx.U when (i.fire) { s.g := g_v } } else { i.valid := false.B i.bits := DontCare } } when (io.router_req.fire) { val id = io.router_req.bits.src_virt_id assert(states(id).g === g_r) states(id).g := g_v for (i <- 0 until nVirtualChannels) { when (i.U === id) { states(i).vc_sel := io.router_resp.vc_sel } } } val mask = RegInit(0.U(nVirtualChannels.W)) val vcalloc_reqs = Wire(Vec(nVirtualChannels, new VCAllocReq(cParam, outParams, egressParams))) val vcalloc_vals = Wire(Vec(nVirtualChannels, Bool())) val vcalloc_filter = PriorityEncoderOH(Cat(vcalloc_vals.asUInt, vcalloc_vals.asUInt & ~mask)) val vcalloc_sel = vcalloc_filter(nVirtualChannels-1,0) | (vcalloc_filter >> nVirtualChannels) // Prioritize incoming packetes when (io.router_req.fire) { mask := (1.U << io.router_req.bits.src_virt_id) - 1.U } .elsewhen (vcalloc_vals.orR) { mask := Mux1H(vcalloc_sel, (0 until nVirtualChannels).map { w => ~(0.U((w+1).W)) }) } io.vcalloc_req.valid := vcalloc_vals.orR io.vcalloc_req.bits := Mux1H(vcalloc_sel, vcalloc_reqs) states.zipWithIndex.map { case (s,idx) => if (virtualChannelParams(idx).traversable) { vcalloc_vals(idx) := s.g === g_v && s.fifo_deps === 0.U vcalloc_reqs(idx).in_vc := idx.U vcalloc_reqs(idx).vc_sel := s.vc_sel vcalloc_reqs(idx).flow := s.flow when (vcalloc_vals(idx) && vcalloc_sel(idx) && io.vcalloc_req.ready) { s.g := g_a } if (combineRCVA) { when (route_arbiter.io.in(idx).fire) { vcalloc_vals(idx) := true.B vcalloc_reqs(idx).vc_sel := io.router_resp.vc_sel } } } else { vcalloc_vals(idx) := false.B vcalloc_reqs(idx) := DontCare } } io.debug.va_stall := PopCount(vcalloc_vals) - io.vcalloc_req.ready when (io.vcalloc_req.fire) { for (i <- 0 until nVirtualChannels) { when (vcalloc_sel(i)) { states(i).vc_sel := io.vcalloc_resp.vc_sel states(i).g := g_a if (!combineRCVA) { assert(states(i).g === g_v) } } } } val salloc_arb = Module(new SwitchArbiter( nVirtualChannels, cParam.destSpeedup, outParams, egressParams )) (states zip salloc_arb.io.in).zipWithIndex.map { case ((s,r),i) => if (virtualChannelParams(i).traversable) { val credit_available = (s.vc_sel.asUInt & io.out_credit_available.asUInt) =/= 0.U r.valid := s.g === g_a && credit_available && input_buffer.io.deq(i).valid r.bits.vc_sel := s.vc_sel val deq_tail = input_buffer.io.deq(i).bits.tail r.bits.tail := deq_tail when (r.fire && deq_tail) { s.g := g_i } input_buffer.io.deq(i).ready := r.ready } else { r.valid := false.B r.bits := DontCare } } io.debug.sa_stall := PopCount(salloc_arb.io.in.map(r => r.valid && !r.ready)) io.salloc_req <> salloc_arb.io.out when (io.block) { salloc_arb.io.out.foreach(_.ready := false.B) io.salloc_req.foreach(_.valid := false.B) } class OutBundle extends Bundle { val valid = Bool() val vid = UInt(virtualChannelBits.W) val out_vid = UInt(log2Up(allOutParams.map(_.nVirtualChannels).max).W) val flit = new Flit(cParam.payloadBits) } val salloc_outs = if (combineSAST) { Wire(Vec(cParam.destSpeedup, new OutBundle)) } else { Reg(Vec(cParam.destSpeedup, new OutBundle)) } io.in.credit_return := salloc_arb.io.out.zipWithIndex.map { case (o, i) => Mux(o.fire, salloc_arb.io.chosen_oh(i), 0.U) }.reduce(_|_) io.in.vc_free := salloc_arb.io.out.zipWithIndex.map { case (o, i) => Mux(o.fire && Mux1H(salloc_arb.io.chosen_oh(i), input_buffer.io.deq.map(_.bits.tail)), salloc_arb.io.chosen_oh(i), 0.U) }.reduce(_|_) for (i <- 0 until cParam.destSpeedup) { val salloc_out = salloc_outs(i) salloc_out.valid := salloc_arb.io.out(i).fire salloc_out.vid := OHToUInt(salloc_arb.io.chosen_oh(i)) val vc_sel = Mux1H(salloc_arb.io.chosen_oh(i), states.map(_.vc_sel)) val channel_oh = vc_sel.map(_.reduce(_||_)).toSeq val virt_channel = Mux1H(channel_oh, vc_sel.map(v => OHToUInt(v)).toSeq) when (salloc_arb.io.out(i).fire) { salloc_out.out_vid := virt_channel salloc_out.flit.payload := Mux1H(salloc_arb.io.chosen_oh(i), input_buffer.io.deq.map(_.bits.payload)) salloc_out.flit.head := Mux1H(salloc_arb.io.chosen_oh(i), input_buffer.io.deq.map(_.bits.head)) salloc_out.flit.tail := Mux1H(salloc_arb.io.chosen_oh(i), input_buffer.io.deq.map(_.bits.tail)) salloc_out.flit.flow := Mux1H(salloc_arb.io.chosen_oh(i), states.map(_.flow)) } .otherwise { salloc_out.out_vid := DontCare salloc_out.flit := DontCare } salloc_out.flit.virt_channel_id := DontCare // this gets set in the switch io.out(i).valid := salloc_out.valid io.out(i).bits.flit := salloc_out.flit io.out(i).bits.out_virt_channel := salloc_out.out_vid } def filterVCSel(sel: MixedVec[Vec[Bool]], srcV: Int) = { if (virtualChannelParams(srcV).traversable) { outParams.zipWithIndex.map { case (oP, oI) => (0 until oP.nVirtualChannels).map { oV => var allow = false virtualChannelParams(srcV).possibleFlows.foreach { pI => allow = allow || routingRelation( cParam.channelRoutingInfos(srcV), oP.channelRoutingInfos(oV), pI ) } if (!allow) sel(oI)(oV) := false.B } } } } (0 until nVirtualChannels).map { i => if (!virtualChannelParams(i).traversable) states(i) := DontCare filterVCSel(states(i).vc_sel, i) } when (reset.asBool) { states.foreach(_.g := g_i) } }

module InputUnit_80( // @[InputUnit.scala:158:7] input clock, // @[InputUnit.scala:158:7] input reset, // @[InputUnit.scala:158:7] input io_vcalloc_req_ready, // @[InputUnit.scala:170:14] output io_vcalloc_req_valid, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_3_0, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_2_0, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_1_0, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_3_0, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_2_0, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_1_0, // @[InputUnit.scala:170:14] input io_out_credit_available_3_0, // @[InputUnit.scala:170:14] input io_out_credit_available_2_0, // @[InputUnit.scala:170:14] input io_out_credit_available_1_0, // @[InputUnit.scala:170:14] input io_out_credit_available_0_1, // @[InputUnit.scala:170:14] input io_salloc_req_0_ready, // @[InputUnit.scala:170:14] output io_salloc_req_0_valid, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_3_0, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_2_0, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_1_0, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_tail, // @[InputUnit.scala:170:14] output io_out_0_valid, // @[InputUnit.scala:170:14] output io_out_0_bits_flit_head, // @[InputUnit.scala:170:14] output io_out_0_bits_flit_tail, // @[InputUnit.scala:170:14] output [72:0] io_out_0_bits_flit_payload, // @[InputUnit.scala:170:14] output [2:0] io_out_0_bits_flit_flow_vnet_id, // @[InputUnit.scala:170:14] output [4:0] io_out_0_bits_flit_flow_ingress_node, // @[InputUnit.scala:170:14] output [1:0] io_out_0_bits_flit_flow_ingress_node_id, // @[InputUnit.scala:170:14] output [4:0] io_out_0_bits_flit_flow_egress_node, // @[InputUnit.scala:170:14] output [1:0] io_out_0_bits_flit_flow_egress_node_id, // @[InputUnit.scala:170:14] output [2:0] io_debug_va_stall, // @[InputUnit.scala:170:14] output [2:0] io_debug_sa_stall, // @[InputUnit.scala:170:14] input io_in_flit_0_valid, // @[InputUnit.scala:170:14] input io_in_flit_0_bits_head, // @[InputUnit.scala:170:14] input io_in_flit_0_bits_tail, // @[InputUnit.scala:170:14] input [72:0] io_in_flit_0_bits_payload, // @[InputUnit.scala:170:14] input [2:0] io_in_flit_0_bits_flow_vnet_id, // @[InputUnit.scala:170:14] input [4:0] io_in_flit_0_bits_flow_ingress_node, // @[InputUnit.scala:170:14] input [1:0] io_in_flit_0_bits_flow_ingress_node_id, // @[InputUnit.scala:170:14] input [4:0] io_in_flit_0_bits_flow_egress_node, // @[InputUnit.scala:170:14] input [1:0] io_in_flit_0_bits_flow_egress_node_id, // @[InputUnit.scala:170:14] input [2:0] io_in_flit_0_bits_virt_channel_id, // @[InputUnit.scala:170:14] output [4:0] io_in_credit_return, // @[InputUnit.scala:170:14] output [4:0] io_in_vc_free // @[InputUnit.scala:170:14] ); wire vcalloc_vals_4; // @[InputUnit.scala:266:32] wire _salloc_arb_io_in_4_ready; // @[InputUnit.scala:296:26] wire _salloc_arb_io_out_0_valid; // @[InputUnit.scala:296:26] wire [4:0] _salloc_arb_io_chosen_oh_0; // @[InputUnit.scala:296:26] wire _route_arbiter_io_in_4_ready; // @[InputUnit.scala:187:29] wire _route_arbiter_io_out_valid; // @[InputUnit.scala:187:29] wire [2:0] _route_arbiter_io_out_bits_src_virt_id; // @[InputUnit.scala:187:29] wire _input_buffer_io_deq_0_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_0_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_0_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_1_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_1_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_1_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_2_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_2_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_2_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_3_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_3_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_3_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_4_valid; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_4_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_4_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_4_bits_payload; // @[InputUnit.scala:181:28] reg [2:0] states_4_g; // @[InputUnit.scala:192:19] reg states_4_vc_sel_3_0; // @[InputUnit.scala:192:19] reg states_4_vc_sel_2_0; // @[InputUnit.scala:192:19] reg states_4_vc_sel_1_0; // @[InputUnit.scala:192:19] reg [2:0] states_4_flow_vnet_id; // @[InputUnit.scala:192:19] reg [4:0] states_4_flow_ingress_node; // @[InputUnit.scala:192:19] reg [1:0] states_4_flow_ingress_node_id; // @[InputUnit.scala:192:19] reg [4:0] states_4_flow_egress_node; // @[InputUnit.scala:192:19] reg [1:0] states_4_flow_egress_node_id; // @[InputUnit.scala:192:19] wire _GEN = io_in_flit_0_valid & io_in_flit_0_bits_head; // @[InputUnit.scala:205:30] wire route_arbiter_io_in_4_valid = states_4_g == 3'h1; // @[InputUnit.scala:192:19, :229:22] reg [4:0] mask; // @[InputUnit.scala:250:21] wire [4:0] _vcalloc_filter_T_3 = {vcalloc_vals_4, 4'h0} & ~mask; // @[InputUnit.scala:158:7, :250:21, :253:{80,87,89}, :266:32] wire [9:0] vcalloc_filter = _vcalloc_filter_T_3[0] ? 10'h1 : _vcalloc_filter_T_3[1] ? 10'h2 : _vcalloc_filter_T_3[2] ? 10'h4 : _vcalloc_filter_T_3[3] ? 10'h8 : _vcalloc_filter_T_3[4] ? 10'h10 : {vcalloc_vals_4, 9'h0}; // @[OneHot.scala:85:71] wire [4:0] vcalloc_sel = vcalloc_filter[4:0] | vcalloc_filter[9:5]; // @[Mux.scala:50:70] assign vcalloc_vals_4 = states_4_g == 3'h2; // @[InputUnit.scala:192:19, :266:32] wire _GEN_0 = io_vcalloc_req_ready & vcalloc_vals_4; // @[Decoupled.scala:51:35] wire _GEN_1 = _GEN_0 & vcalloc_sel[4]; // @[Mux.scala:32:36]

Generate the Verilog code corresponding to the following Chisel files. File ShiftReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ // Similar to the Chisel ShiftRegister but allows the user to suggest a // name to the registers that get instantiated, and // to provide a reset value. object ShiftRegInit { def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T = (0 until n).foldRight(in) { case (i, next) => { val r = RegNext(next, init) name.foreach { na => r.suggestName(s"${na}_${i}") } r } } } /** These wrap behavioral * shift registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * The different types vary in their reset behavior: * AsyncResetShiftReg -- Asynchronously reset register array * A W(width) x D(depth) sized array is constructed from D instantiations of a * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg, * but only used for timing applications */ abstract class AbstractPipelineReg(w: Int = 1) extends Module { val io = IO(new Bundle { val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) } ) } object AbstractPipelineReg { def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = { val chain = Module(gen) name.foreach{ chain.suggestName(_) } chain.io.d := in.asUInt chain.io.q.asTypeOf(in) } } class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) { require(depth > 0, "Depth must be greater than 0.") override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}" val chain = List.tabulate(depth) { i => Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}") } chain.last.io.d := io.d chain.last.io.en := true.B (chain.init zip chain.tail).foreach { case (sink, source) => sink.io.d := source.io.q sink.io.en := true.B } io.q := chain.head.io.q } object AsyncResetShiftReg { def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name) def apply [T <: Data](in: T, depth: Int, name: Option[String]): T = apply(in, depth, 0, name) def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T = apply(in, depth, init.litValue.toInt, name) def apply [T <: Data](in: T, depth: Int, init: T): T = apply (in, depth, init.litValue.toInt, None) } File AsyncQueue.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ case class AsyncQueueParams( depth: Int = 8, sync: Int = 3, safe: Boolean = true, // If safe is true, then effort is made to resynchronize the crossing indices when either side is reset. // This makes it safe/possible to reset one side of the crossing (but not the other) when the queue is empty. narrow: Boolean = false) // If narrow is true then the read mux is moved to the source side of the crossing. // This reduces the number of level shifters in the case where the clock crossing is also a voltage crossing, // at the expense of a combinational path from the sink to the source and back to the sink. { require (depth > 0 && isPow2(depth)) require (sync >= 2) val bits = log2Ceil(depth) val wires = if (narrow) 1 else depth } object AsyncQueueParams { // When there is only one entry, we don't need narrow. def singleton(sync: Int = 3, safe: Boolean = true) = AsyncQueueParams(1, sync, safe, false) } class AsyncBundleSafety extends Bundle { val ridx_valid = Input (Bool()) val widx_valid = Output(Bool()) val source_reset_n = Output(Bool()) val sink_reset_n = Input (Bool()) } class AsyncBundle[T <: Data](private val gen: T, val params: AsyncQueueParams = AsyncQueueParams()) extends Bundle { // Data-path synchronization val mem = Output(Vec(params.wires, gen)) val ridx = Input (UInt((params.bits+1).W)) val widx = Output(UInt((params.bits+1).W)) val index = params.narrow.option(Input(UInt(params.bits.W))) // Signals used to self-stabilize a safe AsyncQueue val safe = params.safe.option(new AsyncBundleSafety) } object GrayCounter { def apply(bits: Int, increment: Bool = true.B, clear: Bool = false.B, name: String = "binary"): UInt = { val incremented = Wire(UInt(bits.W)) val binary = RegNext(next=incremented, init=0.U).suggestName(name) incremented := Mux(clear, 0.U, binary + increment.asUInt) incremented ^ (incremented >> 1) } } class AsyncValidSync(sync: Int, desc: String) extends RawModule { val io = IO(new Bundle { val in = Input(Bool()) val out = Output(Bool()) }) val clock = IO(Input(Clock())) val reset = IO(Input(AsyncReset())) withClockAndReset(clock, reset){ io.out := AsyncResetSynchronizerShiftReg(io.in, sync, Some(desc)) } } class AsyncQueueSource[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module { override def desiredName = s"AsyncQueueSource_${gen.typeName}" val io = IO(new Bundle { // These come from the source domain val enq = Flipped(Decoupled(gen)) // These cross to the sink clock domain val async = new AsyncBundle(gen, params) }) val bits = params.bits val sink_ready = WireInit(true.B) val mem = Reg(Vec(params.depth, gen)) // This does NOT need to be reset at all. val widx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.enq.fire, !sink_ready, "widx_bin")) val ridx = AsyncResetSynchronizerShiftReg(io.async.ridx, params.sync, Some("ridx_gray")) val ready = sink_ready && widx =/= (ridx ^ (params.depth | params.depth >> 1).U) val index = if (bits == 0) 0.U else io.async.widx(bits-1, 0) ^ (io.async.widx(bits, bits) << (bits-1)) when (io.enq.fire) { mem(index) := io.enq.bits } val ready_reg = withReset(reset.asAsyncReset)(RegNext(next=ready, init=false.B).suggestName("ready_reg")) io.enq.ready := ready_reg && sink_ready val widx_reg = withReset(reset.asAsyncReset)(RegNext(next=widx, init=0.U).suggestName("widx_gray")) io.async.widx := widx_reg io.async.index match { case Some(index) => io.async.mem(0) := mem(index) case None => io.async.mem := mem } io.async.safe.foreach { sio => val source_valid_0 = Module(new AsyncValidSync(params.sync, "source_valid_0")) val source_valid_1 = Module(new AsyncValidSync(params.sync, "source_valid_1")) val sink_extend = Module(new AsyncValidSync(params.sync, "sink_extend")) val sink_valid = Module(new AsyncValidSync(params.sync, "sink_valid")) source_valid_0.reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset source_valid_1.reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset sink_extend .reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset sink_valid .reset := reset.asAsyncReset source_valid_0.clock := clock source_valid_1.clock := clock sink_extend .clock := clock sink_valid .clock := clock source_valid_0.io.in := true.B source_valid_1.io.in := source_valid_0.io.out sio.widx_valid := source_valid_1.io.out sink_extend.io.in := sio.ridx_valid sink_valid.io.in := sink_extend.io.out sink_ready := sink_valid.io.out sio.source_reset_n := !reset.asBool // Assert that if there is stuff in the queue, then reset cannot happen // Impossible to write because dequeue can occur on the receiving side, // then reset allowed to happen, but write side cannot know that dequeue // occurred. // TODO: write some sort of sanity check assertion for users // that denote don't reset when there is activity // assert (!(reset || !sio.sink_reset_n) || !io.enq.valid, "Enqueue while sink is reset and AsyncQueueSource is unprotected") // assert (!reset_rise || prev_idx_match.asBool, "Sink reset while AsyncQueueSource not empty") } } class AsyncQueueSink[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module { override def desiredName = s"AsyncQueueSink_${gen.typeName}" val io = IO(new Bundle { // These come from the sink domain val deq = Decoupled(gen) // These cross to the source clock domain val async = Flipped(new AsyncBundle(gen, params)) }) val bits = params.bits val source_ready = WireInit(true.B) val ridx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.deq.fire, !source_ready, "ridx_bin")) val widx = AsyncResetSynchronizerShiftReg(io.async.widx, params.sync, Some("widx_gray")) val valid = source_ready && ridx =/= widx // The mux is safe because timing analysis ensures ridx has reached the register // On an ASIC, changes to the unread location cannot affect the selected value // On an FPGA, only one input changes at a time => mem updates don't cause glitches // The register only latches when the selected valued is not being written val index = if (bits == 0) 0.U else ridx(bits-1, 0) ^ (ridx(bits, bits) << (bits-1)) io.async.index.foreach { _ := index } // This register does not NEED to be reset, as its contents will not // be considered unless the asynchronously reset deq valid register is set. // It is possible that bits latches when the source domain is reset / has power cut // This is safe, because isolation gates brought mem low before the zeroed widx reached us val deq_bits_nxt = io.async.mem(if (params.narrow) 0.U else index) io.deq.bits := ClockCrossingReg(deq_bits_nxt, en = valid, doInit = false, name = Some("deq_bits_reg")) val valid_reg = withReset(reset.asAsyncReset)(RegNext(next=valid, init=false.B).suggestName("valid_reg")) io.deq.valid := valid_reg && source_ready val ridx_reg = withReset(reset.asAsyncReset)(RegNext(next=ridx, init=0.U).suggestName("ridx_gray")) io.async.ridx := ridx_reg io.async.safe.foreach { sio => val sink_valid_0 = Module(new AsyncValidSync(params.sync, "sink_valid_0")) val sink_valid_1 = Module(new AsyncValidSync(params.sync, "sink_valid_1")) val source_extend = Module(new AsyncValidSync(params.sync, "source_extend")) val source_valid = Module(new AsyncValidSync(params.sync, "source_valid")) sink_valid_0 .reset := (reset.asBool || !sio.source_reset_n).asAsyncReset sink_valid_1 .reset := (reset.asBool || !sio.source_reset_n).asAsyncReset source_extend.reset := (reset.asBool || !sio.source_reset_n).asAsyncReset source_valid .reset := reset.asAsyncReset sink_valid_0 .clock := clock sink_valid_1 .clock := clock source_extend.clock := clock source_valid .clock := clock sink_valid_0.io.in := true.B sink_valid_1.io.in := sink_valid_0.io.out sio.ridx_valid := sink_valid_1.io.out source_extend.io.in := sio.widx_valid source_valid.io.in := source_extend.io.out source_ready := source_valid.io.out sio.sink_reset_n := !reset.asBool // TODO: write some sort of sanity check assertion for users // that denote don't reset when there is activity // // val reset_and_extend = !source_ready || !sio.source_reset_n || reset.asBool // val reset_and_extend_prev = RegNext(reset_and_extend, true.B) // val reset_rise = !reset_and_extend_prev && reset_and_extend // val prev_idx_match = AsyncResetReg(updateData=(io.async.widx===io.async.ridx), resetData=0) // assert (!reset_rise || prev_idx_match.asBool, "Source reset while AsyncQueueSink not empty") } } object FromAsyncBundle { // Sometimes it makes sense for the sink to have different sync than the source def apply[T <: Data](x: AsyncBundle[T]): DecoupledIO[T] = apply(x, x.params.sync) def apply[T <: Data](x: AsyncBundle[T], sync: Int): DecoupledIO[T] = { val sink = Module(new AsyncQueueSink(chiselTypeOf(x.mem(0)), x.params.copy(sync = sync))) sink.io.async <> x sink.io.deq } } object ToAsyncBundle { def apply[T <: Data](x: ReadyValidIO[T], params: AsyncQueueParams = AsyncQueueParams()): AsyncBundle[T] = { val source = Module(new AsyncQueueSource(chiselTypeOf(x.bits), params)) source.io.enq <> x source.io.async } } class AsyncQueue[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Crossing[T] { val io = IO(new CrossingIO(gen)) val source = withClockAndReset(io.enq_clock, io.enq_reset) { Module(new AsyncQueueSource(gen, params)) } val sink = withClockAndReset(io.deq_clock, io.deq_reset) { Module(new AsyncQueueSink (gen, params)) } source.io.enq <> io.enq io.deq <> sink.io.deq sink.io.async <> source.io.async }

module AsyncValidSync_72( // @[AsyncQueue.scala:58:7] output io_out, // @[AsyncQueue.scala:59:14] input clock, // @[AsyncQueue.scala:63:17] input reset // @[AsyncQueue.scala:64:17] ); wire io_in = 1'h1; // @[ShiftReg.scala:45:23] wire _io_out_WIRE; // @[ShiftReg.scala:48:24] wire io_out_0; // @[AsyncQueue.scala:58:7] assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24] AsyncResetSynchronizerShiftReg_w1_d3_i0_83 io_out_source_valid_0 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (reset), .io_q (_io_out_WIRE) ); // @[ShiftReg.scala:45:23] assign io_out = io_out_0; // @[AsyncQueue.scala:58:7] endmodule

Generate the Verilog code corresponding to the following Chisel files. File Monitor.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceLine import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import freechips.rocketchip.diplomacy.EnableMonitors import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode} import freechips.rocketchip.util.PlusArg case class TLMonitorArgs(edge: TLEdge) abstract class TLMonitorBase(args: TLMonitorArgs) extends Module { val io = IO(new Bundle { val in = Input(new TLBundle(args.edge.bundle)) }) def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit legalize(io.in, args.edge, reset) } object TLMonitor { def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = { if (enable) { EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) } } else { node } } } class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args) { require (args.edge.params(TLMonitorStrictMode) || (! args.edge.params(TestplanTestType).formal)) val cover_prop_class = PropertyClass.Default //Like assert but can flip to being an assumption for formal verification def monAssert(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir, cond, message, PropertyClass.Default) } def assume(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir.flip, cond, message, PropertyClass.Default) } def extra = { args.edge.sourceInfo match { case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)" case _ => "" } } def visible(address: UInt, source: UInt, edge: TLEdge) = edge.client.clients.map { c => !c.sourceId.contains(source) || c.visibility.map(_.contains(address)).reduce(_ || _) }.reduce(_ && _) def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = { //switch this flag to turn on diplomacy in error messages def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n" monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra) // Reuse these subexpressions to save some firrtl lines val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility") //The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B //TODO: check for acquireT? when (bundle.opcode === TLMessages.AcquireBlock) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra) } when (bundle.opcode === TLMessages.AcquirePerm) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra) monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra) monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra) monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra) } } def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = { monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra) monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility") // Reuse these subexpressions to save some firrtl lines val address_ok = edge.manager.containsSafe(edge.address(bundle)) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source when (bundle.opcode === TLMessages.Probe) { assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra) assume (address_ok, "'B' channel Probe carries unmanaged address" + extra) assume (legal_source, "'B' channel Probe carries source that is not first source" + extra) assume (is_aligned, "'B' channel Probe address not aligned to size" + extra) assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra) assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra) assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra) monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra) monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra) monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra) monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra) } } def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = { monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val address_ok = edge.manager.containsSafe(edge.address(bundle)) monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility") when (bundle.opcode === TLMessages.ProbeAck) { monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra) } when (bundle.opcode === TLMessages.ProbeAckData) { monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.Release) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra) monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra) } when (bundle.opcode === TLMessages.ReleaseData) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.AccessAck) { monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra) } when (bundle.opcode === TLMessages.HintAck) { monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra) } } def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = { assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val sink_ok = bundle.sink < edge.manager.endSinkId.U val deny_put_ok = edge.manager.mayDenyPut.B val deny_get_ok = edge.manager.mayDenyGet.B when (bundle.opcode === TLMessages.ReleaseAck) { assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra) assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra) assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra) } when (bundle.opcode === TLMessages.Grant) { assume (source_ok, "'D' channel Grant carries invalid source ID" + extra) assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra) assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel Grant is denied" + extra) } when (bundle.opcode === TLMessages.GrantData) { assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra) assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra) assume (!bundle.denied || bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra) assume (deny_get_ok || !bundle.denied, "'D' channel GrantData is denied" + extra) } when (bundle.opcode === TLMessages.AccessAck) { assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel AccessAck is denied" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra) assume (!bundle.denied || bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra) assume (deny_get_ok || !bundle.denied, "'D' channel AccessAckData is denied" + extra) } when (bundle.opcode === TLMessages.HintAck) { assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel HintAck is denied" + extra) } } def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = { val sink_ok = bundle.sink < edge.manager.endSinkId.U monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra) } def legalizeFormat(bundle: TLBundle, edge: TLEdge) = { when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) } when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) } when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) } when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) } } else { monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra) monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra) monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra) } } def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = { val a_first = edge.first(a.bits, a.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (a.valid && !a_first) { monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra) monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra) monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra) monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra) monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra) } when (a.fire && a_first) { opcode := a.bits.opcode param := a.bits.param size := a.bits.size source := a.bits.source address := a.bits.address } } def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = { val b_first = edge.first(b.bits, b.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (b.valid && !b_first) { monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra) monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra) monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra) monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra) monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra) } when (b.fire && b_first) { opcode := b.bits.opcode param := b.bits.param size := b.bits.size source := b.bits.source address := b.bits.address } } def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = { // Symbolic variable val sym_source = Wire(UInt(edge.client.endSourceId.W)) // TODO: Connect sym_source to a fixed value for simulation and to a // free wire in formal sym_source := 0.U // Type casting Int to UInt val maxSourceId = Wire(UInt(edge.client.endSourceId.W)) maxSourceId := edge.client.endSourceId.U // Delayed verison of sym_source val sym_source_d = Reg(UInt(edge.client.endSourceId.W)) sym_source_d := sym_source // These will be constraints for FV setup Property( MonitorDirection.Monitor, (sym_source === sym_source_d), "sym_source should remain stable", PropertyClass.Default) Property( MonitorDirection.Monitor, (sym_source <= maxSourceId), "sym_source should take legal value", PropertyClass.Default) val my_resp_pend = RegInit(false.B) val my_opcode = Reg(UInt()) val my_size = Reg(UInt()) val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire) val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire) val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source) val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source) val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat) val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend) when (my_set_resp_pend) { my_resp_pend := true.B } .elsewhen (my_clr_resp_pend) { my_resp_pend := false.B } when (my_a_first_beat) { my_opcode := bundle.a.bits.opcode my_size := bundle.a.bits.size } val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size) val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode) val my_resp_opcode_legal = Wire(Bool()) when ((my_resp_opcode === TLMessages.Get) || (my_resp_opcode === TLMessages.ArithmeticData) || (my_resp_opcode === TLMessages.LogicalData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData) } .elsewhen ((my_resp_opcode === TLMessages.PutFullData) || (my_resp_opcode === TLMessages.PutPartialData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck) } .otherwise { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck) } monAssert (IfThen(my_resp_pend, !my_a_first_beat), "Request message should not be sent with a source ID, for which a response message" + "is already pending (not received until current cycle) for a prior request message" + "with the same source ID" + extra) assume (IfThen(my_clr_resp_pend, (my_set_resp_pend || my_resp_pend)), "Response message should be accepted with a source ID only if a request message with the" + "same source ID has been accepted or is being accepted in the current cycle" + extra) assume (IfThen(my_d_first_beat, (my_a_first_beat || my_resp_pend)), "Response message should be sent with a source ID only if a request message with the" + "same source ID has been accepted or is being sent in the current cycle" + extra) assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)), "If d_valid is 1, then d_size should be same as a_size of the corresponding request" + "message" + extra) assume (IfThen(my_d_first_beat, my_resp_opcode_legal), "If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" + "request message" + extra) } def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = { val c_first = edge.first(c.bits, c.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (c.valid && !c_first) { monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra) monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra) monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra) monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra) monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra) } when (c.fire && c_first) { opcode := c.bits.opcode param := c.bits.param size := c.bits.size source := c.bits.source address := c.bits.address } } def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = { val d_first = edge.first(d.bits, d.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val sink = Reg(UInt()) val denied = Reg(Bool()) when (d.valid && !d_first) { assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra) assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra) assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra) assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra) assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra) assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra) } when (d.fire && d_first) { opcode := d.bits.opcode param := d.bits.param size := d.bits.size source := d.bits.source sink := d.bits.sink denied := d.bits.denied } } def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = { legalizeMultibeatA(bundle.a, edge) legalizeMultibeatD(bundle.d, edge) if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { legalizeMultibeatB(bundle.b, edge) legalizeMultibeatC(bundle.c, edge) } } //This is left in for almond which doesn't adhere to the tilelink protocol @deprecated("Use legalizeADSource instead if possible","") def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.client.endSourceId.W)) val a_first = edge.first(bundle.a.bits, bundle.a.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val a_set = WireInit(0.U(edge.client.endSourceId.W)) when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) assume((a_set | inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra) } if (edge.manager.minLatency > 0) { assume(a_set =/= d_clr || !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight | a_set) & ~d_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") assert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = { val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size) val log_a_size_bus_size = log2Ceil(a_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error inflight.suggestName("inflight") val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) inflight_opcodes.suggestName("inflight_opcodes") val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) inflight_sizes.suggestName("inflight_sizes") val a_first = edge.first(bundle.a.bits, bundle.a.fire) a_first.suggestName("a_first") val d_first = edge.first(bundle.d.bits, bundle.d.fire) d_first.suggestName("d_first") val a_set = WireInit(0.U(edge.client.endSourceId.W)) val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) a_set.suggestName("a_set") a_set_wo_ready.suggestName("a_set_wo_ready") val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) a_opcodes_set.suggestName("a_opcodes_set") val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) a_sizes_set.suggestName("a_sizes_set") val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W)) a_opcode_lookup.suggestName("a_opcode_lookup") a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W)) a_size_lookup.suggestName("a_size_lookup") a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant)) val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant)) val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W)) a_opcodes_set_interm.suggestName("a_opcodes_set_interm") val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W)) a_sizes_set_interm.suggestName("a_sizes_set_interm") when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) { a_set_wo_ready := UIntToOH(bundle.a.bits.source) } when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) | 1.U a_sizes_set_interm := (bundle.a.bits.size << 1.U) | 1.U a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U) a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U) monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) d_opcodes_clr.suggestName("d_opcodes_clr") val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) || (bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra) assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) || (bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra) assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) { assume((!bundle.d.ready) || bundle.a.ready, "ready check") } if (edge.manager.minLatency > 0) { assume(a_set_wo_ready =/= d_clr_wo_ready || !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight | a_set) & ~d_clr inflight_opcodes := (inflight_opcodes | a_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes | a_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = { val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size) val log_c_size_bus_size = log2Ceil(c_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) inflight.suggestName("inflight") inflight_opcodes.suggestName("inflight_opcodes") inflight_sizes.suggestName("inflight_sizes") val c_first = edge.first(bundle.c.bits, bundle.c.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) c_first.suggestName("c_first") d_first.suggestName("d_first") val c_set = WireInit(0.U(edge.client.endSourceId.W)) val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) c_set.suggestName("c_set") c_set_wo_ready.suggestName("c_set_wo_ready") c_opcodes_set.suggestName("c_opcodes_set") c_sizes_set.suggestName("c_sizes_set") val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W)) val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W)) c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U c_opcode_lookup.suggestName("c_opcode_lookup") c_size_lookup.suggestName("c_size_lookup") val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W)) val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W)) c_opcodes_set_interm.suggestName("c_opcodes_set_interm") c_sizes_set_interm.suggestName("c_sizes_set_interm") when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) { c_set_wo_ready := UIntToOH(bundle.c.bits.source) } when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) { c_set := UIntToOH(bundle.c.bits.source) c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) | 1.U c_sizes_set_interm := (bundle.c.bits.size << 1.U) | 1.U c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U) c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U) monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra) } val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck || bundle.c.bits.opcode === TLMessages.ProbeAckData val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") d_opcodes_clr.suggestName("d_opcodes_clr") d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) { assume((!bundle.d.ready) || bundle.c.ready, "ready check") } if (edge.manager.minLatency > 0) { when (c_set_wo_ready.orR) { assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra) } } inflight := (inflight | c_set) & ~d_clr inflight_opcodes := (inflight_opcodes | c_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes | c_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.c.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.manager.endSinkId.W)) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val e_first = true.B val d_set = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) { d_set := UIntToOH(bundle.d.bits.sink) assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra) } val e_clr = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) { e_clr := UIntToOH(bundle.e.bits.sink) monAssert((d_set | inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra) } // edge.client.minLatency applies to BC, not DE inflight := (inflight | d_set) & ~e_clr } def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = { val sourceBits = log2Ceil(edge.client.endSourceId) val tooBig = 14 // >16kB worth of flight information gets to be too much if (sourceBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked") } else { if (args.edge.params(TestplanTestType).simulation) { if (args.edge.params(TLMonitorStrictMode)) { legalizeADSource(bundle, edge) legalizeCDSource(bundle, edge) } else { legalizeADSourceOld(bundle, edge) } } if (args.edge.params(TestplanTestType).formal) { legalizeADSourceFormal(bundle, edge) } } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { // legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize... val sinkBits = log2Ceil(edge.manager.endSinkId) if (sinkBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked") } else { legalizeDESink(bundle, edge) } } } def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = { legalizeFormat (bundle, edge) legalizeMultibeat (bundle, edge) legalizeUnique (bundle, edge) } } File Misc.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import scala.math._ class ParameterizedBundle(implicit p: Parameters) extends Bundle trait Clocked extends Bundle { val clock = Clock() val reset = Bool() } object DecoupledHelper { def apply(rvs: Bool*) = new DecoupledHelper(rvs) } class DecoupledHelper(val rvs: Seq[Bool]) { def fire(exclude: Bool, includes: Bool*) = { require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!") (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _) } def fire() = { rvs.reduce(_ && _) } } object MuxT { def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2)) def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3)) def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4)) } /** Creates a cascade of n MuxTs to search for a key value. */ object MuxTLookup { def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } } object ValidMux { def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]*): ValidIO[T] = { apply(v1 +: v2.toSeq) } def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = { val out = Wire(Valid(valids.head.bits.cloneType)) out.valid := valids.map(_.valid).reduce(_ || _) out.bits := MuxCase(valids.head.bits, valids.map(v => (v.valid -> v.bits))) out } } object Str { def apply(s: String): UInt = { var i = BigInt(0) require(s.forall(validChar _)) for (c <- s) i = (i << 8) | c i.U((s.length*8).W) } def apply(x: Char): UInt = { require(validChar(x)) x.U(8.W) } def apply(x: UInt): UInt = apply(x, 10) def apply(x: UInt, radix: Int): UInt = { val rad = radix.U val w = x.getWidth require(w > 0) var q = x var s = digit(q % rad) for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s) } s } def apply(x: SInt): UInt = apply(x, 10) def apply(x: SInt, radix: Int): UInt = { val neg = x < 0.S val abs = x.abs.asUInt if (radix != 10) { Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix)) } else { val rad = radix.U val w = abs.getWidth require(w > 0) var q = abs var s = digit(q % rad) var needSign = neg for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad val placeSpace = q === 0.U val space = Mux(needSign, Str('-'), Str(' ')) needSign = needSign && !placeSpace s = Cat(Mux(placeSpace, space, digit(q % rad)), s) } Cat(Mux(needSign, Str('-'), Str(' ')), s) } } private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0) private def validChar(x: Char) = x == (x & 0xFF) } object Split { def apply(x: UInt, n0: Int) = { val w = x.getWidth (x.extract(w-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n2: Int, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } } object Random { def apply(mod: Int, random: UInt): UInt = { if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0) else PriorityEncoder(partition(apply(1 << log2Up(mod*8), random), mod)) } def apply(mod: Int): UInt = apply(mod, randomizer) def oneHot(mod: Int, random: UInt): UInt = { if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0)) else PriorityEncoderOH(partition(apply(1 << log2Up(mod*8), random), mod)).asUInt } def oneHot(mod: Int): UInt = oneHot(mod, randomizer) private def randomizer = LFSR(16) private def partition(value: UInt, slices: Int) = Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U) } object Majority { def apply(in: Set[Bool]): Bool = { val n = (in.size >> 1) + 1 val clauses = in.subsets(n).map(_.reduce(_ && _)) clauses.reduce(_ || _) } def apply(in: Seq[Bool]): Bool = apply(in.toSet) def apply(in: UInt): Bool = apply(in.asBools.toSet) } object PopCountAtLeast { private def two(x: UInt): (Bool, Bool) = x.getWidth match { case 1 => (x.asBool, false.B) case n => val half = x.getWidth / 2 val (leftOne, leftTwo) = two(x(half - 1, 0)) val (rightOne, rightTwo) = two(x(x.getWidth - 1, half)) (leftOne || rightOne, leftTwo || rightTwo || (leftOne && rightOne)) } def apply(x: UInt, n: Int): Bool = n match { case 0 => true.B case 1 => x.orR case 2 => two(x)._2 case 3 => PopCount(x) >= n.U } } // This gets used everywhere, so make the smallest circuit possible ... // Given an address and size, create a mask of beatBytes size // eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111 // groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01 object MaskGen { def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = { require (groupBy >= 1 && beatBytes >= groupBy) require (isPow2(beatBytes) && isPow2(groupBy)) val lgBytes = log2Ceil(beatBytes) val sizeOH = UIntToOH(lgSize | 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) | (groupBy*2 - 1).U def helper(i: Int): Seq[(Bool, Bool)] = { if (i == 0) { Seq((lgSize >= lgBytes.asUInt, true.B)) } else { val sub = helper(i-1) val size = sizeOH(lgBytes - i) val bit = addr_lo(lgBytes - i) val nbit = !bit Seq.tabulate (1 << i) { j => val (sub_acc, sub_eq) = sub(j/2) val eq = sub_eq && (if (j % 2 == 1) bit else nbit) val acc = sub_acc || (size && eq) (acc, eq) } } } if (groupBy == beatBytes) 1.U else Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse) } } File PlusArg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.experimental._ import chisel3.util.HasBlackBoxResource @deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05") case class PlusArgInfo(default: BigInt, docstring: String) /** Case class for PlusArg information * * @tparam A scala type of the PlusArg value * @param default optional default value * @param docstring text to include in the help * @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT) */ private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String) /** Typeclass for converting a type to a doctype string * @tparam A some type */ trait Doctypeable[A] { /** Return the doctype string for some option */ def toDoctype(a: Option[A]): String } /** Object containing implementations of the Doctypeable typeclass */ object Doctypes { /** Converts an Int => "INT" */ implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" } /** Converts a BigInt => "INT" */ implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" } /** Converts a String => "STRING" */ implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" } } class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map( "FORMAT" -> StringParam(format), "DEFAULT" -> IntParam(default), "WIDTH" -> IntParam(width) )) with HasBlackBoxResource { val io = IO(new Bundle { val out = Output(UInt(width.W)) }) addResource("/vsrc/plusarg_reader.v") } /* This wrapper class has no outputs, making it clear it is a simulation-only construct */ class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module { val io = IO(new Bundle { val count = Input(UInt(width.W)) }) val max = Module(new plusarg_reader(format, default, docstring, width)).io.out when (max > 0.U) { assert (io.count < max, s"Timeout exceeded: $docstring") } } import Doctypes._ object PlusArg { /** PlusArg("foo") will return 42.U if the simulation is run with +foo=42 * Do not use this as an initial register value. The value is set in an * initial block and thus accessing it from another initial is racey. * Add a docstring to document the arg, which can be dumped in an elaboration * pass. */ def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out } /** PlusArg.timeout(name, default, docstring)(count) will use chisel.assert * to kill the simulation when count exceeds the specified integer argument. * Default 0 will never assert. */ def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count } } object PlusArgArtefacts { private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty /* Add a new PlusArg */ @deprecated( "Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05" ) def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring) /** Add a new PlusArg * * @tparam A scala type of the PlusArg value * @param name name for the PlusArg * @param default optional default value * @param docstring text to include in the help */ def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit = artefacts = artefacts ++ Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default))) /* From plus args, generate help text */ private def serializeHelp_cHeader(tab: String = ""): String = artefacts .map{ case(arg, info) => s"""|$tab+$arg=${info.doctype}\\n\\ |$tab${" "*20}${info.docstring}\\n\\ |""".stripMargin ++ info.default.map{ case default => s"$tab${" "*22}(default=${default})\\n\\\n"}.getOrElse("") }.toSeq.mkString("\\n\\\n") ++ "\"" /* From plus args, generate a char array of their names */ private def serializeArray_cHeader(tab: String = ""): String = { val prettyTab = tab + " " * 44 // Length of 'static const ...' s"${tab}static const char * verilog_plusargs [] = {\\\n" ++ artefacts .map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" } .mkString("")++ s"${prettyTab}0};" } /* Generate C code to be included in emulator.cc that helps with * argument parsing based on available Verilog PlusArgs */ def serialize_cHeader(): String = s"""|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\ |${serializeHelp_cHeader(" "*7)} |${serializeArray_cHeader()} |""".stripMargin } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /** Like Vec.apply(idx), but tolerates indices of mismatched width */ def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /** Any Data subtype that has a Bool member named valid. */ type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /** converts from camel case to to underscores, also removing all spaces */ def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /** converts spaces or underscores to hyphens, also lowering case */ def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y | (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y || y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /** Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation */ def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.diplomacy import chisel3._ import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor} import freechips.rocketchip.util.ShiftQueue /** Options for describing the attributes of memory regions */ object RegionType { // Define the 'more relaxed than' ordering val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS) sealed trait T extends Ordered[T] { def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this) } case object CACHED extends T // an intermediate agent may have cached a copy of the region for you case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively } // A non-empty half-open range; [start, end) case class IdRange(start: Int, end: Int) extends Ordered[IdRange] { require (start >= 0, s"Ids cannot be negative, but got: $start.") require (start <= end, "Id ranges cannot be negative.") def compare(x: IdRange) = { val primary = (this.start - x.start).signum val secondary = (x.end - this.end).signum if (primary != 0) primary else secondary } def overlaps(x: IdRange) = start < x.end && x.start < end def contains(x: IdRange) = start <= x.start && x.end <= end def contains(x: Int) = start <= x && x < end def contains(x: UInt) = if (size == 0) { false.B } else if (size == 1) { // simple comparison x === start.U } else { // find index of largest different bit val largestDeltaBit = log2Floor(start ^ (end-1)) val smallestCommonBit = largestDeltaBit + 1 // may not exist in x val uncommonMask = (1 << smallestCommonBit) - 1 val uncommonBits = (x | 0.U(smallestCommonBit.W))(largestDeltaBit, 0) // the prefix must match exactly (note: may shift ALL bits away) (x >> smallestCommonBit) === (start >> smallestCommonBit).U && // firrtl constant prop range analysis can eliminate these two: (start & uncommonMask).U <= uncommonBits && uncommonBits <= ((end-1) & uncommonMask).U } def shift(x: Int) = IdRange(start+x, end+x) def size = end - start def isEmpty = end == start def range = start until end } object IdRange { def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else { val ranges = s.sorted (ranges.tail zip ranges.init) find { case (a, b) => a overlaps b } } } // An potentially empty inclusive range of 2-powers [min, max] (in bytes) case class TransferSizes(min: Int, max: Int) { def this(x: Int) = this(x, x) require (min <= max, s"Min transfer $min > max transfer $max") require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)") require (max == 0 || isPow2(max), s"TransferSizes must be a power of 2, got: $max") require (min == 0 || isPow2(min), s"TransferSizes must be a power of 2, got: $min") require (max == 0 || min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)") def none = min == 0 def contains(x: Int) = isPow2(x) && min <= x && x <= max def containsLg(x: Int) = contains(1 << x) def containsLg(x: UInt) = if (none) false.B else if (min == max) { log2Ceil(min).U === x } else { log2Ceil(min).U <= x && x <= log2Ceil(max).U } def contains(x: TransferSizes) = x.none || (min <= x.min && x.max <= max) def intersect(x: TransferSizes) = if (x.max < min || max < x.min) TransferSizes.none else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max)) // Not a union, because the result may contain sizes contained by neither term // NOT TO BE CONFUSED WITH COVERPOINTS def mincover(x: TransferSizes) = { if (none) { x } else if (x.none) { this } else { TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max)) } } override def toString() = "TransferSizes[%d, %d]".format(min, max) } object TransferSizes { def apply(x: Int) = new TransferSizes(x) val none = new TransferSizes(0) def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _) def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _) implicit def asBool(x: TransferSizes) = !x.none } // AddressSets specify the address space managed by the manager // Base is the base address, and mask are the bits consumed by the manager // e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff // e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ... case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet] { // Forbid misaligned base address (and empty sets) require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}") require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous // We do allow negative mask (=> ignore all high bits) def contains(x: BigInt) = ((x ^ base) & ~mask) == 0 def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S // turn x into an address contained in this set def legalize(x: UInt): UInt = base.U | (mask.U & x) // overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1) def overlaps(x: AddressSet) = (~(mask | x.mask) & (base ^ x.base)) == 0 // contains iff bitwise: x.mask => mask && contains(x.base) def contains(x: AddressSet) = ((x.mask | (base ^ x.base)) & ~mask) == 0 // The number of bytes to which the manager must be aligned def alignment = ((mask + 1) & ~mask) // Is this a contiguous memory range def contiguous = alignment == mask+1 def finite = mask >= 0 def max = { require (finite, "Max cannot be calculated on infinite mask"); base | mask } // Widen the match function to ignore all bits in imask def widen(imask: BigInt) = AddressSet(base & ~imask, mask | imask) // Return an AddressSet that only contains the addresses both sets contain def intersect(x: AddressSet): Option[AddressSet] = { if (!overlaps(x)) { None } else { val r_mask = mask & x.mask val r_base = base | x.base Some(AddressSet(r_base, r_mask)) } } def subtract(x: AddressSet): Seq[AddressSet] = { intersect(x) match { case None => Seq(this) case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit => val nmask = (mask & (bit-1)) | remove.mask val nbase = (remove.base ^ bit) & ~nmask AddressSet(nbase, nmask) } } } // AddressSets have one natural Ordering (the containment order, if contiguous) def compare(x: AddressSet) = { val primary = (this.base - x.base).signum // smallest address first val secondary = (x.mask - this.mask).signum // largest mask first if (primary != 0) primary else secondary } // We always want to see things in hex override def toString() = { if (mask >= 0) { "AddressSet(0x%x, 0x%x)".format(base, mask) } else { "AddressSet(0x%x, ~0x%x)".format(base, ~mask) } } def toRanges = { require (finite, "Ranges cannot be calculated on infinite mask") val size = alignment val fragments = mask & ~(size-1) val bits = bitIndexes(fragments) (BigInt(0) until (BigInt(1) << bits.size)).map { i => val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) } AddressRange(off, size) } } } object AddressSet { val everything = AddressSet(0, -1) def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = { if (size == 0) tail.reverse else { val maxBaseAlignment = base & (-base) // 0 for infinite (LSB) val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size val step = if (maxBaseAlignment == 0 || maxBaseAlignment > maxSizeAlignment) maxSizeAlignment else maxBaseAlignment misaligned(base+step, size-step, AddressSet(base, step-1) +: tail) } } def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = { // Pair terms up by ignoring 'bit' seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) => if (seq.size == 1) { seq.head // singleton -> unaffected } else { key.copy(mask = key.mask | bit) // pair - widen mask by bit } }.toList } def unify(seq: Seq[AddressSet]): Seq[AddressSet] = { val bits = seq.map(_.base).foldLeft(BigInt(0))(_ | _) AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted } def enumerateMask(mask: BigInt): Seq[BigInt] = { def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] = if (id == mask) (id +: tail).reverse else helper(((~mask | id) + 1) & mask, id +: tail) helper(0, Nil) } def enumerateBits(mask: BigInt): Seq[BigInt] = { def helper(x: BigInt): Seq[BigInt] = { if (x == 0) { Nil } else { val bit = x & (-x) bit +: helper(x & ~bit) } } helper(mask) } } case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean) { require (depth >= 0, "Buffer depth must be >= 0") def isDefined = depth > 0 def latency = if (isDefined && !flow) 1 else 0 def apply[T <: Data](x: DecoupledIO[T]) = if (isDefined) Queue(x, depth, flow=flow, pipe=pipe) else x def irrevocable[T <: Data](x: ReadyValidIO[T]) = if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe) else x def sq[T <: Data](x: DecoupledIO[T]) = if (!isDefined) x else { val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe)) sq.io.enq <> x sq.io.deq } override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "") } object BufferParams { implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false) val default = BufferParams(2) val none = BufferParams(0) val flow = BufferParams(1, true, false) val pipe = BufferParams(1, false, true) } case class TriStateValue(value: Boolean, set: Boolean) { def update(orig: Boolean) = if (set) value else orig } object TriStateValue { implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true) def unset = TriStateValue(false, false) } trait DirectedBuffers[T] { def copyIn(x: BufferParams): T def copyOut(x: BufferParams): T def copyInOut(x: BufferParams): T } trait IdMapEntry { def name: String def from: IdRange def to: IdRange def isCache: Boolean def requestFifo: Boolean def maxTransactionsInFlight: Option[Int] def pretty(fmt: String) = if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5 fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } else { fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } } abstract class IdMap[T <: IdMapEntry] { protected val fmt: String val mapping: Seq[T] def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n") } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) || !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.ProbeAckData || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode | small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U || beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }

module TLMonitor_25( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [11:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [7:0] io_in_d_bits_source // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire [12:0] _GEN = {10'h0, io_in_a_bits_size}; // @[package.scala:243:71] wire _a_first_T_1 = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala:51:35] reg [2:0] a_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [2:0] size; // @[Monitor.scala:389:22] reg [7:0] source; // @[Monitor.scala:390:22] reg [11:0] address; // @[Monitor.scala:391:22] reg [2:0] d_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [2:0] size_1; // @[Monitor.scala:540:22] reg [7:0] source_1; // @[Monitor.scala:541:22] reg [128:0] inflight; // @[Monitor.scala:614:27] reg [515:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [515:0] inflight_sizes; // @[Monitor.scala:618:33] reg [2:0] a_first_counter_1; // @[Edges.scala:229:27] wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] reg [2:0] d_first_counter_1; // @[Edges.scala:229:27] wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _GEN_0 = _a_first_T_1 & a_first_1; // @[Decoupled.scala:51:35] wire d_release_ack = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala:673:46] wire _GEN_1 = io_in_d_bits_opcode != 3'h6; // @[Monitor.scala:673:46, :674:74] reg [31:0] watchdog; // @[Monitor.scala:709:27] reg [128:0] inflight_1; // @[Monitor.scala:726:35] reg [515:0] inflight_sizes_1; // @[Monitor.scala:728:35] reg [2:0] d_first_counter_2; // @[Edges.scala:229:27] wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]

Generate the Verilog code corresponding to the following Chisel files. File Nodes.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.nodes._ import freechips.rocketchip.util.{AsyncQueueParams,RationalDirection} case object TLMonitorBuilder extends Field[TLMonitorArgs => TLMonitorBase](args => new TLMonitor(args)) object TLImp extends NodeImp[TLMasterPortParameters, TLSlavePortParameters, TLEdgeOut, TLEdgeIn, TLBundle] { def edgeO(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeOut(pd, pu, p, sourceInfo) def edgeI(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeIn (pd, pu, p, sourceInfo) def bundleO(eo: TLEdgeOut) = TLBundle(eo.bundle) def bundleI(ei: TLEdgeIn) = TLBundle(ei.bundle) def render(ei: TLEdgeIn) = RenderedEdge(colour = "#000000" /* black */, label = (ei.manager.beatBytes * 8).toString) override def monitor(bundle: TLBundle, edge: TLEdgeIn): Unit = { val monitor = Module(edge.params(TLMonitorBuilder)(TLMonitorArgs(edge))) monitor.io.in := bundle } override def mixO(pd: TLMasterPortParameters, node: OutwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLMasterPortParameters = pd.v1copy(clients = pd.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }) override def mixI(pu: TLSlavePortParameters, node: InwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLSlavePortParameters = pu.v1copy(managers = pu.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }) } trait TLFormatNode extends FormatNode[TLEdgeIn, TLEdgeOut] case class TLClientNode(portParams: Seq[TLMasterPortParameters])(implicit valName: ValName) extends SourceNode(TLImp)(portParams) with TLFormatNode case class TLManagerNode(portParams: Seq[TLSlavePortParameters])(implicit valName: ValName) extends SinkNode(TLImp)(portParams) with TLFormatNode case class TLAdapterNode( clientFn: TLMasterPortParameters => TLMasterPortParameters = { s => s }, managerFn: TLSlavePortParameters => TLSlavePortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLImp)(clientFn, managerFn) with TLFormatNode case class TLJunctionNode( clientFn: Seq[TLMasterPortParameters] => Seq[TLMasterPortParameters], managerFn: Seq[TLSlavePortParameters] => Seq[TLSlavePortParameters])( implicit valName: ValName) extends JunctionNode(TLImp)(clientFn, managerFn) with TLFormatNode case class TLIdentityNode()(implicit valName: ValName) extends IdentityNode(TLImp)() with TLFormatNode object TLNameNode { def apply(name: ValName) = TLIdentityNode()(name) def apply(name: Option[String]): TLIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLIdentityNode = apply(Some(name)) } case class TLEphemeralNode()(implicit valName: ValName) extends EphemeralNode(TLImp)() object TLTempNode { def apply(): TLEphemeralNode = TLEphemeralNode()(ValName("temp")) } case class TLNexusNode( clientFn: Seq[TLMasterPortParameters] => TLMasterPortParameters, managerFn: Seq[TLSlavePortParameters] => TLSlavePortParameters)( implicit valName: ValName) extends NexusNode(TLImp)(clientFn, managerFn) with TLFormatNode abstract class TLCustomNode(implicit valName: ValName) extends CustomNode(TLImp) with TLFormatNode // Asynchronous crossings trait TLAsyncFormatNode extends FormatNode[TLAsyncEdgeParameters, TLAsyncEdgeParameters] object TLAsyncImp extends SimpleNodeImp[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncEdgeParameters, TLAsyncBundle] { def edge(pd: TLAsyncClientPortParameters, pu: TLAsyncManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLAsyncEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLAsyncEdgeParameters) = new TLAsyncBundle(e.bundle) def render(e: TLAsyncEdgeParameters) = RenderedEdge(colour = "#ff0000" /* red */, label = e.manager.async.depth.toString) override def mixO(pd: TLAsyncClientPortParameters, node: OutwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLAsyncManagerPortParameters, node: InwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLAsyncAdapterNode( clientFn: TLAsyncClientPortParameters => TLAsyncClientPortParameters = { s => s }, managerFn: TLAsyncManagerPortParameters => TLAsyncManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLAsyncImp)(clientFn, managerFn) with TLAsyncFormatNode case class TLAsyncIdentityNode()(implicit valName: ValName) extends IdentityNode(TLAsyncImp)() with TLAsyncFormatNode object TLAsyncNameNode { def apply(name: ValName) = TLAsyncIdentityNode()(name) def apply(name: Option[String]): TLAsyncIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLAsyncIdentityNode = apply(Some(name)) } case class TLAsyncSourceNode(sync: Option[Int])(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLAsyncImp)( dFn = { p => TLAsyncClientPortParameters(p) }, uFn = { p => p.base.v1copy(minLatency = p.base.minLatency + sync.getOrElse(p.async.sync)) }) with FormatNode[TLEdgeIn, TLAsyncEdgeParameters] // discard cycles in other clock domain case class TLAsyncSinkNode(async: AsyncQueueParams)(implicit valName: ValName) extends MixedAdapterNode(TLAsyncImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = p.base.minLatency + async.sync) }, uFn = { p => TLAsyncManagerPortParameters(async, p) }) with FormatNode[TLAsyncEdgeParameters, TLEdgeOut] // Rationally related crossings trait TLRationalFormatNode extends FormatNode[TLRationalEdgeParameters, TLRationalEdgeParameters] object TLRationalImp extends SimpleNodeImp[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalEdgeParameters, TLRationalBundle] { def edge(pd: TLRationalClientPortParameters, pu: TLRationalManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLRationalEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLRationalEdgeParameters) = new TLRationalBundle(e.bundle) def render(e: TLRationalEdgeParameters) = RenderedEdge(colour = "#00ff00" /* green */) override def mixO(pd: TLRationalClientPortParameters, node: OutwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLRationalManagerPortParameters, node: InwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLRationalAdapterNode( clientFn: TLRationalClientPortParameters => TLRationalClientPortParameters = { s => s }, managerFn: TLRationalManagerPortParameters => TLRationalManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLRationalImp)(clientFn, managerFn) with TLRationalFormatNode case class TLRationalIdentityNode()(implicit valName: ValName) extends IdentityNode(TLRationalImp)() with TLRationalFormatNode object TLRationalNameNode { def apply(name: ValName) = TLRationalIdentityNode()(name) def apply(name: Option[String]): TLRationalIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLRationalIdentityNode = apply(Some(name)) } case class TLRationalSourceNode()(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLRationalImp)( dFn = { p => TLRationalClientPortParameters(p) }, uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLRationalEdgeParameters] // discard cycles from other clock domain case class TLRationalSinkNode(direction: RationalDirection)(implicit valName: ValName) extends MixedAdapterNode(TLRationalImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = 1) }, uFn = { p => TLRationalManagerPortParameters(direction, p) }) with FormatNode[TLRationalEdgeParameters, TLEdgeOut] // Credited version of TileLink channels trait TLCreditedFormatNode extends FormatNode[TLCreditedEdgeParameters, TLCreditedEdgeParameters] object TLCreditedImp extends SimpleNodeImp[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedEdgeParameters, TLCreditedBundle] { def edge(pd: TLCreditedClientPortParameters, pu: TLCreditedManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLCreditedEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLCreditedEdgeParameters) = new TLCreditedBundle(e.bundle) def render(e: TLCreditedEdgeParameters) = RenderedEdge(colour = "#ffff00" /* yellow */, e.delay.toString) override def mixO(pd: TLCreditedClientPortParameters, node: OutwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLCreditedManagerPortParameters, node: InwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLCreditedAdapterNode( clientFn: TLCreditedClientPortParameters => TLCreditedClientPortParameters = { s => s }, managerFn: TLCreditedManagerPortParameters => TLCreditedManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLCreditedImp)(clientFn, managerFn) with TLCreditedFormatNode case class TLCreditedIdentityNode()(implicit valName: ValName) extends IdentityNode(TLCreditedImp)() with TLCreditedFormatNode object TLCreditedNameNode { def apply(name: ValName) = TLCreditedIdentityNode()(name) def apply(name: Option[String]): TLCreditedIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLCreditedIdentityNode = apply(Some(name)) } case class TLCreditedSourceNode(delay: TLCreditedDelay)(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLCreditedImp)( dFn = { p => TLCreditedClientPortParameters(delay, p) }, uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLCreditedEdgeParameters] // discard cycles from other clock domain case class TLCreditedSinkNode(delay: TLCreditedDelay)(implicit valName: ValName) extends MixedAdapterNode(TLCreditedImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = 1) }, uFn = { p => TLCreditedManagerPortParameters(delay, p) }) with FormatNode[TLCreditedEdgeParameters, TLEdgeOut] File AsyncQueue.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ case class AsyncQueueParams( depth: Int = 8, sync: Int = 3, safe: Boolean = true, // If safe is true, then effort is made to resynchronize the crossing indices when either side is reset. // This makes it safe/possible to reset one side of the crossing (but not the other) when the queue is empty. narrow: Boolean = false) // If narrow is true then the read mux is moved to the source side of the crossing. // This reduces the number of level shifters in the case where the clock crossing is also a voltage crossing, // at the expense of a combinational path from the sink to the source and back to the sink. { require (depth > 0 && isPow2(depth)) require (sync >= 2) val bits = log2Ceil(depth) val wires = if (narrow) 1 else depth } object AsyncQueueParams { // When there is only one entry, we don't need narrow. def singleton(sync: Int = 3, safe: Boolean = true) = AsyncQueueParams(1, sync, safe, false) } class AsyncBundleSafety extends Bundle { val ridx_valid = Input (Bool()) val widx_valid = Output(Bool()) val source_reset_n = Output(Bool()) val sink_reset_n = Input (Bool()) } class AsyncBundle[T <: Data](private val gen: T, val params: AsyncQueueParams = AsyncQueueParams()) extends Bundle { // Data-path synchronization val mem = Output(Vec(params.wires, gen)) val ridx = Input (UInt((params.bits+1).W)) val widx = Output(UInt((params.bits+1).W)) val index = params.narrow.option(Input(UInt(params.bits.W))) // Signals used to self-stabilize a safe AsyncQueue val safe = params.safe.option(new AsyncBundleSafety) } object GrayCounter { def apply(bits: Int, increment: Bool = true.B, clear: Bool = false.B, name: String = "binary"): UInt = { val incremented = Wire(UInt(bits.W)) val binary = RegNext(next=incremented, init=0.U).suggestName(name) incremented := Mux(clear, 0.U, binary + increment.asUInt) incremented ^ (incremented >> 1) } } class AsyncValidSync(sync: Int, desc: String) extends RawModule { val io = IO(new Bundle { val in = Input(Bool()) val out = Output(Bool()) }) val clock = IO(Input(Clock())) val reset = IO(Input(AsyncReset())) withClockAndReset(clock, reset){ io.out := AsyncResetSynchronizerShiftReg(io.in, sync, Some(desc)) } } class AsyncQueueSource[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module { override def desiredName = s"AsyncQueueSource_${gen.typeName}" val io = IO(new Bundle { // These come from the source domain val enq = Flipped(Decoupled(gen)) // These cross to the sink clock domain val async = new AsyncBundle(gen, params) }) val bits = params.bits val sink_ready = WireInit(true.B) val mem = Reg(Vec(params.depth, gen)) // This does NOT need to be reset at all. val widx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.enq.fire, !sink_ready, "widx_bin")) val ridx = AsyncResetSynchronizerShiftReg(io.async.ridx, params.sync, Some("ridx_gray")) val ready = sink_ready && widx =/= (ridx ^ (params.depth | params.depth >> 1).U) val index = if (bits == 0) 0.U else io.async.widx(bits-1, 0) ^ (io.async.widx(bits, bits) << (bits-1)) when (io.enq.fire) { mem(index) := io.enq.bits } val ready_reg = withReset(reset.asAsyncReset)(RegNext(next=ready, init=false.B).suggestName("ready_reg")) io.enq.ready := ready_reg && sink_ready val widx_reg = withReset(reset.asAsyncReset)(RegNext(next=widx, init=0.U).suggestName("widx_gray")) io.async.widx := widx_reg io.async.index match { case Some(index) => io.async.mem(0) := mem(index) case None => io.async.mem := mem } io.async.safe.foreach { sio => val source_valid_0 = Module(new AsyncValidSync(params.sync, "source_valid_0")) val source_valid_1 = Module(new AsyncValidSync(params.sync, "source_valid_1")) val sink_extend = Module(new AsyncValidSync(params.sync, "sink_extend")) val sink_valid = Module(new AsyncValidSync(params.sync, "sink_valid")) source_valid_0.reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset source_valid_1.reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset sink_extend .reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset sink_valid .reset := reset.asAsyncReset source_valid_0.clock := clock source_valid_1.clock := clock sink_extend .clock := clock sink_valid .clock := clock source_valid_0.io.in := true.B source_valid_1.io.in := source_valid_0.io.out sio.widx_valid := source_valid_1.io.out sink_extend.io.in := sio.ridx_valid sink_valid.io.in := sink_extend.io.out sink_ready := sink_valid.io.out sio.source_reset_n := !reset.asBool // Assert that if there is stuff in the queue, then reset cannot happen // Impossible to write because dequeue can occur on the receiving side, // then reset allowed to happen, but write side cannot know that dequeue // occurred. // TODO: write some sort of sanity check assertion for users // that denote don't reset when there is activity // assert (!(reset || !sio.sink_reset_n) || !io.enq.valid, "Enqueue while sink is reset and AsyncQueueSource is unprotected") // assert (!reset_rise || prev_idx_match.asBool, "Sink reset while AsyncQueueSource not empty") } } class AsyncQueueSink[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module { override def desiredName = s"AsyncQueueSink_${gen.typeName}" val io = IO(new Bundle { // These come from the sink domain val deq = Decoupled(gen) // These cross to the source clock domain val async = Flipped(new AsyncBundle(gen, params)) }) val bits = params.bits val source_ready = WireInit(true.B) val ridx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.deq.fire, !source_ready, "ridx_bin")) val widx = AsyncResetSynchronizerShiftReg(io.async.widx, params.sync, Some("widx_gray")) val valid = source_ready && ridx =/= widx // The mux is safe because timing analysis ensures ridx has reached the register // On an ASIC, changes to the unread location cannot affect the selected value // On an FPGA, only one input changes at a time => mem updates don't cause glitches // The register only latches when the selected valued is not being written val index = if (bits == 0) 0.U else ridx(bits-1, 0) ^ (ridx(bits, bits) << (bits-1)) io.async.index.foreach { _ := index } // This register does not NEED to be reset, as its contents will not // be considered unless the asynchronously reset deq valid register is set. // It is possible that bits latches when the source domain is reset / has power cut // This is safe, because isolation gates brought mem low before the zeroed widx reached us val deq_bits_nxt = io.async.mem(if (params.narrow) 0.U else index) io.deq.bits := ClockCrossingReg(deq_bits_nxt, en = valid, doInit = false, name = Some("deq_bits_reg")) val valid_reg = withReset(reset.asAsyncReset)(RegNext(next=valid, init=false.B).suggestName("valid_reg")) io.deq.valid := valid_reg && source_ready val ridx_reg = withReset(reset.asAsyncReset)(RegNext(next=ridx, init=0.U).suggestName("ridx_gray")) io.async.ridx := ridx_reg io.async.safe.foreach { sio => val sink_valid_0 = Module(new AsyncValidSync(params.sync, "sink_valid_0")) val sink_valid_1 = Module(new AsyncValidSync(params.sync, "sink_valid_1")) val source_extend = Module(new AsyncValidSync(params.sync, "source_extend")) val source_valid = Module(new AsyncValidSync(params.sync, "source_valid")) sink_valid_0 .reset := (reset.asBool || !sio.source_reset_n).asAsyncReset sink_valid_1 .reset := (reset.asBool || !sio.source_reset_n).asAsyncReset source_extend.reset := (reset.asBool || !sio.source_reset_n).asAsyncReset source_valid .reset := reset.asAsyncReset sink_valid_0 .clock := clock sink_valid_1 .clock := clock source_extend.clock := clock source_valid .clock := clock sink_valid_0.io.in := true.B sink_valid_1.io.in := sink_valid_0.io.out sio.ridx_valid := sink_valid_1.io.out source_extend.io.in := sio.widx_valid source_valid.io.in := source_extend.io.out source_ready := source_valid.io.out sio.sink_reset_n := !reset.asBool // TODO: write some sort of sanity check assertion for users // that denote don't reset when there is activity // // val reset_and_extend = !source_ready || !sio.source_reset_n || reset.asBool // val reset_and_extend_prev = RegNext(reset_and_extend, true.B) // val reset_rise = !reset_and_extend_prev && reset_and_extend // val prev_idx_match = AsyncResetReg(updateData=(io.async.widx===io.async.ridx), resetData=0) // assert (!reset_rise || prev_idx_match.asBool, "Source reset while AsyncQueueSink not empty") } } object FromAsyncBundle { // Sometimes it makes sense for the sink to have different sync than the source def apply[T <: Data](x: AsyncBundle[T]): DecoupledIO[T] = apply(x, x.params.sync) def apply[T <: Data](x: AsyncBundle[T], sync: Int): DecoupledIO[T] = { val sink = Module(new AsyncQueueSink(chiselTypeOf(x.mem(0)), x.params.copy(sync = sync))) sink.io.async <> x sink.io.deq } } object ToAsyncBundle { def apply[T <: Data](x: ReadyValidIO[T], params: AsyncQueueParams = AsyncQueueParams()): AsyncBundle[T] = { val source = Module(new AsyncQueueSource(chiselTypeOf(x.bits), params)) source.io.enq <> x source.io.async } } class AsyncQueue[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Crossing[T] { val io = IO(new CrossingIO(gen)) val source = withClockAndReset(io.enq_clock, io.enq_reset) { Module(new AsyncQueueSource(gen, params)) } val sink = withClockAndReset(io.deq_clock, io.deq_reset) { Module(new AsyncQueueSink (gen, params)) } source.io.enq <> io.enq io.deq <> sink.io.deq sink.io.async <> source.io.async } File AsyncCrossing.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.diplomacy.{AddressSet, NodeHandle} import freechips.rocketchip.prci.{AsynchronousCrossing} import freechips.rocketchip.subsystem.CrossingWrapper import freechips.rocketchip.util.{AsyncQueueParams, ToAsyncBundle, FromAsyncBundle, Pow2ClockDivider, property} class TLAsyncCrossingSource(sync: Option[Int])(implicit p: Parameters) extends LazyModule { def this(x: Int)(implicit p: Parameters) = this(Some(x)) def this()(implicit p: Parameters) = this(None) val node = TLAsyncSourceNode(sync) lazy val module = new Impl class Impl extends LazyModuleImp(this) { override def desiredName = (Seq("TLAsyncCrossingSource") ++ node.in.headOption.map(_._2.bundle.shortName)).mkString("_") (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => val bce = edgeIn.manager.anySupportAcquireB && edgeIn.client.anySupportProbe val psync = sync.getOrElse(edgeOut.manager.async.sync) val params = edgeOut.manager.async.copy(sync = psync) out.a <> ToAsyncBundle(in.a, params) in.d <> FromAsyncBundle(out.d, psync) property.cover(in.a, "TL_ASYNC_CROSSING_SOURCE_A", "MemorySystem;;TLAsyncCrossingSource Channel A") property.cover(in.d, "TL_ASYNC_CROSSING_SOURCE_D", "MemorySystem;;TLAsyncCrossingSource Channel D") if (bce) { in.b <> FromAsyncBundle(out.b, psync) out.c <> ToAsyncBundle(in.c, params) out.e <> ToAsyncBundle(in.e, params) property.cover(in.b, "TL_ASYNC_CROSSING_SOURCE_B", "MemorySystem;;TLAsyncCrossingSource Channel B") property.cover(in.c, "TL_ASYNC_CROSSING_SOURCE_C", "MemorySystem;;TLAsyncCrossingSource Channel C") property.cover(in.e, "TL_ASYNC_CROSSING_SOURCE_E", "MemorySystem;;TLAsyncCrossingSource Channel E") } else { in.b.valid := false.B in.c.ready := true.B in.e.ready := true.B out.b.ridx := 0.U out.c.widx := 0.U out.e.widx := 0.U } } } } class TLAsyncCrossingSink(params: AsyncQueueParams = AsyncQueueParams())(implicit p: Parameters) extends LazyModule { val node = TLAsyncSinkNode(params) lazy val module = new Impl class Impl extends LazyModuleImp(this) { override def desiredName = (Seq("TLAsyncCrossingSink") ++ node.out.headOption.map(_._2.bundle.shortName)).mkString("_") (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => val bce = edgeOut.manager.anySupportAcquireB && edgeOut.client.anySupportProbe out.a <> FromAsyncBundle(in.a, params.sync) in.d <> ToAsyncBundle(out.d, params) property.cover(out.a, "TL_ASYNC_CROSSING_SINK_A", "MemorySystem;;TLAsyncCrossingSink Channel A") property.cover(out.d, "TL_ASYNC_CROSSING_SINK_D", "MemorySystem;;TLAsyncCrossingSink Channel D") if (bce) { in.b <> ToAsyncBundle(out.b, params) out.c <> FromAsyncBundle(in.c, params.sync) out.e <> FromAsyncBundle(in.e, params.sync) property.cover(out.b, "TL_ASYNC_CROSSING_SINK_B", "MemorySystem;;TLAsyncCrossingSinkChannel B") property.cover(out.c, "TL_ASYNC_CROSSING_SINK_C", "MemorySystem;;TLAsyncCrossingSink Channel C") property.cover(out.e, "TL_ASYNC_CROSSING_SINK_E", "MemorySystem;;TLAsyncCrossingSink Channel E") } else { in.b.widx := 0.U in.c.ridx := 0.U in.e.ridx := 0.U out.b.ready := true.B out.c.valid := false.B out.e.valid := false.B } } } } object TLAsyncCrossingSource { def apply()(implicit p: Parameters): TLAsyncSourceNode = apply(None) def apply(sync: Int)(implicit p: Parameters): TLAsyncSourceNode = apply(Some(sync)) def apply(sync: Option[Int])(implicit p: Parameters): TLAsyncSourceNode = { val asource = LazyModule(new TLAsyncCrossingSource(sync)) asource.node } } object TLAsyncCrossingSink { def apply(params: AsyncQueueParams = AsyncQueueParams())(implicit p: Parameters) = { val asink = LazyModule(new TLAsyncCrossingSink(params)) asink.node } } @deprecated("TLAsyncCrossing is fragile. Use TLAsyncCrossingSource and TLAsyncCrossingSink", "rocket-chip 1.2") class TLAsyncCrossing(params: AsyncQueueParams = AsyncQueueParams())(implicit p: Parameters) extends LazyModule { val source = LazyModule(new TLAsyncCrossingSource()) val sink = LazyModule(new TLAsyncCrossingSink(params)) val node = NodeHandle(source.node, sink.node) sink.node := source.node lazy val module = new Impl class Impl extends LazyModuleImp(this) { val io = IO(new Bundle { val in_clock = Input(Clock()) val in_reset = Input(Bool()) val out_clock = Input(Clock()) val out_reset = Input(Bool()) }) source.module.clock := io.in_clock source.module.reset := io.in_reset sink.module.clock := io.out_clock sink.module.reset := io.out_reset } } // Synthesizable unit tests import freechips.rocketchip.unittest._ class TLRAMAsyncCrossing(txns: Int, params: AsynchronousCrossing = AsynchronousCrossing())(implicit p: Parameters) extends LazyModule { val model = LazyModule(new TLRAMModel("AsyncCrossing")) val fuzz = LazyModule(new TLFuzzer(txns)) val island = LazyModule(new CrossingWrapper(params)) val ram = island { LazyModule(new TLRAM(AddressSet(0x0, 0x3ff))) } island.crossTLIn(ram.node) := TLFragmenter(4, 256) := TLDelayer(0.1) := model.node := fuzz.node lazy val module = new Impl class Impl extends LazyModuleImp(this) with UnitTestModule { io.finished := fuzz.module.io.finished // Shove the RAM into another clock domain val clocks = Module(new Pow2ClockDivider(2)) island.module.clock := clocks.io.clock_out } } class TLRAMAsyncCrossingTest(txns: Int = 5000, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) { val dut_wide = Module(LazyModule(new TLRAMAsyncCrossing(txns)).module) val dut_narrow = Module(LazyModule(new TLRAMAsyncCrossing(txns, AsynchronousCrossing(safe = false, narrow = true))).module) io.finished := dut_wide.io.finished && dut_narrow.io.finished dut_wide.io.start := io.start dut_narrow.io.start := io.start } File LazyModuleImp.scala: package org.chipsalliance.diplomacy.lazymodule import chisel3.{withClockAndReset, Module, RawModule, Reset, _} import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo} import firrtl.passes.InlineAnnotation import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.nodes.Dangle import scala.collection.immutable.SortedMap /** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]]. * * This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy. */ sealed trait LazyModuleImpLike extends RawModule { /** [[LazyModule]] that contains this instance. */ val wrapper: LazyModule /** IOs that will be automatically "punched" for this instance. */ val auto: AutoBundle /** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */ protected[diplomacy] val dangles: Seq[Dangle] // [[wrapper.module]] had better not be accessed while LazyModules are still being built! require( LazyModule.scope.isEmpty, s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}" ) /** Set module name. Defaults to the containing LazyModule's desiredName. */ override def desiredName: String = wrapper.desiredName suggestName(wrapper.suggestedName) /** [[Parameters]] for chisel [[Module]]s. */ implicit val p: Parameters = wrapper.p /** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and * submodules. */ protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = { // 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]], // 2. return [[Dangle]]s from each module. val childDangles = wrapper.children.reverse.flatMap { c => implicit val sourceInfo: SourceInfo = c.info c.cloneProto.map { cp => // If the child is a clone, then recursively set cloneProto of its children as well def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = { require(bases.size == clones.size) (bases.zip(clones)).map { case (l, r) => require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}") l.cloneProto = Some(r) assignCloneProtos(l.children, r.children) } } assignCloneProtos(c.children, cp.children) // Clone the child module as a record, and get its [[AutoBundle]] val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName) val clonedAuto = clone("auto").asInstanceOf[AutoBundle] // Get the empty [[Dangle]]'s of the cloned child val rawDangles = c.cloneDangles() require(rawDangles.size == clonedAuto.elements.size) // Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) } dangles }.getOrElse { // For non-clones, instantiate the child module val mod = try { Module(c.module) } catch { case e: ChiselException => { println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}") throw e } } mod.dangles } } // Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]]. // This will result in a sequence of [[Dangle]] from these [[BaseNode]]s. val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate()) // Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]] val allDangles = nodeDangles ++ childDangles // Group [[allDangles]] by their [[source]]. val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*) // For each [[source]] set of [[Dangle]]s of size 2, ensure that these // can be connected as a source-sink pair (have opposite flipped value). // Make the connection and mark them as [[done]]. val done = Set() ++ pairing.values.filter(_.size == 2).map { case Seq(a, b) => require(a.flipped != b.flipped) // @todo <> in chisel3 makes directionless connection. if (a.flipped) { a.data <> b.data } else { b.data <> a.data } a.source case _ => None } // Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module. val forward = allDangles.filter(d => !done(d.source)) // Generate [[AutoBundle]] IO from [[forward]]. val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*)) // Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]] val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) => if (d.flipped) { d.data <> io } else { io <> d.data } d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name) } // Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]]. wrapper.inModuleBody.reverse.foreach { _() } if (wrapper.shouldBeInlined) { chisel3.experimental.annotate(new ChiselAnnotation { def toFirrtl = InlineAnnotation(toNamed) }) } // Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]]. (auto, dangles) } } /** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike { /** Instantiate hardware of this `Module`. */ val (auto, dangles) = instantiate() } /** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike { // These wires are the default clock+reset for all LazyModule children. // It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the // [[LazyRawModuleImp]] children. // Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly. /** drive clock explicitly. */ val childClock: Clock = Wire(Clock()) /** drive reset explicitly. */ val childReset: Reset = Wire(Reset()) // the default is that these are disabled childClock := false.B.asClock childReset := chisel3.DontCare def provideImplicitClockToLazyChildren: Boolean = false val (auto, dangles) = if (provideImplicitClockToLazyChildren) { withClockAndReset(childClock, childReset) { instantiate() } } else { instantiate() } } File MixedNode.scala: package org.chipsalliance.diplomacy.nodes import chisel3.{Data, DontCare, Wire} import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.{Field, Parameters} import org.chipsalliance.diplomacy.ValName import org.chipsalliance.diplomacy.sourceLine /** One side metadata of a [[Dangle]]. * * Describes one side of an edge going into or out of a [[BaseNode]]. * * @param serial * the global [[BaseNode.serial]] number of the [[BaseNode]] that this [[HalfEdge]] connects to. * @param index * the `index` in the [[BaseNode]]'s input or output port list that this [[HalfEdge]] belongs to. */ case class HalfEdge(serial: Int, index: Int) extends Ordered[HalfEdge] { import scala.math.Ordered.orderingToOrdered def compare(that: HalfEdge): Int = HalfEdge.unapply(this).compare(HalfEdge.unapply(that)) } /** [[Dangle]] captures the `IO` information of a [[LazyModule]] and which two [[BaseNode]]s the [[Edges]]/[[Bundle]] * connects. * * [[Dangle]]s are generated by [[BaseNode.instantiate]] using [[MixedNode.danglesOut]] and [[MixedNode.danglesIn]] , * [[LazyModuleImp.instantiate]] connects those that go to internal or explicit IO connections in a [[LazyModule]]. * * @param source * the source [[HalfEdge]] of this [[Dangle]], which captures the source [[BaseNode]] and the port `index` within * that [[BaseNode]]. * @param sink * sink [[HalfEdge]] of this [[Dangle]], which captures the sink [[BaseNode]] and the port `index` within that * [[BaseNode]]. * @param flipped * flip or not in [[AutoBundle.makeElements]]. If true this corresponds to `danglesOut`, if false it corresponds to * `danglesIn`. * @param dataOpt * actual [[Data]] for the hardware connection. Can be empty if this belongs to a cloned module */ case class Dangle(source: HalfEdge, sink: HalfEdge, flipped: Boolean, name: String, dataOpt: Option[Data]) { def data = dataOpt.get } /** [[Edges]] is a collection of parameters describing the functionality and connection for an interface, which is often * derived from the interconnection protocol and can inform the parameterization of the hardware bundles that actually * implement the protocol. */ case class Edges[EI, EO](in: Seq[EI], out: Seq[EO]) /** A field available in [[Parameters]] used to determine whether [[InwardNodeImp.monitor]] will be called. */ case object MonitorsEnabled extends Field[Boolean](true) /** When rendering the edge in a graphical format, flip the order in which the edges' source and sink are presented. * * For example, when rendering graphML, yEd by default tries to put the source node vertically above the sink node, but * [[RenderFlipped]] inverts this relationship. When a particular [[LazyModule]] contains both source nodes and sink * nodes, flipping the rendering of one node's edge will usual produce a more concise visual layout for the * [[LazyModule]]. */ case object RenderFlipped extends Field[Boolean](false) /** The sealed node class in the package, all node are derived from it. * * @param inner * Sink interface implementation. * @param outer * Source interface implementation. * @param valName * val name of this node. * @tparam DI * Downward-flowing parameters received on the inner side of the node. It is usually a brunch of parameters * describing the protocol parameters from a source. For an [[InwardNode]], it is determined by the connected * [[OutwardNode]]. Since it can be connected to multiple sources, this parameter is always a Seq of source port * parameters. * @tparam UI * Upward-flowing parameters generated by the inner side of the node. It is usually a brunch of parameters describing * the protocol parameters of a sink. For an [[InwardNode]], it is determined itself. * @tparam EI * Edge Parameters describing a connection on the inner side of the node. It is usually a brunch of transfers * specified for a sink according to protocol. * @tparam BI * Bundle type used when connecting to the inner side of the node. It is a hardware interface of this sink interface. * It should extends from [[chisel3.Data]], which represents the real hardware. * @tparam DO * Downward-flowing parameters generated on the outer side of the node. It is usually a brunch of parameters * describing the protocol parameters of a source. For an [[OutwardNode]], it is determined itself. * @tparam UO * Upward-flowing parameters received by the outer side of the node. It is usually a brunch of parameters describing * the protocol parameters from a sink. For an [[OutwardNode]], it is determined by the connected [[InwardNode]]. * Since it can be connected to multiple sinks, this parameter is always a Seq of sink port parameters. * @tparam EO * Edge Parameters describing a connection on the outer side of the node. It is usually a brunch of transfers * specified for a source according to protocol. * @tparam BO * Bundle type used when connecting to the outer side of the node. It is a hardware interface of this source * interface. It should extends from [[chisel3.Data]], which represents the real hardware. * * @note * Call Graph of [[MixedNode]] * - line `─`: source is process by a function and generate pass to others * - Arrow `→`: target of arrow is generated by source * * {{{ * (from the other node) * ┌─────────────────────────────────────────────────────────[[InwardNode.uiParams]]─────────────┐ * ↓ │ * (binding node when elaboration) [[OutwardNode.uoParams]]────────────────────────[[MixedNode.mapParamsU]]→──────────┐ │ * [[InwardNode.accPI]] │ │ │ * │ │ (based on protocol) │ * │ │ [[MixedNode.inner.edgeI]] │ * │ │ ↓ │ * ↓ │ │ │ * (immobilize after elaboration) (inward port from [[OutwardNode]]) │ ↓ │ * [[InwardNode.iBindings]]──┐ [[MixedNode.iDirectPorts]]────────────────────→[[MixedNode.iPorts]] [[InwardNode.uiParams]] │ * │ │ ↑ │ │ │ * │ │ │ [[OutwardNode.doParams]] │ │ * │ │ │ (from the other node) │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * │ │ │ └────────┬──────────────┤ │ * │ │ │ │ │ │ * │ │ │ │ (based on protocol) │ * │ │ │ │ [[MixedNode.inner.edgeI]] │ * │ │ │ │ │ │ * │ │ (from the other node) │ ↓ │ * │ └───[[OutwardNode.oPortMapping]] [[OutwardNode.oStar]] │ [[MixedNode.edgesIn]]───┐ │ * │ ↑ ↑ │ │ ↓ │ * │ │ │ │ │ [[MixedNode.in]] │ * │ │ │ │ ↓ ↑ │ * │ (solve star connection) │ │ │ [[MixedNode.bundleIn]]──┘ │ * ├───[[MixedNode.resolveStar]]→─┼─────────────────────────────┤ └────────────────────────────────────┐ │ * │ │ │ [[MixedNode.bundleOut]]─┐ │ │ * │ │ │ ↑ ↓ │ │ * │ │ │ │ [[MixedNode.out]] │ │ * │ ↓ ↓ │ ↑ │ │ * │ ┌─────[[InwardNode.iPortMapping]] [[InwardNode.iStar]] [[MixedNode.edgesOut]]──┘ │ │ * │ │ (from the other node) ↑ │ │ * │ │ │ │ │ │ * │ │ │ [[MixedNode.outer.edgeO]] │ │ * │ │ │ (based on protocol) │ │ * │ │ │ │ │ │ * │ │ │ ┌────────────────────────────────────────┤ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * (immobilize after elaboration)│ ↓ │ │ │ │ * [[OutwardNode.oBindings]]─┘ [[MixedNode.oDirectPorts]]───→[[MixedNode.oPorts]] [[OutwardNode.doParams]] │ │ * ↑ (inward port from [[OutwardNode]]) │ │ │ │ * │ ┌─────────────────────────────────────────┤ │ │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * [[OutwardNode.accPO]] │ ↓ │ │ │ * (binding node when elaboration) │ [[InwardNode.diParams]]─────→[[MixedNode.mapParamsD]]────────────────────────────┘ │ │ * │ ↑ │ │ * │ └──────────────────────────────────────────────────────────────────────────────────────────┘ │ * └──────────────────────────────────────────────────────────────────────────────────────────────────────────┘ * }}} */ abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data]( val inner: InwardNodeImp[DI, UI, EI, BI], val outer: OutwardNodeImp[DO, UO, EO, BO] )( implicit valName: ValName) extends BaseNode with NodeHandle[DI, UI, EI, BI, DO, UO, EO, BO] with InwardNode[DI, UI, BI] with OutwardNode[DO, UO, BO] { // Generate a [[NodeHandle]] with inward and outward node are both this node. val inward = this val outward = this /** Debug info of nodes binding. */ def bindingInfo: String = s"""$iBindingInfo |$oBindingInfo |""".stripMargin /** Debug info of ports connecting. */ def connectedPortsInfo: String = s"""${oPorts.size} outward ports connected: [${oPorts.map(_._2.name).mkString(",")}] |${iPorts.size} inward ports connected: [${iPorts.map(_._2.name).mkString(",")}] |""".stripMargin /** Debug info of parameters propagations. */ def parametersInfo: String = s"""${doParams.size} downstream outward parameters: [${doParams.mkString(",")}] |${uoParams.size} upstream outward parameters: [${uoParams.mkString(",")}] |${diParams.size} downstream inward parameters: [${diParams.mkString(",")}] |${uiParams.size} upstream inward parameters: [${uiParams.mkString(",")}] |""".stripMargin /** For a given node, converts [[OutwardNode.accPO]] and [[InwardNode.accPI]] to [[MixedNode.oPortMapping]] and * [[MixedNode.iPortMapping]]. * * Given counts of known inward and outward binding and inward and outward star bindings, return the resolved inward * stars and outward stars. * * This method will also validate the arguments and throw a runtime error if the values are unsuitable for this type * of node. * * @param iKnown * Number of known-size ([[BIND_ONCE]]) input bindings. * @param oKnown * Number of known-size ([[BIND_ONCE]]) output bindings. * @param iStar * Number of unknown size ([[BIND_STAR]]) input bindings. * @param oStar * Number of unknown size ([[BIND_STAR]]) output bindings. * @return * A Tuple of the resolved number of input and output connections. */ protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStar: Int, oStar: Int): (Int, Int) /** Function to generate downward-flowing outward params from the downward-flowing input params and the current output * ports. * * @param n * The size of the output sequence to generate. * @param p * Sequence of downward-flowing input parameters of this node. * @return * A `n`-sized sequence of downward-flowing output edge parameters. */ protected[diplomacy] def mapParamsD(n: Int, p: Seq[DI]): Seq[DO] /** Function to generate upward-flowing input parameters from the upward-flowing output parameters [[uiParams]]. * * @param n * Size of the output sequence. * @param p * Upward-flowing output edge parameters. * @return * A n-sized sequence of upward-flowing input edge parameters. */ protected[diplomacy] def mapParamsU(n: Int, p: Seq[UO]): Seq[UI] /** @return * The sink cardinality of the node, the number of outputs bound with [[BIND_QUERY]] summed with inputs bound with * [[BIND_STAR]]. */ protected[diplomacy] lazy val sinkCard: Int = oBindings.count(_._3 == BIND_QUERY) + iBindings.count(_._3 == BIND_STAR) /** @return * The source cardinality of this node, the number of inputs bound with [[BIND_QUERY]] summed with the number of * output bindings bound with [[BIND_STAR]]. */ protected[diplomacy] lazy val sourceCard: Int = iBindings.count(_._3 == BIND_QUERY) + oBindings.count(_._3 == BIND_STAR) /** @return list of nodes involved in flex bindings with this node. */ protected[diplomacy] lazy val flexes: Seq[BaseNode] = oBindings.filter(_._3 == BIND_FLEX).map(_._2) ++ iBindings.filter(_._3 == BIND_FLEX).map(_._2) /** Resolves the flex to be either source or sink and returns the offset where the [[BIND_STAR]] operators begin * greedily taking up the remaining connections. * * @return * A value >= 0 if it is sink cardinality, a negative value for source cardinality. The magnitude of the return * value is not relevant. */ protected[diplomacy] lazy val flexOffset: Int = { /** Recursively performs a depth-first search of the [[flexes]], [[BaseNode]]s connected to this node with flex * operators. The algorithm bottoms out when we either get to a node we have already visited or when we get to a * connection that is not a flex and can set the direction for us. Otherwise, recurse by visiting the `flexes` of * each node in the current set and decide whether they should be added to the set or not. * * @return * the mapping of [[BaseNode]] indexed by their serial numbers. */ def DFS(v: BaseNode, visited: Map[Int, BaseNode]): Map[Int, BaseNode] = { if (visited.contains(v.serial) || !v.flexibleArityDirection) { visited } else { v.flexes.foldLeft(visited + (v.serial -> v))((sum, n) => DFS(n, sum)) } } /** Determine which [[BaseNode]] are involved in resolving the flex connections to/from this node. * * @example * {{{ * a :*=* b :*=* c * d :*=* b * e :*=* f * }}} * * `flexSet` for `a`, `b`, `c`, or `d` will be `Set(a, b, c, d)` `flexSet` for `e` or `f` will be `Set(e,f)` */ val flexSet = DFS(this, Map()).values /** The total number of :*= operators where we're on the left. */ val allSink = flexSet.map(_.sinkCard).sum /** The total number of :=* operators used when we're on the right. */ val allSource = flexSet.map(_.sourceCard).sum require( allSink == 0 || allSource == 0, s"The nodes ${flexSet.map(_.name)} which are inter-connected by :*=* have ${allSink} :*= operators and ${allSource} :=* operators connected to them, making it impossible to determine cardinality inference direction." ) allSink - allSource } /** @return A value >= 0 if it is sink cardinality, a negative value for source cardinality. */ protected[diplomacy] def edgeArityDirection(n: BaseNode): Int = { if (flexibleArityDirection) flexOffset else if (n.flexibleArityDirection) n.flexOffset else 0 } /** For a node which is connected between two nodes, select the one that will influence the direction of the flex * resolution. */ protected[diplomacy] def edgeAritySelect(n: BaseNode, l: => Int, r: => Int): Int = { val dir = edgeArityDirection(n) if (dir < 0) l else if (dir > 0) r else 1 } /** Ensure that the same node is not visited twice in resolving `:*=`, etc operators. */ private var starCycleGuard = false /** Resolve all the star operators into concrete indicies. As connections are being made, some may be "star" * connections which need to be resolved. In some way to determine how many actual edges they correspond to. We also * need to build up the ranges of edges which correspond to each binding operator, so that We can apply the correct * edge parameters and later build up correct bundle connections. * * [[oPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that oPort (binding * operator). [[iPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that iPort * (binding operator). [[oStar]]: `Int` the value to return for this node `N` for any `N :*= foo` or `N :*=* foo :*= * bar` [[iStar]]: `Int` the value to return for this node `N` for any `foo :=* N` or `bar :=* foo :*=* N` */ protected[diplomacy] lazy val ( oPortMapping: Seq[(Int, Int)], iPortMapping: Seq[(Int, Int)], oStar: Int, iStar: Int ) = { try { if (starCycleGuard) throw StarCycleException() starCycleGuard = true // For a given node N... // Number of foo :=* N // + Number of bar :=* foo :*=* N val oStars = oBindings.count { case (_, n, b, _, _) => b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) < 0) } // Number of N :*= foo // + Number of N :*=* foo :*= bar val iStars = iBindings.count { case (_, n, b, _, _) => b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) > 0) } // 1 for foo := N // + bar.iStar for bar :*= foo :*=* N // + foo.iStar for foo :*= N // + 0 for foo :=* N val oKnown = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, 0, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => 0 } }.sum // 1 for N := foo // + bar.oStar for N :*=* foo :=* bar // + foo.oStar for N :=* foo // + 0 for N :*= foo val iKnown = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, 0) case BIND_QUERY => n.oStar case BIND_STAR => 0 } }.sum // Resolve star depends on the node subclass to implement the algorithm for this. val (iStar, oStar) = resolveStar(iKnown, oKnown, iStars, oStars) // Cumulative list of resolved outward binding range starting points val oSum = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, oStar, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => oStar } }.scanLeft(0)(_ + _) // Cumulative list of resolved inward binding range starting points val iSum = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, iStar) case BIND_QUERY => n.oStar case BIND_STAR => iStar } }.scanLeft(0)(_ + _) // Create ranges for each binding based on the running sums and return // those along with resolved values for the star operations. (oSum.init.zip(oSum.tail), iSum.init.zip(iSum.tail), oStar, iStar) } catch { case c: StarCycleException => throw c.copy(loop = context +: c.loop) } } /** Sequence of inward ports. * * This should be called after all star bindings are resolved. * * Each element is: `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. * `n` Instance of inward node. `p` View of [[Parameters]] where this connection was made. `s` Source info where this * connection was made in the source code. */ protected[diplomacy] lazy val oDirectPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oBindings.flatMap { case (i, n, _, p, s) => // for each binding operator in this node, look at what it connects to val (start, end) = n.iPortMapping(i) (start until end).map { j => (j, n, p, s) } } /** Sequence of outward ports. * * This should be called after all star bindings are resolved. * * `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. `n` Instance of * outward node. `p` View of [[Parameters]] where this connection was made. `s` [[SourceInfo]] where this connection * was made in the source code. */ protected[diplomacy] lazy val iDirectPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iBindings.flatMap { case (i, n, _, p, s) => // query this port index range of this node in the other side of node. val (start, end) = n.oPortMapping(i) (start until end).map { j => (j, n, p, s) } } // Ephemeral nodes ( which have non-None iForward/oForward) have in_degree = out_degree // Thus, there must exist an Eulerian path and the below algorithms terminate @scala.annotation.tailrec private def oTrace( tuple: (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) ): (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.iForward(i) match { case None => (i, n, p, s) case Some((j, m)) => oTrace((j, m, p, s)) } } @scala.annotation.tailrec private def iTrace( tuple: (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) ): (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.oForward(i) match { case None => (i, n, p, s) case Some((j, m)) => iTrace((j, m, p, s)) } } /** Final output ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - Numeric index of this binding in the [[InwardNode]] on the other end. * - [[InwardNode]] on the other end of this binding. * - A view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. */ lazy val oPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oDirectPorts.map(oTrace) /** Final input ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - numeric index of this binding in [[OutwardNode]] on the other end. * - [[OutwardNode]] on the other end of this binding. * - a view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. */ lazy val iPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iDirectPorts.map(iTrace) private var oParamsCycleGuard = false protected[diplomacy] lazy val diParams: Seq[DI] = iPorts.map { case (i, n, _, _) => n.doParams(i) } protected[diplomacy] lazy val doParams: Seq[DO] = { try { if (oParamsCycleGuard) throw DownwardCycleException() oParamsCycleGuard = true val o = mapParamsD(oPorts.size, diParams) require( o.size == oPorts.size, s"""Diplomacy has detected a problem with your graph: |At the following node, the number of outward ports should equal the number of produced outward parameters. |$context |$connectedPortsInfo |Downstreamed inward parameters: [${diParams.mkString(",")}] |Produced outward parameters: [${o.mkString(",")}] |""".stripMargin ) o.map(outer.mixO(_, this)) } catch { case c: DownwardCycleException => throw c.copy(loop = context +: c.loop) } } private var iParamsCycleGuard = false protected[diplomacy] lazy val uoParams: Seq[UO] = oPorts.map { case (o, n, _, _) => n.uiParams(o) } protected[diplomacy] lazy val uiParams: Seq[UI] = { try { if (iParamsCycleGuard) throw UpwardCycleException() iParamsCycleGuard = true val i = mapParamsU(iPorts.size, uoParams) require( i.size == iPorts.size, s"""Diplomacy has detected a problem with your graph: |At the following node, the number of inward ports should equal the number of produced inward parameters. |$context |$connectedPortsInfo |Upstreamed outward parameters: [${uoParams.mkString(",")}] |Produced inward parameters: [${i.mkString(",")}] |""".stripMargin ) i.map(inner.mixI(_, this)) } catch { case c: UpwardCycleException => throw c.copy(loop = context +: c.loop) } } /** Outward edge parameters. */ protected[diplomacy] lazy val edgesOut: Seq[EO] = (oPorts.zip(doParams)).map { case ((i, n, p, s), o) => outer.edgeO(o, n.uiParams(i), p, s) } /** Inward edge parameters. */ protected[diplomacy] lazy val edgesIn: Seq[EI] = (iPorts.zip(uiParams)).map { case ((o, n, p, s), i) => inner.edgeI(n.doParams(o), i, p, s) } /** A tuple of the input edge parameters and output edge parameters for the edges bound to this node. * * If you need to access to the edges of a foreign Node, use this method (in/out create bundles). */ lazy val edges: Edges[EI, EO] = Edges(edgesIn, edgesOut) /** Create actual Wires corresponding to the Bundles parameterized by the outward edges of this node. */ protected[diplomacy] lazy val bundleOut: Seq[BO] = edgesOut.map { e => val x = Wire(outer.bundleO(e)).suggestName(s"${valName.value}Out") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } /** Create actual Wires corresponding to the Bundles parameterized by the inward edges of this node. */ protected[diplomacy] lazy val bundleIn: Seq[BI] = edgesIn.map { e => val x = Wire(inner.bundleI(e)).suggestName(s"${valName.value}In") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } private def emptyDanglesOut: Seq[Dangle] = oPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(serial, i), sink = HalfEdge(n.serial, j), flipped = false, name = wirePrefix + "out", dataOpt = None ) } private def emptyDanglesIn: Seq[Dangle] = iPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(n.serial, j), sink = HalfEdge(serial, i), flipped = true, name = wirePrefix + "in", dataOpt = None ) } /** Create the [[Dangle]]s which describe the connections from this node output to other nodes inputs. */ protected[diplomacy] def danglesOut: Seq[Dangle] = emptyDanglesOut.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleOut(i))) } /** Create the [[Dangle]]s which describe the connections from this node input from other nodes outputs. */ protected[diplomacy] def danglesIn: Seq[Dangle] = emptyDanglesIn.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleIn(i))) } private[diplomacy] var instantiated = false /** Gather Bundle and edge parameters of outward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. */ def out: Seq[(BO, EO)] = { require( instantiated, s"$name.out should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleOut.zip(edgesOut) } /** Gather Bundle and edge parameters of inward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. */ def in: Seq[(BI, EI)] = { require( instantiated, s"$name.in should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleIn.zip(edgesIn) } /** Actually instantiate this node during [[LazyModuleImp]] evaluation. Mark that it's safe to use the Bundle wires, * instantiate monitors on all input ports if appropriate, and return all the dangles of this node. */ protected[diplomacy] def instantiate(): Seq[Dangle] = { instantiated = true if (!circuitIdentity) { (iPorts.zip(in)).foreach { case ((_, _, p, _), (b, e)) => if (p(MonitorsEnabled)) inner.monitor(b, e) } } danglesOut ++ danglesIn } protected[diplomacy] def cloneDangles(): Seq[Dangle] = emptyDanglesOut ++ emptyDanglesIn /** Connects the outward part of a node with the inward part of this node. */ protected[diplomacy] def bind( h: OutwardNode[DI, UI, BI], binding: NodeBinding )( implicit p: Parameters, sourceInfo: SourceInfo ): Unit = { val x = this // x := y val y = h sourceLine(sourceInfo, " at ", "") val i = x.iPushed val o = y.oPushed y.oPush( i, x, binding match { case BIND_ONCE => BIND_ONCE case BIND_FLEX => BIND_FLEX case BIND_STAR => BIND_QUERY case BIND_QUERY => BIND_STAR } ) x.iPush(o, y, binding) } /* Metadata for printing the node graph. */ def inputs: Seq[(OutwardNode[DI, UI, BI], RenderedEdge)] = (iPorts.zip(edgesIn)).map { case ((_, n, p, _), e) => val re = inner.render(e) (n, re.copy(flipped = re.flipped != p(RenderFlipped))) } /** Metadata for printing the node graph */ def outputs: Seq[(InwardNode[DO, UO, BO], RenderedEdge)] = oPorts.map { case (i, n, _, _) => (n, n.inputs(i)._2) } }

module TLAsyncCrossingSource_a9d32s1k1z2u( // @[AsyncCrossing.scala:23:9] input clock, // @[AsyncCrossing.scala:23:9] input reset, // @[AsyncCrossing.scala:23:9] output auto_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [8:0] auto_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [31:0] auto_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_d_bits_param, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [31:0] auto_in_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_mem_0_opcode, // @[LazyModuleImp.scala:107:25] output [8:0] auto_out_a_mem_0_address, // @[LazyModuleImp.scala:107:25] output [31:0] auto_out_a_mem_0_data, // @[LazyModuleImp.scala:107:25] input auto_out_a_ridx, // @[LazyModuleImp.scala:107:25] output auto_out_a_widx, // @[LazyModuleImp.scala:107:25] input auto_out_a_safe_ridx_valid, // @[LazyModuleImp.scala:107:25] output auto_out_a_safe_widx_valid, // @[LazyModuleImp.scala:107:25] output auto_out_a_safe_source_reset_n, // @[LazyModuleImp.scala:107:25] input auto_out_a_safe_sink_reset_n, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_d_mem_0_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_out_d_mem_0_size, // @[LazyModuleImp.scala:107:25] input auto_out_d_mem_0_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_out_d_mem_0_data, // @[LazyModuleImp.scala:107:25] output auto_out_d_ridx, // @[LazyModuleImp.scala:107:25] input auto_out_d_widx, // @[LazyModuleImp.scala:107:25] output auto_out_d_safe_ridx_valid, // @[LazyModuleImp.scala:107:25] input auto_out_d_safe_widx_valid, // @[LazyModuleImp.scala:107:25] input auto_out_d_safe_source_reset_n, // @[LazyModuleImp.scala:107:25] output auto_out_d_safe_sink_reset_n // @[LazyModuleImp.scala:107:25] ); wire auto_in_a_valid_0 = auto_in_a_valid; // @[AsyncCrossing.scala:23:9] wire [2:0] auto_in_a_bits_opcode_0 = auto_in_a_bits_opcode; // @[AsyncCrossing.scala:23:9] wire [8:0] auto_in_a_bits_address_0 = auto_in_a_bits_address; // @[AsyncCrossing.scala:23:9] wire [31:0] auto_in_a_bits_data_0 = auto_in_a_bits_data; // @[AsyncCrossing.scala:23:9] wire auto_in_d_ready_0 = auto_in_d_ready; // @[AsyncCrossing.scala:23:9] wire auto_out_a_ridx_0 = auto_out_a_ridx; // @[AsyncCrossing.scala:23:9] wire auto_out_a_safe_ridx_valid_0 = auto_out_a_safe_ridx_valid; // @[AsyncCrossing.scala:23:9] wire auto_out_a_safe_sink_reset_n_0 = auto_out_a_safe_sink_reset_n; // @[AsyncCrossing.scala:23:9] wire [2:0] auto_out_d_mem_0_opcode_0 = auto_out_d_mem_0_opcode; // @[AsyncCrossing.scala:23:9] wire [1:0] auto_out_d_mem_0_size_0 = auto_out_d_mem_0_size; // @[AsyncCrossing.scala:23:9] wire auto_out_d_mem_0_source_0 = auto_out_d_mem_0_source; // @[AsyncCrossing.scala:23:9] wire [31:0] auto_out_d_mem_0_data_0 = auto_out_d_mem_0_data; // @[AsyncCrossing.scala:23:9] wire auto_out_d_widx_0 = auto_out_d_widx; // @[AsyncCrossing.scala:23:9] wire auto_out_d_safe_widx_valid_0 = auto_out_d_safe_widx_valid; // @[AsyncCrossing.scala:23:9] wire auto_out_d_safe_source_reset_n_0 = auto_out_d_safe_source_reset_n; // @[AsyncCrossing.scala:23:9] wire [31:0] auto_out_b_mem_0_data = 32'h0; // @[AsyncCrossing.scala:23:9] wire [31:0] auto_out_c_mem_0_data = 32'h0; // @[AsyncCrossing.scala:23:9] wire [31:0] nodeOut_b_mem_0_data = 32'h0; // @[MixedNode.scala:542:17] wire [31:0] nodeOut_c_mem_0_data = 32'h0; // @[MixedNode.scala:542:17] wire [3:0] auto_out_b_mem_0_mask = 4'h0; // @[AsyncCrossing.scala:23:9] wire [3:0] nodeOut_b_mem_0_mask = 4'h0; // @[AsyncCrossing.scala:23:9] wire [8:0] auto_out_b_mem_0_address = 9'h0; // @[AsyncCrossing.scala:23:9] wire [8:0] auto_out_c_mem_0_address = 9'h0; // @[AsyncCrossing.scala:23:9] wire [8:0] nodeOut_b_mem_0_address = 9'h0; // @[MixedNode.scala:542:17] wire [8:0] nodeOut_c_mem_0_address = 9'h0; // @[MixedNode.scala:542:17] wire [1:0] auto_out_b_mem_0_param = 2'h0; // @[AsyncCrossing.scala:23:9] wire [1:0] auto_out_b_mem_0_size = 2'h0; // @[AsyncCrossing.scala:23:9] wire [1:0] auto_out_c_mem_0_size = 2'h0; // @[AsyncCrossing.scala:23:9] wire [1:0] auto_out_d_mem_0_param = 2'h0; // @[AsyncCrossing.scala:23:9] wire [1:0] nodeOut_b_mem_0_param = 2'h0; // @[MixedNode.scala:542:17] wire [1:0] nodeOut_b_mem_0_size = 2'h0; // @[MixedNode.scala:542:17] wire [1:0] nodeOut_c_mem_0_size = 2'h0; // @[MixedNode.scala:542:17] wire [1:0] nodeOut_d_mem_0_param = 2'h0; // @[MixedNode.scala:542:17] wire [3:0] auto_in_a_bits_mask = 4'hF; // @[AsyncCrossing.scala:23:9] wire [3:0] auto_out_a_mem_0_mask = 4'hF; // @[AsyncCrossing.scala:23:9] wire [3:0] nodeIn_a_bits_mask = 4'hF; // @[MixedNode.scala:551:17] wire [3:0] nodeOut_a_mem_0_mask = 4'hF; // @[MixedNode.scala:542:17] wire auto_in_a_bits_source = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_in_a_bits_corrupt = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_out_a_mem_0_source = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_out_a_mem_0_corrupt = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_out_b_mem_0_source = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_out_b_mem_0_corrupt = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_out_b_ridx = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_out_b_widx = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_out_b_safe_ridx_valid = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_out_b_safe_widx_valid = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_out_b_safe_source_reset_n = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_out_b_safe_sink_reset_n = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_out_c_mem_0_source = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_out_c_mem_0_corrupt = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_out_c_ridx = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_out_c_widx = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_out_c_safe_ridx_valid = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_out_c_safe_widx_valid = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_out_c_safe_source_reset_n = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_out_c_safe_sink_reset_n = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_out_d_mem_0_sink = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_out_d_mem_0_denied = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_out_d_mem_0_corrupt = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_out_e_mem_0_sink = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_out_e_ridx = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_out_e_widx = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_out_e_safe_ridx_valid = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_out_e_safe_widx_valid = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_out_e_safe_source_reset_n = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_out_e_safe_sink_reset_n = 1'h0; // @[AsyncCrossing.scala:23:9] wire nodeIn_a_bits_source = 1'h0; // @[MixedNode.scala:551:17] wire nodeIn_a_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17] wire nodeOut_a_mem_0_source = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_a_mem_0_corrupt = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_b_mem_0_source = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_b_mem_0_corrupt = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_b_ridx = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_b_widx = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_b_safe_ridx_valid = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_b_safe_widx_valid = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_b_safe_source_reset_n = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_b_safe_sink_reset_n = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_c_mem_0_source = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_c_mem_0_corrupt = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_c_ridx = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_c_widx = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_c_safe_ridx_valid = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_c_safe_widx_valid = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_c_safe_source_reset_n = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_c_safe_sink_reset_n = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_d_mem_0_sink = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_d_mem_0_denied = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_d_mem_0_corrupt = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_e_mem_0_sink = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_e_ridx = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_e_widx = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_e_safe_ridx_valid = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_e_safe_widx_valid = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_e_safe_source_reset_n = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_e_safe_sink_reset_n = 1'h0; // @[MixedNode.scala:542:17] wire [1:0] auto_in_a_bits_size = 2'h2; // @[AsyncCrossing.scala:23:9] wire [1:0] auto_out_a_mem_0_size = 2'h2; // @[AsyncCrossing.scala:23:9] wire [1:0] nodeIn_a_bits_size = 2'h2; // @[MixedNode.scala:551:17] wire [1:0] nodeOut_a_mem_0_size = 2'h2; // @[MixedNode.scala:542:17] wire [2:0] auto_in_a_bits_param = 3'h0; // @[AsyncCrossing.scala:23:9] wire [2:0] auto_out_a_mem_0_param = 3'h0; // @[AsyncCrossing.scala:23:9] wire [2:0] auto_out_b_mem_0_opcode = 3'h0; // @[AsyncCrossing.scala:23:9] wire [2:0] auto_out_c_mem_0_opcode = 3'h0; // @[AsyncCrossing.scala:23:9] wire [2:0] auto_out_c_mem_0_param = 3'h0; // @[AsyncCrossing.scala:23:9] wire nodeIn_a_ready; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_a_bits_param = 3'h0; // @[MixedNode.scala:551:17] wire [2:0] nodeOut_a_mem_0_param = 3'h0; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_b_mem_0_opcode = 3'h0; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_c_mem_0_opcode = 3'h0; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_c_mem_0_param = 3'h0; // @[MixedNode.scala:542:17] wire nodeIn_a_valid = auto_in_a_valid_0; // @[AsyncCrossing.scala:23:9] wire [2:0] nodeIn_a_bits_opcode = auto_in_a_bits_opcode_0; // @[AsyncCrossing.scala:23:9] wire [8:0] nodeIn_a_bits_address = auto_in_a_bits_address_0; // @[AsyncCrossing.scala:23:9] wire [31:0] nodeIn_a_bits_data = auto_in_a_bits_data_0; // @[AsyncCrossing.scala:23:9] wire nodeIn_d_ready = auto_in_d_ready_0; // @[AsyncCrossing.scala:23:9] wire nodeIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] nodeIn_d_bits_param; // @[MixedNode.scala:551:17] wire [1:0] nodeIn_d_bits_size; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_source; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_sink; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_denied; // @[MixedNode.scala:551:17] wire [31:0] nodeIn_d_bits_data; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_corrupt; // @[MixedNode.scala:551:17] wire [2:0] nodeOut_a_mem_0_opcode; // @[MixedNode.scala:542:17] wire [8:0] nodeOut_a_mem_0_address; // @[MixedNode.scala:542:17] wire [31:0] nodeOut_a_mem_0_data; // @[MixedNode.scala:542:17] wire nodeOut_a_ridx = auto_out_a_ridx_0; // @[AsyncCrossing.scala:23:9] wire nodeOut_a_widx; // @[MixedNode.scala:542:17] wire nodeOut_a_safe_ridx_valid = auto_out_a_safe_ridx_valid_0; // @[AsyncCrossing.scala:23:9] wire nodeOut_a_safe_widx_valid; // @[MixedNode.scala:542:17] wire nodeOut_a_safe_source_reset_n; // @[MixedNode.scala:542:17] wire nodeOut_a_safe_sink_reset_n = auto_out_a_safe_sink_reset_n_0; // @[AsyncCrossing.scala:23:9] wire [2:0] nodeOut_d_mem_0_opcode = auto_out_d_mem_0_opcode_0; // @[AsyncCrossing.scala:23:9] wire [1:0] nodeOut_d_mem_0_size = auto_out_d_mem_0_size_0; // @[AsyncCrossing.scala:23:9] wire nodeOut_d_mem_0_source = auto_out_d_mem_0_source_0; // @[AsyncCrossing.scala:23:9] wire [31:0] nodeOut_d_mem_0_data = auto_out_d_mem_0_data_0; // @[AsyncCrossing.scala:23:9] wire nodeOut_d_ridx; // @[MixedNode.scala:542:17] wire nodeOut_d_widx = auto_out_d_widx_0; // @[AsyncCrossing.scala:23:9] wire nodeOut_d_safe_ridx_valid; // @[MixedNode.scala:542:17] wire nodeOut_d_safe_widx_valid = auto_out_d_safe_widx_valid_0; // @[AsyncCrossing.scala:23:9] wire nodeOut_d_safe_source_reset_n = auto_out_d_safe_source_reset_n_0; // @[AsyncCrossing.scala:23:9] wire nodeOut_d_safe_sink_reset_n; // @[MixedNode.scala:542:17] wire auto_in_a_ready_0; // @[AsyncCrossing.scala:23:9] wire [2:0] auto_in_d_bits_opcode_0; // @[AsyncCrossing.scala:23:9] wire [1:0] auto_in_d_bits_param_0; // @[AsyncCrossing.scala:23:9] wire [1:0] auto_in_d_bits_size_0; // @[AsyncCrossing.scala:23:9] wire auto_in_d_bits_source_0; // @[AsyncCrossing.scala:23:9] wire auto_in_d_bits_sink_0; // @[AsyncCrossing.scala:23:9] wire auto_in_d_bits_denied_0; // @[AsyncCrossing.scala:23:9] wire [31:0] auto_in_d_bits_data_0; // @[AsyncCrossing.scala:23:9] wire auto_in_d_bits_corrupt_0; // @[AsyncCrossing.scala:23:9] wire auto_in_d_valid_0; // @[AsyncCrossing.scala:23:9] wire [2:0] auto_out_a_mem_0_opcode_0; // @[AsyncCrossing.scala:23:9] wire [8:0] auto_out_a_mem_0_address_0; // @[AsyncCrossing.scala:23:9] wire [31:0] auto_out_a_mem_0_data_0; // @[AsyncCrossing.scala:23:9] wire auto_out_a_safe_widx_valid_0; // @[AsyncCrossing.scala:23:9] wire auto_out_a_safe_source_reset_n_0; // @[AsyncCrossing.scala:23:9] wire auto_out_a_widx_0; // @[AsyncCrossing.scala:23:9] wire auto_out_d_safe_ridx_valid_0; // @[AsyncCrossing.scala:23:9] wire auto_out_d_safe_sink_reset_n_0; // @[AsyncCrossing.scala:23:9] wire auto_out_d_ridx_0; // @[AsyncCrossing.scala:23:9] assign auto_in_a_ready_0 = nodeIn_a_ready; // @[AsyncCrossing.scala:23:9] assign auto_in_d_valid_0 = nodeIn_d_valid; // @[AsyncCrossing.scala:23:9] assign auto_in_d_bits_opcode_0 = nodeIn_d_bits_opcode; // @[AsyncCrossing.scala:23:9] assign auto_in_d_bits_param_0 = nodeIn_d_bits_param; // @[AsyncCrossing.scala:23:9] assign auto_in_d_bits_size_0 = nodeIn_d_bits_size; // @[AsyncCrossing.scala:23:9] assign auto_in_d_bits_source_0 = nodeIn_d_bits_source; // @[AsyncCrossing.scala:23:9] assign auto_in_d_bits_sink_0 = nodeIn_d_bits_sink; // @[AsyncCrossing.scala:23:9] assign auto_in_d_bits_denied_0 = nodeIn_d_bits_denied; // @[AsyncCrossing.scala:23:9] assign auto_in_d_bits_data_0 = nodeIn_d_bits_data; // @[AsyncCrossing.scala:23:9] assign auto_in_d_bits_corrupt_0 = nodeIn_d_bits_corrupt; // @[AsyncCrossing.scala:23:9] assign auto_out_a_mem_0_opcode_0 = nodeOut_a_mem_0_opcode; // @[AsyncCrossing.scala:23:9] assign auto_out_a_mem_0_address_0 = nodeOut_a_mem_0_address; // @[AsyncCrossing.scala:23:9] assign auto_out_a_mem_0_data_0 = nodeOut_a_mem_0_data; // @[AsyncCrossing.scala:23:9] assign auto_out_a_widx_0 = nodeOut_a_widx; // @[AsyncCrossing.scala:23:9] assign auto_out_a_safe_widx_valid_0 = nodeOut_a_safe_widx_valid; // @[AsyncCrossing.scala:23:9] assign auto_out_a_safe_source_reset_n_0 = nodeOut_a_safe_source_reset_n; // @[AsyncCrossing.scala:23:9] assign auto_out_d_ridx_0 = nodeOut_d_ridx; // @[AsyncCrossing.scala:23:9] assign auto_out_d_safe_ridx_valid_0 = nodeOut_d_safe_ridx_valid; // @[AsyncCrossing.scala:23:9] assign auto_out_d_safe_sink_reset_n_0 = nodeOut_d_safe_sink_reset_n; // @[AsyncCrossing.scala:23:9] TLMonitor_39 monitor ( // @[Nodes.scala:27:25] .clock (clock), .reset (reset), .io_in_a_ready (nodeIn_a_ready), // @[MixedNode.scala:551:17] .io_in_a_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17] .io_in_a_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17] .io_in_a_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17] .io_in_a_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17] .io_in_d_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17] .io_in_d_valid (nodeIn_d_valid), // @[MixedNode.scala:551:17] .io_in_d_bits_opcode (nodeIn_d_bits_opcode), // @[MixedNode.scala:551:17] .io_in_d_bits_param (nodeIn_d_bits_param), // @[MixedNode.scala:551:17] .io_in_d_bits_size (nodeIn_d_bits_size), // @[MixedNode.scala:551:17] .io_in_d_bits_source (nodeIn_d_bits_source), // @[MixedNode.scala:551:17] .io_in_d_bits_sink (nodeIn_d_bits_sink), // @[MixedNode.scala:551:17] .io_in_d_bits_denied (nodeIn_d_bits_denied), // @[MixedNode.scala:551:17] .io_in_d_bits_data (nodeIn_d_bits_data), // @[MixedNode.scala:551:17] .io_in_d_bits_corrupt (nodeIn_d_bits_corrupt) // @[MixedNode.scala:551:17] ); // @[Nodes.scala:27:25] AsyncQueueSource_TLBundleA_a9d32s1k1z2u nodeOut_a_source ( // @[AsyncQueue.scala:220:24] .clock (clock), .reset (reset), .io_enq_ready (nodeIn_a_ready), .io_enq_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17] .io_enq_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17] .io_enq_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17] .io_enq_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17] .io_async_mem_0_opcode (nodeOut_a_mem_0_opcode), .io_async_mem_0_address (nodeOut_a_mem_0_address), .io_async_mem_0_data (nodeOut_a_mem_0_data), .io_async_ridx (nodeOut_a_ridx), // @[MixedNode.scala:542:17] .io_async_widx (nodeOut_a_widx), .io_async_safe_ridx_valid (nodeOut_a_safe_ridx_valid), // @[MixedNode.scala:542:17] .io_async_safe_widx_valid (nodeOut_a_safe_widx_valid), .io_async_safe_source_reset_n (nodeOut_a_safe_source_reset_n), .io_async_safe_sink_reset_n (nodeOut_a_safe_sink_reset_n) // @[MixedNode.scala:542:17] ); // @[AsyncQueue.scala:220:24] AsyncQueueSink_TLBundleD_a9d32s1k1z2u nodeIn_d_sink ( // @[AsyncQueue.scala:211:22] .clock (clock), .reset (reset), .io_deq_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17] .io_deq_valid (nodeIn_d_valid), .io_deq_bits_opcode (nodeIn_d_bits_opcode), .io_deq_bits_param (nodeIn_d_bits_param), .io_deq_bits_size (nodeIn_d_bits_size), .io_deq_bits_source (nodeIn_d_bits_source), .io_deq_bits_sink (nodeIn_d_bits_sink), .io_deq_bits_denied (nodeIn_d_bits_denied), .io_deq_bits_data (nodeIn_d_bits_data), .io_deq_bits_corrupt (nodeIn_d_bits_corrupt), .io_async_mem_0_opcode (nodeOut_d_mem_0_opcode), // @[MixedNode.scala:542:17] .io_async_mem_0_size (nodeOut_d_mem_0_size), // @[MixedNode.scala:542:17] .io_async_mem_0_source (nodeOut_d_mem_0_source), // @[MixedNode.scala:542:17] .io_async_mem_0_data (nodeOut_d_mem_0_data), // @[MixedNode.scala:542:17] .io_async_ridx (nodeOut_d_ridx), .io_async_widx (nodeOut_d_widx), // @[MixedNode.scala:542:17] .io_async_safe_ridx_valid (nodeOut_d_safe_ridx_valid), .io_async_safe_widx_valid (nodeOut_d_safe_widx_valid), // @[MixedNode.scala:542:17] .io_async_safe_source_reset_n (nodeOut_d_safe_source_reset_n), // @[MixedNode.scala:542:17] .io_async_safe_sink_reset_n (nodeOut_d_safe_sink_reset_n) ); // @[AsyncQueue.scala:211:22] assign auto_in_a_ready = auto_in_a_ready_0; // @[AsyncCrossing.scala:23:9] assign auto_in_d_valid = auto_in_d_valid_0; // @[AsyncCrossing.scala:23:9] assign auto_in_d_bits_opcode = auto_in_d_bits_opcode_0; // @[AsyncCrossing.scala:23:9] assign auto_in_d_bits_param = auto_in_d_bits_param_0; // @[AsyncCrossing.scala:23:9] assign auto_in_d_bits_size = auto_in_d_bits_size_0; // @[AsyncCrossing.scala:23:9] assign auto_in_d_bits_source = auto_in_d_bits_source_0; // @[AsyncCrossing.scala:23:9] assign auto_in_d_bits_sink = auto_in_d_bits_sink_0; // @[AsyncCrossing.scala:23:9] assign auto_in_d_bits_denied = auto_in_d_bits_denied_0; // @[AsyncCrossing.scala:23:9] assign auto_in_d_bits_data = auto_in_d_bits_data_0; // @[AsyncCrossing.scala:23:9] assign auto_in_d_bits_corrupt = auto_in_d_bits_corrupt_0; // @[AsyncCrossing.scala:23:9] assign auto_out_a_mem_0_opcode = auto_out_a_mem_0_opcode_0; // @[AsyncCrossing.scala:23:9] assign auto_out_a_mem_0_address = auto_out_a_mem_0_address_0; // @[AsyncCrossing.scala:23:9] assign auto_out_a_mem_0_data = auto_out_a_mem_0_data_0; // @[AsyncCrossing.scala:23:9] assign auto_out_a_widx = auto_out_a_widx_0; // @[AsyncCrossing.scala:23:9] assign auto_out_a_safe_widx_valid = auto_out_a_safe_widx_valid_0; // @[AsyncCrossing.scala:23:9] assign auto_out_a_safe_source_reset_n = auto_out_a_safe_source_reset_n_0; // @[AsyncCrossing.scala:23:9] assign auto_out_d_ridx = auto_out_d_ridx_0; // @[AsyncCrossing.scala:23:9] assign auto_out_d_safe_ridx_valid = auto_out_d_safe_ridx_valid_0; // @[AsyncCrossing.scala:23:9] assign auto_out_d_safe_sink_reset_n = auto_out_d_safe_sink_reset_n_0; // @[AsyncCrossing.scala:23:9] endmodule

Generate the Verilog code corresponding to the following Chisel files. File util.scala: //****************************************************************************** // Copyright (c) 2015 - 2019, The Regents of the University of California (Regents). // All Rights Reserved. See LICENSE and LICENSE.SiFive for license details. //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ // Utility Functions //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ package boom.v4.util import chisel3._ import chisel3.util._ import freechips.rocketchip.rocket.Instructions._ import freechips.rocketchip.rocket._ import freechips.rocketchip.util.{Str} import org.chipsalliance.cde.config.{Parameters} import freechips.rocketchip.tile.{TileKey} import boom.v4.common.{MicroOp} import boom.v4.exu.{BrUpdateInfo} /** * Object to XOR fold a input register of fullLength into a compressedLength. */ object Fold { def apply(input: UInt, compressedLength: Int, fullLength: Int): UInt = { val clen = compressedLength val hlen = fullLength if (hlen <= clen) { input } else { var res = 0.U(clen.W) var remaining = input.asUInt for (i <- 0 to hlen-1 by clen) { val len = if (i + clen > hlen ) (hlen - i) else clen require(len > 0) res = res(clen-1,0) ^ remaining(len-1,0) remaining = remaining >> len.U } res } } } /** * Object to check if MicroOp was killed due to a branch mispredict. * Uses "Fast" branch masks */ object IsKilledByBranch { def apply(brupdate: BrUpdateInfo, flush: Bool, uop: MicroOp): Bool = { return apply(brupdate, flush, uop.br_mask) } def apply(brupdate: BrUpdateInfo, flush: Bool, uop_mask: UInt): Bool = { return maskMatch(brupdate.b1.mispredict_mask, uop_mask) || flush } def apply[T <: boom.v4.common.HasBoomUOP](brupdate: BrUpdateInfo, flush: Bool, bundle: T): Bool = { return apply(brupdate, flush, bundle.uop) } def apply[T <: boom.v4.common.HasBoomUOP](brupdate: BrUpdateInfo, flush: Bool, bundle: Valid[T]): Bool = { return apply(brupdate, flush, bundle.bits) } } /** * Object to return new MicroOp with a new BR mask given a MicroOp mask * and old BR mask. */ object GetNewUopAndBrMask { def apply(uop: MicroOp, brupdate: BrUpdateInfo) (implicit p: Parameters): MicroOp = { val newuop = WireInit(uop) newuop.br_mask := uop.br_mask & ~brupdate.b1.resolve_mask newuop } } /** * Object to return a BR mask given a MicroOp mask and old BR mask. */ object GetNewBrMask { def apply(brupdate: BrUpdateInfo, uop: MicroOp): UInt = { return uop.br_mask & ~brupdate.b1.resolve_mask } def apply(brupdate: BrUpdateInfo, br_mask: UInt): UInt = { return br_mask & ~brupdate.b1.resolve_mask } } object UpdateBrMask { def apply(brupdate: BrUpdateInfo, uop: MicroOp): MicroOp = { val out = WireInit(uop) out.br_mask := GetNewBrMask(brupdate, uop) out } def apply[T <: boom.v4.common.HasBoomUOP](brupdate: BrUpdateInfo, bundle: T): T = { val out = WireInit(bundle) out.uop.br_mask := GetNewBrMask(brupdate, bundle.uop.br_mask) out } def apply[T <: boom.v4.common.HasBoomUOP](brupdate: BrUpdateInfo, flush: Bool, bundle: Valid[T]): Valid[T] = { val out = WireInit(bundle) out.bits.uop.br_mask := GetNewBrMask(brupdate, bundle.bits.uop.br_mask) out.valid := bundle.valid && !IsKilledByBranch(brupdate, flush, bundle.bits.uop.br_mask) out } } /** * Object to check if at least 1 bit matches in two masks */ object maskMatch { def apply(msk1: UInt, msk2: UInt): Bool = (msk1 & msk2) =/= 0.U } /** * Object to clear one bit in a mask given an index */ object clearMaskBit { def apply(msk: UInt, idx: UInt): UInt = (msk & ~(1.U << idx))(msk.getWidth-1, 0) } /** * Object to shift a register over by one bit and concat a new one */ object PerformShiftRegister { def apply(reg_val: UInt, new_bit: Bool): UInt = { reg_val := Cat(reg_val(reg_val.getWidth-1, 0).asUInt, new_bit.asUInt).asUInt reg_val } } /** * Object to shift a register over by one bit, wrapping the top bit around to the bottom * (XOR'ed with a new-bit), and evicting a bit at index HLEN. * This is used to simulate a longer HLEN-width shift register that is folded * down to a compressed CLEN. */ object PerformCircularShiftRegister { def apply(csr: UInt, new_bit: Bool, evict_bit: Bool, hlen: Int, clen: Int): UInt = { val carry = csr(clen-1) val newval = Cat(csr, new_bit ^ carry) ^ (evict_bit << (hlen % clen).U) newval } } /** * Object to increment an input value, wrapping it if * necessary. */ object WrapAdd { // "n" is the number of increments, so we wrap at n-1. def apply(value: UInt, amt: UInt, n: Int): UInt = { if (isPow2(n)) { (value + amt)(log2Ceil(n)-1,0) } else { val sum = Cat(0.U(1.W), value) + Cat(0.U(1.W), amt) Mux(sum >= n.U, sum - n.U, sum) } } } /** * Object to decrement an input value, wrapping it if * necessary. */ object WrapSub { // "n" is the number of increments, so we wrap to n-1. def apply(value: UInt, amt: Int, n: Int): UInt = { if (isPow2(n)) { (value - amt.U)(log2Ceil(n)-1,0) } else { val v = Cat(0.U(1.W), value) val b = Cat(0.U(1.W), amt.U) Mux(value >= amt.U, value - amt.U, n.U - amt.U + value) } } } /** * Object to increment an input value, wrapping it if * necessary. */ object WrapInc { // "n" is the number of increments, so we wrap at n-1. def apply(value: UInt, n: Int): UInt = { if (isPow2(n)) { (value + 1.U)(log2Ceil(n)-1,0) } else { val wrap = (value === (n-1).U) Mux(wrap, 0.U, value + 1.U) } } } /** * Object to decrement an input value, wrapping it if * necessary. */ object WrapDec { // "n" is the number of increments, so we wrap at n-1. def apply(value: UInt, n: Int): UInt = { if (isPow2(n)) { (value - 1.U)(log2Ceil(n)-1,0) } else { val wrap = (value === 0.U) Mux(wrap, (n-1).U, value - 1.U) } } } /** * Object to mask off lower bits of a PC to align to a "b" * Byte boundary. */ object AlignPCToBoundary { def apply(pc: UInt, b: Int): UInt = { // Invert for scenario where pc longer than b // (which would clear all bits above size(b)). ~(~pc | (b-1).U) } } /** * Object to rotate a signal left by one */ object RotateL1 { def apply(signal: UInt): UInt = { val w = signal.getWidth val out = Cat(signal(w-2,0), signal(w-1)) return out } } /** * Object to sext a value to a particular length. */ object Sext { def apply(x: UInt, length: Int): UInt = { if (x.getWidth == length) return x else return Cat(Fill(length-x.getWidth, x(x.getWidth-1)), x) } } /** * Object to translate from BOOM's special "packed immediate" to a 32b signed immediate * Asking for U-type gives it shifted up 12 bits. */ object ImmGen { import boom.v4.common.{LONGEST_IMM_SZ, IS_B, IS_I, IS_J, IS_S, IS_U, IS_N} def apply(i: UInt, isel: UInt): UInt = { val ip = Mux(isel === IS_N, 0.U(LONGEST_IMM_SZ.W), i) val sign = ip(LONGEST_IMM_SZ-1).asSInt val i30_20 = Mux(isel === IS_U, ip(18,8).asSInt, sign) val i19_12 = Mux(isel === IS_U || isel === IS_J, ip(7,0).asSInt, sign) val i11 = Mux(isel === IS_U, 0.S, Mux(isel === IS_J || isel === IS_B, ip(8).asSInt, sign)) val i10_5 = Mux(isel === IS_U, 0.S, ip(18,14).asSInt) val i4_1 = Mux(isel === IS_U, 0.S, ip(13,9).asSInt) val i0 = Mux(isel === IS_S || isel === IS_I, ip(8).asSInt, 0.S) return Cat(sign, i30_20, i19_12, i11, i10_5, i4_1, i0) } } /** * Object to see if an instruction is a JALR. */ object DebugIsJALR { def apply(inst: UInt): Bool = { // TODO Chisel not sure why this won't compile // val is_jalr = rocket.DecodeLogic(inst, List(Bool(false)), // Array( // JALR -> Bool(true))) inst(6,0) === "b1100111".U } } /** * Object to take an instruction and output its branch or jal target. Only used * for a debug assert (no where else would we jump straight from instruction * bits to a target). */ object DebugGetBJImm { def apply(inst: UInt): UInt = { // TODO Chisel not sure why this won't compile //val csignals = //rocket.DecodeLogic(inst, // List(Bool(false), Bool(false)), // Array( // BEQ -> List(Bool(true ), Bool(false)), // BNE -> List(Bool(true ), Bool(false)), // BGE -> List(Bool(true ), Bool(false)), // BGEU -> List(Bool(true ), Bool(false)), // BLT -> List(Bool(true ), Bool(false)), // BLTU -> List(Bool(true ), Bool(false)) // )) //val is_br :: nothing :: Nil = csignals val is_br = (inst(6,0) === "b1100011".U) val br_targ = Cat(Fill(12, inst(31)), Fill(8,inst(31)), inst(7), inst(30,25), inst(11,8), 0.U(1.W)) val jal_targ= Cat(Fill(12, inst(31)), inst(19,12), inst(20), inst(30,25), inst(24,21), 0.U(1.W)) Mux(is_br, br_targ, jal_targ) } } /** * Object to return the lowest bit position after the head. */ object AgePriorityEncoder { def apply(in: Seq[Bool], head: UInt): UInt = { val n = in.size val width = log2Ceil(in.size) val n_padded = 1 << width val temp_vec = (0 until n_padded).map(i => if (i < n) in(i) && i.U >= head else false.B) ++ in val idx = PriorityEncoder(temp_vec) idx(width-1, 0) //discard msb } } /** * Object to determine whether queue * index i0 is older than index i1. */ object IsOlder { def apply(i0: UInt, i1: UInt, head: UInt) = ((i0 < i1) ^ (i0 < head) ^ (i1 < head)) } object IsYoungerMask { def apply(i: UInt, head: UInt, n: Integer): UInt = { val hi_mask = ~MaskLower(UIntToOH(i)(n-1,0)) val lo_mask = ~MaskUpper(UIntToOH(head)(n-1,0)) Mux(i < head, hi_mask & lo_mask, hi_mask | lo_mask)(n-1,0) } } /** * Set all bits at or below the highest order '1'. */ object MaskLower { def apply(in: UInt) = { val n = in.getWidth (0 until n).map(i => in >> i.U).reduce(_|_) } } /** * Set all bits at or above the lowest order '1'. */ object MaskUpper { def apply(in: UInt) = { val n = in.getWidth (0 until n).map(i => (in << i.U)(n-1,0)).reduce(_|_) } } /** * Transpose a matrix of Chisel Vecs. */ object Transpose { def apply[T <: chisel3.Data](in: Vec[Vec[T]]) = { val n = in(0).size VecInit((0 until n).map(i => VecInit(in.map(row => row(i))))) } } /** * N-wide one-hot priority encoder. */ object SelectFirstN { def apply(in: UInt, n: Int) = { val sels = Wire(Vec(n, UInt(in.getWidth.W))) var mask = in for (i <- 0 until n) { sels(i) := PriorityEncoderOH(mask) mask = mask & ~sels(i) } sels } } /** * Connect the first k of n valid input interfaces to k output interfaces. */ class Compactor[T <: chisel3.Data](n: Int, k: Int, gen: T) extends Module { require(n >= k) val io = IO(new Bundle { val in = Vec(n, Flipped(DecoupledIO(gen))) val out = Vec(k, DecoupledIO(gen)) }) if (n == k) { io.out <> io.in } else { val counts = io.in.map(_.valid).scanLeft(1.U(k.W)) ((c,e) => Mux(e, (c<<1)(k-1,0), c)) val sels = Transpose(VecInit(counts map (c => VecInit(c.asBools)))) map (col => (col zip io.in.map(_.valid)) map {case (c,v) => c && v}) val in_readys = counts map (row => (row.asBools zip io.out.map(_.ready)) map {case (c,r) => c && r} reduce (_||_)) val out_valids = sels map (col => col.reduce(_||_)) val out_data = sels map (s => Mux1H(s, io.in.map(_.bits))) in_readys zip io.in foreach {case (r,i) => i.ready := r} out_valids zip out_data zip io.out foreach {case ((v,d),o) => o.valid := v; o.bits := d} } } /** * Create a queue that can be killed with a branch kill signal. * Assumption: enq.valid only high if not killed by branch (so don't check IsKilled on io.enq). */ class BranchKillableQueue[T <: boom.v4.common.HasBoomUOP](gen: T, entries: Int, flush_fn: boom.v4.common.MicroOp => Bool = u => true.B, fastDeq: Boolean = false) (implicit p: org.chipsalliance.cde.config.Parameters) extends boom.v4.common.BoomModule()(p) with boom.v4.common.HasBoomCoreParameters { val io = IO(new Bundle { val enq = Flipped(Decoupled(gen)) val deq = Decoupled(gen) val brupdate = Input(new BrUpdateInfo()) val flush = Input(Bool()) val empty = Output(Bool()) val count = Output(UInt(log2Ceil(entries).W)) }) if (fastDeq && entries > 1) { // Pipeline dequeue selection so the mux gets an entire cycle val main = Module(new BranchKillableQueue(gen, entries-1, flush_fn, false)) val out_reg = Reg(gen) val out_valid = RegInit(false.B) val out_uop = Reg(new MicroOp) main.io.enq <> io.enq main.io.brupdate := io.brupdate main.io.flush := io.flush io.empty := main.io.empty && !out_valid io.count := main.io.count + out_valid io.deq.valid := out_valid io.deq.bits := out_reg io.deq.bits.uop := out_uop out_uop := UpdateBrMask(io.brupdate, out_uop) out_valid := out_valid && !IsKilledByBranch(io.brupdate, false.B, out_uop) && !(io.flush && flush_fn(out_uop)) main.io.deq.ready := false.B when (io.deq.fire || !out_valid) { out_valid := main.io.deq.valid && !IsKilledByBranch(io.brupdate, false.B, main.io.deq.bits.uop) && !(io.flush && flush_fn(main.io.deq.bits.uop)) out_reg := main.io.deq.bits out_uop := UpdateBrMask(io.brupdate, main.io.deq.bits.uop) main.io.deq.ready := true.B } } else { val ram = Mem(entries, gen) val valids = RegInit(VecInit(Seq.fill(entries) {false.B})) val uops = Reg(Vec(entries, new MicroOp)) val enq_ptr = Counter(entries) val deq_ptr = Counter(entries) val maybe_full = RegInit(false.B) val ptr_match = enq_ptr.value === deq_ptr.value io.empty := ptr_match && !maybe_full val full = ptr_match && maybe_full val do_enq = WireInit(io.enq.fire && !IsKilledByBranch(io.brupdate, false.B, io.enq.bits.uop) && !(io.flush && flush_fn(io.enq.bits.uop))) val do_deq = WireInit((io.deq.ready || !valids(deq_ptr.value)) && !io.empty) for (i <- 0 until entries) { val mask = uops(i).br_mask val uop = uops(i) valids(i) := valids(i) && !IsKilledByBranch(io.brupdate, false.B, mask) && !(io.flush && flush_fn(uop)) when (valids(i)) { uops(i).br_mask := GetNewBrMask(io.brupdate, mask) } } when (do_enq) { ram(enq_ptr.value) := io.enq.bits valids(enq_ptr.value) := true.B uops(enq_ptr.value) := io.enq.bits.uop uops(enq_ptr.value).br_mask := GetNewBrMask(io.brupdate, io.enq.bits.uop) enq_ptr.inc() } when (do_deq) { valids(deq_ptr.value) := false.B deq_ptr.inc() } when (do_enq =/= do_deq) { maybe_full := do_enq } io.enq.ready := !full val out = Wire(gen) out := ram(deq_ptr.value) out.uop := uops(deq_ptr.value) io.deq.valid := !io.empty && valids(deq_ptr.value) io.deq.bits := out val ptr_diff = enq_ptr.value - deq_ptr.value if (isPow2(entries)) { io.count := Cat(maybe_full && ptr_match, ptr_diff) } else { io.count := Mux(ptr_match, Mux(maybe_full, entries.asUInt, 0.U), Mux(deq_ptr.value > enq_ptr.value, entries.asUInt + ptr_diff, ptr_diff)) } } } // ------------------------------------------ // Printf helper functions // ------------------------------------------ object BoolToChar { /** * Take in a Chisel Bool and convert it into a Str * based on the Chars given * * @param c_bool Chisel Bool * @param trueChar Scala Char if bool is true * @param falseChar Scala Char if bool is false * @return UInt ASCII Char for "trueChar" or "falseChar" */ def apply(c_bool: Bool, trueChar: Char, falseChar: Char = '-'): UInt = { Mux(c_bool, Str(trueChar), Str(falseChar)) } } object CfiTypeToChars { /** * Get a Vec of Strs that can be used for printing * * @param cfi_type specific cfi type * @return Vec of Strs (must be indexed to get specific char) */ def apply(cfi_type: UInt) = { val strings = Seq("----", "BR ", "JAL ", "JALR") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(cfi_type) } } object BpdTypeToChars { /** * Get a Vec of Strs that can be used for printing * * @param bpd_type specific bpd type * @return Vec of Strs (must be indexed to get specific char) */ def apply(bpd_type: UInt) = { val strings = Seq("BR ", "JUMP", "----", "RET ", "----", "CALL", "----", "----") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(bpd_type) } } object RobTypeToChars { /** * Get a Vec of Strs that can be used for printing * * @param rob_type specific rob type * @return Vec of Strs (must be indexed to get specific char) */ def apply(rob_type: UInt) = { val strings = Seq("RST", "NML", "RBK", " WT") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(rob_type) } } object XRegToChars { /** * Get a Vec of Strs that can be used for printing * * @param xreg specific register number * @return Vec of Strs (must be indexed to get specific char) */ def apply(xreg: UInt) = { val strings = Seq(" x0", " ra", " sp", " gp", " tp", " t0", " t1", " t2", " s0", " s1", " a0", " a1", " a2", " a3", " a4", " a5", " a6", " a7", " s2", " s3", " s4", " s5", " s6", " s7", " s8", " s9", "s10", "s11", " t3", " t4", " t5", " t6") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(xreg) } } object FPRegToChars { /** * Get a Vec of Strs that can be used for printing * * @param fpreg specific register number * @return Vec of Strs (must be indexed to get specific char) */ def apply(fpreg: UInt) = { val strings = Seq(" ft0", " ft1", " ft2", " ft3", " ft4", " ft5", " ft6", " ft7", " fs0", " fs1", " fa0", " fa1", " fa2", " fa3", " fa4", " fa5", " fa6", " fa7", " fs2", " fs3", " fs4", " fs5", " fs6", " fs7", " fs8", " fs9", "fs10", "fs11", " ft8", " ft9", "ft10", "ft11") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(fpreg) } } object BoomCoreStringPrefix { /** * Add prefix to BOOM strings (currently only adds the hartId) * * @param strs list of strings * @return String combining the list with the prefix per line */ def apply(strs: String*)(implicit p: Parameters) = { val prefix = "[C" + s"${p(TileKey).tileId}" + "] " strs.map(str => prefix + str + "\n").mkString("") } } class BranchKillablePipeline[T <: boom.v4.common.HasBoomUOP](gen: T, stages: Int) (implicit p: org.chipsalliance.cde.config.Parameters) extends boom.v4.common.BoomModule()(p) with boom.v4.common.HasBoomCoreParameters { val io = IO(new Bundle { val req = Input(Valid(gen)) val flush = Input(Bool()) val brupdate = Input(new BrUpdateInfo) val resp = Output(Vec(stages, Valid(gen))) }) require(stages > 0) val uops = Reg(Vec(stages, Valid(gen))) uops(0).valid := io.req.valid && !IsKilledByBranch(io.brupdate, io.flush, io.req.bits) uops(0).bits := UpdateBrMask(io.brupdate, io.req.bits) for (i <- 1 until stages) { uops(i).valid := uops(i-1).valid && !IsKilledByBranch(io.brupdate, io.flush, uops(i-1).bits) uops(i).bits := UpdateBrMask(io.brupdate, uops(i-1).bits) } for (i <- 0 until stages) { when (reset.asBool) { uops(i).valid := false.B } } io.resp := uops } File issue-slot.scala: //****************************************************************************** // Copyright (c) 2015 - 2018, The Regents of the University of California (Regents). // All Rights Reserved. See LICENSE and LICENSE.SiFive for license details. //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ // RISCV Processor Issue Slot Logic //-------------------------------------------------------------------------- //------------------------------------------------------------------------------ // // Note: stores (and AMOs) are "broken down" into 2 uops, but stored within a single issue-slot. // TODO XXX make a separate issueSlot for MemoryIssueSlots, and only they break apart stores. // TODO Disable ldspec for FP queue. package boom.v4.exu import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.Parameters import boom.v4.common._ import boom.v4.util._ class IssueSlotIO(val numWakeupPorts: Int)(implicit p: Parameters) extends BoomBundle { val valid = Output(Bool()) val will_be_valid = Output(Bool()) // TODO code review, do we need this signal so explicitely? val request = Output(Bool()) val grant = Input(Bool()) val iss_uop = Output(new MicroOp()) val in_uop = Input(Valid(new MicroOp())) // if valid, this WILL overwrite an entry! val out_uop = Output(new MicroOp()) val brupdate = Input(new BrUpdateInfo()) val kill = Input(Bool()) // pipeline flush val clear = Input(Bool()) // entry being moved elsewhere (not mutually exclusive with grant) val squash_grant = Input(Bool()) val wakeup_ports = Flipped(Vec(numWakeupPorts, Valid(new Wakeup))) val pred_wakeup_port = Flipped(Valid(UInt(log2Ceil(ftqSz).W))) val child_rebusys = Input(UInt(aluWidth.W)) } class IssueSlot(val numWakeupPorts: Int, val isMem: Boolean, val isFp: Boolean)(implicit p: Parameters) extends BoomModule { val io = IO(new IssueSlotIO(numWakeupPorts)) val slot_valid = RegInit(false.B) val slot_uop = Reg(new MicroOp()) val next_valid = WireInit(slot_valid) val next_uop = WireInit(UpdateBrMask(io.brupdate, slot_uop)) val killed = IsKilledByBranch(io.brupdate, io.kill, slot_uop) io.valid := slot_valid io.out_uop := next_uop io.will_be_valid := next_valid && !killed when (io.kill) { slot_valid := false.B } .elsewhen (io.in_uop.valid) { slot_valid := true.B } .elsewhen (io.clear) { slot_valid := false.B } .otherwise { slot_valid := next_valid && !killed } when (io.in_uop.valid) { slot_uop := io.in_uop.bits assert (!slot_valid || io.clear || io.kill) } .otherwise { slot_uop := next_uop } // Wakeups next_uop.iw_p1_bypass_hint := false.B next_uop.iw_p2_bypass_hint := false.B next_uop.iw_p3_bypass_hint := false.B next_uop.iw_p1_speculative_child := 0.U next_uop.iw_p2_speculative_child := 0.U val rebusied_prs1 = WireInit(false.B) val rebusied_prs2 = WireInit(false.B) val rebusied = rebusied_prs1 || rebusied_prs2 val prs1_matches = io.wakeup_ports.map { w => w.bits.uop.pdst === slot_uop.prs1 } val prs2_matches = io.wakeup_ports.map { w => w.bits.uop.pdst === slot_uop.prs2 } val prs3_matches = io.wakeup_ports.map { w => w.bits.uop.pdst === slot_uop.prs3 } val prs1_wakeups = (io.wakeup_ports zip prs1_matches).map { case (w,m) => w.valid && m } val prs2_wakeups = (io.wakeup_ports zip prs2_matches).map { case (w,m) => w.valid && m } val prs3_wakeups = (io.wakeup_ports zip prs3_matches).map { case (w,m) => w.valid && m } val prs1_rebusys = (io.wakeup_ports zip prs1_matches).map { case (w,m) => w.bits.rebusy && m } val prs2_rebusys = (io.wakeup_ports zip prs2_matches).map { case (w,m) => w.bits.rebusy && m } val bypassables = io.wakeup_ports.map { w => w.bits.bypassable } val speculative_masks = io.wakeup_ports.map { w => w.bits.speculative_mask } when (prs1_wakeups.reduce(_||_)) { next_uop.prs1_busy := false.B next_uop.iw_p1_speculative_child := Mux1H(prs1_wakeups, speculative_masks) next_uop.iw_p1_bypass_hint := Mux1H(prs1_wakeups, bypassables) } when ((prs1_rebusys.reduce(_||_) || ((io.child_rebusys & slot_uop.iw_p1_speculative_child) =/= 0.U)) && slot_uop.lrs1_rtype === RT_FIX) { next_uop.prs1_busy := true.B rebusied_prs1 := true.B } when (prs2_wakeups.reduce(_||_)) { next_uop.prs2_busy := false.B next_uop.iw_p2_speculative_child := Mux1H(prs2_wakeups, speculative_masks) next_uop.iw_p2_bypass_hint := Mux1H(prs2_wakeups, bypassables) } when ((prs2_rebusys.reduce(_||_) || ((io.child_rebusys & slot_uop.iw_p2_speculative_child) =/= 0.U)) && slot_uop.lrs2_rtype === RT_FIX) { next_uop.prs2_busy := true.B rebusied_prs2 := true.B } when (prs3_wakeups.reduce(_||_)) { next_uop.prs3_busy := false.B next_uop.iw_p3_bypass_hint := Mux1H(prs3_wakeups, bypassables) } when (io.pred_wakeup_port.valid && io.pred_wakeup_port.bits === slot_uop.ppred) { next_uop.ppred_busy := false.B } val iss_ready = !slot_uop.prs1_busy && !slot_uop.prs2_busy && !(slot_uop.ppred_busy && enableSFBOpt.B) && !(slot_uop.prs3_busy && isFp.B) val agen_ready = (slot_uop.fu_code(FC_AGEN) && !slot_uop.prs1_busy && !(slot_uop.ppred_busy && enableSFBOpt.B) && isMem.B) val dgen_ready = (slot_uop.fu_code(FC_DGEN) && !slot_uop.prs2_busy && !(slot_uop.ppred_busy && enableSFBOpt.B) && isMem.B) io.request := slot_valid && !slot_uop.iw_issued && ( iss_ready || agen_ready || dgen_ready ) io.iss_uop := slot_uop // Update state for current micro-op based on grant next_uop.iw_issued := false.B next_uop.iw_issued_partial_agen := false.B next_uop.iw_issued_partial_dgen := false.B when (io.grant && !io.squash_grant) { next_uop.iw_issued := true.B } if (isMem) { when (slot_uop.fu_code(FC_AGEN) && slot_uop.fu_code(FC_DGEN)) { when (agen_ready) { // Issue the AGEN, next slot entry is a DGEN when (io.grant && !io.squash_grant) { next_uop.iw_issued_partial_agen := true.B } io.iss_uop.fu_code(FC_AGEN) := true.B io.iss_uop.fu_code(FC_DGEN) := false.B } .otherwise { // Issue the DGEN, next slot entry is the AGEN when (io.grant && !io.squash_grant) { next_uop.iw_issued_partial_dgen := true.B } io.iss_uop.fu_code(FC_AGEN) := false.B io.iss_uop.fu_code(FC_DGEN) := true.B io.iss_uop.imm_sel := IS_N io.iss_uop.prs1 := slot_uop.prs2 io.iss_uop.lrs1_rtype := slot_uop.lrs2_rtype io.iss_uop.iw_p1_bypass_hint := slot_uop.iw_p2_bypass_hint } } .elsewhen (slot_uop.fu_code(FC_DGEN)) { io.iss_uop.imm_sel := IS_N io.iss_uop.prs1 := slot_uop.prs2 io.iss_uop.lrs1_rtype := slot_uop.lrs2_rtype io.iss_uop.iw_p1_bypass_hint := slot_uop.iw_p2_bypass_hint } io.iss_uop.lrs2_rtype := RT_X io.iss_uop.prs2 := io.iss_uop.prs1 // helps with DCE } when (slot_valid && slot_uop.iw_issued) { next_valid := rebusied if (isMem) { when (slot_uop.iw_issued_partial_agen) { next_valid := true.B when (!rebusied_prs1) { next_uop.fu_code(FC_AGEN) := false.B next_uop.fu_code(FC_DGEN) := true.B } } .elsewhen (slot_uop.iw_issued_partial_dgen) { next_valid := true.B when (!rebusied_prs2) { next_uop.fu_code(FC_AGEN) := true.B next_uop.fu_code(FC_DGEN) := false.B } } } } }

module IssueSlot_56( // @[issue-slot.scala:49:7] input clock, // @[issue-slot.scala:49:7] input reset, // @[issue-slot.scala:49:7] output io_valid, // @[issue-slot.scala:52:14] output io_will_be_valid, // @[issue-slot.scala:52:14] output io_request, // @[issue-slot.scala:52:14] input io_grant, // @[issue-slot.scala:52:14] output [31:0] io_iss_uop_inst, // @[issue-slot.scala:52:14] output [31:0] io_iss_uop_debug_inst, // @[issue-slot.scala:52:14] output io_iss_uop_is_rvc, // @[issue-slot.scala:52:14] output [39:0] io_iss_uop_debug_pc, // @[issue-slot.scala:52:14] output io_iss_uop_iq_type_0, // @[issue-slot.scala:52:14] output io_iss_uop_iq_type_1, // @[issue-slot.scala:52:14] output io_iss_uop_iq_type_2, // @[issue-slot.scala:52:14] output io_iss_uop_iq_type_3, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_0, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_1, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_2, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_3, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_4, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_5, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_6, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_7, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_8, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_9, // @[issue-slot.scala:52:14] output io_iss_uop_iw_issued, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14] output io_iss_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] output io_iss_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] output io_iss_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_dis_col_sel, // @[issue-slot.scala:52:14] output [15:0] io_iss_uop_br_mask, // @[issue-slot.scala:52:14] output [3:0] io_iss_uop_br_tag, // @[issue-slot.scala:52:14] output [3:0] io_iss_uop_br_type, // @[issue-slot.scala:52:14] output io_iss_uop_is_sfb, // @[issue-slot.scala:52:14] output io_iss_uop_is_fence, // @[issue-slot.scala:52:14] output io_iss_uop_is_fencei, // @[issue-slot.scala:52:14] output io_iss_uop_is_sfence, // @[issue-slot.scala:52:14] output io_iss_uop_is_amo, // @[issue-slot.scala:52:14] output io_iss_uop_is_eret, // @[issue-slot.scala:52:14] output io_iss_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14] output io_iss_uop_is_rocc, // @[issue-slot.scala:52:14] output io_iss_uop_is_mov, // @[issue-slot.scala:52:14] output [4:0] io_iss_uop_ftq_idx, // @[issue-slot.scala:52:14] output io_iss_uop_edge_inst, // @[issue-slot.scala:52:14] output [5:0] io_iss_uop_pc_lob, // @[issue-slot.scala:52:14] output io_iss_uop_taken, // @[issue-slot.scala:52:14] output io_iss_uop_imm_rename, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_imm_sel, // @[issue-slot.scala:52:14] output [4:0] io_iss_uop_pimm, // @[issue-slot.scala:52:14] output [19:0] io_iss_uop_imm_packed, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_op1_sel, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_op2_sel, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_div, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14] output [6:0] io_iss_uop_rob_idx, // @[issue-slot.scala:52:14] output [4:0] io_iss_uop_ldq_idx, // @[issue-slot.scala:52:14] output [4:0] io_iss_uop_stq_idx, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_rxq_idx, // @[issue-slot.scala:52:14] output [6:0] io_iss_uop_pdst, // @[issue-slot.scala:52:14] output [6:0] io_iss_uop_prs1, // @[issue-slot.scala:52:14] output [6:0] io_iss_uop_prs2, // @[issue-slot.scala:52:14] output [6:0] io_iss_uop_prs3, // @[issue-slot.scala:52:14] output [4:0] io_iss_uop_ppred, // @[issue-slot.scala:52:14] output io_iss_uop_prs1_busy, // @[issue-slot.scala:52:14] output io_iss_uop_prs2_busy, // @[issue-slot.scala:52:14] output io_iss_uop_prs3_busy, // @[issue-slot.scala:52:14] output io_iss_uop_ppred_busy, // @[issue-slot.scala:52:14] output [6:0] io_iss_uop_stale_pdst, // @[issue-slot.scala:52:14] output io_iss_uop_exception, // @[issue-slot.scala:52:14] output [63:0] io_iss_uop_exc_cause, // @[issue-slot.scala:52:14] output [4:0] io_iss_uop_mem_cmd, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_mem_size, // @[issue-slot.scala:52:14] output io_iss_uop_mem_signed, // @[issue-slot.scala:52:14] output io_iss_uop_uses_ldq, // @[issue-slot.scala:52:14] output io_iss_uop_uses_stq, // @[issue-slot.scala:52:14] output io_iss_uop_is_unique, // @[issue-slot.scala:52:14] output io_iss_uop_flush_on_commit, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_csr_cmd, // @[issue-slot.scala:52:14] output io_iss_uop_ldst_is_rs1, // @[issue-slot.scala:52:14] output [5:0] io_iss_uop_ldst, // @[issue-slot.scala:52:14] output [5:0] io_iss_uop_lrs1, // @[issue-slot.scala:52:14] output [5:0] io_iss_uop_lrs2, // @[issue-slot.scala:52:14] output [5:0] io_iss_uop_lrs3, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_dst_rtype, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_lrs1_rtype, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_lrs2_rtype, // @[issue-slot.scala:52:14] output io_iss_uop_frs3_en, // @[issue-slot.scala:52:14] output io_iss_uop_fcn_dw, // @[issue-slot.scala:52:14] output [4:0] io_iss_uop_fcn_op, // @[issue-slot.scala:52:14] output io_iss_uop_fp_val, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_fp_rm, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_fp_typ, // @[issue-slot.scala:52:14] output io_iss_uop_xcpt_pf_if, // @[issue-slot.scala:52:14] output io_iss_uop_xcpt_ae_if, // @[issue-slot.scala:52:14] output io_iss_uop_xcpt_ma_if, // @[issue-slot.scala:52:14] output io_iss_uop_bp_debug_if, // @[issue-slot.scala:52:14] output io_iss_uop_bp_xcpt_if, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_debug_fsrc, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_debug_tsrc, // @[issue-slot.scala:52:14] input io_in_uop_valid, // @[issue-slot.scala:52:14] input [31:0] io_in_uop_bits_inst, // @[issue-slot.scala:52:14] input [31:0] io_in_uop_bits_debug_inst, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_rvc, // @[issue-slot.scala:52:14] input [39:0] io_in_uop_bits_debug_pc, // @[issue-slot.scala:52:14] input io_in_uop_bits_iq_type_0, // @[issue-slot.scala:52:14] input io_in_uop_bits_iq_type_1, // @[issue-slot.scala:52:14] input io_in_uop_bits_iq_type_2, // @[issue-slot.scala:52:14] input io_in_uop_bits_iq_type_3, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_0, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_1, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_2, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_3, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_4, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_5, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_6, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_7, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_8, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_9, // @[issue-slot.scala:52:14] input io_in_uop_bits_iw_issued, // @[issue-slot.scala:52:14] input [2:0] io_in_uop_bits_iw_p1_speculative_child, // @[issue-slot.scala:52:14] input [2:0] io_in_uop_bits_iw_p2_speculative_child, // @[issue-slot.scala:52:14] input io_in_uop_bits_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] input io_in_uop_bits_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] input io_in_uop_bits_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] input [2:0] io_in_uop_bits_dis_col_sel, // @[issue-slot.scala:52:14] input [15:0] io_in_uop_bits_br_mask, // @[issue-slot.scala:52:14] input [3:0] io_in_uop_bits_br_tag, // @[issue-slot.scala:52:14] input [3:0] io_in_uop_bits_br_type, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_sfb, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_fence, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_fencei, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_sfence, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_amo, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_eret, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_sys_pc2epc, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_rocc, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_mov, // @[issue-slot.scala:52:14] input [4:0] io_in_uop_bits_ftq_idx, // @[issue-slot.scala:52:14] input io_in_uop_bits_edge_inst, // @[issue-slot.scala:52:14] input [5:0] io_in_uop_bits_pc_lob, // @[issue-slot.scala:52:14] input io_in_uop_bits_taken, // @[issue-slot.scala:52:14] input io_in_uop_bits_imm_rename, // @[issue-slot.scala:52:14] input [2:0] io_in_uop_bits_imm_sel, // @[issue-slot.scala:52:14] input [4:0] io_in_uop_bits_pimm, // @[issue-slot.scala:52:14] input [19:0] io_in_uop_bits_imm_packed, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_op1_sel, // @[issue-slot.scala:52:14] input [2:0] io_in_uop_bits_op2_sel, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_ldst, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_wen, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_ren1, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_ren2, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_ren3, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_swap12, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_swap23, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_fromint, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_toint, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_fma, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_div, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_wflags, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_vec, // @[issue-slot.scala:52:14] input [6:0] io_in_uop_bits_rob_idx, // @[issue-slot.scala:52:14] input [4:0] io_in_uop_bits_ldq_idx, // @[issue-slot.scala:52:14] input [4:0] io_in_uop_bits_stq_idx, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_rxq_idx, // @[issue-slot.scala:52:14] input [6:0] io_in_uop_bits_pdst, // @[issue-slot.scala:52:14] input [6:0] io_in_uop_bits_prs1, // @[issue-slot.scala:52:14] input [6:0] io_in_uop_bits_prs2, // @[issue-slot.scala:52:14] input [6:0] io_in_uop_bits_prs3, // @[issue-slot.scala:52:14] input [4:0] io_in_uop_bits_ppred, // @[issue-slot.scala:52:14] input io_in_uop_bits_prs1_busy, // @[issue-slot.scala:52:14] input io_in_uop_bits_prs2_busy, // @[issue-slot.scala:52:14] input io_in_uop_bits_prs3_busy, // @[issue-slot.scala:52:14] input io_in_uop_bits_ppred_busy, // @[issue-slot.scala:52:14] input [6:0] io_in_uop_bits_stale_pdst, // @[issue-slot.scala:52:14] input io_in_uop_bits_exception, // @[issue-slot.scala:52:14] input [63:0] io_in_uop_bits_exc_cause, // @[issue-slot.scala:52:14] input [4:0] io_in_uop_bits_mem_cmd, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_mem_size, // @[issue-slot.scala:52:14] input io_in_uop_bits_mem_signed, // @[issue-slot.scala:52:14] input io_in_uop_bits_uses_ldq, // @[issue-slot.scala:52:14] input io_in_uop_bits_uses_stq, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_unique, // @[issue-slot.scala:52:14] input io_in_uop_bits_flush_on_commit, // @[issue-slot.scala:52:14] input [2:0] io_in_uop_bits_csr_cmd, // @[issue-slot.scala:52:14] input io_in_uop_bits_ldst_is_rs1, // @[issue-slot.scala:52:14] input [5:0] io_in_uop_bits_ldst, // @[issue-slot.scala:52:14] input [5:0] io_in_uop_bits_lrs1, // @[issue-slot.scala:52:14] input [5:0] io_in_uop_bits_lrs2, // @[issue-slot.scala:52:14] input [5:0] io_in_uop_bits_lrs3, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_dst_rtype, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_lrs1_rtype, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_lrs2_rtype, // @[issue-slot.scala:52:14] input io_in_uop_bits_frs3_en, // @[issue-slot.scala:52:14] input io_in_uop_bits_fcn_dw, // @[issue-slot.scala:52:14] input [4:0] io_in_uop_bits_fcn_op, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_val, // @[issue-slot.scala:52:14] input [2:0] io_in_uop_bits_fp_rm, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_fp_typ, // @[issue-slot.scala:52:14] input io_in_uop_bits_xcpt_pf_if, // @[issue-slot.scala:52:14] input io_in_uop_bits_xcpt_ae_if, // @[issue-slot.scala:52:14] input io_in_uop_bits_xcpt_ma_if, // @[issue-slot.scala:52:14] input io_in_uop_bits_bp_debug_if, // @[issue-slot.scala:52:14] input io_in_uop_bits_bp_xcpt_if, // @[issue-slot.scala:52:14] input [2:0] io_in_uop_bits_debug_fsrc, // @[issue-slot.scala:52:14] input [2:0] io_in_uop_bits_debug_tsrc, // @[issue-slot.scala:52:14] output [31:0] io_out_uop_inst, // @[issue-slot.scala:52:14] output [31:0] io_out_uop_debug_inst, // @[issue-slot.scala:52:14] output io_out_uop_is_rvc, // @[issue-slot.scala:52:14] output [39:0] io_out_uop_debug_pc, // @[issue-slot.scala:52:14] output io_out_uop_iq_type_0, // @[issue-slot.scala:52:14] output io_out_uop_iq_type_1, // @[issue-slot.scala:52:14] output io_out_uop_iq_type_2, // @[issue-slot.scala:52:14] output io_out_uop_iq_type_3, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_0, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_1, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_2, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_3, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_4, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_5, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_6, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_7, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_8, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_9, // @[issue-slot.scala:52:14] output io_out_uop_iw_issued, // @[issue-slot.scala:52:14] output [2:0] io_out_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14] output [2:0] io_out_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14] output io_out_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] output io_out_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] output io_out_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] output [2:0] io_out_uop_dis_col_sel, // @[issue-slot.scala:52:14] output [15:0] io_out_uop_br_mask, // @[issue-slot.scala:52:14] output [3:0] io_out_uop_br_tag, // @[issue-slot.scala:52:14] output [3:0] io_out_uop_br_type, // @[issue-slot.scala:52:14] output io_out_uop_is_sfb, // @[issue-slot.scala:52:14] output io_out_uop_is_fence, // @[issue-slot.scala:52:14] output io_out_uop_is_fencei, // @[issue-slot.scala:52:14] output io_out_uop_is_sfence, // @[issue-slot.scala:52:14] output io_out_uop_is_amo, // @[issue-slot.scala:52:14] output io_out_uop_is_eret, // @[issue-slot.scala:52:14] output io_out_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14] output io_out_uop_is_rocc, // @[issue-slot.scala:52:14] output io_out_uop_is_mov, // @[issue-slot.scala:52:14] output [4:0] io_out_uop_ftq_idx, // @[issue-slot.scala:52:14] output io_out_uop_edge_inst, // @[issue-slot.scala:52:14] output [5:0] io_out_uop_pc_lob, // @[issue-slot.scala:52:14] output io_out_uop_taken, // @[issue-slot.scala:52:14] output io_out_uop_imm_rename, // @[issue-slot.scala:52:14] output [2:0] io_out_uop_imm_sel, // @[issue-slot.scala:52:14] output [4:0] io_out_uop_pimm, // @[issue-slot.scala:52:14] output [19:0] io_out_uop_imm_packed, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_op1_sel, // @[issue-slot.scala:52:14] output [2:0] io_out_uop_op2_sel, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_div, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14] output [6:0] io_out_uop_rob_idx, // @[issue-slot.scala:52:14] output [4:0] io_out_uop_ldq_idx, // @[issue-slot.scala:52:14] output [4:0] io_out_uop_stq_idx, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_rxq_idx, // @[issue-slot.scala:52:14] output [6:0] io_out_uop_pdst, // @[issue-slot.scala:52:14] output [6:0] io_out_uop_prs1, // @[issue-slot.scala:52:14] output [6:0] io_out_uop_prs2, // @[issue-slot.scala:52:14] output [6:0] io_out_uop_prs3, // @[issue-slot.scala:52:14] output [4:0] io_out_uop_ppred, // @[issue-slot.scala:52:14] output io_out_uop_prs1_busy, // @[issue-slot.scala:52:14] output io_out_uop_prs2_busy, // @[issue-slot.scala:52:14] output io_out_uop_prs3_busy, // @[issue-slot.scala:52:14] output io_out_uop_ppred_busy, // @[issue-slot.scala:52:14] output [6:0] io_out_uop_stale_pdst, // @[issue-slot.scala:52:14] output io_out_uop_exception, // @[issue-slot.scala:52:14] output [63:0] io_out_uop_exc_cause, // @[issue-slot.scala:52:14] output [4:0] io_out_uop_mem_cmd, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_mem_size, // @[issue-slot.scala:52:14] output io_out_uop_mem_signed, // @[issue-slot.scala:52:14] output io_out_uop_uses_ldq, // @[issue-slot.scala:52:14] output io_out_uop_uses_stq, // @[issue-slot.scala:52:14] output io_out_uop_is_unique, // @[issue-slot.scala:52:14] output io_out_uop_flush_on_commit, // @[issue-slot.scala:52:14] output [2:0] io_out_uop_csr_cmd, // @[issue-slot.scala:52:14] output io_out_uop_ldst_is_rs1, // @[issue-slot.scala:52:14] output [5:0] io_out_uop_ldst, // @[issue-slot.scala:52:14] output [5:0] io_out_uop_lrs1, // @[issue-slot.scala:52:14] output [5:0] io_out_uop_lrs2, // @[issue-slot.scala:52:14] output [5:0] io_out_uop_lrs3, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_dst_rtype, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_lrs1_rtype, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_lrs2_rtype, // @[issue-slot.scala:52:14] output io_out_uop_frs3_en, // @[issue-slot.scala:52:14] output io_out_uop_fcn_dw, // @[issue-slot.scala:52:14] output [4:0] io_out_uop_fcn_op, // @[issue-slot.scala:52:14] output io_out_uop_fp_val, // @[issue-slot.scala:52:14] output [2:0] io_out_uop_fp_rm, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_fp_typ, // @[issue-slot.scala:52:14] output io_out_uop_xcpt_pf_if, // @[issue-slot.scala:52:14] output io_out_uop_xcpt_ae_if, // @[issue-slot.scala:52:14] output io_out_uop_xcpt_ma_if, // @[issue-slot.scala:52:14] output io_out_uop_bp_debug_if, // @[issue-slot.scala:52:14] output io_out_uop_bp_xcpt_if, // @[issue-slot.scala:52:14] output [2:0] io_out_uop_debug_fsrc, // @[issue-slot.scala:52:14] output [2:0] io_out_uop_debug_tsrc, // @[issue-slot.scala:52:14] input [15:0] io_brupdate_b1_resolve_mask, // @[issue-slot.scala:52:14] input [15:0] io_brupdate_b1_mispredict_mask, // @[issue-slot.scala:52:14] input [31:0] io_brupdate_b2_uop_inst, // @[issue-slot.scala:52:14] input [31:0] io_brupdate_b2_uop_debug_inst, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_rvc, // @[issue-slot.scala:52:14] input [39:0] io_brupdate_b2_uop_debug_pc, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iq_type_0, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iq_type_1, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iq_type_2, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iq_type_3, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_0, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_1, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_2, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_3, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_4, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_5, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_6, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_7, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_8, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_9, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iw_issued, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iw_issued_partial_agen, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iw_issued_partial_dgen, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_dis_col_sel, // @[issue-slot.scala:52:14] input [15:0] io_brupdate_b2_uop_br_mask, // @[issue-slot.scala:52:14] input [3:0] io_brupdate_b2_uop_br_tag, // @[issue-slot.scala:52:14] input [3:0] io_brupdate_b2_uop_br_type, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_sfb, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_fence, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_fencei, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_sfence, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_amo, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_eret, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_rocc, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_mov, // @[issue-slot.scala:52:14] input [4:0] io_brupdate_b2_uop_ftq_idx, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_edge_inst, // @[issue-slot.scala:52:14] input [5:0] io_brupdate_b2_uop_pc_lob, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_taken, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_imm_rename, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_imm_sel, // @[issue-slot.scala:52:14] input [4:0] io_brupdate_b2_uop_pimm, // @[issue-slot.scala:52:14] input [19:0] io_brupdate_b2_uop_imm_packed, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_op1_sel, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_op2_sel, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_div, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14] input [6:0] io_brupdate_b2_uop_rob_idx, // @[issue-slot.scala:52:14] input [4:0] io_brupdate_b2_uop_ldq_idx, // @[issue-slot.scala:52:14] input [4:0] io_brupdate_b2_uop_stq_idx, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_rxq_idx, // @[issue-slot.scala:52:14] input [6:0] io_brupdate_b2_uop_pdst, // @[issue-slot.scala:52:14] input [6:0] io_brupdate_b2_uop_prs1, // @[issue-slot.scala:52:14] input [6:0] io_brupdate_b2_uop_prs2, // @[issue-slot.scala:52:14] input [6:0] io_brupdate_b2_uop_prs3, // @[issue-slot.scala:52:14] input [4:0] io_brupdate_b2_uop_ppred, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_prs1_busy, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_prs2_busy, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_prs3_busy, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_ppred_busy, // @[issue-slot.scala:52:14] input [6:0] io_brupdate_b2_uop_stale_pdst, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_exception, // @[issue-slot.scala:52:14] input [63:0] io_brupdate_b2_uop_exc_cause, // @[issue-slot.scala:52:14] input [4:0] io_brupdate_b2_uop_mem_cmd, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_mem_size, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_mem_signed, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_uses_ldq, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_uses_stq, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_unique, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_flush_on_commit, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_csr_cmd, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_ldst_is_rs1, // @[issue-slot.scala:52:14] input [5:0] io_brupdate_b2_uop_ldst, // @[issue-slot.scala:52:14] input [5:0] io_brupdate_b2_uop_lrs1, // @[issue-slot.scala:52:14] input [5:0] io_brupdate_b2_uop_lrs2, // @[issue-slot.scala:52:14] input [5:0] io_brupdate_b2_uop_lrs3, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_dst_rtype, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_lrs1_rtype, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_lrs2_rtype, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_frs3_en, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fcn_dw, // @[issue-slot.scala:52:14] input [4:0] io_brupdate_b2_uop_fcn_op, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_val, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_fp_rm, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_fp_typ, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_xcpt_pf_if, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_xcpt_ae_if, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_xcpt_ma_if, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_bp_debug_if, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_bp_xcpt_if, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_debug_fsrc, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_debug_tsrc, // @[issue-slot.scala:52:14] input io_brupdate_b2_mispredict, // @[issue-slot.scala:52:14] input io_brupdate_b2_taken, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_cfi_type, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_pc_sel, // @[issue-slot.scala:52:14] input [39:0] io_brupdate_b2_jalr_target, // @[issue-slot.scala:52:14] input [20:0] io_brupdate_b2_target_offset, // @[issue-slot.scala:52:14] input io_kill, // @[issue-slot.scala:52:14] input io_squash_grant, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_valid, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_0_bits_uop_inst, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_0_bits_uop_debug_inst, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_rvc, // @[issue-slot.scala:52:14] input [39:0] io_wakeup_ports_0_bits_uop_debug_pc, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iq_type_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iq_type_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iq_type_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iq_type_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_4, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_5, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_6, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_7, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_8, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_9, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iw_issued, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iw_issued_partial_agen, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_dis_col_sel, // @[issue-slot.scala:52:14] input [15:0] io_wakeup_ports_0_bits_uop_br_mask, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_0_bits_uop_br_tag, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_0_bits_uop_br_type, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_sfb, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_fence, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_fencei, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_sfence, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_amo, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_eret, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_rocc, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_mov, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_0_bits_uop_ftq_idx, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_edge_inst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_0_bits_uop_pc_lob, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_taken, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_imm_rename, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_imm_sel, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_0_bits_uop_pimm, // @[issue-slot.scala:52:14] input [19:0] io_wakeup_ports_0_bits_uop_imm_packed, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_op1_sel, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_op2_sel, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_div, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_0_bits_uop_rob_idx, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_0_bits_uop_ldq_idx, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_0_bits_uop_stq_idx, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_rxq_idx, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_0_bits_uop_pdst, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_0_bits_uop_prs1, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_0_bits_uop_prs2, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_0_bits_uop_prs3, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_0_bits_uop_ppred, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_prs1_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_prs2_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_prs3_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_ppred_busy, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_0_bits_uop_stale_pdst, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_exception, // @[issue-slot.scala:52:14] input [63:0] io_wakeup_ports_0_bits_uop_exc_cause, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_0_bits_uop_mem_cmd, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_mem_size, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_mem_signed, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_uses_ldq, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_uses_stq, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_unique, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_flush_on_commit, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_csr_cmd, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_ldst_is_rs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_0_bits_uop_ldst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_0_bits_uop_lrs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_0_bits_uop_lrs2, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_0_bits_uop_lrs3, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_dst_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_lrs1_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_lrs2_rtype, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_frs3_en, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fcn_dw, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_0_bits_uop_fcn_op, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_val, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_fp_rm, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_fp_typ, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_xcpt_pf_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_xcpt_ae_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_xcpt_ma_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_bp_debug_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_bp_xcpt_if, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_debug_fsrc, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_debug_tsrc, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_bypassable, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_speculative_mask, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_rebusy, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_valid, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_1_bits_uop_inst, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_1_bits_uop_debug_inst, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_rvc, // @[issue-slot.scala:52:14] input [39:0] io_wakeup_ports_1_bits_uop_debug_pc, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iq_type_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iq_type_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iq_type_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iq_type_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_4, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_5, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_6, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_7, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_8, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_9, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iw_issued, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iw_issued_partial_agen, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_dis_col_sel, // @[issue-slot.scala:52:14] input [15:0] io_wakeup_ports_1_bits_uop_br_mask, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_1_bits_uop_br_tag, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_1_bits_uop_br_type, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_sfb, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_fence, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_fencei, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_sfence, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_amo, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_eret, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_rocc, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_mov, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_1_bits_uop_ftq_idx, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_edge_inst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_1_bits_uop_pc_lob, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_taken, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_imm_rename, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_imm_sel, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_1_bits_uop_pimm, // @[issue-slot.scala:52:14] input [19:0] io_wakeup_ports_1_bits_uop_imm_packed, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_op1_sel, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_op2_sel, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_div, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_1_bits_uop_rob_idx, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_1_bits_uop_ldq_idx, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_1_bits_uop_stq_idx, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_rxq_idx, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_1_bits_uop_pdst, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_1_bits_uop_prs1, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_1_bits_uop_prs2, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_1_bits_uop_prs3, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_1_bits_uop_ppred, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_prs1_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_prs2_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_prs3_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_ppred_busy, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_1_bits_uop_stale_pdst, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_exception, // @[issue-slot.scala:52:14] input [63:0] io_wakeup_ports_1_bits_uop_exc_cause, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_1_bits_uop_mem_cmd, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_mem_size, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_mem_signed, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_uses_ldq, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_uses_stq, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_unique, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_flush_on_commit, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_csr_cmd, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_ldst_is_rs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_1_bits_uop_ldst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_1_bits_uop_lrs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_1_bits_uop_lrs2, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_1_bits_uop_lrs3, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_dst_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_lrs1_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_lrs2_rtype, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_frs3_en, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fcn_dw, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_1_bits_uop_fcn_op, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_val, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_fp_rm, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_fp_typ, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_xcpt_pf_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_xcpt_ae_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_xcpt_ma_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_bp_debug_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_bp_xcpt_if, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_debug_fsrc, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_debug_tsrc, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_valid, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_2_bits_uop_inst, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_2_bits_uop_debug_inst, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_rvc, // @[issue-slot.scala:52:14] input [39:0] io_wakeup_ports_2_bits_uop_debug_pc, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_iq_type_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_iq_type_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_iq_type_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_iq_type_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_4, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_5, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_6, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_7, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_8, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_9, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_iw_issued, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_2_bits_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_2_bits_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_2_bits_uop_dis_col_sel, // @[issue-slot.scala:52:14] input [15:0] io_wakeup_ports_2_bits_uop_br_mask, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_2_bits_uop_br_tag, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_2_bits_uop_br_type, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_sfb, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_fence, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_fencei, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_sfence, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_amo, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_eret, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_rocc, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_mov, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_2_bits_uop_ftq_idx, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_edge_inst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_2_bits_uop_pc_lob, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_taken, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_imm_rename, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_2_bits_uop_imm_sel, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_2_bits_uop_pimm, // @[issue-slot.scala:52:14] input [19:0] io_wakeup_ports_2_bits_uop_imm_packed, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_op1_sel, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_2_bits_uop_op2_sel, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_div, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_2_bits_uop_rob_idx, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_2_bits_uop_ldq_idx, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_2_bits_uop_stq_idx, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_rxq_idx, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_2_bits_uop_pdst, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_2_bits_uop_prs1, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_2_bits_uop_prs2, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_2_bits_uop_prs3, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_2_bits_uop_ppred, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_prs1_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_prs2_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_prs3_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_ppred_busy, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_2_bits_uop_stale_pdst, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_exception, // @[issue-slot.scala:52:14] input [63:0] io_wakeup_ports_2_bits_uop_exc_cause, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_2_bits_uop_mem_cmd, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_mem_size, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_mem_signed, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_uses_ldq, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_uses_stq, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_unique, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_flush_on_commit, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_2_bits_uop_csr_cmd, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_ldst_is_rs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_2_bits_uop_ldst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_2_bits_uop_lrs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_2_bits_uop_lrs2, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_2_bits_uop_lrs3, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_dst_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_lrs1_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_lrs2_rtype, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_frs3_en, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fcn_dw, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_2_bits_uop_fcn_op, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_val, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_2_bits_uop_fp_rm, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_fp_typ, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_xcpt_pf_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_xcpt_ae_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_xcpt_ma_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_bp_debug_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_bp_xcpt_if, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_2_bits_uop_debug_fsrc, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_2_bits_uop_debug_tsrc, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_valid, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_3_bits_uop_inst, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_3_bits_uop_debug_inst, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_rvc, // @[issue-slot.scala:52:14] input [39:0] io_wakeup_ports_3_bits_uop_debug_pc, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_iq_type_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_iq_type_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_iq_type_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_iq_type_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_4, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_5, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_6, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_7, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_8, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_9, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_iw_issued, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_3_bits_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_3_bits_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_3_bits_uop_dis_col_sel, // @[issue-slot.scala:52:14] input [15:0] io_wakeup_ports_3_bits_uop_br_mask, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_3_bits_uop_br_tag, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_3_bits_uop_br_type, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_sfb, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_fence, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_fencei, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_sfence, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_amo, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_eret, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_rocc, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_mov, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_3_bits_uop_ftq_idx, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_edge_inst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_3_bits_uop_pc_lob, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_taken, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_imm_rename, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_3_bits_uop_imm_sel, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_3_bits_uop_pimm, // @[issue-slot.scala:52:14] input [19:0] io_wakeup_ports_3_bits_uop_imm_packed, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_op1_sel, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_3_bits_uop_op2_sel, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_div, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_3_bits_uop_rob_idx, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_3_bits_uop_ldq_idx, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_3_bits_uop_stq_idx, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_rxq_idx, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_3_bits_uop_pdst, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_3_bits_uop_prs1, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_3_bits_uop_prs2, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_3_bits_uop_prs3, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_3_bits_uop_ppred, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_prs1_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_prs2_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_prs3_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_ppred_busy, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_3_bits_uop_stale_pdst, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_exception, // @[issue-slot.scala:52:14] input [63:0] io_wakeup_ports_3_bits_uop_exc_cause, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_3_bits_uop_mem_cmd, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_mem_size, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_mem_signed, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_uses_ldq, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_uses_stq, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_unique, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_flush_on_commit, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_3_bits_uop_csr_cmd, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_ldst_is_rs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_3_bits_uop_ldst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_3_bits_uop_lrs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_3_bits_uop_lrs2, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_3_bits_uop_lrs3, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_dst_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_lrs1_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_lrs2_rtype, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_frs3_en, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fcn_dw, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_3_bits_uop_fcn_op, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_val, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_3_bits_uop_fp_rm, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_fp_typ, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_xcpt_pf_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_xcpt_ae_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_xcpt_ma_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_bp_debug_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_bp_xcpt_if, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_3_bits_uop_debug_fsrc, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_3_bits_uop_debug_tsrc, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_valid, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_4_bits_uop_inst, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_4_bits_uop_debug_inst, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_is_rvc, // @[issue-slot.scala:52:14] input [39:0] io_wakeup_ports_4_bits_uop_debug_pc, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_iq_type_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_iq_type_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_iq_type_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_iq_type_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fu_code_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fu_code_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fu_code_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fu_code_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fu_code_4, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fu_code_5, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fu_code_6, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fu_code_7, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fu_code_8, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fu_code_9, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_iw_issued, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_4_bits_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_4_bits_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_4_bits_uop_dis_col_sel, // @[issue-slot.scala:52:14] input [15:0] io_wakeup_ports_4_bits_uop_br_mask, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_4_bits_uop_br_tag, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_4_bits_uop_br_type, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_is_sfb, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_is_fence, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_is_fencei, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_is_sfence, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_is_amo, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_is_eret, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_is_rocc, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_is_mov, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_4_bits_uop_ftq_idx, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_edge_inst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_4_bits_uop_pc_lob, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_taken, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_imm_rename, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_4_bits_uop_imm_sel, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_4_bits_uop_pimm, // @[issue-slot.scala:52:14] input [19:0] io_wakeup_ports_4_bits_uop_imm_packed, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_4_bits_uop_op1_sel, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_4_bits_uop_op2_sel, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_4_bits_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_4_bits_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_div, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_4_bits_uop_rob_idx, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_4_bits_uop_ldq_idx, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_4_bits_uop_stq_idx, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_4_bits_uop_rxq_idx, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_4_bits_uop_pdst, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_4_bits_uop_prs1, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_4_bits_uop_prs2, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_4_bits_uop_prs3, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_4_bits_uop_ppred, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_prs1_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_prs2_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_prs3_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_ppred_busy, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_4_bits_uop_stale_pdst, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_exception, // @[issue-slot.scala:52:14] input [63:0] io_wakeup_ports_4_bits_uop_exc_cause, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_4_bits_uop_mem_cmd, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_4_bits_uop_mem_size, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_mem_signed, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_uses_ldq, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_uses_stq, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_is_unique, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_flush_on_commit, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_4_bits_uop_csr_cmd, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_ldst_is_rs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_4_bits_uop_ldst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_4_bits_uop_lrs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_4_bits_uop_lrs2, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_4_bits_uop_lrs3, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_4_bits_uop_dst_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_4_bits_uop_lrs1_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_4_bits_uop_lrs2_rtype, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_frs3_en, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fcn_dw, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_4_bits_uop_fcn_op, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fp_val, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_4_bits_uop_fp_rm, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_4_bits_uop_fp_typ, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_xcpt_pf_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_xcpt_ae_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_xcpt_ma_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_bp_debug_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_bp_xcpt_if, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_4_bits_uop_debug_fsrc, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_4_bits_uop_debug_tsrc, // @[issue-slot.scala:52:14] input io_pred_wakeup_port_valid, // @[issue-slot.scala:52:14] input [4:0] io_pred_wakeup_port_bits, // @[issue-slot.scala:52:14] input [2:0] io_child_rebusys // @[issue-slot.scala:52:14] ); wire [15:0] next_uop_out_br_mask; // @[util.scala:104:23] wire io_grant_0 = io_grant; // @[issue-slot.scala:49:7] wire io_in_uop_valid_0 = io_in_uop_valid; // @[issue-slot.scala:49:7] wire [31:0] io_in_uop_bits_inst_0 = io_in_uop_bits_inst; // @[issue-slot.scala:49:7] wire [31:0] io_in_uop_bits_debug_inst_0 = io_in_uop_bits_debug_inst; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_rvc_0 = io_in_uop_bits_is_rvc; // @[issue-slot.scala:49:7] wire [39:0] io_in_uop_bits_debug_pc_0 = io_in_uop_bits_debug_pc; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iq_type_0_0 = io_in_uop_bits_iq_type_0; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iq_type_1_0 = io_in_uop_bits_iq_type_1; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iq_type_2_0 = io_in_uop_bits_iq_type_2; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iq_type_3_0 = io_in_uop_bits_iq_type_3; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_0_0 = io_in_uop_bits_fu_code_0; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_1_0 = io_in_uop_bits_fu_code_1; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_2_0 = io_in_uop_bits_fu_code_2; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_3_0 = io_in_uop_bits_fu_code_3; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_4_0 = io_in_uop_bits_fu_code_4; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_5_0 = io_in_uop_bits_fu_code_5; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_6_0 = io_in_uop_bits_fu_code_6; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_7_0 = io_in_uop_bits_fu_code_7; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_8_0 = io_in_uop_bits_fu_code_8; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_9_0 = io_in_uop_bits_fu_code_9; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iw_issued_0 = io_in_uop_bits_iw_issued; // @[issue-slot.scala:49:7] wire [2:0] io_in_uop_bits_iw_p1_speculative_child_0 = io_in_uop_bits_iw_p1_speculative_child; // @[issue-slot.scala:49:7] wire [2:0] io_in_uop_bits_iw_p2_speculative_child_0 = io_in_uop_bits_iw_p2_speculative_child; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iw_p1_bypass_hint_0 = io_in_uop_bits_iw_p1_bypass_hint; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iw_p2_bypass_hint_0 = io_in_uop_bits_iw_p2_bypass_hint; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iw_p3_bypass_hint_0 = io_in_uop_bits_iw_p3_bypass_hint; // @[issue-slot.scala:49:7] wire [2:0] io_in_uop_bits_dis_col_sel_0 = io_in_uop_bits_dis_col_sel; // @[issue-slot.scala:49:7] wire [15:0] io_in_uop_bits_br_mask_0 = io_in_uop_bits_br_mask; // @[issue-slot.scala:49:7] wire [3:0] io_in_uop_bits_br_tag_0 = io_in_uop_bits_br_tag; // @[issue-slot.scala:49:7] wire [3:0] io_in_uop_bits_br_type_0 = io_in_uop_bits_br_type; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_sfb_0 = io_in_uop_bits_is_sfb; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_fence_0 = io_in_uop_bits_is_fence; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_fencei_0 = io_in_uop_bits_is_fencei; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_sfence_0 = io_in_uop_bits_is_sfence; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_amo_0 = io_in_uop_bits_is_amo; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_eret_0 = io_in_uop_bits_is_eret; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_sys_pc2epc_0 = io_in_uop_bits_is_sys_pc2epc; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_rocc_0 = io_in_uop_bits_is_rocc; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_mov_0 = io_in_uop_bits_is_mov; // @[issue-slot.scala:49:7] wire [4:0] io_in_uop_bits_ftq_idx_0 = io_in_uop_bits_ftq_idx; // @[issue-slot.scala:49:7] wire io_in_uop_bits_edge_inst_0 = io_in_uop_bits_edge_inst; // @[issue-slot.scala:49:7] wire [5:0] io_in_uop_bits_pc_lob_0 = io_in_uop_bits_pc_lob; // @[issue-slot.scala:49:7] wire io_in_uop_bits_taken_0 = io_in_uop_bits_taken; // @[issue-slot.scala:49:7] wire io_in_uop_bits_imm_rename_0 = io_in_uop_bits_imm_rename; // @[issue-slot.scala:49:7] wire [2:0] io_in_uop_bits_imm_sel_0 = io_in_uop_bits_imm_sel; // @[issue-slot.scala:49:7] wire [4:0] io_in_uop_bits_pimm_0 = io_in_uop_bits_pimm; // @[issue-slot.scala:49:7] wire [19:0] io_in_uop_bits_imm_packed_0 = io_in_uop_bits_imm_packed; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_op1_sel_0 = io_in_uop_bits_op1_sel; // @[issue-slot.scala:49:7] wire [2:0] io_in_uop_bits_op2_sel_0 = io_in_uop_bits_op2_sel; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_ldst_0 = io_in_uop_bits_fp_ctrl_ldst; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_wen_0 = io_in_uop_bits_fp_ctrl_wen; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_ren1_0 = io_in_uop_bits_fp_ctrl_ren1; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_ren2_0 = io_in_uop_bits_fp_ctrl_ren2; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_ren3_0 = io_in_uop_bits_fp_ctrl_ren3; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_swap12_0 = io_in_uop_bits_fp_ctrl_swap12; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_swap23_0 = io_in_uop_bits_fp_ctrl_swap23; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_fp_ctrl_typeTagIn_0 = io_in_uop_bits_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_fp_ctrl_typeTagOut_0 = io_in_uop_bits_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_fromint_0 = io_in_uop_bits_fp_ctrl_fromint; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_toint_0 = io_in_uop_bits_fp_ctrl_toint; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_fastpipe_0 = io_in_uop_bits_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_fma_0 = io_in_uop_bits_fp_ctrl_fma; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_div_0 = io_in_uop_bits_fp_ctrl_div; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_sqrt_0 = io_in_uop_bits_fp_ctrl_sqrt; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_wflags_0 = io_in_uop_bits_fp_ctrl_wflags; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_vec_0 = io_in_uop_bits_fp_ctrl_vec; // @[issue-slot.scala:49:7] wire [6:0] io_in_uop_bits_rob_idx_0 = io_in_uop_bits_rob_idx; // @[issue-slot.scala:49:7] wire [4:0] io_in_uop_bits_ldq_idx_0 = io_in_uop_bits_ldq_idx; // @[issue-slot.scala:49:7] wire [4:0] io_in_uop_bits_stq_idx_0 = io_in_uop_bits_stq_idx; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_rxq_idx_0 = io_in_uop_bits_rxq_idx; // @[issue-slot.scala:49:7] wire [6:0] io_in_uop_bits_pdst_0 = io_in_uop_bits_pdst; // @[issue-slot.scala:49:7] wire [6:0] io_in_uop_bits_prs1_0 = io_in_uop_bits_prs1; // @[issue-slot.scala:49:7] wire [6:0] io_in_uop_bits_prs2_0 = io_in_uop_bits_prs2; // @[issue-slot.scala:49:7] wire [6:0] io_in_uop_bits_prs3_0 = io_in_uop_bits_prs3; // @[issue-slot.scala:49:7] wire [4:0] io_in_uop_bits_ppred_0 = io_in_uop_bits_ppred; // @[issue-slot.scala:49:7] wire io_in_uop_bits_prs1_busy_0 = io_in_uop_bits_prs1_busy; // @[issue-slot.scala:49:7] wire io_in_uop_bits_prs2_busy_0 = io_in_uop_bits_prs2_busy; // @[issue-slot.scala:49:7] wire io_in_uop_bits_prs3_busy_0 = io_in_uop_bits_prs3_busy; // @[issue-slot.scala:49:7] wire io_in_uop_bits_ppred_busy_0 = io_in_uop_bits_ppred_busy; // @[issue-slot.scala:49:7] wire [6:0] io_in_uop_bits_stale_pdst_0 = io_in_uop_bits_stale_pdst; // @[issue-slot.scala:49:7] wire io_in_uop_bits_exception_0 = io_in_uop_bits_exception; // @[issue-slot.scala:49:7] wire [63:0] io_in_uop_bits_exc_cause_0 = io_in_uop_bits_exc_cause; // @[issue-slot.scala:49:7] wire [4:0] io_in_uop_bits_mem_cmd_0 = io_in_uop_bits_mem_cmd; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_mem_size_0 = io_in_uop_bits_mem_size; // @[issue-slot.scala:49:7] wire io_in_uop_bits_mem_signed_0 = io_in_uop_bits_mem_signed; // @[issue-slot.scala:49:7] wire io_in_uop_bits_uses_ldq_0 = io_in_uop_bits_uses_ldq; // @[issue-slot.scala:49:7] wire io_in_uop_bits_uses_stq_0 = io_in_uop_bits_uses_stq; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_unique_0 = io_in_uop_bits_is_unique; // @[issue-slot.scala:49:7] wire io_in_uop_bits_flush_on_commit_0 = io_in_uop_bits_flush_on_commit; // @[issue-slot.scala:49:7] wire [2:0] io_in_uop_bits_csr_cmd_0 = io_in_uop_bits_csr_cmd; // @[issue-slot.scala:49:7] wire io_in_uop_bits_ldst_is_rs1_0 = io_in_uop_bits_ldst_is_rs1; // @[issue-slot.scala:49:7] wire [5:0] io_in_uop_bits_ldst_0 = io_in_uop_bits_ldst; // @[issue-slot.scala:49:7] wire [5:0] io_in_uop_bits_lrs1_0 = io_in_uop_bits_lrs1; // @[issue-slot.scala:49:7] wire [5:0] io_in_uop_bits_lrs2_0 = io_in_uop_bits_lrs2; // @[issue-slot.scala:49:7] wire [5:0] io_in_uop_bits_lrs3_0 = io_in_uop_bits_lrs3; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_dst_rtype_0 = io_in_uop_bits_dst_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_lrs1_rtype_0 = io_in_uop_bits_lrs1_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_lrs2_rtype_0 = io_in_uop_bits_lrs2_rtype; // @[issue-slot.scala:49:7] wire io_in_uop_bits_frs3_en_0 = io_in_uop_bits_frs3_en; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fcn_dw_0 = io_in_uop_bits_fcn_dw; // @[issue-slot.scala:49:7] wire [4:0] io_in_uop_bits_fcn_op_0 = io_in_uop_bits_fcn_op; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_val_0 = io_in_uop_bits_fp_val; // @[issue-slot.scala:49:7] wire [2:0] io_in_uop_bits_fp_rm_0 = io_in_uop_bits_fp_rm; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_fp_typ_0 = io_in_uop_bits_fp_typ; // @[issue-slot.scala:49:7] wire io_in_uop_bits_xcpt_pf_if_0 = io_in_uop_bits_xcpt_pf_if; // @[issue-slot.scala:49:7] wire io_in_uop_bits_xcpt_ae_if_0 = io_in_uop_bits_xcpt_ae_if; // @[issue-slot.scala:49:7] wire io_in_uop_bits_xcpt_ma_if_0 = io_in_uop_bits_xcpt_ma_if; // @[issue-slot.scala:49:7] wire io_in_uop_bits_bp_debug_if_0 = io_in_uop_bits_bp_debug_if; // @[issue-slot.scala:49:7] wire io_in_uop_bits_bp_xcpt_if_0 = io_in_uop_bits_bp_xcpt_if; // @[issue-slot.scala:49:7] wire [2:0] io_in_uop_bits_debug_fsrc_0 = io_in_uop_bits_debug_fsrc; // @[issue-slot.scala:49:7] wire [2:0] io_in_uop_bits_debug_tsrc_0 = io_in_uop_bits_debug_tsrc; // @[issue-slot.scala:49:7] wire [15:0] io_brupdate_b1_resolve_mask_0 = io_brupdate_b1_resolve_mask; // @[issue-slot.scala:49:7] wire [15:0] io_brupdate_b1_mispredict_mask_0 = io_brupdate_b1_mispredict_mask; // @[issue-slot.scala:49:7] wire [31:0] io_brupdate_b2_uop_inst_0 = io_brupdate_b2_uop_inst; // @[issue-slot.scala:49:7] wire [31:0] io_brupdate_b2_uop_debug_inst_0 = io_brupdate_b2_uop_debug_inst; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_rvc_0 = io_brupdate_b2_uop_is_rvc; // @[issue-slot.scala:49:7] wire [39:0] io_brupdate_b2_uop_debug_pc_0 = io_brupdate_b2_uop_debug_pc; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iq_type_0_0 = io_brupdate_b2_uop_iq_type_0; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iq_type_1_0 = io_brupdate_b2_uop_iq_type_1; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iq_type_2_0 = io_brupdate_b2_uop_iq_type_2; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iq_type_3_0 = io_brupdate_b2_uop_iq_type_3; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_0_0 = io_brupdate_b2_uop_fu_code_0; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_1_0 = io_brupdate_b2_uop_fu_code_1; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_2_0 = io_brupdate_b2_uop_fu_code_2; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_3_0 = io_brupdate_b2_uop_fu_code_3; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_4_0 = io_brupdate_b2_uop_fu_code_4; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_5_0 = io_brupdate_b2_uop_fu_code_5; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_6_0 = io_brupdate_b2_uop_fu_code_6; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_7_0 = io_brupdate_b2_uop_fu_code_7; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_8_0 = io_brupdate_b2_uop_fu_code_8; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_9_0 = io_brupdate_b2_uop_fu_code_9; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iw_issued_0 = io_brupdate_b2_uop_iw_issued; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iw_issued_partial_agen_0 = io_brupdate_b2_uop_iw_issued_partial_agen; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iw_issued_partial_dgen_0 = io_brupdate_b2_uop_iw_issued_partial_dgen; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_iw_p1_speculative_child_0 = io_brupdate_b2_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_iw_p2_speculative_child_0 = io_brupdate_b2_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iw_p1_bypass_hint_0 = io_brupdate_b2_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iw_p2_bypass_hint_0 = io_brupdate_b2_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iw_p3_bypass_hint_0 = io_brupdate_b2_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_dis_col_sel_0 = io_brupdate_b2_uop_dis_col_sel; // @[issue-slot.scala:49:7] wire [15:0] io_brupdate_b2_uop_br_mask_0 = io_brupdate_b2_uop_br_mask; // @[issue-slot.scala:49:7] wire [3:0] io_brupdate_b2_uop_br_tag_0 = io_brupdate_b2_uop_br_tag; // @[issue-slot.scala:49:7] wire [3:0] io_brupdate_b2_uop_br_type_0 = io_brupdate_b2_uop_br_type; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_sfb_0 = io_brupdate_b2_uop_is_sfb; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_fence_0 = io_brupdate_b2_uop_is_fence; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_fencei_0 = io_brupdate_b2_uop_is_fencei; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_sfence_0 = io_brupdate_b2_uop_is_sfence; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_amo_0 = io_brupdate_b2_uop_is_amo; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_eret_0 = io_brupdate_b2_uop_is_eret; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_sys_pc2epc_0 = io_brupdate_b2_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_rocc_0 = io_brupdate_b2_uop_is_rocc; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_mov_0 = io_brupdate_b2_uop_is_mov; // @[issue-slot.scala:49:7] wire [4:0] io_brupdate_b2_uop_ftq_idx_0 = io_brupdate_b2_uop_ftq_idx; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_edge_inst_0 = io_brupdate_b2_uop_edge_inst; // @[issue-slot.scala:49:7] wire [5:0] io_brupdate_b2_uop_pc_lob_0 = io_brupdate_b2_uop_pc_lob; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_taken_0 = io_brupdate_b2_uop_taken; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_imm_rename_0 = io_brupdate_b2_uop_imm_rename; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_imm_sel_0 = io_brupdate_b2_uop_imm_sel; // @[issue-slot.scala:49:7] wire [4:0] io_brupdate_b2_uop_pimm_0 = io_brupdate_b2_uop_pimm; // @[issue-slot.scala:49:7] wire [19:0] io_brupdate_b2_uop_imm_packed_0 = io_brupdate_b2_uop_imm_packed; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_op1_sel_0 = io_brupdate_b2_uop_op1_sel; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_op2_sel_0 = io_brupdate_b2_uop_op2_sel; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_ldst_0 = io_brupdate_b2_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_wen_0 = io_brupdate_b2_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_ren1_0 = io_brupdate_b2_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_ren2_0 = io_brupdate_b2_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_ren3_0 = io_brupdate_b2_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_swap12_0 = io_brupdate_b2_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_swap23_0 = io_brupdate_b2_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagIn_0 = io_brupdate_b2_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagOut_0 = io_brupdate_b2_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_fromint_0 = io_brupdate_b2_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_toint_0 = io_brupdate_b2_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_fastpipe_0 = io_brupdate_b2_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_fma_0 = io_brupdate_b2_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_div_0 = io_brupdate_b2_uop_fp_ctrl_div; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_sqrt_0 = io_brupdate_b2_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_wflags_0 = io_brupdate_b2_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_vec_0 = io_brupdate_b2_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7] wire [6:0] io_brupdate_b2_uop_rob_idx_0 = io_brupdate_b2_uop_rob_idx; // @[issue-slot.scala:49:7] wire [4:0] io_brupdate_b2_uop_ldq_idx_0 = io_brupdate_b2_uop_ldq_idx; // @[issue-slot.scala:49:7] wire [4:0] io_brupdate_b2_uop_stq_idx_0 = io_brupdate_b2_uop_stq_idx; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_rxq_idx_0 = io_brupdate_b2_uop_rxq_idx; // @[issue-slot.scala:49:7] wire [6:0] io_brupdate_b2_uop_pdst_0 = io_brupdate_b2_uop_pdst; // @[issue-slot.scala:49:7] wire [6:0] io_brupdate_b2_uop_prs1_0 = io_brupdate_b2_uop_prs1; // @[issue-slot.scala:49:7] wire [6:0] io_brupdate_b2_uop_prs2_0 = io_brupdate_b2_uop_prs2; // @[issue-slot.scala:49:7] wire [6:0] io_brupdate_b2_uop_prs3_0 = io_brupdate_b2_uop_prs3; // @[issue-slot.scala:49:7] wire [4:0] io_brupdate_b2_uop_ppred_0 = io_brupdate_b2_uop_ppred; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_prs1_busy_0 = io_brupdate_b2_uop_prs1_busy; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_prs2_busy_0 = io_brupdate_b2_uop_prs2_busy; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_prs3_busy_0 = io_brupdate_b2_uop_prs3_busy; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_ppred_busy_0 = io_brupdate_b2_uop_ppred_busy; // @[issue-slot.scala:49:7] wire [6:0] io_brupdate_b2_uop_stale_pdst_0 = io_brupdate_b2_uop_stale_pdst; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_exception_0 = io_brupdate_b2_uop_exception; // @[issue-slot.scala:49:7] wire [63:0] io_brupdate_b2_uop_exc_cause_0 = io_brupdate_b2_uop_exc_cause; // @[issue-slot.scala:49:7] wire [4:0] io_brupdate_b2_uop_mem_cmd_0 = io_brupdate_b2_uop_mem_cmd; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_mem_size_0 = io_brupdate_b2_uop_mem_size; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_mem_signed_0 = io_brupdate_b2_uop_mem_signed; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_uses_ldq_0 = io_brupdate_b2_uop_uses_ldq; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_uses_stq_0 = io_brupdate_b2_uop_uses_stq; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_unique_0 = io_brupdate_b2_uop_is_unique; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_flush_on_commit_0 = io_brupdate_b2_uop_flush_on_commit; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_csr_cmd_0 = io_brupdate_b2_uop_csr_cmd; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_ldst_is_rs1_0 = io_brupdate_b2_uop_ldst_is_rs1; // @[issue-slot.scala:49:7] wire [5:0] io_brupdate_b2_uop_ldst_0 = io_brupdate_b2_uop_ldst; // @[issue-slot.scala:49:7] wire [5:0] io_brupdate_b2_uop_lrs1_0 = io_brupdate_b2_uop_lrs1; // @[issue-slot.scala:49:7] wire [5:0] io_brupdate_b2_uop_lrs2_0 = io_brupdate_b2_uop_lrs2; // @[issue-slot.scala:49:7] wire [5:0] io_brupdate_b2_uop_lrs3_0 = io_brupdate_b2_uop_lrs3; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_dst_rtype_0 = io_brupdate_b2_uop_dst_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_lrs1_rtype_0 = io_brupdate_b2_uop_lrs1_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_lrs2_rtype_0 = io_brupdate_b2_uop_lrs2_rtype; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_frs3_en_0 = io_brupdate_b2_uop_frs3_en; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fcn_dw_0 = io_brupdate_b2_uop_fcn_dw; // @[issue-slot.scala:49:7] wire [4:0] io_brupdate_b2_uop_fcn_op_0 = io_brupdate_b2_uop_fcn_op; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_val_0 = io_brupdate_b2_uop_fp_val; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_fp_rm_0 = io_brupdate_b2_uop_fp_rm; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_fp_typ_0 = io_brupdate_b2_uop_fp_typ; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_xcpt_pf_if_0 = io_brupdate_b2_uop_xcpt_pf_if; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_xcpt_ae_if_0 = io_brupdate_b2_uop_xcpt_ae_if; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_xcpt_ma_if_0 = io_brupdate_b2_uop_xcpt_ma_if; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_bp_debug_if_0 = io_brupdate_b2_uop_bp_debug_if; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_bp_xcpt_if_0 = io_brupdate_b2_uop_bp_xcpt_if; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_debug_fsrc_0 = io_brupdate_b2_uop_debug_fsrc; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_debug_tsrc_0 = io_brupdate_b2_uop_debug_tsrc; // @[issue-slot.scala:49:7] wire io_brupdate_b2_mispredict_0 = io_brupdate_b2_mispredict; // @[issue-slot.scala:49:7] wire io_brupdate_b2_taken_0 = io_brupdate_b2_taken; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_cfi_type_0 = io_brupdate_b2_cfi_type; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_pc_sel_0 = io_brupdate_b2_pc_sel; // @[issue-slot.scala:49:7] wire [39:0] io_brupdate_b2_jalr_target_0 = io_brupdate_b2_jalr_target; // @[issue-slot.scala:49:7] wire [20:0] io_brupdate_b2_target_offset_0 = io_brupdate_b2_target_offset; // @[issue-slot.scala:49:7] wire io_kill_0 = io_kill; // @[issue-slot.scala:49:7] wire io_squash_grant_0 = io_squash_grant; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_valid_0 = io_wakeup_ports_0_valid; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_0_bits_uop_inst_0 = io_wakeup_ports_0_bits_uop_inst; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_0_bits_uop_debug_inst_0 = io_wakeup_ports_0_bits_uop_debug_inst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_rvc_0 = io_wakeup_ports_0_bits_uop_is_rvc; // @[issue-slot.scala:49:7] wire [39:0] io_wakeup_ports_0_bits_uop_debug_pc_0 = io_wakeup_ports_0_bits_uop_debug_pc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iq_type_0_0 = io_wakeup_ports_0_bits_uop_iq_type_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iq_type_1_0 = io_wakeup_ports_0_bits_uop_iq_type_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iq_type_2_0 = io_wakeup_ports_0_bits_uop_iq_type_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iq_type_3_0 = io_wakeup_ports_0_bits_uop_iq_type_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_0_0 = io_wakeup_ports_0_bits_uop_fu_code_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_1_0 = io_wakeup_ports_0_bits_uop_fu_code_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_2_0 = io_wakeup_ports_0_bits_uop_fu_code_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_3_0 = io_wakeup_ports_0_bits_uop_fu_code_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_4_0 = io_wakeup_ports_0_bits_uop_fu_code_4; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_5_0 = io_wakeup_ports_0_bits_uop_fu_code_5; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_6_0 = io_wakeup_ports_0_bits_uop_fu_code_6; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_7_0 = io_wakeup_ports_0_bits_uop_fu_code_7; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_8_0 = io_wakeup_ports_0_bits_uop_fu_code_8; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_9_0 = io_wakeup_ports_0_bits_uop_fu_code_9; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iw_issued_0 = io_wakeup_ports_0_bits_uop_iw_issued; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iw_issued_partial_agen_0 = io_wakeup_ports_0_bits_uop_iw_issued_partial_agen; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen_0 = io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_iw_p1_speculative_child_0 = io_wakeup_ports_0_bits_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_iw_p2_speculative_child_0 = io_wakeup_ports_0_bits_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint_0 = io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint_0 = io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint_0 = io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_dis_col_sel_0 = io_wakeup_ports_0_bits_uop_dis_col_sel; // @[issue-slot.scala:49:7] wire [15:0] io_wakeup_ports_0_bits_uop_br_mask_0 = io_wakeup_ports_0_bits_uop_br_mask; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_0_bits_uop_br_tag_0 = io_wakeup_ports_0_bits_uop_br_tag; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_0_bits_uop_br_type_0 = io_wakeup_ports_0_bits_uop_br_type; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_sfb_0 = io_wakeup_ports_0_bits_uop_is_sfb; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_fence_0 = io_wakeup_ports_0_bits_uop_is_fence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_fencei_0 = io_wakeup_ports_0_bits_uop_is_fencei; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_sfence_0 = io_wakeup_ports_0_bits_uop_is_sfence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_amo_0 = io_wakeup_ports_0_bits_uop_is_amo; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_eret_0 = io_wakeup_ports_0_bits_uop_is_eret; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_sys_pc2epc_0 = io_wakeup_ports_0_bits_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_rocc_0 = io_wakeup_ports_0_bits_uop_is_rocc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_mov_0 = io_wakeup_ports_0_bits_uop_is_mov; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_0_bits_uop_ftq_idx_0 = io_wakeup_ports_0_bits_uop_ftq_idx; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_edge_inst_0 = io_wakeup_ports_0_bits_uop_edge_inst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_0_bits_uop_pc_lob_0 = io_wakeup_ports_0_bits_uop_pc_lob; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_taken_0 = io_wakeup_ports_0_bits_uop_taken; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_imm_rename_0 = io_wakeup_ports_0_bits_uop_imm_rename; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_imm_sel_0 = io_wakeup_ports_0_bits_uop_imm_sel; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_0_bits_uop_pimm_0 = io_wakeup_ports_0_bits_uop_pimm; // @[issue-slot.scala:49:7] wire [19:0] io_wakeup_ports_0_bits_uop_imm_packed_0 = io_wakeup_ports_0_bits_uop_imm_packed; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_op1_sel_0 = io_wakeup_ports_0_bits_uop_op1_sel; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_op2_sel_0 = io_wakeup_ports_0_bits_uop_op2_sel; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_ldst_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_wen_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_ren1_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_ren2_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_ren3_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_swap12_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_swap23_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_fromint_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_toint_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_fma_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_div_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_div; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_wflags_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_vec_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_0_bits_uop_rob_idx_0 = io_wakeup_ports_0_bits_uop_rob_idx; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_0_bits_uop_ldq_idx_0 = io_wakeup_ports_0_bits_uop_ldq_idx; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_0_bits_uop_stq_idx_0 = io_wakeup_ports_0_bits_uop_stq_idx; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_rxq_idx_0 = io_wakeup_ports_0_bits_uop_rxq_idx; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_0_bits_uop_pdst_0 = io_wakeup_ports_0_bits_uop_pdst; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_0_bits_uop_prs1_0 = io_wakeup_ports_0_bits_uop_prs1; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_0_bits_uop_prs2_0 = io_wakeup_ports_0_bits_uop_prs2; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_0_bits_uop_prs3_0 = io_wakeup_ports_0_bits_uop_prs3; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_0_bits_uop_ppred_0 = io_wakeup_ports_0_bits_uop_ppred; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_prs1_busy_0 = io_wakeup_ports_0_bits_uop_prs1_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_prs2_busy_0 = io_wakeup_ports_0_bits_uop_prs2_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_prs3_busy_0 = io_wakeup_ports_0_bits_uop_prs3_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_ppred_busy_0 = io_wakeup_ports_0_bits_uop_ppred_busy; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_0_bits_uop_stale_pdst_0 = io_wakeup_ports_0_bits_uop_stale_pdst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_exception_0 = io_wakeup_ports_0_bits_uop_exception; // @[issue-slot.scala:49:7] wire [63:0] io_wakeup_ports_0_bits_uop_exc_cause_0 = io_wakeup_ports_0_bits_uop_exc_cause; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_0_bits_uop_mem_cmd_0 = io_wakeup_ports_0_bits_uop_mem_cmd; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_mem_size_0 = io_wakeup_ports_0_bits_uop_mem_size; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_mem_signed_0 = io_wakeup_ports_0_bits_uop_mem_signed; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_uses_ldq_0 = io_wakeup_ports_0_bits_uop_uses_ldq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_uses_stq_0 = io_wakeup_ports_0_bits_uop_uses_stq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_unique_0 = io_wakeup_ports_0_bits_uop_is_unique; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_flush_on_commit_0 = io_wakeup_ports_0_bits_uop_flush_on_commit; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_csr_cmd_0 = io_wakeup_ports_0_bits_uop_csr_cmd; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_ldst_is_rs1_0 = io_wakeup_ports_0_bits_uop_ldst_is_rs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_0_bits_uop_ldst_0 = io_wakeup_ports_0_bits_uop_ldst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_0_bits_uop_lrs1_0 = io_wakeup_ports_0_bits_uop_lrs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_0_bits_uop_lrs2_0 = io_wakeup_ports_0_bits_uop_lrs2; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_0_bits_uop_lrs3_0 = io_wakeup_ports_0_bits_uop_lrs3; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_dst_rtype_0 = io_wakeup_ports_0_bits_uop_dst_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_lrs1_rtype_0 = io_wakeup_ports_0_bits_uop_lrs1_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_lrs2_rtype_0 = io_wakeup_ports_0_bits_uop_lrs2_rtype; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_frs3_en_0 = io_wakeup_ports_0_bits_uop_frs3_en; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fcn_dw_0 = io_wakeup_ports_0_bits_uop_fcn_dw; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_0_bits_uop_fcn_op_0 = io_wakeup_ports_0_bits_uop_fcn_op; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_val_0 = io_wakeup_ports_0_bits_uop_fp_val; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_fp_rm_0 = io_wakeup_ports_0_bits_uop_fp_rm; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_fp_typ_0 = io_wakeup_ports_0_bits_uop_fp_typ; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_xcpt_pf_if_0 = io_wakeup_ports_0_bits_uop_xcpt_pf_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_xcpt_ae_if_0 = io_wakeup_ports_0_bits_uop_xcpt_ae_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_xcpt_ma_if_0 = io_wakeup_ports_0_bits_uop_xcpt_ma_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_bp_debug_if_0 = io_wakeup_ports_0_bits_uop_bp_debug_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_bp_xcpt_if_0 = io_wakeup_ports_0_bits_uop_bp_xcpt_if; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_debug_fsrc_0 = io_wakeup_ports_0_bits_uop_debug_fsrc; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_debug_tsrc_0 = io_wakeup_ports_0_bits_uop_debug_tsrc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_bypassable_0 = io_wakeup_ports_0_bits_bypassable; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_speculative_mask_0 = io_wakeup_ports_0_bits_speculative_mask; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_rebusy_0 = io_wakeup_ports_0_bits_rebusy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_valid_0 = io_wakeup_ports_1_valid; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_1_bits_uop_inst_0 = io_wakeup_ports_1_bits_uop_inst; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_1_bits_uop_debug_inst_0 = io_wakeup_ports_1_bits_uop_debug_inst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_rvc_0 = io_wakeup_ports_1_bits_uop_is_rvc; // @[issue-slot.scala:49:7] wire [39:0] io_wakeup_ports_1_bits_uop_debug_pc_0 = io_wakeup_ports_1_bits_uop_debug_pc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iq_type_0_0 = io_wakeup_ports_1_bits_uop_iq_type_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iq_type_1_0 = io_wakeup_ports_1_bits_uop_iq_type_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iq_type_2_0 = io_wakeup_ports_1_bits_uop_iq_type_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iq_type_3_0 = io_wakeup_ports_1_bits_uop_iq_type_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_0_0 = io_wakeup_ports_1_bits_uop_fu_code_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_1_0 = io_wakeup_ports_1_bits_uop_fu_code_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_2_0 = io_wakeup_ports_1_bits_uop_fu_code_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_3_0 = io_wakeup_ports_1_bits_uop_fu_code_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_4_0 = io_wakeup_ports_1_bits_uop_fu_code_4; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_5_0 = io_wakeup_ports_1_bits_uop_fu_code_5; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_6_0 = io_wakeup_ports_1_bits_uop_fu_code_6; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_7_0 = io_wakeup_ports_1_bits_uop_fu_code_7; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_8_0 = io_wakeup_ports_1_bits_uop_fu_code_8; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_9_0 = io_wakeup_ports_1_bits_uop_fu_code_9; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iw_issued_0 = io_wakeup_ports_1_bits_uop_iw_issued; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iw_issued_partial_agen_0 = io_wakeup_ports_1_bits_uop_iw_issued_partial_agen; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen_0 = io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_iw_p1_speculative_child_0 = io_wakeup_ports_1_bits_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_iw_p2_speculative_child_0 = io_wakeup_ports_1_bits_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint_0 = io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint_0 = io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint_0 = io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_dis_col_sel_0 = io_wakeup_ports_1_bits_uop_dis_col_sel; // @[issue-slot.scala:49:7] wire [15:0] io_wakeup_ports_1_bits_uop_br_mask_0 = io_wakeup_ports_1_bits_uop_br_mask; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_1_bits_uop_br_tag_0 = io_wakeup_ports_1_bits_uop_br_tag; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_1_bits_uop_br_type_0 = io_wakeup_ports_1_bits_uop_br_type; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_sfb_0 = io_wakeup_ports_1_bits_uop_is_sfb; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_fence_0 = io_wakeup_ports_1_bits_uop_is_fence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_fencei_0 = io_wakeup_ports_1_bits_uop_is_fencei; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_sfence_0 = io_wakeup_ports_1_bits_uop_is_sfence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_amo_0 = io_wakeup_ports_1_bits_uop_is_amo; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_eret_0 = io_wakeup_ports_1_bits_uop_is_eret; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_sys_pc2epc_0 = io_wakeup_ports_1_bits_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_rocc_0 = io_wakeup_ports_1_bits_uop_is_rocc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_mov_0 = io_wakeup_ports_1_bits_uop_is_mov; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_1_bits_uop_ftq_idx_0 = io_wakeup_ports_1_bits_uop_ftq_idx; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_edge_inst_0 = io_wakeup_ports_1_bits_uop_edge_inst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_1_bits_uop_pc_lob_0 = io_wakeup_ports_1_bits_uop_pc_lob; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_taken_0 = io_wakeup_ports_1_bits_uop_taken; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_imm_rename_0 = io_wakeup_ports_1_bits_uop_imm_rename; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_imm_sel_0 = io_wakeup_ports_1_bits_uop_imm_sel; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_1_bits_uop_pimm_0 = io_wakeup_ports_1_bits_uop_pimm; // @[issue-slot.scala:49:7] wire [19:0] io_wakeup_ports_1_bits_uop_imm_packed_0 = io_wakeup_ports_1_bits_uop_imm_packed; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_op1_sel_0 = io_wakeup_ports_1_bits_uop_op1_sel; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_op2_sel_0 = io_wakeup_ports_1_bits_uop_op2_sel; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_ldst_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_wen_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_ren1_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_ren2_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_ren3_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_swap12_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_swap23_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_fromint_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_toint_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_fma_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_div_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_div; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_wflags_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_vec_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_1_bits_uop_rob_idx_0 = io_wakeup_ports_1_bits_uop_rob_idx; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_1_bits_uop_ldq_idx_0 = io_wakeup_ports_1_bits_uop_ldq_idx; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_1_bits_uop_stq_idx_0 = io_wakeup_ports_1_bits_uop_stq_idx; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_rxq_idx_0 = io_wakeup_ports_1_bits_uop_rxq_idx; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_1_bits_uop_pdst_0 = io_wakeup_ports_1_bits_uop_pdst; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_1_bits_uop_prs1_0 = io_wakeup_ports_1_bits_uop_prs1; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_1_bits_uop_prs2_0 = io_wakeup_ports_1_bits_uop_prs2; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_1_bits_uop_prs3_0 = io_wakeup_ports_1_bits_uop_prs3; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_1_bits_uop_ppred_0 = io_wakeup_ports_1_bits_uop_ppred; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_prs1_busy_0 = io_wakeup_ports_1_bits_uop_prs1_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_prs2_busy_0 = io_wakeup_ports_1_bits_uop_prs2_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_prs3_busy_0 = io_wakeup_ports_1_bits_uop_prs3_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_ppred_busy_0 = io_wakeup_ports_1_bits_uop_ppred_busy; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_1_bits_uop_stale_pdst_0 = io_wakeup_ports_1_bits_uop_stale_pdst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_exception_0 = io_wakeup_ports_1_bits_uop_exception; // @[issue-slot.scala:49:7] wire [63:0] io_wakeup_ports_1_bits_uop_exc_cause_0 = io_wakeup_ports_1_bits_uop_exc_cause; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_1_bits_uop_mem_cmd_0 = io_wakeup_ports_1_bits_uop_mem_cmd; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_mem_size_0 = io_wakeup_ports_1_bits_uop_mem_size; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_mem_signed_0 = io_wakeup_ports_1_bits_uop_mem_signed; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_uses_ldq_0 = io_wakeup_ports_1_bits_uop_uses_ldq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_uses_stq_0 = io_wakeup_ports_1_bits_uop_uses_stq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_unique_0 = io_wakeup_ports_1_bits_uop_is_unique; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_flush_on_commit_0 = io_wakeup_ports_1_bits_uop_flush_on_commit; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_csr_cmd_0 = io_wakeup_ports_1_bits_uop_csr_cmd; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_ldst_is_rs1_0 = io_wakeup_ports_1_bits_uop_ldst_is_rs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_1_bits_uop_ldst_0 = io_wakeup_ports_1_bits_uop_ldst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_1_bits_uop_lrs1_0 = io_wakeup_ports_1_bits_uop_lrs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_1_bits_uop_lrs2_0 = io_wakeup_ports_1_bits_uop_lrs2; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_1_bits_uop_lrs3_0 = io_wakeup_ports_1_bits_uop_lrs3; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_dst_rtype_0 = io_wakeup_ports_1_bits_uop_dst_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_lrs1_rtype_0 = io_wakeup_ports_1_bits_uop_lrs1_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_lrs2_rtype_0 = io_wakeup_ports_1_bits_uop_lrs2_rtype; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_frs3_en_0 = io_wakeup_ports_1_bits_uop_frs3_en; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fcn_dw_0 = io_wakeup_ports_1_bits_uop_fcn_dw; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_1_bits_uop_fcn_op_0 = io_wakeup_ports_1_bits_uop_fcn_op; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_val_0 = io_wakeup_ports_1_bits_uop_fp_val; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_fp_rm_0 = io_wakeup_ports_1_bits_uop_fp_rm; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_fp_typ_0 = io_wakeup_ports_1_bits_uop_fp_typ; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_xcpt_pf_if_0 = io_wakeup_ports_1_bits_uop_xcpt_pf_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_xcpt_ae_if_0 = io_wakeup_ports_1_bits_uop_xcpt_ae_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_xcpt_ma_if_0 = io_wakeup_ports_1_bits_uop_xcpt_ma_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_bp_debug_if_0 = io_wakeup_ports_1_bits_uop_bp_debug_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_bp_xcpt_if_0 = io_wakeup_ports_1_bits_uop_bp_xcpt_if; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_debug_fsrc_0 = io_wakeup_ports_1_bits_uop_debug_fsrc; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_debug_tsrc_0 = io_wakeup_ports_1_bits_uop_debug_tsrc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_valid_0 = io_wakeup_ports_2_valid; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_2_bits_uop_inst_0 = io_wakeup_ports_2_bits_uop_inst; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_2_bits_uop_debug_inst_0 = io_wakeup_ports_2_bits_uop_debug_inst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_rvc_0 = io_wakeup_ports_2_bits_uop_is_rvc; // @[issue-slot.scala:49:7] wire [39:0] io_wakeup_ports_2_bits_uop_debug_pc_0 = io_wakeup_ports_2_bits_uop_debug_pc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iq_type_0_0 = io_wakeup_ports_2_bits_uop_iq_type_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iq_type_1_0 = io_wakeup_ports_2_bits_uop_iq_type_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iq_type_2_0 = io_wakeup_ports_2_bits_uop_iq_type_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iq_type_3_0 = io_wakeup_ports_2_bits_uop_iq_type_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_0_0 = io_wakeup_ports_2_bits_uop_fu_code_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_1_0 = io_wakeup_ports_2_bits_uop_fu_code_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_2_0 = io_wakeup_ports_2_bits_uop_fu_code_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_3_0 = io_wakeup_ports_2_bits_uop_fu_code_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_4_0 = io_wakeup_ports_2_bits_uop_fu_code_4; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_5_0 = io_wakeup_ports_2_bits_uop_fu_code_5; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_6_0 = io_wakeup_ports_2_bits_uop_fu_code_6; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_7_0 = io_wakeup_ports_2_bits_uop_fu_code_7; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_8_0 = io_wakeup_ports_2_bits_uop_fu_code_8; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_9_0 = io_wakeup_ports_2_bits_uop_fu_code_9; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iw_issued_0 = io_wakeup_ports_2_bits_uop_iw_issued; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_2_bits_uop_iw_p1_speculative_child_0 = io_wakeup_ports_2_bits_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_2_bits_uop_iw_p2_speculative_child_0 = io_wakeup_ports_2_bits_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iw_p1_bypass_hint_0 = io_wakeup_ports_2_bits_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iw_p2_bypass_hint_0 = io_wakeup_ports_2_bits_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iw_p3_bypass_hint_0 = io_wakeup_ports_2_bits_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_2_bits_uop_dis_col_sel_0 = io_wakeup_ports_2_bits_uop_dis_col_sel; // @[issue-slot.scala:49:7] wire [15:0] io_wakeup_ports_2_bits_uop_br_mask_0 = io_wakeup_ports_2_bits_uop_br_mask; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_2_bits_uop_br_tag_0 = io_wakeup_ports_2_bits_uop_br_tag; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_2_bits_uop_br_type_0 = io_wakeup_ports_2_bits_uop_br_type; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_sfb_0 = io_wakeup_ports_2_bits_uop_is_sfb; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_fence_0 = io_wakeup_ports_2_bits_uop_is_fence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_fencei_0 = io_wakeup_ports_2_bits_uop_is_fencei; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_sfence_0 = io_wakeup_ports_2_bits_uop_is_sfence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_amo_0 = io_wakeup_ports_2_bits_uop_is_amo; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_eret_0 = io_wakeup_ports_2_bits_uop_is_eret; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_sys_pc2epc_0 = io_wakeup_ports_2_bits_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_rocc_0 = io_wakeup_ports_2_bits_uop_is_rocc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_mov_0 = io_wakeup_ports_2_bits_uop_is_mov; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_2_bits_uop_ftq_idx_0 = io_wakeup_ports_2_bits_uop_ftq_idx; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_edge_inst_0 = io_wakeup_ports_2_bits_uop_edge_inst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_2_bits_uop_pc_lob_0 = io_wakeup_ports_2_bits_uop_pc_lob; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_taken_0 = io_wakeup_ports_2_bits_uop_taken; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_imm_rename_0 = io_wakeup_ports_2_bits_uop_imm_rename; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_2_bits_uop_imm_sel_0 = io_wakeup_ports_2_bits_uop_imm_sel; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_2_bits_uop_pimm_0 = io_wakeup_ports_2_bits_uop_pimm; // @[issue-slot.scala:49:7] wire [19:0] io_wakeup_ports_2_bits_uop_imm_packed_0 = io_wakeup_ports_2_bits_uop_imm_packed; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_op1_sel_0 = io_wakeup_ports_2_bits_uop_op1_sel; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_2_bits_uop_op2_sel_0 = io_wakeup_ports_2_bits_uop_op2_sel; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_ldst_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_wen_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_ren1_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_ren2_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_ren3_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_swap12_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_swap23_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_fromint_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_toint_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_fma_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_div_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_div; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_sqrt_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_wflags_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_vec_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_2_bits_uop_rob_idx_0 = io_wakeup_ports_2_bits_uop_rob_idx; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_2_bits_uop_ldq_idx_0 = io_wakeup_ports_2_bits_uop_ldq_idx; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_2_bits_uop_stq_idx_0 = io_wakeup_ports_2_bits_uop_stq_idx; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_rxq_idx_0 = io_wakeup_ports_2_bits_uop_rxq_idx; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_2_bits_uop_pdst_0 = io_wakeup_ports_2_bits_uop_pdst; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_2_bits_uop_prs1_0 = io_wakeup_ports_2_bits_uop_prs1; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_2_bits_uop_prs2_0 = io_wakeup_ports_2_bits_uop_prs2; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_2_bits_uop_prs3_0 = io_wakeup_ports_2_bits_uop_prs3; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_2_bits_uop_ppred_0 = io_wakeup_ports_2_bits_uop_ppred; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_prs1_busy_0 = io_wakeup_ports_2_bits_uop_prs1_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_prs2_busy_0 = io_wakeup_ports_2_bits_uop_prs2_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_prs3_busy_0 = io_wakeup_ports_2_bits_uop_prs3_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_ppred_busy_0 = io_wakeup_ports_2_bits_uop_ppred_busy; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_2_bits_uop_stale_pdst_0 = io_wakeup_ports_2_bits_uop_stale_pdst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_exception_0 = io_wakeup_ports_2_bits_uop_exception; // @[issue-slot.scala:49:7] wire [63:0] io_wakeup_ports_2_bits_uop_exc_cause_0 = io_wakeup_ports_2_bits_uop_exc_cause; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_2_bits_uop_mem_cmd_0 = io_wakeup_ports_2_bits_uop_mem_cmd; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_mem_size_0 = io_wakeup_ports_2_bits_uop_mem_size; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_mem_signed_0 = io_wakeup_ports_2_bits_uop_mem_signed; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_uses_ldq_0 = io_wakeup_ports_2_bits_uop_uses_ldq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_uses_stq_0 = io_wakeup_ports_2_bits_uop_uses_stq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_unique_0 = io_wakeup_ports_2_bits_uop_is_unique; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_flush_on_commit_0 = io_wakeup_ports_2_bits_uop_flush_on_commit; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_2_bits_uop_csr_cmd_0 = io_wakeup_ports_2_bits_uop_csr_cmd; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_ldst_is_rs1_0 = io_wakeup_ports_2_bits_uop_ldst_is_rs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_2_bits_uop_ldst_0 = io_wakeup_ports_2_bits_uop_ldst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_2_bits_uop_lrs1_0 = io_wakeup_ports_2_bits_uop_lrs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_2_bits_uop_lrs2_0 = io_wakeup_ports_2_bits_uop_lrs2; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_2_bits_uop_lrs3_0 = io_wakeup_ports_2_bits_uop_lrs3; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_dst_rtype_0 = io_wakeup_ports_2_bits_uop_dst_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_lrs1_rtype_0 = io_wakeup_ports_2_bits_uop_lrs1_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_lrs2_rtype_0 = io_wakeup_ports_2_bits_uop_lrs2_rtype; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_frs3_en_0 = io_wakeup_ports_2_bits_uop_frs3_en; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fcn_dw_0 = io_wakeup_ports_2_bits_uop_fcn_dw; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_2_bits_uop_fcn_op_0 = io_wakeup_ports_2_bits_uop_fcn_op; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_val_0 = io_wakeup_ports_2_bits_uop_fp_val; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_2_bits_uop_fp_rm_0 = io_wakeup_ports_2_bits_uop_fp_rm; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_fp_typ_0 = io_wakeup_ports_2_bits_uop_fp_typ; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_xcpt_pf_if_0 = io_wakeup_ports_2_bits_uop_xcpt_pf_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_xcpt_ae_if_0 = io_wakeup_ports_2_bits_uop_xcpt_ae_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_xcpt_ma_if_0 = io_wakeup_ports_2_bits_uop_xcpt_ma_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_bp_debug_if_0 = io_wakeup_ports_2_bits_uop_bp_debug_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_bp_xcpt_if_0 = io_wakeup_ports_2_bits_uop_bp_xcpt_if; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_2_bits_uop_debug_fsrc_0 = io_wakeup_ports_2_bits_uop_debug_fsrc; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_2_bits_uop_debug_tsrc_0 = io_wakeup_ports_2_bits_uop_debug_tsrc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_valid_0 = io_wakeup_ports_3_valid; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_3_bits_uop_inst_0 = io_wakeup_ports_3_bits_uop_inst; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_3_bits_uop_debug_inst_0 = io_wakeup_ports_3_bits_uop_debug_inst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_rvc_0 = io_wakeup_ports_3_bits_uop_is_rvc; // @[issue-slot.scala:49:7] wire [39:0] io_wakeup_ports_3_bits_uop_debug_pc_0 = io_wakeup_ports_3_bits_uop_debug_pc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iq_type_0_0 = io_wakeup_ports_3_bits_uop_iq_type_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iq_type_1_0 = io_wakeup_ports_3_bits_uop_iq_type_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iq_type_2_0 = io_wakeup_ports_3_bits_uop_iq_type_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iq_type_3_0 = io_wakeup_ports_3_bits_uop_iq_type_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_0_0 = io_wakeup_ports_3_bits_uop_fu_code_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_1_0 = io_wakeup_ports_3_bits_uop_fu_code_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_2_0 = io_wakeup_ports_3_bits_uop_fu_code_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_3_0 = io_wakeup_ports_3_bits_uop_fu_code_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_4_0 = io_wakeup_ports_3_bits_uop_fu_code_4; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_5_0 = io_wakeup_ports_3_bits_uop_fu_code_5; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_6_0 = io_wakeup_ports_3_bits_uop_fu_code_6; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_7_0 = io_wakeup_ports_3_bits_uop_fu_code_7; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_8_0 = io_wakeup_ports_3_bits_uop_fu_code_8; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_9_0 = io_wakeup_ports_3_bits_uop_fu_code_9; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iw_issued_0 = io_wakeup_ports_3_bits_uop_iw_issued; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_3_bits_uop_iw_p1_speculative_child_0 = io_wakeup_ports_3_bits_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_3_bits_uop_iw_p2_speculative_child_0 = io_wakeup_ports_3_bits_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iw_p1_bypass_hint_0 = io_wakeup_ports_3_bits_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iw_p2_bypass_hint_0 = io_wakeup_ports_3_bits_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iw_p3_bypass_hint_0 = io_wakeup_ports_3_bits_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_3_bits_uop_dis_col_sel_0 = io_wakeup_ports_3_bits_uop_dis_col_sel; // @[issue-slot.scala:49:7] wire [15:0] io_wakeup_ports_3_bits_uop_br_mask_0 = io_wakeup_ports_3_bits_uop_br_mask; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_3_bits_uop_br_tag_0 = io_wakeup_ports_3_bits_uop_br_tag; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_3_bits_uop_br_type_0 = io_wakeup_ports_3_bits_uop_br_type; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_sfb_0 = io_wakeup_ports_3_bits_uop_is_sfb; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_fence_0 = io_wakeup_ports_3_bits_uop_is_fence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_fencei_0 = io_wakeup_ports_3_bits_uop_is_fencei; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_sfence_0 = io_wakeup_ports_3_bits_uop_is_sfence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_amo_0 = io_wakeup_ports_3_bits_uop_is_amo; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_eret_0 = io_wakeup_ports_3_bits_uop_is_eret; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_sys_pc2epc_0 = io_wakeup_ports_3_bits_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_rocc_0 = io_wakeup_ports_3_bits_uop_is_rocc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_mov_0 = io_wakeup_ports_3_bits_uop_is_mov; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_3_bits_uop_ftq_idx_0 = io_wakeup_ports_3_bits_uop_ftq_idx; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_edge_inst_0 = io_wakeup_ports_3_bits_uop_edge_inst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_3_bits_uop_pc_lob_0 = io_wakeup_ports_3_bits_uop_pc_lob; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_taken_0 = io_wakeup_ports_3_bits_uop_taken; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_imm_rename_0 = io_wakeup_ports_3_bits_uop_imm_rename; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_3_bits_uop_imm_sel_0 = io_wakeup_ports_3_bits_uop_imm_sel; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_3_bits_uop_pimm_0 = io_wakeup_ports_3_bits_uop_pimm; // @[issue-slot.scala:49:7] wire [19:0] io_wakeup_ports_3_bits_uop_imm_packed_0 = io_wakeup_ports_3_bits_uop_imm_packed; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_op1_sel_0 = io_wakeup_ports_3_bits_uop_op1_sel; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_3_bits_uop_op2_sel_0 = io_wakeup_ports_3_bits_uop_op2_sel; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_ldst_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_wen_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_ren1_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_ren2_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_ren3_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_swap12_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_swap23_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_fromint_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_toint_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_fma_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_div_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_div; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_sqrt_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_wflags_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_vec_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_3_bits_uop_rob_idx_0 = io_wakeup_ports_3_bits_uop_rob_idx; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_3_bits_uop_ldq_idx_0 = io_wakeup_ports_3_bits_uop_ldq_idx; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_3_bits_uop_stq_idx_0 = io_wakeup_ports_3_bits_uop_stq_idx; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_rxq_idx_0 = io_wakeup_ports_3_bits_uop_rxq_idx; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_3_bits_uop_pdst_0 = io_wakeup_ports_3_bits_uop_pdst; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_3_bits_uop_prs1_0 = io_wakeup_ports_3_bits_uop_prs1; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_3_bits_uop_prs2_0 = io_wakeup_ports_3_bits_uop_prs2; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_3_bits_uop_prs3_0 = io_wakeup_ports_3_bits_uop_prs3; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_3_bits_uop_ppred_0 = io_wakeup_ports_3_bits_uop_ppred; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_prs1_busy_0 = io_wakeup_ports_3_bits_uop_prs1_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_prs2_busy_0 = io_wakeup_ports_3_bits_uop_prs2_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_prs3_busy_0 = io_wakeup_ports_3_bits_uop_prs3_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_ppred_busy_0 = io_wakeup_ports_3_bits_uop_ppred_busy; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_3_bits_uop_stale_pdst_0 = io_wakeup_ports_3_bits_uop_stale_pdst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_exception_0 = io_wakeup_ports_3_bits_uop_exception; // @[issue-slot.scala:49:7] wire [63:0] io_wakeup_ports_3_bits_uop_exc_cause_0 = io_wakeup_ports_3_bits_uop_exc_cause; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_3_bits_uop_mem_cmd_0 = io_wakeup_ports_3_bits_uop_mem_cmd; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_mem_size_0 = io_wakeup_ports_3_bits_uop_mem_size; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_mem_signed_0 = io_wakeup_ports_3_bits_uop_mem_signed; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_uses_ldq_0 = io_wakeup_ports_3_bits_uop_uses_ldq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_uses_stq_0 = io_wakeup_ports_3_bits_uop_uses_stq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_unique_0 = io_wakeup_ports_3_bits_uop_is_unique; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_flush_on_commit_0 = io_wakeup_ports_3_bits_uop_flush_on_commit; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_3_bits_uop_csr_cmd_0 = io_wakeup_ports_3_bits_uop_csr_cmd; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_ldst_is_rs1_0 = io_wakeup_ports_3_bits_uop_ldst_is_rs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_3_bits_uop_ldst_0 = io_wakeup_ports_3_bits_uop_ldst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_3_bits_uop_lrs1_0 = io_wakeup_ports_3_bits_uop_lrs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_3_bits_uop_lrs2_0 = io_wakeup_ports_3_bits_uop_lrs2; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_3_bits_uop_lrs3_0 = io_wakeup_ports_3_bits_uop_lrs3; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_dst_rtype_0 = io_wakeup_ports_3_bits_uop_dst_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_lrs1_rtype_0 = io_wakeup_ports_3_bits_uop_lrs1_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_lrs2_rtype_0 = io_wakeup_ports_3_bits_uop_lrs2_rtype; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_frs3_en_0 = io_wakeup_ports_3_bits_uop_frs3_en; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fcn_dw_0 = io_wakeup_ports_3_bits_uop_fcn_dw; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_3_bits_uop_fcn_op_0 = io_wakeup_ports_3_bits_uop_fcn_op; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_val_0 = io_wakeup_ports_3_bits_uop_fp_val; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_3_bits_uop_fp_rm_0 = io_wakeup_ports_3_bits_uop_fp_rm; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_fp_typ_0 = io_wakeup_ports_3_bits_uop_fp_typ; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_xcpt_pf_if_0 = io_wakeup_ports_3_bits_uop_xcpt_pf_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_xcpt_ae_if_0 = io_wakeup_ports_3_bits_uop_xcpt_ae_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_xcpt_ma_if_0 = io_wakeup_ports_3_bits_uop_xcpt_ma_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_bp_debug_if_0 = io_wakeup_ports_3_bits_uop_bp_debug_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_bp_xcpt_if_0 = io_wakeup_ports_3_bits_uop_bp_xcpt_if; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_3_bits_uop_debug_fsrc_0 = io_wakeup_ports_3_bits_uop_debug_fsrc; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_3_bits_uop_debug_tsrc_0 = io_wakeup_ports_3_bits_uop_debug_tsrc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_valid_0 = io_wakeup_ports_4_valid; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_4_bits_uop_inst_0 = io_wakeup_ports_4_bits_uop_inst; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_4_bits_uop_debug_inst_0 = io_wakeup_ports_4_bits_uop_debug_inst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_is_rvc_0 = io_wakeup_ports_4_bits_uop_is_rvc; // @[issue-slot.scala:49:7] wire [39:0] io_wakeup_ports_4_bits_uop_debug_pc_0 = io_wakeup_ports_4_bits_uop_debug_pc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_iq_type_0_0 = io_wakeup_ports_4_bits_uop_iq_type_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_iq_type_1_0 = io_wakeup_ports_4_bits_uop_iq_type_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_iq_type_2_0 = io_wakeup_ports_4_bits_uop_iq_type_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_iq_type_3_0 = io_wakeup_ports_4_bits_uop_iq_type_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fu_code_0_0 = io_wakeup_ports_4_bits_uop_fu_code_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fu_code_1_0 = io_wakeup_ports_4_bits_uop_fu_code_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fu_code_2_0 = io_wakeup_ports_4_bits_uop_fu_code_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fu_code_3_0 = io_wakeup_ports_4_bits_uop_fu_code_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fu_code_4_0 = io_wakeup_ports_4_bits_uop_fu_code_4; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fu_code_5_0 = io_wakeup_ports_4_bits_uop_fu_code_5; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fu_code_6_0 = io_wakeup_ports_4_bits_uop_fu_code_6; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fu_code_7_0 = io_wakeup_ports_4_bits_uop_fu_code_7; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fu_code_8_0 = io_wakeup_ports_4_bits_uop_fu_code_8; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fu_code_9_0 = io_wakeup_ports_4_bits_uop_fu_code_9; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_iw_issued_0 = io_wakeup_ports_4_bits_uop_iw_issued; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_4_bits_uop_iw_p1_speculative_child_0 = io_wakeup_ports_4_bits_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_4_bits_uop_iw_p2_speculative_child_0 = io_wakeup_ports_4_bits_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_iw_p1_bypass_hint_0 = io_wakeup_ports_4_bits_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_iw_p2_bypass_hint_0 = io_wakeup_ports_4_bits_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_iw_p3_bypass_hint_0 = io_wakeup_ports_4_bits_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_4_bits_uop_dis_col_sel_0 = io_wakeup_ports_4_bits_uop_dis_col_sel; // @[issue-slot.scala:49:7] wire [15:0] io_wakeup_ports_4_bits_uop_br_mask_0 = io_wakeup_ports_4_bits_uop_br_mask; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_4_bits_uop_br_tag_0 = io_wakeup_ports_4_bits_uop_br_tag; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_4_bits_uop_br_type_0 = io_wakeup_ports_4_bits_uop_br_type; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_is_sfb_0 = io_wakeup_ports_4_bits_uop_is_sfb; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_is_fence_0 = io_wakeup_ports_4_bits_uop_is_fence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_is_fencei_0 = io_wakeup_ports_4_bits_uop_is_fencei; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_is_sfence_0 = io_wakeup_ports_4_bits_uop_is_sfence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_is_amo_0 = io_wakeup_ports_4_bits_uop_is_amo; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_is_eret_0 = io_wakeup_ports_4_bits_uop_is_eret; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_is_sys_pc2epc_0 = io_wakeup_ports_4_bits_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_is_rocc_0 = io_wakeup_ports_4_bits_uop_is_rocc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_is_mov_0 = io_wakeup_ports_4_bits_uop_is_mov; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_4_bits_uop_ftq_idx_0 = io_wakeup_ports_4_bits_uop_ftq_idx; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_edge_inst_0 = io_wakeup_ports_4_bits_uop_edge_inst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_4_bits_uop_pc_lob_0 = io_wakeup_ports_4_bits_uop_pc_lob; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_taken_0 = io_wakeup_ports_4_bits_uop_taken; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_imm_rename_0 = io_wakeup_ports_4_bits_uop_imm_rename; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_4_bits_uop_imm_sel_0 = io_wakeup_ports_4_bits_uop_imm_sel; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_4_bits_uop_pimm_0 = io_wakeup_ports_4_bits_uop_pimm; // @[issue-slot.scala:49:7] wire [19:0] io_wakeup_ports_4_bits_uop_imm_packed_0 = io_wakeup_ports_4_bits_uop_imm_packed; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_4_bits_uop_op1_sel_0 = io_wakeup_ports_4_bits_uop_op1_sel; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_4_bits_uop_op2_sel_0 = io_wakeup_ports_4_bits_uop_op2_sel; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_ldst_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_wen_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_ren1_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_ren2_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_ren3_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_swap12_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_swap23_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_4_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_4_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_fromint_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_toint_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_fastpipe_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_fma_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_div_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_div; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_sqrt_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_wflags_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_vec_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_4_bits_uop_rob_idx_0 = io_wakeup_ports_4_bits_uop_rob_idx; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_4_bits_uop_ldq_idx_0 = io_wakeup_ports_4_bits_uop_ldq_idx; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_4_bits_uop_stq_idx_0 = io_wakeup_ports_4_bits_uop_stq_idx; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_4_bits_uop_rxq_idx_0 = io_wakeup_ports_4_bits_uop_rxq_idx; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_4_bits_uop_pdst_0 = io_wakeup_ports_4_bits_uop_pdst; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_4_bits_uop_prs1_0 = io_wakeup_ports_4_bits_uop_prs1; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_4_bits_uop_prs2_0 = io_wakeup_ports_4_bits_uop_prs2; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_4_bits_uop_prs3_0 = io_wakeup_ports_4_bits_uop_prs3; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_4_bits_uop_ppred_0 = io_wakeup_ports_4_bits_uop_ppred; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_prs1_busy_0 = io_wakeup_ports_4_bits_uop_prs1_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_prs2_busy_0 = io_wakeup_ports_4_bits_uop_prs2_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_prs3_busy_0 = io_wakeup_ports_4_bits_uop_prs3_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_ppred_busy_0 = io_wakeup_ports_4_bits_uop_ppred_busy; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_4_bits_uop_stale_pdst_0 = io_wakeup_ports_4_bits_uop_stale_pdst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_exception_0 = io_wakeup_ports_4_bits_uop_exception; // @[issue-slot.scala:49:7] wire [63:0] io_wakeup_ports_4_bits_uop_exc_cause_0 = io_wakeup_ports_4_bits_uop_exc_cause; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_4_bits_uop_mem_cmd_0 = io_wakeup_ports_4_bits_uop_mem_cmd; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_4_bits_uop_mem_size_0 = io_wakeup_ports_4_bits_uop_mem_size; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_mem_signed_0 = io_wakeup_ports_4_bits_uop_mem_signed; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_uses_ldq_0 = io_wakeup_ports_4_bits_uop_uses_ldq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_uses_stq_0 = io_wakeup_ports_4_bits_uop_uses_stq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_is_unique_0 = io_wakeup_ports_4_bits_uop_is_unique; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_flush_on_commit_0 = io_wakeup_ports_4_bits_uop_flush_on_commit; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_4_bits_uop_csr_cmd_0 = io_wakeup_ports_4_bits_uop_csr_cmd; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_ldst_is_rs1_0 = io_wakeup_ports_4_bits_uop_ldst_is_rs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_4_bits_uop_ldst_0 = io_wakeup_ports_4_bits_uop_ldst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_4_bits_uop_lrs1_0 = io_wakeup_ports_4_bits_uop_lrs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_4_bits_uop_lrs2_0 = io_wakeup_ports_4_bits_uop_lrs2; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_4_bits_uop_lrs3_0 = io_wakeup_ports_4_bits_uop_lrs3; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_4_bits_uop_dst_rtype_0 = io_wakeup_ports_4_bits_uop_dst_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_4_bits_uop_lrs1_rtype_0 = io_wakeup_ports_4_bits_uop_lrs1_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_4_bits_uop_lrs2_rtype_0 = io_wakeup_ports_4_bits_uop_lrs2_rtype; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_frs3_en_0 = io_wakeup_ports_4_bits_uop_frs3_en; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fcn_dw_0 = io_wakeup_ports_4_bits_uop_fcn_dw; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_4_bits_uop_fcn_op_0 = io_wakeup_ports_4_bits_uop_fcn_op; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fp_val_0 = io_wakeup_ports_4_bits_uop_fp_val; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_4_bits_uop_fp_rm_0 = io_wakeup_ports_4_bits_uop_fp_rm; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_4_bits_uop_fp_typ_0 = io_wakeup_ports_4_bits_uop_fp_typ; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_xcpt_pf_if_0 = io_wakeup_ports_4_bits_uop_xcpt_pf_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_xcpt_ae_if_0 = io_wakeup_ports_4_bits_uop_xcpt_ae_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_xcpt_ma_if_0 = io_wakeup_ports_4_bits_uop_xcpt_ma_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_bp_debug_if_0 = io_wakeup_ports_4_bits_uop_bp_debug_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_bp_xcpt_if_0 = io_wakeup_ports_4_bits_uop_bp_xcpt_if; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_4_bits_uop_debug_fsrc_0 = io_wakeup_ports_4_bits_uop_debug_fsrc; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_4_bits_uop_debug_tsrc_0 = io_wakeup_ports_4_bits_uop_debug_tsrc; // @[issue-slot.scala:49:7] wire io_pred_wakeup_port_valid_0 = io_pred_wakeup_port_valid; // @[issue-slot.scala:49:7] wire [4:0] io_pred_wakeup_port_bits_0 = io_pred_wakeup_port_bits; // @[issue-slot.scala:49:7] wire [2:0] io_child_rebusys_0 = io_child_rebusys; // @[issue-slot.scala:49:7] wire io_iss_uop_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:49:7] wire io_iss_uop_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:49:7] wire io_out_uop_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:49:7] wire io_out_uop_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:49:7] wire io_clear = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_bypassable = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_rebusy = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_rebusy = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_rebusy = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_rebusy = 1'h0; // @[issue-slot.scala:49:7] wire next_uop_out_iw_issued_partial_agen = 1'h0; // @[util.scala:104:23] wire next_uop_out_iw_issued_partial_dgen = 1'h0; // @[util.scala:104:23] wire next_uop_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:59:28] wire next_uop_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:59:28] wire prs1_rebusys_1 = 1'h0; // @[issue-slot.scala:102:91] wire prs1_rebusys_2 = 1'h0; // @[issue-slot.scala:102:91] wire prs1_rebusys_3 = 1'h0; // @[issue-slot.scala:102:91] wire prs1_rebusys_4 = 1'h0; // @[issue-slot.scala:102:91] wire prs2_rebusys_1 = 1'h0; // @[issue-slot.scala:103:91] wire prs2_rebusys_2 = 1'h0; // @[issue-slot.scala:103:91] wire prs2_rebusys_3 = 1'h0; // @[issue-slot.scala:103:91] wire prs2_rebusys_4 = 1'h0; // @[issue-slot.scala:103:91] wire _next_uop_iw_p1_bypass_hint_T_1 = 1'h0; // @[Mux.scala:30:73] wire _next_uop_iw_p2_bypass_hint_T_1 = 1'h0; // @[Mux.scala:30:73] wire _next_uop_iw_p3_bypass_hint_T_1 = 1'h0; // @[Mux.scala:30:73] wire _iss_ready_T_6 = 1'h0; // @[issue-slot.scala:136:131] wire agen_ready = 1'h0; // @[issue-slot.scala:137:114] wire dgen_ready = 1'h0; // @[issue-slot.scala:138:114] wire [2:0] io_wakeup_ports_1_bits_speculative_mask = 3'h0; // @[issue-slot.scala:49:7] wire [2:0] _next_uop_iw_p1_speculative_child_T_1 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _next_uop_iw_p2_speculative_child_T_1 = 3'h0; // @[Mux.scala:30:73] wire io_wakeup_ports_2_bits_bypassable = 1'h1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_bypassable = 1'h1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_bypassable = 1'h1; // @[issue-slot.scala:49:7] wire _iss_ready_T_7 = 1'h1; // @[issue-slot.scala:136:110] wire [2:0] io_wakeup_ports_2_bits_speculative_mask = 3'h1; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_3_bits_speculative_mask = 3'h2; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_4_bits_speculative_mask = 3'h4; // @[issue-slot.scala:49:7] wire _io_will_be_valid_T_1; // @[issue-slot.scala:65:34] wire _io_request_T_4; // @[issue-slot.scala:140:51] wire [31:0] next_uop_inst; // @[issue-slot.scala:59:28] wire [31:0] next_uop_debug_inst; // @[issue-slot.scala:59:28] wire next_uop_is_rvc; // @[issue-slot.scala:59:28] wire [39:0] next_uop_debug_pc; // @[issue-slot.scala:59:28] wire next_uop_iq_type_0; // @[issue-slot.scala:59:28] wire next_uop_iq_type_1; // @[issue-slot.scala:59:28] wire next_uop_iq_type_2; // @[issue-slot.scala:59:28] wire next_uop_iq_type_3; // @[issue-slot.scala:59:28] wire next_uop_fu_code_0; // @[issue-slot.scala:59:28] wire next_uop_fu_code_1; // @[issue-slot.scala:59:28] wire next_uop_fu_code_2; // @[issue-slot.scala:59:28] wire next_uop_fu_code_3; // @[issue-slot.scala:59:28] wire next_uop_fu_code_4; // @[issue-slot.scala:59:28] wire next_uop_fu_code_5; // @[issue-slot.scala:59:28] wire next_uop_fu_code_6; // @[issue-slot.scala:59:28] wire next_uop_fu_code_7; // @[issue-slot.scala:59:28] wire next_uop_fu_code_8; // @[issue-slot.scala:59:28] wire next_uop_fu_code_9; // @[issue-slot.scala:59:28] wire next_uop_iw_issued; // @[issue-slot.scala:59:28] wire [2:0] next_uop_iw_p1_speculative_child; // @[issue-slot.scala:59:28] wire [2:0] next_uop_iw_p2_speculative_child; // @[issue-slot.scala:59:28] wire next_uop_iw_p1_bypass_hint; // @[issue-slot.scala:59:28] wire next_uop_iw_p2_bypass_hint; // @[issue-slot.scala:59:28] wire next_uop_iw_p3_bypass_hint; // @[issue-slot.scala:59:28] wire [2:0] next_uop_dis_col_sel; // @[issue-slot.scala:59:28] wire [15:0] next_uop_br_mask; // @[issue-slot.scala:59:28] wire [3:0] next_uop_br_tag; // @[issue-slot.scala:59:28] wire [3:0] next_uop_br_type; // @[issue-slot.scala:59:28] wire next_uop_is_sfb; // @[issue-slot.scala:59:28] wire next_uop_is_fence; // @[issue-slot.scala:59:28] wire next_uop_is_fencei; // @[issue-slot.scala:59:28] wire next_uop_is_sfence; // @[issue-slot.scala:59:28] wire next_uop_is_amo; // @[issue-slot.scala:59:28] wire next_uop_is_eret; // @[issue-slot.scala:59:28] wire next_uop_is_sys_pc2epc; // @[issue-slot.scala:59:28] wire next_uop_is_rocc; // @[issue-slot.scala:59:28] wire next_uop_is_mov; // @[issue-slot.scala:59:28] wire [4:0] next_uop_ftq_idx; // @[issue-slot.scala:59:28] wire next_uop_edge_inst; // @[issue-slot.scala:59:28] wire [5:0] next_uop_pc_lob; // @[issue-slot.scala:59:28] wire next_uop_taken; // @[issue-slot.scala:59:28] wire next_uop_imm_rename; // @[issue-slot.scala:59:28] wire [2:0] next_uop_imm_sel; // @[issue-slot.scala:59:28] wire [4:0] next_uop_pimm; // @[issue-slot.scala:59:28] wire [19:0] next_uop_imm_packed; // @[issue-slot.scala:59:28] wire [1:0] next_uop_op1_sel; // @[issue-slot.scala:59:28] wire [2:0] next_uop_op2_sel; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_ldst; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_wen; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_ren1; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_ren2; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_ren3; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_swap12; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_swap23; // @[issue-slot.scala:59:28] wire [1:0] next_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:59:28] wire [1:0] next_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_fromint; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_toint; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_fma; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_div; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_sqrt; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_wflags; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_vec; // @[issue-slot.scala:59:28] wire [6:0] next_uop_rob_idx; // @[issue-slot.scala:59:28] wire [4:0] next_uop_ldq_idx; // @[issue-slot.scala:59:28] wire [4:0] next_uop_stq_idx; // @[issue-slot.scala:59:28] wire [1:0] next_uop_rxq_idx; // @[issue-slot.scala:59:28] wire [6:0] next_uop_pdst; // @[issue-slot.scala:59:28] wire [6:0] next_uop_prs1; // @[issue-slot.scala:59:28] wire [6:0] next_uop_prs2; // @[issue-slot.scala:59:28] wire [6:0] next_uop_prs3; // @[issue-slot.scala:59:28] wire [4:0] next_uop_ppred; // @[issue-slot.scala:59:28] wire next_uop_prs1_busy; // @[issue-slot.scala:59:28] wire next_uop_prs2_busy; // @[issue-slot.scala:59:28] wire next_uop_prs3_busy; // @[issue-slot.scala:59:28] wire next_uop_ppred_busy; // @[issue-slot.scala:59:28] wire [6:0] next_uop_stale_pdst; // @[issue-slot.scala:59:28] wire next_uop_exception; // @[issue-slot.scala:59:28] wire [63:0] next_uop_exc_cause; // @[issue-slot.scala:59:28] wire [4:0] next_uop_mem_cmd; // @[issue-slot.scala:59:28] wire [1:0] next_uop_mem_size; // @[issue-slot.scala:59:28] wire next_uop_mem_signed; // @[issue-slot.scala:59:28] wire next_uop_uses_ldq; // @[issue-slot.scala:59:28] wire next_uop_uses_stq; // @[issue-slot.scala:59:28] wire next_uop_is_unique; // @[issue-slot.scala:59:28] wire next_uop_flush_on_commit; // @[issue-slot.scala:59:28] wire [2:0] next_uop_csr_cmd; // @[issue-slot.scala:59:28] wire next_uop_ldst_is_rs1; // @[issue-slot.scala:59:28] wire [5:0] next_uop_ldst; // @[issue-slot.scala:59:28] wire [5:0] next_uop_lrs1; // @[issue-slot.scala:59:28] wire [5:0] next_uop_lrs2; // @[issue-slot.scala:59:28] wire [5:0] next_uop_lrs3; // @[issue-slot.scala:59:28] wire [1:0] next_uop_dst_rtype; // @[issue-slot.scala:59:28] wire [1:0] next_uop_lrs1_rtype; // @[issue-slot.scala:59:28] wire [1:0] next_uop_lrs2_rtype; // @[issue-slot.scala:59:28] wire next_uop_frs3_en; // @[issue-slot.scala:59:28] wire next_uop_fcn_dw; // @[issue-slot.scala:59:28] wire [4:0] next_uop_fcn_op; // @[issue-slot.scala:59:28] wire next_uop_fp_val; // @[issue-slot.scala:59:28] wire [2:0] next_uop_fp_rm; // @[issue-slot.scala:59:28] wire [1:0] next_uop_fp_typ; // @[issue-slot.scala:59:28] wire next_uop_xcpt_pf_if; // @[issue-slot.scala:59:28] wire next_uop_xcpt_ae_if; // @[issue-slot.scala:59:28] wire next_uop_xcpt_ma_if; // @[issue-slot.scala:59:28] wire next_uop_bp_debug_if; // @[issue-slot.scala:59:28] wire next_uop_bp_xcpt_if; // @[issue-slot.scala:59:28] wire [2:0] next_uop_debug_fsrc; // @[issue-slot.scala:59:28] wire [2:0] next_uop_debug_tsrc; // @[issue-slot.scala:59:28] wire io_iss_uop_iq_type_0_0; // @[issue-slot.scala:49:7] wire io_iss_uop_iq_type_1_0; // @[issue-slot.scala:49:7] wire io_iss_uop_iq_type_2_0; // @[issue-slot.scala:49:7] wire io_iss_uop_iq_type_3_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_0_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_1_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_2_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_3_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_4_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_5_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_6_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_7_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_8_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_9_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_ldst_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_wen_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_ren1_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_ren2_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_ren3_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_swap12_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_swap23_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_fp_ctrl_typeTagIn_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_fp_ctrl_typeTagOut_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_fromint_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_toint_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_fastpipe_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_fma_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_div_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_sqrt_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_wflags_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_vec_0; // @[issue-slot.scala:49:7] wire [31:0] io_iss_uop_inst_0; // @[issue-slot.scala:49:7] wire [31:0] io_iss_uop_debug_inst_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_rvc_0; // @[issue-slot.scala:49:7] wire [39:0] io_iss_uop_debug_pc_0; // @[issue-slot.scala:49:7] wire io_iss_uop_iw_issued_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_iw_p1_speculative_child_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_iw_p2_speculative_child_0; // @[issue-slot.scala:49:7] wire io_iss_uop_iw_p1_bypass_hint_0; // @[issue-slot.scala:49:7] wire io_iss_uop_iw_p2_bypass_hint_0; // @[issue-slot.scala:49:7] wire io_iss_uop_iw_p3_bypass_hint_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_dis_col_sel_0; // @[issue-slot.scala:49:7] wire [15:0] io_iss_uop_br_mask_0; // @[issue-slot.scala:49:7] wire [3:0] io_iss_uop_br_tag_0; // @[issue-slot.scala:49:7] wire [3:0] io_iss_uop_br_type_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_sfb_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_fence_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_fencei_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_sfence_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_amo_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_eret_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_sys_pc2epc_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_rocc_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_mov_0; // @[issue-slot.scala:49:7] wire [4:0] io_iss_uop_ftq_idx_0; // @[issue-slot.scala:49:7] wire io_iss_uop_edge_inst_0; // @[issue-slot.scala:49:7] wire [5:0] io_iss_uop_pc_lob_0; // @[issue-slot.scala:49:7] wire io_iss_uop_taken_0; // @[issue-slot.scala:49:7] wire io_iss_uop_imm_rename_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_imm_sel_0; // @[issue-slot.scala:49:7] wire [4:0] io_iss_uop_pimm_0; // @[issue-slot.scala:49:7] wire [19:0] io_iss_uop_imm_packed_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_op1_sel_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_op2_sel_0; // @[issue-slot.scala:49:7] wire [6:0] io_iss_uop_rob_idx_0; // @[issue-slot.scala:49:7] wire [4:0] io_iss_uop_ldq_idx_0; // @[issue-slot.scala:49:7] wire [4:0] io_iss_uop_stq_idx_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_rxq_idx_0; // @[issue-slot.scala:49:7] wire [6:0] io_iss_uop_pdst_0; // @[issue-slot.scala:49:7] wire [6:0] io_iss_uop_prs1_0; // @[issue-slot.scala:49:7] wire [6:0] io_iss_uop_prs2_0; // @[issue-slot.scala:49:7] wire [6:0] io_iss_uop_prs3_0; // @[issue-slot.scala:49:7] wire [4:0] io_iss_uop_ppred_0; // @[issue-slot.scala:49:7] wire io_iss_uop_prs1_busy_0; // @[issue-slot.scala:49:7] wire io_iss_uop_prs2_busy_0; // @[issue-slot.scala:49:7] wire io_iss_uop_prs3_busy_0; // @[issue-slot.scala:49:7] wire io_iss_uop_ppred_busy_0; // @[issue-slot.scala:49:7] wire [6:0] io_iss_uop_stale_pdst_0; // @[issue-slot.scala:49:7] wire io_iss_uop_exception_0; // @[issue-slot.scala:49:7] wire [63:0] io_iss_uop_exc_cause_0; // @[issue-slot.scala:49:7] wire [4:0] io_iss_uop_mem_cmd_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_mem_size_0; // @[issue-slot.scala:49:7] wire io_iss_uop_mem_signed_0; // @[issue-slot.scala:49:7] wire io_iss_uop_uses_ldq_0; // @[issue-slot.scala:49:7] wire io_iss_uop_uses_stq_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_unique_0; // @[issue-slot.scala:49:7] wire io_iss_uop_flush_on_commit_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_csr_cmd_0; // @[issue-slot.scala:49:7] wire io_iss_uop_ldst_is_rs1_0; // @[issue-slot.scala:49:7] wire [5:0] io_iss_uop_ldst_0; // @[issue-slot.scala:49:7] wire [5:0] io_iss_uop_lrs1_0; // @[issue-slot.scala:49:7] wire [5:0] io_iss_uop_lrs2_0; // @[issue-slot.scala:49:7] wire [5:0] io_iss_uop_lrs3_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_dst_rtype_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_lrs1_rtype_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_lrs2_rtype_0; // @[issue-slot.scala:49:7] wire io_iss_uop_frs3_en_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fcn_dw_0; // @[issue-slot.scala:49:7] wire [4:0] io_iss_uop_fcn_op_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_val_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_fp_rm_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_fp_typ_0; // @[issue-slot.scala:49:7] wire io_iss_uop_xcpt_pf_if_0; // @[issue-slot.scala:49:7] wire io_iss_uop_xcpt_ae_if_0; // @[issue-slot.scala:49:7] wire io_iss_uop_xcpt_ma_if_0; // @[issue-slot.scala:49:7] wire io_iss_uop_bp_debug_if_0; // @[issue-slot.scala:49:7] wire io_iss_uop_bp_xcpt_if_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_debug_fsrc_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_debug_tsrc_0; // @[issue-slot.scala:49:7] wire io_out_uop_iq_type_0_0; // @[issue-slot.scala:49:7] wire io_out_uop_iq_type_1_0; // @[issue-slot.scala:49:7] wire io_out_uop_iq_type_2_0; // @[issue-slot.scala:49:7] wire io_out_uop_iq_type_3_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_0_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_1_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_2_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_3_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_4_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_5_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_6_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_7_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_8_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_9_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_ldst_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_wen_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_ren1_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_ren2_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_ren3_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_swap12_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_swap23_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_fp_ctrl_typeTagIn_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_fp_ctrl_typeTagOut_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_fromint_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_toint_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_fastpipe_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_fma_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_div_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_sqrt_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_wflags_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_vec_0; // @[issue-slot.scala:49:7] wire [31:0] io_out_uop_inst_0; // @[issue-slot.scala:49:7] wire [31:0] io_out_uop_debug_inst_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_rvc_0; // @[issue-slot.scala:49:7] wire [39:0] io_out_uop_debug_pc_0; // @[issue-slot.scala:49:7] wire io_out_uop_iw_issued_0; // @[issue-slot.scala:49:7] wire [2:0] io_out_uop_iw_p1_speculative_child_0; // @[issue-slot.scala:49:7] wire [2:0] io_out_uop_iw_p2_speculative_child_0; // @[issue-slot.scala:49:7] wire io_out_uop_iw_p1_bypass_hint_0; // @[issue-slot.scala:49:7] wire io_out_uop_iw_p2_bypass_hint_0; // @[issue-slot.scala:49:7] wire io_out_uop_iw_p3_bypass_hint_0; // @[issue-slot.scala:49:7] wire [2:0] io_out_uop_dis_col_sel_0; // @[issue-slot.scala:49:7] wire [15:0] io_out_uop_br_mask_0; // @[issue-slot.scala:49:7] wire [3:0] io_out_uop_br_tag_0; // @[issue-slot.scala:49:7] wire [3:0] io_out_uop_br_type_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_sfb_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_fence_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_fencei_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_sfence_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_amo_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_eret_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_sys_pc2epc_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_rocc_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_mov_0; // @[issue-slot.scala:49:7] wire [4:0] io_out_uop_ftq_idx_0; // @[issue-slot.scala:49:7] wire io_out_uop_edge_inst_0; // @[issue-slot.scala:49:7] wire [5:0] io_out_uop_pc_lob_0; // @[issue-slot.scala:49:7] wire io_out_uop_taken_0; // @[issue-slot.scala:49:7] wire io_out_uop_imm_rename_0; // @[issue-slot.scala:49:7] wire [2:0] io_out_uop_imm_sel_0; // @[issue-slot.scala:49:7] wire [4:0] io_out_uop_pimm_0; // @[issue-slot.scala:49:7] wire [19:0] io_out_uop_imm_packed_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_op1_sel_0; // @[issue-slot.scala:49:7] wire [2:0] io_out_uop_op2_sel_0; // @[issue-slot.scala:49:7] wire [6:0] io_out_uop_rob_idx_0; // @[issue-slot.scala:49:7] wire [4:0] io_out_uop_ldq_idx_0; // @[issue-slot.scala:49:7] wire [4:0] io_out_uop_stq_idx_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_rxq_idx_0; // @[issue-slot.scala:49:7] wire [6:0] io_out_uop_pdst_0; // @[issue-slot.scala:49:7] wire [6:0] io_out_uop_prs1_0; // @[issue-slot.scala:49:7] wire [6:0] io_out_uop_prs2_0; // @[issue-slot.scala:49:7] wire [6:0] io_out_uop_prs3_0; // @[issue-slot.scala:49:7] wire [4:0] io_out_uop_ppred_0; // @[issue-slot.scala:49:7] wire io_out_uop_prs1_busy_0; // @[issue-slot.scala:49:7] wire io_out_uop_prs2_busy_0; // @[issue-slot.scala:49:7] wire io_out_uop_prs3_busy_0; // @[issue-slot.scala:49:7] wire io_out_uop_ppred_busy_0; // @[issue-slot.scala:49:7] wire [6:0] io_out_uop_stale_pdst_0; // @[issue-slot.scala:49:7] wire io_out_uop_exception_0; // @[issue-slot.scala:49:7] wire [63:0] io_out_uop_exc_cause_0; // @[issue-slot.scala:49:7] wire [4:0] io_out_uop_mem_cmd_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_mem_size_0; // @[issue-slot.scala:49:7] wire io_out_uop_mem_signed_0; // @[issue-slot.scala:49:7] wire io_out_uop_uses_ldq_0; // @[issue-slot.scala:49:7] wire io_out_uop_uses_stq_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_unique_0; // @[issue-slot.scala:49:7] wire io_out_uop_flush_on_commit_0; // @[issue-slot.scala:49:7] wire [2:0] io_out_uop_csr_cmd_0; // @[issue-slot.scala:49:7] wire io_out_uop_ldst_is_rs1_0; // @[issue-slot.scala:49:7] wire [5:0] io_out_uop_ldst_0; // @[issue-slot.scala:49:7] wire [5:0] io_out_uop_lrs1_0; // @[issue-slot.scala:49:7] wire [5:0] io_out_uop_lrs2_0; // @[issue-slot.scala:49:7] wire [5:0] io_out_uop_lrs3_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_dst_rtype_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_lrs1_rtype_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_lrs2_rtype_0; // @[issue-slot.scala:49:7] wire io_out_uop_frs3_en_0; // @[issue-slot.scala:49:7] wire io_out_uop_fcn_dw_0; // @[issue-slot.scala:49:7] wire [4:0] io_out_uop_fcn_op_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_val_0; // @[issue-slot.scala:49:7] wire [2:0] io_out_uop_fp_rm_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_fp_typ_0; // @[issue-slot.scala:49:7] wire io_out_uop_xcpt_pf_if_0; // @[issue-slot.scala:49:7] wire io_out_uop_xcpt_ae_if_0; // @[issue-slot.scala:49:7] wire io_out_uop_xcpt_ma_if_0; // @[issue-slot.scala:49:7] wire io_out_uop_bp_debug_if_0; // @[issue-slot.scala:49:7] wire io_out_uop_bp_xcpt_if_0; // @[issue-slot.scala:49:7] wire [2:0] io_out_uop_debug_fsrc_0; // @[issue-slot.scala:49:7] wire [2:0] io_out_uop_debug_tsrc_0; // @[issue-slot.scala:49:7] wire io_valid_0; // @[issue-slot.scala:49:7] wire io_will_be_valid_0; // @[issue-slot.scala:49:7] wire io_request_0; // @[issue-slot.scala:49:7] reg slot_valid; // @[issue-slot.scala:55:27] assign io_valid_0 = slot_valid; // @[issue-slot.scala:49:7, :55:27] reg [31:0] slot_uop_inst; // @[issue-slot.scala:56:21] assign io_iss_uop_inst_0 = slot_uop_inst; // @[issue-slot.scala:49:7, :56:21] wire [31:0] next_uop_out_inst = slot_uop_inst; // @[util.scala:104:23] reg [31:0] slot_uop_debug_inst; // @[issue-slot.scala:56:21] assign io_iss_uop_debug_inst_0 = slot_uop_debug_inst; // @[issue-slot.scala:49:7, :56:21] wire [31:0] next_uop_out_debug_inst = slot_uop_debug_inst; // @[util.scala:104:23] reg slot_uop_is_rvc; // @[issue-slot.scala:56:21] assign io_iss_uop_is_rvc_0 = slot_uop_is_rvc; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_rvc = slot_uop_is_rvc; // @[util.scala:104:23] reg [39:0] slot_uop_debug_pc; // @[issue-slot.scala:56:21] assign io_iss_uop_debug_pc_0 = slot_uop_debug_pc; // @[issue-slot.scala:49:7, :56:21] wire [39:0] next_uop_out_debug_pc = slot_uop_debug_pc; // @[util.scala:104:23] reg slot_uop_iq_type_0; // @[issue-slot.scala:56:21] assign io_iss_uop_iq_type_0_0 = slot_uop_iq_type_0; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iq_type_0 = slot_uop_iq_type_0; // @[util.scala:104:23] reg slot_uop_iq_type_1; // @[issue-slot.scala:56:21] assign io_iss_uop_iq_type_1_0 = slot_uop_iq_type_1; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iq_type_1 = slot_uop_iq_type_1; // @[util.scala:104:23] reg slot_uop_iq_type_2; // @[issue-slot.scala:56:21] assign io_iss_uop_iq_type_2_0 = slot_uop_iq_type_2; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iq_type_2 = slot_uop_iq_type_2; // @[util.scala:104:23] reg slot_uop_iq_type_3; // @[issue-slot.scala:56:21] assign io_iss_uop_iq_type_3_0 = slot_uop_iq_type_3; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iq_type_3 = slot_uop_iq_type_3; // @[util.scala:104:23] reg slot_uop_fu_code_0; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_0_0 = slot_uop_fu_code_0; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_0 = slot_uop_fu_code_0; // @[util.scala:104:23] reg slot_uop_fu_code_1; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_1_0 = slot_uop_fu_code_1; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_1 = slot_uop_fu_code_1; // @[util.scala:104:23] reg slot_uop_fu_code_2; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_2_0 = slot_uop_fu_code_2; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_2 = slot_uop_fu_code_2; // @[util.scala:104:23] reg slot_uop_fu_code_3; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_3_0 = slot_uop_fu_code_3; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_3 = slot_uop_fu_code_3; // @[util.scala:104:23] reg slot_uop_fu_code_4; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_4_0 = slot_uop_fu_code_4; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_4 = slot_uop_fu_code_4; // @[util.scala:104:23] reg slot_uop_fu_code_5; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_5_0 = slot_uop_fu_code_5; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_5 = slot_uop_fu_code_5; // @[util.scala:104:23] reg slot_uop_fu_code_6; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_6_0 = slot_uop_fu_code_6; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_6 = slot_uop_fu_code_6; // @[util.scala:104:23] reg slot_uop_fu_code_7; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_7_0 = slot_uop_fu_code_7; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_7 = slot_uop_fu_code_7; // @[util.scala:104:23] reg slot_uop_fu_code_8; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_8_0 = slot_uop_fu_code_8; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_8 = slot_uop_fu_code_8; // @[util.scala:104:23] reg slot_uop_fu_code_9; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_9_0 = slot_uop_fu_code_9; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_9 = slot_uop_fu_code_9; // @[util.scala:104:23] reg slot_uop_iw_issued; // @[issue-slot.scala:56:21] assign io_iss_uop_iw_issued_0 = slot_uop_iw_issued; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iw_issued = slot_uop_iw_issued; // @[util.scala:104:23] reg [2:0] slot_uop_iw_p1_speculative_child; // @[issue-slot.scala:56:21] assign io_iss_uop_iw_p1_speculative_child_0 = slot_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7, :56:21] wire [2:0] next_uop_out_iw_p1_speculative_child = slot_uop_iw_p1_speculative_child; // @[util.scala:104:23] reg [2:0] slot_uop_iw_p2_speculative_child; // @[issue-slot.scala:56:21] assign io_iss_uop_iw_p2_speculative_child_0 = slot_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7, :56:21] wire [2:0] next_uop_out_iw_p2_speculative_child = slot_uop_iw_p2_speculative_child; // @[util.scala:104:23] reg slot_uop_iw_p1_bypass_hint; // @[issue-slot.scala:56:21] assign io_iss_uop_iw_p1_bypass_hint_0 = slot_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iw_p1_bypass_hint = slot_uop_iw_p1_bypass_hint; // @[util.scala:104:23] reg slot_uop_iw_p2_bypass_hint; // @[issue-slot.scala:56:21] assign io_iss_uop_iw_p2_bypass_hint_0 = slot_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iw_p2_bypass_hint = slot_uop_iw_p2_bypass_hint; // @[util.scala:104:23] reg slot_uop_iw_p3_bypass_hint; // @[issue-slot.scala:56:21] assign io_iss_uop_iw_p3_bypass_hint_0 = slot_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iw_p3_bypass_hint = slot_uop_iw_p3_bypass_hint; // @[util.scala:104:23] reg [2:0] slot_uop_dis_col_sel; // @[issue-slot.scala:56:21] assign io_iss_uop_dis_col_sel_0 = slot_uop_dis_col_sel; // @[issue-slot.scala:49:7, :56:21] wire [2:0] next_uop_out_dis_col_sel = slot_uop_dis_col_sel; // @[util.scala:104:23] reg [15:0] slot_uop_br_mask; // @[issue-slot.scala:56:21] assign io_iss_uop_br_mask_0 = slot_uop_br_mask; // @[issue-slot.scala:49:7, :56:21] reg [3:0] slot_uop_br_tag; // @[issue-slot.scala:56:21] assign io_iss_uop_br_tag_0 = slot_uop_br_tag; // @[issue-slot.scala:49:7, :56:21] wire [3:0] next_uop_out_br_tag = slot_uop_br_tag; // @[util.scala:104:23] reg [3:0] slot_uop_br_type; // @[issue-slot.scala:56:21] assign io_iss_uop_br_type_0 = slot_uop_br_type; // @[issue-slot.scala:49:7, :56:21] wire [3:0] next_uop_out_br_type = slot_uop_br_type; // @[util.scala:104:23] reg slot_uop_is_sfb; // @[issue-slot.scala:56:21] assign io_iss_uop_is_sfb_0 = slot_uop_is_sfb; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_sfb = slot_uop_is_sfb; // @[util.scala:104:23] reg slot_uop_is_fence; // @[issue-slot.scala:56:21] assign io_iss_uop_is_fence_0 = slot_uop_is_fence; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_fence = slot_uop_is_fence; // @[util.scala:104:23] reg slot_uop_is_fencei; // @[issue-slot.scala:56:21] assign io_iss_uop_is_fencei_0 = slot_uop_is_fencei; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_fencei = slot_uop_is_fencei; // @[util.scala:104:23] reg slot_uop_is_sfence; // @[issue-slot.scala:56:21] assign io_iss_uop_is_sfence_0 = slot_uop_is_sfence; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_sfence = slot_uop_is_sfence; // @[util.scala:104:23] reg slot_uop_is_amo; // @[issue-slot.scala:56:21] assign io_iss_uop_is_amo_0 = slot_uop_is_amo; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_amo = slot_uop_is_amo; // @[util.scala:104:23] reg slot_uop_is_eret; // @[issue-slot.scala:56:21] assign io_iss_uop_is_eret_0 = slot_uop_is_eret; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_eret = slot_uop_is_eret; // @[util.scala:104:23] reg slot_uop_is_sys_pc2epc; // @[issue-slot.scala:56:21] assign io_iss_uop_is_sys_pc2epc_0 = slot_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_sys_pc2epc = slot_uop_is_sys_pc2epc; // @[util.scala:104:23] reg slot_uop_is_rocc; // @[issue-slot.scala:56:21] assign io_iss_uop_is_rocc_0 = slot_uop_is_rocc; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_rocc = slot_uop_is_rocc; // @[util.scala:104:23] reg slot_uop_is_mov; // @[issue-slot.scala:56:21] assign io_iss_uop_is_mov_0 = slot_uop_is_mov; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_mov = slot_uop_is_mov; // @[util.scala:104:23] reg [4:0] slot_uop_ftq_idx; // @[issue-slot.scala:56:21] assign io_iss_uop_ftq_idx_0 = slot_uop_ftq_idx; // @[issue-slot.scala:49:7, :56:21] wire [4:0] next_uop_out_ftq_idx = slot_uop_ftq_idx; // @[util.scala:104:23] reg slot_uop_edge_inst; // @[issue-slot.scala:56:21] assign io_iss_uop_edge_inst_0 = slot_uop_edge_inst; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_edge_inst = slot_uop_edge_inst; // @[util.scala:104:23] reg [5:0] slot_uop_pc_lob; // @[issue-slot.scala:56:21] assign io_iss_uop_pc_lob_0 = slot_uop_pc_lob; // @[issue-slot.scala:49:7, :56:21] wire [5:0] next_uop_out_pc_lob = slot_uop_pc_lob; // @[util.scala:104:23] reg slot_uop_taken; // @[issue-slot.scala:56:21] assign io_iss_uop_taken_0 = slot_uop_taken; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_taken = slot_uop_taken; // @[util.scala:104:23] reg slot_uop_imm_rename; // @[issue-slot.scala:56:21] assign io_iss_uop_imm_rename_0 = slot_uop_imm_rename; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_imm_rename = slot_uop_imm_rename; // @[util.scala:104:23] reg [2:0] slot_uop_imm_sel; // @[issue-slot.scala:56:21] assign io_iss_uop_imm_sel_0 = slot_uop_imm_sel; // @[issue-slot.scala:49:7, :56:21] wire [2:0] next_uop_out_imm_sel = slot_uop_imm_sel; // @[util.scala:104:23] reg [4:0] slot_uop_pimm; // @[issue-slot.scala:56:21] assign io_iss_uop_pimm_0 = slot_uop_pimm; // @[issue-slot.scala:49:7, :56:21] wire [4:0] next_uop_out_pimm = slot_uop_pimm; // @[util.scala:104:23] reg [19:0] slot_uop_imm_packed; // @[issue-slot.scala:56:21] assign io_iss_uop_imm_packed_0 = slot_uop_imm_packed; // @[issue-slot.scala:49:7, :56:21] wire [19:0] next_uop_out_imm_packed = slot_uop_imm_packed; // @[util.scala:104:23] reg [1:0] slot_uop_op1_sel; // @[issue-slot.scala:56:21] assign io_iss_uop_op1_sel_0 = slot_uop_op1_sel; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_op1_sel = slot_uop_op1_sel; // @[util.scala:104:23] reg [2:0] slot_uop_op2_sel; // @[issue-slot.scala:56:21] assign io_iss_uop_op2_sel_0 = slot_uop_op2_sel; // @[issue-slot.scala:49:7, :56:21] wire [2:0] next_uop_out_op2_sel = slot_uop_op2_sel; // @[util.scala:104:23] reg slot_uop_fp_ctrl_ldst; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_ldst_0 = slot_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_ldst = slot_uop_fp_ctrl_ldst; // @[util.scala:104:23] reg slot_uop_fp_ctrl_wen; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_wen_0 = slot_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_wen = slot_uop_fp_ctrl_wen; // @[util.scala:104:23] reg slot_uop_fp_ctrl_ren1; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_ren1_0 = slot_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_ren1 = slot_uop_fp_ctrl_ren1; // @[util.scala:104:23] reg slot_uop_fp_ctrl_ren2; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_ren2_0 = slot_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_ren2 = slot_uop_fp_ctrl_ren2; // @[util.scala:104:23] reg slot_uop_fp_ctrl_ren3; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_ren3_0 = slot_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_ren3 = slot_uop_fp_ctrl_ren3; // @[util.scala:104:23] reg slot_uop_fp_ctrl_swap12; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_swap12_0 = slot_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_swap12 = slot_uop_fp_ctrl_swap12; // @[util.scala:104:23] reg slot_uop_fp_ctrl_swap23; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_swap23_0 = slot_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_swap23 = slot_uop_fp_ctrl_swap23; // @[util.scala:104:23] reg [1:0] slot_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_typeTagIn_0 = slot_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_fp_ctrl_typeTagIn = slot_uop_fp_ctrl_typeTagIn; // @[util.scala:104:23] reg [1:0] slot_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_typeTagOut_0 = slot_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_fp_ctrl_typeTagOut = slot_uop_fp_ctrl_typeTagOut; // @[util.scala:104:23] reg slot_uop_fp_ctrl_fromint; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_fromint_0 = slot_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_fromint = slot_uop_fp_ctrl_fromint; // @[util.scala:104:23] reg slot_uop_fp_ctrl_toint; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_toint_0 = slot_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_toint = slot_uop_fp_ctrl_toint; // @[util.scala:104:23] reg slot_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_fastpipe_0 = slot_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_fastpipe = slot_uop_fp_ctrl_fastpipe; // @[util.scala:104:23] reg slot_uop_fp_ctrl_fma; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_fma_0 = slot_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_fma = slot_uop_fp_ctrl_fma; // @[util.scala:104:23] reg slot_uop_fp_ctrl_div; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_div_0 = slot_uop_fp_ctrl_div; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_div = slot_uop_fp_ctrl_div; // @[util.scala:104:23] reg slot_uop_fp_ctrl_sqrt; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_sqrt_0 = slot_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_sqrt = slot_uop_fp_ctrl_sqrt; // @[util.scala:104:23] reg slot_uop_fp_ctrl_wflags; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_wflags_0 = slot_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_wflags = slot_uop_fp_ctrl_wflags; // @[util.scala:104:23] reg slot_uop_fp_ctrl_vec; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_vec_0 = slot_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_vec = slot_uop_fp_ctrl_vec; // @[util.scala:104:23] reg [6:0] slot_uop_rob_idx; // @[issue-slot.scala:56:21] assign io_iss_uop_rob_idx_0 = slot_uop_rob_idx; // @[issue-slot.scala:49:7, :56:21] wire [6:0] next_uop_out_rob_idx = slot_uop_rob_idx; // @[util.scala:104:23] reg [4:0] slot_uop_ldq_idx; // @[issue-slot.scala:56:21] assign io_iss_uop_ldq_idx_0 = slot_uop_ldq_idx; // @[issue-slot.scala:49:7, :56:21] wire [4:0] next_uop_out_ldq_idx = slot_uop_ldq_idx; // @[util.scala:104:23] reg [4:0] slot_uop_stq_idx; // @[issue-slot.scala:56:21] assign io_iss_uop_stq_idx_0 = slot_uop_stq_idx; // @[issue-slot.scala:49:7, :56:21] wire [4:0] next_uop_out_stq_idx = slot_uop_stq_idx; // @[util.scala:104:23] reg [1:0] slot_uop_rxq_idx; // @[issue-slot.scala:56:21] assign io_iss_uop_rxq_idx_0 = slot_uop_rxq_idx; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_rxq_idx = slot_uop_rxq_idx; // @[util.scala:104:23] reg [6:0] slot_uop_pdst; // @[issue-slot.scala:56:21] assign io_iss_uop_pdst_0 = slot_uop_pdst; // @[issue-slot.scala:49:7, :56:21] wire [6:0] next_uop_out_pdst = slot_uop_pdst; // @[util.scala:104:23] reg [6:0] slot_uop_prs1; // @[issue-slot.scala:56:21] assign io_iss_uop_prs1_0 = slot_uop_prs1; // @[issue-slot.scala:49:7, :56:21] wire [6:0] next_uop_out_prs1 = slot_uop_prs1; // @[util.scala:104:23] reg [6:0] slot_uop_prs2; // @[issue-slot.scala:56:21] assign io_iss_uop_prs2_0 = slot_uop_prs2; // @[issue-slot.scala:49:7, :56:21] wire [6:0] next_uop_out_prs2 = slot_uop_prs2; // @[util.scala:104:23] reg [6:0] slot_uop_prs3; // @[issue-slot.scala:56:21] assign io_iss_uop_prs3_0 = slot_uop_prs3; // @[issue-slot.scala:49:7, :56:21] wire [6:0] next_uop_out_prs3 = slot_uop_prs3; // @[util.scala:104:23] reg [4:0] slot_uop_ppred; // @[issue-slot.scala:56:21] assign io_iss_uop_ppred_0 = slot_uop_ppred; // @[issue-slot.scala:49:7, :56:21] wire [4:0] next_uop_out_ppred = slot_uop_ppred; // @[util.scala:104:23] reg slot_uop_prs1_busy; // @[issue-slot.scala:56:21] assign io_iss_uop_prs1_busy_0 = slot_uop_prs1_busy; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_prs1_busy = slot_uop_prs1_busy; // @[util.scala:104:23] reg slot_uop_prs2_busy; // @[issue-slot.scala:56:21] assign io_iss_uop_prs2_busy_0 = slot_uop_prs2_busy; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_prs2_busy = slot_uop_prs2_busy; // @[util.scala:104:23] reg slot_uop_prs3_busy; // @[issue-slot.scala:56:21] assign io_iss_uop_prs3_busy_0 = slot_uop_prs3_busy; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_prs3_busy = slot_uop_prs3_busy; // @[util.scala:104:23] reg slot_uop_ppred_busy; // @[issue-slot.scala:56:21] assign io_iss_uop_ppred_busy_0 = slot_uop_ppred_busy; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_ppred_busy = slot_uop_ppred_busy; // @[util.scala:104:23] wire _iss_ready_T_3 = slot_uop_ppred_busy; // @[issue-slot.scala:56:21, :136:88] wire _agen_ready_T_2 = slot_uop_ppred_busy; // @[issue-slot.scala:56:21, :137:95] wire _dgen_ready_T_2 = slot_uop_ppred_busy; // @[issue-slot.scala:56:21, :138:95] reg [6:0] slot_uop_stale_pdst; // @[issue-slot.scala:56:21] assign io_iss_uop_stale_pdst_0 = slot_uop_stale_pdst; // @[issue-slot.scala:49:7, :56:21] wire [6:0] next_uop_out_stale_pdst = slot_uop_stale_pdst; // @[util.scala:104:23] reg slot_uop_exception; // @[issue-slot.scala:56:21] assign io_iss_uop_exception_0 = slot_uop_exception; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_exception = slot_uop_exception; // @[util.scala:104:23] reg [63:0] slot_uop_exc_cause; // @[issue-slot.scala:56:21] assign io_iss_uop_exc_cause_0 = slot_uop_exc_cause; // @[issue-slot.scala:49:7, :56:21] wire [63:0] next_uop_out_exc_cause = slot_uop_exc_cause; // @[util.scala:104:23] reg [4:0] slot_uop_mem_cmd; // @[issue-slot.scala:56:21] assign io_iss_uop_mem_cmd_0 = slot_uop_mem_cmd; // @[issue-slot.scala:49:7, :56:21] wire [4:0] next_uop_out_mem_cmd = slot_uop_mem_cmd; // @[util.scala:104:23] reg [1:0] slot_uop_mem_size; // @[issue-slot.scala:56:21] assign io_iss_uop_mem_size_0 = slot_uop_mem_size; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_mem_size = slot_uop_mem_size; // @[util.scala:104:23] reg slot_uop_mem_signed; // @[issue-slot.scala:56:21] assign io_iss_uop_mem_signed_0 = slot_uop_mem_signed; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_mem_signed = slot_uop_mem_signed; // @[util.scala:104:23] reg slot_uop_uses_ldq; // @[issue-slot.scala:56:21] assign io_iss_uop_uses_ldq_0 = slot_uop_uses_ldq; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_uses_ldq = slot_uop_uses_ldq; // @[util.scala:104:23] reg slot_uop_uses_stq; // @[issue-slot.scala:56:21] assign io_iss_uop_uses_stq_0 = slot_uop_uses_stq; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_uses_stq = slot_uop_uses_stq; // @[util.scala:104:23] reg slot_uop_is_unique; // @[issue-slot.scala:56:21] assign io_iss_uop_is_unique_0 = slot_uop_is_unique; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_unique = slot_uop_is_unique; // @[util.scala:104:23] reg slot_uop_flush_on_commit; // @[issue-slot.scala:56:21] assign io_iss_uop_flush_on_commit_0 = slot_uop_flush_on_commit; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_flush_on_commit = slot_uop_flush_on_commit; // @[util.scala:104:23] reg [2:0] slot_uop_csr_cmd; // @[issue-slot.scala:56:21] assign io_iss_uop_csr_cmd_0 = slot_uop_csr_cmd; // @[issue-slot.scala:49:7, :56:21] wire [2:0] next_uop_out_csr_cmd = slot_uop_csr_cmd; // @[util.scala:104:23] reg slot_uop_ldst_is_rs1; // @[issue-slot.scala:56:21] assign io_iss_uop_ldst_is_rs1_0 = slot_uop_ldst_is_rs1; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_ldst_is_rs1 = slot_uop_ldst_is_rs1; // @[util.scala:104:23] reg [5:0] slot_uop_ldst; // @[issue-slot.scala:56:21] assign io_iss_uop_ldst_0 = slot_uop_ldst; // @[issue-slot.scala:49:7, :56:21] wire [5:0] next_uop_out_ldst = slot_uop_ldst; // @[util.scala:104:23] reg [5:0] slot_uop_lrs1; // @[issue-slot.scala:56:21] assign io_iss_uop_lrs1_0 = slot_uop_lrs1; // @[issue-slot.scala:49:7, :56:21] wire [5:0] next_uop_out_lrs1 = slot_uop_lrs1; // @[util.scala:104:23] reg [5:0] slot_uop_lrs2; // @[issue-slot.scala:56:21] assign io_iss_uop_lrs2_0 = slot_uop_lrs2; // @[issue-slot.scala:49:7, :56:21] wire [5:0] next_uop_out_lrs2 = slot_uop_lrs2; // @[util.scala:104:23] reg [5:0] slot_uop_lrs3; // @[issue-slot.scala:56:21] assign io_iss_uop_lrs3_0 = slot_uop_lrs3; // @[issue-slot.scala:49:7, :56:21] wire [5:0] next_uop_out_lrs3 = slot_uop_lrs3; // @[util.scala:104:23] reg [1:0] slot_uop_dst_rtype; // @[issue-slot.scala:56:21] assign io_iss_uop_dst_rtype_0 = slot_uop_dst_rtype; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_dst_rtype = slot_uop_dst_rtype; // @[util.scala:104:23] reg [1:0] slot_uop_lrs1_rtype; // @[issue-slot.scala:56:21] assign io_iss_uop_lrs1_rtype_0 = slot_uop_lrs1_rtype; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_lrs1_rtype = slot_uop_lrs1_rtype; // @[util.scala:104:23] reg [1:0] slot_uop_lrs2_rtype; // @[issue-slot.scala:56:21] assign io_iss_uop_lrs2_rtype_0 = slot_uop_lrs2_rtype; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_lrs2_rtype = slot_uop_lrs2_rtype; // @[util.scala:104:23] reg slot_uop_frs3_en; // @[issue-slot.scala:56:21] assign io_iss_uop_frs3_en_0 = slot_uop_frs3_en; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_frs3_en = slot_uop_frs3_en; // @[util.scala:104:23] reg slot_uop_fcn_dw; // @[issue-slot.scala:56:21] assign io_iss_uop_fcn_dw_0 = slot_uop_fcn_dw; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fcn_dw = slot_uop_fcn_dw; // @[util.scala:104:23] reg [4:0] slot_uop_fcn_op; // @[issue-slot.scala:56:21] assign io_iss_uop_fcn_op_0 = slot_uop_fcn_op; // @[issue-slot.scala:49:7, :56:21] wire [4:0] next_uop_out_fcn_op = slot_uop_fcn_op; // @[util.scala:104:23] reg slot_uop_fp_val; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_val_0 = slot_uop_fp_val; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_val = slot_uop_fp_val; // @[util.scala:104:23] reg [2:0] slot_uop_fp_rm; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_rm_0 = slot_uop_fp_rm; // @[issue-slot.scala:49:7, :56:21] wire [2:0] next_uop_out_fp_rm = slot_uop_fp_rm; // @[util.scala:104:23] reg [1:0] slot_uop_fp_typ; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_typ_0 = slot_uop_fp_typ; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_fp_typ = slot_uop_fp_typ; // @[util.scala:104:23] reg slot_uop_xcpt_pf_if; // @[issue-slot.scala:56:21] assign io_iss_uop_xcpt_pf_if_0 = slot_uop_xcpt_pf_if; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_xcpt_pf_if = slot_uop_xcpt_pf_if; // @[util.scala:104:23] reg slot_uop_xcpt_ae_if; // @[issue-slot.scala:56:21] assign io_iss_uop_xcpt_ae_if_0 = slot_uop_xcpt_ae_if; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_xcpt_ae_if = slot_uop_xcpt_ae_if; // @[util.scala:104:23] reg slot_uop_xcpt_ma_if; // @[issue-slot.scala:56:21] assign io_iss_uop_xcpt_ma_if_0 = slot_uop_xcpt_ma_if; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_xcpt_ma_if = slot_uop_xcpt_ma_if; // @[util.scala:104:23] reg slot_uop_bp_debug_if; // @[issue-slot.scala:56:21] assign io_iss_uop_bp_debug_if_0 = slot_uop_bp_debug_if; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_bp_debug_if = slot_uop_bp_debug_if; // @[util.scala:104:23] reg slot_uop_bp_xcpt_if; // @[issue-slot.scala:56:21] assign io_iss_uop_bp_xcpt_if_0 = slot_uop_bp_xcpt_if; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_bp_xcpt_if = slot_uop_bp_xcpt_if; // @[util.scala:104:23] reg [2:0] slot_uop_debug_fsrc; // @[issue-slot.scala:56:21] assign io_iss_uop_debug_fsrc_0 = slot_uop_debug_fsrc; // @[issue-slot.scala:49:7, :56:21] wire [2:0] next_uop_out_debug_fsrc = slot_uop_debug_fsrc; // @[util.scala:104:23] reg [2:0] slot_uop_debug_tsrc; // @[issue-slot.scala:56:21] assign io_iss_uop_debug_tsrc_0 = slot_uop_debug_tsrc; // @[issue-slot.scala:49:7, :56:21] wire [2:0] next_uop_out_debug_tsrc = slot_uop_debug_tsrc; // @[util.scala:104:23] wire next_valid; // @[issue-slot.scala:58:28] assign next_uop_inst = next_uop_out_inst; // @[util.scala:104:23] assign next_uop_debug_inst = next_uop_out_debug_inst; // @[util.scala:104:23] assign next_uop_is_rvc = next_uop_out_is_rvc; // @[util.scala:104:23] assign next_uop_debug_pc = next_uop_out_debug_pc; // @[util.scala:104:23] assign next_uop_iq_type_0 = next_uop_out_iq_type_0; // @[util.scala:104:23] assign next_uop_iq_type_1 = next_uop_out_iq_type_1; // @[util.scala:104:23] assign next_uop_iq_type_2 = next_uop_out_iq_type_2; // @[util.scala:104:23] assign next_uop_iq_type_3 = next_uop_out_iq_type_3; // @[util.scala:104:23] assign next_uop_fu_code_0 = next_uop_out_fu_code_0; // @[util.scala:104:23] assign next_uop_fu_code_1 = next_uop_out_fu_code_1; // @[util.scala:104:23] assign next_uop_fu_code_2 = next_uop_out_fu_code_2; // @[util.scala:104:23] assign next_uop_fu_code_3 = next_uop_out_fu_code_3; // @[util.scala:104:23] assign next_uop_fu_code_4 = next_uop_out_fu_code_4; // @[util.scala:104:23] assign next_uop_fu_code_5 = next_uop_out_fu_code_5; // @[util.scala:104:23] assign next_uop_fu_code_6 = next_uop_out_fu_code_6; // @[util.scala:104:23] assign next_uop_fu_code_7 = next_uop_out_fu_code_7; // @[util.scala:104:23] assign next_uop_fu_code_8 = next_uop_out_fu_code_8; // @[util.scala:104:23] assign next_uop_fu_code_9 = next_uop_out_fu_code_9; // @[util.scala:104:23] wire [15:0] _next_uop_out_br_mask_T_1; // @[util.scala:93:25] assign next_uop_dis_col_sel = next_uop_out_dis_col_sel; // @[util.scala:104:23] assign next_uop_br_mask = next_uop_out_br_mask; // @[util.scala:104:23] assign next_uop_br_tag = next_uop_out_br_tag; // @[util.scala:104:23] assign next_uop_br_type = next_uop_out_br_type; // @[util.scala:104:23] assign next_uop_is_sfb = next_uop_out_is_sfb; // @[util.scala:104:23] assign next_uop_is_fence = next_uop_out_is_fence; // @[util.scala:104:23] assign next_uop_is_fencei = next_uop_out_is_fencei; // @[util.scala:104:23] assign next_uop_is_sfence = next_uop_out_is_sfence; // @[util.scala:104:23] assign next_uop_is_amo = next_uop_out_is_amo; // @[util.scala:104:23] assign next_uop_is_eret = next_uop_out_is_eret; // @[util.scala:104:23] assign next_uop_is_sys_pc2epc = next_uop_out_is_sys_pc2epc; // @[util.scala:104:23] assign next_uop_is_rocc = next_uop_out_is_rocc; // @[util.scala:104:23] assign next_uop_is_mov = next_uop_out_is_mov; // @[util.scala:104:23] assign next_uop_ftq_idx = next_uop_out_ftq_idx; // @[util.scala:104:23] assign next_uop_edge_inst = next_uop_out_edge_inst; // @[util.scala:104:23] assign next_uop_pc_lob = next_uop_out_pc_lob; // @[util.scala:104:23] assign next_uop_taken = next_uop_out_taken; // @[util.scala:104:23] assign next_uop_imm_rename = next_uop_out_imm_rename; // @[util.scala:104:23] assign next_uop_imm_sel = next_uop_out_imm_sel; // @[util.scala:104:23] assign next_uop_pimm = next_uop_out_pimm; // @[util.scala:104:23] assign next_uop_imm_packed = next_uop_out_imm_packed; // @[util.scala:104:23] assign next_uop_op1_sel = next_uop_out_op1_sel; // @[util.scala:104:23] assign next_uop_op2_sel = next_uop_out_op2_sel; // @[util.scala:104:23] assign next_uop_fp_ctrl_ldst = next_uop_out_fp_ctrl_ldst; // @[util.scala:104:23] assign next_uop_fp_ctrl_wen = next_uop_out_fp_ctrl_wen; // @[util.scala:104:23] assign next_uop_fp_ctrl_ren1 = next_uop_out_fp_ctrl_ren1; // @[util.scala:104:23] assign next_uop_fp_ctrl_ren2 = next_uop_out_fp_ctrl_ren2; // @[util.scala:104:23] assign next_uop_fp_ctrl_ren3 = next_uop_out_fp_ctrl_ren3; // @[util.scala:104:23] assign next_uop_fp_ctrl_swap12 = next_uop_out_fp_ctrl_swap12; // @[util.scala:104:23] assign next_uop_fp_ctrl_swap23 = next_uop_out_fp_ctrl_swap23; // @[util.scala:104:23] assign next_uop_fp_ctrl_typeTagIn = next_uop_out_fp_ctrl_typeTagIn; // @[util.scala:104:23] assign next_uop_fp_ctrl_typeTagOut = next_uop_out_fp_ctrl_typeTagOut; // @[util.scala:104:23] assign next_uop_fp_ctrl_fromint = next_uop_out_fp_ctrl_fromint; // @[util.scala:104:23] assign next_uop_fp_ctrl_toint = next_uop_out_fp_ctrl_toint; // @[util.scala:104:23] assign next_uop_fp_ctrl_fastpipe = next_uop_out_fp_ctrl_fastpipe; // @[util.scala:104:23] assign next_uop_fp_ctrl_fma = next_uop_out_fp_ctrl_fma; // @[util.scala:104:23] assign next_uop_fp_ctrl_div = next_uop_out_fp_ctrl_div; // @[util.scala:104:23] assign next_uop_fp_ctrl_sqrt = next_uop_out_fp_ctrl_sqrt; // @[util.scala:104:23] assign next_uop_fp_ctrl_wflags = next_uop_out_fp_ctrl_wflags; // @[util.scala:104:23] assign next_uop_fp_ctrl_vec = next_uop_out_fp_ctrl_vec; // @[util.scala:104:23] assign next_uop_rob_idx = next_uop_out_rob_idx; // @[util.scala:104:23] assign next_uop_ldq_idx = next_uop_out_ldq_idx; // @[util.scala:104:23] assign next_uop_stq_idx = next_uop_out_stq_idx; // @[util.scala:104:23] assign next_uop_rxq_idx = next_uop_out_rxq_idx; // @[util.scala:104:23] assign next_uop_pdst = next_uop_out_pdst; // @[util.scala:104:23] assign next_uop_prs1 = next_uop_out_prs1; // @[util.scala:104:23] assign next_uop_prs2 = next_uop_out_prs2; // @[util.scala:104:23] assign next_uop_prs3 = next_uop_out_prs3; // @[util.scala:104:23] assign next_uop_ppred = next_uop_out_ppred; // @[util.scala:104:23] assign next_uop_stale_pdst = next_uop_out_stale_pdst; // @[util.scala:104:23] assign next_uop_exception = next_uop_out_exception; // @[util.scala:104:23] assign next_uop_exc_cause = next_uop_out_exc_cause; // @[util.scala:104:23] assign next_uop_mem_cmd = next_uop_out_mem_cmd; // @[util.scala:104:23] assign next_uop_mem_size = next_uop_out_mem_size; // @[util.scala:104:23] assign next_uop_mem_signed = next_uop_out_mem_signed; // @[util.scala:104:23] assign next_uop_uses_ldq = next_uop_out_uses_ldq; // @[util.scala:104:23] assign next_uop_uses_stq = next_uop_out_uses_stq; // @[util.scala:104:23] assign next_uop_is_unique = next_uop_out_is_unique; // @[util.scala:104:23] assign next_uop_flush_on_commit = next_uop_out_flush_on_commit; // @[util.scala:104:23] assign next_uop_csr_cmd = next_uop_out_csr_cmd; // @[util.scala:104:23] assign next_uop_ldst_is_rs1 = next_uop_out_ldst_is_rs1; // @[util.scala:104:23] assign next_uop_ldst = next_uop_out_ldst; // @[util.scala:104:23] assign next_uop_lrs1 = next_uop_out_lrs1; // @[util.scala:104:23] assign next_uop_lrs2 = next_uop_out_lrs2; // @[util.scala:104:23] assign next_uop_lrs3 = next_uop_out_lrs3; // @[util.scala:104:23] assign next_uop_dst_rtype = next_uop_out_dst_rtype; // @[util.scala:104:23] assign next_uop_lrs1_rtype = next_uop_out_lrs1_rtype; // @[util.scala:104:23] assign next_uop_lrs2_rtype = next_uop_out_lrs2_rtype; // @[util.scala:104:23] assign next_uop_frs3_en = next_uop_out_frs3_en; // @[util.scala:104:23] assign next_uop_fcn_dw = next_uop_out_fcn_dw; // @[util.scala:104:23] assign next_uop_fcn_op = next_uop_out_fcn_op; // @[util.scala:104:23] assign next_uop_fp_val = next_uop_out_fp_val; // @[util.scala:104:23] assign next_uop_fp_rm = next_uop_out_fp_rm; // @[util.scala:104:23] assign next_uop_fp_typ = next_uop_out_fp_typ; // @[util.scala:104:23] assign next_uop_xcpt_pf_if = next_uop_out_xcpt_pf_if; // @[util.scala:104:23] assign next_uop_xcpt_ae_if = next_uop_out_xcpt_ae_if; // @[util.scala:104:23] assign next_uop_xcpt_ma_if = next_uop_out_xcpt_ma_if; // @[util.scala:104:23] assign next_uop_bp_debug_if = next_uop_out_bp_debug_if; // @[util.scala:104:23] assign next_uop_bp_xcpt_if = next_uop_out_bp_xcpt_if; // @[util.scala:104:23] assign next_uop_debug_fsrc = next_uop_out_debug_fsrc; // @[util.scala:104:23] assign next_uop_debug_tsrc = next_uop_out_debug_tsrc; // @[util.scala:104:23] wire [15:0] _next_uop_out_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:93:27] assign _next_uop_out_br_mask_T_1 = slot_uop_br_mask & _next_uop_out_br_mask_T; // @[util.scala:93:{25,27}] assign next_uop_out_br_mask = _next_uop_out_br_mask_T_1; // @[util.scala:93:25, :104:23] assign io_out_uop_inst_0 = next_uop_inst; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_debug_inst_0 = next_uop_debug_inst; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_rvc_0 = next_uop_is_rvc; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_debug_pc_0 = next_uop_debug_pc; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iq_type_0_0 = next_uop_iq_type_0; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iq_type_1_0 = next_uop_iq_type_1; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iq_type_2_0 = next_uop_iq_type_2; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iq_type_3_0 = next_uop_iq_type_3; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_0_0 = next_uop_fu_code_0; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_1_0 = next_uop_fu_code_1; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_2_0 = next_uop_fu_code_2; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_3_0 = next_uop_fu_code_3; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_4_0 = next_uop_fu_code_4; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_5_0 = next_uop_fu_code_5; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_6_0 = next_uop_fu_code_6; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_7_0 = next_uop_fu_code_7; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_8_0 = next_uop_fu_code_8; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_9_0 = next_uop_fu_code_9; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iw_issued_0 = next_uop_iw_issued; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iw_p1_speculative_child_0 = next_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iw_p2_speculative_child_0 = next_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iw_p1_bypass_hint_0 = next_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iw_p2_bypass_hint_0 = next_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iw_p3_bypass_hint_0 = next_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_dis_col_sel_0 = next_uop_dis_col_sel; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_br_mask_0 = next_uop_br_mask; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_br_tag_0 = next_uop_br_tag; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_br_type_0 = next_uop_br_type; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_sfb_0 = next_uop_is_sfb; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_fence_0 = next_uop_is_fence; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_fencei_0 = next_uop_is_fencei; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_sfence_0 = next_uop_is_sfence; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_amo_0 = next_uop_is_amo; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_eret_0 = next_uop_is_eret; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_sys_pc2epc_0 = next_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_rocc_0 = next_uop_is_rocc; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_mov_0 = next_uop_is_mov; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_ftq_idx_0 = next_uop_ftq_idx; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_edge_inst_0 = next_uop_edge_inst; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_pc_lob_0 = next_uop_pc_lob; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_taken_0 = next_uop_taken; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_imm_rename_0 = next_uop_imm_rename; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_imm_sel_0 = next_uop_imm_sel; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_pimm_0 = next_uop_pimm; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_imm_packed_0 = next_uop_imm_packed; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_op1_sel_0 = next_uop_op1_sel; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_op2_sel_0 = next_uop_op2_sel; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_ldst_0 = next_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_wen_0 = next_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_ren1_0 = next_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_ren2_0 = next_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_ren3_0 = next_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_swap12_0 = next_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_swap23_0 = next_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_typeTagIn_0 = next_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_typeTagOut_0 = next_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_fromint_0 = next_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_toint_0 = next_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_fastpipe_0 = next_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_fma_0 = next_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_div_0 = next_uop_fp_ctrl_div; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_sqrt_0 = next_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_wflags_0 = next_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_vec_0 = next_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_rob_idx_0 = next_uop_rob_idx; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_ldq_idx_0 = next_uop_ldq_idx; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_stq_idx_0 = next_uop_stq_idx; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_rxq_idx_0 = next_uop_rxq_idx; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_pdst_0 = next_uop_pdst; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_prs1_0 = next_uop_prs1; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_prs2_0 = next_uop_prs2; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_prs3_0 = next_uop_prs3; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_ppred_0 = next_uop_ppred; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_prs1_busy_0 = next_uop_prs1_busy; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_prs2_busy_0 = next_uop_prs2_busy; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_prs3_busy_0 = next_uop_prs3_busy; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_ppred_busy_0 = next_uop_ppred_busy; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_stale_pdst_0 = next_uop_stale_pdst; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_exception_0 = next_uop_exception; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_exc_cause_0 = next_uop_exc_cause; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_mem_cmd_0 = next_uop_mem_cmd; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_mem_size_0 = next_uop_mem_size; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_mem_signed_0 = next_uop_mem_signed; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_uses_ldq_0 = next_uop_uses_ldq; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_uses_stq_0 = next_uop_uses_stq; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_unique_0 = next_uop_is_unique; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_flush_on_commit_0 = next_uop_flush_on_commit; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_csr_cmd_0 = next_uop_csr_cmd; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_ldst_is_rs1_0 = next_uop_ldst_is_rs1; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_ldst_0 = next_uop_ldst; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_lrs1_0 = next_uop_lrs1; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_lrs2_0 = next_uop_lrs2; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_lrs3_0 = next_uop_lrs3; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_dst_rtype_0 = next_uop_dst_rtype; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_lrs1_rtype_0 = next_uop_lrs1_rtype; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_lrs2_rtype_0 = next_uop_lrs2_rtype; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_frs3_en_0 = next_uop_frs3_en; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fcn_dw_0 = next_uop_fcn_dw; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fcn_op_0 = next_uop_fcn_op; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_val_0 = next_uop_fp_val; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_rm_0 = next_uop_fp_rm; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_typ_0 = next_uop_fp_typ; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_xcpt_pf_if_0 = next_uop_xcpt_pf_if; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_xcpt_ae_if_0 = next_uop_xcpt_ae_if; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_xcpt_ma_if_0 = next_uop_xcpt_ma_if; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_bp_debug_if_0 = next_uop_bp_debug_if; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_bp_xcpt_if_0 = next_uop_bp_xcpt_if; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_debug_fsrc_0 = next_uop_debug_fsrc; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_debug_tsrc_0 = next_uop_debug_tsrc; // @[issue-slot.scala:49:7, :59:28] wire [15:0] _killed_T = io_brupdate_b1_mispredict_mask_0 & slot_uop_br_mask; // @[util.scala:126:51] wire _killed_T_1 = |_killed_T; // @[util.scala:126:{51,59}] wire killed = _killed_T_1 | io_kill_0; // @[util.scala:61:61, :126:59] wire _io_will_be_valid_T = ~killed; // @[util.scala:61:61] assign _io_will_be_valid_T_1 = next_valid & _io_will_be_valid_T; // @[issue-slot.scala:58:28, :65:{34,37}] assign io_will_be_valid_0 = _io_will_be_valid_T_1; // @[issue-slot.scala:49:7, :65:34] wire _slot_valid_T = ~killed; // @[util.scala:61:61] wire _slot_valid_T_1 = next_valid & _slot_valid_T; // @[issue-slot.scala:58:28, :74:{30,33}]

Generate the Verilog code corresponding to the following Chisel files. File Transposer.scala: package gemmini import chisel3._ import chisel3.util._ import Util._ trait Transposer[T <: Data] extends Module { def dim: Int def dataType: T val io = IO(new Bundle { val inRow = Flipped(Decoupled(Vec(dim, dataType))) val outCol = Decoupled(Vec(dim, dataType)) }) } class PipelinedTransposer[T <: Data](val dim: Int, val dataType: T) extends Transposer[T] { require(isPow2(dim)) val regArray = Seq.fill(dim, dim)(Reg(dataType)) val regArrayT = regArray.transpose val sMoveUp :: sMoveLeft :: Nil = Enum(2) val state = RegInit(sMoveUp) val leftCounter = RegInit(0.U(log2Ceil(dim+1).W)) //(io.inRow.fire && state === sMoveLeft, dim+1) val upCounter = RegInit(0.U(log2Ceil(dim+1).W)) //Counter(io.inRow.fire && state === sMoveUp, dim+1) io.outCol.valid := 0.U io.inRow.ready := 0.U switch(state) { is(sMoveUp) { io.inRow.ready := upCounter <= dim.U io.outCol.valid := leftCounter > 0.U when(io.inRow.fire) { upCounter := upCounter + 1.U } when(upCounter === (dim-1).U) { state := sMoveLeft leftCounter := 0.U } when(io.outCol.fire) { leftCounter := leftCounter - 1.U } } is(sMoveLeft) { io.inRow.ready := leftCounter <= dim.U // TODO: this is naive io.outCol.valid := upCounter > 0.U when(leftCounter === (dim-1).U) { state := sMoveUp } when(io.inRow.fire) { leftCounter := leftCounter + 1.U upCounter := 0.U } when(io.outCol.fire) { upCounter := upCounter - 1.U } } } // Propagate input from bottom row to top row systolically in the move up phase // TODO: need to iterate over columns to connect Chisel values of type T // Should be able to operate directly on the Vec, but Seq and Vec don't mix (try Array?) for (colIdx <- 0 until dim) { regArray.foldRight(io.inRow.bits(colIdx)) { case (regRow, prevReg) => when (state === sMoveUp) { regRow(colIdx) := prevReg } regRow(colIdx) } } // Propagate input from right side to left side systolically in the move left phase for (rowIdx <- 0 until dim) { regArrayT.foldRight(io.inRow.bits(rowIdx)) { case (regCol, prevReg) => when (state === sMoveLeft) { regCol(rowIdx) := prevReg } regCol(rowIdx) } } // Pull from the left side or the top side based on the state for (idx <- 0 until dim) { when (state === sMoveUp) { io.outCol.bits(idx) := regArray(0)(idx) }.elsewhen(state === sMoveLeft) { io.outCol.bits(idx) := regArrayT(0)(idx) }.otherwise { io.outCol.bits(idx) := DontCare } } } class AlwaysOutTransposer[T <: Data](val dim: Int, val dataType: T) extends Transposer[T] { require(isPow2(dim)) val LEFT_DIR = 0.U(1.W) val UP_DIR = 1.U(1.W) class PE extends Module { val io = IO(new Bundle { val inR = Input(dataType) val inD = Input(dataType) val outL = Output(dataType) val outU = Output(dataType) val dir = Input(UInt(1.W)) val en = Input(Bool()) }) val reg = RegEnable(Mux(io.dir === LEFT_DIR, io.inR, io.inD), io.en) io.outU := reg io.outL := reg } val pes = Seq.fill(dim,dim)(Module(new PE)) val counter = RegInit(0.U((log2Ceil(dim) max 1).W)) // TODO replace this with a standard Chisel counter val dir = RegInit(LEFT_DIR) // Wire up horizontal signals for (row <- 0 until dim; col <- 0 until dim) { val right_in = if (col == dim-1) io.inRow.bits(row) else pes(row)(col+1).io.outL pes(row)(col).io.inR := right_in } // Wire up vertical signals for (row <- 0 until dim; col <- 0 until dim) { val down_in = if (row == dim-1) io.inRow.bits(col) else pes(row+1)(col).io.outU pes(row)(col).io.inD := down_in } // Wire up global signals pes.flatten.foreach(_.io.dir := dir) pes.flatten.foreach(_.io.en := io.inRow.fire) io.outCol.valid := true.B io.inRow.ready := true.B val left_out = VecInit(pes.transpose.head.map(_.io.outL)) val up_out = VecInit(pes.head.map(_.io.outU)) io.outCol.bits := Mux(dir === LEFT_DIR, left_out, up_out) when (io.inRow.fire) { counter := wrappingAdd(counter, 1.U, dim) } when (counter === (dim-1).U && io.inRow.fire) { dir := ~dir } } class NaiveTransposer[T <: Data](val dim: Int, val dataType: T) extends Transposer[T] { val regArray = Seq.fill(dim, dim)(Reg(dataType)) val regArrayT = regArray.transpose // state = 0 => filling regArray row-wise, state = 1 => draining regArray column-wise val state = RegInit(0.U(1.W)) val countInc = io.inRow.fire || io.outCol.fire val (countValue, countWrap) = Counter(countInc, dim) io.inRow.ready := state === 0.U io.outCol.valid := state === 1.U for (i <- 0 until dim) { for (j <- 0 until dim) { when(countValue === i.U && io.inRow.fire) { regArray(i)(j) := io.inRow.bits(j) } } } for (i <- 0 until dim) { io.outCol.bits(i) := 0.U for (j <- 0 until dim) { when(countValue === j.U) { io.outCol.bits(i) := regArrayT(j)(i) } } } when (io.inRow.fire && countWrap) { state := 1.U } when (io.outCol.fire && countWrap) { state := 0.U } assert(!(state === 0.U) || !io.outCol.fire) assert(!(state === 1.U) || !io.inRow.fire) }

module PE_154( // @[Transposer.scala:100:9] input clock, // @[Transposer.scala:100:9] input reset, // @[Transposer.scala:100:9] input [7:0] io_inR, // @[Transposer.scala:101:16] input [7:0] io_inD, // @[Transposer.scala:101:16] output [7:0] io_outL, // @[Transposer.scala:101:16] output [7:0] io_outU, // @[Transposer.scala:101:16] input io_dir, // @[Transposer.scala:101:16] input io_en // @[Transposer.scala:101:16] ); wire [7:0] io_inR_0 = io_inR; // @[Transposer.scala:100:9] wire [7:0] io_inD_0 = io_inD; // @[Transposer.scala:100:9] wire io_dir_0 = io_dir; // @[Transposer.scala:100:9] wire io_en_0 = io_en; // @[Transposer.scala:100:9] wire [7:0] io_outL_0; // @[Transposer.scala:100:9] wire [7:0] io_outU_0; // @[Transposer.scala:100:9] wire _reg_T = ~io_dir_0; // @[Transposer.scala:100:9, :110:36] wire [7:0] _reg_T_1 = _reg_T ? io_inR_0 : io_inD_0; // @[Transposer.scala:100:9, :110:{28,36}] reg [7:0] reg_0; // @[Transposer.scala:110:24] assign io_outL_0 = reg_0; // @[Transposer.scala:100:9, :110:24] assign io_outU_0 = reg_0; // @[Transposer.scala:100:9, :110:24] always @(posedge clock) begin // @[Transposer.scala:100:9] if (io_en_0) // @[Transposer.scala:100:9] reg_0 <= _reg_T_1; // @[Transposer.scala:110:{24,28}] always @(posedge) assign io_outL = io_outL_0; // @[Transposer.scala:100:9] assign io_outU = io_outU_0; // @[Transposer.scala:100:9] endmodule

Generate the Verilog code corresponding to the following Chisel files. File Monitor.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceLine import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import freechips.rocketchip.diplomacy.EnableMonitors import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode} import freechips.rocketchip.util.PlusArg case class TLMonitorArgs(edge: TLEdge) abstract class TLMonitorBase(args: TLMonitorArgs) extends Module { val io = IO(new Bundle { val in = Input(new TLBundle(args.edge.bundle)) }) def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit legalize(io.in, args.edge, reset) } object TLMonitor { def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = { if (enable) { EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) } } else { node } } } class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args) { require (args.edge.params(TLMonitorStrictMode) || (! args.edge.params(TestplanTestType).formal)) val cover_prop_class = PropertyClass.Default //Like assert but can flip to being an assumption for formal verification def monAssert(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir, cond, message, PropertyClass.Default) } def assume(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir.flip, cond, message, PropertyClass.Default) } def extra = { args.edge.sourceInfo match { case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)" case _ => "" } } def visible(address: UInt, source: UInt, edge: TLEdge) = edge.client.clients.map { c => !c.sourceId.contains(source) || c.visibility.map(_.contains(address)).reduce(_ || _) }.reduce(_ && _) def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = { //switch this flag to turn on diplomacy in error messages def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n" monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra) // Reuse these subexpressions to save some firrtl lines val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility") //The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B //TODO: check for acquireT? when (bundle.opcode === TLMessages.AcquireBlock) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra) } when (bundle.opcode === TLMessages.AcquirePerm) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra) monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra) monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra) monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra) } } def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = { monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra) monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility") // Reuse these subexpressions to save some firrtl lines val address_ok = edge.manager.containsSafe(edge.address(bundle)) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source when (bundle.opcode === TLMessages.Probe) { assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra) assume (address_ok, "'B' channel Probe carries unmanaged address" + extra) assume (legal_source, "'B' channel Probe carries source that is not first source" + extra) assume (is_aligned, "'B' channel Probe address not aligned to size" + extra) assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra) assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra) assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra) monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra) monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra) monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra) monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra) } } def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = { monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val address_ok = edge.manager.containsSafe(edge.address(bundle)) monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility") when (bundle.opcode === TLMessages.ProbeAck) { monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra) } when (bundle.opcode === TLMessages.ProbeAckData) { monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.Release) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra) monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra) } when (bundle.opcode === TLMessages.ReleaseData) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.AccessAck) { monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra) } when (bundle.opcode === TLMessages.HintAck) { monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra) } } def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = { assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val sink_ok = bundle.sink < edge.manager.endSinkId.U val deny_put_ok = edge.manager.mayDenyPut.B val deny_get_ok = edge.manager.mayDenyGet.B when (bundle.opcode === TLMessages.ReleaseAck) { assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra) assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra) assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra) } when (bundle.opcode === TLMessages.Grant) { assume (source_ok, "'D' channel Grant carries invalid source ID" + extra) assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra) assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel Grant is denied" + extra) } when (bundle.opcode === TLMessages.GrantData) { assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra) assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra) assume (!bundle.denied || bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra) assume (deny_get_ok || !bundle.denied, "'D' channel GrantData is denied" + extra) } when (bundle.opcode === TLMessages.AccessAck) { assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel AccessAck is denied" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra) assume (!bundle.denied || bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra) assume (deny_get_ok || !bundle.denied, "'D' channel AccessAckData is denied" + extra) } when (bundle.opcode === TLMessages.HintAck) { assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel HintAck is denied" + extra) } } def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = { val sink_ok = bundle.sink < edge.manager.endSinkId.U monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra) } def legalizeFormat(bundle: TLBundle, edge: TLEdge) = { when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) } when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) } when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) } when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) } } else { monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra) monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra) monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra) } } def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = { val a_first = edge.first(a.bits, a.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (a.valid && !a_first) { monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra) monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra) monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra) monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra) monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra) } when (a.fire && a_first) { opcode := a.bits.opcode param := a.bits.param size := a.bits.size source := a.bits.source address := a.bits.address } } def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = { val b_first = edge.first(b.bits, b.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (b.valid && !b_first) { monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra) monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra) monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra) monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra) monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra) } when (b.fire && b_first) { opcode := b.bits.opcode param := b.bits.param size := b.bits.size source := b.bits.source address := b.bits.address } } def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = { // Symbolic variable val sym_source = Wire(UInt(edge.client.endSourceId.W)) // TODO: Connect sym_source to a fixed value for simulation and to a // free wire in formal sym_source := 0.U // Type casting Int to UInt val maxSourceId = Wire(UInt(edge.client.endSourceId.W)) maxSourceId := edge.client.endSourceId.U // Delayed verison of sym_source val sym_source_d = Reg(UInt(edge.client.endSourceId.W)) sym_source_d := sym_source // These will be constraints for FV setup Property( MonitorDirection.Monitor, (sym_source === sym_source_d), "sym_source should remain stable", PropertyClass.Default) Property( MonitorDirection.Monitor, (sym_source <= maxSourceId), "sym_source should take legal value", PropertyClass.Default) val my_resp_pend = RegInit(false.B) val my_opcode = Reg(UInt()) val my_size = Reg(UInt()) val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire) val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire) val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source) val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source) val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat) val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend) when (my_set_resp_pend) { my_resp_pend := true.B } .elsewhen (my_clr_resp_pend) { my_resp_pend := false.B } when (my_a_first_beat) { my_opcode := bundle.a.bits.opcode my_size := bundle.a.bits.size } val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size) val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode) val my_resp_opcode_legal = Wire(Bool()) when ((my_resp_opcode === TLMessages.Get) || (my_resp_opcode === TLMessages.ArithmeticData) || (my_resp_opcode === TLMessages.LogicalData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData) } .elsewhen ((my_resp_opcode === TLMessages.PutFullData) || (my_resp_opcode === TLMessages.PutPartialData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck) } .otherwise { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck) } monAssert (IfThen(my_resp_pend, !my_a_first_beat), "Request message should not be sent with a source ID, for which a response message" + "is already pending (not received until current cycle) for a prior request message" + "with the same source ID" + extra) assume (IfThen(my_clr_resp_pend, (my_set_resp_pend || my_resp_pend)), "Response message should be accepted with a source ID only if a request message with the" + "same source ID has been accepted or is being accepted in the current cycle" + extra) assume (IfThen(my_d_first_beat, (my_a_first_beat || my_resp_pend)), "Response message should be sent with a source ID only if a request message with the" + "same source ID has been accepted or is being sent in the current cycle" + extra) assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)), "If d_valid is 1, then d_size should be same as a_size of the corresponding request" + "message" + extra) assume (IfThen(my_d_first_beat, my_resp_opcode_legal), "If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" + "request message" + extra) } def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = { val c_first = edge.first(c.bits, c.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (c.valid && !c_first) { monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra) monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra) monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra) monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra) monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra) } when (c.fire && c_first) { opcode := c.bits.opcode param := c.bits.param size := c.bits.size source := c.bits.source address := c.bits.address } } def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = { val d_first = edge.first(d.bits, d.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val sink = Reg(UInt()) val denied = Reg(Bool()) when (d.valid && !d_first) { assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra) assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra) assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra) assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra) assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra) assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra) } when (d.fire && d_first) { opcode := d.bits.opcode param := d.bits.param size := d.bits.size source := d.bits.source sink := d.bits.sink denied := d.bits.denied } } def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = { legalizeMultibeatA(bundle.a, edge) legalizeMultibeatD(bundle.d, edge) if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { legalizeMultibeatB(bundle.b, edge) legalizeMultibeatC(bundle.c, edge) } } //This is left in for almond which doesn't adhere to the tilelink protocol @deprecated("Use legalizeADSource instead if possible","") def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.client.endSourceId.W)) val a_first = edge.first(bundle.a.bits, bundle.a.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val a_set = WireInit(0.U(edge.client.endSourceId.W)) when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) assume((a_set | inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra) } if (edge.manager.minLatency > 0) { assume(a_set =/= d_clr || !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight | a_set) & ~d_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") assert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = { val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size) val log_a_size_bus_size = log2Ceil(a_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error inflight.suggestName("inflight") val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) inflight_opcodes.suggestName("inflight_opcodes") val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) inflight_sizes.suggestName("inflight_sizes") val a_first = edge.first(bundle.a.bits, bundle.a.fire) a_first.suggestName("a_first") val d_first = edge.first(bundle.d.bits, bundle.d.fire) d_first.suggestName("d_first") val a_set = WireInit(0.U(edge.client.endSourceId.W)) val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) a_set.suggestName("a_set") a_set_wo_ready.suggestName("a_set_wo_ready") val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) a_opcodes_set.suggestName("a_opcodes_set") val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) a_sizes_set.suggestName("a_sizes_set") val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W)) a_opcode_lookup.suggestName("a_opcode_lookup") a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W)) a_size_lookup.suggestName("a_size_lookup") a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant)) val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant)) val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W)) a_opcodes_set_interm.suggestName("a_opcodes_set_interm") val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W)) a_sizes_set_interm.suggestName("a_sizes_set_interm") when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) { a_set_wo_ready := UIntToOH(bundle.a.bits.source) } when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) | 1.U a_sizes_set_interm := (bundle.a.bits.size << 1.U) | 1.U a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U) a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U) monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) d_opcodes_clr.suggestName("d_opcodes_clr") val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) || (bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra) assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) || (bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra) assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) { assume((!bundle.d.ready) || bundle.a.ready, "ready check") } if (edge.manager.minLatency > 0) { assume(a_set_wo_ready =/= d_clr_wo_ready || !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight | a_set) & ~d_clr inflight_opcodes := (inflight_opcodes | a_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes | a_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = { val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size) val log_c_size_bus_size = log2Ceil(c_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) inflight.suggestName("inflight") inflight_opcodes.suggestName("inflight_opcodes") inflight_sizes.suggestName("inflight_sizes") val c_first = edge.first(bundle.c.bits, bundle.c.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) c_first.suggestName("c_first") d_first.suggestName("d_first") val c_set = WireInit(0.U(edge.client.endSourceId.W)) val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) c_set.suggestName("c_set") c_set_wo_ready.suggestName("c_set_wo_ready") c_opcodes_set.suggestName("c_opcodes_set") c_sizes_set.suggestName("c_sizes_set") val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W)) val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W)) c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U c_opcode_lookup.suggestName("c_opcode_lookup") c_size_lookup.suggestName("c_size_lookup") val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W)) val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W)) c_opcodes_set_interm.suggestName("c_opcodes_set_interm") c_sizes_set_interm.suggestName("c_sizes_set_interm") when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) { c_set_wo_ready := UIntToOH(bundle.c.bits.source) } when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) { c_set := UIntToOH(bundle.c.bits.source) c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) | 1.U c_sizes_set_interm := (bundle.c.bits.size << 1.U) | 1.U c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U) c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U) monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra) } val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck || bundle.c.bits.opcode === TLMessages.ProbeAckData val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") d_opcodes_clr.suggestName("d_opcodes_clr") d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) { assume((!bundle.d.ready) || bundle.c.ready, "ready check") } if (edge.manager.minLatency > 0) { when (c_set_wo_ready.orR) { assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra) } } inflight := (inflight | c_set) & ~d_clr inflight_opcodes := (inflight_opcodes | c_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes | c_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.c.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.manager.endSinkId.W)) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val e_first = true.B val d_set = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) { d_set := UIntToOH(bundle.d.bits.sink) assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra) } val e_clr = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) { e_clr := UIntToOH(bundle.e.bits.sink) monAssert((d_set | inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra) } // edge.client.minLatency applies to BC, not DE inflight := (inflight | d_set) & ~e_clr } def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = { val sourceBits = log2Ceil(edge.client.endSourceId) val tooBig = 14 // >16kB worth of flight information gets to be too much if (sourceBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked") } else { if (args.edge.params(TestplanTestType).simulation) { if (args.edge.params(TLMonitorStrictMode)) { legalizeADSource(bundle, edge) legalizeCDSource(bundle, edge) } else { legalizeADSourceOld(bundle, edge) } } if (args.edge.params(TestplanTestType).formal) { legalizeADSourceFormal(bundle, edge) } } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { // legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize... val sinkBits = log2Ceil(edge.manager.endSinkId) if (sinkBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked") } else { legalizeDESink(bundle, edge) } } } def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = { legalizeFormat (bundle, edge) legalizeMultibeat (bundle, edge) legalizeUnique (bundle, edge) } } File Misc.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import scala.math._ class ParameterizedBundle(implicit p: Parameters) extends Bundle trait Clocked extends Bundle { val clock = Clock() val reset = Bool() } object DecoupledHelper { def apply(rvs: Bool*) = new DecoupledHelper(rvs) } class DecoupledHelper(val rvs: Seq[Bool]) { def fire(exclude: Bool, includes: Bool*) = { require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!") (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _) } def fire() = { rvs.reduce(_ && _) } } object MuxT { def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2)) def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3)) def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4)) } /** Creates a cascade of n MuxTs to search for a key value. */ object MuxTLookup { def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } } object ValidMux { def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]*): ValidIO[T] = { apply(v1 +: v2.toSeq) } def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = { val out = Wire(Valid(valids.head.bits.cloneType)) out.valid := valids.map(_.valid).reduce(_ || _) out.bits := MuxCase(valids.head.bits, valids.map(v => (v.valid -> v.bits))) out } } object Str { def apply(s: String): UInt = { var i = BigInt(0) require(s.forall(validChar _)) for (c <- s) i = (i << 8) | c i.U((s.length*8).W) } def apply(x: Char): UInt = { require(validChar(x)) x.U(8.W) } def apply(x: UInt): UInt = apply(x, 10) def apply(x: UInt, radix: Int): UInt = { val rad = radix.U val w = x.getWidth require(w > 0) var q = x var s = digit(q % rad) for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s) } s } def apply(x: SInt): UInt = apply(x, 10) def apply(x: SInt, radix: Int): UInt = { val neg = x < 0.S val abs = x.abs.asUInt if (radix != 10) { Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix)) } else { val rad = radix.U val w = abs.getWidth require(w > 0) var q = abs var s = digit(q % rad) var needSign = neg for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad val placeSpace = q === 0.U val space = Mux(needSign, Str('-'), Str(' ')) needSign = needSign && !placeSpace s = Cat(Mux(placeSpace, space, digit(q % rad)), s) } Cat(Mux(needSign, Str('-'), Str(' ')), s) } } private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0) private def validChar(x: Char) = x == (x & 0xFF) } object Split { def apply(x: UInt, n0: Int) = { val w = x.getWidth (x.extract(w-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n2: Int, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } } object Random { def apply(mod: Int, random: UInt): UInt = { if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0) else PriorityEncoder(partition(apply(1 << log2Up(mod*8), random), mod)) } def apply(mod: Int): UInt = apply(mod, randomizer) def oneHot(mod: Int, random: UInt): UInt = { if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0)) else PriorityEncoderOH(partition(apply(1 << log2Up(mod*8), random), mod)).asUInt } def oneHot(mod: Int): UInt = oneHot(mod, randomizer) private def randomizer = LFSR(16) private def partition(value: UInt, slices: Int) = Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U) } object Majority { def apply(in: Set[Bool]): Bool = { val n = (in.size >> 1) + 1 val clauses = in.subsets(n).map(_.reduce(_ && _)) clauses.reduce(_ || _) } def apply(in: Seq[Bool]): Bool = apply(in.toSet) def apply(in: UInt): Bool = apply(in.asBools.toSet) } object PopCountAtLeast { private def two(x: UInt): (Bool, Bool) = x.getWidth match { case 1 => (x.asBool, false.B) case n => val half = x.getWidth / 2 val (leftOne, leftTwo) = two(x(half - 1, 0)) val (rightOne, rightTwo) = two(x(x.getWidth - 1, half)) (leftOne || rightOne, leftTwo || rightTwo || (leftOne && rightOne)) } def apply(x: UInt, n: Int): Bool = n match { case 0 => true.B case 1 => x.orR case 2 => two(x)._2 case 3 => PopCount(x) >= n.U } } // This gets used everywhere, so make the smallest circuit possible ... // Given an address and size, create a mask of beatBytes size // eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111 // groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01 object MaskGen { def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = { require (groupBy >= 1 && beatBytes >= groupBy) require (isPow2(beatBytes) && isPow2(groupBy)) val lgBytes = log2Ceil(beatBytes) val sizeOH = UIntToOH(lgSize | 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) | (groupBy*2 - 1).U def helper(i: Int): Seq[(Bool, Bool)] = { if (i == 0) { Seq((lgSize >= lgBytes.asUInt, true.B)) } else { val sub = helper(i-1) val size = sizeOH(lgBytes - i) val bit = addr_lo(lgBytes - i) val nbit = !bit Seq.tabulate (1 << i) { j => val (sub_acc, sub_eq) = sub(j/2) val eq = sub_eq && (if (j % 2 == 1) bit else nbit) val acc = sub_acc || (size && eq) (acc, eq) } } } if (groupBy == beatBytes) 1.U else Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse) } } File PlusArg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.experimental._ import chisel3.util.HasBlackBoxResource @deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05") case class PlusArgInfo(default: BigInt, docstring: String) /** Case class for PlusArg information * * @tparam A scala type of the PlusArg value * @param default optional default value * @param docstring text to include in the help * @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT) */ private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String) /** Typeclass for converting a type to a doctype string * @tparam A some type */ trait Doctypeable[A] { /** Return the doctype string for some option */ def toDoctype(a: Option[A]): String } /** Object containing implementations of the Doctypeable typeclass */ object Doctypes { /** Converts an Int => "INT" */ implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" } /** Converts a BigInt => "INT" */ implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" } /** Converts a String => "STRING" */ implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" } } class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map( "FORMAT" -> StringParam(format), "DEFAULT" -> IntParam(default), "WIDTH" -> IntParam(width) )) with HasBlackBoxResource { val io = IO(new Bundle { val out = Output(UInt(width.W)) }) addResource("/vsrc/plusarg_reader.v") } /* This wrapper class has no outputs, making it clear it is a simulation-only construct */ class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module { val io = IO(new Bundle { val count = Input(UInt(width.W)) }) val max = Module(new plusarg_reader(format, default, docstring, width)).io.out when (max > 0.U) { assert (io.count < max, s"Timeout exceeded: $docstring") } } import Doctypes._ object PlusArg { /** PlusArg("foo") will return 42.U if the simulation is run with +foo=42 * Do not use this as an initial register value. The value is set in an * initial block and thus accessing it from another initial is racey. * Add a docstring to document the arg, which can be dumped in an elaboration * pass. */ def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out } /** PlusArg.timeout(name, default, docstring)(count) will use chisel.assert * to kill the simulation when count exceeds the specified integer argument. * Default 0 will never assert. */ def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count } } object PlusArgArtefacts { private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty /* Add a new PlusArg */ @deprecated( "Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05" ) def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring) /** Add a new PlusArg * * @tparam A scala type of the PlusArg value * @param name name for the PlusArg * @param default optional default value * @param docstring text to include in the help */ def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit = artefacts = artefacts ++ Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default))) /* From plus args, generate help text */ private def serializeHelp_cHeader(tab: String = ""): String = artefacts .map{ case(arg, info) => s"""|$tab+$arg=${info.doctype}\\n\\ |$tab${" "*20}${info.docstring}\\n\\ |""".stripMargin ++ info.default.map{ case default => s"$tab${" "*22}(default=${default})\\n\\\n"}.getOrElse("") }.toSeq.mkString("\\n\\\n") ++ "\"" /* From plus args, generate a char array of their names */ private def serializeArray_cHeader(tab: String = ""): String = { val prettyTab = tab + " " * 44 // Length of 'static const ...' s"${tab}static const char * verilog_plusargs [] = {\\\n" ++ artefacts .map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" } .mkString("")++ s"${prettyTab}0};" } /* Generate C code to be included in emulator.cc that helps with * argument parsing based on available Verilog PlusArgs */ def serialize_cHeader(): String = s"""|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\ |${serializeHelp_cHeader(" "*7)} |${serializeArray_cHeader()} |""".stripMargin } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /** Like Vec.apply(idx), but tolerates indices of mismatched width */ def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /** Any Data subtype that has a Bool member named valid. */ type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /** converts from camel case to to underscores, also removing all spaces */ def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /** converts spaces or underscores to hyphens, also lowering case */ def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y | (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y || y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /** Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation */ def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Bundles.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import freechips.rocketchip.util._ import scala.collection.immutable.ListMap import chisel3.util.Decoupled import chisel3.util.DecoupledIO import chisel3.reflect.DataMirror abstract class TLBundleBase(val params: TLBundleParameters) extends Bundle // common combos in lazy policy: // Put + Acquire // Release + AccessAck object TLMessages { // A B C D E def PutFullData = 0.U // . . => AccessAck def PutPartialData = 1.U // . . => AccessAck def ArithmeticData = 2.U // . . => AccessAckData def LogicalData = 3.U // . . => AccessAckData def Get = 4.U // . . => AccessAckData def Hint = 5.U // . . => HintAck def AcquireBlock = 6.U // . => Grant[Data] def AcquirePerm = 7.U // . => Grant[Data] def Probe = 6.U // . => ProbeAck[Data] def AccessAck = 0.U // . . def AccessAckData = 1.U // . . def HintAck = 2.U // . . def ProbeAck = 4.U // . def ProbeAckData = 5.U // . def Release = 6.U // . => ReleaseAck def ReleaseData = 7.U // . => ReleaseAck def Grant = 4.U // . => GrantAck def GrantData = 5.U // . => GrantAck def ReleaseAck = 6.U // . def GrantAck = 0.U // . def isA(x: UInt) = x <= AcquirePerm def isB(x: UInt) = x <= Probe def isC(x: UInt) = x <= ReleaseData def isD(x: UInt) = x <= ReleaseAck def adResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, Grant, Grant) def bcResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, ProbeAck, ProbeAck) def a = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("AcquireBlock",TLPermissions.PermMsgGrow), ("AcquirePerm",TLPermissions.PermMsgGrow)) def b = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("Probe",TLPermissions.PermMsgCap)) def c = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("ProbeAck",TLPermissions.PermMsgReport), ("ProbeAckData",TLPermissions.PermMsgReport), ("Release",TLPermissions.PermMsgReport), ("ReleaseData",TLPermissions.PermMsgReport)) def d = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("Grant",TLPermissions.PermMsgCap), ("GrantData",TLPermissions.PermMsgCap), ("ReleaseAck",TLPermissions.PermMsgReserved)) } /** * The three primary TileLink permissions are: * (T)runk: the agent is (or is on inwards path to) the global point of serialization. * (B)ranch: the agent is on an outwards path to * (N)one: * These permissions are permuted by transfer operations in various ways. * Operations can cap permissions, request for them to be grown or shrunk, * or for a report on their current status. */ object TLPermissions { val aWidth = 2 val bdWidth = 2 val cWidth = 3 // Cap types (Grant = new permissions, Probe = permisions <= target) def toT = 0.U(bdWidth.W) def toB = 1.U(bdWidth.W) def toN = 2.U(bdWidth.W) def isCap(x: UInt) = x <= toN // Grow types (Acquire = permissions >= target) def NtoB = 0.U(aWidth.W) def NtoT = 1.U(aWidth.W) def BtoT = 2.U(aWidth.W) def isGrow(x: UInt) = x <= BtoT // Shrink types (ProbeAck, Release) def TtoB = 0.U(cWidth.W) def TtoN = 1.U(cWidth.W) def BtoN = 2.U(cWidth.W) def isShrink(x: UInt) = x <= BtoN // Report types (ProbeAck, Release) def TtoT = 3.U(cWidth.W) def BtoB = 4.U(cWidth.W) def NtoN = 5.U(cWidth.W) def isReport(x: UInt) = x <= NtoN def PermMsgGrow:Seq[String] = Seq("Grow NtoB", "Grow NtoT", "Grow BtoT") def PermMsgCap:Seq[String] = Seq("Cap toT", "Cap toB", "Cap toN") def PermMsgReport:Seq[String] = Seq("Shrink TtoB", "Shrink TtoN", "Shrink BtoN", "Report TotT", "Report BtoB", "Report NtoN") def PermMsgReserved:Seq[String] = Seq("Reserved") } object TLAtomics { val width = 3 // Arithmetic types def MIN = 0.U(width.W) def MAX = 1.U(width.W) def MINU = 2.U(width.W) def MAXU = 3.U(width.W) def ADD = 4.U(width.W) def isArithmetic(x: UInt) = x <= ADD // Logical types def XOR = 0.U(width.W) def OR = 1.U(width.W) def AND = 2.U(width.W) def SWAP = 3.U(width.W) def isLogical(x: UInt) = x <= SWAP def ArithMsg:Seq[String] = Seq("MIN", "MAX", "MINU", "MAXU", "ADD") def LogicMsg:Seq[String] = Seq("XOR", "OR", "AND", "SWAP") } object TLHints { val width = 1 def PREFETCH_READ = 0.U(width.W) def PREFETCH_WRITE = 1.U(width.W) def isHints(x: UInt) = x <= PREFETCH_WRITE def HintsMsg:Seq[String] = Seq("PrefetchRead", "PrefetchWrite") } sealed trait TLChannel extends TLBundleBase { val channelName: String } sealed trait TLDataChannel extends TLChannel sealed trait TLAddrChannel extends TLDataChannel final class TLBundleA(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleA_${params.shortName}" val channelName = "'A' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(List(TLAtomics.width, TLPermissions.aWidth, TLHints.width).max.W) // amo_opcode || grow perms || hint val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleB(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleB_${params.shortName}" val channelName = "'B' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val address = UInt(params.addressBits.W) // from // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleC(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleC_${params.shortName}" val channelName = "'C' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.cWidth.W) // shrink or report perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleD(params: TLBundleParameters) extends TLBundleBase(params) with TLDataChannel { override def typeName = s"TLBundleD_${params.shortName}" val channelName = "'D' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val sink = UInt(params.sinkBits.W) // from val denied = Bool() // implies corrupt iff *Data val user = BundleMap(params.responseFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleE(params: TLBundleParameters) extends TLBundleBase(params) with TLChannel { override def typeName = s"TLBundleE_${params.shortName}" val channelName = "'E' channel" val sink = UInt(params.sinkBits.W) // to } class TLBundle(val params: TLBundleParameters) extends Record { // Emulate a Bundle with elements abcde or ad depending on params.hasBCE private val optA = Some (Decoupled(new TLBundleA(params))) private val optB = params.hasBCE.option(Flipped(Decoupled(new TLBundleB(params)))) private val optC = params.hasBCE.option(Decoupled(new TLBundleC(params))) private val optD = Some (Flipped(Decoupled(new TLBundleD(params)))) private val optE = params.hasBCE.option(Decoupled(new TLBundleE(params))) def a: DecoupledIO[TLBundleA] = optA.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleA(params))))) def b: DecoupledIO[TLBundleB] = optB.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleB(params))))) def c: DecoupledIO[TLBundleC] = optC.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleC(params))))) def d: DecoupledIO[TLBundleD] = optD.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleD(params))))) def e: DecoupledIO[TLBundleE] = optE.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleE(params))))) val elements = if (params.hasBCE) ListMap("e" -> e, "d" -> d, "c" -> c, "b" -> b, "a" -> a) else ListMap("d" -> d, "a" -> a) def tieoff(): Unit = { DataMirror.specifiedDirectionOf(a.ready) match { case SpecifiedDirection.Input => a.ready := false.B c.ready := false.B e.ready := false.B b.valid := false.B d.valid := false.B case SpecifiedDirection.Output => a.valid := false.B c.valid := false.B e.valid := false.B b.ready := false.B d.ready := false.B case _ => } } } object TLBundle { def apply(params: TLBundleParameters) = new TLBundle(params) } class TLAsyncBundleBase(val params: TLAsyncBundleParameters) extends Bundle class TLAsyncBundle(params: TLAsyncBundleParameters) extends TLAsyncBundleBase(params) { val a = new AsyncBundle(new TLBundleA(params.base), params.async) val b = Flipped(new AsyncBundle(new TLBundleB(params.base), params.async)) val c = new AsyncBundle(new TLBundleC(params.base), params.async) val d = Flipped(new AsyncBundle(new TLBundleD(params.base), params.async)) val e = new AsyncBundle(new TLBundleE(params.base), params.async) } class TLRationalBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = RationalIO(new TLBundleA(params)) val b = Flipped(RationalIO(new TLBundleB(params))) val c = RationalIO(new TLBundleC(params)) val d = Flipped(RationalIO(new TLBundleD(params))) val e = RationalIO(new TLBundleE(params)) } class TLCreditedBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = CreditedIO(new TLBundleA(params)) val b = Flipped(CreditedIO(new TLBundleB(params))) val c = CreditedIO(new TLBundleC(params)) val d = Flipped(CreditedIO(new TLBundleD(params))) val e = CreditedIO(new TLBundleE(params)) } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.diplomacy import chisel3._ import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor} import freechips.rocketchip.util.ShiftQueue /** Options for describing the attributes of memory regions */ object RegionType { // Define the 'more relaxed than' ordering val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS) sealed trait T extends Ordered[T] { def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this) } case object CACHED extends T // an intermediate agent may have cached a copy of the region for you case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively } // A non-empty half-open range; [start, end) case class IdRange(start: Int, end: Int) extends Ordered[IdRange] { require (start >= 0, s"Ids cannot be negative, but got: $start.") require (start <= end, "Id ranges cannot be negative.") def compare(x: IdRange) = { val primary = (this.start - x.start).signum val secondary = (x.end - this.end).signum if (primary != 0) primary else secondary } def overlaps(x: IdRange) = start < x.end && x.start < end def contains(x: IdRange) = start <= x.start && x.end <= end def contains(x: Int) = start <= x && x < end def contains(x: UInt) = if (size == 0) { false.B } else if (size == 1) { // simple comparison x === start.U } else { // find index of largest different bit val largestDeltaBit = log2Floor(start ^ (end-1)) val smallestCommonBit = largestDeltaBit + 1 // may not exist in x val uncommonMask = (1 << smallestCommonBit) - 1 val uncommonBits = (x | 0.U(smallestCommonBit.W))(largestDeltaBit, 0) // the prefix must match exactly (note: may shift ALL bits away) (x >> smallestCommonBit) === (start >> smallestCommonBit).U && // firrtl constant prop range analysis can eliminate these two: (start & uncommonMask).U <= uncommonBits && uncommonBits <= ((end-1) & uncommonMask).U } def shift(x: Int) = IdRange(start+x, end+x) def size = end - start def isEmpty = end == start def range = start until end } object IdRange { def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else { val ranges = s.sorted (ranges.tail zip ranges.init) find { case (a, b) => a overlaps b } } } // An potentially empty inclusive range of 2-powers [min, max] (in bytes) case class TransferSizes(min: Int, max: Int) { def this(x: Int) = this(x, x) require (min <= max, s"Min transfer $min > max transfer $max") require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)") require (max == 0 || isPow2(max), s"TransferSizes must be a power of 2, got: $max") require (min == 0 || isPow2(min), s"TransferSizes must be a power of 2, got: $min") require (max == 0 || min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)") def none = min == 0 def contains(x: Int) = isPow2(x) && min <= x && x <= max def containsLg(x: Int) = contains(1 << x) def containsLg(x: UInt) = if (none) false.B else if (min == max) { log2Ceil(min).U === x } else { log2Ceil(min).U <= x && x <= log2Ceil(max).U } def contains(x: TransferSizes) = x.none || (min <= x.min && x.max <= max) def intersect(x: TransferSizes) = if (x.max < min || max < x.min) TransferSizes.none else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max)) // Not a union, because the result may contain sizes contained by neither term // NOT TO BE CONFUSED WITH COVERPOINTS def mincover(x: TransferSizes) = { if (none) { x } else if (x.none) { this } else { TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max)) } } override def toString() = "TransferSizes[%d, %d]".format(min, max) } object TransferSizes { def apply(x: Int) = new TransferSizes(x) val none = new TransferSizes(0) def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _) def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _) implicit def asBool(x: TransferSizes) = !x.none } // AddressSets specify the address space managed by the manager // Base is the base address, and mask are the bits consumed by the manager // e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff // e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ... case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet] { // Forbid misaligned base address (and empty sets) require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}") require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous // We do allow negative mask (=> ignore all high bits) def contains(x: BigInt) = ((x ^ base) & ~mask) == 0 def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S // turn x into an address contained in this set def legalize(x: UInt): UInt = base.U | (mask.U & x) // overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1) def overlaps(x: AddressSet) = (~(mask | x.mask) & (base ^ x.base)) == 0 // contains iff bitwise: x.mask => mask && contains(x.base) def contains(x: AddressSet) = ((x.mask | (base ^ x.base)) & ~mask) == 0 // The number of bytes to which the manager must be aligned def alignment = ((mask + 1) & ~mask) // Is this a contiguous memory range def contiguous = alignment == mask+1 def finite = mask >= 0 def max = { require (finite, "Max cannot be calculated on infinite mask"); base | mask } // Widen the match function to ignore all bits in imask def widen(imask: BigInt) = AddressSet(base & ~imask, mask | imask) // Return an AddressSet that only contains the addresses both sets contain def intersect(x: AddressSet): Option[AddressSet] = { if (!overlaps(x)) { None } else { val r_mask = mask & x.mask val r_base = base | x.base Some(AddressSet(r_base, r_mask)) } } def subtract(x: AddressSet): Seq[AddressSet] = { intersect(x) match { case None => Seq(this) case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit => val nmask = (mask & (bit-1)) | remove.mask val nbase = (remove.base ^ bit) & ~nmask AddressSet(nbase, nmask) } } } // AddressSets have one natural Ordering (the containment order, if contiguous) def compare(x: AddressSet) = { val primary = (this.base - x.base).signum // smallest address first val secondary = (x.mask - this.mask).signum // largest mask first if (primary != 0) primary else secondary } // We always want to see things in hex override def toString() = { if (mask >= 0) { "AddressSet(0x%x, 0x%x)".format(base, mask) } else { "AddressSet(0x%x, ~0x%x)".format(base, ~mask) } } def toRanges = { require (finite, "Ranges cannot be calculated on infinite mask") val size = alignment val fragments = mask & ~(size-1) val bits = bitIndexes(fragments) (BigInt(0) until (BigInt(1) << bits.size)).map { i => val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) } AddressRange(off, size) } } } object AddressSet { val everything = AddressSet(0, -1) def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = { if (size == 0) tail.reverse else { val maxBaseAlignment = base & (-base) // 0 for infinite (LSB) val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size val step = if (maxBaseAlignment == 0 || maxBaseAlignment > maxSizeAlignment) maxSizeAlignment else maxBaseAlignment misaligned(base+step, size-step, AddressSet(base, step-1) +: tail) } } def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = { // Pair terms up by ignoring 'bit' seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) => if (seq.size == 1) { seq.head // singleton -> unaffected } else { key.copy(mask = key.mask | bit) // pair - widen mask by bit } }.toList } def unify(seq: Seq[AddressSet]): Seq[AddressSet] = { val bits = seq.map(_.base).foldLeft(BigInt(0))(_ | _) AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted } def enumerateMask(mask: BigInt): Seq[BigInt] = { def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] = if (id == mask) (id +: tail).reverse else helper(((~mask | id) + 1) & mask, id +: tail) helper(0, Nil) } def enumerateBits(mask: BigInt): Seq[BigInt] = { def helper(x: BigInt): Seq[BigInt] = { if (x == 0) { Nil } else { val bit = x & (-x) bit +: helper(x & ~bit) } } helper(mask) } } case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean) { require (depth >= 0, "Buffer depth must be >= 0") def isDefined = depth > 0 def latency = if (isDefined && !flow) 1 else 0 def apply[T <: Data](x: DecoupledIO[T]) = if (isDefined) Queue(x, depth, flow=flow, pipe=pipe) else x def irrevocable[T <: Data](x: ReadyValidIO[T]) = if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe) else x def sq[T <: Data](x: DecoupledIO[T]) = if (!isDefined) x else { val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe)) sq.io.enq <> x sq.io.deq } override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "") } object BufferParams { implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false) val default = BufferParams(2) val none = BufferParams(0) val flow = BufferParams(1, true, false) val pipe = BufferParams(1, false, true) } case class TriStateValue(value: Boolean, set: Boolean) { def update(orig: Boolean) = if (set) value else orig } object TriStateValue { implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true) def unset = TriStateValue(false, false) } trait DirectedBuffers[T] { def copyIn(x: BufferParams): T def copyOut(x: BufferParams): T def copyInOut(x: BufferParams): T } trait IdMapEntry { def name: String def from: IdRange def to: IdRange def isCache: Boolean def requestFifo: Boolean def maxTransactionsInFlight: Option[Int] def pretty(fmt: String) = if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5 fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } else { fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } } abstract class IdMap[T <: IdMapEntry] { protected val fmt: String val mapping: Seq[T] def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n") } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) || !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.ProbeAckData || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode | small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U || beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }

module TLMonitor_64( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [8:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [20:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [8:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [8:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [20:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [8:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_sink = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_denied = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire sink_ok = 1'h0; // @[Monitor.scala:309:31] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] c_first_beats1_decode = 3'h0; // @[Edges.scala:220:59] wire [2:0] c_first_beats1 = 3'h0; // @[Edges.scala:221:14] wire [2:0] _c_first_count_T = 3'h0; // @[Edges.scala:234:27] wire [2:0] c_first_count = 3'h0; // @[Edges.scala:234:25] wire [2:0] _c_first_counter_T = 3'h0; // @[Edges.scala:236:21] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_size = 3'h0; // @[Bundles.scala:265:61] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_5 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_11 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_15 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_17 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_21 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_23 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_27 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_29 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_33 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_35 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_53 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_55 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_59 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_61 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_65 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_67 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_71 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_73 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_77 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_79 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_83 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_85 = 1'h1; // @[Parameters.scala:57:20] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire [2:0] c_first_counter1 = 3'h7; // @[Edges.scala:230:28] wire [3:0] _c_first_counter1_T = 4'hF; // @[Edges.scala:230:28] wire [1:0] io_in_d_bits_param = 2'h0; // @[Monitor.scala:36:7] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [20:0] _c_first_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_first_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_first_WIRE_2_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_first_WIRE_3_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_set_wo_ready_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_set_wo_ready_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_set_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_set_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_opcodes_set_interm_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_opcodes_set_interm_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_sizes_set_interm_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_sizes_set_interm_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_opcodes_set_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_opcodes_set_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_sizes_set_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_sizes_set_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_probe_ack_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_probe_ack_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_probe_ack_WIRE_2_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_probe_ack_WIRE_3_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _same_cycle_resp_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _same_cycle_resp_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _same_cycle_resp_WIRE_2_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _same_cycle_resp_WIRE_3_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _same_cycle_resp_WIRE_4_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _same_cycle_resp_WIRE_5_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [8:0] _c_first_WIRE_bits_source = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _c_first_WIRE_1_bits_source = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _c_first_WIRE_2_bits_source = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _c_first_WIRE_3_bits_source = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _c_set_wo_ready_WIRE_bits_source = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _c_set_wo_ready_WIRE_1_bits_source = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _c_set_WIRE_bits_source = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _c_set_WIRE_1_bits_source = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _c_opcodes_set_interm_WIRE_bits_source = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _c_opcodes_set_interm_WIRE_1_bits_source = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _c_sizes_set_interm_WIRE_bits_source = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _c_sizes_set_interm_WIRE_1_bits_source = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _c_opcodes_set_WIRE_bits_source = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _c_opcodes_set_WIRE_1_bits_source = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _c_sizes_set_WIRE_bits_source = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _c_sizes_set_WIRE_1_bits_source = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _c_probe_ack_WIRE_bits_source = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _c_probe_ack_WIRE_1_bits_source = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _c_probe_ack_WIRE_2_bits_source = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _c_probe_ack_WIRE_3_bits_source = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _same_cycle_resp_WIRE_bits_source = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _same_cycle_resp_WIRE_1_bits_source = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _same_cycle_resp_WIRE_2_bits_source = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _same_cycle_resp_WIRE_3_bits_source = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _same_cycle_resp_WIRE_4_bits_source = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _same_cycle_resp_WIRE_5_bits_source = 9'h0; // @[Bundles.scala:265:61] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [4098:0] _c_opcodes_set_T_1 = 4099'h0; // @[Monitor.scala:767:54] wire [4098:0] _c_sizes_set_T_1 = 4099'h0; // @[Monitor.scala:768:52] wire [11:0] _c_opcodes_set_T = 12'h0; // @[Monitor.scala:767:79] wire [11:0] _c_sizes_set_T = 12'h0; // @[Monitor.scala:768:77] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [3:0] _c_sizes_set_interm_T_1 = 4'h1; // @[Monitor.scala:766:59] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] c_sizes_set_interm = 4'h0; // @[Monitor.scala:755:40] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_sizes_set_interm_T = 4'h0; // @[Monitor.scala:766:51] wire [511:0] _c_set_wo_ready_T = 512'h1; // @[OneHot.scala:58:35] wire [511:0] _c_set_T = 512'h1; // @[OneHot.scala:58:35] wire [1027:0] c_opcodes_set = 1028'h0; // @[Monitor.scala:740:34] wire [1027:0] c_sizes_set = 1028'h0; // @[Monitor.scala:741:34] wire [256:0] c_set = 257'h0; // @[Monitor.scala:738:34] wire [256:0] c_set_wo_ready = 257'h0; // @[Monitor.scala:739:34] wire [5:0] _c_first_beats1_decode_T_2 = 6'h0; // @[package.scala:243:46] wire [5:0] _c_first_beats1_decode_T_1 = 6'h3F; // @[package.scala:243:76] wire [12:0] _c_first_beats1_decode_T = 13'h3F; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48] wire [2:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire [8:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _source_ok_uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _source_ok_uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _source_ok_uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _source_ok_uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _source_ok_uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_11 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_12 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_13 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_14 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_15 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_16 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_17 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_18 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_19 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_20 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_21 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_22 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_23 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_24 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_25 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_26 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_27 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_28 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_29 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_30 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_31 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_32 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_33 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_34 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_35 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_36 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_37 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_38 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_39 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_40 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_41 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_42 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_43 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_44 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_45 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_46 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_47 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_48 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_49 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_50 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_51 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_52 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_53 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_54 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_55 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_56 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_57 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_58 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_59 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_60 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_61 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_62 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_63 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_64 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_65 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _source_ok_uncommonBits_T_6 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _source_ok_uncommonBits_T_7 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _source_ok_uncommonBits_T_8 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _source_ok_uncommonBits_T_9 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _source_ok_uncommonBits_T_10 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _source_ok_uncommonBits_T_11 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire _source_ok_T = io_in_a_bits_source_0 == 9'h90; // @[Monitor.scala:36:7] wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [6:0] _source_ok_T_1 = io_in_a_bits_source_0[8:2]; // @[Monitor.scala:36:7] wire [6:0] _source_ok_T_7 = io_in_a_bits_source_0[8:2]; // @[Monitor.scala:36:7] wire [6:0] _source_ok_T_13 = io_in_a_bits_source_0[8:2]; // @[Monitor.scala:36:7] wire [6:0] _source_ok_T_19 = io_in_a_bits_source_0[8:2]; // @[Monitor.scala:36:7] wire _source_ok_T_2 = _source_ok_T_1 == 7'h20; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_4 = _source_ok_T_2; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_6 = _source_ok_T_4; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1 = _source_ok_T_6; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_8 = _source_ok_T_7 == 7'h21; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_10 = _source_ok_T_8; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_12 = _source_ok_T_10; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_2 = _source_ok_T_12; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_14 = _source_ok_T_13 == 7'h22; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_16 = _source_ok_T_14; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_18 = _source_ok_T_16; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_3 = _source_ok_T_18; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_3 = _source_ok_uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_20 = _source_ok_T_19 == 7'h23; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_22 = _source_ok_T_20; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_24 = _source_ok_T_22; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_4 = _source_ok_T_24; // @[Parameters.scala:1138:31] wire [5:0] source_ok_uncommonBits_4 = _source_ok_uncommonBits_T_4[5:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] _source_ok_T_25 = io_in_a_bits_source_0[8:6]; // @[Monitor.scala:36:7] wire [2:0] _source_ok_T_31 = io_in_a_bits_source_0[8:6]; // @[Monitor.scala:36:7] wire _source_ok_T_26 = _source_ok_T_25 == 3'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_28 = _source_ok_T_26; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_30 = _source_ok_T_28; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_5 = _source_ok_T_30; // @[Parameters.scala:1138:31] wire [5:0] source_ok_uncommonBits_5 = _source_ok_uncommonBits_T_5[5:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_32 = _source_ok_T_31 == 3'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_34 = _source_ok_T_32; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_36 = _source_ok_T_34; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_6 = _source_ok_T_36; // @[Parameters.scala:1138:31] wire _source_ok_T_37 = io_in_a_bits_source_0 == 9'hA0; // @[Monitor.scala:36:7] wire _source_ok_WIRE_7 = _source_ok_T_37; // @[Parameters.scala:1138:31] wire _source_ok_T_38 = io_in_a_bits_source_0 == 9'hA1; // @[Monitor.scala:36:7] wire _source_ok_WIRE_8 = _source_ok_T_38; // @[Parameters.scala:1138:31] wire _source_ok_T_39 = io_in_a_bits_source_0 == 9'hA2; // @[Monitor.scala:36:7] wire _source_ok_WIRE_9 = _source_ok_T_39; // @[Parameters.scala:1138:31] wire _source_ok_T_40 = io_in_a_bits_source_0 == 9'h100; // @[Monitor.scala:36:7] wire _source_ok_WIRE_10 = _source_ok_T_40; // @[Parameters.scala:1138:31] wire _source_ok_T_41 = _source_ok_WIRE_0 | _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_42 = _source_ok_T_41 | _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_43 = _source_ok_T_42 | _source_ok_WIRE_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_44 = _source_ok_T_43 | _source_ok_WIRE_4; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_45 = _source_ok_T_44 | _source_ok_WIRE_5; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_46 = _source_ok_T_45 | _source_ok_WIRE_6; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_47 = _source_ok_T_46 | _source_ok_WIRE_7; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_48 = _source_ok_T_47 | _source_ok_WIRE_8; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_49 = _source_ok_T_48 | _source_ok_WIRE_9; // @[Parameters.scala:1138:31, :1139:46] wire source_ok = _source_ok_T_49 | _source_ok_WIRE_10; // @[Parameters.scala:1138:31, :1139:46] wire [12:0] _GEN = 13'h3F << io_in_a_bits_size_0; // @[package.scala:243:71] wire [12:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [12:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [12:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [5:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [20:0] _is_aligned_T = {15'h0, io_in_a_bits_address_0[5:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 21'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 3'h2; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [1:0] uncommonBits = _uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_1 = _uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_2 = _uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_3 = _uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire [5:0] uncommonBits_4 = _uncommonBits_T_4[5:0]; // @[Parameters.scala:52:{29,56}] wire [5:0] uncommonBits_5 = _uncommonBits_T_5[5:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_6 = _uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_7 = _uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_8 = _uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_9 = _uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}] wire [5:0] uncommonBits_10 = _uncommonBits_T_10[5:0]; // @[Parameters.scala:52:{29,56}] wire [5:0] uncommonBits_11 = _uncommonBits_T_11[5:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_12 = _uncommonBits_T_12[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_13 = _uncommonBits_T_13[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_14 = _uncommonBits_T_14[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_15 = _uncommonBits_T_15[1:0]; // @[Parameters.scala:52:{29,56}] wire [5:0] uncommonBits_16 = _uncommonBits_T_16[5:0]; // @[Parameters.scala:52:{29,56}] wire [5:0] uncommonBits_17 = _uncommonBits_T_17[5:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_18 = _uncommonBits_T_18[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_19 = _uncommonBits_T_19[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_20 = _uncommonBits_T_20[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_21 = _uncommonBits_T_21[1:0]; // @[Parameters.scala:52:{29,56}] wire [5:0] uncommonBits_22 = _uncommonBits_T_22[5:0]; // @[Parameters.scala:52:{29,56}] wire [5:0] uncommonBits_23 = _uncommonBits_T_23[5:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_24 = _uncommonBits_T_24[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_25 = _uncommonBits_T_25[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_26 = _uncommonBits_T_26[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_27 = _uncommonBits_T_27[1:0]; // @[Parameters.scala:52:{29,56}] wire [5:0] uncommonBits_28 = _uncommonBits_T_28[5:0]; // @[Parameters.scala:52:{29,56}] wire [5:0] uncommonBits_29 = _uncommonBits_T_29[5:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_30 = _uncommonBits_T_30[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_31 = _uncommonBits_T_31[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_32 = _uncommonBits_T_32[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_33 = _uncommonBits_T_33[1:0]; // @[Parameters.scala:52:{29,56}] wire [5:0] uncommonBits_34 = _uncommonBits_T_34[5:0]; // @[Parameters.scala:52:{29,56}] wire [5:0] uncommonBits_35 = _uncommonBits_T_35[5:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_36 = _uncommonBits_T_36[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_37 = _uncommonBits_T_37[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_38 = _uncommonBits_T_38[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_39 = _uncommonBits_T_39[1:0]; // @[Parameters.scala:52:{29,56}] wire [5:0] uncommonBits_40 = _uncommonBits_T_40[5:0]; // @[Parameters.scala:52:{29,56}] wire [5:0] uncommonBits_41 = _uncommonBits_T_41[5:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_42 = _uncommonBits_T_42[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_43 = _uncommonBits_T_43[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_44 = _uncommonBits_T_44[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_45 = _uncommonBits_T_45[1:0]; // @[Parameters.scala:52:{29,56}] wire [5:0] uncommonBits_46 = _uncommonBits_T_46[5:0]; // @[Parameters.scala:52:{29,56}] wire [5:0] uncommonBits_47 = _uncommonBits_T_47[5:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_48 = _uncommonBits_T_48[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_49 = _uncommonBits_T_49[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_50 = _uncommonBits_T_50[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_51 = _uncommonBits_T_51[1:0]; // @[Parameters.scala:52:{29,56}] wire [5:0] uncommonBits_52 = _uncommonBits_T_52[5:0]; // @[Parameters.scala:52:{29,56}] wire [5:0] uncommonBits_53 = _uncommonBits_T_53[5:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_54 = _uncommonBits_T_54[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_55 = _uncommonBits_T_55[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_56 = _uncommonBits_T_56[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_57 = _uncommonBits_T_57[1:0]; // @[Parameters.scala:52:{29,56}] wire [5:0] uncommonBits_58 = _uncommonBits_T_58[5:0]; // @[Parameters.scala:52:{29,56}] wire [5:0] uncommonBits_59 = _uncommonBits_T_59[5:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_60 = _uncommonBits_T_60[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_61 = _uncommonBits_T_61[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_62 = _uncommonBits_T_62[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_63 = _uncommonBits_T_63[1:0]; // @[Parameters.scala:52:{29,56}] wire [5:0] uncommonBits_64 = _uncommonBits_T_64[5:0]; // @[Parameters.scala:52:{29,56}] wire [5:0] uncommonBits_65 = _uncommonBits_T_65[5:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_50 = io_in_d_bits_source_0 == 9'h90; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_0 = _source_ok_T_50; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_6 = _source_ok_uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}] wire [6:0] _source_ok_T_51 = io_in_d_bits_source_0[8:2]; // @[Monitor.scala:36:7] wire [6:0] _source_ok_T_57 = io_in_d_bits_source_0[8:2]; // @[Monitor.scala:36:7] wire [6:0] _source_ok_T_63 = io_in_d_bits_source_0[8:2]; // @[Monitor.scala:36:7] wire [6:0] _source_ok_T_69 = io_in_d_bits_source_0[8:2]; // @[Monitor.scala:36:7] wire _source_ok_T_52 = _source_ok_T_51 == 7'h20; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_54 = _source_ok_T_52; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_56 = _source_ok_T_54; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_1 = _source_ok_T_56; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_7 = _source_ok_uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_58 = _source_ok_T_57 == 7'h21; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_60 = _source_ok_T_58; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_62 = _source_ok_T_60; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_2 = _source_ok_T_62; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_8 = _source_ok_uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_64 = _source_ok_T_63 == 7'h22; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_66 = _source_ok_T_64; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_68 = _source_ok_T_66; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_3 = _source_ok_T_68; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_9 = _source_ok_uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_70 = _source_ok_T_69 == 7'h23; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_72 = _source_ok_T_70; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_74 = _source_ok_T_72; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_4 = _source_ok_T_74; // @[Parameters.scala:1138:31] wire [5:0] source_ok_uncommonBits_10 = _source_ok_uncommonBits_T_10[5:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] _source_ok_T_75 = io_in_d_bits_source_0[8:6]; // @[Monitor.scala:36:7] wire [2:0] _source_ok_T_81 = io_in_d_bits_source_0[8:6]; // @[Monitor.scala:36:7] wire _source_ok_T_76 = _source_ok_T_75 == 3'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_78 = _source_ok_T_76; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_80 = _source_ok_T_78; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_5 = _source_ok_T_80; // @[Parameters.scala:1138:31] wire [5:0] source_ok_uncommonBits_11 = _source_ok_uncommonBits_T_11[5:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_82 = _source_ok_T_81 == 3'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_84 = _source_ok_T_82; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_86 = _source_ok_T_84; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_6 = _source_ok_T_86; // @[Parameters.scala:1138:31] wire _source_ok_T_87 = io_in_d_bits_source_0 == 9'hA0; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_7 = _source_ok_T_87; // @[Parameters.scala:1138:31] wire _source_ok_T_88 = io_in_d_bits_source_0 == 9'hA1; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_8 = _source_ok_T_88; // @[Parameters.scala:1138:31] wire _source_ok_T_89 = io_in_d_bits_source_0 == 9'hA2; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_9 = _source_ok_T_89; // @[Parameters.scala:1138:31] wire _source_ok_T_90 = io_in_d_bits_source_0 == 9'h100; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_10 = _source_ok_T_90; // @[Parameters.scala:1138:31] wire _source_ok_T_91 = _source_ok_WIRE_1_0 | _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_92 = _source_ok_T_91 | _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_93 = _source_ok_T_92 | _source_ok_WIRE_1_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_94 = _source_ok_T_93 | _source_ok_WIRE_1_4; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_95 = _source_ok_T_94 | _source_ok_WIRE_1_5; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_96 = _source_ok_T_95 | _source_ok_WIRE_1_6; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_97 = _source_ok_T_96 | _source_ok_WIRE_1_7; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_98 = _source_ok_T_97 | _source_ok_WIRE_1_8; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_99 = _source_ok_T_98 | _source_ok_WIRE_1_9; // @[Parameters.scala:1138:31, :1139:46] wire source_ok_1 = _source_ok_T_99 | _source_ok_WIRE_1_10; // @[Parameters.scala:1138:31, :1139:46] wire _T_1266 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_1266; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_1266; // @[Decoupled.scala:51:35] wire [5:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [2:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [2:0] a_first_counter; // @[Edges.scala:229:27] wire [3:0] _a_first_counter1_T = {1'h0, a_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] a_first_counter1 = _a_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [2:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [2:0] size; // @[Monitor.scala:389:22] reg [8:0] source; // @[Monitor.scala:390:22] reg [20:0] address; // @[Monitor.scala:391:22] wire _T_1334 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_1334; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_1334; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_1334; // @[Decoupled.scala:51:35] wire [12:0] _GEN_0 = 13'h3F << io_in_d_bits_size_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [2:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T = {1'h0, d_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1 = _d_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [2:0] size_1; // @[Monitor.scala:540:22] reg [8:0] source_1; // @[Monitor.scala:541:22] reg [256:0] inflight; // @[Monitor.scala:614:27] reg [1027:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [1027:0] inflight_sizes; // @[Monitor.scala:618:33] wire [5:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [2:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [2:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [2:0] a_first_counter_1; // @[Edges.scala:229:27] wire [3:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] a_first_counter1_1 = _a_first_counter1_T_1[2:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [2:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [5:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46] wire [2:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter_1; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1_1 = _d_first_counter1_T_1[2:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [256:0] a_set; // @[Monitor.scala:626:34] wire [256:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [1027:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [1027:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [11:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [11:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [11:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :641:65] wire [11:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [11:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :681:99] wire [11:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [11:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :750:67] wire [11:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [11:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :791:99] wire [1027:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [1027:0] _a_opcode_lookup_T_6 = {1024'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [1027:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[1027:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [3:0] a_size_lookup; // @[Monitor.scala:639:33] wire [1027:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [1027:0] _a_size_lookup_T_6 = {1024'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}] wire [1027:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[1027:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [3:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [511:0] _GEN_2 = 512'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [511:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_2; // @[OneHot.scala:58:35] wire [511:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_2; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[256:0] : 257'h0; // @[OneHot.scala:58:35] wire _T_1199 = _T_1266 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_1199 ? _a_set_T[256:0] : 257'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_1199 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [3:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [3:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_1199 ? _a_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [11:0] _GEN_3 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [11:0] _a_opcodes_set_T; // @[Monitor.scala:659:79] assign _a_opcodes_set_T = _GEN_3; // @[Monitor.scala:659:79] wire [11:0] _a_sizes_set_T; // @[Monitor.scala:660:77] assign _a_sizes_set_T = _GEN_3; // @[Monitor.scala:659:79, :660:77] wire [4098:0] _a_opcodes_set_T_1 = {4095'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_1199 ? _a_opcodes_set_T_1[1027:0] : 1028'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [4098:0] _a_sizes_set_T_1 = {4095'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_1199 ? _a_sizes_set_T_1[1027:0] : 1028'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [256:0] d_clr; // @[Monitor.scala:664:34] wire [256:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [1027:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [1027:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46] wire _T_1245 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [511:0] _GEN_5 = 512'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [511:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35] wire [511:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35] wire [511:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35] wire [511:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_1245 & ~d_release_ack ? _d_clr_wo_ready_T[256:0] : 257'h0; // @[OneHot.scala:58:35] wire _T_1214 = _T_1334 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_1214 ? _d_clr_T[256:0] : 257'h0; // @[OneHot.scala:58:35] wire [4110:0] _d_opcodes_clr_T_5 = 4111'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_1214 ? _d_opcodes_clr_T_5[1027:0] : 1028'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [4110:0] _d_sizes_clr_T_5 = 4111'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_1214 ? _d_sizes_clr_T_5[1027:0] : 1028'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [256:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [256:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [256:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [1027:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [1027:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [1027:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [1027:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [1027:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [1027:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [256:0] inflight_1; // @[Monitor.scala:726:35] wire [256:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [1027:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [1027:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [1027:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [1027:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire [5:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[5:3]; // @[package.scala:243:46] wire [2:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter_2; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1_2 = _d_first_counter1_T_2[2:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [3:0] c_size_lookup; // @[Monitor.scala:748:35] wire [1027:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [1027:0] _c_opcode_lookup_T_6 = {1024'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [1027:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[1027:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [1027:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [1027:0] _c_size_lookup_T_6 = {1024'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}] wire [1027:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[1027:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [256:0] d_clr_1; // @[Monitor.scala:774:34] wire [256:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [1027:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [1027:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_1310 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_1310 & d_release_ack_1 ? _d_clr_wo_ready_T_1[256:0] : 257'h0; // @[OneHot.scala:58:35] wire _T_1292 = _T_1334 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_1292 ? _d_clr_T_1[256:0] : 257'h0; // @[OneHot.scala:58:35] wire [4110:0] _d_opcodes_clr_T_11 = 4111'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_1292 ? _d_opcodes_clr_T_11[1027:0] : 1028'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [4110:0] _d_sizes_clr_T_11 = 4111'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_1292 ? _d_sizes_clr_T_11[1027:0] : 1028'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 9'h0; // @[Monitor.scala:36:7, :795:113] wire [256:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [256:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [1027:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [1027:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [1027:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [1027:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]

Generate the Verilog code corresponding to the following Chisel files. File Crossing.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.interrupts import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.util.{SynchronizerShiftReg, AsyncResetReg} @deprecated("IntXing does not ensure interrupt source is glitch free. Use IntSyncSource and IntSyncSink", "rocket-chip 1.2") class IntXing(sync: Int = 3)(implicit p: Parameters) extends LazyModule { val intnode = IntAdapterNode() lazy val module = new Impl class Impl extends LazyModuleImp(this) { (intnode.in zip intnode.out) foreach { case ((in, _), (out, _)) => out := SynchronizerShiftReg(in, sync) } } } object IntSyncCrossingSource { def apply(alreadyRegistered: Boolean = false)(implicit p: Parameters) = { val intsource = LazyModule(new IntSyncCrossingSource(alreadyRegistered)) intsource.node } } class IntSyncCrossingSource(alreadyRegistered: Boolean = false)(implicit p: Parameters) extends LazyModule { val node = IntSyncSourceNode(alreadyRegistered) lazy val module = if (alreadyRegistered) (new ImplRegistered) else (new Impl) class Impl extends LazyModuleImp(this) { def outSize = node.out.headOption.map(_._1.sync.size).getOrElse(0) override def desiredName = s"IntSyncCrossingSource_n${node.out.size}x${outSize}" (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out.sync := AsyncResetReg(Cat(in.reverse)).asBools } } class ImplRegistered extends LazyRawModuleImp(this) { def outSize = node.out.headOption.map(_._1.sync.size).getOrElse(0) override def desiredName = s"IntSyncCrossingSource_n${node.out.size}x${outSize}_Registered" (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out.sync := in } } } object IntSyncCrossingSink { @deprecated("IntSyncCrossingSink which used the `sync` parameter to determine crossing type is deprecated. Use IntSyncAsyncCrossingSink, IntSyncRationalCrossingSink, or IntSyncSyncCrossingSink instead for > 1, 1, and 0 sync values respectively", "rocket-chip 1.2") def apply(sync: Int = 3)(implicit p: Parameters) = { val intsink = LazyModule(new IntSyncAsyncCrossingSink(sync)) intsink.node } } class IntSyncAsyncCrossingSink(sync: Int = 3)(implicit p: Parameters) extends LazyModule { val node = IntSyncSinkNode(sync) lazy val module = new Impl class Impl extends LazyModuleImp(this) { override def desiredName = s"IntSyncAsyncCrossingSink_n${node.out.size}x${node.out.head._1.size}" (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out := SynchronizerShiftReg(in.sync, sync) } } } object IntSyncAsyncCrossingSink { def apply(sync: Int = 3)(implicit p: Parameters) = { val intsink = LazyModule(new IntSyncAsyncCrossingSink(sync)) intsink.node } } class IntSyncSyncCrossingSink()(implicit p: Parameters) extends LazyModule { val node = IntSyncSinkNode(0) lazy val module = new Impl class Impl extends LazyRawModuleImp(this) { def outSize = node.out.headOption.map(_._1.size).getOrElse(0) override def desiredName = s"IntSyncSyncCrossingSink_n${node.out.size}x${outSize}" (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out := in.sync } } } object IntSyncSyncCrossingSink { def apply()(implicit p: Parameters) = { val intsink = LazyModule(new IntSyncSyncCrossingSink()) intsink.node } } class IntSyncRationalCrossingSink()(implicit p: Parameters) extends LazyModule { val node = IntSyncSinkNode(1) lazy val module = new Impl class Impl extends LazyModuleImp(this) { def outSize = node.out.headOption.map(_._1.size).getOrElse(0) override def desiredName = s"IntSyncRationalCrossingSink_n${node.out.size}x${outSize}" (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out := RegNext(in.sync) } } } object IntSyncRationalCrossingSink { def apply()(implicit p: Parameters) = { val intsink = LazyModule(new IntSyncRationalCrossingSink()) intsink.node } } File LazyModuleImp.scala: package org.chipsalliance.diplomacy.lazymodule import chisel3.{withClockAndReset, Module, RawModule, Reset, _} import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo} import firrtl.passes.InlineAnnotation import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.nodes.Dangle import scala.collection.immutable.SortedMap /** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]]. * * This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy. */ sealed trait LazyModuleImpLike extends RawModule { /** [[LazyModule]] that contains this instance. */ val wrapper: LazyModule /** IOs that will be automatically "punched" for this instance. */ val auto: AutoBundle /** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */ protected[diplomacy] val dangles: Seq[Dangle] // [[wrapper.module]] had better not be accessed while LazyModules are still being built! require( LazyModule.scope.isEmpty, s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}" ) /** Set module name. Defaults to the containing LazyModule's desiredName. */ override def desiredName: String = wrapper.desiredName suggestName(wrapper.suggestedName) /** [[Parameters]] for chisel [[Module]]s. */ implicit val p: Parameters = wrapper.p /** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and * submodules. */ protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = { // 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]], // 2. return [[Dangle]]s from each module. val childDangles = wrapper.children.reverse.flatMap { c => implicit val sourceInfo: SourceInfo = c.info c.cloneProto.map { cp => // If the child is a clone, then recursively set cloneProto of its children as well def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = { require(bases.size == clones.size) (bases.zip(clones)).map { case (l, r) => require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}") l.cloneProto = Some(r) assignCloneProtos(l.children, r.children) } } assignCloneProtos(c.children, cp.children) // Clone the child module as a record, and get its [[AutoBundle]] val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName) val clonedAuto = clone("auto").asInstanceOf[AutoBundle] // Get the empty [[Dangle]]'s of the cloned child val rawDangles = c.cloneDangles() require(rawDangles.size == clonedAuto.elements.size) // Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) } dangles }.getOrElse { // For non-clones, instantiate the child module val mod = try { Module(c.module) } catch { case e: ChiselException => { println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}") throw e } } mod.dangles } } // Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]]. // This will result in a sequence of [[Dangle]] from these [[BaseNode]]s. val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate()) // Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]] val allDangles = nodeDangles ++ childDangles // Group [[allDangles]] by their [[source]]. val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*) // For each [[source]] set of [[Dangle]]s of size 2, ensure that these // can be connected as a source-sink pair (have opposite flipped value). // Make the connection and mark them as [[done]]. val done = Set() ++ pairing.values.filter(_.size == 2).map { case Seq(a, b) => require(a.flipped != b.flipped) // @todo <> in chisel3 makes directionless connection. if (a.flipped) { a.data <> b.data } else { b.data <> a.data } a.source case _ => None } // Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module. val forward = allDangles.filter(d => !done(d.source)) // Generate [[AutoBundle]] IO from [[forward]]. val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*)) // Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]] val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) => if (d.flipped) { d.data <> io } else { io <> d.data } d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name) } // Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]]. wrapper.inModuleBody.reverse.foreach { _() } if (wrapper.shouldBeInlined) { chisel3.experimental.annotate(new ChiselAnnotation { def toFirrtl = InlineAnnotation(toNamed) }) } // Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]]. (auto, dangles) } } /** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike { /** Instantiate hardware of this `Module`. */ val (auto, dangles) = instantiate() } /** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike { // These wires are the default clock+reset for all LazyModule children. // It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the // [[LazyRawModuleImp]] children. // Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly. /** drive clock explicitly. */ val childClock: Clock = Wire(Clock()) /** drive reset explicitly. */ val childReset: Reset = Wire(Reset()) // the default is that these are disabled childClock := false.B.asClock childReset := chisel3.DontCare def provideImplicitClockToLazyChildren: Boolean = false val (auto, dangles) = if (provideImplicitClockToLazyChildren) { withClockAndReset(childClock, childReset) { instantiate() } } else { instantiate() } } File MixedNode.scala: package org.chipsalliance.diplomacy.nodes import chisel3.{Data, DontCare, Wire} import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.{Field, Parameters} import org.chipsalliance.diplomacy.ValName import org.chipsalliance.diplomacy.sourceLine /** One side metadata of a [[Dangle]]. * * Describes one side of an edge going into or out of a [[BaseNode]]. * * @param serial * the global [[BaseNode.serial]] number of the [[BaseNode]] that this [[HalfEdge]] connects to. * @param index * the `index` in the [[BaseNode]]'s input or output port list that this [[HalfEdge]] belongs to. */ case class HalfEdge(serial: Int, index: Int) extends Ordered[HalfEdge] { import scala.math.Ordered.orderingToOrdered def compare(that: HalfEdge): Int = HalfEdge.unapply(this).compare(HalfEdge.unapply(that)) } /** [[Dangle]] captures the `IO` information of a [[LazyModule]] and which two [[BaseNode]]s the [[Edges]]/[[Bundle]] * connects. * * [[Dangle]]s are generated by [[BaseNode.instantiate]] using [[MixedNode.danglesOut]] and [[MixedNode.danglesIn]] , * [[LazyModuleImp.instantiate]] connects those that go to internal or explicit IO connections in a [[LazyModule]]. * * @param source * the source [[HalfEdge]] of this [[Dangle]], which captures the source [[BaseNode]] and the port `index` within * that [[BaseNode]]. * @param sink * sink [[HalfEdge]] of this [[Dangle]], which captures the sink [[BaseNode]] and the port `index` within that * [[BaseNode]]. * @param flipped * flip or not in [[AutoBundle.makeElements]]. If true this corresponds to `danglesOut`, if false it corresponds to * `danglesIn`. * @param dataOpt * actual [[Data]] for the hardware connection. Can be empty if this belongs to a cloned module */ case class Dangle(source: HalfEdge, sink: HalfEdge, flipped: Boolean, name: String, dataOpt: Option[Data]) { def data = dataOpt.get } /** [[Edges]] is a collection of parameters describing the functionality and connection for an interface, which is often * derived from the interconnection protocol and can inform the parameterization of the hardware bundles that actually * implement the protocol. */ case class Edges[EI, EO](in: Seq[EI], out: Seq[EO]) /** A field available in [[Parameters]] used to determine whether [[InwardNodeImp.monitor]] will be called. */ case object MonitorsEnabled extends Field[Boolean](true) /** When rendering the edge in a graphical format, flip the order in which the edges' source and sink are presented. * * For example, when rendering graphML, yEd by default tries to put the source node vertically above the sink node, but * [[RenderFlipped]] inverts this relationship. When a particular [[LazyModule]] contains both source nodes and sink * nodes, flipping the rendering of one node's edge will usual produce a more concise visual layout for the * [[LazyModule]]. */ case object RenderFlipped extends Field[Boolean](false) /** The sealed node class in the package, all node are derived from it. * * @param inner * Sink interface implementation. * @param outer * Source interface implementation. * @param valName * val name of this node. * @tparam DI * Downward-flowing parameters received on the inner side of the node. It is usually a brunch of parameters * describing the protocol parameters from a source. For an [[InwardNode]], it is determined by the connected * [[OutwardNode]]. Since it can be connected to multiple sources, this parameter is always a Seq of source port * parameters. * @tparam UI * Upward-flowing parameters generated by the inner side of the node. It is usually a brunch of parameters describing * the protocol parameters of a sink. For an [[InwardNode]], it is determined itself. * @tparam EI * Edge Parameters describing a connection on the inner side of the node. It is usually a brunch of transfers * specified for a sink according to protocol. * @tparam BI * Bundle type used when connecting to the inner side of the node. It is a hardware interface of this sink interface. * It should extends from [[chisel3.Data]], which represents the real hardware. * @tparam DO * Downward-flowing parameters generated on the outer side of the node. It is usually a brunch of parameters * describing the protocol parameters of a source. For an [[OutwardNode]], it is determined itself. * @tparam UO * Upward-flowing parameters received by the outer side of the node. It is usually a brunch of parameters describing * the protocol parameters from a sink. For an [[OutwardNode]], it is determined by the connected [[InwardNode]]. * Since it can be connected to multiple sinks, this parameter is always a Seq of sink port parameters. * @tparam EO * Edge Parameters describing a connection on the outer side of the node. It is usually a brunch of transfers * specified for a source according to protocol. * @tparam BO * Bundle type used when connecting to the outer side of the node. It is a hardware interface of this source * interface. It should extends from [[chisel3.Data]], which represents the real hardware. * * @note * Call Graph of [[MixedNode]] * - line `─`: source is process by a function and generate pass to others * - Arrow `→`: target of arrow is generated by source * * {{{ * (from the other node) * ┌─────────────────────────────────────────────────────────[[InwardNode.uiParams]]─────────────┐ * ↓ │ * (binding node when elaboration) [[OutwardNode.uoParams]]────────────────────────[[MixedNode.mapParamsU]]→──────────┐ │ * [[InwardNode.accPI]] │ │ │ * │ │ (based on protocol) │ * │ │ [[MixedNode.inner.edgeI]] │ * │ │ ↓ │ * ↓ │ │ │ * (immobilize after elaboration) (inward port from [[OutwardNode]]) │ ↓ │ * [[InwardNode.iBindings]]──┐ [[MixedNode.iDirectPorts]]────────────────────→[[MixedNode.iPorts]] [[InwardNode.uiParams]] │ * │ │ ↑ │ │ │ * │ │ │ [[OutwardNode.doParams]] │ │ * │ │ │ (from the other node) │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * │ │ │ └────────┬──────────────┤ │ * │ │ │ │ │ │ * │ │ │ │ (based on protocol) │ * │ │ │ │ [[MixedNode.inner.edgeI]] │ * │ │ │ │ │ │ * │ │ (from the other node) │ ↓ │ * │ └───[[OutwardNode.oPortMapping]] [[OutwardNode.oStar]] │ [[MixedNode.edgesIn]]───┐ │ * │ ↑ ↑ │ │ ↓ │ * │ │ │ │ │ [[MixedNode.in]] │ * │ │ │ │ ↓ ↑ │ * │ (solve star connection) │ │ │ [[MixedNode.bundleIn]]──┘ │ * ├───[[MixedNode.resolveStar]]→─┼─────────────────────────────┤ └────────────────────────────────────┐ │ * │ │ │ [[MixedNode.bundleOut]]─┐ │ │ * │ │ │ ↑ ↓ │ │ * │ │ │ │ [[MixedNode.out]] │ │ * │ ↓ ↓ │ ↑ │ │ * │ ┌─────[[InwardNode.iPortMapping]] [[InwardNode.iStar]] [[MixedNode.edgesOut]]──┘ │ │ * │ │ (from the other node) ↑ │ │ * │ │ │ │ │ │ * │ │ │ [[MixedNode.outer.edgeO]] │ │ * │ │ │ (based on protocol) │ │ * │ │ │ │ │ │ * │ │ │ ┌────────────────────────────────────────┤ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * (immobilize after elaboration)│ ↓ │ │ │ │ * [[OutwardNode.oBindings]]─┘ [[MixedNode.oDirectPorts]]───→[[MixedNode.oPorts]] [[OutwardNode.doParams]] │ │ * ↑ (inward port from [[OutwardNode]]) │ │ │ │ * │ ┌─────────────────────────────────────────┤ │ │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * [[OutwardNode.accPO]] │ ↓ │ │ │ * (binding node when elaboration) │ [[InwardNode.diParams]]─────→[[MixedNode.mapParamsD]]────────────────────────────┘ │ │ * │ ↑ │ │ * │ └──────────────────────────────────────────────────────────────────────────────────────────┘ │ * └──────────────────────────────────────────────────────────────────────────────────────────────────────────┘ * }}} */ abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data]( val inner: InwardNodeImp[DI, UI, EI, BI], val outer: OutwardNodeImp[DO, UO, EO, BO] )( implicit valName: ValName) extends BaseNode with NodeHandle[DI, UI, EI, BI, DO, UO, EO, BO] with InwardNode[DI, UI, BI] with OutwardNode[DO, UO, BO] { // Generate a [[NodeHandle]] with inward and outward node are both this node. val inward = this val outward = this /** Debug info of nodes binding. */ def bindingInfo: String = s"""$iBindingInfo |$oBindingInfo |""".stripMargin /** Debug info of ports connecting. */ def connectedPortsInfo: String = s"""${oPorts.size} outward ports connected: [${oPorts.map(_._2.name).mkString(",")}] |${iPorts.size} inward ports connected: [${iPorts.map(_._2.name).mkString(",")}] |""".stripMargin /** Debug info of parameters propagations. */ def parametersInfo: String = s"""${doParams.size} downstream outward parameters: [${doParams.mkString(",")}] |${uoParams.size} upstream outward parameters: [${uoParams.mkString(",")}] |${diParams.size} downstream inward parameters: [${diParams.mkString(",")}] |${uiParams.size} upstream inward parameters: [${uiParams.mkString(",")}] |""".stripMargin /** For a given node, converts [[OutwardNode.accPO]] and [[InwardNode.accPI]] to [[MixedNode.oPortMapping]] and * [[MixedNode.iPortMapping]]. * * Given counts of known inward and outward binding and inward and outward star bindings, return the resolved inward * stars and outward stars. * * This method will also validate the arguments and throw a runtime error if the values are unsuitable for this type * of node. * * @param iKnown * Number of known-size ([[BIND_ONCE]]) input bindings. * @param oKnown * Number of known-size ([[BIND_ONCE]]) output bindings. * @param iStar * Number of unknown size ([[BIND_STAR]]) input bindings. * @param oStar * Number of unknown size ([[BIND_STAR]]) output bindings. * @return * A Tuple of the resolved number of input and output connections. */ protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStar: Int, oStar: Int): (Int, Int) /** Function to generate downward-flowing outward params from the downward-flowing input params and the current output * ports. * * @param n * The size of the output sequence to generate. * @param p * Sequence of downward-flowing input parameters of this node. * @return * A `n`-sized sequence of downward-flowing output edge parameters. */ protected[diplomacy] def mapParamsD(n: Int, p: Seq[DI]): Seq[DO] /** Function to generate upward-flowing input parameters from the upward-flowing output parameters [[uiParams]]. * * @param n * Size of the output sequence. * @param p * Upward-flowing output edge parameters. * @return * A n-sized sequence of upward-flowing input edge parameters. */ protected[diplomacy] def mapParamsU(n: Int, p: Seq[UO]): Seq[UI] /** @return * The sink cardinality of the node, the number of outputs bound with [[BIND_QUERY]] summed with inputs bound with * [[BIND_STAR]]. */ protected[diplomacy] lazy val sinkCard: Int = oBindings.count(_._3 == BIND_QUERY) + iBindings.count(_._3 == BIND_STAR) /** @return * The source cardinality of this node, the number of inputs bound with [[BIND_QUERY]] summed with the number of * output bindings bound with [[BIND_STAR]]. */ protected[diplomacy] lazy val sourceCard: Int = iBindings.count(_._3 == BIND_QUERY) + oBindings.count(_._3 == BIND_STAR) /** @return list of nodes involved in flex bindings with this node. */ protected[diplomacy] lazy val flexes: Seq[BaseNode] = oBindings.filter(_._3 == BIND_FLEX).map(_._2) ++ iBindings.filter(_._3 == BIND_FLEX).map(_._2) /** Resolves the flex to be either source or sink and returns the offset where the [[BIND_STAR]] operators begin * greedily taking up the remaining connections. * * @return * A value >= 0 if it is sink cardinality, a negative value for source cardinality. The magnitude of the return * value is not relevant. */ protected[diplomacy] lazy val flexOffset: Int = { /** Recursively performs a depth-first search of the [[flexes]], [[BaseNode]]s connected to this node with flex * operators. The algorithm bottoms out when we either get to a node we have already visited or when we get to a * connection that is not a flex and can set the direction for us. Otherwise, recurse by visiting the `flexes` of * each node in the current set and decide whether they should be added to the set or not. * * @return * the mapping of [[BaseNode]] indexed by their serial numbers. */ def DFS(v: BaseNode, visited: Map[Int, BaseNode]): Map[Int, BaseNode] = { if (visited.contains(v.serial) || !v.flexibleArityDirection) { visited } else { v.flexes.foldLeft(visited + (v.serial -> v))((sum, n) => DFS(n, sum)) } } /** Determine which [[BaseNode]] are involved in resolving the flex connections to/from this node. * * @example * {{{ * a :*=* b :*=* c * d :*=* b * e :*=* f * }}} * * `flexSet` for `a`, `b`, `c`, or `d` will be `Set(a, b, c, d)` `flexSet` for `e` or `f` will be `Set(e,f)` */ val flexSet = DFS(this, Map()).values /** The total number of :*= operators where we're on the left. */ val allSink = flexSet.map(_.sinkCard).sum /** The total number of :=* operators used when we're on the right. */ val allSource = flexSet.map(_.sourceCard).sum require( allSink == 0 || allSource == 0, s"The nodes ${flexSet.map(_.name)} which are inter-connected by :*=* have ${allSink} :*= operators and ${allSource} :=* operators connected to them, making it impossible to determine cardinality inference direction." ) allSink - allSource } /** @return A value >= 0 if it is sink cardinality, a negative value for source cardinality. */ protected[diplomacy] def edgeArityDirection(n: BaseNode): Int = { if (flexibleArityDirection) flexOffset else if (n.flexibleArityDirection) n.flexOffset else 0 } /** For a node which is connected between two nodes, select the one that will influence the direction of the flex * resolution. */ protected[diplomacy] def edgeAritySelect(n: BaseNode, l: => Int, r: => Int): Int = { val dir = edgeArityDirection(n) if (dir < 0) l else if (dir > 0) r else 1 } /** Ensure that the same node is not visited twice in resolving `:*=`, etc operators. */ private var starCycleGuard = false /** Resolve all the star operators into concrete indicies. As connections are being made, some may be "star" * connections which need to be resolved. In some way to determine how many actual edges they correspond to. We also * need to build up the ranges of edges which correspond to each binding operator, so that We can apply the correct * edge parameters and later build up correct bundle connections. * * [[oPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that oPort (binding * operator). [[iPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that iPort * (binding operator). [[oStar]]: `Int` the value to return for this node `N` for any `N :*= foo` or `N :*=* foo :*= * bar` [[iStar]]: `Int` the value to return for this node `N` for any `foo :=* N` or `bar :=* foo :*=* N` */ protected[diplomacy] lazy val ( oPortMapping: Seq[(Int, Int)], iPortMapping: Seq[(Int, Int)], oStar: Int, iStar: Int ) = { try { if (starCycleGuard) throw StarCycleException() starCycleGuard = true // For a given node N... // Number of foo :=* N // + Number of bar :=* foo :*=* N val oStars = oBindings.count { case (_, n, b, _, _) => b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) < 0) } // Number of N :*= foo // + Number of N :*=* foo :*= bar val iStars = iBindings.count { case (_, n, b, _, _) => b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) > 0) } // 1 for foo := N // + bar.iStar for bar :*= foo :*=* N // + foo.iStar for foo :*= N // + 0 for foo :=* N val oKnown = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, 0, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => 0 } }.sum // 1 for N := foo // + bar.oStar for N :*=* foo :=* bar // + foo.oStar for N :=* foo // + 0 for N :*= foo val iKnown = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, 0) case BIND_QUERY => n.oStar case BIND_STAR => 0 } }.sum // Resolve star depends on the node subclass to implement the algorithm for this. val (iStar, oStar) = resolveStar(iKnown, oKnown, iStars, oStars) // Cumulative list of resolved outward binding range starting points val oSum = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, oStar, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => oStar } }.scanLeft(0)(_ + _) // Cumulative list of resolved inward binding range starting points val iSum = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, iStar) case BIND_QUERY => n.oStar case BIND_STAR => iStar } }.scanLeft(0)(_ + _) // Create ranges for each binding based on the running sums and return // those along with resolved values for the star operations. (oSum.init.zip(oSum.tail), iSum.init.zip(iSum.tail), oStar, iStar) } catch { case c: StarCycleException => throw c.copy(loop = context +: c.loop) } } /** Sequence of inward ports. * * This should be called after all star bindings are resolved. * * Each element is: `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. * `n` Instance of inward node. `p` View of [[Parameters]] where this connection was made. `s` Source info where this * connection was made in the source code. */ protected[diplomacy] lazy val oDirectPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oBindings.flatMap { case (i, n, _, p, s) => // for each binding operator in this node, look at what it connects to val (start, end) = n.iPortMapping(i) (start until end).map { j => (j, n, p, s) } } /** Sequence of outward ports. * * This should be called after all star bindings are resolved. * * `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. `n` Instance of * outward node. `p` View of [[Parameters]] where this connection was made. `s` [[SourceInfo]] where this connection * was made in the source code. */ protected[diplomacy] lazy val iDirectPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iBindings.flatMap { case (i, n, _, p, s) => // query this port index range of this node in the other side of node. val (start, end) = n.oPortMapping(i) (start until end).map { j => (j, n, p, s) } } // Ephemeral nodes ( which have non-None iForward/oForward) have in_degree = out_degree // Thus, there must exist an Eulerian path and the below algorithms terminate @scala.annotation.tailrec private def oTrace( tuple: (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) ): (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.iForward(i) match { case None => (i, n, p, s) case Some((j, m)) => oTrace((j, m, p, s)) } } @scala.annotation.tailrec private def iTrace( tuple: (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) ): (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.oForward(i) match { case None => (i, n, p, s) case Some((j, m)) => iTrace((j, m, p, s)) } } /** Final output ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - Numeric index of this binding in the [[InwardNode]] on the other end. * - [[InwardNode]] on the other end of this binding. * - A view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. */ lazy val oPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oDirectPorts.map(oTrace) /** Final input ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - numeric index of this binding in [[OutwardNode]] on the other end. * - [[OutwardNode]] on the other end of this binding. * - a view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. */ lazy val iPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iDirectPorts.map(iTrace) private var oParamsCycleGuard = false protected[diplomacy] lazy val diParams: Seq[DI] = iPorts.map { case (i, n, _, _) => n.doParams(i) } protected[diplomacy] lazy val doParams: Seq[DO] = { try { if (oParamsCycleGuard) throw DownwardCycleException() oParamsCycleGuard = true val o = mapParamsD(oPorts.size, diParams) require( o.size == oPorts.size, s"""Diplomacy has detected a problem with your graph: |At the following node, the number of outward ports should equal the number of produced outward parameters. |$context |$connectedPortsInfo |Downstreamed inward parameters: [${diParams.mkString(",")}] |Produced outward parameters: [${o.mkString(",")}] |""".stripMargin ) o.map(outer.mixO(_, this)) } catch { case c: DownwardCycleException => throw c.copy(loop = context +: c.loop) } } private var iParamsCycleGuard = false protected[diplomacy] lazy val uoParams: Seq[UO] = oPorts.map { case (o, n, _, _) => n.uiParams(o) } protected[diplomacy] lazy val uiParams: Seq[UI] = { try { if (iParamsCycleGuard) throw UpwardCycleException() iParamsCycleGuard = true val i = mapParamsU(iPorts.size, uoParams) require( i.size == iPorts.size, s"""Diplomacy has detected a problem with your graph: |At the following node, the number of inward ports should equal the number of produced inward parameters. |$context |$connectedPortsInfo |Upstreamed outward parameters: [${uoParams.mkString(",")}] |Produced inward parameters: [${i.mkString(",")}] |""".stripMargin ) i.map(inner.mixI(_, this)) } catch { case c: UpwardCycleException => throw c.copy(loop = context +: c.loop) } } /** Outward edge parameters. */ protected[diplomacy] lazy val edgesOut: Seq[EO] = (oPorts.zip(doParams)).map { case ((i, n, p, s), o) => outer.edgeO(o, n.uiParams(i), p, s) } /** Inward edge parameters. */ protected[diplomacy] lazy val edgesIn: Seq[EI] = (iPorts.zip(uiParams)).map { case ((o, n, p, s), i) => inner.edgeI(n.doParams(o), i, p, s) } /** A tuple of the input edge parameters and output edge parameters for the edges bound to this node. * * If you need to access to the edges of a foreign Node, use this method (in/out create bundles). */ lazy val edges: Edges[EI, EO] = Edges(edgesIn, edgesOut) /** Create actual Wires corresponding to the Bundles parameterized by the outward edges of this node. */ protected[diplomacy] lazy val bundleOut: Seq[BO] = edgesOut.map { e => val x = Wire(outer.bundleO(e)).suggestName(s"${valName.value}Out") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } /** Create actual Wires corresponding to the Bundles parameterized by the inward edges of this node. */ protected[diplomacy] lazy val bundleIn: Seq[BI] = edgesIn.map { e => val x = Wire(inner.bundleI(e)).suggestName(s"${valName.value}In") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } private def emptyDanglesOut: Seq[Dangle] = oPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(serial, i), sink = HalfEdge(n.serial, j), flipped = false, name = wirePrefix + "out", dataOpt = None ) } private def emptyDanglesIn: Seq[Dangle] = iPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(n.serial, j), sink = HalfEdge(serial, i), flipped = true, name = wirePrefix + "in", dataOpt = None ) } /** Create the [[Dangle]]s which describe the connections from this node output to other nodes inputs. */ protected[diplomacy] def danglesOut: Seq[Dangle] = emptyDanglesOut.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleOut(i))) } /** Create the [[Dangle]]s which describe the connections from this node input from other nodes outputs. */ protected[diplomacy] def danglesIn: Seq[Dangle] = emptyDanglesIn.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleIn(i))) } private[diplomacy] var instantiated = false /** Gather Bundle and edge parameters of outward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. */ def out: Seq[(BO, EO)] = { require( instantiated, s"$name.out should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleOut.zip(edgesOut) } /** Gather Bundle and edge parameters of inward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. */ def in: Seq[(BI, EI)] = { require( instantiated, s"$name.in should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleIn.zip(edgesIn) } /** Actually instantiate this node during [[LazyModuleImp]] evaluation. Mark that it's safe to use the Bundle wires, * instantiate monitors on all input ports if appropriate, and return all the dangles of this node. */ protected[diplomacy] def instantiate(): Seq[Dangle] = { instantiated = true if (!circuitIdentity) { (iPorts.zip(in)).foreach { case ((_, _, p, _), (b, e)) => if (p(MonitorsEnabled)) inner.monitor(b, e) } } danglesOut ++ danglesIn } protected[diplomacy] def cloneDangles(): Seq[Dangle] = emptyDanglesOut ++ emptyDanglesIn /** Connects the outward part of a node with the inward part of this node. */ protected[diplomacy] def bind( h: OutwardNode[DI, UI, BI], binding: NodeBinding )( implicit p: Parameters, sourceInfo: SourceInfo ): Unit = { val x = this // x := y val y = h sourceLine(sourceInfo, " at ", "") val i = x.iPushed val o = y.oPushed y.oPush( i, x, binding match { case BIND_ONCE => BIND_ONCE case BIND_FLEX => BIND_FLEX case BIND_STAR => BIND_QUERY case BIND_QUERY => BIND_STAR } ) x.iPush(o, y, binding) } /* Metadata for printing the node graph. */ def inputs: Seq[(OutwardNode[DI, UI, BI], RenderedEdge)] = (iPorts.zip(edgesIn)).map { case ((_, n, p, _), e) => val re = inner.render(e) (n, re.copy(flipped = re.flipped != p(RenderFlipped))) } /** Metadata for printing the node graph */ def outputs: Seq[(InwardNode[DO, UO, BO], RenderedEdge)] = oPorts.map { case (i, n, _, _) => (n, n.inputs(i)._2) } }

module IntSyncSyncCrossingSink_n1x2_9( // @[Crossing.scala:96:9] input auto_in_sync_0, // @[LazyModuleImp.scala:107:25] input auto_in_sync_1, // @[LazyModuleImp.scala:107:25] output auto_out_0, // @[LazyModuleImp.scala:107:25] output auto_out_1 // @[LazyModuleImp.scala:107:25] ); wire auto_in_sync_0_0 = auto_in_sync_0; // @[Crossing.scala:96:9] wire auto_in_sync_1_0 = auto_in_sync_1; // @[Crossing.scala:96:9] wire childClock = 1'h0; // @[LazyModuleImp.scala:155:31] wire childReset = 1'h0; // @[LazyModuleImp.scala:158:31] wire _childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25] wire nodeIn_sync_0 = auto_in_sync_0_0; // @[Crossing.scala:96:9] wire nodeIn_sync_1 = auto_in_sync_1_0; // @[Crossing.scala:96:9] wire nodeOut_0; // @[MixedNode.scala:542:17] wire nodeOut_1; // @[MixedNode.scala:542:17] wire auto_out_0_0; // @[Crossing.scala:96:9] wire auto_out_1_0; // @[Crossing.scala:96:9] assign nodeOut_0 = nodeIn_sync_0; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_1 = nodeIn_sync_1; // @[MixedNode.scala:542:17, :551:17] assign auto_out_0_0 = nodeOut_0; // @[Crossing.scala:96:9] assign auto_out_1_0 = nodeOut_1; // @[Crossing.scala:96:9] assign auto_out_0 = auto_out_0_0; // @[Crossing.scala:96:9] assign auto_out_1 = auto_out_1_0; // @[Crossing.scala:96:9] endmodule

Generate the Verilog code corresponding to the following Chisel files. File Monitor.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceLine import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import freechips.rocketchip.diplomacy.EnableMonitors import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode} import freechips.rocketchip.util.PlusArg case class TLMonitorArgs(edge: TLEdge) abstract class TLMonitorBase(args: TLMonitorArgs) extends Module { val io = IO(new Bundle { val in = Input(new TLBundle(args.edge.bundle)) }) def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit legalize(io.in, args.edge, reset) } object TLMonitor { def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = { if (enable) { EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) } } else { node } } } class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args) { require (args.edge.params(TLMonitorStrictMode) || (! args.edge.params(TestplanTestType).formal)) val cover_prop_class = PropertyClass.Default //Like assert but can flip to being an assumption for formal verification def monAssert(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir, cond, message, PropertyClass.Default) } def assume(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir.flip, cond, message, PropertyClass.Default) } def extra = { args.edge.sourceInfo match { case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)" case _ => "" } } def visible(address: UInt, source: UInt, edge: TLEdge) = edge.client.clients.map { c => !c.sourceId.contains(source) || c.visibility.map(_.contains(address)).reduce(_ || _) }.reduce(_ && _) def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = { //switch this flag to turn on diplomacy in error messages def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n" monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra) // Reuse these subexpressions to save some firrtl lines val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility") //The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B //TODO: check for acquireT? when (bundle.opcode === TLMessages.AcquireBlock) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra) } when (bundle.opcode === TLMessages.AcquirePerm) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra) monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra) monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra) monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra) } } def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = { monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra) monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility") // Reuse these subexpressions to save some firrtl lines val address_ok = edge.manager.containsSafe(edge.address(bundle)) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source when (bundle.opcode === TLMessages.Probe) { assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra) assume (address_ok, "'B' channel Probe carries unmanaged address" + extra) assume (legal_source, "'B' channel Probe carries source that is not first source" + extra) assume (is_aligned, "'B' channel Probe address not aligned to size" + extra) assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra) assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra) assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra) monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra) monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra) monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra) monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra) } } def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = { monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val address_ok = edge.manager.containsSafe(edge.address(bundle)) monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility") when (bundle.opcode === TLMessages.ProbeAck) { monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra) } when (bundle.opcode === TLMessages.ProbeAckData) { monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.Release) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra) monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra) } when (bundle.opcode === TLMessages.ReleaseData) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.AccessAck) { monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra) } when (bundle.opcode === TLMessages.HintAck) { monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra) } } def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = { assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val sink_ok = bundle.sink < edge.manager.endSinkId.U val deny_put_ok = edge.manager.mayDenyPut.B val deny_get_ok = edge.manager.mayDenyGet.B when (bundle.opcode === TLMessages.ReleaseAck) { assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra) assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra) assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra) } when (bundle.opcode === TLMessages.Grant) { assume (source_ok, "'D' channel Grant carries invalid source ID" + extra) assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra) assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel Grant is denied" + extra) } when (bundle.opcode === TLMessages.GrantData) { assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra) assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra) assume (!bundle.denied || bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra) assume (deny_get_ok || !bundle.denied, "'D' channel GrantData is denied" + extra) } when (bundle.opcode === TLMessages.AccessAck) { assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel AccessAck is denied" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra) assume (!bundle.denied || bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra) assume (deny_get_ok || !bundle.denied, "'D' channel AccessAckData is denied" + extra) } when (bundle.opcode === TLMessages.HintAck) { assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel HintAck is denied" + extra) } } def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = { val sink_ok = bundle.sink < edge.manager.endSinkId.U monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra) } def legalizeFormat(bundle: TLBundle, edge: TLEdge) = { when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) } when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) } when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) } when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) } } else { monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra) monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra) monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra) } } def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = { val a_first = edge.first(a.bits, a.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (a.valid && !a_first) { monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra) monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra) monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra) monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra) monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra) } when (a.fire && a_first) { opcode := a.bits.opcode param := a.bits.param size := a.bits.size source := a.bits.source address := a.bits.address } } def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = { val b_first = edge.first(b.bits, b.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (b.valid && !b_first) { monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra) monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra) monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra) monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra) monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra) } when (b.fire && b_first) { opcode := b.bits.opcode param := b.bits.param size := b.bits.size source := b.bits.source address := b.bits.address } } def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = { // Symbolic variable val sym_source = Wire(UInt(edge.client.endSourceId.W)) // TODO: Connect sym_source to a fixed value for simulation and to a // free wire in formal sym_source := 0.U // Type casting Int to UInt val maxSourceId = Wire(UInt(edge.client.endSourceId.W)) maxSourceId := edge.client.endSourceId.U // Delayed verison of sym_source val sym_source_d = Reg(UInt(edge.client.endSourceId.W)) sym_source_d := sym_source // These will be constraints for FV setup Property( MonitorDirection.Monitor, (sym_source === sym_source_d), "sym_source should remain stable", PropertyClass.Default) Property( MonitorDirection.Monitor, (sym_source <= maxSourceId), "sym_source should take legal value", PropertyClass.Default) val my_resp_pend = RegInit(false.B) val my_opcode = Reg(UInt()) val my_size = Reg(UInt()) val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire) val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire) val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source) val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source) val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat) val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend) when (my_set_resp_pend) { my_resp_pend := true.B } .elsewhen (my_clr_resp_pend) { my_resp_pend := false.B } when (my_a_first_beat) { my_opcode := bundle.a.bits.opcode my_size := bundle.a.bits.size } val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size) val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode) val my_resp_opcode_legal = Wire(Bool()) when ((my_resp_opcode === TLMessages.Get) || (my_resp_opcode === TLMessages.ArithmeticData) || (my_resp_opcode === TLMessages.LogicalData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData) } .elsewhen ((my_resp_opcode === TLMessages.PutFullData) || (my_resp_opcode === TLMessages.PutPartialData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck) } .otherwise { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck) } monAssert (IfThen(my_resp_pend, !my_a_first_beat), "Request message should not be sent with a source ID, for which a response message" + "is already pending (not received until current cycle) for a prior request message" + "with the same source ID" + extra) assume (IfThen(my_clr_resp_pend, (my_set_resp_pend || my_resp_pend)), "Response message should be accepted with a source ID only if a request message with the" + "same source ID has been accepted or is being accepted in the current cycle" + extra) assume (IfThen(my_d_first_beat, (my_a_first_beat || my_resp_pend)), "Response message should be sent with a source ID only if a request message with the" + "same source ID has been accepted or is being sent in the current cycle" + extra) assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)), "If d_valid is 1, then d_size should be same as a_size of the corresponding request" + "message" + extra) assume (IfThen(my_d_first_beat, my_resp_opcode_legal), "If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" + "request message" + extra) } def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = { val c_first = edge.first(c.bits, c.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (c.valid && !c_first) { monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra) monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra) monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra) monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra) monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra) } when (c.fire && c_first) { opcode := c.bits.opcode param := c.bits.param size := c.bits.size source := c.bits.source address := c.bits.address } } def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = { val d_first = edge.first(d.bits, d.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val sink = Reg(UInt()) val denied = Reg(Bool()) when (d.valid && !d_first) { assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra) assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra) assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra) assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra) assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra) assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra) } when (d.fire && d_first) { opcode := d.bits.opcode param := d.bits.param size := d.bits.size source := d.bits.source sink := d.bits.sink denied := d.bits.denied } } def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = { legalizeMultibeatA(bundle.a, edge) legalizeMultibeatD(bundle.d, edge) if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { legalizeMultibeatB(bundle.b, edge) legalizeMultibeatC(bundle.c, edge) } } //This is left in for almond which doesn't adhere to the tilelink protocol @deprecated("Use legalizeADSource instead if possible","") def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.client.endSourceId.W)) val a_first = edge.first(bundle.a.bits, bundle.a.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val a_set = WireInit(0.U(edge.client.endSourceId.W)) when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) assume((a_set | inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra) } if (edge.manager.minLatency > 0) { assume(a_set =/= d_clr || !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight | a_set) & ~d_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") assert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = { val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size) val log_a_size_bus_size = log2Ceil(a_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error inflight.suggestName("inflight") val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) inflight_opcodes.suggestName("inflight_opcodes") val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) inflight_sizes.suggestName("inflight_sizes") val a_first = edge.first(bundle.a.bits, bundle.a.fire) a_first.suggestName("a_first") val d_first = edge.first(bundle.d.bits, bundle.d.fire) d_first.suggestName("d_first") val a_set = WireInit(0.U(edge.client.endSourceId.W)) val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) a_set.suggestName("a_set") a_set_wo_ready.suggestName("a_set_wo_ready") val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) a_opcodes_set.suggestName("a_opcodes_set") val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) a_sizes_set.suggestName("a_sizes_set") val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W)) a_opcode_lookup.suggestName("a_opcode_lookup") a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W)) a_size_lookup.suggestName("a_size_lookup") a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant)) val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant)) val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W)) a_opcodes_set_interm.suggestName("a_opcodes_set_interm") val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W)) a_sizes_set_interm.suggestName("a_sizes_set_interm") when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) { a_set_wo_ready := UIntToOH(bundle.a.bits.source) } when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) | 1.U a_sizes_set_interm := (bundle.a.bits.size << 1.U) | 1.U a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U) a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U) monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) d_opcodes_clr.suggestName("d_opcodes_clr") val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) || (bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra) assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) || (bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra) assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) { assume((!bundle.d.ready) || bundle.a.ready, "ready check") } if (edge.manager.minLatency > 0) { assume(a_set_wo_ready =/= d_clr_wo_ready || !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight | a_set) & ~d_clr inflight_opcodes := (inflight_opcodes | a_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes | a_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = { val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size) val log_c_size_bus_size = log2Ceil(c_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) inflight.suggestName("inflight") inflight_opcodes.suggestName("inflight_opcodes") inflight_sizes.suggestName("inflight_sizes") val c_first = edge.first(bundle.c.bits, bundle.c.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) c_first.suggestName("c_first") d_first.suggestName("d_first") val c_set = WireInit(0.U(edge.client.endSourceId.W)) val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) c_set.suggestName("c_set") c_set_wo_ready.suggestName("c_set_wo_ready") c_opcodes_set.suggestName("c_opcodes_set") c_sizes_set.suggestName("c_sizes_set") val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W)) val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W)) c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U c_opcode_lookup.suggestName("c_opcode_lookup") c_size_lookup.suggestName("c_size_lookup") val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W)) val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W)) c_opcodes_set_interm.suggestName("c_opcodes_set_interm") c_sizes_set_interm.suggestName("c_sizes_set_interm") when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) { c_set_wo_ready := UIntToOH(bundle.c.bits.source) } when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) { c_set := UIntToOH(bundle.c.bits.source) c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) | 1.U c_sizes_set_interm := (bundle.c.bits.size << 1.U) | 1.U c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U) c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U) monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra) } val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck || bundle.c.bits.opcode === TLMessages.ProbeAckData val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") d_opcodes_clr.suggestName("d_opcodes_clr") d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) { assume((!bundle.d.ready) || bundle.c.ready, "ready check") } if (edge.manager.minLatency > 0) { when (c_set_wo_ready.orR) { assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra) } } inflight := (inflight | c_set) & ~d_clr inflight_opcodes := (inflight_opcodes | c_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes | c_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.c.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.manager.endSinkId.W)) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val e_first = true.B val d_set = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) { d_set := UIntToOH(bundle.d.bits.sink) assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra) } val e_clr = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) { e_clr := UIntToOH(bundle.e.bits.sink) monAssert((d_set | inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra) } // edge.client.minLatency applies to BC, not DE inflight := (inflight | d_set) & ~e_clr } def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = { val sourceBits = log2Ceil(edge.client.endSourceId) val tooBig = 14 // >16kB worth of flight information gets to be too much if (sourceBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked") } else { if (args.edge.params(TestplanTestType).simulation) { if (args.edge.params(TLMonitorStrictMode)) { legalizeADSource(bundle, edge) legalizeCDSource(bundle, edge) } else { legalizeADSourceOld(bundle, edge) } } if (args.edge.params(TestplanTestType).formal) { legalizeADSourceFormal(bundle, edge) } } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { // legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize... val sinkBits = log2Ceil(edge.manager.endSinkId) if (sinkBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked") } else { legalizeDESink(bundle, edge) } } } def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = { legalizeFormat (bundle, edge) legalizeMultibeat (bundle, edge) legalizeUnique (bundle, edge) } } File Misc.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import scala.math._ class ParameterizedBundle(implicit p: Parameters) extends Bundle trait Clocked extends Bundle { val clock = Clock() val reset = Bool() } object DecoupledHelper { def apply(rvs: Bool*) = new DecoupledHelper(rvs) } class DecoupledHelper(val rvs: Seq[Bool]) { def fire(exclude: Bool, includes: Bool*) = { require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!") (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _) } def fire() = { rvs.reduce(_ && _) } } object MuxT { def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2)) def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3)) def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4)) } /** Creates a cascade of n MuxTs to search for a key value. */ object MuxTLookup { def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } } object ValidMux { def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]*): ValidIO[T] = { apply(v1 +: v2.toSeq) } def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = { val out = Wire(Valid(valids.head.bits.cloneType)) out.valid := valids.map(_.valid).reduce(_ || _) out.bits := MuxCase(valids.head.bits, valids.map(v => (v.valid -> v.bits))) out } } object Str { def apply(s: String): UInt = { var i = BigInt(0) require(s.forall(validChar _)) for (c <- s) i = (i << 8) | c i.U((s.length*8).W) } def apply(x: Char): UInt = { require(validChar(x)) x.U(8.W) } def apply(x: UInt): UInt = apply(x, 10) def apply(x: UInt, radix: Int): UInt = { val rad = radix.U val w = x.getWidth require(w > 0) var q = x var s = digit(q % rad) for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s) } s } def apply(x: SInt): UInt = apply(x, 10) def apply(x: SInt, radix: Int): UInt = { val neg = x < 0.S val abs = x.abs.asUInt if (radix != 10) { Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix)) } else { val rad = radix.U val w = abs.getWidth require(w > 0) var q = abs var s = digit(q % rad) var needSign = neg for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad val placeSpace = q === 0.U val space = Mux(needSign, Str('-'), Str(' ')) needSign = needSign && !placeSpace s = Cat(Mux(placeSpace, space, digit(q % rad)), s) } Cat(Mux(needSign, Str('-'), Str(' ')), s) } } private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0) private def validChar(x: Char) = x == (x & 0xFF) } object Split { def apply(x: UInt, n0: Int) = { val w = x.getWidth (x.extract(w-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n2: Int, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } } object Random { def apply(mod: Int, random: UInt): UInt = { if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0) else PriorityEncoder(partition(apply(1 << log2Up(mod*8), random), mod)) } def apply(mod: Int): UInt = apply(mod, randomizer) def oneHot(mod: Int, random: UInt): UInt = { if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0)) else PriorityEncoderOH(partition(apply(1 << log2Up(mod*8), random), mod)).asUInt } def oneHot(mod: Int): UInt = oneHot(mod, randomizer) private def randomizer = LFSR(16) private def partition(value: UInt, slices: Int) = Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U) } object Majority { def apply(in: Set[Bool]): Bool = { val n = (in.size >> 1) + 1 val clauses = in.subsets(n).map(_.reduce(_ && _)) clauses.reduce(_ || _) } def apply(in: Seq[Bool]): Bool = apply(in.toSet) def apply(in: UInt): Bool = apply(in.asBools.toSet) } object PopCountAtLeast { private def two(x: UInt): (Bool, Bool) = x.getWidth match { case 1 => (x.asBool, false.B) case n => val half = x.getWidth / 2 val (leftOne, leftTwo) = two(x(half - 1, 0)) val (rightOne, rightTwo) = two(x(x.getWidth - 1, half)) (leftOne || rightOne, leftTwo || rightTwo || (leftOne && rightOne)) } def apply(x: UInt, n: Int): Bool = n match { case 0 => true.B case 1 => x.orR case 2 => two(x)._2 case 3 => PopCount(x) >= n.U } } // This gets used everywhere, so make the smallest circuit possible ... // Given an address and size, create a mask of beatBytes size // eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111 // groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01 object MaskGen { def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = { require (groupBy >= 1 && beatBytes >= groupBy) require (isPow2(beatBytes) && isPow2(groupBy)) val lgBytes = log2Ceil(beatBytes) val sizeOH = UIntToOH(lgSize | 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) | (groupBy*2 - 1).U def helper(i: Int): Seq[(Bool, Bool)] = { if (i == 0) { Seq((lgSize >= lgBytes.asUInt, true.B)) } else { val sub = helper(i-1) val size = sizeOH(lgBytes - i) val bit = addr_lo(lgBytes - i) val nbit = !bit Seq.tabulate (1 << i) { j => val (sub_acc, sub_eq) = sub(j/2) val eq = sub_eq && (if (j % 2 == 1) bit else nbit) val acc = sub_acc || (size && eq) (acc, eq) } } } if (groupBy == beatBytes) 1.U else Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse) } } File PlusArg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.experimental._ import chisel3.util.HasBlackBoxResource @deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05") case class PlusArgInfo(default: BigInt, docstring: String) /** Case class for PlusArg information * * @tparam A scala type of the PlusArg value * @param default optional default value * @param docstring text to include in the help * @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT) */ private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String) /** Typeclass for converting a type to a doctype string * @tparam A some type */ trait Doctypeable[A] { /** Return the doctype string for some option */ def toDoctype(a: Option[A]): String } /** Object containing implementations of the Doctypeable typeclass */ object Doctypes { /** Converts an Int => "INT" */ implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" } /** Converts a BigInt => "INT" */ implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" } /** Converts a String => "STRING" */ implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" } } class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map( "FORMAT" -> StringParam(format), "DEFAULT" -> IntParam(default), "WIDTH" -> IntParam(width) )) with HasBlackBoxResource { val io = IO(new Bundle { val out = Output(UInt(width.W)) }) addResource("/vsrc/plusarg_reader.v") } /* This wrapper class has no outputs, making it clear it is a simulation-only construct */ class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module { val io = IO(new Bundle { val count = Input(UInt(width.W)) }) val max = Module(new plusarg_reader(format, default, docstring, width)).io.out when (max > 0.U) { assert (io.count < max, s"Timeout exceeded: $docstring") } } import Doctypes._ object PlusArg { /** PlusArg("foo") will return 42.U if the simulation is run with +foo=42 * Do not use this as an initial register value. The value is set in an * initial block and thus accessing it from another initial is racey. * Add a docstring to document the arg, which can be dumped in an elaboration * pass. */ def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out } /** PlusArg.timeout(name, default, docstring)(count) will use chisel.assert * to kill the simulation when count exceeds the specified integer argument. * Default 0 will never assert. */ def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count } } object PlusArgArtefacts { private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty /* Add a new PlusArg */ @deprecated( "Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05" ) def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring) /** Add a new PlusArg * * @tparam A scala type of the PlusArg value * @param name name for the PlusArg * @param default optional default value * @param docstring text to include in the help */ def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit = artefacts = artefacts ++ Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default))) /* From plus args, generate help text */ private def serializeHelp_cHeader(tab: String = ""): String = artefacts .map{ case(arg, info) => s"""|$tab+$arg=${info.doctype}\\n\\ |$tab${" "*20}${info.docstring}\\n\\ |""".stripMargin ++ info.default.map{ case default => s"$tab${" "*22}(default=${default})\\n\\\n"}.getOrElse("") }.toSeq.mkString("\\n\\\n") ++ "\"" /* From plus args, generate a char array of their names */ private def serializeArray_cHeader(tab: String = ""): String = { val prettyTab = tab + " " * 44 // Length of 'static const ...' s"${tab}static const char * verilog_plusargs [] = {\\\n" ++ artefacts .map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" } .mkString("")++ s"${prettyTab}0};" } /* Generate C code to be included in emulator.cc that helps with * argument parsing based on available Verilog PlusArgs */ def serialize_cHeader(): String = s"""|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\ |${serializeHelp_cHeader(" "*7)} |${serializeArray_cHeader()} |""".stripMargin } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /** Like Vec.apply(idx), but tolerates indices of mismatched width */ def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /** Any Data subtype that has a Bool member named valid. */ type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /** converts from camel case to to underscores, also removing all spaces */ def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /** converts spaces or underscores to hyphens, also lowering case */ def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y | (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y || y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /** Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation */ def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Bundles.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import freechips.rocketchip.util._ import scala.collection.immutable.ListMap import chisel3.util.Decoupled import chisel3.util.DecoupledIO import chisel3.reflect.DataMirror abstract class TLBundleBase(val params: TLBundleParameters) extends Bundle // common combos in lazy policy: // Put + Acquire // Release + AccessAck object TLMessages { // A B C D E def PutFullData = 0.U // . . => AccessAck def PutPartialData = 1.U // . . => AccessAck def ArithmeticData = 2.U // . . => AccessAckData def LogicalData = 3.U // . . => AccessAckData def Get = 4.U // . . => AccessAckData def Hint = 5.U // . . => HintAck def AcquireBlock = 6.U // . => Grant[Data] def AcquirePerm = 7.U // . => Grant[Data] def Probe = 6.U // . => ProbeAck[Data] def AccessAck = 0.U // . . def AccessAckData = 1.U // . . def HintAck = 2.U // . . def ProbeAck = 4.U // . def ProbeAckData = 5.U // . def Release = 6.U // . => ReleaseAck def ReleaseData = 7.U // . => ReleaseAck def Grant = 4.U // . => GrantAck def GrantData = 5.U // . => GrantAck def ReleaseAck = 6.U // . def GrantAck = 0.U // . def isA(x: UInt) = x <= AcquirePerm def isB(x: UInt) = x <= Probe def isC(x: UInt) = x <= ReleaseData def isD(x: UInt) = x <= ReleaseAck def adResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, Grant, Grant) def bcResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, ProbeAck, ProbeAck) def a = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("AcquireBlock",TLPermissions.PermMsgGrow), ("AcquirePerm",TLPermissions.PermMsgGrow)) def b = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("Probe",TLPermissions.PermMsgCap)) def c = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("ProbeAck",TLPermissions.PermMsgReport), ("ProbeAckData",TLPermissions.PermMsgReport), ("Release",TLPermissions.PermMsgReport), ("ReleaseData",TLPermissions.PermMsgReport)) def d = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("Grant",TLPermissions.PermMsgCap), ("GrantData",TLPermissions.PermMsgCap), ("ReleaseAck",TLPermissions.PermMsgReserved)) } /** * The three primary TileLink permissions are: * (T)runk: the agent is (or is on inwards path to) the global point of serialization. * (B)ranch: the agent is on an outwards path to * (N)one: * These permissions are permuted by transfer operations in various ways. * Operations can cap permissions, request for them to be grown or shrunk, * or for a report on their current status. */ object TLPermissions { val aWidth = 2 val bdWidth = 2 val cWidth = 3 // Cap types (Grant = new permissions, Probe = permisions <= target) def toT = 0.U(bdWidth.W) def toB = 1.U(bdWidth.W) def toN = 2.U(bdWidth.W) def isCap(x: UInt) = x <= toN // Grow types (Acquire = permissions >= target) def NtoB = 0.U(aWidth.W) def NtoT = 1.U(aWidth.W) def BtoT = 2.U(aWidth.W) def isGrow(x: UInt) = x <= BtoT // Shrink types (ProbeAck, Release) def TtoB = 0.U(cWidth.W) def TtoN = 1.U(cWidth.W) def BtoN = 2.U(cWidth.W) def isShrink(x: UInt) = x <= BtoN // Report types (ProbeAck, Release) def TtoT = 3.U(cWidth.W) def BtoB = 4.U(cWidth.W) def NtoN = 5.U(cWidth.W) def isReport(x: UInt) = x <= NtoN def PermMsgGrow:Seq[String] = Seq("Grow NtoB", "Grow NtoT", "Grow BtoT") def PermMsgCap:Seq[String] = Seq("Cap toT", "Cap toB", "Cap toN") def PermMsgReport:Seq[String] = Seq("Shrink TtoB", "Shrink TtoN", "Shrink BtoN", "Report TotT", "Report BtoB", "Report NtoN") def PermMsgReserved:Seq[String] = Seq("Reserved") } object TLAtomics { val width = 3 // Arithmetic types def MIN = 0.U(width.W) def MAX = 1.U(width.W) def MINU = 2.U(width.W) def MAXU = 3.U(width.W) def ADD = 4.U(width.W) def isArithmetic(x: UInt) = x <= ADD // Logical types def XOR = 0.U(width.W) def OR = 1.U(width.W) def AND = 2.U(width.W) def SWAP = 3.U(width.W) def isLogical(x: UInt) = x <= SWAP def ArithMsg:Seq[String] = Seq("MIN", "MAX", "MINU", "MAXU", "ADD") def LogicMsg:Seq[String] = Seq("XOR", "OR", "AND", "SWAP") } object TLHints { val width = 1 def PREFETCH_READ = 0.U(width.W) def PREFETCH_WRITE = 1.U(width.W) def isHints(x: UInt) = x <= PREFETCH_WRITE def HintsMsg:Seq[String] = Seq("PrefetchRead", "PrefetchWrite") } sealed trait TLChannel extends TLBundleBase { val channelName: String } sealed trait TLDataChannel extends TLChannel sealed trait TLAddrChannel extends TLDataChannel final class TLBundleA(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleA_${params.shortName}" val channelName = "'A' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(List(TLAtomics.width, TLPermissions.aWidth, TLHints.width).max.W) // amo_opcode || grow perms || hint val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleB(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleB_${params.shortName}" val channelName = "'B' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val address = UInt(params.addressBits.W) // from // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleC(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleC_${params.shortName}" val channelName = "'C' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.cWidth.W) // shrink or report perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleD(params: TLBundleParameters) extends TLBundleBase(params) with TLDataChannel { override def typeName = s"TLBundleD_${params.shortName}" val channelName = "'D' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val sink = UInt(params.sinkBits.W) // from val denied = Bool() // implies corrupt iff *Data val user = BundleMap(params.responseFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleE(params: TLBundleParameters) extends TLBundleBase(params) with TLChannel { override def typeName = s"TLBundleE_${params.shortName}" val channelName = "'E' channel" val sink = UInt(params.sinkBits.W) // to } class TLBundle(val params: TLBundleParameters) extends Record { // Emulate a Bundle with elements abcde or ad depending on params.hasBCE private val optA = Some (Decoupled(new TLBundleA(params))) private val optB = params.hasBCE.option(Flipped(Decoupled(new TLBundleB(params)))) private val optC = params.hasBCE.option(Decoupled(new TLBundleC(params))) private val optD = Some (Flipped(Decoupled(new TLBundleD(params)))) private val optE = params.hasBCE.option(Decoupled(new TLBundleE(params))) def a: DecoupledIO[TLBundleA] = optA.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleA(params))))) def b: DecoupledIO[TLBundleB] = optB.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleB(params))))) def c: DecoupledIO[TLBundleC] = optC.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleC(params))))) def d: DecoupledIO[TLBundleD] = optD.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleD(params))))) def e: DecoupledIO[TLBundleE] = optE.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleE(params))))) val elements = if (params.hasBCE) ListMap("e" -> e, "d" -> d, "c" -> c, "b" -> b, "a" -> a) else ListMap("d" -> d, "a" -> a) def tieoff(): Unit = { DataMirror.specifiedDirectionOf(a.ready) match { case SpecifiedDirection.Input => a.ready := false.B c.ready := false.B e.ready := false.B b.valid := false.B d.valid := false.B case SpecifiedDirection.Output => a.valid := false.B c.valid := false.B e.valid := false.B b.ready := false.B d.ready := false.B case _ => } } } object TLBundle { def apply(params: TLBundleParameters) = new TLBundle(params) } class TLAsyncBundleBase(val params: TLAsyncBundleParameters) extends Bundle class TLAsyncBundle(params: TLAsyncBundleParameters) extends TLAsyncBundleBase(params) { val a = new AsyncBundle(new TLBundleA(params.base), params.async) val b = Flipped(new AsyncBundle(new TLBundleB(params.base), params.async)) val c = new AsyncBundle(new TLBundleC(params.base), params.async) val d = Flipped(new AsyncBundle(new TLBundleD(params.base), params.async)) val e = new AsyncBundle(new TLBundleE(params.base), params.async) } class TLRationalBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = RationalIO(new TLBundleA(params)) val b = Flipped(RationalIO(new TLBundleB(params))) val c = RationalIO(new TLBundleC(params)) val d = Flipped(RationalIO(new TLBundleD(params))) val e = RationalIO(new TLBundleE(params)) } class TLCreditedBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = CreditedIO(new TLBundleA(params)) val b = Flipped(CreditedIO(new TLBundleB(params))) val c = CreditedIO(new TLBundleC(params)) val d = Flipped(CreditedIO(new TLBundleD(params))) val e = CreditedIO(new TLBundleE(params)) } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.nodes._ import freechips.rocketchip.diplomacy.{ AddressDecoder, AddressSet, BufferParams, DirectedBuffers, IdMap, IdMapEntry, IdRange, RegionType, TransferSizes } import freechips.rocketchip.resources.{Resource, ResourceAddress, ResourcePermissions} import freechips.rocketchip.util.{ AsyncQueueParams, BundleField, BundleFieldBase, BundleKeyBase, CreditedDelay, groupByIntoSeq, RationalDirection, SimpleProduct } import scala.math.max //These transfer sizes describe requests issued from masters on the A channel that will be responded by slaves on the D channel case class TLMasterToSlaveTransferSizes( // Supports both Acquire+Release of the following two sizes: acquireT: TransferSizes = TransferSizes.none, acquireB: TransferSizes = TransferSizes.none, arithmetic: TransferSizes = TransferSizes.none, logical: TransferSizes = TransferSizes.none, get: TransferSizes = TransferSizes.none, putFull: TransferSizes = TransferSizes.none, putPartial: TransferSizes = TransferSizes.none, hint: TransferSizes = TransferSizes.none) extends TLCommonTransferSizes { def intersect(rhs: TLMasterToSlaveTransferSizes) = TLMasterToSlaveTransferSizes( acquireT = acquireT .intersect(rhs.acquireT), acquireB = acquireB .intersect(rhs.acquireB), arithmetic = arithmetic.intersect(rhs.arithmetic), logical = logical .intersect(rhs.logical), get = get .intersect(rhs.get), putFull = putFull .intersect(rhs.putFull), putPartial = putPartial.intersect(rhs.putPartial), hint = hint .intersect(rhs.hint)) def mincover(rhs: TLMasterToSlaveTransferSizes) = TLMasterToSlaveTransferSizes( acquireT = acquireT .mincover(rhs.acquireT), acquireB = acquireB .mincover(rhs.acquireB), arithmetic = arithmetic.mincover(rhs.arithmetic), logical = logical .mincover(rhs.logical), get = get .mincover(rhs.get), putFull = putFull .mincover(rhs.putFull), putPartial = putPartial.mincover(rhs.putPartial), hint = hint .mincover(rhs.hint)) // Reduce rendering to a simple yes/no per field override def toString = { def str(x: TransferSizes, flag: String) = if (x.none) "" else flag def flags = Vector( str(acquireT, "T"), str(acquireB, "B"), str(arithmetic, "A"), str(logical, "L"), str(get, "G"), str(putFull, "F"), str(putPartial, "P"), str(hint, "H")) flags.mkString } // Prints out the actual information in a user readable way def infoString = { s"""acquireT = ${acquireT} |acquireB = ${acquireB} |arithmetic = ${arithmetic} |logical = ${logical} |get = ${get} |putFull = ${putFull} |putPartial = ${putPartial} |hint = ${hint} | |""".stripMargin } } object TLMasterToSlaveTransferSizes { def unknownEmits = TLMasterToSlaveTransferSizes( acquireT = TransferSizes(1, 4096), acquireB = TransferSizes(1, 4096), arithmetic = TransferSizes(1, 4096), logical = TransferSizes(1, 4096), get = TransferSizes(1, 4096), putFull = TransferSizes(1, 4096), putPartial = TransferSizes(1, 4096), hint = TransferSizes(1, 4096)) def unknownSupports = TLMasterToSlaveTransferSizes() } //These transfer sizes describe requests issued from slaves on the B channel that will be responded by masters on the C channel case class TLSlaveToMasterTransferSizes( probe: TransferSizes = TransferSizes.none, arithmetic: TransferSizes = TransferSizes.none, logical: TransferSizes = TransferSizes.none, get: TransferSizes = TransferSizes.none, putFull: TransferSizes = TransferSizes.none, putPartial: TransferSizes = TransferSizes.none, hint: TransferSizes = TransferSizes.none ) extends TLCommonTransferSizes { def intersect(rhs: TLSlaveToMasterTransferSizes) = TLSlaveToMasterTransferSizes( probe = probe .intersect(rhs.probe), arithmetic = arithmetic.intersect(rhs.arithmetic), logical = logical .intersect(rhs.logical), get = get .intersect(rhs.get), putFull = putFull .intersect(rhs.putFull), putPartial = putPartial.intersect(rhs.putPartial), hint = hint .intersect(rhs.hint) ) def mincover(rhs: TLSlaveToMasterTransferSizes) = TLSlaveToMasterTransferSizes( probe = probe .mincover(rhs.probe), arithmetic = arithmetic.mincover(rhs.arithmetic), logical = logical .mincover(rhs.logical), get = get .mincover(rhs.get), putFull = putFull .mincover(rhs.putFull), putPartial = putPartial.mincover(rhs.putPartial), hint = hint .mincover(rhs.hint) ) // Reduce rendering to a simple yes/no per field override def toString = { def str(x: TransferSizes, flag: String) = if (x.none) "" else flag def flags = Vector( str(probe, "P"), str(arithmetic, "A"), str(logical, "L"), str(get, "G"), str(putFull, "F"), str(putPartial, "P"), str(hint, "H")) flags.mkString } // Prints out the actual information in a user readable way def infoString = { s"""probe = ${probe} |arithmetic = ${arithmetic} |logical = ${logical} |get = ${get} |putFull = ${putFull} |putPartial = ${putPartial} |hint = ${hint} | |""".stripMargin } } object TLSlaveToMasterTransferSizes { def unknownEmits = TLSlaveToMasterTransferSizes( arithmetic = TransferSizes(1, 4096), logical = TransferSizes(1, 4096), get = TransferSizes(1, 4096), putFull = TransferSizes(1, 4096), putPartial = TransferSizes(1, 4096), hint = TransferSizes(1, 4096), probe = TransferSizes(1, 4096)) def unknownSupports = TLSlaveToMasterTransferSizes() } trait TLCommonTransferSizes { def arithmetic: TransferSizes def logical: TransferSizes def get: TransferSizes def putFull: TransferSizes def putPartial: TransferSizes def hint: TransferSizes } class TLSlaveParameters private( val nodePath: Seq[BaseNode], val resources: Seq[Resource], setName: Option[String], val address: Seq[AddressSet], val regionType: RegionType.T, val executable: Boolean, val fifoId: Option[Int], val supports: TLMasterToSlaveTransferSizes, val emits: TLSlaveToMasterTransferSizes, // By default, slaves are forbidden from issuing 'denied' responses (it prevents Fragmentation) val alwaysGrantsT: Boolean, // typically only true for CacheCork'd read-write devices; dual: neverReleaseData // If fifoId=Some, all accesses sent to the same fifoId are executed and ACK'd in FIFO order // Note: you can only rely on this FIFO behaviour if your TLMasterParameters include requestFifo val mayDenyGet: Boolean, // applies to: AccessAckData, GrantData val mayDenyPut: Boolean) // applies to: AccessAck, Grant, HintAck // ReleaseAck may NEVER be denied extends SimpleProduct { def sortedAddress = address.sorted override def canEqual(that: Any): Boolean = that.isInstanceOf[TLSlaveParameters] override def productPrefix = "TLSlaveParameters" // We intentionally omit nodePath for equality testing / formatting def productArity: Int = 11 def productElement(n: Int): Any = n match { case 0 => name case 1 => address case 2 => resources case 3 => regionType case 4 => executable case 5 => fifoId case 6 => supports case 7 => emits case 8 => alwaysGrantsT case 9 => mayDenyGet case 10 => mayDenyPut case _ => throw new IndexOutOfBoundsException(n.toString) } def supportsAcquireT: TransferSizes = supports.acquireT def supportsAcquireB: TransferSizes = supports.acquireB def supportsArithmetic: TransferSizes = supports.arithmetic def supportsLogical: TransferSizes = supports.logical def supportsGet: TransferSizes = supports.get def supportsPutFull: TransferSizes = supports.putFull def supportsPutPartial: TransferSizes = supports.putPartial def supportsHint: TransferSizes = supports.hint require (!address.isEmpty, "Address cannot be empty") address.foreach { a => require (a.finite, "Address must be finite") } address.combinations(2).foreach { case Seq(x,y) => require (!x.overlaps(y), s"$x and $y overlap.") } require (supportsPutFull.contains(supportsPutPartial), s"PutFull($supportsPutFull) < PutPartial($supportsPutPartial)") require (supportsPutFull.contains(supportsArithmetic), s"PutFull($supportsPutFull) < Arithmetic($supportsArithmetic)") require (supportsPutFull.contains(supportsLogical), s"PutFull($supportsPutFull) < Logical($supportsLogical)") require (supportsGet.contains(supportsArithmetic), s"Get($supportsGet) < Arithmetic($supportsArithmetic)") require (supportsGet.contains(supportsLogical), s"Get($supportsGet) < Logical($supportsLogical)") require (supportsAcquireB.contains(supportsAcquireT), s"AcquireB($supportsAcquireB) < AcquireT($supportsAcquireT)") require (!alwaysGrantsT || supportsAcquireT, s"Must supportAcquireT if promising to always grantT") // Make sure that the regionType agrees with the capabilities require (!supportsAcquireB || regionType >= RegionType.UNCACHED) // acquire -> uncached, tracked, cached require (regionType <= RegionType.UNCACHED || supportsAcquireB) // tracked, cached -> acquire require (regionType != RegionType.UNCACHED || supportsGet) // uncached -> supportsGet val name = setName.orElse(nodePath.lastOption.map(_.lazyModule.name)).getOrElse("disconnected") val maxTransfer = List( // Largest supported transfer of all types supportsAcquireT.max, supportsAcquireB.max, supportsArithmetic.max, supportsLogical.max, supportsGet.max, supportsPutFull.max, supportsPutPartial.max).max val maxAddress = address.map(_.max).max val minAlignment = address.map(_.alignment).min // The device had better not support a transfer larger than its alignment require (minAlignment >= maxTransfer, s"Bad $address: minAlignment ($minAlignment) must be >= maxTransfer ($maxTransfer)") def toResource: ResourceAddress = { ResourceAddress(address, ResourcePermissions( r = supportsAcquireB || supportsGet, w = supportsAcquireT || supportsPutFull, x = executable, c = supportsAcquireB, a = supportsArithmetic && supportsLogical)) } def findTreeViolation() = nodePath.find { case _: MixedAdapterNode[_, _, _, _, _, _, _, _] => false case _: SinkNode[_, _, _, _, _] => false case node => node.inputs.size != 1 } def isTree = findTreeViolation() == None def infoString = { s"""Slave Name = ${name} |Slave Address = ${address} |supports = ${supports.infoString} | |""".stripMargin } def v1copy( address: Seq[AddressSet] = address, resources: Seq[Resource] = resources, regionType: RegionType.T = regionType, executable: Boolean = executable, nodePath: Seq[BaseNode] = nodePath, supportsAcquireT: TransferSizes = supports.acquireT, supportsAcquireB: TransferSizes = supports.acquireB, supportsArithmetic: TransferSizes = supports.arithmetic, supportsLogical: TransferSizes = supports.logical, supportsGet: TransferSizes = supports.get, supportsPutFull: TransferSizes = supports.putFull, supportsPutPartial: TransferSizes = supports.putPartial, supportsHint: TransferSizes = supports.hint, mayDenyGet: Boolean = mayDenyGet, mayDenyPut: Boolean = mayDenyPut, alwaysGrantsT: Boolean = alwaysGrantsT, fifoId: Option[Int] = fifoId) = { new TLSlaveParameters( setName = setName, address = address, resources = resources, regionType = regionType, executable = executable, nodePath = nodePath, supports = TLMasterToSlaveTransferSizes( acquireT = supportsAcquireT, acquireB = supportsAcquireB, arithmetic = supportsArithmetic, logical = supportsLogical, get = supportsGet, putFull = supportsPutFull, putPartial = supportsPutPartial, hint = supportsHint), emits = emits, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut, alwaysGrantsT = alwaysGrantsT, fifoId = fifoId) } def v2copy( nodePath: Seq[BaseNode] = nodePath, resources: Seq[Resource] = resources, name: Option[String] = setName, address: Seq[AddressSet] = address, regionType: RegionType.T = regionType, executable: Boolean = executable, fifoId: Option[Int] = fifoId, supports: TLMasterToSlaveTransferSizes = supports, emits: TLSlaveToMasterTransferSizes = emits, alwaysGrantsT: Boolean = alwaysGrantsT, mayDenyGet: Boolean = mayDenyGet, mayDenyPut: Boolean = mayDenyPut) = { new TLSlaveParameters( nodePath = nodePath, resources = resources, setName = name, address = address, regionType = regionType, executable = executable, fifoId = fifoId, supports = supports, emits = emits, alwaysGrantsT = alwaysGrantsT, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut) } @deprecated("Use v1copy instead of copy","") def copy( address: Seq[AddressSet] = address, resources: Seq[Resource] = resources, regionType: RegionType.T = regionType, executable: Boolean = executable, nodePath: Seq[BaseNode] = nodePath, supportsAcquireT: TransferSizes = supports.acquireT, supportsAcquireB: TransferSizes = supports.acquireB, supportsArithmetic: TransferSizes = supports.arithmetic, supportsLogical: TransferSizes = supports.logical, supportsGet: TransferSizes = supports.get, supportsPutFull: TransferSizes = supports.putFull, supportsPutPartial: TransferSizes = supports.putPartial, supportsHint: TransferSizes = supports.hint, mayDenyGet: Boolean = mayDenyGet, mayDenyPut: Boolean = mayDenyPut, alwaysGrantsT: Boolean = alwaysGrantsT, fifoId: Option[Int] = fifoId) = { v1copy( address = address, resources = resources, regionType = regionType, executable = executable, nodePath = nodePath, supportsAcquireT = supportsAcquireT, supportsAcquireB = supportsAcquireB, supportsArithmetic = supportsArithmetic, supportsLogical = supportsLogical, supportsGet = supportsGet, supportsPutFull = supportsPutFull, supportsPutPartial = supportsPutPartial, supportsHint = supportsHint, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut, alwaysGrantsT = alwaysGrantsT, fifoId = fifoId) } } object TLSlaveParameters { def v1( address: Seq[AddressSet], resources: Seq[Resource] = Seq(), regionType: RegionType.T = RegionType.GET_EFFECTS, executable: Boolean = false, nodePath: Seq[BaseNode] = Seq(), supportsAcquireT: TransferSizes = TransferSizes.none, supportsAcquireB: TransferSizes = TransferSizes.none, supportsArithmetic: TransferSizes = TransferSizes.none, supportsLogical: TransferSizes = TransferSizes.none, supportsGet: TransferSizes = TransferSizes.none, supportsPutFull: TransferSizes = TransferSizes.none, supportsPutPartial: TransferSizes = TransferSizes.none, supportsHint: TransferSizes = TransferSizes.none, mayDenyGet: Boolean = false, mayDenyPut: Boolean = false, alwaysGrantsT: Boolean = false, fifoId: Option[Int] = None) = { new TLSlaveParameters( setName = None, address = address, resources = resources, regionType = regionType, executable = executable, nodePath = nodePath, supports = TLMasterToSlaveTransferSizes( acquireT = supportsAcquireT, acquireB = supportsAcquireB, arithmetic = supportsArithmetic, logical = supportsLogical, get = supportsGet, putFull = supportsPutFull, putPartial = supportsPutPartial, hint = supportsHint), emits = TLSlaveToMasterTransferSizes.unknownEmits, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut, alwaysGrantsT = alwaysGrantsT, fifoId = fifoId) } def v2( address: Seq[AddressSet], nodePath: Seq[BaseNode] = Seq(), resources: Seq[Resource] = Seq(), name: Option[String] = None, regionType: RegionType.T = RegionType.GET_EFFECTS, executable: Boolean = false, fifoId: Option[Int] = None, supports: TLMasterToSlaveTransferSizes = TLMasterToSlaveTransferSizes.unknownSupports, emits: TLSlaveToMasterTransferSizes = TLSlaveToMasterTransferSizes.unknownEmits, alwaysGrantsT: Boolean = false, mayDenyGet: Boolean = false, mayDenyPut: Boolean = false) = { new TLSlaveParameters( nodePath = nodePath, resources = resources, setName = name, address = address, regionType = regionType, executable = executable, fifoId = fifoId, supports = supports, emits = emits, alwaysGrantsT = alwaysGrantsT, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut) } } object TLManagerParameters { @deprecated("Use TLSlaveParameters.v1 instead of TLManagerParameters","") def apply( address: Seq[AddressSet], resources: Seq[Resource] = Seq(), regionType: RegionType.T = RegionType.GET_EFFECTS, executable: Boolean = false, nodePath: Seq[BaseNode] = Seq(), supportsAcquireT: TransferSizes = TransferSizes.none, supportsAcquireB: TransferSizes = TransferSizes.none, supportsArithmetic: TransferSizes = TransferSizes.none, supportsLogical: TransferSizes = TransferSizes.none, supportsGet: TransferSizes = TransferSizes.none, supportsPutFull: TransferSizes = TransferSizes.none, supportsPutPartial: TransferSizes = TransferSizes.none, supportsHint: TransferSizes = TransferSizes.none, mayDenyGet: Boolean = false, mayDenyPut: Boolean = false, alwaysGrantsT: Boolean = false, fifoId: Option[Int] = None) = TLSlaveParameters.v1( address, resources, regionType, executable, nodePath, supportsAcquireT, supportsAcquireB, supportsArithmetic, supportsLogical, supportsGet, supportsPutFull, supportsPutPartial, supportsHint, mayDenyGet, mayDenyPut, alwaysGrantsT, fifoId, ) } case class TLChannelBeatBytes(a: Option[Int], b: Option[Int], c: Option[Int], d: Option[Int]) { def members = Seq(a, b, c, d) members.collect { case Some(beatBytes) => require (isPow2(beatBytes), "Data channel width must be a power of 2") } } object TLChannelBeatBytes{ def apply(beatBytes: Int): TLChannelBeatBytes = TLChannelBeatBytes( Some(beatBytes), Some(beatBytes), Some(beatBytes), Some(beatBytes)) def apply(): TLChannelBeatBytes = TLChannelBeatBytes( None, None, None, None) } class TLSlavePortParameters private( val slaves: Seq[TLSlaveParameters], val channelBytes: TLChannelBeatBytes, val endSinkId: Int, val minLatency: Int, val responseFields: Seq[BundleFieldBase], val requestKeys: Seq[BundleKeyBase]) extends SimpleProduct { def sortedSlaves = slaves.sortBy(_.sortedAddress.head) override def canEqual(that: Any): Boolean = that.isInstanceOf[TLSlavePortParameters] override def productPrefix = "TLSlavePortParameters" def productArity: Int = 6 def productElement(n: Int): Any = n match { case 0 => slaves case 1 => channelBytes case 2 => endSinkId case 3 => minLatency case 4 => responseFields case 5 => requestKeys case _ => throw new IndexOutOfBoundsException(n.toString) } require (!slaves.isEmpty, "Slave ports must have slaves") require (endSinkId >= 0, "Sink ids cannot be negative") require (minLatency >= 0, "Minimum required latency cannot be negative") // Using this API implies you cannot handle mixed-width busses def beatBytes = { channelBytes.members.foreach { width => require (width.isDefined && width == channelBytes.a) } channelBytes.a.get } // TODO this should be deprecated def managers = slaves def requireFifo(policy: TLFIFOFixer.Policy = TLFIFOFixer.allFIFO) = { val relevant = slaves.filter(m => policy(m)) relevant.foreach { m => require(m.fifoId == relevant.head.fifoId, s"${m.name} had fifoId ${m.fifoId}, which was not homogeneous (${slaves.map(s => (s.name, s.fifoId))}) ") } } // Bounds on required sizes def maxAddress = slaves.map(_.maxAddress).max def maxTransfer = slaves.map(_.maxTransfer).max def mayDenyGet = slaves.exists(_.mayDenyGet) def mayDenyPut = slaves.exists(_.mayDenyPut) // Diplomatically determined operation sizes emitted by all outward Slaves // as opposed to emits* which generate circuitry to check which specific addresses val allEmitClaims = slaves.map(_.emits).reduce( _ intersect _) // Operation Emitted by at least one outward Slaves // as opposed to emits* which generate circuitry to check which specific addresses val anyEmitClaims = slaves.map(_.emits).reduce(_ mincover _) // Diplomatically determined operation sizes supported by all outward Slaves // as opposed to supports* which generate circuitry to check which specific addresses val allSupportClaims = slaves.map(_.supports).reduce( _ intersect _) val allSupportAcquireT = allSupportClaims.acquireT val allSupportAcquireB = allSupportClaims.acquireB val allSupportArithmetic = allSupportClaims.arithmetic val allSupportLogical = allSupportClaims.logical val allSupportGet = allSupportClaims.get val allSupportPutFull = allSupportClaims.putFull val allSupportPutPartial = allSupportClaims.putPartial val allSupportHint = allSupportClaims.hint // Operation supported by at least one outward Slaves // as opposed to supports* which generate circuitry to check which specific addresses val anySupportClaims = slaves.map(_.supports).reduce(_ mincover _) val anySupportAcquireT = !anySupportClaims.acquireT.none val anySupportAcquireB = !anySupportClaims.acquireB.none val anySupportArithmetic = !anySupportClaims.arithmetic.none val anySupportLogical = !anySupportClaims.logical.none val anySupportGet = !anySupportClaims.get.none val anySupportPutFull = !anySupportClaims.putFull.none val anySupportPutPartial = !anySupportClaims.putPartial.none val anySupportHint = !anySupportClaims.hint.none // Supporting Acquire means being routable for GrantAck require ((endSinkId == 0) == !anySupportAcquireB) // These return Option[TLSlaveParameters] for your convenience def find(address: BigInt) = slaves.find(_.address.exists(_.contains(address))) // The safe version will check the entire address def findSafe(address: UInt) = VecInit(sortedSlaves.map(_.address.map(_.contains(address)).reduce(_ || _))) // The fast version assumes the address is valid (you probably want fastProperty instead of this function) def findFast(address: UInt) = { val routingMask = AddressDecoder(slaves.map(_.address)) VecInit(sortedSlaves.map(_.address.map(_.widen(~routingMask)).distinct.map(_.contains(address)).reduce(_ || _))) } // Compute the simplest AddressSets that decide a key def fastPropertyGroup[K](p: TLSlaveParameters => K): Seq[(K, Seq[AddressSet])] = { val groups = groupByIntoSeq(sortedSlaves.map(m => (p(m), m.address)))( _._1).map { case (k, vs) => k -> vs.flatMap(_._2) } val reductionMask = AddressDecoder(groups.map(_._2)) groups.map { case (k, seq) => k -> AddressSet.unify(seq.map(_.widen(~reductionMask)).distinct) } } // Select a property def fastProperty[K, D <: Data](address: UInt, p: TLSlaveParameters => K, d: K => D): D = Mux1H(fastPropertyGroup(p).map { case (v, a) => (a.map(_.contains(address)).reduce(_||_), d(v)) }) // Note: returns the actual fifoId + 1 or 0 if None def findFifoIdFast(address: UInt) = fastProperty(address, _.fifoId.map(_+1).getOrElse(0), (i:Int) => i.U) def hasFifoIdFast(address: UInt) = fastProperty(address, _.fifoId.isDefined, (b:Boolean) => b.B) // Does this Port manage this ID/address? def containsSafe(address: UInt) = findSafe(address).reduce(_ || _) private def addressHelper( // setting safe to false indicates that all addresses are expected to be legal, which might reduce circuit complexity safe: Boolean, // member filters out the sizes being checked based on the opcode being emitted or supported member: TLSlaveParameters => TransferSizes, address: UInt, lgSize: UInt, // range provides a limit on the sizes that are expected to be evaluated, which might reduce circuit complexity range: Option[TransferSizes]): Bool = { // trim reduces circuit complexity by intersecting checked sizes with the range argument def trim(x: TransferSizes) = range.map(_.intersect(x)).getOrElse(x) // groupBy returns an unordered map, convert back to Seq and sort the result for determinism // groupByIntoSeq is turning slaves into trimmed membership sizes // We are grouping all the slaves by their transfer size where // if they support the trimmed size then // member is the type of transfer that you are looking for (What you are trying to filter on) // When you consider membership, you are trimming the sizes to only the ones that you care about // you are filtering the slaves based on both whether they support a particular opcode and the size // Grouping the slaves based on the actual transfer size range they support // intersecting the range and checking their membership // FOR SUPPORTCASES instead of returning the list of slaves, // you are returning a map from transfer size to the set of // address sets that are supported for that transfer size // find all the slaves that support a certain type of operation and then group their addresses by the supported size // for every size there could be multiple address ranges // safety is a trade off between checking between all possible addresses vs only the addresses // that are known to have supported sizes // the trade off is 'checking all addresses is a more expensive circuit but will always give you // the right answer even if you give it an illegal address' // the not safe version is a cheaper circuit but if you give it an illegal address then it might produce the wrong answer // fast presumes address legality // This groupByIntoSeq deterministically groups all address sets for which a given `member` transfer size applies. // In the resulting Map of cases, the keys are transfer sizes and the values are all address sets which emit or support that size. val supportCases = groupByIntoSeq(slaves)(m => trim(member(m))).map { case (k: TransferSizes, vs: Seq[TLSlaveParameters]) => k -> vs.flatMap(_.address) } // safe produces a circuit that compares against all possible addresses, // whereas fast presumes that the address is legal but uses an efficient address decoder val mask = if (safe) ~BigInt(0) else AddressDecoder(supportCases.map(_._2)) // Simplified creates the most concise possible representation of each cases' address sets based on the mask. val simplified = supportCases.map { case (k, seq) => k -> AddressSet.unify(seq.map(_.widen(~mask)).distinct) } simplified.map { case (s, a) => // s is a size, you are checking for this size either the size of the operation is in s // We return an or-reduction of all the cases, checking whether any contains both the dynamic size and dynamic address on the wire. ((Some(s) == range).B || s.containsLg(lgSize)) && a.map(_.contains(address)).reduce(_||_) }.foldLeft(false.B)(_||_) } def supportsAcquireTSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.acquireT, address, lgSize, range) def supportsAcquireBSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.acquireB, address, lgSize, range) def supportsArithmeticSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.arithmetic, address, lgSize, range) def supportsLogicalSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.logical, address, lgSize, range) def supportsGetSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.get, address, lgSize, range) def supportsPutFullSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.putFull, address, lgSize, range) def supportsPutPartialSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.putPartial, address, lgSize, range) def supportsHintSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.hint, address, lgSize, range) def supportsAcquireTFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.acquireT, address, lgSize, range) def supportsAcquireBFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.acquireB, address, lgSize, range) def supportsArithmeticFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.arithmetic, address, lgSize, range) def supportsLogicalFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.logical, address, lgSize, range) def supportsGetFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.get, address, lgSize, range) def supportsPutFullFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.putFull, address, lgSize, range) def supportsPutPartialFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.putPartial, address, lgSize, range) def supportsHintFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.hint, address, lgSize, range) def emitsProbeSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.probe, address, lgSize, range) def emitsArithmeticSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.arithmetic, address, lgSize, range) def emitsLogicalSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.logical, address, lgSize, range) def emitsGetSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.get, address, lgSize, range) def emitsPutFullSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.putFull, address, lgSize, range) def emitsPutPartialSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.putPartial, address, lgSize, range) def emitsHintSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.hint, address, lgSize, range) def findTreeViolation() = slaves.flatMap(_.findTreeViolation()).headOption def isTree = !slaves.exists(!_.isTree) def infoString = "Slave Port Beatbytes = " + beatBytes + "\n" + "Slave Port MinLatency = " + minLatency + "\n\n" + slaves.map(_.infoString).mkString def v1copy( managers: Seq[TLSlaveParameters] = slaves, beatBytes: Int = -1, endSinkId: Int = endSinkId, minLatency: Int = minLatency, responseFields: Seq[BundleFieldBase] = responseFields, requestKeys: Seq[BundleKeyBase] = requestKeys) = { new TLSlavePortParameters( slaves = managers, channelBytes = if (beatBytes != -1) TLChannelBeatBytes(beatBytes) else channelBytes, endSinkId = endSinkId, minLatency = minLatency, responseFields = responseFields, requestKeys = requestKeys) } def v2copy( slaves: Seq[TLSlaveParameters] = slaves, channelBytes: TLChannelBeatBytes = channelBytes, endSinkId: Int = endSinkId, minLatency: Int = minLatency, responseFields: Seq[BundleFieldBase] = responseFields, requestKeys: Seq[BundleKeyBase] = requestKeys) = { new TLSlavePortParameters( slaves = slaves, channelBytes = channelBytes, endSinkId = endSinkId, minLatency = minLatency, responseFields = responseFields, requestKeys = requestKeys) } @deprecated("Use v1copy instead of copy","") def copy( managers: Seq[TLSlaveParameters] = slaves, beatBytes: Int = -1, endSinkId: Int = endSinkId, minLatency: Int = minLatency, responseFields: Seq[BundleFieldBase] = responseFields, requestKeys: Seq[BundleKeyBase] = requestKeys) = { v1copy( managers, beatBytes, endSinkId, minLatency, responseFields, requestKeys) } } object TLSlavePortParameters { def v1( managers: Seq[TLSlaveParameters], beatBytes: Int, endSinkId: Int = 0, minLatency: Int = 0, responseFields: Seq[BundleFieldBase] = Nil, requestKeys: Seq[BundleKeyBase] = Nil) = { new TLSlavePortParameters( slaves = managers, channelBytes = TLChannelBeatBytes(beatBytes), endSinkId = endSinkId, minLatency = minLatency, responseFields = responseFields, requestKeys = requestKeys) } } object TLManagerPortParameters { @deprecated("Use TLSlavePortParameters.v1 instead of TLManagerPortParameters","") def apply( managers: Seq[TLSlaveParameters], beatBytes: Int, endSinkId: Int = 0, minLatency: Int = 0, responseFields: Seq[BundleFieldBase] = Nil, requestKeys: Seq[BundleKeyBase] = Nil) = { TLSlavePortParameters.v1( managers, beatBytes, endSinkId, minLatency, responseFields, requestKeys) } } class TLMasterParameters private( val nodePath: Seq[BaseNode], val resources: Seq[Resource], val name: String, val visibility: Seq[AddressSet], val unusedRegionTypes: Set[RegionType.T], val executesOnly: Boolean, val requestFifo: Boolean, // only a request, not a requirement. applies to A, not C. val supports: TLSlaveToMasterTransferSizes, val emits: TLMasterToSlaveTransferSizes, val neverReleasesData: Boolean, val sourceId: IdRange) extends SimpleProduct { override def canEqual(that: Any): Boolean = that.isInstanceOf[TLMasterParameters] override def productPrefix = "TLMasterParameters" // We intentionally omit nodePath for equality testing / formatting def productArity: Int = 10 def productElement(n: Int): Any = n match { case 0 => name case 1 => sourceId case 2 => resources case 3 => visibility case 4 => unusedRegionTypes case 5 => executesOnly case 6 => requestFifo case 7 => supports case 8 => emits case 9 => neverReleasesData case _ => throw new IndexOutOfBoundsException(n.toString) } require (!sourceId.isEmpty) require (!visibility.isEmpty) require (supports.putFull.contains(supports.putPartial)) // We only support these operations if we support Probe (ie: we're a cache) require (supports.probe.contains(supports.arithmetic)) require (supports.probe.contains(supports.logical)) require (supports.probe.contains(supports.get)) require (supports.probe.contains(supports.putFull)) require (supports.probe.contains(supports.putPartial)) require (supports.probe.contains(supports.hint)) visibility.combinations(2).foreach { case Seq(x,y) => require (!x.overlaps(y), s"$x and $y overlap.") } val maxTransfer = List( supports.probe.max, supports.arithmetic.max, supports.logical.max, supports.get.max, supports.putFull.max, supports.putPartial.max).max def infoString = { s"""Master Name = ${name} |visibility = ${visibility} |emits = ${emits.infoString} |sourceId = ${sourceId} | |""".stripMargin } def v1copy( name: String = name, sourceId: IdRange = sourceId, nodePath: Seq[BaseNode] = nodePath, requestFifo: Boolean = requestFifo, visibility: Seq[AddressSet] = visibility, supportsProbe: TransferSizes = supports.probe, supportsArithmetic: TransferSizes = supports.arithmetic, supportsLogical: TransferSizes = supports.logical, supportsGet: TransferSizes = supports.get, supportsPutFull: TransferSizes = supports.putFull, supportsPutPartial: TransferSizes = supports.putPartial, supportsHint: TransferSizes = supports.hint) = { new TLMasterParameters( nodePath = nodePath, resources = this.resources, name = name, visibility = visibility, unusedRegionTypes = this.unusedRegionTypes, executesOnly = this.executesOnly, requestFifo = requestFifo, supports = TLSlaveToMasterTransferSizes( probe = supportsProbe, arithmetic = supportsArithmetic, logical = supportsLogical, get = supportsGet, putFull = supportsPutFull, putPartial = supportsPutPartial, hint = supportsHint), emits = this.emits, neverReleasesData = this.neverReleasesData, sourceId = sourceId) } def v2copy( nodePath: Seq[BaseNode] = nodePath, resources: Seq[Resource] = resources, name: String = name, visibility: Seq[AddressSet] = visibility, unusedRegionTypes: Set[RegionType.T] = unusedRegionTypes, executesOnly: Boolean = executesOnly, requestFifo: Boolean = requestFifo, supports: TLSlaveToMasterTransferSizes = supports, emits: TLMasterToSlaveTransferSizes = emits, neverReleasesData: Boolean = neverReleasesData, sourceId: IdRange = sourceId) = { new TLMasterParameters( nodePath = nodePath, resources = resources, name = name, visibility = visibility, unusedRegionTypes = unusedRegionTypes, executesOnly = executesOnly, requestFifo = requestFifo, supports = supports, emits = emits, neverReleasesData = neverReleasesData, sourceId = sourceId) } @deprecated("Use v1copy instead of copy","") def copy( name: String = name, sourceId: IdRange = sourceId, nodePath: Seq[BaseNode] = nodePath, requestFifo: Boolean = requestFifo, visibility: Seq[AddressSet] = visibility, supportsProbe: TransferSizes = supports.probe, supportsArithmetic: TransferSizes = supports.arithmetic, supportsLogical: TransferSizes = supports.logical, supportsGet: TransferSizes = supports.get, supportsPutFull: TransferSizes = supports.putFull, supportsPutPartial: TransferSizes = supports.putPartial, supportsHint: TransferSizes = supports.hint) = { v1copy( name = name, sourceId = sourceId, nodePath = nodePath, requestFifo = requestFifo, visibility = visibility, supportsProbe = supportsProbe, supportsArithmetic = supportsArithmetic, supportsLogical = supportsLogical, supportsGet = supportsGet, supportsPutFull = supportsPutFull, supportsPutPartial = supportsPutPartial, supportsHint = supportsHint) } } object TLMasterParameters { def v1( name: String, sourceId: IdRange = IdRange(0,1), nodePath: Seq[BaseNode] = Seq(), requestFifo: Boolean = false, visibility: Seq[AddressSet] = Seq(AddressSet(0, ~0)), supportsProbe: TransferSizes = TransferSizes.none, supportsArithmetic: TransferSizes = TransferSizes.none, supportsLogical: TransferSizes = TransferSizes.none, supportsGet: TransferSizes = TransferSizes.none, supportsPutFull: TransferSizes = TransferSizes.none, supportsPutPartial: TransferSizes = TransferSizes.none, supportsHint: TransferSizes = TransferSizes.none) = { new TLMasterParameters( nodePath = nodePath, resources = Nil, name = name, visibility = visibility, unusedRegionTypes = Set(), executesOnly = false, requestFifo = requestFifo, supports = TLSlaveToMasterTransferSizes( probe = supportsProbe, arithmetic = supportsArithmetic, logical = supportsLogical, get = supportsGet, putFull = supportsPutFull, putPartial = supportsPutPartial, hint = supportsHint), emits = TLMasterToSlaveTransferSizes.unknownEmits, neverReleasesData = false, sourceId = sourceId) } def v2( nodePath: Seq[BaseNode] = Seq(), resources: Seq[Resource] = Nil, name: String, visibility: Seq[AddressSet] = Seq(AddressSet(0, ~0)), unusedRegionTypes: Set[RegionType.T] = Set(), executesOnly: Boolean = false, requestFifo: Boolean = false, supports: TLSlaveToMasterTransferSizes = TLSlaveToMasterTransferSizes.unknownSupports, emits: TLMasterToSlaveTransferSizes = TLMasterToSlaveTransferSizes.unknownEmits, neverReleasesData: Boolean = false, sourceId: IdRange = IdRange(0,1)) = { new TLMasterParameters( nodePath = nodePath, resources = resources, name = name, visibility = visibility, unusedRegionTypes = unusedRegionTypes, executesOnly = executesOnly, requestFifo = requestFifo, supports = supports, emits = emits, neverReleasesData = neverReleasesData, sourceId = sourceId) } } object TLClientParameters { @deprecated("Use TLMasterParameters.v1 instead of TLClientParameters","") def apply( name: String, sourceId: IdRange = IdRange(0,1), nodePath: Seq[BaseNode] = Seq(), requestFifo: Boolean = false, visibility: Seq[AddressSet] = Seq(AddressSet.everything), supportsProbe: TransferSizes = TransferSizes.none, supportsArithmetic: TransferSizes = TransferSizes.none, supportsLogical: TransferSizes = TransferSizes.none, supportsGet: TransferSizes = TransferSizes.none, supportsPutFull: TransferSizes = TransferSizes.none, supportsPutPartial: TransferSizes = TransferSizes.none, supportsHint: TransferSizes = TransferSizes.none) = { TLMasterParameters.v1( name = name, sourceId = sourceId, nodePath = nodePath, requestFifo = requestFifo, visibility = visibility, supportsProbe = supportsProbe, supportsArithmetic = supportsArithmetic, supportsLogical = supportsLogical, supportsGet = supportsGet, supportsPutFull = supportsPutFull, supportsPutPartial = supportsPutPartial, supportsHint = supportsHint) } } class TLMasterPortParameters private( val masters: Seq[TLMasterParameters], val channelBytes: TLChannelBeatBytes, val minLatency: Int, val echoFields: Seq[BundleFieldBase], val requestFields: Seq[BundleFieldBase], val responseKeys: Seq[BundleKeyBase]) extends SimpleProduct { override def canEqual(that: Any): Boolean = that.isInstanceOf[TLMasterPortParameters] override def productPrefix = "TLMasterPortParameters" def productArity: Int = 6 def productElement(n: Int): Any = n match { case 0 => masters case 1 => channelBytes case 2 => minLatency case 3 => echoFields case 4 => requestFields case 5 => responseKeys case _ => throw new IndexOutOfBoundsException(n.toString) } require (!masters.isEmpty) require (minLatency >= 0) def clients = masters // Require disjoint ranges for Ids IdRange.overlaps(masters.map(_.sourceId)).foreach { case (x, y) => require (!x.overlaps(y), s"TLClientParameters.sourceId ${x} overlaps ${y}") } // Bounds on required sizes def endSourceId = masters.map(_.sourceId.end).max def maxTransfer = masters.map(_.maxTransfer).max // The unused sources < endSourceId def unusedSources: Seq[Int] = { val usedSources = masters.map(_.sourceId).sortBy(_.start) ((Seq(0) ++ usedSources.map(_.end)) zip usedSources.map(_.start)) flatMap { case (end, start) => end until start } } // Diplomatically determined operation sizes emitted by all inward Masters // as opposed to emits* which generate circuitry to check which specific addresses val allEmitClaims = masters.map(_.emits).reduce( _ intersect _) // Diplomatically determined operation sizes Emitted by at least one inward Masters // as opposed to emits* which generate circuitry to check which specific addresses val anyEmitClaims = masters.map(_.emits).reduce(_ mincover _) // Diplomatically determined operation sizes supported by all inward Masters // as opposed to supports* which generate circuitry to check which specific addresses val allSupportProbe = masters.map(_.supports.probe) .reduce(_ intersect _) val allSupportArithmetic = masters.map(_.supports.arithmetic).reduce(_ intersect _) val allSupportLogical = masters.map(_.supports.logical) .reduce(_ intersect _) val allSupportGet = masters.map(_.supports.get) .reduce(_ intersect _) val allSupportPutFull = masters.map(_.supports.putFull) .reduce(_ intersect _) val allSupportPutPartial = masters.map(_.supports.putPartial).reduce(_ intersect _) val allSupportHint = masters.map(_.supports.hint) .reduce(_ intersect _) // Diplomatically determined operation sizes supported by at least one master // as opposed to supports* which generate circuitry to check which specific addresses val anySupportProbe = masters.map(!_.supports.probe.none) .reduce(_ || _) val anySupportArithmetic = masters.map(!_.supports.arithmetic.none).reduce(_ || _) val anySupportLogical = masters.map(!_.supports.logical.none) .reduce(_ || _) val anySupportGet = masters.map(!_.supports.get.none) .reduce(_ || _) val anySupportPutFull = masters.map(!_.supports.putFull.none) .reduce(_ || _) val anySupportPutPartial = masters.map(!_.supports.putPartial.none).reduce(_ || _) val anySupportHint = masters.map(!_.supports.hint.none) .reduce(_ || _) // These return Option[TLMasterParameters] for your convenience def find(id: Int) = masters.find(_.sourceId.contains(id)) // Synthesizable lookup methods def find(id: UInt) = VecInit(masters.map(_.sourceId.contains(id))) def contains(id: UInt) = find(id).reduce(_ || _) def requestFifo(id: UInt) = Mux1H(find(id), masters.map(c => c.requestFifo.B)) // Available during RTL runtime, checks to see if (id, size) is supported by the master's (client's) diplomatic parameters private def sourceIdHelper(member: TLMasterParameters => TransferSizes)(id: UInt, lgSize: UInt) = { val allSame = masters.map(member(_) == member(masters(0))).reduce(_ && _) // this if statement is a coarse generalization of the groupBy in the sourceIdHelper2 version; // the case where there is only one group. if (allSame) member(masters(0)).containsLg(lgSize) else { // Find the master associated with ID and returns whether that particular master is able to receive transaction of lgSize Mux1H(find(id), masters.map(member(_).containsLg(lgSize))) } } // Check for support of a given operation at a specific id val supportsProbe = sourceIdHelper(_.supports.probe) _ val supportsArithmetic = sourceIdHelper(_.supports.arithmetic) _ val supportsLogical = sourceIdHelper(_.supports.logical) _ val supportsGet = sourceIdHelper(_.supports.get) _ val supportsPutFull = sourceIdHelper(_.supports.putFull) _ val supportsPutPartial = sourceIdHelper(_.supports.putPartial) _ val supportsHint = sourceIdHelper(_.supports.hint) _ // TODO: Merge sourceIdHelper2 with sourceIdHelper private def sourceIdHelper2( member: TLMasterParameters => TransferSizes, sourceId: UInt, lgSize: UInt): Bool = { // Because sourceIds are uniquely owned by each master, we use them to group the // cases that have to be checked. val emitCases = groupByIntoSeq(masters)(m => member(m)).map { case (k, vs) => k -> vs.map(_.sourceId) } emitCases.map { case (s, a) => (s.containsLg(lgSize)) && a.map(_.contains(sourceId)).reduce(_||_) }.foldLeft(false.B)(_||_) } // Check for emit of a given operation at a specific id def emitsAcquireT (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.acquireT, sourceId, lgSize) def emitsAcquireB (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.acquireB, sourceId, lgSize) def emitsArithmetic(sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.arithmetic, sourceId, lgSize) def emitsLogical (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.logical, sourceId, lgSize) def emitsGet (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.get, sourceId, lgSize) def emitsPutFull (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.putFull, sourceId, lgSize) def emitsPutPartial(sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.putPartial, sourceId, lgSize) def emitsHint (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.hint, sourceId, lgSize) def infoString = masters.map(_.infoString).mkString def v1copy( clients: Seq[TLMasterParameters] = masters, minLatency: Int = minLatency, echoFields: Seq[BundleFieldBase] = echoFields, requestFields: Seq[BundleFieldBase] = requestFields, responseKeys: Seq[BundleKeyBase] = responseKeys) = { new TLMasterPortParameters( masters = clients, channelBytes = channelBytes, minLatency = minLatency, echoFields = echoFields, requestFields = requestFields, responseKeys = responseKeys) } def v2copy( masters: Seq[TLMasterParameters] = masters, channelBytes: TLChannelBeatBytes = channelBytes, minLatency: Int = minLatency, echoFields: Seq[BundleFieldBase] = echoFields, requestFields: Seq[BundleFieldBase] = requestFields, responseKeys: Seq[BundleKeyBase] = responseKeys) = { new TLMasterPortParameters( masters = masters, channelBytes = channelBytes, minLatency = minLatency, echoFields = echoFields, requestFields = requestFields, responseKeys = responseKeys) } @deprecated("Use v1copy instead of copy","") def copy( clients: Seq[TLMasterParameters] = masters, minLatency: Int = minLatency, echoFields: Seq[BundleFieldBase] = echoFields, requestFields: Seq[BundleFieldBase] = requestFields, responseKeys: Seq[BundleKeyBase] = responseKeys) = { v1copy( clients, minLatency, echoFields, requestFields, responseKeys) } } object TLClientPortParameters { @deprecated("Use TLMasterPortParameters.v1 instead of TLClientPortParameters","") def apply( clients: Seq[TLMasterParameters], minLatency: Int = 0, echoFields: Seq[BundleFieldBase] = Nil, requestFields: Seq[BundleFieldBase] = Nil, responseKeys: Seq[BundleKeyBase] = Nil) = { TLMasterPortParameters.v1( clients, minLatency, echoFields, requestFields, responseKeys) } } object TLMasterPortParameters { def v1( clients: Seq[TLMasterParameters], minLatency: Int = 0, echoFields: Seq[BundleFieldBase] = Nil, requestFields: Seq[BundleFieldBase] = Nil, responseKeys: Seq[BundleKeyBase] = Nil) = { new TLMasterPortParameters( masters = clients, channelBytes = TLChannelBeatBytes(), minLatency = minLatency, echoFields = echoFields, requestFields = requestFields, responseKeys = responseKeys) } def v2( masters: Seq[TLMasterParameters], channelBytes: TLChannelBeatBytes = TLChannelBeatBytes(), minLatency: Int = 0, echoFields: Seq[BundleFieldBase] = Nil, requestFields: Seq[BundleFieldBase] = Nil, responseKeys: Seq[BundleKeyBase] = Nil) = { new TLMasterPortParameters( masters = masters, channelBytes = channelBytes, minLatency = minLatency, echoFields = echoFields, requestFields = requestFields, responseKeys = responseKeys) } } case class TLBundleParameters( addressBits: Int, dataBits: Int, sourceBits: Int, sinkBits: Int, sizeBits: Int, echoFields: Seq[BundleFieldBase], requestFields: Seq[BundleFieldBase], responseFields: Seq[BundleFieldBase], hasBCE: Boolean) { // Chisel has issues with 0-width wires require (addressBits >= 1) require (dataBits >= 8) require (sourceBits >= 1) require (sinkBits >= 1) require (sizeBits >= 1) require (isPow2(dataBits)) echoFields.foreach { f => require (f.key.isControl, s"${f} is not a legal echo field") } val addrLoBits = log2Up(dataBits/8) // Used to uniquify bus IP names def shortName = s"a${addressBits}d${dataBits}s${sourceBits}k${sinkBits}z${sizeBits}" + (if (hasBCE) "c" else "u") def union(x: TLBundleParameters) = TLBundleParameters( max(addressBits, x.addressBits), max(dataBits, x.dataBits), max(sourceBits, x.sourceBits), max(sinkBits, x.sinkBits), max(sizeBits, x.sizeBits), echoFields = BundleField.union(echoFields ++ x.echoFields), requestFields = BundleField.union(requestFields ++ x.requestFields), responseFields = BundleField.union(responseFields ++ x.responseFields), hasBCE || x.hasBCE) } object TLBundleParameters { val emptyBundleParams = TLBundleParameters( addressBits = 1, dataBits = 8, sourceBits = 1, sinkBits = 1, sizeBits = 1, echoFields = Nil, requestFields = Nil, responseFields = Nil, hasBCE = false) def union(x: Seq[TLBundleParameters]) = x.foldLeft(emptyBundleParams)((x,y) => x.union(y)) def apply(master: TLMasterPortParameters, slave: TLSlavePortParameters) = new TLBundleParameters( addressBits = log2Up(slave.maxAddress + 1), dataBits = slave.beatBytes * 8, sourceBits = log2Up(master.endSourceId), sinkBits = log2Up(slave.endSinkId), sizeBits = log2Up(log2Ceil(max(master.maxTransfer, slave.maxTransfer))+1), echoFields = master.echoFields, requestFields = BundleField.accept(master.requestFields, slave.requestKeys), responseFields = BundleField.accept(slave.responseFields, master.responseKeys), hasBCE = master.anySupportProbe && slave.anySupportAcquireB) } case class TLEdgeParameters( master: TLMasterPortParameters, slave: TLSlavePortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge { // legacy names: def manager = slave def client = master val maxTransfer = max(master.maxTransfer, slave.maxTransfer) val maxLgSize = log2Ceil(maxTransfer) // Sanity check the link... require (maxTransfer >= slave.beatBytes, s"Link's max transfer (${maxTransfer}) < ${slave.slaves.map(_.name)}'s beatBytes (${slave.beatBytes})") def diplomaticClaimsMasterToSlave = master.anyEmitClaims.intersect(slave.anySupportClaims) val bundle = TLBundleParameters(master, slave) def formatEdge = master.infoString + "\n" + slave.infoString } case class TLCreditedDelay( a: CreditedDelay, b: CreditedDelay, c: CreditedDelay, d: CreditedDelay, e: CreditedDelay) { def + (that: TLCreditedDelay): TLCreditedDelay = TLCreditedDelay( a = a + that.a, b = b + that.b, c = c + that.c, d = d + that.d, e = e + that.e) override def toString = s"(${a}, ${b}, ${c}, ${d}, ${e})" } object TLCreditedDelay { def apply(delay: CreditedDelay): TLCreditedDelay = apply(delay, delay.flip, delay, delay.flip, delay) } case class TLCreditedManagerPortParameters(delay: TLCreditedDelay, base: TLSlavePortParameters) {def infoString = base.infoString} case class TLCreditedClientPortParameters(delay: TLCreditedDelay, base: TLMasterPortParameters) {def infoString = base.infoString} case class TLCreditedEdgeParameters(client: TLCreditedClientPortParameters, manager: TLCreditedManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge { val delay = client.delay + manager.delay val bundle = TLBundleParameters(client.base, manager.base) def formatEdge = client.infoString + "\n" + manager.infoString } case class TLAsyncManagerPortParameters(async: AsyncQueueParams, base: TLSlavePortParameters) {def infoString = base.infoString} case class TLAsyncClientPortParameters(base: TLMasterPortParameters) {def infoString = base.infoString} case class TLAsyncBundleParameters(async: AsyncQueueParams, base: TLBundleParameters) case class TLAsyncEdgeParameters(client: TLAsyncClientPortParameters, manager: TLAsyncManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge { val bundle = TLAsyncBundleParameters(manager.async, TLBundleParameters(client.base, manager.base)) def formatEdge = client.infoString + "\n" + manager.infoString } case class TLRationalManagerPortParameters(direction: RationalDirection, base: TLSlavePortParameters) {def infoString = base.infoString} case class TLRationalClientPortParameters(base: TLMasterPortParameters) {def infoString = base.infoString} case class TLRationalEdgeParameters(client: TLRationalClientPortParameters, manager: TLRationalManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge { val bundle = TLBundleParameters(client.base, manager.base) def formatEdge = client.infoString + "\n" + manager.infoString } // To be unified, devices must agree on all of these terms case class ManagerUnificationKey( resources: Seq[Resource], regionType: RegionType.T, executable: Boolean, supportsAcquireT: TransferSizes, supportsAcquireB: TransferSizes, supportsArithmetic: TransferSizes, supportsLogical: TransferSizes, supportsGet: TransferSizes, supportsPutFull: TransferSizes, supportsPutPartial: TransferSizes, supportsHint: TransferSizes) object ManagerUnificationKey { def apply(x: TLSlaveParameters): ManagerUnificationKey = ManagerUnificationKey( resources = x.resources, regionType = x.regionType, executable = x.executable, supportsAcquireT = x.supportsAcquireT, supportsAcquireB = x.supportsAcquireB, supportsArithmetic = x.supportsArithmetic, supportsLogical = x.supportsLogical, supportsGet = x.supportsGet, supportsPutFull = x.supportsPutFull, supportsPutPartial = x.supportsPutPartial, supportsHint = x.supportsHint) } object ManagerUnification { def apply(slaves: Seq[TLSlaveParameters]): List[TLSlaveParameters] = { slaves.groupBy(ManagerUnificationKey.apply).values.map { seq => val agree = seq.forall(_.fifoId == seq.head.fifoId) seq(0).v1copy( address = AddressSet.unify(seq.flatMap(_.address)), fifoId = if (agree) seq(0).fifoId else None) }.toList } } case class TLBufferParams( a: BufferParams = BufferParams.none, b: BufferParams = BufferParams.none, c: BufferParams = BufferParams.none, d: BufferParams = BufferParams.none, e: BufferParams = BufferParams.none ) extends DirectedBuffers[TLBufferParams] { def copyIn(x: BufferParams) = this.copy(b = x, d = x) def copyOut(x: BufferParams) = this.copy(a = x, c = x, e = x) def copyInOut(x: BufferParams) = this.copyIn(x).copyOut(x) } /** Pretty printing of TL source id maps */ class TLSourceIdMap(tl: TLMasterPortParameters) extends IdMap[TLSourceIdMapEntry] { private val tlDigits = String.valueOf(tl.endSourceId-1).length() protected val fmt = s"\t[%${tlDigits}d, %${tlDigits}d) %s%s%s" private val sorted = tl.masters.sortBy(_.sourceId) val mapping: Seq[TLSourceIdMapEntry] = sorted.map { case c => TLSourceIdMapEntry(c.sourceId, c.name, c.supports.probe, c.requestFifo) } } case class TLSourceIdMapEntry(tlId: IdRange, name: String, isCache: Boolean, requestFifo: Boolean) extends IdMapEntry { val from = tlId val to = tlId val maxTransactionsInFlight = Some(tlId.size) } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) || !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.ProbeAckData || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode | small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U || beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }

module TLMonitor_14( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input [7:0] io_in_d_bits_data, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [3:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [31:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7] wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7] wire [7:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_a_bits_source = 1'h0; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_source = 1'h0; // @[Monitor.scala:36:7] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire c_set = 1'h0; // @[Monitor.scala:738:34] wire c_set_wo_ready = 1'h0; // @[Monitor.scala:739:34] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire io_in_a_bits_mask = 1'h1; // @[Monitor.scala:36:7] wire _source_ok_T = 1'h1; // @[Parameters.scala:46:9] wire _source_ok_WIRE_0 = 1'h1; // @[Parameters.scala:1138:31] wire mask_sizeOH = 1'h1; // @[Misc.scala:202:81] wire _source_ok_T_1 = 1'h1; // @[Parameters.scala:46:9] wire _source_ok_WIRE_1_0 = 1'h1; // @[Parameters.scala:1138:31] wire sink_ok = 1'h1; // @[Monitor.scala:309:31] wire _same_cycle_resp_T_2 = 1'h1; // @[Monitor.scala:684:113] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire _same_cycle_resp_T_8 = 1'h1; // @[Monitor.scala:795:113] wire [3:0] _a_opcode_lookup_T = 4'h0; // @[Monitor.scala:637:69] wire [3:0] _a_size_lookup_T = 4'h0; // @[Monitor.scala:641:65] wire [3:0] _a_opcodes_set_T = 4'h0; // @[Monitor.scala:659:79] wire [3:0] _a_sizes_set_T = 4'h0; // @[Monitor.scala:660:77] wire [3:0] _d_opcodes_clr_T_4 = 4'h0; // @[Monitor.scala:680:101] wire [3:0] _d_sizes_clr_T_4 = 4'h0; // @[Monitor.scala:681:99] wire [3:0] _c_first_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] c_opcodes_set = 4'h0; // @[Monitor.scala:740:34] wire [3:0] _c_opcode_lookup_T = 4'h0; // @[Monitor.scala:749:69] wire [3:0] _c_size_lookup_T = 4'h0; // @[Monitor.scala:750:67] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] _c_set_wo_ready_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_wo_ready_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_sizes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_T = 4'h0; // @[Monitor.scala:767:79] wire [3:0] _c_sizes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_sizes_set_T = 4'h0; // @[Monitor.scala:768:77] wire [3:0] _c_probe_ack_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _d_opcodes_clr_T_10 = 4'h0; // @[Monitor.scala:790:101] wire [3:0] _d_sizes_clr_T_10 = 4'h0; // @[Monitor.scala:791:99] wire [3:0] _same_cycle_resp_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_4_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_5_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [30:0] _d_sizes_clr_T_5 = 31'hFF; // @[Monitor.scala:681:74] wire [30:0] _d_sizes_clr_T_11 = 31'hFF; // @[Monitor.scala:791:74] wire [30:0] _d_opcodes_clr_T_5 = 31'hF; // @[Monitor.scala:680:76] wire [30:0] _d_opcodes_clr_T_11 = 31'hF; // @[Monitor.scala:790:76] wire [1:0] _a_set_wo_ready_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _a_set_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _d_clr_wo_ready_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _d_clr_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _c_set_wo_ready_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _c_set_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _d_clr_wo_ready_T_1 = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _d_clr_T_1 = 2'h1; // @[OneHot.scala:58:35] wire [11:0] _c_first_beats1_decode_T_2 = 12'h0; // @[package.scala:243:46] wire [11:0] c_first_beats1_decode = 12'h0; // @[Edges.scala:220:59] wire [11:0] c_first_beats1 = 12'h0; // @[Edges.scala:221:14] wire [11:0] _c_first_count_T = 12'h0; // @[Edges.scala:234:27] wire [11:0] c_first_count = 12'h0; // @[Edges.scala:234:25] wire [11:0] _c_first_counter_T = 12'h0; // @[Edges.scala:236:21] wire [11:0] _c_first_beats1_decode_T_1 = 12'hFFF; // @[package.scala:243:76] wire [11:0] c_first_counter1 = 12'hFFF; // @[Edges.scala:230:28] wire [12:0] _c_first_counter1_T = 13'h1FFF; // @[Edges.scala:230:28] wire [2:0] io_in_a_bits_param = 3'h0; // @[Monitor.scala:36:7] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [7:0] _c_first_WIRE_bits_data = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_first_WIRE_1_bits_data = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_first_WIRE_2_bits_data = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_first_WIRE_3_bits_data = 8'h0; // @[Bundles.scala:265:61] wire [7:0] c_sizes_set = 8'h0; // @[Monitor.scala:741:34] wire [7:0] _c_set_wo_ready_WIRE_bits_data = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_set_wo_ready_WIRE_1_bits_data = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_set_WIRE_bits_data = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_set_WIRE_1_bits_data = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_opcodes_set_interm_WIRE_bits_data = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_opcodes_set_interm_WIRE_1_bits_data = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_sizes_set_interm_WIRE_bits_data = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_sizes_set_interm_WIRE_1_bits_data = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_opcodes_set_WIRE_bits_data = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_opcodes_set_WIRE_1_bits_data = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_sizes_set_WIRE_bits_data = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_sizes_set_WIRE_1_bits_data = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_probe_ack_WIRE_bits_data = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_probe_ack_WIRE_1_bits_data = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_probe_ack_WIRE_2_bits_data = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_probe_ack_WIRE_3_bits_data = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _same_cycle_resp_WIRE_bits_data = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _same_cycle_resp_WIRE_1_bits_data = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _same_cycle_resp_WIRE_2_bits_data = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _same_cycle_resp_WIRE_3_bits_data = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _same_cycle_resp_WIRE_4_bits_data = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _same_cycle_resp_WIRE_5_bits_data = 8'h0; // @[Bundles.scala:265:61] wire [31:0] _c_first_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_first_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_wo_ready_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_wo_ready_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_4_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_5_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [15:0] _a_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _c_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hFF; // @[Monitor.scala:724:57] wire [16:0] _a_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _c_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hFF; // @[Monitor.scala:724:57] wire [15:0] _a_size_lookup_T_3 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _c_size_lookup_T_3 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [19:0] _c_sizes_set_T_1 = 20'h0; // @[Monitor.scala:768:52] wire [18:0] _c_opcodes_set_T_1 = 19'h0; // @[Monitor.scala:767:54] wire [4:0] _c_sizes_set_interm_T_1 = 5'h1; // @[Monitor.scala:766:59] wire [4:0] c_sizes_set_interm = 5'h0; // @[Monitor.scala:755:40] wire [4:0] _c_sizes_set_interm_T = 5'h0; // @[Monitor.scala:766:51] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [26:0] _c_first_beats1_decode_T = 27'hFFF; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [3:0] _a_size_lookup_T_2 = 4'h8; // @[Monitor.scala:641:117] wire [3:0] _d_sizes_clr_T = 4'h8; // @[Monitor.scala:681:48] wire [3:0] _c_size_lookup_T_2 = 4'h8; // @[Monitor.scala:750:119] wire [3:0] _d_sizes_clr_T_6 = 4'h8; // @[Monitor.scala:791:48] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire [26:0] _GEN = 27'hFFF << io_in_a_bits_size_0; // @[package.scala:243:71] wire [26:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [11:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [31:0] _is_aligned_T = {20'h0, io_in_a_bits_address_0[11:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 32'h0; // @[Edges.scala:21:{16,24}] wire _T_1222 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_1222; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_1222; // @[Decoupled.scala:51:35] wire [11:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [11:0] a_first_beats1_decode = _a_first_beats1_decode_T_2; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [11:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 12'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [11:0] a_first_counter; // @[Edges.scala:229:27] wire [12:0] _a_first_counter1_T = {1'h0, a_first_counter} - 13'h1; // @[Edges.scala:229:27, :230:28] wire [11:0] a_first_counter1 = _a_first_counter1_T[11:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 12'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 12'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 12'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [11:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [11:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [11:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [3:0] size; // @[Monitor.scala:389:22] reg [31:0] address; // @[Monitor.scala:391:22] wire _T_1295 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_1295; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_1295; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_1295; // @[Decoupled.scala:51:35] wire [26:0] _GEN_0 = 27'hFFF << io_in_d_bits_size_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [11:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [11:0] d_first_beats1_decode = _d_first_beats1_decode_T_2; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [11:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 12'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [11:0] d_first_counter; // @[Edges.scala:229:27] wire [12:0] _d_first_counter1_T = {1'h0, d_first_counter} - 13'h1; // @[Edges.scala:229:27, :230:28] wire [11:0] d_first_counter1 = _d_first_counter1_T[11:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 12'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 12'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 12'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [11:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [11:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [11:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [3:0] size_1; // @[Monitor.scala:540:22] reg source_1; // @[Monitor.scala:541:22] reg [2:0] sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] reg [1:0] inflight; // @[Monitor.scala:614:27] reg [3:0] inflight_opcodes; // @[Monitor.scala:616:35] wire [3:0] _a_opcode_lookup_T_1 = inflight_opcodes; // @[Monitor.scala:616:35, :637:44] reg [7:0] inflight_sizes; // @[Monitor.scala:618:33] wire [7:0] _a_size_lookup_T_1 = inflight_sizes; // @[Monitor.scala:618:33, :641:40] wire [11:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [11:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [11:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 12'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [11:0] a_first_counter_1; // @[Edges.scala:229:27] wire [12:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 13'h1; // @[Edges.scala:229:27, :230:28] wire [11:0] a_first_counter1_1 = _a_first_counter1_T_1[11:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 12'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 12'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 12'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [11:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [11:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [11:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [11:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [11:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5; // @[package.scala:243:46] wire [11:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 12'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [11:0] d_first_counter_1; // @[Edges.scala:229:27] wire [12:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 13'h1; // @[Edges.scala:229:27, :230:28] wire [11:0] d_first_counter1_1 = _d_first_counter1_T_1[11:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 12'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 12'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 12'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [11:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [11:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [11:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire a_set; // @[Monitor.scala:626:34] wire a_set_wo_ready; // @[Monitor.scala:627:34] wire [3:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [7:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [15:0] _a_opcode_lookup_T_6 = {12'h0, _a_opcode_lookup_T_1}; // @[Monitor.scala:637:{44,97}] wire [15:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [7:0] a_size_lookup; // @[Monitor.scala:639:33] wire [15:0] _a_size_lookup_T_6 = {8'h0, _a_size_lookup_T_1}; // @[Monitor.scala:641:{40,91}] wire [15:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[15:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[7:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [4:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _T_1145 = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26] assign a_set_wo_ready = _T_1145; // @[Monitor.scala:627:34, :651:26] wire _same_cycle_resp_T; // @[Monitor.scala:684:44] assign _same_cycle_resp_T = _T_1145; // @[Monitor.scala:651:26, :684:44] assign a_set = _T_1222 & a_first_1; // @[Decoupled.scala:51:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = a_set ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:626:34, :646:40, :655:70, :657:{28,61}] wire [4:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [4:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = a_set ? _a_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:626:34, :648:38, :655:70, :658:{28,59}] wire [18:0] _a_opcodes_set_T_1 = {15'h0, a_opcodes_set_interm}; // @[Monitor.scala:646:40, :659:54] assign a_opcodes_set = a_set ? _a_opcodes_set_T_1[3:0] : 4'h0; // @[Monitor.scala:626:34, :630:33, :655:70, :659:{28,54}] wire [19:0] _a_sizes_set_T_1 = {15'h0, a_sizes_set_interm}; // @[Monitor.scala:648:38, :660:52] assign a_sizes_set = a_set ? _a_sizes_set_T_1[7:0] : 8'h0; // @[Monitor.scala:626:34, :632:31, :655:70, :660:{28,52}] wire d_clr; // @[Monitor.scala:664:34] wire d_clr_wo_ready; // @[Monitor.scala:665:34] wire [3:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [7:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_1 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_1; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_1; // @[Monitor.scala:673:46, :783:46] wire _T_1194 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] assign d_clr_wo_ready = _T_1194 & ~d_release_ack; // @[Monitor.scala:665:34, :673:46, :674:{26,71,74}] assign d_clr = _T_1295 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_opcodes_clr = {4{d_clr}}; // @[Monitor.scala:664:34, :668:33, :678:89, :680:21] assign d_sizes_clr = {8{d_clr}}; // @[Monitor.scala:664:34, :670:31, :678:89, :681:21] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire same_cycle_resp = _same_cycle_resp_T_1; // @[Monitor.scala:684:{55,88}] wire [1:0] _inflight_T = {inflight[1], inflight[0] | a_set}; // @[Monitor.scala:614:27, :626:34, :705:27] wire _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [1:0] _inflight_T_2 = {1'h0, _inflight_T[0] & _inflight_T_1}; // @[Monitor.scala:705:{27,36,38}] wire [3:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [3:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [3:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [7:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [7:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [7:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [1:0] inflight_1; // @[Monitor.scala:726:35] wire [1:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [3:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [3:0] _c_opcode_lookup_T_1 = inflight_opcodes_1; // @[Monitor.scala:727:35, :749:44] wire [3:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [7:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [7:0] _c_size_lookup_T_1 = inflight_sizes_1; // @[Monitor.scala:728:35, :750:42] wire [7:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire [11:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [11:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8; // @[package.scala:243:46] wire [11:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 12'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [11:0] d_first_counter_2; // @[Edges.scala:229:27] wire [12:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 13'h1; // @[Edges.scala:229:27, :230:28] wire [11:0] d_first_counter1_2 = _d_first_counter1_T_2[11:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 12'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 12'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 12'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [11:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [11:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [11:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [7:0] c_size_lookup; // @[Monitor.scala:748:35] wire [15:0] _c_opcode_lookup_T_6 = {12'h0, _c_opcode_lookup_T_1}; // @[Monitor.scala:749:{44,97}] wire [15:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [15:0] _c_size_lookup_T_6 = {8'h0, _c_size_lookup_T_1}; // @[Monitor.scala:750:{42,93}] wire [15:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[15:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[7:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire d_clr_1; // @[Monitor.scala:774:34] wire d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [3:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [7:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_1266 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_1266 & d_release_ack_1; // @[Monitor.scala:775:34, :783:46, :784:{26,71}] assign d_clr_1 = _T_1295 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_opcodes_clr_1 = {4{d_clr_1}}; // @[Monitor.scala:774:34, :776:34, :788:88, :790:21] assign d_sizes_clr_1 = {8{d_clr_1}}; // @[Monitor.scala:774:34, :777:34, :788:88, :791:21] wire _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [1:0] _inflight_T_5 = {1'h0, _inflight_T_3[0] & _inflight_T_4}; // @[Monitor.scala:814:{35,44,46}] wire [3:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [3:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [7:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [7:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]

Generate the Verilog code corresponding to the following Chisel files. File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /** Like Vec.apply(idx), but tolerates indices of mismatched width */ def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /** Any Data subtype that has a Bool member named valid. */ type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /** converts from camel case to to underscores, also removing all spaces */ def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /** converts spaces or underscores to hyphens, also lowering case */ def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y | (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y || y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /** Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation */ def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag }

module OptimizationBarrier_TLBEntryData_172( // @[package.scala:267:30] input clock, // @[package.scala:267:30] input reset, // @[package.scala:267:30] input [19:0] io_x_ppn, // @[package.scala:268:18] input io_x_u, // @[package.scala:268:18] input io_x_g, // @[package.scala:268:18] input io_x_ae_ptw, // @[package.scala:268:18] input io_x_ae_final, // @[package.scala:268:18] input io_x_ae_stage2, // @[package.scala:268:18] input io_x_pf, // @[package.scala:268:18] input io_x_gf, // @[package.scala:268:18] input io_x_sw, // @[package.scala:268:18] input io_x_sx, // @[package.scala:268:18] input io_x_sr, // @[package.scala:268:18] input io_x_hw, // @[package.scala:268:18] input io_x_hx, // @[package.scala:268:18] input io_x_hr, // @[package.scala:268:18] input io_x_pw, // @[package.scala:268:18] input io_x_px, // @[package.scala:268:18] input io_x_pr, // @[package.scala:268:18] input io_x_ppp, // @[package.scala:268:18] input io_x_pal, // @[package.scala:268:18] input io_x_paa, // @[package.scala:268:18] input io_x_eff, // @[package.scala:268:18] input io_x_c, // @[package.scala:268:18] input io_x_fragmented_superpage, // @[package.scala:268:18] output io_y_u, // @[package.scala:268:18] output io_y_ae_ptw, // @[package.scala:268:18] output io_y_ae_final, // @[package.scala:268:18] output io_y_ae_stage2, // @[package.scala:268:18] output io_y_pf, // @[package.scala:268:18] output io_y_gf, // @[package.scala:268:18] output io_y_sw, // @[package.scala:268:18] output io_y_sx, // @[package.scala:268:18] output io_y_sr, // @[package.scala:268:18] output io_y_hw, // @[package.scala:268:18] output io_y_hx, // @[package.scala:268:18] output io_y_hr, // @[package.scala:268:18] output io_y_pw, // @[package.scala:268:18] output io_y_px, // @[package.scala:268:18] output io_y_pr, // @[package.scala:268:18] output io_y_ppp, // @[package.scala:268:18] output io_y_pal, // @[package.scala:268:18] output io_y_paa, // @[package.scala:268:18] output io_y_eff, // @[package.scala:268:18] output io_y_c // @[package.scala:268:18] ); wire [19:0] io_x_ppn_0 = io_x_ppn; // @[package.scala:267:30] wire io_x_u_0 = io_x_u; // @[package.scala:267:30] wire io_x_g_0 = io_x_g; // @[package.scala:267:30] wire io_x_ae_ptw_0 = io_x_ae_ptw; // @[package.scala:267:30] wire io_x_ae_final_0 = io_x_ae_final; // @[package.scala:267:30] wire io_x_ae_stage2_0 = io_x_ae_stage2; // @[package.scala:267:30] wire io_x_pf_0 = io_x_pf; // @[package.scala:267:30] wire io_x_gf_0 = io_x_gf; // @[package.scala:267:30] wire io_x_sw_0 = io_x_sw; // @[package.scala:267:30] wire io_x_sx_0 = io_x_sx; // @[package.scala:267:30] wire io_x_sr_0 = io_x_sr; // @[package.scala:267:30] wire io_x_hw_0 = io_x_hw; // @[package.scala:267:30] wire io_x_hx_0 = io_x_hx; // @[package.scala:267:30] wire io_x_hr_0 = io_x_hr; // @[package.scala:267:30] wire io_x_pw_0 = io_x_pw; // @[package.scala:267:30] wire io_x_px_0 = io_x_px; // @[package.scala:267:30] wire io_x_pr_0 = io_x_pr; // @[package.scala:267:30] wire io_x_ppp_0 = io_x_ppp; // @[package.scala:267:30] wire io_x_pal_0 = io_x_pal; // @[package.scala:267:30] wire io_x_paa_0 = io_x_paa; // @[package.scala:267:30] wire io_x_eff_0 = io_x_eff; // @[package.scala:267:30] wire io_x_c_0 = io_x_c; // @[package.scala:267:30] wire io_x_fragmented_superpage_0 = io_x_fragmented_superpage; // @[package.scala:267:30] wire [19:0] io_y_ppn = io_x_ppn_0; // @[package.scala:267:30] wire io_y_u_0 = io_x_u_0; // @[package.scala:267:30] wire io_y_g = io_x_g_0; // @[package.scala:267:30] wire io_y_ae_ptw_0 = io_x_ae_ptw_0; // @[package.scala:267:30] wire io_y_ae_final_0 = io_x_ae_final_0; // @[package.scala:267:30] wire io_y_ae_stage2_0 = io_x_ae_stage2_0; // @[package.scala:267:30] wire io_y_pf_0 = io_x_pf_0; // @[package.scala:267:30] wire io_y_gf_0 = io_x_gf_0; // @[package.scala:267:30] wire io_y_sw_0 = io_x_sw_0; // @[package.scala:267:30] wire io_y_sx_0 = io_x_sx_0; // @[package.scala:267:30] wire io_y_sr_0 = io_x_sr_0; // @[package.scala:267:30] wire io_y_hw_0 = io_x_hw_0; // @[package.scala:267:30] wire io_y_hx_0 = io_x_hx_0; // @[package.scala:267:30] wire io_y_hr_0 = io_x_hr_0; // @[package.scala:267:30] wire io_y_pw_0 = io_x_pw_0; // @[package.scala:267:30] wire io_y_px_0 = io_x_px_0; // @[package.scala:267:30] wire io_y_pr_0 = io_x_pr_0; // @[package.scala:267:30] wire io_y_ppp_0 = io_x_ppp_0; // @[package.scala:267:30] wire io_y_pal_0 = io_x_pal_0; // @[package.scala:267:30] wire io_y_paa_0 = io_x_paa_0; // @[package.scala:267:30] wire io_y_eff_0 = io_x_eff_0; // @[package.scala:267:30] wire io_y_c_0 = io_x_c_0; // @[package.scala:267:30] wire io_y_fragmented_superpage = io_x_fragmented_superpage_0; // @[package.scala:267:30] assign io_y_u = io_y_u_0; // @[package.scala:267:30] assign io_y_ae_ptw = io_y_ae_ptw_0; // @[package.scala:267:30] assign io_y_ae_final = io_y_ae_final_0; // @[package.scala:267:30] assign io_y_ae_stage2 = io_y_ae_stage2_0; // @[package.scala:267:30] assign io_y_pf = io_y_pf_0; // @[package.scala:267:30] assign io_y_gf = io_y_gf_0; // @[package.scala:267:30] assign io_y_sw = io_y_sw_0; // @[package.scala:267:30] assign io_y_sx = io_y_sx_0; // @[package.scala:267:30] assign io_y_sr = io_y_sr_0; // @[package.scala:267:30] assign io_y_hw = io_y_hw_0; // @[package.scala:267:30] assign io_y_hx = io_y_hx_0; // @[package.scala:267:30] assign io_y_hr = io_y_hr_0; // @[package.scala:267:30] assign io_y_pw = io_y_pw_0; // @[package.scala:267:30] assign io_y_px = io_y_px_0; // @[package.scala:267:30] assign io_y_pr = io_y_pr_0; // @[package.scala:267:30] assign io_y_ppp = io_y_ppp_0; // @[package.scala:267:30] assign io_y_pal = io_y_pal_0; // @[package.scala:267:30] assign io_y_paa = io_y_paa_0; // @[package.scala:267:30] assign io_y_eff = io_y_eff_0; // @[package.scala:267:30] assign io_y_c = io_y_c_0; // @[package.scala:267:30] endmodule

Generate the Verilog code corresponding to the following Chisel files. File Monitor.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceLine import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import freechips.rocketchip.diplomacy.EnableMonitors import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode} import freechips.rocketchip.util.PlusArg case class TLMonitorArgs(edge: TLEdge) abstract class TLMonitorBase(args: TLMonitorArgs) extends Module { val io = IO(new Bundle { val in = Input(new TLBundle(args.edge.bundle)) }) def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit legalize(io.in, args.edge, reset) } object TLMonitor { def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = { if (enable) { EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) } } else { node } } } class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args) { require (args.edge.params(TLMonitorStrictMode) || (! args.edge.params(TestplanTestType).formal)) val cover_prop_class = PropertyClass.Default //Like assert but can flip to being an assumption for formal verification def monAssert(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir, cond, message, PropertyClass.Default) } def assume(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir.flip, cond, message, PropertyClass.Default) } def extra = { args.edge.sourceInfo match { case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)" case _ => "" } } def visible(address: UInt, source: UInt, edge: TLEdge) = edge.client.clients.map { c => !c.sourceId.contains(source) || c.visibility.map(_.contains(address)).reduce(_ || _) }.reduce(_ && _) def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = { //switch this flag to turn on diplomacy in error messages def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n" monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra) // Reuse these subexpressions to save some firrtl lines val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility") //The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B //TODO: check for acquireT? when (bundle.opcode === TLMessages.AcquireBlock) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra) } when (bundle.opcode === TLMessages.AcquirePerm) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra) monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra) monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra) monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra) } } def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = { monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra) monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility") // Reuse these subexpressions to save some firrtl lines val address_ok = edge.manager.containsSafe(edge.address(bundle)) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source when (bundle.opcode === TLMessages.Probe) { assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra) assume (address_ok, "'B' channel Probe carries unmanaged address" + extra) assume (legal_source, "'B' channel Probe carries source that is not first source" + extra) assume (is_aligned, "'B' channel Probe address not aligned to size" + extra) assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra) assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra) assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra) monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra) monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra) monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra) monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra) } } def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = { monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val address_ok = edge.manager.containsSafe(edge.address(bundle)) monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility") when (bundle.opcode === TLMessages.ProbeAck) { monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra) } when (bundle.opcode === TLMessages.ProbeAckData) { monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.Release) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra) monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra) } when (bundle.opcode === TLMessages.ReleaseData) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.AccessAck) { monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra) } when (bundle.opcode === TLMessages.HintAck) { monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra) } } def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = { assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val sink_ok = bundle.sink < edge.manager.endSinkId.U val deny_put_ok = edge.manager.mayDenyPut.B val deny_get_ok = edge.manager.mayDenyGet.B when (bundle.opcode === TLMessages.ReleaseAck) { assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra) assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra) assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra) } when (bundle.opcode === TLMessages.Grant) { assume (source_ok, "'D' channel Grant carries invalid source ID" + extra) assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra) assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel Grant is denied" + extra) } when (bundle.opcode === TLMessages.GrantData) { assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra) assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra) assume (!bundle.denied || bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra) assume (deny_get_ok || !bundle.denied, "'D' channel GrantData is denied" + extra) } when (bundle.opcode === TLMessages.AccessAck) { assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel AccessAck is denied" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra) assume (!bundle.denied || bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra) assume (deny_get_ok || !bundle.denied, "'D' channel AccessAckData is denied" + extra) } when (bundle.opcode === TLMessages.HintAck) { assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel HintAck is denied" + extra) } } def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = { val sink_ok = bundle.sink < edge.manager.endSinkId.U monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra) } def legalizeFormat(bundle: TLBundle, edge: TLEdge) = { when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) } when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) } when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) } when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) } } else { monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra) monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra) monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra) } } def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = { val a_first = edge.first(a.bits, a.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (a.valid && !a_first) { monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra) monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra) monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra) monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra) monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra) } when (a.fire && a_first) { opcode := a.bits.opcode param := a.bits.param size := a.bits.size source := a.bits.source address := a.bits.address } } def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = { val b_first = edge.first(b.bits, b.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (b.valid && !b_first) { monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra) monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra) monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra) monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra) monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra) } when (b.fire && b_first) { opcode := b.bits.opcode param := b.bits.param size := b.bits.size source := b.bits.source address := b.bits.address } } def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = { // Symbolic variable val sym_source = Wire(UInt(edge.client.endSourceId.W)) // TODO: Connect sym_source to a fixed value for simulation and to a // free wire in formal sym_source := 0.U // Type casting Int to UInt val maxSourceId = Wire(UInt(edge.client.endSourceId.W)) maxSourceId := edge.client.endSourceId.U // Delayed verison of sym_source val sym_source_d = Reg(UInt(edge.client.endSourceId.W)) sym_source_d := sym_source // These will be constraints for FV setup Property( MonitorDirection.Monitor, (sym_source === sym_source_d), "sym_source should remain stable", PropertyClass.Default) Property( MonitorDirection.Monitor, (sym_source <= maxSourceId), "sym_source should take legal value", PropertyClass.Default) val my_resp_pend = RegInit(false.B) val my_opcode = Reg(UInt()) val my_size = Reg(UInt()) val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire) val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire) val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source) val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source) val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat) val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend) when (my_set_resp_pend) { my_resp_pend := true.B } .elsewhen (my_clr_resp_pend) { my_resp_pend := false.B } when (my_a_first_beat) { my_opcode := bundle.a.bits.opcode my_size := bundle.a.bits.size } val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size) val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode) val my_resp_opcode_legal = Wire(Bool()) when ((my_resp_opcode === TLMessages.Get) || (my_resp_opcode === TLMessages.ArithmeticData) || (my_resp_opcode === TLMessages.LogicalData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData) } .elsewhen ((my_resp_opcode === TLMessages.PutFullData) || (my_resp_opcode === TLMessages.PutPartialData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck) } .otherwise { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck) } monAssert (IfThen(my_resp_pend, !my_a_first_beat), "Request message should not be sent with a source ID, for which a response message" + "is already pending (not received until current cycle) for a prior request message" + "with the same source ID" + extra) assume (IfThen(my_clr_resp_pend, (my_set_resp_pend || my_resp_pend)), "Response message should be accepted with a source ID only if a request message with the" + "same source ID has been accepted or is being accepted in the current cycle" + extra) assume (IfThen(my_d_first_beat, (my_a_first_beat || my_resp_pend)), "Response message should be sent with a source ID only if a request message with the" + "same source ID has been accepted or is being sent in the current cycle" + extra) assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)), "If d_valid is 1, then d_size should be same as a_size of the corresponding request" + "message" + extra) assume (IfThen(my_d_first_beat, my_resp_opcode_legal), "If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" + "request message" + extra) } def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = { val c_first = edge.first(c.bits, c.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (c.valid && !c_first) { monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra) monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra) monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra) monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra) monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra) } when (c.fire && c_first) { opcode := c.bits.opcode param := c.bits.param size := c.bits.size source := c.bits.source address := c.bits.address } } def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = { val d_first = edge.first(d.bits, d.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val sink = Reg(UInt()) val denied = Reg(Bool()) when (d.valid && !d_first) { assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra) assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra) assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra) assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra) assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra) assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra) } when (d.fire && d_first) { opcode := d.bits.opcode param := d.bits.param size := d.bits.size source := d.bits.source sink := d.bits.sink denied := d.bits.denied } } def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = { legalizeMultibeatA(bundle.a, edge) legalizeMultibeatD(bundle.d, edge) if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { legalizeMultibeatB(bundle.b, edge) legalizeMultibeatC(bundle.c, edge) } } //This is left in for almond which doesn't adhere to the tilelink protocol @deprecated("Use legalizeADSource instead if possible","") def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.client.endSourceId.W)) val a_first = edge.first(bundle.a.bits, bundle.a.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val a_set = WireInit(0.U(edge.client.endSourceId.W)) when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) assume((a_set | inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra) } if (edge.manager.minLatency > 0) { assume(a_set =/= d_clr || !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight | a_set) & ~d_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") assert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = { val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size) val log_a_size_bus_size = log2Ceil(a_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error inflight.suggestName("inflight") val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) inflight_opcodes.suggestName("inflight_opcodes") val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) inflight_sizes.suggestName("inflight_sizes") val a_first = edge.first(bundle.a.bits, bundle.a.fire) a_first.suggestName("a_first") val d_first = edge.first(bundle.d.bits, bundle.d.fire) d_first.suggestName("d_first") val a_set = WireInit(0.U(edge.client.endSourceId.W)) val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) a_set.suggestName("a_set") a_set_wo_ready.suggestName("a_set_wo_ready") val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) a_opcodes_set.suggestName("a_opcodes_set") val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) a_sizes_set.suggestName("a_sizes_set") val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W)) a_opcode_lookup.suggestName("a_opcode_lookup") a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W)) a_size_lookup.suggestName("a_size_lookup") a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant)) val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant)) val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W)) a_opcodes_set_interm.suggestName("a_opcodes_set_interm") val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W)) a_sizes_set_interm.suggestName("a_sizes_set_interm") when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) { a_set_wo_ready := UIntToOH(bundle.a.bits.source) } when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) | 1.U a_sizes_set_interm := (bundle.a.bits.size << 1.U) | 1.U a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U) a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U) monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) d_opcodes_clr.suggestName("d_opcodes_clr") val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) || (bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra) assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) || (bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra) assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) { assume((!bundle.d.ready) || bundle.a.ready, "ready check") } if (edge.manager.minLatency > 0) { assume(a_set_wo_ready =/= d_clr_wo_ready || !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight | a_set) & ~d_clr inflight_opcodes := (inflight_opcodes | a_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes | a_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = { val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size) val log_c_size_bus_size = log2Ceil(c_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) inflight.suggestName("inflight") inflight_opcodes.suggestName("inflight_opcodes") inflight_sizes.suggestName("inflight_sizes") val c_first = edge.first(bundle.c.bits, bundle.c.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) c_first.suggestName("c_first") d_first.suggestName("d_first") val c_set = WireInit(0.U(edge.client.endSourceId.W)) val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) c_set.suggestName("c_set") c_set_wo_ready.suggestName("c_set_wo_ready") c_opcodes_set.suggestName("c_opcodes_set") c_sizes_set.suggestName("c_sizes_set") val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W)) val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W)) c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U c_opcode_lookup.suggestName("c_opcode_lookup") c_size_lookup.suggestName("c_size_lookup") val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W)) val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W)) c_opcodes_set_interm.suggestName("c_opcodes_set_interm") c_sizes_set_interm.suggestName("c_sizes_set_interm") when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) { c_set_wo_ready := UIntToOH(bundle.c.bits.source) } when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) { c_set := UIntToOH(bundle.c.bits.source) c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) | 1.U c_sizes_set_interm := (bundle.c.bits.size << 1.U) | 1.U c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U) c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U) monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra) } val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck || bundle.c.bits.opcode === TLMessages.ProbeAckData val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") d_opcodes_clr.suggestName("d_opcodes_clr") d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) { assume((!bundle.d.ready) || bundle.c.ready, "ready check") } if (edge.manager.minLatency > 0) { when (c_set_wo_ready.orR) { assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra) } } inflight := (inflight | c_set) & ~d_clr inflight_opcodes := (inflight_opcodes | c_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes | c_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.c.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.manager.endSinkId.W)) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val e_first = true.B val d_set = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) { d_set := UIntToOH(bundle.d.bits.sink) assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra) } val e_clr = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) { e_clr := UIntToOH(bundle.e.bits.sink) monAssert((d_set | inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra) } // edge.client.minLatency applies to BC, not DE inflight := (inflight | d_set) & ~e_clr } def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = { val sourceBits = log2Ceil(edge.client.endSourceId) val tooBig = 14 // >16kB worth of flight information gets to be too much if (sourceBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked") } else { if (args.edge.params(TestplanTestType).simulation) { if (args.edge.params(TLMonitorStrictMode)) { legalizeADSource(bundle, edge) legalizeCDSource(bundle, edge) } else { legalizeADSourceOld(bundle, edge) } } if (args.edge.params(TestplanTestType).formal) { legalizeADSourceFormal(bundle, edge) } } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { // legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize... val sinkBits = log2Ceil(edge.manager.endSinkId) if (sinkBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked") } else { legalizeDESink(bundle, edge) } } } def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = { legalizeFormat (bundle, edge) legalizeMultibeat (bundle, edge) legalizeUnique (bundle, edge) } } File Misc.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import scala.math._ class ParameterizedBundle(implicit p: Parameters) extends Bundle trait Clocked extends Bundle { val clock = Clock() val reset = Bool() } object DecoupledHelper { def apply(rvs: Bool*) = new DecoupledHelper(rvs) } class DecoupledHelper(val rvs: Seq[Bool]) { def fire(exclude: Bool, includes: Bool*) = { require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!") (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _) } def fire() = { rvs.reduce(_ && _) } } object MuxT { def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2)) def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3)) def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4)) } /** Creates a cascade of n MuxTs to search for a key value. */ object MuxTLookup { def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } } object ValidMux { def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]*): ValidIO[T] = { apply(v1 +: v2.toSeq) } def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = { val out = Wire(Valid(valids.head.bits.cloneType)) out.valid := valids.map(_.valid).reduce(_ || _) out.bits := MuxCase(valids.head.bits, valids.map(v => (v.valid -> v.bits))) out } } object Str { def apply(s: String): UInt = { var i = BigInt(0) require(s.forall(validChar _)) for (c <- s) i = (i << 8) | c i.U((s.length*8).W) } def apply(x: Char): UInt = { require(validChar(x)) x.U(8.W) } def apply(x: UInt): UInt = apply(x, 10) def apply(x: UInt, radix: Int): UInt = { val rad = radix.U val w = x.getWidth require(w > 0) var q = x var s = digit(q % rad) for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s) } s } def apply(x: SInt): UInt = apply(x, 10) def apply(x: SInt, radix: Int): UInt = { val neg = x < 0.S val abs = x.abs.asUInt if (radix != 10) { Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix)) } else { val rad = radix.U val w = abs.getWidth require(w > 0) var q = abs var s = digit(q % rad) var needSign = neg for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad val placeSpace = q === 0.U val space = Mux(needSign, Str('-'), Str(' ')) needSign = needSign && !placeSpace s = Cat(Mux(placeSpace, space, digit(q % rad)), s) } Cat(Mux(needSign, Str('-'), Str(' ')), s) } } private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0) private def validChar(x: Char) = x == (x & 0xFF) } object Split { def apply(x: UInt, n0: Int) = { val w = x.getWidth (x.extract(w-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n2: Int, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } } object Random { def apply(mod: Int, random: UInt): UInt = { if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0) else PriorityEncoder(partition(apply(1 << log2Up(mod*8), random), mod)) } def apply(mod: Int): UInt = apply(mod, randomizer) def oneHot(mod: Int, random: UInt): UInt = { if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0)) else PriorityEncoderOH(partition(apply(1 << log2Up(mod*8), random), mod)).asUInt } def oneHot(mod: Int): UInt = oneHot(mod, randomizer) private def randomizer = LFSR(16) private def partition(value: UInt, slices: Int) = Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U) } object Majority { def apply(in: Set[Bool]): Bool = { val n = (in.size >> 1) + 1 val clauses = in.subsets(n).map(_.reduce(_ && _)) clauses.reduce(_ || _) } def apply(in: Seq[Bool]): Bool = apply(in.toSet) def apply(in: UInt): Bool = apply(in.asBools.toSet) } object PopCountAtLeast { private def two(x: UInt): (Bool, Bool) = x.getWidth match { case 1 => (x.asBool, false.B) case n => val half = x.getWidth / 2 val (leftOne, leftTwo) = two(x(half - 1, 0)) val (rightOne, rightTwo) = two(x(x.getWidth - 1, half)) (leftOne || rightOne, leftTwo || rightTwo || (leftOne && rightOne)) } def apply(x: UInt, n: Int): Bool = n match { case 0 => true.B case 1 => x.orR case 2 => two(x)._2 case 3 => PopCount(x) >= n.U } } // This gets used everywhere, so make the smallest circuit possible ... // Given an address and size, create a mask of beatBytes size // eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111 // groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01 object MaskGen { def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = { require (groupBy >= 1 && beatBytes >= groupBy) require (isPow2(beatBytes) && isPow2(groupBy)) val lgBytes = log2Ceil(beatBytes) val sizeOH = UIntToOH(lgSize | 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) | (groupBy*2 - 1).U def helper(i: Int): Seq[(Bool, Bool)] = { if (i == 0) { Seq((lgSize >= lgBytes.asUInt, true.B)) } else { val sub = helper(i-1) val size = sizeOH(lgBytes - i) val bit = addr_lo(lgBytes - i) val nbit = !bit Seq.tabulate (1 << i) { j => val (sub_acc, sub_eq) = sub(j/2) val eq = sub_eq && (if (j % 2 == 1) bit else nbit) val acc = sub_acc || (size && eq) (acc, eq) } } } if (groupBy == beatBytes) 1.U else Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse) } } File PlusArg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.experimental._ import chisel3.util.HasBlackBoxResource @deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05") case class PlusArgInfo(default: BigInt, docstring: String) /** Case class for PlusArg information * * @tparam A scala type of the PlusArg value * @param default optional default value * @param docstring text to include in the help * @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT) */ private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String) /** Typeclass for converting a type to a doctype string * @tparam A some type */ trait Doctypeable[A] { /** Return the doctype string for some option */ def toDoctype(a: Option[A]): String } /** Object containing implementations of the Doctypeable typeclass */ object Doctypes { /** Converts an Int => "INT" */ implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" } /** Converts a BigInt => "INT" */ implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" } /** Converts a String => "STRING" */ implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" } } class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map( "FORMAT" -> StringParam(format), "DEFAULT" -> IntParam(default), "WIDTH" -> IntParam(width) )) with HasBlackBoxResource { val io = IO(new Bundle { val out = Output(UInt(width.W)) }) addResource("/vsrc/plusarg_reader.v") } /* This wrapper class has no outputs, making it clear it is a simulation-only construct */ class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module { val io = IO(new Bundle { val count = Input(UInt(width.W)) }) val max = Module(new plusarg_reader(format, default, docstring, width)).io.out when (max > 0.U) { assert (io.count < max, s"Timeout exceeded: $docstring") } } import Doctypes._ object PlusArg { /** PlusArg("foo") will return 42.U if the simulation is run with +foo=42 * Do not use this as an initial register value. The value is set in an * initial block and thus accessing it from another initial is racey. * Add a docstring to document the arg, which can be dumped in an elaboration * pass. */ def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out } /** PlusArg.timeout(name, default, docstring)(count) will use chisel.assert * to kill the simulation when count exceeds the specified integer argument. * Default 0 will never assert. */ def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count } } object PlusArgArtefacts { private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty /* Add a new PlusArg */ @deprecated( "Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05" ) def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring) /** Add a new PlusArg * * @tparam A scala type of the PlusArg value * @param name name for the PlusArg * @param default optional default value * @param docstring text to include in the help */ def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit = artefacts = artefacts ++ Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default))) /* From plus args, generate help text */ private def serializeHelp_cHeader(tab: String = ""): String = artefacts .map{ case(arg, info) => s"""|$tab+$arg=${info.doctype}\\n\\ |$tab${" "*20}${info.docstring}\\n\\ |""".stripMargin ++ info.default.map{ case default => s"$tab${" "*22}(default=${default})\\n\\\n"}.getOrElse("") }.toSeq.mkString("\\n\\\n") ++ "\"" /* From plus args, generate a char array of their names */ private def serializeArray_cHeader(tab: String = ""): String = { val prettyTab = tab + " " * 44 // Length of 'static const ...' s"${tab}static const char * verilog_plusargs [] = {\\\n" ++ artefacts .map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" } .mkString("")++ s"${prettyTab}0};" } /* Generate C code to be included in emulator.cc that helps with * argument parsing based on available Verilog PlusArgs */ def serialize_cHeader(): String = s"""|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\ |${serializeHelp_cHeader(" "*7)} |${serializeArray_cHeader()} |""".stripMargin } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /** Like Vec.apply(idx), but tolerates indices of mismatched width */ def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /** Any Data subtype that has a Bool member named valid. */ type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /** converts from camel case to to underscores, also removing all spaces */ def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /** converts spaces or underscores to hyphens, also lowering case */ def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y | (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y || y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /** Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation */ def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Bundles.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import freechips.rocketchip.util._ import scala.collection.immutable.ListMap import chisel3.util.Decoupled import chisel3.util.DecoupledIO import chisel3.reflect.DataMirror abstract class TLBundleBase(val params: TLBundleParameters) extends Bundle // common combos in lazy policy: // Put + Acquire // Release + AccessAck object TLMessages { // A B C D E def PutFullData = 0.U // . . => AccessAck def PutPartialData = 1.U // . . => AccessAck def ArithmeticData = 2.U // . . => AccessAckData def LogicalData = 3.U // . . => AccessAckData def Get = 4.U // . . => AccessAckData def Hint = 5.U // . . => HintAck def AcquireBlock = 6.U // . => Grant[Data] def AcquirePerm = 7.U // . => Grant[Data] def Probe = 6.U // . => ProbeAck[Data] def AccessAck = 0.U // . . def AccessAckData = 1.U // . . def HintAck = 2.U // . . def ProbeAck = 4.U // . def ProbeAckData = 5.U // . def Release = 6.U // . => ReleaseAck def ReleaseData = 7.U // . => ReleaseAck def Grant = 4.U // . => GrantAck def GrantData = 5.U // . => GrantAck def ReleaseAck = 6.U // . def GrantAck = 0.U // . def isA(x: UInt) = x <= AcquirePerm def isB(x: UInt) = x <= Probe def isC(x: UInt) = x <= ReleaseData def isD(x: UInt) = x <= ReleaseAck def adResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, Grant, Grant) def bcResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, ProbeAck, ProbeAck) def a = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("AcquireBlock",TLPermissions.PermMsgGrow), ("AcquirePerm",TLPermissions.PermMsgGrow)) def b = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("Probe",TLPermissions.PermMsgCap)) def c = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("ProbeAck",TLPermissions.PermMsgReport), ("ProbeAckData",TLPermissions.PermMsgReport), ("Release",TLPermissions.PermMsgReport), ("ReleaseData",TLPermissions.PermMsgReport)) def d = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("Grant",TLPermissions.PermMsgCap), ("GrantData",TLPermissions.PermMsgCap), ("ReleaseAck",TLPermissions.PermMsgReserved)) } /** * The three primary TileLink permissions are: * (T)runk: the agent is (or is on inwards path to) the global point of serialization. * (B)ranch: the agent is on an outwards path to * (N)one: * These permissions are permuted by transfer operations in various ways. * Operations can cap permissions, request for them to be grown or shrunk, * or for a report on their current status. */ object TLPermissions { val aWidth = 2 val bdWidth = 2 val cWidth = 3 // Cap types (Grant = new permissions, Probe = permisions <= target) def toT = 0.U(bdWidth.W) def toB = 1.U(bdWidth.W) def toN = 2.U(bdWidth.W) def isCap(x: UInt) = x <= toN // Grow types (Acquire = permissions >= target) def NtoB = 0.U(aWidth.W) def NtoT = 1.U(aWidth.W) def BtoT = 2.U(aWidth.W) def isGrow(x: UInt) = x <= BtoT // Shrink types (ProbeAck, Release) def TtoB = 0.U(cWidth.W) def TtoN = 1.U(cWidth.W) def BtoN = 2.U(cWidth.W) def isShrink(x: UInt) = x <= BtoN // Report types (ProbeAck, Release) def TtoT = 3.U(cWidth.W) def BtoB = 4.U(cWidth.W) def NtoN = 5.U(cWidth.W) def isReport(x: UInt) = x <= NtoN def PermMsgGrow:Seq[String] = Seq("Grow NtoB", "Grow NtoT", "Grow BtoT") def PermMsgCap:Seq[String] = Seq("Cap toT", "Cap toB", "Cap toN") def PermMsgReport:Seq[String] = Seq("Shrink TtoB", "Shrink TtoN", "Shrink BtoN", "Report TotT", "Report BtoB", "Report NtoN") def PermMsgReserved:Seq[String] = Seq("Reserved") } object TLAtomics { val width = 3 // Arithmetic types def MIN = 0.U(width.W) def MAX = 1.U(width.W) def MINU = 2.U(width.W) def MAXU = 3.U(width.W) def ADD = 4.U(width.W) def isArithmetic(x: UInt) = x <= ADD // Logical types def XOR = 0.U(width.W) def OR = 1.U(width.W) def AND = 2.U(width.W) def SWAP = 3.U(width.W) def isLogical(x: UInt) = x <= SWAP def ArithMsg:Seq[String] = Seq("MIN", "MAX", "MINU", "MAXU", "ADD") def LogicMsg:Seq[String] = Seq("XOR", "OR", "AND", "SWAP") } object TLHints { val width = 1 def PREFETCH_READ = 0.U(width.W) def PREFETCH_WRITE = 1.U(width.W) def isHints(x: UInt) = x <= PREFETCH_WRITE def HintsMsg:Seq[String] = Seq("PrefetchRead", "PrefetchWrite") } sealed trait TLChannel extends TLBundleBase { val channelName: String } sealed trait TLDataChannel extends TLChannel sealed trait TLAddrChannel extends TLDataChannel final class TLBundleA(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleA_${params.shortName}" val channelName = "'A' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(List(TLAtomics.width, TLPermissions.aWidth, TLHints.width).max.W) // amo_opcode || grow perms || hint val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleB(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleB_${params.shortName}" val channelName = "'B' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val address = UInt(params.addressBits.W) // from // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleC(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleC_${params.shortName}" val channelName = "'C' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.cWidth.W) // shrink or report perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleD(params: TLBundleParameters) extends TLBundleBase(params) with TLDataChannel { override def typeName = s"TLBundleD_${params.shortName}" val channelName = "'D' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val sink = UInt(params.sinkBits.W) // from val denied = Bool() // implies corrupt iff *Data val user = BundleMap(params.responseFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleE(params: TLBundleParameters) extends TLBundleBase(params) with TLChannel { override def typeName = s"TLBundleE_${params.shortName}" val channelName = "'E' channel" val sink = UInt(params.sinkBits.W) // to } class TLBundle(val params: TLBundleParameters) extends Record { // Emulate a Bundle with elements abcde or ad depending on params.hasBCE private val optA = Some (Decoupled(new TLBundleA(params))) private val optB = params.hasBCE.option(Flipped(Decoupled(new TLBundleB(params)))) private val optC = params.hasBCE.option(Decoupled(new TLBundleC(params))) private val optD = Some (Flipped(Decoupled(new TLBundleD(params)))) private val optE = params.hasBCE.option(Decoupled(new TLBundleE(params))) def a: DecoupledIO[TLBundleA] = optA.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleA(params))))) def b: DecoupledIO[TLBundleB] = optB.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleB(params))))) def c: DecoupledIO[TLBundleC] = optC.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleC(params))))) def d: DecoupledIO[TLBundleD] = optD.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleD(params))))) def e: DecoupledIO[TLBundleE] = optE.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleE(params))))) val elements = if (params.hasBCE) ListMap("e" -> e, "d" -> d, "c" -> c, "b" -> b, "a" -> a) else ListMap("d" -> d, "a" -> a) def tieoff(): Unit = { DataMirror.specifiedDirectionOf(a.ready) match { case SpecifiedDirection.Input => a.ready := false.B c.ready := false.B e.ready := false.B b.valid := false.B d.valid := false.B case SpecifiedDirection.Output => a.valid := false.B c.valid := false.B e.valid := false.B b.ready := false.B d.ready := false.B case _ => } } } object TLBundle { def apply(params: TLBundleParameters) = new TLBundle(params) } class TLAsyncBundleBase(val params: TLAsyncBundleParameters) extends Bundle class TLAsyncBundle(params: TLAsyncBundleParameters) extends TLAsyncBundleBase(params) { val a = new AsyncBundle(new TLBundleA(params.base), params.async) val b = Flipped(new AsyncBundle(new TLBundleB(params.base), params.async)) val c = new AsyncBundle(new TLBundleC(params.base), params.async) val d = Flipped(new AsyncBundle(new TLBundleD(params.base), params.async)) val e = new AsyncBundle(new TLBundleE(params.base), params.async) } class TLRationalBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = RationalIO(new TLBundleA(params)) val b = Flipped(RationalIO(new TLBundleB(params))) val c = RationalIO(new TLBundleC(params)) val d = Flipped(RationalIO(new TLBundleD(params))) val e = RationalIO(new TLBundleE(params)) } class TLCreditedBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = CreditedIO(new TLBundleA(params)) val b = Flipped(CreditedIO(new TLBundleB(params))) val c = CreditedIO(new TLBundleC(params)) val d = Flipped(CreditedIO(new TLBundleD(params))) val e = CreditedIO(new TLBundleE(params)) } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.nodes._ import freechips.rocketchip.diplomacy.{ AddressDecoder, AddressSet, BufferParams, DirectedBuffers, IdMap, IdMapEntry, IdRange, RegionType, TransferSizes } import freechips.rocketchip.resources.{Resource, ResourceAddress, ResourcePermissions} import freechips.rocketchip.util.{ AsyncQueueParams, BundleField, BundleFieldBase, BundleKeyBase, CreditedDelay, groupByIntoSeq, RationalDirection, SimpleProduct } import scala.math.max //These transfer sizes describe requests issued from masters on the A channel that will be responded by slaves on the D channel case class TLMasterToSlaveTransferSizes( // Supports both Acquire+Release of the following two sizes: acquireT: TransferSizes = TransferSizes.none, acquireB: TransferSizes = TransferSizes.none, arithmetic: TransferSizes = TransferSizes.none, logical: TransferSizes = TransferSizes.none, get: TransferSizes = TransferSizes.none, putFull: TransferSizes = TransferSizes.none, putPartial: TransferSizes = TransferSizes.none, hint: TransferSizes = TransferSizes.none) extends TLCommonTransferSizes { def intersect(rhs: TLMasterToSlaveTransferSizes) = TLMasterToSlaveTransferSizes( acquireT = acquireT .intersect(rhs.acquireT), acquireB = acquireB .intersect(rhs.acquireB), arithmetic = arithmetic.intersect(rhs.arithmetic), logical = logical .intersect(rhs.logical), get = get .intersect(rhs.get), putFull = putFull .intersect(rhs.putFull), putPartial = putPartial.intersect(rhs.putPartial), hint = hint .intersect(rhs.hint)) def mincover(rhs: TLMasterToSlaveTransferSizes) = TLMasterToSlaveTransferSizes( acquireT = acquireT .mincover(rhs.acquireT), acquireB = acquireB .mincover(rhs.acquireB), arithmetic = arithmetic.mincover(rhs.arithmetic), logical = logical .mincover(rhs.logical), get = get .mincover(rhs.get), putFull = putFull .mincover(rhs.putFull), putPartial = putPartial.mincover(rhs.putPartial), hint = hint .mincover(rhs.hint)) // Reduce rendering to a simple yes/no per field override def toString = { def str(x: TransferSizes, flag: String) = if (x.none) "" else flag def flags = Vector( str(acquireT, "T"), str(acquireB, "B"), str(arithmetic, "A"), str(logical, "L"), str(get, "G"), str(putFull, "F"), str(putPartial, "P"), str(hint, "H")) flags.mkString } // Prints out the actual information in a user readable way def infoString = { s"""acquireT = ${acquireT} |acquireB = ${acquireB} |arithmetic = ${arithmetic} |logical = ${logical} |get = ${get} |putFull = ${putFull} |putPartial = ${putPartial} |hint = ${hint} | |""".stripMargin } } object TLMasterToSlaveTransferSizes { def unknownEmits = TLMasterToSlaveTransferSizes( acquireT = TransferSizes(1, 4096), acquireB = TransferSizes(1, 4096), arithmetic = TransferSizes(1, 4096), logical = TransferSizes(1, 4096), get = TransferSizes(1, 4096), putFull = TransferSizes(1, 4096), putPartial = TransferSizes(1, 4096), hint = TransferSizes(1, 4096)) def unknownSupports = TLMasterToSlaveTransferSizes() } //These transfer sizes describe requests issued from slaves on the B channel that will be responded by masters on the C channel case class TLSlaveToMasterTransferSizes( probe: TransferSizes = TransferSizes.none, arithmetic: TransferSizes = TransferSizes.none, logical: TransferSizes = TransferSizes.none, get: TransferSizes = TransferSizes.none, putFull: TransferSizes = TransferSizes.none, putPartial: TransferSizes = TransferSizes.none, hint: TransferSizes = TransferSizes.none ) extends TLCommonTransferSizes { def intersect(rhs: TLSlaveToMasterTransferSizes) = TLSlaveToMasterTransferSizes( probe = probe .intersect(rhs.probe), arithmetic = arithmetic.intersect(rhs.arithmetic), logical = logical .intersect(rhs.logical), get = get .intersect(rhs.get), putFull = putFull .intersect(rhs.putFull), putPartial = putPartial.intersect(rhs.putPartial), hint = hint .intersect(rhs.hint) ) def mincover(rhs: TLSlaveToMasterTransferSizes) = TLSlaveToMasterTransferSizes( probe = probe .mincover(rhs.probe), arithmetic = arithmetic.mincover(rhs.arithmetic), logical = logical .mincover(rhs.logical), get = get .mincover(rhs.get), putFull = putFull .mincover(rhs.putFull), putPartial = putPartial.mincover(rhs.putPartial), hint = hint .mincover(rhs.hint) ) // Reduce rendering to a simple yes/no per field override def toString = { def str(x: TransferSizes, flag: String) = if (x.none) "" else flag def flags = Vector( str(probe, "P"), str(arithmetic, "A"), str(logical, "L"), str(get, "G"), str(putFull, "F"), str(putPartial, "P"), str(hint, "H")) flags.mkString } // Prints out the actual information in a user readable way def infoString = { s"""probe = ${probe} |arithmetic = ${arithmetic} |logical = ${logical} |get = ${get} |putFull = ${putFull} |putPartial = ${putPartial} |hint = ${hint} | |""".stripMargin } } object TLSlaveToMasterTransferSizes { def unknownEmits = TLSlaveToMasterTransferSizes( arithmetic = TransferSizes(1, 4096), logical = TransferSizes(1, 4096), get = TransferSizes(1, 4096), putFull = TransferSizes(1, 4096), putPartial = TransferSizes(1, 4096), hint = TransferSizes(1, 4096), probe = TransferSizes(1, 4096)) def unknownSupports = TLSlaveToMasterTransferSizes() } trait TLCommonTransferSizes { def arithmetic: TransferSizes def logical: TransferSizes def get: TransferSizes def putFull: TransferSizes def putPartial: TransferSizes def hint: TransferSizes } class TLSlaveParameters private( val nodePath: Seq[BaseNode], val resources: Seq[Resource], setName: Option[String], val address: Seq[AddressSet], val regionType: RegionType.T, val executable: Boolean, val fifoId: Option[Int], val supports: TLMasterToSlaveTransferSizes, val emits: TLSlaveToMasterTransferSizes, // By default, slaves are forbidden from issuing 'denied' responses (it prevents Fragmentation) val alwaysGrantsT: Boolean, // typically only true for CacheCork'd read-write devices; dual: neverReleaseData // If fifoId=Some, all accesses sent to the same fifoId are executed and ACK'd in FIFO order // Note: you can only rely on this FIFO behaviour if your TLMasterParameters include requestFifo val mayDenyGet: Boolean, // applies to: AccessAckData, GrantData val mayDenyPut: Boolean) // applies to: AccessAck, Grant, HintAck // ReleaseAck may NEVER be denied extends SimpleProduct { def sortedAddress = address.sorted override def canEqual(that: Any): Boolean = that.isInstanceOf[TLSlaveParameters] override def productPrefix = "TLSlaveParameters" // We intentionally omit nodePath for equality testing / formatting def productArity: Int = 11 def productElement(n: Int): Any = n match { case 0 => name case 1 => address case 2 => resources case 3 => regionType case 4 => executable case 5 => fifoId case 6 => supports case 7 => emits case 8 => alwaysGrantsT case 9 => mayDenyGet case 10 => mayDenyPut case _ => throw new IndexOutOfBoundsException(n.toString) } def supportsAcquireT: TransferSizes = supports.acquireT def supportsAcquireB: TransferSizes = supports.acquireB def supportsArithmetic: TransferSizes = supports.arithmetic def supportsLogical: TransferSizes = supports.logical def supportsGet: TransferSizes = supports.get def supportsPutFull: TransferSizes = supports.putFull def supportsPutPartial: TransferSizes = supports.putPartial def supportsHint: TransferSizes = supports.hint require (!address.isEmpty, "Address cannot be empty") address.foreach { a => require (a.finite, "Address must be finite") } address.combinations(2).foreach { case Seq(x,y) => require (!x.overlaps(y), s"$x and $y overlap.") } require (supportsPutFull.contains(supportsPutPartial), s"PutFull($supportsPutFull) < PutPartial($supportsPutPartial)") require (supportsPutFull.contains(supportsArithmetic), s"PutFull($supportsPutFull) < Arithmetic($supportsArithmetic)") require (supportsPutFull.contains(supportsLogical), s"PutFull($supportsPutFull) < Logical($supportsLogical)") require (supportsGet.contains(supportsArithmetic), s"Get($supportsGet) < Arithmetic($supportsArithmetic)") require (supportsGet.contains(supportsLogical), s"Get($supportsGet) < Logical($supportsLogical)") require (supportsAcquireB.contains(supportsAcquireT), s"AcquireB($supportsAcquireB) < AcquireT($supportsAcquireT)") require (!alwaysGrantsT || supportsAcquireT, s"Must supportAcquireT if promising to always grantT") // Make sure that the regionType agrees with the capabilities require (!supportsAcquireB || regionType >= RegionType.UNCACHED) // acquire -> uncached, tracked, cached require (regionType <= RegionType.UNCACHED || supportsAcquireB) // tracked, cached -> acquire require (regionType != RegionType.UNCACHED || supportsGet) // uncached -> supportsGet val name = setName.orElse(nodePath.lastOption.map(_.lazyModule.name)).getOrElse("disconnected") val maxTransfer = List( // Largest supported transfer of all types supportsAcquireT.max, supportsAcquireB.max, supportsArithmetic.max, supportsLogical.max, supportsGet.max, supportsPutFull.max, supportsPutPartial.max).max val maxAddress = address.map(_.max).max val minAlignment = address.map(_.alignment).min // The device had better not support a transfer larger than its alignment require (minAlignment >= maxTransfer, s"Bad $address: minAlignment ($minAlignment) must be >= maxTransfer ($maxTransfer)") def toResource: ResourceAddress = { ResourceAddress(address, ResourcePermissions( r = supportsAcquireB || supportsGet, w = supportsAcquireT || supportsPutFull, x = executable, c = supportsAcquireB, a = supportsArithmetic && supportsLogical)) } def findTreeViolation() = nodePath.find { case _: MixedAdapterNode[_, _, _, _, _, _, _, _] => false case _: SinkNode[_, _, _, _, _] => false case node => node.inputs.size != 1 } def isTree = findTreeViolation() == None def infoString = { s"""Slave Name = ${name} |Slave Address = ${address} |supports = ${supports.infoString} | |""".stripMargin } def v1copy( address: Seq[AddressSet] = address, resources: Seq[Resource] = resources, regionType: RegionType.T = regionType, executable: Boolean = executable, nodePath: Seq[BaseNode] = nodePath, supportsAcquireT: TransferSizes = supports.acquireT, supportsAcquireB: TransferSizes = supports.acquireB, supportsArithmetic: TransferSizes = supports.arithmetic, supportsLogical: TransferSizes = supports.logical, supportsGet: TransferSizes = supports.get, supportsPutFull: TransferSizes = supports.putFull, supportsPutPartial: TransferSizes = supports.putPartial, supportsHint: TransferSizes = supports.hint, mayDenyGet: Boolean = mayDenyGet, mayDenyPut: Boolean = mayDenyPut, alwaysGrantsT: Boolean = alwaysGrantsT, fifoId: Option[Int] = fifoId) = { new TLSlaveParameters( setName = setName, address = address, resources = resources, regionType = regionType, executable = executable, nodePath = nodePath, supports = TLMasterToSlaveTransferSizes( acquireT = supportsAcquireT, acquireB = supportsAcquireB, arithmetic = supportsArithmetic, logical = supportsLogical, get = supportsGet, putFull = supportsPutFull, putPartial = supportsPutPartial, hint = supportsHint), emits = emits, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut, alwaysGrantsT = alwaysGrantsT, fifoId = fifoId) } def v2copy( nodePath: Seq[BaseNode] = nodePath, resources: Seq[Resource] = resources, name: Option[String] = setName, address: Seq[AddressSet] = address, regionType: RegionType.T = regionType, executable: Boolean = executable, fifoId: Option[Int] = fifoId, supports: TLMasterToSlaveTransferSizes = supports, emits: TLSlaveToMasterTransferSizes = emits, alwaysGrantsT: Boolean = alwaysGrantsT, mayDenyGet: Boolean = mayDenyGet, mayDenyPut: Boolean = mayDenyPut) = { new TLSlaveParameters( nodePath = nodePath, resources = resources, setName = name, address = address, regionType = regionType, executable = executable, fifoId = fifoId, supports = supports, emits = emits, alwaysGrantsT = alwaysGrantsT, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut) } @deprecated("Use v1copy instead of copy","") def copy( address: Seq[AddressSet] = address, resources: Seq[Resource] = resources, regionType: RegionType.T = regionType, executable: Boolean = executable, nodePath: Seq[BaseNode] = nodePath, supportsAcquireT: TransferSizes = supports.acquireT, supportsAcquireB: TransferSizes = supports.acquireB, supportsArithmetic: TransferSizes = supports.arithmetic, supportsLogical: TransferSizes = supports.logical, supportsGet: TransferSizes = supports.get, supportsPutFull: TransferSizes = supports.putFull, supportsPutPartial: TransferSizes = supports.putPartial, supportsHint: TransferSizes = supports.hint, mayDenyGet: Boolean = mayDenyGet, mayDenyPut: Boolean = mayDenyPut, alwaysGrantsT: Boolean = alwaysGrantsT, fifoId: Option[Int] = fifoId) = { v1copy( address = address, resources = resources, regionType = regionType, executable = executable, nodePath = nodePath, supportsAcquireT = supportsAcquireT, supportsAcquireB = supportsAcquireB, supportsArithmetic = supportsArithmetic, supportsLogical = supportsLogical, supportsGet = supportsGet, supportsPutFull = supportsPutFull, supportsPutPartial = supportsPutPartial, supportsHint = supportsHint, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut, alwaysGrantsT = alwaysGrantsT, fifoId = fifoId) } } object TLSlaveParameters { def v1( address: Seq[AddressSet], resources: Seq[Resource] = Seq(), regionType: RegionType.T = RegionType.GET_EFFECTS, executable: Boolean = false, nodePath: Seq[BaseNode] = Seq(), supportsAcquireT: TransferSizes = TransferSizes.none, supportsAcquireB: TransferSizes = TransferSizes.none, supportsArithmetic: TransferSizes = TransferSizes.none, supportsLogical: TransferSizes = TransferSizes.none, supportsGet: TransferSizes = TransferSizes.none, supportsPutFull: TransferSizes = TransferSizes.none, supportsPutPartial: TransferSizes = TransferSizes.none, supportsHint: TransferSizes = TransferSizes.none, mayDenyGet: Boolean = false, mayDenyPut: Boolean = false, alwaysGrantsT: Boolean = false, fifoId: Option[Int] = None) = { new TLSlaveParameters( setName = None, address = address, resources = resources, regionType = regionType, executable = executable, nodePath = nodePath, supports = TLMasterToSlaveTransferSizes( acquireT = supportsAcquireT, acquireB = supportsAcquireB, arithmetic = supportsArithmetic, logical = supportsLogical, get = supportsGet, putFull = supportsPutFull, putPartial = supportsPutPartial, hint = supportsHint), emits = TLSlaveToMasterTransferSizes.unknownEmits, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut, alwaysGrantsT = alwaysGrantsT, fifoId = fifoId) } def v2( address: Seq[AddressSet], nodePath: Seq[BaseNode] = Seq(), resources: Seq[Resource] = Seq(), name: Option[String] = None, regionType: RegionType.T = RegionType.GET_EFFECTS, executable: Boolean = false, fifoId: Option[Int] = None, supports: TLMasterToSlaveTransferSizes = TLMasterToSlaveTransferSizes.unknownSupports, emits: TLSlaveToMasterTransferSizes = TLSlaveToMasterTransferSizes.unknownEmits, alwaysGrantsT: Boolean = false, mayDenyGet: Boolean = false, mayDenyPut: Boolean = false) = { new TLSlaveParameters( nodePath = nodePath, resources = resources, setName = name, address = address, regionType = regionType, executable = executable, fifoId = fifoId, supports = supports, emits = emits, alwaysGrantsT = alwaysGrantsT, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut) } } object TLManagerParameters { @deprecated("Use TLSlaveParameters.v1 instead of TLManagerParameters","") def apply( address: Seq[AddressSet], resources: Seq[Resource] = Seq(), regionType: RegionType.T = RegionType.GET_EFFECTS, executable: Boolean = false, nodePath: Seq[BaseNode] = Seq(), supportsAcquireT: TransferSizes = TransferSizes.none, supportsAcquireB: TransferSizes = TransferSizes.none, supportsArithmetic: TransferSizes = TransferSizes.none, supportsLogical: TransferSizes = TransferSizes.none, supportsGet: TransferSizes = TransferSizes.none, supportsPutFull: TransferSizes = TransferSizes.none, supportsPutPartial: TransferSizes = TransferSizes.none, supportsHint: TransferSizes = TransferSizes.none, mayDenyGet: Boolean = false, mayDenyPut: Boolean = false, alwaysGrantsT: Boolean = false, fifoId: Option[Int] = None) = TLSlaveParameters.v1( address, resources, regionType, executable, nodePath, supportsAcquireT, supportsAcquireB, supportsArithmetic, supportsLogical, supportsGet, supportsPutFull, supportsPutPartial, supportsHint, mayDenyGet, mayDenyPut, alwaysGrantsT, fifoId, ) } case class TLChannelBeatBytes(a: Option[Int], b: Option[Int], c: Option[Int], d: Option[Int]) { def members = Seq(a, b, c, d) members.collect { case Some(beatBytes) => require (isPow2(beatBytes), "Data channel width must be a power of 2") } } object TLChannelBeatBytes{ def apply(beatBytes: Int): TLChannelBeatBytes = TLChannelBeatBytes( Some(beatBytes), Some(beatBytes), Some(beatBytes), Some(beatBytes)) def apply(): TLChannelBeatBytes = TLChannelBeatBytes( None, None, None, None) } class TLSlavePortParameters private( val slaves: Seq[TLSlaveParameters], val channelBytes: TLChannelBeatBytes, val endSinkId: Int, val minLatency: Int, val responseFields: Seq[BundleFieldBase], val requestKeys: Seq[BundleKeyBase]) extends SimpleProduct { def sortedSlaves = slaves.sortBy(_.sortedAddress.head) override def canEqual(that: Any): Boolean = that.isInstanceOf[TLSlavePortParameters] override def productPrefix = "TLSlavePortParameters" def productArity: Int = 6 def productElement(n: Int): Any = n match { case 0 => slaves case 1 => channelBytes case 2 => endSinkId case 3 => minLatency case 4 => responseFields case 5 => requestKeys case _ => throw new IndexOutOfBoundsException(n.toString) } require (!slaves.isEmpty, "Slave ports must have slaves") require (endSinkId >= 0, "Sink ids cannot be negative") require (minLatency >= 0, "Minimum required latency cannot be negative") // Using this API implies you cannot handle mixed-width busses def beatBytes = { channelBytes.members.foreach { width => require (width.isDefined && width == channelBytes.a) } channelBytes.a.get } // TODO this should be deprecated def managers = slaves def requireFifo(policy: TLFIFOFixer.Policy = TLFIFOFixer.allFIFO) = { val relevant = slaves.filter(m => policy(m)) relevant.foreach { m => require(m.fifoId == relevant.head.fifoId, s"${m.name} had fifoId ${m.fifoId}, which was not homogeneous (${slaves.map(s => (s.name, s.fifoId))}) ") } } // Bounds on required sizes def maxAddress = slaves.map(_.maxAddress).max def maxTransfer = slaves.map(_.maxTransfer).max def mayDenyGet = slaves.exists(_.mayDenyGet) def mayDenyPut = slaves.exists(_.mayDenyPut) // Diplomatically determined operation sizes emitted by all outward Slaves // as opposed to emits* which generate circuitry to check which specific addresses val allEmitClaims = slaves.map(_.emits).reduce( _ intersect _) // Operation Emitted by at least one outward Slaves // as opposed to emits* which generate circuitry to check which specific addresses val anyEmitClaims = slaves.map(_.emits).reduce(_ mincover _) // Diplomatically determined operation sizes supported by all outward Slaves // as opposed to supports* which generate circuitry to check which specific addresses val allSupportClaims = slaves.map(_.supports).reduce( _ intersect _) val allSupportAcquireT = allSupportClaims.acquireT val allSupportAcquireB = allSupportClaims.acquireB val allSupportArithmetic = allSupportClaims.arithmetic val allSupportLogical = allSupportClaims.logical val allSupportGet = allSupportClaims.get val allSupportPutFull = allSupportClaims.putFull val allSupportPutPartial = allSupportClaims.putPartial val allSupportHint = allSupportClaims.hint // Operation supported by at least one outward Slaves // as opposed to supports* which generate circuitry to check which specific addresses val anySupportClaims = slaves.map(_.supports).reduce(_ mincover _) val anySupportAcquireT = !anySupportClaims.acquireT.none val anySupportAcquireB = !anySupportClaims.acquireB.none val anySupportArithmetic = !anySupportClaims.arithmetic.none val anySupportLogical = !anySupportClaims.logical.none val anySupportGet = !anySupportClaims.get.none val anySupportPutFull = !anySupportClaims.putFull.none val anySupportPutPartial = !anySupportClaims.putPartial.none val anySupportHint = !anySupportClaims.hint.none // Supporting Acquire means being routable for GrantAck require ((endSinkId == 0) == !anySupportAcquireB) // These return Option[TLSlaveParameters] for your convenience def find(address: BigInt) = slaves.find(_.address.exists(_.contains(address))) // The safe version will check the entire address def findSafe(address: UInt) = VecInit(sortedSlaves.map(_.address.map(_.contains(address)).reduce(_ || _))) // The fast version assumes the address is valid (you probably want fastProperty instead of this function) def findFast(address: UInt) = { val routingMask = AddressDecoder(slaves.map(_.address)) VecInit(sortedSlaves.map(_.address.map(_.widen(~routingMask)).distinct.map(_.contains(address)).reduce(_ || _))) } // Compute the simplest AddressSets that decide a key def fastPropertyGroup[K](p: TLSlaveParameters => K): Seq[(K, Seq[AddressSet])] = { val groups = groupByIntoSeq(sortedSlaves.map(m => (p(m), m.address)))( _._1).map { case (k, vs) => k -> vs.flatMap(_._2) } val reductionMask = AddressDecoder(groups.map(_._2)) groups.map { case (k, seq) => k -> AddressSet.unify(seq.map(_.widen(~reductionMask)).distinct) } } // Select a property def fastProperty[K, D <: Data](address: UInt, p: TLSlaveParameters => K, d: K => D): D = Mux1H(fastPropertyGroup(p).map { case (v, a) => (a.map(_.contains(address)).reduce(_||_), d(v)) }) // Note: returns the actual fifoId + 1 or 0 if None def findFifoIdFast(address: UInt) = fastProperty(address, _.fifoId.map(_+1).getOrElse(0), (i:Int) => i.U) def hasFifoIdFast(address: UInt) = fastProperty(address, _.fifoId.isDefined, (b:Boolean) => b.B) // Does this Port manage this ID/address? def containsSafe(address: UInt) = findSafe(address).reduce(_ || _) private def addressHelper( // setting safe to false indicates that all addresses are expected to be legal, which might reduce circuit complexity safe: Boolean, // member filters out the sizes being checked based on the opcode being emitted or supported member: TLSlaveParameters => TransferSizes, address: UInt, lgSize: UInt, // range provides a limit on the sizes that are expected to be evaluated, which might reduce circuit complexity range: Option[TransferSizes]): Bool = { // trim reduces circuit complexity by intersecting checked sizes with the range argument def trim(x: TransferSizes) = range.map(_.intersect(x)).getOrElse(x) // groupBy returns an unordered map, convert back to Seq and sort the result for determinism // groupByIntoSeq is turning slaves into trimmed membership sizes // We are grouping all the slaves by their transfer size where // if they support the trimmed size then // member is the type of transfer that you are looking for (What you are trying to filter on) // When you consider membership, you are trimming the sizes to only the ones that you care about // you are filtering the slaves based on both whether they support a particular opcode and the size // Grouping the slaves based on the actual transfer size range they support // intersecting the range and checking their membership // FOR SUPPORTCASES instead of returning the list of slaves, // you are returning a map from transfer size to the set of // address sets that are supported for that transfer size // find all the slaves that support a certain type of operation and then group their addresses by the supported size // for every size there could be multiple address ranges // safety is a trade off between checking between all possible addresses vs only the addresses // that are known to have supported sizes // the trade off is 'checking all addresses is a more expensive circuit but will always give you // the right answer even if you give it an illegal address' // the not safe version is a cheaper circuit but if you give it an illegal address then it might produce the wrong answer // fast presumes address legality // This groupByIntoSeq deterministically groups all address sets for which a given `member` transfer size applies. // In the resulting Map of cases, the keys are transfer sizes and the values are all address sets which emit or support that size. val supportCases = groupByIntoSeq(slaves)(m => trim(member(m))).map { case (k: TransferSizes, vs: Seq[TLSlaveParameters]) => k -> vs.flatMap(_.address) } // safe produces a circuit that compares against all possible addresses, // whereas fast presumes that the address is legal but uses an efficient address decoder val mask = if (safe) ~BigInt(0) else AddressDecoder(supportCases.map(_._2)) // Simplified creates the most concise possible representation of each cases' address sets based on the mask. val simplified = supportCases.map { case (k, seq) => k -> AddressSet.unify(seq.map(_.widen(~mask)).distinct) } simplified.map { case (s, a) => // s is a size, you are checking for this size either the size of the operation is in s // We return an or-reduction of all the cases, checking whether any contains both the dynamic size and dynamic address on the wire. ((Some(s) == range).B || s.containsLg(lgSize)) && a.map(_.contains(address)).reduce(_||_) }.foldLeft(false.B)(_||_) } def supportsAcquireTSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.acquireT, address, lgSize, range) def supportsAcquireBSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.acquireB, address, lgSize, range) def supportsArithmeticSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.arithmetic, address, lgSize, range) def supportsLogicalSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.logical, address, lgSize, range) def supportsGetSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.get, address, lgSize, range) def supportsPutFullSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.putFull, address, lgSize, range) def supportsPutPartialSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.putPartial, address, lgSize, range) def supportsHintSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.hint, address, lgSize, range) def supportsAcquireTFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.acquireT, address, lgSize, range) def supportsAcquireBFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.acquireB, address, lgSize, range) def supportsArithmeticFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.arithmetic, address, lgSize, range) def supportsLogicalFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.logical, address, lgSize, range) def supportsGetFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.get, address, lgSize, range) def supportsPutFullFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.putFull, address, lgSize, range) def supportsPutPartialFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.putPartial, address, lgSize, range) def supportsHintFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.hint, address, lgSize, range) def emitsProbeSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.probe, address, lgSize, range) def emitsArithmeticSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.arithmetic, address, lgSize, range) def emitsLogicalSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.logical, address, lgSize, range) def emitsGetSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.get, address, lgSize, range) def emitsPutFullSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.putFull, address, lgSize, range) def emitsPutPartialSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.putPartial, address, lgSize, range) def emitsHintSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.hint, address, lgSize, range) def findTreeViolation() = slaves.flatMap(_.findTreeViolation()).headOption def isTree = !slaves.exists(!_.isTree) def infoString = "Slave Port Beatbytes = " + beatBytes + "\n" + "Slave Port MinLatency = " + minLatency + "\n\n" + slaves.map(_.infoString).mkString def v1copy( managers: Seq[TLSlaveParameters] = slaves, beatBytes: Int = -1, endSinkId: Int = endSinkId, minLatency: Int = minLatency, responseFields: Seq[BundleFieldBase] = responseFields, requestKeys: Seq[BundleKeyBase] = requestKeys) = { new TLSlavePortParameters( slaves = managers, channelBytes = if (beatBytes != -1) TLChannelBeatBytes(beatBytes) else channelBytes, endSinkId = endSinkId, minLatency = minLatency, responseFields = responseFields, requestKeys = requestKeys) } def v2copy( slaves: Seq[TLSlaveParameters] = slaves, channelBytes: TLChannelBeatBytes = channelBytes, endSinkId: Int = endSinkId, minLatency: Int = minLatency, responseFields: Seq[BundleFieldBase] = responseFields, requestKeys: Seq[BundleKeyBase] = requestKeys) = { new TLSlavePortParameters( slaves = slaves, channelBytes = channelBytes, endSinkId = endSinkId, minLatency = minLatency, responseFields = responseFields, requestKeys = requestKeys) } @deprecated("Use v1copy instead of copy","") def copy( managers: Seq[TLSlaveParameters] = slaves, beatBytes: Int = -1, endSinkId: Int = endSinkId, minLatency: Int = minLatency, responseFields: Seq[BundleFieldBase] = responseFields, requestKeys: Seq[BundleKeyBase] = requestKeys) = { v1copy( managers, beatBytes, endSinkId, minLatency, responseFields, requestKeys) } } object TLSlavePortParameters { def v1( managers: Seq[TLSlaveParameters], beatBytes: Int, endSinkId: Int = 0, minLatency: Int = 0, responseFields: Seq[BundleFieldBase] = Nil, requestKeys: Seq[BundleKeyBase] = Nil) = { new TLSlavePortParameters( slaves = managers, channelBytes = TLChannelBeatBytes(beatBytes), endSinkId = endSinkId, minLatency = minLatency, responseFields = responseFields, requestKeys = requestKeys) } } object TLManagerPortParameters { @deprecated("Use TLSlavePortParameters.v1 instead of TLManagerPortParameters","") def apply( managers: Seq[TLSlaveParameters], beatBytes: Int, endSinkId: Int = 0, minLatency: Int = 0, responseFields: Seq[BundleFieldBase] = Nil, requestKeys: Seq[BundleKeyBase] = Nil) = { TLSlavePortParameters.v1( managers, beatBytes, endSinkId, minLatency, responseFields, requestKeys) } } class TLMasterParameters private( val nodePath: Seq[BaseNode], val resources: Seq[Resource], val name: String, val visibility: Seq[AddressSet], val unusedRegionTypes: Set[RegionType.T], val executesOnly: Boolean, val requestFifo: Boolean, // only a request, not a requirement. applies to A, not C. val supports: TLSlaveToMasterTransferSizes, val emits: TLMasterToSlaveTransferSizes, val neverReleasesData: Boolean, val sourceId: IdRange) extends SimpleProduct { override def canEqual(that: Any): Boolean = that.isInstanceOf[TLMasterParameters] override def productPrefix = "TLMasterParameters" // We intentionally omit nodePath for equality testing / formatting def productArity: Int = 10 def productElement(n: Int): Any = n match { case 0 => name case 1 => sourceId case 2 => resources case 3 => visibility case 4 => unusedRegionTypes case 5 => executesOnly case 6 => requestFifo case 7 => supports case 8 => emits case 9 => neverReleasesData case _ => throw new IndexOutOfBoundsException(n.toString) } require (!sourceId.isEmpty) require (!visibility.isEmpty) require (supports.putFull.contains(supports.putPartial)) // We only support these operations if we support Probe (ie: we're a cache) require (supports.probe.contains(supports.arithmetic)) require (supports.probe.contains(supports.logical)) require (supports.probe.contains(supports.get)) require (supports.probe.contains(supports.putFull)) require (supports.probe.contains(supports.putPartial)) require (supports.probe.contains(supports.hint)) visibility.combinations(2).foreach { case Seq(x,y) => require (!x.overlaps(y), s"$x and $y overlap.") } val maxTransfer = List( supports.probe.max, supports.arithmetic.max, supports.logical.max, supports.get.max, supports.putFull.max, supports.putPartial.max).max def infoString = { s"""Master Name = ${name} |visibility = ${visibility} |emits = ${emits.infoString} |sourceId = ${sourceId} | |""".stripMargin } def v1copy( name: String = name, sourceId: IdRange = sourceId, nodePath: Seq[BaseNode] = nodePath, requestFifo: Boolean = requestFifo, visibility: Seq[AddressSet] = visibility, supportsProbe: TransferSizes = supports.probe, supportsArithmetic: TransferSizes = supports.arithmetic, supportsLogical: TransferSizes = supports.logical, supportsGet: TransferSizes = supports.get, supportsPutFull: TransferSizes = supports.putFull, supportsPutPartial: TransferSizes = supports.putPartial, supportsHint: TransferSizes = supports.hint) = { new TLMasterParameters( nodePath = nodePath, resources = this.resources, name = name, visibility = visibility, unusedRegionTypes = this.unusedRegionTypes, executesOnly = this.executesOnly, requestFifo = requestFifo, supports = TLSlaveToMasterTransferSizes( probe = supportsProbe, arithmetic = supportsArithmetic, logical = supportsLogical, get = supportsGet, putFull = supportsPutFull, putPartial = supportsPutPartial, hint = supportsHint), emits = this.emits, neverReleasesData = this.neverReleasesData, sourceId = sourceId) } def v2copy( nodePath: Seq[BaseNode] = nodePath, resources: Seq[Resource] = resources, name: String = name, visibility: Seq[AddressSet] = visibility, unusedRegionTypes: Set[RegionType.T] = unusedRegionTypes, executesOnly: Boolean = executesOnly, requestFifo: Boolean = requestFifo, supports: TLSlaveToMasterTransferSizes = supports, emits: TLMasterToSlaveTransferSizes = emits, neverReleasesData: Boolean = neverReleasesData, sourceId: IdRange = sourceId) = { new TLMasterParameters( nodePath = nodePath, resources = resources, name = name, visibility = visibility, unusedRegionTypes = unusedRegionTypes, executesOnly = executesOnly, requestFifo = requestFifo, supports = supports, emits = emits, neverReleasesData = neverReleasesData, sourceId = sourceId) } @deprecated("Use v1copy instead of copy","") def copy( name: String = name, sourceId: IdRange = sourceId, nodePath: Seq[BaseNode] = nodePath, requestFifo: Boolean = requestFifo, visibility: Seq[AddressSet] = visibility, supportsProbe: TransferSizes = supports.probe, supportsArithmetic: TransferSizes = supports.arithmetic, supportsLogical: TransferSizes = supports.logical, supportsGet: TransferSizes = supports.get, supportsPutFull: TransferSizes = supports.putFull, supportsPutPartial: TransferSizes = supports.putPartial, supportsHint: TransferSizes = supports.hint) = { v1copy( name = name, sourceId = sourceId, nodePath = nodePath, requestFifo = requestFifo, visibility = visibility, supportsProbe = supportsProbe, supportsArithmetic = supportsArithmetic, supportsLogical = supportsLogical, supportsGet = supportsGet, supportsPutFull = supportsPutFull, supportsPutPartial = supportsPutPartial, supportsHint = supportsHint) } } object TLMasterParameters { def v1( name: String, sourceId: IdRange = IdRange(0,1), nodePath: Seq[BaseNode] = Seq(), requestFifo: Boolean = false, visibility: Seq[AddressSet] = Seq(AddressSet(0, ~0)), supportsProbe: TransferSizes = TransferSizes.none, supportsArithmetic: TransferSizes = TransferSizes.none, supportsLogical: TransferSizes = TransferSizes.none, supportsGet: TransferSizes = TransferSizes.none, supportsPutFull: TransferSizes = TransferSizes.none, supportsPutPartial: TransferSizes = TransferSizes.none, supportsHint: TransferSizes = TransferSizes.none) = { new TLMasterParameters( nodePath = nodePath, resources = Nil, name = name, visibility = visibility, unusedRegionTypes = Set(), executesOnly = false, requestFifo = requestFifo, supports = TLSlaveToMasterTransferSizes( probe = supportsProbe, arithmetic = supportsArithmetic, logical = supportsLogical, get = supportsGet, putFull = supportsPutFull, putPartial = supportsPutPartial, hint = supportsHint), emits = TLMasterToSlaveTransferSizes.unknownEmits, neverReleasesData = false, sourceId = sourceId) } def v2( nodePath: Seq[BaseNode] = Seq(), resources: Seq[Resource] = Nil, name: String, visibility: Seq[AddressSet] = Seq(AddressSet(0, ~0)), unusedRegionTypes: Set[RegionType.T] = Set(), executesOnly: Boolean = false, requestFifo: Boolean = false, supports: TLSlaveToMasterTransferSizes = TLSlaveToMasterTransferSizes.unknownSupports, emits: TLMasterToSlaveTransferSizes = TLMasterToSlaveTransferSizes.unknownEmits, neverReleasesData: Boolean = false, sourceId: IdRange = IdRange(0,1)) = { new TLMasterParameters( nodePath = nodePath, resources = resources, name = name, visibility = visibility, unusedRegionTypes = unusedRegionTypes, executesOnly = executesOnly, requestFifo = requestFifo, supports = supports, emits = emits, neverReleasesData = neverReleasesData, sourceId = sourceId) } } object TLClientParameters { @deprecated("Use TLMasterParameters.v1 instead of TLClientParameters","") def apply( name: String, sourceId: IdRange = IdRange(0,1), nodePath: Seq[BaseNode] = Seq(), requestFifo: Boolean = false, visibility: Seq[AddressSet] = Seq(AddressSet.everything), supportsProbe: TransferSizes = TransferSizes.none, supportsArithmetic: TransferSizes = TransferSizes.none, supportsLogical: TransferSizes = TransferSizes.none, supportsGet: TransferSizes = TransferSizes.none, supportsPutFull: TransferSizes = TransferSizes.none, supportsPutPartial: TransferSizes = TransferSizes.none, supportsHint: TransferSizes = TransferSizes.none) = { TLMasterParameters.v1( name = name, sourceId = sourceId, nodePath = nodePath, requestFifo = requestFifo, visibility = visibility, supportsProbe = supportsProbe, supportsArithmetic = supportsArithmetic, supportsLogical = supportsLogical, supportsGet = supportsGet, supportsPutFull = supportsPutFull, supportsPutPartial = supportsPutPartial, supportsHint = supportsHint) } } class TLMasterPortParameters private( val masters: Seq[TLMasterParameters], val channelBytes: TLChannelBeatBytes, val minLatency: Int, val echoFields: Seq[BundleFieldBase], val requestFields: Seq[BundleFieldBase], val responseKeys: Seq[BundleKeyBase]) extends SimpleProduct { override def canEqual(that: Any): Boolean = that.isInstanceOf[TLMasterPortParameters] override def productPrefix = "TLMasterPortParameters" def productArity: Int = 6 def productElement(n: Int): Any = n match { case 0 => masters case 1 => channelBytes case 2 => minLatency case 3 => echoFields case 4 => requestFields case 5 => responseKeys case _ => throw new IndexOutOfBoundsException(n.toString) } require (!masters.isEmpty) require (minLatency >= 0) def clients = masters // Require disjoint ranges for Ids IdRange.overlaps(masters.map(_.sourceId)).foreach { case (x, y) => require (!x.overlaps(y), s"TLClientParameters.sourceId ${x} overlaps ${y}") } // Bounds on required sizes def endSourceId = masters.map(_.sourceId.end).max def maxTransfer = masters.map(_.maxTransfer).max // The unused sources < endSourceId def unusedSources: Seq[Int] = { val usedSources = masters.map(_.sourceId).sortBy(_.start) ((Seq(0) ++ usedSources.map(_.end)) zip usedSources.map(_.start)) flatMap { case (end, start) => end until start } } // Diplomatically determined operation sizes emitted by all inward Masters // as opposed to emits* which generate circuitry to check which specific addresses val allEmitClaims = masters.map(_.emits).reduce( _ intersect _) // Diplomatically determined operation sizes Emitted by at least one inward Masters // as opposed to emits* which generate circuitry to check which specific addresses val anyEmitClaims = masters.map(_.emits).reduce(_ mincover _) // Diplomatically determined operation sizes supported by all inward Masters // as opposed to supports* which generate circuitry to check which specific addresses val allSupportProbe = masters.map(_.supports.probe) .reduce(_ intersect _) val allSupportArithmetic = masters.map(_.supports.arithmetic).reduce(_ intersect _) val allSupportLogical = masters.map(_.supports.logical) .reduce(_ intersect _) val allSupportGet = masters.map(_.supports.get) .reduce(_ intersect _) val allSupportPutFull = masters.map(_.supports.putFull) .reduce(_ intersect _) val allSupportPutPartial = masters.map(_.supports.putPartial).reduce(_ intersect _) val allSupportHint = masters.map(_.supports.hint) .reduce(_ intersect _) // Diplomatically determined operation sizes supported by at least one master // as opposed to supports* which generate circuitry to check which specific addresses val anySupportProbe = masters.map(!_.supports.probe.none) .reduce(_ || _) val anySupportArithmetic = masters.map(!_.supports.arithmetic.none).reduce(_ || _) val anySupportLogical = masters.map(!_.supports.logical.none) .reduce(_ || _) val anySupportGet = masters.map(!_.supports.get.none) .reduce(_ || _) val anySupportPutFull = masters.map(!_.supports.putFull.none) .reduce(_ || _) val anySupportPutPartial = masters.map(!_.supports.putPartial.none).reduce(_ || _) val anySupportHint = masters.map(!_.supports.hint.none) .reduce(_ || _) // These return Option[TLMasterParameters] for your convenience def find(id: Int) = masters.find(_.sourceId.contains(id)) // Synthesizable lookup methods def find(id: UInt) = VecInit(masters.map(_.sourceId.contains(id))) def contains(id: UInt) = find(id).reduce(_ || _) def requestFifo(id: UInt) = Mux1H(find(id), masters.map(c => c.requestFifo.B)) // Available during RTL runtime, checks to see if (id, size) is supported by the master's (client's) diplomatic parameters private def sourceIdHelper(member: TLMasterParameters => TransferSizes)(id: UInt, lgSize: UInt) = { val allSame = masters.map(member(_) == member(masters(0))).reduce(_ && _) // this if statement is a coarse generalization of the groupBy in the sourceIdHelper2 version; // the case where there is only one group. if (allSame) member(masters(0)).containsLg(lgSize) else { // Find the master associated with ID and returns whether that particular master is able to receive transaction of lgSize Mux1H(find(id), masters.map(member(_).containsLg(lgSize))) } } // Check for support of a given operation at a specific id val supportsProbe = sourceIdHelper(_.supports.probe) _ val supportsArithmetic = sourceIdHelper(_.supports.arithmetic) _ val supportsLogical = sourceIdHelper(_.supports.logical) _ val supportsGet = sourceIdHelper(_.supports.get) _ val supportsPutFull = sourceIdHelper(_.supports.putFull) _ val supportsPutPartial = sourceIdHelper(_.supports.putPartial) _ val supportsHint = sourceIdHelper(_.supports.hint) _ // TODO: Merge sourceIdHelper2 with sourceIdHelper private def sourceIdHelper2( member: TLMasterParameters => TransferSizes, sourceId: UInt, lgSize: UInt): Bool = { // Because sourceIds are uniquely owned by each master, we use them to group the // cases that have to be checked. val emitCases = groupByIntoSeq(masters)(m => member(m)).map { case (k, vs) => k -> vs.map(_.sourceId) } emitCases.map { case (s, a) => (s.containsLg(lgSize)) && a.map(_.contains(sourceId)).reduce(_||_) }.foldLeft(false.B)(_||_) } // Check for emit of a given operation at a specific id def emitsAcquireT (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.acquireT, sourceId, lgSize) def emitsAcquireB (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.acquireB, sourceId, lgSize) def emitsArithmetic(sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.arithmetic, sourceId, lgSize) def emitsLogical (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.logical, sourceId, lgSize) def emitsGet (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.get, sourceId, lgSize) def emitsPutFull (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.putFull, sourceId, lgSize) def emitsPutPartial(sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.putPartial, sourceId, lgSize) def emitsHint (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.hint, sourceId, lgSize) def infoString = masters.map(_.infoString).mkString def v1copy( clients: Seq[TLMasterParameters] = masters, minLatency: Int = minLatency, echoFields: Seq[BundleFieldBase] = echoFields, requestFields: Seq[BundleFieldBase] = requestFields, responseKeys: Seq[BundleKeyBase] = responseKeys) = { new TLMasterPortParameters( masters = clients, channelBytes = channelBytes, minLatency = minLatency, echoFields = echoFields, requestFields = requestFields, responseKeys = responseKeys) } def v2copy( masters: Seq[TLMasterParameters] = masters, channelBytes: TLChannelBeatBytes = channelBytes, minLatency: Int = minLatency, echoFields: Seq[BundleFieldBase] = echoFields, requestFields: Seq[BundleFieldBase] = requestFields, responseKeys: Seq[BundleKeyBase] = responseKeys) = { new TLMasterPortParameters( masters = masters, channelBytes = channelBytes, minLatency = minLatency, echoFields = echoFields, requestFields = requestFields, responseKeys = responseKeys) } @deprecated("Use v1copy instead of copy","") def copy( clients: Seq[TLMasterParameters] = masters, minLatency: Int = minLatency, echoFields: Seq[BundleFieldBase] = echoFields, requestFields: Seq[BundleFieldBase] = requestFields, responseKeys: Seq[BundleKeyBase] = responseKeys) = { v1copy( clients, minLatency, echoFields, requestFields, responseKeys) } } object TLClientPortParameters { @deprecated("Use TLMasterPortParameters.v1 instead of TLClientPortParameters","") def apply( clients: Seq[TLMasterParameters], minLatency: Int = 0, echoFields: Seq[BundleFieldBase] = Nil, requestFields: Seq[BundleFieldBase] = Nil, responseKeys: Seq[BundleKeyBase] = Nil) = { TLMasterPortParameters.v1( clients, minLatency, echoFields, requestFields, responseKeys) } } object TLMasterPortParameters { def v1( clients: Seq[TLMasterParameters], minLatency: Int = 0, echoFields: Seq[BundleFieldBase] = Nil, requestFields: Seq[BundleFieldBase] = Nil, responseKeys: Seq[BundleKeyBase] = Nil) = { new TLMasterPortParameters( masters = clients, channelBytes = TLChannelBeatBytes(), minLatency = minLatency, echoFields = echoFields, requestFields = requestFields, responseKeys = responseKeys) } def v2( masters: Seq[TLMasterParameters], channelBytes: TLChannelBeatBytes = TLChannelBeatBytes(), minLatency: Int = 0, echoFields: Seq[BundleFieldBase] = Nil, requestFields: Seq[BundleFieldBase] = Nil, responseKeys: Seq[BundleKeyBase] = Nil) = { new TLMasterPortParameters( masters = masters, channelBytes = channelBytes, minLatency = minLatency, echoFields = echoFields, requestFields = requestFields, responseKeys = responseKeys) } } case class TLBundleParameters( addressBits: Int, dataBits: Int, sourceBits: Int, sinkBits: Int, sizeBits: Int, echoFields: Seq[BundleFieldBase], requestFields: Seq[BundleFieldBase], responseFields: Seq[BundleFieldBase], hasBCE: Boolean) { // Chisel has issues with 0-width wires require (addressBits >= 1) require (dataBits >= 8) require (sourceBits >= 1) require (sinkBits >= 1) require (sizeBits >= 1) require (isPow2(dataBits)) echoFields.foreach { f => require (f.key.isControl, s"${f} is not a legal echo field") } val addrLoBits = log2Up(dataBits/8) // Used to uniquify bus IP names def shortName = s"a${addressBits}d${dataBits}s${sourceBits}k${sinkBits}z${sizeBits}" + (if (hasBCE) "c" else "u") def union(x: TLBundleParameters) = TLBundleParameters( max(addressBits, x.addressBits), max(dataBits, x.dataBits), max(sourceBits, x.sourceBits), max(sinkBits, x.sinkBits), max(sizeBits, x.sizeBits), echoFields = BundleField.union(echoFields ++ x.echoFields), requestFields = BundleField.union(requestFields ++ x.requestFields), responseFields = BundleField.union(responseFields ++ x.responseFields), hasBCE || x.hasBCE) } object TLBundleParameters { val emptyBundleParams = TLBundleParameters( addressBits = 1, dataBits = 8, sourceBits = 1, sinkBits = 1, sizeBits = 1, echoFields = Nil, requestFields = Nil, responseFields = Nil, hasBCE = false) def union(x: Seq[TLBundleParameters]) = x.foldLeft(emptyBundleParams)((x,y) => x.union(y)) def apply(master: TLMasterPortParameters, slave: TLSlavePortParameters) = new TLBundleParameters( addressBits = log2Up(slave.maxAddress + 1), dataBits = slave.beatBytes * 8, sourceBits = log2Up(master.endSourceId), sinkBits = log2Up(slave.endSinkId), sizeBits = log2Up(log2Ceil(max(master.maxTransfer, slave.maxTransfer))+1), echoFields = master.echoFields, requestFields = BundleField.accept(master.requestFields, slave.requestKeys), responseFields = BundleField.accept(slave.responseFields, master.responseKeys), hasBCE = master.anySupportProbe && slave.anySupportAcquireB) } case class TLEdgeParameters( master: TLMasterPortParameters, slave: TLSlavePortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge { // legacy names: def manager = slave def client = master val maxTransfer = max(master.maxTransfer, slave.maxTransfer) val maxLgSize = log2Ceil(maxTransfer) // Sanity check the link... require (maxTransfer >= slave.beatBytes, s"Link's max transfer (${maxTransfer}) < ${slave.slaves.map(_.name)}'s beatBytes (${slave.beatBytes})") def diplomaticClaimsMasterToSlave = master.anyEmitClaims.intersect(slave.anySupportClaims) val bundle = TLBundleParameters(master, slave) def formatEdge = master.infoString + "\n" + slave.infoString } case class TLCreditedDelay( a: CreditedDelay, b: CreditedDelay, c: CreditedDelay, d: CreditedDelay, e: CreditedDelay) { def + (that: TLCreditedDelay): TLCreditedDelay = TLCreditedDelay( a = a + that.a, b = b + that.b, c = c + that.c, d = d + that.d, e = e + that.e) override def toString = s"(${a}, ${b}, ${c}, ${d}, ${e})" } object TLCreditedDelay { def apply(delay: CreditedDelay): TLCreditedDelay = apply(delay, delay.flip, delay, delay.flip, delay) } case class TLCreditedManagerPortParameters(delay: TLCreditedDelay, base: TLSlavePortParameters) {def infoString = base.infoString} case class TLCreditedClientPortParameters(delay: TLCreditedDelay, base: TLMasterPortParameters) {def infoString = base.infoString} case class TLCreditedEdgeParameters(client: TLCreditedClientPortParameters, manager: TLCreditedManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge { val delay = client.delay + manager.delay val bundle = TLBundleParameters(client.base, manager.base) def formatEdge = client.infoString + "\n" + manager.infoString } case class TLAsyncManagerPortParameters(async: AsyncQueueParams, base: TLSlavePortParameters) {def infoString = base.infoString} case class TLAsyncClientPortParameters(base: TLMasterPortParameters) {def infoString = base.infoString} case class TLAsyncBundleParameters(async: AsyncQueueParams, base: TLBundleParameters) case class TLAsyncEdgeParameters(client: TLAsyncClientPortParameters, manager: TLAsyncManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge { val bundle = TLAsyncBundleParameters(manager.async, TLBundleParameters(client.base, manager.base)) def formatEdge = client.infoString + "\n" + manager.infoString } case class TLRationalManagerPortParameters(direction: RationalDirection, base: TLSlavePortParameters) {def infoString = base.infoString} case class TLRationalClientPortParameters(base: TLMasterPortParameters) {def infoString = base.infoString} case class TLRationalEdgeParameters(client: TLRationalClientPortParameters, manager: TLRationalManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge { val bundle = TLBundleParameters(client.base, manager.base) def formatEdge = client.infoString + "\n" + manager.infoString } // To be unified, devices must agree on all of these terms case class ManagerUnificationKey( resources: Seq[Resource], regionType: RegionType.T, executable: Boolean, supportsAcquireT: TransferSizes, supportsAcquireB: TransferSizes, supportsArithmetic: TransferSizes, supportsLogical: TransferSizes, supportsGet: TransferSizes, supportsPutFull: TransferSizes, supportsPutPartial: TransferSizes, supportsHint: TransferSizes) object ManagerUnificationKey { def apply(x: TLSlaveParameters): ManagerUnificationKey = ManagerUnificationKey( resources = x.resources, regionType = x.regionType, executable = x.executable, supportsAcquireT = x.supportsAcquireT, supportsAcquireB = x.supportsAcquireB, supportsArithmetic = x.supportsArithmetic, supportsLogical = x.supportsLogical, supportsGet = x.supportsGet, supportsPutFull = x.supportsPutFull, supportsPutPartial = x.supportsPutPartial, supportsHint = x.supportsHint) } object ManagerUnification { def apply(slaves: Seq[TLSlaveParameters]): List[TLSlaveParameters] = { slaves.groupBy(ManagerUnificationKey.apply).values.map { seq => val agree = seq.forall(_.fifoId == seq.head.fifoId) seq(0).v1copy( address = AddressSet.unify(seq.flatMap(_.address)), fifoId = if (agree) seq(0).fifoId else None) }.toList } } case class TLBufferParams( a: BufferParams = BufferParams.none, b: BufferParams = BufferParams.none, c: BufferParams = BufferParams.none, d: BufferParams = BufferParams.none, e: BufferParams = BufferParams.none ) extends DirectedBuffers[TLBufferParams] { def copyIn(x: BufferParams) = this.copy(b = x, d = x) def copyOut(x: BufferParams) = this.copy(a = x, c = x, e = x) def copyInOut(x: BufferParams) = this.copyIn(x).copyOut(x) } /** Pretty printing of TL source id maps */ class TLSourceIdMap(tl: TLMasterPortParameters) extends IdMap[TLSourceIdMapEntry] { private val tlDigits = String.valueOf(tl.endSourceId-1).length() protected val fmt = s"\t[%${tlDigits}d, %${tlDigits}d) %s%s%s" private val sorted = tl.masters.sortBy(_.sourceId) val mapping: Seq[TLSourceIdMapEntry] = sorted.map { case c => TLSourceIdMapEntry(c.sourceId, c.name, c.supports.probe, c.requestFifo) } } case class TLSourceIdMapEntry(tlId: IdRange, name: String, isCache: Boolean, requestFifo: Boolean) extends IdMapEntry { val from = tlId val to = tlId val maxTransactionsInFlight = Some(tlId.size) } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) || !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.ProbeAckData || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode | small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U || beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }

module TLMonitor_8( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [3:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [31:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7] wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_a_bits_source = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_source = 1'h0; // @[Monitor.scala:36:7] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire c_set = 1'h0; // @[Monitor.scala:738:34] wire c_set_wo_ready = 1'h0; // @[Monitor.scala:739:34] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire _source_ok_T = 1'h1; // @[Parameters.scala:46:9] wire _source_ok_WIRE_0 = 1'h1; // @[Parameters.scala:1138:31] wire _source_ok_T_1 = 1'h1; // @[Parameters.scala:46:9] wire _source_ok_WIRE_1_0 = 1'h1; // @[Parameters.scala:1138:31] wire sink_ok = 1'h1; // @[Monitor.scala:309:31] wire _same_cycle_resp_T_2 = 1'h1; // @[Monitor.scala:684:113] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire _same_cycle_resp_T_8 = 1'h1; // @[Monitor.scala:795:113] wire [8:0] c_first_beats1_decode = 9'h0; // @[Edges.scala:220:59] wire [8:0] c_first_beats1 = 9'h0; // @[Edges.scala:221:14] wire [8:0] _c_first_count_T = 9'h0; // @[Edges.scala:234:27] wire [8:0] c_first_count = 9'h0; // @[Edges.scala:234:25] wire [8:0] _c_first_counter_T = 9'h0; // @[Edges.scala:236:21] wire [8:0] c_first_counter1 = 9'h1FF; // @[Edges.scala:230:28] wire [9:0] _c_first_counter1_T = 10'h3FF; // @[Edges.scala:230:28] wire [2:0] io_in_a_bits_param = 3'h0; // @[Monitor.scala:36:7] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [31:0] _c_first_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_first_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_wo_ready_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_wo_ready_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_4_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_5_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [3:0] _a_opcode_lookup_T = 4'h0; // @[Monitor.scala:637:69] wire [3:0] _a_size_lookup_T = 4'h0; // @[Monitor.scala:641:65] wire [3:0] _a_opcodes_set_T = 4'h0; // @[Monitor.scala:659:79] wire [3:0] _a_sizes_set_T = 4'h0; // @[Monitor.scala:660:77] wire [3:0] _d_opcodes_clr_T_4 = 4'h0; // @[Monitor.scala:680:101] wire [3:0] _d_sizes_clr_T_4 = 4'h0; // @[Monitor.scala:681:99] wire [3:0] _c_first_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] c_opcodes_set = 4'h0; // @[Monitor.scala:740:34] wire [3:0] _c_opcode_lookup_T = 4'h0; // @[Monitor.scala:749:69] wire [3:0] _c_size_lookup_T = 4'h0; // @[Monitor.scala:750:67] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] _c_set_wo_ready_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_wo_ready_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_sizes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_T = 4'h0; // @[Monitor.scala:767:79] wire [3:0] _c_sizes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_sizes_set_T = 4'h0; // @[Monitor.scala:768:77] wire [3:0] _c_probe_ack_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _d_opcodes_clr_T_10 = 4'h0; // @[Monitor.scala:790:101] wire [3:0] _d_sizes_clr_T_10 = 4'h0; // @[Monitor.scala:791:99] wire [3:0] _same_cycle_resp_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_4_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_5_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [30:0] _d_sizes_clr_T_5 = 31'hFF; // @[Monitor.scala:681:74] wire [30:0] _d_sizes_clr_T_11 = 31'hFF; // @[Monitor.scala:791:74] wire [15:0] _a_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _c_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hFF; // @[Monitor.scala:724:57] wire [16:0] _a_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _c_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hFF; // @[Monitor.scala:724:57] wire [15:0] _a_size_lookup_T_3 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _c_size_lookup_T_3 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h100; // @[Monitor.scala:724:51] wire [30:0] _d_opcodes_clr_T_5 = 31'hF; // @[Monitor.scala:680:76] wire [30:0] _d_opcodes_clr_T_11 = 31'hF; // @[Monitor.scala:790:76] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [1:0] _a_set_wo_ready_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _a_set_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _d_clr_wo_ready_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _d_clr_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _c_set_wo_ready_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _c_set_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _d_clr_wo_ready_T_1 = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _d_clr_T_1 = 2'h1; // @[OneHot.scala:58:35] wire [19:0] _c_sizes_set_T_1 = 20'h0; // @[Monitor.scala:768:52] wire [18:0] _c_opcodes_set_T_1 = 19'h0; // @[Monitor.scala:767:54] wire [4:0] _c_sizes_set_interm_T_1 = 5'h1; // @[Monitor.scala:766:59] wire [4:0] c_sizes_set_interm = 5'h0; // @[Monitor.scala:755:40] wire [4:0] _c_sizes_set_interm_T = 5'h0; // @[Monitor.scala:766:51] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [7:0] c_sizes_set = 8'h0; // @[Monitor.scala:741:34] wire [11:0] _c_first_beats1_decode_T_2 = 12'h0; // @[package.scala:243:46] wire [11:0] _c_first_beats1_decode_T_1 = 12'hFFF; // @[package.scala:243:76] wire [26:0] _c_first_beats1_decode_T = 27'hFFF; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [3:0] _a_size_lookup_T_2 = 4'h8; // @[Monitor.scala:641:117] wire [3:0] _d_sizes_clr_T = 4'h8; // @[Monitor.scala:681:48] wire [3:0] _c_size_lookup_T_2 = 4'h8; // @[Monitor.scala:750:119] wire [3:0] _d_sizes_clr_T_6 = 4'h8; // @[Monitor.scala:791:48] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire [26:0] _GEN = 27'hFFF << io_in_a_bits_size_0; // @[package.scala:243:71] wire [26:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [11:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [31:0] _is_aligned_T = {20'h0, io_in_a_bits_address_0[11:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 32'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 4'h2; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire _T_1212 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_1212; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_1212; // @[Decoupled.scala:51:35] wire [11:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [8:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [8:0] a_first_counter; // @[Edges.scala:229:27] wire [9:0] _a_first_counter1_T = {1'h0, a_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] a_first_counter1 = _a_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [8:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [3:0] size; // @[Monitor.scala:389:22] reg [31:0] address; // @[Monitor.scala:391:22] wire _T_1285 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_1285; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_1285; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_1285; // @[Decoupled.scala:51:35] wire [26:0] _GEN_0 = 27'hFFF << io_in_d_bits_size_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [11:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [8:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T = {1'h0, d_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1 = _d_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [3:0] size_1; // @[Monitor.scala:540:22] reg [2:0] sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] reg [1:0] inflight; // @[Monitor.scala:614:27] reg [3:0] inflight_opcodes; // @[Monitor.scala:616:35] wire [3:0] _a_opcode_lookup_T_1 = inflight_opcodes; // @[Monitor.scala:616:35, :637:44] reg [7:0] inflight_sizes; // @[Monitor.scala:618:33] wire [7:0] _a_size_lookup_T_1 = inflight_sizes; // @[Monitor.scala:618:33, :641:40] wire [11:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [8:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [8:0] a_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] a_first_counter1_1 = _a_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [11:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_1 = _d_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire a_set; // @[Monitor.scala:626:34] wire a_set_wo_ready; // @[Monitor.scala:627:34] wire [3:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [7:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [15:0] _a_opcode_lookup_T_6 = {12'h0, _a_opcode_lookup_T_1}; // @[Monitor.scala:637:{44,97}] wire [15:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [7:0] a_size_lookup; // @[Monitor.scala:639:33] wire [15:0] _a_size_lookup_T_6 = {8'h0, _a_size_lookup_T_1}; // @[Monitor.scala:641:{40,91}] wire [15:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[15:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[7:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [4:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _T_1135 = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26] assign a_set_wo_ready = _T_1135; // @[Monitor.scala:627:34, :651:26] wire _same_cycle_resp_T; // @[Monitor.scala:684:44] assign _same_cycle_resp_T = _T_1135; // @[Monitor.scala:651:26, :684:44] assign a_set = _T_1212 & a_first_1; // @[Decoupled.scala:51:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = a_set ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:626:34, :646:40, :655:70, :657:{28,61}] wire [4:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [4:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = a_set ? _a_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:626:34, :648:38, :655:70, :658:{28,59}] wire [18:0] _a_opcodes_set_T_1 = {15'h0, a_opcodes_set_interm}; // @[Monitor.scala:646:40, :659:54] assign a_opcodes_set = a_set ? _a_opcodes_set_T_1[3:0] : 4'h0; // @[Monitor.scala:626:34, :630:33, :655:70, :659:{28,54}] wire [19:0] _a_sizes_set_T_1 = {15'h0, a_sizes_set_interm}; // @[Monitor.scala:648:38, :660:52] assign a_sizes_set = a_set ? _a_sizes_set_T_1[7:0] : 8'h0; // @[Monitor.scala:626:34, :632:31, :655:70, :660:{28,52}] wire d_clr; // @[Monitor.scala:664:34] wire d_clr_wo_ready; // @[Monitor.scala:665:34] wire [3:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [7:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_1 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_1; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_1; // @[Monitor.scala:673:46, :783:46] wire _T_1184 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] assign d_clr_wo_ready = _T_1184 & ~d_release_ack; // @[Monitor.scala:665:34, :673:46, :674:{26,71,74}] assign d_clr = _T_1285 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_opcodes_clr = {4{d_clr}}; // @[Monitor.scala:664:34, :668:33, :678:89, :680:21] assign d_sizes_clr = {8{d_clr}}; // @[Monitor.scala:664:34, :670:31, :678:89, :681:21] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire same_cycle_resp = _same_cycle_resp_T_1; // @[Monitor.scala:684:{55,88}] wire [1:0] _inflight_T = {inflight[1], inflight[0] | a_set}; // @[Monitor.scala:614:27, :626:34, :705:27] wire _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [1:0] _inflight_T_2 = {1'h0, _inflight_T[0] & _inflight_T_1}; // @[Monitor.scala:705:{27,36,38}] wire [3:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [3:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [3:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [7:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [7:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [7:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [1:0] inflight_1; // @[Monitor.scala:726:35] wire [1:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [3:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [3:0] _c_opcode_lookup_T_1 = inflight_opcodes_1; // @[Monitor.scala:727:35, :749:44] wire [3:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [7:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [7:0] _c_size_lookup_T_1 = inflight_sizes_1; // @[Monitor.scala:728:35, :750:42] wire [7:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire [11:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_2; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_2 = _d_first_counter1_T_2[8:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [7:0] c_size_lookup; // @[Monitor.scala:748:35] wire [15:0] _c_opcode_lookup_T_6 = {12'h0, _c_opcode_lookup_T_1}; // @[Monitor.scala:749:{44,97}] wire [15:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [15:0] _c_size_lookup_T_6 = {8'h0, _c_size_lookup_T_1}; // @[Monitor.scala:750:{42,93}] wire [15:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[15:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[7:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire d_clr_1; // @[Monitor.scala:774:34] wire d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [3:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [7:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_1256 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_1256 & d_release_ack_1; // @[Monitor.scala:775:34, :783:46, :784:{26,71}] assign d_clr_1 = _T_1285 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_opcodes_clr_1 = {4{d_clr_1}}; // @[Monitor.scala:774:34, :776:34, :788:88, :790:21] assign d_sizes_clr_1 = {8{d_clr_1}}; // @[Monitor.scala:774:34, :777:34, :788:88, :791:21] wire _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [1:0] _inflight_T_5 = {1'h0, _inflight_T_3[0] & _inflight_T_4}; // @[Monitor.scala:814:{35,44,46}] wire [3:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [3:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [7:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [7:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]

Generate the Verilog code corresponding to the following Chisel files. File FPU.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.tile import chisel3._ import chisel3.util._ import chisel3.{DontCare, WireInit, withClock, withReset} import chisel3.experimental.SourceInfo import chisel3.experimental.dataview._ import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.rocket._ import freechips.rocketchip.rocket.Instructions._ import freechips.rocketchip.util._ import freechips.rocketchip.util.property case class FPUParams( minFLen: Int = 32, fLen: Int = 64, divSqrt: Boolean = true, sfmaLatency: Int = 3, dfmaLatency: Int = 4, fpmuLatency: Int = 2, ifpuLatency: Int = 2 ) object FPConstants { val RM_SZ = 3 val FLAGS_SZ = 5 } trait HasFPUCtrlSigs { val ldst = Bool() val wen = Bool() val ren1 = Bool() val ren2 = Bool() val ren3 = Bool() val swap12 = Bool() val swap23 = Bool() val typeTagIn = UInt(2.W) val typeTagOut = UInt(2.W) val fromint = Bool() val toint = Bool() val fastpipe = Bool() val fma = Bool() val div = Bool() val sqrt = Bool() val wflags = Bool() val vec = Bool() } class FPUCtrlSigs extends Bundle with HasFPUCtrlSigs class FPUDecoder(implicit p: Parameters) extends FPUModule()(p) { val io = IO(new Bundle { val inst = Input(Bits(32.W)) val sigs = Output(new FPUCtrlSigs()) }) private val X2 = BitPat.dontCare(2) val default = List(X,X,X,X,X,X,X,X2,X2,X,X,X,X,X,X,X,N) val h: Array[(BitPat, List[BitPat])] = Array(FLH -> List(Y,Y,N,N,N,X,X,X2,X2,N,N,N,N,N,N,N,N), FSH -> List(Y,N,N,Y,N,Y,X, I, H,N,Y,N,N,N,N,N,N), FMV_H_X -> List(N,Y,N,N,N,X,X, H, I,Y,N,N,N,N,N,N,N), FCVT_H_W -> List(N,Y,N,N,N,X,X, H, H,Y,N,N,N,N,N,Y,N), FCVT_H_WU-> List(N,Y,N,N,N,X,X, H, H,Y,N,N,N,N,N,Y,N), FCVT_H_L -> List(N,Y,N,N,N,X,X, H, H,Y,N,N,N,N,N,Y,N), FCVT_H_LU-> List(N,Y,N,N,N,X,X, H, H,Y,N,N,N,N,N,Y,N), FMV_X_H -> List(N,N,Y,N,N,N,X, I, H,N,Y,N,N,N,N,N,N), FCLASS_H -> List(N,N,Y,N,N,N,X, H, H,N,Y,N,N,N,N,N,N), FCVT_W_H -> List(N,N,Y,N,N,N,X, H,X2,N,Y,N,N,N,N,Y,N), FCVT_WU_H-> List(N,N,Y,N,N,N,X, H,X2,N,Y,N,N,N,N,Y,N), FCVT_L_H -> List(N,N,Y,N,N,N,X, H,X2,N,Y,N,N,N,N,Y,N), FCVT_LU_H-> List(N,N,Y,N,N,N,X, H,X2,N,Y,N,N,N,N,Y,N), FCVT_S_H -> List(N,Y,Y,N,N,N,X, H, S,N,N,Y,N,N,N,Y,N), FCVT_H_S -> List(N,Y,Y,N,N,N,X, S, H,N,N,Y,N,N,N,Y,N), FEQ_H -> List(N,N,Y,Y,N,N,N, H, H,N,Y,N,N,N,N,Y,N), FLT_H -> List(N,N,Y,Y,N,N,N, H, H,N,Y,N,N,N,N,Y,N), FLE_H -> List(N,N,Y,Y,N,N,N, H, H,N,Y,N,N,N,N,Y,N), FSGNJ_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,Y,N,N,N,N,N), FSGNJN_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,Y,N,N,N,N,N), FSGNJX_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,Y,N,N,N,N,N), FMIN_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,Y,N,N,N,Y,N), FMAX_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,Y,N,N,N,Y,N), FADD_H -> List(N,Y,Y,Y,N,N,Y, H, H,N,N,N,Y,N,N,Y,N), FSUB_H -> List(N,Y,Y,Y,N,N,Y, H, H,N,N,N,Y,N,N,Y,N), FMUL_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,N,Y,N,N,Y,N), FMADD_H -> List(N,Y,Y,Y,Y,N,N, H, H,N,N,N,Y,N,N,Y,N), FMSUB_H -> List(N,Y,Y,Y,Y,N,N, H, H,N,N,N,Y,N,N,Y,N), FNMADD_H -> List(N,Y,Y,Y,Y,N,N, H, H,N,N,N,Y,N,N,Y,N), FNMSUB_H -> List(N,Y,Y,Y,Y,N,N, H, H,N,N,N,Y,N,N,Y,N), FDIV_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,N,N,Y,N,Y,N), FSQRT_H -> List(N,Y,Y,N,N,N,X, H, H,N,N,N,N,N,Y,Y,N)) val f: Array[(BitPat, List[BitPat])] = Array(FLW -> List(Y,Y,N,N,N,X,X,X2,X2,N,N,N,N,N,N,N,N), FSW -> List(Y,N,N,Y,N,Y,X, I, S,N,Y,N,N,N,N,N,N), FMV_W_X -> List(N,Y,N,N,N,X,X, S, I,Y,N,N,N,N,N,N,N), FCVT_S_W -> List(N,Y,N,N,N,X,X, S, S,Y,N,N,N,N,N,Y,N), FCVT_S_WU-> List(N,Y,N,N,N,X,X, S, S,Y,N,N,N,N,N,Y,N), FCVT_S_L -> List(N,Y,N,N,N,X,X, S, S,Y,N,N,N,N,N,Y,N), FCVT_S_LU-> List(N,Y,N,N,N,X,X, S, S,Y,N,N,N,N,N,Y,N), FMV_X_W -> List(N,N,Y,N,N,N,X, I, S,N,Y,N,N,N,N,N,N), FCLASS_S -> List(N,N,Y,N,N,N,X, S, S,N,Y,N,N,N,N,N,N), FCVT_W_S -> List(N,N,Y,N,N,N,X, S,X2,N,Y,N,N,N,N,Y,N), FCVT_WU_S-> List(N,N,Y,N,N,N,X, S,X2,N,Y,N,N,N,N,Y,N), FCVT_L_S -> List(N,N,Y,N,N,N,X, S,X2,N,Y,N,N,N,N,Y,N), FCVT_LU_S-> List(N,N,Y,N,N,N,X, S,X2,N,Y,N,N,N,N,Y,N), FEQ_S -> List(N,N,Y,Y,N,N,N, S, S,N,Y,N,N,N,N,Y,N), FLT_S -> List(N,N,Y,Y,N,N,N, S, S,N,Y,N,N,N,N,Y,N), FLE_S -> List(N,N,Y,Y,N,N,N, S, S,N,Y,N,N,N,N,Y,N), FSGNJ_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,Y,N,N,N,N,N), FSGNJN_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,Y,N,N,N,N,N), FSGNJX_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,Y,N,N,N,N,N), FMIN_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,Y,N,N,N,Y,N), FMAX_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,Y,N,N,N,Y,N), FADD_S -> List(N,Y,Y,Y,N,N,Y, S, S,N,N,N,Y,N,N,Y,N), FSUB_S -> List(N,Y,Y,Y,N,N,Y, S, S,N,N,N,Y,N,N,Y,N), FMUL_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,N,Y,N,N,Y,N), FMADD_S -> List(N,Y,Y,Y,Y,N,N, S, S,N,N,N,Y,N,N,Y,N), FMSUB_S -> List(N,Y,Y,Y,Y,N,N, S, S,N,N,N,Y,N,N,Y,N), FNMADD_S -> List(N,Y,Y,Y,Y,N,N, S, S,N,N,N,Y,N,N,Y,N), FNMSUB_S -> List(N,Y,Y,Y,Y,N,N, S, S,N,N,N,Y,N,N,Y,N), FDIV_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,N,N,Y,N,Y,N), FSQRT_S -> List(N,Y,Y,N,N,N,X, S, S,N,N,N,N,N,Y,Y,N)) val d: Array[(BitPat, List[BitPat])] = Array(FLD -> List(Y,Y,N,N,N,X,X,X2,X2,N,N,N,N,N,N,N,N), FSD -> List(Y,N,N,Y,N,Y,X, I, D,N,Y,N,N,N,N,N,N), FMV_D_X -> List(N,Y,N,N,N,X,X, D, I,Y,N,N,N,N,N,N,N), FCVT_D_W -> List(N,Y,N,N,N,X,X, D, D,Y,N,N,N,N,N,Y,N), FCVT_D_WU-> List(N,Y,N,N,N,X,X, D, D,Y,N,N,N,N,N,Y,N), FCVT_D_L -> List(N,Y,N,N,N,X,X, D, D,Y,N,N,N,N,N,Y,N), FCVT_D_LU-> List(N,Y,N,N,N,X,X, D, D,Y,N,N,N,N,N,Y,N), FMV_X_D -> List(N,N,Y,N,N,N,X, I, D,N,Y,N,N,N,N,N,N), FCLASS_D -> List(N,N,Y,N,N,N,X, D, D,N,Y,N,N,N,N,N,N), FCVT_W_D -> List(N,N,Y,N,N,N,X, D,X2,N,Y,N,N,N,N,Y,N), FCVT_WU_D-> List(N,N,Y,N,N,N,X, D,X2,N,Y,N,N,N,N,Y,N), FCVT_L_D -> List(N,N,Y,N,N,N,X, D,X2,N,Y,N,N,N,N,Y,N), FCVT_LU_D-> List(N,N,Y,N,N,N,X, D,X2,N,Y,N,N,N,N,Y,N), FCVT_S_D -> List(N,Y,Y,N,N,N,X, D, S,N,N,Y,N,N,N,Y,N), FCVT_D_S -> List(N,Y,Y,N,N,N,X, S, D,N,N,Y,N,N,N,Y,N), FEQ_D -> List(N,N,Y,Y,N,N,N, D, D,N,Y,N,N,N,N,Y,N), FLT_D -> List(N,N,Y,Y,N,N,N, D, D,N,Y,N,N,N,N,Y,N), FLE_D -> List(N,N,Y,Y,N,N,N, D, D,N,Y,N,N,N,N,Y,N), FSGNJ_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,Y,N,N,N,N,N), FSGNJN_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,Y,N,N,N,N,N), FSGNJX_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,Y,N,N,N,N,N), FMIN_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,Y,N,N,N,Y,N), FMAX_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,Y,N,N,N,Y,N), FADD_D -> List(N,Y,Y,Y,N,N,Y, D, D,N,N,N,Y,N,N,Y,N), FSUB_D -> List(N,Y,Y,Y,N,N,Y, D, D,N,N,N,Y,N,N,Y,N), FMUL_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,N,Y,N,N,Y,N), FMADD_D -> List(N,Y,Y,Y,Y,N,N, D, D,N,N,N,Y,N,N,Y,N), FMSUB_D -> List(N,Y,Y,Y,Y,N,N, D, D,N,N,N,Y,N,N,Y,N), FNMADD_D -> List(N,Y,Y,Y,Y,N,N, D, D,N,N,N,Y,N,N,Y,N), FNMSUB_D -> List(N,Y,Y,Y,Y,N,N, D, D,N,N,N,Y,N,N,Y,N), FDIV_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,N,N,Y,N,Y,N), FSQRT_D -> List(N,Y,Y,N,N,N,X, D, D,N,N,N,N,N,Y,Y,N)) val fcvt_hd: Array[(BitPat, List[BitPat])] = Array(FCVT_H_D -> List(N,Y,Y,N,N,N,X, D, H,N,N,Y,N,N,N,Y,N), FCVT_D_H -> List(N,Y,Y,N,N,N,X, H, D,N,N,Y,N,N,N,Y,N)) val vfmv_f_s: Array[(BitPat, List[BitPat])] = Array(VFMV_F_S -> List(N,Y,N,N,N,N,X,X2,X2,N,N,N,N,N,N,N,Y)) val insns = ((minFLen, fLen) match { case (32, 32) => f case (16, 32) => h ++ f case (32, 64) => f ++ d case (16, 64) => h ++ f ++ d ++ fcvt_hd case other => throw new Exception(s"minFLen = ${minFLen} & fLen = ${fLen} is an unsupported configuration") }) ++ (if (usingVector) vfmv_f_s else Array[(BitPat, List[BitPat])]()) val decoder = DecodeLogic(io.inst, default, insns) val s = io.sigs val sigs = Seq(s.ldst, s.wen, s.ren1, s.ren2, s.ren3, s.swap12, s.swap23, s.typeTagIn, s.typeTagOut, s.fromint, s.toint, s.fastpipe, s.fma, s.div, s.sqrt, s.wflags, s.vec) sigs zip decoder map {case(s,d) => s := d} } class FPUCoreIO(implicit p: Parameters) extends CoreBundle()(p) { val hartid = Input(UInt(hartIdLen.W)) val time = Input(UInt(xLen.W)) val inst = Input(Bits(32.W)) val fromint_data = Input(Bits(xLen.W)) val fcsr_rm = Input(Bits(FPConstants.RM_SZ.W)) val fcsr_flags = Valid(Bits(FPConstants.FLAGS_SZ.W)) val v_sew = Input(UInt(3.W)) val store_data = Output(Bits(fLen.W)) val toint_data = Output(Bits(xLen.W)) val ll_resp_val = Input(Bool()) val ll_resp_type = Input(Bits(3.W)) val ll_resp_tag = Input(UInt(5.W)) val ll_resp_data = Input(Bits(fLen.W)) val valid = Input(Bool()) val fcsr_rdy = Output(Bool()) val nack_mem = Output(Bool()) val illegal_rm = Output(Bool()) val killx = Input(Bool()) val killm = Input(Bool()) val dec = Output(new FPUCtrlSigs()) val sboard_set = Output(Bool()) val sboard_clr = Output(Bool()) val sboard_clra = Output(UInt(5.W)) val keep_clock_enabled = Input(Bool()) } class FPUIO(implicit p: Parameters) extends FPUCoreIO ()(p) { val cp_req = Flipped(Decoupled(new FPInput())) //cp doesn't pay attn to kill sigs val cp_resp = Decoupled(new FPResult()) } class FPResult(implicit p: Parameters) extends CoreBundle()(p) { val data = Bits((fLen+1).W) val exc = Bits(FPConstants.FLAGS_SZ.W) } class IntToFPInput(implicit p: Parameters) extends CoreBundle()(p) with HasFPUCtrlSigs { val rm = Bits(FPConstants.RM_SZ.W) val typ = Bits(2.W) val in1 = Bits(xLen.W) } class FPInput(implicit p: Parameters) extends CoreBundle()(p) with HasFPUCtrlSigs { val rm = Bits(FPConstants.RM_SZ.W) val fmaCmd = Bits(2.W) val typ = Bits(2.W) val fmt = Bits(2.W) val in1 = Bits((fLen+1).W) val in2 = Bits((fLen+1).W) val in3 = Bits((fLen+1).W) } case class FType(exp: Int, sig: Int) { def ieeeWidth = exp + sig def recodedWidth = ieeeWidth + 1 def ieeeQNaN = ((BigInt(1) << (ieeeWidth - 1)) - (BigInt(1) << (sig - 2))).U(ieeeWidth.W) def qNaN = ((BigInt(7) << (exp + sig - 3)) + (BigInt(1) << (sig - 2))).U(recodedWidth.W) def isNaN(x: UInt) = x(sig + exp - 1, sig + exp - 3).andR def isSNaN(x: UInt) = isNaN(x) && !x(sig - 2) def classify(x: UInt) = { val sign = x(sig + exp) val code = x(exp + sig - 1, exp + sig - 3) val codeHi = code(2, 1) val isSpecial = codeHi === 3.U val isHighSubnormalIn = x(exp + sig - 3, sig - 1) < 2.U val isSubnormal = code === 1.U || codeHi === 1.U && isHighSubnormalIn val isNormal = codeHi === 1.U && !isHighSubnormalIn || codeHi === 2.U val isZero = code === 0.U val isInf = isSpecial && !code(0) val isNaN = code.andR val isSNaN = isNaN && !x(sig-2) val isQNaN = isNaN && x(sig-2) Cat(isQNaN, isSNaN, isInf && !sign, isNormal && !sign, isSubnormal && !sign, isZero && !sign, isZero && sign, isSubnormal && sign, isNormal && sign, isInf && sign) } // convert between formats, ignoring rounding, range, NaN def unsafeConvert(x: UInt, to: FType) = if (this == to) x else { val sign = x(sig + exp) val fractIn = x(sig - 2, 0) val expIn = x(sig + exp - 1, sig - 1) val fractOut = fractIn << to.sig >> sig val expOut = { val expCode = expIn(exp, exp - 2) val commonCase = (expIn + (1 << to.exp).U) - (1 << exp).U Mux(expCode === 0.U || expCode >= 6.U, Cat(expCode, commonCase(to.exp - 3, 0)), commonCase(to.exp, 0)) } Cat(sign, expOut, fractOut) } private def ieeeBundle = { val expWidth = exp class IEEEBundle extends Bundle { val sign = Bool() val exp = UInt(expWidth.W) val sig = UInt((ieeeWidth-expWidth-1).W) } new IEEEBundle } def unpackIEEE(x: UInt) = x.asTypeOf(ieeeBundle) def recode(x: UInt) = hardfloat.recFNFromFN(exp, sig, x) def ieee(x: UInt) = hardfloat.fNFromRecFN(exp, sig, x) } object FType { val H = new FType(5, 11) val S = new FType(8, 24) val D = new FType(11, 53) val all = List(H, S, D) } trait HasFPUParameters { require(fLen == 0 || FType.all.exists(_.ieeeWidth == fLen)) val minFLen: Int val fLen: Int def xLen: Int val minXLen = 32 val nIntTypes = log2Ceil(xLen/minXLen) + 1 def floatTypes = FType.all.filter(t => minFLen <= t.ieeeWidth && t.ieeeWidth <= fLen) def minType = floatTypes.head def maxType = floatTypes.last def prevType(t: FType) = floatTypes(typeTag(t) - 1) def maxExpWidth = maxType.exp def maxSigWidth = maxType.sig def typeTag(t: FType) = floatTypes.indexOf(t) def typeTagWbOffset = (FType.all.indexOf(minType) + 1).U def typeTagGroup(t: FType) = (if (floatTypes.contains(t)) typeTag(t) else typeTag(maxType)).U // typeTag def H = typeTagGroup(FType.H) def S = typeTagGroup(FType.S) def D = typeTagGroup(FType.D) def I = typeTag(maxType).U private def isBox(x: UInt, t: FType): Bool = x(t.sig + t.exp, t.sig + t.exp - 4).andR private def box(x: UInt, xt: FType, y: UInt, yt: FType): UInt = { require(xt.ieeeWidth == 2 * yt.ieeeWidth) val swizzledNaN = Cat( x(xt.sig + xt.exp, xt.sig + xt.exp - 3), x(xt.sig - 2, yt.recodedWidth - 1).andR, x(xt.sig + xt.exp - 5, xt.sig), y(yt.recodedWidth - 2), x(xt.sig - 2, yt.recodedWidth - 1), y(yt.recodedWidth - 1), y(yt.recodedWidth - 3, 0)) Mux(xt.isNaN(x), swizzledNaN, x) } // implement NaN unboxing for FU inputs def unbox(x: UInt, tag: UInt, exactType: Option[FType]): UInt = { val outType = exactType.getOrElse(maxType) def helper(x: UInt, t: FType): Seq[(Bool, UInt)] = { val prev = if (t == minType) { Seq() } else { val prevT = prevType(t) val unswizzled = Cat( x(prevT.sig + prevT.exp - 1), x(t.sig - 1), x(prevT.sig + prevT.exp - 2, 0)) val prev = helper(unswizzled, prevT) val isbox = isBox(x, t) prev.map(p => (isbox && p._1, p._2)) } prev :+ (true.B, t.unsafeConvert(x, outType)) } val (oks, floats) = helper(x, maxType).unzip if (exactType.isEmpty || floatTypes.size == 1) { Mux(oks(tag), floats(tag), maxType.qNaN) } else { val t = exactType.get floats(typeTag(t)) | Mux(oks(typeTag(t)), 0.U, t.qNaN) } } // make sure that the redundant bits in the NaN-boxed encoding are consistent def consistent(x: UInt): Bool = { def helper(x: UInt, t: FType): Bool = if (typeTag(t) == 0) true.B else { val prevT = prevType(t) val unswizzled = Cat( x(prevT.sig + prevT.exp - 1), x(t.sig - 1), x(prevT.sig + prevT.exp - 2, 0)) val prevOK = !isBox(x, t) || helper(unswizzled, prevT) val curOK = !t.isNaN(x) || x(t.sig + t.exp - 4) === x(t.sig - 2, prevT.recodedWidth - 1).andR prevOK && curOK } helper(x, maxType) } // generate a NaN box from an FU result def box(x: UInt, t: FType): UInt = { if (t == maxType) { x } else { val nt = floatTypes(typeTag(t) + 1) val bigger = box(((BigInt(1) << nt.recodedWidth)-1).U, nt, x, t) bigger | ((BigInt(1) << maxType.recodedWidth) - (BigInt(1) << nt.recodedWidth)).U } } // generate a NaN box from an FU result def box(x: UInt, tag: UInt): UInt = { val opts = floatTypes.map(t => box(x, t)) opts(tag) } // zap bits that hardfloat thinks are don't-cares, but we do care about def sanitizeNaN(x: UInt, t: FType): UInt = { if (typeTag(t) == 0) { x } else { val maskedNaN = x & ~((BigInt(1) << (t.sig-1)) | (BigInt(1) << (t.sig+t.exp-4))).U(t.recodedWidth.W) Mux(t.isNaN(x), maskedNaN, x) } } // implement NaN boxing and recoding for FL*/fmv.*.x def recode(x: UInt, tag: UInt): UInt = { def helper(x: UInt, t: FType): UInt = { if (typeTag(t) == 0) { t.recode(x) } else { val prevT = prevType(t) box(t.recode(x), t, helper(x, prevT), prevT) } } // fill MSBs of subword loads to emulate a wider load of a NaN-boxed value val boxes = floatTypes.map(t => ((BigInt(1) << maxType.ieeeWidth) - (BigInt(1) << t.ieeeWidth)).U) helper(boxes(tag) | x, maxType) } // implement NaN unboxing and un-recoding for FS*/fmv.x.* def ieee(x: UInt, t: FType = maxType): UInt = { if (typeTag(t) == 0) { t.ieee(x) } else { val unrecoded = t.ieee(x) val prevT = prevType(t) val prevRecoded = Cat( x(prevT.recodedWidth-2), x(t.sig-1), x(prevT.recodedWidth-3, 0)) val prevUnrecoded = ieee(prevRecoded, prevT) Cat(unrecoded >> prevT.ieeeWidth, Mux(t.isNaN(x), prevUnrecoded, unrecoded(prevT.ieeeWidth-1, 0))) } } } abstract class FPUModule(implicit val p: Parameters) extends Module with HasCoreParameters with HasFPUParameters class FPToInt(implicit p: Parameters) extends FPUModule()(p) with ShouldBeRetimed { class Output extends Bundle { val in = new FPInput val lt = Bool() val store = Bits(fLen.W) val toint = Bits(xLen.W) val exc = Bits(FPConstants.FLAGS_SZ.W) } val io = IO(new Bundle { val in = Flipped(Valid(new FPInput)) val out = Valid(new Output) }) val in = RegEnable(io.in.bits, io.in.valid) val valid = RegNext(io.in.valid) val dcmp = Module(new hardfloat.CompareRecFN(maxExpWidth, maxSigWidth)) dcmp.io.a := in.in1 dcmp.io.b := in.in2 dcmp.io.signaling := !in.rm(1) val tag = in.typeTagOut val toint_ieee = (floatTypes.map(t => if (t == FType.H) Fill(maxType.ieeeWidth / minXLen, ieee(in.in1)(15, 0).sextTo(minXLen)) else Fill(maxType.ieeeWidth / t.ieeeWidth, ieee(in.in1)(t.ieeeWidth - 1, 0))): Seq[UInt])(tag) val toint = WireDefault(toint_ieee) val intType = WireDefault(in.fmt(0)) io.out.bits.store := (floatTypes.map(t => Fill(fLen / t.ieeeWidth, ieee(in.in1)(t.ieeeWidth - 1, 0))): Seq[UInt])(tag) io.out.bits.toint := ((0 until nIntTypes).map(i => toint((minXLen << i) - 1, 0).sextTo(xLen)): Seq[UInt])(intType) io.out.bits.exc := 0.U when (in.rm(0)) { val classify_out = (floatTypes.map(t => t.classify(maxType.unsafeConvert(in.in1, t))): Seq[UInt])(tag) toint := classify_out | (toint_ieee >> minXLen << minXLen) intType := false.B } when (in.wflags) { // feq/flt/fle, fcvt toint := (~in.rm & Cat(dcmp.io.lt, dcmp.io.eq)).orR | (toint_ieee >> minXLen << minXLen) io.out.bits.exc := dcmp.io.exceptionFlags intType := false.B when (!in.ren2) { // fcvt val cvtType = in.typ.extract(log2Ceil(nIntTypes), 1) intType := cvtType val conv = Module(new hardfloat.RecFNToIN(maxExpWidth, maxSigWidth, xLen)) conv.io.in := in.in1 conv.io.roundingMode := in.rm conv.io.signedOut := ~in.typ(0) toint := conv.io.out io.out.bits.exc := Cat(conv.io.intExceptionFlags(2, 1).orR, 0.U(3.W), conv.io.intExceptionFlags(0)) for (i <- 0 until nIntTypes-1) { val w = minXLen << i when (cvtType === i.U) { val narrow = Module(new hardfloat.RecFNToIN(maxExpWidth, maxSigWidth, w)) narrow.io.in := in.in1 narrow.io.roundingMode := in.rm narrow.io.signedOut := ~in.typ(0) val excSign = in.in1(maxExpWidth + maxSigWidth) && !maxType.isNaN(in.in1) val excOut = Cat(conv.io.signedOut === excSign, Fill(w-1, !excSign)) val invalid = conv.io.intExceptionFlags(2) || narrow.io.intExceptionFlags(1) when (invalid) { toint := Cat(conv.io.out >> w, excOut) } io.out.bits.exc := Cat(invalid, 0.U(3.W), !invalid && conv.io.intExceptionFlags(0)) } } } } io.out.valid := valid io.out.bits.lt := dcmp.io.lt || (dcmp.io.a.asSInt < 0.S && dcmp.io.b.asSInt >= 0.S) io.out.bits.in := in } class IntToFP(val latency: Int)(implicit p: Parameters) extends FPUModule()(p) with ShouldBeRetimed { val io = IO(new Bundle { val in = Flipped(Valid(new IntToFPInput)) val out = Valid(new FPResult) }) val in = Pipe(io.in) val tag = in.bits.typeTagIn val mux = Wire(new FPResult) mux.exc := 0.U mux.data := recode(in.bits.in1, tag) val intValue = { val res = WireDefault(in.bits.in1.asSInt) for (i <- 0 until nIntTypes-1) { val smallInt = in.bits.in1((minXLen << i) - 1, 0) when (in.bits.typ.extract(log2Ceil(nIntTypes), 1) === i.U) { res := Mux(in.bits.typ(0), smallInt.zext, smallInt.asSInt) } } res.asUInt } when (in.bits.wflags) { // fcvt // could be improved for RVD/RVQ with a single variable-position rounding // unit, rather than N fixed-position ones val i2fResults = for (t <- floatTypes) yield { val i2f = Module(new hardfloat.INToRecFN(xLen, t.exp, t.sig)) i2f.io.signedIn := ~in.bits.typ(0) i2f.io.in := intValue i2f.io.roundingMode := in.bits.rm i2f.io.detectTininess := hardfloat.consts.tininess_afterRounding (sanitizeNaN(i2f.io.out, t), i2f.io.exceptionFlags) } val (data, exc) = i2fResults.unzip val dataPadded = data.init.map(d => Cat(data.last >> d.getWidth, d)) :+ data.last mux.data := dataPadded(tag) mux.exc := exc(tag) } io.out <> Pipe(in.valid, mux, latency-1) } class FPToFP(val latency: Int)(implicit p: Parameters) extends FPUModule()(p) with ShouldBeRetimed { val io = IO(new Bundle { val in = Flipped(Valid(new FPInput)) val out = Valid(new FPResult) val lt = Input(Bool()) // from FPToInt }) val in = Pipe(io.in) val signNum = Mux(in.bits.rm(1), in.bits.in1 ^ in.bits.in2, Mux(in.bits.rm(0), ~in.bits.in2, in.bits.in2)) val fsgnj = Cat(signNum(fLen), in.bits.in1(fLen-1, 0)) val fsgnjMux = Wire(new FPResult) fsgnjMux.exc := 0.U fsgnjMux.data := fsgnj when (in.bits.wflags) { // fmin/fmax val isnan1 = maxType.isNaN(in.bits.in1) val isnan2 = maxType.isNaN(in.bits.in2) val isInvalid = maxType.isSNaN(in.bits.in1) || maxType.isSNaN(in.bits.in2) val isNaNOut = isnan1 && isnan2 val isLHS = isnan2 || in.bits.rm(0) =/= io.lt && !isnan1 fsgnjMux.exc := isInvalid << 4 fsgnjMux.data := Mux(isNaNOut, maxType.qNaN, Mux(isLHS, in.bits.in1, in.bits.in2)) } val inTag = in.bits.typeTagIn val outTag = in.bits.typeTagOut val mux = WireDefault(fsgnjMux) for (t <- floatTypes.init) { when (outTag === typeTag(t).U) { mux.data := Cat(fsgnjMux.data >> t.recodedWidth, maxType.unsafeConvert(fsgnjMux.data, t)) } } when (in.bits.wflags && !in.bits.ren2) { // fcvt if (floatTypes.size > 1) { // widening conversions simply canonicalize NaN operands val widened = Mux(maxType.isNaN(in.bits.in1), maxType.qNaN, in.bits.in1) fsgnjMux.data := widened fsgnjMux.exc := maxType.isSNaN(in.bits.in1) << 4 // narrowing conversions require rounding (for RVQ, this could be // optimized to use a single variable-position rounding unit, rather // than two fixed-position ones) for (outType <- floatTypes.init) when (outTag === typeTag(outType).U && ((typeTag(outType) == 0).B || outTag < inTag)) { val narrower = Module(new hardfloat.RecFNToRecFN(maxType.exp, maxType.sig, outType.exp, outType.sig)) narrower.io.in := in.bits.in1 narrower.io.roundingMode := in.bits.rm narrower.io.detectTininess := hardfloat.consts.tininess_afterRounding val narrowed = sanitizeNaN(narrower.io.out, outType) mux.data := Cat(fsgnjMux.data >> narrowed.getWidth, narrowed) mux.exc := narrower.io.exceptionFlags } } } io.out <> Pipe(in.valid, mux, latency-1) } class MulAddRecFNPipe(latency: Int, expWidth: Int, sigWidth: Int) extends Module { override def desiredName = s"MulAddRecFNPipe_l${latency}_e${expWidth}_s${sigWidth}" require(latency<=2) val io = IO(new Bundle { val validin = Input(Bool()) val op = Input(Bits(2.W)) val a = Input(Bits((expWidth + sigWidth + 1).W)) val b = Input(Bits((expWidth + sigWidth + 1).W)) val c = Input(Bits((expWidth + sigWidth + 1).W)) val roundingMode = Input(UInt(3.W)) val detectTininess = Input(UInt(1.W)) val out = Output(Bits((expWidth + sigWidth + 1).W)) val exceptionFlags = Output(Bits(5.W)) val validout = Output(Bool()) }) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val mulAddRecFNToRaw_preMul = Module(new hardfloat.MulAddRecFNToRaw_preMul(expWidth, sigWidth)) val mulAddRecFNToRaw_postMul = Module(new hardfloat.MulAddRecFNToRaw_postMul(expWidth, sigWidth)) mulAddRecFNToRaw_preMul.io.op := io.op mulAddRecFNToRaw_preMul.io.a := io.a mulAddRecFNToRaw_preMul.io.b := io.b mulAddRecFNToRaw_preMul.io.c := io.c val mulAddResult = (mulAddRecFNToRaw_preMul.io.mulAddA * mulAddRecFNToRaw_preMul.io.mulAddB) +& mulAddRecFNToRaw_preMul.io.mulAddC val valid_stage0 = Wire(Bool()) val roundingMode_stage0 = Wire(UInt(3.W)) val detectTininess_stage0 = Wire(UInt(1.W)) val postmul_regs = if(latency>0) 1 else 0 mulAddRecFNToRaw_postMul.io.fromPreMul := Pipe(io.validin, mulAddRecFNToRaw_preMul.io.toPostMul, postmul_regs).bits mulAddRecFNToRaw_postMul.io.mulAddResult := Pipe(io.validin, mulAddResult, postmul_regs).bits mulAddRecFNToRaw_postMul.io.roundingMode := Pipe(io.validin, io.roundingMode, postmul_regs).bits roundingMode_stage0 := Pipe(io.validin, io.roundingMode, postmul_regs).bits detectTininess_stage0 := Pipe(io.validin, io.detectTininess, postmul_regs).bits valid_stage0 := Pipe(io.validin, false.B, postmul_regs).valid //------------------------------------------------------------------------ //------------------------------------------------------------------------ val roundRawFNToRecFN = Module(new hardfloat.RoundRawFNToRecFN(expWidth, sigWidth, 0)) val round_regs = if(latency==2) 1 else 0 roundRawFNToRecFN.io.invalidExc := Pipe(valid_stage0, mulAddRecFNToRaw_postMul.io.invalidExc, round_regs).bits roundRawFNToRecFN.io.in := Pipe(valid_stage0, mulAddRecFNToRaw_postMul.io.rawOut, round_regs).bits roundRawFNToRecFN.io.roundingMode := Pipe(valid_stage0, roundingMode_stage0, round_regs).bits roundRawFNToRecFN.io.detectTininess := Pipe(valid_stage0, detectTininess_stage0, round_regs).bits io.validout := Pipe(valid_stage0, false.B, round_regs).valid roundRawFNToRecFN.io.infiniteExc := false.B io.out := roundRawFNToRecFN.io.out io.exceptionFlags := roundRawFNToRecFN.io.exceptionFlags } class FPUFMAPipe(val latency: Int, val t: FType) (implicit p: Parameters) extends FPUModule()(p) with ShouldBeRetimed { override def desiredName = s"FPUFMAPipe_l${latency}_f${t.ieeeWidth}" require(latency>0) val io = IO(new Bundle { val in = Flipped(Valid(new FPInput)) val out = Valid(new FPResult) }) val valid = RegNext(io.in.valid) val in = Reg(new FPInput) when (io.in.valid) { val one = 1.U << (t.sig + t.exp - 1) val zero = (io.in.bits.in1 ^ io.in.bits.in2) & (1.U << (t.sig + t.exp)) val cmd_fma = io.in.bits.ren3 val cmd_addsub = io.in.bits.swap23 in := io.in.bits when (cmd_addsub) { in.in2 := one } when (!(cmd_fma || cmd_addsub)) { in.in3 := zero } } val fma = Module(new MulAddRecFNPipe((latency-1) min 2, t.exp, t.sig)) fma.io.validin := valid fma.io.op := in.fmaCmd fma.io.roundingMode := in.rm fma.io.detectTininess := hardfloat.consts.tininess_afterRounding fma.io.a := in.in1 fma.io.b := in.in2 fma.io.c := in.in3 val res = Wire(new FPResult) res.data := sanitizeNaN(fma.io.out, t) res.exc := fma.io.exceptionFlags io.out := Pipe(fma.io.validout, res, (latency-3) max 0) } class FPU(cfg: FPUParams)(implicit p: Parameters) extends FPUModule()(p) { val io = IO(new FPUIO) val (useClockGating, useDebugROB) = coreParams match { case r: RocketCoreParams => val sz = if (r.debugROB.isDefined) r.debugROB.get.size else 1 (r.clockGate, sz < 1) case _ => (false, false) } val clock_en_reg = Reg(Bool()) val clock_en = clock_en_reg || io.cp_req.valid val gated_clock = if (!useClockGating) clock else ClockGate(clock, clock_en, "fpu_clock_gate") val fp_decoder = Module(new FPUDecoder) fp_decoder.io.inst := io.inst val id_ctrl = WireInit(fp_decoder.io.sigs) coreParams match { case r: RocketCoreParams => r.vector.map(v => { val v_decode = v.decoder(p) // Only need to get ren1 v_decode.io.inst := io.inst v_decode.io.vconfig := DontCare // core deals with this when (v_decode.io.legal && v_decode.io.read_frs1) { id_ctrl.ren1 := true.B id_ctrl.swap12 := false.B id_ctrl.toint := true.B id_ctrl.typeTagIn := I id_ctrl.typeTagOut := Mux(io.v_sew === 3.U, D, S) } when (v_decode.io.write_frd) { id_ctrl.wen := true.B } })} val ex_reg_valid = RegNext(io.valid, false.B) val ex_reg_inst = RegEnable(io.inst, io.valid) val ex_reg_ctrl = RegEnable(id_ctrl, io.valid) val ex_ra = List.fill(3)(Reg(UInt())) // load/vector response val load_wb = RegNext(io.ll_resp_val) val load_wb_typeTag = RegEnable(io.ll_resp_type(1,0) - typeTagWbOffset, io.ll_resp_val) val load_wb_data = RegEnable(io.ll_resp_data, io.ll_resp_val) val load_wb_tag = RegEnable(io.ll_resp_tag, io.ll_resp_val) class FPUImpl { // entering gated-clock domain val req_valid = ex_reg_valid || io.cp_req.valid val ex_cp_valid = io.cp_req.fire val mem_cp_valid = RegNext(ex_cp_valid, false.B) val wb_cp_valid = RegNext(mem_cp_valid, false.B) val mem_reg_valid = RegInit(false.B) val killm = (io.killm || io.nack_mem) && !mem_cp_valid // Kill X-stage instruction if M-stage is killed. This prevents it from // speculatively being sent to the div-sqrt unit, which can cause priority // inversion for two back-to-back divides, the first of which is killed. val killx = io.killx || mem_reg_valid && killm mem_reg_valid := ex_reg_valid && !killx || ex_cp_valid val mem_reg_inst = RegEnable(ex_reg_inst, ex_reg_valid) val wb_reg_valid = RegNext(mem_reg_valid && (!killm || mem_cp_valid), false.B) val cp_ctrl = Wire(new FPUCtrlSigs) cp_ctrl :<>= io.cp_req.bits.viewAsSupertype(new FPUCtrlSigs) io.cp_resp.valid := false.B io.cp_resp.bits.data := 0.U io.cp_resp.bits.exc := DontCare val ex_ctrl = Mux(ex_cp_valid, cp_ctrl, ex_reg_ctrl) val mem_ctrl = RegEnable(ex_ctrl, req_valid) val wb_ctrl = RegEnable(mem_ctrl, mem_reg_valid) // CoreMonitorBundle to monitor fp register file writes val frfWriteBundle = Seq.fill(2)(WireInit(new CoreMonitorBundle(xLen, fLen), DontCare)) frfWriteBundle.foreach { i => i.clock := clock i.reset := reset i.hartid := io.hartid i.timer := io.time(31,0) i.valid := false.B i.wrenx := false.B i.wrenf := false.B i.excpt := false.B } // regfile val regfile = Mem(32, Bits((fLen+1).W)) when (load_wb) { val wdata = recode(load_wb_data, load_wb_typeTag) regfile(load_wb_tag) := wdata assert(consistent(wdata)) if (enableCommitLog) printf("f%d p%d 0x%x\n", load_wb_tag, load_wb_tag + 32.U, ieee(wdata)) if (useDebugROB) DebugROB.pushWb(clock, reset, io.hartid, load_wb, load_wb_tag + 32.U, ieee(wdata)) frfWriteBundle(0).wrdst := load_wb_tag frfWriteBundle(0).wrenf := true.B frfWriteBundle(0).wrdata := ieee(wdata) } val ex_rs = ex_ra.map(a => regfile(a)) when (io.valid) { when (id_ctrl.ren1) { when (!id_ctrl.swap12) { ex_ra(0) := io.inst(19,15) } when (id_ctrl.swap12) { ex_ra(1) := io.inst(19,15) } } when (id_ctrl.ren2) { when (id_ctrl.swap12) { ex_ra(0) := io.inst(24,20) } when (id_ctrl.swap23) { ex_ra(2) := io.inst(24,20) } when (!id_ctrl.swap12 && !id_ctrl.swap23) { ex_ra(1) := io.inst(24,20) } } when (id_ctrl.ren3) { ex_ra(2) := io.inst(31,27) } } val ex_rm = Mux(ex_reg_inst(14,12) === 7.U, io.fcsr_rm, ex_reg_inst(14,12)) def fuInput(minT: Option[FType]): FPInput = { val req = Wire(new FPInput) val tag = ex_ctrl.typeTagIn req.viewAsSupertype(new Bundle with HasFPUCtrlSigs) :#= ex_ctrl.viewAsSupertype(new Bundle with HasFPUCtrlSigs) req.rm := ex_rm req.in1 := unbox(ex_rs(0), tag, minT) req.in2 := unbox(ex_rs(1), tag, minT) req.in3 := unbox(ex_rs(2), tag, minT) req.typ := ex_reg_inst(21,20) req.fmt := ex_reg_inst(26,25) req.fmaCmd := ex_reg_inst(3,2) | (!ex_ctrl.ren3 && ex_reg_inst(27)) when (ex_cp_valid) { req := io.cp_req.bits when (io.cp_req.bits.swap12) { req.in1 := io.cp_req.bits.in2 req.in2 := io.cp_req.bits.in1 } when (io.cp_req.bits.swap23) { req.in2 := io.cp_req.bits.in3 req.in3 := io.cp_req.bits.in2 } } req } val sfma = Module(new FPUFMAPipe(cfg.sfmaLatency, FType.S)) sfma.io.in.valid := req_valid && ex_ctrl.fma && ex_ctrl.typeTagOut === S sfma.io.in.bits := fuInput(Some(sfma.t)) val fpiu = Module(new FPToInt) fpiu.io.in.valid := req_valid && (ex_ctrl.toint || ex_ctrl.div || ex_ctrl.sqrt || (ex_ctrl.fastpipe && ex_ctrl.wflags)) fpiu.io.in.bits := fuInput(None) io.store_data := fpiu.io.out.bits.store io.toint_data := fpiu.io.out.bits.toint when(fpiu.io.out.valid && mem_cp_valid && mem_ctrl.toint){ io.cp_resp.bits.data := fpiu.io.out.bits.toint io.cp_resp.valid := true.B } val ifpu = Module(new IntToFP(cfg.ifpuLatency)) ifpu.io.in.valid := req_valid && ex_ctrl.fromint ifpu.io.in.bits := fpiu.io.in.bits ifpu.io.in.bits.in1 := Mux(ex_cp_valid, io.cp_req.bits.in1, io.fromint_data) val fpmu = Module(new FPToFP(cfg.fpmuLatency)) fpmu.io.in.valid := req_valid && ex_ctrl.fastpipe fpmu.io.in.bits := fpiu.io.in.bits fpmu.io.lt := fpiu.io.out.bits.lt val divSqrt_wen = WireDefault(false.B) val divSqrt_inFlight = WireDefault(false.B) val divSqrt_waddr = Reg(UInt(5.W)) val divSqrt_cp = Reg(Bool()) val divSqrt_typeTag = Wire(UInt(log2Up(floatTypes.size).W)) val divSqrt_wdata = Wire(UInt((fLen+1).W)) val divSqrt_flags = Wire(UInt(FPConstants.FLAGS_SZ.W)) divSqrt_typeTag := DontCare divSqrt_wdata := DontCare divSqrt_flags := DontCare // writeback arbitration case class Pipe(p: Module, lat: Int, cond: (FPUCtrlSigs) => Bool, res: FPResult) val pipes = List( Pipe(fpmu, fpmu.latency, (c: FPUCtrlSigs) => c.fastpipe, fpmu.io.out.bits), Pipe(ifpu, ifpu.latency, (c: FPUCtrlSigs) => c.fromint, ifpu.io.out.bits), Pipe(sfma, sfma.latency, (c: FPUCtrlSigs) => c.fma && c.typeTagOut === S, sfma.io.out.bits)) ++ (fLen > 32).option({ val dfma = Module(new FPUFMAPipe(cfg.dfmaLatency, FType.D)) dfma.io.in.valid := req_valid && ex_ctrl.fma && ex_ctrl.typeTagOut === D dfma.io.in.bits := fuInput(Some(dfma.t)) Pipe(dfma, dfma.latency, (c: FPUCtrlSigs) => c.fma && c.typeTagOut === D, dfma.io.out.bits) }) ++ (minFLen == 16).option({ val hfma = Module(new FPUFMAPipe(cfg.sfmaLatency, FType.H)) hfma.io.in.valid := req_valid && ex_ctrl.fma && ex_ctrl.typeTagOut === H hfma.io.in.bits := fuInput(Some(hfma.t)) Pipe(hfma, hfma.latency, (c: FPUCtrlSigs) => c.fma && c.typeTagOut === H, hfma.io.out.bits) }) def latencyMask(c: FPUCtrlSigs, offset: Int) = { require(pipes.forall(_.lat >= offset)) pipes.map(p => Mux(p.cond(c), (1 << p.lat-offset).U, 0.U)).reduce(_|_) } def pipeid(c: FPUCtrlSigs) = pipes.zipWithIndex.map(p => Mux(p._1.cond(c), p._2.U, 0.U)).reduce(_|_) val maxLatency = pipes.map(_.lat).max val memLatencyMask = latencyMask(mem_ctrl, 2) class WBInfo extends Bundle { val rd = UInt(5.W) val typeTag = UInt(log2Up(floatTypes.size).W) val cp = Bool() val pipeid = UInt(log2Ceil(pipes.size).W) } val wen = RegInit(0.U((maxLatency-1).W)) val wbInfo = Reg(Vec(maxLatency-1, new WBInfo)) val mem_wen = mem_reg_valid && (mem_ctrl.fma || mem_ctrl.fastpipe || mem_ctrl.fromint) val write_port_busy = RegEnable(mem_wen && (memLatencyMask & latencyMask(ex_ctrl, 1)).orR || (wen & latencyMask(ex_ctrl, 0)).orR, req_valid) ccover(mem_reg_valid && write_port_busy, "WB_STRUCTURAL", "structural hazard on writeback") for (i <- 0 until maxLatency-2) { when (wen(i+1)) { wbInfo(i) := wbInfo(i+1) } } wen := wen >> 1 when (mem_wen) { when (!killm) { wen := wen >> 1 | memLatencyMask } for (i <- 0 until maxLatency-1) { when (!write_port_busy && memLatencyMask(i)) { wbInfo(i).cp := mem_cp_valid wbInfo(i).typeTag := mem_ctrl.typeTagOut wbInfo(i).pipeid := pipeid(mem_ctrl) wbInfo(i).rd := mem_reg_inst(11,7) } } } val waddr = Mux(divSqrt_wen, divSqrt_waddr, wbInfo(0).rd) val wb_cp = Mux(divSqrt_wen, divSqrt_cp, wbInfo(0).cp) val wtypeTag = Mux(divSqrt_wen, divSqrt_typeTag, wbInfo(0).typeTag) val wdata = box(Mux(divSqrt_wen, divSqrt_wdata, (pipes.map(_.res.data): Seq[UInt])(wbInfo(0).pipeid)), wtypeTag) val wexc = (pipes.map(_.res.exc): Seq[UInt])(wbInfo(0).pipeid) when ((!wbInfo(0).cp && wen(0)) || divSqrt_wen) { assert(consistent(wdata)) regfile(waddr) := wdata if (enableCommitLog) { printf("f%d p%d 0x%x\n", waddr, waddr + 32.U, ieee(wdata)) } frfWriteBundle(1).wrdst := waddr frfWriteBundle(1).wrenf := true.B frfWriteBundle(1).wrdata := ieee(wdata) } if (useDebugROB) { DebugROB.pushWb(clock, reset, io.hartid, (!wbInfo(0).cp && wen(0)) || divSqrt_wen, waddr + 32.U, ieee(wdata)) } when (wb_cp && (wen(0) || divSqrt_wen)) { io.cp_resp.bits.data := wdata io.cp_resp.valid := true.B } assert(!io.cp_req.valid || pipes.forall(_.lat == pipes.head.lat).B, s"FPU only supports coprocessor if FMA pipes have uniform latency ${pipes.map(_.lat)}") // Avoid structural hazards and nacking of external requests // toint responds in the MEM stage, so an incoming toint can induce a structural hazard against inflight FMAs io.cp_req.ready := !ex_reg_valid && !(cp_ctrl.toint && wen =/= 0.U) && !divSqrt_inFlight val wb_toint_valid = wb_reg_valid && wb_ctrl.toint val wb_toint_exc = RegEnable(fpiu.io.out.bits.exc, mem_ctrl.toint) io.fcsr_flags.valid := wb_toint_valid || divSqrt_wen || wen(0) io.fcsr_flags.bits := Mux(wb_toint_valid, wb_toint_exc, 0.U) | Mux(divSqrt_wen, divSqrt_flags, 0.U) | Mux(wen(0), wexc, 0.U) val divSqrt_write_port_busy = (mem_ctrl.div || mem_ctrl.sqrt) && wen.orR io.fcsr_rdy := !(ex_reg_valid && ex_ctrl.wflags || mem_reg_valid && mem_ctrl.wflags || wb_reg_valid && wb_ctrl.toint || wen.orR || divSqrt_inFlight) io.nack_mem := (write_port_busy || divSqrt_write_port_busy || divSqrt_inFlight) && !mem_cp_valid io.dec <> id_ctrl def useScoreboard(f: ((Pipe, Int)) => Bool) = pipes.zipWithIndex.filter(_._1.lat > 3).map(x => f(x)).fold(false.B)(_||_) io.sboard_set := wb_reg_valid && !wb_cp_valid && RegNext(useScoreboard(_._1.cond(mem_ctrl)) || mem_ctrl.div || mem_ctrl.sqrt || mem_ctrl.vec) io.sboard_clr := !wb_cp_valid && (divSqrt_wen || (wen(0) && useScoreboard(x => wbInfo(0).pipeid === x._2.U))) io.sboard_clra := waddr ccover(io.sboard_clr && load_wb, "DUAL_WRITEBACK", "load and FMA writeback on same cycle") // we don't currently support round-max-magnitude (rm=4) io.illegal_rm := io.inst(14,12).isOneOf(5.U, 6.U) || io.inst(14,12) === 7.U && io.fcsr_rm >= 5.U if (cfg.divSqrt) { val divSqrt_inValid = mem_reg_valid && (mem_ctrl.div || mem_ctrl.sqrt) && !divSqrt_inFlight val divSqrt_killed = RegNext(divSqrt_inValid && killm, true.B) when (divSqrt_inValid) { divSqrt_waddr := mem_reg_inst(11,7) divSqrt_cp := mem_cp_valid } ccover(divSqrt_inFlight && divSqrt_killed, "DIV_KILLED", "divide killed after issued to divider") ccover(divSqrt_inFlight && mem_reg_valid && (mem_ctrl.div || mem_ctrl.sqrt), "DIV_BUSY", "divider structural hazard") ccover(mem_reg_valid && divSqrt_write_port_busy, "DIV_WB_STRUCTURAL", "structural hazard on division writeback") for (t <- floatTypes) { val tag = mem_ctrl.typeTagOut val divSqrt = withReset(divSqrt_killed) { Module(new hardfloat.DivSqrtRecFN_small(t.exp, t.sig, 0)) } divSqrt.io.inValid := divSqrt_inValid && tag === typeTag(t).U divSqrt.io.sqrtOp := mem_ctrl.sqrt divSqrt.io.a := maxType.unsafeConvert(fpiu.io.out.bits.in.in1, t) divSqrt.io.b := maxType.unsafeConvert(fpiu.io.out.bits.in.in2, t) divSqrt.io.roundingMode := fpiu.io.out.bits.in.rm divSqrt.io.detectTininess := hardfloat.consts.tininess_afterRounding when (!divSqrt.io.inReady) { divSqrt_inFlight := true.B } // only 1 in flight when (divSqrt.io.outValid_div || divSqrt.io.outValid_sqrt) { divSqrt_wen := !divSqrt_killed divSqrt_wdata := sanitizeNaN(divSqrt.io.out, t) divSqrt_flags := divSqrt.io.exceptionFlags divSqrt_typeTag := typeTag(t).U } } when (divSqrt_killed) { divSqrt_inFlight := false.B } } else { when (id_ctrl.div || id_ctrl.sqrt) { io.illegal_rm := true.B } } // gate the clock clock_en_reg := !useClockGating.B || io.keep_clock_enabled || // chicken bit io.valid || // ID stage req_valid || // EX stage mem_reg_valid || mem_cp_valid || // MEM stage wb_reg_valid || wb_cp_valid || // WB stage wen.orR || divSqrt_inFlight || // post-WB stage io.ll_resp_val // load writeback } // leaving gated-clock domain val fpuImpl = withClock (gated_clock) { new FPUImpl } def ccover(cond: Bool, label: String, desc: String)(implicit sourceInfo: SourceInfo) = property.cover(cond, s"FPU_$label", "Core;;" + desc) }

module FPUFMAPipe_l3_f16_6( // @[FPU.scala:697:7] input clock, // @[FPU.scala:697:7] input reset, // @[FPU.scala:697:7] input io_in_valid, // @[FPU.scala:702:14] input io_in_bits_ldst, // @[FPU.scala:702:14] input io_in_bits_wen, // @[FPU.scala:702:14] input io_in_bits_ren1, // @[FPU.scala:702:14] input io_in_bits_ren2, // @[FPU.scala:702:14] input io_in_bits_ren3, // @[FPU.scala:702:14] input io_in_bits_swap12, // @[FPU.scala:702:14] input io_in_bits_swap23, // @[FPU.scala:702:14] input [1:0] io_in_bits_typeTagIn, // @[FPU.scala:702:14] input [1:0] io_in_bits_typeTagOut, // @[FPU.scala:702:14] input io_in_bits_fromint, // @[FPU.scala:702:14] input io_in_bits_toint, // @[FPU.scala:702:14] input io_in_bits_fastpipe, // @[FPU.scala:702:14] input io_in_bits_fma, // @[FPU.scala:702:14] input io_in_bits_div, // @[FPU.scala:702:14] input io_in_bits_sqrt, // @[FPU.scala:702:14] input io_in_bits_wflags, // @[FPU.scala:702:14] input io_in_bits_vec, // @[FPU.scala:702:14] input [2:0] io_in_bits_rm, // @[FPU.scala:702:14] input [1:0] io_in_bits_fmaCmd, // @[FPU.scala:702:14] input [1:0] io_in_bits_typ, // @[FPU.scala:702:14] input [1:0] io_in_bits_fmt, // @[FPU.scala:702:14] input [64:0] io_in_bits_in1, // @[FPU.scala:702:14] input [64:0] io_in_bits_in2, // @[FPU.scala:702:14] input [64:0] io_in_bits_in3, // @[FPU.scala:702:14] output [64:0] io_out_bits_data, // @[FPU.scala:702:14] output [4:0] io_out_bits_exc // @[FPU.scala:702:14] ); wire [64:0] res_data; // @[FPU.scala:728:17] wire [16:0] _fma_io_out; // @[FPU.scala:719:19] wire io_in_valid_0 = io_in_valid; // @[FPU.scala:697:7] wire io_in_bits_ldst_0 = io_in_bits_ldst; // @[FPU.scala:697:7] wire io_in_bits_wen_0 = io_in_bits_wen; // @[FPU.scala:697:7] wire io_in_bits_ren1_0 = io_in_bits_ren1; // @[FPU.scala:697:7] wire io_in_bits_ren2_0 = io_in_bits_ren2; // @[FPU.scala:697:7] wire io_in_bits_ren3_0 = io_in_bits_ren3; // @[FPU.scala:697:7] wire io_in_bits_swap12_0 = io_in_bits_swap12; // @[FPU.scala:697:7] wire io_in_bits_swap23_0 = io_in_bits_swap23; // @[FPU.scala:697:7] wire [1:0] io_in_bits_typeTagIn_0 = io_in_bits_typeTagIn; // @[FPU.scala:697:7] wire [1:0] io_in_bits_typeTagOut_0 = io_in_bits_typeTagOut; // @[FPU.scala:697:7] wire io_in_bits_fromint_0 = io_in_bits_fromint; // @[FPU.scala:697:7] wire io_in_bits_toint_0 = io_in_bits_toint; // @[FPU.scala:697:7] wire io_in_bits_fastpipe_0 = io_in_bits_fastpipe; // @[FPU.scala:697:7] wire io_in_bits_fma_0 = io_in_bits_fma; // @[FPU.scala:697:7] wire io_in_bits_div_0 = io_in_bits_div; // @[FPU.scala:697:7] wire io_in_bits_sqrt_0 = io_in_bits_sqrt; // @[FPU.scala:697:7] wire io_in_bits_wflags_0 = io_in_bits_wflags; // @[FPU.scala:697:7] wire io_in_bits_vec_0 = io_in_bits_vec; // @[FPU.scala:697:7] wire [2:0] io_in_bits_rm_0 = io_in_bits_rm; // @[FPU.scala:697:7] wire [1:0] io_in_bits_fmaCmd_0 = io_in_bits_fmaCmd; // @[FPU.scala:697:7] wire [1:0] io_in_bits_typ_0 = io_in_bits_typ; // @[FPU.scala:697:7] wire [1:0] io_in_bits_fmt_0 = io_in_bits_fmt; // @[FPU.scala:697:7] wire [64:0] io_in_bits_in1_0 = io_in_bits_in1; // @[FPU.scala:697:7] wire [64:0] io_in_bits_in2_0 = io_in_bits_in2; // @[FPU.scala:697:7] wire [64:0] io_in_bits_in3_0 = io_in_bits_in3; // @[FPU.scala:697:7] wire [15:0] one = 16'h8000; // @[FPU.scala:710:19] wire [16:0] _zero_T_1 = 17'h10000; // @[FPU.scala:711:57] wire io_out_out_valid; // @[Valid.scala:135:21] wire [64:0] io_out_out_bits_data; // @[Valid.scala:135:21] wire [4:0] io_out_out_bits_exc; // @[Valid.scala:135:21] wire [64:0] io_out_bits_data_0; // @[FPU.scala:697:7] wire [4:0] io_out_bits_exc_0; // @[FPU.scala:697:7] wire io_out_valid; // @[FPU.scala:697:7] reg valid; // @[FPU.scala:707:22] reg in_ldst; // @[FPU.scala:708:15] reg in_wen; // @[FPU.scala:708:15] reg in_ren1; // @[FPU.scala:708:15] reg in_ren2; // @[FPU.scala:708:15] reg in_ren3; // @[FPU.scala:708:15] reg in_swap12; // @[FPU.scala:708:15] reg in_swap23; // @[FPU.scala:708:15] reg [1:0] in_typeTagIn; // @[FPU.scala:708:15] reg [1:0] in_typeTagOut; // @[FPU.scala:708:15] reg in_fromint; // @[FPU.scala:708:15] reg in_toint; // @[FPU.scala:708:15] reg in_fastpipe; // @[FPU.scala:708:15] reg in_fma; // @[FPU.scala:708:15] reg in_div; // @[FPU.scala:708:15] reg in_sqrt; // @[FPU.scala:708:15] reg in_wflags; // @[FPU.scala:708:15] reg in_vec; // @[FPU.scala:708:15] reg [2:0] in_rm; // @[FPU.scala:708:15] reg [1:0] in_fmaCmd; // @[FPU.scala:708:15] reg [1:0] in_typ; // @[FPU.scala:708:15] reg [1:0] in_fmt; // @[FPU.scala:708:15] reg [64:0] in_in1; // @[FPU.scala:708:15] reg [64:0] in_in2; // @[FPU.scala:708:15] reg [64:0] in_in3; // @[FPU.scala:708:15] wire [64:0] _zero_T = io_in_bits_in1_0 ^ io_in_bits_in2_0; // @[FPU.scala:697:7, :711:32] wire [64:0] zero = {48'h0, _zero_T[16], 16'h0}; // @[FPU.scala:711:{32,50}] assign io_out_out_bits_data = res_data; // @[Valid.scala:135:21] wire [4:0] res_exc; // @[FPU.scala:728:17] assign io_out_out_bits_exc = res_exc; // @[Valid.scala:135:21] assign res_data = {48'h0, _fma_io_out}; // @[FPU.scala:711:50, :719:19, :728:17, :729:12] assign io_out_valid = io_out_out_valid; // @[Valid.scala:135:21] assign io_out_bits_data_0 = io_out_out_bits_data; // @[Valid.scala:135:21] assign io_out_bits_exc_0 = io_out_out_bits_exc; // @[Valid.scala:135:21] always @(posedge clock) begin // @[FPU.scala:697:7] valid <= io_in_valid_0; // @[FPU.scala:697:7, :707:22] if (io_in_valid_0) begin // @[FPU.scala:697:7] in_ldst <= io_in_bits_ldst_0; // @[FPU.scala:697:7, :708:15] in_wen <= io_in_bits_wen_0; // @[FPU.scala:697:7, :708:15] in_ren1 <= io_in_bits_ren1_0; // @[FPU.scala:697:7, :708:15] in_ren2 <= io_in_bits_ren2_0; // @[FPU.scala:697:7, :708:15] in_ren3 <= io_in_bits_ren3_0; // @[FPU.scala:697:7, :708:15] in_swap12 <= io_in_bits_swap12_0; // @[FPU.scala:697:7, :708:15] in_swap23 <= io_in_bits_swap23_0; // @[FPU.scala:697:7, :708:15] in_typeTagIn <= io_in_bits_typeTagIn_0; // @[FPU.scala:697:7, :708:15] in_typeTagOut <= io_in_bits_typeTagOut_0; // @[FPU.scala:697:7, :708:15] in_fromint <= io_in_bits_fromint_0; // @[FPU.scala:697:7, :708:15] in_toint <= io_in_bits_toint_0; // @[FPU.scala:697:7, :708:15] in_fastpipe <= io_in_bits_fastpipe_0; // @[FPU.scala:697:7, :708:15] in_fma <= io_in_bits_fma_0; // @[FPU.scala:697:7, :708:15] in_div <= io_in_bits_div_0; // @[FPU.scala:697:7, :708:15] in_sqrt <= io_in_bits_sqrt_0; // @[FPU.scala:697:7, :708:15] in_wflags <= io_in_bits_wflags_0; // @[FPU.scala:697:7, :708:15] in_vec <= io_in_bits_vec_0; // @[FPU.scala:697:7, :708:15] in_rm <= io_in_bits_rm_0; // @[FPU.scala:697:7, :708:15] in_fmaCmd <= io_in_bits_fmaCmd_0; // @[FPU.scala:697:7, :708:15] in_typ <= io_in_bits_typ_0; // @[FPU.scala:697:7, :708:15] in_fmt <= io_in_bits_fmt_0; // @[FPU.scala:697:7, :708:15] in_in1 <= io_in_bits_in1_0; // @[FPU.scala:697:7, :708:15] in_in2 <= io_in_bits_swap23_0 ? 65'h8000 : io_in_bits_in2_0; // @[FPU.scala:697:7, :708:15, :714:8, :715:{23,32}] in_in3 <= io_in_bits_ren3_0 | io_in_bits_swap23_0 ? io_in_bits_in3_0 : zero; // @[FPU.scala:697:7, :708:15, :711:50, :714:8, :716:{21,37,46}] end always @(posedge) MulAddRecFNPipe_l2_e5_s11_6 fma ( // @[FPU.scala:719:19] .clock (clock), .reset (reset), .io_validin (valid), // @[FPU.scala:707:22] .io_op (in_fmaCmd), // @[FPU.scala:708:15] .io_a (in_in1[16:0]), // @[FPU.scala:708:15, :724:12] .io_b (in_in2[16:0]), // @[FPU.scala:708:15, :725:12] .io_c (in_in3[16:0]), // @[FPU.scala:708:15, :726:12] .io_roundingMode (in_rm), // @[FPU.scala:708:15] .io_out (_fma_io_out), .io_exceptionFlags (res_exc), .io_validout (io_out_out_valid) ); // @[FPU.scala:719:19] assign io_out_bits_data = io_out_bits_data_0; // @[FPU.scala:697:7] assign io_out_bits_exc = io_out_bits_exc_0; // @[FPU.scala:697:7] endmodule

Generate the Verilog code corresponding to the following Chisel files. File Misc.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import scala.math._ class ParameterizedBundle(implicit p: Parameters) extends Bundle trait Clocked extends Bundle { val clock = Clock() val reset = Bool() } object DecoupledHelper { def apply(rvs: Bool*) = new DecoupledHelper(rvs) } class DecoupledHelper(val rvs: Seq[Bool]) { def fire(exclude: Bool, includes: Bool*) = { require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!") (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _) } def fire() = { rvs.reduce(_ && _) } } object MuxT { def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2)) def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3)) def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4)) } /** Creates a cascade of n MuxTs to search for a key value. */ object MuxTLookup { def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } } object ValidMux { def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]*): ValidIO[T] = { apply(v1 +: v2.toSeq) } def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = { val out = Wire(Valid(valids.head.bits.cloneType)) out.valid := valids.map(_.valid).reduce(_ || _) out.bits := MuxCase(valids.head.bits, valids.map(v => (v.valid -> v.bits))) out } } object Str { def apply(s: String): UInt = { var i = BigInt(0) require(s.forall(validChar _)) for (c <- s) i = (i << 8) | c i.U((s.length*8).W) } def apply(x: Char): UInt = { require(validChar(x)) x.U(8.W) } def apply(x: UInt): UInt = apply(x, 10) def apply(x: UInt, radix: Int): UInt = { val rad = radix.U val w = x.getWidth require(w > 0) var q = x var s = digit(q % rad) for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s) } s } def apply(x: SInt): UInt = apply(x, 10) def apply(x: SInt, radix: Int): UInt = { val neg = x < 0.S val abs = x.abs.asUInt if (radix != 10) { Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix)) } else { val rad = radix.U val w = abs.getWidth require(w > 0) var q = abs var s = digit(q % rad) var needSign = neg for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad val placeSpace = q === 0.U val space = Mux(needSign, Str('-'), Str(' ')) needSign = needSign && !placeSpace s = Cat(Mux(placeSpace, space, digit(q % rad)), s) } Cat(Mux(needSign, Str('-'), Str(' ')), s) } } private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0) private def validChar(x: Char) = x == (x & 0xFF) } object Split { def apply(x: UInt, n0: Int) = { val w = x.getWidth (x.extract(w-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n2: Int, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } } object Random { def apply(mod: Int, random: UInt): UInt = { if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0) else PriorityEncoder(partition(apply(1 << log2Up(mod*8), random), mod)) } def apply(mod: Int): UInt = apply(mod, randomizer) def oneHot(mod: Int, random: UInt): UInt = { if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0)) else PriorityEncoderOH(partition(apply(1 << log2Up(mod*8), random), mod)).asUInt } def oneHot(mod: Int): UInt = oneHot(mod, randomizer) private def randomizer = LFSR(16) private def partition(value: UInt, slices: Int) = Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U) } object Majority { def apply(in: Set[Bool]): Bool = { val n = (in.size >> 1) + 1 val clauses = in.subsets(n).map(_.reduce(_ && _)) clauses.reduce(_ || _) } def apply(in: Seq[Bool]): Bool = apply(in.toSet) def apply(in: UInt): Bool = apply(in.asBools.toSet) } object PopCountAtLeast { private def two(x: UInt): (Bool, Bool) = x.getWidth match { case 1 => (x.asBool, false.B) case n => val half = x.getWidth / 2 val (leftOne, leftTwo) = two(x(half - 1, 0)) val (rightOne, rightTwo) = two(x(x.getWidth - 1, half)) (leftOne || rightOne, leftTwo || rightTwo || (leftOne && rightOne)) } def apply(x: UInt, n: Int): Bool = n match { case 0 => true.B case 1 => x.orR case 2 => two(x)._2 case 3 => PopCount(x) >= n.U } } // This gets used everywhere, so make the smallest circuit possible ... // Given an address and size, create a mask of beatBytes size // eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111 // groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01 object MaskGen { def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = { require (groupBy >= 1 && beatBytes >= groupBy) require (isPow2(beatBytes) && isPow2(groupBy)) val lgBytes = log2Ceil(beatBytes) val sizeOH = UIntToOH(lgSize | 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) | (groupBy*2 - 1).U def helper(i: Int): Seq[(Bool, Bool)] = { if (i == 0) { Seq((lgSize >= lgBytes.asUInt, true.B)) } else { val sub = helper(i-1) val size = sizeOH(lgBytes - i) val bit = addr_lo(lgBytes - i) val nbit = !bit Seq.tabulate (1 << i) { j => val (sub_acc, sub_eq) = sub(j/2) val eq = sub_eq && (if (j % 2 == 1) bit else nbit) val acc = sub_acc || (size && eq) (acc, eq) } } } if (groupBy == beatBytes) 1.U else Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse) } } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /** Like Vec.apply(idx), but tolerates indices of mismatched width */ def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /** Any Data subtype that has a Bool member named valid. */ type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /** converts from camel case to to underscores, also removing all spaces */ def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /** converts spaces or underscores to hyphens, also lowering case */ def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y | (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y || y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /** Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation */ def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File SourceD.scala: /* * Copyright 2019 SiFive, Inc. * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You should have received a copy of LICENSE.Apache2 along with * this software. If not, you may obtain a copy at * * https://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ package sifive.blocks.inclusivecache import chisel3._ import chisel3.util._ import freechips.rocketchip.tilelink._ import freechips.rocketchip.util._ import TLMessages._ import TLAtomics._ import TLPermissions._ class SourceDRequest(params: InclusiveCacheParameters) extends FullRequest(params) { val sink = UInt(params.inner.bundle.sinkBits.W) val way = UInt(params.wayBits.W) val bad = Bool() } class SourceDHazard(params: InclusiveCacheParameters) extends InclusiveCacheBundle(params) { val set = UInt(params.setBits.W) val way = UInt(params.wayBits.W) } class PutBufferACEntry(params: InclusiveCacheParameters) extends InclusiveCacheBundle(params) { val data = UInt(params.inner.bundle.dataBits.W) val mask = UInt((params.inner.bundle.dataBits/8).W) val corrupt = Bool() } class SourceD(params: InclusiveCacheParameters) extends Module { val io = IO(new Bundle { val req = Flipped(Decoupled(new SourceDRequest(params))) val d = Decoupled(new TLBundleD(params.inner.bundle)) // Put data from SinkA val pb_pop = Decoupled(new PutBufferPop(params)) val pb_beat = Flipped(new PutBufferAEntry(params)) // Release data from SinkC val rel_pop = Decoupled(new PutBufferPop(params)) val rel_beat = Flipped(new PutBufferCEntry(params)) // Access to the BankedStore val bs_radr = Decoupled(new BankedStoreInnerAddress(params)) val bs_rdat = Flipped(new BankedStoreInnerDecoded(params)) val bs_wadr = Decoupled(new BankedStoreInnerAddress(params)) val bs_wdat = new BankedStoreInnerPoison(params) // Is it safe to evict/replace this way? val evict_req = Flipped(new SourceDHazard(params)) val evict_safe = Bool() val grant_req = Flipped(new SourceDHazard(params)) val grant_safe = Bool() }) val beatBytes = params.inner.manager.beatBytes val writeBytes = params.micro.writeBytes val s1_valid = Wire(Bool()) val s2_valid = Wire(Bool()) val s3_valid = Wire(Bool()) val s2_ready = Wire(Bool()) val s3_ready = Wire(Bool()) val s4_ready = Wire(Bool()) ////////////////////////////////////// STAGE 1 ////////////////////////////////////// // Reform the request beats val busy = RegInit(false.B) val s1_block_r = RegInit(false.B) val s1_counter = RegInit(0.U(params.innerBeatBits.W)) val s1_req_reg = RegEnable(io.req.bits, !busy && io.req.valid) val s1_req = Mux(!busy, io.req.bits, s1_req_reg) val s1_x_bypass = Wire(UInt((beatBytes/writeBytes).W)) // might go from high=>low during stall val s1_latch_bypass = RegNext(!(busy || io.req.valid) || s2_ready) val s1_bypass = Mux(s1_latch_bypass, s1_x_bypass, RegEnable(s1_x_bypass, s1_latch_bypass)) val s1_mask = MaskGen(s1_req.offset, s1_req.size, beatBytes, writeBytes) & ~s1_bypass val s1_grant = (s1_req.opcode === AcquireBlock && s1_req.param === BtoT) || s1_req.opcode === AcquirePerm val s1_need_r = s1_mask.orR && s1_req.prio(0) && s1_req.opcode =/= Hint && !s1_grant && (s1_req.opcode =/= PutFullData || s1_req.size < log2Ceil(writeBytes).U ) val s1_valid_r = (busy || io.req.valid) && s1_need_r && !s1_block_r val s1_need_pb = Mux(s1_req.prio(0), !s1_req.opcode(2), s1_req.opcode(0)) // hasData val s1_single = Mux(s1_req.prio(0), s1_req.opcode === Hint || s1_grant, s1_req.opcode === Release) val s1_retires = !s1_single // retire all operations with data in s3 for bypass (saves energy) // Alternatively: val s1_retires = s1_need_pb // retire only updates for bypass (less backpressure from WB) val s1_beats1 = Mux(s1_single, 0.U, UIntToOH1(s1_req.size, log2Up(params.cache.blockBytes)) >> log2Ceil(beatBytes)) val s1_beat = (s1_req.offset >> log2Ceil(beatBytes)) | s1_counter val s1_last = s1_counter === s1_beats1 val s1_first = s1_counter === 0.U params.ccover(s1_block_r, "SOURCED_1_SRAM_HOLD", "SRAM read-out successful, but stalled by stage 2") params.ccover(!s1_latch_bypass, "SOURCED_1_BYPASS_HOLD", "Bypass match successful, but stalled by stage 2") params.ccover((busy || io.req.valid) && !s1_need_r, "SOURCED_1_NO_MODIFY", "Transaction servicable without SRAM") io.bs_radr.valid := s1_valid_r io.bs_radr.bits.noop := false.B io.bs_radr.bits.way := s1_req.way io.bs_radr.bits.set := s1_req.set io.bs_radr.bits.beat := s1_beat io.bs_radr.bits.mask := s1_mask params.ccover(io.bs_radr.valid && !io.bs_radr.ready, "SOURCED_1_READ_STALL", "Data readout stalled") // Make a queue to catch BS readout during stalls val queue = Module(new Queue(chiselTypeOf(io.bs_rdat), 3, flow=true)) queue.io.enq.valid := RegNext(RegNext(io.bs_radr.fire)) queue.io.enq.bits := io.bs_rdat assert (!queue.io.enq.valid || queue.io.enq.ready) params.ccover(!queue.io.enq.ready, "SOURCED_1_QUEUE_FULL", "Filled SRAM skidpad queue completely") when (io.bs_radr.fire) { s1_block_r := true.B } when (io.req.valid) { busy := true.B } when (s1_valid && s2_ready) { s1_counter := s1_counter + 1.U s1_block_r := false.B when (s1_last) { s1_counter := 0.U busy := false.B } } params.ccover(s1_valid && !s2_ready, "SOURCED_1_STALL", "Stage 1 pipeline blocked") io.req.ready := !busy s1_valid := (busy || io.req.valid) && (!s1_valid_r || io.bs_radr.ready) ////////////////////////////////////// STAGE 2 ////////////////////////////////////// // Fetch the request data val s2_latch = s1_valid && s2_ready val s2_full = RegInit(false.B) val s2_valid_pb = RegInit(false.B) val s2_beat = RegEnable(s1_beat, s2_latch) val s2_bypass = RegEnable(s1_bypass, s2_latch) val s2_req = RegEnable(s1_req, s2_latch) val s2_last = RegEnable(s1_last, s2_latch) val s2_need_r = RegEnable(s1_need_r, s2_latch) val s2_need_pb = RegEnable(s1_need_pb, s2_latch) val s2_retires = RegEnable(s1_retires, s2_latch) val s2_need_d = RegEnable(!s1_need_pb || s1_first, s2_latch) val s2_pdata_raw = Wire(new PutBufferACEntry(params)) val s2_pdata = s2_pdata_raw holdUnless s2_valid_pb s2_pdata_raw.data := Mux(s2_req.prio(0), io.pb_beat.data, io.rel_beat.data) s2_pdata_raw.mask := Mux(s2_req.prio(0), io.pb_beat.mask, ~0.U(params.inner.manager.beatBytes.W)) s2_pdata_raw.corrupt := Mux(s2_req.prio(0), io.pb_beat.corrupt, io.rel_beat.corrupt) io.pb_pop.valid := s2_valid_pb && s2_req.prio(0) io.pb_pop.bits.index := s2_req.put io.pb_pop.bits.last := s2_last io.rel_pop.valid := s2_valid_pb && !s2_req.prio(0) io.rel_pop.bits.index := s2_req.put io.rel_pop.bits.last := s2_last params.ccover(io.pb_pop.valid && !io.pb_pop.ready, "SOURCED_2_PUTA_STALL", "Channel A put buffer was not ready in time") if (!params.firstLevel) params.ccover(io.rel_pop.valid && !io.rel_pop.ready, "SOURCED_2_PUTC_STALL", "Channel C put buffer was not ready in time") val pb_ready = Mux(s2_req.prio(0), io.pb_pop.ready, io.rel_pop.ready) when (pb_ready) { s2_valid_pb := false.B } when (s2_valid && s3_ready) { s2_full := false.B } when (s2_latch) { s2_valid_pb := s1_need_pb } when (s2_latch) { s2_full := true.B } params.ccover(s2_valid && !s3_ready, "SOURCED_2_STALL", "Stage 2 pipeline blocked") s2_valid := s2_full && (!s2_valid_pb || pb_ready) s2_ready := !s2_full || (s3_ready && (!s2_valid_pb || pb_ready)) ////////////////////////////////////// STAGE 3 ////////////////////////////////////// // Send D response val s3_latch = s2_valid && s3_ready val s3_full = RegInit(false.B) val s3_valid_d = RegInit(false.B) val s3_beat = RegEnable(s2_beat, s3_latch) val s3_bypass = RegEnable(s2_bypass, s3_latch) val s3_req = RegEnable(s2_req, s3_latch) val s3_adjusted_opcode = Mux(s3_req.bad, Get, s3_req.opcode) // kill update when denied val s3_last = RegEnable(s2_last, s3_latch) val s3_pdata = RegEnable(s2_pdata, s3_latch) val s3_need_pb = RegEnable(s2_need_pb, s3_latch) val s3_retires = RegEnable(s2_retires, s3_latch) val s3_need_r = RegEnable(s2_need_r, s3_latch) val s3_need_bs = s3_need_pb val s3_acq = s3_req.opcode === AcquireBlock || s3_req.opcode === AcquirePerm // Collect s3's data from either the BankedStore or bypass // NOTE: we use the s3_bypass passed down from s1_bypass, because s2-s4 were guarded by the hazard checks and not stale val s3_bypass_data = Wire(UInt()) def chunk(x: UInt): Seq[UInt] = Seq.tabulate(beatBytes/writeBytes) { i => x((i+1)*writeBytes*8-1, i*writeBytes*8) } def chop (x: UInt): Seq[Bool] = Seq.tabulate(beatBytes/writeBytes) { i => x(i) } def bypass(sel: UInt, x: UInt, y: UInt) = (chop(sel) zip (chunk(x) zip chunk(y))) .map { case (s, (x, y)) => Mux(s, x, y) } .asUInt val s3_rdata = bypass(s3_bypass, s3_bypass_data, queue.io.deq.bits.data) // Lookup table for response codes val grant = Mux(s3_req.param === BtoT, Grant, GrantData) val resp_opcode = VecInit(Seq(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, grant, Grant)) // No restrictions on the type of buffer used here val d = Wire(chiselTypeOf(io.d)) io.d <> params.micro.innerBuf.d(d) d.valid := s3_valid_d d.bits.opcode := Mux(s3_req.prio(0), resp_opcode(s3_req.opcode), ReleaseAck) d.bits.param := Mux(s3_req.prio(0) && s3_acq, Mux(s3_req.param =/= NtoB, toT, toB), 0.U) d.bits.size := s3_req.size d.bits.source := s3_req.source d.bits.sink := s3_req.sink d.bits.denied := s3_req.bad d.bits.data := s3_rdata d.bits.corrupt := s3_req.bad && d.bits.opcode(0) queue.io.deq.ready := s3_valid && s4_ready && s3_need_r assert (!s3_full || !s3_need_r || queue.io.deq.valid) when (d.ready) { s3_valid_d := false.B } when (s3_valid && s4_ready) { s3_full := false.B } when (s3_latch) { s3_valid_d := s2_need_d } when (s3_latch) { s3_full := true.B } params.ccover(s3_valid && !s4_ready, "SOURCED_3_STALL", "Stage 3 pipeline blocked") s3_valid := s3_full && (!s3_valid_d || d.ready) s3_ready := !s3_full || (s4_ready && (!s3_valid_d || d.ready)) ////////////////////////////////////// STAGE 4 ////////////////////////////////////// // Writeback updated data val s4_latch = s3_valid && s3_retires && s4_ready val s4_full = RegInit(false.B) val s4_beat = RegEnable(s3_beat, s4_latch) val s4_need_r = RegEnable(s3_need_r, s4_latch) val s4_need_bs = RegEnable(s3_need_bs, s4_latch) val s4_need_pb = RegEnable(s3_need_pb, s4_latch) val s4_req = RegEnable(s3_req, s4_latch) val s4_adjusted_opcode = RegEnable(s3_adjusted_opcode, s4_latch) val s4_pdata = RegEnable(s3_pdata, s4_latch) val s4_rdata = RegEnable(s3_rdata, s4_latch) val atomics = Module(new Atomics(params.inner.bundle)) atomics.io.write := s4_req.prio(2) atomics.io.a.opcode := s4_adjusted_opcode atomics.io.a.param := s4_req.param atomics.io.a.size := 0.U atomics.io.a.source := 0.U atomics.io.a.address := 0.U atomics.io.a.mask := s4_pdata.mask atomics.io.a.data := s4_pdata.data atomics.io.a.corrupt := DontCare atomics.io.data_in := s4_rdata io.bs_wadr.valid := s4_full && s4_need_bs io.bs_wadr.bits.noop := false.B io.bs_wadr.bits.way := s4_req.way io.bs_wadr.bits.set := s4_req.set io.bs_wadr.bits.beat := s4_beat io.bs_wadr.bits.mask := Cat(s4_pdata.mask.asBools.grouped(writeBytes).map(_.reduce(_||_)).toList.reverse) io.bs_wdat.data := atomics.io.data_out assert (!(s4_full && s4_need_pb && s4_pdata.corrupt), "Data poisoning unsupported") params.ccover(io.bs_wadr.valid && !io.bs_wadr.ready, "SOURCED_4_WRITEBACK_STALL", "Data writeback stalled") params.ccover(s4_req.prio(0) && s4_req.opcode === ArithmeticData && s4_req.param === MIN, "SOURCED_4_ATOMIC_MIN", "Evaluated a signed minimum atomic") params.ccover(s4_req.prio(0) && s4_req.opcode === ArithmeticData && s4_req.param === MAX, "SOURCED_4_ATOMIC_MAX", "Evaluated a signed maximum atomic") params.ccover(s4_req.prio(0) && s4_req.opcode === ArithmeticData && s4_req.param === MINU, "SOURCED_4_ATOMIC_MINU", "Evaluated an unsigned minimum atomic") params.ccover(s4_req.prio(0) && s4_req.opcode === ArithmeticData && s4_req.param === MAXU, "SOURCED_4_ATOMIC_MAXU", "Evaluated an unsigned minimum atomic") params.ccover(s4_req.prio(0) && s4_req.opcode === ArithmeticData && s4_req.param === ADD, "SOURCED_4_ATOMIC_ADD", "Evaluated an addition atomic") params.ccover(s4_req.prio(0) && s4_req.opcode === LogicalData && s4_req.param === XOR, "SOURCED_4_ATOMIC_XOR", "Evaluated a bitwise XOR atomic") params.ccover(s4_req.prio(0) && s4_req.opcode === LogicalData && s4_req.param === OR, "SOURCED_4_ATOMIC_OR", "Evaluated a bitwise OR atomic") params.ccover(s4_req.prio(0) && s4_req.opcode === LogicalData && s4_req.param === AND, "SOURCED_4_ATOMIC_AND", "Evaluated a bitwise AND atomic") params.ccover(s4_req.prio(0) && s4_req.opcode === LogicalData && s4_req.param === SWAP, "SOURCED_4_ATOMIC_SWAP", "Evaluated a bitwise SWAP atomic") when (io.bs_wadr.ready || !s4_need_bs) { s4_full := false.B } when (s4_latch) { s4_full := true.B } s4_ready := !s3_retires || !s4_full || io.bs_wadr.ready || !s4_need_bs ////////////////////////////////////// RETIRED ////////////////////////////////////// // Record for bypass the last three retired writebacks // We need 3 slots to collect what was in s2, s3, s4 when the request was in s1 // ... you can't rely on s4 being full if bubbles got introduced between s1 and s2 val retire = s4_full && (io.bs_wadr.ready || !s4_need_bs) val s5_req = RegEnable(s4_req, retire) val s5_beat = RegEnable(s4_beat, retire) val s5_dat = RegEnable(atomics.io.data_out, retire) val s6_req = RegEnable(s5_req, retire) val s6_beat = RegEnable(s5_beat, retire) val s6_dat = RegEnable(s5_dat, retire) val s7_dat = RegEnable(s6_dat, retire) ////////////////////////////////////// BYPASSS ////////////////////////////////////// // Manually retime this circuit to pull a register stage forward val pre_s3_req = Mux(s3_latch, s2_req, s3_req) val pre_s4_req = Mux(s4_latch, s3_req, s4_req) val pre_s5_req = Mux(retire, s4_req, s5_req) val pre_s6_req = Mux(retire, s5_req, s6_req) val pre_s3_beat = Mux(s3_latch, s2_beat, s3_beat) val pre_s4_beat = Mux(s4_latch, s3_beat, s4_beat) val pre_s5_beat = Mux(retire, s4_beat, s5_beat) val pre_s6_beat = Mux(retire, s5_beat, s6_beat) val pre_s5_dat = Mux(retire, atomics.io.data_out, s5_dat) val pre_s6_dat = Mux(retire, s5_dat, s6_dat) val pre_s7_dat = Mux(retire, s6_dat, s7_dat) val pre_s4_full = s4_latch || (!(io.bs_wadr.ready || !s4_need_bs) && s4_full) val pre_s3_4_match = pre_s4_req.set === pre_s3_req.set && pre_s4_req.way === pre_s3_req.way && pre_s4_beat === pre_s3_beat && pre_s4_full val pre_s3_5_match = pre_s5_req.set === pre_s3_req.set && pre_s5_req.way === pre_s3_req.way && pre_s5_beat === pre_s3_beat val pre_s3_6_match = pre_s6_req.set === pre_s3_req.set && pre_s6_req.way === pre_s3_req.way && pre_s6_beat === pre_s3_beat val pre_s3_4_bypass = Mux(pre_s3_4_match, MaskGen(pre_s4_req.offset, pre_s4_req.size, beatBytes, writeBytes), 0.U) val pre_s3_5_bypass = Mux(pre_s3_5_match, MaskGen(pre_s5_req.offset, pre_s5_req.size, beatBytes, writeBytes), 0.U) val pre_s3_6_bypass = Mux(pre_s3_6_match, MaskGen(pre_s6_req.offset, pre_s6_req.size, beatBytes, writeBytes), 0.U) s3_bypass_data := bypass(RegNext(pre_s3_4_bypass), atomics.io.data_out, RegNext( bypass(pre_s3_5_bypass, pre_s5_dat, bypass(pre_s3_6_bypass, pre_s6_dat, pre_s7_dat)))) // Detect which parts of s1 will be bypassed from later pipeline stages (s1-s4) // Note: we also bypass from reads ahead in the pipeline to save power val s1_2_match = s2_req.set === s1_req.set && s2_req.way === s1_req.way && s2_beat === s1_beat && s2_full && s2_retires val s1_3_match = s3_req.set === s1_req.set && s3_req.way === s1_req.way && s3_beat === s1_beat && s3_full && s3_retires val s1_4_match = s4_req.set === s1_req.set && s4_req.way === s1_req.way && s4_beat === s1_beat && s4_full for (i <- 0 until 8) { val cover = 1.U val s2 = s1_2_match === cover(0) val s3 = s1_3_match === cover(1) val s4 = s1_4_match === cover(2) params.ccover(io.req.valid && s2 && s3 && s4, "SOURCED_BYPASS_CASE_" + i, "Bypass data from all subsets of pipeline stages") } val s1_2_bypass = Mux(s1_2_match, MaskGen(s2_req.offset, s2_req.size, beatBytes, writeBytes), 0.U) val s1_3_bypass = Mux(s1_3_match, MaskGen(s3_req.offset, s3_req.size, beatBytes, writeBytes), 0.U) val s1_4_bypass = Mux(s1_4_match, MaskGen(s4_req.offset, s4_req.size, beatBytes, writeBytes), 0.U) s1_x_bypass := s1_2_bypass | s1_3_bypass | s1_4_bypass ////////////////////////////////////// HAZARDS ////////////////////////////////////// // SinkC, SourceC, and SinkD can never interfer with each other because their operation // is fully contained with an execution plan of an MSHR. That MSHR owns the entire set, so // there is no way for a data race. // However, SourceD is special. We allow it to run ahead after the MSHR and scheduler have // released control of a set+way. This is necessary to allow single cycle occupancy for // hits. Thus, we need to be careful about data hazards between SourceD and the other ports // of the BankedStore. We can at least compare to registers 's1_req_reg', because the first // cycle of SourceD falls within the occupancy of the MSHR's plan. // Must ReleaseData=> be interlocked? RaW hazard io.evict_safe := (!busy || io.evict_req.way =/= s1_req_reg.way || io.evict_req.set =/= s1_req_reg.set) && (!s2_full || io.evict_req.way =/= s2_req.way || io.evict_req.set =/= s2_req.set) && (!s3_full || io.evict_req.way =/= s3_req.way || io.evict_req.set =/= s3_req.set) && (!s4_full || io.evict_req.way =/= s4_req.way || io.evict_req.set =/= s4_req.set) // Must =>GrantData be interlocked? WaR hazard io.grant_safe := (!busy || io.grant_req.way =/= s1_req_reg.way || io.grant_req.set =/= s1_req_reg.set) && (!s2_full || io.grant_req.way =/= s2_req.way || io.grant_req.set =/= s2_req.set) && (!s3_full || io.grant_req.way =/= s3_req.way || io.grant_req.set =/= s3_req.set) && (!s4_full || io.grant_req.way =/= s4_req.way || io.grant_req.set =/= s4_req.set) // SourceD cannot overlap with SinkC b/c the only way inner caches could become // dirty such that they want to put data in via SinkC is if we Granted them permissions, // which must flow through the SourecD pipeline. }

module SourceD( // @[SourceD.scala:48:7] input clock, // @[SourceD.scala:48:7] input reset, // @[SourceD.scala:48:7] output io_req_ready, // @[SourceD.scala:50:14] input io_req_valid, // @[SourceD.scala:50:14] input io_req_bits_prio_0, // @[SourceD.scala:50:14] input io_req_bits_prio_1, // @[SourceD.scala:50:14] input io_req_bits_prio_2, // @[SourceD.scala:50:14] input io_req_bits_control, // @[SourceD.scala:50:14] input [2:0] io_req_bits_opcode, // @[SourceD.scala:50:14] input [2:0] io_req_bits_param, // @[SourceD.scala:50:14] input [2:0] io_req_bits_size, // @[SourceD.scala:50:14] input [4:0] io_req_bits_source, // @[SourceD.scala:50:14] input [11:0] io_req_bits_tag, // @[SourceD.scala:50:14] input [5:0] io_req_bits_offset, // @[SourceD.scala:50:14] input [5:0] io_req_bits_put, // @[SourceD.scala:50:14] input [9:0] io_req_bits_set, // @[SourceD.scala:50:14] input [2:0] io_req_bits_sink, // @[SourceD.scala:50:14] input [2:0] io_req_bits_way, // @[SourceD.scala:50:14] input io_req_bits_bad, // @[SourceD.scala:50:14] input io_d_ready, // @[SourceD.scala:50:14] output io_d_valid, // @[SourceD.scala:50:14] output [2:0] io_d_bits_opcode, // @[SourceD.scala:50:14] output [1:0] io_d_bits_param, // @[SourceD.scala:50:14] output [2:0] io_d_bits_size, // @[SourceD.scala:50:14] output [4:0] io_d_bits_source, // @[SourceD.scala:50:14] output [2:0] io_d_bits_sink, // @[SourceD.scala:50:14] output io_d_bits_denied, // @[SourceD.scala:50:14] output [63:0] io_d_bits_data, // @[SourceD.scala:50:14] output io_d_bits_corrupt, // @[SourceD.scala:50:14] input io_pb_pop_ready, // @[SourceD.scala:50:14] output io_pb_pop_valid, // @[SourceD.scala:50:14] output [5:0] io_pb_pop_bits_index, // @[SourceD.scala:50:14] output io_pb_pop_bits_last, // @[SourceD.scala:50:14] input [63:0] io_pb_beat_data, // @[SourceD.scala:50:14] input [7:0] io_pb_beat_mask, // @[SourceD.scala:50:14] input io_pb_beat_corrupt, // @[SourceD.scala:50:14] input io_rel_pop_ready, // @[SourceD.scala:50:14] output io_rel_pop_valid, // @[SourceD.scala:50:14] output [5:0] io_rel_pop_bits_index, // @[SourceD.scala:50:14] output io_rel_pop_bits_last, // @[SourceD.scala:50:14] input [63:0] io_rel_beat_data, // @[SourceD.scala:50:14] input io_rel_beat_corrupt, // @[SourceD.scala:50:14] input io_bs_radr_ready, // @[SourceD.scala:50:14] output io_bs_radr_valid, // @[SourceD.scala:50:14] output [2:0] io_bs_radr_bits_way, // @[SourceD.scala:50:14] output [9:0] io_bs_radr_bits_set, // @[SourceD.scala:50:14] output [2:0] io_bs_radr_bits_beat, // @[SourceD.scala:50:14] output io_bs_radr_bits_mask, // @[SourceD.scala:50:14] input [63:0] io_bs_rdat_data, // @[SourceD.scala:50:14] input io_bs_wadr_ready, // @[SourceD.scala:50:14] output io_bs_wadr_valid, // @[SourceD.scala:50:14] output [2:0] io_bs_wadr_bits_way, // @[SourceD.scala:50:14] output [9:0] io_bs_wadr_bits_set, // @[SourceD.scala:50:14] output [2:0] io_bs_wadr_bits_beat, // @[SourceD.scala:50:14] output io_bs_wadr_bits_mask, // @[SourceD.scala:50:14] output [63:0] io_bs_wdat_data, // @[SourceD.scala:50:14] input [9:0] io_evict_req_set, // @[SourceD.scala:50:14] input [2:0] io_evict_req_way, // @[SourceD.scala:50:14] output io_evict_safe, // @[SourceD.scala:50:14] input [9:0] io_grant_req_set, // @[SourceD.scala:50:14] input [2:0] io_grant_req_way, // @[SourceD.scala:50:14] output io_grant_safe // @[SourceD.scala:50:14] ); wire [63:0] _atomics_io_data_out; // @[SourceD.scala:258:23] wire _queue_io_enq_ready; // @[SourceD.scala:120:21] wire _queue_io_deq_valid; // @[SourceD.scala:120:21] wire io_req_valid_0 = io_req_valid; // @[SourceD.scala:48:7] wire io_req_bits_prio_0_0 = io_req_bits_prio_0; // @[SourceD.scala:48:7] wire io_req_bits_prio_1_0 = io_req_bits_prio_1; // @[SourceD.scala:48:7] wire io_req_bits_prio_2_0 = io_req_bits_prio_2; // @[SourceD.scala:48:7] wire io_req_bits_control_0 = io_req_bits_control; // @[SourceD.scala:48:7] wire [2:0] io_req_bits_opcode_0 = io_req_bits_opcode; // @[SourceD.scala:48:7] wire [2:0] io_req_bits_param_0 = io_req_bits_param; // @[SourceD.scala:48:7] wire [2:0] io_req_bits_size_0 = io_req_bits_size; // @[SourceD.scala:48:7] wire [4:0] io_req_bits_source_0 = io_req_bits_source; // @[SourceD.scala:48:7] wire [11:0] io_req_bits_tag_0 = io_req_bits_tag; // @[SourceD.scala:48:7] wire [5:0] io_req_bits_offset_0 = io_req_bits_offset; // @[SourceD.scala:48:7] wire [5:0] io_req_bits_put_0 = io_req_bits_put; // @[SourceD.scala:48:7] wire [9:0] io_req_bits_set_0 = io_req_bits_set; // @[SourceD.scala:48:7] wire [2:0] io_req_bits_sink_0 = io_req_bits_sink; // @[SourceD.scala:48:7] wire [2:0] io_req_bits_way_0 = io_req_bits_way; // @[SourceD.scala:48:7] wire io_req_bits_bad_0 = io_req_bits_bad; // @[SourceD.scala:48:7] wire io_d_ready_0 = io_d_ready; // @[SourceD.scala:48:7] wire io_pb_pop_ready_0 = io_pb_pop_ready; // @[SourceD.scala:48:7] wire [63:0] io_pb_beat_data_0 = io_pb_beat_data; // @[SourceD.scala:48:7] wire [7:0] io_pb_beat_mask_0 = io_pb_beat_mask; // @[SourceD.scala:48:7] wire io_pb_beat_corrupt_0 = io_pb_beat_corrupt; // @[SourceD.scala:48:7] wire io_rel_pop_ready_0 = io_rel_pop_ready; // @[SourceD.scala:48:7] wire [63:0] io_rel_beat_data_0 = io_rel_beat_data; // @[SourceD.scala:48:7] wire io_rel_beat_corrupt_0 = io_rel_beat_corrupt; // @[SourceD.scala:48:7] wire io_bs_radr_ready_0 = io_bs_radr_ready; // @[SourceD.scala:48:7] wire [63:0] io_bs_rdat_data_0 = io_bs_rdat_data; // @[SourceD.scala:48:7] wire io_bs_wadr_ready_0 = io_bs_wadr_ready; // @[SourceD.scala:48:7] wire [9:0] io_evict_req_set_0 = io_evict_req_set; // @[SourceD.scala:48:7] wire [2:0] io_evict_req_way_0 = io_evict_req_way; // @[SourceD.scala:48:7] wire [9:0] io_grant_req_set_0 = io_grant_req_set; // @[SourceD.scala:48:7] wire [2:0] io_grant_req_way_0 = io_grant_req_way; // @[SourceD.scala:48:7] wire io_bs_radr_bits_noop = 1'h0; // @[SourceD.scala:48:7] wire io_bs_wadr_bits_noop = 1'h0; // @[SourceD.scala:48:7] wire [3:0] s1_mask_sizeOH = 4'hF; // @[Misc.scala:202:81] wire [3:0] pre_s3_4_bypass_sizeOH = 4'hF; // @[Misc.scala:202:81] wire [3:0] pre_s3_5_bypass_sizeOH = 4'hF; // @[Misc.scala:202:81] wire [3:0] pre_s3_6_bypass_sizeOH = 4'hF; // @[Misc.scala:202:81] wire [3:0] s1_2_bypass_sizeOH = 4'hF; // @[Misc.scala:202:81] wire [3:0] s1_3_bypass_sizeOH = 4'hF; // @[Misc.scala:202:81] wire [3:0] s1_4_bypass_sizeOH = 4'hF; // @[Misc.scala:202:81] wire [2:0] resp_opcode_0 = 3'h0; // @[SourceD.scala:215:28] wire [2:0] resp_opcode_1 = 3'h0; // @[SourceD.scala:215:28] wire [2:0] resp_opcode_7 = 3'h4; // @[SourceD.scala:215:28] wire [2:0] resp_opcode_5 = 3'h2; // @[SourceD.scala:215:28] wire [2:0] resp_opcode_2 = 3'h1; // @[SourceD.scala:215:28] wire [2:0] resp_opcode_3 = 3'h1; // @[SourceD.scala:215:28] wire [2:0] resp_opcode_4 = 3'h1; // @[SourceD.scala:215:28] wire [7:0] _s2_pdata_raw_mask_T = 8'hFF; // @[SourceD.scala:161:64] wire _io_req_ready_T; // @[SourceD.scala:140:19] wire d_ready = io_d_ready_0; // @[SourceD.scala:48:7, :218:15] wire d_valid; // @[SourceD.scala:218:15] wire [2:0] d_bits_opcode; // @[SourceD.scala:218:15] wire [1:0] d_bits_param; // @[SourceD.scala:218:15] wire [2:0] d_bits_size; // @[SourceD.scala:218:15] wire [4:0] d_bits_source; // @[SourceD.scala:218:15] wire [2:0] d_bits_sink; // @[SourceD.scala:218:15] wire d_bits_denied; // @[SourceD.scala:218:15] wire [63:0] d_bits_data; // @[SourceD.scala:218:15] wire d_bits_corrupt; // @[SourceD.scala:218:15] wire _io_pb_pop_valid_T; // @[SourceD.scala:164:34] wire _io_rel_pop_valid_T_1; // @[SourceD.scala:167:35] wire s1_valid_r; // @[SourceD.scala:96:56] wire [2:0] s1_req_way; // @[SourceD.scala:88:19] wire [9:0] s1_req_set; // @[SourceD.scala:88:19] wire [2:0] s1_beat; // @[SourceD.scala:102:56] wire s1_mask; // @[SourceD.scala:92:76] wire _io_bs_wadr_valid_T; // @[SourceD.scala:270:31] wire _io_bs_wadr_bits_mask_T_14; // @[SourceD.scala:275:87] wire _io_evict_safe_T_22; // @[SourceD.scala:378:90] wire _io_grant_safe_T_22; // @[SourceD.scala:385:90] wire io_req_ready_0; // @[SourceD.scala:48:7] wire [2:0] io_d_bits_opcode_0; // @[SourceD.scala:48:7] wire [1:0] io_d_bits_param_0; // @[SourceD.scala:48:7] wire [2:0] io_d_bits_size_0; // @[SourceD.scala:48:7] wire [4:0] io_d_bits_source_0; // @[SourceD.scala:48:7] wire [2:0] io_d_bits_sink_0; // @[SourceD.scala:48:7] wire io_d_bits_denied_0; // @[SourceD.scala:48:7] wire [63:0] io_d_bits_data_0; // @[SourceD.scala:48:7] wire io_d_bits_corrupt_0; // @[SourceD.scala:48:7] wire io_d_valid_0; // @[SourceD.scala:48:7] wire [5:0] io_pb_pop_bits_index_0; // @[SourceD.scala:48:7] wire io_pb_pop_bits_last_0; // @[SourceD.scala:48:7] wire io_pb_pop_valid_0; // @[SourceD.scala:48:7] wire [5:0] io_rel_pop_bits_index_0; // @[SourceD.scala:48:7] wire io_rel_pop_bits_last_0; // @[SourceD.scala:48:7] wire io_rel_pop_valid_0; // @[SourceD.scala:48:7] wire [2:0] io_bs_radr_bits_way_0; // @[SourceD.scala:48:7] wire [9:0] io_bs_radr_bits_set_0; // @[SourceD.scala:48:7] wire [2:0] io_bs_radr_bits_beat_0; // @[SourceD.scala:48:7] wire io_bs_radr_bits_mask_0; // @[SourceD.scala:48:7] wire io_bs_radr_valid_0; // @[SourceD.scala:48:7] wire [2:0] io_bs_wadr_bits_way_0; // @[SourceD.scala:48:7] wire [9:0] io_bs_wadr_bits_set_0; // @[SourceD.scala:48:7] wire [2:0] io_bs_wadr_bits_beat_0; // @[SourceD.scala:48:7] wire io_bs_wadr_bits_mask_0; // @[SourceD.scala:48:7] wire io_bs_wadr_valid_0; // @[SourceD.scala:48:7] wire [63:0] io_bs_wdat_data_0; // @[SourceD.scala:48:7] wire io_evict_safe_0; // @[SourceD.scala:48:7] wire io_grant_safe_0; // @[SourceD.scala:48:7] wire _s1_valid_T_3; // @[SourceD.scala:141:38] wire s1_valid; // @[SourceD.scala:74:22] wire _s2_valid_T_2; // @[SourceD.scala:183:23] wire s2_valid; // @[SourceD.scala:75:22] wire _s3_valid_T_2; // @[SourceD.scala:241:23] wire s3_valid; // @[SourceD.scala:76:22] wire _s2_ready_T_4; // @[SourceD.scala:184:24] wire s2_ready; // @[SourceD.scala:77:22] wire _s3_ready_T_4; // @[SourceD.scala:242:24] wire s3_ready; // @[SourceD.scala:78:22] wire _s4_ready_T_5; // @[SourceD.scala:293:59] wire s4_ready; // @[SourceD.scala:79:22] reg busy; // @[SourceD.scala:84:21] reg s1_block_r; // @[SourceD.scala:85:27] reg [2:0] s1_counter; // @[SourceD.scala:86:27] wire _s1_req_reg_T = ~busy; // @[SourceD.scala:84:21, :87:43] wire _s1_req_reg_T_1 = _s1_req_reg_T & io_req_valid_0; // @[SourceD.scala:48:7, :87:{43,49}] reg s1_req_reg_prio_0; // @[SourceD.scala:87:29] reg s1_req_reg_prio_1; // @[SourceD.scala:87:29] reg s1_req_reg_prio_2; // @[SourceD.scala:87:29] reg s1_req_reg_control; // @[SourceD.scala:87:29] reg [2:0] s1_req_reg_opcode; // @[SourceD.scala:87:29] reg [2:0] s1_req_reg_param; // @[SourceD.scala:87:29] reg [2:0] s1_req_reg_size; // @[SourceD.scala:87:29] reg [4:0] s1_req_reg_source; // @[SourceD.scala:87:29] reg [11:0] s1_req_reg_tag; // @[SourceD.scala:87:29] reg [5:0] s1_req_reg_offset; // @[SourceD.scala:87:29] reg [5:0] s1_req_reg_put; // @[SourceD.scala:87:29] reg [9:0] s1_req_reg_set; // @[SourceD.scala:87:29] reg [2:0] s1_req_reg_sink; // @[SourceD.scala:87:29] reg [2:0] s1_req_reg_way; // @[SourceD.scala:87:29] reg s1_req_reg_bad; // @[SourceD.scala:87:29] wire _s1_req_T = ~busy; // @[SourceD.scala:84:21, :87:43, :88:20] wire s1_req_prio_0 = _s1_req_T ? io_req_bits_prio_0_0 : s1_req_reg_prio_0; // @[SourceD.scala:48:7, :87:29, :88:{19,20}] wire s1_req_prio_1 = _s1_req_T ? io_req_bits_prio_1_0 : s1_req_reg_prio_1; // @[SourceD.scala:48:7, :87:29, :88:{19,20}] wire s1_req_prio_2 = _s1_req_T ? io_req_bits_prio_2_0 : s1_req_reg_prio_2; // @[SourceD.scala:48:7, :87:29, :88:{19,20}] wire s1_req_control = _s1_req_T ? io_req_bits_control_0 : s1_req_reg_control; // @[SourceD.scala:48:7, :87:29, :88:{19,20}] wire [2:0] s1_req_opcode = _s1_req_T ? io_req_bits_opcode_0 : s1_req_reg_opcode; // @[SourceD.scala:48:7, :87:29, :88:{19,20}] wire [2:0] s1_req_param = _s1_req_T ? io_req_bits_param_0 : s1_req_reg_param; // @[SourceD.scala:48:7, :87:29, :88:{19,20}] wire [2:0] s1_req_size = _s1_req_T ? io_req_bits_size_0 : s1_req_reg_size; // @[SourceD.scala:48:7, :87:29, :88:{19,20}] wire [4:0] s1_req_source = _s1_req_T ? io_req_bits_source_0 : s1_req_reg_source; // @[SourceD.scala:48:7, :87:29, :88:{19,20}] wire [11:0] s1_req_tag = _s1_req_T ? io_req_bits_tag_0 : s1_req_reg_tag; // @[SourceD.scala:48:7, :87:29, :88:{19,20}] wire [5:0] s1_req_offset = _s1_req_T ? io_req_bits_offset_0 : s1_req_reg_offset; // @[SourceD.scala:48:7, :87:29, :88:{19,20}] wire [5:0] s1_req_put = _s1_req_T ? io_req_bits_put_0 : s1_req_reg_put; // @[SourceD.scala:48:7, :87:29, :88:{19,20}] assign s1_req_set = _s1_req_T ? io_req_bits_set_0 : s1_req_reg_set; // @[SourceD.scala:48:7, :87:29, :88:{19,20}] wire [2:0] s1_req_sink = _s1_req_T ? io_req_bits_sink_0 : s1_req_reg_sink; // @[SourceD.scala:48:7, :87:29, :88:{19,20}] assign s1_req_way = _s1_req_T ? io_req_bits_way_0 : s1_req_reg_way; // @[SourceD.scala:48:7, :87:29, :88:{19,20}] wire s1_req_bad = _s1_req_T ? io_req_bits_bad_0 : s1_req_reg_bad; // @[SourceD.scala:48:7, :87:29, :88:{19,20}] wire [2:0] _s1_mask_sizeOH_T = s1_req_size; // @[Misc.scala:202:34] assign io_bs_radr_bits_set_0 = s1_req_set; // @[SourceD.scala:48:7, :88:19] assign io_bs_radr_bits_way_0 = s1_req_way; // @[SourceD.scala:48:7, :88:19] wire _s1_x_bypass_T_1; // @[SourceD.scala:360:44] wire s1_x_bypass; // @[SourceD.scala:89:25] wire _T_1 = busy | io_req_valid_0; // @[SourceD.scala:48:7, :84:21, :90:40] wire _s1_latch_bypass_T; // @[SourceD.scala:90:40] assign _s1_latch_bypass_T = _T_1; // @[SourceD.scala:90:40] wire _s1_valid_r_T; // @[SourceD.scala:96:26] assign _s1_valid_r_T = _T_1; // @[SourceD.scala:90:40, :96:26] wire _s1_valid_T; // @[SourceD.scala:141:21] assign _s1_valid_T = _T_1; // @[SourceD.scala:90:40, :141:21] wire _s1_latch_bypass_T_1 = ~_s1_latch_bypass_T; // @[SourceD.scala:90:{33,40}] wire _s1_latch_bypass_T_2 = _s1_latch_bypass_T_1 | s2_ready; // @[SourceD.scala:77:22, :90:{33,57}] reg s1_latch_bypass; // @[SourceD.scala:90:32] reg s1_bypass_r; // @[SourceD.scala:91:62] wire s1_bypass = s1_latch_bypass ? s1_x_bypass : s1_bypass_r; // @[SourceD.scala:89:25, :90:32, :91:{22,62}] wire [1:0] s1_mask_sizeOH_shiftAmount = _s1_mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _s1_mask_sizeOH_T_1 = 4'h1 << s1_mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _s1_mask_sizeOH_T_2 = _s1_mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire _s1_mask_T = ~s1_bypass; // @[SourceD.scala:91:22, :92:78] assign s1_mask = _s1_mask_T; // @[SourceD.scala:92:{76,78}] assign io_bs_radr_bits_mask_0 = s1_mask; // @[SourceD.scala:48:7, :92:76] wire _s1_need_r_T = s1_mask; // @[SourceD.scala:92:76, :94:27] wire _GEN = s1_req_opcode == 3'h6; // @[SourceD.scala:88:19, :93:33] wire _s1_grant_T; // @[SourceD.scala:93:33] assign _s1_grant_T = _GEN; // @[SourceD.scala:93:33] wire _s1_single_T_2; // @[SourceD.scala:98:89] assign _s1_single_T_2 = _GEN; // @[SourceD.scala:93:33, :98:89] wire _s1_grant_T_1 = s1_req_param == 3'h2; // @[SourceD.scala:88:19, :93:66] wire _s1_grant_T_2 = _s1_grant_T & _s1_grant_T_1; // @[SourceD.scala:93:{33,50,66}] wire _s1_grant_T_3 = &s1_req_opcode; // @[SourceD.scala:88:19, :93:93] wire s1_grant = _s1_grant_T_2 | _s1_grant_T_3; // @[SourceD.scala:93:{50,76,93}] wire _s1_need_r_T_1 = _s1_need_r_T & s1_req_prio_0; // @[SourceD.scala:88:19, :94:{27,31}] wire _s1_need_r_T_2 = s1_req_opcode != 3'h5; // @[SourceD.scala:88:19, :94:66] wire _s1_need_r_T_3 = _s1_need_r_T_1 & _s1_need_r_T_2; // @[SourceD.scala:94:{31,49,66}] wire _s1_need_r_T_4 = ~s1_grant; // @[SourceD.scala:93:76, :94:78] wire _s1_need_r_T_5 = _s1_need_r_T_3 & _s1_need_r_T_4; // @[SourceD.scala:94:{49,75,78}] wire _s1_need_r_T_6 = |s1_req_opcode; // @[SourceD.scala:88:19, :95:34] wire _s1_need_r_T_7 = s1_req_size < 3'h3; // @[SourceD.scala:88:19, :95:65] wire _s1_need_r_T_8 = _s1_need_r_T_6 | _s1_need_r_T_7; // @[SourceD.scala:95:{34,50,65}] wire s1_need_r = _s1_need_r_T_5 & _s1_need_r_T_8; // @[SourceD.scala:94:{75,88}, :95:50] wire _s1_valid_r_T_1 = _s1_valid_r_T & s1_need_r; // @[SourceD.scala:94:88, :96:{26,43}] wire _s1_valid_r_T_2 = ~s1_block_r; // @[SourceD.scala:85:27, :96:59] assign s1_valid_r = _s1_valid_r_T_1 & _s1_valid_r_T_2; // @[SourceD.scala:96:{43,56,59}] assign io_bs_radr_valid_0 = s1_valid_r; // @[SourceD.scala:48:7, :96:56] wire _s1_need_pb_T = s1_req_opcode[2]; // @[SourceD.scala:88:19, :97:54] wire _s1_need_pb_T_1 = ~_s1_need_pb_T; // @[SourceD.scala:97:{40,54}] wire _s1_need_pb_T_2 = s1_req_opcode[0]; // @[SourceD.scala:88:19, :97:72] wire s1_need_pb = s1_req_prio_0 ? _s1_need_pb_T_1 : _s1_need_pb_T_2; // @[SourceD.scala:88:19, :97:{23,40,72}] wire _s1_single_T = s1_req_opcode == 3'h5; // @[SourceD.scala:88:19, :98:53] wire _s1_single_T_1 = _s1_single_T | s1_grant; // @[SourceD.scala:93:76, :98:{53,62}] wire s1_single = s1_req_prio_0 ? _s1_single_T_1 : _s1_single_T_2; // @[SourceD.scala:88:19, :98:{22,62,89}] wire s1_retires = ~s1_single; // @[SourceD.scala:98:22, :99:20] wire [12:0] _s1_beats1_T = 13'h3F << s1_req_size; // @[package.scala:243:71] wire [5:0] _s1_beats1_T_1 = _s1_beats1_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _s1_beats1_T_2 = ~_s1_beats1_T_1; // @[package.scala:243:{46,76}] wire [2:0] _s1_beats1_T_3 = _s1_beats1_T_2[5:3]; // @[package.scala:243:46] wire [2:0] s1_beats1 = s1_single ? 3'h0 : _s1_beats1_T_3; // @[SourceD.scala:98:22, :101:{22,95}] wire [2:0] _s1_beat_T = s1_req_offset[5:3]; // @[SourceD.scala:88:19, :102:32] assign s1_beat = _s1_beat_T | s1_counter; // @[SourceD.scala:86:27, :102:{32,56}] assign io_bs_radr_bits_beat_0 = s1_beat; // @[SourceD.scala:48:7, :102:56] wire s1_last = s1_counter == s1_beats1; // @[SourceD.scala:86:27, :101:22, :103:28] wire s1_first = s1_counter == 3'h0; // @[SourceD.scala:86:27, :104:29] wire _queue_io_enq_valid_T = io_bs_radr_ready_0 & io_bs_radr_valid_0; // @[Decoupled.scala:51:35] reg queue_io_enq_valid_REG; // @[SourceD.scala:121:40] reg queue_io_enq_valid_REG_1; // @[SourceD.scala:121:32] wire s2_latch = s1_valid & s2_ready; // @[SourceD.scala:74:22, :77:22, :129:18, :146:27] wire [3:0] _s1_counter_T = {1'h0, s1_counter} + 4'h1; // @[SourceD.scala:86:27, :130:30] wire [2:0] _s1_counter_T_1 = _s1_counter_T[2:0]; // @[SourceD.scala:130:30] assign _io_req_ready_T = ~busy; // @[SourceD.scala:84:21, :87:43, :140:19] assign io_req_ready_0 = _io_req_ready_T; // @[SourceD.scala:48:7, :140:19] wire _s1_valid_T_1 = ~s1_valid_r; // @[SourceD.scala:96:56, :141:42] wire _s1_valid_T_2 = _s1_valid_T_1 | io_bs_radr_ready_0; // @[SourceD.scala:48:7, :141:{42,54}] assign _s1_valid_T_3 = _s1_valid_T & _s1_valid_T_2; // @[SourceD.scala:141:{21,38,54}] assign s1_valid = _s1_valid_T_3; // @[SourceD.scala:74:22, :141:38] reg s2_full; // @[SourceD.scala:147:24] reg s2_valid_pb; // @[SourceD.scala:148:28] reg [2:0] s2_beat; // @[SourceD.scala:149:26] reg s2_bypass; // @[SourceD.scala:150:28] reg s2_req_prio_0; // @[SourceD.scala:151:25] reg s2_req_prio_1; // @[SourceD.scala:151:25] reg s2_req_prio_2; // @[SourceD.scala:151:25] reg s2_req_control; // @[SourceD.scala:151:25] reg [2:0] s2_req_opcode; // @[SourceD.scala:151:25] reg [2:0] s2_req_param; // @[SourceD.scala:151:25] reg [2:0] s2_req_size; // @[SourceD.scala:151:25] wire [2:0] _s1_2_bypass_sizeOH_T = s2_req_size; // @[Misc.scala:202:34] reg [4:0] s2_req_source; // @[SourceD.scala:151:25] reg [11:0] s2_req_tag; // @[SourceD.scala:151:25] reg [5:0] s2_req_offset; // @[SourceD.scala:151:25] reg [5:0] s2_req_put; // @[SourceD.scala:151:25] assign io_pb_pop_bits_index_0 = s2_req_put; // @[SourceD.scala:48:7, :151:25] assign io_rel_pop_bits_index_0 = s2_req_put; // @[SourceD.scala:48:7, :151:25] reg [9:0] s2_req_set; // @[SourceD.scala:151:25] reg [2:0] s2_req_sink; // @[SourceD.scala:151:25] reg [2:0] s2_req_way; // @[SourceD.scala:151:25] reg s2_req_bad; // @[SourceD.scala:151:25] reg s2_last; // @[SourceD.scala:152:26] assign io_pb_pop_bits_last_0 = s2_last; // @[SourceD.scala:48:7, :152:26] assign io_rel_pop_bits_last_0 = s2_last; // @[SourceD.scala:48:7, :152:26] reg s2_need_r; // @[SourceD.scala:153:28] reg s2_need_pb; // @[SourceD.scala:154:29] reg s2_retires; // @[SourceD.scala:155:29] wire _s2_need_d_T = ~s1_need_pb; // @[SourceD.scala:97:23, :156:29] wire _s2_need_d_T_1 = _s2_need_d_T | s1_first; // @[SourceD.scala:104:29, :156:{29,41}] reg s2_need_d; // @[SourceD.scala:156:28] wire [63:0] _s2_pdata_raw_data_T; // @[SourceD.scala:160:30] wire [7:0] _s2_pdata_raw_mask_T_1; // @[SourceD.scala:161:30] wire _s2_pdata_raw_corrupt_T; // @[SourceD.scala:162:30] wire [63:0] s2_pdata_raw_data; // @[SourceD.scala:157:26] wire [7:0] s2_pdata_raw_mask; // @[SourceD.scala:157:26] wire s2_pdata_raw_corrupt; // @[SourceD.scala:157:26] reg [63:0] s2_pdata_r_data; // @[package.scala:88:63] reg [7:0] s2_pdata_r_mask; // @[package.scala:88:63] reg s2_pdata_r_corrupt; // @[package.scala:88:63] wire [63:0] s2_pdata_data = s2_valid_pb ? s2_pdata_raw_data : s2_pdata_r_data; // @[package.scala:88:{42,63}] wire [7:0] s2_pdata_mask = s2_valid_pb ? s2_pdata_raw_mask : s2_pdata_r_mask; // @[package.scala:88:{42,63}] wire s2_pdata_corrupt = s2_valid_pb ? s2_pdata_raw_corrupt : s2_pdata_r_corrupt; // @[package.scala:88:{42,63}] assign _s2_pdata_raw_data_T = s2_req_prio_0 ? io_pb_beat_data_0 : io_rel_beat_data_0; // @[SourceD.scala:48:7, :151:25, :160:30] assign s2_pdata_raw_data = _s2_pdata_raw_data_T; // @[SourceD.scala:157:26, :160:30] assign _s2_pdata_raw_mask_T_1 = s2_req_prio_0 ? io_pb_beat_mask_0 : 8'hFF; // @[SourceD.scala:48:7, :151:25, :161:30] assign s2_pdata_raw_mask = _s2_pdata_raw_mask_T_1; // @[SourceD.scala:157:26, :161:30] assign _s2_pdata_raw_corrupt_T = s2_req_prio_0 ? io_pb_beat_corrupt_0 : io_rel_beat_corrupt_0; // @[SourceD.scala:48:7, :151:25, :162:30] assign s2_pdata_raw_corrupt = _s2_pdata_raw_corrupt_T; // @[SourceD.scala:157:26, :162:30] assign _io_pb_pop_valid_T = s2_valid_pb & s2_req_prio_0; // @[SourceD.scala:148:28, :151:25, :164:34] assign io_pb_pop_valid_0 = _io_pb_pop_valid_T; // @[SourceD.scala:48:7, :164:34] wire _io_rel_pop_valid_T = ~s2_req_prio_0; // @[SourceD.scala:151:25, :167:38] assign _io_rel_pop_valid_T_1 = s2_valid_pb & _io_rel_pop_valid_T; // @[SourceD.scala:148:28, :167:{35,38}] assign io_rel_pop_valid_0 = _io_rel_pop_valid_T_1; // @[SourceD.scala:48:7, :167:35] wire pb_ready = s2_req_prio_0 ? io_pb_pop_ready_0 : io_rel_pop_ready_0; // @[SourceD.scala:48:7, :151:25, :175:21] wire s3_latch = s2_valid & s3_ready; // @[SourceD.scala:75:22, :78:22, :177:18, :189:27] wire _s2_valid_T = ~s2_valid_pb; // @[SourceD.scala:148:28, :183:27] wire _s2_valid_T_1 = _s2_valid_T | pb_ready; // @[SourceD.scala:175:21, :183:{27,40}] assign _s2_valid_T_2 = s2_full & _s2_valid_T_1; // @[SourceD.scala:147:24, :183:{23,40}] assign s2_valid = _s2_valid_T_2; // @[SourceD.scala:75:22, :183:23] wire _s2_ready_T = ~s2_full; // @[SourceD.scala:147:24, :184:15] wire _s2_ready_T_1 = ~s2_valid_pb; // @[SourceD.scala:148:28, :183:27, :184:41] wire _s2_ready_T_2 = _s2_ready_T_1 | pb_ready; // @[SourceD.scala:175:21, :184:{41,54}] wire _s2_ready_T_3 = s3_ready & _s2_ready_T_2; // @[SourceD.scala:78:22, :184:{37,54}] assign _s2_ready_T_4 = _s2_ready_T | _s2_ready_T_3; // @[SourceD.scala:184:{15,24,37}] assign s2_ready = _s2_ready_T_4; // @[SourceD.scala:77:22, :184:24] reg s3_full; // @[SourceD.scala:190:24] reg s3_valid_d; // @[SourceD.scala:191:27] assign d_valid = s3_valid_d; // @[SourceD.scala:191:27, :218:15] reg [2:0] s3_beat; // @[SourceD.scala:192:26] wire [2:0] pre_s3_beat = s3_latch ? s2_beat : s3_beat; // @[SourceD.scala:149:26, :189:27, :192:26, :319:24] reg s3_bypass; // @[SourceD.scala:193:28] wire _s3_rdata_T = s3_bypass; // @[SourceD.scala:193:28, :208:78] reg s3_req_prio_0; // @[SourceD.scala:194:25] reg s3_req_prio_1; // @[SourceD.scala:194:25] reg s3_req_prio_2; // @[SourceD.scala:194:25] reg s3_req_control; // @[SourceD.scala:194:25] reg [2:0] s3_req_opcode; // @[SourceD.scala:194:25] reg [2:0] s3_req_param; // @[SourceD.scala:194:25] reg [2:0] s3_req_size; // @[SourceD.scala:194:25] assign d_bits_size = s3_req_size; // @[SourceD.scala:194:25, :218:15] wire [2:0] _s1_3_bypass_sizeOH_T = s3_req_size; // @[Misc.scala:202:34] reg [4:0] s3_req_source; // @[SourceD.scala:194:25] assign d_bits_source = s3_req_source; // @[SourceD.scala:194:25, :218:15] reg [11:0] s3_req_tag; // @[SourceD.scala:194:25] reg [5:0] s3_req_offset; // @[SourceD.scala:194:25] reg [5:0] s3_req_put; // @[SourceD.scala:194:25] reg [9:0] s3_req_set; // @[SourceD.scala:194:25] reg [2:0] s3_req_sink; // @[SourceD.scala:194:25] assign d_bits_sink = s3_req_sink; // @[SourceD.scala:194:25, :218:15] reg [2:0] s3_req_way; // @[SourceD.scala:194:25] reg s3_req_bad; // @[SourceD.scala:194:25] assign d_bits_denied = s3_req_bad; // @[SourceD.scala:194:25, :218:15] wire pre_s3_req_prio_0 = s3_latch ? s2_req_prio_0 : s3_req_prio_0; // @[SourceD.scala:151:25, :189:27, :194:25, :315:24] wire pre_s3_req_prio_1 = s3_latch ? s2_req_prio_1 : s3_req_prio_1; // @[SourceD.scala:151:25, :189:27, :194:25, :315:24] wire pre_s3_req_prio_2 = s3_latch ? s2_req_prio_2 : s3_req_prio_2; // @[SourceD.scala:151:25, :189:27, :194:25, :315:24] wire pre_s3_req_control = s3_latch ? s2_req_control : s3_req_control; // @[SourceD.scala:151:25, :189:27, :194:25, :315:24] wire [2:0] pre_s3_req_opcode = s3_latch ? s2_req_opcode : s3_req_opcode; // @[SourceD.scala:151:25, :189:27, :194:25, :315:24] wire [2:0] pre_s3_req_param = s3_latch ? s2_req_param : s3_req_param; // @[SourceD.scala:151:25, :189:27, :194:25, :315:24] wire [2:0] pre_s3_req_size = s3_latch ? s2_req_size : s3_req_size; // @[SourceD.scala:151:25, :189:27, :194:25, :315:24] wire [4:0] pre_s3_req_source = s3_latch ? s2_req_source : s3_req_source; // @[SourceD.scala:151:25, :189:27, :194:25, :315:24] wire [11:0] pre_s3_req_tag = s3_latch ? s2_req_tag : s3_req_tag; // @[SourceD.scala:151:25, :189:27, :194:25, :315:24] wire [5:0] pre_s3_req_offset = s3_latch ? s2_req_offset : s3_req_offset; // @[SourceD.scala:151:25, :189:27, :194:25, :315:24] wire [5:0] pre_s3_req_put = s3_latch ? s2_req_put : s3_req_put; // @[SourceD.scala:151:25, :189:27, :194:25, :315:24] wire [9:0] pre_s3_req_set = s3_latch ? s2_req_set : s3_req_set; // @[SourceD.scala:151:25, :189:27, :194:25, :315:24] wire [2:0] pre_s3_req_sink = s3_latch ? s2_req_sink : s3_req_sink; // @[SourceD.scala:151:25, :189:27, :194:25, :315:24] wire [2:0] pre_s3_req_way = s3_latch ? s2_req_way : s3_req_way; // @[SourceD.scala:151:25, :189:27, :194:25, :315:24] wire pre_s3_req_bad = s3_latch ? s2_req_bad : s3_req_bad; // @[SourceD.scala:151:25, :189:27, :194:25, :315:24] wire [2:0] s3_adjusted_opcode = s3_req_bad ? 3'h4 : s3_req_opcode; // @[SourceD.scala:194:25, :195:31] reg s3_last; // @[SourceD.scala:196:26] reg [63:0] s3_pdata_data; // @[SourceD.scala:197:27] reg [7:0] s3_pdata_mask; // @[SourceD.scala:197:27] reg s3_pdata_corrupt; // @[SourceD.scala:197:27] reg s3_need_pb; // @[SourceD.scala:198:29] reg s3_retires; // @[SourceD.scala:199:29] reg s3_need_r; // @[SourceD.scala:200:28] wire _s3_acq_T = s3_req_opcode == 3'h6; // @[SourceD.scala:194:25, :202:30] wire _s3_acq_T_1 = &s3_req_opcode; // @[SourceD.scala:194:25, :202:64] wire s3_acq = _s3_acq_T | _s3_acq_T_1; // @[SourceD.scala:202:{30,47,64}] wire [63:0] _s3_bypass_data_T_11; // @[SourceD.scala:210:75] wire [63:0] s3_bypass_data; // @[SourceD.scala:206:28] wire [63:0] _s3_rdata_T_1 = s3_bypass_data; // @[SourceD.scala:206:28, :207:78] wire [63:0] _s3_rdata_T_2; // @[SourceD.scala:207:78] wire [63:0] s3_rdata = _s3_rdata_T ? _s3_rdata_T_1 : _s3_rdata_T_2; // @[SourceD.scala:207:78, :208:78, :210:75] assign d_bits_data = s3_rdata; // @[SourceD.scala:210:75, :218:15] wire _grant_T = s3_req_param == 3'h2; // @[SourceD.scala:194:25, :214:32] wire [2:0] grant = {2'h2, ~_grant_T}; // @[SourceD.scala:214:{18,32}] wire [2:0] resp_opcode_6 = grant; // @[SourceD.scala:214:18, :215:28] assign io_d_valid_0 = d_valid; // @[SourceD.scala:48:7, :218:15] wire [2:0] _d_bits_opcode_T; // @[SourceD.scala:222:24] assign io_d_bits_opcode_0 = d_bits_opcode; // @[SourceD.scala:48:7, :218:15] wire [1:0] _d_bits_param_T_3; // @[SourceD.scala:223:24] assign io_d_bits_param_0 = d_bits_param; // @[SourceD.scala:48:7, :218:15] assign io_d_bits_size_0 = d_bits_size; // @[SourceD.scala:48:7, :218:15] assign io_d_bits_source_0 = d_bits_source; // @[SourceD.scala:48:7, :218:15] assign io_d_bits_sink_0 = d_bits_sink; // @[SourceD.scala:48:7, :218:15] assign io_d_bits_denied_0 = d_bits_denied; // @[SourceD.scala:48:7, :218:15] assign io_d_bits_data_0 = d_bits_data; // @[SourceD.scala:48:7, :218:15] wire _d_bits_corrupt_T_1; // @[SourceD.scala:229:32] assign io_d_bits_corrupt_0 = d_bits_corrupt; // @[SourceD.scala:48:7, :218:15] wire [7:0][2:0] _GEN_0 = {{3'h4}, {resp_opcode_6}, {3'h2}, {3'h1}, {3'h1}, {3'h1}, {3'h0}, {3'h0}}; // @[SourceD.scala:215:28, :222:24] assign _d_bits_opcode_T = s3_req_prio_0 ? _GEN_0[s3_req_opcode] : 3'h6; // @[SourceD.scala:194:25, :222:24] assign d_bits_opcode = _d_bits_opcode_T; // @[SourceD.scala:218:15, :222:24] wire _d_bits_param_T = s3_req_prio_0 & s3_acq; // @[SourceD.scala:194:25, :202:47, :223:40] wire _d_bits_param_T_1 = |s3_req_param; // @[SourceD.scala:194:25, :223:68] wire [1:0] _d_bits_param_T_2 = {1'h0, ~_d_bits_param_T_1}; // @[SourceD.scala:223:{54,68}] assign _d_bits_param_T_3 = _d_bits_param_T ? _d_bits_param_T_2 : 2'h0; // @[SourceD.scala:223:{24,40,54}] assign d_bits_param = _d_bits_param_T_3; // @[SourceD.scala:218:15, :223:24] wire _d_bits_corrupt_T = d_bits_opcode[0]; // @[SourceD.scala:218:15, :229:48] assign _d_bits_corrupt_T_1 = s3_req_bad & _d_bits_corrupt_T; // @[SourceD.scala:194:25, :229:{32,48}] assign d_bits_corrupt = _d_bits_corrupt_T_1; // @[SourceD.scala:218:15, :229:32] wire _queue_io_deq_ready_T = s3_valid & s4_ready; // @[SourceD.scala:76:22, :79:22, :231:34] wire _queue_io_deq_ready_T_1 = _queue_io_deq_ready_T & s3_need_r; // @[SourceD.scala:200:28, :231:{34,46}] wire _s3_valid_T = ~s3_valid_d; // @[SourceD.scala:191:27, :241:27] wire _s3_valid_T_1 = _s3_valid_T | d_ready; // @[SourceD.scala:218:15, :241:{27,39}] assign _s3_valid_T_2 = s3_full & _s3_valid_T_1; // @[SourceD.scala:190:24, :241:{23,39}] assign s3_valid = _s3_valid_T_2; // @[SourceD.scala:76:22, :241:23] wire _s3_ready_T = ~s3_full; // @[SourceD.scala:190:24, :232:11, :242:15] wire _s3_ready_T_1 = ~s3_valid_d; // @[SourceD.scala:191:27, :241:27, :242:41] wire _s3_ready_T_2 = _s3_ready_T_1 | d_ready; // @[SourceD.scala:218:15, :242:{41,53}] wire _s3_ready_T_3 = s4_ready & _s3_ready_T_2; // @[SourceD.scala:79:22, :242:{37,53}] assign _s3_ready_T_4 = _s3_ready_T | _s3_ready_T_3; // @[SourceD.scala:242:{15,24,37}] assign s3_ready = _s3_ready_T_4; // @[SourceD.scala:78:22, :242:24] wire _s4_latch_T = s3_valid & s3_retires; // @[SourceD.scala:76:22, :199:29, :247:27] wire s4_latch = _s4_latch_T & s4_ready; // @[SourceD.scala:79:22, :247:{27,41}] reg s4_full; // @[SourceD.scala:248:24] reg [2:0] s4_beat; // @[SourceD.scala:249:26] assign io_bs_wadr_bits_beat_0 = s4_beat; // @[SourceD.scala:48:7, :249:26] wire [2:0] pre_s4_beat = s4_latch ? s3_beat : s4_beat; // @[SourceD.scala:192:26, :247:41, :249:26, :320:24] reg s4_need_r; // @[SourceD.scala:250:28] reg s4_need_bs; // @[SourceD.scala:251:29] reg s4_need_pb; // @[SourceD.scala:252:29] reg s4_req_prio_0; // @[SourceD.scala:253:25] reg s4_req_prio_1; // @[SourceD.scala:253:25] reg s4_req_prio_2; // @[SourceD.scala:253:25] reg s4_req_control; // @[SourceD.scala:253:25] reg [2:0] s4_req_opcode; // @[SourceD.scala:253:25] reg [2:0] s4_req_param; // @[SourceD.scala:253:25] reg [2:0] s4_req_size; // @[SourceD.scala:253:25] wire [2:0] _s1_4_bypass_sizeOH_T = s4_req_size; // @[Misc.scala:202:34] reg [4:0] s4_req_source; // @[SourceD.scala:253:25] reg [11:0] s4_req_tag; // @[SourceD.scala:253:25] reg [5:0] s4_req_offset; // @[SourceD.scala:253:25] reg [5:0] s4_req_put; // @[SourceD.scala:253:25] reg [9:0] s4_req_set; // @[SourceD.scala:253:25] assign io_bs_wadr_bits_set_0 = s4_req_set; // @[SourceD.scala:48:7, :253:25] reg [2:0] s4_req_sink; // @[SourceD.scala:253:25] reg [2:0] s4_req_way; // @[SourceD.scala:253:25] assign io_bs_wadr_bits_way_0 = s4_req_way; // @[SourceD.scala:48:7, :253:25] reg s4_req_bad; // @[SourceD.scala:253:25] wire pre_s4_req_prio_0 = s4_latch ? s3_req_prio_0 : s4_req_prio_0; // @[SourceD.scala:194:25, :247:41, :253:25, :316:24] wire pre_s4_req_prio_1 = s4_latch ? s3_req_prio_1 : s4_req_prio_1; // @[SourceD.scala:194:25, :247:41, :253:25, :316:24] wire pre_s4_req_prio_2 = s4_latch ? s3_req_prio_2 : s4_req_prio_2; // @[SourceD.scala:194:25, :247:41, :253:25, :316:24] wire pre_s4_req_control = s4_latch ? s3_req_control : s4_req_control; // @[SourceD.scala:194:25, :247:41, :253:25, :316:24] wire [2:0] pre_s4_req_opcode = s4_latch ? s3_req_opcode : s4_req_opcode; // @[SourceD.scala:194:25, :247:41, :253:25, :316:24] wire [2:0] pre_s4_req_param = s4_latch ? s3_req_param : s4_req_param; // @[SourceD.scala:194:25, :247:41, :253:25, :316:24] wire [2:0] pre_s4_req_size = s4_latch ? s3_req_size : s4_req_size; // @[SourceD.scala:194:25, :247:41, :253:25, :316:24] wire [4:0] pre_s4_req_source = s4_latch ? s3_req_source : s4_req_source; // @[SourceD.scala:194:25, :247:41, :253:25, :316:24] wire [11:0] pre_s4_req_tag = s4_latch ? s3_req_tag : s4_req_tag; // @[SourceD.scala:194:25, :247:41, :253:25, :316:24] wire [5:0] pre_s4_req_offset = s4_latch ? s3_req_offset : s4_req_offset; // @[SourceD.scala:194:25, :247:41, :253:25, :316:24] wire [5:0] pre_s4_req_put = s4_latch ? s3_req_put : s4_req_put; // @[SourceD.scala:194:25, :247:41, :253:25, :316:24] wire [9:0] pre_s4_req_set = s4_latch ? s3_req_set : s4_req_set; // @[SourceD.scala:194:25, :247:41, :253:25, :316:24] wire [2:0] pre_s4_req_sink = s4_latch ? s3_req_sink : s4_req_sink; // @[SourceD.scala:194:25, :247:41, :253:25, :316:24] wire [2:0] pre_s4_req_way = s4_latch ? s3_req_way : s4_req_way; // @[SourceD.scala:194:25, :247:41, :253:25, :316:24] wire pre_s4_req_bad = s4_latch ? s3_req_bad : s4_req_bad; // @[SourceD.scala:194:25, :247:41, :253:25, :316:24] reg [2:0] s4_adjusted_opcode; // @[SourceD.scala:254:37] reg [63:0] s4_pdata_data; // @[SourceD.scala:255:27] reg [7:0] s4_pdata_mask; // @[SourceD.scala:255:27] reg s4_pdata_corrupt; // @[SourceD.scala:255:27] reg [63:0] s4_rdata; // @[SourceD.scala:256:27] assign _io_bs_wadr_valid_T = s4_full & s4_need_bs; // @[SourceD.scala:248:24, :251:29, :270:31] assign io_bs_wadr_valid_0 = _io_bs_wadr_valid_T; // @[SourceD.scala:48:7, :270:31] wire _io_bs_wadr_bits_mask_T = s4_pdata_mask[0]; // @[SourceD.scala:255:27, :275:45] wire _io_bs_wadr_bits_mask_T_1 = s4_pdata_mask[1]; // @[SourceD.scala:255:27, :275:45] wire _io_bs_wadr_bits_mask_T_2 = s4_pdata_mask[2]; // @[SourceD.scala:255:27, :275:45] wire _io_bs_wadr_bits_mask_T_3 = s4_pdata_mask[3]; // @[SourceD.scala:255:27, :275:45] wire _io_bs_wadr_bits_mask_T_4 = s4_pdata_mask[4]; // @[SourceD.scala:255:27, :275:45] wire _io_bs_wadr_bits_mask_T_5 = s4_pdata_mask[5]; // @[SourceD.scala:255:27, :275:45] wire _io_bs_wadr_bits_mask_T_6 = s4_pdata_mask[6]; // @[SourceD.scala:255:27, :275:45] wire _io_bs_wadr_bits_mask_T_7 = s4_pdata_mask[7]; // @[SourceD.scala:255:27, :275:45] wire _io_bs_wadr_bits_mask_T_8 = _io_bs_wadr_bits_mask_T | _io_bs_wadr_bits_mask_T_1; // @[SourceD.scala:275:{45,87}] wire _io_bs_wadr_bits_mask_T_9 = _io_bs_wadr_bits_mask_T_8 | _io_bs_wadr_bits_mask_T_2; // @[SourceD.scala:275:{45,87}] wire _io_bs_wadr_bits_mask_T_10 = _io_bs_wadr_bits_mask_T_9 | _io_bs_wadr_bits_mask_T_3; // @[SourceD.scala:275:{45,87}] wire _io_bs_wadr_bits_mask_T_11 = _io_bs_wadr_bits_mask_T_10 | _io_bs_wadr_bits_mask_T_4; // @[SourceD.scala:275:{45,87}] wire _io_bs_wadr_bits_mask_T_12 = _io_bs_wadr_bits_mask_T_11 | _io_bs_wadr_bits_mask_T_5; // @[SourceD.scala:275:{45,87}] wire _io_bs_wadr_bits_mask_T_13 = _io_bs_wadr_bits_mask_T_12 | _io_bs_wadr_bits_mask_T_6; // @[SourceD.scala:275:{45,87}] assign _io_bs_wadr_bits_mask_T_14 = _io_bs_wadr_bits_mask_T_13 | _io_bs_wadr_bits_mask_T_7; // @[SourceD.scala:275:{45,87}] assign io_bs_wadr_bits_mask_0 = _io_bs_wadr_bits_mask_T_14; // @[SourceD.scala:48:7, :275:87]